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authorWaldemar Brodkorb <wbx@openadk.org>2015-08-01 10:41:19 +0200
committerWaldemar Brodkorb <wbx@openadk.org>2015-08-01 10:42:22 +0200
commit8904b7659a3fff94637af328dae415110b6f46d7 (patch)
treef8388766fa798f5f328c09a584dd9bf248afb990
parentce515b6da73e7b2cfbfb4de79b6c293b3257d47a (diff)
update to 4.1.3, which will be the base for stable branch
Diffstat
-rw-r--r--mk/kernel-ver.mk6
-rw-r--r--mk/modules-4.1.mk6
-rw-r--r--mk/modules.mk4
-rw-r--r--target/arm/bcm28xx/patches/4.1.3/0001-xbian.patch304485
-rw-r--r--target/arm/solidrun-imx6/patches/4.1.3/0001-xbian.patch171697
-rw-r--r--target/config/Config.in.kernelversion.choice5
-rw-r--r--target/config/Config.in.kernelversion.default2
-rw-r--r--target/linux/config/Config.in.audio6
-rw-r--r--target/linux/config/Config.in.cpu1
-rw-r--r--target/linux/config/Config.in.graphics1
-rw-r--r--target/linux/config/Config.in.pm29
11 files changed, 476221 insertions, 21 deletions
diff --git a/mk/kernel-ver.mk b/mk/kernel-ver.mk
index 7f59ff489..2b9a1de32 100644
--- a/mk/kernel-ver.mk
+++ b/mk/kernel-ver.mk
@@ -3,11 +3,11 @@ KERNEL_VERSION:= $(ADK_KERNEL_HASH)
KERNEL_MOD_VERSION:= $(KERNEL_VERSION)
KERNEL_RELEASE:= 1
endif
-ifeq ($(ADK_KERNEL_VERSION_4_1_2),y)
-KERNEL_VERSION:= 4.1.2
+ifeq ($(ADK_KERNEL_VERSION_4_1_3),y)
+KERNEL_VERSION:= 4.1.3
KERNEL_MOD_VERSION:= $(KERNEL_VERSION)
KERNEL_RELEASE:= 1
-KERNEL_HASH:= 1e4a46b8be904af336af2d556dbe01e01b21a6be15434517234540f82d94bed5
+KERNEL_HASH:= 96dd2c30984408a8a2211463618c3564514239f1e4335f6bc461c4b9a9bae30b
endif
ifeq ($(ADK_KERNEL_VERSION_4_0_6),y)
KERNEL_VERSION:= 4.0.6
diff --git a/mk/modules-4.1.mk b/mk/modules-4.1.mk
new file mode 100644
index 000000000..425c180ac
--- /dev/null
+++ b/mk/modules-4.1.mk
@@ -0,0 +1,6 @@
+# This file is part of the OpenADK project. OpenADK is copyrighted
+# material, please see the LICENCE file in the top-level directory.
+
+USBMODULES+=drivers/usb/common/usb-common
+USBMODULES+=drivers/usb/core/usbcore
+USBUDC:=gadget/udc
diff --git a/mk/modules.mk b/mk/modules.mk
index 55136e253..eed6144a4 100644
--- a/mk/modules.mk
+++ b/mk/modules.mk
@@ -1,6 +1,10 @@
# This file is part of the OpenADK project. OpenADK is copyrighted
# material, please see the LICENCE file in the top-level directory.
+ifeq ($(ADK_KERNEL_VERSION_4_1),y)
+include $(ADK_TOPDIR)/mk/modules-4.1.mk
+endif
+
ifeq ($(ADK_KERNEL_VERSION_4_0),y)
include $(ADK_TOPDIR)/mk/modules-4.0.mk
endif
diff --git a/target/arm/bcm28xx/patches/4.1.3/0001-xbian.patch b/target/arm/bcm28xx/patches/4.1.3/0001-xbian.patch
new file mode 100644
index 000000000..318706994
--- /dev/null
+++ b/target/arm/bcm28xx/patches/4.1.3/0001-xbian.patch
@@ -0,0 +1,304485 @@
+diff -Nur linux-4.1.3/arch/arm/boot/dts/bcm2708_common.dtsi linux-xbian-rpi/arch/arm/boot/dts/bcm2708_common.dtsi
+--- linux-4.1.3/arch/arm/boot/dts/bcm2708_common.dtsi 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/boot/dts/bcm2708_common.dtsi 2015-07-28 01:20:58.166151930 +0200
+@@ -0,0 +1,287 @@
++/include/ "skeleton.dtsi"
++
++/ {
++ interrupt-parent = <&intc>;
++
++ aliases {
++ audio = &audio;
++ sound = &sound;
++ soc = &soc;
++ dma = &dma;
++ intc = &intc;
++ watchdog = &watchdog;
++ random = &random;
++ mailbox = &mailbox;
++ gpio = &gpio;
++ uart0 = &uart0;
++ i2s = &i2s;
++ spi0 = &spi0;
++ i2c0 = &i2c0;
++ uart1 = &uart1;
++ mmc = &mmc;
++ i2c1 = &i2c1;
++ i2c2 = &i2c2;
++ usb = &usb;
++ leds = &leds;
++ fb = &fb;
++ vchiq = &vchiq;
++ thermal = &thermal;
++ clocks = &clocks;
++ };
++
++ /* Onboard audio */
++ audio: audio {
++ compatible = "brcm,bcm2835-audio";
++ brcm,pwm-channels = <8>;
++ status = "disabled";
++ };
++
++ /* External sound card */
++ sound: sound {
++ };
++
++ soc: soc {
++ compatible = "simple-bus";
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ dma: dma@7e007000 {
++ compatible = "brcm,bcm2835-dma";
++ reg = <0x7e007000 0xf00>;
++ interrupts = <1 16>,
++ <1 17>,
++ <1 18>,
++ <1 19>,
++ <1 20>,
++ <1 21>,
++ <1 22>,
++ <1 23>,
++ <1 24>,
++ <1 25>,
++ <1 26>,
++ <1 27>,
++ <1 28>;
++
++ #dma-cells = <1>;
++ brcm,dma-channel-mask = <0x7f35>;
++ };
++
++ intc: interrupt-controller {
++ compatible = "brcm,bcm2708-armctrl-ic";
++ reg = <0x7e00b200 0x200>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ };
++
++ mailbox: mailbox@7e00b800 {
++ compatible = "brcm,bcm2835-mbox";
++ reg = <0x7e00b880 0x40>;
++ interrupts = <0 1>;
++ #mbox-cells = <0>;
++ };
++
++ watchdog: watchdog@7e100000 {
++ compatible = "brcm,bcm2835-pm-wdt";
++ reg = <0x7e100000 0x28>;
++ status = "disabled";
++ };
++
++ random: rng@7e104000 {
++ compatible = "brcm,bcm2835-rng";
++ reg = <0x7e104000 0x10>;
++ status = "disabled";
++ };
++
++ gpio: gpio@7e200000 {
++ compatible = "brcm,bcm2835-gpio";
++ reg = <0x7e200000 0xb4>;
++ interrupts = <2 17>, <2 18>;
++
++ gpio-controller;
++ #gpio-cells = <2>;
++
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ };
++
++ uart0: uart@7e201000 {
++ compatible = "arm,pl011", "arm,primecell";
++ reg = <0x7e201000 0x1000>;
++ interrupts = <2 25>;
++ clocks = <&clk_uart0 &clk_apb_p>;
++ clock-names = "uartclk","apb_pclk";
++ arm,primecell-periphid = <0x00241011>; // For an explanation, see
++ // https://github.com/raspberrypi/linux/commit/13731d862cf5219216533a3b0de052cee4cc5038
++ status = "disabled";
++ };
++
++ i2s: i2s@7e203000 {
++ compatible = "brcm,bcm2708-i2s";
++ reg = <0x7e203000 0x24>,
++ <0x7e101098 0x08>;
++
++ //dmas = <&dma 2>,
++ // <&dma 3>;
++ dma-names = "tx", "rx";
++ status = "disabled";
++ };
++
++ spi0: spi@7e204000 {
++ compatible = "brcm,bcm2835-spi";
++ reg = <0x7e204000 0x1000>;
++ interrupts = <2 22>;
++ clocks = <&clk_core>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ /* the dma channels */
++ dmas = <&dma 6>, <&dma 7>;
++ dma-names = "tx", "rx";
++ /* the chipselects used - <0> means native GPIO
++ * add more gpios if necessary as <&gpio 6 1>
++ * (but do not forget to make them output!)
++ */
++ cs-gpios = <0>, <0>;
++ };
++
++ i2c0: i2c@7e205000 {
++ compatible = "brcm,bcm2708-i2c";
++ reg = <0x7e205000 0x1000>;
++ interrupts = <2 21>;
++ clocks = <&clk_i2c>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ };
++
++ uart1: uart@7e215040 {
++ compatible = "brcm,bcm2835-aux-uart", "ns16550";
++ reg = <0x7e215040 0x40>;
++ interrupts = <1 29>;
++ clock-frequency = <500000000>;
++ reg-shift = <2>;
++ no-loopback-test;
++ status = "disabled";
++ };
++
++ mmc: mmc@7e300000 {
++ compatible = "brcm,bcm2835-mmc";
++ reg = <0x7e300000 0x100>;
++ interrupts = <2 30>;
++ clocks = <&clk_mmc>;
++ dmas = <&dma 11>,
++ <&dma 11>;
++ dma-names = "tx", "rx";
++ status = "disabled";
++ };
++
++ i2c1: i2c@7e804000 {
++ compatible = "brcm,bcm2708-i2c";
++ reg = <0x7e804000 0x1000>;
++ interrupts = <2 21>;
++ clocks = <&clk_i2c>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ };
++
++ i2c2: i2c@7e805000 {
++ // Beware - this is shared with the HDMI module.
++ // Careless use may break (really) your display.
++ // Caveat emptor.
++ compatible = "brcm,bcm2708-i2c";
++ reg = <0x7e805000 0x1000>;
++ interrupts = <2 21>;
++ clocks = <&clk_i2c>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ };
++
++ usb: usb@7e980000 {
++ compatible = "brcm,bcm2708-usb";
++ reg = <0x7e980000 0x10000>,
++ <0x7e006000 0x1000>;
++ interrupts = <2 0>,
++ <1 9>;
++ };
++
++ firmware: firmware {
++ compatible = "raspberrypi,bcm2835-firmware";
++ mboxes = <&mailbox>;
++ };
++
++ leds: leds {
++ compatible = "gpio-leds";
++ };
++
++ fb: fb {
++ compatible = "brcm,bcm2708-fb";
++ firmware = <&firmware>;
++ status = "disabled";
++ };
++
++ vchiq: vchiq {
++ compatible = "brcm,bcm2835-vchiq";
++ reg = <0x7e00b840 0xf>;
++ interrupts = <0 2>;
++ cache-line-size = <32>;
++ firmware = <&firmware>;
++ };
++
++ thermal: thermal {
++ compatible = "brcm,bcm2835-thermal";
++ firmware = <&firmware>;
++ };
++ };
++
++ clocks: clocks {
++ compatible = "simple-bus";
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ clk_mmc: clock@0 {
++ compatible = "fixed-clock";
++ reg = <0>;
++ #clock-cells = <0>;
++ clock-output-names = "mmc";
++ clock-frequency = <250000000>;
++ };
++
++ clk_i2c: clock@1 {
++ compatible = "fixed-clock";
++ reg = <1>;
++ #clock-cells = <0>;
++ clock-output-names = "i2c";
++ clock-frequency = <250000000>;
++ };
++
++ clk_core: clock@2 {
++ compatible = "fixed-clock";
++ reg = <2>;
++ #clock-cells = <0>;
++ clock-output-names = "core";
++ clock-frequency = <250000000>;
++ };
++
++ clk_uart0: clock@3 {
++ compatible = "fixed-clock";
++ reg = <3>;
++ #clock-cells = <0>;
++ clock-output-names = "uart0_pclk";
++ clock-frequency = <3000000>;
++ };
++
++ clk_apb_p: clock@4 {
++ compatible = "fixed-clock";
++ reg = <4>;
++ #clock-cells = <0>;
++ clock-output-names = "apb_pclk";
++ clock-frequency = <126000000>;
++ };
++ };
++
++ __overrides__ {
++ cache_line_size = <&vchiq>, "cache-line-size:0";
++ };
++};
+diff -Nur linux-4.1.3/arch/arm/boot/dts/bcm2708.dtsi linux-xbian-rpi/arch/arm/boot/dts/bcm2708.dtsi
+--- linux-4.1.3/arch/arm/boot/dts/bcm2708.dtsi 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/boot/dts/bcm2708.dtsi 2015-07-28 01:20:58.166151930 +0200
+@@ -0,0 +1,19 @@
++/include/ "bcm2708_common.dtsi"
++
++/ {
++ compatible = "brcm,bcm2708";
++ model = "BCM2708";
++
++ chosen {
++ /* No padding required - the boot loader can do that. */
++ bootargs = "";
++ };
++
++ soc {
++ ranges = <0x7e000000 0x20000000 0x01000000>;
++
++ arm-pmu {
++ compatible = "arm,arm1176-pmu";
++ };
++ };
++};
+diff -Nur linux-4.1.3/arch/arm/boot/dts/bcm2708-rpi-b.dts linux-xbian-rpi/arch/arm/boot/dts/bcm2708-rpi-b.dts
+--- linux-4.1.3/arch/arm/boot/dts/bcm2708-rpi-b.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/boot/dts/bcm2708-rpi-b.dts 2015-07-28 01:20:58.166151930 +0200
+@@ -0,0 +1,119 @@
++/dts-v1/;
++
++/include/ "bcm2708.dtsi"
++
++/ {
++ compatible = "brcm,bcm2708";
++ model = "Raspberry Pi Model B";
++};
++
++&gpio {
++ spi0_pins: spi0_pins {
++ brcm,pins = <7 8 9 10 11>;
++ brcm,function = <4>; /* alt0 */
++ };
++
++ i2c0_pins: i2c0 {
++ brcm,pins = <0 1>;
++ brcm,function = <4>;
++ };
++
++ i2c1_pins: i2c1 {
++ brcm,pins = <2 3>;
++ brcm,function = <4>;
++ };
++
++ i2s_pins: i2s {
++ brcm,pins = <28 29 30 31>;
++ brcm,function = <6>; /* alt2 */
++ };
++};
++
++&mmc {
++ status = "okay";
++ bus-width = <4>;
++};
++
++&fb {
++ status = "okay";
++};
++
++&uart0 {
++ status = "okay";
++};
++
++&spi0 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&spi0_pins>;
++
++ spidev@0{
++ compatible = "spidev";
++ reg = <0>; /* CE0 */
++ #address-cells = <1>;
++ #size-cells = <0>;
++ spi-max-frequency = <500000>;
++ };
++
++ spidev@1{
++ compatible = "spidev";
++ reg = <1>; /* CE1 */
++ #address-cells = <1>;
++ #size-cells = <0>;
++ spi-max-frequency = <500000>;
++ };
++};
++
++&i2c0 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&i2c0_pins>;
++ clock-frequency = <100000>;
++};
++
++&i2c1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&i2c1_pins>;
++ clock-frequency = <100000>;
++};
++
++&i2c2 {
++ clock-frequency = <100000>;
++};
++
++&i2s {
++ #sound-dai-cells = <0>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&i2s_pins>;
++};
++
++&leds {
++ act_led: act {
++ label = "led0";
++ linux,default-trigger = "mmc0";
++ gpios = <&gpio 16 1>;
++ };
++};
++
++/ {
++ __overrides__ {
++ uart0 = <&uart0>,"status";
++ uart0_clkrate = <&clk_uart0>,"clock-frequency:0";
++ uart1_clkrate = <&uart1>,"clock-frequency:0";
++ i2s = <&i2s>,"status";
++ spi = <&spi0>,"status";
++ i2c0 = <&i2c0>,"status";
++ i2c1 = <&i2c1>,"status";
++ i2c2_iknowwhatimdoing = <&i2c2>,"status";
++ i2c0_baudrate = <&i2c0>,"clock-frequency:0";
++ i2c1_baudrate = <&i2c1>,"clock-frequency:0";
++ i2c2_baudrate = <&i2c2>,"clock-frequency:0";
++ core_freq = <&clk_core>,"clock-frequency:0";
++
++ act_led_gpio = <&act_led>,"gpios:4";
++ act_led_activelow = <&act_led>,"gpios:8";
++ act_led_trigger = <&act_led>,"linux,default-trigger";
++
++ audio = <&audio>,"status";
++ watchdog = <&watchdog>,"status";
++ random = <&random>,"status";
++ };
++};
+diff -Nur linux-4.1.3/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts linux-xbian-rpi/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts
+--- linux-4.1.3/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts 2015-07-28 01:20:58.166151930 +0200
+@@ -0,0 +1,129 @@
++/dts-v1/;
++
++/include/ "bcm2708.dtsi"
++
++/ {
++ compatible = "brcm,bcm2708";
++ model = "Raspberry Pi Model B+";
++};
++
++&gpio {
++ spi0_pins: spi0_pins {
++ brcm,pins = <7 8 9 10 11>;
++ brcm,function = <4>; /* alt0 */
++ };
++
++ i2c0_pins: i2c0 {
++ brcm,pins = <0 1>;
++ brcm,function = <4>;
++ };
++
++ i2c1_pins: i2c1 {
++ brcm,pins = <2 3>;
++ brcm,function = <4>;
++ };
++
++ i2s_pins: i2s {
++ brcm,pins = <18 19 20 21>;
++ brcm,function = <4>; /* alt0 */
++ };
++};
++
++&mmc {
++ status = "okay";
++ bus-width = <4>;
++};
++
++&fb {
++ status = "okay";
++};
++
++&uart0 {
++ status = "okay";
++};
++
++&spi0 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&spi0_pins>;
++
++ spidev@0{
++ compatible = "spidev";
++ reg = <0>; /* CE0 */
++ #address-cells = <1>;
++ #size-cells = <0>;
++ spi-max-frequency = <500000>;
++ };
++
++ spidev@1{
++ compatible = "spidev";
++ reg = <1>; /* CE1 */
++ #address-cells = <1>;
++ #size-cells = <0>;
++ spi-max-frequency = <500000>;
++ };
++};
++
++&i2c0 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&i2c0_pins>;
++ clock-frequency = <100000>;
++};
++
++&i2c1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&i2c1_pins>;
++ clock-frequency = <100000>;
++};
++
++&i2c2 {
++ clock-frequency = <100000>;
++};
++
++&i2s {
++ #sound-dai-cells = <0>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&i2s_pins>;
++};
++
++&leds {
++ act_led: act {
++ label = "led0";
++ linux,default-trigger = "mmc0";
++ gpios = <&gpio 47 0>;
++ };
++
++ pwr_led: pwr {
++ label = "led1";
++ linux,default-trigger = "input";
++ gpios = <&gpio 35 0>;
++ };
++};
++
++/ {
++ __overrides__ {
++ uart0 = <&uart0>,"status";
++ uart0_clkrate = <&clk_uart0>,"clock-frequency:0";
++ uart1_clkrate = <&uart1>,"clock-frequency:0";
++ i2s = <&i2s>,"status";
++ spi = <&spi0>,"status";
++ i2c0 = <&i2c0>,"status";
++ i2c1 = <&i2c1>,"status";
++ i2c2_iknowwhatimdoing = <&i2c2>,"status";
++ i2c0_baudrate = <&i2c0>,"clock-frequency:0";
++ i2c1_baudrate = <&i2c1>,"clock-frequency:0";
++ i2c2_baudrate = <&i2c2>,"clock-frequency:0";
++ core_freq = <&clk_core>,"clock-frequency:0";
++
++ act_led_gpio = <&act_led>,"gpios:4";
++ act_led_activelow = <&act_led>,"gpios:8";
++ act_led_trigger = <&act_led>,"linux,default-trigger";
++
++ pwr_led_gpio = <&pwr_led>,"gpios:4";
++ pwr_led_activelow = <&pwr_led>,"gpios:8";
++ pwr_led_trigger = <&pwr_led>,"linux,default-trigger";
++
++ audio = <&audio>,"status";
++ watchdog = <&watchdog>,"status";
++ random = <&random>,"status";
++ };
++};
+diff -Nur linux-4.1.3/arch/arm/boot/dts/bcm2708-rpi-cm.dts linux-xbian-rpi/arch/arm/boot/dts/bcm2708-rpi-cm.dts
+--- linux-4.1.3/arch/arm/boot/dts/bcm2708-rpi-cm.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/boot/dts/bcm2708-rpi-cm.dts 2015-07-28 01:20:58.166151930 +0200
+@@ -0,0 +1,93 @@
++/dts-v1/;
++
++/include/ "bcm2708-rpi-cm.dtsi"
++
++/ {
++ model = "Raspberry Pi Compute Module";
++};
++
++&uart0 {
++ status = "okay";
++};
++
++&gpio {
++ spi0_pins: spi0_pins {
++ brcm,pins = <7 8 9 10 11>;
++ brcm,function = <4>; /* alt0 */
++ };
++
++ i2c0_pins: i2c0 {
++ brcm,pins = <0 1>;
++ brcm,function = <4>;
++ };
++
++ i2c1_pins: i2c1 {
++ brcm,pins = <2 3>;
++ brcm,function = <4>;
++ };
++
++ i2s_pins: i2s {
++ brcm,pins = <18 19 20 21>;
++ brcm,function = <4>; /* alt0 */
++ };
++};
++
++&spi0 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&spi0_pins>;
++
++ spidev@0{
++ compatible = "spidev";
++ reg = <0>; /* CE0 */
++ #address-cells = <1>;
++ #size-cells = <0>;
++ spi-max-frequency = <500000>;
++ };
++
++ spidev@1{
++ compatible = "spidev";
++ reg = <1>; /* CE1 */
++ #address-cells = <1>;
++ #size-cells = <0>;
++ spi-max-frequency = <500000>;
++ };
++};
++
++&i2c0 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&i2c0_pins>;
++ clock-frequency = <100000>;
++};
++
++&i2c1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&i2c1_pins>;
++ clock-frequency = <100000>;
++};
++
++&i2c2 {
++ clock-frequency = <100000>;
++};
++
++&i2s {
++ #sound-dai-cells = <0>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&i2s_pins>;
++};
++
++/ {
++ __overrides__ {
++ uart0 = <&uart0>,"status";
++ uart0_clkrate = <&clk_uart0>,"clock-frequency:0";
++ uart1_clkrate = <&uart1>,"clock-frequency:0";
++ i2s = <&i2s>,"status";
++ spi = <&spi0>,"status";
++ i2c0 = <&i2c0>,"status";
++ i2c1 = <&i2c1>,"status";
++ i2c2_iknowwhatimdoing = <&i2c2>,"status";
++ i2c0_baudrate = <&i2c0>,"clock-frequency:0";
++ i2c1_baudrate = <&i2c1>,"clock-frequency:0";
++ i2c2_baudrate = <&i2c2>,"clock-frequency:0";
++ core_freq = <&clk_core>,"clock-frequency:0";
++ };
++};
+diff -Nur linux-4.1.3/arch/arm/boot/dts/bcm2708-rpi-cm.dtsi linux-xbian-rpi/arch/arm/boot/dts/bcm2708-rpi-cm.dtsi
+--- linux-4.1.3/arch/arm/boot/dts/bcm2708-rpi-cm.dtsi 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/boot/dts/bcm2708-rpi-cm.dtsi 2015-07-28 01:20:58.166151930 +0200
+@@ -0,0 +1,30 @@
++/include/ "bcm2708.dtsi"
++
++&leds {
++ act_led: act {
++ label = "led0";
++ linux,default-trigger = "mmc0";
++ gpios = <&gpio 47 0>;
++ };
++};
++
++&mmc {
++ status = "okay";
++ bus-width = <4>;
++};
++
++&fb {
++ status = "okay";
++};
++
++/ {
++ __overrides__ {
++ act_led_gpio = <&act_led>,"gpios:4";
++ act_led_activelow = <&act_led>,"gpios:8";
++ act_led_trigger = <&act_led>,"linux,default-trigger";
++
++ audio = <&audio>,"status";
++ watchdog = <&watchdog>,"status";
++ random = <&random>,"status";
++ };
++};
+diff -Nur linux-4.1.3/arch/arm/boot/dts/bcm2709.dtsi linux-xbian-rpi/arch/arm/boot/dts/bcm2709.dtsi
+--- linux-4.1.3/arch/arm/boot/dts/bcm2709.dtsi 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/boot/dts/bcm2709.dtsi 2015-07-28 01:20:58.166151930 +0200
+@@ -0,0 +1,70 @@
++/include/ "bcm2708_common.dtsi"
++
++/ {
++ compatible = "brcm,bcm2709";
++ model = "BCM2709";
++
++ chosen {
++ /* No padding required - the boot loader can do that. */
++ bootargs = "";
++ };
++
++ soc {
++ ranges = <0x7e000000 0x3f000000 0x01000000>;
++
++ arm-pmu {
++ compatible = "arm,cortex-a7-pmu";
++ interrupts = <3 9>;
++ };
++ };
++
++ timer {
++ compatible = "arm,armv7-timer";
++ clock-frequency = <19200000>;
++ interrupts = <3 0>, // PHYS_SECURE_PPI
++ <3 1>, // PHYS_NONSECURE_PPI
++ <3 3>, // VIRT_PPI
++ <3 2>; // HYP_PPI
++ always-on;
++ };
++
++ cpus: cpus {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ v7_cpu0: cpu@0 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a7";
++ reg = <0xf00>;
++ clock-frequency = <800000000>;
++ };
++
++ v7_cpu1: cpu@1 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a7";
++ reg = <0xf01>;
++ clock-frequency = <800000000>;
++ };
++
++ v7_cpu2: cpu@2 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a7";
++ reg = <0xf02>;
++ clock-frequency = <800000000>;
++ };
++
++ v7_cpu3: cpu@3 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a7";
++ reg = <0xf03>;
++ clock-frequency = <800000000>;
++ };
++ };
++
++ __overrides__ {
++ arm_freq = <&v7_cpu0>, "clock-frequency:0",
++ <&v7_cpu1>, "clock-frequency:0",
++ <&v7_cpu2>, "clock-frequency:0",
++ <&v7_cpu3>, "clock-frequency:0";
++ };
++};
+diff -Nur linux-4.1.3/arch/arm/boot/dts/bcm2709-rpi-2-b.dts linux-xbian-rpi/arch/arm/boot/dts/bcm2709-rpi-2-b.dts
+--- linux-4.1.3/arch/arm/boot/dts/bcm2709-rpi-2-b.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/boot/dts/bcm2709-rpi-2-b.dts 2015-07-28 01:20:58.166151930 +0200
+@@ -0,0 +1,129 @@
++/dts-v1/;
++
++/include/ "bcm2709.dtsi"
++
++/ {
++ compatible = "brcm,bcm2709";
++ model = "Raspberry Pi 2 Model B";
++};
++
++&gpio {
++ spi0_pins: spi0_pins {
++ brcm,pins = <7 8 9 10 11>;
++ brcm,function = <4>; /* alt0 */
++ };
++
++ i2c0_pins: i2c0 {
++ brcm,pins = <0 1>;
++ brcm,function = <4>;
++ };
++
++ i2c1_pins: i2c1 {
++ brcm,pins = <2 3>;
++ brcm,function = <4>;
++ };
++
++ i2s_pins: i2s {
++ brcm,pins = <18 19 20 21>;
++ brcm,function = <4>; /* alt0 */
++ };
++};
++
++&mmc {
++ status = "okay";
++ bus-width = <4>;
++};
++
++&fb {
++ status = "okay";
++};
++
++&uart0 {
++ status = "okay";
++};
++
++&spi0 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&spi0_pins>;
++
++ spidev@0{
++ compatible = "spidev";
++ reg = <0>; /* CE0 */
++ #address-cells = <1>;
++ #size-cells = <0>;
++ spi-max-frequency = <500000>;
++ };
++
++ spidev@1{
++ compatible = "spidev";
++ reg = <1>; /* CE1 */
++ #address-cells = <1>;
++ #size-cells = <0>;
++ spi-max-frequency = <500000>;
++ };
++};
++
++&i2c0 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&i2c0_pins>;
++ clock-frequency = <100000>;
++};
++
++&i2c1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&i2c1_pins>;
++ clock-frequency = <100000>;
++};
++
++&i2c2 {
++ clock-frequency = <100000>;
++};
++
++&i2s {
++ #sound-dai-cells = <0>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&i2s_pins>;
++};
++
++&leds {
++ act_led: act {
++ label = "led0";
++ linux,default-trigger = "mmc0";
++ gpios = <&gpio 47 0>;
++ };
++
++ pwr_led: pwr {
++ label = "led1";
++ linux,default-trigger = "input";
++ gpios = <&gpio 35 0>;
++ };
++};
++
++/ {
++ __overrides__ {
++ uart0 = <&uart0>,"status";
++ uart0_clkrate = <&clk_uart0>,"clock-frequency:0";
++ uart1_clkrate = <&uart1>,"clock-frequency:0";
++ i2s = <&i2s>,"status";
++ spi = <&spi0>,"status";
++ i2c0 = <&i2c0>,"status";
++ i2c1 = <&i2c1>,"status";
++ i2c2_iknowwhatimdoing = <&i2c2>,"status";
++ i2c0_baudrate = <&i2c0>,"clock-frequency:0";
++ i2c1_baudrate = <&i2c1>,"clock-frequency:0";
++ i2c2_baudrate = <&i2c2>,"clock-frequency:0";
++ core_freq = <&clk_core>,"clock-frequency:0";
++
++ act_led_gpio = <&act_led>,"gpios:4";
++ act_led_activelow = <&act_led>,"gpios:8";
++ act_led_trigger = <&act_led>,"linux,default-trigger";
++
++ pwr_led_gpio = <&pwr_led>,"gpios:4";
++ pwr_led_activelow = <&pwr_led>,"gpios:8";
++ pwr_led_trigger = <&pwr_led>,"linux,default-trigger";
++
++ audio = <&audio>,"status";
++ watchdog = <&watchdog>,"status";
++ random = <&random>,"status";
++ };
++};
+diff -Nur linux-4.1.3/arch/arm/boot/dts/bcm2835.dtsi linux-xbian-rpi/arch/arm/boot/dts/bcm2835.dtsi
+--- linux-4.1.3/arch/arm/boot/dts/bcm2835.dtsi 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/arch/arm/boot/dts/bcm2835.dtsi 2015-07-28 01:20:58.166151930 +0200
+@@ -6,14 +6,15 @@
+ interrupt-parent = <&intc>;
+
+ chosen {
+- bootargs = "earlyprintk console=ttyAMA0";
++ bootargs = "";
+ };
+
+- soc {
++ soc: soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x7e000000 0x20000000 0x02000000>;
++ dma-ranges = <0x40000000 0x00000000 0x20000000>;
+
+ timer@7e003000 {
+ compatible = "brcm,bcm2835-system-timer";
+@@ -50,16 +51,23 @@
+ #interrupt-cells = <2>;
+ };
+
+- watchdog@7e100000 {
++ watchdog: watchdog@7e100000 {
+ compatible = "brcm,bcm2835-pm-wdt";
+ reg = <0x7e100000 0x28>;
+ };
+
+- rng@7e104000 {
++ random: rng@7e104000 {
+ compatible = "brcm,bcm2835-rng";
+ reg = <0x7e104000 0x10>;
+ };
+
++ mailbox: mailbox@7e00b800 {
++ compatible = "brcm,bcm2835-mbox";
++ reg = <0x7e00b880 0x40>;
++ interrupts = <0 1>;
++ #mbox-cells = <0>;
++ };
++
+ gpio: gpio@7e200000 {
+ compatible = "brcm,bcm2835-gpio";
+ reg = <0x7e200000 0xb4>;
+@@ -83,7 +91,7 @@
+ #interrupt-cells = <2>;
+ };
+
+- uart@7e201000 {
++ uart0: uart@7e201000 {
+ compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
+ reg = <0x7e201000 0x1000>;
+ interrupts = <2 25>;
+@@ -93,8 +101,8 @@
+
+ i2s: i2s@7e203000 {
+ compatible = "brcm,bcm2835-i2s";
+- reg = <0x7e203000 0x20>,
+- <0x7e101098 0x02>;
++ reg = <0x7e203000 0x24>,
++ <0x7e101098 0x08>;
+
+ dmas = <&dma 2>,
+ <&dma 3>;
+@@ -102,7 +110,7 @@
+ status = "disabled";
+ };
+
+- spi: spi@7e204000 {
++ spi0: spi@7e204000 {
+ compatible = "brcm,bcm2835-spi";
+ reg = <0x7e204000 0x1000>;
+ interrupts = <2 22>;
+@@ -122,11 +130,14 @@
+ status = "disabled";
+ };
+
+- sdhci: sdhci@7e300000 {
+- compatible = "brcm,bcm2835-sdhci";
++ mmc: mmc@7e300000 {
++ compatible = "brcm,bcm2835-mmc";
+ reg = <0x7e300000 0x100>;
+ interrupts = <2 30>;
+ clocks = <&clk_mmc>;
++ dmas = <&dma 11>,
++ <&dma 11>;
++ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+@@ -140,10 +151,12 @@
+ status = "disabled";
+ };
+
+- usb@7e980000 {
+- compatible = "brcm,bcm2835-usb";
+- reg = <0x7e980000 0x10000>;
+- interrupts = <1 9>;
++ usb: usb@7e980000 {
++ compatible = "brcm,bcm2708-usb";
++ reg = <0x7e980000 0x10000>,
++ <0x7e006000 0x1000>;
++ interrupts = <2 0>,
++ <1 9>;
+ };
+
+ arm-pmu {
+@@ -161,7 +174,7 @@
+ reg = <0>;
+ #clock-cells = <0>;
+ clock-output-names = "mmc";
+- clock-frequency = <100000000>;
++ clock-frequency = <250000000>;
+ };
+
+ clk_i2c: clock@1 {
+diff -Nur linux-4.1.3/arch/arm/boot/dts/bcm2835-rpi-b.dts linux-xbian-rpi/arch/arm/boot/dts/bcm2835-rpi-b.dts
+--- linux-4.1.3/arch/arm/boot/dts/bcm2835-rpi-b.dts 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/arch/arm/boot/dts/bcm2835-rpi-b.dts 2015-07-28 01:20:58.166151930 +0200
+@@ -5,19 +5,28 @@
+ compatible = "raspberrypi,model-b", "brcm,bcm2835";
+ model = "Raspberry Pi Model B";
+
+- leds {
+- act {
+- gpios = <&gpio 16 1>;
+- };
+- };
+ };
+
+ &gpio {
+- pinctrl-0 = <&gpioout &alt0 &i2s_alt2 &alt3>;
+-
+- /* I2S interface */
+- i2s_alt2: i2s_alt2 {
++ i2s_pins: i2s {
+ brcm,pins = <28 29 30 31>;
+- brcm,function = <6>; /* alt2 */
++ brcm,function = <4>; /* alt0 */
++ };
++};
++
++&i2s {
++ #sound-dai-cells = <0>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&i2s_pins>;
++};
++
++&act_led {
++ gpios = <&gpio 16 1>;
++};
++
++/ {
++ __overrides__ {
++ act_led_gpio = <&act_led>,"gpios:4";
++ act_led_activelow = <&act_led>,"gpios:8";
+ };
+ };
+diff -Nur linux-4.1.3/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts linux-xbian-rpi/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts
+--- linux-4.1.3/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts 2015-07-28 01:20:58.166151930 +0200
+@@ -4,27 +4,40 @@
+ / {
+ compatible = "raspberrypi,model-b-plus", "brcm,bcm2835";
+ model = "Raspberry Pi Model B+";
+-
+- leds {
+- act {
+- gpios = <&gpio 47 0>;
+- };
+-
+- pwr {
+- label = "PWR";
+- gpios = <&gpio 35 0>;
+- default-state = "keep";
+- linux,default-trigger = "default-on";
+- };
+- };
+ };
+
+ &gpio {
+- pinctrl-0 = <&gpioout &alt0 &i2s_alt0 &alt3>;
+-
+- /* I2S interface */
+- i2s_alt0: i2s_alt0 {
++ i2s_pins: i2s {
+ brcm,pins = <18 19 20 21>;
+ brcm,function = <4>; /* alt0 */
+ };
+ };
++
++&i2s {
++ #sound-dai-cells = <0>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&i2s_pins>;
++};
++
++&act_led {
++ gpios = <&gpio 47 0>;
++};
++
++&leds {
++ pwr_led: pwr {
++ label = "led1";
++ linux,default-trigger = "input";
++ gpios = <&gpio 35 0>;
++ };
++};
++
++/ {
++ __overrides__ {
++ act_led_gpio = <&act_led>,"gpios:4";
++ act_led_activelow = <&act_led>,"gpios:8";
++
++ pwr_led_gpio = <&pwr_led>,"gpios:4";
++ pwr_led_activelow = <&pwr_led>,"gpios:8";
++ pwr_led_trigger = <&pwr_led>,"linux,default-trigger";
++ };
++};
+diff -Nur linux-4.1.3/arch/arm/boot/dts/bcm2835-rpi.dtsi linux-xbian-rpi/arch/arm/boot/dts/bcm2835-rpi.dtsi
+--- linux-4.1.3/arch/arm/boot/dts/bcm2835-rpi.dtsi 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/arch/arm/boot/dts/bcm2835-rpi.dtsi 2015-07-28 01:20:58.166151930 +0200
+@@ -1,51 +1,133 @@
+ /include/ "bcm2835.dtsi"
+
+ / {
++ /* This is left here in case u-boot needs it */
+ memory {
+ reg = <0 0x10000000>;
+ };
+
+- leds {
++ aliases {
++ soc = &soc;
++ spi0 = &spi0;
++ i2c0 = &i2c0;
++ i2c1 = &i2c1;
++ i2s = &i2s;
++ gpio = &gpio;
++ intc = &intc;
++ leds = &leds;
++ sound = &sound;
++ };
++
++ leds: leds {
+ compatible = "gpio-leds";
+
+- act {
+- label = "ACT";
+- default-state = "keep";
+- linux,default-trigger = "heartbeat";
++ act_led: act {
++ label = "led0";
++ linux,default-trigger = "mmc0";
++ };
++ };
++
++ soc {
++ firmware: firmware {
++ compatible = "raspberrypi,bcm2835-firmware";
++ mboxes = <&mailbox>;
++ };
++
++ fb: fb {
++ compatible = "brcm,bcm2708-fb";
++ firmware = <&firmware>;
++ };
++
++ thermal: thermal {
++ compatible = "brcm,bcm2835-thermal";
++ firmware = <&firmware>;
++ };
++
++ vchiq: vchiq {
++ compatible = "brcm,bcm2835-vchiq";
++ reg = <0x7e00b840 0xf>;
++ interrupts = <0 2>;
++ cache-line-size = <32>;
++ firmware = <&firmware>;
+ };
+ };
++
++ /* Onboard audio */
++ audio: audio {
++ compatible = "brcm,bcm2835-audio";
++ brcm,pwm-channels = <8>;
++ status = "disabled";
++ };
++
++ /* External sound card */
++ sound: sound {
++ };
+ };
+
+ &gpio {
+- pinctrl-names = "default";
++ spi0_pins: spi0_pins {
++ brcm,pins = <7 8 9 10 11>;
++ brcm,function = <4>; /* alt0 */
++ };
+
+- gpioout: gpioout {
+- brcm,pins = <6>;
+- brcm,function = <1>; /* GPIO out */
++ i2c0_pins: i2c0 {
++ brcm,pins = <0 1>;
++ brcm,function = <4>;
+ };
+
+- alt0: alt0 {
+- brcm,pins = <0 1 2 3 4 5 7 8 9 10 11 14 15 40 45>;
+- brcm,function = <4>; /* alt0 */
++ i2c1_pins: i2c1 {
++ brcm,pins = <2 3>;
++ brcm,function = <4>;
++ };
++};
++
++&spi0 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&spi0_pins>;
++
++ spidev@0{
++ compatible = "spidev";
++ reg = <0>; /* CE0 */
++ #address-cells = <1>;
++ #size-cells = <0>;
++ spi-max-frequency = <500000>;
+ };
+
+- alt3: alt3 {
+- brcm,pins = <48 49 50 51 52 53>;
+- brcm,function = <7>; /* alt3 */
++ spidev@1{
++ compatible = "spidev";
++ reg = <1>; /* CE1 */
++ #address-cells = <1>;
++ #size-cells = <0>;
++ spi-max-frequency = <500000>;
+ };
+ };
+
+ &i2c0 {
+- status = "okay";
++ pinctrl-names = "default";
++ pinctrl-0 = <&i2c0_pins>;
+ clock-frequency = <100000>;
+ };
+
+ &i2c1 {
+- status = "okay";
++ pinctrl-names = "default";
++ pinctrl-0 = <&i2c1_pins>;
+ clock-frequency = <100000>;
+ };
+
+-&sdhci {
++&mmc {
+ status = "okay";
+ bus-width = <4>;
+ };
++
++/ {
++ __overrides__ {
++ i2s = <&i2s>,"status";
++ spi = <&spi0>,"status";
++ i2c0 = <&i2c0>,"status";
++ i2c1 = <&i2c1>,"status";
++ i2c0_baudrate = <&i2c0>,"clock-frequency:0";
++ i2c1_baudrate = <&i2c1>,"clock-frequency:0";
++ act_led_trigger = <&act_led>,"linux,default-trigger";
++ audio = <&audio>,"status";
++ };
++};
+diff -Nur linux-4.1.3/arch/arm/boot/dts/Makefile linux-xbian-rpi/arch/arm/boot/dts/Makefile
+--- linux-4.1.3/arch/arm/boot/dts/Makefile 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/arch/arm/boot/dts/Makefile 2015-07-28 01:20:58.162166151 +0200
+@@ -1,5 +1,21 @@
+ ifeq ($(CONFIG_OF),y)
+
++dtb-$(CONFIG_BCM2708_DT) += bcm2708-rpi-b.dtb
++dtb-$(CONFIG_BCM2708_DT) += bcm2708-rpi-b-plus.dtb
++dtb-$(CONFIG_BCM2708_DT) += bcm2708-rpi-cm.dtb
++dtb-$(CONFIG_BCM2709_DT) += bcm2709-rpi-2-b.dtb
++
++# Raspberry Pi
++ifeq ($(CONFIG_BCM2708_DT),y)
++ RPI_DT_OVERLAYS=y
++endif
++ifeq ($(CONFIG_BCM2709_DT),y)
++ RPI_DT_OVERLAYS=y
++endif
++ifeq ($(CONFIG_ARCH_BCM2835),y)
++ RPI_DT_OVERLAYS=y
++endif
++
+ dtb-$(CONFIG_ARCH_ALPINE) += \
+ alpine-db.dtb
+ dtb-$(CONFIG_MACH_ASM9260) += \
+@@ -660,7 +676,18 @@
+ mt6592-evb.dtb \
+ mt8127-moose.dtb \
+ mt8135-evbp1.dtb
++
++targets += dtbs dtbs_install
++targets += $(dtb-y)
++
+ endif
+
+ always := $(dtb-y)
+ clean-files := *.dtb
++
++# Enable fixups to support overlays on BCM2708 platforms
++ifeq ($(RPI_DT_OVERLAYS),y)
++ DTC_FLAGS ?= -@
++endif
++
++subdir-y += overlays
+diff -Nur linux-4.1.3/arch/arm/boot/dts/overlays/ads7846-overlay.dts linux-xbian-rpi/arch/arm/boot/dts/overlays/ads7846-overlay.dts
+--- linux-4.1.3/arch/arm/boot/dts/overlays/ads7846-overlay.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/boot/dts/overlays/ads7846-overlay.dts 2015-07-28 01:20:58.166151930 +0200
+@@ -0,0 +1,83 @@
++/*
++ * Generic Device Tree overlay for the ADS7846 touch controller
++ *
++ */
++
++/dts-v1/;
++/plugin/;
++
++/ {
++ compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709";
++
++ fragment@0 {
++ target = <&spi0>;
++ __overlay__ {
++ status = "okay";
++
++ spidev@0{
++ status = "disabled";
++ };
++
++ spidev@1{
++ status = "disabled";
++ };
++ };
++ };
++
++ fragment@1 {
++ target = <&gpio>;
++ __overlay__ {
++ ads7846_pins: ads7846_pins {
++ brcm,pins = <255>; /* illegal default value */
++ brcm,function = <0>; /* in */
++ brcm,pull = <0>; /* none */
++ };
++ };
++ };
++
++ fragment@2 {
++ target = <&spi0>;
++ __overlay__ {
++ /* needed to avoid dtc warning */
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ ads7846: ads7846@1 {
++ compatible = "ti,ads7846";
++ reg = <1>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&ads7846_pins>;
++
++ spi-max-frequency = <2000000>;
++ interrupts = <255 2>; /* high-to-low edge triggered */
++ interrupt-parent = <&gpio>;
++ pendown-gpio = <&gpio 255 0>;
++
++ /* driver defaults */
++ ti,x-min = /bits/ 16 <0>;
++ ti,y-min = /bits/ 16 <0>;
++ ti,x-max = /bits/ 16 <0x0FFF>;
++ ti,y-max = /bits/ 16 <0x0FFF>;
++ ti,pressure-min = /bits/ 16 <0>;
++ ti,pressure-max = /bits/ 16 <0xFFFF>;
++ ti,x-plate-ohms = /bits/ 16 <400>;
++ };
++ };
++ };
++ __overrides__ {
++ cs = <&ads7846>,"reg:0";
++ speed = <&ads7846>,"spi-max-frequency:0";
++ penirq = <&ads7846_pins>,"brcm,pins:0", /* REQUIRED */
++ <&ads7846>,"interrupts:0",
++ <&ads7846>,"pendown-gpio:4";
++ penirq_pull = <&ads7846_pins>,"brcm,pull:0";
++ swapxy = <&ads7846>,"ti,swap-xy?";
++ xmin = <&ads7846>,"ti,x-min;0";
++ ymin = <&ads7846>,"ti,y-min;0";
++ xmax = <&ads7846>,"ti,x-max;0";
++ ymax = <&ads7846>,"ti,y-max;0";
++ pmin = <&ads7846>,"ti,pressure-min;0";
++ pmax = <&ads7846>,"ti,pressure-max;0";
++ xohms = <&ads7846>,"ti,x-plate-ohms;0";
++ };
++};
+diff -Nur linux-4.1.3/arch/arm/boot/dts/overlays/bmp085_i2c-sensor-overlay.dts linux-xbian-rpi/arch/arm/boot/dts/overlays/bmp085_i2c-sensor-overlay.dts
+--- linux-4.1.3/arch/arm/boot/dts/overlays/bmp085_i2c-sensor-overlay.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/boot/dts/overlays/bmp085_i2c-sensor-overlay.dts 2015-07-28 01:20:58.166151930 +0200
+@@ -0,0 +1,23 @@
++// Definitions for BMP085/BMP180 digital barometric pressure and temperature sensors from Bosch Sensortec
++/dts-v1/;
++/plugin/;
++
++/ {
++ compatible = "brcm,bcm2708";
++
++ fragment@0 {
++ target = <&i2c_arm>;
++ __overlay__ {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "okay";
++
++ bmp085@77 {
++ compatible = "bosch,bmp085";
++ reg = <0x77>;
++ default-oversampling = <3>;
++ status = "okay";
++ };
++ };
++ };
++};
+diff -Nur linux-4.1.3/arch/arm/boot/dts/overlays/dht11-overlay.dts linux-xbian-rpi/arch/arm/boot/dts/overlays/dht11-overlay.dts
+--- linux-4.1.3/arch/arm/boot/dts/overlays/dht11-overlay.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/boot/dts/overlays/dht11-overlay.dts 2015-07-28 01:20:58.166151930 +0200
+@@ -0,0 +1,39 @@
++/*
++ * Overlay for the DHT11/21/22 humidity/temperature sensor modules.
++ */
++/dts-v1/;
++/plugin/;
++
++/ {
++ compatible = "brcm,bcm2708";
++
++ fragment@0 {
++ target-path = "/";
++ __overlay__ {
++
++ dht11: dht11@0 {
++ compatible = "dht11";
++ pinctrl-names = "default";
++ pinctrl-0 = <&dht11_pins>;
++ gpios = <&gpio 4 0>;
++ status = "okay";
++ };
++ };
++ };
++
++ fragment@1 {
++ target = <&gpio>;
++ __overlay__ {
++ dht11_pins: dht11_pins {
++ brcm,pins = <4>;
++ brcm,function = <0>; // in
++ brcm,pull = <0>; // off
++ };
++ };
++ };
++
++ __overrides__ {
++ gpiopin = <&dht11_pins>,"brcm,pins:0",
++ <&dht11>,"gpios:4";
++ };
++};
+diff -Nur linux-4.1.3/arch/arm/boot/dts/overlays/enc28j60-overlay.dts linux-xbian-rpi/arch/arm/boot/dts/overlays/enc28j60-overlay.dts
+--- linux-4.1.3/arch/arm/boot/dts/overlays/enc28j60-overlay.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/boot/dts/overlays/enc28j60-overlay.dts 2015-07-28 01:20:58.166151930 +0200
+@@ -0,0 +1,50 @@
++// Overlay for the Microchip ENC28J60 Ethernet Controller
++/dts-v1/;
++/plugin/;
++
++/ {
++ compatible = "brcm,bcm2708";
++
++ fragment@0 {
++ target = <&spi0>;
++ __overlay__ {
++ /* needed to avoid dtc warning */
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ status = "okay";
++
++ spidev@0{
++ status = "disabled";
++ };
++
++ eth1: enc28j60@0{
++ compatible = "microchip,enc28j60";
++ reg = <0>; /* CE0 */
++ pinctrl-names = "default";
++ pinctrl-0 = <&eth1_pins>;
++ interrupt-parent = <&gpio>;
++ interrupts = <25 0x2>; /* falling edge */
++ spi-max-frequency = <12000000>;
++ status = "okay";
++ };
++ };
++ };
++
++ fragment@1 {
++ target = <&gpio>;
++ __overlay__ {
++ eth1_pins: eth1_pins {
++ brcm,pins = <25>;
++ brcm,function = <0>; /* in */
++ brcm,pull = <0>; /* none */
++ };
++ };
++ };
++
++ __overrides__ {
++ int_pin = <&eth1>, "interrupts:0",
++ <&eth1_pins>, "brcm,pins:0";
++ speed = <&eth1>, "spi-max-frequency:0";
++ };
++};
+diff -Nur linux-4.1.3/arch/arm/boot/dts/overlays/gpio-poweroff-overlay.dts linux-xbian-rpi/arch/arm/boot/dts/overlays/gpio-poweroff-overlay.dts
+--- linux-4.1.3/arch/arm/boot/dts/overlays/gpio-poweroff-overlay.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/boot/dts/overlays/gpio-poweroff-overlay.dts 2015-07-28 01:20:58.166151930 +0200
+@@ -0,0 +1,34 @@
++// Definitions for gpio-poweroff module
++/dts-v1/;
++/plugin/;
++
++/ {
++ compatible = "brcm,bcm2708";
++
++ fragment@0 {
++ target-path = "/";
++ __overlay__ {
++ power_ctrl: power_ctrl {
++ compatible = "gpio-poweroff";
++ gpios = <&gpio 26 0>;
++ force;
++ };
++ };
++ };
++
++ fragment@1 {
++ target = <&gpio>;
++ __overlay__ {
++ power_ctrl_pins: power_ctrl_pins {
++ brcm,pins = <26>;
++ brcm,function = <1>; // out
++ };
++ };
++ };
++
++ __overrides__ {
++ gpiopin = <&power_ctrl>,"gpios:4",
++ <&power_ctrl_pins>,"brcm,pins:0";
++ active_low = <&power_ctrl>,"gpios:8";
++ };
++};
+diff -Nur linux-4.1.3/arch/arm/boot/dts/overlays/hifiberry-amp-overlay.dts linux-xbian-rpi/arch/arm/boot/dts/overlays/hifiberry-amp-overlay.dts
+--- linux-4.1.3/arch/arm/boot/dts/overlays/hifiberry-amp-overlay.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/boot/dts/overlays/hifiberry-amp-overlay.dts 2015-07-28 01:20:58.166151930 +0200
+@@ -0,0 +1,39 @@
++// Definitions for HiFiBerry Amp/Amp+
++/dts-v1/;
++/plugin/;
++
++/ {
++ compatible = "brcm,bcm2708";
++
++ fragment@0 {
++ target = <&sound>;
++ __overlay__ {
++ compatible = "hifiberry,hifiberry-amp";
++ i2s-controller = <&i2s>;
++ status = "okay";
++ };
++ };
++
++ fragment@1 {
++ target = <&i2s>;
++ __overlay__ {
++ status = "okay";
++ };
++ };
++
++ fragment@2 {
++ target = <&i2c1>;
++ __overlay__ {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "okay";
++
++ tas5713@1b {
++ #sound-dai-cells = <0>;
++ compatible = "ti,tas5713";
++ reg = <0x1b>;
++ status = "okay";
++ };
++ };
++ };
++};
+diff -Nur linux-4.1.3/arch/arm/boot/dts/overlays/hifiberry-dac-overlay.dts linux-xbian-rpi/arch/arm/boot/dts/overlays/hifiberry-dac-overlay.dts
+--- linux-4.1.3/arch/arm/boot/dts/overlays/hifiberry-dac-overlay.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/boot/dts/overlays/hifiberry-dac-overlay.dts 2015-07-28 01:20:58.166151930 +0200
+@@ -0,0 +1,34 @@
++// Definitions for HiFiBerry DAC
++/dts-v1/;
++/plugin/;
++
++/ {
++ compatible = "brcm,bcm2708";
++
++ fragment@0 {
++ target = <&sound>;
++ __overlay__ {
++ compatible = "hifiberry,hifiberry-dac";
++ i2s-controller = <&i2s>;
++ status = "okay";
++ };
++ };
++
++ fragment@1 {
++ target = <&i2s>;
++ __overlay__ {
++ status = "okay";
++ };
++ };
++
++ fragment@2 {
++ target-path = "/";
++ __overlay__ {
++ pcm5102a-codec {
++ #sound-dai-cells = <0>;
++ compatible = "ti,pcm5102a";
++ status = "okay";
++ };
++ };
++ };
++};
+diff -Nur linux-4.1.3/arch/arm/boot/dts/overlays/hifiberry-dacplus-overlay.dts linux-xbian-rpi/arch/arm/boot/dts/overlays/hifiberry-dacplus-overlay.dts
+--- linux-4.1.3/arch/arm/boot/dts/overlays/hifiberry-dacplus-overlay.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/boot/dts/overlays/hifiberry-dacplus-overlay.dts 2015-07-28 01:20:58.166151930 +0200
+@@ -0,0 +1,39 @@
++// Definitions for HiFiBerry DAC+
++/dts-v1/;
++/plugin/;
++
++/ {
++ compatible = "brcm,bcm2708";
++
++ fragment@0 {
++ target = <&sound>;
++ __overlay__ {
++ compatible = "hifiberry,hifiberry-dacplus";
++ i2s-controller = <&i2s>;
++ status = "okay";
++ };
++ };
++
++ fragment@1 {
++ target = <&i2s>;
++ __overlay__ {
++ status = "okay";
++ };
++ };
++
++ fragment@2 {
++ target = <&i2c1>;
++ __overlay__ {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "okay";
++
++ pcm5122@4d {
++ #sound-dai-cells = <0>;
++ compatible = "ti,pcm5122";
++ reg = <0x4d>;
++ status = "okay";
++ };
++ };
++ };
++};
+diff -Nur linux-4.1.3/arch/arm/boot/dts/overlays/hifiberry-digi-overlay.dts linux-xbian-rpi/arch/arm/boot/dts/overlays/hifiberry-digi-overlay.dts
+--- linux-4.1.3/arch/arm/boot/dts/overlays/hifiberry-digi-overlay.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/boot/dts/overlays/hifiberry-digi-overlay.dts 2015-07-28 01:20:58.166151930 +0200
+@@ -0,0 +1,39 @@
++// Definitions for HiFiBerry Digi
++/dts-v1/;
++/plugin/;
++
++/ {
++ compatible = "brcm,bcm2708";
++
++ fragment@0 {
++ target = <&sound>;
++ __overlay__ {
++ compatible = "hifiberry,hifiberry-digi";
++ i2s-controller = <&i2s>;
++ status = "okay";
++ };
++ };
++
++ fragment@1 {
++ target = <&i2s>;
++ __overlay__ {
++ status = "okay";
++ };
++ };
++
++ fragment@2 {
++ target = <&i2c1>;
++ __overlay__ {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "okay";
++
++ wm8804@3b {
++ #sound-dai-cells = <0>;
++ compatible = "wlf,wm8804";
++ reg = <0x3b>;
++ status = "okay";
++ };
++ };
++ };
++};
+diff -Nur linux-4.1.3/arch/arm/boot/dts/overlays/hy28a-overlay.dts linux-xbian-rpi/arch/arm/boot/dts/overlays/hy28a-overlay.dts
+--- linux-4.1.3/arch/arm/boot/dts/overlays/hy28a-overlay.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/boot/dts/overlays/hy28a-overlay.dts 2015-07-28 01:20:58.166151930 +0200
+@@ -0,0 +1,87 @@
++/*
++ * Device Tree overlay for HY28A display
++ *
++ */
++
++/dts-v1/;
++/plugin/;
++
++/ {
++ compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709";
++
++ fragment@0 {
++ target = <&spi0>;
++ __overlay__ {
++ status = "okay";
++
++ spidev@0{
++ status = "disabled";
++ };
++
++ spidev@1{
++ status = "disabled";
++ };
++ };
++ };
++
++ fragment@1 {
++ target = <&gpio>;
++ __overlay__ {
++ hy28a_pins: hy28a_pins {
++ brcm,pins = <17 25 18>;
++ brcm,function = <0 1 1>; /* in out out */
++ };
++ };
++ };
++
++ fragment@2 {
++ target = <&spi0>;
++ __overlay__ {
++ /* needed to avoid dtc warning */
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ hy28a: hy28a@0{
++ compatible = "ilitek,ili9320";
++ reg = <0>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&hy28a_pins>;
++
++ spi-max-frequency = <32000000>;
++ spi-cpol;
++ spi-cpha;
++ rotate = <270>;
++ bgr;
++ fps = <50>;
++ buswidth = <8>;
++ startbyte = <0x70>;
++ reset-gpios = <&gpio 25 0>;
++ led-gpios = <&gpio 18 1>;
++ debug = <0>;
++ };
++
++ hy28a_ts: hy28a-ts@1 {
++ compatible = "ti,ads7846";
++ reg = <1>;
++
++ spi-max-frequency = <2000000>;
++ interrupts = <17 2>; /* high-to-low edge triggered */
++ interrupt-parent = <&gpio>;
++ pendown-gpio = <&gpio 17 0>;
++ ti,x-plate-ohms = /bits/ 16 <100>;
++ ti,pressure-max = /bits/ 16 <255>;
++ };
++ };
++ };
++ __overrides__ {
++ speed = <&hy28a>,"spi-max-frequency:0";
++ rotate = <&hy28a>,"rotate:0";
++ fps = <&hy28a>,"fps:0";
++ debug = <&hy28a>,"debug:0";
++ xohms = <&hy28a_ts>,"ti,x-plate-ohms;0";
++ resetgpio = <&hy28a>,"reset-gpios:4",
++ <&hy28a_pins>, "brcm,pins:1";
++ ledgpio = <&hy28a>,"led-gpios:4",
++ <&hy28a_pins>, "brcm,pins:2";
++ };
++};
+diff -Nur linux-4.1.3/arch/arm/boot/dts/overlays/hy28b-overlay.dts linux-xbian-rpi/arch/arm/boot/dts/overlays/hy28b-overlay.dts
+--- linux-4.1.3/arch/arm/boot/dts/overlays/hy28b-overlay.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/boot/dts/overlays/hy28b-overlay.dts 2015-07-28 01:20:58.166151930 +0200
+@@ -0,0 +1,142 @@
++/*
++ * Device Tree overlay for HY28b display shield by Texy
++ *
++ */
++
++/dts-v1/;
++/plugin/;
++
++/ {
++ compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709";
++
++ fragment@0 {
++ target = <&spi0>;
++ __overlay__ {
++ status = "okay";
++
++ spidev@0{
++ status = "disabled";
++ };
++
++ spidev@1{
++ status = "disabled";
++ };
++ };
++ };
++
++ fragment@1 {
++ target = <&gpio>;
++ __overlay__ {
++ hy28b_pins: hy28b_pins {
++ brcm,pins = <17 25 18>;
++ brcm,function = <0 1 1>; /* in out out */
++ };
++ };
++ };
++
++ fragment@2 {
++ target = <&spi0>;
++ __overlay__ {
++ /* needed to avoid dtc warning */
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ hy28b: hy28b@0{
++ compatible = "ilitek,ili9325";
++ reg = <0>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&hy28b_pins>;
++
++ spi-max-frequency = <48000000>;
++ spi-cpol;
++ spi-cpha;
++ rotate = <270>;
++ bgr;
++ fps = <50>;
++ buswidth = <8>;
++ startbyte = <0x70>;
++ reset-gpios = <&gpio 25 0>;
++ led-gpios = <&gpio 18 1>;
++
++ gamma = "04 1F 4 7 7 0 7 7 6 0\n0F 00 1 7 4 0 0 0 6 7";
++
++ init = <0x10000e7 0x0010
++ 0x1000000 0x0001
++ 0x1000001 0x0100
++ 0x1000002 0x0700
++ 0x1000003 0x1030
++ 0x1000004 0x0000
++ 0x1000008 0x0207
++ 0x1000009 0x0000
++ 0x100000a 0x0000
++ 0x100000c 0x0001
++ 0x100000d 0x0000
++ 0x100000f 0x0000
++ 0x1000010 0x0000
++ 0x1000011 0x0007
++ 0x1000012 0x0000
++ 0x1000013 0x0000
++ 0x2000032
++ 0x1000010 0x1590
++ 0x1000011 0x0227
++ 0x2000032
++ 0x1000012 0x009c
++ 0x2000032
++ 0x1000013 0x1900
++ 0x1000029 0x0023
++ 0x100002b 0x000e
++ 0x2000032
++ 0x1000020 0x0000
++ 0x1000021 0x0000
++ 0x2000032
++ 0x1000050 0x0000
++ 0x1000051 0x00ef
++ 0x1000052 0x0000
++ 0x1000053 0x013f
++ 0x1000060 0xa700
++ 0x1000061 0x0001
++ 0x100006a 0x0000
++ 0x1000080 0x0000
++ 0x1000081 0x0000
++ 0x1000082 0x0000
++ 0x1000083 0x0000
++ 0x1000084 0x0000
++ 0x1000085 0x0000
++ 0x1000090 0x0010
++ 0x1000092 0x0000
++ 0x1000093 0x0003
++ 0x1000095 0x0110
++ 0x1000097 0x0000
++ 0x1000098 0x0000
++ 0x1000007 0x0133
++ 0x1000020 0x0000
++ 0x1000021 0x0000
++ 0x2000064>;
++ debug = <0>;
++ };
++
++ hy28b_ts: hy28b-ts@1 {
++ compatible = "ti,ads7846";
++ reg = <1>;
++
++ spi-max-frequency = <2000000>;
++ interrupts = <17 2>; /* high-to-low edge triggered */
++ interrupt-parent = <&gpio>;
++ pendown-gpio = <&gpio 17 0>;
++ ti,x-plate-ohms = /bits/ 16 <100>;
++ ti,pressure-max = /bits/ 16 <255>;
++ };
++ };
++ };
++ __overrides__ {
++ speed = <&hy28b>,"spi-max-frequency:0";
++ rotate = <&hy28b>,"rotate:0";
++ fps = <&hy28b>,"fps:0";
++ debug = <&hy28b>,"debug:0";
++ xohms = <&hy28b_ts>,"ti,x-plate-ohms;0";
++ resetgpio = <&hy28b>,"reset-gpios:4",
++ <&hy28b_pins>, "brcm,pins:1";
++ ledgpio = <&hy28b>,"led-gpios:4",
++ <&hy28b_pins>, "brcm,pins:2";
++ };
++};
+diff -Nur linux-4.1.3/arch/arm/boot/dts/overlays/i2c-rtc-overlay.dts linux-xbian-rpi/arch/arm/boot/dts/overlays/i2c-rtc-overlay.dts
+--- linux-4.1.3/arch/arm/boot/dts/overlays/i2c-rtc-overlay.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/boot/dts/overlays/i2c-rtc-overlay.dts 2015-07-28 01:20:58.166151930 +0200
+@@ -0,0 +1,55 @@
++// Definitions for several I2C based Real Time Clocks
++/dts-v1/;
++/plugin/;
++
++/ {
++ compatible = "brcm,bcm2708";
++
++ fragment@0 {
++ target = <&i2c_arm>;
++ __overlay__ {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "okay";
++
++ ds1307: ds1307@68 {
++ compatible = "maxim,ds1307";
++ reg = <0x68>;
++ status = "disable";
++ };
++ mcp7941x: mcp7941x@6f {
++ compatible = "microchip,mcp7941x";
++ reg = <0x6f>;
++ status = "disable";
++ };
++ ds3231: ds3231@68 {
++ compatible = "maxim,ds3231";
++ reg = <0x68>;
++ status = "disable";
++ };
++ pcf2127: pcf2127@51 {
++ compatible = "nxp,pcf2127";
++ reg = <0x51>;
++ status = "disable";
++ };
++ pcf8523: pcf8523@68 {
++ compatible = "nxp,pcf8523";
++ reg = <0x68>;
++ status = "disable";
++ };
++ pcf8563: pcf8563@51 {
++ compatible = "nxp,pcf8563";
++ reg = <0x51>;
++ status = "disable";
++ };
++ };
++ };
++ __overrides__ {
++ ds1307 = <&ds1307>,"status";
++ ds3231 = <&ds3231>,"status";
++ mcp7941x = <&mcp7941x>,"status";
++ pcf2127 = <&pcf2127>,"status";
++ pcf8523 = <&pcf8523>,"status";
++ pcf8563 = <&pcf8563>,"status";
++ };
++};
+diff -Nur linux-4.1.3/arch/arm/boot/dts/overlays/i2s-mmap-overlay.dts linux-xbian-rpi/arch/arm/boot/dts/overlays/i2s-mmap-overlay.dts
+--- linux-4.1.3/arch/arm/boot/dts/overlays/i2s-mmap-overlay.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/boot/dts/overlays/i2s-mmap-overlay.dts 2015-07-28 01:20:58.166151930 +0200
+@@ -0,0 +1,13 @@
++/dts-v1/;
++/plugin/;
++
++/{
++ compatible = "brcm,bcm2708";
++
++ fragment@0 {
++ target = <&i2s>;
++ __overlay__ {
++ brcm,enable-mmap;
++ };
++ };
++};
+diff -Nur linux-4.1.3/arch/arm/boot/dts/overlays/iqaudio-dac-overlay.dts linux-xbian-rpi/arch/arm/boot/dts/overlays/iqaudio-dac-overlay.dts
+--- linux-4.1.3/arch/arm/boot/dts/overlays/iqaudio-dac-overlay.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/boot/dts/overlays/iqaudio-dac-overlay.dts 2015-07-28 01:20:58.166151930 +0200
+@@ -0,0 +1,39 @@
++// Definitions for IQaudIO DAC
++/dts-v1/;
++/plugin/;
++
++/ {
++ compatible = "brcm,bcm2708";
++
++ fragment@0 {
++ target = <&sound>;
++ __overlay__ {
++ compatible = "iqaudio,iqaudio-dac";
++ i2s-controller = <&i2s>;
++ status = "okay";
++ };
++ };
++
++ fragment@1 {
++ target = <&i2s>;
++ __overlay__ {
++ status = "okay";
++ };
++ };
++
++ fragment@2 {
++ target = <&i2c1>;
++ __overlay__ {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "okay";
++
++ pcm5122@4c {
++ #sound-dai-cells = <0>;
++ compatible = "ti,pcm5122";
++ reg = <0x4c>;
++ status = "okay";
++ };
++ };
++ };
++};
+diff -Nur linux-4.1.3/arch/arm/boot/dts/overlays/iqaudio-dacplus-overlay.dts linux-xbian-rpi/arch/arm/boot/dts/overlays/iqaudio-dacplus-overlay.dts
+--- linux-4.1.3/arch/arm/boot/dts/overlays/iqaudio-dacplus-overlay.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/boot/dts/overlays/iqaudio-dacplus-overlay.dts 2015-07-28 01:20:58.166151930 +0200
+@@ -0,0 +1,39 @@
++// Definitions for IQaudIO DAC+
++/dts-v1/;
++/plugin/;
++
++/ {
++ compatible = "brcm,bcm2708";
++
++ fragment@0 {
++ target = <&sound>;
++ __overlay__ {
++ compatible = "iqaudio,iqaudio-dac";
++ i2s-controller = <&i2s>;
++ status = "okay";
++ };
++ };
++
++ fragment@1 {
++ target = <&i2s>;
++ __overlay__ {
++ status = "okay";
++ };
++ };
++
++ fragment@2 {
++ target = <&i2c1>;
++ __overlay__ {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "okay";
++
++ pcm5122@4c {
++ #sound-dai-cells = <0>;
++ compatible = "ti,pcm5122";
++ reg = <0x4c>;
++ status = "okay";
++ };
++ };
++ };
++};
+diff -Nur linux-4.1.3/arch/arm/boot/dts/overlays/lirc-rpi-overlay.dts linux-xbian-rpi/arch/arm/boot/dts/overlays/lirc-rpi-overlay.dts
+--- linux-4.1.3/arch/arm/boot/dts/overlays/lirc-rpi-overlay.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/boot/dts/overlays/lirc-rpi-overlay.dts 2015-07-28 01:20:58.166151930 +0200
+@@ -0,0 +1,57 @@
++// Definitions for lirc-rpi module
++/dts-v1/;
++/plugin/;
++
++/ {
++ compatible = "brcm,bcm2708";
++
++ fragment@0 {
++ target-path = "/";
++ __overlay__ {
++ lirc_rpi: lirc_rpi {
++ compatible = "rpi,lirc-rpi";
++ pinctrl-names = "default";
++ pinctrl-0 = <&lirc_pins>;
++ status = "okay";
++
++ // Override autodetection of IR receiver circuit
++ // (0 = active high, 1 = active low, -1 = no override )
++ rpi,sense = <0xffffffff>;
++
++ // Software carrier
++ // (0 = off, 1 = on)
++ rpi,softcarrier = <1>;
++
++ // Invert output
++ // (0 = off, 1 = on)
++ rpi,invert = <0>;
++
++ // Enable debugging messages
++ // (0 = off, 1 = on)
++ rpi,debug = <0>;
++ };
++ };
++ };
++
++ fragment@1 {
++ target = <&gpio>;
++ __overlay__ {
++ lirc_pins: lirc_pins {
++ brcm,pins = <17 18>;
++ brcm,function = <1 0>; // out in
++ brcm,pull = <0 1>; // off down
++ };
++ };
++ };
++
++ __overrides__ {
++ gpio_out_pin = <&lirc_pins>,"brcm,pins:0";
++ gpio_in_pin = <&lirc_pins>,"brcm,pins:4";
++ gpio_in_pull = <&lirc_pins>,"brcm,pull:4";
++
++ sense = <&lirc_rpi>,"rpi,sense:0";
++ softcarrier = <&lirc_rpi>,"rpi,softcarrier:0";
++ invert = <&lirc_rpi>,"rpi,invert:0";
++ debug = <&lirc_rpi>,"rpi,debug:0";
++ };
++};
+diff -Nur linux-4.1.3/arch/arm/boot/dts/overlays/Makefile linux-xbian-rpi/arch/arm/boot/dts/overlays/Makefile
+--- linux-4.1.3/arch/arm/boot/dts/overlays/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/boot/dts/overlays/Makefile 2015-07-28 01:20:58.166151930 +0200
+@@ -0,0 +1,63 @@
++ifeq ($(CONFIG_OF),y)
++
++# Overlays for the Raspberry Pi platform
++
++ifeq ($(CONFIG_BCM2708_DT),y)
++ RPI_DT_OVERLAYS=y
++endif
++ifeq ($(CONFIG_BCM2709_DT),y)
++ RPI_DT_OVERLAYS=y
++endif
++ifeq ($(CONFIG_ARCH_BCM2835),y)
++ RPI_DT_OVERLAYS=y
++endif
++
++dtb-$(RPI_DT_OVERLAYS) += ads7846-overlay.dtb
++dtb-$(RPI_DT_OVERLAYS) += bmp085_i2c-sensor-overlay.dtb
++dtb-$(RPI_DT_OVERLAYS) += dht11-overlay.dtb
++dtb-$(RPI_DT_OVERLAYS) += enc28j60-overlay.dtb
++dtb-$(RPI_DT_OVERLAYS) += gpio-poweroff-overlay.dtb
++dtb-$(RPI_DT_OVERLAYS) += hifiberry-amp-overlay.dtb
++dtb-$(RPI_DT_OVERLAYS) += hifiberry-dac-overlay.dtb
++dtb-$(RPI_DT_OVERLAYS) += hifiberry-dacplus-overlay.dtb
++dtb-$(RPI_DT_OVERLAYS) += hifiberry-digi-overlay.dtb
++dtb-$(RPI_DT_OVERLAYS) += hy28a-overlay.dtb
++dtb-$(RPI_DT_OVERLAYS) += hy28b-overlay.dtb
++dtb-$(RPI_DT_OVERLAYS) += i2c-rtc-overlay.dtb
++dtb-$(RPI_DT_OVERLAYS) += i2s-mmap-overlay.dtb
++dtb-$(RPI_DT_OVERLAYS) += iqaudio-dac-overlay.dtb
++dtb-$(RPI_DT_OVERLAYS) += iqaudio-dacplus-overlay.dtb
++dtb-$(RPI_DT_OVERLAYS) += lirc-rpi-overlay.dtb
++dtb-$(RPI_DT_OVERLAYS) += mcp2515-can0-overlay.dtb
++dtb-$(RPI_DT_OVERLAYS) += mcp2515-can1-overlay.dtb
++dtb-$(RPI_DT_OVERLAYS) += mmc-overlay.dtb
++dtb-$(RPI_DT_OVERLAYS) += mz61581-overlay.dtb
++dtb-$(RPI_DT_OVERLAYS) += piscreen-overlay.dtb
++dtb-$(RPI_DT_OVERLAYS) += pitft28-resistive-overlay.dtb
++dtb-$(RPI_DT_OVERLAYS) += pps-gpio-overlay.dtb
++dtb-$(RPI_DT_OVERLAYS) += rpi-dac-overlay.dtb
++dtb-$(RPI_DT_OVERLAYS) += rpi-display-overlay.dtb
++dtb-$(RPI_DT_OVERLAYS) += rpi-ft5406-overlay.dtb
++dtb-$(RPI_DT_OVERLAYS) += rpi-proto-overlay.dtb
++dtb-$(RPI_DT_OVERLAYS) += rpi-sense-overlay.dtb
++dtb-$(RPI_DT_OVERLAYS) += sdhost-overlay.dtb
++dtb-$(RPI_DT_OVERLAYS) += spi-bcm2708-overlay.dtb
++dtb-$(RPI_DT_OVERLAYS) += spi-bcm2835-overlay.dtb
++dtb-$(RPI_DT_OVERLAYS) += tinylcd35-overlay.dtb
++dtb-$(RPI_DT_OVERLAYS) += uart1-overlay.dtb
++dtb-$(RPI_DT_OVERLAYS) += vga666-overlay.dtb
++dtb-$(RPI_DT_OVERLAYS) += w1-gpio-overlay.dtb
++dtb-$(RPI_DT_OVERLAYS) += w1-gpio-pullup-overlay.dtb
++
++targets += dtbs dtbs_install
++targets += $(dtb-y)
++
++endif
++
++always := $(dtb-y)
++clean-files := *.dtb
++
++# Enable fixups to support overlays on BCM2708 platforms
++ifeq ($(RPI_DT_OVERLAYS),y)
++ DTC_FLAGS ?= -@
++endif
+diff -Nur linux-4.1.3/arch/arm/boot/dts/overlays/mcp2515-can0-overlay.dts linux-xbian-rpi/arch/arm/boot/dts/overlays/mcp2515-can0-overlay.dts
+--- linux-4.1.3/arch/arm/boot/dts/overlays/mcp2515-can0-overlay.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/boot/dts/overlays/mcp2515-can0-overlay.dts 2015-07-28 01:20:58.166151930 +0200
+@@ -0,0 +1,69 @@
++/*
++ * Device tree overlay for mcp251x/can0 on spi0.0
++ */
++
++/dts-v1/;
++/plugin/;
++
++/ {
++ compatible = "brcm,bcm2835", "brcm,bcm2836", "brcm,bcm2708", "brcm,bcm2709";
++ /* disable spi-dev for spi0.0 */
++ fragment@0 {
++ target = <&spi0>;
++ __overlay__ {
++ status = "okay";
++ spidev@0{
++ status = "disabled";
++ };
++ };
++ };
++
++ /* the interrupt pin of the can-controller */
++ fragment@1 {
++ target = <&gpio>;
++ __overlay__ {
++ can0_pins: can0_pins {
++ brcm,pins = <25>;
++ brcm,function = <0>; /* input */
++ };
++ };
++ };
++
++ /* the clock/oscillator of the can-controller */
++ fragment@2 {
++ target-path = "/clocks";
++ __overlay__ {
++ /* external oscillator of mcp2515 on SPI0.0 */
++ can0_osc: can0_osc {
++ compatible = "fixed-clock";
++ #clock-cells = <0>;
++ clock-frequency = <16000000>;
++ };
++ };
++ };
++
++ /* the spi config of the can-controller itself binding everything together */
++ fragment@3 {
++ target = <&spi0>;
++ __overlay__ {
++ /* needed to avoid dtc warning */
++ #address-cells = <1>;
++ #size-cells = <0>;
++ can0: mcp2515@0 {
++ reg = <0>;
++ compatible = "microchip,mcp2515";
++ pinctrl-names = "default";
++ pinctrl-0 = <&can0_pins>;
++ spi-max-frequency = <10000000>;
++ interrupt-parent = <&gpio>;
++ interrupts = <25 0x2>;
++ clocks = <&can0_osc>;
++ };
++ };
++ };
++ __overrides__ {
++ oscillator = <&can0_osc>,"clock-frequency:0";
++ spimaxfrequency = <&can0>,"spi-max-frequency:0";
++ interrupt = <&can0_pins>,"brcm,pins:0",<&can0>,"interrupts:0";
++ };
++};
+diff -Nur linux-4.1.3/arch/arm/boot/dts/overlays/mcp2515-can1-overlay.dts linux-xbian-rpi/arch/arm/boot/dts/overlays/mcp2515-can1-overlay.dts
+--- linux-4.1.3/arch/arm/boot/dts/overlays/mcp2515-can1-overlay.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/boot/dts/overlays/mcp2515-can1-overlay.dts 2015-07-28 01:20:58.166151930 +0200
+@@ -0,0 +1,69 @@
++/*
++ * Device tree overlay for mcp251x/can1 on spi0.1 edited by petit_miner
++ */
++
++/dts-v1/;
++/plugin/;
++
++/ {
++ compatible = "brcm,bcm2835", "brcm,bcm2836", "brcm,bcm2708", "brcm,bcm2709";
++ /* disable spi-dev for spi0.1 */
++ fragment@0 {
++ target = <&spi0>;
++ __overlay__ {
++ status = "okay";
++ spidev@1{
++ status = "disabled";
++ };
++ };
++ };
++
++ /* the interrupt pin of the can-controller */
++ fragment@1 {
++ target = <&gpio>;
++ __overlay__ {
++ can1_pins: can1_pins {
++ brcm,pins = <25>;
++ brcm,function = <0>; /* input */
++ };
++ };
++ };
++
++ /* the clock/oscillator of the can-controller */
++ fragment@2 {
++ target-path = "/clocks";
++ __overlay__ {
++ /* external oscillator of mcp2515 on spi0.1 */
++ can1_osc: can1_osc {
++ compatible = "fixed-clock";
++ #clock-cells = <0>;
++ clock-frequency = <16000000>;
++ };
++ };
++ };
++
++ /* the spi config of the can-controller itself binding everything together */
++ fragment@3 {
++ target = <&spi0>;
++ __overlay__ {
++ /* needed to avoid dtc warning */
++ #address-cells = <1>;
++ #size-cells = <0>;
++ can1: mcp2515@1 {
++ reg = <1>;
++ compatible = "microchip,mcp2515";
++ pinctrl-names = "default";
++ pinctrl-0 = <&can1_pins>;
++ spi-max-frequency = <10000000>;
++ interrupt-parent = <&gpio>;
++ interrupts = <25 0x2>;
++ clocks = <&can1_osc>;
++ };
++ };
++ };
++ __overrides__ {
++ oscillator = <&can1_osc>,"clock-frequency:0";
++ spimaxfrequency = <&can1>,"spi-max-frequency:0";
++ interrupt = <&can1_pins>,"brcm,pins:0",<&can1>,"interrupts:0";
++ };
++};
+diff -Nur linux-4.1.3/arch/arm/boot/dts/overlays/mmc-overlay.dts linux-xbian-rpi/arch/arm/boot/dts/overlays/mmc-overlay.dts
+--- linux-4.1.3/arch/arm/boot/dts/overlays/mmc-overlay.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/boot/dts/overlays/mmc-overlay.dts 2015-07-28 01:20:58.166151930 +0200
+@@ -0,0 +1,19 @@
++/dts-v1/;
++/plugin/;
++
++/{
++ compatible = "brcm,bcm2708";
++
++ fragment@0 {
++ target = <&mmc>;
++
++ __overlay__ {
++ brcm,overclock-50 = <0>;
++ };
++ };
++
++ __overrides__ {
++ overclock_50 = <&mmc>,"brcm,overclock-50:0";
++ force_pio = <&mmc>,"brcm,force-pio?";
++ };
++};
+diff -Nur linux-4.1.3/arch/arm/boot/dts/overlays/mz61581-overlay.dts linux-xbian-rpi/arch/arm/boot/dts/overlays/mz61581-overlay.dts
+--- linux-4.1.3/arch/arm/boot/dts/overlays/mz61581-overlay.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/boot/dts/overlays/mz61581-overlay.dts 2015-07-28 01:20:58.166151930 +0200
+@@ -0,0 +1,109 @@
++/*
++ * Device Tree overlay for MZ61581-PI-EXT 2014.12.28 by Tontec
++ *
++ */
++
++/dts-v1/;
++/plugin/;
++
++/ {
++ compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709";
++
++ fragment@0 {
++ target = <&spi0>;
++ __overlay__ {
++ status = "okay";
++
++ spidev@0{
++ status = "disabled";
++ };
++
++ spidev@1{
++ status = "disabled";
++ };
++ };
++ };
++
++ fragment@1 {
++ target = <&gpio>;
++ __overlay__ {
++ mz61581_pins: mz61581_pins {
++ brcm,pins = <4 15 18 25>;
++ brcm,function = <0 1 1 1>; /* in out out out */
++ };
++ };
++ };
++
++ fragment@2 {
++ target = <&spi0>;
++ __overlay__ {
++ /* needed to avoid dtc warning */
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ mz61581: mz61581@0{
++ compatible = "samsung,s6d02a1";
++ reg = <0>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&mz61581_pins>;
++
++ spi-max-frequency = <128000000>;
++ spi-cpol;
++ spi-cpha;
++
++ width = <320>;
++ height = <480>;
++ rotate = <270>;
++ bgr;
++ fps = <30>;
++ buswidth = <8>;
++
++ reset-gpios = <&gpio 15 0>;
++ dc-gpios = <&gpio 25 0>;
++ led-gpios = <&gpio 18 0>;
++
++ init = <0x10000b0 00
++ 0x1000011
++ 0x20000ff
++ 0x10000b3 0x02 0x00 0x00 0x00
++ 0x10000c0 0x13 0x3b 0x00 0x02 0x00 0x01 0x00 0x43
++ 0x10000c1 0x08 0x16 0x08 0x08
++ 0x10000c4 0x11 0x07 0x03 0x03
++ 0x10000c6 0x00
++ 0x10000c8 0x03 0x03 0x13 0x5c 0x03 0x07 0x14 0x08 0x00 0x21 0x08 0x14 0x07 0x53 0x0c 0x13 0x03 0x03 0x21 0x00
++ 0x1000035 0x00
++ 0x1000036 0xa0
++ 0x100003a 0x55
++ 0x1000044 0x00 0x01
++ 0x10000d0 0x07 0x07 0x1d 0x03
++ 0x10000d1 0x03 0x30 0x10
++ 0x10000d2 0x03 0x14 0x04
++ 0x1000029
++ 0x100002c>;
++
++ /* This is a workaround to make sure the init sequence slows down and doesn't fail */
++ debug = <3>;
++ };
++
++ mz61581_ts: mz61581_ts@1 {
++ compatible = "ti,ads7846";
++ reg = <1>;
++
++ spi-max-frequency = <2000000>;
++ interrupts = <4 2>; /* high-to-low edge triggered */
++ interrupt-parent = <&gpio>;
++ pendown-gpio = <&gpio 4 0>;
++
++ ti,x-plate-ohms = /bits/ 16 <60>;
++ ti,pressure-max = /bits/ 16 <255>;
++ };
++ };
++ };
++ __overrides__ {
++ speed = <&mz61581>, "spi-max-frequency:0";
++ rotate = <&mz61581>, "rotate:0";
++ fps = <&mz61581>, "fps:0";
++ debug = <&mz61581>, "debug:0";
++ xohms = <&mz61581_ts>,"ti,x-plate-ohms;0";
++ };
++};
+diff -Nur linux-4.1.3/arch/arm/boot/dts/overlays/piscreen-overlay.dts linux-xbian-rpi/arch/arm/boot/dts/overlays/piscreen-overlay.dts
+--- linux-4.1.3/arch/arm/boot/dts/overlays/piscreen-overlay.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/boot/dts/overlays/piscreen-overlay.dts 2015-07-28 01:20:58.166151930 +0200
+@@ -0,0 +1,96 @@
++/*
++ * Device Tree overlay for PiScreen 3.5" display shield by Ozzmaker
++ *
++ */
++
++/dts-v1/;
++/plugin/;
++
++/ {
++ compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709";
++
++ fragment@0 {
++ target = <&spi0>;
++ __overlay__ {
++ status = "okay";
++
++ spidev@0{
++ status = "disabled";
++ };
++
++ spidev@1{
++ status = "disabled";
++ };
++ };
++ };
++
++ fragment@1 {
++ target = <&gpio>;
++ __overlay__ {
++ piscreen_pins: piscreen_pins {
++ brcm,pins = <17 25 24 22>;
++ brcm,function = <0 1 1 1>; /* in out out out */
++ };
++ };
++ };
++
++ fragment@2 {
++ target = <&spi0>;
++ __overlay__ {
++ /* needed to avoid dtc warning */
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ piscreen: piscreen@0{
++ compatible = "ilitek,ili9486";
++ reg = <0>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&piscreen_pins>;
++
++ spi-max-frequency = <24000000>;
++ rotate = <270>;
++ bgr;
++ fps = <30>;
++ buswidth = <8>;
++ regwidth = <16>;
++ reset-gpios = <&gpio 25 0>;
++ dc-gpios = <&gpio 24 0>;
++ led-gpios = <&gpio 22 1>;
++ debug = <0>;
++
++ init = <0x10000b0 0x00
++ 0x1000011
++ 0x20000ff
++ 0x100003a 0x55
++ 0x1000036 0x28
++ 0x10000c2 0x44
++ 0x10000c5 0x00 0x00 0x00 0x00
++ 0x10000e0 0x0f 0x1f 0x1c 0x0c 0x0f 0x08 0x48 0x98 0x37 0x0a 0x13 0x04 0x11 0x0d 0x00
++ 0x10000e1 0x0f 0x32 0x2e 0x0b 0x0d 0x05 0x47 0x75 0x37 0x06 0x10 0x03 0x24 0x20 0x00
++ 0x10000e2 0x0f 0x32 0x2e 0x0b 0x0d 0x05 0x47 0x75 0x37 0x06 0x10 0x03 0x24 0x20 0x00
++ 0x1000011
++ 0x1000029>;
++ };
++
++ piscreen_ts: piscreen-ts@1 {
++ compatible = "ti,ads7846";
++ reg = <1>;
++
++ spi-max-frequency = <2000000>;
++ interrupts = <17 2>; /* high-to-low edge triggered */
++ interrupt-parent = <&gpio>;
++ pendown-gpio = <&gpio 17 0>;
++ ti,swap-xy;
++ ti,x-plate-ohms = /bits/ 16 <100>;
++ ti,pressure-max = /bits/ 16 <255>;
++ };
++ };
++ };
++ __overrides__ {
++ speed = <&piscreen>,"spi-max-frequency:0";
++ rotate = <&piscreen>,"rotate:0";
++ fps = <&piscreen>,"fps:0";
++ debug = <&piscreen>,"debug:0";
++ xohms = <&piscreen_ts>,"ti,x-plate-ohms;0";
++ };
++};
+diff -Nur linux-4.1.3/arch/arm/boot/dts/overlays/pitft28-resistive-overlay.dts linux-xbian-rpi/arch/arm/boot/dts/overlays/pitft28-resistive-overlay.dts
+--- linux-4.1.3/arch/arm/boot/dts/overlays/pitft28-resistive-overlay.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/boot/dts/overlays/pitft28-resistive-overlay.dts 2015-07-28 01:20:58.166151930 +0200
+@@ -0,0 +1,115 @@
++/*
++ * Device Tree overlay for Adafruit PiTFT 2.8" resistive touch screen
++ *
++ */
++
++/dts-v1/;
++/plugin/;
++
++/ {
++ compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709";
++
++ fragment@0 {
++ target = <&spi0>;
++ __overlay__ {
++ status = "okay";
++
++ spidev@0{
++ status = "disabled";
++ };
++
++ spidev@1{
++ status = "disabled";
++ };
++ };
++ };
++
++ fragment@1 {
++ target = <&gpio>;
++ __overlay__ {
++ pitft_pins: pitft_pins {
++ brcm,pins = <24 25>;
++ brcm,function = <0 1>; /* in out */
++ brcm,pull = <2 0>; /* pullup none */
++ };
++ };
++ };
++
++ fragment@2 {
++ target = <&spi0>;
++ __overlay__ {
++ /* needed to avoid dtc warning */
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ pitft: pitft@0{
++ compatible = "ilitek,ili9340";
++ reg = <0>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pitft_pins>;
++
++ spi-max-frequency = <32000000>;
++ rotate = <90>;
++ fps = <25>;
++ bgr;
++ buswidth = <8>;
++ dc-gpios = <&gpio 25 0>;
++ debug = <0>;
++ };
++
++ pitft_ts@1 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "st,stmpe610";
++ reg = <1>;
++
++ spi-max-frequency = <500000>;
++ irq-gpio = <&gpio 24 0x2>; /* IRQF_TRIGGER_FALLING */
++ interrupts = <24 2>; /* high-to-low edge triggered */
++ interrupt-parent = <&gpio>;
++ interrupt-controller;
++
++ stmpe_touchscreen {
++ compatible = "st,stmpe-ts";
++ st,sample-time = <4>;
++ st,mod-12b = <1>;
++ st,ref-sel = <0>;
++ st,adc-freq = <2>;
++ st,ave-ctrl = <3>;
++ st,touch-det-delay = <4>;
++ st,settling = <2>;
++ st,fraction-z = <7>;
++ st,i-drive = <0>;
++ };
++
++ stmpe_gpio: stmpe_gpio {
++ #gpio-cells = <2>;
++ compatible = "st,stmpe-gpio";
++ /*
++ * only GPIO2 is wired/available
++ * and it is wired to the backlight
++ */
++ st,norequest-mask = <0x7b>;
++ };
++ };
++ };
++ };
++
++ fragment@3 {
++ target-path = "/soc";
++ __overlay__ {
++ backlight {
++ compatible = "gpio-backlight";
++ gpios = <&stmpe_gpio 2 0>;
++ default-on;
++ };
++ };
++ };
++
++ __overrides__ {
++ speed = <&pitft>,"spi-max-frequency:0";
++ rotate = <&pitft>,"rotate:0";
++ fps = <&pitft>,"fps:0";
++ debug = <&pitft>,"debug:0";
++ };
++};
+diff -Nur linux-4.1.3/arch/arm/boot/dts/overlays/pps-gpio-overlay.dts linux-xbian-rpi/arch/arm/boot/dts/overlays/pps-gpio-overlay.dts
+--- linux-4.1.3/arch/arm/boot/dts/overlays/pps-gpio-overlay.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/boot/dts/overlays/pps-gpio-overlay.dts 2015-07-28 01:20:58.166151930 +0200
+@@ -0,0 +1,34 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++ compatible = "brcm,bcm2708";
++ fragment@0 {
++ target-path = "/";
++ __overlay__ {
++ pps: pps {
++ compatible = "pps-gpio";
++ pinctrl-names = "default";
++ pinctrl-0 = <&pps_pins>;
++ gpios = <&gpio 18 0>;
++ status = "okay";
++ };
++ };
++ };
++
++ fragment@1 {
++ target = <&gpio>;
++ __overlay__ {
++ pps_pins: pps_pins {
++ brcm,pins = <18>;
++ brcm,function = <0>; // in
++ brcm,pull = <0>; // off
++ };
++ };
++ };
++
++ __overrides__ {
++ gpiopin = <&pps>,"gpios:4",
++ <&pps_pins>,"brcm,pins:0";
++ };
++};
+diff -Nur linux-4.1.3/arch/arm/boot/dts/overlays/README linux-xbian-rpi/arch/arm/boot/dts/overlays/README
+--- linux-4.1.3/arch/arm/boot/dts/overlays/README 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/boot/dts/overlays/README 2015-07-28 01:20:58.166151930 +0200
+@@ -0,0 +1,566 @@
++Introduction
++============
++
++This directory contains Device Tree overlays. Device Tree makes it possible
++to support many hardware configurations with a single kernel and without the
++need to explicitly load or blacklist kernel modules. Note that this isn't a
++"pure" Device Tree configuration (c.f. MACH_BCM2835) - some on-board devices
++are still configured by the board support code, but the intention is to
++eventually reach that goal.
++
++On Raspberry Pi, Device Tree usage is controlled from /boot/config.txt. By
++default, the Raspberry Pi kernel boots with device tree enabled. You can
++completely disable DT usage (for now) by adding:
++
++ device_tree=
++
++to your config.txt, which should cause your Pi to revert to the old way of
++doing things after a reboot.
++
++In /boot you will find a .dtb for each base platform. This describes the
++hardware that is part of the Raspberry Pi board. The loader (start.elf and its
++siblings) selects the .dtb file appropriate for the platform by name, and reads
++it into memory. At this point, all of the optional interfaces (i2c, i2s, spi)
++are disabled, but they can be enabled using Device Tree parameters:
++
++ dtparam=i2c=on,i2s=on,spi=on
++
++However, this shouldn't be necessary in many use cases because loading an
++overlay that requires one of those interfaces will cause it to be enabled
++automatically, and it is advisable to only enable interfaces if they are
++needed.
++
++Configuring additional, optional hardware is done using Device Tree overlays
++(see below).
++
++raspi-config
++============
++
++The Advanced Options section of the raspi-config utility can enable and disable
++Device Tree use, as well as toggling the I2C and SPI interfaces. Note that it
++is possible to both enable an interface and blacklist the driver, if for some
++reason you should want to defer the loading.
++
++Modules
++=======
++
++As well as describing the hardware, Device Tree also gives enough information
++to allow suitable driver modules to be located and loaded, with the corollary
++that unneeded modules are not loaded. As a result it should be possible to
++remove lines from /etc/modules, and /etc/modprobe.d/raspi-blacklist.conf can
++have its contents deleted (or commented out).
++
++Using Overlays
++==============
++
++Overlays are loaded using the "dtoverlay" directive. As an example, consider the
++popular lirc-rpi module, the Linux Infrared Remote Control driver. In the
++pre-DT world this would be loaded from /etc/modules, with an explicit
++"modprobe lirc-rpi" command, or programmatically by lircd. With DT enabled,
++this becomes a line in config.txt:
++
++ dtoverlay=lirc-rpi
++
++This causes the file /boot/overlays/lirc-rpi-overlay.dtb to be loaded. By
++default it will use GPIOs 17 (out) and 18 (in), but this can be modified using
++DT parameters:
++
++ dtoverlay=lirc-rpi,gpio_out_pin=17,gpio_in_pin=13
++
++Parameters always have default values, although in some cases (e.g. "w1-gpio")
++it is necessary to provided multiple overlays in order to get the desired
++behaviour. See the list of overlays below for a description of the parameters and their defaults.
++
++The Overlay and Parameter Reference
++===================================
++
++Name: <The base DTB>
++Info: Configures the base Raspberry Pi hardware
++Load: <loaded automatically>
++Params:
++ audio Set to "on" to enable the onboard ALSA audio
++ interface (default "off")
++
++ i2c_arm Set to "on" to enable the ARM's i2c interface
++ (default "off")
++
++ i2c_vc Set to "on" to enable the i2c interface
++ usually reserved for the VideoCore processor
++ (default "off")
++
++ i2c An alias for i2c_arm
++
++ i2c_arm_baudrate Set the baudrate of the ARM's i2c interface
++ (default "100000")
++
++ i2c_vc_baudrate Set the baudrate of the VideoCore i2c interface
++ (default "100000")
++
++ i2c_baudrate An alias for i2c_arm_baudrate
++
++ i2s Set to "on" to enable the i2s interface
++ (default "off")
++
++ spi Set to "on" to enable the spi interfaces
++ (default "off")
++
++ random Set to "on" to enable the hardware random
++ number generator (default "off")
++
++ uart0 Set to "off" to disable uart0 (default "on")
++
++ watchdog Set to "on" to enable the hardware watchdog
++ (default "off")
++
++ act_led_trigger Choose which activity the LED tracks.
++ Use "heartbeat" for a nice load indicator.
++ (default "mmc")
++
++ act_led_activelow Set to "on" to invert the sense of the LED
++ (default "off")
++
++ act_led_gpio Set which GPIO to use for the activity LED
++ (in case you want to connect it to an external
++ device)
++ (default "16" on a non-Plus board, "47" on a
++ Plus or Pi 2)
++
++ pwr_led_trigger
++ pwr_led_activelow
++ pwr_led_gpio
++ As for act_led_*, but using the PWR LED.
++ Not available on Model A/B boards.
++
++ N.B. It is recommended to only enable those interfaces that are needed.
++ Leaving all interfaces enabled can lead to unwanted behaviour (i2c_vc
++ interfering with Pi Camera, I2S and SPI hogging GPIO pins, etc.)
++ Note also that i2c, i2c_arm and i2c_vc are aliases for the physical
++ interfaces i2c0 and i2c1. Use of the numeric variants is still possible
++ but deprecated because the ARM/VC assignments differ between board
++ revisions. The same board-specific mapping applies to i2c_baudrate,
++ and the other i2c baudrate parameters.
++
++
++Name: ads7846
++Info: ADS7846 Touch controller
++Load: dtoverlay=ads7846,<param>=<val>
++Params: cs SPI bus Chip Select (default 1)
++ speed SPI bus speed (default 2Mhz, max 3.25MHz)
++ penirq GPIO used for PENIRQ. REQUIRED
++ penirq_pull Set GPIO pull (default 0=none, 2=pullup)
++ swapxy Swap x and y axis
++ xmin Minimum value on the X axis (default 0)
++ ymin Minimum value on the Y axis (default 0)
++ xmax Maximum value on the X axis (default 4095)
++ ymax Maximum value on the Y axis (default 4095)
++ pmin Minimum reported pressure value (default 0)
++ pmax Maximum reported pressure value (default 65535)
++ xohms Touchpanel sensitivity (X-plate resistance)
++ (default 400)
++
++ penirq is required and usually xohms (60-100) has to be set as well.
++ Apart from that, pmax (255) and swapxy are also common.
++ The rest of the calibration can be done with xinput-calibrator.
++ See: github.com/notro/fbtft/wiki/FBTFT-on-Raspian
++ Device Tree binding document:
++ www.kernel.org/doc/Documentation/devicetree/bindings/input/ads7846.txt
++
++
++Name: bmp085_i2c-sensor
++Info: Configures the BMP085/BMP180 digital barometric pressure and temperature
++ sensors from Bosch Sensortec
++Load: dtoverlay=bmp085_i2c-sensor
++Params: <None>
++
++
++Name: dht11
++Info: Overlay for the DHT11/DHT21/DHT22 humidity/temperature sensors
++ Also sometimes found with the part number(s) AM230x.
++Load: dtoverlay=dht11,<param>=<val>
++Params: gpiopin GPIO connected to the sensor's DATA output.
++ (default 4)
++
++
++[ The ds1307-rtc overlay has been deleted. See i2c-rtc. ]
++
++
++Name: enc28j60
++Info: Overlay for the Microchip ENC28J60 Ethernet Controller (SPI)
++Load: dtoverlay=enc28j60,<param>=<val>
++Params: int_pin GPIO used for INT (default 25)
++
++ speed SPI bus speed (default 12000000)
++
++
++Name: gpio-poweroff
++Info: Drives a GPIO high or low on reboot
++Load: gpio-poweroff,<param>=<val>
++Params: gpiopin GPIO for signalling (default 26)
++
++ active_low Set if the power control device requires a
++ high->low transition to trigger a power-down.
++ Note that this will require the support of a
++ custom dt-blob.bin to prevent a power-down
++ during the boot process, and that a reboot
++ will also cause the pin to go low.
++
++
++Name: hifiberry-amp
++Info: Configures the HifiBerry Amp and Amp+ audio cards
++Load: dtoverlay=hifiberry-amp
++Params: <None>
++
++
++Name: hifiberry-dac
++Info: Configures the HifiBerry DAC audio card
++Load: dtoverlay=hifiberry-dac
++Params: <None>
++
++
++Name: hifiberry-dacplus
++Info: Configures the HifiBerry DAC+ audio card
++Load: dtoverlay=hifiberry-dacplus
++Params: <None>
++
++
++Name: hifiberry-digi
++Info: Configures the HifiBerry Digi audio card
++Load: dtoverlay=hifiberry-digi
++Params: <None>
++
++
++Name: hy28a
++Info: HY28A - 2.8" TFT LCD Display Module by HAOYU Electronics
++ Default values match Texy's display shield
++Load: dtoverlay=hy28a,<param>=<val>
++Params: speed Display SPI bus speed
++
++ rotate Display rotation {0,90,180,270}
++
++ fps Delay between frame updates
++
++ debug Debug output level {0-7}
++
++ xohms Touchpanel sensitivity (X-plate resistance)
++
++ resetgpio GPIO used to reset controller
++
++ ledgpio GPIO used to control backlight
++
++
++Name: hy28b
++Info: HY28B - 2.8" TFT LCD Display Module by HAOYU Electronics
++ Default values match Texy's display shield
++Load: dtoverlay=hy28b,<param>=<val>
++Params: speed Display SPI bus speed
++
++ rotate Display rotation {0,90,180,270}
++
++ fps Delay between frame updates
++
++ debug Debug output level {0-7}
++
++ xohms Touchpanel sensitivity (X-plate resistance)
++
++ resetgpio GPIO used to reset controller
++
++ ledgpio GPIO used to control backlight
++
++
++Name: i2c-rtc
++Info: Adds support for a number of I2C Real Time Clock devices
++Load: dtoverlay=i2c-rtc,<param>
++Params: ds1307 Select the DS1307 device
++
++ ds3231 Select the DS3231 device
++
++ mcp7941x Select the MCP7941x device
++
++ pcf2127 Select the PCF2127 device
++
++ pcf8523 Select the PCF8523 device
++
++ pcf8563 Select the PCF8563 device
++
++
++Name: i2s-mmap
++Info: Enables mmap support in the bcm2708-i2s driver
++Load: dtoverlay=i2s-mmap
++Params: <None>
++
++
++Name: iqaudio-dac
++Info: Configures the IQaudio DAC audio card
++Load: dtoverlay=iqaudio-dac
++Params: <None>
++
++
++Name: iqaudio-dacplus
++Info: Configures the IQaudio DAC+ audio card
++Load: dtoverlay=iqaudio-dacplus
++Params: <None>
++
++
++Name: lirc-rpi
++Info: Configures lirc-rpi (Linux Infrared Remote Control for Raspberry Pi)
++ Consult the module documentation for more details.
++Load: dtoverlay=lirc-rpi,<param>=<val>,...
++Params: gpio_out_pin GPIO for output (default "17")
++
++ gpio_in_pin GPIO for input (default "18")
++
++ gpio_in_pull Pull up/down/off on the input pin
++ (default "down")
++
++ sense Override the IR receive auto-detection logic:
++ "0" = force active-high
++ "1" = force active-low
++ "-1" = use auto-detection
++ (default "-1")
++
++ softcarrier Turn the software carrier "on" or "off"
++ (default "on")
++
++ invert "on" = invert the output pin (default "off")
++
++ debug "on" = enable additional debug messages
++ (default "off")
++
++
++Name: mcp2515-can0
++Info: Configures the MCP2515 CAN controller on spi0.0
++Load: dtoverlay=mcp2515-can0,<param>=<val>
++Params: oscillator Clock frequency for the CAN controller (Hz)
++
++ spimaxfrequency Maximum SPI frequence (Hz)
++
++ interrupt GPIO for interrupt signal
++
++
++Name: mcp2515-can1
++Info: Configures the MCP2515 CAN controller on spi0.1
++Load: dtoverlay=mcp2515-can1,<param>=<val>
++Params: oscillator Clock frequency for the CAN controller (Hz)
++
++ spimaxfrequency Maximum SPI frequence (Hz)
++
++ interrupt GPIO for interrupt signal
++
++
++Name: mmc
++Info: Selects the bcm2835-mmc SD/MMC driver, optionally with overclock
++Load: dtoverlay=mmc,<param>=<val>
++Params: overclock_50 Clock (in MHz) to use when the MMC framework
++ requests 50MHz
++ force_pio Disable DMA support
++
++
++Name: mz61581
++Info: MZ61581 display by Tontec
++Load: dtoverlay=mz61581,<param>=<val>
++Params: speed Display SPI bus speed
++
++ rotate Display rotation {0,90,180,270}
++
++ fps Delay between frame updates
++
++ debug Debug output level {0-7}
++
++ xohms Touchpanel sensitivity (X-plate resistance)
++
++
++[ The pcf2127-rtc overlay has been deleted. See i2c-rtc. ]
++
++
++[ The pcf8523-rtc overlay has been deleted. See i2c-rtc. ]
++
++
++[ The pcf8563-rtc overlay has been deleted. See i2c-rtc. ]
++
++
++Name: piscreen
++Info: PiScreen display by OzzMaker.com
++Load: dtoverlay=piscreen,<param>=<val>
++Params: speed Display SPI bus speed
++
++ rotate Display rotation {0,90,180,270}
++
++ fps Delay between frame updates
++
++ debug Debug output level {0-7}
++
++ xohms Touchpanel sensitivity (X-plate resistance)
++
++
++Name: pitft28-resistive
++Info: Adafruit PiTFT 2.8" resistive touch screen
++Load: dtoverlay=pitft28-resistive,<param>=<val>
++Params: speed Display SPI bus speed
++
++ rotate Display rotation {0,90,180,270}
++
++ fps Delay between frame updates
++
++ debug Debug output level {0-7}
++
++
++Name: pps-gpio
++Info: Configures the pps-gpio (pulse-per-second time signal via GPIO).
++Load: dtoverlay=pps-gpio,<param>=<val>
++Params: gpiopin Input GPIO (default "18")
++
++
++Name: rpi-dac
++Info: Configures the RPi DAC audio card
++Load: dtoverlay=rpi-dac
++Params: <None>
++
++
++Name: rpi-display
++Info: RPi-Display - 2.8" Touch Display by Watterott
++Load: dtoverlay=rpi-display,<param>=<val>
++Params: speed Display SPI bus speed
++
++ rotate Display rotation {0,90,180,270}
++
++ fps Delay between frame updates
++
++ debug Debug output level {0-7}
++
++ xohms Touchpanel sensitivity (X-plate resistance)
++
++
++Name: rpi-ft5406
++Info: Official Raspberry Pi display touchscreen
++Load: dtoverlay=rpi-ft5406
++Params: <None>
++
++
++Name: rpi-proto
++Info: Configures the RPi Proto audio card
++Load: dtoverlay=rpi-proto
++Params: <None>
++
++
++Name: rpi-sense
++Info: Raspberry Pi Sense HAT
++Load: dtoverlay=rpi-sense
++Params: <None>
++
++
++Name: sdhost
++Info: Selects the bcm2835-sdhost SD/MMC driver, optionally with overclock
++Load: dtoverlay=sdhost,<param>=<val>
++Params: overclock_50 Clock (in MHz) to use when the MMC framework
++ requests 50MHz
++
++ force_pio Disable DMA support (default off)
++
++ pio_limit Number of blocks above which to use DMA
++ (default 1)
++
++ debug Enable debug output (default off)
++
++
++Name: spi-bcm2708
++Info: Selects the bcm2708-spi SPI driver
++Load: dtoverlay=spi-bcm2708
++Params: <None>
++
++
++Name: spi-bcm2835
++Info: Selects the bcm2835-spi SPI driver
++Load: dtoverlay=spi-bcm2835
++Params: <None>
++
++
++Name: tinylcd35
++Info: 3.5" Color TFT Display by www.tinylcd.com
++ Options: Touch, RTC, keypad
++Load: dtoverlay=tinylcd35,<param>=<val>
++Params: speed Display SPI bus speed
++
++ rotate Display rotation {0,90,180,270}
++
++ fps Delay between frame updates
++
++ debug Debug output level {0-7}
++
++ touch Enable touch panel
++
++ touchgpio Touch controller IRQ GPIO
++
++ xohms Touchpanel: Resistance of X-plate in ohms
++
++ rtc-pcf PCF8563 Real Time Clock
++
++ rtc-ds DS1307 Real Time Clock
++
++ keypad Enable keypad
++
++ Examples:
++ Display with touchpanel, PCF8563 RTC and keypad:
++ dtoverlay=tinylcd35,touch,rtc-pcf,keypad
++ Old touch display:
++ dtoverlay=tinylcd35,touch,touchgpio=3
++
++
++Name: uart1
++Info: Enable uart1 in place of uart0
++Load: dtoverlay=uart1,<param>=<val>
++Params: txd1_pin GPIO pin for TXD1 (14, 32 or 40 - default 14)
++
++ rxd1_pin GPIO pin for RXD1 (15, 33 or 41 - default 15)
++
++
++Name: vga666
++Info: Overlay for the Fen Logic VGA666 board
++ This uses GPIOs 2-21 (so no I2C), and activates the output 2-3 seconds
++ after the kernel has started.
++Load: dtoverlay=vga666
++Params: <None>
++
++
++Name: w1-gpio
++Info: Configures the w1-gpio Onewire interface module.
++ Use this overlay if you *don't* need a GPIO to drive an external pullup.
++Load: dtoverlay=w1-gpio,<param>=<val>
++Params: gpiopin GPIO for I/O (default "4")
++
++ pullup Non-zero, "on", or "y" to enable the parasitic
++ power (2-wire, power-on-data) feature
++
++
++Name: w1-gpio-pullup
++Info: Configures the w1-gpio Onewire interface module.
++ Use this overlay if you *do* need a GPIO to drive an external pullup.
++Load: dtoverlay=w1-gpio-pullup,<param>=<val>,...
++Params: gpiopin GPIO for I/O (default "4")
++
++ pullup Non-zero, "on", or "y" to enable the parasitic
++ power (2-wire, power-on-data) feature
++
++ extpullup GPIO for external pullup (default "5")
++
++
++Troubleshooting
++===============
++
++If you are experiencing problems that you think are DT-related, enable DT
++diagnostic output by adding this to /boot/config.txt:
++
++ dtdebug=on
++
++and rebooting. Then run:
++
++ sudo vcdbg log msg
++
++and look for relevant messages.
++
++Further reading
++===============
++
++This is only meant to be a quick introduction to the subject of Device Tree on
++Raspberry Pi. There is a more complete explanation here:
++
++http://www.raspberrypi.org/documentation/configuration/device-tree.md
+diff -Nur linux-4.1.3/arch/arm/boot/dts/overlays/rpi-dac-overlay.dts linux-xbian-rpi/arch/arm/boot/dts/overlays/rpi-dac-overlay.dts
+--- linux-4.1.3/arch/arm/boot/dts/overlays/rpi-dac-overlay.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/boot/dts/overlays/rpi-dac-overlay.dts 2015-07-28 01:20:58.166151930 +0200
+@@ -0,0 +1,34 @@
++// Definitions for RPi DAC
++/dts-v1/;
++/plugin/;
++
++/ {
++ compatible = "brcm,bcm2708";
++
++ fragment@0 {
++ target = <&sound>;
++ __overlay__ {
++ compatible = "rpi,rpi-dac";
++ i2s-controller = <&i2s>;
++ status = "okay";
++ };
++ };
++
++ fragment@1 {
++ target = <&i2s>;
++ __overlay__ {
++ status = "okay";
++ };
++ };
++
++ fragment@2 {
++ target-path = "/";
++ __overlay__ {
++ pcm1794a-codec {
++ #sound-dai-cells = <0>;
++ compatible = "ti,pcm1794a";
++ status = "okay";
++ };
++ };
++ };
++};
+diff -Nur linux-4.1.3/arch/arm/boot/dts/overlays/rpi-display-overlay.dts linux-xbian-rpi/arch/arm/boot/dts/overlays/rpi-display-overlay.dts
+--- linux-4.1.3/arch/arm/boot/dts/overlays/rpi-display-overlay.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/boot/dts/overlays/rpi-display-overlay.dts 2015-07-28 01:20:58.166151930 +0200
+@@ -0,0 +1,82 @@
++/*
++ * Device Tree overlay for rpi-display by Watterott
++ *
++ */
++
++/dts-v1/;
++/plugin/;
++
++/ {
++ compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709";
++
++ fragment@0 {
++ target = <&spi0>;
++ __overlay__ {
++ status = "okay";
++
++ spidev@0{
++ status = "disabled";
++ };
++
++ spidev@1{
++ status = "disabled";
++ };
++ };
++ };
++
++ fragment@1 {
++ target = <&gpio>;
++ __overlay__ {
++ rpi_display_pins: rpi_display_pins {
++ brcm,pins = <18 23 24 25>;
++ brcm,function = <1 1 1 0>; /* out out out in */
++ brcm,pull = <0 0 0 2>; /* - - - up */
++ };
++ };
++ };
++
++ fragment@2 {
++ target = <&spi0>;
++ __overlay__ {
++ /* needed to avoid dtc warning */
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ rpidisplay: rpi-display@0{
++ compatible = "ilitek,ili9341";
++ reg = <0>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&rpi_display_pins>;
++
++ spi-max-frequency = <32000000>;
++ rotate = <270>;
++ bgr;
++ fps = <30>;
++ buswidth = <8>;
++ reset-gpios = <&gpio 23 0>;
++ dc-gpios = <&gpio 24 0>;
++ led-gpios = <&gpio 18 1>;
++ debug = <0>;
++ };
++
++ rpidisplay_ts: rpi-display-ts@1 {
++ compatible = "ti,ads7846";
++ reg = <1>;
++
++ spi-max-frequency = <2000000>;
++ interrupts = <25 2>; /* high-to-low edge triggered */
++ interrupt-parent = <&gpio>;
++ pendown-gpio = <&gpio 25 0>;
++ ti,x-plate-ohms = /bits/ 16 <60>;
++ ti,pressure-max = /bits/ 16 <255>;
++ };
++ };
++ };
++ __overrides__ {
++ speed = <&rpidisplay>,"spi-max-frequency:0";
++ rotate = <&rpidisplay>,"rotate:0";
++ fps = <&rpidisplay>,"fps:0";
++ debug = <&rpidisplay>,"debug:0";
++ xohms = <&rpidisplay_ts>,"ti,x-plate-ohms;0";
++ };
++};
+diff -Nur linux-4.1.3/arch/arm/boot/dts/overlays/rpi-ft5406-overlay.dts linux-xbian-rpi/arch/arm/boot/dts/overlays/rpi-ft5406-overlay.dts
+--- linux-4.1.3/arch/arm/boot/dts/overlays/rpi-ft5406-overlay.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/boot/dts/overlays/rpi-ft5406-overlay.dts 2015-07-28 01:20:58.166151930 +0200
+@@ -0,0 +1,17 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++ compatible = "brcm,bcm2708";
++
++ fragment@0 {
++ target-path = "/";
++ __overlay__ {
++ rpi_ft5406: rpi_ft5406 {
++ compatible = "rpi,rpi-ft5406";
++ firmware = <&firmware>;
++ status = "okay";
++ };
++ };
++ };
++};
+diff -Nur linux-4.1.3/arch/arm/boot/dts/overlays/rpi-proto-overlay.dts linux-xbian-rpi/arch/arm/boot/dts/overlays/rpi-proto-overlay.dts
+--- linux-4.1.3/arch/arm/boot/dts/overlays/rpi-proto-overlay.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/boot/dts/overlays/rpi-proto-overlay.dts 2015-07-28 01:20:58.166151930 +0200
+@@ -0,0 +1,39 @@
++// Definitions for Rpi-Proto
++/dts-v1/;
++/plugin/;
++
++/ {
++ compatible = "brcm,bcm2708";
++
++ fragment@0 {
++ target = <&sound>;
++ __overlay__ {
++ compatible = "rpi,rpi-proto";
++ i2s-controller = <&i2s>;
++ status = "okay";
++ };
++ };
++
++ fragment@1 {
++ target = <&i2s>;
++ __overlay__ {
++ status = "okay";
++ };
++ };
++
++ fragment@2 {
++ target = <&i2c1>;
++ __overlay__ {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "okay";
++
++ wm8731@1a {
++ #sound-dai-cells = <0>;
++ compatible = "wlf,wm8731";
++ reg = <0x1a>;
++ status = "okay";
++ };
++ };
++ };
++};
+diff -Nur linux-4.1.3/arch/arm/boot/dts/overlays/rpi-sense-overlay.dts linux-xbian-rpi/arch/arm/boot/dts/overlays/rpi-sense-overlay.dts
+--- linux-4.1.3/arch/arm/boot/dts/overlays/rpi-sense-overlay.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/boot/dts/overlays/rpi-sense-overlay.dts 2015-07-28 01:20:58.166151930 +0200
+@@ -0,0 +1,47 @@
++// rpi-sense HAT
++/dts-v1/;
++/plugin/;
++
++/ {
++ compatible = "brcm,bcm2708", "brcm,bcm2709";
++
++ fragment@0 {
++ target = <&i2c1>;
++ __overlay__ {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "okay";
++
++ rpi-sense@46 {
++ compatible = "rpi,rpi-sense";
++ reg = <0x46>;
++ keys-int-gpios = <&gpio 23 1>;
++ status = "okay";
++ };
++
++ lsm9ds1-magn@1c {
++ compatible = "st,lsm9ds1-magn";
++ reg = <0x1c>;
++ status = "okay";
++ };
++
++ lsm9ds1-accel6a {
++ compatible = "st,lsm9ds1-accel";
++ reg = <0x6a>;
++ status = "okay";
++ };
++
++ lps25h-press@5c {
++ compatible = "st,lps25h-press";
++ reg = <0x5c>;
++ status = "okay";
++ };
++
++ hts221-humid@5f {
++ compatible = "st,hts221-humid";
++ reg = <0x5f>;
++ status = "okay";
++ };
++ };
++ };
++};
+diff -Nur linux-4.1.3/arch/arm/boot/dts/overlays/sdhost-overlay.dts linux-xbian-rpi/arch/arm/boot/dts/overlays/sdhost-overlay.dts
+--- linux-4.1.3/arch/arm/boot/dts/overlays/sdhost-overlay.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/boot/dts/overlays/sdhost-overlay.dts 2015-07-28 01:20:58.166151930 +0200
+@@ -0,0 +1,56 @@
++/dts-v1/;
++/plugin/;
++
++/{
++ compatible = "brcm,bcm2708";
++
++ fragment@0 {
++ target = <&soc>;
++ __overlay__ {
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ sdhost: sdhost@7e202000 {
++ compatible = "brcm,bcm2835-sdhost";
++ reg = <0x7e202000 0x100>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&sdhost_pins>;
++ interrupts = <2 24>;
++ clocks = <&clk_core>;
++ dmas = <&dma 13>,
++ <&dma 13>;
++ dma-names = "tx", "rx";
++ brcm,delay-after-stop = <0>;
++ brcm,overclock-50 = <0>;
++ brcm,pio-limit = <1>;
++ status = "okay";
++ };
++ };
++ };
++
++ fragment@1 {
++ target = <&gpio>;
++ __overlay__ {
++ sdhost_pins: sdhost_pins {
++ brcm,pins = <48 49 50 51 52 53>;
++ brcm,function = <4>; /* alt0 */
++ };
++ };
++ };
++
++ fragment@2 {
++ target = <&mmc>;
++ __overlay__ {
++ /* Find a way to disable the other driver */
++ compatible = "";
++ status = "disabled";
++ };
++ };
++
++ __overrides__ {
++ overclock_50 = <&sdhost>,"brcm,overclock-50:0";
++ force_pio = <&sdhost>,"brcm,force-pio?";
++ pio_limit = <&sdhost>,"brcm,pio-limit:0";
++ debug = <&sdhost>,"brcm,debug?";
++ };
++};
+diff -Nur linux-4.1.3/arch/arm/boot/dts/overlays/spi-bcm2708-overlay.dts linux-xbian-rpi/arch/arm/boot/dts/overlays/spi-bcm2708-overlay.dts
+--- linux-4.1.3/arch/arm/boot/dts/overlays/spi-bcm2708-overlay.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/boot/dts/overlays/spi-bcm2708-overlay.dts 2015-07-28 01:20:58.166151930 +0200
+@@ -0,0 +1,18 @@
++/*
++ * Device tree overlay for spi-bcm2835
++ */
++
++/dts-v1/;
++/plugin/;
++
++/ {
++ compatible = "brcm,bcm2835", "brcm,bcm2836", "brcm,bcm2708", "brcm,bcm2709";
++ /* setting up compatiblity to allow loading the spi-bcm2835 driver */
++ fragment@0 {
++ target = <&spi0>;
++ __overlay__ {
++ status = "okay";
++ compatible = "brcm,bcm2708-spi";
++ };
++ };
++};
+diff -Nur linux-4.1.3/arch/arm/boot/dts/overlays/spi-bcm2835-overlay.dts linux-xbian-rpi/arch/arm/boot/dts/overlays/spi-bcm2835-overlay.dts
+--- linux-4.1.3/arch/arm/boot/dts/overlays/spi-bcm2835-overlay.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/boot/dts/overlays/spi-bcm2835-overlay.dts 2015-07-28 01:20:58.166151930 +0200
+@@ -0,0 +1,18 @@
++/*
++ * Device tree overlay for spi-bcm2835
++ */
++
++/dts-v1/;
++/plugin/;
++
++/ {
++ compatible = "brcm,bcm2835", "brcm,bcm2836", "brcm,bcm2708", "brcm,bcm2709";
++ /* setting up compatiblity to allow loading the spi-bcm2835 driver */
++ fragment@0 {
++ target = <&spi0>;
++ __overlay__ {
++ status = "okay";
++ compatible = "brcm,bcm2835-spi";
++ };
++ };
++};
+diff -Nur linux-4.1.3/arch/arm/boot/dts/overlays/tinylcd35-overlay.dts linux-xbian-rpi/arch/arm/boot/dts/overlays/tinylcd35-overlay.dts
+--- linux-4.1.3/arch/arm/boot/dts/overlays/tinylcd35-overlay.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/boot/dts/overlays/tinylcd35-overlay.dts 2015-07-28 01:20:58.166151930 +0200
+@@ -0,0 +1,216 @@
++/*
++ * tinylcd35-overlay.dts
++ *
++ * -------------------------------------------------
++ * www.tinlylcd.com
++ * -------------------------------------------------
++ * Device---Driver-----BUS GPIO's
++ * display tinylcd35 spi0.0 25 24 18
++ * touch ads7846 spi0.1 5
++ * rtc ds1307 i2c1-0068
++ * rtc pcf8563 i2c1-0051
++ * keypad gpio-keys --------- 17 22 27 23 28
++ *
++ *
++ * TinyLCD.com 3.5 inch TFT
++ *
++ * Version 001
++ * 5/3/2015 -- Noralf Trønnes Initial Device tree framework
++ * 10/3/2015 -- tinylcd@gmail.com added ds1307 support.
++ *
++ */
++
++/dts-v1/;
++/plugin/;
++
++/ {
++ compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709";
++
++ fragment@0 {
++ target = <&spi0>;
++ __overlay__ {
++ status = "okay";
++
++ spidev@0{
++ status = "disabled";
++ };
++
++ spidev@1{
++ status = "disabled";
++ };
++ };
++ };
++
++ fragment@1 {
++ target = <&gpio>;
++ __overlay__ {
++ tinylcd35_pins: tinylcd35_pins {
++ brcm,pins = <25 24 18>;
++ brcm,function = <1>; /* out */
++ };
++ tinylcd35_ts_pins: tinylcd35_ts_pins {
++ brcm,pins = <5>;
++ brcm,function = <0>; /* in */
++ };
++ keypad_pins: keypad_pins {
++ brcm,pins = <4 17 22 23 27>;
++ brcm,function = <0>; /* in */
++ brcm,pull = <1>; /* down */
++ };
++ };
++ };
++
++ fragment@2 {
++ target = <&spi0>;
++ __overlay__ {
++ /* needed to avoid dtc warning */
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ tinylcd35: tinylcd35@0{
++ compatible = "neosec,tinylcd";
++ reg = <0>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&tinylcd35_pins>,
++ <&tinylcd35_ts_pins>;
++
++ spi-max-frequency = <48000000>;
++ rotate = <270>;
++ fps = <20>;
++ bgr;
++ buswidth = <8>;
++ reset-gpios = <&gpio 25 0>;
++ dc-gpios = <&gpio 24 0>;
++ led-gpios = <&gpio 18 1>;
++ debug = <0>;
++
++ init = <0x10000B0 0x80
++ 0x10000C0 0x0A 0x0A
++ 0x10000C1 0x01 0x01
++ 0x10000C2 0x33
++ 0x10000C5 0x00 0x42 0x80
++ 0x10000B1 0xD0 0x11
++ 0x10000B4 0x02
++ 0x10000B6 0x00 0x22 0x3B
++ 0x10000B7 0x07
++ 0x1000036 0x58
++ 0x10000F0 0x36 0xA5 0xD3
++ 0x10000E5 0x80
++ 0x10000E5 0x01
++ 0x10000B3 0x00
++ 0x10000E5 0x00
++ 0x10000F0 0x36 0xA5 0x53
++ 0x10000E0 0x00 0x35 0x33 0x00 0x00 0x00 0x00 0x35 0x33 0x00 0x00 0x00
++ 0x100003A 0x55
++ 0x1000011
++ 0x2000001
++ 0x1000029>;
++ };
++
++ tinylcd35_ts: tinylcd35_ts@1 {
++ compatible = "ti,ads7846";
++ reg = <1>;
++ status = "disabled";
++
++ spi-max-frequency = <2000000>;
++ interrupts = <5 2>; /* high-to-low edge triggered */
++ interrupt-parent = <&gpio>;
++ pendown-gpio = <&gpio 5 0>;
++ ti,x-plate-ohms = /bits/ 16 <100>;
++ ti,pressure-max = /bits/ 16 <255>;
++ };
++ };
++ };
++
++ /* RTC */
++
++ fragment@3 {
++ target = <&i2c1>;
++ __overlay__ {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ pcf8563: pcf8563@51 {
++ compatible = "nxp,pcf8563";
++ reg = <0x51>;
++ status = "disabled";
++ };
++ };
++ };
++
++ fragment@4 {
++ target = <&i2c1>;
++ __overlay__ {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ ds1307: ds1307@68 {
++ compatible = "maxim,ds1307";
++ reg = <0x68>;
++ status = "disabled";
++ };
++ };
++ };
++
++ /*
++ * Values for input event code is found under the
++ * 'Keys and buttons' heading in include/uapi/linux/input.h
++ */
++ fragment@5 {
++ target-path = "/soc";
++ __overlay__ {
++ keypad: keypad {
++ compatible = "gpio-keys";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&keypad_pins>;
++ status = "disabled";
++ autorepeat;
++
++ button@17 {
++ label = "GPIO KEY_UP";
++ linux,code = <103>;
++ gpios = <&gpio 17 0>;
++ };
++ button@22 {
++ label = "GPIO KEY_DOWN";
++ linux,code = <108>;
++ gpios = <&gpio 22 0>;
++ };
++ button@27 {
++ label = "GPIO KEY_LEFT";
++ linux,code = <105>;
++ gpios = <&gpio 27 0>;
++ };
++ button@23 {
++ label = "GPIO KEY_RIGHT";
++ linux,code = <106>;
++ gpios = <&gpio 23 0>;
++ };
++ button@4 {
++ label = "GPIO KEY_ENTER";
++ linux,code = <28>;
++ gpios = <&gpio 4 0>;
++ };
++ };
++ };
++ };
++
++ __overrides__ {
++ speed = <&tinylcd35>,"spi-max-frequency:0";
++ rotate = <&tinylcd35>,"rotate:0";
++ fps = <&tinylcd35>,"fps:0";
++ debug = <&tinylcd35>,"debug:0";
++ touch = <&tinylcd35_ts>,"status";
++ touchgpio = <&tinylcd35_ts_pins>,"brcm,pins:0",
++ <&tinylcd35_ts>,"interrupts:0",
++ <&tinylcd35_ts>,"pendown-gpio:4";
++ xohms = <&tinylcd35_ts>,"ti,x-plate-ohms;0";
++ rtc-pcf = <&i2c1>,"status",
++ <&pcf8563>,"status";
++ rtc-ds = <&i2c1>,"status",
++ <&ds1307>,"status";
++ keypad = <&keypad>,"status";
++ };
++};
+diff -Nur linux-4.1.3/arch/arm/boot/dts/overlays/uart1-overlay.dts linux-xbian-rpi/arch/arm/boot/dts/overlays/uart1-overlay.dts
+--- linux-4.1.3/arch/arm/boot/dts/overlays/uart1-overlay.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/boot/dts/overlays/uart1-overlay.dts 2015-07-28 01:20:58.166151930 +0200
+@@ -0,0 +1,38 @@
++/dts-v1/;
++/plugin/;
++
++/{
++ compatible = "brcm,bcm2708";
++
++ fragment@0 {
++ target = <&uart1>;
++ __overlay__ {
++ pinctrl-names = "default";
++ pinctrl-0 = <&uart1_pins>;
++ status = "okay";
++ };
++ };
++
++ fragment@1 {
++ target = <&gpio>;
++ __overlay__ {
++ uart1_pins: uart1_pins {
++ brcm,pins = <14 15>;
++ brcm,function = <2>; /* alt5 */
++ brcm,pull = <0 2>;
++ };
++ };
++ };
++
++ fragment@2 {
++ target-path = "/chosen";
++ __overlay__ {
++ bootargs = "8250.nr_uarts=1";
++ };
++ };
++
++ __overrides__ {
++ txd1_pin = <&uart1_pins>,"brcm,pins:0";
++ rxd1_pin = <&uart1_pins>,"brcm,pins:4";
++ };
++};
+diff -Nur linux-4.1.3/arch/arm/boot/dts/overlays/vga666-overlay.dts linux-xbian-rpi/arch/arm/boot/dts/overlays/vga666-overlay.dts
+--- linux-4.1.3/arch/arm/boot/dts/overlays/vga666-overlay.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/boot/dts/overlays/vga666-overlay.dts 2015-07-28 01:20:58.166151930 +0200
+@@ -0,0 +1,30 @@
++/dts-v1/;
++/plugin/;
++
++/{
++ compatible = "brcm,bcm2708";
++
++ // There is no VGA driver module, but we need a platform device
++ // node (that doesn't already use pinctrl) to hang the pinctrl
++ // reference on - leds will do
++
++ fragment@0 {
++ target = <&leds>;
++ __overlay__ {
++ pinctrl-names = "default";
++ pinctrl-0 = <&vga666_pins>;
++ };
++ };
++
++ fragment@1 {
++ target = <&gpio>;
++ __overlay__ {
++ vga666_pins: vga666_pins {
++ brcm,pins = <2 3 4 5 6 7 8 9 10 11 12
++ 13 14 15 16 17 18 19 20 21>;
++ brcm,function = <6>; /* alt2 */
++ brcm,pull = <0>; /* no pull */
++ };
++ };
++ };
++};
+diff -Nur linux-4.1.3/arch/arm/boot/dts/overlays/w1-gpio-overlay.dts linux-xbian-rpi/arch/arm/boot/dts/overlays/w1-gpio-overlay.dts
+--- linux-4.1.3/arch/arm/boot/dts/overlays/w1-gpio-overlay.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/boot/dts/overlays/w1-gpio-overlay.dts 2015-07-28 01:20:58.166151930 +0200
+@@ -0,0 +1,39 @@
++// Definitions for w1-gpio module (without external pullup)
++/dts-v1/;
++/plugin/;
++
++/ {
++ compatible = "brcm,bcm2708";
++
++ fragment@0 {
++ target-path = "/";
++ __overlay__ {
++
++ w1: onewire@0 {
++ compatible = "w1-gpio";
++ pinctrl-names = "default";
++ pinctrl-0 = <&w1_pins>;
++ gpios = <&gpio 4 0>;
++ rpi,parasitic-power = <0>;
++ status = "okay";
++ };
++ };
++ };
++
++ fragment@1 {
++ target = <&gpio>;
++ __overlay__ {
++ w1_pins: w1_pins {
++ brcm,pins = <4>;
++ brcm,function = <0>; // in (initially)
++ brcm,pull = <0>; // off
++ };
++ };
++ };
++
++ __overrides__ {
++ gpiopin = <&w1>,"gpios:4",
++ <&w1_pins>,"brcm,pins:0";
++ pullup = <&w1>,"rpi,parasitic-power:0";
++ };
++};
+diff -Nur linux-4.1.3/arch/arm/boot/dts/overlays/w1-gpio-pullup-overlay.dts linux-xbian-rpi/arch/arm/boot/dts/overlays/w1-gpio-pullup-overlay.dts
+--- linux-4.1.3/arch/arm/boot/dts/overlays/w1-gpio-pullup-overlay.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/boot/dts/overlays/w1-gpio-pullup-overlay.dts 2015-07-28 01:20:58.166151930 +0200
+@@ -0,0 +1,41 @@
++// Definitions for w1-gpio module (with external pullup)
++/dts-v1/;
++/plugin/;
++
++/ {
++ compatible = "brcm,bcm2708";
++
++ fragment@0 {
++ target-path = "/";
++ __overlay__ {
++
++ w1: onewire@0 {
++ compatible = "w1-gpio";
++ pinctrl-names = "default";
++ pinctrl-0 = <&w1_pins>;
++ gpios = <&gpio 4 0>, <&gpio 5 1>;
++ rpi,parasitic-power = <0>;
++ status = "okay";
++ };
++ };
++ };
++
++ fragment@1 {
++ target = <&gpio>;
++ __overlay__ {
++ w1_pins: w1_pins {
++ brcm,pins = <4 5>;
++ brcm,function = <0 1>; // in out
++ brcm,pull = <0 0>; // off off
++ };
++ };
++ };
++
++ __overrides__ {
++ gpiopin = <&w1>,"gpios:4",
++ <&w1_pins>,"brcm,pins:0";
++ extpullup = <&w1>,"gpios:16",
++ <&w1_pins>,"brcm,pins:4";
++ pullup = <&w1>,"rpi,parasitic-power:0";
++ };
++};
+diff -Nur linux-4.1.3/arch/arm/configs/bcm2709_defconfig linux-xbian-rpi/arch/arm/configs/bcm2709_defconfig
+--- linux-4.1.3/arch/arm/configs/bcm2709_defconfig 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/configs/bcm2709_defconfig 2015-07-28 01:20:58.166151930 +0200
+@@ -0,0 +1,1228 @@
++# CONFIG_ARM_PATCH_PHYS_VIRT is not set
++CONFIG_PHYS_OFFSET=0
++CONFIG_LOCALVERSION="-v7"
++# CONFIG_LOCALVERSION_AUTO is not set
++CONFIG_SYSVIPC=y
++CONFIG_POSIX_MQUEUE=y
++CONFIG_FHANDLE=y
++CONFIG_NO_HZ=y
++CONFIG_HIGH_RES_TIMERS=y
++CONFIG_BSD_PROCESS_ACCT=y
++CONFIG_BSD_PROCESS_ACCT_V3=y
++CONFIG_TASKSTATS=y
++CONFIG_TASK_DELAY_ACCT=y
++CONFIG_TASK_XACCT=y
++CONFIG_TASK_IO_ACCOUNTING=y
++CONFIG_IKCONFIG=m
++CONFIG_IKCONFIG_PROC=y
++CONFIG_CGROUP_FREEZER=y
++CONFIG_CGROUP_DEVICE=y
++CONFIG_CGROUP_CPUACCT=y
++CONFIG_MEMCG=y
++CONFIG_BLK_CGROUP=y
++CONFIG_NAMESPACES=y
++CONFIG_SCHED_AUTOGROUP=y
++CONFIG_BLK_DEV_INITRD=y
++CONFIG_EMBEDDED=y
++# CONFIG_COMPAT_BRK is not set
++CONFIG_PROFILING=y
++CONFIG_OPROFILE=m
++CONFIG_KPROBES=y
++CONFIG_JUMP_LABEL=y
++CONFIG_MODULES=y
++CONFIG_MODULE_UNLOAD=y
++CONFIG_MODVERSIONS=y
++CONFIG_MODULE_SRCVERSION_ALL=y
++CONFIG_BLK_DEV_THROTTLING=y
++CONFIG_PARTITION_ADVANCED=y
++CONFIG_MAC_PARTITION=y
++CONFIG_CFQ_GROUP_IOSCHED=y
++CONFIG_ARCH_BCM2709=y
++CONFIG_BCM2709_DT=y
++# CONFIG_CACHE_L2X0 is not set
++CONFIG_SMP=y
++CONFIG_HAVE_ARM_ARCH_TIMER=y
++CONFIG_VMSPLIT_2G=y
++CONFIG_PREEMPT=y
++CONFIG_AEABI=y
++CONFIG_OABI_COMPAT=y
++CONFIG_CLEANCACHE=y
++CONFIG_FRONTSWAP=y
++CONFIG_CMA=y
++CONFIG_ZSMALLOC=m
++CONFIG_PGTABLE_MAPPING=y
++CONFIG_UACCESS_WITH_MEMCPY=y
++CONFIG_SECCOMP=y
++CONFIG_ZBOOT_ROM_TEXT=0x0
++CONFIG_ZBOOT_ROM_BSS=0x0
++CONFIG_CMDLINE="console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext4 rootwait"
++CONFIG_CPU_FREQ=y
++CONFIG_CPU_FREQ_STAT=m
++CONFIG_CPU_FREQ_STAT_DETAILS=y
++CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE=y
++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
++CONFIG_CPU_FREQ_GOV_USERSPACE=y
++CONFIG_CPU_FREQ_GOV_ONDEMAND=y
++CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
++CONFIG_VFP=y
++CONFIG_NEON=y
++CONFIG_KERNEL_MODE_NEON=y
++CONFIG_BINFMT_MISC=m
++# CONFIG_SUSPEND is not set
++CONFIG_NET=y
++CONFIG_PACKET=y
++CONFIG_UNIX=y
++CONFIG_XFRM_USER=y
++CONFIG_NET_KEY=m
++CONFIG_INET=y
++CONFIG_IP_MULTICAST=y
++CONFIG_IP_ADVANCED_ROUTER=y
++CONFIG_IP_MULTIPLE_TABLES=y
++CONFIG_IP_ROUTE_MULTIPATH=y
++CONFIG_IP_ROUTE_VERBOSE=y
++CONFIG_IP_PNP=y
++CONFIG_IP_PNP_DHCP=y
++CONFIG_IP_PNP_RARP=y
++CONFIG_NET_IPIP=m
++CONFIG_NET_IPGRE_DEMUX=m
++CONFIG_NET_IPGRE=m
++CONFIG_IP_MROUTE=y
++CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
++CONFIG_IP_PIMSM_V1=y
++CONFIG_IP_PIMSM_V2=y
++CONFIG_SYN_COOKIES=y
++CONFIG_INET_AH=m
++CONFIG_INET_ESP=m
++CONFIG_INET_IPCOMP=m
++CONFIG_INET_XFRM_MODE_TRANSPORT=m
++CONFIG_INET_XFRM_MODE_TUNNEL=m
++CONFIG_INET_XFRM_MODE_BEET=m
++CONFIG_INET_LRO=m
++CONFIG_INET_DIAG=m
++CONFIG_INET6_AH=m
++CONFIG_INET6_ESP=m
++CONFIG_INET6_IPCOMP=m
++CONFIG_IPV6_TUNNEL=m
++CONFIG_IPV6_MULTIPLE_TABLES=y
++CONFIG_IPV6_MROUTE=y
++CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y
++CONFIG_IPV6_PIMSM_V2=y
++CONFIG_NETFILTER=y
++CONFIG_NF_CONNTRACK=m
++CONFIG_NF_CONNTRACK_ZONES=y
++CONFIG_NF_CONNTRACK_EVENTS=y
++CONFIG_NF_CONNTRACK_TIMESTAMP=y
++CONFIG_NF_CT_PROTO_DCCP=m
++CONFIG_NF_CT_PROTO_UDPLITE=m
++CONFIG_NF_CONNTRACK_AMANDA=m
++CONFIG_NF_CONNTRACK_FTP=m
++CONFIG_NF_CONNTRACK_H323=m
++CONFIG_NF_CONNTRACK_IRC=m
++CONFIG_NF_CONNTRACK_NETBIOS_NS=m
++CONFIG_NF_CONNTRACK_SNMP=m
++CONFIG_NF_CONNTRACK_PPTP=m
++CONFIG_NF_CONNTRACK_SANE=m
++CONFIG_NF_CONNTRACK_SIP=m
++CONFIG_NF_CONNTRACK_TFTP=m
++CONFIG_NF_CT_NETLINK=m
++CONFIG_NETFILTER_XT_SET=m
++CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
++CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
++CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
++CONFIG_NETFILTER_XT_TARGET_DSCP=m
++CONFIG_NETFILTER_XT_TARGET_HMARK=m
++CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
++CONFIG_NETFILTER_XT_TARGET_LED=m
++CONFIG_NETFILTER_XT_TARGET_LOG=m
++CONFIG_NETFILTER_XT_TARGET_MARK=m
++CONFIG_NETFILTER_XT_TARGET_NFLOG=m
++CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
++CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
++CONFIG_NETFILTER_XT_TARGET_TEE=m
++CONFIG_NETFILTER_XT_TARGET_TPROXY=m
++CONFIG_NETFILTER_XT_TARGET_TRACE=m
++CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
++CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
++CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
++CONFIG_NETFILTER_XT_MATCH_BPF=m
++CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
++CONFIG_NETFILTER_XT_MATCH_COMMENT=m
++CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
++CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m
++CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
++CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
++CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
++CONFIG_NETFILTER_XT_MATCH_CPU=m
++CONFIG_NETFILTER_XT_MATCH_DCCP=m
++CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
++CONFIG_NETFILTER_XT_MATCH_DSCP=m
++CONFIG_NETFILTER_XT_MATCH_ESP=m
++CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
++CONFIG_NETFILTER_XT_MATCH_HELPER=m
++CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
++CONFIG_NETFILTER_XT_MATCH_IPVS=m
++CONFIG_NETFILTER_XT_MATCH_LENGTH=m
++CONFIG_NETFILTER_XT_MATCH_LIMIT=m
++CONFIG_NETFILTER_XT_MATCH_MAC=m
++CONFIG_NETFILTER_XT_MATCH_MARK=m
++CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
++CONFIG_NETFILTER_XT_MATCH_NFACCT=m
++CONFIG_NETFILTER_XT_MATCH_OSF=m
++CONFIG_NETFILTER_XT_MATCH_OWNER=m
++CONFIG_NETFILTER_XT_MATCH_POLICY=m
++CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
++CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
++CONFIG_NETFILTER_XT_MATCH_QUOTA=m
++CONFIG_NETFILTER_XT_MATCH_RATEEST=m
++CONFIG_NETFILTER_XT_MATCH_REALM=m
++CONFIG_NETFILTER_XT_MATCH_RECENT=m
++CONFIG_NETFILTER_XT_MATCH_SOCKET=m
++CONFIG_NETFILTER_XT_MATCH_STATE=m
++CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
++CONFIG_NETFILTER_XT_MATCH_STRING=m
++CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
++CONFIG_NETFILTER_XT_MATCH_TIME=m
++CONFIG_NETFILTER_XT_MATCH_U32=m
++CONFIG_IP_SET=m
++CONFIG_IP_SET_BITMAP_IP=m
++CONFIG_IP_SET_BITMAP_IPMAC=m
++CONFIG_IP_SET_BITMAP_PORT=m
++CONFIG_IP_SET_HASH_IP=m
++CONFIG_IP_SET_HASH_IPPORT=m
++CONFIG_IP_SET_HASH_IPPORTIP=m
++CONFIG_IP_SET_HASH_IPPORTNET=m
++CONFIG_IP_SET_HASH_NET=m
++CONFIG_IP_SET_HASH_NETPORT=m
++CONFIG_IP_SET_HASH_NETIFACE=m
++CONFIG_IP_SET_LIST_SET=m
++CONFIG_IP_VS=m
++CONFIG_IP_VS_PROTO_TCP=y
++CONFIG_IP_VS_PROTO_UDP=y
++CONFIG_IP_VS_PROTO_ESP=y
++CONFIG_IP_VS_PROTO_AH=y
++CONFIG_IP_VS_PROTO_SCTP=y
++CONFIG_IP_VS_RR=m
++CONFIG_IP_VS_WRR=m
++CONFIG_IP_VS_LC=m
++CONFIG_IP_VS_WLC=m
++CONFIG_IP_VS_LBLC=m
++CONFIG_IP_VS_LBLCR=m
++CONFIG_IP_VS_DH=m
++CONFIG_IP_VS_SH=m
++CONFIG_IP_VS_SED=m
++CONFIG_IP_VS_NQ=m
++CONFIG_IP_VS_FTP=m
++CONFIG_IP_VS_PE_SIP=m
++CONFIG_NF_CONNTRACK_IPV4=m
++CONFIG_IP_NF_IPTABLES=m
++CONFIG_IP_NF_MATCH_AH=m
++CONFIG_IP_NF_MATCH_ECN=m
++CONFIG_IP_NF_MATCH_TTL=m
++CONFIG_IP_NF_FILTER=m
++CONFIG_IP_NF_TARGET_REJECT=m
++CONFIG_IP_NF_NAT=m
++CONFIG_IP_NF_TARGET_MASQUERADE=m
++CONFIG_IP_NF_TARGET_NETMAP=m
++CONFIG_IP_NF_TARGET_REDIRECT=m
++CONFIG_IP_NF_MANGLE=m
++CONFIG_IP_NF_TARGET_CLUSTERIP=m
++CONFIG_IP_NF_TARGET_ECN=m
++CONFIG_IP_NF_TARGET_TTL=m
++CONFIG_IP_NF_RAW=m
++CONFIG_IP_NF_ARPTABLES=m
++CONFIG_IP_NF_ARPFILTER=m
++CONFIG_IP_NF_ARP_MANGLE=m
++CONFIG_NF_CONNTRACK_IPV6=m
++CONFIG_IP6_NF_IPTABLES=m
++CONFIG_IP6_NF_MATCH_AH=m
++CONFIG_IP6_NF_MATCH_EUI64=m
++CONFIG_IP6_NF_MATCH_FRAG=m
++CONFIG_IP6_NF_MATCH_OPTS=m
++CONFIG_IP6_NF_MATCH_HL=m
++CONFIG_IP6_NF_MATCH_IPV6HEADER=m
++CONFIG_IP6_NF_MATCH_MH=m
++CONFIG_IP6_NF_MATCH_RT=m
++CONFIG_IP6_NF_TARGET_HL=m
++CONFIG_IP6_NF_FILTER=m
++CONFIG_IP6_NF_TARGET_REJECT=m
++CONFIG_IP6_NF_MANGLE=m
++CONFIG_IP6_NF_RAW=m
++CONFIG_IP6_NF_NAT=m
++CONFIG_IP6_NF_TARGET_MASQUERADE=m
++CONFIG_IP6_NF_TARGET_NPT=m
++CONFIG_BRIDGE_NF_EBTABLES=m
++CONFIG_BRIDGE_EBT_BROUTE=m
++CONFIG_BRIDGE_EBT_T_FILTER=m
++CONFIG_BRIDGE_EBT_T_NAT=m
++CONFIG_BRIDGE_EBT_802_3=m
++CONFIG_BRIDGE_EBT_AMONG=m
++CONFIG_BRIDGE_EBT_ARP=m
++CONFIG_BRIDGE_EBT_IP=m
++CONFIG_BRIDGE_EBT_IP6=m
++CONFIG_BRIDGE_EBT_LIMIT=m
++CONFIG_BRIDGE_EBT_MARK=m
++CONFIG_BRIDGE_EBT_PKTTYPE=m
++CONFIG_BRIDGE_EBT_STP=m
++CONFIG_BRIDGE_EBT_VLAN=m
++CONFIG_BRIDGE_EBT_ARPREPLY=m
++CONFIG_BRIDGE_EBT_DNAT=m
++CONFIG_BRIDGE_EBT_MARK_T=m
++CONFIG_BRIDGE_EBT_REDIRECT=m
++CONFIG_BRIDGE_EBT_SNAT=m
++CONFIG_BRIDGE_EBT_LOG=m
++CONFIG_BRIDGE_EBT_NFLOG=m
++CONFIG_SCTP_COOKIE_HMAC_SHA1=y
++CONFIG_ATM=m
++CONFIG_L2TP=m
++CONFIG_L2TP_V3=y
++CONFIG_L2TP_IP=m
++CONFIG_L2TP_ETH=m
++CONFIG_BRIDGE=m
++CONFIG_VLAN_8021Q=m
++CONFIG_VLAN_8021Q_GVRP=y
++CONFIG_ATALK=m
++CONFIG_6LOWPAN=m
++CONFIG_NET_SCHED=y
++CONFIG_NET_SCH_CBQ=m
++CONFIG_NET_SCH_HTB=m
++CONFIG_NET_SCH_HFSC=m
++CONFIG_NET_SCH_PRIO=m
++CONFIG_NET_SCH_MULTIQ=m
++CONFIG_NET_SCH_RED=m
++CONFIG_NET_SCH_SFB=m
++CONFIG_NET_SCH_SFQ=m
++CONFIG_NET_SCH_TEQL=m
++CONFIG_NET_SCH_TBF=m
++CONFIG_NET_SCH_GRED=m
++CONFIG_NET_SCH_DSMARK=m
++CONFIG_NET_SCH_NETEM=m
++CONFIG_NET_SCH_DRR=m
++CONFIG_NET_SCH_MQPRIO=m
++CONFIG_NET_SCH_CHOKE=m
++CONFIG_NET_SCH_QFQ=m
++CONFIG_NET_SCH_CODEL=m
++CONFIG_NET_SCH_FQ_CODEL=m
++CONFIG_NET_SCH_INGRESS=m
++CONFIG_NET_SCH_PLUG=m
++CONFIG_NET_CLS_BASIC=m
++CONFIG_NET_CLS_TCINDEX=m
++CONFIG_NET_CLS_ROUTE4=m
++CONFIG_NET_CLS_FW=m
++CONFIG_NET_CLS_U32=m
++CONFIG_CLS_U32_MARK=y
++CONFIG_NET_CLS_RSVP=m
++CONFIG_NET_CLS_RSVP6=m
++CONFIG_NET_CLS_FLOW=m
++CONFIG_NET_CLS_CGROUP=m
++CONFIG_NET_EMATCH=y
++CONFIG_NET_EMATCH_CMP=m
++CONFIG_NET_EMATCH_NBYTE=m
++CONFIG_NET_EMATCH_U32=m
++CONFIG_NET_EMATCH_META=m
++CONFIG_NET_EMATCH_TEXT=m
++CONFIG_NET_EMATCH_IPSET=m
++CONFIG_NET_CLS_ACT=y
++CONFIG_NET_ACT_POLICE=m
++CONFIG_NET_ACT_GACT=m
++CONFIG_GACT_PROB=y
++CONFIG_NET_ACT_MIRRED=m
++CONFIG_NET_ACT_IPT=m
++CONFIG_NET_ACT_NAT=m
++CONFIG_NET_ACT_PEDIT=m
++CONFIG_NET_ACT_SIMP=m
++CONFIG_NET_ACT_SKBEDIT=m
++CONFIG_NET_ACT_CSUM=m
++CONFIG_BATMAN_ADV=m
++CONFIG_OPENVSWITCH=m
++CONFIG_NET_PKTGEN=m
++CONFIG_HAMRADIO=y
++CONFIG_AX25=m
++CONFIG_NETROM=m
++CONFIG_ROSE=m
++CONFIG_MKISS=m
++CONFIG_6PACK=m
++CONFIG_BPQETHER=m
++CONFIG_BAYCOM_SER_FDX=m
++CONFIG_BAYCOM_SER_HDX=m
++CONFIG_YAM=m
++CONFIG_CAN=m
++CONFIG_CAN_VCAN=m
++CONFIG_CAN_MCP251X=m
++CONFIG_IRDA=m
++CONFIG_IRLAN=m
++CONFIG_IRNET=m
++CONFIG_IRCOMM=m
++CONFIG_IRDA_ULTRA=y
++CONFIG_IRDA_CACHE_LAST_LSAP=y
++CONFIG_IRDA_FAST_RR=y
++CONFIG_IRTTY_SIR=m
++CONFIG_KINGSUN_DONGLE=m
++CONFIG_KSDAZZLE_DONGLE=m
++CONFIG_KS959_DONGLE=m
++CONFIG_USB_IRDA=m
++CONFIG_SIGMATEL_FIR=m
++CONFIG_MCS_FIR=m
++CONFIG_BT=m
++CONFIG_BT_RFCOMM=m
++CONFIG_BT_RFCOMM_TTY=y
++CONFIG_BT_BNEP=m
++CONFIG_BT_BNEP_MC_FILTER=y
++CONFIG_BT_BNEP_PROTO_FILTER=y
++CONFIG_BT_HIDP=m
++CONFIG_BT_6LOWPAN=m
++CONFIG_BT_HCIBTUSB=m
++CONFIG_BT_HCIBCM203X=m
++CONFIG_BT_HCIBPA10X=m
++CONFIG_BT_HCIBFUSB=m
++CONFIG_BT_HCIVHCI=m
++CONFIG_BT_MRVL=m
++CONFIG_BT_MRVL_SDIO=m
++CONFIG_BT_ATH3K=m
++CONFIG_BT_WILINK=m
++CONFIG_MAC80211=m
++CONFIG_MAC80211_MESH=y
++CONFIG_WIMAX=m
++CONFIG_RFKILL=m
++CONFIG_RFKILL_INPUT=y
++CONFIG_NET_9P=m
++CONFIG_NFC=m
++CONFIG_NFC_PN533=m
++CONFIG_DEVTMPFS=y
++CONFIG_DEVTMPFS_MOUNT=y
++CONFIG_DMA_CMA=y
++CONFIG_CMA_SIZE_MBYTES=5
++CONFIG_ZRAM=m
++CONFIG_ZRAM_LZ4_COMPRESS=y
++CONFIG_BLK_DEV_LOOP=y
++CONFIG_BLK_DEV_CRYPTOLOOP=m
++CONFIG_BLK_DEV_DRBD=m
++CONFIG_BLK_DEV_NBD=m
++CONFIG_BLK_DEV_RAM=y
++CONFIG_CDROM_PKTCDVD=m
++CONFIG_ATA_OVER_ETH=m
++CONFIG_EEPROM_AT24=m
++CONFIG_TI_ST=m
++CONFIG_SCSI=y
++# CONFIG_SCSI_PROC_FS is not set
++CONFIG_BLK_DEV_SD=y
++CONFIG_CHR_DEV_ST=m
++CONFIG_CHR_DEV_OSST=m
++CONFIG_BLK_DEV_SR=m
++CONFIG_CHR_DEV_SG=m
++CONFIG_SCSI_ISCSI_ATTRS=y
++CONFIG_ISCSI_TCP=m
++CONFIG_ISCSI_BOOT_SYSFS=m
++CONFIG_MD=y
++CONFIG_MD_LINEAR=m
++CONFIG_MD_RAID0=m
++CONFIG_BLK_DEV_DM=m
++CONFIG_DM_CRYPT=m
++CONFIG_DM_SNAPSHOT=m
++CONFIG_DM_MIRROR=m
++CONFIG_DM_LOG_USERSPACE=m
++CONFIG_DM_RAID=m
++CONFIG_DM_ZERO=m
++CONFIG_DM_DELAY=m
++CONFIG_NETDEVICES=y
++CONFIG_BONDING=m
++CONFIG_DUMMY=m
++CONFIG_IFB=m
++CONFIG_MACVLAN=m
++CONFIG_NETCONSOLE=m
++CONFIG_TUN=m
++CONFIG_VETH=m
++CONFIG_ENC28J60=m
++CONFIG_MDIO_BITBANG=m
++CONFIG_PPP=m
++CONFIG_PPP_BSDCOMP=m
++CONFIG_PPP_DEFLATE=m
++CONFIG_PPP_FILTER=y
++CONFIG_PPP_MPPE=m
++CONFIG_PPP_MULTILINK=y
++CONFIG_PPPOATM=m
++CONFIG_PPPOE=m
++CONFIG_PPPOL2TP=m
++CONFIG_PPP_ASYNC=m
++CONFIG_PPP_SYNC_TTY=m
++CONFIG_SLIP=m
++CONFIG_SLIP_COMPRESSED=y
++CONFIG_SLIP_SMART=y
++CONFIG_USB_CATC=m
++CONFIG_USB_KAWETH=m
++CONFIG_USB_PEGASUS=m
++CONFIG_USB_RTL8150=m
++CONFIG_USB_RTL8152=m
++CONFIG_USB_USBNET=y
++CONFIG_USB_NET_AX8817X=m
++CONFIG_USB_NET_AX88179_178A=m
++CONFIG_USB_NET_CDCETHER=m
++CONFIG_USB_NET_CDC_EEM=m
++CONFIG_USB_NET_CDC_NCM=m
++CONFIG_USB_NET_HUAWEI_CDC_NCM=m
++CONFIG_USB_NET_CDC_MBIM=m
++CONFIG_USB_NET_DM9601=m
++CONFIG_USB_NET_SR9700=m
++CONFIG_USB_NET_SR9800=m
++CONFIG_USB_NET_SMSC75XX=m
++CONFIG_USB_NET_SMSC95XX=y
++CONFIG_USB_NET_GL620A=m
++CONFIG_USB_NET_NET1080=m
++CONFIG_USB_NET_PLUSB=m
++CONFIG_USB_NET_MCS7830=m
++CONFIG_USB_NET_CDC_SUBSET=m
++CONFIG_USB_ALI_M5632=y
++CONFIG_USB_AN2720=y
++CONFIG_USB_EPSON2888=y
++CONFIG_USB_KC2190=y
++CONFIG_USB_NET_ZAURUS=m
++CONFIG_USB_NET_CX82310_ETH=m
++CONFIG_USB_NET_KALMIA=m
++CONFIG_USB_NET_QMI_WWAN=m
++CONFIG_USB_HSO=m
++CONFIG_USB_NET_INT51X1=m
++CONFIG_USB_IPHETH=m
++CONFIG_USB_SIERRA_NET=m
++CONFIG_USB_VL600=m
++CONFIG_LIBERTAS_THINFIRM=m
++CONFIG_LIBERTAS_THINFIRM_USB=m
++CONFIG_AT76C50X_USB=m
++CONFIG_USB_ZD1201=m
++CONFIG_USB_NET_RNDIS_WLAN=m
++CONFIG_RTL8187=m
++CONFIG_MAC80211_HWSIM=m
++CONFIG_ATH_CARDS=m
++CONFIG_ATH9K=m
++CONFIG_ATH9K_HTC=m
++CONFIG_CARL9170=m
++CONFIG_ATH6KL=m
++CONFIG_ATH6KL_USB=m
++CONFIG_AR5523=m
++CONFIG_B43=m
++# CONFIG_B43_PHY_N is not set
++CONFIG_B43LEGACY=m
++CONFIG_BRCMFMAC=m
++CONFIG_BRCMFMAC_USB=y
++CONFIG_HOSTAP=m
++CONFIG_LIBERTAS=m
++CONFIG_LIBERTAS_USB=m
++CONFIG_LIBERTAS_SDIO=m
++CONFIG_P54_COMMON=m
++CONFIG_P54_USB=m
++CONFIG_RT2X00=m
++CONFIG_RT2500USB=m
++CONFIG_RT73USB=m
++CONFIG_RT2800USB=m
++CONFIG_RT2800USB_RT3573=y
++CONFIG_RT2800USB_RT53XX=y
++CONFIG_RT2800USB_RT55XX=y
++CONFIG_RT2800USB_UNKNOWN=y
++CONFIG_RTL8192CU=m
++CONFIG_ZD1211RW=m
++CONFIG_MWIFIEX=m
++CONFIG_MWIFIEX_SDIO=m
++CONFIG_WIMAX_I2400M_USB=m
++CONFIG_INPUT_POLLDEV=m
++# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
++CONFIG_INPUT_JOYDEV=m
++CONFIG_INPUT_EVDEV=m
++# CONFIG_KEYBOARD_ATKBD is not set
++CONFIG_KEYBOARD_GPIO=m
++# CONFIG_INPUT_MOUSE is not set
++CONFIG_INPUT_JOYSTICK=y
++CONFIG_JOYSTICK_IFORCE=m
++CONFIG_JOYSTICK_IFORCE_USB=y
++CONFIG_JOYSTICK_XPAD=m
++CONFIG_JOYSTICK_XPAD_FF=y
++CONFIG_JOYSTICK_RPISENSE=m
++CONFIG_INPUT_TOUCHSCREEN=y
++CONFIG_TOUCHSCREEN_ADS7846=m
++CONFIG_TOUCHSCREEN_EGALAX=m
++CONFIG_TOUCHSCREEN_RPI_FT5406=m
++CONFIG_TOUCHSCREEN_USB_COMPOSITE=m
++CONFIG_TOUCHSCREEN_STMPE=m
++CONFIG_INPUT_MISC=y
++CONFIG_INPUT_AD714X=m
++CONFIG_INPUT_ATI_REMOTE2=m
++CONFIG_INPUT_KEYSPAN_REMOTE=m
++CONFIG_INPUT_POWERMATE=m
++CONFIG_INPUT_YEALINK=m
++CONFIG_INPUT_CM109=m
++CONFIG_INPUT_UINPUT=m
++CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
++CONFIG_INPUT_ADXL34X=m
++CONFIG_INPUT_CMA3000=m
++CONFIG_SERIO=m
++CONFIG_SERIO_RAW=m
++CONFIG_GAMEPORT=m
++CONFIG_GAMEPORT_NS558=m
++CONFIG_GAMEPORT_L4=m
++CONFIG_DEVPTS_MULTIPLE_INSTANCES=y
++# CONFIG_LEGACY_PTYS is not set
++# CONFIG_DEVKMEM is not set
++CONFIG_SERIAL_8250=y
++# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
++CONFIG_SERIAL_8250_CONSOLE=y
++# CONFIG_SERIAL_8250_DMA is not set
++CONFIG_SERIAL_8250_NR_UARTS=1
++CONFIG_SERIAL_8250_RUNTIME_UARTS=0
++CONFIG_SERIAL_AMBA_PL011=y
++CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
++CONFIG_SERIAL_OF_PLATFORM=y
++CONFIG_TTY_PRINTK=y
++CONFIG_HW_RANDOM=y
++CONFIG_HW_RANDOM_BCM2835=m
++CONFIG_HW_RANDOM_BCM2708=m
++CONFIG_RAW_DRIVER=y
++CONFIG_BRCM_CHAR_DRIVERS=y
++CONFIG_BCM_VC_CMA=y
++CONFIG_BCM_VCIO=y
++CONFIG_BCM_VC_SM=y
++CONFIG_I2C=y
++CONFIG_I2C_CHARDEV=m
++CONFIG_I2C_BCM2708=m
++CONFIG_SPI=y
++CONFIG_SPI_BCM2835=m
++CONFIG_SPI_BCM2708=m
++CONFIG_SPI_SPIDEV=y
++CONFIG_PPS=m
++CONFIG_PPS_CLIENT_LDISC=m
++CONFIG_PPS_CLIENT_GPIO=m
++CONFIG_GPIO_SYSFS=y
++CONFIG_GPIO_ARIZONA=m
++CONFIG_GPIO_STMPE=y
++CONFIG_W1=m
++CONFIG_W1_MASTER_DS2490=m
++CONFIG_W1_MASTER_DS2482=m
++CONFIG_W1_MASTER_DS1WM=m
++CONFIG_W1_MASTER_GPIO=m
++CONFIG_W1_SLAVE_THERM=m
++CONFIG_W1_SLAVE_SMEM=m
++CONFIG_W1_SLAVE_DS2408=m
++CONFIG_W1_SLAVE_DS2413=m
++CONFIG_W1_SLAVE_DS2406=m
++CONFIG_W1_SLAVE_DS2423=m
++CONFIG_W1_SLAVE_DS2431=m
++CONFIG_W1_SLAVE_DS2433=m
++CONFIG_W1_SLAVE_DS2760=m
++CONFIG_W1_SLAVE_DS2780=m
++CONFIG_W1_SLAVE_DS2781=m
++CONFIG_W1_SLAVE_DS28E04=m
++CONFIG_W1_SLAVE_BQ27000=m
++CONFIG_BATTERY_DS2760=m
++CONFIG_POWER_RESET=y
++CONFIG_POWER_RESET_GPIO=y
++CONFIG_HWMON=m
++CONFIG_SENSORS_SHT21=m
++CONFIG_SENSORS_SHTC1=m
++CONFIG_THERMAL=y
++CONFIG_THERMAL_BCM2835=y
++CONFIG_WATCHDOG=y
++CONFIG_BCM2708_WDT=m
++CONFIG_BCM2835_WDT=m
++CONFIG_UCB1400_CORE=m
++CONFIG_MFD_STMPE=y
++CONFIG_STMPE_SPI=y
++CONFIG_MFD_ARIZONA_I2C=m
++CONFIG_MFD_ARIZONA_SPI=m
++CONFIG_MFD_WM5102=y
++CONFIG_MEDIA_SUPPORT=m
++CONFIG_MEDIA_CAMERA_SUPPORT=y
++CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
++CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
++CONFIG_MEDIA_RADIO_SUPPORT=y
++CONFIG_MEDIA_RC_SUPPORT=y
++CONFIG_MEDIA_CONTROLLER=y
++CONFIG_LIRC=m
++CONFIG_RC_DEVICES=y
++CONFIG_RC_ATI_REMOTE=m
++CONFIG_IR_IMON=m
++CONFIG_IR_MCEUSB=m
++CONFIG_IR_REDRAT3=m
++CONFIG_IR_STREAMZAP=m
++CONFIG_IR_IGUANA=m
++CONFIG_IR_TTUSBIR=m
++CONFIG_RC_LOOPBACK=m
++CONFIG_IR_GPIO_CIR=m
++CONFIG_MEDIA_USB_SUPPORT=y
++CONFIG_USB_VIDEO_CLASS=m
++CONFIG_USB_M5602=m
++CONFIG_USB_STV06XX=m
++CONFIG_USB_GL860=m
++CONFIG_USB_GSPCA_BENQ=m
++CONFIG_USB_GSPCA_CONEX=m
++CONFIG_USB_GSPCA_CPIA1=m
++CONFIG_USB_GSPCA_DTCS033=m
++CONFIG_USB_GSPCA_ETOMS=m
++CONFIG_USB_GSPCA_FINEPIX=m
++CONFIG_USB_GSPCA_JEILINJ=m
++CONFIG_USB_GSPCA_JL2005BCD=m
++CONFIG_USB_GSPCA_KINECT=m
++CONFIG_USB_GSPCA_KONICA=m
++CONFIG_USB_GSPCA_MARS=m
++CONFIG_USB_GSPCA_MR97310A=m
++CONFIG_USB_GSPCA_NW80X=m
++CONFIG_USB_GSPCA_OV519=m
++CONFIG_USB_GSPCA_OV534=m
++CONFIG_USB_GSPCA_OV534_9=m
++CONFIG_USB_GSPCA_PAC207=m
++CONFIG_USB_GSPCA_PAC7302=m
++CONFIG_USB_GSPCA_PAC7311=m
++CONFIG_USB_GSPCA_SE401=m
++CONFIG_USB_GSPCA_SN9C2028=m
++CONFIG_USB_GSPCA_SN9C20X=m
++CONFIG_USB_GSPCA_SONIXB=m
++CONFIG_USB_GSPCA_SONIXJ=m
++CONFIG_USB_GSPCA_SPCA500=m
++CONFIG_USB_GSPCA_SPCA501=m
++CONFIG_USB_GSPCA_SPCA505=m
++CONFIG_USB_GSPCA_SPCA506=m
++CONFIG_USB_GSPCA_SPCA508=m
++CONFIG_USB_GSPCA_SPCA561=m
++CONFIG_USB_GSPCA_SPCA1528=m
++CONFIG_USB_GSPCA_SQ905=m
++CONFIG_USB_GSPCA_SQ905C=m
++CONFIG_USB_GSPCA_SQ930X=m
++CONFIG_USB_GSPCA_STK014=m
++CONFIG_USB_GSPCA_STK1135=m
++CONFIG_USB_GSPCA_STV0680=m
++CONFIG_USB_GSPCA_SUNPLUS=m
++CONFIG_USB_GSPCA_T613=m
++CONFIG_USB_GSPCA_TOPRO=m
++CONFIG_USB_GSPCA_TV8532=m
++CONFIG_USB_GSPCA_VC032X=m
++CONFIG_USB_GSPCA_VICAM=m
++CONFIG_USB_GSPCA_XIRLINK_CIT=m
++CONFIG_USB_GSPCA_ZC3XX=m
++CONFIG_USB_PWC=m
++CONFIG_VIDEO_CPIA2=m
++CONFIG_USB_ZR364XX=m
++CONFIG_USB_STKWEBCAM=m
++CONFIG_USB_S2255=m
++CONFIG_VIDEO_USBTV=m
++CONFIG_VIDEO_PVRUSB2=m
++CONFIG_VIDEO_HDPVR=m
++CONFIG_VIDEO_USBVISION=m
++CONFIG_VIDEO_STK1160_COMMON=m
++CONFIG_VIDEO_STK1160_AC97=y
++CONFIG_VIDEO_GO7007=m
++CONFIG_VIDEO_GO7007_USB=m
++CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m
++CONFIG_VIDEO_AU0828=m
++CONFIG_VIDEO_AU0828_RC=y
++CONFIG_VIDEO_CX231XX=m
++CONFIG_VIDEO_CX231XX_ALSA=m
++CONFIG_VIDEO_CX231XX_DVB=m
++CONFIG_VIDEO_TM6000=m
++CONFIG_VIDEO_TM6000_ALSA=m
++CONFIG_VIDEO_TM6000_DVB=m
++CONFIG_DVB_USB=m
++CONFIG_DVB_USB_A800=m
++CONFIG_DVB_USB_DIBUSB_MB=m
++CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y
++CONFIG_DVB_USB_DIBUSB_MC=m
++CONFIG_DVB_USB_DIB0700=m
++CONFIG_DVB_USB_UMT_010=m
++CONFIG_DVB_USB_CXUSB=m
++CONFIG_DVB_USB_M920X=m
++CONFIG_DVB_USB_DIGITV=m
++CONFIG_DVB_USB_VP7045=m
++CONFIG_DVB_USB_VP702X=m
++CONFIG_DVB_USB_GP8PSK=m
++CONFIG_DVB_USB_NOVA_T_USB2=m
++CONFIG_DVB_USB_TTUSB2=m
++CONFIG_DVB_USB_DTT200U=m
++CONFIG_DVB_USB_OPERA1=m
++CONFIG_DVB_USB_AF9005=m
++CONFIG_DVB_USB_AF9005_REMOTE=m
++CONFIG_DVB_USB_PCTV452E=m
++CONFIG_DVB_USB_DW2102=m
++CONFIG_DVB_USB_CINERGY_T2=m
++CONFIG_DVB_USB_DTV5100=m
++CONFIG_DVB_USB_FRIIO=m
++CONFIG_DVB_USB_AZ6027=m
++CONFIG_DVB_USB_TECHNISAT_USB2=m
++CONFIG_DVB_USB_V2=m
++CONFIG_DVB_USB_AF9015=m
++CONFIG_DVB_USB_AF9035=m
++CONFIG_DVB_USB_ANYSEE=m
++CONFIG_DVB_USB_AU6610=m
++CONFIG_DVB_USB_AZ6007=m
++CONFIG_DVB_USB_CE6230=m
++CONFIG_DVB_USB_EC168=m
++CONFIG_DVB_USB_GL861=m
++CONFIG_DVB_USB_LME2510=m
++CONFIG_DVB_USB_MXL111SF=m
++CONFIG_DVB_USB_RTL28XXU=m
++CONFIG_DVB_USB_DVBSKY=m
++CONFIG_SMS_USB_DRV=m
++CONFIG_DVB_B2C2_FLEXCOP_USB=m
++CONFIG_DVB_AS102=m
++CONFIG_VIDEO_EM28XX=m
++CONFIG_VIDEO_EM28XX_V4L2=m
++CONFIG_VIDEO_EM28XX_ALSA=m
++CONFIG_VIDEO_EM28XX_DVB=m
++CONFIG_V4L_PLATFORM_DRIVERS=y
++CONFIG_VIDEO_BCM2835=y
++CONFIG_VIDEO_BCM2835_MMAL=m
++CONFIG_RADIO_SI470X=y
++CONFIG_USB_SI470X=m
++CONFIG_I2C_SI470X=m
++CONFIG_RADIO_SI4713=m
++CONFIG_I2C_SI4713=m
++CONFIG_USB_MR800=m
++CONFIG_USB_DSBR=m
++CONFIG_RADIO_SHARK=m
++CONFIG_RADIO_SHARK2=m
++CONFIG_USB_KEENE=m
++CONFIG_USB_MA901=m
++CONFIG_RADIO_TEA5764=m
++CONFIG_RADIO_SAA7706H=m
++CONFIG_RADIO_TEF6862=m
++CONFIG_RADIO_WL1273=m
++CONFIG_RADIO_WL128X=m
++# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
++CONFIG_VIDEO_UDA1342=m
++CONFIG_VIDEO_SONY_BTF_MPX=m
++CONFIG_VIDEO_TVP5150=m
++CONFIG_VIDEO_TW2804=m
++CONFIG_VIDEO_TW9903=m
++CONFIG_VIDEO_TW9906=m
++CONFIG_VIDEO_OV7640=m
++CONFIG_VIDEO_MT9V011=m
++CONFIG_FB=y
++CONFIG_FB_BCM2708=y
++CONFIG_FB_SSD1307=m
++CONFIG_FB_RPISENSE=m
++# CONFIG_BACKLIGHT_GENERIC is not set
++CONFIG_BACKLIGHT_GPIO=m
++CONFIG_FRAMEBUFFER_CONSOLE=y
++CONFIG_LOGO=y
++# CONFIG_LOGO_LINUX_MONO is not set
++# CONFIG_LOGO_LINUX_VGA16 is not set
++CONFIG_SOUND=y
++CONFIG_SND=m
++CONFIG_SND_SEQUENCER=m
++CONFIG_SND_SEQ_DUMMY=m
++CONFIG_SND_MIXER_OSS=m
++CONFIG_SND_PCM_OSS=m
++CONFIG_SND_SEQUENCER_OSS=y
++CONFIG_SND_HRTIMER=m
++CONFIG_SND_DUMMY=m
++CONFIG_SND_ALOOP=m
++CONFIG_SND_VIRMIDI=m
++CONFIG_SND_MTPAV=m
++CONFIG_SND_SERIAL_U16550=m
++CONFIG_SND_MPU401=m
++CONFIG_SND_BCM2835=m
++CONFIG_SND_USB_AUDIO=m
++CONFIG_SND_USB_UA101=m
++CONFIG_SND_USB_CAIAQ=m
++CONFIG_SND_USB_CAIAQ_INPUT=y
++CONFIG_SND_USB_6FIRE=m
++CONFIG_SND_SOC=m
++CONFIG_SND_BCM2708_SOC_I2S=m
++CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC=m
++CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS=m
++CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI=m
++CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP=m
++CONFIG_SND_BCM2708_SOC_RPI_DAC=m
++CONFIG_SND_BCM2708_SOC_RPI_PROTO=m
++CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC=m
++CONFIG_SND_SOC_WM8804_I2C=m
++CONFIG_SND_SIMPLE_CARD=m
++CONFIG_SOUND_PRIME=m
++CONFIG_HIDRAW=y
++CONFIG_HID_A4TECH=m
++CONFIG_HID_ACRUX=m
++CONFIG_HID_APPLE=m
++CONFIG_HID_BELKIN=m
++CONFIG_HID_CHERRY=m
++CONFIG_HID_CHICONY=m
++CONFIG_HID_CYPRESS=m
++CONFIG_HID_DRAGONRISE=m
++CONFIG_HID_EMS_FF=m
++CONFIG_HID_ELECOM=m
++CONFIG_HID_ELO=m
++CONFIG_HID_EZKEY=m
++CONFIG_HID_HOLTEK=m
++CONFIG_HID_KEYTOUCH=m
++CONFIG_HID_KYE=m
++CONFIG_HID_UCLOGIC=m
++CONFIG_HID_WALTOP=m
++CONFIG_HID_GYRATION=m
++CONFIG_HID_TWINHAN=m
++CONFIG_HID_KENSINGTON=m
++CONFIG_HID_LCPOWER=m
++CONFIG_HID_LOGITECH=m
++CONFIG_HID_MAGICMOUSE=m
++CONFIG_HID_MICROSOFT=m
++CONFIG_HID_MONTEREY=m
++CONFIG_HID_MULTITOUCH=m
++CONFIG_HID_NTRIG=m
++CONFIG_HID_ORTEK=m
++CONFIG_HID_PANTHERLORD=m
++CONFIG_HID_PETALYNX=m
++CONFIG_HID_PICOLCD=m
++CONFIG_HID_ROCCAT=m
++CONFIG_HID_SAMSUNG=m
++CONFIG_HID_SONY=m
++CONFIG_HID_SPEEDLINK=m
++CONFIG_HID_SUNPLUS=m
++CONFIG_HID_GREENASIA=m
++CONFIG_HID_SMARTJOYPLUS=m
++CONFIG_HID_TOPSEED=m
++CONFIG_HID_THINGM=m
++CONFIG_HID_THRUSTMASTER=m
++CONFIG_HID_WACOM=m
++CONFIG_HID_WIIMOTE=m
++CONFIG_HID_XINMO=m
++CONFIG_HID_ZEROPLUS=m
++CONFIG_HID_ZYDACRON=m
++CONFIG_HID_PID=y
++CONFIG_USB_HIDDEV=y
++CONFIG_USB=y
++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
++CONFIG_USB_MON=m
++CONFIG_USB_DWCOTG=y
++CONFIG_USB_PRINTER=m
++CONFIG_USB_STORAGE=y
++CONFIG_USB_STORAGE_REALTEK=m
++CONFIG_USB_STORAGE_DATAFAB=m
++CONFIG_USB_STORAGE_FREECOM=m
++CONFIG_USB_STORAGE_ISD200=m
++CONFIG_USB_STORAGE_USBAT=m
++CONFIG_USB_STORAGE_SDDR09=m
++CONFIG_USB_STORAGE_SDDR55=m
++CONFIG_USB_STORAGE_JUMPSHOT=m
++CONFIG_USB_STORAGE_ALAUDA=m
++CONFIG_USB_STORAGE_ONETOUCH=m
++CONFIG_USB_STORAGE_KARMA=m
++CONFIG_USB_STORAGE_CYPRESS_ATACB=m
++CONFIG_USB_STORAGE_ENE_UB6250=m
++CONFIG_USB_MDC800=m
++CONFIG_USB_MICROTEK=m
++CONFIG_USBIP_CORE=m
++CONFIG_USBIP_VHCI_HCD=m
++CONFIG_USBIP_HOST=m
++CONFIG_USB_SERIAL=m
++CONFIG_USB_SERIAL_GENERIC=y
++CONFIG_USB_SERIAL_AIRCABLE=m
++CONFIG_USB_SERIAL_ARK3116=m
++CONFIG_USB_SERIAL_BELKIN=m
++CONFIG_USB_SERIAL_CH341=m
++CONFIG_USB_SERIAL_WHITEHEAT=m
++CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
++CONFIG_USB_SERIAL_CP210X=m
++CONFIG_USB_SERIAL_CYPRESS_M8=m
++CONFIG_USB_SERIAL_EMPEG=m
++CONFIG_USB_SERIAL_FTDI_SIO=m
++CONFIG_USB_SERIAL_VISOR=m
++CONFIG_USB_SERIAL_IPAQ=m
++CONFIG_USB_SERIAL_IR=m
++CONFIG_USB_SERIAL_EDGEPORT=m
++CONFIG_USB_SERIAL_EDGEPORT_TI=m
++CONFIG_USB_SERIAL_F81232=m
++CONFIG_USB_SERIAL_GARMIN=m
++CONFIG_USB_SERIAL_IPW=m
++CONFIG_USB_SERIAL_IUU=m
++CONFIG_USB_SERIAL_KEYSPAN_PDA=m
++CONFIG_USB_SERIAL_KEYSPAN=m
++CONFIG_USB_SERIAL_KLSI=m
++CONFIG_USB_SERIAL_KOBIL_SCT=m
++CONFIG_USB_SERIAL_MCT_U232=m
++CONFIG_USB_SERIAL_METRO=m
++CONFIG_USB_SERIAL_MOS7720=m
++CONFIG_USB_SERIAL_MOS7840=m
++CONFIG_USB_SERIAL_NAVMAN=m
++CONFIG_USB_SERIAL_PL2303=m
++CONFIG_USB_SERIAL_OTI6858=m
++CONFIG_USB_SERIAL_QCAUX=m
++CONFIG_USB_SERIAL_QUALCOMM=m
++CONFIG_USB_SERIAL_SPCP8X5=m
++CONFIG_USB_SERIAL_SAFE=m
++CONFIG_USB_SERIAL_SIERRAWIRELESS=m
++CONFIG_USB_SERIAL_SYMBOL=m
++CONFIG_USB_SERIAL_TI=m
++CONFIG_USB_SERIAL_CYBERJACK=m
++CONFIG_USB_SERIAL_XIRCOM=m
++CONFIG_USB_SERIAL_OPTION=m
++CONFIG_USB_SERIAL_OMNINET=m
++CONFIG_USB_SERIAL_OPTICON=m
++CONFIG_USB_SERIAL_XSENS_MT=m
++CONFIG_USB_SERIAL_WISHBONE=m
++CONFIG_USB_SERIAL_SSU100=m
++CONFIG_USB_SERIAL_QT2=m
++CONFIG_USB_SERIAL_DEBUG=m
++CONFIG_USB_EMI62=m
++CONFIG_USB_EMI26=m
++CONFIG_USB_ADUTUX=m
++CONFIG_USB_SEVSEG=m
++CONFIG_USB_RIO500=m
++CONFIG_USB_LEGOTOWER=m
++CONFIG_USB_LCD=m
++CONFIG_USB_LED=m
++CONFIG_USB_CYPRESS_CY7C63=m
++CONFIG_USB_CYTHERM=m
++CONFIG_USB_IDMOUSE=m
++CONFIG_USB_FTDI_ELAN=m
++CONFIG_USB_APPLEDISPLAY=m
++CONFIG_USB_LD=m
++CONFIG_USB_TRANCEVIBRATOR=m
++CONFIG_USB_IOWARRIOR=m
++CONFIG_USB_TEST=m
++CONFIG_USB_ISIGHTFW=m
++CONFIG_USB_YUREX=m
++CONFIG_USB_ATM=m
++CONFIG_USB_SPEEDTOUCH=m
++CONFIG_USB_CXACRU=m
++CONFIG_USB_UEAGLEATM=m
++CONFIG_USB_XUSBATM=m
++CONFIG_MMC=y
++CONFIG_MMC_BLOCK_MINORS=32
++CONFIG_MMC_BCM2835=y
++CONFIG_MMC_BCM2835_DMA=y
++CONFIG_MMC_BCM2835_SDHOST=y
++CONFIG_MMC_SDHCI=y
++CONFIG_MMC_SDHCI_PLTFM=y
++CONFIG_MMC_SPI=m
++CONFIG_LEDS_CLASS=y
++CONFIG_LEDS_GPIO=y
++CONFIG_LEDS_TRIGGER_TIMER=y
++CONFIG_LEDS_TRIGGER_ONESHOT=y
++CONFIG_LEDS_TRIGGER_HEARTBEAT=y
++CONFIG_LEDS_TRIGGER_BACKLIGHT=y
++CONFIG_LEDS_TRIGGER_CPU=y
++CONFIG_LEDS_TRIGGER_GPIO=y
++CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
++CONFIG_LEDS_TRIGGER_TRANSIENT=m
++CONFIG_LEDS_TRIGGER_CAMERA=m
++CONFIG_LEDS_TRIGGER_INPUT=y
++CONFIG_RTC_CLASS=y
++# CONFIG_RTC_HCTOSYS is not set
++CONFIG_RTC_DRV_DS1307=m
++CONFIG_RTC_DRV_DS1374=m
++CONFIG_RTC_DRV_DS1672=m
++CONFIG_RTC_DRV_DS3232=m
++CONFIG_RTC_DRV_MAX6900=m
++CONFIG_RTC_DRV_RS5C372=m
++CONFIG_RTC_DRV_ISL1208=m
++CONFIG_RTC_DRV_ISL12022=m
++CONFIG_RTC_DRV_ISL12057=m
++CONFIG_RTC_DRV_X1205=m
++CONFIG_RTC_DRV_PCF2127=m
++CONFIG_RTC_DRV_PCF8523=m
++CONFIG_RTC_DRV_PCF8563=m
++CONFIG_RTC_DRV_PCF8583=m
++CONFIG_RTC_DRV_M41T80=m
++CONFIG_RTC_DRV_BQ32K=m
++CONFIG_RTC_DRV_S35390A=m
++CONFIG_RTC_DRV_FM3130=m
++CONFIG_RTC_DRV_RX8581=m
++CONFIG_RTC_DRV_RX8025=m
++CONFIG_RTC_DRV_EM3027=m
++CONFIG_RTC_DRV_RV3029C2=m
++CONFIG_RTC_DRV_M41T93=m
++CONFIG_RTC_DRV_M41T94=m
++CONFIG_RTC_DRV_DS1305=m
++CONFIG_RTC_DRV_DS1390=m
++CONFIG_RTC_DRV_MAX6902=m
++CONFIG_RTC_DRV_R9701=m
++CONFIG_RTC_DRV_RS5C348=m
++CONFIG_RTC_DRV_DS3234=m
++CONFIG_RTC_DRV_PCF2123=m
++CONFIG_RTC_DRV_RX4581=m
++CONFIG_DMADEVICES=y
++CONFIG_DMA_BCM2708=y
++CONFIG_UIO=m
++CONFIG_UIO_PDRV_GENIRQ=m
++CONFIG_STAGING=y
++CONFIG_PRISM2_USB=m
++CONFIG_R8712U=m
++CONFIG_R8188EU=m
++CONFIG_R8723AU=m
++CONFIG_VT6656=m
++CONFIG_SPEAKUP=m
++CONFIG_SPEAKUP_SYNTH_SOFT=m
++CONFIG_STAGING_MEDIA=y
++CONFIG_LIRC_STAGING=y
++CONFIG_LIRC_IMON=m
++CONFIG_LIRC_RPI=m
++CONFIG_LIRC_SASEM=m
++CONFIG_LIRC_SERIAL=m
++CONFIG_FB_TFT=m
++CONFIG_FB_TFT_AGM1264K_FL=m
++CONFIG_FB_TFT_BD663474=m
++CONFIG_FB_TFT_HX8340BN=m
++CONFIG_FB_TFT_HX8347D=m
++CONFIG_FB_TFT_HX8353D=m
++CONFIG_FB_TFT_ILI9320=m
++CONFIG_FB_TFT_ILI9325=m
++CONFIG_FB_TFT_ILI9340=m
++CONFIG_FB_TFT_ILI9341=m
++CONFIG_FB_TFT_ILI9481=m
++CONFIG_FB_TFT_ILI9486=m
++CONFIG_FB_TFT_PCD8544=m
++CONFIG_FB_TFT_RA8875=m
++CONFIG_FB_TFT_S6D02A1=m
++CONFIG_FB_TFT_S6D1121=m
++CONFIG_FB_TFT_SSD1289=m
++CONFIG_FB_TFT_SSD1306=m
++CONFIG_FB_TFT_SSD1331=m
++CONFIG_FB_TFT_SSD1351=m
++CONFIG_FB_TFT_ST7735R=m
++CONFIG_FB_TFT_TINYLCD=m
++CONFIG_FB_TFT_TLS8204=m
++CONFIG_FB_TFT_UC1701=m
++CONFIG_FB_TFT_UPD161704=m
++CONFIG_FB_TFT_WATTEROTT=m
++CONFIG_FB_FLEX=m
++CONFIG_FB_TFT_FBTFT_DEVICE=m
++CONFIG_MAILBOX=y
++CONFIG_BCM2708_MBOX=y
++CONFIG_BCM2835_MBOX=y
++# CONFIG_IOMMU_SUPPORT is not set
++CONFIG_EXTCON=m
++CONFIG_EXTCON_ARIZONA=m
++CONFIG_IIO=m
++CONFIG_IIO_BUFFER=y
++CONFIG_IIO_BUFFER_CB=y
++CONFIG_IIO_KFIFO_BUF=m
++CONFIG_DHT11=m
++CONFIG_RASPBERRYPI_FIRMWARE=y
++CONFIG_EXT4_FS=y
++CONFIG_EXT4_FS_POSIX_ACL=y
++CONFIG_EXT4_FS_SECURITY=y
++CONFIG_REISERFS_FS=m
++CONFIG_REISERFS_FS_XATTR=y
++CONFIG_REISERFS_FS_POSIX_ACL=y
++CONFIG_REISERFS_FS_SECURITY=y
++CONFIG_JFS_FS=m
++CONFIG_JFS_POSIX_ACL=y
++CONFIG_JFS_SECURITY=y
++CONFIG_JFS_STATISTICS=y
++CONFIG_XFS_FS=m
++CONFIG_XFS_QUOTA=y
++CONFIG_XFS_POSIX_ACL=y
++CONFIG_XFS_RT=y
++CONFIG_GFS2_FS=m
++CONFIG_OCFS2_FS=m
++CONFIG_BTRFS_FS=m
++CONFIG_BTRFS_FS_POSIX_ACL=y
++CONFIG_NILFS2_FS=m
++CONFIG_F2FS_FS=y
++CONFIG_FANOTIFY=y
++CONFIG_QFMT_V1=m
++CONFIG_QFMT_V2=m
++CONFIG_AUTOFS4_FS=y
++CONFIG_FUSE_FS=m
++CONFIG_CUSE=m
++CONFIG_FSCACHE=y
++CONFIG_FSCACHE_STATS=y
++CONFIG_FSCACHE_HISTOGRAM=y
++CONFIG_CACHEFILES=y
++CONFIG_ISO9660_FS=m
++CONFIG_JOLIET=y
++CONFIG_ZISOFS=y
++CONFIG_UDF_FS=m
++CONFIG_MSDOS_FS=y
++CONFIG_VFAT_FS=y
++CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
++CONFIG_NTFS_FS=m
++CONFIG_NTFS_RW=y
++CONFIG_TMPFS=y
++CONFIG_TMPFS_POSIX_ACL=y
++CONFIG_CONFIGFS_FS=y
++CONFIG_ECRYPT_FS=m
++CONFIG_HFS_FS=m
++CONFIG_HFSPLUS_FS=m
++CONFIG_SQUASHFS=m
++CONFIG_SQUASHFS_XATTR=y
++CONFIG_SQUASHFS_LZO=y
++CONFIG_SQUASHFS_XZ=y
++CONFIG_NFS_FS=y
++CONFIG_NFS_V3_ACL=y
++CONFIG_NFS_V4=y
++CONFIG_NFS_SWAP=y
++CONFIG_ROOT_NFS=y
++CONFIG_NFS_FSCACHE=y
++CONFIG_NFSD=m
++CONFIG_NFSD_V3_ACL=y
++CONFIG_NFSD_V4=y
++CONFIG_CIFS=m
++CONFIG_CIFS_WEAK_PW_HASH=y
++CONFIG_CIFS_UPCALL=y
++CONFIG_CIFS_XATTR=y
++CONFIG_CIFS_POSIX=y
++CONFIG_9P_FS=m
++CONFIG_9P_FS_POSIX_ACL=y
++CONFIG_NLS_DEFAULT="utf8"
++CONFIG_NLS_CODEPAGE_437=y
++CONFIG_NLS_CODEPAGE_737=m
++CONFIG_NLS_CODEPAGE_775=m
++CONFIG_NLS_CODEPAGE_850=m
++CONFIG_NLS_CODEPAGE_852=m
++CONFIG_NLS_CODEPAGE_855=m
++CONFIG_NLS_CODEPAGE_857=m
++CONFIG_NLS_CODEPAGE_860=m
++CONFIG_NLS_CODEPAGE_861=m
++CONFIG_NLS_CODEPAGE_862=m
++CONFIG_NLS_CODEPAGE_863=m
++CONFIG_NLS_CODEPAGE_864=m
++CONFIG_NLS_CODEPAGE_865=m
++CONFIG_NLS_CODEPAGE_866=m
++CONFIG_NLS_CODEPAGE_869=m
++CONFIG_NLS_CODEPAGE_936=m
++CONFIG_NLS_CODEPAGE_950=m
++CONFIG_NLS_CODEPAGE_932=m
++CONFIG_NLS_CODEPAGE_949=m
++CONFIG_NLS_CODEPAGE_874=m
++CONFIG_NLS_ISO8859_8=m
++CONFIG_NLS_CODEPAGE_1250=m
++CONFIG_NLS_CODEPAGE_1251=m
++CONFIG_NLS_ASCII=y
++CONFIG_NLS_ISO8859_1=m
++CONFIG_NLS_ISO8859_2=m
++CONFIG_NLS_ISO8859_3=m
++CONFIG_NLS_ISO8859_4=m
++CONFIG_NLS_ISO8859_5=m
++CONFIG_NLS_ISO8859_6=m
++CONFIG_NLS_ISO8859_7=m
++CONFIG_NLS_ISO8859_9=m
++CONFIG_NLS_ISO8859_13=m
++CONFIG_NLS_ISO8859_14=m
++CONFIG_NLS_ISO8859_15=m
++CONFIG_NLS_KOI8_R=m
++CONFIG_NLS_KOI8_U=m
++CONFIG_DLM=m
++CONFIG_PRINTK_TIME=y
++CONFIG_BOOT_PRINTK_DELAY=y
++CONFIG_DEBUG_MEMORY_INIT=y
++CONFIG_DETECT_HUNG_TASK=y
++CONFIG_TIMER_STATS=y
++# CONFIG_DEBUG_PREEMPT is not set
++CONFIG_IRQSOFF_TRACER=y
++CONFIG_SCHED_TRACER=y
++CONFIG_STACK_TRACER=y
++CONFIG_BLK_DEV_IO_TRACE=y
++# CONFIG_KPROBE_EVENT is not set
++CONFIG_FUNCTION_PROFILER=y
++CONFIG_KGDB=y
++CONFIG_KGDB_KDB=y
++CONFIG_KDB_KEYBOARD=y
++CONFIG_CRYPTO_USER=m
++CONFIG_CRYPTO_CBC=y
++CONFIG_CRYPTO_CTS=m
++CONFIG_CRYPTO_XTS=m
++CONFIG_CRYPTO_XCBC=m
++CONFIG_CRYPTO_TGR192=m
++CONFIG_CRYPTO_WP512=m
++CONFIG_CRYPTO_CAST5=m
++CONFIG_CRYPTO_DES=y
++# CONFIG_CRYPTO_ANSI_CPRNG is not set
++# CONFIG_CRYPTO_HW is not set
++CONFIG_ARM_CRYPTO=y
++CONFIG_CRYPTO_SHA1_ARM_NEON=m
++CONFIG_CRYPTO_SHA512_ARM_NEON=m
++CONFIG_CRYPTO_AES_ARM_BS=m
++CONFIG_CRC_ITU_T=y
++CONFIG_LIBCRC32C=y
+diff -Nur linux-4.1.3/arch/arm/configs/bcm2835_defconfig linux-xbian-rpi/arch/arm/configs/bcm2835_defconfig
+--- linux-4.1.3/arch/arm/configs/bcm2835_defconfig 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/arch/arm/configs/bcm2835_defconfig 2015-07-28 01:20:58.166151930 +0200
+@@ -1,105 +1,1076 @@
+ # CONFIG_LOCALVERSION_AUTO is not set
+ CONFIG_SYSVIPC=y
++CONFIG_POSIX_MQUEUE=y
+ CONFIG_FHANDLE=y
+ CONFIG_NO_HZ=y
+ CONFIG_HIGH_RES_TIMERS=y
+ CONFIG_BSD_PROCESS_ACCT=y
+ CONFIG_BSD_PROCESS_ACCT_V3=y
++CONFIG_TASKSTATS=y
++CONFIG_TASK_DELAY_ACCT=y
++CONFIG_TASK_XACCT=y
++CONFIG_TASK_IO_ACCOUNTING=y
++CONFIG_IKCONFIG=m
++CONFIG_IKCONFIG_PROC=y
+ CONFIG_LOG_BUF_SHIFT=18
+ CONFIG_CGROUP_FREEZER=y
+ CONFIG_CGROUP_DEVICE=y
+ CONFIG_CPUSETS=y
+ CONFIG_CGROUP_CPUACCT=y
+-CONFIG_RESOURCE_COUNTERS=y
++CONFIG_MEMCG=y
+ CONFIG_CGROUP_PERF=y
+ CONFIG_CFS_BANDWIDTH=y
+ CONFIG_RT_GROUP_SCHED=y
++CONFIG_BLK_CGROUP=y
+ CONFIG_NAMESPACES=y
+ CONFIG_SCHED_AUTOGROUP=y
+-CONFIG_RELAY=y
+ CONFIG_BLK_DEV_INITRD=y
+-CONFIG_RD_BZIP2=y
+-CONFIG_RD_LZMA=y
+-CONFIG_RD_XZ=y
+-CONFIG_RD_LZO=y
+ CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+-CONFIG_KALLSYMS_ALL=y
+ CONFIG_EMBEDDED=y
+ # CONFIG_COMPAT_BRK is not set
+ CONFIG_PROFILING=y
+-CONFIG_OPROFILE=y
++CONFIG_OPROFILE=m
++CONFIG_KPROBES=y
+ CONFIG_JUMP_LABEL=y
++CONFIG_CC_STACKPROTECTOR_REGULAR=y
++CONFIG_MODULES=y
++CONFIG_MODULE_UNLOAD=y
++CONFIG_MODVERSIONS=y
++CONFIG_MODULE_SRCVERSION_ALL=y
++CONFIG_BLK_DEV_THROTTLING=y
++CONFIG_PARTITION_ADVANCED=y
++CONFIG_MAC_PARTITION=y
++CONFIG_CFQ_GROUP_IOSCHED=y
+ CONFIG_ARCH_MULTI_V6=y
+ # CONFIG_ARCH_MULTI_V7 is not set
+ CONFIG_ARCH_BCM=y
+ CONFIG_ARCH_BCM2835=y
+-CONFIG_PREEMPT_VOLUNTARY=y
++CONFIG_PREEMPT=y
+ CONFIG_AEABI=y
++CONFIG_OABI_COMPAT=y
+ CONFIG_KSM=y
+ CONFIG_CLEANCACHE=y
++CONFIG_FRONTSWAP=y
++CONFIG_CMA=y
++CONFIG_UACCESS_WITH_MEMCPY=y
+ CONFIG_SECCOMP=y
+-CONFIG_CC_STACKPROTECTOR=y
++CONFIG_ZBOOT_ROM_TEXT=0x0
++CONFIG_ZBOOT_ROM_BSS=0x0
+ CONFIG_KEXEC=y
+ CONFIG_CRASH_DUMP=y
++CONFIG_CPU_FREQ=y
++CONFIG_CPU_FREQ_STAT=m
++CONFIG_CPU_FREQ_STAT_DETAILS=y
++CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE=y
++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
++CONFIG_CPU_FREQ_GOV_USERSPACE=y
++CONFIG_CPU_FREQ_GOV_ONDEMAND=y
++CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+ CONFIG_VFP=y
+ # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
++CONFIG_BINFMT_MISC=m
+ # CONFIG_SUSPEND is not set
+ CONFIG_NET=y
+ CONFIG_PACKET=y
+ CONFIG_UNIX=y
++CONFIG_XFRM_USER=y
++CONFIG_NET_KEY=m
+ CONFIG_INET=y
++CONFIG_IP_MULTICAST=y
++CONFIG_IP_ADVANCED_ROUTER=y
++CONFIG_IP_MULTIPLE_TABLES=y
++CONFIG_IP_ROUTE_MULTIPATH=y
++CONFIG_IP_ROUTE_VERBOSE=y
++CONFIG_IP_PNP=y
++CONFIG_IP_PNP_DHCP=y
++CONFIG_IP_PNP_RARP=y
++CONFIG_NET_IPIP=m
++CONFIG_NET_IPGRE_DEMUX=m
++CONFIG_NET_IPGRE=m
++CONFIG_IP_MROUTE=y
++CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
++CONFIG_IP_PIMSM_V1=y
++CONFIG_IP_PIMSM_V2=y
++CONFIG_SYN_COOKIES=y
++CONFIG_INET_AH=m
++CONFIG_INET_ESP=m
++CONFIG_INET_IPCOMP=m
++CONFIG_INET_XFRM_MODE_TRANSPORT=m
++CONFIG_INET_XFRM_MODE_TUNNEL=m
++CONFIG_INET_XFRM_MODE_BEET=m
++CONFIG_INET_LRO=m
++CONFIG_INET_DIAG=m
++CONFIG_INET6_AH=m
++CONFIG_INET6_ESP=m
++CONFIG_INET6_IPCOMP=m
++CONFIG_IPV6_TUNNEL=m
++CONFIG_IPV6_MULTIPLE_TABLES=y
++CONFIG_IPV6_MROUTE=y
++CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y
++CONFIG_IPV6_PIMSM_V2=y
+ CONFIG_NETWORK_SECMARK=y
+ CONFIG_NETFILTER=y
+-CONFIG_CFG80211=y
+-CONFIG_MAC80211=y
++CONFIG_NF_CONNTRACK=m
++CONFIG_NF_CONNTRACK_ZONES=y
++CONFIG_NF_CONNTRACK_EVENTS=y
++CONFIG_NF_CONNTRACK_TIMESTAMP=y
++CONFIG_NF_CT_PROTO_DCCP=m
++CONFIG_NF_CT_PROTO_UDPLITE=m
++CONFIG_NF_CONNTRACK_AMANDA=m
++CONFIG_NF_CONNTRACK_FTP=m
++CONFIG_NF_CONNTRACK_H323=m
++CONFIG_NF_CONNTRACK_IRC=m
++CONFIG_NF_CONNTRACK_NETBIOS_NS=m
++CONFIG_NF_CONNTRACK_SNMP=m
++CONFIG_NF_CONNTRACK_PPTP=m
++CONFIG_NF_CONNTRACK_SANE=m
++CONFIG_NF_CONNTRACK_SIP=m
++CONFIG_NF_CONNTRACK_TFTP=m
++CONFIG_NF_CT_NETLINK=m
++CONFIG_NETFILTER_XT_SET=m
++CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
++CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
++CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
++CONFIG_NETFILTER_XT_TARGET_DSCP=m
++CONFIG_NETFILTER_XT_TARGET_HMARK=m
++CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
++CONFIG_NETFILTER_XT_TARGET_LED=m
++CONFIG_NETFILTER_XT_TARGET_LOG=m
++CONFIG_NETFILTER_XT_TARGET_MARK=m
++CONFIG_NETFILTER_XT_TARGET_NFLOG=m
++CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
++CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
++CONFIG_NETFILTER_XT_TARGET_TEE=m
++CONFIG_NETFILTER_XT_TARGET_TPROXY=m
++CONFIG_NETFILTER_XT_TARGET_TRACE=m
++CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
++CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
++CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
++CONFIG_NETFILTER_XT_MATCH_BPF=m
++CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
++CONFIG_NETFILTER_XT_MATCH_COMMENT=m
++CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
++CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m
++CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
++CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
++CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
++CONFIG_NETFILTER_XT_MATCH_CPU=m
++CONFIG_NETFILTER_XT_MATCH_DCCP=m
++CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
++CONFIG_NETFILTER_XT_MATCH_DSCP=m
++CONFIG_NETFILTER_XT_MATCH_ESP=m
++CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
++CONFIG_NETFILTER_XT_MATCH_HELPER=m
++CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
++CONFIG_NETFILTER_XT_MATCH_IPVS=m
++CONFIG_NETFILTER_XT_MATCH_LENGTH=m
++CONFIG_NETFILTER_XT_MATCH_LIMIT=m
++CONFIG_NETFILTER_XT_MATCH_MAC=m
++CONFIG_NETFILTER_XT_MATCH_MARK=m
++CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
++CONFIG_NETFILTER_XT_MATCH_NFACCT=m
++CONFIG_NETFILTER_XT_MATCH_OSF=m
++CONFIG_NETFILTER_XT_MATCH_OWNER=m
++CONFIG_NETFILTER_XT_MATCH_POLICY=m
++CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
++CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
++CONFIG_NETFILTER_XT_MATCH_QUOTA=m
++CONFIG_NETFILTER_XT_MATCH_RATEEST=m
++CONFIG_NETFILTER_XT_MATCH_REALM=m
++CONFIG_NETFILTER_XT_MATCH_RECENT=m
++CONFIG_NETFILTER_XT_MATCH_SOCKET=m
++CONFIG_NETFILTER_XT_MATCH_STATE=m
++CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
++CONFIG_NETFILTER_XT_MATCH_STRING=m
++CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
++CONFIG_NETFILTER_XT_MATCH_TIME=m
++CONFIG_NETFILTER_XT_MATCH_U32=m
++CONFIG_IP_SET=m
++CONFIG_IP_SET_BITMAP_IP=m
++CONFIG_IP_SET_BITMAP_IPMAC=m
++CONFIG_IP_SET_BITMAP_PORT=m
++CONFIG_IP_SET_HASH_IP=m
++CONFIG_IP_SET_HASH_IPPORT=m
++CONFIG_IP_SET_HASH_IPPORTIP=m
++CONFIG_IP_SET_HASH_IPPORTNET=m
++CONFIG_IP_SET_HASH_NET=m
++CONFIG_IP_SET_HASH_NETPORT=m
++CONFIG_IP_SET_HASH_NETIFACE=m
++CONFIG_IP_SET_LIST_SET=m
++CONFIG_IP_VS=m
++CONFIG_IP_VS_PROTO_TCP=y
++CONFIG_IP_VS_PROTO_UDP=y
++CONFIG_IP_VS_PROTO_ESP=y
++CONFIG_IP_VS_PROTO_AH=y
++CONFIG_IP_VS_PROTO_SCTP=y
++CONFIG_IP_VS_RR=m
++CONFIG_IP_VS_WRR=m
++CONFIG_IP_VS_LC=m
++CONFIG_IP_VS_WLC=m
++CONFIG_IP_VS_LBLC=m
++CONFIG_IP_VS_LBLCR=m
++CONFIG_IP_VS_DH=m
++CONFIG_IP_VS_SH=m
++CONFIG_IP_VS_SED=m
++CONFIG_IP_VS_NQ=m
++CONFIG_IP_VS_FTP=m
++CONFIG_IP_VS_PE_SIP=m
++CONFIG_NF_CONNTRACK_IPV4=m
++CONFIG_IP_NF_IPTABLES=m
++CONFIG_IP_NF_MATCH_AH=m
++CONFIG_IP_NF_MATCH_ECN=m
++CONFIG_IP_NF_MATCH_TTL=m
++CONFIG_IP_NF_FILTER=m
++CONFIG_IP_NF_TARGET_REJECT=m
++CONFIG_IP_NF_NAT=m
++CONFIG_IP_NF_TARGET_MASQUERADE=m
++CONFIG_IP_NF_TARGET_NETMAP=m
++CONFIG_IP_NF_TARGET_REDIRECT=m
++CONFIG_IP_NF_MANGLE=m
++CONFIG_IP_NF_TARGET_CLUSTERIP=m
++CONFIG_IP_NF_TARGET_ECN=m
++CONFIG_IP_NF_TARGET_TTL=m
++CONFIG_IP_NF_RAW=m
++CONFIG_IP_NF_ARPTABLES=m
++CONFIG_IP_NF_ARPFILTER=m
++CONFIG_IP_NF_ARP_MANGLE=m
++CONFIG_NF_CONNTRACK_IPV6=m
++CONFIG_IP6_NF_IPTABLES=m
++CONFIG_IP6_NF_MATCH_AH=m
++CONFIG_IP6_NF_MATCH_EUI64=m
++CONFIG_IP6_NF_MATCH_FRAG=m
++CONFIG_IP6_NF_MATCH_OPTS=m
++CONFIG_IP6_NF_MATCH_HL=m
++CONFIG_IP6_NF_MATCH_IPV6HEADER=m
++CONFIG_IP6_NF_MATCH_MH=m
++CONFIG_IP6_NF_MATCH_RT=m
++CONFIG_IP6_NF_TARGET_HL=m
++CONFIG_IP6_NF_FILTER=m
++CONFIG_IP6_NF_TARGET_REJECT=m
++CONFIG_IP6_NF_MANGLE=m
++CONFIG_IP6_NF_RAW=m
++CONFIG_IP6_NF_NAT=m
++CONFIG_IP6_NF_TARGET_MASQUERADE=m
++CONFIG_IP6_NF_TARGET_NPT=m
++CONFIG_BRIDGE_NF_EBTABLES=m
++CONFIG_BRIDGE_EBT_BROUTE=m
++CONFIG_BRIDGE_EBT_T_FILTER=m
++CONFIG_BRIDGE_EBT_T_NAT=m
++CONFIG_BRIDGE_EBT_802_3=m
++CONFIG_BRIDGE_EBT_AMONG=m
++CONFIG_BRIDGE_EBT_ARP=m
++CONFIG_BRIDGE_EBT_IP=m
++CONFIG_BRIDGE_EBT_IP6=m
++CONFIG_BRIDGE_EBT_LIMIT=m
++CONFIG_BRIDGE_EBT_MARK=m
++CONFIG_BRIDGE_EBT_PKTTYPE=m
++CONFIG_BRIDGE_EBT_STP=m
++CONFIG_BRIDGE_EBT_VLAN=m
++CONFIG_BRIDGE_EBT_ARPREPLY=m
++CONFIG_BRIDGE_EBT_DNAT=m
++CONFIG_BRIDGE_EBT_MARK_T=m
++CONFIG_BRIDGE_EBT_REDIRECT=m
++CONFIG_BRIDGE_EBT_SNAT=m
++CONFIG_BRIDGE_EBT_LOG=m
++CONFIG_BRIDGE_EBT_NFLOG=m
++CONFIG_SCTP_COOKIE_HMAC_SHA1=y
++CONFIG_ATM=m
++CONFIG_L2TP=m
++CONFIG_L2TP_V3=y
++CONFIG_L2TP_IP=m
++CONFIG_L2TP_ETH=m
++CONFIG_BRIDGE=m
++CONFIG_VLAN_8021Q=m
++CONFIG_VLAN_8021Q_GVRP=y
++CONFIG_ATALK=m
++CONFIG_6LOWPAN=m
++CONFIG_NET_SCHED=y
++CONFIG_NET_SCH_CBQ=m
++CONFIG_NET_SCH_HTB=m
++CONFIG_NET_SCH_HFSC=m
++CONFIG_NET_SCH_PRIO=m
++CONFIG_NET_SCH_MULTIQ=m
++CONFIG_NET_SCH_RED=m
++CONFIG_NET_SCH_SFB=m
++CONFIG_NET_SCH_SFQ=m
++CONFIG_NET_SCH_TEQL=m
++CONFIG_NET_SCH_TBF=m
++CONFIG_NET_SCH_GRED=m
++CONFIG_NET_SCH_DSMARK=m
++CONFIG_NET_SCH_NETEM=m
++CONFIG_NET_SCH_DRR=m
++CONFIG_NET_SCH_MQPRIO=m
++CONFIG_NET_SCH_CHOKE=m
++CONFIG_NET_SCH_QFQ=m
++CONFIG_NET_SCH_CODEL=m
++CONFIG_NET_SCH_FQ_CODEL=m
++CONFIG_NET_SCH_INGRESS=m
++CONFIG_NET_SCH_PLUG=m
++CONFIG_NET_CLS_BASIC=m
++CONFIG_NET_CLS_TCINDEX=m
++CONFIG_NET_CLS_ROUTE4=m
++CONFIG_NET_CLS_FW=m
++CONFIG_NET_CLS_U32=m
++CONFIG_CLS_U32_MARK=y
++CONFIG_NET_CLS_RSVP=m
++CONFIG_NET_CLS_RSVP6=m
++CONFIG_NET_CLS_FLOW=m
++CONFIG_NET_CLS_CGROUP=m
++CONFIG_NET_EMATCH=y
++CONFIG_NET_EMATCH_CMP=m
++CONFIG_NET_EMATCH_NBYTE=m
++CONFIG_NET_EMATCH_U32=m
++CONFIG_NET_EMATCH_META=m
++CONFIG_NET_EMATCH_TEXT=m
++CONFIG_NET_EMATCH_IPSET=m
++CONFIG_NET_CLS_ACT=y
++CONFIG_NET_ACT_POLICE=m
++CONFIG_NET_ACT_GACT=m
++CONFIG_GACT_PROB=y
++CONFIG_NET_ACT_MIRRED=m
++CONFIG_NET_ACT_IPT=m
++CONFIG_NET_ACT_NAT=m
++CONFIG_NET_ACT_PEDIT=m
++CONFIG_NET_ACT_SIMP=m
++CONFIG_NET_ACT_SKBEDIT=m
++CONFIG_NET_ACT_CSUM=m
++CONFIG_BATMAN_ADV=m
++CONFIG_OPENVSWITCH=m
++CONFIG_NET_PKTGEN=m
++CONFIG_HAMRADIO=y
++CONFIG_AX25=m
++CONFIG_NETROM=m
++CONFIG_ROSE=m
++CONFIG_MKISS=m
++CONFIG_6PACK=m
++CONFIG_BPQETHER=m
++CONFIG_BAYCOM_SER_FDX=m
++CONFIG_BAYCOM_SER_HDX=m
++CONFIG_YAM=m
++CONFIG_CAN=m
++CONFIG_CAN_VCAN=m
++CONFIG_CAN_MCP251X=m
++CONFIG_IRDA=m
++CONFIG_IRLAN=m
++CONFIG_IRNET=m
++CONFIG_IRCOMM=m
++CONFIG_IRDA_ULTRA=y
++CONFIG_IRDA_CACHE_LAST_LSAP=y
++CONFIG_IRDA_FAST_RR=y
++CONFIG_IRTTY_SIR=m
++CONFIG_KINGSUN_DONGLE=m
++CONFIG_KSDAZZLE_DONGLE=m
++CONFIG_KS959_DONGLE=m
++CONFIG_USB_IRDA=m
++CONFIG_SIGMATEL_FIR=m
++CONFIG_MCS_FIR=m
++CONFIG_BT=m
++CONFIG_BT_RFCOMM=m
++CONFIG_BT_RFCOMM_TTY=y
++CONFIG_BT_BNEP=m
++CONFIG_BT_BNEP_MC_FILTER=y
++CONFIG_BT_BNEP_PROTO_FILTER=y
++CONFIG_BT_HIDP=m
++CONFIG_BT_6LOWPAN=m
++CONFIG_BT_HCIBTUSB=m
++CONFIG_BT_HCIBCM203X=m
++CONFIG_BT_HCIBPA10X=m
++CONFIG_BT_HCIBFUSB=m
++CONFIG_BT_HCIVHCI=m
++CONFIG_BT_MRVL=m
++CONFIG_BT_MRVL_SDIO=m
++CONFIG_BT_ATH3K=m
++CONFIG_BT_WILINK=m
++CONFIG_MAC80211=m
++CONFIG_MAC80211_MESH=y
++CONFIG_WIMAX=m
++CONFIG_RFKILL=m
++CONFIG_RFKILL_INPUT=y
++CONFIG_NET_9P=m
++CONFIG_NFC=m
++CONFIG_NFC_PN533=m
+ CONFIG_DEVTMPFS=y
+ CONFIG_DEVTMPFS_MOUNT=y
+ # CONFIG_STANDALONE is not set
++CONFIG_DMA_CMA=y
++CONFIG_CMA_SIZE_MBYTES=5
++CONFIG_BLK_DEV_LOOP=y
++CONFIG_BLK_DEV_CRYPTOLOOP=m
++CONFIG_BLK_DEV_DRBD=m
++CONFIG_BLK_DEV_NBD=m
++CONFIG_BLK_DEV_RAM=y
++CONFIG_CDROM_PKTCDVD=m
++CONFIG_ATA_OVER_ETH=m
++CONFIG_EEPROM_AT24=m
++CONFIG_TI_ST=m
+ CONFIG_SCSI=y
++# CONFIG_SCSI_PROC_FS is not set
+ CONFIG_BLK_DEV_SD=y
+-CONFIG_SCSI_MULTI_LUN=y
++CONFIG_CHR_DEV_ST=m
++CONFIG_CHR_DEV_OSST=m
++CONFIG_BLK_DEV_SR=m
++CONFIG_CHR_DEV_SG=m
+ CONFIG_SCSI_CONSTANTS=y
+ CONFIG_SCSI_SCAN_ASYNC=y
++CONFIG_SCSI_ISCSI_ATTRS=y
++CONFIG_ISCSI_TCP=m
++CONFIG_ISCSI_BOOT_SYSFS=m
++CONFIG_MD=y
++CONFIG_MD_LINEAR=m
++CONFIG_MD_RAID0=m
++CONFIG_BLK_DEV_DM=m
++CONFIG_DM_CRYPT=m
++CONFIG_DM_SNAPSHOT=m
++CONFIG_DM_MIRROR=m
++CONFIG_DM_LOG_USERSPACE=m
++CONFIG_DM_RAID=m
++CONFIG_DM_ZERO=m
++CONFIG_DM_DELAY=m
+ CONFIG_NETDEVICES=y
++CONFIG_BONDING=m
++CONFIG_DUMMY=m
++CONFIG_IFB=m
++CONFIG_MACVLAN=m
++CONFIG_NETCONSOLE=m
++CONFIG_TUN=m
++CONFIG_VETH=m
++CONFIG_ENC28J60=m
++CONFIG_MDIO_BITBANG=m
++CONFIG_PPP=m
++CONFIG_PPP_BSDCOMP=m
++CONFIG_PPP_DEFLATE=m
++CONFIG_PPP_FILTER=y
++CONFIG_PPP_MPPE=m
++CONFIG_PPP_MULTILINK=y
++CONFIG_PPPOATM=m
++CONFIG_PPPOE=m
++CONFIG_PPPOL2TP=m
++CONFIG_PPP_ASYNC=m
++CONFIG_PPP_SYNC_TTY=m
++CONFIG_SLIP=m
++CONFIG_SLIP_COMPRESSED=y
++CONFIG_SLIP_SMART=y
++CONFIG_USB_CATC=m
++CONFIG_USB_KAWETH=m
++CONFIG_USB_PEGASUS=m
++CONFIG_USB_RTL8150=m
++CONFIG_USB_RTL8152=m
+ CONFIG_USB_USBNET=y
++CONFIG_USB_NET_AX8817X=m
++CONFIG_USB_NET_AX88179_178A=m
++CONFIG_USB_NET_CDCETHER=m
++CONFIG_USB_NET_CDC_EEM=m
++CONFIG_USB_NET_CDC_NCM=m
++CONFIG_USB_NET_HUAWEI_CDC_NCM=m
++CONFIG_USB_NET_CDC_MBIM=m
++CONFIG_USB_NET_DM9601=m
++CONFIG_USB_NET_SR9700=m
++CONFIG_USB_NET_SR9800=m
++CONFIG_USB_NET_SMSC75XX=m
+ CONFIG_USB_NET_SMSC95XX=y
+-CONFIG_ZD1211RW=y
+-CONFIG_INPUT_EVDEV=y
++CONFIG_USB_NET_GL620A=m
++CONFIG_USB_NET_NET1080=m
++CONFIG_USB_NET_PLUSB=m
++CONFIG_USB_NET_MCS7830=m
++CONFIG_USB_NET_CDC_SUBSET=m
++CONFIG_USB_ALI_M5632=y
++CONFIG_USB_AN2720=y
++CONFIG_USB_EPSON2888=y
++CONFIG_USB_KC2190=y
++CONFIG_USB_NET_ZAURUS=m
++CONFIG_USB_NET_CX82310_ETH=m
++CONFIG_USB_NET_KALMIA=m
++CONFIG_USB_NET_QMI_WWAN=m
++CONFIG_USB_HSO=m
++CONFIG_USB_NET_INT51X1=m
++CONFIG_USB_IPHETH=m
++CONFIG_USB_SIERRA_NET=m
++CONFIG_USB_VL600=m
++CONFIG_LIBERTAS_THINFIRM=m
++CONFIG_LIBERTAS_THINFIRM_USB=m
++CONFIG_AT76C50X_USB=m
++CONFIG_USB_ZD1201=m
++CONFIG_USB_NET_RNDIS_WLAN=m
++CONFIG_RTL8187=m
++CONFIG_MAC80211_HWSIM=m
++CONFIG_ATH_CARDS=m
++CONFIG_ATH9K=m
++CONFIG_ATH9K_HTC=m
++CONFIG_CARL9170=m
++CONFIG_ATH6KL=m
++CONFIG_ATH6KL_USB=m
++CONFIG_AR5523=m
++CONFIG_B43=m
++# CONFIG_B43_PHY_N is not set
++CONFIG_B43LEGACY=m
++CONFIG_BRCMFMAC=m
++CONFIG_BRCMFMAC_USB=y
++CONFIG_HOSTAP=m
++CONFIG_LIBERTAS=m
++CONFIG_LIBERTAS_USB=m
++CONFIG_LIBERTAS_SDIO=m
++CONFIG_P54_COMMON=m
++CONFIG_P54_USB=m
++CONFIG_RT2X00=m
++CONFIG_RT2500USB=m
++CONFIG_RT73USB=m
++CONFIG_RT2800USB=m
++CONFIG_RT2800USB_RT3573=y
++CONFIG_RT2800USB_RT53XX=y
++CONFIG_RT2800USB_RT55XX=y
++CONFIG_RT2800USB_UNKNOWN=y
++CONFIG_RTL8192CU=m
++CONFIG_ZD1211RW=m
++CONFIG_MWIFIEX=m
++CONFIG_MWIFIEX_SDIO=m
++CONFIG_WIMAX_I2400M_USB=m
++CONFIG_INPUT_POLLDEV=m
++# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
++CONFIG_INPUT_JOYDEV=m
++CONFIG_INPUT_EVDEV=m
++# CONFIG_KEYBOARD_ATKBD is not set
++CONFIG_KEYBOARD_GPIO=m
++# CONFIG_INPUT_MOUSE is not set
++CONFIG_INPUT_JOYSTICK=y
++CONFIG_JOYSTICK_IFORCE=m
++CONFIG_JOYSTICK_IFORCE_USB=y
++CONFIG_JOYSTICK_XPAD=m
++CONFIG_JOYSTICK_XPAD_FF=y
++CONFIG_INPUT_TOUCHSCREEN=y
++CONFIG_TOUCHSCREEN_ADS7846=m
++CONFIG_TOUCHSCREEN_EGALAX=m
++CONFIG_TOUCHSCREEN_USB_COMPOSITE=m
++CONFIG_TOUCHSCREEN_STMPE=m
++CONFIG_INPUT_MISC=y
++CONFIG_INPUT_AD714X=m
++CONFIG_INPUT_ATI_REMOTE2=m
++CONFIG_INPUT_KEYSPAN_REMOTE=m
++CONFIG_INPUT_POWERMATE=m
++CONFIG_INPUT_YEALINK=m
++CONFIG_INPUT_CM109=m
++CONFIG_INPUT_UINPUT=m
++CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
++CONFIG_INPUT_ADXL34X=m
++CONFIG_INPUT_CMA3000=m
++CONFIG_SERIO=m
++CONFIG_SERIO_RAW=m
++CONFIG_GAMEPORT=m
++CONFIG_GAMEPORT_NS558=m
++CONFIG_GAMEPORT_L4=m
++CONFIG_DEVPTS_MULTIPLE_INSTANCES=y
+ # CONFIG_LEGACY_PTYS is not set
+ # CONFIG_DEVKMEM is not set
+ CONFIG_SERIAL_AMBA_PL011=y
+ CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+ CONFIG_TTY_PRINTK=y
++CONFIG_HW_RANDOM=y
++CONFIG_HW_RANDOM_BCM2835=m
++CONFIG_RAW_DRIVER=y
++CONFIG_BRCM_CHAR_DRIVERS=y
++CONFIG_BCM_VC_CMA=y
++CONFIG_BCM_VCIO=y
++CONFIG_BCM_VC_SM=y
+ CONFIG_I2C=y
+-CONFIG_I2C_CHARDEV=y
++CONFIG_I2C_CHARDEV=m
+ CONFIG_I2C_BCM2835=y
+ CONFIG_SPI=y
+-CONFIG_SPI_BCM2835=y
++CONFIG_SPI_BCM2835=m
++CONFIG_SPI_SPIDEV=y
++CONFIG_PPS=m
++CONFIG_PPS_CLIENT_LDISC=m
++CONFIG_PPS_CLIENT_GPIO=m
+ CONFIG_GPIO_SYSFS=y
++CONFIG_GPIO_ARIZONA=m
++CONFIG_GPIO_STMPE=y
++CONFIG_W1=m
++CONFIG_W1_MASTER_DS2490=m
++CONFIG_W1_MASTER_DS2482=m
++CONFIG_W1_MASTER_DS1WM=m
++CONFIG_W1_MASTER_GPIO=m
++CONFIG_W1_SLAVE_THERM=m
++CONFIG_W1_SLAVE_SMEM=m
++CONFIG_W1_SLAVE_DS2408=m
++CONFIG_W1_SLAVE_DS2413=m
++CONFIG_W1_SLAVE_DS2406=m
++CONFIG_W1_SLAVE_DS2423=m
++CONFIG_W1_SLAVE_DS2431=m
++CONFIG_W1_SLAVE_DS2433=m
++CONFIG_W1_SLAVE_DS2760=m
++CONFIG_W1_SLAVE_DS2780=m
++CONFIG_W1_SLAVE_DS2781=m
++CONFIG_W1_SLAVE_DS28E04=m
++CONFIG_W1_SLAVE_BQ27000=m
++CONFIG_BATTERY_DS2760=m
+ # CONFIG_HWMON is not set
++CONFIG_THERMAL=y
++CONFIG_THERMAL_BCM2835=y
++CONFIG_WATCHDOG=y
++CONFIG_BCM2835_WDT=y
++CONFIG_UCB1400_CORE=m
++CONFIG_MFD_STMPE=y
++CONFIG_STMPE_SPI=y
++CONFIG_MFD_ARIZONA_I2C=m
++CONFIG_MFD_ARIZONA_SPI=m
++CONFIG_MFD_WM5102=y
++CONFIG_MEDIA_SUPPORT=m
++CONFIG_MEDIA_CAMERA_SUPPORT=y
++CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
++CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
++CONFIG_MEDIA_RADIO_SUPPORT=y
++CONFIG_MEDIA_RC_SUPPORT=y
++CONFIG_MEDIA_CONTROLLER=y
++CONFIG_LIRC=m
++CONFIG_RC_DEVICES=y
++CONFIG_RC_ATI_REMOTE=m
++CONFIG_IR_IMON=m
++CONFIG_IR_MCEUSB=m
++CONFIG_IR_REDRAT3=m
++CONFIG_IR_STREAMZAP=m
++CONFIG_IR_IGUANA=m
++CONFIG_IR_TTUSBIR=m
++CONFIG_RC_LOOPBACK=m
++CONFIG_IR_GPIO_CIR=m
++CONFIG_MEDIA_USB_SUPPORT=y
++CONFIG_USB_VIDEO_CLASS=m
++CONFIG_USB_M5602=m
++CONFIG_USB_STV06XX=m
++CONFIG_USB_GL860=m
++CONFIG_USB_GSPCA_BENQ=m
++CONFIG_USB_GSPCA_CONEX=m
++CONFIG_USB_GSPCA_CPIA1=m
++CONFIG_USB_GSPCA_DTCS033=m
++CONFIG_USB_GSPCA_ETOMS=m
++CONFIG_USB_GSPCA_FINEPIX=m
++CONFIG_USB_GSPCA_JEILINJ=m
++CONFIG_USB_GSPCA_JL2005BCD=m
++CONFIG_USB_GSPCA_KINECT=m
++CONFIG_USB_GSPCA_KONICA=m
++CONFIG_USB_GSPCA_MARS=m
++CONFIG_USB_GSPCA_MR97310A=m
++CONFIG_USB_GSPCA_NW80X=m
++CONFIG_USB_GSPCA_OV519=m
++CONFIG_USB_GSPCA_OV534=m
++CONFIG_USB_GSPCA_OV534_9=m
++CONFIG_USB_GSPCA_PAC207=m
++CONFIG_USB_GSPCA_PAC7302=m
++CONFIG_USB_GSPCA_PAC7311=m
++CONFIG_USB_GSPCA_SE401=m
++CONFIG_USB_GSPCA_SN9C2028=m
++CONFIG_USB_GSPCA_SN9C20X=m
++CONFIG_USB_GSPCA_SONIXB=m
++CONFIG_USB_GSPCA_SONIXJ=m
++CONFIG_USB_GSPCA_SPCA500=m
++CONFIG_USB_GSPCA_SPCA501=m
++CONFIG_USB_GSPCA_SPCA505=m
++CONFIG_USB_GSPCA_SPCA506=m
++CONFIG_USB_GSPCA_SPCA508=m
++CONFIG_USB_GSPCA_SPCA561=m
++CONFIG_USB_GSPCA_SPCA1528=m
++CONFIG_USB_GSPCA_SQ905=m
++CONFIG_USB_GSPCA_SQ905C=m
++CONFIG_USB_GSPCA_SQ930X=m
++CONFIG_USB_GSPCA_STK014=m
++CONFIG_USB_GSPCA_STK1135=m
++CONFIG_USB_GSPCA_STV0680=m
++CONFIG_USB_GSPCA_SUNPLUS=m
++CONFIG_USB_GSPCA_T613=m
++CONFIG_USB_GSPCA_TOPRO=m
++CONFIG_USB_GSPCA_TV8532=m
++CONFIG_USB_GSPCA_VC032X=m
++CONFIG_USB_GSPCA_VICAM=m
++CONFIG_USB_GSPCA_XIRLINK_CIT=m
++CONFIG_USB_GSPCA_ZC3XX=m
++CONFIG_USB_PWC=m
++CONFIG_VIDEO_CPIA2=m
++CONFIG_USB_ZR364XX=m
++CONFIG_USB_STKWEBCAM=m
++CONFIG_USB_S2255=m
++CONFIG_VIDEO_USBTV=m
++CONFIG_VIDEO_PVRUSB2=m
++CONFIG_VIDEO_HDPVR=m
++CONFIG_VIDEO_USBVISION=m
++CONFIG_VIDEO_STK1160_COMMON=m
++CONFIG_VIDEO_STK1160_AC97=y
++CONFIG_VIDEO_GO7007=m
++CONFIG_VIDEO_GO7007_USB=m
++CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m
++CONFIG_VIDEO_AU0828=m
++CONFIG_VIDEO_AU0828_RC=y
++CONFIG_VIDEO_CX231XX=m
++CONFIG_VIDEO_CX231XX_ALSA=m
++CONFIG_VIDEO_CX231XX_DVB=m
++CONFIG_VIDEO_TM6000=m
++CONFIG_VIDEO_TM6000_ALSA=m
++CONFIG_VIDEO_TM6000_DVB=m
++CONFIG_DVB_USB=m
++CONFIG_DVB_USB_A800=m
++CONFIG_DVB_USB_DIBUSB_MB=m
++CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y
++CONFIG_DVB_USB_DIBUSB_MC=m
++CONFIG_DVB_USB_DIB0700=m
++CONFIG_DVB_USB_UMT_010=m
++CONFIG_DVB_USB_CXUSB=m
++CONFIG_DVB_USB_M920X=m
++CONFIG_DVB_USB_DIGITV=m
++CONFIG_DVB_USB_VP7045=m
++CONFIG_DVB_USB_VP702X=m
++CONFIG_DVB_USB_GP8PSK=m
++CONFIG_DVB_USB_NOVA_T_USB2=m
++CONFIG_DVB_USB_TTUSB2=m
++CONFIG_DVB_USB_DTT200U=m
++CONFIG_DVB_USB_OPERA1=m
++CONFIG_DVB_USB_AF9005=m
++CONFIG_DVB_USB_AF9005_REMOTE=m
++CONFIG_DVB_USB_PCTV452E=m
++CONFIG_DVB_USB_DW2102=m
++CONFIG_DVB_USB_CINERGY_T2=m
++CONFIG_DVB_USB_DTV5100=m
++CONFIG_DVB_USB_FRIIO=m
++CONFIG_DVB_USB_AZ6027=m
++CONFIG_DVB_USB_TECHNISAT_USB2=m
++CONFIG_DVB_USB_V2=m
++CONFIG_DVB_USB_AF9015=m
++CONFIG_DVB_USB_AF9035=m
++CONFIG_DVB_USB_ANYSEE=m
++CONFIG_DVB_USB_AU6610=m
++CONFIG_DVB_USB_AZ6007=m
++CONFIG_DVB_USB_CE6230=m
++CONFIG_DVB_USB_EC168=m
++CONFIG_DVB_USB_GL861=m
++CONFIG_DVB_USB_LME2510=m
++CONFIG_DVB_USB_MXL111SF=m
++CONFIG_DVB_USB_RTL28XXU=m
++CONFIG_DVB_USB_DVBSKY=m
++CONFIG_SMS_USB_DRV=m
++CONFIG_DVB_B2C2_FLEXCOP_USB=m
++CONFIG_DVB_AS102=m
++CONFIG_VIDEO_EM28XX=m
++CONFIG_VIDEO_EM28XX_V4L2=m
++CONFIG_VIDEO_EM28XX_ALSA=m
++CONFIG_VIDEO_EM28XX_DVB=m
++CONFIG_V4L_PLATFORM_DRIVERS=y
++CONFIG_VIDEO_BCM2835=y
++CONFIG_VIDEO_BCM2835_MMAL=m
++CONFIG_RADIO_SI470X=y
++CONFIG_USB_SI470X=m
++CONFIG_I2C_SI470X=m
++CONFIG_RADIO_SI4713=m
++CONFIG_I2C_SI4713=m
++CONFIG_USB_MR800=m
++CONFIG_USB_DSBR=m
++CONFIG_RADIO_SHARK=m
++CONFIG_RADIO_SHARK2=m
++CONFIG_USB_KEENE=m
++CONFIG_USB_MA901=m
++CONFIG_RADIO_TEA5764=m
++CONFIG_RADIO_SAA7706H=m
++CONFIG_RADIO_TEF6862=m
++CONFIG_RADIO_WL1273=m
++CONFIG_RADIO_WL128X=m
++# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
++CONFIG_VIDEO_UDA1342=m
++CONFIG_VIDEO_SONY_BTF_MPX=m
++CONFIG_VIDEO_TVP5150=m
++CONFIG_VIDEO_TW2804=m
++CONFIG_VIDEO_TW9903=m
++CONFIG_VIDEO_TW9906=m
++CONFIG_VIDEO_OV7640=m
++CONFIG_VIDEO_MT9V011=m
+ CONFIG_FB=y
+-CONFIG_FB_SIMPLE=y
++CONFIG_FB_BCM2708=y
++CONFIG_FB_SSD1307=m
++# CONFIG_BACKLIGHT_GENERIC is not set
++CONFIG_BACKLIGHT_GPIO=m
+ CONFIG_FRAMEBUFFER_CONSOLE=y
+ CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
++CONFIG_LOGO=y
++# CONFIG_LOGO_LINUX_MONO is not set
++# CONFIG_LOGO_LINUX_VGA16 is not set
++CONFIG_SOUND=y
++CONFIG_SND=m
++CONFIG_SND_SEQUENCER=m
++CONFIG_SND_SEQ_DUMMY=m
++CONFIG_SND_MIXER_OSS=m
++CONFIG_SND_PCM_OSS=m
++CONFIG_SND_SEQUENCER_OSS=y
++CONFIG_SND_HRTIMER=m
++CONFIG_SND_DUMMY=m
++CONFIG_SND_ALOOP=m
++CONFIG_SND_VIRMIDI=m
++CONFIG_SND_MTPAV=m
++CONFIG_SND_SERIAL_U16550=m
++CONFIG_SND_MPU401=m
++CONFIG_SND_BCM2835=m
++CONFIG_SND_USB_AUDIO=m
++CONFIG_SND_USB_UA101=m
++CONFIG_SND_USB_CAIAQ=m
++CONFIG_SND_USB_CAIAQ_INPUT=y
++CONFIG_SND_USB_6FIRE=m
++CONFIG_SND_SOC=m
++CONFIG_SND_BCM2835_SOC_I2S=m
++CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC=m
++CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS=m
++CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI=m
++CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP=m
++CONFIG_SND_BCM2708_SOC_RPI_DAC=m
++CONFIG_SND_BCM2708_SOC_RPI_PROTO=m
++CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC=m
++CONFIG_SND_SIMPLE_CARD=m
++CONFIG_SOUND_PRIME=m
++CONFIG_HIDRAW=y
++CONFIG_HID_A4TECH=m
++CONFIG_HID_ACRUX=m
++CONFIG_HID_APPLE=m
++CONFIG_HID_BELKIN=m
++CONFIG_HID_CHERRY=m
++CONFIG_HID_CHICONY=m
++CONFIG_HID_CYPRESS=m
++CONFIG_HID_DRAGONRISE=m
++CONFIG_HID_EMS_FF=m
++CONFIG_HID_ELECOM=m
++CONFIG_HID_ELO=m
++CONFIG_HID_EZKEY=m
++CONFIG_HID_HOLTEK=m
++CONFIG_HID_KEYTOUCH=m
++CONFIG_HID_KYE=m
++CONFIG_HID_UCLOGIC=m
++CONFIG_HID_WALTOP=m
++CONFIG_HID_GYRATION=m
++CONFIG_HID_TWINHAN=m
++CONFIG_HID_KENSINGTON=m
++CONFIG_HID_LCPOWER=m
++CONFIG_HID_LOGITECH=m
++CONFIG_HID_MAGICMOUSE=m
++CONFIG_HID_MICROSOFT=m
++CONFIG_HID_MONTEREY=m
++CONFIG_HID_MULTITOUCH=m
++CONFIG_HID_NTRIG=m
++CONFIG_HID_ORTEK=m
++CONFIG_HID_PANTHERLORD=m
++CONFIG_HID_PETALYNX=m
++CONFIG_HID_PICOLCD=m
++CONFIG_HID_ROCCAT=m
++CONFIG_HID_SAMSUNG=m
++CONFIG_HID_SONY=m
++CONFIG_HID_SPEEDLINK=m
++CONFIG_HID_SUNPLUS=m
++CONFIG_HID_GREENASIA=m
++CONFIG_HID_SMARTJOYPLUS=m
++CONFIG_HID_TOPSEED=m
++CONFIG_HID_THINGM=m
++CONFIG_HID_THRUSTMASTER=m
++CONFIG_HID_WACOM=m
++CONFIG_HID_WIIMOTE=m
++CONFIG_HID_XINMO=m
++CONFIG_HID_ZEROPLUS=m
++CONFIG_HID_ZYDACRON=m
++CONFIG_HID_PID=y
++CONFIG_USB_HIDDEV=y
+ CONFIG_USB=y
++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
++CONFIG_USB_MON=m
++CONFIG_USB_DWCOTG=y
++CONFIG_USB_PRINTER=m
+ CONFIG_USB_STORAGE=y
++CONFIG_USB_STORAGE_REALTEK=m
++CONFIG_USB_STORAGE_DATAFAB=m
++CONFIG_USB_STORAGE_FREECOM=m
++CONFIG_USB_STORAGE_ISD200=m
++CONFIG_USB_STORAGE_USBAT=m
++CONFIG_USB_STORAGE_SDDR09=m
++CONFIG_USB_STORAGE_SDDR55=m
++CONFIG_USB_STORAGE_JUMPSHOT=m
++CONFIG_USB_STORAGE_ALAUDA=m
++CONFIG_USB_STORAGE_ONETOUCH=m
++CONFIG_USB_STORAGE_KARMA=m
++CONFIG_USB_STORAGE_CYPRESS_ATACB=m
++CONFIG_USB_STORAGE_ENE_UB6250=m
++CONFIG_USB_MDC800=m
++CONFIG_USB_MICROTEK=m
++CONFIG_USBIP_CORE=m
++CONFIG_USBIP_VHCI_HCD=m
++CONFIG_USBIP_HOST=m
++CONFIG_USB_DWC2=y
++CONFIG_USB_SERIAL=m
++CONFIG_USB_SERIAL_GENERIC=y
++CONFIG_USB_SERIAL_AIRCABLE=m
++CONFIG_USB_SERIAL_ARK3116=m
++CONFIG_USB_SERIAL_BELKIN=m
++CONFIG_USB_SERIAL_CH341=m
++CONFIG_USB_SERIAL_WHITEHEAT=m
++CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
++CONFIG_USB_SERIAL_CP210X=m
++CONFIG_USB_SERIAL_CYPRESS_M8=m
++CONFIG_USB_SERIAL_EMPEG=m
++CONFIG_USB_SERIAL_FTDI_SIO=m
++CONFIG_USB_SERIAL_VISOR=m
++CONFIG_USB_SERIAL_IPAQ=m
++CONFIG_USB_SERIAL_IR=m
++CONFIG_USB_SERIAL_EDGEPORT=m
++CONFIG_USB_SERIAL_EDGEPORT_TI=m
++CONFIG_USB_SERIAL_F81232=m
++CONFIG_USB_SERIAL_GARMIN=m
++CONFIG_USB_SERIAL_IPW=m
++CONFIG_USB_SERIAL_IUU=m
++CONFIG_USB_SERIAL_KEYSPAN_PDA=m
++CONFIG_USB_SERIAL_KEYSPAN=m
++CONFIG_USB_SERIAL_KLSI=m
++CONFIG_USB_SERIAL_KOBIL_SCT=m
++CONFIG_USB_SERIAL_MCT_U232=m
++CONFIG_USB_SERIAL_METRO=m
++CONFIG_USB_SERIAL_MOS7720=m
++CONFIG_USB_SERIAL_MOS7840=m
++CONFIG_USB_SERIAL_NAVMAN=m
++CONFIG_USB_SERIAL_PL2303=m
++CONFIG_USB_SERIAL_OTI6858=m
++CONFIG_USB_SERIAL_QCAUX=m
++CONFIG_USB_SERIAL_QUALCOMM=m
++CONFIG_USB_SERIAL_SPCP8X5=m
++CONFIG_USB_SERIAL_SAFE=m
++CONFIG_USB_SERIAL_SIERRAWIRELESS=m
++CONFIG_USB_SERIAL_SYMBOL=m
++CONFIG_USB_SERIAL_TI=m
++CONFIG_USB_SERIAL_CYBERJACK=m
++CONFIG_USB_SERIAL_XIRCOM=m
++CONFIG_USB_SERIAL_OPTION=m
++CONFIG_USB_SERIAL_OMNINET=m
++CONFIG_USB_SERIAL_OPTICON=m
++CONFIG_USB_SERIAL_XSENS_MT=m
++CONFIG_USB_SERIAL_WISHBONE=m
++CONFIG_USB_SERIAL_SSU100=m
++CONFIG_USB_SERIAL_QT2=m
++CONFIG_USB_SERIAL_DEBUG=m
++CONFIG_USB_EMI62=m
++CONFIG_USB_EMI26=m
++CONFIG_USB_ADUTUX=m
++CONFIG_USB_SEVSEG=m
++CONFIG_USB_RIO500=m
++CONFIG_USB_LEGOTOWER=m
++CONFIG_USB_LCD=m
++CONFIG_USB_LED=m
++CONFIG_USB_CYPRESS_CY7C63=m
++CONFIG_USB_CYTHERM=m
++CONFIG_USB_IDMOUSE=m
++CONFIG_USB_FTDI_ELAN=m
++CONFIG_USB_APPLEDISPLAY=m
++CONFIG_USB_LD=m
++CONFIG_USB_TRANCEVIBRATOR=m
++CONFIG_USB_IOWARRIOR=m
++CONFIG_USB_TEST=m
++CONFIG_USB_ISIGHTFW=m
++CONFIG_USB_YUREX=m
++CONFIG_USB_ATM=m
++CONFIG_USB_SPEEDTOUCH=m
++CONFIG_USB_CXACRU=m
++CONFIG_USB_UEAGLEATM=m
++CONFIG_USB_XUSBATM=m
+ CONFIG_MMC=y
++CONFIG_MMC_BLOCK_MINORS=32
++CONFIG_MMC_BCM2835=y
++CONFIG_MMC_BCM2835_DMA=y
++CONFIG_MMC_BCM2835_SDHOST=y
+ CONFIG_MMC_SDHCI=y
+ CONFIG_MMC_SDHCI_PLTFM=y
+ CONFIG_MMC_SDHCI_BCM2835=y
++CONFIG_MMC_SPI=m
++CONFIG_LEDS_CLASS=y
+ CONFIG_LEDS_GPIO=y
+ CONFIG_LEDS_TRIGGER_TIMER=y
+ CONFIG_LEDS_TRIGGER_ONESHOT=y
+ CONFIG_LEDS_TRIGGER_HEARTBEAT=y
++CONFIG_LEDS_TRIGGER_BACKLIGHT=y
+ CONFIG_LEDS_TRIGGER_CPU=y
+ CONFIG_LEDS_TRIGGER_GPIO=y
+ CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+-CONFIG_LEDS_TRIGGER_TRANSIENT=y
+-CONFIG_LEDS_TRIGGER_CAMERA=y
++CONFIG_LEDS_TRIGGER_TRANSIENT=m
++CONFIG_LEDS_TRIGGER_CAMERA=m
++CONFIG_LEDS_TRIGGER_INPUT=y
++CONFIG_RTC_CLASS=y
++# CONFIG_RTC_HCTOSYS is not set
++CONFIG_RTC_DRV_DS1307=m
++CONFIG_RTC_DRV_DS1374=m
++CONFIG_RTC_DRV_DS1672=m
++CONFIG_RTC_DRV_DS3232=m
++CONFIG_RTC_DRV_MAX6900=m
++CONFIG_RTC_DRV_RS5C372=m
++CONFIG_RTC_DRV_ISL1208=m
++CONFIG_RTC_DRV_ISL12022=m
++CONFIG_RTC_DRV_ISL12057=m
++CONFIG_RTC_DRV_X1205=m
++CONFIG_RTC_DRV_PCF2127=m
++CONFIG_RTC_DRV_PCF8523=m
++CONFIG_RTC_DRV_PCF8563=m
++CONFIG_RTC_DRV_PCF8583=m
++CONFIG_RTC_DRV_M41T80=m
++CONFIG_RTC_DRV_BQ32K=m
++CONFIG_RTC_DRV_S35390A=m
++CONFIG_RTC_DRV_FM3130=m
++CONFIG_RTC_DRV_RX8581=m
++CONFIG_RTC_DRV_RX8025=m
++CONFIG_RTC_DRV_EM3027=m
++CONFIG_RTC_DRV_RV3029C2=m
++CONFIG_RTC_DRV_M41T93=m
++CONFIG_RTC_DRV_M41T94=m
++CONFIG_RTC_DRV_DS1305=m
++CONFIG_RTC_DRV_DS1390=m
++CONFIG_RTC_DRV_MAX6902=m
++CONFIG_RTC_DRV_R9701=m
++CONFIG_RTC_DRV_RS5C348=m
++CONFIG_RTC_DRV_DS3234=m
++CONFIG_RTC_DRV_PCF2123=m
++CONFIG_RTC_DRV_RX4581=m
++CONFIG_DMADEVICES=y
++CONFIG_DMA_BCM2708=y
++CONFIG_UIO=m
++CONFIG_UIO_PDRV_GENIRQ=m
+ CONFIG_STAGING=y
+-CONFIG_USB_DWC2=y
+-CONFIG_USB_DWC2_HOST=y
++CONFIG_PRISM2_USB=m
++CONFIG_R8712U=m
++CONFIG_R8188EU=m
++CONFIG_R8723AU=m
++CONFIG_VT6656=m
++CONFIG_SPEAKUP=m
++CONFIG_SPEAKUP_SYNTH_SOFT=m
++CONFIG_STAGING_MEDIA=y
++CONFIG_LIRC_STAGING=y
++CONFIG_LIRC_IMON=m
++CONFIG_LIRC_SASEM=m
++CONFIG_LIRC_SERIAL=m
++CONFIG_FB_TFT=m
++CONFIG_FB_TFT_AGM1264K_FL=m
++CONFIG_FB_TFT_BD663474=m
++CONFIG_FB_TFT_HX8340BN=m
++CONFIG_FB_TFT_HX8347D=m
++CONFIG_FB_TFT_HX8353D=m
++CONFIG_FB_TFT_ILI9320=m
++CONFIG_FB_TFT_ILI9325=m
++CONFIG_FB_TFT_ILI9340=m
++CONFIG_FB_TFT_ILI9341=m
++CONFIG_FB_TFT_ILI9481=m
++CONFIG_FB_TFT_ILI9486=m
++CONFIG_FB_TFT_PCD8544=m
++CONFIG_FB_TFT_RA8875=m
++CONFIG_FB_TFT_S6D02A1=m
++CONFIG_FB_TFT_S6D1121=m
++CONFIG_FB_TFT_SSD1289=m
++CONFIG_FB_TFT_SSD1306=m
++CONFIG_FB_TFT_SSD1331=m
++CONFIG_FB_TFT_SSD1351=m
++CONFIG_FB_TFT_ST7735R=m
++CONFIG_FB_TFT_TINYLCD=m
++CONFIG_FB_TFT_TLS8204=m
++CONFIG_FB_TFT_UC1701=m
++CONFIG_FB_TFT_UPD161704=m
++CONFIG_FB_TFT_WATTEROTT=m
++CONFIG_FB_FLEX=m
++CONFIG_FB_TFT_FBTFT_DEVICE=m
++CONFIG_MAILBOX=y
++CONFIG_BCM2708_MBOX=y
++CONFIG_BCM2835_MBOX=y
+ # CONFIG_IOMMU_SUPPORT is not set
++CONFIG_EXTCON=m
++CONFIG_EXTCON_ARIZONA=m
++CONFIG_RASPBERRYPI_FIRMWARE=y
+ CONFIG_EXT2_FS=y
+ CONFIG_EXT2_FS_XATTR=y
+ CONFIG_EXT2_FS_POSIX_ACL=y
+@@ -107,18 +1078,110 @@
+ CONFIG_EXT3_FS_POSIX_ACL=y
+ CONFIG_EXT4_FS=y
+ CONFIG_EXT4_FS_POSIX_ACL=y
++CONFIG_EXT4_FS_SECURITY=y
++CONFIG_REISERFS_FS=m
++CONFIG_REISERFS_FS_XATTR=y
++CONFIG_REISERFS_FS_POSIX_ACL=y
++CONFIG_REISERFS_FS_SECURITY=y
++CONFIG_JFS_FS=m
++CONFIG_JFS_POSIX_ACL=y
++CONFIG_JFS_SECURITY=y
++CONFIG_JFS_STATISTICS=y
++CONFIG_XFS_FS=m
++CONFIG_XFS_QUOTA=y
++CONFIG_XFS_POSIX_ACL=y
++CONFIG_XFS_RT=y
++CONFIG_GFS2_FS=m
++CONFIG_OCFS2_FS=m
++CONFIG_BTRFS_FS=m
++CONFIG_BTRFS_FS_POSIX_ACL=y
++CONFIG_NILFS2_FS=m
++CONFIG_F2FS_FS=y
+ CONFIG_FANOTIFY=y
++CONFIG_QFMT_V1=m
++CONFIG_QFMT_V2=m
++CONFIG_AUTOFS4_FS=y
++CONFIG_FUSE_FS=m
++CONFIG_CUSE=m
++CONFIG_FSCACHE=y
++CONFIG_FSCACHE_STATS=y
++CONFIG_FSCACHE_HISTOGRAM=y
++CONFIG_CACHEFILES=y
++CONFIG_ISO9660_FS=m
++CONFIG_JOLIET=y
++CONFIG_ZISOFS=y
++CONFIG_UDF_FS=m
+ CONFIG_MSDOS_FS=y
+ CONFIG_VFAT_FS=y
++CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
++CONFIG_NTFS_FS=m
++CONFIG_NTFS_RW=y
+ CONFIG_TMPFS=y
+ CONFIG_TMPFS_POSIX_ACL=y
+-# CONFIG_MISC_FILESYSTEMS is not set
++CONFIG_CONFIGFS_FS=y
++CONFIG_ECRYPT_FS=m
++CONFIG_HFS_FS=m
++CONFIG_HFSPLUS_FS=m
++CONFIG_SQUASHFS=m
++CONFIG_SQUASHFS_XATTR=y
++CONFIG_SQUASHFS_LZO=y
++CONFIG_SQUASHFS_XZ=y
+ CONFIG_NFS_FS=y
+-CONFIG_NFSD=y
++CONFIG_NFS_V3_ACL=y
++CONFIG_NFS_V4=y
++CONFIG_NFS_SWAP=y
++CONFIG_ROOT_NFS=y
++CONFIG_NFS_FSCACHE=y
++CONFIG_NFSD=m
++CONFIG_NFSD_V3_ACL=y
++CONFIG_NFSD_V4=y
++CONFIG_CIFS=m
++CONFIG_CIFS_WEAK_PW_HASH=y
++CONFIG_CIFS_UPCALL=y
++CONFIG_CIFS_XATTR=y
++CONFIG_CIFS_POSIX=y
++CONFIG_9P_FS=m
++CONFIG_9P_FS_POSIX_ACL=y
++CONFIG_NLS_DEFAULT="utf8"
+ CONFIG_NLS_CODEPAGE_437=y
++CONFIG_NLS_CODEPAGE_737=m
++CONFIG_NLS_CODEPAGE_775=m
++CONFIG_NLS_CODEPAGE_850=m
++CONFIG_NLS_CODEPAGE_852=m
++CONFIG_NLS_CODEPAGE_855=m
++CONFIG_NLS_CODEPAGE_857=m
++CONFIG_NLS_CODEPAGE_860=m
++CONFIG_NLS_CODEPAGE_861=m
++CONFIG_NLS_CODEPAGE_862=m
++CONFIG_NLS_CODEPAGE_863=m
++CONFIG_NLS_CODEPAGE_864=m
++CONFIG_NLS_CODEPAGE_865=m
++CONFIG_NLS_CODEPAGE_866=m
++CONFIG_NLS_CODEPAGE_869=m
++CONFIG_NLS_CODEPAGE_936=m
++CONFIG_NLS_CODEPAGE_950=m
++CONFIG_NLS_CODEPAGE_932=m
++CONFIG_NLS_CODEPAGE_949=m
++CONFIG_NLS_CODEPAGE_874=m
++CONFIG_NLS_ISO8859_8=m
++CONFIG_NLS_CODEPAGE_1250=m
++CONFIG_NLS_CODEPAGE_1251=m
+ CONFIG_NLS_ASCII=y
+-CONFIG_NLS_ISO8859_1=y
++CONFIG_NLS_ISO8859_1=m
++CONFIG_NLS_ISO8859_2=m
++CONFIG_NLS_ISO8859_3=m
++CONFIG_NLS_ISO8859_4=m
++CONFIG_NLS_ISO8859_5=m
++CONFIG_NLS_ISO8859_6=m
++CONFIG_NLS_ISO8859_7=m
++CONFIG_NLS_ISO8859_9=m
++CONFIG_NLS_ISO8859_13=m
++CONFIG_NLS_ISO8859_14=m
++CONFIG_NLS_ISO8859_15=m
++CONFIG_NLS_KOI8_R=m
++CONFIG_NLS_KOI8_U=m
+ CONFIG_NLS_UTF8=y
++CONFIG_DLM=m
+ CONFIG_PRINTK_TIME=y
+ CONFIG_BOOT_PRINTK_DELAY=y
+ CONFIG_DYNAMIC_DEBUG=y
+@@ -128,14 +1191,39 @@
+ CONFIG_UNUSED_SYMBOLS=y
+ CONFIG_DEBUG_MEMORY_INIT=y
+ CONFIG_LOCKUP_DETECTOR=y
++CONFIG_TIMER_STATS=y
++# CONFIG_DEBUG_PREEMPT is not set
++CONFIG_LATENCYTOP=y
++CONFIG_IRQSOFF_TRACER=y
+ CONFIG_SCHED_TRACER=y
+ CONFIG_STACK_TRACER=y
++CONFIG_BLK_DEV_IO_TRACE=y
++# CONFIG_KPROBE_EVENT is not set
+ CONFIG_FUNCTION_PROFILER=y
+ CONFIG_TEST_KSTRTOX=y
+ CONFIG_KGDB=y
+ CONFIG_KGDB_KDB=y
++CONFIG_KDB_KEYBOARD=y
+ CONFIG_STRICT_DEVMEM=y
+ CONFIG_DEBUG_LL=y
+ CONFIG_EARLY_PRINTK=y
++CONFIG_CRYPTO_USER=m
++CONFIG_CRYPTO_CRYPTD=m
++CONFIG_CRYPTO_CBC=y
++CONFIG_CRYPTO_CTS=m
++CONFIG_CRYPTO_XTS=m
++CONFIG_CRYPTO_XCBC=m
++CONFIG_CRYPTO_SHA512=m
++CONFIG_CRYPTO_TGR192=m
++CONFIG_CRYPTO_WP512=m
++CONFIG_CRYPTO_CAST5=m
++CONFIG_CRYPTO_DES=y
++# CONFIG_CRYPTO_ANSI_CPRNG is not set
++# CONFIG_CRYPTO_HW is not set
++CONFIG_ARM_CRYPTO=y
++CONFIG_CRYPTO_SHA1_ARM=m
++CONFIG_CRYPTO_AES_ARM=m
++CONFIG_CRC_ITU_T=y
++CONFIG_LIBCRC32C=y
+ # CONFIG_XZ_DEC_ARM is not set
+ # CONFIG_XZ_DEC_ARMTHUMB is not set
+diff -Nur linux-4.1.3/arch/arm/configs/bcmrpi_defconfig linux-xbian-rpi/arch/arm/configs/bcmrpi_defconfig
+--- linux-4.1.3/arch/arm/configs/bcmrpi_defconfig 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/configs/bcmrpi_defconfig 2015-07-28 01:20:58.170137709 +0200
+@@ -0,0 +1,1223 @@
++# CONFIG_ARM_PATCH_PHYS_VIRT is not set
++CONFIG_PHYS_OFFSET=0
++# CONFIG_LOCALVERSION_AUTO is not set
++CONFIG_SYSVIPC=y
++CONFIG_POSIX_MQUEUE=y
++CONFIG_FHANDLE=y
++CONFIG_NO_HZ=y
++CONFIG_HIGH_RES_TIMERS=y
++CONFIG_BSD_PROCESS_ACCT=y
++CONFIG_BSD_PROCESS_ACCT_V3=y
++CONFIG_TASKSTATS=y
++CONFIG_TASK_DELAY_ACCT=y
++CONFIG_TASK_XACCT=y
++CONFIG_TASK_IO_ACCOUNTING=y
++CONFIG_IKCONFIG=m
++CONFIG_IKCONFIG_PROC=y
++CONFIG_CGROUP_FREEZER=y
++CONFIG_CGROUP_DEVICE=y
++CONFIG_CGROUP_CPUACCT=y
++CONFIG_MEMCG=y
++CONFIG_BLK_CGROUP=y
++CONFIG_NAMESPACES=y
++CONFIG_SCHED_AUTOGROUP=y
++CONFIG_BLK_DEV_INITRD=y
++CONFIG_EMBEDDED=y
++# CONFIG_COMPAT_BRK is not set
++CONFIG_PROFILING=y
++CONFIG_OPROFILE=m
++CONFIG_KPROBES=y
++CONFIG_JUMP_LABEL=y
++CONFIG_MODULES=y
++CONFIG_MODULE_UNLOAD=y
++CONFIG_MODVERSIONS=y
++CONFIG_MODULE_SRCVERSION_ALL=y
++CONFIG_BLK_DEV_THROTTLING=y
++CONFIG_PARTITION_ADVANCED=y
++CONFIG_MAC_PARTITION=y
++CONFIG_CFQ_GROUP_IOSCHED=y
++CONFIG_ARCH_BCM2708=y
++CONFIG_BCM2708_DT=y
++CONFIG_PREEMPT=y
++CONFIG_AEABI=y
++CONFIG_OABI_COMPAT=y
++CONFIG_CLEANCACHE=y
++CONFIG_FRONTSWAP=y
++CONFIG_CMA=y
++CONFIG_ZSMALLOC=m
++CONFIG_PGTABLE_MAPPING=y
++CONFIG_UACCESS_WITH_MEMCPY=y
++CONFIG_SECCOMP=y
++CONFIG_ZBOOT_ROM_TEXT=0x0
++CONFIG_ZBOOT_ROM_BSS=0x0
++CONFIG_CMDLINE="console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext4 rootwait"
++CONFIG_CPU_FREQ=y
++CONFIG_CPU_FREQ_STAT=m
++CONFIG_CPU_FREQ_STAT_DETAILS=y
++CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE=y
++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
++CONFIG_CPU_FREQ_GOV_USERSPACE=y
++CONFIG_CPU_FREQ_GOV_ONDEMAND=y
++CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
++CONFIG_VFP=y
++CONFIG_BINFMT_MISC=m
++# CONFIG_SUSPEND is not set
++CONFIG_NET=y
++CONFIG_PACKET=y
++CONFIG_UNIX=y
++CONFIG_XFRM_USER=y
++CONFIG_NET_KEY=m
++CONFIG_INET=y
++CONFIG_IP_MULTICAST=y
++CONFIG_IP_ADVANCED_ROUTER=y
++CONFIG_IP_MULTIPLE_TABLES=y
++CONFIG_IP_ROUTE_MULTIPATH=y
++CONFIG_IP_ROUTE_VERBOSE=y
++CONFIG_IP_PNP=y
++CONFIG_IP_PNP_DHCP=y
++CONFIG_IP_PNP_RARP=y
++CONFIG_NET_IPIP=m
++CONFIG_NET_IPGRE_DEMUX=m
++CONFIG_NET_IPGRE=m
++CONFIG_IP_MROUTE=y
++CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
++CONFIG_IP_PIMSM_V1=y
++CONFIG_IP_PIMSM_V2=y
++CONFIG_SYN_COOKIES=y
++CONFIG_INET_AH=m
++CONFIG_INET_ESP=m
++CONFIG_INET_IPCOMP=m
++CONFIG_INET_XFRM_MODE_TRANSPORT=m
++CONFIG_INET_XFRM_MODE_TUNNEL=m
++CONFIG_INET_XFRM_MODE_BEET=m
++CONFIG_INET_LRO=m
++CONFIG_INET_DIAG=m
++CONFIG_INET6_AH=m
++CONFIG_INET6_ESP=m
++CONFIG_INET6_IPCOMP=m
++CONFIG_IPV6_TUNNEL=m
++CONFIG_IPV6_MULTIPLE_TABLES=y
++CONFIG_IPV6_MROUTE=y
++CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y
++CONFIG_IPV6_PIMSM_V2=y
++CONFIG_NETFILTER=y
++CONFIG_NF_CONNTRACK=m
++CONFIG_NF_CONNTRACK_ZONES=y
++CONFIG_NF_CONNTRACK_EVENTS=y
++CONFIG_NF_CONNTRACK_TIMESTAMP=y
++CONFIG_NF_CT_PROTO_DCCP=m
++CONFIG_NF_CT_PROTO_UDPLITE=m
++CONFIG_NF_CONNTRACK_AMANDA=m
++CONFIG_NF_CONNTRACK_FTP=m
++CONFIG_NF_CONNTRACK_H323=m
++CONFIG_NF_CONNTRACK_IRC=m
++CONFIG_NF_CONNTRACK_NETBIOS_NS=m
++CONFIG_NF_CONNTRACK_SNMP=m
++CONFIG_NF_CONNTRACK_PPTP=m
++CONFIG_NF_CONNTRACK_SANE=m
++CONFIG_NF_CONNTRACK_SIP=m
++CONFIG_NF_CONNTRACK_TFTP=m
++CONFIG_NF_CT_NETLINK=m
++CONFIG_NETFILTER_XT_SET=m
++CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
++CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
++CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
++CONFIG_NETFILTER_XT_TARGET_DSCP=m
++CONFIG_NETFILTER_XT_TARGET_HMARK=m
++CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
++CONFIG_NETFILTER_XT_TARGET_LED=m
++CONFIG_NETFILTER_XT_TARGET_LOG=m
++CONFIG_NETFILTER_XT_TARGET_MARK=m
++CONFIG_NETFILTER_XT_TARGET_NFLOG=m
++CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
++CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
++CONFIG_NETFILTER_XT_TARGET_TEE=m
++CONFIG_NETFILTER_XT_TARGET_TPROXY=m
++CONFIG_NETFILTER_XT_TARGET_TRACE=m
++CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
++CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
++CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
++CONFIG_NETFILTER_XT_MATCH_BPF=m
++CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
++CONFIG_NETFILTER_XT_MATCH_COMMENT=m
++CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
++CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m
++CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
++CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
++CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
++CONFIG_NETFILTER_XT_MATCH_CPU=m
++CONFIG_NETFILTER_XT_MATCH_DCCP=m
++CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
++CONFIG_NETFILTER_XT_MATCH_DSCP=m
++CONFIG_NETFILTER_XT_MATCH_ESP=m
++CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
++CONFIG_NETFILTER_XT_MATCH_HELPER=m
++CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
++CONFIG_NETFILTER_XT_MATCH_IPVS=m
++CONFIG_NETFILTER_XT_MATCH_LENGTH=m
++CONFIG_NETFILTER_XT_MATCH_LIMIT=m
++CONFIG_NETFILTER_XT_MATCH_MAC=m
++CONFIG_NETFILTER_XT_MATCH_MARK=m
++CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
++CONFIG_NETFILTER_XT_MATCH_NFACCT=m
++CONFIG_NETFILTER_XT_MATCH_OSF=m
++CONFIG_NETFILTER_XT_MATCH_OWNER=m
++CONFIG_NETFILTER_XT_MATCH_POLICY=m
++CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
++CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
++CONFIG_NETFILTER_XT_MATCH_QUOTA=m
++CONFIG_NETFILTER_XT_MATCH_RATEEST=m
++CONFIG_NETFILTER_XT_MATCH_REALM=m
++CONFIG_NETFILTER_XT_MATCH_RECENT=m
++CONFIG_NETFILTER_XT_MATCH_SOCKET=m
++CONFIG_NETFILTER_XT_MATCH_STATE=m
++CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
++CONFIG_NETFILTER_XT_MATCH_STRING=m
++CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
++CONFIG_NETFILTER_XT_MATCH_TIME=m
++CONFIG_NETFILTER_XT_MATCH_U32=m
++CONFIG_IP_SET=m
++CONFIG_IP_SET_BITMAP_IP=m
++CONFIG_IP_SET_BITMAP_IPMAC=m
++CONFIG_IP_SET_BITMAP_PORT=m
++CONFIG_IP_SET_HASH_IP=m
++CONFIG_IP_SET_HASH_IPPORT=m
++CONFIG_IP_SET_HASH_IPPORTIP=m
++CONFIG_IP_SET_HASH_IPPORTNET=m
++CONFIG_IP_SET_HASH_NET=m
++CONFIG_IP_SET_HASH_NETPORT=m
++CONFIG_IP_SET_HASH_NETIFACE=m
++CONFIG_IP_SET_LIST_SET=m
++CONFIG_IP_VS=m
++CONFIG_IP_VS_PROTO_TCP=y
++CONFIG_IP_VS_PROTO_UDP=y
++CONFIG_IP_VS_PROTO_ESP=y
++CONFIG_IP_VS_PROTO_AH=y
++CONFIG_IP_VS_PROTO_SCTP=y
++CONFIG_IP_VS_RR=m
++CONFIG_IP_VS_WRR=m
++CONFIG_IP_VS_LC=m
++CONFIG_IP_VS_WLC=m
++CONFIG_IP_VS_LBLC=m
++CONFIG_IP_VS_LBLCR=m
++CONFIG_IP_VS_DH=m
++CONFIG_IP_VS_SH=m
++CONFIG_IP_VS_SED=m
++CONFIG_IP_VS_NQ=m
++CONFIG_IP_VS_FTP=m
++CONFIG_IP_VS_PE_SIP=m
++CONFIG_NF_CONNTRACK_IPV4=m
++CONFIG_IP_NF_IPTABLES=m
++CONFIG_IP_NF_MATCH_AH=m
++CONFIG_IP_NF_MATCH_ECN=m
++CONFIG_IP_NF_MATCH_TTL=m
++CONFIG_IP_NF_FILTER=m
++CONFIG_IP_NF_TARGET_REJECT=m
++CONFIG_IP_NF_NAT=m
++CONFIG_IP_NF_TARGET_MASQUERADE=m
++CONFIG_IP_NF_TARGET_NETMAP=m
++CONFIG_IP_NF_TARGET_REDIRECT=m
++CONFIG_IP_NF_MANGLE=m
++CONFIG_IP_NF_TARGET_CLUSTERIP=m
++CONFIG_IP_NF_TARGET_ECN=m
++CONFIG_IP_NF_TARGET_TTL=m
++CONFIG_IP_NF_RAW=m
++CONFIG_IP_NF_ARPTABLES=m
++CONFIG_IP_NF_ARPFILTER=m
++CONFIG_IP_NF_ARP_MANGLE=m
++CONFIG_NF_CONNTRACK_IPV6=m
++CONFIG_IP6_NF_IPTABLES=m
++CONFIG_IP6_NF_MATCH_AH=m
++CONFIG_IP6_NF_MATCH_EUI64=m
++CONFIG_IP6_NF_MATCH_FRAG=m
++CONFIG_IP6_NF_MATCH_OPTS=m
++CONFIG_IP6_NF_MATCH_HL=m
++CONFIG_IP6_NF_MATCH_IPV6HEADER=m
++CONFIG_IP6_NF_MATCH_MH=m
++CONFIG_IP6_NF_MATCH_RT=m
++CONFIG_IP6_NF_TARGET_HL=m
++CONFIG_IP6_NF_FILTER=m
++CONFIG_IP6_NF_TARGET_REJECT=m
++CONFIG_IP6_NF_MANGLE=m
++CONFIG_IP6_NF_RAW=m
++CONFIG_IP6_NF_NAT=m
++CONFIG_IP6_NF_TARGET_MASQUERADE=m
++CONFIG_IP6_NF_TARGET_NPT=m
++CONFIG_BRIDGE_NF_EBTABLES=m
++CONFIG_BRIDGE_EBT_BROUTE=m
++CONFIG_BRIDGE_EBT_T_FILTER=m
++CONFIG_BRIDGE_EBT_T_NAT=m
++CONFIG_BRIDGE_EBT_802_3=m
++CONFIG_BRIDGE_EBT_AMONG=m
++CONFIG_BRIDGE_EBT_ARP=m
++CONFIG_BRIDGE_EBT_IP=m
++CONFIG_BRIDGE_EBT_IP6=m
++CONFIG_BRIDGE_EBT_LIMIT=m
++CONFIG_BRIDGE_EBT_MARK=m
++CONFIG_BRIDGE_EBT_PKTTYPE=m
++CONFIG_BRIDGE_EBT_STP=m
++CONFIG_BRIDGE_EBT_VLAN=m
++CONFIG_BRIDGE_EBT_ARPREPLY=m
++CONFIG_BRIDGE_EBT_DNAT=m
++CONFIG_BRIDGE_EBT_MARK_T=m
++CONFIG_BRIDGE_EBT_REDIRECT=m
++CONFIG_BRIDGE_EBT_SNAT=m
++CONFIG_BRIDGE_EBT_LOG=m
++CONFIG_BRIDGE_EBT_NFLOG=m
++CONFIG_SCTP_COOKIE_HMAC_SHA1=y
++CONFIG_ATM=m
++CONFIG_L2TP=m
++CONFIG_L2TP_V3=y
++CONFIG_L2TP_IP=m
++CONFIG_L2TP_ETH=m
++CONFIG_BRIDGE=m
++CONFIG_VLAN_8021Q=m
++CONFIG_VLAN_8021Q_GVRP=y
++CONFIG_ATALK=m
++CONFIG_6LOWPAN=m
++CONFIG_NET_SCHED=y
++CONFIG_NET_SCH_CBQ=m
++CONFIG_NET_SCH_HTB=m
++CONFIG_NET_SCH_HFSC=m
++CONFIG_NET_SCH_PRIO=m
++CONFIG_NET_SCH_MULTIQ=m
++CONFIG_NET_SCH_RED=m
++CONFIG_NET_SCH_SFB=m
++CONFIG_NET_SCH_SFQ=m
++CONFIG_NET_SCH_TEQL=m
++CONFIG_NET_SCH_TBF=m
++CONFIG_NET_SCH_GRED=m
++CONFIG_NET_SCH_DSMARK=m
++CONFIG_NET_SCH_NETEM=m
++CONFIG_NET_SCH_DRR=m
++CONFIG_NET_SCH_MQPRIO=m
++CONFIG_NET_SCH_CHOKE=m
++CONFIG_NET_SCH_QFQ=m
++CONFIG_NET_SCH_CODEL=m
++CONFIG_NET_SCH_FQ_CODEL=m
++CONFIG_NET_SCH_INGRESS=m
++CONFIG_NET_SCH_PLUG=m
++CONFIG_NET_CLS_BASIC=m
++CONFIG_NET_CLS_TCINDEX=m
++CONFIG_NET_CLS_ROUTE4=m
++CONFIG_NET_CLS_FW=m
++CONFIG_NET_CLS_U32=m
++CONFIG_CLS_U32_MARK=y
++CONFIG_NET_CLS_RSVP=m
++CONFIG_NET_CLS_RSVP6=m
++CONFIG_NET_CLS_FLOW=m
++CONFIG_NET_CLS_CGROUP=m
++CONFIG_NET_EMATCH=y
++CONFIG_NET_EMATCH_CMP=m
++CONFIG_NET_EMATCH_NBYTE=m
++CONFIG_NET_EMATCH_U32=m
++CONFIG_NET_EMATCH_META=m
++CONFIG_NET_EMATCH_TEXT=m
++CONFIG_NET_EMATCH_IPSET=m
++CONFIG_NET_CLS_ACT=y
++CONFIG_NET_ACT_POLICE=m
++CONFIG_NET_ACT_GACT=m
++CONFIG_GACT_PROB=y
++CONFIG_NET_ACT_MIRRED=m
++CONFIG_NET_ACT_IPT=m
++CONFIG_NET_ACT_NAT=m
++CONFIG_NET_ACT_PEDIT=m
++CONFIG_NET_ACT_SIMP=m
++CONFIG_NET_ACT_SKBEDIT=m
++CONFIG_NET_ACT_CSUM=m
++CONFIG_BATMAN_ADV=m
++CONFIG_OPENVSWITCH=m
++CONFIG_NET_PKTGEN=m
++CONFIG_HAMRADIO=y
++CONFIG_AX25=m
++CONFIG_NETROM=m
++CONFIG_ROSE=m
++CONFIG_MKISS=m
++CONFIG_6PACK=m
++CONFIG_BPQETHER=m
++CONFIG_BAYCOM_SER_FDX=m
++CONFIG_BAYCOM_SER_HDX=m
++CONFIG_YAM=m
++CONFIG_CAN=m
++CONFIG_CAN_VCAN=m
++CONFIG_CAN_MCP251X=m
++CONFIG_IRDA=m
++CONFIG_IRLAN=m
++CONFIG_IRNET=m
++CONFIG_IRCOMM=m
++CONFIG_IRDA_ULTRA=y
++CONFIG_IRDA_CACHE_LAST_LSAP=y
++CONFIG_IRDA_FAST_RR=y
++CONFIG_IRTTY_SIR=m
++CONFIG_KINGSUN_DONGLE=m
++CONFIG_KSDAZZLE_DONGLE=m
++CONFIG_KS959_DONGLE=m
++CONFIG_USB_IRDA=m
++CONFIG_SIGMATEL_FIR=m
++CONFIG_MCS_FIR=m
++CONFIG_BT=m
++CONFIG_BT_RFCOMM=m
++CONFIG_BT_RFCOMM_TTY=y
++CONFIG_BT_BNEP=m
++CONFIG_BT_BNEP_MC_FILTER=y
++CONFIG_BT_BNEP_PROTO_FILTER=y
++CONFIG_BT_HIDP=m
++CONFIG_BT_6LOWPAN=m
++CONFIG_BT_HCIBTUSB=m
++CONFIG_BT_HCIBCM203X=m
++CONFIG_BT_HCIBPA10X=m
++CONFIG_BT_HCIBFUSB=m
++CONFIG_BT_HCIVHCI=m
++CONFIG_BT_MRVL=m
++CONFIG_BT_MRVL_SDIO=m
++CONFIG_BT_ATH3K=m
++CONFIG_BT_WILINK=m
++CONFIG_MAC80211=m
++CONFIG_MAC80211_MESH=y
++CONFIG_WIMAX=m
++CONFIG_RFKILL=m
++CONFIG_RFKILL_INPUT=y
++CONFIG_NET_9P=m
++CONFIG_NFC=m
++CONFIG_NFC_PN533=m
++CONFIG_DEVTMPFS=y
++CONFIG_DEVTMPFS_MOUNT=y
++CONFIG_DMA_CMA=y
++CONFIG_CMA_SIZE_MBYTES=5
++CONFIG_ZRAM=m
++CONFIG_ZRAM_LZ4_COMPRESS=y
++CONFIG_BLK_DEV_LOOP=y
++CONFIG_BLK_DEV_CRYPTOLOOP=m
++CONFIG_BLK_DEV_DRBD=m
++CONFIG_BLK_DEV_NBD=m
++CONFIG_BLK_DEV_RAM=y
++CONFIG_CDROM_PKTCDVD=m
++CONFIG_ATA_OVER_ETH=m
++CONFIG_EEPROM_AT24=m
++CONFIG_TI_ST=m
++CONFIG_SCSI=y
++# CONFIG_SCSI_PROC_FS is not set
++CONFIG_BLK_DEV_SD=y
++CONFIG_CHR_DEV_ST=m
++CONFIG_CHR_DEV_OSST=m
++CONFIG_BLK_DEV_SR=m
++CONFIG_CHR_DEV_SG=m
++CONFIG_SCSI_ISCSI_ATTRS=y
++CONFIG_ISCSI_TCP=m
++CONFIG_ISCSI_BOOT_SYSFS=m
++CONFIG_MD=y
++CONFIG_MD_LINEAR=m
++CONFIG_MD_RAID0=m
++CONFIG_BLK_DEV_DM=m
++CONFIG_DM_CRYPT=m
++CONFIG_DM_SNAPSHOT=m
++CONFIG_DM_MIRROR=m
++CONFIG_DM_LOG_USERSPACE=m
++CONFIG_DM_RAID=m
++CONFIG_DM_ZERO=m
++CONFIG_DM_DELAY=m
++CONFIG_NETDEVICES=y
++CONFIG_BONDING=m
++CONFIG_DUMMY=m
++CONFIG_IFB=m
++CONFIG_MACVLAN=m
++CONFIG_NETCONSOLE=m
++CONFIG_TUN=m
++CONFIG_VETH=m
++CONFIG_ENC28J60=m
++CONFIG_MDIO_BITBANG=m
++CONFIG_PPP=m
++CONFIG_PPP_BSDCOMP=m
++CONFIG_PPP_DEFLATE=m
++CONFIG_PPP_FILTER=y
++CONFIG_PPP_MPPE=m
++CONFIG_PPP_MULTILINK=y
++CONFIG_PPPOATM=m
++CONFIG_PPPOE=m
++CONFIG_PPPOL2TP=m
++CONFIG_PPP_ASYNC=m
++CONFIG_PPP_SYNC_TTY=m
++CONFIG_SLIP=m
++CONFIG_SLIP_COMPRESSED=y
++CONFIG_SLIP_SMART=y
++CONFIG_USB_CATC=m
++CONFIG_USB_KAWETH=m
++CONFIG_USB_PEGASUS=m
++CONFIG_USB_RTL8150=m
++CONFIG_USB_RTL8152=m
++CONFIG_USB_USBNET=y
++CONFIG_USB_NET_AX8817X=m
++CONFIG_USB_NET_AX88179_178A=m
++CONFIG_USB_NET_CDCETHER=m
++CONFIG_USB_NET_CDC_EEM=m
++CONFIG_USB_NET_CDC_NCM=m
++CONFIG_USB_NET_HUAWEI_CDC_NCM=m
++CONFIG_USB_NET_CDC_MBIM=m
++CONFIG_USB_NET_DM9601=m
++CONFIG_USB_NET_SR9700=m
++CONFIG_USB_NET_SR9800=m
++CONFIG_USB_NET_SMSC75XX=m
++CONFIG_USB_NET_SMSC95XX=y
++CONFIG_USB_NET_GL620A=m
++CONFIG_USB_NET_NET1080=m
++CONFIG_USB_NET_PLUSB=m
++CONFIG_USB_NET_MCS7830=m
++CONFIG_USB_NET_CDC_SUBSET=m
++CONFIG_USB_ALI_M5632=y
++CONFIG_USB_AN2720=y
++CONFIG_USB_EPSON2888=y
++CONFIG_USB_KC2190=y
++CONFIG_USB_NET_ZAURUS=m
++CONFIG_USB_NET_CX82310_ETH=m
++CONFIG_USB_NET_KALMIA=m
++CONFIG_USB_NET_QMI_WWAN=m
++CONFIG_USB_HSO=m
++CONFIG_USB_NET_INT51X1=m
++CONFIG_USB_IPHETH=m
++CONFIG_USB_SIERRA_NET=m
++CONFIG_USB_VL600=m
++CONFIG_LIBERTAS_THINFIRM=m
++CONFIG_LIBERTAS_THINFIRM_USB=m
++CONFIG_AT76C50X_USB=m
++CONFIG_USB_ZD1201=m
++CONFIG_USB_NET_RNDIS_WLAN=m
++CONFIG_RTL8187=m
++CONFIG_MAC80211_HWSIM=m
++CONFIG_ATH_CARDS=m
++CONFIG_ATH9K=m
++CONFIG_ATH9K_HTC=m
++CONFIG_CARL9170=m
++CONFIG_ATH6KL=m
++CONFIG_ATH6KL_USB=m
++CONFIG_AR5523=m
++CONFIG_B43=m
++# CONFIG_B43_PHY_N is not set
++CONFIG_B43LEGACY=m
++CONFIG_BRCMFMAC=m
++CONFIG_BRCMFMAC_USB=y
++CONFIG_HOSTAP=m
++CONFIG_LIBERTAS=m
++CONFIG_LIBERTAS_USB=m
++CONFIG_LIBERTAS_SDIO=m
++CONFIG_P54_COMMON=m
++CONFIG_P54_USB=m
++CONFIG_RT2X00=m
++CONFIG_RT2500USB=m
++CONFIG_RT73USB=m
++CONFIG_RT2800USB=m
++CONFIG_RT2800USB_RT3573=y
++CONFIG_RT2800USB_RT53XX=y
++CONFIG_RT2800USB_RT55XX=y
++CONFIG_RT2800USB_UNKNOWN=y
++CONFIG_RTL8192CU=m
++CONFIG_ZD1211RW=m
++CONFIG_MWIFIEX=m
++CONFIG_MWIFIEX_SDIO=m
++CONFIG_WIMAX_I2400M_USB=m
++CONFIG_INPUT_POLLDEV=m
++# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
++CONFIG_INPUT_JOYDEV=m
++CONFIG_INPUT_EVDEV=m
++# CONFIG_KEYBOARD_ATKBD is not set
++CONFIG_KEYBOARD_GPIO=m
++# CONFIG_INPUT_MOUSE is not set
++CONFIG_INPUT_JOYSTICK=y
++CONFIG_JOYSTICK_IFORCE=m
++CONFIG_JOYSTICK_IFORCE_USB=y
++CONFIG_JOYSTICK_XPAD=m
++CONFIG_JOYSTICK_XPAD_FF=y
++CONFIG_JOYSTICK_RPISENSE=m
++CONFIG_INPUT_TOUCHSCREEN=y
++CONFIG_TOUCHSCREEN_ADS7846=m
++CONFIG_TOUCHSCREEN_EGALAX=m
++CONFIG_TOUCHSCREEN_RPI_FT5406=m
++CONFIG_TOUCHSCREEN_USB_COMPOSITE=m
++CONFIG_TOUCHSCREEN_STMPE=m
++CONFIG_INPUT_MISC=y
++CONFIG_INPUT_AD714X=m
++CONFIG_INPUT_ATI_REMOTE2=m
++CONFIG_INPUT_KEYSPAN_REMOTE=m
++CONFIG_INPUT_POWERMATE=m
++CONFIG_INPUT_YEALINK=m
++CONFIG_INPUT_CM109=m
++CONFIG_INPUT_UINPUT=m
++CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
++CONFIG_INPUT_ADXL34X=m
++CONFIG_INPUT_CMA3000=m
++CONFIG_SERIO=m
++CONFIG_SERIO_RAW=m
++CONFIG_GAMEPORT=m
++CONFIG_GAMEPORT_NS558=m
++CONFIG_GAMEPORT_L4=m
++CONFIG_DEVPTS_MULTIPLE_INSTANCES=y
++# CONFIG_LEGACY_PTYS is not set
++# CONFIG_DEVKMEM is not set
++CONFIG_SERIAL_8250=y
++# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
++CONFIG_SERIAL_8250_CONSOLE=y
++# CONFIG_SERIAL_8250_DMA is not set
++CONFIG_SERIAL_8250_NR_UARTS=1
++CONFIG_SERIAL_8250_RUNTIME_UARTS=0
++CONFIG_SERIAL_AMBA_PL011=y
++CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
++CONFIG_SERIAL_OF_PLATFORM=y
++CONFIG_TTY_PRINTK=y
++CONFIG_HW_RANDOM=y
++CONFIG_HW_RANDOM_BCM2835=m
++CONFIG_HW_RANDOM_BCM2708=m
++CONFIG_RAW_DRIVER=y
++CONFIG_BRCM_CHAR_DRIVERS=y
++CONFIG_BCM_VC_CMA=y
++CONFIG_BCM_VCIO=y
++CONFIG_BCM_VC_SM=y
++CONFIG_I2C=y
++CONFIG_I2C_CHARDEV=m
++CONFIG_I2C_BCM2708=m
++CONFIG_SPI=y
++CONFIG_SPI_BCM2835=m
++CONFIG_SPI_BCM2708=m
++CONFIG_SPI_SPIDEV=y
++CONFIG_PPS=m
++CONFIG_PPS_CLIENT_LDISC=m
++CONFIG_PPS_CLIENT_GPIO=m
++CONFIG_GPIO_SYSFS=y
++CONFIG_GPIO_ARIZONA=m
++CONFIG_GPIO_STMPE=y
++CONFIG_W1=m
++CONFIG_W1_MASTER_DS2490=m
++CONFIG_W1_MASTER_DS2482=m
++CONFIG_W1_MASTER_DS1WM=m
++CONFIG_W1_MASTER_GPIO=m
++CONFIG_W1_SLAVE_THERM=m
++CONFIG_W1_SLAVE_SMEM=m
++CONFIG_W1_SLAVE_DS2408=m
++CONFIG_W1_SLAVE_DS2413=m
++CONFIG_W1_SLAVE_DS2406=m
++CONFIG_W1_SLAVE_DS2423=m
++CONFIG_W1_SLAVE_DS2431=m
++CONFIG_W1_SLAVE_DS2433=m
++CONFIG_W1_SLAVE_DS2760=m
++CONFIG_W1_SLAVE_DS2780=m
++CONFIG_W1_SLAVE_DS2781=m
++CONFIG_W1_SLAVE_DS28E04=m
++CONFIG_W1_SLAVE_BQ27000=m
++CONFIG_BATTERY_DS2760=m
++CONFIG_POWER_RESET=y
++CONFIG_POWER_RESET_GPIO=y
++CONFIG_HWMON=m
++CONFIG_SENSORS_SHT21=m
++CONFIG_SENSORS_SHTC1=m
++CONFIG_THERMAL=y
++CONFIG_THERMAL_BCM2835=y
++CONFIG_WATCHDOG=y
++CONFIG_BCM2708_WDT=m
++CONFIG_BCM2835_WDT=m
++CONFIG_UCB1400_CORE=m
++CONFIG_MFD_STMPE=y
++CONFIG_STMPE_SPI=y
++CONFIG_MFD_ARIZONA_I2C=m
++CONFIG_MFD_ARIZONA_SPI=m
++CONFIG_MFD_WM5102=y
++CONFIG_MEDIA_SUPPORT=m
++CONFIG_MEDIA_CAMERA_SUPPORT=y
++CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
++CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
++CONFIG_MEDIA_RADIO_SUPPORT=y
++CONFIG_MEDIA_RC_SUPPORT=y
++CONFIG_MEDIA_CONTROLLER=y
++CONFIG_LIRC=m
++CONFIG_RC_DEVICES=y
++CONFIG_RC_ATI_REMOTE=m
++CONFIG_IR_IMON=m
++CONFIG_IR_MCEUSB=m
++CONFIG_IR_REDRAT3=m
++CONFIG_IR_STREAMZAP=m
++CONFIG_IR_IGUANA=m
++CONFIG_IR_TTUSBIR=m
++CONFIG_RC_LOOPBACK=m
++CONFIG_IR_GPIO_CIR=m
++CONFIG_MEDIA_USB_SUPPORT=y
++CONFIG_USB_VIDEO_CLASS=m
++CONFIG_USB_M5602=m
++CONFIG_USB_STV06XX=m
++CONFIG_USB_GL860=m
++CONFIG_USB_GSPCA_BENQ=m
++CONFIG_USB_GSPCA_CONEX=m
++CONFIG_USB_GSPCA_CPIA1=m
++CONFIG_USB_GSPCA_DTCS033=m
++CONFIG_USB_GSPCA_ETOMS=m
++CONFIG_USB_GSPCA_FINEPIX=m
++CONFIG_USB_GSPCA_JEILINJ=m
++CONFIG_USB_GSPCA_JL2005BCD=m
++CONFIG_USB_GSPCA_KINECT=m
++CONFIG_USB_GSPCA_KONICA=m
++CONFIG_USB_GSPCA_MARS=m
++CONFIG_USB_GSPCA_MR97310A=m
++CONFIG_USB_GSPCA_NW80X=m
++CONFIG_USB_GSPCA_OV519=m
++CONFIG_USB_GSPCA_OV534=m
++CONFIG_USB_GSPCA_OV534_9=m
++CONFIG_USB_GSPCA_PAC207=m
++CONFIG_USB_GSPCA_PAC7302=m
++CONFIG_USB_GSPCA_PAC7311=m
++CONFIG_USB_GSPCA_SE401=m
++CONFIG_USB_GSPCA_SN9C2028=m
++CONFIG_USB_GSPCA_SN9C20X=m
++CONFIG_USB_GSPCA_SONIXB=m
++CONFIG_USB_GSPCA_SONIXJ=m
++CONFIG_USB_GSPCA_SPCA500=m
++CONFIG_USB_GSPCA_SPCA501=m
++CONFIG_USB_GSPCA_SPCA505=m
++CONFIG_USB_GSPCA_SPCA506=m
++CONFIG_USB_GSPCA_SPCA508=m
++CONFIG_USB_GSPCA_SPCA561=m
++CONFIG_USB_GSPCA_SPCA1528=m
++CONFIG_USB_GSPCA_SQ905=m
++CONFIG_USB_GSPCA_SQ905C=m
++CONFIG_USB_GSPCA_SQ930X=m
++CONFIG_USB_GSPCA_STK014=m
++CONFIG_USB_GSPCA_STK1135=m
++CONFIG_USB_GSPCA_STV0680=m
++CONFIG_USB_GSPCA_SUNPLUS=m
++CONFIG_USB_GSPCA_T613=m
++CONFIG_USB_GSPCA_TOPRO=m
++CONFIG_USB_GSPCA_TV8532=m
++CONFIG_USB_GSPCA_VC032X=m
++CONFIG_USB_GSPCA_VICAM=m
++CONFIG_USB_GSPCA_XIRLINK_CIT=m
++CONFIG_USB_GSPCA_ZC3XX=m
++CONFIG_USB_PWC=m
++CONFIG_VIDEO_CPIA2=m
++CONFIG_USB_ZR364XX=m
++CONFIG_USB_STKWEBCAM=m
++CONFIG_USB_S2255=m
++CONFIG_VIDEO_USBTV=m
++CONFIG_VIDEO_PVRUSB2=m
++CONFIG_VIDEO_HDPVR=m
++CONFIG_VIDEO_USBVISION=m
++CONFIG_VIDEO_STK1160_COMMON=m
++CONFIG_VIDEO_STK1160_AC97=y
++CONFIG_VIDEO_GO7007=m
++CONFIG_VIDEO_GO7007_USB=m
++CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m
++CONFIG_VIDEO_AU0828=m
++CONFIG_VIDEO_AU0828_RC=y
++CONFIG_VIDEO_CX231XX=m
++CONFIG_VIDEO_CX231XX_ALSA=m
++CONFIG_VIDEO_CX231XX_DVB=m
++CONFIG_VIDEO_TM6000=m
++CONFIG_VIDEO_TM6000_ALSA=m
++CONFIG_VIDEO_TM6000_DVB=m
++CONFIG_DVB_USB=m
++CONFIG_DVB_USB_A800=m
++CONFIG_DVB_USB_DIBUSB_MB=m
++CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y
++CONFIG_DVB_USB_DIBUSB_MC=m
++CONFIG_DVB_USB_DIB0700=m
++CONFIG_DVB_USB_UMT_010=m
++CONFIG_DVB_USB_CXUSB=m
++CONFIG_DVB_USB_M920X=m
++CONFIG_DVB_USB_DIGITV=m
++CONFIG_DVB_USB_VP7045=m
++CONFIG_DVB_USB_VP702X=m
++CONFIG_DVB_USB_GP8PSK=m
++CONFIG_DVB_USB_NOVA_T_USB2=m
++CONFIG_DVB_USB_TTUSB2=m
++CONFIG_DVB_USB_DTT200U=m
++CONFIG_DVB_USB_OPERA1=m
++CONFIG_DVB_USB_AF9005=m
++CONFIG_DVB_USB_AF9005_REMOTE=m
++CONFIG_DVB_USB_PCTV452E=m
++CONFIG_DVB_USB_DW2102=m
++CONFIG_DVB_USB_CINERGY_T2=m
++CONFIG_DVB_USB_DTV5100=m
++CONFIG_DVB_USB_FRIIO=m
++CONFIG_DVB_USB_AZ6027=m
++CONFIG_DVB_USB_TECHNISAT_USB2=m
++CONFIG_DVB_USB_V2=m
++CONFIG_DVB_USB_AF9015=m
++CONFIG_DVB_USB_AF9035=m
++CONFIG_DVB_USB_ANYSEE=m
++CONFIG_DVB_USB_AU6610=m
++CONFIG_DVB_USB_AZ6007=m
++CONFIG_DVB_USB_CE6230=m
++CONFIG_DVB_USB_EC168=m
++CONFIG_DVB_USB_GL861=m
++CONFIG_DVB_USB_LME2510=m
++CONFIG_DVB_USB_MXL111SF=m
++CONFIG_DVB_USB_RTL28XXU=m
++CONFIG_DVB_USB_DVBSKY=m
++CONFIG_SMS_USB_DRV=m
++CONFIG_DVB_B2C2_FLEXCOP_USB=m
++CONFIG_DVB_AS102=m
++CONFIG_VIDEO_EM28XX=m
++CONFIG_VIDEO_EM28XX_V4L2=m
++CONFIG_VIDEO_EM28XX_ALSA=m
++CONFIG_VIDEO_EM28XX_DVB=m
++CONFIG_V4L_PLATFORM_DRIVERS=y
++CONFIG_VIDEO_BCM2835=y
++CONFIG_VIDEO_BCM2835_MMAL=m
++CONFIG_RADIO_SI470X=y
++CONFIG_USB_SI470X=m
++CONFIG_I2C_SI470X=m
++CONFIG_RADIO_SI4713=m
++CONFIG_I2C_SI4713=m
++CONFIG_USB_MR800=m
++CONFIG_USB_DSBR=m
++CONFIG_RADIO_SHARK=m
++CONFIG_RADIO_SHARK2=m
++CONFIG_USB_KEENE=m
++CONFIG_USB_MA901=m
++CONFIG_RADIO_TEA5764=m
++CONFIG_RADIO_SAA7706H=m
++CONFIG_RADIO_TEF6862=m
++CONFIG_RADIO_WL1273=m
++CONFIG_RADIO_WL128X=m
++# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
++CONFIG_VIDEO_UDA1342=m
++CONFIG_VIDEO_SONY_BTF_MPX=m
++CONFIG_VIDEO_TVP5150=m
++CONFIG_VIDEO_TW2804=m
++CONFIG_VIDEO_TW9903=m
++CONFIG_VIDEO_TW9906=m
++CONFIG_VIDEO_OV7640=m
++CONFIG_VIDEO_MT9V011=m
++CONFIG_FB=y
++CONFIG_FB_BCM2708=y
++CONFIG_FB_SSD1307=m
++CONFIG_FB_RPISENSE=m
++# CONFIG_BACKLIGHT_GENERIC is not set
++CONFIG_BACKLIGHT_GPIO=m
++CONFIG_FRAMEBUFFER_CONSOLE=y
++CONFIG_LOGO=y
++# CONFIG_LOGO_LINUX_MONO is not set
++# CONFIG_LOGO_LINUX_VGA16 is not set
++CONFIG_SOUND=y
++CONFIG_SND=m
++CONFIG_SND_SEQUENCER=m
++CONFIG_SND_SEQ_DUMMY=m
++CONFIG_SND_MIXER_OSS=m
++CONFIG_SND_PCM_OSS=m
++CONFIG_SND_SEQUENCER_OSS=y
++CONFIG_SND_HRTIMER=m
++CONFIG_SND_DUMMY=m
++CONFIG_SND_ALOOP=m
++CONFIG_SND_VIRMIDI=m
++CONFIG_SND_MTPAV=m
++CONFIG_SND_SERIAL_U16550=m
++CONFIG_SND_MPU401=m
++CONFIG_SND_BCM2835=m
++CONFIG_SND_USB_AUDIO=m
++CONFIG_SND_USB_UA101=m
++CONFIG_SND_USB_CAIAQ=m
++CONFIG_SND_USB_CAIAQ_INPUT=y
++CONFIG_SND_USB_6FIRE=m
++CONFIG_SND_SOC=m
++CONFIG_SND_BCM2708_SOC_I2S=m
++CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC=m
++CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS=m
++CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI=m
++CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP=m
++CONFIG_SND_BCM2708_SOC_RPI_DAC=m
++CONFIG_SND_BCM2708_SOC_RPI_PROTO=m
++CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC=m
++CONFIG_SND_SOC_WM8804_I2C=m
++CONFIG_SND_SIMPLE_CARD=m
++CONFIG_SOUND_PRIME=m
++CONFIG_HIDRAW=y
++CONFIG_HID_A4TECH=m
++CONFIG_HID_ACRUX=m
++CONFIG_HID_APPLE=m
++CONFIG_HID_BELKIN=m
++CONFIG_HID_CHERRY=m
++CONFIG_HID_CHICONY=m
++CONFIG_HID_CYPRESS=m
++CONFIG_HID_DRAGONRISE=m
++CONFIG_HID_EMS_FF=m
++CONFIG_HID_ELECOM=m
++CONFIG_HID_ELO=m
++CONFIG_HID_EZKEY=m
++CONFIG_HID_HOLTEK=m
++CONFIG_HID_KEYTOUCH=m
++CONFIG_HID_KYE=m
++CONFIG_HID_UCLOGIC=m
++CONFIG_HID_WALTOP=m
++CONFIG_HID_GYRATION=m
++CONFIG_HID_TWINHAN=m
++CONFIG_HID_KENSINGTON=m
++CONFIG_HID_LCPOWER=m
++CONFIG_HID_LOGITECH=m
++CONFIG_HID_MAGICMOUSE=m
++CONFIG_HID_MICROSOFT=m
++CONFIG_HID_MONTEREY=m
++CONFIG_HID_MULTITOUCH=m
++CONFIG_HID_NTRIG=m
++CONFIG_HID_ORTEK=m
++CONFIG_HID_PANTHERLORD=m
++CONFIG_HID_PETALYNX=m
++CONFIG_HID_PICOLCD=m
++CONFIG_HID_ROCCAT=m
++CONFIG_HID_SAMSUNG=m
++CONFIG_HID_SONY=m
++CONFIG_HID_SPEEDLINK=m
++CONFIG_HID_SUNPLUS=m
++CONFIG_HID_GREENASIA=m
++CONFIG_HID_SMARTJOYPLUS=m
++CONFIG_HID_TOPSEED=m
++CONFIG_HID_THINGM=m
++CONFIG_HID_THRUSTMASTER=m
++CONFIG_HID_WACOM=m
++CONFIG_HID_WIIMOTE=m
++CONFIG_HID_XINMO=m
++CONFIG_HID_ZEROPLUS=m
++CONFIG_HID_ZYDACRON=m
++CONFIG_HID_PID=y
++CONFIG_USB_HIDDEV=y
++CONFIG_USB=y
++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
++CONFIG_USB_MON=m
++CONFIG_USB_DWCOTG=y
++CONFIG_USB_PRINTER=m
++CONFIG_USB_STORAGE=y
++CONFIG_USB_STORAGE_REALTEK=m
++CONFIG_USB_STORAGE_DATAFAB=m
++CONFIG_USB_STORAGE_FREECOM=m
++CONFIG_USB_STORAGE_ISD200=m
++CONFIG_USB_STORAGE_USBAT=m
++CONFIG_USB_STORAGE_SDDR09=m
++CONFIG_USB_STORAGE_SDDR55=m
++CONFIG_USB_STORAGE_JUMPSHOT=m
++CONFIG_USB_STORAGE_ALAUDA=m
++CONFIG_USB_STORAGE_ONETOUCH=m
++CONFIG_USB_STORAGE_KARMA=m
++CONFIG_USB_STORAGE_CYPRESS_ATACB=m
++CONFIG_USB_STORAGE_ENE_UB6250=m
++CONFIG_USB_MDC800=m
++CONFIG_USB_MICROTEK=m
++CONFIG_USBIP_CORE=m
++CONFIG_USBIP_VHCI_HCD=m
++CONFIG_USBIP_HOST=m
++CONFIG_USB_SERIAL=m
++CONFIG_USB_SERIAL_GENERIC=y
++CONFIG_USB_SERIAL_AIRCABLE=m
++CONFIG_USB_SERIAL_ARK3116=m
++CONFIG_USB_SERIAL_BELKIN=m
++CONFIG_USB_SERIAL_CH341=m
++CONFIG_USB_SERIAL_WHITEHEAT=m
++CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
++CONFIG_USB_SERIAL_CP210X=m
++CONFIG_USB_SERIAL_CYPRESS_M8=m
++CONFIG_USB_SERIAL_EMPEG=m
++CONFIG_USB_SERIAL_FTDI_SIO=m
++CONFIG_USB_SERIAL_VISOR=m
++CONFIG_USB_SERIAL_IPAQ=m
++CONFIG_USB_SERIAL_IR=m
++CONFIG_USB_SERIAL_EDGEPORT=m
++CONFIG_USB_SERIAL_EDGEPORT_TI=m
++CONFIG_USB_SERIAL_F81232=m
++CONFIG_USB_SERIAL_GARMIN=m
++CONFIG_USB_SERIAL_IPW=m
++CONFIG_USB_SERIAL_IUU=m
++CONFIG_USB_SERIAL_KEYSPAN_PDA=m
++CONFIG_USB_SERIAL_KEYSPAN=m
++CONFIG_USB_SERIAL_KLSI=m
++CONFIG_USB_SERIAL_KOBIL_SCT=m
++CONFIG_USB_SERIAL_MCT_U232=m
++CONFIG_USB_SERIAL_METRO=m
++CONFIG_USB_SERIAL_MOS7720=m
++CONFIG_USB_SERIAL_MOS7840=m
++CONFIG_USB_SERIAL_NAVMAN=m
++CONFIG_USB_SERIAL_PL2303=m
++CONFIG_USB_SERIAL_OTI6858=m
++CONFIG_USB_SERIAL_QCAUX=m
++CONFIG_USB_SERIAL_QUALCOMM=m
++CONFIG_USB_SERIAL_SPCP8X5=m
++CONFIG_USB_SERIAL_SAFE=m
++CONFIG_USB_SERIAL_SIERRAWIRELESS=m
++CONFIG_USB_SERIAL_SYMBOL=m
++CONFIG_USB_SERIAL_TI=m
++CONFIG_USB_SERIAL_CYBERJACK=m
++CONFIG_USB_SERIAL_XIRCOM=m
++CONFIG_USB_SERIAL_OPTION=m
++CONFIG_USB_SERIAL_OMNINET=m
++CONFIG_USB_SERIAL_OPTICON=m
++CONFIG_USB_SERIAL_XSENS_MT=m
++CONFIG_USB_SERIAL_WISHBONE=m
++CONFIG_USB_SERIAL_SSU100=m
++CONFIG_USB_SERIAL_QT2=m
++CONFIG_USB_SERIAL_DEBUG=m
++CONFIG_USB_EMI62=m
++CONFIG_USB_EMI26=m
++CONFIG_USB_ADUTUX=m
++CONFIG_USB_SEVSEG=m
++CONFIG_USB_RIO500=m
++CONFIG_USB_LEGOTOWER=m
++CONFIG_USB_LCD=m
++CONFIG_USB_LED=m
++CONFIG_USB_CYPRESS_CY7C63=m
++CONFIG_USB_CYTHERM=m
++CONFIG_USB_IDMOUSE=m
++CONFIG_USB_FTDI_ELAN=m
++CONFIG_USB_APPLEDISPLAY=m
++CONFIG_USB_LD=m
++CONFIG_USB_TRANCEVIBRATOR=m
++CONFIG_USB_IOWARRIOR=m
++CONFIG_USB_TEST=m
++CONFIG_USB_ISIGHTFW=m
++CONFIG_USB_YUREX=m
++CONFIG_USB_ATM=m
++CONFIG_USB_SPEEDTOUCH=m
++CONFIG_USB_CXACRU=m
++CONFIG_USB_UEAGLEATM=m
++CONFIG_USB_XUSBATM=m
++CONFIG_MMC=y
++CONFIG_MMC_BLOCK_MINORS=32
++CONFIG_MMC_BCM2835=y
++CONFIG_MMC_BCM2835_DMA=y
++CONFIG_MMC_BCM2835_SDHOST=y
++CONFIG_MMC_SDHCI=y
++CONFIG_MMC_SDHCI_PLTFM=y
++CONFIG_MMC_SPI=m
++CONFIG_LEDS_CLASS=y
++CONFIG_LEDS_GPIO=y
++CONFIG_LEDS_TRIGGER_TIMER=y
++CONFIG_LEDS_TRIGGER_ONESHOT=y
++CONFIG_LEDS_TRIGGER_HEARTBEAT=y
++CONFIG_LEDS_TRIGGER_BACKLIGHT=y
++CONFIG_LEDS_TRIGGER_CPU=y
++CONFIG_LEDS_TRIGGER_GPIO=y
++CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
++CONFIG_LEDS_TRIGGER_TRANSIENT=m
++CONFIG_LEDS_TRIGGER_CAMERA=m
++CONFIG_LEDS_TRIGGER_INPUT=y
++CONFIG_RTC_CLASS=y
++# CONFIG_RTC_HCTOSYS is not set
++CONFIG_RTC_DRV_DS1307=m
++CONFIG_RTC_DRV_DS1374=m
++CONFIG_RTC_DRV_DS1672=m
++CONFIG_RTC_DRV_DS3232=m
++CONFIG_RTC_DRV_MAX6900=m
++CONFIG_RTC_DRV_RS5C372=m
++CONFIG_RTC_DRV_ISL1208=m
++CONFIG_RTC_DRV_ISL12022=m
++CONFIG_RTC_DRV_ISL12057=m
++CONFIG_RTC_DRV_X1205=m
++CONFIG_RTC_DRV_PCF2127=m
++CONFIG_RTC_DRV_PCF8523=m
++CONFIG_RTC_DRV_PCF8563=m
++CONFIG_RTC_DRV_PCF8583=m
++CONFIG_RTC_DRV_M41T80=m
++CONFIG_RTC_DRV_BQ32K=m
++CONFIG_RTC_DRV_S35390A=m
++CONFIG_RTC_DRV_FM3130=m
++CONFIG_RTC_DRV_RX8581=m
++CONFIG_RTC_DRV_RX8025=m
++CONFIG_RTC_DRV_EM3027=m
++CONFIG_RTC_DRV_RV3029C2=m
++CONFIG_RTC_DRV_M41T93=m
++CONFIG_RTC_DRV_M41T94=m
++CONFIG_RTC_DRV_DS1305=m
++CONFIG_RTC_DRV_DS1390=m
++CONFIG_RTC_DRV_MAX6902=m
++CONFIG_RTC_DRV_R9701=m
++CONFIG_RTC_DRV_RS5C348=m
++CONFIG_RTC_DRV_DS3234=m
++CONFIG_RTC_DRV_PCF2123=m
++CONFIG_RTC_DRV_RX4581=m
++CONFIG_DMADEVICES=y
++CONFIG_DMA_BCM2708=y
++CONFIG_UIO=m
++CONFIG_UIO_PDRV_GENIRQ=m
++CONFIG_STAGING=y
++CONFIG_PRISM2_USB=m
++CONFIG_R8712U=m
++CONFIG_R8188EU=m
++CONFIG_R8723AU=m
++CONFIG_VT6656=m
++CONFIG_SPEAKUP=m
++CONFIG_SPEAKUP_SYNTH_SOFT=m
++CONFIG_STAGING_MEDIA=y
++CONFIG_LIRC_STAGING=y
++CONFIG_LIRC_IMON=m
++CONFIG_LIRC_RPI=m
++CONFIG_LIRC_SASEM=m
++CONFIG_LIRC_SERIAL=m
++CONFIG_FB_TFT=m
++CONFIG_FB_TFT_AGM1264K_FL=m
++CONFIG_FB_TFT_BD663474=m
++CONFIG_FB_TFT_HX8340BN=m
++CONFIG_FB_TFT_HX8347D=m
++CONFIG_FB_TFT_HX8353D=m
++CONFIG_FB_TFT_ILI9320=m
++CONFIG_FB_TFT_ILI9325=m
++CONFIG_FB_TFT_ILI9340=m
++CONFIG_FB_TFT_ILI9341=m
++CONFIG_FB_TFT_ILI9481=m
++CONFIG_FB_TFT_ILI9486=m
++CONFIG_FB_TFT_PCD8544=m
++CONFIG_FB_TFT_RA8875=m
++CONFIG_FB_TFT_S6D02A1=m
++CONFIG_FB_TFT_S6D1121=m
++CONFIG_FB_TFT_SSD1289=m
++CONFIG_FB_TFT_SSD1306=m
++CONFIG_FB_TFT_SSD1331=m
++CONFIG_FB_TFT_SSD1351=m
++CONFIG_FB_TFT_ST7735R=m
++CONFIG_FB_TFT_TINYLCD=m
++CONFIG_FB_TFT_TLS8204=m
++CONFIG_FB_TFT_UC1701=m
++CONFIG_FB_TFT_UPD161704=m
++CONFIG_FB_TFT_WATTEROTT=m
++CONFIG_FB_FLEX=m
++CONFIG_FB_TFT_FBTFT_DEVICE=m
++CONFIG_MAILBOX=y
++CONFIG_BCM2708_MBOX=y
++CONFIG_BCM2835_MBOX=y
++# CONFIG_IOMMU_SUPPORT is not set
++CONFIG_EXTCON=m
++CONFIG_EXTCON_ARIZONA=m
++CONFIG_IIO=m
++CONFIG_IIO_BUFFER=y
++CONFIG_IIO_BUFFER_CB=y
++CONFIG_IIO_KFIFO_BUF=m
++CONFIG_DHT11=m
++CONFIG_RASPBERRYPI_FIRMWARE=y
++CONFIG_EXT4_FS=y
++CONFIG_EXT4_FS_POSIX_ACL=y
++CONFIG_EXT4_FS_SECURITY=y
++CONFIG_REISERFS_FS=m
++CONFIG_REISERFS_FS_XATTR=y
++CONFIG_REISERFS_FS_POSIX_ACL=y
++CONFIG_REISERFS_FS_SECURITY=y
++CONFIG_JFS_FS=m
++CONFIG_JFS_POSIX_ACL=y
++CONFIG_JFS_SECURITY=y
++CONFIG_JFS_STATISTICS=y
++CONFIG_XFS_FS=m
++CONFIG_XFS_QUOTA=y
++CONFIG_XFS_POSIX_ACL=y
++CONFIG_XFS_RT=y
++CONFIG_GFS2_FS=m
++CONFIG_OCFS2_FS=m
++CONFIG_BTRFS_FS=m
++CONFIG_BTRFS_FS_POSIX_ACL=y
++CONFIG_NILFS2_FS=m
++CONFIG_F2FS_FS=y
++CONFIG_FANOTIFY=y
++CONFIG_QFMT_V1=m
++CONFIG_QFMT_V2=m
++CONFIG_AUTOFS4_FS=y
++CONFIG_FUSE_FS=m
++CONFIG_CUSE=m
++CONFIG_FSCACHE=y
++CONFIG_FSCACHE_STATS=y
++CONFIG_FSCACHE_HISTOGRAM=y
++CONFIG_CACHEFILES=y
++CONFIG_ISO9660_FS=m
++CONFIG_JOLIET=y
++CONFIG_ZISOFS=y
++CONFIG_UDF_FS=m
++CONFIG_MSDOS_FS=y
++CONFIG_VFAT_FS=y
++CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
++CONFIG_NTFS_FS=m
++CONFIG_NTFS_RW=y
++CONFIG_TMPFS=y
++CONFIG_TMPFS_POSIX_ACL=y
++CONFIG_CONFIGFS_FS=y
++CONFIG_ECRYPT_FS=m
++CONFIG_HFS_FS=m
++CONFIG_HFSPLUS_FS=m
++CONFIG_SQUASHFS=m
++CONFIG_SQUASHFS_XATTR=y
++CONFIG_SQUASHFS_LZO=y
++CONFIG_SQUASHFS_XZ=y
++CONFIG_NFS_FS=y
++CONFIG_NFS_V3_ACL=y
++CONFIG_NFS_V4=y
++CONFIG_NFS_SWAP=y
++CONFIG_ROOT_NFS=y
++CONFIG_NFS_FSCACHE=y
++CONFIG_NFSD=m
++CONFIG_NFSD_V3_ACL=y
++CONFIG_NFSD_V4=y
++CONFIG_CIFS=m
++CONFIG_CIFS_WEAK_PW_HASH=y
++CONFIG_CIFS_UPCALL=y
++CONFIG_CIFS_XATTR=y
++CONFIG_CIFS_POSIX=y
++CONFIG_9P_FS=m
++CONFIG_9P_FS_POSIX_ACL=y
++CONFIG_NLS_DEFAULT="utf8"
++CONFIG_NLS_CODEPAGE_437=y
++CONFIG_NLS_CODEPAGE_737=m
++CONFIG_NLS_CODEPAGE_775=m
++CONFIG_NLS_CODEPAGE_850=m
++CONFIG_NLS_CODEPAGE_852=m
++CONFIG_NLS_CODEPAGE_855=m
++CONFIG_NLS_CODEPAGE_857=m
++CONFIG_NLS_CODEPAGE_860=m
++CONFIG_NLS_CODEPAGE_861=m
++CONFIG_NLS_CODEPAGE_862=m
++CONFIG_NLS_CODEPAGE_863=m
++CONFIG_NLS_CODEPAGE_864=m
++CONFIG_NLS_CODEPAGE_865=m
++CONFIG_NLS_CODEPAGE_866=m
++CONFIG_NLS_CODEPAGE_869=m
++CONFIG_NLS_CODEPAGE_936=m
++CONFIG_NLS_CODEPAGE_950=m
++CONFIG_NLS_CODEPAGE_932=m
++CONFIG_NLS_CODEPAGE_949=m
++CONFIG_NLS_CODEPAGE_874=m
++CONFIG_NLS_ISO8859_8=m
++CONFIG_NLS_CODEPAGE_1250=m
++CONFIG_NLS_CODEPAGE_1251=m
++CONFIG_NLS_ASCII=y
++CONFIG_NLS_ISO8859_1=m
++CONFIG_NLS_ISO8859_2=m
++CONFIG_NLS_ISO8859_3=m
++CONFIG_NLS_ISO8859_4=m
++CONFIG_NLS_ISO8859_5=m
++CONFIG_NLS_ISO8859_6=m
++CONFIG_NLS_ISO8859_7=m
++CONFIG_NLS_ISO8859_9=m
++CONFIG_NLS_ISO8859_13=m
++CONFIG_NLS_ISO8859_14=m
++CONFIG_NLS_ISO8859_15=m
++CONFIG_NLS_KOI8_R=m
++CONFIG_NLS_KOI8_U=m
++CONFIG_DLM=m
++CONFIG_PRINTK_TIME=y
++CONFIG_BOOT_PRINTK_DELAY=y
++CONFIG_DEBUG_MEMORY_INIT=y
++CONFIG_DETECT_HUNG_TASK=y
++CONFIG_TIMER_STATS=y
++# CONFIG_DEBUG_PREEMPT is not set
++CONFIG_LATENCYTOP=y
++CONFIG_IRQSOFF_TRACER=y
++CONFIG_SCHED_TRACER=y
++CONFIG_STACK_TRACER=y
++CONFIG_BLK_DEV_IO_TRACE=y
++# CONFIG_KPROBE_EVENT is not set
++CONFIG_FUNCTION_PROFILER=y
++CONFIG_KGDB=y
++CONFIG_KGDB_KDB=y
++CONFIG_KDB_KEYBOARD=y
++CONFIG_CRYPTO_USER=m
++CONFIG_CRYPTO_CRYPTD=m
++CONFIG_CRYPTO_CBC=y
++CONFIG_CRYPTO_CTS=m
++CONFIG_CRYPTO_XTS=m
++CONFIG_CRYPTO_XCBC=m
++CONFIG_CRYPTO_SHA512=m
++CONFIG_CRYPTO_TGR192=m
++CONFIG_CRYPTO_WP512=m
++CONFIG_CRYPTO_CAST5=m
++CONFIG_CRYPTO_DES=y
++# CONFIG_CRYPTO_ANSI_CPRNG is not set
++# CONFIG_CRYPTO_HW is not set
++CONFIG_ARM_CRYPTO=y
++CONFIG_CRYPTO_SHA1_ARM=m
++CONFIG_CRYPTO_AES_ARM=m
++CONFIG_CRC_ITU_T=y
++CONFIG_LIBCRC32C=y
+diff -Nur linux-4.1.3/arch/arm/include/asm/entry-macro-multi.S linux-xbian-rpi/arch/arm/include/asm/entry-macro-multi.S
+--- linux-4.1.3/arch/arm/include/asm/entry-macro-multi.S 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/arch/arm/include/asm/entry-macro-multi.S 2015-07-28 01:20:58.170137709 +0200
+@@ -1,5 +1,6 @@
+ #include <asm/assembler.h>
+
++#ifndef CONFIG_ARCH_BCM2709
+ /*
+ * Interrupt handling. Preserves r7, r8, r9
+ */
+@@ -28,6 +29,7 @@
+ #endif
+ 9997:
+ .endm
++#endif
+
+ .macro arch_irq_handler, symbol_name
+ .align 5
+diff -Nur linux-4.1.3/arch/arm/include/asm/irqflags.h linux-xbian-rpi/arch/arm/include/asm/irqflags.h
+--- linux-4.1.3/arch/arm/include/asm/irqflags.h 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/arch/arm/include/asm/irqflags.h 2015-07-28 01:20:58.170137709 +0200
+@@ -145,12 +145,22 @@
+ }
+
+ /*
+- * restore saved IRQ & FIQ state
++ * restore saved IRQ state
+ */
+ static inline void arch_local_irq_restore(unsigned long flags)
+ {
+- asm volatile(
+- " msr " IRQMASK_REG_NAME_W ", %0 @ local_irq_restore"
++ unsigned long temp = 0;
++ flags &= ~(1 << 6);
++ asm volatile (
++ " mrs %0, cpsr"
++ : "=r" (temp)
++ :
++ : "memory", "cc");
++ /* Preserve FIQ bit */
++ temp &= (1 << 6);
++ flags = flags | temp;
++ asm volatile (
++ " msr cpsr_c, %0 @ local_irq_restore"
+ :
+ : "r" (flags)
+ : "memory", "cc");
+diff -Nur linux-4.1.3/arch/arm/include/asm/string.h linux-xbian-rpi/arch/arm/include/asm/string.h
+--- linux-4.1.3/arch/arm/include/asm/string.h 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/arch/arm/include/asm/string.h 2015-07-28 01:20:58.170137709 +0200
+@@ -24,6 +24,11 @@
+ #define __HAVE_ARCH_MEMSET
+ extern void * memset(void *, int, __kernel_size_t);
+
++#ifdef CONFIG_MACH_BCM2708
++#define __HAVE_ARCH_MEMCMP
++extern int memcmp(const void *, const void *, size_t);
++#endif
++
+ extern void __memzero(void *ptr, __kernel_size_t n);
+
+ #define memset(p,v,n) \
+diff -Nur linux-4.1.3/arch/arm/include/asm/uaccess.h linux-xbian-rpi/arch/arm/include/asm/uaccess.h
+--- linux-4.1.3/arch/arm/include/asm/uaccess.h 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/arch/arm/include/asm/uaccess.h 2015-07-28 01:20:58.170137709 +0200
+@@ -475,6 +475,7 @@
+
+ #ifdef CONFIG_MMU
+ extern unsigned long __must_check __copy_from_user(void *to, const void __user *from, unsigned long n);
++extern unsigned long __must_check __copy_from_user_std(void *to, const void __user *from, unsigned long n);
+ extern unsigned long __must_check __copy_to_user(void __user *to, const void *from, unsigned long n);
+ extern unsigned long __must_check __copy_to_user_std(void __user *to, const void *from, unsigned long n);
+ extern unsigned long __must_check __clear_user(void __user *addr, unsigned long n);
+diff -Nur linux-4.1.3/arch/arm/Kconfig linux-xbian-rpi/arch/arm/Kconfig
+--- linux-4.1.3/arch/arm/Kconfig 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/arch/arm/Kconfig 2015-07-28 01:20:58.162166151 +0200
+@@ -314,6 +314,42 @@
+ default ARCH_VERSATILE if !MMU
+ default ARCH_MULTIPLATFORM if MMU
+
++config ARCH_BCM2708
++ bool "Broadcom BCM2708 family"
++ select CPU_V6
++ select ARM_AMBA
++ select HAVE_SCHED_CLOCK
++ select NEED_MACH_GPIO_H
++ select NEED_MACH_MEMORY_H
++ select COMMON_CLK
++ select ARCH_HAS_CPUFREQ
++ select GENERIC_CLOCKEVENTS
++ select ARM_ERRATA_411920
++ select MACH_BCM2708
++ select VC4
++ select FIQ
++ help
++ This enables support for Broadcom BCM2708 boards.
++
++config ARCH_BCM2709
++ bool "Broadcom BCM2709 family"
++ select ARCH_HAS_BARRIERS if SMP
++ select CPU_V7
++ select HAVE_SMP
++ select ARM_AMBA
++ select MIGHT_HAVE_CACHE_L2X0
++ select HAVE_SCHED_CLOCK
++ select NEED_MACH_MEMORY_H
++ select NEED_MACH_IO_H
++ select COMMON_CLK
++ select ARCH_HAS_CPUFREQ
++ select GENERIC_CLOCKEVENTS
++ select MACH_BCM2709
++ select VC4
++ select FIQ
++ help
++ This enables support for Broadcom BCM2709 boards.
++
+ config ARCH_MULTIPLATFORM
+ bool "Allow multiple platforms to be selected"
+ depends on MMU
+@@ -823,6 +859,9 @@
+ # Kconfigs may be included either alphabetically (according to the
+ # plat- suffix) or along side the corresponding mach-* source.
+ #
++source "arch/arm/mach-bcm2708/Kconfig"
++source "arch/arm/mach-bcm2709/Kconfig"
++
+ source "arch/arm/mach-mvebu/Kconfig"
+
+ source "arch/arm/mach-alpine/Kconfig"
+diff -Nur linux-4.1.3/arch/arm/Kconfig.debug linux-xbian-rpi/arch/arm/Kconfig.debug
+--- linux-4.1.3/arch/arm/Kconfig.debug 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/arch/arm/Kconfig.debug 2015-07-28 01:20:58.162166151 +0200
+@@ -1197,6 +1197,14 @@
+ options; the platform specific options are deprecated
+ and will be soon removed.
+
++ config DEBUG_BCM2708_UART0
++ bool "Broadcom BCM2708 UART0 (PL011)"
++ depends on MACH_BCM2708
++ help
++ Say Y here if you want the debug print routines to direct
++ their output to UART 0. The port must have been initialised
++ by the boot-loader before use.
++
+ endchoice
+
+ config DEBUG_AT91_UART
+diff -Nur linux-4.1.3/arch/arm/kernel/fiqasm.S linux-xbian-rpi/arch/arm/kernel/fiqasm.S
+--- linux-4.1.3/arch/arm/kernel/fiqasm.S 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/arch/arm/kernel/fiqasm.S 2015-07-28 01:20:58.170137709 +0200
+@@ -47,3 +47,7 @@
+ mov r0, r0 @ avoid hazard prior to ARMv4
+ ret lr
+ ENDPROC(__get_fiq_regs)
++
++ENTRY(__FIQ_Branch)
++ mov pc, r8
++ENDPROC(__FIQ_Branch)
+diff -Nur linux-4.1.3/arch/arm/kernel/head.S linux-xbian-rpi/arch/arm/kernel/head.S
+--- linux-4.1.3/arch/arm/kernel/head.S 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/arch/arm/kernel/head.S 2015-07-28 01:20:58.170137709 +0200
+@@ -680,6 +680,14 @@
+ ldrcc r7, [r4], #4 @ use branch for delay slot
+ bcc 1b
+ ret lr
++ nop
++ nop
++ nop
++ nop
++ nop
++ nop
++ nop
++ nop
+ #endif
+ ENDPROC(__fixup_a_pv_table)
+
+diff -Nur linux-4.1.3/arch/arm/kernel/process.c linux-xbian-rpi/arch/arm/kernel/process.c
+--- linux-4.1.3/arch/arm/kernel/process.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/arch/arm/kernel/process.c 2015-07-28 01:20:58.170137709 +0200
+@@ -28,6 +28,7 @@
+ #include <linux/random.h>
+ #include <linux/hw_breakpoint.h>
+ #include <linux/leds.h>
++#include <linux/delay.h>
+
+ #include <asm/processor.h>
+ #include <asm/thread_notify.h>
+@@ -98,6 +99,16 @@
+ }
+ #endif
+
++char bcm2708_reboot_mode = 'h';
++
++int __init reboot_setup(char *str)
++{
++ bcm2708_reboot_mode = str[0];
++ return 1;
++}
++
++__setup("reboot=", reboot_setup);
++
+ void __show_regs(struct pt_regs *regs)
+ {
+ unsigned long flags;
+diff -Nur linux-4.1.3/arch/arm/lib/arm-mem.h linux-xbian-rpi/arch/arm/lib/arm-mem.h
+--- linux-4.1.3/arch/arm/lib/arm-mem.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/lib/arm-mem.h 2015-07-28 01:20:58.170137709 +0200
+@@ -0,0 +1,159 @@
++/*
++Copyright (c) 2013, Raspberry Pi Foundation
++Copyright (c) 2013, RISC OS Open Ltd
++All rights reserved.
++
++Redistribution and use in source and binary forms, with or without
++modification, are permitted provided that the following conditions are met:
++ * Redistributions of source code must retain the above copyright
++ notice, this list of conditions and the following disclaimer.
++ * Redistributions in binary form must reproduce the above copyright
++ notice, this list of conditions and the following disclaimer in the
++ documentation and/or other materials provided with the distribution.
++ * Neither the name of the copyright holder nor the
++ names of its contributors may be used to endorse or promote products
++ derived from this software without specific prior written permission.
++
++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY
++DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++*/
++
++.macro myfunc fname
++ .func fname
++ .global fname
++fname:
++.endm
++
++.macro preload_leading_step1 backwards, ptr, base
++/* If the destination is already 16-byte aligned, then we need to preload
++ * between 0 and prefetch_distance (inclusive) cache lines ahead so there
++ * are no gaps when the inner loop starts.
++ */
++ .if backwards
++ sub ptr, base, #1
++ bic ptr, ptr, #31
++ .else
++ bic ptr, base, #31
++ .endif
++ .set OFFSET, 0
++ .rept prefetch_distance+1
++ pld [ptr, #OFFSET]
++ .if backwards
++ .set OFFSET, OFFSET-32
++ .else
++ .set OFFSET, OFFSET+32
++ .endif
++ .endr
++.endm
++
++.macro preload_leading_step2 backwards, ptr, base, leading_bytes, tmp
++/* However, if the destination is not 16-byte aligned, we may need to
++ * preload one more cache line than that. The question we need to ask is:
++ * are the leading bytes more than the amount by which the source
++ * pointer will be rounded down for preloading, and if so, by how many
++ * cache lines?
++ */
++ .if backwards
++/* Here we compare against how many bytes we are into the
++ * cache line, counting down from the highest such address.
++ * Effectively, we want to calculate
++ * leading_bytes = dst&15
++ * cacheline_offset = 31-((src-leading_bytes-1)&31)
++ * extra_needed = leading_bytes - cacheline_offset
++ * and test if extra_needed is <= 0, or rearranging:
++ * leading_bytes + (src-leading_bytes-1)&31 <= 31
++ */
++ mov tmp, base, lsl #32-5
++ sbc tmp, tmp, leading_bytes, lsl #32-5
++ adds tmp, tmp, leading_bytes, lsl #32-5
++ bcc 61f
++ pld [ptr, #-32*(prefetch_distance+1)]
++ .else
++/* Effectively, we want to calculate
++ * leading_bytes = (-dst)&15
++ * cacheline_offset = (src+leading_bytes)&31
++ * extra_needed = leading_bytes - cacheline_offset
++ * and test if extra_needed is <= 0.
++ */
++ mov tmp, base, lsl #32-5
++ add tmp, tmp, leading_bytes, lsl #32-5
++ rsbs tmp, tmp, leading_bytes, lsl #32-5
++ bls 61f
++ pld [ptr, #32*(prefetch_distance+1)]
++ .endif
++61:
++.endm
++
++.macro preload_trailing backwards, base, remain, tmp
++ /* We need either 0, 1 or 2 extra preloads */
++ .if backwards
++ rsb tmp, base, #0
++ mov tmp, tmp, lsl #32-5
++ .else
++ mov tmp, base, lsl #32-5
++ .endif
++ adds tmp, tmp, remain, lsl #32-5
++ adceqs tmp, tmp, #0
++ /* The instruction above has two effects: ensures Z is only
++ * set if C was clear (so Z indicates that both shifted quantities
++ * were 0), and clears C if Z was set (so C indicates that the sum
++ * of the shifted quantities was greater and not equal to 32) */
++ beq 82f
++ .if backwards
++ sub tmp, base, #1
++ bic tmp, tmp, #31
++ .else
++ bic tmp, base, #31
++ .endif
++ bcc 81f
++ .if backwards
++ pld [tmp, #-32*(prefetch_distance+1)]
++81:
++ pld [tmp, #-32*prefetch_distance]
++ .else
++ pld [tmp, #32*(prefetch_distance+2)]
++81:
++ pld [tmp, #32*(prefetch_distance+1)]
++ .endif
++82:
++.endm
++
++.macro preload_all backwards, narrow_case, shift, base, remain, tmp0, tmp1
++ .if backwards
++ sub tmp0, base, #1
++ bic tmp0, tmp0, #31
++ pld [tmp0]
++ sub tmp1, base, remain, lsl #shift
++ .else
++ bic tmp0, base, #31
++ pld [tmp0]
++ add tmp1, base, remain, lsl #shift
++ sub tmp1, tmp1, #1
++ .endif
++ bic tmp1, tmp1, #31
++ cmp tmp1, tmp0
++ beq 92f
++ .if narrow_case
++ /* In this case, all the data fits in either 1 or 2 cache lines */
++ pld [tmp1]
++ .else
++91:
++ .if backwards
++ sub tmp0, tmp0, #32
++ .else
++ add tmp0, tmp0, #32
++ .endif
++ cmp tmp0, tmp1
++ pld [tmp0]
++ bne 91b
++ .endif
++92:
++.endm
+diff -Nur linux-4.1.3/arch/arm/lib/copy_from_user.S linux-xbian-rpi/arch/arm/lib/copy_from_user.S
+--- linux-4.1.3/arch/arm/lib/copy_from_user.S 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/arch/arm/lib/copy_from_user.S 2015-07-28 01:20:58.170137709 +0200
+@@ -89,11 +89,13 @@
+
+ .text
+
+-ENTRY(__copy_from_user)
++ENTRY(__copy_from_user_std)
++WEAK(__copy_from_user)
+
+ #include "copy_template.S"
+
+ ENDPROC(__copy_from_user)
++ENDPROC(__copy_from_user_std)
+
+ .pushsection .fixup,"ax"
+ .align 0
+diff -Nur linux-4.1.3/arch/arm/lib/exports_rpi.c linux-xbian-rpi/arch/arm/lib/exports_rpi.c
+--- linux-4.1.3/arch/arm/lib/exports_rpi.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/lib/exports_rpi.c 2015-07-28 01:20:58.170137709 +0200
+@@ -0,0 +1,37 @@
++/**
++ * Copyright (c) 2014, Raspberry Pi (Trading) Ltd.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ * 1. Redistributions of source code must retain the above copyright
++ * notice, this list of conditions, and the following disclaimer,
++ * without modification.
++ * 2. Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * 3. The names of the above-listed copyright holders may not be used
++ * to endorse or promote products derived from this software without
++ * specific prior written permission.
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") version 2, as published by the Free
++ * Software Foundation.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++
++EXPORT_SYMBOL(memcmp);
+diff -Nur linux-4.1.3/arch/arm/lib/Makefile linux-xbian-rpi/arch/arm/lib/Makefile
+--- linux-4.1.3/arch/arm/lib/Makefile 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/arch/arm/lib/Makefile 2015-07-28 01:20:58.170137709 +0200
+@@ -6,9 +6,8 @@
+
+ lib-y := backtrace.o changebit.o csumipv6.o csumpartial.o \
+ csumpartialcopy.o csumpartialcopyuser.o clearbit.o \
+- delay.o delay-loop.o findbit.o memchr.o memcpy.o \
+- memmove.o memset.o memzero.o setbit.o \
+- strchr.o strrchr.o \
++ delay.o delay-loop.o findbit.o memchr.o memzero.o \
++ setbit.o strchr.o strrchr.o \
+ testchangebit.o testclearbit.o testsetbit.o \
+ ashldi3.o ashrdi3.o lshrdi3.o muldi3.o \
+ ucmpdi2.o lib1funcs.o div64.o \
+@@ -18,6 +17,16 @@
+ mmu-y := clear_user.o copy_page.o getuser.o putuser.o \
+ copy_from_user.o copy_to_user.o
+
++# Choose optimised implementations for Raspberry Pi
++ifeq ($(CONFIG_MACH_BCM2708),y)
++ CFLAGS_uaccess_with_memcpy.o += -DCOPY_FROM_USER_THRESHOLD=1600
++ CFLAGS_uaccess_with_memcpy.o += -DCOPY_TO_USER_THRESHOLD=672
++ obj-$(CONFIG_MODULES) += exports_rpi.o
++ lib-y += memcpy_rpi.o memmove_rpi.o memset_rpi.o memcmp_rpi.o
++else
++ lib-y += memcpy.o memmove.o memset.o
++endif
++
+ # using lib_ here won't override already available weak symbols
+ obj-$(CONFIG_UACCESS_WITH_MEMCPY) += uaccess_with_memcpy.o
+
+diff -Nur linux-4.1.3/arch/arm/lib/memcmp_rpi.S linux-xbian-rpi/arch/arm/lib/memcmp_rpi.S
+--- linux-4.1.3/arch/arm/lib/memcmp_rpi.S 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/lib/memcmp_rpi.S 2015-07-28 01:20:58.170137709 +0200
+@@ -0,0 +1,285 @@
++/*
++Copyright (c) 2013, Raspberry Pi Foundation
++Copyright (c) 2013, RISC OS Open Ltd
++All rights reserved.
++
++Redistribution and use in source and binary forms, with or without
++modification, are permitted provided that the following conditions are met:
++ * Redistributions of source code must retain the above copyright
++ notice, this list of conditions and the following disclaimer.
++ * Redistributions in binary form must reproduce the above copyright
++ notice, this list of conditions and the following disclaimer in the
++ documentation and/or other materials provided with the distribution.
++ * Neither the name of the copyright holder nor the
++ names of its contributors may be used to endorse or promote products
++ derived from this software without specific prior written permission.
++
++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY
++DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++*/
++
++#include <linux/linkage.h>
++#include "arm-mem.h"
++
++/* Prevent the stack from becoming executable */
++#if defined(__linux__) && defined(__ELF__)
++.section .note.GNU-stack,"",%progbits
++#endif
++
++ .text
++ .arch armv6
++ .object_arch armv4
++ .arm
++ .altmacro
++ .p2align 2
++
++.macro memcmp_process_head unaligned
++ .if unaligned
++ ldr DAT0, [S_1], #4
++ ldr DAT1, [S_1], #4
++ ldr DAT2, [S_1], #4
++ ldr DAT3, [S_1], #4
++ .else
++ ldmia S_1!, {DAT0, DAT1, DAT2, DAT3}
++ .endif
++ ldmia S_2!, {DAT4, DAT5, DAT6, DAT7}
++.endm
++
++.macro memcmp_process_tail
++ cmp DAT0, DAT4
++ cmpeq DAT1, DAT5
++ cmpeq DAT2, DAT6
++ cmpeq DAT3, DAT7
++ bne 200f
++.endm
++
++.macro memcmp_leading_31bytes
++ movs DAT0, OFF, lsl #31
++ ldrmib DAT0, [S_1], #1
++ ldrcsh DAT1, [S_1], #2
++ ldrmib DAT4, [S_2], #1
++ ldrcsh DAT5, [S_2], #2
++ movpl DAT0, #0
++ movcc DAT1, #0
++ movpl DAT4, #0
++ movcc DAT5, #0
++ submi N, N, #1
++ subcs N, N, #2
++ cmp DAT0, DAT4
++ cmpeq DAT1, DAT5
++ bne 200f
++ movs DAT0, OFF, lsl #29
++ ldrmi DAT0, [S_1], #4
++ ldrcs DAT1, [S_1], #4
++ ldrcs DAT2, [S_1], #4
++ ldrmi DAT4, [S_2], #4
++ ldmcsia S_2!, {DAT5, DAT6}
++ movpl DAT0, #0
++ movcc DAT1, #0
++ movcc DAT2, #0
++ movpl DAT4, #0
++ movcc DAT5, #0
++ movcc DAT6, #0
++ submi N, N, #4
++ subcs N, N, #8
++ cmp DAT0, DAT4
++ cmpeq DAT1, DAT5
++ cmpeq DAT2, DAT6
++ bne 200f
++ tst OFF, #16
++ beq 105f
++ memcmp_process_head 1
++ sub N, N, #16
++ memcmp_process_tail
++105:
++.endm
++
++.macro memcmp_trailing_15bytes unaligned
++ movs N, N, lsl #29
++ .if unaligned
++ ldrcs DAT0, [S_1], #4
++ ldrcs DAT1, [S_1], #4
++ .else
++ ldmcsia S_1!, {DAT0, DAT1}
++ .endif
++ ldrmi DAT2, [S_1], #4
++ ldmcsia S_2!, {DAT4, DAT5}
++ ldrmi DAT6, [S_2], #4
++ movcc DAT0, #0
++ movcc DAT1, #0
++ movpl DAT2, #0
++ movcc DAT4, #0
++ movcc DAT5, #0
++ movpl DAT6, #0
++ cmp DAT0, DAT4
++ cmpeq DAT1, DAT5
++ cmpeq DAT2, DAT6
++ bne 200f
++ movs N, N, lsl #2
++ ldrcsh DAT0, [S_1], #2
++ ldrmib DAT1, [S_1]
++ ldrcsh DAT4, [S_2], #2
++ ldrmib DAT5, [S_2]
++ movcc DAT0, #0
++ movpl DAT1, #0
++ movcc DAT4, #0
++ movpl DAT5, #0
++ cmp DAT0, DAT4
++ cmpeq DAT1, DAT5
++ bne 200f
++.endm
++
++.macro memcmp_long_inner_loop unaligned
++110:
++ memcmp_process_head unaligned
++ pld [S_2, #prefetch_distance*32 + 16]
++ memcmp_process_tail
++ memcmp_process_head unaligned
++ pld [S_1, OFF]
++ memcmp_process_tail
++ subs N, N, #32
++ bhs 110b
++ /* Just before the final (prefetch_distance+1) 32-byte blocks,
++ * deal with final preloads */
++ preload_trailing 0, S_1, N, DAT0
++ preload_trailing 0, S_2, N, DAT0
++ add N, N, #(prefetch_distance+2)*32 - 16
++120:
++ memcmp_process_head unaligned
++ memcmp_process_tail
++ subs N, N, #16
++ bhs 120b
++ /* Trailing words and bytes */
++ tst N, #15
++ beq 199f
++ memcmp_trailing_15bytes unaligned
++199: /* Reached end without detecting a difference */
++ mov a1, #0
++ setend le
++ pop {DAT1-DAT6, pc}
++.endm
++
++.macro memcmp_short_inner_loop unaligned
++ subs N, N, #16 /* simplifies inner loop termination */
++ blo 122f
++120:
++ memcmp_process_head unaligned
++ memcmp_process_tail
++ subs N, N, #16
++ bhs 120b
++122: /* Trailing words and bytes */
++ tst N, #15
++ beq 199f
++ memcmp_trailing_15bytes unaligned
++199: /* Reached end without detecting a difference */
++ mov a1, #0
++ setend le
++ pop {DAT1-DAT6, pc}
++.endm
++
++/*
++ * int memcmp(const void *s1, const void *s2, size_t n);
++ * On entry:
++ * a1 = pointer to buffer 1
++ * a2 = pointer to buffer 2
++ * a3 = number of bytes to compare (as unsigned chars)
++ * On exit:
++ * a1 = >0/=0/<0 if s1 >/=/< s2
++ */
++
++.set prefetch_distance, 2
++
++ENTRY(memcmp)
++ S_1 .req a1
++ S_2 .req a2
++ N .req a3
++ DAT0 .req a4
++ DAT1 .req v1
++ DAT2 .req v2
++ DAT3 .req v3
++ DAT4 .req v4
++ DAT5 .req v5
++ DAT6 .req v6
++ DAT7 .req ip
++ OFF .req lr
++
++ push {DAT1-DAT6, lr}
++ setend be /* lowest-addressed bytes are most significant */
++
++ /* To preload ahead as we go, we need at least (prefetch_distance+2) 32-byte blocks */
++ cmp N, #(prefetch_distance+3)*32 - 1
++ blo 170f
++
++ /* Long case */
++ /* Adjust N so that the decrement instruction can also test for
++ * inner loop termination. We want it to stop when there are
++ * (prefetch_distance+1) complete blocks to go. */
++ sub N, N, #(prefetch_distance+2)*32
++ preload_leading_step1 0, DAT0, S_1
++ preload_leading_step1 0, DAT1, S_2
++ tst S_2, #31
++ beq 154f
++ rsb OFF, S_2, #0 /* no need to AND with 15 here */
++ preload_leading_step2 0, DAT0, S_1, OFF, DAT2
++ preload_leading_step2 0, DAT1, S_2, OFF, DAT2
++ memcmp_leading_31bytes
++154: /* Second source now cacheline (32-byte) aligned; we have at
++ * least one prefetch to go. */
++ /* Prefetch offset is best selected such that it lies in the
++ * first 8 of each 32 bytes - but it's just as easy to aim for
++ * the first one */
++ and OFF, S_1, #31
++ rsb OFF, OFF, #32*prefetch_distance
++ tst S_1, #3
++ bne 140f
++ memcmp_long_inner_loop 0
++140: memcmp_long_inner_loop 1
++
++170: /* Short case */
++ teq N, #0
++ beq 199f
++ preload_all 0, 0, 0, S_1, N, DAT0, DAT1
++ preload_all 0, 0, 0, S_2, N, DAT0, DAT1
++ tst S_2, #3
++ beq 174f
++172: subs N, N, #1
++ blo 199f
++ ldrb DAT0, [S_1], #1
++ ldrb DAT4, [S_2], #1
++ cmp DAT0, DAT4
++ bne 200f
++ tst S_2, #3
++ bne 172b
++174: /* Second source now 4-byte aligned; we have 0 or more bytes to go */
++ tst S_1, #3
++ bne 140f
++ memcmp_short_inner_loop 0
++140: memcmp_short_inner_loop 1
++
++200: /* Difference found: determine sign. */
++ movhi a1, #1
++ movlo a1, #-1
++ setend le
++ pop {DAT1-DAT6, pc}
++
++ .unreq S_1
++ .unreq S_2
++ .unreq N
++ .unreq DAT0
++ .unreq DAT1
++ .unreq DAT2
++ .unreq DAT3
++ .unreq DAT4
++ .unreq DAT5
++ .unreq DAT6
++ .unreq DAT7
++ .unreq OFF
++ENDPROC(memcmp)
+diff -Nur linux-4.1.3/arch/arm/lib/memcpymove.h linux-xbian-rpi/arch/arm/lib/memcpymove.h
+--- linux-4.1.3/arch/arm/lib/memcpymove.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/lib/memcpymove.h 2015-07-28 01:20:58.170137709 +0200
+@@ -0,0 +1,506 @@
++/*
++Copyright (c) 2013, Raspberry Pi Foundation
++Copyright (c) 2013, RISC OS Open Ltd
++All rights reserved.
++
++Redistribution and use in source and binary forms, with or without
++modification, are permitted provided that the following conditions are met:
++ * Redistributions of source code must retain the above copyright
++ notice, this list of conditions and the following disclaimer.
++ * Redistributions in binary form must reproduce the above copyright
++ notice, this list of conditions and the following disclaimer in the
++ documentation and/or other materials provided with the distribution.
++ * Neither the name of the copyright holder nor the
++ names of its contributors may be used to endorse or promote products
++ derived from this software without specific prior written permission.
++
++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY
++DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++*/
++
++.macro unaligned_words backwards, align, use_pld, words, r0, r1, r2, r3, r4, r5, r6, r7, r8
++ .if words == 1
++ .if backwards
++ mov r1, r0, lsl #32-align*8
++ ldr r0, [S, #-4]!
++ orr r1, r1, r0, lsr #align*8
++ str r1, [D, #-4]!
++ .else
++ mov r0, r1, lsr #align*8
++ ldr r1, [S, #4]!
++ orr r0, r0, r1, lsl #32-align*8
++ str r0, [D], #4
++ .endif
++ .elseif words == 2
++ .if backwards
++ ldr r1, [S, #-4]!
++ mov r2, r0, lsl #32-align*8
++ ldr r0, [S, #-4]!
++ orr r2, r2, r1, lsr #align*8
++ mov r1, r1, lsl #32-align*8
++ orr r1, r1, r0, lsr #align*8
++ stmdb D!, {r1, r2}
++ .else
++ ldr r1, [S, #4]!
++ mov r0, r2, lsr #align*8
++ ldr r2, [S, #4]!
++ orr r0, r0, r1, lsl #32-align*8
++ mov r1, r1, lsr #align*8
++ orr r1, r1, r2, lsl #32-align*8
++ stmia D!, {r0, r1}
++ .endif
++ .elseif words == 4
++ .if backwards
++ ldmdb S!, {r2, r3}
++ mov r4, r0, lsl #32-align*8
++ ldmdb S!, {r0, r1}
++ orr r4, r4, r3, lsr #align*8
++ mov r3, r3, lsl #32-align*8
++ orr r3, r3, r2, lsr #align*8
++ mov r2, r2, lsl #32-align*8
++ orr r2, r2, r1, lsr #align*8
++ mov r1, r1, lsl #32-align*8
++ orr r1, r1, r0, lsr #align*8
++ stmdb D!, {r1, r2, r3, r4}
++ .else
++ ldmib S!, {r1, r2}
++ mov r0, r4, lsr #align*8
++ ldmib S!, {r3, r4}
++ orr r0, r0, r1, lsl #32-align*8
++ mov r1, r1, lsr #align*8
++ orr r1, r1, r2, lsl #32-align*8
++ mov r2, r2, lsr #align*8
++ orr r2, r2, r3, lsl #32-align*8
++ mov r3, r3, lsr #align*8
++ orr r3, r3, r4, lsl #32-align*8
++ stmia D!, {r0, r1, r2, r3}
++ .endif
++ .elseif words == 8
++ .if backwards
++ ldmdb S!, {r4, r5, r6, r7}
++ mov r8, r0, lsl #32-align*8
++ ldmdb S!, {r0, r1, r2, r3}
++ .if use_pld
++ pld [S, OFF]
++ .endif
++ orr r8, r8, r7, lsr #align*8
++ mov r7, r7, lsl #32-align*8
++ orr r7, r7, r6, lsr #align*8
++ mov r6, r6, lsl #32-align*8
++ orr r6, r6, r5, lsr #align*8
++ mov r5, r5, lsl #32-align*8
++ orr r5, r5, r4, lsr #align*8
++ mov r4, r4, lsl #32-align*8
++ orr r4, r4, r3, lsr #align*8
++ mov r3, r3, lsl #32-align*8
++ orr r3, r3, r2, lsr #align*8
++ mov r2, r2, lsl #32-align*8
++ orr r2, r2, r1, lsr #align*8
++ mov r1, r1, lsl #32-align*8
++ orr r1, r1, r0, lsr #align*8
++ stmdb D!, {r5, r6, r7, r8}
++ stmdb D!, {r1, r2, r3, r4}
++ .else
++ ldmib S!, {r1, r2, r3, r4}
++ mov r0, r8, lsr #align*8
++ ldmib S!, {r5, r6, r7, r8}
++ .if use_pld
++ pld [S, OFF]
++ .endif
++ orr r0, r0, r1, lsl #32-align*8
++ mov r1, r1, lsr #align*8
++ orr r1, r1, r2, lsl #32-align*8
++ mov r2, r2, lsr #align*8
++ orr r2, r2, r3, lsl #32-align*8
++ mov r3, r3, lsr #align*8
++ orr r3, r3, r4, lsl #32-align*8
++ mov r4, r4, lsr #align*8
++ orr r4, r4, r5, lsl #32-align*8
++ mov r5, r5, lsr #align*8
++ orr r5, r5, r6, lsl #32-align*8
++ mov r6, r6, lsr #align*8
++ orr r6, r6, r7, lsl #32-align*8
++ mov r7, r7, lsr #align*8
++ orr r7, r7, r8, lsl #32-align*8
++ stmia D!, {r0, r1, r2, r3}
++ stmia D!, {r4, r5, r6, r7}
++ .endif
++ .endif
++.endm
++
++.macro memcpy_leading_15bytes backwards, align
++ movs DAT1, DAT2, lsl #31
++ sub N, N, DAT2
++ .if backwards
++ ldrmib DAT0, [S, #-1]!
++ ldrcsh DAT1, [S, #-2]!
++ strmib DAT0, [D, #-1]!
++ strcsh DAT1, [D, #-2]!
++ .else
++ ldrmib DAT0, [S], #1
++ ldrcsh DAT1, [S], #2
++ strmib DAT0, [D], #1
++ strcsh DAT1, [D], #2
++ .endif
++ movs DAT1, DAT2, lsl #29
++ .if backwards
++ ldrmi DAT0, [S, #-4]!
++ .if align == 0
++ ldmcsdb S!, {DAT1, DAT2}
++ .else
++ ldrcs DAT2, [S, #-4]!
++ ldrcs DAT1, [S, #-4]!
++ .endif
++ strmi DAT0, [D, #-4]!
++ stmcsdb D!, {DAT1, DAT2}
++ .else
++ ldrmi DAT0, [S], #4
++ .if align == 0
++ ldmcsia S!, {DAT1, DAT2}
++ .else
++ ldrcs DAT1, [S], #4
++ ldrcs DAT2, [S], #4
++ .endif
++ strmi DAT0, [D], #4
++ stmcsia D!, {DAT1, DAT2}
++ .endif
++.endm
++
++.macro memcpy_trailing_15bytes backwards, align
++ movs N, N, lsl #29
++ .if backwards
++ .if align == 0
++ ldmcsdb S!, {DAT0, DAT1}
++ .else
++ ldrcs DAT1, [S, #-4]!
++ ldrcs DAT0, [S, #-4]!
++ .endif
++ ldrmi DAT2, [S, #-4]!
++ stmcsdb D!, {DAT0, DAT1}
++ strmi DAT2, [D, #-4]!
++ .else
++ .if align == 0
++ ldmcsia S!, {DAT0, DAT1}
++ .else
++ ldrcs DAT0, [S], #4
++ ldrcs DAT1, [S], #4
++ .endif
++ ldrmi DAT2, [S], #4
++ stmcsia D!, {DAT0, DAT1}
++ strmi DAT2, [D], #4
++ .endif
++ movs N, N, lsl #2
++ .if backwards
++ ldrcsh DAT0, [S, #-2]!
++ ldrmib DAT1, [S, #-1]
++ strcsh DAT0, [D, #-2]!
++ strmib DAT1, [D, #-1]
++ .else
++ ldrcsh DAT0, [S], #2
++ ldrmib DAT1, [S]
++ strcsh DAT0, [D], #2
++ strmib DAT1, [D]
++ .endif
++.endm
++
++.macro memcpy_long_inner_loop backwards, align
++ .if align != 0
++ .if backwards
++ ldr DAT0, [S, #-align]!
++ .else
++ ldr LAST, [S, #-align]!
++ .endif
++ .endif
++110:
++ .if align == 0
++ .if backwards
++ ldmdb S!, {DAT0, DAT1, DAT2, DAT3, DAT4, DAT5, DAT6, LAST}
++ pld [S, OFF]
++ stmdb D!, {DAT4, DAT5, DAT6, LAST}
++ stmdb D!, {DAT0, DAT1, DAT2, DAT3}
++ .else
++ ldmia S!, {DAT0, DAT1, DAT2, DAT3, DAT4, DAT5, DAT6, LAST}
++ pld [S, OFF]
++ stmia D!, {DAT0, DAT1, DAT2, DAT3}
++ stmia D!, {DAT4, DAT5, DAT6, LAST}
++ .endif
++ .else
++ unaligned_words backwards, align, 1, 8, DAT0, DAT1, DAT2, DAT3, DAT4, DAT5, DAT6, DAT7, LAST
++ .endif
++ subs N, N, #32
++ bhs 110b
++ /* Just before the final (prefetch_distance+1) 32-byte blocks, deal with final preloads */
++ preload_trailing backwards, S, N, OFF
++ add N, N, #(prefetch_distance+2)*32 - 32
++120:
++ .if align == 0
++ .if backwards
++ ldmdb S!, {DAT0, DAT1, DAT2, DAT3, DAT4, DAT5, DAT6, LAST}
++ stmdb D!, {DAT4, DAT5, DAT6, LAST}
++ stmdb D!, {DAT0, DAT1, DAT2, DAT3}
++ .else
++ ldmia S!, {DAT0, DAT1, DAT2, DAT3, DAT4, DAT5, DAT6, LAST}
++ stmia D!, {DAT0, DAT1, DAT2, DAT3}
++ stmia D!, {DAT4, DAT5, DAT6, LAST}
++ .endif
++ .else
++ unaligned_words backwards, align, 0, 8, DAT0, DAT1, DAT2, DAT3, DAT4, DAT5, DAT6, DAT7, LAST
++ .endif
++ subs N, N, #32
++ bhs 120b
++ tst N, #16
++ .if align == 0
++ .if backwards
++ ldmnedb S!, {DAT0, DAT1, DAT2, LAST}
++ stmnedb D!, {DAT0, DAT1, DAT2, LAST}
++ .else
++ ldmneia S!, {DAT0, DAT1, DAT2, LAST}
++ stmneia D!, {DAT0, DAT1, DAT2, LAST}
++ .endif
++ .else
++ beq 130f
++ unaligned_words backwards, align, 0, 4, DAT0, DAT1, DAT2, DAT3, LAST
++130:
++ .endif
++ /* Trailing words and bytes */
++ tst N, #15
++ beq 199f
++ .if align != 0
++ add S, S, #align
++ .endif
++ memcpy_trailing_15bytes backwards, align
++199:
++ pop {DAT3, DAT4, DAT5, DAT6, DAT7}
++ pop {D, DAT1, DAT2, pc}
++.endm
++
++.macro memcpy_medium_inner_loop backwards, align
++120:
++ .if backwards
++ .if align == 0
++ ldmdb S!, {DAT0, DAT1, DAT2, LAST}
++ .else
++ ldr LAST, [S, #-4]!
++ ldr DAT2, [S, #-4]!
++ ldr DAT1, [S, #-4]!
++ ldr DAT0, [S, #-4]!
++ .endif
++ stmdb D!, {DAT0, DAT1, DAT2, LAST}
++ .else
++ .if align == 0
++ ldmia S!, {DAT0, DAT1, DAT2, LAST}
++ .else
++ ldr DAT0, [S], #4
++ ldr DAT1, [S], #4
++ ldr DAT2, [S], #4
++ ldr LAST, [S], #4
++ .endif
++ stmia D!, {DAT0, DAT1, DAT2, LAST}
++ .endif
++ subs N, N, #16
++ bhs 120b
++ /* Trailing words and bytes */
++ tst N, #15
++ beq 199f
++ memcpy_trailing_15bytes backwards, align
++199:
++ pop {D, DAT1, DAT2, pc}
++.endm
++
++.macro memcpy_short_inner_loop backwards, align
++ tst N, #16
++ .if backwards
++ .if align == 0
++ ldmnedb S!, {DAT0, DAT1, DAT2, LAST}
++ .else
++ ldrne LAST, [S, #-4]!
++ ldrne DAT2, [S, #-4]!
++ ldrne DAT1, [S, #-4]!
++ ldrne DAT0, [S, #-4]!
++ .endif
++ stmnedb D!, {DAT0, DAT1, DAT2, LAST}
++ .else
++ .if align == 0
++ ldmneia S!, {DAT0, DAT1, DAT2, LAST}
++ .else
++ ldrne DAT0, [S], #4
++ ldrne DAT1, [S], #4
++ ldrne DAT2, [S], #4
++ ldrne LAST, [S], #4
++ .endif
++ stmneia D!, {DAT0, DAT1, DAT2, LAST}
++ .endif
++ memcpy_trailing_15bytes backwards, align
++199:
++ pop {D, DAT1, DAT2, pc}
++.endm
++
++.macro memcpy backwards
++ D .req a1
++ S .req a2
++ N .req a3
++ DAT0 .req a4
++ DAT1 .req v1
++ DAT2 .req v2
++ DAT3 .req v3
++ DAT4 .req v4
++ DAT5 .req v5
++ DAT6 .req v6
++ DAT7 .req sl
++ LAST .req ip
++ OFF .req lr
++
++ .cfi_startproc
++
++ push {D, DAT1, DAT2, lr}
++
++ .cfi_def_cfa_offset 16
++ .cfi_rel_offset D, 0
++ .cfi_undefined S
++ .cfi_undefined N
++ .cfi_undefined DAT0
++ .cfi_rel_offset DAT1, 4
++ .cfi_rel_offset DAT2, 8
++ .cfi_undefined LAST
++ .cfi_rel_offset lr, 12
++
++ .if backwards
++ add D, D, N
++ add S, S, N
++ .endif
++
++ /* See if we're guaranteed to have at least one 16-byte aligned 16-byte write */
++ cmp N, #31
++ blo 170f
++ /* To preload ahead as we go, we need at least (prefetch_distance+2) 32-byte blocks */
++ cmp N, #(prefetch_distance+3)*32 - 1
++ blo 160f
++
++ /* Long case */
++ push {DAT3, DAT4, DAT5, DAT6, DAT7}
++
++ .cfi_def_cfa_offset 36
++ .cfi_rel_offset D, 20
++ .cfi_rel_offset DAT1, 24
++ .cfi_rel_offset DAT2, 28
++ .cfi_rel_offset DAT3, 0
++ .cfi_rel_offset DAT4, 4
++ .cfi_rel_offset DAT5, 8
++ .cfi_rel_offset DAT6, 12
++ .cfi_rel_offset DAT7, 16
++ .cfi_rel_offset lr, 32
++
++ /* Adjust N so that the decrement instruction can also test for
++ * inner loop termination. We want it to stop when there are
++ * (prefetch_distance+1) complete blocks to go. */
++ sub N, N, #(prefetch_distance+2)*32
++ preload_leading_step1 backwards, DAT0, S
++ .if backwards
++ /* Bug in GAS: it accepts, but mis-assembles the instruction
++ * ands DAT2, D, #60, 2
++ * which sets DAT2 to the number of leading bytes until destination is aligned and also clears C (sets borrow)
++ */
++ .word 0xE210513C
++ beq 154f
++ .else
++ ands DAT2, D, #15
++ beq 154f
++ rsb DAT2, DAT2, #16 /* number of leading bytes until destination aligned */
++ .endif
++ preload_leading_step2 backwards, DAT0, S, DAT2, OFF
++ memcpy_leading_15bytes backwards, 1
++154: /* Destination now 16-byte aligned; we have at least one prefetch as well as at least one 16-byte output block */
++ /* Prefetch offset is best selected such that it lies in the first 8 of each 32 bytes - but it's just as easy to aim for the first one */
++ .if backwards
++ rsb OFF, S, #3
++ and OFF, OFF, #28
++ sub OFF, OFF, #32*(prefetch_distance+1)
++ .else
++ and OFF, S, #28
++ rsb OFF, OFF, #32*prefetch_distance
++ .endif
++ movs DAT0, S, lsl #31
++ bhi 157f
++ bcs 156f
++ bmi 155f
++ memcpy_long_inner_loop backwards, 0
++155: memcpy_long_inner_loop backwards, 1
++156: memcpy_long_inner_loop backwards, 2
++157: memcpy_long_inner_loop backwards, 3
++
++ .cfi_def_cfa_offset 16
++ .cfi_rel_offset D, 0
++ .cfi_rel_offset DAT1, 4
++ .cfi_rel_offset DAT2, 8
++ .cfi_same_value DAT3
++ .cfi_same_value DAT4
++ .cfi_same_value DAT5
++ .cfi_same_value DAT6
++ .cfi_same_value DAT7
++ .cfi_rel_offset lr, 12
++
++160: /* Medium case */
++ preload_all backwards, 0, 0, S, N, DAT2, OFF
++ sub N, N, #16 /* simplifies inner loop termination */
++ .if backwards
++ ands DAT2, D, #15
++ beq 164f
++ .else
++ ands DAT2, D, #15
++ beq 164f
++ rsb DAT2, DAT2, #16
++ .endif
++ memcpy_leading_15bytes backwards, align
++164: /* Destination now 16-byte aligned; we have at least one 16-byte output block */
++ tst S, #3
++ bne 140f
++ memcpy_medium_inner_loop backwards, 0
++140: memcpy_medium_inner_loop backwards, 1
++
++170: /* Short case, less than 31 bytes, so no guarantee of at least one 16-byte block */
++ teq N, #0
++ beq 199f
++ preload_all backwards, 1, 0, S, N, DAT2, LAST
++ tst D, #3
++ beq 174f
++172: subs N, N, #1
++ blo 199f
++ .if backwards
++ ldrb DAT0, [S, #-1]!
++ strb DAT0, [D, #-1]!
++ .else
++ ldrb DAT0, [S], #1
++ strb DAT0, [D], #1
++ .endif
++ tst D, #3
++ bne 172b
++174: /* Destination now 4-byte aligned; we have 0 or more output bytes to go */
++ tst S, #3
++ bne 140f
++ memcpy_short_inner_loop backwards, 0
++140: memcpy_short_inner_loop backwards, 1
++
++ .cfi_endproc
++
++ .unreq D
++ .unreq S
++ .unreq N
++ .unreq DAT0
++ .unreq DAT1
++ .unreq DAT2
++ .unreq DAT3
++ .unreq DAT4
++ .unreq DAT5
++ .unreq DAT6
++ .unreq DAT7
++ .unreq LAST
++ .unreq OFF
++.endm
+diff -Nur linux-4.1.3/arch/arm/lib/memcpy_rpi.S linux-xbian-rpi/arch/arm/lib/memcpy_rpi.S
+--- linux-4.1.3/arch/arm/lib/memcpy_rpi.S 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/lib/memcpy_rpi.S 2015-07-28 01:20:58.170137709 +0200
+@@ -0,0 +1,59 @@
++/*
++Copyright (c) 2013, Raspberry Pi Foundation
++Copyright (c) 2013, RISC OS Open Ltd
++All rights reserved.
++
++Redistribution and use in source and binary forms, with or without
++modification, are permitted provided that the following conditions are met:
++ * Redistributions of source code must retain the above copyright
++ notice, this list of conditions and the following disclaimer.
++ * Redistributions in binary form must reproduce the above copyright
++ notice, this list of conditions and the following disclaimer in the
++ documentation and/or other materials provided with the distribution.
++ * Neither the name of the copyright holder nor the
++ names of its contributors may be used to endorse or promote products
++ derived from this software without specific prior written permission.
++
++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY
++DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++*/
++
++#include <linux/linkage.h>
++#include "arm-mem.h"
++#include "memcpymove.h"
++
++/* Prevent the stack from becoming executable */
++#if defined(__linux__) && defined(__ELF__)
++.section .note.GNU-stack,"",%progbits
++#endif
++
++ .text
++ .arch armv6
++ .object_arch armv4
++ .arm
++ .altmacro
++ .p2align 2
++
++/*
++ * void *memcpy(void * restrict s1, const void * restrict s2, size_t n);
++ * On entry:
++ * a1 = pointer to destination
++ * a2 = pointer to source
++ * a3 = number of bytes to copy
++ * On exit:
++ * a1 preserved
++ */
++
++.set prefetch_distance, 3
++
++ENTRY(memcpy)
++ memcpy 0
++ENDPROC(memcpy)
+diff -Nur linux-4.1.3/arch/arm/lib/memmove_rpi.S linux-xbian-rpi/arch/arm/lib/memmove_rpi.S
+--- linux-4.1.3/arch/arm/lib/memmove_rpi.S 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/lib/memmove_rpi.S 2015-07-28 01:20:58.170137709 +0200
+@@ -0,0 +1,61 @@
++/*
++Copyright (c) 2013, Raspberry Pi Foundation
++Copyright (c) 2013, RISC OS Open Ltd
++All rights reserved.
++
++Redistribution and use in source and binary forms, with or without
++modification, are permitted provided that the following conditions are met:
++ * Redistributions of source code must retain the above copyright
++ notice, this list of conditions and the following disclaimer.
++ * Redistributions in binary form must reproduce the above copyright
++ notice, this list of conditions and the following disclaimer in the
++ documentation and/or other materials provided with the distribution.
++ * Neither the name of the copyright holder nor the
++ names of its contributors may be used to endorse or promote products
++ derived from this software without specific prior written permission.
++
++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY
++DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++*/
++
++#include <linux/linkage.h>
++#include "arm-mem.h"
++#include "memcpymove.h"
++
++/* Prevent the stack from becoming executable */
++#if defined(__linux__) && defined(__ELF__)
++.section .note.GNU-stack,"",%progbits
++#endif
++
++ .text
++ .arch armv6
++ .object_arch armv4
++ .arm
++ .altmacro
++ .p2align 2
++
++/*
++ * void *memmove(void *s1, const void *s2, size_t n);
++ * On entry:
++ * a1 = pointer to destination
++ * a2 = pointer to source
++ * a3 = number of bytes to copy
++ * On exit:
++ * a1 preserved
++ */
++
++.set prefetch_distance, 3
++
++ENTRY(memmove)
++ cmp a2, a1
++ bpl memcpy /* pl works even over -1 - 0 and 0x7fffffff - 0x80000000 boundaries */
++ memcpy 1
++ENDPROC(memmove)
+diff -Nur linux-4.1.3/arch/arm/lib/memset_rpi.S linux-xbian-rpi/arch/arm/lib/memset_rpi.S
+--- linux-4.1.3/arch/arm/lib/memset_rpi.S 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/lib/memset_rpi.S 2015-07-28 01:20:58.170137709 +0200
+@@ -0,0 +1,121 @@
++/*
++Copyright (c) 2013, Raspberry Pi Foundation
++Copyright (c) 2013, RISC OS Open Ltd
++All rights reserved.
++
++Redistribution and use in source and binary forms, with or without
++modification, are permitted provided that the following conditions are met:
++ * Redistributions of source code must retain the above copyright
++ notice, this list of conditions and the following disclaimer.
++ * Redistributions in binary form must reproduce the above copyright
++ notice, this list of conditions and the following disclaimer in the
++ documentation and/or other materials provided with the distribution.
++ * Neither the name of the copyright holder nor the
++ names of its contributors may be used to endorse or promote products
++ derived from this software without specific prior written permission.
++
++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY
++DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++*/
++
++#include <linux/linkage.h>
++#include "arm-mem.h"
++
++/* Prevent the stack from becoming executable */
++#if defined(__linux__) && defined(__ELF__)
++.section .note.GNU-stack,"",%progbits
++#endif
++
++ .text
++ .arch armv6
++ .object_arch armv4
++ .arm
++ .altmacro
++ .p2align 2
++
++/*
++ * void *memset(void *s, int c, size_t n);
++ * On entry:
++ * a1 = pointer to buffer to fill
++ * a2 = byte pattern to fill with (caller-narrowed)
++ * a3 = number of bytes to fill
++ * On exit:
++ * a1 preserved
++ */
++ENTRY(memset)
++ S .req a1
++ DAT0 .req a2
++ N .req a3
++ DAT1 .req a4
++ DAT2 .req ip
++ DAT3 .req lr
++
++ orr DAT0, DAT0, lsl #8
++ push {S, lr}
++ orr DAT0, DAT0, lsl #16
++ mov DAT1, DAT0
++
++ /* See if we're guaranteed to have at least one 16-byte aligned 16-byte write */
++ cmp N, #31
++ blo 170f
++
++161: sub N, N, #16 /* simplifies inner loop termination */
++ /* Leading words and bytes */
++ tst S, #15
++ beq 164f
++ rsb DAT3, S, #0 /* bits 0-3 = number of leading bytes until aligned */
++ movs DAT2, DAT3, lsl #31
++ submi N, N, #1
++ strmib DAT0, [S], #1
++ subcs N, N, #2
++ strcsh DAT0, [S], #2
++ movs DAT2, DAT3, lsl #29
++ submi N, N, #4
++ strmi DAT0, [S], #4
++ subcs N, N, #8
++ stmcsia S!, {DAT0, DAT1}
++164: /* Delayed set up of DAT2 and DAT3 so we could use them as scratch registers above */
++ mov DAT2, DAT0
++ mov DAT3, DAT0
++ /* Now the inner loop of 16-byte stores */
++165: stmia S!, {DAT0, DAT1, DAT2, DAT3}
++ subs N, N, #16
++ bhs 165b
++166: /* Trailing words and bytes */
++ movs N, N, lsl #29
++ stmcsia S!, {DAT0, DAT1}
++ strmi DAT0, [S], #4
++ movs N, N, lsl #2
++ strcsh DAT0, [S], #2
++ strmib DAT0, [S]
++199: pop {S, pc}
++
++170: /* Short case */
++ mov DAT2, DAT0
++ mov DAT3, DAT0
++ tst S, #3
++ beq 174f
++172: subs N, N, #1
++ blo 199b
++ strb DAT0, [S], #1
++ tst S, #3
++ bne 172b
++174: tst N, #16
++ stmneia S!, {DAT0, DAT1, DAT2, DAT3}
++ b 166b
++
++ .unreq S
++ .unreq DAT0
++ .unreq N
++ .unreq DAT1
++ .unreq DAT2
++ .unreq DAT3
++ENDPROC(memset)
+diff -Nur linux-4.1.3/arch/arm/lib/uaccess_with_memcpy.c linux-xbian-rpi/arch/arm/lib/uaccess_with_memcpy.c
+--- linux-4.1.3/arch/arm/lib/uaccess_with_memcpy.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/arch/arm/lib/uaccess_with_memcpy.c 2015-07-28 01:20:58.170137709 +0200
+@@ -22,6 +22,14 @@
+ #include <asm/current.h>
+ #include <asm/page.h>
+
++#ifndef COPY_FROM_USER_THRESHOLD
++#define COPY_FROM_USER_THRESHOLD 64
++#endif
++
++#ifndef COPY_TO_USER_THRESHOLD
++#define COPY_TO_USER_THRESHOLD 64
++#endif
++
+ static int
+ pin_page_for_write(const void __user *_addr, pte_t **ptep, spinlock_t **ptlp)
+ {
+@@ -85,7 +93,44 @@
+ return 1;
+ }
+
+-static unsigned long noinline
++static int
++pin_page_for_read(const void __user *_addr, pte_t **ptep, spinlock_t **ptlp)
++{
++ unsigned long addr = (unsigned long)_addr;
++ pgd_t *pgd;
++ pmd_t *pmd;
++ pte_t *pte;
++ pud_t *pud;
++ spinlock_t *ptl;
++
++ pgd = pgd_offset(current->mm, addr);
++ if (unlikely(pgd_none(*pgd) || pgd_bad(*pgd)))
++ {
++ return 0;
++ }
++ pud = pud_offset(pgd, addr);
++ if (unlikely(pud_none(*pud) || pud_bad(*pud)))
++ {
++ return 0;
++ }
++
++ pmd = pmd_offset(pud, addr);
++ if (unlikely(pmd_none(*pmd) || pmd_bad(*pmd)))
++ return 0;
++
++ pte = pte_offset_map_lock(current->mm, pmd, addr, &ptl);
++ if (unlikely(!pte_present(*pte) || !pte_young(*pte))) {
++ pte_unmap_unlock(pte, ptl);
++ return 0;
++ }
++
++ *ptep = pte;
++ *ptlp = ptl;
++
++ return 1;
++}
++
++unsigned long noinline
+ __copy_to_user_memcpy(void __user *to, const void *from, unsigned long n)
+ {
+ int atomic;
+@@ -135,6 +180,54 @@
+ return n;
+ }
+
++unsigned long noinline
++__copy_from_user_memcpy(void *to, const void __user *from, unsigned long n)
++{
++ int atomic;
++
++ if (unlikely(segment_eq(get_fs(), KERNEL_DS))) {
++ memcpy(to, (const void *)from, n);
++ return 0;
++ }
++
++ /* the mmap semaphore is taken only if not in an atomic context */
++ atomic = in_atomic();
++
++ if (!atomic)
++ down_read(&current->mm->mmap_sem);
++ while (n) {
++ pte_t *pte;
++ spinlock_t *ptl;
++ int tocopy;
++
++ while (!pin_page_for_read(from, &pte, &ptl)) {
++ char temp;
++ if (!atomic)
++ up_read(&current->mm->mmap_sem);
++ if (__get_user(temp, (char __user *)from))
++ goto out;
++ if (!atomic)
++ down_read(&current->mm->mmap_sem);
++ }
++
++ tocopy = (~(unsigned long)from & ~PAGE_MASK) + 1;
++ if (tocopy > n)
++ tocopy = n;
++
++ memcpy(to, (const void *)from, tocopy);
++ to += tocopy;
++ from += tocopy;
++ n -= tocopy;
++
++ pte_unmap_unlock(pte, ptl);
++ }
++ if (!atomic)
++ up_read(&current->mm->mmap_sem);
++
++out:
++ return n;
++}
++
+ unsigned long
+ __copy_to_user(void __user *to, const void *from, unsigned long n)
+ {
+@@ -145,10 +238,25 @@
+ * With frame pointer disabled, tail call optimization kicks in
+ * as well making this test almost invisible.
+ */
+- if (n < 64)
++ if (n < COPY_TO_USER_THRESHOLD)
+ return __copy_to_user_std(to, from, n);
+ return __copy_to_user_memcpy(to, from, n);
+ }
++
++unsigned long
++__copy_from_user(void *to, const void __user *from, unsigned long n)
++{
++ /*
++ * This test is stubbed out of the main function above to keep
++ * the overhead for small copies low by avoiding a large
++ * register dump on the stack just to reload them right away.
++ * With frame pointer disabled, tail call optimization kicks in
++ * as well making this test almost invisible.
++ */
++ if (n < COPY_FROM_USER_THRESHOLD)
++ return __copy_from_user_std(to, from, n);
++ return __copy_from_user_memcpy(to, from, n);
++}
+
+ static unsigned long noinline
+ __clear_user_memset(void __user *addr, unsigned long n)
+diff -Nur linux-4.1.3/arch/arm/mach-bcm/board_bcm2835.c linux-xbian-rpi/arch/arm/mach-bcm/board_bcm2835.c
+--- linux-4.1.3/arch/arm/mach-bcm/board_bcm2835.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/arch/arm/mach-bcm/board_bcm2835.c 2015-07-28 01:20:58.170137709 +0200
+@@ -18,6 +18,7 @@
+ #include <linux/of_address.h>
+ #include <linux/of_platform.h>
+ #include <linux/clk/bcm2835.h>
++#include <asm/system_info.h>
+
+ #include <asm/mach/arch.h>
+ #include <asm/mach/map.h>
+@@ -107,6 +108,9 @@
+
+ static void __init bcm2835_init(void)
+ {
++ struct device_node *np = of_find_node_by_path("/system");
++ u32 val;
++ u64 val64;
+ int ret;
+
+ bcm2835_setup_restart();
+@@ -121,6 +125,11 @@
+ pr_err("of_platform_populate failed: %d\n", ret);
+ BUG();
+ }
++
++ if (!of_property_read_u32(np, "linux,revision", &val))
++ system_rev = val;
++ if (!of_property_read_u64(np, "linux,serial", &val64))
++ system_serial_low = val64;
+ }
+
+ static const char * const bcm2835_compat[] = {
+diff -Nur linux-4.1.3/arch/arm/mach-bcm/Kconfig linux-xbian-rpi/arch/arm/mach-bcm/Kconfig
+--- linux-4.1.3/arch/arm/mach-bcm/Kconfig 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/arch/arm/mach-bcm/Kconfig 2015-07-28 01:20:58.170137709 +0200
+@@ -114,6 +114,7 @@
+ select ARM_ERRATA_411920
+ select ARM_TIMER_SP804
+ select CLKSRC_OF
++ select FIQ
+ select PINCTRL
+ select PINCTRL_BCM2835
+ help
+diff -Nur linux-4.1.3/arch/arm/mach-bcm2708/armctrl.c linux-xbian-rpi/arch/arm/mach-bcm2708/armctrl.c
+--- linux-4.1.3/arch/arm/mach-bcm2708/armctrl.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/mach-bcm2708/armctrl.c 2015-07-28 01:20:58.170137709 +0200
+@@ -0,0 +1,315 @@
++/*
++ * linux/arch/arm/mach-bcm2708/armctrl.c
++ *
++ * Copyright (C) 2010 Broadcom
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++#include <linux/init.h>
++#include <linux/list.h>
++#include <linux/io.h>
++#include <linux/version.h>
++#include <linux/syscore_ops.h>
++#include <linux/interrupt.h>
++#include <linux/irqdomain.h>
++#include <linux/of.h>
++
++#include <asm/mach/irq.h>
++#include <mach/hardware.h>
++#include "armctrl.h"
++
++/* For support of kernels >= 3.0 assume only one VIC for now*/
++static unsigned int remap_irqs[(INTERRUPT_ARASANSDIO + 1) - INTERRUPT_JPEG] = {
++ INTERRUPT_VC_JPEG,
++ INTERRUPT_VC_USB,
++ INTERRUPT_VC_3D,
++ INTERRUPT_VC_DMA2,
++ INTERRUPT_VC_DMA3,
++ INTERRUPT_VC_I2C,
++ INTERRUPT_VC_SPI,
++ INTERRUPT_VC_I2SPCM,
++ INTERRUPT_VC_SDIO,
++ INTERRUPT_VC_UART,
++ INTERRUPT_VC_ARASANSDIO
++};
++
++static void armctrl_mask_irq(struct irq_data *d)
++{
++ static const unsigned int disables[4] = {
++ ARM_IRQ_DIBL1,
++ ARM_IRQ_DIBL2,
++ ARM_IRQ_DIBL3,
++ 0
++ };
++
++ if (d->irq >= FIQ_START) {
++ writel(0, __io_address(ARM_IRQ_FAST));
++ } else {
++ unsigned int data = (unsigned int)irq_get_chip_data(d->irq);
++ writel(1 << (data & 0x1f), __io_address(disables[(data >> 5) & 0x3]));
++ }
++}
++
++static void armctrl_unmask_irq(struct irq_data *d)
++{
++ static const unsigned int enables[4] = {
++ ARM_IRQ_ENBL1,
++ ARM_IRQ_ENBL2,
++ ARM_IRQ_ENBL3,
++ 0
++ };
++
++ if (d->irq >= FIQ_START) {
++ unsigned int data =
++ (unsigned int)irq_get_chip_data(d->irq) - FIQ_START;
++ writel(0x80 | data, __io_address(ARM_IRQ_FAST));
++ } else {
++ unsigned int data = (unsigned int)irq_get_chip_data(d->irq);
++ writel(1 << (data & 0x1f), __io_address(enables[(data >> 5) & 0x3]));
++ }
++}
++
++#ifdef CONFIG_OF
++
++#define NR_IRQS_BANK0 21
++#define NR_BANKS 3
++#define IRQS_PER_BANK 32
++
++/* from drivers/irqchip/irq-bcm2835.c */
++static int armctrl_xlate(struct irq_domain *d, struct device_node *ctrlr,
++ const u32 *intspec, unsigned int intsize,
++ unsigned long *out_hwirq, unsigned int *out_type)
++{
++ if (WARN_ON(intsize != 2))
++ return -EINVAL;
++
++ if (WARN_ON(intspec[0] >= NR_BANKS))
++ return -EINVAL;
++
++ if (WARN_ON(intspec[1] >= IRQS_PER_BANK))
++ return -EINVAL;
++
++ if (WARN_ON(intspec[0] == 0 && intspec[1] >= NR_IRQS_BANK0))
++ return -EINVAL;
++
++ if (intspec[0] == 0)
++ *out_hwirq = ARM_IRQ0_BASE + intspec[1];
++ else if (intspec[0] == 1)
++ *out_hwirq = ARM_IRQ1_BASE + intspec[1];
++ else
++ *out_hwirq = ARM_IRQ2_BASE + intspec[1];
++
++ /* reverse remap_irqs[] */
++ switch (*out_hwirq) {
++ case INTERRUPT_VC_JPEG:
++ *out_hwirq = INTERRUPT_JPEG;
++ break;
++ case INTERRUPT_VC_USB:
++ *out_hwirq = INTERRUPT_USB;
++ break;
++ case INTERRUPT_VC_3D:
++ *out_hwirq = INTERRUPT_3D;
++ break;
++ case INTERRUPT_VC_DMA2:
++ *out_hwirq = INTERRUPT_DMA2;
++ break;
++ case INTERRUPT_VC_DMA3:
++ *out_hwirq = INTERRUPT_DMA3;
++ break;
++ case INTERRUPT_VC_I2C:
++ *out_hwirq = INTERRUPT_I2C;
++ break;
++ case INTERRUPT_VC_SPI:
++ *out_hwirq = INTERRUPT_SPI;
++ break;
++ case INTERRUPT_VC_I2SPCM:
++ *out_hwirq = INTERRUPT_I2SPCM;
++ break;
++ case INTERRUPT_VC_SDIO:
++ *out_hwirq = INTERRUPT_SDIO;
++ break;
++ case INTERRUPT_VC_UART:
++ *out_hwirq = INTERRUPT_UART;
++ break;
++ case INTERRUPT_VC_ARASANSDIO:
++ *out_hwirq = INTERRUPT_ARASANSDIO;
++ break;
++ }
++
++ *out_type = IRQ_TYPE_NONE;
++ return 0;
++}
++
++static struct irq_domain_ops armctrl_ops = {
++ .xlate = armctrl_xlate
++};
++
++void __init armctrl_dt_init(void)
++{
++ struct device_node *np;
++ struct irq_domain *domain;
++
++ np = of_find_compatible_node(NULL, NULL, "brcm,bcm2708-armctrl-ic");
++ if (!np)
++ return;
++
++ domain = irq_domain_add_legacy(np, BCM2708_ALLOC_IRQS,
++ IRQ_ARMCTRL_START, 0,
++ &armctrl_ops, NULL);
++ WARN_ON(!domain);
++}
++#else
++void __init armctrl_dt_init(void) { }
++#endif /* CONFIG_OF */
++
++#if defined(CONFIG_PM)
++
++/* for kernels 3.xx use the new syscore_ops apis but for older kernels use the sys dev class */
++
++/* Static defines
++ * struct armctrl_device - VIC PM device (< 3.xx)
++ * @sysdev: The system device which is registered. (< 3.xx)
++ * @irq: The IRQ number for the base of the VIC.
++ * @base: The register base for the VIC.
++ * @resume_sources: A bitmask of interrupts for resume.
++ * @resume_irqs: The IRQs enabled for resume.
++ * @int_select: Save for VIC_INT_SELECT.
++ * @int_enable: Save for VIC_INT_ENABLE.
++ * @soft_int: Save for VIC_INT_SOFT.
++ * @protect: Save for VIC_PROTECT.
++ */
++struct armctrl_info {
++ void __iomem *base;
++ int irq;
++ u32 resume_sources;
++ u32 resume_irqs;
++ u32 int_select;
++ u32 int_enable;
++ u32 soft_int;
++ u32 protect;
++} armctrl;
++
++static int armctrl_suspend(void)
++{
++ return 0;
++}
++
++static void armctrl_resume(void)
++{
++ return;
++}
++
++/**
++ * armctrl_pm_register - Register a VIC for later power management control
++ * @base: The base address of the VIC.
++ * @irq: The base IRQ for the VIC.
++ * @resume_sources: bitmask of interrupts allowed for resume sources.
++ *
++ * For older kernels (< 3.xx) do -
++ * Register the VIC with the system device tree so that it can be notified
++ * of suspend and resume requests and ensure that the correct actions are
++ * taken to re-instate the settings on resume.
++ */
++static void __init armctrl_pm_register(void __iomem * base, unsigned int irq,
++ u32 resume_sources)
++{
++ armctrl.base = base;
++ armctrl.resume_sources = resume_sources;
++ armctrl.irq = irq;
++}
++
++static int armctrl_set_wake(struct irq_data *d, unsigned int on)
++{
++ unsigned int off = d->irq & 31;
++ u32 bit = 1 << off;
++
++ if (!(bit & armctrl.resume_sources))
++ return -EINVAL;
++
++ if (on)
++ armctrl.resume_irqs |= bit;
++ else
++ armctrl.resume_irqs &= ~bit;
++
++ return 0;
++}
++
++#else
++static inline void armctrl_pm_register(void __iomem * base, unsigned int irq,
++ u32 arg1)
++{
++}
++
++#define armctrl_suspend NULL
++#define armctrl_resume NULL
++#define armctrl_set_wake NULL
++#endif /* CONFIG_PM */
++
++static struct syscore_ops armctrl_syscore_ops = {
++ .suspend = armctrl_suspend,
++ .resume = armctrl_resume,
++};
++
++/**
++ * armctrl_syscore_init - initicall to register VIC pm functions
++ *
++ * This is called via late_initcall() to register
++ * the resources for the VICs due to the early
++ * nature of the VIC's registration.
++*/
++static int __init armctrl_syscore_init(void)
++{
++ register_syscore_ops(&armctrl_syscore_ops);
++ return 0;
++}
++
++late_initcall(armctrl_syscore_init);
++
++static struct irq_chip armctrl_chip = {
++ .name = "ARMCTRL",
++ .irq_ack = NULL,
++ .irq_mask = armctrl_mask_irq,
++ .irq_unmask = armctrl_unmask_irq,
++ .irq_set_wake = armctrl_set_wake,
++};
++
++/**
++ * armctrl_init - initialise a vectored interrupt controller
++ * @base: iomem base address
++ * @irq_start: starting interrupt number, must be muliple of 32
++ * @armctrl_sources: bitmask of interrupt sources to allow
++ * @resume_sources: bitmask of interrupt sources to allow for resume
++ */
++int __init armctrl_init(void __iomem * base, unsigned int irq_start,
++ u32 armctrl_sources, u32 resume_sources)
++{
++ unsigned int irq;
++
++ for (irq = 0; irq < BCM2708_ALLOC_IRQS; irq++) {
++ unsigned int data = irq;
++ if (irq >= INTERRUPT_JPEG && irq <= INTERRUPT_ARASANSDIO)
++ data = remap_irqs[irq - INTERRUPT_JPEG];
++
++ irq_set_chip(irq, &armctrl_chip);
++ irq_set_chip_data(irq, (void *)data);
++ irq_set_handler(irq, handle_level_irq);
++ set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
++ }
++
++ armctrl_pm_register(base, irq_start, resume_sources);
++ init_FIQ(FIQ_START);
++ armctrl_dt_init();
++ return 0;
++}
+diff -Nur linux-4.1.3/arch/arm/mach-bcm2708/armctrl.h linux-xbian-rpi/arch/arm/mach-bcm2708/armctrl.h
+--- linux-4.1.3/arch/arm/mach-bcm2708/armctrl.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/mach-bcm2708/armctrl.h 2015-07-28 01:20:58.170137709 +0200
+@@ -0,0 +1,27 @@
++/*
++ * linux/arch/arm/mach-bcm2708/armctrl.h
++ *
++ * Copyright (C) 2010 Broadcom
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++
++#ifndef __BCM2708_ARMCTRL_H
++#define __BCM2708_ARMCTRL_H
++
++extern int __init armctrl_init(void __iomem * base, unsigned int irq_start,
++ u32 armctrl_sources, u32 resume_sources);
++
++#endif
+diff -Nur linux-4.1.3/arch/arm/mach-bcm2708/bcm2708.c linux-xbian-rpi/arch/arm/mach-bcm2708/bcm2708.c
+--- linux-4.1.3/arch/arm/mach-bcm2708/bcm2708.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/mach-bcm2708/bcm2708.c 2015-07-28 01:20:58.170137709 +0200
+@@ -0,0 +1,1162 @@
++/*
++ * linux/arch/arm/mach-bcm2708/bcm2708.c
++ *
++ * Copyright (C) 2010 Broadcom
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++
++#include <linux/init.h>
++#include <linux/device.h>
++#include <linux/dma-mapping.h>
++#include <linux/serial_8250.h>
++#include <linux/platform_device.h>
++#include <linux/syscore_ops.h>
++#include <linux/interrupt.h>
++#include <linux/amba/bus.h>
++#include <linux/amba/clcd.h>
++#include <linux/clk-provider.h>
++#include <linux/clkdev.h>
++#include <linux/clockchips.h>
++#include <linux/cnt32_to_63.h>
++#include <linux/io.h>
++#include <linux/module.h>
++#include <linux/of_platform.h>
++#include <linux/spi/spi.h>
++#include <linux/gpio/machine.h>
++#include <linux/w1-gpio.h>
++#include <linux/pps-gpio.h>
++
++#include <linux/version.h>
++#include <linux/clkdev.h>
++#include <asm/system_info.h>
++#include <mach/hardware.h>
++#include <asm/irq.h>
++#include <linux/leds.h>
++#include <asm/mach-types.h>
++#include <linux/sched_clock.h>
++
++#include <asm/mach/arch.h>
++#include <asm/mach/flash.h>
++#include <asm/mach/irq.h>
++#include <asm/mach/time.h>
++#include <asm/mach/map.h>
++
++#include <mach/timex.h>
++#include <mach/system.h>
++
++#include <linux/delay.h>
++
++#include "bcm2708.h"
++#include "armctrl.h"
++
++#ifdef CONFIG_BCM_VC_CMA
++#include <linux/broadcom/vc_cma.h>
++#endif
++
++
++/* Effectively we have an IOMMU (ARM<->VideoCore map) that is set up to
++ * give us IO access only to 64Mbytes of physical memory (26 bits). We could
++ * represent this window by setting our dmamasks to 26 bits but, in fact
++ * we're not going to use addresses outside this range (they're not in real
++ * memory) so we don't bother.
++ *
++ * In the future we might include code to use this IOMMU to remap other
++ * physical addresses onto VideoCore memory then the use of 32-bits would be
++ * more legitimate.
++ */
++#define DMA_MASK_BITS_COMMON 32
++
++// use GPIO 4 for the one-wire GPIO pin, if enabled
++#define W1_GPIO 4
++// ensure one-wire GPIO pullup is disabled by default
++#define W1_PULLUP -1
++
++/* command line parameters */
++static unsigned boardrev, serial;
++static unsigned uart_clock = UART0_CLOCK;
++static unsigned disk_led_gpio = 16;
++static unsigned disk_led_active_low = 1;
++static unsigned reboot_part = 0;
++static unsigned w1_gpio_pin = W1_GPIO;
++static unsigned w1_gpio_pullup = W1_PULLUP;
++static bool vc_i2c_override = false;
++static int pps_gpio_pin = -1;
++
++static unsigned use_dt = 0;
++
++static void __init bcm2708_init_led(void);
++
++void __init bcm2708_init_irq(void)
++{
++ armctrl_init(__io_address(ARMCTRL_IC_BASE), 0, 0, 0);
++}
++
++static struct map_desc bcm2708_io_desc[] __initdata = {
++ {
++ .virtual = IO_ADDRESS(ARMCTRL_BASE),
++ .pfn = __phys_to_pfn(ARMCTRL_BASE),
++ .length = SZ_4K,
++ .type = MT_DEVICE},
++ {
++ .virtual = IO_ADDRESS(UART0_BASE),
++ .pfn = __phys_to_pfn(UART0_BASE),
++ .length = SZ_4K,
++ .type = MT_DEVICE},
++ {
++ .virtual = IO_ADDRESS(UART1_BASE),
++ .pfn = __phys_to_pfn(UART1_BASE),
++ .length = SZ_4K,
++ .type = MT_DEVICE},
++ {
++ .virtual = IO_ADDRESS(DMA_BASE),
++ .pfn = __phys_to_pfn(DMA_BASE),
++ .length = SZ_4K,
++ .type = MT_DEVICE},
++ {
++ .virtual = IO_ADDRESS(MCORE_BASE),
++ .pfn = __phys_to_pfn(MCORE_BASE),
++ .length = SZ_4K,
++ .type = MT_DEVICE},
++ {
++ .virtual = IO_ADDRESS(ST_BASE),
++ .pfn = __phys_to_pfn(ST_BASE),
++ .length = SZ_4K,
++ .type = MT_DEVICE},
++ {
++ .virtual = IO_ADDRESS(USB_BASE),
++ .pfn = __phys_to_pfn(USB_BASE),
++ .length = SZ_128K,
++ .type = MT_DEVICE},
++ {
++ .virtual = IO_ADDRESS(PM_BASE),
++ .pfn = __phys_to_pfn(PM_BASE),
++ .length = SZ_4K,
++ .type = MT_DEVICE},
++ {
++ .virtual = IO_ADDRESS(GPIO_BASE),
++ .pfn = __phys_to_pfn(GPIO_BASE),
++ .length = SZ_4K,
++ .type = MT_DEVICE}
++};
++
++void __init bcm2708_map_io(void)
++{
++ iotable_init(bcm2708_io_desc, ARRAY_SIZE(bcm2708_io_desc));
++}
++
++/* The STC is a free running counter that increments at the rate of 1MHz */
++#define STC_FREQ_HZ 1000000
++
++static inline uint32_t timer_read(void)
++{
++ /* STC: a free running counter that increments at the rate of 1MHz */
++ return readl(__io_address(ST_BASE + 0x04));
++}
++
++static unsigned long bcm2708_read_current_timer(void)
++{
++ return timer_read();
++}
++
++static u64 notrace bcm2708_read_sched_clock(void)
++{
++ return timer_read();
++}
++
++static cycle_t clksrc_read(struct clocksource *cs)
++{
++ return timer_read();
++}
++
++static struct clocksource clocksource_stc = {
++ .name = "stc",
++ .rating = 300,
++ .read = clksrc_read,
++ .mask = CLOCKSOURCE_MASK(32),
++ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
++};
++
++unsigned long frc_clock_ticks32(void)
++{
++ return timer_read();
++}
++
++static void __init bcm2708_clocksource_init(void)
++{
++ if (clocksource_register_hz(&clocksource_stc, STC_FREQ_HZ)) {
++ printk(KERN_ERR "timer: failed to initialize clock "
++ "source %s\n", clocksource_stc.name);
++ }
++}
++
++struct clk __init *bcm2708_clk_register(const char *name, unsigned long fixed_rate)
++{
++ struct clk *clk;
++
++ clk = clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT,
++ fixed_rate);
++ if (IS_ERR(clk))
++ pr_err("%s not registered\n", name);
++
++ return clk;
++}
++
++void __init bcm2708_register_clkdev(struct clk *clk, const char *name)
++{
++ int ret;
++
++ ret = clk_register_clkdev(clk, NULL, name);
++ if (ret)
++ pr_err("%s alias not registered\n", name);
++}
++
++void __init bcm2708_init_clocks(void)
++{
++ struct clk *clk;
++
++ clk = bcm2708_clk_register("uart0_clk", uart_clock);
++ bcm2708_register_clkdev(clk, "dev:f1");
++
++ clk = bcm2708_clk_register("sdhost_clk", 250000000);
++ bcm2708_register_clkdev(clk, "mmc-bcm2835.0");
++ bcm2708_register_clkdev(clk, "bcm2708_spi.0");
++ bcm2708_register_clkdev(clk, "bcm2708_i2c.0");
++ bcm2708_register_clkdev(clk, "bcm2708_i2c.1");
++}
++
++#define UART0_IRQ { IRQ_UART, 0 /*NO_IRQ*/ }
++#define UART0_DMA { 15, 14 }
++
++AMBA_DEVICE(uart0, "dev:f1", UART0, NULL);
++
++static struct amba_device *amba_devs[] __initdata = {
++ &uart0_device,
++};
++
++static struct resource bcm2708_dmaengine_resources[] = {
++ {
++ .start = DMA_BASE,
++ .end = DMA_BASE + SZ_4K - 1,
++ .flags = IORESOURCE_MEM,
++ }, {
++ .start = IRQ_DMA0,
++ .end = IRQ_DMA0,
++ .flags = IORESOURCE_IRQ,
++ }, {
++ .start = IRQ_DMA1,
++ .end = IRQ_DMA1,
++ .flags = IORESOURCE_IRQ,
++ }, {
++ .start = IRQ_DMA2,
++ .end = IRQ_DMA2,
++ .flags = IORESOURCE_IRQ,
++ }, {
++ .start = IRQ_DMA3,
++ .end = IRQ_DMA3,
++ .flags = IORESOURCE_IRQ,
++ }, {
++ .start = IRQ_DMA4,
++ .end = IRQ_DMA4,
++ .flags = IORESOURCE_IRQ,
++ }, {
++ .start = IRQ_DMA5,
++ .end = IRQ_DMA5,
++ .flags = IORESOURCE_IRQ,
++ }, {
++ .start = IRQ_DMA6,
++ .end = IRQ_DMA6,
++ .flags = IORESOURCE_IRQ,
++ }, {
++ .start = IRQ_DMA7,
++ .end = IRQ_DMA7,
++ .flags = IORESOURCE_IRQ,
++ }, {
++ .start = IRQ_DMA8,
++ .end = IRQ_DMA8,
++ .flags = IORESOURCE_IRQ,
++ }, {
++ .start = IRQ_DMA9,
++ .end = IRQ_DMA9,
++ .flags = IORESOURCE_IRQ,
++ }, {
++ .start = IRQ_DMA10,
++ .end = IRQ_DMA10,
++ .flags = IORESOURCE_IRQ,
++ }, {
++ .start = IRQ_DMA11,
++ .end = IRQ_DMA11,
++ .flags = IORESOURCE_IRQ,
++ }, {
++ .start = IRQ_DMA12,
++ .end = IRQ_DMA12,
++ .flags = IORESOURCE_IRQ,
++ }
++};
++
++static struct platform_device bcm2708_dmaengine_device = {
++ .name = "bcm2708-dmaengine",
++ .id = -1,
++ .resource = bcm2708_dmaengine_resources,
++ .num_resources = ARRAY_SIZE(bcm2708_dmaengine_resources),
++};
++
++#if defined(CONFIG_W1_MASTER_GPIO) || defined(CONFIG_W1_MASTER_GPIO_MODULE)
++static struct w1_gpio_platform_data w1_gpio_pdata = {
++ .pin = W1_GPIO,
++ .ext_pullup_enable_pin = W1_PULLUP,
++ .is_open_drain = 0,
++};
++
++static struct platform_device w1_device = {
++ .name = "w1-gpio",
++ .id = -1,
++ .dev.platform_data = &w1_gpio_pdata,
++};
++#endif
++
++static struct pps_gpio_platform_data pps_gpio_info = {
++ .assert_falling_edge = false,
++ .capture_clear = false,
++ .gpio_pin = -1,
++ .gpio_label = "PPS",
++};
++
++static struct platform_device pps_gpio_device = {
++ .name = "pps-gpio",
++ .id = PLATFORM_DEVID_NONE,
++ .dev.platform_data = &pps_gpio_info,
++};
++
++static u64 fb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
++
++static struct platform_device bcm2708_fb_device = {
++ .name = "bcm2708_fb",
++ .id = -1, /* only one bcm2708_fb */
++ .resource = NULL,
++ .num_resources = 0,
++ .dev = {
++ .dma_mask = &fb_dmamask,
++ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
++ },
++};
++
++static struct resource bcm2708_usb_resources[] = {
++ [0] = {
++ .start = USB_BASE,
++ .end = USB_BASE + SZ_128K - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = MPHI_BASE,
++ .end = MPHI_BASE + SZ_4K - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [2] = {
++ .start = IRQ_HOSTPORT,
++ .end = IRQ_HOSTPORT,
++ .flags = IORESOURCE_IRQ,
++ },
++ [3] = {
++ .start = IRQ_USB,
++ .end = IRQ_USB,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++
++static u64 usb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
++
++static struct platform_device bcm2708_usb_device = {
++ .name = "bcm2708_usb",
++ .id = -1, /* only one bcm2708_usb */
++ .resource = bcm2708_usb_resources,
++ .num_resources = ARRAY_SIZE(bcm2708_usb_resources),
++ .dev = {
++ .dma_mask = &usb_dmamask,
++ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
++ },
++};
++
++static struct resource bcm2708_vcio_resources[] = {
++ {
++ .start = ARMCTRL_0_MAIL0_BASE,
++ .end = ARMCTRL_0_MAIL0_BASE + SZ_64 - 1,
++ .flags = IORESOURCE_MEM,
++ }, {
++ .start = IRQ_ARM_MAILBOX,
++ .end = IRQ_ARM_MAILBOX,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++static u64 vcio_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
++
++static struct platform_device bcm2708_vcio_device = {
++ .name = "bcm2835-mbox",
++ .id = -1, /* only one VideoCore I/O area */
++ .resource = bcm2708_vcio_resources,
++ .num_resources = ARRAY_SIZE(bcm2708_vcio_resources),
++ .dev = {
++ .dma_mask = &vcio_dmamask,
++ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
++ },
++};
++
++static u64 rpifw_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
++
++static struct platform_device bcm2708_rpifw_device = {
++ .name = "raspberrypi-firmware",
++ .dev = {
++ .dma_mask = &rpifw_dmamask,
++ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
++ },
++};
++
++static struct resource bcm2708_vchiq_resources[] = {
++ {
++ .start = ARMCTRL_0_BELL_BASE,
++ .end = ARMCTRL_0_BELL_BASE + 16,
++ .flags = IORESOURCE_MEM,
++ }, {
++ .start = IRQ_ARM_DOORBELL_0,
++ .end = IRQ_ARM_DOORBELL_0,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++static u64 vchiq_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
++
++static struct platform_device bcm2708_vchiq_device = {
++ .name = "bcm2835_vchiq",
++ .id = -1,
++ .resource = bcm2708_vchiq_resources,
++ .num_resources = ARRAY_SIZE(bcm2708_vchiq_resources),
++ .dev = {
++ .dma_mask = &vchiq_dmamask,
++ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
++ },
++};
++
++#ifdef CONFIG_BCM2708_GPIO
++#define BCM_GPIO_DRIVER_NAME "bcm2708_gpio"
++
++static struct resource bcm2708_gpio_resources[] = {
++ [0] = { /* general purpose I/O */
++ .start = GPIO_BASE,
++ .end = GPIO_BASE + SZ_4K - 1,
++ .flags = IORESOURCE_MEM,
++ },
++};
++
++static u64 gpio_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
++
++static struct platform_device bcm2708_gpio_device = {
++ .name = BCM_GPIO_DRIVER_NAME,
++ .id = -1, /* only one VideoCore I/O area */
++ .resource = bcm2708_gpio_resources,
++ .num_resources = ARRAY_SIZE(bcm2708_gpio_resources),
++ .dev = {
++ .dma_mask = &gpio_dmamask,
++ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
++ },
++};
++#endif
++
++#ifdef CONFIG_MMC_BCM2835 /* Arasan emmc SD (new) */
++static struct resource bcm2835_emmc_resources[] = {
++ [0] = {
++ .start = EMMC_BASE,
++ .end = EMMC_BASE + SZ_256 - 1, /* we only need this area */
++ /* the memory map actually makes SZ_4K available */
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = IRQ_ARASANSDIO,
++ .end = IRQ_ARASANSDIO,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++static u64 bcm2835_emmc_dmamask = 0xffffffffUL;
++
++struct platform_device bcm2835_emmc_device = {
++ .name = "mmc-bcm2835",
++ .id = 0,
++ .num_resources = ARRAY_SIZE(bcm2835_emmc_resources),
++ .resource = bcm2835_emmc_resources,
++ .dev = {
++ .dma_mask = &bcm2835_emmc_dmamask,
++ .coherent_dma_mask = 0xffffffffUL},
++};
++#endif /* CONFIG_MMC_BCM2835 */
++
++static struct platform_device bcm2708_alsa_devices[] = {
++ [0] = {
++ .name = "bcm2835_AUD0",
++ .id = 0, /* first audio device */
++ .resource = 0,
++ .num_resources = 0,
++ },
++ [1] = {
++ .name = "bcm2835_AUD1",
++ .id = 1, /* second audio device */
++ .resource = 0,
++ .num_resources = 0,
++ },
++ [2] = {
++ .name = "bcm2835_AUD2",
++ .id = 2, /* third audio device */
++ .resource = 0,
++ .num_resources = 0,
++ },
++ [3] = {
++ .name = "bcm2835_AUD3",
++ .id = 3, /* forth audio device */
++ .resource = 0,
++ .num_resources = 0,
++ },
++ [4] = {
++ .name = "bcm2835_AUD4",
++ .id = 4, /* fifth audio device */
++ .resource = 0,
++ .num_resources = 0,
++ },
++ [5] = {
++ .name = "bcm2835_AUD5",
++ .id = 5, /* sixth audio device */
++ .resource = 0,
++ .num_resources = 0,
++ },
++ [6] = {
++ .name = "bcm2835_AUD6",
++ .id = 6, /* seventh audio device */
++ .resource = 0,
++ .num_resources = 0,
++ },
++ [7] = {
++ .name = "bcm2835_AUD7",
++ .id = 7, /* eighth audio device */
++ .resource = 0,
++ .num_resources = 0,
++ },
++};
++
++static struct resource bcm2708_spi_resources[] = {
++ {
++ .start = SPI0_BASE,
++ .end = SPI0_BASE + SZ_256 - 1,
++ .flags = IORESOURCE_MEM,
++ }, {
++ .start = IRQ_SPI,
++ .end = IRQ_SPI,
++ .flags = IORESOURCE_IRQ,
++ }
++};
++
++
++static u64 bcm2708_spi_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
++static struct platform_device bcm2708_spi_device = {
++ .name = "bcm2708_spi",
++ .id = 0,
++ .num_resources = ARRAY_SIZE(bcm2708_spi_resources),
++ .resource = bcm2708_spi_resources,
++ .dev = {
++ .dma_mask = &bcm2708_spi_dmamask,
++ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON)},
++};
++
++#ifdef CONFIG_BCM2708_SPIDEV
++static struct spi_board_info bcm2708_spi_devices[] = {
++#ifdef CONFIG_SPI_SPIDEV
++ {
++ .modalias = "spidev",
++ .max_speed_hz = 500000,
++ .bus_num = 0,
++ .chip_select = 0,
++ .mode = SPI_MODE_0,
++ }, {
++ .modalias = "spidev",
++ .max_speed_hz = 500000,
++ .bus_num = 0,
++ .chip_select = 1,
++ .mode = SPI_MODE_0,
++ }
++#endif
++};
++#endif
++
++static struct resource bcm2708_bsc0_resources[] = {
++ {
++ .start = BSC0_BASE,
++ .end = BSC0_BASE + SZ_256 - 1,
++ .flags = IORESOURCE_MEM,
++ }, {
++ .start = INTERRUPT_I2C,
++ .end = INTERRUPT_I2C,
++ .flags = IORESOURCE_IRQ,
++ }
++};
++
++static struct platform_device bcm2708_bsc0_device = {
++ .name = "bcm2708_i2c",
++ .id = 0,
++ .num_resources = ARRAY_SIZE(bcm2708_bsc0_resources),
++ .resource = bcm2708_bsc0_resources,
++};
++
++
++static struct resource bcm2708_bsc1_resources[] = {
++ {
++ .start = BSC1_BASE,
++ .end = BSC1_BASE + SZ_256 - 1,
++ .flags = IORESOURCE_MEM,
++ }, {
++ .start = INTERRUPT_I2C,
++ .end = INTERRUPT_I2C,
++ .flags = IORESOURCE_IRQ,
++ }
++};
++
++static struct platform_device bcm2708_bsc1_device = {
++ .name = "bcm2708_i2c",
++ .id = 1,
++ .num_resources = ARRAY_SIZE(bcm2708_bsc1_resources),
++ .resource = bcm2708_bsc1_resources,
++};
++
++static struct platform_device bcm2835_thermal_device = {
++ .name = "bcm2835_thermal",
++};
++
++#if defined(CONFIG_SND_BCM2708_SOC_I2S) || defined(CONFIG_SND_BCM2708_SOC_I2S_MODULE)
++static struct resource bcm2708_i2s_resources[] = {
++ {
++ .start = I2S_BASE,
++ .end = I2S_BASE + 0x20,
++ .flags = IORESOURCE_MEM,
++ },
++ {
++ .start = PCM_CLOCK_BASE,
++ .end = PCM_CLOCK_BASE + 0x02,
++ .flags = IORESOURCE_MEM,
++ }
++};
++
++static struct platform_device bcm2708_i2s_device = {
++ .name = "bcm2708-i2s",
++ .id = 0,
++ .num_resources = ARRAY_SIZE(bcm2708_i2s_resources),
++ .resource = bcm2708_i2s_resources,
++};
++#endif
++
++#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC_MODULE)
++static struct platform_device snd_hifiberry_dac_device = {
++ .name = "snd-hifiberry-dac",
++ .id = 0,
++ .num_resources = 0,
++};
++
++static struct platform_device snd_pcm5102a_codec_device = {
++ .name = "pcm5102a-codec",
++ .id = -1,
++ .num_resources = 0,
++};
++#endif
++
++#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS_MODULE)
++static struct platform_device snd_rpi_hifiberry_dacplus_device = {
++ .name = "snd-rpi-hifiberry-dacplus",
++ .id = 0,
++ .num_resources = 0,
++};
++
++static struct i2c_board_info __initdata snd_pcm512x_hbdacplus_i2c_devices[] = {
++ {
++ I2C_BOARD_INFO("pcm5122", 0x4d)
++ },
++};
++#endif
++
++#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI_MODULE)
++static struct platform_device snd_hifiberry_digi_device = {
++ .name = "snd-hifiberry-digi",
++ .id = 0,
++ .num_resources = 0,
++};
++
++static struct i2c_board_info __initdata snd_wm8804_i2c_devices[] = {
++ {
++ I2C_BOARD_INFO("wm8804", 0x3b)
++ },
++};
++
++#endif
++
++#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP_MODULE)
++static struct platform_device snd_hifiberry_amp_device = {
++ .name = "snd-hifiberry-amp",
++ .id = 0,
++ .num_resources = 0,
++};
++
++static struct i2c_board_info __initdata snd_tas5713_i2c_devices[] = {
++ {
++ I2C_BOARD_INFO("tas5713", 0x1b)
++ },
++};
++#endif
++
++#if defined(CONFIG_SND_BCM2708_SOC_RPI_DAC) || defined(CONFIG_SND_BCM2708_SOC_RPI_DAC_MODULE)
++static struct platform_device snd_rpi_dac_device = {
++ .name = "snd-rpi-dac",
++ .id = 0,
++ .num_resources = 0,
++};
++
++static struct platform_device snd_pcm1794a_codec_device = {
++ .name = "pcm1794a-codec",
++ .id = -1,
++ .num_resources = 0,
++};
++#endif
++
++
++#if defined(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC) || defined(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC_MODULE)
++static struct platform_device snd_rpi_iqaudio_dac_device = {
++ .name = "snd-rpi-iqaudio-dac",
++ .id = 0,
++ .num_resources = 0,
++};
++
++// Use the actual device name rather than generic driver name
++static struct i2c_board_info __initdata snd_pcm512x_i2c_devices[] = {
++ {
++ I2C_BOARD_INFO("pcm5122", 0x4c)
++ },
++};
++#endif
++
++int __init bcm_register_device(struct platform_device *pdev)
++{
++ int ret;
++
++ ret = platform_device_register(pdev);
++ if (ret)
++ pr_debug("Unable to register platform device '%s': %d\n",
++ pdev->name, ret);
++
++ return ret;
++}
++
++/*
++ * Use these macros for platform and i2c devices that are present in the
++ * Device Tree. This way the devices are only added on non-DT systems.
++ */
++#define bcm_register_device_dt(pdev) \
++ if (!use_dt) bcm_register_device(pdev)
++
++#define i2c_register_board_info_dt(busnum, info, n) \
++ if (!use_dt) i2c_register_board_info(busnum, info, n)
++
++int calc_rsts(int partition)
++{
++ return PM_PASSWORD |
++ ((partition & (1 << 0)) << 0) |
++ ((partition & (1 << 1)) << 1) |
++ ((partition & (1 << 2)) << 2) |
++ ((partition & (1 << 3)) << 3) |
++ ((partition & (1 << 4)) << 4) |
++ ((partition & (1 << 5)) << 5);
++}
++
++static void bcm2708_restart(enum reboot_mode mode, const char *cmd)
++{
++ extern char bcm2708_reboot_mode;
++ uint32_t pm_rstc, pm_wdog;
++ uint32_t timeout = 10;
++ uint32_t pm_rsts = 0;
++
++ if(bcm2708_reboot_mode == 'q')
++ {
++ // NOOBS < 1.3 booting with reboot=q
++ pm_rsts = readl(__io_address(PM_RSTS));
++ pm_rsts = PM_PASSWORD | pm_rsts | PM_RSTS_HADWRQ_SET;
++ }
++ else if(bcm2708_reboot_mode == 'p')
++ {
++ // NOOBS < 1.3 halting
++ pm_rsts = readl(__io_address(PM_RSTS));
++ pm_rsts = PM_PASSWORD | pm_rsts | PM_RSTS_HADWRH_SET;
++ }
++ else
++ {
++ pm_rsts = calc_rsts(reboot_part);
++ }
++
++ writel(pm_rsts, __io_address(PM_RSTS));
++
++ /* Setup watchdog for reset */
++ pm_rstc = readl(__io_address(PM_RSTC));
++
++ pm_wdog = PM_PASSWORD | (timeout & PM_WDOG_TIME_SET); // watchdog timer = timer clock / 16; need password (31:16) + value (11:0)
++ pm_rstc = PM_PASSWORD | (pm_rstc & PM_RSTC_WRCFG_CLR) | PM_RSTC_WRCFG_FULL_RESET;
++
++ writel(pm_wdog, __io_address(PM_WDOG));
++ writel(pm_rstc, __io_address(PM_RSTC));
++}
++
++/* We can't really power off, but if we do the normal reset scheme, and indicate to bootcode.bin not to reboot, then most of the chip will be powered off */
++static void bcm2708_power_off(void)
++{
++ extern char bcm2708_reboot_mode;
++ if(bcm2708_reboot_mode == 'q')
++ {
++ // NOOBS < v1.3
++ bcm2708_restart('p', "");
++ }
++ else
++ {
++ /* partition 63 is special code for HALT the bootloader knows not to boot*/
++ reboot_part = 63;
++ /* continue with normal reset mechanism */
++ bcm2708_restart(0, "");
++ }
++}
++
++static void __init bcm2708_init_uart1(void)
++{
++ struct device_node *np;
++
++ np = of_find_compatible_node(NULL, NULL, "brcm,bcm2835-aux-uart");
++ if (of_device_is_available(np)) {
++ pr_info("bcm2708: Mini UART enabled\n");
++ writel(1, __io_address(UART1_BASE + 0x4));
++ }
++}
++
++#ifdef CONFIG_OF
++static void __init bcm2708_dt_init(void)
++{
++ int ret;
++
++ of_clk_init(NULL);
++ ret = of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
++ if (ret) {
++ pr_err("of_platform_populate failed: %d\n", ret);
++ /* Proceed as if CONFIG_OF was not defined */
++ } else {
++ use_dt = 1;
++ }
++}
++#else
++static void __init bcm2708_dt_init(void) { }
++#endif /* CONFIG_OF */
++
++void __init bcm2708_init(void)
++{
++ int i;
++
++#if defined(CONFIG_BCM_VC_CMA)
++ vc_cma_early_init();
++#endif
++ printk("bcm2708.uart_clock = %d\n", uart_clock);
++ pm_power_off = bcm2708_power_off;
++
++ bcm2708_init_clocks();
++ bcm2708_dt_init();
++
++ bcm_register_device_dt(&bcm2708_dmaengine_device);
++ bcm_register_device_dt(&bcm2708_vcio_device);
++ bcm_register_device_dt(&bcm2708_rpifw_device);
++ bcm_register_device_dt(&bcm2708_vchiq_device);
++#ifdef CONFIG_BCM2708_GPIO
++ bcm_register_device_dt(&bcm2708_gpio_device);
++#endif
++
++#if defined(CONFIG_PPS_CLIENT_GPIO) || defined(CONFIG_PPS_CLIENT_GPIO_MODULE)
++ if (!use_dt && (pps_gpio_pin >= 0)) {
++ pr_info("bcm2708: GPIO %d setup as pps-gpio device\n", pps_gpio_pin);
++ pps_gpio_info.gpio_pin = pps_gpio_pin;
++ pps_gpio_device.id = pps_gpio_pin;
++ bcm_register_device(&pps_gpio_device);
++ }
++#endif
++
++#if defined(CONFIG_W1_MASTER_GPIO) || defined(CONFIG_W1_MASTER_GPIO_MODULE)
++ w1_gpio_pdata.pin = w1_gpio_pin;
++ w1_gpio_pdata.ext_pullup_enable_pin = w1_gpio_pullup;
++ bcm_register_device_dt(&w1_device);
++#endif
++ bcm_register_device_dt(&bcm2708_fb_device);
++ bcm_register_device_dt(&bcm2708_usb_device);
++
++#ifdef CONFIG_MMC_BCM2835
++ bcm_register_device_dt(&bcm2835_emmc_device);
++#endif
++ bcm2708_init_led();
++ bcm2708_init_uart1();
++
++ /* Only create the platform devices for the ALSA driver in the
++ absence of an enabled "audio" DT node */
++ if (!use_dt ||
++ !of_device_is_available(of_find_node_by_path("/audio"))) {
++ for (i = 0; i < ARRAY_SIZE(bcm2708_alsa_devices); i++)
++ bcm_register_device(&bcm2708_alsa_devices[i]);
++ }
++
++ bcm_register_device_dt(&bcm2708_spi_device);
++
++ if (vc_i2c_override) {
++ bcm_register_device_dt(&bcm2708_bsc0_device);
++ bcm_register_device_dt(&bcm2708_bsc1_device);
++ } else if ((boardrev & 0xffffff) == 0x2 || (boardrev & 0xffffff) == 0x3) {
++ bcm_register_device_dt(&bcm2708_bsc0_device);
++ } else {
++ bcm_register_device_dt(&bcm2708_bsc1_device);
++ }
++
++ bcm_register_device_dt(&bcm2835_thermal_device);
++
++#if defined(CONFIG_SND_BCM2708_SOC_I2S) || defined(CONFIG_SND_BCM2708_SOC_I2S_MODULE)
++ bcm_register_device_dt(&bcm2708_i2s_device);
++#endif
++
++#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC_MODULE)
++ bcm_register_device_dt(&snd_hifiberry_dac_device);
++ bcm_register_device_dt(&snd_pcm5102a_codec_device);
++#endif
++
++#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS_MODULE)
++ bcm_register_device_dt(&snd_rpi_hifiberry_dacplus_device);
++ i2c_register_board_info_dt(1, snd_pcm512x_hbdacplus_i2c_devices, ARRAY_SIZE(snd_pcm512x_hbdacplus_i2c_devices));
++#endif
++
++#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI_MODULE)
++ bcm_register_device_dt(&snd_hifiberry_digi_device);
++ i2c_register_board_info_dt(1, snd_wm8804_i2c_devices, ARRAY_SIZE(snd_wm8804_i2c_devices));
++#endif
++
++#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP_MODULE)
++ bcm_register_device_dt(&snd_hifiberry_amp_device);
++ i2c_register_board_info_dt(1, snd_tas5713_i2c_devices, ARRAY_SIZE(snd_tas5713_i2c_devices));
++#endif
++
++#if defined(CONFIG_SND_BCM2708_SOC_RPI_DAC) || defined(CONFIG_SND_BCM2708_SOC_RPI_DAC_MODULE)
++ bcm_register_device_dt(&snd_rpi_dac_device);
++ bcm_register_device_dt(&snd_pcm1794a_codec_device);
++#endif
++
++#if defined(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC) || defined(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC_MODULE)
++ bcm_register_device_dt(&snd_rpi_iqaudio_dac_device);
++ i2c_register_board_info_dt(1, snd_pcm512x_i2c_devices, ARRAY_SIZE(snd_pcm512x_i2c_devices));
++#endif
++
++ if (!use_dt) {
++ for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
++ struct amba_device *d = amba_devs[i];
++ amba_device_register(d, &iomem_resource);
++ }
++ }
++ system_rev = boardrev;
++ system_serial_low = serial;
++
++#ifdef CONFIG_BCM2708_SPIDEV
++ if (!use_dt)
++ spi_register_board_info(bcm2708_spi_devices,
++ ARRAY_SIZE(bcm2708_spi_devices));
++#endif
++}
++
++static void timer_set_mode(enum clock_event_mode mode,
++ struct clock_event_device *clk)
++{
++ switch (mode) {
++ case CLOCK_EVT_MODE_ONESHOT: /* Leave the timer disabled, .set_next_event will enable it */
++ case CLOCK_EVT_MODE_SHUTDOWN:
++ break;
++ case CLOCK_EVT_MODE_PERIODIC:
++
++ case CLOCK_EVT_MODE_UNUSED:
++ case CLOCK_EVT_MODE_RESUME:
++
++ default:
++ printk(KERN_ERR "timer_set_mode: unhandled mode:%d\n",
++ (int)mode);
++ break;
++ }
++
++}
++
++static int timer_set_next_event(unsigned long cycles,
++ struct clock_event_device *unused)
++{
++ unsigned long stc;
++ do {
++ stc = readl(__io_address(ST_BASE + 0x04));
++ /* We could take a FIQ here, which may push ST above STC3 */
++ writel(stc + cycles, __io_address(ST_BASE + 0x18));
++ } while ((signed long) cycles >= 0 &&
++ (signed long) (readl(__io_address(ST_BASE + 0x04)) - stc)
++ >= (signed long) cycles);
++ return 0;
++}
++
++static struct clock_event_device timer0_clockevent = {
++ .name = "timer0",
++ .shift = 32,
++ .features = CLOCK_EVT_FEAT_ONESHOT,
++ .set_mode = timer_set_mode,
++ .set_next_event = timer_set_next_event,
++};
++
++/*
++ * IRQ handler for the timer
++ */
++static irqreturn_t bcm2708_timer_interrupt(int irq, void *dev_id)
++{
++ struct clock_event_device *evt = &timer0_clockevent;
++
++ writel(1 << 3, __io_address(ST_BASE + 0x00)); /* stcs clear timer int */
++
++ evt->event_handler(evt);
++
++ return IRQ_HANDLED;
++}
++
++static struct irqaction bcm2708_timer_irq = {
++ .name = "BCM2708 Timer Tick",
++ .flags = IRQF_TIMER | IRQF_IRQPOLL,
++ .handler = bcm2708_timer_interrupt,
++};
++
++/*
++ * Set up timer interrupt, and return the current time in seconds.
++ */
++
++static struct delay_timer bcm2708_delay_timer = {
++ .read_current_timer = bcm2708_read_current_timer,
++ .freq = STC_FREQ_HZ,
++};
++
++static void __init bcm2708_timer_init(void)
++{
++ /* init high res timer */
++ bcm2708_clocksource_init();
++
++ /*
++ * Make irqs happen for the system timer
++ */
++ setup_irq(IRQ_TIMER3, &bcm2708_timer_irq);
++
++ sched_clock_register(bcm2708_read_sched_clock, 32, STC_FREQ_HZ);
++
++ timer0_clockevent.mult =
++ div_sc(STC_FREQ_HZ, NSEC_PER_SEC, timer0_clockevent.shift);
++ timer0_clockevent.max_delta_ns =
++ clockevent_delta2ns(0xffffffff, &timer0_clockevent);
++ timer0_clockevent.min_delta_ns =
++ clockevent_delta2ns(0xf, &timer0_clockevent);
++
++ timer0_clockevent.cpumask = cpumask_of(0);
++ clockevents_register_device(&timer0_clockevent);
++
++ register_current_timer_delay(&bcm2708_delay_timer);
++}
++
++#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
++#include <linux/leds.h>
++
++static struct gpio_led bcm2708_leds[] = {
++ [0] = {
++ .gpio = 16,
++ .name = "led0",
++ .default_trigger = "mmc0",
++ .active_low = 1,
++ },
++};
++
++static struct gpio_led_platform_data bcm2708_led_pdata = {
++ .num_leds = ARRAY_SIZE(bcm2708_leds),
++ .leds = bcm2708_leds,
++};
++
++static struct platform_device bcm2708_led_device = {
++ .name = "leds-gpio",
++ .id = -1,
++ .dev = {
++ .platform_data = &bcm2708_led_pdata,
++ },
++};
++
++static void __init bcm2708_init_led(void)
++{
++ bcm2708_leds[0].gpio = disk_led_gpio;
++ bcm2708_leds[0].active_low = disk_led_active_low;
++ bcm_register_device_dt(&bcm2708_led_device);
++}
++#else
++static inline void bcm2708_init_led(void)
++{
++}
++#endif
++
++void __init bcm2708_init_early(void)
++{
++ /*
++ * Some devices allocate their coherent buffers from atomic
++ * context. Increase size of atomic coherent pool to make sure such
++ * the allocations won't fail.
++ */
++ init_dma_coherent_pool_size(SZ_4M);
++}
++
++static void __init board_reserve(void)
++{
++#if defined(CONFIG_BCM_VC_CMA)
++ vc_cma_reserve();
++#endif
++}
++
++static const char * const bcm2708_compat[] = {
++ "brcm,bcm2708",
++ NULL
++};
++
++MACHINE_START(BCM2708, "BCM2708")
++ /* Maintainer: Broadcom Europe Ltd. */
++ .map_io = bcm2708_map_io,
++ .init_irq = bcm2708_init_irq,
++ .init_time = bcm2708_timer_init,
++ .init_machine = bcm2708_init,
++ .init_early = bcm2708_init_early,
++ .reserve = board_reserve,
++ .restart = bcm2708_restart,
++ .dt_compat = bcm2708_compat,
++MACHINE_END
++
++module_param(boardrev, uint, 0644);
++module_param(serial, uint, 0644);
++module_param(uart_clock, uint, 0644);
++module_param(disk_led_gpio, uint, 0644);
++module_param(disk_led_active_low, uint, 0644);
++module_param(reboot_part, uint, 0644);
++module_param(w1_gpio_pin, uint, 0644);
++module_param(w1_gpio_pullup, uint, 0644);
++module_param(vc_i2c_override, bool, 0644);
++MODULE_PARM_DESC(vc_i2c_override, "Allow the use of VC's I2C peripheral.");
++module_param(pps_gpio_pin, int, 0644);
++MODULE_PARM_DESC(pps_gpio_pin, "Set GPIO pin to reserve for PPS");
+diff -Nur linux-4.1.3/arch/arm/mach-bcm2708/bcm2708_gpio.c linux-xbian-rpi/arch/arm/mach-bcm2708/bcm2708_gpio.c
+--- linux-4.1.3/arch/arm/mach-bcm2708/bcm2708_gpio.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/mach-bcm2708/bcm2708_gpio.c 2015-07-28 01:20:58.170137709 +0200
+@@ -0,0 +1,426 @@
++/*
++ * linux/arch/arm/mach-bcm2708/bcm2708_gpio.c
++ *
++ * Copyright (C) 2010 Broadcom
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#include <linux/spinlock.h>
++#include <linux/module.h>
++#include <linux/delay.h>
++#include <linux/list.h>
++#include <linux/io.h>
++#include <linux/irq.h>
++#include <linux/interrupt.h>
++#include <linux/slab.h>
++#include <mach/gpio.h>
++#include <linux/gpio.h>
++#include <linux/platform_device.h>
++#include <mach/platform.h>
++#include <linux/pinctrl/consumer.h>
++
++#include <linux/platform_data/bcm2708.h>
++
++#define BCM_GPIO_DRIVER_NAME "bcm2708_gpio"
++#define DRIVER_NAME BCM_GPIO_DRIVER_NAME
++#define BCM_GPIO_USE_IRQ 1
++
++#define GPIOFSEL(x) (0x00+(x)*4)
++#define GPIOSET(x) (0x1c+(x)*4)
++#define GPIOCLR(x) (0x28+(x)*4)
++#define GPIOLEV(x) (0x34+(x)*4)
++#define GPIOEDS(x) (0x40+(x)*4)
++#define GPIOREN(x) (0x4c+(x)*4)
++#define GPIOFEN(x) (0x58+(x)*4)
++#define GPIOHEN(x) (0x64+(x)*4)
++#define GPIOLEN(x) (0x70+(x)*4)
++#define GPIOAREN(x) (0x7c+(x)*4)
++#define GPIOAFEN(x) (0x88+(x)*4)
++#define GPIOUD(x) (0x94+(x)*4)
++#define GPIOUDCLK(x) (0x98+(x)*4)
++
++#define GPIO_BANKS 2
++
++enum { GPIO_FSEL_INPUT, GPIO_FSEL_OUTPUT,
++ GPIO_FSEL_ALT5, GPIO_FSEL_ALT_4,
++ GPIO_FSEL_ALT0, GPIO_FSEL_ALT1,
++ GPIO_FSEL_ALT2, GPIO_FSEL_ALT3,
++};
++
++ /* Each of the two spinlocks protects a different set of hardware
++ * regiters and data structurs. This decouples the code of the IRQ from
++ * the GPIO code. This also makes the case of a GPIO routine call from
++ * the IRQ code simpler.
++ */
++static DEFINE_SPINLOCK(lock); /* GPIO registers */
++
++struct bcm2708_gpio {
++ struct list_head list;
++ void __iomem *base;
++ struct gpio_chip gc;
++ unsigned long rising[(BCM2708_NR_GPIOS + 31) / 32];
++ unsigned long falling[(BCM2708_NR_GPIOS + 31) / 32];
++ unsigned long high[(BCM2708_NR_GPIOS + 31) / 32];
++ unsigned long low[(BCM2708_NR_GPIOS + 31) / 32];
++};
++
++static int bcm2708_set_function(struct gpio_chip *gc, unsigned offset,
++ int function)
++{
++ struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc);
++ unsigned long flags;
++ unsigned gpiodir;
++ unsigned gpio_bank = offset / 10;
++ unsigned gpio_field_offset = (offset - 10 * gpio_bank) * 3;
++
++//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_set_function %p (%d,%d)\n", gc, offset, function);
++ if (offset >= BCM2708_NR_GPIOS)
++ return -EINVAL;
++
++ spin_lock_irqsave(&lock, flags);
++
++ gpiodir = readl(gpio->base + GPIOFSEL(gpio_bank));
++ gpiodir &= ~(7 << gpio_field_offset);
++ gpiodir |= function << gpio_field_offset;
++ writel(gpiodir, gpio->base + GPIOFSEL(gpio_bank));
++ spin_unlock_irqrestore(&lock, flags);
++ gpiodir = readl(gpio->base + GPIOFSEL(gpio_bank));
++
++ return 0;
++}
++
++static int bcm2708_gpio_dir_in(struct gpio_chip *gc, unsigned offset)
++{
++ return bcm2708_set_function(gc, offset, GPIO_FSEL_INPUT);
++}
++
++static void bcm2708_gpio_set(struct gpio_chip *gc, unsigned offset, int value);
++static int bcm2708_gpio_dir_out(struct gpio_chip *gc, unsigned offset,
++ int value)
++{
++ int ret;
++ ret = bcm2708_set_function(gc, offset, GPIO_FSEL_OUTPUT);
++ if (ret >= 0)
++ bcm2708_gpio_set(gc, offset, value);
++ return ret;
++}
++
++static int bcm2708_gpio_get(struct gpio_chip *gc, unsigned offset)
++{
++ struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc);
++ unsigned gpio_bank = offset / 32;
++ unsigned gpio_field_offset = (offset - 32 * gpio_bank);
++ unsigned lev;
++
++ if (offset >= BCM2708_NR_GPIOS)
++ return 0;
++ lev = readl(gpio->base + GPIOLEV(gpio_bank));
++//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_get %p (%d)=%d\n", gc, offset, 0x1 & (lev>>gpio_field_offset));
++ return 0x1 & (lev >> gpio_field_offset);
++}
++
++static void bcm2708_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
++{
++ struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc);
++ unsigned gpio_bank = offset / 32;
++ unsigned gpio_field_offset = (offset - 32 * gpio_bank);
++//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_set %p (%d=%d)\n", gc, offset, value);
++ if (offset >= BCM2708_NR_GPIOS)
++ return;
++ if (value)
++ writel(1 << gpio_field_offset, gpio->base + GPIOSET(gpio_bank));
++ else
++ writel(1 << gpio_field_offset, gpio->base + GPIOCLR(gpio_bank));
++}
++
++/**********************
++ * extension to configure pullups
++ */
++int bcm2708_gpio_setpull(struct gpio_chip *gc, unsigned offset,
++ bcm2708_gpio_pull_t value)
++{
++ struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc);
++ unsigned gpio_bank = offset / 32;
++ unsigned gpio_field_offset = (offset - 32 * gpio_bank);
++
++ if (offset >= BCM2708_NR_GPIOS)
++ return -EINVAL;
++
++ switch (value) {
++ case BCM2708_PULL_UP:
++ writel(2, gpio->base + GPIOUD(0));
++ break;
++ case BCM2708_PULL_DOWN:
++ writel(1, gpio->base + GPIOUD(0));
++ break;
++ case BCM2708_PULL_OFF:
++ writel(0, gpio->base + GPIOUD(0));
++ break;
++ }
++
++ udelay(5);
++ writel(1 << gpio_field_offset, gpio->base + GPIOUDCLK(gpio_bank));
++ udelay(5);
++ writel(0, gpio->base + GPIOUD(0));
++ writel(0 << gpio_field_offset, gpio->base + GPIOUDCLK(gpio_bank));
++
++ return 0;
++}
++EXPORT_SYMBOL(bcm2708_gpio_setpull);
++
++/*************************************************************************************************************************
++ * bcm2708 GPIO IRQ
++ */
++
++#if BCM_GPIO_USE_IRQ
++
++static int bcm2708_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
++{
++ return gpio_to_irq(gpio);
++}
++
++static int bcm2708_gpio_irq_set_type(struct irq_data *d, unsigned type)
++{
++ unsigned irq = d->irq;
++ struct bcm2708_gpio *gpio = irq_get_chip_data(irq);
++ unsigned gn = irq_to_gpio(irq);
++ unsigned gb = gn / 32;
++ unsigned go = gn % 32;
++
++ gpio->rising[gb] &= ~(1 << go);
++ gpio->falling[gb] &= ~(1 << go);
++ gpio->high[gb] &= ~(1 << go);
++ gpio->low[gb] &= ~(1 << go);
++
++ if (type & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
++ return -EINVAL;
++
++ if (type & IRQ_TYPE_EDGE_RISING)
++ gpio->rising[gb] |= (1 << go);
++ if (type & IRQ_TYPE_EDGE_FALLING)
++ gpio->falling[gb] |= (1 << go);
++ if (type & IRQ_TYPE_LEVEL_HIGH)
++ gpio->high[gb] |= (1 << go);
++ if (type & IRQ_TYPE_LEVEL_LOW)
++ gpio->low[gb] |= (1 << go);
++ return 0;
++}
++
++static void bcm2708_gpio_irq_mask(struct irq_data *d)
++{
++ unsigned irq = d->irq;
++ struct bcm2708_gpio *gpio = irq_get_chip_data(irq);
++ unsigned gn = irq_to_gpio(irq);
++ unsigned gb = gn / 32;
++ unsigned long rising = readl(gpio->base + GPIOREN(gb));
++ unsigned long falling = readl(gpio->base + GPIOFEN(gb));
++ unsigned long high = readl(gpio->base + GPIOHEN(gb));
++ unsigned long low = readl(gpio->base + GPIOLEN(gb));
++
++ gn = gn % 32;
++
++ writel(rising & ~(1 << gn), gpio->base + GPIOREN(gb));
++ writel(falling & ~(1 << gn), gpio->base + GPIOFEN(gb));
++ writel(high & ~(1 << gn), gpio->base + GPIOHEN(gb));
++ writel(low & ~(1 << gn), gpio->base + GPIOLEN(gb));
++}
++
++static void bcm2708_gpio_irq_unmask(struct irq_data *d)
++{
++ unsigned irq = d->irq;
++ struct bcm2708_gpio *gpio = irq_get_chip_data(irq);
++ unsigned gn = irq_to_gpio(irq);
++ unsigned gb = gn / 32;
++ unsigned go = gn % 32;
++ unsigned long rising = readl(gpio->base + GPIOREN(gb));
++ unsigned long falling = readl(gpio->base + GPIOFEN(gb));
++ unsigned long high = readl(gpio->base + GPIOHEN(gb));
++ unsigned long low = readl(gpio->base + GPIOLEN(gb));
++
++ if (gpio->rising[gb] & (1 << go)) {
++ writel(rising | (1 << go), gpio->base + GPIOREN(gb));
++ } else {
++ writel(rising & ~(1 << go), gpio->base + GPIOREN(gb));
++ }
++
++ if (gpio->falling[gb] & (1 << go)) {
++ writel(falling | (1 << go), gpio->base + GPIOFEN(gb));
++ } else {
++ writel(falling & ~(1 << go), gpio->base + GPIOFEN(gb));
++ }
++
++ if (gpio->high[gb] & (1 << go)) {
++ writel(high | (1 << go), gpio->base + GPIOHEN(gb));
++ } else {
++ writel(high & ~(1 << go), gpio->base + GPIOHEN(gb));
++ }
++
++ if (gpio->low[gb] & (1 << go)) {
++ writel(low | (1 << go), gpio->base + GPIOLEN(gb));
++ } else {
++ writel(low & ~(1 << go), gpio->base + GPIOLEN(gb));
++ }
++}
++
++static struct irq_chip bcm2708_irqchip = {
++ .name = "GPIO",
++ .irq_enable = bcm2708_gpio_irq_unmask,
++ .irq_disable = bcm2708_gpio_irq_mask,
++ .irq_unmask = bcm2708_gpio_irq_unmask,
++ .irq_mask = bcm2708_gpio_irq_mask,
++ .irq_set_type = bcm2708_gpio_irq_set_type,
++};
++
++static irqreturn_t bcm2708_gpio_interrupt(int irq, void *dev_id)
++{
++ unsigned long edsr;
++ unsigned bank;
++ int i;
++ unsigned gpio;
++ unsigned level_bits;
++ struct bcm2708_gpio *gpio_data = dev_id;
++
++ for (bank = 0; bank < GPIO_BANKS; bank++) {
++ edsr = readl(__io_address(GPIO_BASE) + GPIOEDS(bank));
++ level_bits = gpio_data->high[bank] | gpio_data->low[bank];
++
++ for_each_set_bit(i, &edsr, 32) {
++ gpio = i + bank * 32;
++ /* ack edge triggered IRQs immediately */
++ if (!(level_bits & (1<<i)))
++ writel(1<<i,
++ __io_address(GPIO_BASE) + GPIOEDS(bank));
++ generic_handle_irq(gpio_to_irq(gpio));
++ /* ack level triggered IRQ after handling them */
++ if (level_bits & (1<<i))
++ writel(1<<i,
++ __io_address(GPIO_BASE) + GPIOEDS(bank));
++ }
++ }
++ return IRQ_HANDLED;
++}
++
++static struct irqaction bcm2708_gpio_irq = {
++ .name = "BCM2708 GPIO catchall handler",
++ .flags = IRQF_TIMER | IRQF_IRQPOLL,
++ .handler = bcm2708_gpio_interrupt,
++};
++
++static void bcm2708_gpio_irq_init(struct bcm2708_gpio *ucb)
++{
++ unsigned irq;
++
++ ucb->gc.to_irq = bcm2708_gpio_to_irq;
++
++ for (irq = GPIO_IRQ_START; irq < (GPIO_IRQ_START + GPIO_IRQS); irq++) {
++ irq_set_chip_data(irq, ucb);
++ irq_set_chip_and_handler(irq, &bcm2708_irqchip,
++ handle_simple_irq);
++ set_irq_flags(irq, IRQF_VALID);
++ }
++
++ bcm2708_gpio_irq.dev_id = ucb;
++ setup_irq(IRQ_GPIO3, &bcm2708_gpio_irq);
++}
++
++#else
++
++static void bcm2708_gpio_irq_init(struct bcm2708_gpio *ucb)
++{
++}
++
++#endif /* #if BCM_GPIO_USE_IRQ ***************************************************************************************************************** */
++
++static int bcm2708_gpio_probe(struct platform_device *dev)
++{
++ struct bcm2708_gpio *ucb;
++ struct resource *res;
++ int bank;
++ int err = 0;
++
++ printk(KERN_INFO DRIVER_NAME ": bcm2708_gpio_probe %p\n", dev);
++
++ ucb = kzalloc(sizeof(*ucb), GFP_KERNEL);
++ if (NULL == ucb) {
++ printk(KERN_ERR DRIVER_NAME ": failed to allocate "
++ "mailbox memory\n");
++ err = -ENOMEM;
++ goto err;
++ }
++
++ res = platform_get_resource(dev, IORESOURCE_MEM, 0);
++
++ platform_set_drvdata(dev, ucb);
++ ucb->base = __io_address(GPIO_BASE);
++
++ ucb->gc.label = "bcm2708_gpio";
++ ucb->gc.base = 0;
++ ucb->gc.ngpio = BCM2708_NR_GPIOS;
++ ucb->gc.owner = THIS_MODULE;
++
++ ucb->gc.direction_input = bcm2708_gpio_dir_in;
++ ucb->gc.direction_output = bcm2708_gpio_dir_out;
++ ucb->gc.get = bcm2708_gpio_get;
++ ucb->gc.set = bcm2708_gpio_set;
++ ucb->gc.can_sleep = 0;
++
++ for (bank = 0; bank < GPIO_BANKS; bank++) {
++ writel(0, ucb->base + GPIOREN(bank));
++ writel(0, ucb->base + GPIOFEN(bank));
++ writel(0, ucb->base + GPIOHEN(bank));
++ writel(0, ucb->base + GPIOLEN(bank));
++ writel(0, ucb->base + GPIOAREN(bank));
++ writel(0, ucb->base + GPIOAFEN(bank));
++ writel(~0, ucb->base + GPIOEDS(bank));
++ }
++
++ bcm2708_gpio_irq_init(ucb);
++
++ err = gpiochip_add(&ucb->gc);
++
++err:
++ return err;
++
++}
++
++static int bcm2708_gpio_remove(struct platform_device *dev)
++{
++ int err = 0;
++ struct bcm2708_gpio *ucb = platform_get_drvdata(dev);
++
++ printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_remove %p\n", dev);
++
++ gpiochip_remove(&ucb->gc);
++
++ platform_set_drvdata(dev, NULL);
++ kfree(ucb);
++
++ return err;
++}
++
++static struct platform_driver bcm2708_gpio_driver = {
++ .probe = bcm2708_gpio_probe,
++ .remove = bcm2708_gpio_remove,
++ .driver = {
++ .name = "bcm2708_gpio"},
++};
++
++static int __init bcm2708_gpio_init(void)
++{
++ return platform_driver_register(&bcm2708_gpio_driver);
++}
++
++static void __exit bcm2708_gpio_exit(void)
++{
++ platform_driver_unregister(&bcm2708_gpio_driver);
++}
++
++module_init(bcm2708_gpio_init);
++module_exit(bcm2708_gpio_exit);
++
++MODULE_DESCRIPTION("Broadcom BCM2708 GPIO driver");
++MODULE_LICENSE("GPL");
+diff -Nur linux-4.1.3/arch/arm/mach-bcm2708/bcm2708.h linux-xbian-rpi/arch/arm/mach-bcm2708/bcm2708.h
+--- linux-4.1.3/arch/arm/mach-bcm2708/bcm2708.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/mach-bcm2708/bcm2708.h 2015-07-28 01:20:58.170137709 +0200
+@@ -0,0 +1,49 @@
++/*
++ * linux/arch/arm/mach-bcm2708/bcm2708.h
++ *
++ * BCM2708 machine support header
++ *
++ * Copyright (C) 2010 Broadcom
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++
++#ifndef __BCM2708_BCM2708_H
++#define __BCM2708_BCM2708_H
++
++#include <linux/amba/bus.h>
++
++extern void __init bcm2708_init(void);
++extern void __init bcm2708_init_irq(void);
++extern void __init bcm2708_map_io(void);
++extern struct sys_timer bcm2708_timer;
++extern unsigned int mmc_status(struct device *dev);
++
++#define AMBA_DEVICE(name, busid, base, plat) \
++static struct amba_device name##_device = { \
++ .dev = { \
++ .coherent_dma_mask = ~0, \
++ .init_name = busid, \
++ .platform_data = plat, \
++ }, \
++ .res = { \
++ .start = base##_BASE, \
++ .end = (base##_BASE) + SZ_4K - 1,\
++ .flags = IORESOURCE_MEM, \
++ }, \
++ .irq = base##_IRQ, \
++}
++
++#endif
+diff -Nur linux-4.1.3/arch/arm/mach-bcm2708/include/mach/arm_control.h linux-xbian-rpi/arch/arm/mach-bcm2708/include/mach/arm_control.h
+--- linux-4.1.3/arch/arm/mach-bcm2708/include/mach/arm_control.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/mach-bcm2708/include/mach/arm_control.h 2015-07-28 01:20:58.170137709 +0200
+@@ -0,0 +1,419 @@
++/*
++ * linux/arch/arm/mach-bcm2708/arm_control.h
++ *
++ * Copyright (C) 2010 Broadcom
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++
++#ifndef __BCM2708_ARM_CONTROL_H
++#define __BCM2708_ARM_CONTROL_H
++
++/*
++ * Definitions and addresses for the ARM CONTROL logic
++ * This file is manually generated.
++ */
++
++#define ARM_BASE 0x7E00B000
++
++/* Basic configuration */
++#define ARM_CONTROL0 HW_REGISTER_RW(ARM_BASE+0x000)
++#define ARM_C0_SIZ128M 0x00000000
++#define ARM_C0_SIZ256M 0x00000001
++#define ARM_C0_SIZ512M 0x00000002
++#define ARM_C0_SIZ1G 0x00000003
++#define ARM_C0_BRESP0 0x00000000
++#define ARM_C0_BRESP1 0x00000004
++#define ARM_C0_BRESP2 0x00000008
++#define ARM_C0_BOOTHI 0x00000010
++#define ARM_C0_UNUSED05 0x00000020 /* free */
++#define ARM_C0_FULLPERI 0x00000040
++#define ARM_C0_UNUSED78 0x00000180 /* free */
++#define ARM_C0_JTAGMASK 0x00000E00
++#define ARM_C0_JTAGOFF 0x00000000
++#define ARM_C0_JTAGBASH 0x00000800 /* Debug on GPIO off */
++#define ARM_C0_JTAGGPIO 0x00000C00 /* Debug on GPIO on */
++#define ARM_C0_APROTMSK 0x0000F000
++#define ARM_C0_DBG0SYNC 0x00010000 /* VPU0 halt sync */
++#define ARM_C0_DBG1SYNC 0x00020000 /* VPU1 halt sync */
++#define ARM_C0_SWDBGREQ 0x00040000 /* HW debug request */
++#define ARM_C0_PASSHALT 0x00080000 /* ARM halt passed to debugger */
++#define ARM_C0_PRIO_PER 0x00F00000 /* per priority mask */
++#define ARM_C0_PRIO_L2 0x0F000000
++#define ARM_C0_PRIO_UC 0xF0000000
++
++#define ARM_C0_APROTPASS 0x0000A000 /* Translate 1:1 */
++#define ARM_C0_APROTUSER 0x00000000 /* Only user mode */
++#define ARM_C0_APROTSYST 0x0000F000 /* Only system mode */
++
++
++#define ARM_CONTROL1 HW_REGISTER_RW(ARM_BASE+0x440)
++#define ARM_C1_TIMER 0x00000001 /* re-route timer IRQ to VC */
++#define ARM_C1_MAIL 0x00000002 /* re-route Mail IRQ to VC */
++#define ARM_C1_BELL0 0x00000004 /* re-route Doorbell 0 to VC */
++#define ARM_C1_BELL1 0x00000008 /* re-route Doorbell 1 to VC */
++#define ARM_C1_PERSON 0x00000100 /* peripherals on */
++#define ARM_C1_REQSTOP 0x00000200 /* ASYNC bridge request stop */
++
++#define ARM_STATUS HW_REGISTER_RW(ARM_BASE+0x444)
++#define ARM_S_ACKSTOP 0x80000000 /* Bridge stopped */
++#define ARM_S_READPEND 0x000003FF /* pending reads counter */
++#define ARM_S_WRITPEND 0x000FFC00 /* pending writes counter */
++
++#define ARM_ERRHALT HW_REGISTER_RW(ARM_BASE+0x448)
++#define ARM_EH_PERIBURST 0x00000001 /* Burst write seen on peri bus */
++#define ARM_EH_ILLADDRS1 0x00000002 /* Address bits 25-27 error */
++#define ARM_EH_ILLADDRS2 0x00000004 /* Address bits 31-28 error */
++#define ARM_EH_VPU0HALT 0x00000008 /* VPU0 halted & in debug mode */
++#define ARM_EH_VPU1HALT 0x00000010 /* VPU1 halted & in debug mode */
++#define ARM_EH_ARMHALT 0x00000020 /* ARM in halted debug mode */
++
++#define ARM_ID_SECURE HW_REGISTER_RW(ARM_BASE+0x00C)
++#define ARM_ID HW_REGISTER_RW(ARM_BASE+0x44C)
++#define ARM_IDVAL 0x364D5241
++
++/* Translation memory */
++#define ARM_TRANSLATE HW_REGISTER_RW(ARM_BASE+0x100)
++/* 32 locations: 0x100.. 0x17F */
++/* 32 spare means we CAN go to 64 pages.... */
++
++
++/* Interrupts */
++#define ARM_IRQ_PEND0 HW_REGISTER_RW(ARM_BASE+0x200) /* Top IRQ bits */
++#define ARM_I0_TIMER 0x00000001 /* timer IRQ */
++#define ARM_I0_MAIL 0x00000002 /* Mail IRQ */
++#define ARM_I0_BELL0 0x00000004 /* Doorbell 0 */
++#define ARM_I0_BELL1 0x00000008 /* Doorbell 1 */
++#define ARM_I0_BANK1 0x00000100 /* Bank1 IRQ */
++#define ARM_I0_BANK2 0x00000200 /* Bank2 IRQ */
++
++#define ARM_IRQ_PEND1 HW_REGISTER_RW(ARM_BASE+0x204) /* All bank1 IRQ bits */
++/* todo: all I1_interrupt sources */
++#define ARM_IRQ_PEND2 HW_REGISTER_RW(ARM_BASE+0x208) /* All bank2 IRQ bits */
++/* todo: all I2_interrupt sources */
++
++#define ARM_IRQ_FAST HW_REGISTER_RW(ARM_BASE+0x20C) /* FIQ control */
++#define ARM_IF_INDEX 0x0000007F /* FIQ select */
++#define ARM_IF_ENABLE 0x00000080 /* FIQ enable */
++#define ARM_IF_VCMASK 0x0000003F /* FIQ = (index from VC source) */
++#define ARM_IF_TIMER 0x00000040 /* FIQ = ARM timer */
++#define ARM_IF_MAIL 0x00000041 /* FIQ = ARM Mail */
++#define ARM_IF_BELL0 0x00000042 /* FIQ = ARM Doorbell 0 */
++#define ARM_IF_BELL1 0x00000043 /* FIQ = ARM Doorbell 1 */
++#define ARM_IF_VP0HALT 0x00000044 /* FIQ = VPU0 Halt seen */
++#define ARM_IF_VP1HALT 0x00000045 /* FIQ = VPU1 Halt seen */
++#define ARM_IF_ILLEGAL 0x00000046 /* FIQ = Illegal access seen */
++
++#define ARM_IRQ_ENBL1 HW_REGISTER_RW(ARM_BASE+0x210) /* Bank1 enable bits */
++#define ARM_IRQ_ENBL2 HW_REGISTER_RW(ARM_BASE+0x214) /* Bank2 enable bits */
++#define ARM_IRQ_ENBL3 HW_REGISTER_RW(ARM_BASE+0x218) /* ARM irqs enable bits */
++#define ARM_IRQ_DIBL1 HW_REGISTER_RW(ARM_BASE+0x21C) /* Bank1 disable bits */
++#define ARM_IRQ_DIBL2 HW_REGISTER_RW(ARM_BASE+0x220) /* Bank2 disable bits */
++#define ARM_IRQ_DIBL3 HW_REGISTER_RW(ARM_BASE+0x224) /* ARM irqs disable bits */
++#define ARM_IE_TIMER 0x00000001 /* Timer IRQ */
++#define ARM_IE_MAIL 0x00000002 /* Mail IRQ */
++#define ARM_IE_BELL0 0x00000004 /* Doorbell 0 */
++#define ARM_IE_BELL1 0x00000008 /* Doorbell 1 */
++#define ARM_IE_VP0HALT 0x00000010 /* VPU0 Halt */
++#define ARM_IE_VP1HALT 0x00000020 /* VPU1 Halt */
++#define ARM_IE_ILLEGAL 0x00000040 /* Illegal access seen */
++
++/* Timer */
++/* For reg. fields see sp804 spec. */
++#define ARM_T_LOAD HW_REGISTER_RW(ARM_BASE+0x400)
++#define ARM_T_VALUE HW_REGISTER_RW(ARM_BASE+0x404)
++#define ARM_T_CONTROL HW_REGISTER_RW(ARM_BASE+0x408)
++#define ARM_T_IRQCNTL HW_REGISTER_RW(ARM_BASE+0x40C)
++#define ARM_T_RAWIRQ HW_REGISTER_RW(ARM_BASE+0x410)
++#define ARM_T_MSKIRQ HW_REGISTER_RW(ARM_BASE+0x414)
++#define ARM_T_RELOAD HW_REGISTER_RW(ARM_BASE+0x418)
++#define ARM_T_PREDIV HW_REGISTER_RW(ARM_BASE+0x41c)
++#define ARM_T_FREECNT HW_REGISTER_RW(ARM_BASE+0x420)
++
++#define TIMER_CTRL_ONESHOT (1 << 0)
++#define TIMER_CTRL_32BIT (1 << 1)
++#define TIMER_CTRL_DIV1 (0 << 2)
++#define TIMER_CTRL_DIV16 (1 << 2)
++#define TIMER_CTRL_DIV256 (2 << 2)
++#define TIMER_CTRL_IE (1 << 5)
++#define TIMER_CTRL_PERIODIC (1 << 6)
++#define TIMER_CTRL_ENABLE (1 << 7)
++#define TIMER_CTRL_DBGHALT (1 << 8)
++#define TIMER_CTRL_ENAFREE (1 << 9)
++#define TIMER_CTRL_FREEDIV_SHIFT 16)
++#define TIMER_CTRL_FREEDIV_MASK 0xff
++
++/* Semaphores, Doorbells, Mailboxes */
++#define ARM_SBM_OWN0 (ARM_BASE+0x800)
++#define ARM_SBM_OWN1 (ARM_BASE+0x900)
++#define ARM_SBM_OWN2 (ARM_BASE+0xA00)
++#define ARM_SBM_OWN3 (ARM_BASE+0xB00)
++
++/* MAILBOXES
++ * Register flags are common across all
++ * owner registers. See end of this section
++ *
++ * Semaphores, Doorbells, Mailboxes Owner 0
++ *
++ */
++
++#define ARM_0_SEMS HW_REGISTER_RW(ARM_SBM_OWN0+0x00)
++#define ARM_0_SEM0 HW_REGISTER_RW(ARM_SBM_OWN0+0x00)
++#define ARM_0_SEM1 HW_REGISTER_RW(ARM_SBM_OWN0+0x04)
++#define ARM_0_SEM2 HW_REGISTER_RW(ARM_SBM_OWN0+0x08)
++#define ARM_0_SEM3 HW_REGISTER_RW(ARM_SBM_OWN0+0x0C)
++#define ARM_0_SEM4 HW_REGISTER_RW(ARM_SBM_OWN0+0x10)
++#define ARM_0_SEM5 HW_REGISTER_RW(ARM_SBM_OWN0+0x14)
++#define ARM_0_SEM6 HW_REGISTER_RW(ARM_SBM_OWN0+0x18)
++#define ARM_0_SEM7 HW_REGISTER_RW(ARM_SBM_OWN0+0x1C)
++#define ARM_0_BELL0 HW_REGISTER_RW(ARM_SBM_OWN0+0x40)
++#define ARM_0_BELL1 HW_REGISTER_RW(ARM_SBM_OWN0+0x44)
++#define ARM_0_BELL2 HW_REGISTER_RW(ARM_SBM_OWN0+0x48)
++#define ARM_0_BELL3 HW_REGISTER_RW(ARM_SBM_OWN0+0x4C)
++/* MAILBOX 0 access in Owner 0 area */
++/* Some addresses should ONLY be used by owner 0 */
++#define ARM_0_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN0+0x80) /* .. 0x8C (4 locations) */
++#define ARM_0_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN0+0x80) /* .. 0x8C (4 locations) Normal read */
++#define ARM_0_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN0+0x90) /* none-pop read */
++#define ARM_0_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN0+0x94) /* Sender read (only LS 2 bits) */
++#define ARM_0_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN0+0x98) /* Status read */
++#define ARM_0_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN0+0x9C) /* Config read/write */
++/* MAILBOX 1 access in Owner 0 area */
++/* Owner 0 should only WRITE to this mailbox */
++#define ARM_0_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) /* .. 0xAC (4 locations) */
++/*#define ARM_0_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) */ /* DO NOT USE THIS !!!!! */
++/*#define ARM_0_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN0+0xB0) */ /* DO NOT USE THIS !!!!! */
++/*#define ARM_0_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN0+0xB4) */ /* DO NOT USE THIS !!!!! */
++#define ARM_0_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN0+0xB8) /* Status read */
++/*#define ARM_0_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN0+0xBC) */ /* DO NOT USE THIS !!!!! */
++/* General SEM, BELL, MAIL config/status */
++#define ARM_0_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN0+0xE0) /* semaphore clear/debug register */
++#define ARM_0_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN0+0xE4) /* Doorbells clear/debug register */
++#define ARM_0_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN0+0xF8) /* ALL interrupts */
++#define ARM_0_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN0+0xFC) /* IRQS pending for owner 0 */
++
++/* Semaphores, Doorbells, Mailboxes Owner 1 */
++#define ARM_1_SEMS HW_REGISTER_RW(ARM_SBM_OWN1+0x00)
++#define ARM_1_SEM0 HW_REGISTER_RW(ARM_SBM_OWN1+0x00)
++#define ARM_1_SEM1 HW_REGISTER_RW(ARM_SBM_OWN1+0x04)
++#define ARM_1_SEM2 HW_REGISTER_RW(ARM_SBM_OWN1+0x08)
++#define ARM_1_SEM3 HW_REGISTER_RW(ARM_SBM_OWN1+0x0C)
++#define ARM_1_SEM4 HW_REGISTER_RW(ARM_SBM_OWN1+0x10)
++#define ARM_1_SEM5 HW_REGISTER_RW(ARM_SBM_OWN1+0x14)
++#define ARM_1_SEM6 HW_REGISTER_RW(ARM_SBM_OWN1+0x18)
++#define ARM_1_SEM7 HW_REGISTER_RW(ARM_SBM_OWN1+0x1C)
++#define ARM_1_BELL0 HW_REGISTER_RW(ARM_SBM_OWN1+0x40)
++#define ARM_1_BELL1 HW_REGISTER_RW(ARM_SBM_OWN1+0x44)
++#define ARM_1_BELL2 HW_REGISTER_RW(ARM_SBM_OWN1+0x48)
++#define ARM_1_BELL3 HW_REGISTER_RW(ARM_SBM_OWN1+0x4C)
++/* MAILBOX 0 access in Owner 0 area */
++/* Owner 1 should only WRITE to this mailbox */
++#define ARM_1_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN1+0x80) /* .. 0x8C (4 locations) */
++/*#define ARM_1_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN1+0x80) */ /* DO NOT USE THIS !!!!! */
++/*#define ARM_1_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN1+0x90) */ /* DO NOT USE THIS !!!!! */
++/*#define ARM_1_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN1+0x94) */ /* DO NOT USE THIS !!!!! */
++#define ARM_1_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN1+0x98) /* Status read */
++/*#define ARM_1_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN1+0x9C) */ /* DO NOT USE THIS !!!!! */
++/* MAILBOX 1 access in Owner 0 area */
++#define ARM_1_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN1+0xA0) /* .. 0xAC (4 locations) */
++#define ARM_1_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN1+0xA0) /* .. 0xAC (4 locations) Normal read */
++#define ARM_1_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN1+0xB0) /* none-pop read */
++#define ARM_1_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN1+0xB4) /* Sender read (only LS 2 bits) */
++#define ARM_1_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN1+0xB8) /* Status read */
++#define ARM_1_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN1+0xBC)
++/* General SEM, BELL, MAIL config/status */
++#define ARM_1_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN1+0xE0) /* semaphore clear/debug register */
++#define ARM_1_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN1+0xE4) /* Doorbells clear/debug register */
++#define ARM_1_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN1+0xFC) /* IRQS pending for owner 1 */
++#define ARM_1_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN1+0xF8) /* ALL interrupts */
++
++/* Semaphores, Doorbells, Mailboxes Owner 2 */
++#define ARM_2_SEMS HW_REGISTER_RW(ARM_SBM_OWN2+0x00)
++#define ARM_2_SEM0 HW_REGISTER_RW(ARM_SBM_OWN2+0x00)
++#define ARM_2_SEM1 HW_REGISTER_RW(ARM_SBM_OWN2+0x04)
++#define ARM_2_SEM2 HW_REGISTER_RW(ARM_SBM_OWN2+0x08)
++#define ARM_2_SEM3 HW_REGISTER_RW(ARM_SBM_OWN2+0x0C)
++#define ARM_2_SEM4 HW_REGISTER_RW(ARM_SBM_OWN2+0x10)
++#define ARM_2_SEM5 HW_REGISTER_RW(ARM_SBM_OWN2+0x14)
++#define ARM_2_SEM6 HW_REGISTER_RW(ARM_SBM_OWN2+0x18)
++#define ARM_2_SEM7 HW_REGISTER_RW(ARM_SBM_OWN2+0x1C)
++#define ARM_2_BELL0 HW_REGISTER_RW(ARM_SBM_OWN2+0x40)
++#define ARM_2_BELL1 HW_REGISTER_RW(ARM_SBM_OWN2+0x44)
++#define ARM_2_BELL2 HW_REGISTER_RW(ARM_SBM_OWN2+0x48)
++#define ARM_2_BELL3 HW_REGISTER_RW(ARM_SBM_OWN2+0x4C)
++/* MAILBOX 0 access in Owner 2 area */
++/* Owner 2 should only WRITE to this mailbox */
++#define ARM_2_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN2+0x80) /* .. 0x8C (4 locations) */
++/*#define ARM_2_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN2+0x80) */ /* DO NOT USE THIS !!!!! */
++/*#define ARM_2_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN2+0x90) */ /* DO NOT USE THIS !!!!! */
++/*#define ARM_2_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN2+0x94) */ /* DO NOT USE THIS !!!!! */
++#define ARM_2_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN2+0x98) /* Status read */
++/*#define ARM_2_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN2+0x9C) */ /* DO NOT USE THIS !!!!! */
++/* MAILBOX 1 access in Owner 2 area */
++/* Owner 2 should only WRITE to this mailbox */
++#define ARM_2_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) /* .. 0xAC (4 locations) */
++/*#define ARM_2_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) */ /* DO NOT USE THIS !!!!! */
++/*#define ARM_2_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN2+0xB0) */ /* DO NOT USE THIS !!!!! */
++/*#define ARM_2_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN2+0xB4) */ /* DO NOT USE THIS !!!!! */
++#define ARM_2_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN2+0xB8) /* Status read */
++/*#define ARM_2_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN2+0xBC) */ /* DO NOT USE THIS !!!!! */
++/* General SEM, BELL, MAIL config/status */
++#define ARM_2_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN2+0xE0) /* semaphore clear/debug register */
++#define ARM_2_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN2+0xE4) /* Doorbells clear/debug register */
++#define ARM_2_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN2+0xFC) /* IRQS pending for owner 2 */
++#define ARM_2_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN2+0xF8) /* ALL interrupts */
++
++/* Semaphores, Doorbells, Mailboxes Owner 3 */
++#define ARM_3_SEMS HW_REGISTER_RW(ARM_SBM_OWN3+0x00)
++#define ARM_3_SEM0 HW_REGISTER_RW(ARM_SBM_OWN3+0x00)
++#define ARM_3_SEM1 HW_REGISTER_RW(ARM_SBM_OWN3+0x04)
++#define ARM_3_SEM2 HW_REGISTER_RW(ARM_SBM_OWN3+0x08)
++#define ARM_3_SEM3 HW_REGISTER_RW(ARM_SBM_OWN3+0x0C)
++#define ARM_3_SEM4 HW_REGISTER_RW(ARM_SBM_OWN3+0x10)
++#define ARM_3_SEM5 HW_REGISTER_RW(ARM_SBM_OWN3+0x14)
++#define ARM_3_SEM6 HW_REGISTER_RW(ARM_SBM_OWN3+0x18)
++#define ARM_3_SEM7 HW_REGISTER_RW(ARM_SBM_OWN3+0x1C)
++#define ARM_3_BELL0 HW_REGISTER_RW(ARM_SBM_OWN3+0x40)
++#define ARM_3_BELL1 HW_REGISTER_RW(ARM_SBM_OWN3+0x44)
++#define ARM_3_BELL2 HW_REGISTER_RW(ARM_SBM_OWN3+0x48)
++#define ARM_3_BELL3 HW_REGISTER_RW(ARM_SBM_OWN3+0x4C)
++/* MAILBOX 0 access in Owner 3 area */
++/* Owner 3 should only WRITE to this mailbox */
++#define ARM_3_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN3+0x80) /* .. 0x8C (4 locations) */
++/*#define ARM_3_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN3+0x80) */ /* DO NOT USE THIS !!!!! */
++/*#define ARM_3_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN3+0x90) */ /* DO NOT USE THIS !!!!! */
++/*#define ARM_3_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN3+0x94) */ /* DO NOT USE THIS !!!!! */
++#define ARM_3_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN3+0x98) /* Status read */
++/*#define ARM_3_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN3+0x9C) */ /* DO NOT USE THIS !!!!! */
++/* MAILBOX 1 access in Owner 3 area */
++/* Owner 3 should only WRITE to this mailbox */
++#define ARM_3_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) /* .. 0xAC (4 locations) */
++/*#define ARM_3_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) */ /* DO NOT USE THIS !!!!! */
++/*#define ARM_3_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN3+0xB0) */ /* DO NOT USE THIS !!!!! */
++/*#define ARM_3_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN3+0xB4) */ /* DO NOT USE THIS !!!!! */
++#define ARM_3_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN3+0xB8) /* Status read */
++/*#define ARM_3_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN3+0xBC) */ /* DO NOT USE THIS !!!!! */
++/* General SEM, BELL, MAIL config/status */
++#define ARM_3_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN3+0xE0) /* semaphore clear/debug register */
++#define ARM_3_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN3+0xE4) /* Doorbells clear/debug register */
++#define ARM_3_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN3+0xFC) /* IRQS pending for owner 3 */
++#define ARM_3_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN3+0xF8) /* ALL interrupts */
++
++
++
++/* Mailbox flags. Valid for all owners */
++
++/* Mailbox status register (...0x98) */
++#define ARM_MS_FULL 0x80000000
++#define ARM_MS_EMPTY 0x40000000
++#define ARM_MS_LEVEL 0x400000FF /* Max. value depdnds on mailbox depth parameter */
++
++/* MAILBOX config/status register (...0x9C) */
++/* ANY write to this register clears the error bits! */
++#define ARM_MC_IHAVEDATAIRQEN 0x00000001 /* mailbox irq enable: has data */
++#define ARM_MC_IHAVESPACEIRQEN 0x00000002 /* mailbox irq enable: has space */
++#define ARM_MC_OPPISEMPTYIRQEN 0x00000004 /* mailbox irq enable: Opp. is empty */
++#define ARM_MC_MAIL_CLEAR 0x00000008 /* mailbox clear write 1, then 0 */
++#define ARM_MC_IHAVEDATAIRQPEND 0x00000010 /* mailbox irq pending: has space */
++#define ARM_MC_IHAVESPACEIRQPEND 0x00000020 /* mailbox irq pending: Opp. is empty */
++#define ARM_MC_OPPISEMPTYIRQPEND 0x00000040 /* mailbox irq pending */
++/* Bit 7 is unused */
++#define ARM_MC_ERRNOOWN 0x00000100 /* error : none owner read from mailbox */
++#define ARM_MC_ERROVERFLW 0x00000200 /* error : write to fill mailbox */
++#define ARM_MC_ERRUNDRFLW 0x00000400 /* error : read from empty mailbox */
++
++/* Semaphore clear/debug register (...0xE0) */
++#define ARM_SD_OWN0 0x00000003 /* Owner of sem 0 */
++#define ARM_SD_OWN1 0x0000000C /* Owner of sem 1 */
++#define ARM_SD_OWN2 0x00000030 /* Owner of sem 2 */
++#define ARM_SD_OWN3 0x000000C0 /* Owner of sem 3 */
++#define ARM_SD_OWN4 0x00000300 /* Owner of sem 4 */
++#define ARM_SD_OWN5 0x00000C00 /* Owner of sem 5 */
++#define ARM_SD_OWN6 0x00003000 /* Owner of sem 6 */
++#define ARM_SD_OWN7 0x0000C000 /* Owner of sem 7 */
++#define ARM_SD_SEM0 0x00010000 /* Status of sem 0 */
++#define ARM_SD_SEM1 0x00020000 /* Status of sem 1 */
++#define ARM_SD_SEM2 0x00040000 /* Status of sem 2 */
++#define ARM_SD_SEM3 0x00080000 /* Status of sem 3 */
++#define ARM_SD_SEM4 0x00100000 /* Status of sem 4 */
++#define ARM_SD_SEM5 0x00200000 /* Status of sem 5 */
++#define ARM_SD_SEM6 0x00400000 /* Status of sem 6 */
++#define ARM_SD_SEM7 0x00800000 /* Status of sem 7 */
++
++/* Doorbells clear/debug register (...0xE4) */
++#define ARM_BD_OWN0 0x00000003 /* Owner of doorbell 0 */
++#define ARM_BD_OWN1 0x0000000C /* Owner of doorbell 1 */
++#define ARM_BD_OWN2 0x00000030 /* Owner of doorbell 2 */
++#define ARM_BD_OWN3 0x000000C0 /* Owner of doorbell 3 */
++#define ARM_BD_BELL0 0x00000100 /* Status of doorbell 0 */
++#define ARM_BD_BELL1 0x00000200 /* Status of doorbell 1 */
++#define ARM_BD_BELL2 0x00000400 /* Status of doorbell 2 */
++#define ARM_BD_BELL3 0x00000800 /* Status of doorbell 3 */
++
++/* MY IRQS register (...0xF8) */
++#define ARM_MYIRQ_BELL 0x00000001 /* This owner has a doorbell IRQ */
++#define ARM_MYIRQ_MAIL 0x00000002 /* This owner has a mailbox IRQ */
++
++/* ALL IRQS register (...0xF8) */
++#define ARM_AIS_BELL0 0x00000001 /* Doorbell 0 IRQ pending */
++#define ARM_AIS_BELL1 0x00000002 /* Doorbell 1 IRQ pending */
++#define ARM_AIS_BELL2 0x00000004 /* Doorbell 2 IRQ pending */
++#define ARM_AIS_BELL3 0x00000008 /* Doorbell 3 IRQ pending */
++#define ARM_AIS0_HAVEDATA 0x00000010 /* MAIL 0 has data IRQ pending */
++#define ARM_AIS0_HAVESPAC 0x00000020 /* MAIL 0 has space IRQ pending */
++#define ARM_AIS0_OPPEMPTY 0x00000040 /* MAIL 0 opposite is empty IRQ */
++#define ARM_AIS1_HAVEDATA 0x00000080 /* MAIL 1 has data IRQ pending */
++#define ARM_AIS1_HAVESPAC 0x00000100 /* MAIL 1 has space IRQ pending */
++#define ARM_AIS1_OPPEMPTY 0x00000200 /* MAIL 1 opposite is empty IRQ */
++/* Note that bell-0, bell-1 and MAIL0 IRQ go only to the ARM */
++/* Whilst that bell-2, bell-3 and MAIL1 IRQ go only to the VC */
++/* */
++/* ARM JTAG BASH */
++/* */
++#define AJB_BASE 0x7e2000c0
++
++#define AJBCONF HW_REGISTER_RW(AJB_BASE+0x00)
++#define AJB_BITS0 0x000000
++#define AJB_BITS4 0x000004
++#define AJB_BITS8 0x000008
++#define AJB_BITS12 0x00000C
++#define AJB_BITS16 0x000010
++#define AJB_BITS20 0x000014
++#define AJB_BITS24 0x000018
++#define AJB_BITS28 0x00001C
++#define AJB_BITS32 0x000020
++#define AJB_BITS34 0x000022
++#define AJB_OUT_MS 0x000040
++#define AJB_OUT_LS 0x000000
++#define AJB_INV_CLK 0x000080
++#define AJB_D0_RISE 0x000100
++#define AJB_D0_FALL 0x000000
++#define AJB_D1_RISE 0x000200
++#define AJB_D1_FALL 0x000000
++#define AJB_IN_RISE 0x000400
++#define AJB_IN_FALL 0x000000
++#define AJB_ENABLE 0x000800
++#define AJB_HOLD0 0x000000
++#define AJB_HOLD1 0x001000
++#define AJB_HOLD2 0x002000
++#define AJB_HOLD3 0x003000
++#define AJB_RESETN 0x004000
++#define AJB_CLKSHFT 16
++#define AJB_BUSY 0x80000000
++#define AJBTMS HW_REGISTER_RW(AJB_BASE+0x04)
++#define AJBTDI HW_REGISTER_RW(AJB_BASE+0x08)
++#define AJBTDO HW_REGISTER_RW(AJB_BASE+0x0c)
++
++#endif
+diff -Nur linux-4.1.3/arch/arm/mach-bcm2708/include/mach/clkdev.h linux-xbian-rpi/arch/arm/mach-bcm2708/include/mach/clkdev.h
+--- linux-4.1.3/arch/arm/mach-bcm2708/include/mach/clkdev.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/mach-bcm2708/include/mach/clkdev.h 2015-07-28 01:20:58.170137709 +0200
+@@ -0,0 +1,7 @@
++#ifndef __ASM_MACH_CLKDEV_H
++#define __ASM_MACH_CLKDEV_H
++
++#define __clk_get(clk) ({ 1; })
++#define __clk_put(clk) do { } while (0)
++
++#endif
+diff -Nur linux-4.1.3/arch/arm/mach-bcm2708/include/mach/debug-macro.S linux-xbian-rpi/arch/arm/mach-bcm2708/include/mach/debug-macro.S
+--- linux-4.1.3/arch/arm/mach-bcm2708/include/mach/debug-macro.S 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/mach-bcm2708/include/mach/debug-macro.S 2015-07-28 01:20:58.170137709 +0200
+@@ -0,0 +1,22 @@
++/* arch/arm/mach-bcm2708/include/mach/debug-macro.S
++ *
++ * Debugging macro include header
++ *
++ * Copyright (C) 2010 Broadcom
++ * Copyright (C) 1994-1999 Russell King
++ * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++*/
++
++#include <mach/platform.h>
++
++ .macro addruart, rp, rv, tmp
++ ldr \rp, =UART0_BASE
++ ldr \rv, =IO_ADDRESS(UART0_BASE)
++ .endm
++
++#include <debug/pl01x.S>
+diff -Nur linux-4.1.3/arch/arm/mach-bcm2708/include/mach/entry-macro.S linux-xbian-rpi/arch/arm/mach-bcm2708/include/mach/entry-macro.S
+--- linux-4.1.3/arch/arm/mach-bcm2708/include/mach/entry-macro.S 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/mach-bcm2708/include/mach/entry-macro.S 2015-07-28 01:20:58.170137709 +0200
+@@ -0,0 +1,69 @@
++/*
++ * arch/arm/mach-bcm2708/include/mach/entry-macro.S
++ *
++ * Low-level IRQ helper macros for BCM2708 platforms
++ *
++ * Copyright (C) 2010 Broadcom
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++#include <mach/hardware.h>
++
++ .macro disable_fiq
++ .endm
++
++ .macro get_irqnr_preamble, base, tmp
++ ldr \base, =IO_ADDRESS(ARMCTRL_IC_BASE)
++ .endm
++
++ .macro arch_ret_to_user, tmp1, tmp2
++ .endm
++
++ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
++ /* get masked status */
++ ldr \irqstat, [\base, #(ARM_IRQ_PEND0 - ARMCTRL_IC_BASE)]
++ mov \irqnr, #(ARM_IRQ0_BASE + 31)
++ and \tmp, \irqstat, #0x300 @ save bits 8 and 9
++ /* clear bits 8 and 9, and test */
++ bics \irqstat, \irqstat, #0x300
++ bne 1010f
++
++ tst \tmp, #0x100
++ ldrne \irqstat, [\base, #(ARM_IRQ_PEND1 - ARMCTRL_IC_BASE)]
++ movne \irqnr, #(ARM_IRQ1_BASE + 31)
++ @ Mask out the interrupts also present in PEND0 - see SW-5809
++ bicne \irqstat, #((1<<7) | (1<<9) | (1<<10))
++ bicne \irqstat, #((1<<18) | (1<<19))
++ bne 1010f
++
++ tst \tmp, #0x200
++ ldrne \irqstat, [\base, #(ARM_IRQ_PEND2 - ARMCTRL_IC_BASE)]
++ movne \irqnr, #(ARM_IRQ2_BASE + 31)
++ @ Mask out the interrupts also present in PEND0 - see SW-5809
++ bicne \irqstat, #((1<<21) | (1<<22) | (1<<23) | (1<<24) | (1<<25))
++ bicne \irqstat, #((1<<30))
++ beq 1020f
++
++1010:
++ @ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1))
++ @ N.B. CLZ is an ARM5 instruction.
++ sub \tmp, \irqstat, #1
++ eor \irqstat, \irqstat, \tmp
++ clz \tmp, \irqstat
++ sub \irqnr, \tmp
++
++1020: @ EQ will be set if no irqs pending
++
++ .endm
+diff -Nur linux-4.1.3/arch/arm/mach-bcm2708/include/mach/frc.h linux-xbian-rpi/arch/arm/mach-bcm2708/include/mach/frc.h
+--- linux-4.1.3/arch/arm/mach-bcm2708/include/mach/frc.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/mach-bcm2708/include/mach/frc.h 2015-07-28 01:20:58.170137709 +0200
+@@ -0,0 +1,38 @@
++/*
++ * arch/arm/mach-bcm2708/include/mach/timex.h
++ *
++ * BCM2708 free running counter (timer)
++ *
++ * Copyright (C) 2010 Broadcom
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++
++#ifndef _MACH_FRC_H
++#define _MACH_FRC_H
++
++#define FRC_TICK_RATE (1000000)
++
++/*! Free running counter incrementing at the CLOCK_TICK_RATE
++ (slightly faster than frc_clock_ticks63()
++ */
++extern unsigned long frc_clock_ticks32(void);
++
++/*! Free running counter incrementing at the CLOCK_TICK_RATE
++ * Note - top bit should be ignored (see cnt32_to_63)
++ */
++extern unsigned long long frc_clock_ticks63(void);
++
++#endif
+diff -Nur linux-4.1.3/arch/arm/mach-bcm2708/include/mach/gpio.h linux-xbian-rpi/arch/arm/mach-bcm2708/include/mach/gpio.h
+--- linux-4.1.3/arch/arm/mach-bcm2708/include/mach/gpio.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/mach-bcm2708/include/mach/gpio.h 2015-07-28 01:20:58.170137709 +0200
+@@ -0,0 +1,17 @@
++/*
++ * arch/arm/mach-bcm2708/include/mach/gpio.h
++ *
++ * This file is licensed under the terms of the GNU General Public
++ * License version 2. This program is licensed "as is" without any
++ * warranty of any kind, whether express or implied.
++ */
++
++#ifndef __ASM_ARCH_GPIO_H
++#define __ASM_ARCH_GPIO_H
++
++#define BCM2708_NR_GPIOS 54 // number of gpio lines
++
++#define gpio_to_irq(x) ((x) + GPIO_IRQ_START)
++#define irq_to_gpio(x) ((x) - GPIO_IRQ_START)
++
++#endif
+diff -Nur linux-4.1.3/arch/arm/mach-bcm2708/include/mach/hardware.h linux-xbian-rpi/arch/arm/mach-bcm2708/include/mach/hardware.h
+--- linux-4.1.3/arch/arm/mach-bcm2708/include/mach/hardware.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/mach-bcm2708/include/mach/hardware.h 2015-07-28 01:20:58.170137709 +0200
+@@ -0,0 +1,28 @@
++/*
++ * arch/arm/mach-bcm2708/include/mach/hardware.h
++ *
++ * This file contains the hardware definitions of the BCM2708 devices.
++ *
++ * Copyright (C) 2010 Broadcom
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++#ifndef __ASM_ARCH_HARDWARE_H
++#define __ASM_ARCH_HARDWARE_H
++
++#include <asm/sizes.h>
++#include <mach/platform.h>
++
++#endif
+diff -Nur linux-4.1.3/arch/arm/mach-bcm2708/include/mach/io.h linux-xbian-rpi/arch/arm/mach-bcm2708/include/mach/io.h
+--- linux-4.1.3/arch/arm/mach-bcm2708/include/mach/io.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/mach-bcm2708/include/mach/io.h 2015-07-28 01:20:58.170137709 +0200
+@@ -0,0 +1,27 @@
++/*
++ * arch/arm/mach-bcm2708/include/mach/io.h
++ *
++ * Copyright (C) 2003 ARM Limited
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++#ifndef __ASM_ARM_ARCH_IO_H
++#define __ASM_ARM_ARCH_IO_H
++
++#define IO_SPACE_LIMIT 0xffffffff
++
++#define __io(a) __typesafe_io(a)
++
++#endif
+diff -Nur linux-4.1.3/arch/arm/mach-bcm2708/include/mach/irqs.h linux-xbian-rpi/arch/arm/mach-bcm2708/include/mach/irqs.h
+--- linux-4.1.3/arch/arm/mach-bcm2708/include/mach/irqs.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/mach-bcm2708/include/mach/irqs.h 2015-07-28 01:20:58.170137709 +0200
+@@ -0,0 +1,199 @@
++/*
++ * arch/arm/mach-bcm2708/include/mach/irqs.h
++ *
++ * Copyright (C) 2010 Broadcom
++ * Copyright (C) 2003 ARM Limited
++ * Copyright (C) 2000 Deep Blue Solutions Ltd.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++
++#ifndef _BCM2708_IRQS_H_
++#define _BCM2708_IRQS_H_
++
++#include <mach/platform.h>
++
++/*
++ * IRQ interrupts definitions are the same as the INT definitions
++ * held within platform.h
++ */
++#define IRQ_ARMCTRL_START 0
++#define IRQ_TIMER0 (IRQ_ARMCTRL_START + INTERRUPT_TIMER0)
++#define IRQ_TIMER1 (IRQ_ARMCTRL_START + INTERRUPT_TIMER1)
++#define IRQ_TIMER2 (IRQ_ARMCTRL_START + INTERRUPT_TIMER2)
++#define IRQ_TIMER3 (IRQ_ARMCTRL_START + INTERRUPT_TIMER3)
++#define IRQ_CODEC0 (IRQ_ARMCTRL_START + INTERRUPT_CODEC0)
++#define IRQ_CODEC1 (IRQ_ARMCTRL_START + INTERRUPT_CODEC1)
++#define IRQ_CODEC2 (IRQ_ARMCTRL_START + INTERRUPT_CODEC2)
++#define IRQ_JPEG (IRQ_ARMCTRL_START + INTERRUPT_JPEG)
++#define IRQ_ISP (IRQ_ARMCTRL_START + INTERRUPT_ISP)
++#define IRQ_USB (IRQ_ARMCTRL_START + INTERRUPT_USB)
++#define IRQ_3D (IRQ_ARMCTRL_START + INTERRUPT_3D)
++#define IRQ_TRANSPOSER (IRQ_ARMCTRL_START + INTERRUPT_TRANSPOSER)
++#define IRQ_MULTICORESYNC0 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC0)
++#define IRQ_MULTICORESYNC1 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC1)
++#define IRQ_MULTICORESYNC2 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC2)
++#define IRQ_MULTICORESYNC3 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC3)
++#define IRQ_DMA0 (IRQ_ARMCTRL_START + INTERRUPT_DMA0)
++#define IRQ_DMA1 (IRQ_ARMCTRL_START + INTERRUPT_DMA1)
++#define IRQ_DMA2 (IRQ_ARMCTRL_START + INTERRUPT_DMA2)
++#define IRQ_DMA3 (IRQ_ARMCTRL_START + INTERRUPT_DMA3)
++#define IRQ_DMA4 (IRQ_ARMCTRL_START + INTERRUPT_DMA4)
++#define IRQ_DMA5 (IRQ_ARMCTRL_START + INTERRUPT_DMA5)
++#define IRQ_DMA6 (IRQ_ARMCTRL_START + INTERRUPT_DMA6)
++#define IRQ_DMA7 (IRQ_ARMCTRL_START + INTERRUPT_DMA7)
++#define IRQ_DMA8 (IRQ_ARMCTRL_START + INTERRUPT_DMA8)
++#define IRQ_DMA9 (IRQ_ARMCTRL_START + INTERRUPT_DMA9)
++#define IRQ_DMA10 (IRQ_ARMCTRL_START + INTERRUPT_DMA10)
++#define IRQ_DMA11 (IRQ_ARMCTRL_START + INTERRUPT_DMA11)
++#define IRQ_DMA12 (IRQ_ARMCTRL_START + INTERRUPT_DMA12)
++#define IRQ_AUX (IRQ_ARMCTRL_START + INTERRUPT_AUX)
++#define IRQ_ARM (IRQ_ARMCTRL_START + INTERRUPT_ARM)
++#define IRQ_VPUDMA (IRQ_ARMCTRL_START + INTERRUPT_VPUDMA)
++#define IRQ_HOSTPORT (IRQ_ARMCTRL_START + INTERRUPT_HOSTPORT)
++#define IRQ_VIDEOSCALER (IRQ_ARMCTRL_START + INTERRUPT_VIDEOSCALER)
++#define IRQ_CCP2TX (IRQ_ARMCTRL_START + INTERRUPT_CCP2TX)
++#define IRQ_SDC (IRQ_ARMCTRL_START + INTERRUPT_SDC)
++#define IRQ_DSI0 (IRQ_ARMCTRL_START + INTERRUPT_DSI0)
++#define IRQ_AVE (IRQ_ARMCTRL_START + INTERRUPT_AVE)
++#define IRQ_CAM0 (IRQ_ARMCTRL_START + INTERRUPT_CAM0)
++#define IRQ_CAM1 (IRQ_ARMCTRL_START + INTERRUPT_CAM1)
++#define IRQ_HDMI0 (IRQ_ARMCTRL_START + INTERRUPT_HDMI0)
++#define IRQ_HDMI1 (IRQ_ARMCTRL_START + INTERRUPT_HDMI1)
++#define IRQ_PIXELVALVE1 (IRQ_ARMCTRL_START + INTERRUPT_PIXELVALVE1)
++#define IRQ_I2CSPISLV (IRQ_ARMCTRL_START + INTERRUPT_I2CSPISLV)
++#define IRQ_DSI1 (IRQ_ARMCTRL_START + INTERRUPT_DSI1)
++#define IRQ_PWA0 (IRQ_ARMCTRL_START + INTERRUPT_PWA0)
++#define IRQ_PWA1 (IRQ_ARMCTRL_START + INTERRUPT_PWA1)
++#define IRQ_CPR (IRQ_ARMCTRL_START + INTERRUPT_CPR)
++#define IRQ_SMI (IRQ_ARMCTRL_START + INTERRUPT_SMI)
++#define IRQ_GPIO0 (IRQ_ARMCTRL_START + INTERRUPT_GPIO0)
++#define IRQ_GPIO1 (IRQ_ARMCTRL_START + INTERRUPT_GPIO1)
++#define IRQ_GPIO2 (IRQ_ARMCTRL_START + INTERRUPT_GPIO2)
++#define IRQ_GPIO3 (IRQ_ARMCTRL_START + INTERRUPT_GPIO3)
++#define IRQ_I2C (IRQ_ARMCTRL_START + INTERRUPT_I2C)
++#define IRQ_SPI (IRQ_ARMCTRL_START + INTERRUPT_SPI)
++#define IRQ_I2SPCM (IRQ_ARMCTRL_START + INTERRUPT_I2SPCM)
++#define IRQ_SDIO (IRQ_ARMCTRL_START + INTERRUPT_SDIO)
++#define IRQ_UART (IRQ_ARMCTRL_START + INTERRUPT_UART)
++#define IRQ_SLIMBUS (IRQ_ARMCTRL_START + INTERRUPT_SLIMBUS)
++#define IRQ_VEC (IRQ_ARMCTRL_START + INTERRUPT_VEC)
++#define IRQ_CPG (IRQ_ARMCTRL_START + INTERRUPT_CPG)
++#define IRQ_RNG (IRQ_ARMCTRL_START + INTERRUPT_RNG)
++#define IRQ_ARASANSDIO (IRQ_ARMCTRL_START + INTERRUPT_ARASANSDIO)
++#define IRQ_AVSPMON (IRQ_ARMCTRL_START + INTERRUPT_AVSPMON)
++
++#define IRQ_ARM_TIMER (IRQ_ARMCTRL_START + INTERRUPT_ARM_TIMER)
++#define IRQ_ARM_MAILBOX (IRQ_ARMCTRL_START + INTERRUPT_ARM_MAILBOX)
++#define IRQ_ARM_DOORBELL_0 (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_0)
++#define IRQ_ARM_DOORBELL_1 (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_1)
++#define IRQ_VPU0_HALTED (IRQ_ARMCTRL_START + INTERRUPT_VPU0_HALTED)
++#define IRQ_VPU1_HALTED (IRQ_ARMCTRL_START + INTERRUPT_VPU1_HALTED)
++#define IRQ_ILLEGAL_TYPE0 (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE0)
++#define IRQ_ILLEGAL_TYPE1 (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE1)
++#define IRQ_PENDING1 (IRQ_ARMCTRL_START + INTERRUPT_PENDING1)
++#define IRQ_PENDING2 (IRQ_ARMCTRL_START + INTERRUPT_PENDING2)
++
++#define FIQ_START HARD_IRQS
++
++/*
++ * FIQ interrupts definitions are the same as the INT definitions.
++ */
++#define FIQ_TIMER0 (FIQ_START+INTERRUPT_TIMER0)
++#define FIQ_TIMER1 (FIQ_START+INTERRUPT_TIMER1)
++#define FIQ_TIMER2 (FIQ_START+INTERRUPT_TIMER2)
++#define FIQ_TIMER3 (FIQ_START+INTERRUPT_TIMER3)
++#define FIQ_CODEC0 (FIQ_START+INTERRUPT_CODEC0)
++#define FIQ_CODEC1 (FIQ_START+INTERRUPT_CODEC1)
++#define FIQ_CODEC2 (FIQ_START+INTERRUPT_CODEC2)
++#define FIQ_JPEG (FIQ_START+INTERRUPT_JPEG)
++#define FIQ_ISP (FIQ_START+INTERRUPT_ISP)
++#define FIQ_USB (FIQ_START+INTERRUPT_USB)
++#define FIQ_3D (FIQ_START+INTERRUPT_3D)
++#define FIQ_TRANSPOSER (FIQ_START+INTERRUPT_TRANSPOSER)
++#define FIQ_MULTICORESYNC0 (FIQ_START+INTERRUPT_MULTICORESYNC0)
++#define FIQ_MULTICORESYNC1 (FIQ_START+INTERRUPT_MULTICORESYNC1)
++#define FIQ_MULTICORESYNC2 (FIQ_START+INTERRUPT_MULTICORESYNC2)
++#define FIQ_MULTICORESYNC3 (FIQ_START+INTERRUPT_MULTICORESYNC3)
++#define FIQ_DMA0 (FIQ_START+INTERRUPT_DMA0)
++#define FIQ_DMA1 (FIQ_START+INTERRUPT_DMA1)
++#define FIQ_DMA2 (FIQ_START+INTERRUPT_DMA2)
++#define FIQ_DMA3 (FIQ_START+INTERRUPT_DMA3)
++#define FIQ_DMA4 (FIQ_START+INTERRUPT_DMA4)
++#define FIQ_DMA5 (FIQ_START+INTERRUPT_DMA5)
++#define FIQ_DMA6 (FIQ_START+INTERRUPT_DMA6)
++#define FIQ_DMA7 (FIQ_START+INTERRUPT_DMA7)
++#define FIQ_DMA8 (FIQ_START+INTERRUPT_DMA8)
++#define FIQ_DMA9 (FIQ_START+INTERRUPT_DMA9)
++#define FIQ_DMA10 (FIQ_START+INTERRUPT_DMA10)
++#define FIQ_DMA11 (FIQ_START+INTERRUPT_DMA11)
++#define FIQ_DMA12 (FIQ_START+INTERRUPT_DMA12)
++#define FIQ_AUX (FIQ_START+INTERRUPT_AUX)
++#define FIQ_ARM (FIQ_START+INTERRUPT_ARM)
++#define FIQ_VPUDMA (FIQ_START+INTERRUPT_VPUDMA)
++#define FIQ_HOSTPORT (FIQ_START+INTERRUPT_HOSTPORT)
++#define FIQ_VIDEOSCALER (FIQ_START+INTERRUPT_VIDEOSCALER)
++#define FIQ_CCP2TX (FIQ_START+INTERRUPT_CCP2TX)
++#define FIQ_SDC (FIQ_START+INTERRUPT_SDC)
++#define FIQ_DSI0 (FIQ_START+INTERRUPT_DSI0)
++#define FIQ_AVE (FIQ_START+INTERRUPT_AVE)
++#define FIQ_CAM0 (FIQ_START+INTERRUPT_CAM0)
++#define FIQ_CAM1 (FIQ_START+INTERRUPT_CAM1)
++#define FIQ_HDMI0 (FIQ_START+INTERRUPT_HDMI0)
++#define FIQ_HDMI1 (FIQ_START+INTERRUPT_HDMI1)
++#define FIQ_PIXELVALVE1 (FIQ_START+INTERRUPT_PIXELVALVE1)
++#define FIQ_I2CSPISLV (FIQ_START+INTERRUPT_I2CSPISLV)
++#define FIQ_DSI1 (FIQ_START+INTERRUPT_DSI1)
++#define FIQ_PWA0 (FIQ_START+INTERRUPT_PWA0)
++#define FIQ_PWA1 (FIQ_START+INTERRUPT_PWA1)
++#define FIQ_CPR (FIQ_START+INTERRUPT_CPR)
++#define FIQ_SMI (FIQ_START+INTERRUPT_SMI)
++#define FIQ_GPIO0 (FIQ_START+INTERRUPT_GPIO0)
++#define FIQ_GPIO1 (FIQ_START+INTERRUPT_GPIO1)
++#define FIQ_GPIO2 (FIQ_START+INTERRUPT_GPIO2)
++#define FIQ_GPIO3 (FIQ_START+INTERRUPT_GPIO3)
++#define FIQ_I2C (FIQ_START+INTERRUPT_I2C)
++#define FIQ_SPI (FIQ_START+INTERRUPT_SPI)
++#define FIQ_I2SPCM (FIQ_START+INTERRUPT_I2SPCM)
++#define FIQ_SDIO (FIQ_START+INTERRUPT_SDIO)
++#define FIQ_UART (FIQ_START+INTERRUPT_UART)
++#define FIQ_SLIMBUS (FIQ_START+INTERRUPT_SLIMBUS)
++#define FIQ_VEC (FIQ_START+INTERRUPT_VEC)
++#define FIQ_CPG (FIQ_START+INTERRUPT_CPG)
++#define FIQ_RNG (FIQ_START+INTERRUPT_RNG)
++#define FIQ_ARASANSDIO (FIQ_START+INTERRUPT_ARASANSDIO)
++#define FIQ_AVSPMON (FIQ_START+INTERRUPT_AVSPMON)
++
++#define FIQ_ARM_TIMER (FIQ_START+INTERRUPT_ARM_TIMER)
++#define FIQ_ARM_MAILBOX (FIQ_START+INTERRUPT_ARM_MAILBOX)
++#define FIQ_ARM_DOORBELL_0 (FIQ_START+INTERRUPT_ARM_DOORBELL_0)
++#define FIQ_ARM_DOORBELL_1 (FIQ_START+INTERRUPT_ARM_DOORBELL_1)
++#define FIQ_VPU0_HALTED (FIQ_START+INTERRUPT_VPU0_HALTED)
++#define FIQ_VPU1_HALTED (FIQ_START+INTERRUPT_VPU1_HALTED)
++#define FIQ_ILLEGAL_TYPE0 (FIQ_START+INTERRUPT_ILLEGAL_TYPE0)
++#define FIQ_ILLEGAL_TYPE1 (FIQ_START+INTERRUPT_ILLEGAL_TYPE1)
++#define FIQ_PENDING1 (FIQ_START+INTERRUPT_PENDING1)
++#define FIQ_PENDING2 (FIQ_START+INTERRUPT_PENDING2)
++
++#define HARD_IRQS (64 + 21)
++#define FIQ_IRQS (64 + 21)
++#define GPIO_IRQ_START (HARD_IRQS + FIQ_IRQS)
++#define GPIO_IRQS (32*5)
++#define SPARE_ALLOC_IRQS 64
++#define BCM2708_ALLOC_IRQS (HARD_IRQS+FIQ_IRQS+GPIO_IRQS+SPARE_ALLOC_IRQS)
++#define FREE_IRQS 128
++#define NR_IRQS (BCM2708_ALLOC_IRQS+FREE_IRQS)
++
++#endif /* _BCM2708_IRQS_H_ */
+diff -Nur linux-4.1.3/arch/arm/mach-bcm2708/include/mach/memory.h linux-xbian-rpi/arch/arm/mach-bcm2708/include/mach/memory.h
+--- linux-4.1.3/arch/arm/mach-bcm2708/include/mach/memory.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/mach-bcm2708/include/mach/memory.h 2015-07-28 01:20:58.170137709 +0200
+@@ -0,0 +1,57 @@
++/*
++ * arch/arm/mach-bcm2708/include/mach/memory.h
++ *
++ * Copyright (C) 2010 Broadcom
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++#ifndef __ASM_ARCH_MEMORY_H
++#define __ASM_ARCH_MEMORY_H
++
++/* Memory overview:
++
++ [ARMcore] <--virtual addr-->
++ [ARMmmu] <--physical addr-->
++ [GERTmap] <--bus add-->
++ [VCperiph]
++
++*/
++
++/*
++ * Physical DRAM offset.
++ */
++#define BCM_PLAT_PHYS_OFFSET UL(0x00000000)
++#define VC_ARMMEM_OFFSET UL(0x00000000) /* offset in VC of ARM memory */
++
++#ifdef CONFIG_BCM2708_NOL2CACHE
++ #define _REAL_BUS_OFFSET UL(0xC0000000) /* don't use L1 or L2 caches */
++#else
++ #define _REAL_BUS_OFFSET UL(0x40000000) /* use L2 cache */
++#endif
++
++/* We're using the memory at 64M in the VideoCore for Linux - this adjustment
++ * will provide the offset into this area as well as setting the bits that
++ * stop the L1 and L2 cache from being used
++ *
++ * WARNING: this only works because the ARM is given memory at a fixed location
++ * (ARMMEM_OFFSET)
++ */
++#define BUS_OFFSET (VC_ARMMEM_OFFSET + _REAL_BUS_OFFSET)
++#define __virt_to_bus(x) ((x) + (BUS_OFFSET - PAGE_OFFSET))
++#define __bus_to_virt(x) ((x) - (BUS_OFFSET - PAGE_OFFSET))
++#define __pfn_to_bus(x) (__pfn_to_phys(x) + (BUS_OFFSET - BCM_PLAT_PHYS_OFFSET))
++#define __bus_to_pfn(x) __phys_to_pfn((x) - (BUS_OFFSET - BCM_PLAT_PHYS_OFFSET))
++
++#endif
+diff -Nur linux-4.1.3/arch/arm/mach-bcm2708/include/mach/platform.h linux-xbian-rpi/arch/arm/mach-bcm2708/include/mach/platform.h
+--- linux-4.1.3/arch/arm/mach-bcm2708/include/mach/platform.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/mach-bcm2708/include/mach/platform.h 2015-07-28 01:20:58.170137709 +0200
+@@ -0,0 +1,230 @@
++/*
++ * arch/arm/mach-bcm2708/include/mach/platform.h
++ *
++ * Copyright (C) 2010 Broadcom
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++
++#ifndef _BCM2708_PLATFORM_H
++#define _BCM2708_PLATFORM_H
++
++
++/* macros to get at IO space when running virtually */
++#define IO_ADDRESS(x) (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000)
++
++#define __io_address(n) IOMEM(IO_ADDRESS(n))
++
++
++/*
++ * SDRAM
++ */
++#define BCM2708_SDRAM_BASE 0x00000000
++
++/*
++ * Logic expansion modules
++ *
++ */
++
++
++/* ------------------------------------------------------------------------
++ * BCM2708 ARMCTRL Registers
++ * ------------------------------------------------------------------------
++ */
++
++#define HW_REGISTER_RW(addr) (addr)
++#define HW_REGISTER_RO(addr) (addr)
++
++#include "arm_control.h"
++#undef ARM_BASE
++
++/*
++ * Definitions and addresses for the ARM CONTROL logic
++ * This file is manually generated.
++ */
++
++#define BCM2708_PERI_BASE 0x20000000
++#define IC0_BASE (BCM2708_PERI_BASE + 0x2000)
++#define ST_BASE (BCM2708_PERI_BASE + 0x3000) /* System Timer */
++#define MPHI_BASE (BCM2708_PERI_BASE + 0x6000) /* Message -based Parallel Host Interface */
++#define DMA_BASE (BCM2708_PERI_BASE + 0x7000) /* DMA controller */
++#define ARM_BASE (BCM2708_PERI_BASE + 0xB000) /* BCM2708 ARM control block */
++#define PM_BASE (BCM2708_PERI_BASE + 0x100000) /* Power Management, Reset controller and Watchdog registers */
++#define PCM_CLOCK_BASE (BCM2708_PERI_BASE + 0x101098) /* PCM Clock */
++#define RNG_BASE (BCM2708_PERI_BASE + 0x104000) /* Hardware RNG */
++#define GPIO_BASE (BCM2708_PERI_BASE + 0x200000) /* GPIO */
++#define UART0_BASE (BCM2708_PERI_BASE + 0x201000) /* Uart 0 */
++#define MMCI0_BASE (BCM2708_PERI_BASE + 0x202000) /* MMC interface */
++#define I2S_BASE (BCM2708_PERI_BASE + 0x203000) /* I2S */
++#define SPI0_BASE (BCM2708_PERI_BASE + 0x204000) /* SPI0 */
++#define BSC0_BASE (BCM2708_PERI_BASE + 0x205000) /* BSC0 I2C/TWI */
++#define UART1_BASE (BCM2708_PERI_BASE + 0x215000) /* Uart 1 */
++#define EMMC_BASE (BCM2708_PERI_BASE + 0x300000) /* eMMC interface */
++#define SMI_BASE (BCM2708_PERI_BASE + 0x600000) /* SMI */
++#define BSC1_BASE (BCM2708_PERI_BASE + 0x804000) /* BSC1 I2C/TWI */
++#define USB_BASE (BCM2708_PERI_BASE + 0x980000) /* DTC_OTG USB controller */
++#define MCORE_BASE (BCM2708_PERI_BASE + 0x0000) /* Fake frame buffer device (actually the multicore sync block*/
++
++#define ARMCTRL_BASE (ARM_BASE + 0x000)
++#define ARMCTRL_IC_BASE (ARM_BASE + 0x200) /* ARM interrupt controller */
++#define ARMCTRL_TIMER0_1_BASE (ARM_BASE + 0x400) /* Timer 0 and 1 */
++#define ARMCTRL_0_SBM_BASE (ARM_BASE + 0x800) /* User 0 (ARM)'s Semaphores Doorbells and Mailboxes */
++#define ARMCTRL_0_BELL_BASE (ARMCTRL_0_SBM_BASE + 0x40) /* User 0 (ARM)'s Doorbell */
++#define ARMCTRL_0_MAIL0_BASE (ARMCTRL_0_SBM_BASE + 0x80) /* User 0 (ARM)'s Mailbox 0 */
++
++
++/*
++ * Interrupt assignments
++ */
++
++#define ARM_IRQ1_BASE 0
++#define INTERRUPT_TIMER0 (ARM_IRQ1_BASE + 0)
++#define INTERRUPT_TIMER1 (ARM_IRQ1_BASE + 1)
++#define INTERRUPT_TIMER2 (ARM_IRQ1_BASE + 2)
++#define INTERRUPT_TIMER3 (ARM_IRQ1_BASE + 3)
++#define INTERRUPT_CODEC0 (ARM_IRQ1_BASE + 4)
++#define INTERRUPT_CODEC1 (ARM_IRQ1_BASE + 5)
++#define INTERRUPT_CODEC2 (ARM_IRQ1_BASE + 6)
++#define INTERRUPT_VC_JPEG (ARM_IRQ1_BASE + 7)
++#define INTERRUPT_ISP (ARM_IRQ1_BASE + 8)
++#define INTERRUPT_VC_USB (ARM_IRQ1_BASE + 9)
++#define INTERRUPT_VC_3D (ARM_IRQ1_BASE + 10)
++#define INTERRUPT_TRANSPOSER (ARM_IRQ1_BASE + 11)
++#define INTERRUPT_MULTICORESYNC0 (ARM_IRQ1_BASE + 12)
++#define INTERRUPT_MULTICORESYNC1 (ARM_IRQ1_BASE + 13)
++#define INTERRUPT_MULTICORESYNC2 (ARM_IRQ1_BASE + 14)
++#define INTERRUPT_MULTICORESYNC3 (ARM_IRQ1_BASE + 15)
++#define INTERRUPT_DMA0 (ARM_IRQ1_BASE + 16)
++#define INTERRUPT_DMA1 (ARM_IRQ1_BASE + 17)
++#define INTERRUPT_VC_DMA2 (ARM_IRQ1_BASE + 18)
++#define INTERRUPT_VC_DMA3 (ARM_IRQ1_BASE + 19)
++#define INTERRUPT_DMA4 (ARM_IRQ1_BASE + 20)
++#define INTERRUPT_DMA5 (ARM_IRQ1_BASE + 21)
++#define INTERRUPT_DMA6 (ARM_IRQ1_BASE + 22)
++#define INTERRUPT_DMA7 (ARM_IRQ1_BASE + 23)
++#define INTERRUPT_DMA8 (ARM_IRQ1_BASE + 24)
++#define INTERRUPT_DMA9 (ARM_IRQ1_BASE + 25)
++#define INTERRUPT_DMA10 (ARM_IRQ1_BASE + 26)
++#define INTERRUPT_DMA11 (ARM_IRQ1_BASE + 27)
++#define INTERRUPT_DMA12 (ARM_IRQ1_BASE + 28)
++#define INTERRUPT_AUX (ARM_IRQ1_BASE + 29)
++#define INTERRUPT_ARM (ARM_IRQ1_BASE + 30)
++#define INTERRUPT_VPUDMA (ARM_IRQ1_BASE + 31)
++
++#define ARM_IRQ2_BASE 32
++#define INTERRUPT_HOSTPORT (ARM_IRQ2_BASE + 0)
++#define INTERRUPT_VIDEOSCALER (ARM_IRQ2_BASE + 1)
++#define INTERRUPT_CCP2TX (ARM_IRQ2_BASE + 2)
++#define INTERRUPT_SDC (ARM_IRQ2_BASE + 3)
++#define INTERRUPT_DSI0 (ARM_IRQ2_BASE + 4)
++#define INTERRUPT_AVE (ARM_IRQ2_BASE + 5)
++#define INTERRUPT_CAM0 (ARM_IRQ2_BASE + 6)
++#define INTERRUPT_CAM1 (ARM_IRQ2_BASE + 7)
++#define INTERRUPT_HDMI0 (ARM_IRQ2_BASE + 8)
++#define INTERRUPT_HDMI1 (ARM_IRQ2_BASE + 9)
++#define INTERRUPT_PIXELVALVE1 (ARM_IRQ2_BASE + 10)
++#define INTERRUPT_I2CSPISLV (ARM_IRQ2_BASE + 11)
++#define INTERRUPT_DSI1 (ARM_IRQ2_BASE + 12)
++#define INTERRUPT_PWA0 (ARM_IRQ2_BASE + 13)
++#define INTERRUPT_PWA1 (ARM_IRQ2_BASE + 14)
++#define INTERRUPT_CPR (ARM_IRQ2_BASE + 15)
++#define INTERRUPT_SMI (ARM_IRQ2_BASE + 16)
++#define INTERRUPT_GPIO0 (ARM_IRQ2_BASE + 17)
++#define INTERRUPT_GPIO1 (ARM_IRQ2_BASE + 18)
++#define INTERRUPT_GPIO2 (ARM_IRQ2_BASE + 19)
++#define INTERRUPT_GPIO3 (ARM_IRQ2_BASE + 20)
++#define INTERRUPT_VC_I2C (ARM_IRQ2_BASE + 21)
++#define INTERRUPT_VC_SPI (ARM_IRQ2_BASE + 22)
++#define INTERRUPT_VC_I2SPCM (ARM_IRQ2_BASE + 23)
++#define INTERRUPT_VC_SDIO (ARM_IRQ2_BASE + 24)
++#define INTERRUPT_VC_UART (ARM_IRQ2_BASE + 25)
++#define INTERRUPT_SLIMBUS (ARM_IRQ2_BASE + 26)
++#define INTERRUPT_VEC (ARM_IRQ2_BASE + 27)
++#define INTERRUPT_CPG (ARM_IRQ2_BASE + 28)
++#define INTERRUPT_RNG (ARM_IRQ2_BASE + 29)
++#define INTERRUPT_VC_ARASANSDIO (ARM_IRQ2_BASE + 30)
++#define INTERRUPT_AVSPMON (ARM_IRQ2_BASE + 31)
++
++#define ARM_IRQ0_BASE 64
++#define INTERRUPT_ARM_TIMER (ARM_IRQ0_BASE + 0)
++#define INTERRUPT_ARM_MAILBOX (ARM_IRQ0_BASE + 1)
++#define INTERRUPT_ARM_DOORBELL_0 (ARM_IRQ0_BASE + 2)
++#define INTERRUPT_ARM_DOORBELL_1 (ARM_IRQ0_BASE + 3)
++#define INTERRUPT_VPU0_HALTED (ARM_IRQ0_BASE + 4)
++#define INTERRUPT_VPU1_HALTED (ARM_IRQ0_BASE + 5)
++#define INTERRUPT_ILLEGAL_TYPE0 (ARM_IRQ0_BASE + 6)
++#define INTERRUPT_ILLEGAL_TYPE1 (ARM_IRQ0_BASE + 7)
++#define INTERRUPT_PENDING1 (ARM_IRQ0_BASE + 8)
++#define INTERRUPT_PENDING2 (ARM_IRQ0_BASE + 9)
++#define INTERRUPT_JPEG (ARM_IRQ0_BASE + 10)
++#define INTERRUPT_USB (ARM_IRQ0_BASE + 11)
++#define INTERRUPT_3D (ARM_IRQ0_BASE + 12)
++#define INTERRUPT_DMA2 (ARM_IRQ0_BASE + 13)
++#define INTERRUPT_DMA3 (ARM_IRQ0_BASE + 14)
++#define INTERRUPT_I2C (ARM_IRQ0_BASE + 15)
++#define INTERRUPT_SPI (ARM_IRQ0_BASE + 16)
++#define INTERRUPT_I2SPCM (ARM_IRQ0_BASE + 17)
++#define INTERRUPT_SDIO (ARM_IRQ0_BASE + 18)
++#define INTERRUPT_UART (ARM_IRQ0_BASE + 19)
++#define INTERRUPT_ARASANSDIO (ARM_IRQ0_BASE + 20)
++
++#define MAXIRQNUM (32 + 32 + 20)
++#define MAXFIQNUM (32 + 32 + 20)
++
++#define MAX_TIMER 2
++#define MAX_PERIOD 699050
++#define TICKS_PER_uSEC 1
++
++/*
++ * These are useconds NOT ticks.
++ *
++ */
++#define mSEC_1 1000
++#define mSEC_5 (mSEC_1 * 5)
++#define mSEC_10 (mSEC_1 * 10)
++#define mSEC_25 (mSEC_1 * 25)
++#define SEC_1 (mSEC_1 * 1000)
++
++/*
++ * Watchdog
++ */
++#define PM_RSTC (PM_BASE+0x1c)
++#define PM_RSTS (PM_BASE+0x20)
++#define PM_WDOG (PM_BASE+0x24)
++
++#define PM_WDOG_RESET 0000000000
++#define PM_PASSWORD 0x5a000000
++#define PM_WDOG_TIME_SET 0x000fffff
++#define PM_RSTC_WRCFG_CLR 0xffffffcf
++#define PM_RSTC_WRCFG_SET 0x00000030
++#define PM_RSTC_WRCFG_FULL_RESET 0x00000020
++#define PM_RSTC_RESET 0x00000102
++
++#define PM_RSTS_HADPOR_SET 0x00001000
++#define PM_RSTS_HADSRH_SET 0x00000400
++#define PM_RSTS_HADSRF_SET 0x00000200
++#define PM_RSTS_HADSRQ_SET 0x00000100
++#define PM_RSTS_HADWRH_SET 0x00000040
++#define PM_RSTS_HADWRF_SET 0x00000020
++#define PM_RSTS_HADWRQ_SET 0x00000010
++#define PM_RSTS_HADDRH_SET 0x00000004
++#define PM_RSTS_HADDRF_SET 0x00000002
++#define PM_RSTS_HADDRQ_SET 0x00000001
++
++#define UART0_CLOCK 3000000
++
++#endif
++
++/* END */
+diff -Nur linux-4.1.3/arch/arm/mach-bcm2708/include/mach/system.h linux-xbian-rpi/arch/arm/mach-bcm2708/include/mach/system.h
+--- linux-4.1.3/arch/arm/mach-bcm2708/include/mach/system.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/mach-bcm2708/include/mach/system.h 2015-07-28 01:20:58.170137709 +0200
+@@ -0,0 +1,38 @@
++/*
++ * arch/arm/mach-bcm2708/include/mach/system.h
++ *
++ * Copyright (C) 2010 Broadcom
++ * Copyright (C) 2003 ARM Limited
++ * Copyright (C) 2000 Deep Blue Solutions Ltd
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++#ifndef __ASM_ARCH_SYSTEM_H
++#define __ASM_ARCH_SYSTEM_H
++
++#include <linux/io.h>
++#include <mach/hardware.h>
++#include <mach/platform.h>
++
++static inline void arch_idle(void)
++{
++ /*
++ * This should do all the clock switching
++ * and wait for interrupt tricks
++ */
++ cpu_do_idle();
++}
++
++#endif
+diff -Nur linux-4.1.3/arch/arm/mach-bcm2708/include/mach/timex.h linux-xbian-rpi/arch/arm/mach-bcm2708/include/mach/timex.h
+--- linux-4.1.3/arch/arm/mach-bcm2708/include/mach/timex.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/mach-bcm2708/include/mach/timex.h 2015-07-28 01:20:58.170137709 +0200
+@@ -0,0 +1,23 @@
++/*
++ * arch/arm/mach-bcm2708/include/mach/timex.h
++ *
++ * BCM2708 sysem clock frequency
++ *
++ * Copyright (C) 2010 Broadcom
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++
++#define CLOCK_TICK_RATE (1000000)
+diff -Nur linux-4.1.3/arch/arm/mach-bcm2708/include/mach/uncompress.h linux-xbian-rpi/arch/arm/mach-bcm2708/include/mach/uncompress.h
+--- linux-4.1.3/arch/arm/mach-bcm2708/include/mach/uncompress.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/mach-bcm2708/include/mach/uncompress.h 2015-07-28 01:20:58.170137709 +0200
+@@ -0,0 +1,84 @@
++/*
++ * arch/arm/mach-bcn2708/include/mach/uncompress.h
++ *
++ * Copyright (C) 2010 Broadcom
++ * Copyright (C) 2003 ARM Limited
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++
++#include <linux/io.h>
++#include <linux/amba/serial.h>
++#include <mach/hardware.h>
++
++#define UART_BAUD 115200
++
++#define BCM2708_UART_DR __io(UART0_BASE + UART01x_DR)
++#define BCM2708_UART_FR __io(UART0_BASE + UART01x_FR)
++#define BCM2708_UART_IBRD __io(UART0_BASE + UART011_IBRD)
++#define BCM2708_UART_FBRD __io(UART0_BASE + UART011_FBRD)
++#define BCM2708_UART_LCRH __io(UART0_BASE + UART011_LCRH)
++#define BCM2708_UART_CR __io(UART0_BASE + UART011_CR)
++
++/*
++ * This does not append a newline
++ */
++static inline void putc(int c)
++{
++ while (__raw_readl(BCM2708_UART_FR) & UART01x_FR_TXFF)
++ barrier();
++
++ __raw_writel(c, BCM2708_UART_DR);
++}
++
++static inline void flush(void)
++{
++ int fr;
++
++ do {
++ fr = __raw_readl(BCM2708_UART_FR);
++ barrier();
++ } while ((fr & (UART011_FR_TXFE | UART01x_FR_BUSY)) != UART011_FR_TXFE);
++}
++
++static inline void arch_decomp_setup(void)
++{
++ int temp, div, rem, frac;
++
++ temp = 16 * UART_BAUD;
++ div = UART0_CLOCK / temp;
++ rem = UART0_CLOCK % temp;
++ temp = (8 * rem) / UART_BAUD;
++ frac = (temp >> 1) + (temp & 1);
++
++ /* Make sure the UART is disabled before we start */
++ __raw_writel(0, BCM2708_UART_CR);
++
++ /* Set the baud rate */
++ __raw_writel(div, BCM2708_UART_IBRD);
++ __raw_writel(frac, BCM2708_UART_FBRD);
++
++ /* Set the UART to 8n1, FIFO enabled */
++ __raw_writel(UART01x_LCRH_WLEN_8 | UART01x_LCRH_FEN, BCM2708_UART_LCRH);
++
++ /* Enable the UART */
++ __raw_writel(UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_RXE,
++ BCM2708_UART_CR);
++}
++
++/*
++ * nothing to do
++ */
++#define arch_decomp_wdog()
+diff -Nur linux-4.1.3/arch/arm/mach-bcm2708/include/mach/vc_sm_defs.h linux-xbian-rpi/arch/arm/mach-bcm2708/include/mach/vc_sm_defs.h
+--- linux-4.1.3/arch/arm/mach-bcm2708/include/mach/vc_sm_defs.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/mach-bcm2708/include/mach/vc_sm_defs.h 2015-07-28 01:20:58.170137709 +0200
+@@ -0,0 +1,181 @@
++/*****************************************************************************
++* Copyright 2011 Broadcom Corporation. All rights reserved.
++*
++* Unless you and Broadcom execute a separate written software license
++* agreement governing use of this software, this software is licensed to you
++* under the terms of the GNU General Public License version 2, available at
++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
++*
++* Notwithstanding the above, under no circumstances may you combine this
++* software in any way with any other Broadcom software provided under a
++* license other than the GPL, without Broadcom's express prior written
++* consent.
++*****************************************************************************/
++
++#ifndef __VC_SM_DEFS_H__INCLUDED__
++#define __VC_SM_DEFS_H__INCLUDED__
++
++/* FourCC code used for VCHI connection */
++#define VC_SM_SERVER_NAME MAKE_FOURCC("SMEM")
++
++/* Maximum message length */
++#define VC_SM_MAX_MSG_LEN (sizeof(VC_SM_MSG_UNION_T) + \
++ sizeof(VC_SM_MSG_HDR_T))
++#define VC_SM_MAX_RSP_LEN (sizeof(VC_SM_MSG_UNION_T))
++
++/* Resource name maximum size */
++#define VC_SM_RESOURCE_NAME 32
++
++/* All message types supported for HOST->VC direction */
++typedef enum {
++ /* Allocate shared memory block */
++ VC_SM_MSG_TYPE_ALLOC,
++ /* Lock allocated shared memory block */
++ VC_SM_MSG_TYPE_LOCK,
++ /* Unlock allocated shared memory block */
++ VC_SM_MSG_TYPE_UNLOCK,
++ /* Unlock allocated shared memory block, do not answer command */
++ VC_SM_MSG_TYPE_UNLOCK_NOANS,
++ /* Free shared memory block */
++ VC_SM_MSG_TYPE_FREE,
++ /* Resize a shared memory block */
++ VC_SM_MSG_TYPE_RESIZE,
++ /* Walk the allocated shared memory block(s) */
++ VC_SM_MSG_TYPE_WALK_ALLOC,
++
++ /* A previously applied action will need to be reverted */
++ VC_SM_MSG_TYPE_ACTION_CLEAN,
++ VC_SM_MSG_TYPE_MAX
++} VC_SM_MSG_TYPE;
++
++/* Type of memory to be allocated */
++typedef enum {
++ VC_SM_ALLOC_CACHED,
++ VC_SM_ALLOC_NON_CACHED,
++
++} VC_SM_ALLOC_TYPE_T;
++
++/* Message header for all messages in HOST->VC direction */
++typedef struct {
++ int32_t type;
++ uint32_t trans_id;
++ uint8_t body[0];
++
++} VC_SM_MSG_HDR_T;
++
++/* Request to allocate memory (HOST->VC) */
++typedef struct {
++ /* type of memory to allocate */
++ VC_SM_ALLOC_TYPE_T type;
++ /* byte amount of data to allocate per unit */
++ uint32_t base_unit;
++ /* number of unit to allocate */
++ uint32_t num_unit;
++ /* alignement to be applied on allocation */
++ uint32_t alignement;
++ /* identity of who allocated this block */
++ uint32_t allocator;
++ /* resource name (for easier tracking on vc side) */
++ char name[VC_SM_RESOURCE_NAME];
++
++} VC_SM_ALLOC_T;
++
++/* Result of a requested memory allocation (VC->HOST) */
++typedef struct {
++ /* Transaction identifier */
++ uint32_t trans_id;
++
++ /* Resource handle */
++ uint32_t res_handle;
++ /* Pointer to resource buffer */
++ void *res_mem;
++ /* Resource base size (bytes) */
++ uint32_t res_base_size;
++ /* Resource number */
++ uint32_t res_num;
++
++} VC_SM_ALLOC_RESULT_T;
++
++/* Request to free a previously allocated memory (HOST->VC) */
++typedef struct {
++ /* Resource handle (returned from alloc) */
++ uint32_t res_handle;
++ /* Resource buffer (returned from alloc) */
++ void *res_mem;
++
++} VC_SM_FREE_T;
++
++/* Request to lock a previously allocated memory (HOST->VC) */
++typedef struct {
++ /* Resource handle (returned from alloc) */
++ uint32_t res_handle;
++ /* Resource buffer (returned from alloc) */
++ void *res_mem;
++
++} VC_SM_LOCK_UNLOCK_T;
++
++/* Request to resize a previously allocated memory (HOST->VC) */
++typedef struct {
++ /* Resource handle (returned from alloc) */
++ uint32_t res_handle;
++ /* Resource buffer (returned from alloc) */
++ void *res_mem;
++ /* Resource *new* size requested (bytes) */
++ uint32_t res_new_size;
++
++} VC_SM_RESIZE_T;
++
++/* Result of a requested memory lock (VC->HOST) */
++typedef struct {
++ /* Transaction identifier */
++ uint32_t trans_id;
++
++ /* Resource handle */
++ uint32_t res_handle;
++ /* Pointer to resource buffer */
++ void *res_mem;
++ /* Pointer to former resource buffer if the memory
++ * was reallocated */
++ void *res_old_mem;
++
++} VC_SM_LOCK_RESULT_T;
++
++/* Generic result for a request (VC->HOST) */
++typedef struct {
++ /* Transaction identifier */
++ uint32_t trans_id;
++
++ int32_t success;
++
++} VC_SM_RESULT_T;
++
++/* Request to revert a previously applied action (HOST->VC) */
++typedef struct {
++ /* Action of interest */
++ VC_SM_MSG_TYPE res_action;
++ /* Transaction identifier for the action of interest */
++ uint32_t action_trans_id;
++
++} VC_SM_ACTION_CLEAN_T;
++
++/* Request to remove all data associated with a given allocator (HOST->VC) */
++typedef struct {
++ /* Allocator identifier */
++ uint32_t allocator;
++
++} VC_SM_FREE_ALL_T;
++
++/* Union of ALL messages */
++typedef union {
++ VC_SM_ALLOC_T alloc;
++ VC_SM_ALLOC_RESULT_T alloc_result;
++ VC_SM_FREE_T free;
++ VC_SM_ACTION_CLEAN_T action_clean;
++ VC_SM_RESIZE_T resize;
++ VC_SM_LOCK_RESULT_T lock_result;
++ VC_SM_RESULT_T result;
++ VC_SM_FREE_ALL_T free_all;
++
++} VC_SM_MSG_UNION_T;
++
++#endif /* __VC_SM_DEFS_H__INCLUDED__ */
+diff -Nur linux-4.1.3/arch/arm/mach-bcm2708/include/mach/vc_sm_knl.h linux-xbian-rpi/arch/arm/mach-bcm2708/include/mach/vc_sm_knl.h
+--- linux-4.1.3/arch/arm/mach-bcm2708/include/mach/vc_sm_knl.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/mach-bcm2708/include/mach/vc_sm_knl.h 2015-07-28 01:20:58.170137709 +0200
+@@ -0,0 +1,55 @@
++/*****************************************************************************
++* Copyright 2011 Broadcom Corporation. All rights reserved.
++*
++* Unless you and Broadcom execute a separate written software license
++* agreement governing use of this software, this software is licensed to you
++* under the terms of the GNU General Public License version 2, available at
++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
++*
++* Notwithstanding the above, under no circumstances may you combine this
++* software in any way with any other Broadcom software provided under a
++* license other than the GPL, without Broadcom's express prior written
++* consent.
++*****************************************************************************/
++
++#ifndef __VC_SM_KNL_H__INCLUDED__
++#define __VC_SM_KNL_H__INCLUDED__
++
++#if !defined(__KERNEL__)
++#error "This interface is for kernel use only..."
++#endif
++
++/* Type of memory to be locked (ie mapped) */
++typedef enum {
++ VC_SM_LOCK_CACHED,
++ VC_SM_LOCK_NON_CACHED,
++
++} VC_SM_LOCK_CACHE_MODE_T;
++
++/* Allocate a shared memory handle and block.
++*/
++int vc_sm_alloc(VC_SM_ALLOC_T *alloc, int *handle);
++
++/* Free a previously allocated shared memory handle and block.
++*/
++int vc_sm_free(int handle);
++
++/* Lock a memory handle for use by kernel.
++*/
++int vc_sm_lock(int handle, VC_SM_LOCK_CACHE_MODE_T mode,
++ long unsigned int *data);
++
++/* Unlock a memory handle in use by kernel.
++*/
++int vc_sm_unlock(int handle, int flush, int no_vc_unlock);
++
++/* Get an internal resource handle mapped from the external one.
++*/
++int vc_sm_int_handle(int handle);
++
++/* Map a shared memory region for use by kernel.
++*/
++int vc_sm_map(int handle, unsigned int sm_addr, VC_SM_LOCK_CACHE_MODE_T mode,
++ long unsigned int *data);
++
++#endif /* __VC_SM_KNL_H__INCLUDED__ */
+diff -Nur linux-4.1.3/arch/arm/mach-bcm2708/include/mach/vc_vchi_sm.h linux-xbian-rpi/arch/arm/mach-bcm2708/include/mach/vc_vchi_sm.h
+--- linux-4.1.3/arch/arm/mach-bcm2708/include/mach/vc_vchi_sm.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/mach-bcm2708/include/mach/vc_vchi_sm.h 2015-07-28 01:20:58.170137709 +0200
+@@ -0,0 +1,82 @@
++/*****************************************************************************
++* Copyright 2011 Broadcom Corporation. All rights reserved.
++*
++* Unless you and Broadcom execute a separate written software license
++* agreement governing use of this software, this software is licensed to you
++* under the terms of the GNU General Public License version 2, available at
++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
++*
++* Notwithstanding the above, under no circumstances may you combine this
++* software in any way with any other Broadcom software provided under a
++* license other than the GPL, without Broadcom's express prior written
++* consent.
++*****************************************************************************/
++
++#ifndef __VC_VCHI_SM_H__INCLUDED__
++#define __VC_VCHI_SM_H__INCLUDED__
++
++#include "interface/vchi/vchi.h"
++
++#include "vc_sm_defs.h"
++
++/* Forward declare.
++*/
++typedef struct sm_instance *VC_VCHI_SM_HANDLE_T;
++
++/* Initialize the shared memory service, opens up vchi connection to talk to it.
++*/
++VC_VCHI_SM_HANDLE_T vc_vchi_sm_init(VCHI_INSTANCE_T vchi_instance,
++ VCHI_CONNECTION_T **vchi_connections,
++ uint32_t num_connections);
++
++/* Terminates the shared memory service.
++*/
++int vc_vchi_sm_stop(VC_VCHI_SM_HANDLE_T *handle);
++
++/* Ask the shared memory service to allocate some memory on videocre and
++** return the result of this allocation (which upon success will be a pointer
++** to some memory in videocore space).
++*/
++int vc_vchi_sm_alloc(VC_VCHI_SM_HANDLE_T handle,
++ VC_SM_ALLOC_T *alloc,
++ VC_SM_ALLOC_RESULT_T *alloc_result, uint32_t *trans_id);
++
++/* Ask the shared memory service to free up some memory that was previously
++** allocated by the vc_vchi_sm_alloc function call.
++*/
++int vc_vchi_sm_free(VC_VCHI_SM_HANDLE_T handle,
++ VC_SM_FREE_T *free, uint32_t *trans_id);
++
++/* Ask the shared memory service to lock up some memory that was previously
++** allocated by the vc_vchi_sm_alloc function call.
++*/
++int vc_vchi_sm_lock(VC_VCHI_SM_HANDLE_T handle,
++ VC_SM_LOCK_UNLOCK_T *lock_unlock,
++ VC_SM_LOCK_RESULT_T *lock_result, uint32_t *trans_id);
++
++/* Ask the shared memory service to unlock some memory that was previously
++** allocated by the vc_vchi_sm_alloc function call.
++*/
++int vc_vchi_sm_unlock(VC_VCHI_SM_HANDLE_T handle,
++ VC_SM_LOCK_UNLOCK_T *lock_unlock,
++ uint32_t *trans_id, uint8_t wait_reply);
++
++/* Ask the shared memory service to resize some memory that was previously
++** allocated by the vc_vchi_sm_alloc function call.
++*/
++int vc_vchi_sm_resize(VC_VCHI_SM_HANDLE_T handle,
++ VC_SM_RESIZE_T *resize, uint32_t *trans_id);
++
++/* Walk the allocated resources on the videocore side, the allocation will
++** show up in the log. This is purely for debug/information and takes no
++** specific actions.
++*/
++int vc_vchi_sm_walk_alloc(VC_VCHI_SM_HANDLE_T handle);
++
++/* Clean up following a previously interrupted action which left the system
++** in a bad state of some sort.
++*/
++int vc_vchi_sm_clean_up(VC_VCHI_SM_HANDLE_T handle,
++ VC_SM_ACTION_CLEAN_T *action_clean);
++
++#endif /* __VC_VCHI_SM_H__INCLUDED__ */
+diff -Nur linux-4.1.3/arch/arm/mach-bcm2708/include/mach/vmalloc.h linux-xbian-rpi/arch/arm/mach-bcm2708/include/mach/vmalloc.h
+--- linux-4.1.3/arch/arm/mach-bcm2708/include/mach/vmalloc.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/mach-bcm2708/include/mach/vmalloc.h 2015-07-28 01:20:58.170137709 +0200
+@@ -0,0 +1,20 @@
++/*
++ * arch/arm/mach-bcm2708/include/mach/vmalloc.h
++ *
++ * Copyright (C) 2010 Broadcom
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++#define VMALLOC_END (0xe8000000)
+diff -Nur linux-4.1.3/arch/arm/mach-bcm2708/include/mach/vmcs_sm_ioctl.h linux-xbian-rpi/arch/arm/mach-bcm2708/include/mach/vmcs_sm_ioctl.h
+--- linux-4.1.3/arch/arm/mach-bcm2708/include/mach/vmcs_sm_ioctl.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/mach-bcm2708/include/mach/vmcs_sm_ioctl.h 2015-07-28 01:20:58.170137709 +0200
+@@ -0,0 +1,248 @@
++/*****************************************************************************
++* Copyright 2011 Broadcom Corporation. All rights reserved.
++*
++* Unless you and Broadcom execute a separate written software license
++* agreement governing use of this software, this software is licensed to you
++* under the terms of the GNU General Public License version 2, available at
++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
++*
++* Notwithstanding the above, under no circumstances may you combine this
++* software in any way with any other Broadcom software provided under a
++* license other than the GPL, without Broadcom's express prior written
++* consent.
++*
++*****************************************************************************/
++
++#if !defined(__VMCS_SM_IOCTL_H__INCLUDED__)
++#define __VMCS_SM_IOCTL_H__INCLUDED__
++
++/* ---- Include Files ---------------------------------------------------- */
++
++#if defined(__KERNEL__)
++#include <linux/types.h> /* Needed for standard types */
++#else
++#include <stdint.h>
++#endif
++
++#include <linux/ioctl.h>
++
++/* ---- Constants and Types ---------------------------------------------- */
++
++#define VMCS_SM_RESOURCE_NAME 32
++#define VMCS_SM_RESOURCE_NAME_DEFAULT "sm-host-resource"
++
++/* Type define used to create unique IOCTL number */
++#define VMCS_SM_MAGIC_TYPE 'I'
++
++/* IOCTL commands */
++enum vmcs_sm_cmd_e {
++ VMCS_SM_CMD_ALLOC = 0x5A, /* Start at 0x5A arbitrarily */
++ VMCS_SM_CMD_ALLOC_SHARE,
++ VMCS_SM_CMD_LOCK,
++ VMCS_SM_CMD_LOCK_CACHE,
++ VMCS_SM_CMD_UNLOCK,
++ VMCS_SM_CMD_RESIZE,
++ VMCS_SM_CMD_UNMAP,
++ VMCS_SM_CMD_FREE,
++ VMCS_SM_CMD_FLUSH,
++ VMCS_SM_CMD_INVALID,
++
++ VMCS_SM_CMD_SIZE_USR_HANDLE,
++ VMCS_SM_CMD_CHK_USR_HANDLE,
++
++ VMCS_SM_CMD_MAPPED_USR_HANDLE,
++ VMCS_SM_CMD_MAPPED_USR_ADDRESS,
++ VMCS_SM_CMD_MAPPED_VC_HDL_FROM_ADDR,
++ VMCS_SM_CMD_MAPPED_VC_HDL_FROM_HDL,
++ VMCS_SM_CMD_MAPPED_VC_ADDR_FROM_HDL,
++
++ VMCS_SM_CMD_VC_WALK_ALLOC,
++ VMCS_SM_CMD_HOST_WALK_MAP,
++ VMCS_SM_CMD_HOST_WALK_PID_ALLOC,
++ VMCS_SM_CMD_HOST_WALK_PID_MAP,
++
++ VMCS_SM_CMD_CLEAN_INVALID,
++
++ VMCS_SM_CMD_LAST /* Do no delete */
++};
++
++/* Cache type supported, conveniently matches the user space definition in
++** user-vcsm.h.
++*/
++enum vmcs_sm_cache_e {
++ VMCS_SM_CACHE_NONE,
++ VMCS_SM_CACHE_HOST,
++ VMCS_SM_CACHE_VC,
++ VMCS_SM_CACHE_BOTH,
++};
++
++/* IOCTL Data structures */
++struct vmcs_sm_ioctl_alloc {
++ /* user -> kernel */
++ unsigned int size;
++ unsigned int num;
++ enum vmcs_sm_cache_e cached;
++ char name[VMCS_SM_RESOURCE_NAME];
++
++ /* kernel -> user */
++ unsigned int handle;
++ /* unsigned int base_addr; */
++};
++
++struct vmcs_sm_ioctl_alloc_share {
++ /* user -> kernel */
++ unsigned int handle;
++ unsigned int size;
++};
++
++struct vmcs_sm_ioctl_free {
++ /* user -> kernel */
++ unsigned int handle;
++ /* unsigned int base_addr; */
++};
++
++struct vmcs_sm_ioctl_lock_unlock {
++ /* user -> kernel */
++ unsigned int handle;
++
++ /* kernel -> user */
++ unsigned int addr;
++};
++
++struct vmcs_sm_ioctl_lock_cache {
++ /* user -> kernel */
++ unsigned int handle;
++ enum vmcs_sm_cache_e cached;
++};
++
++struct vmcs_sm_ioctl_resize {
++ /* user -> kernel */
++ unsigned int handle;
++ unsigned int new_size;
++
++ /* kernel -> user */
++ unsigned int old_size;
++};
++
++struct vmcs_sm_ioctl_map {
++ /* user -> kernel */
++ /* and kernel -> user */
++ unsigned int pid;
++ unsigned int handle;
++ unsigned int addr;
++
++ /* kernel -> user */
++ unsigned int size;
++};
++
++struct vmcs_sm_ioctl_walk {
++ /* user -> kernel */
++ unsigned int pid;
++};
++
++struct vmcs_sm_ioctl_chk {
++ /* user -> kernel */
++ unsigned int handle;
++
++ /* kernel -> user */
++ unsigned int addr;
++ unsigned int size;
++ enum vmcs_sm_cache_e cache;
++};
++
++struct vmcs_sm_ioctl_size {
++ /* user -> kernel */
++ unsigned int handle;
++
++ /* kernel -> user */
++ unsigned int size;
++};
++
++struct vmcs_sm_ioctl_cache {
++ /* user -> kernel */
++ unsigned int handle;
++ unsigned int addr;
++ unsigned int size;
++};
++
++struct vmcs_sm_ioctl_clean_invalid {
++ /* user -> kernel */
++ struct {
++ unsigned int cmd;
++ unsigned int handle;
++ unsigned int addr;
++ unsigned int size;
++ } s[8];
++};
++
++/* IOCTL numbers */
++#define VMCS_SM_IOCTL_MEM_ALLOC\
++ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_ALLOC,\
++ struct vmcs_sm_ioctl_alloc)
++#define VMCS_SM_IOCTL_MEM_ALLOC_SHARE\
++ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_ALLOC_SHARE,\
++ struct vmcs_sm_ioctl_alloc_share)
++#define VMCS_SM_IOCTL_MEM_LOCK\
++ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_LOCK,\
++ struct vmcs_sm_ioctl_lock_unlock)
++#define VMCS_SM_IOCTL_MEM_LOCK_CACHE\
++ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_LOCK_CACHE,\
++ struct vmcs_sm_ioctl_lock_cache)
++#define VMCS_SM_IOCTL_MEM_UNLOCK\
++ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_UNLOCK,\
++ struct vmcs_sm_ioctl_lock_unlock)
++#define VMCS_SM_IOCTL_MEM_RESIZE\
++ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_RESIZE,\
++ struct vmcs_sm_ioctl_resize)
++#define VMCS_SM_IOCTL_MEM_FREE\
++ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_FREE,\
++ struct vmcs_sm_ioctl_free)
++#define VMCS_SM_IOCTL_MEM_FLUSH\
++ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_FLUSH,\
++ struct vmcs_sm_ioctl_cache)
++#define VMCS_SM_IOCTL_MEM_INVALID\
++ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_INVALID,\
++ struct vmcs_sm_ioctl_cache)
++#define VMCS_SM_IOCTL_MEM_CLEAN_INVALID\
++ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_CLEAN_INVALID,\
++ struct vmcs_sm_ioctl_clean_invalid)
++
++#define VMCS_SM_IOCTL_SIZE_USR_HDL\
++ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_SIZE_USR_HANDLE,\
++ struct vmcs_sm_ioctl_size)
++#define VMCS_SM_IOCTL_CHK_USR_HDL\
++ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_CHK_USR_HANDLE,\
++ struct vmcs_sm_ioctl_chk)
++
++#define VMCS_SM_IOCTL_MAP_USR_HDL\
++ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_MAPPED_USR_HANDLE,\
++ struct vmcs_sm_ioctl_map)
++#define VMCS_SM_IOCTL_MAP_USR_ADDRESS\
++ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_MAPPED_USR_ADDRESS,\
++ struct vmcs_sm_ioctl_map)
++#define VMCS_SM_IOCTL_MAP_VC_HDL_FR_ADDR\
++ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_MAPPED_VC_HDL_FROM_ADDR,\
++ struct vmcs_sm_ioctl_map)
++#define VMCS_SM_IOCTL_MAP_VC_HDL_FR_HDL\
++ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_MAPPED_VC_HDL_FROM_HDL,\
++ struct vmcs_sm_ioctl_map)
++#define VMCS_SM_IOCTL_MAP_VC_ADDR_FR_HDL\
++ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_MAPPED_VC_ADDR_FROM_HDL,\
++ struct vmcs_sm_ioctl_map)
++
++#define VMCS_SM_IOCTL_VC_WALK_ALLOC\
++ _IO(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_VC_WALK_ALLOC)
++#define VMCS_SM_IOCTL_HOST_WALK_MAP\
++ _IO(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_HOST_WALK_MAP)
++#define VMCS_SM_IOCTL_HOST_WALK_PID_ALLOC\
++ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_HOST_WALK_PID_ALLOC,\
++ struct vmcs_sm_ioctl_walk)
++#define VMCS_SM_IOCTL_HOST_WALK_PID_MAP\
++ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_HOST_WALK_PID_MAP,\
++ struct vmcs_sm_ioctl_walk)
++
++/* ---- Variable Externs ------------------------------------------------- */
++
++/* ---- Function Prototypes ---------------------------------------------- */
++
++#endif /* __VMCS_SM_IOCTL_H__INCLUDED__ */
+diff -Nur linux-4.1.3/arch/arm/mach-bcm2708/Kconfig linux-xbian-rpi/arch/arm/mach-bcm2708/Kconfig
+--- linux-4.1.3/arch/arm/mach-bcm2708/Kconfig 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/mach-bcm2708/Kconfig 2015-07-28 01:20:58.170137709 +0200
+@@ -0,0 +1,45 @@
++menu "Broadcom BCM2708 Implementations"
++ depends on ARCH_BCM2708
++
++config MACH_BCM2708
++ bool "Broadcom BCM2708 Development Platform"
++ select NEED_MACH_MEMORY_H
++ select NEED_MACH_IO_H
++ select CPU_V6
++ help
++ Include support for the Broadcom(R) BCM2708 platform.
++
++config BCM2708_DT
++ bool "BCM2708 Device Tree support"
++ depends on MACH_BCM2708
++ default n
++ select USE_OF
++ select ARCH_REQUIRE_GPIOLIB
++ select PINCTRL
++ select PINCTRL_BCM2835
++ help
++ Enable Device Tree support for BCM2708
++
++config BCM2708_GPIO
++ bool "BCM2708 gpio support"
++ depends on MACH_BCM2708
++ select ARCH_REQUIRE_GPIOLIB
++ default y
++ help
++ Include support for the Broadcom(R) BCM2708 gpio.
++
++config BCM2708_NOL2CACHE
++ bool "Videocore L2 cache disable"
++ depends on MACH_BCM2708
++ default n
++ help
++ Do not allow ARM to use GPU's L2 cache. Requires disable_l2cache in config.txt.
++
++config BCM2708_SPIDEV
++ bool "Bind spidev to SPI0 master"
++ depends on MACH_BCM2708
++ depends on SPI
++ default y
++ help
++ Binds spidev driver to the SPI0 master
++endmenu
+diff -Nur linux-4.1.3/arch/arm/mach-bcm2708/Makefile linux-xbian-rpi/arch/arm/mach-bcm2708/Makefile
+--- linux-4.1.3/arch/arm/mach-bcm2708/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/mach-bcm2708/Makefile 2015-07-28 01:20:58.170137709 +0200
+@@ -0,0 +1,6 @@
++#
++# Makefile for the linux kernel.
++#
++
++obj-$(CONFIG_MACH_BCM2708) += bcm2708.o armctrl.o
++obj-$(CONFIG_BCM2708_GPIO) += bcm2708_gpio.o
+diff -Nur linux-4.1.3/arch/arm/mach-bcm2708/Makefile.boot linux-xbian-rpi/arch/arm/mach-bcm2708/Makefile.boot
+--- linux-4.1.3/arch/arm/mach-bcm2708/Makefile.boot 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/mach-bcm2708/Makefile.boot 2015-07-28 01:20:58.170137709 +0200
+@@ -0,0 +1,3 @@
++ zreladdr-y := 0x00008000
++params_phys-y := 0x00000100
++initrd_phys-y := 0x00800000
+diff -Nur linux-4.1.3/arch/arm/mach-bcm2709/armctrl.c linux-xbian-rpi/arch/arm/mach-bcm2709/armctrl.c
+--- linux-4.1.3/arch/arm/mach-bcm2709/armctrl.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/mach-bcm2709/armctrl.c 2015-07-28 01:20:58.170137709 +0200
+@@ -0,0 +1,384 @@
++/*
++ * linux/arch/arm/mach-bcm2708/armctrl.c
++ *
++ * Copyright (C) 2010 Broadcom
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++#include <linux/init.h>
++#include <linux/list.h>
++#include <linux/io.h>
++#include <linux/version.h>
++#include <linux/syscore_ops.h>
++#include <linux/interrupt.h>
++#include <linux/irqdomain.h>
++#include <linux/of.h>
++
++#include <asm/mach/irq.h>
++#include <mach/hardware.h>
++#include "armctrl.h"
++
++/* For support of kernels >= 3.0 assume only one VIC for now*/
++static unsigned int remap_irqs[(INTERRUPT_ARASANSDIO + 1) - INTERRUPT_JPEG] = {
++ INTERRUPT_VC_JPEG,
++ INTERRUPT_VC_USB,
++ INTERRUPT_VC_3D,
++ INTERRUPT_VC_DMA2,
++ INTERRUPT_VC_DMA3,
++ INTERRUPT_VC_I2C,
++ INTERRUPT_VC_SPI,
++ INTERRUPT_VC_I2SPCM,
++ INTERRUPT_VC_SDIO,
++ INTERRUPT_VC_UART,
++ INTERRUPT_VC_ARASANSDIO
++};
++
++extern unsigned force_core;
++
++static void armctrl_mask_irq(struct irq_data *d)
++{
++ static const unsigned int disables[4] = {
++ ARM_IRQ_DIBL1,
++ ARM_IRQ_DIBL2,
++ ARM_IRQ_DIBL3,
++ 0
++ };
++ int i;
++ if (d->irq >= FIQ_START) {
++ writel(0, __io_address(ARM_IRQ_FAST));
++ } else if (d->irq >= IRQ_ARM_LOCAL_CNTPSIRQ && d->irq < IRQ_ARM_LOCAL_CNTPSIRQ + 4) {
++#if 1
++ unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - IRQ_ARM_LOCAL_CNTPSIRQ;
++ for (i=0; i<4; i++) // i = raw_smp_processor_id(); //
++ {
++ unsigned int val = readl(__io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 4*i));
++ writel(val &~ (1 << data), __io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 4*i));
++ }
++#endif
++ } else if (d->irq >= IRQ_ARM_LOCAL_MAILBOX0 && d->irq < IRQ_ARM_LOCAL_MAILBOX0 + 4) {
++#if 0
++ unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - IRQ_ARM_LOCAL_MAILBOX0;
++ for (i=0; i<4; i++) {
++ unsigned int val = readl(__io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 4*i));
++ writel(val &~ (1 << data), __io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 4*i));
++ }
++#endif
++ } else if (d->irq >= ARM_IRQ1_BASE && d->irq < ARM_IRQ_LOCAL_BASE) {
++ unsigned int data = (unsigned int)irq_get_chip_data(d->irq);
++ writel(1 << (data & 0x1f), __io_address(disables[(data >> 5) & 0x3]));
++ } else if (d->irq == INTERRUPT_ARM_LOCAL_PMU_FAST) {
++ writel(0xf, __io_address(ARM_LOCAL_PM_ROUTING_CLR));
++ } else { printk("%s: %d\n", __func__, d->irq); BUG(); }
++}
++
++static void armctrl_unmask_irq(struct irq_data *d)
++{
++ static const unsigned int enables[4] = {
++ ARM_IRQ_ENBL1,
++ ARM_IRQ_ENBL2,
++ ARM_IRQ_ENBL3,
++ 0
++ };
++ int i;
++ if (d->irq >= FIQ_START) {
++ unsigned int data;
++ if (force_core) {
++ data = readl(__io_address(ARM_LOCAL_GPU_INT_ROUTING));
++ data &= ~0xc;
++ data |= ((force_core-1) << 2);
++ writel(data, __io_address(ARM_LOCAL_GPU_INT_ROUTING));
++ }
++ else if (num_online_cpus() > 1) {
++ data = readl(__io_address(ARM_LOCAL_GPU_INT_ROUTING));
++ data &= ~0xc;
++ data |= (1 << 2);
++ writel(data, __io_address(ARM_LOCAL_GPU_INT_ROUTING));
++ }
++ /* Unmask in ARMCTRL block after routing it properly */
++ data = (unsigned int)irq_get_chip_data(d->irq) - FIQ_START;
++ writel(0x80 | data, __io_address(ARM_IRQ_FAST));
++ } else if (d->irq >= IRQ_ARM_LOCAL_CNTPSIRQ && d->irq < IRQ_ARM_LOCAL_CNTPSIRQ + 4) {
++#if 1
++ unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - IRQ_ARM_LOCAL_CNTPSIRQ;
++ for (i=0; i<4; i++) // i = raw_smp_processor_id();
++ {
++ unsigned int val = readl(__io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 4*i));
++ writel(val | (1 << data), __io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 4*i));
++ }
++#endif
++ } else if (d->irq >= IRQ_ARM_LOCAL_MAILBOX0 && d->irq < IRQ_ARM_LOCAL_MAILBOX0 + 4) {
++#if 0
++ unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - IRQ_ARM_LOCAL_MAILBOX0;
++ for (i=0; i<4; i++) {
++ unsigned int val = readl(__io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 4*i));
++ writel(val | (1 << data), __io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 4*i));
++ }
++#endif
++ } else if (d->irq >= ARM_IRQ1_BASE && d->irq < ARM_IRQ_LOCAL_BASE) {
++ if (force_core) {
++ unsigned int data;
++ data = readl(__io_address(ARM_LOCAL_GPU_INT_ROUTING));
++ data &= ~0x3;
++ data |= ((force_core-1) << 0);
++ writel(data, __io_address(ARM_LOCAL_GPU_INT_ROUTING));
++ }
++ unsigned int data = (unsigned int)irq_get_chip_data(d->irq);
++ writel(1 << (data & 0x1f), __io_address(enables[(data >> 5) & 0x3]));
++ } else if (d->irq == INTERRUPT_ARM_LOCAL_PMU_FAST) {
++ writel(0xf, __io_address(ARM_LOCAL_PM_ROUTING_SET));
++ } else { printk("%s: %d\n", __func__, d->irq); BUG(); }
++}
++
++#ifdef CONFIG_OF
++
++#define NR_IRQS_BANK0 21
++#define NR_BANKS 4
++#define IRQS_PER_BANK 32
++
++/* from drivers/irqchip/irq-bcm2835.c */
++static int armctrl_xlate(struct irq_domain *d, struct device_node *ctrlr,
++ const u32 *intspec, unsigned int intsize,
++ unsigned long *out_hwirq, unsigned int *out_type)
++{
++ if (WARN_ON(intsize != 2))
++ return -EINVAL;
++
++ if (WARN_ON(intspec[0] >= NR_BANKS))
++ return -EINVAL;
++
++ if (WARN_ON(intspec[1] >= IRQS_PER_BANK))
++ return -EINVAL;
++
++ if (WARN_ON(intspec[0] == 0 && intspec[1] >= NR_IRQS_BANK0))
++ return -EINVAL;
++
++ if (WARN_ON(intspec[0] == 3 && intspec[1] > 3 && intspec[1] != 5 && intspec[1] != 9))
++ return -EINVAL;
++
++ if (intspec[0] == 0)
++ *out_hwirq = ARM_IRQ0_BASE + intspec[1];
++ else if (intspec[0] == 1)
++ *out_hwirq = ARM_IRQ1_BASE + intspec[1];
++ else if (intspec[0] == 2)
++ *out_hwirq = ARM_IRQ2_BASE + intspec[1];
++ else
++ *out_hwirq = ARM_IRQ_LOCAL_BASE + intspec[1];
++
++ /* reverse remap_irqs[] */
++ switch (*out_hwirq) {
++ case INTERRUPT_VC_JPEG:
++ *out_hwirq = INTERRUPT_JPEG;
++ break;
++ case INTERRUPT_VC_USB:
++ *out_hwirq = INTERRUPT_USB;
++ break;
++ case INTERRUPT_VC_3D:
++ *out_hwirq = INTERRUPT_3D;
++ break;
++ case INTERRUPT_VC_DMA2:
++ *out_hwirq = INTERRUPT_DMA2;
++ break;
++ case INTERRUPT_VC_DMA3:
++ *out_hwirq = INTERRUPT_DMA3;
++ break;
++ case INTERRUPT_VC_I2C:
++ *out_hwirq = INTERRUPT_I2C;
++ break;
++ case INTERRUPT_VC_SPI:
++ *out_hwirq = INTERRUPT_SPI;
++ break;
++ case INTERRUPT_VC_I2SPCM:
++ *out_hwirq = INTERRUPT_I2SPCM;
++ break;
++ case INTERRUPT_VC_SDIO:
++ *out_hwirq = INTERRUPT_SDIO;
++ break;
++ case INTERRUPT_VC_UART:
++ *out_hwirq = INTERRUPT_UART;
++ break;
++ case INTERRUPT_VC_ARASANSDIO:
++ *out_hwirq = INTERRUPT_ARASANSDIO;
++ break;
++ }
++
++ *out_type = IRQ_TYPE_NONE;
++ return 0;
++}
++
++static struct irq_domain_ops armctrl_ops = {
++ .xlate = armctrl_xlate
++};
++
++void __init armctrl_dt_init(void)
++{
++ struct device_node *np;
++ struct irq_domain *domain;
++
++ np = of_find_compatible_node(NULL, NULL, "brcm,bcm2708-armctrl-ic");
++ if (!np)
++ return;
++
++ domain = irq_domain_add_legacy(np, BCM2708_ALLOC_IRQS,
++ IRQ_ARMCTRL_START, 0,
++ &armctrl_ops, NULL);
++ WARN_ON(!domain);
++}
++#else
++void __init armctrl_dt_init(void) { }
++#endif /* CONFIG_OF */
++
++#if defined(CONFIG_PM)
++
++/* for kernels 3.xx use the new syscore_ops apis but for older kernels use the sys dev class */
++
++/* Static defines
++ * struct armctrl_device - VIC PM device (< 3.xx)
++ * @sysdev: The system device which is registered. (< 3.xx)
++ * @irq: The IRQ number for the base of the VIC.
++ * @base: The register base for the VIC.
++ * @resume_sources: A bitmask of interrupts for resume.
++ * @resume_irqs: The IRQs enabled for resume.
++ * @int_select: Save for VIC_INT_SELECT.
++ * @int_enable: Save for VIC_INT_ENABLE.
++ * @soft_int: Save for VIC_INT_SOFT.
++ * @protect: Save for VIC_PROTECT.
++ */
++struct armctrl_info {
++ void __iomem *base;
++ int irq;
++ u32 resume_sources;
++ u32 resume_irqs;
++ u32 int_select;
++ u32 int_enable;
++ u32 soft_int;
++ u32 protect;
++} armctrl;
++
++static int armctrl_suspend(void)
++{
++ return 0;
++}
++
++static void armctrl_resume(void)
++{
++ return;
++}
++
++/**
++ * armctrl_pm_register - Register a VIC for later power management control
++ * @base: The base address of the VIC.
++ * @irq: The base IRQ for the VIC.
++ * @resume_sources: bitmask of interrupts allowed for resume sources.
++ *
++ * For older kernels (< 3.xx) do -
++ * Register the VIC with the system device tree so that it can be notified
++ * of suspend and resume requests and ensure that the correct actions are
++ * taken to re-instate the settings on resume.
++ */
++static void __init armctrl_pm_register(void __iomem * base, unsigned int irq,
++ u32 resume_sources)
++{
++ armctrl.base = base;
++ armctrl.resume_sources = resume_sources;
++ armctrl.irq = irq;
++}
++
++static int armctrl_set_wake(struct irq_data *d, unsigned int on)
++{
++ unsigned int off = d->irq & 31;
++ u32 bit = 1 << off;
++
++ if (!(bit & armctrl.resume_sources))
++ return -EINVAL;
++
++ if (on)
++ armctrl.resume_irqs |= bit;
++ else
++ armctrl.resume_irqs &= ~bit;
++
++ return 0;
++}
++
++#else
++static inline void armctrl_pm_register(void __iomem * base, unsigned int irq,
++ u32 arg1)
++{
++}
++
++#define armctrl_suspend NULL
++#define armctrl_resume NULL
++#define armctrl_set_wake NULL
++#endif /* CONFIG_PM */
++
++static struct syscore_ops armctrl_syscore_ops = {
++ .suspend = armctrl_suspend,
++ .resume = armctrl_resume,
++};
++
++/**
++ * armctrl_syscore_init - initicall to register VIC pm functions
++ *
++ * This is called via late_initcall() to register
++ * the resources for the VICs due to the early
++ * nature of the VIC's registration.
++*/
++static int __init armctrl_syscore_init(void)
++{
++ register_syscore_ops(&armctrl_syscore_ops);
++ return 0;
++}
++
++late_initcall(armctrl_syscore_init);
++
++static struct irq_chip armctrl_chip = {
++ .name = "ARMCTRL",
++ .irq_ack = NULL,
++ .irq_mask = armctrl_mask_irq,
++ .irq_unmask = armctrl_unmask_irq,
++ .irq_set_wake = armctrl_set_wake,
++};
++
++/**
++ * armctrl_init - initialise a vectored interrupt controller
++ * @base: iomem base address
++ * @irq_start: starting interrupt number, must be muliple of 32
++ * @armctrl_sources: bitmask of interrupt sources to allow
++ * @resume_sources: bitmask of interrupt sources to allow for resume
++ */
++int __init armctrl_init(void __iomem * base, unsigned int irq_start,
++ u32 armctrl_sources, u32 resume_sources)
++{
++ unsigned int irq;
++
++ for (irq = 0; irq < BCM2708_ALLOC_IRQS; irq++) {
++ unsigned int data = irq;
++ if (irq >= INTERRUPT_JPEG && irq <= INTERRUPT_ARASANSDIO)
++ data = remap_irqs[irq - INTERRUPT_JPEG];
++ if (irq >= IRQ_ARM_LOCAL_CNTPSIRQ && irq <= IRQ_ARM_LOCAL_TIMER) {
++ irq_set_percpu_devid(irq);
++ irq_set_chip_and_handler(irq, &armctrl_chip, handle_percpu_devid_irq);
++ set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN);
++ } else {
++ irq_set_chip_and_handler(irq, &armctrl_chip, handle_level_irq);
++ set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
++ }
++ irq_set_chip_data(irq, (void *)data);
++ }
++
++ armctrl_pm_register(base, irq_start, resume_sources);
++ init_FIQ(FIQ_START);
++ armctrl_dt_init();
++ return 0;
++}
+diff -Nur linux-4.1.3/arch/arm/mach-bcm2709/armctrl.h linux-xbian-rpi/arch/arm/mach-bcm2709/armctrl.h
+--- linux-4.1.3/arch/arm/mach-bcm2709/armctrl.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/mach-bcm2709/armctrl.h 2015-07-28 01:20:58.174123488 +0200
+@@ -0,0 +1,27 @@
++/*
++ * linux/arch/arm/mach-bcm2708/armctrl.h
++ *
++ * Copyright (C) 2010 Broadcom
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++
++#ifndef __BCM2708_ARMCTRL_H
++#define __BCM2708_ARMCTRL_H
++
++extern int __init armctrl_init(void __iomem * base, unsigned int irq_start,
++ u32 armctrl_sources, u32 resume_sources);
++
++#endif
+diff -Nur linux-4.1.3/arch/arm/mach-bcm2709/bcm2708_gpio.c linux-xbian-rpi/arch/arm/mach-bcm2709/bcm2708_gpio.c
+--- linux-4.1.3/arch/arm/mach-bcm2709/bcm2708_gpio.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/mach-bcm2709/bcm2708_gpio.c 2015-07-28 01:20:58.174123488 +0200
+@@ -0,0 +1,426 @@
++/*
++ * linux/arch/arm/mach-bcm2708/bcm2708_gpio.c
++ *
++ * Copyright (C) 2010 Broadcom
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#include <linux/spinlock.h>
++#include <linux/module.h>
++#include <linux/delay.h>
++#include <linux/list.h>
++#include <linux/io.h>
++#include <linux/irq.h>
++#include <linux/interrupt.h>
++#include <linux/slab.h>
++#include <mach/gpio.h>
++#include <linux/gpio.h>
++#include <linux/platform_device.h>
++#include <mach/platform.h>
++#include <linux/pinctrl/consumer.h>
++
++#include <linux/platform_data/bcm2708.h>
++
++#define BCM_GPIO_DRIVER_NAME "bcm2708_gpio"
++#define DRIVER_NAME BCM_GPIO_DRIVER_NAME
++#define BCM_GPIO_USE_IRQ 1
++
++#define GPIOFSEL(x) (0x00+(x)*4)
++#define GPIOSET(x) (0x1c+(x)*4)
++#define GPIOCLR(x) (0x28+(x)*4)
++#define GPIOLEV(x) (0x34+(x)*4)
++#define GPIOEDS(x) (0x40+(x)*4)
++#define GPIOREN(x) (0x4c+(x)*4)
++#define GPIOFEN(x) (0x58+(x)*4)
++#define GPIOHEN(x) (0x64+(x)*4)
++#define GPIOLEN(x) (0x70+(x)*4)
++#define GPIOAREN(x) (0x7c+(x)*4)
++#define GPIOAFEN(x) (0x88+(x)*4)
++#define GPIOUD(x) (0x94+(x)*4)
++#define GPIOUDCLK(x) (0x98+(x)*4)
++
++#define GPIO_BANKS 2
++
++enum { GPIO_FSEL_INPUT, GPIO_FSEL_OUTPUT,
++ GPIO_FSEL_ALT5, GPIO_FSEL_ALT_4,
++ GPIO_FSEL_ALT0, GPIO_FSEL_ALT1,
++ GPIO_FSEL_ALT2, GPIO_FSEL_ALT3,
++};
++
++ /* Each of the two spinlocks protects a different set of hardware
++ * regiters and data structurs. This decouples the code of the IRQ from
++ * the GPIO code. This also makes the case of a GPIO routine call from
++ * the IRQ code simpler.
++ */
++static DEFINE_SPINLOCK(lock); /* GPIO registers */
++
++struct bcm2708_gpio {
++ struct list_head list;
++ void __iomem *base;
++ struct gpio_chip gc;
++ unsigned long rising[(BCM2708_NR_GPIOS + 31) / 32];
++ unsigned long falling[(BCM2708_NR_GPIOS + 31) / 32];
++ unsigned long high[(BCM2708_NR_GPIOS + 31) / 32];
++ unsigned long low[(BCM2708_NR_GPIOS + 31) / 32];
++};
++
++static int bcm2708_set_function(struct gpio_chip *gc, unsigned offset,
++ int function)
++{
++ struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc);
++ unsigned long flags;
++ unsigned gpiodir;
++ unsigned gpio_bank = offset / 10;
++ unsigned gpio_field_offset = (offset - 10 * gpio_bank) * 3;
++
++//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_set_function %p (%d,%d)\n", gc, offset, function);
++ if (offset >= BCM2708_NR_GPIOS)
++ return -EINVAL;
++
++ spin_lock_irqsave(&lock, flags);
++
++ gpiodir = readl(gpio->base + GPIOFSEL(gpio_bank));
++ gpiodir &= ~(7 << gpio_field_offset);
++ gpiodir |= function << gpio_field_offset;
++ writel(gpiodir, gpio->base + GPIOFSEL(gpio_bank));
++ spin_unlock_irqrestore(&lock, flags);
++ gpiodir = readl(gpio->base + GPIOFSEL(gpio_bank));
++
++ return 0;
++}
++
++static int bcm2708_gpio_dir_in(struct gpio_chip *gc, unsigned offset)
++{
++ return bcm2708_set_function(gc, offset, GPIO_FSEL_INPUT);
++}
++
++static void bcm2708_gpio_set(struct gpio_chip *gc, unsigned offset, int value);
++static int bcm2708_gpio_dir_out(struct gpio_chip *gc, unsigned offset,
++ int value)
++{
++ int ret;
++ ret = bcm2708_set_function(gc, offset, GPIO_FSEL_OUTPUT);
++ if (ret >= 0)
++ bcm2708_gpio_set(gc, offset, value);
++ return ret;
++}
++
++static int bcm2708_gpio_get(struct gpio_chip *gc, unsigned offset)
++{
++ struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc);
++ unsigned gpio_bank = offset / 32;
++ unsigned gpio_field_offset = (offset - 32 * gpio_bank);
++ unsigned lev;
++
++ if (offset >= BCM2708_NR_GPIOS)
++ return 0;
++ lev = readl(gpio->base + GPIOLEV(gpio_bank));
++//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_get %p (%d)=%d\n", gc, offset, 0x1 & (lev>>gpio_field_offset));
++ return 0x1 & (lev >> gpio_field_offset);
++}
++
++static void bcm2708_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
++{
++ struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc);
++ unsigned gpio_bank = offset / 32;
++ unsigned gpio_field_offset = (offset - 32 * gpio_bank);
++//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_set %p (%d=%d)\n", gc, offset, value);
++ if (offset >= BCM2708_NR_GPIOS)
++ return;
++ if (value)
++ writel(1 << gpio_field_offset, gpio->base + GPIOSET(gpio_bank));
++ else
++ writel(1 << gpio_field_offset, gpio->base + GPIOCLR(gpio_bank));
++}
++
++/**********************
++ * extension to configure pullups
++ */
++int bcm2708_gpio_setpull(struct gpio_chip *gc, unsigned offset,
++ bcm2708_gpio_pull_t value)
++{
++ struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc);
++ unsigned gpio_bank = offset / 32;
++ unsigned gpio_field_offset = (offset - 32 * gpio_bank);
++
++ if (offset >= BCM2708_NR_GPIOS)
++ return -EINVAL;
++
++ switch (value) {
++ case BCM2708_PULL_UP:
++ writel(2, gpio->base + GPIOUD(0));
++ break;
++ case BCM2708_PULL_DOWN:
++ writel(1, gpio->base + GPIOUD(0));
++ break;
++ case BCM2708_PULL_OFF:
++ writel(0, gpio->base + GPIOUD(0));
++ break;
++ }
++
++ udelay(5);
++ writel(1 << gpio_field_offset, gpio->base + GPIOUDCLK(gpio_bank));
++ udelay(5);
++ writel(0, gpio->base + GPIOUD(0));
++ writel(0 << gpio_field_offset, gpio->base + GPIOUDCLK(gpio_bank));
++
++ return 0;
++}
++EXPORT_SYMBOL(bcm2708_gpio_setpull);
++
++/*************************************************************************************************************************
++ * bcm2708 GPIO IRQ
++ */
++
++#if BCM_GPIO_USE_IRQ
++
++static int bcm2708_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
++{
++ return gpio_to_irq(gpio);
++}
++
++static int bcm2708_gpio_irq_set_type(struct irq_data *d, unsigned type)
++{
++ unsigned irq = d->irq;
++ struct bcm2708_gpio *gpio = irq_get_chip_data(irq);
++ unsigned gn = irq_to_gpio(irq);
++ unsigned gb = gn / 32;
++ unsigned go = gn % 32;
++
++ gpio->rising[gb] &= ~(1 << go);
++ gpio->falling[gb] &= ~(1 << go);
++ gpio->high[gb] &= ~(1 << go);
++ gpio->low[gb] &= ~(1 << go);
++
++ if (type & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
++ return -EINVAL;
++
++ if (type & IRQ_TYPE_EDGE_RISING)
++ gpio->rising[gb] |= (1 << go);
++ if (type & IRQ_TYPE_EDGE_FALLING)
++ gpio->falling[gb] |= (1 << go);
++ if (type & IRQ_TYPE_LEVEL_HIGH)
++ gpio->high[gb] |= (1 << go);
++ if (type & IRQ_TYPE_LEVEL_LOW)
++ gpio->low[gb] |= (1 << go);
++ return 0;
++}
++
++static void bcm2708_gpio_irq_mask(struct irq_data *d)
++{
++ unsigned irq = d->irq;
++ struct bcm2708_gpio *gpio = irq_get_chip_data(irq);
++ unsigned gn = irq_to_gpio(irq);
++ unsigned gb = gn / 32;
++ unsigned long rising = readl(gpio->base + GPIOREN(gb));
++ unsigned long falling = readl(gpio->base + GPIOFEN(gb));
++ unsigned long high = readl(gpio->base + GPIOHEN(gb));
++ unsigned long low = readl(gpio->base + GPIOLEN(gb));
++
++ gn = gn % 32;
++
++ writel(rising & ~(1 << gn), gpio->base + GPIOREN(gb));
++ writel(falling & ~(1 << gn), gpio->base + GPIOFEN(gb));
++ writel(high & ~(1 << gn), gpio->base + GPIOHEN(gb));
++ writel(low & ~(1 << gn), gpio->base + GPIOLEN(gb));
++}
++
++static void bcm2708_gpio_irq_unmask(struct irq_data *d)
++{
++ unsigned irq = d->irq;
++ struct bcm2708_gpio *gpio = irq_get_chip_data(irq);
++ unsigned gn = irq_to_gpio(irq);
++ unsigned gb = gn / 32;
++ unsigned go = gn % 32;
++ unsigned long rising = readl(gpio->base + GPIOREN(gb));
++ unsigned long falling = readl(gpio->base + GPIOFEN(gb));
++ unsigned long high = readl(gpio->base + GPIOHEN(gb));
++ unsigned long low = readl(gpio->base + GPIOLEN(gb));
++
++ if (gpio->rising[gb] & (1 << go)) {
++ writel(rising | (1 << go), gpio->base + GPIOREN(gb));
++ } else {
++ writel(rising & ~(1 << go), gpio->base + GPIOREN(gb));
++ }
++
++ if (gpio->falling[gb] & (1 << go)) {
++ writel(falling | (1 << go), gpio->base + GPIOFEN(gb));
++ } else {
++ writel(falling & ~(1 << go), gpio->base + GPIOFEN(gb));
++ }
++
++ if (gpio->high[gb] & (1 << go)) {
++ writel(high | (1 << go), gpio->base + GPIOHEN(gb));
++ } else {
++ writel(high & ~(1 << go), gpio->base + GPIOHEN(gb));
++ }
++
++ if (gpio->low[gb] & (1 << go)) {
++ writel(low | (1 << go), gpio->base + GPIOLEN(gb));
++ } else {
++ writel(low & ~(1 << go), gpio->base + GPIOLEN(gb));
++ }
++}
++
++static struct irq_chip bcm2708_irqchip = {
++ .name = "GPIO",
++ .irq_enable = bcm2708_gpio_irq_unmask,
++ .irq_disable = bcm2708_gpio_irq_mask,
++ .irq_unmask = bcm2708_gpio_irq_unmask,
++ .irq_mask = bcm2708_gpio_irq_mask,
++ .irq_set_type = bcm2708_gpio_irq_set_type,
++};
++
++static irqreturn_t bcm2708_gpio_interrupt(int irq, void *dev_id)
++{
++ unsigned long edsr;
++ unsigned bank;
++ int i;
++ unsigned gpio;
++ unsigned level_bits;
++ struct bcm2708_gpio *gpio_data = dev_id;
++
++ for (bank = 0; bank < GPIO_BANKS; bank++) {
++ edsr = readl(__io_address(GPIO_BASE) + GPIOEDS(bank));
++ level_bits = gpio_data->high[bank] | gpio_data->low[bank];
++
++ for_each_set_bit(i, &edsr, 32) {
++ gpio = i + bank * 32;
++ /* ack edge triggered IRQs immediately */
++ if (!(level_bits & (1<<i)))
++ writel(1<<i,
++ __io_address(GPIO_BASE) + GPIOEDS(bank));
++ generic_handle_irq(gpio_to_irq(gpio));
++ /* ack level triggered IRQ after handling them */
++ if (level_bits & (1<<i))
++ writel(1<<i,
++ __io_address(GPIO_BASE) + GPIOEDS(bank));
++ }
++ }
++ return IRQ_HANDLED;
++}
++
++static struct irqaction bcm2708_gpio_irq = {
++ .name = "BCM2708 GPIO catchall handler",
++ .flags = IRQF_TIMER | IRQF_IRQPOLL,
++ .handler = bcm2708_gpio_interrupt,
++};
++
++static void bcm2708_gpio_irq_init(struct bcm2708_gpio *ucb)
++{
++ unsigned irq;
++
++ ucb->gc.to_irq = bcm2708_gpio_to_irq;
++
++ for (irq = GPIO_IRQ_START; irq < (GPIO_IRQ_START + GPIO_IRQS); irq++) {
++ irq_set_chip_data(irq, ucb);
++ irq_set_chip_and_handler(irq, &bcm2708_irqchip,
++ handle_simple_irq);
++ set_irq_flags(irq, IRQF_VALID);
++ }
++
++ bcm2708_gpio_irq.dev_id = ucb;
++ setup_irq(IRQ_GPIO3, &bcm2708_gpio_irq);
++}
++
++#else
++
++static void bcm2708_gpio_irq_init(struct bcm2708_gpio *ucb)
++{
++}
++
++#endif /* #if BCM_GPIO_USE_IRQ ***************************************************************************************************************** */
++
++static int bcm2708_gpio_probe(struct platform_device *dev)
++{
++ struct bcm2708_gpio *ucb;
++ struct resource *res;
++ int bank;
++ int err = 0;
++
++ printk(KERN_INFO DRIVER_NAME ": bcm2708_gpio_probe %p\n", dev);
++
++ ucb = kzalloc(sizeof(*ucb), GFP_KERNEL);
++ if (NULL == ucb) {
++ printk(KERN_ERR DRIVER_NAME ": failed to allocate "
++ "mailbox memory\n");
++ err = -ENOMEM;
++ goto err;
++ }
++
++ res = platform_get_resource(dev, IORESOURCE_MEM, 0);
++
++ platform_set_drvdata(dev, ucb);
++ ucb->base = __io_address(GPIO_BASE);
++
++ ucb->gc.label = "bcm2708_gpio";
++ ucb->gc.base = 0;
++ ucb->gc.ngpio = BCM2708_NR_GPIOS;
++ ucb->gc.owner = THIS_MODULE;
++
++ ucb->gc.direction_input = bcm2708_gpio_dir_in;
++ ucb->gc.direction_output = bcm2708_gpio_dir_out;
++ ucb->gc.get = bcm2708_gpio_get;
++ ucb->gc.set = bcm2708_gpio_set;
++ ucb->gc.can_sleep = 0;
++
++ for (bank = 0; bank < GPIO_BANKS; bank++) {
++ writel(0, ucb->base + GPIOREN(bank));
++ writel(0, ucb->base + GPIOFEN(bank));
++ writel(0, ucb->base + GPIOHEN(bank));
++ writel(0, ucb->base + GPIOLEN(bank));
++ writel(0, ucb->base + GPIOAREN(bank));
++ writel(0, ucb->base + GPIOAFEN(bank));
++ writel(~0, ucb->base + GPIOEDS(bank));
++ }
++
++ bcm2708_gpio_irq_init(ucb);
++
++ err = gpiochip_add(&ucb->gc);
++
++err:
++ return err;
++
++}
++
++static int bcm2708_gpio_remove(struct platform_device *dev)
++{
++ int err = 0;
++ struct bcm2708_gpio *ucb = platform_get_drvdata(dev);
++
++ printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_remove %p\n", dev);
++
++ gpiochip_remove(&ucb->gc);
++
++ platform_set_drvdata(dev, NULL);
++ kfree(ucb);
++
++ return err;
++}
++
++static struct platform_driver bcm2708_gpio_driver = {
++ .probe = bcm2708_gpio_probe,
++ .remove = bcm2708_gpio_remove,
++ .driver = {
++ .name = "bcm2708_gpio"},
++};
++
++static int __init bcm2708_gpio_init(void)
++{
++ return platform_driver_register(&bcm2708_gpio_driver);
++}
++
++static void __exit bcm2708_gpio_exit(void)
++{
++ platform_driver_unregister(&bcm2708_gpio_driver);
++}
++
++module_init(bcm2708_gpio_init);
++module_exit(bcm2708_gpio_exit);
++
++MODULE_DESCRIPTION("Broadcom BCM2708 GPIO driver");
++MODULE_LICENSE("GPL");
+diff -Nur linux-4.1.3/arch/arm/mach-bcm2709/bcm2709.c linux-xbian-rpi/arch/arm/mach-bcm2709/bcm2709.c
+--- linux-4.1.3/arch/arm/mach-bcm2709/bcm2709.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/mach-bcm2709/bcm2709.c 2015-07-28 01:20:58.174123488 +0200
+@@ -0,0 +1,1332 @@
++/*
++ * linux/arch/arm/mach-bcm2709/bcm2709.c
++ *
++ * Copyright (C) 2010 Broadcom
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++
++#include <linux/init.h>
++#include <linux/device.h>
++#include <linux/dma-mapping.h>
++#include <linux/serial_8250.h>
++#include <linux/platform_device.h>
++#include <linux/syscore_ops.h>
++#include <linux/interrupt.h>
++#include <linux/amba/bus.h>
++#include <linux/amba/clcd.h>
++#include <linux/clk-provider.h>
++#include <linux/clkdev.h>
++#include <linux/clockchips.h>
++#include <linux/cnt32_to_63.h>
++#include <linux/io.h>
++#include <linux/module.h>
++#include <linux/of_platform.h>
++#include <linux/spi/spi.h>
++#include <linux/gpio/machine.h>
++#include <linux/w1-gpio.h>
++#include <linux/pps-gpio.h>
++
++#include <linux/version.h>
++#include <linux/clkdev.h>
++#include <asm/system_info.h>
++#include <mach/hardware.h>
++#include <asm/irq.h>
++#include <linux/leds.h>
++#include <asm/mach-types.h>
++#include <asm/cputype.h>
++#include <linux/sched_clock.h>
++
++#include <asm/mach/arch.h>
++#include <asm/mach/flash.h>
++#include <asm/mach/irq.h>
++#include <asm/mach/time.h>
++#include <asm/mach/map.h>
++
++#include <mach/timex.h>
++#include <mach/system.h>
++
++#include <linux/delay.h>
++
++#include "bcm2709.h"
++#include "armctrl.h"
++
++#ifdef CONFIG_BCM_VC_CMA
++#include <linux/broadcom/vc_cma.h>
++#endif
++
++//#define SYSTEM_TIMER
++
++/* Effectively we have an IOMMU (ARM<->VideoCore map) that is set up to
++ * give us IO access only to 64Mbytes of physical memory (26 bits). We could
++ * represent this window by setting our dmamasks to 26 bits but, in fact
++ * we're not going to use addresses outside this range (they're not in real
++ * memory) so we don't bother.
++ *
++ * In the future we might include code to use this IOMMU to remap other
++ * physical addresses onto VideoCore memory then the use of 32-bits would be
++ * more legitimate.
++ */
++#define DMA_MASK_BITS_COMMON 32
++
++// use GPIO 4 for the one-wire GPIO pin, if enabled
++#define W1_GPIO 4
++// ensure one-wire GPIO pullup is disabled by default
++#define W1_PULLUP -1
++
++/* command line parameters */
++static unsigned boardrev, serial;
++static unsigned uart_clock = UART0_CLOCK;
++static unsigned disk_led_gpio = 16;
++static unsigned disk_led_active_low = 1;
++static unsigned reboot_part = 0;
++static unsigned w1_gpio_pin = W1_GPIO;
++static unsigned w1_gpio_pullup = W1_PULLUP;
++static bool vc_i2c_override = false;
++static int pps_gpio_pin = -1;
++unsigned force_core;
++
++static unsigned use_dt = 0;
++
++static void __init bcm2709_init_led(void);
++
++void __init bcm2709_init_irq(void)
++{
++ armctrl_init(__io_address(ARMCTRL_IC_BASE), 0, 0, 0);
++}
++
++static struct map_desc bcm2709_io_desc[] __initdata = {
++ {
++ .virtual = IO_ADDRESS(ARMCTRL_BASE),
++ .pfn = __phys_to_pfn(ARMCTRL_BASE),
++ .length = SZ_4K,
++ .type = MT_DEVICE},
++ {
++ .virtual = IO_ADDRESS(UART0_BASE),
++ .pfn = __phys_to_pfn(UART0_BASE),
++ .length = SZ_4K,
++ .type = MT_DEVICE},
++ {
++ .virtual = IO_ADDRESS(UART1_BASE),
++ .pfn = __phys_to_pfn(UART1_BASE),
++ .length = SZ_4K,
++ .type = MT_DEVICE},
++ {
++ .virtual = IO_ADDRESS(DMA_BASE),
++ .pfn = __phys_to_pfn(DMA_BASE),
++ .length = SZ_4K,
++ .type = MT_DEVICE},
++ {
++ .virtual = IO_ADDRESS(MCORE_BASE),
++ .pfn = __phys_to_pfn(MCORE_BASE),
++ .length = SZ_4K,
++ .type = MT_DEVICE},
++ {
++ .virtual = IO_ADDRESS(ST_BASE),
++ .pfn = __phys_to_pfn(ST_BASE),
++ .length = SZ_4K,
++ .type = MT_DEVICE},
++ {
++ .virtual = IO_ADDRESS(USB_BASE),
++ .pfn = __phys_to_pfn(USB_BASE),
++ .length = SZ_128K,
++ .type = MT_DEVICE},
++ {
++ .virtual = IO_ADDRESS(PM_BASE),
++ .pfn = __phys_to_pfn(PM_BASE),
++ .length = SZ_4K,
++ .type = MT_DEVICE},
++ {
++ .virtual = IO_ADDRESS(GPIO_BASE),
++ .pfn = __phys_to_pfn(GPIO_BASE),
++ .length = SZ_4K,
++ .type = MT_DEVICE},
++ {
++ .virtual = IO_ADDRESS(ARM_LOCAL_BASE),
++ .pfn = __phys_to_pfn(ARM_LOCAL_BASE),
++ .length = SZ_4K,
++ .type = MT_DEVICE},
++};
++
++void __init bcm2709_map_io(void)
++{
++ iotable_init(bcm2709_io_desc, ARRAY_SIZE(bcm2709_io_desc));
++}
++
++#ifdef SYSTEM_TIMER
++
++/* The STC is a free running counter that increments at the rate of 1MHz */
++#define STC_FREQ_HZ 1000000
++
++static inline uint32_t timer_read(void)
++{
++ /* STC: a free running counter that increments at the rate of 1MHz */
++ return readl(__io_address(ST_BASE + 0x04));
++}
++
++static unsigned long bcm2709_read_current_timer(void)
++{
++ return timer_read();
++}
++
++static u64 notrace bcm2709_read_sched_clock(void)
++{
++ return timer_read();
++}
++
++static cycle_t clksrc_read(struct clocksource *cs)
++{
++ return timer_read();
++}
++
++static struct clocksource clocksource_stc = {
++ .name = "stc",
++ .rating = 300,
++ .read = clksrc_read,
++ .mask = CLOCKSOURCE_MASK(32),
++ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
++};
++
++unsigned long frc_clock_ticks32(void)
++{
++ return timer_read();
++}
++
++static void __init bcm2709_clocksource_init(void)
++{
++ if (clocksource_register_hz(&clocksource_stc, STC_FREQ_HZ)) {
++ printk(KERN_ERR "timer: failed to initialize clock "
++ "source %s\n", clocksource_stc.name);
++ }
++}
++#endif
++
++struct clk __init *bcm2709_clk_register(const char *name, unsigned long fixed_rate)
++{
++ struct clk *clk;
++
++ clk = clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT,
++ fixed_rate);
++ if (IS_ERR(clk))
++ pr_err("%s not registered\n", name);
++
++ return clk;
++}
++
++void __init bcm2709_register_clkdev(struct clk *clk, const char *name)
++{
++ int ret;
++
++ ret = clk_register_clkdev(clk, NULL, name);
++ if (ret)
++ pr_err("%s alias not registered\n", name);
++}
++
++void __init bcm2709_init_clocks(void)
++{
++ struct clk *clk;
++
++ clk = bcm2709_clk_register("uart0_clk", uart_clock);
++ bcm2709_register_clkdev(clk, "dev:f1");
++
++ clk = bcm2709_clk_register("sdhost_clk", 250000000);
++ bcm2709_register_clkdev(clk, "mmc-bcm2835.0");
++ bcm2709_register_clkdev(clk, "bcm2708_spi.0");
++ bcm2709_register_clkdev(clk, "bcm2708_i2c.0");
++ bcm2709_register_clkdev(clk, "bcm2708_i2c.1");
++}
++
++#define UART0_IRQ { IRQ_UART, 0 /*NO_IRQ*/ }
++#define UART0_DMA { 15, 14 }
++
++AMBA_DEVICE(uart0, "dev:f1", UART0, NULL);
++
++static struct amba_device *amba_devs[] __initdata = {
++ &uart0_device,
++};
++
++static struct resource bcm2708_dmaengine_resources[] = {
++ {
++ .start = DMA_BASE,
++ .end = DMA_BASE + SZ_4K - 1,
++ .flags = IORESOURCE_MEM,
++ }, {
++ .start = IRQ_DMA0,
++ .end = IRQ_DMA0,
++ .flags = IORESOURCE_IRQ,
++ }, {
++ .start = IRQ_DMA1,
++ .end = IRQ_DMA1,
++ .flags = IORESOURCE_IRQ,
++ }, {
++ .start = IRQ_DMA2,
++ .end = IRQ_DMA2,
++ .flags = IORESOURCE_IRQ,
++ }, {
++ .start = IRQ_DMA3,
++ .end = IRQ_DMA3,
++ .flags = IORESOURCE_IRQ,
++ }, {
++ .start = IRQ_DMA4,
++ .end = IRQ_DMA4,
++ .flags = IORESOURCE_IRQ,
++ }, {
++ .start = IRQ_DMA5,
++ .end = IRQ_DMA5,
++ .flags = IORESOURCE_IRQ,
++ }, {
++ .start = IRQ_DMA6,
++ .end = IRQ_DMA6,
++ .flags = IORESOURCE_IRQ,
++ }, {
++ .start = IRQ_DMA7,
++ .end = IRQ_DMA7,
++ .flags = IORESOURCE_IRQ,
++ }, {
++ .start = IRQ_DMA8,
++ .end = IRQ_DMA8,
++ .flags = IORESOURCE_IRQ,
++ }, {
++ .start = IRQ_DMA9,
++ .end = IRQ_DMA9,
++ .flags = IORESOURCE_IRQ,
++ }, {
++ .start = IRQ_DMA10,
++ .end = IRQ_DMA10,
++ .flags = IORESOURCE_IRQ,
++ }, {
++ .start = IRQ_DMA11,
++ .end = IRQ_DMA11,
++ .flags = IORESOURCE_IRQ,
++ }, {
++ .start = IRQ_DMA12,
++ .end = IRQ_DMA12,
++ .flags = IORESOURCE_IRQ,
++ }
++};
++
++static struct platform_device bcm2708_dmaengine_device = {
++ .name = "bcm2708-dmaengine",
++ .id = -1,
++ .resource = bcm2708_dmaengine_resources,
++ .num_resources = ARRAY_SIZE(bcm2708_dmaengine_resources),
++};
++
++#if defined(CONFIG_W1_MASTER_GPIO) || defined(CONFIG_W1_MASTER_GPIO_MODULE)
++static struct w1_gpio_platform_data w1_gpio_pdata = {
++ .pin = W1_GPIO,
++ .ext_pullup_enable_pin = W1_PULLUP,
++ .is_open_drain = 0,
++};
++
++static struct platform_device w1_device = {
++ .name = "w1-gpio",
++ .id = -1,
++ .dev.platform_data = &w1_gpio_pdata,
++};
++#endif
++
++static struct pps_gpio_platform_data pps_gpio_info = {
++ .assert_falling_edge = false,
++ .capture_clear = false,
++ .gpio_pin = -1,
++ .gpio_label = "PPS",
++};
++
++static struct platform_device pps_gpio_device = {
++ .name = "pps-gpio",
++ .id = PLATFORM_DEVID_NONE,
++ .dev.platform_data = &pps_gpio_info,
++};
++
++static u64 fb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
++
++static struct platform_device bcm2708_fb_device = {
++ .name = "bcm2708_fb",
++ .id = -1, /* only one bcm2708_fb */
++ .resource = NULL,
++ .num_resources = 0,
++ .dev = {
++ .dma_mask = &fb_dmamask,
++ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
++ },
++};
++
++static struct resource bcm2708_usb_resources[] = {
++ [0] = {
++ .start = USB_BASE,
++ .end = USB_BASE + SZ_128K - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = MPHI_BASE,
++ .end = MPHI_BASE + SZ_4K - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [2] = {
++ .start = IRQ_HOSTPORT,
++ .end = IRQ_HOSTPORT,
++ .flags = IORESOURCE_IRQ,
++ },
++ [3] = {
++ .start = IRQ_USB,
++ .end = IRQ_USB,
++ .flags = IORESOURCE_IRQ,
++ },
++ [4] = {
++ .start = ARM_LOCAL_BASE,
++ .end = ARM_LOCAL_BASE + SZ_4K - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [5] = {
++ .start = IRQ_ARM_LOCAL_MAILBOX1,
++ .end = IRQ_ARM_LOCAL_MAILBOX1,
++ .flags = IORESOURCE_IRQ
++ },
++};
++
++
++static u64 usb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
++
++static struct platform_device bcm2708_usb_device = {
++ .name = "bcm2708_usb",
++ .id = -1, /* only one bcm2708_usb */
++ .resource = bcm2708_usb_resources,
++ .num_resources = ARRAY_SIZE(bcm2708_usb_resources),
++ .dev = {
++ .dma_mask = &usb_dmamask,
++ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
++ },
++};
++
++static struct resource bcm2708_vcio_resources[] = {
++ {
++ .start = ARMCTRL_0_MAIL0_BASE,
++ .end = ARMCTRL_0_MAIL0_BASE + SZ_64 - 1,
++ .flags = IORESOURCE_MEM,
++ }, {
++ .start = IRQ_ARM_MAILBOX,
++ .end = IRQ_ARM_MAILBOX,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++static u64 vcio_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
++
++static struct platform_device bcm2708_vcio_device = {
++ .name = "bcm2835-mbox",
++ .id = -1, /* only one VideoCore I/O area */
++ .resource = bcm2708_vcio_resources,
++ .num_resources = ARRAY_SIZE(bcm2708_vcio_resources),
++ .dev = {
++ .dma_mask = &vcio_dmamask,
++ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
++ },
++};
++
++static u64 rpifw_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
++
++static struct platform_device bcm2708_rpifw_device = {
++ .name = "raspberrypi-firmware",
++ .dev = {
++ .dma_mask = &rpifw_dmamask,
++ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
++ },
++};
++
++static struct resource bcm2708_vchiq_resources[] = {
++ {
++ .start = ARMCTRL_0_BELL_BASE,
++ .end = ARMCTRL_0_BELL_BASE + 16,
++ .flags = IORESOURCE_MEM,
++ }, {
++ .start = IRQ_ARM_DOORBELL_0,
++ .end = IRQ_ARM_DOORBELL_0,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++static u64 vchiq_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
++
++static struct platform_device bcm2708_vchiq_device = {
++ .name = "bcm2835_vchiq",
++ .id = -1,
++ .resource = bcm2708_vchiq_resources,
++ .num_resources = ARRAY_SIZE(bcm2708_vchiq_resources),
++ .dev = {
++ .dma_mask = &vchiq_dmamask,
++ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
++ },
++};
++
++#ifdef CONFIG_BCM2708_GPIO
++#define BCM_GPIO_DRIVER_NAME "bcm2708_gpio"
++
++static struct resource bcm2708_gpio_resources[] = {
++ [0] = { /* general purpose I/O */
++ .start = GPIO_BASE,
++ .end = GPIO_BASE + SZ_4K - 1,
++ .flags = IORESOURCE_MEM,
++ },
++};
++
++static u64 gpio_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
++
++static struct platform_device bcm2708_gpio_device = {
++ .name = BCM_GPIO_DRIVER_NAME,
++ .id = -1, /* only one VideoCore I/O area */
++ .resource = bcm2708_gpio_resources,
++ .num_resources = ARRAY_SIZE(bcm2708_gpio_resources),
++ .dev = {
++ .dma_mask = &gpio_dmamask,
++ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
++ },
++};
++#endif
++
++#ifdef CONFIG_MMC_BCM2835 /* Arasan emmc SD (new) */
++static struct resource bcm2835_emmc_resources[] = {
++ [0] = {
++ .start = EMMC_BASE,
++ .end = EMMC_BASE + SZ_256 - 1, /* we only need this area */
++ /* the memory map actually makes SZ_4K available */
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = IRQ_ARASANSDIO,
++ .end = IRQ_ARASANSDIO,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++static u64 bcm2835_emmc_dmamask = 0xffffffffUL;
++
++struct platform_device bcm2835_emmc_device = {
++ .name = "mmc-bcm2835",
++ .id = 0,
++ .num_resources = ARRAY_SIZE(bcm2835_emmc_resources),
++ .resource = bcm2835_emmc_resources,
++ .dev = {
++ .dma_mask = &bcm2835_emmc_dmamask,
++ .coherent_dma_mask = 0xffffffffUL},
++};
++#endif /* CONFIG_MMC_BCM2835 */
++
++static struct platform_device bcm2708_alsa_devices[] = {
++ [0] = {
++ .name = "bcm2835_AUD0",
++ .id = 0, /* first audio device */
++ .resource = 0,
++ .num_resources = 0,
++ },
++ [1] = {
++ .name = "bcm2835_AUD1",
++ .id = 1, /* second audio device */
++ .resource = 0,
++ .num_resources = 0,
++ },
++ [2] = {
++ .name = "bcm2835_AUD2",
++ .id = 2, /* third audio device */
++ .resource = 0,
++ .num_resources = 0,
++ },
++ [3] = {
++ .name = "bcm2835_AUD3",
++ .id = 3, /* forth audio device */
++ .resource = 0,
++ .num_resources = 0,
++ },
++ [4] = {
++ .name = "bcm2835_AUD4",
++ .id = 4, /* fifth audio device */
++ .resource = 0,
++ .num_resources = 0,
++ },
++ [5] = {
++ .name = "bcm2835_AUD5",
++ .id = 5, /* sixth audio device */
++ .resource = 0,
++ .num_resources = 0,
++ },
++ [6] = {
++ .name = "bcm2835_AUD6",
++ .id = 6, /* seventh audio device */
++ .resource = 0,
++ .num_resources = 0,
++ },
++ [7] = {
++ .name = "bcm2835_AUD7",
++ .id = 7, /* eighth audio device */
++ .resource = 0,
++ .num_resources = 0,
++ },
++};
++
++static struct resource bcm2708_spi_resources[] = {
++ {
++ .start = SPI0_BASE,
++ .end = SPI0_BASE + SZ_256 - 1,
++ .flags = IORESOURCE_MEM,
++ }, {
++ .start = IRQ_SPI,
++ .end = IRQ_SPI,
++ .flags = IORESOURCE_IRQ,
++ }
++};
++
++
++static u64 bcm2708_spi_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
++static struct platform_device bcm2708_spi_device = {
++ .name = "bcm2708_spi",
++ .id = 0,
++ .num_resources = ARRAY_SIZE(bcm2708_spi_resources),
++ .resource = bcm2708_spi_resources,
++ .dev = {
++ .dma_mask = &bcm2708_spi_dmamask,
++ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON)},
++};
++
++#ifdef CONFIG_BCM2708_SPIDEV
++static struct spi_board_info bcm2708_spi_devices[] = {
++#ifdef CONFIG_SPI_SPIDEV
++ {
++ .modalias = "spidev",
++ .max_speed_hz = 500000,
++ .bus_num = 0,
++ .chip_select = 0,
++ .mode = SPI_MODE_0,
++ }, {
++ .modalias = "spidev",
++ .max_speed_hz = 500000,
++ .bus_num = 0,
++ .chip_select = 1,
++ .mode = SPI_MODE_0,
++ }
++#endif
++};
++#endif
++
++static struct resource bcm2708_bsc0_resources[] = {
++ {
++ .start = BSC0_BASE,
++ .end = BSC0_BASE + SZ_256 - 1,
++ .flags = IORESOURCE_MEM,
++ }, {
++ .start = INTERRUPT_I2C,
++ .end = INTERRUPT_I2C,
++ .flags = IORESOURCE_IRQ,
++ }
++};
++
++static struct platform_device bcm2708_bsc0_device = {
++ .name = "bcm2708_i2c",
++ .id = 0,
++ .num_resources = ARRAY_SIZE(bcm2708_bsc0_resources),
++ .resource = bcm2708_bsc0_resources,
++};
++
++
++static struct resource bcm2708_bsc1_resources[] = {
++ {
++ .start = BSC1_BASE,
++ .end = BSC1_BASE + SZ_256 - 1,
++ .flags = IORESOURCE_MEM,
++ }, {
++ .start = INTERRUPT_I2C,
++ .end = INTERRUPT_I2C,
++ .flags = IORESOURCE_IRQ,
++ }
++};
++
++static struct platform_device bcm2708_bsc1_device = {
++ .name = "bcm2708_i2c",
++ .id = 1,
++ .num_resources = ARRAY_SIZE(bcm2708_bsc1_resources),
++ .resource = bcm2708_bsc1_resources,
++};
++
++static struct platform_device bcm2835_thermal_device = {
++ .name = "bcm2835_thermal",
++};
++
++#if defined(CONFIG_SND_BCM2708_SOC_I2S) || defined(CONFIG_SND_BCM2708_SOC_I2S_MODULE)
++static struct resource bcm2708_i2s_resources[] = {
++ {
++ .start = I2S_BASE,
++ .end = I2S_BASE + 0x20,
++ .flags = IORESOURCE_MEM,
++ },
++ {
++ .start = PCM_CLOCK_BASE,
++ .end = PCM_CLOCK_BASE + 0x02,
++ .flags = IORESOURCE_MEM,
++ }
++};
++
++static struct platform_device bcm2708_i2s_device = {
++ .name = "bcm2708-i2s",
++ .id = 0,
++ .num_resources = ARRAY_SIZE(bcm2708_i2s_resources),
++ .resource = bcm2708_i2s_resources,
++};
++#endif
++
++#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC_MODULE)
++static struct platform_device snd_hifiberry_dac_device = {
++ .name = "snd-hifiberry-dac",
++ .id = 0,
++ .num_resources = 0,
++};
++
++static struct platform_device snd_pcm5102a_codec_device = {
++ .name = "pcm5102a-codec",
++ .id = -1,
++ .num_resources = 0,
++};
++#endif
++
++#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS_MODULE)
++static struct platform_device snd_rpi_hifiberry_dacplus_device = {
++ .name = "snd-rpi-hifiberry-dacplus",
++ .id = 0,
++ .num_resources = 0,
++};
++
++static struct i2c_board_info __initdata snd_pcm512x_hbdacplus_i2c_devices[] = {
++ {
++ I2C_BOARD_INFO("pcm5122", 0x4d)
++ },
++};
++#endif
++
++#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI_MODULE)
++static struct platform_device snd_hifiberry_digi_device = {
++ .name = "snd-hifiberry-digi",
++ .id = 0,
++ .num_resources = 0,
++};
++
++static struct i2c_board_info __initdata snd_wm8804_i2c_devices[] = {
++ {
++ I2C_BOARD_INFO("wm8804", 0x3b)
++ },
++};
++
++#endif
++
++#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP_MODULE)
++static struct platform_device snd_hifiberry_amp_device = {
++ .name = "snd-hifiberry-amp",
++ .id = 0,
++ .num_resources = 0,
++};
++
++static struct i2c_board_info __initdata snd_tas5713_i2c_devices[] = {
++ {
++ I2C_BOARD_INFO("tas5713", 0x1b)
++ },
++};
++#endif
++
++#if defined(CONFIG_SND_BCM2708_SOC_RPI_DAC) || defined(CONFIG_SND_BCM2708_SOC_RPI_DAC_MODULE)
++static struct platform_device snd_rpi_dac_device = {
++ .name = "snd-rpi-dac",
++ .id = 0,
++ .num_resources = 0,
++};
++
++static struct platform_device snd_pcm1794a_codec_device = {
++ .name = "pcm1794a-codec",
++ .id = -1,
++ .num_resources = 0,
++};
++#endif
++
++
++#if defined(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC) || defined(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC_MODULE)
++static struct platform_device snd_rpi_iqaudio_dac_device = {
++ .name = "snd-rpi-iqaudio-dac",
++ .id = 0,
++ .num_resources = 0,
++};
++
++// Use the actual device name rather than generic driver name
++static struct i2c_board_info __initdata snd_pcm512x_i2c_devices[] = {
++ {
++ I2C_BOARD_INFO("pcm5122", 0x4c)
++ },
++};
++#endif
++
++int __init bcm_register_device(struct platform_device *pdev)
++{
++ int ret;
++
++ ret = platform_device_register(pdev);
++ if (ret)
++ pr_debug("Unable to register platform device '%s': %d\n",
++ pdev->name, ret);
++
++ return ret;
++}
++
++/*
++ * Use these macros for platform and i2c devices that are present in the
++ * Device Tree. This way the devices are only added on non-DT systems.
++ */
++#define bcm_register_device_dt(pdev) \
++ if (!use_dt) bcm_register_device(pdev)
++
++#define i2c_register_board_info_dt(busnum, info, n) \
++ if (!use_dt) i2c_register_board_info(busnum, info, n)
++
++int calc_rsts(int partition)
++{
++ return PM_PASSWORD |
++ ((partition & (1 << 0)) << 0) |
++ ((partition & (1 << 1)) << 1) |
++ ((partition & (1 << 2)) << 2) |
++ ((partition & (1 << 3)) << 3) |
++ ((partition & (1 << 4)) << 4) |
++ ((partition & (1 << 5)) << 5);
++}
++
++static void bcm2709_restart(enum reboot_mode mode, const char *cmd)
++{
++ extern char bcm2708_reboot_mode;
++ uint32_t pm_rstc, pm_wdog;
++ uint32_t timeout = 10;
++ uint32_t pm_rsts = 0;
++
++ if(bcm2708_reboot_mode == 'q')
++ {
++ // NOOBS < 1.3 booting with reboot=q
++ pm_rsts = readl(__io_address(PM_RSTS));
++ pm_rsts = PM_PASSWORD | pm_rsts | PM_RSTS_HADWRQ_SET;
++ }
++ else if(bcm2708_reboot_mode == 'p')
++ {
++ // NOOBS < 1.3 halting
++ pm_rsts = readl(__io_address(PM_RSTS));
++ pm_rsts = PM_PASSWORD | pm_rsts | PM_RSTS_HADWRH_SET;
++ }
++ else
++ {
++ pm_rsts = calc_rsts(reboot_part);
++ }
++
++ writel(pm_rsts, __io_address(PM_RSTS));
++
++ /* Setup watchdog for reset */
++ pm_rstc = readl(__io_address(PM_RSTC));
++
++ pm_wdog = PM_PASSWORD | (timeout & PM_WDOG_TIME_SET); // watchdog timer = timer clock / 16; need password (31:16) + value (11:0)
++ pm_rstc = PM_PASSWORD | (pm_rstc & PM_RSTC_WRCFG_CLR) | PM_RSTC_WRCFG_FULL_RESET;
++
++ writel(pm_wdog, __io_address(PM_WDOG));
++ writel(pm_rstc, __io_address(PM_RSTC));
++}
++
++/* We can't really power off, but if we do the normal reset scheme, and indicate to bootcode.bin not to reboot, then most of the chip will be powered off */
++static void bcm2709_power_off(void)
++{
++ extern char bcm2708_reboot_mode;
++ if(bcm2708_reboot_mode == 'q')
++ {
++ // NOOBS < v1.3
++ bcm2709_restart('p', "");
++ }
++ else
++ {
++ /* partition 63 is special code for HALT the bootloader knows not to boot*/
++ reboot_part = 63;
++ /* continue with normal reset mechanism */
++ bcm2709_restart(0, "");
++ }
++}
++
++static void __init bcm2709_init_uart1(void)
++{
++ struct device_node *np;
++
++ np = of_find_compatible_node(NULL, NULL, "brcm,bcm2835-aux-uart");
++ if (of_device_is_available(np)) {
++ pr_info("bcm2709: Mini UART enabled\n");
++ writel(1, __io_address(UART1_BASE + 0x4));
++ }
++}
++
++#ifdef CONFIG_OF
++static void __init bcm2709_dt_init(void)
++{
++ int ret;
++
++ of_clk_init(NULL);
++ ret = of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
++ if (ret) {
++ pr_err("of_platform_populate failed: %d\n", ret);
++ /* Proceed as if CONFIG_OF was not defined */
++ } else {
++ use_dt = 1;
++ }
++}
++#else
++static void __init bcm2709_dt_init(void) { }
++#endif /* CONFIG_OF */
++
++void __init bcm2709_init(void)
++{
++ int i;
++
++#if defined(CONFIG_BCM_VC_CMA)
++ vc_cma_early_init();
++#endif
++ printk("bcm2709.uart_clock = %d\n", uart_clock);
++ pm_power_off = bcm2709_power_off;
++
++ bcm2709_init_clocks();
++ bcm2709_dt_init();
++
++ bcm_register_device_dt(&bcm2708_dmaengine_device);
++ bcm_register_device_dt(&bcm2708_vcio_device);
++ bcm_register_device_dt(&bcm2708_rpifw_device);
++ bcm_register_device_dt(&bcm2708_vchiq_device);
++#ifdef CONFIG_BCM2708_GPIO
++ bcm_register_device_dt(&bcm2708_gpio_device);
++#endif
++
++#if defined(CONFIG_PPS_CLIENT_GPIO) || defined(CONFIG_PPS_CLIENT_GPIO_MODULE)
++ if (!use_dt && (pps_gpio_pin >= 0)) {
++ pr_info("bcm2709: GPIO %d setup as pps-gpio device\n", pps_gpio_pin);
++ pps_gpio_info.gpio_pin = pps_gpio_pin;
++ pps_gpio_device.id = pps_gpio_pin;
++ bcm_register_device(&pps_gpio_device);
++ }
++#endif
++
++#if defined(CONFIG_W1_MASTER_GPIO) || defined(CONFIG_W1_MASTER_GPIO_MODULE)
++ w1_gpio_pdata.pin = w1_gpio_pin;
++ w1_gpio_pdata.ext_pullup_enable_pin = w1_gpio_pullup;
++ bcm_register_device_dt(&w1_device);
++#endif
++ bcm_register_device_dt(&bcm2708_fb_device);
++ bcm_register_device_dt(&bcm2708_usb_device);
++
++#ifdef CONFIG_MMC_BCM2835
++ bcm_register_device_dt(&bcm2835_emmc_device);
++#endif
++ bcm2709_init_led();
++ bcm2709_init_uart1();
++
++ /* Only create the platform devices for the ALSA driver in the
++ absence of an enabled "audio" DT node */
++ if (!use_dt ||
++ !of_device_is_available(of_find_node_by_path("/audio"))) {
++ for (i = 0; i < ARRAY_SIZE(bcm2708_alsa_devices); i++)
++ bcm_register_device(&bcm2708_alsa_devices[i]);
++ }
++
++ bcm_register_device_dt(&bcm2708_spi_device);
++
++ if (vc_i2c_override) {
++ bcm_register_device_dt(&bcm2708_bsc0_device);
++ bcm_register_device_dt(&bcm2708_bsc1_device);
++ } else if ((boardrev & 0xffffff) == 0x2 || (boardrev & 0xffffff) == 0x3) {
++ bcm_register_device_dt(&bcm2708_bsc0_device);
++ } else {
++ bcm_register_device_dt(&bcm2708_bsc1_device);
++ }
++
++ bcm_register_device_dt(&bcm2835_thermal_device);
++
++#if defined(CONFIG_SND_BCM2708_SOC_I2S) || defined(CONFIG_SND_BCM2708_SOC_I2S_MODULE)
++ bcm_register_device_dt(&bcm2708_i2s_device);
++#endif
++
++#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC_MODULE)
++ bcm_register_device_dt(&snd_hifiberry_dac_device);
++ bcm_register_device_dt(&snd_pcm5102a_codec_device);
++#endif
++
++#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS_MODULE)
++ bcm_register_device_dt(&snd_rpi_hifiberry_dacplus_device);
++ i2c_register_board_info_dt(1, snd_pcm512x_hbdacplus_i2c_devices, ARRAY_SIZE(snd_pcm512x_hbdacplus_i2c_devices));
++#endif
++
++#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI_MODULE)
++ bcm_register_device_dt(&snd_hifiberry_digi_device);
++ i2c_register_board_info_dt(1, snd_wm8804_i2c_devices, ARRAY_SIZE(snd_wm8804_i2c_devices));
++#endif
++
++#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP_MODULE)
++ bcm_register_device_dt(&snd_hifiberry_amp_device);
++ i2c_register_board_info_dt(1, snd_tas5713_i2c_devices, ARRAY_SIZE(snd_tas5713_i2c_devices));
++#endif
++
++#if defined(CONFIG_SND_BCM2708_SOC_RPI_DAC) || defined(CONFIG_SND_BCM2708_SOC_RPI_DAC_MODULE)
++ bcm_register_device_dt(&snd_rpi_dac_device);
++ bcm_register_device_dt(&snd_pcm1794a_codec_device);
++#endif
++
++#if defined(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC) || defined(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC_MODULE)
++ bcm_register_device_dt(&snd_rpi_iqaudio_dac_device);
++ i2c_register_board_info_dt(1, snd_pcm512x_i2c_devices, ARRAY_SIZE(snd_pcm512x_i2c_devices));
++#endif
++
++ if (!use_dt) {
++ for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
++ struct amba_device *d = amba_devs[i];
++ amba_device_register(d, &iomem_resource);
++ }
++ }
++ system_rev = boardrev;
++ system_serial_low = serial;
++
++#ifdef CONFIG_BCM2708_SPIDEV
++ if (!use_dt)
++ spi_register_board_info(bcm2708_spi_devices,
++ ARRAY_SIZE(bcm2708_spi_devices));
++#endif
++}
++
++#ifdef SYSTEM_TIMER
++static void timer_set_mode(enum clock_event_mode mode,
++ struct clock_event_device *clk)
++{
++ switch (mode) {
++ case CLOCK_EVT_MODE_ONESHOT: /* Leave the timer disabled, .set_next_event will enable it */
++ case CLOCK_EVT_MODE_SHUTDOWN:
++ break;
++ case CLOCK_EVT_MODE_PERIODIC:
++
++ case CLOCK_EVT_MODE_UNUSED:
++ case CLOCK_EVT_MODE_RESUME:
++
++ default:
++ printk(KERN_ERR "timer_set_mode: unhandled mode:%d\n",
++ (int)mode);
++ break;
++ }
++
++}
++
++static int timer_set_next_event(unsigned long cycles,
++ struct clock_event_device *unused)
++{
++ unsigned long stc;
++ do {
++ stc = readl(__io_address(ST_BASE + 0x04));
++ /* We could take a FIQ here, which may push ST above STC3 */
++ writel(stc + cycles, __io_address(ST_BASE + 0x18));
++ } while ((signed long) cycles >= 0 &&
++ (signed long) (readl(__io_address(ST_BASE + 0x04)) - stc)
++ >= (signed long) cycles);
++ return 0;
++}
++
++static struct clock_event_device timer0_clockevent = {
++ .name = "timer0",
++ .shift = 32,
++ .features = CLOCK_EVT_FEAT_ONESHOT,
++ .set_mode = timer_set_mode,
++ .set_next_event = timer_set_next_event,
++};
++
++/*
++ * IRQ handler for the timer
++ */
++static irqreturn_t bcm2709_timer_interrupt(int irq, void *dev_id)
++{
++ struct clock_event_device *evt = &timer0_clockevent;
++
++ writel(1 << 3, __io_address(ST_BASE + 0x00)); /* stcs clear timer int */
++
++ evt->event_handler(evt);
++
++ return IRQ_HANDLED;
++}
++
++static struct irqaction bcm2709_timer_irq = {
++ .name = "BCM2709 Timer Tick",
++ .flags = IRQF_TIMER | IRQF_IRQPOLL,
++ .handler = bcm2709_timer_interrupt,
++};
++
++/*
++ * Set up timer interrupt, and return the current time in seconds.
++ */
++
++static struct delay_timer bcm2709_delay_timer = {
++ .read_current_timer = bcm2709_read_current_timer,
++ .freq = STC_FREQ_HZ,
++};
++
++static void __init bcm2709_timer_init(void)
++{
++ /* init high res timer */
++ bcm2709_clocksource_init();
++
++ /*
++ * Make irqs happen for the system timer
++ */
++ setup_irq(IRQ_TIMER3, &bcm2709_timer_irq);
++
++ sched_clock_register(bcm2709_read_sched_clock, 32, STC_FREQ_HZ);
++
++ timer0_clockevent.mult =
++ div_sc(STC_FREQ_HZ, NSEC_PER_SEC, timer0_clockevent.shift);
++ timer0_clockevent.max_delta_ns =
++ clockevent_delta2ns(0xffffffff, &timer0_clockevent);
++ timer0_clockevent.min_delta_ns =
++ clockevent_delta2ns(0xf, &timer0_clockevent);
++
++ timer0_clockevent.cpumask = cpumask_of(0);
++ clockevents_register_device(&timer0_clockevent);
++
++ register_current_timer_delay(&bcm2709_delay_timer);
++}
++
++#else
++
++static void __init bcm2709_timer_init(void)
++{
++ extern void dc4_arch_timer_init(void);
++ // timer control
++ writel(0, __io_address(ARM_LOCAL_CONTROL));
++ // timer pre_scaler
++ writel(0x80000000, __io_address(ARM_LOCAL_PRESCALER)); // 19.2MHz
++ //writel(0x06AAAAAB, __io_address(ARM_LOCAL_PRESCALER)); // 1MHz
++
++ if (use_dt)
++ {
++ of_clk_init(NULL);
++ clocksource_of_init();
++ }
++ else
++ dc4_arch_timer_init();
++}
++
++#endif
++
++#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
++#include <linux/leds.h>
++
++static struct gpio_led bcm2709_leds[] = {
++ [0] = {
++ .gpio = 16,
++ .name = "led0",
++ .default_trigger = "mmc0",
++ .active_low = 1,
++ },
++};
++
++static struct gpio_led_platform_data bcm2709_led_pdata = {
++ .num_leds = ARRAY_SIZE(bcm2709_leds),
++ .leds = bcm2709_leds,
++};
++
++static struct platform_device bcm2709_led_device = {
++ .name = "leds-gpio",
++ .id = -1,
++ .dev = {
++ .platform_data = &bcm2709_led_pdata,
++ },
++};
++
++static void __init bcm2709_init_led(void)
++{
++ bcm2709_leds[0].gpio = disk_led_gpio;
++ bcm2709_leds[0].active_low = disk_led_active_low;
++ bcm_register_device_dt(&bcm2709_led_device);
++}
++#else
++static inline void bcm2709_init_led(void)
++{
++}
++#endif
++
++void __init bcm2709_init_early(void)
++{
++ /*
++ * Some devices allocate their coherent buffers from atomic
++ * context. Increase size of atomic coherent pool to make sure such
++ * the allocations won't fail.
++ */
++ init_dma_coherent_pool_size(SZ_4M);
++}
++
++static void __init board_reserve(void)
++{
++#if defined(CONFIG_BCM_VC_CMA)
++ vc_cma_reserve();
++#endif
++}
++
++
++#ifdef CONFIG_SMP
++#include <linux/smp.h>
++
++#include <mach/hardware.h>
++#include <asm/cacheflush.h>
++#include <asm/smp_plat.h>
++int dc4=0;
++//void dc4_log(unsigned x) { if (dc4) writel((x), __io_address(ST_BASE+10 + raw_smp_processor_id()*4)); }
++void dc4_log_dead(unsigned x) { if (dc4) writel((readl(__io_address(ST_BASE+0x10 + raw_smp_processor_id()*4)) & 0xffff) | ((x)<<16), __io_address(ST_BASE+0x10 + raw_smp_processor_id()*4)); }
++
++static void bcm2835_send_doorbell(const struct cpumask *mask, unsigned int irq)
++{
++ int cpu;
++ /*
++ * Ensure that stores to Normal memory are visible to the
++ * other CPUs before issuing the IPI.
++ */
++ dsb();
++
++ /* Convert our logical CPU mask into a physical one. */
++ for_each_cpu(cpu, mask)
++ {
++ /* submit softirq */
++ writel(1<<irq, __io_address(ARM_LOCAL_MAILBOX0_SET0 + 0x10 * MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 0)));
++ }
++}
++
++void __init bcm2709_smp_init_cpus(void)
++{
++ void secondary_startup(void);
++ unsigned int i, ncores;
++
++ ncores = 4; // xxx scu_get_core_count(NULL);
++ printk("[%s] enter (%x->%x)\n", __FUNCTION__, (unsigned)virt_to_phys((void *)secondary_startup), (unsigned)__io_address(ST_BASE + 0x10));
++ printk("[%s] ncores=%d\n", __FUNCTION__, ncores);
++
++ for (i = 0; i < ncores; i++) {
++ set_cpu_possible(i, true);
++ /* enable IRQ (not FIQ) */
++ writel(0x1, __io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 0x4 * i));
++ //writel(0xf, __io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 0x4 * i));
++ }
++ set_smp_cross_call(bcm2835_send_doorbell);
++}
++
++/*
++ * for arch/arm/kernel/smp.c:smp_prepare_cpus(unsigned int max_cpus)
++ */
++void __init bcm2709_smp_prepare_cpus(unsigned int max_cpus)
++{
++ //void __iomem *scu_base;
++
++ printk("[%s] enter\n", __FUNCTION__);
++ //scu_base = scu_base_addr();
++ //scu_enable(scu_base);
++}
++
++/*
++ * for linux/arch/arm/kernel/smp.c:secondary_start_kernel(void)
++ */
++void __cpuinit bcm2709_secondary_init(unsigned int cpu)
++{
++ printk("[%s] enter cpu:%d\n", __FUNCTION__, cpu);
++ //gic_secondary_init(0);
++}
++
++/*
++ * for linux/arch/arm/kernel/smp.c:__cpu_up(..)
++ */
++int __cpuinit bcm2709_boot_secondary(unsigned int cpu, struct task_struct *idle)
++{
++ void secondary_startup(void);
++ void *mbox_set = __io_address(ARM_LOCAL_MAILBOX3_SET0 + 0x10 * MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 0));
++ void *mbox_clr = __io_address(ARM_LOCAL_MAILBOX3_CLR0 + 0x10 * MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 0));
++ unsigned secondary_boot = (unsigned)virt_to_phys((void *)secondary_startup);
++ int timeout=20;
++ unsigned t = -1;
++ //printk("[%s] enter cpu:%d (%x->%p) %x\n", __FUNCTION__, cpu, secondary_boot, wake, readl(wake));
++
++ dsb();
++ BUG_ON(readl(mbox_clr) != 0);
++ writel(secondary_boot, mbox_set);
++
++ while (--timeout > 0) {
++ t = readl(mbox_clr);
++ if (t == 0) break;
++ cpu_relax();
++ }
++ if (timeout==0)
++ printk("[%s] cpu:%d failed to start (%x)\n", __FUNCTION__, cpu, t);
++ else
++ printk("[%s] cpu:%d started (%x) %d\n", __FUNCTION__, cpu, t, timeout);
++
++ return 0;
++}
++
++
++struct smp_operations bcm2709_smp_ops __initdata = {
++ .smp_init_cpus = bcm2709_smp_init_cpus,
++ .smp_prepare_cpus = bcm2709_smp_prepare_cpus,
++ .smp_secondary_init = bcm2709_secondary_init,
++ .smp_boot_secondary = bcm2709_boot_secondary,
++};
++#endif
++
++static const char * const bcm2709_compat[] = {
++ "brcm,bcm2709",
++ "brcm,bcm2708", /* Could use bcm2708 in a pinch */
++ NULL
++};
++
++MACHINE_START(BCM2709, "BCM2709")
++ /* Maintainer: Broadcom Europe Ltd. */
++#ifdef CONFIG_SMP
++ .smp = smp_ops(bcm2709_smp_ops),
++#endif
++ .map_io = bcm2709_map_io,
++ .init_irq = bcm2709_init_irq,
++ .init_time = bcm2709_timer_init,
++ .init_machine = bcm2709_init,
++ .init_early = bcm2709_init_early,
++ .reserve = board_reserve,
++ .restart = bcm2709_restart,
++ .dt_compat = bcm2709_compat,
++MACHINE_END
++
++MACHINE_START(BCM2708, "BCM2709")
++ /* Maintainer: Broadcom Europe Ltd. */
++#ifdef CONFIG_SMP
++ .smp = smp_ops(bcm2709_smp_ops),
++#endif
++ .map_io = bcm2709_map_io,
++ .init_irq = bcm2709_init_irq,
++ .init_time = bcm2709_timer_init,
++ .init_machine = bcm2709_init,
++ .init_early = bcm2709_init_early,
++ .reserve = board_reserve,
++ .restart = bcm2709_restart,
++ .dt_compat = bcm2709_compat,
++MACHINE_END
++
++module_param(force_core, uint, 0644);
++module_param(boardrev, uint, 0644);
++module_param(serial, uint, 0644);
++module_param(uart_clock, uint, 0644);
++module_param(disk_led_gpio, uint, 0644);
++module_param(disk_led_active_low, uint, 0644);
++module_param(reboot_part, uint, 0644);
++module_param(w1_gpio_pin, uint, 0644);
++module_param(w1_gpio_pullup, uint, 0644);
++module_param(vc_i2c_override, bool, 0644);
++MODULE_PARM_DESC(vc_i2c_override, "Allow the use of VC's I2C peripheral.");
++module_param(pps_gpio_pin, int, 0644);
++MODULE_PARM_DESC(pps_gpio_pin, "Set GPIO pin to reserve for PPS");
+diff -Nur linux-4.1.3/arch/arm/mach-bcm2709/bcm2709.h linux-xbian-rpi/arch/arm/mach-bcm2709/bcm2709.h
+--- linux-4.1.3/arch/arm/mach-bcm2709/bcm2709.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/mach-bcm2709/bcm2709.h 2015-07-28 01:20:58.174123488 +0200
+@@ -0,0 +1,49 @@
++/*
++ * linux/arch/arm/mach-bcm2708/bcm2708.h
++ *
++ * BCM2708 machine support header
++ *
++ * Copyright (C) 2010 Broadcom
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++
++#ifndef __BCM2708_BCM2708_H
++#define __BCM2708_BCM2708_H
++
++#include <linux/amba/bus.h>
++
++extern void __init bcm2708_init(void);
++extern void __init bcm2708_init_irq(void);
++extern void __init bcm2708_map_io(void);
++extern struct sys_timer bcm2708_timer;
++extern unsigned int mmc_status(struct device *dev);
++
++#define AMBA_DEVICE(name, busid, base, plat) \
++static struct amba_device name##_device = { \
++ .dev = { \
++ .coherent_dma_mask = ~0, \
++ .init_name = busid, \
++ .platform_data = plat, \
++ }, \
++ .res = { \
++ .start = base##_BASE, \
++ .end = (base##_BASE) + SZ_4K - 1,\
++ .flags = IORESOURCE_MEM, \
++ }, \
++ .irq = base##_IRQ, \
++}
++
++#endif
+diff -Nur linux-4.1.3/arch/arm/mach-bcm2709/delay.S linux-xbian-rpi/arch/arm/mach-bcm2709/delay.S
+--- linux-4.1.3/arch/arm/mach-bcm2709/delay.S 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/mach-bcm2709/delay.S 2015-07-28 01:20:58.174123488 +0200
+@@ -0,0 +1,21 @@
++/*
++ * linux/arch/arm/lib/delay.S
++ *
++ * Copyright (C) 1995, 1996 Russell King
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++#include <linux/linkage.h>
++#include <asm/assembler.h>
++#include <asm/param.h>
++
++ .text
++.align 3 @ 8 byte alignment seems to be needed to avoid fetching stalls
++@ Delay routine
++ENTRY(bcm2708_delay)
++ subs r0, r0, #1
++ bhi bcm2708_delay
++ mov pc, lr
++ENDPROC(bcm2708_delay)
+diff -Nur linux-4.1.3/arch/arm/mach-bcm2709/include/mach/arm_control.h linux-xbian-rpi/arch/arm/mach-bcm2709/include/mach/arm_control.h
+--- linux-4.1.3/arch/arm/mach-bcm2709/include/mach/arm_control.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/mach-bcm2709/include/mach/arm_control.h 2015-07-28 01:20:58.174123488 +0200
+@@ -0,0 +1,493 @@
++/*
++ * linux/arch/arm/mach-bcm2708/arm_control.h
++ *
++ * Copyright (C) 2010 Broadcom
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++
++#ifndef __BCM2708_ARM_CONTROL_H
++#define __BCM2708_ARM_CONTROL_H
++
++/*
++ * Definitions and addresses for the ARM CONTROL logic
++ * This file is manually generated.
++ */
++
++#define ARM_BASE 0x7E00B000
++
++/* Basic configuration */
++#define ARM_CONTROL0 HW_REGISTER_RW(ARM_BASE+0x000)
++#define ARM_C0_SIZ128M 0x00000000
++#define ARM_C0_SIZ256M 0x00000001
++#define ARM_C0_SIZ512M 0x00000002
++#define ARM_C0_SIZ1G 0x00000003
++#define ARM_C0_BRESP0 0x00000000
++#define ARM_C0_BRESP1 0x00000004
++#define ARM_C0_BRESP2 0x00000008
++#define ARM_C0_BOOTHI 0x00000010
++#define ARM_C0_UNUSED05 0x00000020 /* free */
++#define ARM_C0_FULLPERI 0x00000040
++#define ARM_C0_UNUSED78 0x00000180 /* free */
++#define ARM_C0_JTAGMASK 0x00000E00
++#define ARM_C0_JTAGOFF 0x00000000
++#define ARM_C0_JTAGBASH 0x00000800 /* Debug on GPIO off */
++#define ARM_C0_JTAGGPIO 0x00000C00 /* Debug on GPIO on */
++#define ARM_C0_APROTMSK 0x0000F000
++#define ARM_C0_DBG0SYNC 0x00010000 /* VPU0 halt sync */
++#define ARM_C0_DBG1SYNC 0x00020000 /* VPU1 halt sync */
++#define ARM_C0_SWDBGREQ 0x00040000 /* HW debug request */
++#define ARM_C0_PASSHALT 0x00080000 /* ARM halt passed to debugger */
++#define ARM_C0_PRIO_PER 0x00F00000 /* per priority mask */
++#define ARM_C0_PRIO_L2 0x0F000000
++#define ARM_C0_PRIO_UC 0xF0000000
++
++#define ARM_C0_APROTPASS 0x0000A000 /* Translate 1:1 */
++#define ARM_C0_APROTUSER 0x00000000 /* Only user mode */
++#define ARM_C0_APROTSYST 0x0000F000 /* Only system mode */
++
++
++#define ARM_CONTROL1 HW_REGISTER_RW(ARM_BASE+0x440)
++#define ARM_C1_TIMER 0x00000001 /* re-route timer IRQ to VC */
++#define ARM_C1_MAIL 0x00000002 /* re-route Mail IRQ to VC */
++#define ARM_C1_BELL0 0x00000004 /* re-route Doorbell 0 to VC */
++#define ARM_C1_BELL1 0x00000008 /* re-route Doorbell 1 to VC */
++#define ARM_C1_PERSON 0x00000100 /* peripherals on */
++#define ARM_C1_REQSTOP 0x00000200 /* ASYNC bridge request stop */
++
++#define ARM_STATUS HW_REGISTER_RW(ARM_BASE+0x444)
++#define ARM_S_ACKSTOP 0x80000000 /* Bridge stopped */
++#define ARM_S_READPEND 0x000003FF /* pending reads counter */
++#define ARM_S_WRITPEND 0x000FFC00 /* pending writes counter */
++
++#define ARM_ERRHALT HW_REGISTER_RW(ARM_BASE+0x448)
++#define ARM_EH_PERIBURST 0x00000001 /* Burst write seen on peri bus */
++#define ARM_EH_ILLADDRS1 0x00000002 /* Address bits 25-27 error */
++#define ARM_EH_ILLADDRS2 0x00000004 /* Address bits 31-28 error */
++#define ARM_EH_VPU0HALT 0x00000008 /* VPU0 halted & in debug mode */
++#define ARM_EH_VPU1HALT 0x00000010 /* VPU1 halted & in debug mode */
++#define ARM_EH_ARMHALT 0x00000020 /* ARM in halted debug mode */
++
++#define ARM_ID_SECURE HW_REGISTER_RW(ARM_BASE+0x00C)
++#define ARM_ID HW_REGISTER_RW(ARM_BASE+0x44C)
++#define ARM_IDVAL 0x364D5241
++
++/* Translation memory */
++#define ARM_TRANSLATE HW_REGISTER_RW(ARM_BASE+0x100)
++/* 32 locations: 0x100.. 0x17F */
++/* 32 spare means we CAN go to 64 pages.... */
++
++
++/* Interrupts */
++#define ARM_IRQ_PEND0 HW_REGISTER_RW(ARM_BASE+0x200) /* Top IRQ bits */
++#define ARM_I0_TIMER 0x00000001 /* timer IRQ */
++#define ARM_I0_MAIL 0x00000002 /* Mail IRQ */
++#define ARM_I0_BELL0 0x00000004 /* Doorbell 0 */
++#define ARM_I0_BELL1 0x00000008 /* Doorbell 1 */
++#define ARM_I0_BANK1 0x00000100 /* Bank1 IRQ */
++#define ARM_I0_BANK2 0x00000200 /* Bank2 IRQ */
++
++#define ARM_IRQ_PEND1 HW_REGISTER_RW(ARM_BASE+0x204) /* All bank1 IRQ bits */
++/* todo: all I1_interrupt sources */
++#define ARM_IRQ_PEND2 HW_REGISTER_RW(ARM_BASE+0x208) /* All bank2 IRQ bits */
++/* todo: all I2_interrupt sources */
++
++#define ARM_IRQ_FAST HW_REGISTER_RW(ARM_BASE+0x20C) /* FIQ control */
++#define ARM_IF_INDEX 0x0000007F /* FIQ select */
++#define ARM_IF_ENABLE 0x00000080 /* FIQ enable */
++#define ARM_IF_VCMASK 0x0000003F /* FIQ = (index from VC source) */
++#define ARM_IF_TIMER 0x00000040 /* FIQ = ARM timer */
++#define ARM_IF_MAIL 0x00000041 /* FIQ = ARM Mail */
++#define ARM_IF_BELL0 0x00000042 /* FIQ = ARM Doorbell 0 */
++#define ARM_IF_BELL1 0x00000043 /* FIQ = ARM Doorbell 1 */
++#define ARM_IF_VP0HALT 0x00000044 /* FIQ = VPU0 Halt seen */
++#define ARM_IF_VP1HALT 0x00000045 /* FIQ = VPU1 Halt seen */
++#define ARM_IF_ILLEGAL 0x00000046 /* FIQ = Illegal access seen */
++
++#define ARM_IRQ_ENBL1 HW_REGISTER_RW(ARM_BASE+0x210) /* Bank1 enable bits */
++#define ARM_IRQ_ENBL2 HW_REGISTER_RW(ARM_BASE+0x214) /* Bank2 enable bits */
++#define ARM_IRQ_ENBL3 HW_REGISTER_RW(ARM_BASE+0x218) /* ARM irqs enable bits */
++#define ARM_IRQ_DIBL1 HW_REGISTER_RW(ARM_BASE+0x21C) /* Bank1 disable bits */
++#define ARM_IRQ_DIBL2 HW_REGISTER_RW(ARM_BASE+0x220) /* Bank2 disable bits */
++#define ARM_IRQ_DIBL3 HW_REGISTER_RW(ARM_BASE+0x224) /* ARM irqs disable bits */
++#define ARM_IE_TIMER 0x00000001 /* Timer IRQ */
++#define ARM_IE_MAIL 0x00000002 /* Mail IRQ */
++#define ARM_IE_BELL0 0x00000004 /* Doorbell 0 */
++#define ARM_IE_BELL1 0x00000008 /* Doorbell 1 */
++#define ARM_IE_VP0HALT 0x00000010 /* VPU0 Halt */
++#define ARM_IE_VP1HALT 0x00000020 /* VPU1 Halt */
++#define ARM_IE_ILLEGAL 0x00000040 /* Illegal access seen */
++
++/* Timer */
++/* For reg. fields see sp804 spec. */
++#define ARM_T_LOAD HW_REGISTER_RW(ARM_BASE+0x400)
++#define ARM_T_VALUE HW_REGISTER_RW(ARM_BASE+0x404)
++#define ARM_T_CONTROL HW_REGISTER_RW(ARM_BASE+0x408)
++#define ARM_T_IRQCNTL HW_REGISTER_RW(ARM_BASE+0x40C)
++#define ARM_T_RAWIRQ HW_REGISTER_RW(ARM_BASE+0x410)
++#define ARM_T_MSKIRQ HW_REGISTER_RW(ARM_BASE+0x414)
++#define ARM_T_RELOAD HW_REGISTER_RW(ARM_BASE+0x418)
++#define ARM_T_PREDIV HW_REGISTER_RW(ARM_BASE+0x41c)
++#define ARM_T_FREECNT HW_REGISTER_RW(ARM_BASE+0x420)
++
++#define TIMER_CTRL_ONESHOT (1 << 0)
++#define TIMER_CTRL_32BIT (1 << 1)
++#define TIMER_CTRL_DIV1 (0 << 2)
++#define TIMER_CTRL_DIV16 (1 << 2)
++#define TIMER_CTRL_DIV256 (2 << 2)
++#define TIMER_CTRL_IE (1 << 5)
++#define TIMER_CTRL_PERIODIC (1 << 6)
++#define TIMER_CTRL_ENABLE (1 << 7)
++#define TIMER_CTRL_DBGHALT (1 << 8)
++#define TIMER_CTRL_ENAFREE (1 << 9)
++#define TIMER_CTRL_FREEDIV_SHIFT 16)
++#define TIMER_CTRL_FREEDIV_MASK 0xff
++
++/* Semaphores, Doorbells, Mailboxes */
++#define ARM_SBM_OWN0 (ARM_BASE+0x800)
++#define ARM_SBM_OWN1 (ARM_BASE+0x900)
++#define ARM_SBM_OWN2 (ARM_BASE+0xA00)
++#define ARM_SBM_OWN3 (ARM_BASE+0xB00)
++
++/* MAILBOXES
++ * Register flags are common across all
++ * owner registers. See end of this section
++ *
++ * Semaphores, Doorbells, Mailboxes Owner 0
++ *
++ */
++
++#define ARM_0_SEMS HW_REGISTER_RW(ARM_SBM_OWN0+0x00)
++#define ARM_0_SEM0 HW_REGISTER_RW(ARM_SBM_OWN0+0x00)
++#define ARM_0_SEM1 HW_REGISTER_RW(ARM_SBM_OWN0+0x04)
++#define ARM_0_SEM2 HW_REGISTER_RW(ARM_SBM_OWN0+0x08)
++#define ARM_0_SEM3 HW_REGISTER_RW(ARM_SBM_OWN0+0x0C)
++#define ARM_0_SEM4 HW_REGISTER_RW(ARM_SBM_OWN0+0x10)
++#define ARM_0_SEM5 HW_REGISTER_RW(ARM_SBM_OWN0+0x14)
++#define ARM_0_SEM6 HW_REGISTER_RW(ARM_SBM_OWN0+0x18)
++#define ARM_0_SEM7 HW_REGISTER_RW(ARM_SBM_OWN0+0x1C)
++#define ARM_0_BELL0 HW_REGISTER_RW(ARM_SBM_OWN0+0x40)
++#define ARM_0_BELL1 HW_REGISTER_RW(ARM_SBM_OWN0+0x44)
++#define ARM_0_BELL2 HW_REGISTER_RW(ARM_SBM_OWN0+0x48)
++#define ARM_0_BELL3 HW_REGISTER_RW(ARM_SBM_OWN0+0x4C)
++/* MAILBOX 0 access in Owner 0 area */
++/* Some addresses should ONLY be used by owner 0 */
++#define ARM_0_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN0+0x80) /* .. 0x8C (4 locations) */
++#define ARM_0_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN0+0x80) /* .. 0x8C (4 locations) Normal read */
++#define ARM_0_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN0+0x90) /* none-pop read */
++#define ARM_0_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN0+0x94) /* Sender read (only LS 2 bits) */
++#define ARM_0_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN0+0x98) /* Status read */
++#define ARM_0_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN0+0x9C) /* Config read/write */
++/* MAILBOX 1 access in Owner 0 area */
++/* Owner 0 should only WRITE to this mailbox */
++#define ARM_0_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) /* .. 0xAC (4 locations) */
++/*#define ARM_0_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) */ /* DO NOT USE THIS !!!!! */
++/*#define ARM_0_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN0+0xB0) */ /* DO NOT USE THIS !!!!! */
++/*#define ARM_0_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN0+0xB4) */ /* DO NOT USE THIS !!!!! */
++#define ARM_0_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN0+0xB8) /* Status read */
++/*#define ARM_0_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN0+0xBC) */ /* DO NOT USE THIS !!!!! */
++/* General SEM, BELL, MAIL config/status */
++#define ARM_0_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN0+0xE0) /* semaphore clear/debug register */
++#define ARM_0_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN0+0xE4) /* Doorbells clear/debug register */
++#define ARM_0_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN0+0xF8) /* ALL interrupts */
++#define ARM_0_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN0+0xFC) /* IRQS pending for owner 0 */
++
++/* Semaphores, Doorbells, Mailboxes Owner 1 */
++#define ARM_1_SEMS HW_REGISTER_RW(ARM_SBM_OWN1+0x00)
++#define ARM_1_SEM0 HW_REGISTER_RW(ARM_SBM_OWN1+0x00)
++#define ARM_1_SEM1 HW_REGISTER_RW(ARM_SBM_OWN1+0x04)
++#define ARM_1_SEM2 HW_REGISTER_RW(ARM_SBM_OWN1+0x08)
++#define ARM_1_SEM3 HW_REGISTER_RW(ARM_SBM_OWN1+0x0C)
++#define ARM_1_SEM4 HW_REGISTER_RW(ARM_SBM_OWN1+0x10)
++#define ARM_1_SEM5 HW_REGISTER_RW(ARM_SBM_OWN1+0x14)
++#define ARM_1_SEM6 HW_REGISTER_RW(ARM_SBM_OWN1+0x18)
++#define ARM_1_SEM7 HW_REGISTER_RW(ARM_SBM_OWN1+0x1C)
++#define ARM_1_BELL0 HW_REGISTER_RW(ARM_SBM_OWN1+0x40)
++#define ARM_1_BELL1 HW_REGISTER_RW(ARM_SBM_OWN1+0x44)
++#define ARM_1_BELL2 HW_REGISTER_RW(ARM_SBM_OWN1+0x48)
++#define ARM_1_BELL3 HW_REGISTER_RW(ARM_SBM_OWN1+0x4C)
++/* MAILBOX 0 access in Owner 0 area */
++/* Owner 1 should only WRITE to this mailbox */
++#define ARM_1_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN1+0x80) /* .. 0x8C (4 locations) */
++/*#define ARM_1_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN1+0x80) */ /* DO NOT USE THIS !!!!! */
++/*#define ARM_1_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN1+0x90) */ /* DO NOT USE THIS !!!!! */
++/*#define ARM_1_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN1+0x94) */ /* DO NOT USE THIS !!!!! */
++#define ARM_1_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN1+0x98) /* Status read */
++/*#define ARM_1_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN1+0x9C) */ /* DO NOT USE THIS !!!!! */
++/* MAILBOX 1 access in Owner 0 area */
++#define ARM_1_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN1+0xA0) /* .. 0xAC (4 locations) */
++#define ARM_1_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN1+0xA0) /* .. 0xAC (4 locations) Normal read */
++#define ARM_1_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN1+0xB0) /* none-pop read */
++#define ARM_1_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN1+0xB4) /* Sender read (only LS 2 bits) */
++#define ARM_1_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN1+0xB8) /* Status read */
++#define ARM_1_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN1+0xBC)
++/* General SEM, BELL, MAIL config/status */
++#define ARM_1_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN1+0xE0) /* semaphore clear/debug register */
++#define ARM_1_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN1+0xE4) /* Doorbells clear/debug register */
++#define ARM_1_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN1+0xFC) /* IRQS pending for owner 1 */
++#define ARM_1_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN1+0xF8) /* ALL interrupts */
++
++/* Semaphores, Doorbells, Mailboxes Owner 2 */
++#define ARM_2_SEMS HW_REGISTER_RW(ARM_SBM_OWN2+0x00)
++#define ARM_2_SEM0 HW_REGISTER_RW(ARM_SBM_OWN2+0x00)
++#define ARM_2_SEM1 HW_REGISTER_RW(ARM_SBM_OWN2+0x04)
++#define ARM_2_SEM2 HW_REGISTER_RW(ARM_SBM_OWN2+0x08)
++#define ARM_2_SEM3 HW_REGISTER_RW(ARM_SBM_OWN2+0x0C)
++#define ARM_2_SEM4 HW_REGISTER_RW(ARM_SBM_OWN2+0x10)
++#define ARM_2_SEM5 HW_REGISTER_RW(ARM_SBM_OWN2+0x14)
++#define ARM_2_SEM6 HW_REGISTER_RW(ARM_SBM_OWN2+0x18)
++#define ARM_2_SEM7 HW_REGISTER_RW(ARM_SBM_OWN2+0x1C)
++#define ARM_2_BELL0 HW_REGISTER_RW(ARM_SBM_OWN2+0x40)
++#define ARM_2_BELL1 HW_REGISTER_RW(ARM_SBM_OWN2+0x44)
++#define ARM_2_BELL2 HW_REGISTER_RW(ARM_SBM_OWN2+0x48)
++#define ARM_2_BELL3 HW_REGISTER_RW(ARM_SBM_OWN2+0x4C)
++/* MAILBOX 0 access in Owner 2 area */
++/* Owner 2 should only WRITE to this mailbox */
++#define ARM_2_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN2+0x80) /* .. 0x8C (4 locations) */
++/*#define ARM_2_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN2+0x80) */ /* DO NOT USE THIS !!!!! */
++/*#define ARM_2_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN2+0x90) */ /* DO NOT USE THIS !!!!! */
++/*#define ARM_2_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN2+0x94) */ /* DO NOT USE THIS !!!!! */
++#define ARM_2_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN2+0x98) /* Status read */
++/*#define ARM_2_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN2+0x9C) */ /* DO NOT USE THIS !!!!! */
++/* MAILBOX 1 access in Owner 2 area */
++/* Owner 2 should only WRITE to this mailbox */
++#define ARM_2_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) /* .. 0xAC (4 locations) */
++/*#define ARM_2_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) */ /* DO NOT USE THIS !!!!! */
++/*#define ARM_2_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN2+0xB0) */ /* DO NOT USE THIS !!!!! */
++/*#define ARM_2_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN2+0xB4) */ /* DO NOT USE THIS !!!!! */
++#define ARM_2_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN2+0xB8) /* Status read */
++/*#define ARM_2_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN2+0xBC) */ /* DO NOT USE THIS !!!!! */
++/* General SEM, BELL, MAIL config/status */
++#define ARM_2_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN2+0xE0) /* semaphore clear/debug register */
++#define ARM_2_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN2+0xE4) /* Doorbells clear/debug register */
++#define ARM_2_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN2+0xFC) /* IRQS pending for owner 2 */
++#define ARM_2_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN2+0xF8) /* ALL interrupts */
++
++/* Semaphores, Doorbells, Mailboxes Owner 3 */
++#define ARM_3_SEMS HW_REGISTER_RW(ARM_SBM_OWN3+0x00)
++#define ARM_3_SEM0 HW_REGISTER_RW(ARM_SBM_OWN3+0x00)
++#define ARM_3_SEM1 HW_REGISTER_RW(ARM_SBM_OWN3+0x04)
++#define ARM_3_SEM2 HW_REGISTER_RW(ARM_SBM_OWN3+0x08)
++#define ARM_3_SEM3 HW_REGISTER_RW(ARM_SBM_OWN3+0x0C)
++#define ARM_3_SEM4 HW_REGISTER_RW(ARM_SBM_OWN3+0x10)
++#define ARM_3_SEM5 HW_REGISTER_RW(ARM_SBM_OWN3+0x14)
++#define ARM_3_SEM6 HW_REGISTER_RW(ARM_SBM_OWN3+0x18)
++#define ARM_3_SEM7 HW_REGISTER_RW(ARM_SBM_OWN3+0x1C)
++#define ARM_3_BELL0 HW_REGISTER_RW(ARM_SBM_OWN3+0x40)
++#define ARM_3_BELL1 HW_REGISTER_RW(ARM_SBM_OWN3+0x44)
++#define ARM_3_BELL2 HW_REGISTER_RW(ARM_SBM_OWN3+0x48)
++#define ARM_3_BELL3 HW_REGISTER_RW(ARM_SBM_OWN3+0x4C)
++/* MAILBOX 0 access in Owner 3 area */
++/* Owner 3 should only WRITE to this mailbox */
++#define ARM_3_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN3+0x80) /* .. 0x8C (4 locations) */
++/*#define ARM_3_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN3+0x80) */ /* DO NOT USE THIS !!!!! */
++/*#define ARM_3_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN3+0x90) */ /* DO NOT USE THIS !!!!! */
++/*#define ARM_3_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN3+0x94) */ /* DO NOT USE THIS !!!!! */
++#define ARM_3_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN3+0x98) /* Status read */
++/*#define ARM_3_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN3+0x9C) */ /* DO NOT USE THIS !!!!! */
++/* MAILBOX 1 access in Owner 3 area */
++/* Owner 3 should only WRITE to this mailbox */
++#define ARM_3_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) /* .. 0xAC (4 locations) */
++/*#define ARM_3_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) */ /* DO NOT USE THIS !!!!! */
++/*#define ARM_3_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN3+0xB0) */ /* DO NOT USE THIS !!!!! */
++/*#define ARM_3_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN3+0xB4) */ /* DO NOT USE THIS !!!!! */
++#define ARM_3_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN3+0xB8) /* Status read */
++/*#define ARM_3_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN3+0xBC) */ /* DO NOT USE THIS !!!!! */
++/* General SEM, BELL, MAIL config/status */
++#define ARM_3_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN3+0xE0) /* semaphore clear/debug register */
++#define ARM_3_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN3+0xE4) /* Doorbells clear/debug register */
++#define ARM_3_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN3+0xFC) /* IRQS pending for owner 3 */
++#define ARM_3_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN3+0xF8) /* ALL interrupts */
++
++
++
++/* Mailbox flags. Valid for all owners */
++
++/* Mailbox status register (...0x98) */
++#define ARM_MS_FULL 0x80000000
++#define ARM_MS_EMPTY 0x40000000
++#define ARM_MS_LEVEL 0x400000FF /* Max. value depdnds on mailbox depth parameter */
++
++/* MAILBOX config/status register (...0x9C) */
++/* ANY write to this register clears the error bits! */
++#define ARM_MC_IHAVEDATAIRQEN 0x00000001 /* mailbox irq enable: has data */
++#define ARM_MC_IHAVESPACEIRQEN 0x00000002 /* mailbox irq enable: has space */
++#define ARM_MC_OPPISEMPTYIRQEN 0x00000004 /* mailbox irq enable: Opp. is empty */
++#define ARM_MC_MAIL_CLEAR 0x00000008 /* mailbox clear write 1, then 0 */
++#define ARM_MC_IHAVEDATAIRQPEND 0x00000010 /* mailbox irq pending: has space */
++#define ARM_MC_IHAVESPACEIRQPEND 0x00000020 /* mailbox irq pending: Opp. is empty */
++#define ARM_MC_OPPISEMPTYIRQPEND 0x00000040 /* mailbox irq pending */
++/* Bit 7 is unused */
++#define ARM_MC_ERRNOOWN 0x00000100 /* error : none owner read from mailbox */
++#define ARM_MC_ERROVERFLW 0x00000200 /* error : write to fill mailbox */
++#define ARM_MC_ERRUNDRFLW 0x00000400 /* error : read from empty mailbox */
++
++/* Semaphore clear/debug register (...0xE0) */
++#define ARM_SD_OWN0 0x00000003 /* Owner of sem 0 */
++#define ARM_SD_OWN1 0x0000000C /* Owner of sem 1 */
++#define ARM_SD_OWN2 0x00000030 /* Owner of sem 2 */
++#define ARM_SD_OWN3 0x000000C0 /* Owner of sem 3 */
++#define ARM_SD_OWN4 0x00000300 /* Owner of sem 4 */
++#define ARM_SD_OWN5 0x00000C00 /* Owner of sem 5 */
++#define ARM_SD_OWN6 0x00003000 /* Owner of sem 6 */
++#define ARM_SD_OWN7 0x0000C000 /* Owner of sem 7 */
++#define ARM_SD_SEM0 0x00010000 /* Status of sem 0 */
++#define ARM_SD_SEM1 0x00020000 /* Status of sem 1 */
++#define ARM_SD_SEM2 0x00040000 /* Status of sem 2 */
++#define ARM_SD_SEM3 0x00080000 /* Status of sem 3 */
++#define ARM_SD_SEM4 0x00100000 /* Status of sem 4 */
++#define ARM_SD_SEM5 0x00200000 /* Status of sem 5 */
++#define ARM_SD_SEM6 0x00400000 /* Status of sem 6 */
++#define ARM_SD_SEM7 0x00800000 /* Status of sem 7 */
++
++/* Doorbells clear/debug register (...0xE4) */
++#define ARM_BD_OWN0 0x00000003 /* Owner of doorbell 0 */
++#define ARM_BD_OWN1 0x0000000C /* Owner of doorbell 1 */
++#define ARM_BD_OWN2 0x00000030 /* Owner of doorbell 2 */
++#define ARM_BD_OWN3 0x000000C0 /* Owner of doorbell 3 */
++#define ARM_BD_BELL0 0x00000100 /* Status of doorbell 0 */
++#define ARM_BD_BELL1 0x00000200 /* Status of doorbell 1 */
++#define ARM_BD_BELL2 0x00000400 /* Status of doorbell 2 */
++#define ARM_BD_BELL3 0x00000800 /* Status of doorbell 3 */
++
++/* MY IRQS register (...0xF8) */
++#define ARM_MYIRQ_BELL 0x00000001 /* This owner has a doorbell IRQ */
++#define ARM_MYIRQ_MAIL 0x00000002 /* This owner has a mailbox IRQ */
++
++/* ALL IRQS register (...0xF8) */
++#define ARM_AIS_BELL0 0x00000001 /* Doorbell 0 IRQ pending */
++#define ARM_AIS_BELL1 0x00000002 /* Doorbell 1 IRQ pending */
++#define ARM_AIS_BELL2 0x00000004 /* Doorbell 2 IRQ pending */
++#define ARM_AIS_BELL3 0x00000008 /* Doorbell 3 IRQ pending */
++#define ARM_AIS0_HAVEDATA 0x00000010 /* MAIL 0 has data IRQ pending */
++#define ARM_AIS0_HAVESPAC 0x00000020 /* MAIL 0 has space IRQ pending */
++#define ARM_AIS0_OPPEMPTY 0x00000040 /* MAIL 0 opposite is empty IRQ */
++#define ARM_AIS1_HAVEDATA 0x00000080 /* MAIL 1 has data IRQ pending */
++#define ARM_AIS1_HAVESPAC 0x00000100 /* MAIL 1 has space IRQ pending */
++#define ARM_AIS1_OPPEMPTY 0x00000200 /* MAIL 1 opposite is empty IRQ */
++/* Note that bell-0, bell-1 and MAIL0 IRQ go only to the ARM */
++/* Whilst that bell-2, bell-3 and MAIL1 IRQ go only to the VC */
++/* */
++/* ARM JTAG BASH */
++/* */
++#define AJB_BASE 0x7e2000c0
++
++#define AJBCONF HW_REGISTER_RW(AJB_BASE+0x00)
++#define AJB_BITS0 0x000000
++#define AJB_BITS4 0x000004
++#define AJB_BITS8 0x000008
++#define AJB_BITS12 0x00000C
++#define AJB_BITS16 0x000010
++#define AJB_BITS20 0x000014
++#define AJB_BITS24 0x000018
++#define AJB_BITS28 0x00001C
++#define AJB_BITS32 0x000020
++#define AJB_BITS34 0x000022
++#define AJB_OUT_MS 0x000040
++#define AJB_OUT_LS 0x000000
++#define AJB_INV_CLK 0x000080
++#define AJB_D0_RISE 0x000100
++#define AJB_D0_FALL 0x000000
++#define AJB_D1_RISE 0x000200
++#define AJB_D1_FALL 0x000000
++#define AJB_IN_RISE 0x000400
++#define AJB_IN_FALL 0x000000
++#define AJB_ENABLE 0x000800
++#define AJB_HOLD0 0x000000
++#define AJB_HOLD1 0x001000
++#define AJB_HOLD2 0x002000
++#define AJB_HOLD3 0x003000
++#define AJB_RESETN 0x004000
++#define AJB_CLKSHFT 16
++#define AJB_BUSY 0x80000000
++#define AJBTMS HW_REGISTER_RW(AJB_BASE+0x04)
++#define AJBTDI HW_REGISTER_RW(AJB_BASE+0x08)
++#define AJBTDO HW_REGISTER_RW(AJB_BASE+0x0c)
++
++#define ARM_LOCAL_BASE 0x40000000
++#define ARM_LOCAL_CONTROL HW_REGISTER_RW(ARM_LOCAL_BASE+0x000)
++#define ARM_LOCAL_PRESCALER HW_REGISTER_RW(ARM_LOCAL_BASE+0x008)
++#define ARM_LOCAL_GPU_INT_ROUTING HW_REGISTER_RW(ARM_LOCAL_BASE+0x00C)
++#define ARM_LOCAL_PM_ROUTING_SET HW_REGISTER_RW(ARM_LOCAL_BASE+0x010)
++#define ARM_LOCAL_PM_ROUTING_CLR HW_REGISTER_RW(ARM_LOCAL_BASE+0x014)
++#define ARM_LOCAL_TIMER_LS HW_REGISTER_RW(ARM_LOCAL_BASE+0x01C)
++#define ARM_LOCAL_TIMER_MS HW_REGISTER_RW(ARM_LOCAL_BASE+0x020)
++#define ARM_LOCAL_INT_ROUTING HW_REGISTER_RW(ARM_LOCAL_BASE+0x024)
++#define ARM_LOCAL_AXI_COUNT HW_REGISTER_RW(ARM_LOCAL_BASE+0x02C)
++#define ARM_LOCAL_AXI_IRQ HW_REGISTER_RW(ARM_LOCAL_BASE+0x030)
++#define ARM_LOCAL_TIMER_CONTROL HW_REGISTER_RW(ARM_LOCAL_BASE+0x034)
++#define ARM_LOCAL_TIMER_WRITE HW_REGISTER_RW(ARM_LOCAL_BASE+0x038)
++
++#define ARM_LOCAL_TIMER_INT_CONTROL0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x040)
++#define ARM_LOCAL_TIMER_INT_CONTROL1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x044)
++#define ARM_LOCAL_TIMER_INT_CONTROL2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x048)
++#define ARM_LOCAL_TIMER_INT_CONTROL3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x04C)
++
++#define ARM_LOCAL_MAILBOX_INT_CONTROL0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x050)
++#define ARM_LOCAL_MAILBOX_INT_CONTROL1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x054)
++#define ARM_LOCAL_MAILBOX_INT_CONTROL2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x058)
++#define ARM_LOCAL_MAILBOX_INT_CONTROL3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x05C)
++
++#define ARM_LOCAL_IRQ_PENDING0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x060)
++#define ARM_LOCAL_IRQ_PENDING1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x064)
++#define ARM_LOCAL_IRQ_PENDING2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x068)
++#define ARM_LOCAL_IRQ_PENDING3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x06C)
++
++#define ARM_LOCAL_FIQ_PENDING0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x070)
++#define ARM_LOCAL_FIQ_PENDING1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x074)
++#define ARM_LOCAL_FIQ_PENDING2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x078)
++#define ARM_LOCAL_FIQ_PENDING3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x07C)
++
++#define ARM_LOCAL_MAILBOX0_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x080)
++#define ARM_LOCAL_MAILBOX1_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x084)
++#define ARM_LOCAL_MAILBOX2_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x088)
++#define ARM_LOCAL_MAILBOX3_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x08C)
++
++#define ARM_LOCAL_MAILBOX0_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x090)
++#define ARM_LOCAL_MAILBOX1_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x094)
++#define ARM_LOCAL_MAILBOX2_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x098)
++#define ARM_LOCAL_MAILBOX3_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x09C)
++
++#define ARM_LOCAL_MAILBOX0_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A0)
++#define ARM_LOCAL_MAILBOX1_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A4)
++#define ARM_LOCAL_MAILBOX2_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A8)
++#define ARM_LOCAL_MAILBOX3_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0AC)
++
++#define ARM_LOCAL_MAILBOX0_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B0)
++#define ARM_LOCAL_MAILBOX1_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B4)
++#define ARM_LOCAL_MAILBOX2_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B8)
++#define ARM_LOCAL_MAILBOX3_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0BC)
++
++#define ARM_LOCAL_MAILBOX0_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C0)
++#define ARM_LOCAL_MAILBOX1_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C4)
++#define ARM_LOCAL_MAILBOX2_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C8)
++#define ARM_LOCAL_MAILBOX3_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0CC)
++
++#define ARM_LOCAL_MAILBOX0_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D0)
++#define ARM_LOCAL_MAILBOX1_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D4)
++#define ARM_LOCAL_MAILBOX2_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D8)
++#define ARM_LOCAL_MAILBOX3_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0DC)
++
++#define ARM_LOCAL_MAILBOX0_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E0)
++#define ARM_LOCAL_MAILBOX1_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E4)
++#define ARM_LOCAL_MAILBOX2_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E8)
++#define ARM_LOCAL_MAILBOX3_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0EC)
++
++#define ARM_LOCAL_MAILBOX0_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F0)
++#define ARM_LOCAL_MAILBOX1_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F4)
++#define ARM_LOCAL_MAILBOX2_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F8)
++#define ARM_LOCAL_MAILBOX3_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0FC)
++
++#endif
+diff -Nur linux-4.1.3/arch/arm/mach-bcm2709/include/mach/barriers.h linux-xbian-rpi/arch/arm/mach-bcm2709/include/mach/barriers.h
+--- linux-4.1.3/arch/arm/mach-bcm2709/include/mach/barriers.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/mach-bcm2709/include/mach/barriers.h 2015-07-28 01:20:58.182095047 +0200
+@@ -0,0 +1,3 @@
++#define mb() dsb()
++#define rmb() dsb()
++#define wmb() mb()
+diff -Nur linux-4.1.3/arch/arm/mach-bcm2709/include/mach/clkdev.h linux-xbian-rpi/arch/arm/mach-bcm2709/include/mach/clkdev.h
+--- linux-4.1.3/arch/arm/mach-bcm2709/include/mach/clkdev.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/mach-bcm2709/include/mach/clkdev.h 2015-07-28 01:20:58.182095047 +0200
+@@ -0,0 +1,7 @@
++#ifndef __ASM_MACH_CLKDEV_H
++#define __ASM_MACH_CLKDEV_H
++
++#define __clk_get(clk) ({ 1; })
++#define __clk_put(clk) do { } while (0)
++
++#endif
+diff -Nur linux-4.1.3/arch/arm/mach-bcm2709/include/mach/debug-macro.S linux-xbian-rpi/arch/arm/mach-bcm2709/include/mach/debug-macro.S
+--- linux-4.1.3/arch/arm/mach-bcm2709/include/mach/debug-macro.S 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/mach-bcm2709/include/mach/debug-macro.S 2015-07-28 01:20:58.182095047 +0200
+@@ -0,0 +1,22 @@
++/* arch/arm/mach-bcm2708/include/mach/debug-macro.S
++ *
++ * Debugging macro include header
++ *
++ * Copyright (C) 2010 Broadcom
++ * Copyright (C) 1994-1999 Russell King
++ * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++*/
++
++#include <mach/platform.h>
++
++ .macro addruart, rp, rv, tmp
++ ldr \rp, =UART0_BASE
++ ldr \rv, =IO_ADDRESS(UART0_BASE)
++ .endm
++
++#include <debug/pl01x.S>
+diff -Nur linux-4.1.3/arch/arm/mach-bcm2709/include/mach/entry-macro.S linux-xbian-rpi/arch/arm/mach-bcm2709/include/mach/entry-macro.S
+--- linux-4.1.3/arch/arm/mach-bcm2709/include/mach/entry-macro.S 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/mach-bcm2709/include/mach/entry-macro.S 2015-07-28 01:20:58.182095047 +0200
+@@ -0,0 +1,120 @@
++/*
++ * arch/arm/mach-bcm2708/include/mach/entry-macro.S
++ *
++ * Low-level IRQ helper macros for BCM2708 platforms
++ *
++ * Copyright (C) 2010 Broadcom
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++#include <mach/hardware.h>
++#include <mach/irqs.h>
++
++ .macro arch_ret_to_user, tmp1, tmp2
++ .endm
++
++ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
++
++ /* get core number */
++ mrc p15, 0, \base, c0, c0, 5
++ ubfx \base, \base, #0, #2
++
++ /* get core's local interrupt controller */
++ ldr \irqstat, = __io_address(ARM_LOCAL_IRQ_PENDING0) @ local interrupt source
++ add \irqstat, \irqstat, \base, lsl #2
++ ldr \tmp, [\irqstat]
++#ifdef CONFIG_SMP
++ /* test for mailbox0 (IPI) interrupt */
++ tst \tmp, #0x10
++ beq 1030f
++
++ /* get core's mailbox interrupt control */
++ ldr \irqstat, = __io_address(ARM_LOCAL_MAILBOX0_CLR0) @ mbox_clr
++ add \irqstat, \irqstat, \base, lsl #4
++ ldr \tmp, [\irqstat]
++ clz \tmp, \tmp
++ rsb \irqnr, \tmp, #31
++ mov \tmp, #1
++ lsl \tmp, \irqnr
++ str \tmp, [\irqstat] @ clear interrupt source
++ dsb
++ mov r1, sp
++ adr lr, BSYM(1b)
++ b do_IPI
++#endif
++1030:
++ /* check gpu interrupt */
++ tst \tmp, #0x100
++ beq 1040f
++
++ ldr \base, =IO_ADDRESS(ARMCTRL_IC_BASE)
++ /* get masked status */
++ ldr \irqstat, [\base, #(ARM_IRQ_PEND0 - ARMCTRL_IC_BASE)]
++ mov \irqnr, #(ARM_IRQ0_BASE + 31)
++ and \tmp, \irqstat, #0x300 @ save bits 8 and 9
++ /* clear bits 8 and 9, and test */
++ bics \irqstat, \irqstat, #0x300
++ bne 1010f
++
++ tst \tmp, #0x100
++ ldrne \irqstat, [\base, #(ARM_IRQ_PEND1 - ARMCTRL_IC_BASE)]
++ movne \irqnr, #(ARM_IRQ1_BASE + 31)
++ @ Mask out the interrupts also present in PEND0 - see SW-5809
++ bicne \irqstat, #((1<<7) | (1<<9) | (1<<10))
++ bicne \irqstat, #((1<<18) | (1<<19))
++ bne 1010f
++
++ tst \tmp, #0x200
++ ldrne \irqstat, [\base, #(ARM_IRQ_PEND2 - ARMCTRL_IC_BASE)]
++ movne \irqnr, #(ARM_IRQ2_BASE + 31)
++ @ Mask out the interrupts also present in PEND0 - see SW-5809
++ bicne \irqstat, #((1<<21) | (1<<22) | (1<<23) | (1<<24) | (1<<25))
++ bicne \irqstat, #((1<<30))
++ beq 1020f
++1010:
++ @ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1))
++ sub \tmp, \irqstat, #1
++ eor \irqstat, \irqstat, \tmp
++ clz \tmp, \irqstat
++ sub \irqnr, \tmp
++ b 1050f
++1040:
++ cmp \tmp, #0
++ beq 1020f
++
++ /* handle local (e.g. timer) interrupts */
++ @ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1))
++ mov \irqnr, #(ARM_IRQ_LOCAL_BASE + 31)
++ sub \irqstat, \tmp, #1
++ eor \irqstat, \irqstat, \tmp
++ clz \tmp, \irqstat
++ sub \irqnr, \tmp
++1050:
++ mov r1, sp
++ @
++ @ routine called with r0 = irq number, r1 = struct pt_regs *
++ @
++ adr lr, BSYM(1b)
++ b asm_do_IRQ
++
++1020: @ EQ will be set if no irqs pending
++ .endm
++
++/*
++ * Interrupt handling. Preserves r7, r8, r9
++ */
++ .macro arch_irq_handler_default
++1: get_irqnr_and_base r0, r2, r6, lr
++ .endm
+diff -Nur linux-4.1.3/arch/arm/mach-bcm2709/include/mach/frc.h linux-xbian-rpi/arch/arm/mach-bcm2709/include/mach/frc.h
+--- linux-4.1.3/arch/arm/mach-bcm2709/include/mach/frc.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/mach-bcm2709/include/mach/frc.h 2015-07-28 01:20:58.182095047 +0200
+@@ -0,0 +1,38 @@
++/*
++ * arch/arm/mach-bcm2708/include/mach/timex.h
++ *
++ * BCM2708 free running counter (timer)
++ *
++ * Copyright (C) 2010 Broadcom
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++
++#ifndef _MACH_FRC_H
++#define _MACH_FRC_H
++
++#define FRC_TICK_RATE (1000000)
++
++/*! Free running counter incrementing at the CLOCK_TICK_RATE
++ (slightly faster than frc_clock_ticks63()
++ */
++extern unsigned long frc_clock_ticks32(void);
++
++/*! Free running counter incrementing at the CLOCK_TICK_RATE
++ * Note - top bit should be ignored (see cnt32_to_63)
++ */
++extern unsigned long long frc_clock_ticks63(void);
++
++#endif
+diff -Nur linux-4.1.3/arch/arm/mach-bcm2709/include/mach/gpio.h linux-xbian-rpi/arch/arm/mach-bcm2709/include/mach/gpio.h
+--- linux-4.1.3/arch/arm/mach-bcm2709/include/mach/gpio.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/mach-bcm2709/include/mach/gpio.h 2015-07-28 01:20:58.182095047 +0200
+@@ -0,0 +1,17 @@
++/*
++ * arch/arm/mach-bcm2708/include/mach/gpio.h
++ *
++ * This file is licensed under the terms of the GNU General Public
++ * License version 2. This program is licensed "as is" without any
++ * warranty of any kind, whether express or implied.
++ */
++
++#ifndef __ASM_ARCH_GPIO_H
++#define __ASM_ARCH_GPIO_H
++
++#define BCM2708_NR_GPIOS 54 // number of gpio lines
++
++#define gpio_to_irq(x) ((x) + GPIO_IRQ_START)
++#define irq_to_gpio(x) ((x) - GPIO_IRQ_START)
++
++#endif
+diff -Nur linux-4.1.3/arch/arm/mach-bcm2709/include/mach/hardware.h linux-xbian-rpi/arch/arm/mach-bcm2709/include/mach/hardware.h
+--- linux-4.1.3/arch/arm/mach-bcm2709/include/mach/hardware.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/mach-bcm2709/include/mach/hardware.h 2015-07-28 01:20:58.182095047 +0200
+@@ -0,0 +1,28 @@
++/*
++ * arch/arm/mach-bcm2708/include/mach/hardware.h
++ *
++ * This file contains the hardware definitions of the BCM2708 devices.
++ *
++ * Copyright (C) 2010 Broadcom
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++#ifndef __ASM_ARCH_HARDWARE_H
++#define __ASM_ARCH_HARDWARE_H
++
++#include <asm/sizes.h>
++#include <mach/platform.h>
++
++#endif
+diff -Nur linux-4.1.3/arch/arm/mach-bcm2709/include/mach/io.h linux-xbian-rpi/arch/arm/mach-bcm2709/include/mach/io.h
+--- linux-4.1.3/arch/arm/mach-bcm2709/include/mach/io.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/mach-bcm2709/include/mach/io.h 2015-07-28 01:20:58.182095047 +0200
+@@ -0,0 +1,27 @@
++/*
++ * arch/arm/mach-bcm2708/include/mach/io.h
++ *
++ * Copyright (C) 2003 ARM Limited
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++#ifndef __ASM_ARM_ARCH_IO_H
++#define __ASM_ARM_ARCH_IO_H
++
++#define IO_SPACE_LIMIT 0xffffffff
++
++#define __io(a) __typesafe_io(a)
++
++#endif
+diff -Nur linux-4.1.3/arch/arm/mach-bcm2709/include/mach/irqs.h linux-xbian-rpi/arch/arm/mach-bcm2709/include/mach/irqs.h
+--- linux-4.1.3/arch/arm/mach-bcm2709/include/mach/irqs.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/mach-bcm2709/include/mach/irqs.h 2015-07-28 01:20:58.182095047 +0200
+@@ -0,0 +1,225 @@
++/*
++ * arch/arm/mach-bcm2708/include/mach/irqs.h
++ *
++ * Copyright (C) 2010 Broadcom
++ * Copyright (C) 2003 ARM Limited
++ * Copyright (C) 2000 Deep Blue Solutions Ltd.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++
++#ifndef _BCM2708_IRQS_H_
++#define _BCM2708_IRQS_H_
++
++#include <mach/platform.h>
++
++/*
++ * IRQ interrupts definitions are the same as the INT definitions
++ * held within platform.h
++ */
++#define IRQ_ARMCTRL_START 0
++#define IRQ_TIMER0 (IRQ_ARMCTRL_START + INTERRUPT_TIMER0)
++#define IRQ_TIMER1 (IRQ_ARMCTRL_START + INTERRUPT_TIMER1)
++#define IRQ_TIMER2 (IRQ_ARMCTRL_START + INTERRUPT_TIMER2)
++#define IRQ_TIMER3 (IRQ_ARMCTRL_START + INTERRUPT_TIMER3)
++#define IRQ_CODEC0 (IRQ_ARMCTRL_START + INTERRUPT_CODEC0)
++#define IRQ_CODEC1 (IRQ_ARMCTRL_START + INTERRUPT_CODEC1)
++#define IRQ_CODEC2 (IRQ_ARMCTRL_START + INTERRUPT_CODEC2)
++#define IRQ_JPEG (IRQ_ARMCTRL_START + INTERRUPT_JPEG)
++#define IRQ_ISP (IRQ_ARMCTRL_START + INTERRUPT_ISP)
++#define IRQ_USB (IRQ_ARMCTRL_START + INTERRUPT_USB)
++#define IRQ_3D (IRQ_ARMCTRL_START + INTERRUPT_3D)
++#define IRQ_TRANSPOSER (IRQ_ARMCTRL_START + INTERRUPT_TRANSPOSER)
++#define IRQ_MULTICORESYNC0 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC0)
++#define IRQ_MULTICORESYNC1 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC1)
++#define IRQ_MULTICORESYNC2 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC2)
++#define IRQ_MULTICORESYNC3 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC3)
++#define IRQ_DMA0 (IRQ_ARMCTRL_START + INTERRUPT_DMA0)
++#define IRQ_DMA1 (IRQ_ARMCTRL_START + INTERRUPT_DMA1)
++#define IRQ_DMA2 (IRQ_ARMCTRL_START + INTERRUPT_DMA2)
++#define IRQ_DMA3 (IRQ_ARMCTRL_START + INTERRUPT_DMA3)
++#define IRQ_DMA4 (IRQ_ARMCTRL_START + INTERRUPT_DMA4)
++#define IRQ_DMA5 (IRQ_ARMCTRL_START + INTERRUPT_DMA5)
++#define IRQ_DMA6 (IRQ_ARMCTRL_START + INTERRUPT_DMA6)
++#define IRQ_DMA7 (IRQ_ARMCTRL_START + INTERRUPT_DMA7)
++#define IRQ_DMA8 (IRQ_ARMCTRL_START + INTERRUPT_DMA8)
++#define IRQ_DMA9 (IRQ_ARMCTRL_START + INTERRUPT_DMA9)
++#define IRQ_DMA10 (IRQ_ARMCTRL_START + INTERRUPT_DMA10)
++#define IRQ_DMA11 (IRQ_ARMCTRL_START + INTERRUPT_DMA11)
++#define IRQ_DMA12 (IRQ_ARMCTRL_START + INTERRUPT_DMA12)
++#define IRQ_AUX (IRQ_ARMCTRL_START + INTERRUPT_AUX)
++#define IRQ_ARM (IRQ_ARMCTRL_START + INTERRUPT_ARM)
++#define IRQ_VPUDMA (IRQ_ARMCTRL_START + INTERRUPT_VPUDMA)
++#define IRQ_HOSTPORT (IRQ_ARMCTRL_START + INTERRUPT_HOSTPORT)
++#define IRQ_VIDEOSCALER (IRQ_ARMCTRL_START + INTERRUPT_VIDEOSCALER)
++#define IRQ_CCP2TX (IRQ_ARMCTRL_START + INTERRUPT_CCP2TX)
++#define IRQ_SDC (IRQ_ARMCTRL_START + INTERRUPT_SDC)
++#define IRQ_DSI0 (IRQ_ARMCTRL_START + INTERRUPT_DSI0)
++#define IRQ_AVE (IRQ_ARMCTRL_START + INTERRUPT_AVE)
++#define IRQ_CAM0 (IRQ_ARMCTRL_START + INTERRUPT_CAM0)
++#define IRQ_CAM1 (IRQ_ARMCTRL_START + INTERRUPT_CAM1)
++#define IRQ_HDMI0 (IRQ_ARMCTRL_START + INTERRUPT_HDMI0)
++#define IRQ_HDMI1 (IRQ_ARMCTRL_START + INTERRUPT_HDMI1)
++#define IRQ_PIXELVALVE1 (IRQ_ARMCTRL_START + INTERRUPT_PIXELVALVE1)
++#define IRQ_I2CSPISLV (IRQ_ARMCTRL_START + INTERRUPT_I2CSPISLV)
++#define IRQ_DSI1 (IRQ_ARMCTRL_START + INTERRUPT_DSI1)
++#define IRQ_PWA0 (IRQ_ARMCTRL_START + INTERRUPT_PWA0)
++#define IRQ_PWA1 (IRQ_ARMCTRL_START + INTERRUPT_PWA1)
++#define IRQ_CPR (IRQ_ARMCTRL_START + INTERRUPT_CPR)
++#define IRQ_SMI (IRQ_ARMCTRL_START + INTERRUPT_SMI)
++#define IRQ_GPIO0 (IRQ_ARMCTRL_START + INTERRUPT_GPIO0)
++#define IRQ_GPIO1 (IRQ_ARMCTRL_START + INTERRUPT_GPIO1)
++#define IRQ_GPIO2 (IRQ_ARMCTRL_START + INTERRUPT_GPIO2)
++#define IRQ_GPIO3 (IRQ_ARMCTRL_START + INTERRUPT_GPIO3)
++#define IRQ_I2C (IRQ_ARMCTRL_START + INTERRUPT_I2C)
++#define IRQ_SPI (IRQ_ARMCTRL_START + INTERRUPT_SPI)
++#define IRQ_I2SPCM (IRQ_ARMCTRL_START + INTERRUPT_I2SPCM)
++#define IRQ_SDIO (IRQ_ARMCTRL_START + INTERRUPT_SDIO)
++#define IRQ_UART (IRQ_ARMCTRL_START + INTERRUPT_UART)
++#define IRQ_SLIMBUS (IRQ_ARMCTRL_START + INTERRUPT_SLIMBUS)
++#define IRQ_VEC (IRQ_ARMCTRL_START + INTERRUPT_VEC)
++#define IRQ_CPG (IRQ_ARMCTRL_START + INTERRUPT_CPG)
++#define IRQ_RNG (IRQ_ARMCTRL_START + INTERRUPT_RNG)
++#define IRQ_ARASANSDIO (IRQ_ARMCTRL_START + INTERRUPT_ARASANSDIO)
++#define IRQ_AVSPMON (IRQ_ARMCTRL_START + INTERRUPT_AVSPMON)
++
++#define IRQ_ARM_TIMER (IRQ_ARMCTRL_START + INTERRUPT_ARM_TIMER)
++#define IRQ_ARM_MAILBOX (IRQ_ARMCTRL_START + INTERRUPT_ARM_MAILBOX)
++#define IRQ_ARM_DOORBELL_0 (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_0)
++#define IRQ_ARM_DOORBELL_1 (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_1)
++#define IRQ_VPU0_HALTED (IRQ_ARMCTRL_START + INTERRUPT_VPU0_HALTED)
++#define IRQ_VPU1_HALTED (IRQ_ARMCTRL_START + INTERRUPT_VPU1_HALTED)
++#define IRQ_ILLEGAL_TYPE0 (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE0)
++#define IRQ_ILLEGAL_TYPE1 (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE1)
++#define IRQ_PENDING1 (IRQ_ARMCTRL_START + INTERRUPT_PENDING1)
++#define IRQ_PENDING2 (IRQ_ARMCTRL_START + INTERRUPT_PENDING2)
++
++#define IRQ_ARM_LOCAL_CNTPSIRQ (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTPSIRQ)
++#define IRQ_ARM_LOCAL_CNTPNSIRQ (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTPNSIRQ)
++#define IRQ_ARM_LOCAL_CNTHPIRQ (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTHPIRQ)
++#define IRQ_ARM_LOCAL_CNTVIRQ (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTVIRQ)
++#define IRQ_ARM_LOCAL_MAILBOX0 (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX0)
++#define IRQ_ARM_LOCAL_MAILBOX1 (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX1)
++#define IRQ_ARM_LOCAL_MAILBOX2 (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX2)
++#define IRQ_ARM_LOCAL_MAILBOX3 (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX3)
++#define IRQ_ARM_LOCAL_GPU_FAST (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_GPU_FAST)
++#define IRQ_ARM_LOCAL_PMU_FAST (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_PMU_FAST)
++#define IRQ_ARM_LOCAL_ZERO (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_ZERO)
++#define IRQ_ARM_LOCAL_TIMER (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_TIMER)
++
++#define FIQ_START HARD_IRQS
++
++/*
++ * FIQ interrupts definitions are the same as the INT definitions.
++ */
++#define FIQ_TIMER0 (FIQ_START+INTERRUPT_TIMER0)
++#define FIQ_TIMER1 (FIQ_START+INTERRUPT_TIMER1)
++#define FIQ_TIMER2 (FIQ_START+INTERRUPT_TIMER2)
++#define FIQ_TIMER3 (FIQ_START+INTERRUPT_TIMER3)
++#define FIQ_CODEC0 (FIQ_START+INTERRUPT_CODEC0)
++#define FIQ_CODEC1 (FIQ_START+INTERRUPT_CODEC1)
++#define FIQ_CODEC2 (FIQ_START+INTERRUPT_CODEC2)
++#define FIQ_JPEG (FIQ_START+INTERRUPT_JPEG)
++#define FIQ_ISP (FIQ_START+INTERRUPT_ISP)
++#define FIQ_USB (FIQ_START+INTERRUPT_USB)
++#define FIQ_3D (FIQ_START+INTERRUPT_3D)
++#define FIQ_TRANSPOSER (FIQ_START+INTERRUPT_TRANSPOSER)
++#define FIQ_MULTICORESYNC0 (FIQ_START+INTERRUPT_MULTICORESYNC0)
++#define FIQ_MULTICORESYNC1 (FIQ_START+INTERRUPT_MULTICORESYNC1)
++#define FIQ_MULTICORESYNC2 (FIQ_START+INTERRUPT_MULTICORESYNC2)
++#define FIQ_MULTICORESYNC3 (FIQ_START+INTERRUPT_MULTICORESYNC3)
++#define FIQ_DMA0 (FIQ_START+INTERRUPT_DMA0)
++#define FIQ_DMA1 (FIQ_START+INTERRUPT_DMA1)
++#define FIQ_DMA2 (FIQ_START+INTERRUPT_DMA2)
++#define FIQ_DMA3 (FIQ_START+INTERRUPT_DMA3)
++#define FIQ_DMA4 (FIQ_START+INTERRUPT_DMA4)
++#define FIQ_DMA5 (FIQ_START+INTERRUPT_DMA5)
++#define FIQ_DMA6 (FIQ_START+INTERRUPT_DMA6)
++#define FIQ_DMA7 (FIQ_START+INTERRUPT_DMA7)
++#define FIQ_DMA8 (FIQ_START+INTERRUPT_DMA8)
++#define FIQ_DMA9 (FIQ_START+INTERRUPT_DMA9)
++#define FIQ_DMA10 (FIQ_START+INTERRUPT_DMA10)
++#define FIQ_DMA11 (FIQ_START+INTERRUPT_DMA11)
++#define FIQ_DMA12 (FIQ_START+INTERRUPT_DMA12)
++#define FIQ_AUX (FIQ_START+INTERRUPT_AUX)
++#define FIQ_ARM (FIQ_START+INTERRUPT_ARM)
++#define FIQ_VPUDMA (FIQ_START+INTERRUPT_VPUDMA)
++#define FIQ_HOSTPORT (FIQ_START+INTERRUPT_HOSTPORT)
++#define FIQ_VIDEOSCALER (FIQ_START+INTERRUPT_VIDEOSCALER)
++#define FIQ_CCP2TX (FIQ_START+INTERRUPT_CCP2TX)
++#define FIQ_SDC (FIQ_START+INTERRUPT_SDC)
++#define FIQ_DSI0 (FIQ_START+INTERRUPT_DSI0)
++#define FIQ_AVE (FIQ_START+INTERRUPT_AVE)
++#define FIQ_CAM0 (FIQ_START+INTERRUPT_CAM0)
++#define FIQ_CAM1 (FIQ_START+INTERRUPT_CAM1)
++#define FIQ_HDMI0 (FIQ_START+INTERRUPT_HDMI0)
++#define FIQ_HDMI1 (FIQ_START+INTERRUPT_HDMI1)
++#define FIQ_PIXELVALVE1 (FIQ_START+INTERRUPT_PIXELVALVE1)
++#define FIQ_I2CSPISLV (FIQ_START+INTERRUPT_I2CSPISLV)
++#define FIQ_DSI1 (FIQ_START+INTERRUPT_DSI1)
++#define FIQ_PWA0 (FIQ_START+INTERRUPT_PWA0)
++#define FIQ_PWA1 (FIQ_START+INTERRUPT_PWA1)
++#define FIQ_CPR (FIQ_START+INTERRUPT_CPR)
++#define FIQ_SMI (FIQ_START+INTERRUPT_SMI)
++#define FIQ_GPIO0 (FIQ_START+INTERRUPT_GPIO0)
++#define FIQ_GPIO1 (FIQ_START+INTERRUPT_GPIO1)
++#define FIQ_GPIO2 (FIQ_START+INTERRUPT_GPIO2)
++#define FIQ_GPIO3 (FIQ_START+INTERRUPT_GPIO3)
++#define FIQ_I2C (FIQ_START+INTERRUPT_I2C)
++#define FIQ_SPI (FIQ_START+INTERRUPT_SPI)
++#define FIQ_I2SPCM (FIQ_START+INTERRUPT_I2SPCM)
++#define FIQ_SDIO (FIQ_START+INTERRUPT_SDIO)
++#define FIQ_UART (FIQ_START+INTERRUPT_UART)
++#define FIQ_SLIMBUS (FIQ_START+INTERRUPT_SLIMBUS)
++#define FIQ_VEC (FIQ_START+INTERRUPT_VEC)
++#define FIQ_CPG (FIQ_START+INTERRUPT_CPG)
++#define FIQ_RNG (FIQ_START+INTERRUPT_RNG)
++#define FIQ_ARASANSDIO (FIQ_START+INTERRUPT_ARASANSDIO)
++#define FIQ_AVSPMON (FIQ_START+INTERRUPT_AVSPMON)
++
++#define FIQ_ARM_TIMER (FIQ_START+INTERRUPT_ARM_TIMER)
++#define FIQ_ARM_MAILBOX (FIQ_START+INTERRUPT_ARM_MAILBOX)
++#define FIQ_ARM_DOORBELL_0 (FIQ_START+INTERRUPT_ARM_DOORBELL_0)
++#define FIQ_ARM_DOORBELL_1 (FIQ_START+INTERRUPT_ARM_DOORBELL_1)
++#define FIQ_VPU0_HALTED (FIQ_START+INTERRUPT_VPU0_HALTED)
++#define FIQ_VPU1_HALTED (FIQ_START+INTERRUPT_VPU1_HALTED)
++#define FIQ_ILLEGAL_TYPE0 (FIQ_START+INTERRUPT_ILLEGAL_TYPE0)
++#define FIQ_ILLEGAL_TYPE1 (FIQ_START+INTERRUPT_ILLEGAL_TYPE1)
++#define FIQ_PENDING1 (FIQ_START+INTERRUPT_PENDING1)
++#define FIQ_PENDING2 (FIQ_START+INTERRUPT_PENDING2)
++
++#define FIQ_ARM_LOCAL_CNTPSIRQ (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTPSIRQ)
++#define FIQ_ARM_LOCAL_CNTPNSIRQ (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTPNSIRQ)
++#define FIQ_ARM_LOCAL_CNTHPIRQ (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTHPIRQ)
++#define FIQ_ARM_LOCAL_CNTVIRQ (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTVIRQ)
++#define FIQ_ARM_LOCAL_MAILBOX0 (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX0)
++#define FIQ_ARM_LOCAL_MAILBOX1 (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX1)
++#define FIQ_ARM_LOCAL_MAILBOX2 (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX2)
++#define FIQ_ARM_LOCAL_MAILBOX3 (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX3)
++#define FIQ_ARM_LOCAL_GPU_FAST (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_GPU_FAST)
++#define FIQ_ARM_LOCAL_PMU_FAST (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_PMU_FAST)
++#define FIQ_ARM_LOCAL_ZERO (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_ZERO)
++#define FIQ_ARM_LOCAL_TIMER (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_TIMER)
++
++#define HARD_IRQS (128)
++#define FIQ_IRQS (128)
++#define GPIO_IRQ_START (HARD_IRQS + FIQ_IRQS)
++#define GPIO_IRQS (32*5)
++#define SPARE_ALLOC_IRQS 64
++#define BCM2708_ALLOC_IRQS (HARD_IRQS+FIQ_IRQS+GPIO_IRQS+SPARE_ALLOC_IRQS)
++#define FREE_IRQS 128
++#define NR_IRQS (BCM2708_ALLOC_IRQS+FREE_IRQS)
++
++#endif /* _BCM2708_IRQS_H_ */
+diff -Nur linux-4.1.3/arch/arm/mach-bcm2709/include/mach/memory.h linux-xbian-rpi/arch/arm/mach-bcm2709/include/mach/memory.h
+--- linux-4.1.3/arch/arm/mach-bcm2709/include/mach/memory.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/mach-bcm2709/include/mach/memory.h 2015-07-28 01:20:58.182095047 +0200
+@@ -0,0 +1,57 @@
++/*
++ * arch/arm/mach-bcm2708/include/mach/memory.h
++ *
++ * Copyright (C) 2010 Broadcom
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++#ifndef __ASM_ARCH_MEMORY_H
++#define __ASM_ARCH_MEMORY_H
++
++/* Memory overview:
++
++ [ARMcore] <--virtual addr-->
++ [ARMmmu] <--physical addr-->
++ [GERTmap] <--bus add-->
++ [VCperiph]
++
++*/
++
++/*
++ * Physical DRAM offset.
++ */
++#define BCM_PLAT_PHYS_OFFSET UL(0x00000000)
++#define VC_ARMMEM_OFFSET UL(0x00000000) /* offset in VC of ARM memory */
++
++#ifdef CONFIG_BCM2708_NOL2CACHE
++ #define _REAL_BUS_OFFSET UL(0xC0000000) /* don't use L1 or L2 caches */
++#else
++ #define _REAL_BUS_OFFSET UL(0x40000000) /* use L2 cache */
++#endif
++
++/* We're using the memory at 64M in the VideoCore for Linux - this adjustment
++ * will provide the offset into this area as well as setting the bits that
++ * stop the L1 and L2 cache from being used
++ *
++ * WARNING: this only works because the ARM is given memory at a fixed location
++ * (ARMMEM_OFFSET)
++ */
++#define BUS_OFFSET (VC_ARMMEM_OFFSET + _REAL_BUS_OFFSET)
++#define __virt_to_bus(x) ((x) + (BUS_OFFSET - PAGE_OFFSET))
++#define __bus_to_virt(x) ((x) - (BUS_OFFSET - PAGE_OFFSET))
++#define __pfn_to_bus(x) (__pfn_to_phys(x) + (BUS_OFFSET - BCM_PLAT_PHYS_OFFSET))
++#define __bus_to_pfn(x) __phys_to_pfn((x) - (BUS_OFFSET - BCM_PLAT_PHYS_OFFSET))
++
++#endif
+diff -Nur linux-4.1.3/arch/arm/mach-bcm2709/include/mach/platform.h linux-xbian-rpi/arch/arm/mach-bcm2709/include/mach/platform.h
+--- linux-4.1.3/arch/arm/mach-bcm2709/include/mach/platform.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/mach-bcm2709/include/mach/platform.h 2015-07-28 01:20:58.182095047 +0200
+@@ -0,0 +1,227 @@
++/*
++ * arch/arm/mach-bcm2708/include/mach/platform.h
++ *
++ * Copyright (C) 2010 Broadcom
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++
++#ifndef _BCM2708_PLATFORM_H
++#define _BCM2708_PLATFORM_H
++
++
++/* macros to get at IO space when running virtually */
++#define IO_ADDRESS(x) (((x) & 0x00ffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000)
++
++#define __io_address(n) IOMEM(IO_ADDRESS(n))
++
++
++/*
++ * SDRAM
++ */
++#define BCM2708_SDRAM_BASE 0x00000000
++
++/*
++ * Logic expansion modules
++ *
++ */
++
++
++/* ------------------------------------------------------------------------
++ * BCM2708 ARMCTRL Registers
++ * ------------------------------------------------------------------------
++ */
++
++#define HW_REGISTER_RW(addr) (addr)
++#define HW_REGISTER_RO(addr) (addr)
++
++#include "arm_control.h"
++#undef ARM_BASE
++
++/*
++ * Definitions and addresses for the ARM CONTROL logic
++ * This file is manually generated.
++ */
++
++#define BCM2708_PERI_BASE 0x3F000000
++#define IC0_BASE (BCM2708_PERI_BASE + 0x2000)
++#define ST_BASE (BCM2708_PERI_BASE + 0x3000) /* System Timer */
++#define MPHI_BASE (BCM2708_PERI_BASE + 0x6000) /* Message -based Parallel Host Interface */
++#define DMA_BASE (BCM2708_PERI_BASE + 0x7000) /* DMA controller */
++#define ARM_BASE (BCM2708_PERI_BASE + 0xB000) /* BCM2708 ARM control block */
++#define PM_BASE (BCM2708_PERI_BASE + 0x100000) /* Power Management, Reset controller and Watchdog registers */
++#define PCM_CLOCK_BASE (BCM2708_PERI_BASE + 0x101098) /* PCM Clock */
++#define RNG_BASE (BCM2708_PERI_BASE + 0x104000) /* Hardware RNG */
++#define GPIO_BASE (BCM2708_PERI_BASE + 0x200000) /* GPIO */
++#define UART0_BASE (BCM2708_PERI_BASE + 0x201000) /* Uart 0 */
++#define MMCI0_BASE (BCM2708_PERI_BASE + 0x202000) /* MMC interface */
++#define I2S_BASE (BCM2708_PERI_BASE + 0x203000) /* I2S */
++#define SPI0_BASE (BCM2708_PERI_BASE + 0x204000) /* SPI0 */
++#define BSC0_BASE (BCM2708_PERI_BASE + 0x205000) /* BSC0 I2C/TWI */
++#define UART1_BASE (BCM2708_PERI_BASE + 0x215000) /* Uart 1 */
++#define EMMC_BASE (BCM2708_PERI_BASE + 0x300000) /* eMMC interface */
++#define SMI_BASE (BCM2708_PERI_BASE + 0x600000) /* SMI */
++#define BSC1_BASE (BCM2708_PERI_BASE + 0x804000) /* BSC1 I2C/TWI */
++#define USB_BASE (BCM2708_PERI_BASE + 0x980000) /* DTC_OTG USB controller */
++#define MCORE_BASE (BCM2708_PERI_BASE + 0x0000) /* Fake frame buffer device (actually the multicore sync block*/
++
++#define ARMCTRL_BASE (ARM_BASE + 0x000)
++#define ARMCTRL_IC_BASE (ARM_BASE + 0x200) /* ARM interrupt controller */
++#define ARMCTRL_TIMER0_1_BASE (ARM_BASE + 0x400) /* Timer 0 and 1 */
++#define ARMCTRL_0_SBM_BASE (ARM_BASE + 0x800) /* User 0 (ARM)'s Semaphores Doorbells and Mailboxes */
++#define ARMCTRL_0_BELL_BASE (ARMCTRL_0_SBM_BASE + 0x40) /* User 0 (ARM)'s Doorbell */
++#define ARMCTRL_0_MAIL0_BASE (ARMCTRL_0_SBM_BASE + 0x80) /* User 0 (ARM)'s Mailbox 0 */
++
++
++/*
++ * Interrupt assignments
++ */
++
++#define ARM_IRQ1_BASE 0
++#define INTERRUPT_TIMER0 (ARM_IRQ1_BASE + 0)
++#define INTERRUPT_TIMER1 (ARM_IRQ1_BASE + 1)
++#define INTERRUPT_TIMER2 (ARM_IRQ1_BASE + 2)
++#define INTERRUPT_TIMER3 (ARM_IRQ1_BASE + 3)
++#define INTERRUPT_CODEC0 (ARM_IRQ1_BASE + 4)
++#define INTERRUPT_CODEC1 (ARM_IRQ1_BASE + 5)
++#define INTERRUPT_CODEC2 (ARM_IRQ1_BASE + 6)
++#define INTERRUPT_VC_JPEG (ARM_IRQ1_BASE + 7)
++#define INTERRUPT_ISP (ARM_IRQ1_BASE + 8)
++#define INTERRUPT_VC_USB (ARM_IRQ1_BASE + 9)
++#define INTERRUPT_VC_3D (ARM_IRQ1_BASE + 10)
++#define INTERRUPT_TRANSPOSER (ARM_IRQ1_BASE + 11)
++#define INTERRUPT_MULTICORESYNC0 (ARM_IRQ1_BASE + 12)
++#define INTERRUPT_MULTICORESYNC1 (ARM_IRQ1_BASE + 13)
++#define INTERRUPT_MULTICORESYNC2 (ARM_IRQ1_BASE + 14)
++#define INTERRUPT_MULTICORESYNC3 (ARM_IRQ1_BASE + 15)
++#define INTERRUPT_DMA0 (ARM_IRQ1_BASE + 16)
++#define INTERRUPT_DMA1 (ARM_IRQ1_BASE + 17)
++#define INTERRUPT_VC_DMA2 (ARM_IRQ1_BASE + 18)
++#define INTERRUPT_VC_DMA3 (ARM_IRQ1_BASE + 19)
++#define INTERRUPT_DMA4 (ARM_IRQ1_BASE + 20)
++#define INTERRUPT_DMA5 (ARM_IRQ1_BASE + 21)
++#define INTERRUPT_DMA6 (ARM_IRQ1_BASE + 22)
++#define INTERRUPT_DMA7 (ARM_IRQ1_BASE + 23)
++#define INTERRUPT_DMA8 (ARM_IRQ1_BASE + 24)
++#define INTERRUPT_DMA9 (ARM_IRQ1_BASE + 25)
++#define INTERRUPT_DMA10 (ARM_IRQ1_BASE + 26)
++#define INTERRUPT_DMA11 (ARM_IRQ1_BASE + 27)
++#define INTERRUPT_DMA12 (ARM_IRQ1_BASE + 28)
++#define INTERRUPT_AUX (ARM_IRQ1_BASE + 29)
++#define INTERRUPT_ARM (ARM_IRQ1_BASE + 30)
++#define INTERRUPT_VPUDMA (ARM_IRQ1_BASE + 31)
++
++#define ARM_IRQ2_BASE 32
++#define INTERRUPT_HOSTPORT (ARM_IRQ2_BASE + 0)
++#define INTERRUPT_VIDEOSCALER (ARM_IRQ2_BASE + 1)
++#define INTERRUPT_CCP2TX (ARM_IRQ2_BASE + 2)
++#define INTERRUPT_SDC (ARM_IRQ2_BASE + 3)
++#define INTERRUPT_DSI0 (ARM_IRQ2_BASE + 4)
++#define INTERRUPT_AVE (ARM_IRQ2_BASE + 5)
++#define INTERRUPT_CAM0 (ARM_IRQ2_BASE + 6)
++#define INTERRUPT_CAM1 (ARM_IRQ2_BASE + 7)
++#define INTERRUPT_HDMI0 (ARM_IRQ2_BASE + 8)
++#define INTERRUPT_HDMI1 (ARM_IRQ2_BASE + 9)
++#define INTERRUPT_PIXELVALVE1 (ARM_IRQ2_BASE + 10)
++#define INTERRUPT_I2CSPISLV (ARM_IRQ2_BASE + 11)
++#define INTERRUPT_DSI1 (ARM_IRQ2_BASE + 12)
++#define INTERRUPT_PWA0 (ARM_IRQ2_BASE + 13)
++#define INTERRUPT_PWA1 (ARM_IRQ2_BASE + 14)
++#define INTERRUPT_CPR (ARM_IRQ2_BASE + 15)
++#define INTERRUPT_SMI (ARM_IRQ2_BASE + 16)
++#define INTERRUPT_GPIO0 (ARM_IRQ2_BASE + 17)
++#define INTERRUPT_GPIO1 (ARM_IRQ2_BASE + 18)
++#define INTERRUPT_GPIO2 (ARM_IRQ2_BASE + 19)
++#define INTERRUPT_GPIO3 (ARM_IRQ2_BASE + 20)
++#define INTERRUPT_VC_I2C (ARM_IRQ2_BASE + 21)
++#define INTERRUPT_VC_SPI (ARM_IRQ2_BASE + 22)
++#define INTERRUPT_VC_I2SPCM (ARM_IRQ2_BASE + 23)
++#define INTERRUPT_VC_SDIO (ARM_IRQ2_BASE + 24)
++#define INTERRUPT_VC_UART (ARM_IRQ2_BASE + 25)
++#define INTERRUPT_SLIMBUS (ARM_IRQ2_BASE + 26)
++#define INTERRUPT_VEC (ARM_IRQ2_BASE + 27)
++#define INTERRUPT_CPG (ARM_IRQ2_BASE + 28)
++#define INTERRUPT_RNG (ARM_IRQ2_BASE + 29)
++#define INTERRUPT_VC_ARASANSDIO (ARM_IRQ2_BASE + 30)
++#define INTERRUPT_AVSPMON (ARM_IRQ2_BASE + 31)
++
++#define ARM_IRQ0_BASE 64
++#define INTERRUPT_ARM_TIMER (ARM_IRQ0_BASE + 0)
++#define INTERRUPT_ARM_MAILBOX (ARM_IRQ0_BASE + 1)
++#define INTERRUPT_ARM_DOORBELL_0 (ARM_IRQ0_BASE + 2)
++#define INTERRUPT_ARM_DOORBELL_1 (ARM_IRQ0_BASE + 3)
++#define INTERRUPT_VPU0_HALTED (ARM_IRQ0_BASE + 4)
++#define INTERRUPT_VPU1_HALTED (ARM_IRQ0_BASE + 5)
++#define INTERRUPT_ILLEGAL_TYPE0 (ARM_IRQ0_BASE + 6)
++#define INTERRUPT_ILLEGAL_TYPE1 (ARM_IRQ0_BASE + 7)
++#define INTERRUPT_PENDING1 (ARM_IRQ0_BASE + 8)
++#define INTERRUPT_PENDING2 (ARM_IRQ0_BASE + 9)
++#define INTERRUPT_JPEG (ARM_IRQ0_BASE + 10)
++#define INTERRUPT_USB (ARM_IRQ0_BASE + 11)
++#define INTERRUPT_3D (ARM_IRQ0_BASE + 12)
++#define INTERRUPT_DMA2 (ARM_IRQ0_BASE + 13)
++#define INTERRUPT_DMA3 (ARM_IRQ0_BASE + 14)
++#define INTERRUPT_I2C (ARM_IRQ0_BASE + 15)
++#define INTERRUPT_SPI (ARM_IRQ0_BASE + 16)
++#define INTERRUPT_I2SPCM (ARM_IRQ0_BASE + 17)
++#define INTERRUPT_SDIO (ARM_IRQ0_BASE + 18)
++#define INTERRUPT_UART (ARM_IRQ0_BASE + 19)
++#define INTERRUPT_ARASANSDIO (ARM_IRQ0_BASE + 20)
++
++#define ARM_IRQ_LOCAL_BASE 96
++#define INTERRUPT_ARM_LOCAL_CNTPSIRQ (ARM_IRQ_LOCAL_BASE + 0)
++#define INTERRUPT_ARM_LOCAL_CNTPNSIRQ (ARM_IRQ_LOCAL_BASE + 1)
++#define INTERRUPT_ARM_LOCAL_CNTHPIRQ (ARM_IRQ_LOCAL_BASE + 2)
++#define INTERRUPT_ARM_LOCAL_CNTVIRQ (ARM_IRQ_LOCAL_BASE + 3)
++#define INTERRUPT_ARM_LOCAL_MAILBOX0 (ARM_IRQ_LOCAL_BASE + 4)
++#define INTERRUPT_ARM_LOCAL_MAILBOX1 (ARM_IRQ_LOCAL_BASE + 5)
++#define INTERRUPT_ARM_LOCAL_MAILBOX2 (ARM_IRQ_LOCAL_BASE + 6)
++#define INTERRUPT_ARM_LOCAL_MAILBOX3 (ARM_IRQ_LOCAL_BASE + 7)
++#define INTERRUPT_ARM_LOCAL_GPU_FAST (ARM_IRQ_LOCAL_BASE + 8)
++#define INTERRUPT_ARM_LOCAL_PMU_FAST (ARM_IRQ_LOCAL_BASE + 9)
++#define INTERRUPT_ARM_LOCAL_ZERO (ARM_IRQ_LOCAL_BASE + 10)
++#define INTERRUPT_ARM_LOCAL_TIMER (ARM_IRQ_LOCAL_BASE + 11)
++
++/*
++ * Watchdog
++ */
++#define PM_RSTC (PM_BASE+0x1c)
++#define PM_RSTS (PM_BASE+0x20)
++#define PM_WDOG (PM_BASE+0x24)
++
++#define PM_WDOG_RESET 0000000000
++#define PM_PASSWORD 0x5a000000
++#define PM_WDOG_TIME_SET 0x000fffff
++#define PM_RSTC_WRCFG_CLR 0xffffffcf
++#define PM_RSTC_WRCFG_SET 0x00000030
++#define PM_RSTC_WRCFG_FULL_RESET 0x00000020
++#define PM_RSTC_RESET 0x00000102
++
++#define PM_RSTS_HADPOR_SET 0x00001000
++#define PM_RSTS_HADSRH_SET 0x00000400
++#define PM_RSTS_HADSRF_SET 0x00000200
++#define PM_RSTS_HADSRQ_SET 0x00000100
++#define PM_RSTS_HADWRH_SET 0x00000040
++#define PM_RSTS_HADWRF_SET 0x00000020
++#define PM_RSTS_HADWRQ_SET 0x00000010
++#define PM_RSTS_HADDRH_SET 0x00000004
++#define PM_RSTS_HADDRF_SET 0x00000002
++#define PM_RSTS_HADDRQ_SET 0x00000001
++
++#define UART0_CLOCK 3000000
++
++#endif
++
++/* END */
+diff -Nur linux-4.1.3/arch/arm/mach-bcm2709/include/mach/system.h linux-xbian-rpi/arch/arm/mach-bcm2709/include/mach/system.h
+--- linux-4.1.3/arch/arm/mach-bcm2709/include/mach/system.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/mach-bcm2709/include/mach/system.h 2015-07-28 01:20:58.182095047 +0200
+@@ -0,0 +1,38 @@
++/*
++ * arch/arm/mach-bcm2708/include/mach/system.h
++ *
++ * Copyright (C) 2010 Broadcom
++ * Copyright (C) 2003 ARM Limited
++ * Copyright (C) 2000 Deep Blue Solutions Ltd
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++#ifndef __ASM_ARCH_SYSTEM_H
++#define __ASM_ARCH_SYSTEM_H
++
++#include <linux/io.h>
++#include <mach/hardware.h>
++#include <mach/platform.h>
++
++static inline void arch_idle(void)
++{
++ /*
++ * This should do all the clock switching
++ * and wait for interrupt tricks
++ */
++ cpu_do_idle();
++}
++
++#endif
+diff -Nur linux-4.1.3/arch/arm/mach-bcm2709/include/mach/timex.h linux-xbian-rpi/arch/arm/mach-bcm2709/include/mach/timex.h
+--- linux-4.1.3/arch/arm/mach-bcm2709/include/mach/timex.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/mach-bcm2709/include/mach/timex.h 2015-07-28 01:20:58.182095047 +0200
+@@ -0,0 +1,23 @@
++/*
++ * arch/arm/mach-bcm2708/include/mach/timex.h
++ *
++ * BCM2708 sysem clock frequency
++ *
++ * Copyright (C) 2010 Broadcom
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++
++#define CLOCK_TICK_RATE (1000000)
+diff -Nur linux-4.1.3/arch/arm/mach-bcm2709/include/mach/uncompress.h linux-xbian-rpi/arch/arm/mach-bcm2709/include/mach/uncompress.h
+--- linux-4.1.3/arch/arm/mach-bcm2709/include/mach/uncompress.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/mach-bcm2709/include/mach/uncompress.h 2015-07-28 01:20:58.182095047 +0200
+@@ -0,0 +1,84 @@
++/*
++ * arch/arm/mach-bcn2708/include/mach/uncompress.h
++ *
++ * Copyright (C) 2010 Broadcom
++ * Copyright (C) 2003 ARM Limited
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++
++#include <linux/io.h>
++#include <linux/amba/serial.h>
++#include <mach/hardware.h>
++
++#define UART_BAUD 115200
++
++#define BCM2708_UART_DR __io(UART0_BASE + UART01x_DR)
++#define BCM2708_UART_FR __io(UART0_BASE + UART01x_FR)
++#define BCM2708_UART_IBRD __io(UART0_BASE + UART011_IBRD)
++#define BCM2708_UART_FBRD __io(UART0_BASE + UART011_FBRD)
++#define BCM2708_UART_LCRH __io(UART0_BASE + UART011_LCRH)
++#define BCM2708_UART_CR __io(UART0_BASE + UART011_CR)
++
++/*
++ * This does not append a newline
++ */
++static inline void putc(int c)
++{
++ while (__raw_readl(BCM2708_UART_FR) & UART01x_FR_TXFF)
++ barrier();
++
++ __raw_writel(c, BCM2708_UART_DR);
++}
++
++static inline void flush(void)
++{
++ int fr;
++
++ do {
++ fr = __raw_readl(BCM2708_UART_FR);
++ barrier();
++ } while ((fr & (UART011_FR_TXFE | UART01x_FR_BUSY)) != UART011_FR_TXFE);
++}
++
++static inline void arch_decomp_setup(void)
++{
++ int temp, div, rem, frac;
++
++ temp = 16 * UART_BAUD;
++ div = UART0_CLOCK / temp;
++ rem = UART0_CLOCK % temp;
++ temp = (8 * rem) / UART_BAUD;
++ frac = (temp >> 1) + (temp & 1);
++
++ /* Make sure the UART is disabled before we start */
++ __raw_writel(0, BCM2708_UART_CR);
++
++ /* Set the baud rate */
++ __raw_writel(div, BCM2708_UART_IBRD);
++ __raw_writel(frac, BCM2708_UART_FBRD);
++
++ /* Set the UART to 8n1, FIFO enabled */
++ __raw_writel(UART01x_LCRH_WLEN_8 | UART01x_LCRH_FEN, BCM2708_UART_LCRH);
++
++ /* Enable the UART */
++ __raw_writel(UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_RXE,
++ BCM2708_UART_CR);
++}
++
++/*
++ * nothing to do
++ */
++#define arch_decomp_wdog()
+diff -Nur linux-4.1.3/arch/arm/mach-bcm2709/include/mach/vc_support.h linux-xbian-rpi/arch/arm/mach-bcm2709/include/mach/vc_support.h
+--- linux-4.1.3/arch/arm/mach-bcm2709/include/mach/vc_support.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/mach-bcm2709/include/mach/vc_support.h 2015-07-28 01:20:58.182095047 +0200
+@@ -0,0 +1,69 @@
++#ifndef _VC_SUPPORT_H_
++#define _VC_SUPPORT_H_
++
++/*
++ * vc_support.h
++ *
++ * Created on: 25 Nov 2012
++ * Author: Simon
++ */
++
++enum {
++/*
++ If a MEM_HANDLE_T is discardable, the memory manager may resize it to size
++ 0 at any time when it is not locked or retained.
++ */
++ MEM_FLAG_DISCARDABLE = 1 << 0,
++
++ /*
++ If a MEM_HANDLE_T is allocating (or normal), its block of memory will be
++ accessed in an allocating fashion through the cache.
++ */
++ MEM_FLAG_NORMAL = 0 << 2,
++ MEM_FLAG_ALLOCATING = MEM_FLAG_NORMAL,
++
++ /*
++ If a MEM_HANDLE_T is direct, its block of memory will be accessed
++ directly, bypassing the cache.
++ */
++ MEM_FLAG_DIRECT = 1 << 2,
++
++ /*
++ If a MEM_HANDLE_T is coherent, its block of memory will be accessed in a
++ non-allocating fashion through the cache.
++ */
++ MEM_FLAG_COHERENT = 2 << 2,
++
++ /*
++ If a MEM_HANDLE_T is L1-nonallocating, its block of memory will be accessed by
++ the VPU in a fashion which is allocating in L2, but only coherent in L1.
++ */
++ MEM_FLAG_L1_NONALLOCATING = (MEM_FLAG_DIRECT | MEM_FLAG_COHERENT),
++
++ /*
++ If a MEM_HANDLE_T is zero'd, its contents are set to 0 rather than
++ MEM_HANDLE_INVALID on allocation and resize up.
++ */
++ MEM_FLAG_ZERO = 1 << 4,
++
++ /*
++ If a MEM_HANDLE_T is uninitialised, it will not be reset to a defined value
++ (either zero, or all 1's) on allocation.
++ */
++ MEM_FLAG_NO_INIT = 1 << 5,
++
++ /*
++ Hints.
++ */
++ MEM_FLAG_HINT_PERMALOCK = 1 << 6, /* Likely to be locked for long periods of time. */
++};
++
++unsigned int AllocateVcMemory(unsigned int *pHandle, unsigned int size, unsigned int alignment, unsigned int flags);
++unsigned int ReleaseVcMemory(unsigned int handle);
++unsigned int LockVcMemory(unsigned int *pBusAddress, unsigned int handle);
++unsigned int UnlockVcMemory(unsigned int handle);
++
++unsigned int ExecuteVcCode(unsigned int code,
++ unsigned int r0, unsigned int r1, unsigned int r2, unsigned int r3, unsigned int r4, unsigned int r5);
++
++#endif
+diff -Nur linux-4.1.3/arch/arm/mach-bcm2709/include/mach/vmalloc.h linux-xbian-rpi/arch/arm/mach-bcm2709/include/mach/vmalloc.h
+--- linux-4.1.3/arch/arm/mach-bcm2709/include/mach/vmalloc.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/mach-bcm2709/include/mach/vmalloc.h 2015-07-28 01:20:58.182095047 +0200
+@@ -0,0 +1,20 @@
++/*
++ * arch/arm/mach-bcm2708/include/mach/vmalloc.h
++ *
++ * Copyright (C) 2010 Broadcom
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++#define VMALLOC_END (0xff000000)
+diff -Nur linux-4.1.3/arch/arm/mach-bcm2709/Kconfig linux-xbian-rpi/arch/arm/mach-bcm2709/Kconfig
+--- linux-4.1.3/arch/arm/mach-bcm2709/Kconfig 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/mach-bcm2709/Kconfig 2015-07-28 01:20:58.170137709 +0200
+@@ -0,0 +1,42 @@
++menu "Broadcom BCM2709 Implementations"
++ depends on ARCH_BCM2709
++
++config MACH_BCM2709
++ bool "Broadcom BCM2709 Development Platform"
++ help
++ Include support for the Broadcom(R) BCM2709 platform.
++
++config BCM2709_DT
++ bool "BCM2709 Device Tree support"
++ depends on MACH_BCM2709
++ default n
++ select USE_OF
++ select ARCH_REQUIRE_GPIOLIB
++ select PINCTRL
++ select PINCTRL_BCM2835
++ help
++ Enable Device Tree support for BCM2709
++
++config BCM2708_GPIO
++ bool "BCM2709 gpio support"
++ depends on MACH_BCM2709
++ select ARCH_REQUIRE_GPIOLIB
++ default y
++ help
++ Include support for the Broadcom(R) BCM2709 gpio.
++
++config BCM2708_NOL2CACHE
++ bool "Videocore L2 cache disable"
++ depends on MACH_BCM2709
++ default y
++ help
++ Do not allow ARM to use GPU's L2 cache. Requires disable_l2cache in config.txt.
++
++config BCM2708_SPIDEV
++ bool "Bind spidev to SPI0 master"
++ depends on MACH_BCM2709
++ depends on SPI
++ default y
++ help
++ Binds spidev driver to the SPI0 master
++endmenu
+diff -Nur linux-4.1.3/arch/arm/mach-bcm2709/Makefile linux-xbian-rpi/arch/arm/mach-bcm2709/Makefile
+--- linux-4.1.3/arch/arm/mach-bcm2709/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/mach-bcm2709/Makefile 2015-07-28 01:20:58.170137709 +0200
+@@ -0,0 +1,6 @@
++#
++# Makefile for the linux kernel.
++#
++
++obj-$(CONFIG_MACH_BCM2709) += bcm2709.o armctrl.o
++obj-$(CONFIG_BCM2708_GPIO) += bcm2708_gpio.o
+diff -Nur linux-4.1.3/arch/arm/mach-bcm2709/Makefile.boot linux-xbian-rpi/arch/arm/mach-bcm2709/Makefile.boot
+--- linux-4.1.3/arch/arm/mach-bcm2709/Makefile.boot 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/mach-bcm2709/Makefile.boot 2015-07-28 01:20:58.170137709 +0200
+@@ -0,0 +1,3 @@
++ zreladdr-y := 0x00008000
++params_phys-y := 0x00000100
++initrd_phys-y := 0x00800000
+diff -Nur linux-4.1.3/arch/arm/mach-bcm2709/vc_support.c linux-xbian-rpi/arch/arm/mach-bcm2709/vc_support.c
+--- linux-4.1.3/arch/arm/mach-bcm2709/vc_support.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/arch/arm/mach-bcm2709/vc_support.c 2015-07-28 01:20:58.182095047 +0200
+@@ -0,0 +1,318 @@
++/*
++ * vc_support.c
++ *
++ * Created on: 25 Nov 2012
++ * Author: Simon
++ */
++
++#include <linux/module.h>
++#include <linux/platform_data/mailbox-bcm2708.h>
++
++#ifdef ECLIPSE_IGNORE
++
++#define __user
++#define __init
++#define __exit
++#define __iomem
++#define KERN_DEBUG
++#define KERN_ERR
++#define KERN_WARNING
++#define KERN_INFO
++#define _IOWR(a, b, c) b
++#define _IOW(a, b, c) b
++#define _IO(a, b) b
++
++#endif
++
++/****** VC MAILBOX FUNCTIONALITY ******/
++unsigned int AllocateVcMemory(unsigned int *pHandle, unsigned int size, unsigned int alignment, unsigned int flags)
++{
++ struct vc_msg
++ {
++ unsigned int m_msgSize;
++ unsigned int m_response;
++
++ struct vc_tag
++ {
++ unsigned int m_tagId;
++ unsigned int m_sendBufferSize;
++ union {
++ unsigned int m_sendDataSize;
++ unsigned int m_recvDataSize;
++ };
++
++ struct args
++ {
++ union {
++ unsigned int m_size;
++ unsigned int m_handle;
++ };
++ unsigned int m_alignment;
++ unsigned int m_flags;
++ } m_args;
++ } m_tag;
++
++ unsigned int m_endTag;
++ } msg;
++ int s;
++
++ msg.m_msgSize = sizeof(msg);
++ msg.m_response = 0;
++ msg.m_endTag = 0;
++
++ //fill in the tag for the allocation command
++ msg.m_tag.m_tagId = 0x3000c;
++ msg.m_tag.m_sendBufferSize = 12;
++ msg.m_tag.m_sendDataSize = 12;
++
++ //fill in our args
++ msg.m_tag.m_args.m_size = size;
++ msg.m_tag.m_args.m_alignment = alignment;
++ msg.m_tag.m_args.m_flags = flags;
++
++ //run the command
++ s = bcm_mailbox_property(&msg, sizeof(msg));
++
++ if (s == 0 && msg.m_response == 0x80000000 && msg.m_tag.m_recvDataSize == 0x80000004)
++ {
++ *pHandle = msg.m_tag.m_args.m_handle;
++ return 0;
++ }
++ else
++ {
++ printk(KERN_ERR "failed to allocate vc memory: s=%d response=%08x recv data size=%08x\n",
++ s, msg.m_response, msg.m_tag.m_recvDataSize);
++ return 1;
++ }
++}
++
++unsigned int ReleaseVcMemory(unsigned int handle)
++{
++ struct vc_msg
++ {
++ unsigned int m_msgSize;
++ unsigned int m_response;
++
++ struct vc_tag
++ {
++ unsigned int m_tagId;
++ unsigned int m_sendBufferSize;
++ union {
++ unsigned int m_sendDataSize;
++ unsigned int m_recvDataSize;
++ };
++
++ struct args
++ {
++ union {
++ unsigned int m_handle;
++ unsigned int m_error;
++ };
++ } m_args;
++ } m_tag;
++
++ unsigned int m_endTag;
++ } msg;
++ int s;
++
++ msg.m_msgSize = sizeof(msg);
++ msg.m_response = 0;
++ msg.m_endTag = 0;
++
++ //fill in the tag for the release command
++ msg.m_tag.m_tagId = 0x3000f;
++ msg.m_tag.m_sendBufferSize = 4;
++ msg.m_tag.m_sendDataSize = 4;
++
++ //pass across the handle
++ msg.m_tag.m_args.m_handle = handle;
++
++ s = bcm_mailbox_property(&msg, sizeof(msg));
++
++ if (s == 0 && msg.m_response == 0x80000000 && msg.m_tag.m_recvDataSize == 0x80000004 && msg.m_tag.m_args.m_error == 0)
++ return 0;
++ else
++ {
++ printk(KERN_ERR "failed to release vc memory: s=%d response=%08x recv data size=%08x error=%08x\n",
++ s, msg.m_response, msg.m_tag.m_recvDataSize, msg.m_tag.m_args.m_error);
++ return 1;
++ }
++}
++
++unsigned int LockVcMemory(unsigned int *pBusAddress, unsigned int handle)
++{
++ struct vc_msg
++ {
++ unsigned int m_msgSize;
++ unsigned int m_response;
++
++ struct vc_tag
++ {
++ unsigned int m_tagId;
++ unsigned int m_sendBufferSize;
++ union {
++ unsigned int m_sendDataSize;
++ unsigned int m_recvDataSize;
++ };
++
++ struct args
++ {
++ union {
++ unsigned int m_handle;
++ unsigned int m_busAddress;
++ };
++ } m_args;
++ } m_tag;
++
++ unsigned int m_endTag;
++ } msg;
++ int s;
++
++ msg.m_msgSize = sizeof(msg);
++ msg.m_response = 0;
++ msg.m_endTag = 0;
++
++ //fill in the tag for the lock command
++ msg.m_tag.m_tagId = 0x3000d;
++ msg.m_tag.m_sendBufferSize = 4;
++ msg.m_tag.m_sendDataSize = 4;
++
++ //pass across the handle
++ msg.m_tag.m_args.m_handle = handle;
++
++ s = bcm_mailbox_property(&msg, sizeof(msg));
++
++ if (s == 0 && msg.m_response == 0x80000000 && msg.m_tag.m_recvDataSize == 0x80000004)
++ {
++ //pick out the bus address
++ *pBusAddress = msg.m_tag.m_args.m_busAddress;
++ return 0;
++ }
++ else
++ {
++ printk(KERN_ERR "failed to lock vc memory: s=%d response=%08x recv data size=%08x\n",
++ s, msg.m_response, msg.m_tag.m_recvDataSize);
++ return 1;
++ }
++}
++
++unsigned int UnlockVcMemory(unsigned int handle)
++{
++ struct vc_msg
++ {
++ unsigned int m_msgSize;
++ unsigned int m_response;
++
++ struct vc_tag
++ {
++ unsigned int m_tagId;
++ unsigned int m_sendBufferSize;
++ union {
++ unsigned int m_sendDataSize;
++ unsigned int m_recvDataSize;
++ };
++
++ struct args
++ {
++ union {
++ unsigned int m_handle;
++ unsigned int m_error;
++ };
++ } m_args;
++ } m_tag;
++
++ unsigned int m_endTag;
++ } msg;
++ int s;
++
++ msg.m_msgSize = sizeof(msg);
++ msg.m_response = 0;
++ msg.m_endTag = 0;
++
++ //fill in the tag for the unlock command
++ msg.m_tag.m_tagId = 0x3000e;
++ msg.m_tag.m_sendBufferSize = 4;
++ msg.m_tag.m_sendDataSize = 4;
++
++ //pass across the handle
++ msg.m_tag.m_args.m_handle = handle;
++
++ s = bcm_mailbox_property(&msg, sizeof(msg));
++
++ //check the error code too
++ if (s == 0 && msg.m_response == 0x80000000 && msg.m_tag.m_recvDataSize == 0x80000004 && msg.m_tag.m_args.m_error == 0)
++ return 0;
++ else
++ {
++ printk(KERN_ERR "failed to unlock vc memory: s=%d response=%08x recv data size=%08x error%08x\n",
++ s, msg.m_response, msg.m_tag.m_recvDataSize, msg.m_tag.m_args.m_error);
++ return 1;
++ }
++}
++
++unsigned int ExecuteVcCode(unsigned int code,
++ unsigned int r0, unsigned int r1, unsigned int r2, unsigned int r3, unsigned int r4, unsigned int r5)
++{
++ struct vc_msg
++ {
++ unsigned int m_msgSize;
++ unsigned int m_response;
++
++ struct vc_tag
++ {
++ unsigned int m_tagId;
++ unsigned int m_sendBufferSize;
++ union {
++ unsigned int m_sendDataSize;
++ unsigned int m_recvDataSize;
++ };
++
++ struct args
++ {
++ union {
++ unsigned int m_pCode;
++ unsigned int m_return;
++ };
++ unsigned int m_r0;
++ unsigned int m_r1;
++ unsigned int m_r2;
++ unsigned int m_r3;
++ unsigned int m_r4;
++ unsigned int m_r5;
++ } m_args;
++ } m_tag;
++
++ unsigned int m_endTag;
++ } msg;
++ int s;
++
++ msg.m_msgSize = sizeof(msg);
++ msg.m_response = 0;
++ msg.m_endTag = 0;
++
++ //fill in the tag for the unlock command
++ msg.m_tag.m_tagId = 0x30010;
++ msg.m_tag.m_sendBufferSize = 28;
++ msg.m_tag.m_sendDataSize = 28;
++
++ //pass across the handle
++ msg.m_tag.m_args.m_pCode = code;
++ msg.m_tag.m_args.m_r0 = r0;
++ msg.m_tag.m_args.m_r1 = r1;
++ msg.m_tag.m_args.m_r2 = r2;
++ msg.m_tag.m_args.m_r3 = r3;
++ msg.m_tag.m_args.m_r4 = r4;
++ msg.m_tag.m_args.m_r5 = r5;
++
++ s = bcm_mailbox_property(&msg, sizeof(msg));
++
++ //check the error code too
++ if (s == 0 && msg.m_response == 0x80000000 && msg.m_tag.m_recvDataSize == 0x80000004)
++ return msg.m_tag.m_args.m_return;
++ else
++ {
++ printk(KERN_ERR "failed to execute: s=%d response=%08x recv data size=%08x\n",
++ s, msg.m_response, msg.m_tag.m_recvDataSize);
++ return 1;
++ }
++}
+diff -Nur linux-4.1.3/arch/arm/Makefile linux-xbian-rpi/arch/arm/Makefile
+--- linux-4.1.3/arch/arm/Makefile 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/arch/arm/Makefile 2015-07-28 01:20:58.162166151 +0200
+@@ -142,6 +142,8 @@
+
+ # Machine directory name. This list is sorted alphanumerically
+ # by CONFIG_* macro name.
++machine-$(CONFIG_ARCH_BCM2708) += bcm2708
++machine-$(CONFIG_ARCH_BCM2709) += bcm2709
+ machine-$(CONFIG_ARCH_ALPINE) += alpine
+ machine-$(CONFIG_ARCH_AT91) += at91
+ machine-$(CONFIG_ARCH_AXXIA) += axxia
+diff -Nur linux-4.1.3/arch/arm/mm/Kconfig linux-xbian-rpi/arch/arm/mm/Kconfig
+--- linux-4.1.3/arch/arm/mm/Kconfig 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/arch/arm/mm/Kconfig 2015-07-28 01:20:58.186080826 +0200
+@@ -358,7 +358,7 @@
+
+ # ARMv6
+ config CPU_V6
+- bool "Support ARM V6 processor" if (!ARCH_MULTIPLATFORM || ARCH_MULTI_V6) && (ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX)
++ bool "Support ARM V6 processor" if (!ARCH_MULTIPLATFORM || ARCH_MULTI_V6) && (ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX || MACH_BCM2708)
+ select CPU_32v6
+ select CPU_ABRT_EV6
+ select CPU_CACHE_V6
+diff -Nur linux-4.1.3/arch/arm/mm/proc-v6.S linux-xbian-rpi/arch/arm/mm/proc-v6.S
+--- linux-4.1.3/arch/arm/mm/proc-v6.S 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/arch/arm/mm/proc-v6.S 2015-07-28 01:20:58.186080826 +0200
+@@ -73,10 +73,19 @@
+ *
+ * IRQs are already disabled.
+ */
++
++/* See jira SW-5991 for details of this workaround */
+ ENTRY(cpu_v6_do_idle)
+- mov r1, #0
+- mcr p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode
+- mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt
++ .align 5
++ mov r1, #2
++1: subs r1, #1
++ nop
++ mcreq p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode
++ mcreq p15, 0, r1, c7, c0, 4 @ wait for interrupt
++ nop
++ nop
++ nop
++ bne 1b
+ ret lr
+
+ ENTRY(cpu_v6_dcache_clean_area)
+diff -Nur linux-4.1.3/arch/arm/mm/proc-v7.S linux-xbian-rpi/arch/arm/mm/proc-v7.S
+--- linux-4.1.3/arch/arm/mm/proc-v7.S 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/arch/arm/mm/proc-v7.S 2015-07-28 01:20:58.186080826 +0200
+@@ -456,6 +456,7 @@
+ orr r0, r0, r6 @ set them
+ THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions
+ ret lr @ return to head.S:__ret
++ .space 256
+ ENDPROC(__v7_setup)
+
+ .align 2
+diff -Nur linux-4.1.3/arch/arm/tools/mach-types linux-xbian-rpi/arch/arm/tools/mach-types
+--- linux-4.1.3/arch/arm/tools/mach-types 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/arch/arm/tools/mach-types 2015-07-28 01:20:58.186080826 +0200
+@@ -522,6 +522,8 @@
+ prima2_evb MACH_PRIMA2_EVB PRIMA2_EVB 3103
+ paz00 MACH_PAZ00 PAZ00 3128
+ acmenetusfoxg20 MACH_ACMENETUSFOXG20 ACMENETUSFOXG20 3129
++bcm2708 MACH_BCM2708 BCM2708 3138
++bcm2709 MACH_BCM2709 BCM2709 3139
+ ag5evm MACH_AG5EVM AG5EVM 3189
+ ics_if_voip MACH_ICS_IF_VOIP ICS_IF_VOIP 3206
+ wlf_cragg_6410 MACH_WLF_CRAGG_6410 WLF_CRAGG_6410 3207
+diff -Nur linux-4.1.3/Documentation/ABI/stable/sysfs-driver-w1_ds28ea00 linux-xbian-rpi/Documentation/ABI/stable/sysfs-driver-w1_ds28ea00
+--- linux-4.1.3/Documentation/ABI/stable/sysfs-driver-w1_ds28ea00 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/Documentation/ABI/stable/sysfs-driver-w1_ds28ea00 2015-07-28 01:20:58.162166151 +0200
+@@ -0,0 +1,6 @@
++What: /sys/bus/w1/devices/.../w1_seq
++Date: Apr 2015
++Contact: Matt Campbell <mattrcampbell@gmail.com>
++Description: Support for the DS28EA00 chain sequence function
++ see Documentation/w1/slaves/w1_therm for detailed information
++Users: any user space application which wants to communicate with DS28EA00
+diff -Nur linux-4.1.3/Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt linux-xbian-rpi/Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt
+--- linux-4.1.3/Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt 2015-07-28 01:20:58.162166151 +0200
+@@ -48,8 +48,8 @@
+
+ bcm2835_i2s: i2s@7e203000 {
+ compatible = "brcm,bcm2835-i2s";
+- reg = < 0x7e203000 0x20>,
+- < 0x7e101098 0x02>;
++ reg = < 0x7e203000 0x24>,
++ < 0x7e101098 0x08>;
+
+ dmas = <&dma 2>,
+ <&dma 3>;
+diff -Nur linux-4.1.3/Documentation/devicetree/bindings/sound/brcm,bcm2835-i2s.txt linux-xbian-rpi/Documentation/devicetree/bindings/sound/brcm,bcm2835-i2s.txt
+--- linux-4.1.3/Documentation/devicetree/bindings/sound/brcm,bcm2835-i2s.txt 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/Documentation/devicetree/bindings/sound/brcm,bcm2835-i2s.txt 2015-07-28 01:20:58.162166151 +0200
+@@ -16,8 +16,8 @@
+
+ bcm2835_i2s: i2s@7e203000 {
+ compatible = "brcm,bcm2835-i2s";
+- reg = <0x7e203000 0x20>,
+- <0x7e101098 0x02>;
++ reg = <0x7e203000 0x24>,
++ <0x7e101098 0x08>;
+
+ dmas = <&dma 2>,
+ <&dma 3>;
+diff -Nur linux-4.1.3/Documentation/video4linux/bcm2835-v4l2.txt linux-xbian-rpi/Documentation/video4linux/bcm2835-v4l2.txt
+--- linux-4.1.3/Documentation/video4linux/bcm2835-v4l2.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/Documentation/video4linux/bcm2835-v4l2.txt 2015-07-28 01:20:58.162166151 +0200
+@@ -0,0 +1,60 @@
++
++BCM2835 (aka Raspberry Pi) V4L2 driver
++======================================
++
++1. Copyright
++============
++
++Copyright © 2013 Raspberry Pi (Trading) Ltd.
++
++2. License
++==========
++
++This program is free software; you can redistribute it and/or modify
++it under the terms of the GNU General Public License as published by
++the Free Software Foundation; either version 2 of the License, or
++(at your option) any later version.
++
++This program is distributed in the hope that it will be useful,
++but WITHOUT ANY WARRANTY; without even the implied warranty of
++MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++GNU General Public License for more details.
++
++You should have received a copy of the GNU General Public License
++along with this program; if not, write to the Free Software
++Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++
++3. Quick Start
++==============
++
++You need a version 1.0 or later of v4l2-ctl, available from:
++ git://git.linuxtv.org/v4l-utils.git
++
++$ sudo modprobe bcm2835-v4l2
++
++Turn on the overlay:
++
++$ v4l2-ctl --overlay=1
++
++Turn off the overlay:
++
++$ v4l2-ctl --overlay=0
++
++Set the capture format for video:
++
++$ v4l2-ctl --set-fmt-video=width=1920,height=1088,pixelformat=4
++
++(Note: 1088 not 1080).
++
++Capture:
++
++$ v4l2-ctl --stream-mmap=3 --stream-count=100 --stream-to=somefile.h264
++
++Stills capture:
++
++$ v4l2-ctl --set-fmt-video=width=2592,height=1944,pixelformat=3
++$ v4l2-ctl --stream-mmap=3 --stream-count=1 --stream-to=somefile.jpg
++
++List of available formats:
++
++$ v4l2-ctl --list-formats
+diff -Nur linux-4.1.3/Documentation/w1/slaves/w1_therm linux-xbian-rpi/Documentation/w1/slaves/w1_therm
+--- linux-4.1.3/Documentation/w1/slaves/w1_therm 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/Documentation/w1/slaves/w1_therm 2015-07-28 01:20:58.162166151 +0200
+@@ -11,12 +11,14 @@
+ Description
+ -----------
+
+-w1_therm provides basic temperature conversion for ds18*20 devices.
++w1_therm provides basic temperature conversion for ds18*20 devices, and the
++ds28ea00 device.
+ supported family codes:
+ W1_THERM_DS18S20 0x10
+ W1_THERM_DS1822 0x22
+ W1_THERM_DS18B20 0x28
+ W1_THERM_DS1825 0x3B
++W1_THERM_DS28EA00 0x42
+
+ Support is provided through the sysfs w1_slave file. Each open and
+ read sequence will initiate a temperature conversion then provide two
+@@ -48,3 +50,10 @@
+ maximum current draw of 1.5mA and that a 5k pullup resistor is not
+ sufficient. The strong pullup is designed to provide the additional
+ current required.
++
++The DS28EA00 provides an additional two pins for implementing a sequence
++detection algorithm. This feature allows you to determine the physical
++location of the chip in the 1-wire bus without needing pre-existing
++knowledge of the bus ordering. Support is provided through the sysfs
++w1_seq file. The file will contain a single line with an integer value
++representing the device index in the bus starting at 0.
+diff -Nur linux-4.1.3/drivers/char/broadcom/Kconfig linux-xbian-rpi/drivers/char/broadcom/Kconfig
+--- linux-4.1.3/drivers/char/broadcom/Kconfig 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/char/broadcom/Kconfig 2015-07-28 01:20:58.186080826 +0200
+@@ -0,0 +1,40 @@
++#
++# Broadcom char driver config
++#
++
++menuconfig BRCM_CHAR_DRIVERS
++ bool "Broadcom Char Drivers"
++ help
++ Broadcom's char drivers
++
++if BRCM_CHAR_DRIVERS
++
++config BCM_VC_CMA
++ bool "Videocore CMA"
++ depends on CMA && BCM2708_VCHIQ
++ default n
++ help
++ Helper for videocore CMA access.
++
++config BCM2708_VCMEM
++ bool "Videocore Memory"
++ default y
++ help
++ Helper for videocore memory access and total size allocation.
++
++config BCM_VCIO
++ tristate "Mailbox userspace access"
++ depends on BCM2835_MBOX
++ help
++ Gives access to the mailbox property channel from userspace.
++
++endif
++
++config BCM_VC_SM
++ bool "VMCS Shared Memory"
++ depends on BCM2708_VCHIQ
++ select BCM2708_VCMEM
++ default n
++ help
++ Support for the VC shared memory on the Broadcom reference
++ design. Uses the VCHIQ stack.
+diff -Nur linux-4.1.3/drivers/char/broadcom/Makefile linux-xbian-rpi/drivers/char/broadcom/Makefile
+--- linux-4.1.3/drivers/char/broadcom/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/char/broadcom/Makefile 2015-07-28 01:20:58.186080826 +0200
+@@ -0,0 +1,4 @@
++obj-$(CONFIG_BCM_VC_CMA) += vc_cma/
++obj-$(CONFIG_BCM2708_VCMEM) += vc_mem.o
++obj-$(CONFIG_BCM_VCIO) += vcio.o
++obj-$(CONFIG_BCM_VC_SM) += vc_sm/
+diff -Nur linux-4.1.3/drivers/char/broadcom/vc_cma/Makefile linux-xbian-rpi/drivers/char/broadcom/vc_cma/Makefile
+--- linux-4.1.3/drivers/char/broadcom/vc_cma/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/char/broadcom/vc_cma/Makefile 2015-07-28 01:20:58.186080826 +0200
+@@ -0,0 +1,14 @@
++ccflags-y += -Wall -Wstrict-prototypes -Wno-trigraphs
++ccflags-y += -Werror
++ccflags-y += -Iinclude/linux/broadcom
++ccflags-y += -Idrivers/misc/vc04_services
++ccflags-y += -Idrivers/misc/vc04_services/interface/vchi
++ccflags-y += -Idrivers/misc/vc04_services/interface/vchiq_arm
++
++ccflags-y += -D__KERNEL__
++ccflags-y += -D__linux__
++ccflags-y += -Werror
++
++obj-$(CONFIG_BCM_VC_CMA) += vc-cma.o
++
++vc-cma-objs := vc_cma.o
+diff -Nur linux-4.1.3/drivers/char/broadcom/vc_cma/vc_cma.c linux-xbian-rpi/drivers/char/broadcom/vc_cma/vc_cma.c
+--- linux-4.1.3/drivers/char/broadcom/vc_cma/vc_cma.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/char/broadcom/vc_cma/vc_cma.c 2015-07-28 01:20:58.186080826 +0200
+@@ -0,0 +1,1193 @@
++/**
++ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ * 1. Redistributions of source code must retain the above copyright
++ * notice, this list of conditions, and the following disclaimer,
++ * without modification.
++ * 2. Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * 3. The names of the above-listed copyright holders may not be used
++ * to endorse or promote products derived from this software without
++ * specific prior written permission.
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") version 2, as published by the Free
++ * Software Foundation.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/kthread.h>
++#include <linux/fs.h>
++#include <linux/device.h>
++#include <linux/cdev.h>
++#include <linux/mm.h>
++#include <linux/proc_fs.h>
++#include <linux/seq_file.h>
++#include <linux/dma-mapping.h>
++#include <linux/dma-contiguous.h>
++#include <linux/platform_device.h>
++#include <linux/uaccess.h>
++#include <asm/cacheflush.h>
++
++#include "vc_cma.h"
++
++#include "vchiq_util.h"
++#include "vchiq_connected.h"
++//#include "debug_sym.h"
++//#include "vc_mem.h"
++
++#define DRIVER_NAME "vc-cma"
++
++#define LOG_DBG(fmt, ...) \
++ if (vc_cma_debug) \
++ printk(KERN_INFO fmt "\n", ##__VA_ARGS__)
++#define LOG_INFO(fmt, ...) \
++ printk(KERN_INFO fmt "\n", ##__VA_ARGS__)
++#define LOG_ERR(fmt, ...) \
++ printk(KERN_ERR fmt "\n", ##__VA_ARGS__)
++
++#define VC_CMA_FOURCC VCHIQ_MAKE_FOURCC('C', 'M', 'A', ' ')
++#define VC_CMA_VERSION 2
++
++#define VC_CMA_CHUNK_ORDER 6 /* 256K */
++#define VC_CMA_CHUNK_SIZE (4096 << VC_CMA_CHUNK_ORDER)
++#define VC_CMA_MAX_PARAMS_PER_MSG \
++ ((VCHIQ_MAX_MSG_SIZE - sizeof(unsigned short))/sizeof(unsigned short))
++#define VC_CMA_RESERVE_COUNT_MAX 16
++
++#define PAGES_PER_CHUNK (VC_CMA_CHUNK_SIZE / PAGE_SIZE)
++
++#define VCADDR_TO_PHYSADDR(vcaddr) (mm_vc_mem_phys_addr + vcaddr)
++
++#define loud_error(...) \
++ LOG_ERR("===== " __VA_ARGS__)
++
++enum {
++ VC_CMA_MSG_QUIT,
++ VC_CMA_MSG_OPEN,
++ VC_CMA_MSG_TICK,
++ VC_CMA_MSG_ALLOC, /* chunk count */
++ VC_CMA_MSG_FREE, /* chunk, chunk, ... */
++ VC_CMA_MSG_ALLOCATED, /* chunk, chunk, ... */
++ VC_CMA_MSG_REQUEST_ALLOC, /* chunk count */
++ VC_CMA_MSG_REQUEST_FREE, /* chunk count */
++ VC_CMA_MSG_RESERVE, /* bytes lo, bytes hi */
++ VC_CMA_MSG_UPDATE_RESERVE,
++ VC_CMA_MSG_MAX
++};
++
++struct cma_msg {
++ unsigned short type;
++ unsigned short params[VC_CMA_MAX_PARAMS_PER_MSG];
++};
++
++struct vc_cma_reserve_user {
++ unsigned int pid;
++ unsigned int reserve;
++};
++
++/* Device (/dev) related variables */
++static dev_t vc_cma_devnum;
++static struct class *vc_cma_class;
++static struct cdev vc_cma_cdev;
++static int vc_cma_inited;
++static int vc_cma_debug;
++
++/* Proc entry */
++static struct proc_dir_entry *vc_cma_proc_entry;
++
++phys_addr_t vc_cma_base;
++struct page *vc_cma_base_page;
++unsigned int vc_cma_size;
++EXPORT_SYMBOL(vc_cma_size);
++unsigned int vc_cma_initial;
++unsigned int vc_cma_chunks;
++unsigned int vc_cma_chunks_used;
++unsigned int vc_cma_chunks_reserved;
++
++
++void *vc_cma_dma_alloc;
++unsigned int vc_cma_dma_size;
++
++static int in_loud_error;
++
++unsigned int vc_cma_reserve_total;
++unsigned int vc_cma_reserve_count;
++struct vc_cma_reserve_user vc_cma_reserve_users[VC_CMA_RESERVE_COUNT_MAX];
++static DEFINE_SEMAPHORE(vc_cma_reserve_mutex);
++static DEFINE_SEMAPHORE(vc_cma_worker_queue_push_mutex);
++
++static u64 vc_cma_dma_mask = DMA_BIT_MASK(32);
++static struct platform_device vc_cma_device = {
++ .name = "vc-cma",
++ .id = 0,
++ .dev = {
++ .dma_mask = &vc_cma_dma_mask,
++ .coherent_dma_mask = DMA_BIT_MASK(32),
++ },
++};
++
++static VCHIQ_INSTANCE_T cma_instance;
++static VCHIQ_SERVICE_HANDLE_T cma_service;
++static VCHIU_QUEUE_T cma_msg_queue;
++static struct task_struct *cma_worker;
++
++static int vc_cma_set_reserve(unsigned int reserve, unsigned int pid);
++static int vc_cma_alloc_chunks(int num_chunks, struct cma_msg *reply);
++static VCHIQ_STATUS_T cma_service_callback(VCHIQ_REASON_T reason,
++ VCHIQ_HEADER_T * header,
++ VCHIQ_SERVICE_HANDLE_T service,
++ void *bulk_userdata);
++static void send_vc_msg(unsigned short type,
++ unsigned short param1, unsigned short param2);
++static bool send_worker_msg(VCHIQ_HEADER_T * msg);
++
++static int early_vc_cma_mem(char *p)
++{
++ unsigned int new_size;
++ printk(KERN_NOTICE "early_vc_cma_mem(%s)", p);
++ vc_cma_size = memparse(p, &p);
++ vc_cma_initial = vc_cma_size;
++ if (*p == '/')
++ vc_cma_size = memparse(p + 1, &p);
++ if (*p == '@')
++ vc_cma_base = memparse(p + 1, &p);
++
++ new_size = (vc_cma_size - ((-vc_cma_base) & (VC_CMA_CHUNK_SIZE - 1)))
++ & ~(VC_CMA_CHUNK_SIZE - 1);
++ if (new_size > vc_cma_size)
++ vc_cma_size = 0;
++ vc_cma_initial = (vc_cma_initial + VC_CMA_CHUNK_SIZE - 1)
++ & ~(VC_CMA_CHUNK_SIZE - 1);
++ if (vc_cma_initial > vc_cma_size)
++ vc_cma_initial = vc_cma_size;
++ vc_cma_base = (vc_cma_base + VC_CMA_CHUNK_SIZE - 1)
++ & ~(VC_CMA_CHUNK_SIZE - 1);
++
++ printk(KERN_NOTICE " -> initial %x, size %x, base %x", vc_cma_initial,
++ vc_cma_size, (unsigned int)vc_cma_base);
++
++ return 0;
++}
++
++early_param("vc-cma-mem", early_vc_cma_mem);
++
++void vc_cma_early_init(void)
++{
++ LOG_DBG("vc_cma_early_init - vc_cma_chunks = %d", vc_cma_chunks);
++ if (vc_cma_size) {
++ int rc = platform_device_register(&vc_cma_device);
++ LOG_DBG("platform_device_register -> %d", rc);
++ }
++}
++
++void vc_cma_reserve(void)
++{
++ /* if vc_cma_size is set, then declare vc CMA area of the same
++ * size from the end of memory
++ */
++ if (vc_cma_size) {
++ if (dma_declare_contiguous(&vc_cma_device.dev, vc_cma_size,
++ vc_cma_base, 0) == 0) {
++ if (!dev_get_cma_area(NULL)) {
++ /* There is no default CMA area - make this
++ the default */
++ struct cma *vc_cma_area = dev_get_cma_area(
++ &vc_cma_device.dev);
++ dma_contiguous_set_default(vc_cma_area);
++ LOG_INFO("vc_cma_reserve - using vc_cma as "
++ "the default contiguous DMA area");
++ }
++ } else {
++ LOG_ERR("vc_cma: dma_declare_contiguous(%x,%x) failed",
++ vc_cma_size, (unsigned int)vc_cma_base);
++ vc_cma_size = 0;
++ }
++ }
++ vc_cma_chunks = vc_cma_size / VC_CMA_CHUNK_SIZE;
++}
++
++/****************************************************************************
++*
++* vc_cma_open
++*
++***************************************************************************/
++
++static int vc_cma_open(struct inode *inode, struct file *file)
++{
++ (void)inode;
++ (void)file;
++
++ return 0;
++}
++
++/****************************************************************************
++*
++* vc_cma_release
++*
++***************************************************************************/
++
++static int vc_cma_release(struct inode *inode, struct file *file)
++{
++ (void)inode;
++ (void)file;
++
++ vc_cma_set_reserve(0, current->tgid);
++
++ return 0;
++}
++
++/****************************************************************************
++*
++* vc_cma_ioctl
++*
++***************************************************************************/
++
++static long vc_cma_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
++{
++ int rc = 0;
++
++ (void)cmd;
++ (void)arg;
++
++ switch (cmd) {
++ case VC_CMA_IOC_RESERVE:
++ rc = vc_cma_set_reserve((unsigned int)arg, current->tgid);
++ if (rc >= 0)
++ rc = 0;
++ break;
++ default:
++ LOG_ERR("vc-cma: Unknown ioctl %x", cmd);
++ return -ENOTTY;
++ }
++
++ return rc;
++}
++
++/****************************************************************************
++*
++* File Operations for the driver.
++*
++***************************************************************************/
++
++static const struct file_operations vc_cma_fops = {
++ .owner = THIS_MODULE,
++ .open = vc_cma_open,
++ .release = vc_cma_release,
++ .unlocked_ioctl = vc_cma_ioctl,
++};
++
++/****************************************************************************
++*
++* vc_cma_proc_open
++*
++***************************************************************************/
++
++static int vc_cma_show_info(struct seq_file *m, void *v)
++{
++ int i;
++
++ seq_printf(m, "Videocore CMA:\n");
++ seq_printf(m, " Base : %08x\n", (unsigned int)vc_cma_base);
++ seq_printf(m, " Length : %08x\n", vc_cma_size);
++ seq_printf(m, " Initial : %08x\n", vc_cma_initial);
++ seq_printf(m, " Chunk size : %08x\n", VC_CMA_CHUNK_SIZE);
++ seq_printf(m, " Chunks : %4d (%d bytes)\n",
++ (int)vc_cma_chunks,
++ (int)(vc_cma_chunks * VC_CMA_CHUNK_SIZE));
++ seq_printf(m, " Used : %4d (%d bytes)\n",
++ (int)vc_cma_chunks_used,
++ (int)(vc_cma_chunks_used * VC_CMA_CHUNK_SIZE));
++ seq_printf(m, " Reserved : %4d (%d bytes)\n",
++ (unsigned int)vc_cma_chunks_reserved,
++ (int)(vc_cma_chunks_reserved * VC_CMA_CHUNK_SIZE));
++
++ for (i = 0; i < vc_cma_reserve_count; i++) {
++ struct vc_cma_reserve_user *user = &vc_cma_reserve_users[i];
++ seq_printf(m, " PID %5d: %d bytes\n", user->pid,
++ user->reserve);
++ }
++ seq_printf(m, " dma_alloc : %p (%d pages)\n",
++ vc_cma_dma_alloc ? page_address(vc_cma_dma_alloc) : 0,
++ vc_cma_dma_size);
++
++ seq_printf(m, "\n");
++
++ return 0;
++}
++
++static int vc_cma_proc_open(struct inode *inode, struct file *file)
++{
++ return single_open(file, vc_cma_show_info, NULL);
++}
++
++/****************************************************************************
++*
++* vc_cma_proc_write
++*
++***************************************************************************/
++
++static int vc_cma_proc_write(struct file *file,
++ const char __user *buffer,
++ size_t size, loff_t *ppos)
++{
++ int rc = -EFAULT;
++ char input_str[20];
++
++ memset(input_str, 0, sizeof(input_str));
++
++ if (size > sizeof(input_str)) {
++ LOG_ERR("%s: input string length too long", __func__);
++ goto out;
++ }
++
++ if (copy_from_user(input_str, buffer, size - 1)) {
++ LOG_ERR("%s: failed to get input string", __func__);
++ goto out;
++ }
++#define ALLOC_STR "alloc"
++#define FREE_STR "free"
++#define DEBUG_STR "debug"
++#define RESERVE_STR "reserve"
++#define DMA_ALLOC_STR "dma_alloc"
++#define DMA_FREE_STR "dma_free"
++ if (strncmp(input_str, ALLOC_STR, strlen(ALLOC_STR)) == 0) {
++ int alloc_size;
++ char *p = input_str + strlen(ALLOC_STR);
++
++ while (*p == ' ')
++ p++;
++ alloc_size = memparse(p, NULL);
++ LOG_INFO("/proc/vc-cma: alloc %d", alloc_size);
++ if (alloc_size)
++ send_vc_msg(VC_CMA_MSG_REQUEST_FREE,
++ alloc_size / VC_CMA_CHUNK_SIZE, 0);
++ else
++ LOG_ERR("invalid size '%s'", p);
++ rc = size;
++ } else if (strncmp(input_str, FREE_STR, strlen(FREE_STR)) == 0) {
++ int alloc_size;
++ char *p = input_str + strlen(FREE_STR);
++
++ while (*p == ' ')
++ p++;
++ alloc_size = memparse(p, NULL);
++ LOG_INFO("/proc/vc-cma: free %d", alloc_size);
++ if (alloc_size)
++ send_vc_msg(VC_CMA_MSG_REQUEST_ALLOC,
++ alloc_size / VC_CMA_CHUNK_SIZE, 0);
++ else
++ LOG_ERR("invalid size '%s'", p);
++ rc = size;
++ } else if (strncmp(input_str, DEBUG_STR, strlen(DEBUG_STR)) == 0) {
++ char *p = input_str + strlen(DEBUG_STR);
++ while (*p == ' ')
++ p++;
++ if ((strcmp(p, "on") == 0) || (strcmp(p, "1") == 0))
++ vc_cma_debug = 1;
++ else if ((strcmp(p, "off") == 0) || (strcmp(p, "0") == 0))
++ vc_cma_debug = 0;
++ LOG_INFO("/proc/vc-cma: debug %s", vc_cma_debug ? "on" : "off");
++ rc = size;
++ } else if (strncmp(input_str, RESERVE_STR, strlen(RESERVE_STR)) == 0) {
++ int alloc_size;
++ int reserved;
++ char *p = input_str + strlen(RESERVE_STR);
++ while (*p == ' ')
++ p++;
++ alloc_size = memparse(p, NULL);
++
++ reserved = vc_cma_set_reserve(alloc_size, current->tgid);
++ rc = (reserved >= 0) ? size : reserved;
++ } else if (strncmp(input_str, DMA_ALLOC_STR, strlen(DMA_ALLOC_STR)) == 0) {
++ int alloc_size;
++ char *p = input_str + strlen(DMA_ALLOC_STR);
++ while (*p == ' ')
++ p++;
++ alloc_size = memparse(p, NULL);
++
++ if (vc_cma_dma_alloc) {
++ dma_release_from_contiguous(NULL, vc_cma_dma_alloc,
++ vc_cma_dma_size);
++ vc_cma_dma_alloc = NULL;
++ vc_cma_dma_size = 0;
++ }
++ vc_cma_dma_alloc = dma_alloc_from_contiguous(NULL, alloc_size, 0);
++ vc_cma_dma_size = (vc_cma_dma_alloc ? alloc_size : 0);
++ if (vc_cma_dma_alloc)
++ LOG_INFO("dma_alloc(%d pages) -> %p", alloc_size, page_address(vc_cma_dma_alloc));
++ else
++ LOG_ERR("dma_alloc(%d pages) failed", alloc_size);
++ rc = size;
++ } else if (strncmp(input_str, DMA_FREE_STR, strlen(DMA_FREE_STR)) == 0) {
++ if (vc_cma_dma_alloc) {
++ dma_release_from_contiguous(NULL, vc_cma_dma_alloc,
++ vc_cma_dma_size);
++ vc_cma_dma_alloc = NULL;
++ vc_cma_dma_size = 0;
++ }
++ rc = size;
++ }
++
++out:
++ return rc;
++}
++
++/****************************************************************************
++*
++* File Operations for /proc interface.
++*
++***************************************************************************/
++
++static const struct file_operations vc_cma_proc_fops = {
++ .open = vc_cma_proc_open,
++ .read = seq_read,
++ .write = vc_cma_proc_write,
++ .llseek = seq_lseek,
++ .release = single_release
++};
++
++static int vc_cma_set_reserve(unsigned int reserve, unsigned int pid)
++{
++ struct vc_cma_reserve_user *user = NULL;
++ int delta = 0;
++ int i;
++
++ if (down_interruptible(&vc_cma_reserve_mutex))
++ return -ERESTARTSYS;
++
++ for (i = 0; i < vc_cma_reserve_count; i++) {
++ if (pid == vc_cma_reserve_users[i].pid) {
++ user = &vc_cma_reserve_users[i];
++ delta = reserve - user->reserve;
++ if (reserve)
++ user->reserve = reserve;
++ else {
++ /* Remove this entry by copying downwards */
++ while ((i + 1) < vc_cma_reserve_count) {
++ user[0].pid = user[1].pid;
++ user[0].reserve = user[1].reserve;
++ user++;
++ i++;
++ }
++ vc_cma_reserve_count--;
++ user = NULL;
++ }
++ break;
++ }
++ }
++
++ if (reserve && !user) {
++ if (vc_cma_reserve_count == VC_CMA_RESERVE_COUNT_MAX) {
++ LOG_ERR("vc-cma: Too many reservations - "
++ "increase CMA_RESERVE_COUNT_MAX");
++ up(&vc_cma_reserve_mutex);
++ return -EBUSY;
++ }
++ user = &vc_cma_reserve_users[vc_cma_reserve_count];
++ user->pid = pid;
++ user->reserve = reserve;
++ delta = reserve;
++ vc_cma_reserve_count++;
++ }
++
++ vc_cma_reserve_total += delta;
++
++ send_vc_msg(VC_CMA_MSG_RESERVE,
++ vc_cma_reserve_total & 0xffff, vc_cma_reserve_total >> 16);
++
++ send_worker_msg((VCHIQ_HEADER_T *) VC_CMA_MSG_UPDATE_RESERVE);
++
++ LOG_DBG("/proc/vc-cma: reserve %d (PID %d) - total %u",
++ reserve, pid, vc_cma_reserve_total);
++
++ up(&vc_cma_reserve_mutex);
++
++ return vc_cma_reserve_total;
++}
++
++static VCHIQ_STATUS_T cma_service_callback(VCHIQ_REASON_T reason,
++ VCHIQ_HEADER_T * header,
++ VCHIQ_SERVICE_HANDLE_T service,
++ void *bulk_userdata)
++{
++ switch (reason) {
++ case VCHIQ_MESSAGE_AVAILABLE:
++ if (!send_worker_msg(header))
++ return VCHIQ_RETRY;
++ break;
++ case VCHIQ_SERVICE_CLOSED:
++ LOG_DBG("CMA service closed");
++ break;
++ default:
++ LOG_ERR("Unexpected CMA callback reason %d", reason);
++ break;
++ }
++ return VCHIQ_SUCCESS;
++}
++
++static void send_vc_msg(unsigned short type,
++ unsigned short param1, unsigned short param2)
++{
++ unsigned short msg[] = { type, param1, param2 };
++ VCHIQ_ELEMENT_T elem = { &msg, sizeof(msg) };
++ VCHIQ_STATUS_T ret;
++ vchiq_use_service(cma_service);
++ ret = vchiq_queue_message(cma_service, &elem, 1);
++ vchiq_release_service(cma_service);
++ if (ret != VCHIQ_SUCCESS)
++ LOG_ERR("vchiq_queue_message returned %x", ret);
++}
++
++static bool send_worker_msg(VCHIQ_HEADER_T * msg)
++{
++ if (down_interruptible(&vc_cma_worker_queue_push_mutex))
++ return false;
++ vchiu_queue_push(&cma_msg_queue, msg);
++ up(&vc_cma_worker_queue_push_mutex);
++ return true;
++}
++
++static int vc_cma_alloc_chunks(int num_chunks, struct cma_msg *reply)
++{
++ int i;
++ for (i = 0; i < num_chunks; i++) {
++ struct page *chunk;
++ unsigned int chunk_num;
++ uint8_t *chunk_addr;
++ size_t chunk_size = PAGES_PER_CHUNK << PAGE_SHIFT;
++
++ chunk = dma_alloc_from_contiguous(&vc_cma_device.dev,
++ PAGES_PER_CHUNK,
++ VC_CMA_CHUNK_ORDER);
++ if (!chunk)
++ break;
++
++ chunk_addr = page_address(chunk);
++ dmac_flush_range(chunk_addr, chunk_addr + chunk_size);
++ outer_inv_range(__pa(chunk_addr), __pa(chunk_addr) +
++ chunk_size);
++
++ chunk_num =
++ (page_to_phys(chunk) - vc_cma_base) / VC_CMA_CHUNK_SIZE;
++ BUG_ON(((page_to_phys(chunk) - vc_cma_base) %
++ VC_CMA_CHUNK_SIZE) != 0);
++ if (chunk_num >= vc_cma_chunks) {
++ phys_addr_t _pa = vc_cma_base + vc_cma_size - 1;
++ LOG_ERR("%s: ===============================",
++ __func__);
++ LOG_ERR("%s: chunk phys %x, vc_cma %pa-%pa - "
++ "bad SPARSEMEM configuration?",
++ __func__, (unsigned int)page_to_phys(chunk),
++ &vc_cma_base, &_pa);
++ LOG_ERR("%s: dev->cma_area = %p", __func__,
++ (void*)0/*vc_cma_device.dev.cma_area*/);
++ LOG_ERR("%s: ===============================",
++ __func__);
++ break;
++ }
++ reply->params[i] = chunk_num;
++ vc_cma_chunks_used++;
++ }
++
++ if (i < num_chunks) {
++ LOG_ERR("%s: dma_alloc_from_contiguous failed "
++ "for %x bytes (alloc %d of %d, %d free)",
++ __func__, VC_CMA_CHUNK_SIZE, i,
++ num_chunks, vc_cma_chunks - vc_cma_chunks_used);
++ num_chunks = i;
++ }
++
++ LOG_DBG("CMA allocated %d chunks -> %d used",
++ num_chunks, vc_cma_chunks_used);
++ reply->type = VC_CMA_MSG_ALLOCATED;
++
++ {
++ VCHIQ_ELEMENT_T elem = {
++ reply,
++ offsetof(struct cma_msg, params[0]) +
++ num_chunks * sizeof(reply->params[0])
++ };
++ VCHIQ_STATUS_T ret;
++ vchiq_use_service(cma_service);
++ ret = vchiq_queue_message(cma_service, &elem, 1);
++ vchiq_release_service(cma_service);
++ if (ret != VCHIQ_SUCCESS)
++ LOG_ERR("vchiq_queue_message return " "%x", ret);
++ }
++
++ return num_chunks;
++}
++
++static int cma_worker_proc(void *param)
++{
++ static struct cma_msg reply;
++ (void)param;
++
++ while (1) {
++ VCHIQ_HEADER_T *msg;
++ static struct cma_msg msg_copy;
++ struct cma_msg *cma_msg = &msg_copy;
++ int type, msg_size;
++
++ msg = vchiu_queue_pop(&cma_msg_queue);
++ if ((unsigned int)msg >= VC_CMA_MSG_MAX) {
++ msg_size = msg->size;
++ memcpy(&msg_copy, msg->data, msg_size);
++ type = cma_msg->type;
++ vchiq_release_message(cma_service, msg);
++ } else {
++ msg_size = 0;
++ type = (int)msg;
++ if (type == VC_CMA_MSG_QUIT)
++ break;
++ else if (type == VC_CMA_MSG_UPDATE_RESERVE) {
++ msg = NULL;
++ cma_msg = NULL;
++ } else {
++ BUG();
++ continue;
++ }
++ }
++
++ switch (type) {
++ case VC_CMA_MSG_ALLOC:{
++ int num_chunks, free_chunks;
++ num_chunks = cma_msg->params[0];
++ free_chunks =
++ vc_cma_chunks - vc_cma_chunks_used;
++ LOG_DBG("CMA_MSG_ALLOC(%d chunks)", num_chunks);
++ if (num_chunks > VC_CMA_MAX_PARAMS_PER_MSG) {
++ LOG_ERR
++ ("CMA_MSG_ALLOC - chunk count (%d) "
++ "exceeds VC_CMA_MAX_PARAMS_PER_MSG (%d)",
++ num_chunks,
++ VC_CMA_MAX_PARAMS_PER_MSG);
++ num_chunks = VC_CMA_MAX_PARAMS_PER_MSG;
++ }
++
++ if (num_chunks > free_chunks) {
++ LOG_ERR
++ ("CMA_MSG_ALLOC - chunk count (%d) "
++ "exceeds free chunks (%d)",
++ num_chunks, free_chunks);
++ num_chunks = free_chunks;
++ }
++
++ vc_cma_alloc_chunks(num_chunks, &reply);
++ }
++ break;
++
++ case VC_CMA_MSG_FREE:{
++ int chunk_count =
++ (msg_size -
++ offsetof(struct cma_msg,
++ params)) /
++ sizeof(cma_msg->params[0]);
++ int i;
++ BUG_ON(chunk_count <= 0);
++
++ LOG_DBG("CMA_MSG_FREE(%d chunks - %x, ...)",
++ chunk_count, cma_msg->params[0]);
++ for (i = 0; i < chunk_count; i++) {
++ int chunk_num = cma_msg->params[i];
++ struct page *page = vc_cma_base_page +
++ chunk_num * PAGES_PER_CHUNK;
++ if (chunk_num >= vc_cma_chunks) {
++ LOG_ERR
++ ("CMA_MSG_FREE - chunk %d of %d"
++ " (value %x) exceeds maximum "
++ "(%x)", i, chunk_count,
++ chunk_num,
++ vc_cma_chunks - 1);
++ break;
++ }
++
++ if (!dma_release_from_contiguous
++ (&vc_cma_device.dev, page,
++ PAGES_PER_CHUNK)) {
++ phys_addr_t _pa = page_to_phys(page);
++ LOG_ERR
++ ("CMA_MSG_FREE - failed to "
++ "release chunk %d (phys %pa, "
++ "page %x)", chunk_num,
++ &_pa,
++ (unsigned int)page);
++ }
++ vc_cma_chunks_used--;
++ }
++ LOG_DBG("CMA released %d chunks -> %d used",
++ i, vc_cma_chunks_used);
++ }
++ break;
++
++ case VC_CMA_MSG_UPDATE_RESERVE:{
++ int chunks_needed =
++ ((vc_cma_reserve_total + VC_CMA_CHUNK_SIZE -
++ 1)
++ / VC_CMA_CHUNK_SIZE) -
++ vc_cma_chunks_reserved;
++
++ LOG_DBG
++ ("CMA_MSG_UPDATE_RESERVE(%d chunks needed)",
++ chunks_needed);
++
++ /* Cap the reservations to what is available */
++ if (chunks_needed > 0) {
++ if (chunks_needed >
++ (vc_cma_chunks -
++ vc_cma_chunks_used))
++ chunks_needed =
++ (vc_cma_chunks -
++ vc_cma_chunks_used);
++
++ chunks_needed =
++ vc_cma_alloc_chunks(chunks_needed,
++ &reply);
++ }
++
++ LOG_DBG
++ ("CMA_MSG_UPDATE_RESERVE(%d chunks allocated)",
++ chunks_needed);
++ vc_cma_chunks_reserved += chunks_needed;
++ }
++ break;
++
++ default:
++ LOG_ERR("unexpected msg type %d", type);
++ break;
++ }
++ }
++
++ LOG_DBG("quitting...");
++ return 0;
++}
++
++/****************************************************************************
++*
++* vc_cma_connected_init
++*
++* This function is called once the videocore has been connected.
++*
++***************************************************************************/
++
++static void vc_cma_connected_init(void)
++{
++ VCHIQ_SERVICE_PARAMS_T service_params;
++
++ LOG_DBG("vc_cma_connected_init");
++
++ if (!vchiu_queue_init(&cma_msg_queue, 16)) {
++ LOG_ERR("could not create CMA msg queue");
++ goto fail_queue;
++ }
++
++ if (vchiq_initialise(&cma_instance) != VCHIQ_SUCCESS)
++ goto fail_vchiq_init;
++
++ vchiq_connect(cma_instance);
++
++ service_params.fourcc = VC_CMA_FOURCC;
++ service_params.callback = cma_service_callback;
++ service_params.userdata = NULL;
++ service_params.version = VC_CMA_VERSION;
++ service_params.version_min = VC_CMA_VERSION;
++
++ if (vchiq_open_service(cma_instance, &service_params,
++ &cma_service) != VCHIQ_SUCCESS) {
++ LOG_ERR("failed to open service - already in use?");
++ goto fail_vchiq_open;
++ }
++
++ vchiq_release_service(cma_service);
++
++ cma_worker = kthread_create(cma_worker_proc, NULL, "cma_worker");
++ if (!cma_worker) {
++ LOG_ERR("could not create CMA worker thread");
++ goto fail_worker;
++ }
++ set_user_nice(cma_worker, -20);
++ wake_up_process(cma_worker);
++
++ return;
++
++fail_worker:
++ vchiq_close_service(cma_service);
++fail_vchiq_open:
++ vchiq_shutdown(cma_instance);
++fail_vchiq_init:
++ vchiu_queue_delete(&cma_msg_queue);
++fail_queue:
++ return;
++}
++
++void
++loud_error_header(void)
++{
++ if (in_loud_error)
++ return;
++
++ LOG_ERR("============================================================"
++ "================");
++ LOG_ERR("============================================================"
++ "================");
++ LOG_ERR("=====");
++
++ in_loud_error = 1;
++}
++
++void
++loud_error_footer(void)
++{
++ if (!in_loud_error)
++ return;
++
++ LOG_ERR("=====");
++ LOG_ERR("============================================================"
++ "================");
++ LOG_ERR("============================================================"
++ "================");
++
++ in_loud_error = 0;
++}
++
++#if 1
++static int check_cma_config(void) { return 1; }
++#else
++static int
++read_vc_debug_var(VC_MEM_ACCESS_HANDLE_T handle,
++ const char *symbol,
++ void *buf, size_t bufsize)
++{
++ VC_MEM_ADDR_T vcMemAddr;
++ size_t vcMemSize;
++ uint8_t *mapAddr;
++ off_t vcMapAddr;
++
++ if (!LookupVideoCoreSymbol(handle, symbol,
++ &vcMemAddr,
++ &vcMemSize)) {
++ loud_error_header();
++ loud_error(
++ "failed to find VC symbol \"%s\".",
++ symbol);
++ loud_error_footer();
++ return 0;
++ }
++
++ if (vcMemSize != bufsize) {
++ loud_error_header();
++ loud_error(
++ "VC symbol \"%s\" is the wrong size.",
++ symbol);
++ loud_error_footer();
++ return 0;
++ }
++
++ vcMapAddr = (off_t)vcMemAddr & VC_MEM_TO_ARM_ADDR_MASK;
++ vcMapAddr += mm_vc_mem_phys_addr;
++ mapAddr = ioremap_nocache(vcMapAddr, vcMemSize);
++ if (mapAddr == 0) {
++ loud_error_header();
++ loud_error(
++ "failed to ioremap \"%s\" @ 0x%x "
++ "(phys: 0x%x, size: %u).",
++ symbol,
++ (unsigned int)vcMapAddr,
++ (unsigned int)vcMemAddr,
++ (unsigned int)vcMemSize);
++ loud_error_footer();
++ return 0;
++ }
++
++ memcpy(buf, mapAddr, bufsize);
++ iounmap(mapAddr);
++
++ return 1;
++}
++
++
++static int
++check_cma_config(void)
++{
++ VC_MEM_ACCESS_HANDLE_T mem_hndl;
++ VC_MEM_ADDR_T mempool_start;
++ VC_MEM_ADDR_T mempool_end;
++ VC_MEM_ADDR_T mempool_offline_start;
++ VC_MEM_ADDR_T mempool_offline_end;
++ VC_MEM_ADDR_T cam_alloc_base;
++ VC_MEM_ADDR_T cam_alloc_size;
++ VC_MEM_ADDR_T cam_alloc_end;
++ int success = 0;
++
++ if (OpenVideoCoreMemory(&mem_hndl) != 0)
++ goto out;
++
++ /* Read the relevant VideoCore variables */
++ if (!read_vc_debug_var(mem_hndl, "__MEMPOOL_START",
++ &mempool_start,
++ sizeof(mempool_start)))
++ goto close;
++
++ if (!read_vc_debug_var(mem_hndl, "__MEMPOOL_END",
++ &mempool_end,
++ sizeof(mempool_end)))
++ goto close;
++
++ if (!read_vc_debug_var(mem_hndl, "__MEMPOOL_OFFLINE_START",
++ &mempool_offline_start,
++ sizeof(mempool_offline_start)))
++ goto close;
++
++ if (!read_vc_debug_var(mem_hndl, "__MEMPOOL_OFFLINE_END",
++ &mempool_offline_end,
++ sizeof(mempool_offline_end)))
++ goto close;
++
++ if (!read_vc_debug_var(mem_hndl, "cam_alloc_base",
++ &cam_alloc_base,
++ sizeof(cam_alloc_base)))
++ goto close;
++
++ if (!read_vc_debug_var(mem_hndl, "cam_alloc_size",
++ &cam_alloc_size,
++ sizeof(cam_alloc_size)))
++ goto close;
++
++ cam_alloc_end = cam_alloc_base + cam_alloc_size;
++
++ success = 1;
++
++ /* Now the sanity checks */
++ if (!mempool_offline_start)
++ mempool_offline_start = mempool_start;
++ if (!mempool_offline_end)
++ mempool_offline_end = mempool_end;
++
++ if (VCADDR_TO_PHYSADDR(mempool_offline_start) != vc_cma_base) {
++ loud_error_header();
++ loud_error(
++ "__MEMPOOL_OFFLINE_START(%x -> %lx) doesn't match "
++ "vc_cma_base(%x)",
++ mempool_offline_start,
++ VCADDR_TO_PHYSADDR(mempool_offline_start),
++ vc_cma_base);
++ success = 0;
++ }
++
++ if (VCADDR_TO_PHYSADDR(mempool_offline_end) !=
++ (vc_cma_base + vc_cma_size)) {
++ loud_error_header();
++ loud_error(
++ "__MEMPOOL_OFFLINE_END(%x -> %lx) doesn't match "
++ "vc_cma_base(%x) + vc_cma_size(%x) = %x",
++ mempool_offline_start,
++ VCADDR_TO_PHYSADDR(mempool_offline_end),
++ vc_cma_base, vc_cma_size, vc_cma_base + vc_cma_size);
++ success = 0;
++ }
++
++ if (mempool_end < mempool_start) {
++ loud_error_header();
++ loud_error(
++ "__MEMPOOL_END(%x) must not be before "
++ "__MEMPOOL_START(%x)",
++ mempool_end,
++ mempool_start);
++ success = 0;
++ }
++
++ if (mempool_offline_end < mempool_offline_start) {
++ loud_error_header();
++ loud_error(
++ "__MEMPOOL_OFFLINE_END(%x) must not be before "
++ "__MEMPOOL_OFFLINE_START(%x)",
++ mempool_offline_end,
++ mempool_offline_start);
++ success = 0;
++ }
++
++ if (mempool_offline_start < mempool_start) {
++ loud_error_header();
++ loud_error(
++ "__MEMPOOL_OFFLINE_START(%x) must not be before "
++ "__MEMPOOL_START(%x)",
++ mempool_offline_start,
++ mempool_start);
++ success = 0;
++ }
++
++ if (mempool_offline_end > mempool_end) {
++ loud_error_header();
++ loud_error(
++ "__MEMPOOL_OFFLINE_END(%x) must not be after "
++ "__MEMPOOL_END(%x)",
++ mempool_offline_end,
++ mempool_end);
++ success = 0;
++ }
++
++ if ((cam_alloc_base < mempool_end) &&
++ (cam_alloc_end > mempool_start)) {
++ loud_error_header();
++ loud_error(
++ "cam_alloc pool(%x-%x) overlaps "
++ "mempool(%x-%x)",
++ cam_alloc_base, cam_alloc_end,
++ mempool_start, mempool_end);
++ success = 0;
++ }
++
++ loud_error_footer();
++
++close:
++ CloseVideoCoreMemory(mem_hndl);
++
++out:
++ return success;
++}
++#endif
++
++static int vc_cma_init(void)
++{
++ int rc = -EFAULT;
++ struct device *dev;
++
++ if (!check_cma_config())
++ goto out_release;
++
++ LOG_INFO("vc-cma: Videocore CMA driver");
++ LOG_INFO("vc-cma: vc_cma_base = %pa", &vc_cma_base);
++ LOG_INFO("vc-cma: vc_cma_size = 0x%08x (%u MiB)",
++ vc_cma_size, vc_cma_size / (1024 * 1024));
++ LOG_INFO("vc-cma: vc_cma_initial = 0x%08x (%u MiB)",
++ vc_cma_initial, vc_cma_initial / (1024 * 1024));
++
++ vc_cma_base_page = phys_to_page(vc_cma_base);
++
++ if (vc_cma_chunks) {
++ int chunks_needed = vc_cma_initial / VC_CMA_CHUNK_SIZE;
++
++ for (vc_cma_chunks_used = 0;
++ vc_cma_chunks_used < chunks_needed; vc_cma_chunks_used++) {
++ struct page *chunk;
++ chunk = dma_alloc_from_contiguous(&vc_cma_device.dev,
++ PAGES_PER_CHUNK,
++ VC_CMA_CHUNK_ORDER);
++ if (!chunk)
++ break;
++ BUG_ON(((page_to_phys(chunk) - vc_cma_base) %
++ VC_CMA_CHUNK_SIZE) != 0);
++ }
++ if (vc_cma_chunks_used != chunks_needed) {
++ LOG_ERR("%s: dma_alloc_from_contiguous failed (%d "
++ "bytes, allocation %d of %d)",
++ __func__, VC_CMA_CHUNK_SIZE,
++ vc_cma_chunks_used, chunks_needed);
++ goto out_release;
++ }
++
++ vchiq_add_connected_callback(vc_cma_connected_init);
++ }
++
++ rc = alloc_chrdev_region(&vc_cma_devnum, 0, 1, DRIVER_NAME);
++ if (rc < 0) {
++ LOG_ERR("%s: alloc_chrdev_region failed (rc=%d)", __func__, rc);
++ goto out_release;
++ }
++
++ cdev_init(&vc_cma_cdev, &vc_cma_fops);
++ rc = cdev_add(&vc_cma_cdev, vc_cma_devnum, 1);
++ if (rc != 0) {
++ LOG_ERR("%s: cdev_add failed (rc=%d)", __func__, rc);
++ goto out_unregister;
++ }
++
++ vc_cma_class = class_create(THIS_MODULE, DRIVER_NAME);
++ if (IS_ERR(vc_cma_class)) {
++ rc = PTR_ERR(vc_cma_class);
++ LOG_ERR("%s: class_create failed (rc=%d)", __func__, rc);
++ goto out_cdev_del;
++ }
++
++ dev = device_create(vc_cma_class, NULL, vc_cma_devnum, NULL,
++ DRIVER_NAME);
++ if (IS_ERR(dev)) {
++ rc = PTR_ERR(dev);
++ LOG_ERR("%s: device_create failed (rc=%d)", __func__, rc);
++ goto out_class_destroy;
++ }
++
++ vc_cma_proc_entry = proc_create(DRIVER_NAME, 0444, NULL, &vc_cma_proc_fops);
++ if (vc_cma_proc_entry == NULL) {
++ rc = -EFAULT;
++ LOG_ERR("%s: proc_create failed", __func__);
++ goto out_device_destroy;
++ }
++
++ vc_cma_inited = 1;
++ return 0;
++
++out_device_destroy:
++ device_destroy(vc_cma_class, vc_cma_devnum);
++
++out_class_destroy:
++ class_destroy(vc_cma_class);
++ vc_cma_class = NULL;
++
++out_cdev_del:
++ cdev_del(&vc_cma_cdev);
++
++out_unregister:
++ unregister_chrdev_region(vc_cma_devnum, 1);
++
++out_release:
++ /* It is tempting to try to clean up by calling
++ dma_release_from_contiguous for all allocated chunks, but it isn't
++ a very safe thing to do. If vc_cma_initial is non-zero it is because
++ VideoCore is already using that memory, so giving it back to Linux
++ is likely to be fatal.
++ */
++ return -1;
++}
++
++/****************************************************************************
++*
++* vc_cma_exit
++*
++***************************************************************************/
++
++static void __exit vc_cma_exit(void)
++{
++ LOG_DBG("%s: called", __func__);
++
++ if (vc_cma_inited) {
++ remove_proc_entry(DRIVER_NAME, NULL);
++ device_destroy(vc_cma_class, vc_cma_devnum);
++ class_destroy(vc_cma_class);
++ cdev_del(&vc_cma_cdev);
++ unregister_chrdev_region(vc_cma_devnum, 1);
++ }
++}
++
++module_init(vc_cma_init);
++module_exit(vc_cma_exit);
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Broadcom Corporation");
+diff -Nur linux-4.1.3/drivers/char/broadcom/vcio.c linux-xbian-rpi/drivers/char/broadcom/vcio.c
+--- linux-4.1.3/drivers/char/broadcom/vcio.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/char/broadcom/vcio.c 2015-07-28 01:20:58.186080826 +0200
+@@ -0,0 +1,175 @@
++/*
++ * Copyright (C) 2010 Broadcom
++ * Copyright (C) 2015 Noralf Trønnes
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
++
++#include <linux/cdev.h>
++#include <linux/device.h>
++#include <linux/fs.h>
++#include <linux/init.h>
++#include <linux/ioctl.h>
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <linux/uaccess.h>
++#include <soc/bcm2835/raspberrypi-firmware.h>
++
++#define MBOX_CHAN_PROPERTY 8
++
++#define VCIO_IOC_MAGIC 100
++#define IOCTL_MBOX_PROPERTY _IOWR(VCIO_IOC_MAGIC, 0, char *)
++
++static struct {
++ dev_t devt;
++ struct cdev cdev;
++ struct class *class;
++ struct rpi_firmware *fw;
++} vcio;
++
++static int vcio_user_property_list(void *user)
++{
++ u32 *buf, size;
++ int ret;
++
++ /* The first 32-bit is the size of the buffer */
++ if (copy_from_user(&size, user, sizeof(size)))
++ return -EFAULT;
++
++ buf = kmalloc(size, GFP_KERNEL);
++ if (!buf)
++ return -ENOMEM;
++
++ if (copy_from_user(buf, user, size)) {
++ kfree(buf);
++ return -EFAULT;
++ }
++
++ /* Strip off protocol encapsulation */
++ ret = rpi_firmware_property_list(vcio.fw, &buf[2], size - 12);
++ if (ret) {
++ kfree(buf);
++ return ret;
++ }
++
++ buf[1] = RPI_FIRMWARE_STATUS_SUCCESS;
++ if (copy_to_user(user, buf, size))
++ ret = -EFAULT;
++
++ kfree(buf);
++
++ return ret;
++}
++
++static int vcio_device_open(struct inode *inode, struct file *file)
++{
++ try_module_get(THIS_MODULE);
++
++ return 0;
++}
++
++static int vcio_device_release(struct inode *inode, struct file *file)
++{
++ module_put(THIS_MODULE);
++
++ return 0;
++}
++
++static long vcio_device_ioctl(struct file *file, unsigned int ioctl_num,
++ unsigned long ioctl_param)
++{
++ switch (ioctl_num) {
++ case IOCTL_MBOX_PROPERTY:
++ return vcio_user_property_list((void *)ioctl_param);
++ default:
++ pr_err("unknown ioctl: %d\n", ioctl_num);
++ return -EINVAL;
++ }
++}
++
++const struct file_operations vcio_fops = {
++ .unlocked_ioctl = vcio_device_ioctl,
++ .open = vcio_device_open,
++ .release = vcio_device_release,
++};
++
++static int __init vcio_init(void)
++{
++ struct device_node *np;
++ static struct device *dev;
++ int ret;
++
++ np = of_find_compatible_node(NULL, NULL,
++ "raspberrypi,bcm2835-firmware");
++/* Uncomment this when we only boot with Device Tree
++ if (!of_device_is_available(np))
++ return -ENODEV;
++*/
++ vcio.fw = rpi_firmware_get(np);
++ if (!vcio.fw)
++ return -ENODEV;
++
++ ret = alloc_chrdev_region(&vcio.devt, 0, 1, "vcio");
++ if (ret) {
++ pr_err("failed to allocate device number\n");
++ return ret;
++ }
++
++ cdev_init(&vcio.cdev, &vcio_fops);
++ vcio.cdev.owner = THIS_MODULE;
++ ret = cdev_add(&vcio.cdev, vcio.devt, 1);
++ if (ret) {
++ pr_err("failed to register device\n");
++ goto err_unregister_chardev;
++ }
++
++ /*
++ * Create sysfs entries
++ * 'bcm2708_vcio' is used for backwards compatibility so we don't break
++ * userspace. Raspian has a udev rule that changes the permissions.
++ */
++ vcio.class = class_create(THIS_MODULE, "bcm2708_vcio");
++ if (IS_ERR(vcio.class)) {
++ ret = PTR_ERR(vcio.class);
++ pr_err("failed to create class\n");
++ goto err_cdev_del;
++ }
++
++ dev = device_create(vcio.class, NULL, vcio.devt, NULL, "vcio");
++ if (IS_ERR(dev)) {
++ ret = PTR_ERR(dev);
++ pr_err("failed to create device\n");
++ goto err_class_destroy;
++ }
++
++ return 0;
++
++err_class_destroy:
++ class_destroy(vcio.class);
++err_cdev_del:
++ cdev_del(&vcio.cdev);
++err_unregister_chardev:
++ unregister_chrdev_region(vcio.devt, 1);
++
++ return ret;
++}
++module_init(vcio_init);
++
++static void __exit vcio_exit(void)
++{
++ device_destroy(vcio.class, vcio.devt);
++ class_destroy(vcio.class);
++ cdev_del(&vcio.cdev);
++ unregister_chrdev_region(vcio.devt, 1);
++}
++module_exit(vcio_exit);
++
++MODULE_AUTHOR("Gray Girling");
++MODULE_AUTHOR("Noralf Trønnes");
++MODULE_DESCRIPTION("Mailbox userspace access");
++MODULE_LICENSE("GPL");
+diff -Nur linux-4.1.3/drivers/char/broadcom/vc_mem.c linux-xbian-rpi/drivers/char/broadcom/vc_mem.c
+--- linux-4.1.3/drivers/char/broadcom/vc_mem.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/char/broadcom/vc_mem.c 2015-07-28 01:20:58.186080826 +0200
+@@ -0,0 +1,423 @@
++/*****************************************************************************
++* Copyright 2010 - 2011 Broadcom Corporation. All rights reserved.
++*
++* Unless you and Broadcom execute a separate written software license
++* agreement governing use of this software, this software is licensed to you
++* under the terms of the GNU General Public License version 2, available at
++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
++*
++* Notwithstanding the above, under no circumstances may you combine this
++* software in any way with any other Broadcom software provided under a
++* license other than the GPL, without Broadcom's express prior written
++* consent.
++*****************************************************************************/
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/fs.h>
++#include <linux/device.h>
++#include <linux/cdev.h>
++#include <linux/mm.h>
++#include <linux/slab.h>
++#include <linux/debugfs.h>
++#include <asm/uaccess.h>
++#include <linux/dma-mapping.h>
++#include <linux/platform_data/mailbox-bcm2708.h>
++#include <linux/broadcom/vc_mem.h>
++
++#define DRIVER_NAME "vc-mem"
++
++// Device (/dev) related variables
++static dev_t vc_mem_devnum = 0;
++static struct class *vc_mem_class = NULL;
++static struct cdev vc_mem_cdev;
++static int vc_mem_inited = 0;
++
++#ifdef CONFIG_DEBUG_FS
++static struct dentry *vc_mem_debugfs_entry;
++#endif
++
++/*
++ * Videocore memory addresses and size
++ *
++ * Drivers that wish to know the videocore memory addresses and sizes should
++ * use these variables instead of the MM_IO_BASE and MM_ADDR_IO defines in
++ * headers. This allows the other drivers to not be tied down to a a certain
++ * address/size at compile time.
++ *
++ * In the future, the goal is to have the videocore memory virtual address and
++ * size be calculated at boot time rather than at compile time. The decision of
++ * where the videocore memory resides and its size would be in the hands of the
++ * bootloader (and/or kernel). When that happens, the values of these variables
++ * would be calculated and assigned in the init function.
++ */
++// in the 2835 VC in mapped above ARM, but ARM has full access to VC space
++unsigned long mm_vc_mem_phys_addr = 0x00000000;
++unsigned int mm_vc_mem_size = 0;
++unsigned int mm_vc_mem_base = 0;
++
++EXPORT_SYMBOL(mm_vc_mem_phys_addr);
++EXPORT_SYMBOL(mm_vc_mem_size);
++EXPORT_SYMBOL(mm_vc_mem_base);
++
++static uint phys_addr = 0;
++static uint mem_size = 0;
++static uint mem_base = 0;
++
++
++/****************************************************************************
++*
++* vc_mem_open
++*
++***************************************************************************/
++
++static int
++vc_mem_open(struct inode *inode, struct file *file)
++{
++ (void) inode;
++ (void) file;
++
++ pr_debug("%s: called file = 0x%p\n", __func__, file);
++
++ return 0;
++}
++
++/****************************************************************************
++*
++* vc_mem_release
++*
++***************************************************************************/
++
++static int
++vc_mem_release(struct inode *inode, struct file *file)
++{
++ (void) inode;
++ (void) file;
++
++ pr_debug("%s: called file = 0x%p\n", __func__, file);
++
++ return 0;
++}
++
++/****************************************************************************
++*
++* vc_mem_get_size
++*
++***************************************************************************/
++
++static void
++vc_mem_get_size(void)
++{
++}
++
++/****************************************************************************
++*
++* vc_mem_get_base
++*
++***************************************************************************/
++
++static void
++vc_mem_get_base(void)
++{
++}
++
++/****************************************************************************
++*
++* vc_mem_get_current_size
++*
++***************************************************************************/
++
++int
++vc_mem_get_current_size(void)
++{
++ return mm_vc_mem_size;
++}
++
++EXPORT_SYMBOL_GPL(vc_mem_get_current_size);
++
++/****************************************************************************
++*
++* vc_mem_ioctl
++*
++***************************************************************************/
++
++static long
++vc_mem_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
++{
++ int rc = 0;
++
++ (void) cmd;
++ (void) arg;
++
++ pr_debug("%s: called file = 0x%p\n", __func__, file);
++
++ switch (cmd) {
++ case VC_MEM_IOC_MEM_PHYS_ADDR:
++ {
++ pr_debug("%s: VC_MEM_IOC_MEM_PHYS_ADDR=0x%p\n",
++ __func__, (void *) mm_vc_mem_phys_addr);
++
++ if (copy_to_user((void *) arg, &mm_vc_mem_phys_addr,
++ sizeof (mm_vc_mem_phys_addr)) != 0) {
++ rc = -EFAULT;
++ }
++ break;
++ }
++ case VC_MEM_IOC_MEM_SIZE:
++ {
++ // Get the videocore memory size first
++ vc_mem_get_size();
++
++ pr_debug("%s: VC_MEM_IOC_MEM_SIZE=%u\n", __func__,
++ mm_vc_mem_size);
++
++ if (copy_to_user((void *) arg, &mm_vc_mem_size,
++ sizeof (mm_vc_mem_size)) != 0) {
++ rc = -EFAULT;
++ }
++ break;
++ }
++ case VC_MEM_IOC_MEM_BASE:
++ {
++ // Get the videocore memory base
++ vc_mem_get_base();
++
++ pr_debug("%s: VC_MEM_IOC_MEM_BASE=%u\n", __func__,
++ mm_vc_mem_base);
++
++ if (copy_to_user((void *) arg, &mm_vc_mem_base,
++ sizeof (mm_vc_mem_base)) != 0) {
++ rc = -EFAULT;
++ }
++ break;
++ }
++ case VC_MEM_IOC_MEM_LOAD:
++ {
++ // Get the videocore memory base
++ vc_mem_get_base();
++
++ pr_debug("%s: VC_MEM_IOC_MEM_LOAD=%u\n", __func__,
++ mm_vc_mem_base);
++
++ if (copy_to_user((void *) arg, &mm_vc_mem_base,
++ sizeof (mm_vc_mem_base)) != 0) {
++ rc = -EFAULT;
++ }
++ break;
++ }
++ default:
++ {
++ return -ENOTTY;
++ }
++ }
++ pr_debug("%s: file = 0x%p returning %d\n", __func__, file, rc);
++
++ return rc;
++}
++
++/****************************************************************************
++*
++* vc_mem_mmap
++*
++***************************************************************************/
++
++static int
++vc_mem_mmap(struct file *filp, struct vm_area_struct *vma)
++{
++ int rc = 0;
++ unsigned long length = vma->vm_end - vma->vm_start;
++ unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
++
++ pr_debug("%s: vm_start = 0x%08lx vm_end = 0x%08lx vm_pgoff = 0x%08lx\n",
++ __func__, (long) vma->vm_start, (long) vma->vm_end,
++ (long) vma->vm_pgoff);
++
++ if (offset + length > mm_vc_mem_size) {
++ pr_err("%s: length %ld is too big\n", __func__, length);
++ return -EINVAL;
++ }
++ // Do not cache the memory map
++ vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
++
++ rc = remap_pfn_range(vma, vma->vm_start,
++ (mm_vc_mem_phys_addr >> PAGE_SHIFT) +
++ vma->vm_pgoff, length, vma->vm_page_prot);
++ if (rc != 0) {
++ pr_err("%s: remap_pfn_range failed (rc=%d)\n", __func__, rc);
++ }
++
++ return rc;
++}
++
++/****************************************************************************
++*
++* File Operations for the driver.
++*
++***************************************************************************/
++
++static const struct file_operations vc_mem_fops = {
++ .owner = THIS_MODULE,
++ .open = vc_mem_open,
++ .release = vc_mem_release,
++ .unlocked_ioctl = vc_mem_ioctl,
++ .mmap = vc_mem_mmap,
++};
++
++#ifdef CONFIG_DEBUG_FS
++static void vc_mem_debugfs_deinit(void)
++{
++ debugfs_remove_recursive(vc_mem_debugfs_entry);
++ vc_mem_debugfs_entry = NULL;
++}
++
++
++static int vc_mem_debugfs_init(
++ struct device *dev)
++{
++ vc_mem_debugfs_entry = debugfs_create_dir(DRIVER_NAME, NULL);
++ if (!vc_mem_debugfs_entry) {
++ dev_warn(dev, "could not create debugfs entry\n");
++ return -EFAULT;
++ }
++
++ if (!debugfs_create_x32("vc_mem_phys_addr",
++ 0444,
++ vc_mem_debugfs_entry,
++ (u32 *)&mm_vc_mem_phys_addr)) {
++ dev_warn(dev, "%s:could not create vc_mem_phys entry\n",
++ __func__);
++ goto fail;
++ }
++
++ if (!debugfs_create_x32("vc_mem_size",
++ 0444,
++ vc_mem_debugfs_entry,
++ (u32 *)&mm_vc_mem_size)) {
++ dev_warn(dev, "%s:could not create vc_mem_size entry\n",
++ __func__);
++ goto fail;
++ }
++
++ if (!debugfs_create_x32("vc_mem_base",
++ 0444,
++ vc_mem_debugfs_entry,
++ (u32 *)&mm_vc_mem_base)) {
++ dev_warn(dev, "%s:could not create vc_mem_base entry\n",
++ __func__);
++ goto fail;
++ }
++
++ return 0;
++
++fail:
++ vc_mem_debugfs_deinit();
++ return -EFAULT;
++}
++
++#endif /* CONFIG_DEBUG_FS */
++
++
++/****************************************************************************
++*
++* vc_mem_init
++*
++***************************************************************************/
++
++static int __init
++vc_mem_init(void)
++{
++ int rc = -EFAULT;
++ struct device *dev;
++
++ pr_debug("%s: called\n", __func__);
++
++ mm_vc_mem_phys_addr = phys_addr;
++ mm_vc_mem_size = mem_size;
++ mm_vc_mem_base = mem_base;
++
++ vc_mem_get_size();
++
++ pr_info("vc-mem: phys_addr:0x%08lx mem_base=0x%08x mem_size:0x%08x(%u MiB)\n",
++ mm_vc_mem_phys_addr, mm_vc_mem_base, mm_vc_mem_size, mm_vc_mem_size / (1024 * 1024));
++
++ if ((rc = alloc_chrdev_region(&vc_mem_devnum, 0, 1, DRIVER_NAME)) < 0) {
++ pr_err("%s: alloc_chrdev_region failed (rc=%d)\n",
++ __func__, rc);
++ goto out_err;
++ }
++
++ cdev_init(&vc_mem_cdev, &vc_mem_fops);
++ if ((rc = cdev_add(&vc_mem_cdev, vc_mem_devnum, 1)) != 0) {
++ pr_err("%s: cdev_add failed (rc=%d)\n", __func__, rc);
++ goto out_unregister;
++ }
++
++ vc_mem_class = class_create(THIS_MODULE, DRIVER_NAME);
++ if (IS_ERR(vc_mem_class)) {
++ rc = PTR_ERR(vc_mem_class);
++ pr_err("%s: class_create failed (rc=%d)\n", __func__, rc);
++ goto out_cdev_del;
++ }
++
++ dev = device_create(vc_mem_class, NULL, vc_mem_devnum, NULL,
++ DRIVER_NAME);
++ if (IS_ERR(dev)) {
++ rc = PTR_ERR(dev);
++ pr_err("%s: device_create failed (rc=%d)\n", __func__, rc);
++ goto out_class_destroy;
++ }
++
++#ifdef CONFIG_DEBUG_FS
++ /* don't fail if the debug entries cannot be created */
++ vc_mem_debugfs_init(dev);
++#endif
++
++ vc_mem_inited = 1;
++ return 0;
++
++ device_destroy(vc_mem_class, vc_mem_devnum);
++
++ out_class_destroy:
++ class_destroy(vc_mem_class);
++ vc_mem_class = NULL;
++
++ out_cdev_del:
++ cdev_del(&vc_mem_cdev);
++
++ out_unregister:
++ unregister_chrdev_region(vc_mem_devnum, 1);
++
++ out_err:
++ return -1;
++}
++
++/****************************************************************************
++*
++* vc_mem_exit
++*
++***************************************************************************/
++
++static void __exit
++vc_mem_exit(void)
++{
++ pr_debug("%s: called\n", __func__);
++
++ if (vc_mem_inited) {
++#if CONFIG_DEBUG_FS
++ vc_mem_debugfs_deinit();
++#endif
++ device_destroy(vc_mem_class, vc_mem_devnum);
++ class_destroy(vc_mem_class);
++ cdev_del(&vc_mem_cdev);
++ unregister_chrdev_region(vc_mem_devnum, 1);
++ }
++}
++
++module_init(vc_mem_init);
++module_exit(vc_mem_exit);
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Broadcom Corporation");
++
++module_param(phys_addr, uint, 0644);
++module_param(mem_size, uint, 0644);
++module_param(mem_base, uint, 0644);
+diff -Nur linux-4.1.3/drivers/char/broadcom/vc_sm/Makefile linux-xbian-rpi/drivers/char/broadcom/vc_sm/Makefile
+--- linux-4.1.3/drivers/char/broadcom/vc_sm/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/char/broadcom/vc_sm/Makefile 2015-07-28 01:20:58.186080826 +0200
+@@ -0,0 +1,21 @@
++EXTRA_CFLAGS += -Wall -Wstrict-prototypes -Wno-trigraphs -O2
++
++EXTRA_CFLAGS += -I"./arch/arm/mach-bcm2708/include/mach"
++EXTRA_CFLAGS += -I"drivers/misc/vc04_services"
++EXTRA_CFLAGS += -I"drivers/misc/vc04_services/interface/vchi"
++EXTRA_CFLAGS += -I"drivers/misc/vc04_services/interface/vchiq_arm"
++EXTRA_CFLAGS += -I"$(srctree)/fs/"
++
++EXTRA_CFLAGS += -DOS_ASSERT_FAILURE
++EXTRA_CFLAGS += -D__STDC_VERSION=199901L
++EXTRA_CFLAGS += -D__STDC_VERSION__=199901L
++EXTRA_CFLAGS += -D__VCCOREVER__=0
++EXTRA_CFLAGS += -D__KERNEL__
++EXTRA_CFLAGS += -D__linux__
++EXTRA_CFLAGS += -Werror
++
++obj-$(CONFIG_BCM_VC_SM) := vc-sm.o
++
++vc-sm-objs := \
++ vmcs_sm.o \
++ vc_vchi_sm.o
+diff -Nur linux-4.1.3/drivers/char/broadcom/vc_sm/vc_vchi_sm.c linux-xbian-rpi/drivers/char/broadcom/vc_sm/vc_vchi_sm.c
+--- linux-4.1.3/drivers/char/broadcom/vc_sm/vc_vchi_sm.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/char/broadcom/vc_sm/vc_vchi_sm.c 2015-07-28 01:20:58.186080826 +0200
+@@ -0,0 +1,492 @@
++/*****************************************************************************
++* Copyright 2011-2012 Broadcom Corporation. All rights reserved.
++*
++* Unless you and Broadcom execute a separate written software license
++* agreement governing use of this software, this software is licensed to you
++* under the terms of the GNU General Public License version 2, available at
++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
++*
++* Notwithstanding the above, under no circumstances may you combine this
++* software in any way with any other Broadcom software provided under a
++* license other than the GPL, without Broadcom's express prior written
++* consent.
++*****************************************************************************/
++
++/* ---- Include Files ----------------------------------------------------- */
++#include <linux/types.h>
++#include <linux/kernel.h>
++#include <linux/list.h>
++#include <linux/semaphore.h>
++#include <linux/mutex.h>
++#include <linux/slab.h>
++#include <linux/kthread.h>
++
++#include "vc_vchi_sm.h"
++
++#define VC_SM_VER 1
++#define VC_SM_MIN_VER 0
++
++/* ---- Private Constants and Types -------------------------------------- */
++
++/* Command blocks come from a pool */
++#define SM_MAX_NUM_CMD_RSP_BLKS 32
++
++struct sm_cmd_rsp_blk {
++ struct list_head head; /* To create lists */
++ struct semaphore sema; /* To be signaled when the response is there */
++
++ uint16_t id;
++ uint16_t length;
++
++ uint8_t msg[VC_SM_MAX_MSG_LEN];
++
++ uint32_t wait:1;
++ uint32_t sent:1;
++ uint32_t alloc:1;
++
++};
++
++struct sm_instance {
++ uint32_t num_connections;
++ VCHI_SERVICE_HANDLE_T vchi_handle[VCHI_MAX_NUM_CONNECTIONS];
++ struct task_struct *io_thread;
++ struct semaphore io_sema;
++
++ uint32_t trans_id;
++
++ struct mutex lock;
++ struct list_head cmd_list;
++ struct list_head rsp_list;
++ struct list_head dead_list;
++
++ struct sm_cmd_rsp_blk free_blk[SM_MAX_NUM_CMD_RSP_BLKS];
++ struct list_head free_list;
++ struct mutex free_lock;
++ struct semaphore free_sema;
++
++};
++
++/* ---- Private Variables ------------------------------------------------ */
++
++/* ---- Private Function Prototypes -------------------------------------- */
++
++/* ---- Private Functions ------------------------------------------------ */
++static struct
++sm_cmd_rsp_blk *vc_vchi_cmd_create(struct sm_instance *instance,
++ VC_SM_MSG_TYPE id, void *msg,
++ uint32_t size, int wait)
++{
++ struct sm_cmd_rsp_blk *blk;
++ VC_SM_MSG_HDR_T *hdr;
++
++ if (down_interruptible(&instance->free_sema)) {
++ blk = kmalloc(sizeof(*blk), GFP_KERNEL);
++ if (!blk)
++ return NULL;
++
++ blk->alloc = 1;
++ sema_init(&blk->sema, 0);
++ } else {
++ mutex_lock(&instance->free_lock);
++ blk =
++ list_first_entry(&instance->free_list,
++ struct sm_cmd_rsp_blk, head);
++ list_del(&blk->head);
++ mutex_unlock(&instance->free_lock);
++ }
++
++ blk->sent = 0;
++ blk->wait = wait;
++ blk->length = sizeof(*hdr) + size;
++
++ hdr = (VC_SM_MSG_HDR_T *) blk->msg;
++ hdr->type = id;
++ mutex_lock(&instance->lock);
++ hdr->trans_id = blk->id = ++instance->trans_id;
++ mutex_unlock(&instance->lock);
++
++ if (size)
++ memcpy(hdr->body, msg, size);
++
++ return blk;
++}
++
++static void
++vc_vchi_cmd_delete(struct sm_instance *instance, struct sm_cmd_rsp_blk *blk)
++{
++ if (blk->alloc) {
++ kfree(blk);
++ return;
++ }
++
++ mutex_lock(&instance->free_lock);
++ list_add(&blk->head, &instance->free_list);
++ mutex_unlock(&instance->free_lock);
++ up(&instance->free_sema);
++}
++
++static int vc_vchi_sm_videocore_io(void *arg)
++{
++ struct sm_instance *instance = arg;
++ struct sm_cmd_rsp_blk *cmd = NULL, *cmd_tmp;
++ VC_SM_RESULT_T *reply;
++ uint32_t reply_len;
++ int32_t status;
++ int svc_use = 1;
++
++ while (1) {
++ if (svc_use)
++ vchi_service_release(instance->vchi_handle[0]);
++ svc_use = 0;
++ if (!down_interruptible(&instance->io_sema)) {
++ vchi_service_use(instance->vchi_handle[0]);
++ svc_use = 1;
++
++ do {
++ unsigned int flags;
++ /*
++ * Get new command and move it to response list
++ */
++ mutex_lock(&instance->lock);
++ if (list_empty(&instance->cmd_list)) {
++ /* no more commands to process */
++ mutex_unlock(&instance->lock);
++ break;
++ }
++ cmd =
++ list_first_entry(&instance->cmd_list,
++ struct sm_cmd_rsp_blk,
++ head);
++ list_move(&cmd->head, &instance->rsp_list);
++ cmd->sent = 1;
++ mutex_unlock(&instance->lock);
++
++ /* Send the command */
++ flags = VCHI_FLAGS_BLOCK_UNTIL_QUEUED;
++ status = vchi_msg_queue(
++ instance->vchi_handle[0],
++ cmd->msg, cmd->length,
++ flags, NULL);
++ if (status) {
++ pr_err("%s: failed to queue message (%d)",
++ __func__, status);
++ }
++
++ /* If no reply is needed then we're done */
++ if (!cmd->wait) {
++ mutex_lock(&instance->lock);
++ list_del(&cmd->head);
++ mutex_unlock(&instance->lock);
++ vc_vchi_cmd_delete(instance, cmd);
++ continue;
++ }
++
++ if (status) {
++ up(&cmd->sema);
++ continue;
++ }
++
++ } while (1);
++
++ while (!vchi_msg_peek
++ (instance->vchi_handle[0], (void **)&reply,
++ &reply_len, VCHI_FLAGS_NONE)) {
++ mutex_lock(&instance->lock);
++ list_for_each_entry(cmd, &instance->rsp_list,
++ head) {
++ if (cmd->id == reply->trans_id)
++ break;
++ }
++ mutex_unlock(&instance->lock);
++
++ if (&cmd->head == &instance->rsp_list) {
++ pr_debug("%s: received response %u, throw away...",
++ __func__, reply->trans_id);
++ } else if (reply_len > sizeof(cmd->msg)) {
++ pr_err("%s: reply too big (%u) %u, throw away...",
++ __func__, reply_len,
++ reply->trans_id);
++ } else {
++ memcpy(cmd->msg, reply, reply_len);
++ up(&cmd->sema);
++ }
++
++ vchi_msg_remove(instance->vchi_handle[0]);
++ }
++
++ /* Go through the dead list and free them */
++ mutex_lock(&instance->lock);
++ list_for_each_entry_safe(cmd, cmd_tmp,
++ &instance->dead_list, head) {
++ list_del(&cmd->head);
++ vc_vchi_cmd_delete(instance, cmd);
++ }
++ mutex_unlock(&instance->lock);
++ }
++ }
++
++ return 0;
++}
++
++static void vc_sm_vchi_callback(void *param,
++ const VCHI_CALLBACK_REASON_T reason,
++ void *msg_handle)
++{
++ struct sm_instance *instance = param;
++
++ (void)msg_handle;
++
++ switch (reason) {
++ case VCHI_CALLBACK_MSG_AVAILABLE:
++ up(&instance->io_sema);
++ break;
++
++ case VCHI_CALLBACK_SERVICE_CLOSED:
++ pr_info("%s: service CLOSED!!", __func__);
++ default:
++ break;
++ }
++}
++
++VC_VCHI_SM_HANDLE_T vc_vchi_sm_init(VCHI_INSTANCE_T vchi_instance,
++ VCHI_CONNECTION_T **vchi_connections,
++ uint32_t num_connections)
++{
++ uint32_t i;
++ struct sm_instance *instance;
++ int status;
++
++ pr_debug("%s: start", __func__);
++
++ if (num_connections > VCHI_MAX_NUM_CONNECTIONS) {
++ pr_err("%s: unsupported number of connections %u (max=%u)",
++ __func__, num_connections, VCHI_MAX_NUM_CONNECTIONS);
++
++ goto err_null;
++ }
++ /* Allocate memory for this instance */
++ instance = kzalloc(sizeof(*instance), GFP_KERNEL);
++
++ /* Misc initialisations */
++ mutex_init(&instance->lock);
++ sema_init(&instance->io_sema, 0);
++ INIT_LIST_HEAD(&instance->cmd_list);
++ INIT_LIST_HEAD(&instance->rsp_list);
++ INIT_LIST_HEAD(&instance->dead_list);
++ INIT_LIST_HEAD(&instance->free_list);
++ sema_init(&instance->free_sema, SM_MAX_NUM_CMD_RSP_BLKS);
++ mutex_init(&instance->free_lock);
++ for (i = 0; i < SM_MAX_NUM_CMD_RSP_BLKS; i++) {
++ sema_init(&instance->free_blk[i].sema, 0);
++ list_add(&instance->free_blk[i].head, &instance->free_list);
++ }
++
++ /* Open the VCHI service connections */
++ instance->num_connections = num_connections;
++ for (i = 0; i < num_connections; i++) {
++ SERVICE_CREATION_T params = {
++ VCHI_VERSION_EX(VC_SM_VER, VC_SM_MIN_VER),
++ VC_SM_SERVER_NAME,
++ vchi_connections[i],
++ 0,
++ 0,
++ vc_sm_vchi_callback,
++ instance,
++ 0,
++ 0,
++ 0,
++ };
++
++ status = vchi_service_open(vchi_instance,
++ &params, &instance->vchi_handle[i]);
++ if (status) {
++ pr_err("%s: failed to open VCHI service (%d)",
++ __func__, status);
++
++ goto err_close_services;
++ }
++ }
++
++ /* Create the thread which takes care of all io to/from videoocore. */
++ instance->io_thread = kthread_create(&vc_vchi_sm_videocore_io,
++ (void *)instance, "SMIO");
++ if (instance->io_thread == NULL) {
++ pr_err("%s: failed to create SMIO thread", __func__);
++
++ goto err_close_services;
++ }
++ set_user_nice(instance->io_thread, -10);
++ wake_up_process(instance->io_thread);
++
++ pr_debug("%s: success - instance 0x%x", __func__, (unsigned)instance);
++ return instance;
++
++err_close_services:
++ for (i = 0; i < instance->num_connections; i++) {
++ if (instance->vchi_handle[i] != NULL)
++ vchi_service_close(instance->vchi_handle[i]);
++ }
++ kfree(instance);
++err_null:
++ pr_debug("%s: FAILED", __func__);
++ return NULL;
++}
++
++int vc_vchi_sm_stop(VC_VCHI_SM_HANDLE_T *handle)
++{
++ struct sm_instance *instance;
++ uint32_t i;
++
++ if (handle == NULL) {
++ pr_err("%s: invalid pointer to handle %p", __func__, handle);
++ goto lock;
++ }
++
++ if (*handle == NULL) {
++ pr_err("%s: invalid handle %p", __func__, *handle);
++ goto lock;
++ }
++
++ instance = *handle;
++
++ /* Close all VCHI service connections */
++ for (i = 0; i < instance->num_connections; i++) {
++ int32_t success;
++ vchi_service_use(instance->vchi_handle[i]);
++
++ success = vchi_service_close(instance->vchi_handle[i]);
++ }
++
++ kfree(instance);
++
++ *handle = NULL;
++ return 0;
++
++lock:
++ return -EINVAL;
++}
++
++int vc_vchi_sm_send_msg(VC_VCHI_SM_HANDLE_T handle,
++ VC_SM_MSG_TYPE msg_id,
++ void *msg, uint32_t msg_size,
++ void *result, uint32_t result_size,
++ uint32_t *cur_trans_id, uint8_t wait_reply)
++{
++ int status = 0;
++ struct sm_instance *instance = handle;
++ struct sm_cmd_rsp_blk *cmd_blk;
++
++ if (handle == NULL) {
++ pr_err("%s: invalid handle", __func__);
++ return -EINVAL;
++ }
++ if (msg == NULL) {
++ pr_err("%s: invalid msg pointer", __func__);
++ return -EINVAL;
++ }
++
++ cmd_blk =
++ vc_vchi_cmd_create(instance, msg_id, msg, msg_size, wait_reply);
++ if (cmd_blk == NULL) {
++ pr_err("[%s]: failed to allocate global tracking resource",
++ __func__);
++ return -ENOMEM;
++ }
++
++ if (cur_trans_id != NULL)
++ *cur_trans_id = cmd_blk->id;
++
++ mutex_lock(&instance->lock);
++ list_add_tail(&cmd_blk->head, &instance->cmd_list);
++ mutex_unlock(&instance->lock);
++ up(&instance->io_sema);
++
++ if (!wait_reply)
++ /* We're done */
++ return 0;
++
++ /* Wait for the response */
++ if (down_interruptible(&cmd_blk->sema)) {
++ mutex_lock(&instance->lock);
++ if (!cmd_blk->sent) {
++ list_del(&cmd_blk->head);
++ mutex_unlock(&instance->lock);
++ vc_vchi_cmd_delete(instance, cmd_blk);
++ return -ENXIO;
++ }
++ mutex_unlock(&instance->lock);
++
++ mutex_lock(&instance->lock);
++ list_move(&cmd_blk->head, &instance->dead_list);
++ mutex_unlock(&instance->lock);
++ up(&instance->io_sema);
++ return -EINTR; /* We're done */
++ }
++
++ if (result && result_size) {
++ memcpy(result, cmd_blk->msg, result_size);
++ } else {
++ VC_SM_RESULT_T *res = (VC_SM_RESULT_T *) cmd_blk->msg;
++ status = (res->success == 0) ? 0 : -ENXIO;
++ }
++
++ mutex_lock(&instance->lock);
++ list_del(&cmd_blk->head);
++ mutex_unlock(&instance->lock);
++ vc_vchi_cmd_delete(instance, cmd_blk);
++ return status;
++}
++
++int vc_vchi_sm_alloc(VC_VCHI_SM_HANDLE_T handle, VC_SM_ALLOC_T *msg,
++ VC_SM_ALLOC_RESULT_T *result, uint32_t *cur_trans_id)
++{
++ return vc_vchi_sm_send_msg(handle, VC_SM_MSG_TYPE_ALLOC,
++ msg, sizeof(*msg), result, sizeof(*result),
++ cur_trans_id, 1);
++}
++
++int vc_vchi_sm_free(VC_VCHI_SM_HANDLE_T handle,
++ VC_SM_FREE_T *msg, uint32_t *cur_trans_id)
++{
++ return vc_vchi_sm_send_msg(handle, VC_SM_MSG_TYPE_FREE,
++ msg, sizeof(*msg), 0, 0, cur_trans_id, 0);
++}
++
++int vc_vchi_sm_lock(VC_VCHI_SM_HANDLE_T handle,
++ VC_SM_LOCK_UNLOCK_T *msg,
++ VC_SM_LOCK_RESULT_T *result, uint32_t *cur_trans_id)
++{
++ return vc_vchi_sm_send_msg(handle, VC_SM_MSG_TYPE_LOCK,
++ msg, sizeof(*msg), result, sizeof(*result),
++ cur_trans_id, 1);
++}
++
++int vc_vchi_sm_unlock(VC_VCHI_SM_HANDLE_T handle,
++ VC_SM_LOCK_UNLOCK_T *msg,
++ uint32_t *cur_trans_id, uint8_t wait_reply)
++{
++ return vc_vchi_sm_send_msg(handle, wait_reply ?
++ VC_SM_MSG_TYPE_UNLOCK :
++ VC_SM_MSG_TYPE_UNLOCK_NOANS, msg,
++ sizeof(*msg), 0, 0, cur_trans_id,
++ wait_reply);
++}
++
++int vc_vchi_sm_resize(VC_VCHI_SM_HANDLE_T handle, VC_SM_RESIZE_T *msg,
++ uint32_t *cur_trans_id)
++{
++ return vc_vchi_sm_send_msg(handle, VC_SM_MSG_TYPE_RESIZE,
++ msg, sizeof(*msg), 0, 0, cur_trans_id, 1);
++}
++
++int vc_vchi_sm_walk_alloc(VC_VCHI_SM_HANDLE_T handle)
++{
++ return vc_vchi_sm_send_msg(handle, VC_SM_MSG_TYPE_WALK_ALLOC,
++ 0, 0, 0, 0, 0, 0);
++}
++
++int vc_vchi_sm_clean_up(VC_VCHI_SM_HANDLE_T handle, VC_SM_ACTION_CLEAN_T *msg)
++{
++ return vc_vchi_sm_send_msg(handle, VC_SM_MSG_TYPE_ACTION_CLEAN,
++ msg, sizeof(*msg), 0, 0, 0, 0);
++}
+diff -Nur linux-4.1.3/drivers/char/broadcom/vc_sm/vmcs_sm.c linux-xbian-rpi/drivers/char/broadcom/vc_sm/vmcs_sm.c
+--- linux-4.1.3/drivers/char/broadcom/vc_sm/vmcs_sm.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/char/broadcom/vc_sm/vmcs_sm.c 2015-07-28 01:20:58.186080826 +0200
+@@ -0,0 +1,3211 @@
++/*****************************************************************************
++* Copyright 2011-2012 Broadcom Corporation. All rights reserved.
++*
++* Unless you and Broadcom execute a separate written software license
++* agreement governing use of this software, this software is licensed to you
++* under the terms of the GNU General Public License version 2, available at
++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
++*
++* Notwithstanding the above, under no circumstances may you combine this
++* software in any way with any other Broadcom software provided under a
++* license other than the GPL, without Broadcom's express prior written
++* consent.
++*****************************************************************************/
++
++/* ---- Include Files ----------------------------------------------------- */
++
++#include <linux/cdev.h>
++#include <linux/broadcom/vc_mem.h>
++#include <linux/device.h>
++#include <linux/debugfs.h>
++#include <linux/dma-mapping.h>
++#include <linux/errno.h>
++#include <linux/fs.h>
++#include <linux/hugetlb.h>
++#include <linux/ioctl.h>
++#include <linux/kernel.h>
++#include <linux/list.h>
++#include <linux/module.h>
++#include <linux/mm.h>
++#include <linux/pfn.h>
++#include <linux/proc_fs.h>
++#include <linux/pagemap.h>
++#include <linux/semaphore.h>
++#include <linux/slab.h>
++#include <linux/seq_file.h>
++#include <linux/types.h>
++#include <asm/cacheflush.h>
++
++#include "vchiq_connected.h"
++#include "vc_vchi_sm.h"
++
++#include <vmcs_sm_ioctl.h>
++#include "vc_sm_knl.h"
++
++/* ---- Private Constants and Types --------------------------------------- */
++
++#define DEVICE_NAME "vcsm"
++#define DEVICE_MINOR 0
++
++#define VC_SM_DIR_ROOT_NAME "vc-smem"
++#define VC_SM_DIR_ALLOC_NAME "alloc"
++#define VC_SM_STATE "state"
++#define VC_SM_STATS "statistics"
++#define VC_SM_RESOURCES "resources"
++#define VC_SM_DEBUG "debug"
++#define VC_SM_WRITE_BUF_SIZE 128
++
++/* Statistics tracked per resource and globally.
++*/
++enum SM_STATS_T {
++ /* Attempt. */
++ ALLOC,
++ FREE,
++ LOCK,
++ UNLOCK,
++ MAP,
++ FLUSH,
++ INVALID,
++
++ END_ATTEMPT,
++
++ /* Failure. */
++ ALLOC_FAIL,
++ FREE_FAIL,
++ LOCK_FAIL,
++ UNLOCK_FAIL,
++ MAP_FAIL,
++ FLUSH_FAIL,
++ INVALID_FAIL,
++
++ END_ALL,
++
++};
++
++static const char *const sm_stats_human_read[] = {
++ "Alloc",
++ "Free",
++ "Lock",
++ "Unlock",
++ "Map",
++ "Cache Flush",
++ "Cache Invalidate",
++};
++
++typedef int (*VC_SM_SHOW) (struct seq_file *s, void *v);
++struct SM_PDE_T {
++ VC_SM_SHOW show; /* Debug fs function hookup. */
++ struct dentry *dir_entry; /* Debug fs directory entry. */
++ void *priv_data; /* Private data */
++
++};
++
++/* Single resource allocation tracked for all devices.
++*/
++struct sm_mmap {
++ struct list_head map_list; /* Linked list of maps. */
++
++ struct SM_RESOURCE_T *resource; /* Pointer to the resource. */
++
++ pid_t res_pid; /* PID owning that resource. */
++ unsigned int res_vc_hdl; /* Resource handle (videocore). */
++ unsigned int res_usr_hdl; /* Resource handle (user). */
++
++ long unsigned int res_addr; /* Mapped virtual address. */
++ struct vm_area_struct *vma; /* VM area for this mapping. */
++ unsigned int ref_count; /* Reference count to this vma. */
++
++ /* Used to link maps associated with a resource. */
++ struct list_head resource_map_list;
++};
++
++/* Single resource allocation tracked for each opened device.
++*/
++struct SM_RESOURCE_T {
++ struct list_head resource_list; /* List of resources. */
++ struct list_head global_resource_list; /* Global list of resources. */
++
++ pid_t pid; /* PID owning that resource. */
++ uint32_t res_guid; /* Unique identifier. */
++ uint32_t lock_count; /* Lock count for this resource. */
++ uint32_t ref_count; /* Ref count for this resource. */
++
++ uint32_t res_handle; /* Resource allocation handle. */
++ void *res_base_mem; /* Resource base memory address. */
++ uint32_t res_size; /* Resource size allocated. */
++ enum vmcs_sm_cache_e res_cached; /* Resource cache type. */
++ struct SM_RESOURCE_T *res_shared; /* Shared resource */
++
++ enum SM_STATS_T res_stats[END_ALL]; /* Resource statistics. */
++
++ uint8_t map_count; /* Counter of mappings for this resource. */
++ struct list_head map_list; /* Maps associated with a resource. */
++
++ struct SM_PRIV_DATA_T *private;
++};
++
++/* Private file data associated with each opened device.
++*/
++struct SM_PRIV_DATA_T {
++ struct list_head resource_list; /* List of resources. */
++
++ pid_t pid; /* PID of creator. */
++
++ struct dentry *dir_pid; /* Debug fs entries root. */
++ struct SM_PDE_T dir_stats; /* Debug fs entries statistics sub-tree. */
++ struct SM_PDE_T dir_res; /* Debug fs resource sub-tree. */
++
++ int restart_sys; /* Tracks restart on interrupt. */
++ VC_SM_MSG_TYPE int_action; /* Interrupted action. */
++ uint32_t int_trans_id; /* Interrupted transaction. */
++
++};
++
++/* Global state information.
++*/
++struct SM_STATE_T {
++ VC_VCHI_SM_HANDLE_T sm_handle; /* Handle for videocore service. */
++ struct dentry *dir_root; /* Debug fs entries root. */
++ struct dentry *dir_alloc; /* Debug fs entries allocations. */
++ struct SM_PDE_T dir_stats; /* Debug fs entries statistics sub-tree. */
++ struct SM_PDE_T dir_state; /* Debug fs entries state sub-tree. */
++ struct dentry *debug; /* Debug fs entries debug. */
++
++ struct mutex map_lock; /* Global map lock. */
++ struct list_head map_list; /* List of maps. */
++ struct list_head resource_list; /* List of resources. */
++
++ enum SM_STATS_T deceased[END_ALL]; /* Natural termination stats. */
++ enum SM_STATS_T terminated[END_ALL]; /* Forced termination stats. */
++ uint32_t res_deceased_cnt; /* Natural termination counter. */
++ uint32_t res_terminated_cnt; /* Forced termination counter. */
++
++ struct cdev sm_cdev; /* Device. */
++ dev_t sm_devid; /* Device identifier. */
++ struct class *sm_class; /* Class. */
++ struct device *sm_dev; /* Device. */
++
++ struct SM_PRIV_DATA_T *data_knl; /* Kernel internal data tracking. */
++
++ struct mutex lock; /* Global lock. */
++ uint32_t guid; /* GUID (next) tracker. */
++
++};
++
++/* ---- Private Variables ----------------------------------------------- */
++
++static struct SM_STATE_T *sm_state;
++static int sm_inited;
++
++static const char *const sm_cache_map_vector[] = {
++ "(null)",
++ "host",
++ "videocore",
++ "host+videocore",
++};
++
++/* ---- Private Function Prototypes -------------------------------------- */
++
++/* ---- Private Functions ------------------------------------------------ */
++
++static inline unsigned vcaddr_to_pfn(unsigned long vc_addr)
++{
++ unsigned long pfn = vc_addr & 0x3FFFFFFF;
++ pfn += mm_vc_mem_phys_addr;
++ pfn >>= PAGE_SHIFT;
++ return pfn;
++}
++
++/* Carries over to the state statistics the statistics once owned by a deceased
++** resource.
++*/
++static void vc_sm_resource_deceased(struct SM_RESOURCE_T *p_res, int terminated)
++{
++ if (sm_state != NULL) {
++ if (p_res != NULL) {
++ int ix;
++
++ if (terminated)
++ sm_state->res_terminated_cnt++;
++ else
++ sm_state->res_deceased_cnt++;
++
++ for (ix = 0; ix < END_ALL; ix++) {
++ if (terminated)
++ sm_state->terminated[ix] +=
++ p_res->res_stats[ix];
++ else
++ sm_state->deceased[ix] +=
++ p_res->res_stats[ix];
++ }
++ }
++ }
++}
++
++/* Fetch a videocore handle corresponding to a mapping of the pid+address
++** returns 0 (ie NULL) if no such handle exists in the global map.
++*/
++static unsigned int vmcs_sm_vc_handle_from_pid_and_address(unsigned int pid,
++ unsigned int addr)
++{
++ struct sm_mmap *map = NULL;
++ unsigned int handle = 0;
++
++ if (!sm_state || addr == 0)
++ goto out;
++
++ mutex_lock(&(sm_state->map_lock));
++
++ /* Lookup the resource.
++ */
++ if (!list_empty(&sm_state->map_list)) {
++ list_for_each_entry(map, &sm_state->map_list, map_list) {
++ if (map->res_pid != pid || map->res_addr != addr)
++ continue;
++
++ pr_debug("[%s]: global map %p (pid %u, addr %lx) -> vc-hdl %x (usr-hdl %x)\n",
++ __func__, map, map->res_pid, map->res_addr,
++ map->res_vc_hdl, map->res_usr_hdl);
++
++ handle = map->res_vc_hdl;
++ break;
++ }
++ }
++
++ mutex_unlock(&(sm_state->map_lock));
++
++out:
++ /* Use a debug log here as it may be a valid situation that we query
++ ** for something that is not mapped, we do not want a kernel log each
++ ** time around.
++ **
++ ** There are other error log that would pop up accordingly if someone
++ ** subsequently tries to use something invalid after being told not to
++ ** use it...
++ */
++ if (handle == 0) {
++ pr_debug("[%s]: not a valid map (pid %u, addr %x)\n",
++ __func__, pid, addr);
++ }
++
++ return handle;
++}
++
++/* Fetch a user handle corresponding to a mapping of the pid+address
++** returns 0 (ie NULL) if no such handle exists in the global map.
++*/
++static unsigned int vmcs_sm_usr_handle_from_pid_and_address(unsigned int pid,
++ unsigned int addr)
++{
++ struct sm_mmap *map = NULL;
++ unsigned int handle = 0;
++
++ if (!sm_state || addr == 0)
++ goto out;
++
++ mutex_lock(&(sm_state->map_lock));
++
++ /* Lookup the resource.
++ */
++ if (!list_empty(&sm_state->map_list)) {
++ list_for_each_entry(map, &sm_state->map_list, map_list) {
++ if (map->res_pid != pid || map->res_addr != addr)
++ continue;
++
++ pr_debug("[%s]: global map %p (pid %u, addr %lx) -> usr-hdl %x (vc-hdl %x)\n",
++ __func__, map, map->res_pid, map->res_addr,
++ map->res_usr_hdl, map->res_vc_hdl);
++
++ handle = map->res_usr_hdl;
++ break;
++ }
++ }
++
++ mutex_unlock(&(sm_state->map_lock));
++
++out:
++ /* Use a debug log here as it may be a valid situation that we query
++ * for something that is not mapped yet.
++ *
++ * There are other error log that would pop up accordingly if someone
++ * subsequently tries to use something invalid after being told not to
++ * use it...
++ */
++ if (handle == 0)
++ pr_debug("[%s]: not a valid map (pid %u, addr %x)\n",
++ __func__, pid, addr);
++
++ return handle;
++}
++
++#if defined(DO_NOT_USE)
++/* Fetch an address corresponding to a mapping of the pid+handle
++** returns 0 (ie NULL) if no such address exists in the global map.
++*/
++static unsigned int vmcs_sm_usr_address_from_pid_and_vc_handle(unsigned int pid,
++ unsigned int hdl)
++{
++ struct sm_mmap *map = NULL;
++ unsigned int addr = 0;
++
++ if (sm_state == NULL || hdl == 0)
++ goto out;
++
++ mutex_lock(&(sm_state->map_lock));
++
++ /* Lookup the resource.
++ */
++ if (!list_empty(&sm_state->map_list)) {
++ list_for_each_entry(map, &sm_state->map_list, map_list) {
++ if (map->res_pid != pid || map->res_vc_hdl != hdl)
++ continue;
++
++ pr_debug("[%s]: global map %p (pid %u, vc-hdl %x, usr-hdl %x) -> addr %lx\n",
++ __func__, map, map->res_pid, map->res_vc_hdl,
++ map->res_usr_hdl, map->res_addr);
++
++ addr = map->res_addr;
++ break;
++ }
++ }
++
++ mutex_unlock(&(sm_state->map_lock));
++
++out:
++ /* Use a debug log here as it may be a valid situation that we query
++ ** for something that is not mapped, we do not want a kernel log each
++ ** time around.
++ **
++ ** There are other error log that would pop up accordingly if someone
++ ** subsequently tries to use something invalid after being told not to
++ ** use it...
++ */
++ if (addr == 0)
++ pr_debug("[%s]: not a valid map (pid %u, hdl %x)\n",
++ __func__, pid, hdl);
++
++ return addr;
++}
++#endif
++
++/* Fetch an address corresponding to a mapping of the pid+handle
++** returns 0 (ie NULL) if no such address exists in the global map.
++*/
++static unsigned int vmcs_sm_usr_address_from_pid_and_usr_handle(unsigned int
++ pid,
++ unsigned int
++ hdl)
++{
++ struct sm_mmap *map = NULL;
++ unsigned int addr = 0;
++
++ if (sm_state == NULL || hdl == 0)
++ goto out;
++
++ mutex_lock(&(sm_state->map_lock));
++
++ /* Lookup the resource.
++ */
++ if (!list_empty(&sm_state->map_list)) {
++ list_for_each_entry(map, &sm_state->map_list, map_list) {
++ if (map->res_pid != pid || map->res_usr_hdl != hdl)
++ continue;
++
++ pr_debug("[%s]: global map %p (pid %u, vc-hdl %x, usr-hdl %x) -> addr %lx\n",
++ __func__, map, map->res_pid, map->res_vc_hdl,
++ map->res_usr_hdl, map->res_addr);
++
++ addr = map->res_addr;
++ break;
++ }
++ }
++
++ mutex_unlock(&(sm_state->map_lock));
++
++out:
++ /* Use a debug log here as it may be a valid situation that we query
++ * for something that is not mapped, we do not want a kernel log each
++ * time around.
++ *
++ * There are other error log that would pop up accordingly if someone
++ * subsequently tries to use something invalid after being told not to
++ * use it...
++ */
++ if (addr == 0)
++ pr_debug("[%s]: not a valid map (pid %u, hdl %x)\n", __func__,
++ pid, hdl);
++
++ return addr;
++}
++
++/* Adds a resource mapping to the global data list.
++*/
++static void vmcs_sm_add_map(struct SM_STATE_T *state,
++ struct SM_RESOURCE_T *resource, struct sm_mmap *map)
++{
++ mutex_lock(&(state->map_lock));
++
++ /* Add to the global list of mappings
++ */
++ list_add(&map->map_list, &state->map_list);
++
++ /* Add to the list of mappings for this resource
++ */
++ list_add(&map->resource_map_list, &resource->map_list);
++ resource->map_count++;
++
++ mutex_unlock(&(state->map_lock));
++
++ pr_debug("[%s]: added map %p (pid %u, vc-hdl %x, usr-hdl %x, addr %lx)\n",
++ __func__, map, map->res_pid, map->res_vc_hdl,
++ map->res_usr_hdl, map->res_addr);
++}
++
++/* Removes a resource mapping from the global data list.
++*/
++static void vmcs_sm_remove_map(struct SM_STATE_T *state,
++ struct SM_RESOURCE_T *resource,
++ struct sm_mmap *map)
++{
++ mutex_lock(&(state->map_lock));
++
++ /* Remove from the global list of mappings
++ */
++ list_del(&map->map_list);
++
++ /* Remove from the list of mapping for this resource
++ */
++ list_del(&map->resource_map_list);
++ if (resource->map_count > 0)
++ resource->map_count--;
++
++ mutex_unlock(&(state->map_lock));
++
++ pr_debug("[%s]: removed map %p (pid %d, vc-hdl %x, usr-hdl %x, addr %lx)\n",
++ __func__, map, map->res_pid, map->res_vc_hdl, map->res_usr_hdl,
++ map->res_addr);
++
++ kfree(map);
++}
++
++/* Read callback for the global state proc entry.
++*/
++static int vc_sm_global_state_show(struct seq_file *s, void *v)
++{
++ struct sm_mmap *map = NULL;
++ int map_count = 0;
++
++ if (sm_state == NULL)
++ return 0;
++
++ seq_printf(s, "\nVC-ServiceHandle 0x%x\n",
++ (unsigned int)sm_state->sm_handle);
++
++ /* Log all applicable mapping(s).
++ */
++
++ mutex_lock(&(sm_state->map_lock));
++
++ if (!list_empty(&sm_state->map_list)) {
++ list_for_each_entry(map, &sm_state->map_list, map_list) {
++ map_count++;
++
++ seq_printf(s, "\nMapping 0x%x\n",
++ (unsigned int)map);
++ seq_printf(s, " TGID %u\n",
++ map->res_pid);
++ seq_printf(s, " VC-HDL 0x%x\n",
++ map->res_vc_hdl);
++ seq_printf(s, " USR-HDL 0x%x\n",
++ map->res_usr_hdl);
++ seq_printf(s, " USR-ADDR 0x%lx\n",
++ map->res_addr);
++ }
++ }
++
++ mutex_unlock(&(sm_state->map_lock));
++ seq_printf(s, "\n\nTotal map count: %d\n\n", map_count);
++
++ return 0;
++}
++
++static int vc_sm_global_statistics_show(struct seq_file *s, void *v)
++{
++ int ix;
++
++ /* Global state tracked statistics.
++ */
++ if (sm_state != NULL) {
++ seq_puts(s, "\nDeceased Resources Statistics\n");
++
++ seq_printf(s, "\nNatural Cause (%u occurences)\n",
++ sm_state->res_deceased_cnt);
++ for (ix = 0; ix < END_ATTEMPT; ix++) {
++ if (sm_state->deceased[ix] > 0) {
++ seq_printf(s, " %u\t%s\n",
++ sm_state->deceased[ix],
++ sm_stats_human_read[ix]);
++ }
++ }
++ seq_puts(s, "\n");
++ for (ix = 0; ix < END_ATTEMPT; ix++) {
++ if (sm_state->deceased[ix + END_ATTEMPT] > 0) {
++ seq_printf(s, " %u\tFAILED %s\n",
++ sm_state->deceased[ix + END_ATTEMPT],
++ sm_stats_human_read[ix]);
++ }
++ }
++
++ seq_printf(s, "\nForcefull (%u occurences)\n",
++ sm_state->res_terminated_cnt);
++ for (ix = 0; ix < END_ATTEMPT; ix++) {
++ if (sm_state->terminated[ix] > 0) {
++ seq_printf(s, " %u\t%s\n",
++ sm_state->terminated[ix],
++ sm_stats_human_read[ix]);
++ }
++ }
++ seq_puts(s, "\n");
++ for (ix = 0; ix < END_ATTEMPT; ix++) {
++ if (sm_state->terminated[ix + END_ATTEMPT] > 0) {
++ seq_printf(s, " %u\tFAILED %s\n",
++ sm_state->terminated[ix +
++ END_ATTEMPT],
++ sm_stats_human_read[ix]);
++ }
++ }
++ }
++
++ return 0;
++}
++
++#if 0
++/* Read callback for the statistics proc entry.
++*/
++static int vc_sm_statistics_show(struct seq_file *s, void *v)
++{
++ int ix;
++ struct SM_PRIV_DATA_T *file_data;
++ struct SM_RESOURCE_T *resource;
++ int res_count = 0;
++ struct SM_PDE_T *p_pde;
++
++ p_pde = (struct SM_PDE_T *)(s->private);
++ file_data = (struct SM_PRIV_DATA_T *)(p_pde->priv_data);
++
++ if (file_data == NULL)
++ return 0;
++
++ /* Per process statistics.
++ */
++
++ seq_printf(s, "\nStatistics for TGID %d\n", file_data->pid);
++
++ mutex_lock(&(sm_state->map_lock));
++
++ if (!list_empty(&file_data->resource_list)) {
++ list_for_each_entry(resource, &file_data->resource_list,
++ resource_list) {
++ res_count++;
++
++ seq_printf(s, "\nGUID: 0x%x\n\n",
++ resource->res_guid);
++ for (ix = 0; ix < END_ATTEMPT; ix++) {
++ if (resource->res_stats[ix] > 0) {
++ seq_printf(s,
++ " %u\t%s\n",
++ resource->res_stats[ix],
++ sm_stats_human_read[ix]);
++ }
++ }
++ seq_puts(s, "\n");
++ for (ix = 0; ix < END_ATTEMPT; ix++) {
++ if (resource->res_stats[ix + END_ATTEMPT] > 0) {
++ seq_printf(s,
++ " %u\tFAILED %s\n",
++ resource->res_stats[
++ ix + END_ATTEMPT],
++ sm_stats_human_read[ix]);
++ }
++ }
++ }
++ }
++
++ mutex_unlock(&(sm_state->map_lock));
++
++ seq_printf(s, "\nResources Count %d\n", res_count);
++
++ return 0;
++}
++#endif
++
++#if 0
++/* Read callback for the allocation proc entry. */
++static int vc_sm_alloc_show(struct seq_file *s, void *v)
++{
++ struct SM_PRIV_DATA_T *file_data;
++ struct SM_RESOURCE_T *resource;
++ int alloc_count = 0;
++ struct SM_PDE_T *p_pde;
++
++ p_pde = (struct SM_PDE_T *)(s->private);
++ file_data = (struct SM_PRIV_DATA_T *)(p_pde->priv_data);
++
++ if (!file_data)
++ return 0;
++
++ /* Per process statistics. */
++ seq_printf(s, "\nAllocation for TGID %d\n", file_data->pid);
++
++ mutex_lock(&(sm_state->map_lock));
++
++ if (!list_empty(&file_data->resource_list)) {
++ list_for_each_entry(resource, &file_data->resource_list,
++ resource_list) {
++ alloc_count++;
++
++ seq_printf(s, "\nGUID: 0x%x\n",
++ resource->res_guid);
++ seq_printf(s, "Lock Count: %u\n",
++ resource->lock_count);
++ seq_printf(s, "Mapped: %s\n",
++ (resource->map_count ? "yes" : "no"));
++ seq_printf(s, "VC-handle: 0x%x\n",
++ resource->res_handle);
++ seq_printf(s, "VC-address: 0x%p\n",
++ resource->res_base_mem);
++ seq_printf(s, "VC-size (bytes): %u\n",
++ resource->res_size);
++ seq_printf(s, "Cache: %s\n",
++ sm_cache_map_vector[resource->res_cached]);
++ }
++ }
++
++ mutex_unlock(&(sm_state->map_lock));
++
++ seq_printf(s, "\n\nTotal allocation count: %d\n\n", alloc_count);
++
++ return 0;
++}
++#endif
++
++static int vc_sm_seq_file_show(struct seq_file *s, void *v)
++{
++ struct SM_PDE_T *sm_pde;
++
++ sm_pde = (struct SM_PDE_T *)(s->private);
++
++ if (sm_pde && sm_pde->show)
++ sm_pde->show(s, v);
++
++ return 0;
++}
++
++static int vc_sm_single_open(struct inode *inode, struct file *file)
++{
++ return single_open(file, vc_sm_seq_file_show, inode->i_private);
++}
++
++static const struct file_operations vc_sm_debug_fs_fops = {
++ .open = vc_sm_single_open,
++ .read = seq_read,
++ .llseek = seq_lseek,
++ .release = single_release,
++};
++
++/* Adds a resource to the private data list which tracks all the allocated
++** data.
++*/
++static void vmcs_sm_add_resource(struct SM_PRIV_DATA_T *privdata,
++ struct SM_RESOURCE_T *resource)
++{
++ mutex_lock(&(sm_state->map_lock));
++ list_add(&resource->resource_list, &privdata->resource_list);
++ list_add(&resource->global_resource_list, &sm_state->resource_list);
++ mutex_unlock(&(sm_state->map_lock));
++
++ pr_debug("[%s]: added resource %p (base addr %p, hdl %x, size %u, cache %u)\n",
++ __func__, resource, resource->res_base_mem,
++ resource->res_handle, resource->res_size, resource->res_cached);
++}
++
++/* Locates a resource and acquire a reference on it.
++** The resource won't be deleted while there is a reference on it.
++*/
++static struct SM_RESOURCE_T *vmcs_sm_acquire_resource(struct SM_PRIV_DATA_T
++ *private,
++ unsigned int res_guid)
++{
++ struct SM_RESOURCE_T *resource, *ret = NULL;
++
++ mutex_lock(&(sm_state->map_lock));
++
++ list_for_each_entry(resource, &private->resource_list, resource_list) {
++ if (resource->res_guid != res_guid)
++ continue;
++
++ pr_debug("[%s]: located resource %p (guid: %x, base addr %p, hdl %x, size %u, cache %u)\n",
++ __func__, resource, resource->res_guid,
++ resource->res_base_mem, resource->res_handle,
++ resource->res_size, resource->res_cached);
++ resource->ref_count++;
++ ret = resource;
++ break;
++ }
++
++ mutex_unlock(&(sm_state->map_lock));
++
++ return ret;
++}
++
++/* Locates a resource and acquire a reference on it.
++** The resource won't be deleted while there is a reference on it.
++*/
++static struct SM_RESOURCE_T *vmcs_sm_acquire_first_resource(
++ struct SM_PRIV_DATA_T *private)
++{
++ struct SM_RESOURCE_T *resource, *ret = NULL;
++
++ mutex_lock(&(sm_state->map_lock));
++
++ list_for_each_entry(resource, &private->resource_list, resource_list) {
++ pr_debug("[%s]: located resource %p (guid: %x, base addr %p, hdl %x, size %u, cache %u)\n",
++ __func__, resource, resource->res_guid,
++ resource->res_base_mem, resource->res_handle,
++ resource->res_size, resource->res_cached);
++ resource->ref_count++;
++ ret = resource;
++ break;
++ }
++
++ mutex_unlock(&(sm_state->map_lock));
++
++ return ret;
++}
++
++/* Locates a resource and acquire a reference on it.
++** The resource won't be deleted while there is a reference on it.
++*/
++static struct SM_RESOURCE_T *vmcs_sm_acquire_global_resource(unsigned int
++ res_guid)
++{
++ struct SM_RESOURCE_T *resource, *ret = NULL;
++
++ mutex_lock(&(sm_state->map_lock));
++
++ list_for_each_entry(resource, &sm_state->resource_list,
++ global_resource_list) {
++ if (resource->res_guid != res_guid)
++ continue;
++
++ pr_debug("[%s]: located resource %p (guid: %x, base addr %p, hdl %x, size %u, cache %u)\n",
++ __func__, resource, resource->res_guid,
++ resource->res_base_mem, resource->res_handle,
++ resource->res_size, resource->res_cached);
++ resource->ref_count++;
++ ret = resource;
++ break;
++ }
++
++ mutex_unlock(&(sm_state->map_lock));
++
++ return ret;
++}
++
++/* Release a previously acquired resource.
++** The resource will be deleted when its refcount reaches 0.
++*/
++static void vmcs_sm_release_resource(struct SM_RESOURCE_T *resource, int force)
++{
++ struct SM_PRIV_DATA_T *private = resource->private;
++ struct sm_mmap *map, *map_tmp;
++ struct SM_RESOURCE_T *res_tmp;
++ int ret;
++
++ mutex_lock(&(sm_state->map_lock));
++
++ if (--resource->ref_count) {
++ if (force)
++ pr_err("[%s]: resource %p in use\n", __func__, resource);
++
++ mutex_unlock(&(sm_state->map_lock));
++ return;
++ }
++
++ /* Time to free the resource. Start by removing it from the list */
++ list_del(&resource->resource_list);
++ list_del(&resource->global_resource_list);
++
++ /* Walk the global resource list, find out if the resource is used
++ * somewhere else. In which case we don't want to delete it.
++ */
++ list_for_each_entry(res_tmp, &sm_state->resource_list,
++ global_resource_list) {
++ if (res_tmp->res_handle == resource->res_handle) {
++ resource->res_handle = 0;
++ break;
++ }
++ }
++
++ mutex_unlock(&(sm_state->map_lock));
++
++ pr_debug("[%s]: freeing data - guid %x, hdl %x, base address %p\n",
++ __func__, resource->res_guid, resource->res_handle,
++ resource->res_base_mem);
++ resource->res_stats[FREE]++;
++
++ /* Make sure the resource we're removing is unmapped first */
++ if (resource->map_count && !list_empty(&resource->map_list)) {
++ down_write(&current->mm->mmap_sem);
++ list_for_each_entry_safe(map, map_tmp, &resource->map_list,
++ resource_map_list) {
++ ret =
++ do_munmap(current->mm, map->res_addr,
++ resource->res_size);
++ if (ret) {
++ pr_err("[%s]: could not unmap resource %p\n",
++ __func__, resource);
++ }
++ }
++ up_write(&current->mm->mmap_sem);
++ }
++
++ /* Free up the videocore allocated resource.
++ */
++ if (resource->res_handle) {
++ VC_SM_FREE_T free = {
++ resource->res_handle, resource->res_base_mem
++ };
++ int status = vc_vchi_sm_free(sm_state->sm_handle, &free,
++ &private->int_trans_id);
++ if (status != 0 && status != -EINTR) {
++ pr_err("[%s]: failed to free memory on videocore (status: %u, trans_id: %u)\n",
++ __func__, status, private->int_trans_id);
++ resource->res_stats[FREE_FAIL]++;
++ ret = -EPERM;
++ }
++ }
++
++ /* Free up the shared resource.
++ */
++ if (resource->res_shared)
++ vmcs_sm_release_resource(resource->res_shared, 0);
++
++ /* Free up the local resource tracking this allocation.
++ */
++ vc_sm_resource_deceased(resource, force);
++ kfree(resource);
++}
++
++/* Dump the map table for the driver. If process is -1, dumps the whole table,
++** if process is a valid pid (non -1) dump only the entries associated with the
++** pid of interest.
++*/
++static void vmcs_sm_host_walk_map_per_pid(int pid)
++{
++ struct sm_mmap *map = NULL;
++
++ /* Make sure the device was started properly.
++ */
++ if (sm_state == NULL) {
++ pr_err("[%s]: invalid device\n", __func__);
++ return;
++ }
++
++ mutex_lock(&(sm_state->map_lock));
++
++ /* Log all applicable mapping(s).
++ */
++ if (!list_empty(&sm_state->map_list)) {
++ list_for_each_entry(map, &sm_state->map_list, map_list) {
++ if (pid == -1 || map->res_pid == pid) {
++ pr_info("[%s]: tgid: %u - vc-hdl: %x, usr-hdl: %x, usr-addr: %lx\n",
++ __func__, map->res_pid, map->res_vc_hdl,
++ map->res_usr_hdl, map->res_addr);
++ }
++ }
++ }
++
++ mutex_unlock(&(sm_state->map_lock));
++
++ return;
++}
++
++/* Dump the allocation table from host side point of view. This only dumps the
++** data allocated for this process/device referenced by the file_data.
++*/
++static void vmcs_sm_host_walk_alloc(struct SM_PRIV_DATA_T *file_data)
++{
++ struct SM_RESOURCE_T *resource = NULL;
++
++ /* Make sure the device was started properly.
++ */
++ if ((sm_state == NULL) || (file_data == NULL)) {
++ pr_err("[%s]: invalid device\n", __func__);
++ return;
++ }
++
++ mutex_lock(&(sm_state->map_lock));
++
++ if (!list_empty(&file_data->resource_list)) {
++ list_for_each_entry(resource, &file_data->resource_list,
++ resource_list) {
++ pr_info("[%s]: guid: %x - hdl: %x, vc-mem: %p, size: %u, cache: %u\n",
++ __func__, resource->res_guid, resource->res_handle,
++ resource->res_base_mem, resource->res_size,
++ resource->res_cached);
++ }
++ }
++
++ mutex_unlock(&(sm_state->map_lock));
++
++ return;
++}
++
++/* Create support for private data tracking.
++*/
++static struct SM_PRIV_DATA_T *vc_sm_create_priv_data(pid_t id)
++{
++ char alloc_name[32];
++ struct SM_PRIV_DATA_T *file_data = NULL;
++
++ /* Allocate private structure. */
++ file_data = kzalloc(sizeof(*file_data), GFP_KERNEL);
++
++ if (!file_data) {
++ pr_err("[%s]: cannot allocate file data\n", __func__);
++ goto out;
++ }
++
++ snprintf(alloc_name, sizeof(alloc_name), "%d", id);
++
++ INIT_LIST_HEAD(&file_data->resource_list);
++ file_data->pid = id;
++ file_data->dir_pid = debugfs_create_dir(alloc_name,
++ sm_state->dir_alloc);
++#if 0
++ /* TODO: fix this to support querying statistics per pid */
++
++ if (IS_ERR_OR_NULL(file_data->dir_pid)) {
++ file_data->dir_pid = NULL;
++ } else {
++ struct dentry *dir_entry;
++
++ dir_entry = debugfs_create_file(VC_SM_RESOURCES, S_IRUGO,
++ file_data->dir_pid, file_data,
++ vc_sm_debug_fs_fops);
++
++ file_data->dir_res.dir_entry = dir_entry;
++ file_data->dir_res.priv_data = file_data;
++ file_data->dir_res.show = &vc_sm_alloc_show;
++
++ dir_entry = debugfs_create_file(VC_SM_STATS, S_IRUGO,
++ file_data->dir_pid, file_data,
++ vc_sm_debug_fs_fops);
++
++ file_data->dir_res.dir_entry = dir_entry;
++ file_data->dir_res.priv_data = file_data;
++ file_data->dir_res.show = &vc_sm_statistics_show;
++ }
++ pr_debug("[%s]: private data allocated %p\n", __func__, file_data);
++
++#endif
++out:
++ return file_data;
++}
++
++/* Open the device. Creates a private state to help track all allocation
++** associated with this device.
++*/
++static int vc_sm_open(struct inode *inode, struct file *file)
++{
++ int ret = 0;
++
++ /* Make sure the device was started properly.
++ */
++ if (!sm_state) {
++ pr_err("[%s]: invalid device\n", __func__);
++ ret = -EPERM;
++ goto out;
++ }
++
++ file->private_data = vc_sm_create_priv_data(current->tgid);
++ if (file->private_data == NULL) {
++ pr_err("[%s]: failed to create data tracker\n", __func__);
++
++ ret = -ENOMEM;
++ goto out;
++ }
++
++out:
++ return ret;
++}
++
++/* Close the device. Free up all resources still associated with this device
++** at the time.
++*/
++static int vc_sm_release(struct inode *inode, struct file *file)
++{
++ struct SM_PRIV_DATA_T *file_data =
++ (struct SM_PRIV_DATA_T *)file->private_data;
++ struct SM_RESOURCE_T *resource;
++ int ret = 0;
++
++ /* Make sure the device was started properly.
++ */
++ if (sm_state == NULL || file_data == NULL) {
++ pr_err("[%s]: invalid device\n", __func__);
++ ret = -EPERM;
++ goto out;
++ }
++
++ pr_debug("[%s]: using private data %p\n", __func__, file_data);
++
++ if (file_data->restart_sys == -EINTR) {
++ VC_SM_ACTION_CLEAN_T action_clean;
++
++ pr_debug("[%s]: releasing following EINTR on %u (trans_id: %u) (likely due to signal)...\n",
++ __func__, file_data->int_action,
++ file_data->int_trans_id);
++
++ action_clean.res_action = file_data->int_action;
++ action_clean.action_trans_id = file_data->int_trans_id;
++
++ vc_vchi_sm_clean_up(sm_state->sm_handle, &action_clean);
++ }
++
++ while ((resource = vmcs_sm_acquire_first_resource(file_data)) != NULL) {
++ vmcs_sm_release_resource(resource, 0);
++ vmcs_sm_release_resource(resource, 1);
++ }
++
++ /* Remove the corresponding proc entry. */
++ debugfs_remove_recursive(file_data->dir_pid);
++
++ /* Terminate the private data.
++ */
++ kfree(file_data);
++
++out:
++ return ret;
++}
++
++static void vcsm_vma_open(struct vm_area_struct *vma)
++{
++ struct sm_mmap *map = (struct sm_mmap *)vma->vm_private_data;
++
++ pr_debug("[%s]: virt %lx-%lx, pid %i, pfn %i\n",
++ __func__, vma->vm_start, vma->vm_end, (int)current->tgid,
++ (int)vma->vm_pgoff);
++
++ map->ref_count++;
++}
++
++static void vcsm_vma_close(struct vm_area_struct *vma)
++{
++ struct sm_mmap *map = (struct sm_mmap *)vma->vm_private_data;
++
++ pr_debug("[%s]: virt %lx-%lx, pid %i, pfn %i\n",
++ __func__, vma->vm_start, vma->vm_end, (int)current->tgid,
++ (int)vma->vm_pgoff);
++
++ map->ref_count--;
++
++ /* Remove from the map table.
++ */
++ if (map->ref_count == 0)
++ vmcs_sm_remove_map(sm_state, map->resource, map);
++}
++
++static int vcsm_vma_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
++{
++ struct sm_mmap *map = (struct sm_mmap *)vma->vm_private_data;
++ struct SM_RESOURCE_T *resource = map->resource;
++ pgoff_t page_offset;
++ unsigned long pfn;
++ int ret = 0;
++
++ /* Lock the resource if necessary.
++ */
++ if (!resource->lock_count) {
++ VC_SM_LOCK_UNLOCK_T lock_unlock;
++ VC_SM_LOCK_RESULT_T lock_result;
++ int status;
++
++ lock_unlock.res_handle = resource->res_handle;
++ lock_unlock.res_mem = resource->res_base_mem;
++
++ pr_debug("[%s]: attempt to lock data - hdl %x, base address %p\n",
++ __func__, lock_unlock.res_handle, lock_unlock.res_mem);
++
++ /* Lock the videocore allocated resource.
++ */
++ status = vc_vchi_sm_lock(sm_state->sm_handle,
++ &lock_unlock, &lock_result, 0);
++ if ((status != 0) ||
++ ((status == 0) && (lock_result.res_mem == NULL))) {
++ pr_err("[%s]: failed to lock memory on videocore (status: %u)\n",
++ __func__, status);
++ resource->res_stats[LOCK_FAIL]++;
++ return VM_FAULT_SIGBUS;
++ }
++
++ pfn = vcaddr_to_pfn((unsigned long)resource->res_base_mem);
++ outer_inv_range(__pfn_to_phys(pfn),
++ __pfn_to_phys(pfn) + resource->res_size);
++
++ resource->res_stats[LOCK]++;
++ resource->lock_count++;
++
++ /* Keep track of the new base memory.
++ */
++ if ((lock_result.res_mem != NULL) &&
++ (lock_result.res_old_mem != NULL) &&
++ (lock_result.res_mem != lock_result.res_old_mem)) {
++ resource->res_base_mem = lock_result.res_mem;
++ }
++ }
++
++ /* We don't use vmf->pgoff since that has the fake offset */
++ page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start);
++ pfn = (uint32_t)resource->res_base_mem & 0x3FFFFFFF;
++ pfn += mm_vc_mem_phys_addr;
++ pfn += page_offset;
++ pfn >>= PAGE_SHIFT;
++
++ /* Finally, remap it */
++ ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
++
++ switch (ret) {
++ case 0:
++ case -ERESTARTSYS:
++ return VM_FAULT_NOPAGE;
++ case -ENOMEM:
++ case -EAGAIN:
++ return VM_FAULT_OOM;
++ default:
++ return VM_FAULT_SIGBUS;
++ }
++}
++
++static struct vm_operations_struct vcsm_vm_ops = {
++ .open = vcsm_vma_open,
++ .close = vcsm_vma_close,
++ .fault = vcsm_vma_fault,
++};
++
++/* Walks a VMA and clean each valid page from the cache */
++static void vcsm_vma_cache_clean_page_range(unsigned long addr,
++ unsigned long end)
++{
++ pgd_t *pgd;
++ pud_t *pud;
++ pmd_t *pmd;
++ pte_t *pte;
++ unsigned long pgd_next, pud_next, pmd_next;
++
++ if (addr >= end)
++ return;
++
++ /* Walk PGD */
++ pgd = pgd_offset(current->mm, addr);
++ do {
++ pgd_next = pgd_addr_end(addr, end);
++
++ if (pgd_none(*pgd) || pgd_bad(*pgd))
++ continue;
++
++ /* Walk PUD */
++ pud = pud_offset(pgd, addr);
++ do {
++ pud_next = pud_addr_end(addr, pgd_next);
++ if (pud_none(*pud) || pud_bad(*pud))
++ continue;
++
++ /* Walk PMD */
++ pmd = pmd_offset(pud, addr);
++ do {
++ pmd_next = pmd_addr_end(addr, pud_next);
++ if (pmd_none(*pmd) || pmd_bad(*pmd))
++ continue;
++
++ /* Walk PTE */
++ pte = pte_offset_map(pmd, addr);
++ do {
++ if (pte_none(*pte)
++ || !pte_present(*pte))
++ continue;
++
++ /* Clean + invalidate */
++ dmac_flush_range((const void *) addr,
++ (const void *)
++ (addr + PAGE_SIZE));
++
++ } while (pte++, addr +=
++ PAGE_SIZE, addr != pmd_next);
++ pte_unmap(pte);
++
++ } while (pmd++, addr = pmd_next, addr != pud_next);
++
++ } while (pud++, addr = pud_next, addr != pgd_next);
++ } while (pgd++, addr = pgd_next, addr != end);
++}
++
++/* Map an allocated data into something that the user space.
++*/
++static int vc_sm_mmap(struct file *file, struct vm_area_struct *vma)
++{
++ int ret = 0;
++ struct SM_PRIV_DATA_T *file_data =
++ (struct SM_PRIV_DATA_T *)file->private_data;
++ struct SM_RESOURCE_T *resource = NULL;
++ struct sm_mmap *map = NULL;
++
++ /* Make sure the device was started properly.
++ */
++ if ((sm_state == NULL) || (file_data == NULL)) {
++ pr_err("[%s]: invalid device\n", __func__);
++ return -EPERM;
++ }
++
++ pr_debug("[%s]: private data %p, guid %x\n", __func__, file_data,
++ ((unsigned int)vma->vm_pgoff << PAGE_SHIFT));
++
++ /* We lookup to make sure that the data we are being asked to mmap is
++ ** something that we allocated.
++ **
++ ** We use the offset information as the key to tell us which resource
++ ** we are mapping.
++ */
++ resource = vmcs_sm_acquire_resource(file_data,
++ ((unsigned int)vma->vm_pgoff <<
++ PAGE_SHIFT));
++ if (resource == NULL) {
++ pr_err("[%s]: failed to locate resource for guid %x\n", __func__,
++ ((unsigned int)vma->vm_pgoff << PAGE_SHIFT));
++ return -ENOMEM;
++ }
++
++ pr_debug("[%s]: guid %x, tgid %u, %u, %u\n",
++ __func__, resource->res_guid, current->tgid, resource->pid,
++ file_data->pid);
++
++ /* Check permissions.
++ */
++ if (resource->pid && (resource->pid != current->tgid)) {
++ pr_err("[%s]: current tgid %u != %u owner\n",
++ __func__, current->tgid, resource->pid);
++ ret = -EPERM;
++ goto error;
++ }
++
++ /* Verify that what we are asked to mmap is proper.
++ */
++ if (resource->res_size != (unsigned int)(vma->vm_end - vma->vm_start)) {
++ pr_err("[%s]: size inconsistency (resource: %u - mmap: %u)\n",
++ __func__,
++ resource->res_size,
++ (unsigned int)(vma->vm_end - vma->vm_start));
++
++ ret = -EINVAL;
++ goto error;
++ }
++
++ /* Keep track of the tuple in the global resource list such that one
++ * can do a mapping lookup for address/memory handle.
++ */
++ map = kzalloc(sizeof(*map), GFP_KERNEL);
++ if (map == NULL) {
++ pr_err("[%s]: failed to allocate global tracking resource\n",
++ __func__);
++ ret = -ENOMEM;
++ goto error;
++ }
++
++ map->res_pid = current->tgid;
++ map->res_vc_hdl = resource->res_handle;
++ map->res_usr_hdl = resource->res_guid;
++ map->res_addr = (long unsigned int)vma->vm_start;
++ map->resource = resource;
++ map->vma = vma;
++ vmcs_sm_add_map(sm_state, resource, map);
++
++ /* We are not actually mapping the pages, we just provide a fault
++ ** handler to allow pages to be mapped when accessed
++ */
++ vma->vm_flags |=
++ VM_IO | VM_PFNMAP | VM_DONTCOPY | VM_DONTEXPAND;
++ vma->vm_ops = &vcsm_vm_ops;
++ vma->vm_private_data = map;
++
++ /* vm_pgoff is the first PFN of the mapped memory */
++ vma->vm_pgoff = (unsigned long)resource->res_base_mem & 0x3FFFFFFF;
++ vma->vm_pgoff += mm_vc_mem_phys_addr;
++ vma->vm_pgoff >>= PAGE_SHIFT;
++
++ if ((resource->res_cached == VMCS_SM_CACHE_NONE) ||
++ (resource->res_cached == VMCS_SM_CACHE_VC)) {
++ /* Allocated non host cached memory, honour it.
++ */
++ vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
++ }
++
++ pr_debug("[%s]: resource %p (guid %x) - cnt %u, base address %p, handle %x, size %u (%u), cache %u\n",
++ __func__,
++ resource, resource->res_guid, resource->lock_count,
++ resource->res_base_mem, resource->res_handle,
++ resource->res_size, (unsigned int)(vma->vm_end - vma->vm_start),
++ resource->res_cached);
++
++ pr_debug("[%s]: resource %p (base address %p, handle %x) - map-count %d, usr-addr %x\n",
++ __func__, resource, resource->res_base_mem,
++ resource->res_handle, resource->map_count,
++ (unsigned int)vma->vm_start);
++
++ vcsm_vma_open(vma);
++ resource->res_stats[MAP]++;
++ vmcs_sm_release_resource(resource, 0);
++ return 0;
++
++error:
++ vmcs_sm_release_resource(resource, 0);
++ resource->res_stats[MAP_FAIL]++;
++ return ret;
++}
++
++/* Allocate a shared memory handle and block.
++*/
++int vc_sm_ioctl_alloc(struct SM_PRIV_DATA_T *private,
++ struct vmcs_sm_ioctl_alloc *ioparam)
++{
++ int ret = 0;
++ int status;
++ struct SM_RESOURCE_T *resource;
++ VC_SM_ALLOC_T alloc = { 0 };
++ VC_SM_ALLOC_RESULT_T result = { 0 };
++
++ /* Setup our allocation parameters */
++ alloc.type = ((ioparam->cached == VMCS_SM_CACHE_VC)
++ || (ioparam->cached ==
++ VMCS_SM_CACHE_BOTH)) ? VC_SM_ALLOC_CACHED :
++ VC_SM_ALLOC_NON_CACHED;
++ alloc.base_unit = ioparam->size;
++ alloc.num_unit = ioparam->num;
++ alloc.allocator = current->tgid;
++ /* Align to kernel page size */
++ alloc.alignement = 4096;
++ /* Align the size to the kernel page size */
++ alloc.base_unit =
++ (alloc.base_unit + alloc.alignement - 1) & ~(alloc.alignement - 1);
++ if (*ioparam->name) {
++ memcpy(alloc.name, ioparam->name, sizeof(alloc.name) - 1);
++ } else {
++ memcpy(alloc.name, VMCS_SM_RESOURCE_NAME_DEFAULT,
++ sizeof(VMCS_SM_RESOURCE_NAME_DEFAULT));
++ }
++
++ pr_debug("[%s]: attempt to allocate \"%s\" data - type %u, base %u (%u), num %u, alignement %u\n",
++ __func__, alloc.name, alloc.type, ioparam->size,
++ alloc.base_unit, alloc.num_unit, alloc.alignement);
++
++ /* Allocate local resource to track this allocation.
++ */
++ resource = kzalloc(sizeof(*resource), GFP_KERNEL);
++ if (!resource) {
++ ret = -ENOMEM;
++ goto error;
++ }
++ INIT_LIST_HEAD(&resource->map_list);
++ resource->ref_count++;
++ resource->pid = current->tgid;
++
++ /* Allocate the videocore resource.
++ */
++ status = vc_vchi_sm_alloc(sm_state->sm_handle, &alloc, &result,
++ &private->int_trans_id);
++ if (status == -EINTR) {
++ pr_debug("[%s]: requesting allocate memory action restart (trans_id: %u)\n",
++ __func__, private->int_trans_id);
++ ret = -ERESTARTSYS;
++ private->restart_sys = -EINTR;
++ private->int_action = VC_SM_MSG_TYPE_ALLOC;
++ goto error;
++ } else if (status != 0 || (status == 0 && result.res_mem == NULL)) {
++ pr_err("[%s]: failed to allocate memory on videocore (status: %u, trans_id: %u)\n",
++ __func__, status, private->int_trans_id);
++ ret = -ENOMEM;
++ resource->res_stats[ALLOC_FAIL]++;
++ goto error;
++ }
++
++ /* Keep track of the resource we created.
++ */
++ resource->private = private;
++ resource->res_handle = result.res_handle;
++ resource->res_base_mem = result.res_mem;
++ resource->res_size = alloc.base_unit * alloc.num_unit;
++ resource->res_cached = ioparam->cached;
++
++ /* Kernel/user GUID. This global identifier is used for mmap'ing the
++ * allocated region from user space, it is passed as the mmap'ing
++ * offset, we use it to 'hide' the videocore handle/address.
++ */
++ mutex_lock(&sm_state->lock);
++ resource->res_guid = ++sm_state->guid;
++ mutex_unlock(&sm_state->lock);
++ resource->res_guid <<= PAGE_SHIFT;
++
++ vmcs_sm_add_resource(private, resource);
++
++ pr_debug("[%s]: allocated data - guid %x, hdl %x, base address %p, size %d, cache %d\n",
++ __func__, resource->res_guid, resource->res_handle,
++ resource->res_base_mem, resource->res_size,
++ resource->res_cached);
++
++ /* We're done */
++ resource->res_stats[ALLOC]++;
++ ioparam->handle = resource->res_guid;
++ return 0;
++
++error:
++ pr_err("[%s]: failed to allocate \"%s\" data (%i) - type %u, base %u (%u), num %u, alignment %u\n",
++ __func__, alloc.name, ret, alloc.type, ioparam->size,
++ alloc.base_unit, alloc.num_unit, alloc.alignement);
++ if (resource != NULL) {
++ vc_sm_resource_deceased(resource, 1);
++ kfree(resource);
++ }
++ return ret;
++}
++
++/* Share an allocate memory handle and block.
++*/
++int vc_sm_ioctl_alloc_share(struct SM_PRIV_DATA_T *private,
++ struct vmcs_sm_ioctl_alloc_share *ioparam)
++{
++ struct SM_RESOURCE_T *resource, *shared_resource;
++ int ret = 0;
++
++ pr_debug("[%s]: attempt to share resource %u\n", __func__,
++ ioparam->handle);
++
++ shared_resource = vmcs_sm_acquire_global_resource(ioparam->handle);
++ if (shared_resource == NULL) {
++ ret = -ENOMEM;
++ goto error;
++ }
++
++ /* Allocate local resource to track this allocation.
++ */
++ resource = kzalloc(sizeof(*resource), GFP_KERNEL);
++ if (resource == NULL) {
++ pr_err("[%s]: failed to allocate local tracking resource\n",
++ __func__);
++ ret = -ENOMEM;
++ goto error;
++ }
++ INIT_LIST_HEAD(&resource->map_list);
++ resource->ref_count++;
++ resource->pid = current->tgid;
++
++ /* Keep track of the resource we created.
++ */
++ resource->private = private;
++ resource->res_handle = shared_resource->res_handle;
++ resource->res_base_mem = shared_resource->res_base_mem;
++ resource->res_size = shared_resource->res_size;
++ resource->res_cached = shared_resource->res_cached;
++ resource->res_shared = shared_resource;
++
++ mutex_lock(&sm_state->lock);
++ resource->res_guid = ++sm_state->guid;
++ mutex_unlock(&sm_state->lock);
++ resource->res_guid <<= PAGE_SHIFT;
++
++ vmcs_sm_add_resource(private, resource);
++
++ pr_debug("[%s]: allocated data - guid %x, hdl %x, base address %p, size %d, cache %d\n",
++ __func__, resource->res_guid, resource->res_handle,
++ resource->res_base_mem, resource->res_size,
++ resource->res_cached);
++
++ /* We're done */
++ resource->res_stats[ALLOC]++;
++ ioparam->handle = resource->res_guid;
++ ioparam->size = resource->res_size;
++ return 0;
++
++error:
++ pr_err("[%s]: failed to share %u\n", __func__, ioparam->handle);
++ if (shared_resource != NULL)
++ vmcs_sm_release_resource(shared_resource, 0);
++
++ return ret;
++}
++
++/* Free a previously allocated shared memory handle and block.
++*/
++static int vc_sm_ioctl_free(struct SM_PRIV_DATA_T *private,
++ struct vmcs_sm_ioctl_free *ioparam)
++{
++ struct SM_RESOURCE_T *resource =
++ vmcs_sm_acquire_resource(private, ioparam->handle);
++
++ if (resource == NULL) {
++ pr_err("[%s]: resource for guid %u does not exist\n", __func__,
++ ioparam->handle);
++ return -EINVAL;
++ }
++
++ /* Check permissions.
++ */
++ if (resource->pid && (resource->pid != current->tgid)) {
++ pr_err("[%s]: current tgid %u != %u owner\n",
++ __func__, current->tgid, resource->pid);
++ vmcs_sm_release_resource(resource, 0);
++ return -EPERM;
++ }
++
++ vmcs_sm_release_resource(resource, 0);
++ vmcs_sm_release_resource(resource, 0);
++ return 0;
++}
++
++/* Resize a previously allocated shared memory handle and block.
++*/
++static int vc_sm_ioctl_resize(struct SM_PRIV_DATA_T *private,
++ struct vmcs_sm_ioctl_resize *ioparam)
++{
++ int ret = 0;
++ int status;
++ VC_SM_RESIZE_T resize;
++ struct SM_RESOURCE_T *resource;
++
++ /* Locate resource from GUID.
++ */
++ resource = vmcs_sm_acquire_resource(private, ioparam->handle);
++ if (!resource) {
++ pr_err("[%s]: failed resource - guid %x\n",
++ __func__, ioparam->handle);
++ ret = -EFAULT;
++ goto error;
++ }
++
++ /* If the resource is locked, its reference count will be not NULL,
++ ** in which case we will not be allowed to resize it anyways, so
++ ** reject the attempt here.
++ */
++ if (resource->lock_count != 0) {
++ pr_err("[%s]: cannot resize - guid %x, ref-cnt %d\n",
++ __func__, ioparam->handle, resource->lock_count);
++ ret = -EFAULT;
++ goto error;
++ }
++
++ /* Check permissions.
++ */
++ if (resource->pid && (resource->pid != current->tgid)) {
++ pr_err("[%s]: current tgid %u != %u owner\n", __func__,
++ current->tgid, resource->pid);
++ ret = -EPERM;
++ goto error;
++ }
++
++ if (resource->map_count != 0) {
++ pr_err("[%s]: cannot resize - guid %x, ref-cnt %d\n",
++ __func__, ioparam->handle, resource->map_count);
++ ret = -EFAULT;
++ goto error;
++ }
++
++ resize.res_handle = resource->res_handle;
++ resize.res_mem = resource->res_base_mem;
++ resize.res_new_size = ioparam->new_size;
++
++ pr_debug("[%s]: attempt to resize data - guid %x, hdl %x, base address %p\n",
++ __func__, ioparam->handle, resize.res_handle, resize.res_mem);
++
++ /* Resize the videocore allocated resource.
++ */
++ status = vc_vchi_sm_resize(sm_state->sm_handle, &resize,
++ &private->int_trans_id);
++ if (status == -EINTR) {
++ pr_debug("[%s]: requesting resize memory action restart (trans_id: %u)\n",
++ __func__, private->int_trans_id);
++ ret = -ERESTARTSYS;
++ private->restart_sys = -EINTR;
++ private->int_action = VC_SM_MSG_TYPE_RESIZE;
++ goto error;
++ } else if (status != 0) {
++ pr_err("[%s]: failed to resize memory on videocore (status: %u, trans_id: %u)\n",
++ __func__, status, private->int_trans_id);
++ ret = -EPERM;
++ goto error;
++ }
++
++ pr_debug("[%s]: success to resize data - hdl %x, size %d -> %d\n",
++ __func__, resize.res_handle, resource->res_size,
++ resize.res_new_size);
++
++ /* Successfully resized, save the information and inform the user.
++ */
++ ioparam->old_size = resource->res_size;
++ resource->res_size = resize.res_new_size;
++
++error:
++ if (resource)
++ vmcs_sm_release_resource(resource, 0);
++
++ return ret;
++}
++
++/* Lock a previously allocated shared memory handle and block.
++*/
++static int vc_sm_ioctl_lock(struct SM_PRIV_DATA_T *private,
++ struct vmcs_sm_ioctl_lock_unlock *ioparam,
++ int change_cache, enum vmcs_sm_cache_e cache_type,
++ unsigned int vc_addr)
++{
++ int status;
++ VC_SM_LOCK_UNLOCK_T lock;
++ VC_SM_LOCK_RESULT_T result;
++ struct SM_RESOURCE_T *resource;
++ int ret = 0;
++ struct sm_mmap *map, *map_tmp;
++ long unsigned int phys_addr;
++
++ map = NULL;
++
++ /* Locate resource from GUID.
++ */
++ resource = vmcs_sm_acquire_resource(private, ioparam->handle);
++ if (resource == NULL) {
++ ret = -EINVAL;
++ goto error;
++ }
++
++ /* Check permissions.
++ */
++ if (resource->pid && (resource->pid != current->tgid)) {
++ pr_err("[%s]: current tgid %u != %u owner\n", __func__,
++ current->tgid, resource->pid);
++ ret = -EPERM;
++ goto error;
++ }
++
++ lock.res_handle = resource->res_handle;
++ lock.res_mem = resource->res_base_mem;
++
++ /* Take the lock and get the address to be mapped.
++ */
++ if (vc_addr == 0) {
++ pr_debug("[%s]: attempt to lock data - guid %x, hdl %x, base address %p\n",
++ __func__, ioparam->handle, lock.res_handle,
++ lock.res_mem);
++
++ /* Lock the videocore allocated resource.
++ */
++ status = vc_vchi_sm_lock(sm_state->sm_handle, &lock, &result,
++ &private->int_trans_id);
++ if (status == -EINTR) {
++ pr_debug("[%s]: requesting lock memory action restart (trans_id: %u)\n",
++ __func__, private->int_trans_id);
++ ret = -ERESTARTSYS;
++ private->restart_sys = -EINTR;
++ private->int_action = VC_SM_MSG_TYPE_LOCK;
++ goto error;
++ } else if (status != 0 ||
++ (status == 0 && result.res_mem == NULL)) {
++ pr_err("[%s]: failed to lock memory on videocore (status: %u, trans_id: %u)\n",
++ __func__, status, private->int_trans_id);
++ ret = -EPERM;
++ resource->res_stats[LOCK_FAIL]++;
++ goto error;
++ }
++
++ pr_debug("[%s]: succeed to lock data - hdl %x, base address %p (%p), ref-cnt %d\n",
++ __func__, lock.res_handle, result.res_mem,
++ lock.res_mem, resource->lock_count);
++ }
++ /* Lock assumed taken already, address to be mapped is known.
++ */
++ else
++ resource->res_base_mem = (void *)vc_addr;
++
++ resource->res_stats[LOCK]++;
++ resource->lock_count++;
++
++ /* Keep track of the new base memory allocation if it has changed.
++ */
++ if ((vc_addr == 0) &&
++ (result.res_mem != NULL) &&
++ (result.res_old_mem != NULL) &&
++ (result.res_mem != result.res_old_mem)) {
++ resource->res_base_mem = result.res_mem;
++
++ /* Kernel allocated resources.
++ */
++ if (resource->pid == 0) {
++ if (!list_empty(&resource->map_list)) {
++ list_for_each_entry_safe(map, map_tmp,
++ &resource->map_list,
++ resource_map_list) {
++ if (map->res_addr) {
++ iounmap((void *)map->res_addr);
++ map->res_addr = 0;
++
++ vmcs_sm_remove_map(sm_state,
++ map->resource,
++ map);
++ break;
++ }
++ }
++ }
++ }
++ }
++
++ if (change_cache)
++ resource->res_cached = cache_type;
++
++ if (resource->map_count) {
++ ioparam->addr =
++ vmcs_sm_usr_address_from_pid_and_usr_handle(
++ current->tgid, ioparam->handle);
++
++ pr_debug("[%s] map_count %d private->pid %d current->tgid %d hnd %x addr %u\n",
++ __func__, resource->map_count, private->pid,
++ current->tgid, ioparam->handle, ioparam->addr);
++ } else {
++ /* Kernel allocated resources.
++ */
++ if (resource->pid == 0) {
++ pr_debug("[%s]: attempt mapping kernel resource - guid %x, hdl %x\n",
++ __func__, ioparam->handle, lock.res_handle);
++
++ ioparam->addr = 0;
++
++ map = kzalloc(sizeof(*map), GFP_KERNEL);
++ if (map == NULL) {
++ pr_err("[%s]: failed allocating tracker\n",
++ __func__);
++ ret = -ENOMEM;
++ goto error;
++ } else {
++ phys_addr = (uint32_t)resource->res_base_mem &
++ 0x3FFFFFFF;
++ phys_addr += mm_vc_mem_phys_addr;
++ if (resource->res_cached
++ == VMCS_SM_CACHE_HOST) {
++ ioparam->addr = (long unsigned int)
++ /* TODO - make cached work */
++ ioremap_nocache(phys_addr,
++ resource->res_size);
++
++ pr_debug("[%s]: mapping kernel - guid %x, hdl %x - cached mapping %u\n",
++ __func__, ioparam->handle,
++ lock.res_handle, ioparam->addr);
++ } else {
++ ioparam->addr = (long unsigned int)
++ ioremap_nocache(phys_addr,
++ resource->res_size);
++
++ pr_debug("[%s]: mapping kernel- guid %x, hdl %x - non cached mapping %u\n",
++ __func__, ioparam->handle,
++ lock.res_handle, ioparam->addr);
++ }
++
++ map->res_pid = 0;
++ map->res_vc_hdl = resource->res_handle;
++ map->res_usr_hdl = resource->res_guid;
++ map->res_addr = ioparam->addr;
++ map->resource = resource;
++ map->vma = NULL;
++
++ vmcs_sm_add_map(sm_state, resource, map);
++ }
++ } else
++ ioparam->addr = 0;
++ }
++
++error:
++ if (resource)
++ vmcs_sm_release_resource(resource, 0);
++
++ return ret;
++}
++
++/* Unlock a previously allocated shared memory handle and block.
++*/
++static int vc_sm_ioctl_unlock(struct SM_PRIV_DATA_T *private,
++ struct vmcs_sm_ioctl_lock_unlock *ioparam,
++ int flush, int wait_reply, int no_vc_unlock)
++{
++ int status;
++ VC_SM_LOCK_UNLOCK_T unlock;
++ struct sm_mmap *map, *map_tmp;
++ struct SM_RESOURCE_T *resource;
++ int ret = 0;
++
++ map = NULL;
++
++ /* Locate resource from GUID.
++ */
++ resource = vmcs_sm_acquire_resource(private, ioparam->handle);
++ if (resource == NULL) {
++ ret = -EINVAL;
++ goto error;
++ }
++
++ /* Check permissions.
++ */
++ if (resource->pid && (resource->pid != current->tgid)) {
++ pr_err("[%s]: current tgid %u != %u owner\n",
++ __func__, current->tgid, resource->pid);
++ ret = -EPERM;
++ goto error;
++ }
++
++ unlock.res_handle = resource->res_handle;
++ unlock.res_mem = resource->res_base_mem;
++
++ pr_debug("[%s]: attempt to unlock data - guid %x, hdl %x, base address %p\n",
++ __func__, ioparam->handle, unlock.res_handle, unlock.res_mem);
++
++ /* User space allocated resources.
++ */
++ if (resource->pid) {
++ /* Flush if requested */
++ if (resource->res_cached && flush) {
++ dma_addr_t phys_addr = 0;
++ resource->res_stats[FLUSH]++;
++
++ phys_addr =
++ (dma_addr_t)((uint32_t)resource->res_base_mem &
++ 0x3FFFFFFF);
++ phys_addr += (dma_addr_t)mm_vc_mem_phys_addr;
++
++ /* L1 cache flush */
++ down_read(&current->mm->mmap_sem);
++ list_for_each_entry(map, &resource->map_list,
++ resource_map_list) {
++ if (map->vma) {
++ unsigned long start;
++ unsigned long end;
++ start = map->vma->vm_start;
++ end = map->vma->vm_end;
++
++ vcsm_vma_cache_clean_page_range(
++ start, end);
++ }
++ }
++ up_read(&current->mm->mmap_sem);
++
++ /* L2 cache flush */
++ outer_clean_range(phys_addr,
++ phys_addr +
++ (size_t) resource->res_size);
++ }
++
++ /* We need to zap all the vmas associated with this resource */
++ if (resource->lock_count == 1) {
++ down_read(&current->mm->mmap_sem);
++ list_for_each_entry(map, &resource->map_list,
++ resource_map_list) {
++ if (map->vma) {
++ zap_vma_ptes(map->vma,
++ map->vma->vm_start,
++ map->vma->vm_end -
++ map->vma->vm_start);
++ }
++ }
++ up_read(&current->mm->mmap_sem);
++ }
++ }
++ /* Kernel allocated resources. */
++ else {
++ /* Global + Taken in this context */
++ if (resource->ref_count == 2) {
++ if (!list_empty(&resource->map_list)) {
++ list_for_each_entry_safe(map, map_tmp,
++ &resource->map_list,
++ resource_map_list) {
++ if (map->res_addr) {
++ if (flush &&
++ (resource->res_cached ==
++ VMCS_SM_CACHE_HOST)) {
++ long unsigned int
++ phys_addr;
++ phys_addr = (uint32_t)
++ resource->res_base_mem & 0x3FFFFFFF;
++ phys_addr +=
++ mm_vc_mem_phys_addr;
++
++ /* L1 cache flush */
++ dmac_flush_range((const
++ void
++ *)
++ map->res_addr, (const void *)
++ (map->res_addr + resource->res_size));
++
++ /* L2 cache flush */
++ outer_clean_range
++ (phys_addr,
++ phys_addr +
++ (size_t)
++ resource->res_size);
++ }
++
++ iounmap((void *)map->res_addr);
++ map->res_addr = 0;
++
++ vmcs_sm_remove_map(sm_state,
++ map->resource,
++ map);
++ break;
++ }
++ }
++ }
++ }
++ }
++
++ if (resource->lock_count) {
++ /* Bypass the videocore unlock.
++ */
++ if (no_vc_unlock)
++ status = 0;
++ /* Unlock the videocore allocated resource.
++ */
++ else {
++ status =
++ vc_vchi_sm_unlock(sm_state->sm_handle, &unlock,
++ &private->int_trans_id,
++ wait_reply);
++ if (status == -EINTR) {
++ pr_debug("[%s]: requesting unlock memory action restart (trans_id: %u)\n",
++ __func__, private->int_trans_id);
++
++ ret = -ERESTARTSYS;
++ resource->res_stats[UNLOCK]--;
++ private->restart_sys = -EINTR;
++ private->int_action = VC_SM_MSG_TYPE_UNLOCK;
++ goto error;
++ } else if (status != 0) {
++ pr_err("[%s]: failed to unlock vc mem (status: %u, trans_id: %u)\n",
++ __func__, status, private->int_trans_id);
++
++ ret = -EPERM;
++ resource->res_stats[UNLOCK_FAIL]++;
++ goto error;
++ }
++ }
++
++ resource->res_stats[UNLOCK]++;
++ resource->lock_count--;
++ }
++
++ pr_debug("[%s]: success to unlock data - hdl %x, base address %p, ref-cnt %d\n",
++ __func__, unlock.res_handle, unlock.res_mem,
++ resource->lock_count);
++
++error:
++ if (resource)
++ vmcs_sm_release_resource(resource, 0);
++
++ return ret;
++}
++
++/* Handle control from host. */
++static long vc_sm_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
++{
++ int ret = 0;
++ unsigned int cmdnr = _IOC_NR(cmd);
++ struct SM_PRIV_DATA_T *file_data =
++ (struct SM_PRIV_DATA_T *)file->private_data;
++ struct SM_RESOURCE_T *resource = NULL;
++
++ /* Validate we can work with this device. */
++ if ((sm_state == NULL) || (file_data == NULL)) {
++ pr_err("[%s]: invalid device\n", __func__);
++ ret = -EPERM;
++ goto out;
++ }
++
++ pr_debug("[%s]: cmd %x tgid %u, owner %u\n", __func__, cmdnr,
++ current->tgid, file_data->pid);
++
++ /* Action is a re-post of a previously interrupted action? */
++ if (file_data->restart_sys == -EINTR) {
++ VC_SM_ACTION_CLEAN_T action_clean;
++
++ pr_debug("[%s]: clean up of action %u (trans_id: %u) following EINTR\n",
++ __func__, file_data->int_action,
++ file_data->int_trans_id);
++
++ action_clean.res_action = file_data->int_action;
++ action_clean.action_trans_id = file_data->int_trans_id;
++
++ vc_vchi_sm_clean_up(sm_state->sm_handle, &action_clean);
++
++ file_data->restart_sys = 0;
++ }
++
++ /* Now process the command.
++ */
++ switch (cmdnr) {
++ /* New memory allocation.
++ */
++ case VMCS_SM_CMD_ALLOC:
++ {
++ struct vmcs_sm_ioctl_alloc ioparam;
++
++ /* Get the parameter data.
++ */
++ if (copy_from_user
++ (&ioparam, (void *)arg, sizeof(ioparam)) != 0) {
++ pr_err("[%s]: failed to copy-from-user for cmd %x\n",
++ __func__, cmdnr);
++ ret = -EFAULT;
++ goto out;
++ }
++
++ ret = vc_sm_ioctl_alloc(file_data, &ioparam);
++ if (!ret &&
++ (copy_to_user((void *)arg,
++ &ioparam, sizeof(ioparam)) != 0)) {
++ struct vmcs_sm_ioctl_free freeparam = {
++ ioparam.handle
++ };
++ pr_err("[%s]: failed to copy-to-user for cmd %x\n",
++ __func__, cmdnr);
++ vc_sm_ioctl_free(file_data, &freeparam);
++ ret = -EFAULT;
++ }
++
++ /* Done.
++ */
++ goto out;
++ }
++ break;
++
++ /* Share existing memory allocation.
++ */
++ case VMCS_SM_CMD_ALLOC_SHARE:
++ {
++ struct vmcs_sm_ioctl_alloc_share ioparam;
++
++ /* Get the parameter data.
++ */
++ if (copy_from_user
++ (&ioparam, (void *)arg, sizeof(ioparam)) != 0) {
++ pr_err("[%s]: failed to copy-from-user for cmd %x\n",
++ __func__, cmdnr);
++ ret = -EFAULT;
++ goto out;
++ }
++
++ ret = vc_sm_ioctl_alloc_share(file_data, &ioparam);
++
++ /* Copy result back to user.
++ */
++ if (!ret
++ && copy_to_user((void *)arg, &ioparam,
++ sizeof(ioparam)) != 0) {
++ struct vmcs_sm_ioctl_free freeparam = {
++ ioparam.handle
++ };
++ pr_err("[%s]: failed to copy-to-user for cmd %x\n",
++ __func__, cmdnr);
++ vc_sm_ioctl_free(file_data, &freeparam);
++ ret = -EFAULT;
++ }
++
++ /* Done.
++ */
++ goto out;
++ }
++ break;
++
++ /* Lock (attempt to) *and* register a cache behavior change.
++ */
++ case VMCS_SM_CMD_LOCK_CACHE:
++ {
++ struct vmcs_sm_ioctl_lock_cache ioparam;
++ struct vmcs_sm_ioctl_lock_unlock lock;
++
++ /* Get parameter data.
++ */
++ if (copy_from_user
++ (&ioparam, (void *)arg, sizeof(ioparam)) != 0) {
++ pr_err("[%s]: failed to copy-from-user for cmd %x\n",
++ __func__, cmdnr);
++ ret = -EFAULT;
++ goto out;
++ }
++
++ lock.handle = ioparam.handle;
++ ret =
++ vc_sm_ioctl_lock(file_data, &lock, 1,
++ ioparam.cached, 0);
++
++ /* Done.
++ */
++ goto out;
++ }
++ break;
++
++ /* Lock (attempt to) existing memory allocation.
++ */
++ case VMCS_SM_CMD_LOCK:
++ {
++ struct vmcs_sm_ioctl_lock_unlock ioparam;
++
++ /* Get parameter data.
++ */
++ if (copy_from_user
++ (&ioparam, (void *)arg, sizeof(ioparam)) != 0) {
++ pr_err("[%s]: failed to copy-from-user for cmd %x\n",
++ __func__, cmdnr);
++ ret = -EFAULT;
++ goto out;
++ }
++
++ ret = vc_sm_ioctl_lock(file_data, &ioparam, 0, 0, 0);
++
++ /* Copy result back to user.
++ */
++ if (copy_to_user((void *)arg, &ioparam, sizeof(ioparam))
++ != 0) {
++ pr_err("[%s]: failed to copy-to-user for cmd %x\n",
++ __func__, cmdnr);
++ ret = -EFAULT;
++ }
++
++ /* Done.
++ */
++ goto out;
++ }
++ break;
++
++ /* Unlock (attempt to) existing memory allocation.
++ */
++ case VMCS_SM_CMD_UNLOCK:
++ {
++ struct vmcs_sm_ioctl_lock_unlock ioparam;
++
++ /* Get parameter data.
++ */
++ if (copy_from_user
++ (&ioparam, (void *)arg, sizeof(ioparam)) != 0) {
++ pr_err("[%s]: failed to copy-from-user for cmd %x\n",
++ __func__, cmdnr);
++ ret = -EFAULT;
++ goto out;
++ }
++
++ ret = vc_sm_ioctl_unlock(file_data, &ioparam, 0, 1, 0);
++
++ /* Done.
++ */
++ goto out;
++ }
++ break;
++
++ /* Resize (attempt to) existing memory allocation.
++ */
++ case VMCS_SM_CMD_RESIZE:
++ {
++ struct vmcs_sm_ioctl_resize ioparam;
++
++ /* Get parameter data.
++ */
++ if (copy_from_user
++ (&ioparam, (void *)arg, sizeof(ioparam)) != 0) {
++ pr_err("[%s]: failed to copy-from-user for cmd %x\n",
++ __func__, cmdnr);
++ ret = -EFAULT;
++ goto out;
++ }
++
++ ret = vc_sm_ioctl_resize(file_data, &ioparam);
++
++ /* Copy result back to user.
++ */
++ if (copy_to_user((void *)arg, &ioparam, sizeof(ioparam))
++ != 0) {
++ pr_err("[%s]: failed to copy-to-user for cmd %x\n",
++ __func__, cmdnr);
++ ret = -EFAULT;
++ }
++
++ /* Done.
++ */
++ goto out;
++ }
++ break;
++
++ /* Terminate existing memory allocation.
++ */
++ case VMCS_SM_CMD_FREE:
++ {
++ struct vmcs_sm_ioctl_free ioparam;
++
++ /* Get parameter data.
++ */
++ if (copy_from_user
++ (&ioparam, (void *)arg, sizeof(ioparam)) != 0) {
++ pr_err("[%s]: failed to copy-from-user for cmd %x\n",
++ __func__, cmdnr);
++ ret = -EFAULT;
++ goto out;
++ }
++
++ ret = vc_sm_ioctl_free(file_data, &ioparam);
++
++ /* Done.
++ */
++ goto out;
++ }
++ break;
++
++ /* Walk allocation on videocore, information shows up in the
++ ** videocore log.
++ */
++ case VMCS_SM_CMD_VC_WALK_ALLOC:
++ {
++ pr_debug("[%s]: invoking walk alloc\n", __func__);
++
++ if (vc_vchi_sm_walk_alloc(sm_state->sm_handle) != 0)
++ pr_err("[%s]: failed to walk-alloc on videocore\n",
++ __func__);
++
++ /* Done.
++ */
++ goto out;
++ }
++ break;
++/* Walk mapping table on host, information shows up in the
++ ** kernel log.
++ */
++ case VMCS_SM_CMD_HOST_WALK_MAP:
++ {
++ /* Use pid of -1 to tell to walk the whole map. */
++ vmcs_sm_host_walk_map_per_pid(-1);
++
++ /* Done. */
++ goto out;
++ }
++ break;
++
++ /* Walk mapping table per process on host. */
++ case VMCS_SM_CMD_HOST_WALK_PID_ALLOC:
++ {
++ struct vmcs_sm_ioctl_walk ioparam;
++
++ /* Get parameter data. */
++ if (copy_from_user(&ioparam,
++ (void *)arg, sizeof(ioparam)) != 0) {
++ pr_err("[%s]: failed to copy-from-user for cmd %x\n",
++ __func__, cmdnr);
++ ret = -EFAULT;
++ goto out;
++ }
++
++ vmcs_sm_host_walk_alloc(file_data);
++
++ /* Done. */
++ goto out;
++ }
++ break;
++
++ /* Walk allocation per process on host. */
++ case VMCS_SM_CMD_HOST_WALK_PID_MAP:
++ {
++ struct vmcs_sm_ioctl_walk ioparam;
++
++ /* Get parameter data. */
++ if (copy_from_user(&ioparam,
++ (void *)arg, sizeof(ioparam)) != 0) {
++ pr_err("[%s]: failed to copy-from-user for cmd %x\n",
++ __func__, cmdnr);
++ ret = -EFAULT;
++ goto out;
++ }
++
++ vmcs_sm_host_walk_map_per_pid(ioparam.pid);
++
++ /* Done. */
++ goto out;
++ }
++ break;
++
++ /* Gets the size of the memory associated with a user handle. */
++ case VMCS_SM_CMD_SIZE_USR_HANDLE:
++ {
++ struct vmcs_sm_ioctl_size ioparam;
++
++ /* Get parameter data. */
++ if (copy_from_user(&ioparam,
++ (void *)arg, sizeof(ioparam)) != 0) {
++ pr_err("[%s]: failed to copy-from-user for cmd %x\n",
++ __func__, cmdnr);
++ ret = -EFAULT;
++ goto out;
++ }
++
++ /* Locate resource from GUID. */
++ resource =
++ vmcs_sm_acquire_resource(file_data, ioparam.handle);
++ if (resource != NULL) {
++ ioparam.size = resource->res_size;
++ vmcs_sm_release_resource(resource, 0);
++ } else {
++ ioparam.size = 0;
++ }
++
++ if (copy_to_user((void *)arg,
++ &ioparam, sizeof(ioparam)) != 0) {
++ pr_err("[%s]: failed to copy-to-user for cmd %x\n",
++ __func__, cmdnr);
++ ret = -EFAULT;
++ }
++
++ /* Done. */
++ goto out;
++ }
++ break;
++
++ /* Verify we are dealing with a valid resource. */
++ case VMCS_SM_CMD_CHK_USR_HANDLE:
++ {
++ struct vmcs_sm_ioctl_chk ioparam;
++
++ /* Get parameter data.
++ */
++ if (copy_from_user(&ioparam,
++ (void *)arg, sizeof(ioparam)) != 0) {
++ pr_err("[%s]: failed to copy-from-user for cmd %x\n",
++ __func__, cmdnr);
++
++ ret = -EFAULT;
++ goto out;
++ }
++
++ /* Locate resource from GUID. */
++ resource =
++ vmcs_sm_acquire_resource(file_data, ioparam.handle);
++ if (resource == NULL)
++ ret = -EINVAL;
++ /* If the resource is cacheable, return additional
++ * information that may be needed to flush the cache.
++ */
++ else if ((resource->res_cached == VMCS_SM_CACHE_HOST) ||
++ (resource->res_cached == VMCS_SM_CACHE_BOTH)) {
++ ioparam.addr =
++ vmcs_sm_usr_address_from_pid_and_usr_handle
++ (current->tgid, ioparam.handle);
++ ioparam.size = resource->res_size;
++ ioparam.cache = resource->res_cached;
++ } else {
++ ioparam.addr = 0;
++ ioparam.size = 0;
++ ioparam.cache = resource->res_cached;
++ }
++
++ if (resource)
++ vmcs_sm_release_resource(resource, 0);
++
++ if (copy_to_user((void *)arg,
++ &ioparam, sizeof(ioparam)) != 0) {
++ pr_err("[%s]: failed to copy-to-user for cmd %x\n",
++ __func__, cmdnr);
++ ret = -EFAULT;
++ }
++
++ /* Done.
++ */
++ goto out;
++ }
++ break;
++
++ /*
++ * Maps a user handle given the process and the virtual address.
++ */
++ case VMCS_SM_CMD_MAPPED_USR_HANDLE:
++ {
++ struct vmcs_sm_ioctl_map ioparam;
++
++ /* Get parameter data. */
++ if (copy_from_user(&ioparam,
++ (void *)arg, sizeof(ioparam)) != 0) {
++ pr_err("[%s]: failed to copy-from-user for cmd %x\n",
++ __func__, cmdnr);
++
++ ret = -EFAULT;
++ goto out;
++ }
++
++ ioparam.handle =
++ vmcs_sm_usr_handle_from_pid_and_address(
++ ioparam.pid, ioparam.addr);
++
++ resource =
++ vmcs_sm_acquire_resource(file_data, ioparam.handle);
++ if ((resource != NULL)
++ && ((resource->res_cached == VMCS_SM_CACHE_HOST)
++ || (resource->res_cached ==
++ VMCS_SM_CACHE_BOTH))) {
++ ioparam.size = resource->res_size;
++ } else {
++ ioparam.size = 0;
++ }
++
++ if (resource)
++ vmcs_sm_release_resource(resource, 0);
++
++ if (copy_to_user((void *)arg,
++ &ioparam, sizeof(ioparam)) != 0) {
++ pr_err("[%s]: failed to copy-to-user for cmd %x\n",
++ __func__, cmdnr);
++ ret = -EFAULT;
++ }
++
++ /* Done. */
++ goto out;
++ }
++ break;
++
++ /*
++ * Maps a videocore handle given process and virtual address.
++ */
++ case VMCS_SM_CMD_MAPPED_VC_HDL_FROM_ADDR:
++ {
++ struct vmcs_sm_ioctl_map ioparam;
++
++ /* Get parameter data. */
++ if (copy_from_user(&ioparam,
++ (void *)arg, sizeof(ioparam)) != 0) {
++ pr_err("[%s]: failed to copy-from-user for cmd %x\n",
++ __func__, cmdnr);
++ ret = -EFAULT;
++ goto out;
++ }
++
++ ioparam.handle = vmcs_sm_vc_handle_from_pid_and_address(
++ ioparam.pid, ioparam.addr);
++
++ if (copy_to_user((void *)arg,
++ &ioparam, sizeof(ioparam)) != 0) {
++ pr_err("[%s]: failed to copy-to-user for cmd %x\n",
++ __func__, cmdnr);
++
++ ret = -EFAULT;
++ }
++
++ /* Done.
++ */
++ goto out;
++ }
++ break;
++
++ /* Maps a videocore handle given process and user handle. */
++ case VMCS_SM_CMD_MAPPED_VC_HDL_FROM_HDL:
++ {
++ struct vmcs_sm_ioctl_map ioparam;
++
++ /* Get parameter data. */
++ if (copy_from_user(&ioparam,
++ (void *)arg, sizeof(ioparam)) != 0) {
++ pr_err("[%s]: failed to copy-from-user for cmd %x\n",
++ __func__, cmdnr);
++ ret = -EFAULT;
++ goto out;
++ }
++
++ /* Locate resource from GUID. */
++ resource =
++ vmcs_sm_acquire_resource(file_data, ioparam.handle);
++ if (resource != NULL) {
++ ioparam.handle = resource->res_handle;
++ vmcs_sm_release_resource(resource, 0);
++ } else {
++ ioparam.handle = 0;
++ }
++
++ if (copy_to_user((void *)arg,
++ &ioparam, sizeof(ioparam)) != 0) {
++ pr_err("[%s]: failed to copy-to-user for cmd %x\n",
++ __func__, cmdnr);
++
++ ret = -EFAULT;
++ }
++
++ /* Done. */
++ goto out;
++ }
++ break;
++
++ /*
++ * Maps a videocore address given process and videocore handle.
++ */
++ case VMCS_SM_CMD_MAPPED_VC_ADDR_FROM_HDL:
++ {
++ struct vmcs_sm_ioctl_map ioparam;
++
++ /* Get parameter data. */
++ if (copy_from_user(&ioparam,
++ (void *)arg, sizeof(ioparam)) != 0) {
++ pr_err("[%s]: failed to copy-from-user for cmd %x\n",
++ __func__, cmdnr);
++
++ ret = -EFAULT;
++ goto out;
++ }
++
++ /* Locate resource from GUID. */
++ resource =
++ vmcs_sm_acquire_resource(file_data, ioparam.handle);
++ if (resource != NULL) {
++ ioparam.addr =
++ (unsigned int)resource->res_base_mem;
++ vmcs_sm_release_resource(resource, 0);
++ } else {
++ ioparam.addr = 0;
++ }
++
++ if (copy_to_user((void *)arg,
++ &ioparam, sizeof(ioparam)) != 0) {
++ pr_err("[%s]: failed to copy-to-user for cmd %x\n",
++ __func__, cmdnr);
++ ret = -EFAULT;
++ }
++
++ /* Done. */
++ goto out;
++ }
++ break;
++
++ /* Maps a user address given process and vc handle.
++ */
++ case VMCS_SM_CMD_MAPPED_USR_ADDRESS:
++ {
++ struct vmcs_sm_ioctl_map ioparam;
++
++ /* Get parameter data. */
++ if (copy_from_user(&ioparam,
++ (void *)arg, sizeof(ioparam)) != 0) {
++ pr_err("[%s]: failed to copy-from-user for cmd %x\n",
++ __func__, cmdnr);
++ ret = -EFAULT;
++ goto out;
++ }
++
++ /*
++ * Return the address information from the mapping,
++ * 0 (ie NULL) if it cannot locate the actual mapping.
++ */
++ ioparam.addr =
++ vmcs_sm_usr_address_from_pid_and_usr_handle
++ (ioparam.pid, ioparam.handle);
++
++ if (copy_to_user((void *)arg,
++ &ioparam, sizeof(ioparam)) != 0) {
++ pr_err("[%s]: failed to copy-to-user for cmd %x\n",
++ __func__, cmdnr);
++ ret = -EFAULT;
++ }
++
++ /* Done. */
++ goto out;
++ }
++ break;
++
++ /* Flush the cache for a given mapping. */
++ case VMCS_SM_CMD_FLUSH:
++ {
++ struct vmcs_sm_ioctl_cache ioparam;
++
++ /* Get parameter data. */
++ if (copy_from_user(&ioparam,
++ (void *)arg, sizeof(ioparam)) != 0) {
++ pr_err("[%s]: failed to copy-from-user for cmd %x\n",
++ __func__, cmdnr);
++ ret = -EFAULT;
++ goto out;
++ }
++
++ /* Locate resource from GUID. */
++ resource =
++ vmcs_sm_acquire_resource(file_data, ioparam.handle);
++
++ if ((resource != NULL) && resource->res_cached) {
++ dma_addr_t phys_addr = 0;
++
++ resource->res_stats[FLUSH]++;
++
++ phys_addr =
++ (dma_addr_t)((uint32_t)
++ resource->res_base_mem &
++ 0x3FFFFFFF);
++ phys_addr += (dma_addr_t)mm_vc_mem_phys_addr;
++
++ /* L1 cache flush */
++ down_read(&current->mm->mmap_sem);
++ vcsm_vma_cache_clean_page_range((unsigned long)
++ ioparam.addr,
++ (unsigned long)
++ ioparam.addr +
++ ioparam.size);
++ up_read(&current->mm->mmap_sem);
++
++ /* L2 cache flush */
++ outer_clean_range(phys_addr,
++ phys_addr +
++ (size_t) ioparam.size);
++ } else if (resource == NULL) {
++ ret = -EINVAL;
++ goto out;
++ }
++
++ if (resource)
++ vmcs_sm_release_resource(resource, 0);
++
++ /* Done. */
++ goto out;
++ }
++ break;
++
++ /* Invalidate the cache for a given mapping. */
++ case VMCS_SM_CMD_INVALID:
++ {
++ struct vmcs_sm_ioctl_cache ioparam;
++
++ /* Get parameter data. */
++ if (copy_from_user(&ioparam,
++ (void *)arg, sizeof(ioparam)) != 0) {
++ pr_err("[%s]: failed to copy-from-user for cmd %x\n",
++ __func__, cmdnr);
++ ret = -EFAULT;
++ goto out;
++ }
++
++ /* Locate resource from GUID.
++ */
++ resource =
++ vmcs_sm_acquire_resource(file_data, ioparam.handle);
++
++ if ((resource != NULL) && resource->res_cached) {
++ dma_addr_t phys_addr = 0;
++
++ resource->res_stats[INVALID]++;
++
++ phys_addr =
++ (dma_addr_t)((uint32_t)
++ resource->res_base_mem &
++ 0x3FFFFFFF);
++ phys_addr += (dma_addr_t)mm_vc_mem_phys_addr;
++
++ /* L2 cache invalidate */
++ outer_inv_range(phys_addr,
++ phys_addr +
++ (size_t) ioparam.size);
++
++ /* L1 cache invalidate */
++ down_read(&current->mm->mmap_sem);
++ vcsm_vma_cache_clean_page_range((unsigned long)
++ ioparam.addr,
++ (unsigned long)
++ ioparam.addr +
++ ioparam.size);
++ up_read(&current->mm->mmap_sem);
++ } else if (resource == NULL) {
++ ret = -EINVAL;
++ goto out;
++ }
++
++ if (resource)
++ vmcs_sm_release_resource(resource, 0);
++
++ /* Done.
++ */
++ goto out;
++ }
++ break;
++
++ /* Flush/Invalidate the cache for a given mapping. */
++ case VMCS_SM_CMD_CLEAN_INVALID:
++ {
++ int i;
++ struct vmcs_sm_ioctl_clean_invalid ioparam;
++
++ /* Get parameter data. */
++ if (copy_from_user(&ioparam,
++ (void *)arg, sizeof(ioparam)) != 0) {
++ pr_err("[%s]: failed to copy-from-user for cmd %x\n",
++ __func__, cmdnr);
++ ret = -EFAULT;
++ goto out;
++ }
++ for (i=0; i<sizeof ioparam.s/sizeof *ioparam.s; i++) {
++ switch (ioparam.s[i].cmd) {
++ default: case 0: break; /* NOOP */
++ case 1: /* L1/L2 invalidate virtual range */
++ case 2: /* L1/L2 clean physical range */
++ case 3: /* L1/L2 clean+invalidate all */
++ {
++ /* Locate resource from GUID.
++ */
++ resource =
++ vmcs_sm_acquire_resource(file_data, ioparam.s[i].handle);
++
++ if ((resource != NULL) && resource->res_cached) {
++ unsigned long base = ioparam.s[i].addr & ~(PAGE_SIZE-1);
++ unsigned long end = (ioparam.s[i].addr + ioparam.s[i].size + PAGE_SIZE-1) & ~(PAGE_SIZE-1);
++ resource->res_stats[ioparam.s[i].cmd == 1 ? INVALID:FLUSH]++;
++
++ /* L1/L2 cache flush */
++ down_read(&current->mm->mmap_sem);
++ vcsm_vma_cache_clean_page_range(base, end);
++ up_read(&current->mm->mmap_sem);
++ } else if (resource == NULL) {
++ ret = -EINVAL;
++ goto out;
++ }
++
++ if (resource)
++ vmcs_sm_release_resource(resource, 0);
++ }
++ break;
++ }
++ }
++ }
++ break;
++
++ default:
++ {
++ ret = -EINVAL;
++ goto out;
++ }
++ break;
++ }
++
++out:
++ return ret;
++}
++
++/* Device operations that we managed in this driver.
++*/
++static const struct file_operations vmcs_sm_ops = {
++ .owner = THIS_MODULE,
++ .unlocked_ioctl = vc_sm_ioctl,
++ .open = vc_sm_open,
++ .release = vc_sm_release,
++ .mmap = vc_sm_mmap,
++};
++
++/* Creation of device.
++*/
++static int vc_sm_create_sharedmemory(void)
++{
++ int ret;
++
++ if (sm_state == NULL) {
++ ret = -ENOMEM;
++ goto out;
++ }
++
++ /* Create a device class for creating dev nodes.
++ */
++ sm_state->sm_class = class_create(THIS_MODULE, "vc-sm");
++ if (IS_ERR(sm_state->sm_class)) {
++ pr_err("[%s]: unable to create device class\n", __func__);
++ ret = PTR_ERR(sm_state->sm_class);
++ goto out;
++ }
++
++ /* Create a character driver.
++ */
++ ret = alloc_chrdev_region(&sm_state->sm_devid,
++ DEVICE_MINOR, 1, DEVICE_NAME);
++ if (ret != 0) {
++ pr_err("[%s]: unable to allocate device number\n", __func__);
++ goto out_dev_class_destroy;
++ }
++
++ cdev_init(&sm_state->sm_cdev, &vmcs_sm_ops);
++ ret = cdev_add(&sm_state->sm_cdev, sm_state->sm_devid, 1);
++ if (ret != 0) {
++ pr_err("[%s]: unable to register device\n", __func__);
++ goto out_chrdev_unreg;
++ }
++
++ /* Create a device node.
++ */
++ sm_state->sm_dev = device_create(sm_state->sm_class,
++ NULL,
++ MKDEV(MAJOR(sm_state->sm_devid),
++ DEVICE_MINOR), NULL,
++ DEVICE_NAME);
++ if (IS_ERR(sm_state->sm_dev)) {
++ pr_err("[%s]: unable to create device node\n", __func__);
++ ret = PTR_ERR(sm_state->sm_dev);
++ goto out_chrdev_del;
++ }
++
++ goto out;
++
++out_chrdev_del:
++ cdev_del(&sm_state->sm_cdev);
++out_chrdev_unreg:
++ unregister_chrdev_region(sm_state->sm_devid, 1);
++out_dev_class_destroy:
++ class_destroy(sm_state->sm_class);
++ sm_state->sm_class = NULL;
++out:
++ return ret;
++}
++
++/* Termination of the device.
++*/
++static int vc_sm_remove_sharedmemory(void)
++{
++ int ret;
++
++ if (sm_state == NULL) {
++ /* Nothing to do.
++ */
++ ret = 0;
++ goto out;
++ }
++
++ /* Remove the sharedmemory character driver.
++ */
++ cdev_del(&sm_state->sm_cdev);
++
++ /* Unregister region.
++ */
++ unregister_chrdev_region(sm_state->sm_devid, 1);
++
++ ret = 0;
++ goto out;
++
++out:
++ return ret;
++}
++
++/* Videocore connected. */
++static void vc_sm_connected_init(void)
++{
++ int ret;
++ VCHI_INSTANCE_T vchi_instance;
++ VCHI_CONNECTION_T *vchi_connection = NULL;
++
++ pr_info("[%s]: start\n", __func__);
++
++ /* Allocate memory for the state structure.
++ */
++ sm_state = kzalloc(sizeof(struct SM_STATE_T), GFP_KERNEL);
++ if (sm_state == NULL) {
++ pr_err("[%s]: failed to allocate memory\n", __func__);
++ ret = -ENOMEM;
++ goto out;
++ }
++
++ mutex_init(&sm_state->lock);
++ mutex_init(&sm_state->map_lock);
++
++ /* Initialize and create a VCHI connection for the shared memory service
++ ** running on videocore.
++ */
++ ret = vchi_initialise(&vchi_instance);
++ if (ret != 0) {
++ pr_err("[%s]: failed to initialise VCHI instance (ret=%d)\n",
++ __func__, ret);
++
++ ret = -EIO;
++ goto err_free_mem;
++ }
++
++ ret = vchi_connect(NULL, 0, vchi_instance);
++ if (ret != 0) {
++ pr_err("[%s]: failed to connect VCHI instance (ret=%d)\n",
++ __func__, ret);
++
++ ret = -EIO;
++ goto err_free_mem;
++ }
++
++ /* Initialize an instance of the shared memory service. */
++ sm_state->sm_handle =
++ vc_vchi_sm_init(vchi_instance, &vchi_connection, 1);
++ if (sm_state->sm_handle == NULL) {
++ pr_err("[%s]: failed to initialize shared memory service\n",
++ __func__);
++
++ ret = -EPERM;
++ goto err_free_mem;
++ }
++
++ /* Create a debug fs directory entry (root). */
++ sm_state->dir_root = debugfs_create_dir(VC_SM_DIR_ROOT_NAME, NULL);
++ if (!sm_state->dir_root) {
++ pr_err("[%s]: failed to create \'%s\' directory entry\n",
++ __func__, VC_SM_DIR_ROOT_NAME);
++
++ ret = -EPERM;
++ goto err_stop_sm_service;
++ }
++
++ sm_state->dir_state.show = &vc_sm_global_state_show;
++ sm_state->dir_state.dir_entry = debugfs_create_file(VC_SM_STATE,
++ S_IRUGO, sm_state->dir_root, &sm_state->dir_state,
++ &vc_sm_debug_fs_fops);
++
++ sm_state->dir_stats.show = &vc_sm_global_statistics_show;
++ sm_state->dir_stats.dir_entry = debugfs_create_file(VC_SM_STATS,
++ S_IRUGO, sm_state->dir_root, &sm_state->dir_stats,
++ &vc_sm_debug_fs_fops);
++
++ /* Create the proc entry children. */
++ sm_state->dir_alloc = debugfs_create_dir(VC_SM_DIR_ALLOC_NAME,
++ sm_state->dir_root);
++
++ /* Create a shared memory device. */
++ ret = vc_sm_create_sharedmemory();
++ if (ret != 0) {
++ pr_err("[%s]: failed to create shared memory device\n",
++ __func__);
++ goto err_remove_debugfs;
++ }
++
++ INIT_LIST_HEAD(&sm_state->map_list);
++ INIT_LIST_HEAD(&sm_state->resource_list);
++
++ sm_state->data_knl = vc_sm_create_priv_data(0);
++ if (sm_state->data_knl == NULL) {
++ pr_err("[%s]: failed to create kernel private data tracker\n",
++ __func__);
++ goto err_remove_shared_memory;
++ }
++
++ /* Done!
++ */
++ sm_inited = 1;
++ goto out;
++
++err_remove_shared_memory:
++ vc_sm_remove_sharedmemory();
++err_remove_debugfs:
++ debugfs_remove_recursive(sm_state->dir_root);
++err_stop_sm_service:
++ vc_vchi_sm_stop(&sm_state->sm_handle);
++err_free_mem:
++ kfree(sm_state);
++out:
++ pr_info("[%s]: end - returning %d\n", __func__, ret);
++}
++
++/* Driver loading. */
++static int __init vc_sm_init(void)
++{
++ pr_info("vc-sm: Videocore shared memory driver\n");
++ vchiq_add_connected_callback(vc_sm_connected_init);
++ return 0;
++}
++
++/* Driver unloading. */
++static void __exit vc_sm_exit(void)
++{
++ pr_debug("[%s]: start\n", __func__);
++ if (sm_inited) {
++ /* Remove shared memory device.
++ */
++ vc_sm_remove_sharedmemory();
++
++ /* Remove all proc entries.
++ */
++ debugfs_remove_recursive(sm_state->dir_root);
++
++ /* Stop the videocore shared memory service.
++ */
++ vc_vchi_sm_stop(&sm_state->sm_handle);
++
++ /* Free the memory for the state structure.
++ */
++ mutex_destroy(&(sm_state->map_lock));
++ kfree(sm_state);
++ }
++
++ pr_debug("[%s]: end\n", __func__);
++}
++
++#if defined(__KERNEL__)
++/* Allocate a shared memory handle and block. */
++int vc_sm_alloc(VC_SM_ALLOC_T *alloc, int *handle)
++{
++ struct vmcs_sm_ioctl_alloc ioparam = { 0 };
++ int ret;
++ struct SM_RESOURCE_T *resource;
++
++ /* Validate we can work with this device.
++ */
++ if (sm_state == NULL || alloc == NULL || handle == NULL) {
++ pr_err("[%s]: invalid input\n", __func__);
++ return -EPERM;
++ }
++
++ ioparam.size = alloc->base_unit;
++ ioparam.num = alloc->num_unit;
++ ioparam.cached =
++ alloc->type == VC_SM_ALLOC_CACHED ? VMCS_SM_CACHE_VC : 0;
++
++ ret = vc_sm_ioctl_alloc(sm_state->data_knl, &ioparam);
++
++ if (ret == 0) {
++ resource =
++ vmcs_sm_acquire_resource(sm_state->data_knl,
++ ioparam.handle);
++ if (resource) {
++ resource->pid = 0;
++ vmcs_sm_release_resource(resource, 0);
++
++ /* Assign valid handle at this time.
++ */
++ *handle = ioparam.handle;
++ } else {
++ ret = -ENOMEM;
++ }
++ }
++
++ return ret;
++}
++EXPORT_SYMBOL_GPL(vc_sm_alloc);
++
++/* Get an internal resource handle mapped from the external one.
++*/
++int vc_sm_int_handle(int handle)
++{
++ struct SM_RESOURCE_T *resource;
++ int ret = 0;
++
++ /* Validate we can work with this device.
++ */
++ if (sm_state == NULL || handle == 0) {
++ pr_err("[%s]: invalid input\n", __func__);
++ return 0;
++ }
++
++ /* Locate resource from GUID.
++ */
++ resource = vmcs_sm_acquire_resource(sm_state->data_knl, handle);
++ if (resource) {
++ ret = resource->res_handle;
++ vmcs_sm_release_resource(resource, 0);
++ }
++
++ return ret;
++}
++EXPORT_SYMBOL_GPL(vc_sm_int_handle);
++
++/* Free a previously allocated shared memory handle and block.
++*/
++int vc_sm_free(int handle)
++{
++ struct vmcs_sm_ioctl_free ioparam = { handle };
++
++ /* Validate we can work with this device.
++ */
++ if (sm_state == NULL || handle == 0) {
++ pr_err("[%s]: invalid input\n", __func__);
++ return -EPERM;
++ }
++
++ return vc_sm_ioctl_free(sm_state->data_knl, &ioparam);
++}
++EXPORT_SYMBOL_GPL(vc_sm_free);
++
++/* Lock a memory handle for use by kernel.
++*/
++int vc_sm_lock(int handle, VC_SM_LOCK_CACHE_MODE_T mode,
++ long unsigned int *data)
++{
++ struct vmcs_sm_ioctl_lock_unlock ioparam;
++ int ret;
++
++ /* Validate we can work with this device.
++ */
++ if (sm_state == NULL || handle == 0 || data == NULL) {
++ pr_err("[%s]: invalid input\n", __func__);
++ return -EPERM;
++ }
++
++ *data = 0;
++
++ ioparam.handle = handle;
++ ret = vc_sm_ioctl_lock(sm_state->data_knl,
++ &ioparam,
++ 1,
++ ((mode ==
++ VC_SM_LOCK_CACHED) ? VMCS_SM_CACHE_HOST :
++ VMCS_SM_CACHE_NONE), 0);
++
++ *data = ioparam.addr;
++ return ret;
++}
++EXPORT_SYMBOL_GPL(vc_sm_lock);
++
++/* Unlock a memory handle in use by kernel.
++*/
++int vc_sm_unlock(int handle, int flush, int no_vc_unlock)
++{
++ struct vmcs_sm_ioctl_lock_unlock ioparam;
++
++ /* Validate we can work with this device.
++ */
++ if (sm_state == NULL || handle == 0) {
++ pr_err("[%s]: invalid input\n", __func__);
++ return -EPERM;
++ }
++
++ ioparam.handle = handle;
++ return vc_sm_ioctl_unlock(sm_state->data_knl,
++ &ioparam, flush, 0, no_vc_unlock);
++}
++EXPORT_SYMBOL_GPL(vc_sm_unlock);
++
++/* Map a shared memory region for use by kernel.
++*/
++int vc_sm_map(int handle, unsigned int sm_addr, VC_SM_LOCK_CACHE_MODE_T mode,
++ long unsigned int *data)
++{
++ struct vmcs_sm_ioctl_lock_unlock ioparam;
++ int ret;
++
++ /* Validate we can work with this device.
++ */
++ if (sm_state == NULL || handle == 0 || data == NULL || sm_addr == 0) {
++ pr_err("[%s]: invalid input\n", __func__);
++ return -EPERM;
++ }
++
++ *data = 0;
++
++ ioparam.handle = handle;
++ ret = vc_sm_ioctl_lock(sm_state->data_knl,
++ &ioparam,
++ 1,
++ ((mode ==
++ VC_SM_LOCK_CACHED) ? VMCS_SM_CACHE_HOST :
++ VMCS_SM_CACHE_NONE), sm_addr);
++
++ *data = ioparam.addr;
++ return ret;
++}
++EXPORT_SYMBOL_GPL(vc_sm_map);
++#endif
++
++late_initcall(vc_sm_init);
++module_exit(vc_sm_exit);
++
++MODULE_AUTHOR("Broadcom");
++MODULE_DESCRIPTION("VideoCore SharedMemory Driver");
++MODULE_LICENSE("GPL v2");
+diff -Nur linux-4.1.3/drivers/char/frandom.c linux-xbian-rpi/drivers/char/frandom.c
+--- linux-4.1.3/drivers/char/frandom.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/char/frandom.c 2015-07-27 23:13:03.986757999 +0200
+@@ -0,0 +1,415 @@
++/*
++** frandom.c
++** Fast pseudo-random generator
++**
++** (c) Copyright 2003-2011 Eli Billauer
++** http://www.billauer.co.il
++**
++** This program is free software; you can redistribute it and/or modify
++** it under the terms of the GNU General Public License as published by
++** the Free Software Foundation; either version 2 of the License, or
++** (at your option) any later version.
++**
++**
++*/
++
++#include <linux/version.h>
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/slab.h>
++#include <linux/fs.h>
++#include <linux/errno.h>
++#include <linux/types.h>
++#include <linux/random.h>
++
++#include <asm/uaccess.h>
++#include <linux/cdev.h>
++#include <linux/err.h>
++#include <linux/device.h>
++
++#define INTERNAL_SEED 0
++#define EXTERNAL_SEED 1
++
++#define FRANDOM_MAJOR 235
++#define FRANDOM_MINOR 11
++#define ERANDOM_MINOR 12
++
++static struct file_operations frandom_fops; /* Values assigned below */
++
++static int erandom_seeded = 0; /* Internal flag */
++
++static int frandom_major = FRANDOM_MAJOR;
++static int frandom_minor = FRANDOM_MINOR;
++static int erandom_minor = ERANDOM_MINOR;
++static int frandom_bufsize = 256;
++static int frandom_chunklimit = 0; /* =0 means unlimited */
++
++static struct cdev frandom_cdev;
++static struct cdev erandom_cdev;
++static struct class *frandom_class;
++struct device *frandom_device;
++struct device *erandom_device;
++
++MODULE_DESCRIPTION("Fast pseudo-random number generator");
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Eli Billauer");
++module_param(frandom_major, int, 0);
++module_param(frandom_minor, int, 0);
++module_param(erandom_minor, int, 0);
++module_param(frandom_bufsize, int, 0);
++module_param(frandom_chunklimit, int, 0);
++
++MODULE_PARM_DESC(frandom_major,"Major number of /dev/frandom and /dev/erandom");
++MODULE_PARM_DESC(frandom_minor,"Minor number of /dev/frandom");
++MODULE_PARM_DESC(erandom_minor,"Minor number of /dev/erandom");
++MODULE_PARM_DESC(frandom_bufsize,"Internal buffer size in bytes. Default is 256. Must be >= 256");
++MODULE_PARM_DESC(frandom_chunklimit,"Limit for read() blocks size. 0 (default) is unlimited, otherwise must be >= 256");
++
++struct frandom_state
++{
++ struct semaphore sem; /* Semaphore on the state structure */
++
++ u8 S[256]; /* The state array */
++ u8 i;
++ u8 j;
++
++ char *buf;
++};
++
++static struct frandom_state *erandom_state;
++
++static inline void swap_byte(u8 *a, u8 *b)
++{
++ u8 swapByte;
++
++ swapByte = *a;
++ *a = *b;
++ *b = swapByte;
++}
++
++static void init_rand_state(struct frandom_state *state, int seedflag);
++
++void erandom_get_random_bytes(char *buf, size_t count)
++{
++ struct frandom_state *state = erandom_state;
++ int k;
++
++ unsigned int i;
++ unsigned int j;
++ u8 *S;
++
++ /* If we fail to get the semaphore, we revert to external random data.
++ Since semaphore blocking is expected to be very rare, and interrupts
++ during these rare and very short periods of time even less frequent,
++ we take the better-safe-than-sorry approach, and fill the buffer
++ some expensive random data, in case the caller wasn't aware of this
++ possibility, and expects random data anyhow.
++ */
++
++ if (down_interruptible(&state->sem)) {
++ get_random_bytes(buf, count);
++ return;
++ }
++
++ /* We seed erandom as late as possible, hoping that the kernel's main
++ RNG is already restored in the boot sequence (not critical, but
++ better.
++ */
++
++ if (!erandom_seeded) {
++ erandom_seeded = 1;
++ init_rand_state(state, EXTERNAL_SEED);
++ printk(KERN_INFO "frandom: Seeded global generator now (used by erandom)\n");
++ }
++
++ i = state->i;
++ j = state->j;
++ S = state->S;
++
++ for (k=0; k<count; k++) {
++ i = (i + 1) & 0xff;
++ j = (j + S[i]) & 0xff;
++ swap_byte(&S[i], &S[j]);
++ *buf++ = S[(S[i] + S[j]) & 0xff];
++ }
++
++ state->i = i;
++ state->j = j;
++
++ up(&state->sem);
++}
++
++static void init_rand_state(struct frandom_state *state, int seedflag)
++{
++ unsigned int i, j, k;
++ u8 *S;
++ u8 *seed = state->buf;
++
++ if (seedflag == INTERNAL_SEED)
++ erandom_get_random_bytes(seed, 256);
++ else
++ get_random_bytes(seed, 256);
++
++ S = state->S;
++ for (i=0; i<256; i++)
++ *S++=i;
++
++ j=0;
++ S = state->S;
++
++ for (i=0; i<256; i++) {
++ j = (j + S[i] + *seed++) & 0xff;
++ swap_byte(&S[i], &S[j]);
++ }
++
++ /* It's considered good practice to discard the first 256 bytes
++ generated. So we do it:
++ */
++
++ i=0; j=0;
++ for (k=0; k<256; k++) {
++ i = (i + 1) & 0xff;
++ j = (j + S[i]) & 0xff;
++ swap_byte(&S[i], &S[j]);
++ }
++
++ state->i = i; /* Save state */
++ state->j = j;
++}
++
++static int frandom_open(struct inode *inode, struct file *filp)
++{
++
++ struct frandom_state *state;
++
++ int num = iminor(inode);
++
++ /* This should never happen, now when the minors are regsitered
++ * explicitly
++ */
++ if ((num != frandom_minor) && (num != erandom_minor)) return -ENODEV;
++
++ state = kmalloc(sizeof(struct frandom_state), GFP_KERNEL);
++ if (!state)
++ return -ENOMEM;
++
++ state->buf = kmalloc(frandom_bufsize, GFP_KERNEL);
++ if (!state->buf) {
++ kfree(state);
++ return -ENOMEM;
++ }
++
++ sema_init(&state->sem, 1); /* Init semaphore as a mutex */
++
++ if (num == frandom_minor)
++ init_rand_state(state, EXTERNAL_SEED);
++ else
++ init_rand_state(state, INTERNAL_SEED);
++
++ filp->private_data = state;
++
++ return 0; /* Success */
++}
++
++static int frandom_release(struct inode *inode, struct file *filp)
++{
++
++ struct frandom_state *state = filp->private_data;
++
++ kfree(state->buf);
++ kfree(state);
++
++ return 0;
++}
++
++static ssize_t frandom_read(struct file *filp, char *buf, size_t count,
++ loff_t *f_pos)
++{
++ struct frandom_state *state = filp->private_data;
++ ssize_t ret;
++ int dobytes, k;
++ char *localbuf;
++
++ unsigned int i;
++ unsigned int j;
++ u8 *S;
++
++ if (down_interruptible(&state->sem))
++ return -ERESTARTSYS;
++
++ if ((frandom_chunklimit > 0) && (count > frandom_chunklimit))
++ count = frandom_chunklimit;
++
++ ret = count; /* It's either everything or an error... */
++
++ i = state->i;
++ j = state->j;
++ S = state->S;
++
++ while (count) {
++ if (count > frandom_bufsize)
++ dobytes = frandom_bufsize;
++ else
++ dobytes = count;
++
++ localbuf = state->buf;
++
++ for (k=0; k<dobytes; k++) {
++ i = (i + 1) & 0xff;
++ j = (j + S[i]) & 0xff;
++ swap_byte(&S[i], &S[j]);
++ *localbuf++ = S[(S[i] + S[j]) & 0xff];
++ }
++
++ if (copy_to_user(buf, state->buf, dobytes)) {
++ ret = -EFAULT;
++ goto out;
++ }
++
++ buf += dobytes;
++ count -= dobytes;
++ }
++
++ out:
++ state->i = i;
++ state->j = j;
++
++ up(&state->sem);
++ return ret;
++}
++
++static struct file_operations frandom_fops = {
++ read: frandom_read,
++ open: frandom_open,
++ release: frandom_release,
++};
++
++static void frandom_cleanup_module(void) {
++ unregister_chrdev_region(MKDEV(frandom_major, erandom_minor), 1);
++ cdev_del(&erandom_cdev);
++ device_destroy(frandom_class, MKDEV(frandom_major, erandom_minor));
++
++ unregister_chrdev_region(MKDEV(frandom_major, frandom_minor), 1);
++ cdev_del(&frandom_cdev);
++ device_destroy(frandom_class, MKDEV(frandom_major, frandom_minor));
++ class_destroy(frandom_class);
++
++ kfree(erandom_state->buf);
++ kfree(erandom_state);
++}
++
++
++static int frandom_init_module(void)
++{
++ int result;
++
++ /* The buffer size MUST be at least 256 bytes, because we assume that
++ minimal length in init_rand_state().
++ */
++ if (frandom_bufsize < 256) {
++ printk(KERN_ERR "frandom: Refused to load because frandom_bufsize=%d < 256\n",frandom_bufsize);
++ return -EINVAL;
++ }
++ if ((frandom_chunklimit != 0) && (frandom_chunklimit < 256)) {
++ printk(KERN_ERR "frandom: Refused to load because frandom_chunklimit=%d < 256 and != 0\n",frandom_chunklimit);
++ return -EINVAL;
++ }
++
++ erandom_state = kmalloc(sizeof(struct frandom_state), GFP_KERNEL);
++ if (!erandom_state)
++ return -ENOMEM;
++
++ /* This specific buffer is only used for seeding, so we need
++ 256 bytes exactly */
++ erandom_state->buf = kmalloc(256, GFP_KERNEL);
++ if (!erandom_state->buf) {
++ kfree(erandom_state);
++ return -ENOMEM;
++ }
++
++ sema_init(&erandom_state->sem, 1); /* Init semaphore as a mutex */
++
++ erandom_seeded = 0;
++
++ frandom_class = class_create(THIS_MODULE, "fastrng");
++ if (IS_ERR(frandom_class)) {
++ result = PTR_ERR(frandom_class);
++ printk(KERN_WARNING "frandom: Failed to register class fastrng\n");
++ goto error0;
++ }
++
++ /*
++ * Register your major, and accept a dynamic number. This is the
++ * first thing to do, in order to avoid releasing other module's
++ * fops in frandom_cleanup_module()
++ */
++
++ cdev_init(&frandom_cdev, &frandom_fops);
++ frandom_cdev.owner = THIS_MODULE;
++ result = cdev_add(&frandom_cdev, MKDEV(frandom_major, frandom_minor), 1);
++ if (result) {
++ printk(KERN_WARNING "frandom: Failed to add cdev for /dev/frandom\n");
++ goto error1;
++ }
++
++ result = register_chrdev_region(MKDEV(frandom_major, frandom_minor), 1, "/dev/frandom");
++ if (result < 0) {
++ printk(KERN_WARNING "frandom: can't get major/minor %d/%d\n", frandom_major, frandom_minor);
++ goto error2;
++ }
++
++ frandom_device = device_create(frandom_class, NULL, MKDEV(frandom_major, frandom_minor), NULL, "frandom");
++
++ if (IS_ERR(frandom_device)) {
++ printk(KERN_WARNING "frandom: Failed to create frandom device\n");
++ goto error3;
++ }
++
++ cdev_init(&erandom_cdev, &frandom_fops);
++ erandom_cdev.owner = THIS_MODULE;
++ result = cdev_add(&erandom_cdev, MKDEV(frandom_major, erandom_minor), 1);
++ if (result) {
++ printk(KERN_WARNING "frandom: Failed to add cdev for /dev/erandom\n");
++ goto error4;
++ }
++
++ result = register_chrdev_region(MKDEV(frandom_major, erandom_minor), 1, "/dev/erandom");
++ if (result < 0) {
++ printk(KERN_WARNING "frandom: can't get major/minor %d/%d\n", frandom_major, erandom_minor);
++ goto error5;
++ }
++
++ erandom_device = device_create(frandom_class, NULL, MKDEV(frandom_major, erandom_minor), NULL, "erandom");
++
++ if (IS_ERR(erandom_device)) {
++ printk(KERN_WARNING "frandom: Failed to create erandom device\n");
++ goto error6;
++ }
++ return 0; /* succeed */
++
++ error6:
++ unregister_chrdev_region(MKDEV(frandom_major, erandom_minor), 1);
++ error5:
++ cdev_del(&erandom_cdev);
++ error4:
++ device_destroy(frandom_class, MKDEV(frandom_major, frandom_minor));
++ error3:
++ unregister_chrdev_region(MKDEV(frandom_major, frandom_minor), 1);
++ error2:
++ cdev_del(&frandom_cdev);
++ error1:
++ class_destroy(frandom_class);
++ error0:
++ kfree(erandom_state->buf);
++ kfree(erandom_state);
++
++ return result;
++}
++
++module_init(frandom_init_module);
++module_exit(frandom_cleanup_module);
++
++EXPORT_SYMBOL(erandom_get_random_bytes);
+diff -Nur linux-4.1.3/drivers/char/hw_random/bcm2708-rng.c linux-xbian-rpi/drivers/char/hw_random/bcm2708-rng.c
+--- linux-4.1.3/drivers/char/hw_random/bcm2708-rng.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/char/hw_random/bcm2708-rng.c 2015-07-28 01:20:58.186080826 +0200
+@@ -0,0 +1,118 @@
++/**
++ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ * 1. Redistributions of source code must retain the above copyright
++ * notice, this list of conditions, and the following disclaimer,
++ * without modification.
++ * 2. Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * 3. The names of the above-listed copyright holders may not be used
++ * to endorse or promote products derived from this software without
++ * specific prior written permission.
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") version 2, as published by the Free
++ * Software Foundation.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/hw_random.h>
++#include <linux/printk.h>
++
++#include <asm/io.h>
++#include <mach/hardware.h>
++#include <mach/platform.h>
++
++#define RNG_CTRL (0x0)
++#define RNG_STATUS (0x4)
++#define RNG_DATA (0x8)
++#define RNG_FF_THRESHOLD (0xc)
++
++/* enable rng */
++#define RNG_RBGEN 0x1
++/* double speed, less random mode */
++#define RNG_RBG2X 0x2
++
++/* the initial numbers generated are "less random" so will be discarded */
++#define RNG_WARMUP_COUNT 0x40000
++
++static int bcm2708_rng_data_read(struct hwrng *rng, u32 *buffer)
++{
++ void __iomem *rng_base = (void __iomem *)rng->priv;
++ unsigned words;
++ /* wait for a random number to be in fifo */
++ do {
++ words = __raw_readl(rng_base + RNG_STATUS)>>24;
++ }
++ while (words == 0);
++ /* read the random number */
++ *buffer = __raw_readl(rng_base + RNG_DATA);
++ return 4;
++}
++
++static struct hwrng bcm2708_rng_ops = {
++ .name = "bcm2708",
++ .data_read = bcm2708_rng_data_read,
++};
++
++static int __init bcm2708_rng_init(void)
++{
++ void __iomem *rng_base;
++ int err;
++
++ /* map peripheral */
++ rng_base = ioremap(RNG_BASE, 0x10);
++ pr_info("bcm2708_rng_init=%p\n", rng_base);
++ if (!rng_base) {
++ pr_err("bcm2708_rng_init failed to ioremap\n");
++ return -ENOMEM;
++ }
++ bcm2708_rng_ops.priv = (unsigned long)rng_base;
++
++ /* set warm-up count & enable */
++ __raw_writel(RNG_WARMUP_COUNT, rng_base + RNG_STATUS);
++ __raw_writel(RNG_RBGEN, rng_base + RNG_CTRL);
++
++ /* register driver */
++ err = hwrng_register(&bcm2708_rng_ops);
++ if (err) {
++ pr_err("bcm2708_rng_init hwrng_register()=%d\n", err);
++ iounmap(rng_base);
++ }
++ return err;
++}
++
++static void __exit bcm2708_rng_exit(void)
++{
++ void __iomem *rng_base = (void __iomem *)bcm2708_rng_ops.priv;
++ pr_info("bcm2708_rng_exit\n");
++ /* disable rng hardware */
++ __raw_writel(0, rng_base + RNG_CTRL);
++ /* unregister driver */
++ hwrng_unregister(&bcm2708_rng_ops);
++ iounmap(rng_base);
++}
++
++module_init(bcm2708_rng_init);
++module_exit(bcm2708_rng_exit);
++
++MODULE_DESCRIPTION("BCM2708 H/W Random Number Generator (RNG) driver");
++MODULE_LICENSE("GPL and additional rights");
+diff -Nur linux-4.1.3/drivers/char/hw_random/Kconfig linux-xbian-rpi/drivers/char/hw_random/Kconfig
+--- linux-4.1.3/drivers/char/hw_random/Kconfig 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/char/hw_random/Kconfig 2015-07-28 01:20:58.186080826 +0200
+@@ -90,7 +90,7 @@
+
+ config HW_RANDOM_BCM2835
+ tristate "Broadcom BCM2835 Random Number Generator support"
+- depends on ARCH_BCM2835
++ depends on ARCH_BCM2835 || ARCH_BCM2708 || ARCH_BCM2709
+ default HW_RANDOM
+ ---help---
+ This driver provides kernel-side support for the Random Number
+@@ -333,6 +333,17 @@
+
+ If unsure, say Y.
+
++config HW_RANDOM_BCM2708
++ tristate "BCM2708 generic true random number generator support"
++ depends on HW_RANDOM && (ARCH_BCM2708 || ARCH_BCM2709)
++ ---help---
++ This driver provides the kernel-side support for the BCM2708 hardware.
++
++ To compile this driver as a module, choose M here: the
++ module will be called bcm2708-rng.
++
++ If unsure, say N.
++
+ config HW_RANDOM_MSM
+ tristate "Qualcomm SoCs Random Number Generator support"
+ depends on HW_RANDOM && ARCH_QCOM
+diff -Nur linux-4.1.3/drivers/char/hw_random/Makefile linux-xbian-rpi/drivers/char/hw_random/Makefile
+--- linux-4.1.3/drivers/char/hw_random/Makefile 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/char/hw_random/Makefile 2015-07-28 01:20:58.186080826 +0200
+@@ -4,6 +4,7 @@
+
+ obj-$(CONFIG_HW_RANDOM) += rng-core.o
+ rng-core-y := core.o
++obj-$(CONFIG_HW_RANDOM_BCM2708) += bcm2708-rng.o
+ obj-$(CONFIG_HW_RANDOM_TIMERIOMEM) += timeriomem-rng.o
+ obj-$(CONFIG_HW_RANDOM_INTEL) += intel-rng.o
+ obj-$(CONFIG_HW_RANDOM_AMD) += amd-rng.o
+diff -Nur linux-4.1.3/drivers/char/Kconfig linux-xbian-rpi/drivers/char/Kconfig
+--- linux-4.1.3/drivers/char/Kconfig 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/char/Kconfig 2015-07-28 01:20:58.186080826 +0200
+@@ -590,6 +590,8 @@
+
+ source "drivers/s390/char/Kconfig"
+
++source "drivers/char/broadcom/Kconfig"
++
+ config MSM_SMD_PKT
+ bool "Enable device interface for some SMD packet ports"
+ default n
+diff -Nur linux-4.1.3/drivers/char/Makefile linux-xbian-rpi/drivers/char/Makefile
+--- linux-4.1.3/drivers/char/Makefile 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/char/Makefile 2015-07-28 01:20:58.186080826 +0200
+@@ -2,6 +2,7 @@
+ # Makefile for the kernel character device drivers.
+ #
+
++obj-m += frandom.o
+ obj-y += mem.o random.o
+ obj-$(CONFIG_TTY_PRINTK) += ttyprintk.o
+ obj-y += misc.o
+@@ -62,3 +63,4 @@
+
+ obj-$(CONFIG_TILE_SROM) += tile-srom.o
+ obj-$(CONFIG_XILLYBUS) += xillybus/
++obj-$(CONFIG_BRCM_CHAR_DRIVERS) += broadcom/
+diff -Nur linux-4.1.3/drivers/clocksource/arm_arch_timer.c linux-xbian-rpi/drivers/clocksource/arm_arch_timer.c
+--- linux-4.1.3/drivers/clocksource/arm_arch_timer.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/clocksource/arm_arch_timer.c 2015-07-28 01:20:58.190066605 +0200
+@@ -882,3 +882,39 @@
+ acpi_table_parse(ACPI_SIG_GTDT, arch_timer_acpi_init);
+ }
+ #endif
++
++int __init dc4_arch_timer_init(void)
++{
++ if (arch_timers_present & ARCH_CP15_TIMER) {
++ pr_warn("arch_timer: multiple nodes in dt, skipping\n");
++ return -1;
++ }
++
++ arch_timers_present |= ARCH_CP15_TIMER;
++
++ /* Try to determine the frequency from the device tree or CNTFRQ */
++ arch_timer_rate = 19200000;
++
++ arch_timer_ppi[PHYS_SECURE_PPI] = IRQ_ARM_LOCAL_CNTPSIRQ;
++ arch_timer_ppi[PHYS_NONSECURE_PPI] = IRQ_ARM_LOCAL_CNTPNSIRQ;
++ arch_timer_ppi[VIRT_PPI] = IRQ_ARM_LOCAL_CNTVIRQ;
++ arch_timer_ppi[HYP_PPI] = IRQ_ARM_LOCAL_CNTHPIRQ;
++
++ /*
++ * If HYP mode is available, we know that the physical timer
++ * has been configured to be accessible from PL1. Use it, so
++ * that a guest can use the virtual timer instead.
++ *
++ * If no interrupt provided for virtual timer, we'll have to
++ * stick to the physical timer. It'd better be accessible...
++ */
++ if (is_hyp_mode_available() || !arch_timer_ppi[VIRT_PPI]) {
++ arch_timer_use_virtual = false;
++ }
++
++ arch_timer_c3stop = 0;
++
++ arch_timer_register();
++ arch_timer_common_init();
++ return 0;
++}
+diff -Nur linux-4.1.3/drivers/cpufreq/bcm2835-cpufreq.c linux-xbian-rpi/drivers/cpufreq/bcm2835-cpufreq.c
+--- linux-4.1.3/drivers/cpufreq/bcm2835-cpufreq.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/cpufreq/bcm2835-cpufreq.c 2015-07-28 01:20:58.190066605 +0200
+@@ -0,0 +1,213 @@
++/*****************************************************************************
++* Copyright 2011 Broadcom Corporation. All rights reserved.
++*
++* Unless you and Broadcom execute a separate written software license
++* agreement governing use of this software, this software is licensed to you
++* under the terms of the GNU General Public License version 2, available at
++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
++*
++* Notwithstanding the above, under no circumstances may you combine this
++* software in any way with any other Broadcom software provided under a
++* license other than the GPL, without Broadcom's express prior written
++* consent.
++*****************************************************************************/
++
++/*****************************************************************************
++* FILENAME: bcm2835-cpufreq.h
++* DESCRIPTION: This driver dynamically manages the CPU Frequency of the ARM
++* processor. Messages are sent to Videocore either setting or requesting the
++* frequency of the ARM in order to match an appropiate frequency to the current
++* usage of the processor. The policy which selects the frequency to use is
++* defined in the kernel .config file, but can be changed during runtime.
++*****************************************************************************/
++
++/* ---------- INCLUDES ---------- */
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/cpufreq.h>
++#include <soc/bcm2835/raspberrypi-firmware.h>
++
++/* ---------- DEFINES ---------- */
++/*#define CPUFREQ_DEBUG_ENABLE*/ /* enable debugging */
++#define MODULE_NAME "bcm2835-cpufreq"
++
++#define VCMSG_ID_ARM_CLOCK 0x000000003 /* Clock/Voltage ID's */
++
++/* debug printk macros */
++#ifdef CPUFREQ_DEBUG_ENABLE
++#define print_debug(fmt,...) pr_debug("%s:%s:%d: "fmt, MODULE_NAME, __func__, __LINE__, ##__VA_ARGS__)
++#else
++#define print_debug(fmt,...)
++#endif
++#define print_err(fmt,...) pr_err("%s:%s:%d: "fmt, MODULE_NAME, __func__,__LINE__, ##__VA_ARGS__)
++#define print_info(fmt,...) pr_info("%s: "fmt, MODULE_NAME, ##__VA_ARGS__)
++
++/* ---------- GLOBALS ---------- */
++static struct cpufreq_driver bcm2835_cpufreq_driver; /* the cpufreq driver global */
++
++static struct cpufreq_frequency_table bcm2835_freq_table[] = {
++ {0, 0, 0},
++ {0, 0, 0},
++ {0, 0, CPUFREQ_TABLE_END},
++};
++
++/*
++ ===============================================
++ clk_rate either gets or sets the clock rates.
++ ===============================================
++*/
++
++static int bcm2835_cpufreq_clock_property(u32 tag, u32 id, u32 *val)
++{
++ struct rpi_firmware *fw = rpi_firmware_get(NULL);
++ struct {
++ u32 id;
++ u32 val;
++ } packet;
++ int ret;
++
++ packet.id = id;
++ packet.val = *val;
++ ret = rpi_firmware_property(fw, tag, &packet, sizeof(packet));
++ if (ret)
++ return ret;
++
++ *val = packet.val;
++
++ return 0;
++}
++
++static uint32_t bcm2835_cpufreq_set_clock(int cur_rate, int arm_rate)
++{
++ u32 rate = arm_rate * 1000;
++ int ret;
++
++ ret = bcm2835_cpufreq_clock_property(RPI_FIRMWARE_SET_CLOCK_RATE, VCMSG_ID_ARM_CLOCK, &rate);
++ if (ret) {
++ print_err("Failed to set clock: %d (%d)\n", arm_rate, ret);
++ return 0;
++ }
++
++ rate /= 1000;
++ print_debug("Setting new frequency = %d -> %d (actual %d)\n", cur_rate, arm_rate, rate);
++
++ return rate;
++}
++
++static uint32_t bcm2835_cpufreq_get_clock(int tag)
++{
++ u32 rate;
++ int ret;
++
++ ret = bcm2835_cpufreq_clock_property(tag, VCMSG_ID_ARM_CLOCK, &rate);
++ if (ret) {
++ print_err("Failed to get clock (%d)\n", ret);
++ return 0;
++ }
++
++ rate /= 1000;
++ print_debug("%s frequency = %u\n",
++ tag == RPI_FIRMWARE_GET_CLOCK_RATE ? "Current":
++ tag == RPI_FIRMWARE_GET_MIN_CLOCK_RATE ? "Min":
++ tag == RPI_FIRMWARE_GET_MAX_CLOCK_RATE ? "Max":
++ "Unexpected", rate);
++
++ return rate;
++}
++
++/*
++ ====================================================
++ Module Initialisation registers the cpufreq driver
++ ====================================================
++*/
++static int __init bcm2835_cpufreq_module_init(void)
++{
++ print_debug("IN\n");
++ return cpufreq_register_driver(&bcm2835_cpufreq_driver);
++}
++
++/*
++ =============
++ Module exit
++ =============
++*/
++static void __exit bcm2835_cpufreq_module_exit(void)
++{
++ print_debug("IN\n");
++ cpufreq_unregister_driver(&bcm2835_cpufreq_driver);
++ return;
++}
++
++/*
++ ==============================================================
++ Initialisation function sets up the CPU policy for first use
++ ==============================================================
++*/
++static int bcm2835_cpufreq_driver_init(struct cpufreq_policy *policy)
++{
++ /* measured value of how long it takes to change frequency */
++ const unsigned int transition_latency = 355000; /* ns */
++
++ if (!rpi_firmware_get(NULL)) {
++ print_err("Firmware is not available\n");
++ return -ENODEV;
++ }
++
++ /* now find out what the maximum and minimum frequencies are */
++ bcm2835_freq_table[0].frequency = bcm2835_cpufreq_get_clock(RPI_FIRMWARE_GET_MIN_CLOCK_RATE);
++ bcm2835_freq_table[1].frequency = bcm2835_cpufreq_get_clock(RPI_FIRMWARE_GET_MAX_CLOCK_RATE);
++
++ print_info("min=%d max=%d\n", bcm2835_freq_table[0].frequency, bcm2835_freq_table[1].frequency);
++ return cpufreq_generic_init(policy, bcm2835_freq_table, transition_latency);
++}
++
++/*
++ =====================================================================
++ Target index function chooses the requested frequency from the table
++ =====================================================================
++*/
++
++static int bcm2835_cpufreq_driver_target_index(struct cpufreq_policy *policy, unsigned int state)
++{
++ unsigned int target_freq = bcm2835_freq_table[state].frequency;
++ unsigned int cur = bcm2835_cpufreq_set_clock(policy->cur, target_freq);
++
++ if (!cur)
++ {
++ print_err("Error occurred setting a new frequency (%d)\n", target_freq);
++ return -EINVAL;
++ }
++ print_debug("%s: %i: freq %d->%d\n", policy->governor->name, state, policy->cur, cur);
++ return 0;
++}
++
++/*
++ ======================================================
++ Get function returns the current frequency from table
++ ======================================================
++*/
++
++static unsigned int bcm2835_cpufreq_driver_get(unsigned int cpu)
++{
++ unsigned int actual_rate = bcm2835_cpufreq_get_clock(RPI_FIRMWARE_GET_CLOCK_RATE);
++ print_debug("cpu%d: freq=%d\n", cpu, actual_rate);
++ return actual_rate <= bcm2835_freq_table[0].frequency ? bcm2835_freq_table[0].frequency : bcm2835_freq_table[1].frequency;
++}
++
++/* the CPUFreq driver */
++static struct cpufreq_driver bcm2835_cpufreq_driver = {
++ .name = "BCM2835 CPUFreq",
++ .init = bcm2835_cpufreq_driver_init,
++ .verify = cpufreq_generic_frequency_table_verify,
++ .target_index = bcm2835_cpufreq_driver_target_index,
++ .get = bcm2835_cpufreq_driver_get,
++ .attr = cpufreq_generic_attr,
++};
++
++MODULE_AUTHOR("Dorian Peake and Dom Cobley");
++MODULE_DESCRIPTION("CPU frequency driver for BCM2835 chip");
++MODULE_LICENSE("GPL");
++
++module_init(bcm2835_cpufreq_module_init);
++module_exit(bcm2835_cpufreq_module_exit);
+diff -Nur linux-4.1.3/drivers/cpufreq/Kconfig.arm linux-xbian-rpi/drivers/cpufreq/Kconfig.arm
+--- linux-4.1.3/drivers/cpufreq/Kconfig.arm 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/cpufreq/Kconfig.arm 2015-07-28 01:20:58.190066605 +0200
+@@ -258,6 +258,15 @@
+ help
+ This adds the CPUFreq driver support for SPEAr SOCs.
+
++config ARM_BCM2835_CPUFREQ
++ depends on BCM2708_MBOX
++ bool "BCM2835 Driver"
++ default y
++ help
++ This adds the CPUFreq driver for BCM2835
++
++ If in doubt, say N.
++
+ config ARM_TEGRA_CPUFREQ
+ bool "TEGRA CPUFreq support"
+ depends on ARCH_TEGRA
+diff -Nur linux-4.1.3/drivers/cpufreq/Makefile linux-xbian-rpi/drivers/cpufreq/Makefile
+--- linux-4.1.3/drivers/cpufreq/Makefile 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/cpufreq/Makefile 2015-07-28 01:20:58.190066605 +0200
+@@ -77,6 +77,7 @@
+ obj-$(CONFIG_ARM_SA1100_CPUFREQ) += sa1100-cpufreq.o
+ obj-$(CONFIG_ARM_SA1110_CPUFREQ) += sa1110-cpufreq.o
+ obj-$(CONFIG_ARM_SPEAR_CPUFREQ) += spear-cpufreq.o
++obj-$(CONFIG_ARM_BCM2835_CPUFREQ) += bcm2835-cpufreq.o
+ obj-$(CONFIG_ARM_TEGRA_CPUFREQ) += tegra-cpufreq.o
+ obj-$(CONFIG_ARM_VEXPRESS_SPC_CPUFREQ) += vexpress-spc-cpufreq.o
+
+diff -Nur linux-4.1.3/drivers/dma/bcm2708-dmaengine.c linux-xbian-rpi/drivers/dma/bcm2708-dmaengine.c
+--- linux-4.1.3/drivers/dma/bcm2708-dmaengine.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/dma/bcm2708-dmaengine.c 2015-07-28 01:20:58.194052384 +0200
+@@ -0,0 +1,1299 @@
++/*
++ * BCM2835 DMA engine support
++ *
++ * This driver supports cyclic and scatter/gather DMA transfers.
++ *
++ * Author: Florian Meier <florian.meier@koalo.de>
++ * Gellert Weisz <gellert@raspberrypi.org>
++ * Copyright 2013-2014
++ *
++ * Based on
++ * OMAP DMAengine support by Russell King
++ *
++ * BCM2708 DMA Driver
++ * Copyright (C) 2010 Broadcom
++ *
++ * Raspberry Pi PCM I2S ALSA Driver
++ * Copyright (c) by Phil Poole 2013
++ *
++ * MARVELL MMP Peripheral DMA Driver
++ * Copyright 2012 Marvell International Ltd.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ */
++
++#include <linux/dmaengine.h>
++#include <linux/dma-mapping.h>
++#include <linux/err.h>
++#include <linux/init.h>
++#include <linux/interrupt.h>
++#include <linux/list.h>
++#include <linux/module.h>
++#include <linux/platform_data/dma-bcm2708.h>
++#include <linux/platform_device.h>
++#include <linux/slab.h>
++#include <linux/io.h>
++#include <linux/spinlock.h>
++#include <linux/of.h>
++#include <linux/of_dma.h>
++
++#include "virt-dma.h"
++
++static unsigned dma_debug;
++
++/*
++ * Legacy DMA API
++ */
++
++#ifdef CONFIG_DMA_BCM2708_LEGACY
++
++#define CACHE_LINE_MASK 31
++#define DEFAULT_DMACHAN_BITMAP 0x10 /* channel 4 only */
++
++/* valid only for channels 0 - 14, 15 has its own base address */
++#define BCM2708_DMA_CHAN(n) ((n) << 8) /* base address */
++#define BCM2708_DMA_CHANIO(dma_base, n) \
++ ((void __iomem *)((char *)(dma_base) + BCM2708_DMA_CHAN(n)))
++
++struct vc_dmaman {
++ void __iomem *dma_base;
++ u32 chan_available; /* bitmap of available channels */
++ u32 has_feature[BCM_DMA_FEATURE_COUNT]; /* bitmap of feature presence */
++ struct mutex lock;
++};
++
++static struct device *dmaman_dev; /* we assume there's only one! */
++static struct vc_dmaman *g_dmaman; /* DMA manager */
++static int dmachans = -1; /* module parameter */
++
++/* DMA Auxiliary Functions */
++
++/* A DMA buffer on an arbitrary boundary may separate a cache line into a
++ section inside the DMA buffer and another section outside it.
++ Even if we flush DMA buffers from the cache there is always the chance that
++ during a DMA someone will access the part of a cache line that is outside
++ the DMA buffer - which will then bring in unwelcome data.
++ Without being able to dictate our own buffer pools we must insist that
++ DMA buffers consist of a whole number of cache lines.
++*/
++extern int bcm_sg_suitable_for_dma(struct scatterlist *sg_ptr, int sg_len)
++{
++ int i;
++
++ for (i = 0; i < sg_len; i++) {
++ if (sg_ptr[i].offset & CACHE_LINE_MASK ||
++ sg_ptr[i].length & CACHE_LINE_MASK)
++ return 0;
++ }
++
++ return 1;
++}
++EXPORT_SYMBOL_GPL(bcm_sg_suitable_for_dma);
++
++extern void bcm_dma_start(void __iomem *dma_chan_base,
++ dma_addr_t control_block)
++{
++ dsb(); /* ARM data synchronization (push) operation */
++
++ writel(control_block, dma_chan_base + BCM2708_DMA_ADDR);
++ writel(BCM2708_DMA_ACTIVE, dma_chan_base + BCM2708_DMA_CS);
++}
++EXPORT_SYMBOL_GPL(bcm_dma_start);
++
++extern void bcm_dma_wait_idle(void __iomem *dma_chan_base)
++{
++ dsb();
++
++ /* ugly busy wait only option for now */
++ while (readl(dma_chan_base + BCM2708_DMA_CS) & BCM2708_DMA_ACTIVE)
++ cpu_relax();
++}
++EXPORT_SYMBOL_GPL(bcm_dma_wait_idle);
++
++extern bool bcm_dma_is_busy(void __iomem *dma_chan_base)
++{
++ dsb();
++
++ return readl(dma_chan_base + BCM2708_DMA_CS) & BCM2708_DMA_ACTIVE;
++}
++EXPORT_SYMBOL_GPL(bcm_dma_is_busy);
++
++/* Complete an ongoing DMA (assuming its results are to be ignored)
++ Does nothing if there is no DMA in progress.
++ This routine waits for the current AXI transfer to complete before
++ terminating the current DMA. If the current transfer is hung on a DREQ used
++ by an uncooperative peripheral the AXI transfer may never complete. In this
++ case the routine times out and return a non-zero error code.
++ Use of this routine doesn't guarantee that the ongoing or aborted DMA
++ does not produce an interrupt.
++*/
++extern int bcm_dma_abort(void __iomem *dma_chan_base)
++{
++ unsigned long int cs;
++ int rc = 0;
++
++ cs = readl(dma_chan_base + BCM2708_DMA_CS);
++
++ if (BCM2708_DMA_ACTIVE & cs) {
++ long int timeout = 10000;
++
++ /* write 0 to the active bit - pause the DMA */
++ writel(0, dma_chan_base + BCM2708_DMA_CS);
++
++ /* wait for any current AXI transfer to complete */
++ while (0 != (cs & BCM2708_DMA_ISPAUSED) && --timeout >= 0)
++ cs = readl(dma_chan_base + BCM2708_DMA_CS);
++
++ if (0 != (cs & BCM2708_DMA_ISPAUSED)) {
++ /* we'll un-pause when we set of our next DMA */
++ rc = -ETIMEDOUT;
++
++ } else if (BCM2708_DMA_ACTIVE & cs) {
++ /* terminate the control block chain */
++ writel(0, dma_chan_base + BCM2708_DMA_NEXTCB);
++
++ /* abort the whole DMA */
++ writel(BCM2708_DMA_ABORT | BCM2708_DMA_ACTIVE,
++ dma_chan_base + BCM2708_DMA_CS);
++ }
++ }
++
++ return rc;
++}
++EXPORT_SYMBOL_GPL(bcm_dma_abort);
++
++ /* DMA Manager Device Methods */
++
++static void vc_dmaman_init(struct vc_dmaman *dmaman, void __iomem *dma_base,
++ u32 chans_available)
++{
++ dmaman->dma_base = dma_base;
++ dmaman->chan_available = chans_available;
++ dmaman->has_feature[BCM_DMA_FEATURE_FAST_ORD] = 0x0c; /* 2 & 3 */
++ dmaman->has_feature[BCM_DMA_FEATURE_BULK_ORD] = 0x01; /* 0 */
++ dmaman->has_feature[BCM_DMA_FEATURE_NORMAL_ORD] = 0xfe; /* 1 to 7 */
++ dmaman->has_feature[BCM_DMA_FEATURE_LITE_ORD] = 0x7f00; /* 8 to 14 */
++}
++
++static int vc_dmaman_chan_alloc(struct vc_dmaman *dmaman,
++ unsigned preferred_feature_set)
++{
++ u32 chans;
++ int chan = 0;
++ int feature;
++
++ chans = dmaman->chan_available;
++ for (feature = 0; feature < BCM_DMA_FEATURE_COUNT; feature++)
++ /* select the subset of available channels with the desired
++ feature so long as some of the candidate channels have that
++ feature */
++ if ((preferred_feature_set & (1 << feature)) &&
++ (chans & dmaman->has_feature[feature]))
++ chans &= dmaman->has_feature[feature];
++
++ if (!chans)
++ return -ENOENT;
++
++ /* return the ordinal of the first channel in the bitmap */
++ while (chans != 0 && (chans & 1) == 0) {
++ chans >>= 1;
++ chan++;
++ }
++ /* claim the channel */
++ dmaman->chan_available &= ~(1 << chan);
++
++ return chan;
++}
++
++static int vc_dmaman_chan_free(struct vc_dmaman *dmaman, int chan)
++{
++ if (chan < 0)
++ return -EINVAL;
++
++ if ((1 << chan) & dmaman->chan_available)
++ return -EIDRM;
++
++ dmaman->chan_available |= (1 << chan);
++
++ return 0;
++}
++
++/* DMA Manager Monitor */
++
++extern int bcm_dma_chan_alloc(unsigned preferred_feature_set,
++ void __iomem **out_dma_base, int *out_dma_irq)
++{
++ struct vc_dmaman *dmaman = g_dmaman;
++ struct platform_device *pdev = to_platform_device(dmaman_dev);
++ struct resource *r;
++ int chan;
++
++ if (!dmaman_dev)
++ return -ENODEV;
++
++ mutex_lock(&dmaman->lock);
++ chan = vc_dmaman_chan_alloc(dmaman, preferred_feature_set);
++ if (chan < 0)
++ goto out;
++
++ r = platform_get_resource(pdev, IORESOURCE_IRQ, (unsigned int)chan);
++ if (!r) {
++ dev_err(dmaman_dev, "failed to get irq for DMA channel %d\n",
++ chan);
++ vc_dmaman_chan_free(dmaman, chan);
++ chan = -ENOENT;
++ goto out;
++ }
++
++ *out_dma_base = BCM2708_DMA_CHANIO(dmaman->dma_base, chan);
++ *out_dma_irq = r->start;
++ dev_dbg(dmaman_dev,
++ "Legacy API allocated channel=%d, base=%p, irq=%i\n",
++ chan, *out_dma_base, *out_dma_irq);
++
++out:
++ mutex_unlock(&dmaman->lock);
++
++ return chan;
++}
++EXPORT_SYMBOL_GPL(bcm_dma_chan_alloc);
++
++extern int bcm_dma_chan_free(int channel)
++{
++ struct vc_dmaman *dmaman = g_dmaman;
++ int rc;
++
++ if (!dmaman_dev)
++ return -ENODEV;
++
++ mutex_lock(&dmaman->lock);
++ rc = vc_dmaman_chan_free(dmaman, channel);
++ mutex_unlock(&dmaman->lock);
++
++ return rc;
++}
++EXPORT_SYMBOL_GPL(bcm_dma_chan_free);
++
++static int bcm_dmaman_probe(struct platform_device *pdev)
++{
++ struct device *dev = &pdev->dev;
++ struct vc_dmaman *dmaman;
++ struct resource *r;
++ void __iomem *dma_base;
++ uint32_t val;
++
++ if (!of_property_read_u32(dev->of_node,
++ "brcm,dma-channel-mask", &val))
++ dmachans = val;
++ else if (dmachans == -1)
++ dmachans = DEFAULT_DMACHAN_BITMAP;
++
++ dmaman = devm_kzalloc(dev, sizeof(*dmaman), GFP_KERNEL);
++ if (!dmaman)
++ return -ENOMEM;
++
++ mutex_init(&dmaman->lock);
++ r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ dma_base = devm_ioremap_resource(dev, r);
++ if (IS_ERR(dma_base))
++ return PTR_ERR(dma_base);
++
++ vc_dmaman_init(dmaman, dma_base, dmachans);
++ g_dmaman = dmaman;
++ dmaman_dev = dev;
++
++ dev_info(dev, "DMA legacy API manager at %p, dmachans=0x%x\n",
++ dma_base, dmachans);
++
++ return 0;
++}
++
++static int bcm_dmaman_remove(struct platform_device *pdev)
++{
++ dmaman_dev = NULL;
++
++ return 0;
++}
++
++#else /* CONFIG_DMA_BCM2708_LEGACY */
++
++static int bcm_dmaman_remove(struct platform_device *pdev)
++{
++ return 0;
++}
++
++#endif /* CONFIG_DMA_BCM2708_LEGACY */
++
++/*
++ * DMA engine
++ */
++
++struct bcm2835_dmadev {
++ struct dma_device ddev;
++ spinlock_t lock;
++ void __iomem *base;
++ struct device_dma_parameters dma_parms;
++};
++
++struct bcm2835_dma_cb {
++ uint32_t info;
++ uint32_t src;
++ uint32_t dst;
++ uint32_t length;
++ uint32_t stride;
++ uint32_t next;
++ uint32_t pad[2];
++};
++
++struct bcm2835_chan {
++ struct virt_dma_chan vc;
++ struct list_head node;
++
++ struct dma_slave_config cfg;
++ bool cyclic;
++
++ int ch;
++ struct bcm2835_desc *desc;
++
++ void __iomem *chan_base;
++ int irq_number;
++
++ unsigned int dreq;
++};
++
++struct bcm2835_desc {
++ struct virt_dma_desc vd;
++ enum dma_transfer_direction dir;
++
++ unsigned int control_block_size;
++ struct bcm2835_dma_cb *control_block_base;
++ dma_addr_t control_block_base_phys;
++
++ unsigned int frames;
++ size_t size;
++};
++
++#define BCM2835_DMA_CS 0x00
++#define BCM2835_DMA_ADDR 0x04
++#define BCM2835_DMA_SOURCE_AD 0x0c
++#define BCM2835_DMA_DEST_AD 0x10
++#define BCM2835_DMA_NEXTCB 0x1C
++
++/* DMA CS Control and Status bits */
++#define BCM2835_DMA_ACTIVE BIT(0)
++#define BCM2835_DMA_INT BIT(2)
++#define BCM2835_DMA_ISPAUSED BIT(4) /* Pause requested or not active */
++#define BCM2835_DMA_ISHELD BIT(5) /* Is held by DREQ flow control */
++#define BCM2835_DMA_ERR BIT(8)
++#define BCM2835_DMA_ABORT BIT(30) /* Stop current CB, go to next, WO */
++#define BCM2835_DMA_RESET BIT(31) /* WO, self clearing */
++
++#define BCM2835_DMA_INT_EN BIT(0)
++#define BCM2835_DMA_WAIT_RESP BIT(3)
++#define BCM2835_DMA_D_INC BIT(4)
++#define BCM2835_DMA_D_WIDTH BIT(5)
++#define BCM2835_DMA_D_DREQ BIT(6)
++#define BCM2835_DMA_S_INC BIT(8)
++#define BCM2835_DMA_S_WIDTH BIT(9)
++#define BCM2835_DMA_S_DREQ BIT(10)
++
++#define BCM2835_DMA_PER_MAP(x) ((x) << 16)
++#define BCM2835_DMA_WAITS(x) (((x)&0x1f) << 21)
++
++#define SDHCI_BCM_DMA_WAITS 0 /* delays slowing DMA transfers: 0-31 */
++
++#define BCM2835_DMA_DATA_TYPE_S8 1
++#define BCM2835_DMA_DATA_TYPE_S16 2
++#define BCM2835_DMA_DATA_TYPE_S32 4
++#define BCM2835_DMA_DATA_TYPE_S128 16
++
++#define BCM2835_DMA_BULK_MASK BIT(0)
++#define BCM2835_DMA_FIQ_MASK (BIT(2) | BIT(3))
++
++
++/* Valid only for channels 0 - 14, 15 has its own base address */
++#define BCM2835_DMA_CHAN(n) ((n) << 8) /* Base address */
++#define BCM2835_DMA_CHANIO(base, n) ((base) + BCM2835_DMA_CHAN(n))
++
++#define MAX_LITE_TRANSFER 32768
++#define MAX_NORMAL_TRANSFER 1073741824
++
++static inline struct bcm2835_dmadev *to_bcm2835_dma_dev(struct dma_device *d)
++{
++ return container_of(d, struct bcm2835_dmadev, ddev);
++}
++
++static inline struct bcm2835_chan *to_bcm2835_dma_chan(struct dma_chan *c)
++{
++ return container_of(c, struct bcm2835_chan, vc.chan);
++}
++
++static inline struct bcm2835_desc *to_bcm2835_dma_desc(
++ struct dma_async_tx_descriptor *t)
++{
++ return container_of(t, struct bcm2835_desc, vd.tx);
++}
++
++static void dma_dumpregs(struct bcm2835_chan *c)
++{
++ pr_debug("-------------DMA DUMPREGS-------------\n");
++ pr_debug("CS= %u\n",
++ readl(c->chan_base + BCM2835_DMA_CS));
++ pr_debug("ADDR= %u\n",
++ readl(c->chan_base + BCM2835_DMA_ADDR));
++ pr_debug("SOURCE_ADDR= %u\n",
++ readl(c->chan_base + BCM2835_DMA_SOURCE_AD));
++ pr_debug("DEST_AD= %u\n",
++ readl(c->chan_base + BCM2835_DMA_DEST_AD));
++ pr_debug("NEXTCB= %u\n",
++ readl(c->chan_base + BCM2835_DMA_NEXTCB));
++ pr_debug("--------------------------------------\n");
++}
++
++static void bcm2835_dma_desc_free(struct virt_dma_desc *vd)
++{
++ struct bcm2835_desc *desc = container_of(vd, struct bcm2835_desc, vd);
++ dma_free_coherent(desc->vd.tx.chan->device->dev,
++ desc->control_block_size,
++ desc->control_block_base,
++ desc->control_block_base_phys);
++ kfree(desc);
++}
++
++static int bcm2835_dma_abort(void __iomem *chan_base)
++{
++ unsigned long cs;
++ long int timeout = 10000;
++
++ cs = readl(chan_base + BCM2835_DMA_CS);
++ if (!(cs & BCM2835_DMA_ACTIVE))
++ return 0;
++
++ /* Write 0 to the active bit - Pause the DMA */
++ writel(0, chan_base + BCM2835_DMA_CS);
++
++ /* Wait for any current AXI transfer to complete */
++ while ((cs & BCM2835_DMA_ISPAUSED) && --timeout) {
++ cpu_relax();
++ cs = readl(chan_base + BCM2835_DMA_CS);
++ }
++
++ /* We'll un-pause when we set of our next DMA */
++ if (!timeout)
++ return -ETIMEDOUT;
++
++ if (!(cs & BCM2835_DMA_ACTIVE))
++ return 0;
++
++ /* Terminate the control block chain */
++ writel(0, chan_base + BCM2835_DMA_NEXTCB);
++
++ /* Abort the whole DMA */
++ writel(BCM2835_DMA_ABORT | BCM2835_DMA_ACTIVE,
++ chan_base + BCM2835_DMA_CS);
++
++ return 0;
++}
++
++
++static void bcm2835_dma_start_desc(struct bcm2835_chan *c)
++{
++ struct virt_dma_desc *vd = vchan_next_desc(&c->vc);
++ struct bcm2835_desc *d;
++
++ if (!vd) {
++ c->desc = NULL;
++ return;
++ }
++
++ list_del(&vd->node);
++
++ c->desc = d = to_bcm2835_dma_desc(&vd->tx);
++
++ writel(d->control_block_base_phys, c->chan_base + BCM2835_DMA_ADDR);
++ writel(BCM2835_DMA_ACTIVE, c->chan_base + BCM2835_DMA_CS);
++
++}
++
++static irqreturn_t bcm2835_dma_callback(int irq, void *data)
++{
++ struct bcm2835_chan *c = data;
++ struct bcm2835_desc *d;
++ unsigned long flags;
++
++ spin_lock_irqsave(&c->vc.lock, flags);
++
++ /* Acknowledge interrupt */
++ writel(BCM2835_DMA_INT, c->chan_base + BCM2835_DMA_CS);
++
++ d = c->desc;
++
++ if (d) {
++ if (c->cyclic) {
++ vchan_cyclic_callback(&d->vd);
++
++ /* Keep the DMA engine running */
++ writel(BCM2835_DMA_ACTIVE,
++ c->chan_base + BCM2835_DMA_CS);
++
++ } else {
++ vchan_cookie_complete(&c->desc->vd);
++ bcm2835_dma_start_desc(c);
++ }
++ }
++
++ spin_unlock_irqrestore(&c->vc.lock, flags);
++
++ return IRQ_HANDLED;
++}
++
++static int bcm2835_dma_alloc_chan_resources(struct dma_chan *chan)
++{
++ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
++ int ret;
++
++ dev_dbg(c->vc.chan.device->dev,
++ "Allocating DMA channel %d\n", c->ch);
++
++ ret = request_irq(c->irq_number,
++ bcm2835_dma_callback, 0, "DMA IRQ", c);
++
++ return ret;
++}
++
++static void bcm2835_dma_free_chan_resources(struct dma_chan *chan)
++{
++ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
++
++ vchan_free_chan_resources(&c->vc);
++ free_irq(c->irq_number, c);
++
++ dev_dbg(c->vc.chan.device->dev, "Freeing DMA channel %u\n", c->ch);
++}
++
++static size_t bcm2835_dma_desc_size(struct bcm2835_desc *d)
++{
++ return d->size;
++}
++
++static size_t bcm2835_dma_desc_size_pos(struct bcm2835_desc *d, dma_addr_t addr)
++{
++ unsigned int i;
++ size_t size;
++
++ for (size = i = 0; i < d->frames; i++) {
++ struct bcm2835_dma_cb *control_block =
++ &d->control_block_base[i];
++ size_t this_size = control_block->length;
++ dma_addr_t dma;
++
++ if (d->dir == DMA_DEV_TO_MEM)
++ dma = control_block->dst;
++ else
++ dma = control_block->src;
++
++ if (size)
++ size += this_size;
++ else if (addr >= dma && addr < dma + this_size)
++ size += dma + this_size - addr;
++ }
++
++ return size;
++}
++
++static enum dma_status bcm2835_dma_tx_status(struct dma_chan *chan,
++ dma_cookie_t cookie, struct dma_tx_state *txstate)
++{
++ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
++ struct bcm2835_desc *d;
++ struct virt_dma_desc *vd;
++ enum dma_status ret;
++ unsigned long flags;
++ dma_addr_t pos;
++
++ ret = dma_cookie_status(chan, cookie, txstate);
++ if (ret == DMA_COMPLETE || !txstate)
++ return ret;
++
++ spin_lock_irqsave(&c->vc.lock, flags);
++ vd = vchan_find_desc(&c->vc, cookie);
++ if (vd) {
++ txstate->residue =
++ bcm2835_dma_desc_size(to_bcm2835_dma_desc(&vd->tx));
++ } else if (c->desc && c->desc->vd.tx.cookie == cookie) {
++ d = c->desc;
++
++ if (d->dir == DMA_MEM_TO_DEV)
++ pos = readl(c->chan_base + BCM2835_DMA_SOURCE_AD);
++ else if (d->dir == DMA_DEV_TO_MEM)
++ pos = readl(c->chan_base + BCM2835_DMA_DEST_AD);
++ else
++ pos = 0;
++
++ txstate->residue = bcm2835_dma_desc_size_pos(d, pos);
++ } else {
++ txstate->residue = 0;
++ }
++
++ spin_unlock_irqrestore(&c->vc.lock, flags);
++
++ return ret;
++}
++
++static void bcm2835_dma_issue_pending(struct dma_chan *chan)
++{
++ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
++ unsigned long flags;
++
++ spin_lock_irqsave(&c->vc.lock, flags);
++ if (vchan_issue_pending(&c->vc) && !c->desc)
++ bcm2835_dma_start_desc(c);
++
++ spin_unlock_irqrestore(&c->vc.lock, flags);
++}
++
++static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_cyclic(
++ struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
++ size_t period_len, enum dma_transfer_direction direction,
++ unsigned long flags)
++{
++ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
++ enum dma_slave_buswidth dev_width;
++ struct bcm2835_desc *d;
++ dma_addr_t dev_addr;
++ unsigned int es, sync_type;
++ unsigned int frame, max_size;
++
++ /* Grab configuration */
++ if (!is_slave_direction(direction)) {
++ dev_err(chan->device->dev, "%s: bad direction?\n", __func__);
++ return NULL;
++ }
++
++ if (direction == DMA_DEV_TO_MEM) {
++ dev_addr = c->cfg.src_addr;
++ dev_width = c->cfg.src_addr_width;
++ sync_type = BCM2835_DMA_S_DREQ;
++ } else {
++ dev_addr = c->cfg.dst_addr;
++ dev_width = c->cfg.dst_addr_width;
++ sync_type = BCM2835_DMA_D_DREQ;
++ }
++
++ /* Bus width translates to the element size (ES) */
++ switch (dev_width) {
++ case DMA_SLAVE_BUSWIDTH_4_BYTES:
++ es = BCM2835_DMA_DATA_TYPE_S32;
++ break;
++ default:
++ return NULL;
++ }
++
++ /* Now allocate and setup the descriptor. */
++ d = kzalloc(sizeof(*d), GFP_NOWAIT);
++ if (!d)
++ return NULL;
++
++ d->dir = direction;
++
++ if (c->ch >= 8) /* we have a LITE channel */
++ max_size = MAX_LITE_TRANSFER;
++ else
++ max_size = MAX_NORMAL_TRANSFER;
++ period_len = min(period_len, max_size);
++
++ d->frames = (buf_len-1) / period_len + 1;
++
++ /* Allocate memory for control blocks */
++ d->control_block_size = d->frames * sizeof(struct bcm2835_dma_cb);
++ d->control_block_base = dma_zalloc_coherent(chan->device->dev,
++ d->control_block_size, &d->control_block_base_phys,
++ GFP_NOWAIT);
++
++ if (!d->control_block_base) {
++ kfree(d);
++ return NULL;
++ }
++
++ /*
++ * Iterate over all frames, create a control block
++ * for each frame and link them together.
++ */
++ for (frame = 0; frame < d->frames; frame++) {
++ struct bcm2835_dma_cb *control_block =
++ &d->control_block_base[frame];
++
++ /* Setup adresses */
++ if (d->dir == DMA_DEV_TO_MEM) {
++ control_block->info = BCM2835_DMA_D_INC;
++ control_block->src = dev_addr;
++ control_block->dst = buf_addr + frame * period_len;
++ } else {
++ control_block->info = BCM2835_DMA_S_INC;
++ control_block->src = buf_addr + frame * period_len;
++ control_block->dst = dev_addr;
++ }
++
++ /* Enable interrupt */
++ control_block->info |= BCM2835_DMA_INT_EN;
++
++ /* Setup synchronization */
++ if (sync_type != 0)
++ control_block->info |= sync_type;
++
++ /* Setup DREQ channel */
++ if (c->cfg.slave_id != 0)
++ control_block->info |=
++ BCM2835_DMA_PER_MAP(c->cfg.slave_id);
++
++ /* Length of a frame */
++ if (frame != d->frames-1)
++ control_block->length = period_len;
++ else
++ control_block->length = buf_len - (d->frames - 1) * period_len;
++
++ d->size += control_block->length;
++
++ /*
++ * Next block is the next frame.
++ * This function is called on cyclic DMA transfers.
++ * Therefore, wrap around at number of frames.
++ */
++ control_block->next = d->control_block_base_phys +
++ sizeof(struct bcm2835_dma_cb)
++ * ((frame + 1) % d->frames);
++ }
++
++ c->cyclic = true;
++
++ return vchan_tx_prep(&c->vc, &d->vd, flags);
++}
++
++
++static struct dma_async_tx_descriptor *bcm2835_dma_prep_slave_sg(
++ struct dma_chan *chan, struct scatterlist *sgl,
++ unsigned int sg_len, enum dma_transfer_direction direction,
++ unsigned long flags, void *context)
++{
++ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
++ enum dma_slave_buswidth dev_width;
++ struct bcm2835_desc *d;
++ dma_addr_t dev_addr;
++ struct scatterlist *sgent;
++ unsigned int es, sync_type;
++ unsigned int i, j, splitct, max_size;
++
++ if (!is_slave_direction(direction)) {
++ dev_err(chan->device->dev, "%s: bad direction?\n", __func__);
++ return NULL;
++ }
++
++ if (direction == DMA_DEV_TO_MEM) {
++ dev_addr = c->cfg.src_addr;
++ dev_width = c->cfg.src_addr_width;
++ sync_type = BCM2835_DMA_S_DREQ;
++ } else {
++ dev_addr = c->cfg.dst_addr;
++ dev_width = c->cfg.dst_addr_width;
++ sync_type = BCM2835_DMA_D_DREQ;
++ }
++
++ /* Bus width translates to the element size (ES) */
++ switch (dev_width) {
++ case DMA_SLAVE_BUSWIDTH_4_BYTES:
++ es = BCM2835_DMA_DATA_TYPE_S32;
++ break;
++ default:
++ return NULL;
++ }
++
++ /* Now allocate and setup the descriptor. */
++ d = kzalloc(sizeof(*d), GFP_NOWAIT);
++ if (!d)
++ return NULL;
++
++ d->dir = direction;
++
++ if (c->ch >= 8) /* we have a LITE channel */
++ max_size = MAX_LITE_TRANSFER;
++ else
++ max_size = MAX_NORMAL_TRANSFER;
++
++ /* We store the length of the SG list in d->frames
++ taking care to account for splitting up transfers
++ too large for a LITE channel */
++
++ d->frames = 0;
++ for_each_sg(sgl, sgent, sg_len, i) {
++ uint32_t len = sg_dma_len(sgent);
++ d->frames += 1 + len / max_size;
++ }
++
++ /* Allocate memory for control blocks */
++ d->control_block_size = d->frames * sizeof(struct bcm2835_dma_cb);
++ d->control_block_base = dma_zalloc_coherent(chan->device->dev,
++ d->control_block_size, &d->control_block_base_phys,
++ GFP_NOWAIT);
++
++ if (!d->control_block_base) {
++ kfree(d);
++ return NULL;
++ }
++
++ /*
++ * Iterate over all SG entries, create a control block
++ * for each frame and link them together.
++ */
++
++ /* we count the number of times an SG entry had to be splitct
++ as a result of using a LITE channel */
++ splitct = 0;
++
++ for_each_sg(sgl, sgent, sg_len, i) {
++ dma_addr_t addr = sg_dma_address(sgent);
++ uint32_t len = sg_dma_len(sgent);
++
++ for (j = 0; j < len; j += max_size) {
++ struct bcm2835_dma_cb *control_block =
++ &d->control_block_base[i+splitct];
++
++ /* Setup adresses */
++ if (d->dir == DMA_DEV_TO_MEM) {
++ control_block->info = BCM2835_DMA_D_INC |
++ BCM2835_DMA_D_WIDTH | BCM2835_DMA_S_DREQ;
++ control_block->src = dev_addr;
++ control_block->dst = addr + (dma_addr_t)j;
++ } else {
++ control_block->info = BCM2835_DMA_S_INC |
++ BCM2835_DMA_S_WIDTH | BCM2835_DMA_D_DREQ;
++ control_block->src = addr + (dma_addr_t)j;
++ control_block->dst = dev_addr;
++ }
++
++ /* Common part */
++ u32 waits = SDHCI_BCM_DMA_WAITS;
++ if ((dma_debug >> 0) & 0x1f)
++ waits = (dma_debug >> 0) & 0x1f;
++ control_block->info |= BCM2835_DMA_WAITS(waits);
++ control_block->info |= BCM2835_DMA_WAIT_RESP;
++
++ /* Enable */
++ if (i == sg_len-1 && len-j <= max_size)
++ control_block->info |= BCM2835_DMA_INT_EN;
++
++ /* Setup synchronization */
++ if (sync_type != 0)
++ control_block->info |= sync_type;
++
++ /* Setup DREQ channel */
++ if (c->dreq != 0)
++ control_block->info |=
++ BCM2835_DMA_PER_MAP(c->dreq);
++
++ /* Length of a frame */
++ control_block->length = min(len-j, max_size);
++ d->size += control_block->length;
++
++ /*
++ * Next block is the next frame.
++ */
++ if (i < sg_len-1 || len-j > max_size) {
++ /* next block is the next frame. */
++ control_block->next = d->control_block_base_phys +
++ sizeof(struct bcm2835_dma_cb) * (i + splitct + 1);
++ } else {
++ /* next block is empty. */
++ control_block->next = 0;
++ }
++
++ if (len-j > max_size)
++ splitct++;
++ }
++ }
++
++ c->cyclic = false;
++
++ return vchan_tx_prep(&c->vc, &d->vd, flags);
++}
++
++static int bcm2835_dma_slave_config(struct dma_chan *chan,
++ struct dma_slave_config *cfg)
++{
++ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
++ if ((cfg->direction == DMA_DEV_TO_MEM &&
++ cfg->src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) ||
++ (cfg->direction == DMA_MEM_TO_DEV &&
++ cfg->dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) ||
++ !is_slave_direction(cfg->direction)) {
++ return -EINVAL;
++ }
++
++ c->cfg = *cfg;
++ if (!c->dreq)
++ c->dreq = cfg->slave_id;
++
++ return 0;
++}
++
++static int bcm2835_dma_terminate_all(struct dma_chan *chan)
++{
++ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
++ struct bcm2835_dmadev *d = to_bcm2835_dma_dev(c->vc.chan.device);
++ unsigned long flags;
++ int timeout = 10000;
++ LIST_HEAD(head);
++
++ spin_lock_irqsave(&c->vc.lock, flags);
++
++ /* Prevent this channel being scheduled */
++ spin_lock(&d->lock);
++ list_del_init(&c->node);
++ spin_unlock(&d->lock);
++
++ /*
++ * Stop DMA activity: we assume the callback will not be called
++ * after bcm_dma_abort() returns (even if it does, it will see
++ * c->desc is NULL and exit.)
++ */
++ if (c->desc) {
++ bcm2835_dma_desc_free(&c->desc->vd);
++ c->desc = NULL;
++ bcm2835_dma_abort(c->chan_base);
++
++ /* Wait for stopping */
++ while (--timeout) {
++ if (!(readl(c->chan_base + BCM2835_DMA_CS) &
++ BCM2835_DMA_ACTIVE))
++ break;
++
++ cpu_relax();
++ }
++
++ if (!timeout)
++ dev_err(d->ddev.dev, "DMA transfer could not be terminated\n");
++ }
++
++ vchan_get_all_descriptors(&c->vc, &head);
++ spin_unlock_irqrestore(&c->vc.lock, flags);
++ vchan_dma_desc_free_list(&c->vc, &head);
++
++ return 0;
++}
++
++#ifndef CONFIG_DMA_BCM2708_LEGACY
++static int bcm2835_dma_chan_init(struct bcm2835_dmadev *d, int chan_id, int irq)
++{
++ struct bcm2835_chan *c;
++
++ c = devm_kzalloc(d->ddev.dev, sizeof(*c), GFP_KERNEL);
++ if (!c)
++ return -ENOMEM;
++
++ c->vc.desc_free = bcm2835_dma_desc_free;
++ vchan_init(&c->vc, &d->ddev);
++ INIT_LIST_HEAD(&c->node);
++
++ c->chan_base = BCM2835_DMA_CHANIO(d->base, chan_id);
++ c->ch = chan_id;
++ c->irq_number = irq;
++
++ return 0;
++}
++#endif
++
++static int bcm2708_dma_chan_init(struct bcm2835_dmadev *d,
++ void __iomem *chan_base, int chan_id, int irq)
++{
++ struct bcm2835_chan *c;
++
++ c = devm_kzalloc(d->ddev.dev, sizeof(*c), GFP_KERNEL);
++ if (!c)
++ return -ENOMEM;
++
++ c->vc.desc_free = bcm2835_dma_desc_free;
++ vchan_init(&c->vc, &d->ddev);
++ INIT_LIST_HEAD(&c->node);
++
++ c->chan_base = chan_base;
++ c->ch = chan_id;
++ c->irq_number = irq;
++
++ return 0;
++}
++
++
++static void bcm2835_dma_free(struct bcm2835_dmadev *od)
++{
++ struct bcm2835_chan *c, *next;
++
++ list_for_each_entry_safe(c, next, &od->ddev.channels,
++ vc.chan.device_node) {
++ list_del(&c->vc.chan.device_node);
++ tasklet_kill(&c->vc.task);
++ }
++}
++
++static const struct of_device_id bcm2835_dma_of_match[] = {
++ { .compatible = "brcm,bcm2835-dma", },
++ {},
++};
++MODULE_DEVICE_TABLE(of, bcm2835_dma_of_match);
++
++static struct dma_chan *bcm2835_dma_xlate(struct of_phandle_args *spec,
++ struct of_dma *ofdma)
++{
++ struct bcm2835_dmadev *d = ofdma->of_dma_data;
++ struct dma_chan *chan;
++
++ chan = dma_get_any_slave_channel(&d->ddev);
++ if (!chan)
++ return NULL;
++
++ /* Set DREQ from param */
++ to_bcm2835_dma_chan(chan)->dreq = spec->args[0];
++
++ return chan;
++}
++
++static int bcm2835_dma_probe(struct platform_device *pdev)
++{
++ struct bcm2835_dmadev *od;
++#ifndef CONFIG_DMA_BCM2708_LEGACY
++ struct resource *res;
++ void __iomem *base;
++ uint32_t chans_available;
++#endif
++ int rc;
++ int i;
++ int irq;
++
++
++ if (!pdev->dev.dma_mask)
++ pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
++
++#ifdef CONFIG_DMA_BCM2708_LEGACY
++
++ rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
++ if (rc)
++ return rc;
++ dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
++
++
++ od = devm_kzalloc(&pdev->dev, sizeof(*od), GFP_KERNEL);
++ if (!od)
++ return -ENOMEM;
++
++ rc = bcm_dmaman_probe(pdev);
++ if (rc)
++ return rc;
++
++ pdev->dev.dma_parms = &od->dma_parms;
++ dma_set_max_seg_size(&pdev->dev, 0x3FFFFFFF);
++
++
++ dma_cap_set(DMA_SLAVE, od->ddev.cap_mask);
++ dma_cap_set(DMA_PRIVATE, od->ddev.cap_mask);
++ dma_cap_set(DMA_CYCLIC, od->ddev.cap_mask);
++ od->ddev.device_alloc_chan_resources = bcm2835_dma_alloc_chan_resources;
++ od->ddev.device_free_chan_resources = bcm2835_dma_free_chan_resources;
++ od->ddev.device_tx_status = bcm2835_dma_tx_status;
++ od->ddev.device_issue_pending = bcm2835_dma_issue_pending;
++ od->ddev.device_prep_dma_cyclic = bcm2835_dma_prep_dma_cyclic;
++ od->ddev.device_prep_slave_sg = bcm2835_dma_prep_slave_sg;
++ od->ddev.device_terminate_all = bcm2835_dma_terminate_all;
++ od->ddev.device_config = bcm2835_dma_slave_config;
++ od->ddev.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
++ od->ddev.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
++ od->ddev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
++ od->ddev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
++ od->ddev.dev = &pdev->dev;
++ INIT_LIST_HEAD(&od->ddev.channels);
++ spin_lock_init(&od->lock);
++
++ platform_set_drvdata(pdev, od);
++
++ for (i = 0; i < 5; i++) {
++ void __iomem *chan_base;
++ int chan_id;
++
++ chan_id = bcm_dma_chan_alloc(BCM_DMA_FEATURE_LITE,
++ &chan_base,
++ &irq);
++
++ if (chan_id < 0)
++ break;
++
++ rc = bcm2708_dma_chan_init(od, chan_base, chan_id, irq);
++ if (rc)
++ goto err_no_dma;
++ }
++
++ if (pdev->dev.of_node) {
++ rc = of_dma_controller_register(pdev->dev.of_node,
++ bcm2835_dma_xlate, od);
++ if (rc) {
++ dev_err(&pdev->dev,
++ "Failed to register DMA controller\n");
++ goto err_no_dma;
++ }
++ }
++
++#else
++ rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
++ if (rc)
++ return rc;
++
++
++ od = devm_kzalloc(&pdev->dev, sizeof(*od), GFP_KERNEL);
++ if (!od)
++ return -ENOMEM;
++
++ pdev->dev.dma_parms = &od->dma_parms;
++ dma_set_max_seg_size(&pdev->dev, 0x3FFFFFFF);
++
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ base = devm_ioremap_resource(&pdev->dev, res);
++ if (IS_ERR(base))
++ return PTR_ERR(base);
++
++ od->base = base;
++
++
++ dma_cap_set(DMA_SLAVE, od->ddev.cap_mask);
++ dma_cap_set(DMA_PRIVATE, od->ddev.cap_mask);
++ dma_cap_set(DMA_CYCLIC, od->ddev.cap_mask);
++ od->ddev.device_alloc_chan_resources = bcm2835_dma_alloc_chan_resources;
++ od->ddev.device_free_chan_resources = bcm2835_dma_free_chan_resources;
++ od->ddev.device_tx_status = bcm2835_dma_tx_status;
++ od->ddev.device_issue_pending = bcm2835_dma_issue_pending;
++ od->ddev.device_prep_dma_cyclic = bcm2835_dma_prep_dma_cyclic;
++ od->ddev.device_prep_slave_sg = bcm2835_dma_prep_slave_sg;
++ od->ddev.device_terminate_all = bcm2835_dma_terminate_all;
++ od->ddev.device_config = bcm2835_dma_slave_config;
++ od->ddev.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
++ od->ddev.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
++ od->ddev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
++ od->ddev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
++ od->ddev.dev = &pdev->dev;
++ INIT_LIST_HEAD(&od->ddev.channels);
++ spin_lock_init(&od->lock);
++
++ platform_set_drvdata(pdev, od);
++
++
++ /* Request DMA channel mask from device tree */
++ if (of_property_read_u32(pdev->dev.of_node,
++ "brcm,dma-channel-mask",
++ &chans_available)) {
++ dev_err(&pdev->dev, "Failed to get channel mask\n");
++ rc = -EINVAL;
++ goto err_no_dma;
++ }
++
++
++ /*
++ * Do not use the FIQ and BULK channels,
++ * because they are used by the GPU.
++ */
++ chans_available &= ~(BCM2835_DMA_FIQ_MASK | BCM2835_DMA_BULK_MASK);
++
++
++ for (i = 0; i < pdev->num_resources; i++) {
++ irq = platform_get_irq(pdev, i);
++ if (irq < 0)
++ break;
++
++ if (chans_available & (1 << i)) {
++ rc = bcm2835_dma_chan_init(od, i, irq);
++ if (rc)
++ goto err_no_dma;
++ }
++ }
++
++ dev_dbg(&pdev->dev, "Initialized %i DMA channels\n", i);
++
++ /* Device-tree DMA controller registration */
++ rc = of_dma_controller_register(pdev->dev.of_node,
++ bcm2835_dma_xlate, od);
++ if (rc) {
++ dev_err(&pdev->dev, "Failed to register DMA controller\n");
++ goto err_no_dma;
++ }
++#endif
++
++ rc = dma_async_device_register(&od->ddev);
++ if (rc) {
++ dev_err(&pdev->dev,
++ "Failed to register slave DMA engine device: %d\n", rc);
++ goto err_no_dma;
++ }
++
++ dev_info(&pdev->dev, "Load BCM2835 DMA engine driver\n");
++ dev_info(&pdev->dev, "dma_debug:%x\n", dma_debug);
++
++ return 0;
++
++err_no_dma:
++ bcm2835_dma_free(od);
++ return rc;
++}
++
++static int bcm2835_dma_remove(struct platform_device *pdev)
++{
++ struct bcm2835_dmadev *od = platform_get_drvdata(pdev);
++
++ dma_async_device_unregister(&od->ddev);
++ bcm2835_dma_free(od);
++ bcm_dmaman_remove(pdev);
++
++ return 0;
++}
++
++static struct platform_driver bcm2835_dma_driver = {
++ .probe = bcm2835_dma_probe,
++ .remove = bcm2835_dma_remove,
++ .driver = {
++ .name = "bcm2708-dmaengine",
++ .owner = THIS_MODULE,
++ .of_match_table = of_match_ptr(bcm2835_dma_of_match),
++ },
++};
++
++static int bcm2835_init(void)
++{
++ return platform_driver_register(&bcm2835_dma_driver);
++}
++
++static void bcm2835_exit(void)
++{
++ platform_driver_unregister(&bcm2835_dma_driver);
++}
++
++/*
++ * Load after serial driver (arch_initcall) so we see the messages if it fails,
++ * but before drivers (module_init) that need a DMA channel.
++ */
++subsys_initcall(bcm2835_init);
++module_exit(bcm2835_exit);
++
++module_param(dma_debug, uint, 0644);
++#ifdef CONFIG_DMA_BCM2708_LEGACY
++/* Keep backward compatibility: dma.dmachans= */
++#undef MODULE_PARAM_PREFIX
++#define MODULE_PARAM_PREFIX "dma."
++module_param(dmachans, int, 0644);
++#endif
++MODULE_ALIAS("platform:bcm2835-dma");
++MODULE_DESCRIPTION("BCM2835 DMA engine driver");
++MODULE_AUTHOR("Florian Meier <florian.meier@koalo.de>");
++MODULE_AUTHOR("Gellert Weisz <gellert@raspberrypi.org>");
++MODULE_LICENSE("GPL v2");
+diff -Nur linux-4.1.3/drivers/dma/Kconfig linux-xbian-rpi/drivers/dma/Kconfig
+--- linux-4.1.3/drivers/dma/Kconfig 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/dma/Kconfig 2015-07-28 01:20:58.194052384 +0200
+@@ -337,6 +337,17 @@
+ select DMA_ENGINE
+ select DMA_VIRTUAL_CHANNELS
+
++config DMA_BCM2708
++ tristate "BCM2708 DMA engine support"
++ depends on MACH_BCM2708 || MACH_BCM2709 || ARCH_BCM2835
++ select DMA_ENGINE
++ select DMA_VIRTUAL_CHANNELS
++
++config DMA_BCM2708_LEGACY
++ bool "BCM2708 DMA legacy API support"
++ depends on DMA_BCM2708
++ default y
++
+ config TI_CPPI41
+ tristate "AM33xx CPPI41 DMA support"
+ depends on ARCH_OMAP
+@@ -385,7 +396,7 @@
+ select DMA_VIRTUAL_CHANNELS
+ help
+ Enable support for the MOXA ART SoC DMA controller.
+-
++
+ config FSL_EDMA
+ tristate "Freescale eDMA engine support"
+ depends on OF
+diff -Nur linux-4.1.3/drivers/dma/Makefile linux-xbian-rpi/drivers/dma/Makefile
+--- linux-4.1.3/drivers/dma/Makefile 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/dma/Makefile 2015-07-28 01:20:58.194052384 +0200
+@@ -39,6 +39,7 @@
+ obj-$(CONFIG_MMP_TDMA) += mmp_tdma.o
+ obj-$(CONFIG_DMA_OMAP) += omap-dma.o
+ obj-$(CONFIG_DMA_BCM2835) += bcm2835-dma.o
++obj-$(CONFIG_DMA_BCM2708) += bcm2708-dmaengine.o
+ obj-$(CONFIG_MMP_PDMA) += mmp_pdma.o
+ obj-$(CONFIG_DMA_JZ4740) += dma-jz4740.o
+ obj-$(CONFIG_DMA_JZ4780) += dma-jz4780.o
+diff -Nur linux-4.1.3/drivers/firmware/Kconfig linux-xbian-rpi/drivers/firmware/Kconfig
+--- linux-4.1.3/drivers/firmware/Kconfig 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/firmware/Kconfig 2015-07-28 01:20:58.194052384 +0200
+@@ -136,6 +136,13 @@
+ bool
+ depends on ARM || ARM64
+
++config RASPBERRYPI_FIRMWARE
++ tristate "Raspberry Pi Firmware Driver"
++ depends on BCM2835_MBOX
++ help
++ This option enables support for communicating with the firmware on the
++ Raspberry Pi.
++
+ source "drivers/firmware/google/Kconfig"
+ source "drivers/firmware/efi/Kconfig"
+
+diff -Nur linux-4.1.3/drivers/firmware/Makefile linux-xbian-rpi/drivers/firmware/Makefile
+--- linux-4.1.3/drivers/firmware/Makefile 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/firmware/Makefile 2015-07-28 01:20:58.194052384 +0200
+@@ -13,6 +13,7 @@
+ obj-$(CONFIG_FIRMWARE_MEMMAP) += memmap.o
+ obj-$(CONFIG_QCOM_SCM) += qcom_scm.o
+ CFLAGS_qcom_scm.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1)
++obj-$(CONFIG_RASPBERRYPI_FIRMWARE) += raspberrypi.o
+
+ obj-$(CONFIG_GOOGLE_FIRMWARE) += google/
+ obj-$(CONFIG_EFI) += efi/
+diff -Nur linux-4.1.3/drivers/firmware/raspberrypi.c linux-xbian-rpi/drivers/firmware/raspberrypi.c
+--- linux-4.1.3/drivers/firmware/raspberrypi.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/firmware/raspberrypi.c 2015-07-28 01:20:58.194052384 +0200
+@@ -0,0 +1,308 @@
++/*
++ * Defines interfaces for interacting wtih the Raspberry Pi firmware's
++ * property channel.
++ *
++ * Copyright © 2015 Broadcom
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/dma-mapping.h>
++#include <linux/mailbox_client.h>
++#include <linux/module.h>
++#include <linux/of_platform.h>
++#include <linux/platform_device.h>
++#include <soc/bcm2835/raspberrypi-firmware.h>
++
++#define MBOX_MSG(chan, data28) (((data28) & ~0xf) | ((chan) & 0xf))
++#define MBOX_CHAN(msg) ((msg) & 0xf)
++#define MBOX_DATA28(msg) ((msg) & ~0xf)
++#define MBOX_CHAN_VCHIQ 3
++#define MBOX_CHAN_PROPERTY 8
++
++struct rpi_firmware {
++ struct mbox_client cl;
++ struct mbox_chan *chan; /* The property channel. */
++ struct completion c;
++ u32 enabled;
++ u32 received;
++};
++
++static struct platform_device *g_pdev;
++
++static DEFINE_MUTEX(transaction_lock);
++
++static void response_callback(struct mbox_client *cl, void *msg)
++{
++ struct rpi_firmware *fw = container_of(cl, struct rpi_firmware, cl);
++ fw->received = *(u32 *)msg;
++ complete(&fw->c);
++}
++
++/*
++ * Sends a request to the firmware through the BCM2835 mailbox driver,
++ * and synchronously waits for the reply.
++ */
++int
++rpi_firmware_transaction(struct rpi_firmware *fw, u32 chan, u32 data)
++{
++ u32 message = MBOX_MSG(chan, data);
++ int ret;
++
++ WARN_ON(data & 0xf);
++
++ mutex_lock(&transaction_lock);
++ reinit_completion(&fw->c);
++ ret = mbox_send_message(fw->chan, &message);
++ if (ret >= 0) {
++ if (chan != MBOX_CHAN_VCHIQ)
++ wait_for_completion(&fw->c);
++ ret = 0;
++ } else {
++ dev_err(fw->cl.dev, "mbox_send_message returned %d\n", ret);
++ }
++ mutex_unlock(&transaction_lock);
++
++ return ret;
++}
++EXPORT_SYMBOL(rpi_firmware_transaction);
++
++u32 rpi_firmware_transaction_received(struct rpi_firmware *fw)
++{
++ return MBOX_DATA28(fw->received);
++}
++EXPORT_SYMBOL(rpi_firmware_transaction_received);
++
++/**
++ * rpi_firmware_property_list - Submit firmware property list
++ * @fw: Pointer to firmware structure from rpi_firmware_get().
++ * @data: Buffer holding tags.
++ * @tag_size: Size of tags buffer.
++ *
++ * Submits a set of concatenated tags to the VPU firmware through the
++ * mailbox property interface.
++ *
++ * The buffer header and the ending tag are added by this function and
++ * don't need to be supplied, just the actual tags for your operation.
++ * See struct rpi_firmware_property_tag_header for the per-tag
++ * structure.
++ */
++int rpi_firmware_property_list(struct rpi_firmware *fw,
++ void *data, size_t tag_size)
++{
++ size_t size = tag_size + 12;
++ u32 *buf;
++ dma_addr_t bus_addr;
++ int ret;
++
++ /* Packets are processed a dword at a time. */
++ if (size & 3)
++ return -EINVAL;
++
++ buf = dma_alloc_coherent(fw->cl.dev, PAGE_ALIGN(size), &bus_addr,
++ GFP_ATOMIC);
++ if (!buf)
++ return -ENOMEM;
++
++ /* The firmware will error out without parsing in this case. */
++ WARN_ON(size >= 1024 * 1024);
++
++ buf[0] = size;
++ buf[1] = RPI_FIRMWARE_STATUS_REQUEST;
++ memcpy(&buf[2], data, tag_size);
++ buf[size / 4 - 1] = RPI_FIRMWARE_PROPERTY_END;
++ wmb();
++
++ ret = rpi_firmware_transaction(fw, MBOX_CHAN_PROPERTY, bus_addr);
++
++ rmb();
++ memcpy(data, &buf[2], tag_size);
++ if (ret == 0 && buf[1] != RPI_FIRMWARE_STATUS_SUCCESS) {
++ /*
++ * The tag name here might not be the one causing the
++ * error, if there were multiple tags in the request.
++ * But single-tag is the most common, so go with it.
++ */
++ dev_err(fw->cl.dev, "Request 0x%08x returned status 0x%08x\n",
++ buf[2], buf[1]);
++ ret = -EINVAL;
++ }
++
++ dma_free_coherent(fw->cl.dev, PAGE_ALIGN(size), buf, bus_addr);
++
++ return ret;
++}
++EXPORT_SYMBOL_GPL(rpi_firmware_property_list);
++
++/**
++ * rpi_firmware_property - Submit single firmware property
++ * @fw: Pointer to firmware structure from rpi_firmware_get().
++ * @tag: One of enum_mbox_property_tag.
++ * @tag_data: Tag data buffer.
++ * @buf_size: Buffer size.
++ *
++ * Submits a single tag to the VPU firmware through the mailbox
++ * property interface.
++ *
++ * This is a convenience wrapper around
++ * rpi_firmware_property_list() to avoid some of the
++ * boilerplate in property calls.
++ */
++int rpi_firmware_property(struct rpi_firmware *fw,
++ u32 tag, void *tag_data, size_t buf_size)
++{
++ /* Single tags are very small (generally 8 bytes), so the
++ * stack should be safe.
++ */
++ u8 data[buf_size + sizeof(struct rpi_firmware_property_tag_header)];
++ struct rpi_firmware_property_tag_header *header =
++ (struct rpi_firmware_property_tag_header *)data;
++ int ret;
++
++ header->tag = tag;
++ header->buf_size = buf_size;
++ header->req_resp_size = 0;
++ memcpy(data + sizeof(struct rpi_firmware_property_tag_header),
++ tag_data, buf_size);
++
++ ret = rpi_firmware_property_list(fw, &data, sizeof(data));
++ memcpy(tag_data,
++ data + sizeof(struct rpi_firmware_property_tag_header),
++ buf_size);
++
++ return ret;
++}
++EXPORT_SYMBOL_GPL(rpi_firmware_property);
++
++static void
++rpi_firmware_print_firmware_revision(struct rpi_firmware *fw)
++{
++ u32 packet;
++ int ret = rpi_firmware_property(fw,
++ RPI_FIRMWARE_GET_FIRMWARE_REVISION,
++ &packet, sizeof(packet));
++
++ if (ret == 0) {
++ struct tm tm;
++
++ time_to_tm(packet, 0, &tm);
++
++ dev_info(fw->cl.dev,
++ "Attached to firmware from %04ld-%02d-%02d %02d:%02d\n",
++ tm.tm_year + 1900, tm.tm_mon + 1, tm.tm_mday,
++ tm.tm_hour, tm.tm_min);
++ }
++}
++
++static int raspberrypi_firmware_set_power(struct rpi_firmware *fw,
++ u32 domain, bool on)
++{
++ struct {
++ u32 domain;
++ u32 on;
++ } packet;
++ int ret;
++
++ packet.domain = domain;
++ packet.on = on;
++ ret = rpi_firmware_property(fw, RPI_FIRMWARE_SET_POWER_STATE,
++ &packet, sizeof(packet));
++ if (!ret && packet.on != on)
++ ret = -EINVAL;
++
++ return ret;
++}
++
++static int rpi_firmware_probe(struct platform_device *pdev)
++{
++ struct device *dev = &pdev->dev;
++ struct rpi_firmware *fw;
++
++ fw = devm_kzalloc(dev, sizeof(*fw), GFP_KERNEL);
++ if (!fw)
++ return -ENOMEM;
++
++ fw->cl.dev = dev;
++ fw->cl.rx_callback = response_callback;
++ fw->cl.tx_block = true;
++
++ fw->chan = mbox_request_channel(&fw->cl, 0);
++ if (IS_ERR(fw->chan)) {
++ int ret = PTR_ERR(fw->chan);
++ if (ret != -EPROBE_DEFER)
++ dev_err(dev, "Failed to get mbox channel: %d\n", ret);
++ return ret;
++ }
++
++ init_completion(&fw->c);
++
++ platform_set_drvdata(pdev, fw);
++ g_pdev = pdev;
++
++ rpi_firmware_print_firmware_revision(fw);
++
++ if (raspberrypi_firmware_set_power(fw, 3, true))
++ dev_err(dev, "failed to turn on USB power\n");
++
++ return 0;
++}
++
++static int rpi_firmware_remove(struct platform_device *pdev)
++{
++ struct rpi_firmware *fw = platform_get_drvdata(pdev);
++
++ mbox_free_channel(fw->chan);
++ g_pdev = NULL;
++
++ return 0;
++}
++
++/**
++ * rpi_firmware_get - Get pointer to rpi_firmware structure.
++ * @firmware_node: Pointer to the firmware Device Tree node.
++ *
++ * Returns NULL is the firmware device is not ready.
++ */
++struct rpi_firmware *rpi_firmware_get(struct device_node *firmware_node)
++{
++ struct platform_device *pdev = g_pdev;
++
++ if (!pdev)
++ return NULL;
++
++ return platform_get_drvdata(pdev);
++}
++EXPORT_SYMBOL_GPL(rpi_firmware_get);
++
++static const struct of_device_id rpi_firmware_of_match[] = {
++ { .compatible = "raspberrypi,bcm2835-firmware", },
++ {},
++};
++MODULE_DEVICE_TABLE(of, rpi_firmware_of_match);
++
++static struct platform_driver rpi_firmware_driver = {
++ .driver = {
++ .name = "raspberrypi-firmware",
++ .of_match_table = rpi_firmware_of_match,
++ },
++ .probe = rpi_firmware_probe,
++ .remove = rpi_firmware_remove,
++};
++
++static int __init rpi_firmware_init(void)
++{
++ return platform_driver_register(&rpi_firmware_driver);
++}
++subsys_initcall(rpi_firmware_init);
++
++static void __init rpi_firmware_exit(void)
++{
++ platform_driver_unregister(&rpi_firmware_driver);
++}
++module_exit(rpi_firmware_exit);
++
++MODULE_AUTHOR("Eric Anholt <eric@anholt.net>");
++MODULE_DESCRIPTION("Raspberry Pi firmware driver");
++MODULE_LICENSE("GPL v2");
+diff -Nur linux-4.1.3/drivers/hid/usbhid/hid-core.c linux-xbian-rpi/drivers/hid/usbhid/hid-core.c
+--- linux-4.1.3/drivers/hid/usbhid/hid-core.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/hid/usbhid/hid-core.c 2015-07-28 01:20:58.194052384 +0200
+@@ -49,7 +49,7 @@
+ * Module parameters.
+ */
+
+-static unsigned int hid_mousepoll_interval;
++static unsigned int hid_mousepoll_interval = ~0;
+ module_param_named(mousepoll, hid_mousepoll_interval, uint, 0644);
+ MODULE_PARM_DESC(mousepoll, "Polling interval of mice");
+
+@@ -1090,8 +1090,12 @@
+ }
+
+ /* Change the polling interval of mice. */
+- if (hid->collection->usage == HID_GD_MOUSE && hid_mousepoll_interval > 0)
+- interval = hid_mousepoll_interval;
++ if (hid->collection->usage == HID_GD_MOUSE) {
++ if (hid_mousepoll_interval == ~0 && interval < 16)
++ interval = 16;
++ else if (hid_mousepoll_interval != ~0 && hid_mousepoll_interval != 0)
++ interval = hid_mousepoll_interval;
++ }
+
+ ret = -ENOMEM;
+ if (usb_endpoint_dir_in(endpoint)) {
+diff -Nur linux-4.1.3/drivers/i2c/busses/i2c-bcm2708.c linux-xbian-rpi/drivers/i2c/busses/i2c-bcm2708.c
+--- linux-4.1.3/drivers/i2c/busses/i2c-bcm2708.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/i2c/busses/i2c-bcm2708.c 2015-07-28 01:20:58.198038163 +0200
+@@ -0,0 +1,524 @@
++/*
++ * Driver for Broadcom BCM2708 BSC Controllers
++ *
++ * Copyright (C) 2012 Chris Boot & Frank Buss
++ *
++ * This driver is inspired by:
++ * i2c-ocores.c, by Peter Korsgaard <jacmet@sunsite.dk>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/spinlock.h>
++#include <linux/clk.h>
++#include <linux/err.h>
++#include <linux/of.h>
++#include <linux/platform_device.h>
++#include <linux/io.h>
++#include <linux/slab.h>
++#include <linux/i2c.h>
++#include <linux/interrupt.h>
++#include <linux/sched.h>
++#include <linux/wait.h>
++
++/* BSC register offsets */
++#define BSC_C 0x00
++#define BSC_S 0x04
++#define BSC_DLEN 0x08
++#define BSC_A 0x0c
++#define BSC_FIFO 0x10
++#define BSC_DIV 0x14
++#define BSC_DEL 0x18
++#define BSC_CLKT 0x1c
++
++/* Bitfields in BSC_C */
++#define BSC_C_I2CEN 0x00008000
++#define BSC_C_INTR 0x00000400
++#define BSC_C_INTT 0x00000200
++#define BSC_C_INTD 0x00000100
++#define BSC_C_ST 0x00000080
++#define BSC_C_CLEAR_1 0x00000020
++#define BSC_C_CLEAR_2 0x00000010
++#define BSC_C_READ 0x00000001
++
++/* Bitfields in BSC_S */
++#define BSC_S_CLKT 0x00000200
++#define BSC_S_ERR 0x00000100
++#define BSC_S_RXF 0x00000080
++#define BSC_S_TXE 0x00000040
++#define BSC_S_RXD 0x00000020
++#define BSC_S_TXD 0x00000010
++#define BSC_S_RXR 0x00000008
++#define BSC_S_TXW 0x00000004
++#define BSC_S_DONE 0x00000002
++#define BSC_S_TA 0x00000001
++
++#define I2C_WAIT_LOOP_COUNT 200
++
++#define DRV_NAME "bcm2708_i2c"
++
++static unsigned int baudrate = CONFIG_I2C_BCM2708_BAUDRATE;
++module_param(baudrate, uint, S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP);
++MODULE_PARM_DESC(baudrate, "The I2C baudrate");
++
++static bool combined = false;
++module_param(combined, bool, 0644);
++MODULE_PARM_DESC(combined, "Use combined transactions");
++
++struct bcm2708_i2c {
++ struct i2c_adapter adapter;
++
++ spinlock_t lock;
++ void __iomem *base;
++ int irq;
++ struct clk *clk;
++ u32 cdiv;
++
++ struct completion done;
++
++ struct i2c_msg *msg;
++ int pos;
++ int nmsgs;
++ bool error;
++};
++
++/*
++ * This function sets the ALT mode on the I2C pins so that we can use them with
++ * the BSC hardware.
++ *
++ * FIXME: This is a hack. Use pinmux / pinctrl.
++ */
++static void bcm2708_i2c_init_pinmode(int id)
++{
++#define INP_GPIO(g) *(gpio+((g)/10)) &= ~(7<<(((g)%10)*3))
++#define SET_GPIO_ALT(g,a) *(gpio+(((g)/10))) |= (((a)<=3?(a)+4:(a)==4?3:2)<<(((g)%10)*3))
++
++ int pin;
++ u32 *gpio = ioremap(GPIO_BASE, SZ_16K);
++
++ BUG_ON(id != 0 && id != 1);
++ /* BSC0 is on GPIO 0 & 1, BSC1 is on GPIO 2 & 3 */
++ for (pin = id*2+0; pin <= id*2+1; pin++) {
++ printk("bcm2708_i2c_init_pinmode(%d,%d)\n", id, pin);
++ INP_GPIO(pin); /* set mode to GPIO input first */
++ SET_GPIO_ALT(pin, 0); /* set mode to ALT 0 */
++ }
++
++ iounmap(gpio);
++
++#undef INP_GPIO
++#undef SET_GPIO_ALT
++}
++
++static inline u32 bcm2708_rd(struct bcm2708_i2c *bi, unsigned reg)
++{
++ return readl(bi->base + reg);
++}
++
++static inline void bcm2708_wr(struct bcm2708_i2c *bi, unsigned reg, u32 val)
++{
++ writel(val, bi->base + reg);
++}
++
++static inline void bcm2708_bsc_reset(struct bcm2708_i2c *bi)
++{
++ bcm2708_wr(bi, BSC_C, 0);
++ bcm2708_wr(bi, BSC_S, BSC_S_CLKT | BSC_S_ERR | BSC_S_DONE);
++}
++
++static inline void bcm2708_bsc_fifo_drain(struct bcm2708_i2c *bi)
++{
++ while ((bcm2708_rd(bi, BSC_S) & BSC_S_RXD) && (bi->pos < bi->msg->len))
++ bi->msg->buf[bi->pos++] = bcm2708_rd(bi, BSC_FIFO);
++}
++
++static inline void bcm2708_bsc_fifo_fill(struct bcm2708_i2c *bi)
++{
++ while ((bcm2708_rd(bi, BSC_S) & BSC_S_TXD) && (bi->pos < bi->msg->len))
++ bcm2708_wr(bi, BSC_FIFO, bi->msg->buf[bi->pos++]);
++}
++
++static inline int bcm2708_bsc_setup(struct bcm2708_i2c *bi)
++{
++ u32 cdiv, s;
++ u32 c = BSC_C_I2CEN | BSC_C_INTD | BSC_C_ST | BSC_C_CLEAR_1;
++ int wait_loops = I2C_WAIT_LOOP_COUNT;
++
++ /* Can't call clk_get_rate as it locks a mutex and here we are spinlocked.
++ * Use the value that we cached in the probe.
++ */
++ cdiv = bi->cdiv;
++
++ if (bi->msg->flags & I2C_M_RD)
++ c |= BSC_C_INTR | BSC_C_READ;
++ else
++ c |= BSC_C_INTT;
++
++ bcm2708_wr(bi, BSC_DIV, cdiv);
++ bcm2708_wr(bi, BSC_A, bi->msg->addr);
++ bcm2708_wr(bi, BSC_DLEN, bi->msg->len);
++ if (combined)
++ {
++ /* Do the next two messages meet combined transaction criteria?
++ - Current message is a write, next message is a read
++ - Both messages to same slave address
++ - Write message can fit inside FIFO (16 bytes or less) */
++ if ( (bi->nmsgs > 1) &&
++ !(bi->msg[0].flags & I2C_M_RD) && (bi->msg[1].flags & I2C_M_RD) &&
++ (bi->msg[0].addr == bi->msg[1].addr) && (bi->msg[0].len <= 16)) {
++ /* Fill FIFO with entire write message (16 byte FIFO) */
++ while (bi->pos < bi->msg->len) {
++ bcm2708_wr(bi, BSC_FIFO, bi->msg->buf[bi->pos++]);
++ }
++ /* Start write transfer (no interrupts, don't clear FIFO) */
++ bcm2708_wr(bi, BSC_C, BSC_C_I2CEN | BSC_C_ST);
++
++ /* poll for transfer start bit (should only take 1-20 polls) */
++ do {
++ s = bcm2708_rd(bi, BSC_S);
++ } while (!(s & (BSC_S_TA | BSC_S_ERR | BSC_S_CLKT | BSC_S_DONE)) && --wait_loops >= 0);
++
++ /* did we time out or some error occured? */
++ if (wait_loops < 0 || (s & (BSC_S_ERR | BSC_S_CLKT))) {
++ return -1;
++ }
++
++ /* Send next read message before the write transfer finishes. */
++ bi->nmsgs--;
++ bi->msg++;
++ bi->pos = 0;
++ bcm2708_wr(bi, BSC_DLEN, bi->msg->len);
++ c = BSC_C_I2CEN | BSC_C_INTD | BSC_C_INTR | BSC_C_ST | BSC_C_READ;
++ }
++ }
++ bcm2708_wr(bi, BSC_C, c);
++
++ return 0;
++}
++
++static irqreturn_t bcm2708_i2c_interrupt(int irq, void *dev_id)
++{
++ struct bcm2708_i2c *bi = dev_id;
++ bool handled = true;
++ u32 s;
++ int ret;
++
++ spin_lock(&bi->lock);
++
++ /* we may see camera interrupts on the "other" I2C channel
++ Just return if we've not sent anything */
++ if (!bi->nmsgs || !bi->msg) {
++ goto early_exit;
++ }
++
++ s = bcm2708_rd(bi, BSC_S);
++
++ if (s & (BSC_S_CLKT | BSC_S_ERR)) {
++ bcm2708_bsc_reset(bi);
++ bi->error = true;
++
++ bi->msg = 0; /* to inform the that all work is done */
++ bi->nmsgs = 0;
++ /* wake up our bh */
++ complete(&bi->done);
++ } else if (s & BSC_S_DONE) {
++ bi->nmsgs--;
++
++ if (bi->msg->flags & I2C_M_RD) {
++ bcm2708_bsc_fifo_drain(bi);
++ }
++
++ bcm2708_bsc_reset(bi);
++
++ if (bi->nmsgs) {
++ /* advance to next message */
++ bi->msg++;
++ bi->pos = 0;
++ ret = bcm2708_bsc_setup(bi);
++ if (ret < 0) {
++ bcm2708_bsc_reset(bi);
++ bi->error = true;
++ bi->msg = 0; /* to inform the that all work is done */
++ bi->nmsgs = 0;
++ /* wake up our bh */
++ complete(&bi->done);
++ goto early_exit;
++ }
++ } else {
++ bi->msg = 0; /* to inform the that all work is done */
++ bi->nmsgs = 0;
++ /* wake up our bh */
++ complete(&bi->done);
++ }
++ } else if (s & BSC_S_TXW) {
++ bcm2708_bsc_fifo_fill(bi);
++ } else if (s & BSC_S_RXR) {
++ bcm2708_bsc_fifo_drain(bi);
++ } else {
++ handled = false;
++ }
++
++early_exit:
++ spin_unlock(&bi->lock);
++
++ return handled ? IRQ_HANDLED : IRQ_NONE;
++}
++
++static int bcm2708_i2c_master_xfer(struct i2c_adapter *adap,
++ struct i2c_msg *msgs, int num)
++{
++ struct bcm2708_i2c *bi = adap->algo_data;
++ unsigned long flags;
++ int ret;
++
++ spin_lock_irqsave(&bi->lock, flags);
++
++ reinit_completion(&bi->done);
++ bi->msg = msgs;
++ bi->pos = 0;
++ bi->nmsgs = num;
++ bi->error = false;
++
++ ret = bcm2708_bsc_setup(bi);
++
++ spin_unlock_irqrestore(&bi->lock, flags);
++
++ /* check the result of the setup */
++ if (ret < 0)
++ {
++ dev_err(&adap->dev, "transfer setup timed out\n");
++ goto error_timeout;
++ }
++
++ ret = wait_for_completion_timeout(&bi->done, adap->timeout);
++ if (ret == 0) {
++ dev_err(&adap->dev, "transfer timed out\n");
++ goto error_timeout;
++ }
++
++ ret = bi->error ? -EIO : num;
++ return ret;
++
++error_timeout:
++ spin_lock_irqsave(&bi->lock, flags);
++ bcm2708_bsc_reset(bi);
++ bi->msg = 0; /* to inform the interrupt handler that there's nothing else to be done */
++ bi->nmsgs = 0;
++ spin_unlock_irqrestore(&bi->lock, flags);
++ return -ETIMEDOUT;
++}
++
++static u32 bcm2708_i2c_functionality(struct i2c_adapter *adap)
++{
++ return I2C_FUNC_I2C | /*I2C_FUNC_10BIT_ADDR |*/ I2C_FUNC_SMBUS_EMUL;
++}
++
++static struct i2c_algorithm bcm2708_i2c_algorithm = {
++ .master_xfer = bcm2708_i2c_master_xfer,
++ .functionality = bcm2708_i2c_functionality,
++};
++
++static int bcm2708_i2c_probe(struct platform_device *pdev)
++{
++ struct resource *regs;
++ int irq, err = -ENOMEM;
++ struct clk *clk;
++ struct bcm2708_i2c *bi;
++ struct i2c_adapter *adap;
++ unsigned long bus_hz;
++ u32 cdiv;
++
++ if (pdev->dev.of_node) {
++ u32 bus_clk_rate;
++ pdev->id = of_alias_get_id(pdev->dev.of_node, "i2c");
++ if (pdev->id < 0) {
++ dev_err(&pdev->dev, "alias is missing\n");
++ return -EINVAL;
++ }
++ if (!of_property_read_u32(pdev->dev.of_node,
++ "clock-frequency", &bus_clk_rate))
++ baudrate = bus_clk_rate;
++ else
++ dev_warn(&pdev->dev,
++ "Could not read clock-frequency property\n");
++ }
++
++ regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (!regs) {
++ dev_err(&pdev->dev, "could not get IO memory\n");
++ return -ENXIO;
++ }
++
++ irq = platform_get_irq(pdev, 0);
++ if (irq < 0) {
++ dev_err(&pdev->dev, "could not get IRQ\n");
++ return irq;
++ }
++
++ clk = clk_get(&pdev->dev, NULL);
++ if (IS_ERR(clk)) {
++ dev_err(&pdev->dev, "could not find clk: %ld\n", PTR_ERR(clk));
++ return PTR_ERR(clk);
++ }
++
++ err = clk_prepare_enable(clk);
++ if (err) {
++ dev_err(&pdev->dev, "could not enable clk: %d\n", err);
++ goto out_clk_put;
++ }
++
++ if (!pdev->dev.of_node)
++ bcm2708_i2c_init_pinmode(pdev->id);
++
++ bi = kzalloc(sizeof(*bi), GFP_KERNEL);
++ if (!bi)
++ goto out_clk_disable;
++
++ platform_set_drvdata(pdev, bi);
++
++ adap = &bi->adapter;
++ adap->class = I2C_CLASS_HWMON | I2C_CLASS_DDC;
++ adap->algo = &bcm2708_i2c_algorithm;
++ adap->algo_data = bi;
++ adap->dev.parent = &pdev->dev;
++ adap->nr = pdev->id;
++ strlcpy(adap->name, dev_name(&pdev->dev), sizeof(adap->name));
++ adap->dev.of_node = pdev->dev.of_node;
++
++ switch (pdev->id) {
++ case 0:
++ adap->class = I2C_CLASS_HWMON;
++ break;
++ case 1:
++ adap->class = I2C_CLASS_DDC;
++ break;
++ case 2:
++ adap->class = I2C_CLASS_DDC;
++ break;
++ default:
++ dev_err(&pdev->dev, "can only bind to BSC 0, 1 or 2\n");
++ err = -ENXIO;
++ goto out_free_bi;
++ }
++
++ spin_lock_init(&bi->lock);
++ init_completion(&bi->done);
++
++ bi->base = ioremap(regs->start, resource_size(regs));
++ if (!bi->base) {
++ dev_err(&pdev->dev, "could not remap memory\n");
++ goto out_free_bi;
++ }
++
++ bi->irq = irq;
++ bi->clk = clk;
++
++ err = request_irq(irq, bcm2708_i2c_interrupt, IRQF_SHARED,
++ dev_name(&pdev->dev), bi);
++ if (err) {
++ dev_err(&pdev->dev, "could not request IRQ: %d\n", err);
++ goto out_iounmap;
++ }
++
++ bcm2708_bsc_reset(bi);
++
++ err = i2c_add_numbered_adapter(adap);
++ if (err < 0) {
++ dev_err(&pdev->dev, "could not add I2C adapter: %d\n", err);
++ goto out_free_irq;
++ }
++
++ bus_hz = clk_get_rate(bi->clk);
++ cdiv = bus_hz / baudrate;
++ if (cdiv > 0xffff) {
++ cdiv = 0xffff;
++ baudrate = bus_hz / cdiv;
++ }
++ bi->cdiv = cdiv;
++
++ dev_info(&pdev->dev, "BSC%d Controller at 0x%08lx (irq %d) (baudrate %d)\n",
++ pdev->id, (unsigned long)regs->start, irq, baudrate);
++
++ return 0;
++
++out_free_irq:
++ free_irq(bi->irq, bi);
++out_iounmap:
++ iounmap(bi->base);
++out_free_bi:
++ kfree(bi);
++out_clk_disable:
++ clk_disable_unprepare(clk);
++out_clk_put:
++ clk_put(clk);
++ return err;
++}
++
++static int bcm2708_i2c_remove(struct platform_device *pdev)
++{
++ struct bcm2708_i2c *bi = platform_get_drvdata(pdev);
++
++ platform_set_drvdata(pdev, NULL);
++
++ i2c_del_adapter(&bi->adapter);
++ free_irq(bi->irq, bi);
++ iounmap(bi->base);
++ clk_disable_unprepare(bi->clk);
++ clk_put(bi->clk);
++ kfree(bi);
++
++ return 0;
++}
++
++static const struct of_device_id bcm2708_i2c_of_match[] = {
++ { .compatible = "brcm,bcm2708-i2c" },
++ {},
++};
++MODULE_DEVICE_TABLE(of, bcm2708_i2c_of_match);
++
++static struct platform_driver bcm2708_i2c_driver = {
++ .driver = {
++ .name = DRV_NAME,
++ .owner = THIS_MODULE,
++ .of_match_table = bcm2708_i2c_of_match,
++ },
++ .probe = bcm2708_i2c_probe,
++ .remove = bcm2708_i2c_remove,
++};
++
++// module_platform_driver(bcm2708_i2c_driver);
++
++
++static int __init bcm2708_i2c_init(void)
++{
++ return platform_driver_register(&bcm2708_i2c_driver);
++}
++
++static void __exit bcm2708_i2c_exit(void)
++{
++ platform_driver_unregister(&bcm2708_i2c_driver);
++}
++
++module_init(bcm2708_i2c_init);
++module_exit(bcm2708_i2c_exit);
++
++
++
++MODULE_DESCRIPTION("BSC controller driver for Broadcom BCM2708");
++MODULE_AUTHOR("Chris Boot <bootc@bootc.net>");
++MODULE_LICENSE("GPL v2");
++MODULE_ALIAS("platform:" DRV_NAME);
+diff -Nur linux-4.1.3/drivers/i2c/busses/Kconfig linux-xbian-rpi/drivers/i2c/busses/Kconfig
+--- linux-4.1.3/drivers/i2c/busses/Kconfig 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/i2c/busses/Kconfig 2015-07-28 01:20:58.198038163 +0200
+@@ -8,6 +8,25 @@
+ comment "PC SMBus host controller drivers"
+ depends on PCI
+
++config I2C_BCM2708
++ tristate "BCM2708 BSC"
++ depends on MACH_BCM2708 || MACH_BCM2709
++ help
++ Enabling this option will add BSC (Broadcom Serial Controller)
++ support for the BCM2708. BSC is a Broadcom proprietary bus compatible
++ with I2C/TWI/SMBus.
++
++config I2C_BCM2708_BAUDRATE
++ prompt "BCM2708 I2C baudrate"
++ depends on I2C_BCM2708
++ int
++ default 100000
++ help
++ Set the I2C baudrate. This will alter the default value. A
++ different baudrate can be set by using a module parameter as well. If
++ no parameter is provided when loading, this is the value that will be
++ used.
++
+ config I2C_ALI1535
+ tristate "ALI 1535"
+ depends on PCI
+@@ -362,7 +381,7 @@
+
+ config I2C_BCM2835
+ tristate "Broadcom BCM2835 I2C controller"
+- depends on ARCH_BCM2835
++ depends on ARCH_BCM2835 || ARCH_BCM2708 || ARCH_BCM2709
+ help
+ If you say yes to this option, support will be included for the
+ BCM2835 I2C controller.
+diff -Nur linux-4.1.3/drivers/i2c/busses/Makefile linux-xbian-rpi/drivers/i2c/busses/Makefile
+--- linux-4.1.3/drivers/i2c/busses/Makefile 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/i2c/busses/Makefile 2015-07-28 01:20:58.198038163 +0200
+@@ -2,6 +2,8 @@
+ # Makefile for the i2c bus drivers.
+ #
+
++obj-$(CONFIG_I2C_BCM2708) += i2c-bcm2708.o
++
+ # ACPI drivers
+ obj-$(CONFIG_I2C_SCMI) += i2c-scmi.o
+
+diff -Nur linux-4.1.3/drivers/input/joystick/Kconfig linux-xbian-rpi/drivers/input/joystick/Kconfig
+--- linux-4.1.3/drivers/input/joystick/Kconfig 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/input/joystick/Kconfig 2015-07-28 01:20:58.198038163 +0200
+@@ -329,4 +329,12 @@
+ To compile this as a module choose M here: the module will be called
+ maplecontrol.
+
++config JOYSTICK_RPISENSE
++ tristate "Raspberry Pi Sense HAT joystick"
++ depends on GPIOLIB && INPUT
++ select MFD_RPISENSE_CORE
++
++ help
++ This is the joystick driver for the Raspberry Pi Sense HAT
++
+ endif
+diff -Nur linux-4.1.3/drivers/input/joystick/Makefile linux-xbian-rpi/drivers/input/joystick/Makefile
+--- linux-4.1.3/drivers/input/joystick/Makefile 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/input/joystick/Makefile 2015-07-28 01:20:58.198038163 +0200
+@@ -32,4 +32,5 @@
+ obj-$(CONFIG_JOYSTICK_XPAD) += xpad.o
+ obj-$(CONFIG_JOYSTICK_ZHENHUA) += zhenhua.o
+ obj-$(CONFIG_JOYSTICK_WALKERA0701) += walkera0701.o
++obj-$(CONFIG_JOYSTICK_RPISENSE) += rpisense-js.o
+
+diff -Nur linux-4.1.3/drivers/input/joystick/rpisense-js.c linux-xbian-rpi/drivers/input/joystick/rpisense-js.c
+--- linux-4.1.3/drivers/input/joystick/rpisense-js.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/input/joystick/rpisense-js.c 2015-07-28 01:20:58.198038163 +0200
+@@ -0,0 +1,153 @@
++/*
++ * Raspberry Pi Sense HAT joystick driver
++ * http://raspberrypi.org
++ *
++ * Copyright (C) 2015 Raspberry Pi
++ *
++ * Author: Serge Schneider
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ */
++
++#include <linux/module.h>
++
++#include <linux/mfd/rpisense/joystick.h>
++#include <linux/mfd/rpisense/core.h>
++
++struct rpisense *rpisense;
++unsigned char keymap[5] = {KEY_DOWN, KEY_RIGHT, KEY_UP, KEY_ENTER, KEY_LEFT,};
++
++static void keys_work_fn(struct work_struct *work)
++{
++ int i;
++ static s32 prev_keys;
++ struct rpisense_js *rpisense_js = &rpisense->joystick;
++ s32 keys = rpisense_reg_read(rpisense, RPISENSE_KEYS);
++ s32 changes = keys ^ prev_keys;
++
++ prev_keys = keys;
++ for (i = 0; i < 5; i++) {
++ if (changes & 1) {
++ input_report_key(rpisense_js->keys_dev,
++ keymap[i], keys & 1);
++ }
++ changes >>= 1;
++ keys >>= 1;
++ }
++ input_sync(rpisense_js->keys_dev);
++}
++
++static irqreturn_t keys_irq_handler(int irq, void *pdev)
++{
++ struct rpisense_js *rpisense_js = &rpisense->joystick;
++
++ schedule_work(&rpisense_js->keys_work_s);
++ return IRQ_HANDLED;
++}
++
++static int rpisense_js_probe(struct platform_device *pdev)
++{
++ int ret;
++ int i;
++ struct rpisense_js *rpisense_js;
++
++ rpisense = rpisense_get_dev();
++ rpisense_js = &rpisense->joystick;
++
++ INIT_WORK(&rpisense_js->keys_work_s, keys_work_fn);
++
++ rpisense_js->keys_dev = input_allocate_device();
++ if (!rpisense_js->keys_dev) {
++ dev_err(&pdev->dev, "Could not allocate input device.\n");
++ return -ENOMEM;
++ }
++
++ rpisense_js->keys_dev->evbit[0] = BIT_MASK(EV_KEY);
++ for (i = 0; i < ARRAY_SIZE(keymap); i++) {
++ set_bit(keymap[i],
++ rpisense_js->keys_dev->keybit);
++ }
++
++ rpisense_js->keys_dev->name = "Raspberry Pi Sense HAT Joystick";
++ rpisense_js->keys_dev->phys = "rpi-sense-joy/input0";
++ rpisense_js->keys_dev->id.bustype = BUS_I2C;
++ rpisense_js->keys_dev->evbit[0] = BIT_MASK(EV_KEY) | BIT_MASK(EV_REP);
++ rpisense_js->keys_dev->keycode = keymap;
++ rpisense_js->keys_dev->keycodesize = sizeof(unsigned char);
++ rpisense_js->keys_dev->keycodemax = ARRAY_SIZE(keymap);
++
++ ret = input_register_device(rpisense_js->keys_dev);
++ if (ret) {
++ dev_err(&pdev->dev, "Could not register input device.\n");
++ goto err_keys_alloc;
++ }
++
++ ret = gpiod_direction_input(rpisense_js->keys_desc);
++ if (ret) {
++ dev_err(&pdev->dev, "Could not set keys-int direction.\n");
++ goto err_keys_reg;
++ }
++
++ rpisense_js->keys_irq = gpiod_to_irq(rpisense_js->keys_desc);
++ if (rpisense_js->keys_irq < 0) {
++ dev_err(&pdev->dev, "Could not determine keys-int IRQ.\n");
++ ret = rpisense_js->keys_irq;
++ goto err_keys_reg;
++ }
++
++ ret = devm_request_irq(&pdev->dev, rpisense_js->keys_irq,
++ keys_irq_handler, IRQF_TRIGGER_RISING,
++ "keys", &pdev->dev);
++ if (ret) {
++ dev_err(&pdev->dev, "IRQ request failed.\n");
++ goto err_keys_reg;
++ }
++ return 0;
++err_keys_reg:
++ input_unregister_device(rpisense_js->keys_dev);
++err_keys_alloc:
++ input_free_device(rpisense_js->keys_dev);
++ return ret;
++}
++
++static int rpisense_js_remove(struct platform_device *pdev)
++{
++ struct rpisense_js *rpisense_js = &rpisense->joystick;
++
++ input_unregister_device(rpisense_js->keys_dev);
++ input_free_device(rpisense_js->keys_dev);
++ return 0;
++}
++
++#ifdef CONFIG_OF
++static const struct of_device_id rpisense_js_id[] = {
++ { .compatible = "rpi,rpi-sense-js" },
++ { },
++};
++MODULE_DEVICE_TABLE(of, rpisense_js_id);
++#endif
++
++static struct platform_device_id rpisense_js_device_id[] = {
++ { .name = "rpi-sense-js" },
++ { },
++};
++MODULE_DEVICE_TABLE(platform, rpisense_js_device_id);
++
++static struct platform_driver rpisense_js_driver = {
++ .probe = rpisense_js_probe,
++ .remove = rpisense_js_remove,
++ .driver = {
++ .name = "rpi-sense-js",
++ .owner = THIS_MODULE,
++ },
++};
++
++module_platform_driver(rpisense_js_driver);
++
++MODULE_DESCRIPTION("Raspberry Pi Sense HAT joystick driver");
++MODULE_AUTHOR("Serge Schneider <serge@raspberrypi.org>");
++MODULE_LICENSE("GPL");
+diff -Nur linux-4.1.3/drivers/input/touchscreen/Kconfig linux-xbian-rpi/drivers/input/touchscreen/Kconfig
+--- linux-4.1.3/drivers/input/touchscreen/Kconfig 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/input/touchscreen/Kconfig 2015-07-28 01:20:58.198038163 +0200
+@@ -583,6 +583,13 @@
+ To compile this driver as a module, choose M here: the
+ module will be called edt-ft5x06.
+
++config TOUCHSCREEN_RPI_FT5406
++ tristate "Raspberry Pi FT5406 driver"
++ depends on ARCH_BCM2708 || ARCH_BCM2709
++ help
++ Say Y here to enable the Raspberry Pi memory based FT5406 device
++
++
+ config TOUCHSCREEN_MIGOR
+ tristate "Renesas MIGO-R touchscreen"
+ depends on SH_MIGOR && I2C
+diff -Nur linux-4.1.3/drivers/input/touchscreen/Makefile linux-xbian-rpi/drivers/input/touchscreen/Makefile
+--- linux-4.1.3/drivers/input/touchscreen/Makefile 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/input/touchscreen/Makefile 2015-07-28 01:20:58.198038163 +0200
+@@ -29,6 +29,7 @@
+ obj-$(CONFIG_TOUCHSCREEN_DA9052) += da9052_tsi.o
+ obj-$(CONFIG_TOUCHSCREEN_DYNAPRO) += dynapro.o
+ obj-$(CONFIG_TOUCHSCREEN_EDT_FT5X06) += edt-ft5x06.o
++obj-$(CONFIG_TOUCHSCREEN_RPI_FT5406) += rpi-ft5406.o
+ obj-$(CONFIG_TOUCHSCREEN_HAMPSHIRE) += hampshire.o
+ obj-$(CONFIG_TOUCHSCREEN_GUNZE) += gunze.o
+ obj-$(CONFIG_TOUCHSCREEN_EETI) += eeti_ts.o
+diff -Nur linux-4.1.3/drivers/input/touchscreen/rpi-ft5406.c linux-xbian-rpi/drivers/input/touchscreen/rpi-ft5406.c
+--- linux-4.1.3/drivers/input/touchscreen/rpi-ft5406.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/input/touchscreen/rpi-ft5406.c 2015-07-28 01:20:58.198038163 +0200
+@@ -0,0 +1,246 @@
++/*
++ * Driver for memory based ft5406 touchscreen
++ *
++ * Copyright (C) 2015 Raspberry Pi
++ *
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++
++#include <linux/module.h>
++#include <linux/interrupt.h>
++#include <linux/input.h>
++#include <linux/irq.h>
++#include <linux/delay.h>
++#include <linux/slab.h>
++#include <linux/bitops.h>
++#include <linux/input/mt.h>
++#include <linux/kthread.h>
++#include <linux/platform_device.h>
++#include <asm/io.h>
++#include <soc/bcm2835/raspberrypi-firmware.h>
++
++#define MAXIMUM_SUPPORTED_POINTS 10
++struct ft5406_regs {
++ uint8_t device_mode;
++ uint8_t gesture_id;
++ uint8_t num_points;
++ struct ft5406_touch {
++ uint8_t xh;
++ uint8_t xl;
++ uint8_t yh;
++ uint8_t yl;
++ uint8_t res1;
++ uint8_t res2;
++ } point[MAXIMUM_SUPPORTED_POINTS];
++};
++
++#define SCREEN_WIDTH 800
++#define SCREEN_HEIGHT 480
++
++struct ft5406 {
++ struct platform_device * pdev;
++ struct input_dev * input_dev;
++ void __iomem * ts_base;
++ struct ft5406_regs * regs;
++ struct task_struct * thread;
++};
++
++/* Thread to poll for touchscreen events
++ *
++ * This thread polls the memory based register copy of the ft5406 registers
++ * using the number of points register to know whether the copy has been
++ * updated (we write 99 to the memory copy, the GPU will write between
++ * 0 - 10 points)
++ */
++static int ft5406_thread(void *arg)
++{
++ struct ft5406 *ts = (struct ft5406 *) arg;
++ struct ft5406_regs regs;
++ int known_ids = 0;
++
++ while(!kthread_should_stop())
++ {
++ // 60fps polling
++ msleep(17);
++ memcpy_fromio(&regs, ts->regs, sizeof(*ts->regs));
++ writel(99, &ts->regs->num_points);
++ // Do not output if theres no new information (num_points is 99)
++ // or we have no touch points and don't need to release any
++ if(!(regs.num_points == 99 || (regs.num_points == 0 && known_ids == 0)))
++ {
++ int i;
++ int modified_ids = 0, released_ids;
++ for(i = 0; i < regs.num_points; i++)
++ {
++ int x = (((int) regs.point[i].xh & 0xf) << 8) + regs.point[i].xl;
++ int y = (((int) regs.point[i].yh & 0xf) << 8) + regs.point[i].yl;
++ int touchid = (regs.point[i].yh >> 4) & 0xf;
++
++ modified_ids |= 1 << touchid;
++
++ if(!((1 << touchid) & known_ids))
++ dev_dbg(&ts->pdev->dev, "x = %d, y = %d, touchid = %d\n", x, y, touchid);
++
++ input_mt_slot(ts->input_dev, touchid);
++ input_mt_report_slot_state(ts->input_dev, MT_TOOL_FINGER, 1);
++
++ input_report_abs(ts->input_dev, ABS_MT_POSITION_X, x);
++ input_report_abs(ts->input_dev, ABS_MT_POSITION_Y, y);
++
++ }
++
++ released_ids = known_ids & ~modified_ids;
++ for(i = 0; released_ids && i < MAXIMUM_SUPPORTED_POINTS; i++)
++ {
++ if(released_ids & (1<<i))
++ {
++ dev_dbg(&ts->pdev->dev, "Released %d, known = %x modified = %x\n", i, known_ids, modified_ids);
++ input_mt_slot(ts->input_dev, i);
++ input_mt_report_slot_state(ts->input_dev, MT_TOOL_FINGER, 0);
++ modified_ids &= ~(1 << i);
++ }
++ }
++ known_ids = modified_ids;
++
++ input_mt_report_pointer_emulation(ts->input_dev, true);
++ input_sync(ts->input_dev);
++ }
++
++ }
++
++ return 0;
++}
++
++static int ft5406_probe(struct platform_device *pdev)
++{
++ int ret;
++ struct input_dev * input_dev = input_allocate_device();
++ struct ft5406 * ts;
++ struct device_node *fw_node;
++ struct rpi_firmware *fw;
++ u32 touchbuf;
++
++ dev_info(&pdev->dev, "Probing device\n");
++
++ fw_node = of_parse_phandle(pdev->dev.of_node, "firmware", 0);
++ if (!fw_node) {
++ dev_err(&pdev->dev, "Missing firmware node\n");
++ return -ENOENT;
++ }
++
++ fw = rpi_firmware_get(fw_node);
++ if (!fw)
++ return -EPROBE_DEFER;
++
++ ret = rpi_firmware_property(fw, RPI_FIRMWARE_FRAMEBUFFER_GET_TOUCHBUF,
++ &touchbuf, sizeof(touchbuf));
++ if (ret) {
++ dev_err(&pdev->dev, "Failed to get touch buffer\n");
++ return ret;
++ }
++
++ if (!touchbuf) {
++ dev_err(&pdev->dev, "Touchscreen not detected\n");
++ return -ENODEV;
++ }
++
++ dev_dbg(&pdev->dev, "Got TS buffer 0x%x\n", touchbuf);
++
++ ts = kzalloc(sizeof(struct ft5406), GFP_KERNEL);
++
++ if (!ts || !input_dev) {
++ ret = -ENOMEM;
++ dev_err(&pdev->dev, "Failed to allocate memory\n");
++ return ret;
++ }
++ ts->input_dev = input_dev;
++ platform_set_drvdata(pdev, ts);
++ ts->pdev = pdev;
++
++ input_dev->name = "FT5406 memory based driver";
++
++ __set_bit(EV_KEY, input_dev->evbit);
++ __set_bit(EV_SYN, input_dev->evbit);
++ __set_bit(EV_ABS, input_dev->evbit);
++
++ input_set_abs_params(input_dev, ABS_MT_POSITION_X, 0,
++ SCREEN_WIDTH, 0, 0);
++ input_set_abs_params(input_dev, ABS_MT_POSITION_Y, 0,
++ SCREEN_HEIGHT, 0, 0);
++
++ input_mt_init_slots(input_dev, MAXIMUM_SUPPORTED_POINTS, INPUT_MT_DIRECT);
++
++ input_set_drvdata(input_dev, ts);
++
++ ret = input_register_device(input_dev);
++ if (ret) {
++ dev_err(&pdev->dev, "could not register input device, %d\n",
++ ret);
++ return ret;
++ }
++
++ // mmap the physical memory
++ touchbuf &= ~0xc0000000;
++ ts->ts_base = ioremap(touchbuf, sizeof(*ts->regs));
++ if(ts->ts_base == NULL)
++ {
++ dev_err(&pdev->dev, "Failed to map physical address\n");
++ input_unregister_device(input_dev);
++ kzfree(ts);
++ return -ENOMEM;
++ }
++
++ ts->regs = (struct ft5406_regs *) ts->ts_base;
++
++ // create thread to poll the touch events
++ ts->thread = kthread_run(ft5406_thread, ts, "ft5406");
++ if(ts->thread == NULL)
++ {
++ dev_err(&pdev->dev, "Failed to create kernel thread");
++ iounmap(ts->ts_base);
++ input_unregister_device(input_dev);
++ kzfree(ts);
++ }
++
++ return 0;
++}
++
++static int ft5406_remove(struct platform_device *pdev)
++{
++ struct ft5406 *ts = (struct ft5406 *) platform_get_drvdata(pdev);
++
++ dev_info(&pdev->dev, "Removing rpi-ft5406\n");
++
++ kthread_stop(ts->thread);
++ iounmap(ts->ts_base);
++ input_unregister_device(ts->input_dev);
++ kzfree(ts);
++
++ return 0;
++}
++
++static const struct of_device_id ft5406_match[] = {
++ { .compatible = "rpi,rpi-ft5406", },
++ {},
++};
++MODULE_DEVICE_TABLE(of, ft5406_match);
++
++static struct platform_driver ft5406_driver = {
++ .driver = {
++ .name = "rpi-ft5406",
++ .owner = THIS_MODULE,
++ .of_match_table = ft5406_match,
++ },
++ .probe = ft5406_probe,
++ .remove = ft5406_remove,
++};
++
++module_platform_driver(ft5406_driver);
++
++MODULE_AUTHOR("Gordon Hollingworth");
++MODULE_DESCRIPTION("Touchscreen driver for memory based FT5406");
++MODULE_LICENSE("GPL");
+diff -Nur linux-4.1.3/drivers/irqchip/irq-bcm2835.c linux-xbian-rpi/drivers/irqchip/irq-bcm2835.c
+--- linux-4.1.3/drivers/irqchip/irq-bcm2835.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/irqchip/irq-bcm2835.c 2015-07-28 01:20:58.198038163 +0200
+@@ -56,7 +56,7 @@
+ #include "irqchip.h"
+
+ /* Put the bank and irq (32 bits) into the hwirq */
+-#define MAKE_HWIRQ(b, n) ((b << 5) | (n))
++#define MAKE_HWIRQ(b, n) (((b) << 5) | (n))
+ #define HWIRQ_BANK(i) (i >> 5)
+ #define HWIRQ_BIT(i) BIT(i & 0x1f)
+
+@@ -72,9 +72,13 @@
+ | SHORTCUT1_MASK | SHORTCUT2_MASK)
+
+ #define REG_FIQ_CONTROL 0x0c
++#define REG_FIQ_ENABLE 0x80
++#define REG_FIQ_DISABLE 0
+
+ #define NR_BANKS 3
+ #define IRQS_PER_BANK 32
++#define NUMBER_IRQS MAKE_HWIRQ(NR_BANKS, 0)
++#define FIQ_START (NR_IRQS_BANK0 + MAKE_HWIRQ(NR_BANKS - 1, 0))
+
+ static int reg_pending[] __initconst = { 0x00, 0x04, 0x08 };
+ static int reg_enable[] __initconst = { 0x18, 0x10, 0x14 };
+@@ -98,14 +102,38 @@
+ static void __exception_irq_entry bcm2835_handle_irq(
+ struct pt_regs *regs);
+
++static inline unsigned int hwirq_to_fiq(unsigned long hwirq)
++{
++ hwirq -= NUMBER_IRQS;
++ /*
++ * The hwirq numbering used in this driver is:
++ * BASE (0-7) GPU1 (32-63) GPU2 (64-95).
++ * This differ from the one used in the FIQ register:
++ * GPU1 (0-31) GPU2 (32-63) BASE (64-71)
++ */
++ if (hwirq >= 32)
++ return hwirq - 32;
++
++ return hwirq + 64;
++}
++
+ static void armctrl_mask_irq(struct irq_data *d)
+ {
+- writel_relaxed(HWIRQ_BIT(d->hwirq), intc.disable[HWIRQ_BANK(d->hwirq)]);
++ if (d->hwirq >= NUMBER_IRQS)
++ writel_relaxed(REG_FIQ_DISABLE, intc.base + REG_FIQ_CONTROL);
++ else
++ writel_relaxed(HWIRQ_BIT(d->hwirq),
++ intc.disable[HWIRQ_BANK(d->hwirq)]);
+ }
+
+ static void armctrl_unmask_irq(struct irq_data *d)
+ {
+- writel_relaxed(HWIRQ_BIT(d->hwirq), intc.enable[HWIRQ_BANK(d->hwirq)]);
++ if (d->hwirq >= NUMBER_IRQS)
++ writel_relaxed(REG_FIQ_ENABLE | hwirq_to_fiq(d->hwirq),
++ intc.base + REG_FIQ_CONTROL);
++ else
++ writel_relaxed(HWIRQ_BIT(d->hwirq),
++ intc.enable[HWIRQ_BANK(d->hwirq)]);
+ }
+
+ static struct irq_chip armctrl_chip = {
+@@ -150,8 +178,9 @@
+ panic("%s: unable to map IC registers\n",
+ node->full_name);
+
+- intc.domain = irq_domain_add_linear(node, MAKE_HWIRQ(NR_BANKS, 0),
+- &armctrl_ops, NULL);
++ intc.base = base;
++ intc.domain = irq_domain_add_linear(node, NUMBER_IRQS * 2,
++ &armctrl_ops, NULL);
+ if (!intc.domain)
+ panic("%s: unable to create IRQ domain\n", node->full_name);
+
+@@ -168,8 +197,20 @@
+ set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+ }
+ }
+-
+ set_handle_irq(bcm2835_handle_irq);
++
++ /* Make a duplicate irq range which is used to enable FIQ */
++ for (b = 0; b < NR_BANKS; b++) {
++ for (i = 0; i < bank_irqs[b]; i++) {
++ irq = irq_create_mapping(intc.domain,
++ MAKE_HWIRQ(b, i) + NUMBER_IRQS);
++ BUG_ON(irq <= 0);
++ irq_set_chip(irq, &armctrl_chip);
++ set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
++ }
++ }
++ init_FIQ(FIQ_START);
++
+ return 0;
+ }
+
+diff -Nur linux-4.1.3/drivers/leds/leds-gpio.c linux-xbian-rpi/drivers/leds/leds-gpio.c
+--- linux-4.1.3/drivers/leds/leds-gpio.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/leds/leds-gpio.c 2015-07-28 01:20:58.198038163 +0200
+@@ -41,6 +41,13 @@
+ led_dat->platform_gpio_blink_set(led_dat->gpiod,
+ led_dat->new_level, NULL, NULL);
+ led_dat->blinking = 0;
++ } else if (led_dat->cdev.flags & SET_GPIO_INPUT) {
++ gpiod_direction_input(led_dat->gpiod);
++ led_dat->cdev.flags &= ~SET_GPIO_INPUT;
++ }
++ else if (led_dat->cdev.flags & SET_GPIO_OUTPUT) {
++ gpiod_direction_output(led_dat->gpiod, led_dat->new_level);
++ led_dat->cdev.flags &= ~SET_GPIO_OUTPUT;
+ } else
+ gpiod_set_value_cansleep(led_dat->gpiod, led_dat->new_level);
+ }
+@@ -61,7 +68,8 @@
+ * seem to have a reliable way to know if we're already in one; so
+ * let's just assume the worst.
+ */
+- if (led_dat->can_sleep) {
++ if (led_dat->can_sleep ||
++ (led_dat->cdev.flags & (SET_GPIO_INPUT | SET_GPIO_OUTPUT) )) {
+ led_dat->new_level = level;
+ schedule_work(&led_dat->work);
+ } else {
+@@ -74,6 +82,13 @@
+ }
+ }
+
++static enum led_brightness gpio_led_get(struct led_classdev *led_cdev)
++{
++ struct gpio_led_data *led_dat =
++ container_of(led_cdev, struct gpio_led_data, cdev);
++ return gpiod_get_value_cansleep(led_dat->gpiod) ? LED_FULL : LED_OFF;
++}
++
+ static int gpio_blink_set(struct led_classdev *led_cdev,
+ unsigned long *delay_on, unsigned long *delay_off)
+ {
+@@ -130,6 +145,7 @@
+ led_dat->cdev.blink_set = gpio_blink_set;
+ }
+ led_dat->cdev.brightness_set = gpio_led_set;
++ led_dat->cdev.brightness_get = gpio_led_get;
+ if (template->default_state == LEDS_GPIO_DEFSTATE_KEEP)
+ state = !!gpiod_get_value_cansleep(led_dat->gpiod);
+ else
+diff -Nur linux-4.1.3/drivers/leds/trigger/Kconfig linux-xbian-rpi/drivers/leds/trigger/Kconfig
+--- linux-4.1.3/drivers/leds/trigger/Kconfig 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/leds/trigger/Kconfig 2015-07-28 01:20:58.198038163 +0200
+@@ -108,4 +108,11 @@
+ This enables direct flash/torch on/off by the driver, kernel space.
+ If unsure, say Y.
+
++config LEDS_TRIGGER_INPUT
++ tristate "LED Input Trigger"
++ depends on LEDS_TRIGGERS
++ help
++ This allows the GPIOs assigned to be LEDs to be initialised to inputs.
++ If unsure, say Y.
++
+ endif # LEDS_TRIGGERS
+diff -Nur linux-4.1.3/drivers/leds/trigger/ledtrig-input.c linux-xbian-rpi/drivers/leds/trigger/ledtrig-input.c
+--- linux-4.1.3/drivers/leds/trigger/ledtrig-input.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/leds/trigger/ledtrig-input.c 2015-07-28 01:20:58.198038163 +0200
+@@ -0,0 +1,54 @@
++/*
++ * Set LED GPIO to Input "Trigger"
++ *
++ * Copyright 2015 Phil Elwell <phil@raspberrypi.org>
++ *
++ * Based on Nick Forbes's ledtrig-default-on.c.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/leds.h>
++#include <linux/gpio.h>
++#include "../leds.h"
++
++static void input_trig_activate(struct led_classdev *led_cdev)
++{
++ led_cdev->flags |= SET_GPIO_INPUT;
++ led_set_brightness_async(led_cdev, 0);
++}
++
++static void input_trig_deactivate(struct led_classdev *led_cdev)
++{
++ led_cdev->flags |= SET_GPIO_OUTPUT;
++ led_set_brightness_async(led_cdev, 0);
++}
++
++static struct led_trigger input_led_trigger = {
++ .name = "input",
++ .activate = input_trig_activate,
++ .deactivate = input_trig_deactivate,
++};
++
++static int __init input_trig_init(void)
++{
++ return led_trigger_register(&input_led_trigger);
++}
++
++static void __exit input_trig_exit(void)
++{
++ led_trigger_unregister(&input_led_trigger);
++}
++
++module_init(input_trig_init);
++module_exit(input_trig_exit);
++
++MODULE_AUTHOR("Phil Elwell <phil@raspberrypi.org>");
++MODULE_DESCRIPTION("Set LED GPIO to Input \"trigger\"");
++MODULE_LICENSE("GPL");
+diff -Nur linux-4.1.3/drivers/leds/trigger/Makefile linux-xbian-rpi/drivers/leds/trigger/Makefile
+--- linux-4.1.3/drivers/leds/trigger/Makefile 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/leds/trigger/Makefile 2015-07-28 01:20:58.198038163 +0200
+@@ -8,3 +8,4 @@
+ obj-$(CONFIG_LEDS_TRIGGER_DEFAULT_ON) += ledtrig-default-on.o
+ obj-$(CONFIG_LEDS_TRIGGER_TRANSIENT) += ledtrig-transient.o
+ obj-$(CONFIG_LEDS_TRIGGER_CAMERA) += ledtrig-camera.o
++obj-$(CONFIG_LEDS_TRIGGER_INPUT) += ledtrig-input.o
+diff -Nur linux-4.1.3/drivers/mailbox/bcm2708-vcio.c linux-xbian-rpi/drivers/mailbox/bcm2708-vcio.c
+--- linux-4.1.3/drivers/mailbox/bcm2708-vcio.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/mailbox/bcm2708-vcio.c 2015-07-28 01:20:58.198038163 +0200
+@@ -0,0 +1,86 @@
++/*
++ * Copyright (C) 2010 Broadcom
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * This device provides a shared mechanism for writing to the mailboxes,
++ * semaphores, doorbells etc. that are shared between the ARM and the
++ * VideoCore processor
++ */
++
++#include <linux/dma-mapping.h>
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/platform_data/mailbox-bcm2708.h>
++#include <linux/uaccess.h>
++#include <soc/bcm2835/raspberrypi-firmware.h>
++
++#define DRIVER_NAME "bcm2708_vcio"
++
++extern int bcm_mailbox_write(unsigned chan, uint32_t data28)
++{
++ struct rpi_firmware *fw = rpi_firmware_get(NULL);
++
++ if (!fw)
++ return -ENODEV;
++
++ return rpi_firmware_transaction(fw, chan, data28);
++}
++EXPORT_SYMBOL_GPL(bcm_mailbox_write);
++
++extern int bcm_mailbox_read(unsigned chan, uint32_t *data28)
++{
++ struct rpi_firmware *fw = rpi_firmware_get(NULL);
++
++ if (!fw)
++ return -ENODEV;
++
++ *data28 = rpi_firmware_transaction_received(fw);
++
++ return 0;
++}
++EXPORT_SYMBOL_GPL(bcm_mailbox_read);
++
++static DEFINE_MUTEX(mailbox_lock);
++extern int bcm_mailbox_property(void *data, int size)
++{
++ uint32_t success;
++ dma_addr_t mem_bus; /* the memory address accessed from videocore */
++ void *mem_kern; /* the memory address accessed from driver */
++ int s = 0;
++
++ mutex_lock(&mailbox_lock);
++ /* allocate some memory for the messages communicating with GPU */
++ mem_kern = dma_alloc_coherent(NULL, PAGE_ALIGN(size), &mem_bus,
++ GFP_KERNEL);
++ if (mem_kern) {
++ /* create the message */
++ memcpy(mem_kern, data, size);
++
++ /* send the message */
++ wmb();
++ s = bcm_mailbox_write(MBOX_CHAN_PROPERTY, (uint32_t)mem_bus);
++ if (s == 0)
++ s = bcm_mailbox_read(MBOX_CHAN_PROPERTY, &success);
++ if (s == 0) {
++ /* copy the response */
++ rmb();
++ memcpy(data, mem_kern, size);
++ }
++ dma_free_coherent(NULL, PAGE_ALIGN(size), mem_kern, mem_bus);
++ } else {
++ s = -ENOMEM;
++ }
++ if (s != 0)
++ pr_err(DRIVER_NAME ": %s failed (%d)\n", __func__, s);
++
++ mutex_unlock(&mailbox_lock);
++ return s;
++}
++EXPORT_SYMBOL_GPL(bcm_mailbox_property);
++
++MODULE_AUTHOR("Gray Girling");
++MODULE_DESCRIPTION("ARM I/O to VideoCore processor");
++MODULE_LICENSE("GPL");
+diff -Nur linux-4.1.3/drivers/mailbox/bcm2835-mailbox.c linux-xbian-rpi/drivers/mailbox/bcm2835-mailbox.c
+--- linux-4.1.3/drivers/mailbox/bcm2835-mailbox.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/mailbox/bcm2835-mailbox.c 2015-07-28 01:20:58.198038163 +0200
+@@ -0,0 +1,231 @@
++/*
++ * Copyright (C) 2010,2015 Broadcom
++ * Copyright (C) 2013-2014 Lubomir Rintel
++ * Copyright (C) 2013 Craig McGeachie
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * This device provides a mechanism for writing to the mailboxes,
++ * that are shared between the ARM and the VideoCore processor
++ *
++ * Parts of the driver are based on:
++ * - arch/arm/mach-bcm2708/vcio.c file written by Gray Girling that was
++ * obtained from branch "rpi-3.6.y" of git://github.com/raspberrypi/
++ * linux.git
++ * - drivers/mailbox/bcm2835-ipc.c by Lubomir Rintel at
++ * https://github.com/hackerspace/rpi-linux/blob/lr-raspberry-pi/drivers/
++ * mailbox/bcm2835-ipc.c
++ * - documentation available on the following web site:
++ * https://github.com/raspberrypi/firmware/wiki/Mailbox-property-interface
++ */
++
++#include <linux/device.h>
++#include <linux/dma-mapping.h>
++#include <linux/err.h>
++#include <linux/interrupt.h>
++#include <linux/irq.h>
++#include <linux/kernel.h>
++#include <linux/mailbox_controller.h>
++#include <linux/module.h>
++#include <linux/of_address.h>
++#include <linux/of_irq.h>
++#include <linux/platform_device.h>
++#include <linux/spinlock.h>
++
++/* Mailboxes */
++#define ARM_0_MAIL0 0x00
++#define ARM_0_MAIL1 0x20
++
++/*
++ * Mailbox registers. We basically only support mailbox 0 & 1. We
++ * deliver to the VC in mailbox 1, it delivers to us in mailbox 0. See
++ * BCM2835-ARM-Peripherals.pdf section 1.3 for an explanation about
++ * the placement of memory barriers.
++ */
++#define MAIL0_RD (ARM_0_MAIL0 + 0x00)
++#define MAIL0_POL (ARM_0_MAIL0 + 0x10)
++#define MAIL0_STA (ARM_0_MAIL0 + 0x18)
++#define MAIL0_CNF (ARM_0_MAIL0 + 0x1C)
++#define MAIL1_WRT (ARM_0_MAIL1 + 0x00)
++#define MAIL1_STA (ARM_0_MAIL1 + 0x18)
++
++/* On ARCH_BCM270x these come through <linux/interrupt.h> (arm_control.h ) */
++#ifndef ARM_MS_FULL
++/* Status register: FIFO state. */
++#define ARM_MS_FULL BIT(31)
++#define ARM_MS_EMPTY BIT(30)
++
++/* Configuration register: Enable interrupts. */
++#define ARM_MC_IHAVEDATAIRQEN BIT(0)
++#endif
++
++struct bcm2835_mbox {
++ void __iomem *regs;
++ spinlock_t lock;
++ struct mbox_controller controller;
++};
++
++static struct bcm2835_mbox *bcm2835_link_mbox(struct mbox_chan *link)
++{
++ return container_of(link->mbox, struct bcm2835_mbox, controller);
++}
++
++static irqreturn_t bcm2835_mbox_irq(int irq, void *dev_id)
++{
++ struct bcm2835_mbox *mbox = dev_id;
++ struct device *dev = mbox->controller.dev;
++ struct mbox_chan *link = &mbox->controller.chans[0];
++
++ while (!(readl(mbox->regs + MAIL0_STA) & ARM_MS_EMPTY)) {
++ u32 msg = readl(mbox->regs + MAIL0_RD);
++ dev_dbg(dev, "Reply 0x%08X\n", msg);
++ mbox_chan_received_data(link, &msg);
++ }
++ return IRQ_HANDLED;
++}
++
++static int bcm2835_send_data(struct mbox_chan *link, void *data)
++{
++ struct bcm2835_mbox *mbox = bcm2835_link_mbox(link);
++ u32 msg = *(u32 *)data;
++
++ spin_lock(&mbox->lock);
++ writel(msg, mbox->regs + MAIL1_WRT);
++ dev_dbg(mbox->controller.dev, "Request 0x%08X\n", msg);
++ spin_unlock(&mbox->lock);
++ return 0;
++}
++
++static int bcm2835_startup(struct mbox_chan *link)
++{
++ struct bcm2835_mbox *mbox = bcm2835_link_mbox(link);
++
++ /* Enable the interrupt on data reception */
++ writel(ARM_MC_IHAVEDATAIRQEN, mbox->regs + MAIL0_CNF);
++
++ return 0;
++}
++
++static void bcm2835_shutdown(struct mbox_chan *link)
++{
++ struct bcm2835_mbox *mbox = bcm2835_link_mbox(link);
++
++ writel(0, mbox->regs + MAIL0_CNF);
++}
++
++static bool bcm2835_last_tx_done(struct mbox_chan *link)
++{
++ struct bcm2835_mbox *mbox = bcm2835_link_mbox(link);
++ bool ret;
++
++ spin_lock(&mbox->lock);
++ ret = !(readl(mbox->regs + MAIL1_STA) & ARM_MS_FULL);
++ spin_unlock(&mbox->lock);
++ return ret;
++}
++
++static const struct mbox_chan_ops bcm2835_mbox_chan_ops = {
++ .send_data = bcm2835_send_data,
++ .startup = bcm2835_startup,
++ .shutdown = bcm2835_shutdown,
++ .last_tx_done = bcm2835_last_tx_done
++};
++
++static struct mbox_chan *bcm2835_mbox_index_xlate(struct mbox_controller *mbox,
++ const struct of_phandle_args *sp)
++{
++ if (sp->args_count != 0)
++ return NULL;
++
++ return &mbox->chans[0];
++}
++
++static int bcm2835_mbox_probe(struct platform_device *pdev)
++{
++ struct device *dev = &pdev->dev;
++ int ret = 0;
++ struct resource *iomem;
++ struct bcm2835_mbox *mbox;
++
++ mbox = devm_kzalloc(dev, sizeof(*mbox), GFP_KERNEL);
++ if (mbox == NULL)
++ return -ENOMEM;
++ spin_lock_init(&mbox->lock);
++
++ ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
++ bcm2835_mbox_irq, 0, dev_name(dev), mbox);
++ if (ret) {
++ dev_err(dev, "Failed to register a mailbox IRQ handler: %d\n",
++ ret);
++ return -ENODEV;
++ }
++
++ iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ mbox->regs = devm_ioremap_resource(&pdev->dev, iomem);
++ if (IS_ERR(mbox->regs)) {
++ ret = PTR_ERR(mbox->regs);
++ dev_err(&pdev->dev, "Failed to remap mailbox regs: %d\n", ret);
++ return ret;
++ }
++
++ mbox->controller.txdone_poll = true;
++ mbox->controller.txpoll_period = 5;
++ mbox->controller.ops = &bcm2835_mbox_chan_ops;
++ mbox->controller.of_xlate = &bcm2835_mbox_index_xlate;
++ mbox->controller.dev = dev;
++ mbox->controller.num_chans = 1;
++ mbox->controller.chans = devm_kzalloc(dev,
++ sizeof(*mbox->controller.chans), GFP_KERNEL);
++ if (!mbox->controller.chans)
++ return -ENOMEM;
++
++ ret = mbox_controller_register(&mbox->controller);
++ if (ret)
++ return ret;
++
++ platform_set_drvdata(pdev, mbox);
++ dev_info(dev, "mailbox enabled\n");
++
++ return ret;
++}
++
++static int bcm2835_mbox_remove(struct platform_device *pdev)
++{
++ struct bcm2835_mbox *mbox = platform_get_drvdata(pdev);
++ mbox_controller_unregister(&mbox->controller);
++ return 0;
++}
++
++static const struct of_device_id bcm2835_mbox_of_match[] = {
++ { .compatible = "brcm,bcm2835-mbox", },
++ {},
++};
++MODULE_DEVICE_TABLE(of, bcm2835_mbox_of_match);
++
++static struct platform_driver bcm2835_mbox_driver = {
++ .driver = {
++ .name = "bcm2835-mbox",
++ .owner = THIS_MODULE,
++ .of_match_table = bcm2835_mbox_of_match,
++ },
++ .probe = bcm2835_mbox_probe,
++ .remove = bcm2835_mbox_remove,
++};
++
++static int __init bcm2835_mbox_init(void)
++{
++ return platform_driver_register(&bcm2835_mbox_driver);
++}
++arch_initcall(bcm2835_mbox_init);
++
++static void __init bcm2835_mbox_exit(void)
++{
++ platform_driver_unregister(&bcm2835_mbox_driver);
++}
++module_exit(bcm2835_mbox_exit);
++
++MODULE_AUTHOR("Lubomir Rintel <lkundrak@v3.sk>");
++MODULE_DESCRIPTION("BCM2835 mailbox IPC driver");
++MODULE_LICENSE("GPL v2");
+diff -Nur linux-4.1.3/drivers/mailbox/Kconfig linux-xbian-rpi/drivers/mailbox/Kconfig
+--- linux-4.1.3/drivers/mailbox/Kconfig 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/mailbox/Kconfig 2015-07-28 01:20:58.198038163 +0200
+@@ -7,6 +7,12 @@
+
+ if MAILBOX
+
++config BCM2708_MBOX
++ bool "Broadcom BCM2708 Mailbox (vcio)"
++ depends on BCM2835_MBOX
++ help
++ Broadcom BCM2708 Mailbox (vcio)
++
+ config ARM_MHU
+ tristate "ARM MHU Mailbox"
+ depends on ARM_AMBA
+@@ -60,4 +66,13 @@
+ An implementation of the Altera Mailbox soft core. It is used
+ to send message between processors. Say Y here if you want to use the
+ Altera mailbox support.
++
++config BCM2835_MBOX
++ tristate "BCM2835 Mailbox"
++ depends on ARCH_BCM2835 || ARCH_BCM2708 || ARCH_BCM2709
++ help
++ An implementation of the BCM2385 Mailbox. It is used to invoke
++ the services of the Videocore. Say Y here if you want to use the
++ BCM2835 Mailbox.
++
+ endif
+diff -Nur linux-4.1.3/drivers/mailbox/mailbox.c linux-xbian-rpi/drivers/mailbox/mailbox.c
+--- linux-4.1.3/drivers/mailbox/mailbox.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/mailbox/mailbox.c 2015-07-28 01:20:58.198038163 +0200
+@@ -304,13 +304,23 @@
+ unsigned long flags;
+ int ret;
+
+- if (!dev || !dev->of_node) {
++ if (!dev) {
+ pr_debug("%s: No owner device node\n", __func__);
+ return ERR_PTR(-ENODEV);
+ }
+
+ mutex_lock(&con_mutex);
+
++ if (!dev->of_node) {
++ chan = NULL;
++ /* pick the first controller in the list */
++ list_for_each_entry(mbox, &mbox_cons, node) {
++ chan = &mbox->chans[0];
++ break;
++ }
++ goto skip_dt;
++ }
++
+ if (of_parse_phandle_with_args(dev->of_node, "mboxes",
+ "#mbox-cells", index, &spec)) {
+ dev_dbg(dev, "%s: can't parse \"mboxes\" property\n", __func__);
+@@ -327,6 +337,7 @@
+
+ of_node_put(spec.np);
+
++skip_dt:
+ if (!chan || chan->cl || !try_module_get(mbox->dev->driver->owner)) {
+ dev_dbg(dev, "%s: mailbox not free\n", __func__);
+ mutex_unlock(&con_mutex);
+diff -Nur linux-4.1.3/drivers/mailbox/Makefile linux-xbian-rpi/drivers/mailbox/Makefile
+--- linux-4.1.3/drivers/mailbox/Makefile 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/mailbox/Makefile 2015-07-28 01:20:58.198038163 +0200
+@@ -2,6 +2,8 @@
+
+ obj-$(CONFIG_MAILBOX) += mailbox.o
+
++obj-$(CONFIG_BCM2708_MBOX) += bcm2708-vcio.o
++
+ obj-$(CONFIG_ARM_MHU) += arm_mhu.o
+
+ obj-$(CONFIG_PL320_MBOX) += pl320-ipc.o
+@@ -11,3 +13,5 @@
+ obj-$(CONFIG_PCC) += pcc.o
+
+ obj-$(CONFIG_ALTERA_MBOX) += mailbox-altera.o
++
++obj-$(CONFIG_BCM2835_MBOX) += bcm2835-mailbox.o
+diff -Nur linux-4.1.3/drivers/media/platform/bcm2835/bcm2835-camera.c linux-xbian-rpi/drivers/media/platform/bcm2835/bcm2835-camera.c
+--- linux-4.1.3/drivers/media/platform/bcm2835/bcm2835-camera.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/media/platform/bcm2835/bcm2835-camera.c 2015-07-28 01:20:58.198038163 +0200
+@@ -0,0 +1,1828 @@
++/*
++ * Broadcom BM2835 V4L2 driver
++ *
++ * Copyright © 2013 Raspberry Pi (Trading) Ltd.
++ *
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file COPYING in the main directory of this archive
++ * for more details.
++ *
++ * Authors: Vincent Sanders <vincent.sanders@collabora.co.uk>
++ * Dave Stevenson <dsteve@broadcom.com>
++ * Simon Mellor <simellor@broadcom.com>
++ * Luke Diamand <luked@broadcom.com>
++ */
++
++#include <linux/errno.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <media/videobuf2-vmalloc.h>
++#include <media/videobuf2-dma-contig.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-ioctl.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-fh.h>
++#include <media/v4l2-event.h>
++#include <media/v4l2-common.h>
++#include <linux/delay.h>
++
++#include "mmal-common.h"
++#include "mmal-encodings.h"
++#include "mmal-vchiq.h"
++#include "mmal-msg.h"
++#include "mmal-parameters.h"
++#include "bcm2835-camera.h"
++
++#define BM2835_MMAL_VERSION "0.0.2"
++#define BM2835_MMAL_MODULE_NAME "bcm2835-v4l2"
++#define MIN_WIDTH 16
++#define MIN_HEIGHT 16
++#define MAX_WIDTH 2592
++#define MAX_HEIGHT 1944
++#define MIN_BUFFER_SIZE (80*1024)
++
++#define MAX_VIDEO_MODE_WIDTH 1280
++#define MAX_VIDEO_MODE_HEIGHT 720
++
++MODULE_DESCRIPTION("Broadcom 2835 MMAL video capture");
++MODULE_AUTHOR("Vincent Sanders");
++MODULE_LICENSE("GPL");
++MODULE_VERSION(BM2835_MMAL_VERSION);
++
++int bcm2835_v4l2_debug;
++module_param_named(debug, bcm2835_v4l2_debug, int, 0644);
++MODULE_PARM_DESC(bcm2835_v4l2_debug, "Debug level 0-2");
++
++int max_video_width = MAX_VIDEO_MODE_WIDTH;
++int max_video_height = MAX_VIDEO_MODE_HEIGHT;
++module_param(max_video_width, int, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH);
++MODULE_PARM_DESC(max_video_width, "Threshold for video mode");
++module_param(max_video_height, int, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH);
++MODULE_PARM_DESC(max_video_height, "Threshold for video mode");
++
++/* Gstreamer bug https://bugzilla.gnome.org/show_bug.cgi?id=726521
++ * v4l2src does bad (and actually wrong) things when the vidioc_enum_framesizes
++ * function says type V4L2_FRMSIZE_TYPE_STEPWISE, which we do by default.
++ * It's happier if we just don't say anything at all, when it then
++ * sets up a load of defaults that it thinks might work.
++ * If gst_v4l2src_is_broken is non-zero, then we remove the function from
++ * our function table list (actually switch to an alternate set, but same
++ * result).
++ */
++int gst_v4l2src_is_broken = 0;
++module_param(gst_v4l2src_is_broken, int, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH);
++MODULE_PARM_DESC(gst_v4l2src_is_broken, "If non-zero, enable workaround for Gstreamer");
++
++static struct bm2835_mmal_dev *gdev; /* global device data */
++
++#define FPS_MIN 1
++#define FPS_MAX 90
++
++/* timeperframe: min/max and default */
++static const struct v4l2_fract
++ tpf_min = {.numerator = 1, .denominator = FPS_MAX},
++ tpf_max = {.numerator = 1, .denominator = FPS_MIN},
++ tpf_default = {.numerator = 1000, .denominator = 30000};
++
++/* video formats */
++static struct mmal_fmt formats[] = {
++ {
++ .name = "4:2:0, packed YUV",
++ .fourcc = V4L2_PIX_FMT_YUV420,
++ .flags = 0,
++ .mmal = MMAL_ENCODING_I420,
++ .depth = 12,
++ .mmal_component = MMAL_COMPONENT_CAMERA,
++ },
++ {
++ .name = "4:2:2, packed, YUYV",
++ .fourcc = V4L2_PIX_FMT_YUYV,
++ .flags = 0,
++ .mmal = MMAL_ENCODING_YUYV,
++ .depth = 16,
++ .mmal_component = MMAL_COMPONENT_CAMERA,
++ },
++ {
++ .name = "RGB24 (LE)",
++ .fourcc = V4L2_PIX_FMT_RGB24,
++ .flags = 0,
++ .mmal = MMAL_ENCODING_BGR24,
++ .depth = 24,
++ .mmal_component = MMAL_COMPONENT_CAMERA,
++ },
++ {
++ .name = "JPEG",
++ .fourcc = V4L2_PIX_FMT_JPEG,
++ .flags = V4L2_FMT_FLAG_COMPRESSED,
++ .mmal = MMAL_ENCODING_JPEG,
++ .depth = 8,
++ .mmal_component = MMAL_COMPONENT_IMAGE_ENCODE,
++ },
++ {
++ .name = "H264",
++ .fourcc = V4L2_PIX_FMT_H264,
++ .flags = V4L2_FMT_FLAG_COMPRESSED,
++ .mmal = MMAL_ENCODING_H264,
++ .depth = 8,
++ .mmal_component = MMAL_COMPONENT_VIDEO_ENCODE,
++ },
++ {
++ .name = "MJPEG",
++ .fourcc = V4L2_PIX_FMT_MJPEG,
++ .flags = V4L2_FMT_FLAG_COMPRESSED,
++ .mmal = MMAL_ENCODING_MJPEG,
++ .depth = 8,
++ .mmal_component = MMAL_COMPONENT_VIDEO_ENCODE,
++ },
++ {
++ .name = "4:2:2, packed, YVYU",
++ .fourcc = V4L2_PIX_FMT_YVYU,
++ .flags = 0,
++ .mmal = MMAL_ENCODING_YVYU,
++ .depth = 16,
++ .mmal_component = MMAL_COMPONENT_CAMERA,
++ },
++ {
++ .name = "4:2:2, packed, VYUY",
++ .fourcc = V4L2_PIX_FMT_VYUY,
++ .flags = 0,
++ .mmal = MMAL_ENCODING_VYUY,
++ .depth = 16,
++ .mmal_component = MMAL_COMPONENT_CAMERA,
++ },
++ {
++ .name = "4:2:2, packed, UYVY",
++ .fourcc = V4L2_PIX_FMT_UYVY,
++ .flags = 0,
++ .mmal = MMAL_ENCODING_UYVY,
++ .depth = 16,
++ .mmal_component = MMAL_COMPONENT_CAMERA,
++ },
++ {
++ .name = "4:2:0, packed, NV12",
++ .fourcc = V4L2_PIX_FMT_NV12,
++ .flags = 0,
++ .mmal = MMAL_ENCODING_NV12,
++ .depth = 12,
++ .mmal_component = MMAL_COMPONENT_CAMERA,
++ },
++ {
++ .name = "RGB24 (BE)",
++ .fourcc = V4L2_PIX_FMT_BGR24,
++ .flags = 0,
++ .mmal = MMAL_ENCODING_RGB24,
++ .depth = 24,
++ .mmal_component = MMAL_COMPONENT_CAMERA,
++ },
++ {
++ .name = "4:2:0, packed YVU",
++ .fourcc = V4L2_PIX_FMT_YVU420,
++ .flags = 0,
++ .mmal = MMAL_ENCODING_YV12,
++ .depth = 12,
++ .mmal_component = MMAL_COMPONENT_CAMERA,
++ },
++ {
++ .name = "4:2:0, packed, NV21",
++ .fourcc = V4L2_PIX_FMT_NV21,
++ .flags = 0,
++ .mmal = MMAL_ENCODING_NV21,
++ .depth = 12,
++ .mmal_component = MMAL_COMPONENT_CAMERA,
++ },
++ {
++ .name = "RGB32 (BE)",
++ .fourcc = V4L2_PIX_FMT_BGR32,
++ .flags = 0,
++ .mmal = MMAL_ENCODING_BGRA,
++ .depth = 32,
++ .mmal_component = MMAL_COMPONENT_CAMERA,
++ },
++};
++
++static struct mmal_fmt *get_format(struct v4l2_format *f)
++{
++ struct mmal_fmt *fmt;
++ unsigned int k;
++
++ for (k = 0; k < ARRAY_SIZE(formats); k++) {
++ fmt = &formats[k];
++ if (fmt->fourcc == f->fmt.pix.pixelformat)
++ break;
++ }
++
++ if (k == ARRAY_SIZE(formats))
++ return NULL;
++
++ return &formats[k];
++}
++
++/* ------------------------------------------------------------------
++ Videobuf queue operations
++ ------------------------------------------------------------------*/
++
++static int queue_setup(struct vb2_queue *vq, const struct v4l2_format *fmt,
++ unsigned int *nbuffers, unsigned int *nplanes,
++ unsigned int sizes[], void *alloc_ctxs[])
++{
++ struct bm2835_mmal_dev *dev = vb2_get_drv_priv(vq);
++ unsigned long size;
++
++ /* refuse queue setup if port is not configured */
++ if (dev->capture.port == NULL) {
++ v4l2_err(&dev->v4l2_dev,
++ "%s: capture port not configured\n", __func__);
++ return -EINVAL;
++ }
++
++ size = dev->capture.port->current_buffer.size;
++ if (size == 0) {
++ v4l2_err(&dev->v4l2_dev,
++ "%s: capture port buffer size is zero\n", __func__);
++ return -EINVAL;
++ }
++
++ if (*nbuffers < (dev->capture.port->current_buffer.num + 2))
++ *nbuffers = (dev->capture.port->current_buffer.num + 2);
++
++ *nplanes = 1;
++
++ sizes[0] = size;
++
++ /*
++ * videobuf2-vmalloc allocator is context-less so no need to set
++ * alloc_ctxs array.
++ */
++
++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, "%s: dev:%p\n",
++ __func__, dev);
++
++ return 0;
++}
++
++static int buffer_prepare(struct vb2_buffer *vb)
++{
++ struct bm2835_mmal_dev *dev = vb2_get_drv_priv(vb->vb2_queue);
++ unsigned long size;
++
++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, "%s: dev:%p\n",
++ __func__, dev);
++
++ BUG_ON(dev->capture.port == NULL);
++ BUG_ON(dev->capture.fmt == NULL);
++
++ size = dev->capture.stride * dev->capture.height;
++ if (vb2_plane_size(vb, 0) < size) {
++ v4l2_err(&dev->v4l2_dev,
++ "%s data will not fit into plane (%lu < %lu)\n",
++ __func__, vb2_plane_size(vb, 0), size);
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++static inline bool is_capturing(struct bm2835_mmal_dev *dev)
++{
++ return dev->capture.camera_port ==
++ &dev->
++ component[MMAL_COMPONENT_CAMERA]->output[MMAL_CAMERA_PORT_CAPTURE];
++}
++
++static void buffer_cb(struct vchiq_mmal_instance *instance,
++ struct vchiq_mmal_port *port,
++ int status,
++ struct mmal_buffer *buf,
++ unsigned long length, u32 mmal_flags, s64 dts, s64 pts)
++{
++ struct bm2835_mmal_dev *dev = port->cb_ctx;
++
++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
++ "%s: status:%d, buf:%p, length:%lu, flags %u, pts %lld\n",
++ __func__, status, buf, length, mmal_flags, pts);
++
++ if (status != 0) {
++ /* error in transfer */
++ if (buf != NULL) {
++ /* there was a buffer with the error so return it */
++ vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR);
++ }
++ return;
++ } else if (length == 0) {
++ /* stream ended */
++ if (buf != NULL) {
++ /* this should only ever happen if the port is
++ * disabled and there are buffers still queued
++ */
++ vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR);
++ pr_debug("Empty buffer");
++ } else if (dev->capture.frame_count) {
++ /* grab another frame */
++ if (is_capturing(dev)) {
++ pr_debug("Grab another frame");
++ vchiq_mmal_port_parameter_set(
++ instance,
++ dev->capture.
++ camera_port,
++ MMAL_PARAMETER_CAPTURE,
++ &dev->capture.
++ frame_count,
++ sizeof(dev->capture.frame_count));
++ }
++ } else {
++ /* signal frame completion */
++ complete(&dev->capture.frame_cmplt);
++ }
++ } else {
++ if (dev->capture.frame_count) {
++ if (dev->capture.vc_start_timestamp != -1 &&
++ pts != 0) {
++ s64 runtime_us = pts -
++ dev->capture.vc_start_timestamp;
++ u32 div = 0;
++ u32 rem = 0;
++
++ div =
++ div_u64_rem(runtime_us, USEC_PER_SEC, &rem);
++ buf->vb.v4l2_buf.timestamp.tv_sec =
++ dev->capture.kernel_start_ts.tv_sec - 1 +
++ div;
++ buf->vb.v4l2_buf.timestamp.tv_usec =
++ dev->capture.kernel_start_ts.tv_usec + rem;
++
++ if (buf->vb.v4l2_buf.timestamp.tv_usec >=
++ USEC_PER_SEC) {
++ buf->vb.v4l2_buf.timestamp.tv_sec++;
++ buf->vb.v4l2_buf.timestamp.tv_usec -=
++ USEC_PER_SEC;
++ }
++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
++ "Convert start time %d.%06d and %llu "
++ "with offset %llu to %d.%06d\n",
++ (int)dev->capture.kernel_start_ts.
++ tv_sec,
++ (int)dev->capture.kernel_start_ts.
++ tv_usec,
++ dev->capture.vc_start_timestamp, pts,
++ (int)buf->vb.v4l2_buf.timestamp.tv_sec,
++ (int)buf->vb.v4l2_buf.timestamp.
++ tv_usec);
++ } else {
++ v4l2_get_timestamp(&buf->vb.v4l2_buf.timestamp);
++ }
++
++ vb2_set_plane_payload(&buf->vb, 0, length);
++ vb2_buffer_done(&buf->vb, VB2_BUF_STATE_DONE);
++
++ if (mmal_flags & MMAL_BUFFER_HEADER_FLAG_EOS &&
++ is_capturing(dev)) {
++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
++ "Grab another frame as buffer has EOS");
++ vchiq_mmal_port_parameter_set(
++ instance,
++ dev->capture.
++ camera_port,
++ MMAL_PARAMETER_CAPTURE,
++ &dev->capture.
++ frame_count,
++ sizeof(dev->capture.frame_count));
++ }
++ } else {
++ /* signal frame completion */
++ complete(&dev->capture.frame_cmplt);
++ }
++ }
++}
++
++static int enable_camera(struct bm2835_mmal_dev *dev)
++{
++ int ret;
++ if (!dev->camera_use_count) {
++ ret = vchiq_mmal_component_enable(
++ dev->instance,
++ dev->component[MMAL_COMPONENT_CAMERA]);
++ if (ret < 0) {
++ v4l2_err(&dev->v4l2_dev,
++ "Failed enabling camera, ret %d\n", ret);
++ return -EINVAL;
++ }
++ }
++ dev->camera_use_count++;
++ v4l2_dbg(1, bcm2835_v4l2_debug,
++ &dev->v4l2_dev, "enabled camera (refcount %d)\n",
++ dev->camera_use_count);
++ return 0;
++}
++
++static int disable_camera(struct bm2835_mmal_dev *dev)
++{
++ int ret;
++ if (!dev->camera_use_count) {
++ v4l2_err(&dev->v4l2_dev,
++ "Disabled the camera when already disabled\n");
++ return -EINVAL;
++ }
++ dev->camera_use_count--;
++ if (!dev->camera_use_count) {
++ unsigned int i = 0xFFFFFFFF;
++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
++ "Disabling camera\n");
++ ret =
++ vchiq_mmal_component_disable(
++ dev->instance,
++ dev->component[MMAL_COMPONENT_CAMERA]);
++ if (ret < 0) {
++ v4l2_err(&dev->v4l2_dev,
++ "Failed disabling camera, ret %d\n", ret);
++ return -EINVAL;
++ }
++ vchiq_mmal_port_parameter_set(
++ dev->instance,
++ &dev->component[MMAL_COMPONENT_CAMERA]->control,
++ MMAL_PARAMETER_CAMERA_NUM, &i,
++ sizeof(i));
++ }
++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
++ "Camera refcount now %d\n", dev->camera_use_count);
++ return 0;
++}
++
++static void buffer_queue(struct vb2_buffer *vb)
++{
++ struct bm2835_mmal_dev *dev = vb2_get_drv_priv(vb->vb2_queue);
++ struct mmal_buffer *buf = container_of(vb, struct mmal_buffer, vb);
++ int ret;
++
++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
++ "%s: dev:%p buf:%p\n", __func__, dev, buf);
++
++ buf->buffer = vb2_plane_vaddr(&buf->vb, 0);
++ buf->buffer_size = vb2_plane_size(&buf->vb, 0);
++
++ ret = vchiq_mmal_submit_buffer(dev->instance, dev->capture.port, buf);
++ if (ret < 0)
++ v4l2_err(&dev->v4l2_dev, "%s: error submitting buffer\n",
++ __func__);
++}
++
++static int start_streaming(struct vb2_queue *vq, unsigned int count)
++{
++ struct bm2835_mmal_dev *dev = vb2_get_drv_priv(vq);
++ int ret;
++ int parameter_size;
++
++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, "%s: dev:%p\n",
++ __func__, dev);
++
++ /* ensure a format has actually been set */
++ if (dev->capture.port == NULL)
++ return -EINVAL;
++
++ if (enable_camera(dev) < 0) {
++ v4l2_err(&dev->v4l2_dev, "Failed to enable camera\n");
++ return -EINVAL;
++ }
++
++ /*init_completion(&dev->capture.frame_cmplt); */
++
++ /* enable frame capture */
++ dev->capture.frame_count = 1;
++
++ /* if the preview is not already running, wait for a few frames for AGC
++ * to settle down.
++ */
++ if (!dev->component[MMAL_COMPONENT_PREVIEW]->enabled)
++ msleep(300);
++
++ /* enable the connection from camera to encoder (if applicable) */
++ if (dev->capture.camera_port != dev->capture.port
++ && dev->capture.camera_port) {
++ ret = vchiq_mmal_port_enable(dev->instance,
++ dev->capture.camera_port, NULL);
++ if (ret) {
++ v4l2_err(&dev->v4l2_dev,
++ "Failed to enable encode tunnel - error %d\n",
++ ret);
++ return -1;
++ }
++ }
++
++ /* Get VC timestamp at this point in time */
++ parameter_size = sizeof(dev->capture.vc_start_timestamp);
++ if (vchiq_mmal_port_parameter_get(dev->instance,
++ dev->capture.camera_port,
++ MMAL_PARAMETER_SYSTEM_TIME,
++ &dev->capture.vc_start_timestamp,
++ &parameter_size)) {
++ v4l2_err(&dev->v4l2_dev,
++ "Failed to get VC start time - update your VC f/w\n");
++
++ /* Flag to indicate just to rely on kernel timestamps */
++ dev->capture.vc_start_timestamp = -1;
++ } else
++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
++ "Start time %lld size %d\n",
++ dev->capture.vc_start_timestamp, parameter_size);
++
++ v4l2_get_timestamp(&dev->capture.kernel_start_ts);
++
++ /* enable the camera port */
++ dev->capture.port->cb_ctx = dev;
++ ret =
++ vchiq_mmal_port_enable(dev->instance, dev->capture.port, buffer_cb);
++ if (ret) {
++ v4l2_err(&dev->v4l2_dev,
++ "Failed to enable capture port - error %d. "
++ "Disabling camera port again\n", ret);
++
++ vchiq_mmal_port_disable(dev->instance,
++ dev->capture.camera_port);
++ if (disable_camera(dev) < 0) {
++ v4l2_err(&dev->v4l2_dev, "Failed to disable camera\n");
++ return -EINVAL;
++ }
++ return -1;
++ }
++
++ /* capture the first frame */
++ vchiq_mmal_port_parameter_set(dev->instance,
++ dev->capture.camera_port,
++ MMAL_PARAMETER_CAPTURE,
++ &dev->capture.frame_count,
++ sizeof(dev->capture.frame_count));
++ return 0;
++}
++
++/* abort streaming and wait for last buffer */
++static void stop_streaming(struct vb2_queue *vq)
++{
++ int ret;
++ struct bm2835_mmal_dev *dev = vb2_get_drv_priv(vq);
++
++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, "%s: dev:%p\n",
++ __func__, dev);
++
++ init_completion(&dev->capture.frame_cmplt);
++ dev->capture.frame_count = 0;
++
++ /* ensure a format has actually been set */
++ if (dev->capture.port == NULL) {
++ v4l2_err(&dev->v4l2_dev,
++ "no capture port - stream not started?\n");
++ return;
++ }
++
++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, "stopping capturing\n");
++
++ /* stop capturing frames */
++ vchiq_mmal_port_parameter_set(dev->instance,
++ dev->capture.camera_port,
++ MMAL_PARAMETER_CAPTURE,
++ &dev->capture.frame_count,
++ sizeof(dev->capture.frame_count));
++
++ /* wait for last frame to complete */
++ ret = wait_for_completion_timeout(&dev->capture.frame_cmplt, HZ);
++ if (ret <= 0)
++ v4l2_err(&dev->v4l2_dev,
++ "error %d waiting for frame completion\n", ret);
++
++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
++ "disabling connection\n");
++
++ /* disable the connection from camera to encoder */
++ ret = vchiq_mmal_port_disable(dev->instance, dev->capture.camera_port);
++ if (!ret && dev->capture.camera_port != dev->capture.port) {
++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
++ "disabling port\n");
++ ret = vchiq_mmal_port_disable(dev->instance, dev->capture.port);
++ } else if (dev->capture.camera_port != dev->capture.port) {
++ v4l2_err(&dev->v4l2_dev, "port_disable failed, error %d\n",
++ ret);
++ }
++
++ if (disable_camera(dev) < 0)
++ v4l2_err(&dev->v4l2_dev, "Failed to disable camera\n");
++}
++
++static void bm2835_mmal_lock(struct vb2_queue *vq)
++{
++ struct bm2835_mmal_dev *dev = vb2_get_drv_priv(vq);
++ mutex_lock(&dev->mutex);
++}
++
++static void bm2835_mmal_unlock(struct vb2_queue *vq)
++{
++ struct bm2835_mmal_dev *dev = vb2_get_drv_priv(vq);
++ mutex_unlock(&dev->mutex);
++}
++
++static struct vb2_ops bm2835_mmal_video_qops = {
++ .queue_setup = queue_setup,
++ .buf_prepare = buffer_prepare,
++ .buf_queue = buffer_queue,
++ .start_streaming = start_streaming,
++ .stop_streaming = stop_streaming,
++ .wait_prepare = bm2835_mmal_unlock,
++ .wait_finish = bm2835_mmal_lock,
++};
++
++/* ------------------------------------------------------------------
++ IOCTL operations
++ ------------------------------------------------------------------*/
++
++/* overlay ioctl */
++static int vidioc_enum_fmt_vid_overlay(struct file *file, void *priv,
++ struct v4l2_fmtdesc *f)
++{
++ struct mmal_fmt *fmt;
++
++ if (f->index >= ARRAY_SIZE(formats))
++ return -EINVAL;
++
++ fmt = &formats[f->index];
++
++ strlcpy(f->description, fmt->name, sizeof(f->description));
++ f->pixelformat = fmt->fourcc;
++ f->flags = fmt->flags;
++
++ return 0;
++}
++
++static int vidioc_g_fmt_vid_overlay(struct file *file, void *priv,
++ struct v4l2_format *f)
++{
++ struct bm2835_mmal_dev *dev = video_drvdata(file);
++
++ f->fmt.win = dev->overlay;
++
++ return 0;
++}
++
++static int vidioc_try_fmt_vid_overlay(struct file *file, void *priv,
++ struct v4l2_format *f)
++{
++ /* Only support one format so get the current one. */
++ vidioc_g_fmt_vid_overlay(file, priv, f);
++
++ /* todo: allow the size and/or offset to be changed. */
++ return 0;
++}
++
++static int vidioc_s_fmt_vid_overlay(struct file *file, void *priv,
++ struct v4l2_format *f)
++{
++ struct bm2835_mmal_dev *dev = video_drvdata(file);
++
++ vidioc_try_fmt_vid_overlay(file, priv, f);
++
++ dev->overlay = f->fmt.win;
++
++ /* todo: program the preview port parameters */
++ return 0;
++}
++
++static int vidioc_overlay(struct file *file, void *f, unsigned int on)
++{
++ int ret;
++ struct bm2835_mmal_dev *dev = video_drvdata(file);
++ struct vchiq_mmal_port *src;
++ struct vchiq_mmal_port *dst;
++ struct mmal_parameter_displayregion prev_config = {
++ .set = MMAL_DISPLAY_SET_LAYER | MMAL_DISPLAY_SET_ALPHA |
++ MMAL_DISPLAY_SET_DEST_RECT | MMAL_DISPLAY_SET_FULLSCREEN,
++ .layer = PREVIEW_LAYER,
++ .alpha = 255,
++ .fullscreen = 0,
++ .dest_rect = {
++ .x = dev->overlay.w.left,
++ .y = dev->overlay.w.top,
++ .width = dev->overlay.w.width,
++ .height = dev->overlay.w.height,
++ },
++ };
++
++ if ((on && dev->component[MMAL_COMPONENT_PREVIEW]->enabled) ||
++ (!on && !dev->component[MMAL_COMPONENT_PREVIEW]->enabled))
++ return 0; /* already in requested state */
++
++ src =
++ &dev->component[MMAL_COMPONENT_CAMERA]->
++ output[MMAL_CAMERA_PORT_PREVIEW];
++
++ if (!on) {
++ /* disconnect preview ports and disable component */
++ ret = vchiq_mmal_port_disable(dev->instance, src);
++ if (!ret)
++ ret =
++ vchiq_mmal_port_connect_tunnel(dev->instance, src,
++ NULL);
++ if (ret >= 0)
++ ret = vchiq_mmal_component_disable(
++ dev->instance,
++ dev->component[MMAL_COMPONENT_PREVIEW]);
++
++ disable_camera(dev);
++ return ret;
++ }
++
++ /* set preview port format and connect it to output */
++ dst = &dev->component[MMAL_COMPONENT_PREVIEW]->input[0];
++
++ ret = vchiq_mmal_port_set_format(dev->instance, src);
++ if (ret < 0)
++ goto error;
++
++ ret = vchiq_mmal_port_parameter_set(dev->instance, dst,
++ MMAL_PARAMETER_DISPLAYREGION,
++ &prev_config, sizeof(prev_config));
++ if (ret < 0)
++ goto error;
++
++ if (enable_camera(dev) < 0)
++ goto error;
++
++ ret = vchiq_mmal_component_enable(
++ dev->instance,
++ dev->component[MMAL_COMPONENT_PREVIEW]);
++ if (ret < 0)
++ goto error;
++
++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, "connecting %p to %p\n",
++ src, dst);
++ ret = vchiq_mmal_port_connect_tunnel(dev->instance, src, dst);
++ if (!ret)
++ ret = vchiq_mmal_port_enable(dev->instance, src, NULL);
++error:
++ return ret;
++}
++
++static int vidioc_g_fbuf(struct file *file, void *fh,
++ struct v4l2_framebuffer *a)
++{
++ /* The video overlay must stay within the framebuffer and can't be
++ positioned independently. */
++ struct bm2835_mmal_dev *dev = video_drvdata(file);
++ struct vchiq_mmal_port *preview_port =
++ &dev->component[MMAL_COMPONENT_CAMERA]->
++ output[MMAL_CAMERA_PORT_PREVIEW];
++ a->flags = V4L2_FBUF_FLAG_OVERLAY;
++ a->fmt.width = preview_port->es.video.width;
++ a->fmt.height = preview_port->es.video.height;
++ a->fmt.pixelformat = V4L2_PIX_FMT_YUV420;
++ a->fmt.bytesperline = (preview_port->es.video.width * 3)>>1;
++ a->fmt.sizeimage = (preview_port->es.video.width *
++ preview_port->es.video.height * 3)>>1;
++ a->fmt.colorspace = V4L2_COLORSPACE_SMPTE170M;
++
++ return 0;
++}
++
++/* input ioctls */
++static int vidioc_enum_input(struct file *file, void *priv,
++ struct v4l2_input *inp)
++{
++ /* only a single camera input */
++ if (inp->index != 0)
++ return -EINVAL;
++
++ inp->type = V4L2_INPUT_TYPE_CAMERA;
++ sprintf(inp->name, "Camera %u", inp->index);
++ return 0;
++}
++
++static int vidioc_g_input(struct file *file, void *priv, unsigned int *i)
++{
++ *i = 0;
++ return 0;
++}
++
++static int vidioc_s_input(struct file *file, void *priv, unsigned int i)
++{
++ if (i != 0)
++ return -EINVAL;
++
++ return 0;
++}
++
++/* capture ioctls */
++static int vidioc_querycap(struct file *file, void *priv,
++ struct v4l2_capability *cap)
++{
++ struct bm2835_mmal_dev *dev = video_drvdata(file);
++ u32 major;
++ u32 minor;
++
++ vchiq_mmal_version(dev->instance, &major, &minor);
++
++ strcpy(cap->driver, "bm2835 mmal");
++ snprintf(cap->card, sizeof(cap->card), "mmal service %d.%d",
++ major, minor);
++
++ snprintf(cap->bus_info, sizeof(cap->bus_info),
++ "platform:%s", dev->v4l2_dev.name);
++ cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_VIDEO_OVERLAY |
++ V4L2_CAP_STREAMING | V4L2_CAP_READWRITE;
++ cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
++
++ return 0;
++}
++
++static int vidioc_enum_fmt_vid_cap(struct file *file, void *priv,
++ struct v4l2_fmtdesc *f)
++{
++ struct mmal_fmt *fmt;
++
++ if (f->index >= ARRAY_SIZE(formats))
++ return -EINVAL;
++
++ fmt = &formats[f->index];
++
++ strlcpy(f->description, fmt->name, sizeof(f->description));
++ f->pixelformat = fmt->fourcc;
++ f->flags = fmt->flags;
++
++ return 0;
++}
++
++static int vidioc_g_fmt_vid_cap(struct file *file, void *priv,
++ struct v4l2_format *f)
++{
++ struct bm2835_mmal_dev *dev = video_drvdata(file);
++
++ f->fmt.pix.width = dev->capture.width;
++ f->fmt.pix.height = dev->capture.height;
++ f->fmt.pix.field = V4L2_FIELD_NONE;
++ f->fmt.pix.pixelformat = dev->capture.fmt->fourcc;
++ f->fmt.pix.bytesperline = dev->capture.stride;
++ f->fmt.pix.sizeimage = dev->capture.buffersize;
++
++ if (dev->capture.fmt->fourcc == V4L2_PIX_FMT_RGB24)
++ f->fmt.pix.colorspace = V4L2_COLORSPACE_SRGB;
++ else if (dev->capture.fmt->fourcc == V4L2_PIX_FMT_JPEG)
++ f->fmt.pix.colorspace = V4L2_COLORSPACE_JPEG;
++ else
++ f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M;
++ f->fmt.pix.priv = 0;
++
++ v4l2_dump_pix_format(1, bcm2835_v4l2_debug, &dev->v4l2_dev, &f->fmt.pix,
++ __func__);
++ return 0;
++}
++
++static int vidioc_try_fmt_vid_cap(struct file *file, void *priv,
++ struct v4l2_format *f)
++{
++ struct bm2835_mmal_dev *dev = video_drvdata(file);
++ struct mmal_fmt *mfmt;
++
++ mfmt = get_format(f);
++ if (!mfmt) {
++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
++ "Fourcc format (0x%08x) unknown.\n",
++ f->fmt.pix.pixelformat);
++ f->fmt.pix.pixelformat = formats[0].fourcc;
++ mfmt = get_format(f);
++ }
++
++ f->fmt.pix.field = V4L2_FIELD_NONE;
++
++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
++ "Clipping/aligning %dx%d format %08X\n",
++ f->fmt.pix.width, f->fmt.pix.height, f->fmt.pix.pixelformat);
++
++ v4l_bound_align_image(&f->fmt.pix.width, MIN_WIDTH, MAX_WIDTH, 1,
++ &f->fmt.pix.height, MIN_HEIGHT, MAX_HEIGHT, 1, 0);
++ f->fmt.pix.bytesperline = (f->fmt.pix.width * mfmt->depth)>>3;
++
++ /* Image buffer has to be padded to allow for alignment, even though
++ * we then remove that padding before delivering the buffer.
++ */
++ f->fmt.pix.sizeimage = ((f->fmt.pix.height+15)&~15) *
++ (((f->fmt.pix.width+31)&~31) * mfmt->depth) >> 3;
++
++ if ((mfmt->flags & V4L2_FMT_FLAG_COMPRESSED) &&
++ f->fmt.pix.sizeimage < MIN_BUFFER_SIZE)
++ f->fmt.pix.sizeimage = MIN_BUFFER_SIZE;
++
++ if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_RGB24)
++ f->fmt.pix.colorspace = V4L2_COLORSPACE_SRGB;
++ else if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_JPEG)
++ f->fmt.pix.colorspace = V4L2_COLORSPACE_JPEG;
++ else
++ f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M;
++ f->fmt.pix.priv = 0;
++
++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
++ "Now %dx%d format %08X\n",
++ f->fmt.pix.width, f->fmt.pix.height, f->fmt.pix.pixelformat);
++
++ v4l2_dump_pix_format(1, bcm2835_v4l2_debug, &dev->v4l2_dev, &f->fmt.pix,
++ __func__);
++ return 0;
++}
++
++static int mmal_setup_components(struct bm2835_mmal_dev *dev,
++ struct v4l2_format *f)
++{
++ int ret;
++ struct vchiq_mmal_port *port = NULL, *camera_port = NULL;
++ struct vchiq_mmal_component *encode_component = NULL;
++ struct mmal_fmt *mfmt = get_format(f);
++
++ BUG_ON(!mfmt);
++
++ if (dev->capture.encode_component) {
++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
++ "vid_cap - disconnect previous tunnel\n");
++
++ /* Disconnect any previous connection */
++ vchiq_mmal_port_connect_tunnel(dev->instance,
++ dev->capture.camera_port, NULL);
++ dev->capture.camera_port = NULL;
++ ret = vchiq_mmal_component_disable(dev->instance,
++ dev->capture.
++ encode_component);
++ if (ret)
++ v4l2_err(&dev->v4l2_dev,
++ "Failed to disable encode component %d\n",
++ ret);
++
++ dev->capture.encode_component = NULL;
++ }
++ /* format dependant port setup */
++ switch (mfmt->mmal_component) {
++ case MMAL_COMPONENT_CAMERA:
++ /* Make a further decision on port based on resolution */
++ if (f->fmt.pix.width <= max_video_width
++ && f->fmt.pix.height <= max_video_height)
++ camera_port = port =
++ &dev->component[MMAL_COMPONENT_CAMERA]->
++ output[MMAL_CAMERA_PORT_VIDEO];
++ else
++ camera_port = port =
++ &dev->component[MMAL_COMPONENT_CAMERA]->
++ output[MMAL_CAMERA_PORT_CAPTURE];
++ break;
++ case MMAL_COMPONENT_IMAGE_ENCODE:
++ encode_component = dev->component[MMAL_COMPONENT_IMAGE_ENCODE];
++ port = &dev->component[MMAL_COMPONENT_IMAGE_ENCODE]->output[0];
++ camera_port =
++ &dev->component[MMAL_COMPONENT_CAMERA]->
++ output[MMAL_CAMERA_PORT_CAPTURE];
++ break;
++ case MMAL_COMPONENT_VIDEO_ENCODE:
++ encode_component = dev->component[MMAL_COMPONENT_VIDEO_ENCODE];
++ port = &dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->output[0];
++ camera_port =
++ &dev->component[MMAL_COMPONENT_CAMERA]->
++ output[MMAL_CAMERA_PORT_VIDEO];
++ break;
++ default:
++ break;
++ }
++
++ if (!port)
++ return -EINVAL;
++
++ if (encode_component)
++ camera_port->format.encoding = MMAL_ENCODING_OPAQUE;
++ else
++ camera_port->format.encoding = mfmt->mmal;
++
++ camera_port->format.encoding_variant = 0;
++ camera_port->es.video.width = f->fmt.pix.width;
++ camera_port->es.video.height = f->fmt.pix.height;
++ camera_port->es.video.crop.x = 0;
++ camera_port->es.video.crop.y = 0;
++ camera_port->es.video.crop.width = f->fmt.pix.width;
++ camera_port->es.video.crop.height = f->fmt.pix.height;
++ camera_port->es.video.frame_rate.num = 0;
++ camera_port->es.video.frame_rate.den = 1;
++ camera_port->es.video.color_space = MMAL_COLOR_SPACE_JPEG_JFIF;
++
++ ret = vchiq_mmal_port_set_format(dev->instance, camera_port);
++
++ if (!ret
++ && camera_port ==
++ &dev->component[MMAL_COMPONENT_CAMERA]->
++ output[MMAL_CAMERA_PORT_VIDEO]) {
++ bool overlay_enabled =
++ !!dev->component[MMAL_COMPONENT_PREVIEW]->enabled;
++ struct vchiq_mmal_port *preview_port =
++ &dev->component[MMAL_COMPONENT_CAMERA]->
++ output[MMAL_CAMERA_PORT_PREVIEW];
++ /* Preview and encode ports need to match on resolution */
++ if (overlay_enabled) {
++ /* Need to disable the overlay before we can update
++ * the resolution
++ */
++ ret =
++ vchiq_mmal_port_disable(dev->instance,
++ preview_port);
++ if (!ret)
++ ret =
++ vchiq_mmal_port_connect_tunnel(
++ dev->instance,
++ preview_port,
++ NULL);
++ }
++ preview_port->es.video.width = f->fmt.pix.width;
++ preview_port->es.video.height = f->fmt.pix.height;
++ preview_port->es.video.crop.x = 0;
++ preview_port->es.video.crop.y = 0;
++ preview_port->es.video.crop.width = f->fmt.pix.width;
++ preview_port->es.video.crop.height = f->fmt.pix.height;
++ preview_port->es.video.frame_rate.num =
++ dev->capture.timeperframe.denominator;
++ preview_port->es.video.frame_rate.den =
++ dev->capture.timeperframe.numerator;
++ ret = vchiq_mmal_port_set_format(dev->instance, preview_port);
++ if (overlay_enabled) {
++ ret = vchiq_mmal_port_connect_tunnel(
++ dev->instance,
++ preview_port,
++ &dev->component[MMAL_COMPONENT_PREVIEW]->input[0]);
++ if (!ret)
++ ret = vchiq_mmal_port_enable(dev->instance,
++ preview_port,
++ NULL);
++ }
++ }
++
++ if (ret) {
++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
++ "%s failed to set format %dx%d %08X\n", __func__,
++ f->fmt.pix.width, f->fmt.pix.height,
++ f->fmt.pix.pixelformat);
++ /* ensure capture is not going to be tried */
++ dev->capture.port = NULL;
++ } else {
++ if (encode_component) {
++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
++ "vid_cap - set up encode comp\n");
++
++ /* configure buffering */
++ camera_port->current_buffer.size =
++ camera_port->recommended_buffer.size;
++ camera_port->current_buffer.num =
++ camera_port->recommended_buffer.num;
++
++ ret =
++ vchiq_mmal_port_connect_tunnel(
++ dev->instance,
++ camera_port,
++ &encode_component->input[0]);
++ if (ret) {
++ v4l2_dbg(1, bcm2835_v4l2_debug,
++ &dev->v4l2_dev,
++ "%s failed to create connection\n",
++ __func__);
++ /* ensure capture is not going to be tried */
++ dev->capture.port = NULL;
++ } else {
++ port->es.video.width = f->fmt.pix.width;
++ port->es.video.height = f->fmt.pix.height;
++ port->es.video.crop.x = 0;
++ port->es.video.crop.y = 0;
++ port->es.video.crop.width = f->fmt.pix.width;
++ port->es.video.crop.height = f->fmt.pix.height;
++ port->es.video.frame_rate.num =
++ dev->capture.timeperframe.denominator;
++ port->es.video.frame_rate.den =
++ dev->capture.timeperframe.numerator;
++
++ port->format.encoding = mfmt->mmal;
++ port->format.encoding_variant = 0;
++ /* Set any encoding specific parameters */
++ switch (mfmt->mmal_component) {
++ case MMAL_COMPONENT_VIDEO_ENCODE:
++ port->format.bitrate =
++ dev->capture.encode_bitrate;
++ break;
++ case MMAL_COMPONENT_IMAGE_ENCODE:
++ /* Could set EXIF parameters here */
++ break;
++ default:
++ break;
++ }
++ ret = vchiq_mmal_port_set_format(dev->instance,
++ port);
++ if (ret)
++ v4l2_dbg(1, bcm2835_v4l2_debug,
++ &dev->v4l2_dev,
++ "%s failed to set format %dx%d fmt %08X\n",
++ __func__,
++ f->fmt.pix.width,
++ f->fmt.pix.height,
++ f->fmt.pix.pixelformat
++ );
++ }
++
++ if (!ret) {
++ ret = vchiq_mmal_component_enable(
++ dev->instance,
++ encode_component);
++ if (ret) {
++ v4l2_dbg(1, bcm2835_v4l2_debug,
++ &dev->v4l2_dev,
++ "%s Failed to enable encode components\n",
++ __func__);
++ }
++ }
++ if (!ret) {
++ /* configure buffering */
++ port->current_buffer.num = 1;
++ port->current_buffer.size =
++ f->fmt.pix.sizeimage;
++ if (port->format.encoding ==
++ MMAL_ENCODING_JPEG) {
++ v4l2_dbg(1, bcm2835_v4l2_debug,
++ &dev->v4l2_dev,
++ "JPG - buf size now %d was %d\n",
++ f->fmt.pix.sizeimage,
++ port->current_buffer.size);
++ port->current_buffer.size =
++ (f->fmt.pix.sizeimage <
++ (100 << 10))
++ ? (100 << 10) : f->fmt.pix.
++ sizeimage;
++ }
++ v4l2_dbg(1, bcm2835_v4l2_debug,
++ &dev->v4l2_dev,
++ "vid_cap - cur_buf.size set to %d\n",
++ f->fmt.pix.sizeimage);
++ port->current_buffer.alignment = 0;
++ }
++ } else {
++ /* configure buffering */
++ camera_port->current_buffer.num = 1;
++ camera_port->current_buffer.size = f->fmt.pix.sizeimage;
++ camera_port->current_buffer.alignment = 0;
++ }
++
++ if (!ret) {
++ dev->capture.fmt = mfmt;
++ dev->capture.stride = f->fmt.pix.bytesperline;
++ dev->capture.width = camera_port->es.video.crop.width;
++ dev->capture.height = camera_port->es.video.crop.height;
++ dev->capture.buffersize = port->current_buffer.size;
++
++ /* select port for capture */
++ dev->capture.port = port;
++ dev->capture.camera_port = camera_port;
++ dev->capture.encode_component = encode_component;
++ v4l2_dbg(1, bcm2835_v4l2_debug,
++ &dev->v4l2_dev,
++ "Set dev->capture.fmt %08X, %dx%d, stride %d, size %d",
++ port->format.encoding,
++ dev->capture.width, dev->capture.height,
++ dev->capture.stride, dev->capture.buffersize);
++ }
++ }
++
++ /* todo: Need to convert the vchiq/mmal error into a v4l2 error. */
++ return ret;
++}
++
++static int vidioc_s_fmt_vid_cap(struct file *file, void *priv,
++ struct v4l2_format *f)
++{
++ int ret;
++ struct bm2835_mmal_dev *dev = video_drvdata(file);
++ struct mmal_fmt *mfmt;
++
++ /* try the format to set valid parameters */
++ ret = vidioc_try_fmt_vid_cap(file, priv, f);
++ if (ret) {
++ v4l2_err(&dev->v4l2_dev,
++ "vid_cap - vidioc_try_fmt_vid_cap failed\n");
++ return ret;
++ }
++
++ /* if a capture is running refuse to set format */
++ if (vb2_is_busy(&dev->capture.vb_vidq)) {
++ v4l2_info(&dev->v4l2_dev, "%s device busy\n", __func__);
++ return -EBUSY;
++ }
++
++ /* If the format is unsupported v4l2 says we should switch to
++ * a supported one and not return an error. */
++ mfmt = get_format(f);
++ if (!mfmt) {
++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
++ "Fourcc format (0x%08x) unknown.\n",
++ f->fmt.pix.pixelformat);
++ f->fmt.pix.pixelformat = formats[0].fourcc;
++ mfmt = get_format(f);
++ }
++
++ ret = mmal_setup_components(dev, f);
++ if (ret != 0) {
++ v4l2_err(&dev->v4l2_dev,
++ "%s: failed to setup mmal components: %d\n",
++ __func__, ret);
++ ret = -EINVAL;
++ }
++
++ return ret;
++}
++
++int vidioc_enum_framesizes(struct file *file, void *fh,
++ struct v4l2_frmsizeenum *fsize)
++{
++ static const struct v4l2_frmsize_stepwise sizes = {
++ MIN_WIDTH, MAX_WIDTH, 2,
++ MIN_HEIGHT, MAX_HEIGHT, 2
++ };
++ int i;
++
++ if (fsize->index)
++ return -EINVAL;
++ for (i = 0; i < ARRAY_SIZE(formats); i++)
++ if (formats[i].fourcc == fsize->pixel_format)
++ break;
++ if (i == ARRAY_SIZE(formats))
++ return -EINVAL;
++ fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE;
++ fsize->stepwise = sizes;
++ return 0;
++}
++
++/* timeperframe is arbitrary and continous */
++static int vidioc_enum_frameintervals(struct file *file, void *priv,
++ struct v4l2_frmivalenum *fival)
++{
++ int i;
++
++ if (fival->index)
++ return -EINVAL;
++
++ for (i = 0; i < ARRAY_SIZE(formats); i++)
++ if (formats[i].fourcc == fival->pixel_format)
++ break;
++ if (i == ARRAY_SIZE(formats))
++ return -EINVAL;
++
++ /* regarding width & height - we support any within range */
++ if (fival->width < MIN_WIDTH || fival->width > MAX_WIDTH ||
++ fival->height < MIN_HEIGHT || fival->height > MAX_HEIGHT)
++ return -EINVAL;
++
++ fival->type = V4L2_FRMIVAL_TYPE_CONTINUOUS;
++
++ /* fill in stepwise (step=1.0 is requred by V4L2 spec) */
++ fival->stepwise.min = tpf_min;
++ fival->stepwise.max = tpf_max;
++ fival->stepwise.step = (struct v4l2_fract) {1, 1};
++
++ return 0;
++}
++
++static int vidioc_g_parm(struct file *file, void *priv,
++ struct v4l2_streamparm *parm)
++{
++ struct bm2835_mmal_dev *dev = video_drvdata(file);
++
++ if (parm->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
++ return -EINVAL;
++
++ parm->parm.capture.capability = V4L2_CAP_TIMEPERFRAME;
++ parm->parm.capture.timeperframe = dev->capture.timeperframe;
++ parm->parm.capture.readbuffers = 1;
++ return 0;
++}
++
++#define FRACT_CMP(a, OP, b) \
++ ((u64)(a).numerator * (b).denominator OP \
++ (u64)(b).numerator * (a).denominator)
++
++static int vidioc_s_parm(struct file *file, void *priv,
++ struct v4l2_streamparm *parm)
++{
++ struct bm2835_mmal_dev *dev = video_drvdata(file);
++ struct v4l2_fract tpf;
++ struct mmal_parameter_rational fps_param;
++
++ if (parm->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
++ return -EINVAL;
++
++ tpf = parm->parm.capture.timeperframe;
++
++ /* tpf: {*, 0} resets timing; clip to [min, max]*/
++ tpf = tpf.denominator ? tpf : tpf_default;
++ tpf = FRACT_CMP(tpf, <, tpf_min) ? tpf_min : tpf;
++ tpf = FRACT_CMP(tpf, >, tpf_max) ? tpf_max : tpf;
++
++ dev->capture.timeperframe = tpf;
++ parm->parm.capture.timeperframe = tpf;
++ parm->parm.capture.readbuffers = 1;
++
++ fps_param.num = 0; /* Select variable fps, and then use
++ * FPS_RANGE to select the actual limits.
++ */
++ fps_param.den = 1;
++ set_framerate_params(dev);
++
++ return 0;
++}
++
++static const struct v4l2_ioctl_ops camera0_ioctl_ops = {
++ /* overlay */
++ .vidioc_enum_fmt_vid_overlay = vidioc_enum_fmt_vid_overlay,
++ .vidioc_g_fmt_vid_overlay = vidioc_g_fmt_vid_overlay,
++ .vidioc_try_fmt_vid_overlay = vidioc_try_fmt_vid_overlay,
++ .vidioc_s_fmt_vid_overlay = vidioc_s_fmt_vid_overlay,
++ .vidioc_overlay = vidioc_overlay,
++ .vidioc_g_fbuf = vidioc_g_fbuf,
++
++ /* inputs */
++ .vidioc_enum_input = vidioc_enum_input,
++ .vidioc_g_input = vidioc_g_input,
++ .vidioc_s_input = vidioc_s_input,
++
++ /* capture */
++ .vidioc_querycap = vidioc_querycap,
++ .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
++ .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap,
++ .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap,
++ .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap,
++
++ /* buffer management */
++ .vidioc_reqbufs = vb2_ioctl_reqbufs,
++ .vidioc_create_bufs = vb2_ioctl_create_bufs,
++ .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
++ .vidioc_querybuf = vb2_ioctl_querybuf,
++ .vidioc_qbuf = vb2_ioctl_qbuf,
++ .vidioc_dqbuf = vb2_ioctl_dqbuf,
++ .vidioc_enum_framesizes = vidioc_enum_framesizes,
++ .vidioc_enum_frameintervals = vidioc_enum_frameintervals,
++ .vidioc_g_parm = vidioc_g_parm,
++ .vidioc_s_parm = vidioc_s_parm,
++ .vidioc_streamon = vb2_ioctl_streamon,
++ .vidioc_streamoff = vb2_ioctl_streamoff,
++
++ .vidioc_log_status = v4l2_ctrl_log_status,
++ .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
++ .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
++};
++
++static const struct v4l2_ioctl_ops camera0_ioctl_ops_gstreamer = {
++ /* overlay */
++ .vidioc_enum_fmt_vid_overlay = vidioc_enum_fmt_vid_overlay,
++ .vidioc_g_fmt_vid_overlay = vidioc_g_fmt_vid_overlay,
++ .vidioc_try_fmt_vid_overlay = vidioc_try_fmt_vid_overlay,
++ .vidioc_s_fmt_vid_overlay = vidioc_s_fmt_vid_overlay,
++ .vidioc_overlay = vidioc_overlay,
++ .vidioc_g_fbuf = vidioc_g_fbuf,
++
++ /* inputs */
++ .vidioc_enum_input = vidioc_enum_input,
++ .vidioc_g_input = vidioc_g_input,
++ .vidioc_s_input = vidioc_s_input,
++
++ /* capture */
++ .vidioc_querycap = vidioc_querycap,
++ .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
++ .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap,
++ .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap,
++ .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap,
++
++ /* buffer management */
++ .vidioc_reqbufs = vb2_ioctl_reqbufs,
++ .vidioc_create_bufs = vb2_ioctl_create_bufs,
++ .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
++ .vidioc_querybuf = vb2_ioctl_querybuf,
++ .vidioc_qbuf = vb2_ioctl_qbuf,
++ .vidioc_dqbuf = vb2_ioctl_dqbuf,
++ /* Remove this function ptr to fix gstreamer bug
++ .vidioc_enum_framesizes = vidioc_enum_framesizes, */
++ .vidioc_enum_frameintervals = vidioc_enum_frameintervals,
++ .vidioc_g_parm = vidioc_g_parm,
++ .vidioc_s_parm = vidioc_s_parm,
++ .vidioc_streamon = vb2_ioctl_streamon,
++ .vidioc_streamoff = vb2_ioctl_streamoff,
++
++ .vidioc_log_status = v4l2_ctrl_log_status,
++ .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
++ .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
++};
++
++/* ------------------------------------------------------------------
++ Driver init/finalise
++ ------------------------------------------------------------------*/
++
++static const struct v4l2_file_operations camera0_fops = {
++ .owner = THIS_MODULE,
++ .open = v4l2_fh_open,
++ .release = vb2_fop_release,
++ .read = vb2_fop_read,
++ .poll = vb2_fop_poll,
++ .unlocked_ioctl = video_ioctl2, /* V4L2 ioctl handler */
++ .mmap = vb2_fop_mmap,
++};
++
++static struct video_device vdev_template = {
++ .name = "camera0",
++ .fops = &camera0_fops,
++ .ioctl_ops = &camera0_ioctl_ops,
++ .release = video_device_release_empty,
++};
++
++static int set_camera_parameters(struct vchiq_mmal_instance *instance,
++ struct vchiq_mmal_component *camera)
++{
++ int ret;
++ struct mmal_parameter_camera_config cam_config = {
++ .max_stills_w = MAX_WIDTH,
++ .max_stills_h = MAX_HEIGHT,
++ .stills_yuv422 = 1,
++ .one_shot_stills = 1,
++ .max_preview_video_w = (max_video_width > 1920) ?
++ max_video_width : 1920,
++ .max_preview_video_h = (max_video_height > 1088) ?
++ max_video_height : 1088,
++ .num_preview_video_frames = 3,
++ .stills_capture_circular_buffer_height = 0,
++ .fast_preview_resume = 0,
++ .use_stc_timestamp = MMAL_PARAM_TIMESTAMP_MODE_RAW_STC
++ };
++
++ ret = vchiq_mmal_port_parameter_set(instance, &camera->control,
++ MMAL_PARAMETER_CAMERA_CONFIG,
++ &cam_config, sizeof(cam_config));
++ return ret;
++}
++
++/* MMAL instance and component init */
++static int __init mmal_init(struct bm2835_mmal_dev *dev)
++{
++ int ret;
++ struct mmal_es_format *format;
++ u32 bool_true = 1;
++
++ ret = vchiq_mmal_init(&dev->instance);
++ if (ret < 0)
++ return ret;
++
++ /* get the camera component ready */
++ ret = vchiq_mmal_component_init(dev->instance, "ril.camera",
++ &dev->component[MMAL_COMPONENT_CAMERA]);
++ if (ret < 0)
++ goto unreg_mmal;
++
++ if (dev->component[MMAL_COMPONENT_CAMERA]->outputs <
++ MMAL_CAMERA_PORT_COUNT) {
++ ret = -EINVAL;
++ goto unreg_camera;
++ }
++
++ ret = set_camera_parameters(dev->instance,
++ dev->component[MMAL_COMPONENT_CAMERA]);
++ if (ret < 0)
++ goto unreg_camera;
++
++ format =
++ &dev->component[MMAL_COMPONENT_CAMERA]->
++ output[MMAL_CAMERA_PORT_PREVIEW].format;
++
++ format->encoding = MMAL_ENCODING_OPAQUE;
++ format->encoding_variant = MMAL_ENCODING_I420;
++
++ format->es->video.width = 1024;
++ format->es->video.height = 768;
++ format->es->video.crop.x = 0;
++ format->es->video.crop.y = 0;
++ format->es->video.crop.width = 1024;
++ format->es->video.crop.height = 768;
++ format->es->video.frame_rate.num = 0; /* Rely on fps_range */
++ format->es->video.frame_rate.den = 1;
++
++ format =
++ &dev->component[MMAL_COMPONENT_CAMERA]->
++ output[MMAL_CAMERA_PORT_VIDEO].format;
++
++ format->encoding = MMAL_ENCODING_OPAQUE;
++ format->encoding_variant = MMAL_ENCODING_I420;
++
++ format->es->video.width = 1024;
++ format->es->video.height = 768;
++ format->es->video.crop.x = 0;
++ format->es->video.crop.y = 0;
++ format->es->video.crop.width = 1024;
++ format->es->video.crop.height = 768;
++ format->es->video.frame_rate.num = 0; /* Rely on fps_range */
++ format->es->video.frame_rate.den = 1;
++
++ vchiq_mmal_port_parameter_set(dev->instance,
++ &dev->component[MMAL_COMPONENT_CAMERA]->
++ output[MMAL_CAMERA_PORT_VIDEO],
++ MMAL_PARAMETER_NO_IMAGE_PADDING,
++ &bool_true, sizeof(bool_true));
++
++ format =
++ &dev->component[MMAL_COMPONENT_CAMERA]->
++ output[MMAL_CAMERA_PORT_CAPTURE].format;
++
++ format->encoding = MMAL_ENCODING_OPAQUE;
++
++ format->es->video.width = 2592;
++ format->es->video.height = 1944;
++ format->es->video.crop.x = 0;
++ format->es->video.crop.y = 0;
++ format->es->video.crop.width = 2592;
++ format->es->video.crop.height = 1944;
++ format->es->video.frame_rate.num = 0; /* Rely on fps_range */
++ format->es->video.frame_rate.den = 1;
++
++ dev->capture.width = format->es->video.width;
++ dev->capture.height = format->es->video.height;
++ dev->capture.fmt = &formats[0];
++ dev->capture.encode_component = NULL;
++ dev->capture.timeperframe = tpf_default;
++ dev->capture.enc_profile = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH;
++ dev->capture.enc_level = V4L2_MPEG_VIDEO_H264_LEVEL_4_0;
++
++ vchiq_mmal_port_parameter_set(dev->instance,
++ &dev->component[MMAL_COMPONENT_CAMERA]->
++ output[MMAL_CAMERA_PORT_CAPTURE],
++ MMAL_PARAMETER_NO_IMAGE_PADDING,
++ &bool_true, sizeof(bool_true));
++
++ /* get the preview component ready */
++ ret = vchiq_mmal_component_init(
++ dev->instance, "ril.video_render",
++ &dev->component[MMAL_COMPONENT_PREVIEW]);
++ if (ret < 0)
++ goto unreg_camera;
++
++ if (dev->component[MMAL_COMPONENT_PREVIEW]->inputs < 1) {
++ ret = -EINVAL;
++ pr_debug("too few input ports %d needed %d\n",
++ dev->component[MMAL_COMPONENT_PREVIEW]->inputs, 1);
++ goto unreg_preview;
++ }
++
++ /* get the image encoder component ready */
++ ret = vchiq_mmal_component_init(
++ dev->instance, "ril.image_encode",
++ &dev->component[MMAL_COMPONENT_IMAGE_ENCODE]);
++ if (ret < 0)
++ goto unreg_preview;
++
++ if (dev->component[MMAL_COMPONENT_IMAGE_ENCODE]->inputs < 1) {
++ ret = -EINVAL;
++ v4l2_err(&dev->v4l2_dev, "too few input ports %d needed %d\n",
++ dev->component[MMAL_COMPONENT_IMAGE_ENCODE]->inputs,
++ 1);
++ goto unreg_image_encoder;
++ }
++
++ /* get the video encoder component ready */
++ ret = vchiq_mmal_component_init(dev->instance, "ril.video_encode",
++ &dev->
++ component[MMAL_COMPONENT_VIDEO_ENCODE]);
++ if (ret < 0)
++ goto unreg_image_encoder;
++
++ if (dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->inputs < 1) {
++ ret = -EINVAL;
++ v4l2_err(&dev->v4l2_dev, "too few input ports %d needed %d\n",
++ dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->inputs,
++ 1);
++ goto unreg_vid_encoder;
++ }
++
++ {
++ struct vchiq_mmal_port *encoder_port =
++ &dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->output[0];
++ encoder_port->format.encoding = MMAL_ENCODING_H264;
++ ret = vchiq_mmal_port_set_format(dev->instance,
++ encoder_port);
++ }
++
++ {
++ unsigned int enable = 1;
++ vchiq_mmal_port_parameter_set(
++ dev->instance,
++ &dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->control,
++ MMAL_PARAMETER_VIDEO_IMMUTABLE_INPUT,
++ &enable, sizeof(enable));
++
++ vchiq_mmal_port_parameter_set(dev->instance,
++ &dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->control,
++ MMAL_PARAMETER_MINIMISE_FRAGMENTATION,
++ &enable,
++ sizeof(enable));
++ }
++ ret = bm2835_mmal_set_all_camera_controls(dev);
++ if (ret < 0)
++ goto unreg_vid_encoder;
++
++ return 0;
++
++unreg_vid_encoder:
++ pr_err("Cleanup: Destroy video encoder\n");
++ vchiq_mmal_component_finalise(
++ dev->instance,
++ dev->component[MMAL_COMPONENT_VIDEO_ENCODE]);
++
++unreg_image_encoder:
++ pr_err("Cleanup: Destroy image encoder\n");
++ vchiq_mmal_component_finalise(
++ dev->instance,
++ dev->component[MMAL_COMPONENT_IMAGE_ENCODE]);
++
++unreg_preview:
++ pr_err("Cleanup: Destroy video render\n");
++ vchiq_mmal_component_finalise(dev->instance,
++ dev->component[MMAL_COMPONENT_PREVIEW]);
++
++unreg_camera:
++ pr_err("Cleanup: Destroy camera\n");
++ vchiq_mmal_component_finalise(dev->instance,
++ dev->component[MMAL_COMPONENT_CAMERA]);
++
++unreg_mmal:
++ vchiq_mmal_finalise(dev->instance);
++ return ret;
++}
++
++static int __init bm2835_mmal_init_device(struct bm2835_mmal_dev *dev,
++ struct video_device *vfd)
++{
++ int ret;
++
++ *vfd = vdev_template;
++ if (gst_v4l2src_is_broken) {
++ v4l2_info(&dev->v4l2_dev,
++ "Work-around for gstreamer issue is active.\n");
++ vfd->ioctl_ops = &camera0_ioctl_ops_gstreamer;
++ }
++
++ vfd->v4l2_dev = &dev->v4l2_dev;
++
++ vfd->lock = &dev->mutex;
++
++ vfd->queue = &dev->capture.vb_vidq;
++
++ /* video device needs to be able to access instance data */
++ video_set_drvdata(vfd, dev);
++
++ ret = video_register_device(vfd, VFL_TYPE_GRABBER, -1);
++ if (ret < 0)
++ return ret;
++
++ v4l2_info(vfd->v4l2_dev,
++ "V4L2 device registered as %s - stills mode > %dx%d\n",
++ video_device_node_name(vfd), max_video_width, max_video_height);
++
++ return 0;
++}
++
++static struct v4l2_format default_v4l2_format = {
++ .fmt.pix.pixelformat = V4L2_PIX_FMT_JPEG,
++ .fmt.pix.width = 1024,
++ .fmt.pix.bytesperline = 1024,
++ .fmt.pix.height = 768,
++ .fmt.pix.sizeimage = 1024*768,
++};
++
++static int __init bm2835_mmal_init(void)
++{
++ int ret;
++ struct bm2835_mmal_dev *dev;
++ struct vb2_queue *q;
++
++ dev = kzalloc(sizeof(*gdev), GFP_KERNEL);
++ if (!dev)
++ return -ENOMEM;
++
++ /* setup device defaults */
++ dev->overlay.w.left = 150;
++ dev->overlay.w.top = 50;
++ dev->overlay.w.width = 1024;
++ dev->overlay.w.height = 768;
++ dev->overlay.clipcount = 0;
++ dev->overlay.field = V4L2_FIELD_NONE;
++
++ dev->capture.fmt = &formats[3]; /* JPEG */
++
++ /* v4l device registration */
++ snprintf(dev->v4l2_dev.name, sizeof(dev->v4l2_dev.name),
++ "%s", BM2835_MMAL_MODULE_NAME);
++ ret = v4l2_device_register(NULL, &dev->v4l2_dev);
++ if (ret)
++ goto free_dev;
++
++ /* setup v4l controls */
++ ret = bm2835_mmal_init_controls(dev, &dev->ctrl_handler);
++ if (ret < 0)
++ goto unreg_dev;
++ dev->v4l2_dev.ctrl_handler = &dev->ctrl_handler;
++
++ /* mmal init */
++ ret = mmal_init(dev);
++ if (ret < 0)
++ goto unreg_dev;
++
++ /* initialize queue */
++ q = &dev->capture.vb_vidq;
++ memset(q, 0, sizeof(*q));
++ q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
++ q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_READ;
++ q->drv_priv = dev;
++ q->buf_struct_size = sizeof(struct mmal_buffer);
++ q->ops = &bm2835_mmal_video_qops;
++ q->mem_ops = &vb2_vmalloc_memops;
++ q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
++ ret = vb2_queue_init(q);
++ if (ret < 0)
++ goto unreg_dev;
++
++ /* v4l2 core mutex used to protect all fops and v4l2 ioctls. */
++ mutex_init(&dev->mutex);
++
++ /* initialise video devices */
++ ret = bm2835_mmal_init_device(dev, &dev->vdev);
++ if (ret < 0)
++ goto unreg_dev;
++
++ /* Really want to call vidioc_s_fmt_vid_cap with the default
++ * format, but currently the APIs don't join up.
++ */
++ ret = mmal_setup_components(dev, &default_v4l2_format);
++ if (ret < 0) {
++ v4l2_err(&dev->v4l2_dev,
++ "%s: could not setup components\n", __func__);
++ goto unreg_dev;
++ }
++
++ v4l2_info(&dev->v4l2_dev,
++ "Broadcom 2835 MMAL video capture ver %s loaded.\n",
++ BM2835_MMAL_VERSION);
++
++ gdev = dev;
++ return 0;
++
++unreg_dev:
++ v4l2_ctrl_handler_free(&dev->ctrl_handler);
++ v4l2_device_unregister(&dev->v4l2_dev);
++
++free_dev:
++ kfree(dev);
++
++ v4l2_err(&dev->v4l2_dev,
++ "%s: error %d while loading driver\n",
++ BM2835_MMAL_MODULE_NAME, ret);
++
++ return ret;
++}
++
++static void __exit bm2835_mmal_exit(void)
++{
++ if (!gdev)
++ return;
++
++ v4l2_info(&gdev->v4l2_dev, "unregistering %s\n",
++ video_device_node_name(&gdev->vdev));
++
++ video_unregister_device(&gdev->vdev);
++
++ if (gdev->capture.encode_component) {
++ v4l2_dbg(1, bcm2835_v4l2_debug, &gdev->v4l2_dev,
++ "mmal_exit - disconnect tunnel\n");
++ vchiq_mmal_port_connect_tunnel(gdev->instance,
++ gdev->capture.camera_port, NULL);
++ vchiq_mmal_component_disable(gdev->instance,
++ gdev->capture.encode_component);
++ }
++ vchiq_mmal_component_disable(gdev->instance,
++ gdev->component[MMAL_COMPONENT_CAMERA]);
++
++ vchiq_mmal_component_finalise(gdev->instance,
++ gdev->
++ component[MMAL_COMPONENT_VIDEO_ENCODE]);
++
++ vchiq_mmal_component_finalise(gdev->instance,
++ gdev->
++ component[MMAL_COMPONENT_IMAGE_ENCODE]);
++
++ vchiq_mmal_component_finalise(gdev->instance,
++ gdev->component[MMAL_COMPONENT_PREVIEW]);
++
++ vchiq_mmal_component_finalise(gdev->instance,
++ gdev->component[MMAL_COMPONENT_CAMERA]);
++
++ vchiq_mmal_finalise(gdev->instance);
++
++ v4l2_ctrl_handler_free(&gdev->ctrl_handler);
++
++ v4l2_device_unregister(&gdev->v4l2_dev);
++
++ kfree(gdev);
++}
++
++module_init(bm2835_mmal_init);
++module_exit(bm2835_mmal_exit);
+diff -Nur linux-4.1.3/drivers/media/platform/bcm2835/bcm2835-camera.h linux-xbian-rpi/drivers/media/platform/bcm2835/bcm2835-camera.h
+--- linux-4.1.3/drivers/media/platform/bcm2835/bcm2835-camera.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/media/platform/bcm2835/bcm2835-camera.h 2015-07-28 01:20:58.198038163 +0200
+@@ -0,0 +1,126 @@
++/*
++ * Broadcom BM2835 V4L2 driver
++ *
++ * Copyright © 2013 Raspberry Pi (Trading) Ltd.
++ *
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file COPYING in the main directory of this archive
++ * for more details.
++ *
++ * Authors: Vincent Sanders <vincent.sanders@collabora.co.uk>
++ * Dave Stevenson <dsteve@broadcom.com>
++ * Simon Mellor <simellor@broadcom.com>
++ * Luke Diamand <luked@broadcom.com>
++ *
++ * core driver device
++ */
++
++#define V4L2_CTRL_COUNT 28 /* number of v4l controls */
++
++enum {
++ MMAL_COMPONENT_CAMERA = 0,
++ MMAL_COMPONENT_PREVIEW,
++ MMAL_COMPONENT_IMAGE_ENCODE,
++ MMAL_COMPONENT_VIDEO_ENCODE,
++ MMAL_COMPONENT_COUNT
++};
++
++enum {
++ MMAL_CAMERA_PORT_PREVIEW = 0,
++ MMAL_CAMERA_PORT_VIDEO,
++ MMAL_CAMERA_PORT_CAPTURE,
++ MMAL_CAMERA_PORT_COUNT
++};
++
++#define PREVIEW_LAYER 2
++
++extern int bcm2835_v4l2_debug;
++
++struct bm2835_mmal_dev {
++ /* v4l2 devices */
++ struct v4l2_device v4l2_dev;
++ struct video_device vdev;
++ struct mutex mutex;
++
++ /* controls */
++ struct v4l2_ctrl_handler ctrl_handler;
++ struct v4l2_ctrl *ctrls[V4L2_CTRL_COUNT];
++ enum v4l2_scene_mode scene_mode;
++ struct mmal_colourfx colourfx;
++ int hflip;
++ int vflip;
++ int red_gain;
++ int blue_gain;
++ enum mmal_parameter_exposuremode exposure_mode_user;
++ enum v4l2_exposure_auto_type exposure_mode_v4l2_user;
++ /* active exposure mode may differ if selected via a scene mode */
++ enum mmal_parameter_exposuremode exposure_mode_active;
++ enum mmal_parameter_exposuremeteringmode metering_mode;
++ unsigned int manual_shutter_speed;
++ bool exp_auto_priority;
++
++ /* allocated mmal instance and components */
++ struct vchiq_mmal_instance *instance;
++ struct vchiq_mmal_component *component[MMAL_COMPONENT_COUNT];
++ int camera_use_count;
++
++ struct v4l2_window overlay;
++
++ struct {
++ unsigned int width; /* width */
++ unsigned int height; /* height */
++ unsigned int stride; /* stride */
++ unsigned int buffersize; /* buffer size with padding */
++ struct mmal_fmt *fmt;
++ struct v4l2_fract timeperframe;
++
++ /* H264 encode bitrate */
++ int encode_bitrate;
++ /* H264 bitrate mode. CBR/VBR */
++ int encode_bitrate_mode;
++ /* H264 profile */
++ enum v4l2_mpeg_video_h264_profile enc_profile;
++ /* H264 level */
++ enum v4l2_mpeg_video_h264_level enc_level;
++ /* JPEG Q-factor */
++ int q_factor;
++
++ struct vb2_queue vb_vidq;
++
++ /* VC start timestamp for streaming */
++ s64 vc_start_timestamp;
++ /* Kernel start timestamp for streaming */
++ struct timeval kernel_start_ts;
++
++ struct vchiq_mmal_port *port; /* port being used for capture */
++ /* camera port being used for capture */
++ struct vchiq_mmal_port *camera_port;
++ /* component being used for encode */
++ struct vchiq_mmal_component *encode_component;
++ /* number of frames remaining which driver should capture */
++ unsigned int frame_count;
++ /* last frame completion */
++ struct completion frame_cmplt;
++
++ } capture;
++
++};
++
++int bm2835_mmal_init_controls(
++ struct bm2835_mmal_dev *dev,
++ struct v4l2_ctrl_handler *hdl);
++
++int bm2835_mmal_set_all_camera_controls(struct bm2835_mmal_dev *dev);
++int set_framerate_params(struct bm2835_mmal_dev *dev);
++
++/* Debug helpers */
++
++#define v4l2_dump_pix_format(level, debug, dev, pix_fmt, desc) \
++{ \
++ v4l2_dbg(level, debug, dev, \
++"%s: w %u h %u field %u pfmt 0x%x bpl %u sz_img %u colorspace 0x%x priv %u\n", \
++ desc == NULL ? "" : desc, \
++ (pix_fmt)->width, (pix_fmt)->height, (pix_fmt)->field, \
++ (pix_fmt)->pixelformat, (pix_fmt)->bytesperline, \
++ (pix_fmt)->sizeimage, (pix_fmt)->colorspace, (pix_fmt)->priv); \
++}
+diff -Nur linux-4.1.3/drivers/media/platform/bcm2835/controls.c linux-xbian-rpi/drivers/media/platform/bcm2835/controls.c
+--- linux-4.1.3/drivers/media/platform/bcm2835/controls.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/media/platform/bcm2835/controls.c 2015-07-28 01:20:58.198038163 +0200
+@@ -0,0 +1,1322 @@
++/*
++ * Broadcom BM2835 V4L2 driver
++ *
++ * Copyright © 2013 Raspberry Pi (Trading) Ltd.
++ *
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file COPYING in the main directory of this archive
++ * for more details.
++ *
++ * Authors: Vincent Sanders <vincent.sanders@collabora.co.uk>
++ * Dave Stevenson <dsteve@broadcom.com>
++ * Simon Mellor <simellor@broadcom.com>
++ * Luke Diamand <luked@broadcom.com>
++ */
++
++#include <linux/errno.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <media/videobuf2-vmalloc.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-ioctl.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-fh.h>
++#include <media/v4l2-event.h>
++#include <media/v4l2-common.h>
++
++#include "mmal-common.h"
++#include "mmal-vchiq.h"
++#include "mmal-parameters.h"
++#include "bcm2835-camera.h"
++
++/* The supported V4L2_CID_AUTO_EXPOSURE_BIAS values are from -4.0 to +4.0.
++ * MMAL values are in 1/6th increments so the MMAL range is -24 to +24.
++ * V4L2 docs say value "is expressed in terms of EV, drivers should interpret
++ * the values as 0.001 EV units, where the value 1000 stands for +1 EV."
++ * V4L2 is limited to a max of 32 values in a menu, so count in 1/3rds from
++ * -4 to +4
++ */
++static const s64 ev_bias_qmenu[] = {
++ -4000, -3667, -3333,
++ -3000, -2667, -2333,
++ -2000, -1667, -1333,
++ -1000, -667, -333,
++ 0, 333, 667,
++ 1000, 1333, 1667,
++ 2000, 2333, 2667,
++ 3000, 3333, 3667,
++ 4000
++};
++
++/* Supported ISO values
++ * ISOO = auto ISO
++ */
++static const s64 iso_qmenu[] = {
++ 0, 100, 200, 400, 800,
++};
++
++static const s64 mains_freq_qmenu[] = {
++ V4L2_CID_POWER_LINE_FREQUENCY_DISABLED,
++ V4L2_CID_POWER_LINE_FREQUENCY_50HZ,
++ V4L2_CID_POWER_LINE_FREQUENCY_60HZ,
++ V4L2_CID_POWER_LINE_FREQUENCY_AUTO
++};
++
++/* Supported video encode modes */
++static const s64 bitrate_mode_qmenu[] = {
++ (s64)V4L2_MPEG_VIDEO_BITRATE_MODE_VBR,
++ (s64)V4L2_MPEG_VIDEO_BITRATE_MODE_CBR,
++};
++
++enum bm2835_mmal_ctrl_type {
++ MMAL_CONTROL_TYPE_STD,
++ MMAL_CONTROL_TYPE_STD_MENU,
++ MMAL_CONTROL_TYPE_INT_MENU,
++ MMAL_CONTROL_TYPE_CLUSTER, /* special cluster entry */
++};
++
++struct bm2835_mmal_v4l2_ctrl;
++
++typedef int(bm2835_mmal_v4l2_ctrl_cb)(
++ struct bm2835_mmal_dev *dev,
++ struct v4l2_ctrl *ctrl,
++ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl);
++
++struct bm2835_mmal_v4l2_ctrl {
++ u32 id; /* v4l2 control identifier */
++ enum bm2835_mmal_ctrl_type type;
++ /* control minimum value or
++ * mask for MMAL_CONTROL_TYPE_STD_MENU */
++ s32 min;
++ s32 max; /* maximum value of control */
++ s32 def; /* default value of control */
++ s32 step; /* step size of the control */
++ const s64 *imenu; /* integer menu array */
++ u32 mmal_id; /* mmal parameter id */
++ bm2835_mmal_v4l2_ctrl_cb *setter;
++ bool ignore_errors;
++};
++
++struct v4l2_to_mmal_effects_setting {
++ u32 v4l2_effect;
++ u32 mmal_effect;
++ s32 col_fx_enable;
++ s32 col_fx_fixed_cbcr;
++ u32 u;
++ u32 v;
++ u32 num_effect_params;
++ u32 effect_params[MMAL_MAX_IMAGEFX_PARAMETERS];
++};
++
++static const struct v4l2_to_mmal_effects_setting
++ v4l2_to_mmal_effects_values[] = {
++ { V4L2_COLORFX_NONE, MMAL_PARAM_IMAGEFX_NONE,
++ 0, 0, 0, 0, 0, {0, 0, 0, 0, 0} },
++ { V4L2_COLORFX_BW, MMAL_PARAM_IMAGEFX_NONE,
++ 1, 0, 128, 128, 0, {0, 0, 0, 0, 0} },
++ { V4L2_COLORFX_SEPIA, MMAL_PARAM_IMAGEFX_NONE,
++ 1, 0, 87, 151, 0, {0, 0, 0, 0, 0} },
++ { V4L2_COLORFX_NEGATIVE, MMAL_PARAM_IMAGEFX_NEGATIVE,
++ 0, 0, 0, 0, 0, {0, 0, 0, 0, 0} },
++ { V4L2_COLORFX_EMBOSS, MMAL_PARAM_IMAGEFX_EMBOSS,
++ 0, 0, 0, 0, 0, {0, 0, 0, 0, 0} },
++ { V4L2_COLORFX_SKETCH, MMAL_PARAM_IMAGEFX_SKETCH,
++ 0, 0, 0, 0, 0, {0, 0, 0, 0, 0} },
++ { V4L2_COLORFX_SKY_BLUE, MMAL_PARAM_IMAGEFX_PASTEL,
++ 0, 0, 0, 0, 0, {0, 0, 0, 0, 0} },
++ { V4L2_COLORFX_GRASS_GREEN, MMAL_PARAM_IMAGEFX_WATERCOLOUR,
++ 0, 0, 0, 0, 0, {0, 0, 0, 0, 0} },
++ { V4L2_COLORFX_SKIN_WHITEN, MMAL_PARAM_IMAGEFX_WASHEDOUT,
++ 0, 0, 0, 0, 0, {0, 0, 0, 0, 0} },
++ { V4L2_COLORFX_VIVID, MMAL_PARAM_IMAGEFX_SATURATION,
++ 0, 0, 0, 0, 0, {0, 0, 0, 0, 0} },
++ { V4L2_COLORFX_AQUA, MMAL_PARAM_IMAGEFX_NONE,
++ 1, 0, 171, 121, 0, {0, 0, 0, 0, 0} },
++ { V4L2_COLORFX_ART_FREEZE, MMAL_PARAM_IMAGEFX_HATCH,
++ 0, 0, 0, 0, 0, {0, 0, 0, 0, 0} },
++ { V4L2_COLORFX_SILHOUETTE, MMAL_PARAM_IMAGEFX_FILM,
++ 0, 0, 0, 0, 0, {0, 0, 0, 0, 0} },
++ { V4L2_COLORFX_SOLARIZATION, MMAL_PARAM_IMAGEFX_SOLARIZE,
++ 0, 0, 0, 0, 5, {1, 128, 160, 160, 48} },
++ { V4L2_COLORFX_ANTIQUE, MMAL_PARAM_IMAGEFX_COLOURBALANCE,
++ 0, 0, 0, 0, 3, {108, 274, 238, 0, 0} },
++ { V4L2_COLORFX_SET_CBCR, MMAL_PARAM_IMAGEFX_NONE,
++ 1, 1, 0, 0, 0, {0, 0, 0, 0, 0} }
++};
++
++struct v4l2_mmal_scene_config {
++ enum v4l2_scene_mode v4l2_scene;
++ enum mmal_parameter_exposuremode exposure_mode;
++ enum mmal_parameter_exposuremeteringmode metering_mode;
++};
++
++static const struct v4l2_mmal_scene_config scene_configs[] = {
++ /* V4L2_SCENE_MODE_NONE automatically added */
++ {
++ V4L2_SCENE_MODE_NIGHT,
++ MMAL_PARAM_EXPOSUREMODE_NIGHT,
++ MMAL_PARAM_EXPOSUREMETERINGMODE_AVERAGE
++ },
++ {
++ V4L2_SCENE_MODE_SPORTS,
++ MMAL_PARAM_EXPOSUREMODE_SPORTS,
++ MMAL_PARAM_EXPOSUREMETERINGMODE_AVERAGE
++ },
++};
++
++/* control handlers*/
++
++static int ctrl_set_rational(struct bm2835_mmal_dev *dev,
++ struct v4l2_ctrl *ctrl,
++ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl)
++{
++ struct mmal_parameter_rational rational_value;
++ struct vchiq_mmal_port *control;
++
++ control = &dev->component[MMAL_COMPONENT_CAMERA]->control;
++
++ rational_value.num = ctrl->val;
++ rational_value.den = 100;
++
++ return vchiq_mmal_port_parameter_set(dev->instance, control,
++ mmal_ctrl->mmal_id,
++ &rational_value,
++ sizeof(rational_value));
++}
++
++static int ctrl_set_value(struct bm2835_mmal_dev *dev,
++ struct v4l2_ctrl *ctrl,
++ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl)
++{
++ u32 u32_value;
++ struct vchiq_mmal_port *control;
++
++ control = &dev->component[MMAL_COMPONENT_CAMERA]->control;
++
++ u32_value = ctrl->val;
++
++ return vchiq_mmal_port_parameter_set(dev->instance, control,
++ mmal_ctrl->mmal_id,
++ &u32_value, sizeof(u32_value));
++}
++
++static int ctrl_set_value_menu(struct bm2835_mmal_dev *dev,
++ struct v4l2_ctrl *ctrl,
++ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl)
++{
++ u32 u32_value;
++ struct vchiq_mmal_port *control;
++
++ if (ctrl->val > mmal_ctrl->max || ctrl->val < mmal_ctrl->min)
++ return 1;
++
++ control = &dev->component[MMAL_COMPONENT_CAMERA]->control;
++
++ u32_value = mmal_ctrl->imenu[ctrl->val];
++
++ return vchiq_mmal_port_parameter_set(dev->instance, control,
++ mmal_ctrl->mmal_id,
++ &u32_value, sizeof(u32_value));
++}
++
++static int ctrl_set_value_ev(struct bm2835_mmal_dev *dev,
++ struct v4l2_ctrl *ctrl,
++ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl)
++{
++ s32 s32_value;
++ struct vchiq_mmal_port *control;
++
++ control = &dev->component[MMAL_COMPONENT_CAMERA]->control;
++
++ s32_value = (ctrl->val-12)*2; /* Convert from index to 1/6ths */
++
++ return vchiq_mmal_port_parameter_set(dev->instance, control,
++ mmal_ctrl->mmal_id,
++ &s32_value, sizeof(s32_value));
++}
++
++static int ctrl_set_rotate(struct bm2835_mmal_dev *dev,
++ struct v4l2_ctrl *ctrl,
++ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl)
++{
++ int ret;
++ u32 u32_value;
++ struct vchiq_mmal_component *camera;
++
++ camera = dev->component[MMAL_COMPONENT_CAMERA];
++
++ u32_value = ((ctrl->val % 360) / 90) * 90;
++
++ ret = vchiq_mmal_port_parameter_set(dev->instance, &camera->output[0],
++ mmal_ctrl->mmal_id,
++ &u32_value, sizeof(u32_value));
++ if (ret < 0)
++ return ret;
++
++ ret = vchiq_mmal_port_parameter_set(dev->instance, &camera->output[1],
++ mmal_ctrl->mmal_id,
++ &u32_value, sizeof(u32_value));
++ if (ret < 0)
++ return ret;
++
++ ret = vchiq_mmal_port_parameter_set(dev->instance, &camera->output[2],
++ mmal_ctrl->mmal_id,
++ &u32_value, sizeof(u32_value));
++
++ return ret;
++}
++
++static int ctrl_set_flip(struct bm2835_mmal_dev *dev,
++ struct v4l2_ctrl *ctrl,
++ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl)
++{
++ int ret;
++ u32 u32_value;
++ struct vchiq_mmal_component *camera;
++
++ if (ctrl->id == V4L2_CID_HFLIP)
++ dev->hflip = ctrl->val;
++ else
++ dev->vflip = ctrl->val;
++
++ camera = dev->component[MMAL_COMPONENT_CAMERA];
++
++ if (dev->hflip && dev->vflip)
++ u32_value = MMAL_PARAM_MIRROR_BOTH;
++ else if (dev->hflip)
++ u32_value = MMAL_PARAM_MIRROR_HORIZONTAL;
++ else if (dev->vflip)
++ u32_value = MMAL_PARAM_MIRROR_VERTICAL;
++ else
++ u32_value = MMAL_PARAM_MIRROR_NONE;
++
++ ret = vchiq_mmal_port_parameter_set(dev->instance, &camera->output[0],
++ mmal_ctrl->mmal_id,
++ &u32_value, sizeof(u32_value));
++ if (ret < 0)
++ return ret;
++
++ ret = vchiq_mmal_port_parameter_set(dev->instance, &camera->output[1],
++ mmal_ctrl->mmal_id,
++ &u32_value, sizeof(u32_value));
++ if (ret < 0)
++ return ret;
++
++ ret = vchiq_mmal_port_parameter_set(dev->instance, &camera->output[2],
++ mmal_ctrl->mmal_id,
++ &u32_value, sizeof(u32_value));
++
++ return ret;
++
++}
++
++static int ctrl_set_exposure(struct bm2835_mmal_dev *dev,
++ struct v4l2_ctrl *ctrl,
++ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl)
++{
++ enum mmal_parameter_exposuremode exp_mode = dev->exposure_mode_user;
++ u32 shutter_speed = 0;
++ struct vchiq_mmal_port *control;
++ int ret = 0;
++
++ control = &dev->component[MMAL_COMPONENT_CAMERA]->control;
++
++ if (mmal_ctrl->mmal_id == MMAL_PARAMETER_SHUTTER_SPEED) {
++ /* V4L2 is in 100usec increments.
++ * MMAL is 1usec.
++ */
++ dev->manual_shutter_speed = ctrl->val * 100;
++ } else if (mmal_ctrl->mmal_id == MMAL_PARAMETER_EXPOSURE_MODE) {
++ switch (ctrl->val) {
++ case V4L2_EXPOSURE_AUTO:
++ exp_mode = MMAL_PARAM_EXPOSUREMODE_AUTO;
++ break;
++
++ case V4L2_EXPOSURE_MANUAL:
++ exp_mode = MMAL_PARAM_EXPOSUREMODE_OFF;
++ break;
++ }
++ dev->exposure_mode_user = exp_mode;
++ dev->exposure_mode_v4l2_user = ctrl->val;
++ } else if (mmal_ctrl->id == V4L2_CID_EXPOSURE_AUTO_PRIORITY) {
++ dev->exp_auto_priority = ctrl->val;
++ }
++
++ if (dev->scene_mode == V4L2_SCENE_MODE_NONE) {
++ if (exp_mode == MMAL_PARAM_EXPOSUREMODE_OFF)
++ shutter_speed = dev->manual_shutter_speed;
++
++ ret = vchiq_mmal_port_parameter_set(dev->instance,
++ control,
++ MMAL_PARAMETER_SHUTTER_SPEED,
++ &shutter_speed,
++ sizeof(shutter_speed));
++ ret += vchiq_mmal_port_parameter_set(dev->instance,
++ control,
++ MMAL_PARAMETER_EXPOSURE_MODE,
++ &exp_mode,
++ sizeof(u32));
++ dev->exposure_mode_active = exp_mode;
++ }
++ /* exposure_dynamic_framerate (V4L2_CID_EXPOSURE_AUTO_PRIORITY) should
++ * always apply irrespective of scene mode.
++ */
++ ret += set_framerate_params(dev);
++
++ return ret;
++}
++
++static int ctrl_set_metering_mode(struct bm2835_mmal_dev *dev,
++ struct v4l2_ctrl *ctrl,
++ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl)
++{
++ switch (ctrl->val) {
++ case V4L2_EXPOSURE_METERING_AVERAGE:
++ dev->metering_mode = MMAL_PARAM_EXPOSUREMETERINGMODE_AVERAGE;
++ break;
++
++ case V4L2_EXPOSURE_METERING_CENTER_WEIGHTED:
++ dev->metering_mode = MMAL_PARAM_EXPOSUREMETERINGMODE_BACKLIT;
++ break;
++
++ case V4L2_EXPOSURE_METERING_SPOT:
++ dev->metering_mode = MMAL_PARAM_EXPOSUREMETERINGMODE_SPOT;
++ break;
++
++ /* todo matrix weighting not added to Linux API till 3.9
++ case V4L2_EXPOSURE_METERING_MATRIX:
++ dev->metering_mode = MMAL_PARAM_EXPOSUREMETERINGMODE_MATRIX;
++ break;
++ */
++
++ }
++
++ if (dev->scene_mode == V4L2_SCENE_MODE_NONE) {
++ struct vchiq_mmal_port *control;
++ u32 u32_value = dev->metering_mode;
++
++ control = &dev->component[MMAL_COMPONENT_CAMERA]->control;
++
++ return vchiq_mmal_port_parameter_set(dev->instance, control,
++ mmal_ctrl->mmal_id,
++ &u32_value, sizeof(u32_value));
++ } else
++ return 0;
++}
++
++static int ctrl_set_flicker_avoidance(struct bm2835_mmal_dev *dev,
++ struct v4l2_ctrl *ctrl,
++ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl)
++{
++ u32 u32_value;
++ struct vchiq_mmal_port *control;
++
++ control = &dev->component[MMAL_COMPONENT_CAMERA]->control;
++
++ switch (ctrl->val) {
++ case V4L2_CID_POWER_LINE_FREQUENCY_DISABLED:
++ u32_value = MMAL_PARAM_FLICKERAVOID_OFF;
++ break;
++ case V4L2_CID_POWER_LINE_FREQUENCY_50HZ:
++ u32_value = MMAL_PARAM_FLICKERAVOID_50HZ;
++ break;
++ case V4L2_CID_POWER_LINE_FREQUENCY_60HZ:
++ u32_value = MMAL_PARAM_FLICKERAVOID_60HZ;
++ break;
++ case V4L2_CID_POWER_LINE_FREQUENCY_AUTO:
++ u32_value = MMAL_PARAM_FLICKERAVOID_AUTO;
++ break;
++ }
++
++ return vchiq_mmal_port_parameter_set(dev->instance, control,
++ mmal_ctrl->mmal_id,
++ &u32_value, sizeof(u32_value));
++}
++
++static int ctrl_set_awb_mode(struct bm2835_mmal_dev *dev,
++ struct v4l2_ctrl *ctrl,
++ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl)
++{
++ u32 u32_value;
++ struct vchiq_mmal_port *control;
++
++ control = &dev->component[MMAL_COMPONENT_CAMERA]->control;
++
++ switch (ctrl->val) {
++ case V4L2_WHITE_BALANCE_MANUAL:
++ u32_value = MMAL_PARAM_AWBMODE_OFF;
++ break;
++
++ case V4L2_WHITE_BALANCE_AUTO:
++ u32_value = MMAL_PARAM_AWBMODE_AUTO;
++ break;
++
++ case V4L2_WHITE_BALANCE_INCANDESCENT:
++ u32_value = MMAL_PARAM_AWBMODE_INCANDESCENT;
++ break;
++
++ case V4L2_WHITE_BALANCE_FLUORESCENT:
++ u32_value = MMAL_PARAM_AWBMODE_FLUORESCENT;
++ break;
++
++ case V4L2_WHITE_BALANCE_FLUORESCENT_H:
++ u32_value = MMAL_PARAM_AWBMODE_TUNGSTEN;
++ break;
++
++ case V4L2_WHITE_BALANCE_HORIZON:
++ u32_value = MMAL_PARAM_AWBMODE_HORIZON;
++ break;
++
++ case V4L2_WHITE_BALANCE_DAYLIGHT:
++ u32_value = MMAL_PARAM_AWBMODE_SUNLIGHT;
++ break;
++
++ case V4L2_WHITE_BALANCE_FLASH:
++ u32_value = MMAL_PARAM_AWBMODE_FLASH;
++ break;
++
++ case V4L2_WHITE_BALANCE_CLOUDY:
++ u32_value = MMAL_PARAM_AWBMODE_CLOUDY;
++ break;
++
++ case V4L2_WHITE_BALANCE_SHADE:
++ u32_value = MMAL_PARAM_AWBMODE_SHADE;
++ break;
++
++ }
++
++ return vchiq_mmal_port_parameter_set(dev->instance, control,
++ mmal_ctrl->mmal_id,
++ &u32_value, sizeof(u32_value));
++}
++
++static int ctrl_set_awb_gains(struct bm2835_mmal_dev *dev,
++ struct v4l2_ctrl *ctrl,
++ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl)
++{
++ struct vchiq_mmal_port *control;
++ struct mmal_parameter_awbgains gains;
++
++ control = &dev->component[MMAL_COMPONENT_CAMERA]->control;
++
++ if (ctrl->id == V4L2_CID_RED_BALANCE)
++ dev->red_gain = ctrl->val;
++ else if (ctrl->id == V4L2_CID_BLUE_BALANCE)
++ dev->blue_gain = ctrl->val;
++
++ gains.r_gain.num = dev->red_gain;
++ gains.b_gain.num = dev->blue_gain;
++ gains.r_gain.den = gains.b_gain.den = 1000;
++
++ return vchiq_mmal_port_parameter_set(dev->instance, control,
++ mmal_ctrl->mmal_id,
++ &gains, sizeof(gains));
++}
++
++static int ctrl_set_image_effect(struct bm2835_mmal_dev *dev,
++ struct v4l2_ctrl *ctrl,
++ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl)
++{
++ int ret = -EINVAL;
++ int i, j;
++ struct vchiq_mmal_port *control;
++ struct mmal_parameter_imagefx_parameters imagefx;
++
++ for (i = 0; i < ARRAY_SIZE(v4l2_to_mmal_effects_values); i++) {
++ if (ctrl->val == v4l2_to_mmal_effects_values[i].v4l2_effect) {
++
++ imagefx.effect =
++ v4l2_to_mmal_effects_values[i].mmal_effect;
++ imagefx.num_effect_params =
++ v4l2_to_mmal_effects_values[i].num_effect_params;
++
++ if (imagefx.num_effect_params > MMAL_MAX_IMAGEFX_PARAMETERS)
++ imagefx.num_effect_params = MMAL_MAX_IMAGEFX_PARAMETERS;
++
++ for (j = 0; j < imagefx.num_effect_params; j++)
++ imagefx.effect_parameter[j] =
++ v4l2_to_mmal_effects_values[i].effect_params[j];
++
++ dev->colourfx.enable =
++ v4l2_to_mmal_effects_values[i].col_fx_enable;
++ if (!v4l2_to_mmal_effects_values[i].col_fx_fixed_cbcr) {
++ dev->colourfx.u =
++ v4l2_to_mmal_effects_values[i].u;
++ dev->colourfx.v =
++ v4l2_to_mmal_effects_values[i].v;
++ }
++
++ control = &dev->component[MMAL_COMPONENT_CAMERA]->control;
++
++ ret = vchiq_mmal_port_parameter_set(
++ dev->instance, control,
++ MMAL_PARAMETER_IMAGE_EFFECT_PARAMETERS,
++ &imagefx, sizeof(imagefx));
++ if (ret)
++ goto exit;
++
++ ret = vchiq_mmal_port_parameter_set(
++ dev->instance, control,
++ MMAL_PARAMETER_COLOUR_EFFECT,
++ &dev->colourfx, sizeof(dev->colourfx));
++ }
++ }
++
++exit:
++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
++ "mmal_ctrl:%p ctrl id:0x%x ctrl val:%d imagefx:0x%x color_effect:%s u:%d v:%d ret %d(%d)\n",
++ mmal_ctrl, ctrl->id, ctrl->val, imagefx.effect,
++ dev->colourfx.enable ? "true" : "false",
++ dev->colourfx.u, dev->colourfx.v,
++ ret, (ret == 0 ? 0 : -EINVAL));
++ return (ret == 0 ? 0 : EINVAL);
++}
++
++static int ctrl_set_colfx(struct bm2835_mmal_dev *dev,
++ struct v4l2_ctrl *ctrl,
++ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl)
++{
++ int ret = -EINVAL;
++ struct vchiq_mmal_port *control;
++
++ control = &dev->component[MMAL_COMPONENT_CAMERA]->control;
++
++ dev->colourfx.enable = (ctrl->val & 0xff00) >> 8;
++ dev->colourfx.enable = ctrl->val & 0xff;
++
++ ret = vchiq_mmal_port_parameter_set(dev->instance, control,
++ MMAL_PARAMETER_COLOUR_EFFECT,
++ &dev->colourfx, sizeof(dev->colourfx));
++
++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
++ "%s: After: mmal_ctrl:%p ctrl id:0x%x ctrl val:%d ret %d(%d)\n",
++ __func__, mmal_ctrl, ctrl->id, ctrl->val, ret,
++ (ret == 0 ? 0 : -EINVAL));
++ return (ret == 0 ? 0 : EINVAL);
++}
++
++static int ctrl_set_bitrate(struct bm2835_mmal_dev *dev,
++ struct v4l2_ctrl *ctrl,
++ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl)
++{
++ int ret;
++ struct vchiq_mmal_port *encoder_out;
++
++ dev->capture.encode_bitrate = ctrl->val;
++
++ encoder_out = &dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->output[0];
++
++ ret = vchiq_mmal_port_parameter_set(dev->instance, encoder_out,
++ mmal_ctrl->mmal_id,
++ &ctrl->val, sizeof(ctrl->val));
++ ret = 0;
++ return ret;
++}
++
++static int ctrl_set_bitrate_mode(struct bm2835_mmal_dev *dev,
++ struct v4l2_ctrl *ctrl,
++ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl)
++{
++ u32 bitrate_mode;
++ struct vchiq_mmal_port *encoder_out;
++
++ encoder_out = &dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->output[0];
++
++ dev->capture.encode_bitrate_mode = ctrl->val;
++ switch (ctrl->val) {
++ default:
++ case V4L2_MPEG_VIDEO_BITRATE_MODE_VBR:
++ bitrate_mode = MMAL_VIDEO_RATECONTROL_VARIABLE;
++ break;
++ case V4L2_MPEG_VIDEO_BITRATE_MODE_CBR:
++ bitrate_mode = MMAL_VIDEO_RATECONTROL_CONSTANT;
++ break;
++ }
++
++ vchiq_mmal_port_parameter_set(dev->instance, encoder_out,
++ mmal_ctrl->mmal_id,
++ &bitrate_mode,
++ sizeof(bitrate_mode));
++ return 0;
++}
++
++static int ctrl_set_image_encode_output(struct bm2835_mmal_dev *dev,
++ struct v4l2_ctrl *ctrl,
++ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl)
++{
++ u32 u32_value;
++ struct vchiq_mmal_port *jpeg_out;
++
++ jpeg_out = &dev->component[MMAL_COMPONENT_IMAGE_ENCODE]->output[0];
++
++ u32_value = ctrl->val;
++
++ return vchiq_mmal_port_parameter_set(dev->instance, jpeg_out,
++ mmal_ctrl->mmal_id,
++ &u32_value, sizeof(u32_value));
++}
++
++static int ctrl_set_video_encode_param_output(struct bm2835_mmal_dev *dev,
++ struct v4l2_ctrl *ctrl,
++ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl)
++{
++ u32 u32_value;
++ struct vchiq_mmal_port *vid_enc_ctl;
++
++ vid_enc_ctl = &dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->output[0];
++
++ u32_value = ctrl->val;
++
++ return vchiq_mmal_port_parameter_set(dev->instance, vid_enc_ctl,
++ mmal_ctrl->mmal_id,
++ &u32_value, sizeof(u32_value));
++}
++
++static int ctrl_set_video_encode_profile_level(struct bm2835_mmal_dev *dev,
++ struct v4l2_ctrl *ctrl,
++ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl)
++{
++ struct mmal_parameter_video_profile param;
++ int ret = 0;
++
++ if (ctrl->id == V4L2_CID_MPEG_VIDEO_H264_PROFILE) {
++ switch (ctrl->val) {
++ case V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE:
++ case V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE:
++ case V4L2_MPEG_VIDEO_H264_PROFILE_MAIN:
++ case V4L2_MPEG_VIDEO_H264_PROFILE_HIGH:
++ dev->capture.enc_profile = ctrl->val;
++ break;
++ default:
++ ret = -EINVAL;
++ break;
++ }
++ } else if (ctrl->id == V4L2_CID_MPEG_VIDEO_H264_LEVEL) {
++ switch (ctrl->val) {
++ case V4L2_MPEG_VIDEO_H264_LEVEL_1_0:
++ case V4L2_MPEG_VIDEO_H264_LEVEL_1B:
++ case V4L2_MPEG_VIDEO_H264_LEVEL_1_1:
++ case V4L2_MPEG_VIDEO_H264_LEVEL_1_2:
++ case V4L2_MPEG_VIDEO_H264_LEVEL_1_3:
++ case V4L2_MPEG_VIDEO_H264_LEVEL_2_0:
++ case V4L2_MPEG_VIDEO_H264_LEVEL_2_1:
++ case V4L2_MPEG_VIDEO_H264_LEVEL_2_2:
++ case V4L2_MPEG_VIDEO_H264_LEVEL_3_0:
++ case V4L2_MPEG_VIDEO_H264_LEVEL_3_1:
++ case V4L2_MPEG_VIDEO_H264_LEVEL_3_2:
++ case V4L2_MPEG_VIDEO_H264_LEVEL_4_0:
++ dev->capture.enc_level = ctrl->val;
++ break;
++ default:
++ ret = -EINVAL;
++ break;
++ }
++ }
++
++ if (!ret) {
++ switch (dev->capture.enc_profile) {
++ case V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE:
++ param.profile = MMAL_VIDEO_PROFILE_H264_BASELINE;
++ break;
++ case V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE:
++ param.profile =
++ MMAL_VIDEO_PROFILE_H264_CONSTRAINED_BASELINE;
++ break;
++ case V4L2_MPEG_VIDEO_H264_PROFILE_MAIN:
++ param.profile = MMAL_VIDEO_PROFILE_H264_MAIN;
++ break;
++ case V4L2_MPEG_VIDEO_H264_PROFILE_HIGH:
++ param.profile = MMAL_VIDEO_PROFILE_H264_HIGH;
++ break;
++ default:
++ /* Should never get here */
++ break;
++ }
++
++ switch (dev->capture.enc_level) {
++ case V4L2_MPEG_VIDEO_H264_LEVEL_1_0:
++ param.level = MMAL_VIDEO_LEVEL_H264_1;
++ break;
++ case V4L2_MPEG_VIDEO_H264_LEVEL_1B:
++ param.level = MMAL_VIDEO_LEVEL_H264_1b;
++ break;
++ case V4L2_MPEG_VIDEO_H264_LEVEL_1_1:
++ param.level = MMAL_VIDEO_LEVEL_H264_11;
++ break;
++ case V4L2_MPEG_VIDEO_H264_LEVEL_1_2:
++ param.level = MMAL_VIDEO_LEVEL_H264_12;
++ break;
++ case V4L2_MPEG_VIDEO_H264_LEVEL_1_3:
++ param.level = MMAL_VIDEO_LEVEL_H264_13;
++ break;
++ case V4L2_MPEG_VIDEO_H264_LEVEL_2_0:
++ param.level = MMAL_VIDEO_LEVEL_H264_2;
++ break;
++ case V4L2_MPEG_VIDEO_H264_LEVEL_2_1:
++ param.level = MMAL_VIDEO_LEVEL_H264_21;
++ break;
++ case V4L2_MPEG_VIDEO_H264_LEVEL_2_2:
++ param.level = MMAL_VIDEO_LEVEL_H264_22;
++ break;
++ case V4L2_MPEG_VIDEO_H264_LEVEL_3_0:
++ param.level = MMAL_VIDEO_LEVEL_H264_3;
++ break;
++ case V4L2_MPEG_VIDEO_H264_LEVEL_3_1:
++ param.level = MMAL_VIDEO_LEVEL_H264_31;
++ break;
++ case V4L2_MPEG_VIDEO_H264_LEVEL_3_2:
++ param.level = MMAL_VIDEO_LEVEL_H264_32;
++ break;
++ case V4L2_MPEG_VIDEO_H264_LEVEL_4_0:
++ param.level = MMAL_VIDEO_LEVEL_H264_4;
++ break;
++ default:
++ /* Should never get here */
++ break;
++ }
++
++ ret = vchiq_mmal_port_parameter_set(dev->instance,
++ &dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->output[0],
++ mmal_ctrl->mmal_id,
++ &param, sizeof(param));
++ }
++ return ret;
++}
++
++static int ctrl_set_scene_mode(struct bm2835_mmal_dev *dev,
++ struct v4l2_ctrl *ctrl,
++ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl)
++{
++ int ret = 0;
++ int shutter_speed;
++ struct vchiq_mmal_port *control;
++
++ v4l2_dbg(0, bcm2835_v4l2_debug, &dev->v4l2_dev,
++ "scene mode selected %d, was %d\n", ctrl->val,
++ dev->scene_mode);
++ control = &dev->component[MMAL_COMPONENT_CAMERA]->control;
++
++ if (ctrl->val == dev->scene_mode)
++ return 0;
++
++ if (ctrl->val == V4L2_SCENE_MODE_NONE) {
++ /* Restore all user selections */
++ dev->scene_mode = V4L2_SCENE_MODE_NONE;
++
++ if (dev->exposure_mode_user == MMAL_PARAM_EXPOSUREMODE_OFF)
++ shutter_speed = dev->manual_shutter_speed;
++ else
++ shutter_speed = 0;
++
++ v4l2_dbg(0, bcm2835_v4l2_debug, &dev->v4l2_dev,
++ "%s: scene mode none: shut_speed %d, exp_mode %d, metering %d\n",
++ __func__, shutter_speed, dev->exposure_mode_user,
++ dev->metering_mode);
++ ret = vchiq_mmal_port_parameter_set(dev->instance,
++ control,
++ MMAL_PARAMETER_SHUTTER_SPEED,
++ &shutter_speed,
++ sizeof(shutter_speed));
++ ret += vchiq_mmal_port_parameter_set(dev->instance,
++ control,
++ MMAL_PARAMETER_EXPOSURE_MODE,
++ &dev->exposure_mode_user,
++ sizeof(u32));
++ dev->exposure_mode_active = dev->exposure_mode_user;
++ ret += vchiq_mmal_port_parameter_set(dev->instance,
++ control,
++ MMAL_PARAMETER_EXP_METERING_MODE,
++ &dev->metering_mode,
++ sizeof(u32));
++ ret += set_framerate_params(dev);
++ } else {
++ /* Set up scene mode */
++ int i;
++ const struct v4l2_mmal_scene_config *scene = NULL;
++ int shutter_speed;
++ enum mmal_parameter_exposuremode exposure_mode;
++ enum mmal_parameter_exposuremeteringmode metering_mode;
++
++ for (i = 0; i < ARRAY_SIZE(scene_configs); i++) {
++ if (scene_configs[i].v4l2_scene ==
++ ctrl->val) {
++ scene = &scene_configs[i];
++ break;
++ }
++ }
++ if (i >= ARRAY_SIZE(scene_configs))
++ return -EINVAL;
++
++ /* Set all the values */
++ dev->scene_mode = ctrl->val;
++
++ if (scene->exposure_mode == MMAL_PARAM_EXPOSUREMODE_OFF)
++ shutter_speed = dev->manual_shutter_speed;
++ else
++ shutter_speed = 0;
++ exposure_mode = scene->exposure_mode;
++ metering_mode = scene->metering_mode;
++
++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
++ "%s: scene mode none: shut_speed %d, exp_mode %d, metering %d\n",
++ __func__, shutter_speed, exposure_mode, metering_mode);
++
++ ret = vchiq_mmal_port_parameter_set(dev->instance, control,
++ MMAL_PARAMETER_SHUTTER_SPEED,
++ &shutter_speed,
++ sizeof(shutter_speed));
++ ret += vchiq_mmal_port_parameter_set(dev->instance,
++ control,
++ MMAL_PARAMETER_EXPOSURE_MODE,
++ &exposure_mode,
++ sizeof(u32));
++ dev->exposure_mode_active = exposure_mode;
++ ret += vchiq_mmal_port_parameter_set(dev->instance, control,
++ MMAL_PARAMETER_EXPOSURE_MODE,
++ &exposure_mode,
++ sizeof(u32));
++ ret += vchiq_mmal_port_parameter_set(dev->instance, control,
++ MMAL_PARAMETER_EXP_METERING_MODE,
++ &metering_mode,
++ sizeof(u32));
++ ret += set_framerate_params(dev);
++ }
++ if (ret) {
++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
++ "%s: Setting scene to %d, ret=%d\n",
++ __func__, ctrl->val, ret);
++ ret = -EINVAL;
++ }
++ return 0;
++}
++
++static int bm2835_mmal_s_ctrl(struct v4l2_ctrl *ctrl)
++{
++ struct bm2835_mmal_dev *dev =
++ container_of(ctrl->handler, struct bm2835_mmal_dev,
++ ctrl_handler);
++ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl = ctrl->priv;
++ int ret;
++
++ if ((mmal_ctrl == NULL) ||
++ (mmal_ctrl->id != ctrl->id) ||
++ (mmal_ctrl->setter == NULL)) {
++ pr_warn("mmal_ctrl:%p ctrl id:%d\n", mmal_ctrl, ctrl->id);
++ return -EINVAL;
++ }
++
++ ret = mmal_ctrl->setter(dev, ctrl, mmal_ctrl);
++ if (ret)
++ pr_warn("ctrl id:%d/MMAL param %08X- returned ret %d\n",
++ ctrl->id, mmal_ctrl->mmal_id, ret);
++ if (mmal_ctrl->ignore_errors)
++ ret = 0;
++ return ret;
++}
++
++static const struct v4l2_ctrl_ops bm2835_mmal_ctrl_ops = {
++ .s_ctrl = bm2835_mmal_s_ctrl,
++};
++
++
++
++static const struct bm2835_mmal_v4l2_ctrl v4l2_ctrls[V4L2_CTRL_COUNT] = {
++ {
++ V4L2_CID_SATURATION, MMAL_CONTROL_TYPE_STD,
++ -100, 100, 0, 1, NULL,
++ MMAL_PARAMETER_SATURATION,
++ &ctrl_set_rational,
++ false
++ },
++ {
++ V4L2_CID_SHARPNESS, MMAL_CONTROL_TYPE_STD,
++ -100, 100, 0, 1, NULL,
++ MMAL_PARAMETER_SHARPNESS,
++ &ctrl_set_rational,
++ false
++ },
++ {
++ V4L2_CID_CONTRAST, MMAL_CONTROL_TYPE_STD,
++ -100, 100, 0, 1, NULL,
++ MMAL_PARAMETER_CONTRAST,
++ &ctrl_set_rational,
++ false
++ },
++ {
++ V4L2_CID_BRIGHTNESS, MMAL_CONTROL_TYPE_STD,
++ 0, 100, 50, 1, NULL,
++ MMAL_PARAMETER_BRIGHTNESS,
++ &ctrl_set_rational,
++ false
++ },
++ {
++ V4L2_CID_ISO_SENSITIVITY, MMAL_CONTROL_TYPE_INT_MENU,
++ 0, ARRAY_SIZE(iso_qmenu) - 1, 0, 1, iso_qmenu,
++ MMAL_PARAMETER_ISO,
++ &ctrl_set_value_menu,
++ false
++ },
++ {
++ V4L2_CID_IMAGE_STABILIZATION, MMAL_CONTROL_TYPE_STD,
++ 0, 1, 0, 1, NULL,
++ MMAL_PARAMETER_VIDEO_STABILISATION,
++ &ctrl_set_value,
++ false
++ },
++/* {
++ 0, MMAL_CONTROL_TYPE_CLUSTER, 3, 1, 0, NULL, 0, NULL
++ }, */
++ {
++ V4L2_CID_EXPOSURE_AUTO, MMAL_CONTROL_TYPE_STD_MENU,
++ ~0x03, 3, V4L2_EXPOSURE_AUTO, 0, NULL,
++ MMAL_PARAMETER_EXPOSURE_MODE,
++ &ctrl_set_exposure,
++ false
++ },
++/* todo this needs mixing in with set exposure
++ {
++ V4L2_CID_SCENE_MODE, MMAL_CONTROL_TYPE_STD_MENU,
++ },
++ */
++ {
++ V4L2_CID_EXPOSURE_ABSOLUTE, MMAL_CONTROL_TYPE_STD,
++ /* Units of 100usecs */
++ 1, 1*1000*10, 100*10, 1, NULL,
++ MMAL_PARAMETER_SHUTTER_SPEED,
++ &ctrl_set_exposure,
++ false
++ },
++ {
++ V4L2_CID_AUTO_EXPOSURE_BIAS, MMAL_CONTROL_TYPE_INT_MENU,
++ 0, ARRAY_SIZE(ev_bias_qmenu) - 1,
++ (ARRAY_SIZE(ev_bias_qmenu)+1)/2 - 1, 0, ev_bias_qmenu,
++ MMAL_PARAMETER_EXPOSURE_COMP,
++ &ctrl_set_value_ev,
++ false
++ },
++ {
++ V4L2_CID_EXPOSURE_AUTO_PRIORITY, MMAL_CONTROL_TYPE_STD,
++ 0, 1,
++ 0, 1, NULL,
++ 0, /* Dummy MMAL ID as it gets mapped into FPS range*/
++ &ctrl_set_exposure,
++ false
++ },
++ {
++ V4L2_CID_EXPOSURE_METERING,
++ MMAL_CONTROL_TYPE_STD_MENU,
++ ~0x7, 2, V4L2_EXPOSURE_METERING_AVERAGE, 0, NULL,
++ MMAL_PARAMETER_EXP_METERING_MODE,
++ &ctrl_set_metering_mode,
++ false
++ },
++ {
++ V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE,
++ MMAL_CONTROL_TYPE_STD_MENU,
++ ~0x3ff, 9, V4L2_WHITE_BALANCE_AUTO, 0, NULL,
++ MMAL_PARAMETER_AWB_MODE,
++ &ctrl_set_awb_mode,
++ false
++ },
++ {
++ V4L2_CID_RED_BALANCE, MMAL_CONTROL_TYPE_STD,
++ 1, 7999, 1000, 1, NULL,
++ MMAL_PARAMETER_CUSTOM_AWB_GAINS,
++ &ctrl_set_awb_gains,
++ false
++ },
++ {
++ V4L2_CID_BLUE_BALANCE, MMAL_CONTROL_TYPE_STD,
++ 1, 7999, 1000, 1, NULL,
++ MMAL_PARAMETER_CUSTOM_AWB_GAINS,
++ &ctrl_set_awb_gains,
++ false
++ },
++ {
++ V4L2_CID_COLORFX, MMAL_CONTROL_TYPE_STD_MENU,
++ 0, 15, V4L2_COLORFX_NONE, 0, NULL,
++ MMAL_PARAMETER_IMAGE_EFFECT,
++ &ctrl_set_image_effect,
++ false
++ },
++ {
++ V4L2_CID_COLORFX_CBCR, MMAL_CONTROL_TYPE_STD,
++ 0, 0xffff, 0x8080, 1, NULL,
++ MMAL_PARAMETER_COLOUR_EFFECT,
++ &ctrl_set_colfx,
++ false
++ },
++ {
++ V4L2_CID_ROTATE, MMAL_CONTROL_TYPE_STD,
++ 0, 360, 0, 90, NULL,
++ MMAL_PARAMETER_ROTATION,
++ &ctrl_set_rotate,
++ false
++ },
++ {
++ V4L2_CID_HFLIP, MMAL_CONTROL_TYPE_STD,
++ 0, 1, 0, 1, NULL,
++ MMAL_PARAMETER_MIRROR,
++ &ctrl_set_flip,
++ false
++ },
++ {
++ V4L2_CID_VFLIP, MMAL_CONTROL_TYPE_STD,
++ 0, 1, 0, 1, NULL,
++ MMAL_PARAMETER_MIRROR,
++ &ctrl_set_flip,
++ false
++ },
++ {
++ V4L2_CID_MPEG_VIDEO_BITRATE_MODE, MMAL_CONTROL_TYPE_STD_MENU,
++ 0, ARRAY_SIZE(bitrate_mode_qmenu) - 1,
++ 0, 0, bitrate_mode_qmenu,
++ MMAL_PARAMETER_RATECONTROL,
++ &ctrl_set_bitrate_mode,
++ false
++ },
++ {
++ V4L2_CID_MPEG_VIDEO_BITRATE, MMAL_CONTROL_TYPE_STD,
++ 25*1000, 25*1000*1000, 10*1000*1000, 25*1000, NULL,
++ MMAL_PARAMETER_VIDEO_BIT_RATE,
++ &ctrl_set_bitrate,
++ false
++ },
++ {
++ V4L2_CID_JPEG_COMPRESSION_QUALITY, MMAL_CONTROL_TYPE_STD,
++ 1, 100,
++ 30, 1, NULL,
++ MMAL_PARAMETER_JPEG_Q_FACTOR,
++ &ctrl_set_image_encode_output,
++ false
++ },
++ {
++ V4L2_CID_POWER_LINE_FREQUENCY, MMAL_CONTROL_TYPE_STD_MENU,
++ 0, ARRAY_SIZE(mains_freq_qmenu) - 1,
++ 1, 1, NULL,
++ MMAL_PARAMETER_FLICKER_AVOID,
++ &ctrl_set_flicker_avoidance,
++ false
++ },
++ {
++ V4L2_CID_MPEG_VIDEO_REPEAT_SEQ_HEADER, MMAL_CONTROL_TYPE_STD,
++ 0, 1,
++ 0, 1, NULL,
++ MMAL_PARAMETER_VIDEO_ENCODE_INLINE_HEADER,
++ &ctrl_set_video_encode_param_output,
++ true /* Errors ignored as requires latest firmware to work */
++ },
++ {
++ V4L2_CID_MPEG_VIDEO_H264_PROFILE,
++ MMAL_CONTROL_TYPE_STD_MENU,
++ ~((1<<V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE) |
++ (1<<V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE) |
++ (1<<V4L2_MPEG_VIDEO_H264_PROFILE_MAIN) |
++ (1<<V4L2_MPEG_VIDEO_H264_PROFILE_HIGH)),
++ V4L2_MPEG_VIDEO_H264_PROFILE_HIGH,
++ V4L2_MPEG_VIDEO_H264_PROFILE_HIGH, 1, NULL,
++ MMAL_PARAMETER_PROFILE,
++ &ctrl_set_video_encode_profile_level,
++ false
++ },
++ {
++ V4L2_CID_MPEG_VIDEO_H264_LEVEL, MMAL_CONTROL_TYPE_STD_MENU,
++ ~((1<<V4L2_MPEG_VIDEO_H264_LEVEL_1_0) |
++ (1<<V4L2_MPEG_VIDEO_H264_LEVEL_1B) |
++ (1<<V4L2_MPEG_VIDEO_H264_LEVEL_1_1) |
++ (1<<V4L2_MPEG_VIDEO_H264_LEVEL_1_2) |
++ (1<<V4L2_MPEG_VIDEO_H264_LEVEL_1_3) |
++ (1<<V4L2_MPEG_VIDEO_H264_LEVEL_2_0) |
++ (1<<V4L2_MPEG_VIDEO_H264_LEVEL_2_1) |
++ (1<<V4L2_MPEG_VIDEO_H264_LEVEL_2_2) |
++ (1<<V4L2_MPEG_VIDEO_H264_LEVEL_3_0) |
++ (1<<V4L2_MPEG_VIDEO_H264_LEVEL_3_1) |
++ (1<<V4L2_MPEG_VIDEO_H264_LEVEL_3_2) |
++ (1<<V4L2_MPEG_VIDEO_H264_LEVEL_4_0)),
++ V4L2_MPEG_VIDEO_H264_LEVEL_4_0,
++ V4L2_MPEG_VIDEO_H264_LEVEL_4_0, 1, NULL,
++ MMAL_PARAMETER_PROFILE,
++ &ctrl_set_video_encode_profile_level,
++ false
++ },
++ {
++ V4L2_CID_SCENE_MODE, MMAL_CONTROL_TYPE_STD_MENU,
++ -1, /* Min is computed at runtime */
++ V4L2_SCENE_MODE_TEXT,
++ V4L2_SCENE_MODE_NONE, 1, NULL,
++ MMAL_PARAMETER_PROFILE,
++ &ctrl_set_scene_mode,
++ false
++ },
++ {
++ V4L2_CID_MPEG_VIDEO_H264_I_PERIOD, MMAL_CONTROL_TYPE_STD,
++ 0, 0x7FFFFFFF, 60, 1, NULL,
++ MMAL_PARAMETER_INTRAPERIOD,
++ &ctrl_set_video_encode_param_output,
++ false
++ },
++};
++
++int bm2835_mmal_set_all_camera_controls(struct bm2835_mmal_dev *dev)
++{
++ int c;
++ int ret = 0;
++
++ for (c = 0; c < V4L2_CTRL_COUNT; c++) {
++ if ((dev->ctrls[c]) && (v4l2_ctrls[c].setter)) {
++ ret = v4l2_ctrls[c].setter(dev, dev->ctrls[c],
++ &v4l2_ctrls[c]);
++ if (!v4l2_ctrls[c].ignore_errors && ret) {
++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
++ "Failed when setting default values for ctrl %d\n",
++ c);
++ break;
++ }
++ }
++ }
++ return ret;
++}
++
++int set_framerate_params(struct bm2835_mmal_dev *dev)
++{
++ struct mmal_parameter_fps_range fps_range;
++ int ret;
++
++ if ((dev->exposure_mode_active != MMAL_PARAM_EXPOSUREMODE_OFF) &&
++ (dev->exp_auto_priority)) {
++ /* Variable FPS. Define min FPS as 1fps.
++ * Max as max defined FPS.
++ */
++ fps_range.fps_low.num = 1;
++ fps_range.fps_low.den = 1;
++ fps_range.fps_high.num = dev->capture.timeperframe.denominator;
++ fps_range.fps_high.den = dev->capture.timeperframe.numerator;
++ } else {
++ /* Fixed FPS - set min and max to be the same */
++ fps_range.fps_low.num = fps_range.fps_high.num =
++ dev->capture.timeperframe.denominator;
++ fps_range.fps_low.den = fps_range.fps_high.den =
++ dev->capture.timeperframe.numerator;
++ }
++
++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
++ "Set fps range to %d/%d to %d/%d\n",
++ fps_range.fps_low.num,
++ fps_range.fps_low.den,
++ fps_range.fps_high.num,
++ fps_range.fps_high.den
++ );
++
++ ret = vchiq_mmal_port_parameter_set(dev->instance,
++ &dev->component[MMAL_COMPONENT_CAMERA]->
++ output[MMAL_CAMERA_PORT_PREVIEW],
++ MMAL_PARAMETER_FPS_RANGE,
++ &fps_range, sizeof(fps_range));
++ ret += vchiq_mmal_port_parameter_set(dev->instance,
++ &dev->component[MMAL_COMPONENT_CAMERA]->
++ output[MMAL_CAMERA_PORT_VIDEO],
++ MMAL_PARAMETER_FPS_RANGE,
++ &fps_range, sizeof(fps_range));
++ ret += vchiq_mmal_port_parameter_set(dev->instance,
++ &dev->component[MMAL_COMPONENT_CAMERA]->
++ output[MMAL_CAMERA_PORT_CAPTURE],
++ MMAL_PARAMETER_FPS_RANGE,
++ &fps_range, sizeof(fps_range));
++ if (ret)
++ v4l2_dbg(0, bcm2835_v4l2_debug, &dev->v4l2_dev,
++ "Failed to set fps ret %d\n",
++ ret);
++
++ return ret;
++
++}
++
++int bm2835_mmal_init_controls(struct bm2835_mmal_dev *dev,
++ struct v4l2_ctrl_handler *hdl)
++{
++ int c;
++ const struct bm2835_mmal_v4l2_ctrl *ctrl;
++
++ v4l2_ctrl_handler_init(hdl, V4L2_CTRL_COUNT);
++
++ for (c = 0; c < V4L2_CTRL_COUNT; c++) {
++ ctrl = &v4l2_ctrls[c];
++
++ switch (ctrl->type) {
++ case MMAL_CONTROL_TYPE_STD:
++ dev->ctrls[c] = v4l2_ctrl_new_std(hdl,
++ &bm2835_mmal_ctrl_ops, ctrl->id,
++ ctrl->min, ctrl->max, ctrl->step, ctrl->def);
++ break;
++
++ case MMAL_CONTROL_TYPE_STD_MENU:
++ {
++ int mask = ctrl->min;
++
++ if (ctrl->id == V4L2_CID_SCENE_MODE) {
++ /* Special handling to work out the mask
++ * value based on the scene_configs array
++ * at runtime. Reduces the chance of
++ * mismatches.
++ */
++ int i;
++ mask = 1<<V4L2_SCENE_MODE_NONE;
++ for (i = 0;
++ i < ARRAY_SIZE(scene_configs);
++ i++) {
++ mask |= 1<<scene_configs[i].v4l2_scene;
++ }
++ mask = ~mask;
++ }
++
++ dev->ctrls[c] = v4l2_ctrl_new_std_menu(hdl,
++ &bm2835_mmal_ctrl_ops, ctrl->id,
++ ctrl->max, mask, ctrl->def);
++ break;
++ }
++
++ case MMAL_CONTROL_TYPE_INT_MENU:
++ dev->ctrls[c] = v4l2_ctrl_new_int_menu(hdl,
++ &bm2835_mmal_ctrl_ops, ctrl->id,
++ ctrl->max, ctrl->def, ctrl->imenu);
++ break;
++
++ case MMAL_CONTROL_TYPE_CLUSTER:
++ /* skip this entry when constructing controls */
++ continue;
++ }
++
++ if (hdl->error)
++ break;
++
++ dev->ctrls[c]->priv = (void *)ctrl;
++ }
++
++ if (hdl->error) {
++ pr_err("error adding control %d/%d id 0x%x\n", c,
++ V4L2_CTRL_COUNT, ctrl->id);
++ return hdl->error;
++ }
++
++ for (c = 0; c < V4L2_CTRL_COUNT; c++) {
++ ctrl = &v4l2_ctrls[c];
++
++ switch (ctrl->type) {
++ case MMAL_CONTROL_TYPE_CLUSTER:
++ v4l2_ctrl_auto_cluster(ctrl->min,
++ &dev->ctrls[c+1],
++ ctrl->max,
++ ctrl->def);
++ break;
++
++ case MMAL_CONTROL_TYPE_STD:
++ case MMAL_CONTROL_TYPE_STD_MENU:
++ case MMAL_CONTROL_TYPE_INT_MENU:
++ break;
++ }
++
++ }
++
++ return 0;
++}
+diff -Nur linux-4.1.3/drivers/media/platform/bcm2835/Kconfig linux-xbian-rpi/drivers/media/platform/bcm2835/Kconfig
+--- linux-4.1.3/drivers/media/platform/bcm2835/Kconfig 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/media/platform/bcm2835/Kconfig 2015-07-28 01:20:58.198038163 +0200
+@@ -0,0 +1,25 @@
++# Broadcom VideoCore IV v4l2 camera support
++
++config VIDEO_BCM2835
++ bool "Broadcom BCM2835 camera interface driver"
++ depends on VIDEO_V4L2 && (ARCH_BCM2708 || ARCH_BCM2709 || ARCH_BCM2835)
++ ---help---
++ Say Y here to enable camera host interface devices for
++ Broadcom BCM2835 SoC. This operates over the VCHIQ interface
++ to a service running on VideoCore.
++
++
++if VIDEO_BCM2835
++
++config VIDEO_BCM2835_MMAL
++ tristate "Broadcom BM2835 MMAL camera interface driver"
++ depends on BCM2708_VCHIQ
++ select VIDEOBUF2_VMALLOC
++ ---help---
++ This is a V4L2 driver for the Broadcom BCM2835 MMAL camera host interface
++
++ To compile this driver as a module, choose M here: the
++ module will be called bcm2835-v4l2.o
++
++
++endif # VIDEO_BM2835
+diff -Nur linux-4.1.3/drivers/media/platform/bcm2835/Makefile linux-xbian-rpi/drivers/media/platform/bcm2835/Makefile
+--- linux-4.1.3/drivers/media/platform/bcm2835/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/media/platform/bcm2835/Makefile 2015-07-28 01:20:58.198038163 +0200
+@@ -0,0 +1,5 @@
++bcm2835-v4l2-objs := bcm2835-camera.o controls.o mmal-vchiq.o
++
++obj-$(CONFIG_VIDEO_BCM2835_MMAL) += bcm2835-v4l2.o
++
++ccflags-$(CONFIG_VIDEO_BCM2835) += -Idrivers/misc/vc04_services -Idrivers/misc/vc04_services/interface/vcos/linuxkernel -D__VCCOREVER__=0x04000000
+diff -Nur linux-4.1.3/drivers/media/platform/bcm2835/mmal-common.h linux-xbian-rpi/drivers/media/platform/bcm2835/mmal-common.h
+--- linux-4.1.3/drivers/media/platform/bcm2835/mmal-common.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/media/platform/bcm2835/mmal-common.h 2015-07-28 01:20:58.198038163 +0200
+@@ -0,0 +1,52 @@
++/*
++ * Broadcom BM2835 V4L2 driver
++ *
++ * Copyright © 2013 Raspberry Pi (Trading) Ltd.
++ *
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file COPYING in the main directory of this archive
++ * for more details.
++ *
++ * Authors: Vincent Sanders <vincent.sanders@collabora.co.uk>
++ * Dave Stevenson <dsteve@broadcom.com>
++ * Simon Mellor <simellor@broadcom.com>
++ * Luke Diamand <luked@broadcom.com>
++ *
++ * MMAL structures
++ *
++ */
++
++#define MMAL_FOURCC(a, b, c, d) ((a) | (b << 8) | (c << 16) | (d << 24))
++#define MMAL_MAGIC MMAL_FOURCC('m', 'm', 'a', 'l')
++
++/** Special value signalling that time is not known */
++#define MMAL_TIME_UNKNOWN (1LL<<63)
++
++/* mapping between v4l and mmal video modes */
++struct mmal_fmt {
++ char *name;
++ u32 fourcc; /* v4l2 format id */
++ int flags; /* v4l2 flags field */
++ u32 mmal;
++ int depth;
++ u32 mmal_component; /* MMAL component index to be used to encode */
++};
++
++/* buffer for one video frame */
++struct mmal_buffer {
++ /* v4l buffer data -- must be first */
++ struct vb2_buffer vb;
++
++ /* list of buffers available */
++ struct list_head list;
++
++ void *buffer; /* buffer pointer */
++ unsigned long buffer_size; /* size of allocated buffer */
++};
++
++/* */
++struct mmal_colourfx {
++ s32 enable;
++ u32 u;
++ u32 v;
++};
+diff -Nur linux-4.1.3/drivers/media/platform/bcm2835/mmal-encodings.h linux-xbian-rpi/drivers/media/platform/bcm2835/mmal-encodings.h
+--- linux-4.1.3/drivers/media/platform/bcm2835/mmal-encodings.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/media/platform/bcm2835/mmal-encodings.h 2015-07-28 01:20:58.198038163 +0200
+@@ -0,0 +1,127 @@
++/*
++ * Broadcom BM2835 V4L2 driver
++ *
++ * Copyright © 2013 Raspberry Pi (Trading) Ltd.
++ *
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file COPYING in the main directory of this archive
++ * for more details.
++ *
++ * Authors: Vincent Sanders <vincent.sanders@collabora.co.uk>
++ * Dave Stevenson <dsteve@broadcom.com>
++ * Simon Mellor <simellor@broadcom.com>
++ * Luke Diamand <luked@broadcom.com>
++ */
++#ifndef MMAL_ENCODINGS_H
++#define MMAL_ENCODINGS_H
++
++#define MMAL_ENCODING_H264 MMAL_FOURCC('H', '2', '6', '4')
++#define MMAL_ENCODING_H263 MMAL_FOURCC('H', '2', '6', '3')
++#define MMAL_ENCODING_MP4V MMAL_FOURCC('M', 'P', '4', 'V')
++#define MMAL_ENCODING_MP2V MMAL_FOURCC('M', 'P', '2', 'V')
++#define MMAL_ENCODING_MP1V MMAL_FOURCC('M', 'P', '1', 'V')
++#define MMAL_ENCODING_WMV3 MMAL_FOURCC('W', 'M', 'V', '3')
++#define MMAL_ENCODING_WMV2 MMAL_FOURCC('W', 'M', 'V', '2')
++#define MMAL_ENCODING_WMV1 MMAL_FOURCC('W', 'M', 'V', '1')
++#define MMAL_ENCODING_WVC1 MMAL_FOURCC('W', 'V', 'C', '1')
++#define MMAL_ENCODING_VP8 MMAL_FOURCC('V', 'P', '8', ' ')
++#define MMAL_ENCODING_VP7 MMAL_FOURCC('V', 'P', '7', ' ')
++#define MMAL_ENCODING_VP6 MMAL_FOURCC('V', 'P', '6', ' ')
++#define MMAL_ENCODING_THEORA MMAL_FOURCC('T', 'H', 'E', 'O')
++#define MMAL_ENCODING_SPARK MMAL_FOURCC('S', 'P', 'R', 'K')
++#define MMAL_ENCODING_MJPEG MMAL_FOURCC('M', 'J', 'P', 'G')
++
++#define MMAL_ENCODING_JPEG MMAL_FOURCC('J', 'P', 'E', 'G')
++#define MMAL_ENCODING_GIF MMAL_FOURCC('G', 'I', 'F', ' ')
++#define MMAL_ENCODING_PNG MMAL_FOURCC('P', 'N', 'G', ' ')
++#define MMAL_ENCODING_PPM MMAL_FOURCC('P', 'P', 'M', ' ')
++#define MMAL_ENCODING_TGA MMAL_FOURCC('T', 'G', 'A', ' ')
++#define MMAL_ENCODING_BMP MMAL_FOURCC('B', 'M', 'P', ' ')
++
++#define MMAL_ENCODING_I420 MMAL_FOURCC('I', '4', '2', '0')
++#define MMAL_ENCODING_I420_SLICE MMAL_FOURCC('S', '4', '2', '0')
++#define MMAL_ENCODING_YV12 MMAL_FOURCC('Y', 'V', '1', '2')
++#define MMAL_ENCODING_I422 MMAL_FOURCC('I', '4', '2', '2')
++#define MMAL_ENCODING_I422_SLICE MMAL_FOURCC('S', '4', '2', '2')
++#define MMAL_ENCODING_YUYV MMAL_FOURCC('Y', 'U', 'Y', 'V')
++#define MMAL_ENCODING_YVYU MMAL_FOURCC('Y', 'V', 'Y', 'U')
++#define MMAL_ENCODING_UYVY MMAL_FOURCC('U', 'Y', 'V', 'Y')
++#define MMAL_ENCODING_VYUY MMAL_FOURCC('V', 'Y', 'U', 'Y')
++#define MMAL_ENCODING_NV12 MMAL_FOURCC('N', 'V', '1', '2')
++#define MMAL_ENCODING_NV21 MMAL_FOURCC('N', 'V', '2', '1')
++#define MMAL_ENCODING_ARGB MMAL_FOURCC('A', 'R', 'G', 'B')
++#define MMAL_ENCODING_RGBA MMAL_FOURCC('R', 'G', 'B', 'A')
++#define MMAL_ENCODING_ABGR MMAL_FOURCC('A', 'B', 'G', 'R')
++#define MMAL_ENCODING_BGRA MMAL_FOURCC('B', 'G', 'R', 'A')
++#define MMAL_ENCODING_RGB16 MMAL_FOURCC('R', 'G', 'B', '2')
++#define MMAL_ENCODING_RGB24 MMAL_FOURCC('R', 'G', 'B', '3')
++#define MMAL_ENCODING_RGB32 MMAL_FOURCC('R', 'G', 'B', '4')
++#define MMAL_ENCODING_BGR16 MMAL_FOURCC('B', 'G', 'R', '2')
++#define MMAL_ENCODING_BGR24 MMAL_FOURCC('B', 'G', 'R', '3')
++#define MMAL_ENCODING_BGR32 MMAL_FOURCC('B', 'G', 'R', '4')
++
++/** SAND Video (YUVUV128) format, native format understood by VideoCore.
++ * This format is *not* opaque - if requested you will receive full frames
++ * of YUV_UV video.
++ */
++#define MMAL_ENCODING_YUVUV128 MMAL_FOURCC('S', 'A', 'N', 'D')
++
++/** VideoCore opaque image format, image handles are returned to
++ * the host but not the actual image data.
++ */
++#define MMAL_ENCODING_OPAQUE MMAL_FOURCC('O', 'P', 'Q', 'V')
++
++/** An EGL image handle
++ */
++#define MMAL_ENCODING_EGL_IMAGE MMAL_FOURCC('E', 'G', 'L', 'I')
++
++/* }@ */
++
++/** \name Pre-defined audio encodings */
++/* @{ */
++#define MMAL_ENCODING_PCM_UNSIGNED_BE MMAL_FOURCC('P', 'C', 'M', 'U')
++#define MMAL_ENCODING_PCM_UNSIGNED_LE MMAL_FOURCC('p', 'c', 'm', 'u')
++#define MMAL_ENCODING_PCM_SIGNED_BE MMAL_FOURCC('P', 'C', 'M', 'S')
++#define MMAL_ENCODING_PCM_SIGNED_LE MMAL_FOURCC('p', 'c', 'm', 's')
++#define MMAL_ENCODING_PCM_FLOAT_BE MMAL_FOURCC('P', 'C', 'M', 'F')
++#define MMAL_ENCODING_PCM_FLOAT_LE MMAL_FOURCC('p', 'c', 'm', 'f')
++
++/* Pre-defined H264 encoding variants */
++
++/** ISO 14496-10 Annex B byte stream format */
++#define MMAL_ENCODING_VARIANT_H264_DEFAULT 0
++/** ISO 14496-15 AVC stream format */
++#define MMAL_ENCODING_VARIANT_H264_AVC1 MMAL_FOURCC('A', 'V', 'C', '1')
++/** Implicitly delineated NAL units without emulation prevention */
++#define MMAL_ENCODING_VARIANT_H264_RAW MMAL_FOURCC('R', 'A', 'W', ' ')
++
++
++/** \defgroup MmalColorSpace List of pre-defined video color spaces
++ * This defines a list of common color spaces. This list isn't exhaustive and
++ * is only provided as a convenience to avoid clients having to use FourCC
++ * codes directly. However components are allowed to define and use their own
++ * FourCC codes.
++ */
++/* @{ */
++
++/** Unknown color space */
++#define MMAL_COLOR_SPACE_UNKNOWN 0
++/** ITU-R BT.601-5 [SDTV] */
++#define MMAL_COLOR_SPACE_ITUR_BT601 MMAL_FOURCC('Y', '6', '0', '1')
++/** ITU-R BT.709-3 [HDTV] */
++#define MMAL_COLOR_SPACE_ITUR_BT709 MMAL_FOURCC('Y', '7', '0', '9')
++/** JPEG JFIF */
++#define MMAL_COLOR_SPACE_JPEG_JFIF MMAL_FOURCC('Y', 'J', 'F', 'I')
++/** Title 47 Code of Federal Regulations (2003) 73.682 (a) (20) */
++#define MMAL_COLOR_SPACE_FCC MMAL_FOURCC('Y', 'F', 'C', 'C')
++/** Society of Motion Picture and Television Engineers 240M (1999) */
++#define MMAL_COLOR_SPACE_SMPTE240M MMAL_FOURCC('Y', '2', '4', '0')
++/** ITU-R BT.470-2 System M */
++#define MMAL_COLOR_SPACE_BT470_2_M MMAL_FOURCC('Y', '_', '_', 'M')
++/** ITU-R BT.470-2 System BG */
++#define MMAL_COLOR_SPACE_BT470_2_BG MMAL_FOURCC('Y', '_', 'B', 'G')
++/** JPEG JFIF, but with 16..255 luma */
++#define MMAL_COLOR_SPACE_JFIF_Y16_255 MMAL_FOURCC('Y', 'Y', '1', '6')
++/* @} MmalColorSpace List */
++
++#endif /* MMAL_ENCODINGS_H */
+diff -Nur linux-4.1.3/drivers/media/platform/bcm2835/mmal-msg-common.h linux-xbian-rpi/drivers/media/platform/bcm2835/mmal-msg-common.h
+--- linux-4.1.3/drivers/media/platform/bcm2835/mmal-msg-common.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/media/platform/bcm2835/mmal-msg-common.h 2015-07-28 01:20:58.202023943 +0200
+@@ -0,0 +1,50 @@
++/*
++ * Broadcom BM2835 V4L2 driver
++ *
++ * Copyright © 2013 Raspberry Pi (Trading) Ltd.
++ *
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file COPYING in the main directory of this archive
++ * for more details.
++ *
++ * Authors: Vincent Sanders <vincent.sanders@collabora.co.uk>
++ * Dave Stevenson <dsteve@broadcom.com>
++ * Simon Mellor <simellor@broadcom.com>
++ * Luke Diamand <luked@broadcom.com>
++ */
++
++#ifndef MMAL_MSG_COMMON_H
++#define MMAL_MSG_COMMON_H
++
++enum mmal_msg_status {
++ MMAL_MSG_STATUS_SUCCESS = 0, /**< Success */
++ MMAL_MSG_STATUS_ENOMEM, /**< Out of memory */
++ MMAL_MSG_STATUS_ENOSPC, /**< Out of resources other than memory */
++ MMAL_MSG_STATUS_EINVAL, /**< Argument is invalid */
++ MMAL_MSG_STATUS_ENOSYS, /**< Function not implemented */
++ MMAL_MSG_STATUS_ENOENT, /**< No such file or directory */
++ MMAL_MSG_STATUS_ENXIO, /**< No such device or address */
++ MMAL_MSG_STATUS_EIO, /**< I/O error */
++ MMAL_MSG_STATUS_ESPIPE, /**< Illegal seek */
++ MMAL_MSG_STATUS_ECORRUPT, /**< Data is corrupt \attention */
++ MMAL_MSG_STATUS_ENOTREADY, /**< Component is not ready */
++ MMAL_MSG_STATUS_ECONFIG, /**< Component is not configured */
++ MMAL_MSG_STATUS_EISCONN, /**< Port is already connected */
++ MMAL_MSG_STATUS_ENOTCONN, /**< Port is disconnected */
++ MMAL_MSG_STATUS_EAGAIN, /**< Resource temporarily unavailable. */
++ MMAL_MSG_STATUS_EFAULT, /**< Bad address */
++};
++
++struct mmal_rect {
++ s32 x; /**< x coordinate (from left) */
++ s32 y; /**< y coordinate (from top) */
++ s32 width; /**< width */
++ s32 height; /**< height */
++};
++
++struct mmal_rational {
++ s32 num; /**< Numerator */
++ s32 den; /**< Denominator */
++};
++
++#endif /* MMAL_MSG_COMMON_H */
+diff -Nur linux-4.1.3/drivers/media/platform/bcm2835/mmal-msg-format.h linux-xbian-rpi/drivers/media/platform/bcm2835/mmal-msg-format.h
+--- linux-4.1.3/drivers/media/platform/bcm2835/mmal-msg-format.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/media/platform/bcm2835/mmal-msg-format.h 2015-07-28 01:20:58.202023943 +0200
+@@ -0,0 +1,81 @@
++/*
++ * Broadcom BM2835 V4L2 driver
++ *
++ * Copyright © 2013 Raspberry Pi (Trading) Ltd.
++ *
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file COPYING in the main directory of this archive
++ * for more details.
++ *
++ * Authors: Vincent Sanders <vincent.sanders@collabora.co.uk>
++ * Dave Stevenson <dsteve@broadcom.com>
++ * Simon Mellor <simellor@broadcom.com>
++ * Luke Diamand <luked@broadcom.com>
++ */
++
++#ifndef MMAL_MSG_FORMAT_H
++#define MMAL_MSG_FORMAT_H
++
++#include "mmal-msg-common.h"
++
++/* MMAL_ES_FORMAT_T */
++
++
++struct mmal_audio_format {
++ u32 channels; /**< Number of audio channels */
++ u32 sample_rate; /**< Sample rate */
++
++ u32 bits_per_sample; /**< Bits per sample */
++ u32 block_align; /**< Size of a block of data */
++};
++
++struct mmal_video_format {
++ u32 width; /**< Width of frame in pixels */
++ u32 height; /**< Height of frame in rows of pixels */
++ struct mmal_rect crop; /**< Visible region of the frame */
++ struct mmal_rational frame_rate; /**< Frame rate */
++ struct mmal_rational par; /**< Pixel aspect ratio */
++
++ /* FourCC specifying the color space of the video stream. See the
++ * \ref MmalColorSpace "pre-defined color spaces" for some examples.
++ */
++ u32 color_space;
++};
++
++struct mmal_subpicture_format {
++ u32 x_offset;
++ u32 y_offset;
++};
++
++union mmal_es_specific_format {
++ struct mmal_audio_format audio;
++ struct mmal_video_format video;
++ struct mmal_subpicture_format subpicture;
++};
++
++/** Definition of an elementary stream format (MMAL_ES_FORMAT_T) */
++struct mmal_es_format {
++ u32 type; /* enum mmal_es_type */
++
++ u32 encoding; /* FourCC specifying encoding of the elementary stream.*/
++ u32 encoding_variant; /* FourCC specifying the specific
++ * encoding variant of the elementary
++ * stream.
++ */
++
++ union mmal_es_specific_format *es; /* TODO: pointers in
++ * message serialisation?!?
++ */
++ /* Type specific
++ * information for the
++ * elementary stream
++ */
++
++ u32 bitrate; /**< Bitrate in bits per second */
++ u32 flags; /**< Flags describing properties of the elementary stream. */
++
++ u32 extradata_size; /**< Size of the codec specific data */
++ u8 *extradata; /**< Codec specific data */
++};
++
++#endif /* MMAL_MSG_FORMAT_H */
+diff -Nur linux-4.1.3/drivers/media/platform/bcm2835/mmal-msg.h linux-xbian-rpi/drivers/media/platform/bcm2835/mmal-msg.h
+--- linux-4.1.3/drivers/media/platform/bcm2835/mmal-msg.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/media/platform/bcm2835/mmal-msg.h 2015-07-28 01:20:58.202023943 +0200
+@@ -0,0 +1,404 @@
++/*
++ * Broadcom BM2835 V4L2 driver
++ *
++ * Copyright © 2013 Raspberry Pi (Trading) Ltd.
++ *
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file COPYING in the main directory of this archive
++ * for more details.
++ *
++ * Authors: Vincent Sanders <vincent.sanders@collabora.co.uk>
++ * Dave Stevenson <dsteve@broadcom.com>
++ * Simon Mellor <simellor@broadcom.com>
++ * Luke Diamand <luked@broadcom.com>
++ */
++
++/* all the data structures which serialise the MMAL protocol. note
++ * these are directly mapped onto the recived message data.
++ *
++ * BEWARE: They seem to *assume* pointers are u32 and that there is no
++ * structure padding!
++ *
++ * NOTE: this implementation uses kernel types to ensure sizes. Rather
++ * than assigning values to enums to force their size the
++ * implementation uses fixed size types and not the enums (though the
++ * comments have the actual enum type
++ */
++
++#define VC_MMAL_VER 15
++#define VC_MMAL_MIN_VER 10
++#define VC_MMAL_SERVER_NAME MAKE_FOURCC("mmal")
++
++/* max total message size is 512 bytes */
++#define MMAL_MSG_MAX_SIZE 512
++/* with six 32bit header elements max payload is therefore 488 bytes */
++#define MMAL_MSG_MAX_PAYLOAD 488
++
++#include "mmal-msg-common.h"
++#include "mmal-msg-format.h"
++#include "mmal-msg-port.h"
++
++enum mmal_msg_type {
++ MMAL_MSG_TYPE_QUIT = 1,
++ MMAL_MSG_TYPE_SERVICE_CLOSED,
++ MMAL_MSG_TYPE_GET_VERSION,
++ MMAL_MSG_TYPE_COMPONENT_CREATE,
++ MMAL_MSG_TYPE_COMPONENT_DESTROY, /* 5 */
++ MMAL_MSG_TYPE_COMPONENT_ENABLE,
++ MMAL_MSG_TYPE_COMPONENT_DISABLE,
++ MMAL_MSG_TYPE_PORT_INFO_GET,
++ MMAL_MSG_TYPE_PORT_INFO_SET,
++ MMAL_MSG_TYPE_PORT_ACTION, /* 10 */
++ MMAL_MSG_TYPE_BUFFER_FROM_HOST,
++ MMAL_MSG_TYPE_BUFFER_TO_HOST,
++ MMAL_MSG_TYPE_GET_STATS,
++ MMAL_MSG_TYPE_PORT_PARAMETER_SET,
++ MMAL_MSG_TYPE_PORT_PARAMETER_GET, /* 15 */
++ MMAL_MSG_TYPE_EVENT_TO_HOST,
++ MMAL_MSG_TYPE_GET_CORE_STATS_FOR_PORT,
++ MMAL_MSG_TYPE_OPAQUE_ALLOCATOR,
++ MMAL_MSG_TYPE_CONSUME_MEM,
++ MMAL_MSG_TYPE_LMK, /* 20 */
++ MMAL_MSG_TYPE_OPAQUE_ALLOCATOR_DESC,
++ MMAL_MSG_TYPE_DRM_GET_LHS32,
++ MMAL_MSG_TYPE_DRM_GET_TIME,
++ MMAL_MSG_TYPE_BUFFER_FROM_HOST_ZEROLEN,
++ MMAL_MSG_TYPE_PORT_FLUSH, /* 25 */
++ MMAL_MSG_TYPE_HOST_LOG,
++ MMAL_MSG_TYPE_MSG_LAST
++};
++
++/* port action request messages differ depending on the action type */
++enum mmal_msg_port_action_type {
++ MMAL_MSG_PORT_ACTION_TYPE_UNKNOWN = 0, /* Unkown action */
++ MMAL_MSG_PORT_ACTION_TYPE_ENABLE, /* Enable a port */
++ MMAL_MSG_PORT_ACTION_TYPE_DISABLE, /* Disable a port */
++ MMAL_MSG_PORT_ACTION_TYPE_FLUSH, /* Flush a port */
++ MMAL_MSG_PORT_ACTION_TYPE_CONNECT, /* Connect ports */
++ MMAL_MSG_PORT_ACTION_TYPE_DISCONNECT, /* Disconnect ports */
++ MMAL_MSG_PORT_ACTION_TYPE_SET_REQUIREMENTS, /* Set buffer requirements*/
++};
++
++struct mmal_msg_header {
++ u32 magic;
++ u32 type; /** enum mmal_msg_type */
++
++ /* Opaque handle to the control service */
++ struct mmal_control_service *control_service;
++
++ struct mmal_msg_context *context; /** a u32 per message context */
++ u32 status; /** The status of the vchiq operation */
++ u32 padding;
++};
++
++/* Send from VC to host to report version */
++struct mmal_msg_version {
++ u32 flags;
++ u32 major;
++ u32 minor;
++ u32 minimum;
++};
++
++/* request to VC to create component */
++struct mmal_msg_component_create {
++ void *client_component; /* component context */
++ char name[128];
++ u32 pid; /* For debug */
++};
++
++/* reply from VC to component creation request */
++struct mmal_msg_component_create_reply {
++ u32 status; /** enum mmal_msg_status - how does this differ to
++ * the one in the header?
++ */
++ u32 component_handle; /* VideoCore handle for component */
++ u32 input_num; /* Number of input ports */
++ u32 output_num; /* Number of output ports */
++ u32 clock_num; /* Number of clock ports */
++};
++
++/* request to VC to destroy a component */
++struct mmal_msg_component_destroy {
++ u32 component_handle;
++};
++
++struct mmal_msg_component_destroy_reply {
++ u32 status; /** The component destruction status */
++};
++
++
++/* request and reply to VC to enable a component */
++struct mmal_msg_component_enable {
++ u32 component_handle;
++};
++
++struct mmal_msg_component_enable_reply {
++ u32 status; /** The component enable status */
++};
++
++
++/* request and reply to VC to disable a component */
++struct mmal_msg_component_disable {
++ u32 component_handle;
++};
++
++struct mmal_msg_component_disable_reply {
++ u32 status; /** The component disable status */
++};
++
++/* request to VC to get port information */
++struct mmal_msg_port_info_get {
++ u32 component_handle; /* component handle port is associated with */
++ u32 port_type; /* enum mmal_msg_port_type */
++ u32 index; /* port index to query */
++};
++
++/* reply from VC to get port info request */
++struct mmal_msg_port_info_get_reply {
++ u32 status; /** enum mmal_msg_status */
++ u32 component_handle; /* component handle port is associated with */
++ u32 port_type; /* enum mmal_msg_port_type */
++ u32 port_index; /* port indexed in query */
++ s32 found; /* unused */
++ u32 port_handle; /**< Handle to use for this port */
++ struct mmal_port port;
++ struct mmal_es_format format; /* elementry stream format */
++ union mmal_es_specific_format es; /* es type specific data */
++ u8 extradata[MMAL_FORMAT_EXTRADATA_MAX_SIZE]; /* es extra data */
++};
++
++/* request to VC to set port information */
++struct mmal_msg_port_info_set {
++ u32 component_handle;
++ u32 port_type; /* enum mmal_msg_port_type */
++ u32 port_index; /* port indexed in query */
++ struct mmal_port port;
++ struct mmal_es_format format;
++ union mmal_es_specific_format es;
++ u8 extradata[MMAL_FORMAT_EXTRADATA_MAX_SIZE];
++};
++
++/* reply from VC to port info set request */
++struct mmal_msg_port_info_set_reply {
++ u32 status;
++ u32 component_handle; /* component handle port is associated with */
++ u32 port_type; /* enum mmal_msg_port_type */
++ u32 index; /* port indexed in query */
++ s32 found; /* unused */
++ u32 port_handle; /**< Handle to use for this port */
++ struct mmal_port port;
++ struct mmal_es_format format;
++ union mmal_es_specific_format es;
++ u8 extradata[MMAL_FORMAT_EXTRADATA_MAX_SIZE];
++};
++
++
++/* port action requests that take a mmal_port as a parameter */
++struct mmal_msg_port_action_port {
++ u32 component_handle;
++ u32 port_handle;
++ u32 action; /* enum mmal_msg_port_action_type */
++ struct mmal_port port;
++};
++
++/* port action requests that take handles as a parameter */
++struct mmal_msg_port_action_handle {
++ u32 component_handle;
++ u32 port_handle;
++ u32 action; /* enum mmal_msg_port_action_type */
++ u32 connect_component_handle;
++ u32 connect_port_handle;
++};
++
++struct mmal_msg_port_action_reply {
++ u32 status; /** The port action operation status */
++};
++
++
++
++
++/* MMAL buffer transfer */
++
++/** Size of space reserved in a buffer message for short messages. */
++#define MMAL_VC_SHORT_DATA 128
++
++/** Signals that the current payload is the end of the stream of data */
++#define MMAL_BUFFER_HEADER_FLAG_EOS (1<<0)
++/** Signals that the start of the current payload starts a frame */
++#define MMAL_BUFFER_HEADER_FLAG_FRAME_START (1<<1)
++/** Signals that the end of the current payload ends a frame */
++#define MMAL_BUFFER_HEADER_FLAG_FRAME_END (1<<2)
++/** Signals that the current payload contains only complete frames (>1) */
++#define MMAL_BUFFER_HEADER_FLAG_FRAME \
++ (MMAL_BUFFER_HEADER_FLAG_FRAME_START|MMAL_BUFFER_HEADER_FLAG_FRAME_END)
++/** Signals that the current payload is a keyframe (i.e. self decodable) */
++#define MMAL_BUFFER_HEADER_FLAG_KEYFRAME (1<<3)
++/** Signals a discontinuity in the stream of data (e.g. after a seek).
++ * Can be used for instance by a decoder to reset its state */
++#define MMAL_BUFFER_HEADER_FLAG_DISCONTINUITY (1<<4)
++/** Signals a buffer containing some kind of config data for the component
++ * (e.g. codec config data) */
++#define MMAL_BUFFER_HEADER_FLAG_CONFIG (1<<5)
++/** Signals an encrypted payload */
++#define MMAL_BUFFER_HEADER_FLAG_ENCRYPTED (1<<6)
++/** Signals a buffer containing side information */
++#define MMAL_BUFFER_HEADER_FLAG_CODECSIDEINFO (1<<7)
++/** Signals a buffer which is the snapshot/postview image from a stills
++ * capture
++ */
++#define MMAL_BUFFER_HEADER_FLAGS_SNAPSHOT (1<<8)
++/** Signals a buffer which contains data known to be corrupted */
++#define MMAL_BUFFER_HEADER_FLAG_CORRUPTED (1<<9)
++/** Signals that a buffer failed to be transmitted */
++#define MMAL_BUFFER_HEADER_FLAG_TRANSMISSION_FAILED (1<<10)
++
++struct mmal_driver_buffer {
++ u32 magic;
++ u32 component_handle;
++ u32 port_handle;
++ void *client_context;
++};
++
++/* buffer header */
++struct mmal_buffer_header {
++ struct mmal_buffer_header *next; /* next header */
++ void *priv; /* framework private data */
++ u32 cmd;
++ void *data;
++ u32 alloc_size;
++ u32 length;
++ u32 offset;
++ u32 flags;
++ s64 pts;
++ s64 dts;
++ void *type;
++ void *user_data;
++};
++
++struct mmal_buffer_header_type_specific {
++ union {
++ struct {
++ u32 planes;
++ u32 offset[4];
++ u32 pitch[4];
++ u32 flags;
++ } video;
++ } u;
++};
++
++struct mmal_msg_buffer_from_host {
++ /* The front 32 bytes of the buffer header are copied
++ * back to us in the reply to allow for context. This
++ * area is used to store two mmal_driver_buffer structures to
++ * allow for multiple concurrent service users.
++ */
++ /* control data */
++ struct mmal_driver_buffer drvbuf;
++
++ /* referenced control data for passthrough buffer management */
++ struct mmal_driver_buffer drvbuf_ref;
++ struct mmal_buffer_header buffer_header; /* buffer header itself */
++ struct mmal_buffer_header_type_specific buffer_header_type_specific;
++ s32 is_zero_copy;
++ s32 has_reference;
++
++ /** allows short data to be xfered in control message */
++ u32 payload_in_message;
++ u8 short_data[MMAL_VC_SHORT_DATA];
++};
++
++
++/* port parameter setting */
++
++#define MMAL_WORKER_PORT_PARAMETER_SPACE 96
++
++struct mmal_msg_port_parameter_set {
++ u32 component_handle; /* component */
++ u32 port_handle; /* port */
++ u32 id; /* Parameter ID */
++ u32 size; /* Parameter size */
++ uint32_t value[MMAL_WORKER_PORT_PARAMETER_SPACE];
++};
++
++struct mmal_msg_port_parameter_set_reply {
++ u32 status; /** enum mmal_msg_status todo: how does this
++ * differ to the one in the header?
++ */
++};
++
++/* port parameter getting */
++
++struct mmal_msg_port_parameter_get {
++ u32 component_handle; /* component */
++ u32 port_handle; /* port */
++ u32 id; /* Parameter ID */
++ u32 size; /* Parameter size */
++};
++
++struct mmal_msg_port_parameter_get_reply {
++ u32 status; /* Status of mmal_port_parameter_get call */
++ u32 id; /* Parameter ID */
++ u32 size; /* Parameter size */
++ uint32_t value[MMAL_WORKER_PORT_PARAMETER_SPACE];
++};
++
++/* event messages */
++#define MMAL_WORKER_EVENT_SPACE 256
++
++struct mmal_msg_event_to_host {
++ void *client_component; /* component context */
++
++ u32 port_type;
++ u32 port_num;
++
++ u32 cmd;
++ u32 length;
++ u8 data[MMAL_WORKER_EVENT_SPACE];
++ struct mmal_buffer_header *delayed_buffer;
++};
++
++/* all mmal messages are serialised through this structure */
++struct mmal_msg {
++ /* header */
++ struct mmal_msg_header h;
++ /* payload */
++ union {
++ struct mmal_msg_version version;
++
++ struct mmal_msg_component_create component_create;
++ struct mmal_msg_component_create_reply component_create_reply;
++
++ struct mmal_msg_component_destroy component_destroy;
++ struct mmal_msg_component_destroy_reply component_destroy_reply;
++
++ struct mmal_msg_component_enable component_enable;
++ struct mmal_msg_component_enable_reply component_enable_reply;
++
++ struct mmal_msg_component_disable component_disable;
++ struct mmal_msg_component_disable_reply component_disable_reply;
++
++ struct mmal_msg_port_info_get port_info_get;
++ struct mmal_msg_port_info_get_reply port_info_get_reply;
++
++ struct mmal_msg_port_info_set port_info_set;
++ struct mmal_msg_port_info_set_reply port_info_set_reply;
++
++ struct mmal_msg_port_action_port port_action_port;
++ struct mmal_msg_port_action_handle port_action_handle;
++ struct mmal_msg_port_action_reply port_action_reply;
++
++ struct mmal_msg_buffer_from_host buffer_from_host;
++
++ struct mmal_msg_port_parameter_set port_parameter_set;
++ struct mmal_msg_port_parameter_set_reply
++ port_parameter_set_reply;
++ struct mmal_msg_port_parameter_get
++ port_parameter_get;
++ struct mmal_msg_port_parameter_get_reply
++ port_parameter_get_reply;
++
++ struct mmal_msg_event_to_host event_to_host;
++
++ u8 payload[MMAL_MSG_MAX_PAYLOAD];
++ } u;
++};
+diff -Nur linux-4.1.3/drivers/media/platform/bcm2835/mmal-msg-port.h linux-xbian-rpi/drivers/media/platform/bcm2835/mmal-msg-port.h
+--- linux-4.1.3/drivers/media/platform/bcm2835/mmal-msg-port.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/media/platform/bcm2835/mmal-msg-port.h 2015-07-28 01:20:58.202023943 +0200
+@@ -0,0 +1,107 @@
++/*
++ * Broadcom BM2835 V4L2 driver
++ *
++ * Copyright © 2013 Raspberry Pi (Trading) Ltd.
++ *
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file COPYING in the main directory of this archive
++ * for more details.
++ *
++ * Authors: Vincent Sanders <vincent.sanders@collabora.co.uk>
++ * Dave Stevenson <dsteve@broadcom.com>
++ * Simon Mellor <simellor@broadcom.com>
++ * Luke Diamand <luked@broadcom.com>
++ */
++
++/* MMAL_PORT_TYPE_T */
++enum mmal_port_type {
++ MMAL_PORT_TYPE_UNKNOWN = 0, /**< Unknown port type */
++ MMAL_PORT_TYPE_CONTROL, /**< Control port */
++ MMAL_PORT_TYPE_INPUT, /**< Input port */
++ MMAL_PORT_TYPE_OUTPUT, /**< Output port */
++ MMAL_PORT_TYPE_CLOCK, /**< Clock port */
++};
++
++/** The port is pass-through and doesn't need buffer headers allocated */
++#define MMAL_PORT_CAPABILITY_PASSTHROUGH 0x01
++/** The port wants to allocate the buffer payloads.
++ * This signals a preference that payload allocation should be done
++ * on this port for efficiency reasons. */
++#define MMAL_PORT_CAPABILITY_ALLOCATION 0x02
++/** The port supports format change events.
++ * This applies to input ports and is used to let the client know
++ * whether the port supports being reconfigured via a format
++ * change event (i.e. without having to disable the port). */
++#define MMAL_PORT_CAPABILITY_SUPPORTS_EVENT_FORMAT_CHANGE 0x04
++
++/* mmal port structure (MMAL_PORT_T)
++ *
++ * most elements are informational only, the pointer values for
++ * interogation messages are generally provided as additional
++ * strucures within the message. When used to set values only teh
++ * buffer_num, buffer_size and userdata parameters are writable.
++ */
++struct mmal_port {
++ void *priv; /* Private member used by the framework */
++ const char *name; /* Port name. Used for debugging purposes (RO) */
++
++ u32 type; /* Type of the port (RO) enum mmal_port_type */
++ u16 index; /* Index of the port in its type list (RO) */
++ u16 index_all; /* Index of the port in the list of all ports (RO) */
++
++ u32 is_enabled; /* Indicates whether the port is enabled or not (RO) */
++ struct mmal_es_format *format; /* Format of the elementary stream */
++
++ u32 buffer_num_min; /* Minimum number of buffers the port
++ * requires (RO). This is set by the
++ * component.
++ */
++
++ u32 buffer_size_min; /* Minimum size of buffers the port
++ * requires (RO). This is set by the
++ * component.
++ */
++
++ u32 buffer_alignment_min; /* Minimum alignment requirement for
++ * the buffers (RO). A value of
++ * zero means no special alignment
++ * requirements. This is set by the
++ * component.
++ */
++
++ u32 buffer_num_recommended; /* Number of buffers the port
++ * recommends for optimal
++ * performance (RO). A value of
++ * zero means no special
++ * recommendation. This is set
++ * by the component.
++ */
++
++ u32 buffer_size_recommended; /* Size of buffers the port
++ * recommends for optimal
++ * performance (RO). A value of
++ * zero means no special
++ * recommendation. This is set
++ * by the component.
++ */
++
++ u32 buffer_num; /* Actual number of buffers the port will use.
++ * This is set by the client.
++ */
++
++ u32 buffer_size; /* Actual maximum size of the buffers that
++ * will be sent to the port. This is set by
++ * the client.
++ */
++
++ void *component; /* Component this port belongs to (Read Only) */
++
++ void *userdata; /* Field reserved for use by the client */
++
++ u32 capabilities; /* Flags describing the capabilities of a
++ * port (RO). Bitwise combination of \ref
++ * portcapabilities "Port capabilities"
++ * values.
++ */
++
++};
+diff -Nur linux-4.1.3/drivers/media/platform/bcm2835/mmal-parameters.h linux-xbian-rpi/drivers/media/platform/bcm2835/mmal-parameters.h
+--- linux-4.1.3/drivers/media/platform/bcm2835/mmal-parameters.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/media/platform/bcm2835/mmal-parameters.h 2015-07-28 01:20:58.281739526 +0200
+@@ -0,0 +1,656 @@
++/*
++ * Broadcom BM2835 V4L2 driver
++ *
++ * Copyright © 2013 Raspberry Pi (Trading) Ltd.
++ *
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file COPYING in the main directory of this archive
++ * for more details.
++ *
++ * Authors: Vincent Sanders <vincent.sanders@collabora.co.uk>
++ * Dave Stevenson <dsteve@broadcom.com>
++ * Simon Mellor <simellor@broadcom.com>
++ * Luke Diamand <luked@broadcom.com>
++ */
++
++/* common parameters */
++
++/** @name Parameter groups
++ * Parameters are divided into groups, and then allocated sequentially within
++ * a group using an enum.
++ * @{
++ */
++
++/** Common parameter ID group, used with many types of component. */
++#define MMAL_PARAMETER_GROUP_COMMON (0<<16)
++/** Camera-specific parameter ID group. */
++#define MMAL_PARAMETER_GROUP_CAMERA (1<<16)
++/** Video-specific parameter ID group. */
++#define MMAL_PARAMETER_GROUP_VIDEO (2<<16)
++/** Audio-specific parameter ID group. */
++#define MMAL_PARAMETER_GROUP_AUDIO (3<<16)
++/** Clock-specific parameter ID group. */
++#define MMAL_PARAMETER_GROUP_CLOCK (4<<16)
++/** Miracast-specific parameter ID group. */
++#define MMAL_PARAMETER_GROUP_MIRACAST (5<<16)
++
++/* Common parameters */
++enum mmal_parameter_common_type {
++ MMAL_PARAMETER_UNUSED /**< Never a valid parameter ID */
++ = MMAL_PARAMETER_GROUP_COMMON,
++ MMAL_PARAMETER_SUPPORTED_ENCODINGS, /**< MMAL_PARAMETER_ENCODING_T */
++ MMAL_PARAMETER_URI, /**< MMAL_PARAMETER_URI_T */
++
++ /** MMAL_PARAMETER_CHANGE_EVENT_REQUEST_T */
++ MMAL_PARAMETER_CHANGE_EVENT_REQUEST,
++
++ /** MMAL_PARAMETER_BOOLEAN_T */
++ MMAL_PARAMETER_ZERO_COPY,
++
++ /**< MMAL_PARAMETER_BUFFER_REQUIREMENTS_T */
++ MMAL_PARAMETER_BUFFER_REQUIREMENTS,
++
++ MMAL_PARAMETER_STATISTICS, /**< MMAL_PARAMETER_STATISTICS_T */
++ MMAL_PARAMETER_CORE_STATISTICS, /**< MMAL_PARAMETER_CORE_STATISTICS_T */
++ MMAL_PARAMETER_MEM_USAGE, /**< MMAL_PARAMETER_MEM_USAGE_T */
++ MMAL_PARAMETER_BUFFER_FLAG_FILTER, /**< MMAL_PARAMETER_UINT32_T */
++ MMAL_PARAMETER_SEEK, /**< MMAL_PARAMETER_SEEK_T */
++ MMAL_PARAMETER_POWERMON_ENABLE, /**< MMAL_PARAMETER_BOOLEAN_T */
++ MMAL_PARAMETER_LOGGING, /**< MMAL_PARAMETER_LOGGING_T */
++ MMAL_PARAMETER_SYSTEM_TIME, /**< MMAL_PARAMETER_UINT64_T */
++ MMAL_PARAMETER_NO_IMAGE_PADDING /**< MMAL_PARAMETER_BOOLEAN_T */
++};
++
++/* camera parameters */
++
++enum mmal_parameter_camera_type {
++ /* 0 */
++ /** @ref MMAL_PARAMETER_THUMBNAIL_CONFIG_T */
++ MMAL_PARAMETER_THUMBNAIL_CONFIGURATION
++ = MMAL_PARAMETER_GROUP_CAMERA,
++ MMAL_PARAMETER_CAPTURE_QUALITY, /**< Unused? */
++ MMAL_PARAMETER_ROTATION, /**< @ref MMAL_PARAMETER_INT32_T */
++ MMAL_PARAMETER_EXIF_DISABLE, /**< @ref MMAL_PARAMETER_BOOLEAN_T */
++ MMAL_PARAMETER_EXIF, /**< @ref MMAL_PARAMETER_EXIF_T */
++ MMAL_PARAMETER_AWB_MODE, /**< @ref MMAL_PARAM_AWBMODE_T */
++ MMAL_PARAMETER_IMAGE_EFFECT, /**< @ref MMAL_PARAMETER_IMAGEFX_T */
++ MMAL_PARAMETER_COLOUR_EFFECT, /**< @ref MMAL_PARAMETER_COLOURFX_T */
++ MMAL_PARAMETER_FLICKER_AVOID, /**< @ref MMAL_PARAMETER_FLICKERAVOID_T */
++ MMAL_PARAMETER_FLASH, /**< @ref MMAL_PARAMETER_FLASH_T */
++ MMAL_PARAMETER_REDEYE, /**< @ref MMAL_PARAMETER_REDEYE_T */
++ MMAL_PARAMETER_FOCUS, /**< @ref MMAL_PARAMETER_FOCUS_T */
++ MMAL_PARAMETER_FOCAL_LENGTHS, /**< Unused? */
++ MMAL_PARAMETER_EXPOSURE_COMP, /**< @ref MMAL_PARAMETER_INT32_T */
++ MMAL_PARAMETER_ZOOM, /**< @ref MMAL_PARAMETER_SCALEFACTOR_T */
++ MMAL_PARAMETER_MIRROR, /**< @ref MMAL_PARAMETER_MIRROR_T */
++
++ /* 0x10 */
++ MMAL_PARAMETER_CAMERA_NUM, /**< @ref MMAL_PARAMETER_UINT32_T */
++ MMAL_PARAMETER_CAPTURE, /**< @ref MMAL_PARAMETER_BOOLEAN_T */
++ MMAL_PARAMETER_EXPOSURE_MODE, /**< @ref MMAL_PARAMETER_EXPOSUREMODE_T */
++ MMAL_PARAMETER_EXP_METERING_MODE, /**< @ref MMAL_PARAMETER_EXPOSUREMETERINGMODE_T */
++ MMAL_PARAMETER_FOCUS_STATUS, /**< @ref MMAL_PARAMETER_FOCUS_STATUS_T */
++ MMAL_PARAMETER_CAMERA_CONFIG, /**< @ref MMAL_PARAMETER_CAMERA_CONFIG_T */
++ MMAL_PARAMETER_CAPTURE_STATUS, /**< @ref MMAL_PARAMETER_CAPTURE_STATUS_T */
++ MMAL_PARAMETER_FACE_TRACK, /**< @ref MMAL_PARAMETER_FACE_TRACK_T */
++ MMAL_PARAMETER_DRAW_BOX_FACES_AND_FOCUS, /**< @ref MMAL_PARAMETER_BOOLEAN_T */
++ MMAL_PARAMETER_JPEG_Q_FACTOR, /**< @ref MMAL_PARAMETER_UINT32_T */
++ MMAL_PARAMETER_FRAME_RATE, /**< @ref MMAL_PARAMETER_FRAME_RATE_T */
++ MMAL_PARAMETER_USE_STC, /**< @ref MMAL_PARAMETER_CAMERA_STC_MODE_T */
++ MMAL_PARAMETER_CAMERA_INFO, /**< @ref MMAL_PARAMETER_CAMERA_INFO_T */
++ MMAL_PARAMETER_VIDEO_STABILISATION, /**< @ref MMAL_PARAMETER_BOOLEAN_T */
++ MMAL_PARAMETER_FACE_TRACK_RESULTS, /**< @ref MMAL_PARAMETER_FACE_TRACK_RESULTS_T */
++ MMAL_PARAMETER_ENABLE_RAW_CAPTURE, /**< @ref MMAL_PARAMETER_BOOLEAN_T */
++
++ /* 0x20 */
++ MMAL_PARAMETER_DPF_FILE, /**< @ref MMAL_PARAMETER_URI_T */
++ MMAL_PARAMETER_ENABLE_DPF_FILE, /**< @ref MMAL_PARAMETER_BOOLEAN_T */
++ MMAL_PARAMETER_DPF_FAIL_IS_FATAL, /**< @ref MMAL_PARAMETER_BOOLEAN_T */
++ MMAL_PARAMETER_CAPTURE_MODE, /**< @ref MMAL_PARAMETER_CAPTUREMODE_T */
++ MMAL_PARAMETER_FOCUS_REGIONS, /**< @ref MMAL_PARAMETER_FOCUS_REGIONS_T */
++ MMAL_PARAMETER_INPUT_CROP, /**< @ref MMAL_PARAMETER_INPUT_CROP_T */
++ MMAL_PARAMETER_SENSOR_INFORMATION, /**< @ref MMAL_PARAMETER_SENSOR_INFORMATION_T */
++ MMAL_PARAMETER_FLASH_SELECT, /**< @ref MMAL_PARAMETER_FLASH_SELECT_T */
++ MMAL_PARAMETER_FIELD_OF_VIEW, /**< @ref MMAL_PARAMETER_FIELD_OF_VIEW_T */
++ MMAL_PARAMETER_HIGH_DYNAMIC_RANGE, /**< @ref MMAL_PARAMETER_BOOLEAN_T */
++ MMAL_PARAMETER_DYNAMIC_RANGE_COMPRESSION, /**< @ref MMAL_PARAMETER_DRC_T */
++ MMAL_PARAMETER_ALGORITHM_CONTROL, /**< @ref MMAL_PARAMETER_ALGORITHM_CONTROL_T */
++ MMAL_PARAMETER_SHARPNESS, /**< @ref MMAL_PARAMETER_RATIONAL_T */
++ MMAL_PARAMETER_CONTRAST, /**< @ref MMAL_PARAMETER_RATIONAL_T */
++ MMAL_PARAMETER_BRIGHTNESS, /**< @ref MMAL_PARAMETER_RATIONAL_T */
++ MMAL_PARAMETER_SATURATION, /**< @ref MMAL_PARAMETER_RATIONAL_T */
++
++ /* 0x30 */
++ MMAL_PARAMETER_ISO, /**< @ref MMAL_PARAMETER_UINT32_T */
++ MMAL_PARAMETER_ANTISHAKE, /**< @ref MMAL_PARAMETER_BOOLEAN_T */
++
++ /** @ref MMAL_PARAMETER_IMAGEFX_PARAMETERS_T */
++ MMAL_PARAMETER_IMAGE_EFFECT_PARAMETERS,
++
++ /** @ref MMAL_PARAMETER_BOOLEAN_T */
++ MMAL_PARAMETER_CAMERA_BURST_CAPTURE,
++
++ /** @ref MMAL_PARAMETER_UINT32_T */
++ MMAL_PARAMETER_CAMERA_MIN_ISO,
++
++ /** @ref MMAL_PARAMETER_CAMERA_USE_CASE_T */
++ MMAL_PARAMETER_CAMERA_USE_CASE,
++
++ /**< @ref MMAL_PARAMETER_BOOLEAN_T */
++ MMAL_PARAMETER_CAPTURE_STATS_PASS,
++
++ /** @ref MMAL_PARAMETER_UINT32_T */
++ MMAL_PARAMETER_CAMERA_CUSTOM_SENSOR_CONFIG,
++
++ /** @ref MMAL_PARAMETER_BOOLEAN_T */
++ MMAL_PARAMETER_ENABLE_REGISTER_FILE,
++
++ /** @ref MMAL_PARAMETER_BOOLEAN_T */
++ MMAL_PARAMETER_REGISTER_FAIL_IS_FATAL,
++
++ /** @ref MMAL_PARAMETER_CONFIGFILE_T */
++ MMAL_PARAMETER_CONFIGFILE_REGISTERS,
++
++ /** @ref MMAL_PARAMETER_CONFIGFILE_CHUNK_T */
++ MMAL_PARAMETER_CONFIGFILE_CHUNK_REGISTERS,
++ MMAL_PARAMETER_JPEG_ATTACH_LOG, /**< @ref MMAL_PARAMETER_BOOLEAN_T */
++ MMAL_PARAMETER_ZERO_SHUTTER_LAG, /**< @ref MMAL_PARAMETER_ZEROSHUTTERLAG_T */
++ MMAL_PARAMETER_FPS_RANGE, /**< @ref MMAL_PARAMETER_FPS_RANGE_T */
++ MMAL_PARAMETER_CAPTURE_EXPOSURE_COMP, /**< @ref MMAL_PARAMETER_INT32_T */
++
++ /* 0x40 */
++ MMAL_PARAMETER_SW_SHARPEN_DISABLE, /**< @ref MMAL_PARAMETER_BOOLEAN_T */
++ MMAL_PARAMETER_FLASH_REQUIRED, /**< @ref MMAL_PARAMETER_BOOLEAN_T */
++ MMAL_PARAMETER_SW_SATURATION_DISABLE, /**< @ref MMAL_PARAMETER_BOOLEAN_T */
++ MMAL_PARAMETER_SHUTTER_SPEED, /**< Takes a @ref MMAL_PARAMETER_UINT32_T */
++ MMAL_PARAMETER_CUSTOM_AWB_GAINS, /**< Takes a @ref MMAL_PARAMETER_AWB_GAINS_T */
++};
++
++struct mmal_parameter_rational {
++ s32 num; /**< Numerator */
++ s32 den; /**< Denominator */
++};
++
++enum mmal_parameter_camera_config_timestamp_mode {
++ MMAL_PARAM_TIMESTAMP_MODE_ZERO = 0, /* Always timestamp frames as 0 */
++ MMAL_PARAM_TIMESTAMP_MODE_RAW_STC, /* Use the raw STC value
++ * for the frame timestamp
++ */
++ MMAL_PARAM_TIMESTAMP_MODE_RESET_STC, /* Use the STC timestamp
++ * but subtract the
++ * timestamp of the first
++ * frame sent to give a
++ * zero based timestamp.
++ */
++};
++
++struct mmal_parameter_fps_range {
++ /**< Low end of the permitted framerate range */
++ struct mmal_parameter_rational fps_low;
++ /**< High end of the permitted framerate range */
++ struct mmal_parameter_rational fps_high;
++};
++
++
++/* camera configuration parameter */
++struct mmal_parameter_camera_config {
++ /* Parameters for setting up the image pools */
++ u32 max_stills_w; /* Max size of stills capture */
++ u32 max_stills_h;
++ u32 stills_yuv422; /* Allow YUV422 stills capture */
++ u32 one_shot_stills; /* Continuous or one shot stills captures. */
++
++ u32 max_preview_video_w; /* Max size of the preview or video
++ * capture frames
++ */
++ u32 max_preview_video_h;
++ u32 num_preview_video_frames;
++
++ /** Sets the height of the circular buffer for stills capture. */
++ u32 stills_capture_circular_buffer_height;
++
++ /** Allows preview/encode to resume as fast as possible after the stills
++ * input frame has been received, and then processes the still frame in
++ * the background whilst preview/encode has resumed.
++ * Actual mode is controlled by MMAL_PARAMETER_CAPTURE_MODE.
++ */
++ u32 fast_preview_resume;
++
++ /** Selects algorithm for timestamping frames if
++ * there is no clock component connected.
++ * enum mmal_parameter_camera_config_timestamp_mode
++ */
++ s32 use_stc_timestamp;
++};
++
++
++enum mmal_parameter_exposuremode {
++ MMAL_PARAM_EXPOSUREMODE_OFF,
++ MMAL_PARAM_EXPOSUREMODE_AUTO,
++ MMAL_PARAM_EXPOSUREMODE_NIGHT,
++ MMAL_PARAM_EXPOSUREMODE_NIGHTPREVIEW,
++ MMAL_PARAM_EXPOSUREMODE_BACKLIGHT,
++ MMAL_PARAM_EXPOSUREMODE_SPOTLIGHT,
++ MMAL_PARAM_EXPOSUREMODE_SPORTS,
++ MMAL_PARAM_EXPOSUREMODE_SNOW,
++ MMAL_PARAM_EXPOSUREMODE_BEACH,
++ MMAL_PARAM_EXPOSUREMODE_VERYLONG,
++ MMAL_PARAM_EXPOSUREMODE_FIXEDFPS,
++ MMAL_PARAM_EXPOSUREMODE_ANTISHAKE,
++ MMAL_PARAM_EXPOSUREMODE_FIREWORKS,
++};
++
++enum mmal_parameter_exposuremeteringmode {
++ MMAL_PARAM_EXPOSUREMETERINGMODE_AVERAGE,
++ MMAL_PARAM_EXPOSUREMETERINGMODE_SPOT,
++ MMAL_PARAM_EXPOSUREMETERINGMODE_BACKLIT,
++ MMAL_PARAM_EXPOSUREMETERINGMODE_MATRIX,
++};
++
++enum mmal_parameter_awbmode {
++ MMAL_PARAM_AWBMODE_OFF,
++ MMAL_PARAM_AWBMODE_AUTO,
++ MMAL_PARAM_AWBMODE_SUNLIGHT,
++ MMAL_PARAM_AWBMODE_CLOUDY,
++ MMAL_PARAM_AWBMODE_SHADE,
++ MMAL_PARAM_AWBMODE_TUNGSTEN,
++ MMAL_PARAM_AWBMODE_FLUORESCENT,
++ MMAL_PARAM_AWBMODE_INCANDESCENT,
++ MMAL_PARAM_AWBMODE_FLASH,
++ MMAL_PARAM_AWBMODE_HORIZON,
++};
++
++enum mmal_parameter_imagefx {
++ MMAL_PARAM_IMAGEFX_NONE,
++ MMAL_PARAM_IMAGEFX_NEGATIVE,
++ MMAL_PARAM_IMAGEFX_SOLARIZE,
++ MMAL_PARAM_IMAGEFX_POSTERIZE,
++ MMAL_PARAM_IMAGEFX_WHITEBOARD,
++ MMAL_PARAM_IMAGEFX_BLACKBOARD,
++ MMAL_PARAM_IMAGEFX_SKETCH,
++ MMAL_PARAM_IMAGEFX_DENOISE,
++ MMAL_PARAM_IMAGEFX_EMBOSS,
++ MMAL_PARAM_IMAGEFX_OILPAINT,
++ MMAL_PARAM_IMAGEFX_HATCH,
++ MMAL_PARAM_IMAGEFX_GPEN,
++ MMAL_PARAM_IMAGEFX_PASTEL,
++ MMAL_PARAM_IMAGEFX_WATERCOLOUR,
++ MMAL_PARAM_IMAGEFX_FILM,
++ MMAL_PARAM_IMAGEFX_BLUR,
++ MMAL_PARAM_IMAGEFX_SATURATION,
++ MMAL_PARAM_IMAGEFX_COLOURSWAP,
++ MMAL_PARAM_IMAGEFX_WASHEDOUT,
++ MMAL_PARAM_IMAGEFX_POSTERISE,
++ MMAL_PARAM_IMAGEFX_COLOURPOINT,
++ MMAL_PARAM_IMAGEFX_COLOURBALANCE,
++ MMAL_PARAM_IMAGEFX_CARTOON,
++};
++
++enum MMAL_PARAM_FLICKERAVOID_T {
++ MMAL_PARAM_FLICKERAVOID_OFF,
++ MMAL_PARAM_FLICKERAVOID_AUTO,
++ MMAL_PARAM_FLICKERAVOID_50HZ,
++ MMAL_PARAM_FLICKERAVOID_60HZ,
++ MMAL_PARAM_FLICKERAVOID_MAX = 0x7FFFFFFF
++};
++
++struct mmal_parameter_awbgains {
++ struct mmal_parameter_rational r_gain; /**< Red gain */
++ struct mmal_parameter_rational b_gain; /**< Blue gain */
++};
++
++/** Manner of video rate control */
++enum mmal_parameter_rate_control_mode {
++ MMAL_VIDEO_RATECONTROL_DEFAULT,
++ MMAL_VIDEO_RATECONTROL_VARIABLE,
++ MMAL_VIDEO_RATECONTROL_CONSTANT,
++ MMAL_VIDEO_RATECONTROL_VARIABLE_SKIP_FRAMES,
++ MMAL_VIDEO_RATECONTROL_CONSTANT_SKIP_FRAMES
++};
++
++enum mmal_video_profile {
++ MMAL_VIDEO_PROFILE_H263_BASELINE,
++ MMAL_VIDEO_PROFILE_H263_H320CODING,
++ MMAL_VIDEO_PROFILE_H263_BACKWARDCOMPATIBLE,
++ MMAL_VIDEO_PROFILE_H263_ISWV2,
++ MMAL_VIDEO_PROFILE_H263_ISWV3,
++ MMAL_VIDEO_PROFILE_H263_HIGHCOMPRESSION,
++ MMAL_VIDEO_PROFILE_H263_INTERNET,
++ MMAL_VIDEO_PROFILE_H263_INTERLACE,
++ MMAL_VIDEO_PROFILE_H263_HIGHLATENCY,
++ MMAL_VIDEO_PROFILE_MP4V_SIMPLE,
++ MMAL_VIDEO_PROFILE_MP4V_SIMPLESCALABLE,
++ MMAL_VIDEO_PROFILE_MP4V_CORE,
++ MMAL_VIDEO_PROFILE_MP4V_MAIN,
++ MMAL_VIDEO_PROFILE_MP4V_NBIT,
++ MMAL_VIDEO_PROFILE_MP4V_SCALABLETEXTURE,
++ MMAL_VIDEO_PROFILE_MP4V_SIMPLEFACE,
++ MMAL_VIDEO_PROFILE_MP4V_SIMPLEFBA,
++ MMAL_VIDEO_PROFILE_MP4V_BASICANIMATED,
++ MMAL_VIDEO_PROFILE_MP4V_HYBRID,
++ MMAL_VIDEO_PROFILE_MP4V_ADVANCEDREALTIME,
++ MMAL_VIDEO_PROFILE_MP4V_CORESCALABLE,
++ MMAL_VIDEO_PROFILE_MP4V_ADVANCEDCODING,
++ MMAL_VIDEO_PROFILE_MP4V_ADVANCEDCORE,
++ MMAL_VIDEO_PROFILE_MP4V_ADVANCEDSCALABLE,
++ MMAL_VIDEO_PROFILE_MP4V_ADVANCEDSIMPLE,
++ MMAL_VIDEO_PROFILE_H264_BASELINE,
++ MMAL_VIDEO_PROFILE_H264_MAIN,
++ MMAL_VIDEO_PROFILE_H264_EXTENDED,
++ MMAL_VIDEO_PROFILE_H264_HIGH,
++ MMAL_VIDEO_PROFILE_H264_HIGH10,
++ MMAL_VIDEO_PROFILE_H264_HIGH422,
++ MMAL_VIDEO_PROFILE_H264_HIGH444,
++ MMAL_VIDEO_PROFILE_H264_CONSTRAINED_BASELINE,
++ MMAL_VIDEO_PROFILE_DUMMY = 0x7FFFFFFF
++};
++
++enum mmal_video_level {
++ MMAL_VIDEO_LEVEL_H263_10,
++ MMAL_VIDEO_LEVEL_H263_20,
++ MMAL_VIDEO_LEVEL_H263_30,
++ MMAL_VIDEO_LEVEL_H263_40,
++ MMAL_VIDEO_LEVEL_H263_45,
++ MMAL_VIDEO_LEVEL_H263_50,
++ MMAL_VIDEO_LEVEL_H263_60,
++ MMAL_VIDEO_LEVEL_H263_70,
++ MMAL_VIDEO_LEVEL_MP4V_0,
++ MMAL_VIDEO_LEVEL_MP4V_0b,
++ MMAL_VIDEO_LEVEL_MP4V_1,
++ MMAL_VIDEO_LEVEL_MP4V_2,
++ MMAL_VIDEO_LEVEL_MP4V_3,
++ MMAL_VIDEO_LEVEL_MP4V_4,
++ MMAL_VIDEO_LEVEL_MP4V_4a,
++ MMAL_VIDEO_LEVEL_MP4V_5,
++ MMAL_VIDEO_LEVEL_MP4V_6,
++ MMAL_VIDEO_LEVEL_H264_1,
++ MMAL_VIDEO_LEVEL_H264_1b,
++ MMAL_VIDEO_LEVEL_H264_11,
++ MMAL_VIDEO_LEVEL_H264_12,
++ MMAL_VIDEO_LEVEL_H264_13,
++ MMAL_VIDEO_LEVEL_H264_2,
++ MMAL_VIDEO_LEVEL_H264_21,
++ MMAL_VIDEO_LEVEL_H264_22,
++ MMAL_VIDEO_LEVEL_H264_3,
++ MMAL_VIDEO_LEVEL_H264_31,
++ MMAL_VIDEO_LEVEL_H264_32,
++ MMAL_VIDEO_LEVEL_H264_4,
++ MMAL_VIDEO_LEVEL_H264_41,
++ MMAL_VIDEO_LEVEL_H264_42,
++ MMAL_VIDEO_LEVEL_H264_5,
++ MMAL_VIDEO_LEVEL_H264_51,
++ MMAL_VIDEO_LEVEL_DUMMY = 0x7FFFFFFF
++};
++
++struct mmal_parameter_video_profile {
++ enum mmal_video_profile profile;
++ enum mmal_video_level level;
++};
++
++/* video parameters */
++
++enum mmal_parameter_video_type {
++ /** @ref MMAL_DISPLAYREGION_T */
++ MMAL_PARAMETER_DISPLAYREGION = MMAL_PARAMETER_GROUP_VIDEO,
++
++ /** @ref MMAL_PARAMETER_VIDEO_PROFILE_T */
++ MMAL_PARAMETER_SUPPORTED_PROFILES,
++
++ /** @ref MMAL_PARAMETER_VIDEO_PROFILE_T */
++ MMAL_PARAMETER_PROFILE,
++
++ /** @ref MMAL_PARAMETER_UINT32_T */
++ MMAL_PARAMETER_INTRAPERIOD,
++
++ /** @ref MMAL_PARAMETER_VIDEO_RATECONTROL_T */
++ MMAL_PARAMETER_RATECONTROL,
++
++ /** @ref MMAL_PARAMETER_VIDEO_NALUNITFORMAT_T */
++ MMAL_PARAMETER_NALUNITFORMAT,
++
++ /** @ref MMAL_PARAMETER_BOOLEAN_T */
++ MMAL_PARAMETER_MINIMISE_FRAGMENTATION,
++
++ /** @ref MMAL_PARAMETER_UINT32_T.
++ * Setting the value to zero resets to the default (one slice per frame).
++ */
++ MMAL_PARAMETER_MB_ROWS_PER_SLICE,
++
++ /** @ref MMAL_PARAMETER_VIDEO_LEVEL_EXTENSION_T */
++ MMAL_PARAMETER_VIDEO_LEVEL_EXTENSION,
++
++ /** @ref MMAL_PARAMETER_VIDEO_EEDE_ENABLE_T */
++ MMAL_PARAMETER_VIDEO_EEDE_ENABLE,
++
++ /** @ref MMAL_PARAMETER_VIDEO_EEDE_LOSSRATE_T */
++ MMAL_PARAMETER_VIDEO_EEDE_LOSSRATE,
++
++ /** @ref MMAL_PARAMETER_BOOLEAN_T. Request an I-frame. */
++ MMAL_PARAMETER_VIDEO_REQUEST_I_FRAME,
++ /** @ref MMAL_PARAMETER_VIDEO_INTRA_REFRESH_T */
++ MMAL_PARAMETER_VIDEO_INTRA_REFRESH,
++
++ /** @ref MMAL_PARAMETER_BOOLEAN_T. */
++ MMAL_PARAMETER_VIDEO_IMMUTABLE_INPUT,
++
++ /** @ref MMAL_PARAMETER_UINT32_T. Run-time bit rate control */
++ MMAL_PARAMETER_VIDEO_BIT_RATE,
++
++ /** @ref MMAL_PARAMETER_FRAME_RATE_T */
++ MMAL_PARAMETER_VIDEO_FRAME_RATE,
++
++ /** @ref MMAL_PARAMETER_UINT32_T. */
++ MMAL_PARAMETER_VIDEO_ENCODE_MIN_QUANT,
++
++ /** @ref MMAL_PARAMETER_UINT32_T. */
++ MMAL_PARAMETER_VIDEO_ENCODE_MAX_QUANT,
++
++ /** @ref MMAL_PARAMETER_VIDEO_ENCODE_RC_MODEL_T. */
++ MMAL_PARAMETER_VIDEO_ENCODE_RC_MODEL,
++
++ MMAL_PARAMETER_EXTRA_BUFFERS, /**< @ref MMAL_PARAMETER_UINT32_T. */
++ /** @ref MMAL_PARAMETER_UINT32_T.
++ * Changing this parameter from the default can reduce frame rate
++ * because image buffers need to be re-pitched.
++ */
++ MMAL_PARAMETER_VIDEO_ALIGN_HORIZ,
++
++ /** @ref MMAL_PARAMETER_UINT32_T.
++ * Changing this parameter from the default can reduce frame rate
++ * because image buffers need to be re-pitched.
++ */
++ MMAL_PARAMETER_VIDEO_ALIGN_VERT,
++
++ /** @ref MMAL_PARAMETER_BOOLEAN_T. */
++ MMAL_PARAMETER_VIDEO_DROPPABLE_PFRAMES,
++
++ /** @ref MMAL_PARAMETER_UINT32_T. */
++ MMAL_PARAMETER_VIDEO_ENCODE_INITIAL_QUANT,
++
++ /**< @ref MMAL_PARAMETER_UINT32_T. */
++ MMAL_PARAMETER_VIDEO_ENCODE_QP_P,
++
++ /**< @ref MMAL_PARAMETER_UINT32_T. */
++ MMAL_PARAMETER_VIDEO_ENCODE_RC_SLICE_DQUANT,
++
++ /** @ref MMAL_PARAMETER_UINT32_T */
++ MMAL_PARAMETER_VIDEO_ENCODE_FRAME_LIMIT_BITS,
++
++ /** @ref MMAL_PARAMETER_UINT32_T. */
++ MMAL_PARAMETER_VIDEO_ENCODE_PEAK_RATE,
++
++ /* H264 specific parameters */
++
++ /** @ref MMAL_PARAMETER_BOOLEAN_T. */
++ MMAL_PARAMETER_VIDEO_ENCODE_H264_DISABLE_CABAC,
++
++ /** @ref MMAL_PARAMETER_BOOLEAN_T. */
++ MMAL_PARAMETER_VIDEO_ENCODE_H264_LOW_LATENCY,
++
++ /** @ref MMAL_PARAMETER_BOOLEAN_T. */
++ MMAL_PARAMETER_VIDEO_ENCODE_H264_AU_DELIMITERS,
++
++ /** @ref MMAL_PARAMETER_UINT32_T. */
++ MMAL_PARAMETER_VIDEO_ENCODE_H264_DEBLOCK_IDC,
++
++ /** @ref MMAL_PARAMETER_VIDEO_ENCODER_H264_MB_INTRA_MODES_T. */
++ MMAL_PARAMETER_VIDEO_ENCODE_H264_MB_INTRA_MODE,
++
++ /** @ref MMAL_PARAMETER_BOOLEAN_T */
++ MMAL_PARAMETER_VIDEO_ENCODE_HEADER_ON_OPEN,
++
++ /** @ref MMAL_PARAMETER_BOOLEAN_T */
++ MMAL_PARAMETER_VIDEO_ENCODE_PRECODE_FOR_QP,
++
++ /** @ref MMAL_PARAMETER_VIDEO_DRM_INIT_INFO_T. */
++ MMAL_PARAMETER_VIDEO_DRM_INIT_INFO,
++
++ /** @ref MMAL_PARAMETER_BOOLEAN_T */
++ MMAL_PARAMETER_VIDEO_TIMESTAMP_FIFO,
++
++ /** @ref MMAL_PARAMETER_BOOLEAN_T */
++ MMAL_PARAMETER_VIDEO_DECODE_ERROR_CONCEALMENT,
++
++ /** @ref MMAL_PARAMETER_VIDEO_DRM_PROTECT_BUFFER_T. */
++ MMAL_PARAMETER_VIDEO_DRM_PROTECT_BUFFER,
++
++ /** @ref MMAL_PARAMETER_BYTES_T */
++ MMAL_PARAMETER_VIDEO_DECODE_CONFIG_VD3,
++
++ /**< @ref MMAL_PARAMETER_BOOLEAN_T */
++ MMAL_PARAMETER_VIDEO_ENCODE_H264_VCL_HRD_PARAMETERS,
++
++ /**< @ref MMAL_PARAMETER_BOOLEAN_T */
++ MMAL_PARAMETER_VIDEO_ENCODE_H264_LOW_DELAY_HRD_FLAG,
++
++ /**< @ref MMAL_PARAMETER_BOOLEAN_T */
++ MMAL_PARAMETER_VIDEO_ENCODE_INLINE_HEADER
++};
++
++/** Valid mirror modes */
++enum mmal_parameter_mirror {
++ MMAL_PARAM_MIRROR_NONE,
++ MMAL_PARAM_MIRROR_VERTICAL,
++ MMAL_PARAM_MIRROR_HORIZONTAL,
++ MMAL_PARAM_MIRROR_BOTH,
++};
++
++enum mmal_parameter_displaytransform {
++ MMAL_DISPLAY_ROT0 = 0,
++ MMAL_DISPLAY_MIRROR_ROT0 = 1,
++ MMAL_DISPLAY_MIRROR_ROT180 = 2,
++ MMAL_DISPLAY_ROT180 = 3,
++ MMAL_DISPLAY_MIRROR_ROT90 = 4,
++ MMAL_DISPLAY_ROT270 = 5,
++ MMAL_DISPLAY_ROT90 = 6,
++ MMAL_DISPLAY_MIRROR_ROT270 = 7,
++};
++
++enum mmal_parameter_displaymode {
++ MMAL_DISPLAY_MODE_FILL = 0,
++ MMAL_DISPLAY_MODE_LETTERBOX = 1,
++};
++
++enum mmal_parameter_displayset {
++ MMAL_DISPLAY_SET_NONE = 0,
++ MMAL_DISPLAY_SET_NUM = 1,
++ MMAL_DISPLAY_SET_FULLSCREEN = 2,
++ MMAL_DISPLAY_SET_TRANSFORM = 4,
++ MMAL_DISPLAY_SET_DEST_RECT = 8,
++ MMAL_DISPLAY_SET_SRC_RECT = 0x10,
++ MMAL_DISPLAY_SET_MODE = 0x20,
++ MMAL_DISPLAY_SET_PIXEL = 0x40,
++ MMAL_DISPLAY_SET_NOASPECT = 0x80,
++ MMAL_DISPLAY_SET_LAYER = 0x100,
++ MMAL_DISPLAY_SET_COPYPROTECT = 0x200,
++ MMAL_DISPLAY_SET_ALPHA = 0x400,
++};
++
++struct mmal_parameter_displayregion {
++ /** Bitfield that indicates which fields are set and should be
++ * used. All other fields will maintain their current value.
++ * \ref MMAL_DISPLAYSET_T defines the bits that can be
++ * combined.
++ */
++ u32 set;
++
++ /** Describes the display output device, with 0 typically
++ * being a directly connected LCD display. The actual values
++ * will depend on the hardware. Code using hard-wired numbers
++ * (e.g. 2) is certain to fail.
++ */
++
++ u32 display_num;
++ /** Indicates that we are using the full device screen area,
++ * rather than a window of the display. If zero, then
++ * dest_rect is used to specify a region of the display to
++ * use.
++ */
++
++ s32 fullscreen;
++ /** Indicates any rotation or flipping used to map frames onto
++ * the natural display orientation.
++ */
++ u32 transform; /* enum mmal_parameter_displaytransform */
++
++ /** Where to display the frame within the screen, if
++ * fullscreen is zero.
++ */
++ struct vchiq_mmal_rect dest_rect;
++
++ /** Indicates which area of the frame to display. If all
++ * values are zero, the whole frame will be used.
++ */
++ struct vchiq_mmal_rect src_rect;
++
++ /** If set to non-zero, indicates that any display scaling
++ * should disregard the aspect ratio of the frame region being
++ * displayed.
++ */
++ s32 noaspect;
++
++ /** Indicates how the image should be scaled to fit the
++ * display. \code MMAL_DISPLAY_MODE_FILL \endcode indicates
++ * that the image should fill the screen by potentially
++ * cropping the frames. Setting \code mode \endcode to \code
++ * MMAL_DISPLAY_MODE_LETTERBOX \endcode indicates that all the
++ * source region should be displayed and black bars added if
++ * necessary.
++ */
++ u32 mode; /* enum mmal_parameter_displaymode */
++
++ /** If non-zero, defines the width of a source pixel relative
++ * to \code pixel_y \endcode. If zero, then pixels default to
++ * being square.
++ */
++ u32 pixel_x;
++
++ /** If non-zero, defines the height of a source pixel relative
++ * to \code pixel_x \endcode. If zero, then pixels default to
++ * being square.
++ */
++ u32 pixel_y;
++
++ /** Sets the relative depth of the images, with greater values
++ * being in front of smaller values.
++ */
++ u32 layer;
++
++ /** Set to non-zero to ensure copy protection is used on
++ * output.
++ */
++ s32 copyprotect_required;
++
++ /** Level of opacity of the layer, where zero is fully
++ * transparent and 255 is fully opaque.
++ */
++ u32 alpha;
++};
++
++#define MMAL_MAX_IMAGEFX_PARAMETERS 5
++
++struct mmal_parameter_imagefx_parameters {
++ enum mmal_parameter_imagefx effect;
++ u32 num_effect_params;
++ u32 effect_parameter[MMAL_MAX_IMAGEFX_PARAMETERS];
++};
+diff -Nur linux-4.1.3/drivers/media/platform/bcm2835/mmal-vchiq.c linux-xbian-rpi/drivers/media/platform/bcm2835/mmal-vchiq.c
+--- linux-4.1.3/drivers/media/platform/bcm2835/mmal-vchiq.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/media/platform/bcm2835/mmal-vchiq.c 2015-07-28 01:20:58.281739526 +0200
+@@ -0,0 +1,1916 @@
++/*
++ * Broadcom BM2835 V4L2 driver
++ *
++ * Copyright © 2013 Raspberry Pi (Trading) Ltd.
++ *
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file COPYING in the main directory of this archive
++ * for more details.
++ *
++ * Authors: Vincent Sanders <vincent.sanders@collabora.co.uk>
++ * Dave Stevenson <dsteve@broadcom.com>
++ * Simon Mellor <simellor@broadcom.com>
++ * Luke Diamand <luked@broadcom.com>
++ *
++ * V4L2 driver MMAL vchiq interface code
++ */
++
++#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
++
++#include <linux/errno.h>
++#include <linux/kernel.h>
++#include <linux/mutex.h>
++#include <linux/mm.h>
++#include <linux/slab.h>
++#include <linux/completion.h>
++#include <linux/vmalloc.h>
++#include <asm/cacheflush.h>
++#include <media/videobuf2-vmalloc.h>
++
++#include "mmal-common.h"
++#include "mmal-vchiq.h"
++#include "mmal-msg.h"
++
++#define USE_VCHIQ_ARM
++#include "interface/vchi/vchi.h"
++
++/* maximum number of components supported */
++#define VCHIQ_MMAL_MAX_COMPONENTS 4
++
++/*#define FULL_MSG_DUMP 1*/
++
++#ifdef DEBUG
++static const char *const msg_type_names[] = {
++ "UNKNOWN",
++ "QUIT",
++ "SERVICE_CLOSED",
++ "GET_VERSION",
++ "COMPONENT_CREATE",
++ "COMPONENT_DESTROY",
++ "COMPONENT_ENABLE",
++ "COMPONENT_DISABLE",
++ "PORT_INFO_GET",
++ "PORT_INFO_SET",
++ "PORT_ACTION",
++ "BUFFER_FROM_HOST",
++ "BUFFER_TO_HOST",
++ "GET_STATS",
++ "PORT_PARAMETER_SET",
++ "PORT_PARAMETER_GET",
++ "EVENT_TO_HOST",
++ "GET_CORE_STATS_FOR_PORT",
++ "OPAQUE_ALLOCATOR",
++ "CONSUME_MEM",
++ "LMK",
++ "OPAQUE_ALLOCATOR_DESC",
++ "DRM_GET_LHS32",
++ "DRM_GET_TIME",
++ "BUFFER_FROM_HOST_ZEROLEN",
++ "PORT_FLUSH",
++ "HOST_LOG",
++};
++#endif
++
++static const char *const port_action_type_names[] = {
++ "UNKNOWN",
++ "ENABLE",
++ "DISABLE",
++ "FLUSH",
++ "CONNECT",
++ "DISCONNECT",
++ "SET_REQUIREMENTS",
++};
++
++#if defined(DEBUG)
++#if defined(FULL_MSG_DUMP)
++#define DBG_DUMP_MSG(MSG, MSG_LEN, TITLE) \
++ do { \
++ pr_debug(TITLE" type:%s(%d) length:%d\n", \
++ msg_type_names[(MSG)->h.type], \
++ (MSG)->h.type, (MSG_LEN)); \
++ print_hex_dump(KERN_DEBUG, "<<h: ", DUMP_PREFIX_OFFSET, \
++ 16, 4, (MSG), \
++ sizeof(struct mmal_msg_header), 1); \
++ print_hex_dump(KERN_DEBUG, "<<p: ", DUMP_PREFIX_OFFSET, \
++ 16, 4, \
++ ((u8 *)(MSG)) + sizeof(struct mmal_msg_header),\
++ (MSG_LEN) - sizeof(struct mmal_msg_header), 1); \
++ } while (0)
++#else
++#define DBG_DUMP_MSG(MSG, MSG_LEN, TITLE) \
++ { \
++ pr_debug(TITLE" type:%s(%d) length:%d\n", \
++ msg_type_names[(MSG)->h.type], \
++ (MSG)->h.type, (MSG_LEN)); \
++ }
++#endif
++#else
++#define DBG_DUMP_MSG(MSG, MSG_LEN, TITLE)
++#endif
++
++/* normal message context */
++struct mmal_msg_context {
++ union {
++ struct {
++ /* work struct for defered callback - must come first */
++ struct work_struct work;
++ /* mmal instance */
++ struct vchiq_mmal_instance *instance;
++ /* mmal port */
++ struct vchiq_mmal_port *port;
++ /* actual buffer used to store bulk reply */
++ struct mmal_buffer *buffer;
++ /* amount of buffer used */
++ unsigned long buffer_used;
++ /* MMAL buffer flags */
++ u32 mmal_flags;
++ /* Presentation and Decode timestamps */
++ s64 pts;
++ s64 dts;
++
++ int status; /* context status */
++
++ } bulk; /* bulk data */
++
++ struct {
++ /* message handle to release */
++ VCHI_HELD_MSG_T msg_handle;
++ /* pointer to received message */
++ struct mmal_msg *msg;
++ /* received message length */
++ u32 msg_len;
++ /* completion upon reply */
++ struct completion cmplt;
++ } sync; /* synchronous response */
++ } u;
++
++};
++
++struct vchiq_mmal_instance {
++ VCHI_SERVICE_HANDLE_T handle;
++
++ /* ensure serialised access to service */
++ struct mutex vchiq_mutex;
++
++ /* ensure serialised access to bulk operations */
++ struct mutex bulk_mutex;
++
++ /* vmalloc page to receive scratch bulk xfers into */
++ void *bulk_scratch;
++
++ /* component to use next */
++ int component_idx;
++ struct vchiq_mmal_component component[VCHIQ_MMAL_MAX_COMPONENTS];
++};
++
++static struct mmal_msg_context *get_msg_context(struct vchiq_mmal_instance
++ *instance)
++{
++ struct mmal_msg_context *msg_context;
++
++ /* todo: should this be allocated from a pool to avoid kmalloc */
++ msg_context = kmalloc(sizeof(*msg_context), GFP_KERNEL);
++ memset(msg_context, 0, sizeof(*msg_context));
++
++ return msg_context;
++}
++
++static void release_msg_context(struct mmal_msg_context *msg_context)
++{
++ kfree(msg_context);
++}
++
++/* deals with receipt of event to host message */
++static void event_to_host_cb(struct vchiq_mmal_instance *instance,
++ struct mmal_msg *msg, u32 msg_len)
++{
++ pr_debug("unhandled event\n");
++ pr_debug("component:%p port type:%d num:%d cmd:0x%x length:%d\n",
++ msg->u.event_to_host.client_component,
++ msg->u.event_to_host.port_type,
++ msg->u.event_to_host.port_num,
++ msg->u.event_to_host.cmd, msg->u.event_to_host.length);
++}
++
++/* workqueue scheduled callback
++ *
++ * we do this because it is important we do not call any other vchiq
++ * sync calls from witin the message delivery thread
++ */
++static void buffer_work_cb(struct work_struct *work)
++{
++ struct mmal_msg_context *msg_context = (struct mmal_msg_context *)work;
++
++ msg_context->u.bulk.port->buffer_cb(msg_context->u.bulk.instance,
++ msg_context->u.bulk.port,
++ msg_context->u.bulk.status,
++ msg_context->u.bulk.buffer,
++ msg_context->u.bulk.buffer_used,
++ msg_context->u.bulk.mmal_flags,
++ msg_context->u.bulk.dts,
++ msg_context->u.bulk.pts);
++
++ /* release message context */
++ release_msg_context(msg_context);
++}
++
++/* enqueue a bulk receive for a given message context */
++static int bulk_receive(struct vchiq_mmal_instance *instance,
++ struct mmal_msg *msg,
++ struct mmal_msg_context *msg_context)
++{
++ unsigned long rd_len;
++ unsigned long flags = 0;
++ int ret;
++
++ /* bulk mutex stops other bulk operations while we have a
++ * receive in progress - released in callback
++ */
++ ret = mutex_lock_interruptible(&instance->bulk_mutex);
++ if (ret != 0)
++ return ret;
++
++ rd_len = msg->u.buffer_from_host.buffer_header.length;
++
++ /* take buffer from queue */
++ spin_lock_irqsave(&msg_context->u.bulk.port->slock, flags);
++ if (list_empty(&msg_context->u.bulk.port->buffers)) {
++ spin_unlock_irqrestore(&msg_context->u.bulk.port->slock, flags);
++ pr_err("buffer list empty trying to submit bulk receive\n");
++
++ /* todo: this is a serious error, we should never have
++ * commited a buffer_to_host operation to the mmal
++ * port without the buffer to back it up (underflow
++ * handling) and there is no obvious way to deal with
++ * this - how is the mmal servie going to react when
++ * we fail to do the xfer and reschedule a buffer when
++ * it arrives? perhaps a starved flag to indicate a
++ * waiting bulk receive?
++ */
++
++ mutex_unlock(&instance->bulk_mutex);
++
++ return -EINVAL;
++ }
++
++ msg_context->u.bulk.buffer =
++ list_entry(msg_context->u.bulk.port->buffers.next,
++ struct mmal_buffer, list);
++ list_del(&msg_context->u.bulk.buffer->list);
++
++ spin_unlock_irqrestore(&msg_context->u.bulk.port->slock, flags);
++
++ /* ensure we do not overrun the available buffer */
++ if (rd_len > msg_context->u.bulk.buffer->buffer_size) {
++ rd_len = msg_context->u.bulk.buffer->buffer_size;
++ pr_warn("short read as not enough receive buffer space\n");
++ /* todo: is this the correct response, what happens to
++ * the rest of the message data?
++ */
++ }
++
++ /* store length */
++ msg_context->u.bulk.buffer_used = rd_len;
++ msg_context->u.bulk.mmal_flags =
++ msg->u.buffer_from_host.buffer_header.flags;
++ msg_context->u.bulk.dts = msg->u.buffer_from_host.buffer_header.dts;
++ msg_context->u.bulk.pts = msg->u.buffer_from_host.buffer_header.pts;
++
++ // only need to flush L1 cache here, as VCHIQ takes care of the L2
++ // cache.
++ __cpuc_flush_dcache_area(msg_context->u.bulk.buffer->buffer, rd_len);
++
++ /* queue the bulk submission */
++ vchi_service_use(instance->handle);
++ ret = vchi_bulk_queue_receive(instance->handle,
++ msg_context->u.bulk.buffer->buffer,
++ /* Actual receive needs to be a multiple
++ * of 4 bytes
++ */
++ (rd_len + 3) & ~3,
++ VCHI_FLAGS_CALLBACK_WHEN_OP_COMPLETE |
++ VCHI_FLAGS_BLOCK_UNTIL_QUEUED,
++ msg_context);
++
++ vchi_service_release(instance->handle);
++
++ if (ret != 0) {
++ /* callback will not be clearing the mutex */
++ mutex_unlock(&instance->bulk_mutex);
++ }
++
++ return ret;
++}
++
++/* enque a dummy bulk receive for a given message context */
++static int dummy_bulk_receive(struct vchiq_mmal_instance *instance,
++ struct mmal_msg_context *msg_context)
++{
++ int ret;
++
++ /* bulk mutex stops other bulk operations while we have a
++ * receive in progress - released in callback
++ */
++ ret = mutex_lock_interruptible(&instance->bulk_mutex);
++ if (ret != 0)
++ return ret;
++
++ /* zero length indicates this was a dummy transfer */
++ msg_context->u.bulk.buffer_used = 0;
++
++ /* queue the bulk submission */
++ vchi_service_use(instance->handle);
++
++ ret = vchi_bulk_queue_receive(instance->handle,
++ instance->bulk_scratch,
++ 8,
++ VCHI_FLAGS_CALLBACK_WHEN_OP_COMPLETE |
++ VCHI_FLAGS_BLOCK_UNTIL_QUEUED,
++ msg_context);
++
++ vchi_service_release(instance->handle);
++
++ if (ret != 0) {
++ /* callback will not be clearing the mutex */
++ mutex_unlock(&instance->bulk_mutex);
++ }
++
++ return ret;
++}
++
++/* data in message, memcpy from packet into output buffer */
++static int inline_receive(struct vchiq_mmal_instance *instance,
++ struct mmal_msg *msg,
++ struct mmal_msg_context *msg_context)
++{
++ unsigned long flags = 0;
++
++ /* take buffer from queue */
++ spin_lock_irqsave(&msg_context->u.bulk.port->slock, flags);
++ if (list_empty(&msg_context->u.bulk.port->buffers)) {
++ spin_unlock_irqrestore(&msg_context->u.bulk.port->slock, flags);
++ pr_err("buffer list empty trying to receive inline\n");
++
++ /* todo: this is a serious error, we should never have
++ * commited a buffer_to_host operation to the mmal
++ * port without the buffer to back it up (with
++ * underflow handling) and there is no obvious way to
++ * deal with this. Less bad than the bulk case as we
++ * can just drop this on the floor but...unhelpful
++ */
++ return -EINVAL;
++ }
++
++ msg_context->u.bulk.buffer =
++ list_entry(msg_context->u.bulk.port->buffers.next,
++ struct mmal_buffer, list);
++ list_del(&msg_context->u.bulk.buffer->list);
++
++ spin_unlock_irqrestore(&msg_context->u.bulk.port->slock, flags);
++
++ memcpy(msg_context->u.bulk.buffer->buffer,
++ msg->u.buffer_from_host.short_data,
++ msg->u.buffer_from_host.payload_in_message);
++
++ msg_context->u.bulk.buffer_used =
++ msg->u.buffer_from_host.payload_in_message;
++
++ return 0;
++}
++
++/* queue the buffer availability with MMAL_MSG_TYPE_BUFFER_FROM_HOST */
++static int
++buffer_from_host(struct vchiq_mmal_instance *instance,
++ struct vchiq_mmal_port *port, struct mmal_buffer *buf)
++{
++ struct mmal_msg_context *msg_context;
++ struct mmal_msg m;
++ int ret;
++
++ pr_debug("instance:%p buffer:%p\n", instance->handle, buf);
++
++ /* bulk mutex stops other bulk operations while we
++ * have a receive in progress
++ */
++ if (mutex_lock_interruptible(&instance->bulk_mutex))
++ return -EINTR;
++
++ /* get context */
++ msg_context = get_msg_context(instance);
++ if (msg_context == NULL)
++ return -ENOMEM;
++
++ /* store bulk message context for when data arrives */
++ msg_context->u.bulk.instance = instance;
++ msg_context->u.bulk.port = port;
++ msg_context->u.bulk.buffer = NULL; /* not valid until bulk xfer */
++ msg_context->u.bulk.buffer_used = 0;
++
++ /* initialise work structure ready to schedule callback */
++ INIT_WORK(&msg_context->u.bulk.work, buffer_work_cb);
++
++ /* prep the buffer from host message */
++ memset(&m, 0xbc, sizeof(m)); /* just to make debug clearer */
++
++ m.h.type = MMAL_MSG_TYPE_BUFFER_FROM_HOST;
++ m.h.magic = MMAL_MAGIC;
++ m.h.context = msg_context;
++ m.h.status = 0;
++
++ /* drvbuf is our private data passed back */
++ m.u.buffer_from_host.drvbuf.magic = MMAL_MAGIC;
++ m.u.buffer_from_host.drvbuf.component_handle = port->component->handle;
++ m.u.buffer_from_host.drvbuf.port_handle = port->handle;
++ m.u.buffer_from_host.drvbuf.client_context = msg_context;
++
++ /* buffer header */
++ m.u.buffer_from_host.buffer_header.cmd = 0;
++ m.u.buffer_from_host.buffer_header.data = buf->buffer;
++ m.u.buffer_from_host.buffer_header.alloc_size = buf->buffer_size;
++ m.u.buffer_from_host.buffer_header.length = 0; /* nothing used yet */
++ m.u.buffer_from_host.buffer_header.offset = 0; /* no offset */
++ m.u.buffer_from_host.buffer_header.flags = 0; /* no flags */
++ m.u.buffer_from_host.buffer_header.pts = MMAL_TIME_UNKNOWN;
++ m.u.buffer_from_host.buffer_header.dts = MMAL_TIME_UNKNOWN;
++
++ /* clear buffer type sepecific data */
++ memset(&m.u.buffer_from_host.buffer_header_type_specific, 0,
++ sizeof(m.u.buffer_from_host.buffer_header_type_specific));
++
++ /* no payload in message */
++ m.u.buffer_from_host.payload_in_message = 0;
++
++ vchi_service_use(instance->handle);
++
++ ret = vchi_msg_queue(instance->handle, &m,
++ sizeof(struct mmal_msg_header) +
++ sizeof(m.u.buffer_from_host),
++ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL);
++
++ if (ret != 0) {
++ release_msg_context(msg_context);
++ /* todo: is this correct error value? */
++ }
++
++ vchi_service_release(instance->handle);
++
++ mutex_unlock(&instance->bulk_mutex);
++
++ return ret;
++}
++
++/* submit a buffer to the mmal sevice
++ *
++ * the buffer_from_host uses size data from the ports next available
++ * mmal_buffer and deals with there being no buffer available by
++ * incrementing the underflow for later
++ */
++static int port_buffer_from_host(struct vchiq_mmal_instance *instance,
++ struct vchiq_mmal_port *port)
++{
++ int ret;
++ struct mmal_buffer *buf;
++ unsigned long flags = 0;
++
++ if (!port->enabled)
++ return -EINVAL;
++
++ /* peek buffer from queue */
++ spin_lock_irqsave(&port->slock, flags);
++ if (list_empty(&port->buffers)) {
++ port->buffer_underflow++;
++ spin_unlock_irqrestore(&port->slock, flags);
++ return -ENOSPC;
++ }
++
++ buf = list_entry(port->buffers.next, struct mmal_buffer, list);
++
++ spin_unlock_irqrestore(&port->slock, flags);
++
++ /* issue buffer to mmal service */
++ ret = buffer_from_host(instance, port, buf);
++ if (ret) {
++ pr_err("adding buffer header failed\n");
++ /* todo: how should this be dealt with */
++ }
++
++ return ret;
++}
++
++/* deals with receipt of buffer to host message */
++static void buffer_to_host_cb(struct vchiq_mmal_instance *instance,
++ struct mmal_msg *msg, u32 msg_len)
++{
++ struct mmal_msg_context *msg_context;
++
++ pr_debug("buffer_to_host_cb: instance:%p msg:%p msg_len:%d\n",
++ instance, msg, msg_len);
++
++ if (msg->u.buffer_from_host.drvbuf.magic == MMAL_MAGIC) {
++ msg_context = msg->u.buffer_from_host.drvbuf.client_context;
++ } else {
++ pr_err("MMAL_MSG_TYPE_BUFFER_TO_HOST with bad magic\n");
++ return;
++ }
++
++ if (msg->h.status != MMAL_MSG_STATUS_SUCCESS) {
++ /* message reception had an error */
++ pr_warn("error %d in reply\n", msg->h.status);
++
++ msg_context->u.bulk.status = msg->h.status;
++
++ } else if (msg->u.buffer_from_host.buffer_header.length == 0) {
++ /* empty buffer */
++ if (msg->u.buffer_from_host.buffer_header.flags &
++ MMAL_BUFFER_HEADER_FLAG_EOS) {
++ msg_context->u.bulk.status =
++ dummy_bulk_receive(instance, msg_context);
++ if (msg_context->u.bulk.status == 0)
++ return; /* successful bulk submission, bulk
++ * completion will trigger callback
++ */
++ } else {
++ /* do callback with empty buffer - not EOS though */
++ msg_context->u.bulk.status = 0;
++ msg_context->u.bulk.buffer_used = 0;
++ }
++ } else if (msg->u.buffer_from_host.payload_in_message == 0) {
++ /* data is not in message, queue a bulk receive */
++ msg_context->u.bulk.status =
++ bulk_receive(instance, msg, msg_context);
++ if (msg_context->u.bulk.status == 0)
++ return; /* successful bulk submission, bulk
++ * completion will trigger callback
++ */
++
++ /* failed to submit buffer, this will end badly */
++ pr_err("error %d on bulk submission\n",
++ msg_context->u.bulk.status);
++
++ } else if (msg->u.buffer_from_host.payload_in_message <=
++ MMAL_VC_SHORT_DATA) {
++ /* data payload within message */
++ msg_context->u.bulk.status = inline_receive(instance, msg,
++ msg_context);
++ } else {
++ pr_err("message with invalid short payload\n");
++
++ /* signal error */
++ msg_context->u.bulk.status = -EINVAL;
++ msg_context->u.bulk.buffer_used =
++ msg->u.buffer_from_host.payload_in_message;
++ }
++
++ /* replace the buffer header */
++ port_buffer_from_host(instance, msg_context->u.bulk.port);
++
++ /* schedule the port callback */
++ schedule_work(&msg_context->u.bulk.work);
++}
++
++static void bulk_receive_cb(struct vchiq_mmal_instance *instance,
++ struct mmal_msg_context *msg_context)
++{
++ /* bulk receive operation complete */
++ mutex_unlock(&msg_context->u.bulk.instance->bulk_mutex);
++
++ /* replace the buffer header */
++ port_buffer_from_host(msg_context->u.bulk.instance,
++ msg_context->u.bulk.port);
++
++ msg_context->u.bulk.status = 0;
++
++ /* schedule the port callback */
++ schedule_work(&msg_context->u.bulk.work);
++}
++
++static void bulk_abort_cb(struct vchiq_mmal_instance *instance,
++ struct mmal_msg_context *msg_context)
++{
++ pr_err("%s: bulk ABORTED msg_context:%p\n", __func__, msg_context);
++
++ /* bulk receive operation complete */
++ mutex_unlock(&msg_context->u.bulk.instance->bulk_mutex);
++
++ /* replace the buffer header */
++ port_buffer_from_host(msg_context->u.bulk.instance,
++ msg_context->u.bulk.port);
++
++ msg_context->u.bulk.status = -EINTR;
++
++ schedule_work(&msg_context->u.bulk.work);
++}
++
++/* incoming event service callback */
++static void service_callback(void *param,
++ const VCHI_CALLBACK_REASON_T reason,
++ void *bulk_ctx)
++{
++ struct vchiq_mmal_instance *instance = param;
++ int status;
++ u32 msg_len;
++ struct mmal_msg *msg;
++ VCHI_HELD_MSG_T msg_handle;
++
++ if (!instance) {
++ pr_err("Message callback passed NULL instance\n");
++ return;
++ }
++
++ switch (reason) {
++ case VCHI_CALLBACK_MSG_AVAILABLE:
++ status = vchi_msg_hold(instance->handle, (void **)&msg,
++ &msg_len, VCHI_FLAGS_NONE, &msg_handle);
++ if (status) {
++ pr_err("Unable to dequeue a message (%d)\n", status);
++ break;
++ }
++
++ DBG_DUMP_MSG(msg, msg_len, "<<< reply message");
++
++ /* handling is different for buffer messages */
++ switch (msg->h.type) {
++
++ case MMAL_MSG_TYPE_BUFFER_FROM_HOST:
++ vchi_held_msg_release(&msg_handle);
++ break;
++
++ case MMAL_MSG_TYPE_EVENT_TO_HOST:
++ event_to_host_cb(instance, msg, msg_len);
++ vchi_held_msg_release(&msg_handle);
++
++ break;
++
++ case MMAL_MSG_TYPE_BUFFER_TO_HOST:
++ buffer_to_host_cb(instance, msg, msg_len);
++ vchi_held_msg_release(&msg_handle);
++ break;
++
++ default:
++ /* messages dependant on header context to complete */
++
++ /* todo: the msg.context really ought to be sanity
++ * checked before we just use it, afaict it comes back
++ * and is used raw from the videocore. Perhaps it
++ * should be verified the address lies in the kernel
++ * address space.
++ */
++ if (msg->h.context == NULL) {
++ pr_err("received message context was null!\n");
++ vchi_held_msg_release(&msg_handle);
++ break;
++ }
++
++ /* fill in context values */
++ msg->h.context->u.sync.msg_handle = msg_handle;
++ msg->h.context->u.sync.msg = msg;
++ msg->h.context->u.sync.msg_len = msg_len;
++
++ /* todo: should this check (completion_done()
++ * == 1) for no one waiting? or do we need a
++ * flag to tell us the completion has been
++ * interrupted so we can free the message and
++ * its context. This probably also solves the
++ * message arriving after interruption todo
++ * below
++ */
++
++ /* complete message so caller knows it happened */
++ complete(&msg->h.context->u.sync.cmplt);
++ break;
++ }
++
++ break;
++
++ case VCHI_CALLBACK_BULK_RECEIVED:
++ bulk_receive_cb(instance, bulk_ctx);
++ break;
++
++ case VCHI_CALLBACK_BULK_RECEIVE_ABORTED:
++ bulk_abort_cb(instance, bulk_ctx);
++ break;
++
++ case VCHI_CALLBACK_SERVICE_CLOSED:
++ /* TODO: consider if this requires action if received when
++ * driver is not explicitly closing the service
++ */
++ break;
++
++ default:
++ pr_err("Received unhandled message reason %d\n", reason);
++ break;
++ }
++}
++
++static int send_synchronous_mmal_msg(struct vchiq_mmal_instance *instance,
++ struct mmal_msg *msg,
++ unsigned int payload_len,
++ struct mmal_msg **msg_out,
++ VCHI_HELD_MSG_T *msg_handle_out)
++{
++ struct mmal_msg_context msg_context;
++ int ret;
++
++ /* payload size must not cause message to exceed max size */
++ if (payload_len >
++ (MMAL_MSG_MAX_SIZE - sizeof(struct mmal_msg_header))) {
++ pr_err("payload length %d exceeds max:%d\n", payload_len,
++ (MMAL_MSG_MAX_SIZE - sizeof(struct mmal_msg_header)));
++ return -EINVAL;
++ }
++
++ init_completion(&msg_context.u.sync.cmplt);
++
++ msg->h.magic = MMAL_MAGIC;
++ msg->h.context = &msg_context;
++ msg->h.status = 0;
++
++ DBG_DUMP_MSG(msg, (sizeof(struct mmal_msg_header) + payload_len),
++ ">>> sync message");
++
++ vchi_service_use(instance->handle);
++
++ ret = vchi_msg_queue(instance->handle,
++ msg,
++ sizeof(struct mmal_msg_header) + payload_len,
++ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL);
++
++ vchi_service_release(instance->handle);
++
++ if (ret) {
++ pr_err("error %d queuing message\n", ret);
++ return ret;
++ }
++
++ ret = wait_for_completion_timeout(&msg_context.u.sync.cmplt, 3*HZ);
++ if (ret <= 0) {
++ pr_err("error %d waiting for sync completion\n", ret);
++ if (ret == 0)
++ ret = -ETIME;
++ /* todo: what happens if the message arrives after aborting */
++ return ret;
++ }
++
++ *msg_out = msg_context.u.sync.msg;
++ *msg_handle_out = msg_context.u.sync.msg_handle;
++
++ return 0;
++}
++
++static void dump_port_info(struct vchiq_mmal_port *port)
++{
++ pr_debug("port handle:0x%x enabled:%d\n", port->handle, port->enabled);
++
++ pr_debug("buffer minimum num:%d size:%d align:%d\n",
++ port->minimum_buffer.num,
++ port->minimum_buffer.size, port->minimum_buffer.alignment);
++
++ pr_debug("buffer recommended num:%d size:%d align:%d\n",
++ port->recommended_buffer.num,
++ port->recommended_buffer.size,
++ port->recommended_buffer.alignment);
++
++ pr_debug("buffer current values num:%d size:%d align:%d\n",
++ port->current_buffer.num,
++ port->current_buffer.size, port->current_buffer.alignment);
++
++ pr_debug("elementry stream: type:%d encoding:0x%x varient:0x%x\n",
++ port->format.type,
++ port->format.encoding, port->format.encoding_variant);
++
++ pr_debug(" bitrate:%d flags:0x%x\n",
++ port->format.bitrate, port->format.flags);
++
++ if (port->format.type == MMAL_ES_TYPE_VIDEO) {
++ pr_debug
++ ("es video format: width:%d height:%d colourspace:0x%x\n",
++ port->es.video.width, port->es.video.height,
++ port->es.video.color_space);
++
++ pr_debug(" : crop xywh %d,%d,%d,%d\n",
++ port->es.video.crop.x,
++ port->es.video.crop.y,
++ port->es.video.crop.width, port->es.video.crop.height);
++ pr_debug(" : framerate %d/%d aspect %d/%d\n",
++ port->es.video.frame_rate.num,
++ port->es.video.frame_rate.den,
++ port->es.video.par.num, port->es.video.par.den);
++ }
++}
++
++static void port_to_mmal_msg(struct vchiq_mmal_port *port, struct mmal_port *p)
++{
++
++ /* todo do readonly fields need setting at all? */
++ p->type = port->type;
++ p->index = port->index;
++ p->index_all = 0;
++ p->is_enabled = port->enabled;
++ p->buffer_num_min = port->minimum_buffer.num;
++ p->buffer_size_min = port->minimum_buffer.size;
++ p->buffer_alignment_min = port->minimum_buffer.alignment;
++ p->buffer_num_recommended = port->recommended_buffer.num;
++ p->buffer_size_recommended = port->recommended_buffer.size;
++
++ /* only three writable fields in a port */
++ p->buffer_num = port->current_buffer.num;
++ p->buffer_size = port->current_buffer.size;
++ p->userdata = port;
++}
++
++static int port_info_set(struct vchiq_mmal_instance *instance,
++ struct vchiq_mmal_port *port)
++{
++ int ret;
++ struct mmal_msg m;
++ struct mmal_msg *rmsg;
++ VCHI_HELD_MSG_T rmsg_handle;
++
++ pr_debug("setting port info port %p\n", port);
++ if (!port)
++ return -1;
++ dump_port_info(port);
++
++ m.h.type = MMAL_MSG_TYPE_PORT_INFO_SET;
++
++ m.u.port_info_set.component_handle = port->component->handle;
++ m.u.port_info_set.port_type = port->type;
++ m.u.port_info_set.port_index = port->index;
++
++ port_to_mmal_msg(port, &m.u.port_info_set.port);
++
++ /* elementry stream format setup */
++ m.u.port_info_set.format.type = port->format.type;
++ m.u.port_info_set.format.encoding = port->format.encoding;
++ m.u.port_info_set.format.encoding_variant =
++ port->format.encoding_variant;
++ m.u.port_info_set.format.bitrate = port->format.bitrate;
++ m.u.port_info_set.format.flags = port->format.flags;
++
++ memcpy(&m.u.port_info_set.es, &port->es,
++ sizeof(union mmal_es_specific_format));
++
++ m.u.port_info_set.format.extradata_size = port->format.extradata_size;
++ memcpy(rmsg->u.port_info_set.extradata, port->format.extradata,
++ port->format.extradata_size);
++
++ ret = send_synchronous_mmal_msg(instance, &m,
++ sizeof(m.u.port_info_set),
++ &rmsg, &rmsg_handle);
++ if (ret)
++ return ret;
++
++ if (rmsg->h.type != MMAL_MSG_TYPE_PORT_INFO_SET) {
++ /* got an unexpected message type in reply */
++ ret = -EINVAL;
++ goto release_msg;
++ }
++
++ /* return operation status */
++ ret = -rmsg->u.port_info_get_reply.status;
++
++ pr_debug("%s:result:%d component:0x%x port:%d\n", __func__, ret,
++ port->component->handle, port->handle);
++
++release_msg:
++ vchi_held_msg_release(&rmsg_handle);
++
++ return ret;
++
++}
++
++/* use port info get message to retrive port information */
++static int port_info_get(struct vchiq_mmal_instance *instance,
++ struct vchiq_mmal_port *port)
++{
++ int ret;
++ struct mmal_msg m;
++ struct mmal_msg *rmsg;
++ VCHI_HELD_MSG_T rmsg_handle;
++
++ /* port info time */
++ m.h.type = MMAL_MSG_TYPE_PORT_INFO_GET;
++ m.u.port_info_get.component_handle = port->component->handle;
++ m.u.port_info_get.port_type = port->type;
++ m.u.port_info_get.index = port->index;
++
++ ret = send_synchronous_mmal_msg(instance, &m,
++ sizeof(m.u.port_info_get),
++ &rmsg, &rmsg_handle);
++ if (ret)
++ return ret;
++
++ if (rmsg->h.type != MMAL_MSG_TYPE_PORT_INFO_GET) {
++ /* got an unexpected message type in reply */
++ ret = -EINVAL;
++ goto release_msg;
++ }
++
++ /* return operation status */
++ ret = -rmsg->u.port_info_get_reply.status;
++ if (ret != MMAL_MSG_STATUS_SUCCESS)
++ goto release_msg;
++
++ if (rmsg->u.port_info_get_reply.port.is_enabled == 0)
++ port->enabled = false;
++ else
++ port->enabled = true;
++
++ /* copy the values out of the message */
++ port->handle = rmsg->u.port_info_get_reply.port_handle;
++
++ /* port type and index cached to use on port info set becuase
++ * it does not use a port handle
++ */
++ port->type = rmsg->u.port_info_get_reply.port_type;
++ port->index = rmsg->u.port_info_get_reply.port_index;
++
++ port->minimum_buffer.num =
++ rmsg->u.port_info_get_reply.port.buffer_num_min;
++ port->minimum_buffer.size =
++ rmsg->u.port_info_get_reply.port.buffer_size_min;
++ port->minimum_buffer.alignment =
++ rmsg->u.port_info_get_reply.port.buffer_alignment_min;
++
++ port->recommended_buffer.alignment =
++ rmsg->u.port_info_get_reply.port.buffer_alignment_min;
++ port->recommended_buffer.num =
++ rmsg->u.port_info_get_reply.port.buffer_num_recommended;
++
++ port->current_buffer.num = rmsg->u.port_info_get_reply.port.buffer_num;
++ port->current_buffer.size =
++ rmsg->u.port_info_get_reply.port.buffer_size;
++
++ /* stream format */
++ port->format.type = rmsg->u.port_info_get_reply.format.type;
++ port->format.encoding = rmsg->u.port_info_get_reply.format.encoding;
++ port->format.encoding_variant =
++ rmsg->u.port_info_get_reply.format.encoding_variant;
++ port->format.bitrate = rmsg->u.port_info_get_reply.format.bitrate;
++ port->format.flags = rmsg->u.port_info_get_reply.format.flags;
++
++ /* elementry stream format */
++ memcpy(&port->es,
++ &rmsg->u.port_info_get_reply.es,
++ sizeof(union mmal_es_specific_format));
++ port->format.es = &port->es;
++
++ port->format.extradata_size =
++ rmsg->u.port_info_get_reply.format.extradata_size;
++ memcpy(port->format.extradata,
++ rmsg->u.port_info_get_reply.extradata,
++ port->format.extradata_size);
++
++ pr_debug("received port info\n");
++ dump_port_info(port);
++
++release_msg:
++
++ pr_debug("%s:result:%d component:0x%x port:%d\n",
++ __func__, ret, port->component->handle, port->handle);
++
++ vchi_held_msg_release(&rmsg_handle);
++
++ return ret;
++}
++
++/* create comonent on vc */
++static int create_component(struct vchiq_mmal_instance *instance,
++ struct vchiq_mmal_component *component,
++ const char *name)
++{
++ int ret;
++ struct mmal_msg m;
++ struct mmal_msg *rmsg;
++ VCHI_HELD_MSG_T rmsg_handle;
++
++ /* build component create message */
++ m.h.type = MMAL_MSG_TYPE_COMPONENT_CREATE;
++ m.u.component_create.client_component = component;
++ strncpy(m.u.component_create.name, name,
++ sizeof(m.u.component_create.name));
++
++ ret = send_synchronous_mmal_msg(instance, &m,
++ sizeof(m.u.component_create),
++ &rmsg, &rmsg_handle);
++ if (ret)
++ return ret;
++
++ if (rmsg->h.type != m.h.type) {
++ /* got an unexpected message type in reply */
++ ret = -EINVAL;
++ goto release_msg;
++ }
++
++ ret = -rmsg->u.component_create_reply.status;
++ if (ret != MMAL_MSG_STATUS_SUCCESS)
++ goto release_msg;
++
++ /* a valid component response received */
++ component->handle = rmsg->u.component_create_reply.component_handle;
++ component->inputs = rmsg->u.component_create_reply.input_num;
++ component->outputs = rmsg->u.component_create_reply.output_num;
++ component->clocks = rmsg->u.component_create_reply.clock_num;
++
++ pr_debug("Component handle:0x%x in:%d out:%d clock:%d\n",
++ component->handle,
++ component->inputs, component->outputs, component->clocks);
++
++release_msg:
++ vchi_held_msg_release(&rmsg_handle);
++
++ return ret;
++}
++
++/* destroys a component on vc */
++static int destroy_component(struct vchiq_mmal_instance *instance,
++ struct vchiq_mmal_component *component)
++{
++ int ret;
++ struct mmal_msg m;
++ struct mmal_msg *rmsg;
++ VCHI_HELD_MSG_T rmsg_handle;
++
++ m.h.type = MMAL_MSG_TYPE_COMPONENT_DESTROY;
++ m.u.component_destroy.component_handle = component->handle;
++
++ ret = send_synchronous_mmal_msg(instance, &m,
++ sizeof(m.u.component_destroy),
++ &rmsg, &rmsg_handle);
++ if (ret)
++ return ret;
++
++ if (rmsg->h.type != m.h.type) {
++ /* got an unexpected message type in reply */
++ ret = -EINVAL;
++ goto release_msg;
++ }
++
++ ret = -rmsg->u.component_destroy_reply.status;
++
++release_msg:
++
++ vchi_held_msg_release(&rmsg_handle);
++
++ return ret;
++}
++
++/* enable a component on vc */
++static int enable_component(struct vchiq_mmal_instance *instance,
++ struct vchiq_mmal_component *component)
++{
++ int ret;
++ struct mmal_msg m;
++ struct mmal_msg *rmsg;
++ VCHI_HELD_MSG_T rmsg_handle;
++
++ m.h.type = MMAL_MSG_TYPE_COMPONENT_ENABLE;
++ m.u.component_enable.component_handle = component->handle;
++
++ ret = send_synchronous_mmal_msg(instance, &m,
++ sizeof(m.u.component_enable),
++ &rmsg, &rmsg_handle);
++ if (ret)
++ return ret;
++
++ if (rmsg->h.type != m.h.type) {
++ /* got an unexpected message type in reply */
++ ret = -EINVAL;
++ goto release_msg;
++ }
++
++ ret = -rmsg->u.component_enable_reply.status;
++
++release_msg:
++ vchi_held_msg_release(&rmsg_handle);
++
++ return ret;
++}
++
++/* disable a component on vc */
++static int disable_component(struct vchiq_mmal_instance *instance,
++ struct vchiq_mmal_component *component)
++{
++ int ret;
++ struct mmal_msg m;
++ struct mmal_msg *rmsg;
++ VCHI_HELD_MSG_T rmsg_handle;
++
++ m.h.type = MMAL_MSG_TYPE_COMPONENT_DISABLE;
++ m.u.component_disable.component_handle = component->handle;
++
++ ret = send_synchronous_mmal_msg(instance, &m,
++ sizeof(m.u.component_disable),
++ &rmsg, &rmsg_handle);
++ if (ret)
++ return ret;
++
++ if (rmsg->h.type != m.h.type) {
++ /* got an unexpected message type in reply */
++ ret = -EINVAL;
++ goto release_msg;
++ }
++
++ ret = -rmsg->u.component_disable_reply.status;
++
++release_msg:
++
++ vchi_held_msg_release(&rmsg_handle);
++
++ return ret;
++}
++
++/* get version of mmal implementation */
++static int get_version(struct vchiq_mmal_instance *instance,
++ u32 *major_out, u32 *minor_out)
++{
++ int ret;
++ struct mmal_msg m;
++ struct mmal_msg *rmsg;
++ VCHI_HELD_MSG_T rmsg_handle;
++
++ m.h.type = MMAL_MSG_TYPE_GET_VERSION;
++
++ ret = send_synchronous_mmal_msg(instance, &m,
++ sizeof(m.u.version),
++ &rmsg, &rmsg_handle);
++ if (ret)
++ return ret;
++
++ if (rmsg->h.type != m.h.type) {
++ /* got an unexpected message type in reply */
++ ret = -EINVAL;
++ goto release_msg;
++ }
++
++ *major_out = rmsg->u.version.major;
++ *minor_out = rmsg->u.version.minor;
++
++release_msg:
++ vchi_held_msg_release(&rmsg_handle);
++
++ return ret;
++}
++
++/* do a port action with a port as a parameter */
++static int port_action_port(struct vchiq_mmal_instance *instance,
++ struct vchiq_mmal_port *port,
++ enum mmal_msg_port_action_type action_type)
++{
++ int ret;
++ struct mmal_msg m;
++ struct mmal_msg *rmsg;
++ VCHI_HELD_MSG_T rmsg_handle;
++
++ m.h.type = MMAL_MSG_TYPE_PORT_ACTION;
++ m.u.port_action_port.component_handle = port->component->handle;
++ m.u.port_action_port.port_handle = port->handle;
++ m.u.port_action_port.action = action_type;
++
++ port_to_mmal_msg(port, &m.u.port_action_port.port);
++
++ ret = send_synchronous_mmal_msg(instance, &m,
++ sizeof(m.u.port_action_port),
++ &rmsg, &rmsg_handle);
++ if (ret)
++ return ret;
++
++ if (rmsg->h.type != MMAL_MSG_TYPE_PORT_ACTION) {
++ /* got an unexpected message type in reply */
++ ret = -EINVAL;
++ goto release_msg;
++ }
++
++ ret = -rmsg->u.port_action_reply.status;
++
++ pr_debug("%s:result:%d component:0x%x port:%d action:%s(%d)\n",
++ __func__,
++ ret, port->component->handle, port->handle,
++ port_action_type_names[action_type], action_type);
++
++release_msg:
++ vchi_held_msg_release(&rmsg_handle);
++
++ return ret;
++}
++
++/* do a port action with handles as parameters */
++static int port_action_handle(struct vchiq_mmal_instance *instance,
++ struct vchiq_mmal_port *port,
++ enum mmal_msg_port_action_type action_type,
++ u32 connect_component_handle,
++ u32 connect_port_handle)
++{
++ int ret;
++ struct mmal_msg m;
++ struct mmal_msg *rmsg;
++ VCHI_HELD_MSG_T rmsg_handle;
++
++ m.h.type = MMAL_MSG_TYPE_PORT_ACTION;
++
++ m.u.port_action_handle.component_handle = port->component->handle;
++ m.u.port_action_handle.port_handle = port->handle;
++ m.u.port_action_handle.action = action_type;
++
++ m.u.port_action_handle.connect_component_handle =
++ connect_component_handle;
++ m.u.port_action_handle.connect_port_handle = connect_port_handle;
++
++ ret = send_synchronous_mmal_msg(instance, &m,
++ sizeof(m.u.port_action_handle),
++ &rmsg, &rmsg_handle);
++ if (ret)
++ return ret;
++
++ if (rmsg->h.type != MMAL_MSG_TYPE_PORT_ACTION) {
++ /* got an unexpected message type in reply */
++ ret = -EINVAL;
++ goto release_msg;
++ }
++
++ ret = -rmsg->u.port_action_reply.status;
++
++ pr_debug("%s:result:%d component:0x%x port:%d action:%s(%d)" \
++ " connect component:0x%x connect port:%d\n",
++ __func__,
++ ret, port->component->handle, port->handle,
++ port_action_type_names[action_type],
++ action_type, connect_component_handle, connect_port_handle);
++
++release_msg:
++ vchi_held_msg_release(&rmsg_handle);
++
++ return ret;
++}
++
++static int port_parameter_set(struct vchiq_mmal_instance *instance,
++ struct vchiq_mmal_port *port,
++ u32 parameter_id, void *value, u32 value_size)
++{
++ int ret;
++ struct mmal_msg m;
++ struct mmal_msg *rmsg;
++ VCHI_HELD_MSG_T rmsg_handle;
++
++ m.h.type = MMAL_MSG_TYPE_PORT_PARAMETER_SET;
++
++ m.u.port_parameter_set.component_handle = port->component->handle;
++ m.u.port_parameter_set.port_handle = port->handle;
++ m.u.port_parameter_set.id = parameter_id;
++ m.u.port_parameter_set.size = (2 * sizeof(u32)) + value_size;
++ memcpy(&m.u.port_parameter_set.value, value, value_size);
++
++ ret = send_synchronous_mmal_msg(instance, &m,
++ (4 * sizeof(u32)) + value_size,
++ &rmsg, &rmsg_handle);
++ if (ret)
++ return ret;
++
++ if (rmsg->h.type != MMAL_MSG_TYPE_PORT_PARAMETER_SET) {
++ /* got an unexpected message type in reply */
++ ret = -EINVAL;
++ goto release_msg;
++ }
++
++ ret = -rmsg->u.port_parameter_set_reply.status;
++
++ pr_debug("%s:result:%d component:0x%x port:%d parameter:%d\n",
++ __func__,
++ ret, port->component->handle, port->handle, parameter_id);
++
++release_msg:
++ vchi_held_msg_release(&rmsg_handle);
++
++ return ret;
++}
++
++static int port_parameter_get(struct vchiq_mmal_instance *instance,
++ struct vchiq_mmal_port *port,
++ u32 parameter_id, void *value, u32 *value_size)
++{
++ int ret;
++ struct mmal_msg m;
++ struct mmal_msg *rmsg;
++ VCHI_HELD_MSG_T rmsg_handle;
++
++ m.h.type = MMAL_MSG_TYPE_PORT_PARAMETER_GET;
++
++ m.u.port_parameter_get.component_handle = port->component->handle;
++ m.u.port_parameter_get.port_handle = port->handle;
++ m.u.port_parameter_get.id = parameter_id;
++ m.u.port_parameter_get.size = (2 * sizeof(u32)) + *value_size;
++
++ ret = send_synchronous_mmal_msg(instance, &m,
++ sizeof(struct
++ mmal_msg_port_parameter_get),
++ &rmsg, &rmsg_handle);
++ if (ret)
++ return ret;
++
++ if (rmsg->h.type != MMAL_MSG_TYPE_PORT_PARAMETER_GET) {
++ /* got an unexpected message type in reply */
++ pr_err("Incorrect reply type %d\n", rmsg->h.type);
++ ret = -EINVAL;
++ goto release_msg;
++ }
++
++ ret = -rmsg->u.port_parameter_get_reply.status;
++ if (ret) {
++ /* Copy only as much as we have space for
++ * but report true size of parameter
++ */
++ memcpy(value, &rmsg->u.port_parameter_get_reply.value,
++ *value_size);
++ *value_size = rmsg->u.port_parameter_get_reply.size;
++ } else
++ memcpy(value, &rmsg->u.port_parameter_get_reply.value,
++ rmsg->u.port_parameter_get_reply.size);
++
++ pr_debug("%s:result:%d component:0x%x port:%d parameter:%d\n", __func__,
++ ret, port->component->handle, port->handle, parameter_id);
++
++release_msg:
++ vchi_held_msg_release(&rmsg_handle);
++
++ return ret;
++}
++
++/* disables a port and drains buffers from it */
++static int port_disable(struct vchiq_mmal_instance *instance,
++ struct vchiq_mmal_port *port)
++{
++ int ret;
++ struct list_head *q, *buf_head;
++ unsigned long flags = 0;
++
++ if (!port->enabled)
++ return 0;
++
++ port->enabled = false;
++
++ ret = port_action_port(instance, port,
++ MMAL_MSG_PORT_ACTION_TYPE_DISABLE);
++ if (ret == 0) {
++
++ /* drain all queued buffers on port */
++ spin_lock_irqsave(&port->slock, flags);
++
++ list_for_each_safe(buf_head, q, &port->buffers) {
++ struct mmal_buffer *mmalbuf;
++ mmalbuf = list_entry(buf_head, struct mmal_buffer,
++ list);
++ list_del(buf_head);
++ if (port->buffer_cb)
++ port->buffer_cb(instance,
++ port, 0, mmalbuf, 0, 0,
++ MMAL_TIME_UNKNOWN,
++ MMAL_TIME_UNKNOWN);
++ }
++
++ spin_unlock_irqrestore(&port->slock, flags);
++
++ ret = port_info_get(instance, port);
++ }
++
++ return ret;
++}
++
++/* enable a port */
++static int port_enable(struct vchiq_mmal_instance *instance,
++ struct vchiq_mmal_port *port)
++{
++ unsigned int hdr_count;
++ struct list_head *buf_head;
++ int ret;
++
++ if (port->enabled)
++ return 0;
++
++ /* ensure there are enough buffers queued to cover the buffer headers */
++ if (port->buffer_cb != NULL) {
++ hdr_count = 0;
++ list_for_each(buf_head, &port->buffers) {
++ hdr_count++;
++ }
++ if (hdr_count < port->current_buffer.num)
++ return -ENOSPC;
++ }
++
++ ret = port_action_port(instance, port,
++ MMAL_MSG_PORT_ACTION_TYPE_ENABLE);
++ if (ret)
++ goto done;
++
++ port->enabled = true;
++
++ if (port->buffer_cb) {
++ /* send buffer headers to videocore */
++ hdr_count = 1;
++ list_for_each(buf_head, &port->buffers) {
++ struct mmal_buffer *mmalbuf;
++ mmalbuf = list_entry(buf_head, struct mmal_buffer,
++ list);
++ ret = buffer_from_host(instance, port, mmalbuf);
++ if (ret)
++ goto done;
++
++ hdr_count++;
++ if (hdr_count > port->current_buffer.num)
++ break;
++ }
++ }
++
++ ret = port_info_get(instance, port);
++
++done:
++ return ret;
++}
++
++/* ------------------------------------------------------------------
++ * Exported API
++ *------------------------------------------------------------------*/
++
++int vchiq_mmal_port_set_format(struct vchiq_mmal_instance *instance,
++ struct vchiq_mmal_port *port)
++{
++ int ret;
++
++ if (mutex_lock_interruptible(&instance->vchiq_mutex))
++ return -EINTR;
++
++ ret = port_info_set(instance, port);
++ if (ret)
++ goto release_unlock;
++
++ /* read what has actually been set */
++ ret = port_info_get(instance, port);
++
++release_unlock:
++ mutex_unlock(&instance->vchiq_mutex);
++
++ return ret;
++
++}
++
++int vchiq_mmal_port_parameter_set(struct vchiq_mmal_instance *instance,
++ struct vchiq_mmal_port *port,
++ u32 parameter, void *value, u32 value_size)
++{
++ int ret;
++
++ if (mutex_lock_interruptible(&instance->vchiq_mutex))
++ return -EINTR;
++
++ ret = port_parameter_set(instance, port, parameter, value, value_size);
++
++ mutex_unlock(&instance->vchiq_mutex);
++
++ return ret;
++}
++
++int vchiq_mmal_port_parameter_get(struct vchiq_mmal_instance *instance,
++ struct vchiq_mmal_port *port,
++ u32 parameter, void *value, u32 *value_size)
++{
++ int ret;
++
++ if (mutex_lock_interruptible(&instance->vchiq_mutex))
++ return -EINTR;
++
++ ret = port_parameter_get(instance, port, parameter, value, value_size);
++
++ mutex_unlock(&instance->vchiq_mutex);
++
++ return ret;
++}
++
++/* enable a port
++ *
++ * enables a port and queues buffers for satisfying callbacks if we
++ * provide a callback handler
++ */
++int vchiq_mmal_port_enable(struct vchiq_mmal_instance *instance,
++ struct vchiq_mmal_port *port,
++ vchiq_mmal_buffer_cb buffer_cb)
++{
++ int ret;
++
++ if (mutex_lock_interruptible(&instance->vchiq_mutex))
++ return -EINTR;
++
++ /* already enabled - noop */
++ if (port->enabled) {
++ ret = 0;
++ goto unlock;
++ }
++
++ port->buffer_cb = buffer_cb;
++
++ ret = port_enable(instance, port);
++
++unlock:
++ mutex_unlock(&instance->vchiq_mutex);
++
++ return ret;
++}
++
++int vchiq_mmal_port_disable(struct vchiq_mmal_instance *instance,
++ struct vchiq_mmal_port *port)
++{
++ int ret;
++
++ if (mutex_lock_interruptible(&instance->vchiq_mutex))
++ return -EINTR;
++
++ if (!port->enabled) {
++ mutex_unlock(&instance->vchiq_mutex);
++ return 0;
++ }
++
++ ret = port_disable(instance, port);
++
++ mutex_unlock(&instance->vchiq_mutex);
++
++ return ret;
++}
++
++/* ports will be connected in a tunneled manner so data buffers
++ * are not handled by client.
++ */
++int vchiq_mmal_port_connect_tunnel(struct vchiq_mmal_instance *instance,
++ struct vchiq_mmal_port *src,
++ struct vchiq_mmal_port *dst)
++{
++ int ret;
++
++ if (mutex_lock_interruptible(&instance->vchiq_mutex))
++ return -EINTR;
++
++ /* disconnect ports if connected */
++ if (src->connected != NULL) {
++ ret = port_disable(instance, src);
++ if (ret) {
++ pr_err("failed disabling src port(%d)\n", ret);
++ goto release_unlock;
++ }
++
++ /* do not need to disable the destination port as they
++ * are connected and it is done automatically
++ */
++
++ ret = port_action_handle(instance, src,
++ MMAL_MSG_PORT_ACTION_TYPE_DISCONNECT,
++ src->connected->component->handle,
++ src->connected->handle);
++ if (ret < 0) {
++ pr_err("failed disconnecting src port\n");
++ goto release_unlock;
++ }
++ src->connected->enabled = false;
++ src->connected = NULL;
++ }
++
++ if (dst == NULL) {
++ /* do not make new connection */
++ ret = 0;
++ pr_debug("not making new connection\n");
++ goto release_unlock;
++ }
++
++ /* copy src port format to dst */
++ dst->format.encoding = src->format.encoding;
++ dst->es.video.width = src->es.video.width;
++ dst->es.video.height = src->es.video.height;
++ dst->es.video.crop.x = src->es.video.crop.x;
++ dst->es.video.crop.y = src->es.video.crop.y;
++ dst->es.video.crop.width = src->es.video.crop.width;
++ dst->es.video.crop.height = src->es.video.crop.height;
++ dst->es.video.frame_rate.num = src->es.video.frame_rate.num;
++ dst->es.video.frame_rate.den = src->es.video.frame_rate.den;
++
++ /* set new format */
++ ret = port_info_set(instance, dst);
++ if (ret) {
++ pr_debug("setting port info failed\n");
++ goto release_unlock;
++ }
++
++ /* read what has actually been set */
++ ret = port_info_get(instance, dst);
++ if (ret) {
++ pr_debug("read back port info failed\n");
++ goto release_unlock;
++ }
++
++ /* connect two ports together */
++ ret = port_action_handle(instance, src,
++ MMAL_MSG_PORT_ACTION_TYPE_CONNECT,
++ dst->component->handle, dst->handle);
++ if (ret < 0) {
++ pr_debug("connecting port %d:%d to %d:%d failed\n",
++ src->component->handle, src->handle,
++ dst->component->handle, dst->handle);
++ goto release_unlock;
++ }
++ src->connected = dst;
++
++release_unlock:
++
++ mutex_unlock(&instance->vchiq_mutex);
++
++ return ret;
++}
++
++int vchiq_mmal_submit_buffer(struct vchiq_mmal_instance *instance,
++ struct vchiq_mmal_port *port,
++ struct mmal_buffer *buffer)
++{
++ unsigned long flags = 0;
++
++ spin_lock_irqsave(&port->slock, flags);
++ list_add_tail(&buffer->list, &port->buffers);
++ spin_unlock_irqrestore(&port->slock, flags);
++
++ /* the port previously underflowed because it was missing a
++ * mmal_buffer which has just been added, submit that buffer
++ * to the mmal service.
++ */
++ if (port->buffer_underflow) {
++ port_buffer_from_host(instance, port);
++ port->buffer_underflow--;
++ }
++
++ return 0;
++}
++
++/* Initialise a mmal component and its ports
++ *
++ */
++int vchiq_mmal_component_init(struct vchiq_mmal_instance *instance,
++ const char *name,
++ struct vchiq_mmal_component **component_out)
++{
++ int ret;
++ int idx; /* port index */
++ struct vchiq_mmal_component *component;
++
++ if (mutex_lock_interruptible(&instance->vchiq_mutex))
++ return -EINTR;
++
++ if (instance->component_idx == VCHIQ_MMAL_MAX_COMPONENTS) {
++ ret = -EINVAL; /* todo is this correct error? */
++ goto unlock;
++ }
++
++ component = &instance->component[instance->component_idx];
++
++ ret = create_component(instance, component, name);
++ if (ret < 0)
++ goto unlock;
++
++ /* ports info needs gathering */
++ component->control.type = MMAL_PORT_TYPE_CONTROL;
++ component->control.index = 0;
++ component->control.component = component;
++ spin_lock_init(&component->control.slock);
++ INIT_LIST_HEAD(&component->control.buffers);
++ ret = port_info_get(instance, &component->control);
++ if (ret < 0)
++ goto release_component;
++
++ for (idx = 0; idx < component->inputs; idx++) {
++ component->input[idx].type = MMAL_PORT_TYPE_INPUT;
++ component->input[idx].index = idx;
++ component->input[idx].component = component;
++ spin_lock_init(&component->input[idx].slock);
++ INIT_LIST_HEAD(&component->input[idx].buffers);
++ ret = port_info_get(instance, &component->input[idx]);
++ if (ret < 0)
++ goto release_component;
++ }
++
++ for (idx = 0; idx < component->outputs; idx++) {
++ component->output[idx].type = MMAL_PORT_TYPE_OUTPUT;
++ component->output[idx].index = idx;
++ component->output[idx].component = component;
++ spin_lock_init(&component->output[idx].slock);
++ INIT_LIST_HEAD(&component->output[idx].buffers);
++ ret = port_info_get(instance, &component->output[idx]);
++ if (ret < 0)
++ goto release_component;
++ }
++
++ for (idx = 0; idx < component->clocks; idx++) {
++ component->clock[idx].type = MMAL_PORT_TYPE_CLOCK;
++ component->clock[idx].index = idx;
++ component->clock[idx].component = component;
++ spin_lock_init(&component->clock[idx].slock);
++ INIT_LIST_HEAD(&component->clock[idx].buffers);
++ ret = port_info_get(instance, &component->clock[idx]);
++ if (ret < 0)
++ goto release_component;
++ }
++
++ instance->component_idx++;
++
++ *component_out = component;
++
++ mutex_unlock(&instance->vchiq_mutex);
++
++ return 0;
++
++release_component:
++ destroy_component(instance, component);
++unlock:
++ mutex_unlock(&instance->vchiq_mutex);
++
++ return ret;
++}
++
++/*
++ * cause a mmal component to be destroyed
++ */
++int vchiq_mmal_component_finalise(struct vchiq_mmal_instance *instance,
++ struct vchiq_mmal_component *component)
++{
++ int ret;
++
++ if (mutex_lock_interruptible(&instance->vchiq_mutex))
++ return -EINTR;
++
++ if (component->enabled)
++ ret = disable_component(instance, component);
++
++ ret = destroy_component(instance, component);
++
++ mutex_unlock(&instance->vchiq_mutex);
++
++ return ret;
++}
++
++/*
++ * cause a mmal component to be enabled
++ */
++int vchiq_mmal_component_enable(struct vchiq_mmal_instance *instance,
++ struct vchiq_mmal_component *component)
++{
++ int ret;
++
++ if (mutex_lock_interruptible(&instance->vchiq_mutex))
++ return -EINTR;
++
++ if (component->enabled) {
++ mutex_unlock(&instance->vchiq_mutex);
++ return 0;
++ }
++
++ ret = enable_component(instance, component);
++ if (ret == 0)
++ component->enabled = true;
++
++ mutex_unlock(&instance->vchiq_mutex);
++
++ return ret;
++}
++
++/*
++ * cause a mmal component to be enabled
++ */
++int vchiq_mmal_component_disable(struct vchiq_mmal_instance *instance,
++ struct vchiq_mmal_component *component)
++{
++ int ret;
++
++ if (mutex_lock_interruptible(&instance->vchiq_mutex))
++ return -EINTR;
++
++ if (!component->enabled) {
++ mutex_unlock(&instance->vchiq_mutex);
++ return 0;
++ }
++
++ ret = disable_component(instance, component);
++ if (ret == 0)
++ component->enabled = false;
++
++ mutex_unlock(&instance->vchiq_mutex);
++
++ return ret;
++}
++
++int vchiq_mmal_version(struct vchiq_mmal_instance *instance,
++ u32 *major_out, u32 *minor_out)
++{
++ int ret;
++
++ if (mutex_lock_interruptible(&instance->vchiq_mutex))
++ return -EINTR;
++
++ ret = get_version(instance, major_out, minor_out);
++
++ mutex_unlock(&instance->vchiq_mutex);
++
++ return ret;
++}
++
++int vchiq_mmal_finalise(struct vchiq_mmal_instance *instance)
++{
++ int status = 0;
++
++ if (instance == NULL)
++ return -EINVAL;
++
++ if (mutex_lock_interruptible(&instance->vchiq_mutex))
++ return -EINTR;
++
++ vchi_service_use(instance->handle);
++
++ status = vchi_service_close(instance->handle);
++ if (status != 0)
++ pr_err("mmal-vchiq: VCHIQ close failed");
++
++ mutex_unlock(&instance->vchiq_mutex);
++
++ vfree(instance->bulk_scratch);
++
++ kfree(instance);
++
++ return status;
++}
++
++int vchiq_mmal_init(struct vchiq_mmal_instance **out_instance)
++{
++ int status;
++ struct vchiq_mmal_instance *instance;
++ static VCHI_CONNECTION_T *vchi_connection;
++ static VCHI_INSTANCE_T vchi_instance;
++ SERVICE_CREATION_T params = {
++ VCHI_VERSION_EX(VC_MMAL_VER, VC_MMAL_MIN_VER),
++ VC_MMAL_SERVER_NAME,
++ vchi_connection,
++ 0, /* rx fifo size (unused) */
++ 0, /* tx fifo size (unused) */
++ service_callback,
++ NULL, /* service callback parameter */
++ 1, /* unaligned bulk receives */
++ 1, /* unaligned bulk transmits */
++ 0 /* want crc check on bulk transfers */
++ };
++
++ /* compile time checks to ensure structure size as they are
++ * directly (de)serialised from memory.
++ */
++
++ /* ensure the header structure has packed to the correct size */
++ BUILD_BUG_ON(sizeof(struct mmal_msg_header) != 24);
++
++ /* ensure message structure does not exceed maximum length */
++ BUILD_BUG_ON(sizeof(struct mmal_msg) > MMAL_MSG_MAX_SIZE);
++
++ /* mmal port struct is correct size */
++ BUILD_BUG_ON(sizeof(struct mmal_port) != 64);
++
++ /* create a vchi instance */
++ status = vchi_initialise(&vchi_instance);
++ if (status) {
++ pr_err("Failed to initialise VCHI instance (status=%d)\n",
++ status);
++ return -EIO;
++ }
++
++ status = vchi_connect(NULL, 0, vchi_instance);
++ if (status) {
++ pr_err("Failed to connect VCHI instance (status=%d)\n", status);
++ return -EIO;
++ }
++
++ instance = kmalloc(sizeof(*instance), GFP_KERNEL);
++ memset(instance, 0, sizeof(*instance));
++
++ mutex_init(&instance->vchiq_mutex);
++ mutex_init(&instance->bulk_mutex);
++
++ instance->bulk_scratch = vmalloc(PAGE_SIZE);
++
++ params.callback_param = instance;
++
++ status = vchi_service_open(vchi_instance, &params, &instance->handle);
++ if (status) {
++ pr_err("Failed to open VCHI service connection (status=%d)\n",
++ status);
++ goto err_close_services;
++ }
++
++ vchi_service_release(instance->handle);
++
++ *out_instance = instance;
++
++ return 0;
++
++err_close_services:
++
++ vchi_service_close(instance->handle);
++ vfree(instance->bulk_scratch);
++ kfree(instance);
++ return -ENODEV;
++}
+diff -Nur linux-4.1.3/drivers/media/platform/bcm2835/mmal-vchiq.h linux-xbian-rpi/drivers/media/platform/bcm2835/mmal-vchiq.h
+--- linux-4.1.3/drivers/media/platform/bcm2835/mmal-vchiq.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/media/platform/bcm2835/mmal-vchiq.h 2015-07-28 01:20:58.281739526 +0200
+@@ -0,0 +1,178 @@
++/*
++ * Broadcom BM2835 V4L2 driver
++ *
++ * Copyright © 2013 Raspberry Pi (Trading) Ltd.
++ *
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file COPYING in the main directory of this archive
++ * for more details.
++ *
++ * Authors: Vincent Sanders <vincent.sanders@collabora.co.uk>
++ * Dave Stevenson <dsteve@broadcom.com>
++ * Simon Mellor <simellor@broadcom.com>
++ * Luke Diamand <luked@broadcom.com>
++ *
++ * MMAL interface to VCHIQ message passing
++ */
++
++#ifndef MMAL_VCHIQ_H
++#define MMAL_VCHIQ_H
++
++#include "mmal-msg-format.h"
++
++#define MAX_PORT_COUNT 4
++
++/* Maximum size of the format extradata. */
++#define MMAL_FORMAT_EXTRADATA_MAX_SIZE 128
++
++struct vchiq_mmal_instance;
++
++enum vchiq_mmal_es_type {
++ MMAL_ES_TYPE_UNKNOWN, /**< Unknown elementary stream type */
++ MMAL_ES_TYPE_CONTROL, /**< Elementary stream of control commands */
++ MMAL_ES_TYPE_AUDIO, /**< Audio elementary stream */
++ MMAL_ES_TYPE_VIDEO, /**< Video elementary stream */
++ MMAL_ES_TYPE_SUBPICTURE /**< Sub-picture elementary stream */
++};
++
++/* rectangle, used lots so it gets its own struct */
++struct vchiq_mmal_rect {
++ s32 x;
++ s32 y;
++ s32 width;
++ s32 height;
++};
++
++struct vchiq_mmal_port_buffer {
++ unsigned int num; /* number of buffers */
++ u32 size; /* size of buffers */
++ u32 alignment; /* alignment of buffers */
++};
++
++struct vchiq_mmal_port;
++
++typedef void (*vchiq_mmal_buffer_cb)(
++ struct vchiq_mmal_instance *instance,
++ struct vchiq_mmal_port *port,
++ int status, struct mmal_buffer *buffer,
++ unsigned long length, u32 mmal_flags, s64 dts, s64 pts);
++
++struct vchiq_mmal_port {
++ bool enabled;
++ u32 handle;
++ u32 type; /* port type, cached to use on port info set */
++ u32 index; /* port index, cached to use on port info set */
++
++ /* component port belongs to, allows simple deref */
++ struct vchiq_mmal_component *component;
++
++ struct vchiq_mmal_port *connected; /* port conencted to */
++
++ /* buffer info */
++ struct vchiq_mmal_port_buffer minimum_buffer;
++ struct vchiq_mmal_port_buffer recommended_buffer;
++ struct vchiq_mmal_port_buffer current_buffer;
++
++ /* stream format */
++ struct mmal_es_format format;
++ /* elementry stream format */
++ union mmal_es_specific_format es;
++
++ /* data buffers to fill */
++ struct list_head buffers;
++ /* lock to serialise adding and removing buffers from list */
++ spinlock_t slock;
++ /* count of how many buffer header refils have failed because
++ * there was no buffer to satisfy them
++ */
++ int buffer_underflow;
++ /* callback on buffer completion */
++ vchiq_mmal_buffer_cb buffer_cb;
++ /* callback context */
++ void *cb_ctx;
++};
++
++struct vchiq_mmal_component {
++ bool enabled;
++ u32 handle; /* VideoCore handle for component */
++ u32 inputs; /* Number of input ports */
++ u32 outputs; /* Number of output ports */
++ u32 clocks; /* Number of clock ports */
++ struct vchiq_mmal_port control; /* control port */
++ struct vchiq_mmal_port input[MAX_PORT_COUNT]; /* input ports */
++ struct vchiq_mmal_port output[MAX_PORT_COUNT]; /* output ports */
++ struct vchiq_mmal_port clock[MAX_PORT_COUNT]; /* clock ports */
++};
++
++
++int vchiq_mmal_init(struct vchiq_mmal_instance **out_instance);
++int vchiq_mmal_finalise(struct vchiq_mmal_instance *instance);
++
++/* Initialise a mmal component and its ports
++*
++*/
++int vchiq_mmal_component_init(
++ struct vchiq_mmal_instance *instance,
++ const char *name,
++ struct vchiq_mmal_component **component_out);
++
++int vchiq_mmal_component_finalise(
++ struct vchiq_mmal_instance *instance,
++ struct vchiq_mmal_component *component);
++
++int vchiq_mmal_component_enable(
++ struct vchiq_mmal_instance *instance,
++ struct vchiq_mmal_component *component);
++
++int vchiq_mmal_component_disable(
++ struct vchiq_mmal_instance *instance,
++ struct vchiq_mmal_component *component);
++
++
++
++/* enable a mmal port
++ *
++ * enables a port and if a buffer callback provided enque buffer
++ * headers as apropriate for the port.
++ */
++int vchiq_mmal_port_enable(
++ struct vchiq_mmal_instance *instance,
++ struct vchiq_mmal_port *port,
++ vchiq_mmal_buffer_cb buffer_cb);
++
++/* disable a port
++ *
++ * disable a port will dequeue any pending buffers
++ */
++int vchiq_mmal_port_disable(struct vchiq_mmal_instance *instance,
++ struct vchiq_mmal_port *port);
++
++
++int vchiq_mmal_port_parameter_set(struct vchiq_mmal_instance *instance,
++ struct vchiq_mmal_port *port,
++ u32 parameter,
++ void *value,
++ u32 value_size);
++
++int vchiq_mmal_port_parameter_get(struct vchiq_mmal_instance *instance,
++ struct vchiq_mmal_port *port,
++ u32 parameter,
++ void *value,
++ u32 *value_size);
++
++int vchiq_mmal_port_set_format(struct vchiq_mmal_instance *instance,
++ struct vchiq_mmal_port *port);
++
++int vchiq_mmal_port_connect_tunnel(struct vchiq_mmal_instance *instance,
++ struct vchiq_mmal_port *src,
++ struct vchiq_mmal_port *dst);
++
++int vchiq_mmal_version(struct vchiq_mmal_instance *instance,
++ u32 *major_out,
++ u32 *minor_out);
++
++int vchiq_mmal_submit_buffer(struct vchiq_mmal_instance *instance,
++ struct vchiq_mmal_port *port,
++ struct mmal_buffer *buf);
++
++#endif /* MMAL_VCHIQ_H */
+diff -Nur linux-4.1.3/drivers/media/platform/Kconfig linux-xbian-rpi/drivers/media/platform/Kconfig
+--- linux-4.1.3/drivers/media/platform/Kconfig 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/media/platform/Kconfig 2015-07-28 01:20:58.198038163 +0200
+@@ -11,6 +11,8 @@
+
+ if V4L_PLATFORM_DRIVERS
+
++source "drivers/media/platform/bcm2835/Kconfig"
++
+ source "drivers/media/platform/marvell-ccic/Kconfig"
+
+ config VIDEO_VIA_CAMERA
+diff -Nur linux-4.1.3/drivers/media/platform/Makefile linux-xbian-rpi/drivers/media/platform/Makefile
+--- linux-4.1.3/drivers/media/platform/Makefile 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/media/platform/Makefile 2015-07-28 01:20:58.198038163 +0200
+@@ -2,6 +2,8 @@
+ # Makefile for the video capture/playback device drivers.
+ #
+
++obj-$(CONFIG_VIDEO_BCM2835) += bcm2835/
++
+ obj-$(CONFIG_VIDEO_TIMBERDALE) += timblogiw.o
+ obj-$(CONFIG_VIDEO_M32R_AR_M64278) += arv.o
+
+diff -Nur linux-4.1.3/drivers/media/usb/dvb-usb-v2/rtl28xxu.c linux-xbian-rpi/drivers/media/usb/dvb-usb-v2/rtl28xxu.c
+--- linux-4.1.3/drivers/media/usb/dvb-usb-v2/rtl28xxu.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/media/usb/dvb-usb-v2/rtl28xxu.c 2015-07-28 01:20:58.281739526 +0200
+@@ -1744,6 +1744,10 @@
+ &rtl28xxu_props, "Compro VideoMate U620F", NULL) },
+ { DVB_USB_DEVICE(USB_VID_KWORLD_2, 0xd394,
+ &rtl28xxu_props, "MaxMedia HU394-T", NULL) },
++ { DVB_USB_DEVICE(USB_VID_GTEK, 0xb803 /*USB_PID_AUGUST_DVBT205*/,
++ &rtl28xxu_props, "August DVB-T 205", NULL) },
++ { DVB_USB_DEVICE(USB_VID_GTEK, 0xa803 /*USB_PID_AUGUST_DVBT205*/,
++ &rtl28xxu_props, "August DVB-T 205", NULL) },
+ { DVB_USB_DEVICE(USB_VID_LEADTEK, 0x6a03,
+ &rtl28xxu_props, "Leadtek WinFast DTV Dongle mini", NULL) },
+ { DVB_USB_DEVICE(USB_VID_GTEK, USB_PID_CPYTO_REDI_PC50A,
+diff -Nur linux-4.1.3/drivers/mfd/Kconfig linux-xbian-rpi/drivers/mfd/Kconfig
+--- linux-4.1.3/drivers/mfd/Kconfig 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/mfd/Kconfig 2015-07-28 01:20:58.281739526 +0200
+@@ -10,6 +10,14 @@
+ select IRQ_DOMAIN
+ default n
+
++config MFD_RPISENSE_CORE
++ tristate "Raspberry Pi Sense HAT core functions"
++ depends on I2C
++ select MFD_CORE
++ help
++ This is the core driver for the Raspberry Pi Sense HAT. This provides
++ the necessary functions to communicate with the hardware.
++
+ config MFD_CS5535
+ tristate "AMD CS5535 and CS5536 southbridge core functions"
+ select MFD_CORE
+diff -Nur linux-4.1.3/drivers/mfd/Makefile linux-xbian-rpi/drivers/mfd/Makefile
+--- linux-4.1.3/drivers/mfd/Makefile 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/mfd/Makefile 2015-07-28 01:20:58.281739526 +0200
+@@ -185,3 +185,5 @@
+ intel-soc-pmic-objs := intel_soc_pmic_core.o intel_soc_pmic_crc.o
+ obj-$(CONFIG_INTEL_SOC_PMIC) += intel-soc-pmic.o
+ obj-$(CONFIG_MFD_MT6397) += mt6397-core.o
++
++obj-$(CONFIG_MFD_RPISENSE_CORE) += rpisense-core.o
+diff -Nur linux-4.1.3/drivers/mfd/rpisense-core.c linux-xbian-rpi/drivers/mfd/rpisense-core.c
+--- linux-4.1.3/drivers/mfd/rpisense-core.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/mfd/rpisense-core.c 2015-07-28 01:20:58.281739526 +0200
+@@ -0,0 +1,157 @@
++/*
++ * Raspberry Pi Sense HAT core driver
++ * http://raspberrypi.org
++ *
++ * Copyright (C) 2015 Raspberry Pi
++ *
++ * Author: Serge Schneider
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * This driver is based on wm8350 implementation.
++ */
++
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/err.h>
++#include <linux/init.h>
++#include <linux/i2c.h>
++#include <linux/platform_device.h>
++#include <linux/mfd/rpisense/core.h>
++#include <linux/slab.h>
++
++struct rpisense *rpisense;
++
++static void rpisense_client_dev_register(struct rpisense *rpisense,
++ const char *name,
++ struct platform_device **pdev)
++{
++ int ret;
++
++ *pdev = platform_device_alloc(name, -1);
++ if (*pdev == NULL) {
++ dev_err(rpisense->dev, "Failed to allocate %s\n", name);
++ return;
++ }
++
++ (*pdev)->dev.parent = rpisense->dev;
++ platform_set_drvdata(*pdev, rpisense);
++ ret = platform_device_add(*pdev);
++ if (ret != 0) {
++ dev_err(rpisense->dev, "Failed to register %s: %d\n",
++ name, ret);
++ platform_device_put(*pdev);
++ *pdev = NULL;
++ }
++}
++
++static int rpisense_probe(struct i2c_client *i2c,
++ const struct i2c_device_id *id)
++{
++ int ret;
++ struct rpisense_js *rpisense_js;
++
++ rpisense = devm_kzalloc(&i2c->dev, sizeof(struct rpisense), GFP_KERNEL);
++ if (rpisense == NULL)
++ return -ENOMEM;
++
++ i2c_set_clientdata(i2c, rpisense);
++ rpisense->dev = &i2c->dev;
++ rpisense->i2c_client = i2c;
++
++ ret = rpisense_reg_read(rpisense, RPISENSE_WAI);
++ if (ret > 0) {
++ if (ret != 's')
++ return -EINVAL;
++ } else {
++ return ret;
++ }
++ ret = rpisense_reg_read(rpisense, RPISENSE_VER);
++ if (ret < 0)
++ return ret;
++
++ dev_info(rpisense->dev,
++ "Raspberry Pi Sense HAT firmware version %i\n", ret);
++
++ rpisense_js = &rpisense->joystick;
++ rpisense_js->keys_desc = devm_gpiod_get(&i2c->dev,
++ "keys-int", GPIOD_IN);
++ if (IS_ERR(rpisense_js->keys_desc)) {
++ dev_warn(&i2c->dev, "Failed to get keys-int descriptor.\n");
++ rpisense_js->keys_desc = gpio_to_desc(23);
++ if (rpisense_js->keys_desc == NULL) {
++ dev_err(&i2c->dev, "GPIO23 fallback failed.\n");
++ return PTR_ERR(rpisense_js->keys_desc);
++ }
++ }
++ rpisense_client_dev_register(rpisense, "rpi-sense-js",
++ &(rpisense->joystick.pdev));
++ rpisense_client_dev_register(rpisense, "rpi-sense-fb",
++ &(rpisense->framebuffer.pdev));
++
++ return 0;
++}
++
++static int rpisense_remove(struct i2c_client *i2c)
++{
++ struct rpisense *rpisense = i2c_get_clientdata(i2c);
++
++ platform_device_unregister(rpisense->joystick.pdev);
++ return 0;
++}
++
++struct rpisense *rpisense_get_dev(void)
++{
++ return rpisense;
++}
++EXPORT_SYMBOL_GPL(rpisense_get_dev);
++
++s32 rpisense_reg_read(struct rpisense *rpisense, int reg)
++{
++ int ret = i2c_smbus_read_byte_data(rpisense->i2c_client, reg);
++
++ if (ret < 0)
++ dev_err(rpisense->dev, "Read from reg %d failed\n", reg);
++ /* Due to the BCM270x I2C clock stretching bug, some values
++ * may have MSB set. Clear it to avoid incorrect values.
++ * */
++ return ret & 0x7F;
++}
++EXPORT_SYMBOL_GPL(rpisense_reg_read);
++
++int rpisense_block_write(struct rpisense *rpisense, const char *buf, int count)
++{
++ int ret = i2c_master_send(rpisense->i2c_client, buf, count);
++
++ if (ret < 0)
++ dev_err(rpisense->dev, "Block write failed\n");
++ return ret;
++}
++EXPORT_SYMBOL_GPL(rpisense_block_write);
++
++static const struct i2c_device_id rpisense_i2c_id[] = {
++ { "rpi-sense", 0 },
++ { }
++};
++MODULE_DEVICE_TABLE(i2c, rpisense_i2c_id);
++
++
++static struct i2c_driver rpisense_driver = {
++ .driver = {
++ .name = "rpi-sense",
++ .owner = THIS_MODULE,
++ },
++ .probe = rpisense_probe,
++ .remove = rpisense_remove,
++ .id_table = rpisense_i2c_id,
++};
++
++module_i2c_driver(rpisense_driver);
++
++MODULE_DESCRIPTION("Raspberry Pi Sense HAT core driver");
++MODULE_AUTHOR("Serge Schneider <serge@raspberrypi.org>");
++MODULE_LICENSE("GPL");
++
+diff -Nur linux-4.1.3/drivers/misc/Kconfig linux-xbian-rpi/drivers/misc/Kconfig
+--- linux-4.1.3/drivers/misc/Kconfig 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/misc/Kconfig 2015-07-28 01:20:58.281739526 +0200
+@@ -524,6 +524,7 @@
+ source "drivers/misc/altera-stapl/Kconfig"
+ source "drivers/misc/mei/Kconfig"
+ source "drivers/misc/vmw_vmci/Kconfig"
++source "drivers/misc/vc04_services/Kconfig"
+ source "drivers/misc/mic/Kconfig"
+ source "drivers/misc/genwqe/Kconfig"
+ source "drivers/misc/echo/Kconfig"
+diff -Nur linux-4.1.3/drivers/misc/Makefile linux-xbian-rpi/drivers/misc/Makefile
+--- linux-4.1.3/drivers/misc/Makefile 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/misc/Makefile 2015-07-28 01:20:58.281739526 +0200
+@@ -51,6 +51,7 @@
+ obj-$(CONFIG_VMWARE_VMCI) += vmw_vmci/
+ obj-$(CONFIG_LATTICE_ECP3_CONFIG) += lattice-ecp3-config.o
+ obj-$(CONFIG_SRAM) += sram.o
++obj-$(CONFIG_BCM2708_VCHIQ) += vc04_services/
+ obj-y += mic/
+ obj-$(CONFIG_GENWQE) += genwqe/
+ obj-$(CONFIG_ECHO) += echo/
+diff -Nur linux-4.1.3/drivers/misc/vc04_services/interface/vchi/connections/connection.h linux-xbian-rpi/drivers/misc/vc04_services/interface/vchi/connections/connection.h
+--- linux-4.1.3/drivers/misc/vc04_services/interface/vchi/connections/connection.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/misc/vc04_services/interface/vchi/connections/connection.h 2015-07-28 01:20:58.281739526 +0200
+@@ -0,0 +1,328 @@
++/**
++ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ * 1. Redistributions of source code must retain the above copyright
++ * notice, this list of conditions, and the following disclaimer,
++ * without modification.
++ * 2. Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * 3. The names of the above-listed copyright holders may not be used
++ * to endorse or promote products derived from this software without
++ * specific prior written permission.
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") version 2, as published by the Free
++ * Software Foundation.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#ifndef CONNECTION_H_
++#define CONNECTION_H_
++
++#include <linux/kernel.h>
++#include <linux/types.h>
++#include <linux/semaphore.h>
++
++#include "interface/vchi/vchi_cfg_internal.h"
++#include "interface/vchi/vchi_common.h"
++#include "interface/vchi/message_drivers/message.h"
++
++/******************************************************************************
++ Global defs
++ *****************************************************************************/
++
++// Opaque handle for a connection / service pair
++typedef struct opaque_vchi_connection_connected_service_handle_t *VCHI_CONNECTION_SERVICE_HANDLE_T;
++
++// opaque handle to the connection state information
++typedef struct opaque_vchi_connection_info_t VCHI_CONNECTION_STATE_T;
++
++typedef struct vchi_connection_t VCHI_CONNECTION_T;
++
++
++/******************************************************************************
++ API
++ *****************************************************************************/
++
++// Routine to init a connection with a particular low level driver
++typedef VCHI_CONNECTION_STATE_T * (*VCHI_CONNECTION_INIT_T)( struct vchi_connection_t * connection,
++ const VCHI_MESSAGE_DRIVER_T * driver );
++
++// Routine to control CRC enabling at a connection level
++typedef int32_t (*VCHI_CONNECTION_CRC_CONTROL_T)( VCHI_CONNECTION_STATE_T *state_handle,
++ VCHI_CRC_CONTROL_T control );
++
++// Routine to create a service
++typedef int32_t (*VCHI_CONNECTION_SERVICE_CONNECT_T)( VCHI_CONNECTION_STATE_T *state_handle,
++ int32_t service_id,
++ uint32_t rx_fifo_size,
++ uint32_t tx_fifo_size,
++ int server,
++ VCHI_CALLBACK_T callback,
++ void *callback_param,
++ int32_t want_crc,
++ int32_t want_unaligned_bulk_rx,
++ int32_t want_unaligned_bulk_tx,
++ VCHI_CONNECTION_SERVICE_HANDLE_T *service_handle );
++
++// Routine to close a service
++typedef int32_t (*VCHI_CONNECTION_SERVICE_DISCONNECT_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle );
++
++// Routine to queue a message
++typedef int32_t (*VCHI_CONNECTION_SERVICE_QUEUE_MESSAGE_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle,
++ const void *data,
++ uint32_t data_size,
++ VCHI_FLAGS_T flags,
++ void *msg_handle );
++
++// scatter-gather (vector) message queueing
++typedef int32_t (*VCHI_CONNECTION_SERVICE_QUEUE_MESSAGEV_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle,
++ VCHI_MSG_VECTOR_T *vector,
++ uint32_t count,
++ VCHI_FLAGS_T flags,
++ void *msg_handle );
++
++// Routine to dequeue a message
++typedef int32_t (*VCHI_CONNECTION_SERVICE_DEQUEUE_MESSAGE_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle,
++ void *data,
++ uint32_t max_data_size_to_read,
++ uint32_t *actual_msg_size,
++ VCHI_FLAGS_T flags );
++
++// Routine to peek at a message
++typedef int32_t (*VCHI_CONNECTION_SERVICE_PEEK_MESSAGE_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle,
++ void **data,
++ uint32_t *msg_size,
++ VCHI_FLAGS_T flags );
++
++// Routine to hold a message
++typedef int32_t (*VCHI_CONNECTION_SERVICE_HOLD_MESSAGE_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle,
++ void **data,
++ uint32_t *msg_size,
++ VCHI_FLAGS_T flags,
++ void **message_handle );
++
++// Routine to initialise a received message iterator
++typedef int32_t (*VCHI_CONNECTION_SERVICE_LOOKAHEAD_MESSAGE_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle,
++ VCHI_MSG_ITER_T *iter,
++ VCHI_FLAGS_T flags );
++
++// Routine to release a held message
++typedef int32_t (*VCHI_CONNECTION_HELD_MSG_RELEASE_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle,
++ void *message_handle );
++
++// Routine to get info on a held message
++typedef int32_t (*VCHI_CONNECTION_HELD_MSG_INFO_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle,
++ void *message_handle,
++ void **data,
++ int32_t *msg_size,
++ uint32_t *tx_timestamp,
++ uint32_t *rx_timestamp );
++
++// Routine to check whether the iterator has a next message
++typedef int32_t (*VCHI_CONNECTION_MSG_ITER_HAS_NEXT_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service,
++ const VCHI_MSG_ITER_T *iter );
++
++// Routine to advance the iterator
++typedef int32_t (*VCHI_CONNECTION_MSG_ITER_NEXT_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service,
++ VCHI_MSG_ITER_T *iter,
++ void **data,
++ uint32_t *msg_size );
++
++// Routine to remove the last message returned by the iterator
++typedef int32_t (*VCHI_CONNECTION_MSG_ITER_REMOVE_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service,
++ VCHI_MSG_ITER_T *iter );
++
++// Routine to hold the last message returned by the iterator
++typedef int32_t (*VCHI_CONNECTION_MSG_ITER_HOLD_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service,
++ VCHI_MSG_ITER_T *iter,
++ void **msg_handle );
++
++// Routine to transmit bulk data
++typedef int32_t (*VCHI_CONNECTION_BULK_QUEUE_TRANSMIT_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle,
++ const void *data_src,
++ uint32_t data_size,
++ VCHI_FLAGS_T flags,
++ void *bulk_handle );
++
++// Routine to receive data
++typedef int32_t (*VCHI_CONNECTION_BULK_QUEUE_RECEIVE_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle,
++ void *data_dst,
++ uint32_t data_size,
++ VCHI_FLAGS_T flags,
++ void *bulk_handle );
++
++// Routine to report if a server is available
++typedef int32_t (*VCHI_CONNECTION_SERVER_PRESENT)( VCHI_CONNECTION_STATE_T *state, int32_t service_id, int32_t peer_flags );
++
++// Routine to report the number of RX slots available
++typedef int (*VCHI_CONNECTION_RX_SLOTS_AVAILABLE)( const VCHI_CONNECTION_STATE_T *state );
++
++// Routine to report the RX slot size
++typedef uint32_t (*VCHI_CONNECTION_RX_SLOT_SIZE)( const VCHI_CONNECTION_STATE_T *state );
++
++// Callback to indicate that the other side has added a buffer to the rx bulk DMA FIFO
++typedef void (*VCHI_CONNECTION_RX_BULK_BUFFER_ADDED)(VCHI_CONNECTION_STATE_T *state,
++ int32_t service,
++ uint32_t length,
++ MESSAGE_TX_CHANNEL_T channel,
++ uint32_t channel_params,
++ uint32_t data_length,
++ uint32_t data_offset);
++
++// Callback to inform a service that a Xon or Xoff message has been received
++typedef void (*VCHI_CONNECTION_FLOW_CONTROL)(VCHI_CONNECTION_STATE_T *state, int32_t service_id, int32_t xoff);
++
++// Callback to inform a service that a server available reply message has been received
++typedef void (*VCHI_CONNECTION_SERVER_AVAILABLE_REPLY)(VCHI_CONNECTION_STATE_T *state, int32_t service_id, uint32_t flags);
++
++// Callback to indicate that bulk auxiliary messages have arrived
++typedef void (*VCHI_CONNECTION_BULK_AUX_RECEIVED)(VCHI_CONNECTION_STATE_T *state);
++
++// Callback to indicate that bulk auxiliary messages have arrived
++typedef void (*VCHI_CONNECTION_BULK_AUX_TRANSMITTED)(VCHI_CONNECTION_STATE_T *state, void *handle);
++
++// Callback with all the connection info you require
++typedef void (*VCHI_CONNECTION_INFO)(VCHI_CONNECTION_STATE_T *state, uint32_t protocol_version, uint32_t slot_size, uint32_t num_slots, uint32_t min_bulk_size);
++
++// Callback to inform of a disconnect
++typedef void (*VCHI_CONNECTION_DISCONNECT)(VCHI_CONNECTION_STATE_T *state, uint32_t flags);
++
++// Callback to inform of a power control request
++typedef void (*VCHI_CONNECTION_POWER_CONTROL)(VCHI_CONNECTION_STATE_T *state, MESSAGE_TX_CHANNEL_T channel, int32_t enable);
++
++// allocate memory suitably aligned for this connection
++typedef void * (*VCHI_BUFFER_ALLOCATE)(VCHI_CONNECTION_SERVICE_HANDLE_T service_handle, uint32_t * length);
++
++// free memory allocated by buffer_allocate
++typedef void (*VCHI_BUFFER_FREE)(VCHI_CONNECTION_SERVICE_HANDLE_T service_handle, void * address);
++
++
++/******************************************************************************
++ System driver struct
++ *****************************************************************************/
++
++struct opaque_vchi_connection_api_t
++{
++ // Routine to init the connection
++ VCHI_CONNECTION_INIT_T init;
++
++ // Connection-level CRC control
++ VCHI_CONNECTION_CRC_CONTROL_T crc_control;
++
++ // Routine to connect to or create service
++ VCHI_CONNECTION_SERVICE_CONNECT_T service_connect;
++
++ // Routine to disconnect from a service
++ VCHI_CONNECTION_SERVICE_DISCONNECT_T service_disconnect;
++
++ // Routine to queue a message
++ VCHI_CONNECTION_SERVICE_QUEUE_MESSAGE_T service_queue_msg;
++
++ // scatter-gather (vector) message queue
++ VCHI_CONNECTION_SERVICE_QUEUE_MESSAGEV_T service_queue_msgv;
++
++ // Routine to dequeue a message
++ VCHI_CONNECTION_SERVICE_DEQUEUE_MESSAGE_T service_dequeue_msg;
++
++ // Routine to peek at a message
++ VCHI_CONNECTION_SERVICE_PEEK_MESSAGE_T service_peek_msg;
++
++ // Routine to hold a message
++ VCHI_CONNECTION_SERVICE_HOLD_MESSAGE_T service_hold_msg;
++
++ // Routine to initialise a received message iterator
++ VCHI_CONNECTION_SERVICE_LOOKAHEAD_MESSAGE_T service_look_ahead_msg;
++
++ // Routine to release a message
++ VCHI_CONNECTION_HELD_MSG_RELEASE_T held_msg_release;
++
++ // Routine to get information on a held message
++ VCHI_CONNECTION_HELD_MSG_INFO_T held_msg_info;
++
++ // Routine to check for next message on iterator
++ VCHI_CONNECTION_MSG_ITER_HAS_NEXT_T msg_iter_has_next;
++
++ // Routine to get next message on iterator
++ VCHI_CONNECTION_MSG_ITER_NEXT_T msg_iter_next;
++
++ // Routine to remove the last message returned by iterator
++ VCHI_CONNECTION_MSG_ITER_REMOVE_T msg_iter_remove;
++
++ // Routine to hold the last message returned by iterator
++ VCHI_CONNECTION_MSG_ITER_HOLD_T msg_iter_hold;
++
++ // Routine to transmit bulk data
++ VCHI_CONNECTION_BULK_QUEUE_TRANSMIT_T bulk_queue_transmit;
++
++ // Routine to receive data
++ VCHI_CONNECTION_BULK_QUEUE_RECEIVE_T bulk_queue_receive;
++
++ // Routine to report the available servers
++ VCHI_CONNECTION_SERVER_PRESENT server_present;
++
++ // Routine to report the number of RX slots available
++ VCHI_CONNECTION_RX_SLOTS_AVAILABLE connection_rx_slots_available;
++
++ // Routine to report the RX slot size
++ VCHI_CONNECTION_RX_SLOT_SIZE connection_rx_slot_size;
++
++ // Callback to indicate that the other side has added a buffer to the rx bulk DMA FIFO
++ VCHI_CONNECTION_RX_BULK_BUFFER_ADDED rx_bulk_buffer_added;
++
++ // Callback to inform a service that a Xon or Xoff message has been received
++ VCHI_CONNECTION_FLOW_CONTROL flow_control;
++
++ // Callback to inform a service that a server available reply message has been received
++ VCHI_CONNECTION_SERVER_AVAILABLE_REPLY server_available_reply;
++
++ // Callback to indicate that bulk auxiliary messages have arrived
++ VCHI_CONNECTION_BULK_AUX_RECEIVED bulk_aux_received;
++
++ // Callback to indicate that a bulk auxiliary message has been transmitted
++ VCHI_CONNECTION_BULK_AUX_TRANSMITTED bulk_aux_transmitted;
++
++ // Callback to provide information about the connection
++ VCHI_CONNECTION_INFO connection_info;
++
++ // Callback to notify that peer has requested disconnect
++ VCHI_CONNECTION_DISCONNECT disconnect;
++
++ // Callback to notify that peer has requested power change
++ VCHI_CONNECTION_POWER_CONTROL power_control;
++
++ // allocate memory suitably aligned for this connection
++ VCHI_BUFFER_ALLOCATE buffer_allocate;
++
++ // free memory allocated by buffer_allocate
++ VCHI_BUFFER_FREE buffer_free;
++
++};
++
++struct vchi_connection_t {
++ const VCHI_CONNECTION_API_T *api;
++ VCHI_CONNECTION_STATE_T *state;
++#ifdef VCHI_COARSE_LOCKING
++ struct semaphore sem;
++#endif
++};
++
++
++#endif /* CONNECTION_H_ */
++
++/****************************** End of file **********************************/
+diff -Nur linux-4.1.3/drivers/misc/vc04_services/interface/vchi/message_drivers/message.h linux-xbian-rpi/drivers/misc/vc04_services/interface/vchi/message_drivers/message.h
+--- linux-4.1.3/drivers/misc/vc04_services/interface/vchi/message_drivers/message.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/misc/vc04_services/interface/vchi/message_drivers/message.h 2015-07-28 01:20:58.281739526 +0200
+@@ -0,0 +1,204 @@
++/**
++ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ * 1. Redistributions of source code must retain the above copyright
++ * notice, this list of conditions, and the following disclaimer,
++ * without modification.
++ * 2. Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * 3. The names of the above-listed copyright holders may not be used
++ * to endorse or promote products derived from this software without
++ * specific prior written permission.
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") version 2, as published by the Free
++ * Software Foundation.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#ifndef _VCHI_MESSAGE_H_
++#define _VCHI_MESSAGE_H_
++
++#include <linux/kernel.h>
++#include <linux/types.h>
++#include <linux/semaphore.h>
++
++#include "interface/vchi/vchi_cfg_internal.h"
++#include "interface/vchi/vchi_common.h"
++
++
++typedef enum message_event_type {
++ MESSAGE_EVENT_NONE,
++ MESSAGE_EVENT_NOP,
++ MESSAGE_EVENT_MESSAGE,
++ MESSAGE_EVENT_SLOT_COMPLETE,
++ MESSAGE_EVENT_RX_BULK_PAUSED,
++ MESSAGE_EVENT_RX_BULK_COMPLETE,
++ MESSAGE_EVENT_TX_COMPLETE,
++ MESSAGE_EVENT_MSG_DISCARDED
++} MESSAGE_EVENT_TYPE_T;
++
++typedef enum vchi_msg_flags
++{
++ VCHI_MSG_FLAGS_NONE = 0x0,
++ VCHI_MSG_FLAGS_TERMINATE_DMA = 0x1
++} VCHI_MSG_FLAGS_T;
++
++typedef enum message_tx_channel
++{
++ MESSAGE_TX_CHANNEL_MESSAGE = 0,
++ MESSAGE_TX_CHANNEL_BULK = 1 // drivers may provide multiple bulk channels, from 1 upwards
++} MESSAGE_TX_CHANNEL_T;
++
++// Macros used for cycling through bulk channels
++#define MESSAGE_TX_CHANNEL_BULK_PREV(c) (MESSAGE_TX_CHANNEL_BULK+((c)-MESSAGE_TX_CHANNEL_BULK+VCHI_MAX_BULK_TX_CHANNELS_PER_CONNECTION-1)%VCHI_MAX_BULK_TX_CHANNELS_PER_CONNECTION)
++#define MESSAGE_TX_CHANNEL_BULK_NEXT(c) (MESSAGE_TX_CHANNEL_BULK+((c)-MESSAGE_TX_CHANNEL_BULK+1)%VCHI_MAX_BULK_TX_CHANNELS_PER_CONNECTION)
++
++typedef enum message_rx_channel
++{
++ MESSAGE_RX_CHANNEL_MESSAGE = 0,
++ MESSAGE_RX_CHANNEL_BULK = 1 // drivers may provide multiple bulk channels, from 1 upwards
++} MESSAGE_RX_CHANNEL_T;
++
++// Message receive slot information
++typedef struct rx_msg_slot_info {
++
++ struct rx_msg_slot_info *next;
++ //struct slot_info *prev;
++#if !defined VCHI_COARSE_LOCKING
++ struct semaphore sem;
++#endif
++
++ uint8_t *addr; // base address of slot
++ uint32_t len; // length of slot in bytes
++
++ uint32_t write_ptr; // hardware causes this to advance
++ uint32_t read_ptr; // this module does the reading
++ int active; // is this slot in the hardware dma fifo?
++ uint32_t msgs_parsed; // count how many messages are in this slot
++ uint32_t msgs_released; // how many messages have been released
++ void *state; // connection state information
++ uint8_t ref_count[VCHI_MAX_SERVICES_PER_CONNECTION]; // reference count for slots held by services
++} RX_MSG_SLOTINFO_T;
++
++// The message driver no longer needs to know about the fields of RX_BULK_SLOTINFO_T - sort this out.
++// In particular, it mustn't use addr and len - they're the client buffer, but the message
++// driver will be tasked with sending the aligned core section.
++typedef struct rx_bulk_slotinfo_t {
++ struct rx_bulk_slotinfo_t *next;
++
++ struct semaphore *blocking;
++
++ // needed by DMA
++ void *addr;
++ uint32_t len;
++
++ // needed for the callback
++ void *service;
++ void *handle;
++ VCHI_FLAGS_T flags;
++} RX_BULK_SLOTINFO_T;
++
++
++/* ----------------------------------------------------------------------
++ * each connection driver will have a pool of the following struct.
++ *
++ * the pool will be managed by vchi_qman_*
++ * this means there will be multiple queues (single linked lists)
++ * a given struct message_info will be on exactly one of these queues
++ * at any one time
++ * -------------------------------------------------------------------- */
++typedef struct rx_message_info {
++
++ struct message_info *next;
++ //struct message_info *prev;
++
++ uint8_t *addr;
++ uint32_t len;
++ RX_MSG_SLOTINFO_T *slot; // points to whichever slot contains this message
++ uint32_t tx_timestamp;
++ uint32_t rx_timestamp;
++
++} RX_MESSAGE_INFO_T;
++
++typedef struct {
++ MESSAGE_EVENT_TYPE_T type;
++
++ struct {
++ // for messages
++ void *addr; // address of message
++ uint16_t slot_delta; // whether this message indicated slot delta
++ uint32_t len; // length of message
++ RX_MSG_SLOTINFO_T *slot; // slot this message is in
++ int32_t service; // service id this message is destined for
++ uint32_t tx_timestamp; // timestamp from the header
++ uint32_t rx_timestamp; // timestamp when we parsed it
++ } message;
++
++ // FIXME: cleanup slot reporting...
++ RX_MSG_SLOTINFO_T *rx_msg;
++ RX_BULK_SLOTINFO_T *rx_bulk;
++ void *tx_handle;
++ MESSAGE_TX_CHANNEL_T tx_channel;
++
++} MESSAGE_EVENT_T;
++
++
++// callbacks
++typedef void VCHI_MESSAGE_DRIVER_EVENT_CALLBACK_T( void *state );
++
++typedef struct {
++ VCHI_MESSAGE_DRIVER_EVENT_CALLBACK_T *event_callback;
++} VCHI_MESSAGE_DRIVER_OPEN_T;
++
++
++// handle to this instance of message driver (as returned by ->open)
++typedef struct opaque_mhandle_t *VCHI_MDRIVER_HANDLE_T;
++
++struct opaque_vchi_message_driver_t {
++ VCHI_MDRIVER_HANDLE_T *(*open)( VCHI_MESSAGE_DRIVER_OPEN_T *params, void *state );
++ int32_t (*suspending)( VCHI_MDRIVER_HANDLE_T *handle );
++ int32_t (*resumed)( VCHI_MDRIVER_HANDLE_T *handle );
++ int32_t (*power_control)( VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_TX_CHANNEL_T, int32_t enable );
++ int32_t (*add_msg_rx_slot)( VCHI_MDRIVER_HANDLE_T *handle, RX_MSG_SLOTINFO_T *slot ); // rx message
++ int32_t (*add_bulk_rx)( VCHI_MDRIVER_HANDLE_T *handle, void *data, uint32_t len, RX_BULK_SLOTINFO_T *slot ); // rx data (bulk)
++ int32_t (*send)( VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_TX_CHANNEL_T channel, const void *data, uint32_t len, VCHI_MSG_FLAGS_T flags, void *send_handle ); // tx (message & bulk)
++ void (*next_event)( VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_EVENT_T *event ); // get the next event from message_driver
++ int32_t (*enable)( VCHI_MDRIVER_HANDLE_T *handle );
++ int32_t (*form_message)( VCHI_MDRIVER_HANDLE_T *handle, int32_t service_id, VCHI_MSG_VECTOR_T *vector, uint32_t count, void
++ *address, uint32_t length_avail, uint32_t max_total_length, int32_t pad_to_fill, int32_t allow_partial );
++
++ int32_t (*update_message)( VCHI_MDRIVER_HANDLE_T *handle, void *dest, int16_t *slot_count );
++ int32_t (*buffer_aligned)( VCHI_MDRIVER_HANDLE_T *handle, int tx, int uncached, const void *address, const uint32_t length );
++ void * (*allocate_buffer)( VCHI_MDRIVER_HANDLE_T *handle, uint32_t *length );
++ void (*free_buffer)( VCHI_MDRIVER_HANDLE_T *handle, void *address );
++ int (*rx_slot_size)( VCHI_MDRIVER_HANDLE_T *handle, int msg_size );
++ int (*tx_slot_size)( VCHI_MDRIVER_HANDLE_T *handle, int msg_size );
++
++ int32_t (*tx_supports_terminate)( const VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_TX_CHANNEL_T channel );
++ uint32_t (*tx_bulk_chunk_size)( const VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_TX_CHANNEL_T channel );
++ int (*tx_alignment)( const VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_TX_CHANNEL_T channel );
++ int (*rx_alignment)( const VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_RX_CHANNEL_T channel );
++ void (*form_bulk_aux)( VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_TX_CHANNEL_T channel, const void *data, uint32_t len, uint32_t chunk_size, const void **aux_data, int32_t *aux_len );
++ void (*debug)( VCHI_MDRIVER_HANDLE_T *handle );
++};
++
++
++#endif // _VCHI_MESSAGE_H_
++
++/****************************** End of file ***********************************/
+diff -Nur linux-4.1.3/drivers/misc/vc04_services/interface/vchi/vchi_cfg.h linux-xbian-rpi/drivers/misc/vc04_services/interface/vchi/vchi_cfg.h
+--- linux-4.1.3/drivers/misc/vc04_services/interface/vchi/vchi_cfg.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/misc/vc04_services/interface/vchi/vchi_cfg.h 2015-07-28 01:20:58.281739526 +0200
+@@ -0,0 +1,224 @@
++/**
++ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ * 1. Redistributions of source code must retain the above copyright
++ * notice, this list of conditions, and the following disclaimer,
++ * without modification.
++ * 2. Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * 3. The names of the above-listed copyright holders may not be used
++ * to endorse or promote products derived from this software without
++ * specific prior written permission.
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") version 2, as published by the Free
++ * Software Foundation.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#ifndef VCHI_CFG_H_
++#define VCHI_CFG_H_
++
++/****************************************************************************************
++ * Defines in this first section are part of the VCHI API and may be examined by VCHI
++ * services.
++ ***************************************************************************************/
++
++/* Required alignment of base addresses for bulk transfer, if unaligned transfers are not enabled */
++/* Really determined by the message driver, and should be available from a run-time call. */
++#ifndef VCHI_BULK_ALIGN
++# if __VCCOREVER__ >= 0x04000000
++# define VCHI_BULK_ALIGN 32 // Allows for the need to do cache cleans
++# else
++# define VCHI_BULK_ALIGN 16
++# endif
++#endif
++
++/* Required length multiple for bulk transfers, if unaligned transfers are not enabled */
++/* May be less than or greater than VCHI_BULK_ALIGN */
++/* Really determined by the message driver, and should be available from a run-time call. */
++#ifndef VCHI_BULK_GRANULARITY
++# if __VCCOREVER__ >= 0x04000000
++# define VCHI_BULK_GRANULARITY 32 // Allows for the need to do cache cleans
++# else
++# define VCHI_BULK_GRANULARITY 16
++# endif
++#endif
++
++/* The largest possible message to be queued with vchi_msg_queue. */
++#ifndef VCHI_MAX_MSG_SIZE
++# if defined VCHI_LOCAL_HOST_PORT
++# define VCHI_MAX_MSG_SIZE 16384 // makes file transfers fast, but should they be using bulk?
++# else
++# define VCHI_MAX_MSG_SIZE 4096 // NOTE: THIS MUST BE LARGER THAN OR EQUAL TO THE SIZE OF THE KHRONOS MERGE BUFFER!!
++# endif
++#endif
++
++/******************************************************************************************
++ * Defines below are system configuration options, and should not be used by VCHI services.
++ *****************************************************************************************/
++
++/* How many connections can we support? A localhost implementation uses 2 connections,
++ * 1 for host-app, 1 for VMCS, and these are hooked together by a loopback MPHI VCFW
++ * driver. */
++#ifndef VCHI_MAX_NUM_CONNECTIONS
++# define VCHI_MAX_NUM_CONNECTIONS 3
++#endif
++
++/* How many services can we open per connection? Extending this doesn't cost processing time, just a small
++ * amount of static memory. */
++#ifndef VCHI_MAX_SERVICES_PER_CONNECTION
++# define VCHI_MAX_SERVICES_PER_CONNECTION 36
++#endif
++
++/* Adjust if using a message driver that supports more logical TX channels */
++#ifndef VCHI_MAX_BULK_TX_CHANNELS_PER_CONNECTION
++# define VCHI_MAX_BULK_TX_CHANNELS_PER_CONNECTION 9 // 1 MPHI + 8 CCP2 logical channels
++#endif
++
++/* Adjust if using a message driver that supports more logical RX channels */
++#ifndef VCHI_MAX_BULK_RX_CHANNELS_PER_CONNECTION
++# define VCHI_MAX_BULK_RX_CHANNELS_PER_CONNECTION 1 // 1 MPHI
++#endif
++
++/* How many receive slots do we use. This times VCHI_MAX_MSG_SIZE gives the effective
++ * receive queue space, less message headers. */
++#ifndef VCHI_NUM_READ_SLOTS
++# if defined(VCHI_LOCAL_HOST_PORT)
++# define VCHI_NUM_READ_SLOTS 4
++# else
++# define VCHI_NUM_READ_SLOTS 48
++# endif
++#endif
++
++/* Do we utilise overrun facility for receive message slots? Can aid peer transmit
++ * performance. Only define on VideoCore end, talking to host.
++ */
++//#define VCHI_MSG_RX_OVERRUN
++
++/* How many transmit slots do we use. Generally don't need many, as the hardware driver
++ * underneath VCHI will usually have its own buffering. */
++#ifndef VCHI_NUM_WRITE_SLOTS
++# define VCHI_NUM_WRITE_SLOTS 4
++#endif
++
++/* If a service has held or queued received messages in VCHI_XOFF_THRESHOLD or more slots,
++ * then it's taking up too much buffer space, and the peer service will be told to stop
++ * transmitting with an XOFF message. For this to be effective, the VCHI_NUM_READ_SLOTS
++ * needs to be considerably bigger than VCHI_NUM_WRITE_SLOTS, or the transmit latency
++ * is too high. */
++#ifndef VCHI_XOFF_THRESHOLD
++# define VCHI_XOFF_THRESHOLD (VCHI_NUM_READ_SLOTS / 2)
++#endif
++
++/* After we've sent an XOFF, the peer will be told to resume transmission once the local
++ * service has dequeued/released enough messages that it's now occupying
++ * VCHI_XON_THRESHOLD slots or fewer. */
++#ifndef VCHI_XON_THRESHOLD
++# define VCHI_XON_THRESHOLD (VCHI_NUM_READ_SLOTS / 4)
++#endif
++
++/* A size below which a bulk transfer omits the handshake completely and always goes
++ * via the message channel, if bulk auxiliary is being sent on that service. (The user
++ * can guarantee this by enabling unaligned transmits).
++ * Not API. */
++#ifndef VCHI_MIN_BULK_SIZE
++# define VCHI_MIN_BULK_SIZE ( VCHI_MAX_MSG_SIZE / 2 < 4096 ? VCHI_MAX_MSG_SIZE / 2 : 4096 )
++#endif
++
++/* Maximum size of bulk transmission chunks, for each interface type. A trade-off between
++ * speed and latency; the smaller the chunk size the better change of messages and other
++ * bulk transmissions getting in when big bulk transfers are happening. Set to 0 to not
++ * break transmissions into chunks.
++ */
++#ifndef VCHI_MAX_BULK_CHUNK_SIZE_MPHI
++# define VCHI_MAX_BULK_CHUNK_SIZE_MPHI (16 * 1024)
++#endif
++
++/* NB Chunked CCP2 transmissions violate the letter of the CCP2 spec by using "JPEG8" mode
++ * with multiple-line frames. Only use if the receiver can cope. */
++#ifndef VCHI_MAX_BULK_CHUNK_SIZE_CCP2
++# define VCHI_MAX_BULK_CHUNK_SIZE_CCP2 0
++#endif
++
++/* How many TX messages can we have pending in our transmit slots. Once exhausted,
++ * vchi_msg_queue will be blocked. */
++#ifndef VCHI_TX_MSG_QUEUE_SIZE
++# define VCHI_TX_MSG_QUEUE_SIZE 256
++#endif
++
++/* How many RX messages can we have parsed in the receive slots. Once exhausted, parsing
++ * will be suspended until older messages are dequeued/released. */
++#ifndef VCHI_RX_MSG_QUEUE_SIZE
++# define VCHI_RX_MSG_QUEUE_SIZE 256
++#endif
++
++/* Really should be able to cope if we run out of received message descriptors, by
++ * suspending parsing as the comment above says, but we don't. This sweeps the issue
++ * under the carpet. */
++#if VCHI_RX_MSG_QUEUE_SIZE < (VCHI_MAX_MSG_SIZE/16 + 1) * VCHI_NUM_READ_SLOTS
++# undef VCHI_RX_MSG_QUEUE_SIZE
++# define VCHI_RX_MSG_QUEUE_SIZE (VCHI_MAX_MSG_SIZE/16 + 1) * VCHI_NUM_READ_SLOTS
++#endif
++
++/* How many bulk transmits can we have pending. Once exhausted, vchi_bulk_queue_transmit
++ * will be blocked. */
++#ifndef VCHI_TX_BULK_QUEUE_SIZE
++# define VCHI_TX_BULK_QUEUE_SIZE 64
++#endif
++
++/* How many bulk receives can we have pending. Once exhausted, vchi_bulk_queue_receive
++ * will be blocked. */
++#ifndef VCHI_RX_BULK_QUEUE_SIZE
++# define VCHI_RX_BULK_QUEUE_SIZE 64
++#endif
++
++/* A limit on how many outstanding bulk requests we expect the peer to give us. If
++ * the peer asks for more than this, VCHI will fail and assert. The number is determined
++ * by the peer's hardware - it's the number of outstanding requests that can be queued
++ * on all bulk channels. VC3's MPHI peripheral allows 16. */
++#ifndef VCHI_MAX_PEER_BULK_REQUESTS
++# define VCHI_MAX_PEER_BULK_REQUESTS 32
++#endif
++
++/* Define VCHI_CCP2TX_MANUAL_POWER if the host tells us when to turn the CCP2
++ * transmitter on and off.
++ */
++/*#define VCHI_CCP2TX_MANUAL_POWER*/
++
++#ifndef VCHI_CCP2TX_MANUAL_POWER
++
++/* Timeout (in milliseconds) for putting the CCP2TX interface into IDLE state. Set
++ * negative for no IDLE.
++ */
++# ifndef VCHI_CCP2TX_IDLE_TIMEOUT
++# define VCHI_CCP2TX_IDLE_TIMEOUT 5
++# endif
++
++/* Timeout (in milliseconds) for putting the CCP2TX interface into OFF state. Set
++ * negative for no OFF.
++ */
++# ifndef VCHI_CCP2TX_OFF_TIMEOUT
++# define VCHI_CCP2TX_OFF_TIMEOUT 1000
++# endif
++
++#endif /* VCHI_CCP2TX_MANUAL_POWER */
++
++#endif /* VCHI_CFG_H_ */
++
++/****************************** End of file **********************************/
+diff -Nur linux-4.1.3/drivers/misc/vc04_services/interface/vchi/vchi_cfg_internal.h linux-xbian-rpi/drivers/misc/vc04_services/interface/vchi/vchi_cfg_internal.h
+--- linux-4.1.3/drivers/misc/vc04_services/interface/vchi/vchi_cfg_internal.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/misc/vc04_services/interface/vchi/vchi_cfg_internal.h 2015-07-28 01:20:58.281739526 +0200
+@@ -0,0 +1,71 @@
++/**
++ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ * 1. Redistributions of source code must retain the above copyright
++ * notice, this list of conditions, and the following disclaimer,
++ * without modification.
++ * 2. Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * 3. The names of the above-listed copyright holders may not be used
++ * to endorse or promote products derived from this software without
++ * specific prior written permission.
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") version 2, as published by the Free
++ * Software Foundation.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#ifndef VCHI_CFG_INTERNAL_H_
++#define VCHI_CFG_INTERNAL_H_
++
++/****************************************************************************************
++ * Control optimisation attempts.
++ ***************************************************************************************/
++
++// Don't use lots of short-term locks - use great long ones, reducing the overall locks-per-second
++#define VCHI_COARSE_LOCKING
++
++// Avoid lock then unlock on exit from blocking queue operations (msg tx, bulk rx/tx)
++// (only relevant if VCHI_COARSE_LOCKING)
++#define VCHI_ELIDE_BLOCK_EXIT_LOCK
++
++// Avoid lock on non-blocking peek
++// (only relevant if VCHI_COARSE_LOCKING)
++#define VCHI_AVOID_PEEK_LOCK
++
++// Use one slot-handler thread per connection, rather than 1 thread dealing with all connections in rotation.
++#define VCHI_MULTIPLE_HANDLER_THREADS
++
++// Put free descriptors onto the head of the free queue, rather than the tail, so that we don't thrash
++// our way through the pool of descriptors.
++#define VCHI_PUSH_FREE_DESCRIPTORS_ONTO_HEAD
++
++// Don't issue a MSG_AVAILABLE callback for every single message. Possibly only safe if VCHI_COARSE_LOCKING.
++#define VCHI_FEWER_MSG_AVAILABLE_CALLBACKS
++
++// Don't use message descriptors for TX messages that don't need them
++#define VCHI_MINIMISE_TX_MSG_DESCRIPTORS
++
++// Nano-locks for multiqueue
++//#define VCHI_MQUEUE_NANOLOCKS
++
++// Lock-free(er) dequeuing
++//#define VCHI_RX_NANOLOCKS
++
++#endif /*VCHI_CFG_INTERNAL_H_*/
+diff -Nur linux-4.1.3/drivers/misc/vc04_services/interface/vchi/vchi_common.h linux-xbian-rpi/drivers/misc/vc04_services/interface/vchi/vchi_common.h
+--- linux-4.1.3/drivers/misc/vc04_services/interface/vchi/vchi_common.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/misc/vc04_services/interface/vchi/vchi_common.h 2015-07-28 01:20:58.285725306 +0200
+@@ -0,0 +1,175 @@
++/**
++ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ * 1. Redistributions of source code must retain the above copyright
++ * notice, this list of conditions, and the following disclaimer,
++ * without modification.
++ * 2. Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * 3. The names of the above-listed copyright holders may not be used
++ * to endorse or promote products derived from this software without
++ * specific prior written permission.
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") version 2, as published by the Free
++ * Software Foundation.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#ifndef VCHI_COMMON_H_
++#define VCHI_COMMON_H_
++
++
++//flags used when sending messages (must be bitmapped)
++typedef enum
++{
++ VCHI_FLAGS_NONE = 0x0,
++ VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE = 0x1, // waits for message to be received, or sent (NB. not the same as being seen on other side)
++ VCHI_FLAGS_CALLBACK_WHEN_OP_COMPLETE = 0x2, // run a callback when message sent
++ VCHI_FLAGS_BLOCK_UNTIL_QUEUED = 0x4, // return once the transfer is in a queue ready to go
++ VCHI_FLAGS_ALLOW_PARTIAL = 0x8,
++ VCHI_FLAGS_BLOCK_UNTIL_DATA_READ = 0x10,
++ VCHI_FLAGS_CALLBACK_WHEN_DATA_READ = 0x20,
++
++ VCHI_FLAGS_ALIGN_SLOT = 0x000080, // internal use only
++ VCHI_FLAGS_BULK_AUX_QUEUED = 0x010000, // internal use only
++ VCHI_FLAGS_BULK_AUX_COMPLETE = 0x020000, // internal use only
++ VCHI_FLAGS_BULK_DATA_QUEUED = 0x040000, // internal use only
++ VCHI_FLAGS_BULK_DATA_COMPLETE = 0x080000, // internal use only
++ VCHI_FLAGS_INTERNAL = 0xFF0000
++} VCHI_FLAGS_T;
++
++// constants for vchi_crc_control()
++typedef enum {
++ VCHI_CRC_NOTHING = -1,
++ VCHI_CRC_PER_SERVICE = 0,
++ VCHI_CRC_EVERYTHING = 1,
++} VCHI_CRC_CONTROL_T;
++
++//callback reasons when an event occurs on a service
++typedef enum
++{
++ VCHI_CALLBACK_REASON_MIN,
++
++ //This indicates that there is data available
++ //handle is the msg id that was transmitted with the data
++ // When a message is received and there was no FULL message available previously, send callback
++ // Tasks get kicked by the callback, reset their event and try and read from the fifo until it fails
++ VCHI_CALLBACK_MSG_AVAILABLE,
++ VCHI_CALLBACK_MSG_SENT,
++ VCHI_CALLBACK_MSG_SPACE_AVAILABLE, // XXX not yet implemented
++
++ // This indicates that a transfer from the other side has completed
++ VCHI_CALLBACK_BULK_RECEIVED,
++ //This indicates that data queued up to be sent has now gone
++ //handle is the msg id that was used when sending the data
++ VCHI_CALLBACK_BULK_SENT,
++ VCHI_CALLBACK_BULK_RX_SPACE_AVAILABLE, // XXX not yet implemented
++ VCHI_CALLBACK_BULK_TX_SPACE_AVAILABLE, // XXX not yet implemented
++
++ VCHI_CALLBACK_SERVICE_CLOSED,
++
++ // this side has sent XOFF to peer due to lack of data consumption by service
++ // (suggests the service may need to take some recovery action if it has
++ // been deliberately holding off consuming data)
++ VCHI_CALLBACK_SENT_XOFF,
++ VCHI_CALLBACK_SENT_XON,
++
++ // indicates that a bulk transfer has finished reading the source buffer
++ VCHI_CALLBACK_BULK_DATA_READ,
++
++ // power notification events (currently host side only)
++ VCHI_CALLBACK_PEER_OFF,
++ VCHI_CALLBACK_PEER_SUSPENDED,
++ VCHI_CALLBACK_PEER_ON,
++ VCHI_CALLBACK_PEER_RESUMED,
++ VCHI_CALLBACK_FORCED_POWER_OFF,
++
++#ifdef USE_VCHIQ_ARM
++ // some extra notifications provided by vchiq_arm
++ VCHI_CALLBACK_SERVICE_OPENED,
++ VCHI_CALLBACK_BULK_RECEIVE_ABORTED,
++ VCHI_CALLBACK_BULK_TRANSMIT_ABORTED,
++#endif
++
++ VCHI_CALLBACK_REASON_MAX
++} VCHI_CALLBACK_REASON_T;
++
++// service control options
++typedef enum
++{
++ VCHI_SERVICE_OPTION_MIN,
++
++ VCHI_SERVICE_OPTION_TRACE,
++ VCHI_SERVICE_OPTION_SYNCHRONOUS,
++
++ VCHI_SERVICE_OPTION_MAX
++} VCHI_SERVICE_OPTION_T;
++
++
++//Callback used by all services / bulk transfers
++typedef void (*VCHI_CALLBACK_T)( void *callback_param, //my service local param
++ VCHI_CALLBACK_REASON_T reason,
++ void *handle ); //for transmitting msg's only
++
++
++
++/*
++ * Define vector struct for scatter-gather (vector) operations
++ * Vectors can be nested - if a vector element has negative length, then
++ * the data pointer is treated as pointing to another vector array, with
++ * '-vec_len' elements. Thus to append a header onto an existing vector,
++ * you can do this:
++ *
++ * void foo(const VCHI_MSG_VECTOR_T *v, int n)
++ * {
++ * VCHI_MSG_VECTOR_T nv[2];
++ * nv[0].vec_base = my_header;
++ * nv[0].vec_len = sizeof my_header;
++ * nv[1].vec_base = v;
++ * nv[1].vec_len = -n;
++ * ...
++ *
++ */
++typedef struct vchi_msg_vector {
++ const void *vec_base;
++ int32_t vec_len;
++} VCHI_MSG_VECTOR_T;
++
++// Opaque type for a connection API
++typedef struct opaque_vchi_connection_api_t VCHI_CONNECTION_API_T;
++
++// Opaque type for a message driver
++typedef struct opaque_vchi_message_driver_t VCHI_MESSAGE_DRIVER_T;
++
++
++// Iterator structure for reading ahead through received message queue. Allocated by client,
++// initialised by vchi_msg_look_ahead. Fields are for internal VCHI use only.
++// Iterates over messages in queue at the instant of the call to vchi_msg_lookahead -
++// will not proceed to messages received since. Behaviour is undefined if an iterator
++// is used again after messages for that service are removed/dequeued by any
++// means other than vchi_msg_iter_... calls on the iterator itself.
++typedef struct {
++ struct opaque_vchi_service_t *service;
++ void *last;
++ void *next;
++ void *remove;
++} VCHI_MSG_ITER_T;
++
++
++#endif // VCHI_COMMON_H_
+diff -Nur linux-4.1.3/drivers/misc/vc04_services/interface/vchi/vchi.h linux-xbian-rpi/drivers/misc/vc04_services/interface/vchi/vchi.h
+--- linux-4.1.3/drivers/misc/vc04_services/interface/vchi/vchi.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/misc/vc04_services/interface/vchi/vchi.h 2015-07-28 01:20:58.281739526 +0200
+@@ -0,0 +1,378 @@
++/**
++ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ * 1. Redistributions of source code must retain the above copyright
++ * notice, this list of conditions, and the following disclaimer,
++ * without modification.
++ * 2. Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * 3. The names of the above-listed copyright holders may not be used
++ * to endorse or promote products derived from this software without
++ * specific prior written permission.
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") version 2, as published by the Free
++ * Software Foundation.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#ifndef VCHI_H_
++#define VCHI_H_
++
++#include "interface/vchi/vchi_cfg.h"
++#include "interface/vchi/vchi_common.h"
++#include "interface/vchi/connections/connection.h"
++#include "vchi_mh.h"
++
++
++/******************************************************************************
++ Global defs
++ *****************************************************************************/
++
++#define VCHI_BULK_ROUND_UP(x) ((((unsigned long)(x))+VCHI_BULK_ALIGN-1) & ~(VCHI_BULK_ALIGN-1))
++#define VCHI_BULK_ROUND_DOWN(x) (((unsigned long)(x)) & ~(VCHI_BULK_ALIGN-1))
++#define VCHI_BULK_ALIGN_NBYTES(x) (VCHI_BULK_ALIGNED(x) ? 0 : (VCHI_BULK_ALIGN - ((unsigned long)(x) & (VCHI_BULK_ALIGN-1))))
++
++#ifdef USE_VCHIQ_ARM
++#define VCHI_BULK_ALIGNED(x) 1
++#else
++#define VCHI_BULK_ALIGNED(x) (((unsigned long)(x) & (VCHI_BULK_ALIGN-1)) == 0)
++#endif
++
++struct vchi_version {
++ uint32_t version;
++ uint32_t version_min;
++};
++#define VCHI_VERSION(v_) { v_, v_ }
++#define VCHI_VERSION_EX(v_, m_) { v_, m_ }
++
++typedef enum
++{
++ VCHI_VEC_POINTER,
++ VCHI_VEC_HANDLE,
++ VCHI_VEC_LIST
++} VCHI_MSG_VECTOR_TYPE_T;
++
++typedef struct vchi_msg_vector_ex {
++
++ VCHI_MSG_VECTOR_TYPE_T type;
++ union
++ {
++ // a memory handle
++ struct
++ {
++ VCHI_MEM_HANDLE_T handle;
++ uint32_t offset;
++ int32_t vec_len;
++ } handle;
++
++ // an ordinary data pointer
++ struct
++ {
++ const void *vec_base;
++ int32_t vec_len;
++ } ptr;
++
++ // a nested vector list
++ struct
++ {
++ struct vchi_msg_vector_ex *vec;
++ uint32_t vec_len;
++ } list;
++ } u;
++} VCHI_MSG_VECTOR_EX_T;
++
++
++// Construct an entry in a msg vector for a pointer (p) of length (l)
++#define VCHI_VEC_POINTER(p,l) VCHI_VEC_POINTER, { { (VCHI_MEM_HANDLE_T)(p), (l) } }
++
++// Construct an entry in a msg vector for a message handle (h), starting at offset (o) of length (l)
++#define VCHI_VEC_HANDLE(h,o,l) VCHI_VEC_HANDLE, { { (h), (o), (l) } }
++
++// Macros to manipulate 'FOURCC' values
++#define MAKE_FOURCC(x) ((int32_t)( (x[0] << 24) | (x[1] << 16) | (x[2] << 8) | x[3] ))
++#define FOURCC_TO_CHAR(x) (x >> 24) & 0xFF,(x >> 16) & 0xFF,(x >> 8) & 0xFF, x & 0xFF
++
++
++// Opaque service information
++struct opaque_vchi_service_t;
++
++// Descriptor for a held message. Allocated by client, initialised by vchi_msg_hold,
++// vchi_msg_iter_hold or vchi_msg_iter_hold_next. Fields are for internal VCHI use only.
++typedef struct
++{
++ struct opaque_vchi_service_t *service;
++ void *message;
++} VCHI_HELD_MSG_T;
++
++
++
++// structure used to provide the information needed to open a server or a client
++typedef struct {
++ struct vchi_version version;
++ int32_t service_id;
++ VCHI_CONNECTION_T *connection;
++ uint32_t rx_fifo_size;
++ uint32_t tx_fifo_size;
++ VCHI_CALLBACK_T callback;
++ void *callback_param;
++ /* client intends to receive bulk transfers of
++ odd lengths or into unaligned buffers */
++ int32_t want_unaligned_bulk_rx;
++ /* client intends to transmit bulk transfers of
++ odd lengths or out of unaligned buffers */
++ int32_t want_unaligned_bulk_tx;
++ /* client wants to check CRCs on (bulk) xfers.
++ Only needs to be set at 1 end - will do both directions. */
++ int32_t want_crc;
++} SERVICE_CREATION_T;
++
++// Opaque handle for a VCHI instance
++typedef struct opaque_vchi_instance_handle_t *VCHI_INSTANCE_T;
++
++// Opaque handle for a server or client
++typedef struct opaque_vchi_service_handle_t *VCHI_SERVICE_HANDLE_T;
++
++// Service registration & startup
++typedef void (*VCHI_SERVICE_INIT)(VCHI_INSTANCE_T initialise_instance, VCHI_CONNECTION_T **connections, uint32_t num_connections);
++
++typedef struct service_info_tag {
++ const char * const vll_filename; /* VLL to load to start this service. This is an empty string if VLL is "static" */
++ VCHI_SERVICE_INIT init; /* Service initialisation function */
++ void *vll_handle; /* VLL handle; NULL when unloaded or a "static VLL" in build */
++} SERVICE_INFO_T;
++
++/******************************************************************************
++ Global funcs - implementation is specific to which side you are on (local / remote)
++ *****************************************************************************/
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++extern /*@observer@*/ VCHI_CONNECTION_T * vchi_create_connection( const VCHI_CONNECTION_API_T * function_table,
++ const VCHI_MESSAGE_DRIVER_T * low_level);
++
++
++// Routine used to initialise the vchi on both local + remote connections
++extern int32_t vchi_initialise( VCHI_INSTANCE_T *instance_handle );
++
++extern int32_t vchi_exit( void );
++
++extern int32_t vchi_connect( VCHI_CONNECTION_T **connections,
++ const uint32_t num_connections,
++ VCHI_INSTANCE_T instance_handle );
++
++//When this is called, ensure that all services have no data pending.
++//Bulk transfers can remain 'queued'
++extern int32_t vchi_disconnect( VCHI_INSTANCE_T instance_handle );
++
++// Global control over bulk CRC checking
++extern int32_t vchi_crc_control( VCHI_CONNECTION_T *connection,
++ VCHI_CRC_CONTROL_T control );
++
++// helper functions
++extern void * vchi_allocate_buffer(VCHI_SERVICE_HANDLE_T handle, uint32_t *length);
++extern void vchi_free_buffer(VCHI_SERVICE_HANDLE_T handle, void *address);
++extern uint32_t vchi_current_time(VCHI_INSTANCE_T instance_handle);
++
++
++/******************************************************************************
++ Global service API
++ *****************************************************************************/
++// Routine to create a named service
++extern int32_t vchi_service_create( VCHI_INSTANCE_T instance_handle,
++ SERVICE_CREATION_T *setup,
++ VCHI_SERVICE_HANDLE_T *handle );
++
++// Routine to destory a service
++extern int32_t vchi_service_destroy( const VCHI_SERVICE_HANDLE_T handle );
++
++// Routine to open a named service
++extern int32_t vchi_service_open( VCHI_INSTANCE_T instance_handle,
++ SERVICE_CREATION_T *setup,
++ VCHI_SERVICE_HANDLE_T *handle);
++
++extern int32_t vchi_get_peer_version( const VCHI_SERVICE_HANDLE_T handle,
++ short *peer_version );
++
++// Routine to close a named service
++extern int32_t vchi_service_close( const VCHI_SERVICE_HANDLE_T handle );
++
++// Routine to increment ref count on a named service
++extern int32_t vchi_service_use( const VCHI_SERVICE_HANDLE_T handle );
++
++// Routine to decrement ref count on a named service
++extern int32_t vchi_service_release( const VCHI_SERVICE_HANDLE_T handle );
++
++// Routine to set a control option for a named service
++extern int32_t vchi_service_set_option( const VCHI_SERVICE_HANDLE_T handle,
++ VCHI_SERVICE_OPTION_T option,
++ int value);
++
++// Routine to send a message across a service
++extern int32_t vchi_msg_queue( VCHI_SERVICE_HANDLE_T handle,
++ const void *data,
++ uint32_t data_size,
++ VCHI_FLAGS_T flags,
++ void *msg_handle );
++
++// scatter-gather (vector) and send message
++int32_t vchi_msg_queuev_ex( VCHI_SERVICE_HANDLE_T handle,
++ VCHI_MSG_VECTOR_EX_T *vector,
++ uint32_t count,
++ VCHI_FLAGS_T flags,
++ void *msg_handle );
++
++// legacy scatter-gather (vector) and send message, only handles pointers
++int32_t vchi_msg_queuev( VCHI_SERVICE_HANDLE_T handle,
++ VCHI_MSG_VECTOR_T *vector,
++ uint32_t count,
++ VCHI_FLAGS_T flags,
++ void *msg_handle );
++
++// Routine to receive a msg from a service
++// Dequeue is equivalent to hold, copy into client buffer, release
++extern int32_t vchi_msg_dequeue( VCHI_SERVICE_HANDLE_T handle,
++ void *data,
++ uint32_t max_data_size_to_read,
++ uint32_t *actual_msg_size,
++ VCHI_FLAGS_T flags );
++
++// Routine to look at a message in place.
++// The message is not dequeued, so a subsequent call to peek or dequeue
++// will return the same message.
++extern int32_t vchi_msg_peek( VCHI_SERVICE_HANDLE_T handle,
++ void **data,
++ uint32_t *msg_size,
++ VCHI_FLAGS_T flags );
++
++// Routine to remove a message after it has been read in place with peek
++// The first message on the queue is dequeued.
++extern int32_t vchi_msg_remove( VCHI_SERVICE_HANDLE_T handle );
++
++// Routine to look at a message in place.
++// The message is dequeued, so the caller is left holding it; the descriptor is
++// filled in and must be released when the user has finished with the message.
++extern int32_t vchi_msg_hold( VCHI_SERVICE_HANDLE_T handle,
++ void **data, // } may be NULL, as info can be
++ uint32_t *msg_size, // } obtained from HELD_MSG_T
++ VCHI_FLAGS_T flags,
++ VCHI_HELD_MSG_T *message_descriptor );
++
++// Initialise an iterator to look through messages in place
++extern int32_t vchi_msg_look_ahead( VCHI_SERVICE_HANDLE_T handle,
++ VCHI_MSG_ITER_T *iter,
++ VCHI_FLAGS_T flags );
++
++/******************************************************************************
++ Global service support API - operations on held messages and message iterators
++ *****************************************************************************/
++
++// Routine to get the address of a held message
++extern void *vchi_held_msg_ptr( const VCHI_HELD_MSG_T *message );
++
++// Routine to get the size of a held message
++extern int32_t vchi_held_msg_size( const VCHI_HELD_MSG_T *message );
++
++// Routine to get the transmit timestamp as written into the header by the peer
++extern uint32_t vchi_held_msg_tx_timestamp( const VCHI_HELD_MSG_T *message );
++
++// Routine to get the reception timestamp, written as we parsed the header
++extern uint32_t vchi_held_msg_rx_timestamp( const VCHI_HELD_MSG_T *message );
++
++// Routine to release a held message after it has been processed
++extern int32_t vchi_held_msg_release( VCHI_HELD_MSG_T *message );
++
++// Indicates whether the iterator has a next message.
++extern int32_t vchi_msg_iter_has_next( const VCHI_MSG_ITER_T *iter );
++
++// Return the pointer and length for the next message and advance the iterator.
++extern int32_t vchi_msg_iter_next( VCHI_MSG_ITER_T *iter,
++ void **data,
++ uint32_t *msg_size );
++
++// Remove the last message returned by vchi_msg_iter_next.
++// Can only be called once after each call to vchi_msg_iter_next.
++extern int32_t vchi_msg_iter_remove( VCHI_MSG_ITER_T *iter );
++
++// Hold the last message returned by vchi_msg_iter_next.
++// Can only be called once after each call to vchi_msg_iter_next.
++extern int32_t vchi_msg_iter_hold( VCHI_MSG_ITER_T *iter,
++ VCHI_HELD_MSG_T *message );
++
++// Return information for the next message, and hold it, advancing the iterator.
++extern int32_t vchi_msg_iter_hold_next( VCHI_MSG_ITER_T *iter,
++ void **data, // } may be NULL
++ uint32_t *msg_size, // }
++ VCHI_HELD_MSG_T *message );
++
++
++/******************************************************************************
++ Global bulk API
++ *****************************************************************************/
++
++// Routine to prepare interface for a transfer from the other side
++extern int32_t vchi_bulk_queue_receive( VCHI_SERVICE_HANDLE_T handle,
++ void *data_dst,
++ uint32_t data_size,
++ VCHI_FLAGS_T flags,
++ void *transfer_handle );
++
++
++// Prepare interface for a transfer from the other side into relocatable memory.
++int32_t vchi_bulk_queue_receive_reloc( const VCHI_SERVICE_HANDLE_T handle,
++ VCHI_MEM_HANDLE_T h_dst,
++ uint32_t offset,
++ uint32_t data_size,
++ const VCHI_FLAGS_T flags,
++ void * const bulk_handle );
++
++// Routine to queue up data ready for transfer to the other (once they have signalled they are ready)
++extern int32_t vchi_bulk_queue_transmit( VCHI_SERVICE_HANDLE_T handle,
++ const void *data_src,
++ uint32_t data_size,
++ VCHI_FLAGS_T flags,
++ void *transfer_handle );
++
++
++/******************************************************************************
++ Configuration plumbing
++ *****************************************************************************/
++
++// function prototypes for the different mid layers (the state info gives the different physical connections)
++extern const VCHI_CONNECTION_API_T *single_get_func_table( void );
++//extern const VCHI_CONNECTION_API_T *local_server_get_func_table( void );
++//extern const VCHI_CONNECTION_API_T *local_client_get_func_table( void );
++
++// declare all message drivers here
++const VCHI_MESSAGE_DRIVER_T *vchi_mphi_message_driver_func_table( void );
++
++#ifdef __cplusplus
++}
++#endif
++
++extern int32_t vchi_bulk_queue_transmit_reloc( VCHI_SERVICE_HANDLE_T handle,
++ VCHI_MEM_HANDLE_T h_src,
++ uint32_t offset,
++ uint32_t data_size,
++ VCHI_FLAGS_T flags,
++ void *transfer_handle );
++#endif /* VCHI_H_ */
++
++/****************************** End of file **********************************/
+diff -Nur linux-4.1.3/drivers/misc/vc04_services/interface/vchi/vchi_mh.h linux-xbian-rpi/drivers/misc/vc04_services/interface/vchi/vchi_mh.h
+--- linux-4.1.3/drivers/misc/vc04_services/interface/vchi/vchi_mh.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/misc/vc04_services/interface/vchi/vchi_mh.h 2015-07-28 01:20:58.285725306 +0200
+@@ -0,0 +1,42 @@
++/**
++ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ * 1. Redistributions of source code must retain the above copyright
++ * notice, this list of conditions, and the following disclaimer,
++ * without modification.
++ * 2. Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * 3. The names of the above-listed copyright holders may not be used
++ * to endorse or promote products derived from this software without
++ * specific prior written permission.
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") version 2, as published by the Free
++ * Software Foundation.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#ifndef VCHI_MH_H_
++#define VCHI_MH_H_
++
++#include <linux/types.h>
++
++typedef int32_t VCHI_MEM_HANDLE_T;
++#define VCHI_MEM_HANDLE_INVALID 0
++
++#endif
+diff -Nur linux-4.1.3/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c linux-xbian-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c
+--- linux-4.1.3/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c 2015-07-28 01:20:58.285725306 +0200
+@@ -0,0 +1,580 @@
++/**
++ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ * 1. Redistributions of source code must retain the above copyright
++ * notice, this list of conditions, and the following disclaimer,
++ * without modification.
++ * 2. Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * 3. The names of the above-listed copyright holders may not be used
++ * to endorse or promote products derived from this software without
++ * specific prior written permission.
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") version 2, as published by the Free
++ * Software Foundation.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#include <linux/kernel.h>
++#include <linux/types.h>
++#include <linux/errno.h>
++#include <linux/interrupt.h>
++#include <linux/pagemap.h>
++#include <linux/dma-mapping.h>
++#include <linux/version.h>
++#include <linux/io.h>
++#include <linux/platform_device.h>
++#include <linux/uaccess.h>
++#include <linux/of.h>
++#include <asm/pgtable.h>
++#include <soc/bcm2835/raspberrypi-firmware.h>
++
++#define TOTAL_SLOTS (VCHIQ_SLOT_ZERO_SLOTS + 2 * 32)
++
++#define VCHIQ_ARM_ADDRESS(x) ((void *)((char *)x + g_virt_to_bus_offset))
++
++#include "vchiq_arm.h"
++#include "vchiq_2835.h"
++#include "vchiq_connected.h"
++#include "vchiq_killable.h"
++
++#define MAX_FRAGMENTS (VCHIQ_NUM_CURRENT_BULKS * 2)
++
++#define BELL0 0x00
++#define BELL2 0x08
++
++typedef struct vchiq_2835_state_struct {
++ int inited;
++ VCHIQ_ARM_STATE_T arm_state;
++} VCHIQ_2835_ARM_STATE_T;
++
++static void __iomem *g_regs;
++static unsigned int g_cache_line_size = sizeof(CACHE_LINE_SIZE);
++static unsigned int g_fragments_size;
++static char *g_fragments_base;
++static char *g_free_fragments;
++static struct semaphore g_free_fragments_sema;
++static unsigned long g_virt_to_bus_offset;
++
++extern int vchiq_arm_log_level;
++
++static DEFINE_SEMAPHORE(g_free_fragments_mutex);
++
++static irqreturn_t
++vchiq_doorbell_irq(int irq, void *dev_id);
++
++static int
++create_pagelist(char __user *buf, size_t count, unsigned short type,
++ struct task_struct *task, PAGELIST_T ** ppagelist);
++
++static void
++free_pagelist(PAGELIST_T *pagelist, int actual);
++
++int vchiq_platform_init(struct platform_device *pdev, VCHIQ_STATE_T *state)
++{
++ struct device *dev = &pdev->dev;
++ struct rpi_firmware *fw = platform_get_drvdata(pdev);
++ VCHIQ_SLOT_ZERO_T *vchiq_slot_zero;
++ struct resource *res;
++ void *slot_mem;
++ dma_addr_t slot_phys;
++ u32 channelbase;
++ int slot_mem_size, frag_mem_size;
++ int err, irq, i;
++
++ g_virt_to_bus_offset = virt_to_dma(dev, (void *)0);
++
++ (void)of_property_read_u32(dev->of_node, "cache-line-size",
++ &g_cache_line_size);
++ g_fragments_size = 2 * g_cache_line_size;
++
++ /* Allocate space for the channels in coherent memory */
++ slot_mem_size = PAGE_ALIGN(TOTAL_SLOTS * VCHIQ_SLOT_SIZE);
++ frag_mem_size = PAGE_ALIGN(g_fragments_size * MAX_FRAGMENTS);
++
++ slot_mem = dmam_alloc_coherent(dev, slot_mem_size + frag_mem_size,
++ &slot_phys, GFP_KERNEL);
++ if (!slot_mem) {
++ dev_err(dev, "could not allocate DMA memory\n");
++ return -ENOMEM;
++ }
++
++ WARN_ON(((int)slot_mem & (PAGE_SIZE - 1)) != 0);
++
++ vchiq_slot_zero = vchiq_init_slots(slot_mem, slot_mem_size);
++ if (!vchiq_slot_zero)
++ return -EINVAL;
++
++ vchiq_slot_zero->platform_data[VCHIQ_PLATFORM_FRAGMENTS_OFFSET_IDX] =
++ (int)slot_phys + slot_mem_size;
++ vchiq_slot_zero->platform_data[VCHIQ_PLATFORM_FRAGMENTS_COUNT_IDX] =
++ MAX_FRAGMENTS;
++
++ g_fragments_base = (char *)slot_mem + slot_mem_size;
++ slot_mem_size += frag_mem_size;
++
++ g_free_fragments = g_fragments_base;
++ for (i = 0; i < (MAX_FRAGMENTS - 1); i++) {
++ *(char **)&g_fragments_base[i*g_fragments_size] =
++ &g_fragments_base[(i + 1)*g_fragments_size];
++ }
++ *(char **)&g_fragments_base[i * g_fragments_size] = NULL;
++ sema_init(&g_free_fragments_sema, MAX_FRAGMENTS);
++
++ if (vchiq_init_state(state, vchiq_slot_zero, 0) != VCHIQ_SUCCESS)
++ return -EINVAL;
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ g_regs = devm_ioremap_resource(&pdev->dev, res);
++ if (IS_ERR(g_regs))
++ return PTR_ERR(g_regs);
++
++ irq = platform_get_irq(pdev, 0);
++ if (irq <= 0) {
++ dev_err(dev, "failed to get IRQ\n");
++ return irq;
++ }
++
++ err = devm_request_irq(dev, irq, vchiq_doorbell_irq, IRQF_IRQPOLL,
++ "VCHIQ doorbell", state);
++ if (err) {
++ dev_err(dev, "failed to register irq=%d\n", irq);
++ return err;
++ }
++
++ /* Send the base address of the slots to VideoCore */
++ channelbase = slot_phys;
++ err = rpi_firmware_property(fw, RPI_FIRMWARE_VCHIQ_INIT,
++ &channelbase, sizeof(channelbase));
++ if (err || channelbase) {
++ dev_err(dev, "failed to set channelbase\n");
++ return err ? : -ENXIO;
++ }
++
++ vchiq_log_info(vchiq_arm_log_level,
++ "vchiq_init - done (slots %x, phys %pad)",
++ (unsigned int)vchiq_slot_zero, &slot_phys);
++
++ vchiq_call_connected_callbacks();
++
++ return 0;
++}
++
++VCHIQ_STATUS_T
++vchiq_platform_init_state(VCHIQ_STATE_T *state)
++{
++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS;
++ state->platform_state = kzalloc(sizeof(VCHIQ_2835_ARM_STATE_T), GFP_KERNEL);
++ ((VCHIQ_2835_ARM_STATE_T*)state->platform_state)->inited = 1;
++ status = vchiq_arm_init_state(state, &((VCHIQ_2835_ARM_STATE_T*)state->platform_state)->arm_state);
++ if(status != VCHIQ_SUCCESS)
++ {
++ ((VCHIQ_2835_ARM_STATE_T*)state->platform_state)->inited = 0;
++ }
++ return status;
++}
++
++VCHIQ_ARM_STATE_T*
++vchiq_platform_get_arm_state(VCHIQ_STATE_T *state)
++{
++ if(!((VCHIQ_2835_ARM_STATE_T*)state->platform_state)->inited)
++ {
++ BUG();
++ }
++ return &((VCHIQ_2835_ARM_STATE_T*)state->platform_state)->arm_state;
++}
++
++void
++remote_event_signal(REMOTE_EVENT_T *event)
++{
++ wmb();
++
++ event->fired = 1;
++
++ dsb(); /* data barrier operation */
++
++ if (event->armed)
++ writel(0, g_regs + BELL2); /* trigger vc interrupt */
++}
++
++int
++vchiq_copy_from_user(void *dst, const void *src, int size)
++{
++ if ((uint32_t)src < TASK_SIZE) {
++ return copy_from_user(dst, src, size);
++ } else {
++ memcpy(dst, src, size);
++ return 0;
++ }
++}
++
++VCHIQ_STATUS_T
++vchiq_prepare_bulk_data(VCHIQ_BULK_T *bulk, VCHI_MEM_HANDLE_T memhandle,
++ void *offset, int size, int dir)
++{
++ PAGELIST_T *pagelist;
++ int ret;
++
++ WARN_ON(memhandle != VCHI_MEM_HANDLE_INVALID);
++
++ ret = create_pagelist((char __user *)offset, size,
++ (dir == VCHIQ_BULK_RECEIVE)
++ ? PAGELIST_READ
++ : PAGELIST_WRITE,
++ current,
++ &pagelist);
++ if (ret != 0)
++ return VCHIQ_ERROR;
++
++ bulk->handle = memhandle;
++ bulk->data = VCHIQ_ARM_ADDRESS(pagelist);
++
++ /* Store the pagelist address in remote_data, which isn't used by the
++ slave. */
++ bulk->remote_data = pagelist;
++
++ return VCHIQ_SUCCESS;
++}
++
++void
++vchiq_complete_bulk(VCHIQ_BULK_T *bulk)
++{
++ if (bulk && bulk->remote_data && bulk->actual)
++ free_pagelist((PAGELIST_T *)bulk->remote_data, bulk->actual);
++}
++
++void
++vchiq_transfer_bulk(VCHIQ_BULK_T *bulk)
++{
++ /*
++ * This should only be called on the master (VideoCore) side, but
++ * provide an implementation to avoid the need for ifdefery.
++ */
++ BUG();
++}
++
++void
++vchiq_dump_platform_state(void *dump_context)
++{
++ char buf[80];
++ int len;
++ len = snprintf(buf, sizeof(buf),
++ " Platform: 2835 (VC master)");
++ vchiq_dump(dump_context, buf, len + 1);
++}
++
++VCHIQ_STATUS_T
++vchiq_platform_suspend(VCHIQ_STATE_T *state)
++{
++ return VCHIQ_ERROR;
++}
++
++VCHIQ_STATUS_T
++vchiq_platform_resume(VCHIQ_STATE_T *state)
++{
++ return VCHIQ_SUCCESS;
++}
++
++void
++vchiq_platform_paused(VCHIQ_STATE_T *state)
++{
++}
++
++void
++vchiq_platform_resumed(VCHIQ_STATE_T *state)
++{
++}
++
++int
++vchiq_platform_videocore_wanted(VCHIQ_STATE_T* state)
++{
++ return 1; // autosuspend not supported - videocore always wanted
++}
++
++int
++vchiq_platform_use_suspend_timer(void)
++{
++ return 0;
++}
++void
++vchiq_dump_platform_use_state(VCHIQ_STATE_T *state)
++{
++ vchiq_log_info(vchiq_arm_log_level, "Suspend timer not in use");
++}
++void
++vchiq_platform_handle_timeout(VCHIQ_STATE_T *state)
++{
++ (void)state;
++}
++/*
++ * Local functions
++ */
++
++static irqreturn_t
++vchiq_doorbell_irq(int irq, void *dev_id)
++{
++ VCHIQ_STATE_T *state = dev_id;
++ irqreturn_t ret = IRQ_NONE;
++ unsigned int status;
++
++ /* Read (and clear) the doorbell */
++ status = readl(g_regs + BELL0);
++
++ if (status & 0x4) { /* Was the doorbell rung? */
++ remote_event_pollall(state);
++ ret = IRQ_HANDLED;
++ }
++
++ return ret;
++}
++
++/* There is a potential problem with partial cache lines (pages?)
++** at the ends of the block when reading. If the CPU accessed anything in
++** the same line (page?) then it may have pulled old data into the cache,
++** obscuring the new data underneath. We can solve this by transferring the
++** partial cache lines separately, and allowing the ARM to copy into the
++** cached area.
++
++** N.B. This implementation plays slightly fast and loose with the Linux
++** driver programming rules, e.g. its use of dmac_map_area instead of
++** dma_map_single, but it isn't a multi-platform driver and it benefits
++** from increased speed as a result.
++*/
++
++static int
++create_pagelist(char __user *buf, size_t count, unsigned short type,
++ struct task_struct *task, PAGELIST_T ** ppagelist)
++{
++ PAGELIST_T *pagelist;
++ struct page **pages;
++ unsigned long *addrs;
++ unsigned int num_pages, offset, i;
++ char *addr, *base_addr, *next_addr;
++ int run, addridx, actual_pages;
++ unsigned long *need_release;
++
++ offset = (unsigned int)buf & (PAGE_SIZE - 1);
++ num_pages = (count + offset + PAGE_SIZE - 1) / PAGE_SIZE;
++
++ *ppagelist = NULL;
++
++ /* Allocate enough storage to hold the page pointers and the page
++ ** list
++ */
++ pagelist = kmalloc(sizeof(PAGELIST_T) +
++ (num_pages * sizeof(unsigned long)) +
++ sizeof(unsigned long) +
++ (num_pages * sizeof(pages[0])),
++ GFP_KERNEL);
++
++ vchiq_log_trace(vchiq_arm_log_level,
++ "create_pagelist - %x", (unsigned int)pagelist);
++ if (!pagelist)
++ return -ENOMEM;
++
++ addrs = pagelist->addrs;
++ need_release = (unsigned long *)(addrs + num_pages);
++ pages = (struct page **)(addrs + num_pages + 1);
++
++ if (is_vmalloc_addr(buf)) {
++ int dir = (type == PAGELIST_WRITE) ?
++ DMA_TO_DEVICE : DMA_FROM_DEVICE;
++ unsigned long length = count;
++ unsigned int off = offset;
++
++ for (actual_pages = 0; actual_pages < num_pages;
++ actual_pages++) {
++ struct page *pg = vmalloc_to_page(buf + (actual_pages *
++ PAGE_SIZE));
++ size_t bytes = PAGE_SIZE - off;
++
++ if (bytes > length)
++ bytes = length;
++ pages[actual_pages] = pg;
++ dmac_map_area(page_address(pg) + off, bytes, dir);
++ length -= bytes;
++ off = 0;
++ }
++ *need_release = 0; /* do not try and release vmalloc pages */
++ } else {
++ down_read(&task->mm->mmap_sem);
++ actual_pages = get_user_pages(task, task->mm,
++ (unsigned long)buf & ~(PAGE_SIZE - 1),
++ num_pages,
++ (type == PAGELIST_READ) /*Write */ ,
++ 0 /*Force */ ,
++ pages,
++ NULL /*vmas */);
++ up_read(&task->mm->mmap_sem);
++
++ if (actual_pages != num_pages) {
++ vchiq_log_info(vchiq_arm_log_level,
++ "create_pagelist - only %d/%d pages locked",
++ actual_pages,
++ num_pages);
++
++ /* This is probably due to the process being killed */
++ while (actual_pages > 0)
++ {
++ actual_pages--;
++ page_cache_release(pages[actual_pages]);
++ }
++ kfree(pagelist);
++ if (actual_pages == 0)
++ actual_pages = -ENOMEM;
++ return actual_pages;
++ }
++ *need_release = 1; /* release user pages */
++ }
++
++ pagelist->length = count;
++ pagelist->type = type;
++ pagelist->offset = offset;
++
++ /* Group the pages into runs of contiguous pages */
++
++ base_addr = VCHIQ_ARM_ADDRESS(page_address(pages[0]));
++ next_addr = base_addr + PAGE_SIZE;
++ addridx = 0;
++ run = 0;
++
++ for (i = 1; i < num_pages; i++) {
++ addr = VCHIQ_ARM_ADDRESS(page_address(pages[i]));
++ if ((addr == next_addr) && (run < (PAGE_SIZE - 1))) {
++ next_addr += PAGE_SIZE;
++ run++;
++ } else {
++ addrs[addridx] = (unsigned long)base_addr + run;
++ addridx++;
++ base_addr = addr;
++ next_addr = addr + PAGE_SIZE;
++ run = 0;
++ }
++ }
++
++ addrs[addridx] = (unsigned long)base_addr + run;
++ addridx++;
++
++ /* Partial cache lines (fragments) require special measures */
++ if ((type == PAGELIST_READ) &&
++ ((pagelist->offset & (g_cache_line_size - 1)) ||
++ ((pagelist->offset + pagelist->length) &
++ (g_cache_line_size - 1)))) {
++ char *fragments;
++
++ if (down_interruptible(&g_free_fragments_sema) != 0) {
++ kfree(pagelist);
++ return -EINTR;
++ }
++
++ WARN_ON(g_free_fragments == NULL);
++
++ down(&g_free_fragments_mutex);
++ fragments = g_free_fragments;
++ WARN_ON(fragments == NULL);
++ g_free_fragments = *(char **) g_free_fragments;
++ up(&g_free_fragments_mutex);
++ pagelist->type = PAGELIST_READ_WITH_FRAGMENTS +
++ (fragments - g_fragments_base) / g_fragments_size;
++ }
++
++ dmac_flush_range(pagelist, addrs + num_pages);
++
++ *ppagelist = pagelist;
++
++ return 0;
++}
++
++static void
++free_pagelist(PAGELIST_T *pagelist, int actual)
++{
++ unsigned long *need_release;
++ struct page **pages;
++ unsigned int num_pages, i;
++
++ vchiq_log_trace(vchiq_arm_log_level,
++ "free_pagelist - %x, %d", (unsigned int)pagelist, actual);
++
++ num_pages =
++ (pagelist->length + pagelist->offset + PAGE_SIZE - 1) /
++ PAGE_SIZE;
++
++ need_release = (unsigned long *)(pagelist->addrs + num_pages);
++ pages = (struct page **)(pagelist->addrs + num_pages + 1);
++
++ /* Deal with any partial cache lines (fragments) */
++ if (pagelist->type >= PAGELIST_READ_WITH_FRAGMENTS) {
++ char *fragments = g_fragments_base +
++ (pagelist->type - PAGELIST_READ_WITH_FRAGMENTS) *
++ g_fragments_size;
++ int head_bytes, tail_bytes;
++ head_bytes = (g_cache_line_size - pagelist->offset) &
++ (g_cache_line_size - 1);
++ tail_bytes = (pagelist->offset + actual) &
++ (g_cache_line_size - 1);
++
++ if ((actual >= 0) && (head_bytes != 0)) {
++ if (head_bytes > actual)
++ head_bytes = actual;
++
++ memcpy((char *)page_address(pages[0]) +
++ pagelist->offset,
++ fragments,
++ head_bytes);
++ }
++ if ((actual >= 0) && (head_bytes < actual) &&
++ (tail_bytes != 0)) {
++ memcpy((char *)page_address(pages[num_pages - 1]) +
++ ((pagelist->offset + actual) &
++ (PAGE_SIZE - 1) & ~(g_cache_line_size - 1)),
++ fragments + g_cache_line_size,
++ tail_bytes);
++ }
++
++ down(&g_free_fragments_mutex);
++ *(char **)fragments = g_free_fragments;
++ g_free_fragments = fragments;
++ up(&g_free_fragments_mutex);
++ up(&g_free_fragments_sema);
++ }
++
++ if (*need_release) {
++ unsigned int length = pagelist->length;
++ unsigned int offset = pagelist->offset;
++
++ for (i = 0; i < num_pages; i++) {
++ struct page *pg = pages[i];
++
++ if (pagelist->type != PAGELIST_WRITE) {
++ unsigned int bytes = PAGE_SIZE - offset;
++
++ if (bytes > length)
++ bytes = length;
++ dmac_unmap_area(page_address(pg) + offset,
++ bytes, DMA_FROM_DEVICE);
++ length -= bytes;
++ offset = 0;
++ set_page_dirty(pg);
++ }
++ page_cache_release(pg);
++ }
++ }
++
++ kfree(pagelist);
++}
+diff -Nur linux-4.1.3/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_2835.h linux-xbian-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_2835.h
+--- linux-4.1.3/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_2835.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_2835.h 2015-07-28 01:20:58.285725306 +0200
+@@ -0,0 +1,42 @@
++/**
++ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ * 1. Redistributions of source code must retain the above copyright
++ * notice, this list of conditions, and the following disclaimer,
++ * without modification.
++ * 2. Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * 3. The names of the above-listed copyright holders may not be used
++ * to endorse or promote products derived from this software without
++ * specific prior written permission.
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") version 2, as published by the Free
++ * Software Foundation.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#ifndef VCHIQ_2835_H
++#define VCHIQ_2835_H
++
++#include "vchiq_pagelist.h"
++
++#define VCHIQ_PLATFORM_FRAGMENTS_OFFSET_IDX 0
++#define VCHIQ_PLATFORM_FRAGMENTS_COUNT_IDX 1
++
++#endif /* VCHIQ_2835_H */
+diff -Nur linux-4.1.3/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.c linux-xbian-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.c
+--- linux-4.1.3/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.c 2015-07-28 01:20:58.285725306 +0200
+@@ -0,0 +1,2903 @@
++/**
++ * Copyright (c) 2014 Raspberry Pi (Trading) Ltd. All rights reserved.
++ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ * 1. Redistributions of source code must retain the above copyright
++ * notice, this list of conditions, and the following disclaimer,
++ * without modification.
++ * 2. Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * 3. The names of the above-listed copyright holders may not be used
++ * to endorse or promote products derived from this software without
++ * specific prior written permission.
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") version 2, as published by the Free
++ * Software Foundation.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/types.h>
++#include <linux/errno.h>
++#include <linux/cdev.h>
++#include <linux/fs.h>
++#include <linux/device.h>
++#include <linux/mm.h>
++#include <linux/highmem.h>
++#include <linux/pagemap.h>
++#include <linux/bug.h>
++#include <linux/semaphore.h>
++#include <linux/list.h>
++#include <linux/of.h>
++#include <linux/platform_device.h>
++#include <soc/bcm2835/raspberrypi-firmware.h>
++
++#include "vchiq_core.h"
++#include "vchiq_ioctl.h"
++#include "vchiq_arm.h"
++#include "vchiq_debugfs.h"
++#include "vchiq_killable.h"
++
++#define DEVICE_NAME "vchiq"
++
++/* Override the default prefix, which would be vchiq_arm (from the filename) */
++#undef MODULE_PARAM_PREFIX
++#define MODULE_PARAM_PREFIX DEVICE_NAME "."
++
++#define VCHIQ_MINOR 0
++
++/* Some per-instance constants */
++#define MAX_COMPLETIONS 16
++#define MAX_SERVICES 64
++#define MAX_ELEMENTS 8
++#define MSG_QUEUE_SIZE 64
++
++#define KEEPALIVE_VER 1
++#define KEEPALIVE_VER_MIN KEEPALIVE_VER
++
++/* Run time control of log level, based on KERN_XXX level. */
++int vchiq_arm_log_level = VCHIQ_LOG_DEFAULT;
++int vchiq_susp_log_level = VCHIQ_LOG_ERROR;
++
++#define SUSPEND_TIMER_TIMEOUT_MS 100
++#define SUSPEND_RETRY_TIMER_TIMEOUT_MS 1000
++
++#define VC_SUSPEND_NUM_OFFSET 3 /* number of values before idle which are -ve */
++static const char *const suspend_state_names[] = {
++ "VC_SUSPEND_FORCE_CANCELED",
++ "VC_SUSPEND_REJECTED",
++ "VC_SUSPEND_FAILED",
++ "VC_SUSPEND_IDLE",
++ "VC_SUSPEND_REQUESTED",
++ "VC_SUSPEND_IN_PROGRESS",
++ "VC_SUSPEND_SUSPENDED"
++};
++#define VC_RESUME_NUM_OFFSET 1 /* number of values before idle which are -ve */
++static const char *const resume_state_names[] = {
++ "VC_RESUME_FAILED",
++ "VC_RESUME_IDLE",
++ "VC_RESUME_REQUESTED",
++ "VC_RESUME_IN_PROGRESS",
++ "VC_RESUME_RESUMED"
++};
++/* The number of times we allow force suspend to timeout before actually
++** _forcing_ suspend. This is to cater for SW which fails to release vchiq
++** correctly - we don't want to prevent ARM suspend indefinitely in this case.
++*/
++#define FORCE_SUSPEND_FAIL_MAX 8
++
++/* The time in ms allowed for videocore to go idle when force suspend has been
++ * requested */
++#define FORCE_SUSPEND_TIMEOUT_MS 200
++
++
++static void suspend_timer_callback(unsigned long context);
++
++
++typedef struct user_service_struct {
++ VCHIQ_SERVICE_T *service;
++ void *userdata;
++ VCHIQ_INSTANCE_T instance;
++ char is_vchi;
++ char dequeue_pending;
++ char close_pending;
++ int message_available_pos;
++ int msg_insert;
++ int msg_remove;
++ struct semaphore insert_event;
++ struct semaphore remove_event;
++ struct semaphore close_event;
++ VCHIQ_HEADER_T * msg_queue[MSG_QUEUE_SIZE];
++} USER_SERVICE_T;
++
++struct bulk_waiter_node {
++ struct bulk_waiter bulk_waiter;
++ int pid;
++ struct list_head list;
++};
++
++struct vchiq_instance_struct {
++ VCHIQ_STATE_T *state;
++ VCHIQ_COMPLETION_DATA_T completions[MAX_COMPLETIONS];
++ int completion_insert;
++ int completion_remove;
++ struct semaphore insert_event;
++ struct semaphore remove_event;
++ struct mutex completion_mutex;
++
++ int connected;
++ int closing;
++ int pid;
++ int mark;
++ int use_close_delivered;
++ int trace;
++
++ struct list_head bulk_waiter_list;
++ struct mutex bulk_waiter_list_mutex;
++
++ VCHIQ_DEBUGFS_NODE_T debugfs_node;
++};
++
++typedef struct dump_context_struct {
++ char __user *buf;
++ size_t actual;
++ size_t space;
++ loff_t offset;
++} DUMP_CONTEXT_T;
++
++static struct cdev vchiq_cdev;
++static dev_t vchiq_devid;
++static VCHIQ_STATE_T g_state;
++static struct class *vchiq_class;
++static struct device *vchiq_dev;
++static DEFINE_SPINLOCK(msg_queue_spinlock);
++
++static const char *const ioctl_names[] = {
++ "CONNECT",
++ "SHUTDOWN",
++ "CREATE_SERVICE",
++ "REMOVE_SERVICE",
++ "QUEUE_MESSAGE",
++ "QUEUE_BULK_TRANSMIT",
++ "QUEUE_BULK_RECEIVE",
++ "AWAIT_COMPLETION",
++ "DEQUEUE_MESSAGE",
++ "GET_CLIENT_ID",
++ "GET_CONFIG",
++ "CLOSE_SERVICE",
++ "USE_SERVICE",
++ "RELEASE_SERVICE",
++ "SET_SERVICE_OPTION",
++ "DUMP_PHYS_MEM",
++ "LIB_VERSION",
++ "CLOSE_DELIVERED"
++};
++
++vchiq_static_assert((sizeof(ioctl_names)/sizeof(ioctl_names[0])) ==
++ (VCHIQ_IOC_MAX + 1));
++
++static void
++dump_phys_mem(void *virt_addr, uint32_t num_bytes);
++
++/****************************************************************************
++*
++* add_completion
++*
++***************************************************************************/
++
++static VCHIQ_STATUS_T
++add_completion(VCHIQ_INSTANCE_T instance, VCHIQ_REASON_T reason,
++ VCHIQ_HEADER_T *header, USER_SERVICE_T *user_service,
++ void *bulk_userdata)
++{
++ VCHIQ_COMPLETION_DATA_T *completion;
++ DEBUG_INITIALISE(g_state.local)
++
++ while (instance->completion_insert ==
++ (instance->completion_remove + MAX_COMPLETIONS)) {
++ /* Out of space - wait for the client */
++ DEBUG_TRACE(SERVICE_CALLBACK_LINE);
++ vchiq_log_trace(vchiq_arm_log_level,
++ "add_completion - completion queue full");
++ DEBUG_COUNT(COMPLETION_QUEUE_FULL_COUNT);
++ if (down_interruptible(&instance->remove_event) != 0) {
++ vchiq_log_info(vchiq_arm_log_level,
++ "service_callback interrupted");
++ return VCHIQ_RETRY;
++ } else if (instance->closing) {
++ vchiq_log_info(vchiq_arm_log_level,
++ "service_callback closing");
++ return VCHIQ_ERROR;
++ }
++ DEBUG_TRACE(SERVICE_CALLBACK_LINE);
++ }
++
++ completion =
++ &instance->completions[instance->completion_insert &
++ (MAX_COMPLETIONS - 1)];
++
++ completion->header = header;
++ completion->reason = reason;
++ /* N.B. service_userdata is updated while processing AWAIT_COMPLETION */
++ completion->service_userdata = user_service->service;
++ completion->bulk_userdata = bulk_userdata;
++
++ if (reason == VCHIQ_SERVICE_CLOSED) {
++ /* Take an extra reference, to be held until
++ this CLOSED notification is delivered. */
++ lock_service(user_service->service);
++ if (instance->use_close_delivered)
++ user_service->close_pending = 1;
++ }
++
++ /* A write barrier is needed here to ensure that the entire completion
++ record is written out before the insert point. */
++ wmb();
++
++ if (reason == VCHIQ_MESSAGE_AVAILABLE)
++ user_service->message_available_pos =
++ instance->completion_insert;
++ instance->completion_insert++;
++
++ up(&instance->insert_event);
++
++ return VCHIQ_SUCCESS;
++}
++
++/****************************************************************************
++*
++* service_callback
++*
++***************************************************************************/
++
++static VCHIQ_STATUS_T
++service_callback(VCHIQ_REASON_T reason, VCHIQ_HEADER_T *header,
++ VCHIQ_SERVICE_HANDLE_T handle, void *bulk_userdata)
++{
++ /* How do we ensure the callback goes to the right client?
++ ** The service_user data points to a USER_SERVICE_T record containing
++ ** the original callback and the user state structure, which contains a
++ ** circular buffer for completion records.
++ */
++ USER_SERVICE_T *user_service;
++ VCHIQ_SERVICE_T *service;
++ VCHIQ_INSTANCE_T instance;
++ DEBUG_INITIALISE(g_state.local)
++
++ DEBUG_TRACE(SERVICE_CALLBACK_LINE);
++
++ service = handle_to_service(handle);
++ BUG_ON(!service);
++ user_service = (USER_SERVICE_T *)service->base.userdata;
++ instance = user_service->instance;
++
++ if (!instance || instance->closing)
++ return VCHIQ_SUCCESS;
++
++ vchiq_log_trace(vchiq_arm_log_level,
++ "service_callback - service %lx(%d,%p), reason %d, header %lx, "
++ "instance %lx, bulk_userdata %lx",
++ (unsigned long)user_service,
++ service->localport, user_service->userdata,
++ reason, (unsigned long)header,
++ (unsigned long)instance, (unsigned long)bulk_userdata);
++
++ if (header && user_service->is_vchi) {
++ spin_lock(&msg_queue_spinlock);
++ while (user_service->msg_insert ==
++ (user_service->msg_remove + MSG_QUEUE_SIZE)) {
++ spin_unlock(&msg_queue_spinlock);
++ DEBUG_TRACE(SERVICE_CALLBACK_LINE);
++ DEBUG_COUNT(MSG_QUEUE_FULL_COUNT);
++ vchiq_log_trace(vchiq_arm_log_level,
++ "service_callback - msg queue full");
++ /* If there is no MESSAGE_AVAILABLE in the completion
++ ** queue, add one
++ */
++ if ((user_service->message_available_pos -
++ instance->completion_remove) < 0) {
++ VCHIQ_STATUS_T status;
++ vchiq_log_info(vchiq_arm_log_level,
++ "Inserting extra MESSAGE_AVAILABLE");
++ DEBUG_TRACE(SERVICE_CALLBACK_LINE);
++ status = add_completion(instance, reason,
++ NULL, user_service, bulk_userdata);
++ if (status != VCHIQ_SUCCESS) {
++ DEBUG_TRACE(SERVICE_CALLBACK_LINE);
++ return status;
++ }
++ }
++
++ DEBUG_TRACE(SERVICE_CALLBACK_LINE);
++ if (down_interruptible(&user_service->remove_event)
++ != 0) {
++ vchiq_log_info(vchiq_arm_log_level,
++ "service_callback interrupted");
++ DEBUG_TRACE(SERVICE_CALLBACK_LINE);
++ return VCHIQ_RETRY;
++ } else if (instance->closing) {
++ vchiq_log_info(vchiq_arm_log_level,
++ "service_callback closing");
++ DEBUG_TRACE(SERVICE_CALLBACK_LINE);
++ return VCHIQ_ERROR;
++ }
++ DEBUG_TRACE(SERVICE_CALLBACK_LINE);
++ spin_lock(&msg_queue_spinlock);
++ }
++
++ user_service->msg_queue[user_service->msg_insert &
++ (MSG_QUEUE_SIZE - 1)] = header;
++ user_service->msg_insert++;
++ spin_unlock(&msg_queue_spinlock);
++
++ up(&user_service->insert_event);
++
++ /* If there is a thread waiting in DEQUEUE_MESSAGE, or if
++ ** there is a MESSAGE_AVAILABLE in the completion queue then
++ ** bypass the completion queue.
++ */
++ if (((user_service->message_available_pos -
++ instance->completion_remove) >= 0) ||
++ user_service->dequeue_pending) {
++ DEBUG_TRACE(SERVICE_CALLBACK_LINE);
++ user_service->dequeue_pending = 0;
++ return VCHIQ_SUCCESS;
++ }
++
++ header = NULL;
++ }
++ DEBUG_TRACE(SERVICE_CALLBACK_LINE);
++
++ return add_completion(instance, reason, header, user_service,
++ bulk_userdata);
++}
++
++/****************************************************************************
++*
++* user_service_free
++*
++***************************************************************************/
++static void
++user_service_free(void *userdata)
++{
++ kfree(userdata);
++}
++
++/****************************************************************************
++*
++* close_delivered
++*
++***************************************************************************/
++static void close_delivered(USER_SERVICE_T *user_service)
++{
++ vchiq_log_info(vchiq_arm_log_level,
++ "close_delivered(handle=%x)",
++ user_service->service->handle);
++
++ if (user_service->close_pending) {
++ /* Allow the underlying service to be culled */
++ unlock_service(user_service->service);
++
++ /* Wake the user-thread blocked in close_ or remove_service */
++ up(&user_service->close_event);
++
++ user_service->close_pending = 0;
++ }
++}
++
++/****************************************************************************
++*
++* vchiq_ioctl
++*
++***************************************************************************/
++static long
++vchiq_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
++{
++ VCHIQ_INSTANCE_T instance = file->private_data;
++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS;
++ VCHIQ_SERVICE_T *service = NULL;
++ long ret = 0;
++ int i, rc;
++ DEBUG_INITIALISE(g_state.local)
++
++ vchiq_log_trace(vchiq_arm_log_level,
++ "vchiq_ioctl - instance %x, cmd %s, arg %lx",
++ (unsigned int)instance,
++ ((_IOC_TYPE(cmd) == VCHIQ_IOC_MAGIC) &&
++ (_IOC_NR(cmd) <= VCHIQ_IOC_MAX)) ?
++ ioctl_names[_IOC_NR(cmd)] : "<invalid>", arg);
++
++ switch (cmd) {
++ case VCHIQ_IOC_SHUTDOWN:
++ if (!instance->connected)
++ break;
++
++ /* Remove all services */
++ i = 0;
++ while ((service = next_service_by_instance(instance->state,
++ instance, &i)) != NULL) {
++ status = vchiq_remove_service(service->handle);
++ unlock_service(service);
++ if (status != VCHIQ_SUCCESS)
++ break;
++ }
++ service = NULL;
++
++ if (status == VCHIQ_SUCCESS) {
++ /* Wake the completion thread and ask it to exit */
++ instance->closing = 1;
++ up(&instance->insert_event);
++ }
++
++ break;
++
++ case VCHIQ_IOC_CONNECT:
++ if (instance->connected) {
++ ret = -EINVAL;
++ break;
++ }
++ rc = mutex_lock_interruptible(&instance->state->mutex);
++ if (rc != 0) {
++ vchiq_log_error(vchiq_arm_log_level,
++ "vchiq: connect: could not lock mutex for "
++ "state %d: %d",
++ instance->state->id, rc);
++ ret = -EINTR;
++ break;
++ }
++ status = vchiq_connect_internal(instance->state, instance);
++ mutex_unlock(&instance->state->mutex);
++
++ if (status == VCHIQ_SUCCESS)
++ instance->connected = 1;
++ else
++ vchiq_log_error(vchiq_arm_log_level,
++ "vchiq: could not connect: %d", status);
++ break;
++
++ case VCHIQ_IOC_CREATE_SERVICE: {
++ VCHIQ_CREATE_SERVICE_T args;
++ USER_SERVICE_T *user_service = NULL;
++ void *userdata;
++ int srvstate;
++
++ if (copy_from_user
++ (&args, (const void __user *)arg,
++ sizeof(args)) != 0) {
++ ret = -EFAULT;
++ break;
++ }
++
++ user_service = kmalloc(sizeof(USER_SERVICE_T), GFP_KERNEL);
++ if (!user_service) {
++ ret = -ENOMEM;
++ break;
++ }
++
++ if (args.is_open) {
++ if (!instance->connected) {
++ ret = -ENOTCONN;
++ kfree(user_service);
++ break;
++ }
++ srvstate = VCHIQ_SRVSTATE_OPENING;
++ } else {
++ srvstate =
++ instance->connected ?
++ VCHIQ_SRVSTATE_LISTENING :
++ VCHIQ_SRVSTATE_HIDDEN;
++ }
++
++ userdata = args.params.userdata;
++ args.params.callback = service_callback;
++ args.params.userdata = user_service;
++ service = vchiq_add_service_internal(
++ instance->state,
++ &args.params, srvstate,
++ instance, user_service_free);
++
++ if (service != NULL) {
++ user_service->service = service;
++ user_service->userdata = userdata;
++ user_service->instance = instance;
++ user_service->is_vchi = (args.is_vchi != 0);
++ user_service->dequeue_pending = 0;
++ user_service->close_pending = 0;
++ user_service->message_available_pos =
++ instance->completion_remove - 1;
++ user_service->msg_insert = 0;
++ user_service->msg_remove = 0;
++ sema_init(&user_service->insert_event, 0);
++ sema_init(&user_service->remove_event, 0);
++ sema_init(&user_service->close_event, 0);
++
++ if (args.is_open) {
++ status = vchiq_open_service_internal
++ (service, instance->pid);
++ if (status != VCHIQ_SUCCESS) {
++ vchiq_remove_service(service->handle);
++ service = NULL;
++ ret = (status == VCHIQ_RETRY) ?
++ -EINTR : -EIO;
++ break;
++ }
++ }
++
++ if (copy_to_user((void __user *)
++ &(((VCHIQ_CREATE_SERVICE_T __user *)
++ arg)->handle),
++ (const void *)&service->handle,
++ sizeof(service->handle)) != 0) {
++ ret = -EFAULT;
++ vchiq_remove_service(service->handle);
++ }
++
++ service = NULL;
++ } else {
++ ret = -EEXIST;
++ kfree(user_service);
++ }
++ } break;
++
++ case VCHIQ_IOC_CLOSE_SERVICE: {
++ VCHIQ_SERVICE_HANDLE_T handle = (VCHIQ_SERVICE_HANDLE_T)arg;
++
++ service = find_service_for_instance(instance, handle);
++ if (service != NULL) {
++ USER_SERVICE_T *user_service =
++ (USER_SERVICE_T *)service->base.userdata;
++ /* close_pending is false on first entry, and when the
++ wait in vchiq_close_service has been interrupted. */
++ if (!user_service->close_pending) {
++ status = vchiq_close_service(service->handle);
++ if (status != VCHIQ_SUCCESS)
++ break;
++ }
++
++ /* close_pending is true once the underlying service
++ has been closed until the client library calls the
++ CLOSE_DELIVERED ioctl, signalling close_event. */
++ if (user_service->close_pending &&
++ down_interruptible(&user_service->close_event))
++ status = VCHIQ_RETRY;
++ }
++ else
++ ret = -EINVAL;
++ } break;
++
++ case VCHIQ_IOC_REMOVE_SERVICE: {
++ VCHIQ_SERVICE_HANDLE_T handle = (VCHIQ_SERVICE_HANDLE_T)arg;
++
++ service = find_service_for_instance(instance, handle);
++ if (service != NULL) {
++ USER_SERVICE_T *user_service =
++ (USER_SERVICE_T *)service->base.userdata;
++ /* close_pending is false on first entry, and when the
++ wait in vchiq_close_service has been interrupted. */
++ if (!user_service->close_pending) {
++ status = vchiq_remove_service(service->handle);
++ if (status != VCHIQ_SUCCESS)
++ break;
++ }
++
++ /* close_pending is true once the underlying service
++ has been closed until the client library calls the
++ CLOSE_DELIVERED ioctl, signalling close_event. */
++ if (user_service->close_pending &&
++ down_interruptible(&user_service->close_event))
++ status = VCHIQ_RETRY;
++ }
++ else
++ ret = -EINVAL;
++ } break;
++
++ case VCHIQ_IOC_USE_SERVICE:
++ case VCHIQ_IOC_RELEASE_SERVICE: {
++ VCHIQ_SERVICE_HANDLE_T handle = (VCHIQ_SERVICE_HANDLE_T)arg;
++
++ service = find_service_for_instance(instance, handle);
++ if (service != NULL) {
++ status = (cmd == VCHIQ_IOC_USE_SERVICE) ?
++ vchiq_use_service_internal(service) :
++ vchiq_release_service_internal(service);
++ if (status != VCHIQ_SUCCESS) {
++ vchiq_log_error(vchiq_susp_log_level,
++ "%s: cmd %s returned error %d for "
++ "service %c%c%c%c:%03d",
++ __func__,
++ (cmd == VCHIQ_IOC_USE_SERVICE) ?
++ "VCHIQ_IOC_USE_SERVICE" :
++ "VCHIQ_IOC_RELEASE_SERVICE",
++ status,
++ VCHIQ_FOURCC_AS_4CHARS(
++ service->base.fourcc),
++ service->client_id);
++ ret = -EINVAL;
++ }
++ } else
++ ret = -EINVAL;
++ } break;
++
++ case VCHIQ_IOC_QUEUE_MESSAGE: {
++ VCHIQ_QUEUE_MESSAGE_T args;
++ if (copy_from_user
++ (&args, (const void __user *)arg,
++ sizeof(args)) != 0) {
++ ret = -EFAULT;
++ break;
++ }
++
++ service = find_service_for_instance(instance, args.handle);
++
++ if ((service != NULL) && (args.count <= MAX_ELEMENTS)) {
++ /* Copy elements into kernel space */
++ VCHIQ_ELEMENT_T elements[MAX_ELEMENTS];
++ if (copy_from_user(elements, args.elements,
++ args.count * sizeof(VCHIQ_ELEMENT_T)) == 0)
++ status = vchiq_queue_message
++ (args.handle,
++ elements, args.count);
++ else
++ ret = -EFAULT;
++ } else {
++ ret = -EINVAL;
++ }
++ } break;
++
++ case VCHIQ_IOC_QUEUE_BULK_TRANSMIT:
++ case VCHIQ_IOC_QUEUE_BULK_RECEIVE: {
++ VCHIQ_QUEUE_BULK_TRANSFER_T args;
++ struct bulk_waiter_node *waiter = NULL;
++ VCHIQ_BULK_DIR_T dir =
++ (cmd == VCHIQ_IOC_QUEUE_BULK_TRANSMIT) ?
++ VCHIQ_BULK_TRANSMIT : VCHIQ_BULK_RECEIVE;
++
++ if (copy_from_user
++ (&args, (const void __user *)arg,
++ sizeof(args)) != 0) {
++ ret = -EFAULT;
++ break;
++ }
++
++ service = find_service_for_instance(instance, args.handle);
++ if (!service) {
++ ret = -EINVAL;
++ break;
++ }
++
++ if (args.mode == VCHIQ_BULK_MODE_BLOCKING) {
++ waiter = kzalloc(sizeof(struct bulk_waiter_node),
++ GFP_KERNEL);
++ if (!waiter) {
++ ret = -ENOMEM;
++ break;
++ }
++ args.userdata = &waiter->bulk_waiter;
++ } else if (args.mode == VCHIQ_BULK_MODE_WAITING) {
++ struct list_head *pos;
++ mutex_lock(&instance->bulk_waiter_list_mutex);
++ list_for_each(pos, &instance->bulk_waiter_list) {
++ if (list_entry(pos, struct bulk_waiter_node,
++ list)->pid == current->pid) {
++ waiter = list_entry(pos,
++ struct bulk_waiter_node,
++ list);
++ list_del(pos);
++ break;
++ }
++
++ }
++ mutex_unlock(&instance->bulk_waiter_list_mutex);
++ if (!waiter) {
++ vchiq_log_error(vchiq_arm_log_level,
++ "no bulk_waiter found for pid %d",
++ current->pid);
++ ret = -ESRCH;
++ break;
++ }
++ vchiq_log_info(vchiq_arm_log_level,
++ "found bulk_waiter %x for pid %d",
++ (unsigned int)waiter, current->pid);
++ args.userdata = &waiter->bulk_waiter;
++ }
++ status = vchiq_bulk_transfer
++ (args.handle,
++ VCHI_MEM_HANDLE_INVALID,
++ args.data, args.size,
++ args.userdata, args.mode,
++ dir);
++ if (!waiter)
++ break;
++ if ((status != VCHIQ_RETRY) || fatal_signal_pending(current) ||
++ !waiter->bulk_waiter.bulk) {
++ if (waiter->bulk_waiter.bulk) {
++ /* Cancel the signal when the transfer
++ ** completes. */
++ spin_lock(&bulk_waiter_spinlock);
++ waiter->bulk_waiter.bulk->userdata = NULL;
++ spin_unlock(&bulk_waiter_spinlock);
++ }
++ kfree(waiter);
++ } else {
++ const VCHIQ_BULK_MODE_T mode_waiting =
++ VCHIQ_BULK_MODE_WAITING;
++ waiter->pid = current->pid;
++ mutex_lock(&instance->bulk_waiter_list_mutex);
++ list_add(&waiter->list, &instance->bulk_waiter_list);
++ mutex_unlock(&instance->bulk_waiter_list_mutex);
++ vchiq_log_info(vchiq_arm_log_level,
++ "saved bulk_waiter %x for pid %d",
++ (unsigned int)waiter, current->pid);
++
++ if (copy_to_user((void __user *)
++ &(((VCHIQ_QUEUE_BULK_TRANSFER_T __user *)
++ arg)->mode),
++ (const void *)&mode_waiting,
++ sizeof(mode_waiting)) != 0)
++ ret = -EFAULT;
++ }
++ } break;
++
++ case VCHIQ_IOC_AWAIT_COMPLETION: {
++ VCHIQ_AWAIT_COMPLETION_T args;
++
++ DEBUG_TRACE(AWAIT_COMPLETION_LINE);
++ if (!instance->connected) {
++ ret = -ENOTCONN;
++ break;
++ }
++
++ if (copy_from_user(&args, (const void __user *)arg,
++ sizeof(args)) != 0) {
++ ret = -EFAULT;
++ break;
++ }
++
++ mutex_lock(&instance->completion_mutex);
++
++ DEBUG_TRACE(AWAIT_COMPLETION_LINE);
++ while ((instance->completion_remove ==
++ instance->completion_insert)
++ && !instance->closing) {
++ int rc;
++ DEBUG_TRACE(AWAIT_COMPLETION_LINE);
++ mutex_unlock(&instance->completion_mutex);
++ rc = down_interruptible(&instance->insert_event);
++ mutex_lock(&instance->completion_mutex);
++ if (rc != 0) {
++ DEBUG_TRACE(AWAIT_COMPLETION_LINE);
++ vchiq_log_info(vchiq_arm_log_level,
++ "AWAIT_COMPLETION interrupted");
++ ret = -EINTR;
++ break;
++ }
++ }
++ DEBUG_TRACE(AWAIT_COMPLETION_LINE);
++
++ /* A read memory barrier is needed to stop prefetch of a stale
++ ** completion record
++ */
++ rmb();
++
++ if (ret == 0) {
++ int msgbufcount = args.msgbufcount;
++ for (ret = 0; ret < args.count; ret++) {
++ VCHIQ_COMPLETION_DATA_T *completion;
++ VCHIQ_SERVICE_T *service;
++ USER_SERVICE_T *user_service;
++ VCHIQ_HEADER_T *header;
++ if (instance->completion_remove ==
++ instance->completion_insert)
++ break;
++ completion = &instance->completions[
++ instance->completion_remove &
++ (MAX_COMPLETIONS - 1)];
++
++ service = completion->service_userdata;
++ user_service = service->base.userdata;
++ completion->service_userdata =
++ user_service->userdata;
++
++ header = completion->header;
++ if (header) {
++ void __user *msgbuf;
++ int msglen;
++
++ msglen = header->size +
++ sizeof(VCHIQ_HEADER_T);
++ /* This must be a VCHIQ-style service */
++ if (args.msgbufsize < msglen) {
++ vchiq_log_error(
++ vchiq_arm_log_level,
++ "header %x: msgbufsize"
++ " %x < msglen %x",
++ (unsigned int)header,
++ args.msgbufsize,
++ msglen);
++ WARN(1, "invalid message "
++ "size\n");
++ if (ret == 0)
++ ret = -EMSGSIZE;
++ break;
++ }
++ if (msgbufcount <= 0)
++ /* Stall here for lack of a
++ ** buffer for the message. */
++ break;
++ /* Get the pointer from user space */
++ msgbufcount--;
++ if (copy_from_user(&msgbuf,
++ (const void __user *)
++ &args.msgbufs[msgbufcount],
++ sizeof(msgbuf)) != 0) {
++ if (ret == 0)
++ ret = -EFAULT;
++ break;
++ }
++
++ /* Copy the message to user space */
++ if (copy_to_user(msgbuf, header,
++ msglen) != 0) {
++ if (ret == 0)
++ ret = -EFAULT;
++ break;
++ }
++
++ /* Now it has been copied, the message
++ ** can be released. */
++ vchiq_release_message(service->handle,
++ header);
++
++ /* The completion must point to the
++ ** msgbuf. */
++ completion->header = msgbuf;
++ }
++
++ if ((completion->reason ==
++ VCHIQ_SERVICE_CLOSED) &&
++ !instance->use_close_delivered)
++ unlock_service(service);
++
++ if (copy_to_user((void __user *)(
++ (size_t)args.buf +
++ ret * sizeof(VCHIQ_COMPLETION_DATA_T)),
++ completion,
++ sizeof(VCHIQ_COMPLETION_DATA_T)) != 0) {
++ if (ret == 0)
++ ret = -EFAULT;
++ break;
++ }
++
++ instance->completion_remove++;
++ }
++
++ if (msgbufcount != args.msgbufcount) {
++ if (copy_to_user((void __user *)
++ &((VCHIQ_AWAIT_COMPLETION_T *)arg)->
++ msgbufcount,
++ &msgbufcount,
++ sizeof(msgbufcount)) != 0) {
++ ret = -EFAULT;
++ }
++ }
++ }
++
++ if (ret != 0)
++ up(&instance->remove_event);
++ mutex_unlock(&instance->completion_mutex);
++ DEBUG_TRACE(AWAIT_COMPLETION_LINE);
++ } break;
++
++ case VCHIQ_IOC_DEQUEUE_MESSAGE: {
++ VCHIQ_DEQUEUE_MESSAGE_T args;
++ USER_SERVICE_T *user_service;
++ VCHIQ_HEADER_T *header;
++
++ DEBUG_TRACE(DEQUEUE_MESSAGE_LINE);
++ if (copy_from_user
++ (&args, (const void __user *)arg,
++ sizeof(args)) != 0) {
++ ret = -EFAULT;
++ break;
++ }
++ service = find_service_for_instance(instance, args.handle);
++ if (!service) {
++ ret = -EINVAL;
++ break;
++ }
++ user_service = (USER_SERVICE_T *)service->base.userdata;
++ if (user_service->is_vchi == 0) {
++ ret = -EINVAL;
++ break;
++ }
++
++ spin_lock(&msg_queue_spinlock);
++ if (user_service->msg_remove == user_service->msg_insert) {
++ if (!args.blocking) {
++ spin_unlock(&msg_queue_spinlock);
++ DEBUG_TRACE(DEQUEUE_MESSAGE_LINE);
++ ret = -EWOULDBLOCK;
++ break;
++ }
++ user_service->dequeue_pending = 1;
++ do {
++ spin_unlock(&msg_queue_spinlock);
++ DEBUG_TRACE(DEQUEUE_MESSAGE_LINE);
++ if (down_interruptible(
++ &user_service->insert_event) != 0) {
++ vchiq_log_info(vchiq_arm_log_level,
++ "DEQUEUE_MESSAGE interrupted");
++ ret = -EINTR;
++ break;
++ }
++ spin_lock(&msg_queue_spinlock);
++ } while (user_service->msg_remove ==
++ user_service->msg_insert);
++
++ if (ret)
++ break;
++ }
++
++ BUG_ON((int)(user_service->msg_insert -
++ user_service->msg_remove) < 0);
++
++ header = user_service->msg_queue[user_service->msg_remove &
++ (MSG_QUEUE_SIZE - 1)];
++ user_service->msg_remove++;
++ spin_unlock(&msg_queue_spinlock);
++
++ up(&user_service->remove_event);
++ if (header == NULL)
++ ret = -ENOTCONN;
++ else if (header->size <= args.bufsize) {
++ /* Copy to user space if msgbuf is not NULL */
++ if ((args.buf == NULL) ||
++ (copy_to_user((void __user *)args.buf,
++ header->data,
++ header->size) == 0)) {
++ ret = header->size;
++ vchiq_release_message(
++ service->handle,
++ header);
++ } else
++ ret = -EFAULT;
++ } else {
++ vchiq_log_error(vchiq_arm_log_level,
++ "header %x: bufsize %x < size %x",
++ (unsigned int)header, args.bufsize,
++ header->size);
++ WARN(1, "invalid size\n");
++ ret = -EMSGSIZE;
++ }
++ DEBUG_TRACE(DEQUEUE_MESSAGE_LINE);
++ } break;
++
++ case VCHIQ_IOC_GET_CLIENT_ID: {
++ VCHIQ_SERVICE_HANDLE_T handle = (VCHIQ_SERVICE_HANDLE_T)arg;
++
++ ret = vchiq_get_client_id(handle);
++ } break;
++
++ case VCHIQ_IOC_GET_CONFIG: {
++ VCHIQ_GET_CONFIG_T args;
++ VCHIQ_CONFIG_T config;
++
++ if (copy_from_user(&args, (const void __user *)arg,
++ sizeof(args)) != 0) {
++ ret = -EFAULT;
++ break;
++ }
++ if (args.config_size > sizeof(config)) {
++ ret = -EINVAL;
++ break;
++ }
++ status = vchiq_get_config(instance, args.config_size, &config);
++ if (status == VCHIQ_SUCCESS) {
++ if (copy_to_user((void __user *)args.pconfig,
++ &config, args.config_size) != 0) {
++ ret = -EFAULT;
++ break;
++ }
++ }
++ } break;
++
++ case VCHIQ_IOC_SET_SERVICE_OPTION: {
++ VCHIQ_SET_SERVICE_OPTION_T args;
++
++ if (copy_from_user(
++ &args, (const void __user *)arg,
++ sizeof(args)) != 0) {
++ ret = -EFAULT;
++ break;
++ }
++
++ service = find_service_for_instance(instance, args.handle);
++ if (!service) {
++ ret = -EINVAL;
++ break;
++ }
++
++ status = vchiq_set_service_option(
++ args.handle, args.option, args.value);
++ } break;
++
++ case VCHIQ_IOC_DUMP_PHYS_MEM: {
++ VCHIQ_DUMP_MEM_T args;
++
++ if (copy_from_user
++ (&args, (const void __user *)arg,
++ sizeof(args)) != 0) {
++ ret = -EFAULT;
++ break;
++ }
++ dump_phys_mem(args.virt_addr, args.num_bytes);
++ } break;
++
++ case VCHIQ_IOC_LIB_VERSION: {
++ unsigned int lib_version = (unsigned int)arg;
++
++ if (lib_version < VCHIQ_VERSION_MIN)
++ ret = -EINVAL;
++ else if (lib_version >= VCHIQ_VERSION_CLOSE_DELIVERED)
++ instance->use_close_delivered = 1;
++ } break;
++
++ case VCHIQ_IOC_CLOSE_DELIVERED: {
++ VCHIQ_SERVICE_HANDLE_T handle = (VCHIQ_SERVICE_HANDLE_T)arg;
++
++ service = find_closed_service_for_instance(instance, handle);
++ if (service != NULL) {
++ USER_SERVICE_T *user_service =
++ (USER_SERVICE_T *)service->base.userdata;
++ close_delivered(user_service);
++ }
++ else
++ ret = -EINVAL;
++ } break;
++
++ default:
++ ret = -ENOTTY;
++ break;
++ }
++
++ if (service)
++ unlock_service(service);
++
++ if (ret == 0) {
++ if (status == VCHIQ_ERROR)
++ ret = -EIO;
++ else if (status == VCHIQ_RETRY)
++ ret = -EINTR;
++ }
++
++ if ((status == VCHIQ_SUCCESS) && (ret < 0) && (ret != -EINTR) &&
++ (ret != -EWOULDBLOCK))
++ vchiq_log_info(vchiq_arm_log_level,
++ " ioctl instance %lx, cmd %s -> status %d, %ld",
++ (unsigned long)instance,
++ (_IOC_NR(cmd) <= VCHIQ_IOC_MAX) ?
++ ioctl_names[_IOC_NR(cmd)] :
++ "<invalid>",
++ status, ret);
++ else
++ vchiq_log_trace(vchiq_arm_log_level,
++ " ioctl instance %lx, cmd %s -> status %d, %ld",
++ (unsigned long)instance,
++ (_IOC_NR(cmd) <= VCHIQ_IOC_MAX) ?
++ ioctl_names[_IOC_NR(cmd)] :
++ "<invalid>",
++ status, ret);
++
++ return ret;
++}
++
++/****************************************************************************
++*
++* vchiq_open
++*
++***************************************************************************/
++
++static int
++vchiq_open(struct inode *inode, struct file *file)
++{
++ int dev = iminor(inode) & 0x0f;
++ vchiq_log_info(vchiq_arm_log_level, "vchiq_open");
++ switch (dev) {
++ case VCHIQ_MINOR: {
++ int ret;
++ VCHIQ_STATE_T *state = vchiq_get_state();
++ VCHIQ_INSTANCE_T instance;
++
++ if (!state) {
++ vchiq_log_error(vchiq_arm_log_level,
++ "vchiq has no connection to VideoCore");
++ return -ENOTCONN;
++ }
++
++ instance = kzalloc(sizeof(*instance), GFP_KERNEL);
++ if (!instance)
++ return -ENOMEM;
++
++ instance->state = state;
++ instance->pid = current->tgid;
++
++ ret = vchiq_debugfs_add_instance(instance);
++ if (ret != 0) {
++ kfree(instance);
++ return ret;
++ }
++
++ sema_init(&instance->insert_event, 0);
++ sema_init(&instance->remove_event, 0);
++ mutex_init(&instance->completion_mutex);
++ mutex_init(&instance->bulk_waiter_list_mutex);
++ INIT_LIST_HEAD(&instance->bulk_waiter_list);
++
++ file->private_data = instance;
++ } break;
++
++ default:
++ vchiq_log_error(vchiq_arm_log_level,
++ "Unknown minor device: %d", dev);
++ return -ENXIO;
++ }
++
++ return 0;
++}
++
++/****************************************************************************
++*
++* vchiq_release
++*
++***************************************************************************/
++
++static int
++vchiq_release(struct inode *inode, struct file *file)
++{
++ int dev = iminor(inode) & 0x0f;
++ int ret = 0;
++ switch (dev) {
++ case VCHIQ_MINOR: {
++ VCHIQ_INSTANCE_T instance = file->private_data;
++ VCHIQ_STATE_T *state = vchiq_get_state();
++ VCHIQ_SERVICE_T *service;
++ int i;
++
++ vchiq_log_info(vchiq_arm_log_level,
++ "vchiq_release: instance=%lx",
++ (unsigned long)instance);
++
++ if (!state) {
++ ret = -EPERM;
++ goto out;
++ }
++
++ /* Ensure videocore is awake to allow termination. */
++ vchiq_use_internal(instance->state, NULL,
++ USE_TYPE_VCHIQ);
++
++ mutex_lock(&instance->completion_mutex);
++
++ /* Wake the completion thread and ask it to exit */
++ instance->closing = 1;
++ up(&instance->insert_event);
++
++ mutex_unlock(&instance->completion_mutex);
++
++ /* Wake the slot handler if the completion queue is full. */
++ up(&instance->remove_event);
++
++ /* Mark all services for termination... */
++ i = 0;
++ while ((service = next_service_by_instance(state, instance,
++ &i)) != NULL) {
++ USER_SERVICE_T *user_service = service->base.userdata;
++
++ /* Wake the slot handler if the msg queue is full. */
++ up(&user_service->remove_event);
++
++ vchiq_terminate_service_internal(service);
++ unlock_service(service);
++ }
++
++ /* ...and wait for them to die */
++ i = 0;
++ while ((service = next_service_by_instance(state, instance, &i))
++ != NULL) {
++ USER_SERVICE_T *user_service = service->base.userdata;
++
++ down(&service->remove_event);
++
++ BUG_ON(service->srvstate != VCHIQ_SRVSTATE_FREE);
++
++ spin_lock(&msg_queue_spinlock);
++
++ while (user_service->msg_remove !=
++ user_service->msg_insert) {
++ VCHIQ_HEADER_T *header = user_service->
++ msg_queue[user_service->msg_remove &
++ (MSG_QUEUE_SIZE - 1)];
++ user_service->msg_remove++;
++ spin_unlock(&msg_queue_spinlock);
++
++ if (header)
++ vchiq_release_message(
++ service->handle,
++ header);
++ spin_lock(&msg_queue_spinlock);
++ }
++
++ spin_unlock(&msg_queue_spinlock);
++
++ unlock_service(service);
++ }
++
++ /* Release any closed services */
++ while (instance->completion_remove !=
++ instance->completion_insert) {
++ VCHIQ_COMPLETION_DATA_T *completion;
++ VCHIQ_SERVICE_T *service;
++ completion = &instance->completions[
++ instance->completion_remove &
++ (MAX_COMPLETIONS - 1)];
++ service = completion->service_userdata;
++ if (completion->reason == VCHIQ_SERVICE_CLOSED)
++ {
++ USER_SERVICE_T *user_service =
++ service->base.userdata;
++
++ /* Wake any blocked user-thread */
++ if (instance->use_close_delivered)
++ up(&user_service->close_event);
++ unlock_service(service);
++ }
++ instance->completion_remove++;
++ }
++
++ /* Release the PEER service count. */
++ vchiq_release_internal(instance->state, NULL);
++
++ {
++ struct list_head *pos, *next;
++ list_for_each_safe(pos, next,
++ &instance->bulk_waiter_list) {
++ struct bulk_waiter_node *waiter;
++ waiter = list_entry(pos,
++ struct bulk_waiter_node,
++ list);
++ list_del(pos);
++ vchiq_log_info(vchiq_arm_log_level,
++ "bulk_waiter - cleaned up %x "
++ "for pid %d",
++ (unsigned int)waiter, waiter->pid);
++ kfree(waiter);
++ }
++ }
++
++ vchiq_debugfs_remove_instance(instance);
++
++ kfree(instance);
++ file->private_data = NULL;
++ } break;
++
++ default:
++ vchiq_log_error(vchiq_arm_log_level,
++ "Unknown minor device: %d", dev);
++ ret = -ENXIO;
++ }
++
++out:
++ return ret;
++}
++
++/****************************************************************************
++*
++* vchiq_dump
++*
++***************************************************************************/
++
++void
++vchiq_dump(void *dump_context, const char *str, int len)
++{
++ DUMP_CONTEXT_T *context = (DUMP_CONTEXT_T *)dump_context;
++
++ if (context->actual < context->space) {
++ int copy_bytes;
++ if (context->offset > 0) {
++ int skip_bytes = min(len, (int)context->offset);
++ str += skip_bytes;
++ len -= skip_bytes;
++ context->offset -= skip_bytes;
++ if (context->offset > 0)
++ return;
++ }
++ copy_bytes = min(len, (int)(context->space - context->actual));
++ if (copy_bytes == 0)
++ return;
++ if (copy_to_user(context->buf + context->actual, str,
++ copy_bytes))
++ context->actual = -EFAULT;
++ context->actual += copy_bytes;
++ len -= copy_bytes;
++
++ /* If tne terminating NUL is included in the length, then it
++ ** marks the end of a line and should be replaced with a
++ ** carriage return. */
++ if ((len == 0) && (str[copy_bytes - 1] == '\0')) {
++ char cr = '\n';
++ if (copy_to_user(context->buf + context->actual - 1,
++ &cr, 1))
++ context->actual = -EFAULT;
++ }
++ }
++}
++
++/****************************************************************************
++*
++* vchiq_dump_platform_instance_state
++*
++***************************************************************************/
++
++void
++vchiq_dump_platform_instances(void *dump_context)
++{
++ VCHIQ_STATE_T *state = vchiq_get_state();
++ char buf[80];
++ int len;
++ int i;
++
++ /* There is no list of instances, so instead scan all services,
++ marking those that have been dumped. */
++
++ for (i = 0; i < state->unused_service; i++) {
++ VCHIQ_SERVICE_T *service = state->services[i];
++ VCHIQ_INSTANCE_T instance;
++
++ if (service && (service->base.callback == service_callback)) {
++ instance = service->instance;
++ if (instance)
++ instance->mark = 0;
++ }
++ }
++
++ for (i = 0; i < state->unused_service; i++) {
++ VCHIQ_SERVICE_T *service = state->services[i];
++ VCHIQ_INSTANCE_T instance;
++
++ if (service && (service->base.callback == service_callback)) {
++ instance = service->instance;
++ if (instance && !instance->mark) {
++ len = snprintf(buf, sizeof(buf),
++ "Instance %x: pid %d,%s completions "
++ "%d/%d",
++ (unsigned int)instance, instance->pid,
++ instance->connected ? " connected, " :
++ "",
++ instance->completion_insert -
++ instance->completion_remove,
++ MAX_COMPLETIONS);
++
++ vchiq_dump(dump_context, buf, len + 1);
++
++ instance->mark = 1;
++ }
++ }
++ }
++}
++
++/****************************************************************************
++*
++* vchiq_dump_platform_service_state
++*
++***************************************************************************/
++
++void
++vchiq_dump_platform_service_state(void *dump_context, VCHIQ_SERVICE_T *service)
++{
++ USER_SERVICE_T *user_service = (USER_SERVICE_T *)service->base.userdata;
++ char buf[80];
++ int len;
++
++ len = snprintf(buf, sizeof(buf), " instance %x",
++ (unsigned int)service->instance);
++
++ if ((service->base.callback == service_callback) &&
++ user_service->is_vchi) {
++ len += snprintf(buf + len, sizeof(buf) - len,
++ ", %d/%d messages",
++ user_service->msg_insert - user_service->msg_remove,
++ MSG_QUEUE_SIZE);
++
++ if (user_service->dequeue_pending)
++ len += snprintf(buf + len, sizeof(buf) - len,
++ " (dequeue pending)");
++ }
++
++ vchiq_dump(dump_context, buf, len + 1);
++}
++
++/****************************************************************************
++*
++* dump_user_mem
++*
++***************************************************************************/
++
++static void
++dump_phys_mem(void *virt_addr, uint32_t num_bytes)
++{
++ int rc;
++ uint8_t *end_virt_addr = virt_addr + num_bytes;
++ int num_pages;
++ int offset;
++ int end_offset;
++ int page_idx;
++ int prev_idx;
++ struct page *page;
++ struct page **pages;
++ uint8_t *kmapped_virt_ptr;
++
++ /* Align virtAddr and endVirtAddr to 16 byte boundaries. */
++
++ virt_addr = (void *)((unsigned long)virt_addr & ~0x0fuL);
++ end_virt_addr = (void *)(((unsigned long)end_virt_addr + 15uL) &
++ ~0x0fuL);
++
++ offset = (int)(long)virt_addr & (PAGE_SIZE - 1);
++ end_offset = (int)(long)end_virt_addr & (PAGE_SIZE - 1);
++
++ num_pages = (offset + num_bytes + PAGE_SIZE - 1) / PAGE_SIZE;
++
++ pages = kmalloc(sizeof(struct page *) * num_pages, GFP_KERNEL);
++ if (pages == NULL) {
++ vchiq_log_error(vchiq_arm_log_level,
++ "Unable to allocation memory for %d pages\n",
++ num_pages);
++ return;
++ }
++
++ down_read(&current->mm->mmap_sem);
++ rc = get_user_pages(current, /* task */
++ current->mm, /* mm */
++ (unsigned long)virt_addr, /* start */
++ num_pages, /* len */
++ 0, /* write */
++ 0, /* force */
++ pages, /* pages (array of page pointers) */
++ NULL); /* vmas */
++ up_read(&current->mm->mmap_sem);
++
++ prev_idx = -1;
++ page = NULL;
++
++ while (offset < end_offset) {
++
++ int page_offset = offset % PAGE_SIZE;
++ page_idx = offset / PAGE_SIZE;
++
++ if (page_idx != prev_idx) {
++
++ if (page != NULL)
++ kunmap(page);
++ page = pages[page_idx];
++ kmapped_virt_ptr = kmap(page);
++
++ prev_idx = page_idx;
++ }
++
++ if (vchiq_arm_log_level >= VCHIQ_LOG_TRACE)
++ vchiq_log_dump_mem("ph",
++ (uint32_t)(unsigned long)&kmapped_virt_ptr[
++ page_offset],
++ &kmapped_virt_ptr[page_offset], 16);
++
++ offset += 16;
++ }
++ if (page != NULL)
++ kunmap(page);
++
++ for (page_idx = 0; page_idx < num_pages; page_idx++)
++ page_cache_release(pages[page_idx]);
++
++ kfree(pages);
++}
++
++/****************************************************************************
++*
++* vchiq_read
++*
++***************************************************************************/
++
++static ssize_t
++vchiq_read(struct file *file, char __user *buf,
++ size_t count, loff_t *ppos)
++{
++ DUMP_CONTEXT_T context;
++ context.buf = buf;
++ context.actual = 0;
++ context.space = count;
++ context.offset = *ppos;
++
++ vchiq_dump_state(&context, &g_state);
++
++ *ppos += context.actual;
++
++ return context.actual;
++}
++
++VCHIQ_STATE_T *
++vchiq_get_state(void)
++{
++
++ if (g_state.remote == NULL)
++ printk(KERN_ERR "%s: g_state.remote == NULL\n", __func__);
++ else if (g_state.remote->initialised != 1)
++ printk(KERN_NOTICE "%s: g_state.remote->initialised != 1 (%d)\n",
++ __func__, g_state.remote->initialised);
++
++ return ((g_state.remote != NULL) &&
++ (g_state.remote->initialised == 1)) ? &g_state : NULL;
++}
++
++static const struct file_operations
++vchiq_fops = {
++ .owner = THIS_MODULE,
++ .unlocked_ioctl = vchiq_ioctl,
++ .open = vchiq_open,
++ .release = vchiq_release,
++ .read = vchiq_read
++};
++
++/*
++ * Autosuspend related functionality
++ */
++
++int
++vchiq_videocore_wanted(VCHIQ_STATE_T *state)
++{
++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state);
++ if (!arm_state)
++ /* autosuspend not supported - always return wanted */
++ return 1;
++ else if (arm_state->blocked_count)
++ return 1;
++ else if (!arm_state->videocore_use_count)
++ /* usage count zero - check for override unless we're forcing */
++ if (arm_state->resume_blocked)
++ return 0;
++ else
++ return vchiq_platform_videocore_wanted(state);
++ else
++ /* non-zero usage count - videocore still required */
++ return 1;
++}
++
++static VCHIQ_STATUS_T
++vchiq_keepalive_vchiq_callback(VCHIQ_REASON_T reason,
++ VCHIQ_HEADER_T *header,
++ VCHIQ_SERVICE_HANDLE_T service_user,
++ void *bulk_user)
++{
++ vchiq_log_error(vchiq_susp_log_level,
++ "%s callback reason %d", __func__, reason);
++ return 0;
++}
++
++static int
++vchiq_keepalive_thread_func(void *v)
++{
++ VCHIQ_STATE_T *state = (VCHIQ_STATE_T *) v;
++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state);
++
++ VCHIQ_STATUS_T status;
++ VCHIQ_INSTANCE_T instance;
++ VCHIQ_SERVICE_HANDLE_T ka_handle;
++
++ VCHIQ_SERVICE_PARAMS_T params = {
++ .fourcc = VCHIQ_MAKE_FOURCC('K', 'E', 'E', 'P'),
++ .callback = vchiq_keepalive_vchiq_callback,
++ .version = KEEPALIVE_VER,
++ .version_min = KEEPALIVE_VER_MIN
++ };
++
++ status = vchiq_initialise(&instance);
++ if (status != VCHIQ_SUCCESS) {
++ vchiq_log_error(vchiq_susp_log_level,
++ "%s vchiq_initialise failed %d", __func__, status);
++ goto exit;
++ }
++
++ status = vchiq_connect(instance);
++ if (status != VCHIQ_SUCCESS) {
++ vchiq_log_error(vchiq_susp_log_level,
++ "%s vchiq_connect failed %d", __func__, status);
++ goto shutdown;
++ }
++
++ status = vchiq_add_service(instance, &params, &ka_handle);
++ if (status != VCHIQ_SUCCESS) {
++ vchiq_log_error(vchiq_susp_log_level,
++ "%s vchiq_open_service failed %d", __func__, status);
++ goto shutdown;
++ }
++
++ while (1) {
++ long rc = 0, uc = 0;
++ if (wait_for_completion_interruptible(&arm_state->ka_evt)
++ != 0) {
++ vchiq_log_error(vchiq_susp_log_level,
++ "%s interrupted", __func__);
++ flush_signals(current);
++ continue;
++ }
++
++ /* read and clear counters. Do release_count then use_count to
++ * prevent getting more releases than uses */
++ rc = atomic_xchg(&arm_state->ka_release_count, 0);
++ uc = atomic_xchg(&arm_state->ka_use_count, 0);
++
++ /* Call use/release service the requisite number of times.
++ * Process use before release so use counts don't go negative */
++ while (uc--) {
++ atomic_inc(&arm_state->ka_use_ack_count);
++ status = vchiq_use_service(ka_handle);
++ if (status != VCHIQ_SUCCESS) {
++ vchiq_log_error(vchiq_susp_log_level,
++ "%s vchiq_use_service error %d",
++ __func__, status);
++ }
++ }
++ while (rc--) {
++ status = vchiq_release_service(ka_handle);
++ if (status != VCHIQ_SUCCESS) {
++ vchiq_log_error(vchiq_susp_log_level,
++ "%s vchiq_release_service error %d",
++ __func__, status);
++ }
++ }
++ }
++
++shutdown:
++ vchiq_shutdown(instance);
++exit:
++ return 0;
++}
++
++
++
++VCHIQ_STATUS_T
++vchiq_arm_init_state(VCHIQ_STATE_T *state, VCHIQ_ARM_STATE_T *arm_state)
++{
++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS;
++
++ if (arm_state) {
++ rwlock_init(&arm_state->susp_res_lock);
++
++ init_completion(&arm_state->ka_evt);
++ atomic_set(&arm_state->ka_use_count, 0);
++ atomic_set(&arm_state->ka_use_ack_count, 0);
++ atomic_set(&arm_state->ka_release_count, 0);
++
++ init_completion(&arm_state->vc_suspend_complete);
++
++ init_completion(&arm_state->vc_resume_complete);
++ /* Initialise to 'done' state. We only want to block on resume
++ * completion while videocore is suspended. */
++ set_resume_state(arm_state, VC_RESUME_RESUMED);
++
++ init_completion(&arm_state->resume_blocker);
++ /* Initialise to 'done' state. We only want to block on this
++ * completion while resume is blocked */
++ complete_all(&arm_state->resume_blocker);
++
++ init_completion(&arm_state->blocked_blocker);
++ /* Initialise to 'done' state. We only want to block on this
++ * completion while things are waiting on the resume blocker */
++ complete_all(&arm_state->blocked_blocker);
++
++ arm_state->suspend_timer_timeout = SUSPEND_TIMER_TIMEOUT_MS;
++ arm_state->suspend_timer_running = 0;
++ init_timer(&arm_state->suspend_timer);
++ arm_state->suspend_timer.data = (unsigned long)(state);
++ arm_state->suspend_timer.function = suspend_timer_callback;
++
++ arm_state->first_connect = 0;
++
++ }
++ return status;
++}
++
++/*
++** Functions to modify the state variables;
++** set_suspend_state
++** set_resume_state
++**
++** There are more state variables than we might like, so ensure they remain in
++** step. Suspend and resume state are maintained separately, since most of
++** these state machines can operate independently. However, there are a few
++** states where state transitions in one state machine cause a reset to the
++** other state machine. In addition, there are some completion events which
++** need to occur on state machine reset and end-state(s), so these are also
++** dealt with in these functions.
++**
++** In all states we set the state variable according to the input, but in some
++** cases we perform additional steps outlined below;
++**
++** VC_SUSPEND_IDLE - Initialise the suspend completion at the same time.
++** The suspend completion is completed after any suspend
++** attempt. When we reset the state machine we also reset
++** the completion. This reset occurs when videocore is
++** resumed, and also if we initiate suspend after a suspend
++** failure.
++**
++** VC_SUSPEND_IN_PROGRESS - This state is considered the point of no return for
++** suspend - ie from this point on we must try to suspend
++** before resuming can occur. We therefore also reset the
++** resume state machine to VC_RESUME_IDLE in this state.
++**
++** VC_SUSPEND_SUSPENDED - Suspend has completed successfully. Also call
++** complete_all on the suspend completion to notify
++** anything waiting for suspend to happen.
++**
++** VC_SUSPEND_REJECTED - Videocore rejected suspend. Videocore will also
++** initiate resume, so no need to alter resume state.
++** We call complete_all on the suspend completion to notify
++** of suspend rejection.
++**
++** VC_SUSPEND_FAILED - We failed to initiate videocore suspend. We notify the
++** suspend completion and reset the resume state machine.
++**
++** VC_RESUME_IDLE - Initialise the resume completion at the same time. The
++** resume completion is in it's 'done' state whenever
++** videcore is running. Therfore, the VC_RESUME_IDLE state
++** implies that videocore is suspended.
++** Hence, any thread which needs to wait until videocore is
++** running can wait on this completion - it will only block
++** if videocore is suspended.
++**
++** VC_RESUME_RESUMED - Resume has completed successfully. Videocore is running.
++** Call complete_all on the resume completion to unblock
++** any threads waiting for resume. Also reset the suspend
++** state machine to it's idle state.
++**
++** VC_RESUME_FAILED - Currently unused - no mechanism to fail resume exists.
++*/
++
++void
++set_suspend_state(VCHIQ_ARM_STATE_T *arm_state,
++ enum vc_suspend_status new_state)
++{
++ /* set the state in all cases */
++ arm_state->vc_suspend_state = new_state;
++
++ /* state specific additional actions */
++ switch (new_state) {
++ case VC_SUSPEND_FORCE_CANCELED:
++ complete_all(&arm_state->vc_suspend_complete);
++ break;
++ case VC_SUSPEND_REJECTED:
++ complete_all(&arm_state->vc_suspend_complete);
++ break;
++ case VC_SUSPEND_FAILED:
++ complete_all(&arm_state->vc_suspend_complete);
++ arm_state->vc_resume_state = VC_RESUME_RESUMED;
++ complete_all(&arm_state->vc_resume_complete);
++ break;
++ case VC_SUSPEND_IDLE:
++ reinit_completion(&arm_state->vc_suspend_complete);
++ break;
++ case VC_SUSPEND_REQUESTED:
++ break;
++ case VC_SUSPEND_IN_PROGRESS:
++ set_resume_state(arm_state, VC_RESUME_IDLE);
++ break;
++ case VC_SUSPEND_SUSPENDED:
++ complete_all(&arm_state->vc_suspend_complete);
++ break;
++ default:
++ BUG();
++ break;
++ }
++}
++
++void
++set_resume_state(VCHIQ_ARM_STATE_T *arm_state,
++ enum vc_resume_status new_state)
++{
++ /* set the state in all cases */
++ arm_state->vc_resume_state = new_state;
++
++ /* state specific additional actions */
++ switch (new_state) {
++ case VC_RESUME_FAILED:
++ break;
++ case VC_RESUME_IDLE:
++ reinit_completion(&arm_state->vc_resume_complete);
++ break;
++ case VC_RESUME_REQUESTED:
++ break;
++ case VC_RESUME_IN_PROGRESS:
++ break;
++ case VC_RESUME_RESUMED:
++ complete_all(&arm_state->vc_resume_complete);
++ set_suspend_state(arm_state, VC_SUSPEND_IDLE);
++ break;
++ default:
++ BUG();
++ break;
++ }
++}
++
++
++/* should be called with the write lock held */
++inline void
++start_suspend_timer(VCHIQ_ARM_STATE_T *arm_state)
++{
++ del_timer(&arm_state->suspend_timer);
++ arm_state->suspend_timer.expires = jiffies +
++ msecs_to_jiffies(arm_state->
++ suspend_timer_timeout);
++ add_timer(&arm_state->suspend_timer);
++ arm_state->suspend_timer_running = 1;
++}
++
++/* should be called with the write lock held */
++static inline void
++stop_suspend_timer(VCHIQ_ARM_STATE_T *arm_state)
++{
++ if (arm_state->suspend_timer_running) {
++ del_timer(&arm_state->suspend_timer);
++ arm_state->suspend_timer_running = 0;
++ }
++}
++
++static inline int
++need_resume(VCHIQ_STATE_T *state)
++{
++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state);
++ return (arm_state->vc_suspend_state > VC_SUSPEND_IDLE) &&
++ (arm_state->vc_resume_state < VC_RESUME_REQUESTED) &&
++ vchiq_videocore_wanted(state);
++}
++
++static int
++block_resume(VCHIQ_ARM_STATE_T *arm_state)
++{
++ int status = VCHIQ_SUCCESS;
++ const unsigned long timeout_val =
++ msecs_to_jiffies(FORCE_SUSPEND_TIMEOUT_MS);
++ int resume_count = 0;
++
++ /* Allow any threads which were blocked by the last force suspend to
++ * complete if they haven't already. Only give this one shot; if
++ * blocked_count is incremented after blocked_blocker is completed
++ * (which only happens when blocked_count hits 0) then those threads
++ * will have to wait until next time around */
++ if (arm_state->blocked_count) {
++ reinit_completion(&arm_state->blocked_blocker);
++ write_unlock_bh(&arm_state->susp_res_lock);
++ vchiq_log_info(vchiq_susp_log_level, "%s wait for previously "
++ "blocked clients", __func__);
++ if (wait_for_completion_interruptible_timeout(
++ &arm_state->blocked_blocker, timeout_val)
++ <= 0) {
++ vchiq_log_error(vchiq_susp_log_level, "%s wait for "
++ "previously blocked clients failed" , __func__);
++ status = VCHIQ_ERROR;
++ write_lock_bh(&arm_state->susp_res_lock);
++ goto out;
++ }
++ vchiq_log_info(vchiq_susp_log_level, "%s previously blocked "
++ "clients resumed", __func__);
++ write_lock_bh(&arm_state->susp_res_lock);
++ }
++
++ /* We need to wait for resume to complete if it's in process */
++ while (arm_state->vc_resume_state != VC_RESUME_RESUMED &&
++ arm_state->vc_resume_state > VC_RESUME_IDLE) {
++ if (resume_count > 1) {
++ status = VCHIQ_ERROR;
++ vchiq_log_error(vchiq_susp_log_level, "%s waited too "
++ "many times for resume" , __func__);
++ goto out;
++ }
++ write_unlock_bh(&arm_state->susp_res_lock);
++ vchiq_log_info(vchiq_susp_log_level, "%s wait for resume",
++ __func__);
++ if (wait_for_completion_interruptible_timeout(
++ &arm_state->vc_resume_complete, timeout_val)
++ <= 0) {
++ vchiq_log_error(vchiq_susp_log_level, "%s wait for "
++ "resume failed (%s)", __func__,
++ resume_state_names[arm_state->vc_resume_state +
++ VC_RESUME_NUM_OFFSET]);
++ status = VCHIQ_ERROR;
++ write_lock_bh(&arm_state->susp_res_lock);
++ goto out;
++ }
++ vchiq_log_info(vchiq_susp_log_level, "%s resumed", __func__);
++ write_lock_bh(&arm_state->susp_res_lock);
++ resume_count++;
++ }
++ reinit_completion(&arm_state->resume_blocker);
++ arm_state->resume_blocked = 1;
++
++out:
++ return status;
++}
++
++static inline void
++unblock_resume(VCHIQ_ARM_STATE_T *arm_state)
++{
++ complete_all(&arm_state->resume_blocker);
++ arm_state->resume_blocked = 0;
++}
++
++/* Initiate suspend via slot handler. Should be called with the write lock
++ * held */
++VCHIQ_STATUS_T
++vchiq_arm_vcsuspend(VCHIQ_STATE_T *state)
++{
++ VCHIQ_STATUS_T status = VCHIQ_ERROR;
++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state);
++
++ if (!arm_state)
++ goto out;
++
++ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__);
++ status = VCHIQ_SUCCESS;
++
++
++ switch (arm_state->vc_suspend_state) {
++ case VC_SUSPEND_REQUESTED:
++ vchiq_log_info(vchiq_susp_log_level, "%s: suspend already "
++ "requested", __func__);
++ break;
++ case VC_SUSPEND_IN_PROGRESS:
++ vchiq_log_info(vchiq_susp_log_level, "%s: suspend already in "
++ "progress", __func__);
++ break;
++
++ default:
++ /* We don't expect to be in other states, so log but continue
++ * anyway */
++ vchiq_log_error(vchiq_susp_log_level,
++ "%s unexpected suspend state %s", __func__,
++ suspend_state_names[arm_state->vc_suspend_state +
++ VC_SUSPEND_NUM_OFFSET]);
++ /* fall through */
++ case VC_SUSPEND_REJECTED:
++ case VC_SUSPEND_FAILED:
++ /* Ensure any idle state actions have been run */
++ set_suspend_state(arm_state, VC_SUSPEND_IDLE);
++ /* fall through */
++ case VC_SUSPEND_IDLE:
++ vchiq_log_info(vchiq_susp_log_level,
++ "%s: suspending", __func__);
++ set_suspend_state(arm_state, VC_SUSPEND_REQUESTED);
++ /* kick the slot handler thread to initiate suspend */
++ request_poll(state, NULL, 0);
++ break;
++ }
++
++out:
++ vchiq_log_trace(vchiq_susp_log_level, "%s exit %d", __func__, status);
++ return status;
++}
++
++void
++vchiq_platform_check_suspend(VCHIQ_STATE_T *state)
++{
++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state);
++ int susp = 0;
++
++ if (!arm_state)
++ goto out;
++
++ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__);
++
++ write_lock_bh(&arm_state->susp_res_lock);
++ if (arm_state->vc_suspend_state == VC_SUSPEND_REQUESTED &&
++ arm_state->vc_resume_state == VC_RESUME_RESUMED) {
++ set_suspend_state(arm_state, VC_SUSPEND_IN_PROGRESS);
++ susp = 1;
++ }
++ write_unlock_bh(&arm_state->susp_res_lock);
++
++ if (susp)
++ vchiq_platform_suspend(state);
++
++out:
++ vchiq_log_trace(vchiq_susp_log_level, "%s exit", __func__);
++ return;
++}
++
++
++static void
++output_timeout_error(VCHIQ_STATE_T *state)
++{
++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state);
++ char service_err[50] = "";
++ int vc_use_count = arm_state->videocore_use_count;
++ int active_services = state->unused_service;
++ int i;
++
++ if (!arm_state->videocore_use_count) {
++ snprintf(service_err, 50, " Videocore usecount is 0");
++ goto output_msg;
++ }
++ for (i = 0; i < active_services; i++) {
++ VCHIQ_SERVICE_T *service_ptr = state->services[i];
++ if (service_ptr && service_ptr->service_use_count &&
++ (service_ptr->srvstate != VCHIQ_SRVSTATE_FREE)) {
++ snprintf(service_err, 50, " %c%c%c%c(%d) service has "
++ "use count %d%s", VCHIQ_FOURCC_AS_4CHARS(
++ service_ptr->base.fourcc),
++ service_ptr->client_id,
++ service_ptr->service_use_count,
++ service_ptr->service_use_count ==
++ vc_use_count ? "" : " (+ more)");
++ break;
++ }
++ }
++
++output_msg:
++ vchiq_log_error(vchiq_susp_log_level,
++ "timed out waiting for vc suspend (%d).%s",
++ arm_state->autosuspend_override, service_err);
++
++}
++
++/* Try to get videocore into suspended state, regardless of autosuspend state.
++** We don't actually force suspend, since videocore may get into a bad state
++** if we force suspend at a bad time. Instead, we wait for autosuspend to
++** determine a good point to suspend. If this doesn't happen within 100ms we
++** report failure.
++**
++** Returns VCHIQ_SUCCESS if videocore suspended successfully, VCHIQ_RETRY if
++** videocore failed to suspend in time or VCHIQ_ERROR if interrupted.
++*/
++VCHIQ_STATUS_T
++vchiq_arm_force_suspend(VCHIQ_STATE_T *state)
++{
++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state);
++ VCHIQ_STATUS_T status = VCHIQ_ERROR;
++ long rc = 0;
++ int repeat = -1;
++
++ if (!arm_state)
++ goto out;
++
++ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__);
++
++ write_lock_bh(&arm_state->susp_res_lock);
++
++ status = block_resume(arm_state);
++ if (status != VCHIQ_SUCCESS)
++ goto unlock;
++ if (arm_state->vc_suspend_state == VC_SUSPEND_SUSPENDED) {
++ /* Already suspended - just block resume and exit */
++ vchiq_log_info(vchiq_susp_log_level, "%s already suspended",
++ __func__);
++ status = VCHIQ_SUCCESS;
++ goto unlock;
++ } else if (arm_state->vc_suspend_state <= VC_SUSPEND_IDLE) {
++ /* initiate suspend immediately in the case that we're waiting
++ * for the timeout */
++ stop_suspend_timer(arm_state);
++ if (!vchiq_videocore_wanted(state)) {
++ vchiq_log_info(vchiq_susp_log_level, "%s videocore "
++ "idle, initiating suspend", __func__);
++ status = vchiq_arm_vcsuspend(state);
++ } else if (arm_state->autosuspend_override <
++ FORCE_SUSPEND_FAIL_MAX) {
++ vchiq_log_info(vchiq_susp_log_level, "%s letting "
++ "videocore go idle", __func__);
++ status = VCHIQ_SUCCESS;
++ } else {
++ vchiq_log_warning(vchiq_susp_log_level, "%s failed too "
++ "many times - attempting suspend", __func__);
++ status = vchiq_arm_vcsuspend(state);
++ }
++ } else {
++ vchiq_log_info(vchiq_susp_log_level, "%s videocore suspend "
++ "in progress - wait for completion", __func__);
++ status = VCHIQ_SUCCESS;
++ }
++
++ /* Wait for suspend to happen due to system idle (not forced..) */
++ if (status != VCHIQ_SUCCESS)
++ goto unblock_resume;
++
++ do {
++ write_unlock_bh(&arm_state->susp_res_lock);
++
++ rc = wait_for_completion_interruptible_timeout(
++ &arm_state->vc_suspend_complete,
++ msecs_to_jiffies(FORCE_SUSPEND_TIMEOUT_MS));
++
++ write_lock_bh(&arm_state->susp_res_lock);
++ if (rc < 0) {
++ vchiq_log_warning(vchiq_susp_log_level, "%s "
++ "interrupted waiting for suspend", __func__);
++ status = VCHIQ_ERROR;
++ goto unblock_resume;
++ } else if (rc == 0) {
++ if (arm_state->vc_suspend_state > VC_SUSPEND_IDLE) {
++ /* Repeat timeout once if in progress */
++ if (repeat < 0) {
++ repeat = 1;
++ continue;
++ }
++ }
++ arm_state->autosuspend_override++;
++ output_timeout_error(state);
++
++ status = VCHIQ_RETRY;
++ goto unblock_resume;
++ }
++ } while (0 < (repeat--));
++
++ /* Check and report state in case we need to abort ARM suspend */
++ if (arm_state->vc_suspend_state != VC_SUSPEND_SUSPENDED) {
++ status = VCHIQ_RETRY;
++ vchiq_log_error(vchiq_susp_log_level,
++ "%s videocore suspend failed (state %s)", __func__,
++ suspend_state_names[arm_state->vc_suspend_state +
++ VC_SUSPEND_NUM_OFFSET]);
++ /* Reset the state only if it's still in an error state.
++ * Something could have already initiated another suspend. */
++ if (arm_state->vc_suspend_state < VC_SUSPEND_IDLE)
++ set_suspend_state(arm_state, VC_SUSPEND_IDLE);
++
++ goto unblock_resume;
++ }
++
++ /* successfully suspended - unlock and exit */
++ goto unlock;
++
++unblock_resume:
++ /* all error states need to unblock resume before exit */
++ unblock_resume(arm_state);
++
++unlock:
++ write_unlock_bh(&arm_state->susp_res_lock);
++
++out:
++ vchiq_log_trace(vchiq_susp_log_level, "%s exit %d", __func__, status);
++ return status;
++}
++
++void
++vchiq_check_suspend(VCHIQ_STATE_T *state)
++{
++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state);
++
++ if (!arm_state)
++ goto out;
++
++ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__);
++
++ write_lock_bh(&arm_state->susp_res_lock);
++ if (arm_state->vc_suspend_state != VC_SUSPEND_SUSPENDED &&
++ arm_state->first_connect &&
++ !vchiq_videocore_wanted(state)) {
++ vchiq_arm_vcsuspend(state);
++ }
++ write_unlock_bh(&arm_state->susp_res_lock);
++
++out:
++ vchiq_log_trace(vchiq_susp_log_level, "%s exit", __func__);
++ return;
++}
++
++
++int
++vchiq_arm_allow_resume(VCHIQ_STATE_T *state)
++{
++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state);
++ int resume = 0;
++ int ret = -1;
++
++ if (!arm_state)
++ goto out;
++
++ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__);
++
++ write_lock_bh(&arm_state->susp_res_lock);
++ unblock_resume(arm_state);
++ resume = vchiq_check_resume(state);
++ write_unlock_bh(&arm_state->susp_res_lock);
++
++ if (resume) {
++ if (wait_for_completion_interruptible(
++ &arm_state->vc_resume_complete) < 0) {
++ vchiq_log_error(vchiq_susp_log_level,
++ "%s interrupted", __func__);
++ /* failed, cannot accurately derive suspend
++ * state, so exit early. */
++ goto out;
++ }
++ }
++
++ read_lock_bh(&arm_state->susp_res_lock);
++ if (arm_state->vc_suspend_state == VC_SUSPEND_SUSPENDED) {
++ vchiq_log_info(vchiq_susp_log_level,
++ "%s: Videocore remains suspended", __func__);
++ } else {
++ vchiq_log_info(vchiq_susp_log_level,
++ "%s: Videocore resumed", __func__);
++ ret = 0;
++ }
++ read_unlock_bh(&arm_state->susp_res_lock);
++out:
++ vchiq_log_trace(vchiq_susp_log_level, "%s exit %d", __func__, ret);
++ return ret;
++}
++
++/* This function should be called with the write lock held */
++int
++vchiq_check_resume(VCHIQ_STATE_T *state)
++{
++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state);
++ int resume = 0;
++
++ if (!arm_state)
++ goto out;
++
++ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__);
++
++ if (need_resume(state)) {
++ set_resume_state(arm_state, VC_RESUME_REQUESTED);
++ request_poll(state, NULL, 0);
++ resume = 1;
++ }
++
++out:
++ vchiq_log_trace(vchiq_susp_log_level, "%s exit", __func__);
++ return resume;
++}
++
++void
++vchiq_platform_check_resume(VCHIQ_STATE_T *state)
++{
++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state);
++ int res = 0;
++
++ if (!arm_state)
++ goto out;
++
++ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__);
++
++ write_lock_bh(&arm_state->susp_res_lock);
++ if (arm_state->wake_address == 0) {
++ vchiq_log_info(vchiq_susp_log_level,
++ "%s: already awake", __func__);
++ goto unlock;
++ }
++ if (arm_state->vc_resume_state == VC_RESUME_IN_PROGRESS) {
++ vchiq_log_info(vchiq_susp_log_level,
++ "%s: already resuming", __func__);
++ goto unlock;
++ }
++
++ if (arm_state->vc_resume_state == VC_RESUME_REQUESTED) {
++ set_resume_state(arm_state, VC_RESUME_IN_PROGRESS);
++ res = 1;
++ } else
++ vchiq_log_trace(vchiq_susp_log_level,
++ "%s: not resuming (resume state %s)", __func__,
++ resume_state_names[arm_state->vc_resume_state +
++ VC_RESUME_NUM_OFFSET]);
++
++unlock:
++ write_unlock_bh(&arm_state->susp_res_lock);
++
++ if (res)
++ vchiq_platform_resume(state);
++
++out:
++ vchiq_log_trace(vchiq_susp_log_level, "%s exit", __func__);
++ return;
++
++}
++
++
++
++VCHIQ_STATUS_T
++vchiq_use_internal(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service,
++ enum USE_TYPE_E use_type)
++{
++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state);
++ VCHIQ_STATUS_T ret = VCHIQ_SUCCESS;
++ char entity[16];
++ int *entity_uc;
++ int local_uc, local_entity_uc;
++
++ if (!arm_state)
++ goto out;
++
++ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__);
++
++ if (use_type == USE_TYPE_VCHIQ) {
++ sprintf(entity, "VCHIQ: ");
++ entity_uc = &arm_state->peer_use_count;
++ } else if (service) {
++ sprintf(entity, "%c%c%c%c:%03d",
++ VCHIQ_FOURCC_AS_4CHARS(service->base.fourcc),
++ service->client_id);
++ entity_uc = &service->service_use_count;
++ } else {
++ vchiq_log_error(vchiq_susp_log_level, "%s null service "
++ "ptr", __func__);
++ ret = VCHIQ_ERROR;
++ goto out;
++ }
++
++ write_lock_bh(&arm_state->susp_res_lock);
++ while (arm_state->resume_blocked) {
++ /* If we call 'use' while force suspend is waiting for suspend,
++ * then we're about to block the thread which the force is
++ * waiting to complete, so we're bound to just time out. In this
++ * case, set the suspend state such that the wait will be
++ * canceled, so we can complete as quickly as possible. */
++ if (arm_state->resume_blocked && arm_state->vc_suspend_state ==
++ VC_SUSPEND_IDLE) {
++ set_suspend_state(arm_state, VC_SUSPEND_FORCE_CANCELED);
++ break;
++ }
++ /* If suspend is already in progress then we need to block */
++ if (!try_wait_for_completion(&arm_state->resume_blocker)) {
++ /* Indicate that there are threads waiting on the resume
++ * blocker. These need to be allowed to complete before
++ * a _second_ call to force suspend can complete,
++ * otherwise low priority threads might never actually
++ * continue */
++ arm_state->blocked_count++;
++ write_unlock_bh(&arm_state->susp_res_lock);
++ vchiq_log_info(vchiq_susp_log_level, "%s %s resume "
++ "blocked - waiting...", __func__, entity);
++ if (wait_for_completion_killable(
++ &arm_state->resume_blocker) != 0) {
++ vchiq_log_error(vchiq_susp_log_level, "%s %s "
++ "wait for resume blocker interrupted",
++ __func__, entity);
++ ret = VCHIQ_ERROR;
++ write_lock_bh(&arm_state->susp_res_lock);
++ arm_state->blocked_count--;
++ write_unlock_bh(&arm_state->susp_res_lock);
++ goto out;
++ }
++ vchiq_log_info(vchiq_susp_log_level, "%s %s resume "
++ "unblocked", __func__, entity);
++ write_lock_bh(&arm_state->susp_res_lock);
++ if (--arm_state->blocked_count == 0)
++ complete_all(&arm_state->blocked_blocker);
++ }
++ }
++
++ stop_suspend_timer(arm_state);
++
++ local_uc = ++arm_state->videocore_use_count;
++ local_entity_uc = ++(*entity_uc);
++
++ /* If there's a pending request which hasn't yet been serviced then
++ * just clear it. If we're past VC_SUSPEND_REQUESTED state then
++ * vc_resume_complete will block until we either resume or fail to
++ * suspend */
++ if (arm_state->vc_suspend_state <= VC_SUSPEND_REQUESTED)
++ set_suspend_state(arm_state, VC_SUSPEND_IDLE);
++
++ if ((use_type != USE_TYPE_SERVICE_NO_RESUME) && need_resume(state)) {
++ set_resume_state(arm_state, VC_RESUME_REQUESTED);
++ vchiq_log_info(vchiq_susp_log_level,
++ "%s %s count %d, state count %d",
++ __func__, entity, local_entity_uc, local_uc);
++ request_poll(state, NULL, 0);
++ } else
++ vchiq_log_trace(vchiq_susp_log_level,
++ "%s %s count %d, state count %d",
++ __func__, entity, *entity_uc, local_uc);
++
++
++ write_unlock_bh(&arm_state->susp_res_lock);
++
++ /* Completion is in a done state when we're not suspended, so this won't
++ * block for the non-suspended case. */
++ if (!try_wait_for_completion(&arm_state->vc_resume_complete)) {
++ vchiq_log_info(vchiq_susp_log_level, "%s %s wait for resume",
++ __func__, entity);
++ if (wait_for_completion_killable(
++ &arm_state->vc_resume_complete) != 0) {
++ vchiq_log_error(vchiq_susp_log_level, "%s %s wait for "
++ "resume interrupted", __func__, entity);
++ ret = VCHIQ_ERROR;
++ goto out;
++ }
++ vchiq_log_info(vchiq_susp_log_level, "%s %s resumed", __func__,
++ entity);
++ }
++
++ if (ret == VCHIQ_SUCCESS) {
++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS;
++ long ack_cnt = atomic_xchg(&arm_state->ka_use_ack_count, 0);
++ while (ack_cnt && (status == VCHIQ_SUCCESS)) {
++ /* Send the use notify to videocore */
++ status = vchiq_send_remote_use_active(state);
++ if (status == VCHIQ_SUCCESS)
++ ack_cnt--;
++ else
++ atomic_add(ack_cnt,
++ &arm_state->ka_use_ack_count);
++ }
++ }
++
++out:
++ vchiq_log_trace(vchiq_susp_log_level, "%s exit %d", __func__, ret);
++ return ret;
++}
++
++VCHIQ_STATUS_T
++vchiq_release_internal(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service)
++{
++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state);
++ VCHIQ_STATUS_T ret = VCHIQ_SUCCESS;
++ char entity[16];
++ int *entity_uc;
++ int local_uc, local_entity_uc;
++
++ if (!arm_state)
++ goto out;
++
++ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__);
++
++ if (service) {
++ sprintf(entity, "%c%c%c%c:%03d",
++ VCHIQ_FOURCC_AS_4CHARS(service->base.fourcc),
++ service->client_id);
++ entity_uc = &service->service_use_count;
++ } else {
++ sprintf(entity, "PEER: ");
++ entity_uc = &arm_state->peer_use_count;
++ }
++
++ write_lock_bh(&arm_state->susp_res_lock);
++ if (!arm_state->videocore_use_count || !(*entity_uc)) {
++ /* Don't use BUG_ON - don't allow user thread to crash kernel */
++ WARN_ON(!arm_state->videocore_use_count);
++ WARN_ON(!(*entity_uc));
++ ret = VCHIQ_ERROR;
++ goto unlock;
++ }
++ local_uc = --arm_state->videocore_use_count;
++ local_entity_uc = --(*entity_uc);
++
++ if (!vchiq_videocore_wanted(state)) {
++ if (vchiq_platform_use_suspend_timer() &&
++ !arm_state->resume_blocked) {
++ /* Only use the timer if we're not trying to force
++ * suspend (=> resume_blocked) */
++ start_suspend_timer(arm_state);
++ } else {
++ vchiq_log_info(vchiq_susp_log_level,
++ "%s %s count %d, state count %d - suspending",
++ __func__, entity, *entity_uc,
++ arm_state->videocore_use_count);
++ vchiq_arm_vcsuspend(state);
++ }
++ } else
++ vchiq_log_trace(vchiq_susp_log_level,
++ "%s %s count %d, state count %d",
++ __func__, entity, *entity_uc,
++ arm_state->videocore_use_count);
++
++unlock:
++ write_unlock_bh(&arm_state->susp_res_lock);
++
++out:
++ vchiq_log_trace(vchiq_susp_log_level, "%s exit %d", __func__, ret);
++ return ret;
++}
++
++void
++vchiq_on_remote_use(VCHIQ_STATE_T *state)
++{
++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state);
++ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__);
++ atomic_inc(&arm_state->ka_use_count);
++ complete(&arm_state->ka_evt);
++}
++
++void
++vchiq_on_remote_release(VCHIQ_STATE_T *state)
++{
++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state);
++ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__);
++ atomic_inc(&arm_state->ka_release_count);
++ complete(&arm_state->ka_evt);
++}
++
++VCHIQ_STATUS_T
++vchiq_use_service_internal(VCHIQ_SERVICE_T *service)
++{
++ return vchiq_use_internal(service->state, service, USE_TYPE_SERVICE);
++}
++
++VCHIQ_STATUS_T
++vchiq_release_service_internal(VCHIQ_SERVICE_T *service)
++{
++ return vchiq_release_internal(service->state, service);
++}
++
++VCHIQ_DEBUGFS_NODE_T *
++vchiq_instance_get_debugfs_node(VCHIQ_INSTANCE_T instance)
++{
++ return &instance->debugfs_node;
++}
++
++int
++vchiq_instance_get_use_count(VCHIQ_INSTANCE_T instance)
++{
++ VCHIQ_SERVICE_T *service;
++ int use_count = 0, i;
++ i = 0;
++ while ((service = next_service_by_instance(instance->state,
++ instance, &i)) != NULL) {
++ use_count += service->service_use_count;
++ unlock_service(service);
++ }
++ return use_count;
++}
++
++int
++vchiq_instance_get_pid(VCHIQ_INSTANCE_T instance)
++{
++ return instance->pid;
++}
++
++int
++vchiq_instance_get_trace(VCHIQ_INSTANCE_T instance)
++{
++ return instance->trace;
++}
++
++void
++vchiq_instance_set_trace(VCHIQ_INSTANCE_T instance, int trace)
++{
++ VCHIQ_SERVICE_T *service;
++ int i;
++ i = 0;
++ while ((service = next_service_by_instance(instance->state,
++ instance, &i)) != NULL) {
++ service->trace = trace;
++ unlock_service(service);
++ }
++ instance->trace = (trace != 0);
++}
++
++static void suspend_timer_callback(unsigned long context)
++{
++ VCHIQ_STATE_T *state = (VCHIQ_STATE_T *)context;
++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state);
++ if (!arm_state)
++ goto out;
++ vchiq_log_info(vchiq_susp_log_level,
++ "%s - suspend timer expired - check suspend", __func__);
++ vchiq_check_suspend(state);
++out:
++ return;
++}
++
++VCHIQ_STATUS_T
++vchiq_use_service_no_resume(VCHIQ_SERVICE_HANDLE_T handle)
++{
++ VCHIQ_STATUS_T ret = VCHIQ_ERROR;
++ VCHIQ_SERVICE_T *service = find_service_by_handle(handle);
++ if (service) {
++ ret = vchiq_use_internal(service->state, service,
++ USE_TYPE_SERVICE_NO_RESUME);
++ unlock_service(service);
++ }
++ return ret;
++}
++
++VCHIQ_STATUS_T
++vchiq_use_service(VCHIQ_SERVICE_HANDLE_T handle)
++{
++ VCHIQ_STATUS_T ret = VCHIQ_ERROR;
++ VCHIQ_SERVICE_T *service = find_service_by_handle(handle);
++ if (service) {
++ ret = vchiq_use_internal(service->state, service,
++ USE_TYPE_SERVICE);
++ unlock_service(service);
++ }
++ return ret;
++}
++
++VCHIQ_STATUS_T
++vchiq_release_service(VCHIQ_SERVICE_HANDLE_T handle)
++{
++ VCHIQ_STATUS_T ret = VCHIQ_ERROR;
++ VCHIQ_SERVICE_T *service = find_service_by_handle(handle);
++ if (service) {
++ ret = vchiq_release_internal(service->state, service);
++ unlock_service(service);
++ }
++ return ret;
++}
++
++void
++vchiq_dump_service_use_state(VCHIQ_STATE_T *state)
++{
++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state);
++ int i, j = 0;
++ /* Only dump 64 services */
++ static const int local_max_services = 64;
++ /* If there's more than 64 services, only dump ones with
++ * non-zero counts */
++ int only_nonzero = 0;
++ static const char *nz = "<-- preventing suspend";
++
++ enum vc_suspend_status vc_suspend_state;
++ enum vc_resume_status vc_resume_state;
++ int peer_count;
++ int vc_use_count;
++ int active_services;
++ struct service_data_struct {
++ int fourcc;
++ int clientid;
++ int use_count;
++ } service_data[local_max_services];
++
++ if (!arm_state)
++ return;
++
++ read_lock_bh(&arm_state->susp_res_lock);
++ vc_suspend_state = arm_state->vc_suspend_state;
++ vc_resume_state = arm_state->vc_resume_state;
++ peer_count = arm_state->peer_use_count;
++ vc_use_count = arm_state->videocore_use_count;
++ active_services = state->unused_service;
++ if (active_services > local_max_services)
++ only_nonzero = 1;
++
++ for (i = 0; (i < active_services) && (j < local_max_services); i++) {
++ VCHIQ_SERVICE_T *service_ptr = state->services[i];
++ if (!service_ptr)
++ continue;
++
++ if (only_nonzero && !service_ptr->service_use_count)
++ continue;
++
++ if (service_ptr->srvstate != VCHIQ_SRVSTATE_FREE) {
++ service_data[j].fourcc = service_ptr->base.fourcc;
++ service_data[j].clientid = service_ptr->client_id;
++ service_data[j++].use_count = service_ptr->
++ service_use_count;
++ }
++ }
++
++ read_unlock_bh(&arm_state->susp_res_lock);
++
++ vchiq_log_warning(vchiq_susp_log_level,
++ "-- Videcore suspend state: %s --",
++ suspend_state_names[vc_suspend_state + VC_SUSPEND_NUM_OFFSET]);
++ vchiq_log_warning(vchiq_susp_log_level,
++ "-- Videcore resume state: %s --",
++ resume_state_names[vc_resume_state + VC_RESUME_NUM_OFFSET]);
++
++ if (only_nonzero)
++ vchiq_log_warning(vchiq_susp_log_level, "Too many active "
++ "services (%d). Only dumping up to first %d services "
++ "with non-zero use-count", active_services,
++ local_max_services);
++
++ for (i = 0; i < j; i++) {
++ vchiq_log_warning(vchiq_susp_log_level,
++ "----- %c%c%c%c:%d service count %d %s",
++ VCHIQ_FOURCC_AS_4CHARS(service_data[i].fourcc),
++ service_data[i].clientid,
++ service_data[i].use_count,
++ service_data[i].use_count ? nz : "");
++ }
++ vchiq_log_warning(vchiq_susp_log_level,
++ "----- VCHIQ use count count %d", peer_count);
++ vchiq_log_warning(vchiq_susp_log_level,
++ "--- Overall vchiq instance use count %d", vc_use_count);
++
++ vchiq_dump_platform_use_state(state);
++}
++
++VCHIQ_STATUS_T
++vchiq_check_service(VCHIQ_SERVICE_T *service)
++{
++ VCHIQ_ARM_STATE_T *arm_state;
++ VCHIQ_STATUS_T ret = VCHIQ_ERROR;
++
++ if (!service || !service->state)
++ goto out;
++
++ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__);
++
++ arm_state = vchiq_platform_get_arm_state(service->state);
++
++ read_lock_bh(&arm_state->susp_res_lock);
++ if (service->service_use_count)
++ ret = VCHIQ_SUCCESS;
++ read_unlock_bh(&arm_state->susp_res_lock);
++
++ if (ret == VCHIQ_ERROR) {
++ vchiq_log_error(vchiq_susp_log_level,
++ "%s ERROR - %c%c%c%c:%d service count %d, "
++ "state count %d, videocore suspend state %s", __func__,
++ VCHIQ_FOURCC_AS_4CHARS(service->base.fourcc),
++ service->client_id, service->service_use_count,
++ arm_state->videocore_use_count,
++ suspend_state_names[arm_state->vc_suspend_state +
++ VC_SUSPEND_NUM_OFFSET]);
++ vchiq_dump_service_use_state(service->state);
++ }
++out:
++ return ret;
++}
++
++/* stub functions */
++void vchiq_on_remote_use_active(VCHIQ_STATE_T *state)
++{
++ (void)state;
++}
++
++void vchiq_platform_conn_state_changed(VCHIQ_STATE_T *state,
++ VCHIQ_CONNSTATE_T oldstate, VCHIQ_CONNSTATE_T newstate)
++{
++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state);
++ vchiq_log_info(vchiq_susp_log_level, "%d: %s->%s", state->id,
++ get_conn_state_name(oldstate), get_conn_state_name(newstate));
++ if (state->conn_state == VCHIQ_CONNSTATE_CONNECTED) {
++ write_lock_bh(&arm_state->susp_res_lock);
++ if (!arm_state->first_connect) {
++ char threadname[10];
++ arm_state->first_connect = 1;
++ write_unlock_bh(&arm_state->susp_res_lock);
++ snprintf(threadname, sizeof(threadname), "VCHIQka-%d",
++ state->id);
++ arm_state->ka_thread = kthread_create(
++ &vchiq_keepalive_thread_func,
++ (void *)state,
++ threadname);
++ if (arm_state->ka_thread == NULL) {
++ vchiq_log_error(vchiq_susp_log_level,
++ "vchiq: FATAL: couldn't create thread %s",
++ threadname);
++ } else {
++ wake_up_process(arm_state->ka_thread);
++ }
++ } else
++ write_unlock_bh(&arm_state->susp_res_lock);
++ }
++}
++
++static int vchiq_probe(struct platform_device *pdev)
++{
++ struct device_node *fw_node;
++ struct rpi_firmware *fw;
++ int err;
++ void *ptr_err;
++
++ fw_node = of_parse_phandle(pdev->dev.of_node, "firmware", 0);
++/* Remove comment when booting without Device Tree is no longer supported
++ if (!fw_node) {
++ dev_err(&pdev->dev, "Missing firmware node\n");
++ return -ENOENT;
++ }
++*/
++ fw = rpi_firmware_get(fw_node);
++ if (!fw)
++ return -EPROBE_DEFER;
++
++ platform_set_drvdata(pdev, fw);
++
++ /* create debugfs entries */
++ err = vchiq_debugfs_init();
++ if (err != 0)
++ goto failed_debugfs_init;
++
++ err = alloc_chrdev_region(&vchiq_devid, VCHIQ_MINOR, 1, DEVICE_NAME);
++ if (err != 0) {
++ vchiq_log_error(vchiq_arm_log_level,
++ "Unable to allocate device number");
++ goto failed_alloc_chrdev;
++ }
++ cdev_init(&vchiq_cdev, &vchiq_fops);
++ vchiq_cdev.owner = THIS_MODULE;
++ err = cdev_add(&vchiq_cdev, vchiq_devid, 1);
++ if (err != 0) {
++ vchiq_log_error(vchiq_arm_log_level,
++ "Unable to register device");
++ goto failed_cdev_add;
++ }
++
++ /* create sysfs entries */
++ vchiq_class = class_create(THIS_MODULE, DEVICE_NAME);
++ ptr_err = vchiq_class;
++ if (IS_ERR(ptr_err))
++ goto failed_class_create;
++
++ vchiq_dev = device_create(vchiq_class, NULL,
++ vchiq_devid, NULL, "vchiq");
++ ptr_err = vchiq_dev;
++ if (IS_ERR(ptr_err))
++ goto failed_device_create;
++
++ err = vchiq_platform_init(pdev, &g_state);
++ if (err != 0)
++ goto failed_platform_init;
++
++ vchiq_log_info(vchiq_arm_log_level,
++ "vchiq: initialised - version %d (min %d), device %d.%d",
++ VCHIQ_VERSION, VCHIQ_VERSION_MIN,
++ MAJOR(vchiq_devid), MINOR(vchiq_devid));
++
++ return 0;
++
++failed_platform_init:
++ device_destroy(vchiq_class, vchiq_devid);
++failed_device_create:
++ class_destroy(vchiq_class);
++failed_class_create:
++ cdev_del(&vchiq_cdev);
++ err = PTR_ERR(ptr_err);
++failed_cdev_add:
++ unregister_chrdev_region(vchiq_devid, 1);
++failed_alloc_chrdev:
++ vchiq_debugfs_deinit();
++failed_debugfs_init:
++ vchiq_log_warning(vchiq_arm_log_level, "could not load vchiq");
++ return err;
++}
++
++static int vchiq_remove(struct platform_device *pdev)
++{
++ device_destroy(vchiq_class, vchiq_devid);
++ class_destroy(vchiq_class);
++ cdev_del(&vchiq_cdev);
++ unregister_chrdev_region(vchiq_devid, 1);
++
++ return 0;
++}
++
++static const struct of_device_id vchiq_of_match[] = {
++ { .compatible = "brcm,bcm2835-vchiq", },
++ {},
++};
++MODULE_DEVICE_TABLE(of, vchiq_of_match);
++
++static struct platform_driver vchiq_driver = {
++ .driver = {
++ .name = "bcm2835_vchiq",
++ .owner = THIS_MODULE,
++ .of_match_table = vchiq_of_match,
++ },
++ .probe = vchiq_probe,
++ .remove = vchiq_remove,
++};
++module_platform_driver(vchiq_driver);
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Broadcom Corporation");
+diff -Nur linux-4.1.3/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.h linux-xbian-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.h
+--- linux-4.1.3/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.h 2015-07-28 01:20:58.285725306 +0200
+@@ -0,0 +1,220 @@
++/**
++ * Copyright (c) 2014 Raspberry Pi (Trading) Ltd. All rights reserved.
++ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ * 1. Redistributions of source code must retain the above copyright
++ * notice, this list of conditions, and the following disclaimer,
++ * without modification.
++ * 2. Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * 3. The names of the above-listed copyright holders may not be used
++ * to endorse or promote products derived from this software without
++ * specific prior written permission.
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") version 2, as published by the Free
++ * Software Foundation.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#ifndef VCHIQ_ARM_H
++#define VCHIQ_ARM_H
++
++#include <linux/mutex.h>
++#include <linux/platform_device.h>
++#include <linux/semaphore.h>
++#include <linux/atomic.h>
++#include "vchiq_core.h"
++#include "vchiq_debugfs.h"
++
++
++enum vc_suspend_status {
++ VC_SUSPEND_FORCE_CANCELED = -3, /* Force suspend canceled, too busy */
++ VC_SUSPEND_REJECTED = -2, /* Videocore rejected suspend request */
++ VC_SUSPEND_FAILED = -1, /* Videocore suspend failed */
++ VC_SUSPEND_IDLE = 0, /* VC active, no suspend actions */
++ VC_SUSPEND_REQUESTED, /* User has requested suspend */
++ VC_SUSPEND_IN_PROGRESS, /* Slot handler has recvd suspend request */
++ VC_SUSPEND_SUSPENDED /* Videocore suspend succeeded */
++};
++
++enum vc_resume_status {
++ VC_RESUME_FAILED = -1, /* Videocore resume failed */
++ VC_RESUME_IDLE = 0, /* VC suspended, no resume actions */
++ VC_RESUME_REQUESTED, /* User has requested resume */
++ VC_RESUME_IN_PROGRESS, /* Slot handler has received resume request */
++ VC_RESUME_RESUMED /* Videocore resumed successfully (active) */
++};
++
++
++enum USE_TYPE_E {
++ USE_TYPE_SERVICE,
++ USE_TYPE_SERVICE_NO_RESUME,
++ USE_TYPE_VCHIQ
++};
++
++
++
++typedef struct vchiq_arm_state_struct {
++ /* Keepalive-related data */
++ struct task_struct *ka_thread;
++ struct completion ka_evt;
++ atomic_t ka_use_count;
++ atomic_t ka_use_ack_count;
++ atomic_t ka_release_count;
++
++ struct completion vc_suspend_complete;
++ struct completion vc_resume_complete;
++
++ rwlock_t susp_res_lock;
++ enum vc_suspend_status vc_suspend_state;
++ enum vc_resume_status vc_resume_state;
++
++ unsigned int wake_address;
++
++ struct timer_list suspend_timer;
++ int suspend_timer_timeout;
++ int suspend_timer_running;
++
++ /* Global use count for videocore.
++ ** This is equal to the sum of the use counts for all services. When
++ ** this hits zero the videocore suspend procedure will be initiated.
++ */
++ int videocore_use_count;
++
++ /* Use count to track requests from videocore peer.
++ ** This use count is not associated with a service, so needs to be
++ ** tracked separately with the state.
++ */
++ int peer_use_count;
++
++ /* Flag to indicate whether resume is blocked. This happens when the
++ ** ARM is suspending
++ */
++ struct completion resume_blocker;
++ int resume_blocked;
++ struct completion blocked_blocker;
++ int blocked_count;
++
++ int autosuspend_override;
++
++ /* Flag to indicate that the first vchiq connect has made it through.
++ ** This means that both sides should be fully ready, and we should
++ ** be able to suspend after this point.
++ */
++ int first_connect;
++
++ unsigned long long suspend_start_time;
++ unsigned long long sleep_start_time;
++ unsigned long long resume_start_time;
++ unsigned long long last_wake_time;
++
++} VCHIQ_ARM_STATE_T;
++
++extern int vchiq_arm_log_level;
++extern int vchiq_susp_log_level;
++
++int vchiq_platform_init(struct platform_device *pdev, VCHIQ_STATE_T *state);
++
++extern VCHIQ_STATE_T *
++vchiq_get_state(void);
++
++extern VCHIQ_STATUS_T
++vchiq_arm_vcsuspend(VCHIQ_STATE_T *state);
++
++extern VCHIQ_STATUS_T
++vchiq_arm_force_suspend(VCHIQ_STATE_T *state);
++
++extern int
++vchiq_arm_allow_resume(VCHIQ_STATE_T *state);
++
++extern VCHIQ_STATUS_T
++vchiq_arm_vcresume(VCHIQ_STATE_T *state);
++
++extern VCHIQ_STATUS_T
++vchiq_arm_init_state(VCHIQ_STATE_T *state, VCHIQ_ARM_STATE_T *arm_state);
++
++extern int
++vchiq_check_resume(VCHIQ_STATE_T *state);
++
++extern void
++vchiq_check_suspend(VCHIQ_STATE_T *state);
++ VCHIQ_STATUS_T
++vchiq_use_service(VCHIQ_SERVICE_HANDLE_T handle);
++
++extern VCHIQ_STATUS_T
++vchiq_release_service(VCHIQ_SERVICE_HANDLE_T handle);
++
++extern VCHIQ_STATUS_T
++vchiq_check_service(VCHIQ_SERVICE_T *service);
++
++extern VCHIQ_STATUS_T
++vchiq_platform_suspend(VCHIQ_STATE_T *state);
++
++extern int
++vchiq_platform_videocore_wanted(VCHIQ_STATE_T *state);
++
++extern int
++vchiq_platform_use_suspend_timer(void);
++
++extern void
++vchiq_dump_platform_use_state(VCHIQ_STATE_T *state);
++
++extern void
++vchiq_dump_service_use_state(VCHIQ_STATE_T *state);
++
++extern VCHIQ_ARM_STATE_T*
++vchiq_platform_get_arm_state(VCHIQ_STATE_T *state);
++
++extern int
++vchiq_videocore_wanted(VCHIQ_STATE_T *state);
++
++extern VCHIQ_STATUS_T
++vchiq_use_internal(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service,
++ enum USE_TYPE_E use_type);
++extern VCHIQ_STATUS_T
++vchiq_release_internal(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service);
++
++extern VCHIQ_DEBUGFS_NODE_T *
++vchiq_instance_get_debugfs_node(VCHIQ_INSTANCE_T instance);
++
++extern int
++vchiq_instance_get_use_count(VCHIQ_INSTANCE_T instance);
++
++extern int
++vchiq_instance_get_pid(VCHIQ_INSTANCE_T instance);
++
++extern int
++vchiq_instance_get_trace(VCHIQ_INSTANCE_T instance);
++
++extern void
++vchiq_instance_set_trace(VCHIQ_INSTANCE_T instance, int trace);
++
++extern void
++set_suspend_state(VCHIQ_ARM_STATE_T *arm_state,
++ enum vc_suspend_status new_state);
++
++extern void
++set_resume_state(VCHIQ_ARM_STATE_T *arm_state,
++ enum vc_resume_status new_state);
++
++extern void
++start_suspend_timer(VCHIQ_ARM_STATE_T *arm_state);
++
++
++#endif /* VCHIQ_ARM_H */
+diff -Nur linux-4.1.3/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_build_info.h linux-xbian-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_build_info.h
+--- linux-4.1.3/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_build_info.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_build_info.h 2015-07-28 01:20:58.285725306 +0200
+@@ -0,0 +1,37 @@
++/**
++ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ * 1. Redistributions of source code must retain the above copyright
++ * notice, this list of conditions, and the following disclaimer,
++ * without modification.
++ * 2. Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * 3. The names of the above-listed copyright holders may not be used
++ * to endorse or promote products derived from this software without
++ * specific prior written permission.
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") version 2, as published by the Free
++ * Software Foundation.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++const char *vchiq_get_build_hostname(void);
++const char *vchiq_get_build_version(void);
++const char *vchiq_get_build_time(void);
++const char *vchiq_get_build_date(void);
+diff -Nur linux-4.1.3/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_cfg.h linux-xbian-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_cfg.h
+--- linux-4.1.3/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_cfg.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_cfg.h 2015-07-28 01:20:58.285725306 +0200
+@@ -0,0 +1,69 @@
++/**
++ * Copyright (c) 2010-2014 Broadcom. All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ * 1. Redistributions of source code must retain the above copyright
++ * notice, this list of conditions, and the following disclaimer,
++ * without modification.
++ * 2. Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * 3. The names of the above-listed copyright holders may not be used
++ * to endorse or promote products derived from this software without
++ * specific prior written permission.
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") version 2, as published by the Free
++ * Software Foundation.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#ifndef VCHIQ_CFG_H
++#define VCHIQ_CFG_H
++
++#define VCHIQ_MAGIC VCHIQ_MAKE_FOURCC('V', 'C', 'H', 'I')
++/* The version of VCHIQ - change with any non-trivial change */
++#define VCHIQ_VERSION 8
++/* The minimum compatible version - update to match VCHIQ_VERSION with any
++** incompatible change */
++#define VCHIQ_VERSION_MIN 3
++
++/* The version that introduced the VCHIQ_IOC_LIB_VERSION ioctl */
++#define VCHIQ_VERSION_LIB_VERSION 7
++
++/* The version that introduced the VCHIQ_IOC_CLOSE_DELIVERED ioctl */
++#define VCHIQ_VERSION_CLOSE_DELIVERED 7
++
++/* The version that made it safe to use SYNCHRONOUS mode */
++#define VCHIQ_VERSION_SYNCHRONOUS_MODE 8
++
++#define VCHIQ_MAX_STATES 1
++#define VCHIQ_MAX_SERVICES 4096
++#define VCHIQ_MAX_SLOTS 128
++#define VCHIQ_MAX_SLOTS_PER_SIDE 64
++
++#define VCHIQ_NUM_CURRENT_BULKS 32
++#define VCHIQ_NUM_SERVICE_BULKS 4
++
++#ifndef VCHIQ_ENABLE_DEBUG
++#define VCHIQ_ENABLE_DEBUG 1
++#endif
++
++#ifndef VCHIQ_ENABLE_STATS
++#define VCHIQ_ENABLE_STATS 1
++#endif
++
++#endif /* VCHIQ_CFG_H */
+diff -Nur linux-4.1.3/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_connected.c linux-xbian-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_connected.c
+--- linux-4.1.3/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_connected.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_connected.c 2015-07-28 01:20:58.285725306 +0200
+@@ -0,0 +1,120 @@
++/**
++ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ * 1. Redistributions of source code must retain the above copyright
++ * notice, this list of conditions, and the following disclaimer,
++ * without modification.
++ * 2. Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * 3. The names of the above-listed copyright holders may not be used
++ * to endorse or promote products derived from this software without
++ * specific prior written permission.
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") version 2, as published by the Free
++ * Software Foundation.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#include "vchiq_connected.h"
++#include "vchiq_core.h"
++#include "vchiq_killable.h"
++#include <linux/module.h>
++#include <linux/mutex.h>
++
++#define MAX_CALLBACKS 10
++
++static int g_connected;
++static int g_num_deferred_callbacks;
++static VCHIQ_CONNECTED_CALLBACK_T g_deferred_callback[MAX_CALLBACKS];
++static int g_once_init;
++static struct mutex g_connected_mutex;
++
++/****************************************************************************
++*
++* Function to initialize our lock.
++*
++***************************************************************************/
++
++static void connected_init(void)
++{
++ if (!g_once_init) {
++ mutex_init(&g_connected_mutex);
++ g_once_init = 1;
++ }
++}
++
++/****************************************************************************
++*
++* This function is used to defer initialization until the vchiq stack is
++* initialized. If the stack is already initialized, then the callback will
++* be made immediately, otherwise it will be deferred until
++* vchiq_call_connected_callbacks is called.
++*
++***************************************************************************/
++
++void vchiq_add_connected_callback(VCHIQ_CONNECTED_CALLBACK_T callback)
++{
++ connected_init();
++
++ if (mutex_lock_interruptible(&g_connected_mutex) != 0)
++ return;
++
++ if (g_connected)
++ /* We're already connected. Call the callback immediately. */
++
++ callback();
++ else {
++ if (g_num_deferred_callbacks >= MAX_CALLBACKS)
++ vchiq_log_error(vchiq_core_log_level,
++ "There already %d callback registered - "
++ "please increase MAX_CALLBACKS",
++ g_num_deferred_callbacks);
++ else {
++ g_deferred_callback[g_num_deferred_callbacks] =
++ callback;
++ g_num_deferred_callbacks++;
++ }
++ }
++ mutex_unlock(&g_connected_mutex);
++}
++
++/****************************************************************************
++*
++* This function is called by the vchiq stack once it has been connected to
++* the videocore and clients can start to use the stack.
++*
++***************************************************************************/
++
++void vchiq_call_connected_callbacks(void)
++{
++ int i;
++
++ connected_init();
++
++ if (mutex_lock_interruptible(&g_connected_mutex) != 0)
++ return;
++
++ for (i = 0; i < g_num_deferred_callbacks; i++)
++ g_deferred_callback[i]();
++
++ g_num_deferred_callbacks = 0;
++ g_connected = 1;
++ mutex_unlock(&g_connected_mutex);
++}
++EXPORT_SYMBOL(vchiq_add_connected_callback);
+diff -Nur linux-4.1.3/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_connected.h linux-xbian-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_connected.h
+--- linux-4.1.3/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_connected.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_connected.h 2015-07-28 01:20:58.285725306 +0200
+@@ -0,0 +1,50 @@
++/**
++ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ * 1. Redistributions of source code must retain the above copyright
++ * notice, this list of conditions, and the following disclaimer,
++ * without modification.
++ * 2. Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * 3. The names of the above-listed copyright holders may not be used
++ * to endorse or promote products derived from this software without
++ * specific prior written permission.
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") version 2, as published by the Free
++ * Software Foundation.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#ifndef VCHIQ_CONNECTED_H
++#define VCHIQ_CONNECTED_H
++
++/* ---- Include Files ----------------------------------------------------- */
++
++/* ---- Constants and Types ---------------------------------------------- */
++
++typedef void (*VCHIQ_CONNECTED_CALLBACK_T)(void);
++
++/* ---- Variable Externs ------------------------------------------------- */
++
++/* ---- Function Prototypes ---------------------------------------------- */
++
++void vchiq_add_connected_callback(VCHIQ_CONNECTED_CALLBACK_T callback);
++void vchiq_call_connected_callbacks(void);
++
++#endif /* VCHIQ_CONNECTED_H */
+diff -Nur linux-4.1.3/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.c linux-xbian-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.c
+--- linux-4.1.3/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.c 2015-07-28 01:20:58.285725306 +0200
+@@ -0,0 +1,3934 @@
++/**
++ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ * 1. Redistributions of source code must retain the above copyright
++ * notice, this list of conditions, and the following disclaimer,
++ * without modification.
++ * 2. Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * 3. The names of the above-listed copyright holders may not be used
++ * to endorse or promote products derived from this software without
++ * specific prior written permission.
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") version 2, as published by the Free
++ * Software Foundation.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#include "vchiq_core.h"
++#include "vchiq_killable.h"
++
++#define VCHIQ_SLOT_HANDLER_STACK 8192
++
++#define HANDLE_STATE_SHIFT 12
++
++#define SLOT_INFO_FROM_INDEX(state, index) (state->slot_info + (index))
++#define SLOT_DATA_FROM_INDEX(state, index) (state->slot_data + (index))
++#define SLOT_INDEX_FROM_DATA(state, data) \
++ (((unsigned int)((char *)data - (char *)state->slot_data)) / \
++ VCHIQ_SLOT_SIZE)
++#define SLOT_INDEX_FROM_INFO(state, info) \
++ ((unsigned int)(info - state->slot_info))
++#define SLOT_QUEUE_INDEX_FROM_POS(pos) \
++ ((int)((unsigned int)(pos) / VCHIQ_SLOT_SIZE))
++
++#define BULK_INDEX(x) (x & (VCHIQ_NUM_SERVICE_BULKS - 1))
++
++#define SRVTRACE_LEVEL(srv) \
++ (((srv) && (srv)->trace) ? VCHIQ_LOG_TRACE : vchiq_core_msg_log_level)
++#define SRVTRACE_ENABLED(srv, lev) \
++ (((srv) && (srv)->trace) || (vchiq_core_msg_log_level >= (lev)))
++
++struct vchiq_open_payload {
++ int fourcc;
++ int client_id;
++ short version;
++ short version_min;
++};
++
++struct vchiq_openack_payload {
++ short version;
++};
++
++enum
++{
++ QMFLAGS_IS_BLOCKING = (1 << 0),
++ QMFLAGS_NO_MUTEX_LOCK = (1 << 1),
++ QMFLAGS_NO_MUTEX_UNLOCK = (1 << 2)
++};
++
++/* we require this for consistency between endpoints */
++vchiq_static_assert(sizeof(VCHIQ_HEADER_T) == 8);
++vchiq_static_assert(IS_POW2(sizeof(VCHIQ_HEADER_T)));
++vchiq_static_assert(IS_POW2(VCHIQ_NUM_CURRENT_BULKS));
++vchiq_static_assert(IS_POW2(VCHIQ_NUM_SERVICE_BULKS));
++vchiq_static_assert(IS_POW2(VCHIQ_MAX_SERVICES));
++vchiq_static_assert(VCHIQ_VERSION >= VCHIQ_VERSION_MIN);
++
++/* Run time control of log level, based on KERN_XXX level. */
++int vchiq_core_log_level = VCHIQ_LOG_DEFAULT;
++int vchiq_core_msg_log_level = VCHIQ_LOG_DEFAULT;
++int vchiq_sync_log_level = VCHIQ_LOG_DEFAULT;
++
++static atomic_t pause_bulks_count = ATOMIC_INIT(0);
++
++static DEFINE_SPINLOCK(service_spinlock);
++DEFINE_SPINLOCK(bulk_waiter_spinlock);
++DEFINE_SPINLOCK(quota_spinlock);
++
++VCHIQ_STATE_T *vchiq_states[VCHIQ_MAX_STATES];
++static unsigned int handle_seq;
++
++static const char *const srvstate_names[] = {
++ "FREE",
++ "HIDDEN",
++ "LISTENING",
++ "OPENING",
++ "OPEN",
++ "OPENSYNC",
++ "CLOSESENT",
++ "CLOSERECVD",
++ "CLOSEWAIT",
++ "CLOSED"
++};
++
++static const char *const reason_names[] = {
++ "SERVICE_OPENED",
++ "SERVICE_CLOSED",
++ "MESSAGE_AVAILABLE",
++ "BULK_TRANSMIT_DONE",
++ "BULK_RECEIVE_DONE",
++ "BULK_TRANSMIT_ABORTED",
++ "BULK_RECEIVE_ABORTED"
++};
++
++static const char *const conn_state_names[] = {
++ "DISCONNECTED",
++ "CONNECTING",
++ "CONNECTED",
++ "PAUSING",
++ "PAUSE_SENT",
++ "PAUSED",
++ "RESUMING",
++ "PAUSE_TIMEOUT",
++ "RESUME_TIMEOUT"
++};
++
++
++static void
++release_message_sync(VCHIQ_STATE_T *state, VCHIQ_HEADER_T *header);
++
++static const char *msg_type_str(unsigned int msg_type)
++{
++ switch (msg_type) {
++ case VCHIQ_MSG_PADDING: return "PADDING";
++ case VCHIQ_MSG_CONNECT: return "CONNECT";
++ case VCHIQ_MSG_OPEN: return "OPEN";
++ case VCHIQ_MSG_OPENACK: return "OPENACK";
++ case VCHIQ_MSG_CLOSE: return "CLOSE";
++ case VCHIQ_MSG_DATA: return "DATA";
++ case VCHIQ_MSG_BULK_RX: return "BULK_RX";
++ case VCHIQ_MSG_BULK_TX: return "BULK_TX";
++ case VCHIQ_MSG_BULK_RX_DONE: return "BULK_RX_DONE";
++ case VCHIQ_MSG_BULK_TX_DONE: return "BULK_TX_DONE";
++ case VCHIQ_MSG_PAUSE: return "PAUSE";
++ case VCHIQ_MSG_RESUME: return "RESUME";
++ case VCHIQ_MSG_REMOTE_USE: return "REMOTE_USE";
++ case VCHIQ_MSG_REMOTE_RELEASE: return "REMOTE_RELEASE";
++ case VCHIQ_MSG_REMOTE_USE_ACTIVE: return "REMOTE_USE_ACTIVE";
++ }
++ return "???";
++}
++
++static inline void
++vchiq_set_service_state(VCHIQ_SERVICE_T *service, int newstate)
++{
++ vchiq_log_info(vchiq_core_log_level, "%d: srv:%d %s->%s",
++ service->state->id, service->localport,
++ srvstate_names[service->srvstate],
++ srvstate_names[newstate]);
++ service->srvstate = newstate;
++}
++
++VCHIQ_SERVICE_T *
++find_service_by_handle(VCHIQ_SERVICE_HANDLE_T handle)
++{
++ VCHIQ_SERVICE_T *service;
++
++ spin_lock(&service_spinlock);
++ service = handle_to_service(handle);
++ if (service && (service->srvstate != VCHIQ_SRVSTATE_FREE) &&
++ (service->handle == handle)) {
++ BUG_ON(service->ref_count == 0);
++ service->ref_count++;
++ } else
++ service = NULL;
++ spin_unlock(&service_spinlock);
++
++ if (!service)
++ vchiq_log_info(vchiq_core_log_level,
++ "Invalid service handle 0x%x", handle);
++
++ return service;
++}
++
++VCHIQ_SERVICE_T *
++find_service_by_port(VCHIQ_STATE_T *state, int localport)
++{
++ VCHIQ_SERVICE_T *service = NULL;
++ if ((unsigned int)localport <= VCHIQ_PORT_MAX) {
++ spin_lock(&service_spinlock);
++ service = state->services[localport];
++ if (service && (service->srvstate != VCHIQ_SRVSTATE_FREE)) {
++ BUG_ON(service->ref_count == 0);
++ service->ref_count++;
++ } else
++ service = NULL;
++ spin_unlock(&service_spinlock);
++ }
++
++ if (!service)
++ vchiq_log_info(vchiq_core_log_level,
++ "Invalid port %d", localport);
++
++ return service;
++}
++
++VCHIQ_SERVICE_T *
++find_service_for_instance(VCHIQ_INSTANCE_T instance,
++ VCHIQ_SERVICE_HANDLE_T handle) {
++ VCHIQ_SERVICE_T *service;
++
++ spin_lock(&service_spinlock);
++ service = handle_to_service(handle);
++ if (service && (service->srvstate != VCHIQ_SRVSTATE_FREE) &&
++ (service->handle == handle) &&
++ (service->instance == instance)) {
++ BUG_ON(service->ref_count == 0);
++ service->ref_count++;
++ } else
++ service = NULL;
++ spin_unlock(&service_spinlock);
++
++ if (!service)
++ vchiq_log_info(vchiq_core_log_level,
++ "Invalid service handle 0x%x", handle);
++
++ return service;
++}
++
++VCHIQ_SERVICE_T *
++find_closed_service_for_instance(VCHIQ_INSTANCE_T instance,
++ VCHIQ_SERVICE_HANDLE_T handle) {
++ VCHIQ_SERVICE_T *service;
++
++ spin_lock(&service_spinlock);
++ service = handle_to_service(handle);
++ if (service &&
++ ((service->srvstate == VCHIQ_SRVSTATE_FREE) ||
++ (service->srvstate == VCHIQ_SRVSTATE_CLOSED)) &&
++ (service->handle == handle) &&
++ (service->instance == instance)) {
++ BUG_ON(service->ref_count == 0);
++ service->ref_count++;
++ } else
++ service = NULL;
++ spin_unlock(&service_spinlock);
++
++ if (!service)
++ vchiq_log_info(vchiq_core_log_level,
++ "Invalid service handle 0x%x", handle);
++
++ return service;
++}
++
++VCHIQ_SERVICE_T *
++next_service_by_instance(VCHIQ_STATE_T *state, VCHIQ_INSTANCE_T instance,
++ int *pidx)
++{
++ VCHIQ_SERVICE_T *service = NULL;
++ int idx = *pidx;
++
++ spin_lock(&service_spinlock);
++ while (idx < state->unused_service) {
++ VCHIQ_SERVICE_T *srv = state->services[idx++];
++ if (srv && (srv->srvstate != VCHIQ_SRVSTATE_FREE) &&
++ (srv->instance == instance)) {
++ service = srv;
++ BUG_ON(service->ref_count == 0);
++ service->ref_count++;
++ break;
++ }
++ }
++ spin_unlock(&service_spinlock);
++
++ *pidx = idx;
++
++ return service;
++}
++
++void
++lock_service(VCHIQ_SERVICE_T *service)
++{
++ spin_lock(&service_spinlock);
++ BUG_ON(!service || (service->ref_count == 0));
++ if (service)
++ service->ref_count++;
++ spin_unlock(&service_spinlock);
++}
++
++void
++unlock_service(VCHIQ_SERVICE_T *service)
++{
++ VCHIQ_STATE_T *state = service->state;
++ spin_lock(&service_spinlock);
++ BUG_ON(!service || (service->ref_count == 0));
++ if (service && service->ref_count) {
++ service->ref_count--;
++ if (!service->ref_count) {
++ BUG_ON(service->srvstate != VCHIQ_SRVSTATE_FREE);
++ state->services[service->localport] = NULL;
++ } else
++ service = NULL;
++ }
++ spin_unlock(&service_spinlock);
++
++ if (service && service->userdata_term)
++ service->userdata_term(service->base.userdata);
++
++ kfree(service);
++}
++
++int
++vchiq_get_client_id(VCHIQ_SERVICE_HANDLE_T handle)
++{
++ VCHIQ_SERVICE_T *service = find_service_by_handle(handle);
++ int id;
++
++ id = service ? service->client_id : 0;
++ if (service)
++ unlock_service(service);
++
++ return id;
++}
++
++void *
++vchiq_get_service_userdata(VCHIQ_SERVICE_HANDLE_T handle)
++{
++ VCHIQ_SERVICE_T *service = handle_to_service(handle);
++
++ return service ? service->base.userdata : NULL;
++}
++
++int
++vchiq_get_service_fourcc(VCHIQ_SERVICE_HANDLE_T handle)
++{
++ VCHIQ_SERVICE_T *service = handle_to_service(handle);
++
++ return service ? service->base.fourcc : 0;
++}
++
++static void
++mark_service_closing_internal(VCHIQ_SERVICE_T *service, int sh_thread)
++{
++ VCHIQ_STATE_T *state = service->state;
++ VCHIQ_SERVICE_QUOTA_T *service_quota;
++
++ service->closing = 1;
++
++ /* Synchronise with other threads. */
++ mutex_lock(&state->recycle_mutex);
++ mutex_unlock(&state->recycle_mutex);
++ if (!sh_thread || (state->conn_state != VCHIQ_CONNSTATE_PAUSE_SENT)) {
++ /* If we're pausing then the slot_mutex is held until resume
++ * by the slot handler. Therefore don't try to acquire this
++ * mutex if we're the slot handler and in the pause sent state.
++ * We don't need to in this case anyway. */
++ mutex_lock(&state->slot_mutex);
++ mutex_unlock(&state->slot_mutex);
++ }
++
++ /* Unblock any sending thread. */
++ service_quota = &state->service_quotas[service->localport];
++ up(&service_quota->quota_event);
++}
++
++static void
++mark_service_closing(VCHIQ_SERVICE_T *service)
++{
++ mark_service_closing_internal(service, 0);
++}
++
++static inline VCHIQ_STATUS_T
++make_service_callback(VCHIQ_SERVICE_T *service, VCHIQ_REASON_T reason,
++ VCHIQ_HEADER_T *header, void *bulk_userdata)
++{
++ VCHIQ_STATUS_T status;
++ vchiq_log_trace(vchiq_core_log_level, "%d: callback:%d (%s, %x, %x)",
++ service->state->id, service->localport, reason_names[reason],
++ (unsigned int)header, (unsigned int)bulk_userdata);
++ status = service->base.callback(reason, header, service->handle,
++ bulk_userdata);
++ if (status == VCHIQ_ERROR) {
++ vchiq_log_warning(vchiq_core_log_level,
++ "%d: ignoring ERROR from callback to service %x",
++ service->state->id, service->handle);
++ status = VCHIQ_SUCCESS;
++ }
++ return status;
++}
++
++inline void
++vchiq_set_conn_state(VCHIQ_STATE_T *state, VCHIQ_CONNSTATE_T newstate)
++{
++ VCHIQ_CONNSTATE_T oldstate = state->conn_state;
++ vchiq_log_info(vchiq_core_log_level, "%d: %s->%s", state->id,
++ conn_state_names[oldstate],
++ conn_state_names[newstate]);
++ state->conn_state = newstate;
++ vchiq_platform_conn_state_changed(state, oldstate, newstate);
++}
++
++static inline void
++remote_event_create(REMOTE_EVENT_T *event)
++{
++ event->armed = 0;
++ /* Don't clear the 'fired' flag because it may already have been set
++ ** by the other side. */
++ sema_init(event->event, 0);
++}
++
++static inline void
++remote_event_destroy(REMOTE_EVENT_T *event)
++{
++ (void)event;
++}
++
++static inline int
++remote_event_wait(REMOTE_EVENT_T *event)
++{
++ if (!event->fired) {
++ event->armed = 1;
++ dsb();
++ if (!event->fired) {
++ if (down_interruptible(event->event) != 0) {
++ event->armed = 0;
++ return 0;
++ }
++ }
++ event->armed = 0;
++ wmb();
++ }
++
++ event->fired = 0;
++ return 1;
++}
++
++static inline void
++remote_event_signal_local(REMOTE_EVENT_T *event)
++{
++ event->armed = 0;
++ up(event->event);
++}
++
++static inline void
++remote_event_poll(REMOTE_EVENT_T *event)
++{
++ if (event->fired && event->armed)
++ remote_event_signal_local(event);
++}
++
++void
++remote_event_pollall(VCHIQ_STATE_T *state)
++{
++ remote_event_poll(&state->local->sync_trigger);
++ remote_event_poll(&state->local->sync_release);
++ remote_event_poll(&state->local->trigger);
++ remote_event_poll(&state->local->recycle);
++}
++
++/* Round up message sizes so that any space at the end of a slot is always big
++** enough for a header. This relies on header size being a power of two, which
++** has been verified earlier by a static assertion. */
++
++static inline unsigned int
++calc_stride(unsigned int size)
++{
++ /* Allow room for the header */
++ size += sizeof(VCHIQ_HEADER_T);
++
++ /* Round up */
++ return (size + sizeof(VCHIQ_HEADER_T) - 1) & ~(sizeof(VCHIQ_HEADER_T)
++ - 1);
++}
++
++/* Called by the slot handler thread */
++static VCHIQ_SERVICE_T *
++get_listening_service(VCHIQ_STATE_T *state, int fourcc)
++{
++ int i;
++
++ WARN_ON(fourcc == VCHIQ_FOURCC_INVALID);
++
++ for (i = 0; i < state->unused_service; i++) {
++ VCHIQ_SERVICE_T *service = state->services[i];
++ if (service &&
++ (service->public_fourcc == fourcc) &&
++ ((service->srvstate == VCHIQ_SRVSTATE_LISTENING) ||
++ ((service->srvstate == VCHIQ_SRVSTATE_OPEN) &&
++ (service->remoteport == VCHIQ_PORT_FREE)))) {
++ lock_service(service);
++ return service;
++ }
++ }
++
++ return NULL;
++}
++
++/* Called by the slot handler thread */
++static VCHIQ_SERVICE_T *
++get_connected_service(VCHIQ_STATE_T *state, unsigned int port)
++{
++ int i;
++ for (i = 0; i < state->unused_service; i++) {
++ VCHIQ_SERVICE_T *service = state->services[i];
++ if (service && (service->srvstate == VCHIQ_SRVSTATE_OPEN)
++ && (service->remoteport == port)) {
++ lock_service(service);
++ return service;
++ }
++ }
++ return NULL;
++}
++
++inline void
++request_poll(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service, int poll_type)
++{
++ uint32_t value;
++
++ if (service) {
++ do {
++ value = atomic_read(&service->poll_flags);
++ } while (atomic_cmpxchg(&service->poll_flags, value,
++ value | (1 << poll_type)) != value);
++
++ do {
++ value = atomic_read(&state->poll_services[
++ service->localport>>5]);
++ } while (atomic_cmpxchg(
++ &state->poll_services[service->localport>>5],
++ value, value | (1 << (service->localport & 0x1f)))
++ != value);
++ }
++
++ state->poll_needed = 1;
++ wmb();
++
++ /* ... and ensure the slot handler runs. */
++ remote_event_signal_local(&state->local->trigger);
++}
++
++/* Called from queue_message, by the slot handler and application threads,
++** with slot_mutex held */
++static VCHIQ_HEADER_T *
++reserve_space(VCHIQ_STATE_T *state, int space, int is_blocking)
++{
++ VCHIQ_SHARED_STATE_T *local = state->local;
++ int tx_pos = state->local_tx_pos;
++ int slot_space = VCHIQ_SLOT_SIZE - (tx_pos & VCHIQ_SLOT_MASK);
++
++ if (space > slot_space) {
++ VCHIQ_HEADER_T *header;
++ /* Fill the remaining space with padding */
++ WARN_ON(state->tx_data == NULL);
++ header = (VCHIQ_HEADER_T *)
++ (state->tx_data + (tx_pos & VCHIQ_SLOT_MASK));
++ header->msgid = VCHIQ_MSGID_PADDING;
++ header->size = slot_space - sizeof(VCHIQ_HEADER_T);
++
++ tx_pos += slot_space;
++ }
++
++ /* If necessary, get the next slot. */
++ if ((tx_pos & VCHIQ_SLOT_MASK) == 0) {
++ int slot_index;
++
++ /* If there is no free slot... */
++
++ if (down_trylock(&state->slot_available_event) != 0) {
++ /* ...wait for one. */
++
++ VCHIQ_STATS_INC(state, slot_stalls);
++
++ /* But first, flush through the last slot. */
++ state->local_tx_pos = tx_pos;
++ local->tx_pos = tx_pos;
++ remote_event_signal(&state->remote->trigger);
++
++ if (!is_blocking ||
++ (down_interruptible(
++ &state->slot_available_event) != 0))
++ return NULL; /* No space available */
++ }
++
++ BUG_ON(tx_pos ==
++ (state->slot_queue_available * VCHIQ_SLOT_SIZE));
++
++ slot_index = local->slot_queue[
++ SLOT_QUEUE_INDEX_FROM_POS(tx_pos) &
++ VCHIQ_SLOT_QUEUE_MASK];
++ state->tx_data =
++ (char *)SLOT_DATA_FROM_INDEX(state, slot_index);
++ }
++
++ state->local_tx_pos = tx_pos + space;
++
++ return (VCHIQ_HEADER_T *)(state->tx_data + (tx_pos & VCHIQ_SLOT_MASK));
++}
++
++/* Called by the recycle thread. */
++static void
++process_free_queue(VCHIQ_STATE_T *state)
++{
++ VCHIQ_SHARED_STATE_T *local = state->local;
++ BITSET_T service_found[BITSET_SIZE(VCHIQ_MAX_SERVICES)];
++ int slot_queue_available;
++
++ /* Use a read memory barrier to ensure that any state that may have
++ ** been modified by another thread is not masked by stale prefetched
++ ** values. */
++ rmb();
++
++ /* Find slots which have been freed by the other side, and return them
++ ** to the available queue. */
++ slot_queue_available = state->slot_queue_available;
++
++ while (slot_queue_available != local->slot_queue_recycle) {
++ unsigned int pos;
++ int slot_index = local->slot_queue[slot_queue_available++ &
++ VCHIQ_SLOT_QUEUE_MASK];
++ char *data = (char *)SLOT_DATA_FROM_INDEX(state, slot_index);
++ int data_found = 0;
++
++ vchiq_log_trace(vchiq_core_log_level, "%d: pfq %d=%x %x %x",
++ state->id, slot_index, (unsigned int)data,
++ local->slot_queue_recycle, slot_queue_available);
++
++ /* Initialise the bitmask for services which have used this
++ ** slot */
++ BITSET_ZERO(service_found);
++
++ pos = 0;
++
++ while (pos < VCHIQ_SLOT_SIZE) {
++ VCHIQ_HEADER_T *header =
++ (VCHIQ_HEADER_T *)(data + pos);
++ int msgid = header->msgid;
++ if (VCHIQ_MSG_TYPE(msgid) == VCHIQ_MSG_DATA) {
++ int port = VCHIQ_MSG_SRCPORT(msgid);
++ VCHIQ_SERVICE_QUOTA_T *service_quota =
++ &state->service_quotas[port];
++ int count;
++ spin_lock(&quota_spinlock);
++ count = service_quota->message_use_count;
++ if (count > 0)
++ service_quota->message_use_count =
++ count - 1;
++ spin_unlock(&quota_spinlock);
++
++ if (count == service_quota->message_quota)
++ /* Signal the service that it
++ ** has dropped below its quota
++ */
++ up(&service_quota->quota_event);
++ else if (count == 0) {
++ vchiq_log_error(vchiq_core_log_level,
++ "service %d "
++ "message_use_count=%d "
++ "(header %x, msgid %x, "
++ "header->msgid %x, "
++ "header->size %x)",
++ port,
++ service_quota->
++ message_use_count,
++ (unsigned int)header, msgid,
++ header->msgid,
++ header->size);
++ WARN(1, "invalid message use count\n");
++ }
++ if (!BITSET_IS_SET(service_found, port)) {
++ /* Set the found bit for this service */
++ BITSET_SET(service_found, port);
++
++ spin_lock(&quota_spinlock);
++ count = service_quota->slot_use_count;
++ if (count > 0)
++ service_quota->slot_use_count =
++ count - 1;
++ spin_unlock(&quota_spinlock);
++
++ if (count > 0) {
++ /* Signal the service in case
++ ** it has dropped below its
++ ** quota */
++ up(&service_quota->quota_event);
++ vchiq_log_trace(
++ vchiq_core_log_level,
++ "%d: pfq:%d %x@%x - "
++ "slot_use->%d",
++ state->id, port,
++ header->size,
++ (unsigned int)header,
++ count - 1);
++ } else {
++ vchiq_log_error(
++ vchiq_core_log_level,
++ "service %d "
++ "slot_use_count"
++ "=%d (header %x"
++ ", msgid %x, "
++ "header->msgid"
++ " %x, header->"
++ "size %x)",
++ port, count,
++ (unsigned int)header,
++ msgid,
++ header->msgid,
++ header->size);
++ WARN(1, "bad slot use count\n");
++ }
++ }
++
++ data_found = 1;
++ }
++
++ pos += calc_stride(header->size);
++ if (pos > VCHIQ_SLOT_SIZE) {
++ vchiq_log_error(vchiq_core_log_level,
++ "pfq - pos %x: header %x, msgid %x, "
++ "header->msgid %x, header->size %x",
++ pos, (unsigned int)header, msgid,
++ header->msgid, header->size);
++ WARN(1, "invalid slot position\n");
++ }
++ }
++
++ if (data_found) {
++ int count;
++ spin_lock(&quota_spinlock);
++ count = state->data_use_count;
++ if (count > 0)
++ state->data_use_count =
++ count - 1;
++ spin_unlock(&quota_spinlock);
++ if (count == state->data_quota)
++ up(&state->data_quota_event);
++ }
++
++ state->slot_queue_available = slot_queue_available;
++ up(&state->slot_available_event);
++ }
++}
++
++/* Called by the slot handler and application threads */
++static VCHIQ_STATUS_T
++queue_message(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service,
++ int msgid, const VCHIQ_ELEMENT_T *elements,
++ int count, int size, int flags)
++{
++ VCHIQ_SHARED_STATE_T *local;
++ VCHIQ_SERVICE_QUOTA_T *service_quota = NULL;
++ VCHIQ_HEADER_T *header;
++ int type = VCHIQ_MSG_TYPE(msgid);
++
++ unsigned int stride;
++
++ local = state->local;
++
++ stride = calc_stride(size);
++
++ WARN_ON(!(stride <= VCHIQ_SLOT_SIZE));
++
++ if (!(flags & QMFLAGS_NO_MUTEX_LOCK) &&
++ (mutex_lock_interruptible(&state->slot_mutex) != 0))
++ return VCHIQ_RETRY;
++
++ if (type == VCHIQ_MSG_DATA) {
++ int tx_end_index;
++
++ BUG_ON(!service);
++ BUG_ON((flags & (QMFLAGS_NO_MUTEX_LOCK |
++ QMFLAGS_NO_MUTEX_UNLOCK)) != 0);
++
++ if (service->closing) {
++ /* The service has been closed */
++ mutex_unlock(&state->slot_mutex);
++ return VCHIQ_ERROR;
++ }
++
++ service_quota = &state->service_quotas[service->localport];
++
++ spin_lock(&quota_spinlock);
++
++ /* Ensure this service doesn't use more than its quota of
++ ** messages or slots */
++ tx_end_index = SLOT_QUEUE_INDEX_FROM_POS(
++ state->local_tx_pos + stride - 1);
++
++ /* Ensure data messages don't use more than their quota of
++ ** slots */
++ while ((tx_end_index != state->previous_data_index) &&
++ (state->data_use_count == state->data_quota)) {
++ VCHIQ_STATS_INC(state, data_stalls);
++ spin_unlock(&quota_spinlock);
++ mutex_unlock(&state->slot_mutex);
++
++ if (down_interruptible(&state->data_quota_event)
++ != 0)
++ return VCHIQ_RETRY;
++
++ mutex_lock(&state->slot_mutex);
++ spin_lock(&quota_spinlock);
++ tx_end_index = SLOT_QUEUE_INDEX_FROM_POS(
++ state->local_tx_pos + stride - 1);
++ if ((tx_end_index == state->previous_data_index) ||
++ (state->data_use_count < state->data_quota)) {
++ /* Pass the signal on to other waiters */
++ up(&state->data_quota_event);
++ break;
++ }
++ }
++
++ while ((service_quota->message_use_count ==
++ service_quota->message_quota) ||
++ ((tx_end_index != service_quota->previous_tx_index) &&
++ (service_quota->slot_use_count ==
++ service_quota->slot_quota))) {
++ spin_unlock(&quota_spinlock);
++ vchiq_log_trace(vchiq_core_log_level,
++ "%d: qm:%d %s,%x - quota stall "
++ "(msg %d, slot %d)",
++ state->id, service->localport,
++ msg_type_str(type), size,
++ service_quota->message_use_count,
++ service_quota->slot_use_count);
++ VCHIQ_SERVICE_STATS_INC(service, quota_stalls);
++ mutex_unlock(&state->slot_mutex);
++ if (down_interruptible(&service_quota->quota_event)
++ != 0)
++ return VCHIQ_RETRY;
++ if (service->closing)
++ return VCHIQ_ERROR;
++ if (mutex_lock_interruptible(&state->slot_mutex) != 0)
++ return VCHIQ_RETRY;
++ if (service->srvstate != VCHIQ_SRVSTATE_OPEN) {
++ /* The service has been closed */
++ mutex_unlock(&state->slot_mutex);
++ return VCHIQ_ERROR;
++ }
++ spin_lock(&quota_spinlock);
++ tx_end_index = SLOT_QUEUE_INDEX_FROM_POS(
++ state->local_tx_pos + stride - 1);
++ }
++
++ spin_unlock(&quota_spinlock);
++ }
++
++ header = reserve_space(state, stride, flags & QMFLAGS_IS_BLOCKING);
++
++ if (!header) {
++ if (service)
++ VCHIQ_SERVICE_STATS_INC(service, slot_stalls);
++ /* In the event of a failure, return the mutex to the
++ state it was in */
++ if (!(flags & QMFLAGS_NO_MUTEX_LOCK))
++ mutex_unlock(&state->slot_mutex);
++ return VCHIQ_RETRY;
++ }
++
++ if (type == VCHIQ_MSG_DATA) {
++ int i, pos;
++ int tx_end_index;
++ int slot_use_count;
++
++ vchiq_log_info(vchiq_core_log_level,
++ "%d: qm %s@%x,%x (%d->%d)",
++ state->id,
++ msg_type_str(VCHIQ_MSG_TYPE(msgid)),
++ (unsigned int)header, size,
++ VCHIQ_MSG_SRCPORT(msgid),
++ VCHIQ_MSG_DSTPORT(msgid));
++
++ BUG_ON(!service);
++ BUG_ON((flags & (QMFLAGS_NO_MUTEX_LOCK |
++ QMFLAGS_NO_MUTEX_UNLOCK)) != 0);
++
++ for (i = 0, pos = 0; i < (unsigned int)count;
++ pos += elements[i++].size)
++ if (elements[i].size) {
++ if (vchiq_copy_from_user
++ (header->data + pos, elements[i].data,
++ (size_t) elements[i].size) !=
++ VCHIQ_SUCCESS) {
++ mutex_unlock(&state->slot_mutex);
++ VCHIQ_SERVICE_STATS_INC(service,
++ error_count);
++ return VCHIQ_ERROR;
++ }
++ if (i == 0) {
++ if (SRVTRACE_ENABLED(service,
++ VCHIQ_LOG_INFO))
++ vchiq_log_dump_mem("Sent", 0,
++ header->data + pos,
++ min(64u,
++ elements[0].size));
++ }
++ }
++
++ spin_lock(&quota_spinlock);
++ service_quota->message_use_count++;
++
++ tx_end_index =
++ SLOT_QUEUE_INDEX_FROM_POS(state->local_tx_pos - 1);
++
++ /* If this transmission can't fit in the last slot used by any
++ ** service, the data_use_count must be increased. */
++ if (tx_end_index != state->previous_data_index) {
++ state->previous_data_index = tx_end_index;
++ state->data_use_count++;
++ }
++
++ /* If this isn't the same slot last used by this service,
++ ** the service's slot_use_count must be increased. */
++ if (tx_end_index != service_quota->previous_tx_index) {
++ service_quota->previous_tx_index = tx_end_index;
++ slot_use_count = ++service_quota->slot_use_count;
++ } else {
++ slot_use_count = 0;
++ }
++
++ spin_unlock(&quota_spinlock);
++
++ if (slot_use_count)
++ vchiq_log_trace(vchiq_core_log_level,
++ "%d: qm:%d %s,%x - slot_use->%d (hdr %p)",
++ state->id, service->localport,
++ msg_type_str(VCHIQ_MSG_TYPE(msgid)), size,
++ slot_use_count, header);
++
++ VCHIQ_SERVICE_STATS_INC(service, ctrl_tx_count);
++ VCHIQ_SERVICE_STATS_ADD(service, ctrl_tx_bytes, size);
++ } else {
++ vchiq_log_info(vchiq_core_log_level,
++ "%d: qm %s@%x,%x (%d->%d)", state->id,
++ msg_type_str(VCHIQ_MSG_TYPE(msgid)),
++ (unsigned int)header, size,
++ VCHIQ_MSG_SRCPORT(msgid),
++ VCHIQ_MSG_DSTPORT(msgid));
++ if (size != 0) {
++ WARN_ON(!((count == 1) && (size == elements[0].size)));
++ memcpy(header->data, elements[0].data,
++ elements[0].size);
++ }
++ VCHIQ_STATS_INC(state, ctrl_tx_count);
++ }
++
++ header->msgid = msgid;
++ header->size = size;
++
++ {
++ int svc_fourcc;
++
++ svc_fourcc = service
++ ? service->base.fourcc
++ : VCHIQ_MAKE_FOURCC('?', '?', '?', '?');
++
++ vchiq_log_info(SRVTRACE_LEVEL(service),
++ "Sent Msg %s(%u) to %c%c%c%c s:%u d:%d len:%d",
++ msg_type_str(VCHIQ_MSG_TYPE(msgid)),
++ VCHIQ_MSG_TYPE(msgid),
++ VCHIQ_FOURCC_AS_4CHARS(svc_fourcc),
++ VCHIQ_MSG_SRCPORT(msgid),
++ VCHIQ_MSG_DSTPORT(msgid),
++ size);
++ }
++
++ /* Make sure the new header is visible to the peer. */
++ wmb();
++
++ /* Make the new tx_pos visible to the peer. */
++ local->tx_pos = state->local_tx_pos;
++ wmb();
++
++ if (service && (type == VCHIQ_MSG_CLOSE))
++ vchiq_set_service_state(service, VCHIQ_SRVSTATE_CLOSESENT);
++
++ if (!(flags & QMFLAGS_NO_MUTEX_UNLOCK))
++ mutex_unlock(&state->slot_mutex);
++
++ remote_event_signal(&state->remote->trigger);
++
++ return VCHIQ_SUCCESS;
++}
++
++/* Called by the slot handler and application threads */
++static VCHIQ_STATUS_T
++queue_message_sync(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service,
++ int msgid, const VCHIQ_ELEMENT_T *elements,
++ int count, int size, int is_blocking)
++{
++ VCHIQ_SHARED_STATE_T *local;
++ VCHIQ_HEADER_T *header;
++
++ local = state->local;
++
++ if ((VCHIQ_MSG_TYPE(msgid) != VCHIQ_MSG_RESUME) &&
++ (mutex_lock_interruptible(&state->sync_mutex) != 0))
++ return VCHIQ_RETRY;
++
++ remote_event_wait(&local->sync_release);
++
++ rmb();
++
++ header = (VCHIQ_HEADER_T *)SLOT_DATA_FROM_INDEX(state,
++ local->slot_sync);
++
++ {
++ int oldmsgid = header->msgid;
++ if (oldmsgid != VCHIQ_MSGID_PADDING)
++ vchiq_log_error(vchiq_core_log_level,
++ "%d: qms - msgid %x, not PADDING",
++ state->id, oldmsgid);
++ }
++
++ if (service) {
++ int i, pos;
++
++ vchiq_log_info(vchiq_sync_log_level,
++ "%d: qms %s@%x,%x (%d->%d)", state->id,
++ msg_type_str(VCHIQ_MSG_TYPE(msgid)),
++ (unsigned int)header, size,
++ VCHIQ_MSG_SRCPORT(msgid),
++ VCHIQ_MSG_DSTPORT(msgid));
++
++ for (i = 0, pos = 0; i < (unsigned int)count;
++ pos += elements[i++].size)
++ if (elements[i].size) {
++ if (vchiq_copy_from_user
++ (header->data + pos, elements[i].data,
++ (size_t) elements[i].size) !=
++ VCHIQ_SUCCESS) {
++ mutex_unlock(&state->sync_mutex);
++ VCHIQ_SERVICE_STATS_INC(service,
++ error_count);
++ return VCHIQ_ERROR;
++ }
++ if (i == 0) {
++ if (vchiq_sync_log_level >=
++ VCHIQ_LOG_TRACE)
++ vchiq_log_dump_mem("Sent Sync",
++ 0, header->data + pos,
++ min(64u,
++ elements[0].size));
++ }
++ }
++
++ VCHIQ_SERVICE_STATS_INC(service, ctrl_tx_count);
++ VCHIQ_SERVICE_STATS_ADD(service, ctrl_tx_bytes, size);
++ } else {
++ vchiq_log_info(vchiq_sync_log_level,
++ "%d: qms %s@%x,%x (%d->%d)", state->id,
++ msg_type_str(VCHIQ_MSG_TYPE(msgid)),
++ (unsigned int)header, size,
++ VCHIQ_MSG_SRCPORT(msgid),
++ VCHIQ_MSG_DSTPORT(msgid));
++ if (size != 0) {
++ WARN_ON(!((count == 1) && (size == elements[0].size)));
++ memcpy(header->data, elements[0].data,
++ elements[0].size);
++ }
++ VCHIQ_STATS_INC(state, ctrl_tx_count);
++ }
++
++ header->size = size;
++ header->msgid = msgid;
++
++ if (vchiq_sync_log_level >= VCHIQ_LOG_TRACE) {
++ int svc_fourcc;
++
++ svc_fourcc = service
++ ? service->base.fourcc
++ : VCHIQ_MAKE_FOURCC('?', '?', '?', '?');
++
++ vchiq_log_trace(vchiq_sync_log_level,
++ "Sent Sync Msg %s(%u) to %c%c%c%c s:%u d:%d len:%d",
++ msg_type_str(VCHIQ_MSG_TYPE(msgid)),
++ VCHIQ_MSG_TYPE(msgid),
++ VCHIQ_FOURCC_AS_4CHARS(svc_fourcc),
++ VCHIQ_MSG_SRCPORT(msgid),
++ VCHIQ_MSG_DSTPORT(msgid),
++ size);
++ }
++
++ /* Make sure the new header is visible to the peer. */
++ wmb();
++
++ remote_event_signal(&state->remote->sync_trigger);
++
++ if (VCHIQ_MSG_TYPE(msgid) != VCHIQ_MSG_PAUSE)
++ mutex_unlock(&state->sync_mutex);
++
++ return VCHIQ_SUCCESS;
++}
++
++static inline void
++claim_slot(VCHIQ_SLOT_INFO_T *slot)
++{
++ slot->use_count++;
++}
++
++static void
++release_slot(VCHIQ_STATE_T *state, VCHIQ_SLOT_INFO_T *slot_info,
++ VCHIQ_HEADER_T *header, VCHIQ_SERVICE_T *service)
++{
++ int release_count;
++
++ mutex_lock(&state->recycle_mutex);
++
++ if (header) {
++ int msgid = header->msgid;
++ if (((msgid & VCHIQ_MSGID_CLAIMED) == 0) ||
++ (service && service->closing)) {
++ mutex_unlock(&state->recycle_mutex);
++ return;
++ }
++
++ /* Rewrite the message header to prevent a double
++ ** release */
++ header->msgid = msgid & ~VCHIQ_MSGID_CLAIMED;
++ }
++
++ release_count = slot_info->release_count;
++ slot_info->release_count = ++release_count;
++
++ if (release_count == slot_info->use_count) {
++ int slot_queue_recycle;
++ /* Add to the freed queue */
++
++ /* A read barrier is necessary here to prevent speculative
++ ** fetches of remote->slot_queue_recycle from overtaking the
++ ** mutex. */
++ rmb();
++
++ slot_queue_recycle = state->remote->slot_queue_recycle;
++ state->remote->slot_queue[slot_queue_recycle &
++ VCHIQ_SLOT_QUEUE_MASK] =
++ SLOT_INDEX_FROM_INFO(state, slot_info);
++ state->remote->slot_queue_recycle = slot_queue_recycle + 1;
++ vchiq_log_info(vchiq_core_log_level,
++ "%d: release_slot %d - recycle->%x",
++ state->id, SLOT_INDEX_FROM_INFO(state, slot_info),
++ state->remote->slot_queue_recycle);
++
++ /* A write barrier is necessary, but remote_event_signal
++ ** contains one. */
++ remote_event_signal(&state->remote->recycle);
++ }
++
++ mutex_unlock(&state->recycle_mutex);
++}
++
++/* Called by the slot handler - don't hold the bulk mutex */
++static VCHIQ_STATUS_T
++notify_bulks(VCHIQ_SERVICE_T *service, VCHIQ_BULK_QUEUE_T *queue,
++ int retry_poll)
++{
++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS;
++
++ vchiq_log_trace(vchiq_core_log_level,
++ "%d: nb:%d %cx - p=%x rn=%x r=%x",
++ service->state->id, service->localport,
++ (queue == &service->bulk_tx) ? 't' : 'r',
++ queue->process, queue->remote_notify, queue->remove);
++
++ if (service->state->is_master) {
++ while (queue->remote_notify != queue->process) {
++ VCHIQ_BULK_T *bulk =
++ &queue->bulks[BULK_INDEX(queue->remote_notify)];
++ int msgtype = (bulk->dir == VCHIQ_BULK_TRANSMIT) ?
++ VCHIQ_MSG_BULK_RX_DONE : VCHIQ_MSG_BULK_TX_DONE;
++ int msgid = VCHIQ_MAKE_MSG(msgtype, service->localport,
++ service->remoteport);
++ VCHIQ_ELEMENT_T element = { &bulk->actual, 4 };
++ /* Only reply to non-dummy bulk requests */
++ if (bulk->remote_data) {
++ status = queue_message(service->state, NULL,
++ msgid, &element, 1, 4, 0);
++ if (status != VCHIQ_SUCCESS)
++ break;
++ }
++ queue->remote_notify++;
++ }
++ } else {
++ queue->remote_notify = queue->process;
++ }
++
++ if (status == VCHIQ_SUCCESS) {
++ while (queue->remove != queue->remote_notify) {
++ VCHIQ_BULK_T *bulk =
++ &queue->bulks[BULK_INDEX(queue->remove)];
++
++ /* Only generate callbacks for non-dummy bulk
++ ** requests, and non-terminated services */
++ if (bulk->data && service->instance) {
++ if (bulk->actual != VCHIQ_BULK_ACTUAL_ABORTED) {
++ if (bulk->dir == VCHIQ_BULK_TRANSMIT) {
++ VCHIQ_SERVICE_STATS_INC(service,
++ bulk_tx_count);
++ VCHIQ_SERVICE_STATS_ADD(service,
++ bulk_tx_bytes,
++ bulk->actual);
++ } else {
++ VCHIQ_SERVICE_STATS_INC(service,
++ bulk_rx_count);
++ VCHIQ_SERVICE_STATS_ADD(service,
++ bulk_rx_bytes,
++ bulk->actual);
++ }
++ } else {
++ VCHIQ_SERVICE_STATS_INC(service,
++ bulk_aborted_count);
++ }
++ if (bulk->mode == VCHIQ_BULK_MODE_BLOCKING) {
++ struct bulk_waiter *waiter;
++ spin_lock(&bulk_waiter_spinlock);
++ waiter = bulk->userdata;
++ if (waiter) {
++ waiter->actual = bulk->actual;
++ up(&waiter->event);
++ }
++ spin_unlock(&bulk_waiter_spinlock);
++ } else if (bulk->mode ==
++ VCHIQ_BULK_MODE_CALLBACK) {
++ VCHIQ_REASON_T reason = (bulk->dir ==
++ VCHIQ_BULK_TRANSMIT) ?
++ ((bulk->actual ==
++ VCHIQ_BULK_ACTUAL_ABORTED) ?
++ VCHIQ_BULK_TRANSMIT_ABORTED :
++ VCHIQ_BULK_TRANSMIT_DONE) :
++ ((bulk->actual ==
++ VCHIQ_BULK_ACTUAL_ABORTED) ?
++ VCHIQ_BULK_RECEIVE_ABORTED :
++ VCHIQ_BULK_RECEIVE_DONE);
++ status = make_service_callback(service,
++ reason, NULL, bulk->userdata);
++ if (status == VCHIQ_RETRY)
++ break;
++ }
++ }
++
++ queue->remove++;
++ up(&service->bulk_remove_event);
++ }
++ if (!retry_poll)
++ status = VCHIQ_SUCCESS;
++ }
++
++ if (status == VCHIQ_RETRY)
++ request_poll(service->state, service,
++ (queue == &service->bulk_tx) ?
++ VCHIQ_POLL_TXNOTIFY : VCHIQ_POLL_RXNOTIFY);
++
++ return status;
++}
++
++/* Called by the slot handler thread */
++static void
++poll_services(VCHIQ_STATE_T *state)
++{
++ int group, i;
++
++ for (group = 0; group < BITSET_SIZE(state->unused_service); group++) {
++ uint32_t flags;
++ flags = atomic_xchg(&state->poll_services[group], 0);
++ for (i = 0; flags; i++) {
++ if (flags & (1 << i)) {
++ VCHIQ_SERVICE_T *service =
++ find_service_by_port(state,
++ (group<<5) + i);
++ uint32_t service_flags;
++ flags &= ~(1 << i);
++ if (!service)
++ continue;
++ service_flags =
++ atomic_xchg(&service->poll_flags, 0);
++ if (service_flags &
++ (1 << VCHIQ_POLL_REMOVE)) {
++ vchiq_log_info(vchiq_core_log_level,
++ "%d: ps - remove %d<->%d",
++ state->id, service->localport,
++ service->remoteport);
++
++ /* Make it look like a client, because
++ it must be removed and not left in
++ the LISTENING state. */
++ service->public_fourcc =
++ VCHIQ_FOURCC_INVALID;
++
++ if (vchiq_close_service_internal(
++ service, 0/*!close_recvd*/) !=
++ VCHIQ_SUCCESS)
++ request_poll(state, service,
++ VCHIQ_POLL_REMOVE);
++ } else if (service_flags &
++ (1 << VCHIQ_POLL_TERMINATE)) {
++ vchiq_log_info(vchiq_core_log_level,
++ "%d: ps - terminate %d<->%d",
++ state->id, service->localport,
++ service->remoteport);
++ if (vchiq_close_service_internal(
++ service, 0/*!close_recvd*/) !=
++ VCHIQ_SUCCESS)
++ request_poll(state, service,
++ VCHIQ_POLL_TERMINATE);
++ }
++ if (service_flags & (1 << VCHIQ_POLL_TXNOTIFY))
++ notify_bulks(service,
++ &service->bulk_tx,
++ 1/*retry_poll*/);
++ if (service_flags & (1 << VCHIQ_POLL_RXNOTIFY))
++ notify_bulks(service,
++ &service->bulk_rx,
++ 1/*retry_poll*/);
++ unlock_service(service);
++ }
++ }
++ }
++}
++
++/* Called by the slot handler or application threads, holding the bulk mutex. */
++static int
++resolve_bulks(VCHIQ_SERVICE_T *service, VCHIQ_BULK_QUEUE_T *queue)
++{
++ VCHIQ_STATE_T *state = service->state;
++ int resolved = 0;
++ int rc;
++
++ while ((queue->process != queue->local_insert) &&
++ (queue->process != queue->remote_insert)) {
++ VCHIQ_BULK_T *bulk = &queue->bulks[BULK_INDEX(queue->process)];
++
++ vchiq_log_trace(vchiq_core_log_level,
++ "%d: rb:%d %cx - li=%x ri=%x p=%x",
++ state->id, service->localport,
++ (queue == &service->bulk_tx) ? 't' : 'r',
++ queue->local_insert, queue->remote_insert,
++ queue->process);
++
++ WARN_ON(!((int)(queue->local_insert - queue->process) > 0));
++ WARN_ON(!((int)(queue->remote_insert - queue->process) > 0));
++
++ rc = mutex_lock_interruptible(&state->bulk_transfer_mutex);
++ if (rc != 0)
++ break;
++
++ vchiq_transfer_bulk(bulk);
++ mutex_unlock(&state->bulk_transfer_mutex);
++
++ if (SRVTRACE_ENABLED(service, VCHIQ_LOG_INFO)) {
++ const char *header = (queue == &service->bulk_tx) ?
++ "Send Bulk to" : "Recv Bulk from";
++ if (bulk->actual != VCHIQ_BULK_ACTUAL_ABORTED)
++ vchiq_log_info(SRVTRACE_LEVEL(service),
++ "%s %c%c%c%c d:%d len:%d %x<->%x",
++ header,
++ VCHIQ_FOURCC_AS_4CHARS(
++ service->base.fourcc),
++ service->remoteport,
++ bulk->size,
++ (unsigned int)bulk->data,
++ (unsigned int)bulk->remote_data);
++ else
++ vchiq_log_info(SRVTRACE_LEVEL(service),
++ "%s %c%c%c%c d:%d ABORTED - tx len:%d,"
++ " rx len:%d %x<->%x",
++ header,
++ VCHIQ_FOURCC_AS_4CHARS(
++ service->base.fourcc),
++ service->remoteport,
++ bulk->size,
++ bulk->remote_size,
++ (unsigned int)bulk->data,
++ (unsigned int)bulk->remote_data);
++ }
++
++ vchiq_complete_bulk(bulk);
++ queue->process++;
++ resolved++;
++ }
++ return resolved;
++}
++
++/* Called with the bulk_mutex held */
++static void
++abort_outstanding_bulks(VCHIQ_SERVICE_T *service, VCHIQ_BULK_QUEUE_T *queue)
++{
++ int is_tx = (queue == &service->bulk_tx);
++ vchiq_log_trace(vchiq_core_log_level,
++ "%d: aob:%d %cx - li=%x ri=%x p=%x",
++ service->state->id, service->localport, is_tx ? 't' : 'r',
++ queue->local_insert, queue->remote_insert, queue->process);
++
++ WARN_ON(!((int)(queue->local_insert - queue->process) >= 0));
++ WARN_ON(!((int)(queue->remote_insert - queue->process) >= 0));
++
++ while ((queue->process != queue->local_insert) ||
++ (queue->process != queue->remote_insert)) {
++ VCHIQ_BULK_T *bulk = &queue->bulks[BULK_INDEX(queue->process)];
++
++ if (queue->process == queue->remote_insert) {
++ /* fabricate a matching dummy bulk */
++ bulk->remote_data = NULL;
++ bulk->remote_size = 0;
++ queue->remote_insert++;
++ }
++
++ if (queue->process != queue->local_insert) {
++ vchiq_complete_bulk(bulk);
++
++ vchiq_log_info(SRVTRACE_LEVEL(service),
++ "%s %c%c%c%c d:%d ABORTED - tx len:%d, "
++ "rx len:%d",
++ is_tx ? "Send Bulk to" : "Recv Bulk from",
++ VCHIQ_FOURCC_AS_4CHARS(service->base.fourcc),
++ service->remoteport,
++ bulk->size,
++ bulk->remote_size);
++ } else {
++ /* fabricate a matching dummy bulk */
++ bulk->data = NULL;
++ bulk->size = 0;
++ bulk->actual = VCHIQ_BULK_ACTUAL_ABORTED;
++ bulk->dir = is_tx ? VCHIQ_BULK_TRANSMIT :
++ VCHIQ_BULK_RECEIVE;
++ queue->local_insert++;
++ }
++
++ queue->process++;
++ }
++}
++
++/* Called from the slot handler thread */
++static void
++pause_bulks(VCHIQ_STATE_T *state)
++{
++ if (unlikely(atomic_inc_return(&pause_bulks_count) != 1)) {
++ WARN_ON_ONCE(1);
++ atomic_set(&pause_bulks_count, 1);
++ return;
++ }
++
++ /* Block bulk transfers from all services */
++ mutex_lock(&state->bulk_transfer_mutex);
++}
++
++/* Called from the slot handler thread */
++static void
++resume_bulks(VCHIQ_STATE_T *state)
++{
++ int i;
++ if (unlikely(atomic_dec_return(&pause_bulks_count) != 0)) {
++ WARN_ON_ONCE(1);
++ atomic_set(&pause_bulks_count, 0);
++ return;
++ }
++
++ /* Allow bulk transfers from all services */
++ mutex_unlock(&state->bulk_transfer_mutex);
++
++ if (state->deferred_bulks == 0)
++ return;
++
++ /* Deal with any bulks which had to be deferred due to being in
++ * paused state. Don't try to match up to number of deferred bulks
++ * in case we've had something come and close the service in the
++ * interim - just process all bulk queues for all services */
++ vchiq_log_info(vchiq_core_log_level, "%s: processing %d deferred bulks",
++ __func__, state->deferred_bulks);
++
++ for (i = 0; i < state->unused_service; i++) {
++ VCHIQ_SERVICE_T *service = state->services[i];
++ int resolved_rx = 0;
++ int resolved_tx = 0;
++ if (!service || (service->srvstate != VCHIQ_SRVSTATE_OPEN))
++ continue;
++
++ mutex_lock(&service->bulk_mutex);
++ resolved_rx = resolve_bulks(service, &service->bulk_rx);
++ resolved_tx = resolve_bulks(service, &service->bulk_tx);
++ mutex_unlock(&service->bulk_mutex);
++ if (resolved_rx)
++ notify_bulks(service, &service->bulk_rx, 1);
++ if (resolved_tx)
++ notify_bulks(service, &service->bulk_tx, 1);
++ }
++ state->deferred_bulks = 0;
++}
++
++static int
++parse_open(VCHIQ_STATE_T *state, VCHIQ_HEADER_T *header)
++{
++ VCHIQ_SERVICE_T *service = NULL;
++ int msgid, size;
++ int type;
++ unsigned int localport, remoteport;
++
++ msgid = header->msgid;
++ size = header->size;
++ type = VCHIQ_MSG_TYPE(msgid);
++ localport = VCHIQ_MSG_DSTPORT(msgid);
++ remoteport = VCHIQ_MSG_SRCPORT(msgid);
++ if (size >= sizeof(struct vchiq_open_payload)) {
++ const struct vchiq_open_payload *payload =
++ (struct vchiq_open_payload *)header->data;
++ unsigned int fourcc;
++
++ fourcc = payload->fourcc;
++ vchiq_log_info(vchiq_core_log_level,
++ "%d: prs OPEN@%x (%d->'%c%c%c%c')",
++ state->id, (unsigned int)header,
++ localport,
++ VCHIQ_FOURCC_AS_4CHARS(fourcc));
++
++ service = get_listening_service(state, fourcc);
++
++ if (service) {
++ /* A matching service exists */
++ short version = payload->version;
++ short version_min = payload->version_min;
++ if ((service->version < version_min) ||
++ (version < service->version_min)) {
++ /* Version mismatch */
++ vchiq_loud_error_header();
++ vchiq_loud_error("%d: service %d (%c%c%c%c) "
++ "version mismatch - local (%d, min %d)"
++ " vs. remote (%d, min %d)",
++ state->id, service->localport,
++ VCHIQ_FOURCC_AS_4CHARS(fourcc),
++ service->version, service->version_min,
++ version, version_min);
++ vchiq_loud_error_footer();
++ unlock_service(service);
++ service = NULL;
++ goto fail_open;
++ }
++ service->peer_version = version;
++
++ if (service->srvstate == VCHIQ_SRVSTATE_LISTENING) {
++ struct vchiq_openack_payload ack_payload = {
++ service->version
++ };
++ VCHIQ_ELEMENT_T body = {
++ &ack_payload,
++ sizeof(ack_payload)
++ };
++
++ if (state->version_common <
++ VCHIQ_VERSION_SYNCHRONOUS_MODE)
++ service->sync = 0;
++
++ /* Acknowledge the OPEN */
++ if (service->sync &&
++ (state->version_common >=
++ VCHIQ_VERSION_SYNCHRONOUS_MODE)) {
++ if (queue_message_sync(state, NULL,
++ VCHIQ_MAKE_MSG(
++ VCHIQ_MSG_OPENACK,
++ service->localport,
++ remoteport),
++ &body, 1, sizeof(ack_payload),
++ 0) == VCHIQ_RETRY)
++ goto bail_not_ready;
++ } else {
++ if (queue_message(state, NULL,
++ VCHIQ_MAKE_MSG(
++ VCHIQ_MSG_OPENACK,
++ service->localport,
++ remoteport),
++ &body, 1, sizeof(ack_payload),
++ 0) == VCHIQ_RETRY)
++ goto bail_not_ready;
++ }
++
++ /* The service is now open */
++ vchiq_set_service_state(service,
++ service->sync ? VCHIQ_SRVSTATE_OPENSYNC
++ : VCHIQ_SRVSTATE_OPEN);
++ }
++
++ service->remoteport = remoteport;
++ service->client_id = ((int *)header->data)[1];
++ if (make_service_callback(service, VCHIQ_SERVICE_OPENED,
++ NULL, NULL) == VCHIQ_RETRY) {
++ /* Bail out if not ready */
++ service->remoteport = VCHIQ_PORT_FREE;
++ goto bail_not_ready;
++ }
++
++ /* Success - the message has been dealt with */
++ unlock_service(service);
++ return 1;
++ }
++ }
++
++fail_open:
++ /* No available service, or an invalid request - send a CLOSE */
++ if (queue_message(state, NULL,
++ VCHIQ_MAKE_MSG(VCHIQ_MSG_CLOSE, 0, VCHIQ_MSG_SRCPORT(msgid)),
++ NULL, 0, 0, 0) == VCHIQ_RETRY)
++ goto bail_not_ready;
++
++ return 1;
++
++bail_not_ready:
++ if (service)
++ unlock_service(service);
++
++ return 0;
++}
++
++/* Called by the slot handler thread */
++static void
++parse_rx_slots(VCHIQ_STATE_T *state)
++{
++ VCHIQ_SHARED_STATE_T *remote = state->remote;
++ VCHIQ_SERVICE_T *service = NULL;
++ int tx_pos;
++ DEBUG_INITIALISE(state->local)
++
++ tx_pos = remote->tx_pos;
++
++ while (state->rx_pos != tx_pos) {
++ VCHIQ_HEADER_T *header;
++ int msgid, size;
++ int type;
++ unsigned int localport, remoteport;
++
++ DEBUG_TRACE(PARSE_LINE);
++ if (!state->rx_data) {
++ int rx_index;
++ WARN_ON(!((state->rx_pos & VCHIQ_SLOT_MASK) == 0));
++ rx_index = remote->slot_queue[
++ SLOT_QUEUE_INDEX_FROM_POS(state->rx_pos) &
++ VCHIQ_SLOT_QUEUE_MASK];
++ state->rx_data = (char *)SLOT_DATA_FROM_INDEX(state,
++ rx_index);
++ state->rx_info = SLOT_INFO_FROM_INDEX(state, rx_index);
++
++ /* Initialise use_count to one, and increment
++ ** release_count at the end of the slot to avoid
++ ** releasing the slot prematurely. */
++ state->rx_info->use_count = 1;
++ state->rx_info->release_count = 0;
++ }
++
++ header = (VCHIQ_HEADER_T *)(state->rx_data +
++ (state->rx_pos & VCHIQ_SLOT_MASK));
++ DEBUG_VALUE(PARSE_HEADER, (int)header);
++ msgid = header->msgid;
++ DEBUG_VALUE(PARSE_MSGID, msgid);
++ size = header->size;
++ type = VCHIQ_MSG_TYPE(msgid);
++ localport = VCHIQ_MSG_DSTPORT(msgid);
++ remoteport = VCHIQ_MSG_SRCPORT(msgid);
++
++ if (type != VCHIQ_MSG_DATA)
++ VCHIQ_STATS_INC(state, ctrl_rx_count);
++
++ switch (type) {
++ case VCHIQ_MSG_OPENACK:
++ case VCHIQ_MSG_CLOSE:
++ case VCHIQ_MSG_DATA:
++ case VCHIQ_MSG_BULK_RX:
++ case VCHIQ_MSG_BULK_TX:
++ case VCHIQ_MSG_BULK_RX_DONE:
++ case VCHIQ_MSG_BULK_TX_DONE:
++ service = find_service_by_port(state, localport);
++ if ((!service ||
++ ((service->remoteport != remoteport) &&
++ (service->remoteport != VCHIQ_PORT_FREE))) &&
++ (localport == 0) &&
++ (type == VCHIQ_MSG_CLOSE)) {
++ /* This could be a CLOSE from a client which
++ hadn't yet received the OPENACK - look for
++ the connected service */
++ if (service)
++ unlock_service(service);
++ service = get_connected_service(state,
++ remoteport);
++ if (service)
++ vchiq_log_warning(vchiq_core_log_level,
++ "%d: prs %s@%x (%d->%d) - "
++ "found connected service %d",
++ state->id, msg_type_str(type),
++ (unsigned int)header,
++ remoteport, localport,
++ service->localport);
++ }
++
++ if (!service) {
++ vchiq_log_error(vchiq_core_log_level,
++ "%d: prs %s@%x (%d->%d) - "
++ "invalid/closed service %d",
++ state->id, msg_type_str(type),
++ (unsigned int)header,
++ remoteport, localport, localport);
++ goto skip_message;
++ }
++ break;
++ default:
++ break;
++ }
++
++ if (SRVTRACE_ENABLED(service, VCHIQ_LOG_INFO)) {
++ int svc_fourcc;
++
++ svc_fourcc = service
++ ? service->base.fourcc
++ : VCHIQ_MAKE_FOURCC('?', '?', '?', '?');
++ vchiq_log_info(SRVTRACE_LEVEL(service),
++ "Rcvd Msg %s(%u) from %c%c%c%c s:%d d:%d "
++ "len:%d",
++ msg_type_str(type), type,
++ VCHIQ_FOURCC_AS_4CHARS(svc_fourcc),
++ remoteport, localport, size);
++ if (size > 0)
++ vchiq_log_dump_mem("Rcvd", 0, header->data,
++ min(64, size));
++ }
++
++ if (((unsigned int)header & VCHIQ_SLOT_MASK) + calc_stride(size)
++ > VCHIQ_SLOT_SIZE) {
++ vchiq_log_error(vchiq_core_log_level,
++ "header %x (msgid %x) - size %x too big for "
++ "slot",
++ (unsigned int)header, (unsigned int)msgid,
++ (unsigned int)size);
++ WARN(1, "oversized for slot\n");
++ }
++
++ switch (type) {
++ case VCHIQ_MSG_OPEN:
++ WARN_ON(!(VCHIQ_MSG_DSTPORT(msgid) == 0));
++ if (!parse_open(state, header))
++ goto bail_not_ready;
++ break;
++ case VCHIQ_MSG_OPENACK:
++ if (size >= sizeof(struct vchiq_openack_payload)) {
++ const struct vchiq_openack_payload *payload =
++ (struct vchiq_openack_payload *)
++ header->data;
++ service->peer_version = payload->version;
++ }
++ vchiq_log_info(vchiq_core_log_level,
++ "%d: prs OPENACK@%x,%x (%d->%d) v:%d",
++ state->id, (unsigned int)header, size,
++ remoteport, localport, service->peer_version);
++ if (service->srvstate ==
++ VCHIQ_SRVSTATE_OPENING) {
++ service->remoteport = remoteport;
++ vchiq_set_service_state(service,
++ VCHIQ_SRVSTATE_OPEN);
++ up(&service->remove_event);
++ } else
++ vchiq_log_error(vchiq_core_log_level,
++ "OPENACK received in state %s",
++ srvstate_names[service->srvstate]);
++ break;
++ case VCHIQ_MSG_CLOSE:
++ WARN_ON(size != 0); /* There should be no data */
++
++ vchiq_log_info(vchiq_core_log_level,
++ "%d: prs CLOSE@%x (%d->%d)",
++ state->id, (unsigned int)header,
++ remoteport, localport);
++
++ mark_service_closing_internal(service, 1);
++
++ if (vchiq_close_service_internal(service,
++ 1/*close_recvd*/) == VCHIQ_RETRY)
++ goto bail_not_ready;
++
++ vchiq_log_info(vchiq_core_log_level,
++ "Close Service %c%c%c%c s:%u d:%d",
++ VCHIQ_FOURCC_AS_4CHARS(service->base.fourcc),
++ service->localport,
++ service->remoteport);
++ break;
++ case VCHIQ_MSG_DATA:
++ vchiq_log_info(vchiq_core_log_level,
++ "%d: prs DATA@%x,%x (%d->%d)",
++ state->id, (unsigned int)header, size,
++ remoteport, localport);
++
++ if ((service->remoteport == remoteport)
++ && (service->srvstate ==
++ VCHIQ_SRVSTATE_OPEN)) {
++ header->msgid = msgid | VCHIQ_MSGID_CLAIMED;
++ claim_slot(state->rx_info);
++ DEBUG_TRACE(PARSE_LINE);
++ if (make_service_callback(service,
++ VCHIQ_MESSAGE_AVAILABLE, header,
++ NULL) == VCHIQ_RETRY) {
++ DEBUG_TRACE(PARSE_LINE);
++ goto bail_not_ready;
++ }
++ VCHIQ_SERVICE_STATS_INC(service, ctrl_rx_count);
++ VCHIQ_SERVICE_STATS_ADD(service, ctrl_rx_bytes,
++ size);
++ } else {
++ VCHIQ_STATS_INC(state, error_count);
++ }
++ break;
++ case VCHIQ_MSG_CONNECT:
++ vchiq_log_info(vchiq_core_log_level,
++ "%d: prs CONNECT@%x",
++ state->id, (unsigned int)header);
++ state->version_common = ((VCHIQ_SLOT_ZERO_T *)
++ state->slot_data)->version;
++ up(&state->connect);
++ break;
++ case VCHIQ_MSG_BULK_RX:
++ case VCHIQ_MSG_BULK_TX: {
++ VCHIQ_BULK_QUEUE_T *queue;
++ WARN_ON(!state->is_master);
++ queue = (type == VCHIQ_MSG_BULK_RX) ?
++ &service->bulk_tx : &service->bulk_rx;
++ if ((service->remoteport == remoteport)
++ && (service->srvstate ==
++ VCHIQ_SRVSTATE_OPEN)) {
++ VCHIQ_BULK_T *bulk;
++ int resolved = 0;
++
++ DEBUG_TRACE(PARSE_LINE);
++ if (mutex_lock_interruptible(
++ &service->bulk_mutex) != 0) {
++ DEBUG_TRACE(PARSE_LINE);
++ goto bail_not_ready;
++ }
++
++ WARN_ON(!(queue->remote_insert < queue->remove +
++ VCHIQ_NUM_SERVICE_BULKS));
++ bulk = &queue->bulks[
++ BULK_INDEX(queue->remote_insert)];
++ bulk->remote_data =
++ (void *)((int *)header->data)[0];
++ bulk->remote_size = ((int *)header->data)[1];
++ wmb();
++
++ vchiq_log_info(vchiq_core_log_level,
++ "%d: prs %s@%x (%d->%d) %x@%x",
++ state->id, msg_type_str(type),
++ (unsigned int)header,
++ remoteport, localport,
++ bulk->remote_size,
++ (unsigned int)bulk->remote_data);
++
++ queue->remote_insert++;
++
++ if (atomic_read(&pause_bulks_count)) {
++ state->deferred_bulks++;
++ vchiq_log_info(vchiq_core_log_level,
++ "%s: deferring bulk (%d)",
++ __func__,
++ state->deferred_bulks);
++ if (state->conn_state !=
++ VCHIQ_CONNSTATE_PAUSE_SENT)
++ vchiq_log_error(
++ vchiq_core_log_level,
++ "%s: bulks paused in "
++ "unexpected state %s",
++ __func__,
++ conn_state_names[
++ state->conn_state]);
++ } else if (state->conn_state ==
++ VCHIQ_CONNSTATE_CONNECTED) {
++ DEBUG_TRACE(PARSE_LINE);
++ resolved = resolve_bulks(service,
++ queue);
++ }
++
++ mutex_unlock(&service->bulk_mutex);
++ if (resolved)
++ notify_bulks(service, queue,
++ 1/*retry_poll*/);
++ }
++ } break;
++ case VCHIQ_MSG_BULK_RX_DONE:
++ case VCHIQ_MSG_BULK_TX_DONE:
++ WARN_ON(state->is_master);
++ if ((service->remoteport == remoteport)
++ && (service->srvstate !=
++ VCHIQ_SRVSTATE_FREE)) {
++ VCHIQ_BULK_QUEUE_T *queue;
++ VCHIQ_BULK_T *bulk;
++
++ queue = (type == VCHIQ_MSG_BULK_RX_DONE) ?
++ &service->bulk_rx : &service->bulk_tx;
++
++ DEBUG_TRACE(PARSE_LINE);
++ if (mutex_lock_interruptible(
++ &service->bulk_mutex) != 0) {
++ DEBUG_TRACE(PARSE_LINE);
++ goto bail_not_ready;
++ }
++ if ((int)(queue->remote_insert -
++ queue->local_insert) >= 0) {
++ vchiq_log_error(vchiq_core_log_level,
++ "%d: prs %s@%x (%d->%d) "
++ "unexpected (ri=%d,li=%d)",
++ state->id, msg_type_str(type),
++ (unsigned int)header,
++ remoteport, localport,
++ queue->remote_insert,
++ queue->local_insert);
++ mutex_unlock(&service->bulk_mutex);
++ break;
++ }
++
++ BUG_ON(queue->process == queue->local_insert);
++ BUG_ON(queue->process != queue->remote_insert);
++
++ bulk = &queue->bulks[
++ BULK_INDEX(queue->remote_insert)];
++ bulk->actual = *(int *)header->data;
++ queue->remote_insert++;
++
++ vchiq_log_info(vchiq_core_log_level,
++ "%d: prs %s@%x (%d->%d) %x@%x",
++ state->id, msg_type_str(type),
++ (unsigned int)header,
++ remoteport, localport,
++ bulk->actual, (unsigned int)bulk->data);
++
++ vchiq_log_trace(vchiq_core_log_level,
++ "%d: prs:%d %cx li=%x ri=%x p=%x",
++ state->id, localport,
++ (type == VCHIQ_MSG_BULK_RX_DONE) ?
++ 'r' : 't',
++ queue->local_insert,
++ queue->remote_insert, queue->process);
++
++ DEBUG_TRACE(PARSE_LINE);
++ WARN_ON(queue->process == queue->local_insert);
++ vchiq_complete_bulk(bulk);
++ queue->process++;
++ mutex_unlock(&service->bulk_mutex);
++ DEBUG_TRACE(PARSE_LINE);
++ notify_bulks(service, queue, 1/*retry_poll*/);
++ DEBUG_TRACE(PARSE_LINE);
++ }
++ break;
++ case VCHIQ_MSG_PADDING:
++ vchiq_log_trace(vchiq_core_log_level,
++ "%d: prs PADDING@%x,%x",
++ state->id, (unsigned int)header, size);
++ break;
++ case VCHIQ_MSG_PAUSE:
++ /* If initiated, signal the application thread */
++ vchiq_log_trace(vchiq_core_log_level,
++ "%d: prs PAUSE@%x,%x",
++ state->id, (unsigned int)header, size);
++ if (state->conn_state == VCHIQ_CONNSTATE_PAUSED) {
++ vchiq_log_error(vchiq_core_log_level,
++ "%d: PAUSE received in state PAUSED",
++ state->id);
++ break;
++ }
++ if (state->conn_state != VCHIQ_CONNSTATE_PAUSE_SENT) {
++ /* Send a PAUSE in response */
++ if (queue_message(state, NULL,
++ VCHIQ_MAKE_MSG(VCHIQ_MSG_PAUSE, 0, 0),
++ NULL, 0, 0, QMFLAGS_NO_MUTEX_UNLOCK)
++ == VCHIQ_RETRY)
++ goto bail_not_ready;
++ if (state->is_master)
++ pause_bulks(state);
++ }
++ /* At this point slot_mutex is held */
++ vchiq_set_conn_state(state, VCHIQ_CONNSTATE_PAUSED);
++ vchiq_platform_paused(state);
++ break;
++ case VCHIQ_MSG_RESUME:
++ vchiq_log_trace(vchiq_core_log_level,
++ "%d: prs RESUME@%x,%x",
++ state->id, (unsigned int)header, size);
++ /* Release the slot mutex */
++ mutex_unlock(&state->slot_mutex);
++ if (state->is_master)
++ resume_bulks(state);
++ vchiq_set_conn_state(state, VCHIQ_CONNSTATE_CONNECTED);
++ vchiq_platform_resumed(state);
++ break;
++
++ case VCHIQ_MSG_REMOTE_USE:
++ vchiq_on_remote_use(state);
++ break;
++ case VCHIQ_MSG_REMOTE_RELEASE:
++ vchiq_on_remote_release(state);
++ break;
++ case VCHIQ_MSG_REMOTE_USE_ACTIVE:
++ vchiq_on_remote_use_active(state);
++ break;
++
++ default:
++ vchiq_log_error(vchiq_core_log_level,
++ "%d: prs invalid msgid %x@%x,%x",
++ state->id, msgid, (unsigned int)header, size);
++ WARN(1, "invalid message\n");
++ break;
++ }
++
++skip_message:
++ if (service) {
++ unlock_service(service);
++ service = NULL;
++ }
++
++ state->rx_pos += calc_stride(size);
++
++ DEBUG_TRACE(PARSE_LINE);
++ /* Perform some housekeeping when the end of the slot is
++ ** reached. */
++ if ((state->rx_pos & VCHIQ_SLOT_MASK) == 0) {
++ /* Remove the extra reference count. */
++ release_slot(state, state->rx_info, NULL, NULL);
++ state->rx_data = NULL;
++ }
++ }
++
++bail_not_ready:
++ if (service)
++ unlock_service(service);
++}
++
++/* Called by the slot handler thread */
++static int
++slot_handler_func(void *v)
++{
++ VCHIQ_STATE_T *state = (VCHIQ_STATE_T *) v;
++ VCHIQ_SHARED_STATE_T *local = state->local;
++ DEBUG_INITIALISE(local)
++
++ while (1) {
++ DEBUG_COUNT(SLOT_HANDLER_COUNT);
++ DEBUG_TRACE(SLOT_HANDLER_LINE);
++ remote_event_wait(&local->trigger);
++
++ rmb();
++
++ DEBUG_TRACE(SLOT_HANDLER_LINE);
++ if (state->poll_needed) {
++ /* Check if we need to suspend - may change our
++ * conn_state */
++ vchiq_platform_check_suspend(state);
++
++ state->poll_needed = 0;
++
++ /* Handle service polling and other rare conditions here
++ ** out of the mainline code */
++ switch (state->conn_state) {
++ case VCHIQ_CONNSTATE_CONNECTED:
++ /* Poll the services as requested */
++ poll_services(state);
++ break;
++
++ case VCHIQ_CONNSTATE_PAUSING:
++ if (state->is_master)
++ pause_bulks(state);
++ if (queue_message(state, NULL,
++ VCHIQ_MAKE_MSG(VCHIQ_MSG_PAUSE, 0, 0),
++ NULL, 0, 0,
++ QMFLAGS_NO_MUTEX_UNLOCK)
++ != VCHIQ_RETRY) {
++ vchiq_set_conn_state(state,
++ VCHIQ_CONNSTATE_PAUSE_SENT);
++ } else {
++ if (state->is_master)
++ resume_bulks(state);
++ /* Retry later */
++ state->poll_needed = 1;
++ }
++ break;
++
++ case VCHIQ_CONNSTATE_PAUSED:
++ vchiq_platform_resume(state);
++ break;
++
++ case VCHIQ_CONNSTATE_RESUMING:
++ if (queue_message(state, NULL,
++ VCHIQ_MAKE_MSG(VCHIQ_MSG_RESUME, 0, 0),
++ NULL, 0, 0, QMFLAGS_NO_MUTEX_LOCK)
++ != VCHIQ_RETRY) {
++ if (state->is_master)
++ resume_bulks(state);
++ vchiq_set_conn_state(state,
++ VCHIQ_CONNSTATE_CONNECTED);
++ vchiq_platform_resumed(state);
++ } else {
++ /* This should really be impossible,
++ ** since the PAUSE should have flushed
++ ** through outstanding messages. */
++ vchiq_log_error(vchiq_core_log_level,
++ "Failed to send RESUME "
++ "message");
++ BUG();
++ }
++ break;
++
++ case VCHIQ_CONNSTATE_PAUSE_TIMEOUT:
++ case VCHIQ_CONNSTATE_RESUME_TIMEOUT:
++ vchiq_platform_handle_timeout(state);
++ break;
++ default:
++ break;
++ }
++
++
++ }
++
++ DEBUG_TRACE(SLOT_HANDLER_LINE);
++ parse_rx_slots(state);
++ }
++ return 0;
++}
++
++
++/* Called by the recycle thread */
++static int
++recycle_func(void *v)
++{
++ VCHIQ_STATE_T *state = (VCHIQ_STATE_T *) v;
++ VCHIQ_SHARED_STATE_T *local = state->local;
++
++ while (1) {
++ remote_event_wait(&local->recycle);
++
++ process_free_queue(state);
++ }
++ return 0;
++}
++
++
++/* Called by the sync thread */
++static int
++sync_func(void *v)
++{
++ VCHIQ_STATE_T *state = (VCHIQ_STATE_T *) v;
++ VCHIQ_SHARED_STATE_T *local = state->local;
++ VCHIQ_HEADER_T *header = (VCHIQ_HEADER_T *)SLOT_DATA_FROM_INDEX(state,
++ state->remote->slot_sync);
++
++ while (1) {
++ VCHIQ_SERVICE_T *service;
++ int msgid, size;
++ int type;
++ unsigned int localport, remoteport;
++
++ remote_event_wait(&local->sync_trigger);
++
++ rmb();
++
++ msgid = header->msgid;
++ size = header->size;
++ type = VCHIQ_MSG_TYPE(msgid);
++ localport = VCHIQ_MSG_DSTPORT(msgid);
++ remoteport = VCHIQ_MSG_SRCPORT(msgid);
++
++ service = find_service_by_port(state, localport);
++
++ if (!service) {
++ vchiq_log_error(vchiq_sync_log_level,
++ "%d: sf %s@%x (%d->%d) - "
++ "invalid/closed service %d",
++ state->id, msg_type_str(type),
++ (unsigned int)header,
++ remoteport, localport, localport);
++ release_message_sync(state, header);
++ continue;
++ }
++
++ if (vchiq_sync_log_level >= VCHIQ_LOG_TRACE) {
++ int svc_fourcc;
++
++ svc_fourcc = service
++ ? service->base.fourcc
++ : VCHIQ_MAKE_FOURCC('?', '?', '?', '?');
++ vchiq_log_trace(vchiq_sync_log_level,
++ "Rcvd Msg %s from %c%c%c%c s:%d d:%d len:%d",
++ msg_type_str(type),
++ VCHIQ_FOURCC_AS_4CHARS(svc_fourcc),
++ remoteport, localport, size);
++ if (size > 0)
++ vchiq_log_dump_mem("Rcvd", 0, header->data,
++ min(64, size));
++ }
++
++ switch (type) {
++ case VCHIQ_MSG_OPENACK:
++ if (size >= sizeof(struct vchiq_openack_payload)) {
++ const struct vchiq_openack_payload *payload =
++ (struct vchiq_openack_payload *)
++ header->data;
++ service->peer_version = payload->version;
++ }
++ vchiq_log_info(vchiq_sync_log_level,
++ "%d: sf OPENACK@%x,%x (%d->%d) v:%d",
++ state->id, (unsigned int)header, size,
++ remoteport, localport, service->peer_version);
++ if (service->srvstate == VCHIQ_SRVSTATE_OPENING) {
++ service->remoteport = remoteport;
++ vchiq_set_service_state(service,
++ VCHIQ_SRVSTATE_OPENSYNC);
++ service->sync = 1;
++ up(&service->remove_event);
++ }
++ release_message_sync(state, header);
++ break;
++
++ case VCHIQ_MSG_DATA:
++ vchiq_log_trace(vchiq_sync_log_level,
++ "%d: sf DATA@%x,%x (%d->%d)",
++ state->id, (unsigned int)header, size,
++ remoteport, localport);
++
++ if ((service->remoteport == remoteport) &&
++ (service->srvstate ==
++ VCHIQ_SRVSTATE_OPENSYNC)) {
++ if (make_service_callback(service,
++ VCHIQ_MESSAGE_AVAILABLE, header,
++ NULL) == VCHIQ_RETRY)
++ vchiq_log_error(vchiq_sync_log_level,
++ "synchronous callback to "
++ "service %d returns "
++ "VCHIQ_RETRY",
++ localport);
++ }
++ break;
++
++ default:
++ vchiq_log_error(vchiq_sync_log_level,
++ "%d: sf unexpected msgid %x@%x,%x",
++ state->id, msgid, (unsigned int)header, size);
++ release_message_sync(state, header);
++ break;
++ }
++
++ unlock_service(service);
++ }
++
++ return 0;
++}
++
++
++static void
++init_bulk_queue(VCHIQ_BULK_QUEUE_T *queue)
++{
++ queue->local_insert = 0;
++ queue->remote_insert = 0;
++ queue->process = 0;
++ queue->remote_notify = 0;
++ queue->remove = 0;
++}
++
++
++inline const char *
++get_conn_state_name(VCHIQ_CONNSTATE_T conn_state)
++{
++ return conn_state_names[conn_state];
++}
++
++
++VCHIQ_SLOT_ZERO_T *
++vchiq_init_slots(void *mem_base, int mem_size)
++{
++ int mem_align = (VCHIQ_SLOT_SIZE - (int)mem_base) & VCHIQ_SLOT_MASK;
++ VCHIQ_SLOT_ZERO_T *slot_zero =
++ (VCHIQ_SLOT_ZERO_T *)((char *)mem_base + mem_align);
++ int num_slots = (mem_size - mem_align)/VCHIQ_SLOT_SIZE;
++ int first_data_slot = VCHIQ_SLOT_ZERO_SLOTS;
++
++ /* Ensure there is enough memory to run an absolutely minimum system */
++ num_slots -= first_data_slot;
++
++ if (num_slots < 4) {
++ vchiq_log_error(vchiq_core_log_level,
++ "vchiq_init_slots - insufficient memory %x bytes",
++ mem_size);
++ return NULL;
++ }
++
++ memset(slot_zero, 0, sizeof(VCHIQ_SLOT_ZERO_T));
++
++ slot_zero->magic = VCHIQ_MAGIC;
++ slot_zero->version = VCHIQ_VERSION;
++ slot_zero->version_min = VCHIQ_VERSION_MIN;
++ slot_zero->slot_zero_size = sizeof(VCHIQ_SLOT_ZERO_T);
++ slot_zero->slot_size = VCHIQ_SLOT_SIZE;
++ slot_zero->max_slots = VCHIQ_MAX_SLOTS;
++ slot_zero->max_slots_per_side = VCHIQ_MAX_SLOTS_PER_SIDE;
++
++ slot_zero->master.slot_sync = first_data_slot;
++ slot_zero->master.slot_first = first_data_slot + 1;
++ slot_zero->master.slot_last = first_data_slot + (num_slots/2) - 1;
++ slot_zero->slave.slot_sync = first_data_slot + (num_slots/2);
++ slot_zero->slave.slot_first = first_data_slot + (num_slots/2) + 1;
++ slot_zero->slave.slot_last = first_data_slot + num_slots - 1;
++
++ return slot_zero;
++}
++
++VCHIQ_STATUS_T
++vchiq_init_state(VCHIQ_STATE_T *state, VCHIQ_SLOT_ZERO_T *slot_zero,
++ int is_master)
++{
++ VCHIQ_SHARED_STATE_T *local;
++ VCHIQ_SHARED_STATE_T *remote;
++ VCHIQ_STATUS_T status;
++ char threadname[10];
++ static int id;
++ int i;
++
++ vchiq_log_warning(vchiq_core_log_level,
++ "%s: slot_zero = 0x%08lx, is_master = %d",
++ __func__, (unsigned long)slot_zero, is_master);
++
++ /* Check the input configuration */
++
++ if (slot_zero->magic != VCHIQ_MAGIC) {
++ vchiq_loud_error_header();
++ vchiq_loud_error("Invalid VCHIQ magic value found.");
++ vchiq_loud_error("slot_zero=%x: magic=%x (expected %x)",
++ (unsigned int)slot_zero, slot_zero->magic, VCHIQ_MAGIC);
++ vchiq_loud_error_footer();
++ return VCHIQ_ERROR;
++ }
++
++ if (slot_zero->version < VCHIQ_VERSION_MIN) {
++ vchiq_loud_error_header();
++ vchiq_loud_error("Incompatible VCHIQ versions found.");
++ vchiq_loud_error("slot_zero=%x: VideoCore version=%d "
++ "(minimum %d)",
++ (unsigned int)slot_zero, slot_zero->version,
++ VCHIQ_VERSION_MIN);
++ vchiq_loud_error("Restart with a newer VideoCore image.");
++ vchiq_loud_error_footer();
++ return VCHIQ_ERROR;
++ }
++
++ if (VCHIQ_VERSION < slot_zero->version_min) {
++ vchiq_loud_error_header();
++ vchiq_loud_error("Incompatible VCHIQ versions found.");
++ vchiq_loud_error("slot_zero=%x: version=%d (VideoCore "
++ "minimum %d)",
++ (unsigned int)slot_zero, VCHIQ_VERSION,
++ slot_zero->version_min);
++ vchiq_loud_error("Restart with a newer kernel.");
++ vchiq_loud_error_footer();
++ return VCHIQ_ERROR;
++ }
++
++ if ((slot_zero->slot_zero_size != sizeof(VCHIQ_SLOT_ZERO_T)) ||
++ (slot_zero->slot_size != VCHIQ_SLOT_SIZE) ||
++ (slot_zero->max_slots != VCHIQ_MAX_SLOTS) ||
++ (slot_zero->max_slots_per_side != VCHIQ_MAX_SLOTS_PER_SIDE)) {
++ vchiq_loud_error_header();
++ if (slot_zero->slot_zero_size != sizeof(VCHIQ_SLOT_ZERO_T))
++ vchiq_loud_error("slot_zero=%x: slot_zero_size=%x "
++ "(expected %x)",
++ (unsigned int)slot_zero,
++ slot_zero->slot_zero_size,
++ sizeof(VCHIQ_SLOT_ZERO_T));
++ if (slot_zero->slot_size != VCHIQ_SLOT_SIZE)
++ vchiq_loud_error("slot_zero=%x: slot_size=%d "
++ "(expected %d",
++ (unsigned int)slot_zero, slot_zero->slot_size,
++ VCHIQ_SLOT_SIZE);
++ if (slot_zero->max_slots != VCHIQ_MAX_SLOTS)
++ vchiq_loud_error("slot_zero=%x: max_slots=%d "
++ "(expected %d)",
++ (unsigned int)slot_zero, slot_zero->max_slots,
++ VCHIQ_MAX_SLOTS);
++ if (slot_zero->max_slots_per_side != VCHIQ_MAX_SLOTS_PER_SIDE)
++ vchiq_loud_error("slot_zero=%x: max_slots_per_side=%d "
++ "(expected %d)",
++ (unsigned int)slot_zero,
++ slot_zero->max_slots_per_side,
++ VCHIQ_MAX_SLOTS_PER_SIDE);
++ vchiq_loud_error_footer();
++ return VCHIQ_ERROR;
++ }
++
++ if (VCHIQ_VERSION < slot_zero->version)
++ slot_zero->version = VCHIQ_VERSION;
++
++ if (is_master) {
++ local = &slot_zero->master;
++ remote = &slot_zero->slave;
++ } else {
++ local = &slot_zero->slave;
++ remote = &slot_zero->master;
++ }
++
++ if (local->initialised) {
++ vchiq_loud_error_header();
++ if (remote->initialised)
++ vchiq_loud_error("local state has already been "
++ "initialised");
++ else
++ vchiq_loud_error("master/slave mismatch - two %ss",
++ is_master ? "master" : "slave");
++ vchiq_loud_error_footer();
++ return VCHIQ_ERROR;
++ }
++
++ memset(state, 0, sizeof(VCHIQ_STATE_T));
++
++ state->id = id++;
++ state->is_master = is_master;
++
++ /*
++ initialize shared state pointers
++ */
++
++ state->local = local;
++ state->remote = remote;
++ state->slot_data = (VCHIQ_SLOT_T *)slot_zero;
++
++ /*
++ initialize events and mutexes
++ */
++
++ sema_init(&state->connect, 0);
++ mutex_init(&state->mutex);
++ sema_init(&state->trigger_event, 0);
++ sema_init(&state->recycle_event, 0);
++ sema_init(&state->sync_trigger_event, 0);
++ sema_init(&state->sync_release_event, 0);
++
++ mutex_init(&state->slot_mutex);
++ mutex_init(&state->recycle_mutex);
++ mutex_init(&state->sync_mutex);
++ mutex_init(&state->bulk_transfer_mutex);
++
++ sema_init(&state->slot_available_event, 0);
++ sema_init(&state->slot_remove_event, 0);
++ sema_init(&state->data_quota_event, 0);
++
++ state->slot_queue_available = 0;
++
++ for (i = 0; i < VCHIQ_MAX_SERVICES; i++) {
++ VCHIQ_SERVICE_QUOTA_T *service_quota =
++ &state->service_quotas[i];
++ sema_init(&service_quota->quota_event, 0);
++ }
++
++ for (i = local->slot_first; i <= local->slot_last; i++) {
++ local->slot_queue[state->slot_queue_available++] = i;
++ up(&state->slot_available_event);
++ }
++
++ state->default_slot_quota = state->slot_queue_available/2;
++ state->default_message_quota =
++ min((unsigned short)(state->default_slot_quota * 256),
++ (unsigned short)~0);
++
++ state->previous_data_index = -1;
++ state->data_use_count = 0;
++ state->data_quota = state->slot_queue_available - 1;
++
++ local->trigger.event = &state->trigger_event;
++ remote_event_create(&local->trigger);
++ local->tx_pos = 0;
++
++ local->recycle.event = &state->recycle_event;
++ remote_event_create(&local->recycle);
++ local->slot_queue_recycle = state->slot_queue_available;
++
++ local->sync_trigger.event = &state->sync_trigger_event;
++ remote_event_create(&local->sync_trigger);
++
++ local->sync_release.event = &state->sync_release_event;
++ remote_event_create(&local->sync_release);
++
++ /* At start-of-day, the slot is empty and available */
++ ((VCHIQ_HEADER_T *)SLOT_DATA_FROM_INDEX(state, local->slot_sync))->msgid
++ = VCHIQ_MSGID_PADDING;
++ remote_event_signal_local(&local->sync_release);
++
++ local->debug[DEBUG_ENTRIES] = DEBUG_MAX;
++
++ status = vchiq_platform_init_state(state);
++
++ /*
++ bring up slot handler thread
++ */
++ snprintf(threadname, sizeof(threadname), "VCHIQ-%d", state->id);
++ state->slot_handler_thread = kthread_create(&slot_handler_func,
++ (void *)state,
++ threadname);
++
++ if (state->slot_handler_thread == NULL) {
++ vchiq_loud_error_header();
++ vchiq_loud_error("couldn't create thread %s", threadname);
++ vchiq_loud_error_footer();
++ return VCHIQ_ERROR;
++ }
++ set_user_nice(state->slot_handler_thread, -19);
++ wake_up_process(state->slot_handler_thread);
++
++ snprintf(threadname, sizeof(threadname), "VCHIQr-%d", state->id);
++ state->recycle_thread = kthread_create(&recycle_func,
++ (void *)state,
++ threadname);
++ if (state->recycle_thread == NULL) {
++ vchiq_loud_error_header();
++ vchiq_loud_error("couldn't create thread %s", threadname);
++ vchiq_loud_error_footer();
++ return VCHIQ_ERROR;
++ }
++ set_user_nice(state->recycle_thread, -19);
++ wake_up_process(state->recycle_thread);
++
++ snprintf(threadname, sizeof(threadname), "VCHIQs-%d", state->id);
++ state->sync_thread = kthread_create(&sync_func,
++ (void *)state,
++ threadname);
++ if (state->sync_thread == NULL) {
++ vchiq_loud_error_header();
++ vchiq_loud_error("couldn't create thread %s", threadname);
++ vchiq_loud_error_footer();
++ return VCHIQ_ERROR;
++ }
++ set_user_nice(state->sync_thread, -20);
++ wake_up_process(state->sync_thread);
++
++ BUG_ON(state->id >= VCHIQ_MAX_STATES);
++ vchiq_states[state->id] = state;
++
++ /* Indicate readiness to the other side */
++ local->initialised = 1;
++
++ return status;
++}
++
++/* Called from application thread when a client or server service is created. */
++VCHIQ_SERVICE_T *
++vchiq_add_service_internal(VCHIQ_STATE_T *state,
++ const VCHIQ_SERVICE_PARAMS_T *params, int srvstate,
++ VCHIQ_INSTANCE_T instance, VCHIQ_USERDATA_TERM_T userdata_term)
++{
++ VCHIQ_SERVICE_T *service;
++
++ service = kmalloc(sizeof(VCHIQ_SERVICE_T), GFP_KERNEL);
++ if (service) {
++ service->base.fourcc = params->fourcc;
++ service->base.callback = params->callback;
++ service->base.userdata = params->userdata;
++ service->handle = VCHIQ_SERVICE_HANDLE_INVALID;
++ service->ref_count = 1;
++ service->srvstate = VCHIQ_SRVSTATE_FREE;
++ service->userdata_term = userdata_term;
++ service->localport = VCHIQ_PORT_FREE;
++ service->remoteport = VCHIQ_PORT_FREE;
++
++ service->public_fourcc = (srvstate == VCHIQ_SRVSTATE_OPENING) ?
++ VCHIQ_FOURCC_INVALID : params->fourcc;
++ service->client_id = 0;
++ service->auto_close = 1;
++ service->sync = 0;
++ service->closing = 0;
++ service->trace = 0;
++ atomic_set(&service->poll_flags, 0);
++ service->version = params->version;
++ service->version_min = params->version_min;
++ service->state = state;
++ service->instance = instance;
++ service->service_use_count = 0;
++ init_bulk_queue(&service->bulk_tx);
++ init_bulk_queue(&service->bulk_rx);
++ sema_init(&service->remove_event, 0);
++ sema_init(&service->bulk_remove_event, 0);
++ mutex_init(&service->bulk_mutex);
++ memset(&service->stats, 0, sizeof(service->stats));
++ } else {
++ vchiq_log_error(vchiq_core_log_level,
++ "Out of memory");
++ }
++
++ if (service) {
++ VCHIQ_SERVICE_T **pservice = NULL;
++ int i;
++
++ /* Although it is perfectly possible to use service_spinlock
++ ** to protect the creation of services, it is overkill as it
++ ** disables interrupts while the array is searched.
++ ** The only danger is of another thread trying to create a
++ ** service - service deletion is safe.
++ ** Therefore it is preferable to use state->mutex which,
++ ** although slower to claim, doesn't block interrupts while
++ ** it is held.
++ */
++
++ mutex_lock(&state->mutex);
++
++ /* Prepare to use a previously unused service */
++ if (state->unused_service < VCHIQ_MAX_SERVICES)
++ pservice = &state->services[state->unused_service];
++
++ if (srvstate == VCHIQ_SRVSTATE_OPENING) {
++ for (i = 0; i < state->unused_service; i++) {
++ VCHIQ_SERVICE_T *srv = state->services[i];
++ if (!srv) {
++ pservice = &state->services[i];
++ break;
++ }
++ }
++ } else {
++ for (i = (state->unused_service - 1); i >= 0; i--) {
++ VCHIQ_SERVICE_T *srv = state->services[i];
++ if (!srv)
++ pservice = &state->services[i];
++ else if ((srv->public_fourcc == params->fourcc)
++ && ((srv->instance != instance) ||
++ (srv->base.callback !=
++ params->callback))) {
++ /* There is another server using this
++ ** fourcc which doesn't match. */
++ pservice = NULL;
++ break;
++ }
++ }
++ }
++
++ if (pservice) {
++ service->localport = (pservice - state->services);
++ if (!handle_seq)
++ handle_seq = VCHIQ_MAX_STATES *
++ VCHIQ_MAX_SERVICES;
++ service->handle = handle_seq |
++ (state->id * VCHIQ_MAX_SERVICES) |
++ service->localport;
++ handle_seq += VCHIQ_MAX_STATES * VCHIQ_MAX_SERVICES;
++ *pservice = service;
++ if (pservice == &state->services[state->unused_service])
++ state->unused_service++;
++ }
++
++ mutex_unlock(&state->mutex);
++
++ if (!pservice) {
++ kfree(service);
++ service = NULL;
++ }
++ }
++
++ if (service) {
++ VCHIQ_SERVICE_QUOTA_T *service_quota =
++ &state->service_quotas[service->localport];
++ service_quota->slot_quota = state->default_slot_quota;
++ service_quota->message_quota = state->default_message_quota;
++ if (service_quota->slot_use_count == 0)
++ service_quota->previous_tx_index =
++ SLOT_QUEUE_INDEX_FROM_POS(state->local_tx_pos)
++ - 1;
++
++ /* Bring this service online */
++ vchiq_set_service_state(service, srvstate);
++
++ vchiq_log_info(vchiq_core_msg_log_level,
++ "%s Service %c%c%c%c SrcPort:%d",
++ (srvstate == VCHIQ_SRVSTATE_OPENING)
++ ? "Open" : "Add",
++ VCHIQ_FOURCC_AS_4CHARS(params->fourcc),
++ service->localport);
++ }
++
++ /* Don't unlock the service - leave it with a ref_count of 1. */
++
++ return service;
++}
++
++VCHIQ_STATUS_T
++vchiq_open_service_internal(VCHIQ_SERVICE_T *service, int client_id)
++{
++ struct vchiq_open_payload payload = {
++ service->base.fourcc,
++ client_id,
++ service->version,
++ service->version_min
++ };
++ VCHIQ_ELEMENT_T body = { &payload, sizeof(payload) };
++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS;
++
++ service->client_id = client_id;
++ vchiq_use_service_internal(service);
++ status = queue_message(service->state, NULL,
++ VCHIQ_MAKE_MSG(VCHIQ_MSG_OPEN, service->localport, 0),
++ &body, 1, sizeof(payload), QMFLAGS_IS_BLOCKING);
++ if (status == VCHIQ_SUCCESS) {
++ /* Wait for the ACK/NAK */
++ if (down_interruptible(&service->remove_event) != 0) {
++ status = VCHIQ_RETRY;
++ vchiq_release_service_internal(service);
++ } else if ((service->srvstate != VCHIQ_SRVSTATE_OPEN) &&
++ (service->srvstate != VCHIQ_SRVSTATE_OPENSYNC)) {
++ if (service->srvstate != VCHIQ_SRVSTATE_CLOSEWAIT)
++ vchiq_log_error(vchiq_core_log_level,
++ "%d: osi - srvstate = %s (ref %d)",
++ service->state->id,
++ srvstate_names[service->srvstate],
++ service->ref_count);
++ status = VCHIQ_ERROR;
++ VCHIQ_SERVICE_STATS_INC(service, error_count);
++ vchiq_release_service_internal(service);
++ }
++ }
++ return status;
++}
++
++static void
++release_service_messages(VCHIQ_SERVICE_T *service)
++{
++ VCHIQ_STATE_T *state = service->state;
++ int slot_last = state->remote->slot_last;
++ int i;
++
++ /* Release any claimed messages aimed at this service */
++
++ if (service->sync) {
++ VCHIQ_HEADER_T *header =
++ (VCHIQ_HEADER_T *)SLOT_DATA_FROM_INDEX(state,
++ state->remote->slot_sync);
++ if (VCHIQ_MSG_DSTPORT(header->msgid) == service->localport)
++ release_message_sync(state, header);
++
++ return;
++ }
++
++ for (i = state->remote->slot_first; i <= slot_last; i++) {
++ VCHIQ_SLOT_INFO_T *slot_info =
++ SLOT_INFO_FROM_INDEX(state, i);
++ if (slot_info->release_count != slot_info->use_count) {
++ char *data =
++ (char *)SLOT_DATA_FROM_INDEX(state, i);
++ unsigned int pos, end;
++
++ end = VCHIQ_SLOT_SIZE;
++ if (data == state->rx_data)
++ /* This buffer is still being read from - stop
++ ** at the current read position */
++ end = state->rx_pos & VCHIQ_SLOT_MASK;
++
++ pos = 0;
++
++ while (pos < end) {
++ VCHIQ_HEADER_T *header =
++ (VCHIQ_HEADER_T *)(data + pos);
++ int msgid = header->msgid;
++ int port = VCHIQ_MSG_DSTPORT(msgid);
++ if ((port == service->localport) &&
++ (msgid & VCHIQ_MSGID_CLAIMED)) {
++ vchiq_log_info(vchiq_core_log_level,
++ " fsi - hdr %x",
++ (unsigned int)header);
++ release_slot(state, slot_info, header,
++ NULL);
++ }
++ pos += calc_stride(header->size);
++ if (pos > VCHIQ_SLOT_SIZE) {
++ vchiq_log_error(vchiq_core_log_level,
++ "fsi - pos %x: header %x, "
++ "msgid %x, header->msgid %x, "
++ "header->size %x",
++ pos, (unsigned int)header,
++ msgid, header->msgid,
++ header->size);
++ WARN(1, "invalid slot position\n");
++ }
++ }
++ }
++ }
++}
++
++static int
++do_abort_bulks(VCHIQ_SERVICE_T *service)
++{
++ VCHIQ_STATUS_T status;
++
++ /* Abort any outstanding bulk transfers */
++ if (mutex_lock_interruptible(&service->bulk_mutex) != 0)
++ return 0;
++ abort_outstanding_bulks(service, &service->bulk_tx);
++ abort_outstanding_bulks(service, &service->bulk_rx);
++ mutex_unlock(&service->bulk_mutex);
++
++ status = notify_bulks(service, &service->bulk_tx, 0/*!retry_poll*/);
++ if (status == VCHIQ_SUCCESS)
++ status = notify_bulks(service, &service->bulk_rx,
++ 0/*!retry_poll*/);
++ return (status == VCHIQ_SUCCESS);
++}
++
++static VCHIQ_STATUS_T
++close_service_complete(VCHIQ_SERVICE_T *service, int failstate)
++{
++ VCHIQ_STATUS_T status;
++ int is_server = (service->public_fourcc != VCHIQ_FOURCC_INVALID);
++ int newstate;
++
++ switch (service->srvstate) {
++ case VCHIQ_SRVSTATE_OPEN:
++ case VCHIQ_SRVSTATE_CLOSESENT:
++ case VCHIQ_SRVSTATE_CLOSERECVD:
++ if (is_server) {
++ if (service->auto_close) {
++ service->client_id = 0;
++ service->remoteport = VCHIQ_PORT_FREE;
++ newstate = VCHIQ_SRVSTATE_LISTENING;
++ } else
++ newstate = VCHIQ_SRVSTATE_CLOSEWAIT;
++ } else
++ newstate = VCHIQ_SRVSTATE_CLOSED;
++ vchiq_set_service_state(service, newstate);
++ break;
++ case VCHIQ_SRVSTATE_LISTENING:
++ break;
++ default:
++ vchiq_log_error(vchiq_core_log_level,
++ "close_service_complete(%x) called in state %s",
++ service->handle, srvstate_names[service->srvstate]);
++ WARN(1, "close_service_complete in unexpected state\n");
++ return VCHIQ_ERROR;
++ }
++
++ status = make_service_callback(service,
++ VCHIQ_SERVICE_CLOSED, NULL, NULL);
++
++ if (status != VCHIQ_RETRY) {
++ int uc = service->service_use_count;
++ int i;
++ /* Complete the close process */
++ for (i = 0; i < uc; i++)
++ /* cater for cases where close is forced and the
++ ** client may not close all it's handles */
++ vchiq_release_service_internal(service);
++
++ service->client_id = 0;
++ service->remoteport = VCHIQ_PORT_FREE;
++
++ if (service->srvstate == VCHIQ_SRVSTATE_CLOSED)
++ vchiq_free_service_internal(service);
++ else if (service->srvstate != VCHIQ_SRVSTATE_CLOSEWAIT) {
++ if (is_server)
++ service->closing = 0;
++
++ up(&service->remove_event);
++ }
++ } else
++ vchiq_set_service_state(service, failstate);
++
++ return status;
++}
++
++/* Called by the slot handler */
++VCHIQ_STATUS_T
++vchiq_close_service_internal(VCHIQ_SERVICE_T *service, int close_recvd)
++{
++ VCHIQ_STATE_T *state = service->state;
++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS;
++ int is_server = (service->public_fourcc != VCHIQ_FOURCC_INVALID);
++
++ vchiq_log_info(vchiq_core_log_level, "%d: csi:%d,%d (%s)",
++ service->state->id, service->localport, close_recvd,
++ srvstate_names[service->srvstate]);
++
++ switch (service->srvstate) {
++ case VCHIQ_SRVSTATE_CLOSED:
++ case VCHIQ_SRVSTATE_HIDDEN:
++ case VCHIQ_SRVSTATE_LISTENING:
++ case VCHIQ_SRVSTATE_CLOSEWAIT:
++ if (close_recvd)
++ vchiq_log_error(vchiq_core_log_level,
++ "vchiq_close_service_internal(1) called "
++ "in state %s",
++ srvstate_names[service->srvstate]);
++ else if (is_server) {
++ if (service->srvstate == VCHIQ_SRVSTATE_LISTENING) {
++ status = VCHIQ_ERROR;
++ } else {
++ service->client_id = 0;
++ service->remoteport = VCHIQ_PORT_FREE;
++ if (service->srvstate ==
++ VCHIQ_SRVSTATE_CLOSEWAIT)
++ vchiq_set_service_state(service,
++ VCHIQ_SRVSTATE_LISTENING);
++ }
++ up(&service->remove_event);
++ } else
++ vchiq_free_service_internal(service);
++ break;
++ case VCHIQ_SRVSTATE_OPENING:
++ if (close_recvd) {
++ /* The open was rejected - tell the user */
++ vchiq_set_service_state(service,
++ VCHIQ_SRVSTATE_CLOSEWAIT);
++ up(&service->remove_event);
++ } else {
++ /* Shutdown mid-open - let the other side know */
++ status = queue_message(state, service,
++ VCHIQ_MAKE_MSG
++ (VCHIQ_MSG_CLOSE,
++ service->localport,
++ VCHIQ_MSG_DSTPORT(service->remoteport)),
++ NULL, 0, 0, 0);
++ }
++ break;
++
++ case VCHIQ_SRVSTATE_OPENSYNC:
++ mutex_lock(&state->sync_mutex);
++ /* Drop through */
++
++ case VCHIQ_SRVSTATE_OPEN:
++ if (state->is_master || close_recvd) {
++ if (!do_abort_bulks(service))
++ status = VCHIQ_RETRY;
++ }
++
++ release_service_messages(service);
++
++ if (status == VCHIQ_SUCCESS)
++ status = queue_message(state, service,
++ VCHIQ_MAKE_MSG
++ (VCHIQ_MSG_CLOSE,
++ service->localport,
++ VCHIQ_MSG_DSTPORT(service->remoteport)),
++ NULL, 0, 0, QMFLAGS_NO_MUTEX_UNLOCK);
++
++ if (status == VCHIQ_SUCCESS) {
++ if (!close_recvd) {
++ /* Change the state while the mutex is
++ still held */
++ vchiq_set_service_state(service,
++ VCHIQ_SRVSTATE_CLOSESENT);
++ mutex_unlock(&state->slot_mutex);
++ if (service->sync)
++ mutex_unlock(&state->sync_mutex);
++ break;
++ }
++ } else if (service->srvstate == VCHIQ_SRVSTATE_OPENSYNC) {
++ mutex_unlock(&state->sync_mutex);
++ break;
++ } else
++ break;
++
++ /* Change the state while the mutex is still held */
++ vchiq_set_service_state(service, VCHIQ_SRVSTATE_CLOSERECVD);
++ mutex_unlock(&state->slot_mutex);
++ if (service->sync)
++ mutex_unlock(&state->sync_mutex);
++
++ status = close_service_complete(service,
++ VCHIQ_SRVSTATE_CLOSERECVD);
++ break;
++
++ case VCHIQ_SRVSTATE_CLOSESENT:
++ if (!close_recvd)
++ /* This happens when a process is killed mid-close */
++ break;
++
++ if (!state->is_master) {
++ if (!do_abort_bulks(service)) {
++ status = VCHIQ_RETRY;
++ break;
++ }
++ }
++
++ if (status == VCHIQ_SUCCESS)
++ status = close_service_complete(service,
++ VCHIQ_SRVSTATE_CLOSERECVD);
++ break;
++
++ case VCHIQ_SRVSTATE_CLOSERECVD:
++ if (!close_recvd && is_server)
++ /* Force into LISTENING mode */
++ vchiq_set_service_state(service,
++ VCHIQ_SRVSTATE_LISTENING);
++ status = close_service_complete(service,
++ VCHIQ_SRVSTATE_CLOSERECVD);
++ break;
++
++ default:
++ vchiq_log_error(vchiq_core_log_level,
++ "vchiq_close_service_internal(%d) called in state %s",
++ close_recvd, srvstate_names[service->srvstate]);
++ break;
++ }
++
++ return status;
++}
++
++/* Called from the application process upon process death */
++void
++vchiq_terminate_service_internal(VCHIQ_SERVICE_T *service)
++{
++ VCHIQ_STATE_T *state = service->state;
++
++ vchiq_log_info(vchiq_core_log_level, "%d: tsi - (%d<->%d)",
++ state->id, service->localport, service->remoteport);
++
++ mark_service_closing(service);
++
++ /* Mark the service for removal by the slot handler */
++ request_poll(state, service, VCHIQ_POLL_REMOVE);
++}
++
++/* Called from the slot handler */
++void
++vchiq_free_service_internal(VCHIQ_SERVICE_T *service)
++{
++ VCHIQ_STATE_T *state = service->state;
++
++ vchiq_log_info(vchiq_core_log_level, "%d: fsi - (%d)",
++ state->id, service->localport);
++
++ switch (service->srvstate) {
++ case VCHIQ_SRVSTATE_OPENING:
++ case VCHIQ_SRVSTATE_CLOSED:
++ case VCHIQ_SRVSTATE_HIDDEN:
++ case VCHIQ_SRVSTATE_LISTENING:
++ case VCHIQ_SRVSTATE_CLOSEWAIT:
++ break;
++ default:
++ vchiq_log_error(vchiq_core_log_level,
++ "%d: fsi - (%d) in state %s",
++ state->id, service->localport,
++ srvstate_names[service->srvstate]);
++ return;
++ }
++
++ vchiq_set_service_state(service, VCHIQ_SRVSTATE_FREE);
++
++ up(&service->remove_event);
++
++ /* Release the initial lock */
++ unlock_service(service);
++}
++
++VCHIQ_STATUS_T
++vchiq_connect_internal(VCHIQ_STATE_T *state, VCHIQ_INSTANCE_T instance)
++{
++ VCHIQ_SERVICE_T *service;
++ int i;
++
++ /* Find all services registered to this client and enable them. */
++ i = 0;
++ while ((service = next_service_by_instance(state, instance,
++ &i)) != NULL) {
++ if (service->srvstate == VCHIQ_SRVSTATE_HIDDEN)
++ vchiq_set_service_state(service,
++ VCHIQ_SRVSTATE_LISTENING);
++ unlock_service(service);
++ }
++
++ if (state->conn_state == VCHIQ_CONNSTATE_DISCONNECTED) {
++ if (queue_message(state, NULL,
++ VCHIQ_MAKE_MSG(VCHIQ_MSG_CONNECT, 0, 0), NULL, 0,
++ 0, QMFLAGS_IS_BLOCKING) == VCHIQ_RETRY)
++ return VCHIQ_RETRY;
++
++ vchiq_set_conn_state(state, VCHIQ_CONNSTATE_CONNECTING);
++ }
++
++ if (state->conn_state == VCHIQ_CONNSTATE_CONNECTING) {
++ if (down_interruptible(&state->connect) != 0)
++ return VCHIQ_RETRY;
++
++ vchiq_set_conn_state(state, VCHIQ_CONNSTATE_CONNECTED);
++ up(&state->connect);
++ }
++
++ return VCHIQ_SUCCESS;
++}
++
++VCHIQ_STATUS_T
++vchiq_shutdown_internal(VCHIQ_STATE_T *state, VCHIQ_INSTANCE_T instance)
++{
++ VCHIQ_SERVICE_T *service;
++ int i;
++
++ /* Find all services registered to this client and enable them. */
++ i = 0;
++ while ((service = next_service_by_instance(state, instance,
++ &i)) != NULL) {
++ (void)vchiq_remove_service(service->handle);
++ unlock_service(service);
++ }
++
++ return VCHIQ_SUCCESS;
++}
++
++VCHIQ_STATUS_T
++vchiq_pause_internal(VCHIQ_STATE_T *state)
++{
++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS;
++
++ switch (state->conn_state) {
++ case VCHIQ_CONNSTATE_CONNECTED:
++ /* Request a pause */
++ vchiq_set_conn_state(state, VCHIQ_CONNSTATE_PAUSING);
++ request_poll(state, NULL, 0);
++ break;
++ default:
++ vchiq_log_error(vchiq_core_log_level,
++ "vchiq_pause_internal in state %s\n",
++ conn_state_names[state->conn_state]);
++ status = VCHIQ_ERROR;
++ VCHIQ_STATS_INC(state, error_count);
++ break;
++ }
++
++ return status;
++}
++
++VCHIQ_STATUS_T
++vchiq_resume_internal(VCHIQ_STATE_T *state)
++{
++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS;
++
++ if (state->conn_state == VCHIQ_CONNSTATE_PAUSED) {
++ vchiq_set_conn_state(state, VCHIQ_CONNSTATE_RESUMING);
++ request_poll(state, NULL, 0);
++ } else {
++ status = VCHIQ_ERROR;
++ VCHIQ_STATS_INC(state, error_count);
++ }
++
++ return status;
++}
++
++VCHIQ_STATUS_T
++vchiq_close_service(VCHIQ_SERVICE_HANDLE_T handle)
++{
++ /* Unregister the service */
++ VCHIQ_SERVICE_T *service = find_service_by_handle(handle);
++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS;
++
++ if (!service)
++ return VCHIQ_ERROR;
++
++ vchiq_log_info(vchiq_core_log_level,
++ "%d: close_service:%d",
++ service->state->id, service->localport);
++
++ if ((service->srvstate == VCHIQ_SRVSTATE_FREE) ||
++ (service->srvstate == VCHIQ_SRVSTATE_LISTENING) ||
++ (service->srvstate == VCHIQ_SRVSTATE_HIDDEN)) {
++ unlock_service(service);
++ return VCHIQ_ERROR;
++ }
++
++ mark_service_closing(service);
++
++ if (current == service->state->slot_handler_thread) {
++ status = vchiq_close_service_internal(service,
++ 0/*!close_recvd*/);
++ BUG_ON(status == VCHIQ_RETRY);
++ } else {
++ /* Mark the service for termination by the slot handler */
++ request_poll(service->state, service, VCHIQ_POLL_TERMINATE);
++ }
++
++ while (1) {
++ if (down_interruptible(&service->remove_event) != 0) {
++ status = VCHIQ_RETRY;
++ break;
++ }
++
++ if ((service->srvstate == VCHIQ_SRVSTATE_FREE) ||
++ (service->srvstate == VCHIQ_SRVSTATE_LISTENING) ||
++ (service->srvstate == VCHIQ_SRVSTATE_OPEN))
++ break;
++
++ vchiq_log_warning(vchiq_core_log_level,
++ "%d: close_service:%d - waiting in state %s",
++ service->state->id, service->localport,
++ srvstate_names[service->srvstate]);
++ }
++
++ if ((status == VCHIQ_SUCCESS) &&
++ (service->srvstate != VCHIQ_SRVSTATE_FREE) &&
++ (service->srvstate != VCHIQ_SRVSTATE_LISTENING))
++ status = VCHIQ_ERROR;
++
++ unlock_service(service);
++
++ return status;
++}
++
++VCHIQ_STATUS_T
++vchiq_remove_service(VCHIQ_SERVICE_HANDLE_T handle)
++{
++ /* Unregister the service */
++ VCHIQ_SERVICE_T *service = find_service_by_handle(handle);
++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS;
++
++ if (!service)
++ return VCHIQ_ERROR;
++
++ vchiq_log_info(vchiq_core_log_level,
++ "%d: remove_service:%d",
++ service->state->id, service->localport);
++
++ if (service->srvstate == VCHIQ_SRVSTATE_FREE) {
++ unlock_service(service);
++ return VCHIQ_ERROR;
++ }
++
++ mark_service_closing(service);
++
++ if ((service->srvstate == VCHIQ_SRVSTATE_HIDDEN) ||
++ (current == service->state->slot_handler_thread)) {
++ /* Make it look like a client, because it must be removed and
++ not left in the LISTENING state. */
++ service->public_fourcc = VCHIQ_FOURCC_INVALID;
++
++ status = vchiq_close_service_internal(service,
++ 0/*!close_recvd*/);
++ BUG_ON(status == VCHIQ_RETRY);
++ } else {
++ /* Mark the service for removal by the slot handler */
++ request_poll(service->state, service, VCHIQ_POLL_REMOVE);
++ }
++ while (1) {
++ if (down_interruptible(&service->remove_event) != 0) {
++ status = VCHIQ_RETRY;
++ break;
++ }
++
++ if ((service->srvstate == VCHIQ_SRVSTATE_FREE) ||
++ (service->srvstate == VCHIQ_SRVSTATE_OPEN))
++ break;
++
++ vchiq_log_warning(vchiq_core_log_level,
++ "%d: remove_service:%d - waiting in state %s",
++ service->state->id, service->localport,
++ srvstate_names[service->srvstate]);
++ }
++
++ if ((status == VCHIQ_SUCCESS) &&
++ (service->srvstate != VCHIQ_SRVSTATE_FREE))
++ status = VCHIQ_ERROR;
++
++ unlock_service(service);
++
++ return status;
++}
++
++
++/* This function may be called by kernel threads or user threads.
++ * User threads may receive VCHIQ_RETRY to indicate that a signal has been
++ * received and the call should be retried after being returned to user
++ * context.
++ * When called in blocking mode, the userdata field points to a bulk_waiter
++ * structure.
++ */
++VCHIQ_STATUS_T
++vchiq_bulk_transfer(VCHIQ_SERVICE_HANDLE_T handle,
++ VCHI_MEM_HANDLE_T memhandle, void *offset, int size, void *userdata,
++ VCHIQ_BULK_MODE_T mode, VCHIQ_BULK_DIR_T dir)
++{
++ VCHIQ_SERVICE_T *service = find_service_by_handle(handle);
++ VCHIQ_BULK_QUEUE_T *queue;
++ VCHIQ_BULK_T *bulk;
++ VCHIQ_STATE_T *state;
++ struct bulk_waiter *bulk_waiter = NULL;
++ const char dir_char = (dir == VCHIQ_BULK_TRANSMIT) ? 't' : 'r';
++ const int dir_msgtype = (dir == VCHIQ_BULK_TRANSMIT) ?
++ VCHIQ_MSG_BULK_TX : VCHIQ_MSG_BULK_RX;
++ VCHIQ_STATUS_T status = VCHIQ_ERROR;
++
++ if (!service ||
++ (service->srvstate != VCHIQ_SRVSTATE_OPEN) ||
++ ((memhandle == VCHI_MEM_HANDLE_INVALID) && (offset == NULL)) ||
++ (vchiq_check_service(service) != VCHIQ_SUCCESS))
++ goto error_exit;
++
++ switch (mode) {
++ case VCHIQ_BULK_MODE_NOCALLBACK:
++ case VCHIQ_BULK_MODE_CALLBACK:
++ break;
++ case VCHIQ_BULK_MODE_BLOCKING:
++ bulk_waiter = (struct bulk_waiter *)userdata;
++ sema_init(&bulk_waiter->event, 0);
++ bulk_waiter->actual = 0;
++ bulk_waiter->bulk = NULL;
++ break;
++ case VCHIQ_BULK_MODE_WAITING:
++ bulk_waiter = (struct bulk_waiter *)userdata;
++ bulk = bulk_waiter->bulk;
++ goto waiting;
++ default:
++ goto error_exit;
++ }
++
++ state = service->state;
++
++ queue = (dir == VCHIQ_BULK_TRANSMIT) ?
++ &service->bulk_tx : &service->bulk_rx;
++
++ if (mutex_lock_interruptible(&service->bulk_mutex) != 0) {
++ status = VCHIQ_RETRY;
++ goto error_exit;
++ }
++
++ if (queue->local_insert == queue->remove + VCHIQ_NUM_SERVICE_BULKS) {
++ VCHIQ_SERVICE_STATS_INC(service, bulk_stalls);
++ do {
++ mutex_unlock(&service->bulk_mutex);
++ if (down_interruptible(&service->bulk_remove_event)
++ != 0) {
++ status = VCHIQ_RETRY;
++ goto error_exit;
++ }
++ if (mutex_lock_interruptible(&service->bulk_mutex)
++ != 0) {
++ status = VCHIQ_RETRY;
++ goto error_exit;
++ }
++ } while (queue->local_insert == queue->remove +
++ VCHIQ_NUM_SERVICE_BULKS);
++ }
++
++ bulk = &queue->bulks[BULK_INDEX(queue->local_insert)];
++
++ bulk->mode = mode;
++ bulk->dir = dir;
++ bulk->userdata = userdata;
++ bulk->size = size;
++ bulk->actual = VCHIQ_BULK_ACTUAL_ABORTED;
++
++ if (vchiq_prepare_bulk_data(bulk, memhandle, offset, size, dir) !=
++ VCHIQ_SUCCESS)
++ goto unlock_error_exit;
++
++ wmb();
++
++ vchiq_log_info(vchiq_core_log_level,
++ "%d: bt (%d->%d) %cx %x@%x %x",
++ state->id,
++ service->localport, service->remoteport, dir_char,
++ size, (unsigned int)bulk->data, (unsigned int)userdata);
++
++ /* The slot mutex must be held when the service is being closed, so
++ claim it here to ensure that isn't happening */
++ if (mutex_lock_interruptible(&state->slot_mutex) != 0) {
++ status = VCHIQ_RETRY;
++ goto cancel_bulk_error_exit;
++ }
++
++ if (service->srvstate != VCHIQ_SRVSTATE_OPEN)
++ goto unlock_both_error_exit;
++
++ if (state->is_master) {
++ queue->local_insert++;
++ if (resolve_bulks(service, queue))
++ request_poll(state, service,
++ (dir == VCHIQ_BULK_TRANSMIT) ?
++ VCHIQ_POLL_TXNOTIFY : VCHIQ_POLL_RXNOTIFY);
++ } else {
++ int payload[2] = { (int)bulk->data, bulk->size };
++ VCHIQ_ELEMENT_T element = { payload, sizeof(payload) };
++
++ status = queue_message(state, NULL,
++ VCHIQ_MAKE_MSG(dir_msgtype,
++ service->localport, service->remoteport),
++ &element, 1, sizeof(payload),
++ QMFLAGS_IS_BLOCKING |
++ QMFLAGS_NO_MUTEX_LOCK |
++ QMFLAGS_NO_MUTEX_UNLOCK);
++ if (status != VCHIQ_SUCCESS) {
++ goto unlock_both_error_exit;
++ }
++ queue->local_insert++;
++ }
++
++ mutex_unlock(&state->slot_mutex);
++ mutex_unlock(&service->bulk_mutex);
++
++ vchiq_log_trace(vchiq_core_log_level,
++ "%d: bt:%d %cx li=%x ri=%x p=%x",
++ state->id,
++ service->localport, dir_char,
++ queue->local_insert, queue->remote_insert, queue->process);
++
++waiting:
++ unlock_service(service);
++
++ status = VCHIQ_SUCCESS;
++
++ if (bulk_waiter) {
++ bulk_waiter->bulk = bulk;
++ if (down_interruptible(&bulk_waiter->event) != 0)
++ status = VCHIQ_RETRY;
++ else if (bulk_waiter->actual == VCHIQ_BULK_ACTUAL_ABORTED)
++ status = VCHIQ_ERROR;
++ }
++
++ return status;
++
++unlock_both_error_exit:
++ mutex_unlock(&state->slot_mutex);
++cancel_bulk_error_exit:
++ vchiq_complete_bulk(bulk);
++unlock_error_exit:
++ mutex_unlock(&service->bulk_mutex);
++
++error_exit:
++ if (service)
++ unlock_service(service);
++ return status;
++}
++
++VCHIQ_STATUS_T
++vchiq_queue_message(VCHIQ_SERVICE_HANDLE_T handle,
++ const VCHIQ_ELEMENT_T *elements, unsigned int count)
++{
++ VCHIQ_SERVICE_T *service = find_service_by_handle(handle);
++ VCHIQ_STATUS_T status = VCHIQ_ERROR;
++
++ unsigned int size = 0;
++ unsigned int i;
++
++ if (!service ||
++ (vchiq_check_service(service) != VCHIQ_SUCCESS))
++ goto error_exit;
++
++ for (i = 0; i < (unsigned int)count; i++) {
++ if (elements[i].size) {
++ if (elements[i].data == NULL) {
++ VCHIQ_SERVICE_STATS_INC(service, error_count);
++ goto error_exit;
++ }
++ size += elements[i].size;
++ }
++ }
++
++ if (size > VCHIQ_MAX_MSG_SIZE) {
++ VCHIQ_SERVICE_STATS_INC(service, error_count);
++ goto error_exit;
++ }
++
++ switch (service->srvstate) {
++ case VCHIQ_SRVSTATE_OPEN:
++ status = queue_message(service->state, service,
++ VCHIQ_MAKE_MSG(VCHIQ_MSG_DATA,
++ service->localport,
++ service->remoteport),
++ elements, count, size, 1);
++ break;
++ case VCHIQ_SRVSTATE_OPENSYNC:
++ status = queue_message_sync(service->state, service,
++ VCHIQ_MAKE_MSG(VCHIQ_MSG_DATA,
++ service->localport,
++ service->remoteport),
++ elements, count, size, 1);
++ break;
++ default:
++ status = VCHIQ_ERROR;
++ break;
++ }
++
++error_exit:
++ if (service)
++ unlock_service(service);
++
++ return status;
++}
++
++void
++vchiq_release_message(VCHIQ_SERVICE_HANDLE_T handle, VCHIQ_HEADER_T *header)
++{
++ VCHIQ_SERVICE_T *service = find_service_by_handle(handle);
++ VCHIQ_SHARED_STATE_T *remote;
++ VCHIQ_STATE_T *state;
++ int slot_index;
++
++ if (!service)
++ return;
++
++ state = service->state;
++ remote = state->remote;
++
++ slot_index = SLOT_INDEX_FROM_DATA(state, (void *)header);
++
++ if ((slot_index >= remote->slot_first) &&
++ (slot_index <= remote->slot_last)) {
++ int msgid = header->msgid;
++ if (msgid & VCHIQ_MSGID_CLAIMED) {
++ VCHIQ_SLOT_INFO_T *slot_info =
++ SLOT_INFO_FROM_INDEX(state, slot_index);
++
++ release_slot(state, slot_info, header, service);
++ }
++ } else if (slot_index == remote->slot_sync)
++ release_message_sync(state, header);
++
++ unlock_service(service);
++}
++
++static void
++release_message_sync(VCHIQ_STATE_T *state, VCHIQ_HEADER_T *header)
++{
++ header->msgid = VCHIQ_MSGID_PADDING;
++ wmb();
++ remote_event_signal(&state->remote->sync_release);
++}
++
++VCHIQ_STATUS_T
++vchiq_get_peer_version(VCHIQ_SERVICE_HANDLE_T handle, short *peer_version)
++{
++ VCHIQ_STATUS_T status = VCHIQ_ERROR;
++ VCHIQ_SERVICE_T *service = find_service_by_handle(handle);
++
++ if (!service ||
++ (vchiq_check_service(service) != VCHIQ_SUCCESS) ||
++ !peer_version)
++ goto exit;
++ *peer_version = service->peer_version;
++ status = VCHIQ_SUCCESS;
++
++exit:
++ if (service)
++ unlock_service(service);
++ return status;
++}
++
++VCHIQ_STATUS_T
++vchiq_get_config(VCHIQ_INSTANCE_T instance,
++ int config_size, VCHIQ_CONFIG_T *pconfig)
++{
++ VCHIQ_CONFIG_T config;
++
++ (void)instance;
++
++ config.max_msg_size = VCHIQ_MAX_MSG_SIZE;
++ config.bulk_threshold = VCHIQ_MAX_MSG_SIZE;
++ config.max_outstanding_bulks = VCHIQ_NUM_SERVICE_BULKS;
++ config.max_services = VCHIQ_MAX_SERVICES;
++ config.version = VCHIQ_VERSION;
++ config.version_min = VCHIQ_VERSION_MIN;
++
++ if (config_size > sizeof(VCHIQ_CONFIG_T))
++ return VCHIQ_ERROR;
++
++ memcpy(pconfig, &config,
++ min(config_size, (int)(sizeof(VCHIQ_CONFIG_T))));
++
++ return VCHIQ_SUCCESS;
++}
++
++VCHIQ_STATUS_T
++vchiq_set_service_option(VCHIQ_SERVICE_HANDLE_T handle,
++ VCHIQ_SERVICE_OPTION_T option, int value)
++{
++ VCHIQ_SERVICE_T *service = find_service_by_handle(handle);
++ VCHIQ_STATUS_T status = VCHIQ_ERROR;
++
++ if (service) {
++ switch (option) {
++ case VCHIQ_SERVICE_OPTION_AUTOCLOSE:
++ service->auto_close = value;
++ status = VCHIQ_SUCCESS;
++ break;
++
++ case VCHIQ_SERVICE_OPTION_SLOT_QUOTA: {
++ VCHIQ_SERVICE_QUOTA_T *service_quota =
++ &service->state->service_quotas[
++ service->localport];
++ if (value == 0)
++ value = service->state->default_slot_quota;
++ if ((value >= service_quota->slot_use_count) &&
++ (value < (unsigned short)~0)) {
++ service_quota->slot_quota = value;
++ if ((value >= service_quota->slot_use_count) &&
++ (service_quota->message_quota >=
++ service_quota->message_use_count)) {
++ /* Signal the service that it may have
++ ** dropped below its quota */
++ up(&service_quota->quota_event);
++ }
++ status = VCHIQ_SUCCESS;
++ }
++ } break;
++
++ case VCHIQ_SERVICE_OPTION_MESSAGE_QUOTA: {
++ VCHIQ_SERVICE_QUOTA_T *service_quota =
++ &service->state->service_quotas[
++ service->localport];
++ if (value == 0)
++ value = service->state->default_message_quota;
++ if ((value >= service_quota->message_use_count) &&
++ (value < (unsigned short)~0)) {
++ service_quota->message_quota = value;
++ if ((value >=
++ service_quota->message_use_count) &&
++ (service_quota->slot_quota >=
++ service_quota->slot_use_count))
++ /* Signal the service that it may have
++ ** dropped below its quota */
++ up(&service_quota->quota_event);
++ status = VCHIQ_SUCCESS;
++ }
++ } break;
++
++ case VCHIQ_SERVICE_OPTION_SYNCHRONOUS:
++ if ((service->srvstate == VCHIQ_SRVSTATE_HIDDEN) ||
++ (service->srvstate ==
++ VCHIQ_SRVSTATE_LISTENING)) {
++ service->sync = value;
++ status = VCHIQ_SUCCESS;
++ }
++ break;
++
++ case VCHIQ_SERVICE_OPTION_TRACE:
++ service->trace = value;
++ status = VCHIQ_SUCCESS;
++ break;
++
++ default:
++ break;
++ }
++ unlock_service(service);
++ }
++
++ return status;
++}
++
++void
++vchiq_dump_shared_state(void *dump_context, VCHIQ_STATE_T *state,
++ VCHIQ_SHARED_STATE_T *shared, const char *label)
++{
++ static const char *const debug_names[] = {
++ "<entries>",
++ "SLOT_HANDLER_COUNT",
++ "SLOT_HANDLER_LINE",
++ "PARSE_LINE",
++ "PARSE_HEADER",
++ "PARSE_MSGID",
++ "AWAIT_COMPLETION_LINE",
++ "DEQUEUE_MESSAGE_LINE",
++ "SERVICE_CALLBACK_LINE",
++ "MSG_QUEUE_FULL_COUNT",
++ "COMPLETION_QUEUE_FULL_COUNT"
++ };
++ int i;
++
++ char buf[80];
++ int len;
++ len = snprintf(buf, sizeof(buf),
++ " %s: slots %d-%d tx_pos=%x recycle=%x",
++ label, shared->slot_first, shared->slot_last,
++ shared->tx_pos, shared->slot_queue_recycle);
++ vchiq_dump(dump_context, buf, len + 1);
++
++ len = snprintf(buf, sizeof(buf),
++ " Slots claimed:");
++ vchiq_dump(dump_context, buf, len + 1);
++
++ for (i = shared->slot_first; i <= shared->slot_last; i++) {
++ VCHIQ_SLOT_INFO_T slot_info = *SLOT_INFO_FROM_INDEX(state, i);
++ if (slot_info.use_count != slot_info.release_count) {
++ len = snprintf(buf, sizeof(buf),
++ " %d: %d/%d", i, slot_info.use_count,
++ slot_info.release_count);
++ vchiq_dump(dump_context, buf, len + 1);
++ }
++ }
++
++ for (i = 1; i < shared->debug[DEBUG_ENTRIES]; i++) {
++ len = snprintf(buf, sizeof(buf), " DEBUG: %s = %d(%x)",
++ debug_names[i], shared->debug[i], shared->debug[i]);
++ vchiq_dump(dump_context, buf, len + 1);
++ }
++}
++
++void
++vchiq_dump_state(void *dump_context, VCHIQ_STATE_T *state)
++{
++ char buf[80];
++ int len;
++ int i;
++
++ len = snprintf(buf, sizeof(buf), "State %d: %s", state->id,
++ conn_state_names[state->conn_state]);
++ vchiq_dump(dump_context, buf, len + 1);
++
++ len = snprintf(buf, sizeof(buf),
++ " tx_pos=%x(@%x), rx_pos=%x(@%x)",
++ state->local->tx_pos,
++ (uint32_t)state->tx_data +
++ (state->local_tx_pos & VCHIQ_SLOT_MASK),
++ state->rx_pos,
++ (uint32_t)state->rx_data +
++ (state->rx_pos & VCHIQ_SLOT_MASK));
++ vchiq_dump(dump_context, buf, len + 1);
++
++ len = snprintf(buf, sizeof(buf),
++ " Version: %d (min %d)",
++ VCHIQ_VERSION, VCHIQ_VERSION_MIN);
++ vchiq_dump(dump_context, buf, len + 1);
++
++ if (VCHIQ_ENABLE_STATS) {
++ len = snprintf(buf, sizeof(buf),
++ " Stats: ctrl_tx_count=%d, ctrl_rx_count=%d, "
++ "error_count=%d",
++ state->stats.ctrl_tx_count, state->stats.ctrl_rx_count,
++ state->stats.error_count);
++ vchiq_dump(dump_context, buf, len + 1);
++ }
++
++ len = snprintf(buf, sizeof(buf),
++ " Slots: %d available (%d data), %d recyclable, %d stalls "
++ "(%d data)",
++ ((state->slot_queue_available * VCHIQ_SLOT_SIZE) -
++ state->local_tx_pos) / VCHIQ_SLOT_SIZE,
++ state->data_quota - state->data_use_count,
++ state->local->slot_queue_recycle - state->slot_queue_available,
++ state->stats.slot_stalls, state->stats.data_stalls);
++ vchiq_dump(dump_context, buf, len + 1);
++
++ vchiq_dump_platform_state(dump_context);
++
++ vchiq_dump_shared_state(dump_context, state, state->local, "Local");
++ vchiq_dump_shared_state(dump_context, state, state->remote, "Remote");
++
++ vchiq_dump_platform_instances(dump_context);
++
++ for (i = 0; i < state->unused_service; i++) {
++ VCHIQ_SERVICE_T *service = find_service_by_port(state, i);
++
++ if (service) {
++ vchiq_dump_service_state(dump_context, service);
++ unlock_service(service);
++ }
++ }
++}
++
++void
++vchiq_dump_service_state(void *dump_context, VCHIQ_SERVICE_T *service)
++{
++ char buf[80];
++ int len;
++
++ len = snprintf(buf, sizeof(buf), "Service %d: %s (ref %u)",
++ service->localport, srvstate_names[service->srvstate],
++ service->ref_count - 1); /*Don't include the lock just taken*/
++
++ if (service->srvstate != VCHIQ_SRVSTATE_FREE) {
++ char remoteport[30];
++ VCHIQ_SERVICE_QUOTA_T *service_quota =
++ &service->state->service_quotas[service->localport];
++ int fourcc = service->base.fourcc;
++ int tx_pending, rx_pending;
++ if (service->remoteport != VCHIQ_PORT_FREE) {
++ int len2 = snprintf(remoteport, sizeof(remoteport),
++ "%d", service->remoteport);
++ if (service->public_fourcc != VCHIQ_FOURCC_INVALID)
++ snprintf(remoteport + len2,
++ sizeof(remoteport) - len2,
++ " (client %x)", service->client_id);
++ } else
++ strcpy(remoteport, "n/a");
++
++ len += snprintf(buf + len, sizeof(buf) - len,
++ " '%c%c%c%c' remote %s (msg use %d/%d, slot use %d/%d)",
++ VCHIQ_FOURCC_AS_4CHARS(fourcc),
++ remoteport,
++ service_quota->message_use_count,
++ service_quota->message_quota,
++ service_quota->slot_use_count,
++ service_quota->slot_quota);
++
++ vchiq_dump(dump_context, buf, len + 1);
++
++ tx_pending = service->bulk_tx.local_insert -
++ service->bulk_tx.remote_insert;
++
++ rx_pending = service->bulk_rx.local_insert -
++ service->bulk_rx.remote_insert;
++
++ len = snprintf(buf, sizeof(buf),
++ " Bulk: tx_pending=%d (size %d),"
++ " rx_pending=%d (size %d)",
++ tx_pending,
++ tx_pending ? service->bulk_tx.bulks[
++ BULK_INDEX(service->bulk_tx.remove)].size : 0,
++ rx_pending,
++ rx_pending ? service->bulk_rx.bulks[
++ BULK_INDEX(service->bulk_rx.remove)].size : 0);
++
++ if (VCHIQ_ENABLE_STATS) {
++ vchiq_dump(dump_context, buf, len + 1);
++
++ len = snprintf(buf, sizeof(buf),
++ " Ctrl: tx_count=%d, tx_bytes=%llu, "
++ "rx_count=%d, rx_bytes=%llu",
++ service->stats.ctrl_tx_count,
++ service->stats.ctrl_tx_bytes,
++ service->stats.ctrl_rx_count,
++ service->stats.ctrl_rx_bytes);
++ vchiq_dump(dump_context, buf, len + 1);
++
++ len = snprintf(buf, sizeof(buf),
++ " Bulk: tx_count=%d, tx_bytes=%llu, "
++ "rx_count=%d, rx_bytes=%llu",
++ service->stats.bulk_tx_count,
++ service->stats.bulk_tx_bytes,
++ service->stats.bulk_rx_count,
++ service->stats.bulk_rx_bytes);
++ vchiq_dump(dump_context, buf, len + 1);
++
++ len = snprintf(buf, sizeof(buf),
++ " %d quota stalls, %d slot stalls, "
++ "%d bulk stalls, %d aborted, %d errors",
++ service->stats.quota_stalls,
++ service->stats.slot_stalls,
++ service->stats.bulk_stalls,
++ service->stats.bulk_aborted_count,
++ service->stats.error_count);
++ }
++ }
++
++ vchiq_dump(dump_context, buf, len + 1);
++
++ if (service->srvstate != VCHIQ_SRVSTATE_FREE)
++ vchiq_dump_platform_service_state(dump_context, service);
++}
++
++
++void
++vchiq_loud_error_header(void)
++{
++ vchiq_log_error(vchiq_core_log_level,
++ "============================================================"
++ "================");
++ vchiq_log_error(vchiq_core_log_level,
++ "============================================================"
++ "================");
++ vchiq_log_error(vchiq_core_log_level, "=====");
++}
++
++void
++vchiq_loud_error_footer(void)
++{
++ vchiq_log_error(vchiq_core_log_level, "=====");
++ vchiq_log_error(vchiq_core_log_level,
++ "============================================================"
++ "================");
++ vchiq_log_error(vchiq_core_log_level,
++ "============================================================"
++ "================");
++}
++
++
++VCHIQ_STATUS_T vchiq_send_remote_use(VCHIQ_STATE_T *state)
++{
++ VCHIQ_STATUS_T status = VCHIQ_RETRY;
++ if (state->conn_state != VCHIQ_CONNSTATE_DISCONNECTED)
++ status = queue_message(state, NULL,
++ VCHIQ_MAKE_MSG(VCHIQ_MSG_REMOTE_USE, 0, 0),
++ NULL, 0, 0, 0);
++ return status;
++}
++
++VCHIQ_STATUS_T vchiq_send_remote_release(VCHIQ_STATE_T *state)
++{
++ VCHIQ_STATUS_T status = VCHIQ_RETRY;
++ if (state->conn_state != VCHIQ_CONNSTATE_DISCONNECTED)
++ status = queue_message(state, NULL,
++ VCHIQ_MAKE_MSG(VCHIQ_MSG_REMOTE_RELEASE, 0, 0),
++ NULL, 0, 0, 0);
++ return status;
++}
++
++VCHIQ_STATUS_T vchiq_send_remote_use_active(VCHIQ_STATE_T *state)
++{
++ VCHIQ_STATUS_T status = VCHIQ_RETRY;
++ if (state->conn_state != VCHIQ_CONNSTATE_DISCONNECTED)
++ status = queue_message(state, NULL,
++ VCHIQ_MAKE_MSG(VCHIQ_MSG_REMOTE_USE_ACTIVE, 0, 0),
++ NULL, 0, 0, 0);
++ return status;
++}
++
++void vchiq_log_dump_mem(const char *label, uint32_t addr, const void *voidMem,
++ size_t numBytes)
++{
++ const uint8_t *mem = (const uint8_t *)voidMem;
++ size_t offset;
++ char lineBuf[100];
++ char *s;
++
++ while (numBytes > 0) {
++ s = lineBuf;
++
++ for (offset = 0; offset < 16; offset++) {
++ if (offset < numBytes)
++ s += snprintf(s, 4, "%02x ", mem[offset]);
++ else
++ s += snprintf(s, 4, " ");
++ }
++
++ for (offset = 0; offset < 16; offset++) {
++ if (offset < numBytes) {
++ uint8_t ch = mem[offset];
++
++ if ((ch < ' ') || (ch > '~'))
++ ch = '.';
++ *s++ = (char)ch;
++ }
++ }
++ *s++ = '\0';
++
++ if ((label != NULL) && (*label != '\0'))
++ vchiq_log_trace(VCHIQ_LOG_TRACE,
++ "%s: %08x: %s", label, addr, lineBuf);
++ else
++ vchiq_log_trace(VCHIQ_LOG_TRACE,
++ "%08x: %s", addr, lineBuf);
++
++ addr += 16;
++ mem += 16;
++ if (numBytes > 16)
++ numBytes -= 16;
++ else
++ numBytes = 0;
++ }
++}
+diff -Nur linux-4.1.3/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.h linux-xbian-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.h
+--- linux-4.1.3/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.h 2015-07-28 01:20:58.285725306 +0200
+@@ -0,0 +1,712 @@
++/**
++ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ * 1. Redistributions of source code must retain the above copyright
++ * notice, this list of conditions, and the following disclaimer,
++ * without modification.
++ * 2. Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * 3. The names of the above-listed copyright holders may not be used
++ * to endorse or promote products derived from this software without
++ * specific prior written permission.
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") version 2, as published by the Free
++ * Software Foundation.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#ifndef VCHIQ_CORE_H
++#define VCHIQ_CORE_H
++
++#include <linux/mutex.h>
++#include <linux/semaphore.h>
++#include <linux/kthread.h>
++
++#include "vchiq_cfg.h"
++
++#include "vchiq.h"
++
++/* Run time control of log level, based on KERN_XXX level. */
++#define VCHIQ_LOG_DEFAULT 4
++#define VCHIQ_LOG_ERROR 3
++#define VCHIQ_LOG_WARNING 4
++#define VCHIQ_LOG_INFO 6
++#define VCHIQ_LOG_TRACE 7
++
++#define VCHIQ_LOG_PREFIX KERN_INFO "vchiq: "
++
++#ifndef vchiq_log_error
++#define vchiq_log_error(cat, fmt, ...) \
++ do { if (cat >= VCHIQ_LOG_ERROR) \
++ printk(VCHIQ_LOG_PREFIX fmt "\n", ##__VA_ARGS__); } while (0)
++#endif
++#ifndef vchiq_log_warning
++#define vchiq_log_warning(cat, fmt, ...) \
++ do { if (cat >= VCHIQ_LOG_WARNING) \
++ printk(VCHIQ_LOG_PREFIX fmt "\n", ##__VA_ARGS__); } while (0)
++#endif
++#ifndef vchiq_log_info
++#define vchiq_log_info(cat, fmt, ...) \
++ do { if (cat >= VCHIQ_LOG_INFO) \
++ printk(VCHIQ_LOG_PREFIX fmt "\n", ##__VA_ARGS__); } while (0)
++#endif
++#ifndef vchiq_log_trace
++#define vchiq_log_trace(cat, fmt, ...) \
++ do { if (cat >= VCHIQ_LOG_TRACE) \
++ printk(VCHIQ_LOG_PREFIX fmt "\n", ##__VA_ARGS__); } while (0)
++#endif
++
++#define vchiq_loud_error(...) \
++ vchiq_log_error(vchiq_core_log_level, "===== " __VA_ARGS__)
++
++#ifndef vchiq_static_assert
++#define vchiq_static_assert(cond) __attribute__((unused)) \
++ extern int vchiq_static_assert[(cond) ? 1 : -1]
++#endif
++
++#define IS_POW2(x) (x && ((x & (x - 1)) == 0))
++
++/* Ensure that the slot size and maximum number of slots are powers of 2 */
++vchiq_static_assert(IS_POW2(VCHIQ_SLOT_SIZE));
++vchiq_static_assert(IS_POW2(VCHIQ_MAX_SLOTS));
++vchiq_static_assert(IS_POW2(VCHIQ_MAX_SLOTS_PER_SIDE));
++
++#define VCHIQ_SLOT_MASK (VCHIQ_SLOT_SIZE - 1)
++#define VCHIQ_SLOT_QUEUE_MASK (VCHIQ_MAX_SLOTS_PER_SIDE - 1)
++#define VCHIQ_SLOT_ZERO_SLOTS ((sizeof(VCHIQ_SLOT_ZERO_T) + \
++ VCHIQ_SLOT_SIZE - 1) / VCHIQ_SLOT_SIZE)
++
++#define VCHIQ_MSG_PADDING 0 /* - */
++#define VCHIQ_MSG_CONNECT 1 /* - */
++#define VCHIQ_MSG_OPEN 2 /* + (srcport, -), fourcc, client_id */
++#define VCHIQ_MSG_OPENACK 3 /* + (srcport, dstport) */
++#define VCHIQ_MSG_CLOSE 4 /* + (srcport, dstport) */
++#define VCHIQ_MSG_DATA 5 /* + (srcport, dstport) */
++#define VCHIQ_MSG_BULK_RX 6 /* + (srcport, dstport), data, size */
++#define VCHIQ_MSG_BULK_TX 7 /* + (srcport, dstport), data, size */
++#define VCHIQ_MSG_BULK_RX_DONE 8 /* + (srcport, dstport), actual */
++#define VCHIQ_MSG_BULK_TX_DONE 9 /* + (srcport, dstport), actual */
++#define VCHIQ_MSG_PAUSE 10 /* - */
++#define VCHIQ_MSG_RESUME 11 /* - */
++#define VCHIQ_MSG_REMOTE_USE 12 /* - */
++#define VCHIQ_MSG_REMOTE_RELEASE 13 /* - */
++#define VCHIQ_MSG_REMOTE_USE_ACTIVE 14 /* - */
++
++#define VCHIQ_PORT_MAX (VCHIQ_MAX_SERVICES - 1)
++#define VCHIQ_PORT_FREE 0x1000
++#define VCHIQ_PORT_IS_VALID(port) (port < VCHIQ_PORT_FREE)
++#define VCHIQ_MAKE_MSG(type, srcport, dstport) \
++ ((type<<24) | (srcport<<12) | (dstport<<0))
++#define VCHIQ_MSG_TYPE(msgid) ((unsigned int)msgid >> 24)
++#define VCHIQ_MSG_SRCPORT(msgid) \
++ (unsigned short)(((unsigned int)msgid >> 12) & 0xfff)
++#define VCHIQ_MSG_DSTPORT(msgid) \
++ ((unsigned short)msgid & 0xfff)
++
++#define VCHIQ_FOURCC_AS_4CHARS(fourcc) \
++ ((fourcc) >> 24) & 0xff, \
++ ((fourcc) >> 16) & 0xff, \
++ ((fourcc) >> 8) & 0xff, \
++ (fourcc) & 0xff
++
++/* Ensure the fields are wide enough */
++vchiq_static_assert(VCHIQ_MSG_SRCPORT(VCHIQ_MAKE_MSG(0, 0, VCHIQ_PORT_MAX))
++ == 0);
++vchiq_static_assert(VCHIQ_MSG_TYPE(VCHIQ_MAKE_MSG(0, VCHIQ_PORT_MAX, 0)) == 0);
++vchiq_static_assert((unsigned int)VCHIQ_PORT_MAX <
++ (unsigned int)VCHIQ_PORT_FREE);
++
++#define VCHIQ_MSGID_PADDING VCHIQ_MAKE_MSG(VCHIQ_MSG_PADDING, 0, 0)
++#define VCHIQ_MSGID_CLAIMED 0x40000000
++
++#define VCHIQ_FOURCC_INVALID 0x00000000
++#define VCHIQ_FOURCC_IS_LEGAL(fourcc) (fourcc != VCHIQ_FOURCC_INVALID)
++
++#define VCHIQ_BULK_ACTUAL_ABORTED -1
++
++typedef uint32_t BITSET_T;
++
++vchiq_static_assert((sizeof(BITSET_T) * 8) == 32);
++
++#define BITSET_SIZE(b) ((b + 31) >> 5)
++#define BITSET_WORD(b) (b >> 5)
++#define BITSET_BIT(b) (1 << (b & 31))
++#define BITSET_ZERO(bs) memset(bs, 0, sizeof(bs))
++#define BITSET_IS_SET(bs, b) (bs[BITSET_WORD(b)] & BITSET_BIT(b))
++#define BITSET_SET(bs, b) (bs[BITSET_WORD(b)] |= BITSET_BIT(b))
++#define BITSET_CLR(bs, b) (bs[BITSET_WORD(b)] &= ~BITSET_BIT(b))
++
++#if VCHIQ_ENABLE_STATS
++#define VCHIQ_STATS_INC(state, stat) (state->stats. stat++)
++#define VCHIQ_SERVICE_STATS_INC(service, stat) (service->stats. stat++)
++#define VCHIQ_SERVICE_STATS_ADD(service, stat, addend) \
++ (service->stats. stat += addend)
++#else
++#define VCHIQ_STATS_INC(state, stat) ((void)0)
++#define VCHIQ_SERVICE_STATS_INC(service, stat) ((void)0)
++#define VCHIQ_SERVICE_STATS_ADD(service, stat, addend) ((void)0)
++#endif
++
++enum {
++ DEBUG_ENTRIES,
++#if VCHIQ_ENABLE_DEBUG
++ DEBUG_SLOT_HANDLER_COUNT,
++ DEBUG_SLOT_HANDLER_LINE,
++ DEBUG_PARSE_LINE,
++ DEBUG_PARSE_HEADER,
++ DEBUG_PARSE_MSGID,
++ DEBUG_AWAIT_COMPLETION_LINE,
++ DEBUG_DEQUEUE_MESSAGE_LINE,
++ DEBUG_SERVICE_CALLBACK_LINE,
++ DEBUG_MSG_QUEUE_FULL_COUNT,
++ DEBUG_COMPLETION_QUEUE_FULL_COUNT,
++#endif
++ DEBUG_MAX
++};
++
++#if VCHIQ_ENABLE_DEBUG
++
++#define DEBUG_INITIALISE(local) int *debug_ptr = (local)->debug;
++#define DEBUG_TRACE(d) \
++ do { debug_ptr[DEBUG_ ## d] = __LINE__; dsb(); } while (0)
++#define DEBUG_VALUE(d, v) \
++ do { debug_ptr[DEBUG_ ## d] = (v); dsb(); } while (0)
++#define DEBUG_COUNT(d) \
++ do { debug_ptr[DEBUG_ ## d]++; dsb(); } while (0)
++
++#else /* VCHIQ_ENABLE_DEBUG */
++
++#define DEBUG_INITIALISE(local)
++#define DEBUG_TRACE(d)
++#define DEBUG_VALUE(d, v)
++#define DEBUG_COUNT(d)
++
++#endif /* VCHIQ_ENABLE_DEBUG */
++
++typedef enum {
++ VCHIQ_CONNSTATE_DISCONNECTED,
++ VCHIQ_CONNSTATE_CONNECTING,
++ VCHIQ_CONNSTATE_CONNECTED,
++ VCHIQ_CONNSTATE_PAUSING,
++ VCHIQ_CONNSTATE_PAUSE_SENT,
++ VCHIQ_CONNSTATE_PAUSED,
++ VCHIQ_CONNSTATE_RESUMING,
++ VCHIQ_CONNSTATE_PAUSE_TIMEOUT,
++ VCHIQ_CONNSTATE_RESUME_TIMEOUT
++} VCHIQ_CONNSTATE_T;
++
++enum {
++ VCHIQ_SRVSTATE_FREE,
++ VCHIQ_SRVSTATE_HIDDEN,
++ VCHIQ_SRVSTATE_LISTENING,
++ VCHIQ_SRVSTATE_OPENING,
++ VCHIQ_SRVSTATE_OPEN,
++ VCHIQ_SRVSTATE_OPENSYNC,
++ VCHIQ_SRVSTATE_CLOSESENT,
++ VCHIQ_SRVSTATE_CLOSERECVD,
++ VCHIQ_SRVSTATE_CLOSEWAIT,
++ VCHIQ_SRVSTATE_CLOSED
++};
++
++enum {
++ VCHIQ_POLL_TERMINATE,
++ VCHIQ_POLL_REMOVE,
++ VCHIQ_POLL_TXNOTIFY,
++ VCHIQ_POLL_RXNOTIFY,
++ VCHIQ_POLL_COUNT
++};
++
++typedef enum {
++ VCHIQ_BULK_TRANSMIT,
++ VCHIQ_BULK_RECEIVE
++} VCHIQ_BULK_DIR_T;
++
++typedef void (*VCHIQ_USERDATA_TERM_T)(void *userdata);
++
++typedef struct vchiq_bulk_struct {
++ short mode;
++ short dir;
++ void *userdata;
++ VCHI_MEM_HANDLE_T handle;
++ void *data;
++ int size;
++ void *remote_data;
++ int remote_size;
++ int actual;
++} VCHIQ_BULK_T;
++
++typedef struct vchiq_bulk_queue_struct {
++ int local_insert; /* Where to insert the next local bulk */
++ int remote_insert; /* Where to insert the next remote bulk (master) */
++ int process; /* Bulk to transfer next */
++ int remote_notify; /* Bulk to notify the remote client of next (mstr) */
++ int remove; /* Bulk to notify the local client of, and remove,
++ ** next */
++ VCHIQ_BULK_T bulks[VCHIQ_NUM_SERVICE_BULKS];
++} VCHIQ_BULK_QUEUE_T;
++
++typedef struct remote_event_struct {
++ int armed;
++ int fired;
++ struct semaphore *event;
++} REMOTE_EVENT_T;
++
++typedef struct opaque_platform_state_t *VCHIQ_PLATFORM_STATE_T;
++
++typedef struct vchiq_state_struct VCHIQ_STATE_T;
++
++typedef struct vchiq_slot_struct {
++ char data[VCHIQ_SLOT_SIZE];
++} VCHIQ_SLOT_T;
++
++typedef struct vchiq_slot_info_struct {
++ /* Use two counters rather than one to avoid the need for a mutex. */
++ short use_count;
++ short release_count;
++} VCHIQ_SLOT_INFO_T;
++
++typedef struct vchiq_service_struct {
++ VCHIQ_SERVICE_BASE_T base;
++ VCHIQ_SERVICE_HANDLE_T handle;
++ unsigned int ref_count;
++ int srvstate;
++ VCHIQ_USERDATA_TERM_T userdata_term;
++ unsigned int localport;
++ unsigned int remoteport;
++ int public_fourcc;
++ int client_id;
++ char auto_close;
++ char sync;
++ char closing;
++ char trace;
++ atomic_t poll_flags;
++ short version;
++ short version_min;
++ short peer_version;
++
++ VCHIQ_STATE_T *state;
++ VCHIQ_INSTANCE_T instance;
++
++ int service_use_count;
++
++ VCHIQ_BULK_QUEUE_T bulk_tx;
++ VCHIQ_BULK_QUEUE_T bulk_rx;
++
++ struct semaphore remove_event;
++ struct semaphore bulk_remove_event;
++ struct mutex bulk_mutex;
++
++ struct service_stats_struct {
++ int quota_stalls;
++ int slot_stalls;
++ int bulk_stalls;
++ int error_count;
++ int ctrl_tx_count;
++ int ctrl_rx_count;
++ int bulk_tx_count;
++ int bulk_rx_count;
++ int bulk_aborted_count;
++ uint64_t ctrl_tx_bytes;
++ uint64_t ctrl_rx_bytes;
++ uint64_t bulk_tx_bytes;
++ uint64_t bulk_rx_bytes;
++ } stats;
++} VCHIQ_SERVICE_T;
++
++/* The quota information is outside VCHIQ_SERVICE_T so that it can be
++ statically allocated, since for accounting reasons a service's slot
++ usage is carried over between users of the same port number.
++ */
++typedef struct vchiq_service_quota_struct {
++ unsigned short slot_quota;
++ unsigned short slot_use_count;
++ unsigned short message_quota;
++ unsigned short message_use_count;
++ struct semaphore quota_event;
++ int previous_tx_index;
++} VCHIQ_SERVICE_QUOTA_T;
++
++typedef struct vchiq_shared_state_struct {
++
++ /* A non-zero value here indicates that the content is valid. */
++ int initialised;
++
++ /* The first and last (inclusive) slots allocated to the owner. */
++ int slot_first;
++ int slot_last;
++
++ /* The slot allocated to synchronous messages from the owner. */
++ int slot_sync;
++
++ /* Signalling this event indicates that owner's slot handler thread
++ ** should run. */
++ REMOTE_EVENT_T trigger;
++
++ /* Indicates the byte position within the stream where the next message
++ ** will be written. The least significant bits are an index into the
++ ** slot. The next bits are the index of the slot in slot_queue. */
++ int tx_pos;
++
++ /* This event should be signalled when a slot is recycled. */
++ REMOTE_EVENT_T recycle;
++
++ /* The slot_queue index where the next recycled slot will be written. */
++ int slot_queue_recycle;
++
++ /* This event should be signalled when a synchronous message is sent. */
++ REMOTE_EVENT_T sync_trigger;
++
++ /* This event should be signalled when a synchronous message has been
++ ** released. */
++ REMOTE_EVENT_T sync_release;
++
++ /* A circular buffer of slot indexes. */
++ int slot_queue[VCHIQ_MAX_SLOTS_PER_SIDE];
++
++ /* Debugging state */
++ int debug[DEBUG_MAX];
++} VCHIQ_SHARED_STATE_T;
++
++typedef struct vchiq_slot_zero_struct {
++ int magic;
++ short version;
++ short version_min;
++ int slot_zero_size;
++ int slot_size;
++ int max_slots;
++ int max_slots_per_side;
++ int platform_data[2];
++ VCHIQ_SHARED_STATE_T master;
++ VCHIQ_SHARED_STATE_T slave;
++ VCHIQ_SLOT_INFO_T slots[VCHIQ_MAX_SLOTS];
++} VCHIQ_SLOT_ZERO_T;
++
++struct vchiq_state_struct {
++ int id;
++ int initialised;
++ VCHIQ_CONNSTATE_T conn_state;
++ int is_master;
++ short version_common;
++
++ VCHIQ_SHARED_STATE_T *local;
++ VCHIQ_SHARED_STATE_T *remote;
++ VCHIQ_SLOT_T *slot_data;
++
++ unsigned short default_slot_quota;
++ unsigned short default_message_quota;
++
++ /* Event indicating connect message received */
++ struct semaphore connect;
++
++ /* Mutex protecting services */
++ struct mutex mutex;
++ VCHIQ_INSTANCE_T *instance;
++
++ /* Processes incoming messages */
++ struct task_struct *slot_handler_thread;
++
++ /* Processes recycled slots */
++ struct task_struct *recycle_thread;
++
++ /* Processes synchronous messages */
++ struct task_struct *sync_thread;
++
++ /* Local implementation of the trigger remote event */
++ struct semaphore trigger_event;
++
++ /* Local implementation of the recycle remote event */
++ struct semaphore recycle_event;
++
++ /* Local implementation of the sync trigger remote event */
++ struct semaphore sync_trigger_event;
++
++ /* Local implementation of the sync release remote event */
++ struct semaphore sync_release_event;
++
++ char *tx_data;
++ char *rx_data;
++ VCHIQ_SLOT_INFO_T *rx_info;
++
++ struct mutex slot_mutex;
++
++ struct mutex recycle_mutex;
++
++ struct mutex sync_mutex;
++
++ struct mutex bulk_transfer_mutex;
++
++ /* Indicates the byte position within the stream from where the next
++ ** message will be read. The least significant bits are an index into
++ ** the slot.The next bits are the index of the slot in
++ ** remote->slot_queue. */
++ int rx_pos;
++
++ /* A cached copy of local->tx_pos. Only write to local->tx_pos, and read
++ from remote->tx_pos. */
++ int local_tx_pos;
++
++ /* The slot_queue index of the slot to become available next. */
++ int slot_queue_available;
++
++ /* A flag to indicate if any poll has been requested */
++ int poll_needed;
++
++ /* Ths index of the previous slot used for data messages. */
++ int previous_data_index;
++
++ /* The number of slots occupied by data messages. */
++ unsigned short data_use_count;
++
++ /* The maximum number of slots to be occupied by data messages. */
++ unsigned short data_quota;
++
++ /* An array of bit sets indicating which services must be polled. */
++ atomic_t poll_services[BITSET_SIZE(VCHIQ_MAX_SERVICES)];
++
++ /* The number of the first unused service */
++ int unused_service;
++
++ /* Signalled when a free slot becomes available. */
++ struct semaphore slot_available_event;
++
++ struct semaphore slot_remove_event;
++
++ /* Signalled when a free data slot becomes available. */
++ struct semaphore data_quota_event;
++
++ /* Incremented when there are bulk transfers which cannot be processed
++ * whilst paused and must be processed on resume */
++ int deferred_bulks;
++
++ struct state_stats_struct {
++ int slot_stalls;
++ int data_stalls;
++ int ctrl_tx_count;
++ int ctrl_rx_count;
++ int error_count;
++ } stats;
++
++ VCHIQ_SERVICE_T * services[VCHIQ_MAX_SERVICES];
++ VCHIQ_SERVICE_QUOTA_T service_quotas[VCHIQ_MAX_SERVICES];
++ VCHIQ_SLOT_INFO_T slot_info[VCHIQ_MAX_SLOTS];
++
++ VCHIQ_PLATFORM_STATE_T platform_state;
++};
++
++struct bulk_waiter {
++ VCHIQ_BULK_T *bulk;
++ struct semaphore event;
++ int actual;
++};
++
++extern spinlock_t bulk_waiter_spinlock;
++
++extern int vchiq_core_log_level;
++extern int vchiq_core_msg_log_level;
++extern int vchiq_sync_log_level;
++
++extern VCHIQ_STATE_T *vchiq_states[VCHIQ_MAX_STATES];
++
++extern const char *
++get_conn_state_name(VCHIQ_CONNSTATE_T conn_state);
++
++extern VCHIQ_SLOT_ZERO_T *
++vchiq_init_slots(void *mem_base, int mem_size);
++
++extern VCHIQ_STATUS_T
++vchiq_init_state(VCHIQ_STATE_T *state, VCHIQ_SLOT_ZERO_T *slot_zero,
++ int is_master);
++
++extern VCHIQ_STATUS_T
++vchiq_connect_internal(VCHIQ_STATE_T *state, VCHIQ_INSTANCE_T instance);
++
++extern VCHIQ_SERVICE_T *
++vchiq_add_service_internal(VCHIQ_STATE_T *state,
++ const VCHIQ_SERVICE_PARAMS_T *params, int srvstate,
++ VCHIQ_INSTANCE_T instance, VCHIQ_USERDATA_TERM_T userdata_term);
++
++extern VCHIQ_STATUS_T
++vchiq_open_service_internal(VCHIQ_SERVICE_T *service, int client_id);
++
++extern VCHIQ_STATUS_T
++vchiq_close_service_internal(VCHIQ_SERVICE_T *service, int close_recvd);
++
++extern void
++vchiq_terminate_service_internal(VCHIQ_SERVICE_T *service);
++
++extern void
++vchiq_free_service_internal(VCHIQ_SERVICE_T *service);
++
++extern VCHIQ_STATUS_T
++vchiq_shutdown_internal(VCHIQ_STATE_T *state, VCHIQ_INSTANCE_T instance);
++
++extern VCHIQ_STATUS_T
++vchiq_pause_internal(VCHIQ_STATE_T *state);
++
++extern VCHIQ_STATUS_T
++vchiq_resume_internal(VCHIQ_STATE_T *state);
++
++extern void
++remote_event_pollall(VCHIQ_STATE_T *state);
++
++extern VCHIQ_STATUS_T
++vchiq_bulk_transfer(VCHIQ_SERVICE_HANDLE_T handle,
++ VCHI_MEM_HANDLE_T memhandle, void *offset, int size, void *userdata,
++ VCHIQ_BULK_MODE_T mode, VCHIQ_BULK_DIR_T dir);
++
++extern void
++vchiq_dump_state(void *dump_context, VCHIQ_STATE_T *state);
++
++extern void
++vchiq_dump_service_state(void *dump_context, VCHIQ_SERVICE_T *service);
++
++extern void
++vchiq_loud_error_header(void);
++
++extern void
++vchiq_loud_error_footer(void);
++
++extern void
++request_poll(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service, int poll_type);
++
++static inline VCHIQ_SERVICE_T *
++handle_to_service(VCHIQ_SERVICE_HANDLE_T handle)
++{
++ VCHIQ_STATE_T *state = vchiq_states[(handle / VCHIQ_MAX_SERVICES) &
++ (VCHIQ_MAX_STATES - 1)];
++ if (!state)
++ return NULL;
++
++ return state->services[handle & (VCHIQ_MAX_SERVICES - 1)];
++}
++
++extern VCHIQ_SERVICE_T *
++find_service_by_handle(VCHIQ_SERVICE_HANDLE_T handle);
++
++extern VCHIQ_SERVICE_T *
++find_service_by_port(VCHIQ_STATE_T *state, int localport);
++
++extern VCHIQ_SERVICE_T *
++find_service_for_instance(VCHIQ_INSTANCE_T instance,
++ VCHIQ_SERVICE_HANDLE_T handle);
++
++extern VCHIQ_SERVICE_T *
++find_closed_service_for_instance(VCHIQ_INSTANCE_T instance,
++ VCHIQ_SERVICE_HANDLE_T handle);
++
++extern VCHIQ_SERVICE_T *
++next_service_by_instance(VCHIQ_STATE_T *state, VCHIQ_INSTANCE_T instance,
++ int *pidx);
++
++extern void
++lock_service(VCHIQ_SERVICE_T *service);
++
++extern void
++unlock_service(VCHIQ_SERVICE_T *service);
++
++/* The following functions are called from vchiq_core, and external
++** implementations must be provided. */
++
++extern VCHIQ_STATUS_T
++vchiq_prepare_bulk_data(VCHIQ_BULK_T *bulk,
++ VCHI_MEM_HANDLE_T memhandle, void *offset, int size, int dir);
++
++extern void
++vchiq_transfer_bulk(VCHIQ_BULK_T *bulk);
++
++extern void
++vchiq_complete_bulk(VCHIQ_BULK_T *bulk);
++
++extern VCHIQ_STATUS_T
++vchiq_copy_from_user(void *dst, const void *src, int size);
++
++extern void
++remote_event_signal(REMOTE_EVENT_T *event);
++
++void
++vchiq_platform_check_suspend(VCHIQ_STATE_T *state);
++
++extern void
++vchiq_platform_paused(VCHIQ_STATE_T *state);
++
++extern VCHIQ_STATUS_T
++vchiq_platform_resume(VCHIQ_STATE_T *state);
++
++extern void
++vchiq_platform_resumed(VCHIQ_STATE_T *state);
++
++extern void
++vchiq_dump(void *dump_context, const char *str, int len);
++
++extern void
++vchiq_dump_platform_state(void *dump_context);
++
++extern void
++vchiq_dump_platform_instances(void *dump_context);
++
++extern void
++vchiq_dump_platform_service_state(void *dump_context,
++ VCHIQ_SERVICE_T *service);
++
++extern VCHIQ_STATUS_T
++vchiq_use_service_internal(VCHIQ_SERVICE_T *service);
++
++extern VCHIQ_STATUS_T
++vchiq_release_service_internal(VCHIQ_SERVICE_T *service);
++
++extern void
++vchiq_on_remote_use(VCHIQ_STATE_T *state);
++
++extern void
++vchiq_on_remote_release(VCHIQ_STATE_T *state);
++
++extern VCHIQ_STATUS_T
++vchiq_platform_init_state(VCHIQ_STATE_T *state);
++
++extern VCHIQ_STATUS_T
++vchiq_check_service(VCHIQ_SERVICE_T *service);
++
++extern void
++vchiq_on_remote_use_active(VCHIQ_STATE_T *state);
++
++extern VCHIQ_STATUS_T
++vchiq_send_remote_use(VCHIQ_STATE_T *state);
++
++extern VCHIQ_STATUS_T
++vchiq_send_remote_release(VCHIQ_STATE_T *state);
++
++extern VCHIQ_STATUS_T
++vchiq_send_remote_use_active(VCHIQ_STATE_T *state);
++
++extern void
++vchiq_platform_conn_state_changed(VCHIQ_STATE_T *state,
++ VCHIQ_CONNSTATE_T oldstate, VCHIQ_CONNSTATE_T newstate);
++
++extern void
++vchiq_platform_handle_timeout(VCHIQ_STATE_T *state);
++
++extern void
++vchiq_set_conn_state(VCHIQ_STATE_T *state, VCHIQ_CONNSTATE_T newstate);
++
++
++extern void
++vchiq_log_dump_mem(const char *label, uint32_t addr, const void *voidMem,
++ size_t numBytes);
++
++#endif
+diff -Nur linux-4.1.3/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_debugfs.c linux-xbian-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_debugfs.c
+--- linux-4.1.3/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_debugfs.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_debugfs.c 2015-07-28 01:20:58.285725306 +0200
+@@ -0,0 +1,383 @@
++/**
++ * Copyright (c) 2014 Raspberry Pi (Trading) Ltd. All rights reserved.
++ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ * 1. Redistributions of source code must retain the above copyright
++ * notice, this list of conditions, and the following disclaimer,
++ * without modification.
++ * 2. Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * 3. The names of the above-listed copyright holders may not be used
++ * to endorse or promote products derived from this software without
++ * specific prior written permission.
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") version 2, as published by the Free
++ * Software Foundation.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++
++#include <linux/debugfs.h>
++#include "vchiq_core.h"
++#include "vchiq_arm.h"
++#include "vchiq_debugfs.h"
++
++#ifdef CONFIG_DEBUG_FS
++
++/****************************************************************************
++*
++* log category entries
++*
++***************************************************************************/
++#define DEBUGFS_WRITE_BUF_SIZE 256
++
++#define VCHIQ_LOG_ERROR_STR "error"
++#define VCHIQ_LOG_WARNING_STR "warning"
++#define VCHIQ_LOG_INFO_STR "info"
++#define VCHIQ_LOG_TRACE_STR "trace"
++
++
++/* Top-level debug info */
++struct vchiq_debugfs_info {
++ /* Global 'vchiq' debugfs entry used by all instances */
++ struct dentry *vchiq_cfg_dir;
++
++ /* one entry per client process */
++ struct dentry *clients;
++
++ /* log categories */
++ struct dentry *log_categories;
++};
++
++static struct vchiq_debugfs_info debugfs_info;
++
++/* Log category debugfs entries */
++struct vchiq_debugfs_log_entry {
++ const char *name;
++ int *plevel;
++ struct dentry *dir;
++};
++
++static struct vchiq_debugfs_log_entry vchiq_debugfs_log_entries[] = {
++ { "core", &vchiq_core_log_level },
++ { "msg", &vchiq_core_msg_log_level },
++ { "sync", &vchiq_sync_log_level },
++ { "susp", &vchiq_susp_log_level },
++ { "arm", &vchiq_arm_log_level },
++};
++static int n_log_entries =
++ sizeof(vchiq_debugfs_log_entries)/sizeof(vchiq_debugfs_log_entries[0]);
++
++
++static struct dentry *vchiq_clients_top(void);
++static struct dentry *vchiq_debugfs_top(void);
++
++static int debugfs_log_show(struct seq_file *f, void *offset)
++{
++ int *levp = f->private;
++ char *log_value = NULL;
++
++ switch (*levp) {
++ case VCHIQ_LOG_ERROR:
++ log_value = VCHIQ_LOG_ERROR_STR;
++ break;
++ case VCHIQ_LOG_WARNING:
++ log_value = VCHIQ_LOG_WARNING_STR;
++ break;
++ case VCHIQ_LOG_INFO:
++ log_value = VCHIQ_LOG_INFO_STR;
++ break;
++ case VCHIQ_LOG_TRACE:
++ log_value = VCHIQ_LOG_TRACE_STR;
++ break;
++ default:
++ break;
++ }
++
++ seq_printf(f, "%s\n", log_value ? log_value : "(null)");
++
++ return 0;
++}
++
++static int debugfs_log_open(struct inode *inode, struct file *file)
++{
++ return single_open(file, debugfs_log_show, inode->i_private);
++}
++
++static int debugfs_log_write(struct file *file,
++ const char __user *buffer,
++ size_t count, loff_t *ppos)
++{
++ struct seq_file *f = (struct seq_file *)file->private_data;
++ int *levp = f->private;
++ char kbuf[DEBUGFS_WRITE_BUF_SIZE + 1];
++
++ memset(kbuf, 0, DEBUGFS_WRITE_BUF_SIZE + 1);
++ if (count >= DEBUGFS_WRITE_BUF_SIZE)
++ count = DEBUGFS_WRITE_BUF_SIZE;
++
++ if (copy_from_user(kbuf, buffer, count) != 0)
++ return -EFAULT;
++ kbuf[count - 1] = 0;
++
++ if (strncmp("error", kbuf, strlen("error")) == 0)
++ *levp = VCHIQ_LOG_ERROR;
++ else if (strncmp("warning", kbuf, strlen("warning")) == 0)
++ *levp = VCHIQ_LOG_WARNING;
++ else if (strncmp("info", kbuf, strlen("info")) == 0)
++ *levp = VCHIQ_LOG_INFO;
++ else if (strncmp("trace", kbuf, strlen("trace")) == 0)
++ *levp = VCHIQ_LOG_TRACE;
++ else
++ *levp = VCHIQ_LOG_DEFAULT;
++
++ *ppos += count;
++
++ return count;
++}
++
++static const struct file_operations debugfs_log_fops = {
++ .owner = THIS_MODULE,
++ .open = debugfs_log_open,
++ .write = debugfs_log_write,
++ .read = seq_read,
++ .llseek = seq_lseek,
++ .release = single_release,
++};
++
++/* create an entry under <debugfs>/vchiq/log for each log category */
++static int vchiq_debugfs_create_log_entries(struct dentry *top)
++{
++ struct dentry *dir;
++ size_t i;
++ int ret = 0;
++ dir = debugfs_create_dir("log", vchiq_debugfs_top());
++ if (!dir)
++ return -ENOMEM;
++ debugfs_info.log_categories = dir;
++
++ for (i = 0; i < n_log_entries; i++) {
++ void *levp = (void *)vchiq_debugfs_log_entries[i].plevel;
++ dir = debugfs_create_file(vchiq_debugfs_log_entries[i].name,
++ 0644,
++ debugfs_info.log_categories,
++ levp,
++ &debugfs_log_fops);
++ if (!dir) {
++ ret = -ENOMEM;
++ break;
++ }
++
++ vchiq_debugfs_log_entries[i].dir = dir;
++ }
++ return ret;
++}
++
++static int debugfs_usecount_show(struct seq_file *f, void *offset)
++{
++ VCHIQ_INSTANCE_T instance = f->private;
++ int use_count;
++
++ use_count = vchiq_instance_get_use_count(instance);
++ seq_printf(f, "%d\n", use_count);
++
++ return 0;
++}
++
++static int debugfs_usecount_open(struct inode *inode, struct file *file)
++{
++ return single_open(file, debugfs_usecount_show, inode->i_private);
++}
++
++static const struct file_operations debugfs_usecount_fops = {
++ .owner = THIS_MODULE,
++ .open = debugfs_usecount_open,
++ .read = seq_read,
++ .llseek = seq_lseek,
++ .release = single_release,
++};
++
++static int debugfs_trace_show(struct seq_file *f, void *offset)
++{
++ VCHIQ_INSTANCE_T instance = f->private;
++ int trace;
++
++ trace = vchiq_instance_get_trace(instance);
++ seq_printf(f, "%s\n", trace ? "Y" : "N");
++
++ return 0;
++}
++
++static int debugfs_trace_open(struct inode *inode, struct file *file)
++{
++ return single_open(file, debugfs_trace_show, inode->i_private);
++}
++
++static int debugfs_trace_write(struct file *file,
++ const char __user *buffer,
++ size_t count, loff_t *ppos)
++{
++ struct seq_file *f = (struct seq_file *)file->private_data;
++ VCHIQ_INSTANCE_T instance = f->private;
++ char firstchar;
++
++ if (copy_from_user(&firstchar, buffer, 1) != 0)
++ return -EFAULT;
++
++ switch (firstchar) {
++ case 'Y':
++ case 'y':
++ case '1':
++ vchiq_instance_set_trace(instance, 1);
++ break;
++ case 'N':
++ case 'n':
++ case '0':
++ vchiq_instance_set_trace(instance, 0);
++ break;
++ default:
++ break;
++ }
++
++ *ppos += count;
++
++ return count;
++}
++
++static const struct file_operations debugfs_trace_fops = {
++ .owner = THIS_MODULE,
++ .open = debugfs_trace_open,
++ .write = debugfs_trace_write,
++ .read = seq_read,
++ .llseek = seq_lseek,
++ .release = single_release,
++};
++
++/* add an instance (process) to the debugfs entries */
++int vchiq_debugfs_add_instance(VCHIQ_INSTANCE_T instance)
++{
++ char pidstr[16];
++ struct dentry *top, *use_count, *trace;
++ struct dentry *clients = vchiq_clients_top();
++
++ snprintf(pidstr, sizeof(pidstr), "%d",
++ vchiq_instance_get_pid(instance));
++
++ top = debugfs_create_dir(pidstr, clients);
++ if (!top)
++ goto fail_top;
++
++ use_count = debugfs_create_file("use_count",
++ 0444, top,
++ instance,
++ &debugfs_usecount_fops);
++ if (!use_count)
++ goto fail_use_count;
++
++ trace = debugfs_create_file("trace",
++ 0644, top,
++ instance,
++ &debugfs_trace_fops);
++ if (!trace)
++ goto fail_trace;
++
++ vchiq_instance_get_debugfs_node(instance)->dentry = top;
++
++ return 0;
++
++fail_trace:
++ debugfs_remove(use_count);
++fail_use_count:
++ debugfs_remove(top);
++fail_top:
++ return -ENOMEM;
++}
++
++void vchiq_debugfs_remove_instance(VCHIQ_INSTANCE_T instance)
++{
++ VCHIQ_DEBUGFS_NODE_T *node = vchiq_instance_get_debugfs_node(instance);
++ debugfs_remove_recursive(node->dentry);
++}
++
++
++int vchiq_debugfs_init(void)
++{
++ BUG_ON(debugfs_info.vchiq_cfg_dir != NULL);
++
++ debugfs_info.vchiq_cfg_dir = debugfs_create_dir("vchiq", NULL);
++ if (debugfs_info.vchiq_cfg_dir == NULL)
++ goto fail;
++
++ debugfs_info.clients = debugfs_create_dir("clients",
++ vchiq_debugfs_top());
++ if (!debugfs_info.clients)
++ goto fail;
++
++ if (vchiq_debugfs_create_log_entries(vchiq_debugfs_top()) != 0)
++ goto fail;
++
++ return 0;
++
++fail:
++ vchiq_debugfs_deinit();
++ vchiq_log_error(vchiq_arm_log_level,
++ "%s: failed to create debugfs directory",
++ __func__);
++
++ return -ENOMEM;
++}
++
++/* remove all the debugfs entries */
++void vchiq_debugfs_deinit(void)
++{
++ debugfs_remove_recursive(vchiq_debugfs_top());
++}
++
++static struct dentry *vchiq_clients_top(void)
++{
++ return debugfs_info.clients;
++}
++
++static struct dentry *vchiq_debugfs_top(void)
++{
++ BUG_ON(debugfs_info.vchiq_cfg_dir == NULL);
++ return debugfs_info.vchiq_cfg_dir;
++}
++
++#else /* CONFIG_DEBUG_FS */
++
++int vchiq_debugfs_init(void)
++{
++ return 0;
++}
++
++void vchiq_debugfs_deinit(void)
++{
++}
++
++int vchiq_debugfs_add_instance(VCHIQ_INSTANCE_T instance)
++{
++ return 0;
++}
++
++void vchiq_debugfs_remove_instance(VCHIQ_INSTANCE_T instance)
++{
++}
++
++#endif /* CONFIG_DEBUG_FS */
+diff -Nur linux-4.1.3/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_debugfs.h linux-xbian-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_debugfs.h
+--- linux-4.1.3/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_debugfs.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_debugfs.h 2015-07-28 01:20:58.285725306 +0200
+@@ -0,0 +1,52 @@
++/**
++ * Copyright (c) 2014 Raspberry Pi (Trading) Ltd. All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ * 1. Redistributions of source code must retain the above copyright
++ * notice, this list of conditions, and the following disclaimer,
++ * without modification.
++ * 2. Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * 3. The names of the above-listed copyright holders may not be used
++ * to endorse or promote products derived from this software without
++ * specific prior written permission.
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") version 2, as published by the Free
++ * Software Foundation.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#ifndef VCHIQ_DEBUGFS_H
++#define VCHIQ_DEBUGFS_H
++
++#include "vchiq_core.h"
++
++typedef struct vchiq_debugfs_node_struct
++{
++ struct dentry *dentry;
++} VCHIQ_DEBUGFS_NODE_T;
++
++int vchiq_debugfs_init(void);
++
++void vchiq_debugfs_deinit(void);
++
++int vchiq_debugfs_add_instance(VCHIQ_INSTANCE_T instance);
++
++void vchiq_debugfs_remove_instance(VCHIQ_INSTANCE_T instance);
++
++#endif /* VCHIQ_DEBUGFS_H */
+diff -Nur linux-4.1.3/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_genversion linux-xbian-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_genversion
+--- linux-4.1.3/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_genversion 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_genversion 2015-07-28 01:20:58.285725306 +0200
+@@ -0,0 +1,87 @@
++#!/usr/bin/perl -w
++
++use strict;
++
++#
++# Generate a version from available information
++#
++
++my $prefix = shift @ARGV;
++my $root = shift @ARGV;
++
++
++if ( not defined $root ) {
++ die "usage: $0 prefix root-dir\n";
++}
++
++if ( ! -d $root ) {
++ die "root directory $root not found\n";
++}
++
++my $version = "unknown";
++my $tainted = "";
++
++if ( -d "$root/.git" ) {
++ # attempt to work out git version. only do so
++ # on a linux build host, as cygwin builds are
++ # already slow enough
++
++ if ( -f "/usr/bin/git" || -f "/usr/local/bin/git" ) {
++ if (not open(F, "git --git-dir $root/.git rev-parse --verify HEAD|")) {
++ $version = "no git version";
++ }
++ else {
++ $version = <F>;
++ $version =~ s/[ \r\n]*$//; # chomp may not be enough (cygwin).
++ $version =~ s/^[ \r\n]*//; # chomp may not be enough (cygwin).
++ }
++
++ if (open(G, "git --git-dir $root/.git status --porcelain|")) {
++ $tainted = <G>;
++ $tainted =~ s/[ \r\n]*$//; # chomp may not be enough (cygwin).
++ $tainted =~ s/^[ \r\n]*//; # chomp may not be enough (cygwin).
++ if (length $tainted) {
++ $version = join ' ', $version, "(tainted)";
++ }
++ else {
++ $version = join ' ', $version, "(clean)";
++ }
++ }
++ }
++}
++
++my $hostname = `hostname`;
++$hostname =~ s/[ \r\n]*$//; # chomp may not be enough (cygwin).
++$hostname =~ s/^[ \r\n]*//; # chomp may not be enough (cygwin).
++
++
++print STDERR "Version $version\n";
++print <<EOF;
++#include "${prefix}_build_info.h"
++#include <linux/broadcom/vc_debug_sym.h>
++
++VC_DEBUG_DECLARE_STRING_VAR( ${prefix}_build_hostname, "$hostname" );
++VC_DEBUG_DECLARE_STRING_VAR( ${prefix}_build_version, "$version" );
++VC_DEBUG_DECLARE_STRING_VAR( ${prefix}_build_time, __TIME__ );
++VC_DEBUG_DECLARE_STRING_VAR( ${prefix}_build_date, __DATE__ );
++
++const char *vchiq_get_build_hostname( void )
++{
++ return vchiq_build_hostname;
++}
++
++const char *vchiq_get_build_version( void )
++{
++ return vchiq_build_version;
++}
++
++const char *vchiq_get_build_date( void )
++{
++ return vchiq_build_date;
++}
++
++const char *vchiq_get_build_time( void )
++{
++ return vchiq_build_time;
++}
++EOF
+diff -Nur linux-4.1.3/drivers/misc/vc04_services/interface/vchiq_arm/vchiq.h linux-xbian-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq.h
+--- linux-4.1.3/drivers/misc/vc04_services/interface/vchiq_arm/vchiq.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq.h 2015-07-28 01:20:58.285725306 +0200
+@@ -0,0 +1,40 @@
++/**
++ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ * 1. Redistributions of source code must retain the above copyright
++ * notice, this list of conditions, and the following disclaimer,
++ * without modification.
++ * 2. Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * 3. The names of the above-listed copyright holders may not be used
++ * to endorse or promote products derived from this software without
++ * specific prior written permission.
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") version 2, as published by the Free
++ * Software Foundation.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#ifndef VCHIQ_VCHIQ_H
++#define VCHIQ_VCHIQ_H
++
++#include "vchiq_if.h"
++#include "vchiq_util.h"
++
++#endif
+diff -Nur linux-4.1.3/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_if.h linux-xbian-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_if.h
+--- linux-4.1.3/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_if.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_if.h 2015-07-28 01:20:58.285725306 +0200
+@@ -0,0 +1,189 @@
++/**
++ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ * 1. Redistributions of source code must retain the above copyright
++ * notice, this list of conditions, and the following disclaimer,
++ * without modification.
++ * 2. Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * 3. The names of the above-listed copyright holders may not be used
++ * to endorse or promote products derived from this software without
++ * specific prior written permission.
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") version 2, as published by the Free
++ * Software Foundation.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#ifndef VCHIQ_IF_H
++#define VCHIQ_IF_H
++
++#include "interface/vchi/vchi_mh.h"
++
++#define VCHIQ_SERVICE_HANDLE_INVALID 0
++
++#define VCHIQ_SLOT_SIZE 4096
++#define VCHIQ_MAX_MSG_SIZE (VCHIQ_SLOT_SIZE - sizeof(VCHIQ_HEADER_T))
++#define VCHIQ_CHANNEL_SIZE VCHIQ_MAX_MSG_SIZE /* For backwards compatibility */
++
++#define VCHIQ_MAKE_FOURCC(x0, x1, x2, x3) \
++ (((x0) << 24) | ((x1) << 16) | ((x2) << 8) | (x3))
++#define VCHIQ_GET_SERVICE_USERDATA(service) vchiq_get_service_userdata(service)
++#define VCHIQ_GET_SERVICE_FOURCC(service) vchiq_get_service_fourcc(service)
++
++typedef enum {
++ VCHIQ_SERVICE_OPENED, /* service, -, - */
++ VCHIQ_SERVICE_CLOSED, /* service, -, - */
++ VCHIQ_MESSAGE_AVAILABLE, /* service, header, - */
++ VCHIQ_BULK_TRANSMIT_DONE, /* service, -, bulk_userdata */
++ VCHIQ_BULK_RECEIVE_DONE, /* service, -, bulk_userdata */
++ VCHIQ_BULK_TRANSMIT_ABORTED, /* service, -, bulk_userdata */
++ VCHIQ_BULK_RECEIVE_ABORTED /* service, -, bulk_userdata */
++} VCHIQ_REASON_T;
++
++typedef enum {
++ VCHIQ_ERROR = -1,
++ VCHIQ_SUCCESS = 0,
++ VCHIQ_RETRY = 1
++} VCHIQ_STATUS_T;
++
++typedef enum {
++ VCHIQ_BULK_MODE_CALLBACK,
++ VCHIQ_BULK_MODE_BLOCKING,
++ VCHIQ_BULK_MODE_NOCALLBACK,
++ VCHIQ_BULK_MODE_WAITING /* Reserved for internal use */
++} VCHIQ_BULK_MODE_T;
++
++typedef enum {
++ VCHIQ_SERVICE_OPTION_AUTOCLOSE,
++ VCHIQ_SERVICE_OPTION_SLOT_QUOTA,
++ VCHIQ_SERVICE_OPTION_MESSAGE_QUOTA,
++ VCHIQ_SERVICE_OPTION_SYNCHRONOUS,
++ VCHIQ_SERVICE_OPTION_TRACE
++} VCHIQ_SERVICE_OPTION_T;
++
++typedef struct vchiq_header_struct {
++ /* The message identifier - opaque to applications. */
++ int msgid;
++
++ /* Size of message data. */
++ unsigned int size;
++
++ char data[0]; /* message */
++} VCHIQ_HEADER_T;
++
++typedef struct {
++ const void *data;
++ unsigned int size;
++} VCHIQ_ELEMENT_T;
++
++typedef unsigned int VCHIQ_SERVICE_HANDLE_T;
++
++typedef VCHIQ_STATUS_T (*VCHIQ_CALLBACK_T)(VCHIQ_REASON_T, VCHIQ_HEADER_T *,
++ VCHIQ_SERVICE_HANDLE_T, void *);
++
++typedef struct vchiq_service_base_struct {
++ int fourcc;
++ VCHIQ_CALLBACK_T callback;
++ void *userdata;
++} VCHIQ_SERVICE_BASE_T;
++
++typedef struct vchiq_service_params_struct {
++ int fourcc;
++ VCHIQ_CALLBACK_T callback;
++ void *userdata;
++ short version; /* Increment for non-trivial changes */
++ short version_min; /* Update for incompatible changes */
++} VCHIQ_SERVICE_PARAMS_T;
++
++typedef struct vchiq_config_struct {
++ unsigned int max_msg_size;
++ unsigned int bulk_threshold; /* The message size above which it
++ is better to use a bulk transfer
++ (<= max_msg_size) */
++ unsigned int max_outstanding_bulks;
++ unsigned int max_services;
++ short version; /* The version of VCHIQ */
++ short version_min; /* The minimum compatible version of VCHIQ */
++} VCHIQ_CONFIG_T;
++
++typedef struct vchiq_instance_struct *VCHIQ_INSTANCE_T;
++typedef void (*VCHIQ_REMOTE_USE_CALLBACK_T)(void *cb_arg);
++
++extern VCHIQ_STATUS_T vchiq_initialise(VCHIQ_INSTANCE_T *pinstance);
++extern VCHIQ_STATUS_T vchiq_shutdown(VCHIQ_INSTANCE_T instance);
++extern VCHIQ_STATUS_T vchiq_connect(VCHIQ_INSTANCE_T instance);
++extern VCHIQ_STATUS_T vchiq_add_service(VCHIQ_INSTANCE_T instance,
++ const VCHIQ_SERVICE_PARAMS_T *params,
++ VCHIQ_SERVICE_HANDLE_T *pservice);
++extern VCHIQ_STATUS_T vchiq_open_service(VCHIQ_INSTANCE_T instance,
++ const VCHIQ_SERVICE_PARAMS_T *params,
++ VCHIQ_SERVICE_HANDLE_T *pservice);
++extern VCHIQ_STATUS_T vchiq_close_service(VCHIQ_SERVICE_HANDLE_T service);
++extern VCHIQ_STATUS_T vchiq_remove_service(VCHIQ_SERVICE_HANDLE_T service);
++extern VCHIQ_STATUS_T vchiq_use_service(VCHIQ_SERVICE_HANDLE_T service);
++extern VCHIQ_STATUS_T vchiq_use_service_no_resume(
++ VCHIQ_SERVICE_HANDLE_T service);
++extern VCHIQ_STATUS_T vchiq_release_service(VCHIQ_SERVICE_HANDLE_T service);
++
++extern VCHIQ_STATUS_T vchiq_queue_message(VCHIQ_SERVICE_HANDLE_T service,
++ const VCHIQ_ELEMENT_T *elements, unsigned int count);
++extern void vchiq_release_message(VCHIQ_SERVICE_HANDLE_T service,
++ VCHIQ_HEADER_T *header);
++extern VCHIQ_STATUS_T vchiq_queue_bulk_transmit(VCHIQ_SERVICE_HANDLE_T service,
++ const void *data, unsigned int size, void *userdata);
++extern VCHIQ_STATUS_T vchiq_queue_bulk_receive(VCHIQ_SERVICE_HANDLE_T service,
++ void *data, unsigned int size, void *userdata);
++extern VCHIQ_STATUS_T vchiq_queue_bulk_transmit_handle(
++ VCHIQ_SERVICE_HANDLE_T service, VCHI_MEM_HANDLE_T handle,
++ const void *offset, unsigned int size, void *userdata);
++extern VCHIQ_STATUS_T vchiq_queue_bulk_receive_handle(
++ VCHIQ_SERVICE_HANDLE_T service, VCHI_MEM_HANDLE_T handle,
++ void *offset, unsigned int size, void *userdata);
++extern VCHIQ_STATUS_T vchiq_bulk_transmit(VCHIQ_SERVICE_HANDLE_T service,
++ const void *data, unsigned int size, void *userdata,
++ VCHIQ_BULK_MODE_T mode);
++extern VCHIQ_STATUS_T vchiq_bulk_receive(VCHIQ_SERVICE_HANDLE_T service,
++ void *data, unsigned int size, void *userdata,
++ VCHIQ_BULK_MODE_T mode);
++extern VCHIQ_STATUS_T vchiq_bulk_transmit_handle(VCHIQ_SERVICE_HANDLE_T service,
++ VCHI_MEM_HANDLE_T handle, const void *offset, unsigned int size,
++ void *userdata, VCHIQ_BULK_MODE_T mode);
++extern VCHIQ_STATUS_T vchiq_bulk_receive_handle(VCHIQ_SERVICE_HANDLE_T service,
++ VCHI_MEM_HANDLE_T handle, void *offset, unsigned int size,
++ void *userdata, VCHIQ_BULK_MODE_T mode);
++extern int vchiq_get_client_id(VCHIQ_SERVICE_HANDLE_T service);
++extern void *vchiq_get_service_userdata(VCHIQ_SERVICE_HANDLE_T service);
++extern int vchiq_get_service_fourcc(VCHIQ_SERVICE_HANDLE_T service);
++extern VCHIQ_STATUS_T vchiq_get_config(VCHIQ_INSTANCE_T instance,
++ int config_size, VCHIQ_CONFIG_T *pconfig);
++extern VCHIQ_STATUS_T vchiq_set_service_option(VCHIQ_SERVICE_HANDLE_T service,
++ VCHIQ_SERVICE_OPTION_T option, int value);
++
++extern VCHIQ_STATUS_T vchiq_remote_use(VCHIQ_INSTANCE_T instance,
++ VCHIQ_REMOTE_USE_CALLBACK_T callback, void *cb_arg);
++extern VCHIQ_STATUS_T vchiq_remote_release(VCHIQ_INSTANCE_T instance);
++
++extern VCHIQ_STATUS_T vchiq_dump_phys_mem(VCHIQ_SERVICE_HANDLE_T service,
++ void *ptr, size_t num_bytes);
++
++extern VCHIQ_STATUS_T vchiq_get_peer_version(VCHIQ_SERVICE_HANDLE_T handle,
++ short *peer_version);
++
++#endif /* VCHIQ_IF_H */
+diff -Nur linux-4.1.3/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_ioctl.h linux-xbian-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_ioctl.h
+--- linux-4.1.3/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_ioctl.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_ioctl.h 2015-07-28 01:20:58.285725306 +0200
+@@ -0,0 +1,131 @@
++/**
++ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ * 1. Redistributions of source code must retain the above copyright
++ * notice, this list of conditions, and the following disclaimer,
++ * without modification.
++ * 2. Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * 3. The names of the above-listed copyright holders may not be used
++ * to endorse or promote products derived from this software without
++ * specific prior written permission.
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") version 2, as published by the Free
++ * Software Foundation.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#ifndef VCHIQ_IOCTLS_H
++#define VCHIQ_IOCTLS_H
++
++#include <linux/ioctl.h>
++#include "vchiq_if.h"
++
++#define VCHIQ_IOC_MAGIC 0xc4
++#define VCHIQ_INVALID_HANDLE (~0)
++
++typedef struct {
++ VCHIQ_SERVICE_PARAMS_T params;
++ int is_open;
++ int is_vchi;
++ unsigned int handle; /* OUT */
++} VCHIQ_CREATE_SERVICE_T;
++
++typedef struct {
++ unsigned int handle;
++ unsigned int count;
++ const VCHIQ_ELEMENT_T *elements;
++} VCHIQ_QUEUE_MESSAGE_T;
++
++typedef struct {
++ unsigned int handle;
++ void *data;
++ unsigned int size;
++ void *userdata;
++ VCHIQ_BULK_MODE_T mode;
++} VCHIQ_QUEUE_BULK_TRANSFER_T;
++
++typedef struct {
++ VCHIQ_REASON_T reason;
++ VCHIQ_HEADER_T *header;
++ void *service_userdata;
++ void *bulk_userdata;
++} VCHIQ_COMPLETION_DATA_T;
++
++typedef struct {
++ unsigned int count;
++ VCHIQ_COMPLETION_DATA_T *buf;
++ unsigned int msgbufsize;
++ unsigned int msgbufcount; /* IN/OUT */
++ void **msgbufs;
++} VCHIQ_AWAIT_COMPLETION_T;
++
++typedef struct {
++ unsigned int handle;
++ int blocking;
++ unsigned int bufsize;
++ void *buf;
++} VCHIQ_DEQUEUE_MESSAGE_T;
++
++typedef struct {
++ unsigned int config_size;
++ VCHIQ_CONFIG_T *pconfig;
++} VCHIQ_GET_CONFIG_T;
++
++typedef struct {
++ unsigned int handle;
++ VCHIQ_SERVICE_OPTION_T option;
++ int value;
++} VCHIQ_SET_SERVICE_OPTION_T;
++
++typedef struct {
++ void *virt_addr;
++ size_t num_bytes;
++} VCHIQ_DUMP_MEM_T;
++
++#define VCHIQ_IOC_CONNECT _IO(VCHIQ_IOC_MAGIC, 0)
++#define VCHIQ_IOC_SHUTDOWN _IO(VCHIQ_IOC_MAGIC, 1)
++#define VCHIQ_IOC_CREATE_SERVICE \
++ _IOWR(VCHIQ_IOC_MAGIC, 2, VCHIQ_CREATE_SERVICE_T)
++#define VCHIQ_IOC_REMOVE_SERVICE _IO(VCHIQ_IOC_MAGIC, 3)
++#define VCHIQ_IOC_QUEUE_MESSAGE \
++ _IOW(VCHIQ_IOC_MAGIC, 4, VCHIQ_QUEUE_MESSAGE_T)
++#define VCHIQ_IOC_QUEUE_BULK_TRANSMIT \
++ _IOWR(VCHIQ_IOC_MAGIC, 5, VCHIQ_QUEUE_BULK_TRANSFER_T)
++#define VCHIQ_IOC_QUEUE_BULK_RECEIVE \
++ _IOWR(VCHIQ_IOC_MAGIC, 6, VCHIQ_QUEUE_BULK_TRANSFER_T)
++#define VCHIQ_IOC_AWAIT_COMPLETION \
++ _IOWR(VCHIQ_IOC_MAGIC, 7, VCHIQ_AWAIT_COMPLETION_T)
++#define VCHIQ_IOC_DEQUEUE_MESSAGE \
++ _IOWR(VCHIQ_IOC_MAGIC, 8, VCHIQ_DEQUEUE_MESSAGE_T)
++#define VCHIQ_IOC_GET_CLIENT_ID _IO(VCHIQ_IOC_MAGIC, 9)
++#define VCHIQ_IOC_GET_CONFIG \
++ _IOWR(VCHIQ_IOC_MAGIC, 10, VCHIQ_GET_CONFIG_T)
++#define VCHIQ_IOC_CLOSE_SERVICE _IO(VCHIQ_IOC_MAGIC, 11)
++#define VCHIQ_IOC_USE_SERVICE _IO(VCHIQ_IOC_MAGIC, 12)
++#define VCHIQ_IOC_RELEASE_SERVICE _IO(VCHIQ_IOC_MAGIC, 13)
++#define VCHIQ_IOC_SET_SERVICE_OPTION \
++ _IOW(VCHIQ_IOC_MAGIC, 14, VCHIQ_SET_SERVICE_OPTION_T)
++#define VCHIQ_IOC_DUMP_PHYS_MEM \
++ _IOW(VCHIQ_IOC_MAGIC, 15, VCHIQ_DUMP_MEM_T)
++#define VCHIQ_IOC_LIB_VERSION _IO(VCHIQ_IOC_MAGIC, 16)
++#define VCHIQ_IOC_CLOSE_DELIVERED _IO(VCHIQ_IOC_MAGIC, 17)
++#define VCHIQ_IOC_MAX 17
++
++#endif
+diff -Nur linux-4.1.3/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_kern_lib.c linux-xbian-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_kern_lib.c
+--- linux-4.1.3/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_kern_lib.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_kern_lib.c 2015-07-28 01:20:58.285725306 +0200
+@@ -0,0 +1,458 @@
++/**
++ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ * 1. Redistributions of source code must retain the above copyright
++ * notice, this list of conditions, and the following disclaimer,
++ * without modification.
++ * 2. Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * 3. The names of the above-listed copyright holders may not be used
++ * to endorse or promote products derived from this software without
++ * specific prior written permission.
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") version 2, as published by the Free
++ * Software Foundation.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++/* ---- Include Files ---------------------------------------------------- */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/mutex.h>
++
++#include "vchiq_core.h"
++#include "vchiq_arm.h"
++#include "vchiq_killable.h"
++
++/* ---- Public Variables ------------------------------------------------- */
++
++/* ---- Private Constants and Types -------------------------------------- */
++
++struct bulk_waiter_node {
++ struct bulk_waiter bulk_waiter;
++ int pid;
++ struct list_head list;
++};
++
++struct vchiq_instance_struct {
++ VCHIQ_STATE_T *state;
++
++ int connected;
++
++ struct list_head bulk_waiter_list;
++ struct mutex bulk_waiter_list_mutex;
++};
++
++static VCHIQ_STATUS_T
++vchiq_blocking_bulk_transfer(VCHIQ_SERVICE_HANDLE_T handle, void *data,
++ unsigned int size, VCHIQ_BULK_DIR_T dir);
++
++/****************************************************************************
++*
++* vchiq_initialise
++*
++***************************************************************************/
++#define VCHIQ_INIT_RETRIES 10
++VCHIQ_STATUS_T vchiq_initialise(VCHIQ_INSTANCE_T *instanceOut)
++{
++ VCHIQ_STATUS_T status = VCHIQ_ERROR;
++ VCHIQ_STATE_T *state;
++ VCHIQ_INSTANCE_T instance = NULL;
++ int i;
++
++ vchiq_log_trace(vchiq_core_log_level, "%s called", __func__);
++
++ /* VideoCore may not be ready due to boot up timing.
++ It may never be ready if kernel and firmware are mismatched, so don't block forever. */
++ for (i=0; i<VCHIQ_INIT_RETRIES; i++) {
++ state = vchiq_get_state();
++ if (state)
++ break;
++ udelay(500);
++ }
++ if (i==VCHIQ_INIT_RETRIES) {
++ vchiq_log_error(vchiq_core_log_level,
++ "%s: videocore not initialized\n", __func__);
++ goto failed;
++ } else if (i>0) {
++ vchiq_log_warning(vchiq_core_log_level,
++ "%s: videocore initialized after %d retries\n", __func__, i);
++ }
++
++ instance = kzalloc(sizeof(*instance), GFP_KERNEL);
++ if (!instance) {
++ vchiq_log_error(vchiq_core_log_level,
++ "%s: error allocating vchiq instance\n", __func__);
++ goto failed;
++ }
++
++ instance->connected = 0;
++ instance->state = state;
++ mutex_init(&instance->bulk_waiter_list_mutex);
++ INIT_LIST_HEAD(&instance->bulk_waiter_list);
++
++ *instanceOut = instance;
++
++ status = VCHIQ_SUCCESS;
++
++failed:
++ vchiq_log_trace(vchiq_core_log_level,
++ "%s(%p): returning %d", __func__, instance, status);
++
++ return status;
++}
++EXPORT_SYMBOL(vchiq_initialise);
++
++/****************************************************************************
++*
++* vchiq_shutdown
++*
++***************************************************************************/
++
++VCHIQ_STATUS_T vchiq_shutdown(VCHIQ_INSTANCE_T instance)
++{
++ VCHIQ_STATUS_T status;
++ VCHIQ_STATE_T *state = instance->state;
++
++ vchiq_log_trace(vchiq_core_log_level,
++ "%s(%p) called", __func__, instance);
++
++ if (mutex_lock_interruptible(&state->mutex) != 0)
++ return VCHIQ_RETRY;
++
++ /* Remove all services */
++ status = vchiq_shutdown_internal(state, instance);
++
++ mutex_unlock(&state->mutex);
++
++ vchiq_log_trace(vchiq_core_log_level,
++ "%s(%p): returning %d", __func__, instance, status);
++
++ if (status == VCHIQ_SUCCESS) {
++ struct list_head *pos, *next;
++ list_for_each_safe(pos, next,
++ &instance->bulk_waiter_list) {
++ struct bulk_waiter_node *waiter;
++ waiter = list_entry(pos,
++ struct bulk_waiter_node,
++ list);
++ list_del(pos);
++ vchiq_log_info(vchiq_arm_log_level,
++ "bulk_waiter - cleaned up %x "
++ "for pid %d",
++ (unsigned int)waiter, waiter->pid);
++ kfree(waiter);
++ }
++ kfree(instance);
++ }
++
++ return status;
++}
++EXPORT_SYMBOL(vchiq_shutdown);
++
++/****************************************************************************
++*
++* vchiq_is_connected
++*
++***************************************************************************/
++
++int vchiq_is_connected(VCHIQ_INSTANCE_T instance)
++{
++ return instance->connected;
++}
++
++/****************************************************************************
++*
++* vchiq_connect
++*
++***************************************************************************/
++
++VCHIQ_STATUS_T vchiq_connect(VCHIQ_INSTANCE_T instance)
++{
++ VCHIQ_STATUS_T status;
++ VCHIQ_STATE_T *state = instance->state;
++
++ vchiq_log_trace(vchiq_core_log_level,
++ "%s(%p) called", __func__, instance);
++
++ if (mutex_lock_interruptible(&state->mutex) != 0) {
++ vchiq_log_trace(vchiq_core_log_level,
++ "%s: call to mutex_lock failed", __func__);
++ status = VCHIQ_RETRY;
++ goto failed;
++ }
++ status = vchiq_connect_internal(state, instance);
++
++ if (status == VCHIQ_SUCCESS)
++ instance->connected = 1;
++
++ mutex_unlock(&state->mutex);
++
++failed:
++ vchiq_log_trace(vchiq_core_log_level,
++ "%s(%p): returning %d", __func__, instance, status);
++
++ return status;
++}
++EXPORT_SYMBOL(vchiq_connect);
++
++/****************************************************************************
++*
++* vchiq_add_service
++*
++***************************************************************************/
++
++VCHIQ_STATUS_T vchiq_add_service(
++ VCHIQ_INSTANCE_T instance,
++ const VCHIQ_SERVICE_PARAMS_T *params,
++ VCHIQ_SERVICE_HANDLE_T *phandle)
++{
++ VCHIQ_STATUS_T status;
++ VCHIQ_STATE_T *state = instance->state;
++ VCHIQ_SERVICE_T *service = NULL;
++ int srvstate;
++
++ vchiq_log_trace(vchiq_core_log_level,
++ "%s(%p) called", __func__, instance);
++
++ *phandle = VCHIQ_SERVICE_HANDLE_INVALID;
++
++ srvstate = vchiq_is_connected(instance)
++ ? VCHIQ_SRVSTATE_LISTENING
++ : VCHIQ_SRVSTATE_HIDDEN;
++
++ service = vchiq_add_service_internal(
++ state,
++ params,
++ srvstate,
++ instance,
++ NULL);
++
++ if (service) {
++ *phandle = service->handle;
++ status = VCHIQ_SUCCESS;
++ } else
++ status = VCHIQ_ERROR;
++
++ vchiq_log_trace(vchiq_core_log_level,
++ "%s(%p): returning %d", __func__, instance, status);
++
++ return status;
++}
++EXPORT_SYMBOL(vchiq_add_service);
++
++/****************************************************************************
++*
++* vchiq_open_service
++*
++***************************************************************************/
++
++VCHIQ_STATUS_T vchiq_open_service(
++ VCHIQ_INSTANCE_T instance,
++ const VCHIQ_SERVICE_PARAMS_T *params,
++ VCHIQ_SERVICE_HANDLE_T *phandle)
++{
++ VCHIQ_STATUS_T status = VCHIQ_ERROR;
++ VCHIQ_STATE_T *state = instance->state;
++ VCHIQ_SERVICE_T *service = NULL;
++
++ vchiq_log_trace(vchiq_core_log_level,
++ "%s(%p) called", __func__, instance);
++
++ *phandle = VCHIQ_SERVICE_HANDLE_INVALID;
++
++ if (!vchiq_is_connected(instance))
++ goto failed;
++
++ service = vchiq_add_service_internal(state,
++ params,
++ VCHIQ_SRVSTATE_OPENING,
++ instance,
++ NULL);
++
++ if (service) {
++ *phandle = service->handle;
++ status = vchiq_open_service_internal(service, current->pid);
++ if (status != VCHIQ_SUCCESS) {
++ vchiq_remove_service(service->handle);
++ *phandle = VCHIQ_SERVICE_HANDLE_INVALID;
++ }
++ }
++
++failed:
++ vchiq_log_trace(vchiq_core_log_level,
++ "%s(%p): returning %d", __func__, instance, status);
++
++ return status;
++}
++EXPORT_SYMBOL(vchiq_open_service);
++
++VCHIQ_STATUS_T
++vchiq_queue_bulk_transmit(VCHIQ_SERVICE_HANDLE_T handle,
++ const void *data, unsigned int size, void *userdata)
++{
++ return vchiq_bulk_transfer(handle,
++ VCHI_MEM_HANDLE_INVALID, (void *)data, size, userdata,
++ VCHIQ_BULK_MODE_CALLBACK, VCHIQ_BULK_TRANSMIT);
++}
++EXPORT_SYMBOL(vchiq_queue_bulk_transmit);
++
++VCHIQ_STATUS_T
++vchiq_queue_bulk_receive(VCHIQ_SERVICE_HANDLE_T handle, void *data,
++ unsigned int size, void *userdata)
++{
++ return vchiq_bulk_transfer(handle,
++ VCHI_MEM_HANDLE_INVALID, data, size, userdata,
++ VCHIQ_BULK_MODE_CALLBACK, VCHIQ_BULK_RECEIVE);
++}
++EXPORT_SYMBOL(vchiq_queue_bulk_receive);
++
++VCHIQ_STATUS_T
++vchiq_bulk_transmit(VCHIQ_SERVICE_HANDLE_T handle, const void *data,
++ unsigned int size, void *userdata, VCHIQ_BULK_MODE_T mode)
++{
++ VCHIQ_STATUS_T status;
++
++ switch (mode) {
++ case VCHIQ_BULK_MODE_NOCALLBACK:
++ case VCHIQ_BULK_MODE_CALLBACK:
++ status = vchiq_bulk_transfer(handle,
++ VCHI_MEM_HANDLE_INVALID, (void *)data, size, userdata,
++ mode, VCHIQ_BULK_TRANSMIT);
++ break;
++ case VCHIQ_BULK_MODE_BLOCKING:
++ status = vchiq_blocking_bulk_transfer(handle,
++ (void *)data, size, VCHIQ_BULK_TRANSMIT);
++ break;
++ default:
++ return VCHIQ_ERROR;
++ }
++
++ return status;
++}
++EXPORT_SYMBOL(vchiq_bulk_transmit);
++
++VCHIQ_STATUS_T
++vchiq_bulk_receive(VCHIQ_SERVICE_HANDLE_T handle, void *data,
++ unsigned int size, void *userdata, VCHIQ_BULK_MODE_T mode)
++{
++ VCHIQ_STATUS_T status;
++
++ switch (mode) {
++ case VCHIQ_BULK_MODE_NOCALLBACK:
++ case VCHIQ_BULK_MODE_CALLBACK:
++ status = vchiq_bulk_transfer(handle,
++ VCHI_MEM_HANDLE_INVALID, data, size, userdata,
++ mode, VCHIQ_BULK_RECEIVE);
++ break;
++ case VCHIQ_BULK_MODE_BLOCKING:
++ status = vchiq_blocking_bulk_transfer(handle,
++ (void *)data, size, VCHIQ_BULK_RECEIVE);
++ break;
++ default:
++ return VCHIQ_ERROR;
++ }
++
++ return status;
++}
++EXPORT_SYMBOL(vchiq_bulk_receive);
++
++static VCHIQ_STATUS_T
++vchiq_blocking_bulk_transfer(VCHIQ_SERVICE_HANDLE_T handle, void *data,
++ unsigned int size, VCHIQ_BULK_DIR_T dir)
++{
++ VCHIQ_INSTANCE_T instance;
++ VCHIQ_SERVICE_T *service;
++ VCHIQ_STATUS_T status;
++ struct bulk_waiter_node *waiter = NULL;
++ struct list_head *pos;
++
++ service = find_service_by_handle(handle);
++ if (!service)
++ return VCHIQ_ERROR;
++
++ instance = service->instance;
++
++ unlock_service(service);
++
++ mutex_lock(&instance->bulk_waiter_list_mutex);
++ list_for_each(pos, &instance->bulk_waiter_list) {
++ if (list_entry(pos, struct bulk_waiter_node,
++ list)->pid == current->pid) {
++ waiter = list_entry(pos,
++ struct bulk_waiter_node,
++ list);
++ list_del(pos);
++ break;
++ }
++ }
++ mutex_unlock(&instance->bulk_waiter_list_mutex);
++
++ if (waiter) {
++ VCHIQ_BULK_T *bulk = waiter->bulk_waiter.bulk;
++ if (bulk) {
++ /* This thread has an outstanding bulk transfer. */
++ if ((bulk->data != data) ||
++ (bulk->size != size)) {
++ /* This is not a retry of the previous one.
++ ** Cancel the signal when the transfer
++ ** completes. */
++ spin_lock(&bulk_waiter_spinlock);
++ bulk->userdata = NULL;
++ spin_unlock(&bulk_waiter_spinlock);
++ }
++ }
++ }
++
++ if (!waiter) {
++ waiter = kzalloc(sizeof(struct bulk_waiter_node), GFP_KERNEL);
++ if (!waiter) {
++ vchiq_log_error(vchiq_core_log_level,
++ "%s - out of memory", __func__);
++ return VCHIQ_ERROR;
++ }
++ }
++
++ status = vchiq_bulk_transfer(handle, VCHI_MEM_HANDLE_INVALID,
++ data, size, &waiter->bulk_waiter, VCHIQ_BULK_MODE_BLOCKING,
++ dir);
++ if ((status != VCHIQ_RETRY) || fatal_signal_pending(current) ||
++ !waiter->bulk_waiter.bulk) {
++ VCHIQ_BULK_T *bulk = waiter->bulk_waiter.bulk;
++ if (bulk) {
++ /* Cancel the signal when the transfer
++ ** completes. */
++ spin_lock(&bulk_waiter_spinlock);
++ bulk->userdata = NULL;
++ spin_unlock(&bulk_waiter_spinlock);
++ }
++ kfree(waiter);
++ } else {
++ waiter->pid = current->pid;
++ mutex_lock(&instance->bulk_waiter_list_mutex);
++ list_add(&waiter->list, &instance->bulk_waiter_list);
++ mutex_unlock(&instance->bulk_waiter_list_mutex);
++ vchiq_log_info(vchiq_arm_log_level,
++ "saved bulk_waiter %x for pid %d",
++ (unsigned int)waiter, current->pid);
++ }
++
++ return status;
++}
+diff -Nur linux-4.1.3/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_killable.h linux-xbian-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_killable.h
+--- linux-4.1.3/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_killable.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_killable.h 2015-07-28 01:20:58.285725306 +0200
+@@ -0,0 +1,69 @@
++/**
++ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ * 1. Redistributions of source code must retain the above copyright
++ * notice, this list of conditions, and the following disclaimer,
++ * without modification.
++ * 2. Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * 3. The names of the above-listed copyright holders may not be used
++ * to endorse or promote products derived from this software without
++ * specific prior written permission.
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") version 2, as published by the Free
++ * Software Foundation.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#ifndef VCHIQ_KILLABLE_H
++#define VCHIQ_KILLABLE_H
++
++#include <linux/mutex.h>
++#include <linux/semaphore.h>
++
++#define SHUTDOWN_SIGS (sigmask(SIGKILL) | sigmask(SIGINT) | sigmask(SIGQUIT) | sigmask(SIGTRAP) | sigmask(SIGSTOP) | sigmask(SIGCONT))
++
++static inline int __must_check down_interruptible_killable(struct semaphore *sem)
++{
++ /* Allow interception of killable signals only. We don't want to be interrupted by harmless signals like SIGALRM */
++ int ret;
++ sigset_t blocked, oldset;
++ siginitsetinv(&blocked, SHUTDOWN_SIGS);
++ sigprocmask(SIG_SETMASK, &blocked, &oldset);
++ ret = down_interruptible(sem);
++ sigprocmask(SIG_SETMASK, &oldset, NULL);
++ return ret;
++}
++#define down_interruptible down_interruptible_killable
++
++
++static inline int __must_check mutex_lock_interruptible_killable(struct mutex *lock)
++{
++ /* Allow interception of killable signals only. We don't want to be interrupted by harmless signals like SIGALRM */
++ int ret;
++ sigset_t blocked, oldset;
++ siginitsetinv(&blocked, SHUTDOWN_SIGS);
++ sigprocmask(SIG_SETMASK, &blocked, &oldset);
++ ret = mutex_lock_interruptible(lock);
++ sigprocmask(SIG_SETMASK, &oldset, NULL);
++ return ret;
++}
++#define mutex_lock_interruptible mutex_lock_interruptible_killable
++
++#endif
+diff -Nur linux-4.1.3/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_memdrv.h linux-xbian-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_memdrv.h
+--- linux-4.1.3/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_memdrv.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_memdrv.h 2015-07-28 01:20:58.285725306 +0200
+@@ -0,0 +1,71 @@
++/**
++ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ * 1. Redistributions of source code must retain the above copyright
++ * notice, this list of conditions, and the following disclaimer,
++ * without modification.
++ * 2. Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * 3. The names of the above-listed copyright holders may not be used
++ * to endorse or promote products derived from this software without
++ * specific prior written permission.
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") version 2, as published by the Free
++ * Software Foundation.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#ifndef VCHIQ_MEMDRV_H
++#define VCHIQ_MEMDRV_H
++
++/* ---- Include Files ----------------------------------------------------- */
++
++#include <linux/kernel.h>
++#include "vchiq_if.h"
++
++/* ---- Constants and Types ---------------------------------------------- */
++
++typedef struct {
++ void *armSharedMemVirt;
++ dma_addr_t armSharedMemPhys;
++ size_t armSharedMemSize;
++
++ void *vcSharedMemVirt;
++ dma_addr_t vcSharedMemPhys;
++ size_t vcSharedMemSize;
++} VCHIQ_SHARED_MEM_INFO_T;
++
++/* ---- Variable Externs ------------------------------------------------- */
++
++/* ---- Function Prototypes ---------------------------------------------- */
++
++void vchiq_get_shared_mem_info(VCHIQ_SHARED_MEM_INFO_T *info);
++
++VCHIQ_STATUS_T vchiq_memdrv_initialise(void);
++
++VCHIQ_STATUS_T vchiq_userdrv_create_instance(
++ const VCHIQ_PLATFORM_DATA_T * platform_data);
++
++VCHIQ_STATUS_T vchiq_userdrv_suspend(
++ const VCHIQ_PLATFORM_DATA_T * platform_data);
++
++VCHIQ_STATUS_T vchiq_userdrv_resume(
++ const VCHIQ_PLATFORM_DATA_T * platform_data);
++
++#endif
+diff -Nur linux-4.1.3/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_pagelist.h linux-xbian-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_pagelist.h
+--- linux-4.1.3/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_pagelist.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_pagelist.h 2015-07-28 01:20:58.285725306 +0200
+@@ -0,0 +1,58 @@
++/**
++ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ * 1. Redistributions of source code must retain the above copyright
++ * notice, this list of conditions, and the following disclaimer,
++ * without modification.
++ * 2. Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * 3. The names of the above-listed copyright holders may not be used
++ * to endorse or promote products derived from this software without
++ * specific prior written permission.
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") version 2, as published by the Free
++ * Software Foundation.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#ifndef VCHIQ_PAGELIST_H
++#define VCHIQ_PAGELIST_H
++
++#ifndef PAGE_SIZE
++#define PAGE_SIZE 4096
++#endif
++#define CACHE_LINE_SIZE 32
++#define PAGELIST_WRITE 0
++#define PAGELIST_READ 1
++#define PAGELIST_READ_WITH_FRAGMENTS 2
++
++typedef struct pagelist_struct {
++ unsigned long length;
++ unsigned short type;
++ unsigned short offset;
++ unsigned long addrs[1]; /* N.B. 12 LSBs hold the number of following
++ pages at consecutive addresses. */
++} PAGELIST_T;
++
++typedef struct fragments_struct {
++ char headbuf[CACHE_LINE_SIZE];
++ char tailbuf[CACHE_LINE_SIZE];
++} FRAGMENTS_T;
++
++#endif /* VCHIQ_PAGELIST_H */
+diff -Nur linux-4.1.3/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_shim.c linux-xbian-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_shim.c
+--- linux-4.1.3/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_shim.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_shim.c 2015-07-28 01:20:58.285725306 +0200
+@@ -0,0 +1,860 @@
++/**
++ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ * 1. Redistributions of source code must retain the above copyright
++ * notice, this list of conditions, and the following disclaimer,
++ * without modification.
++ * 2. Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * 3. The names of the above-listed copyright holders may not be used
++ * to endorse or promote products derived from this software without
++ * specific prior written permission.
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") version 2, as published by the Free
++ * Software Foundation.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++#include <linux/module.h>
++#include <linux/types.h>
++
++#include "interface/vchi/vchi.h"
++#include "vchiq.h"
++#include "vchiq_core.h"
++
++#include "vchiq_util.h"
++
++#include <stddef.h>
++
++#define vchiq_status_to_vchi(status) ((int32_t)status)
++
++typedef struct {
++ VCHIQ_SERVICE_HANDLE_T handle;
++
++ VCHIU_QUEUE_T queue;
++
++ VCHI_CALLBACK_T callback;
++ void *callback_param;
++} SHIM_SERVICE_T;
++
++/* ----------------------------------------------------------------------
++ * return pointer to the mphi message driver function table
++ * -------------------------------------------------------------------- */
++const VCHI_MESSAGE_DRIVER_T *
++vchi_mphi_message_driver_func_table(void)
++{
++ return NULL;
++}
++
++/* ----------------------------------------------------------------------
++ * return a pointer to the 'single' connection driver fops
++ * -------------------------------------------------------------------- */
++const VCHI_CONNECTION_API_T *
++single_get_func_table(void)
++{
++ return NULL;
++}
++
++VCHI_CONNECTION_T *vchi_create_connection(
++ const VCHI_CONNECTION_API_T *function_table,
++ const VCHI_MESSAGE_DRIVER_T *low_level)
++{
++ (void)function_table;
++ (void)low_level;
++ return NULL;
++}
++
++/***********************************************************
++ * Name: vchi_msg_peek
++ *
++ * Arguments: const VCHI_SERVICE_HANDLE_T handle,
++ * void **data,
++ * uint32_t *msg_size,
++
++
++ * VCHI_FLAGS_T flags
++ *
++ * Description: Routine to return a pointer to the current message (to allow in
++ * place processing). The message can be removed using
++ * vchi_msg_remove when you're finished
++ *
++ * Returns: int32_t - success == 0
++ *
++ ***********************************************************/
++int32_t vchi_msg_peek(VCHI_SERVICE_HANDLE_T handle,
++ void **data,
++ uint32_t *msg_size,
++ VCHI_FLAGS_T flags)
++{
++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle;
++ VCHIQ_HEADER_T *header;
++
++ WARN_ON((flags != VCHI_FLAGS_NONE) &&
++ (flags != VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE));
++
++ if (flags == VCHI_FLAGS_NONE)
++ if (vchiu_queue_is_empty(&service->queue))
++ return -1;
++
++ header = vchiu_queue_peek(&service->queue);
++
++ *data = header->data;
++ *msg_size = header->size;
++
++ return 0;
++}
++EXPORT_SYMBOL(vchi_msg_peek);
++
++/***********************************************************
++ * Name: vchi_msg_remove
++ *
++ * Arguments: const VCHI_SERVICE_HANDLE_T handle,
++ *
++ * Description: Routine to remove a message (after it has been read with
++ * vchi_msg_peek)
++ *
++ * Returns: int32_t - success == 0
++ *
++ ***********************************************************/
++int32_t vchi_msg_remove(VCHI_SERVICE_HANDLE_T handle)
++{
++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle;
++ VCHIQ_HEADER_T *header;
++
++ header = vchiu_queue_pop(&service->queue);
++
++ vchiq_release_message(service->handle, header);
++
++ return 0;
++}
++EXPORT_SYMBOL(vchi_msg_remove);
++
++/***********************************************************
++ * Name: vchi_msg_queue
++ *
++ * Arguments: VCHI_SERVICE_HANDLE_T handle,
++ * const void *data,
++ * uint32_t data_size,
++ * VCHI_FLAGS_T flags,
++ * void *msg_handle,
++ *
++ * Description: Thin wrapper to queue a message onto a connection
++ *
++ * Returns: int32_t - success == 0
++ *
++ ***********************************************************/
++int32_t vchi_msg_queue(VCHI_SERVICE_HANDLE_T handle,
++ const void *data,
++ uint32_t data_size,
++ VCHI_FLAGS_T flags,
++ void *msg_handle)
++{
++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle;
++ VCHIQ_ELEMENT_T element = {data, data_size};
++ VCHIQ_STATUS_T status;
++
++ (void)msg_handle;
++
++ WARN_ON(flags != VCHI_FLAGS_BLOCK_UNTIL_QUEUED);
++
++ status = vchiq_queue_message(service->handle, &element, 1);
++
++ /* vchiq_queue_message() may return VCHIQ_RETRY, so we need to
++ ** implement a retry mechanism since this function is supposed
++ ** to block until queued
++ */
++ while (status == VCHIQ_RETRY) {
++ msleep(1);
++ status = vchiq_queue_message(service->handle, &element, 1);
++ }
++
++ return vchiq_status_to_vchi(status);
++}
++EXPORT_SYMBOL(vchi_msg_queue);
++
++/***********************************************************
++ * Name: vchi_bulk_queue_receive
++ *
++ * Arguments: VCHI_BULK_HANDLE_T handle,
++ * void *data_dst,
++ * const uint32_t data_size,
++ * VCHI_FLAGS_T flags
++ * void *bulk_handle
++ *
++ * Description: Routine to setup a rcv buffer
++ *
++ * Returns: int32_t - success == 0
++ *
++ ***********************************************************/
++int32_t vchi_bulk_queue_receive(VCHI_SERVICE_HANDLE_T handle,
++ void *data_dst,
++ uint32_t data_size,
++ VCHI_FLAGS_T flags,
++ void *bulk_handle)
++{
++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle;
++ VCHIQ_BULK_MODE_T mode;
++ VCHIQ_STATUS_T status;
++
++ switch ((int)flags) {
++ case VCHI_FLAGS_CALLBACK_WHEN_OP_COMPLETE
++ | VCHI_FLAGS_BLOCK_UNTIL_QUEUED:
++ WARN_ON(!service->callback);
++ mode = VCHIQ_BULK_MODE_CALLBACK;
++ break;
++ case VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE:
++ mode = VCHIQ_BULK_MODE_BLOCKING;
++ break;
++ case VCHI_FLAGS_BLOCK_UNTIL_QUEUED:
++ case VCHI_FLAGS_NONE:
++ mode = VCHIQ_BULK_MODE_NOCALLBACK;
++ break;
++ default:
++ WARN(1, "unsupported message\n");
++ return vchiq_status_to_vchi(VCHIQ_ERROR);
++ }
++
++ status = vchiq_bulk_receive(service->handle, data_dst, data_size,
++ bulk_handle, mode);
++
++ /* vchiq_bulk_receive() may return VCHIQ_RETRY, so we need to
++ ** implement a retry mechanism since this function is supposed
++ ** to block until queued
++ */
++ while (status == VCHIQ_RETRY) {
++ msleep(1);
++ status = vchiq_bulk_receive(service->handle, data_dst,
++ data_size, bulk_handle, mode);
++ }
++
++ return vchiq_status_to_vchi(status);
++}
++EXPORT_SYMBOL(vchi_bulk_queue_receive);
++
++/***********************************************************
++ * Name: vchi_bulk_queue_transmit
++ *
++ * Arguments: VCHI_BULK_HANDLE_T handle,
++ * const void *data_src,
++ * uint32_t data_size,
++ * VCHI_FLAGS_T flags,
++ * void *bulk_handle
++ *
++ * Description: Routine to transmit some data
++ *
++ * Returns: int32_t - success == 0
++ *
++ ***********************************************************/
++int32_t vchi_bulk_queue_transmit(VCHI_SERVICE_HANDLE_T handle,
++ const void *data_src,
++ uint32_t data_size,
++ VCHI_FLAGS_T flags,
++ void *bulk_handle)
++{
++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle;
++ VCHIQ_BULK_MODE_T mode;
++ VCHIQ_STATUS_T status;
++
++ switch ((int)flags) {
++ case VCHI_FLAGS_CALLBACK_WHEN_OP_COMPLETE
++ | VCHI_FLAGS_BLOCK_UNTIL_QUEUED:
++ WARN_ON(!service->callback);
++ mode = VCHIQ_BULK_MODE_CALLBACK;
++ break;
++ case VCHI_FLAGS_BLOCK_UNTIL_DATA_READ:
++ case VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE:
++ mode = VCHIQ_BULK_MODE_BLOCKING;
++ break;
++ case VCHI_FLAGS_BLOCK_UNTIL_QUEUED:
++ case VCHI_FLAGS_NONE:
++ mode = VCHIQ_BULK_MODE_NOCALLBACK;
++ break;
++ default:
++ WARN(1, "unsupported message\n");
++ return vchiq_status_to_vchi(VCHIQ_ERROR);
++ }
++
++ status = vchiq_bulk_transmit(service->handle, data_src, data_size,
++ bulk_handle, mode);
++
++ /* vchiq_bulk_transmit() may return VCHIQ_RETRY, so we need to
++ ** implement a retry mechanism since this function is supposed
++ ** to block until queued
++ */
++ while (status == VCHIQ_RETRY) {
++ msleep(1);
++ status = vchiq_bulk_transmit(service->handle, data_src,
++ data_size, bulk_handle, mode);
++ }
++
++ return vchiq_status_to_vchi(status);
++}
++EXPORT_SYMBOL(vchi_bulk_queue_transmit);
++
++/***********************************************************
++ * Name: vchi_msg_dequeue
++ *
++ * Arguments: VCHI_SERVICE_HANDLE_T handle,
++ * void *data,
++ * uint32_t max_data_size_to_read,
++ * uint32_t *actual_msg_size
++ * VCHI_FLAGS_T flags
++ *
++ * Description: Routine to dequeue a message into the supplied buffer
++ *
++ * Returns: int32_t - success == 0
++ *
++ ***********************************************************/
++int32_t vchi_msg_dequeue(VCHI_SERVICE_HANDLE_T handle,
++ void *data,
++ uint32_t max_data_size_to_read,
++ uint32_t *actual_msg_size,
++ VCHI_FLAGS_T flags)
++{
++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle;
++ VCHIQ_HEADER_T *header;
++
++ WARN_ON((flags != VCHI_FLAGS_NONE) &&
++ (flags != VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE));
++
++ if (flags == VCHI_FLAGS_NONE)
++ if (vchiu_queue_is_empty(&service->queue))
++ return -1;
++
++ header = vchiu_queue_pop(&service->queue);
++
++ memcpy(data, header->data, header->size < max_data_size_to_read ?
++ header->size : max_data_size_to_read);
++
++ *actual_msg_size = header->size;
++
++ vchiq_release_message(service->handle, header);
++
++ return 0;
++}
++EXPORT_SYMBOL(vchi_msg_dequeue);
++
++/***********************************************************
++ * Name: vchi_msg_queuev
++ *
++ * Arguments: VCHI_SERVICE_HANDLE_T handle,
++ * VCHI_MSG_VECTOR_T *vector,
++ * uint32_t count,
++ * VCHI_FLAGS_T flags,
++ * void *msg_handle
++ *
++ * Description: Thin wrapper to queue a message onto a connection
++ *
++ * Returns: int32_t - success == 0
++ *
++ ***********************************************************/
++
++vchiq_static_assert(sizeof(VCHI_MSG_VECTOR_T) == sizeof(VCHIQ_ELEMENT_T));
++vchiq_static_assert(offsetof(VCHI_MSG_VECTOR_T, vec_base) ==
++ offsetof(VCHIQ_ELEMENT_T, data));
++vchiq_static_assert(offsetof(VCHI_MSG_VECTOR_T, vec_len) ==
++ offsetof(VCHIQ_ELEMENT_T, size));
++
++int32_t vchi_msg_queuev(VCHI_SERVICE_HANDLE_T handle,
++ VCHI_MSG_VECTOR_T *vector,
++ uint32_t count,
++ VCHI_FLAGS_T flags,
++ void *msg_handle)
++{
++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle;
++
++ (void)msg_handle;
++
++ WARN_ON(flags != VCHI_FLAGS_BLOCK_UNTIL_QUEUED);
++
++ return vchiq_status_to_vchi(vchiq_queue_message(service->handle,
++ (const VCHIQ_ELEMENT_T *)vector, count));
++}
++EXPORT_SYMBOL(vchi_msg_queuev);
++
++/***********************************************************
++ * Name: vchi_held_msg_release
++ *
++ * Arguments: VCHI_HELD_MSG_T *message
++ *
++ * Description: Routine to release a held message (after it has been read with
++ * vchi_msg_hold)
++ *
++ * Returns: int32_t - success == 0
++ *
++ ***********************************************************/
++int32_t vchi_held_msg_release(VCHI_HELD_MSG_T *message)
++{
++ vchiq_release_message((VCHIQ_SERVICE_HANDLE_T)message->service,
++ (VCHIQ_HEADER_T *)message->message);
++
++ return 0;
++}
++EXPORT_SYMBOL(vchi_held_msg_release);
++
++/***********************************************************
++ * Name: vchi_msg_hold
++ *
++ * Arguments: VCHI_SERVICE_HANDLE_T handle,
++ * void **data,
++ * uint32_t *msg_size,
++ * VCHI_FLAGS_T flags,
++ * VCHI_HELD_MSG_T *message_handle
++ *
++ * Description: Routine to return a pointer to the current message (to allow
++ * in place processing). The message is dequeued - don't forget
++ * to release the message using vchi_held_msg_release when you're
++ * finished.
++ *
++ * Returns: int32_t - success == 0
++ *
++ ***********************************************************/
++int32_t vchi_msg_hold(VCHI_SERVICE_HANDLE_T handle,
++ void **data,
++ uint32_t *msg_size,
++ VCHI_FLAGS_T flags,
++ VCHI_HELD_MSG_T *message_handle)
++{
++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle;
++ VCHIQ_HEADER_T *header;
++
++ WARN_ON((flags != VCHI_FLAGS_NONE) &&
++ (flags != VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE));
++
++ if (flags == VCHI_FLAGS_NONE)
++ if (vchiu_queue_is_empty(&service->queue))
++ return -1;
++
++ header = vchiu_queue_pop(&service->queue);
++
++ *data = header->data;
++ *msg_size = header->size;
++
++ message_handle->service =
++ (struct opaque_vchi_service_t *)service->handle;
++ message_handle->message = header;
++
++ return 0;
++}
++EXPORT_SYMBOL(vchi_msg_hold);
++
++/***********************************************************
++ * Name: vchi_initialise
++ *
++ * Arguments: VCHI_INSTANCE_T *instance_handle
++ *
++ * Description: Initialises the hardware but does not transmit anything
++ * When run as a Host App this will be called twice hence the need
++ * to malloc the state information
++ *
++ * Returns: 0 if successful, failure otherwise
++ *
++ ***********************************************************/
++
++int32_t vchi_initialise(VCHI_INSTANCE_T *instance_handle)
++{
++ VCHIQ_INSTANCE_T instance;
++ VCHIQ_STATUS_T status;
++
++ status = vchiq_initialise(&instance);
++
++ *instance_handle = (VCHI_INSTANCE_T)instance;
++
++ return vchiq_status_to_vchi(status);
++}
++EXPORT_SYMBOL(vchi_initialise);
++
++/***********************************************************
++ * Name: vchi_connect
++ *
++ * Arguments: VCHI_CONNECTION_T **connections
++ * const uint32_t num_connections
++ * VCHI_INSTANCE_T instance_handle)
++ *
++ * Description: Starts the command service on each connection,
++ * causing INIT messages to be pinged back and forth
++ *
++ * Returns: 0 if successful, failure otherwise
++ *
++ ***********************************************************/
++int32_t vchi_connect(VCHI_CONNECTION_T **connections,
++ const uint32_t num_connections,
++ VCHI_INSTANCE_T instance_handle)
++{
++ VCHIQ_INSTANCE_T instance = (VCHIQ_INSTANCE_T)instance_handle;
++
++ (void)connections;
++ (void)num_connections;
++
++ return vchiq_connect(instance);
++}
++EXPORT_SYMBOL(vchi_connect);
++
++
++/***********************************************************
++ * Name: vchi_disconnect
++ *
++ * Arguments: VCHI_INSTANCE_T instance_handle
++ *
++ * Description: Stops the command service on each connection,
++ * causing DE-INIT messages to be pinged back and forth
++ *
++ * Returns: 0 if successful, failure otherwise
++ *
++ ***********************************************************/
++int32_t vchi_disconnect(VCHI_INSTANCE_T instance_handle)
++{
++ VCHIQ_INSTANCE_T instance = (VCHIQ_INSTANCE_T)instance_handle;
++ return vchiq_status_to_vchi(vchiq_shutdown(instance));
++}
++EXPORT_SYMBOL(vchi_disconnect);
++
++
++/***********************************************************
++ * Name: vchi_service_open
++ * Name: vchi_service_create
++ *
++ * Arguments: VCHI_INSTANCE_T *instance_handle
++ * SERVICE_CREATION_T *setup,
++ * VCHI_SERVICE_HANDLE_T *handle
++ *
++ * Description: Routine to open a service
++ *
++ * Returns: int32_t - success == 0
++ *
++ ***********************************************************/
++
++static VCHIQ_STATUS_T shim_callback(VCHIQ_REASON_T reason,
++ VCHIQ_HEADER_T *header, VCHIQ_SERVICE_HANDLE_T handle, void *bulk_user)
++{
++ SHIM_SERVICE_T *service =
++ (SHIM_SERVICE_T *)VCHIQ_GET_SERVICE_USERDATA(handle);
++
++ if (!service->callback)
++ goto release;
++
++ switch (reason) {
++ case VCHIQ_MESSAGE_AVAILABLE:
++ vchiu_queue_push(&service->queue, header);
++
++ service->callback(service->callback_param,
++ VCHI_CALLBACK_MSG_AVAILABLE, NULL);
++
++ goto done;
++ break;
++
++ case VCHIQ_BULK_TRANSMIT_DONE:
++ service->callback(service->callback_param,
++ VCHI_CALLBACK_BULK_SENT, bulk_user);
++ break;
++
++ case VCHIQ_BULK_RECEIVE_DONE:
++ service->callback(service->callback_param,
++ VCHI_CALLBACK_BULK_RECEIVED, bulk_user);
++ break;
++
++ case VCHIQ_SERVICE_CLOSED:
++ service->callback(service->callback_param,
++ VCHI_CALLBACK_SERVICE_CLOSED, NULL);
++ break;
++
++ case VCHIQ_SERVICE_OPENED:
++ /* No equivalent VCHI reason */
++ break;
++
++ case VCHIQ_BULK_TRANSMIT_ABORTED:
++ service->callback(service->callback_param,
++ VCHI_CALLBACK_BULK_TRANSMIT_ABORTED,
++ bulk_user);
++ break;
++
++ case VCHIQ_BULK_RECEIVE_ABORTED:
++ service->callback(service->callback_param,
++ VCHI_CALLBACK_BULK_RECEIVE_ABORTED,
++ bulk_user);
++ break;
++
++ default:
++ WARN(1, "not supported\n");
++ break;
++ }
++
++release:
++ vchiq_release_message(service->handle, header);
++done:
++ return VCHIQ_SUCCESS;
++}
++
++static SHIM_SERVICE_T *service_alloc(VCHIQ_INSTANCE_T instance,
++ SERVICE_CREATION_T *setup)
++{
++ SHIM_SERVICE_T *service = kzalloc(sizeof(SHIM_SERVICE_T), GFP_KERNEL);
++
++ (void)instance;
++
++ if (service) {
++ if (vchiu_queue_init(&service->queue, 64)) {
++ service->callback = setup->callback;
++ service->callback_param = setup->callback_param;
++ } else {
++ kfree(service);
++ service = NULL;
++ }
++ }
++
++ return service;
++}
++
++static void service_free(SHIM_SERVICE_T *service)
++{
++ if (service) {
++ vchiu_queue_delete(&service->queue);
++ kfree(service);
++ }
++}
++
++int32_t vchi_service_open(VCHI_INSTANCE_T instance_handle,
++ SERVICE_CREATION_T *setup,
++ VCHI_SERVICE_HANDLE_T *handle)
++{
++ VCHIQ_INSTANCE_T instance = (VCHIQ_INSTANCE_T)instance_handle;
++ SHIM_SERVICE_T *service = service_alloc(instance, setup);
++
++ *handle = (VCHI_SERVICE_HANDLE_T)service;
++
++ if (service) {
++ VCHIQ_SERVICE_PARAMS_T params;
++ VCHIQ_STATUS_T status;
++
++ memset(&params, 0, sizeof(params));
++ params.fourcc = setup->service_id;
++ params.callback = shim_callback;
++ params.userdata = service;
++ params.version = setup->version.version;
++ params.version_min = setup->version.version_min;
++
++ status = vchiq_open_service(instance, &params,
++ &service->handle);
++ if (status != VCHIQ_SUCCESS) {
++ service_free(service);
++ service = NULL;
++ *handle = NULL;
++ }
++ }
++
++ return (service != NULL) ? 0 : -1;
++}
++EXPORT_SYMBOL(vchi_service_open);
++
++int32_t vchi_service_create(VCHI_INSTANCE_T instance_handle,
++ SERVICE_CREATION_T *setup,
++ VCHI_SERVICE_HANDLE_T *handle)
++{
++ VCHIQ_INSTANCE_T instance = (VCHIQ_INSTANCE_T)instance_handle;
++ SHIM_SERVICE_T *service = service_alloc(instance, setup);
++
++ *handle = (VCHI_SERVICE_HANDLE_T)service;
++
++ if (service) {
++ VCHIQ_SERVICE_PARAMS_T params;
++ VCHIQ_STATUS_T status;
++
++ memset(&params, 0, sizeof(params));
++ params.fourcc = setup->service_id;
++ params.callback = shim_callback;
++ params.userdata = service;
++ params.version = setup->version.version;
++ params.version_min = setup->version.version_min;
++ status = vchiq_add_service(instance, &params, &service->handle);
++
++ if (status != VCHIQ_SUCCESS) {
++ service_free(service);
++ service = NULL;
++ *handle = NULL;
++ }
++ }
++
++ return (service != NULL) ? 0 : -1;
++}
++EXPORT_SYMBOL(vchi_service_create);
++
++int32_t vchi_service_close(const VCHI_SERVICE_HANDLE_T handle)
++{
++ int32_t ret = -1;
++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle;
++ if (service) {
++ VCHIQ_STATUS_T status = vchiq_close_service(service->handle);
++ if (status == VCHIQ_SUCCESS) {
++ service_free(service);
++ service = NULL;
++ }
++
++ ret = vchiq_status_to_vchi(status);
++ }
++ return ret;
++}
++EXPORT_SYMBOL(vchi_service_close);
++
++int32_t vchi_service_destroy(const VCHI_SERVICE_HANDLE_T handle)
++{
++ int32_t ret = -1;
++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle;
++ if (service) {
++ VCHIQ_STATUS_T status = vchiq_remove_service(service->handle);
++ if (status == VCHIQ_SUCCESS) {
++ service_free(service);
++ service = NULL;
++ }
++
++ ret = vchiq_status_to_vchi(status);
++ }
++ return ret;
++}
++EXPORT_SYMBOL(vchi_service_destroy);
++
++int32_t vchi_service_set_option(const VCHI_SERVICE_HANDLE_T handle,
++ VCHI_SERVICE_OPTION_T option,
++ int value)
++{
++ int32_t ret = -1;
++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle;
++ VCHIQ_SERVICE_OPTION_T vchiq_option;
++ switch (option) {
++ case VCHI_SERVICE_OPTION_TRACE:
++ vchiq_option = VCHIQ_SERVICE_OPTION_TRACE;
++ break;
++ case VCHI_SERVICE_OPTION_SYNCHRONOUS:
++ vchiq_option = VCHIQ_SERVICE_OPTION_SYNCHRONOUS;
++ break;
++ default:
++ service = NULL;
++ break;
++ }
++ if (service) {
++ VCHIQ_STATUS_T status =
++ vchiq_set_service_option(service->handle,
++ vchiq_option,
++ value);
++
++ ret = vchiq_status_to_vchi(status);
++ }
++ return ret;
++}
++EXPORT_SYMBOL(vchi_service_set_option);
++
++int32_t vchi_get_peer_version( const VCHI_SERVICE_HANDLE_T handle, short *peer_version )
++{
++ int32_t ret = -1;
++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle;
++ if(service)
++ {
++ VCHIQ_STATUS_T status = vchiq_get_peer_version(service->handle, peer_version);
++ ret = vchiq_status_to_vchi( status );
++ }
++ return ret;
++}
++EXPORT_SYMBOL(vchi_get_peer_version);
++
++/* ----------------------------------------------------------------------
++ * read a uint32_t from buffer.
++ * network format is defined to be little endian
++ * -------------------------------------------------------------------- */
++uint32_t
++vchi_readbuf_uint32(const void *_ptr)
++{
++ const unsigned char *ptr = _ptr;
++ return ptr[0] | (ptr[1] << 8) | (ptr[2] << 16) | (ptr[3] << 24);
++}
++
++/* ----------------------------------------------------------------------
++ * write a uint32_t to buffer.
++ * network format is defined to be little endian
++ * -------------------------------------------------------------------- */
++void
++vchi_writebuf_uint32(void *_ptr, uint32_t value)
++{
++ unsigned char *ptr = _ptr;
++ ptr[0] = (unsigned char)((value >> 0) & 0xFF);
++ ptr[1] = (unsigned char)((value >> 8) & 0xFF);
++ ptr[2] = (unsigned char)((value >> 16) & 0xFF);
++ ptr[3] = (unsigned char)((value >> 24) & 0xFF);
++}
++
++/* ----------------------------------------------------------------------
++ * read a uint16_t from buffer.
++ * network format is defined to be little endian
++ * -------------------------------------------------------------------- */
++uint16_t
++vchi_readbuf_uint16(const void *_ptr)
++{
++ const unsigned char *ptr = _ptr;
++ return ptr[0] | (ptr[1] << 8);
++}
++
++/* ----------------------------------------------------------------------
++ * write a uint16_t into the buffer.
++ * network format is defined to be little endian
++ * -------------------------------------------------------------------- */
++void
++vchi_writebuf_uint16(void *_ptr, uint16_t value)
++{
++ unsigned char *ptr = _ptr;
++ ptr[0] = (value >> 0) & 0xFF;
++ ptr[1] = (value >> 8) & 0xFF;
++}
++
++/***********************************************************
++ * Name: vchi_service_use
++ *
++ * Arguments: const VCHI_SERVICE_HANDLE_T handle
++ *
++ * Description: Routine to increment refcount on a service
++ *
++ * Returns: void
++ *
++ ***********************************************************/
++int32_t vchi_service_use(const VCHI_SERVICE_HANDLE_T handle)
++{
++ int32_t ret = -1;
++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle;
++ if (service)
++ ret = vchiq_status_to_vchi(vchiq_use_service(service->handle));
++ return ret;
++}
++EXPORT_SYMBOL(vchi_service_use);
++
++/***********************************************************
++ * Name: vchi_service_release
++ *
++ * Arguments: const VCHI_SERVICE_HANDLE_T handle
++ *
++ * Description: Routine to decrement refcount on a service
++ *
++ * Returns: void
++ *
++ ***********************************************************/
++int32_t vchi_service_release(const VCHI_SERVICE_HANDLE_T handle)
++{
++ int32_t ret = -1;
++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle;
++ if (service)
++ ret = vchiq_status_to_vchi(
++ vchiq_release_service(service->handle));
++ return ret;
++}
++EXPORT_SYMBOL(vchi_service_release);
+diff -Nur linux-4.1.3/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.c linux-xbian-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.c
+--- linux-4.1.3/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.c 2015-07-28 01:20:58.285725306 +0200
+@@ -0,0 +1,152 @@
++/**
++ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ * 1. Redistributions of source code must retain the above copyright
++ * notice, this list of conditions, and the following disclaimer,
++ * without modification.
++ * 2. Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * 3. The names of the above-listed copyright holders may not be used
++ * to endorse or promote products derived from this software without
++ * specific prior written permission.
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") version 2, as published by the Free
++ * Software Foundation.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#include "vchiq_util.h"
++#include "vchiq_killable.h"
++
++static inline int is_pow2(int i)
++{
++ return i && !(i & (i - 1));
++}
++
++int vchiu_queue_init(VCHIU_QUEUE_T *queue, int size)
++{
++ WARN_ON(!is_pow2(size));
++
++ queue->size = size;
++ queue->read = 0;
++ queue->write = 0;
++
++ sema_init(&queue->pop, 0);
++ sema_init(&queue->push, 0);
++
++ queue->storage = kzalloc(size * sizeof(VCHIQ_HEADER_T *), GFP_KERNEL);
++ if (queue->storage == NULL) {
++ vchiu_queue_delete(queue);
++ return 0;
++ }
++ return 1;
++}
++
++void vchiu_queue_delete(VCHIU_QUEUE_T *queue)
++{
++ if (queue->storage != NULL)
++ kfree(queue->storage);
++}
++
++int vchiu_queue_is_empty(VCHIU_QUEUE_T *queue)
++{
++ return queue->read == queue->write;
++}
++
++int vchiu_queue_is_full(VCHIU_QUEUE_T *queue)
++{
++ return queue->write == queue->read + queue->size;
++}
++
++void vchiu_queue_push(VCHIU_QUEUE_T *queue, VCHIQ_HEADER_T *header)
++{
++ while (queue->write == queue->read + queue->size) {
++ if (down_interruptible(&queue->pop) != 0) {
++ flush_signals(current);
++ }
++ }
++
++ /*
++ * Write to queue->storage must be visible after read from
++ * queue->read
++ */
++ smp_mb();
++
++ queue->storage[queue->write & (queue->size - 1)] = header;
++
++ /*
++ * Write to queue->storage must be visible before write to
++ * queue->write
++ */
++ smp_wmb();
++
++ queue->write++;
++
++ up(&queue->push);
++}
++
++VCHIQ_HEADER_T *vchiu_queue_peek(VCHIU_QUEUE_T *queue)
++{
++ while (queue->write == queue->read) {
++ if (down_interruptible(&queue->push) != 0) {
++ flush_signals(current);
++ }
++ }
++
++ up(&queue->push); // We haven't removed anything from the queue.
++
++ /*
++ * Read from queue->storage must be visible after read from
++ * queue->write
++ */
++ smp_rmb();
++
++ return queue->storage[queue->read & (queue->size - 1)];
++}
++
++VCHIQ_HEADER_T *vchiu_queue_pop(VCHIU_QUEUE_T *queue)
++{
++ VCHIQ_HEADER_T *header;
++
++ while (queue->write == queue->read) {
++ if (down_interruptible(&queue->push) != 0) {
++ flush_signals(current);
++ }
++ }
++
++ /*
++ * Read from queue->storage must be visible after read from
++ * queue->write
++ */
++ smp_rmb();
++
++ header = queue->storage[queue->read & (queue->size - 1)];
++
++ /*
++ * Read from queue->storage must be visible before write to
++ * queue->read
++ */
++ smp_mb();
++
++ queue->read++;
++
++ up(&queue->pop);
++
++ return header;
++}
+diff -Nur linux-4.1.3/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.h linux-xbian-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.h
+--- linux-4.1.3/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.h 2015-07-28 01:20:58.285725306 +0200
+@@ -0,0 +1,81 @@
++/**
++ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ * 1. Redistributions of source code must retain the above copyright
++ * notice, this list of conditions, and the following disclaimer,
++ * without modification.
++ * 2. Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * 3. The names of the above-listed copyright holders may not be used
++ * to endorse or promote products derived from this software without
++ * specific prior written permission.
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") version 2, as published by the Free
++ * Software Foundation.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#ifndef VCHIQ_UTIL_H
++#define VCHIQ_UTIL_H
++
++#include <linux/types.h>
++#include <linux/semaphore.h>
++#include <linux/mutex.h>
++#include <linux/bitops.h>
++#include <linux/kthread.h>
++#include <linux/wait.h>
++#include <linux/vmalloc.h>
++#include <linux/jiffies.h>
++#include <linux/delay.h>
++#include <linux/string.h>
++#include <linux/types.h>
++#include <linux/interrupt.h>
++#include <linux/random.h>
++#include <linux/sched.h>
++#include <linux/ctype.h>
++#include <linux/uaccess.h>
++#include <linux/time.h> /* for time_t */
++#include <linux/slab.h>
++#include <linux/vmalloc.h>
++
++#include "vchiq_if.h"
++
++typedef struct {
++ int size;
++ int read;
++ int write;
++
++ struct semaphore pop;
++ struct semaphore push;
++
++ VCHIQ_HEADER_T **storage;
++} VCHIU_QUEUE_T;
++
++extern int vchiu_queue_init(VCHIU_QUEUE_T *queue, int size);
++extern void vchiu_queue_delete(VCHIU_QUEUE_T *queue);
++
++extern int vchiu_queue_is_empty(VCHIU_QUEUE_T *queue);
++extern int vchiu_queue_is_full(VCHIU_QUEUE_T *queue);
++
++extern void vchiu_queue_push(VCHIU_QUEUE_T *queue, VCHIQ_HEADER_T *header);
++
++extern VCHIQ_HEADER_T *vchiu_queue_peek(VCHIU_QUEUE_T *queue);
++extern VCHIQ_HEADER_T *vchiu_queue_pop(VCHIU_QUEUE_T *queue);
++
++#endif
+diff -Nur linux-4.1.3/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_version.c linux-xbian-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_version.c
+--- linux-4.1.3/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_version.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_version.c 2015-07-28 01:20:58.285725306 +0200
+@@ -0,0 +1,59 @@
++/**
++ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ * 1. Redistributions of source code must retain the above copyright
++ * notice, this list of conditions, and the following disclaimer,
++ * without modification.
++ * 2. Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * 3. The names of the above-listed copyright holders may not be used
++ * to endorse or promote products derived from this software without
++ * specific prior written permission.
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") version 2, as published by the Free
++ * Software Foundation.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++#include "vchiq_build_info.h"
++#include <linux/broadcom/vc_debug_sym.h>
++
++VC_DEBUG_DECLARE_STRING_VAR( vchiq_build_hostname, "dc4-arm-01" );
++VC_DEBUG_DECLARE_STRING_VAR( vchiq_build_version, "9245b4c35b99b3870e1f7dc598c5692b3c66a6f0 (tainted)" );
++VC_DEBUG_DECLARE_STRING_VAR( vchiq_build_time, __TIME__ );
++VC_DEBUG_DECLARE_STRING_VAR( vchiq_build_date, __DATE__ );
++
++const char *vchiq_get_build_hostname( void )
++{
++ return vchiq_build_hostname;
++}
++
++const char *vchiq_get_build_version( void )
++{
++ return vchiq_build_version;
++}
++
++const char *vchiq_get_build_date( void )
++{
++ return vchiq_build_date;
++}
++
++const char *vchiq_get_build_time( void )
++{
++ return vchiq_build_time;
++}
+diff -Nur linux-4.1.3/drivers/misc/vc04_services/Kconfig linux-xbian-rpi/drivers/misc/vc04_services/Kconfig
+--- linux-4.1.3/drivers/misc/vc04_services/Kconfig 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/misc/vc04_services/Kconfig 2015-07-28 01:20:58.281739526 +0200
+@@ -0,0 +1,9 @@
++config BCM2708_VCHIQ
++ tristate "Videocore VCHIQ"
++ depends on (MACH_BCM2708 || MACH_BCM2709 || ARCH_BCM2835) && BCM2708_MBOX
++ default y
++ help
++ Kernel to VideoCore communication interface for the
++ BCM2708 family of products.
++ Defaults to Y when the Broadcom Videocore services
++ are included in the build, N otherwise.
+diff -Nur linux-4.1.3/drivers/misc/vc04_services/Makefile linux-xbian-rpi/drivers/misc/vc04_services/Makefile
+--- linux-4.1.3/drivers/misc/vc04_services/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/misc/vc04_services/Makefile 2015-07-28 01:20:58.281739526 +0200
+@@ -0,0 +1,14 @@
++obj-$(CONFIG_BCM2708_VCHIQ) += vchiq.o
++
++vchiq-objs := \
++ interface/vchiq_arm/vchiq_core.o \
++ interface/vchiq_arm/vchiq_arm.o \
++ interface/vchiq_arm/vchiq_kern_lib.o \
++ interface/vchiq_arm/vchiq_2835_arm.o \
++ interface/vchiq_arm/vchiq_debugfs.o \
++ interface/vchiq_arm/vchiq_shim.o \
++ interface/vchiq_arm/vchiq_util.o \
++ interface/vchiq_arm/vchiq_connected.o \
++
++ccflags-y += -DVCOS_VERIFY_BKPTS=1 -Idrivers/misc/vc04_services -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000
++
+diff -Nur linux-4.1.3/drivers/mmc/card/block.c linux-xbian-rpi/drivers/mmc/card/block.c
+--- linux-4.1.3/drivers/mmc/card/block.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/mmc/card/block.c 2015-07-28 01:20:58.285725306 +0200
+@@ -1413,6 +1413,7 @@
+ brq->data.blocks = card->host->ops->multi_io_quirk(card,
+ (rq_data_dir(req) == READ) ?
+ MMC_DATA_READ : MMC_DATA_WRITE,
++ blk_rq_pos(req),
+ brq->data.blocks);
+ }
+
+diff -Nur linux-4.1.3/drivers/mmc/core/quirks.c linux-xbian-rpi/drivers/mmc/core/quirks.c
+--- linux-4.1.3/drivers/mmc/core/quirks.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/mmc/core/quirks.c 2015-07-28 01:20:58.289711085 +0200
+@@ -71,6 +71,7 @@
+
+ void mmc_fixup_device(struct mmc_card *card, const struct mmc_fixup *table)
+ {
++ extern unsigned mmc_debug;
+ const struct mmc_fixup *f;
+ u64 rev = cid_rev_card(card);
+
+@@ -95,5 +96,10 @@
+ f->vendor_fixup(card, f->data);
+ }
+ }
++ /* SDHCI on BCM2708 - bug causes a certain sequence of CMD23 operations to fail.
++ * Disable this flag for all cards (fall-back to CMD25/CMD18 multi-block transfers).
++ */
++ if (mmc_debug & (1<<13))
++ card->quirks |= MMC_QUIRK_BLK_NO_CMD23;
+ }
+ EXPORT_SYMBOL(mmc_fixup_device);
+diff -Nur linux-4.1.3/drivers/mmc/host/bcm2835-mmc.c linux-xbian-rpi/drivers/mmc/host/bcm2835-mmc.c
+--- linux-4.1.3/drivers/mmc/host/bcm2835-mmc.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/mmc/host/bcm2835-mmc.c 2015-07-28 01:20:58.289711085 +0200
+@@ -0,0 +1,1558 @@
++/*
++ * BCM2835 MMC host driver.
++ *
++ * Author: Gellert Weisz <gellert@raspberrypi.org>
++ * Copyright 2014
++ *
++ * Based on
++ * sdhci-bcm2708.c by Broadcom
++ * sdhci-bcm2835.c by Stephen Warren and Oleksandr Tymoshenko
++ * sdhci.c and sdhci-pci.c by Pierre Ossman
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms and conditions of the GNU General Public License,
++ * version 2, as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/delay.h>
++#include <linux/module.h>
++#include <linux/io.h>
++#include <linux/mmc/mmc.h>
++#include <linux/mmc/host.h>
++#include <linux/mmc/sd.h>
++#include <linux/scatterlist.h>
++#include <linux/of_address.h>
++#include <linux/of_irq.h>
++#include <linux/clk.h>
++#include <linux/platform_device.h>
++#include <linux/err.h>
++#include <linux/blkdev.h>
++#include <linux/dmaengine.h>
++#include <linux/dma-mapping.h>
++#include <linux/of_dma.h>
++
++#include "sdhci.h"
++
++
++#define DRIVER_NAME "mmc-bcm2835"
++
++#define DBG(f, x...) \
++pr_debug(DRIVER_NAME " [%s()]: " f, __func__, ## x)
++
++#ifndef CONFIG_MMC_BCM2835_DMA
++ #define FORCE_PIO
++#endif
++
++
++/* the inclusive limit in bytes under which PIO will be used instead of DMA */
++#ifdef CONFIG_MMC_BCM2835_PIO_DMA_BARRIER
++#define PIO_DMA_BARRIER CONFIG_MMC_BCM2835_PIO_DMA_BARRIER
++#else
++#define PIO_DMA_BARRIER 00
++#endif
++
++#define MIN_FREQ 400000
++#define TIMEOUT_VAL 0xE
++#define BCM2835_SDHCI_WRITE_DELAY(f) (((2 * 1000000) / f) + 1)
++
++#ifndef BCM2708_PERI_BASE
++ #define BCM2708_PERI_BASE 0x20000000
++#endif
++
++/* FIXME: Needs IOMMU support */
++#define BCM2835_VCMMU_SHIFT (0x7E000000 - BCM2708_PERI_BASE)
++
++
++unsigned mmc_debug;
++unsigned mmc_debug2;
++
++struct bcm2835_host {
++ spinlock_t lock;
++
++ void __iomem *ioaddr;
++ u32 phys_addr;
++
++ struct mmc_host *mmc;
++
++ u32 timeout;
++
++ int clock; /* Current clock speed */
++ u8 pwr; /* Current voltage */
++
++ unsigned int max_clk; /* Max possible freq */
++ unsigned int timeout_clk; /* Timeout freq (KHz) */
++ unsigned int clk_mul; /* Clock Muliplier value */
++
++ struct tasklet_struct finish_tasklet; /* Tasklet structures */
++
++ struct timer_list timer; /* Timer for timeouts */
++
++ struct sg_mapping_iter sg_miter; /* SG state for PIO */
++ unsigned int blocks; /* remaining PIO blocks */
++
++ int irq; /* Device IRQ */
++
++
++ u32 ier; /* cached registers */
++
++ struct mmc_request *mrq; /* Current request */
++ struct mmc_command *cmd; /* Current command */
++ struct mmc_data *data; /* Current data request */
++ unsigned int data_early:1; /* Data finished before cmd */
++
++ wait_queue_head_t buf_ready_int; /* Waitqueue for Buffer Read Ready interrupt */
++
++ u32 thread_isr;
++
++ u32 shadow;
++
++ /*DMA part*/
++ struct dma_chan *dma_chan_rx; /* DMA channel for reads */
++ struct dma_chan *dma_chan_tx; /* DMA channel for writes */
++ struct dma_async_tx_descriptor *tx_desc; /* descriptor */
++
++ bool have_dma;
++ bool use_dma;
++ /*end of DMA part*/
++
++ int max_delay; /* maximum length of time spent waiting */
++
++ int flags; /* Host attributes */
++#define SDHCI_REQ_USE_DMA (1<<2) /* Use DMA for this req. */
++#define SDHCI_DEVICE_DEAD (1<<3) /* Device unresponsive */
++#define SDHCI_AUTO_CMD12 (1<<6) /* Auto CMD12 support */
++#define SDHCI_AUTO_CMD23 (1<<7) /* Auto CMD23 support */
++#define SDHCI_SDIO_IRQ_ENABLED (1<<9) /* SDIO irq enabled */
++
++ u32 overclock_50; /* frequency to use when 50MHz is requested (in MHz) */
++ u32 max_overclock; /* Highest reported */
++};
++
++
++static inline void bcm2835_mmc_writel(struct bcm2835_host *host, u32 val, int reg, int from)
++{
++ unsigned delay;
++ lockdep_assert_held_once(&host->lock);
++ writel(val, host->ioaddr + reg);
++ udelay(BCM2835_SDHCI_WRITE_DELAY(max(host->clock, MIN_FREQ)));
++
++ delay = ((mmc_debug >> 16) & 0xf) << ((mmc_debug >> 20) & 0xf);
++ if (delay && !((1<<from) & mmc_debug2))
++ udelay(delay);
++}
++
++static inline void mmc_raw_writel(struct bcm2835_host *host, u32 val, int reg)
++{
++ unsigned delay;
++ lockdep_assert_held_once(&host->lock);
++ writel(val, host->ioaddr + reg);
++
++ delay = ((mmc_debug >> 24) & 0xf) << ((mmc_debug >> 28) & 0xf);
++ if (delay)
++ udelay(delay);
++}
++
++static inline u32 bcm2835_mmc_readl(struct bcm2835_host *host, int reg)
++{
++ lockdep_assert_held_once(&host->lock);
++ return readl(host->ioaddr + reg);
++}
++
++static inline void bcm2835_mmc_writew(struct bcm2835_host *host, u16 val, int reg)
++{
++ u32 oldval = (reg == SDHCI_COMMAND) ? host->shadow :
++ bcm2835_mmc_readl(host, reg & ~3);
++ u32 word_num = (reg >> 1) & 1;
++ u32 word_shift = word_num * 16;
++ u32 mask = 0xffff << word_shift;
++ u32 newval = (oldval & ~mask) | (val << word_shift);
++
++ if (reg == SDHCI_TRANSFER_MODE)
++ host->shadow = newval;
++ else
++ bcm2835_mmc_writel(host, newval, reg & ~3, 0);
++
++}
++
++static inline void bcm2835_mmc_writeb(struct bcm2835_host *host, u8 val, int reg)
++{
++ u32 oldval = bcm2835_mmc_readl(host, reg & ~3);
++ u32 byte_num = reg & 3;
++ u32 byte_shift = byte_num * 8;
++ u32 mask = 0xff << byte_shift;
++ u32 newval = (oldval & ~mask) | (val << byte_shift);
++
++ bcm2835_mmc_writel(host, newval, reg & ~3, 1);
++}
++
++
++static inline u16 bcm2835_mmc_readw(struct bcm2835_host *host, int reg)
++{
++ u32 val = bcm2835_mmc_readl(host, (reg & ~3));
++ u32 word_num = (reg >> 1) & 1;
++ u32 word_shift = word_num * 16;
++ u32 word = (val >> word_shift) & 0xffff;
++
++ return word;
++}
++
++static inline u8 bcm2835_mmc_readb(struct bcm2835_host *host, int reg)
++{
++ u32 val = bcm2835_mmc_readl(host, (reg & ~3));
++ u32 byte_num = reg & 3;
++ u32 byte_shift = byte_num * 8;
++ u32 byte = (val >> byte_shift) & 0xff;
++
++ return byte;
++}
++
++static void bcm2835_mmc_unsignal_irqs(struct bcm2835_host *host, u32 clear)
++{
++ u32 ier;
++
++ ier = bcm2835_mmc_readl(host, SDHCI_SIGNAL_ENABLE);
++ ier &= ~clear;
++ /* change which requests generate IRQs - makes no difference to
++ the content of SDHCI_INT_STATUS, or the need to acknowledge IRQs */
++ bcm2835_mmc_writel(host, ier, SDHCI_SIGNAL_ENABLE, 2);
++}
++
++
++static void bcm2835_mmc_dumpregs(struct bcm2835_host *host)
++{
++ pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
++ mmc_hostname(host->mmc));
++
++ pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
++ bcm2835_mmc_readl(host, SDHCI_DMA_ADDRESS),
++ bcm2835_mmc_readw(host, SDHCI_HOST_VERSION));
++ pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
++ bcm2835_mmc_readw(host, SDHCI_BLOCK_SIZE),
++ bcm2835_mmc_readw(host, SDHCI_BLOCK_COUNT));
++ pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
++ bcm2835_mmc_readl(host, SDHCI_ARGUMENT),
++ bcm2835_mmc_readw(host, SDHCI_TRANSFER_MODE));
++ pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
++ bcm2835_mmc_readl(host, SDHCI_PRESENT_STATE),
++ bcm2835_mmc_readb(host, SDHCI_HOST_CONTROL));
++ pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
++ bcm2835_mmc_readb(host, SDHCI_POWER_CONTROL),
++ bcm2835_mmc_readb(host, SDHCI_BLOCK_GAP_CONTROL));
++ pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
++ bcm2835_mmc_readb(host, SDHCI_WAKE_UP_CONTROL),
++ bcm2835_mmc_readw(host, SDHCI_CLOCK_CONTROL));
++ pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
++ bcm2835_mmc_readb(host, SDHCI_TIMEOUT_CONTROL),
++ bcm2835_mmc_readl(host, SDHCI_INT_STATUS));
++ pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
++ bcm2835_mmc_readl(host, SDHCI_INT_ENABLE),
++ bcm2835_mmc_readl(host, SDHCI_SIGNAL_ENABLE));
++ pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
++ bcm2835_mmc_readw(host, SDHCI_ACMD12_ERR),
++ bcm2835_mmc_readw(host, SDHCI_SLOT_INT_STATUS));
++ pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
++ bcm2835_mmc_readl(host, SDHCI_CAPABILITIES),
++ bcm2835_mmc_readl(host, SDHCI_CAPABILITIES_1));
++ pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
++ bcm2835_mmc_readw(host, SDHCI_COMMAND),
++ bcm2835_mmc_readl(host, SDHCI_MAX_CURRENT));
++ pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
++ bcm2835_mmc_readw(host, SDHCI_HOST_CONTROL2));
++
++ pr_debug(DRIVER_NAME ": ===========================================\n");
++}
++
++
++static void bcm2835_mmc_reset(struct bcm2835_host *host, u8 mask)
++{
++ unsigned long timeout;
++ unsigned long flags;
++
++ spin_lock_irqsave(&host->lock, flags);
++ bcm2835_mmc_writeb(host, mask, SDHCI_SOFTWARE_RESET);
++
++ if (mask & SDHCI_RESET_ALL)
++ host->clock = 0;
++
++ /* Wait max 100 ms */
++ timeout = 100;
++
++ /* hw clears the bit when it's done */
++ while (bcm2835_mmc_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
++ if (timeout == 0) {
++ pr_err("%s: Reset 0x%x never completed.\n",
++ mmc_hostname(host->mmc), (int)mask);
++ bcm2835_mmc_dumpregs(host);
++ return;
++ }
++ timeout--;
++ spin_unlock_irqrestore(&host->lock, flags);
++ mdelay(1);
++ spin_lock_irqsave(&host->lock, flags);
++ }
++
++ if (100-timeout > 10 && 100-timeout > host->max_delay) {
++ host->max_delay = 100-timeout;
++ pr_warning("Warning: MMC controller hung for %d ms\n", host->max_delay);
++ }
++ spin_unlock_irqrestore(&host->lock, flags);
++}
++
++static void bcm2835_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
++
++static void bcm2835_mmc_init(struct bcm2835_host *host, int soft)
++{
++ unsigned long flags;
++ if (soft)
++ bcm2835_mmc_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
++ else
++ bcm2835_mmc_reset(host, SDHCI_RESET_ALL);
++
++ host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
++ SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
++ SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
++ SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
++ SDHCI_INT_RESPONSE;
++
++ spin_lock_irqsave(&host->lock, flags);
++ bcm2835_mmc_writel(host, host->ier, SDHCI_INT_ENABLE, 3);
++ bcm2835_mmc_writel(host, host->ier, SDHCI_SIGNAL_ENABLE, 3);
++ spin_unlock_irqrestore(&host->lock, flags);
++
++ if (soft) {
++ /* force clock reconfiguration */
++ host->clock = 0;
++ bcm2835_mmc_set_ios(host->mmc, &host->mmc->ios);
++ }
++}
++
++
++
++static void bcm2835_mmc_finish_data(struct bcm2835_host *host);
++
++static void bcm2835_mmc_dma_complete(void *param)
++{
++ struct bcm2835_host *host = param;
++ struct dma_chan *dma_chan;
++ unsigned long flags;
++ u32 dir_data;
++
++ spin_lock_irqsave(&host->lock, flags);
++
++ if (host->data && !(host->data->flags & MMC_DATA_WRITE)) {
++ /* otherwise handled in SDHCI IRQ */
++ dma_chan = host->dma_chan_rx;
++ dir_data = DMA_FROM_DEVICE;
++
++ dma_unmap_sg(dma_chan->device->dev,
++ host->data->sg, host->data->sg_len,
++ dir_data);
++
++ bcm2835_mmc_finish_data(host);
++ }
++
++ spin_unlock_irqrestore(&host->lock, flags);
++}
++
++static void bcm2835_bcm2835_mmc_read_block_pio(struct bcm2835_host *host)
++{
++ unsigned long flags;
++ size_t blksize, len, chunk;
++
++ u32 uninitialized_var(scratch);
++ u8 *buf;
++
++ blksize = host->data->blksz;
++ chunk = 0;
++
++ local_irq_save(flags);
++
++ while (blksize) {
++ if (!sg_miter_next(&host->sg_miter))
++ BUG();
++
++ len = min(host->sg_miter.length, blksize);
++
++ blksize -= len;
++ host->sg_miter.consumed = len;
++
++ buf = host->sg_miter.addr;
++
++ while (len) {
++ if (chunk == 0) {
++ scratch = bcm2835_mmc_readl(host, SDHCI_BUFFER);
++ chunk = 4;
++ }
++
++ *buf = scratch & 0xFF;
++
++ buf++;
++ scratch >>= 8;
++ chunk--;
++ len--;
++ }
++ }
++
++ sg_miter_stop(&host->sg_miter);
++
++ local_irq_restore(flags);
++}
++
++static void bcm2835_bcm2835_mmc_write_block_pio(struct bcm2835_host *host)
++{
++ unsigned long flags;
++ size_t blksize, len, chunk;
++ u32 scratch;
++ u8 *buf;
++
++ blksize = host->data->blksz;
++ chunk = 0;
++ chunk = 0;
++ scratch = 0;
++
++ local_irq_save(flags);
++
++ while (blksize) {
++ if (!sg_miter_next(&host->sg_miter))
++ BUG();
++
++ len = min(host->sg_miter.length, blksize);
++
++ blksize -= len;
++ host->sg_miter.consumed = len;
++
++ buf = host->sg_miter.addr;
++
++ while (len) {
++ scratch |= (u32)*buf << (chunk * 8);
++
++ buf++;
++ chunk++;
++ len--;
++
++ if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
++ mmc_raw_writel(host, scratch, SDHCI_BUFFER);
++ chunk = 0;
++ scratch = 0;
++ }
++ }
++ }
++
++ sg_miter_stop(&host->sg_miter);
++
++ local_irq_restore(flags);
++}
++
++
++static void bcm2835_mmc_transfer_pio(struct bcm2835_host *host)
++{
++ u32 mask;
++
++ BUG_ON(!host->data);
++
++ if (host->blocks == 0)
++ return;
++
++ if (host->data->flags & MMC_DATA_READ)
++ mask = SDHCI_DATA_AVAILABLE;
++ else
++ mask = SDHCI_SPACE_AVAILABLE;
++
++ while (bcm2835_mmc_readl(host, SDHCI_PRESENT_STATE) & mask) {
++
++ if (host->data->flags & MMC_DATA_READ)
++ bcm2835_bcm2835_mmc_read_block_pio(host);
++ else
++ bcm2835_bcm2835_mmc_write_block_pio(host);
++
++ host->blocks--;
++
++ /* QUIRK used in sdhci.c removes the 'if' */
++ /* but it seems this is unnecessary */
++ if (host->blocks == 0)
++ break;
++
++
++ }
++}
++
++
++static void bcm2835_mmc_transfer_dma(struct bcm2835_host *host)
++{
++ u32 len, dir_data, dir_slave;
++ struct dma_async_tx_descriptor *desc = NULL;
++ struct dma_chan *dma_chan;
++
++
++ WARN_ON(!host->data);
++
++ if (!host->data)
++ return;
++
++ if (host->blocks == 0)
++ return;
++
++ if (host->data->flags & MMC_DATA_READ) {
++ dma_chan = host->dma_chan_rx;
++ dir_data = DMA_FROM_DEVICE;
++ dir_slave = DMA_DEV_TO_MEM;
++ } else {
++ dma_chan = host->dma_chan_tx;
++ dir_data = DMA_TO_DEVICE;
++ dir_slave = DMA_MEM_TO_DEV;
++ }
++
++ BUG_ON(!dma_chan->device);
++ BUG_ON(!dma_chan->device->dev);
++ BUG_ON(!host->data->sg);
++
++ len = dma_map_sg(dma_chan->device->dev, host->data->sg,
++ host->data->sg_len, dir_data);
++ if (len > 0) {
++ desc = dmaengine_prep_slave_sg(dma_chan, host->data->sg,
++ len, dir_slave,
++ DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
++ } else {
++ dev_err(mmc_dev(host->mmc), "dma_map_sg returned zero length\n");
++ }
++ if (desc) {
++ unsigned long flags;
++ spin_lock_irqsave(&host->lock, flags);
++ bcm2835_mmc_unsignal_irqs(host, SDHCI_INT_DATA_AVAIL |
++ SDHCI_INT_SPACE_AVAIL);
++ host->tx_desc = desc;
++ desc->callback = bcm2835_mmc_dma_complete;
++ desc->callback_param = host;
++ spin_unlock_irqrestore(&host->lock, flags);
++ dmaengine_submit(desc);
++ dma_async_issue_pending(dma_chan);
++ }
++
++}
++
++
++
++static void bcm2835_mmc_set_transfer_irqs(struct bcm2835_host *host)
++{
++ u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
++ u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
++
++ if (host->use_dma)
++ host->ier = (host->ier & ~pio_irqs) | dma_irqs;
++ else
++ host->ier = (host->ier & ~dma_irqs) | pio_irqs;
++
++ bcm2835_mmc_writel(host, host->ier, SDHCI_INT_ENABLE, 4);
++ bcm2835_mmc_writel(host, host->ier, SDHCI_SIGNAL_ENABLE, 4);
++}
++
++
++static void bcm2835_mmc_prepare_data(struct bcm2835_host *host, struct mmc_command *cmd)
++{
++ u8 count;
++ struct mmc_data *data = cmd->data;
++
++ WARN_ON(host->data);
++
++ if (data || (cmd->flags & MMC_RSP_BUSY)) {
++ count = TIMEOUT_VAL;
++ bcm2835_mmc_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
++ }
++
++ if (!data)
++ return;
++
++ /* Sanity checks */
++ BUG_ON(data->blksz * data->blocks > 524288);
++ BUG_ON(data->blksz > host->mmc->max_blk_size);
++ BUG_ON(data->blocks > 65535);
++
++ host->data = data;
++ host->data_early = 0;
++ host->data->bytes_xfered = 0;
++
++
++ if (!(host->flags & SDHCI_REQ_USE_DMA)) {
++ int flags;
++
++ flags = SG_MITER_ATOMIC;
++ if (host->data->flags & MMC_DATA_READ)
++ flags |= SG_MITER_TO_SG;
++ else
++ flags |= SG_MITER_FROM_SG;
++ sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
++ host->blocks = data->blocks;
++ }
++
++ host->use_dma = host->have_dma && data->blocks > PIO_DMA_BARRIER;
++
++ bcm2835_mmc_set_transfer_irqs(host);
++
++ /* Set the DMA boundary value and block size */
++ bcm2835_mmc_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
++ data->blksz), SDHCI_BLOCK_SIZE);
++ bcm2835_mmc_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
++
++ BUG_ON(!host->data);
++}
++
++static void bcm2835_mmc_set_transfer_mode(struct bcm2835_host *host,
++ struct mmc_command *cmd)
++{
++ u16 mode;
++ struct mmc_data *data = cmd->data;
++
++ if (data == NULL) {
++ /* clear Auto CMD settings for no data CMDs */
++ mode = bcm2835_mmc_readw(host, SDHCI_TRANSFER_MODE);
++ bcm2835_mmc_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
++ SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
++ return;
++ }
++
++ WARN_ON(!host->data);
++
++ mode = SDHCI_TRNS_BLK_CNT_EN;
++
++ if ((mmc_op_multi(cmd->opcode) || data->blocks > 1)) {
++ mode |= SDHCI_TRNS_MULTI;
++
++ /*
++ * If we are sending CMD23, CMD12 never gets sent
++ * on successful completion (so no Auto-CMD12).
++ */
++ if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
++ mode |= SDHCI_TRNS_AUTO_CMD12;
++ else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
++ mode |= SDHCI_TRNS_AUTO_CMD23;
++ bcm2835_mmc_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2, 5);
++ }
++ }
++
++ if (data->flags & MMC_DATA_READ)
++ mode |= SDHCI_TRNS_READ;
++ if (host->flags & SDHCI_REQ_USE_DMA)
++ mode |= SDHCI_TRNS_DMA;
++
++ bcm2835_mmc_writew(host, mode, SDHCI_TRANSFER_MODE);
++}
++
++void bcm2835_mmc_send_command(struct bcm2835_host *host, struct mmc_command *cmd)
++{
++ int flags;
++ u32 mask;
++ unsigned long timeout;
++
++ WARN_ON(host->cmd);
++
++ /* Wait max 10 ms */
++ timeout = 1000;
++
++ mask = SDHCI_CMD_INHIBIT;
++ if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
++ mask |= SDHCI_DATA_INHIBIT;
++
++ /* We shouldn't wait for data inihibit for stop commands, even
++ though they might use busy signaling */
++ if (host->mrq->data && (cmd == host->mrq->data->stop))
++ mask &= ~SDHCI_DATA_INHIBIT;
++
++ while (bcm2835_mmc_readl(host, SDHCI_PRESENT_STATE) & mask) {
++ if (timeout == 0) {
++ pr_err("%s: Controller never released inhibit bit(s).\n",
++ mmc_hostname(host->mmc));
++ bcm2835_mmc_dumpregs(host);
++ cmd->error = -EIO;
++ tasklet_schedule(&host->finish_tasklet);
++ return;
++ }
++ timeout--;
++ udelay(10);
++ }
++
++ if ((1000-timeout)/100 > 1 && (1000-timeout)/100 > host->max_delay) {
++ host->max_delay = (1000-timeout)/100;
++ pr_warning("Warning: MMC controller hung for %d ms\n", host->max_delay);
++ }
++
++ timeout = jiffies;
++#ifdef CONFIG_ARCH_BCM2835
++ if (!cmd->data && cmd->busy_timeout > 9000)
++ timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
++ else
++#endif
++ timeout += 10 * HZ;
++ mod_timer(&host->timer, timeout);
++
++ host->cmd = cmd;
++
++ bcm2835_mmc_prepare_data(host, cmd);
++
++ bcm2835_mmc_writel(host, cmd->arg, SDHCI_ARGUMENT, 6);
++
++ bcm2835_mmc_set_transfer_mode(host, cmd);
++
++ if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
++ pr_err("%s: Unsupported response type!\n",
++ mmc_hostname(host->mmc));
++ cmd->error = -EINVAL;
++ tasklet_schedule(&host->finish_tasklet);
++ return;
++ }
++
++ if (!(cmd->flags & MMC_RSP_PRESENT))
++ flags = SDHCI_CMD_RESP_NONE;
++ else if (cmd->flags & MMC_RSP_136)
++ flags = SDHCI_CMD_RESP_LONG;
++ else if (cmd->flags & MMC_RSP_BUSY)
++ flags = SDHCI_CMD_RESP_SHORT_BUSY;
++ else
++ flags = SDHCI_CMD_RESP_SHORT;
++
++ if (cmd->flags & MMC_RSP_CRC)
++ flags |= SDHCI_CMD_CRC;
++ if (cmd->flags & MMC_RSP_OPCODE)
++ flags |= SDHCI_CMD_INDEX;
++
++ if (cmd->data)
++ flags |= SDHCI_CMD_DATA;
++
++ bcm2835_mmc_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
++}
++
++
++static void bcm2835_mmc_finish_data(struct bcm2835_host *host)
++{
++ struct mmc_data *data;
++
++ BUG_ON(!host->data);
++
++ data = host->data;
++ host->data = NULL;
++
++ if (data->error)
++ data->bytes_xfered = 0;
++ else
++ data->bytes_xfered = data->blksz * data->blocks;
++
++ /*
++ * Need to send CMD12 if -
++ * a) open-ended multiblock transfer (no CMD23)
++ * b) error in multiblock transfer
++ */
++ if (data->stop &&
++ (data->error ||
++ !host->mrq->sbc)) {
++
++ /*
++ * The controller needs a reset of internal state machines
++ * upon error conditions.
++ */
++ if (data->error) {
++ bcm2835_mmc_reset(host, SDHCI_RESET_CMD);
++ bcm2835_mmc_reset(host, SDHCI_RESET_DATA);
++ }
++
++ bcm2835_mmc_send_command(host, data->stop);
++ } else
++ tasklet_schedule(&host->finish_tasklet);
++}
++
++static void bcm2835_mmc_finish_command(struct bcm2835_host *host)
++{
++ int i;
++
++ BUG_ON(host->cmd == NULL);
++
++ if (host->cmd->flags & MMC_RSP_PRESENT) {
++ if (host->cmd->flags & MMC_RSP_136) {
++ /* CRC is stripped so we need to do some shifting. */
++ for (i = 0; i < 4; i++) {
++ host->cmd->resp[i] = bcm2835_mmc_readl(host,
++ SDHCI_RESPONSE + (3-i)*4) << 8;
++ if (i != 3)
++ host->cmd->resp[i] |=
++ bcm2835_mmc_readb(host,
++ SDHCI_RESPONSE + (3-i)*4-1);
++ }
++ } else {
++ host->cmd->resp[0] = bcm2835_mmc_readl(host, SDHCI_RESPONSE);
++ }
++ }
++
++ host->cmd->error = 0;
++
++ /* Finished CMD23, now send actual command. */
++ if (host->cmd == host->mrq->sbc) {
++ host->cmd = NULL;
++ bcm2835_mmc_send_command(host, host->mrq->cmd);
++
++ if (host->mrq->cmd->data && host->use_dma) {
++ /* DMA transfer starts now, PIO starts after interrupt */
++ bcm2835_mmc_transfer_dma(host);
++ }
++ } else {
++
++ /* Processed actual command. */
++ if (host->data && host->data_early)
++ bcm2835_mmc_finish_data(host);
++
++ if (!host->cmd->data)
++ tasklet_schedule(&host->finish_tasklet);
++
++ host->cmd = NULL;
++ }
++}
++
++
++static void bcm2835_mmc_timeout_timer(unsigned long data)
++{
++ struct bcm2835_host *host;
++ unsigned long flags;
++
++ host = (struct bcm2835_host *)data;
++
++ spin_lock_irqsave(&host->lock, flags);
++
++ if (host->mrq) {
++ pr_err("%s: Timeout waiting for hardware interrupt.\n",
++ mmc_hostname(host->mmc));
++ bcm2835_mmc_dumpregs(host);
++
++ if (host->data) {
++ host->data->error = -ETIMEDOUT;
++ bcm2835_mmc_finish_data(host);
++ } else {
++ if (host->cmd)
++ host->cmd->error = -ETIMEDOUT;
++ else
++ host->mrq->cmd->error = -ETIMEDOUT;
++
++ tasklet_schedule(&host->finish_tasklet);
++ }
++ }
++
++ mmiowb();
++ spin_unlock_irqrestore(&host->lock, flags);
++}
++
++
++static void bcm2835_mmc_enable_sdio_irq_nolock(struct bcm2835_host *host, int enable)
++{
++ if (!(host->flags & SDHCI_DEVICE_DEAD)) {
++ if (enable)
++ host->ier |= SDHCI_INT_CARD_INT;
++ else
++ host->ier &= ~SDHCI_INT_CARD_INT;
++
++ bcm2835_mmc_writel(host, host->ier, SDHCI_INT_ENABLE, 7);
++ bcm2835_mmc_writel(host, host->ier, SDHCI_SIGNAL_ENABLE, 7);
++ mmiowb();
++ }
++}
++
++static void bcm2835_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
++{
++ struct bcm2835_host *host = mmc_priv(mmc);
++ unsigned long flags;
++
++ spin_lock_irqsave(&host->lock, flags);
++ if (enable)
++ host->flags |= SDHCI_SDIO_IRQ_ENABLED;
++ else
++ host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
++
++ bcm2835_mmc_enable_sdio_irq_nolock(host, enable);
++ spin_unlock_irqrestore(&host->lock, flags);
++}
++
++static void bcm2835_mmc_cmd_irq(struct bcm2835_host *host, u32 intmask)
++{
++
++ BUG_ON(intmask == 0);
++
++ if (!host->cmd) {
++ pr_err("%s: Got command interrupt 0x%08x even "
++ "though no command operation was in progress.\n",
++ mmc_hostname(host->mmc), (unsigned)intmask);
++ bcm2835_mmc_dumpregs(host);
++ return;
++ }
++
++ if (intmask & SDHCI_INT_TIMEOUT)
++ host->cmd->error = -ETIMEDOUT;
++ else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
++ SDHCI_INT_INDEX)) {
++ host->cmd->error = -EILSEQ;
++ }
++
++ if (host->cmd->error) {
++ tasklet_schedule(&host->finish_tasklet);
++ return;
++ }
++
++ if (intmask & SDHCI_INT_RESPONSE)
++ bcm2835_mmc_finish_command(host);
++
++}
++
++static void bcm2835_mmc_data_irq(struct bcm2835_host *host, u32 intmask)
++{
++ struct dma_chan *dma_chan;
++ u32 dir_data;
++
++ BUG_ON(intmask == 0);
++
++ if (!host->data) {
++ /*
++ * The "data complete" interrupt is also used to
++ * indicate that a busy state has ended. See comment
++ * above in sdhci_cmd_irq().
++ */
++ if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
++ if (intmask & SDHCI_INT_DATA_END) {
++ bcm2835_mmc_finish_command(host);
++ return;
++ }
++ }
++
++ pr_debug("%s: Got data interrupt 0x%08x even "
++ "though no data operation was in progress.\n",
++ mmc_hostname(host->mmc), (unsigned)intmask);
++ bcm2835_mmc_dumpregs(host);
++
++ return;
++ }
++
++ if (intmask & SDHCI_INT_DATA_TIMEOUT)
++ host->data->error = -ETIMEDOUT;
++ else if (intmask & SDHCI_INT_DATA_END_BIT)
++ host->data->error = -EILSEQ;
++ else if ((intmask & SDHCI_INT_DATA_CRC) &&
++ SDHCI_GET_CMD(bcm2835_mmc_readw(host, SDHCI_COMMAND))
++ != MMC_BUS_TEST_R)
++ host->data->error = -EILSEQ;
++
++ if (host->use_dma) {
++ if (host->data->flags & MMC_DATA_WRITE) {
++ /* IRQ handled here */
++
++ dma_chan = host->dma_chan_tx;
++ dir_data = DMA_TO_DEVICE;
++ dma_unmap_sg(dma_chan->device->dev,
++ host->data->sg, host->data->sg_len,
++ dir_data);
++
++ bcm2835_mmc_finish_data(host);
++ }
++
++ } else {
++ if (host->data->error)
++ bcm2835_mmc_finish_data(host);
++ else {
++ if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
++ bcm2835_mmc_transfer_pio(host);
++
++ if (intmask & SDHCI_INT_DATA_END) {
++ if (host->cmd) {
++ /*
++ * Data managed to finish before the
++ * command completed. Make sure we do
++ * things in the proper order.
++ */
++ host->data_early = 1;
++ } else {
++ bcm2835_mmc_finish_data(host);
++ }
++ }
++ }
++ }
++}
++
++
++static irqreturn_t bcm2835_mmc_irq(int irq, void *dev_id)
++{
++ irqreturn_t result = IRQ_NONE;
++ struct bcm2835_host *host = dev_id;
++ u32 intmask, mask, unexpected = 0;
++ int max_loops = 16;
++#ifndef CONFIG_ARCH_BCM2835
++ int cardint = 0;
++#endif
++
++ spin_lock(&host->lock);
++
++ intmask = bcm2835_mmc_readl(host, SDHCI_INT_STATUS);
++
++ if (!intmask || intmask == 0xffffffff) {
++ result = IRQ_NONE;
++ goto out;
++ }
++
++ do {
++ /* Clear selected interrupts. */
++ mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
++ SDHCI_INT_BUS_POWER);
++ bcm2835_mmc_writel(host, mask, SDHCI_INT_STATUS, 8);
++
++
++ if (intmask & SDHCI_INT_CMD_MASK)
++ bcm2835_mmc_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
++
++ if (intmask & SDHCI_INT_DATA_MASK)
++ bcm2835_mmc_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
++
++ if (intmask & SDHCI_INT_BUS_POWER)
++ pr_err("%s: Card is consuming too much power!\n",
++ mmc_hostname(host->mmc));
++
++ if (intmask & SDHCI_INT_CARD_INT) {
++#ifndef CONFIG_ARCH_BCM2835
++ cardint = 1;
++#else
++ bcm2835_mmc_enable_sdio_irq_nolock(host, false);
++ host->thread_isr |= SDHCI_INT_CARD_INT;
++ result = IRQ_WAKE_THREAD;
++#endif
++ }
++
++ intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
++ SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
++ SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
++ SDHCI_INT_CARD_INT);
++
++ if (intmask) {
++ unexpected |= intmask;
++ bcm2835_mmc_writel(host, intmask, SDHCI_INT_STATUS, 9);
++ }
++
++ if (result == IRQ_NONE)
++ result = IRQ_HANDLED;
++
++ intmask = bcm2835_mmc_readl(host, SDHCI_INT_STATUS);
++ } while (intmask && --max_loops);
++out:
++ spin_unlock(&host->lock);
++
++ if (unexpected) {
++ pr_err("%s: Unexpected interrupt 0x%08x.\n",
++ mmc_hostname(host->mmc), unexpected);
++ bcm2835_mmc_dumpregs(host);
++ }
++
++#ifndef CONFIG_ARCH_BCM2835
++ if (cardint)
++ mmc_signal_sdio_irq(host->mmc);
++#endif
++
++ return result;
++}
++
++#ifdef CONFIG_ARCH_BCM2835
++static irqreturn_t bcm2835_mmc_thread_irq(int irq, void *dev_id)
++{
++ struct bcm2835_host *host = dev_id;
++ unsigned long flags;
++ u32 isr;
++
++ spin_lock_irqsave(&host->lock, flags);
++ isr = host->thread_isr;
++ host->thread_isr = 0;
++ spin_unlock_irqrestore(&host->lock, flags);
++
++ if (isr & SDHCI_INT_CARD_INT) {
++ sdio_run_irqs(host->mmc);
++
++ spin_lock_irqsave(&host->lock, flags);
++ if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
++ bcm2835_mmc_enable_sdio_irq_nolock(host, true);
++ spin_unlock_irqrestore(&host->lock, flags);
++ }
++
++ return isr ? IRQ_HANDLED : IRQ_NONE;
++}
++#endif
++
++
++
++void bcm2835_mmc_set_clock(struct bcm2835_host *host, unsigned int clock)
++{
++ int div = 0; /* Initialized for compiler warning */
++ int real_div = div, clk_mul = 1;
++ u16 clk = 0;
++ unsigned long timeout;
++ unsigned int input_clock = clock;
++
++ if (host->overclock_50 && (clock == 50000000))
++ clock = host->overclock_50 * 1000000 + 999999;
++
++ host->mmc->actual_clock = 0;
++
++ bcm2835_mmc_writew(host, 0, SDHCI_CLOCK_CONTROL);
++
++ if (clock == 0)
++ return;
++
++ /* Version 3.00 divisors must be a multiple of 2. */
++ if (host->max_clk <= clock)
++ div = 1;
++ else {
++ for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
++ div += 2) {
++ if ((host->max_clk / div) <= clock)
++ break;
++ }
++ }
++
++ real_div = div;
++ div >>= 1;
++
++ if (real_div)
++ clock = (host->max_clk * clk_mul) / real_div;
++ host->mmc->actual_clock = clock;
++
++ if ((clock > input_clock) && (clock > host->max_overclock)) {
++ pr_warn("%s: Overclocking to %dHz\n",
++ mmc_hostname(host->mmc), clock);
++ host->max_overclock = clock;
++ }
++
++ clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
++ clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
++ << SDHCI_DIVIDER_HI_SHIFT;
++ clk |= SDHCI_CLOCK_INT_EN;
++ bcm2835_mmc_writew(host, clk, SDHCI_CLOCK_CONTROL);
++
++ /* Wait max 20 ms */
++ timeout = 20;
++ while (!((clk = bcm2835_mmc_readw(host, SDHCI_CLOCK_CONTROL))
++ & SDHCI_CLOCK_INT_STABLE)) {
++ if (timeout == 0) {
++ pr_err("%s: Internal clock never "
++ "stabilised.\n", mmc_hostname(host->mmc));
++ bcm2835_mmc_dumpregs(host);
++ return;
++ }
++ timeout--;
++ mdelay(1);
++ }
++
++ if (20-timeout > 10 && 20-timeout > host->max_delay) {
++ host->max_delay = 20-timeout;
++ pr_warning("Warning: MMC controller hung for %d ms\n", host->max_delay);
++ }
++
++ clk |= SDHCI_CLOCK_CARD_EN;
++ bcm2835_mmc_writew(host, clk, SDHCI_CLOCK_CONTROL);
++}
++
++static void bcm2835_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
++{
++ struct bcm2835_host *host;
++ unsigned long flags;
++
++ host = mmc_priv(mmc);
++
++ spin_lock_irqsave(&host->lock, flags);
++
++ WARN_ON(host->mrq != NULL);
++
++ host->mrq = mrq;
++
++ if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
++ bcm2835_mmc_send_command(host, mrq->sbc);
++ else
++ bcm2835_mmc_send_command(host, mrq->cmd);
++
++ mmiowb();
++ spin_unlock_irqrestore(&host->lock, flags);
++
++ if (!(mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23)) && mrq->cmd->data && host->use_dma) {
++ /* DMA transfer starts now, PIO starts after interrupt */
++ bcm2835_mmc_transfer_dma(host);
++ }
++}
++
++
++static void bcm2835_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
++{
++
++ struct bcm2835_host *host = mmc_priv(mmc);
++ unsigned long flags;
++ u8 ctrl;
++ u16 clk, ctrl_2;
++
++ pr_debug("bcm2835_mmc_set_ios: clock %d, pwr %d, bus_width %d, timing %d, vdd %d, drv_type %d\n",
++ ios->clock, ios->power_mode, ios->bus_width,
++ ios->timing, ios->signal_voltage, ios->drv_type);
++
++ spin_lock_irqsave(&host->lock, flags);
++
++ if (!ios->clock || ios->clock != host->clock) {
++ bcm2835_mmc_set_clock(host, ios->clock);
++ host->clock = ios->clock;
++ }
++
++ if (host->pwr != SDHCI_POWER_330) {
++ host->pwr = SDHCI_POWER_330;
++ bcm2835_mmc_writeb(host, SDHCI_POWER_330 | SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
++ }
++
++ ctrl = bcm2835_mmc_readb(host, SDHCI_HOST_CONTROL);
++
++ /* set bus width */
++ ctrl &= ~SDHCI_CTRL_8BITBUS;
++ if (ios->bus_width == MMC_BUS_WIDTH_4)
++ ctrl |= SDHCI_CTRL_4BITBUS;
++ else
++ ctrl &= ~SDHCI_CTRL_4BITBUS;
++
++ ctrl &= ~SDHCI_CTRL_HISPD; /* NO_HISPD_BIT */
++
++
++ bcm2835_mmc_writeb(host, ctrl, SDHCI_HOST_CONTROL);
++ /*
++ * We only need to set Driver Strength if the
++ * preset value enable is not set.
++ */
++ ctrl_2 = bcm2835_mmc_readw(host, SDHCI_HOST_CONTROL2);
++ ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
++ if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
++ ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
++ else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
++ ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
++
++ bcm2835_mmc_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
++
++ /* Reset SD Clock Enable */
++ clk = bcm2835_mmc_readw(host, SDHCI_CLOCK_CONTROL);
++ clk &= ~SDHCI_CLOCK_CARD_EN;
++ bcm2835_mmc_writew(host, clk, SDHCI_CLOCK_CONTROL);
++
++ /* Re-enable SD Clock */
++ bcm2835_mmc_set_clock(host, host->clock);
++ bcm2835_mmc_writeb(host, ctrl, SDHCI_HOST_CONTROL);
++
++ mmiowb();
++
++ spin_unlock_irqrestore(&host->lock, flags);
++}
++
++
++static struct mmc_host_ops bcm2835_ops = {
++ .request = bcm2835_mmc_request,
++ .set_ios = bcm2835_mmc_set_ios,
++ .enable_sdio_irq = bcm2835_mmc_enable_sdio_irq,
++};
++
++
++static void bcm2835_mmc_tasklet_finish(unsigned long param)
++{
++ struct bcm2835_host *host;
++ unsigned long flags;
++ struct mmc_request *mrq;
++
++ host = (struct bcm2835_host *)param;
++
++ spin_lock_irqsave(&host->lock, flags);
++
++ /*
++ * If this tasklet gets rescheduled while running, it will
++ * be run again afterwards but without any active request.
++ */
++ if (!host->mrq) {
++ spin_unlock_irqrestore(&host->lock, flags);
++ return;
++ }
++
++ del_timer(&host->timer);
++
++ mrq = host->mrq;
++
++ /*
++ * The controller needs a reset of internal state machines
++ * upon error conditions.
++ */
++ if (!(host->flags & SDHCI_DEVICE_DEAD) &&
++ ((mrq->cmd && mrq->cmd->error) ||
++ (mrq->data && (mrq->data->error ||
++ (mrq->data->stop && mrq->data->stop->error))))) {
++
++ spin_unlock_irqrestore(&host->lock, flags);
++ bcm2835_mmc_reset(host, SDHCI_RESET_CMD);
++ bcm2835_mmc_reset(host, SDHCI_RESET_DATA);
++ spin_lock_irqsave(&host->lock, flags);
++ }
++
++ host->mrq = NULL;
++ host->cmd = NULL;
++ host->data = NULL;
++
++ mmiowb();
++
++ spin_unlock_irqrestore(&host->lock, flags);
++ mmc_request_done(host->mmc, mrq);
++}
++
++
++
++static int bcm2835_mmc_add_host(struct bcm2835_host *host)
++{
++ struct mmc_host *mmc = host->mmc;
++ struct device *dev = mmc->parent;
++#ifndef FORCE_PIO
++ struct dma_slave_config cfg;
++#endif
++ int ret;
++
++ bcm2835_mmc_reset(host, SDHCI_RESET_ALL);
++
++ host->clk_mul = 0;
++
++ mmc->f_max = host->max_clk;
++ mmc->f_max = host->max_clk;
++ mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
++
++ /* SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK */
++ host->timeout_clk = mmc->f_max / 1000;
++#ifdef CONFIG_ARCH_BCM2835
++ mmc->max_busy_timeout = (1 << 27) / host->timeout_clk;
++#endif
++ /* host controller capabilities */
++ mmc->caps = MMC_CAP_CMD23 | MMC_CAP_ERASE | MMC_CAP_NEEDS_POLL | MMC_CAP_SDIO_IRQ |
++ MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_4_BIT_DATA;
++
++ host->flags = SDHCI_AUTO_CMD23;
++
++ dev_info(dev, "mmc_debug:%x mmc_debug2:%x\n", mmc_debug, mmc_debug2);
++#ifdef FORCE_PIO
++ dev_info(dev, "Forcing PIO mode\n");
++ host->have_dma = false;
++#else
++ if (IS_ERR_OR_NULL(host->dma_chan_tx) ||
++ IS_ERR_OR_NULL(host->dma_chan_rx)) {
++ dev_err(dev, "%s: Unable to initialise DMA channels. Falling back to PIO\n",
++ DRIVER_NAME);
++ host->have_dma = false;
++ } else {
++ dev_info(dev, "DMA channels allocated");
++ host->have_dma = true;
++
++ cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
++ cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
++ cfg.slave_id = 11; /* DREQ channel */
++
++ cfg.direction = DMA_MEM_TO_DEV;
++ cfg.src_addr = 0;
++ cfg.dst_addr = host->phys_addr + SDHCI_BUFFER;
++ ret = dmaengine_slave_config(host->dma_chan_tx, &cfg);
++
++ cfg.direction = DMA_DEV_TO_MEM;
++ cfg.src_addr = host->phys_addr + SDHCI_BUFFER;
++ cfg.dst_addr = 0;
++ ret = dmaengine_slave_config(host->dma_chan_rx, &cfg);
++ }
++#endif
++ mmc->max_segs = 128;
++ mmc->max_req_size = 524288;
++ mmc->max_seg_size = mmc->max_req_size;
++ mmc->max_blk_size = 512;
++ mmc->max_blk_count = 65535;
++
++ /* report supported voltage ranges */
++ mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
++
++ tasklet_init(&host->finish_tasklet,
++ bcm2835_mmc_tasklet_finish, (unsigned long)host);
++
++ setup_timer(&host->timer, bcm2835_mmc_timeout_timer, (unsigned long)host);
++ init_waitqueue_head(&host->buf_ready_int);
++
++ bcm2835_mmc_init(host, 0);
++#ifndef CONFIG_ARCH_BCM2835
++ ret = devm_request_irq(dev, host->irq, bcm2835_mmc_irq, 0,
++ mmc_hostname(mmc), host);
++#else
++ ret = devm_request_threaded_irq(dev, host->irq, bcm2835_mmc_irq,
++ bcm2835_mmc_thread_irq, IRQF_SHARED,
++ mmc_hostname(mmc), host);
++#endif
++ if (ret) {
++ dev_err(dev, "Failed to request IRQ %d: %d\n", host->irq, ret);
++ goto untasklet;
++ }
++
++ mmiowb();
++ mmc_add_host(mmc);
++
++ return 0;
++
++untasklet:
++ tasklet_kill(&host->finish_tasklet);
++
++ return ret;
++}
++
++static int bcm2835_mmc_probe(struct platform_device *pdev)
++{
++ struct device *dev = &pdev->dev;
++ struct device_node *node = dev->of_node;
++ struct clk *clk;
++ struct resource *iomem;
++ struct bcm2835_host *host;
++ struct mmc_host *mmc;
++ int ret;
++
++ mmc = mmc_alloc_host(sizeof(*host), dev);
++ if (!mmc)
++ return -ENOMEM;
++
++ mmc->ops = &bcm2835_ops;
++ host = mmc_priv(mmc);
++ host->mmc = mmc;
++ host->timeout = msecs_to_jiffies(1000);
++ spin_lock_init(&host->lock);
++
++ iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ host->ioaddr = devm_ioremap_resource(dev, iomem);
++ if (IS_ERR(host->ioaddr)) {
++ ret = PTR_ERR(host->ioaddr);
++ goto err;
++ }
++
++ host->phys_addr = iomem->start + BCM2835_VCMMU_SHIFT;
++
++#ifndef FORCE_PIO
++ if (node) {
++ host->dma_chan_tx = dma_request_slave_channel(dev, "tx");
++ host->dma_chan_rx = dma_request_slave_channel(dev, "rx");
++ } else {
++ dma_cap_mask_t mask;
++
++ dma_cap_zero(mask);
++ /* we don't care about the channel, any would work */
++ dma_cap_set(DMA_SLAVE, mask);
++ host->dma_chan_tx = dma_request_channel(mask, NULL, NULL);
++ host->dma_chan_rx = dma_request_channel(mask, NULL, NULL);
++ }
++#endif
++ clk = devm_clk_get(dev, NULL);
++ if (IS_ERR(clk)) {
++ dev_err(dev, "could not get clk\n");
++ ret = PTR_ERR(clk);
++ goto err;
++ }
++
++ host->max_clk = clk_get_rate(clk);
++
++ host->irq = platform_get_irq(pdev, 0);
++ if (host->irq <= 0) {
++ dev_err(dev, "get IRQ failed\n");
++ ret = -EINVAL;
++ goto err;
++ }
++
++ if (node) {
++ mmc_of_parse(mmc);
++
++ /* Read any custom properties */
++ of_property_read_u32(node,
++ "brcm,overclock-50",
++ &host->overclock_50);
++ } else {
++ mmc->caps |= MMC_CAP_4_BIT_DATA;
++ }
++
++ ret = bcm2835_mmc_add_host(host);
++ if (ret)
++ goto err;
++
++ platform_set_drvdata(pdev, host);
++
++ return 0;
++err:
++ mmc_free_host(mmc);
++
++ return ret;
++}
++
++static int bcm2835_mmc_remove(struct platform_device *pdev)
++{
++ struct bcm2835_host *host = platform_get_drvdata(pdev);
++ unsigned long flags;
++ int dead;
++ u32 scratch;
++
++ dead = 0;
++ scratch = bcm2835_mmc_readl(host, SDHCI_INT_STATUS);
++ if (scratch == (u32)-1)
++ dead = 1;
++
++
++ if (dead) {
++ spin_lock_irqsave(&host->lock, flags);
++
++ host->flags |= SDHCI_DEVICE_DEAD;
++
++ if (host->mrq) {
++ pr_err("%s: Controller removed during "
++ " transfer!\n", mmc_hostname(host->mmc));
++
++ host->mrq->cmd->error = -ENOMEDIUM;
++ tasklet_schedule(&host->finish_tasklet);
++ }
++
++ spin_unlock_irqrestore(&host->lock, flags);
++ }
++
++ mmc_remove_host(host->mmc);
++
++ if (!dead)
++ bcm2835_mmc_reset(host, SDHCI_RESET_ALL);
++
++ free_irq(host->irq, host);
++
++ del_timer_sync(&host->timer);
++
++ tasklet_kill(&host->finish_tasklet);
++
++ mmc_free_host(host->mmc);
++ platform_set_drvdata(pdev, NULL);
++
++ return 0;
++}
++
++
++static const struct of_device_id bcm2835_mmc_match[] = {
++ { .compatible = "brcm,bcm2835-mmc" },
++ { }
++};
++MODULE_DEVICE_TABLE(of, bcm2835_mmc_match);
++
++
++
++static struct platform_driver bcm2835_mmc_driver = {
++ .probe = bcm2835_mmc_probe,
++ .remove = bcm2835_mmc_remove,
++ .driver = {
++ .name = DRIVER_NAME,
++ .owner = THIS_MODULE,
++ .of_match_table = bcm2835_mmc_match,
++ },
++};
++module_platform_driver(bcm2835_mmc_driver);
++
++module_param(mmc_debug, uint, 0644);
++module_param(mmc_debug2, uint, 0644);
++MODULE_ALIAS("platform:mmc-bcm2835");
++MODULE_DESCRIPTION("BCM2835 SDHCI driver");
++MODULE_LICENSE("GPL v2");
++MODULE_AUTHOR("Gellert Weisz");
+diff -Nur linux-4.1.3/drivers/mmc/host/bcm2835-sdhost.c linux-xbian-rpi/drivers/mmc/host/bcm2835-sdhost.c
+--- linux-4.1.3/drivers/mmc/host/bcm2835-sdhost.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/mmc/host/bcm2835-sdhost.c 2015-07-28 01:20:58.289711085 +0200
+@@ -0,0 +1,1930 @@
++/*
++ * BCM2835 SD host driver.
++ *
++ * Author: Phil Elwell <phil@raspberrypi.org>
++ * Copyright 2015
++ *
++ * Based on
++ * mmc-bcm2835.c by Gellert Weisz
++ * which is, in turn, based on
++ * sdhci-bcm2708.c by Broadcom
++ * sdhci-bcm2835.c by Stephen Warren and Oleksandr Tymoshenko
++ * sdhci.c and sdhci-pci.c by Pierre Ossman
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms and conditions of the GNU General Public License,
++ * version 2, as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#define SAFE_READ_THRESHOLD 4
++#define SAFE_WRITE_THRESHOLD 4
++#define ALLOW_DMA 1
++#define ALLOW_CMD23 0
++#define ALLOW_FAST 1
++#define USE_BLOCK_IRQ 1
++
++#include <linux/delay.h>
++#include <linux/module.h>
++#include <linux/io.h>
++#include <linux/mmc/mmc.h>
++#include <linux/mmc/host.h>
++#include <linux/mmc/sd.h>
++#include <linux/scatterlist.h>
++#include <linux/of_address.h>
++#include <linux/of_irq.h>
++#include <linux/clk.h>
++#include <linux/platform_device.h>
++#include <linux/err.h>
++#include <linux/blkdev.h>
++#include <linux/dmaengine.h>
++#include <linux/dma-mapping.h>
++#include <linux/of_dma.h>
++#include <linux/time.h>
++
++#define DRIVER_NAME "sdhost-bcm2835"
++
++#define SDCMD 0x00 /* Command to SD card - 16 R/W */
++#define SDARG 0x04 /* Argument to SD card - 32 R/W */
++#define SDTOUT 0x08 /* Start value for timeout counter - 32 R/W */
++#define SDCDIV 0x0c /* Start value for clock divider - 11 R/W */
++#define SDRSP0 0x10 /* SD card response (31:0) - 32 R */
++#define SDRSP1 0x14 /* SD card response (63:32) - 32 R */
++#define SDRSP2 0x18 /* SD card response (95:64) - 32 R */
++#define SDRSP3 0x1c /* SD card response (127:96) - 32 R */
++#define SDHSTS 0x20 /* SD host status - 11 R */
++#define SDVDD 0x30 /* SD card power control - 1 R/W */
++#define SDEDM 0x34 /* Emergency Debug Mode - 13 R/W */
++#define SDHCFG 0x38 /* Host configuration - 2 R/W */
++#define SDHBCT 0x3c /* Host byte count (debug) - 32 R/W */
++#define SDDATA 0x40 /* Data to/from SD card - 32 R/W */
++#define SDHBLC 0x50 /* Host block count (SDIO/SDHC) - 9 R/W */
++
++#define SDCMD_NEW_FLAG 0x8000
++#define SDCMD_FAIL_FLAG 0x4000
++#define SDCMD_BUSYWAIT 0x800
++#define SDCMD_NO_RESPONSE 0x400
++#define SDCMD_LONG_RESPONSE 0x200
++#define SDCMD_WRITE_CMD 0x80
++#define SDCMD_READ_CMD 0x40
++#define SDCMD_CMD_MASK 0x3f
++
++#define SDCDIV_MAX_CDIV 0x7ff
++
++#define SDHSTS_BUSY_IRPT 0x400
++#define SDHSTS_BLOCK_IRPT 0x200
++#define SDHSTS_SDIO_IRPT 0x100
++#define SDHSTS_REW_TIME_OUT 0x80
++#define SDHSTS_CMD_TIME_OUT 0x40
++#define SDHSTS_CRC16_ERROR 0x20
++#define SDHSTS_CRC7_ERROR 0x10
++#define SDHSTS_FIFO_ERROR 0x08
++/* Reserved */
++/* Reserved */
++#define SDHSTS_DATA_FLAG 0x01
++
++#define SDHSTS_TRANSFER_ERROR_MASK (SDHSTS_CRC7_ERROR|SDHSTS_CRC16_ERROR|SDHSTS_REW_TIME_OUT|SDHSTS_FIFO_ERROR)
++#define SDHSTS_ERROR_MASK (SDHSTS_CMD_TIME_OUT|SDHSTS_TRANSFER_ERROR_MASK)
++
++#define SDHCFG_BUSY_IRPT_EN (1<<10)
++#define SDHCFG_BLOCK_IRPT_EN (1<<8)
++#define SDHCFG_SDIO_IRPT_EN (1<<5)
++#define SDHCFG_DATA_IRPT_EN (1<<4)
++#define SDHCFG_SLOW_CARD (1<<3)
++#define SDHCFG_WIDE_EXT_BUS (1<<2)
++#define SDHCFG_WIDE_INT_BUS (1<<1)
++#define SDHCFG_REL_CMD_LINE (1<<0)
++
++#define SDEDM_FORCE_DATA_MODE (1<<19)
++#define SDEDM_CLOCK_PULSE (1<<20)
++#define SDEDM_BYPASS (1<<21)
++
++#define SDEDM_WRITE_THRESHOLD_SHIFT 9
++#define SDEDM_READ_THRESHOLD_SHIFT 14
++#define SDEDM_THRESHOLD_MASK 0x1f
++
++#define MHZ 1000000
++
++#ifndef BCM2708_PERI_BASE
++ #define BCM2708_PERI_BASE 0x20000000
++#endif
++
++/* FIXME: Needs IOMMU support */
++#define BCM2835_VCMMU_SHIFT (0x7E000000 - BCM2708_PERI_BASE)
++
++
++struct bcm2835_host {
++ spinlock_t lock;
++
++ void __iomem *ioaddr;
++ u32 phys_addr;
++
++ struct mmc_host *mmc;
++
++ u32 pio_timeout; /* In jiffies */
++
++ int clock; /* Current clock speed */
++
++ bool slow_card; /* Force 11-bit divisor */
++
++ unsigned int max_clk; /* Max possible freq */
++
++ struct tasklet_struct finish_tasklet; /* Tasklet structures */
++
++ struct timer_list timer; /* Timer for timeouts */
++
++ struct timer_list pio_timer; /* PIO error detection timer */
++
++ struct sg_mapping_iter sg_miter; /* SG state for PIO */
++ unsigned int blocks; /* remaining PIO blocks */
++
++ int irq; /* Device IRQ */
++
++
++ /* cached registers */
++ u32 hcfg;
++ u32 cdiv;
++
++ struct mmc_request *mrq; /* Current request */
++ struct mmc_command *cmd; /* Current command */
++ struct mmc_data *data; /* Current data request */
++ unsigned int data_complete:1; /* Data finished before cmd */
++
++ unsigned int flush_fifo:1; /* Drain the fifo when finishing */
++
++ unsigned int use_busy:1; /* Wait for busy interrupt */
++
++ unsigned int debug:1; /* Enable debug output */
++
++ u32 thread_isr;
++
++ /*DMA part*/
++ struct dma_chan *dma_chan_rx; /* DMA channel for reads */
++ struct dma_chan *dma_chan_tx; /* DMA channel for writes */
++
++ bool allow_dma;
++ bool have_dma;
++ bool use_dma;
++ /*end of DMA part*/
++
++ int max_delay; /* maximum length of time spent waiting */
++ struct timeval stop_time; /* when the last stop was issued */
++ u32 delay_after_stop; /* minimum time between stop and subsequent data transfer */
++ u32 overclock_50; /* frequency to use when 50MHz is requested (in MHz) */
++ u32 overclock; /* Current frequency if overclocked, else zero */
++ u32 pio_limit; /* Maximum block count for PIO (0 = always DMA) */
++};
++
++
++static inline void bcm2835_sdhost_write(struct bcm2835_host *host, u32 val, int reg)
++{
++ writel(val, host->ioaddr + reg);
++}
++
++static inline u32 bcm2835_sdhost_read(struct bcm2835_host *host, int reg)
++{
++ return readl(host->ioaddr + reg);
++}
++
++static inline u32 bcm2835_sdhost_read_relaxed(struct bcm2835_host *host, int reg)
++{
++ return readl_relaxed(host->ioaddr + reg);
++}
++
++static void bcm2835_sdhost_dumpcmd(struct bcm2835_host *host,
++ struct mmc_command *cmd,
++ const char *label)
++{
++ if (cmd)
++ pr_info("%s:%c%s op %d arg 0x%x flags 0x%x - resp %08x %08x %08x %08x, err %d\n",
++ mmc_hostname(host->mmc),
++ (cmd == host->cmd) ? '>' : ' ',
++ label, cmd->opcode, cmd->arg, cmd->flags,
++ cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3],
++ cmd->error);
++}
++
++static void bcm2835_sdhost_dumpregs(struct bcm2835_host *host)
++{
++ bcm2835_sdhost_dumpcmd(host, host->mrq->sbc, "sbc");
++ bcm2835_sdhost_dumpcmd(host, host->mrq->cmd, "cmd");
++ if (host->mrq->data)
++ pr_err("%s: data blocks %x blksz %x - err %d\n",
++ mmc_hostname(host->mmc),
++ host->mrq->data->blocks,
++ host->mrq->data->blksz,
++ host->mrq->data->error);
++ bcm2835_sdhost_dumpcmd(host, host->mrq->stop, "stop");
++
++ pr_info("%s: =========== REGISTER DUMP ===========\n",
++ mmc_hostname(host->mmc));
++
++ pr_info("%s: SDCMD 0x%08x\n",
++ mmc_hostname(host->mmc),
++ bcm2835_sdhost_read(host, SDCMD));
++ pr_info("%s: SDARG 0x%08x\n",
++ mmc_hostname(host->mmc),
++ bcm2835_sdhost_read(host, SDARG));
++ pr_info("%s: SDTOUT 0x%08x\n",
++ mmc_hostname(host->mmc),
++ bcm2835_sdhost_read(host, SDTOUT));
++ pr_info("%s: SDCDIV 0x%08x\n",
++ mmc_hostname(host->mmc),
++ bcm2835_sdhost_read(host, SDCDIV));
++ pr_info("%s: SDRSP0 0x%08x\n",
++ mmc_hostname(host->mmc),
++ bcm2835_sdhost_read(host, SDRSP0));
++ pr_info("%s: SDRSP1 0x%08x\n",
++ mmc_hostname(host->mmc),
++ bcm2835_sdhost_read(host, SDRSP1));
++ pr_info("%s: SDRSP2 0x%08x\n",
++ mmc_hostname(host->mmc),
++ bcm2835_sdhost_read(host, SDRSP2));
++ pr_info("%s: SDRSP3 0x%08x\n",
++ mmc_hostname(host->mmc),
++ bcm2835_sdhost_read(host, SDRSP3));
++ pr_info("%s: SDHSTS 0x%08x\n",
++ mmc_hostname(host->mmc),
++ bcm2835_sdhost_read(host, SDHSTS));
++ pr_info("%s: SDVDD 0x%08x\n",
++ mmc_hostname(host->mmc),
++ bcm2835_sdhost_read(host, SDVDD));
++ pr_info("%s: SDEDM 0x%08x\n",
++ mmc_hostname(host->mmc),
++ bcm2835_sdhost_read(host, SDEDM));
++ pr_info("%s: SDHCFG 0x%08x\n",
++ mmc_hostname(host->mmc),
++ bcm2835_sdhost_read(host, SDHCFG));
++ pr_info("%s: SDHBCT 0x%08x\n",
++ mmc_hostname(host->mmc),
++ bcm2835_sdhost_read(host, SDHBCT));
++ pr_info("%s: SDHBLC 0x%08x\n",
++ mmc_hostname(host->mmc),
++ bcm2835_sdhost_read(host, SDHBLC));
++
++ pr_info("%s: ===========================================\n",
++ mmc_hostname(host->mmc));
++}
++
++
++static void bcm2835_sdhost_set_power(struct bcm2835_host *host, bool on)
++{
++ bcm2835_sdhost_write(host, on ? 1 : 0, SDVDD);
++}
++
++
++static void bcm2835_sdhost_reset_internal(struct bcm2835_host *host)
++{
++ u32 temp;
++
++ bcm2835_sdhost_set_power(host, false);
++
++ bcm2835_sdhost_write(host, 0, SDCMD);
++ bcm2835_sdhost_write(host, 0, SDARG);
++ bcm2835_sdhost_write(host, 0xf00000, SDTOUT);
++ bcm2835_sdhost_write(host, 0, SDCDIV);
++ bcm2835_sdhost_write(host, 0x7f8, SDHSTS); /* Write 1s to clear */
++ bcm2835_sdhost_write(host, 0, SDHCFG);
++ bcm2835_sdhost_write(host, 0, SDHBCT);
++ bcm2835_sdhost_write(host, 0, SDHBLC);
++
++ /* Limit fifo usage due to silicon bug */
++ temp = bcm2835_sdhost_read(host, SDEDM);
++ temp &= ~((SDEDM_THRESHOLD_MASK<<SDEDM_READ_THRESHOLD_SHIFT) |
++ (SDEDM_THRESHOLD_MASK<<SDEDM_WRITE_THRESHOLD_SHIFT));
++ temp |= (SAFE_READ_THRESHOLD << SDEDM_READ_THRESHOLD_SHIFT) |
++ (SAFE_WRITE_THRESHOLD << SDEDM_WRITE_THRESHOLD_SHIFT);
++ bcm2835_sdhost_write(host, temp, SDEDM);
++ mdelay(10);
++ bcm2835_sdhost_set_power(host, true);
++ mdelay(10);
++ host->clock = 0;
++ bcm2835_sdhost_write(host, host->hcfg, SDHCFG);
++ bcm2835_sdhost_write(host, host->cdiv, SDCDIV);
++ mmiowb();
++}
++
++
++static void bcm2835_sdhost_reset(struct mmc_host *mmc)
++{
++ struct bcm2835_host *host = mmc_priv(mmc);
++ unsigned long flags;
++ if (host->debug)
++ pr_info("%s: reset\n", mmc_hostname(mmc));
++ spin_lock_irqsave(&host->lock, flags);
++
++ bcm2835_sdhost_reset_internal(host);
++
++ spin_unlock_irqrestore(&host->lock, flags);
++}
++
++static void bcm2835_sdhost_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
++
++static void bcm2835_sdhost_init(struct bcm2835_host *host, int soft)
++{
++ pr_debug("bcm2835_sdhost_init(%d)\n", soft);
++
++ /* Set interrupt enables */
++ host->hcfg = SDHCFG_BUSY_IRPT_EN;
++
++ bcm2835_sdhost_reset_internal(host);
++
++ if (soft) {
++ /* force clock reconfiguration */
++ host->clock = 0;
++ bcm2835_sdhost_set_ios(host->mmc, &host->mmc->ios);
++ }
++}
++
++static bool bcm2835_sdhost_is_write_complete(struct bcm2835_host *host)
++{
++ bool write_complete = ((bcm2835_sdhost_read(host, SDEDM) & 0xf) == 1);
++
++ if (!write_complete) {
++ /* Request an IRQ for the last block */
++ host->hcfg |= SDHCFG_BLOCK_IRPT_EN;
++ bcm2835_sdhost_write(host, host->hcfg, SDHCFG);
++ if ((bcm2835_sdhost_read(host, SDEDM) & 0xf) == 1) {
++ /* The write has now completed. Disable the interrupt
++ and clear the status flag */
++ host->hcfg &= ~SDHCFG_BLOCK_IRPT_EN;
++ bcm2835_sdhost_write(host, host->hcfg, SDHCFG);
++ bcm2835_sdhost_write(host, SDHSTS_BLOCK_IRPT, SDHSTS);
++ write_complete = true;
++ }
++ }
++
++ return write_complete;
++}
++
++static void bcm2835_sdhost_wait_write_complete(struct bcm2835_host *host)
++{
++ int timediff;
++#ifdef DEBUG
++ static struct timeval start_time;
++ static int max_stall_time = 0;
++ static int total_stall_time = 0;
++ struct timeval before, after;
++
++ do_gettimeofday(&before);
++ if (max_stall_time == 0)
++ start_time = before;
++#endif
++
++ timediff = 0;
++
++ while (1) {
++ u32 edm = bcm2835_sdhost_read(host, SDEDM);
++ if ((edm & 0xf) == 1)
++ break;
++ timediff++;
++ if (timediff > 5000000) {
++#ifdef DEBUG
++ do_gettimeofday(&after);
++ timediff = (after.tv_sec - before.tv_sec)*1000000 +
++ (after.tv_usec - before.tv_usec);
++
++ pr_err(" wait_write_complete - still waiting after %dus\n",
++ timediff);
++#else
++ pr_err(" wait_write_complete - still waiting after %d retries\n",
++ timediff);
++#endif
++ bcm2835_sdhost_dumpregs(host);
++ host->data->error = -ETIMEDOUT;
++ return;
++ }
++ }
++
++#ifdef DEBUG
++ do_gettimeofday(&after);
++ timediff = (after.tv_sec - before.tv_sec)*1000000 + (after.tv_usec - before.tv_usec);
++
++ total_stall_time += timediff;
++ if (timediff > max_stall_time)
++ max_stall_time = timediff;
++
++ if ((after.tv_sec - start_time.tv_sec) > 10) {
++ pr_debug(" wait_write_complete - max wait %dus, total %dus\n",
++ max_stall_time, total_stall_time);
++ start_time = after;
++ max_stall_time = 0;
++ total_stall_time = 0;
++ }
++#endif
++}
++
++static void bcm2835_sdhost_finish_data(struct bcm2835_host *host);
++
++static void bcm2835_sdhost_dma_complete(void *param)
++{
++ struct bcm2835_host *host = param;
++ struct dma_chan *dma_chan;
++ unsigned long flags;
++ u32 dir_data;
++
++ spin_lock_irqsave(&host->lock, flags);
++
++ if (host->data) {
++ bool write_complete;
++ if (USE_BLOCK_IRQ)
++ write_complete = bcm2835_sdhost_is_write_complete(host);
++ else {
++ bcm2835_sdhost_wait_write_complete(host);
++ write_complete = true;
++ }
++ pr_debug("dma_complete() - write_complete=%d\n",
++ write_complete);
++
++ if (write_complete || (host->data->flags & MMC_DATA_READ))
++ {
++ if (write_complete) {
++ dma_chan = host->dma_chan_tx;
++ dir_data = DMA_TO_DEVICE;
++ } else {
++ dma_chan = host->dma_chan_rx;
++ dir_data = DMA_FROM_DEVICE;
++ }
++
++ dma_unmap_sg(dma_chan->device->dev,
++ host->data->sg, host->data->sg_len,
++ dir_data);
++
++ bcm2835_sdhost_finish_data(host);
++ }
++ }
++
++ spin_unlock_irqrestore(&host->lock, flags);
++}
++
++static bool data_transfer_wait(struct bcm2835_host *host)
++{
++ unsigned long timeout = 1000000;
++ while (timeout)
++ {
++ u32 sdhsts = bcm2835_sdhost_read(host, SDHSTS);
++ if (sdhsts & SDHSTS_DATA_FLAG) {
++ bcm2835_sdhost_write(host, SDHSTS_DATA_FLAG, SDHSTS);
++ break;
++ }
++ timeout--;
++ }
++ if (timeout == 0) {
++ pr_err("%s: Data %s timeout\n",
++ mmc_hostname(host->mmc),
++ (host->data->flags & MMC_DATA_READ) ? "read" : "write");
++ bcm2835_sdhost_dumpregs(host);
++ host->data->error = -ETIMEDOUT;
++ return false;
++ }
++ return true;
++}
++
++static void bcm2835_sdhost_read_block_pio(struct bcm2835_host *host)
++{
++ unsigned long flags;
++ size_t blksize, len;
++ u32 *buf;
++
++ blksize = host->data->blksz;
++
++ local_irq_save(flags);
++
++ while (blksize) {
++ if (!sg_miter_next(&host->sg_miter))
++ BUG();
++
++ len = min(host->sg_miter.length, blksize);
++ BUG_ON(len % 4);
++
++ blksize -= len;
++ host->sg_miter.consumed = len;
++
++ buf = (u32 *)host->sg_miter.addr;
++
++ while (len) {
++ if (!data_transfer_wait(host))
++ break;
++
++ *(buf++) = bcm2835_sdhost_read(host, SDDATA);
++ len -= 4;
++ }
++
++ if (host->data->error)
++ break;
++ }
++
++ sg_miter_stop(&host->sg_miter);
++
++ local_irq_restore(flags);
++}
++
++static void bcm2835_sdhost_write_block_pio(struct bcm2835_host *host)
++{
++ unsigned long flags;
++ size_t blksize, len;
++ u32 *buf;
++
++ blksize = host->data->blksz;
++
++ local_irq_save(flags);
++
++ while (blksize) {
++ if (!sg_miter_next(&host->sg_miter))
++ BUG();
++
++ len = min(host->sg_miter.length, blksize);
++ BUG_ON(len % 4);
++
++ blksize -= len;
++ host->sg_miter.consumed = len;
++
++ buf = host->sg_miter.addr;
++
++ while (len) {
++ if (!data_transfer_wait(host))
++ break;
++
++ bcm2835_sdhost_write(host, *(buf++), SDDATA);
++ len -= 4;
++ }
++
++ if (host->data->error)
++ break;
++ }
++
++ sg_miter_stop(&host->sg_miter);
++
++ local_irq_restore(flags);
++}
++
++
++static void bcm2835_sdhost_transfer_pio(struct bcm2835_host *host)
++{
++ u32 sdhsts;
++ bool is_read;
++ BUG_ON(!host->data);
++
++ is_read = (host->data->flags & MMC_DATA_READ) != 0;
++ if (is_read)
++ bcm2835_sdhost_read_block_pio(host);
++ else
++ bcm2835_sdhost_write_block_pio(host);
++
++ sdhsts = bcm2835_sdhost_read(host, SDHSTS);
++ if (sdhsts & (SDHSTS_CRC16_ERROR |
++ SDHSTS_CRC7_ERROR |
++ SDHSTS_FIFO_ERROR)) {
++ pr_err("%s: %s transfer error - HSTS %x\n",
++ mmc_hostname(host->mmc),
++ is_read ? "read" : "write",
++ sdhsts);
++ host->data->error = -EILSEQ;
++ } else if ((sdhsts & (SDHSTS_CMD_TIME_OUT |
++ SDHSTS_REW_TIME_OUT))) {
++ pr_err("%s: %s timeout error - HSTS %x\n",
++ mmc_hostname(host->mmc),
++ is_read ? "read" : "write",
++ sdhsts);
++ host->data->error = -ETIMEDOUT;
++ } else if (!is_read && !host->data->error) {
++ /* Start a timer in case a transfer error occurs because
++ there is no error interrupt */
++ mod_timer(&host->pio_timer, jiffies + host->pio_timeout);
++ }
++}
++
++
++static void bcm2835_sdhost_transfer_dma(struct bcm2835_host *host)
++{
++ u32 len, dir_data, dir_slave;
++ struct dma_async_tx_descriptor *desc = NULL;
++ struct dma_chan *dma_chan;
++
++ pr_debug("bcm2835_sdhost_transfer_dma()\n");
++
++ WARN_ON(!host->data);
++
++ if (!host->data)
++ return;
++
++ if (host->data->flags & MMC_DATA_READ) {
++ dma_chan = host->dma_chan_rx;
++ dir_data = DMA_FROM_DEVICE;
++ dir_slave = DMA_DEV_TO_MEM;
++ } else {
++ dma_chan = host->dma_chan_tx;
++ dir_data = DMA_TO_DEVICE;
++ dir_slave = DMA_MEM_TO_DEV;
++ }
++
++ BUG_ON(!dma_chan->device);
++ BUG_ON(!dma_chan->device->dev);
++ BUG_ON(!host->data->sg);
++
++ len = dma_map_sg(dma_chan->device->dev, host->data->sg,
++ host->data->sg_len, dir_data);
++ if (len > 0) {
++ desc = dmaengine_prep_slave_sg(dma_chan, host->data->sg,
++ len, dir_slave,
++ DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
++ } else {
++ dev_err(mmc_dev(host->mmc), "dma_map_sg returned zero length\n");
++ }
++ if (desc) {
++ desc->callback = bcm2835_sdhost_dma_complete;
++ desc->callback_param = host;
++ dmaengine_submit(desc);
++ dma_async_issue_pending(dma_chan);
++ }
++
++}
++
++
++static void bcm2835_sdhost_set_transfer_irqs(struct bcm2835_host *host)
++{
++ u32 all_irqs = SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN |
++ SDHCFG_BUSY_IRPT_EN;
++ if (host->use_dma)
++ host->hcfg = (host->hcfg & ~all_irqs) |
++ SDHCFG_BUSY_IRPT_EN;
++ else
++ host->hcfg = (host->hcfg & ~all_irqs) |
++ SDHCFG_DATA_IRPT_EN |
++ SDHCFG_BUSY_IRPT_EN;
++
++ bcm2835_sdhost_write(host, host->hcfg, SDHCFG);
++}
++
++
++static void bcm2835_sdhost_prepare_data(struct bcm2835_host *host, struct mmc_command *cmd)
++{
++ struct mmc_data *data = cmd->data;
++
++ WARN_ON(host->data);
++
++ if (!data)
++ return;
++
++ /* Sanity checks */
++ BUG_ON(data->blksz * data->blocks > 524288);
++ BUG_ON(data->blksz > host->mmc->max_blk_size);
++ BUG_ON(data->blocks > 65535);
++
++ host->data = data;
++ host->data_complete = 0;
++ host->flush_fifo = 0;
++ host->data->bytes_xfered = 0;
++
++ host->use_dma = host->have_dma && (data->blocks > host->pio_limit);
++ if (!host->use_dma) {
++ int flags;
++
++ flags = SG_MITER_ATOMIC;
++ if (data->flags & MMC_DATA_READ)
++ flags |= SG_MITER_TO_SG;
++ else
++ flags |= SG_MITER_FROM_SG;
++ sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
++ host->blocks = data->blocks;
++ }
++
++ bcm2835_sdhost_set_transfer_irqs(host);
++
++ bcm2835_sdhost_write(host, data->blksz, SDHBCT);
++ bcm2835_sdhost_write(host, host->use_dma ? data->blocks : 0, SDHBLC);
++
++ BUG_ON(!host->data);
++}
++
++
++void bcm2835_sdhost_send_command(struct bcm2835_host *host, struct mmc_command *cmd)
++{
++ u32 sdcmd, sdhsts;
++ unsigned long timeout;
++ int delay;
++
++ WARN_ON(host->cmd);
++
++ if (cmd->data)
++ pr_debug("%s: send_command %d 0x%x "
++ "(flags 0x%x) - %s %d*%d\n",
++ mmc_hostname(host->mmc),
++ cmd->opcode, cmd->arg, cmd->flags,
++ (cmd->data->flags & MMC_DATA_READ) ?
++ "read" : "write", cmd->data->blocks,
++ cmd->data->blksz);
++ else
++ pr_debug("%s: send_command %d 0x%x (flags 0x%x)\n",
++ mmc_hostname(host->mmc),
++ cmd->opcode, cmd->arg, cmd->flags);
++
++ /* Wait max 100 ms */
++ timeout = 10000;
++
++ while (bcm2835_sdhost_read(host, SDCMD) & SDCMD_NEW_FLAG) {
++ if (timeout == 0) {
++ pr_err("%s: previous command never completed.\n",
++ mmc_hostname(host->mmc));
++ bcm2835_sdhost_dumpregs(host);
++ cmd->error = -EIO;
++ tasklet_schedule(&host->finish_tasklet);
++ return;
++ }
++ timeout--;
++ udelay(10);
++ }
++
++ delay = (10000 - timeout)/100;
++ if (delay > host->max_delay) {
++ host->max_delay = delay;
++ pr_warning("%s: controller hung for %d ms\n",
++ mmc_hostname(host->mmc),
++ host->max_delay);
++ }
++
++ timeout = jiffies;
++ if (!cmd->data && cmd->busy_timeout > 9000)
++ timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
++ else
++ timeout += 10 * HZ;
++ mod_timer(&host->timer, timeout);
++
++ host->cmd = cmd;
++
++ /* Clear any error flags */
++ sdhsts = bcm2835_sdhost_read(host, SDHSTS);
++ if (sdhsts & SDHSTS_ERROR_MASK)
++ bcm2835_sdhost_write(host, sdhsts, SDHSTS);
++
++ bcm2835_sdhost_prepare_data(host, cmd);
++
++ bcm2835_sdhost_write(host, cmd->arg, SDARG);
++
++ if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
++ pr_err("%s: unsupported response type!\n",
++ mmc_hostname(host->mmc));
++ cmd->error = -EINVAL;
++ tasklet_schedule(&host->finish_tasklet);
++ return;
++ }
++
++ sdcmd = cmd->opcode & SDCMD_CMD_MASK;
++
++ if (!(cmd->flags & MMC_RSP_PRESENT))
++ sdcmd |= SDCMD_NO_RESPONSE;
++ else {
++ if (cmd->flags & MMC_RSP_136)
++ sdcmd |= SDCMD_LONG_RESPONSE;
++ if (cmd->flags & MMC_RSP_BUSY) {
++ sdcmd |= SDCMD_BUSYWAIT;
++ host->use_busy = 1;
++ }
++ }
++
++ if (cmd->data) {
++ if (host->delay_after_stop) {
++ struct timeval now;
++ int time_since_stop;
++ do_gettimeofday(&now);
++ time_since_stop = (now.tv_sec - host->stop_time.tv_sec);
++ if (time_since_stop < 2) {
++ /* Possibly less than one second */
++ time_since_stop = time_since_stop * 1000000 +
++ (now.tv_usec - host->stop_time.tv_usec);
++ if (time_since_stop < host->delay_after_stop)
++ udelay(host->delay_after_stop -
++ time_since_stop);
++ }
++ }
++
++ if (cmd->data->flags & MMC_DATA_WRITE)
++ sdcmd |= SDCMD_WRITE_CMD;
++ if (cmd->data->flags & MMC_DATA_READ)
++ sdcmd |= SDCMD_READ_CMD;
++ }
++
++ bcm2835_sdhost_write(host, sdcmd | SDCMD_NEW_FLAG, SDCMD);
++}
++
++
++static void bcm2835_sdhost_finish_command(struct bcm2835_host *host);
++static void bcm2835_sdhost_transfer_complete(struct bcm2835_host *host);
++
++static void bcm2835_sdhost_finish_data(struct bcm2835_host *host)
++{
++ struct mmc_data *data;
++
++ data = host->data;
++ BUG_ON(!data);
++
++ pr_debug("finish_data(error %d, stop %d, sbc %d)\n",
++ data->error, data->stop ? 1 : 0,
++ host->mrq->sbc ? 1 : 0);
++
++ host->hcfg &= ~(SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN);
++ bcm2835_sdhost_write(host, host->hcfg, SDHCFG);
++
++ if (data->error) {
++ data->bytes_xfered = 0;
++ } else
++ data->bytes_xfered = data->blksz * data->blocks;
++
++ host->data_complete = 1;
++
++ if (host->cmd) {
++ /*
++ * Data managed to finish before the
++ * command completed. Make sure we do
++ * things in the proper order.
++ */
++ pr_debug("Finished early - HSTS %x\n",
++ bcm2835_sdhost_read(host, SDHSTS));
++ }
++ else
++ bcm2835_sdhost_transfer_complete(host);
++}
++
++
++static void bcm2835_sdhost_transfer_complete(struct bcm2835_host *host)
++{
++ struct mmc_data *data;
++
++ BUG_ON(host->cmd);
++ BUG_ON(!host->data);
++ BUG_ON(!host->data_complete);
++
++ data = host->data;
++ host->data = NULL;
++
++ pr_debug("transfer_complete(error %d, stop %d)\n",
++ data->error, data->stop ? 1 : 0);
++
++ /*
++ * Need to send CMD12 if -
++ * a) open-ended multiblock transfer (no CMD23)
++ * b) error in multiblock transfer
++ */
++ if (data->stop &&
++ (data->error ||
++ !host->mrq->sbc)) {
++ host->flush_fifo = 1;
++ bcm2835_sdhost_send_command(host, data->stop);
++ if (host->delay_after_stop)
++ do_gettimeofday(&host->stop_time);
++ if (!host->use_busy)
++ bcm2835_sdhost_finish_command(host);
++ } else {
++ tasklet_schedule(&host->finish_tasklet);
++ }
++}
++
++static void bcm2835_sdhost_finish_command(struct bcm2835_host *host)
++{
++ u32 sdcmd;
++ unsigned long timeout;
++#ifdef DEBUG
++ struct timeval before, after;
++ int timediff = 0;
++#endif
++
++ pr_debug("finish_command(%x)\n", bcm2835_sdhost_read(host, SDCMD));
++
++ BUG_ON(!host->cmd || !host->mrq);
++
++#ifdef DEBUG
++ do_gettimeofday(&before);
++#endif
++ /* Wait max 100 ms */
++ timeout = 10000;
++ for (sdcmd = bcm2835_sdhost_read(host, SDCMD);
++ (sdcmd & SDCMD_NEW_FLAG) && timeout;
++ timeout--) {
++ if (host->flush_fifo) {
++ while (bcm2835_sdhost_read(host, SDHSTS) &
++ SDHSTS_DATA_FLAG)
++ (void)bcm2835_sdhost_read(host, SDDATA);
++ }
++ udelay(10);
++ sdcmd = bcm2835_sdhost_read(host, SDCMD);
++ }
++#ifdef DEBUG
++ do_gettimeofday(&after);
++ timediff = (after.tv_sec - before.tv_sec)*1000000 +
++ (after.tv_usec - before.tv_usec);
++
++ pr_debug(" finish_command - waited %dus\n", timediff);
++#endif
++
++ if (timeout == 0) {
++ pr_err("%s: command never completed.\n",
++ mmc_hostname(host->mmc));
++ bcm2835_sdhost_dumpregs(host);
++ host->cmd->error = -EIO;
++ tasklet_schedule(&host->finish_tasklet);
++ return;
++ }
++
++ if (host->flush_fifo) {
++ for (timeout = 100;
++ (bcm2835_sdhost_read(host, SDHSTS) & SDHSTS_DATA_FLAG) && timeout;
++ timeout--) {
++ (void)bcm2835_sdhost_read(host, SDDATA);
++ }
++ host->flush_fifo = 0;
++ if (timeout == 0) {
++ pr_err("%s: FIFO never drained.\n",
++ mmc_hostname(host->mmc));
++ bcm2835_sdhost_dumpregs(host);
++ host->cmd->error = -EIO;
++ tasklet_schedule(&host->finish_tasklet);
++ return;
++ }
++ }
++
++ /* Check for errors */
++ if (sdcmd & SDCMD_FAIL_FLAG)
++ {
++ u32 sdhsts = bcm2835_sdhost_read(host, SDHSTS);
++
++ if (host->debug)
++ pr_info("%s: error detected - CMD %x, HSTS %03x, EDM %x\n",
++ mmc_hostname(host->mmc), sdcmd, sdhsts,
++ bcm2835_sdhost_read(host, SDEDM));
++
++ if ((sdhsts & SDHSTS_CRC7_ERROR) &&
++ (host->cmd->opcode == 1)) {
++ if (host->debug)
++ pr_info("%s: ignoring CRC7 error for CMD1\n",
++ mmc_hostname(host->mmc));
++ } else {
++ if (sdhsts & SDHSTS_CMD_TIME_OUT) {
++ switch (host->cmd->opcode) {
++ case 5: case 52: case 53:
++ /* Don't warn about SDIO commands */
++ break;
++ default:
++ pr_err("%s: command timeout\n",
++ mmc_hostname(host->mmc));
++ break;
++ }
++ host->cmd->error = -ETIMEDOUT;
++ } else {
++ pr_err("%s: unexpected command error\n",
++ mmc_hostname(host->mmc));
++ bcm2835_sdhost_dumpregs(host);
++ host->cmd->error = -EIO;
++ }
++ tasklet_schedule(&host->finish_tasklet);
++ return;
++ }
++ }
++
++ if (host->cmd->flags & MMC_RSP_PRESENT) {
++ if (host->cmd->flags & MMC_RSP_136) {
++ int i;
++ for (i = 0; i < 4; i++)
++ host->cmd->resp[3 - i] = bcm2835_sdhost_read(host, SDRSP0 + i*4);
++ pr_debug("%s: finish_command %08x %08x %08x %08x\n",
++ mmc_hostname(host->mmc),
++ host->cmd->resp[0], host->cmd->resp[1], host->cmd->resp[2], host->cmd->resp[3]);
++ } else {
++ host->cmd->resp[0] = bcm2835_sdhost_read(host, SDRSP0);
++ pr_debug("%s: finish_command %08x\n",
++ mmc_hostname(host->mmc),
++ host->cmd->resp[0]);
++ }
++ }
++
++ host->cmd->error = 0;
++
++ if (host->cmd == host->mrq->sbc) {
++ /* Finished CMD23, now send actual command. */
++ host->cmd = NULL;
++ bcm2835_sdhost_send_command(host, host->mrq->cmd);
++
++ if (host->cmd->data && host->use_dma)
++ /* DMA transfer starts now, PIO starts after irq */
++ bcm2835_sdhost_transfer_dma(host);
++
++ if (!host->use_busy)
++ bcm2835_sdhost_finish_command(host);
++ } else if (host->cmd == host->mrq->stop)
++ /* Finished CMD12 */
++ tasklet_schedule(&host->finish_tasklet);
++ else {
++ /* Processed actual command. */
++ host->cmd = NULL;
++ if (!host->data)
++ tasklet_schedule(&host->finish_tasklet);
++ else if (host->data_complete)
++ bcm2835_sdhost_transfer_complete(host);
++ }
++}
++
++static void bcm2835_sdhost_timeout(unsigned long data)
++{
++ struct bcm2835_host *host;
++ unsigned long flags;
++
++ host = (struct bcm2835_host *)data;
++
++ spin_lock_irqsave(&host->lock, flags);
++
++ if (host->mrq) {
++ pr_err("%s: timeout waiting for hardware interrupt.\n",
++ mmc_hostname(host->mmc));
++ bcm2835_sdhost_dumpregs(host);
++
++ if (host->data) {
++ host->data->error = -ETIMEDOUT;
++ bcm2835_sdhost_finish_data(host);
++ } else {
++ if (host->cmd)
++ host->cmd->error = -ETIMEDOUT;
++ else
++ host->mrq->cmd->error = -ETIMEDOUT;
++
++ pr_debug("timeout_timer tasklet_schedule\n");
++ tasklet_schedule(&host->finish_tasklet);
++ }
++ }
++
++ mmiowb();
++ spin_unlock_irqrestore(&host->lock, flags);
++}
++
++static void bcm2835_sdhost_pio_timeout(unsigned long data)
++{
++ struct bcm2835_host *host;
++ unsigned long flags;
++
++ host = (struct bcm2835_host *)data;
++
++ spin_lock_irqsave(&host->lock, flags);
++
++ if (host->data) {
++ u32 sdhsts = bcm2835_sdhost_read(host, SDHSTS);
++
++ if (sdhsts & SDHSTS_REW_TIME_OUT) {
++ pr_err("%s: transfer timeout\n",
++ mmc_hostname(host->mmc));
++ if (host->debug)
++ bcm2835_sdhost_dumpregs(host);
++ } else {
++ pr_err("%s: unexpected transfer timeout\n",
++ mmc_hostname(host->mmc));
++ bcm2835_sdhost_dumpregs(host);
++ }
++
++ bcm2835_sdhost_write(host, SDHSTS_TRANSFER_ERROR_MASK,
++ SDHSTS);
++
++ host->data->error = -ETIMEDOUT;
++
++ bcm2835_sdhost_finish_data(host);
++ }
++
++ mmiowb();
++ spin_unlock_irqrestore(&host->lock, flags);
++}
++
++static void bcm2835_sdhost_enable_sdio_irq_nolock(struct bcm2835_host *host, int enable)
++{
++ if (enable)
++ host->hcfg |= SDHCFG_SDIO_IRPT_EN;
++ else
++ host->hcfg &= ~SDHCFG_SDIO_IRPT_EN;
++ bcm2835_sdhost_write(host, host->hcfg, SDHCFG);
++ mmiowb();
++}
++
++static void bcm2835_sdhost_enable_sdio_irq(struct mmc_host *mmc, int enable)
++{
++ struct bcm2835_host *host = mmc_priv(mmc);
++ unsigned long flags;
++
++ pr_debug("%s: enable_sdio_irq(%d)\n", mmc_hostname(mmc), enable);
++ spin_lock_irqsave(&host->lock, flags);
++ bcm2835_sdhost_enable_sdio_irq_nolock(host, enable);
++ spin_unlock_irqrestore(&host->lock, flags);
++}
++
++static u32 bcm2835_sdhost_busy_irq(struct bcm2835_host *host, u32 intmask)
++{
++ const u32 handled = (SDHSTS_REW_TIME_OUT | SDHSTS_CMD_TIME_OUT |
++ SDHSTS_CRC16_ERROR | SDHSTS_CRC7_ERROR |
++ SDHSTS_FIFO_ERROR);
++
++ if (!host->cmd) {
++ pr_err("%s: got command busy interrupt 0x%08x even "
++ "though no command operation was in progress.\n",
++ mmc_hostname(host->mmc), (unsigned)intmask);
++ bcm2835_sdhost_dumpregs(host);
++ return 0;
++ }
++
++ if (!host->use_busy) {
++ pr_err("%s: got command busy interrupt 0x%08x even "
++ "though not expecting one.\n",
++ mmc_hostname(host->mmc), (unsigned)intmask);
++ bcm2835_sdhost_dumpregs(host);
++ return 0;
++ }
++ host->use_busy = 0;
++
++ if (intmask & SDHSTS_ERROR_MASK)
++ {
++ pr_err("sdhost_busy_irq: intmask %x, data %p\n", intmask, host->mrq->data);
++ if (intmask & SDHSTS_CRC7_ERROR)
++ host->cmd->error = -EILSEQ;
++ else if (intmask & (SDHSTS_CRC16_ERROR |
++ SDHSTS_FIFO_ERROR)) {
++ if (host->mrq->data)
++ host->mrq->data->error = -EILSEQ;
++ else
++ host->cmd->error = -EILSEQ;
++ } else if (intmask & SDHSTS_REW_TIME_OUT) {
++ if (host->mrq->data)
++ host->mrq->data->error = -ETIMEDOUT;
++ else
++ host->cmd->error = -ETIMEDOUT;
++ } else if (intmask & SDHSTS_CMD_TIME_OUT)
++ host->cmd->error = -ETIMEDOUT;
++
++ bcm2835_sdhost_dumpregs(host);
++ tasklet_schedule(&host->finish_tasklet);
++ }
++ else
++ bcm2835_sdhost_finish_command(host);
++
++ return handled;
++}
++
++static u32 bcm2835_sdhost_data_irq(struct bcm2835_host *host, u32 intmask)
++{
++ const u32 handled = (SDHSTS_REW_TIME_OUT |
++ SDHSTS_CRC16_ERROR |
++ SDHSTS_FIFO_ERROR);
++
++ /* There are no dedicated data/space available interrupt
++ status bits, so it is necessary to use the single shared
++ data/space available FIFO status bits. It is therefore not
++ an error to get here when there is no data transfer in
++ progress. */
++ if (!host->data)
++ return 0;
++
++ if (intmask & (SDHSTS_CRC16_ERROR |
++ SDHSTS_FIFO_ERROR |
++ SDHSTS_REW_TIME_OUT)) {
++ if (intmask & (SDHSTS_CRC16_ERROR |
++ SDHSTS_FIFO_ERROR))
++ host->data->error = -EILSEQ;
++ else
++ host->data->error = -ETIMEDOUT;
++
++ bcm2835_sdhost_dumpregs(host);
++ tasklet_schedule(&host->finish_tasklet);
++ return handled;
++ }
++
++ /* Use the block interrupt for writes after the first block */
++ if (host->data->flags & MMC_DATA_WRITE) {
++ host->hcfg &= ~(SDHCFG_DATA_IRPT_EN);
++ host->hcfg |= SDHCFG_BLOCK_IRPT_EN;
++ bcm2835_sdhost_write(host, host->hcfg, SDHCFG);
++ if (host->data->error)
++ bcm2835_sdhost_finish_data(host);
++ else
++ bcm2835_sdhost_transfer_pio(host);
++ } else {
++ if (!host->data->error) {
++ bcm2835_sdhost_transfer_pio(host);
++ host->blocks--;
++ }
++ if ((host->blocks == 0) || host->data->error)
++ bcm2835_sdhost_finish_data(host);
++ }
++
++ return handled;
++}
++
++static u32 bcm2835_sdhost_block_irq(struct bcm2835_host *host, u32 intmask)
++{
++ struct dma_chan *dma_chan;
++ u32 dir_data;
++ const u32 handled = (SDHSTS_REW_TIME_OUT |
++ SDHSTS_CRC16_ERROR |
++ SDHSTS_FIFO_ERROR);
++
++ if (!host->data) {
++ pr_err("%s: got block interrupt 0x%08x even "
++ "though no data operation was in progress.\n",
++ mmc_hostname(host->mmc), (unsigned)intmask);
++ bcm2835_sdhost_dumpregs(host);
++ return handled;
++ }
++
++ if (intmask & (SDHSTS_CRC16_ERROR |
++ SDHSTS_FIFO_ERROR |
++ SDHSTS_REW_TIME_OUT)) {
++ if (intmask & (SDHSTS_CRC16_ERROR |
++ SDHSTS_FIFO_ERROR))
++ host->data->error = -EILSEQ;
++ else
++ host->data->error = -ETIMEDOUT;
++
++ if (host->debug)
++ bcm2835_sdhost_dumpregs(host);
++ tasklet_schedule(&host->finish_tasklet);
++ return handled;
++ }
++
++ if (!host->use_dma) {
++ BUG_ON(!host->blocks);
++ host->blocks--;
++ if ((host->blocks == 0) || host->data->error) {
++ /* Cancel the timer */
++ del_timer(&host->pio_timer);
++
++ bcm2835_sdhost_finish_data(host);
++ } else {
++ bcm2835_sdhost_transfer_pio(host);
++
++ /* Reset the timer */
++ mod_timer(&host->pio_timer,
++ jiffies + host->pio_timeout);
++ }
++ } else if (host->data->flags & MMC_DATA_WRITE) {
++ dma_chan = host->dma_chan_tx;
++ dir_data = DMA_TO_DEVICE;
++ dma_unmap_sg(dma_chan->device->dev,
++ host->data->sg, host->data->sg_len,
++ dir_data);
++
++ bcm2835_sdhost_finish_data(host);
++ }
++
++ return handled;
++}
++
++
++static irqreturn_t bcm2835_sdhost_irq(int irq, void *dev_id)
++{
++ irqreturn_t result = IRQ_NONE;
++ struct bcm2835_host *host = dev_id;
++ u32 unexpected = 0, early = 0;
++ int loops = 0;
++#ifndef CONFIG_ARCH_BCM2835
++ int cardint = 0;
++#endif
++ spin_lock(&host->lock);
++
++ for (loops = 0; loops < 1; loops++) {
++ u32 intmask, handled;
++
++ intmask = bcm2835_sdhost_read(host, SDHSTS);
++ handled = intmask & (SDHSTS_BUSY_IRPT |
++ SDHSTS_BLOCK_IRPT |
++ SDHSTS_SDIO_IRPT |
++ SDHSTS_DATA_FLAG);
++ if ((handled == SDHSTS_DATA_FLAG) &&
++ (loops == 0) && !host->data) {
++ pr_err("%s: sdhost_irq data interrupt 0x%08x even "
++ "though no data operation was in progress.\n",
++ mmc_hostname(host->mmc),
++ (unsigned)intmask);
++
++ bcm2835_sdhost_dumpregs(host);
++ }
++
++ if (!handled)
++ break;
++
++ if (loops)
++ early |= handled;
++
++ result = IRQ_HANDLED;
++
++ /* Clear all interrupts and notifications */
++ bcm2835_sdhost_write(host, intmask, SDHSTS);
++
++ if (intmask & SDHSTS_BUSY_IRPT)
++ handled |= bcm2835_sdhost_busy_irq(host, intmask);
++
++ /* There is no true data interrupt status bit, so it is
++ necessary to qualify the data flag with the interrupt
++ enable bit */
++ if ((intmask & SDHSTS_DATA_FLAG) &&
++ (host->hcfg & SDHCFG_DATA_IRPT_EN))
++ handled |= bcm2835_sdhost_data_irq(host, intmask);
++
++ if (intmask & SDHSTS_BLOCK_IRPT)
++ handled |= bcm2835_sdhost_block_irq(host, intmask);
++
++ if (intmask & SDHSTS_SDIO_IRPT) {
++#ifndef CONFIG_ARCH_BCM2835
++ cardint = 1;
++#else
++ bcm2835_sdhost_enable_sdio_irq_nolock(host, false);
++ host->thread_isr |= SDHSTS_SDIO_IRPT;
++ result = IRQ_WAKE_THREAD;
++#endif
++ }
++
++ unexpected |= (intmask & ~handled);
++ }
++
++ mmiowb();
++
++ spin_unlock(&host->lock);
++
++ if (early)
++ pr_debug("%s: early %x (loops %d)\n",
++ mmc_hostname(host->mmc), early, loops);
++
++ if (unexpected) {
++ pr_err("%s: unexpected interrupt 0x%08x.\n",
++ mmc_hostname(host->mmc), unexpected);
++ bcm2835_sdhost_dumpregs(host);
++ }
++
++#ifndef CONFIG_ARCH_BCM2835
++ if (cardint)
++ mmc_signal_sdio_irq(host->mmc);
++#endif
++
++ return result;
++}
++
++#ifdef CONFIG_ARCH_BCM2835
++static irqreturn_t bcm2835_sdhost_thread_irq(int irq, void *dev_id)
++{
++ struct bcm2835_host *host = dev_id;
++ unsigned long flags;
++ u32 isr;
++
++ spin_lock_irqsave(&host->lock, flags);
++ isr = host->thread_isr;
++ host->thread_isr = 0;
++ spin_unlock_irqrestore(&host->lock, flags);
++
++ if (isr & SDHSTS_SDIO_IRPT) {
++ sdio_run_irqs(host->mmc);
++
++/* Is this necessary? Why re-enable an interrupt which is enabled?
++ spin_lock_irqsave(&host->lock, flags);
++ if (host->flags & SDHSTS_SDIO_IRPT_ENABLED)
++ bcm2835_sdhost_enable_sdio_irq_nolock(host, true);
++ spin_unlock_irqrestore(&host->lock, flags);
++*/
++ }
++
++ return isr ? IRQ_HANDLED : IRQ_NONE;
++}
++#endif
++
++
++
++void bcm2835_sdhost_set_clock(struct bcm2835_host *host, unsigned int clock)
++{
++ int div = 0; /* Initialized for compiler warning */
++ unsigned int input_clock = clock;
++
++ if (host->debug)
++ pr_info("%s: set_clock(%d)\n", mmc_hostname(host->mmc), clock);
++
++ if ((host->overclock_50 > 50) &&
++ (clock == 50*MHZ)) {
++ clock = host->overclock_50 * MHZ + (MHZ - 1);
++ }
++
++ /* The SDCDIV register has 11 bits, and holds (div - 2).
++ But in data mode the max is 50MHz wihout a minimum, and only the
++ bottom 3 bits are used. Since the switch over is automatic (unless
++ we have marked the card as slow...), chosen values have to make
++ sense in both modes.
++ Ident mode must be 100-400KHz, so can range check the requested
++ clock. CMD15 must be used to return to data mode, so this can be
++ monitored.
++
++ clock 250MHz -> 0->125MHz, 1->83.3MHz, 2->62.5MHz, 3->50.0MHz
++ 4->41.7MHz, 5->35.7MHz, 6->31.3MHz, 7->27.8MHz
++
++ 623->400KHz/27.8MHz
++ reset value (507)->491159/50MHz
++
++ BUT, the 3-bit clock divisor in data mode is too small if the
++ core clock is higher than 250MHz, so instead use the SLOW_CARD
++ configuration bit to force the use of the ident clock divisor
++ at all times.
++ */
++
++ host->mmc->actual_clock = 0;
++
++ if (clock < 100000) {
++ /* Can't stop the clock, but make it as slow as possible
++ * to show willing
++ */
++ host->cdiv = SDCDIV_MAX_CDIV;
++ bcm2835_sdhost_write(host, host->cdiv, SDCDIV);
++ return;
++ }
++
++ div = host->max_clk / clock;
++ if (div < 2)
++ div = 2;
++ if ((host->max_clk / div) > clock)
++ div++;
++ div -= 2;
++
++ if (div > SDCDIV_MAX_CDIV)
++ div = SDCDIV_MAX_CDIV;
++
++ clock = host->max_clk / (div + 2);
++ host->mmc->actual_clock = clock;
++
++ if (clock > input_clock) {
++ /* Save the closest value, to make it easier
++ to reduce in the event of error */
++ host->overclock_50 = (clock/MHZ);
++
++ if (clock != host->overclock) {
++ pr_warn("%s: overclocking to %dHz\n",
++ mmc_hostname(host->mmc), clock);
++ host->overclock = clock;
++ }
++ }
++ else if (host->overclock)
++ {
++ host->overclock = 0;
++ if (clock == 50 * MHZ)
++ pr_warn("%s: cancelling overclock\n",
++ mmc_hostname(host->mmc));
++ }
++
++ host->cdiv = div;
++ bcm2835_sdhost_write(host, host->cdiv, SDCDIV);
++
++ /* Set the timeout to 500ms */
++ bcm2835_sdhost_write(host, host->mmc->actual_clock/2, SDTOUT);
++
++ if (host->debug)
++ pr_info("%s: clock=%d -> max_clk=%d, cdiv=%x (actual clock %d)\n",
++ mmc_hostname(host->mmc), input_clock,
++ host->max_clk, host->cdiv, host->mmc->actual_clock);
++}
++
++static void bcm2835_sdhost_request(struct mmc_host *mmc, struct mmc_request *mrq)
++{
++ struct bcm2835_host *host;
++ unsigned long flags;
++
++ host = mmc_priv(mmc);
++
++ if (host->debug) {
++ struct mmc_command *cmd = mrq->cmd;
++ BUG_ON(!cmd);
++ if (cmd->data)
++ pr_info("%s: cmd %d 0x%x (flags 0x%x) - %s %d*%d\n",
++ mmc_hostname(mmc),
++ cmd->opcode, cmd->arg, cmd->flags,
++ (cmd->data->flags & MMC_DATA_READ) ?
++ "read" : "write", cmd->data->blocks,
++ cmd->data->blksz);
++ else
++ pr_info("%s: cmd %d 0x%x (flags 0x%x)\n",
++ mmc_hostname(mmc),
++ cmd->opcode, cmd->arg, cmd->flags);
++ }
++
++ /* Reset the error statuses in case this is a retry */
++ if (mrq->cmd)
++ mrq->cmd->error = 0;
++ if (mrq->data)
++ mrq->data->error = 0;
++ if (mrq->stop)
++ mrq->stop->error = 0;
++
++ if (mrq->data && !is_power_of_2(mrq->data->blksz)) {
++ pr_err("%s: unsupported block size (%d bytes)\n",
++ mmc_hostname(mmc), mrq->data->blksz);
++ mrq->cmd->error = -EINVAL;
++ mmc_request_done(mmc, mrq);
++ return;
++ }
++
++ spin_lock_irqsave(&host->lock, flags);
++
++ WARN_ON(host->mrq != NULL);
++
++ host->mrq = mrq;
++
++ if (mrq->sbc)
++ bcm2835_sdhost_send_command(host, mrq->sbc);
++ else
++ bcm2835_sdhost_send_command(host, mrq->cmd);
++
++ mmiowb();
++ spin_unlock_irqrestore(&host->lock, flags);
++
++ if (!mrq->sbc && mrq->cmd->data && host->use_dma)
++ /* DMA transfer starts now, PIO starts after irq */
++ bcm2835_sdhost_transfer_dma(host);
++
++ if (!host->use_busy)
++ bcm2835_sdhost_finish_command(host);
++}
++
++
++static void bcm2835_sdhost_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
++{
++
++ struct bcm2835_host *host = mmc_priv(mmc);
++ unsigned long flags;
++
++ if (host->debug)
++ pr_info("%s: ios clock %d, pwr %d, bus_width %d, "
++ "timing %d, vdd %d, drv_type %d\n",
++ mmc_hostname(mmc),
++ ios->clock, ios->power_mode, ios->bus_width,
++ ios->timing, ios->signal_voltage, ios->drv_type);
++
++ spin_lock_irqsave(&host->lock, flags);
++
++ if (!ios->clock || ios->clock != host->clock) {
++ bcm2835_sdhost_set_clock(host, ios->clock);
++ host->clock = ios->clock;
++ }
++
++ /* set bus width */
++ host->hcfg &= ~SDHCFG_WIDE_EXT_BUS;
++ if (ios->bus_width == MMC_BUS_WIDTH_4)
++ host->hcfg |= SDHCFG_WIDE_EXT_BUS;
++
++ host->hcfg |= SDHCFG_WIDE_INT_BUS;
++
++ /* Disable clever clock switching, to cope with fast core clocks */
++ host->hcfg |= SDHCFG_SLOW_CARD;
++
++ bcm2835_sdhost_write(host, host->hcfg, SDHCFG);
++
++ mmiowb();
++
++ spin_unlock_irqrestore(&host->lock, flags);
++}
++
++static int bcm2835_sdhost_multi_io_quirk(struct mmc_card *card,
++ unsigned int direction,
++ u32 blk_pos, int blk_size)
++{
++ /* There is a bug in the host controller hardware that makes
++ reading the final sector of the card as part of a multiple read
++ problematic. Detect that case and shorten the read accordingly.
++ */
++ /* csd.capacity is in weird units - convert to sectors */
++ u32 card_sectors = (card->csd.capacity << (card->csd.read_blkbits - 9));
++
++ if ((direction == MMC_DATA_READ) &&
++ ((blk_pos + blk_size) == card_sectors))
++ blk_size--;
++
++ return blk_size;
++}
++
++
++static struct mmc_host_ops bcm2835_sdhost_ops = {
++ .request = bcm2835_sdhost_request,
++ .set_ios = bcm2835_sdhost_set_ios,
++ .enable_sdio_irq = bcm2835_sdhost_enable_sdio_irq,
++ .hw_reset = bcm2835_sdhost_reset,
++ .multi_io_quirk = bcm2835_sdhost_multi_io_quirk,
++};
++
++
++static void bcm2835_sdhost_tasklet_finish(unsigned long param)
++{
++ struct bcm2835_host *host;
++ unsigned long flags;
++ struct mmc_request *mrq;
++
++ host = (struct bcm2835_host *)param;
++
++ spin_lock_irqsave(&host->lock, flags);
++
++ /*
++ * If this tasklet gets rescheduled while running, it will
++ * be run again afterwards but without any active request.
++ */
++ if (!host->mrq) {
++ spin_unlock_irqrestore(&host->lock, flags);
++ return;
++ }
++
++ del_timer(&host->timer);
++
++ mrq = host->mrq;
++
++ /* Drop the overclock after any data corruption, or after any
++ error overclocked */
++ if (host->overclock) {
++ if ((mrq->cmd && mrq->cmd->error) ||
++ (mrq->data && mrq->data->error) ||
++ (mrq->stop && mrq->stop->error)) {
++ host->overclock_50--;
++ pr_warn("%s: reducing overclock due to errors\n",
++ mmc_hostname(host->mmc));
++ bcm2835_sdhost_set_clock(host,50*MHZ);
++ mrq->cmd->error = -EILSEQ;
++ mrq->cmd->retries = 1;
++ }
++ }
++
++ host->mrq = NULL;
++ host->cmd = NULL;
++ host->data = NULL;
++
++ mmiowb();
++
++ spin_unlock_irqrestore(&host->lock, flags);
++ mmc_request_done(host->mmc, mrq);
++}
++
++
++
++int bcm2835_sdhost_add_host(struct bcm2835_host *host)
++{
++ struct mmc_host *mmc;
++ struct dma_slave_config cfg;
++ char pio_limit_string[20];
++ int ret;
++
++ mmc = host->mmc;
++
++ bcm2835_sdhost_reset_internal(host);
++
++ mmc->f_max = host->max_clk;
++ mmc->f_min = host->max_clk / SDCDIV_MAX_CDIV;
++
++ mmc->max_busy_timeout = (~(unsigned int)0)/(mmc->f_max/1000);
++
++ pr_debug("f_max %d, f_min %d, max_busy_timeout %d\n",
++ mmc->f_max, mmc->f_min, mmc->max_busy_timeout);
++
++ /* host controller capabilities */
++ mmc->caps |= /* MMC_CAP_SDIO_IRQ |*/ MMC_CAP_4_BIT_DATA |
++ MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED |
++ MMC_CAP_NEEDS_POLL | MMC_CAP_HW_RESET | MMC_CAP_ERASE |
++ (ALLOW_CMD23 * MMC_CAP_CMD23);
++
++ spin_lock_init(&host->lock);
++
++ if (host->allow_dma) {
++ if (IS_ERR_OR_NULL(host->dma_chan_tx) ||
++ IS_ERR_OR_NULL(host->dma_chan_rx)) {
++ pr_err("%s: unable to initialise DMA channels. "
++ "Falling back to PIO\n",
++ mmc_hostname(mmc));
++ host->have_dma = false;
++ } else {
++ host->have_dma = true;
++
++ cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
++ cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
++ cfg.slave_id = 13; /* DREQ channel */
++
++ cfg.direction = DMA_MEM_TO_DEV;
++ cfg.src_addr = 0;
++ cfg.dst_addr = host->phys_addr + SDDATA;
++ ret = dmaengine_slave_config(host->dma_chan_tx, &cfg);
++
++ cfg.direction = DMA_DEV_TO_MEM;
++ cfg.src_addr = host->phys_addr + SDDATA;
++ cfg.dst_addr = 0;
++ ret = dmaengine_slave_config(host->dma_chan_rx, &cfg);
++ }
++ } else {
++ host->have_dma = false;
++ }
++
++ mmc->max_segs = 128;
++ mmc->max_req_size = 524288;
++ mmc->max_seg_size = mmc->max_req_size;
++ mmc->max_blk_size = 512;
++ mmc->max_blk_count = 65535;
++
++ /* report supported voltage ranges */
++ mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
++
++ tasklet_init(&host->finish_tasklet,
++ bcm2835_sdhost_tasklet_finish, (unsigned long)host);
++
++ setup_timer(&host->timer, bcm2835_sdhost_timeout,
++ (unsigned long)host);
++
++ setup_timer(&host->pio_timer, bcm2835_sdhost_pio_timeout,
++ (unsigned long)host);
++
++ bcm2835_sdhost_init(host, 0);
++#ifndef CONFIG_ARCH_BCM2835
++ ret = request_irq(host->irq, bcm2835_sdhost_irq, 0 /*IRQF_SHARED*/,
++ mmc_hostname(mmc), host);
++#else
++ ret = request_threaded_irq(host->irq, bcm2835_sdhost_irq,
++ bcm2835_sdhost_thread_irq,
++ IRQF_SHARED, mmc_hostname(mmc), host);
++#endif
++ if (ret) {
++ pr_err("%s: failed to request IRQ %d: %d\n",
++ mmc_hostname(mmc), host->irq, ret);
++ goto untasklet;
++ }
++
++ mmiowb();
++ mmc_add_host(mmc);
++
++ pio_limit_string[0] = '\0';
++ if (host->have_dma && (host->pio_limit > 0))
++ sprintf(pio_limit_string, " (>%d)", host->pio_limit);
++ pr_info("%s: %s loaded - DMA %s%s\n",
++ mmc_hostname(mmc), DRIVER_NAME,
++ host->have_dma ? "enabled" : "disabled",
++ pio_limit_string);
++
++ return 0;
++
++untasklet:
++ tasklet_kill(&host->finish_tasklet);
++
++ return ret;
++}
++
++static int bcm2835_sdhost_probe(struct platform_device *pdev)
++{
++ struct device *dev = &pdev->dev;
++ struct device_node *node = dev->of_node;
++ struct clk *clk;
++ struct resource *iomem;
++ struct bcm2835_host *host;
++ struct mmc_host *mmc;
++ int ret;
++
++ pr_debug("bcm2835_sdhost_probe\n");
++ mmc = mmc_alloc_host(sizeof(*host), dev);
++ if (!mmc)
++ return -ENOMEM;
++
++ mmc->ops = &bcm2835_sdhost_ops;
++ host = mmc_priv(mmc);
++ host->mmc = mmc;
++ host->pio_timeout = msecs_to_jiffies(500);
++ host->max_delay = 1; /* Warn if over 1ms */
++ spin_lock_init(&host->lock);
++
++ iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ host->ioaddr = devm_ioremap_resource(dev, iomem);
++ if (IS_ERR(host->ioaddr)) {
++ ret = PTR_ERR(host->ioaddr);
++ goto err;
++ }
++
++ host->phys_addr = iomem->start + BCM2835_VCMMU_SHIFT;
++ pr_debug(" - ioaddr %lx, iomem->start %lx, phys_addr %lx\n",
++ (unsigned long)host->ioaddr,
++ (unsigned long)iomem->start,
++ (unsigned long)host->phys_addr);
++
++ host->allow_dma = ALLOW_DMA;
++
++ if (node) {
++ /* Read any custom properties */
++ of_property_read_u32(node,
++ "brcm,delay-after-stop",
++ &host->delay_after_stop);
++ of_property_read_u32(node,
++ "brcm,overclock-50",
++ &host->overclock_50);
++ of_property_read_u32(node,
++ "brcm,pio-limit",
++ &host->pio_limit);
++ host->allow_dma = ALLOW_DMA &&
++ !of_property_read_bool(node, "brcm,force-pio");
++ host->debug = of_property_read_bool(node, "brcm,debug");
++ }
++
++ if (host->allow_dma) {
++ if (node) {
++ host->dma_chan_tx =
++ dma_request_slave_channel(dev, "tx");
++ host->dma_chan_rx =
++ dma_request_slave_channel(dev, "rx");
++ } else {
++ dma_cap_mask_t mask;
++
++ dma_cap_zero(mask);
++ /* we don't care about the channel, any would work */
++ dma_cap_set(DMA_SLAVE, mask);
++ host->dma_chan_tx =
++ dma_request_channel(mask, NULL, NULL);
++ host->dma_chan_rx =
++ dma_request_channel(mask, NULL, NULL);
++ }
++ }
++
++ clk = devm_clk_get(dev, NULL);
++ if (IS_ERR(clk)) {
++ dev_err(dev, "could not get clk\n");
++ ret = PTR_ERR(clk);
++ goto err;
++ }
++
++ host->max_clk = clk_get_rate(clk);
++
++ host->irq = platform_get_irq(pdev, 0);
++ if (host->irq <= 0) {
++ dev_err(dev, "get IRQ failed\n");
++ ret = -EINVAL;
++ goto err;
++ }
++
++ pr_debug(" - max_clk %lx, irq %d\n",
++ (unsigned long)host->max_clk,
++ (int)host->irq);
++
++ if (node)
++ mmc_of_parse(mmc);
++ else
++ mmc->caps |= MMC_CAP_4_BIT_DATA;
++
++ ret = bcm2835_sdhost_add_host(host);
++ if (ret)
++ goto err;
++
++ platform_set_drvdata(pdev, host);
++
++ pr_debug("bcm2835_sdhost_probe -> OK\n");
++
++ return 0;
++
++err:
++ pr_debug("bcm2835_sdhost_probe -> err %d\n", ret);
++ mmc_free_host(mmc);
++
++ return ret;
++}
++
++static int bcm2835_sdhost_remove(struct platform_device *pdev)
++{
++ struct bcm2835_host *host = platform_get_drvdata(pdev);
++
++ pr_debug("bcm2835_sdhost_remove\n");
++
++ mmc_remove_host(host->mmc);
++
++ bcm2835_sdhost_set_power(host, false);
++
++ free_irq(host->irq, host);
++
++ del_timer_sync(&host->timer);
++
++ tasklet_kill(&host->finish_tasklet);
++
++ mmc_free_host(host->mmc);
++ platform_set_drvdata(pdev, NULL);
++
++ pr_debug("bcm2835_sdhost_remove - OK\n");
++ return 0;
++}
++
++
++static const struct of_device_id bcm2835_sdhost_match[] = {
++ { .compatible = "brcm,bcm2835-sdhost" },
++ { }
++};
++MODULE_DEVICE_TABLE(of, bcm2835_sdhost_match);
++
++
++
++static struct platform_driver bcm2835_sdhost_driver = {
++ .probe = bcm2835_sdhost_probe,
++ .remove = bcm2835_sdhost_remove,
++ .driver = {
++ .name = DRIVER_NAME,
++ .owner = THIS_MODULE,
++ .of_match_table = bcm2835_sdhost_match,
++ },
++};
++module_platform_driver(bcm2835_sdhost_driver);
++
++MODULE_ALIAS("platform:sdhost-bcm2835");
++MODULE_DESCRIPTION("BCM2835 SDHost driver");
++MODULE_LICENSE("GPL v2");
++MODULE_AUTHOR("Phil Elwell");
+diff -Nur linux-4.1.3/drivers/mmc/host/Kconfig linux-xbian-rpi/drivers/mmc/host/Kconfig
+--- linux-4.1.3/drivers/mmc/host/Kconfig 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/mmc/host/Kconfig 2015-07-28 01:20:58.289711085 +0200
+@@ -4,6 +4,45 @@
+
+ comment "MMC/SD/SDIO Host Controller Drivers"
+
++config MMC_BCM2835
++ tristate "MMC support on BCM2835"
++ depends on MACH_BCM2708 || MACH_BCM2709 || ARCH_BCM2835
++ help
++ This selects the MMC Interface on BCM2835.
++
++ If you have a controller with this interface, say Y or M here.
++
++ If unsure, say N.
++
++config MMC_BCM2835_DMA
++ bool "DMA support on BCM2835 Arasan controller"
++ depends on MMC_BCM2835
++ help
++ Enable DMA support on the Arasan SDHCI controller in Broadcom 2708
++ based chips.
++
++ If unsure, say N.
++
++config MMC_BCM2835_PIO_DMA_BARRIER
++ int "Block count limit for PIO transfers"
++ depends on MMC_BCM2835 && MMC_BCM2835_DMA
++ range 0 256
++ default 2
++ help
++ The inclusive limit in bytes under which PIO will be used instead of DMA
++
++ If unsure, say 2 here.
++
++config MMC_BCM2835_SDHOST
++ tristate "Support for the SDHost controller on BCM2708/9"
++ depends on MACH_BCM2708 || MACH_BCM2709 || ARCH_BCM2835
++ help
++ This selects the SDHost controller on BCM2835/6.
++
++ If you have a controller with this interface, say Y or M here.
++
++ If unsure, say N.
++
+ config MMC_ARMMMCI
+ tristate "ARM AMBA Multimedia Card Interface support"
+ depends on ARM_AMBA
+diff -Nur linux-4.1.3/drivers/mmc/host/Makefile linux-xbian-rpi/drivers/mmc/host/Makefile
+--- linux-4.1.3/drivers/mmc/host/Makefile 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/mmc/host/Makefile 2015-07-28 01:20:58.289711085 +0200
+@@ -18,6 +18,8 @@
+ obj-$(CONFIG_MMC_SDHCI_SIRF) += sdhci-sirf.o
+ obj-$(CONFIG_MMC_SDHCI_F_SDH30) += sdhci_f_sdh30.o
+ obj-$(CONFIG_MMC_SDHCI_SPEAR) += sdhci-spear.o
++obj-$(CONFIG_MMC_BCM2835_SDHOST) += bcm2835-sdhost.o
++obj-$(CONFIG_MMC_BCM2835) += bcm2835-mmc.o
+ obj-$(CONFIG_MMC_WBSD) += wbsd.o
+ obj-$(CONFIG_MMC_AU1X) += au1xmmc.o
+ obj-$(CONFIG_MMC_OMAP) += omap.o
+diff -Nur linux-4.1.3/drivers/mmc/host/omap_hsmmc.c linux-xbian-rpi/drivers/mmc/host/omap_hsmmc.c
+--- linux-4.1.3/drivers/mmc/host/omap_hsmmc.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/mmc/host/omap_hsmmc.c 2015-07-28 01:20:58.289711085 +0200
+@@ -1749,7 +1749,9 @@
+ }
+
+ static int omap_hsmmc_multi_io_quirk(struct mmc_card *card,
+- unsigned int direction, int blk_size)
++ unsigned int direction,
++ u32 blk_pos,
++ int blk_size)
+ {
+ /* This controller can't do multiblock reads due to hw bugs */
+ if (direction == MMC_DATA_READ)
+diff -Nur linux-4.1.3/drivers/mmc/host/sh_mobile_sdhi.c linux-xbian-rpi/drivers/mmc/host/sh_mobile_sdhi.c
+--- linux-4.1.3/drivers/mmc/host/sh_mobile_sdhi.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/mmc/host/sh_mobile_sdhi.c 2015-07-28 01:20:58.289711085 +0200
+@@ -170,7 +170,9 @@
+ }
+
+ static int sh_mobile_sdhi_multi_io_quirk(struct mmc_card *card,
+- unsigned int direction, int blk_size)
++ unsigned int direction,
++ u32 blk_pos,
++ int blk_size)
+ {
+ /*
+ * In Renesas controllers, when performing a
+diff -Nur linux-4.1.3/drivers/mmc/host/tmio_mmc_pio.c linux-xbian-rpi/drivers/mmc/host/tmio_mmc_pio.c
+--- linux-4.1.3/drivers/mmc/host/tmio_mmc_pio.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/mmc/host/tmio_mmc_pio.c 2015-07-28 01:20:58.289711085 +0200
+@@ -1001,7 +1001,9 @@
+ }
+
+ static int tmio_multi_io_quirk(struct mmc_card *card,
+- unsigned int direction, int blk_size)
++ unsigned int direction,
++ u32 blk_pos,
++ int blk_size)
+ {
+ struct tmio_mmc_host *host = mmc_priv(card->host);
+
+diff -Nur linux-4.1.3/drivers/net/ethernet/microchip/enc28j60.c linux-xbian-rpi/drivers/net/ethernet/microchip/enc28j60.c
+--- linux-4.1.3/drivers/net/ethernet/microchip/enc28j60.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/net/ethernet/microchip/enc28j60.c 2015-07-28 01:20:58.293696864 +0200
+@@ -1630,10 +1630,21 @@
+ return 0;
+ }
+
++#ifdef CONFIG_OF
++static const struct of_device_id enc28j60_of_match[] = {
++ { .compatible = "microchip,enc28j60", },
++ { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, enc28j60_of_match);
++#endif
++
+ static struct spi_driver enc28j60_driver = {
+ .driver = {
+ .name = DRV_NAME,
+ .owner = THIS_MODULE,
++#ifdef CONFIG_OF
++ .of_match_table = enc28j60_of_match,
++#endif
+ },
+ .probe = enc28j60_probe,
+ .remove = enc28j60_remove,
+diff -Nur linux-4.1.3/drivers/net/usb/smsc95xx.c linux-xbian-rpi/drivers/net/usb/smsc95xx.c
+--- linux-4.1.3/drivers/net/usb/smsc95xx.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/net/usb/smsc95xx.c 2015-07-28 01:20:58.293696864 +0200
+@@ -59,6 +59,7 @@
+ #define SUSPEND_SUSPEND3 (0x08)
+ #define SUSPEND_ALLMODES (SUSPEND_SUSPEND0 | SUSPEND_SUSPEND1 | \
+ SUSPEND_SUSPEND2 | SUSPEND_SUSPEND3)
++#define MAC_ADDR_LEN (6)
+
+ struct smsc95xx_priv {
+ u32 mac_cr;
+@@ -70,10 +71,14 @@
+ u8 suspend_flags;
+ };
+
+-static bool turbo_mode = true;
++static bool turbo_mode = false;
+ module_param(turbo_mode, bool, 0644);
+ MODULE_PARM_DESC(turbo_mode, "Enable multiple frames per Rx transaction");
+
++static char *macaddr = ":";
++module_param(macaddr, charp, 0);
++MODULE_PARM_DESC(macaddr, "MAC address");
++
+ static int __must_check __smsc95xx_read_reg(struct usbnet *dev, u32 index,
+ u32 *data, int in_pm)
+ {
+@@ -763,8 +768,59 @@
+ return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
+ }
+
++/* Check the macaddr module parameter for a MAC address */
++static int smsc95xx_is_macaddr_param(struct usbnet *dev, u8 *dev_mac)
++{
++ int i, j, got_num, num;
++ u8 mtbl[MAC_ADDR_LEN];
++
++ if (macaddr[0] == ':')
++ return 0;
++
++ i = 0;
++ j = 0;
++ num = 0;
++ got_num = 0;
++ while (j < MAC_ADDR_LEN) {
++ if (macaddr[i] && macaddr[i] != ':') {
++ got_num++;
++ if ('0' <= macaddr[i] && macaddr[i] <= '9')
++ num = num * 16 + macaddr[i] - '0';
++ else if ('A' <= macaddr[i] && macaddr[i] <= 'F')
++ num = num * 16 + 10 + macaddr[i] - 'A';
++ else if ('a' <= macaddr[i] && macaddr[i] <= 'f')
++ num = num * 16 + 10 + macaddr[i] - 'a';
++ else
++ break;
++ i++;
++ } else if (got_num == 2) {
++ mtbl[j++] = (u8) num;
++ num = 0;
++ got_num = 0;
++ i++;
++ } else {
++ break;
++ }
++ }
++
++ if (j == MAC_ADDR_LEN) {
++ netif_dbg(dev, ifup, dev->net, "Overriding MAC address with: "
++ "%02x:%02x:%02x:%02x:%02x:%02x\n", mtbl[0], mtbl[1], mtbl[2],
++ mtbl[3], mtbl[4], mtbl[5]);
++ for (i = 0; i < MAC_ADDR_LEN; i++)
++ dev_mac[i] = mtbl[i];
++ return 1;
++ } else {
++ return 0;
++ }
++}
++
+ static void smsc95xx_init_mac_address(struct usbnet *dev)
+ {
++ /* Check module parameters */
++ if (smsc95xx_is_macaddr_param(dev, dev->net->dev_addr))
++ return;
++
+ /* try reading mac address from EEPROM */
+ if (smsc95xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN,
+ dev->net->dev_addr) == 0) {
+@@ -1086,6 +1142,12 @@
+ return 0;
+ }
+
++#ifdef CONFIG_NET_POLL_CONTROLLER
++static void smsc95xx_poll_dummy(struct net_device *netdev)
++{
++}
++#endif
++
+ static const struct net_device_ops smsc95xx_netdev_ops = {
+ .ndo_open = usbnet_open,
+ .ndo_stop = usbnet_stop,
+@@ -1097,6 +1159,9 @@
+ .ndo_do_ioctl = smsc95xx_ioctl,
+ .ndo_set_rx_mode = smsc95xx_set_multicast,
+ .ndo_set_features = smsc95xx_set_features,
++#ifdef CONFIG_NET_POLL_CONTROLLER
++ .ndo_poll_controller = smsc95xx_poll_dummy,
++#endif
+ };
+
+ static int smsc95xx_bind(struct usbnet *dev, struct usb_interface *intf)
+@@ -1785,7 +1850,6 @@
+ if (dev->net->features & NETIF_F_RXCSUM)
+ smsc95xx_rx_csum_offload(skb);
+ skb_trim(skb, skb->len - 4); /* remove fcs */
+- skb->truesize = size + sizeof(struct sk_buff);
+
+ return 1;
+ }
+@@ -1803,7 +1867,6 @@
+ if (dev->net->features & NETIF_F_RXCSUM)
+ smsc95xx_rx_csum_offload(ax_skb);
+ skb_trim(ax_skb, ax_skb->len - 4); /* remove fcs */
+- ax_skb->truesize = size + sizeof(struct sk_buff);
+
+ usbnet_skb_return(dev, ax_skb);
+ }
+diff -Nur linux-4.1.3/drivers/net/wireless/Kconfig linux-xbian-rpi/drivers/net/wireless/Kconfig
+--- linux-4.1.3/drivers/net/wireless/Kconfig 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/net/wireless/Kconfig 2015-07-28 01:20:58.293696864 +0200
+@@ -277,7 +277,8 @@
+ source "drivers/net/wireless/orinoco/Kconfig"
+ source "drivers/net/wireless/p54/Kconfig"
+ source "drivers/net/wireless/rt2x00/Kconfig"
+-source "drivers/net/wireless/rtlwifi/Kconfig"
++#source "drivers/net/wireless/rtlwifi/Kconfig"
++source "drivers/net/wireless/rtl8192cu/Kconfig"
+ source "drivers/net/wireless/ti/Kconfig"
+ source "drivers/net/wireless/zd1211rw/Kconfig"
+ source "drivers/net/wireless/mwifiex/Kconfig"
+diff -Nur linux-4.1.3/drivers/net/wireless/Makefile linux-xbian-rpi/drivers/net/wireless/Makefile
+--- linux-4.1.3/drivers/net/wireless/Makefile 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/net/wireless/Makefile 2015-07-28 01:20:58.293696864 +0200
+@@ -24,7 +24,8 @@
+ obj-$(CONFIG_ZD1211RW) += zd1211rw/
+ obj-$(CONFIG_RTL8180) += rtl818x/
+ obj-$(CONFIG_RTL8187) += rtl818x/
+-obj-$(CONFIG_RTLWIFI) += rtlwifi/
++#obj-$(CONFIG_RTLWIFI) += rtlwifi/
++obj-$(CONFIG_RTL8192CU) += rtl8192cu/
+
+ # 16-bit wireless PCMCIA client drivers
+ obj-$(CONFIG_PCMCIA_RAYCS) += ray_cs.o
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/clean linux-xbian-rpi/drivers/net/wireless/rtl8192cu/clean
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/clean 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/clean 2015-07-28 01:20:58.297682643 +0200
+@@ -0,0 +1,5 @@
++#!/bin/bash
++rmmod 8192cu
++rmmod 8192ce
++rmmod 8192du
++rmmod 8192de
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/core/efuse/rtw_efuse.c linux-xbian-rpi/drivers/net/wireless/rtl8192cu/core/efuse/rtw_efuse.c
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/core/efuse/rtw_efuse.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/core/efuse/rtw_efuse.c 2015-07-28 01:20:58.297682643 +0200
+@@ -0,0 +1,1145 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#define _RTW_EFUSE_C_
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++
++#include <rtw_efuse.h>
++
++
++
++/*------------------------Define local variable------------------------------*/
++u8 fakeEfuseBank=0;
++u32 fakeEfuseUsedBytes=0;
++u8 fakeEfuseContent[EFUSE_MAX_HW_SIZE]={0};
++u8 fakeEfuseInitMap[EFUSE_MAX_MAP_LEN]={0};
++u8 fakeEfuseModifiedMap[EFUSE_MAX_MAP_LEN]={0};
++
++u32 BTEfuseUsedBytes=0;
++u8 BTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE];
++u8 BTEfuseInitMap[EFUSE_BT_MAX_MAP_LEN]={0};
++u8 BTEfuseModifiedMap[EFUSE_BT_MAX_MAP_LEN]={0};
++
++u32 fakeBTEfuseUsedBytes=0;
++u8 fakeBTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE];
++u8 fakeBTEfuseInitMap[EFUSE_BT_MAX_MAP_LEN]={0};
++u8 fakeBTEfuseModifiedMap[EFUSE_BT_MAX_MAP_LEN]={0};
++/*------------------------Define local variable------------------------------*/
++
++//------------------------------------------------------------------------------
++#define REG_EFUSE_CTRL 0x0030
++#define EFUSE_CTRL REG_EFUSE_CTRL // E-Fuse Control.
++//------------------------------------------------------------------------------
++
++BOOLEAN
++Efuse_Read1ByteFromFakeContent(
++ IN PADAPTER pAdapter,
++ IN u16 Offset,
++ IN OUT u8 *Value );
++BOOLEAN
++Efuse_Read1ByteFromFakeContent(
++ IN PADAPTER pAdapter,
++ IN u16 Offset,
++ IN OUT u8 *Value )
++{
++ if(Offset >= EFUSE_MAX_HW_SIZE)
++ {
++ return _FALSE;
++ }
++ //DbgPrint("Read fake content, offset = %d\n", Offset);
++ if(fakeEfuseBank == 0)
++ *Value = fakeEfuseContent[Offset];
++ else
++ *Value = fakeBTEfuseContent[fakeEfuseBank-1][Offset];
++ return _TRUE;
++}
++
++BOOLEAN
++Efuse_Write1ByteToFakeContent(
++ IN PADAPTER pAdapter,
++ IN u16 Offset,
++ IN u8 Value );
++BOOLEAN
++Efuse_Write1ByteToFakeContent(
++ IN PADAPTER pAdapter,
++ IN u16 Offset,
++ IN u8 Value )
++{
++ if(Offset >= EFUSE_MAX_HW_SIZE)
++ {
++ return _FALSE;
++ }
++ if(fakeEfuseBank == 0)
++ fakeEfuseContent[Offset] = Value;
++ else
++ {
++ fakeBTEfuseContent[fakeEfuseBank-1][Offset] = Value;
++ }
++ return _TRUE;
++}
++
++/*-----------------------------------------------------------------------------
++ * Function: Efuse_PowerSwitch
++ *
++ * Overview: When we want to enable write operation, we should change to
++ * pwr on state. When we stop write, we should switch to 500k mode
++ * and disable LDO 2.5V.
++ *
++ * Input: NONE
++ *
++ * Output: NONE
++ *
++ * Return: NONE
++ *
++ * Revised History:
++ * When Who Remark
++ * 11/17/2008 MHC Create Version 0.
++ *
++ *---------------------------------------------------------------------------*/
++VOID
++Efuse_PowerSwitch(
++ IN PADAPTER pAdapter,
++ IN u8 bWrite,
++ IN u8 PwrState)
++{
++ pAdapter->HalFunc.EfusePowerSwitch(pAdapter, bWrite, PwrState);
++}
++
++/*-----------------------------------------------------------------------------
++ * Function: efuse_GetCurrentSize
++ *
++ * Overview: Get current efuse size!!!
++ *
++ * Input: NONE
++ *
++ * Output: NONE
++ *
++ * Return: NONE
++ *
++ * Revised History:
++ * When Who Remark
++ * 11/16/2008 MHC Create Version 0.
++ *
++ *---------------------------------------------------------------------------*/
++u16
++Efuse_GetCurrentSize(
++ IN PADAPTER pAdapter,
++ IN u8 efuseType,
++ IN BOOLEAN bPseudoTest)
++{
++ u16 ret=0;
++
++ ret = pAdapter->HalFunc.EfuseGetCurrentSize(pAdapter, efuseType, bPseudoTest);
++
++ return ret;
++}
++
++/* 11/16/2008 MH Add description. Get current efuse area enabled word!!. */
++u8
++Efuse_CalculateWordCnts(IN u8 word_en)
++{
++ u8 word_cnts = 0;
++ if(!(word_en & BIT(0))) word_cnts++; // 0 : write enable
++ if(!(word_en & BIT(1))) word_cnts++;
++ if(!(word_en & BIT(2))) word_cnts++;
++ if(!(word_en & BIT(3))) word_cnts++;
++ return word_cnts;
++}
++
++//
++// Description:
++// Execute E-Fuse read byte operation.
++// Refered from SD1 Richard.
++//
++// Assumption:
++// 1. Boot from E-Fuse and successfully auto-load.
++// 2. PASSIVE_LEVEL (USB interface)
++//
++// Created by Roger, 2008.10.21.
++//
++VOID
++ReadEFuseByte(
++ PADAPTER Adapter,
++ u16 _offset,
++ u8 *pbuf,
++ IN BOOLEAN bPseudoTest)
++{
++ u32 value32;
++ u8 readbyte;
++ u16 retry;
++ //u32 start=rtw_get_current_time();
++
++ if(bPseudoTest)
++ {
++ Efuse_Read1ByteFromFakeContent(Adapter, _offset, pbuf);
++ return;
++ }
++
++ //Write Address
++ rtw_write8(Adapter, EFUSE_CTRL+1, (_offset & 0xff));
++ readbyte = rtw_read8(Adapter, EFUSE_CTRL+2);
++ rtw_write8(Adapter, EFUSE_CTRL+2, ((_offset >> 8) & 0x03) | (readbyte & 0xfc));
++
++ //Write bit 32 0
++ readbyte = rtw_read8(Adapter, EFUSE_CTRL+3);
++ rtw_write8(Adapter, EFUSE_CTRL+3, (readbyte & 0x7f));
++
++ //Check bit 32 read-ready
++ retry = 0;
++ value32 = rtw_read32(Adapter, EFUSE_CTRL);
++ //while(!(((value32 >> 24) & 0xff) & 0x80) && (retry<10))
++ while(!(((value32 >> 24) & 0xff) & 0x80) && (retry<10000))
++ {
++ value32 = rtw_read32(Adapter, EFUSE_CTRL);
++ retry++;
++ }
++
++ // 20100205 Joseph: Add delay suggested by SD1 Victor.
++ // This fix the problem that Efuse read error in high temperature condition.
++ // Designer says that there shall be some delay after ready bit is set, or the
++ // result will always stay on last data we read.
++ rtw_udelay_os(50);
++ value32 = rtw_read32(Adapter, EFUSE_CTRL);
++
++ *pbuf = (u8)(value32 & 0xff);
++ //DBG_871X("ReadEFuseByte _offset:%08u, in %d ms\n",_offset ,rtw_get_passing_time_ms(start));
++
++}
++
++
++//
++// Description:
++// 1. Execute E-Fuse read byte operation according as map offset and
++// save to E-Fuse table.
++// 2. Refered from SD1 Richard.
++//
++// Assumption:
++// 1. Boot from E-Fuse and successfully auto-load.
++// 2. PASSIVE_LEVEL (USB interface)
++//
++// Created by Roger, 2008.10.21.
++//
++// 2008/12/12 MH 1. Reorganize code flow and reserve bytes. and add description.
++// 2. Add efuse utilization collect.
++// 2008/12/22 MH Read Efuse must check if we write section 1 data again!!! Sec1
++// write addr must be after sec5.
++//
++
++VOID
++efuse_ReadEFuse(
++ PADAPTER Adapter,
++ u8 efuseType,
++ u16 _offset,
++ u16 _size_byte,
++ u8 *pbuf,
++ IN BOOLEAN bPseudoTest
++ );
++VOID
++efuse_ReadEFuse(
++ PADAPTER Adapter,
++ u8 efuseType,
++ u16 _offset,
++ u16 _size_byte,
++ u8 *pbuf,
++ IN BOOLEAN bPseudoTest
++ )
++{
++ Adapter->HalFunc.ReadEFuse(Adapter, efuseType, _offset, _size_byte, pbuf, bPseudoTest);
++}
++
++VOID
++EFUSE_GetEfuseDefinition(
++ IN PADAPTER pAdapter,
++ IN u8 efuseType,
++ IN u8 type,
++ OUT void *pOut,
++ IN BOOLEAN bPseudoTest
++ )
++{
++ pAdapter->HalFunc.EFUSEGetEfuseDefinition(pAdapter, efuseType, type, pOut, bPseudoTest);
++}
++
++/*-----------------------------------------------------------------------------
++ * Function: EFUSE_Read1Byte
++ *
++ * Overview: Copy from WMAC fot EFUSE read 1 byte.
++ *
++ * Input: NONE
++ *
++ * Output: NONE
++ *
++ * Return: NONE
++ *
++ * Revised History:
++ * When Who Remark
++ * 09/23/2008 MHC Copy from WMAC.
++ *
++ *---------------------------------------------------------------------------*/
++u8
++EFUSE_Read1Byte(
++ IN PADAPTER Adapter,
++ IN u16 Address)
++{
++ u8 data;
++ u8 Bytetemp = {0x00};
++ u8 temp = {0x00};
++ u32 k=0;
++ u16 contentLen=0;
++
++ EFUSE_GetEfuseDefinition(Adapter, EFUSE_WIFI , TYPE_EFUSE_REAL_CONTENT_LEN, (PVOID)&contentLen, _FALSE);
++
++ if (Address < contentLen) //E-fuse 512Byte
++ {
++ //Write E-fuse Register address bit0~7
++ temp = Address & 0xFF;
++ rtw_write8(Adapter, EFUSE_CTRL+1, temp);
++ Bytetemp = rtw_read8(Adapter, EFUSE_CTRL+2);
++ //Write E-fuse Register address bit8~9
++ temp = ((Address >> 8) & 0x03) | (Bytetemp & 0xFC);
++ rtw_write8(Adapter, EFUSE_CTRL+2, temp);
++
++ //Write 0x30[31]=0
++ Bytetemp = rtw_read8(Adapter, EFUSE_CTRL+3);
++ temp = Bytetemp & 0x7F;
++ rtw_write8(Adapter, EFUSE_CTRL+3, temp);
++
++ //Wait Write-ready (0x30[31]=1)
++ Bytetemp = rtw_read8(Adapter, EFUSE_CTRL+3);
++ while(!(Bytetemp & 0x80))
++ {
++ Bytetemp = rtw_read8(Adapter, EFUSE_CTRL+3);
++ k++;
++ if(k==1000)
++ {
++ k=0;
++ break;
++ }
++ }
++ data=rtw_read8(Adapter, EFUSE_CTRL);
++ return data;
++ }
++ else
++ return 0xFF;
++
++}/* EFUSE_Read1Byte */
++
++/*-----------------------------------------------------------------------------
++ * Function: EFUSE_Write1Byte
++ *
++ * Overview: Copy from WMAC fot EFUSE write 1 byte.
++ *
++ * Input: NONE
++ *
++ * Output: NONE
++ *
++ * Return: NONE
++ *
++ * Revised History:
++ * When Who Remark
++ * 09/23/2008 MHC Copy from WMAC.
++ *
++ *---------------------------------------------------------------------------*/
++
++void
++EFUSE_Write1Byte(
++ IN PADAPTER Adapter,
++ IN u16 Address,
++ IN u8 Value);
++void
++EFUSE_Write1Byte(
++ IN PADAPTER Adapter,
++ IN u16 Address,
++ IN u8 Value)
++{
++ u8 Bytetemp = {0x00};
++ u8 temp = {0x00};
++ u32 k=0;
++ u16 contentLen=0;
++
++ //RT_TRACE(COMP_EFUSE, DBG_LOUD, ("Addr=%x Data =%x\n", Address, Value));
++ EFUSE_GetEfuseDefinition(Adapter, EFUSE_WIFI , TYPE_EFUSE_REAL_CONTENT_LEN, (PVOID)&contentLen, _FALSE);
++
++ if( Address < contentLen) //E-fuse 512Byte
++ {
++ rtw_write8(Adapter, EFUSE_CTRL, Value);
++
++ //Write E-fuse Register address bit0~7
++ temp = Address & 0xFF;
++ rtw_write8(Adapter, EFUSE_CTRL+1, temp);
++ Bytetemp = rtw_read8(Adapter, EFUSE_CTRL+2);
++
++ //Write E-fuse Register address bit8~9
++ temp = ((Address >> 8) & 0x03) | (Bytetemp & 0xFC);
++ rtw_write8(Adapter, EFUSE_CTRL+2, temp);
++
++ //Write 0x30[31]=1
++ Bytetemp = rtw_read8(Adapter, EFUSE_CTRL+3);
++ temp = Bytetemp | 0x80;
++ rtw_write8(Adapter, EFUSE_CTRL+3, temp);
++
++ //Wait Write-ready (0x30[31]=0)
++ Bytetemp = rtw_read8(Adapter, EFUSE_CTRL+3);
++ while(Bytetemp & 0x80)
++ {
++ Bytetemp = rtw_read8(Adapter, EFUSE_CTRL+3);
++ k++;
++ if(k==100)
++ {
++ k=0;
++ break;
++ }
++ }
++ }
++}/* EFUSE_Write1Byte */
++
++/* 11/16/2008 MH Read one byte from real Efuse. */
++u8
++efuse_OneByteRead(
++ IN PADAPTER pAdapter,
++ IN u16 addr,
++ IN u8 *data,
++ IN BOOLEAN bPseudoTest)
++{
++ u8 tmpidx = 0;
++ u8 bResult;
++
++ if(bPseudoTest)
++ {
++ bResult = Efuse_Read1ByteFromFakeContent(pAdapter, addr, data);
++ return bResult;
++ }
++ // -----------------e-fuse reg ctrl ---------------------------------
++ //address
++ rtw_write8(pAdapter, EFUSE_CTRL+1, (u8)(addr&0xff));
++ rtw_write8(pAdapter, EFUSE_CTRL+2, ((u8)((addr>>8) &0x03) ) |
++ (rtw_read8(pAdapter, EFUSE_CTRL+2)&0xFC ));
++
++ rtw_write8(pAdapter, EFUSE_CTRL+3, 0x72);//read cmd
++
++ while(!(0x80 &rtw_read8(pAdapter, EFUSE_CTRL+3))&&(tmpidx<100))
++ {
++ tmpidx++;
++ }
++ if(tmpidx<100)
++ {
++ *data=rtw_read8(pAdapter, EFUSE_CTRL);
++ bResult = _TRUE;
++ }
++ else
++ {
++ *data = 0xff;
++ bResult = _FALSE;
++ }
++ return bResult;
++}
++
++/* 11/16/2008 MH Write one byte to reald Efuse. */
++u8
++efuse_OneByteWrite(
++ IN PADAPTER pAdapter,
++ IN u16 addr,
++ IN u8 data,
++ IN BOOLEAN bPseudoTest)
++{
++ u8 tmpidx = 0;
++ u8 bResult;
++
++ if(bPseudoTest)
++ {
++ bResult = Efuse_Write1ByteToFakeContent(pAdapter, addr, data);
++ return bResult;
++ }
++ //RT_TRACE(COMP_EFUSE, DBG_LOUD, ("Addr = %x Data=%x\n", addr, data));
++
++ //return 0;
++
++ // -----------------e-fuse reg ctrl ---------------------------------
++ //address
++ rtw_write8(pAdapter, EFUSE_CTRL+1, (u8)(addr&0xff));
++ rtw_write8(pAdapter, EFUSE_CTRL+2,
++ (rtw_read8(pAdapter, EFUSE_CTRL+2)&0xFC )|(u8)((addr>>8)&0x03) );
++ rtw_write8(pAdapter, EFUSE_CTRL, data);//data
++
++ rtw_write8(pAdapter, EFUSE_CTRL+3, 0xF2);//write cmd
++
++ while((0x80 & rtw_read8(pAdapter, EFUSE_CTRL+3)) && (tmpidx<100) ){
++ tmpidx++;
++ }
++
++ if(tmpidx<100)
++ {
++ bResult = _TRUE;
++ }
++ else
++ {
++ bResult = _FALSE;
++ }
++
++ return bResult;
++}
++
++int
++Efuse_PgPacketRead( IN PADAPTER pAdapter,
++ IN u8 offset,
++ IN u8 *data,
++ IN BOOLEAN bPseudoTest)
++{
++ int ret=0;
++
++ ret = pAdapter->HalFunc.Efuse_PgPacketRead(pAdapter, offset, data, bPseudoTest);
++
++ return ret;
++}
++
++int
++Efuse_PgPacketWrite(IN PADAPTER pAdapter,
++ IN u8 offset,
++ IN u8 word_en,
++ IN u8 *data,
++ IN BOOLEAN bPseudoTest)
++{
++ int ret;
++
++ ret = pAdapter->HalFunc.Efuse_PgPacketWrite(pAdapter, offset, word_en, data, bPseudoTest);
++
++ return ret;
++}
++
++/*-----------------------------------------------------------------------------
++ * Function: efuse_WordEnableDataRead
++ *
++ * Overview: Read allowed word in current efuse section data.
++ *
++ * Input: NONE
++ *
++ * Output: NONE
++ *
++ * Return: NONE
++ *
++ * Revised History:
++ * When Who Remark
++ * 11/16/2008 MHC Create Version 0.
++ * 11/21/2008 MHC Fix Write bug when we only enable late word.
++ *
++ *---------------------------------------------------------------------------*/
++void
++efuse_WordEnableDataRead(IN u8 word_en,
++ IN u8 *sourdata,
++ IN u8 *targetdata)
++{
++ if (!(word_en&BIT(0)))
++ {
++ targetdata[0] = sourdata[0];
++ targetdata[1] = sourdata[1];
++ }
++ if (!(word_en&BIT(1)))
++ {
++ targetdata[2] = sourdata[2];
++ targetdata[3] = sourdata[3];
++ }
++ if (!(word_en&BIT(2)))
++ {
++ targetdata[4] = sourdata[4];
++ targetdata[5] = sourdata[5];
++ }
++ if (!(word_en&BIT(3)))
++ {
++ targetdata[6] = sourdata[6];
++ targetdata[7] = sourdata[7];
++ }
++}
++
++
++u8
++Efuse_WordEnableDataWrite( IN PADAPTER pAdapter,
++ IN u16 efuse_addr,
++ IN u8 word_en,
++ IN u8 *data,
++ IN BOOLEAN bPseudoTest)
++{
++ u8 ret=0;
++
++ ret = pAdapter->HalFunc.Efuse_WordEnableDataWrite(pAdapter, efuse_addr, word_en, data, bPseudoTest);
++
++ return ret;
++}
++
++static u8 efuse_read8(PADAPTER padapter, u16 address, u8 *value)
++{
++ return efuse_OneByteRead(padapter,address, value, _FALSE);
++}
++
++static u8 efuse_write8(PADAPTER padapter, u16 address, u8 *value)
++{
++ return efuse_OneByteWrite(padapter,address, *value, _FALSE);
++}
++
++/*
++ * read/wirte raw efuse data
++ */
++u8 rtw_efuse_access(PADAPTER padapter, u8 bWrite, u16 start_addr, u16 cnts, u8 *data)
++{
++ int i = 0;
++ u16 real_content_len = 0, max_available_size = 0;
++ u8 res = _FAIL ;
++ u8 (*rw8)(PADAPTER, u16, u8*);
++
++ EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_REAL_CONTENT_LEN, (PVOID)&real_content_len, _FALSE);
++ EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, (PVOID)&max_available_size, _FALSE);
++
++ if (start_addr > real_content_len)
++ return _FAIL;
++
++ if (_TRUE == bWrite) {
++ if ((start_addr + cnts) > max_available_size)
++ return _FAIL;
++ rw8 = &efuse_write8;
++ } else
++ rw8 = &efuse_read8;
++
++ Efuse_PowerSwitch(padapter, bWrite, _TRUE);
++
++ // e-fuse one byte read / write
++ for (i = 0; i < cnts; i++) {
++ if (start_addr >= real_content_len) {
++ res = _FAIL;
++ break;
++ }
++
++ res = rw8(padapter, start_addr++, data++);
++ if (_FAIL == res) break;
++ }
++
++ Efuse_PowerSwitch(padapter, bWrite, _FALSE);
++
++ return res;
++}
++//------------------------------------------------------------------------------
++u16 efuse_GetMaxSize(PADAPTER padapter)
++{
++ u16 max_size;
++ EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI , TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, (PVOID)&max_size, _FALSE);
++ return max_size;
++}
++//------------------------------------------------------------------------------
++u8 efuse_GetCurrentSize(PADAPTER padapter, u16 *size)
++{
++ Efuse_PowerSwitch(padapter, _FALSE, _TRUE);
++ *size = Efuse_GetCurrentSize(padapter, EFUSE_WIFI, _FALSE);
++ Efuse_PowerSwitch(padapter, _FALSE, _FALSE);
++
++ return _SUCCESS;
++}
++//------------------------------------------------------------------------------
++u8 rtw_efuse_map_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data)
++{
++ u16 mapLen=0;
++
++ EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (PVOID)&mapLen, _FALSE);
++
++ if ((addr + cnts) > mapLen)
++ return _FAIL;
++
++ Efuse_PowerSwitch(padapter, _FALSE, _TRUE);
++
++ efuse_ReadEFuse(padapter, EFUSE_WIFI, addr, cnts, data, _FALSE);
++
++ Efuse_PowerSwitch(padapter, _FALSE, _FALSE);
++
++ return _SUCCESS;
++}
++//------------------------------------------------------------------------------
++u8 rtw_efuse_map_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data)
++{
++ u8 offset, word_en;
++ u8 *map;
++ u8 newdata[PGPKT_DATA_SIZE];
++ s32 i, j, idx;
++ u8 ret = _SUCCESS;
++ u16 mapLen=0;
++
++ EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (PVOID)&mapLen, _FALSE);
++
++ if ((addr + cnts) > mapLen)
++ return _FAIL;
++
++ map = rtw_zmalloc(mapLen);
++ if(map == NULL){
++ return _FAIL;
++ }
++
++ ret = rtw_efuse_map_read(padapter, 0, mapLen, map);
++ if (ret == _FAIL) goto exit;
++
++ Efuse_PowerSwitch(padapter, _TRUE, _TRUE);
++
++ offset = (addr >> 3);
++ word_en = 0xF;
++ _rtw_memset(newdata, 0xFF, PGPKT_DATA_SIZE);
++ i = addr & 0x7; // index of one package
++ j = 0; // index of new package
++ idx = 0; // data index
++
++ if (i & 0x1) {
++ // odd start
++ if (data[idx] != map[addr+idx]) {
++ word_en &= ~BIT(i >> 1);
++ newdata[i-1] = map[addr+idx-1];
++ newdata[i] = data[idx];
++ }
++ i++;
++ idx++;
++ }
++ do {
++ for (; i < PGPKT_DATA_SIZE; i += 2)
++ {
++ if (cnts == idx) break;
++ if ((cnts - idx) == 1) {
++ if (data[idx] != map[addr+idx]) {
++ word_en &= ~BIT(i >> 1);
++ newdata[i] = data[idx];
++ newdata[i+1] = map[addr+idx+1];
++ }
++ idx++;
++ break;
++ } else {
++ if ((data[idx] != map[addr+idx]) ||
++ (data[idx+1] != map[addr+idx+1]))
++ {
++ word_en &= ~BIT(i >> 1);
++ newdata[i] = data[idx];
++ newdata[i+1] = data[idx + 1];
++ }
++ idx += 2;
++ }
++ if (idx == cnts) break;
++ }
++
++ if (word_en != 0xF) {
++ ret = Efuse_PgPacketWrite(padapter, offset, word_en, newdata, _FALSE);
++ DBG_871X("offset=%x \n",offset);
++ DBG_871X("word_en=%x \n",word_en);
++
++ for(i=0;i<PGPKT_DATA_SIZE;i++)
++ {
++ DBG_871X("data=%x \t",newdata[i]);
++ }
++ if (ret == _FAIL) break;
++ }
++
++ if (idx == cnts) break;
++
++ offset++;
++ i = 0;
++ j = 0;
++ word_en = 0xF;
++ _rtw_memset(newdata, 0xFF, PGPKT_DATA_SIZE);
++ } while (1);
++
++ Efuse_PowerSwitch(padapter, _TRUE, _FALSE);
++
++exit:
++
++ rtw_mfree(map, mapLen);
++
++ return ret;
++}
++
++
++/*-----------------------------------------------------------------------------
++ * Function: Efuse_ReadAllMap
++ *
++ * Overview: Read All Efuse content
++ *
++ * Input: NONE
++ *
++ * Output: NONE
++ *
++ * Return: NONE
++ *
++ * Revised History:
++ * When Who Remark
++ * 11/11/2008 MHC Create Version 0.
++ *
++ *---------------------------------------------------------------------------*/
++VOID
++Efuse_ReadAllMap(
++ IN PADAPTER pAdapter,
++ IN u8 efuseType,
++ IN OUT u8 *Efuse,
++ IN BOOLEAN bPseudoTest);
++VOID
++Efuse_ReadAllMap(
++ IN PADAPTER pAdapter,
++ IN u8 efuseType,
++ IN OUT u8 *Efuse,
++ IN BOOLEAN bPseudoTest)
++{
++ u16 mapLen=0;
++
++ Efuse_PowerSwitch(pAdapter,_FALSE, _TRUE);
++
++ EFUSE_GetEfuseDefinition(pAdapter, efuseType, TYPE_EFUSE_MAP_LEN, (PVOID)&mapLen, bPseudoTest);
++
++ efuse_ReadEFuse(pAdapter, efuseType, 0, mapLen, Efuse, bPseudoTest);
++
++ Efuse_PowerSwitch(pAdapter,_FALSE, _FALSE);
++}
++
++/*-----------------------------------------------------------------------------
++ * Function: efuse_ShadowRead1Byte
++ * efuse_ShadowRead2Byte
++ * efuse_ShadowRead4Byte
++ *
++ * Overview: Read from efuse init map by one/two/four bytes !!!!!
++ *
++ * Input: NONE
++ *
++ * Output: NONE
++ *
++ * Return: NONE
++ *
++ * Revised History:
++ * When Who Remark
++ * 11/12/2008 MHC Create Version 0.
++ *
++ *---------------------------------------------------------------------------*/
++static VOID
++efuse_ShadowRead1Byte(
++ IN PADAPTER pAdapter,
++ IN u16 Offset,
++ IN OUT u8 *Value)
++{
++ EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(pAdapter);
++
++ *Value = pEEPROM->efuse_eeprom_data[Offset];
++
++} // EFUSE_ShadowRead1Byte
++
++//---------------Read Two Bytes
++static VOID
++efuse_ShadowRead2Byte(
++ IN PADAPTER pAdapter,
++ IN u16 Offset,
++ IN OUT u16 *Value)
++{
++ EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(pAdapter);
++
++ *Value = pEEPROM->efuse_eeprom_data[Offset];
++ *Value |= pEEPROM->efuse_eeprom_data[Offset+1]<<8;
++
++} // EFUSE_ShadowRead2Byte
++
++//---------------Read Four Bytes
++static VOID
++efuse_ShadowRead4Byte(
++ IN PADAPTER pAdapter,
++ IN u16 Offset,
++ IN OUT u32 *Value)
++{
++ EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(pAdapter);
++
++ *Value = pEEPROM->efuse_eeprom_data[Offset];
++ *Value |= pEEPROM->efuse_eeprom_data[Offset+1]<<8;
++ *Value |= pEEPROM->efuse_eeprom_data[Offset+2]<<16;
++ *Value |= pEEPROM->efuse_eeprom_data[Offset+3]<<24;
++
++} // efuse_ShadowRead4Byte
++
++
++/*-----------------------------------------------------------------------------
++ * Function: efuse_ShadowWrite1Byte
++ * efuse_ShadowWrite2Byte
++ * efuse_ShadowWrite4Byte
++ *
++ * Overview: Write efuse modify map by one/two/four byte.
++ *
++ * Input: NONE
++ *
++ * Output: NONE
++ *
++ * Return: NONE
++ *
++ * Revised History:
++ * When Who Remark
++ * 11/12/2008 MHC Create Version 0.
++ *
++ *---------------------------------------------------------------------------*/
++#ifdef PLATFORM
++static VOID
++efuse_ShadowWrite1Byte(
++ IN PADAPTER pAdapter,
++ IN u16 Offset,
++ IN u8 Value);
++#endif //PLATFORM
++static VOID
++efuse_ShadowWrite1Byte(
++ IN PADAPTER pAdapter,
++ IN u16 Offset,
++ IN u8 Value)
++{
++ EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(pAdapter);
++
++ pEEPROM->efuse_eeprom_data[Offset] = Value;
++
++} // efuse_ShadowWrite1Byte
++
++//---------------Write Two Bytes
++static VOID
++efuse_ShadowWrite2Byte(
++ IN PADAPTER pAdapter,
++ IN u16 Offset,
++ IN u16 Value)
++{
++ EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(pAdapter);
++
++ pEEPROM->efuse_eeprom_data[Offset] = Value&0x00FF;
++ pEEPROM->efuse_eeprom_data[Offset+1] = Value>>8;
++
++} // efuse_ShadowWrite1Byte
++
++//---------------Write Four Bytes
++static VOID
++efuse_ShadowWrite4Byte(
++ IN PADAPTER pAdapter,
++ IN u16 Offset,
++ IN u32 Value)
++{
++ EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(pAdapter);
++
++ pEEPROM->efuse_eeprom_data[Offset] = (u8)(Value&0x000000FF);
++ pEEPROM->efuse_eeprom_data[Offset+1] = (u8)((Value>>8)&0x0000FF);
++ pEEPROM->efuse_eeprom_data[Offset+2] = (u8)((Value>>16)&0x00FF);
++ pEEPROM->efuse_eeprom_data[Offset+3] = (u8)((Value>>24)&0xFF);
++
++} // efuse_ShadowWrite1Byte
++
++/*-----------------------------------------------------------------------------
++ * Function: EFUSE_ShadowMapUpdate
++ *
++ * Overview: Transfer current EFUSE content to shadow init and modify map.
++ *
++ * Input: NONE
++ *
++ * Output: NONE
++ *
++ * Return: NONE
++ *
++ * Revised History:
++ * When Who Remark
++ * 11/13/2008 MHC Create Version 0.
++ *
++ *---------------------------------------------------------------------------*/
++void EFUSE_ShadowMapUpdate(
++ IN PADAPTER pAdapter,
++ IN u8 efuseType,
++ IN BOOLEAN bPseudoTest)
++{
++ EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(pAdapter);
++ u16 mapLen=0;
++
++ EFUSE_GetEfuseDefinition(pAdapter, efuseType, TYPE_EFUSE_MAP_LEN, (PVOID)&mapLen, bPseudoTest);
++
++ if (pEEPROM->bautoload_fail_flag == _TRUE)
++ {
++ _rtw_memset(pEEPROM->efuse_eeprom_data, 0xFF, mapLen);
++ }
++ else
++ {
++ #ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE
++ if(_SUCCESS != retriveAdaptorInfoFile(pAdapter->registrypriv.adaptor_info_caching_file_path, pEEPROM)) {
++ #endif
++
++ Efuse_ReadAllMap(pAdapter, efuseType, pEEPROM->efuse_eeprom_data, bPseudoTest);
++
++ #ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE
++ storeAdaptorInfoFile(pAdapter->registrypriv.adaptor_info_caching_file_path, pEEPROM);
++ }
++ #endif
++ }
++
++ //PlatformMoveMemory((PVOID)&pHalData->EfuseMap[EFUSE_MODIFY_MAP][0],
++ //(PVOID)&pHalData->EfuseMap[EFUSE_INIT_MAP][0], mapLen);
++}// EFUSE_ShadowMapUpdate
++
++
++/*-----------------------------------------------------------------------------
++ * Function: EFUSE_ShadowRead
++ *
++ * Overview: Read from efuse init map !!!!!
++ *
++ * Input: NONE
++ *
++ * Output: NONE
++ *
++ * Return: NONE
++ *
++ * Revised History:
++ * When Who Remark
++ * 11/12/2008 MHC Create Version 0.
++ *
++ *---------------------------------------------------------------------------*/
++void
++EFUSE_ShadowRead(
++ IN PADAPTER pAdapter,
++ IN u8 Type,
++ IN u16 Offset,
++ IN OUT u32 *Value )
++{
++ if (Type == 1)
++ efuse_ShadowRead1Byte(pAdapter, Offset, (u8 *)Value);
++ else if (Type == 2)
++ efuse_ShadowRead2Byte(pAdapter, Offset, (u16 *)Value);
++ else if (Type == 4)
++ efuse_ShadowRead4Byte(pAdapter, Offset, (u32 *)Value);
++
++} // EFUSE_ShadowRead
++
++/*-----------------------------------------------------------------------------
++ * Function: EFUSE_ShadowWrite
++ *
++ * Overview: Write efuse modify map for later update operation to use!!!!!
++ *
++ * Input: NONE
++ *
++ * Output: NONE
++ *
++ * Return: NONE
++ *
++ * Revised History:
++ * When Who Remark
++ * 11/12/2008 MHC Create Version 0.
++ *
++ *---------------------------------------------------------------------------*/
++VOID
++EFUSE_ShadowWrite(
++ IN PADAPTER pAdapter,
++ IN u8 Type,
++ IN u16 Offset,
++ IN OUT u32 Value);
++VOID
++EFUSE_ShadowWrite(
++ IN PADAPTER pAdapter,
++ IN u8 Type,
++ IN u16 Offset,
++ IN OUT u32 Value)
++{
++#if (MP_DRIVER == 0)
++ return;
++#endif
++
++ if (Type == 1)
++ efuse_ShadowWrite1Byte(pAdapter, Offset, (u8)Value);
++ else if (Type == 2)
++ efuse_ShadowWrite2Byte(pAdapter, Offset, (u16)Value);
++ else if (Type == 4)
++ efuse_ShadowWrite4Byte(pAdapter, Offset, (u32)Value);
++
++} // EFUSE_ShadowWrite
++
++VOID
++Efuse_InitSomeVar(
++ IN PADAPTER pAdapter
++ );
++VOID
++Efuse_InitSomeVar(
++ IN PADAPTER pAdapter
++ )
++{
++ u8 i;
++
++ _rtw_memset((PVOID)&fakeEfuseContent[0], 0xff, EFUSE_MAX_HW_SIZE);
++ _rtw_memset((PVOID)&fakeEfuseInitMap[0], 0xff, EFUSE_MAX_MAP_LEN);
++ _rtw_memset((PVOID)&fakeEfuseModifiedMap[0], 0xff, EFUSE_MAX_MAP_LEN);
++
++ for(i=0; i<EFUSE_MAX_BT_BANK; i++)
++ {
++ _rtw_memset((PVOID)&BTEfuseContent[i][0], EFUSE_MAX_HW_SIZE, 0xff);
++ }
++ _rtw_memset((PVOID)&BTEfuseInitMap[0], 0xff, EFUSE_BT_MAX_MAP_LEN);
++ _rtw_memset((PVOID)&BTEfuseModifiedMap[0], 0xff, EFUSE_BT_MAX_MAP_LEN);
++
++ for(i=0; i<EFUSE_MAX_BT_BANK; i++)
++ {
++ _rtw_memset((PVOID)&fakeBTEfuseContent[i][0], 0xff, EFUSE_MAX_HW_SIZE);
++ }
++ _rtw_memset((PVOID)&fakeBTEfuseInitMap[0], 0xff, EFUSE_BT_MAX_MAP_LEN);
++ _rtw_memset((PVOID)&fakeBTEfuseModifiedMap[0], 0xff, EFUSE_BT_MAX_MAP_LEN);
++}
++
++#ifdef PLATFORM_LINUX
++#ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE
++//#include <rtw_eeprom.h>
++
++ int isAdaptorInfoFileValid(void)
++{
++ return _TRUE;
++}
++
++int storeAdaptorInfoFile(char *path, struct eeprom_priv * eeprom_priv)
++{
++ int ret =_SUCCESS;
++
++ if(path && eeprom_priv) {
++ ret = rtw_store_to_file(path, eeprom_priv->efuse_eeprom_data, EEPROM_MAX_SIZE);
++ if(ret == EEPROM_MAX_SIZE)
++ ret = _SUCCESS;
++ else
++ ret = _FAIL;
++ } else {
++ DBG_871X("%s NULL pointer\n",__FUNCTION__);
++ ret = _FAIL;
++ }
++ return ret;
++}
++
++int retriveAdaptorInfoFile(char *path, struct eeprom_priv * eeprom_priv)
++{
++ int ret = _SUCCESS;
++ mm_segment_t oldfs;
++ struct file *fp;
++
++ if(path && eeprom_priv) {
++
++ ret = rtw_retrive_from_file(path, eeprom_priv->efuse_eeprom_data, EEPROM_MAX_SIZE);
++
++ if(ret == EEPROM_MAX_SIZE)
++ ret = _SUCCESS;
++ else
++ ret = _FAIL;
++
++ #if 0
++ if(isAdaptorInfoFileValid()) {
++ return 0;
++ } else {
++ return _FAIL;
++ }
++ #endif
++
++ } else {
++ DBG_871X("%s NULL pointer\n",__FUNCTION__);
++ ret = _FAIL;
++ }
++ return ret;
++}
++#endif //CONFIG_ADAPTOR_INFO_CACHING_FILE
++#endif //PLATFORM_LINUX
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/core/rtw_ap.c linux-xbian-rpi/drivers/net/wireless/rtl8192cu/core/rtw_ap.c
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/core/rtw_ap.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/core/rtw_ap.c 2015-07-28 01:20:58.297682643 +0200
+@@ -0,0 +1,2939 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#define _RTW_AP_C_
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++#include <wifi.h>
++
++
++#ifdef CONFIG_AP_MODE
++
++extern unsigned char RTW_WPA_OUI[];
++extern unsigned char WMM_OUI[];
++extern unsigned char WPS_OUI[];
++extern unsigned char P2P_OUI[];
++extern unsigned char WFD_OUI[];
++
++void init_mlme_ap_info(_adapter *padapter)
++{
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ struct sta_priv *pstapriv = &padapter->stapriv;
++ struct wlan_acl_pool *pacl_list = &pstapriv->acl_list;
++
++
++ _rtw_spinlock_init(&pmlmepriv->bcn_update_lock);
++
++ //for ACL
++ _rtw_init_queue(&pacl_list->acl_node_q);
++
++ //pmlmeext->bstart_bss = _FALSE;
++
++ start_ap_mode(padapter);
++}
++
++void free_mlme_ap_info(_adapter *padapter)
++{
++ _irqL irqL;
++ struct sta_info *psta=NULL;
++ struct sta_priv *pstapriv = &padapter->stapriv;
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++
++ //stop_ap_mode(padapter);
++
++ pmlmepriv->update_bcn = _FALSE;
++ pmlmeext->bstart_bss = _FALSE;
++
++ rtw_sta_flush(padapter);
++
++ pmlmeinfo->state = _HW_STATE_NOLINK_;
++
++ //free_assoc_sta_resources
++ rtw_free_all_stainfo(padapter);
++
++ //free bc/mc sta_info
++ psta = rtw_get_bcmc_stainfo(padapter);
++ _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL);
++ rtw_free_stainfo(padapter, psta);
++ _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);
++
++
++ _rtw_spinlock_free(&pmlmepriv->bcn_update_lock);
++
++}
++
++static void update_BCNTIM(_adapter *padapter)
++{
++ struct sta_priv *pstapriv = &padapter->stapriv;
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ WLAN_BSSID_EX *pnetwork_mlmeext = &(pmlmeinfo->network);
++ unsigned char *pie = pnetwork_mlmeext->IEs;
++
++ //DBG_871X("%s\n", __FUNCTION__);
++
++ //update TIM IE
++ //if(pstapriv->tim_bitmap)
++ if(_TRUE)
++ {
++ u8 *p, *dst_ie, *premainder_ie=NULL, *pbackup_remainder_ie=NULL;
++ u16 tim_bitmap_le;
++ uint offset, tmp_len, tim_ielen, tim_ie_offset, remainder_ielen;
++
++ tim_bitmap_le = cpu_to_le16(pstapriv->tim_bitmap);
++
++ p = rtw_get_ie(pie + _FIXED_IE_LENGTH_, _TIM_IE_, &tim_ielen, pnetwork_mlmeext->IELength - _FIXED_IE_LENGTH_);
++ if (p != NULL && tim_ielen>0)
++ {
++ tim_ielen += 2;
++
++ premainder_ie = p+tim_ielen;
++
++ tim_ie_offset = (sint)(p -pie);
++
++ remainder_ielen = pnetwork_mlmeext->IELength - tim_ie_offset - tim_ielen;
++
++ //append TIM IE from dst_ie offset
++ dst_ie = p;
++ }
++ else
++ {
++ tim_ielen = 0;
++
++ //calucate head_len
++ offset = _FIXED_IE_LENGTH_;
++
++ /* get ssid_ie len */
++ p = rtw_get_ie(pie + _BEACON_IE_OFFSET_, _SSID_IE_, &tmp_len, (pnetwork_mlmeext->IELength - _BEACON_IE_OFFSET_));
++ if (p != NULL)
++ offset += tmp_len+2;
++
++ // get supported rates len
++ p = rtw_get_ie(pie + _BEACON_IE_OFFSET_, _SUPPORTEDRATES_IE_, &tmp_len, (pnetwork_mlmeext->IELength - _BEACON_IE_OFFSET_));
++ if (p != NULL)
++ {
++ offset += tmp_len+2;
++ }
++
++ //DS Parameter Set IE, len=3
++ offset += 3;
++
++ premainder_ie = pie + offset;
++
++ remainder_ielen = pnetwork_mlmeext->IELength - offset - tim_ielen;
++
++ //append TIM IE from offset
++ dst_ie = pie + offset;
++
++ }
++
++
++ if(remainder_ielen>0)
++ {
++ pbackup_remainder_ie = rtw_malloc(remainder_ielen);
++ if(pbackup_remainder_ie && premainder_ie)
++ _rtw_memcpy(pbackup_remainder_ie, premainder_ie, remainder_ielen);
++ }
++
++ *dst_ie++=_TIM_IE_;
++
++ if((pstapriv->tim_bitmap&0xff00) && (pstapriv->tim_bitmap&0x00fc))
++ tim_ielen = 5;
++ else
++ tim_ielen = 4;
++
++ *dst_ie++= tim_ielen;
++
++ *dst_ie++=0;//DTIM count
++ *dst_ie++=1;//DTIM peroid
++
++ if(pstapriv->tim_bitmap&BIT(0))//for bc/mc frames
++ *dst_ie++ = BIT(0);//bitmap ctrl
++ else
++ *dst_ie++ = 0;
++
++ if(tim_ielen==4)
++ {
++ *dst_ie++ = *(u8*)&tim_bitmap_le;
++ }
++ else if(tim_ielen==5)
++ {
++ _rtw_memcpy(dst_ie, &tim_bitmap_le, 2);
++ dst_ie+=2;
++ }
++
++ //copy remainder IE
++ if(pbackup_remainder_ie)
++ {
++ _rtw_memcpy(dst_ie, pbackup_remainder_ie, remainder_ielen);
++
++ rtw_mfree(pbackup_remainder_ie, remainder_ielen);
++ }
++
++ offset = (uint)(dst_ie - pie);
++ pnetwork_mlmeext->IELength = offset + remainder_ielen;
++
++ }
++
++#ifndef CONFIG_INTERRUPT_BASED_TXBCN
++#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
++ set_tx_beacon_cmd(padapter);
++#endif
++#endif //!CONFIG_INTERRUPT_BASED_TXBCN
++
++
++}
++
++void rtw_add_bcn_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 index, u8 *data, u8 len)
++{
++ PNDIS_802_11_VARIABLE_IEs pIE;
++ u8 bmatch = _FALSE;
++ u8 *pie = pnetwork->IEs;
++ u8 *p, *dst_ie, *premainder_ie=NULL, *pbackup_remainder_ie=NULL;
++ u32 i, offset, ielen, ie_offset, remainder_ielen = 0;
++
++ for (i = sizeof(NDIS_802_11_FIXED_IEs); i < pnetwork->IELength;)
++ {
++ pIE = (PNDIS_802_11_VARIABLE_IEs)(pnetwork->IEs + i);
++
++ if (pIE->ElementID > index)
++ {
++ break;
++ }
++ else if(pIE->ElementID == index) // already exist the same IE
++ {
++ p = (u8 *)pIE;
++ ielen = pIE->Length;
++ bmatch = _TRUE;
++ break;
++ }
++
++ p = (u8 *)pIE;
++ ielen = pIE->Length;
++ i += (pIE->Length + 2);
++ }
++
++ if (p != NULL && ielen>0)
++ {
++ ielen += 2;
++
++ premainder_ie = p+ielen;
++
++ ie_offset = (sint)(p -pie);
++
++ remainder_ielen = pnetwork->IELength - ie_offset - ielen;
++
++ if(bmatch)
++ dst_ie = p;
++ else
++ dst_ie = (p+ielen);
++ }
++
++ if(remainder_ielen>0)
++ {
++ pbackup_remainder_ie = rtw_malloc(remainder_ielen);
++ if(pbackup_remainder_ie && premainder_ie)
++ _rtw_memcpy(pbackup_remainder_ie, premainder_ie, remainder_ielen);
++ }
++
++ *dst_ie++=index;
++ *dst_ie++=len;
++
++ _rtw_memcpy(dst_ie, data, len);
++ dst_ie+=len;
++
++ //copy remainder IE
++ if(pbackup_remainder_ie)
++ {
++ _rtw_memcpy(dst_ie, pbackup_remainder_ie, remainder_ielen);
++
++ rtw_mfree(pbackup_remainder_ie, remainder_ielen);
++ }
++
++ offset = (uint)(dst_ie - pie);
++ pnetwork->IELength = offset + remainder_ielen;
++}
++
++void rtw_remove_bcn_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 index)
++{
++ u8 *p, *dst_ie, *premainder_ie=NULL, *pbackup_remainder_ie=NULL;
++ uint offset, ielen, ie_offset, remainder_ielen = 0;
++ u8 *pie = pnetwork->IEs;
++
++ p = rtw_get_ie(pie + _FIXED_IE_LENGTH_, index, &ielen, pnetwork->IELength - _FIXED_IE_LENGTH_);
++ if (p != NULL && ielen>0)
++ {
++ ielen += 2;
++
++ premainder_ie = p+ielen;
++
++ ie_offset = (sint)(p -pie);
++
++ remainder_ielen = pnetwork->IELength - ie_offset - ielen;
++
++ dst_ie = p;
++ }
++ else {
++ return;
++ }
++
++ if(remainder_ielen>0)
++ {
++ pbackup_remainder_ie = rtw_malloc(remainder_ielen);
++ if(pbackup_remainder_ie && premainder_ie)
++ _rtw_memcpy(pbackup_remainder_ie, premainder_ie, remainder_ielen);
++ }
++
++ //copy remainder IE
++ if(pbackup_remainder_ie)
++ {
++ _rtw_memcpy(dst_ie, pbackup_remainder_ie, remainder_ielen);
++
++ rtw_mfree(pbackup_remainder_ie, remainder_ielen);
++ }
++
++ offset = (uint)(dst_ie - pie);
++ pnetwork->IELength = offset + remainder_ielen;
++}
++
++
++u8 chk_sta_is_alive(struct sta_info *psta);
++u8 chk_sta_is_alive(struct sta_info *psta)
++{
++ u8 ret = _FALSE;
++ #ifdef DBG_EXPIRATION_CHK
++ DBG_871X("sta:"MAC_FMT", rssi:%d, rx:"STA_PKTS_FMT", expire_to:%u, %s%ssq_len:%u\n"
++ , MAC_ARG(psta->hwaddr)
++ , psta->rssi_stat.UndecoratedSmoothedPWDB
++ //, STA_RX_PKTS_ARG(psta)
++ , STA_RX_PKTS_DIFF_ARG(psta)
++ , psta->expire_to
++ , psta->state&WIFI_SLEEP_STATE?"PS, ":""
++ , psta->state&WIFI_STA_ALIVE_CHK_STATE?"SAC, ":""
++ , psta->sleepq_len
++ );
++ #endif
++
++ //if(sta_last_rx_pkts(psta) == sta_rx_pkts(psta))
++ if((psta->sta_stats.last_rx_data_pkts + psta->sta_stats.last_rx_ctrl_pkts) == (psta->sta_stats.rx_data_pkts + psta->sta_stats.rx_ctrl_pkts))
++ {
++ #if 0
++ if(psta->state&WIFI_SLEEP_STATE)
++ ret = _TRUE;
++ #endif
++ }
++ else
++ {
++ ret = _TRUE;
++ }
++
++ sta_update_last_rx_pkts(psta);
++
++ return ret;
++}
++
++void expire_timeout_chk(_adapter *padapter)
++{
++ _irqL irqL;
++ _list *phead, *plist;
++ u8 updated;
++ struct sta_info *psta=NULL;
++ struct sta_priv *pstapriv = &padapter->stapriv;
++ u8 chk_alive_num = 0;
++ char chk_alive_list[NUM_STA];
++ int i;
++
++ _enter_critical_bh(&pstapriv->auth_list_lock, &irqL);
++
++ phead = &pstapriv->auth_list;
++ plist = get_next(phead);
++
++ //check auth_queue
++ #ifdef DBG_EXPIRATION_CHK
++ if (rtw_end_of_queue_search(phead, plist) == _FALSE) {
++ DBG_871X(FUNC_NDEV_FMT" auth_list, cnt:%u\n"
++ , FUNC_NDEV_ARG(padapter->pnetdev), pstapriv->auth_list_cnt);
++ }
++ #endif
++ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE)
++ {
++ psta = LIST_CONTAINOR(plist, struct sta_info, auth_list);
++ plist = get_next(plist);
++
++ if(psta->expire_to>0)
++ {
++ psta->expire_to--;
++ if (psta->expire_to == 0)
++ {
++ rtw_list_delete(&psta->auth_list);
++ pstapriv->auth_list_cnt--;
++
++ DBG_871X("auth expire %02X%02X%02X%02X%02X%02X\n",
++ psta->hwaddr[0],psta->hwaddr[1],psta->hwaddr[2],psta->hwaddr[3],psta->hwaddr[4],psta->hwaddr[5]);
++
++ _exit_critical_bh(&pstapriv->auth_list_lock, &irqL);
++
++ _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL);
++ rtw_free_stainfo(padapter, psta);
++ _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);
++
++ _enter_critical_bh(&pstapriv->auth_list_lock, &irqL);
++ }
++ }
++
++ }
++
++ _exit_critical_bh(&pstapriv->auth_list_lock, &irqL);
++
++ psta = NULL;
++
++
++ _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++
++ phead = &pstapriv->asoc_list;
++ plist = get_next(phead);
++
++ //check asoc_queue
++ #ifdef DBG_EXPIRATION_CHK
++ if (rtw_end_of_queue_search(phead, plist) == _FALSE) {
++ DBG_871X(FUNC_NDEV_FMT" asoc_list, cnt:%u\n"
++ , FUNC_NDEV_ARG(padapter->pnetdev), pstapriv->asoc_list_cnt);
++ }
++ #endif
++ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE)
++ {
++ psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);
++ plist = get_next(plist);
++
++ if (chk_sta_is_alive(psta) || !psta->expire_to) {
++ psta->expire_to = pstapriv->expire_to;
++ psta->keep_alive_trycnt = 0;
++ #ifdef CONFIG_TX_MCAST2UNI
++ psta->under_exist_checking = 0;
++ #endif // CONFIG_TX_MCAST2UNI
++ } else {
++ psta->expire_to--;
++ }
++
++#ifndef CONFIG_ACTIVE_KEEP_ALIVE_CHECK
++#ifdef CONFIG_TX_MCAST2UNI
++ if ( (psta->flags & WLAN_STA_HT) && (psta->htpriv.agg_enable_bitmap || psta->under_exist_checking) ) {
++ // check sta by delba(addba) for 11n STA
++ // ToDo: use CCX report to check for all STAs
++ //DBG_871X("asoc check by DELBA/ADDBA! (pstapriv->expire_to=%d s)(psta->expire_to=%d s), [%02x, %d]\n", pstapriv->expire_to*2, psta->expire_to*2, psta->htpriv.agg_enable_bitmap, psta->under_exist_checking);
++
++ if ( psta->expire_to <= (pstapriv->expire_to - 50 ) ) {
++ DBG_871X("asoc expire by DELBA/ADDBA! (%d s)\n", (pstapriv->expire_to-psta->expire_to)*2);
++ psta->under_exist_checking = 0;
++ psta->expire_to = 0;
++ } else if ( psta->expire_to <= (pstapriv->expire_to - 3) && (psta->under_exist_checking==0)) {
++ DBG_871X("asoc check by DELBA/ADDBA! (%d s)\n", (pstapriv->expire_to-psta->expire_to)*2);
++ psta->under_exist_checking = 1;
++ //tear down TX AMPDU
++ send_delba(padapter, 1, psta->hwaddr);// // originator
++ psta->htpriv.agg_enable_bitmap = 0x0;//reset
++ psta->htpriv.candidate_tid_bitmap = 0x0;//reset
++ }
++ }
++#endif // CONFIG_TX_MCAST2UNI
++#endif //CONFIG_ACTIVE_KEEP_ALIVE_CHECK
++
++ if (psta->expire_to <= 0)
++ {
++ #ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++
++ if (padapter->registrypriv.wifi_spec == 1)
++ {
++ psta->expire_to = pstapriv->expire_to;
++ continue;
++ }
++
++ if (psta->state & WIFI_SLEEP_STATE) {
++ if (!(psta->state & WIFI_STA_ALIVE_CHK_STATE)) {
++ //to check if alive by another methods if staion is at ps mode.
++ psta->expire_to = pstapriv->expire_to;
++ psta->state |= WIFI_STA_ALIVE_CHK_STATE;
++
++ //DBG_871X("alive chk, sta:" MAC_FMT " is at ps mode!\n", MAC_ARG(psta->hwaddr));
++
++ //to update bcn with tim_bitmap for this station
++ pstapriv->tim_bitmap |= BIT(psta->aid);
++ update_beacon(padapter, _TIM_IE_, NULL, _FALSE);
++
++ if(!pmlmeext->active_keep_alive_check)
++ continue;
++ }
++ }
++
++ if (pmlmeext->active_keep_alive_check) {
++ int stainfo_offset;
++
++ stainfo_offset = rtw_stainfo_offset(pstapriv, psta);
++ if (stainfo_offset_valid(stainfo_offset)) {
++ chk_alive_list[chk_alive_num++] = stainfo_offset;
++ }
++
++ continue;
++ }
++ #endif /* CONFIG_ACTIVE_KEEP_ALIVE_CHECK */
++
++ rtw_list_delete(&psta->asoc_list);
++ pstapriv->asoc_list_cnt--;
++
++ DBG_871X("asoc expire "MAC_FMT", state=0x%x\n", MAC_ARG(psta->hwaddr), psta->state);
++ updated = ap_free_sta(padapter, psta, _FALSE, WLAN_REASON_DEAUTH_LEAVING);
++ }
++ else
++ {
++ /* TODO: Aging mechanism to digest frames in sleep_q to avoid running out of xmitframe */
++ if (psta->sleepq_len > (NR_XMITFRAME/pstapriv->asoc_list_cnt)
++ && padapter->xmitpriv.free_xmitframe_cnt < (NR_XMITFRAME/pstapriv->asoc_list_cnt/2)
++ ){
++ DBG_871X("%s sta:"MAC_FMT", sleepq_len:%u, free_xmitframe_cnt:%u, asoc_list_cnt:%u, clear sleep_q\n", __func__
++ , MAC_ARG(psta->hwaddr)
++ , psta->sleepq_len, padapter->xmitpriv.free_xmitframe_cnt, pstapriv->asoc_list_cnt);
++ wakeup_sta_to_xmit(padapter, psta);
++ }
++ }
++ }
++
++ _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++
++#ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK
++if (chk_alive_num) {
++
++ u8 backup_oper_channel=0;
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ /* switch to correct channel of current network before issue keep-alive frames */
++ if (rtw_get_oper_ch(padapter) != pmlmeext->cur_channel) {
++ backup_oper_channel = rtw_get_oper_ch(padapter);
++ SelectChannel(padapter, pmlmeext->cur_channel);
++ }
++
++ /* issue null data to check sta alive*/
++ for (i = 0; i < chk_alive_num; i++) {
++
++ int ret = _FAIL;
++
++ psta = rtw_get_stainfo_by_offset(pstapriv, chk_alive_list[i]);
++ if(!(psta->state &_FW_LINKED))
++ continue;
++
++ if (psta->state & WIFI_SLEEP_STATE)
++ ret = issue_nulldata(padapter, psta->hwaddr, 0, 1, 50);
++ else
++ ret = issue_nulldata(padapter, psta->hwaddr, 0, 3, 50);
++
++ psta->keep_alive_trycnt++;
++ if (ret == _SUCCESS)
++ {
++ DBG_871X("asoc check, sta(" MAC_FMT ") is alive\n", MAC_ARG(psta->hwaddr));
++ psta->expire_to = pstapriv->expire_to;
++ psta->keep_alive_trycnt = 0;
++ continue;
++ }
++ else if (psta->keep_alive_trycnt <= 3)
++ {
++ DBG_871X("ack check for asoc expire, keep_alive_trycnt=%d\n", psta->keep_alive_trycnt);
++ psta->expire_to = 1;
++ continue;
++ }
++
++ psta->keep_alive_trycnt = 0;
++
++ DBG_871X("asoc expire "MAC_FMT", state=0x%x\n", MAC_ARG(psta->hwaddr), psta->state);
++ _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++ if (rtw_is_list_empty(&psta->asoc_list)==_FALSE) {
++ rtw_list_delete(&psta->asoc_list);
++ pstapriv->asoc_list_cnt--;
++ updated = ap_free_sta(padapter, psta, _FALSE, WLAN_REASON_DEAUTH_LEAVING);
++ }
++ _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++
++ }
++
++ if (backup_oper_channel>0) /* back to the original operation channel */
++ SelectChannel(padapter, backup_oper_channel);
++}
++#endif /* CONFIG_ACTIVE_KEEP_ALIVE_CHECK */
++
++ associated_clients_update(padapter, updated);
++}
++
++
++static void add_RATid(_adapter *padapter, struct sta_info *psta)
++{
++ int i;
++ u8 rf_type;
++ u32 init_rate=0;
++ unsigned char sta_band = 0, raid, shortGIrate = _FALSE;
++ unsigned char limit;
++ unsigned int tx_ra_bitmap=0;
++ struct ht_priv *psta_ht = NULL;
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ WLAN_BSSID_EX *pcur_network = (WLAN_BSSID_EX *)&pmlmepriv->cur_network.network;
++
++
++ if(psta)
++ psta_ht = &psta->htpriv;
++ else
++ return;
++
++ //b/g mode ra_bitmap
++ for (i=0; i<sizeof(psta->bssrateset); i++)
++ {
++ if (psta->bssrateset[i])
++ tx_ra_bitmap |= rtw_get_bit_value_from_ieee_value(psta->bssrateset[i]&0x7f);
++ }
++
++ //n mode ra_bitmap
++ if(psta_ht->ht_option)
++ {
++ rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));
++ if(rf_type == RF_2T2R)
++ limit=16;// 2R
++ else
++ limit=8;// 1R
++
++ for (i=0; i<limit; i++) {
++ if (psta_ht->ht_cap.supp_mcs_set[i/8] & BIT(i%8))
++ tx_ra_bitmap |= BIT(i+12);
++ }
++
++ //max short GI rate
++ shortGIrate = psta_ht->sgi;
++ }
++
++
++#if 0//gtest
++ if(get_rf_mimo_mode(padapter) == RTL8712_RF_2T2R)
++ {
++ //is this a 2r STA?
++ if((pstat->tx_ra_bitmap & 0x0ff00000) != 0 && !(priv->pshare->has_2r_sta & BIT(pstat->aid)))
++ {
++ priv->pshare->has_2r_sta |= BIT(pstat->aid);
++ if(rtw_read16(padapter, 0x102501f6) != 0xffff)
++ {
++ rtw_write16(padapter, 0x102501f6, 0xffff);
++ reset_1r_sta_RA(priv, 0xffff);
++ Switch_1SS_Antenna(priv, 3);
++ }
++ }
++ else// bg or 1R STA?
++ {
++ if((priv->pmib->dot11BssType.net_work_type & WIRELESS_11N) && pstat->ht_cap_len && priv->pshare->has_2r_sta == 0)
++ {
++ if(rtw_read16(padapter, 0x102501f6) != 0x7777)
++ { // MCS7 SGI
++ rtw_write16(padapter, 0x102501f6,0x7777);
++ reset_1r_sta_RA(priv, 0x7777);
++ Switch_1SS_Antenna(priv, 2);
++ }
++ }
++ }
++
++ }
++
++ if ((pstat->rssi_level < 1) || (pstat->rssi_level > 3))
++ {
++ if (pstat->rssi >= priv->pshare->rf_ft_var.raGoDownUpper)
++ pstat->rssi_level = 1;
++ else if ((pstat->rssi >= priv->pshare->rf_ft_var.raGoDown20MLower) ||
++ ((priv->pshare->is_40m_bw) && (pstat->ht_cap_len) &&
++ (pstat->rssi >= priv->pshare->rf_ft_var.raGoDown40MLower) &&
++ (pstat->ht_cap_buf.ht_cap_info & cpu_to_le16(_HTCAP_SUPPORT_CH_WDTH_))))
++ pstat->rssi_level = 2;
++ else
++ pstat->rssi_level = 3;
++ }
++
++ // rate adaptive by rssi
++ if ((priv->pmib->dot11BssType.net_work_type & WIRELESS_11N) && pstat->ht_cap_len)
++ {
++ if ((get_rf_mimo_mode(priv) == MIMO_1T2R) || (get_rf_mimo_mode(priv) == MIMO_1T1R))
++ {
++ switch (pstat->rssi_level) {
++ case 1:
++ pstat->tx_ra_bitmap &= 0x100f0000;
++ break;
++ case 2:
++ pstat->tx_ra_bitmap &= 0x100ff000;
++ break;
++ case 3:
++ if (priv->pshare->is_40m_bw)
++ pstat->tx_ra_bitmap &= 0x100ff005;
++ else
++ pstat->tx_ra_bitmap &= 0x100ff001;
++
++ break;
++ }
++ }
++ else
++ {
++ switch (pstat->rssi_level) {
++ case 1:
++ pstat->tx_ra_bitmap &= 0x1f0f0000;
++ break;
++ case 2:
++ pstat->tx_ra_bitmap &= 0x1f0ff000;
++ break;
++ case 3:
++ if (priv->pshare->is_40m_bw)
++ pstat->tx_ra_bitmap &= 0x000ff005;
++ else
++ pstat->tx_ra_bitmap &= 0x000ff001;
++
++ break;
++ }
++
++ // Don't need to mask high rates due to new rate adaptive parameters
++ //if (pstat->is_broadcom_sta) // use MCS12 as the highest rate vs. Broadcom sta
++ // pstat->tx_ra_bitmap &= 0x81ffffff;
++
++ // NIC driver will report not supporting MCS15 and MCS14 in asoc req
++ //if (pstat->is_rtl8190_sta && !pstat->is_2t_mimo_sta)
++ // pstat->tx_ra_bitmap &= 0x83ffffff; // if Realtek 1x2 sta, don't use MCS15 and MCS14
++ }
++ }
++ else if ((priv->pmib->dot11BssType.net_work_type & WIRELESS_11G) && isErpSta(pstat))
++ {
++ switch (pstat->rssi_level) {
++ case 1:
++ pstat->tx_ra_bitmap &= 0x00000f00;
++ break;
++ case 2:
++ pstat->tx_ra_bitmap &= 0x00000ff0;
++ break;
++ case 3:
++ pstat->tx_ra_bitmap &= 0x00000ff5;
++ break;
++ }
++ }
++ else
++ {
++ pstat->tx_ra_bitmap &= 0x0000000d;
++ }
++
++ // disable tx short GI when station cannot rx MCS15(AP is 2T2R)
++ // disable tx short GI when station cannot rx MCS7 (AP is 1T2R or 1T1R)
++ // if there is only 1r STA and we are 2T2R, DO NOT mask SGI rate
++ if ((!(pstat->tx_ra_bitmap & 0x8000000) && (priv->pshare->has_2r_sta > 0) && (get_rf_mimo_mode(padapter) == RTL8712_RF_2T2R)) ||
++ (!(pstat->tx_ra_bitmap & 0x80000) && (get_rf_mimo_mode(padapter) != RTL8712_RF_2T2R)))
++ {
++ pstat->tx_ra_bitmap &= ~BIT(28);
++ }
++#endif
++
++ if ( pcur_network->Configuration.DSConfig > 14 ) {
++ // 5G band
++ if (tx_ra_bitmap & 0xffff000)
++ sta_band |= WIRELESS_11_5N | WIRELESS_11A;
++ else
++ sta_band |= WIRELESS_11A;
++ } else {
++ if (tx_ra_bitmap & 0xffff000)
++ sta_band |= WIRELESS_11_24N | WIRELESS_11G | WIRELESS_11B;
++ else if (tx_ra_bitmap & 0xff0)
++ sta_band |= WIRELESS_11G |WIRELESS_11B;
++ else
++ sta_band |= WIRELESS_11B;
++ }
++
++ raid = networktype_to_raid(sta_band);
++ init_rate = get_highest_rate_idx(tx_ra_bitmap&0x0fffffff)&0x3f;
++
++ if (psta->aid < NUM_STA)
++ {
++ u8 arg = 0;
++
++ arg = psta->mac_id&0x1f;
++
++ arg |= BIT(7);//support entry 2~31
++
++ if (shortGIrate==_TRUE)
++ arg |= BIT(5);
++
++ tx_ra_bitmap |= ((raid<<28)&0xf0000000);
++
++ DBG_871X("%s=> mac_id:%d , raid:%d , bitmap=0x%x, arg=0x%x\n",
++ __FUNCTION__ , psta->mac_id, raid ,tx_ra_bitmap, arg);
++
++ //bitmap[0:27] = tx_rate_bitmap
++ //bitmap[28:31]= Rate Adaptive id
++ //arg[0:4] = macid
++ //arg[5] = Short GI
++ rtw_hal_add_ra_tid(padapter, tx_ra_bitmap, arg);
++
++ if (shortGIrate==_TRUE)
++ init_rate |= BIT(6);
++
++ //set ra_id, init_rate
++ psta->raid = raid;
++ psta->init_rate = init_rate;
++
++ }
++ else
++ {
++ DBG_871X("station aid %d exceed the max number\n", psta->aid);
++ }
++
++}
++
++static void update_bmc_sta(_adapter *padapter)
++{
++ _irqL irqL;
++ u32 init_rate=0;
++ unsigned char network_type, raid;
++ int i, supportRateNum = 0;
++ unsigned int tx_ra_bitmap=0;
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ WLAN_BSSID_EX *pcur_network = (WLAN_BSSID_EX *)&pmlmepriv->cur_network.network;
++ struct sta_info *psta = rtw_get_bcmc_stainfo(padapter);
++
++ if(psta)
++ {
++ psta->aid = 0;//default set to 0
++ //psta->mac_id = psta->aid+4;
++ psta->mac_id = psta->aid + 1;
++
++ psta->qos_option = 0;
++ psta->htpriv.ht_option = _FALSE;
++
++ psta->ieee8021x_blocked = 0;
++
++ _rtw_memset((void*)&psta->sta_stats, 0, sizeof(struct stainfo_stats));
++
++ //psta->dot118021XPrivacy = _NO_PRIVACY_;//!!! remove it, because it has been set before this.
++
++
++
++ //prepare for add_RATid
++ supportRateNum = rtw_get_rateset_len((u8*)&pcur_network->SupportedRates);
++ network_type = rtw_check_network_type((u8*)&pcur_network->SupportedRates, supportRateNum, 1);
++
++ _rtw_memcpy(psta->bssrateset, &pcur_network->SupportedRates, supportRateNum);
++ psta->bssratelen = supportRateNum;
++
++ //b/g mode ra_bitmap
++ for (i=0; i<supportRateNum; i++)
++ {
++ if (psta->bssrateset[i])
++ tx_ra_bitmap |= rtw_get_bit_value_from_ieee_value(psta->bssrateset[i]&0x7f);
++ }
++
++ if ( pcur_network->Configuration.DSConfig > 14 ) {
++ //force to A mode. 5G doesn't support CCK rates
++ network_type = WIRELESS_11A;
++ tx_ra_bitmap = 0x150; // 6, 12, 24 Mbps
++ } else {
++ //force to b mode
++ network_type = WIRELESS_11B;
++ tx_ra_bitmap = 0xf;
++ }
++
++ //tx_ra_bitmap = update_basic_rate(pcur_network->SupportedRates, supportRateNum);
++
++ raid = networktype_to_raid(network_type);
++ init_rate = get_highest_rate_idx(tx_ra_bitmap&0x0fffffff)&0x3f;
++
++ //DBG_871X("Add id %d val %08x to ratr for bmc sta\n", psta->aid, tx_ra_bitmap);
++
++ //if(pHalData->fw_ractrl == _TRUE)
++ {
++ u8 arg = 0;
++
++ arg = psta->mac_id&0x1f;
++
++ arg |= BIT(7);
++
++ //if (shortGIrate==_TRUE)
++ // arg |= BIT(5);
++
++ tx_ra_bitmap |= ((raid<<28)&0xf0000000);
++
++ DBG_871X("update_bmc_sta, mask=0x%x, arg=0x%x\n", tx_ra_bitmap, arg);
++
++ //bitmap[0:27] = tx_rate_bitmap
++ //bitmap[28:31]= Rate Adaptive id
++ //arg[0:4] = macid
++ //arg[5] = Short GI
++ rtw_hal_add_ra_tid(padapter, tx_ra_bitmap, arg);
++
++ }
++
++ //set ra_id, init_rate
++ psta->raid = raid;
++ psta->init_rate = init_rate;
++
++ _enter_critical_bh(&psta->lock, &irqL);
++ psta->state = _FW_LINKED;
++ _exit_critical_bh(&psta->lock, &irqL);
++
++ }
++ else
++ {
++ DBG_871X("add_RATid_bmc_sta error!\n");
++ }
++
++}
++
++//notes:
++//AID: 1~MAX for sta and 0 for bc/mc in ap/adhoc mode
++//MAC_ID = AID+1 for sta in ap/adhoc mode
++//MAC_ID = 1 for bc/mc for sta/ap/adhoc
++//MAC_ID = 0 for bssid for sta/ap/adhoc
++//CAM_ID = //0~3 for default key, cmd_id=macid + 3, macid=aid+1;
++
++void update_sta_info_apmode(_adapter *padapter, struct sta_info *psta)
++{
++ _irqL irqL;
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ struct security_priv *psecuritypriv = &padapter->securitypriv;
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++ struct ht_priv *phtpriv_ap = &pmlmepriv->htpriv;
++ struct ht_priv *phtpriv_sta = &psta->htpriv;
++
++ //set intf_tag to if1
++ //psta->intf_tag = 0;
++
++ //psta->mac_id = psta->aid+4;
++ psta->mac_id = psta->aid+1;
++
++ if(psecuritypriv->dot11AuthAlgrthm==dot11AuthAlgrthm_8021X)
++ psta->ieee8021x_blocked = _TRUE;
++ else
++ psta->ieee8021x_blocked = _FALSE;
++
++
++ //update sta's cap
++
++ //ERP
++ VCS_update(padapter, psta);
++
++ //HT related cap
++ if(phtpriv_sta->ht_option)
++ {
++ //check if sta supports rx ampdu
++ phtpriv_sta->ampdu_enable = phtpriv_ap->ampdu_enable;
++
++ //check if sta support s Short GI
++ if((phtpriv_sta->ht_cap.cap_info & phtpriv_ap->ht_cap.cap_info) & cpu_to_le16(IEEE80211_HT_CAP_SGI_20|IEEE80211_HT_CAP_SGI_40))
++ {
++ phtpriv_sta->sgi = _TRUE;
++ }
++
++ // bwmode
++ if((phtpriv_sta->ht_cap.cap_info & phtpriv_ap->ht_cap.cap_info) & cpu_to_le16(IEEE80211_HT_CAP_SUP_WIDTH))
++ {
++ //phtpriv_sta->bwmode = HT_CHANNEL_WIDTH_40;
++ phtpriv_sta->bwmode = pmlmeext->cur_bwmode;
++ phtpriv_sta->ch_offset = pmlmeext->cur_ch_offset;
++
++ }
++
++ psta->qos_option = _TRUE;
++
++ }
++ else
++ {
++ phtpriv_sta->ampdu_enable = _FALSE;
++
++ phtpriv_sta->sgi = _FALSE;
++ phtpriv_sta->bwmode = HT_CHANNEL_WIDTH_20;
++ phtpriv_sta->ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++ }
++
++ //Rx AMPDU
++ send_delba(padapter, 0, psta->hwaddr);// recipient
++
++ //TX AMPDU
++ send_delba(padapter, 1, psta->hwaddr);// // originator
++ phtpriv_sta->agg_enable_bitmap = 0x0;//reset
++ phtpriv_sta->candidate_tid_bitmap = 0x0;//reset
++
++
++ //todo: init other variables
++
++ _rtw_memset((void*)&psta->sta_stats, 0, sizeof(struct stainfo_stats));
++
++
++ //add ratid
++ //add_RATid(padapter, psta);//move to ap_sta_info_defer_update()
++
++
++ _enter_critical_bh(&psta->lock, &irqL);
++ psta->state |= _FW_LINKED;
++ _exit_critical_bh(&psta->lock, &irqL);
++
++
++}
++
++static void update_hw_ht_param(_adapter *padapter)
++{
++ unsigned char max_AMPDU_len;
++ unsigned char min_MPDU_spacing;
++ struct registry_priv *pregpriv = &padapter->registrypriv;
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++
++ DBG_871X("%s\n", __FUNCTION__);
++
++
++ //handle A-MPDU parameter field
++ /*
++ AMPDU_para [1:0]:Max AMPDU Len => 0:8k , 1:16k, 2:32k, 3:64k
++ AMPDU_para [4:2]:Min MPDU Start Spacing
++ */
++ max_AMPDU_len = pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x03;
++
++ min_MPDU_spacing = (pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x1c) >> 2;
++
++ rtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_MIN_SPACE, (u8 *)(&min_MPDU_spacing));
++
++ rtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_FACTOR, (u8 *)(&max_AMPDU_len));
++
++ //
++ // Config SM Power Save setting
++ //
++ pmlmeinfo->SM_PS = (pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info & 0x0C) >> 2;
++ if(pmlmeinfo->SM_PS == WLAN_HT_CAP_SM_PS_STATIC)
++ {
++ /*u8 i;
++ //update the MCS rates
++ for (i = 0; i < 16; i++)
++ {
++ pmlmeinfo->HT_caps.HT_cap_element.MCS_rate[i] &= MCS_rate_1R[i];
++ }*/
++ DBG_871X("%s(): WLAN_HT_CAP_SM_PS_STATIC\n",__FUNCTION__);
++ }
++
++ //
++ // Config current HT Protection mode.
++ //
++ //pmlmeinfo->HT_protection = pmlmeinfo->HT_info.infos[1] & 0x3;
++
++}
++
++static void start_bss_network(_adapter *padapter, u8 *pbuf)
++{
++ u8 *p;
++ u8 val8, cur_channel, cur_bwmode, cur_ch_offset;
++ u16 bcn_interval;
++ u32 acparm;
++ int ie_len;
++ struct registry_priv *pregpriv = &padapter->registrypriv;
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ struct security_priv* psecuritypriv=&(padapter->securitypriv);
++ WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)&pmlmepriv->cur_network.network;
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ WLAN_BSSID_EX *pnetwork_mlmeext = &(pmlmeinfo->network);
++ struct HT_info_element *pht_info=NULL;
++#ifdef CONFIG_P2P
++ struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
++#endif //CONFIG_P2P
++ u8 cbw40_enable=0;
++ u8 change_band = _FALSE;
++ //DBG_871X("%s\n", __FUNCTION__);
++
++ bcn_interval = (u16)pnetwork->Configuration.BeaconPeriod;
++ cur_channel = pnetwork->Configuration.DSConfig;
++ cur_bwmode = HT_CHANNEL_WIDTH_20;;
++ cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++
++
++ //check if there is wps ie,
++ //if there is wpsie in beacon, the hostapd will update beacon twice when stating hostapd,
++ //and at first time the security ie ( RSN/WPA IE) will not include in beacon.
++ if(NULL == rtw_get_wps_ie(pnetwork->IEs+_FIXED_IE_LENGTH_, pnetwork->IELength-_FIXED_IE_LENGTH_, NULL, NULL))
++ {
++ pmlmeext->bstart_bss = _TRUE;
++ }
++
++ //todo: update wmm, ht cap
++ //pmlmeinfo->WMM_enable;
++ //pmlmeinfo->HT_enable;
++ if(pmlmepriv->qospriv.qos_option)
++ pmlmeinfo->WMM_enable = _TRUE;
++
++ if(pmlmepriv->htpriv.ht_option)
++ {
++ pmlmeinfo->WMM_enable = _TRUE;
++ pmlmeinfo->HT_enable = _TRUE;
++ //pmlmeinfo->HT_info_enable = _TRUE;
++ //pmlmeinfo->HT_caps_enable = _TRUE;
++
++ update_hw_ht_param(padapter);
++ }
++
++
++ if(pmlmepriv->cur_network.join_res != _TRUE) //setting only at first time
++ {
++ //WEP Key will be set before this function, do not clear CAM.
++ if ((psecuritypriv->dot11PrivacyAlgrthm != _WEP40_) && (psecuritypriv->dot11PrivacyAlgrthm != _WEP104_))
++ flush_all_cam_entry(padapter); //clear CAM
++ }
++
++ //set MSR to AP_Mode
++ Set_MSR(padapter, _HW_STATE_AP_);
++
++ //Set BSSID REG
++ rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, pnetwork->MacAddress);
++
++ //Set EDCA param reg
++#ifdef CONFIG_CONCURRENT_MODE
++ acparm = 0x005ea42b;
++#else
++ acparm = 0x002F3217; // VO
++#endif
++ rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VO, (u8 *)(&acparm));
++ acparm = 0x005E4317; // VI
++ rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VI, (u8 *)(&acparm));
++ //acparm = 0x00105320; // BE
++ acparm = 0x005ea42b;
++ rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acparm));
++ acparm = 0x0000A444; // BK
++ rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BK, (u8 *)(&acparm));
++
++ //Set Security
++ val8 = (psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X)? 0xcc: 0xcf;
++ rtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, (u8 *)(&val8));
++
++ //Beacon Control related register
++ rtw_hal_set_hwreg(padapter, HW_VAR_BEACON_INTERVAL, (u8 *)(&bcn_interval));
++
++ if(pmlmepriv->cur_network.join_res != _TRUE) //setting only at first time
++ {
++ u32 initialgain;
++
++ initialgain = 0x1e;
++
++
++ //disable dynamic functions, such as high power, DIG
++ //Save_DM_Func_Flag(padapter);
++ //Switch_DM_Func(padapter, DYNAMIC_FUNC_DISABLE, _FALSE);
++
++#ifdef CONFIG_CONCURRENT_MODE
++ if(padapter->adapter_type > PRIMARY_ADAPTER)
++ {
++ if(rtw_buddy_adapter_up(padapter))
++ {
++ _adapter *pbuddy_adapter = padapter->pbuddy_adapter;
++
++ //turn on dynamic functions on PRIMARY_ADAPTER, dynamic functions only runs at PRIMARY_ADAPTER
++ Switch_DM_Func(pbuddy_adapter, DYNAMIC_FUNC_DIG|DYNAMIC_FUNC_HP|DYNAMIC_FUNC_SS, _TRUE);
++
++ rtw_hal_set_hwreg(pbuddy_adapter, HW_VAR_INITIAL_GAIN, (u8 *)(&initialgain));
++ }
++ }
++ else
++#endif
++ {
++ //turn on dynamic functions
++ Switch_DM_Func(padapter, DYNAMIC_FUNC_DIG|DYNAMIC_FUNC_HP|DYNAMIC_FUNC_SS, _TRUE);
++
++ rtw_hal_set_hwreg(padapter, HW_VAR_INITIAL_GAIN, (u8 *)(&initialgain));
++ }
++
++ }
++
++ //set channel, bwmode
++ p = rtw_get_ie((pnetwork->IEs + sizeof(NDIS_802_11_FIXED_IEs)), _HT_ADD_INFO_IE_, &ie_len, (pnetwork->IELength - sizeof(NDIS_802_11_FIXED_IEs)));
++ if( p && ie_len)
++ {
++ pht_info = (struct HT_info_element *)(p+2);
++
++ if( pmlmeext->cur_channel > 14 )
++ {
++ if( pregpriv->cbw40_enable & BIT(1) )
++ cbw40_enable = 1;
++ }
++ else
++ if( pregpriv->cbw40_enable & BIT(0) )
++ cbw40_enable = 1;
++
++ if ((cbw40_enable) && (pht_info->infos[0] & BIT(2)))
++ {
++ //switch to the 40M Hz mode
++ //pmlmeext->cur_bwmode = HT_CHANNEL_WIDTH_40;
++ cur_bwmode = HT_CHANNEL_WIDTH_40;
++ switch (pht_info->infos[0] & 0x3)
++ {
++ case 1:
++ //pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_LOWER;
++ cur_ch_offset = HAL_PRIME_CHNL_OFFSET_LOWER;
++ break;
++
++ case 3:
++ //pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_UPPER;
++ cur_ch_offset = HAL_PRIME_CHNL_OFFSET_UPPER;
++ break;
++
++ default:
++ //pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++ cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++ break;
++ }
++
++ }
++
++ }
++
++#ifdef CONFIG_DUALMAC_CONCURRENT
++ dc_set_ap_channel_bandwidth(padapter, cur_channel, cur_ch_offset, cur_bwmode);
++#else
++ //TODO: need to judge the phy parameters on concurrent mode for single phy
++ //set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode);
++#ifdef CONFIG_CONCURRENT_MODE
++ if(!check_buddy_fwstate(padapter, _FW_LINKED|_FW_UNDER_LINKING|_FW_UNDER_SURVEY))
++ {
++ set_channel_bwmode(padapter, cur_channel, cur_ch_offset, cur_bwmode);
++ }
++ else if(check_buddy_fwstate(padapter, _FW_LINKED)==_TRUE)//only second adapter can enter AP Mode
++ {
++ _adapter *pbuddy_adapter = padapter->pbuddy_adapter;
++ struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv;
++
++ //To sync cur_channel/cur_bwmode/cur_ch_offset with primary adapter
++ DBG_871X("primary iface is at linked state, sync cur_channel/cur_bwmode/cur_ch_offset\n");
++ DBG_871X("primary adapter, CH=%d, BW=%d, offset=%d\n", pbuddy_mlmeext->cur_channel, pbuddy_mlmeext->cur_bwmode, pbuddy_mlmeext->cur_ch_offset);
++ DBG_871X("second adapter, CH=%d, BW=%d, offset=%d\n", cur_channel, cur_bwmode, cur_ch_offset);
++
++ if((cur_channel <= 14 && pbuddy_mlmeext->cur_channel >= 36) ||
++ (cur_channel >= 36 && pbuddy_mlmeext->cur_channel <= 14))
++ change_band = _TRUE;
++
++ cur_channel = pbuddy_mlmeext->cur_channel;
++ if(cur_bwmode == HT_CHANNEL_WIDTH_40)
++ {
++ if(pht_info)
++ pht_info->infos[0] &= ~(BIT(0)|BIT(1));
++
++ if(pbuddy_mlmeext->cur_bwmode == HT_CHANNEL_WIDTH_40)
++ {
++ cur_ch_offset = pbuddy_mlmeext->cur_ch_offset;
++
++ //to update cur_ch_offset value in beacon
++ if(pht_info)
++ {
++ switch(cur_ch_offset)
++ {
++ case HAL_PRIME_CHNL_OFFSET_LOWER:
++ pht_info->infos[0] |= 0x1;
++ break;
++ case HAL_PRIME_CHNL_OFFSET_UPPER:
++ pht_info->infos[0] |= 0x3;
++ break;
++ case HAL_PRIME_CHNL_OFFSET_DONT_CARE:
++ default:
++ break;
++ }
++ }
++
++ }
++ else if(pbuddy_mlmeext->cur_bwmode == HT_CHANNEL_WIDTH_20)
++ {
++ cur_bwmode = HT_CHANNEL_WIDTH_20;
++ cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++
++ if(cur_channel>0 && cur_channel<5)
++ {
++ if(pht_info)
++ pht_info->infos[0] |= 0x1;
++
++ cur_bwmode = HT_CHANNEL_WIDTH_40;
++ cur_ch_offset = HAL_PRIME_CHNL_OFFSET_LOWER;
++ }
++
++ if(cur_channel>7 && cur_channel<(14+1))
++ {
++ if(pht_info)
++ pht_info->infos[0] |= 0x3;
++
++ cur_bwmode = HT_CHANNEL_WIDTH_40;
++ cur_ch_offset = HAL_PRIME_CHNL_OFFSET_UPPER;
++ }
++
++ set_channel_bwmode(padapter, cur_channel, cur_ch_offset, cur_bwmode);
++ }
++
++ }
++
++ // to update channel value in beacon
++ pnetwork->Configuration.DSConfig = cur_channel;
++ p = rtw_get_ie((pnetwork->IEs + sizeof(NDIS_802_11_FIXED_IEs)), _DSSET_IE_, &ie_len, (pnetwork->IELength - sizeof(NDIS_802_11_FIXED_IEs)));
++ if(p && ie_len>0)
++ *(p + 2) = cur_channel;
++
++ if(pht_info)
++ pht_info->primary_channel = cur_channel;
++
++ //set buddy adapter channel, bandwidth, offeset to current adapter
++ pmlmeext->cur_channel = cur_channel;
++ pmlmeext->cur_bwmode = cur_bwmode;
++ pmlmeext->cur_ch_offset = cur_ch_offset;
++
++ //buddy interface band is different from current interface, update ERP, support rate, ext support rate IE
++ if(change_band == _TRUE)
++ change_band_update_ie(padapter, pnetwork);
++ }
++#else
++ set_channel_bwmode(padapter, cur_channel, cur_ch_offset, cur_bwmode);
++#endif //CONFIG_CONCURRENT_MODE
++
++ DBG_871X("CH=%d, BW=%d, offset=%d\n", cur_channel, cur_bwmode, cur_ch_offset);
++
++ //
++ pmlmeext->cur_channel = cur_channel;
++ pmlmeext->cur_bwmode = cur_bwmode;
++ pmlmeext->cur_ch_offset = cur_ch_offset;
++#endif //CONFIG_DUALMAC_CONCURRENT
++ pmlmeext->cur_wireless_mode = pmlmepriv->cur_network.network_type;
++
++ //update cur_wireless_mode
++ update_wireless_mode(padapter);
++
++ //update RRSR after set channel and bandwidth
++ UpdateBrateTbl(padapter, pnetwork->SupportedRates);
++ rtw_hal_set_hwreg(padapter, HW_VAR_BASIC_RATE, pnetwork->SupportedRates);
++
++ //udpate capability after cur_wireless_mode updated
++ update_capinfo(padapter, rtw_get_capability((WLAN_BSSID_EX *)pnetwork));
++
++ //let pnetwork_mlmeext == pnetwork_mlme.
++ _rtw_memcpy(pnetwork_mlmeext, pnetwork, pnetwork->Length);
++
++#ifdef CONFIG_P2P
++ _rtw_memcpy(pwdinfo->p2p_group_ssid, pnetwork->Ssid.Ssid, pnetwork->Ssid.SsidLength);
++ pwdinfo->p2p_group_ssid_len = pnetwork->Ssid.SsidLength;
++#endif //CONFIG_P2P
++
++ if(_TRUE == pmlmeext->bstart_bss)
++ {
++ update_beacon(padapter, _TIM_IE_, NULL, _FALSE);
++
++#ifndef CONFIG_INTERRUPT_BASED_TXBCN //other case will tx beacon when bcn interrupt coming in.
++#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
++ //issue beacon frame
++ if(send_beacon(padapter)==_FAIL)
++ {
++ DBG_871X("issue_beacon, fail!\n");
++ }
++#endif
++#endif //!CONFIG_INTERRUPT_BASED_TXBCN
++
++ }
++
++
++ //update bc/mc sta_info
++ update_bmc_sta(padapter);
++
++ //pmlmeext->bstart_bss = _TRUE;
++
++}
++
++int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len)
++{
++ int ret=_SUCCESS;
++ u8 *p;
++ u8 *pHT_caps_ie=NULL;
++ u8 *pHT_info_ie=NULL;
++ struct sta_info *psta = NULL;
++ u16 cap, ht_cap=_FALSE;
++ uint ie_len = 0;
++ int group_cipher, pairwise_cipher;
++ u8 channel, network_type, supportRate[NDIS_802_11_LENGTH_RATES_EX];
++ int supportRateNum = 0;
++ u8 OUI1[] = {0x00, 0x50, 0xf2,0x01};
++ u8 wps_oui[4]={0x0,0x50,0xf2,0x04};
++ u8 WMM_PARA_IE[] = {0x00, 0x50, 0xf2, 0x02, 0x01, 0x01};
++ struct registry_priv *pregistrypriv = &padapter->registrypriv;
++ struct security_priv *psecuritypriv = &padapter->securitypriv;
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ WLAN_BSSID_EX *pbss_network = (WLAN_BSSID_EX *)&pmlmepriv->cur_network.network;
++ struct sta_priv *pstapriv = &padapter->stapriv;
++ u8 *ie = pbss_network->IEs;
++
++
++ /* SSID */
++ /* Supported rates */
++ /* DS Params */
++ /* WLAN_EID_COUNTRY */
++ /* ERP Information element */
++ /* Extended supported rates */
++ /* WPA/WPA2 */
++ /* Wi-Fi Wireless Multimedia Extensions */
++ /* ht_capab, ht_oper */
++ /* WPS IE */
++
++ DBG_871X("%s, len=%d\n", __FUNCTION__, len);
++
++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE)
++ return _FAIL;
++
++
++ if(len>MAX_IE_SZ)
++ return _FAIL;
++
++ pbss_network->IELength = len;
++
++ _rtw_memset(ie, 0, MAX_IE_SZ);
++
++ _rtw_memcpy(ie, pbuf, pbss_network->IELength);
++
++
++ if(pbss_network->InfrastructureMode!=Ndis802_11APMode)
++ return _FAIL;
++
++ pbss_network->Rssi = 0;
++
++ _rtw_memcpy(pbss_network->MacAddress, myid(&(padapter->eeprompriv)), ETH_ALEN);
++
++ //beacon interval
++ p = rtw_get_beacon_interval_from_ie(ie);//ie + 8; // 8: TimeStamp, 2: Beacon Interval 2:Capability
++ //pbss_network->Configuration.BeaconPeriod = le16_to_cpu(*(unsigned short*)p);
++ pbss_network->Configuration.BeaconPeriod = RTW_GET_LE16(p);
++
++ //capability
++ //cap = *(unsigned short *)rtw_get_capability_from_ie(ie);
++ //cap = le16_to_cpu(cap);
++ cap = RTW_GET_LE16(ie);
++
++ //SSID
++ p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _SSID_IE_, &ie_len, (pbss_network->IELength -_BEACON_IE_OFFSET_));
++ if(p && ie_len>0)
++ {
++ _rtw_memset(&pbss_network->Ssid, 0, sizeof(NDIS_802_11_SSID));
++ _rtw_memcpy(pbss_network->Ssid.Ssid, (p + 2), ie_len);
++ pbss_network->Ssid.SsidLength = ie_len;
++ }
++
++ //chnnel
++ channel = 0;
++ pbss_network->Configuration.Length = 0;
++ p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _DSSET_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_));
++ if(p && ie_len>0)
++ channel = *(p + 2);
++
++ pbss_network->Configuration.DSConfig = channel;
++
++
++ _rtw_memset(supportRate, 0, NDIS_802_11_LENGTH_RATES_EX);
++ // get supported rates
++ p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _SUPPORTEDRATES_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_));
++ if (p != NULL)
++ {
++ _rtw_memcpy(supportRate, p+2, ie_len);
++ supportRateNum = ie_len;
++ }
++
++ //get ext_supported rates
++ p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _EXT_SUPPORTEDRATES_IE_, &ie_len, pbss_network->IELength - _BEACON_IE_OFFSET_);
++ if (p != NULL)
++ {
++ _rtw_memcpy(supportRate+supportRateNum, p+2, ie_len);
++ supportRateNum += ie_len;
++
++ }
++
++ network_type = rtw_check_network_type(supportRate, supportRateNum, channel);
++
++ rtw_set_supported_rate(pbss_network->SupportedRates, network_type);
++
++
++ //parsing ERP_IE
++ p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _ERPINFO_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_));
++ if(p && ie_len>0)
++ {
++ ERP_IE_handler(padapter, (PNDIS_802_11_VARIABLE_IEs)p);
++ }
++
++ //update privacy/security
++ if (cap & BIT(4))
++ pbss_network->Privacy = 1;
++ else
++ pbss_network->Privacy = 0;
++
++ psecuritypriv->wpa_psk = 0;
++
++ //wpa2
++ group_cipher = 0; pairwise_cipher = 0;
++ psecuritypriv->wpa2_group_cipher = _NO_PRIVACY_;
++ psecuritypriv->wpa2_pairwise_cipher = _NO_PRIVACY_;
++ p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _RSN_IE_2_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_));
++ if(p && ie_len>0)
++ {
++ if(rtw_parse_wpa2_ie(p, ie_len+2, &group_cipher, &pairwise_cipher) == _SUCCESS)
++ {
++ psecuritypriv->dot11AuthAlgrthm= dot11AuthAlgrthm_8021X;
++
++ psecuritypriv->dot8021xalg = 1;//psk, todo:802.1x
++ psecuritypriv->wpa_psk |= BIT(1);
++
++ psecuritypriv->wpa2_group_cipher = group_cipher;
++ psecuritypriv->wpa2_pairwise_cipher = pairwise_cipher;
++#if 0
++ switch(group_cipher)
++ {
++ case WPA_CIPHER_NONE:
++ psecuritypriv->wpa2_group_cipher = _NO_PRIVACY_;
++ break;
++ case WPA_CIPHER_WEP40:
++ psecuritypriv->wpa2_group_cipher = _WEP40_;
++ break;
++ case WPA_CIPHER_TKIP:
++ psecuritypriv->wpa2_group_cipher = _TKIP_;
++ break;
++ case WPA_CIPHER_CCMP:
++ psecuritypriv->wpa2_group_cipher = _AES_;
++ break;
++ case WPA_CIPHER_WEP104:
++ psecuritypriv->wpa2_group_cipher = _WEP104_;
++ break;
++ }
++
++ switch(pairwise_cipher)
++ {
++ case WPA_CIPHER_NONE:
++ psecuritypriv->wpa2_pairwise_cipher = _NO_PRIVACY_;
++ break;
++ case WPA_CIPHER_WEP40:
++ psecuritypriv->wpa2_pairwise_cipher = _WEP40_;
++ break;
++ case WPA_CIPHER_TKIP:
++ psecuritypriv->wpa2_pairwise_cipher = _TKIP_;
++ break;
++ case WPA_CIPHER_CCMP:
++ psecuritypriv->wpa2_pairwise_cipher = _AES_;
++ break;
++ case WPA_CIPHER_WEP104:
++ psecuritypriv->wpa2_pairwise_cipher = _WEP104_;
++ break;
++ }
++#endif
++ }
++
++ }
++
++ //wpa
++ ie_len = 0;
++ group_cipher = 0; pairwise_cipher = 0;
++ psecuritypriv->wpa_group_cipher = _NO_PRIVACY_;
++ psecuritypriv->wpa_pairwise_cipher = _NO_PRIVACY_;
++ for (p = ie + _BEACON_IE_OFFSET_; ;p += (ie_len + 2))
++ {
++ p = rtw_get_ie(p, _SSN_IE_1_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_ - (ie_len + 2)));
++ if ((p) && (_rtw_memcmp(p+2, OUI1, 4)))
++ {
++ if(rtw_parse_wpa_ie(p, ie_len+2, &group_cipher, &pairwise_cipher) == _SUCCESS)
++ {
++ psecuritypriv->dot11AuthAlgrthm= dot11AuthAlgrthm_8021X;
++
++ psecuritypriv->dot8021xalg = 1;//psk, todo:802.1x
++
++ psecuritypriv->wpa_psk |= BIT(0);
++
++ psecuritypriv->wpa_group_cipher = group_cipher;
++ psecuritypriv->wpa_pairwise_cipher = pairwise_cipher;
++
++#if 0
++ switch(group_cipher)
++ {
++ case WPA_CIPHER_NONE:
++ psecuritypriv->wpa_group_cipher = _NO_PRIVACY_;
++ break;
++ case WPA_CIPHER_WEP40:
++ psecuritypriv->wpa_group_cipher = _WEP40_;
++ break;
++ case WPA_CIPHER_TKIP:
++ psecuritypriv->wpa_group_cipher = _TKIP_;
++ break;
++ case WPA_CIPHER_CCMP:
++ psecuritypriv->wpa_group_cipher = _AES_;
++ break;
++ case WPA_CIPHER_WEP104:
++ psecuritypriv->wpa_group_cipher = _WEP104_;
++ break;
++ }
++
++ switch(pairwise_cipher)
++ {
++ case WPA_CIPHER_NONE:
++ psecuritypriv->wpa_pairwise_cipher = _NO_PRIVACY_;
++ break;
++ case WPA_CIPHER_WEP40:
++ psecuritypriv->wpa_pairwise_cipher = _WEP40_;
++ break;
++ case WPA_CIPHER_TKIP:
++ psecuritypriv->wpa_pairwise_cipher = _TKIP_;
++ break;
++ case WPA_CIPHER_CCMP:
++ psecuritypriv->wpa_pairwise_cipher = _AES_;
++ break;
++ case WPA_CIPHER_WEP104:
++ psecuritypriv->wpa_pairwise_cipher = _WEP104_;
++ break;
++ }
++#endif
++ }
++
++ break;
++
++ }
++
++ if ((p == NULL) || (ie_len == 0))
++ {
++ break;
++ }
++
++ }
++
++ //wmm
++ ie_len = 0;
++ pmlmepriv->qospriv.qos_option = 0;
++ if(pregistrypriv->wmm_enable)
++ {
++ for (p = ie + _BEACON_IE_OFFSET_; ;p += (ie_len + 2))
++ {
++ p = rtw_get_ie(p, _VENDOR_SPECIFIC_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_ - (ie_len + 2)));
++ if((p) && _rtw_memcmp(p+2, WMM_PARA_IE, 6))
++ {
++ pmlmepriv->qospriv.qos_option = 1;
++
++ *(p+8) |= BIT(7);//QoS Info, support U-APSD
++
++ /* disable all ACM bits since the WMM admission control is not supported */
++ *(p + 10) &= ~BIT(4); /* BE */
++ *(p + 14) &= ~BIT(4); /* BK */
++ *(p + 18) &= ~BIT(4); /* VI */
++ *(p + 22) &= ~BIT(4); /* VO */
++
++ break;
++ }
++
++ if ((p == NULL) || (ie_len == 0))
++ {
++ break;
++ }
++ }
++ }
++
++ //parsing HT_CAP_IE
++ p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _HT_CAPABILITY_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_));
++ if(p && ie_len>0)
++ {
++ u8 rf_type;
++
++ struct rtw_ieee80211_ht_cap *pht_cap = (struct rtw_ieee80211_ht_cap *)(p+2);
++
++ pHT_caps_ie=p;
++
++
++ ht_cap = _TRUE;
++ network_type |= WIRELESS_11_24N;
++
++
++ rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));
++
++ if((psecuritypriv->wpa_pairwise_cipher & WPA_CIPHER_CCMP) ||
++ (psecuritypriv->wpa2_pairwise_cipher & WPA_CIPHER_CCMP))
++ {
++ pht_cap->ampdu_params_info |= (IEEE80211_HT_CAP_AMPDU_DENSITY&(0x07<<2));
++ }
++ else
++ {
++ pht_cap->ampdu_params_info |= (IEEE80211_HT_CAP_AMPDU_DENSITY&0x00);
++ }
++
++ pht_cap->ampdu_params_info |= (IEEE80211_HT_CAP_AMPDU_FACTOR & 0x03); //set Max Rx AMPDU size to 64K
++
++ if(rf_type == RF_1T1R)
++ {
++ pht_cap->supp_mcs_set[0] = 0xff;
++ pht_cap->supp_mcs_set[1] = 0x0;
++ }
++
++ _rtw_memcpy(&pmlmepriv->htpriv.ht_cap, p+2, ie_len);
++
++ }
++
++ //parsing HT_INFO_IE
++ p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _HT_ADD_INFO_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_));
++ if(p && ie_len>0)
++ {
++ pHT_info_ie=p;
++ }
++
++ switch(network_type)
++ {
++ case WIRELESS_11B:
++ pbss_network->NetworkTypeInUse = Ndis802_11DS;
++ break;
++ case WIRELESS_11G:
++ case WIRELESS_11BG:
++ case WIRELESS_11G_24N:
++ case WIRELESS_11BG_24N:
++ pbss_network->NetworkTypeInUse = Ndis802_11OFDM24;
++ break;
++ case WIRELESS_11A:
++ pbss_network->NetworkTypeInUse = Ndis802_11OFDM5;
++ break;
++ default :
++ pbss_network->NetworkTypeInUse = Ndis802_11OFDM24;
++ break;
++ }
++
++ pmlmepriv->cur_network.network_type = network_type;
++
++
++ pmlmepriv->htpriv.ht_option = _FALSE;
++#ifdef CONFIG_80211N_HT
++ if( (psecuritypriv->wpa2_pairwise_cipher&WPA_CIPHER_TKIP) ||
++ (psecuritypriv->wpa_pairwise_cipher&WPA_CIPHER_TKIP))
++ {
++ //todo:
++ //ht_cap = _FALSE;
++ }
++
++ //ht_cap
++ if(pregistrypriv->ht_enable && ht_cap==_TRUE)
++ {
++ pmlmepriv->htpriv.ht_option = _TRUE;
++ pmlmepriv->qospriv.qos_option = 1;
++
++ if(pregistrypriv->ampdu_enable==1)
++ {
++ pmlmepriv->htpriv.ampdu_enable = _TRUE;
++ }
++
++ HT_caps_handler(padapter, (PNDIS_802_11_VARIABLE_IEs)pHT_caps_ie);
++
++ HT_info_handler(padapter, (PNDIS_802_11_VARIABLE_IEs)pHT_info_ie);
++ }
++#endif
++
++
++ pbss_network->Length = get_WLAN_BSSID_EX_sz((WLAN_BSSID_EX *)pbss_network);
++
++ //issue beacon to start bss network
++ start_bss_network(padapter, (u8*)pbss_network);
++
++
++ //alloc sta_info for ap itself
++ psta = rtw_get_stainfo(&padapter->stapriv, pbss_network->MacAddress);
++ if(!psta)
++ {
++ psta = rtw_alloc_stainfo(&padapter->stapriv, pbss_network->MacAddress);
++ if (psta == NULL)
++ {
++ return _FAIL;
++ }
++ }
++ psta->state |= WIFI_AP_STATE; //Aries, add,fix bug of flush_cam_entry at STOP AP mode , 0724
++ rtw_indicate_connect( padapter);
++
++ pmlmepriv->cur_network.join_res = _TRUE;//for check if already set beacon
++
++ //update bc/mc sta_info
++ //update_bmc_sta(padapter);
++
++ return ret;
++
++}
++
++void rtw_set_macaddr_acl(_adapter *padapter, int mode)
++{
++ struct sta_priv *pstapriv = &padapter->stapriv;
++ struct wlan_acl_pool *pacl_list = &pstapriv->acl_list;
++
++ DBG_871X("%s, mode=%d\n", __func__, mode);
++
++ pacl_list->mode = mode;
++}
++
++int rtw_acl_add_sta(_adapter *padapter, u8 *addr)
++{
++ _irqL irqL;
++ _list *plist, *phead;
++ u8 added = _FALSE;
++ int i, ret=0;
++ struct rtw_wlan_acl_node *paclnode;
++ struct sta_priv *pstapriv = &padapter->stapriv;
++ struct wlan_acl_pool *pacl_list = &pstapriv->acl_list;
++ _queue *pacl_node_q =&pacl_list->acl_node_q;
++
++ DBG_871X("%s(acl_num=%d)=" MAC_FMT "\n", __func__, pacl_list->num, MAC_ARG(addr));
++
++ if((NUM_ACL-1) < pacl_list->num)
++ return (-1);
++
++
++ _enter_critical_bh(&(pacl_node_q->lock), &irqL);
++
++ phead = get_list_head(pacl_node_q);
++ plist = get_next(phead);
++
++ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE)
++ {
++ paclnode = LIST_CONTAINOR(plist, struct rtw_wlan_acl_node, list);
++ plist = get_next(plist);
++
++ if(_rtw_memcmp(paclnode->addr, addr, ETH_ALEN))
++ {
++ if(paclnode->valid == _TRUE)
++ {
++ added = _TRUE;
++ DBG_871X("%s, sta has been added\n", __func__);
++ break;
++ }
++ }
++ }
++
++ _exit_critical_bh(&(pacl_node_q->lock), &irqL);
++
++
++ if(added == _TRUE)
++ return ret;
++
++
++ _enter_critical_bh(&(pacl_node_q->lock), &irqL);
++
++ for(i=0; i< NUM_ACL; i++)
++ {
++ paclnode = &pacl_list->aclnode[i];
++
++ if(paclnode->valid == _FALSE)
++ {
++ _rtw_init_listhead(&paclnode->list);
++
++ _rtw_memcpy(paclnode->addr, addr, ETH_ALEN);
++
++ paclnode->valid = _TRUE;
++
++ rtw_list_insert_tail(&paclnode->list, get_list_head(pacl_node_q));
++
++ pacl_list->num++;
++
++ break;
++ }
++ }
++
++ DBG_871X("%s, acl_num=%d\n", __func__, pacl_list->num);
++
++ _exit_critical_bh(&(pacl_node_q->lock), &irqL);
++
++ return ret;
++}
++
++int rtw_acl_remove_sta(_adapter *padapter, u8 *addr)
++{
++ _irqL irqL;
++ _list *plist, *phead;
++ int i, ret=0;
++ struct rtw_wlan_acl_node *paclnode;
++ struct sta_priv *pstapriv = &padapter->stapriv;
++ struct wlan_acl_pool *pacl_list = &pstapriv->acl_list;
++ _queue *pacl_node_q =&pacl_list->acl_node_q;
++
++ DBG_871X("%s(acl_num=%d)=" MAC_FMT "\n", __func__, pacl_list->num, MAC_ARG(addr));
++
++ _enter_critical_bh(&(pacl_node_q->lock), &irqL);
++
++ phead = get_list_head(pacl_node_q);
++ plist = get_next(phead);
++
++ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE)
++ {
++ paclnode = LIST_CONTAINOR(plist, struct rtw_wlan_acl_node, list);
++ plist = get_next(plist);
++
++ if(_rtw_memcmp(paclnode->addr, addr, ETH_ALEN))
++ {
++ if(paclnode->valid == _TRUE)
++ {
++ paclnode->valid = _FALSE;
++
++ rtw_list_delete(&paclnode->list);
++
++ pacl_list->num--;
++ }
++ }
++ }
++
++ _exit_critical_bh(&(pacl_node_q->lock), &irqL);
++
++ DBG_871X("%s, acl_num=%d\n", __func__, pacl_list->num);
++
++ return ret;
++
++}
++
++#ifdef CONFIG_NATIVEAP_MLME
++
++static void update_bcn_fixed_ie(_adapter *padapter)
++{
++ DBG_871X("%s\n", __FUNCTION__);
++
++}
++
++static void update_bcn_erpinfo_ie(_adapter *padapter)
++{
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ WLAN_BSSID_EX *pnetwork = &(pmlmeinfo->network);
++ unsigned char *p, *ie = pnetwork->IEs;
++ u32 len = 0;
++
++ DBG_871X("%s, ERP_enable=%d\n", __FUNCTION__, pmlmeinfo->ERP_enable);
++
++ if(!pmlmeinfo->ERP_enable)
++ return;
++
++ //parsing ERP_IE
++ p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _ERPINFO_IE_, &len, (pnetwork->IELength - _BEACON_IE_OFFSET_));
++ if(p && len>0)
++ {
++ PNDIS_802_11_VARIABLE_IEs pIE = (PNDIS_802_11_VARIABLE_IEs)p;
++
++ if (pmlmepriv->num_sta_non_erp == 1)
++ pIE->data[0] |= RTW_ERP_INFO_NON_ERP_PRESENT|RTW_ERP_INFO_USE_PROTECTION;
++ else
++ pIE->data[0] &= ~(RTW_ERP_INFO_NON_ERP_PRESENT|RTW_ERP_INFO_USE_PROTECTION);
++
++ if(pmlmepriv->num_sta_no_short_preamble > 0)
++ pIE->data[0] |= RTW_ERP_INFO_BARKER_PREAMBLE_MODE;
++ else
++ pIE->data[0] &= ~(RTW_ERP_INFO_BARKER_PREAMBLE_MODE);
++
++ ERP_IE_handler(padapter, pIE);
++ }
++
++}
++
++static void update_bcn_htcap_ie(_adapter *padapter)
++{
++ DBG_871X("%s\n", __FUNCTION__);
++
++}
++
++static void update_bcn_htinfo_ie(_adapter *padapter)
++{
++ DBG_871X("%s\n", __FUNCTION__);
++
++}
++
++static void update_bcn_rsn_ie(_adapter *padapter)
++{
++ DBG_871X("%s\n", __FUNCTION__);
++
++}
++
++static void update_bcn_wpa_ie(_adapter *padapter)
++{
++ DBG_871X("%s\n", __FUNCTION__);
++
++}
++
++static void update_bcn_wmm_ie(_adapter *padapter)
++{
++ DBG_871X("%s\n", __FUNCTION__);
++
++}
++
++static void update_bcn_wps_ie(_adapter *padapter)
++{
++ u8 *pwps_ie=NULL, *pwps_ie_src, *premainder_ie, *pbackup_remainder_ie=NULL;
++ uint wps_ielen=0, wps_offset, remainder_ielen;
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ WLAN_BSSID_EX *pnetwork = &(pmlmeinfo->network);
++ unsigned char *ie = pnetwork->IEs;
++ u32 ielen = pnetwork->IELength;
++
++
++ DBG_871X("%s\n", __FUNCTION__);
++
++ pwps_ie = rtw_get_wps_ie(ie+_FIXED_IE_LENGTH_, ielen-_FIXED_IE_LENGTH_, NULL, &wps_ielen);
++
++ if(pwps_ie==NULL || wps_ielen==0)
++ return;
++
++ wps_offset = (uint)(pwps_ie-ie);
++
++ premainder_ie = pwps_ie + wps_ielen;
++
++ remainder_ielen = ielen - wps_offset - wps_ielen;
++
++ if(remainder_ielen>0)
++ {
++ pbackup_remainder_ie = rtw_malloc(remainder_ielen);
++ if(pbackup_remainder_ie)
++ _rtw_memcpy(pbackup_remainder_ie, premainder_ie, remainder_ielen);
++ }
++
++
++ pwps_ie_src = pmlmepriv->wps_beacon_ie;
++ if(pwps_ie_src == NULL)
++ return;
++
++
++ wps_ielen = (uint)pwps_ie_src[1];//to get ie data len
++ if((wps_offset+wps_ielen+2+remainder_ielen)<=MAX_IE_SZ)
++ {
++ _rtw_memcpy(pwps_ie, pwps_ie_src, wps_ielen+2);
++ pwps_ie += (wps_ielen+2);
++
++ if(pbackup_remainder_ie)
++ _rtw_memcpy(pwps_ie, pbackup_remainder_ie, remainder_ielen);
++
++ //update IELength
++ pnetwork->IELength = wps_offset + (wps_ielen+2) + remainder_ielen;
++ }
++
++ if(pbackup_remainder_ie)
++ rtw_mfree(pbackup_remainder_ie, remainder_ielen);
++
++}
++
++static void update_bcn_p2p_ie(_adapter *padapter)
++{
++
++}
++
++static void update_bcn_vendor_spec_ie(_adapter *padapter, u8*oui)
++{
++ DBG_871X("%s\n", __FUNCTION__);
++
++ if(_rtw_memcmp(RTW_WPA_OUI, oui, 4))
++ {
++ update_bcn_wpa_ie(padapter);
++ }
++ else if(_rtw_memcmp(WMM_OUI, oui, 4))
++ {
++ update_bcn_wmm_ie(padapter);
++ }
++ else if(_rtw_memcmp(WPS_OUI, oui, 4))
++ {
++ update_bcn_wps_ie(padapter);
++ }
++ else if(_rtw_memcmp(P2P_OUI, oui, 4))
++ {
++ update_bcn_p2p_ie(padapter);
++ }
++ else
++ {
++ DBG_871X("unknown OUI type!\n");
++ }
++
++
++}
++
++void update_beacon(_adapter *padapter, u8 ie_id, u8 *oui, u8 tx)
++{
++ _irqL irqL;
++ struct mlme_priv *pmlmepriv;
++ struct mlme_ext_priv *pmlmeext;
++ //struct mlme_ext_info *pmlmeinfo;
++
++ //DBG_871X("%s\n", __FUNCTION__);
++
++ if(!padapter)
++ return;
++
++ pmlmepriv = &(padapter->mlmepriv);
++ pmlmeext = &(padapter->mlmeextpriv);
++ //pmlmeinfo = &(pmlmeext->mlmext_info);
++
++ if(_FALSE == pmlmeext->bstart_bss)
++ return;
++
++ _enter_critical_bh(&pmlmepriv->bcn_update_lock, &irqL);
++
++ switch(ie_id)
++ {
++ case 0xFF:
++
++ update_bcn_fixed_ie(padapter);//8: TimeStamp, 2: Beacon Interval 2:Capability
++
++ break;
++
++ case _TIM_IE_:
++
++ update_BCNTIM(padapter);
++
++ break;
++
++ case _ERPINFO_IE_:
++
++ update_bcn_erpinfo_ie(padapter);
++
++ break;
++
++ case _HT_CAPABILITY_IE_:
++
++ update_bcn_htcap_ie(padapter);
++
++ break;
++
++ case _RSN_IE_2_:
++
++ update_bcn_rsn_ie(padapter);
++
++ break;
++
++ case _HT_ADD_INFO_IE_:
++
++ update_bcn_htinfo_ie(padapter);
++
++ break;
++
++ case _VENDOR_SPECIFIC_IE_:
++
++ update_bcn_vendor_spec_ie(padapter, oui);
++
++ break;
++
++ default:
++ break;
++ }
++
++ pmlmepriv->update_bcn = _TRUE;
++
++ _exit_critical_bh(&pmlmepriv->bcn_update_lock, &irqL);
++
++#ifndef CONFIG_INTERRUPT_BASED_TXBCN
++#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
++ if(tx)
++ {
++ //send_beacon(padapter);//send_beacon must execute on TSR level
++ set_tx_beacon_cmd(padapter);
++ }
++#else
++ {
++ //PCI will issue beacon when BCN interrupt occurs.
++ }
++#endif
++#endif //!CONFIG_INTERRUPT_BASED_TXBCN
++
++}
++
++#ifdef CONFIG_80211N_HT
++
++/*
++op_mode
++Set to 0 (HT pure) under the followign conditions
++ - all STAs in the BSS are 20/40 MHz HT in 20/40 MHz BSS or
++ - all STAs in the BSS are 20 MHz HT in 20 MHz BSS
++Set to 1 (HT non-member protection) if there may be non-HT STAs
++ in both the primary and the secondary channel
++Set to 2 if only HT STAs are associated in BSS,
++ however and at least one 20 MHz HT STA is associated
++Set to 3 (HT mixed mode) when one or more non-HT STAs are associated
++ (currently non-GF HT station is considered as non-HT STA also)
++*/
++static int rtw_ht_operation_update(_adapter *padapter)
++{
++ u16 cur_op_mode, new_op_mode;
++ int op_mode_changes = 0;
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ struct ht_priv *phtpriv_ap = &pmlmepriv->htpriv;
++
++ if(pmlmepriv->htpriv.ht_option == _TRUE)
++ return 0;
++
++ //if (!iface->conf->ieee80211n || iface->conf->ht_op_mode_fixed)
++ // return 0;
++
++ DBG_871X("%s current operation mode=0x%X\n",
++ __FUNCTION__, pmlmepriv->ht_op_mode);
++
++ if (!(pmlmepriv->ht_op_mode & HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT)
++ && pmlmepriv->num_sta_ht_no_gf) {
++ pmlmepriv->ht_op_mode |=
++ HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT;
++ op_mode_changes++;
++ } else if ((pmlmepriv->ht_op_mode &
++ HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT) &&
++ pmlmepriv->num_sta_ht_no_gf == 0) {
++ pmlmepriv->ht_op_mode &=
++ ~HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT;
++ op_mode_changes++;
++ }
++
++ if (!(pmlmepriv->ht_op_mode & HT_INFO_OPERATION_MODE_NON_HT_STA_PRESENT) &&
++ (pmlmepriv->num_sta_no_ht || pmlmepriv->olbc_ht)) {
++ pmlmepriv->ht_op_mode |= HT_INFO_OPERATION_MODE_NON_HT_STA_PRESENT;
++ op_mode_changes++;
++ } else if ((pmlmepriv->ht_op_mode &
++ HT_INFO_OPERATION_MODE_NON_HT_STA_PRESENT) &&
++ (pmlmepriv->num_sta_no_ht == 0 && !pmlmepriv->olbc_ht)) {
++ pmlmepriv->ht_op_mode &=
++ ~HT_INFO_OPERATION_MODE_NON_HT_STA_PRESENT;
++ op_mode_changes++;
++ }
++
++ /* Note: currently we switch to the MIXED op mode if HT non-greenfield
++ * station is associated. Probably it's a theoretical case, since
++ * it looks like all known HT STAs support greenfield.
++ */
++ new_op_mode = 0;
++ if (pmlmepriv->num_sta_no_ht ||
++ (pmlmepriv->ht_op_mode & HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT))
++ new_op_mode = OP_MODE_MIXED;
++ else if ((phtpriv_ap->ht_cap.cap_info & IEEE80211_HT_CAP_SUP_WIDTH)
++ && pmlmepriv->num_sta_ht_20mhz)
++ new_op_mode = OP_MODE_20MHZ_HT_STA_ASSOCED;
++ else if (pmlmepriv->olbc_ht)
++ new_op_mode = OP_MODE_MAY_BE_LEGACY_STAS;
++ else
++ new_op_mode = OP_MODE_PURE;
++
++ cur_op_mode = pmlmepriv->ht_op_mode & HT_INFO_OPERATION_MODE_OP_MODE_MASK;
++ if (cur_op_mode != new_op_mode) {
++ pmlmepriv->ht_op_mode &= ~HT_INFO_OPERATION_MODE_OP_MODE_MASK;
++ pmlmepriv->ht_op_mode |= new_op_mode;
++ op_mode_changes++;
++ }
++
++ DBG_871X("%s new operation mode=0x%X changes=%d\n",
++ __FUNCTION__, pmlmepriv->ht_op_mode, op_mode_changes);
++
++ return op_mode_changes;
++
++}
++
++#endif /* CONFIG_80211N_HT */
++
++void associated_clients_update(_adapter *padapter, u8 updated)
++{
++ //update associcated stations cap.
++ if(updated == _TRUE)
++ {
++ _irqL irqL;
++ _list *phead, *plist;
++ struct sta_info *psta=NULL;
++ struct sta_priv *pstapriv = &padapter->stapriv;
++
++ _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++
++ phead = &pstapriv->asoc_list;
++ plist = get_next(phead);
++
++ //check asoc_queue
++ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE)
++ {
++ psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);
++
++ plist = get_next(plist);
++
++ VCS_update(padapter, psta);
++ }
++
++ _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++
++ }
++
++}
++
++/* called > TSR LEVEL for USB or SDIO Interface*/
++void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta)
++{
++ u8 beacon_updated = _FALSE;
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++
++
++#if 0
++ if (!(psta->capability & WLAN_CAPABILITY_SHORT_PREAMBLE) &&
++ !psta->no_short_preamble_set) {
++ psta->no_short_preamble_set = 1;
++ pmlmepriv->num_sta_no_short_preamble++;
++ if ((pmlmeext->cur_wireless_mode > WIRELESS_11B) &&
++ (pmlmepriv->num_sta_no_short_preamble == 1))
++ ieee802_11_set_beacons(hapd->iface);
++ }
++#endif
++
++
++ if(!(psta->flags & WLAN_STA_SHORT_PREAMBLE))
++ {
++ if(!psta->no_short_preamble_set)
++ {
++ psta->no_short_preamble_set = 1;
++
++ pmlmepriv->num_sta_no_short_preamble++;
++
++ if ((pmlmeext->cur_wireless_mode > WIRELESS_11B) &&
++ (pmlmepriv->num_sta_no_short_preamble == 1))
++ {
++ beacon_updated = _TRUE;
++ update_beacon(padapter, 0xFF, NULL, _TRUE);
++ }
++
++ }
++ }
++ else
++ {
++ if(psta->no_short_preamble_set)
++ {
++ psta->no_short_preamble_set = 0;
++
++ pmlmepriv->num_sta_no_short_preamble--;
++
++ if ((pmlmeext->cur_wireless_mode > WIRELESS_11B) &&
++ (pmlmepriv->num_sta_no_short_preamble == 0))
++ {
++ beacon_updated = _TRUE;
++ update_beacon(padapter, 0xFF, NULL, _TRUE);
++ }
++
++ }
++ }
++
++#if 0
++ if (psta->flags & WLAN_STA_NONERP && !psta->nonerp_set) {
++ psta->nonerp_set = 1;
++ pmlmepriv->num_sta_non_erp++;
++ if (pmlmepriv->num_sta_non_erp == 1)
++ ieee802_11_set_beacons(hapd->iface);
++ }
++#endif
++
++ if(psta->flags & WLAN_STA_NONERP)
++ {
++ if(!psta->nonerp_set)
++ {
++ psta->nonerp_set = 1;
++
++ pmlmepriv->num_sta_non_erp++;
++
++ if (pmlmepriv->num_sta_non_erp == 1)
++ {
++ beacon_updated = _TRUE;
++ update_beacon(padapter, _ERPINFO_IE_, NULL, _TRUE);
++ }
++ }
++
++ }
++ else
++ {
++ if(psta->nonerp_set)
++ {
++ psta->nonerp_set = 0;
++
++ pmlmepriv->num_sta_non_erp--;
++
++ if (pmlmepriv->num_sta_non_erp == 0)
++ {
++ beacon_updated = _TRUE;
++ update_beacon(padapter, _ERPINFO_IE_, NULL, _TRUE);
++ }
++ }
++
++ }
++
++
++#if 0
++ if (!(psta->capability & WLAN_CAPABILITY_SHORT_SLOT) &&
++ !psta->no_short_slot_time_set) {
++ psta->no_short_slot_time_set = 1;
++ pmlmepriv->num_sta_no_short_slot_time++;
++ if ((pmlmeext->cur_wireless_mode > WIRELESS_11B) &&
++ (pmlmepriv->num_sta_no_short_slot_time == 1))
++ ieee802_11_set_beacons(hapd->iface);
++ }
++#endif
++
++ if(!(psta->capability & WLAN_CAPABILITY_SHORT_SLOT))
++ {
++ if(!psta->no_short_slot_time_set)
++ {
++ psta->no_short_slot_time_set = 1;
++
++ pmlmepriv->num_sta_no_short_slot_time++;
++
++ if ((pmlmeext->cur_wireless_mode > WIRELESS_11B) &&
++ (pmlmepriv->num_sta_no_short_slot_time == 1))
++ {
++ beacon_updated = _TRUE;
++ update_beacon(padapter, 0xFF, NULL, _TRUE);
++ }
++
++ }
++ }
++ else
++ {
++ if(psta->no_short_slot_time_set)
++ {
++ psta->no_short_slot_time_set = 0;
++
++ pmlmepriv->num_sta_no_short_slot_time--;
++
++ if ((pmlmeext->cur_wireless_mode > WIRELESS_11B) &&
++ (pmlmepriv->num_sta_no_short_slot_time == 0))
++ {
++ beacon_updated = _TRUE;
++ update_beacon(padapter, 0xFF, NULL, _TRUE);
++ }
++ }
++ }
++
++#ifdef CONFIG_80211N_HT
++
++ if (psta->flags & WLAN_STA_HT)
++ {
++ u16 ht_capab = le16_to_cpu(psta->htpriv.ht_cap.cap_info);
++
++ DBG_871X("HT: STA " MAC_FMT " HT Capabilities "
++ "Info: 0x%04x\n", MAC_ARG(psta->hwaddr), ht_capab);
++
++ if (psta->no_ht_set) {
++ psta->no_ht_set = 0;
++ pmlmepriv->num_sta_no_ht--;
++ }
++
++ if ((ht_capab & IEEE80211_HT_CAP_GRN_FLD) == 0) {
++ if (!psta->no_ht_gf_set) {
++ psta->no_ht_gf_set = 1;
++ pmlmepriv->num_sta_ht_no_gf++;
++ }
++ DBG_871X("%s STA " MAC_FMT " - no "
++ "greenfield, num of non-gf stations %d\n",
++ __FUNCTION__, MAC_ARG(psta->hwaddr),
++ pmlmepriv->num_sta_ht_no_gf);
++ }
++
++ if ((ht_capab & IEEE80211_HT_CAP_SUP_WIDTH) == 0) {
++ if (!psta->ht_20mhz_set) {
++ psta->ht_20mhz_set = 1;
++ pmlmepriv->num_sta_ht_20mhz++;
++ }
++ DBG_871X("%s STA " MAC_FMT " - 20 MHz HT, "
++ "num of 20MHz HT STAs %d\n",
++ __FUNCTION__, MAC_ARG(psta->hwaddr),
++ pmlmepriv->num_sta_ht_20mhz);
++ }
++
++ }
++ else
++ {
++ if (!psta->no_ht_set) {
++ psta->no_ht_set = 1;
++ pmlmepriv->num_sta_no_ht++;
++ }
++ if(pmlmepriv->htpriv.ht_option == _TRUE) {
++ DBG_871X("%s STA " MAC_FMT
++ " - no HT, num of non-HT stations %d\n",
++ __FUNCTION__, MAC_ARG(psta->hwaddr),
++ pmlmepriv->num_sta_no_ht);
++ }
++ }
++
++ if (rtw_ht_operation_update(padapter) > 0)
++ {
++ update_beacon(padapter, _HT_CAPABILITY_IE_, NULL, _FALSE);
++ update_beacon(padapter, _HT_ADD_INFO_IE_, NULL, _TRUE);
++ }
++
++#endif /* CONFIG_80211N_HT */
++
++ //update associcated stations cap.
++ associated_clients_update(padapter, beacon_updated);
++
++ DBG_871X("%s, updated=%d\n", __func__, beacon_updated);
++
++}
++
++u8 bss_cap_update_on_sta_leave(_adapter *padapter, struct sta_info *psta)
++{
++ u8 beacon_updated = _FALSE;
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++
++ if(!psta)
++ return beacon_updated;
++
++ if (psta->no_short_preamble_set) {
++ psta->no_short_preamble_set = 0;
++ pmlmepriv->num_sta_no_short_preamble--;
++ if (pmlmeext->cur_wireless_mode > WIRELESS_11B
++ && pmlmepriv->num_sta_no_short_preamble == 0)
++ {
++ beacon_updated = _TRUE;
++ update_beacon(padapter, 0xFF, NULL, _TRUE);
++ }
++ }
++
++ if (psta->nonerp_set) {
++ psta->nonerp_set = 0;
++ pmlmepriv->num_sta_non_erp--;
++ if (pmlmepriv->num_sta_non_erp == 0)
++ {
++ beacon_updated = _TRUE;
++ update_beacon(padapter, _ERPINFO_IE_, NULL, _TRUE);
++ }
++ }
++
++ if (psta->no_short_slot_time_set) {
++ psta->no_short_slot_time_set = 0;
++ pmlmepriv->num_sta_no_short_slot_time--;
++ if (pmlmeext->cur_wireless_mode > WIRELESS_11B
++ && pmlmepriv->num_sta_no_short_slot_time == 0)
++ {
++ beacon_updated = _TRUE;
++ update_beacon(padapter, 0xFF, NULL, _TRUE);
++ }
++ }
++
++#ifdef CONFIG_80211N_HT
++
++ if (psta->no_ht_gf_set) {
++ psta->no_ht_gf_set = 0;
++ pmlmepriv->num_sta_ht_no_gf--;
++ }
++
++ if (psta->no_ht_set) {
++ psta->no_ht_set = 0;
++ pmlmepriv->num_sta_no_ht--;
++ }
++
++ if (psta->ht_20mhz_set) {
++ psta->ht_20mhz_set = 0;
++ pmlmepriv->num_sta_ht_20mhz--;
++ }
++
++ if (rtw_ht_operation_update(padapter) > 0)
++ {
++ update_beacon(padapter, _HT_CAPABILITY_IE_, NULL, _FALSE);
++ update_beacon(padapter, _HT_ADD_INFO_IE_, NULL, _TRUE);
++ }
++
++#endif /* CONFIG_80211N_HT */
++
++ //update associcated stations cap.
++ //associated_clients_update(padapter, beacon_updated); //move it to avoid deadlock
++
++ DBG_871X("%s, updated=%d\n", __func__, beacon_updated);
++
++ return beacon_updated;
++
++}
++
++u8 ap_free_sta(_adapter *padapter, struct sta_info *psta, bool active, u16 reason)
++{
++ _irqL irqL;
++ u8 beacon_updated = _FALSE;
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++ struct sta_priv *pstapriv = &padapter->stapriv;
++
++ if(!psta)
++ return beacon_updated;
++
++ if (active == _TRUE)
++ {
++#ifdef CONFIG_80211N_HT
++ //tear down Rx AMPDU
++ send_delba(padapter, 0, psta->hwaddr);// recipient
++
++ //tear down TX AMPDU
++ send_delba(padapter, 1, psta->hwaddr);// // originator
++
++#endif //CONFIG_80211N_HT
++
++ issue_deauth(padapter, psta->hwaddr, reason);
++ }
++
++ psta->htpriv.agg_enable_bitmap = 0x0;//reset
++ psta->htpriv.candidate_tid_bitmap = 0x0;//reset
++
++
++ //report_del_sta_event(padapter, psta->hwaddr, reason);
++
++ //clear cam entry / key
++ //clear_cam_entry(padapter, (psta->mac_id + 3));
++ rtw_clearstakey_cmd(padapter, (u8*)psta, (u8)(psta->mac_id + 3), _TRUE);
++
++
++ _enter_critical_bh(&psta->lock, &irqL);
++ psta->state &= ~_FW_LINKED;
++ _exit_critical_bh(&psta->lock, &irqL);
++
++ #ifdef CONFIG_IOCTL_CFG80211
++ if (1) {
++ #ifdef COMPAT_KERNEL_RELEASE
++ rtw_cfg80211_indicate_sta_disassoc(padapter, psta->hwaddr, reason);
++ #elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER)
++ rtw_cfg80211_indicate_sta_disassoc(padapter, psta->hwaddr, reason);
++ #else //(LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER)
++ /* will call rtw_cfg80211_indicate_sta_disassoc() in cmd_thread for old API context */
++ #endif //(LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER)
++ } else
++ #endif //CONFIG_IOCTL_CFG80211
++ {
++ rtw_indicate_sta_disassoc_event(padapter, psta);
++ }
++
++ report_del_sta_event(padapter, psta->hwaddr, reason);
++
++ beacon_updated = bss_cap_update_on_sta_leave(padapter, psta);
++
++ _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL);
++ rtw_free_stainfo(padapter, psta);
++ _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);
++
++
++ return beacon_updated;
++
++}
++
++int rtw_ap_inform_ch_switch(_adapter *padapter, u8 new_ch, u8 ch_offset)
++{
++ _irqL irqL;
++ _list *phead, *plist;
++ int ret=0;
++ struct sta_info *psta = NULL;
++ struct sta_priv *pstapriv = &padapter->stapriv;
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ u8 bc_addr[ETH_ALEN] = {0xff,0xff,0xff,0xff,0xff,0xff};
++
++ if((pmlmeinfo->state&0x03) != WIFI_FW_AP_STATE)
++ return ret;
++
++ DBG_871X(FUNC_NDEV_FMT" with ch:%u, offset:%u\n",
++ FUNC_NDEV_ARG(padapter->pnetdev), new_ch, ch_offset);
++
++ _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++ phead = &pstapriv->asoc_list;
++ plist = get_next(phead);
++
++ /* for each sta in asoc_queue */
++ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE)
++ {
++ psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);
++ plist = get_next(plist);
++
++ issue_action_spct_ch_switch(padapter, psta->hwaddr, new_ch, ch_offset);
++ psta->expire_to = ((pstapriv->expire_to * 2) > 5) ? 5 : (pstapriv->expire_to * 2);
++ }
++ _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++
++ issue_action_spct_ch_switch(padapter, bc_addr, new_ch, ch_offset);
++
++ return ret;
++}
++
++int rtw_sta_flush(_adapter *padapter)
++{
++ _irqL irqL;
++ _list *phead, *plist;
++ int ret=0;
++ struct sta_info *psta = NULL;
++ struct sta_priv *pstapriv = &padapter->stapriv;
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ u8 bc_addr[ETH_ALEN] = {0xff,0xff,0xff,0xff,0xff,0xff};
++ u8 chk_alive_num = 0;
++ char chk_alive_list[NUM_STA];
++ int i;
++
++ DBG_871X(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(padapter->pnetdev));
++
++ if((pmlmeinfo->state&0x03) != WIFI_FW_AP_STATE)
++ return ret;
++
++ _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++ phead = &pstapriv->asoc_list;
++ plist = get_next(phead);
++
++ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
++ int stainfo_offset;
++
++ psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);
++ plist = get_next(plist);
++
++ /* Remove sta from asoc_list */
++ rtw_list_delete(&psta->asoc_list);
++ pstapriv->asoc_list_cnt--;
++
++ /* Keep sta for ap_free_sta() beyond this asoc_list loop */
++ stainfo_offset = rtw_stainfo_offset(pstapriv, psta);
++ if (stainfo_offset_valid(stainfo_offset)) {
++ chk_alive_list[chk_alive_num++] = stainfo_offset;
++ }
++ }
++ _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++
++
++ /* For each sta in chk_alive_list, call ap_free_sta */
++ for (i = 0; i < chk_alive_num; i++) {
++ psta = rtw_get_stainfo_by_offset(pstapriv, chk_alive_list[i]);
++ ap_free_sta(padapter, psta, _TRUE, WLAN_REASON_DEAUTH_LEAVING);
++ }
++
++ issue_deauth(padapter, bc_addr, WLAN_REASON_DEAUTH_LEAVING);
++
++ associated_clients_update(padapter, _TRUE);
++
++ return ret;
++
++}
++
++/* called > TSR LEVEL for USB or SDIO Interface*/
++void sta_info_update(_adapter *padapter, struct sta_info *psta)
++{
++ int flags = psta->flags;
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++
++
++ //update wmm cap.
++ if(WLAN_STA_WME&flags)
++ psta->qos_option = 1;
++ else
++ psta->qos_option = 0;
++
++ if(pmlmepriv->qospriv.qos_option == 0)
++ psta->qos_option = 0;
++
++
++#ifdef CONFIG_80211N_HT
++ //update 802.11n ht cap.
++ if(WLAN_STA_HT&flags)
++ {
++ psta->htpriv.ht_option = _TRUE;
++ psta->qos_option = 1;
++ }
++ else
++ {
++ psta->htpriv.ht_option = _FALSE;
++ }
++
++ if(pmlmepriv->htpriv.ht_option == _FALSE)
++ psta->htpriv.ht_option = _FALSE;
++#endif
++
++
++ update_sta_info_apmode(padapter, psta);
++
++
++}
++
++/* called >= TSR LEVEL for USB or SDIO Interface*/
++void ap_sta_info_defer_update(_adapter *padapter, struct sta_info *psta)
++{
++ if(psta->state & _FW_LINKED)
++ {
++ //add ratid
++ add_RATid(padapter, psta);
++ }
++}
++
++/* restore hw setting from sw data structures */
++void rtw_ap_restore_network(_adapter *padapter)
++{
++ struct mlme_priv *mlmepriv = &padapter->mlmepriv;
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ struct sta_priv * pstapriv = &padapter->stapriv;
++ struct sta_info *psta;
++ struct security_priv* psecuritypriv=&(padapter->securitypriv);
++ _irqL irqL;
++ _list *phead, *plist;
++ u8 chk_alive_num = 0;
++ char chk_alive_list[NUM_STA];
++ int i;
++
++ rtw_setopmode_cmd(padapter, Ndis802_11APMode);
++
++ set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode);
++
++ start_bss_network(padapter, (u8*)&mlmepriv->cur_network.network);
++
++ if((padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_) ||
++ (padapter->securitypriv.dot11PrivacyAlgrthm == _AES_))
++ {
++ /* restore group key, WEP keys is restored in ips_leave() */
++ rtw_set_key(padapter, psecuritypriv, psecuritypriv->dot118021XGrpKeyid, 0);
++ }
++
++ /* per sta pairwise key and settings */
++ if((padapter->securitypriv.dot11PrivacyAlgrthm != _TKIP_) &&
++ (padapter->securitypriv.dot11PrivacyAlgrthm != _AES_)) {
++ return;
++ }
++
++ _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++
++ phead = &pstapriv->asoc_list;
++ plist = get_next(phead);
++
++ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
++ int stainfo_offset;
++
++ psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);
++ plist = get_next(plist);
++
++ stainfo_offset = rtw_stainfo_offset(pstapriv, psta);
++ if (stainfo_offset_valid(stainfo_offset)) {
++ chk_alive_list[chk_alive_num++] = stainfo_offset;
++ }
++ }
++
++ _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++
++ for (i = 0; i < chk_alive_num; i++) {
++ psta = rtw_get_stainfo_by_offset(pstapriv, chk_alive_list[i]);
++
++ if (psta == NULL) {
++ DBG_871X(FUNC_ADPT_FMT" sta_info is null\n", FUNC_ADPT_ARG(padapter));
++ } else if (psta->state &_FW_LINKED) {
++ Update_RA_Entry(padapter, psta->mac_id);
++ //pairwise key
++ rtw_setstakey_cmd(padapter, (unsigned char *)psta, _TRUE);
++ }
++ }
++
++}
++
++void start_ap_mode(_adapter *padapter)
++{
++ int i;
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ struct sta_priv *pstapriv = &padapter->stapriv;
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct wlan_acl_pool *pacl_list = &pstapriv->acl_list;
++
++ pmlmepriv->update_bcn = _FALSE;
++
++ //init_mlme_ap_info(padapter);
++ pmlmeext->bstart_bss = _FALSE;
++
++ pmlmepriv->num_sta_non_erp = 0;
++
++ pmlmepriv->num_sta_no_short_slot_time = 0;
++
++ pmlmepriv->num_sta_no_short_preamble = 0;
++
++ pmlmepriv->num_sta_ht_no_gf = 0;
++
++ pmlmepriv->num_sta_no_ht = 0;
++
++ pmlmepriv->num_sta_ht_20mhz = 0;
++
++ pmlmepriv->olbc = _FALSE;
++
++ pmlmepriv->olbc_ht = _FALSE;
++
++#ifdef CONFIG_80211N_HT
++ pmlmepriv->ht_op_mode = 0;
++#endif
++
++ for(i=0; i<NUM_STA; i++)
++ pstapriv->sta_aid[i] = NULL;
++
++ pmlmepriv->wps_beacon_ie = NULL;
++ pmlmepriv->wps_probe_resp_ie = NULL;
++ pmlmepriv->wps_assoc_resp_ie = NULL;
++
++ pmlmepriv->p2p_beacon_ie = NULL;
++ pmlmepriv->p2p_probe_resp_ie = NULL;
++
++
++ //for ACL
++ _rtw_init_listhead(&(pacl_list->acl_node_q.queue));
++ pacl_list->num = 0;
++ pacl_list->mode = 0;
++ for(i = 0; i < NUM_ACL; i++)
++ {
++ _rtw_init_listhead(&pacl_list->aclnode[i].list);
++ pacl_list->aclnode[i].valid = _FALSE;
++ }
++
++}
++
++void stop_ap_mode(_adapter *padapter)
++{
++ _irqL irqL;
++ _list *phead, *plist;
++ struct rtw_wlan_acl_node *paclnode;
++ struct sta_info *psta=NULL;
++ struct sta_priv *pstapriv = &padapter->stapriv;
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct wlan_acl_pool *pacl_list = &pstapriv->acl_list;
++ _queue *pacl_node_q =&pacl_list->acl_node_q;
++
++ pmlmepriv->update_bcn = _FALSE;
++ pmlmeext->bstart_bss = _FALSE;
++ //_rtw_spinlock_free(&pmlmepriv->bcn_update_lock);
++
++ //reset and init security priv , this can refine with rtw_reset_securitypriv
++ _rtw_memset((unsigned char *)&padapter->securitypriv, 0, sizeof (struct security_priv));
++ padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeOpen;
++ padapter->securitypriv.ndisencryptstatus = Ndis802_11WEPDisabled;
++
++ //for ACL
++ _enter_critical_bh(&(pacl_node_q->lock), &irqL);
++ phead = get_list_head(pacl_node_q);
++ plist = get_next(phead);
++ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE)
++ {
++ paclnode = LIST_CONTAINOR(plist, struct rtw_wlan_acl_node, list);
++ plist = get_next(plist);
++
++ if(paclnode->valid == _TRUE)
++ {
++ paclnode->valid = _FALSE;
++
++ rtw_list_delete(&paclnode->list);
++
++ pacl_list->num--;
++ }
++ }
++ _exit_critical_bh(&(pacl_node_q->lock), &irqL);
++
++ DBG_871X("%s, free acl_node_queue, num=%d\n", __func__, pacl_list->num);
++
++ rtw_sta_flush(padapter);
++
++ //free_assoc_sta_resources
++ rtw_free_all_stainfo(padapter);
++
++ psta = rtw_get_bcmc_stainfo(padapter);
++ _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL);
++ rtw_free_stainfo(padapter, psta);
++ _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);
++
++ rtw_init_bcmc_stainfo(padapter);
++
++ rtw_free_mlme_priv_ie_data(pmlmepriv);
++
++}
++
++#endif //CONFIG_NATIVEAP_MLME
++#endif //CONFIG_AP_MODE
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/core/rtw_br_ext.c linux-xbian-rpi/drivers/net/wireless/rtl8192cu/core/rtw_br_ext.c
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/core/rtw_br_ext.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/core/rtw_br_ext.c 2015-07-28 01:20:58.301668422 +0200
+@@ -0,0 +1,1699 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#define _RTW_BR_EXT_C_
++
++#ifdef __KERNEL__
++#include <linux/if_arp.h>
++#include <net/ip.h>
++#include <net/ipx.h>
++#include <linux/atalk.h>
++#include <linux/udp.h>
++#include <linux/if_pppox.h>
++#endif
++
++#if 1 // rtw_wifi_driver
++#include <drv_conf.h>
++#include <drv_types.h>
++#include "rtw_br_ext.h"
++#else // rtw_wifi_driver
++#include "./8192cd_cfg.h"
++
++#ifndef __KERNEL__
++#include "./sys-support.h"
++#endif
++
++#include "./8192cd.h"
++#include "./8192cd_headers.h"
++#include "./8192cd_br_ext.h"
++#include "./8192cd_debug.h"
++#endif // rtw_wifi_driver
++
++#ifdef CL_IPV6_PASS
++#ifdef __KERNEL__
++#include <linux/ipv6.h>
++#include <linux/icmpv6.h>
++#include <net/ndisc.h>
++#include <net/checksum.h>
++#endif
++#endif
++
++#ifdef CONFIG_BR_EXT
++
++//#define BR_EXT_DEBUG
++
++#define NAT25_IPV4 01
++#define NAT25_IPV6 02
++#define NAT25_IPX 03
++#define NAT25_APPLE 04
++#define NAT25_PPPOE 05
++
++#define RTL_RELAY_TAG_LEN (ETH_ALEN)
++#define TAG_HDR_LEN 4
++
++#define MAGIC_CODE 0x8186
++#define MAGIC_CODE_LEN 2
++#define WAIT_TIME_PPPOE 5 // waiting time for pppoe server in sec
++
++/*-----------------------------------------------------------------
++ How database records network address:
++ 0 1 2 3 4 5 6 7 8 9 10
++ |----|----|----|----|----|----|----|----|----|----|----|
++ IPv4 |type| | IP addr |
++ IPX |type| Net addr | Node addr |
++ IPX |type| Net addr |Sckt addr|
++ Apple |type| Network |node|
++ PPPoE |type| SID | AC MAC |
++-----------------------------------------------------------------*/
++
++
++//Find a tag in pppoe frame and return the pointer
++static __inline__ unsigned char *__nat25_find_pppoe_tag(struct pppoe_hdr *ph, unsigned short type)
++{
++ unsigned char *cur_ptr, *start_ptr;
++ unsigned short tagLen, tagType;
++
++ start_ptr = cur_ptr = (unsigned char *)ph->tag;
++ while((cur_ptr - start_ptr) < ntohs(ph->length)) {
++ // prevent un-alignment access
++ tagType = (unsigned short)((cur_ptr[0] << 8) + cur_ptr[1]);
++ tagLen = (unsigned short)((cur_ptr[2] << 8) + cur_ptr[3]);
++ if(tagType == type)
++ return cur_ptr;
++ cur_ptr = cur_ptr + TAG_HDR_LEN + tagLen;
++ }
++ return 0;
++}
++
++
++static __inline__ int __nat25_add_pppoe_tag(struct sk_buff *skb, struct pppoe_tag *tag)
++{
++ struct pppoe_hdr *ph = (struct pppoe_hdr *)(skb->data + ETH_HLEN);
++ int data_len;
++
++ data_len = tag->tag_len + TAG_HDR_LEN;
++ if (skb_tailroom(skb) < data_len) {
++ _DEBUG_ERR("skb_tailroom() failed in add SID tag!\n");
++ return -1;
++ }
++
++ skb_put(skb, data_len);
++ // have a room for new tag
++ memmove(((unsigned char *)ph->tag + data_len), (unsigned char *)ph->tag, ntohs(ph->length));
++ ph->length = htons(ntohs(ph->length) + data_len);
++ memcpy((unsigned char *)ph->tag, tag, data_len);
++ return data_len;
++}
++
++static int skb_pull_and_merge(struct sk_buff *skb, unsigned char *src, int len)
++{
++ int tail_len;
++ unsigned long end, tail;
++
++ if ((src+len) > skb_tail_pointer(skb) || skb->len < len)
++ return -1;
++
++ tail = (unsigned long)skb_tail_pointer(skb);
++ end = (unsigned long)src+len;
++ if (tail < end)
++ return -1;
++
++ tail_len = (int)(tail-end);
++ if (tail_len > 0)
++ memmove(src, src+len, tail_len);
++
++ skb_trim(skb, skb->len-len);
++ return 0;
++}
++
++static __inline__ unsigned long __nat25_timeout(_adapter *priv)
++{
++ unsigned long timeout;
++
++ timeout = jiffies - NAT25_AGEING_TIME*HZ;
++
++ return timeout;
++}
++
++
++static __inline__ int __nat25_has_expired(_adapter *priv,
++ struct nat25_network_db_entry *fdb)
++{
++ if(time_before_eq(fdb->ageing_timer, __nat25_timeout(priv)))
++ return 1;
++
++ return 0;
++}
++
++
++static __inline__ void __nat25_generate_ipv4_network_addr(unsigned char *networkAddr,
++ unsigned int *ipAddr)
++{
++ memset(networkAddr, 0, MAX_NETWORK_ADDR_LEN);
++
++ networkAddr[0] = NAT25_IPV4;
++ memcpy(networkAddr+7, (unsigned char *)ipAddr, 4);
++}
++
++
++static __inline__ void __nat25_generate_ipx_network_addr_with_node(unsigned char *networkAddr,
++ unsigned int *ipxNetAddr, unsigned char *ipxNodeAddr)
++{
++ memset(networkAddr, 0, MAX_NETWORK_ADDR_LEN);
++
++ networkAddr[0] = NAT25_IPX;
++ memcpy(networkAddr+1, (unsigned char *)ipxNetAddr, 4);
++ memcpy(networkAddr+5, ipxNodeAddr, 6);
++}
++
++
++static __inline__ void __nat25_generate_ipx_network_addr_with_socket(unsigned char *networkAddr,
++ unsigned int *ipxNetAddr, unsigned short *ipxSocketAddr)
++{
++ memset(networkAddr, 0, MAX_NETWORK_ADDR_LEN);
++
++ networkAddr[0] = NAT25_IPX;
++ memcpy(networkAddr+1, (unsigned char *)ipxNetAddr, 4);
++ memcpy(networkAddr+5, (unsigned char *)ipxSocketAddr, 2);
++}
++
++
++static __inline__ void __nat25_generate_apple_network_addr(unsigned char *networkAddr,
++ unsigned short *network, unsigned char *node)
++{
++ memset(networkAddr, 0, MAX_NETWORK_ADDR_LEN);
++
++ networkAddr[0] = NAT25_APPLE;
++ memcpy(networkAddr+1, (unsigned char *)network, 2);
++ networkAddr[3] = *node;
++}
++
++
++static __inline__ void __nat25_generate_pppoe_network_addr(unsigned char *networkAddr,
++ unsigned char *ac_mac, unsigned short *sid)
++{
++ memset(networkAddr, 0, MAX_NETWORK_ADDR_LEN);
++
++ networkAddr[0] = NAT25_PPPOE;
++ memcpy(networkAddr+1, (unsigned char *)sid, 2);
++ memcpy(networkAddr+3, (unsigned char *)ac_mac, 6);
++}
++
++
++#ifdef CL_IPV6_PASS
++static void __nat25_generate_ipv6_network_addr(unsigned char *networkAddr,
++ unsigned int *ipAddr)
++{
++ memset(networkAddr, 0, MAX_NETWORK_ADDR_LEN);
++
++ networkAddr[0] = NAT25_IPV6;
++ memcpy(networkAddr+1, (unsigned char *)ipAddr, 16);
++}
++
++
++static unsigned char *scan_tlv(unsigned char *data, int len, unsigned char tag, unsigned char len8b)
++{
++ while (len > 0) {
++ if (*data == tag && *(data+1) == len8b && len >= len8b*8)
++ return data+2;
++
++ len -= (*(data+1))*8;
++ data += (*(data+1))*8;
++ }
++ return NULL;
++}
++
++
++static int update_nd_link_layer_addr(unsigned char *data, int len, unsigned char *replace_mac)
++{
++ struct icmp6hdr *icmphdr = (struct icmp6hdr *)data;
++ unsigned char *mac;
++
++ if (icmphdr->icmp6_type == NDISC_ROUTER_SOLICITATION) {
++ if (len >= 8) {
++ mac = scan_tlv(&data[8], len-8, 1, 1);
++ if (mac) {
++ _DEBUG_INFO("Router Solicitation, replace MAC From: %02x:%02x:%02x:%02x:%02x:%02x, To: %02x:%02x:%02x:%02x:%02x:%02x\n",
++ mac[0],mac[1],mac[2],mac[3],mac[4],mac[5],
++ replace_mac[0],replace_mac[1],replace_mac[2],replace_mac[3],replace_mac[4],replace_mac[5]);
++ memcpy(mac, replace_mac, 6);
++ return 1;
++ }
++ }
++ }
++ else if (icmphdr->icmp6_type == NDISC_ROUTER_ADVERTISEMENT) {
++ if (len >= 16) {
++ mac = scan_tlv(&data[16], len-16, 1, 1);
++ if (mac) {
++ _DEBUG_INFO("Router Advertisement, replace MAC From: %02x:%02x:%02x:%02x:%02x:%02x, To: %02x:%02x:%02x:%02x:%02x:%02x\n",
++ mac[0],mac[1],mac[2],mac[3],mac[4],mac[5],
++ replace_mac[0],replace_mac[1],replace_mac[2],replace_mac[3],replace_mac[4],replace_mac[5]);
++ memcpy(mac, replace_mac, 6);
++ return 1;
++ }
++ }
++ }
++ else if (icmphdr->icmp6_type == NDISC_NEIGHBOUR_SOLICITATION) {
++ if (len >= 24) {
++ mac = scan_tlv(&data[24], len-24, 1, 1);
++ if (mac) {
++ _DEBUG_INFO("Neighbor Solicitation, replace MAC From: %02x:%02x:%02x:%02x:%02x:%02x, To: %02x:%02x:%02x:%02x:%02x:%02x\n",
++ mac[0],mac[1],mac[2],mac[3],mac[4],mac[5],
++ replace_mac[0],replace_mac[1],replace_mac[2],replace_mac[3],replace_mac[4],replace_mac[5]);
++ memcpy(mac, replace_mac, 6);
++ return 1;
++ }
++ }
++ }
++ else if (icmphdr->icmp6_type == NDISC_NEIGHBOUR_ADVERTISEMENT) {
++ if (len >= 24) {
++ mac = scan_tlv(&data[24], len-24, 2, 1);
++ if (mac) {
++ _DEBUG_INFO("Neighbor Advertisement, replace MAC From: %02x:%02x:%02x:%02x:%02x:%02x, To: %02x:%02x:%02x:%02x:%02x:%02x\n",
++ mac[0],mac[1],mac[2],mac[3],mac[4],mac[5],
++ replace_mac[0],replace_mac[1],replace_mac[2],replace_mac[3],replace_mac[4],replace_mac[5]);
++ memcpy(mac, replace_mac, 6);
++ return 1;
++ }
++ }
++ }
++ else if (icmphdr->icmp6_type == NDISC_REDIRECT) {
++ if (len >= 40) {
++ mac = scan_tlv(&data[40], len-40, 2, 1);
++ if (mac) {
++ _DEBUG_INFO("Redirect, replace MAC From: %02x:%02x:%02x:%02x:%02x:%02x, To: %02x:%02x:%02x:%02x:%02x:%02x\n",
++ mac[0],mac[1],mac[2],mac[3],mac[4],mac[5],
++ replace_mac[0],replace_mac[1],replace_mac[2],replace_mac[3],replace_mac[4],replace_mac[5]);
++ memcpy(mac, replace_mac, 6);
++ return 1;
++ }
++ }
++ }
++ return 0;
++}
++
++
++static void convert_ipv6_mac_to_mc(struct sk_buff *skb)
++{
++ struct ipv6hdr *iph = (struct ipv6hdr *)(skb->data + ETH_HLEN);
++ unsigned char *dst_mac = skb->data;
++
++ //dst_mac[0] = 0xff;
++ //dst_mac[1] = 0xff;
++ /*modified by qinjunjie,ipv6 multicast address ix 0x33-33-xx-xx-xx-xx*/
++ dst_mac[0] = 0x33;
++ dst_mac[1] = 0x33;
++ memcpy(&dst_mac[2], &iph->daddr.s6_addr32[3], 4);
++ #if defined(__LINUX_2_6__)
++ /*modified by qinjunjie,warning:should not remove next line*/
++ skb->pkt_type = PACKET_MULTICAST;
++ #endif
++}
++#endif /* CL_IPV6_PASS */
++
++
++static __inline__ int __nat25_network_hash(unsigned char *networkAddr)
++{
++ if(networkAddr[0] == NAT25_IPV4)
++ {
++ unsigned long x;
++
++ x = networkAddr[7] ^ networkAddr[8] ^ networkAddr[9] ^ networkAddr[10];
++
++ return x & (NAT25_HASH_SIZE - 1);
++ }
++ else if(networkAddr[0] == NAT25_IPX)
++ {
++ unsigned long x;
++
++ x = networkAddr[1] ^ networkAddr[2] ^ networkAddr[3] ^ networkAddr[4] ^ networkAddr[5] ^
++ networkAddr[6] ^ networkAddr[7] ^ networkAddr[8] ^ networkAddr[9] ^ networkAddr[10];
++
++ return x & (NAT25_HASH_SIZE - 1);
++ }
++ else if(networkAddr[0] == NAT25_APPLE)
++ {
++ unsigned long x;
++
++ x = networkAddr[1] ^ networkAddr[2] ^ networkAddr[3];
++
++ return x & (NAT25_HASH_SIZE - 1);
++ }
++ else if(networkAddr[0] == NAT25_PPPOE)
++ {
++ unsigned long x;
++
++ x = networkAddr[0] ^ networkAddr[1] ^ networkAddr[2] ^ networkAddr[3] ^ networkAddr[4] ^ networkAddr[5] ^ networkAddr[6] ^ networkAddr[7] ^ networkAddr[8];
++
++ return x & (NAT25_HASH_SIZE - 1);
++ }
++#ifdef CL_IPV6_PASS
++ else if(networkAddr[0] == NAT25_IPV6)
++ {
++ unsigned long x;
++
++ x = networkAddr[1] ^ networkAddr[2] ^ networkAddr[3] ^ networkAddr[4] ^ networkAddr[5] ^
++ networkAddr[6] ^ networkAddr[7] ^ networkAddr[8] ^ networkAddr[9] ^ networkAddr[10] ^
++ networkAddr[11] ^ networkAddr[12] ^ networkAddr[13] ^ networkAddr[14] ^ networkAddr[15] ^
++ networkAddr[16];
++
++ return x & (NAT25_HASH_SIZE - 1);
++ }
++#endif
++ else
++ {
++ unsigned long x = 0;
++ int i;
++
++ for (i=0; i<MAX_NETWORK_ADDR_LEN; i++)
++ x ^= networkAddr[i];
++
++ return x & (NAT25_HASH_SIZE - 1);
++ }
++}
++
++
++static __inline__ void __network_hash_link(_adapter *priv,
++ struct nat25_network_db_entry *ent, int hash)
++{
++ // Caller must _enter_critical_bh already!
++ //_irqL irqL;
++ //_enter_critical_bh(&priv->br_ext_lock, &irqL);
++
++ ent->next_hash = priv->nethash[hash];
++ if(ent->next_hash != NULL)
++ ent->next_hash->pprev_hash = &ent->next_hash;
++ priv->nethash[hash] = ent;
++ ent->pprev_hash = &priv->nethash[hash];
++
++ //_exit_critical_bh(&priv->br_ext_lock, &irqL);
++}
++
++
++static __inline__ void __network_hash_unlink(struct nat25_network_db_entry *ent)
++{
++ // Caller must _enter_critical_bh already!
++ //_irqL irqL;
++ //_enter_critical_bh(&priv->br_ext_lock, &irqL);
++
++ *(ent->pprev_hash) = ent->next_hash;
++ if(ent->next_hash != NULL)
++ ent->next_hash->pprev_hash = ent->pprev_hash;
++ ent->next_hash = NULL;
++ ent->pprev_hash = NULL;
++
++ //_exit_critical_bh(&priv->br_ext_lock, &irqL);
++}
++
++
++static int __nat25_db_network_lookup_and_replace(_adapter *priv,
++ struct sk_buff *skb, unsigned char *networkAddr)
++{
++ struct nat25_network_db_entry *db;
++ _irqL irqL;
++ _enter_critical_bh(&priv->br_ext_lock, &irqL);
++
++ db = priv->nethash[__nat25_network_hash(networkAddr)];
++ while (db != NULL)
++ {
++ if(!memcmp(db->networkAddr, networkAddr, MAX_NETWORK_ADDR_LEN))
++ {
++ if(!__nat25_has_expired(priv, db))
++ {
++ // replace the destination mac address
++ memcpy(skb->data, db->macAddr, ETH_ALEN);
++ atomic_inc(&db->use_count);
++
++#ifdef CL_IPV6_PASS
++ DEBUG_INFO("NAT25: Lookup M:%02x%02x%02x%02x%02x%02x N:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x"
++ "%02x%02x%02x%02x%02x%02x\n",
++ db->macAddr[0],
++ db->macAddr[1],
++ db->macAddr[2],
++ db->macAddr[3],
++ db->macAddr[4],
++ db->macAddr[5],
++ db->networkAddr[0],
++ db->networkAddr[1],
++ db->networkAddr[2],
++ db->networkAddr[3],
++ db->networkAddr[4],
++ db->networkAddr[5],
++ db->networkAddr[6],
++ db->networkAddr[7],
++ db->networkAddr[8],
++ db->networkAddr[9],
++ db->networkAddr[10],
++ db->networkAddr[11],
++ db->networkAddr[12],
++ db->networkAddr[13],
++ db->networkAddr[14],
++ db->networkAddr[15],
++ db->networkAddr[16]);
++#else
++ DEBUG_INFO("NAT25: Lookup M:%02x%02x%02x%02x%02x%02x N:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\n",
++ db->macAddr[0],
++ db->macAddr[1],
++ db->macAddr[2],
++ db->macAddr[3],
++ db->macAddr[4],
++ db->macAddr[5],
++ db->networkAddr[0],
++ db->networkAddr[1],
++ db->networkAddr[2],
++ db->networkAddr[3],
++ db->networkAddr[4],
++ db->networkAddr[5],
++ db->networkAddr[6],
++ db->networkAddr[7],
++ db->networkAddr[8],
++ db->networkAddr[9],
++ db->networkAddr[10]);
++#endif
++ }
++ _exit_critical_bh(&priv->br_ext_lock, &irqL);
++ return 1;
++ }
++
++ db = db->next_hash;
++ }
++
++ _exit_critical_bh(&priv->br_ext_lock, &irqL);
++ return 0;
++}
++
++
++static void __nat25_db_network_insert(_adapter *priv,
++ unsigned char *macAddr, unsigned char *networkAddr)
++{
++ struct nat25_network_db_entry *db;
++ int hash;
++ _irqL irqL;
++ _enter_critical_bh(&priv->br_ext_lock, &irqL);
++
++ hash = __nat25_network_hash(networkAddr);
++ db = priv->nethash[hash];
++ while (db != NULL)
++ {
++ if(!memcmp(db->networkAddr, networkAddr, MAX_NETWORK_ADDR_LEN))
++ {
++ memcpy(db->macAddr, macAddr, ETH_ALEN);
++ db->ageing_timer = jiffies;
++ _exit_critical_bh(&priv->br_ext_lock, &irqL);
++ return;
++ }
++
++ db = db->next_hash;
++ }
++
++ db = (struct nat25_network_db_entry *) rtw_malloc(sizeof(*db));
++ if(db == NULL) {
++ _exit_critical_bh(&priv->br_ext_lock, &irqL);
++ return;
++ }
++
++ memcpy(db->networkAddr, networkAddr, MAX_NETWORK_ADDR_LEN);
++ memcpy(db->macAddr, macAddr, ETH_ALEN);
++ atomic_set(&db->use_count, 1);
++ db->ageing_timer = jiffies;
++
++ __network_hash_link(priv, db, hash);
++
++ _exit_critical_bh(&priv->br_ext_lock, &irqL);
++}
++
++
++static void __nat25_db_print(_adapter *priv)
++{
++ _irqL irqL;
++ _enter_critical_bh(&priv->br_ext_lock, &irqL);
++
++#ifdef BR_EXT_DEBUG
++ static int counter = 0;
++ int i, j;
++ struct nat25_network_db_entry *db;
++
++ counter++;
++ if((counter % 16) != 0)
++ return;
++
++ for(i=0, j=0; i<NAT25_HASH_SIZE; i++)
++ {
++ db = priv->nethash[i];
++
++ while (db != NULL)
++ {
++#ifdef CL_IPV6_PASS
++ panic_printk("NAT25: DB(%d) H(%02d) C(%d) M:%02x%02x%02x%02x%02x%02x N:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x"
++ "%02x%02x%02x%02x%02x%02x\n",
++ j,
++ i,
++ atomic_read(&db->use_count),
++ db->macAddr[0],
++ db->macAddr[1],
++ db->macAddr[2],
++ db->macAddr[3],
++ db->macAddr[4],
++ db->macAddr[5],
++ db->networkAddr[0],
++ db->networkAddr[1],
++ db->networkAddr[2],
++ db->networkAddr[3],
++ db->networkAddr[4],
++ db->networkAddr[5],
++ db->networkAddr[6],
++ db->networkAddr[7],
++ db->networkAddr[8],
++ db->networkAddr[9],
++ db->networkAddr[10],
++ db->networkAddr[11],
++ db->networkAddr[12],
++ db->networkAddr[13],
++ db->networkAddr[14],
++ db->networkAddr[15],
++ db->networkAddr[16]);
++#else
++ panic_printk("NAT25: DB(%d) H(%02d) C(%d) M:%02x%02x%02x%02x%02x%02x N:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\n",
++ j,
++ i,
++ atomic_read(&db->use_count),
++ db->macAddr[0],
++ db->macAddr[1],
++ db->macAddr[2],
++ db->macAddr[3],
++ db->macAddr[4],
++ db->macAddr[5],
++ db->networkAddr[0],
++ db->networkAddr[1],
++ db->networkAddr[2],
++ db->networkAddr[3],
++ db->networkAddr[4],
++ db->networkAddr[5],
++ db->networkAddr[6],
++ db->networkAddr[7],
++ db->networkAddr[8],
++ db->networkAddr[9],
++ db->networkAddr[10]);
++#endif
++ j++;
++
++ db = db->next_hash;
++ }
++ }
++#endif
++
++ _exit_critical_bh(&priv->br_ext_lock, &irqL);
++}
++
++
++
++
++/*
++ * NAT2.5 interface
++ */
++
++void nat25_db_cleanup(_adapter *priv)
++{
++ int i;
++ _irqL irqL;
++ _enter_critical_bh(&priv->br_ext_lock, &irqL);
++
++ for(i=0; i<NAT25_HASH_SIZE; i++)
++ {
++ struct nat25_network_db_entry *f;
++ f = priv->nethash[i];
++ while (f != NULL) {
++ struct nat25_network_db_entry *g;
++
++ g = f->next_hash;
++ if(priv->scdb_entry == f)
++ {
++ memset(priv->scdb_mac, 0, ETH_ALEN);
++ memset(priv->scdb_ip, 0, 4);
++ priv->scdb_entry = NULL;
++ }
++ __network_hash_unlink(f);
++ rtw_mfree((u8 *) f, sizeof(struct nat25_network_db_entry));
++
++ f = g;
++ }
++ }
++
++ _exit_critical_bh(&priv->br_ext_lock, &irqL);
++}
++
++
++void nat25_db_expire(_adapter *priv)
++{
++ int i;
++ _irqL irqL;
++ _enter_critical_bh(&priv->br_ext_lock, &irqL);
++
++ //if(!priv->ethBrExtInfo.nat25_disable)
++ {
++ for (i=0; i<NAT25_HASH_SIZE; i++)
++ {
++ struct nat25_network_db_entry *f;
++ f = priv->nethash[i];
++
++ while (f != NULL)
++ {
++ struct nat25_network_db_entry *g;
++ g = f->next_hash;
++
++ if(__nat25_has_expired(priv, f))
++ {
++ if(atomic_dec_and_test(&f->use_count))
++ {
++#ifdef BR_EXT_DEBUG
++#ifdef CL_IPV6_PASS
++ panic_printk("NAT25 Expire H(%02d) M:%02x%02x%02x%02x%02x%02x N:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x"
++ "%02x%02x%02x%02x%02x%02x\n",
++ i,
++ f->macAddr[0],
++ f->macAddr[1],
++ f->macAddr[2],
++ f->macAddr[3],
++ f->macAddr[4],
++ f->macAddr[5],
++ f->networkAddr[0],
++ f->networkAddr[1],
++ f->networkAddr[2],
++ f->networkAddr[3],
++ f->networkAddr[4],
++ f->networkAddr[5],
++ f->networkAddr[6],
++ f->networkAddr[7],
++ f->networkAddr[8],
++ f->networkAddr[9],
++ f->networkAddr[10],
++ f->networkAddr[11],
++ f->networkAddr[12],
++ f->networkAddr[13],
++ f->networkAddr[14],
++ f->networkAddr[15],
++ f->networkAddr[16]);
++#else
++
++ panic_printk("NAT25 Expire H(%02d) M:%02x%02x%02x%02x%02x%02x N:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\n",
++ i,
++ f->macAddr[0],
++ f->macAddr[1],
++ f->macAddr[2],
++ f->macAddr[3],
++ f->macAddr[4],
++ f->macAddr[5],
++ f->networkAddr[0],
++ f->networkAddr[1],
++ f->networkAddr[2],
++ f->networkAddr[3],
++ f->networkAddr[4],
++ f->networkAddr[5],
++ f->networkAddr[6],
++ f->networkAddr[7],
++ f->networkAddr[8],
++ f->networkAddr[9],
++ f->networkAddr[10]);
++#endif
++#endif
++ if(priv->scdb_entry == f)
++ {
++ memset(priv->scdb_mac, 0, ETH_ALEN);
++ memset(priv->scdb_ip, 0, 4);
++ priv->scdb_entry = NULL;
++ }
++ __network_hash_unlink(f);
++ rtw_mfree((u8 *) f, sizeof(struct nat25_network_db_entry));
++ }
++ }
++
++ f = g;
++ }
++ }
++ }
++
++ _exit_critical_bh(&priv->br_ext_lock, &irqL);
++}
++
++
++#ifdef SUPPORT_TX_MCAST2UNI
++static int checkIPMcAndReplace(_adapter *priv, struct sk_buff *skb, unsigned int *dst_ip)
++{
++ struct stat_info *pstat;
++ struct list_head *phead, *plist;
++ int i;
++
++ phead = &priv->asoc_list;
++ plist = phead->next;
++
++ while (plist != phead) {
++ pstat = list_entry(plist, struct stat_info, asoc_list);
++ plist = plist->next;
++
++ if (pstat->ipmc_num == 0)
++ continue;
++
++ for (i=0; i<MAX_IP_MC_ENTRY; i++) {
++ if (pstat->ipmc[i].used && !memcmp(&pstat->ipmc[i].mcmac[3], ((unsigned char *)dst_ip)+1, 3)) {
++ memcpy(skb->data, pstat->ipmc[i].mcmac, ETH_ALEN);
++ return 1;
++ }
++ }
++ }
++ return 0;
++}
++#endif
++
++int nat25_db_handle(_adapter *priv, struct sk_buff *skb, int method)
++{
++ unsigned short protocol;
++ unsigned char networkAddr[MAX_NETWORK_ADDR_LEN];
++
++ if(skb == NULL)
++ return -1;
++
++ if((method <= NAT25_MIN) || (method >= NAT25_MAX))
++ return -1;
++
++ protocol = *((unsigned short *)(skb->data + 2 * ETH_ALEN));
++
++ /*---------------------------------------------------*/
++ /* Handle IP frame */
++ /*---------------------------------------------------*/
++ if(protocol == __constant_htons(ETH_P_IP))
++ {
++ struct iphdr* iph = (struct iphdr *)(skb->data + ETH_HLEN);
++
++ if(((unsigned char*)(iph) + (iph->ihl<<2)) >= (skb->data + ETH_HLEN + skb->len))
++ {
++ DEBUG_WARN("NAT25: malformed IP packet !\n");
++ return -1;
++ }
++
++ switch(method)
++ {
++ case NAT25_CHECK:
++ return -1;
++
++ case NAT25_INSERT:
++ {
++ //some muticast with source IP is all zero, maybe other case is illegal
++ //in class A, B, C, host address is all zero or all one is illegal
++ if (iph->saddr == 0)
++ return 0;
++ DEBUG_INFO("NAT25: Insert IP, SA=%08x, DA=%08x\n", iph->saddr, iph->daddr);
++ __nat25_generate_ipv4_network_addr(networkAddr, &iph->saddr);
++ //record source IP address and , source mac address into db
++ __nat25_db_network_insert(priv, skb->data+ETH_ALEN, networkAddr);
++
++ __nat25_db_print(priv);
++ }
++ return 0;
++
++ case NAT25_LOOKUP:
++ {
++ DEBUG_INFO("NAT25: Lookup IP, SA=%08x, DA=%08x\n", iph->saddr, iph->daddr);
++#ifdef SUPPORT_TX_MCAST2UNI
++ if (priv->pshare->rf_ft_var.mc2u_disable ||
++ ((((OPMODE & (WIFI_STATION_STATE|WIFI_ASOC_STATE))
++ == (WIFI_STATION_STATE|WIFI_ASOC_STATE)) &&
++ !checkIPMcAndReplace(priv, skb, &iph->daddr)) ||
++ (OPMODE & WIFI_ADHOC_STATE)))
++#endif
++ {
++ __nat25_generate_ipv4_network_addr(networkAddr, &iph->daddr);
++
++ if (!__nat25_db_network_lookup_and_replace(priv, skb, networkAddr)) {
++ if (*((unsigned char *)&iph->daddr + 3) == 0xff) {
++ // L2 is unicast but L3 is broadcast, make L2 bacome broadcast
++ DEBUG_INFO("NAT25: Set DA as boardcast\n");
++ memset(skb->data, 0xff, ETH_ALEN);
++ }
++ else {
++ // forward unknow IP packet to upper TCP/IP
++ DEBUG_INFO("NAT25: Replace DA with BR's MAC\n");
++ if ( (*(u32 *)priv->br_mac) == 0 && (*(u16 *)(priv->br_mac+4)) == 0 ) {
++ void netdev_br_init(struct net_device *netdev);
++ printk("Re-init netdev_br_init() due to br_mac==0!\n");
++ netdev_br_init(priv->pnetdev);
++ }
++ memcpy(skb->data, priv->br_mac, ETH_ALEN);
++ }
++ }
++ }
++ }
++ return 0;
++
++ default:
++ return -1;
++ }
++ }
++
++ /*---------------------------------------------------*/
++ /* Handle ARP frame */
++ /*---------------------------------------------------*/
++ else if(protocol == __constant_htons(ETH_P_ARP))
++ {
++ struct arphdr *arp = (struct arphdr *)(skb->data + ETH_HLEN);
++ unsigned char *arp_ptr = (unsigned char *)(arp + 1);
++ unsigned int *sender, *target;
++
++ if(arp->ar_pro != __constant_htons(ETH_P_IP))
++ {
++ DEBUG_WARN("NAT25: arp protocol unknown (%4x)!\n", htons(arp->ar_pro));
++ return -1;
++ }
++
++ switch(method)
++ {
++ case NAT25_CHECK:
++ return 0; // skb_copy for all ARP frame
++
++ case NAT25_INSERT:
++ {
++ DEBUG_INFO("NAT25: Insert ARP, MAC=%02x%02x%02x%02x%02x%02x\n", arp_ptr[0],
++ arp_ptr[1], arp_ptr[2], arp_ptr[3], arp_ptr[4], arp_ptr[5]);
++
++ // change to ARP sender mac address to wlan STA address
++ memcpy(arp_ptr, GET_MY_HWADDR(priv), ETH_ALEN);
++
++ arp_ptr += arp->ar_hln;
++ sender = (unsigned int *)arp_ptr;
++
++ __nat25_generate_ipv4_network_addr(networkAddr, sender);
++
++ __nat25_db_network_insert(priv, skb->data+ETH_ALEN, networkAddr);
++
++ __nat25_db_print(priv);
++ }
++ return 0;
++
++ case NAT25_LOOKUP:
++ {
++ DEBUG_INFO("NAT25: Lookup ARP\n");
++
++ arp_ptr += arp->ar_hln;
++ sender = (unsigned int *)arp_ptr;
++ arp_ptr += (arp->ar_hln + arp->ar_pln);
++ target = (unsigned int *)arp_ptr;
++
++ __nat25_generate_ipv4_network_addr(networkAddr, target);
++
++ __nat25_db_network_lookup_and_replace(priv, skb, networkAddr);
++
++ // change to ARP target mac address to Lookup result
++ arp_ptr = (unsigned char *)(arp + 1);
++ arp_ptr += (arp->ar_hln + arp->ar_pln);
++ memcpy(arp_ptr, skb->data, ETH_ALEN);
++ }
++ return 0;
++
++ default:
++ return -1;
++ }
++ }
++
++ /*---------------------------------------------------*/
++ /* Handle IPX and Apple Talk frame */
++ /*---------------------------------------------------*/
++ else if((protocol == __constant_htons(ETH_P_IPX)) ||
++ (protocol <= __constant_htons(ETH_FRAME_LEN)))
++ {
++ unsigned char ipx_header[2] = {0xFF, 0xFF};
++ struct ipxhdr *ipx = NULL;
++ struct elapaarp *ea = NULL;
++ struct ddpehdr *ddp = NULL;
++ unsigned char *framePtr = skb->data + ETH_HLEN;
++
++ if(protocol == __constant_htons(ETH_P_IPX))
++ {
++ DEBUG_INFO("NAT25: Protocol=IPX (Ethernet II)\n");
++ ipx = (struct ipxhdr *)framePtr;
++ }
++ else if(protocol <= __constant_htons(ETH_FRAME_LEN))
++ {
++ if(!memcmp(ipx_header, framePtr, 2))
++ {
++ DEBUG_INFO("NAT25: Protocol=IPX (Ethernet 802.3)\n");
++ ipx = (struct ipxhdr *)framePtr;
++ }
++ else
++ {
++ unsigned char ipx_8022_type = 0xE0;
++ unsigned char snap_8022_type = 0xAA;
++
++ if(*framePtr == snap_8022_type)
++ {
++ unsigned char ipx_snap_id[5] = {0x0, 0x0, 0x0, 0x81, 0x37}; // IPX SNAP ID
++ unsigned char aarp_snap_id[5] = {0x00, 0x00, 0x00, 0x80, 0xF3}; // Apple Talk AARP SNAP ID
++ unsigned char ddp_snap_id[5] = {0x08, 0x00, 0x07, 0x80, 0x9B}; // Apple Talk DDP SNAP ID
++
++ framePtr += 3; // eliminate the 802.2 header
++
++ if(!memcmp(ipx_snap_id, framePtr, 5))
++ {
++ framePtr += 5; // eliminate the SNAP header
++
++ DEBUG_INFO("NAT25: Protocol=IPX (Ethernet SNAP)\n");
++ ipx = (struct ipxhdr *)framePtr;
++ }
++ else if(!memcmp(aarp_snap_id, framePtr, 5))
++ {
++ framePtr += 5; // eliminate the SNAP header
++
++ ea = (struct elapaarp *)framePtr;
++ }
++ else if(!memcmp(ddp_snap_id, framePtr, 5))
++ {
++ framePtr += 5; // eliminate the SNAP header
++
++ ddp = (struct ddpehdr *)framePtr;
++ }
++ else
++ {
++ DEBUG_WARN("NAT25: Protocol=Ethernet SNAP %02x%02x%02x%02x%02x\n", framePtr[0],
++ framePtr[1], framePtr[2], framePtr[3], framePtr[4]);
++ return -1;
++ }
++ }
++ else if(*framePtr == ipx_8022_type)
++ {
++ framePtr += 3; // eliminate the 802.2 header
++
++ if(!memcmp(ipx_header, framePtr, 2))
++ {
++ DEBUG_INFO("NAT25: Protocol=IPX (Ethernet 802.2)\n");
++ ipx = (struct ipxhdr *)framePtr;
++ }
++ else
++ return -1;
++ }
++ else
++ return -1;
++ }
++ }
++ else
++ return -1;
++
++ /* IPX */
++ if(ipx != NULL)
++ {
++ switch(method)
++ {
++ case NAT25_CHECK:
++ if(!memcmp(skb->data+ETH_ALEN, ipx->ipx_source.node, ETH_ALEN))
++ {
++ DEBUG_INFO("NAT25: Check IPX skb_copy\n");
++ return 0;
++ }
++ return -1;
++
++ case NAT25_INSERT:
++ {
++ DEBUG_INFO("NAT25: Insert IPX, Dest=%08x,%02x%02x%02x%02x%02x%02x,%04x Source=%08x,%02x%02x%02x%02x%02x%02x,%04x\n",
++ ipx->ipx_dest.net,
++ ipx->ipx_dest.node[0],
++ ipx->ipx_dest.node[1],
++ ipx->ipx_dest.node[2],
++ ipx->ipx_dest.node[3],
++ ipx->ipx_dest.node[4],
++ ipx->ipx_dest.node[5],
++ ipx->ipx_dest.sock,
++ ipx->ipx_source.net,
++ ipx->ipx_source.node[0],
++ ipx->ipx_source.node[1],
++ ipx->ipx_source.node[2],
++ ipx->ipx_source.node[3],
++ ipx->ipx_source.node[4],
++ ipx->ipx_source.node[5],
++ ipx->ipx_source.sock);
++
++ if(!memcmp(skb->data+ETH_ALEN, ipx->ipx_source.node, ETH_ALEN))
++ {
++ DEBUG_INFO("NAT25: Use IPX Net, and Socket as network addr\n");
++
++ __nat25_generate_ipx_network_addr_with_socket(networkAddr, &ipx->ipx_source.net, &ipx->ipx_source.sock);
++
++ // change IPX source node addr to wlan STA address
++ memcpy(ipx->ipx_source.node, GET_MY_HWADDR(priv), ETH_ALEN);
++ }
++ else
++ {
++ __nat25_generate_ipx_network_addr_with_node(networkAddr, &ipx->ipx_source.net, ipx->ipx_source.node);
++ }
++
++ __nat25_db_network_insert(priv, skb->data+ETH_ALEN, networkAddr);
++
++ __nat25_db_print(priv);
++ }
++ return 0;
++
++ case NAT25_LOOKUP:
++ {
++ if(!memcmp(GET_MY_HWADDR(priv), ipx->ipx_dest.node, ETH_ALEN))
++ {
++ DEBUG_INFO("NAT25: Lookup IPX, Modify Destination IPX Node addr\n");
++
++ __nat25_generate_ipx_network_addr_with_socket(networkAddr, &ipx->ipx_dest.net, &ipx->ipx_dest.sock);
++
++ __nat25_db_network_lookup_and_replace(priv, skb, networkAddr);
++
++ // replace IPX destination node addr with Lookup destination MAC addr
++ memcpy(ipx->ipx_dest.node, skb->data, ETH_ALEN);
++ }
++ else
++ {
++ __nat25_generate_ipx_network_addr_with_node(networkAddr, &ipx->ipx_dest.net, ipx->ipx_dest.node);
++
++ __nat25_db_network_lookup_and_replace(priv, skb, networkAddr);
++ }
++ }
++ return 0;
++
++ default:
++ return -1;
++ }
++ }
++
++ /* AARP */
++ else if(ea != NULL)
++ {
++ /* Sanity check fields. */
++ if(ea->hw_len != ETH_ALEN || ea->pa_len != AARP_PA_ALEN)
++ {
++ DEBUG_WARN("NAT25: Appletalk AARP Sanity check fail!\n");
++ return -1;
++ }
++
++ switch(method)
++ {
++ case NAT25_CHECK:
++ return 0;
++
++ case NAT25_INSERT:
++ {
++ // change to AARP source mac address to wlan STA address
++ memcpy(ea->hw_src, GET_MY_HWADDR(priv), ETH_ALEN);
++
++ DEBUG_INFO("NAT25: Insert AARP, Source=%d,%d Destination=%d,%d\n",
++ ea->pa_src_net,
++ ea->pa_src_node,
++ ea->pa_dst_net,
++ ea->pa_dst_node);
++
++ __nat25_generate_apple_network_addr(networkAddr, &ea->pa_src_net, &ea->pa_src_node);
++
++ __nat25_db_network_insert(priv, skb->data+ETH_ALEN, networkAddr);
++
++ __nat25_db_print(priv);
++ }
++ return 0;
++
++ case NAT25_LOOKUP:
++ {
++ DEBUG_INFO("NAT25: Lookup AARP, Source=%d,%d Destination=%d,%d\n",
++ ea->pa_src_net,
++ ea->pa_src_node,
++ ea->pa_dst_net,
++ ea->pa_dst_node);
++
++ __nat25_generate_apple_network_addr(networkAddr, &ea->pa_dst_net, &ea->pa_dst_node);
++
++ __nat25_db_network_lookup_and_replace(priv, skb, networkAddr);
++
++ // change to AARP destination mac address to Lookup result
++ memcpy(ea->hw_dst, skb->data, ETH_ALEN);
++ }
++ return 0;
++
++ default:
++ return -1;
++ }
++ }
++
++ /* DDP */
++ else if(ddp != NULL)
++ {
++ switch(method)
++ {
++ case NAT25_CHECK:
++ return -1;
++
++ case NAT25_INSERT:
++ {
++ DEBUG_INFO("NAT25: Insert DDP, Source=%d,%d Destination=%d,%d\n",
++ ddp->deh_snet,
++ ddp->deh_snode,
++ ddp->deh_dnet,
++ ddp->deh_dnode);
++
++ __nat25_generate_apple_network_addr(networkAddr, &ddp->deh_snet, &ddp->deh_snode);
++
++ __nat25_db_network_insert(priv, skb->data+ETH_ALEN, networkAddr);
++
++ __nat25_db_print(priv);
++ }
++ return 0;
++
++ case NAT25_LOOKUP:
++ {
++ DEBUG_INFO("NAT25: Lookup DDP, Source=%d,%d Destination=%d,%d\n",
++ ddp->deh_snet,
++ ddp->deh_snode,
++ ddp->deh_dnet,
++ ddp->deh_dnode);
++
++ __nat25_generate_apple_network_addr(networkAddr, &ddp->deh_dnet, &ddp->deh_dnode);
++
++ __nat25_db_network_lookup_and_replace(priv, skb, networkAddr);
++ }
++ return 0;
++
++ default:
++ return -1;
++ }
++ }
++
++ return -1;
++ }
++
++ /*---------------------------------------------------*/
++ /* Handle PPPoE frame */
++ /*---------------------------------------------------*/
++ else if((protocol == __constant_htons(ETH_P_PPP_DISC)) ||
++ (protocol == __constant_htons(ETH_P_PPP_SES)))
++ {
++ struct pppoe_hdr *ph = (struct pppoe_hdr *)(skb->data + ETH_HLEN);
++ unsigned short *pMagic;
++
++ switch(method)
++ {
++ case NAT25_CHECK:
++ if (ph->sid == 0)
++ return 0;
++ return 1;
++
++ case NAT25_INSERT:
++ if(ph->sid == 0) // Discovery phase according to tag
++ {
++ if(ph->code == PADI_CODE || ph->code == PADR_CODE)
++ {
++ if (priv->ethBrExtInfo.addPPPoETag) {
++ struct pppoe_tag *tag, *pOldTag;
++ unsigned char tag_buf[40];
++ int old_tag_len=0;
++
++ tag = (struct pppoe_tag *)tag_buf;
++ pOldTag = (struct pppoe_tag *)__nat25_find_pppoe_tag(ph, ntohs(PTT_RELAY_SID));
++ if (pOldTag) { // if SID existed, copy old value and delete it
++ old_tag_len = ntohs(pOldTag->tag_len);
++ if (old_tag_len+TAG_HDR_LEN+MAGIC_CODE_LEN+RTL_RELAY_TAG_LEN > sizeof(tag_buf)) {
++ DEBUG_ERR("SID tag length too long!\n");
++ return -1;
++ }
++
++ memcpy(tag->tag_data+MAGIC_CODE_LEN+RTL_RELAY_TAG_LEN,
++ pOldTag->tag_data, old_tag_len);
++
++ if (skb_pull_and_merge(skb, (unsigned char *)pOldTag, TAG_HDR_LEN+old_tag_len) < 0) {
++ DEBUG_ERR("call skb_pull_and_merge() failed in PADI/R packet!\n");
++ return -1;
++ }
++ ph->length = htons(ntohs(ph->length)-TAG_HDR_LEN-old_tag_len);
++ }
++
++ tag->tag_type = PTT_RELAY_SID;
++ tag->tag_len = htons(MAGIC_CODE_LEN+RTL_RELAY_TAG_LEN+old_tag_len);
++
++ // insert the magic_code+client mac in relay tag
++ pMagic = (unsigned short *)tag->tag_data;
++ *pMagic = htons(MAGIC_CODE);
++ memcpy(tag->tag_data+MAGIC_CODE_LEN, skb->data+ETH_ALEN, ETH_ALEN);
++
++ //Add relay tag
++ if(__nat25_add_pppoe_tag(skb, tag) < 0)
++ return -1;
++
++ DEBUG_INFO("NAT25: Insert PPPoE, forward %s packet\n",
++ (ph->code == PADI_CODE ? "PADI" : "PADR"));
++ }
++ else { // not add relay tag
++ if (priv->pppoe_connection_in_progress &&
++ memcmp(skb->data+ETH_ALEN, priv->pppoe_addr, ETH_ALEN)) {
++ DEBUG_ERR("Discard PPPoE packet due to another PPPoE connection is in progress!\n");
++ return -2;
++ }
++
++ if (priv->pppoe_connection_in_progress == 0)
++ memcpy(priv->pppoe_addr, skb->data+ETH_ALEN, ETH_ALEN);
++
++ priv->pppoe_connection_in_progress = WAIT_TIME_PPPOE;
++ }
++ }
++ else
++ return -1;
++ }
++ else // session phase
++ {
++ DEBUG_INFO("NAT25: Insert PPPoE, insert session packet to %s\n", skb->dev->name);
++
++ __nat25_generate_pppoe_network_addr(networkAddr, skb->data, &(ph->sid));
++
++ __nat25_db_network_insert(priv, skb->data+ETH_ALEN, networkAddr);
++
++ __nat25_db_print(priv);
++
++ if (!priv->ethBrExtInfo.addPPPoETag &&
++ priv->pppoe_connection_in_progress &&
++ !memcmp(skb->data+ETH_ALEN, priv->pppoe_addr, ETH_ALEN))
++ priv->pppoe_connection_in_progress = 0;
++ }
++ return 0;
++
++ case NAT25_LOOKUP:
++ if(ph->code == PADO_CODE || ph->code == PADS_CODE)
++ {
++ if (priv->ethBrExtInfo.addPPPoETag) {
++ struct pppoe_tag *tag;
++ unsigned char *ptr;
++ unsigned short tagType, tagLen;
++ int offset=0;
++
++ if((ptr = __nat25_find_pppoe_tag(ph, ntohs(PTT_RELAY_SID))) == 0) {
++ DEBUG_ERR("Fail to find PTT_RELAY_SID in FADO!\n");
++ return -1;
++ }
++
++ tag = (struct pppoe_tag *)ptr;
++ tagType = (unsigned short)((ptr[0] << 8) + ptr[1]);
++ tagLen = (unsigned short)((ptr[2] << 8) + ptr[3]);
++
++ if((tagType != ntohs(PTT_RELAY_SID)) || (tagLen < (MAGIC_CODE_LEN+RTL_RELAY_TAG_LEN))) {
++ DEBUG_ERR("Invalid PTT_RELAY_SID tag length [%d]!\n", tagLen);
++ return -1;
++ }
++
++ pMagic = (unsigned short *)tag->tag_data;
++ if (ntohs(*pMagic) != MAGIC_CODE) {
++ DEBUG_ERR("Can't find MAGIC_CODE in %s packet!\n",
++ (ph->code == PADO_CODE ? "PADO" : "PADS"));
++ return -1;
++ }
++
++ memcpy(skb->data, tag->tag_data+MAGIC_CODE_LEN, ETH_ALEN);
++
++ if (tagLen > MAGIC_CODE_LEN+RTL_RELAY_TAG_LEN)
++ offset = TAG_HDR_LEN;
++
++ if (skb_pull_and_merge(skb, ptr+offset, TAG_HDR_LEN+MAGIC_CODE_LEN+RTL_RELAY_TAG_LEN-offset) < 0) {
++ DEBUG_ERR("call skb_pull_and_merge() failed in PADO packet!\n");
++ return -1;
++ }
++ ph->length = htons(ntohs(ph->length)-(TAG_HDR_LEN+MAGIC_CODE_LEN+RTL_RELAY_TAG_LEN-offset));
++ if (offset > 0)
++ tag->tag_len = htons(tagLen-MAGIC_CODE_LEN-RTL_RELAY_TAG_LEN);
++
++ DEBUG_INFO("NAT25: Lookup PPPoE, forward %s Packet from %s\n",
++ (ph->code == PADO_CODE ? "PADO" : "PADS"), skb->dev->name);
++ }
++ else { // not add relay tag
++ if (!priv->pppoe_connection_in_progress) {
++ DEBUG_ERR("Discard PPPoE packet due to no connection in progresss!\n");
++ return -1;
++ }
++ memcpy(skb->data, priv->pppoe_addr, ETH_ALEN);
++ priv->pppoe_connection_in_progress = WAIT_TIME_PPPOE;
++ }
++ }
++ else {
++ if(ph->sid != 0)
++ {
++ DEBUG_INFO("NAT25: Lookup PPPoE, lookup session packet from %s\n", skb->dev->name);
++ __nat25_generate_pppoe_network_addr(networkAddr, skb->data+ETH_ALEN, &(ph->sid));
++
++ __nat25_db_network_lookup_and_replace(priv, skb, networkAddr);
++
++ __nat25_db_print(priv);
++ }
++ else
++ return -1;
++
++ }
++ return 0;
++
++ default:
++ return -1;
++ }
++ }
++
++ /*---------------------------------------------------*/
++ /* Handle EAP frame */
++ /*---------------------------------------------------*/
++ else if(protocol == __constant_htons(0x888e))
++ {
++ switch(method)
++ {
++ case NAT25_CHECK:
++ return -1;
++
++ case NAT25_INSERT:
++ return 0;
++
++ case NAT25_LOOKUP:
++ return 0;
++
++ default:
++ return -1;
++ }
++ }
++
++ /*---------------------------------------------------*/
++ /* Handle C-Media proprietary frame */
++ /*---------------------------------------------------*/
++ else if((protocol == __constant_htons(0xe2ae)) ||
++ (protocol == __constant_htons(0xe2af)))
++ {
++ switch(method)
++ {
++ case NAT25_CHECK:
++ return -1;
++
++ case NAT25_INSERT:
++ return 0;
++
++ case NAT25_LOOKUP:
++ return 0;
++
++ default:
++ return -1;
++ }
++ }
++
++ /*---------------------------------------------------*/
++ /* Handle IPV6 frame */
++ /*---------------------------------------------------*/
++#ifdef CL_IPV6_PASS
++ else if(protocol == __constant_htons(ETH_P_IPV6))
++ {
++ struct ipv6hdr *iph = (struct ipv6hdr *)(skb->data + ETH_HLEN);
++
++ if (sizeof(*iph) >= (skb->len - ETH_HLEN))
++ {
++ DEBUG_WARN("NAT25: malformed IPv6 packet !\n");
++ return -1;
++ }
++
++ switch(method)
++ {
++ case NAT25_CHECK:
++ if (skb->data[0] & 1)
++ return 0;
++ return -1;
++
++ case NAT25_INSERT:
++ {
++ DEBUG_INFO("NAT25: Insert IP, SA=%4x:%4x:%4x:%4x:%4x:%4x:%4x:%4x,"
++ " DA=%4x:%4x:%4x:%4x:%4x:%4x:%4x:%4x\n",
++ iph->saddr.s6_addr16[0],iph->saddr.s6_addr16[1],iph->saddr.s6_addr16[2],iph->saddr.s6_addr16[3],
++ iph->saddr.s6_addr16[4],iph->saddr.s6_addr16[5],iph->saddr.s6_addr16[6],iph->saddr.s6_addr16[7],
++ iph->daddr.s6_addr16[0],iph->daddr.s6_addr16[1],iph->daddr.s6_addr16[2],iph->daddr.s6_addr16[3],
++ iph->daddr.s6_addr16[4],iph->daddr.s6_addr16[5],iph->daddr.s6_addr16[6],iph->daddr.s6_addr16[7]);
++
++ if (memcmp(&iph->saddr, "\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0", 16)) {
++ __nat25_generate_ipv6_network_addr(networkAddr, (unsigned int *)&iph->saddr);
++ __nat25_db_network_insert(priv, skb->data+ETH_ALEN, networkAddr);
++ __nat25_db_print(priv);
++
++ if (iph->nexthdr == IPPROTO_ICMPV6 &&
++ skb->len > (ETH_HLEN + sizeof(*iph) + 4)) {
++ if (update_nd_link_layer_addr(skb->data + ETH_HLEN + sizeof(*iph),
++ skb->len - ETH_HLEN - sizeof(*iph), GET_MY_HWADDR(priv))) {
++ struct icmp6hdr *hdr = (struct icmp6hdr *)(skb->data + ETH_HLEN + sizeof(*iph));
++ hdr->icmp6_cksum = 0;
++ hdr->icmp6_cksum = csum_ipv6_magic(&iph->saddr, &iph->daddr,
++ iph->payload_len,
++ IPPROTO_ICMPV6,
++ csum_partial((__u8 *)hdr, iph->payload_len, 0));
++ }
++ }
++ }
++ }
++ return 0;
++
++ case NAT25_LOOKUP:
++ DEBUG_INFO("NAT25: Lookup IP, SA=%4x:%4x:%4x:%4x:%4x:%4x:%4x:%4x,"
++ " DA=%4x:%4x:%4x:%4x:%4x:%4x:%4x:%4x\n",
++ iph->saddr.s6_addr16[0],iph->saddr.s6_addr16[1],iph->saddr.s6_addr16[2],iph->saddr.s6_addr16[3],
++ iph->saddr.s6_addr16[4],iph->saddr.s6_addr16[5],iph->saddr.s6_addr16[6],iph->saddr.s6_addr16[7],
++ iph->daddr.s6_addr16[0],iph->daddr.s6_addr16[1],iph->daddr.s6_addr16[2],iph->daddr.s6_addr16[3],
++ iph->daddr.s6_addr16[4],iph->daddr.s6_addr16[5],iph->daddr.s6_addr16[6],iph->daddr.s6_addr16[7]);
++
++
++ __nat25_generate_ipv6_network_addr(networkAddr, (unsigned int *)&iph->daddr);
++ if (!__nat25_db_network_lookup_and_replace(priv, skb, networkAddr)) {
++#ifdef SUPPORT_RX_UNI2MCAST
++ if (iph->daddr.s6_addr[0] == 0xff)
++ convert_ipv6_mac_to_mc(skb);
++#endif
++ }
++ return 0;
++
++ default:
++ return -1;
++ }
++ }
++#endif // CL_IPV6_PASS
++
++ return -1;
++}
++
++
++int nat25_handle_frame(_adapter *priv, struct sk_buff *skb)
++{
++#ifdef BR_EXT_DEBUG
++ if((!priv->ethBrExtInfo.nat25_disable) && (!(skb->data[0] & 1)))
++ {
++ panic_printk("NAT25: Input Frame: DA=%02x%02x%02x%02x%02x%02x SA=%02x%02x%02x%02x%02x%02x\n",
++ skb->data[0],
++ skb->data[1],
++ skb->data[2],
++ skb->data[3],
++ skb->data[4],
++ skb->data[5],
++ skb->data[6],
++ skb->data[7],
++ skb->data[8],
++ skb->data[9],
++ skb->data[10],
++ skb->data[11]);
++ }
++#endif
++
++ if(!(skb->data[0] & 1))
++ {
++ int is_vlan_tag=0, i, retval=0;
++ unsigned short vlan_hdr=0;
++
++ if (*((unsigned short *)(skb->data+ETH_ALEN*2)) == __constant_htons(ETH_P_8021Q)) {
++ is_vlan_tag = 1;
++ vlan_hdr = *((unsigned short *)(skb->data+ETH_ALEN*2+2));
++ for (i=0; i<6; i++)
++ *((unsigned short *)(skb->data+ETH_ALEN*2+2-i*2)) = *((unsigned short *)(skb->data+ETH_ALEN*2-2-i*2));
++ skb_pull(skb, 4);
++ }
++
++ if (!priv->ethBrExtInfo.nat25_disable)
++ {
++ _irqL irqL;
++ _enter_critical_bh(&priv->br_ext_lock, &irqL);
++ /*
++ * This function look up the destination network address from
++ * the NAT2.5 database. Return value = -1 means that the
++ * corresponding network protocol is NOT support.
++ */
++ if (!priv->ethBrExtInfo.nat25sc_disable &&
++ (*((unsigned short *)(skb->data+ETH_ALEN*2)) == __constant_htons(ETH_P_IP)) &&
++ !memcmp(priv->scdb_ip, skb->data+ETH_HLEN+16, 4)) {
++ memcpy(skb->data, priv->scdb_mac, ETH_ALEN);
++
++ _exit_critical_bh(&priv->br_ext_lock, &irqL);
++ }
++ else {
++ _exit_critical_bh(&priv->br_ext_lock, &irqL);
++
++ retval = nat25_db_handle(priv, skb, NAT25_LOOKUP);
++ }
++ }
++ else {
++ if (((*((unsigned short *)(skb->data+ETH_ALEN*2)) == __constant_htons(ETH_P_IP)) &&
++ !memcmp(priv->br_ip, skb->data+ETH_HLEN+16, 4)) ||
++ ((*((unsigned short *)(skb->data+ETH_ALEN*2)) == __constant_htons(ETH_P_ARP)) &&
++ !memcmp(priv->br_ip, skb->data+ETH_HLEN+24, 4))) {
++ // for traffic to upper TCP/IP
++ retval = nat25_db_handle(priv, skb, NAT25_LOOKUP);
++ }
++ }
++
++ if (is_vlan_tag) {
++ skb_push(skb, 4);
++ for (i=0; i<6; i++)
++ *((unsigned short *)(skb->data+i*2)) = *((unsigned short *)(skb->data+4+i*2));
++ *((unsigned short *)(skb->data+ETH_ALEN*2)) = __constant_htons(ETH_P_8021Q);
++ *((unsigned short *)(skb->data+ETH_ALEN*2+2)) = vlan_hdr;
++ }
++
++ if(retval == -1) {
++ //DEBUG_ERR("NAT25: Lookup fail!\n");
++ return -1;
++ }
++ }
++
++ return 0;
++}
++
++#if 0
++void mac_clone(_adapter *priv, unsigned char *addr)
++{
++ struct sockaddr sa;
++
++ memcpy(sa.sa_data, addr, ETH_ALEN);
++ DEBUG_INFO("MAC Clone: Addr=%02x%02x%02x%02x%02x%02x\n",
++ addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
++ rtl8192cd_set_hwaddr(priv->dev, &sa);
++}
++
++
++int mac_clone_handle_frame(_adapter *priv, struct sk_buff *skb)
++{
++ if(priv->ethBrExtInfo.macclone_enable && !priv->macclone_completed)
++ {
++ if(!(skb->data[ETH_ALEN] & 1)) //// check any other particular MAC add
++ {
++ if(memcmp(skb->data+ETH_ALEN, GET_MY_HWADDR(priv), ETH_ALEN) &&
++ ((priv->dev->br_port) &&
++ memcmp(skb->data+ETH_ALEN, priv->br_mac, ETH_ALEN)))
++ {
++ mac_clone(priv, skb->data+ETH_ALEN);
++ priv->macclone_completed = 1;
++ }
++ }
++ }
++
++ return 0;
++}
++#endif // 0
++
++#define SERVER_PORT 67
++#define CLIENT_PORT 68
++#define DHCP_MAGIC 0x63825363
++#define BROADCAST_FLAG 0x8000
++
++struct dhcpMessage {
++ u_int8_t op;
++ u_int8_t htype;
++ u_int8_t hlen;
++ u_int8_t hops;
++ u_int32_t xid;
++ u_int16_t secs;
++ u_int16_t flags;
++ u_int32_t ciaddr;
++ u_int32_t yiaddr;
++ u_int32_t siaddr;
++ u_int32_t giaddr;
++ u_int8_t chaddr[16];
++ u_int8_t sname[64];
++ u_int8_t file[128];
++ u_int32_t cookie;
++ u_int8_t options[308]; /* 312 - cookie */
++};
++
++void dhcp_flag_bcast(_adapter *priv, struct sk_buff *skb)
++{
++ if(skb == NULL)
++ return;
++
++ if(!priv->ethBrExtInfo.dhcp_bcst_disable)
++ {
++ unsigned short protocol = *((unsigned short *)(skb->data + 2 * ETH_ALEN));
++
++ if(protocol == __constant_htons(ETH_P_IP)) // IP
++ {
++ struct iphdr* iph = (struct iphdr *)(skb->data + ETH_HLEN);
++
++ if(iph->protocol == IPPROTO_UDP) // UDP
++ {
++ struct udphdr *udph = (struct udphdr *)((SIZE_PTR)iph + (iph->ihl << 2));
++
++ if((udph->source == __constant_htons(CLIENT_PORT))
++ && (udph->dest == __constant_htons(SERVER_PORT))) // DHCP request
++ {
++ struct dhcpMessage *dhcph =
++ (struct dhcpMessage *)((SIZE_PTR)udph + sizeof(struct udphdr));
++
++ if(dhcph->cookie == __constant_htonl(DHCP_MAGIC)) // match magic word
++ {
++ if(!(dhcph->flags & htons(BROADCAST_FLAG))) // if not broadcast
++ {
++ register int sum = 0;
++
++ DEBUG_INFO("DHCP: change flag of DHCP request to broadcast.\n");
++ // or BROADCAST flag
++ dhcph->flags |= htons(BROADCAST_FLAG);
++ // recalculate checksum
++ sum = ~(udph->check) & 0xffff;
++ sum += dhcph->flags;
++ while(sum >> 16)
++ sum = (sum & 0xffff) + (sum >> 16);
++ udph->check = ~sum;
++ }
++ }
++ }
++ }
++ }
++ }
++}
++
++
++void *scdb_findEntry(_adapter *priv, unsigned char *macAddr,
++ unsigned char *ipAddr)
++{
++ unsigned char networkAddr[MAX_NETWORK_ADDR_LEN];
++ struct nat25_network_db_entry *db;
++ int hash;
++ //_irqL irqL;
++ //_enter_critical_bh(&priv->br_ext_lock, &irqL);
++
++ __nat25_generate_ipv4_network_addr(networkAddr, (unsigned int *)ipAddr);
++ hash = __nat25_network_hash(networkAddr);
++ db = priv->nethash[hash];
++ while (db != NULL)
++ {
++ if(!memcmp(db->networkAddr, networkAddr, MAX_NETWORK_ADDR_LEN)) {
++ //_exit_critical_bh(&priv->br_ext_lock, &irqL);
++ return (void *)db;
++ }
++
++ db = db->next_hash;
++ }
++
++ //_exit_critical_bh(&priv->br_ext_lock, &irqL);
++ return NULL;
++}
++
++#endif // CONFIG_BR_EXT
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/core/rtw_cmd.c linux-xbian-rpi/drivers/net/wireless/rtl8192cu/core/rtw_cmd.c
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/core/rtw_cmd.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/core/rtw_cmd.c 2015-07-28 01:20:58.301668422 +0200
+@@ -0,0 +1,3034 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#define _RTW_CMD_C_
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++#include <recv_osdep.h>
++#include <cmd_osdep.h>
++#include <mlme_osdep.h>
++#include <rtw_byteorder.h>
++#ifdef CONFIG_BR_EXT
++#include <rtw_br_ext.h>
++#endif //CONFIG_BR_EXT
++/*
++Caller and the rtw_cmd_thread can protect cmd_q by spin_lock.
++No irqsave is necessary.
++*/
++
++sint _rtw_init_cmd_priv (struct cmd_priv *pcmdpriv)
++{
++ sint res=_SUCCESS;
++
++_func_enter_;
++
++ _rtw_init_sema(&(pcmdpriv->cmd_queue_sema), 0);
++ //_rtw_init_sema(&(pcmdpriv->cmd_done_sema), 0);
++ _rtw_init_sema(&(pcmdpriv->terminate_cmdthread_sema), 0);
++
++
++ _rtw_init_queue(&(pcmdpriv->cmd_queue));
++
++ //allocate DMA-able/Non-Page memory for cmd_buf and rsp_buf
++
++ pcmdpriv->cmd_seq = 1;
++
++ pcmdpriv->cmd_allocated_buf = rtw_zmalloc(MAX_CMDSZ + CMDBUFF_ALIGN_SZ);
++
++ if (pcmdpriv->cmd_allocated_buf == NULL){
++ res= _FAIL;
++ goto exit;
++ }
++
++ pcmdpriv->cmd_buf = pcmdpriv->cmd_allocated_buf + CMDBUFF_ALIGN_SZ - ( (SIZE_PTR)(pcmdpriv->cmd_allocated_buf) & (CMDBUFF_ALIGN_SZ-1));
++
++ pcmdpriv->rsp_allocated_buf = rtw_zmalloc(MAX_RSPSZ + 4);
++
++ if (pcmdpriv->rsp_allocated_buf == NULL){
++ res= _FAIL;
++ goto exit;
++ }
++
++ pcmdpriv->rsp_buf = pcmdpriv->rsp_allocated_buf + 4 - ( (SIZE_PTR)(pcmdpriv->rsp_allocated_buf) & 3);
++
++ pcmdpriv->cmd_issued_cnt = pcmdpriv->cmd_done_cnt = pcmdpriv->rsp_cnt = 0;
++
++exit:
++
++_func_exit_;
++
++ return res;
++
++}
++
++#ifdef CONFIG_C2H_WK
++static void c2h_wk_callback(_workitem *work);
++#endif
++sint _rtw_init_evt_priv(struct evt_priv *pevtpriv)
++{
++ sint res=_SUCCESS;
++
++_func_enter_;
++
++#ifdef CONFIG_H2CLBK
++ _rtw_init_sema(&(pevtpriv->lbkevt_done), 0);
++ pevtpriv->lbkevt_limit = 0;
++ pevtpriv->lbkevt_num = 0;
++ pevtpriv->cmdevt_parm = NULL;
++#endif
++
++ //allocate DMA-able/Non-Page memory for cmd_buf and rsp_buf
++ ATOMIC_SET(&pevtpriv->event_seq, 0);
++ pevtpriv->evt_done_cnt = 0;
++
++#ifdef CONFIG_EVENT_THREAD_MODE
++
++ _rtw_init_sema(&(pevtpriv->evt_notify), 0);
++ _rtw_init_sema(&(pevtpriv->terminate_evtthread_sema), 0);
++
++ pevtpriv->evt_allocated_buf = rtw_zmalloc(MAX_EVTSZ + 4);
++ if (pevtpriv->evt_allocated_buf == NULL){
++ res= _FAIL;
++ goto exit;
++ }
++ pevtpriv->evt_buf = pevtpriv->evt_allocated_buf + 4 - ((unsigned int)(pevtpriv->evt_allocated_buf) & 3);
++
++
++#ifdef CONFIG_SDIO_HCI
++ pevtpriv->allocated_c2h_mem = rtw_zmalloc(C2H_MEM_SZ +4);
++
++ if (pevtpriv->allocated_c2h_mem == NULL){
++ res= _FAIL;
++ goto exit;
++ }
++
++ pevtpriv->c2h_mem = pevtpriv->allocated_c2h_mem + 4\
++ - ( (u32)(pevtpriv->allocated_c2h_mem) & 3);
++#ifdef PLATFORM_OS_XP
++ pevtpriv->pc2h_mdl= IoAllocateMdl((u8 *)pevtpriv->c2h_mem, C2H_MEM_SZ , FALSE, FALSE, NULL);
++
++ if(pevtpriv->pc2h_mdl == NULL){
++ res= _FAIL;
++ goto exit;
++ }
++ MmBuildMdlForNonPagedPool(pevtpriv->pc2h_mdl);
++#endif
++#endif //end of CONFIG_SDIO_HCI
++
++ _rtw_init_queue(&(pevtpriv->evt_queue));
++
++exit:
++
++#endif //end of CONFIG_EVENT_THREAD_MODE
++
++#ifdef CONFIG_C2H_WK
++ _init_workitem(&pevtpriv->c2h_wk, c2h_wk_callback, NULL);
++ pevtpriv->c2h_wk_alive = _FALSE;
++ pevtpriv->c2h_queue = rtw_cbuf_alloc(C2H_QUEUE_MAX_LEN+1);
++#endif
++
++_func_exit_;
++
++ return res;
++}
++
++void _rtw_free_evt_priv (struct evt_priv *pevtpriv)
++{
++_func_enter_;
++
++ RT_TRACE(_module_rtl871x_cmd_c_,_drv_info_,("+_rtw_free_evt_priv \n"));
++
++#ifdef CONFIG_EVENT_THREAD_MODE
++ _rtw_free_sema(&(pevtpriv->evt_notify));
++ _rtw_free_sema(&(pevtpriv->terminate_evtthread_sema));
++
++
++ if (pevtpriv->evt_allocated_buf)
++ rtw_mfree(pevtpriv->evt_allocated_buf, MAX_EVTSZ + 4);
++#endif
++
++#ifdef CONFIG_C2H_WK
++ _cancel_workitem_sync(&pevtpriv->c2h_wk);
++ while(pevtpriv->c2h_wk_alive)
++ rtw_msleep_os(10);
++
++ while (!rtw_cbuf_empty(pevtpriv->c2h_queue)) {
++ void *c2h;
++ if ((c2h = rtw_cbuf_pop(pevtpriv->c2h_queue)) != NULL
++ && c2h != (void *)pevtpriv) {
++ rtw_mfree(c2h, 16);
++ }
++ }
++ rtw_cbuf_free(pevtpriv->c2h_queue);
++#endif
++
++ RT_TRACE(_module_rtl871x_cmd_c_,_drv_info_,("-_rtw_free_evt_priv \n"));
++
++_func_exit_;
++
++}
++
++void _rtw_free_cmd_priv (struct cmd_priv *pcmdpriv)
++{
++_func_enter_;
++
++ if(pcmdpriv){
++ _rtw_spinlock_free(&(pcmdpriv->cmd_queue.lock));
++ _rtw_free_sema(&(pcmdpriv->cmd_queue_sema));
++ //_rtw_free_sema(&(pcmdpriv->cmd_done_sema));
++ _rtw_free_sema(&(pcmdpriv->terminate_cmdthread_sema));
++
++ if (pcmdpriv->cmd_allocated_buf)
++ rtw_mfree(pcmdpriv->cmd_allocated_buf, MAX_CMDSZ + CMDBUFF_ALIGN_SZ);
++
++ if (pcmdpriv->rsp_allocated_buf)
++ rtw_mfree(pcmdpriv->rsp_allocated_buf, MAX_RSPSZ + 4);
++ }
++_func_exit_;
++}
++
++/*
++Calling Context:
++
++rtw_enqueue_cmd can only be called between kernel thread,
++since only spin_lock is used.
++
++ISR/Call-Back functions can't call this sub-function.
++
++*/
++
++sint _rtw_enqueue_cmd(_queue *queue, struct cmd_obj *obj)
++{
++ _irqL irqL;
++
++_func_enter_;
++
++ if (obj == NULL)
++ goto exit;
++
++ //_enter_critical_bh(&queue->lock, &irqL);
++ _enter_critical(&queue->lock, &irqL);
++
++ rtw_list_insert_tail(&obj->list, &queue->queue);
++
++ //_exit_critical_bh(&queue->lock, &irqL);
++ _exit_critical(&queue->lock, &irqL);
++
++exit:
++
++_func_exit_;
++
++ return _SUCCESS;
++}
++
++struct cmd_obj *_rtw_dequeue_cmd(_queue *queue)
++{
++ _irqL irqL;
++ struct cmd_obj *obj;
++
++_func_enter_;
++
++ //_enter_critical_bh(&(queue->lock), &irqL);
++ _enter_critical(&queue->lock, &irqL);
++ if (rtw_is_list_empty(&(queue->queue)))
++ obj = NULL;
++ else
++ {
++ obj = LIST_CONTAINOR(get_next(&(queue->queue)), struct cmd_obj, list);
++ rtw_list_delete(&obj->list);
++ }
++
++ //_exit_critical_bh(&(queue->lock), &irqL);
++ _exit_critical(&queue->lock, &irqL);
++
++_func_exit_;
++
++ return obj;
++}
++
++u32 rtw_init_cmd_priv(struct cmd_priv *pcmdpriv)
++{
++ u32 res;
++_func_enter_;
++ res = _rtw_init_cmd_priv (pcmdpriv);
++_func_exit_;
++ return res;
++}
++
++u32 rtw_init_evt_priv (struct evt_priv *pevtpriv)
++{
++ int res;
++_func_enter_;
++ res = _rtw_init_evt_priv(pevtpriv);
++_func_exit_;
++ return res;
++}
++
++void rtw_free_evt_priv (struct evt_priv *pevtpriv)
++{
++_func_enter_;
++ RT_TRACE(_module_rtl871x_cmd_c_,_drv_info_,("rtw_free_evt_priv\n"));
++ _rtw_free_evt_priv(pevtpriv);
++_func_exit_;
++}
++
++void rtw_free_cmd_priv (struct cmd_priv *pcmdpriv)
++{
++_func_enter_;
++ RT_TRACE(_module_rtl871x_cmd_c_,_drv_info_,("rtw_free_cmd_priv\n"));
++ _rtw_free_cmd_priv(pcmdpriv);
++_func_exit_;
++}
++
++int rtw_cmd_filter(struct cmd_priv *pcmdpriv, struct cmd_obj *cmd_obj);
++int rtw_cmd_filter(struct cmd_priv *pcmdpriv, struct cmd_obj *cmd_obj)
++{
++ u8 bAllow = _FALSE; //set to _TRUE to allow enqueuing cmd when hw_init_completed is _FALSE
++
++ #ifdef SUPPORT_HW_RFOFF_DETECTED
++ //To decide allow or not
++ if( (pcmdpriv->padapter->pwrctrlpriv.bHWPwrPindetect)
++ &&(!pcmdpriv->padapter->registrypriv.usbss_enable)
++ )
++ {
++ if(cmd_obj->cmdcode == GEN_CMD_CODE(_Set_Drv_Extra) )
++ {
++ struct drvextra_cmd_parm *pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)cmd_obj->parmbuf;
++ if(pdrvextra_cmd_parm->ec_id == POWER_SAVING_CTRL_WK_CID)
++ {
++ //DBG_871X("==>enqueue POWER_SAVING_CTRL_WK_CID\n");
++ bAllow = _TRUE;
++ }
++ }
++ }
++ #endif
++
++ if(cmd_obj->cmdcode == GEN_CMD_CODE(_SetChannelPlan))
++ bAllow = _TRUE;
++
++ if( (pcmdpriv->padapter->hw_init_completed ==_FALSE && bAllow == _FALSE)
++ || pcmdpriv->cmdthd_running== _FALSE //com_thread not running
++ )
++ {
++ //DBG_871X("%s:%s: drop cmdcode:%u, hw_init_completed:%u, cmdthd_running:%u\n", caller_func, __FUNCTION__,
++ // cmd_obj->cmdcode,
++ // pcmdpriv->padapter->hw_init_completed,
++ // pcmdpriv->cmdthd_running
++ //);
++
++ return _FAIL;
++ }
++ return _SUCCESS;
++}
++
++
++
++u32 rtw_enqueue_cmd(struct cmd_priv *pcmdpriv, struct cmd_obj *cmd_obj)
++{
++ int res = _FAIL;
++ PADAPTER padapter = pcmdpriv->padapter;
++
++_func_enter_;
++
++ if (cmd_obj == NULL) {
++ goto exit;
++ }
++
++ cmd_obj->padapter = padapter;
++
++#ifdef CONFIG_CONCURRENT_MODE
++ //change pcmdpriv to primary's pcmdpriv
++ if (padapter->adapter_type != PRIMARY_ADAPTER && padapter->pbuddy_adapter)
++ pcmdpriv = &(padapter->pbuddy_adapter->cmdpriv);
++#endif
++
++ if( _FAIL == (res=rtw_cmd_filter(pcmdpriv, cmd_obj)) ) {
++ rtw_free_cmd_obj(cmd_obj);
++ goto exit;
++ }
++
++ res = _rtw_enqueue_cmd(&pcmdpriv->cmd_queue, cmd_obj);
++
++ if(res == _SUCCESS)
++ _rtw_up_sema(&pcmdpriv->cmd_queue_sema);
++
++exit:
++
++_func_exit_;
++
++ return res;
++}
++
++struct cmd_obj *rtw_dequeue_cmd(struct cmd_priv *pcmdpriv)
++{
++ struct cmd_obj *cmd_obj;
++
++_func_enter_;
++
++ cmd_obj = _rtw_dequeue_cmd(&pcmdpriv->cmd_queue);
++
++_func_exit_;
++ return cmd_obj;
++}
++
++void rtw_cmd_clr_isr(struct cmd_priv *pcmdpriv)
++{
++_func_enter_;
++ pcmdpriv->cmd_done_cnt++;
++ //_rtw_up_sema(&(pcmdpriv->cmd_done_sema));
++_func_exit_;
++}
++
++void rtw_free_cmd_obj(struct cmd_obj *pcmd)
++{
++_func_enter_;
++
++ if((pcmd->cmdcode!=_JoinBss_CMD_) &&(pcmd->cmdcode!= _CreateBss_CMD_))
++ {
++ //free parmbuf in cmd_obj
++ rtw_mfree((unsigned char*)pcmd->parmbuf, pcmd->cmdsz);
++ }
++
++ if(pcmd->rsp!=NULL)
++ {
++ if(pcmd->rspsz!= 0)
++ {
++ //free rsp in cmd_obj
++ rtw_mfree((unsigned char*)pcmd->rsp, pcmd->rspsz);
++ }
++ }
++
++ //free cmd_obj
++ rtw_mfree((unsigned char*)pcmd, sizeof(struct cmd_obj));
++
++_func_exit_;
++}
++
++void rtw_stop_cmd_thread(_adapter *adapter)
++{
++ if(adapter->cmdThread && adapter->cmdpriv.cmdthd_running == _TRUE
++ && adapter->cmdpriv.stop_req == 0)
++ {
++ adapter->cmdpriv.stop_req = 1;
++ _rtw_up_sema(&adapter->cmdpriv.cmd_queue_sema);
++ _rtw_down_sema(&adapter->cmdpriv.terminate_cmdthread_sema);
++ }
++}
++
++thread_return rtw_cmd_thread(thread_context context)
++{
++ u8 ret;
++ struct cmd_obj *pcmd;
++ u8 *pcmdbuf, *prspbuf;
++ u8 (*cmd_hdl)(_adapter *padapter, u8* pbuf);
++ void (*pcmd_callback)(_adapter *dev, struct cmd_obj *pcmd);
++ _adapter *padapter = (_adapter *)context;
++ struct cmd_priv *pcmdpriv = &(padapter->cmdpriv);
++
++_func_enter_;
++
++ thread_enter("RTW_CMD_THREAD");
++
++ pcmdbuf = pcmdpriv->cmd_buf;
++ prspbuf = pcmdpriv->rsp_buf;
++
++ pcmdpriv->stop_req = 0;
++ pcmdpriv->cmdthd_running=_TRUE;
++ _rtw_up_sema(&pcmdpriv->terminate_cmdthread_sema);
++
++ RT_TRACE(_module_rtl871x_cmd_c_,_drv_info_,("start r871x rtw_cmd_thread !!!!\n"));
++
++ while(1)
++ {
++ if ((_rtw_down_sema(&(pcmdpriv->cmd_queue_sema))) == _FAIL) {
++ LOG_LEVEL(_drv_err_, FUNC_ADPT_FMT" _rtw_down_sema(&pcmdpriv->cmd_queue_sema) return _FAIL, break\n", FUNC_ADPT_ARG(padapter));
++ break;
++ }
++
++ if (pcmdpriv->stop_req) {
++ LOG_LEVEL(_drv_err_, FUNC_ADPT_FMT" stop_req:%u, break\n", FUNC_ADPT_ARG(padapter), pcmdpriv->stop_req);
++ break;
++ }
++
++#ifdef CONFIG_LPS_LCLK
++ if (rtw_register_cmd_alive(padapter) != _SUCCESS)
++ {
++ continue;
++ }
++#endif
++
++_next:
++ if ((padapter->bDriverStopped == _TRUE)||(padapter->bSurpriseRemoved == _TRUE))
++ {
++ LOG_LEVEL(_drv_err_, "%s: DriverStopped(%d) SurpriseRemoved(%d) break at line %d\n",
++ __FUNCTION__, padapter->bDriverStopped, padapter->bSurpriseRemoved, __LINE__);
++ break;
++ }
++
++ if(!(pcmd = rtw_dequeue_cmd(pcmdpriv))) {
++#ifdef CONFIG_LPS_LCLK
++ rtw_unregister_cmd_alive(padapter);
++#endif
++ continue;
++ }
++
++ if( _FAIL == rtw_cmd_filter(pcmdpriv, pcmd) )
++ {
++ pcmd->res = H2C_DROPPED;
++ goto post_process;
++ }
++
++ if( _FAIL == rtw_cmd_filter(pcmdpriv, pcmd) ) {
++ rtw_free_cmd_obj(pcmd);
++ continue;
++ }
++
++ pcmdpriv->cmd_issued_cnt++;
++
++ pcmd->cmdsz = _RND4((pcmd->cmdsz));//_RND4
++
++ _rtw_memcpy(pcmdbuf, pcmd->parmbuf, pcmd->cmdsz);
++
++ if(pcmd->cmdcode <= (sizeof(wlancmds) /sizeof(struct cmd_hdl)))
++ {
++ cmd_hdl = wlancmds[pcmd->cmdcode].h2cfuns;
++
++ if (cmd_hdl)
++ {
++ ret = cmd_hdl(pcmd->padapter, pcmdbuf);
++ pcmd->res = ret;
++ }
++
++ pcmdpriv->cmd_seq++;
++ }
++ else
++ {
++ pcmd->res = H2C_PARAMETERS_ERROR;
++ }
++
++ cmd_hdl = NULL;
++
++post_process:
++
++ //call callback function for post-processed
++ if(pcmd->cmdcode <= (sizeof(rtw_cmd_callback) /sizeof(struct _cmd_callback)))
++ {
++ pcmd_callback = rtw_cmd_callback[pcmd->cmdcode].callback;
++ if(pcmd_callback == NULL)
++ {
++ RT_TRACE(_module_rtl871x_cmd_c_,_drv_info_,("mlme_cmd_hdl(): pcmd_callback=0x%p, cmdcode=0x%x\n", pcmd_callback, pcmd->cmdcode));
++ rtw_free_cmd_obj(pcmd);
++ }
++ else
++ {
++ //todo: !!! fill rsp_buf to pcmd->rsp if (pcmd->rsp!=NULL)
++ pcmd_callback(pcmd->padapter, pcmd);//need conider that free cmd_obj in rtw_cmd_callback
++ }
++ }
++
++ flush_signals_thread();
++
++ goto _next;
++
++ }
++ pcmdpriv->cmdthd_running=_FALSE;
++
++
++ // free all cmd_obj resources
++ do{
++ pcmd = rtw_dequeue_cmd(pcmdpriv);
++ if(pcmd==NULL)
++ break;
++
++ //DBG_871X("%s: leaving... drop cmdcode:%u\n", __FUNCTION__, pcmd->cmdcode);
++
++ rtw_free_cmd_obj(pcmd);
++ }while(1);
++
++ _rtw_up_sema(&pcmdpriv->terminate_cmdthread_sema);
++
++_func_exit_;
++
++ thread_exit();
++
++}
++
++
++#ifdef CONFIG_EVENT_THREAD_MODE
++u32 rtw_enqueue_evt(struct evt_priv *pevtpriv, struct evt_obj *obj)
++{
++ _irqL irqL;
++ int res;
++ _queue *queue = &pevtpriv->evt_queue;
++
++_func_enter_;
++
++ res = _SUCCESS;
++
++ if (obj == NULL) {
++ res = _FAIL;
++ goto exit;
++ }
++
++ _enter_critical_bh(&queue->lock, &irqL);
++
++ rtw_list_insert_tail(&obj->list, &queue->queue);
++
++ _exit_critical_bh(&queue->lock, &irqL);
++
++ //rtw_evt_notify_isr(pevtpriv);
++
++exit:
++
++_func_exit_;
++
++ return res;
++}
++
++struct evt_obj *rtw_dequeue_evt(_queue *queue)
++{
++ _irqL irqL;
++ struct evt_obj *pevtobj;
++
++_func_enter_;
++
++ _enter_critical_bh(&queue->lock, &irqL);
++
++ if (rtw_is_list_empty(&(queue->queue)))
++ pevtobj = NULL;
++ else
++ {
++ pevtobj = LIST_CONTAINOR(get_next(&(queue->queue)), struct evt_obj, list);
++ rtw_list_delete(&pevtobj->list);
++ }
++
++ _exit_critical_bh(&queue->lock, &irqL);
++
++_func_exit_;
++
++ return pevtobj;
++}
++
++void rtw_free_evt_obj(struct evt_obj *pevtobj)
++{
++_func_enter_;
++
++ if(pevtobj->parmbuf)
++ rtw_mfree((unsigned char*)pevtobj->parmbuf, pevtobj->evtsz);
++
++ rtw_mfree((unsigned char*)pevtobj, sizeof(struct evt_obj));
++
++_func_exit_;
++}
++
++void rtw_evt_notify_isr(struct evt_priv *pevtpriv)
++{
++_func_enter_;
++ pevtpriv->evt_done_cnt++;
++ _rtw_up_sema(&(pevtpriv->evt_notify));
++_func_exit_;
++}
++#endif
++
++
++/*
++u8 rtw_setstandby_cmd(unsigned char *adapter)
++*/
++u8 rtw_setstandby_cmd(_adapter *padapter, uint action)
++{
++ struct cmd_obj* ph2c;
++ struct usb_suspend_parm* psetusbsuspend;
++ struct cmd_priv *pcmdpriv=&padapter->cmdpriv;
++
++ u8 ret = _SUCCESS;
++
++_func_enter_;
++
++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj));
++ if (ph2c == NULL) {
++ ret = _FAIL;
++ goto exit;
++ }
++
++ psetusbsuspend = (struct usb_suspend_parm*)rtw_zmalloc(sizeof(struct usb_suspend_parm));
++ if (psetusbsuspend == NULL) {
++ rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj));
++ ret = _FAIL;
++ goto exit;
++ }
++
++ psetusbsuspend->action = action;
++
++ init_h2fwcmd_w_parm_no_rsp(ph2c, psetusbsuspend, GEN_CMD_CODE(_SetUsbSuspend));
++
++ ret = rtw_enqueue_cmd(pcmdpriv, ph2c);
++
++exit:
++
++_func_exit_;
++
++ return ret;
++}
++
++/*
++rtw_sitesurvey_cmd(~)
++ ### NOTE:#### (!!!!)
++ MUST TAKE CARE THAT BEFORE CALLING THIS FUNC, YOU SHOULD HAVE LOCKED pmlmepriv->lock
++*/
++u8 rtw_sitesurvey_cmd(_adapter *padapter, NDIS_802_11_SSID *ssid, int ssid_num,
++ struct rtw_ieee80211_channel *ch, int ch_num)
++{
++ u8 res = _FAIL;
++ struct cmd_obj *ph2c;
++ struct sitesurvey_parm *psurveyPara;
++ struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++
++_func_enter_;
++
++#ifdef CONFIG_LPS
++ if(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE){
++ rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_SCAN, 1);
++ }
++#endif
++
++#ifdef CONFIG_P2P_PS
++ if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) {
++ p2p_ps_wk_cmd(padapter, P2P_PS_SCAN, 1);
++ }
++#endif // CONFIG_P2P_PS
++
++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj));
++ if (ph2c == NULL)
++ return _FAIL;
++
++ psurveyPara = (struct sitesurvey_parm*)rtw_zmalloc(sizeof(struct sitesurvey_parm));
++ if (psurveyPara == NULL) {
++ rtw_mfree((unsigned char*) ph2c, sizeof(struct cmd_obj));
++ return _FAIL;
++ }
++
++ rtw_free_network_queue(padapter, _FALSE);
++
++ RT_TRACE(_module_rtl871x_cmd_c_, _drv_info_, ("\nflush network queue\n\n"));
++
++ init_h2fwcmd_w_parm_no_rsp(ph2c, psurveyPara, GEN_CMD_CODE(_SiteSurvey));
++
++ /* psurveyPara->bsslimit = 48; */
++ psurveyPara->scan_mode = pmlmepriv->scan_mode;
++
++ /* prepare ssid list */
++ if (ssid) {
++ int i;
++ for (i=0; i<ssid_num && i< RTW_SSID_SCAN_AMOUNT; i++) {
++ if (ssid[i].SsidLength) {
++ _rtw_memcpy(&psurveyPara->ssid[i], &ssid[i], sizeof(NDIS_802_11_SSID));
++ psurveyPara->ssid_num++;
++ if (0)
++ DBG_871X(FUNC_ADPT_FMT" ssid:(%s, %d)\n", FUNC_ADPT_ARG(padapter),
++ psurveyPara->ssid[i].Ssid, psurveyPara->ssid[i].SsidLength);
++ }
++ }
++ }
++
++ /* prepare channel list */
++ if (ch) {
++ int i;
++ for (i=0; i<ch_num && i< RTW_CHANNEL_SCAN_AMOUNT; i++) {
++ if (ch[i].hw_value && !(ch[i].flags & RTW_IEEE80211_CHAN_DISABLED)) {
++ _rtw_memcpy(&psurveyPara->ch[i], &ch[i], sizeof(struct rtw_ieee80211_channel));
++ psurveyPara->ch_num++;
++ if (0)
++ DBG_871X(FUNC_ADPT_FMT" ch:%u\n", FUNC_ADPT_ARG(padapter),
++ psurveyPara->ch[i].hw_value);
++ }
++ }
++ }
++
++ set_fwstate(pmlmepriv, _FW_UNDER_SURVEY);
++
++ res = rtw_enqueue_cmd(pcmdpriv, ph2c);
++
++ if(res == _SUCCESS) {
++
++ pmlmepriv->scan_start_time = rtw_get_current_time();
++
++#ifdef CONFIG_STA_MODE_SCAN_UNDER_AP_MODE
++ if (padapter->pbuddy_adapter == NULL )
++ goto full_scan_timeout;
++ if((padapter->pbuddy_adapter->mlmeextpriv.mlmext_info.state&0x03) == WIFI_FW_AP_STATE)
++ _set_timer(&pmlmepriv->scan_to_timer,
++ SURVEY_TO * ( padapter->mlmeextpriv.max_chan_nums + ( padapter->mlmeextpriv.max_chan_nums / RTW_SCAN_NUM_OF_CH ) * RTW_STAY_AP_CH_MILLISECOND ) + 1000 );
++ else
++#endif //CONFIG_STA_MODE_SCAN_UNDER_AP_MODE
++full_scan_timeout:
++ _set_timer(&pmlmepriv->scan_to_timer, SCANNING_TIMEOUT);
++
++ rtw_led_control(padapter, LED_CTL_SITE_SURVEY);
++
++ pmlmepriv->scan_interval = SCAN_INTERVAL;// 30*2 sec = 60sec
++ } else {
++ _clr_fwstate_(pmlmepriv, _FW_UNDER_SURVEY);
++ }
++
++_func_exit_;
++
++ return res;
++}
++
++u8 rtw_setdatarate_cmd(_adapter *padapter, u8 *rateset)
++{
++ struct cmd_obj* ph2c;
++ struct setdatarate_parm* pbsetdataratepara;
++ struct cmd_priv* pcmdpriv = &padapter->cmdpriv;
++ u8 res = _SUCCESS;
++
++_func_enter_;
++
++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj));
++ if (ph2c == NULL) {
++ res = _FAIL;
++ goto exit;
++ }
++
++ pbsetdataratepara = (struct setdatarate_parm*)rtw_zmalloc(sizeof(struct setdatarate_parm));
++ if (pbsetdataratepara == NULL) {
++ rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj));
++ res = _FAIL;
++ goto exit;
++ }
++
++ init_h2fwcmd_w_parm_no_rsp(ph2c, pbsetdataratepara, GEN_CMD_CODE(_SetDataRate));
++#ifdef MP_FIRMWARE_OFFLOAD
++ pbsetdataratepara->curr_rateidx = *(u32*)rateset;
++// _rtw_memcpy(pbsetdataratepara, rateset, sizeof(u32));
++#else
++ pbsetdataratepara->mac_id = 5;
++ _rtw_memcpy(pbsetdataratepara->datarates, rateset, NumRates);
++#endif
++ res = rtw_enqueue_cmd(pcmdpriv, ph2c);
++exit:
++
++_func_exit_;
++
++ return res;
++}
++
++u8 rtw_setbasicrate_cmd(_adapter *padapter, u8 *rateset)
++{
++ struct cmd_obj* ph2c;
++ struct setbasicrate_parm* pssetbasicratepara;
++ struct cmd_priv* pcmdpriv=&padapter->cmdpriv;
++ u8 res = _SUCCESS;
++
++_func_enter_;
++
++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj));
++ if (ph2c == NULL) {
++ res= _FAIL;
++ goto exit;
++ }
++ pssetbasicratepara = (struct setbasicrate_parm*)rtw_zmalloc(sizeof(struct setbasicrate_parm));
++
++ if (pssetbasicratepara == NULL) {
++ rtw_mfree((u8*) ph2c, sizeof(struct cmd_obj));
++ res = _FAIL;
++ goto exit;
++ }
++
++ init_h2fwcmd_w_parm_no_rsp(ph2c, pssetbasicratepara, _SetBasicRate_CMD_);
++
++ _rtw_memcpy(pssetbasicratepara->basicrates, rateset, NumRates);
++
++ res = rtw_enqueue_cmd(pcmdpriv, ph2c);
++exit:
++
++_func_exit_;
++
++ return res;
++}
++
++
++/*
++unsigned char rtw_setphy_cmd(unsigned char *adapter)
++
++1. be called only after rtw_update_registrypriv_dev_network( ~) or mp testing program
++2. for AdHoc/Ap mode or mp mode?
++
++*/
++u8 rtw_setphy_cmd(_adapter *padapter, u8 modem, u8 ch)
++{
++ struct cmd_obj* ph2c;
++ struct setphy_parm* psetphypara;
++ struct cmd_priv *pcmdpriv=&padapter->cmdpriv;
++// struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++// struct registry_priv* pregistry_priv = &padapter->registrypriv;
++ u8 res=_SUCCESS;
++
++_func_enter_;
++
++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj));
++ if(ph2c==NULL){
++ res= _FAIL;
++ goto exit;
++ }
++ psetphypara = (struct setphy_parm*)rtw_zmalloc(sizeof(struct setphy_parm));
++
++ if(psetphypara==NULL){
++ rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj));
++ res= _FAIL;
++ goto exit;
++ }
++
++ init_h2fwcmd_w_parm_no_rsp(ph2c, psetphypara, _SetPhy_CMD_);
++
++ RT_TRACE(_module_rtl871x_cmd_c_,_drv_info_,("CH=%d, modem=%d", ch, modem));
++
++ psetphypara->modem = modem;
++ psetphypara->rfchannel = ch;
++
++ res = rtw_enqueue_cmd(pcmdpriv, ph2c);
++exit:
++_func_exit_;
++ return res;
++}
++
++u8 rtw_setbbreg_cmd(_adapter*padapter, u8 offset, u8 val)
++{
++ struct cmd_obj* ph2c;
++ struct writeBB_parm* pwritebbparm;
++ struct cmd_priv *pcmdpriv=&padapter->cmdpriv;
++ u8 res=_SUCCESS;
++_func_enter_;
++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj));
++ if(ph2c==NULL){
++ res= _FAIL;
++ goto exit;
++ }
++ pwritebbparm = (struct writeBB_parm*)rtw_zmalloc(sizeof(struct writeBB_parm));
++
++ if(pwritebbparm==NULL){
++ rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj));
++ res= _FAIL;
++ goto exit;
++ }
++
++ init_h2fwcmd_w_parm_no_rsp(ph2c, pwritebbparm, GEN_CMD_CODE(_SetBBReg));
++
++ pwritebbparm->offset = offset;
++ pwritebbparm->value = val;
++
++ res = rtw_enqueue_cmd(pcmdpriv, ph2c);
++exit:
++_func_exit_;
++ return res;
++}
++
++u8 rtw_getbbreg_cmd(_adapter *padapter, u8 offset, u8 *pval)
++{
++ struct cmd_obj* ph2c;
++ struct readBB_parm* prdbbparm;
++ struct cmd_priv *pcmdpriv=&padapter->cmdpriv;
++ u8 res=_SUCCESS;
++
++_func_enter_;
++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj));
++ if(ph2c==NULL){
++ res=_FAIL;
++ goto exit;
++ }
++ prdbbparm = (struct readBB_parm*)rtw_zmalloc(sizeof(struct readBB_parm));
++
++ if(prdbbparm ==NULL){
++ rtw_mfree((unsigned char *) ph2c, sizeof(struct cmd_obj));
++ return _FAIL;
++ }
++
++ _rtw_init_listhead(&ph2c->list);
++ ph2c->cmdcode =GEN_CMD_CODE(_GetBBReg);
++ ph2c->parmbuf = (unsigned char *)prdbbparm;
++ ph2c->cmdsz = sizeof(struct readBB_parm);
++ ph2c->rsp = pval;
++ ph2c->rspsz = sizeof(struct readBB_rsp);
++
++ prdbbparm ->offset = offset;
++
++ res = rtw_enqueue_cmd(pcmdpriv, ph2c);
++exit:
++_func_exit_;
++ return res;
++}
++
++u8 rtw_setrfreg_cmd(_adapter *padapter, u8 offset, u32 val)
++{
++ struct cmd_obj* ph2c;
++ struct writeRF_parm* pwriterfparm;
++ struct cmd_priv *pcmdpriv=&padapter->cmdpriv;
++ u8 res=_SUCCESS;
++_func_enter_;
++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj));
++ if(ph2c==NULL){
++ res= _FAIL;
++ goto exit;
++ }
++ pwriterfparm = (struct writeRF_parm*)rtw_zmalloc(sizeof(struct writeRF_parm));
++
++ if(pwriterfparm==NULL){
++ rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj));
++ res= _FAIL;
++ goto exit;
++ }
++
++ init_h2fwcmd_w_parm_no_rsp(ph2c, pwriterfparm, GEN_CMD_CODE(_SetRFReg));
++
++ pwriterfparm->offset = offset;
++ pwriterfparm->value = val;
++
++ res = rtw_enqueue_cmd(pcmdpriv, ph2c);
++exit:
++_func_exit_;
++ return res;
++}
++
++u8 rtw_getrfreg_cmd(_adapter *padapter, u8 offset, u8 *pval)
++{
++ struct cmd_obj* ph2c;
++ struct readRF_parm* prdrfparm;
++ struct cmd_priv *pcmdpriv=&padapter->cmdpriv;
++ u8 res=_SUCCESS;
++
++_func_enter_;
++
++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj));
++ if(ph2c==NULL){
++ res= _FAIL;
++ goto exit;
++ }
++
++ prdrfparm = (struct readRF_parm*)rtw_zmalloc(sizeof(struct readRF_parm));
++ if(prdrfparm ==NULL){
++ rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj));
++ res= _FAIL;
++ goto exit;
++ }
++
++ _rtw_init_listhead(&ph2c->list);
++ ph2c->cmdcode =GEN_CMD_CODE(_GetRFReg);
++ ph2c->parmbuf = (unsigned char *)prdrfparm;
++ ph2c->cmdsz = sizeof(struct readRF_parm);
++ ph2c->rsp = pval;
++ ph2c->rspsz = sizeof(struct readRF_rsp);
++
++ prdrfparm ->offset = offset;
++
++ res = rtw_enqueue_cmd(pcmdpriv, ph2c);
++
++exit:
++
++_func_exit_;
++
++ return res;
++}
++
++void rtw_getbbrfreg_cmdrsp_callback(_adapter* padapter, struct cmd_obj *pcmd)
++{
++ _func_enter_;
++
++ //rtw_free_cmd_obj(pcmd);
++ rtw_mfree((unsigned char*) pcmd->parmbuf, pcmd->cmdsz);
++ rtw_mfree((unsigned char*) pcmd, sizeof(struct cmd_obj));
++
++#ifdef CONFIG_MP_INCLUDED
++ padapter->mppriv.workparam.bcompleted= _TRUE;
++#endif
++_func_exit_;
++}
++
++void rtw_readtssi_cmdrsp_callback(_adapter* padapter, struct cmd_obj *pcmd)
++{
++ _func_enter_;
++
++ rtw_mfree((unsigned char*) pcmd->parmbuf, pcmd->cmdsz);
++ rtw_mfree((unsigned char*) pcmd, sizeof(struct cmd_obj));
++
++#ifdef CONFIG_MP_INCLUDED
++ padapter->mppriv.workparam.bcompleted= _TRUE;
++#endif
++
++_func_exit_;
++}
++
++u8 rtw_createbss_cmd(_adapter *padapter)
++{
++ struct cmd_obj* pcmd;
++ struct cmd_priv *pcmdpriv=&padapter->cmdpriv;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ WLAN_BSSID_EX *pdev_network = &padapter->registrypriv.dev_network;
++ u8 res=_SUCCESS;
++
++_func_enter_;
++
++ rtw_led_control(padapter, LED_CTL_START_TO_LINK);
++
++ if (pmlmepriv->assoc_ssid.SsidLength == 0){
++ RT_TRACE(_module_rtl871x_cmd_c_,_drv_info_,(" createbss for Any SSid:%s\n",pmlmepriv->assoc_ssid.Ssid));
++ } else {
++ RT_TRACE(_module_rtl871x_cmd_c_,_drv_info_,(" createbss for SSid:%s\n", pmlmepriv->assoc_ssid.Ssid));
++ }
++
++ pcmd = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj));
++ if(pcmd==NULL){
++ res= _FAIL;
++ goto exit;
++ }
++
++ _rtw_init_listhead(&pcmd->list);
++ pcmd->cmdcode = _CreateBss_CMD_;
++ pcmd->parmbuf = (unsigned char *)pdev_network;
++ pcmd->cmdsz = get_WLAN_BSSID_EX_sz((WLAN_BSSID_EX*)pdev_network);
++ pcmd->rsp = NULL;
++ pcmd->rspsz = 0;
++
++ pdev_network->Length = pcmd->cmdsz;
++
++#ifdef CONFIG_RTL8712
++ //notes: translate IELength & Length after assign the Length to cmdsz;
++ pdev_network->Length = cpu_to_le32(pcmd->cmdsz);
++ pdev_network->IELength = cpu_to_le32(pdev_network->IELength);
++ pdev_network->Ssid.SsidLength = cpu_to_le32(pdev_network->Ssid.SsidLength);
++#endif
++
++ res = rtw_enqueue_cmd(pcmdpriv, pcmd);
++
++exit:
++
++_func_exit_;
++
++ return res;
++}
++
++u8 rtw_createbss_cmd_ex(_adapter *padapter, unsigned char *pbss, unsigned int sz)
++{
++ struct cmd_obj* pcmd;
++ struct cmd_priv *pcmdpriv=&padapter->cmdpriv;
++ u8 res=_SUCCESS;
++
++_func_enter_;
++
++ pcmd = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj));
++ if(pcmd==NULL){
++ res= _FAIL;
++ goto exit;
++ }
++
++ _rtw_init_listhead(&pcmd->list);
++ pcmd->cmdcode = GEN_CMD_CODE(_CreateBss);
++ pcmd->parmbuf = pbss;
++ pcmd->cmdsz = sz;
++ pcmd->rsp = NULL;
++ pcmd->rspsz = 0;
++
++ res = rtw_enqueue_cmd(pcmdpriv, pcmd);
++
++exit:
++
++_func_exit_;
++
++ return res;
++}
++
++u8 rtw_joinbss_cmd(_adapter *padapter, struct wlan_network* pnetwork)
++{
++ u8 *auth, res = _SUCCESS;
++ uint t_len = 0;
++ WLAN_BSSID_EX *psecnetwork;
++ struct cmd_obj *pcmd;
++ struct cmd_priv *pcmdpriv=&padapter->cmdpriv;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct qos_priv *pqospriv= &pmlmepriv->qospriv;
++ struct security_priv *psecuritypriv=&padapter->securitypriv;
++ struct registry_priv *pregistrypriv = &padapter->registrypriv;
++ struct ht_priv *phtpriv = &pmlmepriv->htpriv;
++ NDIS_802_11_NETWORK_INFRASTRUCTURE ndis_network_mode = pnetwork->network.InfrastructureMode;
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++
++_func_enter_;
++
++ rtw_led_control(padapter, LED_CTL_START_TO_LINK);
++
++ if (pmlmepriv->assoc_ssid.SsidLength == 0){
++ RT_TRACE(_module_rtl871x_cmd_c_, _drv_info_, ("+Join cmd: Any SSid\n"));
++ } else {
++ RT_TRACE(_module_rtl871x_cmd_c_, _drv_notice_, ("+Join cmd: SSid=[%s]\n", pmlmepriv->assoc_ssid.Ssid));
++ }
++
++ pcmd = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj));
++ if(pcmd==NULL){
++ res=_FAIL;
++ RT_TRACE(_module_rtl871x_cmd_c_, _drv_err_, ("rtw_joinbss_cmd: memory allocate for cmd_obj fail!!!\n"));
++ goto exit;
++ }
++ /* // for IEs is pointer
++ t_len = sizeof (ULONG) + sizeof (NDIS_802_11_MAC_ADDRESS) + 2 +
++ sizeof (NDIS_802_11_SSID) + sizeof (ULONG) +
++ sizeof (NDIS_802_11_RSSI) + sizeof (NDIS_802_11_NETWORK_TYPE) +
++ sizeof (NDIS_802_11_CONFIGURATION) +
++ sizeof (NDIS_802_11_NETWORK_INFRASTRUCTURE) +
++ sizeof (NDIS_802_11_RATES_EX)+ sizeof(WLAN_PHY_INFO)+ sizeof (ULONG) + MAX_IE_SZ;
++ */
++ //for IEs is fix buf size
++ t_len = sizeof(WLAN_BSSID_EX);
++
++
++ //for hidden ap to set fw_state here
++ if (check_fwstate(pmlmepriv, WIFI_STATION_STATE|WIFI_ADHOC_STATE) != _TRUE)
++ {
++ switch(ndis_network_mode)
++ {
++ case Ndis802_11IBSS:
++ set_fwstate(pmlmepriv, WIFI_ADHOC_STATE);
++ break;
++
++ case Ndis802_11Infrastructure:
++ set_fwstate(pmlmepriv, WIFI_STATION_STATE);
++ break;
++
++ case Ndis802_11APMode:
++ case Ndis802_11AutoUnknown:
++ case Ndis802_11InfrastructureMax:
++ break;
++
++ }
++ }
++
++ psecnetwork=(WLAN_BSSID_EX *)&psecuritypriv->sec_bss;
++ if(psecnetwork==NULL)
++ {
++ if(pcmd !=NULL)
++ rtw_mfree((unsigned char *)pcmd, sizeof(struct cmd_obj));
++
++ res=_FAIL;
++
++ RT_TRACE(_module_rtl871x_cmd_c_, _drv_err_, ("rtw_joinbss_cmd :psecnetwork==NULL!!!\n"));
++
++ goto exit;
++ }
++
++ _rtw_memset(psecnetwork, 0, t_len);
++
++ _rtw_memcpy(psecnetwork, &pnetwork->network, get_WLAN_BSSID_EX_sz(&pnetwork->network));
++
++ auth=&psecuritypriv->authenticator_ie[0];
++ psecuritypriv->authenticator_ie[0]=(unsigned char)psecnetwork->IELength;
++
++ if((psecnetwork->IELength-12) < (256-1)) {
++ _rtw_memcpy(&psecuritypriv->authenticator_ie[1], &psecnetwork->IEs[12], psecnetwork->IELength-12);
++ } else {
++ _rtw_memcpy(&psecuritypriv->authenticator_ie[1], &psecnetwork->IEs[12], (256-1));
++ }
++
++ psecnetwork->IELength = 0;
++ // Added by Albert 2009/02/18
++ // If the the driver wants to use the bssid to create the connection.
++ // If not, we have to copy the connecting AP's MAC address to it so that
++ // the driver just has the bssid information for PMKIDList searching.
++
++ if ( pmlmepriv->assoc_by_bssid == _FALSE )
++ {
++ _rtw_memcpy( &pmlmepriv->assoc_bssid[ 0 ], &pnetwork->network.MacAddress[ 0 ], ETH_ALEN );
++ }
++
++ psecnetwork->IELength = rtw_restruct_sec_ie(padapter, &pnetwork->network.IEs[0], &psecnetwork->IEs[0], pnetwork->network.IELength);
++
++
++ pqospriv->qos_option = 0;
++
++ if(pregistrypriv->wmm_enable)
++ {
++ u32 tmp_len;
++
++ tmp_len = rtw_restruct_wmm_ie(padapter, &pnetwork->network.IEs[0], &psecnetwork->IEs[0], pnetwork->network.IELength, psecnetwork->IELength);
++
++ if (psecnetwork->IELength != tmp_len)
++ {
++ psecnetwork->IELength = tmp_len;
++ pqospriv->qos_option = 1; //There is WMM IE in this corresp. beacon
++ }
++ else
++ {
++ pqospriv->qos_option = 0;//There is no WMM IE in this corresp. beacon
++ }
++ }
++
++#ifdef CONFIG_80211N_HT
++ phtpriv->ht_option = _FALSE;
++ if(pregistrypriv->ht_enable)
++ {
++ // Added by Albert 2010/06/23
++ // For the WEP mode, we will use the bg mode to do the connection to avoid some IOT issue.
++ // Especially for Realtek 8192u SoftAP.
++ if ( ( padapter->securitypriv.dot11PrivacyAlgrthm != _WEP40_ ) &&
++ ( padapter->securitypriv.dot11PrivacyAlgrthm != _WEP104_ ) &&
++ ( padapter->securitypriv.dot11PrivacyAlgrthm != _TKIP_ ))
++ {
++ //rtw_restructure_ht_ie
++ rtw_restructure_ht_ie(padapter, &pnetwork->network.IEs[0], &psecnetwork->IEs[0],
++ pnetwork->network.IELength, &psecnetwork->IELength, (u8)psecnetwork->Configuration.DSConfig );
++ }
++ }
++
++#endif
++
++ pmlmeinfo->assoc_AP_vendor = check_assoc_AP(pnetwork->network.IEs, pnetwork->network.IELength);
++
++ #if 0
++ psecuritypriv->supplicant_ie[0]=(u8)psecnetwork->IELength;
++
++ if(psecnetwork->IELength < (256-1))
++ {
++ _rtw_memcpy(&psecuritypriv->supplicant_ie[1], &psecnetwork->IEs[0], psecnetwork->IELength);
++ }
++ else
++ {
++ _rtw_memcpy(&psecuritypriv->supplicant_ie[1], &psecnetwork->IEs[0], (256-1));
++ }
++ #endif
++
++ pcmd->cmdsz = get_WLAN_BSSID_EX_sz(psecnetwork);//get cmdsz before endian conversion
++
++#ifdef CONFIG_RTL8712
++ //wlan_network endian conversion
++ psecnetwork->Length = cpu_to_le32(psecnetwork->Length);
++ psecnetwork->Ssid.SsidLength= cpu_to_le32(psecnetwork->Ssid.SsidLength);
++ psecnetwork->Privacy = cpu_to_le32(psecnetwork->Privacy);
++ psecnetwork->Rssi = cpu_to_le32(psecnetwork->Rssi);
++ psecnetwork->NetworkTypeInUse = cpu_to_le32(psecnetwork->NetworkTypeInUse);
++ psecnetwork->Configuration.ATIMWindow = cpu_to_le32(psecnetwork->Configuration.ATIMWindow);
++ psecnetwork->Configuration.BeaconPeriod = cpu_to_le32(psecnetwork->Configuration.BeaconPeriod);
++ psecnetwork->Configuration.DSConfig = cpu_to_le32(psecnetwork->Configuration.DSConfig);
++ psecnetwork->Configuration.FHConfig.DwellTime=cpu_to_le32(psecnetwork->Configuration.FHConfig.DwellTime);
++ psecnetwork->Configuration.FHConfig.HopPattern=cpu_to_le32(psecnetwork->Configuration.FHConfig.HopPattern);
++ psecnetwork->Configuration.FHConfig.HopSet=cpu_to_le32(psecnetwork->Configuration.FHConfig.HopSet);
++ psecnetwork->Configuration.FHConfig.Length=cpu_to_le32(psecnetwork->Configuration.FHConfig.Length);
++ psecnetwork->Configuration.Length = cpu_to_le32(psecnetwork->Configuration.Length);
++ psecnetwork->InfrastructureMode = cpu_to_le32(psecnetwork->InfrastructureMode);
++ psecnetwork->IELength = cpu_to_le32(psecnetwork->IELength);
++#endif
++
++ _rtw_init_listhead(&pcmd->list);
++ pcmd->cmdcode = _JoinBss_CMD_;//GEN_CMD_CODE(_JoinBss)
++ pcmd->parmbuf = (unsigned char *)psecnetwork;
++ pcmd->rsp = NULL;
++ pcmd->rspsz = 0;
++
++ res = rtw_enqueue_cmd(pcmdpriv, pcmd);
++
++exit:
++
++_func_exit_;
++
++ return res;
++}
++
++u8 rtw_disassoc_cmd(_adapter*padapter, u32 deauth_timeout_ms, bool enqueue) /* for sta_mode */
++{
++ struct cmd_obj *cmdobj = NULL;
++ struct disconnect_parm *param = NULL;
++ struct cmd_priv *cmdpriv = &padapter->cmdpriv;
++ u8 res = _SUCCESS;
++
++_func_enter_;
++
++ RT_TRACE(_module_rtl871x_cmd_c_, _drv_notice_, ("+rtw_disassoc_cmd\n"));
++
++ /* prepare cmd parameter */
++ param = (struct disconnect_parm *)rtw_zmalloc(sizeof(*param));
++ if (param == NULL) {
++ res = _FAIL;
++ goto exit;
++ }
++ param->deauth_timeout_ms = deauth_timeout_ms;
++
++ if (enqueue) {
++ /* need enqueue, prepare cmd_obj and enqueue */
++ cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj));
++ if (cmdobj == NULL) {
++ res = _FAIL;
++ rtw_mfree((u8 *)param, sizeof(*param));
++ goto exit;
++ }
++ init_h2fwcmd_w_parm_no_rsp(cmdobj, param, _DisConnect_CMD_);
++ res = rtw_enqueue_cmd(cmdpriv, cmdobj);
++ } else {
++ /* no need to enqueue, do the cmd hdl directly and free cmd parameter */
++ if (H2C_SUCCESS != disconnect_hdl(padapter, (u8 *)param))
++ res = _FAIL;
++ rtw_mfree((u8 *)param, sizeof(*param));
++ }
++
++exit:
++
++_func_exit_;
++
++ return res;
++}
++
++u8 rtw_setopmode_cmd(_adapter *padapter, NDIS_802_11_NETWORK_INFRASTRUCTURE networktype)
++{
++ struct cmd_obj* ph2c;
++ struct setopmode_parm* psetop;
++
++ struct cmd_priv *pcmdpriv= &padapter->cmdpriv;
++ u8 res=_SUCCESS;
++
++_func_enter_;
++
++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj));
++ if(ph2c==NULL){
++ res= _FALSE;
++ goto exit;
++ }
++ psetop = (struct setopmode_parm*)rtw_zmalloc(sizeof(struct setopmode_parm));
++
++ if(psetop==NULL){
++ rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj));
++ res=_FALSE;
++ goto exit;
++ }
++
++ init_h2fwcmd_w_parm_no_rsp(ph2c, psetop, _SetOpMode_CMD_);
++ psetop->mode = (u8)networktype;
++
++ res = rtw_enqueue_cmd(pcmdpriv, ph2c);
++
++exit:
++
++_func_exit_;
++
++ return res;
++}
++
++u8 rtw_setstakey_cmd(_adapter *padapter, u8 *psta, u8 unicast_key)
++{
++ struct cmd_obj* ph2c;
++ struct set_stakey_parm *psetstakey_para;
++ struct cmd_priv *pcmdpriv=&padapter->cmdpriv;
++ struct set_stakey_rsp *psetstakey_rsp = NULL;
++
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct security_priv *psecuritypriv = &padapter->securitypriv;
++ struct sta_info* sta = (struct sta_info* )psta;
++ u8 res=_SUCCESS;
++
++_func_enter_;
++
++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj));
++ if ( ph2c == NULL){
++ res= _FAIL;
++ goto exit;
++ }
++
++ psetstakey_para = (struct set_stakey_parm*)rtw_zmalloc(sizeof(struct set_stakey_parm));
++ if(psetstakey_para==NULL){
++ rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj));
++ res=_FAIL;
++ goto exit;
++ }
++
++ psetstakey_rsp = (struct set_stakey_rsp*)rtw_zmalloc(sizeof(struct set_stakey_rsp));
++ if(psetstakey_rsp == NULL){
++ rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj));
++ rtw_mfree((u8 *) psetstakey_para, sizeof(struct set_stakey_parm));
++ res=_FAIL;
++ goto exit;
++ }
++
++ init_h2fwcmd_w_parm_no_rsp(ph2c, psetstakey_para, _SetStaKey_CMD_);
++ ph2c->rsp = (u8 *) psetstakey_rsp;
++ ph2c->rspsz = sizeof(struct set_stakey_rsp);
++
++ _rtw_memcpy(psetstakey_para->addr, sta->hwaddr,ETH_ALEN);
++
++ if(check_fwstate(pmlmepriv, WIFI_STATION_STATE)){
++#ifdef CONFIG_TDLS
++ if(sta->tdls_sta_state&TDLS_LINKED_STATE)
++ psetstakey_para->algorithm=(u8)sta->dot118021XPrivacy;
++ else
++#endif //CONFIG_TDLS
++ psetstakey_para->algorithm =(unsigned char) psecuritypriv->dot11PrivacyAlgrthm;
++ }else{
++ GET_ENCRY_ALGO(psecuritypriv, sta, psetstakey_para->algorithm, _FALSE);
++ }
++
++ if (unicast_key == _TRUE) {
++#ifdef CONFIG_TDLS
++ if(sta->tdls_sta_state&TDLS_LINKED_STATE)
++ _rtw_memcpy(&psetstakey_para->key, sta->tpk.tk, 16);
++ else
++#endif //CONFIG_TDLS
++ _rtw_memcpy(&psetstakey_para->key, &sta->dot118021x_UncstKey, 16);
++ } else {
++ _rtw_memcpy(&psetstakey_para->key, &psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey, 16);
++ }
++
++ //jeff: set this becasue at least sw key is ready
++ padapter->securitypriv.busetkipkey=_TRUE;
++
++ res = rtw_enqueue_cmd(pcmdpriv, ph2c);
++
++exit:
++
++_func_exit_;
++
++ return res;
++}
++
++u8 rtw_clearstakey_cmd(_adapter *padapter, u8 *psta, u8 entry, u8 enqueue)
++{
++ struct cmd_obj* ph2c;
++ struct set_stakey_parm *psetstakey_para;
++ struct cmd_priv *pcmdpriv=&padapter->cmdpriv;
++ struct set_stakey_rsp *psetstakey_rsp = NULL;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct security_priv *psecuritypriv = &padapter->securitypriv;
++ struct sta_info* sta = (struct sta_info* )psta;
++ u8 res=_SUCCESS;
++
++_func_enter_;
++
++ if(!enqueue)
++ {
++ clear_cam_entry(padapter, entry);
++ }
++ else
++ {
++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj));
++ if ( ph2c == NULL){
++ res= _FAIL;
++ goto exit;
++ }
++
++ psetstakey_para = (struct set_stakey_parm*)rtw_zmalloc(sizeof(struct set_stakey_parm));
++ if(psetstakey_para==NULL){
++ rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj));
++ res=_FAIL;
++ goto exit;
++ }
++
++ psetstakey_rsp = (struct set_stakey_rsp*)rtw_zmalloc(sizeof(struct set_stakey_rsp));
++ if(psetstakey_rsp == NULL){
++ rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj));
++ rtw_mfree((u8 *) psetstakey_para, sizeof(struct set_stakey_parm));
++ res=_FAIL;
++ goto exit;
++ }
++
++ init_h2fwcmd_w_parm_no_rsp(ph2c, psetstakey_para, _SetStaKey_CMD_);
++ ph2c->rsp = (u8 *) psetstakey_rsp;
++ ph2c->rspsz = sizeof(struct set_stakey_rsp);
++
++ _rtw_memcpy(psetstakey_para->addr, sta->hwaddr, ETH_ALEN);
++
++ psetstakey_para->algorithm = _NO_PRIVACY_;
++
++ psetstakey_para->id = entry;
++
++ res = rtw_enqueue_cmd(pcmdpriv, ph2c);
++
++ }
++
++exit:
++
++_func_exit_;
++
++ return res;
++}
++
++u8 rtw_setrttbl_cmd(_adapter *padapter, struct setratable_parm *prate_table)
++{
++ struct cmd_obj* ph2c;
++ struct setratable_parm * psetrttblparm;
++ struct cmd_priv *pcmdpriv=&padapter->cmdpriv;
++ u8 res=_SUCCESS;
++_func_enter_;
++
++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj));
++ if(ph2c==NULL){
++ res= _FAIL;
++ goto exit;
++ }
++ psetrttblparm = (struct setratable_parm*)rtw_zmalloc(sizeof(struct setratable_parm));
++
++ if(psetrttblparm==NULL){
++ rtw_mfree((unsigned char *) ph2c, sizeof(struct cmd_obj));
++ res= _FAIL;
++ goto exit;
++ }
++
++ init_h2fwcmd_w_parm_no_rsp(ph2c, psetrttblparm, GEN_CMD_CODE(_SetRaTable));
++
++ _rtw_memcpy(psetrttblparm,prate_table,sizeof(struct setratable_parm));
++
++ res = rtw_enqueue_cmd(pcmdpriv, ph2c);
++exit:
++_func_exit_;
++ return res;
++
++}
++
++u8 rtw_getrttbl_cmd(_adapter *padapter, struct getratable_rsp *pval)
++{
++ struct cmd_obj* ph2c;
++ struct getratable_parm * pgetrttblparm;
++ struct cmd_priv *pcmdpriv=&padapter->cmdpriv;
++ u8 res=_SUCCESS;
++_func_enter_;
++
++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj));
++ if(ph2c==NULL){
++ res= _FAIL;
++ goto exit;
++ }
++ pgetrttblparm = (struct getratable_parm*)rtw_zmalloc(sizeof(struct getratable_parm));
++
++ if(pgetrttblparm==NULL){
++ rtw_mfree((unsigned char *) ph2c, sizeof(struct cmd_obj));
++ res= _FAIL;
++ goto exit;
++ }
++
++// init_h2fwcmd_w_parm_no_rsp(ph2c, psetrttblparm, GEN_CMD_CODE(_SetRaTable));
++
++ _rtw_init_listhead(&ph2c->list);
++ ph2c->cmdcode =GEN_CMD_CODE(_GetRaTable);
++ ph2c->parmbuf = (unsigned char *)pgetrttblparm;
++ ph2c->cmdsz = sizeof(struct getratable_parm);
++ ph2c->rsp = (u8*)pval;
++ ph2c->rspsz = sizeof(struct getratable_rsp);
++
++ pgetrttblparm ->rsvd = 0x0;
++
++ res = rtw_enqueue_cmd(pcmdpriv, ph2c);
++exit:
++_func_exit_;
++ return res;
++
++}
++
++u8 rtw_setassocsta_cmd(_adapter *padapter, u8 *mac_addr)
++{
++ struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
++ struct cmd_obj* ph2c;
++ struct set_assocsta_parm *psetassocsta_para;
++ struct set_stakey_rsp *psetassocsta_rsp = NULL;
++
++ u8 res=_SUCCESS;
++
++_func_enter_;
++
++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj));
++ if(ph2c==NULL){
++ res= _FAIL;
++ goto exit;
++ }
++
++ psetassocsta_para = (struct set_assocsta_parm*)rtw_zmalloc(sizeof(struct set_assocsta_parm));
++ if(psetassocsta_para==NULL){
++ rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj));
++ res=_FAIL;
++ goto exit;
++ }
++
++ psetassocsta_rsp = (struct set_stakey_rsp*)rtw_zmalloc(sizeof(struct set_assocsta_rsp));
++ if(psetassocsta_rsp==NULL){
++ rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj));
++ rtw_mfree((u8 *) psetassocsta_para, sizeof(struct set_assocsta_parm));
++ return _FAIL;
++ }
++
++ init_h2fwcmd_w_parm_no_rsp(ph2c, psetassocsta_para, _SetAssocSta_CMD_);
++ ph2c->rsp = (u8 *) psetassocsta_rsp;
++ ph2c->rspsz = sizeof(struct set_assocsta_rsp);
++
++ _rtw_memcpy(psetassocsta_para->addr, mac_addr,ETH_ALEN);
++
++ res = rtw_enqueue_cmd(pcmdpriv, ph2c);
++
++exit:
++
++_func_exit_;
++
++ return res;
++ }
++
++u8 rtw_addbareq_cmd(_adapter*padapter, u8 tid, u8 *addr)
++{
++ struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
++ struct cmd_obj* ph2c;
++ struct addBaReq_parm *paddbareq_parm;
++
++ u8 res=_SUCCESS;
++
++_func_enter_;
++
++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj));
++ if(ph2c==NULL){
++ res= _FAIL;
++ goto exit;
++ }
++
++ paddbareq_parm = (struct addBaReq_parm*)rtw_zmalloc(sizeof(struct addBaReq_parm));
++ if(paddbareq_parm==NULL){
++ rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));
++ res= _FAIL;
++ goto exit;
++ }
++
++ paddbareq_parm->tid = tid;
++ _rtw_memcpy(paddbareq_parm->addr, addr, ETH_ALEN);
++
++ init_h2fwcmd_w_parm_no_rsp(ph2c, paddbareq_parm, GEN_CMD_CODE(_AddBAReq));
++
++ //DBG_871X("rtw_addbareq_cmd, tid=%d\n", tid);
++
++ //rtw_enqueue_cmd(pcmdpriv, ph2c);
++ res = rtw_enqueue_cmd(pcmdpriv, ph2c);
++
++exit:
++
++_func_exit_;
++
++ return res;
++}
++//add for CONFIG_IEEE80211W, none 11w can use it
++u8 rtw_reset_securitypriv_cmd(_adapter*padapter)
++{
++ struct cmd_obj* ph2c;
++ struct drvextra_cmd_parm *pdrvextra_cmd_parm;
++ struct cmd_priv *pcmdpriv=&padapter->cmdpriv;
++ u8 res=_SUCCESS;
++
++_func_enter_;
++
++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj));
++ if(ph2c==NULL){
++ res= _FAIL;
++ goto exit;
++ }
++
++ pdrvextra_cmd_parm = (struct drvextra_cmd_parm*)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
++ if(pdrvextra_cmd_parm==NULL){
++ rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));
++ res= _FAIL;
++ goto exit;
++ }
++
++ pdrvextra_cmd_parm->ec_id = RESET_SECURITYPRIV;
++ pdrvextra_cmd_parm->type_size = 0;
++ pdrvextra_cmd_parm->pbuf = (u8 *)padapter;
++
++ init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));
++
++
++ //rtw_enqueue_cmd(pcmdpriv, ph2c);
++ res = rtw_enqueue_cmd(pcmdpriv, ph2c);
++
++exit:
++
++_func_exit_;
++
++ return res;
++
++}
++
++u8 rtw_free_assoc_resources_cmd(_adapter*padapter)
++{
++ struct cmd_obj* ph2c;
++ struct drvextra_cmd_parm *pdrvextra_cmd_parm;
++ struct cmd_priv *pcmdpriv=&padapter->cmdpriv;
++ u8 res=_SUCCESS;
++
++_func_enter_;
++
++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj));
++ if(ph2c==NULL){
++ res= _FAIL;
++ goto exit;
++ }
++
++ pdrvextra_cmd_parm = (struct drvextra_cmd_parm*)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
++ if(pdrvextra_cmd_parm==NULL){
++ rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));
++ res= _FAIL;
++ goto exit;
++ }
++
++ pdrvextra_cmd_parm->ec_id = FREE_ASSOC_RESOURCES;
++ pdrvextra_cmd_parm->type_size = 0;
++ pdrvextra_cmd_parm->pbuf = (u8 *)padapter;
++
++ init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));
++
++
++ //rtw_enqueue_cmd(pcmdpriv, ph2c);
++ res = rtw_enqueue_cmd(pcmdpriv, ph2c);
++
++exit:
++
++_func_exit_;
++
++ return res;
++
++}
++
++
++u8 rtw_dynamic_chk_wk_cmd(_adapter*padapter)
++{
++ struct cmd_obj* ph2c;
++ struct drvextra_cmd_parm *pdrvextra_cmd_parm;
++ struct cmd_priv *pcmdpriv=&padapter->cmdpriv;
++ u8 res=_SUCCESS;
++
++_func_enter_;
++
++ if ((padapter->bDriverStopped == _TRUE)||(padapter->bSurpriseRemoved== _TRUE))
++ goto exit;
++
++
++#ifdef CONFIG_CONCURRENT_MODE
++ if (padapter->adapter_type != PRIMARY_ADAPTER && padapter->pbuddy_adapter)
++ pcmdpriv = &(padapter->pbuddy_adapter->cmdpriv);
++#endif
++
++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj));
++ if(ph2c==NULL){
++ res= _FAIL;
++ goto exit;
++ }
++
++ pdrvextra_cmd_parm = (struct drvextra_cmd_parm*)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
++ if(pdrvextra_cmd_parm==NULL){
++ rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));
++ res= _FAIL;
++ goto exit;
++ }
++
++ pdrvextra_cmd_parm->ec_id = DYNAMIC_CHK_WK_CID;
++ pdrvextra_cmd_parm->type_size = 0;
++ pdrvextra_cmd_parm->pbuf = (u8 *)padapter;
++
++ init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));
++
++
++ //rtw_enqueue_cmd(pcmdpriv, ph2c);
++ res = rtw_enqueue_cmd(pcmdpriv, ph2c);
++
++exit:
++
++_func_exit_;
++
++ return res;
++
++}
++
++u8 rtw_set_ch_cmd(_adapter*padapter, u8 ch, u8 bw, u8 ch_offset, u8 enqueue)
++{
++ struct cmd_obj *pcmdobj;
++ struct set_ch_parm *set_ch_parm;
++ struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
++
++ u8 res=_SUCCESS;
++
++_func_enter_;
++
++ DBG_871X(FUNC_NDEV_FMT" ch:%u, bw:%u, ch_offset:%u\n",
++ FUNC_NDEV_ARG(padapter->pnetdev), ch, bw, ch_offset);
++
++ /* check input parameter */
++
++ /* prepare cmd parameter */
++ set_ch_parm = (struct set_ch_parm *)rtw_zmalloc(sizeof(*set_ch_parm));
++ if (set_ch_parm == NULL) {
++ res= _FAIL;
++ goto exit;
++ }
++ set_ch_parm->ch = ch;
++ set_ch_parm->bw = bw;
++ set_ch_parm->ch_offset = ch_offset;
++
++ if (enqueue) {
++ /* need enqueue, prepare cmd_obj and enqueue */
++ pcmdobj = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj));
++ if(pcmdobj == NULL){
++ rtw_mfree((u8 *)set_ch_parm, sizeof(*set_ch_parm));
++ res=_FAIL;
++ goto exit;
++ }
++
++ init_h2fwcmd_w_parm_no_rsp(pcmdobj, set_ch_parm, GEN_CMD_CODE(_SetChannel));
++ res = rtw_enqueue_cmd(pcmdpriv, pcmdobj);
++ } else {
++ /* no need to enqueue, do the cmd hdl directly and free cmd parameter */
++ if( H2C_SUCCESS !=set_ch_hdl(padapter, (u8 *)set_ch_parm) )
++ res = _FAIL;
++
++ rtw_mfree((u8 *)set_ch_parm, sizeof(*set_ch_parm));
++ }
++
++ /* do something based on res... */
++
++exit:
++
++ DBG_871X(FUNC_NDEV_FMT" res:%u\n", FUNC_NDEV_ARG(padapter->pnetdev), res);
++
++_func_exit_;
++
++ return res;
++}
++
++u8 rtw_set_chplan_cmd(_adapter*padapter, u8 chplan, u8 enqueue)
++{
++ struct cmd_obj* pcmdobj;
++ struct SetChannelPlan_param *setChannelPlan_param;
++ struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
++
++ u8 res=_SUCCESS;
++
++_func_enter_;
++
++ RT_TRACE(_module_rtl871x_cmd_c_, _drv_notice_, ("+rtw_set_chplan_cmd\n"));
++
++ //check input parameter
++ if(!rtw_is_channel_plan_valid(chplan)) {
++ res = _FAIL;
++ goto exit;
++ }
++
++ //prepare cmd parameter
++ setChannelPlan_param = (struct SetChannelPlan_param *)rtw_zmalloc(sizeof(struct SetChannelPlan_param));
++ if(setChannelPlan_param == NULL) {
++ res= _FAIL;
++ goto exit;
++ }
++ setChannelPlan_param->channel_plan=chplan;
++
++ if(enqueue)
++ {
++ //need enqueue, prepare cmd_obj and enqueue
++ pcmdobj = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj));
++ if(pcmdobj == NULL){
++ rtw_mfree((u8 *)setChannelPlan_param, sizeof(struct SetChannelPlan_param));
++ res=_FAIL;
++ goto exit;
++ }
++
++ init_h2fwcmd_w_parm_no_rsp(pcmdobj, setChannelPlan_param, GEN_CMD_CODE(_SetChannelPlan));
++ res = rtw_enqueue_cmd(pcmdpriv, pcmdobj);
++ }
++ else
++ {
++ //no need to enqueue, do the cmd hdl directly and free cmd parameter
++ if( H2C_SUCCESS !=set_chplan_hdl(padapter, (unsigned char *)setChannelPlan_param) )
++ res = _FAIL;
++
++ rtw_mfree((u8 *)setChannelPlan_param, sizeof(struct SetChannelPlan_param));
++ }
++
++ //do something based on res...
++ if(res == _SUCCESS)
++ padapter->mlmepriv.ChannelPlan = chplan;
++
++exit:
++
++_func_exit_;
++
++ return res;
++}
++
++u8 rtw_led_blink_cmd(_adapter*padapter, PLED_871x pLed)
++{
++ struct cmd_obj* pcmdobj;
++ struct LedBlink_param *ledBlink_param;
++ struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
++
++ u8 res=_SUCCESS;
++
++_func_enter_;
++
++ RT_TRACE(_module_rtl871x_cmd_c_, _drv_notice_, ("+rtw_led_blink_cmd\n"));
++
++ pcmdobj = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj));
++ if(pcmdobj == NULL){
++ res=_FAIL;
++ goto exit;
++ }
++
++ ledBlink_param = (struct LedBlink_param *)rtw_zmalloc(sizeof(struct LedBlink_param));
++ if(ledBlink_param == NULL) {
++ rtw_mfree((u8 *)pcmdobj, sizeof(struct cmd_obj));
++ res= _FAIL;
++ goto exit;
++ }
++
++ ledBlink_param->pLed=pLed;
++
++ init_h2fwcmd_w_parm_no_rsp(pcmdobj, ledBlink_param, GEN_CMD_CODE(_LedBlink));
++ res = rtw_enqueue_cmd(pcmdpriv, pcmdobj);
++
++exit:
++
++_func_exit_;
++
++ return res;
++}
++
++u8 rtw_set_csa_cmd(_adapter*padapter, u8 new_ch_no)
++{
++ struct cmd_obj* pcmdobj;
++ struct SetChannelSwitch_param*setChannelSwitch_param;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
++
++ u8 res=_SUCCESS;
++
++_func_enter_;
++
++ RT_TRACE(_module_rtl871x_cmd_c_, _drv_notice_, ("+rtw_set_csa_cmd\n"));
++
++ pcmdobj = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj));
++ if(pcmdobj == NULL){
++ res=_FAIL;
++ goto exit;
++ }
++
++ setChannelSwitch_param = (struct SetChannelSwitch_param *)rtw_zmalloc(sizeof(struct SetChannelSwitch_param));
++ if(setChannelSwitch_param == NULL) {
++ rtw_mfree((u8 *)pcmdobj, sizeof(struct cmd_obj));
++ res= _FAIL;
++ goto exit;
++ }
++
++ setChannelSwitch_param->new_ch_no=new_ch_no;
++
++ init_h2fwcmd_w_parm_no_rsp(pcmdobj, setChannelSwitch_param, GEN_CMD_CODE(_SetChannelSwitch));
++ res = rtw_enqueue_cmd(pcmdpriv, pcmdobj);
++
++exit:
++
++_func_exit_;
++
++ return res;
++}
++
++u8 rtw_tdls_cmd(_adapter *padapter, u8 *addr, u8 option)
++{
++ struct cmd_obj* pcmdobj;
++ struct TDLSoption_param *TDLSoption;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
++
++ u8 res=_SUCCESS;
++
++_func_enter_;
++
++#ifdef CONFIG_TDLS
++
++ RT_TRACE(_module_rtl871x_cmd_c_, _drv_notice_, ("+rtw_set_tdls_cmd\n"));
++
++ pcmdobj = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj));
++ if(pcmdobj == NULL){
++ res=_FAIL;
++ goto exit;
++ }
++
++ TDLSoption= (struct TDLSoption_param *)rtw_zmalloc(sizeof(struct TDLSoption_param));
++ if(TDLSoption == NULL) {
++ rtw_mfree((u8 *)pcmdobj, sizeof(struct cmd_obj));
++ res= _FAIL;
++ goto exit;
++ }
++
++ _rtw_spinlock(&(padapter->tdlsinfo.cmd_lock));
++ _rtw_memcpy(TDLSoption->addr, addr, 6);
++ TDLSoption->option = option;
++ _rtw_spinunlock(&(padapter->tdlsinfo.cmd_lock));
++ init_h2fwcmd_w_parm_no_rsp(pcmdobj, TDLSoption, GEN_CMD_CODE(_TDLS));
++ res = rtw_enqueue_cmd(pcmdpriv, pcmdobj);
++
++#endif //CONFIG_TDLS
++
++exit:
++
++
++_func_exit_;
++
++ return res;
++}
++
++static void traffic_status_watchdog(_adapter *padapter)
++{
++#ifdef CONFIG_LPS
++ u8 bEnterPS;
++#endif
++ u16 BusyThreshold = 100;
++ u8 bBusyTraffic = _FALSE, bTxBusyTraffic = _FALSE, bRxBusyTraffic = _FALSE;
++ u8 bHigherBusyTraffic = _FALSE, bHigherBusyRxTraffic = _FALSE, bHigherBusyTxTraffic = _FALSE;
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++#ifdef CONFIG_TDLS
++ struct tdls_info *ptdlsinfo = &(padapter->tdlsinfo);
++#endif //CONFIG_TDLS
++
++ RT_LINK_DETECT_T * link_detect = &pmlmepriv->LinkDetectInfo;
++
++ //
++ // Determine if our traffic is busy now
++ //
++ if((check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE)
++ /*&& !MgntInitAdapterInProgress(pMgntInfo)*/)
++ {
++
++ // if we raise bBusyTraffic in last watchdog, using lower threshold.
++ if (pmlmepriv->LinkDetectInfo.bBusyTraffic)
++ BusyThreshold = 75;
++ if( pmlmepriv->LinkDetectInfo.NumRxOkInPeriod > BusyThreshold ||
++ pmlmepriv->LinkDetectInfo.NumTxOkInPeriod > BusyThreshold )
++ {
++ bBusyTraffic = _TRUE;
++
++ if(pmlmepriv->LinkDetectInfo.NumRxOkInPeriod > BusyThreshold)
++ bRxBusyTraffic = _TRUE;
++
++ if(pmlmepriv->LinkDetectInfo.NumTxOkInPeriod > BusyThreshold)
++ bTxBusyTraffic = _TRUE;
++ }
++
++ // Higher Tx/Rx data.
++ if( pmlmepriv->LinkDetectInfo.NumRxOkInPeriod > 4000 ||
++ pmlmepriv->LinkDetectInfo.NumTxOkInPeriod > 4000 )
++ {
++ bHigherBusyTraffic = _TRUE;
++
++ // Extremely high Rx data.
++ if(pmlmepriv->LinkDetectInfo.NumRxOkInPeriod > 5000)
++ bHigherBusyRxTraffic = _TRUE;
++
++ // Extremely high Tx data.
++ if(pmlmepriv->LinkDetectInfo.NumTxOkInPeriod > 5000)
++ bHigherBusyTxTraffic = _TRUE;
++ }
++
++#ifdef CONFIG_TRAFFIC_PROTECT
++#define TX_ACTIVE_TH 2
++#define RX_ACTIVE_TH 1
++#define TRAFFIC_PROTECT_PERIOD_MS 4500
++
++ if (link_detect->NumTxOkInPeriod > TX_ACTIVE_TH
++ || link_detect->NumRxUnicastOkInPeriod > RX_ACTIVE_TH) {
++
++ LOG_LEVEL(_drv_info_, FUNC_ADPT_FMT" acqiure wake_lock for %u ms(tx:%d,rx_unicast:%d)\n",
++ FUNC_ADPT_ARG(padapter),
++ TRAFFIC_PROTECT_PERIOD_MS,
++ link_detect->NumTxOkInPeriod,
++ link_detect->NumRxUnicastOkInPeriod);
++
++ rtw_lock_suspend_timeout(TRAFFIC_PROTECT_PERIOD_MS);
++ }
++#endif
++
++#ifdef CONFIG_TDLS
++#ifdef CONFIG_TDLS_AUTOSETUP
++ if( ( ptdlsinfo->watchdog_count % TDLS_WATCHDOG_PERIOD ) == 0 ) //TDLS_WATCHDOG_PERIOD * 2sec, periodically sending
++ issue_tdls_dis_req( padapter, NULL );
++ ptdlsinfo->watchdog_count++;
++#endif //CONFIG_TDLS_AUTOSETUP
++#endif //CONFIG_TDLS
++
++#ifdef CONFIG_LPS
++ // check traffic for powersaving.
++ if( ((pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod + pmlmepriv->LinkDetectInfo.NumTxOkInPeriod) > 8 ) ||
++ (pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod > 2) )
++ {
++ //DBG_871X("Tx = %d, Rx = %d \n",pmlmepriv->LinkDetectInfo.NumTxOkInPeriod,pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod);
++ bEnterPS= _FALSE;
++ }
++ else
++ {
++ bEnterPS= _TRUE;
++ }
++
++ // LeisurePS only work in infra mode.
++ if(bEnterPS)
++ {
++ LPS_Enter(padapter);
++ }
++ else
++ {
++ LPS_Leave(padapter);
++ }
++#endif
++ }
++ else
++ {
++#ifdef CONFIG_LPS
++ LPS_Leave(padapter);
++#endif
++ }
++
++ pmlmepriv->LinkDetectInfo.NumRxOkInPeriod = 0;
++ pmlmepriv->LinkDetectInfo.NumTxOkInPeriod = 0;
++ pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod = 0;
++ pmlmepriv->LinkDetectInfo.bBusyTraffic = bBusyTraffic;
++ pmlmepriv->LinkDetectInfo.bTxBusyTraffic = bTxBusyTraffic;
++ pmlmepriv->LinkDetectInfo.bRxBusyTraffic = bRxBusyTraffic;
++ pmlmepriv->LinkDetectInfo.bHigherBusyTraffic = bHigherBusyTraffic;
++ pmlmepriv->LinkDetectInfo.bHigherBusyRxTraffic = bHigherBusyRxTraffic;
++ pmlmepriv->LinkDetectInfo.bHigherBusyTxTraffic = bHigherBusyTxTraffic;
++
++}
++
++void dynamic_chk_wk_hdl(_adapter *padapter, u8 *pbuf, int sz);
++void dynamic_chk_wk_hdl(_adapter *padapter, u8 *pbuf, int sz)
++{
++ struct mlme_priv *pmlmepriv;
++
++ if ((padapter->bDriverStopped == _TRUE)||(padapter->bSurpriseRemoved== _TRUE))
++ return;
++
++ if((void*)padapter != (void*)pbuf && padapter->pbuddy_adapter == NULL)
++ return;
++
++ padapter = (_adapter *)pbuf;
++
++ if ((padapter->bDriverStopped == _TRUE)||(padapter->bSurpriseRemoved== _TRUE))
++ return;
++
++ pmlmepriv = &(padapter->mlmepriv);
++
++#ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK
++#ifdef CONFIG_AP_MODE
++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE)
++ {
++ expire_timeout_chk(padapter);
++ }
++#endif
++#endif //CONFIG_ACTIVE_KEEP_ALIVE_CHECK
++
++ #ifdef DBG_CONFIG_ERROR_DETECT
++ rtw_hal_sreset_xmit_status_check(padapter);
++ #endif
++
++ //if(check_fwstate(pmlmepriv, _FW_UNDER_LINKING|_FW_UNDER_SURVEY)==_FALSE)
++ {
++ linked_status_chk(padapter);
++ traffic_status_watchdog(padapter);
++ }
++
++ rtw_hal_dm_watchdog(padapter);
++
++ //check_hw_pbc(padapter, pdrvextra_cmd->pbuf, pdrvextra_cmd->type_size);
++
++}
++
++#ifdef CONFIG_LPS
++
++void lps_ctrl_wk_hdl(_adapter *padapter, u8 lps_ctrl_type);
++void lps_ctrl_wk_hdl(_adapter *padapter, u8 lps_ctrl_type)
++{
++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ u8 mstatus;
++
++_func_enter_;
++
++ if((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)
++ || (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE))
++ {
++ return;
++ }
++
++ switch(lps_ctrl_type)
++ {
++ case LPS_CTRL_SCAN:
++ //DBG_871X("LPS_CTRL_SCAN \n");
++ LeaveAllPowerSaveMode(padapter);
++ break;
++ case LPS_CTRL_JOINBSS:
++ //DBG_871X("LPS_CTRL_JOINBSS \n");
++ LPS_Leave(padapter);
++ break;
++ case LPS_CTRL_CONNECT:
++ //DBG_871X("LPS_CTRL_CONNECT \n");
++ mstatus = 1;
++ // Reset LPS Setting
++ padapter->pwrctrlpriv.LpsIdleCount = 0;
++ rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_JOINBSSRPT, (u8 *)(&mstatus));
++ break;
++ case LPS_CTRL_DISCONNECT:
++ //DBG_871X("LPS_CTRL_DISCONNECT \n");
++ mstatus = 0;
++ LPS_Leave(padapter);
++ rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_JOINBSSRPT, (u8 *)(&mstatus));
++ break;
++ case LPS_CTRL_SPECIAL_PACKET:
++ //DBG_871X("LPS_CTRL_SPECIAL_PACKET \n");
++ pwrpriv->DelayLPSLastTimeStamp = rtw_get_current_time();
++ LPS_Leave(padapter);
++ break;
++
++ default:
++ break;
++ }
++
++_func_exit_;
++}
++
++u8 rtw_lps_ctrl_wk_cmd(_adapter*padapter, u8 lps_ctrl_type, u8 enqueue)
++{
++ struct cmd_obj *ph2c;
++ struct drvextra_cmd_parm *pdrvextra_cmd_parm;
++ struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
++ //struct pwrctrl_priv *pwrctrlpriv = &padapter->pwrctrlpriv;
++ u8 res = _SUCCESS;
++
++_func_enter_;
++
++ //if(!pwrctrlpriv->bLeisurePs)
++ // return res;
++
++#ifdef CONFIG_CONCURRENT_MODE
++ if (padapter->iface_type != IFACE_PORT0)
++ return res;
++#endif
++
++ if(enqueue)
++ {
++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj));
++ if(ph2c==NULL){
++ res= _FAIL;
++ goto exit;
++ }
++
++ pdrvextra_cmd_parm = (struct drvextra_cmd_parm*)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
++ if(pdrvextra_cmd_parm==NULL){
++ rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));
++ res= _FAIL;
++ goto exit;
++ }
++
++ pdrvextra_cmd_parm->ec_id = LPS_CTRL_WK_CID;
++ pdrvextra_cmd_parm->type_size = lps_ctrl_type;
++ pdrvextra_cmd_parm->pbuf = NULL;
++
++ init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));
++
++ res = rtw_enqueue_cmd(pcmdpriv, ph2c);
++ }
++ else
++ {
++ lps_ctrl_wk_hdl(padapter, lps_ctrl_type);
++ }
++
++exit:
++
++_func_exit_;
++
++ return res;
++
++}
++
++#endif
++#ifdef CONFIG_ANTENNA_DIVERSITY
++
++void antenna_select_wk_hdl(_adapter *padapter, u8 antenna)
++{
++ rtw_hal_set_hwreg(padapter, HW_VAR_ANTENNA_DIVERSITY_SELECT, (u8 *)(&antenna));
++}
++
++u8 rtw_antenna_select_cmd(_adapter*padapter, u8 antenna,u8 enqueue)
++{
++ struct cmd_obj *ph2c;
++ struct drvextra_cmd_parm *pdrvextra_cmd_parm;
++ struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
++ u8 bSupportAntDiv = _FALSE;
++ u8 res = _SUCCESS;
++
++_func_enter_;
++ rtw_hal_get_def_var(padapter, HAL_DEF_IS_SUPPORT_ANT_DIV, &(bSupportAntDiv));
++ if(_FALSE == bSupportAntDiv ) return res;
++
++ if(_TRUE == enqueue)
++ {
++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj));
++ if(ph2c==NULL){
++ res= _FAIL;
++ goto exit;
++ }
++
++ pdrvextra_cmd_parm = (struct drvextra_cmd_parm*)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
++ if(pdrvextra_cmd_parm==NULL){
++ rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));
++ res= _FAIL;
++ goto exit;
++ }
++
++ pdrvextra_cmd_parm->ec_id = ANT_SELECT_WK_CID;
++ pdrvextra_cmd_parm->type_size = antenna;
++ pdrvextra_cmd_parm->pbuf = NULL;
++ init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));
++
++ res = rtw_enqueue_cmd(pcmdpriv, ph2c);
++ }
++ else{
++ antenna_select_wk_hdl(padapter,antenna );
++ }
++exit:
++
++_func_exit_;
++
++ return res;
++
++}
++#endif
++
++void power_saving_wk_hdl(_adapter *padapter, u8 *pbuf, int sz);
++void power_saving_wk_hdl(_adapter *padapter, u8 *pbuf, int sz)
++{
++ rtw_ps_processor(padapter);
++}
++
++//add for CONFIG_IEEE80211W, none 11w can use it
++void reset_securitypriv_hdl(_adapter *padapter)
++{
++ rtw_reset_securitypriv(padapter);
++}
++
++void free_assoc_resources_hdl(_adapter *padapter)
++{
++ rtw_free_assoc_resources(padapter, 1);
++}
++
++#ifdef CONFIG_P2P
++u8 p2p_protocol_wk_cmd(_adapter*padapter, int intCmdType )
++{
++ struct cmd_obj *ph2c;
++ struct drvextra_cmd_parm *pdrvextra_cmd_parm;
++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo);
++ struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
++ u8 res = _SUCCESS;
++
++_func_enter_;
++
++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
++ {
++ return res;
++ }
++
++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj));
++ if(ph2c==NULL){
++ res= _FAIL;
++ goto exit;
++ }
++
++ pdrvextra_cmd_parm = (struct drvextra_cmd_parm*)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
++ if(pdrvextra_cmd_parm==NULL){
++ rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));
++ res= _FAIL;
++ goto exit;
++ }
++
++ pdrvextra_cmd_parm->ec_id = P2P_PROTO_WK_CID;
++ pdrvextra_cmd_parm->type_size = intCmdType; // As the command tppe.
++ pdrvextra_cmd_parm->pbuf = NULL; // Must be NULL here
++
++ init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));
++
++ res = rtw_enqueue_cmd(pcmdpriv, ph2c);
++
++exit:
++
++_func_exit_;
++
++ return res;
++
++}
++#endif //CONFIG_P2P
++
++u8 rtw_ps_cmd(_adapter*padapter)
++{
++ struct cmd_obj *ppscmd;
++ struct drvextra_cmd_parm *pdrvextra_cmd_parm;
++ struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
++
++ u8 res = _SUCCESS;
++_func_enter_;
++
++#ifdef CONFIG_CONCURRENT_MODE
++ if (padapter->adapter_type != PRIMARY_ADAPTER)
++ goto exit;
++#endif
++
++ ppscmd = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj));
++ if(ppscmd==NULL){
++ res= _FAIL;
++ goto exit;
++ }
++
++ pdrvextra_cmd_parm = (struct drvextra_cmd_parm*)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
++ if(pdrvextra_cmd_parm==NULL){
++ rtw_mfree((unsigned char *)ppscmd, sizeof(struct cmd_obj));
++ res= _FAIL;
++ goto exit;
++ }
++
++ pdrvextra_cmd_parm->ec_id = POWER_SAVING_CTRL_WK_CID;
++ pdrvextra_cmd_parm->pbuf = NULL;
++ init_h2fwcmd_w_parm_no_rsp(ppscmd, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));
++
++ res = rtw_enqueue_cmd(pcmdpriv, ppscmd);
++
++exit:
++
++_func_exit_;
++
++ return res;
++
++}
++
++#ifdef CONFIG_AP_MODE
++
++static void rtw_chk_hi_queue_hdl(_adapter *padapter)
++{
++ int cnt=0;
++ struct sta_info *psta_bmc;
++ struct sta_priv *pstapriv = &padapter->stapriv;
++
++ psta_bmc = rtw_get_bcmc_stainfo(padapter);
++ if(!psta_bmc)
++ return;
++
++
++ if(psta_bmc->sleepq_len==0)
++ {
++ while((rtw_read32(padapter, 0x414)&0x00ffff00)!=0)
++ {
++ rtw_msleep_os(100);
++
++ cnt++;
++
++ if(cnt>10)
++ break;
++ }
++
++ if(cnt<=10)
++ {
++ pstapriv->tim_bitmap &= ~BIT(0);
++ pstapriv->sta_dz_bitmap &= ~BIT(0);
++
++ update_beacon(padapter, _TIM_IE_, NULL, _FALSE);
++ }
++ }
++
++}
++
++u8 rtw_chk_hi_queue_cmd(_adapter*padapter)
++{
++ struct cmd_obj *ph2c;
++ struct drvextra_cmd_parm *pdrvextra_cmd_parm;
++ struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
++ u8 res = _SUCCESS;
++
++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj));
++ if(ph2c==NULL){
++ res= _FAIL;
++ goto exit;
++ }
++
++ pdrvextra_cmd_parm = (struct drvextra_cmd_parm*)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
++ if(pdrvextra_cmd_parm==NULL){
++ rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));
++ res= _FAIL;
++ goto exit;
++ }
++
++ pdrvextra_cmd_parm->ec_id = CHECK_HIQ_WK_CID;
++ pdrvextra_cmd_parm->type_size = 0;
++ pdrvextra_cmd_parm->pbuf = NULL;
++
++ init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));
++
++ res = rtw_enqueue_cmd(pcmdpriv, ph2c);
++
++exit:
++
++ return res;
++
++}
++#endif
++
++u8 rtw_c2h_wk_cmd(PADAPTER padapter, u8 *c2h_evt)
++{
++ struct cmd_obj *ph2c;
++ struct drvextra_cmd_parm *pdrvextra_cmd_parm;
++ struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
++ u8 res = _SUCCESS;
++
++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj));
++ if (ph2c == NULL) {
++ res = _FAIL;
++ goto exit;
++ }
++
++ pdrvextra_cmd_parm = (struct drvextra_cmd_parm*)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
++ if (pdrvextra_cmd_parm == NULL) {
++ rtw_mfree((u8*)ph2c, sizeof(struct cmd_obj));
++ res = _FAIL;
++ goto exit;
++ }
++
++ pdrvextra_cmd_parm->ec_id = C2H_WK_CID;
++ pdrvextra_cmd_parm->type_size = c2h_evt?16:0;
++ pdrvextra_cmd_parm->pbuf = c2h_evt;
++
++ init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));
++
++ res = rtw_enqueue_cmd(pcmdpriv, ph2c);
++
++exit:
++
++ return res;
++}
++
++s32 c2h_evt_hdl(_adapter *adapter, struct c2h_evt_hdr *c2h_evt, c2h_id_filter filter)
++{
++ s32 ret = _FAIL;
++ u8 buf[16];
++
++ if (!c2h_evt) {
++ /* No c2h event in cmd_obj, read c2h event before handling*/
++ if (c2h_evt_read(adapter, buf) == _SUCCESS) {
++ c2h_evt = (struct c2h_evt_hdr *)buf;
++
++ if (filter && filter(c2h_evt->id) == _FALSE)
++ goto exit;
++
++ ret = rtw_hal_c2h_handler(adapter, c2h_evt);
++ }
++ } else {
++
++ if (filter && filter(c2h_evt->id) == _FALSE)
++ goto exit;
++
++ ret = rtw_hal_c2h_handler(adapter, c2h_evt);
++ }
++exit:
++ return ret;
++}
++
++#ifdef CONFIG_C2H_WK
++static void c2h_wk_callback(_workitem *work)
++{
++ struct evt_priv *evtpriv = container_of(work, struct evt_priv, c2h_wk);
++ _adapter *adapter = container_of(evtpriv, _adapter, evtpriv);
++ struct c2h_evt_hdr *c2h_evt;
++ c2h_id_filter ccx_id_filter = rtw_hal_c2h_id_filter_ccx(adapter);
++
++ evtpriv->c2h_wk_alive = _TRUE;
++
++ while (!rtw_cbuf_empty(evtpriv->c2h_queue)) {
++ if ((c2h_evt = (struct c2h_evt_hdr *)rtw_cbuf_pop(evtpriv->c2h_queue)) != NULL) {
++ /* This C2H event is read, clear it */
++ c2h_evt_clear(adapter);
++ } else if ((c2h_evt = (struct c2h_evt_hdr *)rtw_malloc(16)) != NULL) {
++ /* This C2H event is not read, read & clear now */
++ if (c2h_evt_read(adapter, (u8*)c2h_evt) != _SUCCESS)
++ continue;
++ }
++
++ /* Special pointer to trigger c2h_evt_clear only */
++ if ((void *)c2h_evt == (void *)evtpriv)
++ continue;
++
++ if (!c2h_evt_exist(c2h_evt)) {
++ rtw_mfree((u8*)c2h_evt, 16);
++ continue;
++ }
++
++ if (ccx_id_filter(c2h_evt->id) == _TRUE) {
++ /* Handle CCX report here */
++ rtw_hal_c2h_handler(adapter, c2h_evt);
++ rtw_mfree((u8*)c2h_evt, 16);
++ } else {
++ /* Enqueue into cmd_thread for others */
++ rtw_c2h_wk_cmd(adapter, (u8 *)c2h_evt);
++ }
++ }
++
++ evtpriv->c2h_wk_alive = _FALSE;
++}
++#endif
++
++u8 rtw_drvextra_cmd_hdl(_adapter *padapter, unsigned char *pbuf)
++{
++ struct drvextra_cmd_parm *pdrvextra_cmd;
++
++ if(!pbuf)
++ return H2C_PARAMETERS_ERROR;
++
++ pdrvextra_cmd = (struct drvextra_cmd_parm*)pbuf;
++
++ switch(pdrvextra_cmd->ec_id)
++ {
++ case DYNAMIC_CHK_WK_CID:
++ dynamic_chk_wk_hdl(padapter, pdrvextra_cmd->pbuf, pdrvextra_cmd->type_size);
++ break;
++ case POWER_SAVING_CTRL_WK_CID:
++ power_saving_wk_hdl(padapter, pdrvextra_cmd->pbuf, pdrvextra_cmd->type_size);
++ break;
++#ifdef CONFIG_LPS
++ case LPS_CTRL_WK_CID:
++ lps_ctrl_wk_hdl(padapter, (u8)pdrvextra_cmd->type_size);
++ break;
++#endif
++#ifdef CONFIG_ANTENNA_DIVERSITY
++ case ANT_SELECT_WK_CID:
++ antenna_select_wk_hdl(padapter, pdrvextra_cmd->type_size);
++ break;
++#endif
++#ifdef CONFIG_P2P_PS
++ case P2P_PS_WK_CID:
++ p2p_ps_wk_hdl(padapter, pdrvextra_cmd->type_size);
++ break;
++#endif // CONFIG_P2P_PS
++ case P2P_PROTO_WK_CID:
++ // Commented by Albert 2011/07/01
++ // I used the type_size as the type command
++ p2p_protocol_wk_hdl( padapter, pdrvextra_cmd->type_size );
++ break;
++#ifdef CONFIG_AP_MODE
++ case CHECK_HIQ_WK_CID:
++ rtw_chk_hi_queue_hdl(padapter);
++ break;
++#endif //CONFIG_AP_MODE
++#ifdef CONFIG_INTEL_WIDI
++ case INTEl_WIDI_WK_CID:
++ intel_widi_wk_hdl(padapter, pdrvextra_cmd->type_size, pdrvextra_cmd->pbuf);
++ break;
++#endif //CONFIG_INTEL_WIDI
++ //add for CONFIG_IEEE80211W, none 11w can use it
++ case RESET_SECURITYPRIV:
++ reset_securitypriv_hdl(padapter);
++ break;
++ case FREE_ASSOC_RESOURCES:
++ free_assoc_resources_hdl(padapter);
++ break;
++ case C2H_WK_CID:
++ c2h_evt_hdl(padapter, (struct c2h_evt_hdr *)pdrvextra_cmd->pbuf, NULL);
++ break;
++
++ default:
++ break;
++ }
++
++
++ if(pdrvextra_cmd->pbuf && pdrvextra_cmd->type_size>0)
++ {
++ rtw_mfree(pdrvextra_cmd->pbuf, pdrvextra_cmd->type_size);
++ }
++
++
++ return H2C_SUCCESS;
++
++}
++
++void rtw_survey_cmd_callback(_adapter* padapter , struct cmd_obj *pcmd)
++{
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++
++_func_enter_;
++
++ if(pcmd->res == H2C_DROPPED)
++ {
++ //TODO: cancel timer and do timeout handler directly...
++ //need to make timeout handlerOS independent
++ _set_timer(&pmlmepriv->scan_to_timer, 1);
++ }
++ else if (pcmd->res != H2C_SUCCESS) {
++ _set_timer(&pmlmepriv->scan_to_timer, 1);
++ RT_TRACE(_module_rtl871x_cmd_c_,_drv_err_,("\n ********Error: MgntActrtw_set_802_11_bssid_LIST_SCAN Fail ************\n\n."));
++ }
++
++ // free cmd
++ rtw_free_cmd_obj(pcmd);
++
++_func_exit_;
++}
++void rtw_disassoc_cmd_callback(_adapter* padapter, struct cmd_obj *pcmd)
++{
++ _irqL irqL;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++
++_func_enter_;
++
++ if (pcmd->res != H2C_SUCCESS)
++ {
++ _enter_critical_bh(&pmlmepriv->lock, &irqL);
++ set_fwstate(pmlmepriv, _FW_LINKED);
++ _exit_critical_bh(&pmlmepriv->lock, &irqL);
++
++ RT_TRACE(_module_rtl871x_cmd_c_,_drv_err_,("\n ***Error: disconnect_cmd_callback Fail ***\n."));
++
++ goto exit;
++ }
++#ifdef CONFIG_BR_EXT
++ else //clear bridge database
++ nat25_db_cleanup(padapter);
++#endif //CONFIG_BR_EXT
++
++ // free cmd
++ rtw_free_cmd_obj(pcmd);
++
++exit:
++
++_func_exit_;
++}
++
++
++void rtw_joinbss_cmd_callback(_adapter* padapter, struct cmd_obj *pcmd)
++{
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++
++_func_enter_;
++
++ if(pcmd->res == H2C_DROPPED)
++ {
++ //TODO: cancel timer and do timeout handler directly...
++ //need to make timeout handlerOS independent
++ _set_timer(&pmlmepriv->assoc_timer, 1);
++ }
++ else if(pcmd->res != H2C_SUCCESS)
++ {
++ RT_TRACE(_module_rtl871x_cmd_c_,_drv_err_,("********Error:rtw_select_and_join_from_scanned_queue Wait Sema Fail ************\n"));
++ _set_timer(&pmlmepriv->assoc_timer, 1);
++ }
++
++ rtw_free_cmd_obj(pcmd);
++
++_func_exit_;
++}
++
++void rtw_createbss_cmd_callback(_adapter *padapter, struct cmd_obj *pcmd)
++{
++ _irqL irqL;
++ u8 timer_cancelled;
++ struct sta_info *psta = NULL;
++ struct wlan_network *pwlan = NULL;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)pcmd->parmbuf;
++ struct wlan_network *tgt_network = &(pmlmepriv->cur_network);
++
++_func_enter_;
++
++ if((pcmd->res != H2C_SUCCESS))
++ {
++ RT_TRACE(_module_rtl871x_cmd_c_,_drv_err_,("\n ********Error: rtw_createbss_cmd_callback Fail ************\n\n."));
++ _set_timer(&pmlmepriv->assoc_timer, 1 );
++ }
++
++ _cancel_timer(&pmlmepriv->assoc_timer, &timer_cancelled);
++
++#ifdef CONFIG_FW_MLMLE
++ //endian_convert
++ pnetwork->Length = le32_to_cpu(pnetwork->Length);
++ pnetwork->Ssid.SsidLength = le32_to_cpu(pnetwork->Ssid.SsidLength);
++ pnetwork->Privacy =le32_to_cpu(pnetwork->Privacy);
++ pnetwork->Rssi = le32_to_cpu(pnetwork->Rssi);
++ pnetwork->NetworkTypeInUse =le32_to_cpu(pnetwork->NetworkTypeInUse);
++ pnetwork->Configuration.ATIMWindow = le32_to_cpu(pnetwork->Configuration.ATIMWindow);
++ //pnetwork->Configuration.BeaconPeriod = le32_to_cpu(pnetwork->Configuration.BeaconPeriod);
++ pnetwork->Configuration.DSConfig =le32_to_cpu(pnetwork->Configuration.DSConfig);
++ pnetwork->Configuration.FHConfig.DwellTime=le32_to_cpu(pnetwork->Configuration.FHConfig.DwellTime);
++ pnetwork->Configuration.FHConfig.HopPattern=le32_to_cpu(pnetwork->Configuration.FHConfig.HopPattern);
++ pnetwork->Configuration.FHConfig.HopSet=le32_to_cpu(pnetwork->Configuration.FHConfig.HopSet);
++ pnetwork->Configuration.FHConfig.Length=le32_to_cpu(pnetwork->Configuration.FHConfig.Length);
++ pnetwork->Configuration.Length = le32_to_cpu(pnetwork->Configuration.Length);
++ pnetwork->InfrastructureMode = le32_to_cpu(pnetwork->InfrastructureMode);
++ pnetwork->IELength = le32_to_cpu(pnetwork->IELength);
++#endif
++
++ _enter_critical_bh(&pmlmepriv->lock, &irqL);
++
++
++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) )
++ {
++ psta = rtw_get_stainfo(&padapter->stapriv, pnetwork->MacAddress);
++ if(!psta)
++ {
++ psta = rtw_alloc_stainfo(&padapter->stapriv, pnetwork->MacAddress);
++ if (psta == NULL)
++ {
++ RT_TRACE(_module_rtl871x_cmd_c_,_drv_err_,("\nCan't alloc sta_info when createbss_cmd_callback\n"));
++ goto createbss_cmd_fail ;
++ }
++ }
++
++ rtw_indicate_connect( padapter);
++ }
++ else
++ {
++ _irqL irqL;
++
++ pwlan = _rtw_alloc_network(pmlmepriv);
++ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++ if ( pwlan == NULL)
++ {
++ pwlan = rtw_get_oldest_wlan_network(&pmlmepriv->scanned_queue);
++ if( pwlan == NULL)
++ {
++ RT_TRACE(_module_rtl871x_cmd_c_,_drv_err_,("\n Error: can't get pwlan in rtw_joinbss_event_callback \n"));
++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++ goto createbss_cmd_fail;
++ }
++ pwlan->last_scanned = rtw_get_current_time();
++ }
++ else
++ {
++ rtw_list_insert_tail(&(pwlan->list), &pmlmepriv->scanned_queue.queue);
++ }
++
++ pnetwork->Length = get_WLAN_BSSID_EX_sz(pnetwork);
++ _rtw_memcpy(&(pwlan->network), pnetwork, pnetwork->Length);
++ //pwlan->fixed = _TRUE;
++
++ //rtw_list_insert_tail(&(pwlan->list), &pmlmepriv->scanned_queue.queue);
++
++ // copy pdev_network information to pmlmepriv->cur_network
++ _rtw_memcpy(&tgt_network->network, pnetwork, (get_WLAN_BSSID_EX_sz(pnetwork)));
++
++ // reset DSConfig
++ //tgt_network->network.Configuration.DSConfig = (u32)rtw_ch2freq(pnetwork->Configuration.DSConfig);
++
++ _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING);
++
++#if 0
++ if((pmlmepriv->fw_state) & WIFI_AP_STATE)
++ {
++ psta = rtw_alloc_stainfo(&padapter->stapriv, pnetwork->MacAddress);
++
++ if (psta == NULL) { // for AP Mode & Adhoc Master Mode
++ RT_TRACE(_module_rtl871x_cmd_c_,_drv_err_,("\nCan't alloc sta_info when createbss_cmd_callback\n"));
++ goto createbss_cmd_fail ;
++ }
++
++ rtw_indicate_connect( padapter);
++ }
++ else {
++
++ //rtw_indicate_disconnect(dev);
++ }
++#endif
++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++ // we will set _FW_LINKED when there is one more sat to join us (rtw_stassoc_event_callback)
++
++ }
++
++createbss_cmd_fail:
++
++ _exit_critical_bh(&pmlmepriv->lock, &irqL);
++
++ rtw_free_cmd_obj(pcmd);
++
++_func_exit_;
++
++}
++
++
++
++void rtw_setstaKey_cmdrsp_callback(_adapter* padapter , struct cmd_obj *pcmd)
++{
++
++ struct sta_priv * pstapriv = &padapter->stapriv;
++ struct set_stakey_rsp* psetstakey_rsp = (struct set_stakey_rsp*) (pcmd->rsp);
++ struct sta_info* psta = rtw_get_stainfo(pstapriv, psetstakey_rsp->addr);
++
++_func_enter_;
++
++ if(psta==NULL)
++ {
++ RT_TRACE(_module_rtl871x_cmd_c_,_drv_err_,("\nERROR: rtw_setstaKey_cmdrsp_callback => can't get sta_info \n\n"));
++ goto exit;
++ }
++
++ //psta->aid = psta->mac_id = psetstakey_rsp->keyid; //CAM_ID(CAM_ENTRY)
++
++exit:
++
++ rtw_free_cmd_obj(pcmd);
++
++_func_exit_;
++
++}
++void rtw_setassocsta_cmdrsp_callback(_adapter* padapter, struct cmd_obj *pcmd)
++{
++ _irqL irqL;
++ struct sta_priv * pstapriv = &padapter->stapriv;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct set_assocsta_parm* passocsta_parm = (struct set_assocsta_parm*)(pcmd->parmbuf);
++ struct set_assocsta_rsp* passocsta_rsp = (struct set_assocsta_rsp*) (pcmd->rsp);
++ struct sta_info* psta = rtw_get_stainfo(pstapriv, passocsta_parm->addr);
++
++_func_enter_;
++
++ if(psta==NULL)
++ {
++ RT_TRACE(_module_rtl871x_cmd_c_,_drv_err_,("\nERROR: setassocsta_cmdrsp_callbac => can't get sta_info \n\n"));
++ goto exit;
++ }
++
++ psta->aid = psta->mac_id = passocsta_rsp->cam_id;
++
++ _enter_critical_bh(&pmlmepriv->lock, &irqL);
++
++ if ((check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE) && (check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == _TRUE))
++ _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING);
++
++ set_fwstate(pmlmepriv, _FW_LINKED);
++ _exit_critical_bh(&pmlmepriv->lock, &irqL);
++
++exit:
++ rtw_free_cmd_obj(pcmd);
++
++_func_exit_;
++}
++
++void rtw_getrttbl_cmd_cmdrsp_callback(_adapter* padapter, struct cmd_obj *pcmd);
++void rtw_getrttbl_cmd_cmdrsp_callback(_adapter* padapter, struct cmd_obj *pcmd)
++{
++_func_enter_;
++
++ rtw_free_cmd_obj(pcmd);
++#ifdef CONFIG_MP_INCLUDED
++ padapter->mppriv.workparam.bcompleted=_TRUE;
++#endif
++
++_func_exit_;
++
++}
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/core/rtw_debug.c linux-xbian-rpi/drivers/net/wireless/rtl8192cu/core/rtw_debug.c
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/core/rtw_debug.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/core/rtw_debug.c 2015-07-28 01:20:58.301668422 +0200
+@@ -0,0 +1,1336 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#define _RTW_DEBUG_C_
++
++
++#include <rtw_debug.h>
++#include <../hal/dm.h>
++
++//#ifdef CONFIG_DEBUG_RTL871X
++
++ u32 GlobalDebugLevel = _drv_err_;
++
++ u64 GlobalDebugComponents = \
++ _module_rtl871x_xmit_c_ |
++ _module_xmit_osdep_c_ |
++ _module_rtl871x_recv_c_ |
++ _module_recv_osdep_c_ |
++ _module_rtl871x_mlme_c_ |
++ _module_mlme_osdep_c_ |
++ _module_rtl871x_sta_mgt_c_ |
++ _module_rtl871x_cmd_c_ |
++ _module_cmd_osdep_c_ |
++ _module_rtl871x_io_c_ |
++ _module_io_osdep_c_ |
++ _module_os_intfs_c_|
++ _module_rtl871x_security_c_|
++ _module_rtl871x_eeprom_c_|
++ _module_hal_init_c_|
++ _module_hci_hal_init_c_|
++ _module_rtl871x_ioctl_c_|
++ _module_rtl871x_ioctl_set_c_|
++ _module_rtl871x_ioctl_query_c_|
++ _module_rtl871x_pwrctrl_c_|
++ _module_hci_intfs_c_|
++ _module_hci_ops_c_|
++ _module_hci_ops_os_c_|
++ _module_rtl871x_ioctl_os_c|
++ _module_rtl8712_cmd_c_|
++ _module_hal_xmit_c_|
++ _module_rtl8712_recv_c_ |
++ _module_mp_ |
++ _module_efuse_;
++
++//#endif
++
++#ifdef CONFIG_PROC_DEBUG
++#include <rtw_version.h>
++
++int proc_get_drv_version(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data)
++{
++ struct net_device *dev = data;
++
++ int len = 0;
++
++ len += snprintf(page + len, count - len, "%s\n", DRIVERVERSION);
++
++ *eof = 1;
++ return len;
++}
++
++int proc_get_log_level(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data)
++{
++ struct net_device *dev = data;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++
++ int len = 0;
++
++ len += snprintf(page + len, count - len,
++ "log_level:%d\n",
++ GlobalDebugLevel
++ );
++
++ *eof = 1;
++ return len;
++}
++
++int proc_set_log_level(struct file *file, const char *buffer,
++ unsigned long count, void *data)
++{
++ struct net_device *dev = (struct net_device *)data;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ char tmp[32];
++ u32 is_signal_dbg;
++
++ if (count < 1)
++ return -EFAULT;
++
++ if (buffer && !copy_from_user(tmp, buffer, sizeof(tmp))) {
++
++ int num = sscanf(tmp, "%d ", &is_signal_dbg);
++
++ if( is_signal_dbg >= 0 && is_signal_dbg < 10 )
++ {
++ GlobalDebugLevel= is_signal_dbg;
++ printk("%d\n", GlobalDebugLevel);
++ }
++ }
++
++ return count;
++
++}
++
++#ifdef DBG_MEM_ALLOC
++int proc_get_mstat(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data)
++{
++ int len = 0;
++
++ len += _rtw_mstat_dump(page+len, count-len);
++ *eof = 1;
++
++ return len;
++}
++#endif /* DBG_MEM_ALLOC */
++
++int proc_get_write_reg(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data)
++{
++ *eof = 1;
++ return 0;
++}
++
++int proc_set_write_reg(struct file *file, const char *buffer,
++ unsigned long count, void *data)
++{
++ struct net_device *dev = (struct net_device *)data;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ char tmp[32];
++ u32 addr, val, len;
++
++ if (count < 3)
++ {
++ DBG_871X("argument size is less than 3\n");
++ return -EFAULT;
++ }
++
++ if (buffer && !copy_from_user(tmp, buffer, sizeof(tmp))) {
++
++ int num = sscanf(tmp, "%x %x %x", &addr, &val, &len);
++
++ if (num != 3) {
++ DBG_871X("invalid write_reg parameter!\n");
++ return count;
++ }
++
++ switch(len)
++ {
++ case 1:
++ rtw_write8(padapter, addr, (u8)val);
++ break;
++ case 2:
++ rtw_write16(padapter, addr, (u16)val);
++ break;
++ case 4:
++ rtw_write32(padapter, addr, val);
++ break;
++ default:
++ DBG_871X("error write length=%d", len);
++ break;
++ }
++
++ }
++
++ return count;
++
++}
++
++static u32 proc_get_read_addr=0xeeeeeeee;
++static u32 proc_get_read_len=0x4;
++
++int proc_get_read_reg(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data)
++{
++ struct net_device *dev = data;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++
++ int len = 0;
++
++ if(proc_get_read_addr==0xeeeeeeee)
++ {
++ *eof = 1;
++ return len;
++ }
++
++ switch(proc_get_read_len)
++ {
++ case 1:
++ len += snprintf(page + len, count - len, "rtw_read8(0x%x)=0x%x\n", proc_get_read_addr, rtw_read8(padapter, proc_get_read_addr));
++ break;
++ case 2:
++ len += snprintf(page + len, count - len, "rtw_read16(0x%x)=0x%x\n", proc_get_read_addr, rtw_read16(padapter, proc_get_read_addr));
++ break;
++ case 4:
++ len += snprintf(page + len, count - len, "rtw_read32(0x%x)=0x%x\n", proc_get_read_addr, rtw_read32(padapter, proc_get_read_addr));
++ break;
++ default:
++ len += snprintf(page + len, count - len, "error read length=%d\n", proc_get_read_len);
++ break;
++ }
++
++ *eof = 1;
++ return len;
++
++}
++
++int proc_set_read_reg(struct file *file, const char *buffer,
++ unsigned long count, void *data)
++{
++ char tmp[16];
++ u32 addr, len;
++
++ if (count < 2)
++ {
++ DBG_871X("argument size is less than 2\n");
++ return -EFAULT;
++ }
++
++ if (buffer && !copy_from_user(tmp, buffer, sizeof(tmp))) {
++
++ int num = sscanf(tmp, "%x %x", &addr, &len);
++
++ if (num != 2) {
++ DBG_871X("invalid read_reg parameter!\n");
++ return count;
++ }
++
++ proc_get_read_addr = addr;
++
++ proc_get_read_len = len;
++ }
++
++ return count;
++
++}
++
++int proc_get_fwstate(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data)
++{
++ struct net_device *dev = data;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++
++ int len = 0;
++
++ len += snprintf(page + len, count - len, "fwstate=0x%x\n", get_fwstate(pmlmepriv));
++
++ *eof = 1;
++ return len;
++}
++
++int proc_get_sec_info(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data)
++{
++ struct net_device *dev = data;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct security_priv *psecuritypriv = &padapter->securitypriv;
++
++ int len = 0;
++
++ len += snprintf(page + len, count - len, "auth_alg=0x%x, enc_alg=0x%x, auth_type=0x%x, enc_type=0x%x\n",
++ psecuritypriv->dot11AuthAlgrthm, psecuritypriv->dot11PrivacyAlgrthm,
++ psecuritypriv->ndisauthtype, psecuritypriv->ndisencryptstatus);
++
++ *eof = 1;
++ return len;
++}
++
++int proc_get_mlmext_state(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data)
++{
++ struct net_device *dev = data;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++
++ int len = 0;
++
++ len += snprintf(page + len, count - len, "pmlmeinfo->state=0x%x\n", pmlmeinfo->state);
++
++ *eof = 1;
++ return len;
++}
++
++int proc_get_qos_option(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data)
++{
++ struct net_device *dev = data;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++
++ int len = 0;
++
++ len += snprintf(page + len, count - len, "qos_option=%d\n", pmlmepriv->qospriv.qos_option);
++
++ *eof = 1;
++ return len;
++
++}
++
++int proc_get_ht_option(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data)
++{
++ struct net_device *dev = data;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++
++ int len = 0;
++
++ len += snprintf(page + len, count - len, "ht_option=%d\n", pmlmepriv->htpriv.ht_option);
++
++ *eof = 1;
++ return len;
++}
++
++int proc_get_rf_info(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data)
++{
++ struct net_device *dev = data;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ int len = 0;
++
++ len += snprintf(page + len, count - len, "cur_ch=%d, cur_bw=%d, cur_ch_offet=%d\n"
++ "oper_ch=%d, oper_bw=%d, oper_ch_offet=%d\n",
++ pmlmeext->cur_channel, pmlmeext->cur_bwmode, pmlmeext->cur_ch_offset,
++ rtw_get_oper_ch(padapter), rtw_get_oper_bw(padapter), rtw_get_oper_choffset(padapter));
++ *eof = 1;
++
++ return len;
++}
++
++int proc_get_ap_info(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data)
++{
++ struct sta_info *psta;
++ struct net_device *dev = data;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct wlan_network *cur_network = &(pmlmepriv->cur_network);
++ struct sta_priv *pstapriv = &padapter->stapriv;
++ int len = 0;
++
++ psta = rtw_get_stainfo(pstapriv, cur_network->network.MacAddress);
++ if(psta)
++ {
++ int i;
++ struct recv_reorder_ctrl *preorder_ctrl;
++
++ len += snprintf(page + len, count - len, "SSID=%s\n", cur_network->network.Ssid.Ssid);
++ len += snprintf(page + len, count - len, "sta's macaddr:" MAC_FMT "\n", MAC_ARG(psta->hwaddr));
++ len += snprintf(page + len, count - len, "cur_channel=%d, cur_bwmode=%d, cur_ch_offset=%d\n", pmlmeext->cur_channel, pmlmeext->cur_bwmode, pmlmeext->cur_ch_offset);
++ len += snprintf(page + len, count - len, "rtsen=%d, cts2slef=%d\n", psta->rtsen, psta->cts2self);
++ len += snprintf(page + len, count - len, "qos_en=%d, ht_en=%d, init_rate=%d\n", psta->qos_option, psta->htpriv.ht_option, psta->init_rate);
++ len += snprintf(page + len, count - len, "state=0x%x, aid=%d, macid=%d, raid=%d\n", psta->state, psta->aid, psta->mac_id, psta->raid);
++ len += snprintf(page + len, count - len, "bwmode=%d, ch_offset=%d, sgi=%d\n", psta->htpriv.bwmode, psta->htpriv.ch_offset, psta->htpriv.sgi);
++ len += snprintf(page + len, count - len, "ampdu_enable = %d\n", psta->htpriv.ampdu_enable);
++ len += snprintf(page + len, count - len, "agg_enable_bitmap=%x, candidate_tid_bitmap=%x\n", psta->htpriv.agg_enable_bitmap, psta->htpriv.candidate_tid_bitmap);
++
++ for(i=0;i<16;i++)
++ {
++ preorder_ctrl = &psta->recvreorder_ctrl[i];
++ if(preorder_ctrl->enable)
++ {
++ len += snprintf(page + len, count - len, "tid=%d, indicate_seq=%d\n", i, preorder_ctrl->indicate_seq);
++ }
++ }
++
++ }
++ else
++ {
++ len += snprintf(page + len, count - len, "can't get sta's macaddr, cur_network's macaddr:" MAC_FMT "\n", MAC_ARG(cur_network->network.MacAddress));
++ }
++
++ *eof = 1;
++ return len;
++
++}
++
++int proc_get_adapter_state(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data)
++{
++ struct net_device *dev = data;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ int len = 0;
++
++ len += snprintf(page + len, count - len, "bSurpriseRemoved=%d, bDriverStopped=%d\n",
++ padapter->bSurpriseRemoved, padapter->bDriverStopped);
++
++ *eof = 1;
++ return len;
++
++}
++
++int proc_get_trx_info(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data)
++{
++ int i;
++ struct net_device *dev = data;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++ struct recv_priv *precvpriv = &padapter->recvpriv;
++ struct dvobj_priv *pdvobj = adapter_to_dvobj(padapter);
++ struct hw_xmit *phwxmit;
++ int len = 0;
++
++ len += snprintf(page + len, count - len, "free_xmitbuf_cnt=%d, free_xmitframe_cnt=%d"
++ ", free_ext_xmitbuf_cnt=%d, free_xframe_ext_cnt=%d"
++ ", free_recvframe_cnt=%d\n",
++ pxmitpriv->free_xmitbuf_cnt, pxmitpriv->free_xmitframe_cnt,
++ pxmitpriv->free_xmit_extbuf_cnt, pxmitpriv->free_xframe_ext_cnt,
++ precvpriv->free_recvframe_cnt);
++#ifdef CONFIG_USB_HCI
++ len += snprintf(page + len, count - len, "rx_urb_pending_cnt=%d\n", precvpriv->rx_pending_cnt);
++#endif
++
++ len += snprintf(page + len, count - len, "recvbuf_skb_alloc_fail_cnt=%d\n", precvpriv->recvbuf_skb_alloc_fail_cnt);
++ len += snprintf(page + len, count - len, "recvbuf_null_cnt=%d\n", precvpriv->recvbuf_null_cnt);
++ len += snprintf(page + len, count - len, "read_port_complete_EINPROGRESS_cnt=%d\n", precvpriv->read_port_complete_EINPROGRESS_cnt);
++ len += snprintf(page + len, count - len, "read_port_complete_other_urb_err_cnt=%d\n", precvpriv->read_port_complete_other_urb_err_cnt);
++ len += snprintf(page + len, count - len, "hw_init_completed=%d\n", padapter->hw_init_completed);
++#ifdef CONFIG_USB_HCI
++ len += snprintf(page + len, count - len, "continual_urb_error=%d\n", atomic_read(&pdvobj->continual_urb_error));
++#endif
++
++ for(i = 0; i < 4; i++)
++ {
++ phwxmit = pxmitpriv->hwxmits + i;
++ len += snprintf(page + len, count - len, "%d, hwq.accnt=%d\n", i, phwxmit->accnt);
++ }
++
++ *eof = 1;
++ return len;
++
++}
++
++
++
++int proc_get_mac_reg_dump1(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data)
++{
++ struct net_device *dev = data;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ int len = 0;
++ int i,j=1;
++
++ len += snprintf(page + len, count - len, "\n======= MAC REG =======\n");
++
++ for(i=0x0;i<0x300;i+=4)
++ {
++ if(j%4==1) len += snprintf(page + len, count - len,"0x%02x",i);
++ len += snprintf(page + len, count - len," 0x%08x ",rtw_read32(padapter,i));
++ if((j++)%4 == 0) len += snprintf(page + len, count - len,"\n");
++ }
++
++ *eof = 1;
++ return len;
++
++}
++
++int proc_get_mac_reg_dump2(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data)
++{
++ struct net_device *dev = data;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ int len = 0;
++ int i,j=1;
++
++ len += snprintf(page + len, count - len, "\n======= MAC REG =======\n");
++ memset(page, 0, count);
++ for(i=0x300;i<0x600;i+=4)
++ {
++ if(j%4==1) len += snprintf(page + len, count - len,"0x%02x",i);
++ len += snprintf(page + len, count - len," 0x%08x ",rtw_read32(padapter,i));
++ if((j++)%4 == 0) len += snprintf(page + len, count - len,"\n");
++ }
++
++ *eof = 1;
++ return len;
++
++}
++
++int proc_get_mac_reg_dump3(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data)
++{
++ struct net_device *dev = data;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ int len = 0;
++ int i,j=1;
++
++ len += snprintf(page + len, count - len, "\n======= MAC REG =======\n");
++
++ for(i=0x600;i<0x800;i+=4)
++ {
++ if(j%4==1) len += snprintf(page + len, count - len,"0x%02x",i);
++ len += snprintf(page + len, count - len," 0x%08x ",rtw_read32(padapter,i));
++ if((j++)%4 == 0) len += snprintf(page + len, count - len,"\n");
++ }
++
++ *eof = 1;
++ return len;
++
++}
++
++int proc_get_bb_reg_dump1(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data)
++{
++ struct net_device *dev = data;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ int len = 0;
++ int i,j=1;
++
++ len += snprintf(page + len, count - len, "\n======= BB REG =======\n");
++ for(i=0x800;i<0xB00;i+=4)
++ {
++ if(j%4==1) len += snprintf(page + len, count - len,"0x%02x",i);
++ len += snprintf(page + len, count - len," 0x%08x ",rtw_read32(padapter,i));
++ if((j++)%4 == 0) len += snprintf(page + len, count - len,"\n");
++ }
++ *eof = 1;
++ return len;
++}
++
++int proc_get_bb_reg_dump2(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data)
++{
++ struct net_device *dev = data;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ int len = 0;
++ int i,j=1;
++
++ len += snprintf(page + len, count - len, "\n======= BB REG =======\n");
++ for(i=0xB00;i<0xE00;i+=4)
++ {
++ if(j%4==1) len += snprintf(page + len, count - len,"0x%02x",i);
++ len += snprintf(page + len, count - len," 0x%08x ",rtw_read32(padapter,i));
++ if((j++)%4 == 0) len += snprintf(page + len, count - len,"\n");
++ }
++ *eof = 1;
++ return len;
++}
++
++int proc_get_bb_reg_dump3(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data)
++{
++ struct net_device *dev = data;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ int len = 0;
++ int i,j=1;
++
++ len += snprintf(page + len, count - len, "\n======= BB REG =======\n");
++ for(i=0xE00;i<0x1000;i+=4)
++ {
++ if(j%4==1) len += snprintf(page + len, count - len,"0x%02x",i);
++ len += snprintf(page + len, count - len," 0x%08x ",rtw_read32(padapter,i));
++ if((j++)%4 == 0) len += snprintf(page + len, count - len,"\n");
++ }
++ *eof = 1;
++ return len;
++}
++
++int proc_get_rf_reg_dump1(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data)
++{
++ struct net_device *dev = data;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ int len = 0;
++ int i,j=1,path;
++ u32 value;
++
++ len += snprintf(page + len, count - len, "\n======= RF REG =======\n");
++ path = 1;
++ len += snprintf(page + len, count - len, "\nRF_Path(%x)\n",path);
++ for(i=0;i<0xC0;i++)
++ {
++ //value = PHY_QueryRFReg(padapter, (RF90_RADIO_PATH_E)path,i, bMaskDWord);
++ value =rtw_hal_read_rfreg(padapter, path, i, 0xffffffff);
++ if(j%4==1) len += snprintf(page + len, count - len, "0x%02x ",i);
++ len += snprintf(page + len, count - len, " 0x%08x ",value);
++ if((j++)%4==0) len += snprintf(page + len, count - len, "\n");
++ }
++
++ *eof = 1;
++ return len;
++}
++
++
++int proc_get_rf_reg_dump2(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data)
++{
++ struct net_device *dev = data;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ int len = 0;
++ int i,j=1,path;
++ u32 value;
++
++ len += snprintf(page + len, count - len, "\n======= RF REG =======\n");
++ path = 1;
++ len += snprintf(page + len, count - len, "\nRF_Path(%x)\n",path);
++ for(i=0xC0;i<0x100;i++)
++ {
++ //value = PHY_QueryRFReg(padapter, (RF90_RADIO_PATH_E)path,i, bMaskDWord);
++ value =rtw_hal_read_rfreg(padapter, path, i, 0xffffffff);
++ if(j%4==1) len += snprintf(page + len, count - len, "0x%02x ",i);
++ len += snprintf(page + len, count - len, " 0x%08x ",value);
++ if((j++)%4==0) len += snprintf(page + len, count - len, "\n");
++ }
++ *eof = 1;
++ return len;
++}
++
++
++int proc_get_rf_reg_dump3(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data)
++{
++ struct net_device *dev = data;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ int len = 0;
++ int i,j=1,path;
++ u32 value;
++
++ len += snprintf(page + len, count - len, "\n======= RF REG =======\n");
++ path = 2;
++ len += snprintf(page + len, count - len, "\nRF_Path(%x)\n",path);
++ for(i=0;i<0xC0;i++)
++ {
++ //value = PHY_QueryRFReg(padapter, (RF90_RADIO_PATH_E)path,i, bMaskDWord);
++ value =rtw_hal_read_rfreg(padapter, path, i, 0xffffffff);
++ if(j%4==1) len += snprintf(page + len, count - len, "0x%02x ",i);
++ len += snprintf(page + len, count - len, " 0x%08x ",value);
++ if((j++)%4==0) len += snprintf(page + len, count - len, "\n");
++ }
++
++ *eof = 1;
++ return len;
++}
++
++
++int proc_get_rf_reg_dump4(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data)
++{
++ struct net_device *dev = data;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ int len = 0;
++ int i,j=1,path;
++ u32 value;
++
++ len += snprintf(page + len, count - len, "\n======= RF REG =======\n");
++ path = 2;
++ len += snprintf(page + len, count - len, "\nRF_Path(%x)\n",path);
++ for(i=0xC0;i<0x100;i++)
++ {
++ //value = PHY_QueryRFReg(padapter, (RF90_RADIO_PATH_E)path,i, bMaskDWord);
++ value =rtw_hal_read_rfreg(padapter, path, i, 0xffffffff);
++ if(j%4==1) len += snprintf(page + len, count - len, "0x%02x ",i);
++ len += snprintf(page + len, count - len, " 0x%08x ",value);
++ if((j++)%4==0) len += snprintf(page + len, count - len, "\n");
++ }
++ *eof = 1;
++ return len;
++}
++
++
++
++int proc_get_rx_signal(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data)
++{
++ struct net_device *dev = data;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++
++ int len = 0;
++
++ len += snprintf(page + len, count - len,
++ "rssi:%d\n"
++ "rxpwdb:%d\n"
++ "signal_strength:%u\n"
++ "signal_qual:%u\n"
++ "noise:%u\n",
++ padapter->recvpriv.rssi,
++ padapter->recvpriv.rxpwdb,
++ padapter->recvpriv.signal_strength,
++ padapter->recvpriv.signal_qual,
++ padapter->recvpriv.noise
++ );
++
++ *eof = 1;
++ return len;
++}
++
++int proc_set_rx_signal(struct file *file, const char *buffer,
++ unsigned long count, void *data)
++{
++ struct net_device *dev = (struct net_device *)data;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ char tmp[32];
++ u32 is_signal_dbg, signal_strength;
++
++ if (count < 1)
++ return -EFAULT;
++
++ if (buffer && !copy_from_user(tmp, buffer, sizeof(tmp))) {
++
++ int num = sscanf(tmp, "%u %u", &is_signal_dbg, &signal_strength);
++
++ is_signal_dbg = is_signal_dbg==0?0:1;
++
++ if(is_signal_dbg && num!=2)
++ return count;
++
++ signal_strength = signal_strength>100?100:signal_strength;
++ signal_strength = signal_strength<0?0:signal_strength;
++
++ padapter->recvpriv.is_signal_dbg = is_signal_dbg;
++ padapter->recvpriv.signal_strength_dbg=signal_strength;
++
++ if(is_signal_dbg)
++ DBG_871X("set %s %u\n", "DBG_SIGNAL_STRENGTH", signal_strength);
++ else
++ DBG_871X("set %s\n", "HW_SIGNAL_STRENGTH");
++
++ }
++
++ return count;
++
++}
++
++int proc_get_ht_enable(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data)
++{
++ struct net_device *dev = data;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct registry_priv *pregpriv = &padapter->registrypriv;
++
++ int len = 0;
++
++ if(pregpriv)
++ len += snprintf(page + len, count - len,
++ "%d\n",
++ pregpriv->ht_enable
++ );
++
++ *eof = 1;
++ return len;
++}
++
++int proc_set_ht_enable(struct file *file, const char *buffer,
++ unsigned long count, void *data)
++{
++ struct net_device *dev = (struct net_device *)data;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct registry_priv *pregpriv = &padapter->registrypriv;
++ char tmp[32];
++ u32 mode;
++
++ if (count < 1)
++ return -EFAULT;
++
++ if (buffer && !copy_from_user(tmp, buffer, sizeof(tmp))) {
++
++ int num = sscanf(tmp, "%d ", &mode);
++
++ if( pregpriv && mode >= 0 && mode < 2 )
++ {
++ pregpriv->ht_enable= mode;
++ printk("ht_enable=%d\n", pregpriv->ht_enable);
++ }
++ }
++
++ return count;
++
++}
++
++
++int proc_get_cbw40_enable(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data)
++{
++ struct net_device *dev = data;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct registry_priv *pregpriv = &padapter->registrypriv;
++
++ int len = 0;
++
++ if(pregpriv)
++ len += snprintf(page + len, count - len,
++ "%d\n",
++ pregpriv->cbw40_enable
++ );
++
++ *eof = 1;
++ return len;
++}
++
++int proc_set_cbw40_enable(struct file *file, const char *buffer,
++ unsigned long count, void *data)
++{
++ struct net_device *dev = (struct net_device *)data;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct registry_priv *pregpriv = &padapter->registrypriv;
++ char tmp[32];
++ u32 mode;
++
++ if (count < 1)
++ return -EFAULT;
++
++ if (buffer && !copy_from_user(tmp, buffer, sizeof(tmp))) {
++
++ int num = sscanf(tmp, "%d ", &mode);
++
++ if( pregpriv && mode >= 0 && mode < 2 )
++ {
++ pregpriv->cbw40_enable= mode;
++ printk("cbw40_enable=%d\n", mode);
++ }
++ }
++
++ return count;
++
++}
++
++int proc_get_ampdu_enable(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data)
++{
++ struct net_device *dev = data;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct registry_priv *pregpriv = &padapter->registrypriv;
++
++ int len = 0;
++
++ if(pregpriv)
++ len += snprintf(page + len, count - len,
++ "%d\n",
++ pregpriv->ampdu_enable
++ );
++
++ *eof = 1;
++ return len;
++}
++
++int proc_set_ampdu_enable(struct file *file, const char *buffer,
++ unsigned long count, void *data)
++{
++ struct net_device *dev = (struct net_device *)data;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct registry_priv *pregpriv = &padapter->registrypriv;
++ char tmp[32];
++ u32 mode;
++
++ if (count < 1)
++ return -EFAULT;
++
++ if (buffer && !copy_from_user(tmp, buffer, sizeof(tmp))) {
++
++ int num = sscanf(tmp, "%d ", &mode);
++
++ if( pregpriv && mode >= 0 && mode < 3 )
++ {
++ pregpriv->ampdu_enable= mode;
++ printk("ampdu_enable=%d\n", mode);
++ }
++ }
++
++ return count;
++
++}
++
++
++int proc_get_two_path_rssi(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data)
++{
++ struct net_device *dev = data;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++
++ int len = 0;
++
++ if(padapter)
++ len += snprintf(page + len, count - len,
++ "%d %d\n",
++ padapter->recvpriv.RxRssi[0],
++ padapter->recvpriv.RxRssi[1]
++ );
++
++ *eof = 1;
++ return len;
++}
++
++int proc_get_rx_stbc(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data)
++{
++ struct net_device *dev = data;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct registry_priv *pregpriv = &padapter->registrypriv;
++
++ int len = 0;
++
++ if(pregpriv)
++ len += snprintf(page + len, count - len,
++ "%d\n",
++ pregpriv->rx_stbc
++ );
++
++ *eof = 1;
++ return len;
++}
++
++int proc_set_rx_stbc(struct file *file, const char *buffer,
++ unsigned long count, void *data)
++{
++ struct net_device *dev = (struct net_device *)data;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct registry_priv *pregpriv = &padapter->registrypriv;
++ char tmp[32];
++ u32 mode;
++
++ if (count < 1)
++ return -EFAULT;
++
++ if (buffer && !copy_from_user(tmp, buffer, sizeof(tmp))) {
++
++ int num = sscanf(tmp, "%d ", &mode);
++
++ if( pregpriv && (mode == 0 || mode == 1|| mode == 2|| mode == 3))
++ {
++ pregpriv->rx_stbc= mode;
++ printk("rx_stbc=%d\n", mode);
++ }
++ }
++
++ return count;
++
++}
++
++int proc_get_vid(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data)
++{
++ struct net_device *dev = data;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ u16 VID=0;
++ int len = 0;
++
++ rtw_hal_get_hwreg(padapter, HW_VAR_VID, (u8 *)&VID);
++ len += snprintf(page + len, count - len,
++ "%04x\n",
++ VID
++ );
++
++ *eof = 1;
++ return len;
++}
++
++int proc_get_pid(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data)
++{
++ struct net_device *dev = data;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ u16 PID=0;
++ int len = 0;
++
++ rtw_hal_get_hwreg(padapter, HW_VAR_PID, (u8 *)&PID);
++ len += snprintf(page + len, count - len,
++ "%04x\n",
++ PID
++ );
++
++ *eof = 1;
++ return len;
++}
++
++int proc_get_rssi_disp(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data)
++{
++ *eof = 1;
++ return 0;
++}
++
++int proc_set_rssi_disp(struct file *file, const char *buffer,
++ unsigned long count, void *data)
++{
++ struct net_device *dev = (struct net_device *)data;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ char tmp[32];
++ u32 enable=0;
++
++ if (count < 1)
++ {
++ DBG_8192C("argument size is less than 1\n");
++ return -EFAULT;
++ }
++
++ if (buffer && !copy_from_user(tmp, buffer, sizeof(tmp))) {
++
++ int num = sscanf(tmp, "%x", &enable);
++
++ if (num != 1) {
++ DBG_8192C("invalid set_rssi_disp parameter!\n");
++ return count;
++ }
++
++ if(enable)
++ {
++ DBG_8192C("Turn On Rx RSSI Display Function\n");
++ padapter->bRxRSSIDisplay = enable ;
++ }
++ else
++ {
++ DBG_8192C("Turn Off Rx RSSI Display Function\n");
++ padapter->bRxRSSIDisplay = 0 ;
++ }
++
++ }
++
++ return count;
++
++}
++
++
++#ifdef CONFIG_AP_MODE
++
++int proc_get_all_sta_info(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data)
++{
++ _irqL irqL;
++ struct sta_info *psta;
++ struct net_device *dev = data;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct sta_priv *pstapriv = &padapter->stapriv;
++ int i, j;
++ _list *plist, *phead;
++ struct recv_reorder_ctrl *preorder_ctrl;
++ int len = 0;
++
++
++ len += snprintf(page + len, count - len, "sta_dz_bitmap=0x%x, tim_bitmap=0x%x\n", pstapriv->sta_dz_bitmap, pstapriv->tim_bitmap);
++
++ _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
++
++ for(i=0; i< NUM_STA; i++)
++ {
++ phead = &(pstapriv->sta_hash[i]);
++ plist = get_next(phead);
++
++ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE)
++ {
++ psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
++
++ plist = get_next(plist);
++
++ //if(extra_arg == psta->aid)
++ {
++ len += snprintf(page + len, count - len, "sta's macaddr:" MAC_FMT "\n", MAC_ARG(psta->hwaddr));
++ len += snprintf(page + len, count - len, "rtsen=%d, cts2slef=%d\n", psta->rtsen, psta->cts2self);
++ len += snprintf(page + len, count - len, "qos_en=%d, ht_en=%d, init_rate=%d\n", psta->qos_option, psta->htpriv.ht_option, psta->init_rate);
++ len += snprintf(page + len, count - len, "state=0x%x, aid=%d, macid=%d, raid=%d\n", psta->state, psta->aid, psta->mac_id, psta->raid);
++ len += snprintf(page + len, count - len, "bwmode=%d, ch_offset=%d, sgi=%d\n", psta->htpriv.bwmode, psta->htpriv.ch_offset, psta->htpriv.sgi);
++ len += snprintf(page + len, count - len, "ampdu_enable = %d\n", psta->htpriv.ampdu_enable);
++ len += snprintf(page + len, count - len, "agg_enable_bitmap=%x, candidate_tid_bitmap=%x\n", psta->htpriv.agg_enable_bitmap, psta->htpriv.candidate_tid_bitmap);
++ len += snprintf(page + len, count - len, "sleepq_len=%d\n", psta->sleepq_len);
++ len += snprintf(page + len, count - len, "capability=0x%x\n", psta->capability);
++ len += snprintf(page + len, count - len, "flags=0x%x\n", psta->flags);
++ len += snprintf(page + len, count - len, "wpa_psk=0x%x\n", psta->wpa_psk);
++ len += snprintf(page + len, count - len, "wpa2_group_cipher=0x%x\n", psta->wpa2_group_cipher);
++ len += snprintf(page + len, count - len, "wpa2_pairwise_cipher=0x%x\n", psta->wpa2_pairwise_cipher);
++ len += snprintf(page + len, count - len, "qos_info=0x%x\n", psta->qos_info);
++ len += snprintf(page + len, count - len, "dot118021XPrivacy=0x%x\n", psta->dot118021XPrivacy);
++
++ for(j=0;j<16;j++)
++ {
++ preorder_ctrl = &psta->recvreorder_ctrl[j];
++ if(preorder_ctrl->enable)
++ {
++ len += snprintf(page + len, count - len, "tid=%d, indicate_seq=%d\n", j, preorder_ctrl->indicate_seq);
++ }
++ }
++
++ }
++
++ }
++
++ }
++
++ _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
++
++ *eof = 1;
++ return len;
++
++}
++
++#endif
++
++#ifdef DBG_MEMORY_LEAK
++#include <asm/atomic.h>
++extern atomic_t _malloc_cnt;;
++extern atomic_t _malloc_size;;
++
++int proc_get_malloc_cnt(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data)
++{
++
++ int len = 0;
++
++ len += snprintf(page + len, count - len, "_malloc_cnt=%d\n", atomic_read(&_malloc_cnt));
++ len += snprintf(page + len, count - len, "_malloc_size=%d\n", atomic_read(&_malloc_size));
++
++ *eof = 1;
++ return len;
++}
++#endif /* DBG_MEMORY_LEAK */
++
++#ifdef CONFIG_FIND_BEST_CHANNEL
++int proc_get_best_channel(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data)
++{
++ struct net_device *dev = data;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ int len = 0;
++ u32 i, best_channel_24G = 1, best_channel_5G = 36, index_24G = 0, index_5G = 0;
++
++ for (i=0; pmlmeext->channel_set[i].ChannelNum !=0; i++) {
++ if ( pmlmeext->channel_set[i].ChannelNum == 1)
++ index_24G = i;
++ if ( pmlmeext->channel_set[i].ChannelNum == 36)
++ index_5G = i;
++ }
++
++ for (i=0; pmlmeext->channel_set[i].ChannelNum !=0; i++) {
++ // 2.4G
++ if ( pmlmeext->channel_set[i].ChannelNum == 6 ) {
++ if ( pmlmeext->channel_set[i].rx_count < pmlmeext->channel_set[index_24G].rx_count ) {
++ index_24G = i;
++ best_channel_24G = pmlmeext->channel_set[i].ChannelNum;
++ }
++ }
++
++ // 5G
++ if ( pmlmeext->channel_set[i].ChannelNum >= 36
++ && pmlmeext->channel_set[i].ChannelNum < 140 ) {
++ // Find primary channel
++ if ( (( pmlmeext->channel_set[i].ChannelNum - 36) % 8 == 0)
++ && (pmlmeext->channel_set[i].rx_count < pmlmeext->channel_set[index_5G].rx_count) ) {
++ index_5G = i;
++ best_channel_5G = pmlmeext->channel_set[i].ChannelNum;
++ }
++ }
++
++ if ( pmlmeext->channel_set[i].ChannelNum >= 149
++ && pmlmeext->channel_set[i].ChannelNum < 165) {
++ // find primary channel
++ if ( (( pmlmeext->channel_set[i].ChannelNum - 149) % 8 == 0)
++ && (pmlmeext->channel_set[i].rx_count < pmlmeext->channel_set[index_5G].rx_count) ) {
++ index_5G = i;
++ best_channel_5G = pmlmeext->channel_set[i].ChannelNum;
++ }
++ }
++#if 1 // debug
++ len += snprintf(page + len, count - len, "The rx cnt of channel %3d = %d\n",
++ pmlmeext->channel_set[i].ChannelNum, pmlmeext->channel_set[i].rx_count);
++#endif
++ }
++
++ len += snprintf(page + len, count - len, "best_channel_5G = %d\n", best_channel_5G);
++ len += snprintf(page + len, count - len, "best_channel_24G = %d\n", best_channel_24G);
++
++ *eof = 1;
++ return len;
++
++}
++
++int proc_set_best_channel(struct file *file, const char *buffer,
++ unsigned long count, void *data)
++{
++ struct net_device *dev = (struct net_device *)data;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ char tmp[32];
++
++ if(count < 1)
++ return -EFAULT;
++
++ if(buffer && !copy_from_user(tmp, buffer, sizeof(tmp)))
++ {
++ int i;
++ for(i = 0; pmlmeext->channel_set[i].ChannelNum != 0; i++)
++ {
++ pmlmeext->channel_set[i].rx_count = 0;
++ }
++
++ DBG_871X("set %s\n", "Clean Best Channel Count");
++ }
++
++ return count;
++}
++#endif /* CONFIG_FIND_BEST_CHANNEL */
++
++#if defined(DBG_CONFIG_ERROR_DETECT)
++#include <rtw_sreset.h>
++int proc_get_sreset(char *page, char **start, off_t offset, int count, int *eof, void *data)
++{
++ struct net_device *dev = data;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++
++ int len = 0;
++
++ *eof = 1;
++ return len;
++}
++
++int proc_set_sreset(struct file *file, const char *buffer, unsigned long count, void *data)
++{
++ struct net_device *dev = (struct net_device *)data;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ char tmp[32];
++ s32 trigger_point;
++
++ if (count < 1)
++ return -EFAULT;
++
++ if (buffer && !copy_from_user(tmp, buffer, sizeof(tmp))) {
++
++ int num = sscanf(tmp, "%d", &trigger_point);
++
++ if (trigger_point == SRESET_TGP_NULL)
++ rtw_hal_sreset_reset(padapter);
++ else
++ sreset_set_trigger_point(padapter, trigger_point);
++ }
++
++ return count;
++
++}
++#endif /* DBG_CONFIG_ERROR_DETECT */
++
++#ifdef CONFIG_DM_ADAPTIVITY
++int proc_get_dm_adaptivity(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data)
++{
++ struct net_device *dev = data;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ int len = 0;
++
++ len += dm_adaptivity_get_parm_str(padapter, page, count);
++
++ *eof = 1;
++ return len;
++}
++
++int proc_set_dm_adaptivity(struct file *file, const char *buffer,
++ unsigned long count, void *data)
++{
++ struct net_device *dev = (struct net_device *)data;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ char tmp[32];
++ u32 TH_L2H_ini;
++ s8 TH_EDCCA_HL_diff;
++ u32 IGI_Base;
++ int ForceEDCCA;
++ u8 AdapEn_RSSI;
++ u8 IGI_LowerBound;
++
++ if (count < 1)
++ return -EFAULT;
++
++ if (buffer && !copy_from_user(tmp, buffer, sizeof(tmp))) {
++
++ int num = sscanf(tmp, "%x %hhd %x %d %hhu %hhu",
++ &TH_L2H_ini, &TH_EDCCA_HL_diff, &IGI_Base, &ForceEDCCA, &AdapEn_RSSI, &IGI_LowerBound);
++
++ if (num != 6)
++ return count;
++
++ dm_adaptivity_set_parm(padapter, (s8)TH_L2H_ini, TH_EDCCA_HL_diff, (s8)IGI_Base, (bool)ForceEDCCA, AdapEn_RSSI, IGI_LowerBound);
++ }
++
++ return count;
++}
++#endif /* CONFIG_DM_ADAPTIVITY */
++
++#endif
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/core/rtw_eeprom.c linux-xbian-rpi/drivers/net/wireless/rtl8192cu/core/rtw_eeprom.c
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/core/rtw_eeprom.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/core/rtw_eeprom.c 2015-07-28 01:20:58.301668422 +0200
+@@ -0,0 +1,422 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#define _RTW_EEPROM_C_
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++
++void up_clk(_adapter* padapter, u16 *x)
++{
++_func_enter_;
++ *x = *x | _EESK;
++ rtw_write8(padapter, EE_9346CR, (u8)*x);
++ rtw_udelay_os(CLOCK_RATE);
++
++_func_exit_;
++
++}
++
++void down_clk(_adapter * padapter, u16 *x )
++{
++_func_enter_;
++ *x = *x & ~_EESK;
++ rtw_write8(padapter, EE_9346CR, (u8)*x);
++ rtw_udelay_os(CLOCK_RATE);
++_func_exit_;
++}
++
++void shift_out_bits(_adapter * padapter, u16 data, u16 count)
++{
++ u16 x,mask;
++_func_enter_;
++
++ if(padapter->bSurpriseRemoved==_TRUE){
++ RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
++ goto out;
++ }
++ mask = 0x01 << (count - 1);
++ x = rtw_read8(padapter, EE_9346CR);
++
++ x &= ~(_EEDO | _EEDI);
++
++ do
++ {
++ x &= ~_EEDI;
++ if(data & mask)
++ x |= _EEDI;
++ if(padapter->bSurpriseRemoved==_TRUE){
++ RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
++ goto out;
++ }
++ rtw_write8(padapter, EE_9346CR, (u8)x);
++ rtw_udelay_os(CLOCK_RATE);
++ up_clk(padapter, &x);
++ down_clk(padapter, &x);
++ mask = mask >> 1;
++ } while(mask);
++ if(padapter->bSurpriseRemoved==_TRUE){
++ RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
++ goto out;
++ }
++ x &= ~_EEDI;
++ rtw_write8(padapter, EE_9346CR, (u8)x);
++out:
++_func_exit_;
++}
++
++u16 shift_in_bits (_adapter * padapter)
++{
++ u16 x,d=0,i;
++_func_enter_;
++ if(padapter->bSurpriseRemoved==_TRUE){
++ RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
++ goto out;
++ }
++ x = rtw_read8(padapter, EE_9346CR);
++
++ x &= ~( _EEDO | _EEDI);
++ d = 0;
++
++ for(i=0; i<16; i++)
++ {
++ d = d << 1;
++ up_clk(padapter, &x);
++ if(padapter->bSurpriseRemoved==_TRUE){
++ RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
++ goto out;
++ }
++ x = rtw_read8(padapter, EE_9346CR);
++
++ x &= ~(_EEDI);
++ if(x & _EEDO)
++ d |= 1;
++
++ down_clk(padapter, &x);
++ }
++out:
++_func_exit_;
++
++ return d;
++}
++
++void standby(_adapter * padapter )
++{
++ u8 x;
++_func_enter_;
++ x = rtw_read8(padapter, EE_9346CR);
++
++ x &= ~(_EECS | _EESK);
++ rtw_write8(padapter, EE_9346CR,x);
++
++ rtw_udelay_os(CLOCK_RATE);
++ x |= _EECS;
++ rtw_write8(padapter, EE_9346CR, x);
++ rtw_udelay_os(CLOCK_RATE);
++_func_exit_;
++}
++
++u16 wait_eeprom_cmd_done(_adapter* padapter)
++{
++ u8 x;
++ u16 i,res=_FALSE;
++_func_enter_;
++ standby(padapter );
++ for (i=0; i<200; i++)
++ {
++ x = rtw_read8(padapter, EE_9346CR);
++ if (x & _EEDO){
++ res=_TRUE;
++ goto exit;
++ }
++ rtw_udelay_os(CLOCK_RATE);
++ }
++exit:
++_func_exit_;
++ return res;
++}
++
++void eeprom_clean(_adapter * padapter)
++{
++ u16 x;
++_func_enter_;
++ if(padapter->bSurpriseRemoved==_TRUE){
++ RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
++ goto out;
++ }
++ x = rtw_read8(padapter, EE_9346CR);
++ if(padapter->bSurpriseRemoved==_TRUE){
++ RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
++ goto out;
++ }
++ x &= ~(_EECS | _EEDI);
++ rtw_write8(padapter, EE_9346CR, (u8)x);
++ if(padapter->bSurpriseRemoved==_TRUE){
++ RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
++ goto out;
++ }
++ up_clk(padapter, &x);
++ if(padapter->bSurpriseRemoved==_TRUE){
++ RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
++ goto out;
++ }
++ down_clk(padapter, &x);
++out:
++_func_exit_;
++}
++
++void eeprom_write16(_adapter * padapter, u16 reg, u16 data)
++{
++ u8 x;
++#ifdef CONFIG_RTL8712
++ u8 tmp8_ori,tmp8_new,tmp8_clk_ori,tmp8_clk_new;
++ tmp8_ori=rtw_read8(padapter, 0x102502f1);
++ tmp8_new=tmp8_ori & 0xf7;
++ if(tmp8_ori != tmp8_new){
++ rtw_write8(padapter, 0x102502f1, tmp8_new);
++ RT_TRACE(_module_rtl871x_mp_ioctl_c_,_drv_err_,("====write 0x102502f1=====\n"));
++ }
++ tmp8_clk_ori=rtw_read8(padapter,0x10250003);
++ tmp8_clk_new=tmp8_clk_ori|0x20;
++ if(tmp8_clk_new!=tmp8_clk_ori){
++ RT_TRACE(_module_rtl871x_mp_ioctl_c_,_drv_err_,("====write 0x10250003=====\n"));
++ rtw_write8(padapter, 0x10250003, tmp8_clk_new);
++ }
++#endif
++_func_enter_;
++
++ x = rtw_read8(padapter, EE_9346CR);
++
++ x &= ~(_EEDI | _EEDO | _EESK | _EEM0);
++ x |= _EEM1 | _EECS;
++ rtw_write8(padapter, EE_9346CR, x);
++
++ shift_out_bits(padapter, EEPROM_EWEN_OPCODE, 5);
++
++ if(padapter->EepromAddressSize==8) //CF+ and SDIO
++ shift_out_bits(padapter, 0, 6);
++ else //USB
++ shift_out_bits(padapter, 0, 4);
++
++ standby( padapter);
++
++// Commented out by rcnjko, 2004.0
++// // Erase this particular word. Write the erase opcode and register
++// // number in that order. The opcode is 3bits in length; reg is 6 bits long.
++// shift_out_bits(Adapter, EEPROM_ERASE_OPCODE, 3);
++// shift_out_bits(Adapter, reg, Adapter->EepromAddressSize);
++//
++// if (wait_eeprom_cmd_done(Adapter ) == FALSE)
++// {
++// return;
++// }
++
++
++ standby(padapter );
++
++ // write the new word to the EEPROM
++
++ // send the write opcode the EEPORM
++ shift_out_bits(padapter, EEPROM_WRITE_OPCODE, 3);
++
++ // select which word in the EEPROM that we are writing to.
++ shift_out_bits(padapter, reg, padapter->EepromAddressSize);
++
++ // write the data to the selected EEPROM word.
++ shift_out_bits(padapter, data, 16);
++
++ if (wait_eeprom_cmd_done(padapter ) == _FALSE)
++ {
++
++ goto exit;
++ }
++
++ standby(padapter );
++
++ shift_out_bits(padapter, EEPROM_EWDS_OPCODE, 5);
++ shift_out_bits(padapter, reg, 4);
++
++ eeprom_clean(padapter );
++exit:
++#ifdef CONFIG_RTL8712
++ if(tmp8_clk_new!=tmp8_clk_ori)
++ rtw_write8(padapter, 0x10250003, tmp8_clk_ori);
++ if(tmp8_new!=tmp8_ori)
++ rtw_write8(padapter, 0x102502f1, tmp8_ori);
++
++#endif
++_func_exit_;
++ return;
++}
++
++u16 eeprom_read16(_adapter * padapter, u16 reg) //ReadEEprom
++{
++
++ u16 x;
++ u16 data=0;
++#ifdef CONFIG_RTL8712
++ u8 tmp8_ori,tmp8_new,tmp8_clk_ori,tmp8_clk_new;
++ tmp8_ori= rtw_read8(padapter, 0x102502f1);
++ tmp8_new = tmp8_ori & 0xf7;
++ if(tmp8_ori != tmp8_new){
++ rtw_write8(padapter, 0x102502f1, tmp8_new);
++ RT_TRACE(_module_rtl871x_mp_ioctl_c_,_drv_err_,("====write 0x102502f1=====\n"));
++ }
++ tmp8_clk_ori=rtw_read8(padapter,0x10250003);
++ tmp8_clk_new=tmp8_clk_ori|0x20;
++ if(tmp8_clk_new!=tmp8_clk_ori){
++ RT_TRACE(_module_rtl871x_mp_ioctl_c_,_drv_err_,("====write 0x10250003=====\n"));
++ rtw_write8(padapter, 0x10250003, tmp8_clk_new);
++ }
++#endif
++_func_enter_;
++
++ if(padapter->bSurpriseRemoved==_TRUE){
++ RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
++ goto out;
++ }
++ // select EEPROM, reset bits, set _EECS
++ x = rtw_read8(padapter, EE_9346CR);
++
++ if(padapter->bSurpriseRemoved==_TRUE){
++ RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
++ goto out;
++ }
++
++ x &= ~(_EEDI | _EEDO | _EESK | _EEM0);
++ x |= _EEM1 | _EECS;
++ rtw_write8(padapter, EE_9346CR, (unsigned char)x);
++
++ // write the read opcode and register number in that order
++ // The opcode is 3bits in length, reg is 6 bits long
++ shift_out_bits(padapter, EEPROM_READ_OPCODE, 3);
++ shift_out_bits(padapter, reg, padapter->EepromAddressSize);
++
++ // Now read the data (16 bits) in from the selected EEPROM word
++ data = shift_in_bits(padapter);
++
++ eeprom_clean(padapter);
++out:
++#ifdef CONFIG_RTL8712
++ if(tmp8_clk_new!=tmp8_clk_ori)
++ rtw_write8(padapter, 0x10250003, tmp8_clk_ori);
++ if(tmp8_new!=tmp8_ori)
++ rtw_write8(padapter, 0x102502f1, tmp8_ori);
++
++#endif
++_func_exit_;
++ return data;
++
++
++}
++
++
++
++
++//From even offset
++void eeprom_read_sz(_adapter * padapter, u16 reg, u8* data, u32 sz)
++{
++
++ u16 x, data16;
++ u32 i;
++_func_enter_;
++ if(padapter->bSurpriseRemoved==_TRUE){
++ RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
++ goto out;
++ }
++ // select EEPROM, reset bits, set _EECS
++ x = rtw_read8(padapter, EE_9346CR);
++
++ if(padapter->bSurpriseRemoved==_TRUE){
++ RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
++ goto out;
++ }
++
++ x &= ~(_EEDI | _EEDO | _EESK | _EEM0);
++ x |= _EEM1 | _EECS;
++ rtw_write8(padapter, EE_9346CR, (unsigned char)x);
++
++ // write the read opcode and register number in that order
++ // The opcode is 3bits in length, reg is 6 bits long
++ shift_out_bits(padapter, EEPROM_READ_OPCODE, 3);
++ shift_out_bits(padapter, reg, padapter->EepromAddressSize);
++
++
++ for(i=0; i<sz; i+=2)
++ {
++ data16 = shift_in_bits(padapter);
++ data[i] = data16 & 0xff;
++ data[i+1] = data16 >>8;
++ }
++
++ eeprom_clean(padapter);
++out:
++_func_exit_;
++
++
++
++}
++
++
++//addr_off : address offset of the entry in eeprom (not the tuple number of eeprom (reg); that is addr_off !=reg)
++u8 eeprom_read(_adapter * padapter, u32 addr_off, u8 sz, u8* rbuf)
++{
++ u8 quotient, remainder, addr_2align_odd;
++ u16 reg, stmp , i=0, idx = 0;
++_func_enter_;
++ reg = (u16)(addr_off >> 1);
++ addr_2align_odd = (u8)(addr_off & 0x1);
++
++ if(addr_2align_odd) //read that start at high part: e.g 1,3,5,7,9,...
++ {
++ stmp = eeprom_read16(padapter, reg);
++ rbuf[idx++] = (u8) ((stmp>>8)&0xff); //return hogh-part of the short
++ reg++; sz--;
++ }
++
++ quotient = sz >> 1;
++ remainder = sz & 0x1;
++
++ for( i=0 ; i < quotient; i++)
++ {
++ stmp = eeprom_read16(padapter, reg+i);
++ rbuf[idx++] = (u8) (stmp&0xff);
++ rbuf[idx++] = (u8) ((stmp>>8)&0xff);
++ }
++
++ reg = reg+i;
++ if(remainder){ //end of read at lower part of short : 0,2,4,6,...
++ stmp = eeprom_read16(padapter, reg);
++ rbuf[idx] = (u8)(stmp & 0xff);
++ }
++_func_exit_;
++ return _TRUE;
++}
++
++
++
++VOID read_eeprom_content(_adapter * padapter)
++{
++
++_func_enter_;
++
++
++_func_exit_;
++}
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/core/rtw_ieee80211.c linux-xbian-rpi/drivers/net/wireless/rtl8192cu/core/rtw_ieee80211.c
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/core/rtw_ieee80211.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/core/rtw_ieee80211.c 2015-07-28 01:20:58.301668422 +0200
+@@ -0,0 +1,1914 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#define _IEEE80211_C
++
++#include <drv_types.h>
++#include <ieee80211.h>
++#include <wifi.h>
++#include <osdep_service.h>
++#include <wlan_bssdef.h>
++
++u8 RTW_WPA_OUI_TYPE[] = { 0x00, 0x50, 0xf2, 1 };
++u16 RTW_WPA_VERSION = 1;
++u8 WPA_AUTH_KEY_MGMT_NONE[] = { 0x00, 0x50, 0xf2, 0 };
++u8 WPA_AUTH_KEY_MGMT_UNSPEC_802_1X[] = { 0x00, 0x50, 0xf2, 1 };
++u8 WPA_AUTH_KEY_MGMT_PSK_OVER_802_1X[] = { 0x00, 0x50, 0xf2, 2 };
++u8 WPA_CIPHER_SUITE_NONE[] = { 0x00, 0x50, 0xf2, 0 };
++u8 WPA_CIPHER_SUITE_WEP40[] = { 0x00, 0x50, 0xf2, 1 };
++u8 WPA_CIPHER_SUITE_TKIP[] = { 0x00, 0x50, 0xf2, 2 };
++u8 WPA_CIPHER_SUITE_WRAP[] = { 0x00, 0x50, 0xf2, 3 };
++u8 WPA_CIPHER_SUITE_CCMP[] = { 0x00, 0x50, 0xf2, 4 };
++u8 WPA_CIPHER_SUITE_WEP104[] = { 0x00, 0x50, 0xf2, 5 };
++
++u16 RSN_VERSION_BSD = 1;
++u8 RSN_AUTH_KEY_MGMT_UNSPEC_802_1X[] = { 0x00, 0x0f, 0xac, 1 };
++u8 RSN_AUTH_KEY_MGMT_PSK_OVER_802_1X[] = { 0x00, 0x0f, 0xac, 2 };
++u8 RSN_CIPHER_SUITE_NONE[] = { 0x00, 0x0f, 0xac, 0 };
++u8 RSN_CIPHER_SUITE_WEP40[] = { 0x00, 0x0f, 0xac, 1 };
++u8 RSN_CIPHER_SUITE_TKIP[] = { 0x00, 0x0f, 0xac, 2 };
++u8 RSN_CIPHER_SUITE_WRAP[] = { 0x00, 0x0f, 0xac, 3 };
++u8 RSN_CIPHER_SUITE_CCMP[] = { 0x00, 0x0f, 0xac, 4 };
++u8 RSN_CIPHER_SUITE_WEP104[] = { 0x00, 0x0f, 0xac, 5 };
++//-----------------------------------------------------------
++// for adhoc-master to generate ie and provide supported-rate to fw
++//-----------------------------------------------------------
++
++static u8 WIFI_CCKRATES[] =
++{(IEEE80211_CCK_RATE_1MB | IEEE80211_BASIC_RATE_MASK),
++ (IEEE80211_CCK_RATE_2MB | IEEE80211_BASIC_RATE_MASK),
++ (IEEE80211_CCK_RATE_5MB | IEEE80211_BASIC_RATE_MASK),
++ (IEEE80211_CCK_RATE_11MB | IEEE80211_BASIC_RATE_MASK)};
++
++static u8 WIFI_OFDMRATES[] =
++{(IEEE80211_OFDM_RATE_6MB),
++ (IEEE80211_OFDM_RATE_9MB),
++ (IEEE80211_OFDM_RATE_12MB),
++ (IEEE80211_OFDM_RATE_18MB),
++ (IEEE80211_OFDM_RATE_24MB),
++ IEEE80211_OFDM_RATE_36MB,
++ IEEE80211_OFDM_RATE_48MB,
++ IEEE80211_OFDM_RATE_54MB};
++
++
++int rtw_get_bit_value_from_ieee_value(u8 val)
++{
++ unsigned char dot11_rate_table[]={2,4,11,22,12,18,24,36,48,72,96,108,0}; // last element must be zero!!
++
++ int i=0;
++ while(dot11_rate_table[i] != 0) {
++ if (dot11_rate_table[i] == val)
++ return BIT(i);
++ i++;
++ }
++ return 0;
++}
++
++uint rtw_is_cckrates_included(u8 *rate)
++{
++ u32 i = 0;
++
++ while(rate[i]!=0)
++ {
++ if ( (((rate[i]) & 0x7f) == 2) || (((rate[i]) & 0x7f) == 4) ||
++ (((rate[i]) & 0x7f) == 11) || (((rate[i]) & 0x7f) == 22) )
++ return _TRUE;
++ i++;
++ }
++
++ return _FALSE;
++}
++
++uint rtw_is_cckratesonly_included(u8 *rate)
++{
++ u32 i = 0;
++
++
++ while(rate[i]!=0)
++ {
++ if ( (((rate[i]) & 0x7f) != 2) && (((rate[i]) & 0x7f) != 4) &&
++ (((rate[i]) & 0x7f) != 11) && (((rate[i]) & 0x7f) != 22) )
++
++ return _FALSE;
++
++ i++;
++ }
++
++ return _TRUE;
++
++}
++
++int rtw_check_network_type(unsigned char *rate, int ratelen, int channel)
++{
++ if (channel > 14)
++ {
++ if ((rtw_is_cckrates_included(rate)) == _TRUE)
++ return WIRELESS_INVALID;
++ else
++ return WIRELESS_11A;
++ }
++ else // could be pure B, pure G, or B/G
++ {
++ if ((rtw_is_cckratesonly_included(rate)) == _TRUE)
++ return WIRELESS_11B;
++ else if((rtw_is_cckrates_included(rate)) == _TRUE)
++ return WIRELESS_11BG;
++ else
++ return WIRELESS_11G;
++ }
++
++}
++
++u8 *rtw_set_fixed_ie(unsigned char *pbuf, unsigned int len, unsigned char *source,
++ unsigned int *frlen)
++{
++ _rtw_memcpy((void *)pbuf, (void *)source, len);
++ *frlen = *frlen + len;
++ return (pbuf + len);
++}
++
++// rtw_set_ie will update frame length
++u8 *rtw_set_ie
++(
++ u8 *pbuf,
++ sint index,
++ uint len,
++ u8 *source,
++ uint *frlen //frame length
++)
++{
++_func_enter_;
++ *pbuf = (u8)index;
++
++ *(pbuf + 1) = (u8)len;
++
++ if (len > 0)
++ _rtw_memcpy((void *)(pbuf + 2), (void *)source, len);
++
++ *frlen = *frlen + (len + 2);
++
++ return (pbuf + len + 2);
++_func_exit_;
++}
++
++inline u8 *rtw_set_ie_ch_switch(u8 *buf, u32 *buf_len, u8 ch_switch_mode,
++ u8 new_ch, u8 ch_switch_cnt)
++{
++ u8 ie_data[3];
++
++ ie_data[0] = ch_switch_mode;
++ ie_data[1] = new_ch;
++ ie_data[2] = ch_switch_cnt;
++ return rtw_set_ie(buf, WLAN_EID_CHANNEL_SWITCH, 3, ie_data, buf_len);
++}
++
++inline u8 secondary_ch_offset_to_hal_ch_offset(u8 ch_offset)
++{
++ if (ch_offset == SCN)
++ return HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++ else if(ch_offset == SCA)
++ return HAL_PRIME_CHNL_OFFSET_UPPER;
++ else if(ch_offset == SCB)
++ return HAL_PRIME_CHNL_OFFSET_LOWER;
++
++ return HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++}
++
++inline u8 hal_ch_offset_to_secondary_ch_offset(u8 ch_offset)
++{
++ if (ch_offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE)
++ return SCN;
++ else if(ch_offset == HAL_PRIME_CHNL_OFFSET_LOWER)
++ return SCB;
++ else if(ch_offset == HAL_PRIME_CHNL_OFFSET_UPPER)
++ return SCA;
++
++ return SCN;
++}
++
++inline u8 *rtw_set_ie_secondary_ch_offset(u8 *buf, u32 *buf_len, u8 secondary_ch_offset)
++{
++ return rtw_set_ie(buf, WLAN_EID_SECONDARY_CHANNEL_OFFSET, 1, &secondary_ch_offset, buf_len);
++}
++
++inline u8 *rtw_set_ie_mesh_ch_switch_parm(u8 *buf, u32 *buf_len, u8 ttl,
++ u8 flags, u16 reason, u16 precedence)
++{
++ u8 ie_data[6];
++
++ ie_data[0] = ttl;
++ ie_data[1] = flags;
++ RTW_PUT_LE16((u8*)&ie_data[2], reason);
++ RTW_PUT_LE16((u8*)&ie_data[4], precedence);
++
++ return rtw_set_ie(buf, 0x118, 6, ie_data, buf_len);
++}
++
++/*----------------------------------------------------------------------------
++index: the information element id index, limit is the limit for search
++-----------------------------------------------------------------------------*/
++u8 *rtw_get_ie(u8 *pbuf, sint index, sint *len, sint limit)
++{
++ sint tmp,i;
++ u8 *p;
++_func_enter_;
++ if (limit < 1){
++ _func_exit_;
++ return NULL;
++ }
++
++ p = pbuf;
++ i = 0;
++ *len = 0;
++ while(1)
++ {
++ if (*p == index)
++ {
++ *len = *(p + 1);
++ return (p);
++ }
++ else
++ {
++ tmp = *(p + 1);
++ p += (tmp + 2);
++ i += (tmp + 2);
++ }
++ if (i >= limit)
++ break;
++ }
++_func_exit_;
++ return NULL;
++}
++
++/**
++ * rtw_get_ie_ex - Search specific IE from a series of IEs
++ * @in_ie: Address of IEs to search
++ * @in_len: Length limit from in_ie
++ * @eid: Element ID to match
++ * @oui: OUI to match
++ * @oui_len: OUI length
++ * @ie: If not NULL and the specific IE is found, the IE will be copied to the buf starting from the specific IE
++ * @ielen: If not NULL and the specific IE is found, will set to the length of the entire IE
++ *
++ * Returns: The address of the specific IE found, or NULL
++ */
++u8 *rtw_get_ie_ex(u8 *in_ie, uint in_len, u8 eid, u8 *oui, u8 oui_len, u8 *ie, uint *ielen)
++{
++ uint cnt;
++ u8 *target_ie = NULL;
++
++
++ if(ielen)
++ *ielen = 0;
++
++ if(!in_ie || in_len<=0)
++ return target_ie;
++
++ cnt = 0;
++
++ while(cnt<in_len)
++ {
++ if(eid == in_ie[cnt]
++ && ( !oui || _rtw_memcmp(&in_ie[cnt+2], oui, oui_len) == _TRUE))
++ {
++ target_ie = &in_ie[cnt];
++
++ if(ie)
++ _rtw_memcpy(ie, &in_ie[cnt], in_ie[cnt+1]+2);
++
++ if(ielen)
++ *ielen = in_ie[cnt+1]+2;
++
++ break;
++ }
++ else
++ {
++ cnt+=in_ie[cnt+1]+2; //goto next
++ }
++
++ }
++
++ return target_ie;
++}
++
++/**
++ * rtw_ies_remove_ie - Find matching IEs and remove
++ * @ies: Address of IEs to search
++ * @ies_len: Pointer of length of ies, will update to new length
++ * @offset: The offset to start scarch
++ * @eid: Element ID to match
++ * @oui: OUI to match
++ * @oui_len: OUI length
++ *
++ * Returns: _SUCCESS: ies is updated, _FAIL: not updated
++ */
++int rtw_ies_remove_ie(u8 *ies, uint *ies_len, uint offset, u8 eid, u8 *oui, u8 oui_len)
++{
++ int ret = _FAIL;
++ u8 *target_ie;
++ u32 target_ielen;
++ u8 *start;
++ uint search_len;
++
++ if(!ies || !ies_len || *ies_len <= offset)
++ goto exit;
++
++ start = ies + offset;
++ search_len = *ies_len - offset;
++
++ while (1) {
++ target_ie = rtw_get_ie_ex(start, search_len, eid, oui, oui_len, NULL, &target_ielen);
++ if (target_ie && target_ielen) {
++ u8 buf[MAX_IE_SZ] = {0};
++ u8 *remain_ies = target_ie + target_ielen;
++ uint remain_len = search_len - (remain_ies - start);
++
++ _rtw_memcpy(buf, remain_ies, remain_len);
++ _rtw_memcpy(target_ie, buf, remain_len);
++ *ies_len = *ies_len - target_ielen;
++ ret = _SUCCESS;
++
++ start = target_ie;
++ search_len = remain_len;
++ } else {
++ break;
++ }
++ }
++exit:
++ return ret;
++}
++
++void rtw_set_supported_rate(u8* SupportedRates, uint mode)
++{
++_func_enter_;
++
++ _rtw_memset(SupportedRates, 0, NDIS_802_11_LENGTH_RATES_EX);
++
++ switch (mode)
++ {
++ case WIRELESS_11B:
++ _rtw_memcpy(SupportedRates, WIFI_CCKRATES, IEEE80211_CCK_RATE_LEN);
++ break;
++
++ case WIRELESS_11G:
++ case WIRELESS_11A:
++ case WIRELESS_11_5N:
++ case WIRELESS_11A_5N://Todo: no basic rate for ofdm ?
++ _rtw_memcpy(SupportedRates, WIFI_OFDMRATES, IEEE80211_NUM_OFDM_RATESLEN);
++ break;
++
++ case WIRELESS_11BG:
++ case WIRELESS_11G_24N:
++ case WIRELESS_11_24N:
++ case WIRELESS_11BG_24N:
++ _rtw_memcpy(SupportedRates, WIFI_CCKRATES, IEEE80211_CCK_RATE_LEN);
++ _rtw_memcpy(SupportedRates + IEEE80211_CCK_RATE_LEN, WIFI_OFDMRATES, IEEE80211_NUM_OFDM_RATESLEN);
++ break;
++
++ }
++_func_exit_;
++}
++
++uint rtw_get_rateset_len(u8 *rateset)
++{
++ uint i = 0;
++_func_enter_;
++ while(1)
++ {
++ if ((rateset[i]) == 0)
++ break;
++
++ if (i > 12)
++ break;
++
++ i++;
++ }
++_func_exit_;
++ return i;
++}
++
++int rtw_generate_ie(struct registry_priv *pregistrypriv)
++{
++ u8 wireless_mode;
++ int sz = 0, rateLen;
++ WLAN_BSSID_EX* pdev_network = &pregistrypriv->dev_network;
++ u8* ie = pdev_network->IEs;
++
++_func_enter_;
++
++ //timestamp will be inserted by hardware
++ sz += 8;
++ ie += sz;
++
++ //beacon interval : 2bytes
++ *(u16*)ie = cpu_to_le16((u16)pdev_network->Configuration.BeaconPeriod);//BCN_INTERVAL;
++ sz += 2;
++ ie += 2;
++
++ //capability info
++ *(u16*)ie = 0;
++
++ *(u16*)ie |= cpu_to_le16(cap_IBSS);
++
++ if(pregistrypriv->preamble == PREAMBLE_SHORT)
++ *(u16*)ie |= cpu_to_le16(cap_ShortPremble);
++
++ if (pdev_network->Privacy)
++ *(u16*)ie |= cpu_to_le16(cap_Privacy);
++
++ sz += 2;
++ ie += 2;
++
++ //SSID
++ ie = rtw_set_ie(ie, _SSID_IE_, pdev_network->Ssid.SsidLength, pdev_network->Ssid.Ssid, &sz);
++
++ //supported rates
++ if(pregistrypriv->wireless_mode == WIRELESS_11ABGN)
++ {
++ if(pdev_network->Configuration.DSConfig > 14)
++ wireless_mode = WIRELESS_11A_5N;
++ else
++ wireless_mode = WIRELESS_11BG_24N;
++ }
++ else
++ {
++ wireless_mode = pregistrypriv->wireless_mode;
++ }
++
++ rtw_set_supported_rate(pdev_network->SupportedRates, wireless_mode) ;
++
++ rateLen = rtw_get_rateset_len(pdev_network->SupportedRates);
++
++ if (rateLen > 8)
++ {
++ ie = rtw_set_ie(ie, _SUPPORTEDRATES_IE_, 8, pdev_network->SupportedRates, &sz);
++ //ie = rtw_set_ie(ie, _EXT_SUPPORTEDRATES_IE_, (rateLen - 8), (pdev_network->SupportedRates + 8), &sz);
++ }
++ else
++ {
++ ie = rtw_set_ie(ie, _SUPPORTEDRATES_IE_, rateLen, pdev_network->SupportedRates, &sz);
++ }
++
++ //DS parameter set
++ ie = rtw_set_ie(ie, _DSSET_IE_, 1, (u8 *)&(pdev_network->Configuration.DSConfig), &sz);
++
++
++ //IBSS Parameter Set
++
++ ie = rtw_set_ie(ie, _IBSS_PARA_IE_, 2, (u8 *)&(pdev_network->Configuration.ATIMWindow), &sz);
++
++ if (rateLen > 8)
++ {
++ ie = rtw_set_ie(ie, _EXT_SUPPORTEDRATES_IE_, (rateLen - 8), (pdev_network->SupportedRates + 8), &sz);
++ }
++
++
++ //HT Cap.
++ if(((pregistrypriv->wireless_mode&WIRELESS_11_5N)||(pregistrypriv->wireless_mode&WIRELESS_11_24N))
++ && (pregistrypriv->ht_enable==_TRUE))
++ {
++ //todo:
++ }
++
++ //pdev_network->IELength = sz; //update IELength
++
++_func_exit_;
++
++ //return _SUCCESS;
++
++ return sz;
++
++}
++
++unsigned char *rtw_get_wpa_ie(unsigned char *pie, int *wpa_ie_len, int limit)
++{
++ int len;
++ u16 val16;
++ unsigned char wpa_oui_type[] = {0x00, 0x50, 0xf2, 0x01};
++ u8 *pbuf = pie;
++
++ while(1)
++ {
++ pbuf = rtw_get_ie(pbuf, _WPA_IE_ID_, &len, limit);
++
++ if (pbuf) {
++
++ //check if oui matches...
++ if (_rtw_memcmp((pbuf + 2), wpa_oui_type, sizeof (wpa_oui_type)) == _FALSE) {
++
++ goto check_next_ie;
++ }
++
++ //check version...
++ _rtw_memcpy((u8 *)&val16, (pbuf + 6), sizeof(val16));
++
++ val16 = le16_to_cpu(val16);
++ if (val16 != 0x0001)
++ goto check_next_ie;
++
++ *wpa_ie_len = *(pbuf + 1);
++
++ return pbuf;
++ }
++ else {
++
++ *wpa_ie_len = 0;
++ return NULL;
++ }
++
++check_next_ie:
++
++ limit -= (2 + len);
++
++ if (limit <= 0)
++ break;
++
++ pbuf += (2 + len);
++ }
++
++ *wpa_ie_len = 0;
++
++ return NULL;
++}
++
++unsigned char *rtw_get_wpa2_ie(unsigned char *pie, int *rsn_ie_len, int limit)
++{
++
++ return rtw_get_ie(pie, _WPA2_IE_ID_,rsn_ie_len, limit);
++
++}
++
++int rtw_get_wpa_cipher_suite(u8 *s)
++{
++ if (_rtw_memcmp(s, WPA_CIPHER_SUITE_NONE, WPA_SELECTOR_LEN) == _TRUE)
++ return WPA_CIPHER_NONE;
++ if (_rtw_memcmp(s, WPA_CIPHER_SUITE_WEP40, WPA_SELECTOR_LEN) == _TRUE)
++ return WPA_CIPHER_WEP40;
++ if (_rtw_memcmp(s, WPA_CIPHER_SUITE_TKIP, WPA_SELECTOR_LEN) == _TRUE)
++ return WPA_CIPHER_TKIP;
++ if (_rtw_memcmp(s, WPA_CIPHER_SUITE_CCMP, WPA_SELECTOR_LEN) == _TRUE)
++ return WPA_CIPHER_CCMP;
++ if (_rtw_memcmp(s, WPA_CIPHER_SUITE_WEP104, WPA_SELECTOR_LEN) == _TRUE)
++ return WPA_CIPHER_WEP104;
++
++ return 0;
++}
++
++int rtw_get_wpa2_cipher_suite(u8 *s)
++{
++ if (_rtw_memcmp(s, RSN_CIPHER_SUITE_NONE, RSN_SELECTOR_LEN) == _TRUE)
++ return WPA_CIPHER_NONE;
++ if (_rtw_memcmp(s, RSN_CIPHER_SUITE_WEP40, RSN_SELECTOR_LEN) == _TRUE)
++ return WPA_CIPHER_WEP40;
++ if (_rtw_memcmp(s, RSN_CIPHER_SUITE_TKIP, RSN_SELECTOR_LEN) == _TRUE)
++ return WPA_CIPHER_TKIP;
++ if (_rtw_memcmp(s, RSN_CIPHER_SUITE_CCMP, RSN_SELECTOR_LEN) == _TRUE)
++ return WPA_CIPHER_CCMP;
++ if (_rtw_memcmp(s, RSN_CIPHER_SUITE_WEP104, RSN_SELECTOR_LEN) == _TRUE)
++ return WPA_CIPHER_WEP104;
++
++ return 0;
++}
++
++
++int rtw_parse_wpa_ie(u8* wpa_ie, int wpa_ie_len, int *group_cipher, int *pairwise_cipher)
++{
++ int i, ret=_SUCCESS;
++ int left, count;
++ u8 *pos;
++
++ if (wpa_ie_len <= 0) {
++ /* No WPA IE - fail silently */
++ return _FAIL;
++ }
++
++
++ if ((*wpa_ie != _WPA_IE_ID_) || (*(wpa_ie+1) != (u8)(wpa_ie_len - 2)) ||
++ (_rtw_memcmp(wpa_ie+2, RTW_WPA_OUI_TYPE, WPA_SELECTOR_LEN) != _TRUE) )
++ {
++ return _FAIL;
++ }
++
++ pos = wpa_ie;
++
++ pos += 8;
++ left = wpa_ie_len - 8;
++
++
++ //group_cipher
++ if (left >= WPA_SELECTOR_LEN) {
++
++ *group_cipher = rtw_get_wpa_cipher_suite(pos);
++
++ pos += WPA_SELECTOR_LEN;
++ left -= WPA_SELECTOR_LEN;
++
++ }
++ else if (left > 0)
++ {
++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("%s: ie length mismatch, %u too much", __FUNCTION__, left));
++
++ return _FAIL;
++ }
++
++
++ //pairwise_cipher
++ if (left >= 2)
++ {
++ //count = le16_to_cpu(*(u16*)pos);
++ count = RTW_GET_LE16(pos);
++ pos += 2;
++ left -= 2;
++
++ if (count == 0 || left < count * WPA_SELECTOR_LEN) {
++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("%s: ie count botch (pairwise), "
++ "count %u left %u", __FUNCTION__, count, left));
++ return _FAIL;
++ }
++
++ for (i = 0; i < count; i++)
++ {
++ *pairwise_cipher |= rtw_get_wpa_cipher_suite(pos);
++
++ pos += WPA_SELECTOR_LEN;
++ left -= WPA_SELECTOR_LEN;
++ }
++
++ }
++ else if (left == 1)
++ {
++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("%s: ie too short (for key mgmt)", __FUNCTION__));
++ return _FAIL;
++ }
++
++
++ return ret;
++
++}
++
++int rtw_parse_wpa2_ie(u8* rsn_ie, int rsn_ie_len, int *group_cipher, int *pairwise_cipher)
++{
++ int i, ret=_SUCCESS;
++ int left, count;
++ u8 *pos;
++
++ if (rsn_ie_len <= 0) {
++ /* No RSN IE - fail silently */
++ return _FAIL;
++ }
++
++
++ if ((*rsn_ie!= _WPA2_IE_ID_) || (*(rsn_ie+1) != (u8)(rsn_ie_len - 2)))
++ {
++ return _FAIL;
++ }
++
++ pos = rsn_ie;
++ pos += 4;
++ left = rsn_ie_len - 4;
++
++ //group_cipher
++ if (left >= RSN_SELECTOR_LEN) {
++
++ *group_cipher = rtw_get_wpa2_cipher_suite(pos);
++
++ pos += RSN_SELECTOR_LEN;
++ left -= RSN_SELECTOR_LEN;
++
++ } else if (left > 0) {
++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("%s: ie length mismatch, %u too much", __FUNCTION__, left));
++ return _FAIL;
++ }
++
++ //pairwise_cipher
++ if (left >= 2)
++ {
++ //count = le16_to_cpu(*(u16*)pos);
++ count = RTW_GET_LE16(pos);
++ pos += 2;
++ left -= 2;
++
++ if (count == 0 || left < count * RSN_SELECTOR_LEN) {
++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("%s: ie count botch (pairwise), "
++ "count %u left %u", __FUNCTION__, count, left));
++ return _FAIL;
++ }
++
++ for (i = 0; i < count; i++)
++ {
++ *pairwise_cipher |= rtw_get_wpa2_cipher_suite(pos);
++
++ pos += RSN_SELECTOR_LEN;
++ left -= RSN_SELECTOR_LEN;
++ }
++
++ }
++ else if (left == 1)
++ {
++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("%s: ie too short (for key mgmt)", __FUNCTION__));
++
++ return _FAIL;
++ }
++
++
++ return ret;
++
++}
++
++int rtw_get_sec_ie(u8 *in_ie,uint in_len,u8 *rsn_ie,u16 *rsn_len,u8 *wpa_ie,u16 *wpa_len)
++{
++ u8 authmode, sec_idx, i;
++ u8 wpa_oui[4]={0x0,0x50,0xf2,0x01};
++ uint cnt;
++
++_func_enter_;
++
++ //Search required WPA or WPA2 IE and copy to sec_ie[ ]
++
++ cnt = (_TIMESTAMP_ + _BEACON_ITERVAL_ + _CAPABILITY_);
++
++ sec_idx=0;
++
++ while(cnt<in_len)
++ {
++ authmode=in_ie[cnt];
++
++ if((authmode==_WPA_IE_ID_)&&(_rtw_memcmp(&in_ie[cnt+2], &wpa_oui[0],4)==_TRUE))
++ {
++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("\n rtw_get_wpa_ie: sec_idx=%d in_ie[cnt+1]+2=%d\n",sec_idx,in_ie[cnt+1]+2));
++
++ _rtw_memcpy(wpa_ie, &in_ie[cnt],in_ie[cnt+1]+2);
++
++ for(i=0;i<(in_ie[cnt+1]+2);i=i+8){
++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("\n %2x,%2x,%2x,%2x,%2x,%2x,%2x,%2x\n",wpa_ie[i],wpa_ie[i+1],wpa_ie[i+2],wpa_ie[i+3],wpa_ie[i+4],wpa_ie[i+5],wpa_ie[i+6],wpa_ie[i+7]));
++ }
++
++ *wpa_len=in_ie[cnt+1]+2;
++ cnt+=in_ie[cnt+1]+2; //get next
++ }
++ else
++ {
++ if(authmode==_WPA2_IE_ID_)
++ {
++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("\n get_rsn_ie: sec_idx=%d in_ie[cnt+1]+2=%d\n",sec_idx,in_ie[cnt+1]+2));
++
++ _rtw_memcpy(rsn_ie, &in_ie[cnt],in_ie[cnt+1]+2);
++
++ for(i=0;i<(in_ie[cnt+1]+2);i=i+8){
++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("\n %2x,%2x,%2x,%2x,%2x,%2x,%2x,%2x\n",rsn_ie[i],rsn_ie[i+1],rsn_ie[i+2],rsn_ie[i+3],rsn_ie[i+4],rsn_ie[i+5],rsn_ie[i+6],rsn_ie[i+7]));
++ }
++
++ *rsn_len=in_ie[cnt+1]+2;
++ cnt+=in_ie[cnt+1]+2; //get next
++ }
++ else
++ {
++ cnt+=in_ie[cnt+1]+2; //get next
++ }
++ }
++
++ }
++
++_func_exit_;
++
++ return (*rsn_len+*wpa_len);
++
++}
++
++u8 rtw_is_wps_ie(u8 *ie_ptr, uint *wps_ielen)
++{
++ u8 match = _FALSE;
++ u8 eid, wps_oui[4]={0x0,0x50,0xf2,0x04};
++
++ if(ie_ptr == NULL) return match;
++
++ eid = ie_ptr[0];
++
++ if((eid==_WPA_IE_ID_)&&(_rtw_memcmp(&ie_ptr[2], wps_oui, 4)==_TRUE))
++ {
++ //printk("==> found WPS_IE.....\n");
++ *wps_ielen = ie_ptr[1]+2;
++ match=_TRUE;
++ }
++ return match;
++}
++
++/**
++ * rtw_get_wps_ie - Search WPS IE from a series of IEs
++ * @in_ie: Address of IEs to search
++ * @in_len: Length limit from in_ie
++ * @wps_ie: If not NULL and WPS IE is found, WPS IE will be copied to the buf starting from wps_ie
++ * @wps_ielen: If not NULL and WPS IE is found, will set to the length of the entire WPS IE
++ *
++ * Returns: The address of the WPS IE found, or NULL
++ */
++u8 *rtw_get_wps_ie(u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen)
++{
++ uint cnt;
++ u8 *wpsie_ptr=NULL;
++ u8 eid, wps_oui[4]={0x0,0x50,0xf2,0x04};
++
++ if(wps_ielen)
++ *wps_ielen = 0;
++
++ if(!in_ie || in_len<=0)
++ return wpsie_ptr;
++
++ cnt = 0;
++
++ while(cnt<in_len)
++ {
++ eid = in_ie[cnt];
++
++ if((eid==_WPA_IE_ID_)&&(_rtw_memcmp(&in_ie[cnt+2], wps_oui, 4)==_TRUE))
++ {
++ wpsie_ptr = &in_ie[cnt];
++
++ if(wps_ie)
++ _rtw_memcpy(wps_ie, &in_ie[cnt], in_ie[cnt+1]+2);
++
++ if(wps_ielen)
++ *wps_ielen = in_ie[cnt+1]+2;
++
++ cnt+=in_ie[cnt+1]+2;
++
++ break;
++ }
++ else
++ {
++ cnt+=in_ie[cnt+1]+2; //goto next
++ }
++
++ }
++
++ return wpsie_ptr;
++}
++
++/**
++ * rtw_get_wps_attr - Search a specific WPS attribute from a given WPS IE
++ * @wps_ie: Address of WPS IE to search
++ * @wps_ielen: Length limit from wps_ie
++ * @target_attr_id: The attribute ID of WPS attribute to search
++ * @buf_attr: If not NULL and the WPS attribute is found, WPS attribute will be copied to the buf starting from buf_attr
++ * @len_attr: If not NULL and the WPS attribute is found, will set to the length of the entire WPS attribute
++ *
++ * Returns: the address of the specific WPS attribute found, or NULL
++ */
++u8 *rtw_get_wps_attr(u8 *wps_ie, uint wps_ielen, u16 target_attr_id ,u8 *buf_attr, u32 *len_attr)
++{
++ u8 *attr_ptr = NULL;
++ u8 * target_attr_ptr = NULL;
++ u8 wps_oui[4]={0x00,0x50,0xF2,0x04};
++
++ if(len_attr)
++ *len_attr = 0;
++
++ if ( ( wps_ie[0] != _VENDOR_SPECIFIC_IE_ ) ||
++ ( _rtw_memcmp( wps_ie + 2, wps_oui , 4 ) != _TRUE ) )
++ {
++ return attr_ptr;
++ }
++
++ // 6 = 1(Element ID) + 1(Length) + 4(WPS OUI)
++ attr_ptr = wps_ie + 6; //goto first attr
++
++ while(attr_ptr - wps_ie < wps_ielen)
++ {
++ // 4 = 2(Attribute ID) + 2(Length)
++ u16 attr_id = RTW_GET_BE16(attr_ptr);
++ u16 attr_data_len = RTW_GET_BE16(attr_ptr + 2);
++ u16 attr_len = attr_data_len + 4;
++
++ //DBG_871X("%s attr_ptr:%p, id:%u, length:%u\n", __FUNCTION__, attr_ptr, attr_id, attr_data_len);
++ if( attr_id == target_attr_id )
++ {
++ target_attr_ptr = attr_ptr;
++
++ if(buf_attr)
++ _rtw_memcpy(buf_attr, attr_ptr, attr_len);
++
++ if(len_attr)
++ *len_attr = attr_len;
++
++ break;
++ }
++ else
++ {
++ attr_ptr += attr_len; //goto next
++ }
++
++ }
++
++ return target_attr_ptr;
++}
++
++/**
++ * rtw_get_wps_attr_content - Search a specific WPS attribute content from a given WPS IE
++ * @wps_ie: Address of WPS IE to search
++ * @wps_ielen: Length limit from wps_ie
++ * @target_attr_id: The attribute ID of WPS attribute to search
++ * @buf_content: If not NULL and the WPS attribute is found, WPS attribute content will be copied to the buf starting from buf_content
++ * @len_content: If not NULL and the WPS attribute is found, will set to the length of the WPS attribute content
++ *
++ * Returns: the address of the specific WPS attribute content found, or NULL
++ */
++u8 *rtw_get_wps_attr_content(u8 *wps_ie, uint wps_ielen, u16 target_attr_id ,u8 *buf_content, uint *len_content)
++{
++ u8 *attr_ptr;
++ u32 attr_len;
++
++ if(len_content)
++ *len_content = 0;
++
++ attr_ptr = rtw_get_wps_attr(wps_ie, wps_ielen, target_attr_id, NULL, &attr_len);
++
++ if(attr_ptr && attr_len)
++ {
++ if(buf_content)
++ _rtw_memcpy(buf_content, attr_ptr+4, attr_len-4);
++
++ if(len_content)
++ *len_content = attr_len-4;
++
++ return attr_ptr+4;
++ }
++
++ return NULL;
++}
++
++static int rtw_ieee802_11_parse_vendor_specific(u8 *pos, uint elen,
++ struct rtw_ieee802_11_elems *elems,
++ int show_errors)
++{
++ unsigned int oui;
++
++ /* first 3 bytes in vendor specific information element are the IEEE
++ * OUI of the vendor. The following byte is used a vendor specific
++ * sub-type. */
++ if (elen < 4) {
++ if (show_errors) {
++ DBG_871X("short vendor specific "
++ "information element ignored (len=%lu)\n",
++ (unsigned long) elen);
++ }
++ return -1;
++ }
++
++ oui = RTW_GET_BE24(pos);
++ switch (oui) {
++ case OUI_MICROSOFT:
++ /* Microsoft/Wi-Fi information elements are further typed and
++ * subtyped */
++ switch (pos[3]) {
++ case 1:
++ /* Microsoft OUI (00:50:F2) with OUI Type 1:
++ * real WPA information element */
++ elems->wpa_ie = pos;
++ elems->wpa_ie_len = elen;
++ break;
++ case WME_OUI_TYPE: /* this is a Wi-Fi WME info. element */
++ if (elen < 5) {
++ DBG_871X("short WME "
++ "information element ignored "
++ "(len=%lu)\n",
++ (unsigned long) elen);
++ return -1;
++ }
++ switch (pos[4]) {
++ case WME_OUI_SUBTYPE_INFORMATION_ELEMENT:
++ case WME_OUI_SUBTYPE_PARAMETER_ELEMENT:
++ elems->wme = pos;
++ elems->wme_len = elen;
++ break;
++ case WME_OUI_SUBTYPE_TSPEC_ELEMENT:
++ elems->wme_tspec = pos;
++ elems->wme_tspec_len = elen;
++ break;
++ default:
++ DBG_871X("unknown WME "
++ "information element ignored "
++ "(subtype=%d len=%lu)\n",
++ pos[4], (unsigned long) elen);
++ return -1;
++ }
++ break;
++ case 4:
++ /* Wi-Fi Protected Setup (WPS) IE */
++ elems->wps_ie = pos;
++ elems->wps_ie_len = elen;
++ break;
++ default:
++ DBG_871X("Unknown Microsoft "
++ "information element ignored "
++ "(type=%d len=%lu)\n",
++ pos[3], (unsigned long) elen);
++ return -1;
++ }
++ break;
++
++ case OUI_BROADCOM:
++ switch (pos[3]) {
++ case VENDOR_HT_CAPAB_OUI_TYPE:
++ elems->vendor_ht_cap = pos;
++ elems->vendor_ht_cap_len = elen;
++ break;
++ default:
++ DBG_871X("Unknown Broadcom "
++ "information element ignored "
++ "(type=%d len=%lu)\n",
++ pos[3], (unsigned long) elen);
++ return -1;
++ }
++ break;
++
++ default:
++ DBG_871X("unknown vendor specific information "
++ "element ignored (vendor OUI %02x:%02x:%02x "
++ "len=%lu)\n",
++ pos[0], pos[1], pos[2], (unsigned long) elen);
++ return -1;
++ }
++
++ return 0;
++
++}
++
++/**
++ * ieee802_11_parse_elems - Parse information elements in management frames
++ * @start: Pointer to the start of IEs
++ * @len: Length of IE buffer in octets
++ * @elems: Data structure for parsed elements
++ * @show_errors: Whether to show parsing errors in debug log
++ * Returns: Parsing result
++ */
++ParseRes rtw_ieee802_11_parse_elems(u8 *start, uint len,
++ struct rtw_ieee802_11_elems *elems,
++ int show_errors)
++{
++ uint left = len;
++ u8 *pos = start;
++ int unknown = 0;
++
++ _rtw_memset(elems, 0, sizeof(*elems));
++
++ while (left >= 2) {
++ u8 id, elen;
++
++ id = *pos++;
++ elen = *pos++;
++ left -= 2;
++
++ if (elen > left) {
++ if (show_errors) {
++ DBG_871X("IEEE 802.11 element "
++ "parse failed (id=%d elen=%d "
++ "left=%lu)\n",
++ id, elen, (unsigned long) left);
++ }
++ return ParseFailed;
++ }
++
++ switch (id) {
++ case WLAN_EID_SSID:
++ elems->ssid = pos;
++ elems->ssid_len = elen;
++ break;
++ case WLAN_EID_SUPP_RATES:
++ elems->supp_rates = pos;
++ elems->supp_rates_len = elen;
++ break;
++ case WLAN_EID_FH_PARAMS:
++ elems->fh_params = pos;
++ elems->fh_params_len = elen;
++ break;
++ case WLAN_EID_DS_PARAMS:
++ elems->ds_params = pos;
++ elems->ds_params_len = elen;
++ break;
++ case WLAN_EID_CF_PARAMS:
++ elems->cf_params = pos;
++ elems->cf_params_len = elen;
++ break;
++ case WLAN_EID_TIM:
++ elems->tim = pos;
++ elems->tim_len = elen;
++ break;
++ case WLAN_EID_IBSS_PARAMS:
++ elems->ibss_params = pos;
++ elems->ibss_params_len = elen;
++ break;
++ case WLAN_EID_CHALLENGE:
++ elems->challenge = pos;
++ elems->challenge_len = elen;
++ break;
++ case WLAN_EID_ERP_INFO:
++ elems->erp_info = pos;
++ elems->erp_info_len = elen;
++ break;
++ case WLAN_EID_EXT_SUPP_RATES:
++ elems->ext_supp_rates = pos;
++ elems->ext_supp_rates_len = elen;
++ break;
++ case WLAN_EID_VENDOR_SPECIFIC:
++ if (rtw_ieee802_11_parse_vendor_specific(pos, elen,
++ elems,
++ show_errors))
++ unknown++;
++ break;
++ case WLAN_EID_RSN:
++ elems->rsn_ie = pos;
++ elems->rsn_ie_len = elen;
++ break;
++ case WLAN_EID_PWR_CAPABILITY:
++ elems->power_cap = pos;
++ elems->power_cap_len = elen;
++ break;
++ case WLAN_EID_SUPPORTED_CHANNELS:
++ elems->supp_channels = pos;
++ elems->supp_channels_len = elen;
++ break;
++ case WLAN_EID_MOBILITY_DOMAIN:
++ elems->mdie = pos;
++ elems->mdie_len = elen;
++ break;
++ case WLAN_EID_FAST_BSS_TRANSITION:
++ elems->ftie = pos;
++ elems->ftie_len = elen;
++ break;
++ case WLAN_EID_TIMEOUT_INTERVAL:
++ elems->timeout_int = pos;
++ elems->timeout_int_len = elen;
++ break;
++ case WLAN_EID_HT_CAP:
++ elems->ht_capabilities = pos;
++ elems->ht_capabilities_len = elen;
++ break;
++ case WLAN_EID_HT_OPERATION:
++ elems->ht_operation = pos;
++ elems->ht_operation_len = elen;
++ break;
++ default:
++ unknown++;
++ if (!show_errors)
++ break;
++ DBG_871X("IEEE 802.11 element parse "
++ "ignored unknown element (id=%d elen=%d)\n",
++ id, elen);
++ break;
++ }
++
++ left -= elen;
++ pos += elen;
++ }
++
++ if (left)
++ return ParseFailed;
++
++ return unknown ? ParseUnknown : ParseOK;
++
++}
++
++static u8 key_char2num(u8 ch);
++static u8 key_char2num(u8 ch)
++{
++ if((ch>='0')&&(ch<='9'))
++ return ch - '0';
++ else if ((ch>='a')&&(ch<='f'))
++ return ch - 'a' + 10;
++ else if ((ch>='A')&&(ch<='F'))
++ return ch - 'A' + 10;
++ else
++ return 0xff;
++}
++
++u8 str_2char2num(u8 hch, u8 lch);
++u8 str_2char2num(u8 hch, u8 lch)
++{
++ return ((key_char2num(hch) * 10 ) + key_char2num(lch));
++}
++
++u8 key_2char2num(u8 hch, u8 lch);
++u8 key_2char2num(u8 hch, u8 lch)
++{
++ return ((key_char2num(hch) << 4) | key_char2num(lch));
++}
++
++u8 convert_ip_addr(u8 hch, u8 mch, u8 lch)
++{
++ return ((key_char2num(hch) * 100) + (key_char2num(mch) * 10 ) + key_char2num(lch));
++}
++
++extern char* rtw_initmac;
++void rtw_macaddr_cfg(u8 *mac_addr)
++{
++ u8 mac[ETH_ALEN];
++ if(mac_addr == NULL) return;
++
++ if ( rtw_initmac )
++ { // Users specify the mac address
++ int jj,kk;
++
++ for( jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3 )
++ {
++ mac[jj] = key_2char2num(rtw_initmac[kk], rtw_initmac[kk+ 1]);
++ }
++ _rtw_memcpy(mac_addr, mac, ETH_ALEN);
++ }
++ else
++ { // Use the mac address stored in the Efuse
++ _rtw_memcpy(mac, mac_addr, ETH_ALEN);
++ }
++
++ if (((mac[0]==0xff) &&(mac[1]==0xff) && (mac[2]==0xff) &&
++ (mac[3]==0xff) && (mac[4]==0xff) &&(mac[5]==0xff)) ||
++ ((mac[0]==0x0) && (mac[1]==0x0) && (mac[2]==0x0) &&
++ (mac[3]==0x0) && (mac[4]==0x0) &&(mac[5]==0x0)))
++ {
++ mac[0] = 0x00;
++ mac[1] = 0xe0;
++ mac[2] = 0x4c;
++ mac[3] = 0x87;
++ mac[4] = 0x00;
++ mac[5] = 0x00;
++ // use default mac addresss
++ _rtw_memcpy(mac_addr, mac, ETH_ALEN);
++ DBG_871X("MAC Address from efuse error, assign default one !!!\n");
++ }
++
++ DBG_871X("rtw_macaddr_cfg MAC Address = "MAC_FMT"\n", MAC_ARG(mac_addr));
++}
++
++void dump_ies(u8 *buf, u32 buf_len) {
++ u8* pos = (u8*)buf;
++ u8 id, len;
++
++ while(pos-buf<=buf_len){
++ id = *pos;
++ len = *(pos+1);
++
++ DBG_871X("%s ID:%u, LEN:%u\n", __FUNCTION__, id, len);
++ #ifdef CONFIG_P2P
++ dump_p2p_ie(pos, len);
++ #endif
++ dump_wps_ie(pos, len);
++
++ pos+=(2+len);
++ }
++}
++
++void dump_wps_ie(u8 *ie, u32 ie_len) {
++ u8* pos = (u8*)ie;
++ u16 id;
++ u16 len;
++
++ u8 *wps_ie;
++ uint wps_ielen;
++
++ wps_ie = rtw_get_wps_ie(ie, ie_len, NULL, &wps_ielen);
++ if(wps_ie != ie || wps_ielen == 0)
++ return;
++
++ pos+=6;
++ while(pos-ie < ie_len){
++ id = RTW_GET_BE16(pos);
++ len = RTW_GET_BE16(pos + 2);
++
++ DBG_871X("%s ID:0x%04x, LEN:%u\n", __FUNCTION__, id, len);
++
++ pos+=(4+len);
++ }
++}
++
++#ifdef CONFIG_P2P
++/**
++ * rtw_get_p2p_merged_len - Get merged ie length from muitiple p2p ies.
++ * @in_ie: Pointer of the first p2p ie
++ * @in_len: Total len of muiltiple p2p ies
++ * Returns: Length of merged p2p ie length
++ */
++u32 rtw_get_p2p_merged_ies_len(u8 *in_ie, u32 in_len)
++{
++ PNDIS_802_11_VARIABLE_IEs pIE;
++ u8 OUI[4] = { 0x50, 0x6f, 0x9a, 0x09 };
++ int i=0;
++ int j=0, len=0;
++
++ while( i < in_len)
++ {
++ pIE = (PNDIS_802_11_VARIABLE_IEs)(in_ie+ i);
++
++ if( pIE->ElementID == _VENDOR_SPECIFIC_IE_ && _rtw_memcmp(pIE->data, OUI, 4) )
++ {
++ len += pIE->Length-4; // 4 is P2P OUI length, don't count it in this loop
++ }
++
++ i += (pIE->Length + 2);
++ }
++
++ return len + 4; // Append P2P OUI length at last.
++}
++
++/**
++ * rtw_p2p_merge_ies - Merge muitiple p2p ies into one
++ * @in_ie: Pointer of the first p2p ie
++ * @in_len: Total len of muiltiple p2p ies
++ * @merge_ie: Pointer of merged ie
++ * Returns: Length of merged p2p ie
++ */
++int rtw_p2p_merge_ies(u8 *in_ie, u32 in_len, u8 *merge_ie)
++{
++ PNDIS_802_11_VARIABLE_IEs pIE;
++ u8 len = 0;
++ u8 OUI[4] = { 0x50, 0x6f, 0x9a, 0x09 };
++ u8 ELOUI[6] = { 0xDD, 0x00, 0x50, 0x6f, 0x9a, 0x09 }; //EID;Len;OUI, Len would copy at the end of function
++ int i=0;
++
++ if( merge_ie != NULL)
++ {
++ //Set first P2P OUI
++ _rtw_memcpy(merge_ie, ELOUI, 6);
++ merge_ie += 6;
++
++ while( i < in_len)
++ {
++ pIE = (PNDIS_802_11_VARIABLE_IEs)(in_ie+ i);
++
++ // Take out the rest of P2P OUIs
++ if( pIE->ElementID == _VENDOR_SPECIFIC_IE_ && _rtw_memcmp(pIE->data, OUI, 4) )
++ {
++ _rtw_memcpy( merge_ie, pIE->data +4, pIE->Length -4);
++ len += pIE->Length-4;
++ merge_ie += pIE->Length-4;
++ }
++
++ i += (pIE->Length + 2);
++ }
++
++ return len + 4; // 4 is for P2P OUI
++
++ }
++
++ return 0;
++}
++
++void dump_p2p_ie(u8 *ie, u32 ie_len) {
++ u8* pos = (u8*)ie;
++ u8 id;
++ u16 len;
++
++ u8 *p2p_ie;
++ uint p2p_ielen;
++
++ p2p_ie = rtw_get_p2p_ie(ie, ie_len, NULL, &p2p_ielen);
++ if(p2p_ie != ie || p2p_ielen == 0)
++ return;
++
++ pos+=6;
++ while(pos-ie < ie_len){
++ id = *pos;
++ len = RTW_GET_LE16(pos+1);
++
++ DBG_871X("%s ID:%u, LEN:%u\n", __FUNCTION__, id, len);
++
++ pos+=(3+len);
++ }
++}
++
++/**
++ * rtw_get_p2p_ie - Search P2P IE from a series of IEs
++ * @in_ie: Address of IEs to search
++ * @in_len: Length limit from in_ie
++ * @p2p_ie: If not NULL and P2P IE is found, P2P IE will be copied to the buf starting from p2p_ie
++ * @p2p_ielen: If not NULL and P2P IE is found, will set to the length of the entire P2P IE
++ *
++ * Returns: The address of the P2P IE found, or NULL
++ */
++u8 *rtw_get_p2p_ie(u8 *in_ie, int in_len, u8 *p2p_ie, uint *p2p_ielen)
++{
++ uint cnt = 0;
++ u8 *p2p_ie_ptr;
++ u8 eid, p2p_oui[4]={0x50,0x6F,0x9A,0x09};
++
++ if ( p2p_ielen != NULL )
++ *p2p_ielen = 0;
++
++ while(cnt<in_len)
++ {
++ eid = in_ie[cnt];
++ if ((in_len < 0) || (cnt > MAX_IE_SZ)) {
++#ifdef PLATFORM_LINUX
++ dump_stack();
++#endif
++ return NULL;
++ }
++ if( ( eid == _VENDOR_SPECIFIC_IE_ ) && ( _rtw_memcmp( &in_ie[cnt+2], p2p_oui, 4) == _TRUE ) )
++ {
++ p2p_ie_ptr = in_ie + cnt;
++
++ if ( p2p_ie != NULL )
++ {
++ _rtw_memcpy( p2p_ie, &in_ie[ cnt ], in_ie[ cnt + 1 ] + 2 );
++ }
++
++ if ( p2p_ielen != NULL )
++ {
++ *p2p_ielen = in_ie[ cnt + 1 ] + 2;
++ }
++
++ return p2p_ie_ptr;
++
++ break;
++ }
++ else
++ {
++ cnt += in_ie[ cnt + 1 ] +2; //goto next
++ }
++
++ }
++
++ return NULL;
++
++}
++
++/**
++ * rtw_get_p2p_attr - Search a specific P2P attribute from a given P2P IE
++ * @p2p_ie: Address of P2P IE to search
++ * @p2p_ielen: Length limit from p2p_ie
++ * @target_attr_id: The attribute ID of P2P attribute to search
++ * @buf_attr: If not NULL and the P2P attribute is found, P2P attribute will be copied to the buf starting from buf_attr
++ * @len_attr: If not NULL and the P2P attribute is found, will set to the length of the entire P2P attribute
++ *
++ * Returns: the address of the specific WPS attribute found, or NULL
++ */
++u8 *rtw_get_p2p_attr(u8 *p2p_ie, uint p2p_ielen, u8 target_attr_id ,u8 *buf_attr, u32 *len_attr)
++{
++ u8 *attr_ptr = NULL;
++ u8 *target_attr_ptr = NULL;
++ u8 p2p_oui[4]={0x50,0x6F,0x9A,0x09};
++
++ if(len_attr)
++ *len_attr = 0;
++
++ if ( !p2p_ie || ( p2p_ie[0] != _VENDOR_SPECIFIC_IE_ ) ||
++ ( _rtw_memcmp( p2p_ie + 2, p2p_oui , 4 ) != _TRUE ) )
++ {
++ return attr_ptr;
++ }
++
++ // 6 = 1(Element ID) + 1(Length) + 3 (OUI) + 1(OUI Type)
++ attr_ptr = p2p_ie + 6; //goto first attr
++
++ while(attr_ptr - p2p_ie < p2p_ielen)
++ {
++ // 3 = 1(Attribute ID) + 2(Length)
++ u8 attr_id = *attr_ptr;
++ u16 attr_data_len = RTW_GET_LE16(attr_ptr + 1);
++ u16 attr_len = attr_data_len + 3;
++
++ //DBG_871X("%s attr_ptr:%p, id:%u, length:%u\n", __FUNCTION__, attr_ptr, attr_id, attr_data_len);
++ if( attr_id == target_attr_id )
++ {
++ target_attr_ptr = attr_ptr;
++
++ if(buf_attr)
++ _rtw_memcpy(buf_attr, attr_ptr, attr_len);
++
++ if(len_attr)
++ *len_attr = attr_len;
++
++ break;
++ }
++ else
++ {
++ attr_ptr += attr_len; //goto next
++ }
++
++ }
++
++ return target_attr_ptr;
++}
++
++/**
++ * rtw_get_p2p_attr_content - Search a specific P2P attribute content from a given P2P IE
++ * @p2p_ie: Address of P2P IE to search
++ * @p2p_ielen: Length limit from p2p_ie
++ * @target_attr_id: The attribute ID of P2P attribute to search
++ * @buf_content: If not NULL and the P2P attribute is found, P2P attribute content will be copied to the buf starting from buf_content
++ * @len_content: If not NULL and the P2P attribute is found, will set to the length of the P2P attribute content
++ *
++ * Returns: the address of the specific P2P attribute content found, or NULL
++ */
++u8 *rtw_get_p2p_attr_content(u8 *p2p_ie, uint p2p_ielen, u8 target_attr_id ,u8 *buf_content, uint *len_content)
++{
++ u8 *attr_ptr;
++ u32 attr_len;
++
++ if(len_content)
++ *len_content = 0;
++
++ attr_ptr = rtw_get_p2p_attr(p2p_ie, p2p_ielen, target_attr_id, NULL, &attr_len);
++
++ if(attr_ptr && attr_len)
++ {
++ if(buf_content)
++ _rtw_memcpy(buf_content, attr_ptr+3, attr_len-3);
++
++ if(len_content)
++ *len_content = attr_len-3;
++
++ return attr_ptr+3;
++ }
++
++ return NULL;
++}
++
++u32 rtw_set_p2p_attr_content(u8 *pbuf, u8 attr_id, u16 attr_len, u8 *pdata_attr)
++{
++ u32 a_len;
++
++ *pbuf = attr_id;
++
++ //*(u16*)(pbuf + 1) = cpu_to_le16(attr_len);
++ RTW_PUT_LE16(pbuf + 1, attr_len);
++
++ if(pdata_attr)
++ _rtw_memcpy(pbuf + 3, pdata_attr, attr_len);
++
++ a_len = attr_len + 3;
++
++ return a_len;
++}
++
++static uint rtw_p2p_attr_remove(u8 *ie, uint ielen_ori, u8 attr_id)
++{
++ u8 *target_attr;
++ u32 target_attr_len;
++ uint ielen = ielen_ori;
++ int index=0;
++
++ while(1) {
++ target_attr=rtw_get_p2p_attr(ie, ielen, attr_id, NULL, &target_attr_len);
++ if(target_attr && target_attr_len)
++ {
++ u8 *next_attr = target_attr+target_attr_len;
++ uint remain_len = ielen-(next_attr-ie);
++ //dump_ies(ie, ielen);
++ #if 0
++ DBG_871X("[%d] ie:%p, ielen:%u\n"
++ "target_attr:%p, target_attr_len:%u\n"
++ "next_attr:%p, remain_len:%u\n"
++ , index++
++ , ie, ielen
++ , target_attr, target_attr_len
++ , next_attr, remain_len
++ );
++ #endif
++
++ _rtw_memset(target_attr, 0, target_attr_len);
++ _rtw_memcpy(target_attr, next_attr, remain_len);
++ _rtw_memset(target_attr+remain_len, 0, target_attr_len);
++ *(ie+1) -= target_attr_len;
++ ielen-=target_attr_len;
++ }
++ else
++ {
++ //if(index>0)
++ // dump_ies(ie, ielen);
++ break;
++ }
++ }
++
++ return ielen;
++}
++
++void rtw_WLAN_BSSID_EX_remove_p2p_attr(WLAN_BSSID_EX *bss_ex, u8 attr_id)
++{
++ u8 *p2p_ie;
++ uint p2p_ielen, p2p_ielen_ori;
++ int cnt;
++
++ if( (p2p_ie=rtw_get_p2p_ie(bss_ex->IEs+_FIXED_IE_LENGTH_, bss_ex->IELength-_FIXED_IE_LENGTH_, NULL, &p2p_ielen_ori)) )
++ {
++ #if 0
++ if(rtw_get_p2p_attr(p2p_ie, p2p_ielen_ori, attr_id, NULL, NULL)) {
++ DBG_871X("rtw_get_p2p_attr: GOT P2P_ATTR:%u!!!!!!!!\n", attr_id);
++ dump_ies(bss_ex->IEs+_FIXED_IE_LENGTH_, bss_ex->IELength-_FIXED_IE_LENGTH_);
++ }
++ #endif
++
++ p2p_ielen=rtw_p2p_attr_remove(p2p_ie, p2p_ielen_ori, attr_id);
++ if(p2p_ielen != p2p_ielen_ori) {
++
++ u8 *next_ie_ori = p2p_ie+p2p_ielen_ori;
++ u8 *next_ie = p2p_ie+p2p_ielen;
++ uint remain_len = bss_ex->IELength-(next_ie_ori-bss_ex->IEs);
++
++ _rtw_memcpy(next_ie, next_ie_ori, remain_len);
++ _rtw_memset(next_ie+remain_len, 0, p2p_ielen_ori-p2p_ielen);
++ bss_ex->IELength -= p2p_ielen_ori-p2p_ielen;
++
++ #if 0
++ DBG_871X("remove P2P_ATTR:%u!\n", attr_id);
++ dump_ies(bss_ex->IEs+_FIXED_IE_LENGTH_, bss_ex->IELength-_FIXED_IE_LENGTH_);
++ #endif
++ }
++ }
++}
++
++#endif //CONFIG_P2P
++
++#ifdef CONFIG_WFD
++int rtw_get_wfd_ie(u8 *in_ie, int in_len, u8 *wfd_ie, uint *wfd_ielen)
++{
++ int match;
++ uint cnt = 0;
++ u8 eid, wfd_oui[4]={0x50,0x6F,0x9A,0x0A};
++
++
++ match=_FALSE;
++
++ if ( in_len < 0 )
++ {
++ return match;
++ }
++
++ while(cnt<in_len)
++ {
++ eid = in_ie[cnt];
++
++ if( ( eid == _VENDOR_SPECIFIC_IE_ ) && ( _rtw_memcmp( &in_ie[cnt+2], wfd_oui, 4) == _TRUE ) )
++ {
++ if ( wfd_ie != NULL )
++ {
++ _rtw_memcpy( wfd_ie, &in_ie[ cnt ], in_ie[ cnt + 1 ] + 2 );
++
++ }
++ else
++ {
++ if ( wfd_ielen != NULL )
++ {
++ *wfd_ielen = 0;
++ }
++ }
++
++ if ( wfd_ielen != NULL )
++ {
++ *wfd_ielen = in_ie[ cnt + 1 ] + 2;
++ }
++
++ cnt += in_ie[ cnt + 1 ] + 2;
++
++ match = _TRUE;
++ break;
++ }
++ else
++ {
++ cnt += in_ie[ cnt + 1 ] +2; //goto next
++ }
++
++ }
++
++ if ( match == _TRUE )
++ {
++ match = cnt;
++ }
++
++ return match;
++
++}
++
++// attr_content: The output buffer, contains the "body field" of WFD attribute.
++// attr_contentlen: The data length of the "body field" of WFD attribute.
++int rtw_get_wfd_attr_content(u8 *wfd_ie, uint wfd_ielen, u8 target_attr_id ,u8 *attr_content, uint *attr_contentlen)
++{
++ int match;
++ uint cnt = 0;
++ u8 attr_id, wfd_oui[4]={0x50,0x6F,0x9A,0x0A};
++
++
++ match=_FALSE;
++
++ if ( ( wfd_ie[ 0 ] != _VENDOR_SPECIFIC_IE_ ) ||
++ ( _rtw_memcmp( wfd_ie + 2, wfd_oui , 4 ) != _TRUE ) )
++ {
++ return( match );
++ }
++
++ // 1 ( WFD IE ) + 1 ( Length ) + 3 ( OUI ) + 1 ( OUI Type )
++ cnt = 6;
++ while( cnt < wfd_ielen )
++ {
++ u16 attrlen = RTW_GET_BE16(wfd_ie + cnt + 1);
++
++ attr_id = wfd_ie[cnt];
++ if( attr_id == target_attr_id )
++ {
++ // 3 -> 1 byte for attribute ID field, 2 bytes for length field
++ if(attr_content)
++ _rtw_memcpy( attr_content, &wfd_ie[ cnt + 3 ], attrlen );
++
++ if(attr_contentlen)
++ *attr_contentlen = attrlen;
++
++ cnt += attrlen + 3;
++
++ match = _TRUE;
++ break;
++ }
++ else
++ {
++ cnt += attrlen + 3; //goto next
++ }
++
++ }
++
++ return match;
++
++}
++#endif // CONFIG_WFD
++
++//Baron adds to avoid FreeBSD warning
++int ieee80211_is_empty_essid(const char *essid, int essid_len)
++{
++ /* Single white space is for Linksys APs */
++ if (essid_len == 1 && essid[0] == ' ')
++ return 1;
++
++ /* Otherwise, if the entire essid is 0, we assume it is hidden */
++ while (essid_len) {
++ essid_len--;
++ if (essid[essid_len] != '\0')
++ return 0;
++ }
++
++ return 1;
++}
++
++int ieee80211_get_hdrlen(u16 fc)
++{
++ int hdrlen = 24;
++
++ switch (WLAN_FC_GET_TYPE(fc)) {
++ case RTW_IEEE80211_FTYPE_DATA:
++ if (fc & RTW_IEEE80211_STYPE_QOS_DATA)
++ hdrlen += 2;
++ if ((fc & RTW_IEEE80211_FCTL_FROMDS) && (fc & RTW_IEEE80211_FCTL_TODS))
++ hdrlen += 6; /* Addr4 */
++ break;
++ case RTW_IEEE80211_FTYPE_CTL:
++ switch (WLAN_FC_GET_STYPE(fc)) {
++ case RTW_IEEE80211_STYPE_CTS:
++ case RTW_IEEE80211_STYPE_ACK:
++ hdrlen = 10;
++ break;
++ default:
++ hdrlen = 16;
++ break;
++ }
++ break;
++ }
++
++ return hdrlen;
++}
++
++//show MCS rate, unit: 100Kbps
++u16 rtw_mcs_rate(u8 rf_type, u8 bw_40MHz, u8 short_GI_20, u8 short_GI_40, unsigned char * MCS_rate)
++{
++ u16 max_rate = 0;
++
++ if(rf_type == RF_1T1R)
++ {
++ if(MCS_rate[0] & BIT(7))
++ max_rate = (bw_40MHz) ? ((short_GI_40)?1500:1350):((short_GI_20)?722:650);
++ else if(MCS_rate[0] & BIT(6))
++ max_rate = (bw_40MHz) ? ((short_GI_40)?1350:1215):((short_GI_20)?650:585);
++ else if(MCS_rate[0] & BIT(5))
++ max_rate = (bw_40MHz) ? ((short_GI_40)?1200:1080):((short_GI_20)?578:520);
++ else if(MCS_rate[0] & BIT(4))
++ max_rate = (bw_40MHz) ? ((short_GI_40)?900:810):((short_GI_20)?433:390);
++ else if(MCS_rate[0] & BIT(3))
++ max_rate = (bw_40MHz) ? ((short_GI_40)?600:540):((short_GI_20)?289:260);
++ else if(MCS_rate[0] & BIT(2))
++ max_rate = (bw_40MHz) ? ((short_GI_40)?450:405):((short_GI_20)?217:195);
++ else if(MCS_rate[0] & BIT(1))
++ max_rate = (bw_40MHz) ? ((short_GI_40)?300:270):((short_GI_20)?144:130);
++ else if(MCS_rate[0] & BIT(0))
++ max_rate = (bw_40MHz) ? ((short_GI_40)?150:135):((short_GI_20)?72:65);
++ }
++ else
++ {
++ if(MCS_rate[1])
++ {
++ if(MCS_rate[1] & BIT(7))
++ max_rate = (bw_40MHz) ? ((short_GI_40)?3000:2700):((short_GI_20)?1444:1300);
++ else if(MCS_rate[1] & BIT(6))
++ max_rate = (bw_40MHz) ? ((short_GI_40)?2700:2430):((short_GI_20)?1300:1170);
++ else if(MCS_rate[1] & BIT(5))
++ max_rate = (bw_40MHz) ? ((short_GI_40)?2400:2160):((short_GI_20)?1156:1040);
++ else if(MCS_rate[1] & BIT(4))
++ max_rate = (bw_40MHz) ? ((short_GI_40)?1800:1620):((short_GI_20)?867:780);
++ else if(MCS_rate[1] & BIT(3))
++ max_rate = (bw_40MHz) ? ((short_GI_40)?1200:1080):((short_GI_20)?578:520);
++ else if(MCS_rate[1] & BIT(2))
++ max_rate = (bw_40MHz) ? ((short_GI_40)?900:810):((short_GI_20)?433:390);
++ else if(MCS_rate[1] & BIT(1))
++ max_rate = (bw_40MHz) ? ((short_GI_40)?600:540):((short_GI_20)?289:260);
++ else if(MCS_rate[1] & BIT(0))
++ max_rate = (bw_40MHz) ? ((short_GI_40)?300:270):((short_GI_20)?144:130);
++ }
++ else
++ {
++ if(MCS_rate[0] & BIT(7))
++ max_rate = (bw_40MHz) ? ((short_GI_40)?1500:1350):((short_GI_20)?722:650);
++ else if(MCS_rate[0] & BIT(6))
++ max_rate = (bw_40MHz) ? ((short_GI_40)?1350:1215):((short_GI_20)?650:585);
++ else if(MCS_rate[0] & BIT(5))
++ max_rate = (bw_40MHz) ? ((short_GI_40)?1200:1080):((short_GI_20)?578:520);
++ else if(MCS_rate[0] & BIT(4))
++ max_rate = (bw_40MHz) ? ((short_GI_40)?900:810):((short_GI_20)?433:390);
++ else if(MCS_rate[0] & BIT(3))
++ max_rate = (bw_40MHz) ? ((short_GI_40)?600:540):((short_GI_20)?289:260);
++ else if(MCS_rate[0] & BIT(2))
++ max_rate = (bw_40MHz) ? ((short_GI_40)?450:405):((short_GI_20)?217:195);
++ else if(MCS_rate[0] & BIT(1))
++ max_rate = (bw_40MHz) ? ((short_GI_40)?300:270):((short_GI_20)?144:130);
++ else if(MCS_rate[0] & BIT(0))
++ max_rate = (bw_40MHz) ? ((short_GI_40)?150:135):((short_GI_20)?72:65);
++ }
++ }
++ return max_rate;
++}
++
++int rtw_action_frame_parse(const u8 *frame, u32 frame_len, u8* category, u8 *action)
++{
++ const u8 *frame_body = frame + sizeof(struct rtw_ieee80211_hdr_3addr);
++ u16 fc;
++ u8 c, a;
++
++ fc = le16_to_cpu(((struct rtw_ieee80211_hdr_3addr *)frame)->frame_ctl);
++
++ if ((fc & (RTW_IEEE80211_FCTL_FTYPE|RTW_IEEE80211_FCTL_STYPE))
++ != (RTW_IEEE80211_FTYPE_MGMT|RTW_IEEE80211_STYPE_ACTION)
++ )
++ {
++ return _FALSE;
++ }
++
++ c = frame_body[0];
++
++ switch(c) {
++ case RTW_WLAN_CATEGORY_P2P: /* vendor-specific */
++ break;
++ default:
++ a = frame_body[1];
++ }
++
++ if (category)
++ *category = c;
++ if (action)
++ *action = a;
++
++ return _TRUE;
++}
++
++static const char *_action_public_str[] = {
++ "ACT_PUB_BSSCOEXIST",
++ "ACT_PUB_DSE_ENABLE",
++ "ACT_PUB_DSE_DEENABLE",
++ "ACT_PUB_DSE_REG_LOCATION",
++ "ACT_PUB_EXT_CHL_SWITCH",
++ "ACT_PUB_DSE_MSR_REQ",
++ "ACT_PUB_DSE_MSR_RPRT",
++ "ACT_PUB_MP",
++ "ACT_PUB_DSE_PWR_CONSTRAINT",
++ "ACT_PUB_VENDOR",
++ "ACT_PUB_GAS_INITIAL_REQ",
++ "ACT_PUB_GAS_INITIAL_RSP",
++ "ACT_PUB_GAS_COMEBACK_REQ",
++ "ACT_PUB_GAS_COMEBACK_RSP",
++ "ACT_PUB_TDLS_DISCOVERY_RSP",
++ "ACT_PUB_LOCATION_TRACK",
++ "ACT_PUB_RSVD",
++};
++
++const char *action_public_str(u8 action)
++{
++ action = (action >= ACT_PUBLIC_MAX) ? ACT_PUBLIC_MAX : action;
++ return _action_public_str[action];
++}
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/core/rtw_io.c linux-xbian-rpi/drivers/net/wireless/rtl8192cu/core/rtw_io.c
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/core/rtw_io.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/core/rtw_io.c 2015-07-28 01:20:58.301668422 +0200
+@@ -0,0 +1,462 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++/*
++
++The purpose of rtw_io.c
++
++a. provides the API
++
++b. provides the protocol engine
++
++c. provides the software interface between caller and the hardware interface
++
++
++Compiler Flag Option:
++
++1. CONFIG_SDIO_HCI:
++ a. USE_SYNC_IRP: Only sync operations are provided.
++ b. USE_ASYNC_IRP:Both sync/async operations are provided.
++
++2. CONFIG_USB_HCI:
++ a. USE_ASYNC_IRP: Both sync/async operations are provided.
++
++3. CONFIG_CFIO_HCI:
++ b. USE_SYNC_IRP: Only sync operations are provided.
++
++
++Only sync read/rtw_write_mem operations are provided.
++
++jackson@realtek.com.tw
++
++*/
++
++#define _RTW_IO_C_
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++#include <rtw_io.h>
++#include <osdep_intf.h>
++
++#if defined (PLATFORM_LINUX) && defined (PLATFORM_WINDOWS)
++#error "Shall be Linux or Windows, but not both!\n"
++#endif
++
++#ifdef CONFIG_SDIO_HCI
++#include <sdio_ops.h>
++#endif
++
++#ifdef CONFIG_USB_HCI
++#include <usb_ops.h>
++#endif
++
++#ifdef CONFIG_PCI_HCI
++#include <pci_ops.h>
++#endif
++
++
++u8 _rtw_read8(_adapter *adapter, u32 addr)
++{
++ u8 r_val;
++ //struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
++ struct io_priv *pio_priv = &adapter->iopriv;
++ struct intf_hdl *pintfhdl = &(pio_priv->intf);
++ u8 (*_read8)(struct intf_hdl *pintfhdl, u32 addr);
++ _func_enter_;
++ _read8 = pintfhdl->io_ops._read8;
++
++ r_val = _read8(pintfhdl, addr);
++ _func_exit_;
++ return r_val;
++}
++
++u16 _rtw_read16(_adapter *adapter, u32 addr)
++{
++ u16 r_val;
++ //struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
++ struct io_priv *pio_priv = &adapter->iopriv;
++ struct intf_hdl *pintfhdl = &(pio_priv->intf);
++ u16 (*_read16)(struct intf_hdl *pintfhdl, u32 addr);
++ _func_enter_;
++ _read16 = pintfhdl->io_ops._read16;
++
++ r_val = _read16(pintfhdl, addr);
++ _func_exit_;
++ return r_val;
++}
++
++u32 _rtw_read32(_adapter *adapter, u32 addr)
++{
++ u32 r_val;
++ //struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
++ struct io_priv *pio_priv = &adapter->iopriv;
++ struct intf_hdl *pintfhdl = &(pio_priv->intf);
++ u32 (*_read32)(struct intf_hdl *pintfhdl, u32 addr);
++ _func_enter_;
++ _read32 = pintfhdl->io_ops._read32;
++
++ r_val = _read32(pintfhdl, addr);
++ _func_exit_;
++ return r_val;
++
++}
++
++int _rtw_write8(_adapter *adapter, u32 addr, u8 val)
++{
++ //struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
++ struct io_priv *pio_priv = &adapter->iopriv;
++ struct intf_hdl *pintfhdl = &(pio_priv->intf);
++ int (*_write8)(struct intf_hdl *pintfhdl, u32 addr, u8 val);
++ int ret;
++ _func_enter_;
++ _write8 = pintfhdl->io_ops._write8;
++
++ ret = _write8(pintfhdl, addr, val);
++ _func_exit_;
++
++ return RTW_STATUS_CODE(ret);
++}
++int _rtw_write16(_adapter *adapter, u32 addr, u16 val)
++{
++ //struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
++ struct io_priv *pio_priv = &adapter->iopriv;
++ struct intf_hdl *pintfhdl = &(pio_priv->intf);
++ int (*_write16)(struct intf_hdl *pintfhdl, u32 addr, u16 val);
++ int ret;
++ _func_enter_;
++ _write16 = pintfhdl->io_ops._write16;
++
++ ret = _write16(pintfhdl, addr, val);
++ _func_exit_;
++
++ return RTW_STATUS_CODE(ret);
++}
++int _rtw_write32(_adapter *adapter, u32 addr, u32 val)
++{
++ //struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
++ struct io_priv *pio_priv = &adapter->iopriv;
++ struct intf_hdl *pintfhdl = &(pio_priv->intf);
++ int (*_write32)(struct intf_hdl *pintfhdl, u32 addr, u32 val);
++ int ret;
++ _func_enter_;
++ _write32 = pintfhdl->io_ops._write32;
++
++ ret = _write32(pintfhdl, addr, val);
++ _func_exit_;
++
++ return RTW_STATUS_CODE(ret);
++}
++
++int _rtw_writeN(_adapter *adapter, u32 addr ,u32 length , u8 *pdata)
++{
++ //struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
++ struct io_priv *pio_priv = &adapter->iopriv;
++ struct intf_hdl *pintfhdl = (struct intf_hdl*)(&(pio_priv->intf));
++ int (*_writeN)(struct intf_hdl *pintfhdl, u32 addr,u32 length, u8 *pdata);
++ int ret;
++ _func_enter_;
++ _writeN = pintfhdl->io_ops._writeN;
++
++ ret = _writeN(pintfhdl, addr,length,pdata);
++ _func_exit_;
++
++ return RTW_STATUS_CODE(ret);
++}
++int _rtw_write8_async(_adapter *adapter, u32 addr, u8 val)
++{
++ //struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
++ struct io_priv *pio_priv = &adapter->iopriv;
++ struct intf_hdl *pintfhdl = &(pio_priv->intf);
++ int (*_write8_async)(struct intf_hdl *pintfhdl, u32 addr, u8 val);
++ int ret;
++ _func_enter_;
++ _write8_async = pintfhdl->io_ops._write8_async;
++
++ ret = _write8_async(pintfhdl, addr, val);
++ _func_exit_;
++
++ return RTW_STATUS_CODE(ret);
++}
++int _rtw_write16_async(_adapter *adapter, u32 addr, u16 val)
++{
++ //struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
++ struct io_priv *pio_priv = &adapter->iopriv;
++ struct intf_hdl *pintfhdl = &(pio_priv->intf);
++ int (*_write16_async)(struct intf_hdl *pintfhdl, u32 addr, u16 val);
++ int ret;
++ _func_enter_;
++ _write16_async = pintfhdl->io_ops._write16_async;
++
++ ret = _write16_async(pintfhdl, addr, val);
++ _func_exit_;
++
++ return RTW_STATUS_CODE(ret);
++}
++int _rtw_write32_async(_adapter *adapter, u32 addr, u32 val)
++{
++ //struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
++ struct io_priv *pio_priv = &adapter->iopriv;
++ struct intf_hdl *pintfhdl = &(pio_priv->intf);
++ int (*_write32_async)(struct intf_hdl *pintfhdl, u32 addr, u32 val);
++ int ret;
++ _func_enter_;
++ _write32_async = pintfhdl->io_ops._write32_async;
++
++ ret = _write32_async(pintfhdl, addr, val);
++ _func_exit_;
++
++ return RTW_STATUS_CODE(ret);
++}
++void _rtw_read_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem)
++{
++ void (*_read_mem)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
++ //struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
++ struct io_priv *pio_priv = &adapter->iopriv;
++ struct intf_hdl *pintfhdl = &(pio_priv->intf);
++
++ _func_enter_;
++
++ if( (adapter->bDriverStopped ==_TRUE) || (adapter->bSurpriseRemoved == _TRUE))
++ {
++ RT_TRACE(_module_rtl871x_io_c_, _drv_info_, ("rtw_read_mem:bDriverStopped(%d) OR bSurpriseRemoved(%d)", adapter->bDriverStopped, adapter->bSurpriseRemoved));
++ return;
++ }
++
++ _read_mem = pintfhdl->io_ops._read_mem;
++
++ _read_mem(pintfhdl, addr, cnt, pmem);
++
++ _func_exit_;
++
++}
++
++void _rtw_write_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem)
++{
++ void (*_write_mem)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
++ //struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
++ struct io_priv *pio_priv = &adapter->iopriv;
++ struct intf_hdl *pintfhdl = &(pio_priv->intf);
++
++ _func_enter_;
++
++ _write_mem = pintfhdl->io_ops._write_mem;
++
++ _write_mem(pintfhdl, addr, cnt, pmem);
++
++ _func_exit_;
++
++}
++
++void _rtw_read_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem)
++{
++ u32 (*_read_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
++ //struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
++ struct io_priv *pio_priv = &adapter->iopriv;
++ struct intf_hdl *pintfhdl = &(pio_priv->intf);
++
++ _func_enter_;
++
++ if( (adapter->bDriverStopped ==_TRUE) || (adapter->bSurpriseRemoved == _TRUE))
++ {
++ RT_TRACE(_module_rtl871x_io_c_, _drv_info_, ("rtw_read_port:bDriverStopped(%d) OR bSurpriseRemoved(%d)", adapter->bDriverStopped, adapter->bSurpriseRemoved));
++ return;
++ }
++
++ _read_port = pintfhdl->io_ops._read_port;
++
++ _read_port(pintfhdl, addr, cnt, pmem);
++
++ _func_exit_;
++
++}
++
++void _rtw_read_port_cancel(_adapter *adapter)
++{
++ void (*_read_port_cancel)(struct intf_hdl *pintfhdl);
++ struct io_priv *pio_priv = &adapter->iopriv;
++ struct intf_hdl *pintfhdl = &(pio_priv->intf);
++
++ _read_port_cancel = pintfhdl->io_ops._read_port_cancel;
++
++ if(_read_port_cancel)
++ _read_port_cancel(pintfhdl);
++
++}
++
++u32 _rtw_write_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem)
++{
++ u32 (*_write_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
++ //struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
++ struct io_priv *pio_priv = &adapter->iopriv;
++ struct intf_hdl *pintfhdl = &(pio_priv->intf);
++ u32 ret = _SUCCESS;
++
++ _func_enter_;
++
++ _write_port = pintfhdl->io_ops._write_port;
++
++ ret = _write_port(pintfhdl, addr, cnt, pmem);
++
++ _func_exit_;
++
++ return ret;
++}
++
++u32 _rtw_write_port_and_wait(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem, int timeout_ms)
++{
++ int ret = _SUCCESS;
++ struct xmit_buf *pxmitbuf = (struct xmit_buf *)pmem;
++ struct submit_ctx sctx;
++
++ rtw_sctx_init(&sctx, timeout_ms);
++ pxmitbuf->sctx = &sctx;
++
++ ret = _rtw_write_port(adapter, addr, cnt, pmem);
++
++ if (ret == _SUCCESS)
++ ret = rtw_sctx_wait(&sctx);
++
++ return ret;
++}
++
++void _rtw_write_port_cancel(_adapter *adapter)
++{
++ void (*_write_port_cancel)(struct intf_hdl *pintfhdl);
++ struct io_priv *pio_priv = &adapter->iopriv;
++ struct intf_hdl *pintfhdl = &(pio_priv->intf);
++
++ _write_port_cancel = pintfhdl->io_ops._write_port_cancel;
++
++ if(_write_port_cancel)
++ _write_port_cancel(pintfhdl);
++
++}
++
++int rtw_init_io_priv(_adapter *padapter, void (*set_intf_ops)(struct _io_ops *pops))
++{
++ struct io_priv *piopriv = &padapter->iopriv;
++ struct intf_hdl *pintf = &piopriv->intf;
++
++ if (set_intf_ops == NULL)
++ return _FAIL;
++
++ piopriv->padapter = padapter;
++ pintf->padapter = padapter;
++ pintf->pintf_dev = adapter_to_dvobj(padapter);
++
++ set_intf_ops(&pintf->io_ops);
++
++ return _SUCCESS;
++}
++
++#ifdef DBG_IO
++
++u16 read_sniff_ranges[][2] = {
++ //{0x550, 0x551},
++};
++
++u16 write_sniff_ranges[][2] = {
++ //{0x550, 0x551},
++ //{0x4c, 0x4c},
++};
++
++int read_sniff_num = sizeof(read_sniff_ranges)/sizeof(u16)/2;
++int write_sniff_num = sizeof(write_sniff_ranges)/sizeof(u16)/2;
++
++bool match_read_sniff_ranges(u16 addr, u16 len)
++{
++ int i;
++ for (i = 0; i<read_sniff_num; i++) {
++ if (addr + len > read_sniff_ranges[i][0] && addr <= read_sniff_ranges[i][1])
++ return _TRUE;
++ }
++
++ return _FALSE;
++}
++
++bool match_write_sniff_ranges(u16 addr, u16 len)
++{
++ int i;
++ for (i = 0; i<write_sniff_num; i++) {
++ if (addr + len > write_sniff_ranges[i][0] && addr <= write_sniff_ranges[i][1])
++ return _TRUE;
++ }
++
++ return _FALSE;
++}
++
++u8 dbg_rtw_read8(_adapter *adapter, u32 addr, const char *caller, const int line)
++{
++ u8 val = _rtw_read8(adapter, addr);
++
++ if (match_read_sniff_ranges(addr, 1))
++ DBG_871X("DBG_IO %s:%d rtw_read8(0x%04x) return 0x%02x\n", caller, line, addr, val);
++
++ return val;
++}
++
++u16 dbg_rtw_read16(_adapter *adapter, u32 addr, const char *caller, const int line)
++{
++ u16 val = _rtw_read16(adapter, addr);
++
++ if (match_read_sniff_ranges(addr, 2))
++ DBG_871X("DBG_IO %s:%d rtw_read16(0x%04x) return 0x%04x\n", caller, line, addr, val);
++
++ return val;
++}
++
++u32 dbg_rtw_read32(_adapter *adapter, u32 addr, const char *caller, const int line)
++{
++ u32 val = _rtw_read32(adapter, addr);
++
++ if (match_read_sniff_ranges(addr, 4))
++ DBG_871X("DBG_IO %s:%d rtw_read32(0x%04x) return 0x%08x\n", caller, line, addr, val);
++
++ return val;
++}
++
++int dbg_rtw_write8(_adapter *adapter, u32 addr, u8 val, const char *caller, const int line)
++{
++ if (match_write_sniff_ranges(addr, 1))
++ DBG_871X("DBG_IO %s:%d rtw_write8(0x%04x, 0x%02x)\n", caller, line, addr, val);
++
++ return _rtw_write8(adapter, addr, val);
++}
++int dbg_rtw_write16(_adapter *adapter, u32 addr, u16 val, const char *caller, const int line)
++{
++ if (match_write_sniff_ranges(addr, 2))
++ DBG_871X("DBG_IO %s:%d rtw_write16(0x%04x, 0x%04x)\n", caller, line, addr, val);
++
++ return _rtw_write16(adapter, addr, val);
++}
++int dbg_rtw_write32(_adapter *adapter, u32 addr, u32 val, const char *caller, const int line)
++{
++ if (match_write_sniff_ranges(addr, 4))
++ DBG_871X("DBG_IO %s:%d rtw_write32(0x%04x, 0x%08x)\n", caller, line, addr, val);
++
++ return _rtw_write32(adapter, addr, val);
++}
++int dbg_rtw_writeN(_adapter *adapter, u32 addr ,u32 length , u8 *data, const char *caller, const int line)
++{
++ if (match_write_sniff_ranges(addr, length))
++ DBG_871X("DBG_IO %s:%d rtw_writeN(0x%04x, %u)\n", caller, line, addr, length);
++
++ return _rtw_writeN(adapter, addr, length, data);
++}
++#endif
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/core/rtw_ioctl_query.c linux-xbian-rpi/drivers/net/wireless/rtl8192cu/core/rtw_ioctl_query.c
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/core/rtw_ioctl_query.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/core/rtw_ioctl_query.c 2015-07-28 01:20:58.301668422 +0200
+@@ -0,0 +1,195 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#define _RTW_IOCTL_QUERY_C_
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++#include <rtw_ioctl_query.h>
++#include <wifi.h>
++
++
++#ifdef PLATFORM_WINDOWS
++//
++// Added for WPA2-PSK, by Annie, 2005-09-20.
++//
++u8
++query_802_11_capability(
++ _adapter* Adapter,
++ u8* pucBuf,
++ u32 * pulOutLen
++)
++{
++ static NDIS_802_11_AUTHENTICATION_ENCRYPTION szAuthEnc[] =
++ {
++ {Ndis802_11AuthModeOpen, Ndis802_11EncryptionDisabled},
++ {Ndis802_11AuthModeOpen, Ndis802_11Encryption1Enabled},
++ {Ndis802_11AuthModeShared, Ndis802_11EncryptionDisabled},
++ {Ndis802_11AuthModeShared, Ndis802_11Encryption1Enabled},
++ {Ndis802_11AuthModeWPA, Ndis802_11Encryption2Enabled},
++ {Ndis802_11AuthModeWPA, Ndis802_11Encryption3Enabled},
++ {Ndis802_11AuthModeWPAPSK, Ndis802_11Encryption2Enabled},
++ {Ndis802_11AuthModeWPAPSK, Ndis802_11Encryption3Enabled},
++ {Ndis802_11AuthModeWPANone, Ndis802_11Encryption2Enabled},
++ {Ndis802_11AuthModeWPANone, Ndis802_11Encryption3Enabled},
++ {Ndis802_11AuthModeWPA2, Ndis802_11Encryption2Enabled},
++ {Ndis802_11AuthModeWPA2, Ndis802_11Encryption3Enabled},
++ {Ndis802_11AuthModeWPA2PSK, Ndis802_11Encryption2Enabled},
++ {Ndis802_11AuthModeWPA2PSK, Ndis802_11Encryption3Enabled}
++ };
++ static ULONG ulNumOfPairSupported = sizeof(szAuthEnc)/sizeof(NDIS_802_11_AUTHENTICATION_ENCRYPTION);
++ NDIS_802_11_CAPABILITY * pCap = (NDIS_802_11_CAPABILITY *)pucBuf;
++ u8* pucAuthEncryptionSupported = (u8*) pCap->AuthenticationEncryptionSupported;
++
++
++ pCap->Length = sizeof(NDIS_802_11_CAPABILITY);
++ if(ulNumOfPairSupported > 1 )
++ pCap->Length += (ulNumOfPairSupported-1) * sizeof(NDIS_802_11_AUTHENTICATION_ENCRYPTION);
++
++ pCap->Version = 2;
++ pCap->NoOfPMKIDs = NUM_PMKID_CACHE;
++ pCap->NoOfAuthEncryptPairsSupported = ulNumOfPairSupported;
++
++ if( sizeof (szAuthEnc) <= 240 ) // 240 = 256 - 4*4 // SecurityInfo.szCapability: only 256 bytes in size.
++ {
++ _rtw_memcpy( pucAuthEncryptionSupported, (u8*)szAuthEnc, sizeof (szAuthEnc) );
++ *pulOutLen = pCap->Length;
++ return _TRUE;
++ }
++ else
++ {
++ *pulOutLen = 0;
++ RT_TRACE(_module_rtl871x_ioctl_query_c_,_drv_info_,("_query_802_11_capability(): szAuthEnc size is too large.\n"));
++ return _FALSE;
++ }
++}
++
++u8 query_802_11_association_information( _adapter *padapter,PNDIS_802_11_ASSOCIATION_INFORMATION pAssocInfo)
++{
++ struct wlan_network *tgt_network;
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ struct security_priv *psecuritypriv=&(padapter->securitypriv);
++ WLAN_BSSID_EX *psecnetwork=(WLAN_BSSID_EX*)&(psecuritypriv->sec_bss);
++ u8 * pDest = (u8 *)pAssocInfo + sizeof(NDIS_802_11_ASSOCIATION_INFORMATION);
++ unsigned char i,*auth_ie,*supp_ie;
++
++ //NdisZeroMemory(pAssocInfo, sizeof(NDIS_802_11_ASSOCIATION_INFORMATION));
++ _rtw_memset(pAssocInfo, 0, sizeof(NDIS_802_11_ASSOCIATION_INFORMATION));
++ //pAssocInfo->Length = sizeof(NDIS_802_11_ASSOCIATION_INFORMATION);
++
++ //------------------------------------------------------
++ // Association Request related information
++ //------------------------------------------------------
++ // Req_1. AvailableRequestFixedIEs
++ if(psecnetwork!=NULL){
++
++ pAssocInfo->AvailableRequestFixedIEs |= NDIS_802_11_AI_REQFI_CAPABILITIES|NDIS_802_11_AI_REQFI_CURRENTAPADDRESS;
++ pAssocInfo->RequestFixedIEs.Capabilities = (unsigned short)* & psecnetwork->IEs[10];
++ _rtw_memcpy(pAssocInfo->RequestFixedIEs.CurrentAPAddress,
++ & psecnetwork->MacAddress, 6);
++
++ pAssocInfo->OffsetRequestIEs = sizeof(NDIS_802_11_ASSOCIATION_INFORMATION);
++
++ if(check_fwstate( pmlmepriv, _FW_UNDER_LINKING|_FW_LINKED)==_TRUE)
++ {
++
++ if(psecuritypriv->ndisauthtype>=Ndis802_11AuthModeWPA2)
++ pDest[0] =48; //RSN Information Element
++ else
++ pDest[0] =221; //WPA(SSN) Information Element
++
++ RT_TRACE(_module_rtl871x_ioctl_query_c_,_drv_info_,("\n Adapter->ndisauthtype==Ndis802_11AuthModeWPA)?0xdd:0x30 [%d]",pDest[0]));
++ supp_ie=&psecuritypriv->supplicant_ie[0];
++ for(i=0;i<supp_ie[0];i++)
++ {
++ RT_TRACE(_module_rtl871x_ioctl_query_c_,_drv_info_,("IEs [%d] = 0x%x \n\n", i,supp_ie[i]));
++ }
++
++ i=13; //0~11 is fixed information element
++ RT_TRACE(_module_rtl871x_ioctl_query_c_,_drv_info_,("i= %d tgt_network->network.IELength=%d\n\n", i,(int)psecnetwork->IELength));
++ while((i<supp_ie[0]) && (i<256)){
++ if((unsigned char)supp_ie[i]==pDest[0]){
++ _rtw_memcpy((u8 *)(pDest),
++ &supp_ie[i],
++ supp_ie[1+i]+2);
++
++ break;
++ }
++
++ i=i+supp_ie[i+1]+2;
++ if(supp_ie[1+i]==0)
++ i=i+1;
++ RT_TRACE(_module_rtl871x_ioctl_query_c_,_drv_info_,("iteration i=%d IEs [%d] = 0x%x \n\n", i,i,supp_ie[i+1]));
++
++ }
++
++
++ pAssocInfo->RequestIELength += (2 + supp_ie[1+i]);// (2 + psecnetwork->IEs[1+i]+4);
++
++ }
++
++
++ RT_TRACE(_module_rtl871x_ioctl_query_c_,_drv_info_,("\n psecnetwork != NULL,fwstate==_FW_UNDER_LINKING \n"));
++
++ }
++
++
++ //------------------------------------------------------
++ // Association Response related information
++ //------------------------------------------------------
++
++ if(check_fwstate( pmlmepriv, _FW_LINKED)==_TRUE)
++ {
++ tgt_network =&(pmlmepriv->cur_network);
++ if(tgt_network!=NULL){
++ pAssocInfo->AvailableResponseFixedIEs =
++ NDIS_802_11_AI_RESFI_CAPABILITIES
++ |NDIS_802_11_AI_RESFI_ASSOCIATIONID
++ ;
++
++ pAssocInfo->ResponseFixedIEs.Capabilities =(unsigned short)* & tgt_network->network.IEs[10];
++ pAssocInfo->ResponseFixedIEs.StatusCode = 0;
++ pAssocInfo->ResponseFixedIEs.AssociationId =(unsigned short) tgt_network->aid;
++
++ pDest = (u8 *)pAssocInfo + sizeof(NDIS_802_11_ASSOCIATION_INFORMATION)+pAssocInfo->RequestIELength;
++ auth_ie=&psecuritypriv->authenticator_ie[0];
++
++ for(i=0;i<auth_ie[0];i++)
++ RT_TRACE(_module_rtl871x_ioctl_query_c_,_drv_info_,("IEs [%d] = 0x%x \n\n", i,auth_ie[i]));
++
++ i=auth_ie[0]-12;
++ if(i>0){
++ _rtw_memcpy((u8 *)&pDest[0],&auth_ie[1],i);
++ pAssocInfo->ResponseIELength =i;
++ }
++
++
++ pAssocInfo->OffsetResponseIEs = sizeof(NDIS_802_11_ASSOCIATION_INFORMATION) + pAssocInfo->RequestIELength;
++
++
++ RT_TRACE(_module_rtl871x_ioctl_query_c_,_drv_info_,("\n tgt_network != NULL,fwstate==_FW_LINKED \n"));
++ }
++ }
++ RT_TRACE(_module_rtl871x_ioctl_query_c_,_drv_info_,("\n exit query_802_11_association_information \n"));
++_func_exit_;
++
++ return _TRUE;
++}
++#endif
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/core/rtw_ioctl_rtl.c linux-xbian-rpi/drivers/net/wireless/rtl8192cu/core/rtw_ioctl_rtl.c
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/core/rtw_ioctl_rtl.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/core/rtw_ioctl_rtl.c 2015-07-28 01:20:58.301668422 +0200
+@@ -0,0 +1,1031 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#define _RTW_IOCTL_RTL_C_
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++#include <wlan_bssdef.h>
++#include <wifi.h>
++#include <rtw_ioctl.h>
++#include <rtw_ioctl_set.h>
++#include <rtw_ioctl_query.h>
++#include <rtw_ioctl_rtl.h>
++#include <mp_custom_oid.h>
++#ifdef CONFIG_MP_INCLUDED
++#include <rtw_mp.h>
++#include <rtw_mp_ioctl.h>
++#endif
++
++struct oid_obj_priv oid_rtl_seg_01_01[] =
++{
++ {1, &oid_null_function}, //0x80
++ {1, &oid_null_function}, //0x81
++ {1, &oid_null_function}, //0x82
++ {1, &oid_null_function}, //0x83//OID_RT_SET_SNIFFER_MODE
++ {1, &oid_rt_get_signal_quality_hdl}, //0x84
++ {1, &oid_rt_get_small_packet_crc_hdl}, //0x85
++ {1, &oid_rt_get_middle_packet_crc_hdl}, //0x86
++ {1, &oid_rt_get_large_packet_crc_hdl}, //0x87
++ {1, &oid_rt_get_tx_retry_hdl}, //0x88
++ {1, &oid_rt_get_rx_retry_hdl}, //0x89
++ {1, &oid_rt_pro_set_fw_dig_state_hdl}, //0x8A
++ {1, &oid_rt_pro_set_fw_ra_state_hdl} , //0x8B
++ {1, &oid_null_function}, //0x8C
++ {1, &oid_null_function}, //0x8D
++ {1, &oid_null_function}, //0x8E
++ {1, &oid_null_function}, //0x8F
++ {1, &oid_rt_get_rx_total_packet_hdl}, //0x90
++ {1, &oid_rt_get_tx_beacon_ok_hdl}, //0x91
++ {1, &oid_rt_get_tx_beacon_err_hdl}, //0x92
++ {1, &oid_rt_get_rx_icv_err_hdl}, //0x93
++ {1, &oid_rt_set_encryption_algorithm_hdl}, //0x94
++ {1, &oid_null_function}, //0x95
++ {1, &oid_rt_get_preamble_mode_hdl}, //0x96
++ {1, &oid_null_function}, //0x97
++ {1, &oid_rt_get_ap_ip_hdl}, //0x98
++ {1, &oid_rt_get_channelplan_hdl}, //0x99
++ {1, &oid_rt_set_preamble_mode_hdl}, //0x9A
++ {1, &oid_rt_set_bcn_intvl_hdl}, //0x9B
++ {1, &oid_null_function}, //0x9C
++ {1, &oid_rt_dedicate_probe_hdl}, //0x9D
++ {1, &oid_null_function}, //0x9E
++ {1, &oid_null_function}, //0x9F
++ {1, &oid_null_function}, //0xA0
++ {1, &oid_null_function}, //0xA1
++ {1, &oid_null_function}, //0xA2
++ {1, &oid_null_function}, //0xA3
++ {1, &oid_null_function}, //0xA4
++ {1, &oid_null_function}, //0xA5
++ {1, &oid_null_function}, //0xA6
++ {1, &oid_rt_get_total_tx_bytes_hdl}, //0xA7
++ {1, &oid_rt_get_total_rx_bytes_hdl}, //0xA8
++ {1, &oid_rt_current_tx_power_level_hdl}, //0xA9
++ {1, &oid_rt_get_enc_key_mismatch_count_hdl}, //0xAA
++ {1, &oid_rt_get_enc_key_match_count_hdl}, //0xAB
++ {1, &oid_rt_get_channel_hdl}, //0xAC
++ {1, &oid_rt_set_channelplan_hdl}, //0xAD
++ {1, &oid_rt_get_hardware_radio_off_hdl}, //0xAE
++ {1, &oid_null_function}, //0xAF
++ {1, &oid_null_function}, //0xB0
++ {1, &oid_null_function}, //0xB1
++ {1, &oid_null_function}, //0xB2
++ {1, &oid_null_function}, //0xB3
++ {1, &oid_rt_get_key_mismatch_hdl}, //0xB4
++ {1, &oid_null_function}, //0xB5
++ {1, &oid_null_function}, //0xB6
++ {1, &oid_null_function}, //0xB7
++ {1, &oid_null_function}, //0xB8
++ {1, &oid_null_function}, //0xB9
++ {1, &oid_null_function}, //0xBA
++ {1, &oid_rt_supported_wireless_mode_hdl}, //0xBB
++ {1, &oid_rt_get_channel_list_hdl}, //0xBC
++ {1, &oid_rt_get_scan_in_progress_hdl}, //0xBD
++ {1, &oid_null_function}, //0xBE
++ {1, &oid_null_function}, //0xBF
++ {1, &oid_null_function}, //0xC0
++ {1, &oid_rt_forced_data_rate_hdl}, //0xC1
++ {1, &oid_rt_wireless_mode_for_scan_list_hdl}, //0xC2
++ {1, &oid_rt_get_bss_wireless_mode_hdl}, //0xC3
++ {1, &oid_rt_scan_with_magic_packet_hdl}, //0xC4
++ {1, &oid_null_function}, //0xC5
++ {1, &oid_null_function}, //0xC6
++ {1, &oid_null_function}, //0xC7
++ {1, &oid_null_function}, //0xC8
++ {1, &oid_null_function}, //0xC9
++ {1, &oid_null_function}, //0xCA
++ {1, &oid_null_function}, //0xCB
++ {1, &oid_null_function}, //0xCC
++ {1, &oid_null_function}, //0xCD
++ {1, &oid_null_function}, //0xCE
++ {1, &oid_null_function}, //0xCF
++
++};
++
++struct oid_obj_priv oid_rtl_seg_01_03[] =
++{
++ {1, &oid_rt_ap_get_associated_station_list_hdl}, //0x00
++ {1, &oid_null_function}, //0x01
++ {1, &oid_rt_ap_switch_into_ap_mode_hdl}, //0x02
++ {1, &oid_null_function}, //0x03
++ {1, &oid_rt_ap_supported_hdl}, //0x04
++ {1, &oid_rt_ap_set_passphrase_hdl}, //0x05
++
++};
++
++struct oid_obj_priv oid_rtl_seg_01_11[] =
++{
++ {1, &oid_null_function}, //0xC0 OID_RT_PRO_RX_FILTER
++ {1, &oid_null_function}, //0xC1 OID_CE_USB_WRITE_REGISTRY
++ {1, &oid_null_function}, //0xC2 OID_CE_USB_READ_REGISTRY
++ {1, &oid_null_function}, //0xC3 OID_RT_PRO_SET_INITIAL_GAIN
++ {1, &oid_null_function}, //0xC4 OID_RT_PRO_SET_BB_RF_STANDBY_MODE
++ {1, &oid_null_function}, //0xC5 OID_RT_PRO_SET_BB_RF_SHUTDOWN_MODE
++ {1, &oid_null_function}, //0xC6 OID_RT_PRO_SET_TX_CHARGE_PUMP
++ {1, &oid_null_function}, //0xC7 OID_RT_PRO_SET_RX_CHARGE_PUMP
++ {1, &oid_rt_pro_rf_write_registry_hdl}, //0xC8
++ {1, &oid_rt_pro_rf_read_registry_hdl}, //0xC9
++ {1, &oid_null_function} //0xCA OID_RT_PRO_QUERY_RF_TYPE
++
++};
++
++struct oid_obj_priv oid_rtl_seg_03_00[] =
++{
++ {1, &oid_null_function}, //0x00
++ {1, &oid_rt_get_connect_state_hdl}, //0x01
++ {1, &oid_null_function}, //0x02
++ {1, &oid_null_function}, //0x03
++ {1, &oid_rt_set_default_key_id_hdl}, //0x04
++
++
++};
++
++
++//************** oid_rtl_seg_01_01 section start **************
++
++NDIS_STATUS oid_rt_pro_set_fw_dig_state_hdl(struct oid_par_priv* poid_par_priv)
++{
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++#if 0
++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
++ _irqL oldirql;
++
++ _func_enter_;
++
++ if(poid_par_priv->type_of_oid != SET_OID)
++ {
++ status = NDIS_STATUS_NOT_ACCEPTED;
++ return status;
++ }
++
++ _irqlevel_changed_(&oldirql,LOWER);
++ if(poid_par_priv->information_buf_len >= sizeof(struct setdig_parm))
++ {
++ //DEBUG_ERR(("===> oid_rt_pro_set_fw_dig_state_hdl. type:0x%02x.\n",*((unsigned char*)poid_par_priv->information_buf )));
++ if(!rtw_setfwdig_cmd(Adapter,*((unsigned char*)poid_par_priv->information_buf )))
++ {
++ status = NDIS_STATUS_NOT_ACCEPTED;
++ }
++
++ }
++ else{
++ status = NDIS_STATUS_NOT_ACCEPTED;
++ }
++ _irqlevel_changed_(&oldirql,RAISE);
++ _func_exit_;
++#endif
++ return status;
++}
++//-----------------------------------------------------------------------------
++NDIS_STATUS oid_rt_pro_set_fw_ra_state_hdl(struct oid_par_priv* poid_par_priv)
++{
++
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++#if 0
++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
++ _irqL oldirql;
++
++ _func_enter_;
++ if(poid_par_priv->type_of_oid != SET_OID)
++ {
++ status = NDIS_STATUS_NOT_ACCEPTED;
++ return status;
++ }
++
++
++ _irqlevel_changed_(&oldirql,LOWER);
++
++ if(poid_par_priv->information_buf_len >= sizeof(struct setra_parm))
++ {
++ //DEBUG_ERR(("===> oid_rt_pro_set_fw_ra_state_hdl. type:0x%02x.\n",*((unsigned char*)poid_par_priv->information_buf )));
++ if(!rtw_setfwra_cmd(Adapter,*((unsigned char*)poid_par_priv->information_buf )))
++ {
++ status = NDIS_STATUS_NOT_ACCEPTED;
++ }
++
++ }
++ else{
++ status = NDIS_STATUS_NOT_ACCEPTED;
++ }
++ _irqlevel_changed_(&oldirql,RAISE);
++ _func_exit_;
++#endif
++ return status;
++}
++//-----------------------------------------------------------------------------
++NDIS_STATUS oid_rt_get_signal_quality_hdl(struct oid_par_priv* poid_par_priv)
++{
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++ //DEBUG_ERR(("<**********************oid_rt_get_signal_quality_hdl \n"));
++ if(poid_par_priv->type_of_oid != QUERY_OID)
++ {
++ status = NDIS_STATUS_NOT_ACCEPTED;
++ return status;
++ }
++
++#if 0
++ if(pMgntInfo->mAssoc || pMgntInfo->mIbss)
++ {
++ ulInfo = pAdapter->RxStats.SignalQuality;
++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
++ }
++ else
++ {
++ ulInfo = 0xffffffff; // It stands for -1 in 4-byte integer.
++ }
++ break;
++#endif
++
++ return status;
++}
++
++//------------------------------------------------------------------------------
++
++NDIS_STATUS oid_rt_get_small_packet_crc_hdl(struct oid_par_priv* poid_par_priv)
++{
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++ if(poid_par_priv->type_of_oid != QUERY_OID)
++ {
++ status = NDIS_STATUS_NOT_ACCEPTED;
++ return status;
++ }
++
++ if(poid_par_priv->information_buf_len >= sizeof(ULONG) )
++ {
++ *(ULONG *)poid_par_priv->information_buf = padapter->recvpriv.rx_smallpacket_crcerr;
++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
++ }
++ else
++ {
++ status = NDIS_STATUS_INVALID_LENGTH;
++ }
++
++ return status;
++}
++//------------------------------------------------------------------------------
++NDIS_STATUS oid_rt_get_middle_packet_crc_hdl(struct oid_par_priv* poid_par_priv)
++{
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++ if(poid_par_priv->type_of_oid != QUERY_OID)
++ {
++ status = NDIS_STATUS_NOT_ACCEPTED;
++ return status;
++ }
++
++ if(poid_par_priv->information_buf_len >= sizeof(ULONG) )
++ {
++ *(ULONG *)poid_par_priv->information_buf = padapter->recvpriv.rx_middlepacket_crcerr;
++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
++ }
++ else
++ {
++ status = NDIS_STATUS_INVALID_LENGTH;
++ }
++
++
++ return status;
++}
++//------------------------------------------------------------------------------
++NDIS_STATUS oid_rt_get_large_packet_crc_hdl(struct oid_par_priv* poid_par_priv)
++{
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++ if(poid_par_priv->type_of_oid != QUERY_OID)
++ {
++ status = NDIS_STATUS_NOT_ACCEPTED;
++ return status;
++ }
++
++ if(poid_par_priv->information_buf_len >= sizeof(ULONG) )
++ {
++ *(ULONG *)poid_par_priv->information_buf = padapter->recvpriv.rx_largepacket_crcerr;
++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
++ }
++ else
++ {
++ status = NDIS_STATUS_INVALID_LENGTH;
++ }
++
++
++ return status;
++}
++
++//------------------------------------------------------------------------------
++NDIS_STATUS oid_rt_get_tx_retry_hdl(struct oid_par_priv* poid_par_priv)
++{
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++ if(poid_par_priv->type_of_oid != QUERY_OID)
++ {
++ status = NDIS_STATUS_NOT_ACCEPTED;
++ return status;
++ }
++
++ return status;
++}
++NDIS_STATUS oid_rt_get_rx_retry_hdl(struct oid_par_priv* poid_par_priv)
++{
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++ if(poid_par_priv->type_of_oid != QUERY_OID)
++ {
++ status = NDIS_STATUS_NOT_ACCEPTED;
++ return status;
++ }
++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
++ return status;
++}
++//------------------------------------------------------------------------------
++NDIS_STATUS oid_rt_get_rx_total_packet_hdl(struct oid_par_priv* poid_par_priv)
++{
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++ if(poid_par_priv->type_of_oid != QUERY_OID)
++ {
++ status = NDIS_STATUS_NOT_ACCEPTED;
++ return status;
++ }
++ if(poid_par_priv->information_buf_len >= sizeof(ULONG) )
++ {
++ *(u64 *)poid_par_priv->information_buf = padapter->recvpriv.rx_pkts + padapter->recvpriv.rx_drop;
++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
++ }
++ else
++ {
++ status = NDIS_STATUS_INVALID_LENGTH;
++ }
++
++
++ return status;
++}
++//------------------------------------------------------------------------------
++NDIS_STATUS oid_rt_get_tx_beacon_ok_hdl(struct oid_par_priv* poid_par_priv)
++{
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++ if(poid_par_priv->type_of_oid != QUERY_OID)
++ {
++ status = NDIS_STATUS_NOT_ACCEPTED;
++ return status;
++ }
++
++ return status;
++}
++NDIS_STATUS oid_rt_get_tx_beacon_err_hdl(struct oid_par_priv* poid_par_priv)
++{
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++ if(poid_par_priv->type_of_oid != QUERY_OID)
++ {
++ status = NDIS_STATUS_NOT_ACCEPTED;
++ return status;
++ }
++
++ return status;
++}
++//------------------------------------------------------------------------------
++NDIS_STATUS oid_rt_get_rx_icv_err_hdl(struct oid_par_priv* poid_par_priv)
++{
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++ if(poid_par_priv->type_of_oid != QUERY_OID)
++ {
++ status = NDIS_STATUS_NOT_ACCEPTED;
++ return status;
++ }
++ if(poid_par_priv->information_buf_len>= sizeof(u32))
++ {
++ //_rtw_memcpy(*(uint *)poid_par_priv->information_buf,padapter->recvpriv.rx_icv_err,sizeof(u32));
++ *(uint *)poid_par_priv->information_buf = padapter->recvpriv.rx_icv_err;
++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
++ }
++ else
++ {
++ status = NDIS_STATUS_INVALID_LENGTH ;
++ }
++
++
++ return status;
++}
++//------------------------------------------------------------------------------
++NDIS_STATUS oid_rt_set_encryption_algorithm_hdl(struct oid_par_priv* poid_par_priv)
++{
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++ if(poid_par_priv->type_of_oid != SET_OID)
++ {
++ status = NDIS_STATUS_NOT_ACCEPTED;
++ return status;
++ }
++
++ return status;
++}
++//------------------------------------------------------------------------------
++NDIS_STATUS oid_rt_get_preamble_mode_hdl(struct oid_par_priv* poid_par_priv)
++{
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
++ ULONG preamblemode = 0 ;
++
++ if(poid_par_priv->type_of_oid != QUERY_OID)
++ {
++ status = NDIS_STATUS_NOT_ACCEPTED;
++ return status;
++ }
++ if(poid_par_priv->information_buf_len>= sizeof(ULONG))
++ {
++ if(padapter->registrypriv.preamble == PREAMBLE_LONG)
++ preamblemode = 0;
++ else if (padapter->registrypriv.preamble == PREAMBLE_AUTO)
++ preamblemode = 1;
++ else if (padapter->registrypriv.preamble == PREAMBLE_SHORT)
++ preamblemode = 2;
++
++
++ *(ULONG *)poid_par_priv->information_buf = preamblemode ;
++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
++ }
++ else
++ {
++ status = NDIS_STATUS_INVALID_LENGTH ;
++ }
++ return status;
++}
++//------------------------------------------------------------------------------
++NDIS_STATUS oid_rt_get_ap_ip_hdl(struct oid_par_priv* poid_par_priv)
++{
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++ if(poid_par_priv->type_of_oid != QUERY_OID)
++ {
++ status = NDIS_STATUS_NOT_ACCEPTED;
++ return status;
++ }
++
++ return status;
++}
++
++NDIS_STATUS oid_rt_get_channelplan_hdl(struct oid_par_priv* poid_par_priv)
++{
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
++ struct eeprom_priv* peeprompriv = &padapter->eeprompriv;
++
++ if(poid_par_priv->type_of_oid != QUERY_OID)
++ {
++ status = NDIS_STATUS_NOT_ACCEPTED;
++ return status;
++ }
++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
++ *(u16 *)poid_par_priv->information_buf = peeprompriv->channel_plan ;
++
++ return status;
++}
++NDIS_STATUS oid_rt_set_channelplan_hdl(struct oid_par_priv* poid_par_priv)
++{
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
++ struct eeprom_priv* peeprompriv = &padapter->eeprompriv;
++
++ if(poid_par_priv->type_of_oid != SET_OID)
++ {
++ status = NDIS_STATUS_NOT_ACCEPTED;
++ return status;
++ }
++
++ peeprompriv->channel_plan = *(u16 *)poid_par_priv->information_buf ;
++
++ return status;
++}
++//------------------------------------------------------------------------------
++NDIS_STATUS oid_rt_set_preamble_mode_hdl(struct oid_par_priv* poid_par_priv)
++{
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
++ ULONG preamblemode = 0;
++ if(poid_par_priv->type_of_oid != SET_OID)
++ {
++ status = NDIS_STATUS_NOT_ACCEPTED;
++ return status;
++ }
++
++ if(poid_par_priv->information_buf_len>= sizeof(ULONG))
++ {
++ preamblemode = *(ULONG *)poid_par_priv->information_buf ;
++ if( preamblemode == 0)
++ padapter->registrypriv.preamble = PREAMBLE_LONG;
++ else if (preamblemode==1 )
++ padapter->registrypriv.preamble = PREAMBLE_AUTO;
++ else if ( preamblemode==2 )
++ padapter->registrypriv.preamble = PREAMBLE_SHORT;
++
++ *(ULONG *)poid_par_priv->information_buf = preamblemode ;
++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
++ }
++ else
++ {
++ status = NDIS_STATUS_INVALID_LENGTH ;
++ }
++
++ return status;
++}
++//------------------------------------------------------------------------------
++NDIS_STATUS oid_rt_set_bcn_intvl_hdl(struct oid_par_priv* poid_par_priv)
++{
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++ if(poid_par_priv->type_of_oid != SET_OID)
++ {
++ status = NDIS_STATUS_NOT_ACCEPTED;
++ return status;
++ }
++
++ return status;
++}
++NDIS_STATUS oid_rt_dedicate_probe_hdl(struct oid_par_priv* poid_par_priv)
++{
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++ return status;
++}
++//------------------------------------------------------------------------------
++NDIS_STATUS oid_rt_get_total_tx_bytes_hdl(struct oid_par_priv* poid_par_priv)
++{
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++ if(poid_par_priv->type_of_oid != QUERY_OID)
++ {
++ status = NDIS_STATUS_NOT_ACCEPTED;
++ return status;
++ }
++ if(poid_par_priv->information_buf_len>= sizeof(ULONG))
++ {
++ *(u64 *)poid_par_priv->information_buf = padapter->xmitpriv.tx_bytes;
++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
++ }
++ else
++ {
++ status = NDIS_STATUS_INVALID_LENGTH ;
++ }
++
++
++ return status;
++}
++//------------------------------------------------------------------------------
++NDIS_STATUS oid_rt_get_total_rx_bytes_hdl(struct oid_par_priv* poid_par_priv)
++{
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++ if(poid_par_priv->type_of_oid != QUERY_OID)
++ {
++ status = NDIS_STATUS_NOT_ACCEPTED;
++ return status;
++ }
++ if(poid_par_priv->information_buf_len>= sizeof(ULONG))
++ {
++ //_rtw_memcpy(*(uint *)poid_par_priv->information_buf,padapter->recvpriv.rx_icv_err,sizeof(u32));
++ *(u64 *)poid_par_priv->information_buf = padapter->recvpriv.rx_bytes;
++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
++ }
++ else
++ {
++ status = NDIS_STATUS_INVALID_LENGTH ;
++ }
++ return status;
++}
++//------------------------------------------------------------------------------
++NDIS_STATUS oid_rt_current_tx_power_level_hdl(struct oid_par_priv* poid_par_priv)
++{
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++ return status;
++}
++NDIS_STATUS oid_rt_get_enc_key_mismatch_count_hdl(struct oid_par_priv* poid_par_priv)
++{
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++ if(poid_par_priv->type_of_oid != QUERY_OID)
++ {
++ status = NDIS_STATUS_NOT_ACCEPTED;
++ return status;
++ }
++
++ return status;
++}
++NDIS_STATUS oid_rt_get_enc_key_match_count_hdl(struct oid_par_priv* poid_par_priv)
++{
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++ if(poid_par_priv->type_of_oid != QUERY_OID)
++ {
++ status = NDIS_STATUS_NOT_ACCEPTED;
++ return status;
++ }
++
++ return status;
++}
++NDIS_STATUS oid_rt_get_channel_hdl(struct oid_par_priv* poid_par_priv)
++{
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ NDIS_802_11_CONFIGURATION *pnic_Config;
++
++ ULONG channelnum;
++
++ _func_enter_;
++ if(poid_par_priv->type_of_oid != QUERY_OID)
++ {
++ status = NDIS_STATUS_NOT_ACCEPTED;
++ return status;
++ }
++
++ if ( (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) ||
++ (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE))
++ pnic_Config = &pmlmepriv->cur_network.network.Configuration;
++ else
++ pnic_Config = &padapter->registrypriv.dev_network.Configuration;
++
++ channelnum = pnic_Config->DSConfig;
++ *(ULONG *)poid_par_priv->information_buf = channelnum;
++
++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
++
++ _func_exit_;
++
++
++
++ return status;
++}
++NDIS_STATUS oid_rt_get_hardware_radio_off_hdl(struct oid_par_priv* poid_par_priv)
++{
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++ if(poid_par_priv->type_of_oid != QUERY_OID)
++ {
++ status = NDIS_STATUS_NOT_ACCEPTED;
++ return status;
++ }
++
++ return status;
++}
++NDIS_STATUS oid_rt_get_key_mismatch_hdl(struct oid_par_priv* poid_par_priv)
++{
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++ if(poid_par_priv->type_of_oid != QUERY_OID)
++ {
++ status = NDIS_STATUS_NOT_ACCEPTED;
++ return status;
++ }
++
++ return status;
++}
++NDIS_STATUS oid_rt_supported_wireless_mode_hdl(struct oid_par_priv* poid_par_priv)
++{
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
++ ULONG ulInfo = 0 ;
++ //DEBUG_ERR(("<**********************oid_rt_supported_wireless_mode_hdl \n"));
++ if(poid_par_priv->type_of_oid != QUERY_OID)
++ {
++ status = NDIS_STATUS_NOT_ACCEPTED;
++ return status;
++ }
++ if(poid_par_priv->information_buf_len >= sizeof(ULONG)){
++ ulInfo |= 0x0100; //WIRELESS_MODE_B
++ ulInfo |= 0x0200; //WIRELESS_MODE_G
++ ulInfo |= 0x0400; //WIRELESS_MODE_A
++
++ *(ULONG *) poid_par_priv->information_buf = ulInfo;
++ //DEBUG_ERR(("<===oid_rt_supported_wireless_mode %x\n",ulInfo));
++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
++ }
++ else{
++ status = NDIS_STATUS_INVALID_LENGTH;
++ }
++
++ return status;
++}
++NDIS_STATUS oid_rt_get_channel_list_hdl(struct oid_par_priv* poid_par_priv)
++{
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++ if(poid_par_priv->type_of_oid != QUERY_OID)
++ {
++ status = NDIS_STATUS_NOT_ACCEPTED;
++ return status;
++ }
++
++ return status;
++}
++NDIS_STATUS oid_rt_get_scan_in_progress_hdl(struct oid_par_priv* poid_par_priv)
++{
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++ if(poid_par_priv->type_of_oid != QUERY_OID)
++ {
++ status = NDIS_STATUS_NOT_ACCEPTED;
++ return status;
++ }
++
++ return status;
++}
++
++
++NDIS_STATUS oid_rt_forced_data_rate_hdl(struct oid_par_priv* poid_par_priv)
++{
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++ return status;
++}
++NDIS_STATUS oid_rt_wireless_mode_for_scan_list_hdl(struct oid_par_priv* poid_par_priv)
++{
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++ return status;
++}
++NDIS_STATUS oid_rt_get_bss_wireless_mode_hdl(struct oid_par_priv* poid_par_priv)
++{
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++ if(poid_par_priv->type_of_oid != QUERY_OID)
++ {
++ status = NDIS_STATUS_NOT_ACCEPTED;
++ return status;
++ }
++
++ return status;
++}
++
++NDIS_STATUS oid_rt_scan_with_magic_packet_hdl(struct oid_par_priv* poid_par_priv)
++{
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++ return status;
++}
++//************** oid_rtl_seg_01_01 section end **************
++
++//************** oid_rtl_seg_01_03 section start **************
++NDIS_STATUS oid_rt_ap_get_associated_station_list_hdl(struct oid_par_priv* poid_par_priv)
++{
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++ if(poid_par_priv->type_of_oid != QUERY_OID)
++ {
++ status = NDIS_STATUS_NOT_ACCEPTED;
++ return status;
++ }
++
++ return status;
++}
++NDIS_STATUS oid_rt_ap_switch_into_ap_mode_hdl(struct oid_par_priv* poid_par_priv)
++{
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++ return status;
++}
++NDIS_STATUS oid_rt_ap_supported_hdl(struct oid_par_priv* poid_par_priv)
++{
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++ return status;
++}
++NDIS_STATUS oid_rt_ap_set_passphrase_hdl(struct oid_par_priv* poid_par_priv)
++{
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++ if(poid_par_priv->type_of_oid != SET_OID)
++ {
++ status = NDIS_STATUS_NOT_ACCEPTED;
++ return status;
++ }
++
++ return status;
++}
++
++//************** oid_rtl_seg_01_03 section end **************
++
++//**************** oid_rtl_seg_01_11 section start ****************
++NDIS_STATUS oid_rt_pro_rf_write_registry_hdl(struct oid_par_priv* poid_par_priv)
++{
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
++ _irqL oldirql;
++ _func_enter_;
++ //DEBUG_ERR(("<**********************oid_rt_pro_rf_write_registry_hdl \n"));
++ if(poid_par_priv->type_of_oid != SET_OID) //QUERY_OID
++ {
++ status = NDIS_STATUS_NOT_ACCEPTED;
++ return status;
++ }
++
++ _irqlevel_changed_(&oldirql,LOWER);
++ if(poid_par_priv->information_buf_len== (sizeof(unsigned long)*3))
++ {
++ //RegOffsetValue - The offset of RF register to write.
++ //RegDataWidth - The data width of RF register to write.
++ //RegDataValue - The value to write.
++ //RegOffsetValue = *((unsigned long*)InformationBuffer);
++ //RegDataWidth = *((unsigned long*)InformationBuffer+1);
++ //RegDataValue = *((unsigned long*)InformationBuffer+2);
++ if(!rtw_setrfreg_cmd(Adapter,
++ *(unsigned char*)poid_par_priv->information_buf,
++ (unsigned long)(*((unsigned long*)poid_par_priv->information_buf+2))))
++ {
++ status = NDIS_STATUS_NOT_ACCEPTED;
++ }
++
++ }
++ else{
++ status = NDIS_STATUS_INVALID_LENGTH;
++ }
++ _irqlevel_changed_(&oldirql,RAISE);
++ _func_exit_;
++
++ return status;
++}
++
++//------------------------------------------------------------------------------
++NDIS_STATUS oid_rt_pro_rf_read_registry_hdl(struct oid_par_priv* poid_par_priv)
++{
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++#if 0
++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
++ _irqL oldirql;
++ _func_enter_;
++
++ //DEBUG_ERR(("<**********************oid_rt_pro_rf_read_registry_hdl \n"));
++ if(poid_par_priv->type_of_oid != SET_OID) //QUERY_OID
++ {
++ status = NDIS_STATUS_NOT_ACCEPTED;
++ return status;
++ }
++
++ _irqlevel_changed_(&oldirql,LOWER);
++ if(poid_par_priv->information_buf_len== (sizeof(unsigned long)*3))
++ {
++ if(Adapter->mppriv.act_in_progress == _TRUE)
++ {
++ status = NDIS_STATUS_NOT_ACCEPTED;
++ }
++ else
++ {
++ //init workparam
++ Adapter->mppriv.act_in_progress = _TRUE;
++ Adapter->mppriv.workparam.bcompleted= _FALSE;
++ Adapter->mppriv.workparam.act_type = MPT_READ_RF;
++ Adapter->mppriv.workparam.io_offset = *(unsigned long*)poid_par_priv->information_buf;
++ Adapter->mppriv.workparam.io_value = 0xcccccccc;
++
++ //RegOffsetValue - The offset of RF register to read.
++ //RegDataWidth - The data width of RF register to read.
++ //RegDataValue - The value to read.
++ //RegOffsetValue = *((unsigned long*)InformationBuffer);
++ //RegDataWidth = *((unsigned long*)InformationBuffer+1);
++ //RegDataValue = *((unsigned long*)InformationBuffer+2);
++ if(!rtw_getrfreg_cmd(Adapter,
++ *(unsigned char*)poid_par_priv->information_buf,
++ (unsigned char*)&Adapter->mppriv.workparam.io_value))
++ {
++ status = NDIS_STATUS_NOT_ACCEPTED;
++ }
++ }
++
++
++ }
++ else {
++ status = NDIS_STATUS_INVALID_LENGTH;
++ }
++ _irqlevel_changed_(&oldirql,RAISE);
++ _func_exit_;
++#endif
++ return status;
++}
++
++//**************** oid_rtl_seg_01_11 section end****************
++
++
++//************** oid_rtl_seg_03_00 section start **************
++enum _CONNECT_STATE_{
++ CHECKINGSTATUS,
++ ASSOCIATED,
++ ADHOCMODE,
++ NOTASSOCIATED
++};
++
++NDIS_STATUS oid_rt_get_connect_state_hdl(struct oid_par_priv* poid_par_priv)
++{
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++
++ ULONG ulInfo;
++
++ if(poid_par_priv->type_of_oid != QUERY_OID)
++ {
++ status = NDIS_STATUS_NOT_ACCEPTED;
++ return status;
++ }
++
++ // nStatus==0 CheckingStatus
++ // nStatus==1 Associated
++ // nStatus==2 AdHocMode
++ // nStatus==3 NotAssociated
++
++ if(check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == _TRUE)
++ ulInfo = CHECKINGSTATUS;
++ else if(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)
++ ulInfo = ASSOCIATED;
++ else if(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE)== _TRUE)
++ ulInfo = ADHOCMODE;
++ else
++ ulInfo = NOTASSOCIATED ;
++
++ *(ULONG *)poid_par_priv->information_buf = ulInfo;
++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
++
++#if 0
++ // Rearrange the order to let the UI still shows connection when scan is in progress
++ RT_TRACE(COMP_OID_QUERY, DBG_LOUD, ("===> Query OID_RT_GET_CONNECT_STATE.\n"));
++ if(pMgntInfo->mAssoc)
++ ulInfo = 1;
++ else if(pMgntInfo->mIbss)
++ ulInfo = 2;
++ else if(pMgntInfo->bScanInProgress)
++ ulInfo = 0;
++ else
++ ulInfo = 3;
++ ulInfoLen = sizeof(ULONG);
++ RT_TRACE(COMP_OID_QUERY, DBG_LOUD, ("<=== Query OID_RT_GET_CONNECT_STATE: %d\n", ulInfo));
++#endif
++
++ return status;
++}
++
++NDIS_STATUS oid_rt_set_default_key_id_hdl(struct oid_par_priv* poid_par_priv)
++{
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++ if(poid_par_priv->type_of_oid != SET_OID)
++ {
++ status = NDIS_STATUS_NOT_ACCEPTED;
++ return status;
++ }
++
++ return status;
++}
++//************** oid_rtl_seg_03_00 section end **************
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/core/rtw_ioctl_set.c linux-xbian-rpi/drivers/net/wireless/rtl8192cu/core/rtw_ioctl_set.c
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/core/rtw_ioctl_set.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/core/rtw_ioctl_set.c 2015-07-28 01:20:58.301668422 +0200
+@@ -0,0 +1,1493 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#define _RTW_IOCTL_SET_C_
++
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++#include <rtw_ioctl_set.h>
++#include <hal_intf.h>
++
++#ifdef CONFIG_USB_HCI
++#include <usb_osintf.h>
++#include <usb_ops.h>
++#endif
++#ifdef CONFIG_SDIO_HCI
++#include <sdio_osintf.h>
++#endif
++
++extern void indicate_wx_scan_complete_event(_adapter *padapter);
++
++#define IS_MAC_ADDRESS_BROADCAST(addr) \
++( \
++ ( (addr[0] == 0xff) && (addr[1] == 0xff) && \
++ (addr[2] == 0xff) && (addr[3] == 0xff) && \
++ (addr[4] == 0xff) && (addr[5] == 0xff) ) ? _TRUE : _FALSE \
++)
++
++u8 rtw_validate_bssid(u8 *bssid)
++{
++ u8 ret = _TRUE;
++
++ if (is_zero_mac_addr(bssid)
++ || is_broadcast_mac_addr(bssid)
++ || is_multicast_mac_addr(bssid)
++ ) {
++ ret = _FALSE;
++ }
++
++ return ret;
++}
++
++u8 rtw_validate_ssid(NDIS_802_11_SSID *ssid)
++{
++ u8 i;
++ u8 ret=_TRUE;
++
++_func_enter_;
++
++ if (ssid->SsidLength > 32) {
++ RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("ssid length >32\n"));
++ ret= _FALSE;
++ goto exit;
++ }
++
++#ifdef CONFIG_VALIDATE_SSID
++ for(i = 0; i < ssid->SsidLength; i++)
++ {
++ //wifi, printable ascii code must be supported
++ if(!( (ssid->Ssid[i] >= 0x20) && (ssid->Ssid[i] <= 0x7e) )){
++ RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("ssid has nonprintabl ascii\n"));
++ ret= _FALSE;
++ break;
++ }
++ }
++#endif /* CONFIG_VALIDATE_SSID */
++
++exit:
++
++_func_exit_;
++
++ return ret;
++}
++
++u8 rtw_do_join(_adapter * padapter);
++u8 rtw_do_join(_adapter * padapter)
++{
++ _irqL irqL;
++ _list *plist, *phead;
++ u8* pibss = NULL;
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ _queue *queue = &(pmlmepriv->scanned_queue);
++ u8 ret=_SUCCESS;
++
++_func_enter_;
++
++ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++ phead = get_list_head(queue);
++ plist = get_next(phead);
++
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("\n rtw_do_join: phead = %p; plist = %p \n\n\n", phead, plist));
++
++ pmlmepriv->cur_network.join_res = -2;
++
++ set_fwstate(pmlmepriv, _FW_UNDER_LINKING);
++
++ pmlmepriv->pscanned = plist;
++
++ pmlmepriv->to_join = _TRUE;
++
++ if(_rtw_queue_empty(queue)== _TRUE)
++ {
++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++ _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING);
++
++ //when set_ssid/set_bssid for rtw_do_join(), but scanning queue is empty
++ //we try to issue sitesurvey firstly
++
++ if (pmlmepriv->LinkDetectInfo.bBusyTraffic ==_FALSE
++ || rtw_to_roaming(padapter) > 0
++ )
++ {
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("rtw_do_join(): site survey if scanned_queue is empty\n."));
++ // submit site_survey_cmd
++ if(_SUCCESS!=(ret=rtw_sitesurvey_cmd(padapter, &pmlmepriv->assoc_ssid, 1, NULL, 0)) ) {
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("rtw_do_join(): site survey return error\n."));
++ }
++ }
++
++ goto exit;
++ }
++ else
++ {
++ int select_ret;
++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++ if((select_ret=rtw_select_and_join_from_scanned_queue(pmlmepriv))==_SUCCESS)
++ {
++ pmlmepriv->to_join = _FALSE;
++ _set_timer(&pmlmepriv->assoc_timer, MAX_JOIN_TIMEOUT);
++ }
++ else if(ret == 2)//there is no need to wait for join
++ {
++ ret = _SUCCESS;
++ _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING);
++ rtw_indicate_connect(padapter);
++ }
++ else
++ {
++ if(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE)==_TRUE)
++ {
++ // submit createbss_cmd to change to a ADHOC_MASTER
++
++ //pmlmepriv->lock has been acquired by caller...
++ WLAN_BSSID_EX *pdev_network = &(padapter->registrypriv.dev_network);
++
++ pmlmepriv->fw_state = WIFI_ADHOC_MASTER_STATE;
++
++ pibss = padapter->registrypriv.dev_network.MacAddress;
++
++ _rtw_memset(&pdev_network->Ssid, 0, sizeof(NDIS_802_11_SSID));
++ _rtw_memcpy(&pdev_network->Ssid, &pmlmepriv->assoc_ssid, sizeof(NDIS_802_11_SSID));
++
++ rtw_update_registrypriv_dev_network(padapter);
++
++ rtw_generate_random_ibss(pibss);
++
++ if(rtw_createbss_cmd(padapter)!=_SUCCESS)
++ {
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("***Error=>do_goin: rtw_createbss_cmd status FAIL*** \n "));
++ ret = _FALSE;
++ goto exit;
++ }
++
++ pmlmepriv->to_join = _FALSE;
++
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("***Error=> rtw_select_and_join_from_scanned_queue FAIL under STA_Mode*** \n "));
++
++ }
++ else
++ {
++ // can't associate ; reset under-linking
++ _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING);
++
++#if 0
++ if((check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE))
++ {
++ if(_rtw_memcmp(pmlmepriv->cur_network.network.Ssid.Ssid, pmlmepriv->assoc_ssid.Ssid, pmlmepriv->assoc_ssid.SsidLength))
++ {
++ // for funk to do roaming
++ // funk will reconnect, but funk will not sitesurvey before reconnect
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("for funk to do roaming"));
++ if(pmlmepriv->sitesurveyctrl.traffic_busy==_FALSE)
++ rtw_sitesurvey_cmd(padapter, &pmlmepriv->assoc_ssid, 1, NULL, 0);
++ }
++
++ }
++#endif
++
++ //when set_ssid/set_bssid for rtw_do_join(), but there are no desired bss in scanning queue
++ //we try to issue sitesurvey firstly
++ if(pmlmepriv->LinkDetectInfo.bBusyTraffic==_FALSE
++ || rtw_to_roaming(padapter) > 0
++ )
++ {
++ //DBG_871X("rtw_do_join() when no desired bss in scanning queue \n");
++ if( _SUCCESS!=(ret=rtw_sitesurvey_cmd(padapter, &pmlmepriv->assoc_ssid, 1, NULL, 0)) ){
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("do_join(): site survey return error\n."));
++ }
++ }
++
++
++ }
++
++ }
++
++ }
++
++exit:
++
++_func_exit_;
++
++ return ret;
++}
++
++#ifdef PLATFORM_WINDOWS
++u8 rtw_pnp_set_power_wakeup(_adapter* padapter)
++{
++ u8 res=_SUCCESS;
++
++_func_enter_;
++
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("==>rtw_pnp_set_power_wakeup!!!\n"));
++
++ res = rtw_setstandby_cmd(padapter, 0);
++
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("<==rtw_pnp_set_power_wakeup!!!\n"));
++
++_func_exit_;
++
++ return res;
++}
++
++u8 rtw_pnp_set_power_sleep(_adapter* padapter)
++{
++ u8 res=_SUCCESS;
++
++_func_enter_;
++
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("==>rtw_pnp_set_power_sleep!!!\n"));
++ //DbgPrint("+rtw_pnp_set_power_sleep\n");
++
++ res = rtw_setstandby_cmd(padapter, 1);
++
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("<==rtw_pnp_set_power_sleep!!!\n"));
++
++_func_exit_;
++
++ return res;
++}
++
++u8 rtw_set_802_11_reload_defaults(_adapter * padapter, NDIS_802_11_RELOAD_DEFAULTS reloadDefaults)
++{
++_func_enter_;
++
++ switch( reloadDefaults)
++ {
++ case Ndis802_11ReloadWEPKeys:
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("SetInfo OID_802_11_RELOAD_DEFAULTS : Ndis802_11ReloadWEPKeys\n"));
++ break;
++ }
++
++ // SecClearAllKeys(Adapter);
++ // 8711 CAM was not for En/Decrypt only
++ // so, we can't clear all keys.
++ // should we disable WPAcfg (ox0088) bit 1-2, instead of clear all CAM
++
++ //TO DO...
++
++_func_exit_;
++
++ return _TRUE;
++}
++
++u8 set_802_11_test(_adapter* padapter, NDIS_802_11_TEST *test)
++{
++ u8 ret=_TRUE;
++
++_func_enter_;
++
++ switch(test->Type)
++ {
++ case 1:
++ NdisMIndicateStatus(padapter->hndis_adapter, NDIS_STATUS_MEDIA_SPECIFIC_INDICATION, (PVOID)&test->AuthenticationEvent, test->Length - 8);
++ NdisMIndicateStatusComplete(padapter->hndis_adapter);
++ break;
++
++ case 2:
++ NdisMIndicateStatus(padapter->hndis_adapter, NDIS_STATUS_MEDIA_SPECIFIC_INDICATION, (PVOID)&test->RssiTrigger, sizeof(NDIS_802_11_RSSI));
++ NdisMIndicateStatusComplete(padapter->hndis_adapter);
++ break;
++
++ default:
++ ret=_FALSE;
++ break;
++ }
++
++_func_exit_;
++
++ return ret;
++}
++
++u8 rtw_set_802_11_pmkid(_adapter* padapter, NDIS_802_11_PMKID *pmkid)
++{
++ u8 ret=_SUCCESS;
++
++ return ret;
++}
++
++#endif
++
++u8 rtw_set_802_11_bssid(_adapter* padapter, u8 *bssid)
++{
++ _irqL irqL;
++ u8 status=_SUCCESS;
++ u32 cur_time = 0;
++
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++
++_func_enter_;
++
++ RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_notice_,
++ ("+rtw_set_802_11_bssid: bssid="MAC_FMT"\n", MAC_ARG(bssid) ));
++
++ if ((bssid[0]==0x00 && bssid[1]==0x00 && bssid[2]==0x00 && bssid[3]==0x00 && bssid[4]==0x00 &&bssid[5]==0x00) ||
++ (bssid[0]==0xFF && bssid[1]==0xFF && bssid[2]==0xFF && bssid[3]==0xFF && bssid[4]==0xFF &&bssid[5]==0xFF))
++ {
++ status = _FAIL;
++ goto exit;
++ }
++
++ _enter_critical_bh(&pmlmepriv->lock, &irqL);
++
++
++ DBG_871X("Set BSSID under fw_state=0x%08x\n", get_fwstate(pmlmepriv));
++ if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE) {
++ goto handle_tkip_countermeasure;
++ } else if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == _TRUE) {
++ goto release_mlme_lock;
++ }
++
++ if (check_fwstate(pmlmepriv, _FW_LINKED|WIFI_ADHOC_MASTER_STATE) == _TRUE)
++ {
++ RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ("set_bssid: _FW_LINKED||WIFI_ADHOC_MASTER_STATE\n"));
++
++ if (_rtw_memcmp(&pmlmepriv->cur_network.network.MacAddress, bssid, ETH_ALEN) == _TRUE)
++ {
++ if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _FALSE)
++ goto release_mlme_lock;//it means driver is in WIFI_ADHOC_MASTER_STATE, we needn't create bss again.
++ } else {
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("Set BSSID not the same bssid\n"));
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("set_bssid="MAC_FMT"\n", MAC_ARG(bssid) ));
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("cur_bssid="MAC_FMT"\n", MAC_ARG(pmlmepriv->cur_network.network.MacAddress) ));
++
++ rtw_disassoc_cmd(padapter, 0, _TRUE);
++
++ if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)
++ rtw_indicate_disconnect(padapter);
++
++ rtw_free_assoc_resources(padapter, 1);
++
++ if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)) {
++ _clr_fwstate_(pmlmepriv, WIFI_ADHOC_MASTER_STATE);
++ set_fwstate(pmlmepriv, WIFI_ADHOC_STATE);
++ }
++ }
++ }
++
++handle_tkip_countermeasure:
++ if (rtw_handle_tkip_countermeasure(padapter, __func__) == _FAIL) {
++ status = _FAIL;
++ goto release_mlme_lock;
++ }
++
++ _rtw_memcpy(&pmlmepriv->assoc_bssid, bssid, ETH_ALEN);
++ pmlmepriv->assoc_by_bssid=_TRUE;
++
++ if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE) {
++ pmlmepriv->to_join = _TRUE;
++ }
++ else {
++ status = rtw_do_join(padapter);
++ }
++
++release_mlme_lock:
++ _exit_critical_bh(&pmlmepriv->lock, &irqL);
++
++exit:
++ RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_,
++ ("rtw_set_802_11_bssid: status=%d\n", status));
++
++_func_exit_;
++
++ return status;
++}
++
++u8 rtw_set_802_11_ssid(_adapter* padapter, NDIS_802_11_SSID *ssid)
++{
++ _irqL irqL;
++ u8 status = _SUCCESS;
++ u32 cur_time = 0;
++
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct wlan_network *pnetwork = &pmlmepriv->cur_network;
++
++_func_enter_;
++
++ RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_notice_,
++ ("+rtw_set_802_11_ssid: ssid=[%s] fw_state=0x%08x\n",
++ ssid->Ssid, get_fwstate(pmlmepriv)));
++
++ if(padapter->hw_init_completed==_FALSE){
++ RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_,
++ ("set_ssid: hw_init_completed==_FALSE=>exit!!!\n"));
++ status = _FAIL;
++ goto exit;
++ }
++
++ _enter_critical_bh(&pmlmepriv->lock, &irqL);
++
++ DBG_871X("Set SSID under fw_state=0x%08x\n", get_fwstate(pmlmepriv));
++ if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE) {
++ goto handle_tkip_countermeasure;
++ } else if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == _TRUE) {
++ goto release_mlme_lock;
++ }
++
++ if (check_fwstate(pmlmepriv, _FW_LINKED|WIFI_ADHOC_MASTER_STATE) == _TRUE)
++ {
++ RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_,
++ ("set_ssid: _FW_LINKED||WIFI_ADHOC_MASTER_STATE\n"));
++
++ if ((pmlmepriv->assoc_ssid.SsidLength == ssid->SsidLength) &&
++ (_rtw_memcmp(&pmlmepriv->assoc_ssid.Ssid, ssid->Ssid, ssid->SsidLength) == _TRUE))
++ {
++ if((check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _FALSE))
++ {
++ RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_,
++ ("Set SSID is the same ssid, fw_state=0x%08x\n",
++ get_fwstate(pmlmepriv)));
++
++ if(rtw_is_same_ibss(padapter, pnetwork) == _FALSE)
++ {
++ //if in WIFI_ADHOC_MASTER_STATE | WIFI_ADHOC_STATE, create bss or rejoin again
++ rtw_disassoc_cmd(padapter, 0, _TRUE);
++
++ if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)
++ rtw_indicate_disconnect(padapter);
++
++ rtw_free_assoc_resources(padapter, 1);
++
++ if (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) {
++ _clr_fwstate_(pmlmepriv, WIFI_ADHOC_MASTER_STATE);
++ set_fwstate(pmlmepriv, WIFI_ADHOC_STATE);
++ }
++ }
++ else
++ {
++ goto release_mlme_lock;//it means driver is in WIFI_ADHOC_MASTER_STATE, we needn't create bss again.
++ }
++ }
++#ifdef CONFIG_LPS
++ else {
++ rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_JOINBSS, 1);
++ }
++#endif
++ }
++ else
++ {
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("Set SSID not the same ssid\n"));
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("set_ssid=[%s] len=0x%x\n", ssid->Ssid, (unsigned int)ssid->SsidLength));
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("assoc_ssid=[%s] len=0x%x\n", pmlmepriv->assoc_ssid.Ssid, (unsigned int)pmlmepriv->assoc_ssid.SsidLength));
++
++ rtw_disassoc_cmd(padapter, 0, _TRUE);
++
++ if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)
++ rtw_indicate_disconnect(padapter);
++
++ rtw_free_assoc_resources(padapter, 1);
++
++ if (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) {
++ _clr_fwstate_(pmlmepriv, WIFI_ADHOC_MASTER_STATE);
++ set_fwstate(pmlmepriv, WIFI_ADHOC_STATE);
++ }
++ }
++ }
++
++handle_tkip_countermeasure:
++ if (rtw_handle_tkip_countermeasure(padapter, __func__) == _FAIL) {
++ status = _FAIL;
++ goto release_mlme_lock;
++ }
++
++ if (rtw_validate_ssid(ssid) == _FALSE) {
++ status = _FAIL;
++ goto release_mlme_lock;
++ }
++
++ _rtw_memcpy(&pmlmepriv->assoc_ssid, ssid, sizeof(NDIS_802_11_SSID));
++ pmlmepriv->assoc_by_bssid=_FALSE;
++
++ if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE) {
++ pmlmepriv->to_join = _TRUE;
++ }
++ else {
++ status = rtw_do_join(padapter);
++ }
++
++release_mlme_lock:
++ _exit_critical_bh(&pmlmepriv->lock, &irqL);
++
++exit:
++ RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_,
++ ("-rtw_set_802_11_ssid: status=%d\n", status));
++
++_func_exit_;
++
++ return status;
++
++}
++
++u8 rtw_set_802_11_connect(_adapter* padapter, u8 *bssid, NDIS_802_11_SSID *ssid)
++{
++ _irqL irqL;
++ u8 status = _SUCCESS;
++ u32 cur_time = 0;
++ bool bssid_valid = _TRUE;
++ bool ssid_valid = _TRUE;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++
++_func_enter_;
++
++ if (!ssid || rtw_validate_ssid(ssid) == _FALSE)
++ ssid_valid = _FALSE;
++
++ if (!bssid || rtw_validate_bssid(bssid) == _FALSE)
++ bssid_valid = _FALSE;
++
++ if (ssid_valid == _FALSE && bssid_valid == _FALSE) {
++ DBG_871X(FUNC_ADPT_FMT" ssid:%p, ssid_valid:%d, bssid:%p, bssid_valid:%d\n",
++ FUNC_ADPT_ARG(padapter), ssid, ssid_valid, bssid, bssid_valid);
++ status = _FAIL;
++ goto exit;
++ }
++
++ if(padapter->hw_init_completed==_FALSE){
++ RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_,
++ ("set_ssid: hw_init_completed==_FALSE=>exit!!!\n"));
++ status = _FAIL;
++ goto exit;
++ }
++
++ _enter_critical_bh(&pmlmepriv->lock, &irqL);
++
++ LOG_LEVEL(_drv_info_, FUNC_ADPT_FMT" fw_state=0x%08x\n",
++ FUNC_ADPT_ARG(padapter), get_fwstate(pmlmepriv));
++
++ if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE) {
++ goto handle_tkip_countermeasure;
++ } else if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == _TRUE) {
++ goto release_mlme_lock;
++ }
++
++handle_tkip_countermeasure:
++ if (rtw_handle_tkip_countermeasure(padapter, __func__) == _FAIL) {
++ status = _FAIL;
++ goto release_mlme_lock;
++ }
++
++ if (ssid && ssid_valid)
++ _rtw_memcpy(&pmlmepriv->assoc_ssid, ssid, sizeof(NDIS_802_11_SSID));
++
++ if (bssid && bssid_valid) {
++ _rtw_memcpy(&pmlmepriv->assoc_bssid, bssid, ETH_ALEN);
++ pmlmepriv->assoc_by_bssid = _TRUE;
++ }
++
++ if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE) {
++ pmlmepriv->to_join = _TRUE;
++ }
++ else {
++ status = rtw_do_join(padapter);
++ }
++
++release_mlme_lock:
++ _exit_critical_bh(&pmlmepriv->lock, &irqL);
++
++exit:
++
++_func_exit_;
++
++ return status;
++}
++
++/*
++rtw_set_802_11_infrastructure_mode(~)
++ ### NOTE:#### (!!!!)
++ MUST TAKE CARE THAT BEFORE CALLING THIS FUNC, YOU SHOULD HAVE LOCKED pmlmepriv->lock and scanned_queue->lock in sequence
++*/
++u8 rtw_set_802_11_infrastructure_mode(_adapter* padapter,
++ NDIS_802_11_NETWORK_INFRASTRUCTURE networktype)
++{
++ _irqL irqL;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct wlan_network *cur_network = &pmlmepriv->cur_network;
++ NDIS_802_11_NETWORK_INFRASTRUCTURE* pold_state = &(cur_network->network.InfrastructureMode);
++
++_func_enter_;
++
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_notice_,
++ ("+rtw_set_802_11_infrastructure_mode: old=%d new=%d fw_state=0x%08x\n",
++ *pold_state, networktype, get_fwstate(pmlmepriv)));
++
++ if(*pold_state != networktype)
++ {
++
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,(" change mode!"));
++ //DBG_871X("change mode, old_mode=%d, new_mode=%d, fw_state=0x%x\n", *pold_state, networktype, get_fwstate(pmlmepriv));
++
++ if(*pold_state==Ndis802_11APMode)
++ {
++ //change to other mode from Ndis802_11APMode
++ cur_network->join_res = -1;
++
++#ifdef CONFIG_NATIVEAP_MLME
++ stop_ap_mode(padapter);
++#endif
++ }
++
++ if((check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE) ||(*pold_state==Ndis802_11IBSS))
++ rtw_disassoc_cmd(padapter, 0, _TRUE);
++
++ if((check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE) ||
++ (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)== _TRUE) )
++ rtw_free_assoc_resources(padapter, 0);
++
++ if((*pold_state == Ndis802_11Infrastructure) ||(*pold_state == Ndis802_11IBSS))
++ {
++ if(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)
++ {
++ rtw_indicate_disconnect(padapter); //will clr Linked_state; before this function, we must have chked whether issue dis-assoc_cmd or not
++ }
++ }
++
++ *pold_state = networktype;
++
++ _clr_fwstate_(pmlmepriv, ~WIFI_NULL_STATE);
++
++ switch(networktype)
++ {
++ case Ndis802_11IBSS:
++ set_fwstate(pmlmepriv, WIFI_ADHOC_STATE);
++ break;
++
++ case Ndis802_11Infrastructure:
++ set_fwstate(pmlmepriv, WIFI_STATION_STATE);
++ break;
++
++ case Ndis802_11APMode:
++ set_fwstate(pmlmepriv, WIFI_AP_STATE);
++#ifdef CONFIG_NATIVEAP_MLME
++ start_ap_mode(padapter);
++ //rtw_indicate_connect(padapter);
++#endif
++
++ break;
++
++ case Ndis802_11AutoUnknown:
++ case Ndis802_11InfrastructureMax:
++ break;
++ }
++
++ //SecClearAllKeys(adapter);
++
++ //RT_TRACE(COMP_OID_SET, DBG_LOUD, ("set_infrastructure: fw_state:%x after changing mode\n",
++ // get_fwstate(pmlmepriv) ));
++
++ }
++
++_func_exit_;
++
++ return _TRUE;
++}
++
++
++u8 rtw_set_802_11_disassociate(_adapter *padapter)
++{
++ _irqL irqL;
++ struct mlme_priv * pmlmepriv = &padapter->mlmepriv;
++
++_func_enter_;
++
++ _enter_critical_bh(&pmlmepriv->lock, &irqL);
++
++ if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)
++ {
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("MgntActrtw_set_802_11_disassociate: rtw_indicate_disconnect\n"));
++
++ rtw_disassoc_cmd(padapter, 0, _TRUE);
++ rtw_indicate_disconnect(padapter);
++ //modify for CONFIG_IEEE80211W, none 11w can use it
++ rtw_free_assoc_resources_cmd(padapter);
++ }
++
++ _exit_critical_bh(&pmlmepriv->lock, &irqL);
++
++_func_exit_;
++
++ return _TRUE;
++}
++
++u8 rtw_set_802_11_bssid_list_scan(_adapter* padapter, NDIS_802_11_SSID *pssid, int ssid_max_num)
++{
++ _irqL irqL;
++ struct mlme_priv *pmlmepriv= &padapter->mlmepriv;
++ u8 res=_TRUE;
++
++_func_enter_;
++
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("+rtw_set_802_11_bssid_list_scan(), fw_state=%x\n", get_fwstate(pmlmepriv)));
++
++ if (padapter == NULL) {
++ res=_FALSE;
++ goto exit;
++ }
++ if (padapter->hw_init_completed==_FALSE){
++ res = _FALSE;
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("\n===rtw_set_802_11_bssid_list_scan:hw_init_completed==_FALSE===\n"));
++ goto exit;
++ }
++
++ if ((check_fwstate(pmlmepriv, _FW_UNDER_SURVEY|_FW_UNDER_LINKING) == _TRUE) ||
++ (pmlmepriv->LinkDetectInfo.bBusyTraffic == _TRUE))
++ {
++ // Scan or linking is in progress, do nothing.
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("rtw_set_802_11_bssid_list_scan fail since fw_state = %x\n", get_fwstate(pmlmepriv)));
++ res = _TRUE;
++
++ if(check_fwstate(pmlmepriv, (_FW_UNDER_SURVEY|_FW_UNDER_LINKING))== _TRUE){
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("\n###_FW_UNDER_SURVEY|_FW_UNDER_LINKING\n\n"));
++ } else {
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("\n###pmlmepriv->sitesurveyctrl.traffic_busy==_TRUE\n\n"));
++ }
++ } else {
++ if (rtw_is_scan_deny(padapter)) {
++ DBG_871X(FUNC_ADPT_FMT": scan deny\n", FUNC_ADPT_ARG(padapter));
++ indicate_wx_scan_complete_event(padapter);
++ return _SUCCESS;
++ }
++
++ _enter_critical_bh(&pmlmepriv->lock, &irqL);
++
++ res = rtw_sitesurvey_cmd(padapter, pssid, ssid_max_num, NULL, 0);
++
++ _exit_critical_bh(&pmlmepriv->lock, &irqL);
++ }
++exit:
++
++_func_exit_;
++
++ return res;
++}
++
++u8 rtw_set_802_11_authentication_mode(_adapter* padapter, NDIS_802_11_AUTHENTICATION_MODE authmode)
++{
++ struct security_priv *psecuritypriv = &padapter->securitypriv;
++ int res;
++ u8 ret;
++
++_func_enter_;
++
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("set_802_11_auth.mode(): mode=%x\n", authmode));
++
++ psecuritypriv->ndisauthtype=authmode;
++
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("rtw_set_802_11_authentication_mode:psecuritypriv->ndisauthtype=%d", psecuritypriv->ndisauthtype));
++
++ if(psecuritypriv->ndisauthtype>3)
++ psecuritypriv->dot11AuthAlgrthm=dot11AuthAlgrthm_8021X;
++
++ res=rtw_set_auth(padapter,psecuritypriv);
++
++ if(res==_SUCCESS)
++ ret=_TRUE;
++ else
++ ret=_FALSE;
++
++_func_exit_;
++
++ return ret;
++}
++
++u8 rtw_set_802_11_add_wep(_adapter* padapter, NDIS_802_11_WEP *wep){
++
++ u8 bdefaultkey;
++ u8 btransmitkey;
++ sint keyid,res;
++ struct security_priv* psecuritypriv=&(padapter->securitypriv);
++ u8 ret=_SUCCESS;
++
++_func_enter_;
++
++ bdefaultkey=(wep->KeyIndex & 0x40000000) > 0 ? _FALSE : _TRUE; //for ???
++ btransmitkey= (wep->KeyIndex & 0x80000000) > 0 ? _TRUE : _FALSE; //for ???
++ keyid=wep->KeyIndex & 0x3fffffff;
++
++ if(keyid>4)
++ {
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("MgntActrtw_set_802_11_add_wep:keyid>4=>fail\n"));
++ ret=_FALSE;
++ goto exit;
++ }
++
++ switch(wep->KeyLength)
++ {
++ case 5:
++ psecuritypriv->dot11PrivacyAlgrthm=_WEP40_;
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("MgntActrtw_set_802_11_add_wep:wep->KeyLength=5\n"));
++ break;
++ case 13:
++ psecuritypriv->dot11PrivacyAlgrthm=_WEP104_;
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("MgntActrtw_set_802_11_add_wep:wep->KeyLength=13\n"));
++ break;
++ default:
++ psecuritypriv->dot11PrivacyAlgrthm=_NO_PRIVACY_;
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("MgntActrtw_set_802_11_add_wep:wep->KeyLength!=5 or 13\n"));
++ break;
++ }
++
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("rtw_set_802_11_add_wep:befor memcpy, wep->KeyLength=0x%x wep->KeyIndex=0x%x keyid =%x\n",wep->KeyLength,wep->KeyIndex,keyid));
++
++ _rtw_memcpy(&(psecuritypriv->dot11DefKey[keyid].skey[0]),&(wep->KeyMaterial),wep->KeyLength);
++
++ psecuritypriv->dot11DefKeylen[keyid]=wep->KeyLength;
++
++ psecuritypriv->dot11PrivacyKeyIndex=keyid;
++
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("rtw_set_802_11_add_wep:security key material : %x %x %x %x %x %x %x %x %x %x %x %x %x \n",
++ psecuritypriv->dot11DefKey[keyid].skey[0],psecuritypriv->dot11DefKey[keyid].skey[1],psecuritypriv->dot11DefKey[keyid].skey[2],
++ psecuritypriv->dot11DefKey[keyid].skey[3],psecuritypriv->dot11DefKey[keyid].skey[4],psecuritypriv->dot11DefKey[keyid].skey[5],
++ psecuritypriv->dot11DefKey[keyid].skey[6],psecuritypriv->dot11DefKey[keyid].skey[7],psecuritypriv->dot11DefKey[keyid].skey[8],
++ psecuritypriv->dot11DefKey[keyid].skey[9],psecuritypriv->dot11DefKey[keyid].skey[10],psecuritypriv->dot11DefKey[keyid].skey[11],
++ psecuritypriv->dot11DefKey[keyid].skey[12]));
++
++ res=rtw_set_key(padapter,psecuritypriv, keyid, 1);
++
++ if(res==_FAIL)
++ ret= _FALSE;
++exit:
++
++_func_exit_;
++
++ return ret;
++
++}
++
++u8 rtw_set_802_11_remove_wep(_adapter* padapter, u32 keyindex){
++
++ u8 ret=_SUCCESS;
++
++_func_enter_;
++
++ if (keyindex >= 0x80000000 || padapter == NULL){
++
++ ret=_FALSE;
++ goto exit;
++
++ }
++ else
++ {
++ int res;
++ struct security_priv* psecuritypriv=&(padapter->securitypriv);
++ if( keyindex < 4 ){
++
++ _rtw_memset(&psecuritypriv->dot11DefKey[keyindex], 0, 16);
++
++ res=rtw_set_key(padapter,psecuritypriv,keyindex, 0);
++
++ psecuritypriv->dot11DefKeylen[keyindex]=0;
++
++ if(res==_FAIL)
++ ret=_FAIL;
++
++ }
++ else
++ {
++ ret=_FAIL;
++ }
++
++ }
++
++exit:
++
++_func_exit_;
++
++ return ret;
++
++}
++
++u8 rtw_set_802_11_add_key(_adapter* padapter, NDIS_802_11_KEY *key){
++
++ uint encryptionalgo;
++ u8 * pbssid;
++ struct sta_info *stainfo;
++ u8 bgroup = _FALSE;
++ u8 bgrouptkey = _FALSE;//can be remove later
++ u8 ret=_SUCCESS;
++
++_func_enter_;
++
++ if (((key->KeyIndex & 0x80000000) == 0) && ((key->KeyIndex & 0x40000000) > 0)){
++
++ // It is invalid to clear bit 31 and set bit 30. If the miniport driver encounters this combination,
++ // it must fail the request and return NDIS_STATUS_INVALID_DATA.
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("rtw_set_802_11_add_key: ((key->KeyIndex & 0x80000000) == 0)[=%d] ",(int)(key->KeyIndex & 0x80000000) == 0));
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("rtw_set_802_11_add_key:((key->KeyIndex & 0x40000000) > 0)[=%d]" , (int)(key->KeyIndex & 0x40000000) > 0));
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("rtw_set_802_11_add_key: key->KeyIndex=%d \n" ,(int)key->KeyIndex));
++ ret= _FAIL;
++ goto exit;
++ }
++
++ if(key->KeyIndex & 0x40000000)
++ {
++ // Pairwise key
++
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("OID_802_11_ADD_KEY: +++++ Pairwise key +++++\n"));
++
++ pbssid=get_bssid(&padapter->mlmepriv);
++ stainfo=rtw_get_stainfo(&padapter->stapriv, pbssid);
++
++ if((stainfo!=NULL)&&(padapter->securitypriv.dot11AuthAlgrthm==dot11AuthAlgrthm_8021X)){
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("OID_802_11_ADD_KEY:( stainfo!=NULL)&&(Adapter->securitypriv.dot11AuthAlgrthm==dot11AuthAlgrthm_8021X)\n"));
++ encryptionalgo=stainfo->dot118021XPrivacy;
++ }
++ else{
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("OID_802_11_ADD_KEY: stainfo==NULL)||(Adapter->securitypriv.dot11AuthAlgrthm!=dot11AuthAlgrthm_8021X)\n"));
++ encryptionalgo=padapter->securitypriv.dot11PrivacyAlgrthm;
++ }
++
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("rtw_set_802_11_add_key: (encryptionalgo ==%d)!\n",encryptionalgo ));
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("rtw_set_802_11_add_key: (Adapter->securitypriv.dot11PrivacyAlgrthm ==%d)!\n",padapter->securitypriv.dot11PrivacyAlgrthm));
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("rtw_set_802_11_add_key: (Adapter->securitypriv.dot11AuthAlgrthm ==%d)!\n",padapter->securitypriv.dot11AuthAlgrthm));
++
++ if((stainfo!=NULL)){
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("rtw_set_802_11_add_key: (stainfo->dot118021XPrivacy ==%d)!\n", stainfo->dot118021XPrivacy));
++ }
++
++ if(key->KeyIndex & 0x000000FF){
++ // The key index is specified in the lower 8 bits by values of zero to 255.
++ // The key index should be set to zero for a Pairwise key, and the driver should fail with
++ // NDIS_STATUS_INVALID_DATA if the lower 8 bits is not zero
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,(" key->KeyIndex & 0x000000FF.\n"));
++ ret= _FAIL;
++ goto exit;
++ }
++
++ // check BSSID
++ if (IS_MAC_ADDRESS_BROADCAST(key->BSSID) == _TRUE){
++
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("MacAddr_isBcst(key->BSSID)\n"));
++ ret= _FALSE;
++ goto exit;
++ }
++
++ // Check key length for TKIP.
++ //if(encryptionAlgorithm == RT_ENC_TKIP_ENCRYPTION && key->KeyLength != 32)
++ if((encryptionalgo== _TKIP_)&& (key->KeyLength != 32)){
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("TKIP KeyLength:0x%x != 32\n", key->KeyLength));
++ ret=_FAIL;
++ goto exit;
++
++ }
++
++ // Check key length for AES.
++ if((encryptionalgo== _AES_)&& (key->KeyLength != 16)) {
++ // For our supplicant, EAPPkt9x.vxd, cannot differentiate TKIP and AES case.
++ if(key->KeyLength == 32) {
++ key->KeyLength = 16;
++ } else {
++ ret= _FAIL;
++ goto exit;
++ }
++ }
++
++ // Check key length for WEP. For NDTEST, 2005.01.27, by rcnjko.
++ if( (encryptionalgo== _WEP40_|| encryptionalgo== _WEP104_) && (key->KeyLength != 5 || key->KeyLength != 13)) {
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("WEP KeyLength:0x%x != 5 or 13\n", key->KeyLength));
++ ret=_FAIL;
++ goto exit;
++ }
++
++ bgroup = _FALSE;
++
++ // Check the pairwise key. Added by Annie, 2005-07-06.
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("------------------------------------------\n"));
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("[Pairwise Key set]\n"));
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("------------------------------------------\n"));
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("key index: 0x%8x(0x%8x)\n", key->KeyIndex,(key->KeyIndex&0x3)));
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("key Length: %d\n", key->KeyLength));
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("------------------------------------------\n"));
++
++ }
++ else
++ {
++ // Group key - KeyIndex(BIT30==0)
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("OID_802_11_ADD_KEY: +++++ Group key +++++\n"));
++
++
++ // when add wep key through add key and didn't assigned encryption type before
++ if((padapter->securitypriv.ndisauthtype<=3)&&(padapter->securitypriv.dot118021XGrpPrivacy==0))
++ {
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("keylen=%d( Adapter->securitypriv.dot11PrivacyAlgrthm=%x )padapter->securitypriv.dot118021XGrpPrivacy(%x)\n", key->KeyLength,padapter->securitypriv.dot11PrivacyAlgrthm,padapter->securitypriv.dot118021XGrpPrivacy));
++
++ switch(key->KeyLength)
++ {
++ case 5:
++ padapter->securitypriv.dot11PrivacyAlgrthm=_WEP40_;
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("Adapter->securitypriv.dot11PrivacyAlgrthm= %x key->KeyLength=%u\n", padapter->securitypriv.dot11PrivacyAlgrthm,key->KeyLength));
++ break;
++ case 13:
++ padapter->securitypriv.dot11PrivacyAlgrthm=_WEP104_;
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("Adapter->securitypriv.dot11PrivacyAlgrthm= %x key->KeyLength=%u\n", padapter->securitypriv.dot11PrivacyAlgrthm,key->KeyLength));
++ break;
++ default:
++ padapter->securitypriv.dot11PrivacyAlgrthm=_NO_PRIVACY_;
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("Adapter->securitypriv.dot11PrivacyAlgrthm= %x key->KeyLength=%u \n", padapter->securitypriv.dot11PrivacyAlgrthm,key->KeyLength));
++ break;
++ }
++
++ encryptionalgo=padapter->securitypriv.dot11PrivacyAlgrthm;
++
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,(" Adapter->securitypriv.dot11PrivacyAlgrthm=%x\n", padapter->securitypriv.dot11PrivacyAlgrthm));
++
++ }
++ else
++ {
++ encryptionalgo=padapter->securitypriv.dot118021XGrpPrivacy;
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("( Adapter->securitypriv.dot11PrivacyAlgrthm=%x )encryptionalgo(%x)=padapter->securitypriv.dot118021XGrpPrivacy(%x)keylen=%d\n", padapter->securitypriv.dot11PrivacyAlgrthm,encryptionalgo,padapter->securitypriv.dot118021XGrpPrivacy,key->KeyLength));
++
++ }
++
++ if((check_fwstate(&padapter->mlmepriv, WIFI_ADHOC_STATE)==_TRUE) && (IS_MAC_ADDRESS_BROADCAST(key->BSSID) == _FALSE)) {
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,(" IBSS but BSSID is not Broadcast Address.\n"));
++ ret= _FAIL;
++ goto exit;
++ }
++
++ // Check key length for TKIP
++ if((encryptionalgo== _TKIP_) && (key->KeyLength != 32)) {
++
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,(" TKIP GTK KeyLength:%u != 32\n", key->KeyLength));
++ ret= _FAIL;
++ goto exit;
++
++ } else if(encryptionalgo== _AES_ && (key->KeyLength != 16 && key->KeyLength != 32) ) {
++
++ // Check key length for AES
++ // For NDTEST, we allow keylen=32 in this case. 2005.01.27, by rcnjko.
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("<=== SetInfo, OID_802_11_ADD_KEY: AES GTK KeyLength:%u != 16 or 32\n", key->KeyLength));
++ ret= _FAIL;
++ goto exit;
++ }
++
++ // Change the key length for EAPPkt9x.vxd. Added by Annie, 2005-11-03.
++ if((encryptionalgo== _AES_) && (key->KeyLength == 32) ) {
++ key->KeyLength = 16;
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("AES key length changed: %u\n", key->KeyLength) );
++ }
++
++ if(key->KeyIndex & 0x8000000) {//error ??? 0x8000_0000
++ bgrouptkey = _TRUE;
++ }
++
++ if((check_fwstate(&padapter->mlmepriv, WIFI_ADHOC_STATE)==_TRUE)&&(check_fwstate(&padapter->mlmepriv, _FW_LINKED)==_TRUE))
++ {
++ bgrouptkey = _TRUE;
++ }
++
++ bgroup = _TRUE;
++
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("------------------------------------------\n") );
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("[Group Key set]\n") );
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("------------------------------------------\n")) ;
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("key index: 0x%8x(0x%8x)\n", key->KeyIndex,(key->KeyIndex&0x3)));
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("key Length: %d\n", key->KeyLength)) ;
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("------------------------------------------\n"));
++
++ }
++
++ // If WEP encryption algorithm, just call rtw_set_802_11_add_wep().
++ if((padapter->securitypriv.dot11AuthAlgrthm !=dot11AuthAlgrthm_8021X)&&(encryptionalgo== _WEP40_ || encryptionalgo== _WEP104_))
++ {
++ u8 ret;
++ u32 keyindex;
++ u32 len = FIELD_OFFSET(NDIS_802_11_KEY, KeyMaterial) + key->KeyLength;
++ NDIS_802_11_WEP *wep = &padapter->securitypriv.ndiswep;
++
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("OID_802_11_ADD_KEY: +++++ WEP key +++++\n"));
++
++ wep->Length = len;
++ keyindex = key->KeyIndex&0x7fffffff;
++ wep->KeyIndex = keyindex ;
++ wep->KeyLength = key->KeyLength;
++
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("OID_802_11_ADD_KEY:Before memcpy \n"));
++
++ _rtw_memcpy(wep->KeyMaterial, key->KeyMaterial, key->KeyLength);
++ _rtw_memcpy(&(padapter->securitypriv.dot11DefKey[keyindex].skey[0]), key->KeyMaterial, key->KeyLength);
++
++ padapter->securitypriv.dot11DefKeylen[keyindex]=key->KeyLength;
++ padapter->securitypriv.dot11PrivacyKeyIndex=keyindex;
++
++ ret = rtw_set_802_11_add_wep(padapter, wep);
++
++ goto exit;
++
++ }
++
++ if(key->KeyIndex & 0x20000000){
++ // SetRSC
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("OID_802_11_ADD_KEY: +++++ SetRSC+++++\n"));
++ if(bgroup == _TRUE)
++ {
++ NDIS_802_11_KEY_RSC keysrc=key->KeyRSC & 0x00FFFFFFFFFFFFULL;
++ _rtw_memcpy(&padapter->securitypriv.dot11Grprxpn, &keysrc, 8);
++ }
++ else
++ {
++ NDIS_802_11_KEY_RSC keysrc=key->KeyRSC & 0x00FFFFFFFFFFFFULL;
++ _rtw_memcpy(&padapter->securitypriv.dot11Grptxpn, &keysrc, 8);
++ }
++
++ }
++
++ // Indicate this key idx is used for TX
++ // Save the key in KeyMaterial
++ if(bgroup == _TRUE) // Group transmit key
++ {
++ int res;
++
++ if(bgrouptkey == _TRUE)
++ {
++ padapter->securitypriv.dot118021XGrpKeyid=(u8)key->KeyIndex;
++ }
++
++ if((key->KeyIndex&0x3) == 0){
++ ret = _FAIL;
++ goto exit;
++ }
++
++ _rtw_memset(&padapter->securitypriv.dot118021XGrpKey[(u8)((key->KeyIndex) & 0x03)], 0, 16);
++ _rtw_memset(&padapter->securitypriv.dot118021XGrptxmickey[(u8)((key->KeyIndex) & 0x03)], 0, 16);
++ _rtw_memset(&padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)], 0, 16);
++
++ if((key->KeyIndex & 0x10000000))
++ {
++ _rtw_memcpy(&padapter->securitypriv.dot118021XGrptxmickey[(u8)((key->KeyIndex) & 0x03)], key->KeyMaterial + 16, 8);
++ _rtw_memcpy(&padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)], key->KeyMaterial + 24, 8);
++
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("\n rtw_set_802_11_add_key:rx mic :0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x\n",
++ padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)].skey[0],padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex-1) & 0x03)].skey[1],
++ padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)].skey[2],padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex-1) & 0x03)].skey[3],
++ padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)].skey[4],padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex-1) & 0x03)].skey[5],
++ padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)].skey[6],padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex-1) & 0x03)].skey[7]));
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("\n rtw_set_802_11_add_key:set Group mic key!!!!!!!!\n"));
++
++ }
++ else
++ {
++ _rtw_memcpy(&padapter->securitypriv.dot118021XGrptxmickey[(u8)((key->KeyIndex) & 0x03)], key->KeyMaterial + 24, 8);
++ _rtw_memcpy(&padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)], key->KeyMaterial + 16, 8);
++
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("\n rtw_set_802_11_add_key:rx mic :0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x\n",
++ padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)].skey[0],padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex-1) & 0x03)].skey[1],
++ padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)].skey[2],padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex-1) & 0x03)].skey[3],
++ padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)].skey[4],padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex-1) & 0x03)].skey[5],
++ padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)].skey[6],padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex-1) & 0x03)].skey[7]));
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("\n rtw_set_802_11_add_key:set Group mic key!!!!!!!!\n"));
++
++ }
++
++ //set group key by index
++ _rtw_memcpy(&padapter->securitypriv.dot118021XGrpKey[(u8)((key->KeyIndex) & 0x03)], key->KeyMaterial, key->KeyLength);
++
++ key->KeyIndex=key->KeyIndex & 0x03;
++
++ padapter->securitypriv.binstallGrpkey=_TRUE;
++
++ padapter->securitypriv.bcheck_grpkey=_FALSE;
++
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("reset group key"));
++
++ res=rtw_set_key(padapter,&padapter->securitypriv, key->KeyIndex, 1);
++
++ if(res==_FAIL)
++ ret= _FAIL;
++
++ goto exit;
++
++ }
++ else // Pairwise Key
++ {
++ u8 res;
++
++ pbssid=get_bssid(&padapter->mlmepriv);
++ stainfo=rtw_get_stainfo(&padapter->stapriv , pbssid );
++
++ if(stainfo!=NULL)
++ {
++ _rtw_memset( &stainfo->dot118021x_UncstKey, 0, 16);// clear keybuffer
++
++ _rtw_memcpy(&stainfo->dot118021x_UncstKey, key->KeyMaterial, 16);
++
++ if(encryptionalgo== _TKIP_)
++ {
++ padapter->securitypriv.busetkipkey=_FALSE;
++
++ //_set_timer(&padapter->securitypriv.tkip_timer, 50);
++
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("\n ==========_set_timer\n"));
++
++ // if TKIP, save the Receive/Transmit MIC key in KeyMaterial[128-255]
++ if((key->KeyIndex & 0x10000000)){
++ _rtw_memcpy(&stainfo->dot11tkiptxmickey, key->KeyMaterial + 16, 8);
++ _rtw_memcpy(&stainfo->dot11tkiprxmickey, key->KeyMaterial + 24, 8);
++
++ } else {
++ _rtw_memcpy(&stainfo->dot11tkiptxmickey, key->KeyMaterial + 24, 8);
++ _rtw_memcpy(&stainfo->dot11tkiprxmickey, key->KeyMaterial + 16, 8);
++
++ }
++
++ }
++ else if(encryptionalgo == _AES_)
++ {
++
++ }
++
++
++ //Set key to CAM through H2C command
++ if(bgrouptkey)//never go to here
++ {
++ res=rtw_setstakey_cmd(padapter, (unsigned char *)stainfo, _FALSE);
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("\n rtw_set_802_11_add_key:rtw_setstakey_cmd(group)\n"));
++ }
++ else{
++ res=rtw_setstakey_cmd(padapter, (unsigned char *)stainfo, _TRUE);
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("\n rtw_set_802_11_add_key:rtw_setstakey_cmd(unicast)\n"));
++ }
++
++ if(res ==_FALSE)
++ ret= _FAIL;
++
++ }
++
++ }
++
++exit:
++
++_func_exit_;
++
++ return ret;
++}
++
++u8 rtw_set_802_11_remove_key(_adapter* padapter, NDIS_802_11_REMOVE_KEY *key){
++
++ uint encryptionalgo;
++ u8 * pbssid;
++ struct sta_info *stainfo;
++ u8 bgroup = (key->KeyIndex & 0x4000000) > 0 ? _FALSE: _TRUE;
++ u8 keyIndex = (u8)key->KeyIndex & 0x03;
++ u8 ret=_SUCCESS;
++
++_func_enter_;
++
++ if ((key->KeyIndex & 0xbffffffc) > 0) {
++ ret=_FAIL;
++ goto exit;
++ }
++
++ if (bgroup == _TRUE) {
++ encryptionalgo= padapter->securitypriv.dot118021XGrpPrivacy;
++ // clear group key by index
++ //NdisZeroMemory(Adapter->MgntInfo.SecurityInfo.KeyBuf[keyIndex], MAX_WEP_KEY_LEN);
++ //Adapter->MgntInfo.SecurityInfo.KeyLen[keyIndex] = 0;
++
++ _rtw_memset(&padapter->securitypriv.dot118021XGrpKey[keyIndex], 0, 16);
++
++ //! \todo Send a H2C Command to Firmware for removing this Key in CAM Entry.
++
++ } else {
++
++ pbssid=get_bssid(&padapter->mlmepriv);
++ stainfo=rtw_get_stainfo(&padapter->stapriv , pbssid );
++ if(stainfo !=NULL){
++ encryptionalgo=stainfo->dot118021XPrivacy;
++
++ // clear key by BSSID
++ _rtw_memset(&stainfo->dot118021x_UncstKey, 0, 16);
++
++ //! \todo Send a H2C Command to Firmware for disable this Key in CAM Entry.
++
++ }
++ else{
++ ret= _FAIL;
++ goto exit;
++ }
++ }
++
++exit:
++
++_func_exit_;
++
++ return _TRUE;
++
++}
++
++/*
++* rtw_get_cur_max_rate -
++* @adapter: pointer to _adapter structure
++*
++* Return 0 or 100Kbps
++*/
++u16 rtw_get_cur_max_rate(_adapter *adapter)
++{
++ int i = 0;
++ u8 *p;
++ u16 rate = 0, max_rate = 0;
++ struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ struct registry_priv *pregistrypriv = &adapter->registrypriv;
++ struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
++ WLAN_BSSID_EX *pcur_bss = &pmlmepriv->cur_network.network;
++#ifdef CONFIG_80211N_HT
++ struct rtw_ieee80211_ht_cap *pht_capie;
++ u8 rf_type = 0;
++ u8 bw_40MHz=0, short_GI_20=0, short_GI_40=0;
++ u16 mcs_rate=0;
++ u32 ht_ielen = 0;
++#endif
++
++#ifdef CONFIG_MP_INCLUDED
++ if (adapter->registrypriv.mp_mode == 1)
++ {
++ if (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE)
++ return 0;
++ }
++#endif
++
++ if((check_fwstate(pmlmepriv, _FW_LINKED) != _TRUE)
++ && (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) != _TRUE))
++ return 0;
++
++#ifdef CONFIG_80211N_HT
++ if (pmlmeext->cur_wireless_mode & (WIRELESS_11_24N|WIRELESS_11_5N)) {
++ p = rtw_get_ie(&pcur_bss->IEs[12], _HT_CAPABILITY_IE_, &ht_ielen, pcur_bss->IELength-12);
++ if(p && ht_ielen>0)
++ {
++ pht_capie = (struct rtw_ieee80211_ht_cap *)(p+2);
++
++ _rtw_memcpy(&mcs_rate , pht_capie->supp_mcs_set, 2);
++
++ //bw_40MHz = (pht_capie->cap_info&IEEE80211_HT_CAP_SUP_WIDTH) ? 1:0;
++ //cur_bwmod is updated by beacon, pmlmeinfo is updated by association response
++ bw_40MHz = (pmlmeext->cur_bwmode && (HT_INFO_HT_PARAM_REC_TRANS_CHNL_WIDTH & pmlmeinfo->HT_info.infos[0])) ? 1:0;
++
++ //short_GI = (pht_capie->cap_info&(IEEE80211_HT_CAP_SGI_20|IEEE80211_HT_CAP_SGI_40)) ? 1:0;
++ short_GI_20 = (pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info&IEEE80211_HT_CAP_SGI_20) ? 1:0;
++ short_GI_40 = (pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info&IEEE80211_HT_CAP_SGI_40) ? 1:0;
++
++ rtw_hal_get_hwreg(adapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));
++ max_rate = rtw_mcs_rate(
++ rf_type,
++ bw_40MHz & (pregistrypriv->cbw40_enable),
++ short_GI_20,
++ short_GI_40,
++ pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate
++ );
++ }
++ }
++ else
++#endif //CONFIG_80211N_HT
++ {
++ while( (pcur_bss->SupportedRates[i]!=0) && (pcur_bss->SupportedRates[i]!=0xFF))
++ {
++ rate = pcur_bss->SupportedRates[i]&0x7F;
++ if(rate>max_rate)
++ max_rate = rate;
++ i++;
++ }
++
++ max_rate = max_rate*10/2;
++ }
++
++ return max_rate;
++}
++
++/*
++* rtw_set_scan_mode -
++* @adapter: pointer to _adapter structure
++* @scan_mode:
++*
++* Return _SUCCESS or _FAIL
++*/
++int rtw_set_scan_mode(_adapter *adapter, RT_SCAN_TYPE scan_mode)
++{
++ if(scan_mode != SCAN_ACTIVE && scan_mode != SCAN_PASSIVE)
++ return _FAIL;
++
++ adapter->mlmepriv.scan_mode = scan_mode;
++
++ return _SUCCESS;
++}
++
++/*
++* rtw_set_channel_plan -
++* @adapter: pointer to _adapter structure
++* @channel_plan:
++*
++* Return _SUCCESS or _FAIL
++*/
++int rtw_set_channel_plan(_adapter *adapter, u8 channel_plan)
++{
++ struct registry_priv *pregistrypriv = &adapter->registrypriv;
++ struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
++
++ //handle by cmd_thread to sync with scan operation
++ return rtw_set_chplan_cmd(adapter, channel_plan, 1);
++}
++
++/*
++* rtw_set_country -
++* @adapter: pointer to _adapter structure
++* @country_code: string of country code
++*
++* Return _SUCCESS or _FAIL
++*/
++int rtw_set_country(_adapter *adapter, const char *country_code)
++{
++ int channel_plan = RT_CHANNEL_DOMAIN_WORLD_WIDE_5G;
++
++ DBG_871X("%s country_code:%s\n", __func__, country_code);
++
++ //TODO: should have a table to match country code and RT_CHANNEL_DOMAIN
++ //TODO: should consider 2-character and 3-character country code
++ if(0 == strcmp(country_code, "US"))
++ channel_plan = RT_CHANNEL_DOMAIN_FCC;
++ else if(0 == strcmp(country_code, "EU"))
++ channel_plan = RT_CHANNEL_DOMAIN_ETSI;
++ else if(0 == strcmp(country_code, "JP"))
++ channel_plan = RT_CHANNEL_DOMAIN_MKK;
++ else if(0 == strcmp(country_code, "CN"))
++ channel_plan = RT_CHANNEL_DOMAIN_CHINA;
++ else
++ DBG_871X("%s unknown country_code:%s\n", __FUNCTION__, country_code);
++
++ return rtw_set_channel_plan(adapter, channel_plan);
++}
++
++/*
++* rtw_set_band -
++* @adapter: pointer to _adapter structure
++* @band: band to set
++*
++* Return _SUCCESS or _FAIL
++*/
++int rtw_set_band(_adapter *adapter, enum _BAND band)
++{
++ if (rtw_band_valid(band)) {
++ DBG_871X(FUNC_ADPT_FMT" band:%d\n", FUNC_ADPT_ARG(adapter), band);
++ adapter->setband = band;
++ return _SUCCESS;
++ }
++
++ DBG_871X_LEVEL(_drv_always_, FUNC_ADPT_FMT" band:%d fail\n", FUNC_ADPT_ARG(adapter), band);
++ return _FAIL;
++}
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/core/rtw_iol.c linux-xbian-rpi/drivers/net/wireless/rtl8192cu/core/rtw_iol.c
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/core/rtw_iol.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/core/rtw_iol.c 2015-07-28 01:20:58.301668422 +0200
+@@ -0,0 +1,262 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++
++#include<rtw_iol.h>
++
++#ifdef CONFIG_IOL
++struct xmit_frame *rtw_IOL_accquire_xmit_frame(ADAPTER *adapter)
++{
++ struct xmit_frame *xmit_frame;
++ struct xmit_buf *xmitbuf;
++ struct pkt_attrib *pattrib;
++ struct xmit_priv *pxmitpriv = &(adapter->xmitpriv);
++
++#if 1
++ if ((xmit_frame = rtw_alloc_xmitframe(pxmitpriv)) == NULL)
++ {
++ DBG_871X("%s rtw_alloc_xmitframe return null\n", __FUNCTION__);
++ goto exit;
++ }
++
++ if ((xmitbuf = rtw_alloc_xmitbuf(pxmitpriv)) == NULL)
++ {
++ DBG_871X("%s rtw_alloc_xmitbuf return null\n", __FUNCTION__);
++ rtw_free_xmitframe(pxmitpriv, xmit_frame);
++ xmit_frame=NULL;
++ goto exit;
++ }
++
++ xmit_frame->frame_tag = MGNT_FRAMETAG;
++ xmit_frame->pxmitbuf = xmitbuf;
++ xmit_frame->buf_addr = xmitbuf->pbuf;
++ xmitbuf->priv_data = xmit_frame;
++
++ pattrib = &xmit_frame->attrib;
++ update_mgntframe_attrib(adapter, pattrib);
++ pattrib->qsel = 0x10;
++ pattrib->pktlen = pattrib->last_txcmdsz = 0;
++
++#else
++ if ((xmit_frame = alloc_mgtxmitframe(pxmitpriv)) == NULL)
++ {
++ DBG_871X("%s alloc_mgtxmitframe return null\n", __FUNCTION__);
++ }
++ else {
++ pattrib = &xmit_frame->attrib;
++ update_mgntframe_attrib(adapter, pattrib);
++ pattrib->qsel = 0x10;
++ pattrib->pktlen = pattrib->last_txcmdsz = 0;
++ }
++#endif
++
++exit:
++ return xmit_frame;
++}
++
++
++int rtw_IOL_append_cmds(struct xmit_frame *xmit_frame, u8 *IOL_cmds, u32 cmd_len)
++{
++ struct pkt_attrib *pattrib = &xmit_frame->attrib;
++ u16 buf_offset;
++ u32 ori_len;
++
++//Todo: bulkout without this offset
++#ifdef CONFIG_USB_HCI
++ buf_offset = TXDESC_OFFSET;
++#else
++ buf_offset = 0;
++#endif
++
++ ori_len = buf_offset+pattrib->pktlen;
++
++ //check if the io_buf can accommodate new cmds
++ if(ori_len + cmd_len + 8 > MAX_XMITBUF_SZ) {
++ DBG_871X("%s %u is large than MAX_XMITBUF_SZ:%u, can't accommodate new cmds\n", __FUNCTION__
++ , ori_len + cmd_len + 8, MAX_XMITBUF_SZ);
++ return _FAIL;
++ }
++
++ _rtw_memcpy(xmit_frame->buf_addr + buf_offset + pattrib->pktlen, IOL_cmds, cmd_len);
++ pattrib->pktlen += cmd_len;
++ pattrib->last_txcmdsz += cmd_len;
++
++ //DBG_871X("%s ori:%u + cmd_len:%u = %u\n", __FUNCTION__, ori_len, cmd_len, buf_offset+pattrib->pktlen);
++
++ return _SUCCESS;
++}
++
++int rtw_IOL_append_LLT_cmd(struct xmit_frame *xmit_frame, u8 page_boundary)
++{
++ IOL_CMD cmd = {0x0, IOL_CMD_LLT, 0x0, 0x0};
++
++ RTW_PUT_BE32((u8*)&cmd.value, (u32)page_boundary);
++
++ return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, 8);
++}
++
++int _rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value)
++{
++ IOL_CMD cmd = {0x0, IOL_CMD_WB_REG, 0x0, 0x0};
++
++ RTW_PUT_BE16((u8*)&cmd.address, (u16)addr);
++ RTW_PUT_BE32((u8*)&cmd.value, (u32)value);
++
++ return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, 8);
++}
++
++int _rtw_IOL_append_WW_cmd(struct xmit_frame *xmit_frame, u16 addr, u16 value)
++{
++ IOL_CMD cmd = {0x0, IOL_CMD_WW_REG, 0x0, 0x0};
++
++ RTW_PUT_BE16((u8*)&cmd.address, (u16)addr);
++ RTW_PUT_BE32((u8*)&cmd.value, (u32)value);
++
++ return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, 8);
++}
++
++int _rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value)
++{
++ IOL_CMD cmd = {0x0, IOL_CMD_WD_REG, 0x0, 0x0};
++ u8* pos = (u8 *)&cmd;
++
++ RTW_PUT_BE16((u8*)&cmd.address, (u16)addr);
++ RTW_PUT_BE32((u8*)&cmd.value, (u32)value);
++
++ return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, 8);
++}
++
++#ifdef DBG_IO
++int dbg_rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value, const char *caller, const int line)
++{
++ if (match_write_sniff_ranges(addr, 1))
++ DBG_871X("DBG_IO %s:%d IOL_WB(0x%04x, 0x%02x)\n", caller, line, addr, value);
++
++ return _rtw_IOL_append_WB_cmd(xmit_frame, addr, value);
++}
++
++int dbg_rtw_IOL_append_WW_cmd(struct xmit_frame *xmit_frame, u16 addr, u16 value, const char *caller, const int line)
++{
++ if (match_write_sniff_ranges(addr, 2))
++ DBG_871X("DBG_IO %s:%d IOL_WW(0x%04x, 0x%04x)\n", caller, line, addr, value);
++
++ return _rtw_IOL_append_WW_cmd(xmit_frame, addr, value);
++}
++
++int dbg_rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value, const char *caller, const int line)
++{
++ if (match_write_sniff_ranges(addr, 4))
++ DBG_871X("DBG_IO %s:%d IOL_WD(0x%04x, 0x%08x)\n", caller, line, addr, value);
++
++ return _rtw_IOL_append_WD_cmd(xmit_frame, addr, value);
++}
++#endif
++
++int rtw_IOL_append_DELAY_US_cmd(struct xmit_frame *xmit_frame, u16 us)
++{
++ IOL_CMD cmd = {0x0, IOL_CMD_DELAY_US, 0x0, 0x0};
++
++ RTW_PUT_BE32((u8*)&cmd.value, (u32)us);
++
++ //DBG_871X("%s %u\n", __FUNCTION__, us);
++
++ return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, 8);
++}
++
++int rtw_IOL_append_DELAY_MS_cmd(struct xmit_frame *xmit_frame, u16 ms)
++{
++ IOL_CMD cmd = {0x0, IOL_CMD_DELAY_MS, 0x0, 0x0};
++
++ RTW_PUT_BE32((u8*)&cmd.value, (u32)ms);
++
++ //DBG_871X("%s %u\n", __FUNCTION__, ms);
++
++ return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, 8);
++}
++
++int rtw_IOL_append_END_cmd(struct xmit_frame *xmit_frame)
++{
++ struct pkt_attrib *pattrib = &xmit_frame->attrib;
++ u16 buf_offset;
++ u32 ori_len;
++ IOL_CMD end_cmd = {0x0, IOL_CMD_END, 0x0, 0x0};
++
++//Todo: bulkout without this offset
++#ifdef CONFIG_USB_HCI
++ buf_offset = TXDESC_OFFSET;
++#else
++ buf_offset = 0;
++#endif
++
++ ori_len = buf_offset+pattrib->pktlen;
++
++ //check if the io_buf can accommodate new cmds
++ if(ori_len + 8 > MAX_XMITBUF_SZ) {
++ DBG_871X("%s %u is large than MAX_XMITBUF_SZ:%u, can't accommodate end cmd\n", __FUNCTION__
++ , ori_len + 8, MAX_XMITBUF_SZ);
++ return _FAIL;
++ }
++
++ _rtw_memcpy(xmit_frame->buf_addr + buf_offset + pattrib->pktlen, (u8*)&end_cmd, 8);
++ pattrib->pktlen += 8;
++ pattrib->last_txcmdsz += 8;
++
++ //DBG_871X("%s ori:%u + 8 = %u\n", __FUNCTION__ , ori_len, buf_offset+pattrib->pktlen);
++
++ return _SUCCESS;
++}
++
++int rtw_IOL_exec_cmds_sync(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms)
++{
++ return rtw_hal_iol_cmd(adapter, xmit_frame, max_wating_ms);
++}
++
++int rtw_IOL_exec_cmd_array_sync(PADAPTER adapter, u8 *IOL_cmds, u32 cmd_num, u32 max_wating_ms)
++{
++ struct xmit_frame *xmit_frame;
++
++ if((xmit_frame=rtw_IOL_accquire_xmit_frame(adapter)) == NULL)
++ return _FAIL;
++
++ if(rtw_IOL_append_cmds(xmit_frame, IOL_cmds, cmd_num<<3) == _FAIL)
++ return _FAIL;
++
++ return rtw_IOL_exec_cmds_sync(adapter, xmit_frame, max_wating_ms);
++}
++
++int rtw_IOL_exec_empty_cmds_sync(ADAPTER *adapter, u32 max_wating_ms)
++{
++ IOL_CMD end_cmd = {0x0, IOL_CMD_END, 0x0, 0x0};
++ return rtw_IOL_exec_cmd_array_sync(adapter, (u8*)&end_cmd, 1, max_wating_ms);
++}
++
++bool rtw_IOL_applied(ADAPTER *adapter)
++{
++ if(adapter->registrypriv.force_iol)
++ return _TRUE;
++
++#ifdef CONFIG_USB_HCI
++ if(!adapter_to_dvobj(adapter)->ishighspeed)
++ return _TRUE;
++#endif
++
++ return _FALSE;
++}
++
++#endif //CONFIG_IOL
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/core/rtw_mlme.c linux-xbian-rpi/drivers/net/wireless/rtl8192cu/core/rtw_mlme.c
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/core/rtw_mlme.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/core/rtw_mlme.c 2015-07-28 01:20:58.301668422 +0200
+@@ -0,0 +1,3966 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#define _RTW_MLME_C_
++
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++#include <recv_osdep.h>
++#include <xmit_osdep.h>
++#include <hal_intf.h>
++#include <mlme_osdep.h>
++#include <sta_info.h>
++#include <wifi.h>
++#include <wlan_bssdef.h>
++#include <rtw_ioctl_set.h>
++
++extern void indicate_wx_scan_complete_event(_adapter *padapter);
++extern u8 rtw_do_join(_adapter * padapter);
++
++#ifdef CONFIG_DISABLE_MCS13TO15
++extern unsigned char MCS_rate_2R_MCS13TO15_OFF[16];
++extern unsigned char MCS_rate_2R[16];
++#else //CONFIG_DISABLE_MCS13TO15
++extern unsigned char MCS_rate_2R[16];
++#endif //CONFIG_DISABLE_MCS13TO15
++extern unsigned char MCS_rate_1R[16];
++
++sint _rtw_init_mlme_priv (_adapter* padapter)
++{
++ sint i;
++ u8 *pbuf;
++ struct wlan_network *pnetwork;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ sint res = _SUCCESS;
++
++_func_enter_;
++
++ // We don't need to memset padapter->XXX to zero, because adapter is allocated by rtw_zvmalloc().
++ //_rtw_memset((u8 *)pmlmepriv, 0, sizeof(struct mlme_priv));
++
++ pmlmepriv->nic_hdl = (u8 *)padapter;
++
++ pmlmepriv->pscanned = NULL;
++ pmlmepriv->fw_state = 0;
++ pmlmepriv->cur_network.network.InfrastructureMode = Ndis802_11AutoUnknown;
++ pmlmepriv->scan_mode=SCAN_ACTIVE;// 1: active, 0: pasive. Maybe someday we should rename this varable to "active_mode" (Jeff)
++
++ _rtw_spinlock_init(&(pmlmepriv->lock));
++ _rtw_init_queue(&(pmlmepriv->free_bss_pool));
++ _rtw_init_queue(&(pmlmepriv->scanned_queue));
++
++ set_scanned_network_val(pmlmepriv, 0);
++
++ _rtw_memset(&pmlmepriv->assoc_ssid,0,sizeof(NDIS_802_11_SSID));
++
++ pbuf = rtw_zvmalloc(MAX_BSS_CNT * (sizeof(struct wlan_network)));
++
++ if (pbuf == NULL){
++ res=_FAIL;
++ goto exit;
++ }
++ pmlmepriv->free_bss_buf = pbuf;
++
++ pnetwork = (struct wlan_network *)pbuf;
++
++ for(i = 0; i < MAX_BSS_CNT; i++)
++ {
++ _rtw_init_listhead(&(pnetwork->list));
++
++ rtw_list_insert_tail(&(pnetwork->list), &(pmlmepriv->free_bss_pool.queue));
++
++ pnetwork++;
++ }
++
++ //allocate DMA-able/Non-Page memory for cmd_buf and rsp_buf
++
++ rtw_clear_scan_deny(padapter);
++
++ rtw_init_mlme_timer(padapter);
++
++exit:
++
++_func_exit_;
++
++ return res;
++}
++
++void rtw_mfree_mlme_priv_lock (struct mlme_priv *pmlmepriv);
++void rtw_mfree_mlme_priv_lock (struct mlme_priv *pmlmepriv)
++{
++ _rtw_spinlock_free(&pmlmepriv->lock);
++ _rtw_spinlock_free(&(pmlmepriv->free_bss_pool.lock));
++ _rtw_spinlock_free(&(pmlmepriv->scanned_queue.lock));
++}
++
++static void rtw_free_mlme_ie_data(u8 **ppie, u32 *plen)
++{
++ if(*ppie)
++ {
++ rtw_mfree(*ppie, *plen);
++ *plen = 0;
++ *ppie=NULL;
++ }
++}
++
++void rtw_free_mlme_priv_ie_data(struct mlme_priv *pmlmepriv)
++{
++#if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME)
++ rtw_buf_free(&pmlmepriv->assoc_req, &pmlmepriv->assoc_req_len);
++ rtw_buf_free(&pmlmepriv->assoc_rsp, &pmlmepriv->assoc_rsp_len);
++ rtw_free_mlme_ie_data(&pmlmepriv->wps_beacon_ie, &pmlmepriv->wps_beacon_ie_len);
++ rtw_free_mlme_ie_data(&pmlmepriv->wps_probe_req_ie, &pmlmepriv->wps_probe_req_ie_len);
++ rtw_free_mlme_ie_data(&pmlmepriv->wps_probe_resp_ie, &pmlmepriv->wps_probe_resp_ie_len);
++ rtw_free_mlme_ie_data(&pmlmepriv->wps_assoc_resp_ie, &pmlmepriv->wps_assoc_resp_ie_len);
++
++ rtw_free_mlme_ie_data(&pmlmepriv->p2p_beacon_ie, &pmlmepriv->p2p_beacon_ie_len);
++ rtw_free_mlme_ie_data(&pmlmepriv->p2p_probe_req_ie, &pmlmepriv->p2p_probe_req_ie_len);
++ rtw_free_mlme_ie_data(&pmlmepriv->p2p_probe_resp_ie, &pmlmepriv->p2p_probe_resp_ie_len);
++ rtw_free_mlme_ie_data(&pmlmepriv->p2p_go_probe_resp_ie, &pmlmepriv->p2p_go_probe_resp_ie_len);
++ rtw_free_mlme_ie_data(&pmlmepriv->p2p_assoc_req_ie, &pmlmepriv->p2p_assoc_req_ie_len);
++#endif
++
++#if defined(CONFIG_WFD) && defined(CONFIG_IOCTL_CFG80211)
++ rtw_free_mlme_ie_data(&pmlmepriv->wfd_beacon_ie, &pmlmepriv->wfd_beacon_ie_len);
++ rtw_free_mlme_ie_data(&pmlmepriv->wfd_probe_req_ie, &pmlmepriv->wfd_probe_req_ie_len);
++ rtw_free_mlme_ie_data(&pmlmepriv->wfd_probe_resp_ie, &pmlmepriv->wfd_probe_resp_ie_len);
++ rtw_free_mlme_ie_data(&pmlmepriv->wfd_go_probe_resp_ie, &pmlmepriv->wfd_go_probe_resp_ie_len);
++ rtw_free_mlme_ie_data(&pmlmepriv->wfd_assoc_req_ie, &pmlmepriv->wfd_assoc_req_ie_len);
++#endif
++
++}
++
++void _rtw_free_mlme_priv (struct mlme_priv *pmlmepriv)
++{
++_func_enter_;
++
++ rtw_free_mlme_priv_ie_data(pmlmepriv);
++
++ if(pmlmepriv){
++ rtw_mfree_mlme_priv_lock (pmlmepriv);
++
++ if (pmlmepriv->free_bss_buf) {
++ rtw_vmfree(pmlmepriv->free_bss_buf, MAX_BSS_CNT * sizeof(struct wlan_network));
++ }
++ }
++_func_exit_;
++}
++
++sint _rtw_enqueue_network(_queue *queue, struct wlan_network *pnetwork)
++{
++ _irqL irqL;
++
++_func_enter_;
++
++ if (pnetwork == NULL)
++ goto exit;
++
++ _enter_critical_bh(&queue->lock, &irqL);
++
++ rtw_list_insert_tail(&pnetwork->list, &queue->queue);
++
++ _exit_critical_bh(&queue->lock, &irqL);
++
++exit:
++
++_func_exit_;
++
++ return _SUCCESS;
++}
++
++struct wlan_network *_rtw_dequeue_network(_queue *queue)
++{
++ _irqL irqL;
++
++ struct wlan_network *pnetwork;
++
++_func_enter_;
++
++ _enter_critical_bh(&queue->lock, &irqL);
++
++ if (_rtw_queue_empty(queue) == _TRUE)
++
++ pnetwork = NULL;
++
++ else
++ {
++ pnetwork = LIST_CONTAINOR(get_next(&queue->queue), struct wlan_network, list);
++
++ rtw_list_delete(&(pnetwork->list));
++ }
++
++ _exit_critical_bh(&queue->lock, &irqL);
++
++_func_exit_;
++
++ return pnetwork;
++}
++
++struct wlan_network *_rtw_alloc_network(struct mlme_priv *pmlmepriv )//(_queue *free_queue)
++{
++ _irqL irqL;
++ struct wlan_network *pnetwork;
++ _queue *free_queue = &pmlmepriv->free_bss_pool;
++ _list* plist = NULL;
++
++_func_enter_;
++
++ _enter_critical_bh(&free_queue->lock, &irqL);
++
++ if (_rtw_queue_empty(free_queue) == _TRUE) {
++ pnetwork=NULL;
++ goto exit;
++ }
++ plist = get_next(&(free_queue->queue));
++
++ pnetwork = LIST_CONTAINOR(plist , struct wlan_network, list);
++
++ rtw_list_delete(&pnetwork->list);
++
++ RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("_rtw_alloc_network: ptr=%p\n", plist));
++ pnetwork->network_type = 0;
++ pnetwork->fixed = _FALSE;
++ pnetwork->last_scanned = rtw_get_current_time();
++ pnetwork->aid=0;
++ pnetwork->join_res=0;
++
++ pmlmepriv->num_of_scanned ++;
++
++exit:
++ _exit_critical_bh(&free_queue->lock, &irqL);
++
++_func_exit_;
++
++ return pnetwork;
++}
++
++void _rtw_free_network(struct mlme_priv *pmlmepriv ,struct wlan_network *pnetwork, u8 isfreeall)
++{
++ u32 curr_time, delta_time;
++ u32 lifetime = SCANQUEUE_LIFETIME;
++ _irqL irqL;
++ _queue *free_queue = &(pmlmepriv->free_bss_pool);
++
++_func_enter_;
++
++ if (pnetwork == NULL)
++ goto exit;
++
++ if (pnetwork->fixed == _TRUE)
++ goto exit;
++
++ curr_time = rtw_get_current_time();
++
++ if ( (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)==_TRUE ) ||
++ (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE)==_TRUE ) )
++ lifetime = 1;
++
++ if(!isfreeall)
++ {
++#ifdef PLATFORM_WINDOWS
++
++ delta_time = (curr_time -pnetwork->last_scanned)/10;
++
++ if(delta_time < lifetime*1000000)// unit:usec
++ {
++ goto exit;
++ }
++
++#endif
++
++#ifdef PLATFORM_LINUX
++
++ delta_time = (curr_time -pnetwork->last_scanned)/HZ;
++
++ if(delta_time < lifetime)// unit:sec
++ {
++ goto exit;
++ }
++
++#endif
++
++#ifdef PLATFORM_FREEBSD
++ //i think needs to check again
++ delta_time = (curr_time -pnetwork->last_scanned)/hz;
++
++ if(delta_time < lifetime)// unit:sec
++ {
++ goto exit;
++ }
++
++#endif
++ }
++
++ _enter_critical_bh(&free_queue->lock, &irqL);
++
++ rtw_list_delete(&(pnetwork->list));
++
++ rtw_list_insert_tail(&(pnetwork->list),&(free_queue->queue));
++
++ pmlmepriv->num_of_scanned --;
++
++
++ //DBG_871X("_rtw_free_network:SSID=%s\n", pnetwork->network.Ssid.Ssid);
++
++ _exit_critical_bh(&free_queue->lock, &irqL);
++
++exit:
++
++_func_exit_;
++
++}
++
++void _rtw_free_network_nolock(struct mlme_priv *pmlmepriv, struct wlan_network *pnetwork)
++{
++
++ _queue *free_queue = &(pmlmepriv->free_bss_pool);
++
++_func_enter_;
++
++ if (pnetwork == NULL)
++ goto exit;
++
++ if (pnetwork->fixed == _TRUE)
++ goto exit;
++
++ //_enter_critical(&free_queue->lock, &irqL);
++
++ rtw_list_delete(&(pnetwork->list));
++
++ rtw_list_insert_tail(&(pnetwork->list), get_list_head(free_queue));
++
++ pmlmepriv->num_of_scanned --;
++
++ //_exit_critical(&free_queue->lock, &irqL);
++
++exit:
++
++_func_exit_;
++
++}
++
++
++/*
++ return the wlan_network with the matching addr
++
++ Shall be calle under atomic context... to avoid possible racing condition...
++*/
++struct wlan_network *_rtw_find_network(_queue *scanned_queue, u8 *addr)
++{
++
++ //_irqL irqL;
++ _list *phead, *plist;
++ struct wlan_network *pnetwork = NULL;
++ u8 zero_addr[ETH_ALEN] = {0,0,0,0,0,0};
++
++_func_enter_;
++
++ if(_rtw_memcmp(zero_addr, addr, ETH_ALEN)){
++ pnetwork=NULL;
++ goto exit;
++ }
++
++ //_enter_critical_bh(&scanned_queue->lock, &irqL);
++
++ phead = get_list_head(scanned_queue);
++ plist = get_next(phead);
++
++ while (plist != phead)
++ {
++ pnetwork = LIST_CONTAINOR(plist, struct wlan_network ,list);
++
++ if (_rtw_memcmp(addr, pnetwork->network.MacAddress, ETH_ALEN) == _TRUE)
++ break;
++
++ plist = get_next(plist);
++ }
++
++ if(plist == phead)
++ pnetwork = NULL;
++
++ //_exit_critical_bh(&scanned_queue->lock, &irqL);
++
++exit:
++
++_func_exit_;
++
++ return pnetwork;
++
++}
++
++
++void _rtw_free_network_queue(_adapter *padapter, u8 isfreeall)
++{
++ _irqL irqL;
++ _list *phead, *plist;
++ struct wlan_network *pnetwork;
++ struct mlme_priv* pmlmepriv = &padapter->mlmepriv;
++ _queue *scanned_queue = &pmlmepriv->scanned_queue;
++
++_func_enter_;
++
++
++ _enter_critical_bh(&scanned_queue->lock, &irqL);
++
++ phead = get_list_head(scanned_queue);
++ plist = get_next(phead);
++
++ while (rtw_end_of_queue_search(phead, plist) == _FALSE)
++ {
++
++ pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
++
++ plist = get_next(plist);
++
++ _rtw_free_network(pmlmepriv,pnetwork, isfreeall);
++
++ }
++
++ _exit_critical_bh(&scanned_queue->lock, &irqL);
++
++_func_exit_;
++
++}
++
++
++
++
++sint rtw_if_up(_adapter *padapter) {
++
++ sint res;
++_func_enter_;
++
++ if( padapter->bDriverStopped || padapter->bSurpriseRemoved ||
++ (check_fwstate(&padapter->mlmepriv, _FW_LINKED)== _FALSE)){
++ RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("rtw_if_up:bDriverStopped(%d) OR bSurpriseRemoved(%d)", padapter->bDriverStopped, padapter->bSurpriseRemoved));
++ res=_FALSE;
++ }
++ else
++ res= _TRUE;
++
++_func_exit_;
++ return res;
++}
++
++
++void rtw_generate_random_ibss(u8* pibss)
++{
++ u32 curtime = rtw_get_current_time();
++
++_func_enter_;
++ pibss[0] = 0x02; //in ad-hoc mode bit1 must set to 1
++ pibss[1] = 0x11;
++ pibss[2] = 0x87;
++ pibss[3] = (u8)(curtime & 0xff) ;//p[0];
++ pibss[4] = (u8)((curtime>>8) & 0xff) ;//p[1];
++ pibss[5] = (u8)((curtime>>16) & 0xff) ;//p[2];
++_func_exit_;
++ return;
++}
++
++u8 *rtw_get_capability_from_ie(u8 *ie)
++{
++ return (ie + 8 + 2);
++}
++
++
++u16 rtw_get_capability(WLAN_BSSID_EX *bss)
++{
++ u16 val;
++_func_enter_;
++
++ _rtw_memcpy((u8 *)&val, rtw_get_capability_from_ie(bss->IEs), 2);
++
++_func_exit_;
++ return le16_to_cpu(val);
++}
++
++u8 *rtw_get_timestampe_from_ie(u8 *ie)
++{
++ return (ie + 0);
++}
++
++u8 *rtw_get_beacon_interval_from_ie(u8 *ie)
++{
++ return (ie + 8);
++}
++
++
++int rtw_init_mlme_priv (_adapter *padapter)//(struct mlme_priv *pmlmepriv)
++{
++ int res;
++_func_enter_;
++ res = _rtw_init_mlme_priv(padapter);// (pmlmepriv);
++_func_exit_;
++ return res;
++}
++
++void rtw_free_mlme_priv (struct mlme_priv *pmlmepriv)
++{
++_func_enter_;
++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("rtw_free_mlme_priv\n"));
++ _rtw_free_mlme_priv (pmlmepriv);
++_func_exit_;
++}
++
++int rtw_enqueue_network(_queue *queue, struct wlan_network *pnetwork);
++int rtw_enqueue_network(_queue *queue, struct wlan_network *pnetwork)
++{
++ int res;
++_func_enter_;
++ res = _rtw_enqueue_network(queue, pnetwork);
++_func_exit_;
++ return res;
++}
++
++
++#ifndef PLATFORM_FREEBSD //Baron
++static struct wlan_network *rtw_dequeue_network(_queue *queue)
++{
++ struct wlan_network *pnetwork;
++_func_enter_;
++ pnetwork = _rtw_dequeue_network(queue);
++_func_exit_;
++ return pnetwork;
++}
++#endif //PLATFORM_FREEBSD
++
++struct wlan_network *rtw_alloc_network(struct mlme_priv *pmlmepriv );
++struct wlan_network *rtw_alloc_network(struct mlme_priv *pmlmepriv )//(_queue *free_queue)
++{
++ struct wlan_network *pnetwork;
++_func_enter_;
++ pnetwork = _rtw_alloc_network(pmlmepriv);
++_func_exit_;
++ return pnetwork;
++}
++
++void rtw_free_network(struct mlme_priv *pmlmepriv, struct wlan_network *pnetwork, u8 is_freeall);
++void rtw_free_network(struct mlme_priv *pmlmepriv, struct wlan_network *pnetwork, u8 is_freeall)//(struct wlan_network *pnetwork, _queue *free_queue)
++{
++_func_enter_;
++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("rtw_free_network==> ssid = %s \n\n" , pnetwork->network.Ssid.Ssid));
++ _rtw_free_network(pmlmepriv, pnetwork, is_freeall);
++_func_exit_;
++}
++
++void rtw_free_network_nolock(struct mlme_priv *pmlmepriv, struct wlan_network *pnetwork );
++void rtw_free_network_nolock(struct mlme_priv *pmlmepriv, struct wlan_network *pnetwork )
++{
++_func_enter_;
++ //RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("rtw_free_network==> ssid = %s \n\n" , pnetwork->network.Ssid.Ssid));
++ _rtw_free_network_nolock(pmlmepriv, pnetwork);
++_func_exit_;
++}
++
++
++void rtw_free_network_queue(_adapter* dev, u8 isfreeall)
++{
++_func_enter_;
++ _rtw_free_network_queue(dev, isfreeall);
++_func_exit_;
++}
++
++/*
++ return the wlan_network with the matching addr
++
++ Shall be calle under atomic context... to avoid possible racing condition...
++*/
++struct wlan_network *rtw_find_network(_queue *scanned_queue, u8 *addr)
++{
++ struct wlan_network *pnetwork = _rtw_find_network(scanned_queue, addr);
++
++ return pnetwork;
++}
++
++int rtw_is_same_ibss(_adapter *adapter, struct wlan_network *pnetwork)
++{
++ int ret=_TRUE;
++ struct security_priv *psecuritypriv = &adapter->securitypriv;
++
++ if ( (psecuritypriv->dot11PrivacyAlgrthm != _NO_PRIVACY_ ) &&
++ ( pnetwork->network.Privacy == 0 ) )
++ {
++ ret=_FALSE;
++ }
++ else if((psecuritypriv->dot11PrivacyAlgrthm == _NO_PRIVACY_ ) &&
++ ( pnetwork->network.Privacy == 1 ) )
++ {
++ ret=_FALSE;
++ }
++ else
++ {
++ ret=_TRUE;
++ }
++
++ return ret;
++
++}
++
++inline int is_same_ess(WLAN_BSSID_EX *a, WLAN_BSSID_EX *b);
++inline int is_same_ess(WLAN_BSSID_EX *a, WLAN_BSSID_EX *b)
++{
++ //RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("(%s,%d)(%s,%d)\n",
++ // a->Ssid.Ssid,a->Ssid.SsidLength,b->Ssid.Ssid,b->Ssid.SsidLength));
++ return (a->Ssid.SsidLength == b->Ssid.SsidLength)
++ && _rtw_memcmp(a->Ssid.Ssid, b->Ssid.Ssid, a->Ssid.SsidLength)==_TRUE;
++}
++
++int is_same_network(WLAN_BSSID_EX *src, WLAN_BSSID_EX *dst)
++{
++ u16 s_cap, d_cap;
++
++_func_enter_;
++
++#ifdef PLATFORM_OS_XP
++ if ( ((uint)dst) <= 0x7fffffff ||
++ ((uint)src) <= 0x7fffffff ||
++ ((uint)&s_cap) <= 0x7fffffff ||
++ ((uint)&d_cap) <= 0x7fffffff)
++ {
++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("\n@@@@ error address of dst\n"));
++
++ KeBugCheckEx(0x87110000, (ULONG_PTR)dst, (ULONG_PTR)src,(ULONG_PTR)&s_cap, (ULONG_PTR)&d_cap);
++
++ return _FALSE;
++ }
++#endif
++
++
++ _rtw_memcpy((u8 *)&s_cap, rtw_get_capability_from_ie(src->IEs), 2);
++ _rtw_memcpy((u8 *)&d_cap, rtw_get_capability_from_ie(dst->IEs), 2);
++
++
++ s_cap = le16_to_cpu(s_cap);
++ d_cap = le16_to_cpu(d_cap);
++
++_func_exit_;
++
++ return ((src->Ssid.SsidLength == dst->Ssid.SsidLength) &&
++ // (src->Configuration.DSConfig == dst->Configuration.DSConfig) &&
++ ( (_rtw_memcmp(src->MacAddress, dst->MacAddress, ETH_ALEN)) == _TRUE) &&
++ ( (_rtw_memcmp(src->Ssid.Ssid, dst->Ssid.Ssid, src->Ssid.SsidLength)) == _TRUE) &&
++ ((s_cap & WLAN_CAPABILITY_IBSS) ==
++ (d_cap & WLAN_CAPABILITY_IBSS)) &&
++ ((s_cap & WLAN_CAPABILITY_BSS) ==
++ (d_cap & WLAN_CAPABILITY_BSS)));
++
++}
++
++struct wlan_network * rtw_get_oldest_wlan_network(_queue *scanned_queue)
++{
++ _list *plist, *phead;
++
++
++ struct wlan_network *pwlan = NULL;
++ struct wlan_network *oldest = NULL;
++_func_enter_;
++ phead = get_list_head(scanned_queue);
++
++ plist = get_next(phead);
++
++ while(1)
++ {
++
++ if (rtw_end_of_queue_search(phead,plist)== _TRUE)
++ break;
++
++ pwlan= LIST_CONTAINOR(plist, struct wlan_network, list);
++
++ if(pwlan->fixed!=_TRUE)
++ {
++ if (oldest == NULL ||time_after(oldest->last_scanned, pwlan->last_scanned))
++ oldest = pwlan;
++ }
++
++ plist = get_next(plist);
++ }
++_func_exit_;
++ return oldest;
++
++}
++
++static void update_network(WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src,
++ _adapter * padapter, bool update_ie)
++{
++ u8 ss_ori = dst->PhyInfo.SignalStrength;
++ u8 sq_ori = dst->PhyInfo.SignalQuality;
++ long rssi_ori = dst->Rssi;
++
++ u8 ss_smp = src->PhyInfo.SignalStrength;
++ u8 sq_smp = src->PhyInfo.SignalQuality;
++ long rssi_smp = src->Rssi;
++
++ u8 ss_final;
++ u8 sq_final;
++ long rssi_final;
++
++_func_enter_;
++
++#ifdef CONFIG_ANTENNA_DIVERSITY
++ rtw_hal_antdiv_rssi_compared(padapter, dst, src); //this will update src.Rssi, need consider again
++#endif
++
++ #if defined(DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED) && 1
++ if(strcmp(dst->Ssid.Ssid, DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED) == 0) {
++ DBG_871X(FUNC_ADPT_FMT" %s("MAC_FMT", ch%u) ss_ori:%3u, sq_ori:%3u, rssi_ori:%3ld, ss_smp:%3u, sq_smp:%3u, rssi_smp:%3ld\n"
++ , FUNC_ADPT_ARG(padapter)
++ , src->Ssid.Ssid, MAC_ARG(src->MacAddress), src->Configuration.DSConfig
++ ,ss_ori, sq_ori, rssi_ori
++ ,ss_smp, sq_smp, rssi_smp
++ );
++ }
++ #endif
++
++ /* The rule below is 1/5 for sample value, 4/5 for history value */
++ if (check_fwstate(&padapter->mlmepriv, _FW_LINKED) && is_same_network(&(padapter->mlmepriv.cur_network.network), src)) {
++ /* Take the recvpriv's value for the connected AP*/
++ ss_final = padapter->recvpriv.signal_strength;
++ sq_final = padapter->recvpriv.signal_qual;
++ /* the rssi value here is undecorated, and will be used for antenna diversity */
++ if(sq_smp != 101) /* from the right channel */
++ rssi_final = (src->Rssi+dst->Rssi*4)/5;
++ else
++ rssi_final = rssi_ori;
++ }
++ else {
++ if(sq_smp != 101) { /* from the right channel */
++ ss_final = ((u32)(src->PhyInfo.SignalStrength)+(u32)(dst->PhyInfo.SignalStrength)*4)/5;
++ sq_final = ((u32)(src->PhyInfo.SignalQuality)+(u32)(dst->PhyInfo.SignalQuality)*4)/5;
++ rssi_final = (src->Rssi+dst->Rssi*4)/5;
++ } else {
++ /* bss info not receving from the right channel, use the original RX signal infos */
++ ss_final = dst->PhyInfo.SignalStrength;
++ sq_final = dst->PhyInfo.SignalQuality;
++ rssi_final = dst->Rssi;
++ }
++
++ }
++
++ if (update_ie)
++ _rtw_memcpy((u8 *)dst, (u8 *)src, get_WLAN_BSSID_EX_sz(src));
++
++ dst->PhyInfo.SignalStrength = ss_final;
++ dst->PhyInfo.SignalQuality = sq_final;
++ dst->Rssi = rssi_final;
++
++ #if defined(DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED) && 1
++ if(strcmp(dst->Ssid.Ssid, DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED) == 0) {
++ DBG_871X(FUNC_ADPT_FMT" %s("MAC_FMT"), SignalStrength:%u, SignalQuality:%u, RawRSSI:%ld\n"
++ , FUNC_ADPT_ARG(padapter)
++ , dst->Ssid.Ssid, MAC_ARG(dst->MacAddress), dst->PhyInfo.SignalStrength, dst->PhyInfo.SignalQuality, dst->Rssi);
++ }
++ #endif
++
++#if 0 // old codes, may be useful one day...
++// DBG_871X("update_network: rssi=0x%lx dst->Rssi=%d ,dst->Rssi=0x%lx , src->Rssi=0x%lx",(dst->Rssi+src->Rssi)/2,dst->Rssi,dst->Rssi,src->Rssi);
++ if (check_fwstate(&padapter->mlmepriv, _FW_LINKED) && is_same_network(&(padapter->mlmepriv.cur_network.network), src))
++ {
++
++ //DBG_871X("b:ssid=%s update_network: src->rssi=0x%d padapter->recvpriv.ui_rssi=%d\n",src->Ssid.Ssid,src->Rssi,padapter->recvpriv.signal);
++ if(padapter->recvpriv.signal_qual_data.total_num++ >= PHY_LINKQUALITY_SLID_WIN_MAX)
++ {
++ padapter->recvpriv.signal_qual_data.total_num = PHY_LINKQUALITY_SLID_WIN_MAX;
++ last_evm = padapter->recvpriv.signal_qual_data.elements[padapter->recvpriv.signal_qual_data.index];
++ padapter->recvpriv.signal_qual_data.total_val -= last_evm;
++ }
++ padapter->recvpriv.signal_qual_data.total_val += query_rx_pwr_percentage(src->Rssi);
++
++ padapter->recvpriv.signal_qual_data.elements[padapter->recvpriv.signal_qual_data.index++] = query_rx_pwr_percentage(src->Rssi);
++ if(padapter->recvpriv.signal_qual_data.index >= PHY_LINKQUALITY_SLID_WIN_MAX)
++ padapter->recvpriv.signal_qual_data.index = 0;
++
++ //DBG_871X("Total SQ=%d pattrib->signal_qual= %d\n", padapter->recvpriv.signal_qual_data.total_val, src->Rssi);
++
++ // <1> Showed on UI for user,in percentage.
++ tmpVal = padapter->recvpriv.signal_qual_data.total_val/padapter->recvpriv.signal_qual_data.total_num;
++ padapter->recvpriv.signal=(u8)tmpVal;//Link quality
++
++ src->Rssi= translate_percentage_to_dbm(padapter->recvpriv.signal) ;
++ }
++ else{
++// DBG_871X("ELSE:ssid=%s update_network: src->rssi=0x%d dst->rssi=%d\n",src->Ssid.Ssid,src->Rssi,dst->Rssi);
++ src->Rssi=(src->Rssi +dst->Rssi)/2;//dBM
++ }
++
++// DBG_871X("a:update_network: src->rssi=0x%d padapter->recvpriv.ui_rssi=%d\n",src->Rssi,padapter->recvpriv.signal);
++
++#endif
++
++_func_exit_;
++}
++
++static void update_current_network(_adapter *adapter, WLAN_BSSID_EX *pnetwork)
++{
++ struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
++
++_func_enter_;
++
++#ifdef PLATFORM_OS_XP
++ if ((unsigned long)(&(pmlmepriv->cur_network.network)) < 0x7ffffff)
++ {
++ KeBugCheckEx(0x87111c1c, (ULONG_PTR)(&(pmlmepriv->cur_network.network)), 0, 0,0);
++ }
++#endif
++
++ if ( (check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE) && (is_same_network(&(pmlmepriv->cur_network.network), pnetwork)))
++ {
++ //RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,"Same Network\n");
++
++ //if(pmlmepriv->cur_network.network.IELength<= pnetwork->IELength)
++ {
++ update_network(&(pmlmepriv->cur_network.network), pnetwork,adapter, _TRUE);
++ rtw_update_protection(adapter, (pmlmepriv->cur_network.network.IEs) + sizeof (NDIS_802_11_FIXED_IEs),
++ pmlmepriv->cur_network.network.IELength);
++ }
++ }
++
++_func_exit_;
++
++}
++
++
++/*
++
++Caller must hold pmlmepriv->lock first.
++
++
++*/
++void rtw_update_scanned_network(_adapter *adapter, WLAN_BSSID_EX *target)
++{
++ _irqL irqL;
++ _list *plist, *phead;
++ ULONG bssid_ex_sz;
++ struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
++ _queue *queue = &(pmlmepriv->scanned_queue);
++ struct wlan_network *pnetwork = NULL;
++ struct wlan_network *oldest = NULL;
++
++_func_enter_;
++
++ _enter_critical_bh(&queue->lock, &irqL);
++ phead = get_list_head(queue);
++ plist = get_next(phead);
++
++ while(1)
++ {
++ if (rtw_end_of_queue_search(phead,plist)== _TRUE)
++ break;
++
++ pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
++
++ if ((unsigned long)(pnetwork) < 0x7ffffff)
++ {
++#ifdef PLATFORM_OS_XP
++ KeBugCheckEx(0x87111c1c, (ULONG_PTR)pnetwork, 0, 0,0);
++#endif
++ }
++
++ if (is_same_network(&(pnetwork->network), target))
++ break;
++
++ if ((oldest == ((struct wlan_network *)0)) ||
++ time_after(oldest->last_scanned, pnetwork->last_scanned))
++ oldest = pnetwork;
++
++ plist = get_next(plist);
++
++ }
++
++
++ /* If we didn't find a match, then get a new network slot to initialize
++ * with this beacon's information */
++ if (rtw_end_of_queue_search(phead,plist)== _TRUE) {
++
++ if (_rtw_queue_empty(&(pmlmepriv->free_bss_pool)) == _TRUE) {
++ /* If there are no more slots, expire the oldest */
++ //list_del_init(&oldest->list);
++ pnetwork = oldest;
++
++#ifdef CONFIG_ANTENNA_DIVERSITY
++ //target->PhyInfo.Optimum_antenna = pHalData->CurAntenna;//optimum_antenna=>For antenna diversity
++ rtw_hal_get_def_var(adapter, HAL_DEF_CURRENT_ANTENNA, &(target->PhyInfo.Optimum_antenna));
++#endif
++ _rtw_memcpy(&(pnetwork->network), target, get_WLAN_BSSID_EX_sz(target));
++ //pnetwork->last_scanned = rtw_get_current_time();
++ // variable initialize
++ pnetwork->fixed = _FALSE;
++ pnetwork->last_scanned = rtw_get_current_time();
++
++ pnetwork->network_type = 0;
++ pnetwork->aid=0;
++ pnetwork->join_res=0;
++
++ /* bss info not receving from the right channel */
++ if (pnetwork->network.PhyInfo.SignalQuality == 101)
++ pnetwork->network.PhyInfo.SignalQuality = 0;
++ }
++ else {
++ /* Otherwise just pull from the free list */
++
++ pnetwork = rtw_alloc_network(pmlmepriv); // will update scan_time
++
++ if(pnetwork==NULL){
++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("\n\n\nsomething wrong here\n\n\n"));
++ goto exit;
++ }
++
++ bssid_ex_sz = get_WLAN_BSSID_EX_sz(target);
++ target->Length = bssid_ex_sz;
++#ifdef CONFIG_ANTENNA_DIVERSITY
++ //target->PhyInfo.Optimum_antenna = pHalData->CurAntenna;
++ rtw_hal_get_def_var(adapter, HAL_DEF_CURRENT_ANTENNA, &(target->PhyInfo.Optimum_antenna));
++#endif
++ _rtw_memcpy(&(pnetwork->network), target, bssid_ex_sz );
++
++ pnetwork->last_scanned = rtw_get_current_time();
++
++ /* bss info not receving from the right channel */
++ if (pnetwork->network.PhyInfo.SignalQuality == 101)
++ pnetwork->network.PhyInfo.SignalQuality = 0;
++
++ rtw_list_insert_tail(&(pnetwork->list),&(queue->queue));
++
++ }
++ }
++ else {
++ /* we have an entry and we are going to update it. But this entry may
++ * be already expired. In this case we do the same as we found a new
++ * net and call the new_net handler
++ */
++ bool update_ie = _TRUE;
++
++ pnetwork->last_scanned = rtw_get_current_time();
++
++ //target.Reserved[0]==1, means that scaned network is a bcn frame.
++ if((pnetwork->network.IELength>target->IELength) && (target->Reserved[0]==1))
++ update_ie = _FALSE;
++
++ update_network(&(pnetwork->network), target,adapter, update_ie);
++ }
++
++exit:
++ _exit_critical_bh(&queue->lock, &irqL);
++
++_func_exit_;
++}
++
++void rtw_add_network(_adapter *adapter, WLAN_BSSID_EX *pnetwork);
++void rtw_add_network(_adapter *adapter, WLAN_BSSID_EX *pnetwork)
++{
++ _irqL irqL;
++ struct mlme_priv *pmlmepriv = &(((_adapter *)adapter)->mlmepriv);
++ //_queue *queue = &(pmlmepriv->scanned_queue);
++
++_func_enter_;
++
++ //_enter_critical_bh(&queue->lock, &irqL);
++
++ #if defined(CONFIG_P2P) && defined(CONFIG_P2P_REMOVE_GROUP_INFO)
++ rtw_WLAN_BSSID_EX_remove_p2p_attr(pnetwork, P2P_ATTR_GROUP_INFO);
++ #endif
++
++ update_current_network(adapter, pnetwork);
++
++ rtw_update_scanned_network(adapter, pnetwork);
++
++ //_exit_critical_bh(&queue->lock, &irqL);
++
++_func_exit_;
++}
++
++//select the desired network based on the capability of the (i)bss.
++// check items: (1) security
++// (2) network_type
++// (3) WMM
++// (4) HT
++// (5) others
++int rtw_is_desired_network(_adapter *adapter, struct wlan_network *pnetwork);
++int rtw_is_desired_network(_adapter *adapter, struct wlan_network *pnetwork)
++{
++ struct security_priv *psecuritypriv = &adapter->securitypriv;
++ struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
++ u32 desired_encmode;
++ u32 privacy;
++
++ //u8 wps_ie[512];
++ uint wps_ielen;
++
++ int bselected = _TRUE;
++
++ desired_encmode = psecuritypriv->ndisencryptstatus;
++ privacy = pnetwork->network.Privacy;
++
++ if(check_fwstate(pmlmepriv, WIFI_UNDER_WPS))
++ {
++ if(rtw_get_wps_ie(pnetwork->network.IEs+_FIXED_IE_LENGTH_, pnetwork->network.IELength-_FIXED_IE_LENGTH_, NULL, &wps_ielen)!=NULL)
++ {
++ return _TRUE;
++ }
++ else
++ {
++ return _FALSE;
++ }
++ }
++ if (adapter->registrypriv.wifi_spec == 1) //for correct flow of 8021X to do....
++ {
++ u8 *p=NULL;
++ uint ie_len=0;
++
++ if ((desired_encmode == Ndis802_11EncryptionDisabled) && (privacy != 0))
++ bselected = _FALSE;
++
++ if ( psecuritypriv->ndisauthtype == Ndis802_11AuthModeWPA2PSK) {
++ p = rtw_get_ie(pnetwork->network.IEs + _BEACON_IE_OFFSET_, _RSN_IE_2_, &ie_len, (pnetwork->network.IELength - _BEACON_IE_OFFSET_));
++ if (p && ie_len>0) {
++ bselected = _TRUE;
++ } else {
++ bselected = _FALSE;
++ }
++ }
++ }
++
++
++ if ((desired_encmode != Ndis802_11EncryptionDisabled) && (privacy == 0)) {
++ DBG_871X("desired_encmode: %d, privacy: %d\n", desired_encmode, privacy);
++ bselected = _FALSE;
++ }
++
++ if(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE)
++ {
++ if(pnetwork->network.InfrastructureMode != pmlmepriv->cur_network.network.InfrastructureMode)
++ bselected = _FALSE;
++ }
++
++
++ return bselected;
++}
++
++/* TODO: Perry : For Power Management */
++void rtw_atimdone_event_callback(_adapter *adapter , u8 *pbuf)
++{
++
++_func_enter_;
++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("receive atimdone_evet\n"));
++_func_exit_;
++ return;
++}
++
++
++void rtw_survey_event_callback(_adapter *adapter, u8 *pbuf)
++{
++ _irqL irqL;
++ u32 len;
++ WLAN_BSSID_EX *pnetwork;
++ struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
++
++_func_enter_;
++
++ pnetwork = (WLAN_BSSID_EX *)pbuf;
++
++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("rtw_survey_event_callback, ssid=%s\n", pnetwork->Ssid.Ssid));
++
++#ifdef CONFIG_RTL8712
++ //endian_convert
++ pnetwork->Length = le32_to_cpu(pnetwork->Length);
++ pnetwork->Ssid.SsidLength = le32_to_cpu(pnetwork->Ssid.SsidLength);
++ pnetwork->Privacy =le32_to_cpu( pnetwork->Privacy);
++ pnetwork->Rssi = le32_to_cpu(pnetwork->Rssi);
++ pnetwork->NetworkTypeInUse =le32_to_cpu(pnetwork->NetworkTypeInUse);
++ pnetwork->Configuration.ATIMWindow = le32_to_cpu(pnetwork->Configuration.ATIMWindow);
++ pnetwork->Configuration.BeaconPeriod = le32_to_cpu(pnetwork->Configuration.BeaconPeriod);
++ pnetwork->Configuration.DSConfig =le32_to_cpu(pnetwork->Configuration.DSConfig);
++ pnetwork->Configuration.FHConfig.DwellTime=le32_to_cpu(pnetwork->Configuration.FHConfig.DwellTime);
++ pnetwork->Configuration.FHConfig.HopPattern=le32_to_cpu(pnetwork->Configuration.FHConfig.HopPattern);
++ pnetwork->Configuration.FHConfig.HopSet=le32_to_cpu(pnetwork->Configuration.FHConfig.HopSet);
++ pnetwork->Configuration.FHConfig.Length=le32_to_cpu(pnetwork->Configuration.FHConfig.Length);
++ pnetwork->Configuration.Length = le32_to_cpu(pnetwork->Configuration.Length);
++ pnetwork->InfrastructureMode = le32_to_cpu(pnetwork->InfrastructureMode);
++ pnetwork->IELength = le32_to_cpu(pnetwork->IELength);
++#endif
++
++ len = get_WLAN_BSSID_EX_sz(pnetwork);
++ if(len > (sizeof(WLAN_BSSID_EX)))
++ {
++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("\n ****rtw_survey_event_callback: return a wrong bss ***\n"));
++ return;
++ }
++
++
++ _enter_critical_bh(&pmlmepriv->lock, &irqL);
++
++ // update IBSS_network 's timestamp
++ if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)) == _TRUE)
++ {
++ //RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,"rtw_survey_event_callback : WIFI_ADHOC_MASTER_STATE \n\n");
++ if(_rtw_memcmp(&(pmlmepriv->cur_network.network.MacAddress), pnetwork->MacAddress, ETH_ALEN))
++ {
++ struct wlan_network* ibss_wlan = NULL;
++ _irqL irqL;
++
++ _rtw_memcpy(pmlmepriv->cur_network.network.IEs, pnetwork->IEs, 8);
++ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++ ibss_wlan = rtw_find_network(&pmlmepriv->scanned_queue, pnetwork->MacAddress);
++ if(ibss_wlan)
++ {
++ _rtw_memcpy(ibss_wlan->network.IEs , pnetwork->IEs, 8);
++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++ goto exit;
++ }
++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++ }
++ }
++
++ // lock pmlmepriv->lock when you accessing network_q
++ if ((check_fwstate(pmlmepriv, _FW_UNDER_LINKING)) == _FALSE)
++ {
++ if( pnetwork->Ssid.Ssid[0] == 0 )
++ {
++ pnetwork->Ssid.SsidLength = 0;
++ }
++ rtw_add_network(adapter, pnetwork);
++ }
++
++exit:
++
++ _exit_critical_bh(&pmlmepriv->lock, &irqL);
++
++_func_exit_;
++
++ return;
++}
++
++
++
++void rtw_surveydone_event_callback(_adapter *adapter, u8 *pbuf)
++{
++ _irqL irqL;
++ u8 timer_cancelled = _FALSE;
++ struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
++
++#ifdef CONFIG_MLME_EXT
++
++ mlmeext_surveydone_event_callback(adapter);
++
++#endif
++
++_func_enter_;
++
++ _enter_critical_bh(&pmlmepriv->lock, &irqL);
++ if(pmlmepriv->wps_probe_req_ie)
++ {
++ u32 free_len = pmlmepriv->wps_probe_req_ie_len;
++ pmlmepriv->wps_probe_req_ie_len = 0;
++ rtw_mfree(pmlmepriv->wps_probe_req_ie, free_len);
++ pmlmepriv->wps_probe_req_ie = NULL;
++ }
++
++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("rtw_surveydone_event_callback: fw_state:%x\n\n", get_fwstate(pmlmepriv)));
++
++ if (check_fwstate(pmlmepriv,_FW_UNDER_SURVEY))
++ {
++ //u8 timer_cancelled;
++
++ timer_cancelled = _TRUE;
++ //_cancel_timer(&pmlmepriv->scan_to_timer, &timer_cancelled);
++
++ _clr_fwstate_(pmlmepriv, _FW_UNDER_SURVEY);
++ }
++ else {
++
++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("nic status =%x, survey done event comes too late!\n", get_fwstate(pmlmepriv)));
++ }
++ _exit_critical_bh(&pmlmepriv->lock, &irqL);
++
++ if(timer_cancelled)
++ _cancel_timer(&pmlmepriv->scan_to_timer, &timer_cancelled);
++
++
++ _enter_critical_bh(&pmlmepriv->lock, &irqL);
++
++ #ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
++ rtw_set_signal_stat_timer(&adapter->recvpriv);
++ #endif
++
++ if(pmlmepriv->to_join == _TRUE)
++ {
++ if((check_fwstate(pmlmepriv, WIFI_ADHOC_STATE)==_TRUE) )
++ {
++ if(check_fwstate(pmlmepriv, _FW_LINKED)==_FALSE)
++ {
++ set_fwstate(pmlmepriv, _FW_UNDER_LINKING);
++
++ if(rtw_select_and_join_from_scanned_queue(pmlmepriv)==_SUCCESS)
++ {
++ _set_timer(&pmlmepriv->assoc_timer, MAX_JOIN_TIMEOUT );
++ }
++ else
++ {
++ WLAN_BSSID_EX *pdev_network = &(adapter->registrypriv.dev_network);
++ u8 *pibss = adapter->registrypriv.dev_network.MacAddress;
++
++ //pmlmepriv->fw_state ^= _FW_UNDER_SURVEY;//because don't set assoc_timer
++ _clr_fwstate_(pmlmepriv, _FW_UNDER_SURVEY);
++
++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("switching to adhoc master\n"));
++
++ _rtw_memset(&pdev_network->Ssid, 0, sizeof(NDIS_802_11_SSID));
++ _rtw_memcpy(&pdev_network->Ssid, &pmlmepriv->assoc_ssid, sizeof(NDIS_802_11_SSID));
++
++ rtw_update_registrypriv_dev_network(adapter);
++ rtw_generate_random_ibss(pibss);
++
++ pmlmepriv->fw_state = WIFI_ADHOC_MASTER_STATE;
++
++ if(rtw_createbss_cmd(adapter)!=_SUCCESS)
++ {
++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("Error=>rtw_createbss_cmd status FAIL\n"));
++ }
++
++ pmlmepriv->to_join = _FALSE;
++ }
++ }
++ }
++ else
++ {
++ int s_ret;
++ set_fwstate(pmlmepriv, _FW_UNDER_LINKING);
++ pmlmepriv->to_join = _FALSE;
++ if(_SUCCESS == (s_ret=rtw_select_and_join_from_scanned_queue(pmlmepriv)))
++ {
++ _set_timer(&pmlmepriv->assoc_timer, MAX_JOIN_TIMEOUT);
++ }
++ else if(s_ret == 2)//there is no need to wait for join
++ {
++ _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING);
++ rtw_indicate_connect(adapter);
++ }
++ else
++ {
++ DBG_871X("try_to_join, but select scanning queue fail, to_roaming:%d\n", rtw_to_roaming(adapter));
++ #ifdef CONFIG_LAYER2_ROAMING
++ if (rtw_to_roaming(adapter) != 0) {
++ if( --pmlmepriv->to_roaming == 0
++ || _SUCCESS != rtw_sitesurvey_cmd(adapter, &pmlmepriv->assoc_ssid, 1, NULL, 0)
++ ) {
++ rtw_set_roaming(adapter, 0);
++#ifdef CONFIG_INTEL_WIDI
++ if(adapter->mlmepriv.widi_state == INTEL_WIDI_STATE_ROAMING)
++ {
++ _rtw_memset(pmlmepriv->sa_ext, 0x00, L2SDTA_SERVICE_VE_LEN);
++ intel_widi_wk_cmd(adapter, INTEL_WIDI_LISTEN_WK, NULL);
++ DBG_871X("change to widi listen\n");
++ }
++#endif // CONFIG_INTEL_WIDI
++ rtw_free_assoc_resources(adapter, 1);
++ rtw_indicate_disconnect(adapter);
++ } else {
++ pmlmepriv->to_join = _TRUE;
++ }
++ }
++ #endif
++ _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING);
++ }
++ }
++ }
++
++ indicate_wx_scan_complete_event(adapter);
++ //DBG_871X("scan complete in %dms\n",rtw_get_passing_time_ms(pmlmepriv->scan_start_time));
++
++ _exit_critical_bh(&pmlmepriv->lock, &irqL);
++
++#ifdef CONFIG_P2P_PS
++ if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) {
++ p2p_ps_wk_cmd(adapter, P2P_PS_SCAN_DONE, 0);
++ }
++#endif // CONFIG_P2P_PS
++
++ rtw_os_xmit_schedule(adapter);
++#ifdef CONFIG_CONCURRENT_MODE
++ rtw_os_xmit_schedule(adapter->pbuddy_adapter);
++#endif
++#ifdef CONFIG_DUALMAC_CONCURRENT
++ dc_resume_xmit(adapter);
++#endif
++
++#ifdef CONFIG_DRVEXT_MODULE_WSC
++ drvext_surveydone_callback(&adapter->drvextpriv);
++#endif
++
++#ifdef DBG_CONFIG_ERROR_DETECT
++#ifdef CONFIG_INTEL_WIDI
++ if (adapter->mlmepriv.widi_state == INTEL_WIDI_STATE_NONE)
++#endif
++ {
++ struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
++ if(pmlmeext->sitesurvey_res.bss_cnt == 0){
++ rtw_hal_sreset_reset(adapter);
++ }
++ }
++#endif
++
++#ifdef CONFIG_IOCTL_CFG80211
++ rtw_cfg80211_surveydone_event_callback(adapter);
++#endif //CONFIG_IOCTL_CFG80211
++
++_func_exit_;
++
++}
++
++void rtw_dummy_event_callback(_adapter *adapter , u8 *pbuf)
++{
++
++}
++
++void rtw_fwdbg_event_callback(_adapter *adapter , u8 *pbuf)
++{
++
++}
++
++static void free_scanqueue(struct mlme_priv *pmlmepriv)
++{
++ _irqL irqL, irqL0;
++ _queue *free_queue = &pmlmepriv->free_bss_pool;
++ _queue *scan_queue = &pmlmepriv->scanned_queue;
++ _list *plist, *phead, *ptemp;
++
++_func_enter_;
++
++ RT_TRACE(_module_rtl871x_mlme_c_, _drv_notice_, ("+free_scanqueue\n"));
++ _enter_critical_bh(&scan_queue->lock, &irqL0);
++ _enter_critical_bh(&free_queue->lock, &irqL);
++
++ phead = get_list_head(scan_queue);
++ plist = get_next(phead);
++
++ while (plist != phead)
++ {
++ ptemp = get_next(plist);
++ rtw_list_delete(plist);
++ rtw_list_insert_tail(plist, &free_queue->queue);
++ plist =ptemp;
++ pmlmepriv->num_of_scanned --;
++ }
++
++ _exit_critical_bh(&free_queue->lock, &irqL);
++ _exit_critical_bh(&scan_queue->lock, &irqL0);
++
++_func_exit_;
++}
++
++/*
++*rtw_free_assoc_resources: the caller has to lock pmlmepriv->lock
++*/
++void rtw_free_assoc_resources(_adapter *adapter, int lock_scanned_queue)
++{
++ _irqL irqL;
++ struct wlan_network* pwlan = NULL;
++ struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
++ struct sta_priv *pstapriv = &adapter->stapriv;
++ struct wlan_network *tgt_network = &pmlmepriv->cur_network;
++
++#ifdef CONFIG_TDLS
++ struct tdls_info *ptdlsinfo = &adapter->tdlsinfo;
++#endif //CONFIG_TDLS
++_func_enter_;
++
++ RT_TRACE(_module_rtl871x_mlme_c_, _drv_notice_, ("+rtw_free_assoc_resources\n"));
++ RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("tgt_network->network.MacAddress="MAC_FMT" ssid=%s\n",
++ MAC_ARG(tgt_network->network.MacAddress), tgt_network->network.Ssid.Ssid));
++
++ if(check_fwstate( pmlmepriv, WIFI_STATION_STATE|WIFI_AP_STATE))
++ {
++ struct sta_info* psta;
++
++ psta = rtw_get_stainfo(&adapter->stapriv, tgt_network->network.MacAddress);
++
++#ifdef CONFIG_TDLS
++ if(ptdlsinfo->setup_state != TDLS_STATE_NONE)
++ {
++ rtw_tdls_cmd(adapter, myid(&(adapter->eeprompriv)), TDLS_RS_RCR);
++ rtw_reset_tdls_info(adapter);
++ rtw_free_all_stainfo(adapter);
++ _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL);
++ }
++ else
++#endif //CONFIG_TDLS
++ {
++ _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL);
++ rtw_free_stainfo(adapter, psta);
++ }
++
++ _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);
++
++ }
++
++ if(check_fwstate( pmlmepriv, WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE|WIFI_AP_STATE))
++ {
++ struct sta_info* psta;
++
++ rtw_free_all_stainfo(adapter);
++
++ psta = rtw_get_bcmc_stainfo(adapter);
++ _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL);
++ rtw_free_stainfo(adapter, psta);
++ _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);
++
++ rtw_init_bcmc_stainfo(adapter);
++ }
++
++ if(lock_scanned_queue)
++ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++
++ pwlan = rtw_find_network(&pmlmepriv->scanned_queue, tgt_network->network.MacAddress);
++ if(pwlan)
++ {
++ pwlan->fixed = _FALSE;
++#ifdef CONFIG_P2P
++ if(!rtw_p2p_chk_state(&adapter->wdinfo, P2P_STATE_NONE))
++ {
++ u32 p2p_ielen=0;
++ u8 *p2p_ie;
++ //u16 capability;
++ u8 *pcap = NULL;
++ u32 capability_len=0;
++
++ //DBG_871X("free disconnecting network\n");
++ //rtw_free_network_nolock(pmlmepriv, pwlan);
++
++ if((p2p_ie=rtw_get_p2p_ie(pwlan->network.IEs+_FIXED_IE_LENGTH_, pwlan->network.IELength-_FIXED_IE_LENGTH_, NULL, &p2p_ielen)))
++ {
++ pcap = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CAPABILITY, NULL, &capability_len);
++ if(pcap && capability_len==2)
++ {
++ u16 cap = *(u16*)pcap ;
++ *(u16*)pcap = cap&0x00ff;//clear group capability when free this network
++ }
++ }
++
++ rtw_set_scan_deny(adapter, 2000);
++ //rtw_clear_scan_deny(adapter);
++ }
++#endif //CONFIG_P2P
++ }
++ else
++ {
++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("rtw_free_assoc_resources : pwlan== NULL \n\n"));
++ }
++
++
++ if((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) && (adapter->stapriv.asoc_sta_count== 1))
++ /*||check_fwstate(pmlmepriv, WIFI_STATION_STATE)*/)
++ {
++ rtw_free_network_nolock(pmlmepriv, pwlan);
++ }
++
++ if(lock_scanned_queue)
++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++
++ adapter->securitypriv.key_mask = 0;
++
++_func_exit_;
++
++}
++
++/*
++*rtw_indicate_connect: the caller has to lock pmlmepriv->lock
++*/
++void rtw_indicate_connect(_adapter *padapter)
++{
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++
++_func_enter_;
++
++ RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("+rtw_indicate_connect\n"));
++
++ pmlmepriv->to_join = _FALSE;
++
++ if(!check_fwstate(&padapter->mlmepriv, _FW_LINKED))
++ {
++
++#ifdef CONFIG_SW_ANTENNA_DIVERSITY
++ rtw_hal_set_hwreg(padapter, HW_VAR_ANTENNA_DIVERSITY_LINK, 0);
++#endif
++ set_fwstate(pmlmepriv, _FW_LINKED);
++
++ rtw_led_control(padapter, LED_CTL_LINK);
++
++#ifdef CONFIG_DRVEXT_MODULE
++ if(padapter->drvextpriv.enable_wpa)
++ {
++ indicate_l2_connect(padapter);
++ }
++ else
++#endif
++ {
++ rtw_os_indicate_connect(padapter);
++ }
++
++ }
++
++ rtw_set_roaming(padapter, 0);
++
++#ifdef CONFIG_INTEL_WIDI
++ if(padapter->mlmepriv.widi_state == INTEL_WIDI_STATE_ROAMING)
++ {
++ _rtw_memset(pmlmepriv->sa_ext, 0x00, L2SDTA_SERVICE_VE_LEN);
++ intel_widi_wk_cmd(padapter, INTEL_WIDI_LISTEN_WK, NULL);
++ DBG_871X("change to widi listen\n");
++ }
++#endif // CONFIG_INTEL_WIDI
++
++ rtw_set_scan_deny(padapter, 3000);
++
++ RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("-rtw_indicate_connect: fw_state=0x%08x\n", get_fwstate(pmlmepriv)));
++
++_func_exit_;
++
++}
++
++
++/*
++*rtw_indicate_disconnect: the caller has to lock pmlmepriv->lock
++*/
++void rtw_indicate_disconnect( _adapter *padapter )
++{
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++
++_func_enter_;
++
++ RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("+rtw_indicate_disconnect\n"));
++
++ _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING|WIFI_UNDER_WPS);
++
++ if(rtw_to_roaming(padapter) > 0)
++ _clr_fwstate_(pmlmepriv, _FW_LINKED);
++
++ if(check_fwstate(&padapter->mlmepriv, _FW_LINKED)
++ || (rtw_to_roaming(padapter) <= 0)
++ )
++ {
++ rtw_os_indicate_disconnect(padapter);
++
++ //set ips_deny_time to avoid enter IPS before LPS leave
++ padapter->pwrctrlpriv.ips_deny_time = rtw_get_current_time() + rtw_ms_to_systime(3000);
++
++ _clr_fwstate_(pmlmepriv, _FW_LINKED);
++
++ rtw_led_control(padapter, LED_CTL_NO_LINK);
++
++ rtw_clear_scan_deny(padapter);
++
++ }
++
++#ifdef CONFIG_P2P_PS
++ p2p_ps_wk_cmd(padapter, P2P_PS_DISABLE, 1);
++#endif // CONFIG_P2P_PS
++
++#ifdef CONFIG_LPS
++#ifdef CONFIG_WOWLAN
++ if(padapter->pwrctrlpriv.wowlan_mode==_FALSE)
++#endif //CONFIG_WOWLAN
++ rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_DISCONNECT, 1);
++
++#endif
++
++_func_exit_;
++}
++
++inline void rtw_indicate_scan_done( _adapter *padapter, bool aborted)
++{
++ rtw_os_indicate_scan_done(padapter, aborted);
++}
++
++void rtw_scan_abort(_adapter *adapter)
++{
++ u32 cnt=0;
++ u32 start;
++ struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
++ struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);
++
++ start = rtw_get_current_time();
++ pmlmeext->scan_abort = _TRUE;
++ while (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY)
++ && rtw_get_passing_time_ms(start) <= 200) {
++
++ if (adapter->bDriverStopped || adapter->bSurpriseRemoved)
++ break;
++
++ DBG_871X(FUNC_NDEV_FMT"fw_state=_FW_UNDER_SURVEY!\n", FUNC_NDEV_ARG(adapter->pnetdev));
++ rtw_msleep_os(20);
++ }
++
++ if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY)) {
++ if (!adapter->bDriverStopped && !adapter->bSurpriseRemoved)
++ DBG_871X(FUNC_NDEV_FMT"waiting for scan_abort time out!\n", FUNC_NDEV_ARG(adapter->pnetdev));
++ #ifdef CONFIG_PLATFORM_MSTAR
++ //_clr_fwstate_(pmlmepriv, _FW_UNDER_SURVEY);
++ set_survey_timer(pmlmeext, 0);
++ _set_timer(&pmlmepriv->scan_to_timer, 50);
++ #endif
++ rtw_indicate_scan_done(adapter, _TRUE);
++ }
++ pmlmeext->scan_abort = _FALSE;
++}
++
++static struct sta_info *rtw_joinbss_update_stainfo(_adapter *padapter, struct wlan_network *pnetwork)
++{
++ int i;
++ struct sta_info *bmc_sta, *psta=NULL;
++ struct recv_reorder_ctrl *preorder_ctrl;
++ struct sta_priv *pstapriv = &padapter->stapriv;
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++
++ psta = rtw_get_stainfo(pstapriv, pnetwork->network.MacAddress);
++ if(psta==NULL) {
++ psta = rtw_alloc_stainfo(pstapriv, pnetwork->network.MacAddress);
++ }
++
++ if(psta) //update ptarget_sta
++ {
++ DBG_871X("%s\n", __FUNCTION__);
++
++ psta->aid = pnetwork->join_res;
++#ifdef CONFIG_CONCURRENT_MODE
++
++ if(PRIMARY_ADAPTER == padapter->adapter_type)
++ psta->mac_id=0;
++ else
++ psta->mac_id=2;
++#else
++ psta->mac_id=0;
++#endif
++
++ psta->raid = networktype_to_raid(pmlmeext->cur_wireless_mode);
++
++ //security related
++ if(padapter->securitypriv.dot11AuthAlgrthm== dot11AuthAlgrthm_8021X)
++ {
++ padapter->securitypriv.binstallGrpkey=_FALSE;
++ padapter->securitypriv.busetkipkey=_FALSE;
++ padapter->securitypriv.bgrpkey_handshake=_FALSE;
++
++ psta->ieee8021x_blocked=_TRUE;
++ psta->dot118021XPrivacy=padapter->securitypriv.dot11PrivacyAlgrthm;
++
++ _rtw_memset((u8 *)&psta->dot118021x_UncstKey, 0, sizeof (union Keytype));
++
++ _rtw_memset((u8 *)&psta->dot11tkiprxmickey, 0, sizeof (union Keytype));
++ _rtw_memset((u8 *)&psta->dot11tkiptxmickey, 0, sizeof (union Keytype));
++
++ _rtw_memset((u8 *)&psta->dot11txpn, 0, sizeof (union pn48));
++#ifdef CONFIG_IEEE80211W
++ _rtw_memset((u8 *)&psta->dot11wtxpn, 0, sizeof (union pn48));
++#endif //CONFIG_IEEE80211W
++ _rtw_memset((u8 *)&psta->dot11rxpn, 0, sizeof (union pn48));
++ }
++
++ // Commented by Albert 2012/07/21
++ // When doing the WPS, the wps_ie_len won't equal to 0
++ // And the Wi-Fi driver shouldn't allow the data packet to be tramsmitted.
++ if ( padapter->securitypriv.wps_ie_len != 0 )
++ {
++ psta->ieee8021x_blocked=_TRUE;
++ padapter->securitypriv.wps_ie_len = 0;
++ }
++
++
++ //for A-MPDU Rx reordering buffer control for bmc_sta & sta_info
++ //if A-MPDU Rx is enabled, reseting rx_ordering_ctrl wstart_b(indicate_seq) to default value=0xffff
++ //todo: check if AP can send A-MPDU packets
++ for(i=0; i < 16 ; i++)
++ {
++ //preorder_ctrl = &precvpriv->recvreorder_ctrl[i];
++ preorder_ctrl = &psta->recvreorder_ctrl[i];
++ preorder_ctrl->enable = _FALSE;
++ preorder_ctrl->indicate_seq = 0xffff;
++ #ifdef DBG_RX_SEQ
++ DBG_871X("DBG_RX_SEQ %s:%d indicate_seq:%u \n", __FUNCTION__, __LINE__,
++ preorder_ctrl->indicate_seq);
++ #endif
++ preorder_ctrl->wend_b= 0xffff;
++ preorder_ctrl->wsize_b = 64;//max_ampdu_sz;//ex. 32(kbytes) -> wsize_b=32
++ }
++
++
++ bmc_sta = rtw_get_bcmc_stainfo(padapter);
++ if(bmc_sta)
++ {
++ for(i=0; i < 16 ; i++)
++ {
++ //preorder_ctrl = &precvpriv->recvreorder_ctrl[i];
++ preorder_ctrl = &bmc_sta->recvreorder_ctrl[i];
++ preorder_ctrl->enable = _FALSE;
++ preorder_ctrl->indicate_seq = 0xffff;
++ #ifdef DBG_RX_SEQ
++ DBG_871X("DBG_RX_SEQ %s:%d indicate_seq:%u \n", __FUNCTION__, __LINE__,
++ preorder_ctrl->indicate_seq);
++ #endif
++ preorder_ctrl->wend_b= 0xffff;
++ preorder_ctrl->wsize_b = 64;//max_ampdu_sz;//ex. 32(kbytes) -> wsize_b=32
++ }
++ }
++
++
++ //misc.
++ update_sta_info(padapter, psta);
++
++ }
++
++ return psta;
++
++}
++
++//pnetwork : returns from rtw_joinbss_event_callback
++//ptarget_wlan: found from scanned_queue
++static void rtw_joinbss_update_network(_adapter *padapter, struct wlan_network *ptarget_wlan, struct wlan_network *pnetwork)
++{
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ struct wlan_network *cur_network = &(pmlmepriv->cur_network);
++
++ DBG_871X("%s\n", __FUNCTION__);
++
++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("\nfw_state:%x, BSSID:"MAC_FMT"\n"
++ ,get_fwstate(pmlmepriv), MAC_ARG(pnetwork->network.MacAddress)));
++
++
++ // why not use ptarget_wlan??
++ _rtw_memcpy(&cur_network->network, &pnetwork->network, pnetwork->network.Length);
++
++ cur_network->aid = pnetwork->join_res;
++
++
++#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
++ rtw_set_signal_stat_timer(&padapter->recvpriv);
++#endif
++ padapter->recvpriv.signal_strength = ptarget_wlan->network.PhyInfo.SignalStrength;
++ padapter->recvpriv.signal_qual = ptarget_wlan->network.PhyInfo.SignalQuality;
++ //the ptarget_wlan->network.Rssi is raw data, we use ptarget_wlan->network.PhyInfo.SignalStrength instead (has scaled)
++ padapter->recvpriv.rssi = translate_percentage_to_dbm(ptarget_wlan->network.PhyInfo.SignalStrength);
++ #if defined(DBG_RX_SIGNAL_DISPLAY_PROCESSING) && 1
++ DBG_871X(FUNC_ADPT_FMT" signal_strength:%3u, rssi:%3d, signal_qual:%3u"
++ "\n"
++ , FUNC_ADPT_ARG(padapter)
++ , padapter->recvpriv.signal_strength
++ , padapter->recvpriv.rssi
++ , padapter->recvpriv.signal_qual
++ );
++ #endif
++#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
++ rtw_set_signal_stat_timer(&padapter->recvpriv);
++#endif
++
++ //update fw_state //will clr _FW_UNDER_LINKING here indirectly
++ switch(pnetwork->network.InfrastructureMode)
++ {
++ case Ndis802_11Infrastructure:
++
++ if(pmlmepriv->fw_state&WIFI_UNDER_WPS)
++ pmlmepriv->fw_state = WIFI_STATION_STATE|WIFI_UNDER_WPS;
++ else
++ pmlmepriv->fw_state = WIFI_STATION_STATE;
++
++ break;
++ case Ndis802_11IBSS:
++ pmlmepriv->fw_state = WIFI_ADHOC_STATE;
++ break;
++ default:
++ pmlmepriv->fw_state = WIFI_NULL_STATE;
++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("Invalid network_mode\n"));
++ break;
++ }
++
++ rtw_update_protection(padapter, (cur_network->network.IEs) + sizeof (NDIS_802_11_FIXED_IEs),
++ (cur_network->network.IELength));
++
++#ifdef CONFIG_80211N_HT
++ rtw_update_ht_cap(padapter, cur_network->network.IEs, cur_network->network.IELength, (u8) cur_network->network.Configuration.DSConfig);
++#endif
++
++
++}
++
++//Notes: the fucntion could be > passive_level (the same context as Rx tasklet)
++//pnetwork : returns from rtw_joinbss_event_callback
++//ptarget_wlan: found from scanned_queue
++//if join_res > 0, for (fw_state==WIFI_STATION_STATE), we check if "ptarget_sta" & "ptarget_wlan" exist.
++//if join_res > 0, for (fw_state==WIFI_ADHOC_STATE), we only check if "ptarget_wlan" exist.
++//if join_res > 0, update "cur_network->network" from "pnetwork->network" if (ptarget_wlan !=NULL).
++//
++//#define REJOIN
++void rtw_joinbss_event_prehandle(_adapter *adapter, u8 *pbuf)
++{
++ _irqL irqL,irqL2;
++ static u8 retry=0;
++ u8 timer_cancelled;
++ struct sta_info *ptarget_sta= NULL, *pcur_sta = NULL;
++ struct sta_priv *pstapriv = &adapter->stapriv;
++ struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
++ struct wlan_network *pnetwork = (struct wlan_network *)pbuf;
++ struct wlan_network *cur_network = &(pmlmepriv->cur_network);
++ struct wlan_network *pcur_wlan = NULL, *ptarget_wlan = NULL;
++ unsigned int the_same_macaddr = _FALSE;
++
++_func_enter_;
++
++#ifdef CONFIG_RTL8712
++ //endian_convert
++ pnetwork->join_res = le32_to_cpu(pnetwork->join_res);
++ pnetwork->network_type = le32_to_cpu(pnetwork->network_type);
++ pnetwork->network.Length = le32_to_cpu(pnetwork->network.Length);
++ pnetwork->network.Ssid.SsidLength = le32_to_cpu(pnetwork->network.Ssid.SsidLength);
++ pnetwork->network.Privacy =le32_to_cpu( pnetwork->network.Privacy);
++ pnetwork->network.Rssi = le32_to_cpu(pnetwork->network.Rssi);
++ pnetwork->network.NetworkTypeInUse =le32_to_cpu(pnetwork->network.NetworkTypeInUse) ;
++ pnetwork->network.Configuration.ATIMWindow = le32_to_cpu(pnetwork->network.Configuration.ATIMWindow);
++ pnetwork->network.Configuration.BeaconPeriod = le32_to_cpu(pnetwork->network.Configuration.BeaconPeriod);
++ pnetwork->network.Configuration.DSConfig = le32_to_cpu(pnetwork->network.Configuration.DSConfig);
++ pnetwork->network.Configuration.FHConfig.DwellTime=le32_to_cpu(pnetwork->network.Configuration.FHConfig.DwellTime);
++ pnetwork->network.Configuration.FHConfig.HopPattern=le32_to_cpu(pnetwork->network.Configuration.FHConfig.HopPattern);
++ pnetwork->network.Configuration.FHConfig.HopSet=le32_to_cpu(pnetwork->network.Configuration.FHConfig.HopSet);
++ pnetwork->network.Configuration.FHConfig.Length=le32_to_cpu(pnetwork->network.Configuration.FHConfig.Length);
++ pnetwork->network.Configuration.Length = le32_to_cpu(pnetwork->network.Configuration.Length);
++ pnetwork->network.InfrastructureMode = le32_to_cpu(pnetwork->network.InfrastructureMode);
++ pnetwork->network.IELength = le32_to_cpu(pnetwork->network.IELength );
++#endif
++
++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("joinbss event call back received with res=%d\n", pnetwork->join_res));
++
++ rtw_get_encrypt_decrypt_from_registrypriv(adapter);
++
++
++ if (pmlmepriv->assoc_ssid.SsidLength == 0)
++ {
++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("@@@@@ joinbss event call back for Any SSid\n"));
++ }
++ else
++ {
++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("@@@@@ rtw_joinbss_event_callback for SSid:%s\n", pmlmepriv->assoc_ssid.Ssid));
++ }
++
++ the_same_macaddr = _rtw_memcmp(pnetwork->network.MacAddress, cur_network->network.MacAddress, ETH_ALEN);
++
++ pnetwork->network.Length = get_WLAN_BSSID_EX_sz(&pnetwork->network);
++ if(pnetwork->network.Length > sizeof(WLAN_BSSID_EX))
++ {
++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("\n\n ***joinbss_evt_callback return a wrong bss ***\n\n"));
++ goto ignore_joinbss_callback;
++ }
++
++ _enter_critical_bh(&pmlmepriv->lock, &irqL);
++
++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("\n rtw_joinbss_event_callback !! _enter_critical \n"));
++
++ if(pnetwork->join_res > 0)
++ {
++ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++ retry = 0;
++ if (check_fwstate(pmlmepriv,_FW_UNDER_LINKING) )
++ {
++ //s1. find ptarget_wlan
++ if(check_fwstate(pmlmepriv, _FW_LINKED) )
++ {
++ if(the_same_macaddr == _TRUE)
++ {
++ ptarget_wlan = rtw_find_network(&pmlmepriv->scanned_queue, cur_network->network.MacAddress);
++ }
++ else
++ {
++ pcur_wlan = rtw_find_network(&pmlmepriv->scanned_queue, cur_network->network.MacAddress);
++ if(pcur_wlan) pcur_wlan->fixed = _FALSE;
++
++ pcur_sta = rtw_get_stainfo(pstapriv, cur_network->network.MacAddress);
++ if(pcur_sta){
++ _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL2);
++ rtw_free_stainfo(adapter, pcur_sta);
++ _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL2);
++ }
++
++ ptarget_wlan = rtw_find_network(&pmlmepriv->scanned_queue, pnetwork->network.MacAddress);
++ if(check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE){
++ if(ptarget_wlan) ptarget_wlan->fixed = _TRUE;
++ }
++ }
++
++ }
++ else
++ {
++ ptarget_wlan = rtw_find_network(&pmlmepriv->scanned_queue, pnetwork->network.MacAddress);
++ if(check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE){
++ if(ptarget_wlan) ptarget_wlan->fixed = _TRUE;
++ }
++ }
++
++ //s2. update cur_network
++ if(ptarget_wlan)
++ {
++ rtw_joinbss_update_network(adapter, ptarget_wlan, pnetwork);
++ }
++ else
++ {
++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("Can't find ptarget_wlan when joinbss_event callback\n"));
++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++ goto ignore_joinbss_callback;
++ }
++
++
++ //s3. find ptarget_sta & update ptarget_sta after update cur_network only for station mode
++ if(check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)
++ {
++ ptarget_sta = rtw_joinbss_update_stainfo(adapter, pnetwork);
++ if(ptarget_sta==NULL)
++ {
++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("Can't update stainfo when joinbss_event callback\n"));
++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++ goto ignore_joinbss_callback;
++ }
++ }
++
++ //s4. indicate connect
++ if(check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)
++ {
++ rtw_indicate_connect(adapter);
++ }
++ else
++ {
++ //adhoc mode will rtw_indicate_connect when rtw_stassoc_event_callback
++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("adhoc mode, fw_state:%x", get_fwstate(pmlmepriv)));
++ }
++
++
++ //s5. Cancle assoc_timer
++ _cancel_timer(&pmlmepriv->assoc_timer, &timer_cancelled);
++
++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("Cancle assoc_timer\n"));
++
++ }
++ else
++ {
++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("rtw_joinbss_event_callback err: fw_state:%x", get_fwstate(pmlmepriv)));
++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++ goto ignore_joinbss_callback;
++ }
++
++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++
++ }
++ else if(pnetwork->join_res == -4)
++ {
++ rtw_reset_securitypriv(adapter);
++ _set_timer(&pmlmepriv->assoc_timer, 1);
++
++ //rtw_free_assoc_resources(adapter, 1);
++
++ if((check_fwstate(pmlmepriv, _FW_UNDER_LINKING)) == _TRUE)
++ {
++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("fail! clear _FW_UNDER_LINKING ^^^fw_state=%x\n", get_fwstate(pmlmepriv)));
++ _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING);
++ }
++
++ }
++ else //if join_res < 0 (join fails), then try again
++ {
++
++ #ifdef REJOIN
++ res = _FAIL;
++ if(retry < 2) {
++ res = rtw_select_and_join_from_scanned_queue(pmlmepriv);
++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("rtw_select_and_join_from_scanned_queue again! res:%d\n",res));
++ }
++
++ if(res == _SUCCESS)
++ {
++ //extend time of assoc_timer
++ _set_timer(&pmlmepriv->assoc_timer, MAX_JOIN_TIMEOUT);
++ retry++;
++ }
++ else if(res == 2)//there is no need to wait for join
++ {
++ _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING);
++ rtw_indicate_connect(adapter);
++ }
++ else
++ {
++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("Set Assoc_Timer = 1; can't find match ssid in scanned_q \n"));
++ #endif
++
++ _set_timer(&pmlmepriv->assoc_timer, 1);
++ //rtw_free_assoc_resources(adapter, 1);
++ _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING);
++
++ #ifdef REJOIN
++ retry = 0;
++ }
++ #endif
++ }
++
++ignore_joinbss_callback:
++
++ _exit_critical_bh(&pmlmepriv->lock, &irqL);
++ _func_exit_;
++}
++
++void rtw_joinbss_event_callback(_adapter *adapter, u8 *pbuf)
++{
++ struct wlan_network *pnetwork = (struct wlan_network *)pbuf;
++
++_func_enter_;
++
++ mlmeext_joinbss_event_callback(adapter, pnetwork->join_res);
++
++ rtw_os_xmit_schedule(adapter);
++
++#ifdef CONFIG_CONCURRENT_MODE
++ rtw_os_xmit_schedule(adapter->pbuddy_adapter);
++#endif
++
++#ifdef CONFIG_DUALMAC_CONCURRENT
++ dc_resume_xmit(adapter);
++#endif
++
++_func_exit_;
++}
++
++void rtw_stassoc_event_callback(_adapter *adapter, u8 *pbuf)
++{
++ _irqL irqL;
++ struct sta_info *psta;
++ struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
++ struct stassoc_event *pstassoc = (struct stassoc_event*)pbuf;
++ struct wlan_network *cur_network = &(pmlmepriv->cur_network);
++ struct wlan_network *ptarget_wlan = NULL;
++
++_func_enter_;
++
++ if(rtw_access_ctrl(adapter, pstassoc->macaddr) == _FALSE)
++ return;
++
++#if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME)
++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE))
++ {
++ psta = rtw_get_stainfo(&adapter->stapriv, pstassoc->macaddr);
++ if(psta)
++ {
++#ifdef CONFIG_IOCTL_CFG80211
++#ifdef COMPAT_KERNEL_RELEASE
++
++#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,37)) || defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER)
++ u8 *passoc_req = NULL;
++ u32 assoc_req_len;
++
++ _enter_critical_bh(&psta->lock, &irqL);
++ if(psta->passoc_req && psta->assoc_req_len>0)
++ {
++ passoc_req = rtw_zmalloc(psta->assoc_req_len);
++ if(passoc_req)
++ {
++ assoc_req_len = psta->assoc_req_len;
++ _rtw_memcpy(passoc_req, psta->passoc_req, assoc_req_len);
++
++ rtw_mfree(psta->passoc_req , psta->assoc_req_len);
++ psta->passoc_req = NULL;
++ psta->assoc_req_len = 0;
++ }
++ }
++ _exit_critical_bh(&psta->lock, &irqL);
++
++ if(passoc_req && assoc_req_len>0)
++ {
++ rtw_cfg80211_indicate_sta_assoc(adapter, passoc_req, assoc_req_len);
++
++ rtw_mfree(passoc_req, assoc_req_len);
++ }
++#endif //(LINUX_VERSION_CODE < KERNEL_VERSION(2,6,37)) || defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER)
++#endif //CONFIG_IOCTL_CFG80211
++
++ //bss_cap_update_on_sta_join(adapter, psta);
++ //sta_info_update(adapter, psta);
++ ap_sta_info_defer_update(adapter, psta);
++ }
++
++ goto exit;
++ }
++#endif
++
++ psta = rtw_get_stainfo(&adapter->stapriv, pstassoc->macaddr);
++ if( psta != NULL)
++ {
++ //the sta have been in sta_info_queue => do nothing
++
++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("Error: rtw_stassoc_event_callback: sta has been in sta_hash_queue \n"));
++
++ goto exit; //(between drv has received this event before and fw have not yet to set key to CAM_ENTRY)
++ }
++
++ psta = rtw_alloc_stainfo(&adapter->stapriv, pstassoc->macaddr);
++ if (psta == NULL) {
++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("Can't alloc sta_info when rtw_stassoc_event_callback\n"));
++ goto exit;
++ }
++
++ //to do : init sta_info variable
++ psta->qos_option = 0;
++ psta->mac_id = (uint)pstassoc->cam_id;
++ //psta->aid = (uint)pstassoc->cam_id;
++
++ if(adapter->securitypriv.dot11AuthAlgrthm==dot11AuthAlgrthm_8021X)
++ psta->dot118021XPrivacy = adapter->securitypriv.dot11PrivacyAlgrthm;
++
++ psta->ieee8021x_blocked = _FALSE;
++
++ _enter_critical_bh(&pmlmepriv->lock, &irqL);
++
++ if ( (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)==_TRUE ) ||
++ (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE)==_TRUE ) )
++ {
++ if(adapter->stapriv.asoc_sta_count== 2)
++ {
++ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++ ptarget_wlan = rtw_find_network(&pmlmepriv->scanned_queue, cur_network->network.MacAddress);
++ if(ptarget_wlan) ptarget_wlan->fixed = _TRUE;
++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++ // a sta + bc/mc_stainfo (not Ibss_stainfo)
++ rtw_indicate_connect(adapter);
++ }
++ }
++
++ _exit_critical_bh(&pmlmepriv->lock, &irqL);
++
++
++ mlmeext_sta_add_event_callback(adapter, psta);
++
++#ifdef CONFIG_RTL8711
++ //submit SetStaKey_cmd to tell fw, fw will allocate an CAM entry for this sta
++ rtw_setstakey_cmd(adapter, (unsigned char*)psta, _FALSE);
++#endif
++
++exit:
++
++_func_exit_;
++
++}
++
++void rtw_stadel_event_callback(_adapter *adapter, u8 *pbuf)
++{
++ _irqL irqL,irqL2;
++ struct sta_info *psta;
++ struct wlan_network* pwlan = NULL;
++ WLAN_BSSID_EX *pdev_network=NULL;
++ u8* pibss = NULL;
++ struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
++ struct stadel_event *pstadel = (struct stadel_event*)pbuf;
++ struct sta_priv *pstapriv = &adapter->stapriv;
++ struct wlan_network *tgt_network = &(pmlmepriv->cur_network);
++
++_func_enter_;
++
++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE))
++ {
++#ifdef CONFIG_IOCTL_CFG80211
++#ifdef COMPAT_KERNEL_RELEASE
++
++#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,37)) || defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER)
++ rtw_cfg80211_indicate_sta_disassoc(adapter, pstadel->macaddr, *(u16*)pstadel->rsvd);
++#endif //(LINUX_VERSION_CODE < KERNEL_VERSION(2,6,37)) || defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER)
++#endif //CONFIG_IOCTL_CFG80211
++
++ return;
++ }
++
++
++ mlmeext_sta_del_event_callback(adapter);
++
++ _enter_critical_bh(&pmlmepriv->lock, &irqL2);
++
++ if(check_fwstate(pmlmepriv, WIFI_STATION_STATE) )
++ {
++ #ifdef CONFIG_LAYER2_ROAMING
++ if (rtw_to_roaming(adapter) > 0)
++ pmlmepriv->to_roaming--; /* this stadel_event is caused by roaming, decrease to_roaming */
++ else if (rtw_to_roaming(adapter) == 0)
++ rtw_set_roaming(adapter, adapter->registrypriv.max_roaming_times);
++#ifdef CONFIG_INTEL_WIDI
++ if(adapter->mlmepriv.widi_state != INTEL_WIDI_STATE_CONNECTED)
++#endif // CONFIG_INTEL_WIDI
++ if(*((unsigned short *)(pstadel->rsvd)) != WLAN_REASON_EXPIRATION_CHK)
++ rtw_set_roaming(adapter, 0); /* don't roam */
++ #endif
++
++ rtw_free_uc_swdec_pending_queue(adapter);
++
++ rtw_free_assoc_resources(adapter, 1);
++ rtw_indicate_disconnect(adapter);
++ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++ // remove the network entry in scanned_queue
++ pwlan = rtw_find_network(&pmlmepriv->scanned_queue, tgt_network->network.MacAddress);
++ if (pwlan) {
++ pwlan->fixed = _FALSE;
++ rtw_free_network_nolock(pmlmepriv, pwlan);
++ }
++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++
++ _rtw_roaming(adapter, tgt_network);
++
++#ifdef CONFIG_INTEL_WIDI
++ if (!rtw_to_roaming(adapter))
++ process_intel_widi_disconnect(adapter, 1);
++#endif // CONFIG_INTEL_WIDI
++ }
++
++ if ( check_fwstate(pmlmepriv,WIFI_ADHOC_MASTER_STATE) ||
++ check_fwstate(pmlmepriv,WIFI_ADHOC_STATE))
++ {
++ psta = rtw_get_stainfo(&adapter->stapriv, pstadel->macaddr);
++
++ _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL);
++ rtw_free_stainfo(adapter, psta);
++ _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);
++
++ if(adapter->stapriv.asoc_sta_count== 1) //a sta + bc/mc_stainfo (not Ibss_stainfo)
++ {
++ //rtw_indicate_disconnect(adapter);//removed@20091105
++ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++ //free old ibss network
++ //pwlan = rtw_find_network(&pmlmepriv->scanned_queue, pstadel->macaddr);
++ pwlan = rtw_find_network(&pmlmepriv->scanned_queue, tgt_network->network.MacAddress);
++ if(pwlan)
++ {
++ pwlan->fixed = _FALSE;
++ rtw_free_network_nolock(pmlmepriv, pwlan);
++ }
++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++ //re-create ibss
++ pdev_network = &(adapter->registrypriv.dev_network);
++ pibss = adapter->registrypriv.dev_network.MacAddress;
++
++ _rtw_memcpy(pdev_network, &tgt_network->network, get_WLAN_BSSID_EX_sz(&tgt_network->network));
++
++ _rtw_memset(&pdev_network->Ssid, 0, sizeof(NDIS_802_11_SSID));
++ _rtw_memcpy(&pdev_network->Ssid, &pmlmepriv->assoc_ssid, sizeof(NDIS_802_11_SSID));
++
++ rtw_update_registrypriv_dev_network(adapter);
++
++ rtw_generate_random_ibss(pibss);
++
++ if(check_fwstate(pmlmepriv,WIFI_ADHOC_STATE))
++ {
++ set_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE);
++ _clr_fwstate_(pmlmepriv, WIFI_ADHOC_STATE);
++ }
++
++ if(rtw_createbss_cmd(adapter)!=_SUCCESS)
++ {
++
++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("***Error=>stadel_event_callback: rtw_createbss_cmd status FAIL*** \n "));
++
++ }
++
++
++ }
++
++ }
++
++ _exit_critical_bh(&pmlmepriv->lock, &irqL2);
++
++_func_exit_;
++
++}
++
++
++void rtw_cpwm_event_callback(PADAPTER padapter, u8 *pbuf)
++{
++#ifdef CONFIG_LPS_LCLK
++ struct reportpwrstate_parm *preportpwrstate;
++#endif
++
++_func_enter_;
++
++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("rtw_cpwm_event_callback !!!\n"));
++#ifdef CONFIG_LPS_LCLK
++ preportpwrstate = (struct reportpwrstate_parm*)pbuf;
++ preportpwrstate->state |= (u8)(padapter->pwrctrlpriv.cpwm_tog + 0x80);
++ cpwm_int_hdl(padapter, preportpwrstate);
++#endif
++
++_func_exit_;
++
++}
++
++/*
++* _rtw_join_timeout_handler - Timeout/faliure handler for CMD JoinBss
++* @adapter: pointer to _adapter structure
++*/
++void _rtw_join_timeout_handler (_adapter *adapter)
++{
++ _irqL irqL;
++ struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
++#ifdef CONFIG_LAYER2_ROAMING
++ int do_join_r;
++#endif //CONFIG_LAYER2_ROAMING
++
++#if 0
++ if (adapter->bDriverStopped == _TRUE){
++ _rtw_up_sema(&pmlmepriv->assoc_terminate);
++ return;
++ }
++#endif
++
++_func_enter_;
++#ifdef PLATFORM_FREEBSD
++ rtw_mtx_lock(NULL);
++ if (callout_pending(&adapter->mlmepriv.assoc_timer.callout)) {
++ /* callout was reset */
++ //mtx_unlock(&sc->sc_mtx);
++ rtw_mtx_unlock(NULL);
++ return;
++ }
++ if (!callout_active(&adapter->mlmepriv.assoc_timer.callout)) {
++ /* callout was stopped */
++ //mtx_unlock(&sc->sc_mtx);
++ rtw_mtx_unlock(NULL);
++ return;
++ }
++ callout_deactivate(&adapter->mlmepriv.assoc_timer.callout);
++
++
++#endif
++
++ DBG_871X("%s, fw_state=%x\n", __FUNCTION__, get_fwstate(pmlmepriv));
++
++ if(adapter->bDriverStopped ||adapter->bSurpriseRemoved)
++ return;
++
++
++ _enter_critical_bh(&pmlmepriv->lock, &irqL);
++
++ #ifdef CONFIG_LAYER2_ROAMING
++ if (rtw_to_roaming(adapter) > 0) { /* join timeout caused by roaming */
++ while(1) {
++ pmlmepriv->to_roaming--;
++ if (rtw_to_roaming(adapter) != 0) { /* try another */
++ DBG_871X("%s try another roaming\n", __FUNCTION__);
++ if( _SUCCESS!=(do_join_r=rtw_do_join(adapter)) ) {
++ DBG_871X("%s roaming do_join return %d\n", __FUNCTION__ ,do_join_r);
++ continue;
++ }
++ break;
++ } else {
++#ifdef CONFIG_INTEL_WIDI
++ if(adapter->mlmepriv.widi_state == INTEL_WIDI_STATE_ROAMING)
++ {
++ _rtw_memset(pmlmepriv->sa_ext, 0x00, L2SDTA_SERVICE_VE_LEN);
++ intel_widi_wk_cmd(adapter, INTEL_WIDI_LISTEN_WK, NULL);
++ DBG_871X("change to widi listen\n");
++ }
++#endif // CONFIG_INTEL_WIDI
++ DBG_871X("%s We've try roaming but fail\n", __FUNCTION__);
++ rtw_indicate_disconnect(adapter);
++ break;
++ }
++ }
++
++ } else
++ #endif
++ {
++ rtw_indicate_disconnect(adapter);
++ free_scanqueue(pmlmepriv);//???
++
++#ifdef CONFIG_IOCTL_CFG80211
++ //indicate disconnect for the case that join_timeout and check_fwstate != FW_LINKED
++ rtw_cfg80211_indicate_disconnect(adapter);
++#endif //CONFIG_IOCTL_CFG80211
++
++ }
++
++ _exit_critical_bh(&pmlmepriv->lock, &irqL);
++
++
++#ifdef CONFIG_DRVEXT_MODULE_WSC
++ drvext_assoc_fail_indicate(&adapter->drvextpriv);
++#endif
++#ifdef PLATFORM_FREEBSD
++ rtw_mtx_unlock(NULL);
++#endif
++
++_func_exit_;
++
++}
++
++/*
++* rtw_scan_timeout_handler - Timeout/Faliure handler for CMD SiteSurvey
++* @adapter: pointer to _adapter structure
++*/
++void rtw_scan_timeout_handler (_adapter *adapter)
++{
++ _irqL irqL;
++ struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
++
++ DBG_871X(FUNC_ADPT_FMT" fw_state=%x\n", FUNC_ADPT_ARG(adapter), get_fwstate(pmlmepriv));
++
++ _enter_critical_bh(&pmlmepriv->lock, &irqL);
++
++ _clr_fwstate_(pmlmepriv, _FW_UNDER_SURVEY);
++
++ _exit_critical_bh(&pmlmepriv->lock, &irqL);
++
++ rtw_indicate_scan_done(adapter, _TRUE);
++
++}
++
++static void rtw_auto_scan_handler(_adapter *padapter)
++{
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct pwrctrl_priv *pwrctrlpriv = &padapter->pwrctrlpriv;
++
++ //auto site survey per 60sec
++ if(pmlmepriv->scan_interval >0)
++ {
++ pmlmepriv->scan_interval--;
++ if(pmlmepriv->scan_interval==0)
++ {
++/*
++ if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY|_FW_UNDER_LINKING) == _TRUE)
++ {
++ DBG_871X("exit %s when _FW_UNDER_SURVEY|_FW_UNDER_LINKING -> \n", __FUNCTION__);
++ return;
++ }
++
++ if(pmlmepriv->sitesurveyctrl.traffic_busy == _TRUE)
++ {
++ DBG_871X("%s exit cause traffic_busy(%x)\n",__FUNCTION__, pmlmepriv->sitesurveyctrl.traffic_busy);
++ return;
++ }
++*/
++
++#ifdef CONFIG_CONCURRENT_MODE
++ if (rtw_buddy_adapter_up(padapter))
++ {
++ if ((check_buddy_fwstate(padapter, _FW_UNDER_SURVEY|_FW_UNDER_LINKING) == _TRUE) ||
++ (padapter->pbuddy_adapter->mlmepriv.LinkDetectInfo.bBusyTraffic == _TRUE))
++ {
++ DBG_871X("%s, but buddy_intf is under scanning or linking or BusyTraffic\n", __FUNCTION__);
++ return;
++ }
++ }
++#endif
++
++ DBG_871X("%s\n", __FUNCTION__);
++
++ rtw_set_802_11_bssid_list_scan(padapter, NULL, 0);
++
++ pmlmepriv->scan_interval = SCAN_INTERVAL;// 30*2 sec = 60sec
++
++ }
++
++ }
++
++}
++
++void rtw_dynamic_check_timer_handlder(_adapter *adapter)
++{
++#ifdef CONFIG_AP_MODE
++ struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
++#endif //CONFIG_AP_MODE
++ struct registry_priv *pregistrypriv = &adapter->registrypriv;
++#ifdef CONFIG_CONCURRENT_MODE
++ PADAPTER pbuddy_adapter = adapter->pbuddy_adapter;
++#endif
++
++ if(!adapter)
++ return;
++
++ if(adapter->hw_init_completed == _FALSE)
++ return;
++
++ if ((adapter->bDriverStopped == _TRUE)||(adapter->bSurpriseRemoved== _TRUE))
++ return;
++
++
++#ifdef CONFIG_CONCURRENT_MODE
++ if(pbuddy_adapter)
++ {
++ if(adapter->net_closed == _TRUE && pbuddy_adapter->net_closed == _TRUE)
++ {
++ return;
++ }
++ }
++ else
++#endif //CONFIG_CONCURRENT_MODE
++ if(adapter->net_closed == _TRUE)
++ {
++ return;
++ }
++
++ rtw_dynamic_chk_wk_cmd(adapter);
++
++ if(pregistrypriv->wifi_spec==1)
++ {
++#ifdef CONFIG_P2P
++ struct wifidirect_info *pwdinfo = &adapter->wdinfo;
++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
++#endif
++ {
++ //auto site survey
++ rtw_auto_scan_handler(adapter);
++ }
++ }
++
++#ifndef CONFIG_ACTIVE_KEEP_ALIVE_CHECK
++#ifdef CONFIG_AP_MODE
++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE)
++ {
++ expire_timeout_chk(adapter);
++ }
++#endif
++#endif //!CONFIG_ACTIVE_KEEP_ALIVE_CHECK
++
++#ifdef CONFIG_BR_EXT
++
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35))
++ rcu_read_lock();
++#endif // (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35))
++
++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35))
++ if( adapter->pnetdev->br_port
++#else // (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35))
++ if( rcu_dereference(adapter->pnetdev->rx_handler_data)
++#endif // (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35))
++ && (check_fwstate(pmlmepriv, WIFI_STATION_STATE|WIFI_ADHOC_STATE) == _TRUE) )
++ {
++ // expire NAT2.5 entry
++ void nat25_db_expire(_adapter *priv);
++ nat25_db_expire(adapter);
++
++ if (adapter->pppoe_connection_in_progress > 0) {
++ adapter->pppoe_connection_in_progress--;
++ }
++
++ // due to rtw_dynamic_check_timer_handlder() is called every 2 seconds
++ if (adapter->pppoe_connection_in_progress > 0) {
++ adapter->pppoe_connection_in_progress--;
++ }
++ }
++
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35))
++ rcu_read_unlock();
++#endif // (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35))
++
++#endif // CONFIG_BR_EXT
++
++}
++
++
++#ifdef CONFIG_SET_SCAN_DENY_TIMER
++inline bool rtw_is_scan_deny(_adapter *adapter)
++{
++ struct mlme_priv *mlmepriv = &adapter->mlmepriv;
++ return (ATOMIC_READ(&mlmepriv->set_scan_deny) != 0) ? _TRUE : _FALSE;
++}
++
++inline void rtw_clear_scan_deny(_adapter *adapter)
++{
++ struct mlme_priv *mlmepriv = &adapter->mlmepriv;
++ ATOMIC_SET(&mlmepriv->set_scan_deny, 0);
++ if (0)
++ DBG_871X(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(adapter));
++}
++
++void rtw_set_scan_deny_timer_hdl(_adapter *adapter)
++{
++ rtw_clear_scan_deny(adapter);
++}
++
++void rtw_set_scan_deny(_adapter *adapter, u32 ms)
++{
++ struct mlme_priv *mlmepriv = &adapter->mlmepriv;
++#ifdef CONFIG_CONCURRENT_MODE
++ struct mlme_priv *b_mlmepriv;
++#endif
++
++ if (0)
++ DBG_871X(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(adapter));
++ ATOMIC_SET(&mlmepriv->set_scan_deny, 1);
++ _set_timer(&mlmepriv->set_scan_deny_timer, ms);
++
++#ifdef CONFIG_CONCURRENT_MODE
++ if (!adapter->pbuddy_adapter)
++ return;
++
++ if (0)
++ DBG_871X(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(adapter->pbuddy_adapter));
++ b_mlmepriv = &adapter->pbuddy_adapter->mlmepriv;
++ ATOMIC_SET(&b_mlmepriv->set_scan_deny, 1);
++ _set_timer(&b_mlmepriv->set_scan_deny_timer, ms);
++#endif
++
++}
++#endif
++
++#if defined(IEEE80211_SCAN_RESULT_EXPIRE)
++#define RTW_SCAN_RESULT_EXPIRE IEEE80211_SCAN_RESULT_EXPIRE/HZ*1000 -1000 //3000 -1000
++#else
++#define RTW_SCAN_RESULT_EXPIRE 2000
++#endif
++
++#ifndef PLATFORM_FREEBSD
++/*
++* Select a new join candidate from the original @param candidate and @param competitor
++* @return _TRUE: candidate is updated
++* @return _FALSE: candidate is not updated
++*/
++static int rtw_check_join_candidate(struct mlme_priv *pmlmepriv
++ , struct wlan_network **candidate, struct wlan_network *competitor)
++{
++ int updated = _FALSE;
++ _adapter *adapter = container_of(pmlmepriv, _adapter, mlmepriv);
++
++
++ //check bssid, if needed
++ if(pmlmepriv->assoc_by_bssid==_TRUE) {
++ if(_rtw_memcmp(competitor->network.MacAddress, pmlmepriv->assoc_bssid, ETH_ALEN) ==_FALSE)
++ goto exit;
++ }
++
++ //check ssid, if needed
++ if(pmlmepriv->assoc_ssid.Ssid && pmlmepriv->assoc_ssid.SsidLength) {
++ if( competitor->network.Ssid.SsidLength != pmlmepriv->assoc_ssid.SsidLength
++ || _rtw_memcmp(competitor->network.Ssid.Ssid, pmlmepriv->assoc_ssid.Ssid, pmlmepriv->assoc_ssid.SsidLength) == _FALSE
++ )
++ goto exit;
++ }
++
++ if(rtw_is_desired_network(adapter, competitor) == _FALSE)
++ goto exit;
++
++#ifdef CONFIG_LAYER2_ROAMING
++ if(rtw_to_roaming(adapter) > 0) {
++ if( rtw_get_passing_time_ms((u32)competitor->last_scanned) >= RTW_SCAN_RESULT_EXPIRE
++ || is_same_ess(&competitor->network, &pmlmepriv->cur_network.network) == _FALSE
++ )
++ goto exit;
++ }
++#endif
++
++ if(*candidate == NULL ||(*candidate)->network.Rssi<competitor->network.Rssi )
++ {
++ *candidate = competitor;
++ updated = _TRUE;
++ }
++
++#if 0
++ if(pmlmepriv->assoc_by_bssid==_TRUE) { // associate with bssid
++ if( (*candidate == NULL ||(*candidate)->network.Rssi<competitor->network.Rssi )
++ && _rtw_memcmp(competitor->network.MacAddress, pmlmepriv->assoc_bssid, ETH_ALEN)==_TRUE
++ ) {
++ *candidate = competitor;
++ updated = _TRUE;
++ }
++ } else if (pmlmepriv->assoc_ssid.SsidLength == 0 ) { // associate with ssid, but ssidlength is 0
++ if( (*candidate == NULL ||(*candidate)->network.Rssi<competitor->network.Rssi ) ) {
++ *candidate = competitor;
++ updated = _TRUE;
++ }
++ } else
++#ifdef CONFIG_LAYER2_ROAMING
++ if(rtw_to_roaming(adapter)) { // roaming
++ if( (*candidate == NULL ||(*candidate)->network.Rssi<competitor->network.Rssi )
++ && is_same_ess(&competitor->network, &pmlmepriv->cur_network.network)
++ //&&(!is_same_network(&competitor->network, &pmlmepriv->cur_network.network))
++ && rtw_get_passing_time_ms((u32)competitor->last_scanned) < RTW_SCAN_RESULT_EXPIRE
++ && rtw_is_desired_network(adapter, competitor)
++ ) {
++ *candidate = competitor;
++ updated = _TRUE;
++ }
++
++ } else
++#endif
++ { // associate with ssid
++ if( (*candidate == NULL ||(*candidate)->network.Rssi<competitor->network.Rssi )
++ && (competitor->network.Ssid.SsidLength==pmlmepriv->assoc_ssid.SsidLength)
++ &&((_rtw_memcmp(competitor->network.Ssid.Ssid, pmlmepriv->assoc_ssid.Ssid, pmlmepriv->assoc_ssid.SsidLength)) == _TRUE)
++ && rtw_is_desired_network(adapter, competitor)
++ ) {
++ *candidate = competitor;
++ updated = _TRUE;
++ }
++ }
++#endif
++
++ if(updated){
++ DBG_871X("[by_bssid:%u][assoc_ssid:%s]"
++ #ifdef CONFIG_LAYER2_ROAMING
++ "[to_roaming:%u] "
++ #endif
++ "new candidate: %s("MAC_FMT", ch%u) rssi:%d\n",
++ pmlmepriv->assoc_by_bssid,
++ pmlmepriv->assoc_ssid.Ssid,
++ #ifdef CONFIG_LAYER2_ROAMING
++ rtw_to_roaming(adapter),
++ #endif
++ (*candidate)->network.Ssid.Ssid,
++ MAC_ARG((*candidate)->network.MacAddress),
++ (*candidate)->network.Configuration.DSConfig,
++ (int)(*candidate)->network.Rssi
++ );
++ }
++
++exit:
++ return updated;
++}
++
++/*
++Calling context:
++The caller of the sub-routine will be in critical section...
++
++The caller must hold the following spinlock
++
++pmlmepriv->lock
++
++
++*/
++
++int rtw_select_and_join_from_scanned_queue(struct mlme_priv *pmlmepriv )
++{
++ _irqL irqL;
++ int ret;
++ _list *phead;
++ _adapter *adapter;
++ _queue *queue = &(pmlmepriv->scanned_queue);
++ struct wlan_network *pnetwork = NULL;
++ struct wlan_network *candidate = NULL;
++ u8 bSupportAntDiv = _FALSE;
++
++_func_enter_;
++
++ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++ phead = get_list_head(queue);
++ adapter = (_adapter *)pmlmepriv->nic_hdl;
++
++ pmlmepriv->pscanned = get_next( phead );
++
++ while (!rtw_end_of_queue_search(phead, pmlmepriv->pscanned)) {
++
++ pnetwork = LIST_CONTAINOR(pmlmepriv->pscanned, struct wlan_network, list);
++ if(pnetwork==NULL){
++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("%s return _FAIL:(pnetwork==NULL)\n", __FUNCTION__));
++ ret = _FAIL;
++ goto exit;
++ }
++
++ pmlmepriv->pscanned = get_next(pmlmepriv->pscanned);
++
++ #if 0
++ DBG_871X("MacAddress:"MAC_FMT" ssid:%s\n", MAC_ARG(pnetwork->network.MacAddress), pnetwork->network.Ssid.Ssid);
++ #endif
++
++ rtw_check_join_candidate(pmlmepriv, &candidate, pnetwork);
++
++ }
++
++ if(candidate == NULL) {
++ DBG_871X("%s: return _FAIL(candidate == NULL)\n", __FUNCTION__);
++ ret = _FAIL;
++ goto exit;
++ } else {
++ DBG_871X("%s: candidate: %s("MAC_FMT", ch:%u)\n", __FUNCTION__,
++ candidate->network.Ssid.Ssid, MAC_ARG(candidate->network.MacAddress),
++ candidate->network.Configuration.DSConfig);
++ }
++
++
++ // check for situation of _FW_LINKED
++ if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)
++ {
++ DBG_871X("%s: _FW_LINKED while ask_for_joinbss!!!\n", __FUNCTION__);
++
++ #if 0 // for WPA/WPA2 authentication, wpa_supplicant will expect authentication from AP, it is needed to reconnect AP...
++ if(is_same_network(&pmlmepriv->cur_network.network, &candidate->network))
++ {
++ DBG_871X("%s: _FW_LINKED and is same network, it needn't join again\n", __FUNCTION__);
++
++ rtw_indicate_connect(adapter);//rtw_indicate_connect again
++
++ ret = 2;
++ goto exit;
++ }
++ else
++ #endif
++ {
++ rtw_disassoc_cmd(adapter, 0, _TRUE);
++ rtw_indicate_disconnect(adapter);
++ rtw_free_assoc_resources(adapter, 0);
++ }
++ }
++
++ #ifdef CONFIG_ANTENNA_DIVERSITY
++ rtw_hal_get_def_var(adapter, HAL_DEF_IS_SUPPORT_ANT_DIV, &(bSupportAntDiv));
++ if(_TRUE == bSupportAntDiv)
++ {
++ u8 CurrentAntenna;
++ rtw_hal_get_def_var(adapter, HAL_DEF_CURRENT_ANTENNA, &(CurrentAntenna));
++ DBG_871X("#### Opt_Ant_(%s) , cur_Ant(%s)\n",
++ (2==candidate->network.PhyInfo.Optimum_antenna)?"A":"B",
++ (2==CurrentAntenna)?"A":"B"
++ );
++ }
++ #endif
++ set_fwstate(pmlmepriv, _FW_UNDER_LINKING);
++ ret = rtw_joinbss_cmd(adapter, candidate);
++
++exit:
++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++
++_func_exit_;
++
++ return ret;
++}
++#else
++int rtw_select_and_join_from_scanned_queue(struct mlme_priv *pmlmepriv )
++{
++ _irqL irqL;
++ _list *phead;
++#ifdef CONFIG_ANTENNA_DIVERSITY
++ u8 CurrentAntenna;
++#endif
++ unsigned char *dst_ssid, *src_ssid;
++ _adapter *adapter;
++ _queue *queue = &(pmlmepriv->scanned_queue);
++ struct wlan_network *pnetwork = NULL;
++ struct wlan_network *pnetwork_max_rssi = NULL;
++ #ifdef CONFIG_LAYER2_ROAMING
++ struct wlan_network * roaming_candidate=NULL;
++ u32 cur_time=rtw_get_current_time();
++ #endif
++
++_func_enter_;
++ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++ phead = get_list_head(queue);
++ adapter = (_adapter *)pmlmepriv->nic_hdl;
++
++ pmlmepriv->pscanned = get_next( phead );
++
++ while (!rtw_end_of_queue_search(phead, pmlmepriv->pscanned)) {
++
++ pnetwork = LIST_CONTAINOR(pmlmepriv->pscanned, struct wlan_network, list);
++ if(pnetwork==NULL){
++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("(2)rtw_select_and_join_from_scanned_queue return _FAIL:(pnetwork==NULL)\n"));
++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++ return _FAIL;
++ }
++
++ dst_ssid = pnetwork->network.Ssid.Ssid;
++ src_ssid = pmlmepriv->assoc_ssid.Ssid;
++
++ pmlmepriv->pscanned = get_next(pmlmepriv->pscanned);
++
++ #if 0
++ DBG_871X("MacAddress:"MAC_FMT" ssid:%s\n", MAC_ARG(pnetwork->network.MacAddress), pnetwork->network.Ssid.Ssid);
++ #endif
++
++ if(pmlmepriv->assoc_by_bssid==_TRUE)
++ {
++ if(_rtw_memcmp(pnetwork->network.MacAddress, pmlmepriv->assoc_bssid, ETH_ALEN)==_TRUE)
++ {
++ //remove the condition @ 20081125
++ //if((pmlmepriv->cur_network.network.InfrastructureMode==Ndis802_11AutoUnknown)||
++ // pmlmepriv->cur_network.network.InfrastructureMode == pnetwork->network.InfrastructureMode)
++ // goto ask_for_joinbss;
++
++ if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)
++ {
++ if(is_same_network(&pmlmepriv->cur_network.network, &pnetwork->network))
++ {
++ //DBG_871X("select_and_join(1): _FW_LINKED and is same network, it needn't join again\n");
++
++ rtw_indicate_connect(adapter);//rtw_indicate_connect again
++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++ return 2;
++ }
++ else
++ {
++ rtw_disassoc_cmd(adapter, 0, _TRUE);
++ rtw_indicate_disconnect(adapter);
++ rtw_free_assoc_resources(adapter, 0);
++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++ goto ask_for_joinbss;
++
++ }
++ }
++ else
++ {
++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++ goto ask_for_joinbss;
++ }
++
++ }
++
++ } else if (pmlmepriv->assoc_ssid.SsidLength == 0) {
++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++ goto ask_for_joinbss;//anyway, join first selected(dequeued) pnetwork if ssid_len=0
++
++ #ifdef CONFIG_LAYER2_ROAMING
++ } else if (rtw_to_roaming(adapter) > 0) {
++
++ if( (roaming_candidate == NULL ||roaming_candidate->network.Rssi<pnetwork->network.Rssi )
++ && is_same_ess(&pnetwork->network, &pmlmepriv->cur_network.network)
++ //&&(!is_same_network(&pnetwork->network, &pmlmepriv->cur_network.network))
++ && rtw_get_time_interval_ms((u32)pnetwork->last_scanned,cur_time) < 5000
++ ) {
++ roaming_candidate = pnetwork;
++ //RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,
++ DBG_871X
++ ("roaming_candidate???: %s("MAC_FMT")\n",
++ roaming_candidate->network.Ssid.Ssid, MAC_ARG(roaming_candidate->network.MacAddress) )
++ //)
++ ;
++ }
++ continue;
++ #endif
++
++ } else if ( (pnetwork->network.Ssid.SsidLength==pmlmepriv->assoc_ssid.SsidLength)
++ &&((_rtw_memcmp(dst_ssid, src_ssid, pmlmepriv->assoc_ssid.SsidLength)) == _TRUE)
++ )
++ {
++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("dst_ssid=%s, src_ssid=%s \n", dst_ssid, src_ssid));
++#ifdef CONFIG_ANTENNA_DIVERSITY
++ rtw_hal_get_def_var(adapter, HAL_DEF_CURRENT_ANTENNA, &(CurrentAntenna));
++ DBG_871X("#### dst_ssid=(%s) Opt_Ant_(%s) , cur_Ant(%s)\n", dst_ssid,
++ (2==pnetwork->network.PhyInfo.Optimum_antenna)?"A":"B",
++ (2==CurrentAntenna)?"A":"B");
++#endif
++ //remove the condition @ 20081125
++ //if((pmlmepriv->cur_network.network.InfrastructureMode==Ndis802_11AutoUnknown)||
++ // pmlmepriv->cur_network.network.InfrastructureMode == pnetwork->network.InfrastructureMode)
++ //{
++ // _rtw_memcpy(pmlmepriv->assoc_bssid, pnetwork->network.MacAddress, ETH_ALEN);
++ // goto ask_for_joinbss;
++ //}
++
++ if(pmlmepriv->assoc_by_rssi==_TRUE)//if the ssid is the same, select the bss which has the max rssi
++ {
++ if( NULL==pnetwork_max_rssi|| pnetwork->network.Rssi > pnetwork_max_rssi->network.Rssi)
++ pnetwork_max_rssi = pnetwork;
++ }
++ else if(rtw_is_desired_network(adapter, pnetwork) == _TRUE)
++ {
++ if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)
++ {
++#if 0
++ if(is_same_network(&pmlmepriv->cur_network.network, &pnetwork->network))
++ {
++ DBG_871X("select_and_join(2): _FW_LINKED and is same network, it needn't join again\n");
++
++ rtw_indicate_connect(adapter);//rtw_indicate_connect again
++
++ return 2;
++ }
++ else
++#endif
++ {
++ rtw_disassoc_cmd(adapter, 0, _TRUE);
++ //rtw_indicate_disconnect(adapter);//
++ rtw_free_assoc_resources(adapter, 0);
++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++ goto ask_for_joinbss;
++ }
++ }
++ else
++ {
++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++ goto ask_for_joinbss;
++ }
++
++ }
++
++
++ }
++
++ }
++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++ #ifdef CONFIG_LAYER2_ROAMING
++ if(rtw_to_roaming(adapter) > 0 && roaming_candidate ){
++ pnetwork=roaming_candidate;
++ DBG_871X("select_and_join_from_scanned_queue: roaming_candidate: %s("MAC_FMT")\n",
++ pnetwork->network.Ssid.Ssid, MAC_ARG(pnetwork->network.MacAddress));
++ goto ask_for_joinbss;
++ }
++ #endif
++
++ if((pmlmepriv->assoc_by_rssi==_TRUE) && (pnetwork_max_rssi!=NULL))
++ {
++ pnetwork = pnetwork_max_rssi;
++ DBG_871X("select_and_join_from_scanned_queue: pnetwork_max_rssi: %s("MAC_FMT")\n",
++ pnetwork->network.Ssid.Ssid, MAC_ARG(pnetwork->network.MacAddress));
++ goto ask_for_joinbss;
++ }
++
++ DBG_871X("(1)rtw_select_and_join_from_scanned_queue return _FAIL\n");
++
++_func_exit_;
++
++ return _FAIL;
++
++ask_for_joinbss:
++
++_func_exit_;
++
++ return rtw_joinbss_cmd(adapter, pnetwork);
++
++}
++#endif //PLATFORM_FREEBSD
++
++
++sint rtw_set_auth(_adapter * adapter,struct security_priv *psecuritypriv)
++{
++ struct cmd_obj* pcmd;
++ struct setauth_parm *psetauthparm;
++ struct cmd_priv *pcmdpriv=&(adapter->cmdpriv);
++ sint res=_SUCCESS;
++
++_func_enter_;
++
++ pcmd = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj));
++ if(pcmd==NULL){
++ res= _FAIL; //try again
++ goto exit;
++ }
++
++ psetauthparm=(struct setauth_parm*)rtw_zmalloc(sizeof(struct setauth_parm));
++ if(psetauthparm==NULL){
++ rtw_mfree((unsigned char *)pcmd, sizeof(struct cmd_obj));
++ res= _FAIL;
++ goto exit;
++ }
++
++ _rtw_memset(psetauthparm, 0, sizeof(struct setauth_parm));
++ psetauthparm->mode=(unsigned char)psecuritypriv->dot11AuthAlgrthm;
++
++ pcmd->cmdcode = _SetAuth_CMD_;
++ pcmd->parmbuf = (unsigned char *)psetauthparm;
++ pcmd->cmdsz = (sizeof(struct setauth_parm));
++ pcmd->rsp = NULL;
++ pcmd->rspsz = 0;
++
++
++ _rtw_init_listhead(&pcmd->list);
++
++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("after enqueue set_auth_cmd, auth_mode=%x\n", psecuritypriv->dot11AuthAlgrthm));
++
++ res = rtw_enqueue_cmd(pcmdpriv, pcmd);
++
++exit:
++
++_func_exit_;
++
++ return res;
++
++}
++
++
++sint rtw_set_key(_adapter * adapter,struct security_priv *psecuritypriv,sint keyid, u8 set_tx)
++{
++ u8 keylen;
++ struct cmd_obj *pcmd;
++ struct setkey_parm *psetkeyparm;
++ struct cmd_priv *pcmdpriv = &(adapter->cmdpriv);
++ struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
++ sint res=_SUCCESS;
++
++_func_enter_;
++
++ pcmd = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj));
++ if(pcmd==NULL){
++ res= _FAIL; //try again
++ goto exit;
++ }
++ psetkeyparm=(struct setkey_parm*)rtw_zmalloc(sizeof(struct setkey_parm));
++ if(psetkeyparm==NULL){
++ rtw_mfree((unsigned char *)pcmd, sizeof(struct cmd_obj));
++ res= _FAIL;
++ goto exit;
++ }
++
++ _rtw_memset(psetkeyparm, 0, sizeof(struct setkey_parm));
++
++ if(psecuritypriv->dot11AuthAlgrthm ==dot11AuthAlgrthm_8021X){
++ psetkeyparm->algorithm=(unsigned char)psecuritypriv->dot118021XGrpPrivacy;
++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("\n rtw_set_key: psetkeyparm->algorithm=(unsigned char)psecuritypriv->dot118021XGrpPrivacy=%d \n", psetkeyparm->algorithm));
++ }
++ else{
++ psetkeyparm->algorithm=(u8)psecuritypriv->dot11PrivacyAlgrthm;
++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("\n rtw_set_key: psetkeyparm->algorithm=(u8)psecuritypriv->dot11PrivacyAlgrthm=%d \n", psetkeyparm->algorithm));
++
++ }
++ psetkeyparm->keyid = (u8)keyid;//0~3
++ psetkeyparm->set_tx = set_tx;
++ if (is_wep_enc(psetkeyparm->algorithm))
++ psecuritypriv->key_mask |= BIT(psetkeyparm->keyid);
++
++ DBG_871X("==> rtw_set_key algorithm(%x),keyid(%x),key_mask(%x)\n",psetkeyparm->algorithm,psetkeyparm->keyid, psecuritypriv->key_mask);
++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("\n rtw_set_key: psetkeyparm->algorithm=%d psetkeyparm->keyid=(u8)keyid=%d \n",psetkeyparm->algorithm, keyid));
++
++ switch(psetkeyparm->algorithm){
++
++ case _WEP40_:
++ keylen=5;
++ _rtw_memcpy(&(psetkeyparm->key[0]), &(psecuritypriv->dot11DefKey[keyid].skey[0]), keylen);
++ break;
++ case _WEP104_:
++ keylen=13;
++ _rtw_memcpy(&(psetkeyparm->key[0]), &(psecuritypriv->dot11DefKey[keyid].skey[0]), keylen);
++ break;
++ case _TKIP_:
++ keylen=16;
++ _rtw_memcpy(&psetkeyparm->key, &psecuritypriv->dot118021XGrpKey[keyid], keylen);
++ psetkeyparm->grpkey=1;
++ break;
++ case _AES_:
++ keylen=16;
++ _rtw_memcpy(&psetkeyparm->key, &psecuritypriv->dot118021XGrpKey[keyid], keylen);
++ psetkeyparm->grpkey=1;
++ break;
++ default:
++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("\n rtw_set_key:psecuritypriv->dot11PrivacyAlgrthm = %x (must be 1 or 2 or 4 or 5)\n",psecuritypriv->dot11PrivacyAlgrthm));
++ res= _FAIL;
++ goto exit;
++ }
++
++
++ pcmd->cmdcode = _SetKey_CMD_;
++ pcmd->parmbuf = (u8 *)psetkeyparm;
++ pcmd->cmdsz = (sizeof(struct setkey_parm));
++ pcmd->rsp = NULL;
++ pcmd->rspsz = 0;
++
++
++ _rtw_init_listhead(&pcmd->list);
++
++ //_rtw_init_sema(&(pcmd->cmd_sem), 0);
++
++ res = rtw_enqueue_cmd(pcmdpriv, pcmd);
++
++exit:
++_func_exit_;
++ return res;
++
++}
++
++
++//adjust IEs for rtw_joinbss_cmd in WMM
++int rtw_restruct_wmm_ie(_adapter *adapter, u8 *in_ie, u8 *out_ie, uint in_len, uint initial_out_len)
++{
++ unsigned int ielength=0;
++ unsigned int i, j;
++
++ i = 12; //after the fixed IE
++ while(i<in_len)
++ {
++ ielength = initial_out_len;
++
++ if(in_ie[i] == 0xDD && in_ie[i+2] == 0x00 && in_ie[i+3] == 0x50 && in_ie[i+4] == 0xF2 && in_ie[i+5] == 0x02 && i+5 < in_len) //WMM element ID and OUI
++ {
++
++ //Append WMM IE to the last index of out_ie
++ /*
++ for(j=i; j< i+(in_ie[i+1]+2); j++)
++ {
++ out_ie[ielength] = in_ie[j];
++ ielength++;
++ }
++ out_ie[initial_out_len+8] = 0x00; //force the QoS Info Field to be zero
++ */
++
++ for ( j = i; j < i + 9; j++ )
++ {
++ out_ie[ ielength] = in_ie[ j ];
++ ielength++;
++ }
++ out_ie[ initial_out_len + 1 ] = 0x07;
++ out_ie[ initial_out_len + 6 ] = 0x00;
++ out_ie[ initial_out_len + 8 ] = 0x00;
++
++ break;
++ }
++
++ i+=(in_ie[i+1]+2); // to the next IE element
++ }
++
++ return ielength;
++
++}
++
++
++//
++// Ported from 8185: IsInPreAuthKeyList(). (Renamed from SecIsInPreAuthKeyList(), 2006-10-13.)
++// Added by Annie, 2006-05-07.
++//
++// Search by BSSID,
++// Return Value:
++// -1 :if there is no pre-auth key in the table
++// >=0 :if there is pre-auth key, and return the entry id
++//
++//
++
++static int SecIsInPMKIDList(_adapter *Adapter, u8 *bssid)
++{
++ struct security_priv *psecuritypriv=&Adapter->securitypriv;
++ int i=0;
++
++ do
++ {
++ if( ( psecuritypriv->PMKIDList[i].bUsed ) &&
++ ( _rtw_memcmp( psecuritypriv->PMKIDList[i].Bssid, bssid, ETH_ALEN ) == _TRUE ) )
++ {
++ break;
++ }
++ else
++ {
++ i++;
++ //continue;
++ }
++
++ }while(i<NUM_PMKID_CACHE);
++
++ if( i == NUM_PMKID_CACHE )
++ {
++ i = -1;// Could not find.
++ }
++ else
++ {
++ // There is one Pre-Authentication Key for the specific BSSID.
++ }
++
++ return (i);
++
++}
++
++//
++// Check the RSN IE length
++// If the RSN IE length <= 20, the RSN IE didn't include the PMKID information
++// 0-11th element in the array are the fixed IE
++// 12th element in the array is the IE
++// 13th element in the array is the IE length
++//
++
++static int rtw_append_pmkid(_adapter *Adapter,int iEntry, u8 *ie, uint ie_len)
++{
++ struct security_priv *psecuritypriv=&Adapter->securitypriv;
++
++ if(ie[13]<=20){
++ // The RSN IE didn't include the PMK ID, append the PMK information
++ ie[ie_len]=1;
++ ie_len++;
++ ie[ie_len]=0; //PMKID count = 0x0100
++ ie_len++;
++ _rtw_memcpy( &ie[ie_len], &psecuritypriv->PMKIDList[iEntry].PMKID, 16);
++
++ ie_len+=16;
++ ie[13]+=18;//PMKID length = 2+16
++
++ }
++ return (ie_len);
++
++}
++sint rtw_restruct_sec_ie(_adapter *adapter,u8 *in_ie, u8 *out_ie, uint in_len)
++{
++ u8 authmode, securitytype, match;
++ u8 sec_ie[255], uncst_oui[4], bkup_ie[255];
++ u8 wpa_oui[4]={0x0, 0x50, 0xf2, 0x01};
++ uint ielength, cnt, remove_cnt;
++ int iEntry;
++
++ struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
++ struct security_priv *psecuritypriv=&adapter->securitypriv;
++ uint ndisauthmode=psecuritypriv->ndisauthtype;
++ uint ndissecuritytype = psecuritypriv->ndisencryptstatus;
++
++_func_enter_;
++
++ RT_TRACE(_module_rtl871x_mlme_c_, _drv_notice_,
++ ("+rtw_restruct_sec_ie: ndisauthmode=%d ndissecuritytype=%d\n",
++ ndisauthmode, ndissecuritytype));
++
++ //copy fixed ie only
++ _rtw_memcpy(out_ie, in_ie,12);
++ ielength=12;
++ if((ndisauthmode==Ndis802_11AuthModeWPA)||(ndisauthmode==Ndis802_11AuthModeWPAPSK))
++ authmode=_WPA_IE_ID_;
++ if((ndisauthmode==Ndis802_11AuthModeWPA2)||(ndisauthmode==Ndis802_11AuthModeWPA2PSK))
++ authmode=_WPA2_IE_ID_;
++
++ if(check_fwstate(pmlmepriv, WIFI_UNDER_WPS))
++ {
++ _rtw_memcpy(out_ie+ielength, psecuritypriv->wps_ie, psecuritypriv->wps_ie_len);
++
++ ielength += psecuritypriv->wps_ie_len;
++ }
++ else if((authmode==_WPA_IE_ID_)||(authmode==_WPA2_IE_ID_))
++ {
++ //copy RSN or SSN
++ _rtw_memcpy(&out_ie[ielength], &psecuritypriv->supplicant_ie[0], psecuritypriv->supplicant_ie[1]+2);
++ /* debug for CONFIG_IEEE80211W
++ {
++ int jj;
++ printk("supplicant_ie_length=%d &&&&&&&&&&&&&&&&&&&\n", psecuritypriv->supplicant_ie[1]+2);
++ for(jj=0; jj < psecuritypriv->supplicant_ie[1]+2; jj++)
++ printk(" %02x ", psecuritypriv->supplicant_ie[jj]);
++ printk("\n");
++ }*/
++ ielength+=psecuritypriv->supplicant_ie[1]+2;
++ rtw_report_sec_ie(adapter, authmode, psecuritypriv->supplicant_ie);
++
++#ifdef CONFIG_DRVEXT_MODULE
++ drvext_report_sec_ie(&adapter->drvextpriv, authmode, sec_ie);
++#endif
++ }
++
++ iEntry = SecIsInPMKIDList(adapter, pmlmepriv->assoc_bssid);
++ if(iEntry<0)
++ {
++ return ielength;
++ }
++ else
++ {
++ if(authmode == _WPA2_IE_ID_)
++ {
++ ielength=rtw_append_pmkid(adapter, iEntry, out_ie, ielength);
++ }
++ }
++
++_func_exit_;
++
++ return ielength;
++}
++
++void rtw_init_registrypriv_dev_network( _adapter* adapter)
++{
++ struct registry_priv* pregistrypriv = &adapter->registrypriv;
++ struct eeprom_priv* peepriv = &adapter->eeprompriv;
++ WLAN_BSSID_EX *pdev_network = &pregistrypriv->dev_network;
++ u8 *myhwaddr = myid(peepriv);
++
++_func_enter_;
++
++ _rtw_memcpy(pdev_network->MacAddress, myhwaddr, ETH_ALEN);
++
++ _rtw_memcpy(&pdev_network->Ssid, &pregistrypriv->ssid, sizeof(NDIS_802_11_SSID));
++
++ pdev_network->Configuration.Length=sizeof(NDIS_802_11_CONFIGURATION);
++ pdev_network->Configuration.BeaconPeriod = 100;
++ pdev_network->Configuration.FHConfig.Length = 0;
++ pdev_network->Configuration.FHConfig.HopPattern = 0;
++ pdev_network->Configuration.FHConfig.HopSet = 0;
++ pdev_network->Configuration.FHConfig.DwellTime = 0;
++
++
++_func_exit_;
++
++}
++
++void rtw_update_registrypriv_dev_network(_adapter* adapter)
++{
++ int sz=0;
++ struct registry_priv* pregistrypriv = &adapter->registrypriv;
++ WLAN_BSSID_EX *pdev_network = &pregistrypriv->dev_network;
++ struct security_priv* psecuritypriv = &adapter->securitypriv;
++ struct wlan_network *cur_network = &adapter->mlmepriv.cur_network;
++ //struct xmit_priv *pxmitpriv = &adapter->xmitpriv;
++
++_func_enter_;
++
++#if 0
++ pxmitpriv->vcs_setting = pregistrypriv->vrtl_carrier_sense;
++ pxmitpriv->vcs = pregistrypriv->vcs_type;
++ pxmitpriv->vcs_type = pregistrypriv->vcs_type;
++ //pxmitpriv->rts_thresh = pregistrypriv->rts_thresh;
++ pxmitpriv->frag_len = pregistrypriv->frag_thresh;
++
++ adapter->qospriv.qos_option = pregistrypriv->wmm_enable;
++#endif
++
++ pdev_network->Privacy = (psecuritypriv->dot11PrivacyAlgrthm > 0 ? 1 : 0) ; // adhoc no 802.1x
++
++ pdev_network->Rssi = 0;
++
++ switch(pregistrypriv->wireless_mode)
++ {
++ case WIRELESS_11B:
++ pdev_network->NetworkTypeInUse = (Ndis802_11DS);
++ break;
++ case WIRELESS_11G:
++ case WIRELESS_11BG:
++ case WIRELESS_11_24N:
++ case WIRELESS_11G_24N:
++ case WIRELESS_11BG_24N:
++ pdev_network->NetworkTypeInUse = (Ndis802_11OFDM24);
++ break;
++ case WIRELESS_11A:
++ case WIRELESS_11A_5N:
++ pdev_network->NetworkTypeInUse = (Ndis802_11OFDM5);
++ break;
++ case WIRELESS_11ABGN:
++ if(pregistrypriv->channel > 14)
++ pdev_network->NetworkTypeInUse = (Ndis802_11OFDM5);
++ else
++ pdev_network->NetworkTypeInUse = (Ndis802_11OFDM24);
++ break;
++ default :
++ // TODO
++ break;
++ }
++
++ pdev_network->Configuration.DSConfig = (pregistrypriv->channel);
++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("pregistrypriv->channel=%d, pdev_network->Configuration.DSConfig=0x%x\n", pregistrypriv->channel, pdev_network->Configuration.DSConfig));
++
++ if(cur_network->network.InfrastructureMode == Ndis802_11IBSS)
++ pdev_network->Configuration.ATIMWindow = (0);
++
++ pdev_network->InfrastructureMode = (cur_network->network.InfrastructureMode);
++
++ // 1. Supported rates
++ // 2. IE
++
++ //rtw_set_supported_rate(pdev_network->SupportedRates, pregistrypriv->wireless_mode) ; // will be called in rtw_generate_ie
++ sz = rtw_generate_ie(pregistrypriv);
++
++ pdev_network->IELength = sz;
++
++ pdev_network->Length = get_WLAN_BSSID_EX_sz((WLAN_BSSID_EX *)pdev_network);
++
++ //notes: translate IELength & Length after assign the Length to cmdsz in createbss_cmd();
++ //pdev_network->IELength = cpu_to_le32(sz);
++
++_func_exit_;
++
++}
++
++void rtw_get_encrypt_decrypt_from_registrypriv(_adapter* adapter)
++{
++_func_enter_;
++
++
++_func_exit_;
++
++}
++
++//the fucntion is at passive_level
++void rtw_joinbss_reset(_adapter *padapter)
++{
++ u8 threshold;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++
++#ifdef CONFIG_80211N_HT
++ struct ht_priv *phtpriv = &pmlmepriv->htpriv;
++#endif
++
++ //todo: if you want to do something io/reg/hw setting before join_bss, please add code here
++
++
++
++
++#ifdef CONFIG_80211N_HT
++
++ pmlmepriv->num_FortyMHzIntolerant = 0;
++
++ pmlmepriv->num_sta_no_ht = 0;
++
++ phtpriv->ampdu_enable = _FALSE;//reset to disabled
++
++#ifdef CONFIG_USB_HCI
++ // TH=1 => means that invalidate usb rx aggregation
++ // TH=0 => means that validate usb rx aggregation, use init value.
++ if(phtpriv->ht_option)
++ {
++ if(padapter->registrypriv.wifi_spec==1)
++ threshold = 1;
++ else
++ threshold = 0;
++ rtw_hal_set_hwreg(padapter, HW_VAR_RXDMA_AGG_PG_TH, (u8 *)(&threshold));
++ }
++ else
++ {
++ threshold = 1;
++ rtw_hal_set_hwreg(padapter, HW_VAR_RXDMA_AGG_PG_TH, (u8 *)(&threshold));
++ }
++#endif
++
++#endif
++
++}
++
++
++#ifdef CONFIG_80211N_HT
++
++//the fucntion is >= passive_level
++unsigned int rtw_restructure_ht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, uint in_len, uint *pout_len, u8 channel)
++{
++ u32 ielen, out_len;
++ unsigned char *p, *pframe;
++ struct rtw_ieee80211_ht_cap ht_capie;
++ unsigned char WMM_IE[] = {0x00, 0x50, 0xf2, 0x02, 0x00, 0x01, 0x00};
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct qos_priv *pqospriv= &pmlmepriv->qospriv;
++ struct ht_priv *phtpriv = &pmlmepriv->htpriv;
++ struct registry_priv *pregpriv = &padapter->registrypriv;
++ u8 cbw40_enable = 0;
++
++ phtpriv->ht_option = _FALSE;
++
++ p = rtw_get_ie(in_ie+12, _HT_CAPABILITY_IE_, &ielen, in_len-12);
++
++ if(p && ielen>0)
++ {
++ if(pqospriv->qos_option == 0)
++ {
++ out_len = *pout_len;
++ pframe = rtw_set_ie(out_ie+out_len, _VENDOR_SPECIFIC_IE_,
++ _WMM_IE_Length_, WMM_IE, pout_len);
++
++ pqospriv->qos_option = 1;
++ }
++
++ out_len = *pout_len;
++
++ _rtw_memset(&ht_capie, 0, sizeof(struct rtw_ieee80211_ht_cap));
++
++ ht_capie.cap_info = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_TX_STBC |
++ IEEE80211_HT_CAP_DSSSCCK40;
++ //if insert module set only support 20MHZ, don't add the 40MHZ and SGI_40
++ if( channel > 14 )
++ {
++ if( pregpriv->cbw40_enable & BIT(1) )
++ cbw40_enable = 1;
++ }
++ else
++ if( pregpriv->cbw40_enable & BIT(0) )
++ cbw40_enable = 1;
++
++ if ( cbw40_enable != 0 )
++ ht_capie.cap_info |= IEEE80211_HT_CAP_SUP_WIDTH | IEEE80211_HT_CAP_SGI_40;
++
++
++
++ {
++ u32 rx_packet_offset, max_recvbuf_sz;
++ rtw_hal_get_def_var(padapter, HAL_DEF_RX_PACKET_OFFSET, &rx_packet_offset);
++ rtw_hal_get_def_var(padapter, HAL_DEF_MAX_RECVBUF_SZ, &max_recvbuf_sz);
++ //if(max_recvbuf_sz-rx_packet_offset>(8191-256)) {
++ // DBG_871X("%s IEEE80211_HT_CAP_MAX_AMSDU is set\n", __FUNCTION__);
++ // ht_capie.cap_info = ht_capie.cap_info |IEEE80211_HT_CAP_MAX_AMSDU;
++ //}
++ }
++
++ ht_capie.ampdu_params_info = (IEEE80211_HT_CAP_AMPDU_FACTOR&0x03);
++
++ if(padapter->securitypriv.dot11PrivacyAlgrthm == _AES_ )
++ ht_capie.ampdu_params_info |= (IEEE80211_HT_CAP_AMPDU_DENSITY&(0x07<<2));
++ else
++ ht_capie.ampdu_params_info |= (IEEE80211_HT_CAP_AMPDU_DENSITY&0x00);
++
++
++ pframe = rtw_set_ie(out_ie+out_len, _HT_CAPABILITY_IE_,
++ sizeof(struct rtw_ieee80211_ht_cap), (unsigned char*)&ht_capie, pout_len);
++
++
++ //_rtw_memcpy(out_ie+out_len, p, ielen+2);//gtest
++ //*pout_len = *pout_len + (ielen+2);
++
++
++ phtpriv->ht_option = _TRUE;
++
++ p = rtw_get_ie(in_ie+12, _HT_ADD_INFO_IE_, &ielen, in_len-12);
++ if(p && (ielen==sizeof(struct ieee80211_ht_addt_info)))
++ {
++ out_len = *pout_len;
++ pframe = rtw_set_ie(out_ie+out_len, _HT_ADD_INFO_IE_, ielen, p+2 , pout_len);
++ }
++
++ }
++
++ return (phtpriv->ht_option);
++
++}
++
++//the fucntion is > passive_level (in critical_section)
++void rtw_update_ht_cap(_adapter *padapter, u8 *pie, uint ie_len, u8 channel)
++{
++ u8 *p, max_ampdu_sz;
++ int len;
++ //struct sta_info *bmc_sta, *psta;
++ struct rtw_ieee80211_ht_cap *pht_capie;
++ struct ieee80211_ht_addt_info *pht_addtinfo;
++ //struct recv_reorder_ctrl *preorder_ctrl;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct ht_priv *phtpriv = &pmlmepriv->htpriv;
++ //struct recv_priv *precvpriv = &padapter->recvpriv;
++ struct registry_priv *pregistrypriv = &padapter->registrypriv;
++ //struct wlan_network *pcur_network = &(pmlmepriv->cur_network);;
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ u8 cbw40_enable=0;
++
++ if(!phtpriv->ht_option)
++ return;
++
++ if ((!pmlmeinfo->HT_info_enable) || (!pmlmeinfo->HT_caps_enable))
++ return;
++
++ DBG_871X("+rtw_update_ht_cap()\n");
++
++ //maybe needs check if ap supports rx ampdu.
++ if((phtpriv->ampdu_enable==_FALSE) &&(pregistrypriv->ampdu_enable==1))
++ {
++ //In the wifi cert. test, the test Lab should turn off the AP's RX AMPDU. client doen't need to close the TX AMPDU
++ /*if(pregistrypriv->wifi_spec==1)
++ {
++ phtpriv->ampdu_enable = _FALSE;
++ }
++ else*/
++ {
++ phtpriv->ampdu_enable = _TRUE;
++ }
++ }
++ else if(pregistrypriv->ampdu_enable==2)
++ {
++ phtpriv->ampdu_enable = _TRUE;
++ }
++
++
++ //check Max Rx A-MPDU Size
++ len = 0;
++ p = rtw_get_ie(pie+sizeof (NDIS_802_11_FIXED_IEs), _HT_CAPABILITY_IE_, &len, ie_len-sizeof (NDIS_802_11_FIXED_IEs));
++ if(p && len>0)
++ {
++ pht_capie = (struct rtw_ieee80211_ht_cap *)(p+2);
++ max_ampdu_sz = (pht_capie->ampdu_params_info & IEEE80211_HT_CAP_AMPDU_FACTOR);
++ max_ampdu_sz = 1 << (max_ampdu_sz+3); // max_ampdu_sz (kbytes);
++
++ //DBG_871X("rtw_update_ht_cap(): max_ampdu_sz=%d\n", max_ampdu_sz);
++ phtpriv->rx_ampdu_maxlen = max_ampdu_sz;
++
++ }
++
++
++ len=0;
++ p = rtw_get_ie(pie+sizeof (NDIS_802_11_FIXED_IEs), _HT_ADD_INFO_IE_, &len, ie_len-sizeof (NDIS_802_11_FIXED_IEs));
++ if(p && len>0)
++ {
++ pht_addtinfo = (struct ieee80211_ht_addt_info *)(p+2);
++ //todo:
++ }
++
++ if( channel > 14 )
++ {
++ if( pregistrypriv->cbw40_enable & BIT(1) )
++ cbw40_enable = 1;
++ }
++ else
++ if( pregistrypriv->cbw40_enable & BIT(0) )
++ cbw40_enable = 1;
++
++
++ //update cur_bwmode & cur_ch_offset
++ if ((cbw40_enable) &&
++ (pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info & BIT(1)) &&
++ (pmlmeinfo->HT_info.infos[0] & BIT(2)))
++ {
++ int i;
++ u8 rf_type;
++
++ rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));
++
++ //update the MCS rates
++ for (i = 0; i < 16; i++)
++ {
++ if((rf_type == RF_1T1R) || (rf_type == RF_1T2R))
++ {
++ pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate[i] &= MCS_rate_1R[i];
++ }
++ else
++ {
++ #ifdef CONFIG_DISABLE_MCS13TO15
++ if(pmlmeext->cur_bwmode == HT_CHANNEL_WIDTH_40 && pregistrypriv->wifi_spec != 1 )
++ {
++ pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate[i] &= MCS_rate_2R_MCS13TO15_OFF[i];
++ }
++ else
++ pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate[i] &= MCS_rate_2R[i];
++ #else
++ pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate[i] &= MCS_rate_2R[i];
++ #endif //CONFIG_DISABLE_MCS13TO15
++ }
++ #ifdef RTL8192C_RECONFIG_TO_1T1R
++ {
++ pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate[i] &= MCS_rate_1R[i];
++ }
++ #endif
++
++ if(pregistrypriv->special_rf_path)
++ pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate[i] &= MCS_rate_1R[i];
++
++ }
++ //switch to the 40M Hz mode accoring to the AP
++ pmlmeext->cur_bwmode = HT_CHANNEL_WIDTH_40;
++ switch ((pmlmeinfo->HT_info.infos[0] & 0x3))
++ {
++ case HT_EXTCHNL_OFFSET_UPPER:
++ pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_LOWER;
++ break;
++
++ case HT_EXTCHNL_OFFSET_LOWER:
++ pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_UPPER;
++ break;
++
++ default:
++ pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++ break;
++ }
++ }
++
++ //
++ // Config SM Power Save setting
++ //
++ pmlmeinfo->SM_PS = (pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info & 0x0C) >> 2;
++ if(pmlmeinfo->SM_PS == WLAN_HT_CAP_SM_PS_STATIC)
++ {
++ /*u8 i;
++ //update the MCS rates
++ for (i = 0; i < 16; i++)
++ {
++ pmlmeinfo->HT_caps.HT_cap_element.MCS_rate[i] &= MCS_rate_1R[i];
++ }*/
++ DBG_871X("%s(): WLAN_HT_CAP_SM_PS_STATIC\n",__FUNCTION__);
++ }
++
++ //
++ // Config current HT Protection mode.
++ //
++ pmlmeinfo->HT_protection = pmlmeinfo->HT_info.infos[1] & 0x3;
++
++
++
++#if 0 //move to rtw_update_sta_info_client()
++ //for A-MPDU Rx reordering buffer control for bmc_sta & sta_info
++ //if A-MPDU Rx is enabled, reseting rx_ordering_ctrl wstart_b(indicate_seq) to default value=0xffff
++ //todo: check if AP can send A-MPDU packets
++ bmc_sta = rtw_get_bcmc_stainfo(padapter);
++ if(bmc_sta)
++ {
++ for(i=0; i < 16 ; i++)
++ {
++ //preorder_ctrl = &precvpriv->recvreorder_ctrl[i];
++ preorder_ctrl = &bmc_sta->recvreorder_ctrl[i];
++ preorder_ctrl->enable = _FALSE;
++ preorder_ctrl->indicate_seq = 0xffff;
++ #ifdef DBG_RX_SEQ
++ DBG_871X("DBG_RX_SEQ %s:%d indicate_seq:%u \n", __FUNCTION__, __LINE__,
++ preorder_ctrl->indicate_seq);
++ #endif
++ preorder_ctrl->wend_b= 0xffff;
++ preorder_ctrl->wsize_b = 64;//max_ampdu_sz;//ex. 32(kbytes) -> wsize_b=32
++ }
++ }
++
++ psta = rtw_get_stainfo(&padapter->stapriv, pcur_network->network.MacAddress);
++ if(psta)
++ {
++ for(i=0; i < 16 ; i++)
++ {
++ //preorder_ctrl = &precvpriv->recvreorder_ctrl[i];
++ preorder_ctrl = &psta->recvreorder_ctrl[i];
++ preorder_ctrl->enable = _FALSE;
++ preorder_ctrl->indicate_seq = 0xffff;
++ #ifdef DBG_RX_SEQ
++ DBG_871X("DBG_RX_SEQ %s:%d indicate_seq:%u \n", __FUNCTION__, __LINE__,
++ preorder_ctrl->indicate_seq);
++ #endif
++ preorder_ctrl->wend_b= 0xffff;
++ preorder_ctrl->wsize_b = 64;//max_ampdu_sz;//ex. 32(kbytes) -> wsize_b=32
++ }
++ }
++#endif
++
++}
++
++void rtw_issue_addbareq_cmd(_adapter *padapter, struct xmit_frame *pxmitframe)
++{
++ u8 issued;
++ int priority;
++ struct sta_info *psta=NULL;
++ struct ht_priv *phtpriv;
++ struct pkt_attrib *pattrib =&pxmitframe->attrib;
++ s32 bmcst = IS_MCAST(pattrib->ra);
++
++ if(bmcst || (padapter->mlmepriv.LinkDetectInfo.bTxBusyTraffic == _FALSE))
++ return;
++
++ priority = pattrib->priority;
++
++ if (pattrib->psta)
++ psta = pattrib->psta;
++ else
++ {
++ DBG_871X("%s, call rtw_get_stainfo()\n", __func__);
++ psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra);
++ }
++
++ if(psta==NULL)
++ {
++ DBG_871X("%s, psta==NUL\n", __func__);
++ return;
++ }
++
++ if(!(psta->state &_FW_LINKED))
++ {
++ DBG_871X("%s, psta->state(0x%x) != _FW_LINKED\n", __func__, psta->state);
++ return;
++ }
++
++
++ phtpriv = &psta->htpriv;
++
++ if((phtpriv->ht_option==_TRUE) && (phtpriv->ampdu_enable==_TRUE))
++ {
++ issued = (phtpriv->agg_enable_bitmap>>priority)&0x1;
++ issued |= (phtpriv->candidate_tid_bitmap>>priority)&0x1;
++
++ if(0==issued)
++ {
++ DBG_871X("rtw_issue_addbareq_cmd, p=%d\n", priority);
++ psta->htpriv.candidate_tid_bitmap |= BIT((u8)priority);
++ rtw_addbareq_cmd(padapter,(u8) priority, pattrib->ra);
++ }
++ }
++
++}
++
++#endif
++
++#ifdef CONFIG_LAYER2_ROAMING
++inline void rtw_set_roaming(_adapter *adapter, u8 to_roaming)
++{
++ if (to_roaming == 0)
++ adapter->mlmepriv.to_join = _FALSE;
++ adapter->mlmepriv.to_roaming = to_roaming;
++}
++
++inline u8 rtw_to_roaming(_adapter *adapter)
++{
++ return adapter->mlmepriv.to_roaming;
++}
++
++void rtw_roaming(_adapter *padapter, struct wlan_network *tgt_network)
++{
++ _irqL irqL;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++
++ _enter_critical_bh(&pmlmepriv->lock, &irqL);
++ _rtw_roaming(padapter, tgt_network);
++ _exit_critical_bh(&pmlmepriv->lock, &irqL);
++}
++void _rtw_roaming(_adapter *padapter, struct wlan_network *tgt_network)
++{
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ int do_join_r;
++
++ struct wlan_network *pnetwork;
++
++ if(tgt_network != NULL)
++ pnetwork = tgt_network;
++ else
++ pnetwork = &pmlmepriv->cur_network;
++
++ if(0 < rtw_to_roaming(padapter)) {
++ DBG_871X("roaming from %s("MAC_FMT"), length:%d\n",
++ pnetwork->network.Ssid.Ssid, MAC_ARG(pnetwork->network.MacAddress),
++ pnetwork->network.Ssid.SsidLength);
++ _rtw_memcpy(&pmlmepriv->assoc_ssid, &pnetwork->network.Ssid, sizeof(NDIS_802_11_SSID));
++
++ pmlmepriv->assoc_by_bssid = _FALSE;
++
++ while(1) {
++ if( _SUCCESS==(do_join_r=rtw_do_join(padapter)) ) {
++ break;
++ } else {
++ DBG_871X("roaming do_join return %d\n", do_join_r);
++ pmlmepriv->to_roaming--;
++
++ if(0< rtw_to_roaming(padapter)) {
++ continue;
++ } else {
++ DBG_871X("%s(%d) -to roaming fail, indicate_disconnect\n", __FUNCTION__,__LINE__);
++ rtw_indicate_disconnect(padapter);
++ break;
++ }
++ }
++ }
++ }
++
++}
++#endif
++
++#ifdef CONFIG_CONCURRENT_MODE
++sint rtw_buddy_adapter_up(_adapter *padapter)
++{
++ sint res = _FALSE;
++
++ if(padapter == NULL)
++ return res;
++
++
++ if(padapter->pbuddy_adapter == NULL)
++ {
++ res = _FALSE;
++ }
++ else if( (padapter->pbuddy_adapter->bDriverStopped) || (padapter->pbuddy_adapter->bSurpriseRemoved) ||
++ (padapter->pbuddy_adapter->bup == _FALSE) || (padapter->pbuddy_adapter->hw_init_completed == _FALSE))
++ {
++ res = _FALSE;
++ }
++ else
++ {
++ res = _TRUE;
++ }
++
++ return res;
++
++}
++
++sint check_buddy_fwstate(_adapter *padapter, sint state)
++{
++ if(padapter == NULL)
++ return _FALSE;
++
++ if(padapter->pbuddy_adapter == NULL)
++ return _FALSE;
++
++ if ((state == WIFI_FW_NULL_STATE) &&
++ (padapter->pbuddy_adapter->mlmepriv.fw_state == WIFI_FW_NULL_STATE))
++ return _TRUE;
++
++ if (padapter->pbuddy_adapter->mlmepriv.fw_state & state)
++ return _TRUE;
++
++ return _FALSE;
++}
++#endif //CONFIG_CONCURRENT_MODE
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/core/rtw_mlme_ext.c linux-xbian-rpi/drivers/net/wireless/rtl8192cu/core/rtw_mlme_ext.c
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/core/rtw_mlme_ext.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/core/rtw_mlme_ext.c 2015-07-28 01:20:58.305654202 +0200
+@@ -0,0 +1,13599 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#define _RTW_MLME_EXT_C_
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++#include <wifi.h>
++#include <rtw_mlme_ext.h>
++#include <wlan_bssdef.h>
++#include <mlme_osdep.h>
++#include <recv_osdep.h>
++
++struct mlme_handler mlme_sta_tbl[]={
++ {WIFI_ASSOCREQ, "OnAssocReq", &OnAssocReq},
++ {WIFI_ASSOCRSP, "OnAssocRsp", &OnAssocRsp},
++ {WIFI_REASSOCREQ, "OnReAssocReq", &OnAssocReq},
++ {WIFI_REASSOCRSP, "OnReAssocRsp", &OnAssocRsp},
++ {WIFI_PROBEREQ, "OnProbeReq", &OnProbeReq},
++ {WIFI_PROBERSP, "OnProbeRsp", &OnProbeRsp},
++
++ /*----------------------------------------------------------
++ below 2 are reserved
++ -----------------------------------------------------------*/
++ {0, "DoReserved", &DoReserved},
++ {0, "DoReserved", &DoReserved},
++ {WIFI_BEACON, "OnBeacon", &OnBeacon},
++ {WIFI_ATIM, "OnATIM", &OnAtim},
++ {WIFI_DISASSOC, "OnDisassoc", &OnDisassoc},
++ {WIFI_AUTH, "OnAuth", &OnAuthClient},
++ {WIFI_DEAUTH, "OnDeAuth", &OnDeAuth},
++ {WIFI_ACTION, "OnAction", &OnAction},
++};
++
++#ifdef _CONFIG_NATIVEAP_MLME_
++struct mlme_handler mlme_ap_tbl[]={
++ {WIFI_ASSOCREQ, "OnAssocReq", &OnAssocReq},
++ {WIFI_ASSOCRSP, "OnAssocRsp", &OnAssocRsp},
++ {WIFI_REASSOCREQ, "OnReAssocReq", &OnAssocReq},
++ {WIFI_REASSOCRSP, "OnReAssocRsp", &OnAssocRsp},
++ {WIFI_PROBEREQ, "OnProbeReq", &OnProbeReq},
++ {WIFI_PROBERSP, "OnProbeRsp", &OnProbeRsp},
++
++ /*----------------------------------------------------------
++ below 2 are reserved
++ -----------------------------------------------------------*/
++ {0, "DoReserved", &DoReserved},
++ {0, "DoReserved", &DoReserved},
++ {WIFI_BEACON, "OnBeacon", &OnBeacon},
++ {WIFI_ATIM, "OnATIM", &OnAtim},
++ {WIFI_DISASSOC, "OnDisassoc", &OnDisassoc},
++ {WIFI_AUTH, "OnAuth", &OnAuth},
++ {WIFI_DEAUTH, "OnDeAuth", &OnDeAuth},
++ {WIFI_ACTION, "OnAction", &OnAction},
++};
++#endif
++
++struct action_handler OnAction_tbl[]={
++ {RTW_WLAN_CATEGORY_SPECTRUM_MGMT, "ACTION_SPECTRUM_MGMT", on_action_spct},
++ {RTW_WLAN_CATEGORY_QOS, "ACTION_QOS", &OnAction_qos},
++ {RTW_WLAN_CATEGORY_DLS, "ACTION_DLS", &OnAction_dls},
++ {RTW_WLAN_CATEGORY_BACK, "ACTION_BACK", &OnAction_back},
++ {RTW_WLAN_CATEGORY_PUBLIC, "ACTION_PUBLIC", on_action_public},
++ {RTW_WLAN_CATEGORY_RADIO_MEASUREMENT, "ACTION_RADIO_MEASUREMENT", &DoReserved},
++ {RTW_WLAN_CATEGORY_FT, "ACTION_FT", &DoReserved},
++ {RTW_WLAN_CATEGORY_HT, "ACTION_HT", &OnAction_ht},
++#ifdef CONFIG_IEEE80211W
++ {RTW_WLAN_CATEGORY_SA_QUERY, "ACTION_SA_QUERY", &OnAction_sa_query},
++#else
++ {RTW_WLAN_CATEGORY_SA_QUERY, "ACTION_SA_QUERY", &DoReserved},
++#endif //CONFIG_IEEE80211W
++ //add for CONFIG_IEEE80211W
++ {RTW_WLAN_CATEGORY_UNPROTECTED_WNM, "ACTION_UNPROTECTED_WNM", &DoReserved},
++ {RTW_WLAN_CATEGORY_SELF_PROTECTED, "ACTION_SELF_PROTECTED", &DoReserved},
++ {RTW_WLAN_CATEGORY_WMM, "ACTION_WMM", &OnAction_wmm},
++ {RTW_WLAN_CATEGORY_P2P, "ACTION_P2P", &OnAction_p2p},
++};
++
++
++u8 null_addr[ETH_ALEN]= {0,0,0,0,0,0};
++
++/**************************************************
++OUI definitions for the vendor specific IE
++***************************************************/
++unsigned char RTW_WPA_OUI[] = {0x00, 0x50, 0xf2, 0x01};
++unsigned char WMM_OUI[] = {0x00, 0x50, 0xf2, 0x02};
++unsigned char WPS_OUI[] = {0x00, 0x50, 0xf2, 0x04};
++unsigned char P2P_OUI[] = {0x50,0x6F,0x9A,0x09};
++unsigned char WFD_OUI[] = {0x50,0x6F,0x9A,0x0A};
++
++unsigned char WMM_INFO_OUI[] = {0x00, 0x50, 0xf2, 0x02, 0x00, 0x01};
++unsigned char WMM_PARA_OUI[] = {0x00, 0x50, 0xf2, 0x02, 0x01, 0x01};
++
++unsigned char WPA_TKIP_CIPHER[4] = {0x00, 0x50, 0xf2, 0x02};
++unsigned char RSN_TKIP_CIPHER[4] = {0x00, 0x0f, 0xac, 0x02};
++
++extern unsigned char REALTEK_96B_IE[];
++
++/********************************************************
++MCS rate definitions
++*********************************************************/
++#ifdef CONFIG_DISABLE_MCS13TO15
++unsigned char MCS_rate_2R_MCS13TO15_OFF[16] = {0xff, 0x1f, 0x0, 0x0, 0x01, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
++unsigned char MCS_rate_2R[16] = {0xff, 0xff, 0x0, 0x0, 0x01, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
++#else //CONFIG_DISABLE_MCS13TO15
++unsigned char MCS_rate_2R[16] = {0xff, 0xff, 0x0, 0x0, 0x01, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
++#endif //CONFIG_DISABLE_MCS13TO15
++unsigned char MCS_rate_1R[16] = {0xff, 0x00, 0x0, 0x0, 0x01, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
++
++/********************************************************
++ChannelPlan definitions
++*********************************************************/
++/*static RT_CHANNEL_PLAN DefaultChannelPlan[RT_CHANNEL_DOMAIN_MAX] = {
++ {{1,2,3,4,5,6,7,8,9,10,11,36,40,44,48,52,56,60,64,100,104,108,112,116,132,136,140,149,153,157,161,165},32}, // 0x00, RT_CHANNEL_DOMAIN_FCC
++ {{1,2,3,4,5,6,7,8,9,10,11,36,40,44,48,52,56,60,64,100,104,108,112,116,136,140,149,153,157,161,165},31}, // 0x01, RT_CHANNEL_DOMAIN_IC
++ {{1,2,3,4,5,6,7,8,9,10,11,12,13,36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140},32}, // 0x02, RT_CHANNEL_DOMAIN_ETSI
++ {{1,2,3,4,5,6,7,8,9,10,11,12,13},13}, // 0x03, RT_CHANNEL_DOMAIN_SPAIN
++ {{1,2,3,4,5,6,7,8,9,10,11,12,13},13}, // 0x04, RT_CHANNEL_DOMAIN_FRANCE
++ {{1,2,3,4,5,6,7,8,9,10,11,12,13},13}, // 0x05, RT_CHANNEL_DOMAIN_MKK
++ {{1,2,3,4,5,6,7,8,9,10,11,12,13},13}, // 0x06, RT_CHANNEL_DOMAIN_MKK1
++ {{1,2,3,4,5,6,7,8,9,10,11,12,13,36,40,44,48,52,56,60,64},21}, // 0x07, RT_CHANNEL_DOMAIN_ISRAEL
++ {{1,2,3,4,5,6,7,8,9,10,11,12,13,14,36,40,44,48,52,56,60,64},22}, // 0x08, RT_CHANNEL_DOMAIN_TELEC
++ {{1,2,3,4,5,6,7,8,9,10,11,12,13,14},14}, // 0x09, RT_CHANNEL_DOMAIN_GLOBAL_DOAMIN
++ {{1,2,3,4,5,6,7,8,9,10,11,12,13},13}, // 0x0A, RT_CHANNEL_DOMAIN_WORLD_WIDE_13
++ {{1,2,3,4,5,6,7,8,9,10,11,56,60,64,100,104,108,112,116,136,140,149,153,157,161,165},26}, // 0x0B, RT_CHANNEL_DOMAIN_TAIWAN
++ {{1,2,3,4,5,6,7,8,9,10,11,12,13,149,153,157,161,165},18}, // 0x0C, RT_CHANNEL_DOMAIN_CHINA
++ {{1,2,3,4,5,6,7,8,9,10,11,36,40,44,48,52,56,60,64,149,153,157,161,165},24}, // 0x0D, RT_CHANNEL_DOMAIN_SINGAPORE_INDIA_MEXICO
++ {{1,2,3,4,5,6,7,8,9,10,11,36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,149,153,157,161,165},31}, // 0x0E, RT_CHANNEL_DOMAIN_KOREA
++ {{1,2,3,4,5,6,7,8,9,10,11,36,40,44,48,52,56,60,64},19}, // 0x0F, RT_CHANNEL_DOMAIN_TURKEY
++ {{1,2,3,4,5,6,7,8,9,10,11,12,13,36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140},32}, // 0x10, RT_CHANNEL_DOMAIN_JAPAN
++ {{1,2,3,4,5,6,7,8,9,10,11,36,40,44,48,149,153,157,161,165},20}, // 0x11, RT_CHANNEL_DOMAIN_FCC_NO_DFS
++ {{1,2,3,4,5,6,7,8,9,10,11,12,13,36,40,44,48},17}, // 0x12, RT_CHANNEL_DOMAIN_JAPAN_NO_DFS
++ {{1,2,3,4,5,6,7,8,9,10,11,12,13,36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140,149,153,157,161,165},37}, // 0x13, RT_CHANNEL_DOMAIN_WORLD_WIDE_5G
++ {{1,2,3,4,5,6,7,8,9,10,11,56,60,64,149,153,157,161,165},19}, // 0x14, RT_CHANNEL_DOMAIN_TAIWAN_NO_DFS
++};*/
++
++static RT_CHANNEL_PLAN_2G RTW_ChannelPlan2G[RT_CHANNEL_DOMAIN_2G_MAX] = {
++ {{1,2,3,4,5,6,7,8,9,10,11,12,13},13}, // 0x00, RT_CHANNEL_DOMAIN_2G_WORLD , Passive scan CH 12, 13
++ {{1,2,3,4,5,6,7,8,9,10,11,12,13},13}, // 0x01, RT_CHANNEL_DOMAIN_2G_ETSI1
++ {{1,2,3,4,5,6,7,8,9,10,11},11}, // 0x02, RT_CHANNEL_DOMAIN_2G_FCC1
++ {{1,2,3,4,5,6,7,8,9,10,11,12,13,14},14}, // 0x03, RT_CHANNEL_DOMAIN_2G_MIKK1
++ {{10,11,12,13},4}, // 0x04, RT_CHANNEL_DOMAIN_2G_ETSI2
++ {{},0}, // 0x05, RT_CHANNEL_DOMAIN_2G_NULL
++};
++
++static RT_CHANNEL_PLAN_5G RTW_ChannelPlan5G[RT_CHANNEL_DOMAIN_5G_MAX] = {
++ {{},0}, // 0x00, RT_CHANNEL_DOMAIN_5G_NULL
++ {{36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140},19}, // 0x01, RT_CHANNEL_DOMAIN_5G_ETSI1
++ {{36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140,149,153,157,161,165},24}, // 0x02, RT_CHANNEL_DOMAIN_5G_ETSI2
++ {{36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,149,153,157,161,165},22}, // 0x03, RT_CHANNEL_DOMAIN_5G_ETSI3
++ {{36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140,149,153,157,161,165},24}, // 0x04, RT_CHANNEL_DOMAIN_5G_FCC1
++ {{36,40,44,48,149,153,157,161,165},9}, // 0x05, RT_CHANNEL_DOMAIN_5G_FCC2
++ {{36,40,44,48,52,56,60,64,149,153,157,161,165},13}, // 0x06, RT_CHANNEL_DOMAIN_5G_FCC3
++ {{36,40,44,48,52,56,60,64,149,153,157,161},12}, // 0x07, RT_CHANNEL_DOMAIN_5G_FCC4
++ {{149,153,157,161,165},5}, // 0x08, RT_CHANNEL_DOMAIN_5G_FCC5
++ {{36,40,44,48,52,56,60,64},8}, // 0x09, RT_CHANNEL_DOMAIN_5G_FCC6
++ {{36,40,44,48,52,56,60,64,100,104,108,112,116,136,140,149,153,157,161,165},20}, // 0x0A, RT_CHANNEL_DOMAIN_5G_FCC7_IC1
++ {{36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,149,153,157,161,165},20}, // 0x0B, RT_CHANNEL_DOMAIN_5G_KCC1
++ {{36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140},19}, // 0x0C, RT_CHANNEL_DOMAIN_5G_MKK1
++ {{36,40,44,48,52,56,60,64},8}, // 0x0D, RT_CHANNEL_DOMAIN_5G_MKK2
++ {{100,104,108,112,116,120,124,128,132,136,140},11}, // 0x0E, RT_CHANNEL_DOMAIN_5G_MKK3
++ {{56,60,64,100,104,108,112,116,136,140,149,153,157,161,165},15}, // 0x0F, RT_CHANNEL_DOMAIN_5G_NCC1
++ {{56,60,64,149,153,157,161,165},8}, // 0x10, RT_CHANNEL_DOMAIN_5G_NCC2
++
++ //===== Driver self defined for old channel plan Compatible ,Remember to modify if have new channel plan definition =====
++ {{36,40,44,48,52,56,60,64,100,104,108,112,116,132,136,140,149,153,157,161,165},21}, // 0x11, RT_CHANNEL_DOMAIN_5G_FCC
++ {{36,40,44,48},4}, // 0x12, RT_CHANNEL_DOMAIN_5G_JAPAN_NO_DFS
++ {{36,40,44,48,149,153,157,161},8}, // 0x13, RT_CHANNEL_DOMAIN_5G_FCC4_NO_DFS
++};
++
++static RT_CHANNEL_PLAN_MAP RTW_ChannelPlanMap[RT_CHANNEL_DOMAIN_MAX] = {
++ //===== 0x00 ~ 0x1F , Old Define =====
++ {0x02,0x11}, //0x00, RT_CHANNEL_DOMAIN_FCC
++ {0x02,0x0A}, //0x01, RT_CHANNEL_DOMAIN_IC
++ {0x01,0x01}, //0x02, RT_CHANNEL_DOMAIN_ETSI
++ {0x01,0x00}, //0x03, RT_CHANNEL_DOMAIN_SPAIN
++ {0x01,0x00}, //0x04, RT_CHANNEL_DOMAIN_FRANCE
++ {0x03,0x00}, //0x05, RT_CHANNEL_DOMAIN_MKK
++ {0x03,0x00}, //0x06, RT_CHANNEL_DOMAIN_MKK1
++ {0x01,0x09}, //0x07, RT_CHANNEL_DOMAIN_ISRAEL
++ {0x03,0x09}, //0x08, RT_CHANNEL_DOMAIN_TELEC
++ {0x03,0x00}, //0x09, RT_CHANNEL_DOMAIN_GLOBAL_DOAMIN
++ {0x00,0x00}, //0x0A, RT_CHANNEL_DOMAIN_WORLD_WIDE_13
++ {0x02,0x0F}, //0x0B, RT_CHANNEL_DOMAIN_TAIWAN
++ {0x01,0x08}, //0x0C, RT_CHANNEL_DOMAIN_CHINA
++ {0x02,0x06}, //0x0D, RT_CHANNEL_DOMAIN_SINGAPORE_INDIA_MEXICO
++ {0x02,0x0B}, //0x0E, RT_CHANNEL_DOMAIN_KOREA
++ {0x02,0x09}, //0x0F, RT_CHANNEL_DOMAIN_TURKEY
++ {0x01,0x01}, //0x10, RT_CHANNEL_DOMAIN_JAPAN
++ {0x02,0x05}, //0x11, RT_CHANNEL_DOMAIN_FCC_NO_DFS
++ {0x01,0x12}, //0x12, RT_CHANNEL_DOMAIN_JAPAN_NO_DFS
++ {0x00,0x04}, //0x13, RT_CHANNEL_DOMAIN_WORLD_WIDE_5G
++ {0x02,0x10}, //0x14, RT_CHANNEL_DOMAIN_TAIWAN_NO_DFS
++ {0x00,0x12}, //0x15, RT_CHANNEL_DOMAIN_ETSI_NO_DFS
++ {0x00,0x13}, //0x16, RT_CHANNEL_DOMAIN_KOREA_NO_DFS
++ {0x03,0x12}, //0x17, RT_CHANNEL_DOMAIN_JAPAN_NO_DFS
++ {0x05,0x08}, //0x18, RT_CHANNEL_DOMAIN_PAKISTAN_NO_DFS
++ {0x02,0x08}, //0x19, RT_CHANNEL_DOMAIN_TAIWAN2_NO_DFS
++ {0x00,0x00}, //0x1A,
++ {0x00,0x00}, //0x1B,
++ {0x00,0x00}, //0x1C,
++ {0x00,0x00}, //0x1D,
++ {0x00,0x00}, //0x1E,
++ {0x05,0x04}, //0x1F, RT_CHANNEL_DOMAIN_WORLD_WIDE_ONLY_5G
++ //===== 0x20 ~ 0x7F ,New Define =====
++ {0x00,0x00}, //0x20, RT_CHANNEL_DOMAIN_WORLD_NULL
++ {0x01,0x00}, //0x21, RT_CHANNEL_DOMAIN_ETSI1_NULL
++ {0x02,0x00}, //0x22, RT_CHANNEL_DOMAIN_FCC1_NULL
++ {0x03,0x00}, //0x23, RT_CHANNEL_DOMAIN_MKK1_NULL
++ {0x04,0x00}, //0x24, RT_CHANNEL_DOMAIN_ETSI2_NULL
++ {0x02,0x04}, //0x25, RT_CHANNEL_DOMAIN_FCC1_FCC1
++ {0x00,0x01}, //0x26, RT_CHANNEL_DOMAIN_WORLD_ETSI1
++ {0x03,0x0C}, //0x27, RT_CHANNEL_DOMAIN_MKK1_MKK1
++ {0x00,0x0B}, //0x28, RT_CHANNEL_DOMAIN_WORLD_KCC1
++ {0x00,0x05}, //0x29, RT_CHANNEL_DOMAIN_WORLD_FCC2
++ {0x00,0x00}, //0x2A,
++ {0x00,0x00}, //0x2B,
++ {0x00,0x00}, //0x2C,
++ {0x00,0x00}, //0x2D,
++ {0x00,0x00}, //0x2E,
++ {0x00,0x00}, //0x2F,
++ {0x00,0x06}, //0x30, RT_CHANNEL_DOMAIN_WORLD_FCC3
++ {0x00,0x07}, //0x31, RT_CHANNEL_DOMAIN_WORLD_FCC4
++ {0x00,0x08}, //0x32, RT_CHANNEL_DOMAIN_WORLD_FCC5
++ {0x00,0x09}, //0x33, RT_CHANNEL_DOMAIN_WORLD_FCC6
++ {0x02,0x0A}, //0x34, RT_CHANNEL_DOMAIN_FCC1_FCC7
++ {0x00,0x02}, //0x35, RT_CHANNEL_DOMAIN_WORLD_ETSI2
++ {0x00,0x03}, //0x36, RT_CHANNEL_DOMAIN_WORLD_ETSI3
++ {0x03,0x0D}, //0x37, RT_CHANNEL_DOMAIN_MKK1_MKK2
++ {0x03,0x0E}, //0x38, RT_CHANNEL_DOMAIN_MKK1_MKK3
++ {0x02,0x0F}, //0x39, RT_CHANNEL_DOMAIN_FCC1_NCC1
++ {0x00,0x00}, //0x3A,
++ {0x00,0x00}, //0x3B,
++ {0x00,0x00}, //0x3C,
++ {0x00,0x00}, //0x3D,
++ {0x00,0x00}, //0x3E,
++ {0x00,0x00}, //0x3F,
++ {0x02,0x10}, //0x40, RT_CHANNEL_DOMAIN_FCC1_NCC2
++};
++
++static RT_CHANNEL_PLAN_MAP RTW_CHANNEL_PLAN_MAP_REALTEK_DEFINE = {0x03,0x02}; //use the conbination for max channel numbers
++
++/*
++ * Search the @param ch in given @param ch_set
++ * @ch_set: the given channel set
++ * @ch: the given channel number
++ *
++ * return the index of channel_num in channel_set, -1 if not found
++ */
++int rtw_ch_set_search_ch(RT_CHANNEL_INFO *ch_set, const u32 ch)
++{
++ int i;
++ for(i=0;ch_set[i].ChannelNum!=0;i++){
++ if(ch == ch_set[i].ChannelNum)
++ break;
++ }
++
++ if(i >= ch_set[i].ChannelNum)
++ return -1;
++ return i;
++}
++
++/*
++ * Check the @param ch is fit with setband setting of @param adapter
++ * @adapter: the given adapter
++ * @ch: the given channel number
++ *
++ * return _TRUE when check valid, _FALSE not valid
++ */
++bool rtw_mlme_band_check(_adapter *adapter, const u32 ch)
++{
++ if (adapter->setband == GHZ24_50 /* 2.4G and 5G */
++ || (adapter->setband == GHZ_24 && ch < 35) /* 2.4G only */
++ || (adapter->setband == GHZ_50 && ch > 35) /* 5G only */
++ ) {
++ return _TRUE;
++ }
++ return _FALSE;
++}
++
++/****************************************************************************
++
++Following are the initialization functions for WiFi MLME
++
++*****************************************************************************/
++
++int init_hw_mlme_ext(_adapter *padapter)
++{
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++
++ //set_opmode_cmd(padapter, infra_client_with_mlme);//removed
++
++ set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode);
++
++ return _SUCCESS;
++}
++
++static void init_mlme_ext_priv_value(_adapter* padapter)
++{
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++
++ //unsigned char default_channel_set[MAX_CHANNEL_NUM] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 0, 0};
++ unsigned char mixed_datarate[NumRates] = {_1M_RATE_, _2M_RATE_, _5M_RATE_, _11M_RATE_, _6M_RATE_,_9M_RATE_, _12M_RATE_, _18M_RATE_, _24M_RATE_, _36M_RATE_, _48M_RATE_, _54M_RATE_, 0xff};
++ unsigned char mixed_basicrate[NumRates] ={_1M_RATE_, _2M_RATE_, _5M_RATE_, _11M_RATE_, _6M_RATE_, _12M_RATE_, _24M_RATE_, 0xff,};
++
++ ATOMIC_SET(&pmlmeext->event_seq, 0);
++ pmlmeext->mgnt_seq = 0;//reset to zero when disconnect at client mode
++#ifdef CONFIG_IEEE80211W
++ pmlmeext->sa_query_seq = 0;
++ pmlmeext->mgnt_80211w_IPN=0;
++ pmlmeext->mgnt_80211w_IPN_rx=0;
++#endif //CONFIG_IEEE80211W
++ pmlmeext->cur_channel = padapter->registrypriv.channel;
++ pmlmeext->cur_bwmode = HT_CHANNEL_WIDTH_20;
++ pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++
++ pmlmeext->retry = 0;
++
++ pmlmeext->cur_wireless_mode = padapter->registrypriv.wireless_mode;
++
++ //_rtw_memcpy(pmlmeext->channel_set, DefaultChannelPlan[padapter->mlmepriv.ChannelPlan].Channel, DefaultChannelPlan[padapter->mlmepriv.ChannelPlan].Len);
++ //_rtw_memcpy(pmlmeext->channel_set, default_channel_set, MAX_CHANNEL_NUM);
++ _rtw_memcpy(pmlmeext->datarate, mixed_datarate, NumRates);
++ _rtw_memcpy(pmlmeext->basicrate, mixed_basicrate, NumRates);
++
++ if(pmlmeext->cur_channel > 14)
++ pmlmeext->tx_rate = IEEE80211_OFDM_RATE_6MB;
++ else
++ pmlmeext->tx_rate = IEEE80211_CCK_RATE_1MB;
++
++ pmlmeext->sitesurvey_res.state = SCAN_DISABLE;
++ pmlmeext->sitesurvey_res.channel_idx = 0;
++ pmlmeext->sitesurvey_res.bss_cnt = 0;
++ pmlmeext->scan_abort = _FALSE;
++
++ pmlmeinfo->state = WIFI_FW_NULL_STATE;
++ pmlmeinfo->reauth_count = 0;
++ pmlmeinfo->reassoc_count = 0;
++ pmlmeinfo->link_count = 0;
++ pmlmeinfo->auth_seq = 0;
++ pmlmeinfo->auth_algo = dot11AuthAlgrthm_Open;
++ pmlmeinfo->key_index = 0;
++ pmlmeinfo->iv = 0;
++
++ pmlmeinfo->enc_algo = _NO_PRIVACY_;
++ pmlmeinfo->authModeToggle = 0;
++
++ _rtw_memset(pmlmeinfo->chg_txt, 0, 128);
++
++ pmlmeinfo->slotTime = SHORT_SLOT_TIME;
++ pmlmeinfo->preamble_mode = PREAMBLE_AUTO;
++
++ pmlmeinfo->dialogToken = 0;
++
++ pmlmeext->action_public_rxseq = 0xffff;
++ pmlmeext->action_public_dialog_token = 0xff;
++}
++
++static int has_channel(RT_CHANNEL_INFO *channel_set,
++ u8 chanset_size,
++ u8 chan) {
++ int i;
++
++ for (i = 0; i < chanset_size; i++) {
++ if (channel_set[i].ChannelNum == chan) {
++ return 1;
++ }
++ }
++
++ return 0;
++}
++
++static void init_channel_list(_adapter *padapter, RT_CHANNEL_INFO *channel_set,
++ u8 chanset_size,
++ struct p2p_channels *channel_list) {
++
++ struct p2p_oper_class_map op_class[] = {
++ { IEEE80211G, 81, 1, 13, 1, BW20 },
++ { IEEE80211G, 82, 14, 14, 1, BW20 },
++#if 0 /* Do not enable HT40 on 2 GHz */
++ { IEEE80211G, 83, 1, 9, 1, BW40PLUS },
++ { IEEE80211G, 84, 5, 13, 1, BW40MINUS },
++#endif
++ { IEEE80211A, 115, 36, 48, 4, BW20 },
++ { IEEE80211A, 116, 36, 44, 8, BW40PLUS },
++ { IEEE80211A, 117, 40, 48, 8, BW40MINUS },
++ { IEEE80211A, 124, 149, 161, 4, BW20 },
++ { IEEE80211A, 125, 149, 169, 4, BW20 },
++ { IEEE80211A, 126, 149, 157, 8, BW40PLUS },
++ { IEEE80211A, 127, 153, 161, 8, BW40MINUS },
++ { -1, 0, 0, 0, 0, BW20 }
++ };
++
++ int cla, op;
++
++ cla = 0;
++
++ for (op = 0; op_class[op].op_class; op++) {
++ u8 ch;
++ struct p2p_oper_class_map *o = &op_class[op];
++ struct p2p_reg_class *reg = NULL;
++
++ for (ch = o->min_chan; ch <= o->max_chan; ch += o->inc) {
++ if (!has_channel(channel_set, chanset_size, ch)) {
++ continue;
++ }
++
++ if ((0 == padapter->registrypriv.ht_enable) && (8 == o->inc))
++ continue;
++
++ if ((0 == (padapter->registrypriv.cbw40_enable & BIT(1))) &&
++ ((BW40MINUS == o->bw) || (BW40PLUS == o->bw)))
++ continue;
++
++ if (reg == NULL) {
++ reg = &channel_list->reg_class[cla];
++ cla++;
++ reg->reg_class = o->op_class;
++ reg->channels = 0;
++ }
++ reg->channel[reg->channels] = ch;
++ reg->channels++;
++ }
++ }
++ channel_list->reg_classes = cla;
++
++}
++
++static u8 init_channel_set(_adapter* padapter, u8 ChannelPlan, RT_CHANNEL_INFO *channel_set)
++{
++ u8 index,chanset_size = 0;
++ u8 b5GBand = _FALSE, b2_4GBand = _FALSE;
++ u8 Index2G = 0, Index5G=0;
++
++ _rtw_memset(channel_set, 0, sizeof(RT_CHANNEL_INFO)*MAX_CHANNEL_NUM);
++
++ if(ChannelPlan >= RT_CHANNEL_DOMAIN_MAX && ChannelPlan != RT_CHANNEL_DOMAIN_REALTEK_DEFINE)
++ {
++ DBG_871X("ChannelPlan ID %x error !!!!!\n",ChannelPlan);
++ return chanset_size;
++ }
++
++ if(padapter->registrypriv.wireless_mode & WIRELESS_11G)
++ {
++ b2_4GBand = _TRUE;
++ if(RT_CHANNEL_DOMAIN_REALTEK_DEFINE == ChannelPlan)
++ Index2G = RTW_CHANNEL_PLAN_MAP_REALTEK_DEFINE.Index2G;
++ else
++ Index2G = RTW_ChannelPlanMap[ChannelPlan].Index2G;
++ }
++
++ if(padapter->registrypriv.wireless_mode & WIRELESS_11A)
++ {
++ b5GBand = _TRUE;
++ if(RT_CHANNEL_DOMAIN_REALTEK_DEFINE == ChannelPlan)
++ Index5G = RTW_CHANNEL_PLAN_MAP_REALTEK_DEFINE.Index5G;
++ else
++ Index5G = RTW_ChannelPlanMap[ChannelPlan].Index5G;
++ }
++
++ if(b2_4GBand)
++ {
++ for(index=0;index<RTW_ChannelPlan2G[Index2G].Len;index++)
++ {
++ channel_set[chanset_size].ChannelNum = RTW_ChannelPlan2G[Index2G].Channel[index];
++
++ if(RT_CHANNEL_DOMAIN_GLOBAL_DOAMIN == ChannelPlan) //Channel 1~11 is active, and 12~14 is passive
++ {
++ if(channel_set[chanset_size].ChannelNum >= 1 && channel_set[chanset_size].ChannelNum <= 11)
++ channel_set[chanset_size].ScanType = SCAN_ACTIVE;
++ else if((channel_set[chanset_size].ChannelNum >= 12 && channel_set[chanset_size].ChannelNum <= 14))
++ channel_set[chanset_size].ScanType = SCAN_PASSIVE;
++ }
++ else if(RT_CHANNEL_DOMAIN_WORLD_WIDE_13 == ChannelPlan ||
++ RT_CHANNEL_DOMAIN_WORLD_WIDE_5G == ChannelPlan ||
++ RT_CHANNEL_DOMAIN_2G_WORLD == Index2G)// channel 12~13, passive scan
++ {
++ if(channel_set[chanset_size].ChannelNum <= 11)
++ channel_set[chanset_size].ScanType = SCAN_ACTIVE;
++ else
++ channel_set[chanset_size].ScanType = SCAN_PASSIVE;
++ }
++ else
++ {
++ channel_set[chanset_size].ScanType = SCAN_ACTIVE;
++ }
++
++ chanset_size++;
++ }
++ }
++
++ if(b5GBand)
++ {
++ for(index=0;index<RTW_ChannelPlan5G[Index5G].Len;index++)
++ {
++#ifdef CONFIG_DFS
++ channel_set[chanset_size].ChannelNum = RTW_ChannelPlan5G[Index5G].Channel[index];
++ if ( channel_set[chanset_size].ChannelNum <= 48
++ || channel_set[chanset_size].ChannelNum >= 149 )
++ {
++ if(RT_CHANNEL_DOMAIN_WORLD_WIDE_5G == ChannelPlan)//passive scan for all 5G channels
++ channel_set[chanset_size].ScanType = SCAN_PASSIVE;
++ else
++ channel_set[chanset_size].ScanType = SCAN_ACTIVE;
++ }
++ else
++ {
++ channel_set[chanset_size].ScanType = SCAN_PASSIVE;
++ }
++ chanset_size++;
++#else /* CONFIG_DFS */
++ if ( RTW_ChannelPlan5G[Index5G].Channel[index] <= 48
++ || RTW_ChannelPlan5G[Index5G].Channel[index] >= 149 ) {
++ channel_set[chanset_size].ChannelNum = RTW_ChannelPlan5G[Index5G].Channel[index];
++ if(RT_CHANNEL_DOMAIN_WORLD_WIDE_5G == ChannelPlan)//passive scan for all 5G channels
++ channel_set[chanset_size].ScanType = SCAN_PASSIVE;
++ else
++ channel_set[chanset_size].ScanType = SCAN_ACTIVE;
++ DBG_871X("%s(): channel_set[%d].ChannelNum = %d\n", __FUNCTION__, chanset_size, channel_set[chanset_size].ChannelNum);
++ chanset_size++;
++ }
++#endif /* CONFIG_DFS */
++ }
++ }
++
++ return chanset_size;
++}
++
++int init_mlme_ext_priv(_adapter* padapter)
++{
++ int res = _SUCCESS;
++ struct registry_priv* pregistrypriv = &padapter->registrypriv;
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++
++ // We don't need to memset padapter->XXX to zero, because adapter is allocated by rtw_zvmalloc().
++ //_rtw_memset((u8 *)pmlmeext, 0, sizeof(struct mlme_ext_priv));
++
++ pmlmeext->padapter = padapter;
++
++ //fill_fwpriv(padapter, &(pmlmeext->fwpriv));
++
++ init_mlme_ext_priv_value(padapter);
++ pmlmeinfo->bAcceptAddbaReq = pregistrypriv->bAcceptAddbaReq;
++
++ init_mlme_ext_timer(padapter);
++
++#ifdef CONFIG_AP_MODE
++ init_mlme_ap_info(padapter);
++#endif
++
++ pmlmeext->max_chan_nums = init_channel_set(padapter, pmlmepriv->ChannelPlan,pmlmeext->channel_set);
++ init_channel_list(padapter, pmlmeext->channel_set, pmlmeext->max_chan_nums, &pmlmeext->channel_list);
++
++ pmlmeext->chan_scan_time = SURVEY_TO;
++ pmlmeext->mlmeext_init = _TRUE;
++
++
++#ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK
++ pmlmeext->active_keep_alive_check = _TRUE;
++#endif
++
++ return res;
++
++}
++
++void free_mlme_ext_priv (struct mlme_ext_priv *pmlmeext)
++{
++ _adapter *padapter = pmlmeext->padapter;
++
++ if (!padapter)
++ return;
++
++ if (padapter->bDriverStopped == _TRUE)
++ {
++ _cancel_timer_ex(&pmlmeext->survey_timer);
++ _cancel_timer_ex(&pmlmeext->link_timer);
++ //_cancel_timer_ex(&pmlmeext->ADDBA_timer);
++ }
++}
++
++static u8 cmp_pkt_chnl_diff(_adapter *padapter,u8* pframe,uint packet_len)
++{ // if the channel is same, return 0. else return channel differential
++ uint len;
++ u8 channel;
++ u8 *p;
++ p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + _BEACON_IE_OFFSET_, _DSSET_IE_, &len, packet_len - _BEACON_IE_OFFSET_);
++ if (p)
++ {
++ channel = *(p + 2);
++ if(padapter->mlmeextpriv.cur_channel >= channel)
++ {
++ return (padapter->mlmeextpriv.cur_channel - channel);
++ }
++ else
++ {
++ return (channel-padapter->mlmeextpriv.cur_channel);
++ }
++ }
++ else
++ {
++ return 0;
++ }
++}
++
++static void _mgt_dispatcher(_adapter *padapter, struct mlme_handler *ptable, union recv_frame *precv_frame)
++{
++ u8 bc_addr[ETH_ALEN] = {0xff,0xff,0xff,0xff,0xff,0xff};
++ u8 *pframe = precv_frame->u.hdr.rx_data;
++
++ if(ptable->func)
++ {
++ //receive the frames that ra(a1) is my address or ra(a1) is bc address.
++ if (!_rtw_memcmp(GetAddr1Ptr(pframe), myid(&padapter->eeprompriv), ETH_ALEN) &&
++ !_rtw_memcmp(GetAddr1Ptr(pframe), bc_addr, ETH_ALEN))
++ {
++ return;
++ }
++
++ ptable->func(padapter, precv_frame);
++ }
++
++}
++
++void mgt_dispatcher(_adapter *padapter, union recv_frame *precv_frame)
++{
++ int index;
++ struct mlme_handler *ptable;
++#ifdef CONFIG_AP_MODE
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++#endif //CONFIG_AP_MODE
++ u8 bc_addr[ETH_ALEN] = {0xff,0xff,0xff,0xff,0xff,0xff};
++ u8 *pframe = precv_frame->u.hdr.rx_data;
++ struct sta_info *psta = rtw_get_stainfo(&padapter->stapriv, GetAddr2Ptr(pframe));
++
++ RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_,
++ ("+mgt_dispatcher: type(0x%x) subtype(0x%x)\n",
++ GetFrameType(pframe), GetFrameSubType(pframe)));
++
++#if 0
++ {
++ u8 *pbuf;
++ pbuf = GetAddr1Ptr(pframe);
++ DBG_871X("A1-%x:%x:%x:%x:%x:%x\n", *pbuf, *(pbuf+1), *(pbuf+2), *(pbuf+3), *(pbuf+4), *(pbuf+5));
++ pbuf = GetAddr2Ptr(pframe);
++ DBG_871X("A2-%x:%x:%x:%x:%x:%x\n", *pbuf, *(pbuf+1), *(pbuf+2), *(pbuf+3), *(pbuf+4), *(pbuf+5));
++ pbuf = GetAddr3Ptr(pframe);
++ DBG_871X("A3-%x:%x:%x:%x:%x:%x\n", *pbuf, *(pbuf+1), *(pbuf+2), *(pbuf+3), *(pbuf+4), *(pbuf+5));
++ }
++#endif
++
++ if (GetFrameType(pframe) != WIFI_MGT_TYPE)
++ {
++ RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("mgt_dispatcher: type(0x%x) error!\n", GetFrameType(pframe)));
++ return;
++ }
++
++ //receive the frames that ra(a1) is my address or ra(a1) is bc address.
++ if (!_rtw_memcmp(GetAddr1Ptr(pframe), myid(&padapter->eeprompriv), ETH_ALEN) &&
++ !_rtw_memcmp(GetAddr1Ptr(pframe), bc_addr, ETH_ALEN))
++ {
++ return;
++ }
++
++ ptable = mlme_sta_tbl;
++
++ index = GetFrameSubType(pframe) >> 4;
++
++#ifdef CONFIG_TDLS
++ if((index << 4)==WIFI_ACTION){
++ //category==RTW_WLAN_CATEGORY_PUBLIC, action==TDLS_DISCOVERY_RESPONSE
++ if(*(pframe + IEEE80211_MGMT_HDR_LEN ) == RTW_WLAN_CATEGORY_PUBLIC
++ && *(pframe + IEEE80211_MGMT_HDR_LEN + 1) == TDLS_DISCOVERY_RESPONSE )
++ {
++ DBG_871X("recv tdls discovery response frame\n");
++ On_TDLS_Dis_Rsp(padapter, precv_frame);
++ }
++ }
++#endif //CONFIG_TDLS
++
++ if (index > 13)
++ {
++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("Currently we do not support reserved sub-fr-type=%d\n", index));
++ return;
++ }
++ ptable += index;
++
++#if 1
++ if (psta != NULL)
++ {
++ if (GetRetry(pframe))
++ {
++ if (precv_frame->u.hdr.attrib.seq_num == psta->RxMgmtFrameSeqNum)
++ {
++ /* drop the duplicate management frame */
++ DBG_871X("Drop duplicate management frame with seq_num = %d.\n", precv_frame->u.hdr.attrib.seq_num);
++ return;
++ }
++ }
++ psta->RxMgmtFrameSeqNum = precv_frame->u.hdr.attrib.seq_num;
++ }
++#else
++
++ if(GetRetry(pframe))
++ {
++ //RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("drop due to decache!\n"));
++ //return;
++ }
++#endif
++
++#ifdef CONFIG_AP_MODE
++ switch (GetFrameSubType(pframe))
++ {
++ case WIFI_AUTH:
++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE)
++ ptable->func = &OnAuth;
++ else
++ ptable->func = &OnAuthClient;
++ //pass through
++ case WIFI_ASSOCREQ:
++ case WIFI_REASSOCREQ:
++ _mgt_dispatcher(padapter, ptable, precv_frame);
++#ifdef CONFIG_HOSTAPD_MLME
++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE)
++ rtw_hostapd_mlme_rx(padapter, precv_frame);
++#endif
++ break;
++ case WIFI_PROBEREQ:
++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE)
++ {
++#ifdef CONFIG_HOSTAPD_MLME
++ rtw_hostapd_mlme_rx(padapter, precv_frame);
++#else
++ _mgt_dispatcher(padapter, ptable, precv_frame);
++#endif
++ }
++ else
++ _mgt_dispatcher(padapter, ptable, precv_frame);
++ break;
++ case WIFI_BEACON:
++ _mgt_dispatcher(padapter, ptable, precv_frame);
++ break;
++ case WIFI_ACTION:
++ //if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE)
++ _mgt_dispatcher(padapter, ptable, precv_frame);
++ break;
++ default:
++ _mgt_dispatcher(padapter, ptable, precv_frame);
++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE)
++ rtw_hostapd_mlme_rx(padapter, precv_frame);
++ break;
++ }
++#else
++
++ _mgt_dispatcher(padapter, ptable, precv_frame);
++
++#endif
++
++}
++
++#ifdef CONFIG_P2P
++u32 p2p_listen_state_process(_adapter *padapter, unsigned char *da)
++{
++ bool response = _TRUE;
++
++#ifdef CONFIG_IOCTL_CFG80211
++ if( padapter->wdinfo.driver_interface == DRIVER_CFG80211 )
++ {
++ if (wdev_to_priv(padapter->rtw_wdev)->p2p_enabled == _FALSE
++ || padapter->mlmepriv.wps_probe_resp_ie == NULL
++ || padapter->mlmepriv.p2p_probe_resp_ie == NULL
++ )
++ {
++ DBG_871X("DON'T issue_probersp_p2p: p2p_enabled:%d, wps_probe_resp_ie:%p, p2p_probe_resp_ie:%p\n",
++ wdev_to_priv(padapter->rtw_wdev)->p2p_enabled,
++ padapter->mlmepriv.wps_probe_resp_ie,
++ padapter->mlmepriv.p2p_probe_resp_ie);
++ response = _FALSE;
++ }
++ }
++ else
++#endif //CONFIG_IOCTL_CFG80211
++ if( padapter->wdinfo.driver_interface == DRIVER_WEXT )
++ {
++ // do nothing if the device name is empty
++ if ( !padapter->wdinfo.device_name_len )
++ {
++ response = _FALSE;
++ }
++ }
++
++ if (response == _TRUE)
++ issue_probersp_p2p( padapter, da);
++
++ return _SUCCESS;
++}
++#endif //CONFIG_P2P
++
++
++/****************************************************************************
++
++Following are the callback functions for each subtype of the management frames
++
++*****************************************************************************/
++
++unsigned int OnProbeReq(_adapter *padapter, union recv_frame *precv_frame)
++{
++ unsigned int ielen;
++ unsigned char *p;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ WLAN_BSSID_EX *cur = &(pmlmeinfo->network);
++ u8 *pframe = precv_frame->u.hdr.rx_data;
++ uint len = precv_frame->u.hdr.len;
++ u8 is_valid_p2p_probereq = _FALSE;
++
++#ifdef CONFIG_P2P
++ struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
++ struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;
++ u8 wifi_test_chk_rate = 1;
++
++ if ( !rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) &&
++ !rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE) &&
++ !rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT) &&
++ !rtw_p2p_chk_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH) &&
++ !rtw_p2p_chk_state(pwdinfo, P2P_STATE_SCAN)
++ )
++ {
++ // Commented by Albert 2011/03/17
++ // mcs_rate = 0 -> CCK 1M rate
++ // mcs_rate = 1 -> CCK 2M rate
++ // mcs_rate = 2 -> CCK 5.5M rate
++ // mcs_rate = 3 -> CCK 11M rate
++ // In the P2P mode, the driver should not support the CCK rate
++
++ // Commented by Kurt 2012/10/16
++ // IOT issue: Google Nexus7 use 1M rate to send p2p_probe_req after GO nego completed and Nexus7 is client
++#ifdef CONFIG_WIFI_TEST
++ if ( pattrib->mcs_rate <= 3 )
++ {
++ wifi_test_chk_rate = 0;
++ }
++#endif //CONFIG_WIFI_TEST
++
++ if( wifi_test_chk_rate == 1 )
++ {
++ if((is_valid_p2p_probereq = process_probe_req_p2p_ie(pwdinfo, pframe, len)) == _TRUE)
++ {
++ if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE))
++ {
++ p2p_listen_state_process( padapter, get_sa(pframe));
++
++ return _SUCCESS;
++ }
++
++ if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO))
++ {
++ goto _continue;
++ }
++ }
++ }
++ }
++
++_continue:
++#endif //CONFIG_P2P
++
++ if(check_fwstate(pmlmepriv, WIFI_STATION_STATE))
++ {
++ return _SUCCESS;
++ }
++
++ if(check_fwstate(pmlmepriv, _FW_LINKED) == _FALSE &&
++ check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE|WIFI_AP_STATE)==_FALSE)
++ {
++ return _SUCCESS;
++ }
++
++
++ //DBG_871X("+OnProbeReq\n");
++
++#ifdef CONFIG_AUTO_AP_MODE
++ if(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE &&
++ pmlmepriv->cur_network.join_res == _TRUE)
++ {
++ _irqL irqL;
++ struct sta_info *psta;
++ u8 *mac_addr, *peer_addr;
++ struct sta_priv *pstapriv = &padapter->stapriv;
++ u8 RC_OUI[4]={0x00,0xE0,0x4C,0x0A};
++ //EID[1] + EID_LEN[1] + RC_OUI[4] + MAC[6] + PairingID[2] + ChannelNum[2]
++
++ p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + _PROBEREQ_IE_OFFSET_, _VENDOR_SPECIFIC_IE_, (int *)&ielen,
++ len - WLAN_HDR_A3_LEN - _PROBEREQ_IE_OFFSET_);
++
++ if(!p || ielen !=14)
++ goto _non_rc_device;
++
++ if(!_rtw_memcmp(p+2, RC_OUI, sizeof(RC_OUI)))
++ goto _non_rc_device;
++
++ if(!_rtw_memcmp(p+6, get_sa(pframe), ETH_ALEN))
++ {
++ DBG_871X("%s, do rc pairing ("MAC_FMT"), but mac addr mismatch!("MAC_FMT")\n", __FUNCTION__,
++ MAC_ARG(get_sa(pframe)), MAC_ARG(p+6));
++
++ goto _non_rc_device;
++ }
++
++ DBG_871X("%s, got the pairing device("MAC_FMT")\n", __FUNCTION__, MAC_ARG(get_sa(pframe)));
++
++ //new a station
++ psta = rtw_get_stainfo(pstapriv, get_sa(pframe));
++ if (psta == NULL)
++ {
++ // allocate a new one
++ DBG_871X("going to alloc stainfo for rc="MAC_FMT"\n", MAC_ARG(get_sa(pframe)));
++ psta = rtw_alloc_stainfo(pstapriv, get_sa(pframe));
++ if (psta == NULL)
++ {
++ //TODO:
++ DBG_871X(" Exceed the upper limit of supported clients...\n");
++ return _SUCCESS;
++ }
++
++ _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++ if (rtw_is_list_empty(&psta->asoc_list))
++ {
++ psta->expire_to = pstapriv->expire_to;
++ rtw_list_insert_tail(&psta->asoc_list, &pstapriv->asoc_list);
++ pstapriv->asoc_list_cnt++;
++ }
++ _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++
++ //generate pairing ID
++ mac_addr = myid(&(padapter->eeprompriv));
++ peer_addr = psta->hwaddr;
++ psta->pid = (u16)(((mac_addr[4]<<8) + mac_addr[5]) + ((peer_addr[4]<<8) + peer_addr[5]));
++
++ //update peer stainfo
++ psta->isrc = _TRUE;
++ //psta->aid = 0;
++ //psta->mac_id = 2;
++
++ /* get a unique AID */
++ if (psta->aid > 0) {
++ DBG_871X("old AID %d\n", psta->aid);
++ } else {
++ for (psta->aid = 1; psta->aid <= NUM_STA; psta->aid++)
++ if (pstapriv->sta_aid[psta->aid - 1] == NULL)
++ break;
++
++ if (psta->aid > pstapriv->max_num_sta) {
++ psta->aid = 0;
++ DBG_871X("no room for more AIDs\n");
++ return _SUCCESS;
++ } else {
++ pstapriv->sta_aid[psta->aid - 1] = psta;
++ DBG_871X("allocate new AID = (%d)\n", psta->aid);
++ }
++ }
++
++ psta->qos_option = 1;
++ psta->htpriv.ht_option = _TRUE;
++ psta->ieee8021x_blocked = _FALSE;
++ psta->htpriv.ampdu_enable = _FALSE;
++ psta->htpriv.sgi = _FALSE;
++ psta->htpriv.bwmode = HT_CHANNEL_WIDTH_20;
++ psta->htpriv.ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++
++ //rtw_hal_set_odm_var(padapter, HAL_ODM_STA_INFO, psta, _TRUE);
++
++ psta->htpriv.agg_enable_bitmap = 0x0;//reset
++ psta->htpriv.candidate_tid_bitmap = 0x0;//reset
++
++ _rtw_memset((void*)&psta->sta_stats, 0, sizeof(struct stainfo_stats));
++
++ _enter_critical_bh(&psta->lock, &irqL);
++ psta->state |= _FW_LINKED;
++ _exit_critical_bh(&psta->lock, &irqL);
++
++ report_add_sta_event(padapter, psta->hwaddr, psta->aid);
++
++ }
++
++ issue_probersp(padapter, get_sa(pframe), _FALSE);
++
++ return _SUCCESS;
++
++ }
++
++_non_rc_device:
++
++ return _SUCCESS;
++#endif //CONFIG_AUTO_AP_MODE
++
++
++#ifdef CONFIG_CONCURRENT_MODE
++ if(((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE) &&
++ check_buddy_fwstate(padapter, _FW_UNDER_LINKING|_FW_UNDER_SURVEY))
++ {
++ //don't process probe req
++ return _SUCCESS;
++ }
++#endif
++
++ p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + _PROBEREQ_IE_OFFSET_, _SSID_IE_, (int *)&ielen,
++ len - WLAN_HDR_A3_LEN - _PROBEREQ_IE_OFFSET_);
++
++
++ //check (wildcard) SSID
++ if (p != NULL)
++ {
++ if(is_valid_p2p_probereq == _TRUE)
++ {
++ goto _issue_probersp;
++ }
++
++ if ( (ielen != 0 && _FALSE ==_rtw_memcmp((void *)(p+2), (void *)cur->Ssid.Ssid, cur->Ssid.SsidLength))
++ || (ielen == 0 && pmlmeinfo->hidden_ssid_mode)
++ )
++ {
++ return _SUCCESS;
++ }
++
++_issue_probersp:
++
++ if(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE &&
++ pmlmepriv->cur_network.join_res == _TRUE)
++ {
++ //DBG_871X("+issue_probersp during ap mode\n");
++ issue_probersp(padapter, get_sa(pframe), is_valid_p2p_probereq);
++ }
++
++ }
++
++ return _SUCCESS;
++
++}
++
++unsigned int OnProbeRsp(_adapter *padapter, union recv_frame *precv_frame)
++{
++ struct sta_info *psta;
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ struct sta_priv *pstapriv = &padapter->stapriv;
++ u8 *pframe = precv_frame->u.hdr.rx_data;
++#ifdef CONFIG_P2P
++ struct wifidirect_info *pwdinfo = &padapter->wdinfo;
++#endif
++
++
++#ifdef CONFIG_P2P
++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_PROVISION_DIS_REQ))
++ {
++ if ( _TRUE == pwdinfo->tx_prov_disc_info.benable )
++ {
++ if( _rtw_memcmp( pwdinfo->tx_prov_disc_info.peerIFAddr, GetAddr2Ptr(pframe), ETH_ALEN ) )
++ {
++ if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT))
++ {
++ pwdinfo->tx_prov_disc_info.benable = _FALSE;
++ issue_p2p_provision_request( padapter,
++ pwdinfo->tx_prov_disc_info.ssid.Ssid,
++ pwdinfo->tx_prov_disc_info.ssid.SsidLength,
++ pwdinfo->tx_prov_disc_info.peerDevAddr );
++ }
++ else if ( rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE) || rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO) )
++ {
++ pwdinfo->tx_prov_disc_info.benable = _FALSE;
++ issue_p2p_provision_request( padapter,
++ NULL,
++ 0,
++ pwdinfo->tx_prov_disc_info.peerDevAddr );
++ }
++ }
++ }
++ return _SUCCESS;
++ }
++ else if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING))
++ {
++ if ( _TRUE == pwdinfo->nego_req_info.benable )
++ {
++ DBG_871X( "[%s] P2P State is GONEGO ING!\n", __FUNCTION__ );
++ if( _rtw_memcmp( pwdinfo->nego_req_info.peerDevAddr, GetAddr2Ptr(pframe), ETH_ALEN ) )
++ {
++ pwdinfo->nego_req_info.benable = _FALSE;
++ issue_p2p_GO_request( padapter, pwdinfo->nego_req_info.peerDevAddr);
++ }
++ }
++ }
++ else if( rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_INVITE_REQ ) )
++ {
++ if ( _TRUE == pwdinfo->invitereq_info.benable )
++ {
++ DBG_871X( "[%s] P2P_STATE_TX_INVITE_REQ!\n", __FUNCTION__ );
++ if( _rtw_memcmp( pwdinfo->invitereq_info.peer_macaddr, GetAddr2Ptr(pframe), ETH_ALEN ) )
++ {
++ pwdinfo->invitereq_info.benable = _FALSE;
++ issue_p2p_invitation_request( padapter, pwdinfo->invitereq_info.peer_macaddr );
++ }
++ }
++ }
++#endif
++
++
++ if (pmlmeext->sitesurvey_res.state == SCAN_PROCESS)
++ {
++ report_survey_event(padapter, precv_frame);
++#ifdef CONFIG_CONCURRENT_MODE
++ report_survey_event(padapter->pbuddy_adapter, precv_frame);
++#endif
++#ifdef CONFIG_DUALMAC_CONCURRENT
++ dc_report_survey_event(padapter, precv_frame);
++#endif
++ return _SUCCESS;
++ }
++
++ #if 0 //move to validate_recv_mgnt_frame
++ if (_rtw_memcmp(GetAddr3Ptr(pframe), get_my_bssid(&pmlmeinfo->network), ETH_ALEN))
++ {
++ if (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)
++ {
++ if ((psta = rtw_get_stainfo(pstapriv, GetAddr2Ptr(pframe))) != NULL)
++ {
++ psta->sta_stats.rx_mgnt_pkts++;
++ }
++ }
++ }
++ #endif
++
++ return _SUCCESS;
++
++}
++
++unsigned int OnBeacon(_adapter *padapter, union recv_frame *precv_frame)
++{
++ int cam_idx;
++ struct sta_info *psta;
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ struct sta_priv *pstapriv = &padapter->stapriv;
++ u8 *pframe = precv_frame->u.hdr.rx_data;
++ uint len = precv_frame->u.hdr.len;
++ u8 *p = NULL;
++ u32 ielen = 0;
++
++#ifdef CONFIG_ATTEMPT_TO_FIX_AP_BEACON_ERROR
++ p = rtw_get_ie(pframe + sizeof(struct rtw_ieee80211_hdr_3addr) + _BEACON_IE_OFFSET_, _EXT_SUPPORTEDRATES_IE_, &ielen, precv_frame->u.hdr.len -sizeof(struct rtw_ieee80211_hdr_3addr) - _BEACON_IE_OFFSET_);
++ if ((p != NULL) && (ielen > 0))
++ {
++ if ((*(p + 1 + ielen) == 0x2D) && (*(p + 2 + ielen) != 0x2D))
++ {
++ /* Invalid value 0x2D is detected in Extended Supported Rates (ESR) IE. Try to fix the IE length to avoid failed Beacon parsing. */
++ DBG_871X("[WIFIDBG] Error in ESR IE is detected in Beacon of BSSID:"MAC_FMT". Fix the length of ESR IE to avoid failed Beacon parsing.\n", MAC_ARG(GetAddr3Ptr(pframe)));
++ *(p + 1) = ielen - 1;
++ }
++ }
++#endif
++
++ if (pmlmeext->sitesurvey_res.state == SCAN_PROCESS)
++ {
++ report_survey_event(padapter, precv_frame);
++#ifdef CONFIG_CONCURRENT_MODE
++ report_survey_event(padapter->pbuddy_adapter, precv_frame);
++#endif
++
++#ifdef CONFIG_DUALMAC_CONCURRENT
++ dc_report_survey_event(padapter, precv_frame);
++#endif
++
++ return _SUCCESS;
++ }
++
++ if (_rtw_memcmp(GetAddr3Ptr(pframe), get_my_bssid(&pmlmeinfo->network), ETH_ALEN))
++ {
++ if (pmlmeinfo->state & WIFI_FW_AUTH_NULL)
++ {
++ //check the vendor of the assoc AP
++ pmlmeinfo->assoc_AP_vendor = check_assoc_AP(pframe+sizeof(struct rtw_ieee80211_hdr_3addr), len-sizeof(struct rtw_ieee80211_hdr_3addr));
++#ifdef CONFIG_P2P_PS
++ // do P2P PS Before link ? , ToDo
++ //process_p2p_ps_ie(padapter, (pframe + WLAN_HDR_A3_LEN), (len - WLAN_HDR_A3_LEN));
++#endif // CONFIG_P2P_PS
++
++ //update TSF Value
++ update_TSF(pmlmeext, pframe, len);
++
++ //start auth
++ start_clnt_auth(padapter);
++
++ return _SUCCESS;
++ }
++
++ if(((pmlmeinfo->state&0x03) == WIFI_FW_STATION_STATE) && (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS))
++ {
++ if ((psta = rtw_get_stainfo(pstapriv, GetAddr2Ptr(pframe))) != NULL)
++ {
++ #ifdef CONFIG_PATCH_JOIN_WRONG_CHANNEL
++ //Merge from 8712 FW code
++ if (cmp_pkt_chnl_diff(padapter,pframe,len) != 0)
++ { // join wrong channel, deauth and reconnect
++ issue_deauth(padapter, (&(pmlmeinfo->network))->MacAddress, WLAN_REASON_DEAUTH_LEAVING);
++
++ report_del_sta_event(padapter,(&(pmlmeinfo->network))->MacAddress, WLAN_REASON_JOIN_WRONG_CHANNEL);
++ pmlmeinfo->state &= (~WIFI_FW_ASSOC_SUCCESS);
++ return _SUCCESS;
++ }
++ #endif //CONFIG_PATCH_JOIN_WRONG_CHANNEL
++
++ //update WMM, ERP in the beacon
++ //todo: the timer is used instead of the number of the beacon received
++ if ((sta_rx_pkts(psta) & 0xf) == 0)
++ {
++ //DBG_871X("update_bcn_info\n");
++ update_beacon_info(padapter, pframe, len, psta);
++ }
++
++#ifdef CONFIG_DFS
++ process_csa_ie(padapter, pframe, len); //channel switch announcement
++#endif //CONFIG_DFS
++
++#ifdef CONFIG_P2P_PS
++ //if(psta->ieee8021x_blocked == _FALSE) // do not allow P2P PS during EAPOL handshake ?
++ process_p2p_ps_ie(padapter, (pframe + WLAN_HDR_A3_LEN), (len - WLAN_HDR_A3_LEN));
++#endif //CONFIG_P2P_PS
++
++ #if 0 //move to validate_recv_mgnt_frame
++ psta->sta_stats.rx_mgnt_pkts++;
++ #endif
++ }
++ }
++ else if((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE)
++ {
++ if ((psta = rtw_get_stainfo(pstapriv, GetAddr2Ptr(pframe))) != NULL)
++ {
++ //update WMM, ERP in the beacon
++ //todo: the timer is used instead of the number of the beacon received
++ if ((sta_rx_pkts(psta) & 0xf) == 0)
++ {
++ //DBG_871X("update_bcn_info\n");
++ update_beacon_info(padapter, pframe, len, psta);
++ }
++
++ #if 0 //move to validate_recv_mgnt_frame
++ psta->sta_stats.rx_mgnt_pkts++;
++ #endif
++ }
++ else
++ {
++ //allocate a new CAM entry for IBSS station
++ if ((cam_idx = allocate_fw_sta_entry(padapter)) == NUM_STA)
++ {
++ goto _END_ONBEACON_;
++ }
++
++ //get supported rate
++ if (update_sta_support_rate(padapter, (pframe + WLAN_HDR_A3_LEN + _BEACON_IE_OFFSET_), (len - WLAN_HDR_A3_LEN - _BEACON_IE_OFFSET_), cam_idx) == _FAIL)
++ {
++ pmlmeinfo->FW_sta_info[cam_idx].status = 0;
++ goto _END_ONBEACON_;
++ }
++
++ //update TSF Value
++ update_TSF(pmlmeext, pframe, len);
++
++ //report sta add event
++ report_add_sta_event(padapter, GetAddr2Ptr(pframe), cam_idx);
++ }
++ }
++ }
++
++_END_ONBEACON_:
++
++ return _SUCCESS;
++
++}
++
++unsigned int OnAuth(_adapter *padapter, union recv_frame *precv_frame)
++{
++#ifdef CONFIG_AP_MODE
++ _irqL irqL;
++ unsigned int auth_mode, seq, ie_len;
++ unsigned char *sa, *p;
++ u16 algorithm;
++ int status;
++ static struct sta_info stat;
++ struct sta_info *pstat=NULL;
++ struct sta_priv *pstapriv = &padapter->stapriv;
++ struct security_priv *psecuritypriv = &padapter->securitypriv;
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ u8 *pframe = precv_frame->u.hdr.rx_data;
++ uint len = precv_frame->u.hdr.len;
++
++
++#ifdef CONFIG_CONCURRENT_MODE
++ if(((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE) &&
++ check_buddy_fwstate(padapter, _FW_UNDER_LINKING|_FW_UNDER_SURVEY))
++ {
++ //don't process auth request;
++ return _SUCCESS;
++ }
++#endif //CONFIG_CONCURRENT_MODE
++
++ if((pmlmeinfo->state&0x03) != WIFI_FW_AP_STATE)
++ return _FAIL;
++
++ DBG_871X("+OnAuth\n");
++
++ sa = GetAddr2Ptr(pframe);
++
++ auth_mode = psecuritypriv->dot11AuthAlgrthm;
++ seq = cpu_to_le16(*(u16*)((SIZE_PTR)pframe + WLAN_HDR_A3_LEN + 2));
++ algorithm = cpu_to_le16(*(u16*)((SIZE_PTR)pframe + WLAN_HDR_A3_LEN));
++
++ if (GetPrivacy(pframe))
++ {
++#if 0 //TODO: SW rtw_wep_decrypt
++ if (SWCRYPTO)
++ {
++ status = rtw_wep_decrypt(priv, pframe, pfrinfo->pktlen,
++ priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm);
++ if (status == FALSE)
++ {
++ SAVE_INT_AND_CLI(flags);
++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,"wep-decrypt a Auth frame error!\n");
++ status = _STATS_CHALLENGE_FAIL_;
++ goto auth_fail;
++ }
++ }
++
++ seq = cpu_to_le16(*(unsigned short *)((unsigned int)pframe + WLAN_HDR_A3_LEN + 4 + 2));
++ algorithm = cpu_to_le16(*(unsigned short *)((unsigned int)pframe + WLAN_HDR_A3_LEN + 4));
++#endif
++ }
++
++
++ DBG_871X("auth alg=%x, seq=%X\n", algorithm, seq);
++
++ if (auth_mode == 2 &&
++ psecuritypriv->dot11PrivacyAlgrthm != _WEP40_ &&
++ psecuritypriv->dot11PrivacyAlgrthm != _WEP104_)
++ auth_mode = 0;
++
++ if ((algorithm > 0 && auth_mode == 0) || // rx a shared-key auth but shared not enabled
++ (algorithm == 0 && auth_mode == 1) ) // rx a open-system auth but shared-key is enabled
++ {
++ DBG_871X("auth rejected due to bad alg [alg=%d, auth_mib=%d] %02X%02X%02X%02X%02X%02X\n",
++ algorithm, auth_mode, sa[0], sa[1], sa[2], sa[3], sa[4], sa[5]);
++
++ status = _STATS_NO_SUPP_ALG_;
++
++ goto auth_fail;
++ }
++
++#if 0 //ACL control
++ phead = &priv->wlan_acl_list;
++ plist = phead->next;
++ //check sa
++ if (acl_mode == 1) // 1: positive check, only those on acl_list can be connected.
++ res = FAIL;
++ else
++ res = SUCCESS;
++
++ while(plist != phead)
++ {
++ paclnode = list_entry(plist, struct rtw_wlan_acl_node, list);
++ plist = plist->next;
++ if (!memcmp((void *)sa, paclnode->addr, 6)) {
++ if (paclnode->mode & 2) { // deny
++ res = FAIL;
++ break;
++ }
++ else {
++ res = SUCCESS;
++ break;
++ }
++ }
++ }
++
++ if (res != SUCCESS) {
++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,"auth abort because ACL!\n");
++ return FAIL;
++ }
++#else
++ if(rtw_access_ctrl(padapter, sa) == _FALSE)
++ {
++ status = _STATS_UNABLE_HANDLE_STA_;
++ goto auth_fail;
++ }
++#endif
++
++ pstat = rtw_get_stainfo(pstapriv, sa);
++ if (pstat == NULL)
++ {
++ // allocate a new one
++ DBG_871X("going to alloc stainfo for sa="MAC_FMT"\n", MAC_ARG(sa));
++ pstat = rtw_alloc_stainfo(pstapriv, sa);
++ if (pstat == NULL)
++ {
++ DBG_871X(" Exceed the upper limit of supported clients...\n");
++ status = _STATS_UNABLE_HANDLE_STA_;
++ goto auth_fail;
++ }
++
++ pstat->state = WIFI_FW_AUTH_NULL;
++ pstat->auth_seq = 0;
++
++ //pstat->flags = 0;
++ //pstat->capability = 0;
++ }
++ else
++ {
++ _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++ if(rtw_is_list_empty(&pstat->asoc_list)==_FALSE)
++ {
++ rtw_list_delete(&pstat->asoc_list);
++ pstapriv->asoc_list_cnt--;
++ if (pstat->expire_to > 0)
++ {
++ //TODO: STA re_auth within expire_to
++ }
++ }
++ _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++
++ if (seq==1) {
++ //TODO: STA re_auth and auth timeout
++ }
++ }
++
++ _enter_critical_bh(&pstapriv->auth_list_lock, &irqL);
++ if (rtw_is_list_empty(&pstat->auth_list))
++ {
++ rtw_list_insert_tail(&pstat->auth_list, &pstapriv->auth_list);
++ pstapriv->auth_list_cnt++;
++ }
++ _exit_critical_bh(&pstapriv->auth_list_lock, &irqL);
++
++ if (pstat->auth_seq == 0)
++ pstat->expire_to = pstapriv->auth_to;
++
++ if ((pstat->auth_seq + 1) != seq)
++ {
++ DBG_871X("(1)auth rejected because out of seq [rx_seq=%d, exp_seq=%d]!\n",
++ seq, pstat->auth_seq+1);
++ status = _STATS_OUT_OF_AUTH_SEQ_;
++ goto auth_fail;
++ }
++
++ if (algorithm==0 && (auth_mode == 0 || auth_mode == 2))
++ {
++ if (seq == 1)
++ {
++ pstat->state &= ~WIFI_FW_AUTH_NULL;
++ pstat->state |= WIFI_FW_AUTH_SUCCESS;
++ pstat->expire_to = pstapriv->assoc_to;
++ pstat->authalg = algorithm;
++ }
++ else
++ {
++ DBG_871X("(2)auth rejected because out of seq [rx_seq=%d, exp_seq=%d]!\n",
++ seq, pstat->auth_seq+1);
++ status = _STATS_OUT_OF_AUTH_SEQ_;
++ goto auth_fail;
++ }
++ }
++ else // shared system or auto authentication
++ {
++ if (seq == 1)
++ {
++ //prepare for the challenging txt...
++
++ //get_random_bytes((void *)pstat->chg_txt, 128);//TODO:
++
++ pstat->state &= ~WIFI_FW_AUTH_NULL;
++ pstat->state |= WIFI_FW_AUTH_STATE;
++ pstat->authalg = algorithm;
++ pstat->auth_seq = 2;
++ }
++ else if (seq == 3)
++ {
++ //checking for challenging txt...
++ DBG_871X("checking for challenging txt...\n");
++
++ p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + 4 + _AUTH_IE_OFFSET_ , _CHLGETXT_IE_, (int *)&ie_len,
++ len - WLAN_HDR_A3_LEN - _AUTH_IE_OFFSET_ - 4);
++
++ if((p==NULL) || (ie_len<=0))
++ {
++ DBG_871X("auth rejected because challenge failure!(1)\n");
++ status = _STATS_CHALLENGE_FAIL_;
++ goto auth_fail;
++ }
++
++ if (_rtw_memcmp((void *)(p + 2), pstat->chg_txt, 128))
++ {
++ pstat->state &= (~WIFI_FW_AUTH_STATE);
++ pstat->state |= WIFI_FW_AUTH_SUCCESS;
++ // challenging txt is correct...
++ pstat->expire_to = pstapriv->assoc_to;
++ }
++ else
++ {
++ DBG_871X("auth rejected because challenge failure!\n");
++ status = _STATS_CHALLENGE_FAIL_;
++ goto auth_fail;
++ }
++ }
++ else
++ {
++ DBG_871X("(3)auth rejected because out of seq [rx_seq=%d, exp_seq=%d]!\n",
++ seq, pstat->auth_seq+1);
++ status = _STATS_OUT_OF_AUTH_SEQ_;
++ goto auth_fail;
++ }
++ }
++
++
++ // Now, we are going to issue_auth...
++ pstat->auth_seq = seq + 1;
++
++#ifdef CONFIG_NATIVEAP_MLME
++ issue_auth(padapter, pstat, (unsigned short)(_STATS_SUCCESSFUL_));
++#endif
++
++ if (pstat->state & WIFI_FW_AUTH_SUCCESS)
++ pstat->auth_seq = 0;
++
++
++ return _SUCCESS;
++
++auth_fail:
++
++ if(pstat)
++ rtw_free_stainfo(padapter , pstat);
++
++ pstat = &stat;
++ _rtw_memset((char *)pstat, '\0', sizeof(stat));
++ pstat->auth_seq = 2;
++ _rtw_memcpy(pstat->hwaddr, sa, 6);
++
++#ifdef CONFIG_NATIVEAP_MLME
++ issue_auth(padapter, pstat, (unsigned short)status);
++#endif
++
++#endif
++ return _FAIL;
++
++}
++
++unsigned int OnAuthClient(_adapter *padapter, union recv_frame *precv_frame)
++{
++ unsigned int seq, len, status, algthm, offset;
++ unsigned char *p;
++ unsigned int go2asoc = 0;
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ u8 *pframe = precv_frame->u.hdr.rx_data;
++ uint pkt_len = precv_frame->u.hdr.len;
++
++ DBG_871X("%s\n", __FUNCTION__);
++
++ //check A1 matches or not
++ if (!_rtw_memcmp(myid(&(padapter->eeprompriv)), get_da(pframe), ETH_ALEN))
++ return _SUCCESS;
++
++ if (!(pmlmeinfo->state & WIFI_FW_AUTH_STATE))
++ return _SUCCESS;
++
++ offset = (GetPrivacy(pframe))? 4: 0;
++
++ algthm = le16_to_cpu(*(unsigned short *)((SIZE_PTR)pframe + WLAN_HDR_A3_LEN + offset));
++ seq = le16_to_cpu(*(unsigned short *)((SIZE_PTR)pframe + WLAN_HDR_A3_LEN + offset + 2));
++ status = le16_to_cpu(*(unsigned short *)((SIZE_PTR)pframe + WLAN_HDR_A3_LEN + offset + 4));
++
++ if (status != 0)
++ {
++ DBG_871X("clnt auth fail, status: %d\n", status);
++ if(status == 13)//&& pmlmeinfo->auth_algo == dot11AuthAlgrthm_Auto)
++ {
++ if(pmlmeinfo->auth_algo == dot11AuthAlgrthm_Shared)
++ pmlmeinfo->auth_algo = dot11AuthAlgrthm_Open;
++ else
++ pmlmeinfo->auth_algo = dot11AuthAlgrthm_Shared;
++ //pmlmeinfo->reauth_count = 0;
++ }
++
++ set_link_timer(pmlmeext, 1);
++ goto authclnt_fail;
++ }
++
++ if (seq == 2)
++ {
++ if (pmlmeinfo->auth_algo == dot11AuthAlgrthm_Shared)
++ {
++ // legendary shared system
++ p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + _AUTH_IE_OFFSET_, _CHLGETXT_IE_, (int *)&len,
++ pkt_len - WLAN_HDR_A3_LEN - _AUTH_IE_OFFSET_);
++
++ if (p == NULL)
++ {
++ //DBG_871X("marc: no challenge text?\n");
++ goto authclnt_fail;
++ }
++
++ _rtw_memcpy((void *)(pmlmeinfo->chg_txt), (void *)(p + 2), len);
++ pmlmeinfo->auth_seq = 3;
++ issue_auth(padapter, NULL, 0);
++ set_link_timer(pmlmeext, REAUTH_TO);
++
++ return _SUCCESS;
++ }
++ else
++ {
++ // open system
++ go2asoc = 1;
++ }
++ }
++ else if (seq == 4)
++ {
++ if (pmlmeinfo->auth_algo == dot11AuthAlgrthm_Shared)
++ {
++ go2asoc = 1;
++ }
++ else
++ {
++ goto authclnt_fail;
++ }
++ }
++ else
++ {
++ // this is also illegal
++ //DBG_871X("marc: clnt auth failed due to illegal seq=%x\n", seq);
++ goto authclnt_fail;
++ }
++
++ if (go2asoc)
++ {
++ start_clnt_assoc(padapter);
++ return _SUCCESS;
++ }
++
++authclnt_fail:
++
++ //pmlmeinfo->state &= ~(WIFI_FW_AUTH_STATE);
++
++ return _FAIL;
++
++}
++
++unsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame)
++{
++#ifdef CONFIG_AP_MODE
++ _irqL irqL;
++ u16 capab_info, listen_interval;
++ struct rtw_ieee802_11_elems elems;
++ struct sta_info *pstat;
++ unsigned char reassoc, *p, *pos, *wpa_ie;
++ unsigned char WMM_IE[] = {0x00, 0x50, 0xf2, 0x02, 0x00, 0x01};
++ int i, ie_len, wpa_ie_len, left;
++ unsigned char supportRate[16];
++ int supportRateNum;
++ unsigned short status = _STATS_SUCCESSFUL_;
++ unsigned short frame_type, ie_offset=0;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct security_priv *psecuritypriv = &padapter->securitypriv;
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ WLAN_BSSID_EX *cur = &(pmlmeinfo->network);
++ struct sta_priv *pstapriv = &padapter->stapriv;
++ u8 *pframe = precv_frame->u.hdr.rx_data;
++ uint pkt_len = precv_frame->u.hdr.len;
++#ifdef CONFIG_P2P
++ struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
++ u8 p2p_status_code = P2P_STATUS_SUCCESS;
++ u8 *p2pie;
++ u32 p2pielen = 0;
++#ifdef CONFIG_WFD
++ u8 wfd_ie[ 128 ] = { 0x00 };
++ u32 wfd_ielen = 0;
++#endif // CONFIG_WFD
++#endif //CONFIG_P2P
++
++#ifdef CONFIG_CONCURRENT_MODE
++ if(((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE) &&
++ check_buddy_fwstate(padapter, _FW_UNDER_LINKING|_FW_UNDER_SURVEY))
++ {
++ //don't process assoc request;
++ return _SUCCESS;
++ }
++#endif //CONFIG_CONCURRENT_MODE
++
++ if((pmlmeinfo->state&0x03) != WIFI_FW_AP_STATE)
++ return _FAIL;
++
++ frame_type = GetFrameSubType(pframe);
++ if (frame_type == WIFI_ASSOCREQ)
++ {
++ reassoc = 0;
++ ie_offset = _ASOCREQ_IE_OFFSET_;
++ }
++ else // WIFI_REASSOCREQ
++ {
++ reassoc = 1;
++ ie_offset = _REASOCREQ_IE_OFFSET_;
++ }
++
++
++ if (pkt_len < IEEE80211_3ADDR_LEN + ie_offset) {
++ DBG_871X("handle_assoc(reassoc=%d) - too short payload (len=%lu)"
++ "\n", reassoc, (unsigned long)pkt_len);
++ return _FAIL;
++ }
++
++ pstat = rtw_get_stainfo(pstapriv, GetAddr2Ptr(pframe));
++ if (pstat == (struct sta_info *)NULL)
++ {
++ status = _RSON_CLS2_;
++ goto asoc_class2_error;
++ }
++
++ capab_info = RTW_GET_LE16(pframe + WLAN_HDR_A3_LEN);
++ //capab_info = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN));
++ //listen_interval = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN+2));
++ listen_interval = RTW_GET_LE16(pframe + WLAN_HDR_A3_LEN+2);
++
++ left = pkt_len - (IEEE80211_3ADDR_LEN + ie_offset);
++ pos = pframe + (IEEE80211_3ADDR_LEN + ie_offset);
++
++
++ DBG_871X("%s\n", __FUNCTION__);
++
++ // check if this stat has been successfully authenticated/assocated
++ if (!((pstat->state) & WIFI_FW_AUTH_SUCCESS))
++ {
++ if (!((pstat->state) & WIFI_FW_ASSOC_SUCCESS))
++ {
++ status = _RSON_CLS2_;
++ goto asoc_class2_error;
++ }
++ else
++ {
++ pstat->state &= (~WIFI_FW_ASSOC_SUCCESS);
++ pstat->state |= WIFI_FW_ASSOC_STATE;
++ }
++ }
++ else
++ {
++ pstat->state &= (~WIFI_FW_AUTH_SUCCESS);
++ pstat->state |= WIFI_FW_ASSOC_STATE;
++ }
++
++
++#if 0// todo:tkip_countermeasures
++ if (hapd->tkip_countermeasures) {
++ resp = WLAN_REASON_MICHAEL_MIC_FAILURE;
++ goto fail;
++ }
++#endif
++
++ pstat->capability = capab_info;
++
++#if 0//todo:
++ //check listen_interval
++ if (listen_interval > hapd->conf->max_listen_interval) {
++ hostapd_logger(hapd, mgmt->sa, HOSTAPD_MODULE_IEEE80211,
++ HOSTAPD_LEVEL_DEBUG,
++ "Too large Listen Interval (%d)",
++ listen_interval);
++ resp = WLAN_STATUS_ASSOC_DENIED_LISTEN_INT_TOO_LARGE;
++ goto fail;
++ }
++
++ pstat->listen_interval = listen_interval;
++#endif
++
++ //now parse all ieee802_11 ie to point to elems
++ if (rtw_ieee802_11_parse_elems(pos, left, &elems, 1) == ParseFailed ||
++ !elems.ssid) {
++ DBG_871X("STA " MAC_FMT " sent invalid association request\n",
++ MAC_ARG(pstat->hwaddr));
++ status = _STATS_FAILURE_;
++ goto OnAssocReqFail;
++ }
++
++
++ // now we should check all the fields...
++ // checking SSID
++ p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + ie_offset, _SSID_IE_, &ie_len,
++ pkt_len - WLAN_HDR_A3_LEN - ie_offset);
++ if (p == NULL)
++ {
++ status = _STATS_FAILURE_;
++ }
++
++ if (ie_len == 0) // broadcast ssid, however it is not allowed in assocreq
++ status = _STATS_FAILURE_;
++ else
++ {
++ // check if ssid match
++ if (!_rtw_memcmp((void *)(p+2), cur->Ssid.Ssid, cur->Ssid.SsidLength))
++ status = _STATS_FAILURE_;
++
++ if (ie_len != cur->Ssid.SsidLength)
++ status = _STATS_FAILURE_;
++ }
++
++ if(_STATS_SUCCESSFUL_ != status)
++ goto OnAssocReqFail;
++
++ // check if the supported rate is ok
++ p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + ie_offset, _SUPPORTEDRATES_IE_, &ie_len, pkt_len - WLAN_HDR_A3_LEN - ie_offset);
++ if (p == NULL) {
++ DBG_871X("Rx a sta assoc-req which supported rate is empty!\n");
++ // use our own rate set as statoin used
++ //_rtw_memcpy(supportRate, AP_BSSRATE, AP_BSSRATE_LEN);
++ //supportRateNum = AP_BSSRATE_LEN;
++
++ status = _STATS_FAILURE_;
++ goto OnAssocReqFail;
++ }
++ else {
++ _rtw_memcpy(supportRate, p+2, ie_len);
++ supportRateNum = ie_len;
++
++ p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + ie_offset, _EXT_SUPPORTEDRATES_IE_ , &ie_len,
++ pkt_len - WLAN_HDR_A3_LEN - ie_offset);
++ if (p != NULL) {
++
++ if(supportRateNum<=sizeof(supportRate))
++ {
++ _rtw_memcpy(supportRate+supportRateNum, p+2, ie_len);
++ supportRateNum += ie_len;
++ }
++ }
++ }
++
++ //todo: mask supportRate between AP & STA -> move to update raid
++ //get_matched_rate(pmlmeext, supportRate, &supportRateNum, 0);
++
++ //update station supportRate
++ pstat->bssratelen = supportRateNum;
++ _rtw_memcpy(pstat->bssrateset, supportRate, supportRateNum);
++
++
++ //check RSN/WPA/WPS
++ pstat->dot8021xalg = 0;
++ pstat->wpa_psk = 0;
++ pstat->wpa_group_cipher = 0;
++ pstat->wpa2_group_cipher = 0;
++ pstat->wpa_pairwise_cipher = 0;
++ pstat->wpa2_pairwise_cipher = 0;
++ _rtw_memset(pstat->wpa_ie, 0, sizeof(pstat->wpa_ie));
++ if((psecuritypriv->wpa_psk & BIT(1)) && elems.rsn_ie) {
++
++ int group_cipher=0, pairwise_cipher=0;
++
++ wpa_ie = elems.rsn_ie;
++ wpa_ie_len = elems.rsn_ie_len;
++
++ if(rtw_parse_wpa2_ie(wpa_ie-2, wpa_ie_len+2, &group_cipher, &pairwise_cipher) == _SUCCESS)
++ {
++ pstat->dot8021xalg = 1;//psk, todo:802.1x
++ pstat->wpa_psk |= BIT(1);
++
++ pstat->wpa2_group_cipher = group_cipher&psecuritypriv->wpa2_group_cipher;
++ pstat->wpa2_pairwise_cipher = pairwise_cipher&psecuritypriv->wpa2_pairwise_cipher;
++
++ if(!pstat->wpa2_group_cipher)
++ status = WLAN_STATUS_GROUP_CIPHER_NOT_VALID;
++
++ if(!pstat->wpa2_pairwise_cipher)
++ status = WLAN_STATUS_PAIRWISE_CIPHER_NOT_VALID;
++ }
++ else
++ {
++ status = WLAN_STATUS_INVALID_IE;
++ }
++
++ } else if ((psecuritypriv->wpa_psk & BIT(0)) && elems.wpa_ie) {
++
++ int group_cipher=0, pairwise_cipher=0;
++
++ wpa_ie = elems.wpa_ie;
++ wpa_ie_len = elems.wpa_ie_len;
++
++ if(rtw_parse_wpa_ie(wpa_ie-2, wpa_ie_len+2, &group_cipher, &pairwise_cipher) == _SUCCESS)
++ {
++ pstat->dot8021xalg = 1;//psk, todo:802.1x
++ pstat->wpa_psk |= BIT(0);
++
++ pstat->wpa_group_cipher = group_cipher&psecuritypriv->wpa_group_cipher;
++ pstat->wpa_pairwise_cipher = pairwise_cipher&psecuritypriv->wpa_pairwise_cipher;
++
++ if(!pstat->wpa_group_cipher)
++ status = WLAN_STATUS_GROUP_CIPHER_NOT_VALID;
++
++ if(!pstat->wpa_pairwise_cipher)
++ status = WLAN_STATUS_PAIRWISE_CIPHER_NOT_VALID;
++
++ }
++ else
++ {
++ status = WLAN_STATUS_INVALID_IE;
++ }
++
++ } else {
++ wpa_ie = NULL;
++ wpa_ie_len = 0;
++ }
++
++ if(_STATS_SUCCESSFUL_ != status)
++ goto OnAssocReqFail;
++
++ pstat->flags &= ~(WLAN_STA_WPS | WLAN_STA_MAYBE_WPS);
++ //if (hapd->conf->wps_state && wpa_ie == NULL) { //todo: to check ap if supporting WPS
++ if(wpa_ie == NULL) {
++ if (elems.wps_ie) {
++ DBG_871X("STA included WPS IE in "
++ "(Re)Association Request - assume WPS is "
++ "used\n");
++ pstat->flags |= WLAN_STA_WPS;
++ //wpabuf_free(sta->wps_ie);
++ //sta->wps_ie = wpabuf_alloc_copy(elems.wps_ie + 4,
++ // elems.wps_ie_len - 4);
++ } else {
++ DBG_871X("STA did not include WPA/RSN IE "
++ "in (Re)Association Request - possible WPS "
++ "use\n");
++ pstat->flags |= WLAN_STA_MAYBE_WPS;
++ }
++
++
++ // AP support WPA/RSN, and sta is going to do WPS, but AP is not ready
++ // that the selected registrar of AP is _FLASE
++ if((psecuritypriv->wpa_psk >0)
++ && (pstat->flags & (WLAN_STA_WPS|WLAN_STA_MAYBE_WPS)))
++ {
++ if(pmlmepriv->wps_beacon_ie)
++ {
++ u8 selected_registrar = 0;
++
++ rtw_get_wps_attr_content(pmlmepriv->wps_beacon_ie, pmlmepriv->wps_beacon_ie_len, WPS_ATTR_SELECTED_REGISTRAR , &selected_registrar, NULL);
++
++ if(!selected_registrar)
++ {
++ DBG_871X("selected_registrar is _FALSE , or AP is not ready to do WPS\n");
++
++ status = _STATS_UNABLE_HANDLE_STA_;
++
++ goto OnAssocReqFail;
++ }
++ }
++ }
++
++ }
++ else
++ {
++ int copy_len;
++
++ if(psecuritypriv->wpa_psk == 0)
++ {
++ DBG_871X("STA " MAC_FMT ": WPA/RSN IE in association "
++ "request, but AP don't support WPA/RSN\n", MAC_ARG(pstat->hwaddr));
++
++ status = WLAN_STATUS_INVALID_IE;
++
++ goto OnAssocReqFail;
++
++ }
++
++ if (elems.wps_ie) {
++ DBG_871X("STA included WPS IE in "
++ "(Re)Association Request - WPS is "
++ "used\n");
++ pstat->flags |= WLAN_STA_WPS;
++ copy_len=0;
++ }
++ else
++ {
++ copy_len = ((wpa_ie_len+2) > sizeof(pstat->wpa_ie)) ? (sizeof(pstat->wpa_ie)):(wpa_ie_len+2);
++ }
++
++
++ if(copy_len>0)
++ _rtw_memcpy(pstat->wpa_ie, wpa_ie-2, copy_len);
++
++ }
++
++
++ // check if there is WMM IE & support WWM-PS
++ pstat->flags &= ~WLAN_STA_WME;
++ pstat->qos_option = 0;
++ pstat->qos_info = 0;
++ pstat->has_legacy_ac = _TRUE;
++ pstat->uapsd_vo = 0;
++ pstat->uapsd_vi = 0;
++ pstat->uapsd_be = 0;
++ pstat->uapsd_bk = 0;
++ if (pmlmepriv->qospriv.qos_option)
++ {
++ p = pframe + WLAN_HDR_A3_LEN + ie_offset; ie_len = 0;
++ for (;;)
++ {
++ p = rtw_get_ie(p, _VENDOR_SPECIFIC_IE_, &ie_len, pkt_len - WLAN_HDR_A3_LEN - ie_offset);
++ if (p != NULL) {
++ if (_rtw_memcmp(p+2, WMM_IE, 6)) {
++
++ pstat->flags |= WLAN_STA_WME;
++
++ pstat->qos_option = 1;
++ pstat->qos_info = *(p+8);
++
++ pstat->max_sp_len = (pstat->qos_info>>5)&0x3;
++
++ if((pstat->qos_info&0xf) !=0xf)
++ pstat->has_legacy_ac = _TRUE;
++ else
++ pstat->has_legacy_ac = _FALSE;
++
++ if(pstat->qos_info&0xf)
++ {
++ if(pstat->qos_info&BIT(0))
++ pstat->uapsd_vo = BIT(0)|BIT(1);
++ else
++ pstat->uapsd_vo = 0;
++
++ if(pstat->qos_info&BIT(1))
++ pstat->uapsd_vi = BIT(0)|BIT(1);
++ else
++ pstat->uapsd_vi = 0;
++
++ if(pstat->qos_info&BIT(2))
++ pstat->uapsd_bk = BIT(0)|BIT(1);
++ else
++ pstat->uapsd_bk = 0;
++
++ if(pstat->qos_info&BIT(3))
++ pstat->uapsd_be = BIT(0)|BIT(1);
++ else
++ pstat->uapsd_be = 0;
++
++ }
++
++ break;
++ }
++ }
++ else {
++ break;
++ }
++ p = p + ie_len + 2;
++ }
++ }
++
++
++#ifdef CONFIG_80211N_HT
++ /* save HT capabilities in the sta object */
++ _rtw_memset(&pstat->htpriv.ht_cap, 0, sizeof(struct rtw_ieee80211_ht_cap));
++ if (elems.ht_capabilities && elems.ht_capabilities_len >= sizeof(struct rtw_ieee80211_ht_cap))
++ {
++ pstat->flags |= WLAN_STA_HT;
++
++ pstat->flags |= WLAN_STA_WME;
++
++ _rtw_memcpy(&pstat->htpriv.ht_cap, elems.ht_capabilities, sizeof(struct rtw_ieee80211_ht_cap));
++
++ } else
++ pstat->flags &= ~WLAN_STA_HT;
++
++
++ if((pmlmepriv->htpriv.ht_option == _FALSE) && (pstat->flags&WLAN_STA_HT))
++ {
++ status = _STATS_FAILURE_;
++ goto OnAssocReqFail;
++ }
++
++
++ if ((pstat->flags & WLAN_STA_HT) &&
++ ((pstat->wpa2_pairwise_cipher&WPA_CIPHER_TKIP) ||
++ (pstat->wpa_pairwise_cipher&WPA_CIPHER_TKIP)))
++ {
++ DBG_871X("HT: " MAC_FMT " tried to "
++ "use TKIP with HT association\n", MAC_ARG(pstat->hwaddr));
++
++ //status = WLAN_STATUS_CIPHER_REJECTED_PER_POLICY;
++ //goto OnAssocReqFail;
++ }
++#endif /* CONFIG_80211N_HT */
++
++ //
++ //if (hapd->iface->current_mode->mode == HOSTAPD_MODE_IEEE80211G)//?
++ pstat->flags |= WLAN_STA_NONERP;
++ for (i = 0; i < pstat->bssratelen; i++) {
++ if ((pstat->bssrateset[i] & 0x7f) > 22) {
++ pstat->flags &= ~WLAN_STA_NONERP;
++ break;
++ }
++ }
++
++ if (pstat->capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
++ pstat->flags |= WLAN_STA_SHORT_PREAMBLE;
++ else
++ pstat->flags &= ~WLAN_STA_SHORT_PREAMBLE;
++
++
++
++ if (status != _STATS_SUCCESSFUL_)
++ goto OnAssocReqFail;
++
++#ifdef CONFIG_P2P
++ pstat->is_p2p_device = _FALSE;
++ if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO))
++ {
++ if( (p2pie=rtw_get_p2p_ie(pframe + WLAN_HDR_A3_LEN + ie_offset , pkt_len - WLAN_HDR_A3_LEN - ie_offset , NULL, &p2pielen)))
++ {
++ pstat->is_p2p_device = _TRUE;
++ if((p2p_status_code=(u8)process_assoc_req_p2p_ie(pwdinfo, pframe, pkt_len, pstat))>0)
++ {
++ pstat->p2p_status_code = p2p_status_code;
++ status = _STATS_CAP_FAIL_;
++ goto OnAssocReqFail;
++ }
++ }
++#ifdef CONFIG_WFD
++ if(rtw_get_wfd_ie(pframe + WLAN_HDR_A3_LEN + ie_offset , pkt_len - WLAN_HDR_A3_LEN - ie_offset , wfd_ie, &wfd_ielen ))
++ {
++ u8 attr_content[ 10 ] = { 0x00 };
++ u32 attr_contentlen = 0;
++
++ DBG_8192C( "[%s] WFD IE Found!!\n", __FUNCTION__ );
++ rtw_get_wfd_attr_content( wfd_ie, wfd_ielen, WFD_ATTR_DEVICE_INFO, attr_content, &attr_contentlen);
++ if ( attr_contentlen )
++ {
++ pwdinfo->wfd_info->peer_rtsp_ctrlport = RTW_GET_BE16( attr_content + 2 );
++ DBG_8192C( "[%s] Peer PORT NUM = %d\n", __FUNCTION__, pwdinfo->wfd_info->peer_rtsp_ctrlport );
++ }
++ }
++#endif
++ }
++ pstat->p2p_status_code = p2p_status_code;
++#endif //CONFIG_P2P
++
++ //TODO: identify_proprietary_vendor_ie();
++ // Realtek proprietary IE
++ // identify if this is Broadcom sta
++ // identify if this is ralink sta
++ // Customer proprietary IE
++
++
++
++ /* get a unique AID */
++ if (pstat->aid > 0) {
++ DBG_871X(" old AID %d\n", pstat->aid);
++ } else {
++ for (pstat->aid = 1; pstat->aid <= NUM_STA; pstat->aid++)
++ if (pstapriv->sta_aid[pstat->aid - 1] == NULL)
++ break;
++
++ //if (pstat->aid > NUM_STA) {
++ if (pstat->aid > pstapriv->max_num_sta) {
++
++ pstat->aid = 0;
++
++ DBG_871X(" no room for more AIDs\n");
++
++ status = WLAN_STATUS_AP_UNABLE_TO_HANDLE_NEW_STA;
++
++ goto OnAssocReqFail;
++
++
++ } else {
++ pstapriv->sta_aid[pstat->aid - 1] = pstat;
++ DBG_871X("allocate new AID = (%d)\n", pstat->aid);
++ }
++ }
++
++
++ pstat->state &= (~WIFI_FW_ASSOC_STATE);
++ pstat->state |= WIFI_FW_ASSOC_SUCCESS;
++
++ _enter_critical_bh(&pstapriv->auth_list_lock, &irqL);
++ if (!rtw_is_list_empty(&pstat->auth_list))
++ {
++ rtw_list_delete(&pstat->auth_list);
++ pstapriv->auth_list_cnt--;
++ }
++ _exit_critical_bh(&pstapriv->auth_list_lock, &irqL);
++
++ _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++ if (rtw_is_list_empty(&pstat->asoc_list))
++ {
++ pstat->expire_to = pstapriv->expire_to;
++ rtw_list_insert_tail(&pstat->asoc_list, &pstapriv->asoc_list);
++ pstapriv->asoc_list_cnt++;
++ }
++ _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++
++ // now the station is qualified to join our BSS...
++ if(pstat && (pstat->state & WIFI_FW_ASSOC_SUCCESS) && (_STATS_SUCCESSFUL_==status))
++ {
++#ifdef CONFIG_NATIVEAP_MLME
++ //.1 bss_cap_update & sta_info_update
++ bss_cap_update_on_sta_join(padapter, pstat);
++ sta_info_update(padapter, pstat);
++
++ //issue assoc rsp before notify station join event.
++ if (frame_type == WIFI_ASSOCREQ)
++ issue_asocrsp(padapter, status, pstat, WIFI_ASSOCRSP);
++ else
++ issue_asocrsp(padapter, status, pstat, WIFI_REASSOCRSP);
++
++ //.2 - report to upper layer
++ DBG_871X("indicate_sta_join_event to upper layer - hostapd\n");
++
++#ifdef CONFIG_IOCTL_CFG80211
++ #ifdef COMPAT_KERNEL_RELEASE
++ rtw_cfg80211_indicate_sta_assoc(padapter, pframe, pkt_len);
++ #elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER)
++ rtw_cfg80211_indicate_sta_assoc(padapter, pframe, pkt_len);
++ #else //(LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER)
++ _enter_critical_bh(&pstat->lock, &irqL);
++ if(pstat->passoc_req)
++ {
++ rtw_mfree(pstat->passoc_req, pstat->assoc_req_len);
++ pstat->passoc_req = NULL;
++ pstat->assoc_req_len = 0;
++ }
++
++ pstat->passoc_req = rtw_zmalloc(pkt_len);
++ if(pstat->passoc_req)
++ {
++ _rtw_memcpy(pstat->passoc_req, pframe, pkt_len);
++ pstat->assoc_req_len = pkt_len;
++ }
++ _exit_critical_bh(&pstat->lock, &irqL);
++ #endif //(LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER)
++#else
++ rtw_indicate_sta_assoc_event(padapter, pstat);
++#endif //CONFIG_IOCTL_CFG80211
++
++ //.3-(1) report sta add event
++ report_add_sta_event(padapter, pstat->hwaddr, pstat->aid);
++
++/*
++ //issue assoc rsp before notify station join event.
++ if (frame_type == WIFI_ASSOCREQ)
++ issue_asocrsp(padapter, status, pstat, WIFI_ASSOCRSP);
++ else
++ issue_asocrsp(padapter, status, pstat, WIFI_REASSOCRSP);
++*/
++
++#endif
++ }
++
++ return _SUCCESS;
++
++asoc_class2_error:
++
++#ifdef CONFIG_NATIVEAP_MLME
++ issue_deauth(padapter, (void *)GetAddr2Ptr(pframe), status);
++#endif
++
++ return _FAIL;
++
++OnAssocReqFail:
++
++
++#ifdef CONFIG_NATIVEAP_MLME
++ pstat->aid = 0;
++ if (frame_type == WIFI_ASSOCREQ)
++ issue_asocrsp(padapter, status, pstat, WIFI_ASSOCRSP);
++ else
++ issue_asocrsp(padapter, status, pstat, WIFI_REASSOCRSP);
++#endif
++
++
++#endif /* CONFIG_AP_MODE */
++
++ return _FAIL;
++
++}
++
++unsigned int OnAssocRsp(_adapter *padapter, union recv_frame *precv_frame)
++{
++ uint i;
++ int res;
++ unsigned short status;
++ PNDIS_802_11_VARIABLE_IEs pIE;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ //WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network);
++ u8 *pframe = precv_frame->u.hdr.rx_data;
++ uint pkt_len = precv_frame->u.hdr.len;
++
++ DBG_871X("%s\n", __FUNCTION__);
++
++ //check A1 matches or not
++ if (!_rtw_memcmp(myid(&(padapter->eeprompriv)), get_da(pframe), ETH_ALEN))
++ return _SUCCESS;
++
++ if (!(pmlmeinfo->state & (WIFI_FW_AUTH_SUCCESS | WIFI_FW_ASSOC_STATE)))
++ return _SUCCESS;
++
++ if (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)
++ return _SUCCESS;
++
++ _cancel_timer_ex(&pmlmeext->link_timer);
++
++ //status
++ if ((status = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN + 2))) > 0)
++ {
++ DBG_871X("assoc reject, status code: %d\n", status);
++ pmlmeinfo->state = WIFI_FW_NULL_STATE;
++ res = -4;
++ goto report_assoc_result;
++ }
++
++ //get capabilities
++ pmlmeinfo->capability = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN));
++
++ //set slot time
++ pmlmeinfo->slotTime = (pmlmeinfo->capability & BIT(10))? 9: 20;
++
++ //AID
++ res = pmlmeinfo->aid = (int)(le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN + 4))&0x3fff);
++
++ //following are moved to join event callback function
++ //to handle HT, WMM, rate adaptive, update MAC reg
++ //for not to handle the synchronous IO in the tasklet
++ for (i = (6 + WLAN_HDR_A3_LEN); i < pkt_len;)
++ {
++ pIE = (PNDIS_802_11_VARIABLE_IEs)(pframe + i);
++
++ switch (pIE->ElementID)
++ {
++ case _VENDOR_SPECIFIC_IE_:
++ if (_rtw_memcmp(pIE->data, WMM_PARA_OUI, 6)) //WMM
++ {
++ WMM_param_handler(padapter, pIE);
++ }
++#if defined(CONFIG_P2P) && defined(CONFIG_WFD)
++ else if ( _rtw_memcmp(pIE->data, WFD_OUI, 4)) //WFD
++ {
++ DBG_871X( "[%s] Found WFD IE\n", __FUNCTION__ );
++ WFD_info_handler( padapter, pIE );
++ }
++#endif
++ break;
++
++ case _HT_CAPABILITY_IE_: //HT caps
++ HT_caps_handler(padapter, pIE);
++ break;
++
++ case _HT_EXTRA_INFO_IE_: //HT info
++ HT_info_handler(padapter, pIE);
++ break;
++
++ case _ERPINFO_IE_:
++ ERP_IE_handler(padapter, pIE);
++
++ default:
++ break;
++ }
++
++ i += (pIE->Length + 2);
++ }
++
++ pmlmeinfo->state &= (~WIFI_FW_ASSOC_STATE);
++ pmlmeinfo->state |= WIFI_FW_ASSOC_SUCCESS;
++
++ //Update Basic Rate Table for spec, 2010-12-28 , by thomas
++ UpdateBrateTbl(padapter, pmlmeinfo->network.SupportedRates);
++
++#ifdef CONFIG_IOCTL_CFG80211
++ if (!rtw_cfg80211_check_bss(padapter)) {
++ DBG_871X("rtw_cfg80211_check_bss() : BSS not found !!\n");
++ res = -2;
++ goto report_assoc_result;
++ }
++#endif
++
++report_assoc_result:
++ if (res > 0) {
++ rtw_buf_update(&pmlmepriv->assoc_rsp, &pmlmepriv->assoc_rsp_len, pframe, pkt_len);
++ } else {
++ rtw_buf_free(&pmlmepriv->assoc_rsp, &pmlmepriv->assoc_rsp_len);
++ }
++
++ report_join_res(padapter, res);
++ return _SUCCESS;
++}
++
++unsigned int OnDeAuth(_adapter *padapter, union recv_frame *precv_frame)
++{
++ unsigned short reason;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ u8 *pframe = precv_frame->u.hdr.rx_data;
++#ifdef CONFIG_P2P
++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo);
++#endif //CONFIG_P2P
++
++ //check A3
++ if (!(_rtw_memcmp(GetAddr3Ptr(pframe), get_my_bssid(&pmlmeinfo->network), ETH_ALEN)))
++ return _SUCCESS;
++
++#ifdef CONFIG_P2P
++ if ( pwdinfo->rx_invitereq_info.scan_op_ch_only )
++ {
++ _cancel_timer_ex( &pwdinfo->reset_ch_sitesurvey );
++ _set_timer( &pwdinfo->reset_ch_sitesurvey, 10 );
++ }
++#endif //CONFIG_P2P
++
++ reason = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN));
++
++ DBG_871X("%s Reason code(%d)\n", __FUNCTION__,reason);
++
++#ifdef CONFIG_AP_MODE
++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE)
++ {
++ _irqL irqL;
++ struct sta_info *psta;
++ struct sta_priv *pstapriv = &padapter->stapriv;
++
++ //_enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL);
++ //rtw_free_stainfo(padapter, psta);
++ //_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);
++
++ DBG_871X("%s, STA:" MAC_FMT "\n", __FUNCTION__, MAC_ARG(GetAddr2Ptr(pframe)));
++
++ psta = rtw_get_stainfo(pstapriv, GetAddr2Ptr(pframe));
++ if(psta)
++ {
++ u8 updated;
++
++ _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++ if(rtw_is_list_empty(&psta->asoc_list)==_FALSE)
++ {
++ rtw_list_delete(&psta->asoc_list);
++ pstapriv->asoc_list_cnt--;
++ updated = ap_free_sta(padapter, psta, _FALSE, reason);
++
++ }
++ _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++
++ associated_clients_update(padapter, updated);
++ }
++
++
++ return _SUCCESS;
++ }
++ else
++#endif
++ {
++ int ignore_received_deauth = 0;
++
++ // Commented by Albert 20130604
++ // Before sending the auth frame to start the STA/GC mode connection with AP/GO,
++ // we will send the deauth first.
++ // However, the Win8.1 with BRCM Wi-Fi will send the deauth with reason code 6 to us after receieving our deauth.
++ // Added the following code to avoid this case.
++ if ( ( pmlmeinfo->state & WIFI_FW_AUTH_STATE ) ||
++ ( pmlmeinfo->state & WIFI_FW_ASSOC_STATE ) )
++ {
++ if ( reason == WLAN_REASON_CLASS2_FRAME_FROM_NONAUTH_STA )
++ {
++ ignore_received_deauth = 1;
++ } else if (WLAN_REASON_PREV_AUTH_NOT_VALID == reason) {
++ // TODO: 802.11r
++ ignore_received_deauth = 1;
++ }
++ }
++
++ DBG_871X("%s, STA:" MAC_FMT ", ignore = %d\n", __FUNCTION__, MAC_ARG(GetAddr3Ptr(pframe)), ignore_received_deauth);
++ if ( 0 == ignore_received_deauth )
++ {
++ receive_disconnect(padapter, GetAddr3Ptr(pframe) ,reason);
++ }
++ }
++ pmlmepriv->LinkDetectInfo.bBusyTraffic = _FALSE;
++ return _SUCCESS;
++
++}
++
++unsigned int OnDisassoc(_adapter *padapter, union recv_frame *precv_frame)
++{
++ unsigned short reason;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ u8 *pframe = precv_frame->u.hdr.rx_data;
++#ifdef CONFIG_P2P
++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo);
++#endif //CONFIG_P2P
++
++ //check A3
++ if (!(_rtw_memcmp(GetAddr3Ptr(pframe), get_my_bssid(&pmlmeinfo->network), ETH_ALEN)))
++ return _SUCCESS;
++
++#ifdef CONFIG_P2P
++ if ( pwdinfo->rx_invitereq_info.scan_op_ch_only )
++ {
++ _cancel_timer_ex( &pwdinfo->reset_ch_sitesurvey );
++ _set_timer( &pwdinfo->reset_ch_sitesurvey, 10 );
++ }
++#endif //CONFIG_P2P
++
++ reason = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN));
++
++ DBG_871X("%s Reason code(%d)\n", __FUNCTION__,reason);
++
++#ifdef CONFIG_AP_MODE
++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE)
++ {
++ _irqL irqL;
++ struct sta_info *psta;
++ struct sta_priv *pstapriv = &padapter->stapriv;
++
++ //_enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL);
++ //rtw_free_stainfo(padapter, psta);
++ //_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);
++
++ DBG_871X("%s, STA:" MAC_FMT "\n", __FUNCTION__, MAC_ARG(GetAddr2Ptr(pframe)));
++
++ psta = rtw_get_stainfo(pstapriv, GetAddr2Ptr(pframe));
++ if(psta)
++ {
++ u8 updated;
++
++ _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++ if(rtw_is_list_empty(&psta->asoc_list)==_FALSE)
++ {
++ rtw_list_delete(&psta->asoc_list);
++ pstapriv->asoc_list_cnt--;
++ updated = ap_free_sta(padapter, psta, _FALSE, reason);
++
++ }
++ _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++
++ associated_clients_update(padapter, updated);
++ }
++
++ return _SUCCESS;
++ }
++ else
++#endif
++ {
++ DBG_871X("%s, STA:" MAC_FMT "\n", __FUNCTION__, MAC_ARG(GetAddr3Ptr(pframe)));
++
++ receive_disconnect(padapter, GetAddr3Ptr(pframe), reason);
++ }
++ pmlmepriv->LinkDetectInfo.bBusyTraffic = _FALSE;
++ return _SUCCESS;
++
++}
++
++unsigned int OnAtim(_adapter *padapter, union recv_frame *precv_frame)
++{
++ DBG_871X("%s\n", __FUNCTION__);
++ return _SUCCESS;
++}
++
++unsigned int on_action_spct_ch_switch(_adapter *padapter, struct sta_info *psta, u8 *ies, uint ies_len)
++{
++ unsigned int ret = _FAIL;
++ struct mlme_ext_priv *mlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(mlmeext->mlmext_info);
++
++ if (!(pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)) {
++ ret = _SUCCESS;
++ goto exit;
++ }
++
++ if ((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE) {
++
++ int ch_switch_mode = -1, ch = -1, ch_switch_cnt = -1;
++ int ch_offset = -1;
++ u8 bwmode;
++ struct ieee80211_info_element *ie;
++
++ DBG_871X(FUNC_NDEV_FMT" from "MAC_FMT"\n",
++ FUNC_NDEV_ARG(padapter->pnetdev), MAC_ARG(psta->hwaddr));
++
++ for_each_ie(ie, ies, ies_len) {
++ if (ie->id == WLAN_EID_CHANNEL_SWITCH) {
++ ch_switch_mode = ie->data[0];
++ ch = ie->data[1];
++ ch_switch_cnt = ie->data[2];
++ DBG_871X("ch_switch_mode:%d, ch:%d, ch_switch_cnt:%d\n",
++ ch_switch_mode, ch, ch_switch_cnt);
++ }
++ else if (ie->id == WLAN_EID_SECONDARY_CHANNEL_OFFSET) {
++ ch_offset = secondary_ch_offset_to_hal_ch_offset(ie->data[0]);
++ DBG_871X("ch_offset:%d\n", ch_offset);
++ }
++ }
++
++ if (ch == -1)
++ return _SUCCESS;
++
++ if (ch_offset == -1)
++ bwmode = mlmeext->cur_bwmode;
++ else
++ bwmode = (ch_offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE) ?
++ HT_CHANNEL_WIDTH_20 : HT_CHANNEL_WIDTH_40;
++
++ ch_offset = (ch_offset == -1) ? mlmeext->cur_ch_offset : ch_offset;
++
++ /* todo:
++ * 1. the decision of channel switching
++ * 2. things after channel switching
++ */
++
++ ret = rtw_set_ch_cmd(padapter, ch, bwmode, ch_offset, _TRUE);
++ }
++
++exit:
++ return ret;
++}
++
++unsigned int on_action_spct(_adapter *padapter, union recv_frame *precv_frame)
++{
++ unsigned int ret = _FAIL;
++ struct sta_info *psta = NULL;
++ struct sta_priv *pstapriv = &padapter->stapriv;
++ u8 *pframe = precv_frame->u.hdr.rx_data;
++ uint frame_len = precv_frame->u.hdr.len;
++ u8 *frame_body = (u8 *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr));
++ u8 category;
++ u8 action;
++
++ DBG_871X(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(padapter->pnetdev));
++
++ psta = rtw_get_stainfo(pstapriv, GetAddr2Ptr(pframe));
++
++ if (!psta)
++ goto exit;
++
++ category = frame_body[0];
++ if(category != RTW_WLAN_CATEGORY_SPECTRUM_MGMT)
++ goto exit;
++
++ action = frame_body[1];
++ switch (action) {
++ case RTW_WLAN_ACTION_SPCT_MSR_REQ:
++ case RTW_WLAN_ACTION_SPCT_MSR_RPRT:
++ case RTW_WLAN_ACTION_SPCT_TPC_REQ:
++ case RTW_WLAN_ACTION_SPCT_TPC_RPRT:
++ break;
++ case RTW_WLAN_ACTION_SPCT_CHL_SWITCH:
++ #ifdef CONFIG_SPCT_CH_SWITCH
++ ret = on_action_spct_ch_switch(padapter, psta, &frame_body[2],
++ frame_len-(frame_body-pframe)-2);
++ #endif
++ break;
++ default:
++ break;
++ }
++
++exit:
++ return ret;
++}
++
++unsigned int OnAction_qos(_adapter *padapter, union recv_frame *precv_frame)
++{
++ return _SUCCESS;
++}
++
++unsigned int OnAction_dls(_adapter *padapter, union recv_frame *precv_frame)
++{
++ return _SUCCESS;
++}
++
++unsigned int OnAction_back(_adapter *padapter, union recv_frame *precv_frame)
++{
++ u8 *addr;
++ struct sta_info *psta=NULL;
++ struct recv_reorder_ctrl *preorder_ctrl;
++ unsigned char *frame_body;
++ unsigned char category, action;
++ unsigned short tid, status, reason_code = 0;
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ u8 *pframe = precv_frame->u.hdr.rx_data;
++ struct sta_priv *pstapriv = &padapter->stapriv;
++
++ //check RA matches or not
++ if (!_rtw_memcmp(myid(&(padapter->eeprompriv)), GetAddr1Ptr(pframe), ETH_ALEN))//for if1, sta/ap mode
++ return _SUCCESS;
++
++/*
++ //check A1 matches or not
++ if (!_rtw_memcmp(myid(&(padapter->eeprompriv)), get_da(pframe), ETH_ALEN))
++ return _SUCCESS;
++*/
++ DBG_871X("%s\n", __FUNCTION__);
++
++ if((pmlmeinfo->state&0x03) != WIFI_FW_AP_STATE)
++ if (!(pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS))
++ return _SUCCESS;
++
++ addr = GetAddr2Ptr(pframe);
++ psta = rtw_get_stainfo(pstapriv, addr);
++
++ if(psta==NULL)
++ return _SUCCESS;
++
++ frame_body = (unsigned char *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr));
++
++ category = frame_body[0];
++ if (category == RTW_WLAN_CATEGORY_BACK)// representing Block Ack
++ {
++#ifdef CONFIG_TDLS
++ if((psta->tdls_sta_state & TDLS_LINKED_STATE) &&
++ (psta->htpriv.ht_option==_TRUE) &&
++ (psta->htpriv.ampdu_enable==_TRUE) )
++ {
++ //do nothing; just don't want to return _SUCCESS;
++ }
++ else
++#endif //CONFIG_TDLS
++ if (!pmlmeinfo->HT_enable)
++ {
++ return _SUCCESS;
++ }
++
++ action = frame_body[1];
++ DBG_871X("%s, action=%d\n", __FUNCTION__, action);
++ switch (action)
++ {
++ case RTW_WLAN_ACTION_ADDBA_REQ: //ADDBA request
++
++ _rtw_memcpy(&(pmlmeinfo->ADDBA_req), &(frame_body[2]), sizeof(struct ADDBA_request));
++ //process_addba_req(padapter, (u8*)&(pmlmeinfo->ADDBA_req), GetAddr3Ptr(pframe));
++ process_addba_req(padapter, (u8*)&(pmlmeinfo->ADDBA_req), addr);
++
++ if(pmlmeinfo->bAcceptAddbaReq == _TRUE)
++ {
++ issue_action_BA(padapter, addr, RTW_WLAN_ACTION_ADDBA_RESP, 0);
++ }
++ else
++ {
++ issue_action_BA(padapter, addr, RTW_WLAN_ACTION_ADDBA_RESP, 37);//reject ADDBA Req
++ }
++
++ break;
++
++ case RTW_WLAN_ACTION_ADDBA_RESP: //ADDBA response
++
++ //status = frame_body[3] | (frame_body[4] << 8); //endian issue
++ status = RTW_GET_LE16(&frame_body[3]);
++ tid = ((frame_body[5] >> 2) & 0x7);
++
++ if (status == 0)
++ { //successful
++ DBG_871X("agg_enable for TID=%d\n", tid);
++ psta->htpriv.agg_enable_bitmap |= 1 << tid;
++ psta->htpriv.candidate_tid_bitmap &= ~BIT(tid);
++ }
++ else
++ {
++ psta->htpriv.agg_enable_bitmap &= ~BIT(tid);
++ }
++
++ //DBG_871X("marc: ADDBA RSP: %x\n", pmlmeinfo->agg_enable_bitmap);
++ break;
++
++ case RTW_WLAN_ACTION_DELBA: //DELBA
++ if ((frame_body[3] & BIT(3)) == 0)
++ {
++ psta->htpriv.agg_enable_bitmap &= ~(1 << ((frame_body[3] >> 4) & 0xf));
++ psta->htpriv.candidate_tid_bitmap &= ~(1 << ((frame_body[3] >> 4) & 0xf));
++
++ //reason_code = frame_body[4] | (frame_body[5] << 8);
++ reason_code = RTW_GET_LE16(&frame_body[4]);
++ }
++ else if((frame_body[3] & BIT(3)) == BIT(3))
++ {
++ tid = (frame_body[3] >> 4) & 0x0F;
++
++ preorder_ctrl = &psta->recvreorder_ctrl[tid];
++ preorder_ctrl->enable = _FALSE;
++ preorder_ctrl->indicate_seq = 0xffff;
++ #ifdef DBG_RX_SEQ
++ DBG_871X("DBG_RX_SEQ %s:%d indicate_seq:%u \n", __FUNCTION__, __LINE__,
++ preorder_ctrl->indicate_seq);
++ #endif
++ }
++
++ DBG_871X("%s(): DELBA: %x(%x)\n", __FUNCTION__,pmlmeinfo->agg_enable_bitmap, reason_code);
++ //todo: how to notify the host while receiving DELETE BA
++ break;
++
++ default:
++ break;
++ }
++ }
++
++ return _SUCCESS;
++}
++
++#ifdef CONFIG_P2P
++
++static int get_reg_classes_full_count(struct p2p_channels channel_list) {
++ int cnt = 0;
++ int i;
++
++ for (i = 0; i < channel_list.reg_classes; i++) {
++ cnt += channel_list.reg_class[i].channels;
++ }
++
++ return cnt;
++}
++
++static void get_channel_cnt_24g_5gl_5gh( struct mlme_ext_priv *pmlmeext, u8* p24g_cnt, u8* p5gl_cnt, u8* p5gh_cnt )
++{
++ int i = 0;
++
++ *p24g_cnt = 0;
++ *p5gl_cnt = 0;
++ *p5gh_cnt = 0;
++
++ for( i = 0; i < pmlmeext->max_chan_nums; i++ )
++ {
++ if ( pmlmeext->channel_set[ i ].ChannelNum <= 14 )
++ {
++ (*p24g_cnt)++;
++ }
++ else if ( ( pmlmeext->channel_set[ i ].ChannelNum > 14 ) && ( pmlmeext->channel_set[ i ].ChannelNum <= 48 ) )
++ {
++ // Just include the channel 36, 40, 44, 48 channels for 5G low
++ (*p5gl_cnt)++;
++ }
++ else if ( ( pmlmeext->channel_set[ i ].ChannelNum >= 149 ) && ( pmlmeext->channel_set[ i ].ChannelNum <= 161 ) )
++ {
++ // Just include the channel 149, 153, 157, 161 channels for 5G high
++ (*p5gh_cnt)++;
++ }
++ }
++}
++
++void issue_p2p_GO_request(_adapter *padapter, u8* raddr)
++{
++
++ unsigned char category = RTW_WLAN_CATEGORY_PUBLIC;
++ u8 action = P2P_PUB_ACTION_ACTION;
++ u32 p2poui = cpu_to_be32(P2POUI);
++ u8 oui_subtype = P2P_GO_NEGO_REQ;
++ u8 wpsie[ 255 ] = { 0x00 }, p2pie[ 255 ] = { 0x00 };
++ u8 wpsielen = 0, p2pielen = 0, i;
++ u8 channel_cnt_24g = 0, channel_cnt_5gl = 0, channel_cnt_5gh = 0;
++ u16 len_channellist_attr = 0;
++#ifdef CONFIG_WFD
++ u32 wfdielen = 0;
++#endif //CONFIG_WFD
++
++ struct xmit_frame *pmgntframe;
++ struct pkt_attrib *pattrib;
++ unsigned char *pframe;
++ struct rtw_ieee80211_hdr *pwlanhdr;
++ unsigned short *fctrl;
++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo);
++
++
++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL)
++ {
++ return;
++ }
++
++ DBG_871X( "[%s] In\n", __FUNCTION__ );
++ //update attribute
++ pattrib = &pmgntframe->attrib;
++ update_mgntframe_attrib(padapter, pattrib);
++
++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++ fctrl = &(pwlanhdr->frame_ctl);
++ *(fctrl) = 0;
++
++ _rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr3, myid(&(padapter->eeprompriv)), ETH_ALEN);
++
++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
++ pmlmeext->mgnt_seq++;
++ SetFrameSubType(pframe, WIFI_ACTION);
++
++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
++ pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++
++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
++ pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));
++ pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen));
++ pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen));
++ pwdinfo->negotiation_dialog_token = 1; // Initialize the dialog value
++ pframe = rtw_set_fixed_ie(pframe, 1, &pwdinfo->negotiation_dialog_token, &(pattrib->pktlen));
++
++
++
++ // WPS Section
++ wpsielen = 0;
++ // WPS OUI
++ *(u32*) ( wpsie ) = cpu_to_be32( WPSOUI );
++ wpsielen += 4;
++
++ // WPS version
++ // Type:
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_VER1 );
++ wpsielen += 2;
++
++ // Length:
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0001 );
++ wpsielen += 2;
++
++ // Value:
++ wpsie[wpsielen++] = WPS_VERSION_1; // Version 1.0
++
++ // Device Password ID
++ // Type:
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_DEVICE_PWID );
++ wpsielen += 2;
++
++ // Length:
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0002 );
++ wpsielen += 2;
++
++ // Value:
++
++ if ( pwdinfo->ui_got_wps_info == P2P_GOT_WPSINFO_PEER_DISPLAY_PIN )
++ {
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_DPID_USER_SPEC );
++ }
++ else if ( pwdinfo->ui_got_wps_info == P2P_GOT_WPSINFO_SELF_DISPLAY_PIN )
++ {
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_DPID_REGISTRAR_SPEC );
++ }
++ else if ( pwdinfo->ui_got_wps_info == P2P_GOT_WPSINFO_PBC )
++ {
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_DPID_PBC );
++ }
++
++ wpsielen += 2;
++
++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen );
++
++
++ // P2P IE Section.
++
++ // P2P OUI
++ p2pielen = 0;
++ p2pie[ p2pielen++ ] = 0x50;
++ p2pie[ p2pielen++ ] = 0x6F;
++ p2pie[ p2pielen++ ] = 0x9A;
++ p2pie[ p2pielen++ ] = 0x09; // WFA P2P v1.0
++
++ // Commented by Albert 20110306
++ // According to the P2P Specification, the group negoitation request frame should contain 9 P2P attributes
++ // 1. P2P Capability
++ // 2. Group Owner Intent
++ // 3. Configuration Timeout
++ // 4. Listen Channel
++ // 5. Extended Listen Timing
++ // 6. Intended P2P Interface Address
++ // 7. Channel List
++ // 8. P2P Device Info
++ // 9. Operating Channel
++
++
++ // P2P Capability
++ // Type:
++ p2pie[ p2pielen++ ] = P2P_ATTR_CAPABILITY;
++
++ // Length:
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0002 );
++ p2pielen += 2;
++
++ // Value:
++ // Device Capability Bitmap, 1 byte
++ p2pie[ p2pielen++ ] = DMP_P2P_DEVCAP_SUPPORT;
++
++ // Group Capability Bitmap, 1 byte
++ if ( pwdinfo->persistent_supported )
++ {
++ p2pie[ p2pielen++ ] = P2P_GRPCAP_CROSS_CONN | P2P_GRPCAP_PERSISTENT_GROUP;
++ }
++ else
++ {
++ p2pie[ p2pielen++ ] = P2P_GRPCAP_CROSS_CONN;
++ }
++
++
++ // Group Owner Intent
++ // Type:
++ p2pie[ p2pielen++ ] = P2P_ATTR_GO_INTENT;
++
++ // Length:
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0001 );
++ p2pielen += 2;
++
++ // Value:
++ // Todo the tie breaker bit.
++ p2pie[ p2pielen++ ] = ( ( pwdinfo->intent << 1 ) | BIT(0) );
++
++ // Configuration Timeout
++ // Type:
++ p2pie[ p2pielen++ ] = P2P_ATTR_CONF_TIMEOUT;
++
++ // Length:
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0002 );
++ p2pielen += 2;
++
++ // Value:
++ p2pie[ p2pielen++ ] = 200; // 2 seconds needed to be the P2P GO
++ p2pie[ p2pielen++ ] = 200; // 2 seconds needed to be the P2P Client
++
++
++ // Listen Channel
++ // Type:
++ p2pie[ p2pielen++ ] = P2P_ATTR_LISTEN_CH;
++
++ // Length:
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0005 );
++ p2pielen += 2;
++
++ // Value:
++ // Country String
++ p2pie[ p2pielen++ ] = 'X';
++ p2pie[ p2pielen++ ] = 'X';
++
++ // The third byte should be set to 0x04.
++ // Described in the "Operating Channel Attribute" section.
++ p2pie[ p2pielen++ ] = 0x04;
++
++ // Operating Class
++ p2pie[ p2pielen++ ] = 0x51; // Copy from SD7
++
++ // Channel Number
++ p2pie[ p2pielen++ ] = pwdinfo->listen_channel; // listening channel number
++
++
++ // Extended Listen Timing ATTR
++ // Type:
++ p2pie[ p2pielen++ ] = P2P_ATTR_EX_LISTEN_TIMING;
++
++ // Length:
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0004 );
++ p2pielen += 2;
++
++ // Value:
++ // Availability Period
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0xFFFF );
++ p2pielen += 2;
++
++ // Availability Interval
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0xFFFF );
++ p2pielen += 2;
++
++
++ // Intended P2P Interface Address
++ // Type:
++ p2pie[ p2pielen++ ] = P2P_ATTR_INTENTED_IF_ADDR;
++
++ // Length:
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( ETH_ALEN );
++ p2pielen += 2;
++
++ // Value:
++ _rtw_memcpy( p2pie + p2pielen, myid( &padapter->eeprompriv ), ETH_ALEN );
++ p2pielen += ETH_ALEN;
++
++
++ // Channel List
++ // Type:
++ p2pie[ p2pielen++ ] = P2P_ATTR_CH_LIST;
++
++ // Length:
++ // Country String(3)
++ // + ( Operating Class (1) + Number of Channels(1) ) * Operation Classes (?)
++ // + number of channels in all classes
++ len_channellist_attr = 3
++ + (1 + 1) * (u16)(pmlmeext->channel_list.reg_classes)
++ + get_reg_classes_full_count(pmlmeext->channel_list);
++
++#ifdef CONFIG_CONCURRENT_MODE
++ if ( check_buddy_fwstate(padapter, _FW_LINKED ) )
++ {
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 5 + 1 );
++ }
++ else
++ {
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( len_channellist_attr );
++ }
++#else
++
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( len_channellist_attr );
++
++#endif
++ p2pielen += 2;
++
++ // Value:
++ // Country String
++ p2pie[ p2pielen++ ] = 'X';
++ p2pie[ p2pielen++ ] = 'X';
++
++ // The third byte should be set to 0x04.
++ // Described in the "Operating Channel Attribute" section.
++ p2pie[ p2pielen++ ] = 0x04;
++
++ // Channel Entry List
++
++#ifdef CONFIG_CONCURRENT_MODE
++ if ( check_buddy_fwstate(padapter, _FW_LINKED ) )
++ {
++ _adapter *pbuddy_adapter = padapter->pbuddy_adapter;
++ struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv;
++
++ // Operating Class
++ if ( pbuddy_mlmeext->cur_channel > 14 )
++ {
++ if ( pbuddy_mlmeext->cur_channel >= 149 )
++ {
++ p2pie[ p2pielen++ ] = 0x7c;
++ }
++ else
++ {
++ p2pie[ p2pielen++ ] = 0x73;
++ }
++ }
++ else
++ {
++ p2pie[ p2pielen++ ] = 0x51;
++ }
++
++ // Number of Channels
++ // Just support 1 channel and this channel is AP's channel
++ p2pie[ p2pielen++ ] = 1;
++
++ // Channel List
++ p2pie[ p2pielen++ ] = pbuddy_mlmeext->cur_channel;
++ }
++ else
++ {
++ int i,j;
++ for (j = 0; j < pmlmeext->channel_list.reg_classes; j++) {
++ // Operating Class
++ p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class;
++
++ // Number of Channels
++ p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels;
++
++ // Channel List
++ for (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++) {
++ p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i];
++ }
++ }
++ }
++#else // CONFIG_CONCURRENT_MODE
++ {
++ int i,j;
++ for (j = 0; j < pmlmeext->channel_list.reg_classes; j++) {
++ // Operating Class
++ p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class;
++
++ // Number of Channels
++ p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels;
++
++ // Channel List
++ for (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++) {
++ p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i];
++ }
++ }
++ }
++#endif // CONFIG_CONCURRENT_MODE
++
++ // Device Info
++ // Type:
++ p2pie[ p2pielen++ ] = P2P_ATTR_DEVICE_INFO;
++
++ // Length:
++ // 21 -> P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes)
++ // + NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes)
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 21 + pwdinfo->device_name_len );
++ p2pielen += 2;
++
++ // Value:
++ // P2P Device Address
++ _rtw_memcpy( p2pie + p2pielen, myid( &padapter->eeprompriv ), ETH_ALEN );
++ p2pielen += ETH_ALEN;
++
++ // Config Method
++ // This field should be big endian. Noted by P2P specification.
++
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( pwdinfo->supported_wps_cm );
++
++ p2pielen += 2;
++
++ // Primary Device Type
++ // Category ID
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_CID_MULIT_MEDIA );
++ p2pielen += 2;
++
++ // OUI
++ *(u32*) ( p2pie + p2pielen ) = cpu_to_be32( WPSOUI );
++ p2pielen += 4;
++
++ // Sub Category ID
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_SCID_MEDIA_SERVER );
++ p2pielen += 2;
++
++ // Number of Secondary Device Types
++ p2pie[ p2pielen++ ] = 0x00; // No Secondary Device Type List
++
++ // Device Name
++ // Type:
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_ATTR_DEVICE_NAME );
++ p2pielen += 2;
++
++ // Length:
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( pwdinfo->device_name_len );
++ p2pielen += 2;
++
++ // Value:
++ _rtw_memcpy( p2pie + p2pielen, pwdinfo->device_name , pwdinfo->device_name_len );
++ p2pielen += pwdinfo->device_name_len;
++
++
++ // Operating Channel
++ // Type:
++ p2pie[ p2pielen++ ] = P2P_ATTR_OPERATING_CH;
++
++ // Length:
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0005 );
++ p2pielen += 2;
++
++ // Value:
++ // Country String
++ p2pie[ p2pielen++ ] = 'X';
++ p2pie[ p2pielen++ ] = 'X';
++
++ // The third byte should be set to 0x04.
++ // Described in the "Operating Channel Attribute" section.
++ p2pie[ p2pielen++ ] = 0x04;
++
++ // Operating Class
++ if ( pwdinfo->operating_channel <= 14 )
++ {
++ // Operating Class
++ p2pie[ p2pielen++ ] = 0x51;
++ }
++ else if ( ( pwdinfo->operating_channel >= 36 ) && ( pwdinfo->operating_channel <= 48 ) )
++ {
++ // Operating Class
++ p2pie[ p2pielen++ ] = 0x73;
++ }
++ else
++ {
++ // Operating Class
++ p2pie[ p2pielen++ ] = 0x7c;
++ }
++
++ // Channel Number
++ p2pie[ p2pielen++ ] = pwdinfo->operating_channel; // operating channel number
++
++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen );
++
++#ifdef CONFIG_WFD
++ wfdielen = build_nego_req_wfd_ie(pwdinfo, pframe);
++ pframe += wfdielen;
++ pattrib->pktlen += wfdielen;
++#endif //CONFIG_WFD
++
++ pattrib->last_txcmdsz = pattrib->pktlen;
++
++ dump_mgntframe(padapter, pmgntframe);
++
++ return;
++
++}
++
++
++void issue_p2p_GO_response(_adapter *padapter, u8* raddr, u8* frame_body,uint len, u8 result)
++{
++
++ unsigned char category = RTW_WLAN_CATEGORY_PUBLIC;
++ u8 action = P2P_PUB_ACTION_ACTION;
++ u32 p2poui = cpu_to_be32(P2POUI);
++ u8 oui_subtype = P2P_GO_NEGO_RESP;
++ u8 wpsie[ 255 ] = { 0x00 }, p2pie[ 255 ] = { 0x00 };
++ u8 p2pielen = 0, i;
++ uint wpsielen = 0;
++ u16 wps_devicepassword_id = 0x0000;
++ uint wps_devicepassword_id_len = 0;
++ u8 channel_cnt_24g = 0, channel_cnt_5gl = 0, channel_cnt_5gh;
++ u16 len_channellist_attr = 0;
++
++ struct xmit_frame *pmgntframe;
++ struct pkt_attrib *pattrib;
++ unsigned char *pframe;
++ struct rtw_ieee80211_hdr *pwlanhdr;
++ unsigned short *fctrl;
++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo);
++
++#ifdef CONFIG_WFD
++ u32 wfdielen = 0;
++#endif //CONFIG_WFD
++
++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL)
++ {
++ return;
++ }
++
++ DBG_871X( "[%s] In, result = %d\n", __FUNCTION__, result );
++ //update attribute
++ pattrib = &pmgntframe->attrib;
++ update_mgntframe_attrib(padapter, pattrib);
++
++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++ fctrl = &(pwlanhdr->frame_ctl);
++ *(fctrl) = 0;
++
++ _rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr3, myid(&(padapter->eeprompriv)), ETH_ALEN);
++
++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
++ pmlmeext->mgnt_seq++;
++ SetFrameSubType(pframe, WIFI_ACTION);
++
++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
++ pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++
++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
++ pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));
++ pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen));
++ pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen));
++ pwdinfo->negotiation_dialog_token = frame_body[7]; // The Dialog Token of provisioning discovery request frame.
++ pframe = rtw_set_fixed_ie(pframe, 1, &(pwdinfo->negotiation_dialog_token), &(pattrib->pktlen));
++
++ // Commented by Albert 20110328
++ // Try to get the device password ID from the WPS IE of group negotiation request frame
++ // WiFi Direct test plan 5.1.15
++ rtw_get_wps_ie( frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, wpsie, &wpsielen);
++ rtw_get_wps_attr_content( wpsie, wpsielen, WPS_ATTR_DEVICE_PWID, (u8*) &wps_devicepassword_id, &wps_devicepassword_id_len);
++ wps_devicepassword_id = be16_to_cpu( wps_devicepassword_id );
++
++ _rtw_memset( wpsie, 0x00, 255 );
++ wpsielen = 0;
++
++ // WPS Section
++ wpsielen = 0;
++ // WPS OUI
++ *(u32*) ( wpsie ) = cpu_to_be32( WPSOUI );
++ wpsielen += 4;
++
++ // WPS version
++ // Type:
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_VER1 );
++ wpsielen += 2;
++
++ // Length:
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0001 );
++ wpsielen += 2;
++
++ // Value:
++ wpsie[wpsielen++] = WPS_VERSION_1; // Version 1.0
++
++ // Device Password ID
++ // Type:
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_DEVICE_PWID );
++ wpsielen += 2;
++
++ // Length:
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0002 );
++ wpsielen += 2;
++
++ // Value:
++ if ( wps_devicepassword_id == WPS_DPID_USER_SPEC )
++ {
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_DPID_REGISTRAR_SPEC );
++ }
++ else if ( wps_devicepassword_id == WPS_DPID_REGISTRAR_SPEC )
++ {
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_DPID_USER_SPEC );
++ }
++ else
++ {
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_DPID_PBC );
++ }
++ wpsielen += 2;
++
++ // Commented by Kurt 20120113
++ // If some device wants to do p2p handshake without sending prov_disc_req
++ // We have to get peer_req_cm from here.
++ if(_rtw_memcmp( pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "000", 3) )
++ {
++ if ( wps_devicepassword_id == WPS_DPID_USER_SPEC )
++ {
++ _rtw_memcpy( pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "dis", 3 );
++ }
++ else if ( wps_devicepassword_id == WPS_DPID_REGISTRAR_SPEC )
++ {
++ _rtw_memcpy( pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "pad", 3 );
++ }
++ else
++ {
++ _rtw_memcpy( pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "pbc", 3 );
++ }
++ }
++
++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen );
++
++
++ // P2P IE Section.
++
++ // P2P OUI
++ p2pielen = 0;
++ p2pie[ p2pielen++ ] = 0x50;
++ p2pie[ p2pielen++ ] = 0x6F;
++ p2pie[ p2pielen++ ] = 0x9A;
++ p2pie[ p2pielen++ ] = 0x09; // WFA P2P v1.0
++
++ // Commented by Albert 20100908
++ // According to the P2P Specification, the group negoitation response frame should contain 9 P2P attributes
++ // 1. Status
++ // 2. P2P Capability
++ // 3. Group Owner Intent
++ // 4. Configuration Timeout
++ // 5. Operating Channel
++ // 6. Intended P2P Interface Address
++ // 7. Channel List
++ // 8. Device Info
++ // 9. Group ID ( Only GO )
++
++
++ // ToDo:
++
++ // P2P Status
++ // Type:
++ p2pie[ p2pielen++ ] = P2P_ATTR_STATUS;
++
++ // Length:
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0001 );
++ p2pielen += 2;
++
++ // Value:
++ p2pie[ p2pielen++ ] = result;
++
++ // P2P Capability
++ // Type:
++ p2pie[ p2pielen++ ] = P2P_ATTR_CAPABILITY;
++
++ // Length:
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0002 );
++ p2pielen += 2;
++
++ // Value:
++ // Device Capability Bitmap, 1 byte
++
++ if ( rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT) )
++ {
++ // Commented by Albert 2011/03/08
++ // According to the P2P specification
++ // if the sending device will be client, the P2P Capability should be reserved of group negotation response frame
++ p2pie[ p2pielen++ ] = 0;
++ }
++ else
++ {
++ // Be group owner or meet the error case
++ p2pie[ p2pielen++ ] = DMP_P2P_DEVCAP_SUPPORT;
++ }
++
++ // Group Capability Bitmap, 1 byte
++ if ( pwdinfo->persistent_supported )
++ {
++ p2pie[ p2pielen++ ] = P2P_GRPCAP_CROSS_CONN | P2P_GRPCAP_PERSISTENT_GROUP;
++ }
++ else
++ {
++ p2pie[ p2pielen++ ] = P2P_GRPCAP_CROSS_CONN;
++ }
++
++ // Group Owner Intent
++ // Type:
++ p2pie[ p2pielen++ ] = P2P_ATTR_GO_INTENT;
++
++ // Length:
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0001 );
++ p2pielen += 2;
++
++ // Value:
++ if ( pwdinfo->peer_intent & 0x01 )
++ {
++ // Peer's tie breaker bit is 1, our tie breaker bit should be 0
++ p2pie[ p2pielen++ ] = ( pwdinfo->intent << 1 );
++ }
++ else
++ {
++ // Peer's tie breaker bit is 0, our tie breaker bit should be 1
++ p2pie[ p2pielen++ ] = ( ( pwdinfo->intent << 1 ) | BIT(0) );
++ }
++
++
++ // Configuration Timeout
++ // Type:
++ p2pie[ p2pielen++ ] = P2P_ATTR_CONF_TIMEOUT;
++
++ // Length:
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0002 );
++ p2pielen += 2;
++
++ // Value:
++ p2pie[ p2pielen++ ] = 200; // 2 seconds needed to be the P2P GO
++ p2pie[ p2pielen++ ] = 200; // 2 seconds needed to be the P2P Client
++
++ // Operating Channel
++ // Type:
++ p2pie[ p2pielen++ ] = P2P_ATTR_OPERATING_CH;
++
++ // Length:
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0005 );
++ p2pielen += 2;
++
++ // Value:
++ // Country String
++ p2pie[ p2pielen++ ] = 'X';
++ p2pie[ p2pielen++ ] = 'X';
++
++ // The third byte should be set to 0x04.
++ // Described in the "Operating Channel Attribute" section.
++ p2pie[ p2pielen++ ] = 0x04;
++
++ // Operating Class
++ if ( pwdinfo->operating_channel <= 14 )
++ {
++ // Operating Class
++ p2pie[ p2pielen++ ] = 0x51;
++ }
++ else if ( ( pwdinfo->operating_channel >= 36 ) && ( pwdinfo->operating_channel <= 48 ) )
++ {
++ // Operating Class
++ p2pie[ p2pielen++ ] = 0x73;
++ }
++ else
++ {
++ // Operating Class
++ p2pie[ p2pielen++ ] = 0x7c;
++ }
++
++ // Channel Number
++ p2pie[ p2pielen++ ] = pwdinfo->operating_channel; // operating channel number
++
++ // Intended P2P Interface Address
++ // Type:
++ p2pie[ p2pielen++ ] = P2P_ATTR_INTENTED_IF_ADDR;
++
++ // Length:
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( ETH_ALEN );
++ p2pielen += 2;
++
++ // Value:
++ _rtw_memcpy( p2pie + p2pielen, myid( &padapter->eeprompriv ), ETH_ALEN );
++ p2pielen += ETH_ALEN;
++
++ // Channel List
++ // Type:
++ p2pie[ p2pielen++ ] = P2P_ATTR_CH_LIST;
++
++ // Country String(3)
++ // + ( Operating Class (1) + Number of Channels(1) ) * Operation Classes (?)
++ // + number of channels in all classes
++ len_channellist_attr = 3
++ + (1 + 1) * (u16)pmlmeext->channel_list.reg_classes
++ + get_reg_classes_full_count(pmlmeext->channel_list);
++
++#ifdef CONFIG_CONCURRENT_MODE
++ if ( check_buddy_fwstate(padapter, _FW_LINKED ) )
++ {
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 5 + 1 );
++ }
++ else
++ {
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( len_channellist_attr );
++ }
++#else
++
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( len_channellist_attr );
++
++ #endif
++ p2pielen += 2;
++
++ // Value:
++ // Country String
++ p2pie[ p2pielen++ ] = 'X';
++ p2pie[ p2pielen++ ] = 'X';
++
++ // The third byte should be set to 0x04.
++ // Described in the "Operating Channel Attribute" section.
++ p2pie[ p2pielen++ ] = 0x04;
++
++ // Channel Entry List
++
++#ifdef CONFIG_CONCURRENT_MODE
++ if ( check_buddy_fwstate(padapter, _FW_LINKED ) )
++ {
++ _adapter *pbuddy_adapter = padapter->pbuddy_adapter;
++ struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv;
++
++ // Operating Class
++ if ( pbuddy_mlmeext->cur_channel > 14 )
++ {
++ if ( pbuddy_mlmeext->cur_channel >= 149 )
++ {
++ p2pie[ p2pielen++ ] = 0x7c;
++ }
++ else
++ {
++ p2pie[ p2pielen++ ] = 0x73;
++ }
++ }
++ else
++ {
++ p2pie[ p2pielen++ ] = 0x51;
++ }
++
++ // Number of Channels
++ // Just support 1 channel and this channel is AP's channel
++ p2pie[ p2pielen++ ] = 1;
++
++ // Channel List
++ p2pie[ p2pielen++ ] = pbuddy_mlmeext->cur_channel;
++ }
++ else
++ {
++ int i, j;
++ for (j = 0; j < pmlmeext->channel_list.reg_classes; j++) {
++ // Operating Class
++ p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class;
++
++ // Number of Channels
++ p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels;
++
++ // Channel List
++ for (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++) {
++ p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i];
++ }
++ }
++ }
++#else // CONFIG_CONCURRENT_MODE
++ {
++ int i, j;
++ for (j = 0; j < pmlmeext->channel_list.reg_classes; j++) {
++ // Operating Class
++ p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class;
++
++ // Number of Channels
++ p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels;
++
++ // Channel List
++ for (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++) {
++ p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i];
++ }
++ }
++ }
++#endif // CONFIG_CONCURRENT_MODE
++
++ // Device Info
++ // Type:
++ p2pie[ p2pielen++ ] = P2P_ATTR_DEVICE_INFO;
++
++ // Length:
++ // 21 -> P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes)
++ // + NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes)
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 21 + pwdinfo->device_name_len );
++ p2pielen += 2;
++
++ // Value:
++ // P2P Device Address
++ _rtw_memcpy( p2pie + p2pielen, myid( &padapter->eeprompriv ), ETH_ALEN );
++ p2pielen += ETH_ALEN;
++
++ // Config Method
++ // This field should be big endian. Noted by P2P specification.
++
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( pwdinfo->supported_wps_cm );
++
++ p2pielen += 2;
++
++ // Primary Device Type
++ // Category ID
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_CID_MULIT_MEDIA );
++ p2pielen += 2;
++
++ // OUI
++ *(u32*) ( p2pie + p2pielen ) = cpu_to_be32( WPSOUI );
++ p2pielen += 4;
++
++ // Sub Category ID
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_SCID_MEDIA_SERVER );
++ p2pielen += 2;
++
++ // Number of Secondary Device Types
++ p2pie[ p2pielen++ ] = 0x00; // No Secondary Device Type List
++
++ // Device Name
++ // Type:
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_ATTR_DEVICE_NAME );
++ p2pielen += 2;
++
++ // Length:
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( pwdinfo->device_name_len );
++ p2pielen += 2;
++
++ // Value:
++ _rtw_memcpy( p2pie + p2pielen, pwdinfo->device_name , pwdinfo->device_name_len );
++ p2pielen += pwdinfo->device_name_len;
++
++ if ( rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO) )
++ {
++ // Group ID Attribute
++ // Type:
++ p2pie[ p2pielen++ ] = P2P_ATTR_GROUP_ID;
++
++ // Length:
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( ETH_ALEN + pwdinfo->nego_ssidlen );
++ p2pielen += 2;
++
++ // Value:
++ // p2P Device Address
++ _rtw_memcpy( p2pie + p2pielen , pwdinfo->device_addr, ETH_ALEN );
++ p2pielen += ETH_ALEN;
++
++ // SSID
++ _rtw_memcpy( p2pie + p2pielen, pwdinfo->nego_ssid, pwdinfo->nego_ssidlen );
++ p2pielen += pwdinfo->nego_ssidlen;
++
++ }
++
++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen );
++
++#ifdef CONFIG_WFD
++ wfdielen = build_nego_resp_wfd_ie(pwdinfo, pframe);
++ pframe += wfdielen;
++ pattrib->pktlen += wfdielen;
++#endif //CONFIG_WFD
++
++ pattrib->last_txcmdsz = pattrib->pktlen;
++
++ dump_mgntframe(padapter, pmgntframe);
++
++ return;
++
++}
++
++void issue_p2p_GO_confirm(_adapter *padapter, u8* raddr, u8 result)
++{
++
++ unsigned char category = RTW_WLAN_CATEGORY_PUBLIC;
++ u8 action = P2P_PUB_ACTION_ACTION;
++ u32 p2poui = cpu_to_be32(P2POUI);
++ u8 oui_subtype = P2P_GO_NEGO_CONF;
++ u8 wpsie[ 255 ] = { 0x00 }, p2pie[ 255 ] = { 0x00 };
++ u8 wpsielen = 0, p2pielen = 0;
++
++ struct xmit_frame *pmgntframe;
++ struct pkt_attrib *pattrib;
++ unsigned char *pframe;
++ struct rtw_ieee80211_hdr *pwlanhdr;
++ unsigned short *fctrl;
++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo);
++#ifdef CONFIG_WFD
++ u32 wfdielen = 0;
++#endif //CONFIG_WFD
++
++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL)
++ {
++ return;
++ }
++
++ DBG_871X( "[%s] In\n", __FUNCTION__ );
++ //update attribute
++ pattrib = &pmgntframe->attrib;
++ update_mgntframe_attrib(padapter, pattrib);
++
++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++ fctrl = &(pwlanhdr->frame_ctl);
++ *(fctrl) = 0;
++
++ _rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr3, myid(&(padapter->eeprompriv)), ETH_ALEN);
++
++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
++ pmlmeext->mgnt_seq++;
++ SetFrameSubType(pframe, WIFI_ACTION);
++
++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
++ pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++
++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
++ pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));
++ pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen));
++ pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen));
++ pframe = rtw_set_fixed_ie(pframe, 1, &(pwdinfo->negotiation_dialog_token), &(pattrib->pktlen));
++
++
++
++ // P2P IE Section.
++
++ // P2P OUI
++ p2pielen = 0;
++ p2pie[ p2pielen++ ] = 0x50;
++ p2pie[ p2pielen++ ] = 0x6F;
++ p2pie[ p2pielen++ ] = 0x9A;
++ p2pie[ p2pielen++ ] = 0x09; // WFA P2P v1.0
++
++ // Commented by Albert 20110306
++ // According to the P2P Specification, the group negoitation request frame should contain 5 P2P attributes
++ // 1. Status
++ // 2. P2P Capability
++ // 3. Operating Channel
++ // 4. Channel List
++ // 5. Group ID ( if this WiFi is GO )
++
++ // P2P Status
++ // Type:
++ p2pie[ p2pielen++ ] = P2P_ATTR_STATUS;
++
++ // Length:
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0001 );
++ p2pielen += 2;
++
++ // Value:
++ p2pie[ p2pielen++ ] = result;
++
++ // P2P Capability
++ // Type:
++ p2pie[ p2pielen++ ] = P2P_ATTR_CAPABILITY;
++
++ // Length:
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0002 );
++ p2pielen += 2;
++
++ // Value:
++ // Device Capability Bitmap, 1 byte
++ p2pie[ p2pielen++ ] = DMP_P2P_DEVCAP_SUPPORT;
++
++ // Group Capability Bitmap, 1 byte
++ if ( pwdinfo->persistent_supported )
++ {
++ p2pie[ p2pielen++ ] = P2P_GRPCAP_CROSS_CONN | P2P_GRPCAP_PERSISTENT_GROUP;
++ }
++ else
++ {
++ p2pie[ p2pielen++ ] = P2P_GRPCAP_CROSS_CONN;
++ }
++
++
++ // Operating Channel
++ // Type:
++ p2pie[ p2pielen++ ] = P2P_ATTR_OPERATING_CH;
++
++ // Length:
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0005 );
++ p2pielen += 2;
++
++ // Value:
++ // Country String
++ p2pie[ p2pielen++ ] = 'X';
++ p2pie[ p2pielen++ ] = 'X';
++
++ // The third byte should be set to 0x04.
++ // Described in the "Operating Channel Attribute" section.
++ p2pie[ p2pielen++ ] = 0x04;
++
++
++ if ( rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT) )
++ {
++ if ( pwdinfo->peer_operating_ch <= 14 )
++ {
++ // Operating Class
++ p2pie[ p2pielen++ ] = 0x51;
++ }
++ else if ( ( pwdinfo->peer_operating_ch >= 36 ) && ( pwdinfo->peer_operating_ch <= 48 ) )
++ {
++ // Operating Class
++ p2pie[ p2pielen++ ] = 0x73;
++ }
++ else
++ {
++ // Operating Class
++ p2pie[ p2pielen++ ] = 0x7c;
++ }
++
++ p2pie[ p2pielen++ ] = pwdinfo->peer_operating_ch;
++ }
++ else
++ {
++ if ( pwdinfo->operating_channel <= 14 )
++ {
++ // Operating Class
++ p2pie[ p2pielen++ ] = 0x51;
++ }
++ else if ( ( pwdinfo->operating_channel >= 36 ) && ( pwdinfo->operating_channel <= 48 ) )
++ {
++ // Operating Class
++ p2pie[ p2pielen++ ] = 0x73;
++ }
++ else
++ {
++ // Operating Class
++ p2pie[ p2pielen++ ] = 0x7c;
++ }
++
++ // Channel Number
++ p2pie[ p2pielen++ ] = pwdinfo->operating_channel; // Use the listen channel as the operating channel
++ }
++
++
++ // Channel List
++ // Type:
++ p2pie[ p2pielen++ ] = P2P_ATTR_CH_LIST;
++
++ *(u16*) ( p2pie + p2pielen ) = 6;
++ p2pielen += 2;
++
++ // Country String
++ p2pie[ p2pielen++ ] = 'X';
++ p2pie[ p2pielen++ ] = 'X';
++
++ // The third byte should be set to 0x04.
++ // Described in the "Operating Channel Attribute" section.
++ p2pie[ p2pielen++ ] = 0x04;
++
++ // Value:
++ if ( rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT) )
++ {
++ if ( pwdinfo->peer_operating_ch <= 14 )
++ {
++ // Operating Class
++ p2pie[ p2pielen++ ] = 0x51;
++ }
++ else if ( ( pwdinfo->peer_operating_ch >= 36 ) && ( pwdinfo->peer_operating_ch <= 48 ) )
++ {
++ // Operating Class
++ p2pie[ p2pielen++ ] = 0x73;
++ }
++ else
++ {
++ // Operating Class
++ p2pie[ p2pielen++ ] = 0x7c;
++ }
++ p2pie[ p2pielen++ ] = 1;
++ p2pie[ p2pielen++ ] = pwdinfo->peer_operating_ch;
++ }
++ else
++ {
++ if ( pwdinfo->operating_channel <= 14 )
++ {
++ // Operating Class
++ p2pie[ p2pielen++ ] = 0x51;
++ }
++ else if ( ( pwdinfo->operating_channel >= 36 ) && ( pwdinfo->operating_channel <= 48 ) )
++ {
++ // Operating Class
++ p2pie[ p2pielen++ ] = 0x73;
++ }
++ else
++ {
++ // Operating Class
++ p2pie[ p2pielen++ ] = 0x7c;
++ }
++
++ // Channel Number
++ p2pie[ p2pielen++ ] = 1;
++ p2pie[ p2pielen++ ] = pwdinfo->operating_channel; // Use the listen channel as the operating channel
++ }
++
++ if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO) )
++ {
++ // Group ID Attribute
++ // Type:
++ p2pie[ p2pielen++ ] = P2P_ATTR_GROUP_ID;
++
++ // Length:
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( ETH_ALEN + pwdinfo->nego_ssidlen );
++ p2pielen += 2;
++
++ // Value:
++ // p2P Device Address
++ _rtw_memcpy( p2pie + p2pielen , pwdinfo->device_addr, ETH_ALEN );
++ p2pielen += ETH_ALEN;
++
++ // SSID
++ _rtw_memcpy( p2pie + p2pielen, pwdinfo->nego_ssid, pwdinfo->nego_ssidlen );
++ p2pielen += pwdinfo->nego_ssidlen;
++ }
++
++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen );
++
++#ifdef CONFIG_WFD
++ wfdielen = build_nego_confirm_wfd_ie(pwdinfo, pframe);
++ pframe += wfdielen;
++ pattrib->pktlen += wfdielen;
++#endif //CONFIG_WFD
++
++ pattrib->last_txcmdsz = pattrib->pktlen;
++
++ dump_mgntframe(padapter, pmgntframe);
++
++ return;
++
++}
++
++void issue_p2p_invitation_request(_adapter *padapter, u8* raddr )
++{
++
++ unsigned char category = RTW_WLAN_CATEGORY_PUBLIC;
++ u8 action = P2P_PUB_ACTION_ACTION;
++ u32 p2poui = cpu_to_be32(P2POUI);
++ u8 oui_subtype = P2P_INVIT_REQ;
++ u8 p2pie[ 255 ] = { 0x00 };
++ u8 p2pielen = 0, i;
++ u8 dialogToken = 3;
++ u8 channel_cnt_24g = 0, channel_cnt_5gl = 0, channel_cnt_5gh = 0;
++ u16 len_channellist_attr = 0;
++#ifdef CONFIG_WFD
++ u32 wfdielen = 0;
++#endif //CONFIG_WFD
++#ifdef CONFIG_CONCURRENT_MODE
++ _adapter *pbuddy_adapter = padapter->pbuddy_adapter;
++ struct wifidirect_info *pbuddy_wdinfo = &pbuddy_adapter->wdinfo;
++ struct mlme_priv *pbuddy_mlmepriv = &pbuddy_adapter->mlmepriv;
++ struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv;
++#endif
++
++ struct xmit_frame *pmgntframe;
++ struct pkt_attrib *pattrib;
++ unsigned char *pframe;
++ struct rtw_ieee80211_hdr *pwlanhdr;
++ unsigned short *fctrl;
++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo);
++
++
++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL)
++ {
++ return;
++ }
++
++ //update attribute
++ pattrib = &pmgntframe->attrib;
++ update_mgntframe_attrib(padapter, pattrib);
++
++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++ fctrl = &(pwlanhdr->frame_ctl);
++ *(fctrl) = 0;
++
++ _rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr3, raddr, ETH_ALEN);
++
++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
++ pmlmeext->mgnt_seq++;
++ SetFrameSubType(pframe, WIFI_ACTION);
++
++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
++ pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++
++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
++ pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));
++ pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen));
++ pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen));
++ pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen));
++
++ // P2P IE Section.
++
++ // P2P OUI
++ p2pielen = 0;
++ p2pie[ p2pielen++ ] = 0x50;
++ p2pie[ p2pielen++ ] = 0x6F;
++ p2pie[ p2pielen++ ] = 0x9A;
++ p2pie[ p2pielen++ ] = 0x09; // WFA P2P v1.0
++
++ // Commented by Albert 20101011
++ // According to the P2P Specification, the P2P Invitation request frame should contain 7 P2P attributes
++ // 1. Configuration Timeout
++ // 2. Invitation Flags
++ // 3. Operating Channel ( Only GO )
++ // 4. P2P Group BSSID ( Should be included if I am the GO )
++ // 5. Channel List
++ // 6. P2P Group ID
++ // 7. P2P Device Info
++
++ // Configuration Timeout
++ // Type:
++ p2pie[ p2pielen++ ] = P2P_ATTR_CONF_TIMEOUT;
++
++ // Length:
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0002 );
++ p2pielen += 2;
++
++ // Value:
++ p2pie[ p2pielen++ ] = 200; // 2 seconds needed to be the P2P GO
++ p2pie[ p2pielen++ ] = 200; // 2 seconds needed to be the P2P Client
++
++ // Invitation Flags
++ // Type:
++ p2pie[ p2pielen++ ] = P2P_ATTR_INVITATION_FLAGS;
++
++ // Length:
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0001 );
++ p2pielen += 2;
++
++ // Value:
++ p2pie[ p2pielen++ ] = P2P_INVITATION_FLAGS_PERSISTENT;
++
++
++ // Operating Channel
++ // Type:
++ p2pie[ p2pielen++ ] = P2P_ATTR_OPERATING_CH;
++
++ // Length:
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0005 );
++ p2pielen += 2;
++
++ // Value:
++ // Country String
++ p2pie[ p2pielen++ ] = 'X';
++ p2pie[ p2pielen++ ] = 'X';
++
++ // The third byte should be set to 0x04.
++ // Described in the "Operating Channel Attribute" section.
++ p2pie[ p2pielen++ ] = 0x04;
++
++ // Operating Class
++ if ( pwdinfo->invitereq_info.operating_ch <= 14 )
++ p2pie[ p2pielen++ ] = 0x51;
++ else if ( ( pwdinfo->invitereq_info.operating_ch >= 36 ) && ( pwdinfo->invitereq_info.operating_ch <= 48 ) )
++ p2pie[ p2pielen++ ] = 0x73;
++ else
++ p2pie[ p2pielen++ ] = 0x7c;
++
++ // Channel Number
++ p2pie[ p2pielen++ ] = pwdinfo->invitereq_info.operating_ch; // operating channel number
++
++ if ( _rtw_memcmp( myid( &padapter->eeprompriv ), pwdinfo->invitereq_info.go_bssid, ETH_ALEN ) )
++ {
++ // P2P Group BSSID
++ // Type:
++ p2pie[ p2pielen++ ] = P2P_ATTR_GROUP_BSSID;
++
++ // Length:
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( ETH_ALEN );
++ p2pielen += 2;
++
++ // Value:
++ // P2P Device Address for GO
++ _rtw_memcpy( p2pie + p2pielen, pwdinfo->invitereq_info.go_bssid, ETH_ALEN );
++ p2pielen += ETH_ALEN;
++ }
++
++ // Channel List
++ // Type:
++ p2pie[ p2pielen++ ] = P2P_ATTR_CH_LIST;
++
++
++ // Length:
++ // Country String(3)
++ // + ( Operating Class (1) + Number of Channels(1) ) * Operation Classes (?)
++ // + number of channels in all classes
++ len_channellist_attr = 3
++ + (1 + 1) * (u16)pmlmeext->channel_list.reg_classes
++ + get_reg_classes_full_count(pmlmeext->channel_list);
++
++#ifdef CONFIG_CONCURRENT_MODE
++ if ( check_buddy_fwstate(padapter, _FW_LINKED ) )
++ {
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 5 + 1 );
++ }
++ else
++ {
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( len_channellist_attr );
++ }
++#else
++
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( len_channellist_attr );
++
++ #endif
++ p2pielen += 2;
++
++ // Value:
++ // Country String
++ p2pie[ p2pielen++ ] = 'X';
++ p2pie[ p2pielen++ ] = 'X';
++
++ // The third byte should be set to 0x04.
++ // Described in the "Operating Channel Attribute" section.
++ p2pie[ p2pielen++ ] = 0x04;
++
++ // Channel Entry List
++#ifdef CONFIG_CONCURRENT_MODE
++ if ( check_buddy_fwstate(padapter, _FW_LINKED ) )
++ {
++ _adapter *pbuddy_adapter = padapter->pbuddy_adapter;
++ struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv;
++
++ // Operating Class
++ if ( pbuddy_mlmeext->cur_channel > 14 )
++ {
++ if ( pbuddy_mlmeext->cur_channel >= 149 )
++ {
++ p2pie[ p2pielen++ ] = 0x7c;
++ }
++ else
++ {
++ p2pie[ p2pielen++ ] = 0x73;
++ }
++ }
++ else
++ {
++ p2pie[ p2pielen++ ] = 0x51;
++ }
++
++ // Number of Channels
++ // Just support 1 channel and this channel is AP's channel
++ p2pie[ p2pielen++ ] = 1;
++
++ // Channel List
++ p2pie[ p2pielen++ ] = pbuddy_mlmeext->cur_channel;
++ }
++ else
++ {
++ int i, j;
++ for (j = 0; j < pmlmeext->channel_list.reg_classes; j++) {
++ // Operating Class
++ p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class;
++
++ // Number of Channels
++ p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels;
++
++ // Channel List
++ for (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++) {
++ p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i];
++ }
++ }
++ }
++#else // CONFIG_CONCURRENT_MODE
++ {
++ int i, j;
++ for (j = 0; j < pmlmeext->channel_list.reg_classes; j++) {
++ // Operating Class
++ p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class;
++
++ // Number of Channels
++ p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels;
++
++ // Channel List
++ for (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++) {
++ p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i];
++ }
++ }
++ }
++#endif // CONFIG_CONCURRENT_MODE
++
++
++ // P2P Group ID
++ // Type:
++ p2pie[ p2pielen++ ] = P2P_ATTR_GROUP_ID;
++
++ // Length:
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 6 + pwdinfo->invitereq_info.ssidlen );
++ p2pielen += 2;
++
++ // Value:
++ // P2P Device Address for GO
++ _rtw_memcpy( p2pie + p2pielen, pwdinfo->invitereq_info.go_bssid, ETH_ALEN );
++ p2pielen += ETH_ALEN;
++
++ // SSID
++ _rtw_memcpy( p2pie + p2pielen, pwdinfo->invitereq_info.go_ssid, pwdinfo->invitereq_info.ssidlen );
++ p2pielen += pwdinfo->invitereq_info.ssidlen;
++
++
++ // Device Info
++ // Type:
++ p2pie[ p2pielen++ ] = P2P_ATTR_DEVICE_INFO;
++
++ // Length:
++ // 21 -> P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes)
++ // + NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes)
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 21 + pwdinfo->device_name_len );
++ p2pielen += 2;
++
++ // Value:
++ // P2P Device Address
++ _rtw_memcpy( p2pie + p2pielen, myid( &padapter->eeprompriv ), ETH_ALEN );
++ p2pielen += ETH_ALEN;
++
++ // Config Method
++ // This field should be big endian. Noted by P2P specification.
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_CONFIG_METHOD_DISPLAY );
++ p2pielen += 2;
++
++ // Primary Device Type
++ // Category ID
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_CID_MULIT_MEDIA );
++ p2pielen += 2;
++
++ // OUI
++ *(u32*) ( p2pie + p2pielen ) = cpu_to_be32( WPSOUI );
++ p2pielen += 4;
++
++ // Sub Category ID
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_SCID_MEDIA_SERVER );
++ p2pielen += 2;
++
++ // Number of Secondary Device Types
++ p2pie[ p2pielen++ ] = 0x00; // No Secondary Device Type List
++
++ // Device Name
++ // Type:
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_ATTR_DEVICE_NAME );
++ p2pielen += 2;
++
++ // Length:
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( pwdinfo->device_name_len );
++ p2pielen += 2;
++
++ // Value:
++ _rtw_memcpy( p2pie + p2pielen, pwdinfo->device_name, pwdinfo->device_name_len );
++ p2pielen += pwdinfo->device_name_len;
++
++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen );
++
++#ifdef CONFIG_WFD
++ wfdielen = build_invitation_req_wfd_ie(pwdinfo, pframe);
++ pframe += wfdielen;
++ pattrib->pktlen += wfdielen;
++#endif //CONFIG_WFD
++
++ pattrib->last_txcmdsz = pattrib->pktlen;
++
++ dump_mgntframe(padapter, pmgntframe);
++
++ return;
++
++}
++
++void issue_p2p_invitation_response(_adapter *padapter, u8* raddr, u8 dialogToken, u8 status_code)
++{
++
++ unsigned char category = RTW_WLAN_CATEGORY_PUBLIC;
++ u8 action = P2P_PUB_ACTION_ACTION;
++ u32 p2poui = cpu_to_be32(P2POUI);
++ u8 oui_subtype = P2P_INVIT_RESP;
++ u8 p2pie[ 255 ] = { 0x00 };
++ u8 p2pielen = 0, i;
++ u8 channel_cnt_24g = 0, channel_cnt_5gl = 0, channel_cnt_5gh = 0;
++ u16 len_channellist_attr = 0;
++#ifdef CONFIG_CONCURRENT_MODE
++ _adapter *pbuddy_adapter = padapter->pbuddy_adapter;
++ struct wifidirect_info *pbuddy_wdinfo = &pbuddy_adapter->wdinfo;
++ struct mlme_priv *pbuddy_mlmepriv = &pbuddy_adapter->mlmepriv;
++ struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv;
++#endif
++#ifdef CONFIG_WFD
++ u32 wfdielen = 0;
++#endif //CONFIG_WFD
++
++ struct xmit_frame *pmgntframe;
++ struct pkt_attrib *pattrib;
++ unsigned char *pframe;
++ struct rtw_ieee80211_hdr *pwlanhdr;
++ unsigned short *fctrl;
++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo);
++
++
++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL)
++ {
++ return;
++ }
++
++ //update attribute
++ pattrib = &pmgntframe->attrib;
++ update_mgntframe_attrib(padapter, pattrib);
++
++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++ fctrl = &(pwlanhdr->frame_ctl);
++ *(fctrl) = 0;
++
++ _rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr3, raddr, ETH_ALEN);
++
++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
++ pmlmeext->mgnt_seq++;
++ SetFrameSubType(pframe, WIFI_ACTION);
++
++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
++ pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++
++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
++ pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));
++ pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen));
++ pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen));
++ pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen));
++
++ // P2P IE Section.
++
++ // P2P OUI
++ p2pielen = 0;
++ p2pie[ p2pielen++ ] = 0x50;
++ p2pie[ p2pielen++ ] = 0x6F;
++ p2pie[ p2pielen++ ] = 0x9A;
++ p2pie[ p2pielen++ ] = 0x09; // WFA P2P v1.0
++
++ // Commented by Albert 20101005
++ // According to the P2P Specification, the P2P Invitation response frame should contain 5 P2P attributes
++ // 1. Status
++ // 2. Configuration Timeout
++ // 3. Operating Channel ( Only GO )
++ // 4. P2P Group BSSID ( Only GO )
++ // 5. Channel List
++
++ // P2P Status
++ // Type:
++ p2pie[ p2pielen++ ] = P2P_ATTR_STATUS;
++
++ // Length:
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0001 );
++ p2pielen += 2;
++
++ // Value:
++ // When status code is P2P_STATUS_FAIL_INFO_UNAVAILABLE.
++ // Sent the event receiving the P2P Invitation Req frame to DMP UI.
++ // DMP had to compare the MAC address to find out the profile.
++ // So, the WiFi driver will send the P2P_STATUS_FAIL_INFO_UNAVAILABLE to NB.
++ // If the UI found the corresponding profile, the WiFi driver sends the P2P Invitation Req
++ // to NB to rebuild the persistent group.
++ p2pie[ p2pielen++ ] = status_code;
++
++ // Configuration Timeout
++ // Type:
++ p2pie[ p2pielen++ ] = P2P_ATTR_CONF_TIMEOUT;
++
++ // Length:
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0002 );
++ p2pielen += 2;
++
++ // Value:
++ p2pie[ p2pielen++ ] = 200; // 2 seconds needed to be the P2P GO
++ p2pie[ p2pielen++ ] = 200; // 2 seconds needed to be the P2P Client
++
++ if( status_code == P2P_STATUS_SUCCESS )
++ {
++ if( rtw_p2p_chk_role( pwdinfo, P2P_ROLE_GO ) )
++ {
++ // The P2P Invitation request frame asks this Wi-Fi device to be the P2P GO
++ // In this case, the P2P Invitation response frame should carry the two more P2P attributes.
++ // First one is operating channel attribute.
++ // Second one is P2P Group BSSID attribute.
++
++ // Operating Channel
++ // Type:
++ p2pie[ p2pielen++ ] = P2P_ATTR_OPERATING_CH;
++
++ // Length:
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0005 );
++ p2pielen += 2;
++
++ // Value:
++ // Country String
++ p2pie[ p2pielen++ ] = 'X';
++ p2pie[ p2pielen++ ] = 'X';
++
++ // The third byte should be set to 0x04.
++ // Described in the "Operating Channel Attribute" section.
++ p2pie[ p2pielen++ ] = 0x04;
++
++ // Operating Class
++ p2pie[ p2pielen++ ] = 0x51; // Copy from SD7
++
++ // Channel Number
++ p2pie[ p2pielen++ ] = pwdinfo->operating_channel; // operating channel number
++
++
++ // P2P Group BSSID
++ // Type:
++ p2pie[ p2pielen++ ] = P2P_ATTR_GROUP_BSSID;
++
++ // Length:
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( ETH_ALEN );
++ p2pielen += 2;
++
++ // Value:
++ // P2P Device Address for GO
++ _rtw_memcpy( p2pie + p2pielen, myid( &padapter->eeprompriv ), ETH_ALEN );
++ p2pielen += ETH_ALEN;
++
++ }
++
++ // Channel List
++ // Type:
++ p2pie[ p2pielen++ ] = P2P_ATTR_CH_LIST;
++
++ // Length:
++ // Country String(3)
++ // + ( Operating Class (1) + Number of Channels(1) ) * Operation Classes (?)
++ // + number of channels in all classes
++ len_channellist_attr = 3
++ + (1 + 1) * (u16)pmlmeext->channel_list.reg_classes
++ + get_reg_classes_full_count(pmlmeext->channel_list);
++
++#ifdef CONFIG_CONCURRENT_MODE
++ if ( check_buddy_fwstate(padapter, _FW_LINKED ) )
++ {
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 5 + 1 );
++ }
++ else
++ {
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( len_channellist_attr );
++ }
++#else
++
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( len_channellist_attr );
++
++#endif
++ p2pielen += 2;
++
++ // Value:
++ // Country String
++ p2pie[ p2pielen++ ] = 'X';
++ p2pie[ p2pielen++ ] = 'X';
++
++ // The third byte should be set to 0x04.
++ // Described in the "Operating Channel Attribute" section.
++ p2pie[ p2pielen++ ] = 0x04;
++
++ // Channel Entry List
++#ifdef CONFIG_CONCURRENT_MODE
++ if ( check_buddy_fwstate(padapter, _FW_LINKED ) )
++ {
++ _adapter *pbuddy_adapter = padapter->pbuddy_adapter;
++ struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv;
++
++ // Operating Class
++ if ( pbuddy_mlmeext->cur_channel > 14 )
++ {
++ if ( pbuddy_mlmeext->cur_channel >= 149 )
++ {
++ p2pie[ p2pielen++ ] = 0x7c;
++ }
++ else
++ {
++ p2pie[ p2pielen++ ] = 0x73;
++ }
++ }
++ else
++ {
++ p2pie[ p2pielen++ ] = 0x51;
++ }
++
++ // Number of Channels
++ // Just support 1 channel and this channel is AP's channel
++ p2pie[ p2pielen++ ] = 1;
++
++ // Channel List
++ p2pie[ p2pielen++ ] = pbuddy_mlmeext->cur_channel;
++ }
++ else
++ {
++ int i, j;
++ for (j = 0; j < pmlmeext->channel_list.reg_classes; j++) {
++ // Operating Class
++ p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class;
++
++ // Number of Channels
++ p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels;
++
++ // Channel List
++ for (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++) {
++ p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i];
++ }
++ }
++ }
++#else // CONFIG_CONCURRENT_MODE
++ {
++ int i, j;
++ for (j = 0; j < pmlmeext->channel_list.reg_classes; j++) {
++ // Operating Class
++ p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class;
++
++ // Number of Channels
++ p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels;
++
++ // Channel List
++ for (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++) {
++ p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i];
++ }
++ }
++ }
++#endif // CONFIG_CONCURRENT_MODE
++ }
++
++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen );
++
++#ifdef CONFIG_WFD
++ wfdielen = build_invitation_resp_wfd_ie(pwdinfo, pframe);
++ pframe += wfdielen;
++ pattrib->pktlen += wfdielen;
++#endif //CONFIG_WFD
++
++ pattrib->last_txcmdsz = pattrib->pktlen;
++
++ dump_mgntframe(padapter, pmgntframe);
++
++ return;
++
++}
++
++void issue_p2p_provision_request(_adapter *padapter, u8* pssid, u8 ussidlen, u8* pdev_raddr )
++{
++ unsigned char category = RTW_WLAN_CATEGORY_PUBLIC;
++ u8 action = P2P_PUB_ACTION_ACTION;
++ u8 dialogToken = 1;
++ u32 p2poui = cpu_to_be32(P2POUI);
++ u8 oui_subtype = P2P_PROVISION_DISC_REQ;
++ u8 wpsie[ 100 ] = { 0x00 };
++ u8 wpsielen = 0;
++ u32 p2pielen = 0;
++#ifdef CONFIG_WFD
++ u32 wfdielen = 0;
++#endif //CONFIG_WFD
++
++ struct xmit_frame *pmgntframe;
++ struct pkt_attrib *pattrib;
++ unsigned char *pframe;
++ struct rtw_ieee80211_hdr *pwlanhdr;
++ unsigned short *fctrl;
++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
++
++
++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL)
++ {
++ return;
++ }
++
++ DBG_871X( "[%s] In\n", __FUNCTION__ );
++ //update attribute
++ pattrib = &pmgntframe->attrib;
++ update_mgntframe_attrib(padapter, pattrib);
++
++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++ fctrl = &(pwlanhdr->frame_ctl);
++ *(fctrl) = 0;
++
++ _rtw_memcpy(pwlanhdr->addr1, pdev_raddr, ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr3, pdev_raddr, ETH_ALEN);
++
++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
++ pmlmeext->mgnt_seq++;
++ SetFrameSubType(pframe, WIFI_ACTION);
++
++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
++ pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++
++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
++ pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));
++ pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen));
++ pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen));
++ pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen));
++
++ p2pielen = build_prov_disc_request_p2p_ie( pwdinfo, pframe, pssid, ussidlen, pdev_raddr );
++
++ pframe += p2pielen;
++ pattrib->pktlen += p2pielen;
++
++ wpsielen = 0;
++ // WPS OUI
++ *(u32*) ( wpsie ) = cpu_to_be32( WPSOUI );
++ wpsielen += 4;
++
++ // WPS version
++ // Type:
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_VER1 );
++ wpsielen += 2;
++
++ // Length:
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0001 );
++ wpsielen += 2;
++
++ // Value:
++ wpsie[wpsielen++] = WPS_VERSION_1; // Version 1.0
++
++ // Config Method
++ // Type:
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_CONF_METHOD );
++ wpsielen += 2;
++
++ // Length:
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0002 );
++ wpsielen += 2;
++
++ // Value:
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( pwdinfo->tx_prov_disc_info.wps_config_method_request );
++ wpsielen += 2;
++
++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen );
++
++
++#ifdef CONFIG_WFD
++ wfdielen = build_provdisc_req_wfd_ie(pwdinfo, pframe);
++ pframe += wfdielen;
++ pattrib->pktlen += wfdielen;
++#endif //CONFIG_WFD
++
++ pattrib->last_txcmdsz = pattrib->pktlen;
++
++ dump_mgntframe(padapter, pmgntframe);
++
++ return;
++
++}
++
++
++u8 is_matched_in_profilelist( u8* peermacaddr, struct profile_info* profileinfo )
++{
++ u8 i, match_result = 0;
++
++ DBG_871X( "[%s] peermac = %.2X %.2X %.2X %.2X %.2X %.2X\n", __FUNCTION__,
++ peermacaddr[0], peermacaddr[1],peermacaddr[2],peermacaddr[3],peermacaddr[4],peermacaddr[5]);
++
++ for( i = 0; i < P2P_MAX_PERSISTENT_GROUP_NUM; i++, profileinfo++ )
++ {
++ DBG_871X( "[%s] profileinfo_mac = %.2X %.2X %.2X %.2X %.2X %.2X\n", __FUNCTION__,
++ profileinfo->peermac[0], profileinfo->peermac[1],profileinfo->peermac[2],profileinfo->peermac[3],profileinfo->peermac[4],profileinfo->peermac[5]);
++ if ( _rtw_memcmp( peermacaddr, profileinfo->peermac, ETH_ALEN ) )
++ {
++ match_result = 1;
++ DBG_871X( "[%s] Match!\n", __FUNCTION__ );
++ break;
++ }
++ }
++
++ return (match_result );
++}
++
++void issue_probersp_p2p(_adapter *padapter, unsigned char *da)
++{
++ struct xmit_frame *pmgntframe;
++ struct pkt_attrib *pattrib;
++ unsigned char *pframe;
++ struct rtw_ieee80211_hdr *pwlanhdr;
++ unsigned short *fctrl;
++ unsigned char *mac;
++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ //WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network);
++ u16 beacon_interval = 100;
++ u16 capInfo = 0;
++ struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
++ u8 wpsie[255] = { 0x00 };
++ u32 wpsielen = 0, p2pielen = 0;
++#ifdef CONFIG_WFD
++ u32 wfdielen = 0;
++#endif //CONFIG_WFD
++#ifdef CONFIG_INTEL_WIDI
++ u8 zero_array_check[L2SDTA_SERVICE_VE_LEN] = { 0x00 };
++#endif //CONFIG_INTEL_WIDI
++
++ //DBG_871X("%s\n", __FUNCTION__);
++
++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL)
++ {
++ return;
++ }
++
++ //update attribute
++ pattrib = &pmgntframe->attrib;
++ update_mgntframe_attrib(padapter, pattrib);
++
++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++ mac = myid(&(padapter->eeprompriv));
++
++ fctrl = &(pwlanhdr->frame_ctl);
++ *(fctrl) = 0;
++ _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN);
++
++ // Use the device address for BSSID field.
++ _rtw_memcpy(pwlanhdr->addr3, mac, ETH_ALEN);
++
++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
++ pmlmeext->mgnt_seq++;
++ SetFrameSubType(fctrl, WIFI_PROBERSP);
++
++ pattrib->hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++ pattrib->pktlen = pattrib->hdrlen;
++ pframe += pattrib->hdrlen;
++
++ //timestamp will be inserted by hardware
++ pframe += 8;
++ pattrib->pktlen += 8;
++
++ // beacon interval: 2 bytes
++ _rtw_memcpy(pframe, (unsigned char *) &beacon_interval, 2);
++ pframe += 2;
++ pattrib->pktlen += 2;
++
++ // capability info: 2 bytes
++ // ESS and IBSS bits must be 0 (defined in the 3.1.2.1.1 of WiFi Direct Spec)
++ capInfo |= cap_ShortPremble;
++ capInfo |= cap_ShortSlot;
++
++ _rtw_memcpy(pframe, (unsigned char *) &capInfo, 2);
++ pframe += 2;
++ pattrib->pktlen += 2;
++
++
++ // SSID
++ pframe = rtw_set_ie(pframe, _SSID_IE_, 7, pwdinfo->p2p_wildcard_ssid, &pattrib->pktlen);
++
++ // supported rates...
++ // Use the OFDM rate in the P2P probe response frame. ( 6(B), 9(B), 12, 18, 24, 36, 48, 54 )
++ pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, 8, pwdinfo->support_rate, &pattrib->pktlen);
++
++ // DS parameter set
++ pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&pwdinfo->listen_channel, &pattrib->pktlen);
++
++#ifdef CONFIG_IOCTL_CFG80211
++ if(wdev_to_priv(padapter->rtw_wdev)->p2p_enabled && pwdinfo->driver_interface == DRIVER_CFG80211 )
++ {
++ if( pmlmepriv->wps_probe_resp_ie != NULL && pmlmepriv->p2p_probe_resp_ie != NULL )
++ {
++ //WPS IE
++ _rtw_memcpy(pframe, pmlmepriv->wps_probe_resp_ie, pmlmepriv->wps_probe_resp_ie_len);
++ pattrib->pktlen += pmlmepriv->wps_probe_resp_ie_len;
++ pframe += pmlmepriv->wps_probe_resp_ie_len;
++
++ //P2P IE
++ _rtw_memcpy(pframe, pmlmepriv->p2p_probe_resp_ie, pmlmepriv->p2p_probe_resp_ie_len);
++ pattrib->pktlen += pmlmepriv->p2p_probe_resp_ie_len;
++ pframe += pmlmepriv->p2p_probe_resp_ie_len;
++ }
++ }
++ else
++#endif //CONFIG_IOCTL_CFG80211
++ {
++
++ // Todo: WPS IE
++ // Noted by Albert 20100907
++ // According to the WPS specification, all the WPS attribute is presented by Big Endian.
++
++ wpsielen = 0;
++ // WPS OUI
++ *(u32*) ( wpsie ) = cpu_to_be32( WPSOUI );
++ wpsielen += 4;
++
++ // WPS version
++ // Type:
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_VER1 );
++ wpsielen += 2;
++
++ // Length:
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0001 );
++ wpsielen += 2;
++
++ // Value:
++ wpsie[wpsielen++] = WPS_VERSION_1; // Version 1.0
++
++#ifdef CONFIG_INTEL_WIDI
++ // Commented by Kurt
++ // Appended WiDi info. only if we did issued_probereq_widi(), and then we saved ven. ext. in pmlmepriv->sa_ext.
++ if( _rtw_memcmp(pmlmepriv->sa_ext, zero_array_check, L2SDTA_SERVICE_VE_LEN) == _FALSE
++ || pmlmepriv->num_p2p_sdt != 0 )
++ {
++ //Sec dev type
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_SEC_DEV_TYPE_LIST );
++ wpsielen += 2;
++
++ // Length:
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0008 );
++ wpsielen += 2;
++
++ // Value:
++ // Category ID
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_PDT_CID_DISPLAYS );
++ wpsielen += 2;
++
++ // OUI
++ *(u32*) ( wpsie + wpsielen ) = cpu_to_be32( INTEL_DEV_TYPE_OUI );
++ wpsielen += 4;
++
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_PDT_SCID_WIDI_CONSUMER_SINK );
++ wpsielen += 2;
++
++ if( _rtw_memcmp(pmlmepriv->sa_ext, zero_array_check, L2SDTA_SERVICE_VE_LEN) == _FALSE )
++ {
++ // Vendor Extension
++ _rtw_memcpy( wpsie + wpsielen, pmlmepriv->sa_ext, L2SDTA_SERVICE_VE_LEN );
++ wpsielen += L2SDTA_SERVICE_VE_LEN;
++ }
++ }
++#endif //CONFIG_INTEL_WIDI
++
++ // WiFi Simple Config State
++ // Type:
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_SIMPLE_CONF_STATE );
++ wpsielen += 2;
++
++ // Length:
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0001 );
++ wpsielen += 2;
++
++ // Value:
++ wpsie[wpsielen++] = WPS_WSC_STATE_NOT_CONFIG; // Not Configured.
++
++ // Response Type
++ // Type:
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_RESP_TYPE );
++ wpsielen += 2;
++
++ // Length:
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0001 );
++ wpsielen += 2;
++
++ // Value:
++ wpsie[wpsielen++] = WPS_RESPONSE_TYPE_8021X;
++
++ // UUID-E
++ // Type:
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_UUID_E );
++ wpsielen += 2;
++
++ // Length:
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0010 );
++ wpsielen += 2;
++
++ // Value:
++ if (pwdinfo->external_uuid == 0) {
++ _rtw_memset( wpsie + wpsielen, 0x0, 16 );
++ _rtw_memcpy( wpsie + wpsielen, myid( &padapter->eeprompriv ), ETH_ALEN );
++ } else {
++ _rtw_memcpy( wpsie + wpsielen, pwdinfo->uuid, 0x10 );
++ }
++ wpsielen += 0x10;
++
++ // Manufacturer
++ // Type:
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_MANUFACTURER );
++ wpsielen += 2;
++
++ // Length:
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0007 );
++ wpsielen += 2;
++
++ // Value:
++ _rtw_memcpy( wpsie + wpsielen, "Realtek", 7 );
++ wpsielen += 7;
++
++ // Model Name
++ // Type:
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_MODEL_NAME );
++ wpsielen += 2;
++
++ // Length:
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0006 );
++ wpsielen += 2;
++
++ // Value:
++ _rtw_memcpy( wpsie + wpsielen, "8192CU", 6 );
++ wpsielen += 6;
++
++ // Model Number
++ // Type:
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_MODEL_NUMBER );
++ wpsielen += 2;
++
++ // Length:
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0001 );
++ wpsielen += 2;
++
++ // Value:
++ wpsie[ wpsielen++ ] = 0x31; // character 1
++
++ // Serial Number
++ // Type:
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_SERIAL_NUMBER );
++ wpsielen += 2;
++
++ // Length:
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( ETH_ALEN );
++ wpsielen += 2;
++
++ // Value:
++ _rtw_memcpy( wpsie + wpsielen, "123456" , ETH_ALEN );
++ wpsielen += ETH_ALEN;
++
++ // Primary Device Type
++ // Type:
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_PRIMARY_DEV_TYPE );
++ wpsielen += 2;
++
++ // Length:
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0008 );
++ wpsielen += 2;
++
++ // Value:
++ // Category ID
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_PDT_CID_RTK_WIDI );
++ wpsielen += 2;
++
++ // OUI
++ *(u32*) ( wpsie + wpsielen ) = cpu_to_be32( WPSOUI );
++ wpsielen += 4;
++
++ // Sub Category ID
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_PDT_SCID_RTK_DMP );
++ wpsielen += 2;
++
++ // Device Name
++ // Type:
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_DEVICE_NAME );
++ wpsielen += 2;
++
++ // Length:
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( pwdinfo->device_name_len );
++ wpsielen += 2;
++
++ // Value:
++ _rtw_memcpy( wpsie + wpsielen, pwdinfo->device_name, pwdinfo->device_name_len );
++ wpsielen += pwdinfo->device_name_len;
++
++ // Config Method
++ // Type:
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_CONF_METHOD );
++ wpsielen += 2;
++
++ // Length:
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0002 );
++ wpsielen += 2;
++
++ // Value:
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( pwdinfo->supported_wps_cm );
++ wpsielen += 2;
++
++
++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen );
++
++
++ p2pielen = build_probe_resp_p2p_ie(pwdinfo, pframe);
++ pframe += p2pielen;
++ pattrib->pktlen += p2pielen;
++ }
++
++#ifdef CONFIG_WFD
++#ifdef CONFIG_IOCTL_CFG80211
++ if ( _TRUE == pwdinfo->wfd_info->wfd_enable )
++#endif //CONFIG_IOCTL_CFG80211
++ {
++ wfdielen = build_probe_resp_wfd_ie(pwdinfo, pframe, 0);
++ pframe += wfdielen;
++ pattrib->pktlen += wfdielen;
++ }
++#ifdef CONFIG_IOCTL_CFG80211
++ else if (pmlmepriv->wfd_probe_resp_ie != NULL && pmlmepriv->wfd_probe_resp_ie_len>0)
++ {
++ //WFD IE
++ _rtw_memcpy(pframe, pmlmepriv->wfd_probe_resp_ie, pmlmepriv->wfd_probe_resp_ie_len);
++ pattrib->pktlen += pmlmepriv->wfd_probe_resp_ie_len;
++ pframe += pmlmepriv->wfd_probe_resp_ie_len;
++ }
++#endif //CONFIG_IOCTL_CFG80211
++#endif //CONFIG_WFD
++
++ pattrib->last_txcmdsz = pattrib->pktlen;
++
++
++ dump_mgntframe(padapter, pmgntframe);
++
++ return;
++
++}
++
++int _issue_probereq_p2p(_adapter *padapter, u8 *da, int wait_ack)
++{
++ int ret = _FAIL;
++ struct xmit_frame *pmgntframe;
++ struct pkt_attrib *pattrib;
++ unsigned char *pframe;
++ struct rtw_ieee80211_hdr *pwlanhdr;
++ unsigned short *fctrl;
++ unsigned char *mac;
++ unsigned char bssrate[NumRates];
++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ int bssrate_len = 0;
++ u8 bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
++ struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
++ u8 wpsie[255] = { 0x00 }, p2pie[ 255 ] = { 0x00 };
++ u16 wpsielen = 0, p2pielen = 0;
++#ifdef CONFIG_WFD
++ u32 wfdielen = 0;
++#endif //CONFIG_WFD
++
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++
++
++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL)
++ {
++ goto exit;
++ }
++
++ //update attribute
++ pattrib = &pmgntframe->attrib;
++ update_mgntframe_attrib(padapter, pattrib);
++
++
++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++ mac = myid(&(padapter->eeprompriv));
++
++ fctrl = &(pwlanhdr->frame_ctl);
++ *(fctrl) = 0;
++
++ if (da) {
++ _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr3, da, ETH_ALEN);
++ } else {
++ if ( ( pwdinfo->p2p_info.scan_op_ch_only ) || ( pwdinfo->rx_invitereq_info.scan_op_ch_only ) )
++ {
++ // This two flags will be set when this is only the P2P client mode.
++ _rtw_memcpy(pwlanhdr->addr1, pwdinfo->p2p_peer_interface_addr, ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr3, pwdinfo->p2p_peer_interface_addr, ETH_ALEN);
++ }
++ else
++ {
++ // broadcast probe request frame
++ _rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr3, bc_addr, ETH_ALEN);
++ }
++ }
++ _rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN);
++
++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
++ pmlmeext->mgnt_seq++;
++ SetFrameSubType(pframe, WIFI_PROBEREQ);
++
++ pframe += sizeof (struct rtw_ieee80211_hdr_3addr);
++ pattrib->pktlen = sizeof (struct rtw_ieee80211_hdr_3addr);
++
++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_PROVISION_DIS_REQ))
++ {
++ pframe = rtw_set_ie(pframe, _SSID_IE_, pwdinfo->tx_prov_disc_info.ssid.SsidLength, pwdinfo->tx_prov_disc_info.ssid.Ssid, &(pattrib->pktlen));
++ }
++ else
++ {
++ pframe = rtw_set_ie(pframe, _SSID_IE_, P2P_WILDCARD_SSID_LEN, pwdinfo->p2p_wildcard_ssid, &(pattrib->pktlen));
++ }
++ // Use the OFDM rate in the P2P probe request frame. ( 6(B), 9(B), 12(B), 24(B), 36, 48, 54 )
++ pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, 8, pwdinfo->support_rate, &pattrib->pktlen);
++
++#ifdef CONFIG_IOCTL_CFG80211
++ if(wdev_to_priv(padapter->rtw_wdev)->p2p_enabled && pwdinfo->driver_interface == DRIVER_CFG80211 )
++ {
++ if( pmlmepriv->wps_probe_req_ie != NULL && pmlmepriv->p2p_probe_req_ie != NULL )
++ {
++ //WPS IE
++ _rtw_memcpy(pframe, pmlmepriv->wps_probe_req_ie, pmlmepriv->wps_probe_req_ie_len);
++ pattrib->pktlen += pmlmepriv->wps_probe_req_ie_len;
++ pframe += pmlmepriv->wps_probe_req_ie_len;
++
++ //P2P IE
++ _rtw_memcpy(pframe, pmlmepriv->p2p_probe_req_ie, pmlmepriv->p2p_probe_req_ie_len);
++ pattrib->pktlen += pmlmepriv->p2p_probe_req_ie_len;
++ pframe += pmlmepriv->p2p_probe_req_ie_len;
++ }
++ }
++ else
++#endif //CONFIG_IOCTL_CFG80211
++ {
++
++ // WPS IE
++ // Noted by Albert 20110221
++ // According to the WPS specification, all the WPS attribute is presented by Big Endian.
++
++ wpsielen = 0;
++ // WPS OUI
++ *(u32*) ( wpsie ) = cpu_to_be32( WPSOUI );
++ wpsielen += 4;
++
++ // WPS version
++ // Type:
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_VER1 );
++ wpsielen += 2;
++
++ // Length:
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0001 );
++ wpsielen += 2;
++
++ // Value:
++ wpsie[wpsielen++] = WPS_VERSION_1; // Version 1.0
++
++ if( pmlmepriv->wps_probe_req_ie == NULL )
++ {
++ // UUID-E
++ // Type:
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_UUID_E );
++ wpsielen += 2;
++
++ // Length:
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0010 );
++ wpsielen += 2;
++
++ // Value:
++ if (pwdinfo->external_uuid == 0) {
++ _rtw_memset( wpsie + wpsielen, 0x0, 16 );
++ _rtw_memcpy( wpsie + wpsielen, myid( &padapter->eeprompriv ), ETH_ALEN );
++ } else {
++ _rtw_memcpy( wpsie + wpsielen, pwdinfo->uuid, 0x10 );
++ }
++ wpsielen += 0x10;
++
++ // Config Method
++ // Type:
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_CONF_METHOD );
++ wpsielen += 2;
++
++ // Length:
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0002 );
++ wpsielen += 2;
++
++ // Value:
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( pwdinfo->supported_wps_cm );
++ wpsielen += 2;
++ }
++
++ // Device Name
++ // Type:
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_DEVICE_NAME );
++ wpsielen += 2;
++
++ // Length:
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( pwdinfo->device_name_len );
++ wpsielen += 2;
++
++ // Value:
++ _rtw_memcpy( wpsie + wpsielen, pwdinfo->device_name, pwdinfo->device_name_len );
++ wpsielen += pwdinfo->device_name_len;
++
++ // Primary Device Type
++ // Type:
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_PRIMARY_DEV_TYPE );
++ wpsielen += 2;
++
++ // Length:
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0008 );
++ wpsielen += 2;
++
++ // Value:
++ // Category ID
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_PDT_CID_MULIT_MEDIA );
++ wpsielen += 2;
++
++ // OUI
++ *(u32*) ( wpsie + wpsielen ) = cpu_to_be32( WPSOUI );
++ wpsielen += 4;
++
++ // Sub Category ID
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_PDT_SCID_MEDIA_SERVER );
++ wpsielen += 2;
++
++ // Device Password ID
++ // Type:
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_DEVICE_PWID );
++ wpsielen += 2;
++
++ // Length:
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0002 );
++ wpsielen += 2;
++
++ // Value:
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_DPID_REGISTRAR_SPEC ); // Registrar-specified
++ wpsielen += 2;
++
++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen );
++
++ // P2P OUI
++ p2pielen = 0;
++ p2pie[ p2pielen++ ] = 0x50;
++ p2pie[ p2pielen++ ] = 0x6F;
++ p2pie[ p2pielen++ ] = 0x9A;
++ p2pie[ p2pielen++ ] = 0x09; // WFA P2P v1.0
++
++ // Commented by Albert 20110221
++ // According to the P2P Specification, the probe request frame should contain 5 P2P attributes
++ // 1. P2P Capability
++ // 2. P2P Device ID if this probe request wants to find the specific P2P device
++ // 3. Listen Channel
++ // 4. Extended Listen Timing
++ // 5. Operating Channel if this WiFi is working as the group owner now
++
++ // P2P Capability
++ // Type:
++ p2pie[ p2pielen++ ] = P2P_ATTR_CAPABILITY;
++
++ // Length:
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0002 );
++ p2pielen += 2;
++
++ // Value:
++ // Device Capability Bitmap, 1 byte
++ p2pie[ p2pielen++ ] = DMP_P2P_DEVCAP_SUPPORT;
++
++ // Group Capability Bitmap, 1 byte
++ if ( pwdinfo->persistent_supported )
++ p2pie[ p2pielen++ ] = P2P_GRPCAP_PERSISTENT_GROUP | DMP_P2P_GRPCAP_SUPPORT;
++ else
++ p2pie[ p2pielen++ ] = DMP_P2P_GRPCAP_SUPPORT;
++
++ // Listen Channel
++ // Type:
++ p2pie[ p2pielen++ ] = P2P_ATTR_LISTEN_CH;
++
++ // Length:
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0005 );
++ p2pielen += 2;
++
++ // Value:
++ // Country String
++ p2pie[ p2pielen++ ] = 'X';
++ p2pie[ p2pielen++ ] = 'X';
++
++ // The third byte should be set to 0x04.
++ // Described in the "Operating Channel Attribute" section.
++ p2pie[ p2pielen++ ] = 0x04;
++
++ // Operating Class
++ p2pie[ p2pielen++ ] = 0x51; // Copy from SD7
++
++ // Channel Number
++ p2pie[ p2pielen++ ] = pwdinfo->listen_channel; // listen channel
++
++
++ // Extended Listen Timing
++ // Type:
++ p2pie[ p2pielen++ ] = P2P_ATTR_EX_LISTEN_TIMING;
++
++ // Length:
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0004 );
++ p2pielen += 2;
++
++ // Value:
++ // Availability Period
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0xFFFF );
++ p2pielen += 2;
++
++ // Availability Interval
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0xFFFF );
++ p2pielen += 2;
++
++ if ( rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO) )
++ {
++ // Operating Channel (if this WiFi is working as the group owner now)
++ // Type:
++ p2pie[ p2pielen++ ] = P2P_ATTR_OPERATING_CH;
++
++ // Length:
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0005 );
++ p2pielen += 2;
++
++ // Value:
++ // Country String
++ p2pie[ p2pielen++ ] = 'X';
++ p2pie[ p2pielen++ ] = 'X';
++
++ // The third byte should be set to 0x04.
++ // Described in the "Operating Channel Attribute" section.
++ p2pie[ p2pielen++ ] = 0x04;
++
++ // Operating Class
++ p2pie[ p2pielen++ ] = 0x51; // Copy from SD7
++
++ // Channel Number
++ p2pie[ p2pielen++ ] = pwdinfo->operating_channel; // operating channel number
++
++ }
++
++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen );
++
++ if( pmlmepriv->wps_probe_req_ie != NULL )
++ {
++ //WPS IE
++ _rtw_memcpy(pframe, pmlmepriv->wps_probe_req_ie, pmlmepriv->wps_probe_req_ie_len);
++ pattrib->pktlen += pmlmepriv->wps_probe_req_ie_len;
++ pframe += pmlmepriv->wps_probe_req_ie_len;
++ }
++ }
++
++#ifdef CONFIG_WFD
++#ifdef CONFIG_IOCTL_CFG80211
++ if ( _TRUE == pwdinfo->wfd_info->wfd_enable )
++#endif
++ {
++ wfdielen = build_probe_req_wfd_ie(pwdinfo, pframe);
++ pframe += wfdielen;
++ pattrib->pktlen += wfdielen;
++ }
++#ifdef CONFIG_IOCTL_CFG80211
++ else if (pmlmepriv->wfd_probe_req_ie != NULL && pmlmepriv->wfd_probe_req_ie_len>0)
++ {
++ //WFD IE
++ _rtw_memcpy(pframe, pmlmepriv->wfd_probe_req_ie, pmlmepriv->wfd_probe_req_ie_len);
++ pattrib->pktlen += pmlmepriv->wfd_probe_req_ie_len;
++ pframe += pmlmepriv->wfd_probe_req_ie_len;
++ }
++#endif //CONFIG_IOCTL_CFG80211
++#endif //CONFIG_WFD
++
++ pattrib->last_txcmdsz = pattrib->pktlen;
++
++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("issuing probe_req, tx_len=%d\n", pattrib->last_txcmdsz));
++
++ if (wait_ack) {
++ ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe);
++ } else {
++ dump_mgntframe(padapter, pmgntframe);
++ ret = _SUCCESS;
++ }
++
++exit:
++ return ret;
++}
++
++inline void issue_probereq_p2p(_adapter *adapter, u8 *da)
++{
++ _issue_probereq_p2p(adapter, da, _FALSE);
++}
++
++int issue_probereq_p2p_ex(_adapter *adapter, u8 *da, int try_cnt, int wait_ms)
++{
++ int ret;
++ int i = 0;
++ u32 start = rtw_get_current_time();
++
++ do
++ {
++ ret = _issue_probereq_p2p(adapter, da, wait_ms>0?_TRUE:_FALSE);
++
++ i++;
++
++ if (adapter->bDriverStopped || adapter->bSurpriseRemoved)
++ break;
++
++ if(i < try_cnt && wait_ms > 0 && ret==_FAIL)
++ rtw_msleep_os(wait_ms);
++
++ }while((i<try_cnt) && ((ret==_FAIL)||(wait_ms==0)));
++
++ if (ret != _FAIL) {
++ ret = _SUCCESS;
++ #ifndef DBG_XMIT_ACK
++ goto exit;
++ #endif
++ }
++
++ if (try_cnt && wait_ms) {
++ if (da)
++ DBG_871X(FUNC_ADPT_FMT" to "MAC_FMT", ch:%u%s, %d/%d in %u ms\n",
++ FUNC_ADPT_ARG(adapter), MAC_ARG(da), rtw_get_oper_ch(adapter),
++ ret==_SUCCESS?", acked":"", i, try_cnt, rtw_get_passing_time_ms(start));
++ else
++ DBG_871X(FUNC_ADPT_FMT", ch:%u%s, %d/%d in %u ms\n",
++ FUNC_ADPT_ARG(adapter), rtw_get_oper_ch(adapter),
++ ret==_SUCCESS?", acked":"", i, try_cnt, rtw_get_passing_time_ms(start));
++ }
++exit:
++ return ret;
++}
++
++#endif //CONFIG_P2P
++
++s32 rtw_action_public_decache(union recv_frame *recv_frame, s32 token)
++{
++ _adapter *adapter = recv_frame->u.hdr.adapter;
++ struct mlme_ext_priv *mlmeext = &(adapter->mlmeextpriv);
++ u8 *frame = recv_frame->u.hdr.rx_data;
++ u16 seq_ctrl = ( (recv_frame->u.hdr.attrib.seq_num&0xffff) << 4) |
++ (recv_frame->u.hdr.attrib.frag_num & 0xf);
++
++ if (GetRetry(frame)) {
++ if (token >= 0) {
++ if ((seq_ctrl == mlmeext->action_public_rxseq)
++ && (token == mlmeext->action_public_dialog_token))
++ {
++ DBG_871X(FUNC_ADPT_FMT" seq_ctrl=0x%x, rxseq=0x%x, token:%d\n",
++ FUNC_ADPT_ARG(adapter), seq_ctrl, mlmeext->action_public_rxseq, token);
++ return _FAIL;
++ }
++ } else {
++ if (seq_ctrl == mlmeext->action_public_rxseq) {
++ DBG_871X(FUNC_ADPT_FMT" seq_ctrl=0x%x, rxseq=0x%x\n",
++ FUNC_ADPT_ARG(adapter), seq_ctrl, mlmeext->action_public_rxseq);
++ return _FAIL;
++ }
++ }
++ }
++
++ mlmeext->action_public_rxseq = seq_ctrl;
++
++ if (token >= 0)
++ mlmeext->action_public_dialog_token = token;
++
++ return _SUCCESS;
++}
++
++unsigned int on_action_public_p2p(union recv_frame *precv_frame)
++{
++ _adapter *padapter = precv_frame->u.hdr.adapter;
++ u8 *pframe = precv_frame->u.hdr.rx_data;
++ uint len = precv_frame->u.hdr.len;
++ u8 *frame_body;
++ u8 dialogToken=0;
++#ifdef CONFIG_P2P
++ u8 *p2p_ie;
++ u32 p2p_ielen, wps_ielen;
++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo );
++ u8 result = P2P_STATUS_SUCCESS;
++ u8 empty_addr[ETH_ALEN] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
++ u8 *merged_p2pie = NULL;
++ u32 merged_p2p_ielen = 0;
++#endif //CONFIG_P2P
++
++ frame_body = (unsigned char *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr));
++
++ dialogToken = frame_body[7];
++
++ if (rtw_action_public_decache(precv_frame, dialogToken) == _FAIL)
++ return _FAIL;
++
++#ifdef CONFIG_P2P
++ _cancel_timer_ex( &pwdinfo->reset_ch_sitesurvey );
++#ifdef CONFIG_IOCTL_CFG80211
++ if(wdev_to_priv(padapter->rtw_wdev)->p2p_enabled && pwdinfo->driver_interface == DRIVER_CFG80211)
++ {
++ rtw_cfg80211_rx_p2p_action_public(padapter, pframe, len);
++ }
++ else
++#endif //CONFIG_IOCTL_CFG80211
++ {
++ // Do nothing if the driver doesn't enable the P2P function.
++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) || rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE))
++ return _SUCCESS;
++
++ len -= sizeof(struct rtw_ieee80211_hdr_3addr);
++
++ switch( frame_body[ 6 ] )//OUI Subtype
++ {
++ case P2P_GO_NEGO_REQ:
++ {
++ DBG_871X( "[%s] Got GO Nego Req Frame\n", __FUNCTION__);
++ _rtw_memset( &pwdinfo->groupid_info, 0x00, sizeof( struct group_id_info ) );
++
++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_RX_PROVISION_DIS_REQ))
++ {
++ rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo));
++ }
++
++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_FAIL))
++ {
++ // Commented by Albert 20110526
++ // In this case, this means the previous nego fail doesn't be reset yet.
++ _cancel_timer_ex( &pwdinfo->restore_p2p_state_timer );
++ // Restore the previous p2p state
++ rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo));
++ DBG_871X( "[%s] Restore the previous p2p state to %d\n", __FUNCTION__, rtw_p2p_state(pwdinfo) );
++ }
++#ifdef CONFIG_CONCURRENT_MODE
++ if ( check_buddy_fwstate(padapter, _FW_LINKED ) )
++ {
++ _cancel_timer_ex( &pwdinfo->ap_p2p_switch_timer );
++ }
++#endif // CONFIG_CONCURRENT_MODE
++
++ // Commented by Kurt 20110902
++ //Add if statement to avoid receiving duplicate prov disc req. such that pre_p2p_state would be covered.
++ if(!rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING))
++ rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo));
++
++ // Commented by Kurt 20120113
++ // Get peer_dev_addr here if peer doesn't issue prov_disc frame.
++ if( _rtw_memcmp(pwdinfo->rx_prov_disc_info.peerDevAddr, empty_addr, ETH_ALEN) );
++ _rtw_memcpy(pwdinfo->rx_prov_disc_info.peerDevAddr, GetAddr2Ptr(pframe), ETH_ALEN);
++
++ result = process_p2p_group_negotation_req( pwdinfo, frame_body, len );
++ issue_p2p_GO_response( padapter, GetAddr2Ptr(pframe), frame_body, len, result );
++#ifdef CONFIG_INTEL_WIDI
++ if( (padapter->mlmepriv.widi_state == INTEL_WIDI_STATE_LISTEN) && (padapter->mlmepriv.widi_state != INTEL_WIDI_STATE_WFD_CONNECTION) )
++ {
++ padapter->mlmepriv.widi_state = INTEL_WIDI_STATE_WFD_CONNECTION;
++ _cancel_timer_ex(&(padapter->mlmepriv.listen_timer));
++ intel_widi_wk_cmd(padapter, INTEL_WIDI_LISTEN_STOP_WK, NULL);
++ }
++#endif //CONFIG_INTEL_WIDI
++
++ // Commented by Albert 20110718
++ // No matter negotiating or negotiation failure, the driver should set up the restore P2P state timer.
++#ifdef CONFIG_CONCURRENT_MODE
++ // Commented by Albert 20120107
++ _set_timer( &pwdinfo->restore_p2p_state_timer, 3000 );
++#else // CONFIG_CONCURRENT_MODE
++ _set_timer( &pwdinfo->restore_p2p_state_timer, 5000 );
++#endif // CONFIG_CONCURRENT_MODE
++ break;
++ }
++ case P2P_GO_NEGO_RESP:
++ {
++ DBG_871X( "[%s] Got GO Nego Resp Frame\n", __FUNCTION__);
++
++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING))
++ {
++ // Commented by Albert 20110425
++ // The restore timer is enabled when issuing the nego request frame of rtw_p2p_connect function.
++ _cancel_timer_ex( &pwdinfo->restore_p2p_state_timer );
++ pwdinfo->nego_req_info.benable = _FALSE;
++ result = process_p2p_group_negotation_resp( pwdinfo, frame_body, len);
++ issue_p2p_GO_confirm( pwdinfo->padapter, GetAddr2Ptr(pframe), result);
++ if ( P2P_STATUS_SUCCESS == result )
++ {
++ if ( rtw_p2p_role(pwdinfo) == P2P_ROLE_CLIENT )
++ {
++ pwdinfo->p2p_info.operation_ch[ 0 ] = pwdinfo->peer_operating_ch;
++ #ifdef P2P_OP_CHECK_SOCIAL_CH
++ pwdinfo->p2p_info.operation_ch[ 1 ] = 1; //Check whether GO is operating in channel 1;
++ pwdinfo->p2p_info.operation_ch[ 2 ] = 6; //Check whether GO is operating in channel 6;
++ pwdinfo->p2p_info.operation_ch[ 3 ] = 11; //Check whether GO is operating in channel 11;
++ #endif //P2P_OP_CHECK_SOCIAL_CH
++ pwdinfo->p2p_info.scan_op_ch_only = 1;
++ _set_timer( &pwdinfo->reset_ch_sitesurvey2, P2P_RESET_SCAN_CH );
++ }
++ }
++
++ // Reset the dialog token for group negotiation frames.
++ pwdinfo->negotiation_dialog_token = 1;
++
++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_FAIL))
++ {
++ _set_timer( &pwdinfo->restore_p2p_state_timer, 5000 );
++ }
++ }
++ else
++ {
++ DBG_871X( "[%s] Skipped GO Nego Resp Frame (p2p_state != P2P_STATE_GONEGO_ING)\n", __FUNCTION__);
++ }
++
++ break;
++ }
++ case P2P_GO_NEGO_CONF:
++ {
++ DBG_871X( "[%s] Got GO Nego Confirm Frame\n", __FUNCTION__);
++ result = process_p2p_group_negotation_confirm( pwdinfo, frame_body, len);
++ if ( P2P_STATUS_SUCCESS == result )
++ {
++ if ( rtw_p2p_role(pwdinfo) == P2P_ROLE_CLIENT )
++ {
++ pwdinfo->p2p_info.operation_ch[ 0 ] = pwdinfo->peer_operating_ch;
++ #ifdef P2P_OP_CHECK_SOCIAL_CH
++ pwdinfo->p2p_info.operation_ch[ 1 ] = 1; //Check whether GO is operating in channel 1;
++ pwdinfo->p2p_info.operation_ch[ 2 ] = 6; //Check whether GO is operating in channel 6;
++ pwdinfo->p2p_info.operation_ch[ 3 ] = 11; //Check whether GO is operating in channel 11;
++ #endif //P2P_OP_CHECK_SOCIAL_CH
++ pwdinfo->p2p_info.scan_op_ch_only = 1;
++ _set_timer( &pwdinfo->reset_ch_sitesurvey2, P2P_RESET_SCAN_CH );
++ }
++ }
++ break;
++ }
++ case P2P_INVIT_REQ:
++ {
++ // Added by Albert 2010/10/05
++ // Received the P2P Invite Request frame.
++
++ DBG_871X( "[%s] Got invite request frame!\n", __FUNCTION__ );
++ if ( (p2p_ie=rtw_get_p2p_ie( frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, NULL, &p2p_ielen)) )
++ {
++ // Parse the necessary information from the P2P Invitation Request frame.
++ // For example: The MAC address of sending this P2P Invitation Request frame.
++ u32 attr_contentlen = 0;
++ u8 status_code = P2P_STATUS_FAIL_INFO_UNAVAILABLE;
++ struct group_id_info group_id;
++ u8 invitation_flag = 0;
++
++ merged_p2p_ielen = rtw_get_p2p_merged_ies_len(frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_);
++
++ merged_p2pie = rtw_malloc(merged_p2p_ielen);
++ if (merged_p2pie == NULL)
++ {
++ DBG_871X( "[%s] Malloc p2p ie fail\n", __FUNCTION__);
++ goto exit;
++ }
++ _rtw_memset(merged_p2pie, 0x00, merged_p2p_ielen);
++
++ merged_p2p_ielen = rtw_p2p_merge_ies(frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, merged_p2pie);
++
++ rtw_get_p2p_attr_content( merged_p2pie, merged_p2p_ielen, P2P_ATTR_INVITATION_FLAGS, &invitation_flag, &attr_contentlen);
++ if ( attr_contentlen )
++ {
++
++ rtw_get_p2p_attr_content( merged_p2pie, merged_p2p_ielen, P2P_ATTR_GROUP_BSSID, pwdinfo->p2p_peer_interface_addr, &attr_contentlen);
++ // Commented by Albert 20120510
++ // Copy to the pwdinfo->p2p_peer_interface_addr.
++ // So that the WFD UI ( or Sigma ) can get the peer interface address by using the following command.
++ // #> iwpriv wlan0 p2p_get peer_ifa
++ // After having the peer interface address, the sigma can find the correct conf file for wpa_supplicant.
++
++ if ( attr_contentlen )
++ {
++ DBG_871X( "[%s] GO's BSSID = %.2X %.2X %.2X %.2X %.2X %.2X\n", __FUNCTION__,
++ pwdinfo->p2p_peer_interface_addr[0], pwdinfo->p2p_peer_interface_addr[1],
++ pwdinfo->p2p_peer_interface_addr[2], pwdinfo->p2p_peer_interface_addr[3],
++ pwdinfo->p2p_peer_interface_addr[4], pwdinfo->p2p_peer_interface_addr[5] );
++ }
++
++ if ( invitation_flag & P2P_INVITATION_FLAGS_PERSISTENT )
++ {
++ // Re-invoke the persistent group.
++
++ _rtw_memset( &group_id, 0x00, sizeof( struct group_id_info ) );
++ rtw_get_p2p_attr_content( merged_p2pie, merged_p2p_ielen, P2P_ATTR_GROUP_ID, ( u8* ) &group_id, &attr_contentlen);
++ if ( attr_contentlen )
++ {
++ if ( _rtw_memcmp( group_id.go_device_addr, myid( &padapter->eeprompriv ), ETH_ALEN ) )
++ {
++ // The p2p device sending this p2p invitation request wants this Wi-Fi device to be the persistent GO.
++ rtw_p2p_set_state(pwdinfo, P2P_STATE_RECV_INVITE_REQ_GO );
++ rtw_p2p_set_role( pwdinfo, P2P_ROLE_GO );
++ status_code = P2P_STATUS_SUCCESS;
++ }
++ else
++ {
++ // The p2p device sending this p2p invitation request wants to be the persistent GO.
++ if ( is_matched_in_profilelist( pwdinfo->p2p_peer_interface_addr, &pwdinfo->profileinfo[ 0 ] ) )
++ {
++ u8 operatingch_info[5] = { 0x00 };
++
++ if ( rtw_get_p2p_attr_content(merged_p2pie, merged_p2p_ielen, P2P_ATTR_OPERATING_CH, operatingch_info, &attr_contentlen) )
++ {
++ if( rtw_ch_set_search_ch(padapter->mlmeextpriv.channel_set, (u32)operatingch_info[4] ) >= 0 )
++ {
++ // The operating channel is acceptable for this device.
++ pwdinfo->rx_invitereq_info.operation_ch[0]= operatingch_info[4];
++ #ifdef P2P_OP_CHECK_SOCIAL_CH
++ pwdinfo->rx_invitereq_info.operation_ch[1]= 1; //Check whether GO is operating in channel 1;
++ pwdinfo->rx_invitereq_info.operation_ch[2]= 6; //Check whether GO is operating in channel 6;
++ pwdinfo->rx_invitereq_info.operation_ch[3]= 11; //Check whether GO is operating in channel 11;
++ #endif //P2P_OP_CHECK_SOCIAL_CH
++ pwdinfo->rx_invitereq_info.scan_op_ch_only = 1;
++ _set_timer( &pwdinfo->reset_ch_sitesurvey, P2P_RESET_SCAN_CH );
++ rtw_p2p_set_state(pwdinfo, P2P_STATE_RECV_INVITE_REQ_MATCH );
++ rtw_p2p_set_role( pwdinfo, P2P_ROLE_CLIENT );
++ status_code = P2P_STATUS_SUCCESS;
++ }
++ else
++ {
++ // The operating channel isn't supported by this device.
++ rtw_p2p_set_state(pwdinfo, P2P_STATE_RECV_INVITE_REQ_DISMATCH );
++ rtw_p2p_set_role( pwdinfo, P2P_ROLE_DEVICE );
++ status_code = P2P_STATUS_FAIL_NO_COMMON_CH;
++ _set_timer( &pwdinfo->restore_p2p_state_timer, 3000 );
++ }
++ }
++ else
++ {
++ // Commented by Albert 20121130
++ // Intel will use the different P2P IE to store the operating channel information
++ // Workaround for Intel WiDi 3.5
++ rtw_p2p_set_state(pwdinfo, P2P_STATE_RECV_INVITE_REQ_MATCH );
++ rtw_p2p_set_role( pwdinfo, P2P_ROLE_CLIENT );
++ status_code = P2P_STATUS_SUCCESS;
++ }
++ }
++ else
++ {
++ rtw_p2p_set_state(pwdinfo, P2P_STATE_RECV_INVITE_REQ_DISMATCH );
++ #ifdef CONFIG_INTEL_WIDI
++ _rtw_memcpy( pwdinfo->p2p_peer_device_addr, group_id.go_device_addr , ETH_ALEN );
++ rtw_p2p_set_role( pwdinfo, P2P_ROLE_CLIENT );
++ #endif //CONFIG_INTEL_WIDI
++
++ status_code = P2P_STATUS_FAIL_UNKNOWN_P2PGROUP;
++ }
++ }
++ }
++ else
++ {
++ DBG_871X( "[%s] P2P Group ID Attribute NOT FOUND!\n", __FUNCTION__ );
++ status_code = P2P_STATUS_FAIL_INFO_UNAVAILABLE;
++ }
++ }
++ else
++ {
++ // Received the invitation to join a P2P group.
++
++ _rtw_memset( &group_id, 0x00, sizeof( struct group_id_info ) );
++ rtw_get_p2p_attr_content( merged_p2pie, merged_p2p_ielen, P2P_ATTR_GROUP_ID, ( u8* ) &group_id, &attr_contentlen);
++ if ( attr_contentlen )
++ {
++ if ( _rtw_memcmp( group_id.go_device_addr, myid( &padapter->eeprompriv ), ETH_ALEN ) )
++ {
++ // In this case, the GO can't be myself.
++ rtw_p2p_set_state(pwdinfo, P2P_STATE_RECV_INVITE_REQ_DISMATCH );
++ status_code = P2P_STATUS_FAIL_INFO_UNAVAILABLE;
++ }
++ else
++ {
++ // The p2p device sending this p2p invitation request wants to join an existing P2P group
++ // Commented by Albert 2012/06/28
++ // In this case, this Wi-Fi device should use the iwpriv command to get the peer device address.
++ // The peer device address should be the destination address for the provisioning discovery request.
++ // Then, this Wi-Fi device should use the iwpriv command to get the peer interface address.
++ // The peer interface address should be the address for WPS mac address
++ _rtw_memcpy( pwdinfo->p2p_peer_device_addr, group_id.go_device_addr , ETH_ALEN );
++ rtw_p2p_set_role( pwdinfo, P2P_ROLE_CLIENT );
++ rtw_p2p_set_state(pwdinfo, P2P_STATE_RECV_INVITE_REQ_JOIN );
++ status_code = P2P_STATUS_SUCCESS;
++ }
++ }
++ else
++ {
++ DBG_871X( "[%s] P2P Group ID Attribute NOT FOUND!\n", __FUNCTION__ );
++ status_code = P2P_STATUS_FAIL_INFO_UNAVAILABLE;
++ }
++ }
++ }
++ else
++ {
++ DBG_871X( "[%s] P2P Invitation Flags Attribute NOT FOUND!\n", __FUNCTION__ );
++ status_code = P2P_STATUS_FAIL_INFO_UNAVAILABLE;
++ }
++
++ DBG_871X( "[%s] status_code = %d\n", __FUNCTION__, status_code );
++
++ pwdinfo->inviteresp_info.token = frame_body[ 7 ];
++ issue_p2p_invitation_response( padapter, GetAddr2Ptr(pframe), pwdinfo->inviteresp_info.token, status_code );
++ _set_timer( &pwdinfo->restore_p2p_state_timer, 3000 );
++ }
++#ifdef CONFIG_INTEL_WIDI
++ if( (padapter->mlmepriv.widi_state == INTEL_WIDI_STATE_LISTEN) && (padapter->mlmepriv.widi_state != INTEL_WIDI_STATE_WFD_CONNECTION) )
++ {
++ padapter->mlmepriv.widi_state = INTEL_WIDI_STATE_WFD_CONNECTION;
++ _cancel_timer_ex(&(padapter->mlmepriv.listen_timer));
++ intel_widi_wk_cmd(padapter, INTEL_WIDI_LISTEN_STOP_WK, NULL);
++ }
++#endif //CONFIG_INTEL_WIDI
++ break;
++ }
++ case P2P_INVIT_RESP:
++ {
++ u8 attr_content = 0x00;
++ u32 attr_contentlen = 0;
++
++ DBG_871X( "[%s] Got invite response frame!\n", __FUNCTION__ );
++ _cancel_timer_ex( &pwdinfo->restore_p2p_state_timer );
++ if ( (p2p_ie=rtw_get_p2p_ie( frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, NULL, &p2p_ielen)) )
++ {
++ rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_STATUS, &attr_content, &attr_contentlen);
++
++ if ( attr_contentlen == 1 )
++ {
++ DBG_871X( "[%s] Status = %d\n", __FUNCTION__, attr_content );
++ pwdinfo->invitereq_info.benable = _FALSE;
++
++ if ( attr_content == P2P_STATUS_SUCCESS )
++ {
++ if ( _rtw_memcmp( pwdinfo->invitereq_info.go_bssid, myid( &padapter->eeprompriv ), ETH_ALEN ))
++ {
++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO );
++ }
++ else
++ {
++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT);
++ }
++ rtw_p2p_set_state( pwdinfo, P2P_STATE_RX_INVITE_RESP_OK );
++ }
++ else
++ {
++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE);
++ rtw_p2p_set_state( pwdinfo, P2P_STATE_RX_INVITE_RESP_FAIL );
++ }
++ }
++ else
++ {
++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE);
++ rtw_p2p_set_state( pwdinfo, P2P_STATE_RX_INVITE_RESP_FAIL );
++ }
++ }
++ else
++ {
++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE);
++ rtw_p2p_set_state( pwdinfo, P2P_STATE_RX_INVITE_RESP_FAIL );
++ }
++
++ if ( rtw_p2p_chk_state( pwdinfo, P2P_STATE_RX_INVITE_RESP_FAIL ) )
++ {
++ _set_timer( &pwdinfo->restore_p2p_state_timer, 5000 );
++ }
++ break;
++ }
++ case P2P_DEVDISC_REQ:
++
++ process_p2p_devdisc_req(pwdinfo, pframe, len);
++
++ break;
++
++ case P2P_DEVDISC_RESP:
++
++ process_p2p_devdisc_resp(pwdinfo, pframe, len);
++
++ break;
++
++ case P2P_PROVISION_DISC_REQ:
++ DBG_871X( "[%s] Got Provisioning Discovery Request Frame\n", __FUNCTION__ );
++ process_p2p_provdisc_req(pwdinfo, pframe, len);
++ _rtw_memcpy(pwdinfo->rx_prov_disc_info.peerDevAddr, GetAddr2Ptr(pframe), ETH_ALEN);
++
++ //20110902 Kurt
++ //Add the following statement to avoid receiving duplicate prov disc req. such that pre_p2p_state would be covered.
++ if(!rtw_p2p_chk_state(pwdinfo, P2P_STATE_RX_PROVISION_DIS_REQ))
++ rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo));
++
++ rtw_p2p_set_state(pwdinfo, P2P_STATE_RX_PROVISION_DIS_REQ);
++ _set_timer( &pwdinfo->restore_p2p_state_timer, P2P_PROVISION_TIMEOUT );
++#ifdef CONFIG_INTEL_WIDI
++ if( (padapter->mlmepriv.widi_state == INTEL_WIDI_STATE_LISTEN) && (padapter->mlmepriv.widi_state != INTEL_WIDI_STATE_WFD_CONNECTION) )
++ {
++ padapter->mlmepriv.widi_state = INTEL_WIDI_STATE_WFD_CONNECTION;
++ _cancel_timer_ex(&(padapter->mlmepriv.listen_timer));
++ intel_widi_wk_cmd(padapter, INTEL_WIDI_LISTEN_STOP_WK, NULL);
++ }
++#endif //CONFIG_INTEL_WIDI
++ break;
++
++ case P2P_PROVISION_DISC_RESP:
++ // Commented by Albert 20110707
++ // Should we check the pwdinfo->tx_prov_disc_info.bsent flag here??
++ DBG_871X( "[%s] Got Provisioning Discovery Response Frame\n", __FUNCTION__ );
++ // Commented by Albert 20110426
++ // The restore timer is enabled when issuing the provisioing request frame in rtw_p2p_prov_disc function.
++ _cancel_timer_ex( &pwdinfo->restore_p2p_state_timer );
++ rtw_p2p_set_state(pwdinfo, P2P_STATE_RX_PROVISION_DIS_RSP);
++ process_p2p_provdisc_resp(pwdinfo, pframe);
++ _set_timer( &pwdinfo->restore_p2p_state_timer, P2P_PROVISION_TIMEOUT );
++ break;
++
++ }
++ }
++#endif //CONFIG_P2P
++
++exit:
++
++ if(merged_p2pie)
++ {
++ rtw_mfree(merged_p2pie, merged_p2p_ielen);
++ }
++
++ return _SUCCESS;
++}
++
++unsigned int on_action_public_vendor(union recv_frame *precv_frame)
++{
++ unsigned int ret = _FAIL;
++ u8 *pframe = precv_frame->u.hdr.rx_data;
++ uint frame_len = precv_frame->u.hdr.len;
++ u8 *frame_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr);
++
++ if (_rtw_memcmp(frame_body + 2, P2P_OUI, 4) == _TRUE) {
++ ret = on_action_public_p2p(precv_frame);
++ }
++
++ return ret;
++}
++
++unsigned int on_action_public_default(union recv_frame *precv_frame, u8 action)
++{
++ unsigned int ret = _FAIL;
++ u8 *pframe = precv_frame->u.hdr.rx_data;
++ uint frame_len = precv_frame->u.hdr.len;
++ u8 *frame_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr);
++ u8 token;
++ _adapter *adapter = precv_frame->u.hdr.adapter;
++ int cnt = 0;
++ char msg[64];
++
++ token = frame_body[2];
++
++ if (rtw_action_public_decache(precv_frame, token) == _FAIL)
++ goto exit;
++
++ #ifdef CONFIG_IOCTL_CFG80211
++ cnt += sprintf((msg+cnt), "%s(token:%u)", action_public_str(action), token);
++ rtw_cfg80211_rx_action(adapter, pframe, frame_len, msg);
++ #endif
++
++ ret = _SUCCESS;
++
++exit:
++ return ret;
++}
++
++unsigned int on_action_public(_adapter *padapter, union recv_frame *precv_frame)
++{
++ unsigned int ret = _FAIL;
++ u8 *pframe = precv_frame->u.hdr.rx_data;
++ uint frame_len = precv_frame->u.hdr.len;
++ u8 *frame_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr);
++ u8 category, action;
++
++ /* check RA matches or not */
++ if (!_rtw_memcmp(myid(&(padapter->eeprompriv)), GetAddr1Ptr(pframe), ETH_ALEN))
++ goto exit;
++
++ category = frame_body[0];
++ if(category != RTW_WLAN_CATEGORY_PUBLIC)
++ goto exit;
++
++ action = frame_body[1];
++ switch (action) {
++ case ACT_PUBLIC_VENDOR:
++ ret = on_action_public_vendor(precv_frame);
++ break;
++ default:
++ ret = on_action_public_default(precv_frame, action);
++ break;
++ }
++
++exit:
++ return ret;
++}
++
++unsigned int OnAction_ht(_adapter *padapter, union recv_frame *precv_frame)
++{
++ return _SUCCESS;
++}
++
++#ifdef CONFIG_IEEE80211W
++unsigned int OnAction_sa_query(_adapter *padapter, union recv_frame *precv_frame)
++{
++ u8 *pframe = precv_frame->u.hdr.rx_data;
++ struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++ unsigned short tid;
++ //Baron
++
++ DBG_871X("OnAction_sa_query\n");
++
++ switch (pframe[WLAN_HDR_A3_LEN+1])
++ {
++ case 0: //SA Query req
++ _rtw_memcpy(&tid, &pframe[WLAN_HDR_A3_LEN+2], sizeof(unsigned short));
++ DBG_871X("OnAction_sa_query request,action=%d, tid=%04x\n", pframe[WLAN_HDR_A3_LEN+1], tid);
++ issue_action_SA_Query(padapter, GetAddr2Ptr(pframe), 1, tid);
++ break;
++
++ case 1: //SA Query rsp
++ _cancel_timer_ex(&pmlmeext->sa_query_timer);
++ DBG_871X("OnAction_sa_query response,action=%d, tid=%04x, cancel timer\n", pframe[WLAN_HDR_A3_LEN+1], pframe[WLAN_HDR_A3_LEN+2]);
++ break;
++ default:
++ break;
++ }
++ if(0)
++ {
++ int pp;
++ printk("pattrib->pktlen = %d =>", pattrib->pkt_len);
++ for(pp=0;pp< pattrib->pkt_len; pp++)
++ printk(" %02x ", pframe[pp]);
++ printk("\n");
++ }
++
++ return _SUCCESS;
++}
++#endif //CONFIG_IEEE80211W
++
++unsigned int OnAction_wmm(_adapter *padapter, union recv_frame *precv_frame)
++{
++ return _SUCCESS;
++}
++
++unsigned int OnAction_p2p(_adapter *padapter, union recv_frame *precv_frame)
++{
++#ifdef CONFIG_P2P
++ u8 *frame_body;
++ u8 category, OUI_Subtype, dialogToken=0;
++ u8 *pframe = precv_frame->u.hdr.rx_data;
++ uint len = precv_frame->u.hdr.len;
++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo );
++
++
++ DBG_871X("%s\n", __FUNCTION__);
++
++ //check RA matches or not
++ if (!_rtw_memcmp(myid(&(padapter->eeprompriv)), GetAddr1Ptr(pframe), ETH_ALEN))//for if1, sta/ap mode
++ return _SUCCESS;
++
++ frame_body = (unsigned char *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr));
++
++ category = frame_body[0];
++ if(category != RTW_WLAN_CATEGORY_P2P)
++ return _SUCCESS;
++
++ if ( cpu_to_be32( *( ( u32* ) ( frame_body + 1 ) ) ) != P2POUI )
++ return _SUCCESS;
++
++#ifdef CONFIG_IOCTL_CFG80211
++ if(wdev_to_priv(padapter->rtw_wdev)->p2p_enabled && pwdinfo->driver_interface == DRIVER_CFG80211 )
++ {
++ rtw_cfg80211_rx_action_p2p(padapter, pframe, len);
++ return _SUCCESS;
++ }
++ else
++#endif //CONFIG_IOCTL_CFG80211
++ {
++ len -= sizeof(struct rtw_ieee80211_hdr_3addr);
++ OUI_Subtype = frame_body[5];
++ dialogToken = frame_body[6];
++
++ switch(OUI_Subtype)
++ {
++ case P2P_NOTICE_OF_ABSENCE:
++
++ break;
++
++ case P2P_PRESENCE_REQUEST:
++
++ process_p2p_presence_req(pwdinfo, pframe, len);
++
++ break;
++
++ case P2P_PRESENCE_RESPONSE:
++
++ break;
++
++ case P2P_GO_DISC_REQUEST:
++
++ break;
++
++ default:
++ break;
++
++ }
++ }
++#endif //CONFIG_P2P
++
++ return _SUCCESS;
++
++}
++
++unsigned int OnAction(_adapter *padapter, union recv_frame *precv_frame)
++{
++ int i;
++ unsigned char category;
++ struct action_handler *ptable;
++ unsigned char *frame_body;
++ u8 *pframe = precv_frame->u.hdr.rx_data;
++
++ frame_body = (unsigned char *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr));
++
++ category = frame_body[0];
++
++ for(i = 0; i < sizeof(OnAction_tbl)/sizeof(struct action_handler); i++)
++ {
++ ptable = &OnAction_tbl[i];
++
++ if(category == ptable->num)
++ ptable->func(padapter, precv_frame);
++
++ }
++
++ return _SUCCESS;
++
++}
++
++unsigned int DoReserved(_adapter *padapter, union recv_frame *precv_frame)
++{
++
++ //DBG_871X("rcvd mgt frame(%x, %x)\n", (GetFrameSubType(pframe) >> 4), *(unsigned int *)GetAddr1Ptr(pframe));
++ return _SUCCESS;
++}
++
++struct xmit_frame *_alloc_mgtxmitframe(struct xmit_priv *pxmitpriv, bool once)
++{
++ struct xmit_frame *pmgntframe;
++ struct xmit_buf *pxmitbuf;
++
++ if (once)
++ pmgntframe = rtw_alloc_xmitframe_once(pxmitpriv);
++ else
++ pmgntframe = rtw_alloc_xmitframe_ext(pxmitpriv);
++
++ if (pmgntframe == NULL) {
++ DBG_871X(FUNC_ADPT_FMT" alloc xmitframe fail, once:%d\n", FUNC_ADPT_ARG(pxmitpriv->adapter), once);
++ goto exit;
++ }
++
++ if ((pxmitbuf = rtw_alloc_xmitbuf_ext(pxmitpriv)) == NULL) {
++ DBG_871X(FUNC_ADPT_FMT" alloc xmitbuf fail\n", FUNC_ADPT_ARG(pxmitpriv->adapter));
++ rtw_free_xmitframe(pxmitpriv, pmgntframe);
++ pmgntframe = NULL;
++ goto exit;
++ }
++
++ pmgntframe->frame_tag = MGNT_FRAMETAG;
++ pmgntframe->pxmitbuf = pxmitbuf;
++ pmgntframe->buf_addr = pxmitbuf->pbuf;
++ pxmitbuf->priv_data = pmgntframe;
++
++exit:
++ return pmgntframe;
++
++}
++
++inline struct xmit_frame *alloc_mgtxmitframe(struct xmit_priv *pxmitpriv)
++{
++ return _alloc_mgtxmitframe(pxmitpriv, _FALSE);
++}
++
++inline struct xmit_frame *alloc_mgtxmitframe_once(struct xmit_priv *pxmitpriv)
++{
++ return _alloc_mgtxmitframe(pxmitpriv, _TRUE);
++}
++
++
++/****************************************************************************
++
++Following are some TX fuctions for WiFi MLME
++
++*****************************************************************************/
++
++void update_mgnt_tx_rate(_adapter *padapter, u8 rate)
++{
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++
++ pmlmeext->tx_rate = rate;
++
++ //DBG_871X("%s(): rate = %x\n",__FUNCTION__, rate);
++}
++
++void update_mgntframe_attrib(_adapter *padapter, struct pkt_attrib *pattrib)
++{
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++
++ _rtw_memset((u8 *)(pattrib), 0, sizeof(struct pkt_attrib));
++
++ pattrib->hdrlen = 24;
++ pattrib->nr_frags = 1;
++ pattrib->priority = 7;
++ pattrib->mac_id = 0;
++ pattrib->qsel = 0x12;
++
++ pattrib->pktlen = 0;
++
++ if(pmlmeext->cur_wireless_mode & WIRELESS_11B)
++ pattrib->raid = 6;//b mode
++ else
++ pattrib->raid = 5;//a/g mode
++
++ pattrib->encrypt = _NO_PRIVACY_;
++ pattrib->bswenc = _FALSE;
++
++ pattrib->qos_en = _FALSE;
++ pattrib->ht_en = _FALSE;
++ pattrib->bwmode = HT_CHANNEL_WIDTH_20;
++ pattrib->ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++ pattrib->sgi = _FALSE;
++
++ pattrib->seqnum = pmlmeext->mgnt_seq;
++
++ pattrib->retry_ctrl = _TRUE;
++
++}
++
++void dump_mgntframe(_adapter *padapter, struct xmit_frame *pmgntframe)
++{
++ if(padapter->bSurpriseRemoved == _TRUE ||
++ padapter->bDriverStopped == _TRUE)
++ {
++ rtw_free_xmitbuf(&padapter->xmitpriv, pmgntframe->pxmitbuf);
++ rtw_free_xmitframe(&padapter->xmitpriv, pmgntframe);
++ return;
++ }
++
++ rtw_hal_mgnt_xmit(padapter, pmgntframe);
++}
++
++s32 dump_mgntframe_and_wait(_adapter *padapter, struct xmit_frame *pmgntframe, int timeout_ms)
++{
++ s32 ret = _FAIL;
++ _irqL irqL;
++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++ struct xmit_buf *pxmitbuf = pmgntframe->pxmitbuf;
++ struct submit_ctx sctx;
++
++ if(padapter->bSurpriseRemoved == _TRUE ||
++ padapter->bDriverStopped == _TRUE)
++ {
++ rtw_free_xmitbuf(&padapter->xmitpriv, pmgntframe->pxmitbuf);
++ rtw_free_xmitframe(&padapter->xmitpriv, pmgntframe);
++ return ret;
++ }
++
++ rtw_sctx_init(&sctx, timeout_ms);
++ pxmitbuf->sctx = &sctx;
++
++ ret = rtw_hal_mgnt_xmit(padapter, pmgntframe);
++
++ if (ret == _SUCCESS)
++ ret = rtw_sctx_wait(&sctx);
++
++ _enter_critical(&pxmitpriv->lock_sctx, &irqL);
++ pxmitbuf->sctx = NULL;
++ _exit_critical(&pxmitpriv->lock_sctx, &irqL);
++
++ return ret;
++}
++
++s32 dump_mgntframe_and_wait_ack(_adapter *padapter, struct xmit_frame *pmgntframe)
++{
++#ifdef CONFIG_XMIT_ACK
++ s32 ret = _FAIL;
++ u32 timeout_ms = 500;// 500ms
++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++ #ifdef CONFIG_CONCURRENT_MODE
++ if (padapter->pbuddy_adapter && !padapter->isprimary)
++ pxmitpriv = &(padapter->pbuddy_adapter->xmitpriv);
++ #endif
++
++ if(padapter->bSurpriseRemoved == _TRUE ||
++ padapter->bDriverStopped == _TRUE)
++ {
++ rtw_free_xmitbuf(&padapter->xmitpriv, pmgntframe->pxmitbuf);
++ rtw_free_xmitframe(&padapter->xmitpriv, pmgntframe);
++ return -1;
++ }
++
++ _enter_critical_mutex(&pxmitpriv->ack_tx_mutex, NULL);
++ pxmitpriv->ack_tx = _TRUE;
++
++ pmgntframe->ack_report = 1;
++ if (rtw_hal_mgnt_xmit(padapter, pmgntframe) == _SUCCESS) {
++ ret = rtw_ack_tx_wait(pxmitpriv, timeout_ms);
++ }
++
++ pxmitpriv->ack_tx = _FALSE;
++ _exit_critical_mutex(&pxmitpriv->ack_tx_mutex, NULL);
++
++ return ret;
++#else //!CONFIG_XMIT_ACK
++ dump_mgntframe(padapter, pmgntframe);
++ rtw_msleep_os(50);
++ return _SUCCESS;
++#endif //!CONFIG_XMIT_ACK
++}
++
++int update_hidden_ssid(u8 *ies, u32 ies_len, u8 hidden_ssid_mode)
++{
++ u8 *ssid_ie;
++ sint ssid_len_ori;
++ int len_diff = 0;
++
++ ssid_ie = rtw_get_ie(ies, WLAN_EID_SSID, &ssid_len_ori, ies_len);
++
++ //DBG_871X("%s hidden_ssid_mode:%u, ssid_ie:%p, ssid_len_ori:%d\n", __FUNCTION__, hidden_ssid_mode, ssid_ie, ssid_len_ori);
++
++ if(ssid_ie && ssid_len_ori>0)
++ {
++ switch(hidden_ssid_mode)
++ {
++ case 1:
++ {
++ u8 *next_ie = ssid_ie + 2 + ssid_len_ori;
++ u32 remain_len = 0;
++
++ remain_len = ies_len -(next_ie-ies);
++
++ ssid_ie[1] = 0;
++ _rtw_memcpy(ssid_ie+2, next_ie, remain_len);
++ len_diff -= ssid_len_ori;
++
++ break;
++ }
++ case 2:
++ _rtw_memset(&ssid_ie[2], 0, ssid_len_ori);
++ break;
++ default:
++ break;
++ }
++ }
++
++ return len_diff;
++}
++
++void issue_beacon(_adapter *padapter)
++{
++ struct xmit_frame *pmgntframe;
++ struct pkt_attrib *pattrib;
++ unsigned char *pframe;
++ struct rtw_ieee80211_hdr *pwlanhdr;
++ unsigned short *fctrl;
++ unsigned int rate_len;
++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
++#if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME)
++ _irqL irqL;
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++#endif //#if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME)
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network);
++ u8 bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
++#ifdef CONFIG_P2P
++ struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
++#endif //CONFIG_P2P
++
++
++ //DBG_871X("%s\n", __FUNCTION__);
++
++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL)
++ {
++ DBG_871X("%s, alloc mgnt frame fail\n", __FUNCTION__);
++ return;
++ }
++#if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME)
++ _enter_critical_bh(&pmlmepriv->bcn_update_lock, &irqL);
++#endif //#if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME)
++
++ //update attribute
++ pattrib = &pmgntframe->attrib;
++ update_mgntframe_attrib(padapter, pattrib);
++ pattrib->qsel = 0x10;
++
++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++
++ fctrl = &(pwlanhdr->frame_ctl);
++ *(fctrl) = 0;
++
++ _rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(cur_network), ETH_ALEN);
++
++ SetSeqNum(pwlanhdr, 0/*pmlmeext->mgnt_seq*/);
++ //pmlmeext->mgnt_seq++;
++ SetFrameSubType(pframe, WIFI_BEACON);
++
++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
++ pattrib->pktlen = sizeof (struct rtw_ieee80211_hdr_3addr);
++
++ if( (pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE)
++ {
++ //DBG_871X("ie len=%d\n", cur_network->IELength);
++#ifdef CONFIG_P2P
++ // for P2P : Primary Device Type & Device Name
++ u32 wpsielen=0, insert_len=0;
++ u8 *wpsie=NULL;
++ wpsie = rtw_get_wps_ie(cur_network->IEs+_FIXED_IE_LENGTH_, cur_network->IELength-_FIXED_IE_LENGTH_, NULL, &wpsielen);
++
++ if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO) && wpsie && wpsielen>0)
++ {
++ uint wps_offset, remainder_ielen;
++ u8 *premainder_ie, *pframe_wscie;
++
++ wps_offset = (uint)(wpsie - cur_network->IEs);
++
++ premainder_ie = wpsie + wpsielen;
++
++ remainder_ielen = cur_network->IELength - wps_offset - wpsielen;
++
++#ifdef CONFIG_IOCTL_CFG80211
++ if(wdev_to_priv(padapter->rtw_wdev)->p2p_enabled && pwdinfo->driver_interface == DRIVER_CFG80211 )
++ {
++ if(pmlmepriv->wps_beacon_ie && pmlmepriv->wps_beacon_ie_len>0)
++ {
++ _rtw_memcpy(pframe, cur_network->IEs, wps_offset);
++ pframe += wps_offset;
++ pattrib->pktlen += wps_offset;
++
++ _rtw_memcpy(pframe, pmlmepriv->wps_beacon_ie, pmlmepriv->wps_beacon_ie_len);
++ pframe += pmlmepriv->wps_beacon_ie_len;
++ pattrib->pktlen += pmlmepriv->wps_beacon_ie_len;
++
++ //copy remainder_ie to pframe
++ _rtw_memcpy(pframe, premainder_ie, remainder_ielen);
++ pframe += remainder_ielen;
++ pattrib->pktlen += remainder_ielen;
++ }
++ else
++ {
++ _rtw_memcpy(pframe, cur_network->IEs, cur_network->IELength);
++ pframe += cur_network->IELength;
++ pattrib->pktlen += cur_network->IELength;
++ }
++ }
++ else
++#endif //CONFIG_IOCTL_CFG80211
++ {
++ pframe_wscie = pframe + wps_offset;
++ _rtw_memcpy(pframe, cur_network->IEs, wps_offset+wpsielen);
++ pframe += (wps_offset + wpsielen);
++ pattrib->pktlen += (wps_offset + wpsielen);
++
++ //now pframe is end of wsc ie, insert Primary Device Type & Device Name
++ // Primary Device Type
++ // Type:
++ *(u16*) ( pframe + insert_len) = cpu_to_be16( WPS_ATTR_PRIMARY_DEV_TYPE );
++ insert_len += 2;
++
++ // Length:
++ *(u16*) ( pframe + insert_len ) = cpu_to_be16( 0x0008 );
++ insert_len += 2;
++
++ // Value:
++ // Category ID
++ *(u16*) ( pframe + insert_len ) = cpu_to_be16( WPS_PDT_CID_MULIT_MEDIA );
++ insert_len += 2;
++
++ // OUI
++ *(u32*) ( pframe + insert_len ) = cpu_to_be32( WPSOUI );
++ insert_len += 4;
++
++ // Sub Category ID
++ *(u16*) ( pframe + insert_len ) = cpu_to_be16( WPS_PDT_SCID_MEDIA_SERVER );
++ insert_len += 2;
++
++
++ // Device Name
++ // Type:
++ *(u16*) ( pframe + insert_len ) = cpu_to_be16( WPS_ATTR_DEVICE_NAME );
++ insert_len += 2;
++
++ // Length:
++ *(u16*) ( pframe + insert_len ) = cpu_to_be16( pwdinfo->device_name_len );
++ insert_len += 2;
++
++ // Value:
++ _rtw_memcpy( pframe + insert_len, pwdinfo->device_name, pwdinfo->device_name_len );
++ insert_len += pwdinfo->device_name_len;
++
++
++ //update wsc ie length
++ *(pframe_wscie+1) = (wpsielen -2) + insert_len;
++
++ //pframe move to end
++ pframe+=insert_len;
++ pattrib->pktlen += insert_len;
++
++ //copy remainder_ie to pframe
++ _rtw_memcpy(pframe, premainder_ie, remainder_ielen);
++ pframe += remainder_ielen;
++ pattrib->pktlen += remainder_ielen;
++ }
++ }
++ else
++#endif //CONFIG_P2P
++ {
++ int len_diff;
++ _rtw_memcpy(pframe, cur_network->IEs, cur_network->IELength);
++ len_diff = update_hidden_ssid(
++ pframe+_BEACON_IE_OFFSET_
++ , cur_network->IELength-_BEACON_IE_OFFSET_
++ , pmlmeinfo->hidden_ssid_mode
++ );
++ pframe += (cur_network->IELength+len_diff);
++ pattrib->pktlen += (cur_network->IELength+len_diff);
++ }
++
++ {
++ u8 *wps_ie;
++ uint wps_ielen;
++ u8 sr = 0;
++ wps_ie = rtw_get_wps_ie(pmgntframe->buf_addr+TXDESC_OFFSET+sizeof (struct rtw_ieee80211_hdr_3addr)+_BEACON_IE_OFFSET_,
++ pattrib->pktlen-sizeof (struct rtw_ieee80211_hdr_3addr)-_BEACON_IE_OFFSET_, NULL, &wps_ielen);
++ if (wps_ie && wps_ielen>0) {
++ rtw_get_wps_attr_content(wps_ie, wps_ielen, WPS_ATTR_SELECTED_REGISTRAR, (u8*)(&sr), NULL);
++ }
++ if (sr != 0)
++ set_fwstate(pmlmepriv, WIFI_UNDER_WPS);
++ else
++ _clr_fwstate_(pmlmepriv, WIFI_UNDER_WPS);
++ }
++
++#ifdef CONFIG_P2P
++ if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO))
++ {
++ u32 len;
++#ifdef CONFIG_IOCTL_CFG80211
++ if(wdev_to_priv(padapter->rtw_wdev)->p2p_enabled && pwdinfo->driver_interface == DRIVER_CFG80211 )
++ {
++ len = pmlmepriv->p2p_beacon_ie_len;
++ if(pmlmepriv->p2p_beacon_ie && len>0)
++ _rtw_memcpy(pframe, pmlmepriv->p2p_beacon_ie, len);
++ }
++ else
++#endif //CONFIG_IOCTL_CFG80211
++ {
++ len = build_beacon_p2p_ie(pwdinfo, pframe);
++ }
++
++ pframe += len;
++ pattrib->pktlen += len;
++#ifdef CONFIG_WFD
++#ifdef CONFIG_IOCTL_CFG80211
++ if(_TRUE == pwdinfo->wfd_info->wfd_enable)
++#endif //CONFIG_IOCTL_CFG80211
++ {
++ len = build_beacon_wfd_ie( pwdinfo, pframe );
++ }
++#ifdef CONFIG_IOCTL_CFG80211
++ else
++ {
++ len = 0;
++ if(pmlmepriv->wfd_beacon_ie && pmlmepriv->wfd_beacon_ie_len>0)
++ {
++ len = pmlmepriv->wfd_beacon_ie_len;
++ _rtw_memcpy(pframe, pmlmepriv->wfd_beacon_ie, len);
++ }
++ }
++#endif //CONFIG_IOCTL_CFG80211
++ pframe += len;
++ pattrib->pktlen += len;
++#endif //CONFIG_WFD
++ }
++#endif //CONFIG_P2P
++
++ goto _issue_bcn;
++
++ }
++
++ //below for ad-hoc mode
++
++ //timestamp will be inserted by hardware
++ pframe += 8;
++ pattrib->pktlen += 8;
++
++ // beacon interval: 2 bytes
++
++ _rtw_memcpy(pframe, (unsigned char *)(rtw_get_beacon_interval_from_ie(cur_network->IEs)), 2);
++
++ pframe += 2;
++ pattrib->pktlen += 2;
++
++ // capability info: 2 bytes
++
++ _rtw_memcpy(pframe, (unsigned char *)(rtw_get_capability_from_ie(cur_network->IEs)), 2);
++
++ pframe += 2;
++ pattrib->pktlen += 2;
++
++ // SSID
++ pframe = rtw_set_ie(pframe, _SSID_IE_, cur_network->Ssid.SsidLength, cur_network->Ssid.Ssid, &pattrib->pktlen);
++
++ // supported rates...
++ rate_len = rtw_get_rateset_len(cur_network->SupportedRates);
++ pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, ((rate_len > 8)? 8: rate_len), cur_network->SupportedRates, &pattrib->pktlen);
++
++ // DS parameter set
++ pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&(cur_network->Configuration.DSConfig), &pattrib->pktlen);
++
++ //if( (pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE)
++ {
++ u8 erpinfo=0;
++ u32 ATIMWindow;
++ // IBSS Parameter Set...
++ //ATIMWindow = cur->Configuration.ATIMWindow;
++ ATIMWindow = 0;
++ pframe = rtw_set_ie(pframe, _IBSS_PARA_IE_, 2, (unsigned char *)(&ATIMWindow), &pattrib->pktlen);
++
++ //ERP IE
++ pframe = rtw_set_ie(pframe, _ERPINFO_IE_, 1, &erpinfo, &pattrib->pktlen);
++ }
++
++
++ // EXTERNDED SUPPORTED RATE
++ if (rate_len > 8)
++ {
++ pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (rate_len - 8), (cur_network->SupportedRates + 8), &pattrib->pktlen);
++ }
++
++
++ //todo:HT for adhoc
++
++_issue_bcn:
++
++#if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME)
++ pmlmepriv->update_bcn = _FALSE;
++
++ _exit_critical_bh(&pmlmepriv->bcn_update_lock, &irqL);
++#endif //#if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME)
++
++ if ((pattrib->pktlen + TXDESC_SIZE) > 512)
++ {
++ DBG_871X("beacon frame too large\n");
++ return;
++ }
++
++ pattrib->last_txcmdsz = pattrib->pktlen;
++
++ //DBG_871X("issue bcn_sz=%d\n", pattrib->last_txcmdsz);
++
++ dump_mgntframe(padapter, pmgntframe);
++
++}
++
++void issue_probersp(_adapter *padapter, unsigned char *da, u8 is_valid_p2p_probereq)
++{
++ struct xmit_frame *pmgntframe;
++ struct pkt_attrib *pattrib;
++ unsigned char *pframe;
++ struct rtw_ieee80211_hdr *pwlanhdr;
++ unsigned short *fctrl;
++ unsigned char *mac, *bssid;
++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
++#if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME)
++ u8 *pwps_ie;
++ uint wps_ielen;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++#endif //#if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME)
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network);
++ unsigned int rate_len;
++#ifdef CONFIG_P2P
++ struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
++#ifdef CONFIG_WFD
++ u32 wfdielen = 0;
++#endif //CONFIG_WFD
++#endif //CONFIG_P2P
++
++ //DBG_871X("%s\n", __FUNCTION__);
++
++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL)
++ {
++ DBG_871X("%s, alloc mgnt frame fail\n", __FUNCTION__);
++ return;
++ }
++
++
++ //update attribute
++ pattrib = &pmgntframe->attrib;
++ update_mgntframe_attrib(padapter, pattrib);
++
++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++ mac = myid(&(padapter->eeprompriv));
++ bssid = cur_network->MacAddress;
++
++ fctrl = &(pwlanhdr->frame_ctl);
++ *(fctrl) = 0;
++ _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr3, bssid, ETH_ALEN);
++
++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
++ pmlmeext->mgnt_seq++;
++ SetFrameSubType(fctrl, WIFI_PROBERSP);
++
++ pattrib->hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++ pattrib->pktlen = pattrib->hdrlen;
++ pframe += pattrib->hdrlen;
++
++
++ if(cur_network->IELength>MAX_IE_SZ)
++ return;
++
++#if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME)
++ if( (pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE)
++ {
++ pwps_ie = rtw_get_wps_ie(cur_network->IEs+_FIXED_IE_LENGTH_, cur_network->IELength-_FIXED_IE_LENGTH_, NULL, &wps_ielen);
++
++ //inerset & update wps_probe_resp_ie
++ if((pmlmepriv->wps_probe_resp_ie!=NULL) && pwps_ie && (wps_ielen>0))
++ {
++ uint wps_offset, remainder_ielen;
++ u8 *premainder_ie;
++
++ wps_offset = (uint)(pwps_ie - cur_network->IEs);
++
++ premainder_ie = pwps_ie + wps_ielen;
++
++ remainder_ielen = cur_network->IELength - wps_offset - wps_ielen;
++
++ _rtw_memcpy(pframe, cur_network->IEs, wps_offset);
++ pframe += wps_offset;
++ pattrib->pktlen += wps_offset;
++
++ wps_ielen = (uint)pmlmepriv->wps_probe_resp_ie[1];//to get ie data len
++ if((wps_offset+wps_ielen+2)<=MAX_IE_SZ)
++ {
++ _rtw_memcpy(pframe, pmlmepriv->wps_probe_resp_ie, wps_ielen+2);
++ pframe += wps_ielen+2;
++ pattrib->pktlen += wps_ielen+2;
++ }
++
++ if((wps_offset+wps_ielen+2+remainder_ielen)<=MAX_IE_SZ)
++ {
++ _rtw_memcpy(pframe, premainder_ie, remainder_ielen);
++ pframe += remainder_ielen;
++ pattrib->pktlen += remainder_ielen;
++ }
++ }
++ else
++ {
++ _rtw_memcpy(pframe, cur_network->IEs, cur_network->IELength);
++ pframe += cur_network->IELength;
++ pattrib->pktlen += cur_network->IELength;
++ }
++
++ /* retrieve SSID IE from cur_network->Ssid */
++ {
++ u8 *ssid_ie;
++ sint ssid_ielen;
++ sint ssid_ielen_diff;
++ u8 buf[MAX_IE_SZ];
++ u8 *ies = pmgntframe->buf_addr+TXDESC_OFFSET+sizeof(struct rtw_ieee80211_hdr_3addr);
++
++ ssid_ie = rtw_get_ie(ies+_FIXED_IE_LENGTH_, _SSID_IE_, &ssid_ielen,
++ (pframe-ies)-_FIXED_IE_LENGTH_);
++
++ ssid_ielen_diff = cur_network->Ssid.SsidLength - ssid_ielen;
++
++ if (ssid_ie && cur_network->Ssid.SsidLength) {
++ uint remainder_ielen;
++ u8 *remainder_ie;
++ remainder_ie = ssid_ie+2;
++ remainder_ielen = (pframe-remainder_ie);
++
++ LOG_LEVEL(_drv_warning_, FUNC_ADPT_FMT" remainder_ielen > MAX_IE_SZ\n", FUNC_ADPT_ARG(padapter));
++ if (remainder_ielen > MAX_IE_SZ) {
++ remainder_ielen = MAX_IE_SZ;
++ }
++
++ _rtw_memcpy(buf, remainder_ie, remainder_ielen);
++ _rtw_memcpy(remainder_ie+ssid_ielen_diff, buf, remainder_ielen);
++ *(ssid_ie+1) = cur_network->Ssid.SsidLength;
++ _rtw_memcpy(ssid_ie+2, cur_network->Ssid.Ssid, cur_network->Ssid.SsidLength);
++
++ pframe += ssid_ielen_diff;
++ pattrib->pktlen += ssid_ielen_diff;
++ }
++ }
++ }
++ else
++#endif
++ {
++
++ //timestamp will be inserted by hardware
++ pframe += 8;
++ pattrib->pktlen += 8;
++
++ // beacon interval: 2 bytes
++
++ _rtw_memcpy(pframe, (unsigned char *)(rtw_get_beacon_interval_from_ie(cur_network->IEs)), 2);
++
++ pframe += 2;
++ pattrib->pktlen += 2;
++
++ // capability info: 2 bytes
++
++ _rtw_memcpy(pframe, (unsigned char *)(rtw_get_capability_from_ie(cur_network->IEs)), 2);
++
++ pframe += 2;
++ pattrib->pktlen += 2;
++
++ //below for ad-hoc mode
++
++ // SSID
++ pframe = rtw_set_ie(pframe, _SSID_IE_, cur_network->Ssid.SsidLength, cur_network->Ssid.Ssid, &pattrib->pktlen);
++
++ // supported rates...
++ rate_len = rtw_get_rateset_len(cur_network->SupportedRates);
++ pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, ((rate_len > 8)? 8: rate_len), cur_network->SupportedRates, &pattrib->pktlen);
++
++ // DS parameter set
++ pframe =rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&(cur_network->Configuration.DSConfig), &pattrib->pktlen);
++
++ if( (pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE)
++ {
++ u8 erpinfo=0;
++ u32 ATIMWindow;
++ // IBSS Parameter Set...
++ //ATIMWindow = cur->Configuration.ATIMWindow;
++ ATIMWindow = 0;
++ pframe = rtw_set_ie(pframe, _IBSS_PARA_IE_, 2, (unsigned char *)(&ATIMWindow), &pattrib->pktlen);
++
++ //ERP IE
++ pframe = rtw_set_ie(pframe, _ERPINFO_IE_, 1, &erpinfo, &pattrib->pktlen);
++ }
++
++
++ // EXTERNDED SUPPORTED RATE
++ if (rate_len > 8)
++ {
++ pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (rate_len - 8), (cur_network->SupportedRates + 8), &pattrib->pktlen);
++ }
++
++
++ //todo:HT for adhoc
++
++ }
++
++#ifdef CONFIG_P2P
++ if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO) /*&& is_valid_p2p_probereq*/)
++ {
++ u32 len;
++#ifdef CONFIG_IOCTL_CFG80211
++ if(wdev_to_priv(padapter->rtw_wdev)->p2p_enabled && pwdinfo->driver_interface == DRIVER_CFG80211 )
++ {
++ //if pwdinfo->role == P2P_ROLE_DEVICE will call issue_probersp_p2p()
++ len = pmlmepriv->p2p_go_probe_resp_ie_len;
++ if(pmlmepriv->p2p_go_probe_resp_ie && len>0)
++ _rtw_memcpy(pframe, pmlmepriv->p2p_go_probe_resp_ie, len);
++ }
++ else
++#endif //CONFIG_IOCTL_CFG80211
++ {
++ len = build_probe_resp_p2p_ie(pwdinfo, pframe);
++ }
++
++ pframe += len;
++ pattrib->pktlen += len;
++
++#ifdef CONFIG_WFD
++#ifdef CONFIG_IOCTL_CFG80211
++ if(_TRUE == pwdinfo->wfd_info->wfd_enable)
++#endif //CONFIG_IOCTL_CFG80211
++ {
++ len = build_probe_resp_wfd_ie(pwdinfo, pframe, 0);
++ }
++#ifdef CONFIG_IOCTL_CFG80211
++ else
++ {
++ len = 0;
++ if(pmlmepriv->wfd_probe_resp_ie && pmlmepriv->wfd_probe_resp_ie_len>0)
++ {
++ len = pmlmepriv->wfd_probe_resp_ie_len;
++ _rtw_memcpy(pframe, pmlmepriv->wfd_probe_resp_ie, len);
++ }
++ }
++#endif //CONFIG_IOCTL_CFG80211
++ pframe += len;
++ pattrib->pktlen += len;
++#endif //CONFIG_WFD
++
++ }
++#endif //CONFIG_P2P
++
++
++#ifdef CONFIG_AUTO_AP_MODE
++{
++ struct sta_info *psta;
++ struct sta_priv *pstapriv = &padapter->stapriv;
++
++ DBG_871X("(%s)\n", __FUNCTION__);
++
++ //check rc station
++ psta = rtw_get_stainfo(pstapriv, da);
++ if (psta && psta->isrc && psta->pid>0)
++ {
++ u8 RC_OUI[4]={0x00,0xE0,0x4C,0x0A};
++ u8 RC_INFO[14] = {0};
++ //EID[1] + EID_LEN[1] + RC_OUI[4] + MAC[6] + PairingID[2] + ChannelNum[2]
++ u16 cu_ch = (u16)cur_network->Configuration.DSConfig;
++
++ DBG_871X("%s, reply rc(pid=0x%x) device "MAC_FMT" in ch=%d\n", __FUNCTION__,
++ psta->pid, MAC_ARG(psta->hwaddr), cu_ch);
++
++ //append vendor specific ie
++ _rtw_memcpy(RC_INFO, RC_OUI, sizeof(RC_OUI));
++ _rtw_memcpy(&RC_INFO[4], mac, ETH_ALEN);
++ _rtw_memcpy(&RC_INFO[10], (u8*)&psta->pid, 2);
++ _rtw_memcpy(&RC_INFO[12], (u8*)&cu_ch, 2);
++
++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, sizeof(RC_INFO), RC_INFO, &pattrib->pktlen);
++ }
++}
++#endif //CONFIG_AUTO_AP_MODE
++
++
++ pattrib->last_txcmdsz = pattrib->pktlen;
++
++
++ dump_mgntframe(padapter, pmgntframe);
++
++ return;
++
++}
++
++int _issue_probereq(_adapter *padapter, NDIS_802_11_SSID *pssid, u8 *da, int wait_ack)
++{
++ int ret = _FAIL;
++ struct xmit_frame *pmgntframe;
++ struct pkt_attrib *pattrib;
++ unsigned char *pframe;
++ struct rtw_ieee80211_hdr *pwlanhdr;
++ unsigned short *fctrl;
++ unsigned char *mac;
++ unsigned char bssrate[NumRates];
++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ int bssrate_len = 0;
++ u8 bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
++
++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_notice_,("+issue_probereq\n"));
++
++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL)
++ {
++ goto exit;
++ }
++
++ //update attribute
++ pattrib = &pmgntframe->attrib;
++ update_mgntframe_attrib(padapter, pattrib);
++
++
++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++ mac = myid(&(padapter->eeprompriv));
++
++ fctrl = &(pwlanhdr->frame_ctl);
++ *(fctrl) = 0;
++
++ if (da)
++ {
++ // unicast probe request frame
++ _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr3, da, ETH_ALEN);
++ }
++ else
++ {
++ // broadcast probe request frame
++ _rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr3, bc_addr, ETH_ALEN);
++ }
++
++ _rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN);
++
++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
++ pmlmeext->mgnt_seq++;
++ SetFrameSubType(pframe, WIFI_PROBEREQ);
++
++ pframe += sizeof (struct rtw_ieee80211_hdr_3addr);
++ pattrib->pktlen = sizeof (struct rtw_ieee80211_hdr_3addr);
++
++ if(pssid)
++ pframe = rtw_set_ie(pframe, _SSID_IE_, pssid->SsidLength, pssid->Ssid, &(pattrib->pktlen));
++ else
++ pframe = rtw_set_ie(pframe, _SSID_IE_, 0, NULL, &(pattrib->pktlen));
++
++ get_rate_set(padapter, bssrate, &bssrate_len);
++
++ if (bssrate_len > 8)
++ {
++ pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , 8, bssrate, &(pattrib->pktlen));
++ pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_ , (bssrate_len - 8), (bssrate + 8), &(pattrib->pktlen));
++ }
++ else
++ {
++ pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , bssrate_len , bssrate, &(pattrib->pktlen));
++ }
++
++#if 0
++ //add wps_ie for wps2.0
++ if(pmlmepriv->probereq_wpsie_len>0 && pmlmepriv->probereq_wpsie_len<MAX_WPS_IE_LEN)
++ {
++ _rtw_memcpy(pframe, pmlmepriv->probereq_wpsie, pmlmepriv->probereq_wpsie_len);
++ pframe += pmlmepriv->probereq_wpsie_len;
++ pattrib->pktlen += pmlmepriv->probereq_wpsie_len;
++ //pmlmepriv->probereq_wpsie_len = 0 ;//reset to zero
++ }
++#else
++ //add wps_ie for wps2.0
++ if(pmlmepriv->wps_probe_req_ie_len>0 && pmlmepriv->wps_probe_req_ie)
++ {
++ _rtw_memcpy(pframe, pmlmepriv->wps_probe_req_ie, pmlmepriv->wps_probe_req_ie_len);
++ pframe += pmlmepriv->wps_probe_req_ie_len;
++ pattrib->pktlen += pmlmepriv->wps_probe_req_ie_len;
++ //pmlmepriv->wps_probe_req_ie_len = 0 ;//reset to zero
++ }
++#endif
++
++ pattrib->last_txcmdsz = pattrib->pktlen;
++
++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_notice_,("issuing probe_req, tx_len=%d\n", pattrib->last_txcmdsz));
++
++ if (wait_ack) {
++ ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe);
++ } else {
++ dump_mgntframe(padapter, pmgntframe);
++ ret = _SUCCESS;
++ }
++
++exit:
++ return ret;
++}
++
++inline void issue_probereq(_adapter *padapter, NDIS_802_11_SSID *pssid, u8 *da)
++{
++ _issue_probereq(padapter, pssid, da, _FALSE);
++}
++
++int issue_probereq_ex(_adapter *padapter, NDIS_802_11_SSID *pssid, u8 *da,
++ int try_cnt, int wait_ms)
++{
++ int ret;
++ int i = 0;
++ u32 start = rtw_get_current_time();
++
++ do
++ {
++ ret = _issue_probereq(padapter, pssid, da, wait_ms>0?_TRUE:_FALSE);
++
++ i++;
++
++ if (padapter->bDriverStopped || padapter->bSurpriseRemoved)
++ break;
++
++ if(i < try_cnt && wait_ms > 0 && ret==_FAIL)
++ rtw_msleep_os(wait_ms);
++
++ }while((i<try_cnt) && ((ret==_FAIL)||(wait_ms==0)));
++
++ if (ret != _FAIL) {
++ ret = _SUCCESS;
++ #ifndef DBG_XMIT_ACK
++ goto exit;
++ #endif
++ }
++
++ if (try_cnt && wait_ms) {
++ if (da)
++ DBG_871X(FUNC_ADPT_FMT" to "MAC_FMT", ch:%u%s, %d/%d in %u ms\n",
++ FUNC_ADPT_ARG(padapter), MAC_ARG(da), rtw_get_oper_ch(padapter),
++ ret==_SUCCESS?", acked":"", i, try_cnt, rtw_get_passing_time_ms(start));
++ else
++ DBG_871X(FUNC_ADPT_FMT", ch:%u%s, %d/%d in %u ms\n",
++ FUNC_ADPT_ARG(padapter), rtw_get_oper_ch(padapter),
++ ret==_SUCCESS?", acked":"", i, try_cnt, rtw_get_passing_time_ms(start));
++ }
++exit:
++ return ret;
++}
++
++// if psta == NULL, indiate we are station(client) now...
++void issue_auth(_adapter *padapter, struct sta_info *psta, unsigned short status)
++{
++ struct xmit_frame *pmgntframe;
++ struct pkt_attrib *pattrib;
++ unsigned char *pframe;
++ struct rtw_ieee80211_hdr *pwlanhdr;
++ unsigned short *fctrl;
++ unsigned int val32;
++ unsigned short val16;
++ int use_shared_key = 0;
++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++
++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL)
++ {
++ return;
++ }
++
++ //update attribute
++ pattrib = &pmgntframe->attrib;
++ update_mgntframe_attrib(padapter, pattrib);
++
++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++ fctrl = &(pwlanhdr->frame_ctl);
++ *(fctrl) = 0;
++
++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
++ pmlmeext->mgnt_seq++;
++ SetFrameSubType(pframe, WIFI_AUTH);
++
++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
++ pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++
++
++ if(psta)// for AP mode
++ {
++#ifdef CONFIG_NATIVEAP_MLME
++
++ _rtw_memcpy(pwlanhdr->addr1, psta->hwaddr, ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr3, myid(&(padapter->eeprompriv)), ETH_ALEN);
++
++
++ // setting auth algo number
++ val16 = (u16)psta->authalg;
++
++ if(status != _STATS_SUCCESSFUL_)
++ val16 = 0;
++
++ if (val16) {
++ val16 = cpu_to_le16(val16);
++ use_shared_key = 1;
++ }
++
++ pframe = rtw_set_fixed_ie(pframe, _AUTH_ALGM_NUM_, (unsigned char *)&val16, &(pattrib->pktlen));
++
++ // setting auth seq number
++ val16 =(u16)psta->auth_seq;
++ val16 = cpu_to_le16(val16);
++ pframe = rtw_set_fixed_ie(pframe, _AUTH_SEQ_NUM_, (unsigned char *)&val16, &(pattrib->pktlen));
++
++ // setting status code...
++ val16 = status;
++ val16 = cpu_to_le16(val16);
++ pframe = rtw_set_fixed_ie(pframe, _STATUS_CODE_, (unsigned char *)&val16, &(pattrib->pktlen));
++
++ // added challenging text...
++ if ((psta->auth_seq == 2) && (psta->state & WIFI_FW_AUTH_STATE) && (use_shared_key==1))
++ {
++ pframe = rtw_set_ie(pframe, _CHLGETXT_IE_, 128, psta->chg_txt, &(pattrib->pktlen));
++ }
++#endif
++ }
++ else
++ {
++ _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&pmlmeinfo->network), ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr2, myid(&padapter->eeprompriv), ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&pmlmeinfo->network), ETH_ALEN);
++
++ // setting auth algo number
++ val16 = (pmlmeinfo->auth_algo == dot11AuthAlgrthm_Shared)? 1: 0;// 0:OPEN System, 1:Shared key
++ if (val16) {
++ val16 = cpu_to_le16(val16);
++ use_shared_key = 1;
++ }
++ //DBG_871X("%s auth_algo= %s auth_seq=%d\n",__FUNCTION__,(pmlmeinfo->auth_algo==0)?"OPEN":"SHARED",pmlmeinfo->auth_seq);
++
++ //setting IV for auth seq #3
++ if ((pmlmeinfo->auth_seq == 3) && (pmlmeinfo->state & WIFI_FW_AUTH_STATE) && (use_shared_key==1))
++ {
++ //DBG_871X("==> iv(%d),key_index(%d)\n",pmlmeinfo->iv,pmlmeinfo->key_index);
++ val32 = ((pmlmeinfo->iv++) | (pmlmeinfo->key_index << 30));
++ val32 = cpu_to_le32(val32);
++ pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *)&val32, &(pattrib->pktlen));
++
++ pattrib->iv_len = 4;
++ }
++
++ pframe = rtw_set_fixed_ie(pframe, _AUTH_ALGM_NUM_, (unsigned char *)&val16, &(pattrib->pktlen));
++
++ // setting auth seq number
++ val16 = pmlmeinfo->auth_seq;
++ val16 = cpu_to_le16(val16);
++ pframe = rtw_set_fixed_ie(pframe, _AUTH_SEQ_NUM_, (unsigned char *)&val16, &(pattrib->pktlen));
++
++
++ // setting status code...
++ val16 = status;
++ val16 = cpu_to_le16(val16);
++ pframe = rtw_set_fixed_ie(pframe, _STATUS_CODE_, (unsigned char *)&val16, &(pattrib->pktlen));
++
++ // then checking to see if sending challenging text...
++ if ((pmlmeinfo->auth_seq == 3) && (pmlmeinfo->state & WIFI_FW_AUTH_STATE) && (use_shared_key==1))
++ {
++ pframe = rtw_set_ie(pframe, _CHLGETXT_IE_, 128, pmlmeinfo->chg_txt, &(pattrib->pktlen));
++
++ SetPrivacy(fctrl);
++
++ pattrib->hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++
++ pattrib->encrypt = _WEP40_;
++
++ pattrib->icv_len = 4;
++
++ pattrib->pktlen += pattrib->icv_len;
++
++ }
++
++ }
++
++ pattrib->last_txcmdsz = pattrib->pktlen;
++
++ rtw_wep_encrypt(padapter, (u8 *)pmgntframe);
++
++ dump_mgntframe(padapter, pmgntframe);
++
++ return;
++}
++
++
++void issue_asocrsp(_adapter *padapter, unsigned short status, struct sta_info *pstat, int pkt_type)
++{
++#ifdef CONFIG_AP_MODE
++ struct xmit_frame *pmgntframe;
++ struct rtw_ieee80211_hdr *pwlanhdr;
++ struct pkt_attrib *pattrib;
++ unsigned char *pbuf, *pframe;
++ unsigned short val;
++ unsigned short *fctrl;
++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ WLAN_BSSID_EX *pnetwork = &(pmlmeinfo->network);
++ u8 *ie = pnetwork->IEs;
++#ifdef CONFIG_P2P
++ struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
++#ifdef CONFIG_WFD
++ u32 wfdielen = 0;
++#endif //CONFIG_WFD
++#endif //CONFIG_P2P
++
++ DBG_871X("%s\n", __FUNCTION__);
++
++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL)
++ {
++ return;
++ }
++
++ //update attribute
++ pattrib = &pmgntframe->attrib;
++ update_mgntframe_attrib(padapter, pattrib);
++
++
++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++ fctrl = &(pwlanhdr->frame_ctl);
++ *(fctrl) = 0;
++
++ _rtw_memcpy((void *)GetAddr1Ptr(pwlanhdr), pstat->hwaddr, ETH_ALEN);
++ _rtw_memcpy((void *)GetAddr2Ptr(pwlanhdr), myid(&(padapter->eeprompriv)), ETH_ALEN);
++ _rtw_memcpy((void *)GetAddr3Ptr(pwlanhdr), get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
++
++
++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
++ pmlmeext->mgnt_seq++;
++ if ((pkt_type == WIFI_ASSOCRSP) || (pkt_type == WIFI_REASSOCRSP))
++ SetFrameSubType(pwlanhdr, pkt_type);
++ else
++ return;
++
++ pattrib->hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++ pattrib->pktlen += pattrib->hdrlen;
++ pframe += pattrib->hdrlen;
++
++ //capability
++ val = *(unsigned short *)rtw_get_capability_from_ie(ie);
++
++ pframe = rtw_set_fixed_ie(pframe, _CAPABILITY_ , (unsigned char *)&val, &(pattrib->pktlen));
++
++ status = cpu_to_le16(status);
++ pframe = rtw_set_fixed_ie(pframe , _STATUS_CODE_ , (unsigned char *)&status, &(pattrib->pktlen));
++
++ val = cpu_to_le16(pstat->aid | BIT(14) | BIT(15));
++ pframe = rtw_set_fixed_ie(pframe, _ASOC_ID_ , (unsigned char *)&val, &(pattrib->pktlen));
++
++ if (pstat->bssratelen <= 8)
++ {
++ pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, pstat->bssratelen, pstat->bssrateset, &(pattrib->pktlen));
++ }
++ else
++ {
++ pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, 8, pstat->bssrateset, &(pattrib->pktlen));
++ pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (pstat->bssratelen-8), pstat->bssrateset+8, &(pattrib->pktlen));
++ }
++
++#ifdef CONFIG_80211N_HT
++ if ((pstat->flags & WLAN_STA_HT) && (pmlmepriv->htpriv.ht_option))
++ {
++ uint ie_len=0;
++
++ //FILL HT CAP INFO IE
++ //p = hostapd_eid_ht_capabilities_info(hapd, p);
++ pbuf = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _HT_CAPABILITY_IE_, &ie_len, (pnetwork->IELength - _BEACON_IE_OFFSET_));
++ if(pbuf && ie_len>0)
++ {
++ _rtw_memcpy(pframe, pbuf, ie_len+2);
++ pframe += (ie_len+2);
++ pattrib->pktlen +=(ie_len+2);
++ }
++
++ //FILL HT ADD INFO IE
++ //p = hostapd_eid_ht_operation(hapd, p);
++ pbuf = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _HT_ADD_INFO_IE_, &ie_len, (pnetwork->IELength - _BEACON_IE_OFFSET_));
++ if(pbuf && ie_len>0)
++ {
++ _rtw_memcpy(pframe, pbuf, ie_len+2);
++ pframe += (ie_len+2);
++ pattrib->pktlen +=(ie_len+2);
++ }
++
++ }
++#endif
++
++ //FILL WMM IE
++ if ((pstat->flags & WLAN_STA_WME) && (pmlmepriv->qospriv.qos_option))
++ {
++ uint ie_len=0;
++ unsigned char WMM_PARA_IE[] = {0x00, 0x50, 0xf2, 0x02, 0x01, 0x01};
++
++ for (pbuf = ie + _BEACON_IE_OFFSET_; ;pbuf+= (ie_len + 2))
++ {
++ pbuf = rtw_get_ie(pbuf, _VENDOR_SPECIFIC_IE_, &ie_len, (pnetwork->IELength - _BEACON_IE_OFFSET_ - (ie_len + 2)));
++ if(pbuf && _rtw_memcmp(pbuf+2, WMM_PARA_IE, 6))
++ {
++ _rtw_memcpy(pframe, pbuf, ie_len+2);
++ pframe += (ie_len+2);
++ pattrib->pktlen +=(ie_len+2);
++
++ break;
++ }
++
++ if ((pbuf == NULL) || (ie_len == 0))
++ {
++ break;
++ }
++ }
++
++ }
++
++
++ if (pmlmeinfo->assoc_AP_vendor == realtekAP)
++ {
++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, 6 , REALTEK_96B_IE, &(pattrib->pktlen));
++ }
++
++ //add WPS IE ie for wps 2.0
++ if(pmlmepriv->wps_assoc_resp_ie && pmlmepriv->wps_assoc_resp_ie_len>0)
++ {
++ _rtw_memcpy(pframe, pmlmepriv->wps_assoc_resp_ie, pmlmepriv->wps_assoc_resp_ie_len);
++
++ pframe += pmlmepriv->wps_assoc_resp_ie_len;
++ pattrib->pktlen += pmlmepriv->wps_assoc_resp_ie_len;
++ }
++
++#ifdef CONFIG_P2P
++ if( padapter->wdinfo.driver_interface == DRIVER_WEXT )
++ {
++ if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO) && (pstat->is_p2p_device == _TRUE))
++ {
++ u32 len;
++
++ len = build_assoc_resp_p2p_ie(pwdinfo, pframe, pstat->p2p_status_code);
++
++ pframe += len;
++ pattrib->pktlen += len;
++ }
++ }
++#ifdef CONFIG_WFD
++ if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)
++#ifdef CONFIG_IOCTL_CFG80211
++ && (_TRUE == pwdinfo->wfd_info->wfd_enable)
++#endif //CONFIG_IOCTL_CFG80211
++ )
++ {
++ wfdielen = build_assoc_resp_wfd_ie(pwdinfo, pframe);
++ pframe += wfdielen;
++ pattrib->pktlen += wfdielen;
++ }
++#endif //CONFIG_WFD
++#endif //CONFIG_P2P
++
++ pattrib->last_txcmdsz = pattrib->pktlen;
++
++ dump_mgntframe(padapter, pmgntframe);
++
++#endif
++}
++
++void issue_assocreq(_adapter *padapter)
++{
++ int ret = _FAIL;
++ struct xmit_frame *pmgntframe;
++ struct pkt_attrib *pattrib;
++ unsigned char *pframe, *p;
++ struct rtw_ieee80211_hdr *pwlanhdr;
++ unsigned short *fctrl;
++ unsigned short val16;
++ unsigned int i, j, ie_len, index=0;
++ unsigned char rf_type, bssrate[NumRates], sta_bssrate[NumRates];
++ PNDIS_802_11_VARIABLE_IEs pIE;
++ struct registry_priv *pregpriv = &padapter->registrypriv;
++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ int bssrate_len = 0, sta_bssrate_len = 0;
++ u8 cbw40_enable = 0;
++#ifdef CONFIG_P2P
++ struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
++ u8 p2pie[ 255 ] = { 0x00 };
++ u16 p2pielen = 0;
++#ifdef CONFIG_WFD
++ u32 wfdielen = 0;
++#endif //CONFIG_WFD
++#endif //CONFIG_P2P
++
++#ifdef CONFIG_DFS
++ u16 cap;
++ u8 pow_cap_ele[2] = { 0x00 };
++ u8 sup_ch[ 30 * 2 ] = {0x00 }, sup_ch_idx = 0, idx_5g = 2; //For supported channel
++#endif //CONFIG_DFS
++
++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL)
++ goto exit;
++
++ //update attribute
++ pattrib = &pmgntframe->attrib;
++ update_mgntframe_attrib(padapter, pattrib);
++
++
++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++ fctrl = &(pwlanhdr->frame_ctl);
++ *(fctrl) = 0;
++ _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
++
++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
++ pmlmeext->mgnt_seq++;
++ SetFrameSubType(pframe, WIFI_ASSOCREQ);
++
++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
++ pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++
++ //caps
++
++#ifdef CONFIG_DFS
++ _rtw_memcpy(&cap, rtw_get_capability_from_ie(pmlmeinfo->network.IEs), 2);
++ if(pmlmeext->cur_channel > 14)
++ cap |= BIT(8); //Spectrum Mgmt. Enabled
++ _rtw_memcpy(pframe, &cap, 2);
++#else
++ _rtw_memcpy(pframe, rtw_get_capability_from_ie(pmlmeinfo->network.IEs), 2);
++#endif //CONFIG_DFS
++
++ pframe += 2;
++ pattrib->pktlen += 2;
++
++ //listen interval
++ //todo: listen interval for power saving
++ val16 = cpu_to_le16(3);
++ _rtw_memcpy(pframe ,(unsigned char *)&val16, 2);
++ pframe += 2;
++ pattrib->pktlen += 2;
++
++ //SSID
++ pframe = rtw_set_ie(pframe, _SSID_IE_, pmlmeinfo->network.Ssid.SsidLength, pmlmeinfo->network.Ssid.Ssid, &(pattrib->pktlen));
++
++ //supported rate & extended supported rate
++
++#if 1 // Check if the AP's supported rates are also supported by STA.
++ get_rate_set(padapter, sta_bssrate, &sta_bssrate_len);
++ //DBG_871X("sta_bssrate_len=%d\n", sta_bssrate_len);
++
++ if(pmlmeext->cur_channel == 14)// for JAPAN, channel 14 can only uses B Mode(CCK)
++ {
++ sta_bssrate_len = 4;
++ }
++
++
++ //for (i = 0; i < sta_bssrate_len; i++) {
++ // DBG_871X("sta_bssrate[%d]=%02X\n", i, sta_bssrate[i]);
++ //}
++
++ for (i = 0; i < NDIS_802_11_LENGTH_RATES_EX; i++) {
++ if (pmlmeinfo->network.SupportedRates[i] == 0) break;
++ DBG_871X("network.SupportedRates[%d]=%02X\n", i, pmlmeinfo->network.SupportedRates[i]);
++ }
++
++
++ for (i = 0; i < NDIS_802_11_LENGTH_RATES_EX; i++) {
++ if (pmlmeinfo->network.SupportedRates[i] == 0) break;
++
++
++ // Check if the AP's supported rates are also supported by STA.
++ for (j=0; j < sta_bssrate_len; j++) {
++ // Avoid the proprietary data rate (22Mbps) of Handlink WSG-4000 AP
++ if ( (pmlmeinfo->network.SupportedRates[i]|IEEE80211_BASIC_RATE_MASK)
++ == (sta_bssrate[j]|IEEE80211_BASIC_RATE_MASK)) {
++ //DBG_871X("match i = %d, j=%d\n", i, j);
++ break;
++ } else {
++ //DBG_871X("not match: %02X != %02X\n", (pmlmeinfo->network.SupportedRates[i]|IEEE80211_BASIC_RATE_MASK), (sta_bssrate[j]|IEEE80211_BASIC_RATE_MASK));
++ }
++ }
++
++ if (j == sta_bssrate_len) {
++ // the rate is not supported by STA
++ DBG_871X("%s(): the rate[%d]=%02X is not supported by STA!\n",__FUNCTION__, i, pmlmeinfo->network.SupportedRates[i]);
++ } else {
++ // the rate is supported by STA
++ bssrate[index++] = pmlmeinfo->network.SupportedRates[i];
++ }
++ }
++
++ bssrate_len = index;
++ DBG_871X("bssrate_len = %d\n", bssrate_len);
++
++#else // Check if the AP's supported rates are also supported by STA.
++#if 0
++ get_rate_set(padapter, bssrate, &bssrate_len);
++#else
++ for (bssrate_len = 0; bssrate_len < NumRates; bssrate_len++) {
++ if (pmlmeinfo->network.SupportedRates[bssrate_len] == 0) break;
++
++ if (pmlmeinfo->network.SupportedRates[bssrate_len] == 0x2C) // Avoid the proprietary data rate (22Mbps) of Handlink WSG-4000 AP
++ break;
++
++ bssrate[bssrate_len] = pmlmeinfo->network.SupportedRates[bssrate_len];
++ }
++#endif
++#endif // Check if the AP's supported rates are also supported by STA.
++
++ if (bssrate_len == 0) {
++ rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf);
++ rtw_free_xmitframe(pxmitpriv, pmgntframe);
++ goto exit; //don't connect to AP if no joint supported rate
++ }
++
++
++ if (bssrate_len > 8)
++ {
++ pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , 8, bssrate, &(pattrib->pktlen));
++ pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_ , (bssrate_len - 8), (bssrate + 8), &(pattrib->pktlen));
++ }
++ else
++ {
++ pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , bssrate_len , bssrate, &(pattrib->pktlen));
++ }
++
++#ifdef CONFIG_DFS
++ if(pmlmeext->cur_channel > 14)
++ {
++ pow_cap_ele[0] = 13; // Minimum transmit power capability
++ pow_cap_ele[1] = 21; // Maximum transmit power capability
++ pframe = rtw_set_ie(pframe, _POW_CAP_IE_, 2, pow_cap_ele, &(pattrib->pktlen));
++
++ //supported channels
++ do{
++ if( pmlmeext->channel_set[sup_ch_idx].ChannelNum <= 14 )
++ {
++ sup_ch[0] = 1; //First channel number
++ sup_ch[1] = pmlmeext->channel_set[sup_ch_idx].ChannelNum; //Number of channel
++ }
++ else
++ {
++ sup_ch[idx_5g++] = pmlmeext->channel_set[sup_ch_idx].ChannelNum;
++ sup_ch[idx_5g++] = 1;
++ }
++ sup_ch_idx++;
++ }
++ while( pmlmeext->channel_set[sup_ch_idx].ChannelNum != 0 );
++ pframe = rtw_set_ie(pframe, _SUPPORTED_CH_IE_, idx_5g, sup_ch, &(pattrib->pktlen));
++ }
++#endif //CONFIG_DFS
++
++ //RSN
++ p = rtw_get_ie((pmlmeinfo->network.IEs + sizeof(NDIS_802_11_FIXED_IEs)), _RSN_IE_2_, &ie_len, (pmlmeinfo->network.IELength - sizeof(NDIS_802_11_FIXED_IEs)));
++ if (p != NULL)
++ {
++ pframe = rtw_set_ie(pframe, _RSN_IE_2_, ie_len, (p + 2), &(pattrib->pktlen));
++ }
++
++#ifdef CONFIG_80211N_HT
++ //HT caps
++ if(padapter->mlmepriv.htpriv.ht_option==_TRUE)
++ {
++ p = rtw_get_ie((pmlmeinfo->network.IEs + sizeof(NDIS_802_11_FIXED_IEs)), _HT_CAPABILITY_IE_, &ie_len, (pmlmeinfo->network.IELength - sizeof(NDIS_802_11_FIXED_IEs)));
++ if ((p != NULL) && (!(is_ap_in_tkip(padapter))))
++ {
++ _rtw_memcpy(&(pmlmeinfo->HT_caps), (p + 2), sizeof(struct HT_caps_element));
++
++ //to disable 40M Hz support while gd_bw_40MHz_en = 0
++ if( pmlmeext->cur_channel > 14)
++ {
++ if(pregpriv->cbw40_enable & BIT(1) )
++ cbw40_enable=1;
++ }
++ else
++ if(pregpriv->cbw40_enable & BIT(0) )
++ cbw40_enable=1;
++
++ if (cbw40_enable == 0)
++ {
++ pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info &= (~(BIT(6) | BIT(1)));
++ }
++ else
++ {
++ pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info |= BIT(1);
++ }
++
++ //todo: disable SM power save mode
++ pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info |= 0x000c;
++
++ rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));
++ //switch (pregpriv->rf_config)
++ switch(rf_type)
++ {
++ case RF_1T1R:
++
++ if(pregpriv->rx_stbc)
++ pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info |= cpu_to_le16(0x0100);//RX STBC One spatial stream
++
++ _rtw_memcpy(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_rate_1R, 16);
++ break;
++
++ case RF_2T2R:
++ case RF_1T2R:
++ default:
++
++
++ if(pregpriv->special_rf_path)
++ {
++ if(pregpriv->rx_stbc)
++ pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info |= cpu_to_le16(0x0100);//RX STBC One spatial stream
++ _rtw_memcpy(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_rate_1R, 16);
++ break;
++ }
++
++ if((pregpriv->rx_stbc == 0x3) ||//enable for 2.4/5 GHz
++ ((pmlmeext->cur_wireless_mode & WIRELESS_11_24N) && (pregpriv->rx_stbc == 0x1)) || //enable for 2.4GHz
++ ((pmlmeext->cur_wireless_mode & WIRELESS_11_5N) && (pregpriv->rx_stbc == 0x2)) || //enable for 5GHz
++ (pregpriv->wifi_spec==1))
++ {
++ DBG_871X("declare supporting RX STBC\n");
++ pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info |= cpu_to_le16(0x0200);//RX STBC two spatial stream
++ }
++ #ifdef CONFIG_DISABLE_MCS13TO15
++ if(pmlmeext->cur_bwmode == HT_CHANNEL_WIDTH_40 && (pregpriv->wifi_spec!=1))
++ _rtw_memcpy(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_rate_2R_MCS13TO15_OFF, 16);
++ else
++ _rtw_memcpy(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_rate_2R, 16);
++ #else //CONFIG_DISABLE_MCS13TO15
++ _rtw_memcpy(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_rate_2R, 16);
++ #endif //CONFIG_DISABLE_MCS13TO15
++ break;
++ }
++#ifdef RTL8192C_RECONFIG_TO_1T1R
++ {
++ if(pregpriv->rx_stbc)
++ pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info |= cpu_to_le16(0x0100);//RX STBC One spatial stream
++
++ _rtw_memcpy(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_rate_1R, 16);
++ }
++#endif
++ pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info = cpu_to_le16(pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info);
++ pframe = rtw_set_ie(pframe, _HT_CAPABILITY_IE_, ie_len , (u8 *)(&(pmlmeinfo->HT_caps)), &(pattrib->pktlen));
++
++ }
++ }
++#endif
++
++ //vendor specific IE, such as WPA, WMM, WPS
++ for (i = sizeof(NDIS_802_11_FIXED_IEs); i < pmlmeinfo->network.IELength;)
++ {
++ pIE = (PNDIS_802_11_VARIABLE_IEs)(pmlmeinfo->network.IEs + i);
++
++ switch (pIE->ElementID)
++ {
++ case _VENDOR_SPECIFIC_IE_:
++ if ((_rtw_memcmp(pIE->data, RTW_WPA_OUI, 4)) ||
++ (_rtw_memcmp(pIE->data, WMM_OUI, 4)) ||
++ (_rtw_memcmp(pIE->data, WPS_OUI, 4)))
++ {
++ if(!padapter->registrypriv.wifi_spec)
++ {
++ //Commented by Kurt 20110629
++ //In some older APs, WPS handshake
++ //would be fail if we append vender extensions informations to AP
++ if(_rtw_memcmp(pIE->data, WPS_OUI, 4)){
++ pIE->Length=14;
++ }
++ }
++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, pIE->Length, pIE->data, &(pattrib->pktlen));
++ }
++ break;
++
++ default:
++ break;
++ }
++
++ i += (pIE->Length + 2);
++ }
++
++ if (pmlmeinfo->assoc_AP_vendor == realtekAP)
++ {
++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, 6 , REALTEK_96B_IE, &(pattrib->pktlen));
++ }
++
++#ifdef CONFIG_P2P
++
++#ifdef CONFIG_IOCTL_CFG80211
++ if(wdev_to_priv(padapter->rtw_wdev)->p2p_enabled && pwdinfo->driver_interface == DRIVER_CFG80211 )
++ {
++ if(pmlmepriv->p2p_assoc_req_ie && pmlmepriv->p2p_assoc_req_ie_len>0)
++ {
++ _rtw_memcpy(pframe, pmlmepriv->p2p_assoc_req_ie, pmlmepriv->p2p_assoc_req_ie_len);
++ pframe += pmlmepriv->p2p_assoc_req_ie_len;
++ pattrib->pktlen += pmlmepriv->p2p_assoc_req_ie_len;
++ }
++ }
++ else
++#endif //CONFIG_IOCTL_CFG80211
++ {
++ if(!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) && !rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE))
++ {
++ // Should add the P2P IE in the association request frame.
++ // P2P OUI
++
++ p2pielen = 0;
++ p2pie[ p2pielen++ ] = 0x50;
++ p2pie[ p2pielen++ ] = 0x6F;
++ p2pie[ p2pielen++ ] = 0x9A;
++ p2pie[ p2pielen++ ] = 0x09; // WFA P2P v1.0
++
++ // Commented by Albert 20101109
++ // According to the P2P Specification, the association request frame should contain 3 P2P attributes
++ // 1. P2P Capability
++ // 2. Extended Listen Timing
++ // 3. Device Info
++ // Commented by Albert 20110516
++ // 4. P2P Interface
++
++ // P2P Capability
++ // Type:
++ p2pie[ p2pielen++ ] = P2P_ATTR_CAPABILITY;
++
++ // Length:
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0002 );
++ p2pielen += 2;
++
++ // Value:
++ // Device Capability Bitmap, 1 byte
++ p2pie[ p2pielen++ ] = DMP_P2P_DEVCAP_SUPPORT;
++
++ // Group Capability Bitmap, 1 byte
++ if ( pwdinfo->persistent_supported )
++ p2pie[ p2pielen++ ] = P2P_GRPCAP_PERSISTENT_GROUP | DMP_P2P_GRPCAP_SUPPORT;
++ else
++ p2pie[ p2pielen++ ] = DMP_P2P_GRPCAP_SUPPORT;
++
++ // Extended Listen Timing
++ // Type:
++ p2pie[ p2pielen++ ] = P2P_ATTR_EX_LISTEN_TIMING;
++
++ // Length:
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0004 );
++ p2pielen += 2;
++
++ // Value:
++ // Availability Period
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0xFFFF );
++ p2pielen += 2;
++
++ // Availability Interval
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0xFFFF );
++ p2pielen += 2;
++
++ // Device Info
++ // Type:
++ p2pie[ p2pielen++ ] = P2P_ATTR_DEVICE_INFO;
++
++ // Length:
++ // 21 -> P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes)
++ // + NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes)
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 21 + pwdinfo->device_name_len );
++ p2pielen += 2;
++
++ // Value:
++ // P2P Device Address
++ _rtw_memcpy( p2pie + p2pielen, myid( &padapter->eeprompriv ), ETH_ALEN );
++ p2pielen += ETH_ALEN;
++
++ // Config Method
++ // This field should be big endian. Noted by P2P specification.
++ if ( ( pwdinfo->ui_got_wps_info == P2P_GOT_WPSINFO_PEER_DISPLAY_PIN ) ||
++ ( pwdinfo->ui_got_wps_info == P2P_GOT_WPSINFO_SELF_DISPLAY_PIN ) )
++ {
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_CONFIG_METHOD_DISPLAY );
++ }
++ else
++ {
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_CONFIG_METHOD_PBC );
++ }
++
++ p2pielen += 2;
++
++ // Primary Device Type
++ // Category ID
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_CID_MULIT_MEDIA );
++ p2pielen += 2;
++
++ // OUI
++ *(u32*) ( p2pie + p2pielen ) = cpu_to_be32( WPSOUI );
++ p2pielen += 4;
++
++ // Sub Category ID
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_SCID_MEDIA_SERVER );
++ p2pielen += 2;
++
++ // Number of Secondary Device Types
++ p2pie[ p2pielen++ ] = 0x00; // No Secondary Device Type List
++
++ // Device Name
++ // Type:
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_ATTR_DEVICE_NAME );
++ p2pielen += 2;
++
++ // Length:
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( pwdinfo->device_name_len );
++ p2pielen += 2;
++
++ // Value:
++ _rtw_memcpy( p2pie + p2pielen, pwdinfo->device_name, pwdinfo->device_name_len );
++ p2pielen += pwdinfo->device_name_len;
++
++ // P2P Interface
++ // Type:
++ p2pie[ p2pielen++ ] = P2P_ATTR_INTERFACE;
++
++ // Length:
++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x000D );
++ p2pielen += 2;
++
++ // Value:
++ _rtw_memcpy( p2pie + p2pielen, pwdinfo->device_addr, ETH_ALEN ); // P2P Device Address
++ p2pielen += ETH_ALEN;
++
++ p2pie[ p2pielen++ ] = 1; // P2P Interface Address Count
++
++ _rtw_memcpy( p2pie + p2pielen, pwdinfo->device_addr, ETH_ALEN ); // P2P Interface Address List
++ p2pielen += ETH_ALEN;
++
++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen );
++
++#ifdef CONFIG_WFD
++ //wfdielen = build_assoc_req_wfd_ie(pwdinfo, pframe);
++ //pframe += wfdielen;
++ //pattrib->pktlen += wfdielen;
++#endif //CONFIG_WFD
++ }
++ }
++
++#endif //CONFIG_P2P
++
++#ifdef CONFIG_WFD
++#ifdef CONFIG_IOCTL_CFG80211
++ if ( _TRUE == pwdinfo->wfd_info->wfd_enable )
++#endif //CONFIG_IOCTL_CFG80211
++ {
++ wfdielen = build_assoc_req_wfd_ie(pwdinfo, pframe);
++ pframe += wfdielen;
++ pattrib->pktlen += wfdielen;
++ }
++#ifdef CONFIG_IOCTL_CFG80211
++ else if (pmlmepriv->wfd_assoc_req_ie != NULL && pmlmepriv->wfd_assoc_req_ie_len>0)
++ {
++ //WFD IE
++ _rtw_memcpy(pframe, pmlmepriv->wfd_assoc_req_ie, pmlmepriv->wfd_assoc_req_ie_len);
++ pattrib->pktlen += pmlmepriv->wfd_assoc_req_ie_len;
++ pframe += pmlmepriv->wfd_assoc_req_ie_len;
++ }
++#endif //CONFIG_IOCTL_CFG80211
++#endif //CONFIG_WFD
++
++ pattrib->last_txcmdsz = pattrib->pktlen;
++ dump_mgntframe(padapter, pmgntframe);
++
++ ret = _SUCCESS;
++
++exit:
++ if (ret == _SUCCESS)
++ rtw_buf_update(&pmlmepriv->assoc_req, &pmlmepriv->assoc_req_len, (u8 *)pwlanhdr, pattrib->pktlen);
++ else
++ rtw_buf_free(&pmlmepriv->assoc_req, &pmlmepriv->assoc_req_len);
++
++ return;
++}
++
++//when wait_ack is ture, this function shoule be called at process context
++static int _issue_nulldata(_adapter *padapter, unsigned char *da, unsigned int power_mode, int wait_ack)
++{
++ int ret = _FAIL;
++ struct xmit_frame *pmgntframe;
++ struct pkt_attrib *pattrib;
++ unsigned char *pframe;
++ struct rtw_ieee80211_hdr *pwlanhdr;
++ unsigned short *fctrl;
++ struct xmit_priv *pxmitpriv;
++ struct mlme_ext_priv *pmlmeext;
++ struct mlme_ext_info *pmlmeinfo;
++
++ //DBG_871X("%s:%d\n", __FUNCTION__, power_mode);
++
++ if(!padapter)
++ goto exit;
++
++ pxmitpriv = &(padapter->xmitpriv);
++ pmlmeext = &(padapter->mlmeextpriv);
++ pmlmeinfo = &(pmlmeext->mlmext_info);
++
++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL)
++ {
++ goto exit;
++ }
++
++ //update attribute
++ pattrib = &pmgntframe->attrib;
++ update_mgntframe_attrib(padapter, pattrib);
++ pattrib->retry_ctrl = _FALSE;
++
++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++ fctrl = &(pwlanhdr->frame_ctl);
++ *(fctrl) = 0;
++
++ if((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE)
++ {
++ SetFrDs(fctrl);
++ }
++ else if((pmlmeinfo->state&0x03) == WIFI_FW_STATION_STATE)
++ {
++ SetToDs(fctrl);
++ }
++
++ if (power_mode)
++ {
++ SetPwrMgt(fctrl);
++ }
++
++ _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
++
++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
++ pmlmeext->mgnt_seq++;
++ SetFrameSubType(pframe, WIFI_DATA_NULL);
++
++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
++ pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++
++ pattrib->last_txcmdsz = pattrib->pktlen;
++
++ if(wait_ack)
++ {
++ ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe);
++ }
++ else
++ {
++ dump_mgntframe(padapter, pmgntframe);
++ ret = _SUCCESS;
++ }
++
++exit:
++ return ret;
++}
++
++
++//when wait_ms >0 , this function shoule be called at process context
++//da == NULL for station mode
++int issue_nulldata(_adapter *padapter, unsigned char *da, unsigned int power_mode, int try_cnt, int wait_ms)
++{
++ int ret;
++ int i = 0;
++ u32 start = rtw_get_current_time();
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++
++ /* da == NULL, assum it's null data for sta to ap*/
++ if (da == NULL)
++ da = get_my_bssid(&(pmlmeinfo->network));
++
++ do
++ {
++ ret = _issue_nulldata(padapter, da, power_mode, wait_ms>0?_TRUE:_FALSE);
++
++ i++;
++
++ if (padapter->bDriverStopped || padapter->bSurpriseRemoved)
++ break;
++
++ if(i < try_cnt && wait_ms > 0 && ret==_FAIL)
++ rtw_msleep_os(wait_ms);
++
++ }while((i<try_cnt) && ((ret==_FAIL)||(wait_ms==0)));
++
++ if (ret != _FAIL) {
++ ret = _SUCCESS;
++ #ifndef DBG_XMIT_ACK
++ goto exit;
++ #endif
++ }
++
++ if (try_cnt && wait_ms) {
++ if (da)
++ DBG_871X(FUNC_ADPT_FMT" to "MAC_FMT", ch:%u%s, %d/%d in %u ms\n",
++ FUNC_ADPT_ARG(padapter), MAC_ARG(da), rtw_get_oper_ch(padapter),
++ ret==_SUCCESS?", acked":"", i, try_cnt, rtw_get_passing_time_ms(start));
++ else
++ DBG_871X(FUNC_ADPT_FMT", ch:%u%s, %d/%d in %u ms\n",
++ FUNC_ADPT_ARG(padapter), rtw_get_oper_ch(padapter),
++ ret==_SUCCESS?", acked":"", i, try_cnt, rtw_get_passing_time_ms(start));
++ }
++exit:
++ return ret;
++}
++
++//when wait_ack is ture, this function shoule be called at process context
++static int _issue_qos_nulldata(_adapter *padapter, unsigned char *da, u16 tid, int wait_ack)
++{
++ int ret = _FAIL;
++ struct xmit_frame *pmgntframe;
++ struct pkt_attrib *pattrib;
++ unsigned char *pframe;
++ struct rtw_ieee80211_hdr *pwlanhdr;
++ unsigned short *fctrl, *qc;
++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++
++ DBG_871X("%s\n", __FUNCTION__);
++
++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL)
++ {
++ goto exit;
++ }
++
++ //update attribute
++ pattrib = &pmgntframe->attrib;
++ update_mgntframe_attrib(padapter, pattrib);
++
++ pattrib->hdrlen +=2;
++ pattrib->qos_en = _TRUE;
++ pattrib->eosp = 1;
++ pattrib->ack_policy = 0;
++ pattrib->mdata = 0;
++
++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++ fctrl = &(pwlanhdr->frame_ctl);
++ *(fctrl) = 0;
++
++ if((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE)
++ {
++ SetFrDs(fctrl);
++ }
++ else if((pmlmeinfo->state&0x03) == WIFI_FW_STATION_STATE)
++ {
++ SetToDs(fctrl);
++ }
++
++ if(pattrib->mdata)
++ SetMData(fctrl);
++
++ qc = (unsigned short *)(pframe + pattrib->hdrlen - 2);
++
++ SetPriority(qc, tid);
++
++ SetEOSP(qc, pattrib->eosp);
++
++ SetAckpolicy(qc, pattrib->ack_policy);
++
++ _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
++
++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
++ pmlmeext->mgnt_seq++;
++ SetFrameSubType(pframe, WIFI_QOS_DATA_NULL);
++
++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr_qos);
++ pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr_qos);
++
++ pattrib->last_txcmdsz = pattrib->pktlen;
++
++ if(wait_ack)
++ {
++ ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe);
++ }
++ else
++ {
++ dump_mgntframe(padapter, pmgntframe);
++ ret = _SUCCESS;
++ }
++
++exit:
++ return ret;
++}
++
++//when wait_ms >0 , this function shoule be called at process context
++//da == NULL for station mode
++int issue_qos_nulldata(_adapter *padapter, unsigned char *da, u16 tid, int try_cnt, int wait_ms)
++{
++ int ret;
++ int i = 0;
++ u32 start = rtw_get_current_time();
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++
++ /* da == NULL, assum it's null data for sta to ap*/
++ if (da == NULL)
++ da = get_my_bssid(&(pmlmeinfo->network));
++
++ do
++ {
++ ret = _issue_qos_nulldata(padapter, da, tid, wait_ms>0?_TRUE:_FALSE);
++
++ i++;
++
++ if (padapter->bDriverStopped || padapter->bSurpriseRemoved)
++ break;
++
++ if(i < try_cnt && wait_ms > 0 && ret==_FAIL)
++ rtw_msleep_os(wait_ms);
++
++ }while((i<try_cnt) && ((ret==_FAIL)||(wait_ms==0)));
++
++ if (ret != _FAIL) {
++ ret = _SUCCESS;
++ #ifndef DBG_XMIT_ACK
++ goto exit;
++ #endif
++ }
++
++ if (try_cnt && wait_ms) {
++ if (da)
++ DBG_871X(FUNC_ADPT_FMT" to "MAC_FMT", ch:%u%s, %d/%d in %u ms\n",
++ FUNC_ADPT_ARG(padapter), MAC_ARG(da), rtw_get_oper_ch(padapter),
++ ret==_SUCCESS?", acked":"", i, try_cnt, rtw_get_passing_time_ms(start));
++ else
++ DBG_871X(FUNC_ADPT_FMT", ch:%u%s, %d/%d in %u ms\n",
++ FUNC_ADPT_ARG(padapter), rtw_get_oper_ch(padapter),
++ ret==_SUCCESS?", acked":"", i, try_cnt, rtw_get_passing_time_ms(start));
++ }
++exit:
++ return ret;
++}
++
++static int _issue_deauth(_adapter *padapter, unsigned char *da, unsigned short reason, u8 wait_ack)
++{
++ struct xmit_frame *pmgntframe;
++ struct pkt_attrib *pattrib;
++ unsigned char *pframe;
++ struct rtw_ieee80211_hdr *pwlanhdr;
++ unsigned short *fctrl;
++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ int ret = _FAIL;
++#ifdef CONFIG_P2P
++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo);
++#endif //CONFIG_P2P
++
++ //DBG_871X("%s to "MAC_FMT"\n", __func__, MAC_ARG(da));
++
++#ifdef CONFIG_P2P
++ if ( !( rtw_p2p_chk_state( pwdinfo, P2P_STATE_NONE ) ) && ( pwdinfo->rx_invitereq_info.scan_op_ch_only ) )
++ {
++ _cancel_timer_ex( &pwdinfo->reset_ch_sitesurvey );
++ _set_timer( &pwdinfo->reset_ch_sitesurvey, 10 );
++ }
++#endif //CONFIG_P2P
++
++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL)
++ {
++ goto exit;
++ }
++
++ //update attribute
++ pattrib = &pmgntframe->attrib;
++ update_mgntframe_attrib(padapter, pattrib);
++ pattrib->retry_ctrl = _FALSE;
++
++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++ fctrl = &(pwlanhdr->frame_ctl);
++ *(fctrl) = 0;
++
++ _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
++
++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
++ pmlmeext->mgnt_seq++;
++ SetFrameSubType(pframe, WIFI_DEAUTH);
++
++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
++ pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++
++ reason = cpu_to_le16(reason);
++ pframe = rtw_set_fixed_ie(pframe, _RSON_CODE_ , (unsigned char *)&reason, &(pattrib->pktlen));
++
++ pattrib->last_txcmdsz = pattrib->pktlen;
++
++
++ if(wait_ack)
++ {
++ ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe);
++ }
++ else
++ {
++ dump_mgntframe(padapter, pmgntframe);
++ ret = _SUCCESS;
++ }
++
++exit:
++ return ret;
++}
++
++int issue_deauth(_adapter *padapter, unsigned char *da, unsigned short reason)
++{
++ DBG_871X("%s to "MAC_FMT"\n", __func__, MAC_ARG(da));
++ return _issue_deauth(padapter, da, reason, _FALSE);
++}
++
++int issue_deauth_ex(_adapter *padapter, u8 *da, unsigned short reason, int try_cnt,
++ int wait_ms)
++{
++ int ret;
++ int i = 0;
++ u32 start = rtw_get_current_time();
++
++ do
++ {
++ ret = _issue_deauth(padapter, da, reason, wait_ms>0?_TRUE:_FALSE);
++
++ i++;
++
++ if (padapter->bDriverStopped || padapter->bSurpriseRemoved)
++ break;
++
++ if(i < try_cnt && wait_ms > 0 && ret==_FAIL)
++ rtw_msleep_os(wait_ms);
++
++ }while((i<try_cnt) && ((ret==_FAIL)||(wait_ms==0)));
++
++ if (ret != _FAIL) {
++ ret = _SUCCESS;
++ #ifndef DBG_XMIT_ACK
++ goto exit;
++ #endif
++ }
++
++ if (try_cnt && wait_ms) {
++ if (da)
++ DBG_871X(FUNC_ADPT_FMT" to "MAC_FMT", ch:%u%s, %d/%d in %u ms\n",
++ FUNC_ADPT_ARG(padapter), MAC_ARG(da), rtw_get_oper_ch(padapter),
++ ret==_SUCCESS?", acked":"", i, try_cnt, rtw_get_passing_time_ms(start));
++ else
++ DBG_871X(FUNC_ADPT_FMT", ch:%u%s, %d/%d in %u ms\n",
++ FUNC_ADPT_ARG(padapter), rtw_get_oper_ch(padapter),
++ ret==_SUCCESS?", acked":"", i, try_cnt, rtw_get_passing_time_ms(start));
++ }
++exit:
++ return ret;
++}
++
++void issue_action_spct_ch_switch(_adapter *padapter, u8 *ra, u8 new_ch, u8 ch_offset)
++{
++ _irqL irqL;
++ _list *plist, *phead;
++ struct xmit_frame *pmgntframe;
++ struct pkt_attrib *pattrib;
++ unsigned char *pframe;
++ struct rtw_ieee80211_hdr *pwlanhdr;
++ unsigned short *fctrl;
++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++
++
++ DBG_871X(FUNC_NDEV_FMT" ra="MAC_FMT", ch:%u, offset:%u\n",
++ FUNC_NDEV_ARG(padapter->pnetdev), MAC_ARG(ra), new_ch, ch_offset);
++
++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL)
++ return;
++
++ //update attribute
++ pattrib = &pmgntframe->attrib;
++ update_mgntframe_attrib(padapter, pattrib);
++
++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++ fctrl = &(pwlanhdr->frame_ctl);
++ *(fctrl) = 0;
++
++ _rtw_memcpy(pwlanhdr->addr1, ra, ETH_ALEN); /* RA */
++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN); /* TA */
++ _rtw_memcpy(pwlanhdr->addr3, ra, ETH_ALEN); /* DA = RA */
++
++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
++ pmlmeext->mgnt_seq++;
++ SetFrameSubType(pframe, WIFI_ACTION);
++
++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
++ pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++
++ /* category, action */
++ {
++ u8 category, action;
++ category = RTW_WLAN_CATEGORY_SPECTRUM_MGMT;
++ action = RTW_WLAN_ACTION_SPCT_CHL_SWITCH;
++
++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
++ pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));
++ }
++
++ pframe = rtw_set_ie_ch_switch(pframe, &(pattrib->pktlen), 0, new_ch, 0);
++ pframe = rtw_set_ie_secondary_ch_offset(pframe, &(pattrib->pktlen),
++ hal_ch_offset_to_secondary_ch_offset(ch_offset));
++
++ pattrib->last_txcmdsz = pattrib->pktlen;
++
++ dump_mgntframe(padapter, pmgntframe);
++
++}
++
++#ifdef CONFIG_IEEE80211W
++void issue_action_SA_Query(_adapter *padapter, unsigned char *raddr, unsigned char action, unsigned short tid)
++{
++ u8 category = RTW_WLAN_CATEGORY_SA_QUERY;
++ u16 reason_code;
++ struct xmit_frame *pmgntframe;
++ struct pkt_attrib *pattrib;
++ u8 *pframe;
++ struct rtw_ieee80211_hdr *pwlanhdr;
++ u16 *fctrl;
++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ struct sta_info *psta;
++ struct sta_priv *pstapriv = &padapter->stapriv;
++ struct registry_priv *pregpriv = &padapter->registrypriv;
++
++
++ DBG_871X("%s\n", __FUNCTION__);
++
++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL)
++ {
++ DBG_871X("%s: alloc_mgtxmitframe fail\n", __FUNCTION__);
++ return;
++ }
++
++ //update attribute
++ pattrib = &pmgntframe->attrib;
++ update_mgntframe_attrib(padapter, pattrib);
++
++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++ fctrl = &(pwlanhdr->frame_ctl);
++ *(fctrl) = 0;
++
++ if(raddr)
++ _rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN);
++ else
++ _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
++
++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
++ pmlmeext->mgnt_seq++;
++ SetFrameSubType(pframe, WIFI_ACTION);
++
++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
++ pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++
++ pframe = rtw_set_fixed_ie(pframe, 1, &category, &pattrib->pktlen);
++ pframe = rtw_set_fixed_ie(pframe, 1, &action, &pattrib->pktlen);
++
++ switch (action)
++ {
++ case 0: //SA Query req
++ pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)&pmlmeext->sa_query_seq, &pattrib->pktlen);
++ pmlmeext->sa_query_seq++;
++ //send sa query request to AP, AP should reply sa query response in 1 second
++ set_sa_query_timer(pmlmeext, 1000);
++ break;
++
++ case 1: //SA Query rsp
++ tid = cpu_to_le16(tid);
++ pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)&tid, &pattrib->pktlen);
++ break;
++ default:
++ break;
++ }
++
++ pattrib->last_txcmdsz = pattrib->pktlen;
++
++ dump_mgntframe(padapter, pmgntframe);
++}
++#endif //CONFIG_IEEE80211W
++
++void issue_action_BA(_adapter *padapter, unsigned char *raddr, unsigned char action, unsigned short status)
++{
++ u8 category = RTW_WLAN_CATEGORY_BACK;
++ u16 start_seq;
++ u16 BA_para_set;
++ u16 reason_code;
++ u16 BA_timeout_value;
++ u16 BA_starting_seqctrl;
++ struct xmit_frame *pmgntframe;
++ struct pkt_attrib *pattrib;
++ u8 *pframe;
++ struct rtw_ieee80211_hdr *pwlanhdr;
++ u16 *fctrl;
++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ struct sta_info *psta;
++ struct sta_priv *pstapriv = &padapter->stapriv;
++ struct registry_priv *pregpriv = &padapter->registrypriv;
++
++
++ DBG_871X("%s, category=%d, action=%d, status=%d\n", __FUNCTION__, category, action, status);
++
++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL)
++ {
++ return;
++ }
++
++ //update attribute
++ pattrib = &pmgntframe->attrib;
++ update_mgntframe_attrib(padapter, pattrib);
++
++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++ fctrl = &(pwlanhdr->frame_ctl);
++ *(fctrl) = 0;
++
++ //_rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
++
++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
++ pmlmeext->mgnt_seq++;
++ SetFrameSubType(pframe, WIFI_ACTION);
++
++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
++ pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++
++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
++ pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));
++
++ status = cpu_to_le16(status);
++
++
++ if (category == 3)
++ {
++ switch (action)
++ {
++ case 0: //ADDBA req
++ do {
++ pmlmeinfo->dialogToken++;
++ } while (pmlmeinfo->dialogToken == 0);
++ pframe = rtw_set_fixed_ie(pframe, 1, &(pmlmeinfo->dialogToken), &(pattrib->pktlen));
++
++ BA_para_set = (0x1002 | ((status & 0xf) << 2)); //immediate ack & 64 buffer size
++ //sys_mib.BA_para_set = 0x0802; //immediate ack & 32 buffer size
++ BA_para_set = cpu_to_le16(BA_para_set);
++ pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(BA_para_set)), &(pattrib->pktlen));
++
++ //BA_timeout_value = 0xffff;//max: 65535 TUs(~ 65 ms)
++ BA_timeout_value = 5000;//~ 5ms
++ BA_timeout_value = cpu_to_le16(BA_timeout_value);
++ pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(BA_timeout_value)), &(pattrib->pktlen));
++
++ //if ((psta = rtw_get_stainfo(pstapriv, pmlmeinfo->network.MacAddress)) != NULL)
++ if ((psta = rtw_get_stainfo(pstapriv, raddr)) != NULL)
++ {
++ start_seq = (psta->sta_xmitpriv.txseq_tid[status & 0x07]&0xfff) + 1;
++
++ DBG_871X("BA_starting_seqctrl = %d for TID=%d\n", start_seq, status & 0x07);
++
++ psta->BA_starting_seqctrl[status & 0x07] = start_seq;
++
++ BA_starting_seqctrl = start_seq << 4;
++ }
++
++ BA_starting_seqctrl = cpu_to_le16(BA_starting_seqctrl);
++ pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(BA_starting_seqctrl)), &(pattrib->pktlen));
++ break;
++
++ case 1: //ADDBA rsp
++ pframe = rtw_set_fixed_ie(pframe, 1, &(pmlmeinfo->ADDBA_req.dialog_token), &(pattrib->pktlen));
++ pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&status), &(pattrib->pktlen));
++
++ //BA_para_set = cpu_to_le16((le16_to_cpu(pmlmeinfo->ADDBA_req.BA_para_set) & 0x3f) | 0x1000); //64 buffer size
++ BA_para_set = ((le16_to_cpu(pmlmeinfo->ADDBA_req.BA_para_set) & 0x3f) | 0x1000); //64 buffer size
++
++ if(pregpriv->ampdu_amsdu==0)//disabled
++ BA_para_set = cpu_to_le16(BA_para_set & ~BIT(0));
++ else if(pregpriv->ampdu_amsdu==1)//enabled
++ BA_para_set = cpu_to_le16(BA_para_set | BIT(0));
++ else //auto
++ BA_para_set = cpu_to_le16(BA_para_set);
++
++ pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(BA_para_set)), &(pattrib->pktlen));
++ pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(pmlmeinfo->ADDBA_req.BA_timeout_value)), &(pattrib->pktlen));
++ break;
++ case 2://DELBA
++ BA_para_set = (status & 0x1F) << 3;
++ BA_para_set = cpu_to_le16(BA_para_set);
++ pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(BA_para_set)), &(pattrib->pktlen));
++
++ reason_code = 37;//Requested from peer STA as it does not want to use the mechanism
++ reason_code = cpu_to_le16(reason_code);
++ pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(reason_code)), &(pattrib->pktlen));
++ break;
++ default:
++ break;
++ }
++ }
++
++ pattrib->last_txcmdsz = pattrib->pktlen;
++
++ dump_mgntframe(padapter, pmgntframe);
++}
++
++static void issue_action_BSSCoexistPacket(_adapter *padapter)
++{
++ _irqL irqL;
++ _list *plist, *phead;
++ unsigned char category, action;
++ struct xmit_frame *pmgntframe;
++ struct pkt_attrib *pattrib;
++ unsigned char *pframe;
++ struct rtw_ieee80211_hdr *pwlanhdr;
++ unsigned short *fctrl;
++ struct wlan_network *pnetwork = NULL;
++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ _queue *queue = &(pmlmepriv->scanned_queue);
++ u8 InfoContent[16] = {0};
++ u8 ICS[8][15];
++
++ if((pmlmepriv->num_FortyMHzIntolerant==0) || (pmlmepriv->num_sta_no_ht==0))
++ return;
++
++ if(_TRUE == pmlmeinfo->bwmode_updated)
++ return;
++
++
++ DBG_871X("%s\n", __FUNCTION__);
++
++
++ category = RTW_WLAN_CATEGORY_PUBLIC;
++ action = ACT_PUBLIC_BSSCOEXIST;
++
++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL)
++ {
++ return;
++ }
++
++ //update attribute
++ pattrib = &pmgntframe->attrib;
++ update_mgntframe_attrib(padapter, pattrib);
++
++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++ fctrl = &(pwlanhdr->frame_ctl);
++ *(fctrl) = 0;
++
++ _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
++
++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
++ pmlmeext->mgnt_seq++;
++ SetFrameSubType(pframe, WIFI_ACTION);
++
++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
++ pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++
++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
++ pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));
++
++
++ //
++ if(pmlmepriv->num_FortyMHzIntolerant>0)
++ {
++ u8 iedata=0;
++
++ iedata |= BIT(2);//20 MHz BSS Width Request
++
++ pframe = rtw_set_ie(pframe, EID_BSSCoexistence, 1, &iedata, &(pattrib->pktlen));
++
++ }
++
++
++ //
++ _rtw_memset(ICS, 0, sizeof(ICS));
++ if(pmlmepriv->num_sta_no_ht>0)
++ {
++ int i;
++
++ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++
++ phead = get_list_head(queue);
++ plist = get_next(phead);
++
++ while(1)
++ {
++ int len;
++ u8 *p;
++ WLAN_BSSID_EX *pbss_network;
++
++ if (rtw_end_of_queue_search(phead,plist)== _TRUE)
++ break;
++
++ pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
++
++ plist = get_next(plist);
++
++ pbss_network = (WLAN_BSSID_EX *)&pnetwork->network;
++
++ p = rtw_get_ie(pbss_network->IEs + _FIXED_IE_LENGTH_, _HT_CAPABILITY_IE_, &len, pbss_network->IELength - _FIXED_IE_LENGTH_);
++ if((p==NULL) || (len==0))//non-HT
++ {
++ if((pbss_network->Configuration.DSConfig<=0) || (pbss_network->Configuration.DSConfig>14))
++ continue;
++
++ ICS[0][pbss_network->Configuration.DSConfig]=1;
++
++ if(ICS[0][0] == 0)
++ ICS[0][0] = 1;
++ }
++
++ }
++
++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++
++
++ for(i= 0;i<8;i++)
++ {
++ if(ICS[i][0] == 1)
++ {
++ int j, k = 0;
++
++ InfoContent[k] = i;
++ //SET_BSS_INTOLERANT_ELE_REG_CLASS(InfoContent,i);
++ k++;
++
++ for(j=1;j<=14;j++)
++ {
++ if(ICS[i][j]==1)
++ {
++ if(k<16)
++ {
++ InfoContent[k] = j; //channel number
++ //SET_BSS_INTOLERANT_ELE_CHANNEL(InfoContent+k, j);
++ k++;
++ }
++ }
++ }
++
++ pframe = rtw_set_ie(pframe, EID_BSSIntolerantChlReport, k, InfoContent, &(pattrib->pktlen));
++
++ }
++
++ }
++
++
++ }
++
++
++ pattrib->last_txcmdsz = pattrib->pktlen;
++
++ dump_mgntframe(padapter, pmgntframe);
++
++}
++
++unsigned int send_delba(_adapter *padapter, u8 initiator, u8 *addr)
++{
++ struct sta_priv *pstapriv = &padapter->stapriv;
++ struct sta_info *psta = NULL;
++ //struct recv_reorder_ctrl *preorder_ctrl;
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ u16 tid;
++
++ if((pmlmeinfo->state&0x03) != WIFI_FW_AP_STATE)
++ if (!(pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS))
++ return _SUCCESS;
++
++ psta = rtw_get_stainfo(pstapriv, addr);
++ if(psta==NULL)
++ return _SUCCESS;
++
++ //DBG_871X("%s:%s\n", __FUNCTION__, (initiator==0)?"RX_DIR":"TX_DIR");
++
++ if(initiator==0) // recipient
++ {
++ for(tid = 0;tid<MAXTID;tid++)
++ {
++ if(psta->recvreorder_ctrl[tid].enable == _TRUE)
++ {
++ DBG_871X("rx agg disable tid(%d)\n",tid);
++ issue_action_BA(padapter, addr, RTW_WLAN_ACTION_DELBA, (((tid <<1) |initiator)&0x1F));
++ psta->recvreorder_ctrl[tid].enable = _FALSE;
++ psta->recvreorder_ctrl[tid].indicate_seq = 0xffff;
++ #ifdef DBG_RX_SEQ
++ DBG_871X("DBG_RX_SEQ %s:%d indicate_seq:%u \n", __FUNCTION__, __LINE__,
++ psta->recvreorder_ctrl[tid].indicate_seq);
++ #endif
++ }
++ }
++ }
++ else if(initiator == 1)// originator
++ {
++ //DBG_871X("tx agg_enable_bitmap(0x%08x)\n", psta->htpriv.agg_enable_bitmap);
++ for(tid = 0;tid<MAXTID;tid++)
++ {
++ if(psta->htpriv.agg_enable_bitmap & BIT(tid))
++ {
++ DBG_871X("tx agg disable tid(%d)\n",tid);
++ issue_action_BA(padapter, addr, RTW_WLAN_ACTION_DELBA, (((tid <<1) |initiator)&0x1F) );
++ psta->htpriv.agg_enable_bitmap &= ~BIT(tid);
++ psta->htpriv.candidate_tid_bitmap &= ~BIT(tid);
++
++ }
++ }
++ }
++
++ return _SUCCESS;
++
++}
++
++unsigned int send_beacon(_adapter *padapter)
++{
++ u8 bxmitok = _FALSE;
++ int issue=0;
++ int poll = 0;
++//#ifdef CONFIG_CONCURRENT_MODE
++ //struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++ //struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ //_adapter *pbuddy_adapter = padapter->pbuddy_adapter;
++ //struct mlme_priv *pbuddy_mlmepriv = &(pbuddy_adapter->mlmepriv);
++//#endif
++
++#ifdef CONFIG_PCI_HCI
++
++ //DBG_871X("%s\n", __FUNCTION__);
++
++ issue_beacon(padapter);
++
++ return _SUCCESS;
++
++#endif
++
++#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
++ u32 start = rtw_get_current_time();
++
++ rtw_hal_set_hwreg(padapter, HW_VAR_BCN_VALID, NULL);
++ do{
++ issue_beacon(padapter);
++ issue++;
++ do {
++ rtw_yield_os();
++ rtw_hal_get_hwreg(padapter, HW_VAR_BCN_VALID, (u8 *)(&bxmitok));
++ poll++;
++ }while((poll%10)!=0 && _FALSE == bxmitok && !padapter->bSurpriseRemoved && !padapter->bDriverStopped);
++
++ }while(_FALSE == bxmitok && issue<100 && !padapter->bSurpriseRemoved && !padapter->bDriverStopped);
++
++ if(padapter->bSurpriseRemoved || padapter->bDriverStopped)
++ {
++ return _FAIL;
++ }
++ if(_FALSE == bxmitok)
++ {
++ DBG_871X("%s fail! %u ms\n", __FUNCTION__, rtw_get_passing_time_ms(start));
++ return _FAIL;
++ }
++ else
++ {
++ u32 passing_time = rtw_get_passing_time_ms(start);
++
++ if(passing_time > 100 || issue > 3)
++ DBG_871X("%s success, issue:%d, poll:%d, %u ms\n", __FUNCTION__, issue, poll, rtw_get_passing_time_ms(start));
++ //else
++ // DBG_871X("%s success, issue:%d, poll:%d, %u ms\n", __FUNCTION__, issue, poll, rtw_get_passing_time_ms(start));
++
++ return _SUCCESS;
++ }
++
++#endif
++
++}
++
++/****************************************************************************
++
++Following are some utitity fuctions for WiFi MLME
++
++*****************************************************************************/
++
++BOOLEAN IsLegal5GChannel(
++ IN PADAPTER Adapter,
++ IN u8 channel)
++{
++
++ int i=0;
++ u8 Channel_5G[45] = {36,38,40,42,44,46,48,50,52,54,56,58,
++ 60,62,64,100,102,104,106,108,110,112,114,116,118,120,122,
++ 124,126,128,130,132,134,136,138,140,149,151,153,155,157,159,
++ 161,163,165};
++ for(i=0;i<sizeof(Channel_5G);i++)
++ if(channel == Channel_5G[i])
++ return _TRUE;
++ return _FALSE;
++}
++
++void site_survey(_adapter *padapter)
++{
++ unsigned char survey_channel = 0, val8;
++ RT_SCAN_TYPE ScanType = SCAN_PASSIVE;
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ u32 initialgain = 0;
++ u8 restore_initial_gain = 1;
++
++#ifdef CONFIG_P2P
++
++#ifdef CONFIG_CONCURRENT_MODE
++
++#ifdef CONFIG_STA_MODE_SCAN_UNDER_AP_MODE
++ u8 stay_buddy_ch = 0;
++#endif //CONFIG_STA_MODE_SCAN_UNDER_AP_MODE
++
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ PADAPTER pbuddy_adapter = padapter->pbuddy_adapter;
++ struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv;
++
++#endif //CONFIG_CONCURRENT_MODE
++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo);
++ static unsigned char prev_survey_channel = 0;
++ static unsigned int p2p_scan_count = 0;
++
++
++ if ( ( pwdinfo->rx_invitereq_info.scan_op_ch_only ) || ( pwdinfo->p2p_info.scan_op_ch_only ) )
++ {
++ if ( pwdinfo->rx_invitereq_info.scan_op_ch_only )
++ {
++ survey_channel = pwdinfo->rx_invitereq_info.operation_ch[pmlmeext->sitesurvey_res.channel_idx];
++ }
++ else
++ {
++ survey_channel = pwdinfo->p2p_info.operation_ch[pmlmeext->sitesurvey_res.channel_idx];
++ }
++ ScanType = SCAN_ACTIVE;
++ }
++ else if(rtw_p2p_findphase_ex_is_social(pwdinfo))
++ {
++ // Commented by Albert 2011/06/03
++ // The driver is in the find phase, it should go through the social channel.
++ int ch_set_idx;
++ survey_channel = pwdinfo->social_chan[pmlmeext->sitesurvey_res.channel_idx];
++ ch_set_idx = rtw_ch_set_search_ch(pmlmeext->channel_set, survey_channel);
++ if (ch_set_idx >= 0)
++ ScanType = pmlmeext->channel_set[ch_set_idx].ScanType;
++ else
++ ScanType = SCAN_ACTIVE;
++ }
++ else
++#endif //CONFIG_P2P
++ {
++ struct rtw_ieee80211_channel *ch;
++ if (pmlmeext->sitesurvey_res.channel_idx < pmlmeext->sitesurvey_res.ch_num) {
++ ch = &pmlmeext->sitesurvey_res.ch[pmlmeext->sitesurvey_res.channel_idx];
++ survey_channel = ch->hw_value;
++ ScanType = (ch->flags & RTW_IEEE80211_CHAN_PASSIVE_SCAN) ? SCAN_PASSIVE : SCAN_ACTIVE;
++ }
++ }
++
++ if (0)
++ DBG_871X(FUNC_ADPT_FMT" ch:%u(cnt:%u,idx:%d) at %dms, %c%c%c\n"
++ , FUNC_ADPT_ARG(padapter)
++ , survey_channel
++ , pwdinfo->find_phase_state_exchange_cnt, pmlmeext->sitesurvey_res.channel_idx
++ , rtw_get_passing_time_ms(padapter->mlmepriv.scan_start_time)
++ , ScanType?'A':'P', pmlmeext->sitesurvey_res.scan_mode?'A':'P'
++ , pmlmeext->sitesurvey_res.ssid[0].SsidLength?'S':' '
++ );
++
++ if(survey_channel != 0)
++ {
++ //PAUSE 4-AC Queue when site_survey
++ //rtw_hal_get_hwreg(padapter, HW_VAR_TXPAUSE, (u8 *)(&val8));
++ //val8 |= 0x0f;
++ //rtw_hal_set_hwreg(padapter, HW_VAR_TXPAUSE, (u8 *)(&val8));
++#ifdef CONFIG_CONCURRENT_MODE
++#ifdef CONFIG_STA_MODE_SCAN_UNDER_AP_MODE
++ if((padapter->pbuddy_adapter->mlmeextpriv.mlmext_info.state&0x03) == WIFI_FW_AP_STATE)
++ {
++ if( pmlmeinfo->scan_cnt == RTW_SCAN_NUM_OF_CH )
++ {
++ pmlmeinfo->scan_cnt = 0;
++ survey_channel = pbuddy_mlmeext->cur_channel;
++ stay_buddy_ch = 1;
++ }
++ else
++ {
++ if( pmlmeinfo->scan_cnt == 0 )
++ stay_buddy_ch = 2;
++ pmlmeinfo->scan_cnt++;
++ }
++ }
++#endif //CONFIG_STA_MODE_SCAN_UNDER_AP_MODE
++#endif //CONFIG_CONCURRENT_MODE
++ if(pmlmeext->sitesurvey_res.channel_idx == 0)
++ {
++ set_channel_bwmode(padapter, survey_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HT_CHANNEL_WIDTH_20);
++ }
++ else
++ {
++ SelectChannel(padapter, survey_channel);
++ }
++
++#ifdef CONFIG_STA_MODE_SCAN_UNDER_AP_MODE
++ if( stay_buddy_ch == 1 )
++ {
++ val8 = 0; //survey done
++ rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));
++
++ if(check_buddy_mlmeinfo_state(padapter, WIFI_FW_AP_STATE) &&
++ check_buddy_fwstate(padapter, _FW_LINKED))
++ {
++ update_beacon(padapter->pbuddy_adapter, 0, NULL, _TRUE);
++ }
++ }
++ else if( stay_buddy_ch == 2 )
++ {
++ val8 = 1; //under site survey
++ rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));
++ }
++#endif //CONFIG_STA_MODE_SCAN_UNDER_AP_MODE
++
++ if(ScanType == SCAN_ACTIVE) //obey the channel plan setting...
++ {
++ #ifdef CONFIG_P2P
++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_SCAN) ||
++ rtw_p2p_chk_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH)
++ )
++ {
++ issue_probereq_p2p(padapter, NULL);
++ issue_probereq_p2p(padapter, NULL);
++ issue_probereq_p2p(padapter, NULL);
++ }
++ else
++ #endif //CONFIG_P2P
++ {
++ int i;
++ for(i=0;i<RTW_SSID_SCAN_AMOUNT;i++){
++ if(pmlmeext->sitesurvey_res.ssid[i].SsidLength) {
++ //todo: to issue two probe req???
++ issue_probereq(padapter, &(pmlmeext->sitesurvey_res.ssid[i]), NULL);
++ //rtw_msleep_os(SURVEY_TO>>1);
++ issue_probereq(padapter, &(pmlmeext->sitesurvey_res.ssid[i]), NULL);
++ } else {
++ break;
++ }
++ }
++
++ if(pmlmeext->sitesurvey_res.scan_mode == SCAN_ACTIVE) {
++ //todo: to issue two probe req???
++ issue_probereq(padapter, NULL, NULL);
++ //rtw_msleep_os(SURVEY_TO>>1);
++ issue_probereq(padapter, NULL, NULL);
++ }
++ }
++ }
++
++#ifdef CONFIG_STA_MODE_SCAN_UNDER_AP_MODE
++ if( stay_buddy_ch == 1 )
++ set_survey_timer(pmlmeext, pmlmeext->chan_scan_time * RTW_STAY_AP_CH_MILLISECOND );
++ else
++#endif //CONFIG_STA_MODE_SCAN_UNDER_AP_MODE
++ set_survey_timer(pmlmeext, pmlmeext->chan_scan_time);
++
++ }
++ else
++ {
++
++ // channel number is 0 or this channel is not valid.
++
++#ifdef CONFIG_CONCURRENT_MODE
++ u8 cur_channel;
++ u8 cur_bwmode;
++ u8 cur_ch_offset;
++
++ if (rtw_get_ch_setting_union(padapter, &cur_channel, &cur_bwmode, &cur_ch_offset) != 0)
++ {
++ if (0)
++ DBG_871X(FUNC_ADPT_FMT" back to linked union - ch:%u, bw:%u, offset:%u\n",
++ FUNC_ADPT_ARG(padapter), cur_channel, cur_bwmode, cur_ch_offset);
++ }
++ #ifdef CONFIG_IOCTL_CFG80211
++ else if(padapter->pbuddy_adapter
++ && pbuddy_adapter->wdinfo.driver_interface == DRIVER_CFG80211
++ && wdev_to_priv(pbuddy_adapter->rtw_wdev)->p2p_enabled
++ && rtw_p2p_chk_state(&pbuddy_adapter->wdinfo, P2P_STATE_LISTEN)
++ )
++ {
++ cur_channel = pbuddy_adapter->wdinfo.listen_channel;
++ cur_bwmode = pbuddy_mlmeext->cur_bwmode;
++ cur_ch_offset = pbuddy_mlmeext->cur_ch_offset;
++ }
++ #endif
++ else
++ {
++ cur_channel = pmlmeext->cur_channel;
++ cur_bwmode = pmlmeext->cur_bwmode;
++ cur_ch_offset = pmlmeext->cur_ch_offset;
++ }
++#endif
++
++
++#ifdef CONFIG_P2P
++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_SCAN) || rtw_p2p_chk_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH))
++ {
++ if( ( pwdinfo->rx_invitereq_info.scan_op_ch_only ) || ( pwdinfo->p2p_info.scan_op_ch_only ) )
++ {
++ // Set the find_phase_state_exchange_cnt to P2P_FINDPHASE_EX_CNT.
++ // This will let the following flow to run the scanning end.
++ rtw_p2p_findphase_ex_set(pwdinfo, P2P_FINDPHASE_EX_MAX);
++ }
++ #ifdef CONFIG_DBG_P2P
++ DBG_871X( "[%s] find phase exchange cnt = %d\n", __FUNCTION__, pwdinfo->find_phase_state_exchange_cnt );
++ #endif
++ }
++
++ if(rtw_p2p_findphase_ex_is_needed(pwdinfo))
++ {
++ // Set the P2P State to the listen state of find phase and set the current channel to the listen channel
++ set_channel_bwmode(padapter, pwdinfo->listen_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HT_CHANNEL_WIDTH_20);
++ rtw_p2p_set_state(pwdinfo, P2P_STATE_FIND_PHASE_LISTEN);
++ pmlmeext->sitesurvey_res.state = SCAN_DISABLE;
++
++ //turn on dynamic functions
++ Restore_DM_Func_Flag(padapter);
++ //Switch_DM_Func(padapter, DYNAMIC_FUNC_DIG|DYNAMIC_FUNC_HP|DYNAMIC_FUNC_SS, _TRUE);
++
++ _set_timer( &pwdinfo->find_phase_timer, ( u32 ) ( ( u32 ) ( pwdinfo->listen_dwell ) * 100 ) );
++ }
++ else
++#endif //CONFIG_P2P
++ {
++
++#ifdef CONFIG_STA_MODE_SCAN_UNDER_AP_MODE
++ pmlmeinfo->scan_cnt = 0;
++#endif //CONFIG_DMP_STA_NODE_SCAN_UNDER_AP_MODE
++
++#ifdef CONFIG_ANTENNA_DIVERSITY
++ // 20100721:Interrupt scan operation here.
++ // For SW antenna diversity before link, it needs to switch to another antenna and scan again.
++ // It compares the scan result and select beter one to do connection.
++ if(rtw_hal_antdiv_before_linked(padapter))
++ {
++ pmlmeext->sitesurvey_res.bss_cnt = 0;
++ pmlmeext->sitesurvey_res.channel_idx = -1;
++ pmlmeext->chan_scan_time = SURVEY_TO /2;
++ set_survey_timer(pmlmeext, pmlmeext->chan_scan_time);
++ return;
++ }
++#endif
++
++#ifdef CONFIG_P2P
++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_SCAN) || rtw_p2p_chk_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH))
++ {
++ #ifdef CONFIG_CONCURRENT_MODE
++ if( pwdinfo->driver_interface == DRIVER_WEXT )
++ {
++ if ( check_buddy_fwstate(padapter, _FW_LINKED ) )
++ {
++ _set_timer( &pwdinfo->ap_p2p_switch_timer, 500 );
++ }
++ }
++ rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo));
++ #else
++ rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo));
++ #endif
++ }
++ rtw_p2p_findphase_ex_set(pwdinfo, P2P_FINDPHASE_EX_NONE);
++#endif //CONFIG_P2P
++
++ pmlmeext->sitesurvey_res.state = SCAN_COMPLETE;
++
++ //switch back to the original channel
++ //SelectChannel(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset);
++
++ {
++#ifdef CONFIG_CONCURRENT_MODE
++ set_channel_bwmode(padapter, cur_channel, cur_ch_offset, cur_bwmode);
++#else
++#ifdef CONFIG_DUALMAC_CONCURRENT
++ dc_set_channel_bwmode_survey_done(padapter);
++#else
++ if( pwdinfo->driver_interface == DRIVER_WEXT )
++ {
++ if( rtw_p2p_chk_state(pwdinfo, P2P_STATE_LISTEN) )
++ {
++ set_channel_bwmode(padapter, pwdinfo->listen_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HT_CHANNEL_WIDTH_20);
++ }
++ else
++ set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode);
++ }
++ else if( pwdinfo->driver_interface == DRIVER_CFG80211 )
++ {
++ set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode);
++ }
++#endif //CONFIG_DUALMAC_CONCURRENT
++#endif //CONFIG_CONCURRENT_MODE
++ }
++
++ //flush 4-AC Queue after site_survey
++ //val8 = 0;
++ //rtw_hal_set_hwreg(padapter, HW_VAR_TXPAUSE, (u8 *)(&val8));
++
++ val8 = 0; //survey done
++ rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));
++
++ //config MSR
++ Set_MSR(padapter, (pmlmeinfo->state & 0x3));
++
++
++#ifdef CONFIG_IOCTL_CFG80211
++ if((wdev_to_priv(padapter->rtw_wdev))->p2p_enabled == _TRUE)
++ {
++ restore_initial_gain = 0;
++ }
++#endif //CONFIG_IOCTL_CFG80211
++
++ if(restore_initial_gain == 1)
++ {
++ initialgain = 0xff; //restore RX GAIN
++ rtw_hal_set_hwreg(padapter, HW_VAR_INITIAL_GAIN, (u8 *)(&initialgain));
++ }
++
++ //turn on dynamic functions
++ Restore_DM_Func_Flag(padapter);
++ //Switch_DM_Func(padapter, DYNAMIC_FUNC_DIG|DYNAMIC_FUNC_HP|DYNAMIC_FUNC_SS, _TRUE);
++
++ if (is_client_associated_to_ap(padapter) == _TRUE)
++ {
++ issue_nulldata(padapter, NULL, 0, 3, 500);
++
++#ifdef CONFIG_CONCURRENT_MODE
++ if(is_client_associated_to_ap(padapter->pbuddy_adapter) == _TRUE)
++ {
++ DBG_871X("adapter is surveydone(buddy_adapter is linked), issue nulldata(pwrbit=0)\n");
++
++ issue_nulldata(padapter->pbuddy_adapter, NULL, 0, 3, 500);
++ }
++#endif
++ }
++#ifdef CONFIG_CONCURRENT_MODE
++ else if(is_client_associated_to_ap(padapter->pbuddy_adapter) == _TRUE)
++ {
++ issue_nulldata(padapter->pbuddy_adapter, NULL, 0, 3, 500);
++ }
++#endif
++
++ report_surveydone_event(padapter);
++
++ pmlmeext->chan_scan_time = SURVEY_TO;
++ pmlmeext->sitesurvey_res.state = SCAN_DISABLE;
++
++ issue_action_BSSCoexistPacket(padapter);
++ issue_action_BSSCoexistPacket(padapter);
++ issue_action_BSSCoexistPacket(padapter);
++
++ }
++
++#ifdef CONFIG_CONCURRENT_MODE
++ if(check_buddy_mlmeinfo_state(padapter, WIFI_FW_AP_STATE) &&
++ check_buddy_fwstate(padapter, _FW_LINKED))
++ {
++
++ DBG_871X("survey done, current CH=%d, BW=%d, offset=%d\n", cur_channel, cur_bwmode, cur_ch_offset);
++
++ DBG_871X("restart pbuddy_adapter's beacon\n");
++
++ update_beacon(padapter->pbuddy_adapter, 0, NULL, _TRUE);
++ }
++#endif
++
++ }
++
++ return;
++
++}
++
++//collect bss info from Beacon and Probe response frames.
++u8 collect_bss_info(_adapter *padapter, union recv_frame *precv_frame, WLAN_BSSID_EX *bssid)
++{
++ int i;
++ u32 len;
++ u8 *p;
++ u16 val16, subtype;
++ u8 *pframe = precv_frame->u.hdr.rx_data;
++ u32 packet_len = precv_frame->u.hdr.len;
++ struct registry_priv *pregistrypriv = &padapter->registrypriv;
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++
++ len = packet_len - sizeof(struct rtw_ieee80211_hdr_3addr);
++
++ if (len > MAX_IE_SZ)
++ {
++ //DBG_871X("IE too long for survey event\n");
++ return _FAIL;
++ }
++
++ _rtw_memset(bssid, 0, sizeof(WLAN_BSSID_EX));
++
++ subtype = GetFrameSubType(pframe);
++
++ if(subtype==WIFI_BEACON)
++ bssid->Reserved[0] = 1;
++ else
++ bssid->Reserved[0] = 0;
++
++ bssid->Length = sizeof(WLAN_BSSID_EX) - MAX_IE_SZ + len;
++
++ //below is to copy the information element
++ bssid->IELength = len;
++ _rtw_memcpy(bssid->IEs, (pframe + sizeof(struct rtw_ieee80211_hdr_3addr)), bssid->IELength);
++
++ //get the signal strength
++ bssid->PhyInfo.SignalQuality = precv_frame->u.hdr.attrib.signal_qual;//in percentage
++ bssid->PhyInfo.SignalStrength = precv_frame->u.hdr.attrib.signal_strength;//in percentage
++ bssid->Rssi = precv_frame->u.hdr.attrib.RecvSignalPower; // in dBM.raw data
++
++#ifdef CONFIG_ANTENNA_DIVERSITY
++ //rtw_hal_get_hwreg(padapter, HW_VAR_CURRENT_ANTENNA, (u8 *)(&bssid->PhyInfo.Optimum_antenna));
++ rtw_hal_get_def_var(padapter, HAL_DEF_CURRENT_ANTENNA, &bssid->PhyInfo.Optimum_antenna);
++#endif
++
++ // checking SSID
++ if ((p = rtw_get_ie(bssid->IEs + _FIXED_IE_LENGTH_, _SSID_IE_, &len, bssid->IELength - _FIXED_IE_LENGTH_)) == NULL)
++ {
++ DBG_871X("marc: cannot find SSID for survey event\n");
++ return _FAIL;
++ }
++
++ if (*(p + 1))
++ {
++ if (len > NDIS_802_11_LENGTH_SSID)
++ {
++ DBG_871X("%s()-%d: IE too long (%d) for survey event\n", __FUNCTION__, __LINE__, len);
++ return _FAIL;
++ }
++ _rtw_memcpy(bssid->Ssid.Ssid, (p + 2), *(p + 1));
++ bssid->Ssid.SsidLength = *(p + 1);
++ }
++ else
++ {
++ bssid->Ssid.SsidLength = 0;
++ }
++
++ _rtw_memset(bssid->SupportedRates, 0, NDIS_802_11_LENGTH_RATES_EX);
++
++ //checking rate info...
++ i = 0;
++ p = rtw_get_ie(bssid->IEs + _FIXED_IE_LENGTH_, _SUPPORTEDRATES_IE_, &len, bssid->IELength - _FIXED_IE_LENGTH_);
++ if (p != NULL)
++ {
++ if (len > NDIS_802_11_LENGTH_RATES_EX)
++ {
++ DBG_871X("%s()-%d: IE too long (%d) for survey event\n", __FUNCTION__, __LINE__, len);
++ return _FAIL;
++ }
++ _rtw_memcpy(bssid->SupportedRates, (p + 2), len);
++ i = len;
++ }
++
++ p = rtw_get_ie(bssid->IEs + _FIXED_IE_LENGTH_, _EXT_SUPPORTEDRATES_IE_, &len, bssid->IELength - _FIXED_IE_LENGTH_);
++ if (p != NULL)
++ {
++ if (len > (NDIS_802_11_LENGTH_RATES_EX-i))
++ {
++ DBG_871X("%s()-%d: IE too long (%d) for survey event\n", __FUNCTION__, __LINE__, len);
++ return _FAIL;
++ }
++ _rtw_memcpy(bssid->SupportedRates + i, (p + 2), len);
++ }
++
++ //todo:
++#if 0
++ if (judge_network_type(bssid->SupportedRates, (len + i)) == WIRELESS_11B)
++ {
++ bssid->NetworkTypeInUse = Ndis802_11DS;
++ }
++ else
++#endif
++ {
++ bssid->NetworkTypeInUse = Ndis802_11OFDM24;
++ }
++
++ if (bssid->IELength < 12)
++ return _FAIL;
++
++ // Checking for DSConfig
++ p = rtw_get_ie(bssid->IEs + _FIXED_IE_LENGTH_, _DSSET_IE_, &len, bssid->IELength - _FIXED_IE_LENGTH_);
++
++ bssid->Configuration.DSConfig = 0;
++ bssid->Configuration.Length = 0;
++
++ if (p)
++ {
++ bssid->Configuration.DSConfig = *(p + 2);
++ }
++ else
++ {// In 5G, some ap do not have DSSET IE
++ // checking HT info for channel
++ p = rtw_get_ie(bssid->IEs + _FIXED_IE_LENGTH_, _HT_ADD_INFO_IE_, &len, bssid->IELength - _FIXED_IE_LENGTH_);
++ if(p)
++ {
++ struct HT_info_element *HT_info = (struct HT_info_element *)(p + 2);
++ bssid->Configuration.DSConfig = HT_info->primary_channel;
++ }
++ else
++ { // use current channel
++ bssid->Configuration.DSConfig = rtw_get_oper_ch(padapter);
++ }
++ }
++
++ _rtw_memcpy(&bssid->Configuration.BeaconPeriod, rtw_get_beacon_interval_from_ie(bssid->IEs), 2);
++ bssid->Configuration.BeaconPeriod = le32_to_cpu(bssid->Configuration.BeaconPeriod);
++
++ val16 = rtw_get_capability((WLAN_BSSID_EX *)bssid);
++
++ if (val16 & BIT(0))
++ {
++ bssid->InfrastructureMode = Ndis802_11Infrastructure;
++ _rtw_memcpy(bssid->MacAddress, GetAddr2Ptr(pframe), ETH_ALEN);
++ }
++ else
++ {
++ bssid->InfrastructureMode = Ndis802_11IBSS;
++ _rtw_memcpy(bssid->MacAddress, GetAddr3Ptr(pframe), ETH_ALEN);
++ }
++
++ if (val16 & BIT(4))
++ bssid->Privacy = 1;
++ else
++ bssid->Privacy = 0;
++
++ bssid->Configuration.ATIMWindow = 0;
++
++ //20/40 BSS Coexistence check
++ if((pregistrypriv->wifi_spec==1) && (_FALSE == pmlmeinfo->bwmode_updated))
++ {
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++
++ p = rtw_get_ie(bssid->IEs + _FIXED_IE_LENGTH_, _HT_CAPABILITY_IE_, &len, bssid->IELength - _FIXED_IE_LENGTH_);
++ if(p && len>0)
++ {
++ struct HT_caps_element *pHT_caps;
++ pHT_caps = (struct HT_caps_element *)(p + 2);
++
++ if(pHT_caps->u.HT_cap_element.HT_caps_info&BIT(14))
++ {
++ pmlmepriv->num_FortyMHzIntolerant++;
++ }
++ }
++ else
++ {
++ pmlmepriv->num_sta_no_ht++;
++ }
++
++ }
++
++#ifdef CONFIG_INTEL_WIDI
++ //process_intel_widi_query_or_tigger(padapter, bssid);
++ if(process_intel_widi_query_or_tigger(padapter, bssid))
++ {
++ return _FAIL;
++ }
++#endif // CONFIG_INTEL_WIDI
++
++ #if defined(DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED) & 1
++ if(strcmp(bssid->Ssid.Ssid, DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED) == 0) {
++ DBG_871X("Receiving %s("MAC_FMT", DSConfig:%u) from ch%u with ss:%3u, sq:%3u, RawRSSI:%3ld\n"
++ , bssid->Ssid.Ssid, MAC_ARG(bssid->MacAddress), bssid->Configuration.DSConfig
++ , rtw_get_oper_ch(padapter)
++ , bssid->PhyInfo.SignalStrength, bssid->PhyInfo.SignalQuality, bssid->Rssi
++ );
++ }
++ #endif
++
++ // mark bss info receving from nearby channel as SignalQuality 101
++ if(bssid->Configuration.DSConfig != rtw_get_oper_ch(padapter))
++ {
++ bssid->PhyInfo.SignalQuality= 101;
++ }
++
++ return _SUCCESS;
++}
++
++void start_create_ibss(_adapter* padapter)
++{
++ unsigned short caps;
++ u8 val8;
++ u8 join_type;
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX*)(&(pmlmeinfo->network));
++ pmlmeext->cur_channel = (u8)pnetwork->Configuration.DSConfig;
++ pmlmeinfo->bcn_interval = get_beacon_interval(pnetwork);
++
++ //update wireless mode
++ update_wireless_mode(padapter);
++
++ //udpate capability
++ caps = rtw_get_capability((WLAN_BSSID_EX *)pnetwork);
++ update_capinfo(padapter, caps);
++ if(caps&cap_IBSS)//adhoc master
++ {
++ //set_opmode_cmd(padapter, adhoc);//removed
++
++ val8 = 0xcf;
++ rtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, (u8 *)(&val8));
++
++ //switch channel
++ //SelectChannel(padapter, pmlmeext->cur_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE);
++ set_channel_bwmode(padapter, pmlmeext->cur_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HT_CHANNEL_WIDTH_20);
++
++ beacon_timing_control(padapter);
++
++ //set msr to WIFI_FW_ADHOC_STATE
++ pmlmeinfo->state = WIFI_FW_ADHOC_STATE;
++ Set_MSR(padapter, (pmlmeinfo->state & 0x3));
++
++ //issue beacon
++ if(send_beacon(padapter)==_FAIL)
++ {
++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("issuing beacon frame fail....\n"));
++
++ report_join_res(padapter, -1);
++ pmlmeinfo->state = WIFI_FW_NULL_STATE;
++ }
++ else
++ {
++ rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, padapter->registrypriv.dev_network.MacAddress);
++ join_type = 0;
++ rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type));
++
++ report_join_res(padapter, 1);
++ pmlmeinfo->state |= WIFI_FW_ASSOC_SUCCESS;
++ }
++ }
++ else
++ {
++ DBG_871X("start_create_ibss, invalid cap:%x\n", caps);
++ return;
++ }
++
++}
++
++void start_clnt_join(_adapter* padapter)
++{
++ unsigned short caps;
++ u8 val8;
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX*)(&(pmlmeinfo->network));
++
++ //update wireless mode
++ update_wireless_mode(padapter);
++
++ //udpate capability
++ caps = rtw_get_capability((WLAN_BSSID_EX *)pnetwork);
++ update_capinfo(padapter, caps);
++ if (caps&cap_ESS)
++ {
++ Set_MSR(padapter, WIFI_FW_STATION_STATE);
++
++ val8 = (pmlmeinfo->auth_algo == dot11AuthAlgrthm_8021X)? 0xcc: 0xcf;
++ rtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, (u8 *)(&val8));
++
++ #ifdef CONFIG_DEAUTH_BEFORE_CONNECT
++ // Because of AP's not receiving deauth before
++ // AP may: 1)not response auth or 2)deauth us after link is complete
++ // issue deauth before issuing auth to deal with the situation
++
++ // Commented by Albert 2012/07/21
++ // For the Win8 P2P connection, it will be hard to have a successful connection if this Wi-Fi doesn't connect to it.
++ {
++ #ifdef CONFIG_P2P
++ _queue *queue = &(padapter->mlmepriv.scanned_queue);
++ _list *head = get_list_head(queue);
++ _list *pos = get_next(head);
++ struct wlan_network *scanned = NULL;
++ u8 ie_offset = 0;
++ _irqL irqL;
++ bool has_p2p_ie = _FALSE;
++
++ _enter_critical_bh(&(padapter->mlmepriv.scanned_queue.lock), &irqL);
++
++ for (pos = get_next(head);!rtw_end_of_queue_search(head, pos); pos = get_next(pos)) {
++
++ scanned = LIST_CONTAINOR(pos, struct wlan_network, list);
++ if(scanned==NULL)
++ rtw_warn_on(1);
++
++ if (_rtw_memcmp(&(scanned->network.Ssid), &(pnetwork->Ssid), sizeof(NDIS_802_11_SSID)) == _TRUE
++ && _rtw_memcmp(scanned->network.MacAddress, pnetwork->MacAddress, sizeof(NDIS_802_11_MAC_ADDRESS)) == _TRUE
++ ) {
++ ie_offset = (scanned->network.Reserved[0] == 2? 0:12);
++ if (rtw_get_p2p_ie(scanned->network.IEs+ie_offset, scanned->network.IELength-ie_offset, NULL, NULL))
++ has_p2p_ie = _TRUE;
++ break;
++ }
++ }
++
++ _exit_critical_bh(&(padapter->mlmepriv.scanned_queue.lock), &irqL);
++
++ if (scanned == NULL || rtw_end_of_queue_search(head, pos) || has_p2p_ie == _FALSE)
++ #endif /* CONFIG_P2P */
++ issue_deauth_ex(padapter, pnetwork->MacAddress, WLAN_REASON_DEAUTH_LEAVING, 5, 100);
++ }
++ #endif /* CONFIG_DEAUTH_BEFORE_CONNECT */
++
++ //here wait for receiving the beacon to start auth
++ //and enable a timer
++ set_link_timer(pmlmeext, decide_wait_for_beacon_timeout(pmlmeinfo->bcn_interval));
++
++ pmlmeinfo->state = WIFI_FW_AUTH_NULL | WIFI_FW_STATION_STATE;
++ }
++ else if (caps&cap_IBSS) //adhoc client
++ {
++ Set_MSR(padapter, WIFI_FW_ADHOC_STATE);
++
++ val8 = 0xcf;
++ rtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, (u8 *)(&val8));
++
++ //switch channel
++ set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode);
++
++ beacon_timing_control(padapter);
++
++ pmlmeinfo->state = WIFI_FW_ADHOC_STATE;
++
++ report_join_res(padapter, 1);
++ }
++ else
++ {
++ //DBG_871X("marc: invalid cap:%x\n", caps);
++ return;
++ }
++
++}
++
++void start_clnt_auth(_adapter* padapter)
++{
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++
++ _cancel_timer_ex(&pmlmeext->link_timer);
++
++ pmlmeinfo->state &= (~WIFI_FW_AUTH_NULL);
++ pmlmeinfo->state |= WIFI_FW_AUTH_STATE;
++
++ pmlmeinfo->auth_seq = 1;
++ pmlmeinfo->reauth_count = 0;
++ pmlmeinfo->reassoc_count = 0;
++ pmlmeinfo->link_count = 0;
++ pmlmeext->retry = 0;
++
++
++ issue_auth(padapter, NULL, 0);
++
++ set_link_timer(pmlmeext, REAUTH_TO);
++
++}
++
++
++void start_clnt_assoc(_adapter* padapter)
++{
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++
++ _cancel_timer_ex(&pmlmeext->link_timer);
++
++ pmlmeinfo->state &= (~(WIFI_FW_AUTH_NULL | WIFI_FW_AUTH_STATE));
++ pmlmeinfo->state |= (WIFI_FW_AUTH_SUCCESS | WIFI_FW_ASSOC_STATE);
++
++ issue_assocreq(padapter);
++
++ set_link_timer(pmlmeext, REASSOC_TO);
++}
++
++unsigned int receive_disconnect(_adapter *padapter, unsigned char *MacAddr, unsigned short reason)
++{
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++
++ //check A3
++ if (!(_rtw_memcmp(MacAddr, get_my_bssid(&pmlmeinfo->network), ETH_ALEN)))
++ return _SUCCESS;
++
++ DBG_871X("%s\n", __FUNCTION__);
++
++ if((pmlmeinfo->state&0x03) == WIFI_FW_STATION_STATE)
++ {
++ if (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)
++ {
++ pmlmeinfo->state = WIFI_FW_NULL_STATE;
++ report_del_sta_event(padapter, MacAddr, reason);
++
++ }
++ else if (pmlmeinfo->state & WIFI_FW_LINKING_STATE)
++ {
++ pmlmeinfo->state = WIFI_FW_NULL_STATE;
++ report_join_res(padapter, -2);
++ }
++ }
++
++ return _SUCCESS;
++}
++
++#ifdef CONFIG_80211D
++static void process_80211d(PADAPTER padapter, WLAN_BSSID_EX *bssid)
++{
++ struct registry_priv *pregistrypriv;
++ struct mlme_ext_priv *pmlmeext;
++ RT_CHANNEL_INFO *chplan_new;
++ u8 channel;
++ u8 i;
++
++
++ pregistrypriv = &padapter->registrypriv;
++ pmlmeext = &padapter->mlmeextpriv;
++
++ // Adjust channel plan by AP Country IE
++ if (pregistrypriv->enable80211d &&
++ (!pmlmeext->update_channel_plan_by_ap_done))
++ {
++ u8 *ie, *p;
++ u32 len;
++ RT_CHANNEL_PLAN chplan_ap;
++ RT_CHANNEL_INFO chplan_sta[MAX_CHANNEL_NUM];
++ u8 country[4];
++ u8 fcn; // first channel number
++ u8 noc; // number of channel
++ u8 j, k;
++
++ ie = rtw_get_ie(bssid->IEs + _FIXED_IE_LENGTH_, _COUNTRY_IE_, &len, bssid->IELength - _FIXED_IE_LENGTH_);
++ if (!ie) return;
++ if (len < 6) return;
++
++ ie += 2;
++ p = ie;
++ ie += len;
++
++ _rtw_memset(country, 0, 4);
++ _rtw_memcpy(country, p, 3);
++ p += 3;
++ RT_TRACE(_module_rtl871x_mlme_c_, _drv_notice_,
++ ("%s: 802.11d country=%s\n", __FUNCTION__, country));
++
++ i = 0;
++ while ((ie - p) >= 3)
++ {
++ fcn = *(p++);
++ noc = *(p++);
++ p++;
++
++ for (j = 0; j < noc; j++)
++ {
++ if (fcn <= 14) channel = fcn + j; // 2.4 GHz
++ else channel = fcn + j*4; // 5 GHz
++
++ chplan_ap.Channel[i++] = channel;
++ }
++ }
++ chplan_ap.Len = i;
++
++#ifdef CONFIG_DEBUG_RTL871X
++#ifdef PLATFORM_LINUX
++ i = 0;
++ printk("%s: AP[%s] channel plan {", __func__, bssid->Ssid.Ssid);
++ while ((i < chplan_ap.Len) && (chplan_ap.Channel[i] != 0))
++ {
++ printk("%02d,", chplan_ap.Channel[i]);
++ i++;
++ }
++ printk("}\n");
++#endif
++#endif
++
++ _rtw_memcpy(chplan_sta, pmlmeext->channel_set, sizeof(chplan_sta));
++#ifdef CONFIG_DEBUG_RTL871X
++#ifdef PLATFORM_LINUX
++ i = 0;
++ printk("%s: STA channel plan {", __func__);
++ while ((i < MAX_CHANNEL_NUM) && (chplan_sta[i].ChannelNum != 0))
++ {
++ printk("%02d(%c),", chplan_sta[i].ChannelNum, chplan_sta[i].ScanType==SCAN_PASSIVE?'p':'a');
++ i++;
++ }
++ printk("}\n");
++#endif
++#endif
++
++ _rtw_memset(pmlmeext->channel_set, 0, sizeof(pmlmeext->channel_set));
++ chplan_new = pmlmeext->channel_set;
++
++ i = j = k = 0;
++ if (pregistrypriv->wireless_mode & WIRELESS_11G)
++ {
++ do {
++ if ((i == MAX_CHANNEL_NUM) ||
++ (chplan_sta[i].ChannelNum == 0) ||
++ (chplan_sta[i].ChannelNum > 14))
++ break;
++
++ if ((j == chplan_ap.Len) || (chplan_ap.Channel[j] > 14))
++ break;
++
++ if (chplan_sta[i].ChannelNum == chplan_ap.Channel[j])
++ {
++ chplan_new[k].ChannelNum = chplan_ap.Channel[j];
++ chplan_new[k].ScanType = SCAN_ACTIVE;
++ i++;
++ j++;
++ k++;
++ }
++ else if (chplan_sta[i].ChannelNum < chplan_ap.Channel[j])
++ {
++ chplan_new[k].ChannelNum = chplan_sta[i].ChannelNum;
++// chplan_new[k].ScanType = chplan_sta[i].ScanType;
++ chplan_new[k].ScanType = SCAN_PASSIVE;
++ i++;
++ k++;
++ }
++ else if (chplan_sta[i].ChannelNum > chplan_ap.Channel[j])
++ {
++ chplan_new[k].ChannelNum = chplan_ap.Channel[j];
++ chplan_new[k].ScanType = SCAN_ACTIVE;
++ j++;
++ k++;
++ }
++ } while (1);
++
++ // change AP not support channel to Passive scan
++ while ((i < MAX_CHANNEL_NUM) &&
++ (chplan_sta[i].ChannelNum != 0) &&
++ (chplan_sta[i].ChannelNum <= 14))
++ {
++ chplan_new[k].ChannelNum = chplan_sta[i].ChannelNum;
++// chplan_new[k].ScanType = chplan_sta[i].ScanType;
++ chplan_new[k].ScanType = SCAN_PASSIVE;
++ i++;
++ k++;
++ }
++
++ // add channel AP supported
++ while ((j < chplan_ap.Len) && (chplan_ap.Channel[j] <= 14))
++ {
++ chplan_new[k].ChannelNum = chplan_ap.Channel[j];
++ chplan_new[k].ScanType = SCAN_ACTIVE;
++ j++;
++ k++;
++ }
++ }
++ else
++ {
++ // keep original STA 2.4G channel plan
++ while ((i < MAX_CHANNEL_NUM) &&
++ (chplan_sta[i].ChannelNum != 0) &&
++ (chplan_sta[i].ChannelNum <= 14))
++ {
++ chplan_new[k].ChannelNum = chplan_sta[i].ChannelNum;
++ chplan_new[k].ScanType = chplan_sta[i].ScanType;
++ i++;
++ k++;
++ }
++
++ // skip AP 2.4G channel plan
++ while ((j < chplan_ap.Len) && (chplan_ap.Channel[j] <= 14))
++ {
++ j++;
++ }
++ }
++
++ if (pregistrypriv->wireless_mode & WIRELESS_11A)
++ {
++ do {
++ if ((i == MAX_CHANNEL_NUM) ||
++ (chplan_sta[i].ChannelNum == 0))
++ break;
++
++ if ((j == chplan_ap.Len) || (chplan_ap.Channel[j] == 0))
++ break;
++
++ if (chplan_sta[i].ChannelNum == chplan_ap.Channel[j])
++ {
++ chplan_new[k].ChannelNum = chplan_ap.Channel[j];
++ chplan_new[k].ScanType = SCAN_ACTIVE;
++ i++;
++ j++;
++ k++;
++ }
++ else if (chplan_sta[i].ChannelNum < chplan_ap.Channel[j])
++ {
++ chplan_new[k].ChannelNum = chplan_sta[i].ChannelNum;
++// chplan_new[k].ScanType = chplan_sta[i].ScanType;
++ chplan_new[k].ScanType = SCAN_PASSIVE;
++ i++;
++ k++;
++ }
++ else if (chplan_sta[i].ChannelNum > chplan_ap.Channel[j])
++ {
++ chplan_new[k].ChannelNum = chplan_ap.Channel[j];
++ chplan_new[k].ScanType = SCAN_ACTIVE;
++ j++;
++ k++;
++ }
++ } while (1);
++
++ // change AP not support channel to Passive scan
++ while ((i < MAX_CHANNEL_NUM) && (chplan_sta[i].ChannelNum != 0))
++ {
++ chplan_new[k].ChannelNum = chplan_sta[i].ChannelNum;
++// chplan_new[k].ScanType = chplan_sta[i].ScanType;
++ chplan_new[k].ScanType = SCAN_PASSIVE;
++ i++;
++ k++;
++ }
++
++ // add channel AP supported
++ while ((j < chplan_ap.Len) && (chplan_ap.Channel[j] != 0))
++ {
++ chplan_new[k].ChannelNum = chplan_ap.Channel[j];
++ chplan_new[k].ScanType = SCAN_ACTIVE;
++ j++;
++ k++;
++ }
++ }
++ else
++ {
++ // keep original STA 5G channel plan
++ while ((i < MAX_CHANNEL_NUM) && (chplan_sta[i].ChannelNum != 0))
++ {
++ chplan_new[k].ChannelNum = chplan_sta[i].ChannelNum;
++ chplan_new[k].ScanType = chplan_sta[i].ScanType;
++ i++;
++ k++;
++ }
++ }
++
++ pmlmeext->update_channel_plan_by_ap_done = 1;
++
++#ifdef CONFIG_DEBUG_RTL871X
++#ifdef PLATFORM_LINUX
++ k = 0;
++ printk("%s: new STA channel plan {", __func__);
++ while ((k < MAX_CHANNEL_NUM) && (chplan_new[k].ChannelNum != 0))
++ {
++ printk("%02d(%c),", chplan_new[k].ChannelNum, chplan_new[k].ScanType==SCAN_PASSIVE?'p':'c');
++ k++;
++ }
++ printk("}\n");
++#endif
++#endif
++
++#if 0
++ // recover the right channel index
++ channel = chplan_sta[pmlmeext->sitesurvey_res.channel_idx].ChannelNum;
++ k = 0;
++ while ((k < MAX_CHANNEL_NUM) && (chplan_new[k].ChannelNum != 0))
++ {
++ if (chplan_new[k].ChannelNum == channel) {
++ RT_TRACE(_module_rtl871x_mlme_c_, _drv_notice_,
++ ("%s: change mlme_ext sitesurvey channel index from %d to %d\n",
++ __FUNCTION__, pmlmeext->sitesurvey_res.channel_idx, k));
++ pmlmeext->sitesurvey_res.channel_idx = k;
++ break;
++ }
++ k++;
++ }
++#endif
++ }
++
++ // If channel is used by AP, set channel scan type to active
++ channel = bssid->Configuration.DSConfig;
++ chplan_new = pmlmeext->channel_set;
++ i = 0;
++ while ((i < MAX_CHANNEL_NUM) && (chplan_new[i].ChannelNum != 0))
++ {
++ if (chplan_new[i].ChannelNum == channel)
++ {
++ if (chplan_new[i].ScanType == SCAN_PASSIVE)
++ {
++ //5G Bnad 2, 3 (DFS) doesn't change to active scan
++ if(channel >= 52 && channel <= 144)
++ break;
++
++ chplan_new[i].ScanType = SCAN_ACTIVE;
++ RT_TRACE(_module_rtl871x_mlme_c_, _drv_notice_,
++ ("%s: change channel %d scan type from passive to active\n",
++ __FUNCTION__, channel));
++ }
++ break;
++ }
++ i++;
++ }
++}
++#endif
++
++/****************************************************************************
++
++Following are the functions to report events
++
++*****************************************************************************/
++
++void report_survey_event(_adapter *padapter, union recv_frame *precv_frame)
++{
++ struct cmd_obj *pcmd_obj;
++ u8 *pevtcmd;
++ u32 cmdsz;
++ struct survey_event *psurvey_evt;
++ struct C2HEvent_Header *pc2h_evt_hdr;
++ struct mlme_ext_priv *pmlmeext;
++ struct cmd_priv *pcmdpriv;
++ //u8 *pframe = precv_frame->u.hdr.rx_data;
++ //uint len = precv_frame->u.hdr.len;
++
++ if(!padapter)
++ return;
++
++ pmlmeext = &padapter->mlmeextpriv;
++ pcmdpriv = &padapter->cmdpriv;
++
++
++ if ((pcmd_obj = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj))) == NULL)
++ {
++ return;
++ }
++
++ cmdsz = (sizeof(struct survey_event) + sizeof(struct C2HEvent_Header));
++ if ((pevtcmd = (u8*)rtw_zmalloc(cmdsz)) == NULL)
++ {
++ rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj));
++ return;
++ }
++
++ _rtw_init_listhead(&pcmd_obj->list);
++
++ pcmd_obj->cmdcode = GEN_CMD_CODE(_Set_MLME_EVT);
++ pcmd_obj->cmdsz = cmdsz;
++ pcmd_obj->parmbuf = pevtcmd;
++
++ pcmd_obj->rsp = NULL;
++ pcmd_obj->rspsz = 0;
++
++ pc2h_evt_hdr = (struct C2HEvent_Header*)(pevtcmd);
++ pc2h_evt_hdr->len = sizeof(struct survey_event);
++ pc2h_evt_hdr->ID = GEN_EVT_CODE(_Survey);
++ pc2h_evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq);
++
++ psurvey_evt = (struct survey_event*)(pevtcmd + sizeof(struct C2HEvent_Header));
++
++ if (collect_bss_info(padapter, precv_frame, (WLAN_BSSID_EX *)&psurvey_evt->bss) == _FAIL)
++ {
++ rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj));
++ rtw_mfree((u8 *)pevtcmd, cmdsz);
++ return;
++ }
++
++#ifdef CONFIG_80211D
++ process_80211d(padapter, &psurvey_evt->bss);
++#endif
++
++ rtw_enqueue_cmd(pcmdpriv, pcmd_obj);
++
++ pmlmeext->sitesurvey_res.bss_cnt++;
++
++ return;
++
++}
++
++void report_surveydone_event(_adapter *padapter)
++{
++ struct cmd_obj *pcmd_obj;
++ u8 *pevtcmd;
++ u32 cmdsz;
++ struct surveydone_event *psurveydone_evt;
++ struct C2HEvent_Header *pc2h_evt_hdr;
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
++
++ if ((pcmd_obj = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj))) == NULL)
++ {
++ return;
++ }
++
++ cmdsz = (sizeof(struct surveydone_event) + sizeof(struct C2HEvent_Header));
++ if ((pevtcmd = (u8*)rtw_zmalloc(cmdsz)) == NULL)
++ {
++ rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj));
++ return;
++ }
++
++ _rtw_init_listhead(&pcmd_obj->list);
++
++ pcmd_obj->cmdcode = GEN_CMD_CODE(_Set_MLME_EVT);
++ pcmd_obj->cmdsz = cmdsz;
++ pcmd_obj->parmbuf = pevtcmd;
++
++ pcmd_obj->rsp = NULL;
++ pcmd_obj->rspsz = 0;
++
++ pc2h_evt_hdr = (struct C2HEvent_Header*)(pevtcmd);
++ pc2h_evt_hdr->len = sizeof(struct surveydone_event);
++ pc2h_evt_hdr->ID = GEN_EVT_CODE(_SurveyDone);
++ pc2h_evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq);
++
++ psurveydone_evt = (struct surveydone_event*)(pevtcmd + sizeof(struct C2HEvent_Header));
++ psurveydone_evt->bss_cnt = pmlmeext->sitesurvey_res.bss_cnt;
++
++ DBG_871X("survey done event(%x) band:%d for "ADPT_FMT"\n", psurveydone_evt->bss_cnt, padapter->setband, ADPT_ARG(padapter));
++
++ rtw_enqueue_cmd(pcmdpriv, pcmd_obj);
++
++ return;
++
++}
++
++void report_join_res(_adapter *padapter, int res)
++{
++ struct cmd_obj *pcmd_obj;
++ u8 *pevtcmd;
++ u32 cmdsz;
++ struct joinbss_event *pjoinbss_evt;
++ struct C2HEvent_Header *pc2h_evt_hdr;
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
++
++ if ((pcmd_obj = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj))) == NULL)
++ {
++ return;
++ }
++
++ cmdsz = (sizeof(struct joinbss_event) + sizeof(struct C2HEvent_Header));
++ if ((pevtcmd = (u8*)rtw_zmalloc(cmdsz)) == NULL)
++ {
++ rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj));
++ return;
++ }
++
++ _rtw_init_listhead(&pcmd_obj->list);
++
++ pcmd_obj->cmdcode = GEN_CMD_CODE(_Set_MLME_EVT);
++ pcmd_obj->cmdsz = cmdsz;
++ pcmd_obj->parmbuf = pevtcmd;
++
++ pcmd_obj->rsp = NULL;
++ pcmd_obj->rspsz = 0;
++
++ pc2h_evt_hdr = (struct C2HEvent_Header*)(pevtcmd);
++ pc2h_evt_hdr->len = sizeof(struct joinbss_event);
++ pc2h_evt_hdr->ID = GEN_EVT_CODE(_JoinBss);
++ pc2h_evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq);
++
++ pjoinbss_evt = (struct joinbss_event*)(pevtcmd + sizeof(struct C2HEvent_Header));
++ _rtw_memcpy((unsigned char *)(&(pjoinbss_evt->network.network)), &(pmlmeinfo->network), sizeof(WLAN_BSSID_EX));
++ pjoinbss_evt->network.join_res = pjoinbss_evt->network.aid = res;
++
++ DBG_871X("report_join_res(%d)\n", res);
++
++
++ rtw_joinbss_event_prehandle(padapter, (u8 *)&pjoinbss_evt->network);
++
++
++ rtw_enqueue_cmd(pcmdpriv, pcmd_obj);
++
++ return;
++
++}
++
++void report_del_sta_event(_adapter *padapter, unsigned char* MacAddr, unsigned short reason)
++{
++ struct cmd_obj *pcmd_obj;
++ u8 *pevtcmd;
++ u32 cmdsz;
++ struct sta_info *psta;
++ int mac_id;
++ struct stadel_event *pdel_sta_evt;
++ struct C2HEvent_Header *pc2h_evt_hdr;
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
++
++ if ((pcmd_obj = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj))) == NULL)
++ {
++ return;
++ }
++
++ cmdsz = (sizeof(struct stadel_event) + sizeof(struct C2HEvent_Header));
++ if ((pevtcmd = (u8*)rtw_zmalloc(cmdsz)) == NULL)
++ {
++ rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj));
++ return;
++ }
++
++ _rtw_init_listhead(&pcmd_obj->list);
++
++ pcmd_obj->cmdcode = GEN_CMD_CODE(_Set_MLME_EVT);
++ pcmd_obj->cmdsz = cmdsz;
++ pcmd_obj->parmbuf = pevtcmd;
++
++ pcmd_obj->rsp = NULL;
++ pcmd_obj->rspsz = 0;
++
++ pc2h_evt_hdr = (struct C2HEvent_Header*)(pevtcmd);
++ pc2h_evt_hdr->len = sizeof(struct stadel_event);
++ pc2h_evt_hdr->ID = GEN_EVT_CODE(_DelSTA);
++ pc2h_evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq);
++
++ pdel_sta_evt = (struct stadel_event*)(pevtcmd + sizeof(struct C2HEvent_Header));
++ _rtw_memcpy((unsigned char *)(&(pdel_sta_evt->macaddr)), MacAddr, ETH_ALEN);
++ _rtw_memcpy((unsigned char *)(pdel_sta_evt->rsvd),(unsigned char *)(&reason),2);
++
++
++ psta = rtw_get_stainfo(&padapter->stapriv, MacAddr);
++ if(psta)
++ mac_id = (int)psta->mac_id;
++ else
++ mac_id = (-1);
++
++ pdel_sta_evt->mac_id = mac_id;
++
++ DBG_871X("report_del_sta_event: delete STA, mac_id=%d\n", mac_id);
++
++ rtw_enqueue_cmd(pcmdpriv, pcmd_obj);
++
++ return;
++}
++
++void report_add_sta_event(_adapter *padapter, unsigned char* MacAddr, int cam_idx)
++{
++ struct cmd_obj *pcmd_obj;
++ u8 *pevtcmd;
++ u32 cmdsz;
++ struct stassoc_event *padd_sta_evt;
++ struct C2HEvent_Header *pc2h_evt_hdr;
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
++
++ if ((pcmd_obj = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj))) == NULL)
++ {
++ return;
++ }
++
++ cmdsz = (sizeof(struct stassoc_event) + sizeof(struct C2HEvent_Header));
++ if ((pevtcmd = (u8*)rtw_zmalloc(cmdsz)) == NULL)
++ {
++ rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj));
++ return;
++ }
++
++ _rtw_init_listhead(&pcmd_obj->list);
++
++ pcmd_obj->cmdcode = GEN_CMD_CODE(_Set_MLME_EVT);
++ pcmd_obj->cmdsz = cmdsz;
++ pcmd_obj->parmbuf = pevtcmd;
++
++ pcmd_obj->rsp = NULL;
++ pcmd_obj->rspsz = 0;
++
++ pc2h_evt_hdr = (struct C2HEvent_Header*)(pevtcmd);
++ pc2h_evt_hdr->len = sizeof(struct stassoc_event);
++ pc2h_evt_hdr->ID = GEN_EVT_CODE(_AddSTA);
++ pc2h_evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq);
++
++ padd_sta_evt = (struct stassoc_event*)(pevtcmd + sizeof(struct C2HEvent_Header));
++ _rtw_memcpy((unsigned char *)(&(padd_sta_evt->macaddr)), MacAddr, ETH_ALEN);
++ padd_sta_evt->cam_id = cam_idx;
++
++ DBG_871X("report_add_sta_event: add STA\n");
++
++ rtw_enqueue_cmd(pcmdpriv, pcmd_obj);
++
++ return;
++}
++
++
++/****************************************************************************
++
++Following are the event callback functions
++
++*****************************************************************************/
++
++//for sta/adhoc mode
++void update_sta_info(_adapter *padapter, struct sta_info *psta)
++{
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++
++ //ERP
++ VCS_update(padapter, psta);
++
++
++ //HT
++ if(pmlmepriv->htpriv.ht_option)
++ {
++ psta->htpriv.ht_option = _TRUE;
++
++ psta->htpriv.ampdu_enable = pmlmepriv->htpriv.ampdu_enable;
++
++ if (support_short_GI(padapter, &(pmlmeinfo->HT_caps)))
++ psta->htpriv.sgi = _TRUE;
++
++ psta->qos_option = _TRUE;
++
++ }
++ else
++ {
++ psta->htpriv.ht_option = _FALSE;
++
++ psta->htpriv.ampdu_enable = _FALSE;
++
++ psta->htpriv.sgi = _FALSE;
++
++ psta->qos_option = _FALSE;
++
++ }
++
++ psta->htpriv.bwmode = pmlmeext->cur_bwmode;
++ psta->htpriv.ch_offset = pmlmeext->cur_ch_offset;
++
++ psta->htpriv.agg_enable_bitmap = 0x0;//reset
++ psta->htpriv.candidate_tid_bitmap = 0x0;//reset
++
++
++ //QoS
++ if(pmlmepriv->qospriv.qos_option)
++ psta->qos_option = _TRUE;
++
++
++ psta->state = _FW_LINKED;
++
++}
++
++void mlmeext_joinbss_event_callback(_adapter *padapter, int join_res)
++{
++ struct sta_info *psta, *psta_bmc;
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network);
++ struct sta_priv *pstapriv = &padapter->stapriv;
++ u8 join_type;
++
++ if(join_res < 0)
++ {
++ join_type = 1;
++ rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type));
++ rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, null_addr);
++
++ //restore to initial setting.
++ update_tx_basic_rate(padapter, padapter->registrypriv.wireless_mode);
++#if 0 //temply remove
++#ifdef CONFIG_INTEL_WIDI
++#ifdef DBG_CONFIG_ERROR_DETECT
++ DBG_871X("%s(): do silentreset\n",__FUNCTION__);
++ rtw_hal_sreset_reset(padapter);
++#endif
++#endif
++#endif
++ goto exit_mlmeext_joinbss_event_callback;
++ }
++
++ if((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE)
++ {
++ //for bc/mc
++ psta_bmc = rtw_get_bcmc_stainfo(padapter);
++ if(psta_bmc)
++ {
++ pmlmeinfo->FW_sta_info[psta_bmc->mac_id].psta = psta_bmc;
++ update_bmc_sta_support_rate(padapter, psta_bmc->mac_id);
++ Update_RA_Entry(padapter, psta_bmc->mac_id);
++ }
++ }
++
++
++ //turn on dynamic functions
++ Switch_DM_Func(padapter, DYNAMIC_FUNC_DIG|DYNAMIC_FUNC_HP|DYNAMIC_FUNC_SS, _TRUE);
++
++ // update IOT-releated issue
++ update_IOT_info(padapter);
++
++ rtw_hal_set_hwreg(padapter, HW_VAR_BASIC_RATE, cur_network->SupportedRates);
++
++ //BCN interval
++ rtw_hal_set_hwreg(padapter, HW_VAR_BEACON_INTERVAL, (u8 *)(&pmlmeinfo->bcn_interval));
++
++ //udpate capability
++ update_capinfo(padapter, pmlmeinfo->capability);
++
++ //WMM, Update EDCA param
++ WMMOnAssocRsp(padapter);
++
++ //HT
++ HTOnAssocRsp(padapter);
++
++#ifndef CONFIG_CONCURRENT_MODE
++ // Call set_channel_bwmode when the CONFIG_CONCURRENT_MODE doesn't be defined.
++ //Set cur_channel&cur_bwmode&cur_ch_offset
++ set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode);
++#endif
++
++ psta = rtw_get_stainfo(pstapriv, cur_network->MacAddress);
++ if (psta) //only for infra. mode
++ {
++ pmlmeinfo->FW_sta_info[psta->mac_id].psta = psta;
++
++ //DBG_871X("set_sta_rate\n");
++
++ //set per sta rate after updating HT cap.
++ set_sta_rate(padapter, psta);
++ }
++
++ join_type = 2;
++ rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type));
++
++ if((pmlmeinfo->state&0x03) == WIFI_FW_STATION_STATE)
++ {
++ // correcting TSF
++ correct_TSF(padapter, pmlmeext);
++
++ //set_link_timer(pmlmeext, DISCONNECT_TO);
++ }
++
++#ifdef CONFIG_LPS
++ rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_CONNECT, 0);
++#endif
++
++exit_mlmeext_joinbss_event_callback:
++
++#ifdef CONFIG_DUALMAC_CONCURRENT
++ dc_handle_join_done(padapter, join_res);
++#endif
++#ifdef CONFIG_CONCURRENT_MODE
++ concurrent_chk_joinbss_done(padapter, join_res);
++#endif
++
++ DBG_871X("=>%s\n", __FUNCTION__);
++
++}
++
++void mlmeext_sta_add_event_callback(_adapter *padapter, struct sta_info *psta)
++{
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ u8 join_type;
++
++ DBG_871X("%s\n", __FUNCTION__);
++
++ if((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE)
++ {
++ if(pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)//adhoc master or sta_count>1
++ {
++ //nothing to do
++ }
++ else//adhoc client
++ {
++ //update TSF Value
++ //update_TSF(pmlmeext, pframe, len);
++
++ // correcting TSF
++ correct_TSF(padapter, pmlmeext);
++
++ //start beacon
++ if(send_beacon(padapter)==_FAIL)
++ {
++ pmlmeinfo->FW_sta_info[psta->mac_id].status = 0;
++
++ pmlmeinfo->state ^= WIFI_FW_ADHOC_STATE;
++
++ return;
++ }
++
++ pmlmeinfo->state |= WIFI_FW_ASSOC_SUCCESS;
++
++ }
++
++ join_type = 2;
++ rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type));
++ }
++
++ pmlmeinfo->FW_sta_info[psta->mac_id].psta = psta;
++
++ //rate radaptive
++ Update_RA_Entry(padapter, psta->mac_id);
++
++ //update adhoc sta_info
++ update_sta_info(padapter, psta);
++
++}
++
++void mlmeext_sta_del_event_callback(_adapter *padapter)
++{
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++
++ if (is_client_associated_to_ap(padapter) || is_IBSS_empty(padapter))
++ {
++ //set_opmode_cmd(padapter, infra_client_with_mlme);
++
++ rtw_hal_set_hwreg(padapter, HW_VAR_MLME_DISCONNECT, 0);
++ rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, null_addr);
++
++ //restore to initial setting.
++ update_tx_basic_rate(padapter, padapter->registrypriv.wireless_mode);
++
++#ifdef CONFIG_DUALMAC_CONCURRENT
++ dc_set_channel_bwmode_disconnect(padapter);
++#else
++#ifdef CONFIG_CONCURRENT_MODE
++ if((check_buddy_fwstate(padapter, _FW_LINKED)) != _TRUE)
++ {
++#endif //CONFIG_CONCURRENT_MODE
++
++ //switch to the 20M Hz mode after disconnect
++ pmlmeext->cur_bwmode = HT_CHANNEL_WIDTH_20;
++ pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++
++ //SelectChannel(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset);
++ set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode);
++
++#ifdef CONFIG_CONCURRENT_MODE
++ }
++#endif //CONFIG_CONCURRENT_MODE
++#endif //CONFIG_DUALMAC_CONCURRENT
++
++ flush_all_cam_entry(padapter);
++
++ pmlmeinfo->state = WIFI_FW_NULL_STATE;
++
++ //set MSR to no link state -> infra. mode
++ Set_MSR(padapter, _HW_STATE_STATION_);
++
++ _cancel_timer_ex(&pmlmeext->link_timer);
++
++ }
++
++}
++
++/****************************************************************************
++
++Following are the functions for the timer handlers
++
++*****************************************************************************/
++void _linked_rx_signal_strehgth_display(_adapter *padapter);
++void _linked_rx_signal_strehgth_display(_adapter *padapter)
++{
++ int UndecoratedSmoothedPWDB;
++
++#ifdef CONFIG_CONCURRENT_MODE
++ PADAPTER pbuddy_adapter = padapter->pbuddy_adapter;
++ DBG_871X("============ pbuddy_adapter linked status check ===================\n");
++ DBG_871X("buddy_adapter_type=%d\n", pbuddy_adapter->adapter_type);
++ DBG_871X("pbuddy_adapter pathA Rx SNRdb:%d\n",pbuddy_adapter->recvpriv.RxSNRdB[0]);
++ DBG_871X("pbuddy_adapter pathA Rx PWDB:%d\n",pbuddy_adapter->recvpriv.rxpwdb);
++ DBG_871X("pbuddy_adapter pathA Rx RSSI:%d,pathB Rx RSSI:%d\n"
++ ,pbuddy_adapter->recvpriv.RxRssi[0],pbuddy_adapter->recvpriv.RxRssi[1]);
++ rtw_hal_get_def_var(pbuddy_adapter, HAL_DEF_UNDERCORATEDSMOOTHEDPWDB, &UndecoratedSmoothedPWDB);
++ DBG_871X("pbuddy_adapter UndecoratedSmoothedPWDB:%d\n",UndecoratedSmoothedPWDB);
++ DBG_871X("Rx RSSI:%d\n",pbuddy_adapter->recvpriv.rssi);
++ DBG_871X("Rx Signal_strength:%d\n",pbuddy_adapter->recvpriv.signal_strength);
++ DBG_871X("Rx Signal_qual:%d \n",pbuddy_adapter->recvpriv.signal_qual);
++ DBG_871X("============ linked status check ===================\n");
++ DBG_871X("adapter_type=%d\n", padapter->adapter_type);
++#else //CONFIG_CONCURRENT_MODE
++ DBG_871X("============ linked status check ===================\n");
++#endif //CONFIG_CONCURRENT_MODE
++ DBG_871X("pathA Rx SNRdb:%d, pathB Rx SNRdb:%d\n",padapter->recvpriv.RxSNRdB[0], padapter->recvpriv.RxSNRdB[1]);
++ DBG_871X("pathA Rx PWDB:%d\n",padapter->recvpriv.rxpwdb);
++ DBG_871X("pathA Rx RSSI:%d,pathB Rx RSSI:%d\n",padapter->recvpriv.RxRssi[0],padapter->recvpriv.RxRssi[1]);
++ rtw_hal_get_def_var(padapter, HAL_DEF_UNDERCORATEDSMOOTHEDPWDB, &UndecoratedSmoothedPWDB);
++ DBG_871X("UndecoratedSmoothedPWDB:%d\n",UndecoratedSmoothedPWDB);
++ DBG_871X("Rx RSSI:%d\n",padapter->recvpriv.rssi);
++ DBG_871X("Rx Signal_strength:%d\n",padapter->recvpriv.signal_strength);
++ DBG_871X("Rx Signal_qual:%d \n",padapter->recvpriv.signal_qual);
++ if ( check_fwstate( &padapter->mlmepriv, _FW_LINKED ))
++ {
++ DBG_871X("bw mode: %d, channel: %d\n", padapter->mlmeextpriv.cur_bwmode, padapter->mlmeextpriv.cur_channel );
++ DBG_871X("received bytes = %d\n", (u32) (padapter->recvpriv.rx_bytes - padapter->recvpriv.last_rx_bytes ) );
++ }
++ DBG_871X("============ linked status check ===================\n");
++ DBG_871X(" DIG PATH-A(0x%02x), PATH-B(0x%02x)\n",rtw_read8(padapter,0xc50),rtw_read8(padapter,0xc58));
++ DBG_871X(" OFDM -Alarm DA2(0x%04x),DA4(0x%04x),DA6(0x%04x),DA8(0x%04x)\n",
++ rtw_read16(padapter,0xDA2),rtw_read16(padapter,0xDA4),rtw_read16(padapter,0xDA6),rtw_read16(padapter,0xDA8));
++
++ DBG_871X(" CCK -Alarm A5B(0x%02x),A5C(0x%02x)\n",rtw_read8(padapter,0xA5B),rtw_read8(padapter,0xA5C));
++ DBG_871X(" FalseAlmCnt_all(%d)\n",padapter->recvpriv.FalseAlmCnt_all);
++
++}
++
++u8 chk_ap_is_alive(_adapter *padapter, struct sta_info *psta)
++{
++ u8 ret = _FALSE;
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++
++ #ifdef DBG_EXPIRATION_CHK
++ DBG_871X(FUNC_ADPT_FMT" rx:"STA_PKTS_FMT", beacon:%llu, probersp_to_self:%llu"
++ /*", probersp_bm:%llu, probersp_uo:%llu, probereq:%llu, BI:%u"*/
++ ", retry:%u\n"
++ , FUNC_ADPT_ARG(padapter)
++ , STA_RX_PKTS_DIFF_ARG(psta)
++ , psta->sta_stats.rx_beacon_pkts - psta->sta_stats.last_rx_beacon_pkts
++ , psta->sta_stats.rx_probersp_pkts - psta->sta_stats.last_rx_probersp_pkts
++ /*, psta->sta_stats.rx_probersp_bm_pkts - psta->sta_stats.last_rx_probersp_bm_pkts
++ , psta->sta_stats.rx_probersp_uo_pkts - psta->sta_stats.last_rx_probersp_uo_pkts
++ , psta->sta_stats.rx_probereq_pkts - psta->sta_stats.last_rx_probereq_pkts
++ , pmlmeinfo->bcn_interval*/
++ , pmlmeext->retry
++ );
++
++ DBG_871X(FUNC_ADPT_FMT" tx_pkts:%llu, link_count:%u\n", FUNC_ADPT_ARG(padapter)
++ , padapter->xmitpriv.tx_pkts
++ , pmlmeinfo->link_count
++ );
++ #endif
++
++ if((sta_rx_data_pkts(psta) == sta_last_rx_data_pkts(psta))
++ && sta_rx_beacon_pkts(psta) == sta_last_rx_beacon_pkts(psta)
++ && sta_rx_probersp_pkts(psta) == sta_last_rx_probersp_pkts(psta)
++ )
++ {
++ ret = _FALSE;
++ }
++ else
++ {
++ ret = _TRUE;
++ }
++
++ sta_update_last_rx_pkts(psta);
++
++ return ret;
++}
++
++void linked_status_chk(_adapter *padapter)
++{
++ u32 i;
++ struct sta_info *psta;
++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ struct sta_priv *pstapriv = &padapter->stapriv;
++
++ if(padapter->bRxRSSIDisplay)
++ _linked_rx_signal_strehgth_display(padapter);
++
++ #ifdef DBG_CONFIG_ERROR_DETECT
++ rtw_hal_sreset_linked_status_check(padapter);
++ #endif
++
++ if (is_client_associated_to_ap(padapter))
++ {
++ //linked infrastructure client mode
++
++ int tx_chk = _SUCCESS, rx_chk = _SUCCESS;
++ int rx_chk_limit;
++
++ #if defined(DBG_ROAMING_TEST)
++ rx_chk_limit = 1;
++ #elif defined(CONFIG_ACTIVE_KEEP_ALIVE_CHECK)
++ rx_chk_limit = 4;
++ #else
++ rx_chk_limit = 8;
++ #endif
++
++ // Marked by Kurt 20130715
++ // For WiDi 3.5 and later on, they don't ask WiDi sink to do roaming, so we could not check rx limit that strictly.
++ // todo: To check why rx_chk would be _FALSE under miracast session.
++ //#ifdef CONFIG_INTEL_WIDI
++ //if (padapter->mlmepriv.widi_state != INTEL_WIDI_STATE_NONE)
++ // rx_chk_limit = 1;
++ //#endif
++
++ if ((psta = rtw_get_stainfo(pstapriv, pmlmeinfo->network.MacAddress)) != NULL)
++ {
++ bool is_p2p_enable = _FALSE;
++ #ifdef CONFIG_P2P
++ is_p2p_enable = !rtw_p2p_chk_state(&padapter->wdinfo, P2P_STATE_NONE);
++ #endif
++
++ if (chk_ap_is_alive(padapter, psta) == _FALSE)
++ rx_chk = _FAIL;
++
++ if (pxmitpriv->last_tx_pkts == pxmitpriv->tx_pkts)
++ tx_chk = _FAIL;
++
++ #ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK
++ if (pmlmeext->active_keep_alive_check && (rx_chk == _FAIL || tx_chk == _FAIL)) {
++ u8 backup_oper_channel=0;
++
++ /* switch to correct channel of current network before issue keep-alive frames */
++ if (rtw_get_oper_ch(padapter) != pmlmeext->cur_channel) {
++ backup_oper_channel = rtw_get_oper_ch(padapter);
++ SelectChannel(padapter, pmlmeext->cur_channel);
++ }
++
++ if (rx_chk != _SUCCESS)
++ issue_probereq_ex(padapter, &pmlmeinfo->network.Ssid, psta->hwaddr, 3, 1);
++
++ if ((tx_chk != _SUCCESS && pmlmeinfo->link_count++ == 0xf) || rx_chk != _SUCCESS) {
++ tx_chk = issue_nulldata(padapter, psta->hwaddr, 0, 3, 1);
++ /* if tx acked and p2p disabled, set rx_chk _SUCCESS to reset retry count */
++ if (tx_chk == _SUCCESS && !is_p2p_enable)
++ rx_chk = _SUCCESS;
++ }
++
++ /* back to the original operation channel */
++ if(backup_oper_channel>0)
++ SelectChannel(padapter, backup_oper_channel);
++
++ }
++ else
++ #endif /* CONFIG_ACTIVE_KEEP_ALIVE_CHECK */
++ {
++ if (rx_chk != _SUCCESS) {
++ if (pmlmeext->retry == 0) {
++ #ifdef DBG_EXPIRATION_CHK
++ DBG_871X("issue_probereq to trigger probersp, retry=%d\n", pmlmeext->retry);
++ #endif
++ issue_probereq(padapter, &pmlmeinfo->network.Ssid, pmlmeinfo->network.MacAddress);
++ issue_probereq(padapter, &pmlmeinfo->network.Ssid, pmlmeinfo->network.MacAddress);
++ issue_probereq(padapter, &pmlmeinfo->network.Ssid, pmlmeinfo->network.MacAddress);
++ }
++ }
++
++ if (tx_chk != _SUCCESS && pmlmeinfo->link_count++ == 0xf) {
++ #ifdef DBG_EXPIRATION_CHK
++ DBG_871X("%s issue_nulldata 0\n", __FUNCTION__);
++ #endif
++ tx_chk = issue_nulldata(padapter, NULL, 0, 1, 0);
++ }
++ }
++
++ if (rx_chk == _FAIL) {
++ pmlmeext->retry++;
++ if (pmlmeext->retry > rx_chk_limit) {
++ DBG_871X(FUNC_ADPT_FMT" disconnect or roaming\n",
++ FUNC_ADPT_ARG(padapter));
++ receive_disconnect(padapter, pmlmeinfo->network.MacAddress
++ , WLAN_REASON_EXPIRATION_CHK);
++ return;
++ }
++ } else {
++ pmlmeext->retry = 0;
++ }
++
++ if (tx_chk == _FAIL) {
++ pmlmeinfo->link_count &= 0xf;
++ } else {
++ pxmitpriv->last_tx_pkts = pxmitpriv->tx_pkts;
++ pmlmeinfo->link_count = 0;
++ }
++
++ } //end of if ((psta = rtw_get_stainfo(pstapriv, passoc_res->network.MacAddress)) != NULL)
++ }
++ else if (is_client_associated_to_ibss(padapter))
++ {
++ //linked IBSS mode
++ //for each assoc list entry to check the rx pkt counter
++ for (i = IBSS_START_MAC_ID; i < NUM_STA; i++)
++ {
++ if (pmlmeinfo->FW_sta_info[i].status == 1)
++ {
++ psta = pmlmeinfo->FW_sta_info[i].psta;
++
++ if(NULL==psta) continue;
++
++ if (pmlmeinfo->FW_sta_info[i].rx_pkt == sta_rx_pkts(psta))
++ {
++
++ if(pmlmeinfo->FW_sta_info[i].retry<3)
++ {
++ pmlmeinfo->FW_sta_info[i].retry++;
++ }
++ else
++ {
++ pmlmeinfo->FW_sta_info[i].retry = 0;
++ pmlmeinfo->FW_sta_info[i].status = 0;
++ report_del_sta_event(padapter, psta->hwaddr
++ , 65535// indicate disconnect caused by no rx
++ );
++ }
++ }
++ else
++ {
++ pmlmeinfo->FW_sta_info[i].retry = 0;
++ pmlmeinfo->FW_sta_info[i].rx_pkt = (u32)sta_rx_pkts(psta);
++ }
++ }
++ }
++
++ //set_link_timer(pmlmeext, DISCONNECT_TO);
++
++ }
++
++}
++
++void survey_timer_hdl(_adapter *padapter)
++{
++ struct cmd_obj *ph2c;
++ struct sitesurvey_parm *psurveyPara;
++ struct cmd_priv *pcmdpriv=&padapter->cmdpriv;
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++#ifdef CONFIG_P2P
++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo);
++#endif
++
++ //DBG_871X("marc: survey timer\n");
++#ifdef PLATFORM_FREEBSD
++ rtw_mtx_lock(NULL);
++ if (callout_pending(&padapter->mlmeextpriv.survey_timer.callout)) {
++ /* callout was reset */
++ //mtx_unlock(&sc->sc_mtx);
++ rtw_mtx_unlock(NULL);
++ return;
++ }
++ if (!callout_active(&padapter->mlmeextpriv.survey_timer.callout)) {
++ /* callout was stopped */
++ //mtx_unlock(&sc->sc_mtx);
++ rtw_mtx_unlock(NULL);
++ return;
++ }
++ callout_deactivate(&padapter->mlmeextpriv.survey_timer.callout);
++
++
++#endif
++
++ //issue rtw_sitesurvey_cmd
++ if (pmlmeext->sitesurvey_res.state > SCAN_START)
++ {
++ if(pmlmeext->sitesurvey_res.state == SCAN_PROCESS)
++ {
++#ifdef CONFIG_STA_MODE_SCAN_UNDER_AP_MODE
++ if( padapter->mlmeextpriv.mlmext_info.scan_cnt != RTW_SCAN_NUM_OF_CH )
++#endif //CONFIG_STA_MODE_SCAN_UNDER_AP_MODE
++ pmlmeext->sitesurvey_res.channel_idx++;
++ }
++
++ if(pmlmeext->scan_abort == _TRUE)
++ {
++ #ifdef CONFIG_P2P
++ if(!rtw_p2p_chk_state(&padapter->wdinfo, P2P_STATE_NONE))
++ {
++ rtw_p2p_findphase_ex_set(pwdinfo, P2P_FINDPHASE_EX_MAX);
++ pmlmeext->sitesurvey_res.channel_idx = 3;
++ DBG_871X("%s idx:%d, cnt:%u\n", __FUNCTION__
++ , pmlmeext->sitesurvey_res.channel_idx
++ , pwdinfo->find_phase_state_exchange_cnt
++ );
++ }
++ else
++ #endif
++ {
++ pmlmeext->sitesurvey_res.channel_idx = pmlmeext->sitesurvey_res.ch_num;
++ DBG_871X("%s idx:%d\n", __FUNCTION__
++ , pmlmeext->sitesurvey_res.channel_idx
++ );
++ }
++
++ pmlmeext->scan_abort = _FALSE;//reset
++ }
++
++ if ((ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj))) == NULL)
++ {
++ goto exit_survey_timer_hdl;
++ }
++
++ if ((psurveyPara = (struct sitesurvey_parm*)rtw_zmalloc(sizeof(struct sitesurvey_parm))) == NULL)
++ {
++ rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));
++ goto exit_survey_timer_hdl;
++ }
++
++ init_h2fwcmd_w_parm_no_rsp(ph2c, psurveyPara, GEN_CMD_CODE(_SiteSurvey));
++ rtw_enqueue_cmd(pcmdpriv, ph2c);
++ }
++
++
++exit_survey_timer_hdl:
++#ifdef PLATFORM_FREEBSD
++ rtw_mtx_unlock(NULL);
++#endif
++
++ return;
++}
++
++void link_timer_hdl(_adapter *padapter)
++{
++ //static unsigned int rx_pkt = 0;
++ //static u64 tx_cnt = 0;
++ //struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ //struct sta_priv *pstapriv = &padapter->stapriv;
++
++#ifdef PLATFORM_FREEBSD
++ rtw_mtx_lock(NULL);
++ if (callout_pending(&padapter->mlmeextpriv.survey_timer.callout)) {
++ /* callout was reset */
++ //mtx_unlock(&sc->sc_mtx);
++ rtw_mtx_unlock(NULL);
++ return;
++ }
++ if (!callout_active(&padapter->mlmeextpriv.survey_timer.callout)) {
++ /* callout was stopped */
++ //mtx_unlock(&sc->sc_mtx);
++ rtw_mtx_unlock(NULL);
++ return;
++ }
++ callout_deactivate(&padapter->mlmeextpriv.survey_timer.callout);
++
++
++#endif
++
++ if (pmlmeinfo->state & WIFI_FW_AUTH_NULL)
++ {
++ DBG_871X("link_timer_hdl:no beacon while connecting\n");
++ pmlmeinfo->state = WIFI_FW_NULL_STATE;
++ report_join_res(padapter, -3);
++ }
++ else if (pmlmeinfo->state & WIFI_FW_AUTH_STATE)
++ {
++ //re-auth timer
++ if (++pmlmeinfo->reauth_count > REAUTH_LIMIT)
++ {
++ //if (pmlmeinfo->auth_algo != dot11AuthAlgrthm_Auto)
++ //{
++ pmlmeinfo->state = 0;
++ report_join_res(padapter, -1);
++ return;
++ //}
++ //else
++ //{
++ // pmlmeinfo->auth_algo = dot11AuthAlgrthm_Shared;
++ // pmlmeinfo->reauth_count = 0;
++ //}
++ }
++
++ DBG_871X("link_timer_hdl: auth timeout and try again\n");
++ pmlmeinfo->auth_seq = 1;
++ issue_auth(padapter, NULL, 0);
++ set_link_timer(pmlmeext, REAUTH_TO);
++ }
++ else if (pmlmeinfo->state & WIFI_FW_ASSOC_STATE)
++ {
++ //re-assoc timer
++ if (++pmlmeinfo->reassoc_count > REASSOC_LIMIT)
++ {
++ pmlmeinfo->state = WIFI_FW_NULL_STATE;
++ report_join_res(padapter, -2);
++ return;
++ }
++
++ DBG_871X("link_timer_hdl: assoc timeout and try again\n");
++ issue_assocreq(padapter);
++ set_link_timer(pmlmeext, REASSOC_TO);
++ }
++#if 0
++ else if (is_client_associated_to_ap(padapter))
++ {
++ //linked infrastructure client mode
++ if ((psta = rtw_get_stainfo(pstapriv, pmlmeinfo->network.MacAddress)) != NULL)
++ {
++ /*to monitor whether the AP is alive or not*/
++ if (rx_pkt == psta->sta_stats.rx_pkts)
++ {
++ receive_disconnect(padapter, pmlmeinfo->network.MacAddress);
++ return;
++ }
++ else
++ {
++ rx_pkt = psta->sta_stats.rx_pkts;
++ set_link_timer(pmlmeext, DISCONNECT_TO);
++ }
++
++ //update the EDCA paramter according to the Tx/RX mode
++ update_EDCA_param(padapter);
++
++ /*to send the AP a nulldata if no frame is xmitted in order to keep alive*/
++ if (pmlmeinfo->link_count++ == 0)
++ {
++ tx_cnt = pxmitpriv->tx_pkts;
++ }
++ else if ((pmlmeinfo->link_count & 0xf) == 0)
++ {
++ if (tx_cnt == pxmitpriv->tx_pkts)
++ {
++ issue_nulldata(padapter, NULL, 0, 0, 0);
++ }
++
++ tx_cnt = pxmitpriv->tx_pkts;
++ }
++ } //end of if ((psta = rtw_get_stainfo(pstapriv, passoc_res->network.MacAddress)) != NULL)
++ }
++ else if (is_client_associated_to_ibss(padapter))
++ {
++ //linked IBSS mode
++ //for each assoc list entry to check the rx pkt counter
++ for (i = IBSS_START_MAC_ID; i < NUM_STA; i++)
++ {
++ if (pmlmeinfo->FW_sta_info[i].status == 1)
++ {
++ psta = pmlmeinfo->FW_sta_info[i].psta;
++
++ if (pmlmeinfo->FW_sta_info[i].rx_pkt == psta->sta_stats.rx_pkts)
++ {
++ pmlmeinfo->FW_sta_info[i].status = 0;
++ report_del_sta_event(padapter, psta->hwaddr);
++ }
++ else
++ {
++ pmlmeinfo->FW_sta_info[i].rx_pkt = psta->sta_stats.rx_pkts;
++ }
++ }
++ }
++
++ set_link_timer(pmlmeext, DISCONNECT_TO);
++ }
++#endif
++
++#ifdef PLATFORM_FREEBSD
++ rtw_mtx_unlock(NULL);
++#endif
++
++ return;
++}
++
++void addba_timer_hdl(struct sta_info *psta)
++{
++ struct ht_priv *phtpriv;
++
++ if(!psta)
++ return;
++
++ phtpriv = &psta->htpriv;
++
++ if((phtpriv->ht_option==_TRUE) && (phtpriv->ampdu_enable==_TRUE))
++ {
++ if(phtpriv->candidate_tid_bitmap)
++ phtpriv->candidate_tid_bitmap=0x0;
++
++ }
++}
++
++#ifdef CONFIG_IEEE80211W
++void sa_query_timer_hdl(_adapter *padapter)
++{
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_priv * pmlmepriv = &padapter->mlmepriv;
++ _irqL irqL;
++ //disconnect
++ _enter_critical_bh(&pmlmepriv->lock, &irqL);
++
++ if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)
++ {
++ rtw_disassoc_cmd(padapter, 0, _TRUE);
++ rtw_indicate_disconnect(padapter);
++ rtw_free_assoc_resources(padapter, 1);
++ }
++
++ _exit_critical_bh(&pmlmepriv->lock, &irqL);
++ DBG_871X("SA query timeout disconnect\n");
++}
++#endif //CONFIG_IEEE80211W
++
++u8 NULL_hdl(_adapter *padapter, u8 *pbuf)
++{
++ return H2C_SUCCESS;
++}
++
++#ifdef CONFIG_AUTO_AP_MODE
++void rtw_start_auto_ap(_adapter *adapter)
++{
++ DBG_871X("%s\n", __FUNCTION__);
++
++ rtw_set_802_11_infrastructure_mode(adapter, Ndis802_11APMode);
++
++ rtw_setopmode_cmd(adapter, Ndis802_11APMode);
++}
++
++static int rtw_auto_ap_start_beacon(_adapter *adapter)
++{
++ int ret=0;
++ u8 *pbuf = NULL;
++ uint len;
++ u8 supportRate[16];
++ int sz = 0, rateLen;
++ u8 * ie;
++ u8 wireless_mode, oper_channel;
++ u8 ssid[3] = {0}; //hidden ssid
++ u32 ssid_len = sizeof(ssid);
++ struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
++
++
++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE)
++ return -EINVAL;
++
++
++ len = 128;
++ pbuf = rtw_zmalloc(len);
++ if(!pbuf)
++ return -ENOMEM;
++
++
++ //generate beacon
++ ie = pbuf;
++
++ //timestamp will be inserted by hardware
++ sz += 8;
++ ie += sz;
++
++ //beacon interval : 2bytes
++ *(u16*)ie = cpu_to_le16((u16)100);//BCN_INTERVAL=100;
++ sz += 2;
++ ie += 2;
++
++ //capability info
++ *(u16*)ie = 0;
++ *(u16*)ie |= cpu_to_le16(cap_ESS);
++ *(u16*)ie |= cpu_to_le16(cap_ShortPremble);
++ //*(u16*)ie |= cpu_to_le16(cap_Privacy);
++ sz += 2;
++ ie += 2;
++
++ //SSID
++ ie = rtw_set_ie(ie, _SSID_IE_, ssid_len, ssid, &sz);
++
++ //supported rates
++ wireless_mode = WIRELESS_11BG_24N;
++ rtw_set_supported_rate(supportRate, wireless_mode) ;
++ rateLen = rtw_get_rateset_len(supportRate);
++ if (rateLen > 8)
++ {
++ ie = rtw_set_ie(ie, _SUPPORTEDRATES_IE_, 8, supportRate, &sz);
++ }
++ else
++ {
++ ie = rtw_set_ie(ie, _SUPPORTEDRATES_IE_, rateLen, supportRate, &sz);
++ }
++
++
++ //DS parameter set
++ if(check_buddy_fwstate(adapter, _FW_LINKED) &&
++ check_buddy_fwstate(adapter, WIFI_STATION_STATE))
++ {
++ PADAPTER pbuddy_adapter = adapter->pbuddy_adapter;
++ struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv;
++
++ oper_channel = pbuddy_mlmeext->cur_channel;
++ }
++ else
++ {
++ oper_channel = adapter_to_dvobj(adapter)->oper_channel;
++ }
++ ie = rtw_set_ie(ie, _DSSET_IE_, 1, &oper_channel, &sz);
++
++ //ext supported rates
++ if (rateLen > 8)
++ {
++ ie = rtw_set_ie(ie, _EXT_SUPPORTEDRATES_IE_, (rateLen - 8), (supportRate + 8), &sz);
++ }
++
++ DBG_871X("%s, start auto ap beacon sz=%d\n", __FUNCTION__, sz);
++
++ //lunch ap mode & start to issue beacon
++ if(rtw_check_beacon_data(adapter, pbuf, sz) == _SUCCESS)
++ {
++
++ }
++ else
++ {
++ ret = -EINVAL;
++ }
++
++
++ rtw_mfree(pbuf, len);
++
++ return ret;
++
++}
++#endif//CONFIG_AUTO_AP_MODE
++
++u8 setopmode_hdl(_adapter *padapter, u8 *pbuf)
++{
++ u8 type;
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ struct setopmode_parm *psetop = (struct setopmode_parm *)pbuf;
++
++ if(psetop->mode == Ndis802_11APMode)
++ {
++ pmlmeinfo->state = WIFI_FW_AP_STATE;
++ type = _HW_STATE_AP_;
++#ifdef CONFIG_NATIVEAP_MLME
++ //start_ap_mode(padapter);
++#endif
++ }
++ else if(psetop->mode == Ndis802_11Infrastructure)
++ {
++ pmlmeinfo->state &= ~(BIT(0)|BIT(1));// clear state
++ pmlmeinfo->state |= WIFI_FW_STATION_STATE;//set to STATION_STATE
++ type = _HW_STATE_STATION_;
++ }
++ else if(psetop->mode == Ndis802_11IBSS)
++ {
++ type = _HW_STATE_ADHOC_;
++ }
++ else
++ {
++ type = _HW_STATE_NOLINK_;
++ }
++
++ rtw_hal_set_hwreg(padapter, HW_VAR_SET_OPMODE, (u8 *)(&type));
++ //Set_NETYPE0_MSR(padapter, type);
++
++#ifdef CONFIG_AUTO_AP_MODE
++ if(psetop->mode == Ndis802_11APMode)
++ rtw_auto_ap_start_beacon(padapter);
++#endif
++
++ return H2C_SUCCESS;
++
++}
++
++u8 createbss_hdl(_adapter *padapter, u8 *pbuf)
++{
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX*)(&(pmlmeinfo->network));
++ struct joinbss_parm *pparm = (struct joinbss_parm *)pbuf;
++ u32 initialgain;
++
++
++ if(pparm->network.InfrastructureMode == Ndis802_11APMode)
++ {
++#ifdef CONFIG_AP_MODE
++
++ if(pmlmeinfo->state == WIFI_FW_AP_STATE)
++ {
++ //todo:
++ return H2C_SUCCESS;
++ }
++#endif
++ }
++
++ //below is for ad-hoc master
++ if(pparm->network.InfrastructureMode == Ndis802_11IBSS)
++ {
++ rtw_joinbss_reset(padapter);
++
++ pmlmeext->cur_bwmode = HT_CHANNEL_WIDTH_20;
++ pmlmeext->cur_ch_offset= HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++ pmlmeinfo->ERP_enable = 0;
++ pmlmeinfo->WMM_enable = 0;
++ pmlmeinfo->HT_enable = 0;
++ pmlmeinfo->HT_caps_enable = 0;
++ pmlmeinfo->HT_info_enable = 0;
++ pmlmeinfo->agg_enable_bitmap = 0;
++ pmlmeinfo->candidate_tid_bitmap = 0;
++
++ //disable dynamic functions, such as high power, DIG
++ Save_DM_Func_Flag(padapter);
++ Switch_DM_Func(padapter, DYNAMIC_FUNC_DISABLE, _FALSE);
++
++ //config the initial gain under linking, need to write the BB registers
++ initialgain = 0x1E;
++ rtw_hal_set_hwreg(padapter, HW_VAR_INITIAL_GAIN, (u8 *)(&initialgain));
++
++ //cancel link timer
++ _cancel_timer_ex(&pmlmeext->link_timer);
++
++ //clear CAM
++ flush_all_cam_entry(padapter);
++
++ _rtw_memcpy(pnetwork, pbuf, FIELD_OFFSET(WLAN_BSSID_EX, IELength));
++ pnetwork->IELength = ((WLAN_BSSID_EX *)pbuf)->IELength;
++
++ if(pnetwork->IELength>MAX_IE_SZ)//Check pbuf->IELength
++ return H2C_PARAMETERS_ERROR;
++
++ _rtw_memcpy(pnetwork->IEs, ((WLAN_BSSID_EX *)pbuf)->IEs, pnetwork->IELength);
++
++ start_create_ibss(padapter);
++
++ }
++
++ return H2C_SUCCESS;
++
++}
++
++u8 join_cmd_hdl(_adapter *padapter, u8 *pbuf)
++{
++ u8 join_type;
++ PNDIS_802_11_VARIABLE_IEs pIE;
++ struct registry_priv *pregpriv = &padapter->registrypriv;
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX*)(&(pmlmeinfo->network));
++#ifdef CONFIG_ANTENNA_DIVERSITY
++ struct joinbss_parm *pparm = (struct joinbss_parm *)pbuf;
++#endif //CONFIG_ANTENNA_DIVERSITY
++ u32 initialgain, i;
++ u8 cbw40_enable=0;
++ //u32 acparm;
++
++ //check already connecting to AP or not
++ if (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)
++ {
++ if (pmlmeinfo->state & WIFI_FW_STATION_STATE)
++ {
++ issue_deauth_ex(padapter, pnetwork->MacAddress, WLAN_REASON_DEAUTH_LEAVING, 5, 100);
++ }
++
++ pmlmeinfo->state = WIFI_FW_NULL_STATE;
++
++ //clear CAM
++ flush_all_cam_entry(padapter);
++
++ _cancel_timer_ex(&pmlmeext->link_timer);
++
++ //set MSR to nolink -> infra. mode
++ //Set_MSR(padapter, _HW_STATE_NOLINK_);
++ Set_MSR(padapter, _HW_STATE_STATION_);
++
++
++ rtw_hal_set_hwreg(padapter, HW_VAR_MLME_DISCONNECT, 0);
++ }
++
++#ifdef CONFIG_ANTENNA_DIVERSITY
++ rtw_antenna_select_cmd(padapter, pparm->network.PhyInfo.Optimum_antenna, _FALSE);
++#endif
++
++ rtw_joinbss_reset(padapter);
++
++ pmlmeext->cur_bwmode = HT_CHANNEL_WIDTH_20;
++ pmlmeext->cur_ch_offset= HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++ pmlmeinfo->ERP_enable = 0;
++ pmlmeinfo->WMM_enable = 0;
++ pmlmeinfo->HT_enable = 0;
++ pmlmeinfo->HT_caps_enable = 0;
++ pmlmeinfo->HT_info_enable = 0;
++ pmlmeinfo->agg_enable_bitmap = 0;
++ pmlmeinfo->candidate_tid_bitmap = 0;
++ pmlmeinfo->bwmode_updated = _FALSE;
++ //pmlmeinfo->assoc_AP_vendor = maxAP;
++
++ _rtw_memcpy(pnetwork, pbuf, FIELD_OFFSET(WLAN_BSSID_EX, IELength));
++ pnetwork->IELength = ((WLAN_BSSID_EX *)pbuf)->IELength;
++
++ if(pnetwork->IELength>MAX_IE_SZ)//Check pbuf->IELength
++ return H2C_PARAMETERS_ERROR;
++
++ _rtw_memcpy(pnetwork->IEs, ((WLAN_BSSID_EX *)pbuf)->IEs, pnetwork->IELength);
++
++ pmlmeext->cur_channel = (u8)pnetwork->Configuration.DSConfig;
++ pmlmeinfo->bcn_interval = get_beacon_interval(pnetwork);
++
++ //Check AP vendor to move rtw_joinbss_cmd()
++ //pmlmeinfo->assoc_AP_vendor = check_assoc_AP(pnetwork->IEs, pnetwork->IELength);
++
++ for (i = sizeof(NDIS_802_11_FIXED_IEs); i < pnetwork->IELength;)
++ {
++ pIE = (PNDIS_802_11_VARIABLE_IEs)(pnetwork->IEs + i);
++
++ switch (pIE->ElementID)
++ {
++ case _VENDOR_SPECIFIC_IE_://Get WMM IE.
++ if ( _rtw_memcmp(pIE->data, WMM_OUI, 4) )
++ {
++ pmlmeinfo->WMM_enable = 1;
++ }
++ break;
++
++ case _HT_CAPABILITY_IE_: //Get HT Cap IE.
++ pmlmeinfo->HT_caps_enable = 1;
++ break;
++
++ case _HT_EXTRA_INFO_IE_: //Get HT Info IE.
++ pmlmeinfo->HT_info_enable = 1;
++
++ //spec case only for cisco's ap because cisco's ap issue assoc rsp using mcs rate @40MHz or @20MHz
++//#if !defined(CONFIG_CONCURRENT_MODE) && !defined(CONFIG_DUALMAC_CONCURRENT)
++// if(pmlmeinfo->assoc_AP_vendor == ciscoAP)
++//#endif
++ {
++ struct HT_info_element *pht_info = (struct HT_info_element *)(pIE->data);
++
++ if( pnetwork->Configuration.DSConfig > 14 )
++ {
++ if( pregpriv->cbw40_enable & BIT(1) )
++ cbw40_enable = 1;
++ }
++ else
++ if( pregpriv->cbw40_enable & BIT(0) )
++ cbw40_enable = 1;
++
++ if ((cbw40_enable) && (pht_info->infos[0] & BIT(2)))
++ {
++ //switch to the 40M Hz mode according to the AP
++ pmlmeext->cur_bwmode = HT_CHANNEL_WIDTH_40;
++ switch (pht_info->infos[0] & 0x3)
++ {
++ case 1:
++ pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_LOWER;
++ break;
++
++ case 3:
++ pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_UPPER;
++ break;
++
++ default:
++ pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++ break;
++ }
++
++ DBG_871X("set ch/bw before connected\n");
++ }
++ }
++ break;
++
++ default:
++ break;
++ }
++
++ i += (pIE->Length + 2);
++ }
++#if 0
++ if (padapter->registrypriv.wifi_spec) {
++ // for WiFi test, follow WMM test plan spec
++ acparm = 0x002F431C; // VO
++ rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VO, (u8 *)(&acparm));
++ acparm = 0x005E541C; // VI
++ rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VI, (u8 *)(&acparm));
++ acparm = 0x0000A525; // BE
++ rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acparm));
++ acparm = 0x0000A549; // BK
++ rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BK, (u8 *)(&acparm));
++
++ // for WiFi test, mixed mode with intel STA under bg mode throughput issue
++ if (padapter->mlmepriv.htpriv.ht_option == _FALSE){
++ acparm = 0x00004320;
++ rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acparm));
++ }
++ }
++ else {
++ acparm = 0x002F3217; // VO
++ rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VO, (u8 *)(&acparm));
++ acparm = 0x005E4317; // VI
++ rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VI, (u8 *)(&acparm));
++ acparm = 0x00105320; // BE
++ rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acparm));
++ acparm = 0x0000A444; // BK
++ rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BK, (u8 *)(&acparm));
++ }
++#endif
++
++ /* check channel, bandwidth, offset and switch */
++#ifdef CONFIG_DUALMAC_CONCURRENT
++ if(dc_handle_join_request(padapter) == _FAIL) {
++ DBG_871X("dc_handle_join_request fail !!!\n");
++ return H2C_SUCCESS;
++ }
++ set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode);
++#else //NON CONFIG_DUALMAC_CONCURRENT
++ if(rtw_chk_start_clnt_join(padapter) == _FAIL) {
++ report_join_res(padapter, (-4));
++ return H2C_SUCCESS;
++ }
++#endif
++
++ //disable dynamic functions, such as high power, DIG
++ //Switch_DM_Func(padapter, DYNAMIC_FUNC_DISABLE, _FALSE);
++
++ //config the initial gain under linking, need to write the BB registers
++
++ initialgain = 0x1E;
++ rtw_hal_set_hwreg(padapter, HW_VAR_INITIAL_GAIN, (u8 *)(&initialgain));
++
++
++ rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, pmlmeinfo->network.MacAddress);
++ join_type = 0;
++ rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type));
++
++ //cancel link timer
++ _cancel_timer_ex(&pmlmeext->link_timer);
++
++ start_clnt_join(padapter);
++
++ return H2C_SUCCESS;
++
++}
++
++u8 disconnect_hdl(_adapter *padapter, unsigned char *pbuf)
++{
++ struct disconnect_parm *param = (struct disconnect_parm *)pbuf;
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX*)(&(pmlmeinfo->network));
++ u8 val8;
++
++ if (is_client_associated_to_ap(padapter))
++ {
++ issue_deauth_ex(padapter, pnetwork->MacAddress, WLAN_REASON_DEAUTH_LEAVING, param->deauth_timeout_ms/100, 100);
++ }
++
++ //set_opmode_cmd(padapter, infra_client_with_mlme);
++
++ //pmlmeinfo->state = WIFI_FW_NULL_STATE;
++
++
++ rtw_hal_set_hwreg(padapter, HW_VAR_MLME_DISCONNECT, 0);
++ rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, null_addr);
++
++ //restore to initial setting.
++ update_tx_basic_rate(padapter, padapter->registrypriv.wireless_mode);
++
++ if(((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE))
++ {
++ //Stop BCN
++ val8 = 0;
++ rtw_hal_set_hwreg(padapter, HW_VAR_BCN_FUNC, (u8 *)(&val8));
++ }
++
++
++ //set MSR to no link state -> infra. mode
++ Set_MSR(padapter, _HW_STATE_STATION_);
++
++ pmlmeinfo->state = WIFI_FW_NULL_STATE;
++
++#ifdef CONFIG_DUALMAC_CONCURRENT
++ dc_set_channel_bwmode_disconnect(padapter);
++#else
++#ifdef CONFIG_CONCURRENT_MODE
++ if((check_buddy_fwstate(padapter, _FW_LINKED)) != _TRUE)
++ {
++#endif //CONFIG_CONCURRENT_MODE
++ //switch to the 20M Hz mode after disconnect
++ pmlmeext->cur_bwmode = HT_CHANNEL_WIDTH_20;
++ pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++
++ set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode);
++#ifdef CONFIG_CONCURRENT_MODE
++ }
++#endif //CONFIG_CONCURRENT_MODE
++#endif //CONFIG_DUALMAC_CONCURRENT
++
++ flush_all_cam_entry(padapter);
++
++ _cancel_timer_ex(&pmlmeext->link_timer);
++
++ rtw_free_uc_swdec_pending_queue(padapter);
++
++ return H2C_SUCCESS;
++}
++
++int rtw_scan_ch_decision(_adapter *padapter, struct rtw_ieee80211_channel *out,
++ u32 out_num, struct rtw_ieee80211_channel *in, u32 in_num)
++{
++ int i, j;
++ int scan_ch_num = 0;
++ int set_idx;
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++
++ /* clear first */
++ _rtw_memset(out, 0, sizeof(struct rtw_ieee80211_channel)*out_num);
++
++ /* acquire channels from in */
++ j = 0;
++ for (i=0;i<in_num;i++) {
++
++ if (0)
++ DBG_871X(FUNC_ADPT_FMT" "CHAN_FMT"\n", FUNC_ADPT_ARG(padapter), CHAN_ARG(&in[i]));
++
++ if(in[i].hw_value && !(in[i].flags & RTW_IEEE80211_CHAN_DISABLED)
++ && (set_idx=rtw_ch_set_search_ch(pmlmeext->channel_set, in[i].hw_value)) >=0
++ && rtw_mlme_band_check(padapter, in[i].hw_value) == _TRUE
++ )
++ {
++ if (j >= out_num) {
++ DBG_871X_LEVEL(_drv_always_, FUNC_ADPT_FMT" out_num:%u not enough\n",
++ FUNC_ADPT_ARG(padapter), out_num);
++ break;
++ }
++
++ _rtw_memcpy(&out[j], &in[i], sizeof(struct rtw_ieee80211_channel));
++
++ if(pmlmeext->channel_set[set_idx].ScanType == SCAN_PASSIVE)
++ out[j].flags &= RTW_IEEE80211_CHAN_PASSIVE_SCAN;
++
++ j++;
++ }
++ if(j>=out_num)
++ break;
++ }
++
++ /* if out is empty, use channel_set as default */
++ if(j == 0) {
++ for (i=0;i<pmlmeext->max_chan_nums;i++) {
++
++ if (0)
++ DBG_871X(FUNC_ADPT_FMT" ch:%u\n", FUNC_ADPT_ARG(padapter), pmlmeext->channel_set[i].ChannelNum);
++
++ if (rtw_mlme_band_check(padapter, pmlmeext->channel_set[i].ChannelNum) == _TRUE) {
++
++ if (j >= out_num) {
++ DBG_871X_LEVEL(_drv_always_, FUNC_ADPT_FMT" out_num:%u not enough\n",
++ FUNC_ADPT_ARG(padapter), out_num);
++ break;
++ }
++
++ out[j].hw_value = pmlmeext->channel_set[i].ChannelNum;
++
++ if(pmlmeext->channel_set[i].ScanType == SCAN_PASSIVE)
++ out[j].flags &= RTW_IEEE80211_CHAN_PASSIVE_SCAN;
++
++ j++;
++ }
++ }
++ }
++
++ return j;
++}
++
++u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf)
++{
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct sitesurvey_parm *pparm = (struct sitesurvey_parm *)pbuf;
++ u8 bdelayscan = _FALSE;
++ u8 val8;
++ u32 initialgain;
++ u32 i;
++ u8 write_initial_gain = 1;
++
++#ifdef CONFIG_P2P
++ struct wifidirect_info* pwdinfo = &padapter->wdinfo;
++#endif
++
++ if (pmlmeext->sitesurvey_res.state == SCAN_DISABLE)
++ {
++#ifdef CONFIG_CONCURRENT_MODE
++ //for first time sitesurvey_cmd
++ rtw_hal_set_hwreg(padapter, HW_VAR_CHECK_TXBUF, 0);
++#endif //CONFIG_CONCURRENT_MODE
++
++ pmlmeext->sitesurvey_res.state = SCAN_START;
++ pmlmeext->sitesurvey_res.bss_cnt = 0;
++ pmlmeext->sitesurvey_res.channel_idx = 0;
++
++ for(i=0;i<RTW_SSID_SCAN_AMOUNT;i++){
++ if(pparm->ssid[i].SsidLength) {
++ _rtw_memcpy(pmlmeext->sitesurvey_res.ssid[i].Ssid, pparm->ssid[i].Ssid, IW_ESSID_MAX_SIZE);
++ pmlmeext->sitesurvey_res.ssid[i].SsidLength= pparm->ssid[i].SsidLength;
++ } else {
++ pmlmeext->sitesurvey_res.ssid[i].SsidLength= 0;
++ }
++ }
++
++ pmlmeext->sitesurvey_res.ch_num = rtw_scan_ch_decision(padapter
++ , pmlmeext->sitesurvey_res.ch, RTW_CHANNEL_SCAN_AMOUNT
++ , pparm->ch, pparm->ch_num
++ );
++
++ pmlmeext->sitesurvey_res.scan_mode = pparm->scan_mode;
++
++#ifdef CONFIG_DUALMAC_CONCURRENT
++ bdelayscan = dc_handle_site_survey(padapter);
++#endif
++
++ //issue null data if associating to the AP
++ if (is_client_associated_to_ap(padapter) == _TRUE)
++ {
++ pmlmeext->sitesurvey_res.state = SCAN_TXNULL;
++
++ issue_nulldata(padapter, NULL, 1, 3, 500);
++
++#ifdef CONFIG_CONCURRENT_MODE
++ if(is_client_associated_to_ap(padapter->pbuddy_adapter) == _TRUE)
++ {
++ DBG_871X("adapter is scanning(buddy_adapter is linked), issue nulldata(pwrbit=1)\n");
++
++ issue_nulldata(padapter->pbuddy_adapter, NULL, 1, 3, 500);
++ }
++#endif
++ bdelayscan = _TRUE;
++ }
++#ifdef CONFIG_CONCURRENT_MODE
++ else if(is_client_associated_to_ap(padapter->pbuddy_adapter) == _TRUE)
++ {
++ #ifdef CONFIG_TDLS
++ if(padapter->pbuddy_adapter->wdinfo.wfd_tdls_enable == 1)
++ {
++ issue_tunneled_probe_req(padapter->pbuddy_adapter);
++ }
++ #endif //CONFIG_TDLS
++
++ pmlmeext->sitesurvey_res.state = SCAN_TXNULL;
++
++ issue_nulldata(padapter->pbuddy_adapter, NULL, 1, 3, 500);
++
++ bdelayscan = _TRUE;
++ }
++#endif
++ if(bdelayscan)
++ {
++ //delay 50ms to protect nulldata(1).
++ set_survey_timer(pmlmeext, 50);
++ return H2C_SUCCESS;
++ }
++ }
++
++ if ((pmlmeext->sitesurvey_res.state == SCAN_START) || (pmlmeext->sitesurvey_res.state == SCAN_TXNULL))
++ {
++#ifdef CONFIG_FIND_BEST_CHANNEL
++#if 0
++ for (i=0; pmlmeext->channel_set[i].ChannelNum !=0; i++) {
++ pmlmeext->channel_set[i].rx_count = 0;
++ }
++#endif
++#endif /* CONFIG_FIND_BEST_CHANNEL */
++
++ //disable dynamic functions, such as high power, DIG
++ Save_DM_Func_Flag(padapter);
++ Switch_DM_Func(padapter, DYNAMIC_FUNC_DISABLE, _FALSE);
++
++ //config the initial gain under scaning, need to write the BB registers
++
++#ifdef CONFIG_P2P
++#ifdef CONFIG_IOCTL_CFG80211
++ if((wdev_to_priv(padapter->rtw_wdev))->p2p_enabled == _TRUE && pwdinfo->driver_interface == DRIVER_CFG80211 )
++ {
++ write_initial_gain = 0;
++ }
++ else
++#endif //CONFIG_IOCTL_CFG80211
++ if ( !rtw_p2p_chk_state( pwdinfo, P2P_STATE_NONE ) )
++ initialgain = 0x28;
++ else
++#endif //CONFIG_P2P
++ initialgain = 0x17;
++
++ if(write_initial_gain == 1)
++ rtw_hal_set_hwreg(padapter, HW_VAR_INITIAL_GAIN, (u8 *)(&initialgain));
++
++ //set MSR to no link state
++ Set_MSR(padapter, _HW_STATE_NOLINK_);
++
++ val8 = 1; //under site survey
++ rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));
++
++ pmlmeext->sitesurvey_res.state = SCAN_PROCESS;
++ }
++
++ site_survey(padapter);
++
++ return H2C_SUCCESS;
++
++}
++
++u8 setauth_hdl(_adapter *padapter, unsigned char *pbuf)
++{
++ struct setauth_parm *pparm = (struct setauth_parm *)pbuf;
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++
++ if (pparm->mode < 4)
++ {
++ pmlmeinfo->auth_algo = pparm->mode;
++ }
++
++ return H2C_SUCCESS;
++}
++
++u8 setkey_hdl(_adapter *padapter, u8 *pbuf)
++{
++ unsigned short ctrl;
++ struct setkey_parm *pparm = (struct setkey_parm *)pbuf;
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ unsigned char null_sta[] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
++
++ //main tx key for wep.
++ if(pparm->set_tx)
++ pmlmeinfo->key_index = pparm->keyid;
++
++ //write cam
++ ctrl = BIT(15) | ((pparm->algorithm) << 2) | pparm->keyid;
++
++ write_cam(padapter, pparm->keyid, ctrl, null_sta, pparm->key);
++
++ //allow multicast packets to driver
++ rtw_hal_set_hwreg(padapter, HW_VAR_ON_RCR_AM, null_addr);
++
++ return H2C_SUCCESS;
++}
++
++u8 set_stakey_hdl(_adapter *padapter, u8 *pbuf)
++{
++ u16 ctrl=0;
++ u8 cam_id;//cam_entry
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ struct set_stakey_parm *pparm = (struct set_stakey_parm *)pbuf;
++#ifdef CONFIG_TDLS
++ struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
++ struct sta_priv *pstapriv = &padapter->stapriv;
++ struct sta_info *psta;
++#endif //CONFIG_TDLS
++
++ //cam_entry:
++ //0~3 for default key
++
++ //for concurrent mode (ap+sta):
++ //default key is disable, using sw encrypt/decrypt
++ //cam_entry = 4 //for sta mode (macid=0)
++ //cam_entry(macid+3) = 5 ~ N//for ap mode (aid=1~N, macid=2 ~N)
++
++ //for concurrent mode (sta+sta):
++ //default key is disable, using sw encrypt/decrypt
++ //cam_entry = 4 //mapping to macid=0
++ //cam_entry = 5 //mapping to macid=2
++
++#ifdef CONFIG_CONCURRENT_MODE
++ if((pmlmeinfo->state&0x03) == WIFI_FW_STATION_STATE)
++ {
++ struct sta_priv *pstapriv = &padapter->stapriv;
++ struct sta_info *psta;
++
++ psta = rtw_get_stainfo(pstapriv, pmlmeinfo->network.MacAddress);
++
++ if(psta && psta->mac_id==2)
++ {
++ cam_id = 5;
++ }
++ else
++ {
++ cam_id = 4;
++ }
++/*
++ if(padapter->iface_type > PRIMARY_IFACE)
++ {
++ cam_id = 5;
++ }
++ else
++ {
++ cam_id = 4;
++ }
++*/
++ }
++#else
++ cam_id = 4;
++#endif
++
++
++ if((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE)
++ {
++
++ struct sta_info *psta;
++ struct sta_priv *pstapriv = &padapter->stapriv;
++
++ if(pparm->algorithm == _NO_PRIVACY_) // clear cam entry
++ {
++ clear_cam_entry(padapter, pparm->id);
++ return H2C_SUCCESS_RSP;
++ }
++
++ psta = rtw_get_stainfo(pstapriv, pparm->addr);
++ if(psta)
++ {
++ ctrl = (BIT(15) | ((pparm->algorithm) << 2));
++
++ DBG_871X("r871x_set_stakey_hdl(): enc_algorithm=%d\n", pparm->algorithm);
++
++ if((psta->mac_id<1) || (psta->mac_id>(NUM_STA-4)))
++ {
++ DBG_871X("r871x_set_stakey_hdl():set_stakey failed, mac_id(aid)=%d\n", psta->mac_id);
++ return H2C_REJECTED;
++ }
++
++ cam_id = (psta->mac_id + 3);//0~3 for default key, cmd_id=macid + 3, macid=aid+1;
++
++ DBG_871X("Write CAM, mac_addr=%x:%x:%x:%x:%x:%x, cam_entry=%d\n", pparm->addr[0],
++ pparm->addr[1], pparm->addr[2], pparm->addr[3], pparm->addr[4],
++ pparm->addr[5], cam_id);
++
++ write_cam(padapter, cam_id, ctrl, pparm->addr, pparm->key);
++
++ return H2C_SUCCESS_RSP;
++
++ }
++ else
++ {
++ DBG_871X("r871x_set_stakey_hdl(): sta has been free\n");
++ return H2C_REJECTED;
++ }
++
++ }
++
++ //below for sta mode
++
++ if(pparm->algorithm == _NO_PRIVACY_) // clear cam entry
++ {
++ clear_cam_entry(padapter, pparm->id);
++ return H2C_SUCCESS;
++ }
++
++ ctrl = BIT(15) | ((pparm->algorithm) << 2);
++
++#ifdef CONFIG_TDLS
++ if(ptdlsinfo->clear_cam!=0){
++ clear_cam_entry(padapter, ptdlsinfo->clear_cam);
++ ptdlsinfo->clear_cam=0;
++
++ return H2C_SUCCESS;
++ }
++
++ psta = rtw_get_stainfo(pstapriv, pparm->addr);//Get TDLS Peer STA
++ if( psta->tdls_sta_state&TDLS_LINKED_STATE ){
++ write_cam(padapter, psta->mac_id, ctrl, pparm->addr, pparm->key);
++ }
++ else
++#endif //CONFIG_TDLS
++ write_cam(padapter, cam_id, ctrl, pparm->addr, pparm->key);
++
++ pmlmeinfo->enc_algo = pparm->algorithm;
++
++ return H2C_SUCCESS;
++}
++
++u8 add_ba_hdl(_adapter *padapter, unsigned char *pbuf)
++{
++ struct addBaReq_parm *pparm = (struct addBaReq_parm *)pbuf;
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++
++ struct sta_info *psta = rtw_get_stainfo(&padapter->stapriv, pparm->addr);
++
++ if(!psta)
++ return H2C_SUCCESS;
++
++
++ if (((pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) && (pmlmeinfo->HT_enable)) ||
++ ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE))
++ {
++ //pmlmeinfo->ADDBA_retry_count = 0;
++ //pmlmeinfo->candidate_tid_bitmap |= (0x1 << pparm->tid);
++ //psta->htpriv.candidate_tid_bitmap |= BIT(pparm->tid);
++ issue_action_BA(padapter, pparm->addr, RTW_WLAN_ACTION_ADDBA_REQ, (u16)pparm->tid);
++ //_set_timer(&pmlmeext->ADDBA_timer, ADDBA_TO);
++ _set_timer(&psta->addba_retry_timer, ADDBA_TO);
++ }
++#ifdef CONFIG_TDLS
++ else if((psta->tdls_sta_state & TDLS_LINKED_STATE)&&
++ (psta->htpriv.ht_option==_TRUE) &&
++ (psta->htpriv.ampdu_enable==_TRUE) )
++ {
++ issue_action_BA(padapter, pparm->addr, RTW_WLAN_ACTION_ADDBA_REQ, (u16)pparm->tid);
++ //_set_timer(&pmlmeext->ADDBA_timer, ADDBA_TO);
++ _set_timer(&psta->addba_retry_timer, ADDBA_TO);
++ }
++#endif //CONFIG
++ else
++ {
++ psta->htpriv.candidate_tid_bitmap &= ~BIT(pparm->tid);
++ }
++
++ return H2C_SUCCESS;
++}
++
++u8 set_tx_beacon_cmd(_adapter* padapter)
++{
++ struct cmd_obj *ph2c;
++ struct Tx_Beacon_param *ptxBeacon_parm;
++ struct cmd_priv *pcmdpriv = &(padapter->cmdpriv);
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ u8 res = _SUCCESS;
++ int len_diff = 0;
++
++_func_enter_;
++
++ if ((ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj))) == NULL)
++ {
++ res= _FAIL;
++ goto exit;
++ }
++
++ if ((ptxBeacon_parm = (struct Tx_Beacon_param *)rtw_zmalloc(sizeof(struct Tx_Beacon_param))) == NULL)
++ {
++ rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));
++ res= _FAIL;
++ goto exit;
++ }
++
++ _rtw_memcpy(&(ptxBeacon_parm->network), &(pmlmeinfo->network), sizeof(WLAN_BSSID_EX));
++
++ len_diff = update_hidden_ssid(
++ ptxBeacon_parm->network.IEs+_BEACON_IE_OFFSET_
++ , ptxBeacon_parm->network.IELength-_BEACON_IE_OFFSET_
++ , pmlmeinfo->hidden_ssid_mode
++ );
++ ptxBeacon_parm->network.IELength += len_diff;
++
++ init_h2fwcmd_w_parm_no_rsp(ph2c, ptxBeacon_parm, GEN_CMD_CODE(_TX_Beacon));
++
++ res = rtw_enqueue_cmd(pcmdpriv, ph2c);
++
++
++exit:
++
++_func_exit_;
++
++ return res;
++}
++
++
++u8 mlme_evt_hdl(_adapter *padapter, unsigned char *pbuf)
++{
++ u8 evt_code, evt_seq;
++ u16 evt_sz;
++ uint *peventbuf;
++ void (*event_callback)(_adapter *dev, u8 *pbuf);
++ struct evt_priv *pevt_priv = &(padapter->evtpriv);
++
++ peventbuf = (uint*)pbuf;
++ evt_sz = (u16)(*peventbuf&0xffff);
++ evt_seq = (u8)((*peventbuf>>24)&0x7f);
++ evt_code = (u8)((*peventbuf>>16)&0xff);
++
++
++ #ifdef CHECK_EVENT_SEQ
++ // checking event sequence...
++ if (evt_seq != (ATOMIC_READ(&pevt_priv->event_seq) & 0x7f) )
++ {
++ RT_TRACE(_module_rtl871x_cmd_c_,_drv_info_,("Evetn Seq Error! %d vs %d\n", (evt_seq & 0x7f), (ATOMIC_READ(&pevt_priv->event_seq) & 0x7f)));
++
++ pevt_priv->event_seq = (evt_seq+1)&0x7f;
++
++ goto _abort_event_;
++ }
++ #endif
++
++ // checking if event code is valid
++ if (evt_code >= MAX_C2HEVT)
++ {
++ RT_TRACE(_module_rtl871x_cmd_c_,_drv_err_,("\nEvent Code(%d) mismatch!\n", evt_code));
++ goto _abort_event_;
++ }
++
++ // checking if event size match the event parm size
++ if ((wlanevents[evt_code].parmsize != 0) &&
++ (wlanevents[evt_code].parmsize != evt_sz))
++ {
++
++ RT_TRACE(_module_rtl871x_cmd_c_,_drv_err_,("\nEvent(%d) Parm Size mismatch (%d vs %d)!\n",
++ evt_code, wlanevents[evt_code].parmsize, evt_sz));
++ goto _abort_event_;
++
++ }
++
++ ATOMIC_INC(&pevt_priv->event_seq);
++
++ peventbuf += 2;
++
++ if(peventbuf)
++ {
++ event_callback = wlanevents[evt_code].event_callback;
++ event_callback(padapter, (u8*)peventbuf);
++
++ pevt_priv->evt_done_cnt++;
++ }
++
++
++_abort_event_:
++
++
++ return H2C_SUCCESS;
++
++}
++
++u8 h2c_msg_hdl(_adapter *padapter, unsigned char *pbuf)
++{
++ if(!pbuf)
++ return H2C_PARAMETERS_ERROR;
++
++ return H2C_SUCCESS;
++}
++
++u8 tx_beacon_hdl(_adapter *padapter, unsigned char *pbuf)
++{
++ if(send_beacon(padapter)==_FAIL)
++ {
++ DBG_871X("issue_beacon, fail!\n");
++ return H2C_PARAMETERS_ERROR;
++ }
++#ifdef CONFIG_AP_MODE
++ else //tx bc/mc frames after update TIM
++ {
++ _irqL irqL;
++ struct sta_info *psta_bmc;
++ _list *xmitframe_plist, *xmitframe_phead;
++ struct xmit_frame *pxmitframe=NULL;
++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++ struct sta_priv *pstapriv = &padapter->stapriv;
++
++ //for BC/MC Frames
++ psta_bmc = rtw_get_bcmc_stainfo(padapter);
++ if(!psta_bmc)
++ return H2C_SUCCESS;
++
++ if((pstapriv->tim_bitmap&BIT(0)) && (psta_bmc->sleepq_len>0))
++ {
++#ifndef CONFIG_PCI_HCI
++ rtw_msleep_os(10);// 10ms, ATIM(HIQ) Windows
++#endif
++ //_enter_critical_bh(&psta_bmc->sleep_q.lock, &irqL);
++ _enter_critical_bh(&pxmitpriv->lock, &irqL);
++
++ xmitframe_phead = get_list_head(&psta_bmc->sleep_q);
++ xmitframe_plist = get_next(xmitframe_phead);
++
++ while ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE)
++ {
++ pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list);
++
++ xmitframe_plist = get_next(xmitframe_plist);
++
++ rtw_list_delete(&pxmitframe->list);
++
++ psta_bmc->sleepq_len--;
++ if(psta_bmc->sleepq_len>0)
++ pxmitframe->attrib.mdata = 1;
++ else
++ pxmitframe->attrib.mdata = 0;
++
++ pxmitframe->attrib.triggered=1;
++
++ pxmitframe->attrib.qsel = 0x11;//HIQ
++
++#if 0
++ _exit_critical_bh(&psta_bmc->sleep_q.lock, &irqL);
++ if(rtw_hal_xmit(padapter, pxmitframe) == _TRUE)
++ {
++ rtw_os_xmit_complete(padapter, pxmitframe);
++ }
++ _enter_critical_bh(&psta_bmc->sleep_q.lock, &irqL);
++
++#endif
++ rtw_hal_xmitframe_enqueue(padapter, pxmitframe);
++
++ //pstapriv->tim_bitmap &= ~BIT(0);
++
++ }
++
++ //_exit_critical_bh(&psta_bmc->sleep_q.lock, &irqL);
++ _exit_critical_bh(&pxmitpriv->lock, &irqL);
++
++ }
++
++ }
++#endif
++
++ return H2C_SUCCESS;
++
++}
++
++void change_band_update_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork)
++{
++ u8 network_type,rate_len, total_rate_len,remainder_rate_len;
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ u8 erpinfo=0x4;
++
++ //DBG_871X("%s\n", __FUNCTION__);
++
++ if(pmlmeext->cur_channel >= 36)
++ {
++ network_type = WIRELESS_11A;
++ total_rate_len = IEEE80211_NUM_OFDM_RATESLEN;
++ DBG_871X("%s(): change to 5G Band\n",__FUNCTION__);
++ rtw_remove_bcn_ie(padapter, pnetwork, _ERPINFO_IE_);
++ }
++ else
++ {
++ network_type = WIRELESS_11BG;
++ total_rate_len = IEEE80211_CCK_RATE_LEN+IEEE80211_NUM_OFDM_RATESLEN;
++ DBG_871X("%s(): change to 2.4G Band\n",__FUNCTION__);
++ rtw_add_bcn_ie(padapter, pnetwork, _ERPINFO_IE_, &erpinfo, 1);
++ }
++
++ rtw_set_supported_rate(pnetwork->SupportedRates, network_type);
++
++ UpdateBrateTbl(padapter, pnetwork->SupportedRates);
++ rtw_hal_set_hwreg(padapter, HW_VAR_BASIC_RATE, pnetwork->SupportedRates);
++
++ if(total_rate_len > 8)
++ {
++ rate_len = 8;
++ remainder_rate_len = total_rate_len - 8;
++ }
++ else
++ {
++ rate_len = total_rate_len;
++ remainder_rate_len = 0;
++ }
++
++ rtw_add_bcn_ie(padapter, pnetwork, _SUPPORTEDRATES_IE_, pnetwork->SupportedRates, rate_len);
++
++ if(remainder_rate_len)
++ {
++ rtw_add_bcn_ie(padapter, pnetwork, _EXT_SUPPORTEDRATES_IE_, (pnetwork->SupportedRates+8), remainder_rate_len);
++ }
++ else
++ {
++ rtw_remove_bcn_ie(padapter, pnetwork, _EXT_SUPPORTEDRATES_IE_);
++ }
++}
++
++
++#ifdef CONFIG_DUALMAC_CONCURRENT
++void dc_SelectChannel(_adapter *padapter, unsigned char channel)
++{
++ PADAPTER ptarget_adapter;
++
++ if( (padapter->pbuddy_adapter != NULL) &&
++ (padapter->DualMacConcurrent == _TRUE) &&
++ (padapter->adapter_type == SECONDARY_ADAPTER))
++ {
++ // only mac0 could control BB&RF
++ ptarget_adapter = padapter->pbuddy_adapter;
++ }
++ else
++ {
++ ptarget_adapter = padapter;
++ }
++
++ _enter_critical_mutex(&(adapter_to_dvobj(ptarget_adapter)->setch_mutex), NULL);
++
++ rtw_hal_set_chan(ptarget_adapter, channel);
++
++ _exit_critical_mutex(&(adapter_to_dvobj(ptarget_adapter)->setch_mutex), NULL);
++}
++
++void dc_SetBWMode(_adapter *padapter, unsigned short bwmode, unsigned char channel_offset)
++{
++ PADAPTER ptarget_adapter;
++
++ if( (padapter->pbuddy_adapter != NULL) &&
++ (padapter->DualMacConcurrent == _TRUE) &&
++ (padapter->adapter_type == SECONDARY_ADAPTER))
++ {
++ // only mac0 could control BB&RF
++ ptarget_adapter = padapter->pbuddy_adapter;
++ }
++ else
++ {
++ ptarget_adapter = padapter;
++ }
++
++ _enter_critical_mutex(&(adapter_to_dvobj(ptarget_adapter)->setbw_mutex), NULL);
++
++ rtw_hal_set_bwmode(ptarget_adapter, (HT_CHANNEL_WIDTH)bwmode, channel_offset);
++
++ _exit_critical_mutex(&(adapter_to_dvobj(ptarget_adapter)->setbw_mutex), NULL);
++}
++
++void dc_set_channel_bwmode_disconnect(_adapter *padapter)
++{
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ PADAPTER pbuddy_adapter = padapter->pbuddy_adapter;
++ struct mlme_priv *pbuddy_mlmepriv = NULL;
++
++ if(pbuddy_adapter != NULL &&
++ padapter->DualMacConcurrent == _TRUE)
++ {
++ pbuddy_mlmepriv = &(pbuddy_adapter->mlmepriv);
++ if((check_fwstate(pbuddy_mlmepriv, _FW_LINKED)) != _TRUE)
++ {
++ //switch to the 20M Hz mode after disconnect
++ pmlmeext->cur_bwmode = HT_CHANNEL_WIDTH_20;
++ pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++
++ set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode);
++ }
++ }
++ else
++ {
++ //switch to the 20M Hz mode after disconnect
++ pmlmeext->cur_bwmode = HT_CHANNEL_WIDTH_20;
++ pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++
++ set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode);
++ }
++}
++
++u8 dc_handle_join_request(_adapter *padapter)
++{
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX*)(&(pmlmeinfo->network));
++ PADAPTER pbuddy_adapter = padapter->pbuddy_adapter;
++ struct mlme_ext_priv *pbuddy_mlmeext = NULL;
++ struct mlme_priv *pbuddy_mlmepriv = NULL;
++ u8 ret = _SUCCESS;
++
++ if(pbuddy_adapter != NULL &&
++ padapter->DualMacConcurrent == _TRUE)
++ {
++ pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv;
++ pbuddy_mlmepriv = &(pbuddy_adapter->mlmepriv);
++
++ if(pmlmeext->cur_channel != pbuddy_mlmeext->cur_channel ||
++ pmlmeext->cur_bwmode != pbuddy_mlmeext->cur_bwmode ||
++ pmlmeext->cur_ch_offset != pbuddy_mlmeext->cur_ch_offset)
++ {
++ if((check_fwstate(pbuddy_mlmepriv, WIFI_AP_STATE)) == _TRUE)
++ {
++ //issue deauth to all stas if if2 is at ap mode
++ rtw_sta_flush(pbuddy_adapter);
++
++ //rtw_hal_set_hwreg(padapter, HW_VAR_CHECK_TXBUF, 0);
++ rtw_hal_set_hwreg(pbuddy_adapter, HW_VAR_CHECK_TXBUF, 0);
++ }
++ else if(check_fwstate(pbuddy_mlmepriv, _FW_LINKED) == _TRUE)
++ {
++ if(pmlmeext->cur_channel == pbuddy_mlmeext->cur_channel)
++ {
++ // HT_CHANNEL_WIDTH_40 or HT_CHANNEL_WIDTH_20 but channel offset is different
++ if((pmlmeext->cur_bwmode == pbuddy_mlmeext->cur_bwmode) &&
++ (pmlmeext->cur_ch_offset != pbuddy_mlmeext->cur_ch_offset) )
++ {
++ report_join_res(padapter, -4);
++ ret = _FAIL;
++ }
++ }
++ else
++ {
++ report_join_res(padapter, -4);
++ ret = _FAIL;
++ }
++ }
++ }
++ else if (is_client_associated_to_ap(pbuddy_adapter) == _TRUE)
++ {
++ issue_nulldata(pbuddy_adapter, NULL, 1, 0, 0);
++ }
++ }
++
++ return ret;
++}
++
++void dc_handle_join_done(_adapter *padapter, u8 join_res)
++{
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ PADAPTER pbuddy_adapter = padapter->pbuddy_adapter;
++ struct mlme_priv *pbuddy_mlmepriv = NULL;
++ struct mlme_ext_priv *pbuddy_mlmeext = NULL;
++ struct mlme_ext_info *pbuddy_mlmeinfo = NULL;
++ WLAN_BSSID_EX *pbuddy_network_mlmeext = NULL;
++ u8 change_band = _FALSE;
++
++
++ if(pbuddy_adapter != NULL &&
++ padapter->DualMacConcurrent == _TRUE)
++ {
++ pbuddy_mlmepriv = &(pbuddy_adapter->mlmepriv);
++ pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv;
++ pbuddy_mlmeinfo = &(pbuddy_mlmeext->mlmext_info);
++ pbuddy_network_mlmeext = &(pbuddy_mlmeinfo->network);
++
++ if(((pbuddy_mlmeinfo->state&0x03) == WIFI_FW_AP_STATE) &&
++ check_fwstate(pbuddy_mlmepriv, _FW_LINKED))
++ {
++ //restart and update beacon
++ DBG_871X("after join, current adapter, CH=%d, BW=%d, offset=%d\n", pmlmeext->cur_channel, pmlmeext->cur_bwmode, pmlmeext->cur_ch_offset);
++
++ if(join_res >= 0)
++ {
++ u8 *p;
++ int ie_len;
++ struct HT_info_element *pht_info=NULL;
++
++ if((pbuddy_mlmeext->cur_channel <= 14 && pmlmeext->cur_channel >= 36) ||
++ (pbuddy_mlmeext->cur_channel >= 36 && pmlmeext->cur_channel <= 14))
++ {
++ change_band = _TRUE;
++ }
++
++ //sync channel/bwmode/ch_offset with another adapter
++ pbuddy_mlmeext->cur_channel = pmlmeext->cur_channel;
++
++ if(pbuddy_mlmeext->cur_bwmode == HT_CHANNEL_WIDTH_40)
++ {
++ p = rtw_get_ie((pbuddy_network_mlmeext->IEs + sizeof(NDIS_802_11_FIXED_IEs)), _HT_ADD_INFO_IE_, &ie_len, (pbuddy_network_mlmeext->IELength - sizeof(NDIS_802_11_FIXED_IEs)));
++ if( p && ie_len)
++ {
++ pht_info = (struct HT_info_element *)(p+2);
++ pht_info->infos[0] &= ~(BIT(0)|BIT(1)); //no secondary channel is present
++ }
++
++ if(pmlmeext->cur_bwmode == HT_CHANNEL_WIDTH_40)
++ {
++ pbuddy_mlmeext->cur_ch_offset = pmlmeext->cur_ch_offset;
++
++ //to update cur_ch_offset value in beacon
++ if( pht_info )
++ {
++ switch(pmlmeext->cur_ch_offset)
++ {
++ case HAL_PRIME_CHNL_OFFSET_LOWER:
++ pht_info->infos[0] |= 0x1;
++ break;
++ case HAL_PRIME_CHNL_OFFSET_UPPER:
++ pht_info->infos[0] |= 0x3;
++ break;
++ case HAL_PRIME_CHNL_OFFSET_DONT_CARE:
++ default:
++ break;
++ }
++ }
++ }
++ else if(pmlmeext->cur_bwmode == HT_CHANNEL_WIDTH_20)
++ {
++ pbuddy_mlmeext->cur_bwmode = HT_CHANNEL_WIDTH_20;
++ pbuddy_mlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++
++ if(pmlmeext->cur_channel>0 && pmlmeext->cur_channel<5)
++ {
++ if(pht_info)
++ pht_info->infos[0] |= 0x1;
++
++ pbuddy_mlmeext->cur_bwmode = HT_CHANNEL_WIDTH_40;
++ pbuddy_mlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_LOWER;
++ }
++
++ if(pmlmeext->cur_channel>7 && pmlmeext->cur_channel<(14+1))
++ {
++ if(pht_info)
++ pht_info->infos[0] |= 0x3;
++
++ pbuddy_mlmeext->cur_bwmode = HT_CHANNEL_WIDTH_40;
++ pbuddy_mlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_UPPER;
++ }
++
++ set_channel_bwmode(padapter, pbuddy_mlmeext->cur_channel, pbuddy_mlmeext->cur_ch_offset, pbuddy_mlmeext->cur_bwmode);
++ }
++ }
++
++ // to update channel value in beacon
++ pbuddy_network_mlmeext->Configuration.DSConfig = pmlmeext->cur_channel;
++ p = rtw_get_ie((pbuddy_network_mlmeext->IEs + sizeof(NDIS_802_11_FIXED_IEs)), _DSSET_IE_, &ie_len, (pbuddy_network_mlmeext->IELength - sizeof(NDIS_802_11_FIXED_IEs)));
++ if(p && ie_len>0)
++ *(p + 2) = pmlmeext->cur_channel;
++
++ p = rtw_get_ie((pbuddy_network_mlmeext->IEs + sizeof(NDIS_802_11_FIXED_IEs)), _HT_ADD_INFO_IE_, &ie_len, (pbuddy_network_mlmeext->IELength - sizeof(NDIS_802_11_FIXED_IEs)));
++ if( p && ie_len)
++ {
++ pht_info = (struct HT_info_element *)(p+2);
++ pht_info->primary_channel = pmlmeext->cur_channel;
++ }
++
++ // update mlmepriv's cur_network
++ _rtw_memcpy(&pbuddy_mlmepriv->cur_network.network, pbuddy_network_mlmeext, pbuddy_network_mlmeext->Length);
++ }
++ else
++ {
++ // switch back to original channel/bwmode/ch_offset;
++ set_channel_bwmode(padapter, pbuddy_mlmeext->cur_channel, pbuddy_mlmeext->cur_ch_offset, pbuddy_mlmeext->cur_bwmode);
++ }
++
++ DBG_871X("after join, another adapter, CH=%d, BW=%d, offset=%d\n", pbuddy_mlmeext->cur_channel, pbuddy_mlmeext->cur_bwmode, pbuddy_mlmeext->cur_ch_offset);
++
++ if(change_band == _TRUE)
++ change_band_update_ie(pbuddy_adapter, pbuddy_network_mlmeext);
++
++ DBG_871X("update pbuddy_adapter's beacon\n");
++
++ update_beacon(pbuddy_adapter, 0, NULL, _TRUE);
++ }
++ else if (is_client_associated_to_ap(pbuddy_adapter) == _TRUE)
++ {
++ if((pbuddy_mlmeext->cur_bwmode == HT_CHANNEL_WIDTH_40) &&
++ (pmlmeext->cur_bwmode == HT_CHANNEL_WIDTH_20))
++ {
++ set_channel_bwmode(padapter, pbuddy_mlmeext->cur_channel, pbuddy_mlmeext->cur_ch_offset, pbuddy_mlmeext->cur_bwmode);
++ }
++
++ issue_nulldata(pbuddy_adapter, NULL, 0, 0, 0);
++ }
++ }
++}
++
++sint dc_check_fwstate(_adapter *padapter, sint fw_state)
++{
++ PADAPTER pbuddy_adapter = padapter->pbuddy_adapter;
++ struct mlme_priv *pbuddy_mlmepriv = NULL;
++
++ if(padapter->pbuddy_adapter != NULL &&
++ padapter->DualMacConcurrent == _TRUE)
++
++ {
++ pbuddy_mlmepriv = &(pbuddy_adapter->mlmepriv);
++
++ return check_fwstate(pbuddy_mlmepriv, fw_state);
++ }
++
++ return _FALSE;
++}
++
++u8 dc_handle_site_survey(_adapter *padapter)
++{
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ PADAPTER pbuddy_adapter = padapter->pbuddy_adapter;
++
++ // only mac0 can do scan request, help issue nulldata(1) for mac1
++ if(pbuddy_adapter != NULL &&
++ padapter->DualMacConcurrent == _TRUE)
++ {
++ if (is_client_associated_to_ap(pbuddy_adapter) == _TRUE)
++ {
++ pmlmeext->sitesurvey_res.state = SCAN_TXNULL;
++
++ issue_nulldata(pbuddy_adapter, NULL, 1, 2, 0);
++
++ return _TRUE;
++ }
++ }
++
++ return _FALSE;
++}
++
++void dc_report_survey_event(_adapter *padapter, union recv_frame *precv_frame)
++{
++ if(padapter->pbuddy_adapter != NULL &&
++ padapter->DualMacConcurrent == _TRUE)
++ {
++ report_survey_event(padapter->pbuddy_adapter, precv_frame);
++ }
++}
++
++void dc_set_channel_bwmode_survey_done(_adapter *padapter)
++{
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ PADAPTER pbuddy_adapter = padapter->pbuddy_adapter;
++ struct mlme_priv *pbuddy_mlmepriv = NULL;
++ struct mlme_ext_priv *pbuddy_mlmeext = NULL;
++ struct mlme_ext_info *pbuddy_mlmeinfo = NULL;
++ u8 cur_channel;
++ u8 cur_bwmode;
++ u8 cur_ch_offset;
++
++ if(pbuddy_adapter != NULL &&
++ padapter->DualMacConcurrent == _TRUE)
++ {
++ pbuddy_mlmepriv = &(pbuddy_adapter->mlmepriv);
++ pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv;
++ pbuddy_mlmeinfo = &(pbuddy_mlmeext->mlmext_info);
++
++ if(check_fwstate(pbuddy_mlmepriv, _FW_LINKED))
++ {
++ if(check_fwstate(pmlmepriv, _FW_LINKED) &&
++ (pmlmeext->cur_bwmode == HT_CHANNEL_WIDTH_40))
++ {
++ cur_channel = pmlmeext->cur_channel;
++ cur_bwmode = pmlmeext->cur_bwmode;
++ cur_ch_offset = pmlmeext->cur_ch_offset;
++ }
++ else
++ {
++ cur_channel = pbuddy_mlmeext->cur_channel;
++ cur_bwmode = pbuddy_mlmeext->cur_bwmode;
++ cur_ch_offset = pbuddy_mlmeext->cur_ch_offset;
++ }
++ }
++ else
++ {
++ cur_channel = pmlmeext->cur_channel;
++ cur_bwmode = pmlmeext->cur_bwmode;
++ cur_ch_offset = pmlmeext->cur_ch_offset;
++ }
++
++ set_channel_bwmode(padapter, cur_channel, cur_ch_offset, cur_bwmode);
++
++ if (is_client_associated_to_ap(pbuddy_adapter) == _TRUE)
++ {
++ //issue null data
++ issue_nulldata(pbuddy_adapter, NULL, 0, 0, 0);
++ }
++
++ if(((pbuddy_mlmeinfo->state&0x03) == WIFI_FW_AP_STATE) &&
++ check_fwstate(pbuddy_mlmepriv, _FW_LINKED))
++ {
++
++ DBG_871X("survey done, current CH=%d, BW=%d, offset=%d\n", cur_channel, cur_bwmode, cur_ch_offset);
++
++ DBG_871X("restart pbuddy_adapter's beacon\n");
++
++ update_beacon(pbuddy_adapter, 0, NULL, _TRUE);
++ }
++ }
++ else
++ {
++ set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode);
++ }
++}
++
++void dc_set_ap_channel_bandwidth(_adapter *padapter, u8 channel, u8 channel_offset, u8 bwmode)
++{
++ u8 *p;
++ u8 val8, cur_channel, cur_bwmode, cur_ch_offset, change_band;
++ int ie_len;
++ struct registry_priv *pregpriv = &padapter->registrypriv;
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)&pmlmepriv->cur_network.network;
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ struct HT_info_element *pht_info=NULL;
++ _adapter *pbuddy_adapter = padapter->pbuddy_adapter;
++ struct mlme_priv *pbuddy_mlmepriv = NULL;
++ struct mlme_ext_priv *pbuddy_mlmeext = NULL;
++
++ DBG_871X("dualmac_concurrent_ap_set_channel_bwmode ==>\n");
++
++ cur_channel = channel;
++ cur_bwmode = bwmode;
++ cur_ch_offset = channel_offset;
++ change_band = _FALSE;
++
++ p = rtw_get_ie((pnetwork->IEs + sizeof(NDIS_802_11_FIXED_IEs)), _HT_ADD_INFO_IE_, &ie_len, (pnetwork->IELength - sizeof(NDIS_802_11_FIXED_IEs)));
++ if( p && ie_len)
++ {
++ pht_info = (struct HT_info_element *)(p+2);
++ }
++
++ if(pbuddy_adapter != NULL &&
++ padapter->DualMacConcurrent == _TRUE)
++ {
++ pbuddy_mlmepriv = &(pbuddy_adapter->mlmepriv);
++ pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv;
++
++ if(!check_fwstate(pbuddy_mlmepriv, _FW_LINKED|_FW_UNDER_LINKING|_FW_UNDER_SURVEY))
++ {
++ set_channel_bwmode(padapter, cur_channel, cur_ch_offset, cur_bwmode);
++ }
++ else if(check_fwstate(pbuddy_mlmepriv, _FW_LINKED)==_TRUE)
++ {
++ //To sync cur_channel/cur_bwmode/cur_ch_offset with another adapter
++ DBG_871X("Another iface is at linked state, sync cur_channel/cur_bwmode/cur_ch_offset\n");
++ DBG_871X("Another adapter, CH=%d, BW=%d, offset=%d\n", pbuddy_mlmeext->cur_channel, pbuddy_mlmeext->cur_bwmode, pbuddy_mlmeext->cur_ch_offset);
++ DBG_871X("Current adapter, CH=%d, BW=%d, offset=%d\n", cur_channel, cur_bwmode, cur_ch_offset);
++
++ cur_channel = pbuddy_mlmeext->cur_channel;
++ if(cur_bwmode == HT_CHANNEL_WIDTH_40)
++ {
++ if(pht_info)
++ pht_info->infos[0] &= ~(BIT(0)|BIT(1));
++
++ if(pbuddy_mlmeext->cur_bwmode == HT_CHANNEL_WIDTH_40)
++ {
++ cur_ch_offset = pbuddy_mlmeext->cur_ch_offset;
++
++ //to update cur_ch_offset value in beacon
++ if(pht_info)
++ {
++ switch(cur_ch_offset)
++ {
++ case HAL_PRIME_CHNL_OFFSET_LOWER:
++ pht_info->infos[0] |= 0x1;
++ break;
++ case HAL_PRIME_CHNL_OFFSET_UPPER:
++ pht_info->infos[0] |= 0x3;
++ break;
++ case HAL_PRIME_CHNL_OFFSET_DONT_CARE:
++ default:
++ break;
++ }
++ }
++ }
++ else if(pbuddy_mlmeext->cur_bwmode == HT_CHANNEL_WIDTH_20)
++ {
++ cur_bwmode = HT_CHANNEL_WIDTH_20;
++ cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++
++ if(cur_channel>0 && cur_channel<5)
++ {
++ if(pht_info)
++ pht_info->infos[0] |= 0x1;
++
++ cur_bwmode = HT_CHANNEL_WIDTH_40;
++ cur_ch_offset = HAL_PRIME_CHNL_OFFSET_LOWER;
++ }
++
++ if(cur_channel>7 && cur_channel<(14+1))
++ {
++ if(pht_info)
++ pht_info->infos[0] |= 0x3;
++
++ cur_bwmode = HT_CHANNEL_WIDTH_40;
++ cur_ch_offset = HAL_PRIME_CHNL_OFFSET_UPPER;
++ }
++
++ set_channel_bwmode(padapter, cur_channel, cur_ch_offset, cur_bwmode);
++ }
++ }
++
++ // to update channel value in beacon
++ pnetwork->Configuration.DSConfig = cur_channel;
++ p = rtw_get_ie((pnetwork->IEs + sizeof(NDIS_802_11_FIXED_IEs)), _DSSET_IE_, &ie_len, (pnetwork->IELength - sizeof(NDIS_802_11_FIXED_IEs)));
++ if(p && ie_len>0)
++ *(p + 2) = cur_channel;
++
++ if(pht_info)
++ pht_info->primary_channel = cur_channel;
++ }
++ }
++ else
++ {
++ set_channel_bwmode(padapter, cur_channel, cur_ch_offset, cur_bwmode);
++ }
++
++ DBG_871X("CH=%d, BW=%d, offset=%d\n", cur_channel, cur_bwmode, cur_ch_offset);
++
++ if((channel <= 14 && cur_channel >= 36) ||
++ (channel >= 36 && cur_channel <= 14))
++ {
++ change_band = _TRUE;
++ }
++
++ pmlmeext->cur_channel = cur_channel;
++ pmlmeext->cur_bwmode = cur_bwmode;
++ pmlmeext->cur_ch_offset = cur_ch_offset;
++
++ if(change_band == _TRUE)
++ change_band_update_ie(padapter, pnetwork);
++
++ DBG_871X("dualmac_concurrent_ap_set_channel_bwmode <==\n");
++}
++
++void dc_resume_xmit(_adapter *padapter)
++{
++ PADAPTER pbuddy_adapter = padapter->pbuddy_adapter;
++
++ if(pbuddy_adapter != NULL &&
++ padapter->DualMacConcurrent == _TRUE)
++ {
++ DBG_871X("dc_resume_xmit, resume pbuddy_adapter Tx\n");
++ rtw_os_xmit_schedule(pbuddy_adapter);
++ }
++}
++
++u8 dc_check_xmit(_adapter *padapter)
++{
++ PADAPTER pbuddy_adapter = padapter->pbuddy_adapter;
++ struct mlme_priv *pbuddy_mlmepriv = NULL;
++
++ if(pbuddy_adapter != NULL &&
++ padapter->DualMacConcurrent == _TRUE)
++ {
++ pbuddy_mlmepriv = &(pbuddy_adapter->mlmepriv);
++ if (check_fwstate(pbuddy_mlmepriv, _FW_UNDER_SURVEY|_FW_UNDER_LINKING) == _TRUE)
++ {
++ DBG_871X("dc_check_xmit pbuddy_adapter is under survey or under linking\n");
++ return _FALSE;
++ }
++ }
++
++ return _TRUE;
++}
++#endif
++
++#ifdef CONFIG_CONCURRENT_MODE
++sint check_buddy_mlmeinfo_state(_adapter *padapter, u32 state)
++{
++ PADAPTER pbuddy_adapter;
++ struct mlme_ext_priv *pbuddy_mlmeext;
++ struct mlme_ext_info *pbuddy_mlmeinfo;
++
++ if(padapter == NULL)
++ return _FALSE;
++
++ pbuddy_adapter = padapter->pbuddy_adapter;
++
++ if(pbuddy_adapter == NULL)
++ return _FALSE;
++
++
++ pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv;
++ pbuddy_mlmeinfo = &(pbuddy_mlmeext->mlmext_info);
++
++ if((pbuddy_mlmeinfo->state&0x03) == state)
++ return _TRUE;
++
++ return _FALSE;
++
++}
++
++void concurrent_chk_joinbss_done(_adapter *padapter, int join_res)
++{
++ struct mlme_ext_priv *pmlmeext;
++ struct mlme_ext_info *pmlmeinfo;
++ PADAPTER pbuddy_adapter;
++ struct mlme_priv *pbuddy_mlmepriv;
++ struct mlme_ext_priv *pbuddy_mlmeext;
++ struct mlme_ext_info *pbuddy_mlmeinfo;
++ WLAN_BSSID_EX *pbuddy_network_mlmeext;
++
++ pmlmeext = &padapter->mlmeextpriv;
++ pmlmeinfo = &(pmlmeext->mlmext_info);
++
++
++ if(!rtw_buddy_adapter_up(padapter))
++ {
++ set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode);
++ return;
++ }
++
++ pbuddy_adapter = padapter->pbuddy_adapter;
++ pbuddy_mlmepriv = &(pbuddy_adapter->mlmepriv);
++ pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv;
++ pbuddy_mlmeinfo = &(pbuddy_mlmeext->mlmext_info);
++ pbuddy_network_mlmeext = &(pbuddy_mlmeinfo->network);
++
++ if(((pbuddy_mlmeinfo->state&0x03) == WIFI_FW_AP_STATE) &&
++ check_fwstate(pbuddy_mlmepriv, _FW_LINKED))
++ {
++ //restart and update beacon
++
++ DBG_871X("after join,primary adapter, CH=%d, BW=%d, offset=%d\n"
++ , pmlmeext->cur_channel, pmlmeext->cur_bwmode, pmlmeext->cur_ch_offset);
++
++
++ if(join_res >= 0)
++ {
++ u8 *p;
++ int ie_len;
++ u8 change_band = _FALSE;
++ struct HT_info_element *pht_info=NULL;
++
++ if((pmlmeext->cur_channel <= 14 && pbuddy_mlmeext->cur_channel >= 36) ||
++ (pmlmeext->cur_channel >= 36 && pbuddy_mlmeext->cur_channel <= 14))
++ change_band = _TRUE;
++
++ //sync channel/bwmode/ch_offset with primary adapter
++ pbuddy_mlmeext->cur_channel = pmlmeext->cur_channel;
++ if(pbuddy_mlmeext->cur_bwmode == HT_CHANNEL_WIDTH_40)
++ {
++ p = rtw_get_ie((pbuddy_network_mlmeext->IEs + sizeof(NDIS_802_11_FIXED_IEs)), _HT_ADD_INFO_IE_, &ie_len, (pbuddy_network_mlmeext->IELength - sizeof(NDIS_802_11_FIXED_IEs)));
++ if( p && ie_len)
++ {
++ pht_info = (struct HT_info_element *)(p+2);
++ pht_info->infos[0] &= ~(BIT(0)|BIT(1)); //no secondary channel is present
++ }
++
++ if(pmlmeext->cur_bwmode == HT_CHANNEL_WIDTH_40)
++ {
++ pbuddy_mlmeext->cur_ch_offset = pmlmeext->cur_ch_offset;
++
++ //to update cur_ch_offset value in beacon
++ if( pht_info )
++ {
++ switch(pmlmeext->cur_ch_offset)
++ {
++ case HAL_PRIME_CHNL_OFFSET_LOWER:
++ pht_info->infos[0] |= 0x1;
++ break;
++ case HAL_PRIME_CHNL_OFFSET_UPPER:
++ pht_info->infos[0] |= 0x3;
++ break;
++ case HAL_PRIME_CHNL_OFFSET_DONT_CARE:
++ default:
++ break;
++ }
++
++ }
++
++ }
++ else if(pmlmeext->cur_bwmode == HT_CHANNEL_WIDTH_20)
++ {
++ if(pmlmeext->cur_channel>=1 && pmlmeext->cur_channel<=4)
++ {
++ if(pht_info)
++ pht_info->infos[0] |= HT_INFO_HT_PARAM_SECONDARY_CHNL_ABOVE;
++
++ pbuddy_mlmeext->cur_bwmode = HT_CHANNEL_WIDTH_40;
++ pbuddy_mlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_LOWER;
++ }
++ else if(pmlmeext->cur_channel>=5 && pmlmeext->cur_channel<=14)
++ {
++ if(pht_info)
++ pht_info->infos[0] |= HT_INFO_HT_PARAM_SECONDARY_CHNL_BELOW;
++
++ pbuddy_mlmeext->cur_bwmode = HT_CHANNEL_WIDTH_40;
++ pbuddy_mlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_UPPER;
++ }
++ else
++ {
++ switch(pmlmeext->cur_channel)
++ {
++ case 36:
++ case 44:
++ case 52:
++ case 60:
++ case 100:
++ case 108:
++ case 116:
++ case 124:
++ case 132:
++ case 149:
++ case 157:
++ {
++ if(pht_info)
++ pht_info->infos[0] |= HT_INFO_HT_PARAM_SECONDARY_CHNL_ABOVE;
++ pbuddy_mlmeext->cur_bwmode = HT_CHANNEL_WIDTH_40;
++ pbuddy_mlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_LOWER;
++ break;
++ }
++ case 40:
++ case 48:
++ case 56:
++ case 64:
++ case 104:
++ case 112:
++ case 120:
++ case 128:
++ case 136:
++ case 153:
++ case 161:
++ {
++ if(pht_info)
++ pht_info->infos[0] |= HT_INFO_HT_PARAM_SECONDARY_CHNL_BELOW;
++
++ pbuddy_mlmeext->cur_bwmode = HT_CHANNEL_WIDTH_40;
++ pbuddy_mlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_UPPER;
++ break;
++ }
++ default:
++ if(pht_info)
++ pht_info->infos[0] &= ~HT_INFO_HT_PARAM_SECONDARY_CHNL_BELOW;
++ pbuddy_mlmeext->cur_bwmode = HT_CHANNEL_WIDTH_20;
++ pbuddy_mlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++ break;
++
++ }
++
++ }
++
++ }
++
++ set_channel_bwmode(padapter, pbuddy_mlmeext->cur_channel, pbuddy_mlmeext->cur_ch_offset, pbuddy_mlmeext->cur_bwmode);
++
++ }
++ else
++ {
++ set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode);
++ }
++
++
++ // to update channel value in beacon
++ pbuddy_network_mlmeext->Configuration.DSConfig = pmlmeext->cur_channel;
++ p = rtw_get_ie((pbuddy_network_mlmeext->IEs + sizeof(NDIS_802_11_FIXED_IEs)), _DSSET_IE_, &ie_len, (pbuddy_network_mlmeext->IELength - sizeof(NDIS_802_11_FIXED_IEs)));
++ if(p && ie_len>0)
++ *(p + 2) = pmlmeext->cur_channel;
++
++ p = rtw_get_ie((pbuddy_network_mlmeext->IEs + sizeof(NDIS_802_11_FIXED_IEs)), _HT_ADD_INFO_IE_, &ie_len, (pbuddy_network_mlmeext->IELength - sizeof(NDIS_802_11_FIXED_IEs)));
++ if( p && ie_len)
++ {
++ pht_info = (struct HT_info_element *)(p+2);
++ pht_info->primary_channel = pmlmeext->cur_channel;
++ }
++
++ //buddy interface band is different from current interface, update ERP, support rate, ext support rate IE
++ if(change_band == _TRUE)
++ change_band_update_ie(pbuddy_adapter, pbuddy_network_mlmeext);
++ }
++ else
++ {
++ // switch back to original channel/bwmode/ch_offset;
++ set_channel_bwmode(padapter, pbuddy_mlmeext->cur_channel, pbuddy_mlmeext->cur_ch_offset, pbuddy_mlmeext->cur_bwmode);
++ }
++
++ DBG_871X("after join, second adapter, CH=%d, BW=%d, offset=%d\n", pbuddy_mlmeext->cur_channel, pbuddy_mlmeext->cur_bwmode, pbuddy_mlmeext->cur_ch_offset);
++
++ DBG_871X("update pbuddy_adapter's beacon\n");
++
++ update_beacon(pbuddy_adapter, 0, NULL, _TRUE);
++
++ }
++ else if(((pbuddy_mlmeinfo->state&0x03) == WIFI_FW_STATION_STATE) &&
++ check_fwstate(pbuddy_mlmepriv, _FW_LINKED))
++ {
++ if(join_res >= 0)
++ {
++ pbuddy_mlmeext->cur_channel = pmlmeext->cur_channel;
++ if(pbuddy_mlmeext->cur_bwmode == HT_CHANNEL_WIDTH_40)
++ set_channel_bwmode(padapter, pbuddy_mlmeext->cur_channel, pbuddy_mlmeext->cur_ch_offset, pbuddy_mlmeext->cur_bwmode);
++ else if(pmlmeext->cur_bwmode == HT_CHANNEL_WIDTH_40)
++ set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode);
++ else
++ set_channel_bwmode(padapter, pmlmeext->cur_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HT_CHANNEL_WIDTH_20);
++ }
++ else
++ {
++ // switch back to original channel/bwmode/ch_offset;
++ set_channel_bwmode(padapter, pbuddy_mlmeext->cur_channel, pbuddy_mlmeext->cur_ch_offset, pbuddy_mlmeext->cur_bwmode);
++ }
++ }
++ else
++ {
++ set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode);
++ }
++
++}
++#endif //CONFIG_CONCURRENT_MODE
++
++int rtw_chk_start_clnt_join(_adapter *padapter)
++{
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ unsigned char cur_ch = pmlmeext->cur_channel;
++ unsigned char cur_bw = pmlmeext->cur_bwmode;
++ unsigned char cur_ch_offset = pmlmeext->cur_ch_offset;
++ bool chbw_allow = _TRUE;
++ bool connect_allow = _TRUE;
++
++#ifdef CONFIG_CONCURRENT_MODE
++ PADAPTER pbuddy_adapter;
++ struct mlme_ext_priv *pbuddy_mlmeext;
++ struct mlme_ext_info *pbuddy_pmlmeinfo;
++ struct mlme_priv *pbuddy_mlmepriv;
++
++ if (!rtw_buddy_adapter_up(padapter)) {
++ goto start_join_set_ch_bw;
++ }
++
++ pbuddy_adapter = padapter->pbuddy_adapter;
++ pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv;
++ pbuddy_pmlmeinfo = &(pbuddy_mlmeext->mlmext_info);
++ pbuddy_mlmepriv = &(pbuddy_adapter->mlmepriv);
++
++ if((pbuddy_pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE)//for AP MODE
++ {
++ DBG_871X("start_clnt_join: "ADPT_FMT"(ch=%d, bw=%d, ch_offset=%d)"
++ ", "ADPT_FMT" AP mode(ch=%d, bw=%d, ch_offset=%d)\n",
++ ADPT_ARG(padapter), pmlmeext->cur_channel, pmlmeext->cur_bwmode, pmlmeext->cur_ch_offset,
++ ADPT_ARG(pbuddy_adapter), pbuddy_mlmeext->cur_channel, pbuddy_mlmeext->cur_bwmode, pbuddy_mlmeext->cur_ch_offset);
++
++ if(pmlmeext->cur_channel != pbuddy_mlmeext->cur_channel)
++ {
++ chbw_allow = _FALSE;
++ }
++ else if((pmlmeext->cur_bwmode == HT_CHANNEL_WIDTH_40) &&
++ (pbuddy_mlmeext->cur_bwmode == HT_CHANNEL_WIDTH_40) &&
++ (pmlmeext->cur_ch_offset != pbuddy_mlmeext->cur_ch_offset))
++ {
++ chbw_allow = _FALSE;
++ }
++ else if((pmlmeext->cur_bwmode == HT_CHANNEL_WIDTH_20) &&
++ (pbuddy_mlmeext->cur_bwmode == HT_CHANNEL_WIDTH_40))
++ {
++ cur_ch = pmlmeext->cur_channel;
++ cur_bw = pbuddy_mlmeext->cur_bwmode;
++ cur_ch_offset = pbuddy_mlmeext->cur_ch_offset;
++ }
++
++ DBG_871X("start_clnt_join: connect_allow:%d, chbw_allow:%d\n", connect_allow, chbw_allow);
++ if (chbw_allow == _FALSE) {
++ #ifdef CONFIG_SPCT_CH_SWITCH
++ if (1) {
++ rtw_ap_inform_ch_switch(pbuddy_adapter, pmlmeext->cur_channel , pmlmeext->cur_ch_offset);
++ } else
++ #endif
++ {
++ //issue deauth to all stas if if2 is at ap mode
++ rtw_sta_flush(pbuddy_adapter);
++ }
++ rtw_hal_set_hwreg(padapter, HW_VAR_CHECK_TXBUF, 0);
++ }
++ }
++ else if(check_fwstate(pbuddy_mlmepriv, _FW_LINKED) == _TRUE &&
++ check_fwstate(pbuddy_mlmepriv, WIFI_STATION_STATE) == _TRUE) //for Client Mode/p2p client
++ {
++ DBG_871X("start_clnt_join: "ADPT_FMT"(ch=%d, bw=%d, ch_offset=%d)"
++ ", "ADPT_FMT" STA mode(ch=%d, bw=%d, ch_offset=%d)\n",
++ ADPT_ARG(padapter), pmlmeext->cur_channel, pmlmeext->cur_bwmode, pmlmeext->cur_ch_offset,
++ ADPT_ARG(pbuddy_adapter), pbuddy_mlmeext->cur_channel, pbuddy_mlmeext->cur_bwmode, pbuddy_mlmeext->cur_ch_offset);
++
++ if(pmlmeext->cur_channel != pbuddy_mlmeext->cur_channel)
++ {
++ chbw_allow = _FALSE;
++ }
++ else if((pmlmeext->cur_bwmode == HT_CHANNEL_WIDTH_20) &&
++ (pbuddy_mlmeext->cur_bwmode == HT_CHANNEL_WIDTH_40))
++ {
++ cur_bw = HT_CHANNEL_WIDTH_40;
++ cur_ch_offset = pbuddy_mlmeext->cur_ch_offset;
++ }
++ else if((pmlmeext->cur_bwmode == HT_CHANNEL_WIDTH_40) &&
++ (pbuddy_mlmeext->cur_bwmode == HT_CHANNEL_WIDTH_40) &&
++ (pmlmeext->cur_ch_offset != pbuddy_mlmeext->cur_ch_offset))
++ {
++ chbw_allow = _FALSE;
++ }
++
++ connect_allow = chbw_allow;
++
++ #if defined(CONFIG_P2P) && defined(CONFIG_IOCTL_CFG80211)
++ /* wlan0-sta mode has higher priority than p2p0-p2p client */
++ if (!rtw_p2p_chk_state(&(pbuddy_adapter->wdinfo), P2P_STATE_NONE)
++ && pbuddy_adapter->wdinfo.driver_interface == DRIVER_CFG80211)
++ {
++ connect_allow = _TRUE;
++ }
++ #endif /* CONFIG_P2P && CONFIG_IOCTL_CFG80211 */
++
++ DBG_871X("start_clnt_join: connect_allow:%d, chbw_allow:%d\n", connect_allow, chbw_allow);
++ if (connect_allow == _TRUE && chbw_allow == _FALSE) {
++ /* disconnect buddy's connection */
++ rtw_disassoc_cmd(pbuddy_adapter, 500, _FALSE);
++ rtw_indicate_disconnect(pbuddy_adapter);
++ rtw_free_assoc_resources(pbuddy_adapter, 1);
++ }
++ }
++
++start_join_set_ch_bw:
++#endif /* CONFIG_CONCURRENT_MODE */
++
++ if (connect_allow == _TRUE) {
++ DBG_871X("start_join_set_ch_bw: ch=%d, bwmode=%d, ch_offset=%d\n", cur_ch, cur_bw, cur_ch_offset);
++ set_channel_bwmode(padapter, cur_ch, cur_ch_offset, cur_bw);
++ }
++
++ return connect_allow == _TRUE ? _SUCCESS : _FAIL;
++}
++
++/* Find union about ch, bw, ch_offset of all linked interfaces */
++int rtw_get_ch_setting_union(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset)
++{
++ struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++ _adapter *iface;
++ struct mlme_ext_priv *mlmeext;
++ int i;
++ u8 ch_ret = 0;
++ u8 bw_ret = HT_CHANNEL_WIDTH_20;
++ u8 offset_ret = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++ int num = 0;
++
++ if (ch) *ch = 0;
++ if (bw) *bw = HT_CHANNEL_WIDTH_20;
++ if (offset) *offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++
++ for (i = 0; i<dvobj->iface_nums; i++) {
++ iface = dvobj->padapters[i];
++ mlmeext = &iface->mlmeextpriv;
++
++ if (!check_fwstate(&iface->mlmepriv, _FW_LINKED))
++ continue;
++
++ if (num == 0) {
++ ch_ret = mlmeext->cur_channel;
++ bw_ret = mlmeext->cur_bwmode;
++ offset_ret = mlmeext->cur_ch_offset;
++ num++;
++ continue;
++ }
++
++ if (ch_ret != mlmeext->cur_channel) {
++ num = 0;
++ break;
++ }
++
++ if (bw_ret < mlmeext->cur_bwmode) {
++ bw_ret = mlmeext->cur_bwmode;
++ offset_ret = mlmeext->cur_ch_offset;
++ } else if (bw_ret == mlmeext->cur_bwmode && offset_ret != mlmeext->cur_ch_offset) {
++ num = 0;
++ break;
++ }
++
++ num++;
++ }
++
++ if (num) {
++ if (ch) *ch = ch_ret;
++ if (bw) *bw = bw_ret;
++ if (offset) *offset = offset_ret;
++ }
++
++ return num;
++}
++
++u8 set_ch_hdl(_adapter *padapter, u8 *pbuf)
++{
++ struct set_ch_parm *set_ch_parm;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++
++ if(!pbuf)
++ return H2C_PARAMETERS_ERROR;
++
++ set_ch_parm = (struct set_ch_parm *)pbuf;
++
++ DBG_871X(FUNC_NDEV_FMT" ch:%u, bw:%u, ch_offset:%u\n",
++ FUNC_NDEV_ARG(padapter->pnetdev),
++ set_ch_parm->ch, set_ch_parm->bw, set_ch_parm->ch_offset);
++
++ pmlmeext->cur_channel = set_ch_parm->ch;
++ pmlmeext->cur_ch_offset = set_ch_parm->ch_offset;
++ pmlmeext->cur_bwmode = set_ch_parm->bw;
++
++ set_channel_bwmode(padapter, set_ch_parm->ch, set_ch_parm->ch_offset, set_ch_parm->bw);
++
++ return H2C_SUCCESS;
++}
++
++u8 set_chplan_hdl(_adapter *padapter, unsigned char *pbuf)
++{
++ struct SetChannelPlan_param *setChannelPlan_param;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++
++ if(!pbuf)
++ return H2C_PARAMETERS_ERROR;
++
++ setChannelPlan_param = (struct SetChannelPlan_param *)pbuf;
++
++ pmlmeext->max_chan_nums = init_channel_set(padapter, setChannelPlan_param->channel_plan, pmlmeext->channel_set);
++ init_channel_list(padapter, pmlmeext->channel_set, pmlmeext->max_chan_nums, &pmlmeext->channel_list);
++
++ return H2C_SUCCESS;
++}
++
++u8 led_blink_hdl(_adapter *padapter, unsigned char *pbuf)
++{
++ struct LedBlink_param *ledBlink_param;
++
++ if(!pbuf)
++ return H2C_PARAMETERS_ERROR;
++
++ ledBlink_param = (struct LedBlink_param *)pbuf;
++
++ #ifdef CONFIG_LED_HANDLED_BY_CMD_THREAD
++ BlinkHandler(ledBlink_param->pLed);
++ #endif
++
++ return H2C_SUCCESS;
++}
++
++u8 set_csa_hdl(_adapter *padapter, unsigned char *pbuf)
++{
++#ifdef CONFIG_DFS
++ struct SetChannelSwitch_param *setChannelSwitch_param;
++ struct SetChannelPlan_param *setChannelPlan_param;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
++ u8 new_ch_no;
++ u8 gval8 = 0x00, sval8 = 0xff;
++
++ if(!pbuf)
++ return H2C_PARAMETERS_ERROR;
++
++ setChannelSwitch_param = (struct SetChannelSwitch_param *)pbuf;
++ new_ch_no = setChannelSwitch_param->new_ch_no;
++
++ rtw_hal_get_hwreg(padapter, HW_VAR_TXPAUSE, &gval8);
++
++ rtw_hal_set_hwreg(padapter, HW_VAR_TXPAUSE, &sval8);
++
++ DBG_871X("DFS detected! Swiching channel to %d!\n", new_ch_no);
++ SelectChannel(padapter, new_ch_no);
++
++ rtw_hal_set_hwreg(padapter, HW_VAR_TXPAUSE, &gval8);
++
++ rtw_free_network_queue(padapter, _TRUE);
++ rtw_indicate_disconnect(padapter);
++
++ if ( ((new_ch_no >= 52) && (new_ch_no <= 64)) ||((new_ch_no >= 100) && (new_ch_no <= 140)) ) {
++ DBG_871X("Switched to DFS band (ch %02x) again!!\n", new_ch_no);
++ }
++
++ return H2C_SUCCESS;
++#else
++ return H2C_REJECTED;
++#endif //CONFIG_DFS
++
++}
++
++// TDLS_WRCR : write RCR DATA BIT
++// TDLS_SD_PTI : issue peer traffic indication
++// TDLS_CS_OFF : go back to the channel linked with AP, terminating channel switch procedure
++// TDLS_INIT_CH_SEN : init channel sensing, receive all data and mgnt frame
++// TDLS_DONE_CH_SEN: channel sensing and report candidate channel
++// TDLS_OFF_CH : first time set channel to off channel
++// TDLS_BASE_CH : go back tp the channel linked with AP when set base channel as target channel
++// TDLS_P_OFF_CH : periodically go to off channel
++// TDLS_P_BASE_CH : periodically go back to base channel
++// TDLS_RS_RCR : restore RCR
++// TDLS_CKALV_PH1 : check alive timer phase1
++// TDLS_CKALV_PH2 : check alive timer phase2
++// TDLS_FREE_STA : free tdls sta
++u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf)
++{
++#ifdef CONFIG_TDLS
++ _irqL irqL;
++ struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
++ struct TDLSoption_param *TDLSoption;
++ struct sta_info *ptdls_sta;
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
++ u8 survey_channel, i, min, option;
++
++ if(!pbuf)
++ return H2C_PARAMETERS_ERROR;
++
++ TDLSoption = (struct TDLSoption_param *)pbuf;
++
++ ptdls_sta = rtw_get_stainfo( &(padapter->stapriv), TDLSoption->addr );
++ option = TDLSoption->option;
++
++ if( ptdls_sta == NULL )
++ {
++ if( option != TDLS_RS_RCR )
++ return H2C_REJECTED;
++ }
++
++ //_enter_critical_bh(&(ptdlsinfo->hdl_lock), &irqL);
++ DBG_871X("[%s] option:%d\n", __FUNCTION__, option);
++
++ switch(option){
++ case TDLS_WRCR:
++ //As long as TDLS handshake success, we should set RCR_CBSSID_DATA bit to 0
++ //such we can receive all kinds of data frames.
++ rtw_hal_set_hwreg(padapter, HW_VAR_TDLS_WRCR, 0);
++ DBG_871X("TDLS with "MAC_FMT"\n", MAC_ARG(ptdls_sta->hwaddr));
++
++ pmlmeinfo->FW_sta_info[ptdls_sta->mac_id].psta = ptdls_sta;
++ //set TDLS sta rate.
++ set_sta_rate(padapter, ptdls_sta);
++ break;
++ case TDLS_SD_PTI:
++ issue_tdls_peer_traffic_indication(padapter, ptdls_sta);
++ break;
++ case TDLS_CS_OFF:
++ _cancel_timer_ex(&ptdls_sta->base_ch_timer);
++ _cancel_timer_ex(&ptdls_sta->off_ch_timer);
++ SelectChannel(padapter, pmlmeext->cur_channel);
++ ptdls_sta->tdls_sta_state &= ~(TDLS_CH_SWITCH_ON_STATE |
++ TDLS_PEER_AT_OFF_STATE |
++ TDLS_AT_OFF_CH_STATE);
++ DBG_871X("go back to base channel\n ");
++ issue_nulldata(padapter, NULL, 0, 0, 0);
++ break;
++ case TDLS_INIT_CH_SEN:
++ rtw_hal_set_hwreg(padapter, HW_VAR_TDLS_INIT_CH_SEN, 0);
++ pmlmeext->sitesurvey_res.channel_idx = 0;
++ ptdls_sta->option = TDLS_DONE_CH_SEN;
++ rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_DONE_CH_SEN);
++ break;
++ case TDLS_DONE_CH_SEN:
++ survey_channel = pmlmeext->channel_set[pmlmeext->sitesurvey_res.channel_idx].ChannelNum;
++ if(survey_channel){
++ SelectChannel(padapter, survey_channel);
++ ptdlsinfo->cur_channel = survey_channel;
++ pmlmeext->sitesurvey_res.channel_idx++;
++ _set_timer(&ptdls_sta->option_timer, SURVEY_TO);
++ }else{
++ SelectChannel(padapter, pmlmeext->cur_channel);
++
++ rtw_hal_set_hwreg(padapter, HW_VAR_TDLS_DONE_CH_SEN, 0);
++
++ if(ptdlsinfo->ch_sensing==1){
++ ptdlsinfo->ch_sensing=0;
++ ptdlsinfo->cur_channel=1;
++ min=ptdlsinfo->collect_pkt_num[0];
++ for(i=1; i<MAX_CHANNEL_NUM-1; i++){
++ if(min > ptdlsinfo->collect_pkt_num[i]){
++ ptdlsinfo->cur_channel=i+1;
++ min=ptdlsinfo->collect_pkt_num[i];
++ }
++ ptdlsinfo->collect_pkt_num[i]=0;
++ }
++ ptdlsinfo->collect_pkt_num[0]=0;
++ ptdlsinfo->candidate_ch=ptdlsinfo->cur_channel;
++ DBG_871X("TDLS channel sensing done, candidate channel: %02x\n", ptdlsinfo->candidate_ch);
++ ptdlsinfo->cur_channel=0;
++
++ }
++
++ if(ptdls_sta->tdls_sta_state & TDLS_PEER_SLEEP_STATE){
++ ptdls_sta->tdls_sta_state |= TDLS_APSD_CHSW_STATE;
++ }else{
++ //send null data with pwrbit==1 before send ch_switching_req to peer STA.
++ issue_nulldata(padapter, NULL, 1, 0, 0);
++
++ ptdls_sta->tdls_sta_state |= TDLS_CH_SW_INITIATOR_STATE;
++
++ issue_tdls_ch_switch_req(padapter, ptdls_sta->hwaddr);
++ DBG_871X("issue tdls ch switch req\n");
++ }
++ }
++ break;
++ case TDLS_OFF_CH:
++ issue_nulldata(padapter, NULL, 1, 0, 0);
++ SelectChannel(padapter, ptdls_sta->off_ch);
++
++ DBG_871X("change channel to tar ch:%02x\n", ptdls_sta->off_ch);
++ ptdls_sta->tdls_sta_state |= TDLS_AT_OFF_CH_STATE;
++ ptdls_sta->tdls_sta_state &= ~(TDLS_PEER_AT_OFF_STATE);
++ _set_timer(&ptdls_sta->option_timer, (u32)ptdls_sta->ch_switch_time);
++ break;
++ case TDLS_BASE_CH:
++ _cancel_timer_ex(&ptdls_sta->base_ch_timer);
++ _cancel_timer_ex(&ptdls_sta->off_ch_timer);
++ SelectChannel(padapter, pmlmeext->cur_channel);
++ ptdls_sta->tdls_sta_state &= ~(TDLS_CH_SWITCH_ON_STATE |
++ TDLS_PEER_AT_OFF_STATE |
++ TDLS_AT_OFF_CH_STATE);
++ DBG_871X("go back to base channel\n ");
++ issue_nulldata(padapter, NULL, 0, 0, 0);
++ _set_timer(&ptdls_sta->option_timer, (u32)ptdls_sta->ch_switch_time);
++ break;
++ case TDLS_P_OFF_CH:
++ SelectChannel(padapter, pmlmeext->cur_channel);
++ issue_nulldata(padapter, NULL, 0, 0, 0);
++ DBG_871X("change channel to base ch:%02x\n", pmlmeext->cur_channel);
++ ptdls_sta->tdls_sta_state &= ~(TDLS_PEER_AT_OFF_STATE| TDLS_AT_OFF_CH_STATE);
++ _set_timer(&ptdls_sta->off_ch_timer, TDLS_STAY_TIME);
++ break;
++ case TDLS_P_BASE_CH:
++ issue_nulldata(ptdls_sta->padapter, NULL, 1, 0, 0);
++ SelectChannel(padapter, ptdls_sta->off_ch);
++ DBG_871X("change channel to off ch:%02x\n", ptdls_sta->off_ch);
++ ptdls_sta->tdls_sta_state |= TDLS_AT_OFF_CH_STATE;
++ if((ptdls_sta->tdls_sta_state & TDLS_PEER_AT_OFF_STATE) != TDLS_PEER_AT_OFF_STATE){
++ issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta, 0);
++ }
++ _set_timer(&ptdls_sta->base_ch_timer, TDLS_STAY_TIME);
++ break;
++ case TDLS_RS_RCR:
++ rtw_hal_set_hwreg(padapter, HW_VAR_TDLS_RS_RCR, 0);
++ DBG_871X("wirte REG_RCR, set bit6 on\n");
++ break;
++ case TDLS_CKALV_PH1:
++ _set_timer(&ptdls_sta->alive_timer2, TDLS_ALIVE_TIMER_PH2);
++ break;
++ case TDLS_CKALV_PH2:
++ _set_timer(&ptdls_sta->alive_timer1, TDLS_ALIVE_TIMER_PH1);
++ break;
++ case TDLS_FREE_STA:
++ free_tdls_sta(padapter, ptdls_sta);
++ break;
++
++ }
++
++ //_exit_critical_bh(&(ptdlsinfo->hdl_lock), &irqL);
++
++ return H2C_SUCCESS;
++#else
++ return H2C_REJECTED;
++#endif //CONFIG_TDLS
++
++}
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/core/rtw_mp.c linux-xbian-rpi/drivers/net/wireless/rtl8192cu/core/rtw_mp.c
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/core/rtw_mp.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/core/rtw_mp.c 2015-07-28 01:20:58.305654202 +0200
+@@ -0,0 +1,1323 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#define _RTW_MP_C_
++
++#include <drv_types.h>
++
++#ifdef PLATFORM_FREEBSD
++#include <sys/unistd.h> /* for RFHIGHPID */
++#endif
++
++#ifdef CONFIG_RTL8712
++#include <rtw_mp_phy_regdef.h>
++#endif
++#ifdef CONFIG_RTL8192C
++#include <rtl8192c_hal.h>
++#endif
++#ifdef CONFIG_RTL8192D
++#include <rtl8192d_hal.h>
++#endif
++#ifdef CONFIG_RTL8723A
++#include <rtl8723a_hal.h>
++#endif
++
++
++#ifdef CONFIG_MP_INCLUDED
++
++u32 read_macreg(_adapter *padapter, u32 addr, u32 sz)
++{
++ u32 val = 0;
++
++ switch(sz)
++ {
++ case 1:
++ val = rtw_read8(padapter, addr);
++ break;
++ case 2:
++ val = rtw_read16(padapter, addr);
++ break;
++ case 4:
++ val = rtw_read32(padapter, addr);
++ break;
++ default:
++ val = 0xffffffff;
++ break;
++ }
++
++ return val;
++
++}
++
++void write_macreg(_adapter *padapter, u32 addr, u32 val, u32 sz)
++{
++ switch(sz)
++ {
++ case 1:
++ rtw_write8(padapter, addr, (u8)val);
++ break;
++ case 2:
++ rtw_write16(padapter, addr, (u16)val);
++ break;
++ case 4:
++ rtw_write32(padapter, addr, val);
++ break;
++ default:
++ break;
++ }
++
++}
++
++u32 read_bbreg(_adapter *padapter, u32 addr, u32 bitmask)
++{
++ return rtw_hal_read_bbreg(padapter, addr, bitmask);
++}
++
++void write_bbreg(_adapter *padapter, u32 addr, u32 bitmask, u32 val)
++{
++ rtw_hal_write_bbreg(padapter, addr, bitmask, val);
++}
++
++u32 _read_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 bitmask)
++{
++ return rtw_hal_read_rfreg(padapter, (RF_RADIO_PATH_E)rfpath, addr, bitmask);
++}
++
++void _write_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 bitmask, u32 val)
++{
++ rtw_hal_write_rfreg(padapter, (RF_RADIO_PATH_E)rfpath, addr, bitmask, val);
++}
++
++u32 read_rfreg(PADAPTER padapter, u8 rfpath, u32 addr)
++{
++ return _read_rfreg(padapter, (RF_RADIO_PATH_E)rfpath, addr, bRFRegOffsetMask);
++}
++
++void write_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 val)
++{
++ _write_rfreg(padapter, (RF_RADIO_PATH_E)rfpath, addr, bRFRegOffsetMask, val);
++}
++
++static void _init_mp_priv_(struct mp_priv *pmp_priv)
++{
++ WLAN_BSSID_EX *pnetwork;
++
++ _rtw_memset(pmp_priv, 0, sizeof(struct mp_priv));
++
++ pmp_priv->mode = MP_OFF;
++
++ pmp_priv->channel = 1;
++ pmp_priv->bandwidth = HT_CHANNEL_WIDTH_20;
++ pmp_priv->prime_channel_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++ pmp_priv->rateidx = MPT_RATE_1M;
++ pmp_priv->txpoweridx = 0x2A;
++
++ pmp_priv->antenna_tx = ANTENNA_A;
++ pmp_priv->antenna_rx = ANTENNA_AB;
++
++ pmp_priv->check_mp_pkt = 0;
++
++ pmp_priv->tx_pktcount = 0;
++
++ pmp_priv->rx_pktcount = 0;
++ pmp_priv->rx_crcerrpktcount = 0;
++
++ pmp_priv->network_macaddr[0] = 0x00;
++ pmp_priv->network_macaddr[1] = 0xE0;
++ pmp_priv->network_macaddr[2] = 0x4C;
++ pmp_priv->network_macaddr[3] = 0x87;
++ pmp_priv->network_macaddr[4] = 0x66;
++ pmp_priv->network_macaddr[5] = 0x55;
++
++ pnetwork = &pmp_priv->mp_network.network;
++ _rtw_memcpy(pnetwork->MacAddress, pmp_priv->network_macaddr, ETH_ALEN);
++
++ pnetwork->Ssid.SsidLength = 8;
++ _rtw_memcpy(pnetwork->Ssid.Ssid, "mp_871x", pnetwork->Ssid.SsidLength);
++}
++
++#ifdef PLATFORM_WINDOWS
++/*
++void mp_wi_callback(
++ IN NDIS_WORK_ITEM* pwk_item,
++ IN PVOID cntx
++ )
++{
++ _adapter* padapter =(_adapter *)cntx;
++ struct mp_priv *pmppriv=&padapter->mppriv;
++ struct mp_wi_cntx *pmp_wi_cntx=&pmppriv->wi_cntx;
++
++ // Execute specified action.
++ if(pmp_wi_cntx->curractfunc != NULL)
++ {
++ LARGE_INTEGER cur_time;
++ ULONGLONG start_time, end_time;
++ NdisGetCurrentSystemTime(&cur_time); // driver version
++ start_time = cur_time.QuadPart/10; // The return value is in microsecond
++
++ pmp_wi_cntx->curractfunc(padapter);
++
++ NdisGetCurrentSystemTime(&cur_time); // driver version
++ end_time = cur_time.QuadPart/10; // The return value is in microsecond
++
++ RT_TRACE(_module_mp_, _drv_info_,
++ ("WorkItemActType: %d, time spent: %I64d us\n",
++ pmp_wi_cntx->param.act_type, (end_time-start_time)));
++ }
++
++ NdisAcquireSpinLock(&(pmp_wi_cntx->mp_wi_lock));
++ pmp_wi_cntx->bmp_wi_progress= _FALSE;
++ NdisReleaseSpinLock(&(pmp_wi_cntx->mp_wi_lock));
++
++ if (pmp_wi_cntx->bmpdrv_unload)
++ {
++ NdisSetEvent(&(pmp_wi_cntx->mp_wi_evt));
++ }
++
++}
++*/
++
++static int init_mp_priv_by_os(struct mp_priv *pmp_priv)
++{
++ struct mp_wi_cntx *pmp_wi_cntx;
++
++ if (pmp_priv == NULL) return _FAIL;
++
++ pmp_priv->rx_testcnt = 0;
++ pmp_priv->rx_testcnt1 = 0;
++ pmp_priv->rx_testcnt2 = 0;
++
++ pmp_priv->tx_testcnt = 0;
++ pmp_priv->tx_testcnt1 = 0;
++
++ pmp_wi_cntx = &pmp_priv->wi_cntx
++ pmp_wi_cntx->bmpdrv_unload = _FALSE;
++ pmp_wi_cntx->bmp_wi_progress = _FALSE;
++ pmp_wi_cntx->curractfunc = NULL;
++
++ return _SUCCESS;
++}
++#endif
++
++#ifdef PLATFORM_LINUX
++static int init_mp_priv_by_os(struct mp_priv *pmp_priv)
++{
++ int i, res;
++ struct mp_xmit_frame *pmp_xmitframe;
++
++ if (pmp_priv == NULL) return _FAIL;
++
++ _rtw_init_queue(&pmp_priv->free_mp_xmitqueue);
++
++ pmp_priv->pallocated_mp_xmitframe_buf = NULL;
++ pmp_priv->pallocated_mp_xmitframe_buf = rtw_zmalloc(NR_MP_XMITFRAME * sizeof(struct mp_xmit_frame) + 4);
++ if (pmp_priv->pallocated_mp_xmitframe_buf == NULL) {
++ res = _FAIL;
++ goto _exit_init_mp_priv;
++ }
++
++ pmp_priv->pmp_xmtframe_buf = pmp_priv->pallocated_mp_xmitframe_buf + 4 - ((uint) (pmp_priv->pallocated_mp_xmitframe_buf) & 3);
++
++ pmp_xmitframe = (struct mp_xmit_frame*)pmp_priv->pmp_xmtframe_buf;
++
++ for (i = 0; i < NR_MP_XMITFRAME; i++)
++ {
++ _rtw_init_listhead(&pmp_xmitframe->list);
++ rtw_list_insert_tail(&pmp_xmitframe->list, &pmp_priv->free_mp_xmitqueue.queue);
++
++ pmp_xmitframe->pkt = NULL;
++ pmp_xmitframe->frame_tag = MP_FRAMETAG;
++ pmp_xmitframe->padapter = pmp_priv->papdater;
++
++ pmp_xmitframe++;
++ }
++
++ pmp_priv->free_mp_xmitframe_cnt = NR_MP_XMITFRAME;
++
++ res = _SUCCESS;
++
++_exit_init_mp_priv:
++
++ return res;
++}
++#endif
++
++static void mp_init_xmit_attrib(struct mp_tx *pmptx, PADAPTER padapter)
++{
++ struct pkt_attrib *pattrib;
++ struct tx_desc *desc;
++
++ // init xmitframe attribute
++ pattrib = &pmptx->attrib;
++ _rtw_memset(pattrib, 0, sizeof(struct pkt_attrib));
++ desc = &pmptx->desc;
++ _rtw_memset(desc, 0, TXDESC_SIZE);
++
++ pattrib->ether_type = 0x8712;
++ //_rtw_memcpy(pattrib->src, padapter->eeprompriv.mac_addr, ETH_ALEN);
++// _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
++ _rtw_memset(pattrib->dst, 0xFF, ETH_ALEN);
++// pattrib->pctrl = 0;
++// pattrib->dhcp_pkt = 0;
++// pattrib->pktlen = 0;
++ pattrib->ack_policy = 0;
++// pattrib->pkt_hdrlen = ETH_HLEN;
++ pattrib->hdrlen = WLAN_HDR_A3_LEN;
++ pattrib->subtype = WIFI_DATA;
++ pattrib->priority = 0;
++ pattrib->qsel = pattrib->priority;
++// do_queue_select(padapter, pattrib);
++ pattrib->nr_frags = 1;
++ pattrib->encrypt = 0;
++ pattrib->bswenc = _FALSE;
++ pattrib->qos_en = _FALSE;
++}
++
++s32 init_mp_priv(PADAPTER padapter)
++{
++ struct mp_priv *pmppriv = &padapter->mppriv;
++
++ _init_mp_priv_(pmppriv);
++ pmppriv->papdater = padapter;
++
++ pmppriv->tx.stop = 1;
++ mp_init_xmit_attrib(&pmppriv->tx, padapter);
++
++ switch (padapter->registrypriv.rf_config) {
++ case RF_1T1R:
++ pmppriv->antenna_tx = ANTENNA_A;
++ pmppriv->antenna_rx = ANTENNA_A;
++ break;
++ case RF_1T2R:
++ default:
++ pmppriv->antenna_tx = ANTENNA_A;
++ pmppriv->antenna_rx = ANTENNA_AB;
++ break;
++ case RF_2T2R:
++ case RF_2T2R_GREEN:
++ pmppriv->antenna_tx = ANTENNA_AB;
++ pmppriv->antenna_rx = ANTENNA_AB;
++ break;
++ case RF_2T4R:
++ pmppriv->antenna_tx = ANTENNA_AB;
++ pmppriv->antenna_rx = ANTENNA_ABCD;
++ break;
++ }
++
++ return _SUCCESS;
++}
++
++void free_mp_priv(struct mp_priv *pmp_priv)
++{
++ if (pmp_priv->pallocated_mp_xmitframe_buf) {
++ rtw_mfree(pmp_priv->pallocated_mp_xmitframe_buf, 0);
++ pmp_priv->pallocated_mp_xmitframe_buf = NULL;
++ }
++ pmp_priv->pmp_xmtframe_buf = NULL;
++}
++
++#ifdef CONFIG_RTL8192C
++#define PHY_IQCalibrate(a,b) rtl8192c_PHY_IQCalibrate(a,b)
++#define PHY_LCCalibrate(a) rtl8192c_PHY_LCCalibrate(a)
++#define dm_CheckTXPowerTracking(a) rtl8192c_dm_CheckTXPowerTracking(a)
++#define PHY_SetRFPathSwitch(a,b) rtl8192c_PHY_SetRFPathSwitch(a,b)
++#endif
++
++#ifdef CONFIG_RTL8192D
++#define PHY_IQCalibrate(a) rtl8192d_PHY_IQCalibrate(a)
++#define PHY_LCCalibrate(a) rtl8192d_PHY_LCCalibrate(a)
++#define dm_CheckTXPowerTracking(a) rtl8192d_dm_CheckTXPowerTracking(a)
++#define PHY_SetRFPathSwitch(a,b) rtl8192d_PHY_SetRFPathSwitch(a,b)
++#endif
++
++s32
++MPT_InitializeAdapter(
++ IN PADAPTER pAdapter,
++ IN u8 Channel
++ )
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
++ s32 rtStatus = _SUCCESS;
++ PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.MptCtx;
++ u32 ledsetting;
++
++ //-------------------------------------------------------------------------
++ // HW Initialization for 8190 MPT.
++ //-------------------------------------------------------------------------
++ //-------------------------------------------------------------------------
++ // SW Initialization for 8190 MP.
++ //-------------------------------------------------------------------------
++ pMptCtx->bMptDrvUnload = _FALSE;
++ pMptCtx->bMassProdTest = _FALSE;
++ pMptCtx->bMptIndexEven = _TRUE; //default gain index is -6.0db
++
++ /* Init mpt event. */
++#if 0 // for Windows
++ NdisInitializeEvent( &(pMptCtx->MptWorkItemEvent) );
++ NdisAllocateSpinLock( &(pMptCtx->MptWorkItemSpinLock) );
++
++ PlatformInitializeWorkItem(
++ Adapter,
++ &(pMptCtx->MptWorkItem),
++ (RT_WORKITEM_CALL_BACK)MPT_WorkItemCallback,
++ (PVOID)Adapter,
++ "MptWorkItem");
++#endif
++ pMptCtx->bMptWorkItemInProgress = _FALSE;
++ pMptCtx->CurrMptAct = NULL;
++ //-------------------------------------------------------------------------
++
++#if 1
++ // Don't accept any packets
++ rtw_write32(pAdapter, REG_RCR, 0);
++#else
++ // Accept CRC error and destination address
++ pHalData->ReceiveConfig |= (RCR_ACRC32|RCR_AAP);
++ rtw_write32(pAdapter, REG_RCR, pHalData->ReceiveConfig);
++#endif
++
++#if 0
++ // If EEPROM or EFUSE is empty,we assign as RF 2T2R for MP.
++ if (pHalData->AutoloadFailFlag == TRUE)
++ {
++ pHalData->RF_Type = RF_2T2R;
++ }
++#endif
++ ledsetting = rtw_read32(pAdapter, REG_LEDCFG0);
++ rtw_write32(pAdapter, REG_LEDCFG0, ledsetting & ~LED0DIS);
++
++#ifdef CONFIG_RTL8192C
++ PHY_IQCalibrate(pAdapter, _FALSE);
++ dm_CheckTXPowerTracking(pAdapter); //trigger thermal meter
++ PHY_LCCalibrate(pAdapter);
++#endif
++
++#ifdef CONFIG_RTL8192D
++ PHY_IQCalibrate(pAdapter);
++ dm_CheckTXPowerTracking(pAdapter); //trigger thermal meter
++ PHY_LCCalibrate(pAdapter);
++#endif
++
++#ifdef CONFIG_PCI_HCI
++ PHY_SetRFPathSwitch(pAdapter, 1/*pHalData->bDefaultAntenna*/); //Wifi default use Main
++#else
++
++#ifdef CONFIG_RTL8192C
++#if 1
++ if (pHalData->BoardType == BOARD_MINICARD)
++ PHY_SetRFPathSwitch(pAdapter, 1/*pHalData->bDefaultAntenna*/); //default use Main
++#else
++ if(pAdapter->HalFunc.GetInterfaceSelectionHandler(pAdapter) == INTF_SEL2_MINICARD )
++ PHY_SetRFPathSwitch(Adapter, pAdapter->MgntInfo.bDefaultAntenna); //default use Main
++#endif
++
++#endif
++
++#endif
++
++ pMptCtx->backup0xc50 = (u1Byte)PHY_QueryBBReg(pAdapter, rOFDM0_XAAGCCore1, bMaskByte0);
++ pMptCtx->backup0xc58 = (u1Byte)PHY_QueryBBReg(pAdapter, rOFDM0_XBAGCCore1, bMaskByte0);
++ pMptCtx->backup0xc30 = (u1Byte)PHY_QueryBBReg(pAdapter, rOFDM0_RxDetector1, bMaskByte0);
++
++ return rtStatus;
++}
++
++/*-----------------------------------------------------------------------------
++ * Function: MPT_DeInitAdapter()
++ *
++ * Overview: Extra DeInitialization for Mass Production Test.
++ *
++ * Input: PADAPTER pAdapter
++ *
++ * Output: NONE
++ *
++ * Return: NONE
++ *
++ * Revised History:
++ * When Who Remark
++ * 05/08/2007 MHC Create Version 0.
++ * 05/18/2007 MHC Add normal driver MPHalt code.
++ *
++ *---------------------------------------------------------------------------*/
++VOID
++MPT_DeInitAdapter(
++ IN PADAPTER pAdapter
++ )
++{
++ PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.MptCtx;
++
++ pMptCtx->bMptDrvUnload = _TRUE;
++#if 0 // for Windows
++ PlatformFreeWorkItem( &(pMptCtx->MptWorkItem) );
++
++ while(pMptCtx->bMptWorkItemInProgress)
++ {
++ if(NdisWaitEvent(&(pMptCtx->MptWorkItemEvent), 50))
++ {
++ break;
++ }
++ }
++ NdisFreeSpinLock( &(pMptCtx->MptWorkItemSpinLock) );
++#endif
++}
++
++static u8 mpt_ProStartTest(PADAPTER padapter)
++{
++ PMPT_CONTEXT pMptCtx = &padapter->mppriv.MptCtx;
++
++ pMptCtx->bMassProdTest = _TRUE;
++ pMptCtx->bStartContTx = _FALSE;
++ pMptCtx->bCckContTx = _FALSE;
++ pMptCtx->bOfdmContTx = _FALSE;
++ pMptCtx->bSingleCarrier = _FALSE;
++ pMptCtx->bCarrierSuppression = _FALSE;
++ pMptCtx->bSingleTone = _FALSE;
++
++ return _SUCCESS;
++}
++
++/*
++ * General use
++ */
++s32 SetPowerTracking(PADAPTER padapter, u8 enable)
++{
++
++ Hal_SetPowerTracking( padapter, enable );
++ return 0;
++}
++
++void GetPowerTracking(PADAPTER padapter, u8 *enable)
++{
++ Hal_GetPowerTracking( padapter, enable );
++}
++
++static void disable_dm(PADAPTER padapter)
++{
++#ifndef CONFIG_RTL8723A
++ u8 v8;
++#endif
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++ struct dm_priv *pdmpriv = &pHalData->dmpriv;
++
++
++ //3 1. disable firmware dynamic mechanism
++ // disable Power Training, Rate Adaptive
++#ifdef CONFIG_RTL8723A
++ SetBcnCtrlReg(padapter, 0, EN_BCN_FUNCTION);
++#else
++ v8 = rtw_read8(padapter, REG_BCN_CTRL);
++ v8 &= ~EN_BCN_FUNCTION;
++ rtw_write8(padapter, REG_BCN_CTRL, v8);
++#endif
++
++ //3 2. disable driver dynamic mechanism
++ // disable Dynamic Initial Gain
++ // disable High Power
++ // disable Power Tracking
++ Switch_DM_Func(padapter, DYNAMIC_FUNC_DISABLE, _FALSE);
++
++ // enable APK, LCK and IQK but disable power tracking
++ pdmpriv->TxPowerTrackControl = _FALSE;
++ Switch_DM_Func(padapter, DYNAMIC_FUNC_SS, _TRUE);
++}
++
++//This function initializes the DUT to the MP test mode
++s32 mp_start_test(PADAPTER padapter)
++{
++ WLAN_BSSID_EX bssid;
++ struct sta_info *psta;
++ u32 length;
++ u8 val8;
++
++ _irqL irqL;
++ s32 res = _SUCCESS;
++
++ struct mp_priv *pmppriv = &padapter->mppriv;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct wlan_network *tgt_network = &pmlmepriv->cur_network;
++
++
++ //3 disable dynamic mechanism
++ disable_dm(padapter);
++
++ //3 0. update mp_priv
++#if defined (CONFIG_RTL8192C) || defined (CONFIG_RTL8192D)
++ if (padapter->registrypriv.rf_config == RF_819X_MAX_TYPE) {
++// HAL_DATA_TYPE *phal = GET_HAL_DATA(padapter);
++// switch (phal->rf_type) {
++ switch (GET_RF_TYPE(padapter)) {
++ case RF_1T1R:
++ pmppriv->antenna_tx = ANTENNA_A;
++ pmppriv->antenna_rx = ANTENNA_A;
++ break;
++ case RF_1T2R:
++ default:
++ pmppriv->antenna_tx = ANTENNA_A;
++ pmppriv->antenna_rx = ANTENNA_AB;
++ break;
++ case RF_2T2R:
++ case RF_2T2R_GREEN:
++ pmppriv->antenna_tx = ANTENNA_AB;
++ pmppriv->antenna_rx = ANTENNA_AB;
++ break;
++ case RF_2T4R:
++ pmppriv->antenna_tx = ANTENNA_AB;
++ pmppriv->antenna_rx = ANTENNA_ABCD;
++ break;
++ }
++ }
++#endif
++ mpt_ProStartTest(padapter);
++
++ //3 1. initialize a new WLAN_BSSID_EX
++// _rtw_memset(&bssid, 0, sizeof(WLAN_BSSID_EX));
++ _rtw_memcpy(bssid.MacAddress, pmppriv->network_macaddr, ETH_ALEN);
++ bssid.Ssid.SsidLength = strlen("mp_pseudo_adhoc");
++ _rtw_memcpy(bssid.Ssid.Ssid, (u8*)"mp_pseudo_adhoc", bssid.Ssid.SsidLength);
++ bssid.InfrastructureMode = Ndis802_11IBSS;
++ bssid.NetworkTypeInUse = Ndis802_11DS;
++ bssid.IELength = 0;
++
++ length = get_WLAN_BSSID_EX_sz(&bssid);
++ if (length % 4)
++ bssid.Length = ((length >> 2) + 1) << 2; //round up to multiple of 4 bytes.
++ else
++ bssid.Length = length;
++
++ _enter_critical_bh(&pmlmepriv->lock, &irqL);
++
++ if (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE)
++ goto end_of_mp_start_test;
++
++ //init mp_start_test status
++ if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) {
++ rtw_disassoc_cmd(padapter, 500, _TRUE);
++ rtw_indicate_disconnect(padapter);
++ rtw_free_assoc_resources(padapter, 1);
++ }
++ pmppriv->prev_fw_state = get_fwstate(pmlmepriv);
++ pmlmepriv->fw_state = WIFI_MP_STATE;
++#if 0
++ if (pmppriv->mode == _LOOPBOOK_MODE_) {
++ set_fwstate(pmlmepriv, WIFI_MP_LPBK_STATE); //append txdesc
++ RT_TRACE(_module_mp_, _drv_notice_, ("+start mp in Lookback mode\n"));
++ } else {
++ RT_TRACE(_module_mp_, _drv_notice_, ("+start mp in normal mode\n"));
++ }
++#endif
++ set_fwstate(pmlmepriv, _FW_UNDER_LINKING);
++
++ //3 2. create a new psta for mp driver
++ //clear psta in the cur_network, if any
++ psta = rtw_get_stainfo(&padapter->stapriv, tgt_network->network.MacAddress);
++ if (psta) rtw_free_stainfo(padapter, psta);
++
++ psta = rtw_alloc_stainfo(&padapter->stapriv, bssid.MacAddress);
++ if (psta == NULL) {
++ RT_TRACE(_module_mp_, _drv_err_, ("mp_start_test: Can't alloc sta_info!\n"));
++ pmlmepriv->fw_state = pmppriv->prev_fw_state;
++ res = _FAIL;
++ goto end_of_mp_start_test;
++ }
++
++ //3 3. join psudo AdHoc
++ tgt_network->join_res = 1;
++ tgt_network->aid = psta->aid = 1;
++ _rtw_memcpy(&tgt_network->network, &bssid, length);
++
++ rtw_indicate_connect(padapter);
++ _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING);
++
++end_of_mp_start_test:
++
++ _exit_critical_bh(&pmlmepriv->lock, &irqL);
++
++ if (res == _SUCCESS)
++ {
++ // set MSR to WIFI_FW_ADHOC_STATE
++#if defined (CONFIG_RTL8192C) || defined (CONFIG_RTL8192D)
++ val8 = rtw_read8(padapter, MSR) & 0xFC; // 0x0102
++ val8 |= WIFI_FW_ADHOC_STATE;
++ rtw_write8(padapter, MSR, val8); // Link in ad hoc network
++#endif
++
++#if !defined (CONFIG_RTL8192C) && !defined (CONFIG_RTL8192D)
++ rtw_write8(padapter, MSR, 1); // Link in ad hoc network
++ rtw_write8(padapter, RCR, 0); // RCR : disable all pkt, 0x10250048
++ rtw_write8(padapter, RCR+2, 0x57); // RCR disable Check BSSID, 0x1025004a
++
++ // disable RX filter map , mgt frames will put in RX FIFO 0
++ rtw_write16(padapter, RXFLTMAP0, 0x0); // 0x10250116
++
++ val8 = rtw_read8(padapter, EE_9346CR); // 0x1025000A
++ if (!(val8 & _9356SEL))//boot from EFUSE
++ efuse_change_max_size(padapter);
++#endif
++ }
++
++ return res;
++}
++//------------------------------------------------------------------------------
++//This function change the DUT from the MP test mode into normal mode
++void mp_stop_test(PADAPTER padapter)
++{
++ struct mp_priv *pmppriv = &padapter->mppriv;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct wlan_network *tgt_network = &pmlmepriv->cur_network;
++ struct sta_info *psta;
++
++ _irqL irqL;
++
++
++ _enter_critical_bh(&pmlmepriv->lock, &irqL);
++
++ if (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _FALSE)
++ goto end_of_mp_stop_test;
++
++ //3 1. disconnect psudo AdHoc
++ rtw_indicate_disconnect(padapter);
++
++ //3 2. clear psta used in mp test mode.
++// rtw_free_assoc_resources(padapter, 1);
++ psta = rtw_get_stainfo(&padapter->stapriv, tgt_network->network.MacAddress);
++ if (psta) rtw_free_stainfo(padapter, psta);
++
++ //3 3. return to normal state (default:station mode)
++ pmlmepriv->fw_state = pmppriv->prev_fw_state; // WIFI_STATION_STATE;
++
++ //flush the cur_network
++ _rtw_memset(tgt_network, 0, sizeof(struct wlan_network));
++
++ _clr_fwstate_(pmlmepriv, WIFI_MP_STATE);
++
++end_of_mp_stop_test:
++
++ _exit_critical_bh(&pmlmepriv->lock, &irqL);
++}
++/*---------------------------hal\rtl8192c\MPT_Phy.c---------------------------*/
++#if 0
++//#ifdef CONFIG_USB_HCI
++static VOID mpt_AdjustRFRegByRateByChan92CU(PADAPTER pAdapter, u8 RateIdx, u8 Channel, u8 BandWidthID)
++{
++ u8 eRFPath;
++ u32 rfReg0x26;
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
++
++
++ if (RateIdx < MPT_RATE_6M) { // CCK rate,for 88cu
++ rfReg0x26 = 0xf400;
++ }
++ else if ((RateIdx >= MPT_RATE_6M) && (RateIdx <= MPT_RATE_54M)) {// OFDM rate,for 88cu
++ if ((4 == Channel) || (8 == Channel) || (12 == Channel))
++ rfReg0x26 = 0xf000;
++ else if ((5 == Channel) || (7 == Channel) || (13 == Channel) || (14 == Channel))
++ rfReg0x26 = 0xf400;
++ else
++ rfReg0x26 = 0x4f200;
++ }
++ else if ((RateIdx >= MPT_RATE_MCS0) && (RateIdx <= MPT_RATE_MCS15)) {// MCS 20M ,for 88cu // MCS40M rate,for 88cu
++
++ if (HT_CHANNEL_WIDTH_20 == BandWidthID) {
++ if ((4 == Channel) || (8 == Channel))
++ rfReg0x26 = 0xf000;
++ else if ((5 == Channel) || (7 == Channel) || (13 == Channel) || (14 == Channel))
++ rfReg0x26 = 0xf400;
++ else
++ rfReg0x26 = 0x4f200;
++ }
++ else{
++ if ((4 == Channel) || (8 == Channel))
++ rfReg0x26 = 0xf000;
++ else if ((5 == Channel) || (7 == Channel))
++ rfReg0x26 = 0xf400;
++ else
++ rfReg0x26 = 0x4f200;
++ }
++ }
++
++// RT_TRACE(COMP_CMD, DBG_LOUD, ("\n mpt_AdjustRFRegByRateByChan92CU():Chan:%d Rate=%d rfReg0x26:0x%08x\n",Channel, RateIdx,rfReg0x26));
++ for (eRFPath = 0; eRFPath < pHalData->NumTotalRFPath; eRFPath++) {
++ write_rfreg(pAdapter, eRFPath, RF_SYN_G2, rfReg0x26);
++ }
++}
++#endif
++/*-----------------------------------------------------------------------------
++ * Function: mpt_SwitchRfSetting
++ *
++ * Overview: Change RF Setting when we siwthc channel/rate/BW for MP.
++ *
++ * Input: IN PADAPTER pAdapter
++ *
++ * Output: NONE
++ *
++ * Return: NONE
++ *
++ * Revised History:
++ * When Who Remark
++ * 01/08/2009 MHC Suggestion from SD3 Willis for 92S series.
++ * 01/09/2009 MHC Add CCK modification for 40MHZ. Suggestion from SD3.
++ *
++ *---------------------------------------------------------------------------*/
++static void mpt_SwitchRfSetting(PADAPTER pAdapter)
++{
++ Hal_mpt_SwitchRfSetting(pAdapter);
++ }
++
++/*---------------------------hal\rtl8192c\MPT_Phy.c---------------------------*/
++/*---------------------------hal\rtl8192c\MPT_HelperFunc.c---------------------------*/
++static void MPT_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14)
++{
++ Hal_MPT_CCKTxPowerAdjust(Adapter,bInCH14);
++}
++
++static void MPT_CCKTxPowerAdjustbyIndex(PADAPTER pAdapter, BOOLEAN beven)
++{
++ Hal_MPT_CCKTxPowerAdjustbyIndex(pAdapter,beven);
++ }
++
++/*---------------------------hal\rtl8192c\MPT_HelperFunc.c---------------------------*/
++
++/*
++ * SetChannel
++ * Description
++ * Use H2C command to change channel,
++ * not only modify rf register, but also other setting need to be done.
++ */
++void SetChannel(PADAPTER pAdapter)
++{
++ Hal_SetChannel(pAdapter);
++
++}
++
++/*
++ * Notice
++ * Switch bandwitdth may change center frequency(channel)
++ */
++void SetBandwidth(PADAPTER pAdapter)
++{
++ Hal_SetBandwidth(pAdapter);
++
++}
++
++static void SetCCKTxPower(PADAPTER pAdapter, u8 *TxPower)
++{
++ Hal_SetCCKTxPower(pAdapter,TxPower);
++}
++
++static void SetOFDMTxPower(PADAPTER pAdapter, u8 *TxPower)
++{
++ Hal_SetOFDMTxPower(pAdapter,TxPower);
++ }
++
++
++void SetAntenna(PADAPTER pAdapter)
++ {
++ Hal_SetAntenna(pAdapter);
++}
++
++void SetAntennaPathPower(PADAPTER pAdapter)
++{
++ Hal_SetAntennaPathPower(pAdapter);
++}
++
++void SetTxPower(PADAPTER pAdapter)
++{
++ Hal_SetTxPower(pAdapter);
++ }
++
++void SetTxAGCOffset(PADAPTER pAdapter, u32 ulTxAGCOffset)
++{
++ u32 TxAGCOffset_B, TxAGCOffset_C, TxAGCOffset_D,tmpAGC;
++
++ TxAGCOffset_B = (ulTxAGCOffset&0x000000ff);
++ TxAGCOffset_C = ((ulTxAGCOffset&0x0000ff00)>>8);
++ TxAGCOffset_D = ((ulTxAGCOffset&0x00ff0000)>>16);
++
++ tmpAGC = (TxAGCOffset_D<<8 | TxAGCOffset_C<<4 | TxAGCOffset_B);
++ write_bbreg(pAdapter, rFPGA0_TxGainStage,
++ (bXBTxAGC|bXCTxAGC|bXDTxAGC), tmpAGC);
++}
++
++void SetDataRate(PADAPTER pAdapter)
++{
++ Hal_SetDataRate(pAdapter);
++}
++
++#if !defined (CONFIG_RTL8192C) && !defined (CONFIG_RTL8192D)
++/*------------------------------Define structure----------------------------*/
++typedef struct _R_ANTENNA_SELECT_OFDM {
++ u32 r_tx_antenna:4;
++ u32 r_ant_l:4;
++ u32 r_ant_non_ht:4;
++ u32 r_ant_ht1:4;
++ u32 r_ant_ht2:4;
++ u32 r_ant_ht_s1:4;
++ u32 r_ant_non_ht_s1:4;
++ u32 OFDM_TXSC:2;
++ u32 Reserved:2;
++}R_ANTENNA_SELECT_OFDM;
++
++typedef struct _R_ANTENNA_SELECT_CCK {
++ u8 r_cckrx_enable_2:2;
++ u8 r_cckrx_enable:2;
++ u8 r_ccktx_enable:4;
++}R_ANTENNA_SELECT_CCK;
++#endif
++
++s32 SetThermalMeter(PADAPTER pAdapter, u8 target_ther)
++{
++ return Hal_SetThermalMeter( pAdapter, target_ther);
++}
++
++static void TriggerRFThermalMeter(PADAPTER pAdapter)
++{
++ Hal_TriggerRFThermalMeter(pAdapter);
++}
++
++static u8 ReadRFThermalMeter(PADAPTER pAdapter)
++{
++ return Hal_ReadRFThermalMeter(pAdapter);
++}
++
++void GetThermalMeter(PADAPTER pAdapter, u8 *value)
++{
++ Hal_GetThermalMeter(pAdapter,value);
++}
++
++void SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart)
++{
++ Hal_SetSingleCarrierTx(pAdapter,bStart);
++}
++
++void SetSingleToneTx(PADAPTER pAdapter, u8 bStart)
++{
++ Hal_SetSingleToneTx(pAdapter,bStart);
++}
++
++void SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart)
++{
++ Hal_SetCarrierSuppressionTx(pAdapter, bStart);
++}
++
++void SetCCKContinuousTx(PADAPTER pAdapter, u8 bStart)
++ {
++ Hal_SetCCKContinuousTx(pAdapter,bStart);
++ }
++
++void SetOFDMContinuousTx(PADAPTER pAdapter, u8 bStart)
++ {
++ Hal_SetOFDMContinuousTx( pAdapter, bStart);
++}/* mpt_StartOfdmContTx */
++
++void SetContinuousTx(PADAPTER pAdapter, u8 bStart)
++{
++ Hal_SetContinuousTx(pAdapter,bStart);
++}
++
++//------------------------------------------------------------------------------
++static void dump_mpframe(PADAPTER padapter, struct xmit_frame *pmpframe)
++{
++ rtw_hal_mgnt_xmit(padapter, pmpframe);
++}
++
++static struct xmit_frame *alloc_mp_xmitframe(struct xmit_priv *pxmitpriv)
++{
++ struct xmit_frame *pmpframe;
++ struct xmit_buf *pxmitbuf;
++
++ if ((pmpframe = rtw_alloc_xmitframe(pxmitpriv)) == NULL)
++ {
++ return NULL;
++ }
++
++ if ((pxmitbuf = rtw_alloc_xmitbuf(pxmitpriv)) == NULL)
++ {
++ rtw_free_xmitframe(pxmitpriv, pmpframe);
++ return NULL;
++ }
++
++ pmpframe->frame_tag = MP_FRAMETAG;
++
++ pmpframe->pxmitbuf = pxmitbuf;
++
++ pmpframe->buf_addr = pxmitbuf->pbuf;
++
++ pxmitbuf->priv_data = pmpframe;
++
++ return pmpframe;
++
++}
++
++static thread_return mp_xmit_packet_thread(thread_context context)
++{
++ struct xmit_frame *pxmitframe;
++ struct mp_tx *pmptx;
++ struct mp_priv *pmp_priv;
++ struct xmit_priv *pxmitpriv;
++ PADAPTER padapter;
++
++ pmp_priv = (struct mp_priv *)context;
++ pmptx = &pmp_priv->tx;
++ padapter = pmp_priv->papdater;
++ pxmitpriv = &(padapter->xmitpriv);
++
++ thread_enter("RTW_MP_THREAD");
++
++ DBG_871X("%s:pkTx Start\n", __func__);
++ while (1) {
++ pxmitframe = alloc_mp_xmitframe(pxmitpriv);
++ if (pxmitframe == NULL) {
++ if (pmptx->stop ||
++ padapter->bSurpriseRemoved ||
++ padapter->bDriverStopped) {
++ goto exit;
++ }
++ else {
++ rtw_msleep_os(1);
++ continue;
++ }
++ }
++
++ _rtw_memcpy((u8 *)(pxmitframe->buf_addr+TXDESC_OFFSET), pmptx->buf, pmptx->write_size);
++ _rtw_memcpy(&(pxmitframe->attrib), &(pmptx->attrib), sizeof(struct pkt_attrib));
++
++ dump_mpframe(padapter, pxmitframe);
++
++ pmptx->sended++;
++ pmp_priv->tx_pktcount++;
++
++ if (pmptx->stop ||
++ padapter->bSurpriseRemoved ||
++ padapter->bDriverStopped)
++ goto exit;
++ if ((pmptx->count != 0) &&
++ (pmptx->count == pmptx->sended))
++ goto exit;
++
++ flush_signals_thread();
++ }
++
++exit:
++ //DBG_871X("%s:pkTx Exit\n", __func__);
++ rtw_mfree(pmptx->pallocated_buf, pmptx->buf_size);
++ pmptx->pallocated_buf = NULL;
++ pmptx->stop = 1;
++
++ thread_exit();
++}
++
++void fill_txdesc_for_mp(PADAPTER padapter, struct tx_desc *ptxdesc)
++{
++ struct mp_priv *pmp_priv = &padapter->mppriv;
++ _rtw_memcpy(ptxdesc, &(pmp_priv->tx.desc), TXDESC_SIZE);
++}
++
++void SetPacketTx(PADAPTER padapter)
++{
++ u8 *ptr, *pkt_start, *pkt_end;
++ u32 pkt_size;
++ struct tx_desc *desc;
++ struct rtw_ieee80211_hdr *hdr;
++ u8 payload;
++ s32 bmcast;
++ struct pkt_attrib *pattrib;
++ struct mp_priv *pmp_priv;
++
++
++ pmp_priv = &padapter->mppriv;
++ if (pmp_priv->tx.stop) return;
++ pmp_priv->tx.sended = 0;
++ pmp_priv->tx.stop = 0;
++ pmp_priv->tx_pktcount = 0;
++
++ //3 1. update_attrib()
++ pattrib = &pmp_priv->tx.attrib;
++ _rtw_memcpy(pattrib->src, padapter->eeprompriv.mac_addr, ETH_ALEN);
++ _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
++ _rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN);
++ bmcast = IS_MCAST(pattrib->ra);
++ if (bmcast) {
++ pattrib->mac_id = 1;
++ pattrib->psta = rtw_get_bcmc_stainfo(padapter);
++ } else {
++ pattrib->mac_id = 0;
++ pattrib->psta = rtw_get_stainfo(&padapter->stapriv, get_bssid(&padapter->mlmepriv));
++ }
++
++ pattrib->last_txcmdsz = pattrib->hdrlen + pattrib->pktlen;
++
++ //3 2. allocate xmit buffer
++ pkt_size = pattrib->last_txcmdsz;
++
++ if (pmp_priv->tx.pallocated_buf)
++ rtw_mfree(pmp_priv->tx.pallocated_buf, pmp_priv->tx.buf_size);
++ pmp_priv->tx.write_size = pkt_size;
++ pmp_priv->tx.buf_size = pkt_size + XMITBUF_ALIGN_SZ;
++ pmp_priv->tx.pallocated_buf = rtw_zmalloc(pmp_priv->tx.buf_size);
++ if (pmp_priv->tx.pallocated_buf == NULL) {
++ DBG_871X("%s: malloc(%d) fail!!\n", __func__, pmp_priv->tx.buf_size);
++ return;
++ }
++ pmp_priv->tx.buf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pmp_priv->tx.pallocated_buf), XMITBUF_ALIGN_SZ);
++ ptr = pmp_priv->tx.buf;
++
++ desc = &(pmp_priv->tx.desc);
++ _rtw_memset(desc, 0, TXDESC_SIZE);
++ pkt_start = ptr;
++ pkt_end = pkt_start + pkt_size;
++
++ //3 3. init TX descriptor
++ // offset 0
++ //desc->txdw0 |= cpu_to_le32(pkt_size & 0x0000FFFF); // packet size
++ //desc->txdw0 |= cpu_to_le32(OWN | FSG | LSG);
++ //desc->txdw0 |= cpu_to_le32(((TXDESC_SIZE + OFFSET_SZ) << OFFSET_SHT) & 0x00FF0000); //32 bytes for TX Desc
++ //if (bmcast) desc->txdw0 |= cpu_to_le32(BMC); // broadcast packet
++
++ // offset 4
++ desc->txdw1 |= cpu_to_le32(BK); // don't aggregate(AMPDU)
++ desc->txdw1 |= cpu_to_le32((pattrib->mac_id) & 0x1F); //CAM_ID(MAC_ID)
++ desc->txdw1 |= cpu_to_le32((pattrib->qsel << QSEL_SHT) & 0x00001F00); // Queue Select, TID
++ desc->txdw1 |= cpu_to_le32((pattrib->raid << Rate_ID_SHT) & 0x000F0000); // Rate Adaptive ID
++
++ // offset 8
++ // offset 12
++ //desc->txdw3 |= cpu_to_le32((pattrib->seqnum << SEQ_SHT) & 0xffff0000);
++
++ // offset 16
++ //desc->txdw4 |= cpu_to_le32(QoS);
++ desc->txdw4 |= cpu_to_le32(HW_SEQ_EN);
++ desc->txdw4 |= cpu_to_le32(USERATE);
++ desc->txdw4 |= cpu_to_le32(DISDATAFB);
++
++ if( pmp_priv->preamble ){
++ if (pmp_priv->rateidx <= MPT_RATE_54M)
++ desc->txdw4 |= cpu_to_le32(DATA_SHORT); // CCK Short Preamble
++ }
++ if (pmp_priv->bandwidth == HT_CHANNEL_WIDTH_40)
++ desc->txdw4 |= cpu_to_le32(DATA_BW);
++
++ // offset 20
++ desc->txdw5 |= cpu_to_le32(pmp_priv->rateidx & 0x0000001F);
++
++ if( pmp_priv->preamble ){
++ if (pmp_priv->rateidx > MPT_RATE_54M)
++ desc->txdw5 |= cpu_to_le32(SGI); // MCS Short Guard Interval
++ }
++ desc->txdw5 |= cpu_to_le32(0x0001FF00); // DATA/RTS Rate Fallback Limit
++
++ //3 4. make wlan header, make_wlanhdr()
++ hdr = (struct rtw_ieee80211_hdr *)pkt_start;
++ SetFrameSubType(&hdr->frame_ctl, pattrib->subtype);
++ _rtw_memcpy(hdr->addr1, pattrib->dst, ETH_ALEN); // DA
++ _rtw_memcpy(hdr->addr2, pattrib->src, ETH_ALEN); // SA
++ _rtw_memcpy(hdr->addr3, get_bssid(&padapter->mlmepriv), ETH_ALEN); // RA, BSSID
++
++ //3 5. make payload
++ ptr = pkt_start + pattrib->hdrlen;
++
++ switch (pmp_priv->tx.payload) {
++ case 0:
++ payload = 0x00;
++ break;
++ case 1:
++ payload = 0x5a;
++ break;
++ case 2:
++ payload = 0xa5;
++ break;
++ case 3:
++ payload = 0xff;
++ break;
++ default:
++ payload = 0x00;
++ break;
++ }
++
++ _rtw_memset(ptr, payload, pkt_end - ptr);
++
++ //3 6. start thread
++#ifdef PLATFORM_LINUX
++ pmp_priv->tx.PktTxThread = kthread_run(mp_xmit_packet_thread, pmp_priv, "RTW_MP_THREAD");
++ if (IS_ERR(pmp_priv->tx.PktTxThread))
++ DBG_871X("Create PktTx Thread Fail !!!!!\n");
++#endif
++#ifdef PLATFORM_FREEBSD
++{
++ struct proc *p;
++ struct thread *td;
++ pmp_priv->tx.PktTxThread = kproc_kthread_add(mp_xmit_packet_thread, pmp_priv,
++ &p, &td, RFHIGHPID, 0, "MPXmitThread", "MPXmitThread");
++
++ if (pmp_priv->tx.PktTxThread < 0)
++ DBG_871X("Create PktTx Thread Fail !!!!!\n");
++}
++#endif
++}
++
++void SetPacketRx(PADAPTER pAdapter, u8 bStartRx)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
++
++ if(bStartRx)
++ {
++ pHalData->ReceiveConfig = AAP | APM | AM | AB | APP_ICV | ADF | AMF | HTC_LOC_CTRL | APP_MIC | APP_PHYSTS;
++
++ pHalData->ReceiveConfig |= ACRC32;
++
++ rtw_write32(pAdapter, REG_RCR, pHalData->ReceiveConfig);
++
++ // Accept all data frames
++ rtw_write16(pAdapter, REG_RXFLTMAP2, 0xFFFF);
++ }
++ else
++ {
++ rtw_write32(pAdapter, REG_RCR, 0);
++ }
++}
++
++void ResetPhyRxPktCount(PADAPTER pAdapter)
++{
++ u32 i, phyrx_set = 0;
++
++ for (i = 0; i <= 0xF; i++) {
++ phyrx_set = 0;
++ phyrx_set |= _RXERR_RPT_SEL(i); //select
++ phyrx_set |= RXERR_RPT_RST; // set counter to zero
++ rtw_write32(pAdapter, REG_RXERR_RPT, phyrx_set);
++ }
++}
++
++static u32 GetPhyRxPktCounts(PADAPTER pAdapter, u32 selbit)
++{
++ //selection
++ u32 phyrx_set = 0, count = 0;
++
++ phyrx_set = _RXERR_RPT_SEL(selbit & 0xF);
++ rtw_write32(pAdapter, REG_RXERR_RPT, phyrx_set);
++
++ //Read packet count
++ count = rtw_read32(pAdapter, REG_RXERR_RPT) & RXERR_COUNTER_MASK;
++
++ return count;
++}
++
++u32 GetPhyRxPktReceived(PADAPTER pAdapter)
++{
++ u32 OFDM_cnt = 0, CCK_cnt = 0, HT_cnt = 0;
++
++ OFDM_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_OFDM_MPDU_OK);
++ CCK_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_CCK_MPDU_OK);
++ HT_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_HT_MPDU_OK);
++
++ return OFDM_cnt + CCK_cnt + HT_cnt;
++}
++
++u32 GetPhyRxPktCRC32Error(PADAPTER pAdapter)
++{
++ u32 OFDM_cnt = 0, CCK_cnt = 0, HT_cnt = 0;
++
++ OFDM_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_OFDM_MPDU_FAIL);
++ CCK_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_CCK_MPDU_FAIL);
++ HT_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_HT_MPDU_FAIL);
++
++ return OFDM_cnt + CCK_cnt + HT_cnt;
++}
++
++//reg 0x808[9:0]: FFT data x
++//reg 0x808[22]: 0 --> 1 to get 1 FFT data y
++//reg 0x8B4[15:0]: FFT data y report
++static u32 GetPSDData(PADAPTER pAdapter, u32 point)
++{
++ int psd_val;
++
++
++ psd_val = rtw_read32(pAdapter, 0x808);
++ psd_val &= 0xFFBFFC00;
++ psd_val |= point;
++
++ rtw_write32(pAdapter, 0x808, psd_val);
++ rtw_mdelay_os(1);
++ psd_val |= 0x00400000;
++
++ rtw_write32(pAdapter, 0x808, psd_val);
++ rtw_mdelay_os(1);
++ psd_val = rtw_read32(pAdapter, 0x8B4);
++
++ psd_val &= 0x0000FFFF;
++
++ return psd_val;
++}
++
++/*
++ * pts start_point_min stop_point_max
++ * 128 64 64 + 128 = 192
++ * 256 128 128 + 256 = 384
++ * 512 256 256 + 512 = 768
++ * 1024 512 512 + 1024 = 1536
++ *
++ */
++u32 mp_query_psd(PADAPTER pAdapter, u8 *data)
++{
++ u32 i, psd_pts=0, psd_start=0, psd_stop=0;
++ u32 psd_data=0;
++
++#ifdef PLATFORM_LINUX
++ if (!netif_running(pAdapter->pnetdev)) {
++ RT_TRACE(_module_mp_, _drv_warning_, ("mp_query_psd: Fail! interface not opened!\n"));
++ return 0;
++ }
++#endif
++
++ if (check_fwstate(&pAdapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {
++ RT_TRACE(_module_mp_, _drv_warning_, ("mp_query_psd: Fail! not in MP mode!\n"));
++ return 0;
++ }
++
++ if (strlen(data) == 0) { //default value
++ psd_pts = 128;
++ psd_start = 64;
++ psd_stop = 128;
++ } else {
++ sscanf(data, "pts=%d,start=%d,stop=%d", &psd_pts, &psd_start, &psd_stop);
++ }
++
++ _rtw_memset(data, '\0', sizeof(data));
++
++ i = psd_start;
++ while (i < psd_stop)
++ {
++ if (i >= psd_pts) {
++ psd_data = GetPSDData(pAdapter, i-psd_pts);
++ } else {
++ psd_data = GetPSDData(pAdapter, i);
++ }
++ sprintf(data, "%s%x ", data, psd_data);
++ i++;
++ }
++
++ #ifdef CONFIG_LONG_DELAY_ISSUE
++ rtw_msleep_os(100);
++ #else
++ rtw_mdelay_os(100);
++ #endif
++
++ return strlen(data)+1;
++}
++
++#endif
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/core/rtw_mp_ioctl.c linux-xbian-rpi/drivers/net/wireless/rtl8192cu/core/rtw_mp_ioctl.c
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/core/rtw_mp_ioctl.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/core/rtw_mp_ioctl.c 2015-07-28 01:20:58.305654202 +0200
+@@ -0,0 +1,2953 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#define _RTW_MP_IOCTL_C_
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++#include <mlme_osdep.h>
++
++//#include <rtw_mp.h>
++#include <rtw_mp_ioctl.h>
++
++
++//**************** oid_rtl_seg_81_85 section start ****************
++NDIS_STATUS oid_rt_wireless_mode_hdl(struct oid_par_priv *poid_par_priv)
++{
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++_func_enter_;
++
++ if (poid_par_priv->information_buf_len < sizeof(u8))
++ return NDIS_STATUS_INVALID_LENGTH;
++
++ if (poid_par_priv->type_of_oid == SET_OID) {
++ Adapter->registrypriv.wireless_mode = *(u8*)poid_par_priv->information_buf;
++ } else if (poid_par_priv->type_of_oid == QUERY_OID) {
++ *(u8*)poid_par_priv->information_buf = Adapter->registrypriv.wireless_mode;
++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
++ RT_TRACE(_module_mp_, _drv_info_, ("-query Wireless Mode=%d\n", Adapter->registrypriv.wireless_mode));
++ } else {
++ status = NDIS_STATUS_NOT_ACCEPTED;
++ }
++
++_func_exit_;
++
++ return status;
++}
++//**************** oid_rtl_seg_81_87_80 section start ****************
++NDIS_STATUS oid_rt_pro_write_bb_reg_hdl(struct oid_par_priv *poid_par_priv)
++{
++#ifdef PLATFORM_OS_XP
++ _irqL oldirql;
++#endif
++ struct bb_reg_param *pbbreg;
++ u16 offset;
++ u32 value;
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++_func_enter_;
++
++ RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_write_bb_reg_hdl\n"));
++
++ if (poid_par_priv->type_of_oid != SET_OID)
++ return NDIS_STATUS_NOT_ACCEPTED;
++
++ if (poid_par_priv->information_buf_len < sizeof(struct bb_reg_param))
++ return NDIS_STATUS_INVALID_LENGTH;
++
++ pbbreg = (struct bb_reg_param *)(poid_par_priv->information_buf);
++
++ offset = (u16)(pbbreg->offset) & 0xFFF; //0ffset :0x800~0xfff
++ if (offset < BB_REG_BASE_ADDR) offset |= BB_REG_BASE_ADDR;
++
++ value = pbbreg->value;
++
++ RT_TRACE(_module_mp_, _drv_notice_,
++ ("oid_rt_pro_write_bb_reg_hdl: offset=0x%03X value=0x%08X\n",
++ offset, value));
++
++ _irqlevel_changed_(&oldirql, LOWER);
++ write_bbreg(Adapter, offset, 0xFFFFFFFF, value);
++ _irqlevel_changed_(&oldirql, RAISE);
++
++_func_exit_;
++
++ return status;
++}
++//------------------------------------------------------------------------------
++NDIS_STATUS oid_rt_pro_read_bb_reg_hdl(struct oid_par_priv *poid_par_priv)
++{
++#ifdef PLATFORM_OS_XP
++ _irqL oldirql;
++#endif
++ struct bb_reg_param *pbbreg;
++ u16 offset;
++ u32 value;
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++_func_enter_;
++
++ RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_read_bb_reg_hdl\n"));
++
++ if (poid_par_priv->type_of_oid != QUERY_OID)
++ return NDIS_STATUS_NOT_ACCEPTED;
++
++ if (poid_par_priv->information_buf_len < sizeof(struct bb_reg_param))
++ return NDIS_STATUS_INVALID_LENGTH;
++
++ pbbreg = (struct bb_reg_param *)(poid_par_priv->information_buf);
++
++ offset = (u16)(pbbreg->offset) & 0xFFF; //0ffset :0x800~0xfff
++ if (offset < BB_REG_BASE_ADDR) offset |= BB_REG_BASE_ADDR;
++
++ _irqlevel_changed_(&oldirql, LOWER);
++ value = read_bbreg(Adapter, offset, 0xFFFFFFFF);
++ _irqlevel_changed_(&oldirql, RAISE);
++
++ pbbreg->value = value;
++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
++
++ RT_TRACE(_module_mp_, _drv_notice_,
++ ("-oid_rt_pro_read_bb_reg_hdl: offset=0x%03X value:0x%08X\n",
++ offset, value));
++_func_exit_;
++
++ return status;
++}
++//------------------------------------------------------------------------------
++NDIS_STATUS oid_rt_pro_write_rf_reg_hdl(struct oid_par_priv *poid_par_priv)
++{
++#ifdef PLATFORM_OS_XP
++ _irqL oldirql;
++#endif
++ struct rf_reg_param *pbbreg;
++ u8 path;
++ u8 offset;
++ u32 value;
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++_func_enter_;
++
++ RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_write_rf_reg_hdl\n"));
++
++ if (poid_par_priv->type_of_oid != SET_OID)
++ return NDIS_STATUS_NOT_ACCEPTED;
++
++ if (poid_par_priv->information_buf_len < sizeof(struct rf_reg_param))
++ return NDIS_STATUS_INVALID_LENGTH;
++
++ pbbreg = (struct rf_reg_param *)(poid_par_priv->information_buf);
++
++ if (pbbreg->path >= MAX_RF_PATH_NUMS)
++ return NDIS_STATUS_NOT_ACCEPTED;
++ if (pbbreg->offset > 0xFF)
++ return NDIS_STATUS_NOT_ACCEPTED;
++ if (pbbreg->value > 0xFFFFF)
++ return NDIS_STATUS_NOT_ACCEPTED;
++
++ path = (u8)pbbreg->path;
++ offset = (u8)pbbreg->offset;
++ value = pbbreg->value;
++
++ RT_TRACE(_module_mp_, _drv_notice_,
++ ("oid_rt_pro_write_rf_reg_hdl: path=%d offset=0x%02X value=0x%05X\n",
++ path, offset, value));
++
++ _irqlevel_changed_(&oldirql, LOWER);
++ write_rfreg(Adapter, path, offset, value);
++ _irqlevel_changed_(&oldirql, RAISE);
++
++_func_exit_;
++
++ return status;
++}
++//------------------------------------------------------------------------------
++NDIS_STATUS oid_rt_pro_read_rf_reg_hdl(struct oid_par_priv *poid_par_priv)
++{
++#ifdef PLATFORM_OS_XP
++ _irqL oldirql;
++#endif
++ struct rf_reg_param *pbbreg;
++ u8 path;
++ u8 offset;
++ u32 value;
++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++
++_func_enter_;
++
++ RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_read_rf_reg_hdl\n"));
++
++ if (poid_par_priv->type_of_oid != QUERY_OID)
++ return NDIS_STATUS_NOT_ACCEPTED;
++
++ if (poid_par_priv->information_buf_len < sizeof(struct rf_reg_param))
++ return NDIS_STATUS_INVALID_LENGTH;
++
++ pbbreg = (struct rf_reg_param *)(poid_par_priv->information_buf);
++
++ if (pbbreg->path >= MAX_RF_PATH_NUMS)
++ return NDIS_STATUS_NOT_ACCEPTED;
++ if (pbbreg->offset > 0xFF)
++ return NDIS_STATUS_NOT_ACCEPTED;
++
++ path = (u8)pbbreg->path;
++ offset = (u8)pbbreg->offset;
++
++ _irqlevel_changed_(&oldirql, LOWER);
++ value = read_rfreg(Adapter, path, offset);
++ _irqlevel_changed_(&oldirql, RAISE);
++
++ pbbreg->value = value;
++
++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
++
++ RT_TRACE(_module_mp_, _drv_notice_,
++ ("-oid_rt_pro_read_rf_reg_hdl: path=%d offset=0x%02X value=0x%05X\n",
++ path, offset, value));
++
++_func_exit_;
++
++ return status;
++}
++//**************** oid_rtl_seg_81_87_00 section end****************
++//------------------------------------------------------------------------------
++
++//**************** oid_rtl_seg_81_80_00 section start ****************
++//------------------------------------------------------------------------------
++NDIS_STATUS oid_rt_pro_set_data_rate_hdl(struct oid_par_priv *poid_par_priv)
++{
++#ifdef PLATFORM_OS_XP
++ _irqL oldirql;
++#endif
++ u32 ratevalue;//4
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++_func_enter_;
++
++ RT_TRACE(_module_mp_, _drv_notice_,
++ ("+oid_rt_pro_set_data_rate_hdl\n"));
++
++ if (poid_par_priv->type_of_oid != SET_OID)
++ return NDIS_STATUS_NOT_ACCEPTED;
++
++ if (poid_par_priv->information_buf_len != sizeof(u32))
++ return NDIS_STATUS_INVALID_LENGTH;
++
++ ratevalue = *((u32*)poid_par_priv->information_buf);//4
++ RT_TRACE(_module_mp_, _drv_notice_,
++ ("oid_rt_pro_set_data_rate_hdl: data rate idx=%d\n", ratevalue));
++ if (ratevalue >= MPT_RATE_LAST)
++ return NDIS_STATUS_INVALID_DATA;
++
++ Adapter->mppriv.rateidx = ratevalue;
++
++ _irqlevel_changed_(&oldirql, LOWER);
++ SetDataRate(Adapter);
++ _irqlevel_changed_(&oldirql, RAISE);
++
++_func_exit_;
++
++ return status;
++}
++//------------------------------------------------------------------------------
++NDIS_STATUS oid_rt_pro_start_test_hdl(struct oid_par_priv *poid_par_priv)
++{
++#ifdef PLATFORM_OS_XP
++ _irqL oldirql;
++#endif
++ u32 mode;
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++_func_enter_;
++
++ RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_start_test_hdl\n"));
++
++ if (Adapter->registrypriv.mp_mode == 0)
++ return NDIS_STATUS_NOT_ACCEPTED;
++
++ if (poid_par_priv->type_of_oid != SET_OID)
++ return NDIS_STATUS_NOT_ACCEPTED;
++
++ _irqlevel_changed_(&oldirql, LOWER);
++
++ //IQCalibrateBcut(Adapter);
++
++ mode = *((u32*)poid_par_priv->information_buf);
++ Adapter->mppriv.mode = mode;// 1 for loopback
++
++ if (mp_start_test(Adapter) == _FAIL) {
++ status = NDIS_STATUS_NOT_ACCEPTED;
++ goto exit;
++ }
++
++exit:
++ _irqlevel_changed_(&oldirql, RAISE);
++
++ RT_TRACE(_module_mp_, _drv_notice_, ("-oid_rt_pro_start_test_hdl: mp_mode=%d\n", Adapter->mppriv.mode));
++
++_func_exit_;
++
++ return status;
++}
++//------------------------------------------------------------------------------
++NDIS_STATUS oid_rt_pro_stop_test_hdl(struct oid_par_priv *poid_par_priv)
++{
++#ifdef PLATFORM_OS_XP
++ _irqL oldirql;
++#endif
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++_func_enter_;
++
++ RT_TRACE(_module_mp_, _drv_notice_, ("+Set OID_RT_PRO_STOP_TEST\n"));
++
++ if (poid_par_priv->type_of_oid != SET_OID)
++ return NDIS_STATUS_NOT_ACCEPTED;
++
++ _irqlevel_changed_(&oldirql, LOWER);
++ mp_stop_test(Adapter);
++ _irqlevel_changed_(&oldirql, RAISE);
++
++ RT_TRACE(_module_mp_, _drv_notice_, ("-Set OID_RT_PRO_STOP_TEST\n"));
++
++_func_exit_;
++
++ return status;
++}
++//------------------------------------------------------------------------------
++NDIS_STATUS oid_rt_pro_set_channel_direct_call_hdl(struct oid_par_priv *poid_par_priv)
++{
++#ifdef PLATFORM_OS_XP
++ _irqL oldirql;
++#endif
++ u32 Channel;
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++_func_enter_;
++
++ RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_set_channel_direct_call_hdl\n"));
++
++ if (poid_par_priv->information_buf_len != sizeof(u32))
++ return NDIS_STATUS_INVALID_LENGTH;
++
++ if (poid_par_priv->type_of_oid == QUERY_OID) {
++ *((u32*)poid_par_priv->information_buf) = Adapter->mppriv.channel;
++ return NDIS_STATUS_SUCCESS;
++ }
++
++ if (poid_par_priv->type_of_oid != SET_OID)
++ return NDIS_STATUS_NOT_ACCEPTED;
++
++ Channel = *((u32*)poid_par_priv->information_buf);
++ RT_TRACE(_module_mp_, _drv_notice_, ("oid_rt_pro_set_channel_direct_call_hdl: Channel=%d\n", Channel));
++ if (Channel > 14)
++ return NDIS_STATUS_NOT_ACCEPTED;
++ Adapter->mppriv.channel = Channel;
++
++ _irqlevel_changed_(&oldirql, LOWER);
++ SetChannel(Adapter);
++ _irqlevel_changed_(&oldirql, RAISE);
++
++_func_exit_;
++
++ return status;
++}
++//------------------------------------------------------------------------------
++NDIS_STATUS oid_rt_set_bandwidth_hdl(struct oid_par_priv *poid_par_priv)
++{
++#ifdef PLATFORM_OS_XP
++ _irqL oldirql;
++#endif
++ u16 bandwidth;
++ u16 channel_offset;
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++_func_enter_;
++
++ RT_TRACE(_module_mp_, _drv_info_,
++ ("+oid_rt_set_bandwidth_hdl\n"));
++
++ if (poid_par_priv->type_of_oid != SET_OID)
++ return NDIS_STATUS_NOT_ACCEPTED;
++
++ if (poid_par_priv->information_buf_len < sizeof(u32))
++ return NDIS_STATUS_INVALID_LENGTH;
++
++ bandwidth = *((u32*)poid_par_priv->information_buf);//4
++ channel_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++
++ if (bandwidth != HT_CHANNEL_WIDTH_40)
++ bandwidth = HT_CHANNEL_WIDTH_20;
++ padapter->mppriv.bandwidth = (u8)bandwidth;
++ padapter->mppriv.prime_channel_offset = (u8)channel_offset;
++
++ _irqlevel_changed_(&oldirql, LOWER);
++ SetBandwidth(padapter);
++ _irqlevel_changed_(&oldirql, RAISE);
++
++ RT_TRACE(_module_mp_, _drv_notice_,
++ ("-oid_rt_set_bandwidth_hdl: bandwidth=%d channel_offset=%d\n",
++ bandwidth, channel_offset));
++
++_func_exit_;
++
++ return status;
++}
++//------------------------------------------------------------------------------
++NDIS_STATUS oid_rt_pro_set_antenna_bb_hdl(struct oid_par_priv *poid_par_priv)
++{
++#ifdef PLATFORM_OS_XP
++ _irqL oldirql;
++#endif
++ u32 antenna;
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++_func_enter_;
++
++ RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_set_antenna_bb_hdl\n"));
++
++ if (poid_par_priv->information_buf_len != sizeof(u32))
++ return NDIS_STATUS_INVALID_LENGTH;
++
++ if (poid_par_priv->type_of_oid == SET_OID)
++ {
++ antenna = *(u32*)poid_par_priv->information_buf;
++
++ Adapter->mppriv.antenna_tx = (u16)((antenna & 0xFFFF0000) >> 16);
++ Adapter->mppriv.antenna_rx = (u16)(antenna & 0x0000FFFF);
++ RT_TRACE(_module_mp_, _drv_notice_,
++ ("oid_rt_pro_set_antenna_bb_hdl: tx_ant=0x%04x rx_ant=0x%04x\n",
++ Adapter->mppriv.antenna_tx, Adapter->mppriv.antenna_rx));
++
++ _irqlevel_changed_(&oldirql, LOWER);
++ SetAntenna(Adapter);
++ _irqlevel_changed_(&oldirql, RAISE);
++ } else {
++ antenna = (Adapter->mppriv.antenna_tx << 16)|Adapter->mppriv.antenna_rx;
++ *(u32*)poid_par_priv->information_buf = antenna;
++ }
++
++_func_exit_;
++
++ return status;
++}
++
++NDIS_STATUS oid_rt_pro_set_tx_power_control_hdl(struct oid_par_priv *poid_par_priv)
++{
++#ifdef PLATFORM_OS_XP
++ _irqL oldirql;
++#endif
++ u32 tx_pwr_idx;
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++_func_enter_;
++
++ RT_TRACE(_module_mp_, _drv_info_, ("+oid_rt_pro_set_tx_power_control_hdl\n"));
++
++ if (poid_par_priv->type_of_oid != SET_OID)
++ return NDIS_STATUS_NOT_ACCEPTED;
++
++ if (poid_par_priv->information_buf_len != sizeof(u32))
++ return NDIS_STATUS_INVALID_LENGTH;
++
++ tx_pwr_idx = *((u32*)poid_par_priv->information_buf);
++ if (tx_pwr_idx > MAX_TX_PWR_INDEX_N_MODE)
++ return NDIS_STATUS_NOT_ACCEPTED;
++
++ Adapter->mppriv.txpoweridx = (u8)tx_pwr_idx;
++
++ RT_TRACE(_module_mp_, _drv_notice_,
++ ("oid_rt_pro_set_tx_power_control_hdl: idx=0x%2x\n",
++ Adapter->mppriv.txpoweridx));
++
++ _irqlevel_changed_(&oldirql, LOWER);
++ SetTxPower(Adapter);
++ _irqlevel_changed_(&oldirql, RAISE);
++
++_func_exit_;
++
++ return status;
++}
++
++//------------------------------------------------------------------------------
++//**************** oid_rtl_seg_81_80_20 section start ****************
++//------------------------------------------------------------------------------
++NDIS_STATUS oid_rt_pro_query_tx_packet_sent_hdl(struct oid_par_priv *poid_par_priv)
++{
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++_func_enter_;
++
++ if (poid_par_priv->type_of_oid !=QUERY_OID) {
++ status = NDIS_STATUS_NOT_ACCEPTED;
++ return status;
++ }
++
++ if (poid_par_priv->information_buf_len == sizeof(ULONG)) {
++ *(ULONG*)poid_par_priv->information_buf = Adapter->mppriv.tx_pktcount;
++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
++ } else {
++ status = NDIS_STATUS_INVALID_LENGTH;
++ }
++
++_func_exit_;
++
++ return status;
++}
++//------------------------------------------------------------------------------
++NDIS_STATUS oid_rt_pro_query_rx_packet_received_hdl(struct oid_par_priv *poid_par_priv)
++{
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++_func_enter_;
++
++ if (poid_par_priv->type_of_oid != QUERY_OID) {
++ status = NDIS_STATUS_NOT_ACCEPTED;
++ return status;
++ }
++ RT_TRACE(_module_mp_, _drv_alert_, ("===> oid_rt_pro_query_rx_packet_received_hdl.\n"));
++ if (poid_par_priv->information_buf_len == sizeof(ULONG)) {
++ *(ULONG*)poid_par_priv->information_buf = Adapter->mppriv.rx_pktcount;
++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
++ RT_TRACE(_module_mp_, _drv_alert_, ("recv_ok:%d \n",Adapter->mppriv.rx_pktcount));
++ } else {
++ status = NDIS_STATUS_INVALID_LENGTH;
++ }
++
++_func_exit_;
++
++ return status;
++}
++//------------------------------------------------------------------------------
++NDIS_STATUS oid_rt_pro_query_rx_packet_crc32_error_hdl(struct oid_par_priv *poid_par_priv)
++{
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++_func_enter_;
++
++ if (poid_par_priv->type_of_oid != QUERY_OID) {
++ status = NDIS_STATUS_NOT_ACCEPTED;
++ return status;
++ }
++ RT_TRACE(_module_mp_, _drv_alert_, ("===> oid_rt_pro_query_rx_packet_crc32_error_hdl.\n"));
++ if (poid_par_priv->information_buf_len == sizeof(ULONG)) {
++ *(ULONG*)poid_par_priv->information_buf = Adapter->mppriv.rx_crcerrpktcount;
++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
++ RT_TRACE(_module_mp_, _drv_alert_, ("recv_err:%d \n",Adapter->mppriv.rx_crcerrpktcount));
++ } else {
++ status = NDIS_STATUS_INVALID_LENGTH;
++ }
++
++_func_exit_;
++
++ return status;
++}
++//------------------------------------------------------------------------------
++
++NDIS_STATUS oid_rt_pro_reset_tx_packet_sent_hdl(struct oid_par_priv *poid_par_priv)
++{
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++_func_enter_;
++
++ if (poid_par_priv->type_of_oid != SET_OID) {
++ status = NDIS_STATUS_NOT_ACCEPTED;
++ return status;
++ }
++
++ RT_TRACE(_module_mp_, _drv_alert_, ("===> oid_rt_pro_reset_tx_packet_sent_hdl.\n"));
++ Adapter->mppriv.tx_pktcount = 0;
++
++_func_exit_;
++
++ return status;
++}
++//------------------------------------------------------------------------------
++NDIS_STATUS oid_rt_pro_reset_rx_packet_received_hdl(struct oid_par_priv *poid_par_priv)
++{
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++_func_enter_;
++
++ if (poid_par_priv->type_of_oid != SET_OID)
++ {
++ status = NDIS_STATUS_NOT_ACCEPTED;
++ return status;
++ }
++
++ if (poid_par_priv->information_buf_len == sizeof(ULONG)) {
++ Adapter->mppriv.rx_pktcount = 0;
++ Adapter->mppriv.rx_crcerrpktcount = 0;
++ } else {
++ status = NDIS_STATUS_INVALID_LENGTH;
++ }
++
++_func_exit_;
++
++ return status;
++}
++//------------------------------------------------------------------------------
++NDIS_STATUS oid_rt_reset_phy_rx_packet_count_hdl(struct oid_par_priv *poid_par_priv)
++{
++#ifdef PLATFORM_OS_XP
++ _irqL oldirql;
++#endif
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++_func_enter_;
++
++ if (poid_par_priv->type_of_oid != SET_OID) {
++ status = NDIS_STATUS_NOT_ACCEPTED;
++ return status;
++ }
++
++ _irqlevel_changed_(&oldirql, LOWER);
++ ResetPhyRxPktCount(Adapter);
++ _irqlevel_changed_(&oldirql, RAISE);
++
++_func_exit_;
++
++ return status;
++}
++//------------------------------------------------------------------------------
++NDIS_STATUS oid_rt_get_phy_rx_packet_received_hdl(struct oid_par_priv *poid_par_priv)
++{
++#ifdef PLATFORM_OS_XP
++ _irqL oldirql;
++#endif
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++_func_enter_;
++
++ RT_TRACE(_module_mp_, _drv_info_, ("+oid_rt_get_phy_rx_packet_received_hdl\n"));
++
++ if (poid_par_priv->type_of_oid != QUERY_OID)
++ return NDIS_STATUS_NOT_ACCEPTED;
++
++ if (poid_par_priv->information_buf_len != sizeof(ULONG))
++ return NDIS_STATUS_INVALID_LENGTH;
++
++ _irqlevel_changed_(&oldirql, LOWER);
++ *(ULONG*)poid_par_priv->information_buf = GetPhyRxPktReceived(Adapter);
++ _irqlevel_changed_(&oldirql, RAISE);
++
++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
++
++ RT_TRACE(_module_mp_, _drv_notice_, ("-oid_rt_get_phy_rx_packet_received_hdl: recv_ok=%d\n", *(ULONG*)poid_par_priv->information_buf));
++
++_func_exit_;
++
++ return status;
++}
++//------------------------------------------------------------------------------
++NDIS_STATUS oid_rt_get_phy_rx_packet_crc32_error_hdl(struct oid_par_priv *poid_par_priv)
++{
++#ifdef PLATFORM_OS_XP
++ _irqL oldirql;
++#endif
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++_func_enter_;
++
++ RT_TRACE(_module_mp_, _drv_info_, ("+oid_rt_get_phy_rx_packet_crc32_error_hdl\n"));
++
++ if (poid_par_priv->type_of_oid != QUERY_OID)
++ return NDIS_STATUS_NOT_ACCEPTED;
++
++
++ if (poid_par_priv->information_buf_len != sizeof(ULONG))
++ return NDIS_STATUS_INVALID_LENGTH;
++
++ _irqlevel_changed_(&oldirql, LOWER);
++ *(ULONG*)poid_par_priv->information_buf = GetPhyRxPktCRC32Error(Adapter);
++ _irqlevel_changed_(&oldirql, RAISE);
++
++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
++
++ RT_TRACE(_module_mp_, _drv_info_, ("-oid_rt_get_phy_rx_packet_crc32_error_hdl: recv_err=%d\n", *(ULONG*)poid_par_priv->information_buf));
++
++_func_exit_;
++
++ return status;
++}
++//**************** oid_rtl_seg_81_80_20 section end ****************
++NDIS_STATUS oid_rt_pro_set_continuous_tx_hdl(struct oid_par_priv *poid_par_priv)
++{
++#ifdef PLATFORM_OS_XP
++ _irqL oldirql;
++#endif
++ u32 bStartTest;
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++_func_enter_;
++
++ RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_set_continuous_tx_hdl\n"));
++
++ if (poid_par_priv->type_of_oid != SET_OID)
++ return NDIS_STATUS_NOT_ACCEPTED;
++
++ bStartTest = *((u32*)poid_par_priv->information_buf);
++
++ _irqlevel_changed_(&oldirql, LOWER);
++ SetContinuousTx(Adapter,(u8)bStartTest);
++ if (bStartTest) {
++ struct mp_priv *pmp_priv = &Adapter->mppriv;
++ if (pmp_priv->tx.stop == 0) {
++ pmp_priv->tx.stop = 1;
++ DBG_871X("%s: pkt tx is running...\n", __func__);
++ rtw_msleep_os(5);
++ }
++ pmp_priv->tx.stop = 0;
++ pmp_priv->tx.count = 1;
++ SetPacketTx(Adapter);
++ }
++ _irqlevel_changed_(&oldirql, RAISE);
++
++_func_exit_;
++
++ return status;
++}
++
++NDIS_STATUS oid_rt_pro_set_single_carrier_tx_hdl(struct oid_par_priv *poid_par_priv)
++{
++#ifdef PLATFORM_OS_XP
++ _irqL oldirql;
++#endif
++ u32 bStartTest;
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++_func_enter_;
++
++ RT_TRACE(_module_mp_, _drv_alert_, ("+oid_rt_pro_set_single_carrier_tx_hdl\n"));
++
++ if (poid_par_priv->type_of_oid != SET_OID)
++ return NDIS_STATUS_NOT_ACCEPTED;
++
++ bStartTest = *((u32*)poid_par_priv->information_buf);
++
++ _irqlevel_changed_(&oldirql, LOWER);
++ SetSingleCarrierTx(Adapter, (u8)bStartTest);
++ if (bStartTest) {
++ struct mp_priv *pmp_priv = &Adapter->mppriv;
++ if (pmp_priv->tx.stop == 0) {
++ pmp_priv->tx.stop = 1;
++ DBG_871X("%s: pkt tx is running...\n", __func__);
++ rtw_msleep_os(5);
++ }
++ pmp_priv->tx.stop = 0;
++ pmp_priv->tx.count = 1;
++ SetPacketTx(Adapter);
++ }
++ _irqlevel_changed_(&oldirql, RAISE);
++
++_func_exit_;
++
++ return status;
++}
++
++NDIS_STATUS oid_rt_pro_set_carrier_suppression_tx_hdl(struct oid_par_priv *poid_par_priv)
++{
++#ifdef PLATFORM_OS_XP
++ _irqL oldirql;
++#endif
++ u32 bStartTest;
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++_func_enter_;
++
++ RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_set_carrier_suppression_tx_hdl\n"));
++
++ if (poid_par_priv->type_of_oid != SET_OID)
++ return NDIS_STATUS_NOT_ACCEPTED;
++
++ bStartTest = *((u32*)poid_par_priv->information_buf);
++
++ _irqlevel_changed_(&oldirql, LOWER);
++ SetCarrierSuppressionTx(Adapter, (u8)bStartTest);
++ if (bStartTest) {
++ struct mp_priv *pmp_priv = &Adapter->mppriv;
++ if (pmp_priv->tx.stop == 0) {
++ pmp_priv->tx.stop = 1;
++ DBG_871X("%s: pkt tx is running...\n", __func__);
++ rtw_msleep_os(5);
++ }
++ pmp_priv->tx.stop = 0;
++ pmp_priv->tx.count = 1;
++ SetPacketTx(Adapter);
++ }
++ _irqlevel_changed_(&oldirql, RAISE);
++
++_func_exit_;
++
++ return status;
++}
++
++NDIS_STATUS oid_rt_pro_set_single_tone_tx_hdl(struct oid_par_priv *poid_par_priv)
++{
++#ifdef PLATFORM_OS_XP
++ _irqL oldirql;
++#endif
++ u32 bStartTest;
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++_func_enter_;
++
++ RT_TRACE(_module_mp_, _drv_alert_, ("+oid_rt_pro_set_single_tone_tx_hdl\n"));
++
++ if (poid_par_priv->type_of_oid != SET_OID)
++ return NDIS_STATUS_NOT_ACCEPTED;
++
++ bStartTest = *((u32*)poid_par_priv->information_buf);
++
++ _irqlevel_changed_(&oldirql, LOWER);
++ SetSingleToneTx(Adapter,(u8)bStartTest);
++ _irqlevel_changed_(&oldirql, RAISE);
++
++_func_exit_;
++
++ return status;
++}
++
++NDIS_STATUS oid_rt_pro_set_modulation_hdl(struct oid_par_priv* poid_par_priv)
++{
++ return 0;
++}
++
++NDIS_STATUS oid_rt_pro_trigger_gpio_hdl(struct oid_par_priv *poid_par_priv)
++{
++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++#ifdef PLATFORM_OS_XP
++ _irqL oldirql;
++#endif
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++_func_enter_;
++
++ if (poid_par_priv->type_of_oid != SET_OID)
++ return NDIS_STATUS_NOT_ACCEPTED;
++
++ _irqlevel_changed_(&oldirql, LOWER);
++ rtw_hal_set_hwreg(Adapter, HW_VAR_TRIGGER_GPIO_0, 0);
++ _irqlevel_changed_(&oldirql, RAISE);
++
++_func_exit_;
++
++ return status;
++}
++//**************** oid_rtl_seg_81_80_00 section end ****************
++//------------------------------------------------------------------------------
++NDIS_STATUS oid_rt_pro8711_join_bss_hdl(struct oid_par_priv *poid_par_priv)
++{
++#if 0
++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++#ifdef PLATFORM_OS_XP
++ _irqL oldirql;
++#endif
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++
++ PNDIS_802_11_SSID pssid;
++
++_func_enter_;
++
++ if (poid_par_priv->type_of_oid != SET_OID)
++ return NDIS_STATUS_NOT_ACCEPTED;
++
++ *poid_par_priv->bytes_needed = (u32)sizeof(NDIS_802_11_SSID);
++ *poid_par_priv->bytes_rw = 0;
++ if (poid_par_priv->information_buf_len < *poid_par_priv->bytes_needed)
++ return NDIS_STATUS_INVALID_LENGTH;
++
++ pssid = (PNDIS_802_11_SSID)poid_par_priv->information_buf;
++
++ _irqlevel_changed_(&oldirql, LOWER);
++
++ if (mp_start_joinbss(Adapter, pssid) == _FAIL)
++ status = NDIS_STATUS_NOT_ACCEPTED;
++
++ _irqlevel_changed_(&oldirql, RAISE);
++
++ *poid_par_priv->bytes_rw = sizeof(NDIS_802_11_SSID);
++
++_func_exit_;
++
++ return status;
++#else
++ return 0;
++#endif
++}
++//------------------------------------------------------------------------------
++NDIS_STATUS oid_rt_pro_read_register_hdl(struct oid_par_priv *poid_par_priv)
++{
++#ifdef PLATFORM_OS_XP
++ _irqL oldirql;
++#endif
++ pRW_Reg RegRWStruct;
++ u32 offset, width;
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++_func_enter_;
++
++ RT_TRACE(_module_mp_, _drv_info_,
++ ("+oid_rt_pro_read_register_hdl\n"));
++
++ if (poid_par_priv->type_of_oid != QUERY_OID)
++ return NDIS_STATUS_NOT_ACCEPTED;
++
++ RegRWStruct = (pRW_Reg)poid_par_priv->information_buf;
++ offset = RegRWStruct->offset;
++ width = RegRWStruct->width;
++
++ if (offset > 0xFFF)
++ return NDIS_STATUS_NOT_ACCEPTED;
++
++ _irqlevel_changed_(&oldirql, LOWER);
++
++ switch (width) {
++ case 1:
++ RegRWStruct->value = rtw_read8(Adapter, offset);
++ break;
++ case 2:
++ RegRWStruct->value = rtw_read16(Adapter, offset);
++ break;
++ default:
++ width = 4;
++ RegRWStruct->value = rtw_read32(Adapter, offset);
++ break;
++ }
++ RT_TRACE(_module_mp_, _drv_notice_,
++ ("oid_rt_pro_read_register_hdl: offset:0x%04X value:0x%X\n",
++ offset, RegRWStruct->value));
++
++ _irqlevel_changed_(&oldirql, RAISE);
++
++ *poid_par_priv->bytes_rw = width;
++
++_func_exit_;
++
++ return status;
++}
++//------------------------------------------------------------------------------
++NDIS_STATUS oid_rt_pro_write_register_hdl(struct oid_par_priv *poid_par_priv)
++{
++#ifdef PLATFORM_OS_XP
++ _irqL oldirql;
++#endif
++ pRW_Reg RegRWStruct;
++ u32 offset, width, value;
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++_func_enter_;
++
++ RT_TRACE(_module_mp_, _drv_info_,
++ ("+oid_rt_pro_write_register_hdl\n"));
++
++ if (poid_par_priv->type_of_oid != SET_OID)
++ return NDIS_STATUS_NOT_ACCEPTED;
++
++ RegRWStruct = (pRW_Reg)poid_par_priv->information_buf;
++ offset = RegRWStruct->offset;
++ width = RegRWStruct->width;
++ value = RegRWStruct->value;
++
++ if (offset > 0xFFF)
++ return NDIS_STATUS_NOT_ACCEPTED;
++
++ _irqlevel_changed_(&oldirql, LOWER);
++
++ switch (RegRWStruct->width)
++ {
++ case 1:
++ if (value > 0xFF) {
++ status = NDIS_STATUS_NOT_ACCEPTED;
++ break;
++ }
++ rtw_write8(padapter, offset, (u8)value);
++ break;
++ case 2:
++ if (value > 0xFFFF) {
++ status = NDIS_STATUS_NOT_ACCEPTED;
++ break;
++ }
++ rtw_write16(padapter, offset, (u16)value);
++ break;
++ case 4:
++ rtw_write32(padapter, offset, value);
++ break;
++ default:
++ status = NDIS_STATUS_NOT_ACCEPTED;
++ break;
++ }
++
++ _irqlevel_changed_(&oldirql, RAISE);
++
++ RT_TRACE(_module_mp_, _drv_info_,
++ ("-oid_rt_pro_write_register_hdl: offset=0x%08X width=%d value=0x%X\n",
++ offset, width, value));
++
++_func_exit_;
++
++ return status;
++}
++//------------------------------------------------------------------------------
++NDIS_STATUS oid_rt_pro_burst_read_register_hdl(struct oid_par_priv *poid_par_priv)
++{
++#if 0
++#ifdef PLATFORM_OS_XP
++ _irqL oldirql;
++#endif
++ pBurst_RW_Reg pBstRwReg;
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++_func_enter_;
++
++ RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_burst_read_register_hdl\n"));
++
++ if (poid_par_priv->type_of_oid != QUERY_OID)
++ return NDIS_STATUS_NOT_ACCEPTED;
++
++ pBstRwReg = (pBurst_RW_Reg)poid_par_priv->information_buf;
++
++ _irqlevel_changed_(&oldirql, LOWER);
++ rtw_read_mem(padapter, pBstRwReg->offset, (u32)pBstRwReg->len, pBstRwReg->Data);
++ _irqlevel_changed_(&oldirql, RAISE);
++
++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
++
++ RT_TRACE(_module_mp_, _drv_info_, ("-oid_rt_pro_burst_read_register_hdl\n"));
++
++_func_exit_;
++
++ return status;
++#else
++ return 0;
++#endif
++}
++//------------------------------------------------------------------------------
++NDIS_STATUS oid_rt_pro_burst_write_register_hdl(struct oid_par_priv *poid_par_priv)
++{
++#if 0
++#ifdef PLATFORM_OS_XP
++ _irqL oldirql;
++#endif
++ pBurst_RW_Reg pBstRwReg;
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++_func_enter_;
++
++ RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_burst_write_register_hdl\n"));
++
++ if (poid_par_priv->type_of_oid != SET_OID)
++ return NDIS_STATUS_NOT_ACCEPTED;
++
++ pBstRwReg = (pBurst_RW_Reg)poid_par_priv->information_buf;
++
++ _irqlevel_changed_(&oldirql, LOWER);
++ rtw_write_mem(padapter, pBstRwReg->offset, (u32)pBstRwReg->len, pBstRwReg->Data);
++ _irqlevel_changed_(&oldirql, RAISE);
++
++ RT_TRACE(_module_mp_, _drv_info_, ("-oid_rt_pro_burst_write_register_hdl\n"));
++
++_func_exit_;
++
++ return status;
++#else
++ return 0;
++#endif
++}
++//------------------------------------------------------------------------------
++NDIS_STATUS oid_rt_pro_write_txcmd_hdl(struct oid_par_priv *poid_par_priv)
++{
++#if 0
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++
++ PADAPTER Adapter = (PADAPTER)( poid_par_priv->adapter_context);
++
++#ifdef PLATFORM_OS_XP
++ _irqL oldirql;
++#endif
++
++ TX_CMD_Desc *TxCmd_Info;
++
++_func_enter_;
++
++ if (poid_par_priv->type_of_oid != SET_OID)
++ return NDIS_STATUS_NOT_ACCEPTED;
++
++ RT_TRACE(_module_mp_, _drv_info_, ("+Set OID_RT_PRO_WRITE_TXCMD\n"));
++
++ TxCmd_Info=(TX_CMD_Desc*)poid_par_priv->information_buf;
++
++ RT_TRACE(_module_mp_, _drv_info_, ("WRITE_TXCMD:Addr=%.8X\n", TxCmd_Info->offset));
++ RT_TRACE(_module_mp_, _drv_info_, ("WRITE_TXCMD:1.)%.8X\n", (ULONG)TxCmd_Info->TxCMD.value[0]));
++ RT_TRACE(_module_mp_, _drv_info_, ("WRITE_TXCMD:2.)%.8X\n", (ULONG)TxCmd_Info->TxCMD.value[1]));
++ RT_TRACE(_module_mp_, _drv_info_, (("WRITE_TXCMD:3.)%.8X\n", (ULONG)TxCmd_Info->TxCMD.value[2]));
++ RT_TRACE(_module_mp_, _drv_info_, ("WRITE_TXCMD:4.)%.8X\n", (ULONG)TxCmd_Info->TxCMD.value[3]));
++
++ _irqlevel_changed_(&oldirql, LOWER);
++
++ rtw_write32(Adapter, TxCmd_Info->offset + 0, (unsigned int)TxCmd_Info->TxCMD.value[0]);
++ rtw_write32(Adapter, TxCmd_Info->offset + 4, (unsigned int)TxCmd_Info->TxCMD.value[1]);
++
++ _irqlevel_changed_(&oldirql, RAISE);
++
++ RT_TRACE(_module_mp_, _drv_notice_,
++ ("-Set OID_RT_PRO_WRITE_TXCMD: status=0x%08X\n", status));
++
++_func_exit_;
++
++ return status;
++#else
++ return 0;
++#endif
++}
++
++//------------------------------------------------------------------------------
++NDIS_STATUS oid_rt_pro_read16_eeprom_hdl(struct oid_par_priv *poid_par_priv)
++{
++#if 0
++#ifdef PLATFORM_OS_XP
++ _irqL oldirql;
++#endif
++ pEEPROM_RWParam pEEPROM;
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++_func_enter_;
++
++ RT_TRACE(_module_mp_, _drv_info_, ("+Query OID_RT_PRO_READ16_EEPROM\n"));
++
++ if (poid_par_priv->type_of_oid != QUERY_OID)
++ return NDIS_STATUS_NOT_ACCEPTED;
++
++ pEEPROM = (pEEPROM_RWParam)poid_par_priv->information_buf;
++
++ _irqlevel_changed_(&oldirql, LOWER);
++ pEEPROM->value = eeprom_read16(padapter, (u16)(pEEPROM->offset >> 1));
++ _irqlevel_changed_(&oldirql, RAISE);
++
++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
++
++ RT_TRACE(_module_mp_, _drv_notice_,
++ ("-Query OID_RT_PRO_READ16_EEPROM: offset=0x%x value=0x%x\n",
++ pEEPROM->offset, pEEPROM->value));
++
++_func_exit_;
++
++ return status;
++#else
++ return 0;
++#endif
++}
++
++//------------------------------------------------------------------------------
++NDIS_STATUS oid_rt_pro_write16_eeprom_hdl (struct oid_par_priv *poid_par_priv)
++{
++#if 0
++#ifdef PLATFORM_OS_XP
++ _irqL oldirql;
++#endif
++ pEEPROM_RWParam pEEPROM;
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++_func_enter_;
++
++ RT_TRACE(_module_mp_, _drv_notice_, ("+Set OID_RT_PRO_WRITE16_EEPROM\n"));
++
++ if (poid_par_priv->type_of_oid != SET_OID)
++ return NDIS_STATUS_NOT_ACCEPTED;
++
++ pEEPROM = (pEEPROM_RWParam)poid_par_priv->information_buf;
++
++ _irqlevel_changed_(&oldirql, LOWER);
++ eeprom_write16(padapter, (u16)(pEEPROM->offset >> 1), pEEPROM->value);
++ _irqlevel_changed_(&oldirql, RAISE);
++
++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
++
++_func_exit_;
++
++ return status;
++#else
++ return 0;
++#endif
++}
++//------------------------------------------------------------------------------
++NDIS_STATUS oid_rt_pro8711_wi_poll_hdl(struct oid_par_priv *poid_par_priv)
++{
++#if 0
++ PADAPTER Adapter = (PADAPTER)( poid_par_priv->adapter_context);
++
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++
++ struct mp_wiparam *pwi_param;
++
++_func_enter_;
++
++ if (poid_par_priv->type_of_oid != QUERY_OID)
++ return NDIS_STATUS_NOT_ACCEPTED;
++
++ if (poid_par_priv->information_buf_len < sizeof(struct mp_wiparam))
++ return NDIS_STATUS_INVALID_LENGTH;
++
++ if (Adapter->mppriv.workparam.bcompleted == _FALSE)
++ return NDIS_STATUS_NOT_ACCEPTED;
++
++ pwi_param = (struct mp_wiparam *)poid_par_priv->information_buf;
++
++ _rtw_memcpy(pwi_param, &Adapter->mppriv.workparam, sizeof(struct mp_wiparam));
++ Adapter->mppriv.act_in_progress = _FALSE;
++// RT_TRACE(_module_mp_, _drv_info_, ("rf:%x\n", pwiparam->IoValue));
++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
++
++_func_exit_;
++
++ return status;
++#else
++ return 0;
++#endif
++}
++//------------------------------------------------------------------------------
++NDIS_STATUS oid_rt_pro8711_pkt_loss_hdl(struct oid_par_priv *poid_par_priv)
++{
++#if 0
++ PADAPTER Adapter = (PADAPTER)( poid_par_priv->adapter_context);
++
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++
++_func_enter_;
++
++ RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro8711_pkt_loss_hdl\n"));
++
++ if (poid_par_priv->type_of_oid != QUERY_OID)
++ return NDIS_STATUS_NOT_ACCEPTED;
++
++ if (poid_par_priv->information_buf_len < sizeof(uint)*2) {
++ RT_TRACE(_module_mp_, _drv_err_, ("-oid_rt_pro8711_pkt_loss_hdl: buf_len=%d\n", (int)poid_par_priv->information_buf_len));
++ return NDIS_STATUS_INVALID_LENGTH;
++ }
++
++ if (*(uint*)poid_par_priv->information_buf == 1)//init==1
++ Adapter->mppriv.rx_pktloss = 0;
++
++ *((uint*)poid_par_priv->information_buf+1) = Adapter->mppriv.rx_pktloss;
++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
++
++_func_exit_;
++
++ return status;
++#else
++ return 0;
++#endif
++}
++//------------------------------------------------------------------------------
++NDIS_STATUS oid_rt_rd_attrib_mem_hdl(struct oid_par_priv *poid_par_priv)
++{
++#if 0
++ PADAPTER Adapter = (PADAPTER)( poid_par_priv->adapter_context);
++ struct io_queue *pio_queue = (struct io_queue *)Adapter->pio_queue;
++ struct intf_hdl *pintfhdl = &pio_queue->intf;
++
++#ifdef PLATFORM_OS_XP
++ _irqL oldirql;
++#endif
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++
++#ifdef CONFIG_SDIO_HCI
++ void (*_attrib_read)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
++#endif
++
++_func_enter_;
++
++ RT_TRACE(_module_mp_, _drv_notice_, ("+Query OID_RT_RD_ATTRIB_MEM\n"));
++
++ if (poid_par_priv->type_of_oid != QUERY_OID)
++ return NDIS_STATUS_NOT_ACCEPTED;
++
++#ifdef CONFIG_SDIO_HCI
++ _irqlevel_changed_(&oldirql, LOWER);
++{
++ u32 *plmem = (u32*)poid_par_priv->information_buf+2;
++ _attrib_read = pintfhdl->io_ops._attrib_read;
++ _attrib_read(pintfhdl, *((u32*)poid_par_priv->information_buf),
++ *((u32*)poid_par_priv->information_buf+1), (u8*)plmem);
++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
++}
++ _irqlevel_changed_(&oldirql, RAISE);
++#endif
++
++_func_exit_;
++
++ return status;
++#else
++ return 0;
++#endif
++}
++//------------------------------------------------------------------------------
++NDIS_STATUS oid_rt_wr_attrib_mem_hdl (struct oid_par_priv *poid_par_priv)
++{
++#if 0
++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
++ struct io_queue *pio_queue = (struct io_queue *)Adapter->pio_queue;
++ struct intf_hdl *pintfhdl = &pio_queue->intf;
++
++#ifdef PLATFORM_OS_XP
++ _irqL oldirql;
++#endif
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++
++#ifdef CONFIG_SDIO_HCI
++ void (*_attrib_write)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
++#endif
++
++_func_enter_;
++
++ if (poid_par_priv->type_of_oid != SET_OID)
++ return NDIS_STATUS_NOT_ACCEPTED;
++
++#ifdef CONFIG_SDIO_HCI
++ _irqlevel_changed_(&oldirql, LOWER);
++{
++ u32 *plmem = (u32*)poid_par_priv->information_buf + 2;
++ _attrib_write = pintfhdl->io_ops._attrib_write;
++ _attrib_write(pintfhdl, *(u32*)poid_par_priv->information_buf,
++ *((u32*)poid_par_priv->information_buf+1), (u8*)plmem);
++}
++ _irqlevel_changed_(&oldirql, RAISE);
++#endif
++
++_func_exit_;
++
++ return status;
++#else
++ return 0;
++#endif
++}
++//------------------------------------------------------------------------------
++NDIS_STATUS oid_rt_pro_set_rf_intfs_hdl(struct oid_par_priv *poid_par_priv)
++{
++#if 0
++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++#ifdef PLATFORM_OS_XP
++ _irqL oldirql;
++#endif
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++
++_func_enter_;
++
++ RT_TRACE(_module_mp_, _drv_notice_, ("+OID_RT_PRO_SET_RF_INTFS\n"));
++
++ if (poid_par_priv->type_of_oid != SET_OID)
++ return NDIS_STATUS_NOT_ACCEPTED;
++
++ _irqlevel_changed_(&oldirql, LOWER);
++
++ if (rtw_setrfintfs_cmd(Adapter, *(unsigned char*)poid_par_priv->information_buf) == _FAIL)
++ status = NDIS_STATUS_NOT_ACCEPTED;
++
++ _irqlevel_changed_(&oldirql, RAISE);
++
++_func_exit_;
++
++ return status;
++#else
++ return 0;
++#endif
++}
++//------------------------------------------------------------------------------
++NDIS_STATUS oid_rt_poll_rx_status_hdl(struct oid_par_priv *poid_par_priv)
++{
++#if 0
++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++
++_func_enter_;
++
++ if (poid_par_priv->type_of_oid != QUERY_OID)
++ return NDIS_STATUS_NOT_ACCEPTED;
++
++ _rtw_memcpy(poid_par_priv->information_buf, (unsigned char*)&Adapter->mppriv.rxstat, sizeof(struct recv_stat));
++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
++
++_func_exit_;
++
++ return status;
++#else
++ return 0;
++#endif
++}
++//------------------------------------------------------------------------------
++NDIS_STATUS oid_rt_pro_cfg_debug_message_hdl(struct oid_par_priv *poid_par_priv)
++{
++#if 0
++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++
++ PCFG_DBG_MSG_STRUCT pdbg_msg;
++
++_func_enter_;
++
++// RT_TRACE(0xffffffffff,_drv_alert_,("===> oid_rt_pro_cfg_debug_message_hdl.\n"));
++
++#if 0//#ifdef CONFIG_DEBUG_RTL871X
++
++ pdbg_msg = (PCFG_DBG_MSG_STRUCT)(poid_par_priv->information_buf);
++
++ if (poid_par_priv->type_of_oid == SET_OID) {
++ RT_TRACE(0xffffffffff, _drv_alert_,
++ ("===>Set level :0x%08x, H32:0x%08x L32:0x%08x\n",
++ pdbg_msg->DebugLevel, pdbg_msg->DebugComponent_H32, pdbg_msg->DebugComponent_L32));
++
++ GlobalDebugLevel = pdbg_msg->DebugLevel;
++ GlobalDebugComponents = (pdbg_msg->DebugComponent_H32 << 32) | pdbg_msg->DebugComponent_L32;
++ RT_TRACE(0xffffffffff, _drv_alert_,
++ ("===> Set level :0x%08x, component:0x%016x\n",
++ GlobalDebugLevel, (u32)GlobalDebugComponents));
++ } else {
++ pdbg_msg->DebugLevel = GlobalDebugLevel;
++ pdbg_msg->DebugComponent_H32 = (u32)(GlobalDebugComponents >> 32);
++ pdbg_msg->DebugComponent_L32 = (u32)GlobalDebugComponents;
++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
++
++ RT_TRACE(0xffffffffff, _drv_alert_,
++ ("===>Query level:0x%08x H32:0x%08x L32:0x%08x\n",
++ (u32)pdbg_msg->DebugLevel, (u32)pdbg_msg->DebugComponent_H32, (u32)pdbg_msg->DebugComponent_L32));
++ }
++
++#endif
++
++_func_exit_;
++
++ return status;
++#else
++ return 0;
++#endif
++}
++//------------------------------------------------------------------------------
++NDIS_STATUS oid_rt_pro_set_data_rate_ex_hdl(struct oid_par_priv *poid_par_priv)
++{
++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++#ifdef PLATFORM_OS_XP
++ _irqL oldirql;
++#endif
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++
++_func_enter_;
++
++ RT_TRACE(_module_mp_, _drv_notice_, ("+OID_RT_PRO_SET_DATA_RATE_EX\n"));
++
++ if (poid_par_priv->type_of_oid != SET_OID)
++ return NDIS_STATUS_NOT_ACCEPTED;
++
++ _irqlevel_changed_(&oldirql, LOWER);
++
++ if (rtw_setdatarate_cmd(Adapter, poid_par_priv->information_buf) !=_SUCCESS)
++ status = NDIS_STATUS_NOT_ACCEPTED;
++
++ _irqlevel_changed_(&oldirql, RAISE);
++
++_func_exit_;
++
++ return status;
++}
++//-----------------------------------------------------------------------------
++NDIS_STATUS oid_rt_get_thermal_meter_hdl(struct oid_par_priv *poid_par_priv)
++{
++#ifdef PLATFORM_OS_XP
++ _irqL oldirql;
++#endif
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ u8 thermal = 0;
++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++_func_enter_;
++
++ RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_get_thermal_meter_hdl\n"));
++
++ if (poid_par_priv->type_of_oid != QUERY_OID)
++ return NDIS_STATUS_NOT_ACCEPTED;
++
++ if (poid_par_priv->information_buf_len < sizeof(u32))
++ return NDIS_STATUS_INVALID_LENGTH;
++
++ _irqlevel_changed_(&oldirql, LOWER);
++ GetThermalMeter(Adapter, &thermal);
++ _irqlevel_changed_(&oldirql, RAISE);
++
++ *(u32*)poid_par_priv->information_buf = (u32)thermal;
++ *poid_par_priv->bytes_rw = sizeof(u32);
++
++_func_exit_;
++
++ return status;
++}
++//-----------------------------------------------------------------------------
++NDIS_STATUS oid_rt_pro_read_tssi_hdl(struct oid_par_priv *poid_par_priv)
++{
++#if 0
++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++#ifdef PLATFORM_OS_XP
++ _irqL oldirql;
++#endif
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++
++_func_enter_;
++
++ RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_read_tssi_hdl\n"));
++
++ if (poid_par_priv->type_of_oid != SET_OID)
++ return NDIS_STATUS_NOT_ACCEPTED;
++
++ if (Adapter->mppriv.act_in_progress == _TRUE)
++ return NDIS_STATUS_NOT_ACCEPTED;
++
++ if (poid_par_priv->information_buf_len < sizeof(u8))
++ return NDIS_STATUS_INVALID_LENGTH;
++
++ //init workparam
++ Adapter->mppriv.act_in_progress = _TRUE;
++ Adapter->mppriv.workparam.bcompleted = _FALSE;
++ Adapter->mppriv.workparam.act_type = MPT_READ_TSSI;
++ Adapter->mppriv.workparam.io_offset = 0;
++ Adapter->mppriv.workparam.io_value = 0xFFFFFFFF;
++
++ _irqlevel_changed_(&oldirql, LOWER);
++
++ if (!rtw_gettssi_cmd(Adapter,0, (u8*)&Adapter->mppriv.workparam.io_value))
++ status = NDIS_STATUS_NOT_ACCEPTED;
++
++ _irqlevel_changed_(&oldirql, RAISE);
++
++_func_exit_;
++
++ return status;
++#else
++ return 0;
++#endif
++}
++//------------------------------------------------------------------------------
++NDIS_STATUS oid_rt_pro_set_power_tracking_hdl(struct oid_par_priv *poid_par_priv)
++{
++#ifdef PLATFORM_OS_XP
++ _irqL oldirql;
++#endif
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++
++_func_enter_;
++
++// if (poid_par_priv->type_of_oid != SET_OID)
++// return NDIS_STATUS_NOT_ACCEPTED;
++
++ if (poid_par_priv->information_buf_len < sizeof(u8))
++ return NDIS_STATUS_INVALID_LENGTH;
++
++ _irqlevel_changed_(&oldirql, LOWER);
++ if (poid_par_priv->type_of_oid == SET_OID) {
++ u8 enable;
++
++ enable = *(u8*)poid_par_priv->information_buf;
++ RT_TRACE(_module_mp_, _drv_notice_,
++ ("+oid_rt_pro_set_power_tracking_hdl: enable=%d\n", enable));
++
++ SetPowerTracking(Adapter, enable);
++ } else {
++ GetPowerTracking(Adapter, (u8*)poid_par_priv->information_buf);
++ }
++ _irqlevel_changed_(&oldirql, RAISE);
++
++_func_exit_;
++
++ return status;
++}
++//-----------------------------------------------------------------------------
++NDIS_STATUS oid_rt_pro_set_basic_rate_hdl(struct oid_par_priv *poid_par_priv)
++{
++#if 0
++#ifdef PLATFORM_OS_XP
++ _irqL oldirql;
++#endif
++ u32 ratevalue;
++ u8 datarates[NumRates];
++ int i;
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++_func_enter_;
++
++ RT_TRACE(_module_mp_, _drv_info_, ("+OID_RT_PRO_SET_BASIC_RATE\n"));
++
++ if (poid_par_priv->type_of_oid != SET_OID)
++ return NDIS_STATUS_NOT_ACCEPTED;
++#if 0
++ ratevalue = *((u32*)poid_par_priv->information_buf);
++
++ for (i = 0; i < NumRates; i++) {
++ if (ratevalue == mpdatarate[i])
++ datarates[i] = mpdatarate[i];
++ else
++ datarates[i] = 0xff;
++ RT_TRACE(_module_rtl871x_ioctl_c_, _drv_info_, ("basicrate_inx=%d\n", datarates[i]));
++ }
++
++ _irqlevel_changed_(&oldirql, LOWER);
++
++ if (rtw_setbasicrate_cmd(padapter, datarates) != _SUCCESS)
++ status = NDIS_STATUS_NOT_ACCEPTED;
++
++ _irqlevel_changed_(&oldirql, RAISE);
++#endif
++ RT_TRACE(_module_mp_, _drv_notice_,
++ ("-OID_RT_PRO_SET_BASIC_RATE: status=0x%08X\n", status));
++
++_func_exit_;
++
++ return status;
++#else
++ return 0;
++#endif
++}
++//------------------------------------------------------------------------------
++NDIS_STATUS oid_rt_pro_qry_pwrstate_hdl(struct oid_par_priv *poid_par_priv)
++{
++#if 0
++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++
++_func_enter_;
++
++ if (poid_par_priv->type_of_oid != QUERY_OID)
++ return NDIS_STATUS_NOT_ACCEPTED;
++
++ if (poid_par_priv->information_buf_len < 8)
++ return NDIS_STATUS_INVALID_LENGTH;
++
++ *poid_par_priv->bytes_rw = 8;
++ _rtw_memcpy(poid_par_priv->information_buf, &(Adapter->pwrctrlpriv.pwr_mode), 8);
++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
++
++ RT_TRACE(_module_mp_, _drv_notice_,
++ ("-oid_rt_pro_qry_pwrstate_hdl: pwr_mode=%d smart_ps=%d\n",
++ Adapter->pwrctrlpriv.pwr_mode, Adapter->pwrctrlpriv.smart_ps));
++
++_func_exit_;
++
++ return status;
++#else
++ return 0;
++#endif
++}
++//------------------------------------------------------------------------------
++NDIS_STATUS oid_rt_pro_set_pwrstate_hdl(struct oid_par_priv *poid_par_priv)
++{
++#if 0
++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++
++ uint pwr_mode, smart_ps;
++
++_func_enter_;
++
++ RT_TRACE(_module_mp_, _drv_notice_, ("+Set OID_RT_PRO_SET_PWRSTATE\n"));
++
++ if (poid_par_priv->type_of_oid != SET_OID)
++ return NDIS_STATUS_NOT_ACCEPTED;
++
++ *poid_par_priv->bytes_rw = 0;
++ *poid_par_priv->bytes_needed = 8;
++
++ if (poid_par_priv->information_buf_len < 8)
++ return NDIS_STATUS_INVALID_LENGTH;
++
++ pwr_mode = *(uint *)(poid_par_priv->information_buf);
++ smart_ps = *(uint *)((int)poid_par_priv->information_buf + 4);
++
++ *poid_par_priv->bytes_rw = 8;
++
++_func_exit_;
++
++ return status;
++#else
++ return 0;
++#endif
++}
++//------------------------------------------------------------------------------
++NDIS_STATUS oid_rt_pro_h2c_set_rate_table_hdl(struct oid_par_priv *poid_par_priv)
++{
++#if 0
++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++#ifdef PLATFORM_OS_XP
++ _irqL oldirql;
++#endif
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++
++ struct setratable_parm *prate_table;
++ u8 res;
++
++_func_enter_;
++
++ if (poid_par_priv->type_of_oid != SET_OID)
++ return NDIS_STATUS_NOT_ACCEPTED;
++
++ *poid_par_priv->bytes_needed = sizeof(struct setratable_parm);
++ if (poid_par_priv->information_buf_len < sizeof(struct setratable_parm))
++ return NDIS_STATUS_INVALID_LENGTH;
++
++ prate_table = (struct setratable_parm*)poid_par_priv->information_buf;
++
++ _irqlevel_changed_(&oldirql, LOWER);
++ res = rtw_setrttbl_cmd(Adapter, prate_table);
++ _irqlevel_changed_(&oldirql, RAISE);
++
++ if (res == _FAIL)
++ status = NDIS_STATUS_FAILURE;
++
++_func_exit_;
++
++ return status;
++#else
++ return 0;
++#endif
++}
++//------------------------------------------------------------------------------
++NDIS_STATUS oid_rt_pro_h2c_get_rate_table_hdl(struct oid_par_priv *poid_par_priv)
++{
++#if 0
++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++
++_func_enter_;
++
++ if (poid_par_priv->type_of_oid != QUERY_OID)
++ return NDIS_STATUS_NOT_ACCEPTED;
++
++ #if 0
++ struct mp_wi_cntx *pmp_wi_cntx=&(Adapter->mppriv.wi_cntx);
++ u8 res=_SUCCESS;
++ DEBUG_INFO(("===> Set OID_RT_PRO_H2C_GET_RATE_TABLE.\n"));
++
++ if(pmp_wi_cntx->bmp_wi_progress ==_TRUE){
++ DEBUG_ERR(("\n mp workitem is progressing, not allow to set another workitem right now!!!\n"));
++ Status = NDIS_STATUS_NOT_ACCEPTED;
++ break;
++ }
++ else{
++ pmp_wi_cntx->bmp_wi_progress=_TRUE;
++ pmp_wi_cntx->param.bcompleted=_FALSE;
++ pmp_wi_cntx->param.act_type=MPT_GET_RATE_TABLE;
++ pmp_wi_cntx->param.io_offset=0x0;
++ pmp_wi_cntx->param.bytes_cnt=sizeof(struct getratable_rsp);
++ pmp_wi_cntx->param.io_value=0xffffffff;
++
++ res=rtw_getrttbl_cmd(Adapter,(struct getratable_rsp *)pmp_wi_cntx->param.data);
++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
++ if(res != _SUCCESS)
++ {
++ Status = NDIS_STATUS_NOT_ACCEPTED;
++ }
++ }
++ DEBUG_INFO(("\n <=== Set OID_RT_PRO_H2C_GET_RATE_TABLE.\n"));
++ #endif
++
++_func_exit_;
++
++ return status;
++#else
++ return 0;
++#endif
++}
++
++//**************** oid_rtl_seg_87_12_00 section start ****************
++NDIS_STATUS oid_rt_pro_encryption_ctrl_hdl(struct oid_par_priv *poid_par_priv)
++{
++#if 0
++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
++ struct security_priv *psecuritypriv = &Adapter->securitypriv;
++
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++
++ ENCRY_CTRL_STATE encry_mode;
++
++
++ *poid_par_priv->bytes_needed = sizeof(u8);
++ if (poid_par_priv->information_buf_len < *poid_par_priv->bytes_needed)
++ return NDIS_STATUS_INVALID_LENGTH;
++
++ if (poid_par_priv->type_of_oid == SET_OID)
++ {
++ encry_mode = *((u8*)poid_par_priv->information_buf);
++ switch (encry_mode)
++ {
++ case HW_CONTROL:
++ #if 0
++ Adapter->registrypriv.software_decrypt=_FALSE;
++ Adapter->registrypriv.software_encrypt=_FALSE;
++ #else
++ psecuritypriv->sw_decrypt = _FALSE;
++ psecuritypriv->sw_encrypt = _FALSE;
++ #endif
++ break;
++ case SW_CONTROL:
++ #if 0
++ Adapter->registrypriv.software_decrypt=_TRUE;
++ Adapter->registrypriv.software_encrypt=_TRUE;
++ #else
++ psecuritypriv->sw_decrypt = _TRUE;
++ psecuritypriv->sw_encrypt = _TRUE;
++ #endif
++ break;
++ case HW_ENCRY_SW_DECRY:
++ #if 0
++ Adapter->registrypriv.software_decrypt=_TRUE;
++ Adapter->registrypriv.software_encrypt=_FALSE;
++ #else
++ psecuritypriv->sw_decrypt = _TRUE;
++ psecuritypriv->sw_encrypt = _FALSE;
++ #endif
++ break;
++ case SW_ENCRY_HW_DECRY:
++ #if 0
++ Adapter->registrypriv.software_decrypt=_FALSE;
++ Adapter->registrypriv.software_encrypt=_TRUE;
++ #else
++ psecuritypriv->sw_decrypt = _FALSE;
++ psecuritypriv->sw_encrypt = _TRUE;
++ #endif
++ break;
++ }
++
++ RT_TRACE(_module_rtl871x_ioctl_c_, _drv_notice_,
++ ("-oid_rt_pro_encryption_ctrl_hdl: SET encry_mode=0x%x sw_encrypt=0x%x sw_decrypt=0x%x\n",
++ encry_mode, psecuritypriv->sw_encrypt, psecuritypriv->sw_decrypt));
++ }
++ else {
++ #if 0
++ if (Adapter->registrypriv.software_encrypt == _FALSE) {
++ if (Adapter->registrypriv.software_decrypt == _FALSE)
++ encry_mode = HW_CONTROL;
++ else
++ encry_mode = HW_ENCRY_SW_DECRY;
++ }
++ else {
++ if (Adapter->registrypriv.software_decrypt == _FALSE)
++ encry_mode = SW_ENCRY_HW_DECRY;
++ else
++ encry_mode = SW_CONTROL;
++ }
++ #else
++
++ if ((psecuritypriv->sw_encrypt == _FALSE) && (psecuritypriv->sw_decrypt == _FALSE))
++ encry_mode = HW_CONTROL;
++ else if ((psecuritypriv->sw_encrypt == _FALSE) && (psecuritypriv->sw_decrypt == _TRUE))
++ encry_mode = HW_ENCRY_SW_DECRY;
++ else if ((psecuritypriv->sw_encrypt == _TRUE) && (psecuritypriv->sw_decrypt == _FALSE))
++ encry_mode = SW_ENCRY_HW_DECRY;
++ else if ((psecuritypriv->sw_encrypt == _TRUE) && (psecuritypriv->sw_decrypt == _TRUE))
++ encry_mode = SW_CONTROL;
++
++ #endif
++
++ *(u8*)poid_par_priv->information_buf = encry_mode;
++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
++
++ RT_TRACE(_module_mp_, _drv_notice_,
++ ("-oid_rt_pro_encryption_ctrl_hdl: QUERY encry_mode=0x%x\n",
++ encry_mode));
++ }
++
++ return status;
++#else
++ return 0;
++#endif
++}
++//------------------------------------------------------------------------------
++NDIS_STATUS oid_rt_pro_add_sta_info_hdl(struct oid_par_priv *poid_par_priv)
++{
++#if 0
++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++#ifdef PLATFORM_OS_XP
++ _irqL oldirql;
++#endif
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++
++ struct sta_info *psta = NULL;
++ UCHAR *macaddr;
++
++
++ if (poid_par_priv->type_of_oid != SET_OID)
++ return NDIS_STATUS_NOT_ACCEPTED;
++
++ *poid_par_priv->bytes_needed = ETH_ALEN;
++ if (poid_par_priv->information_buf_len < *poid_par_priv->bytes_needed)
++ return NDIS_STATUS_INVALID_LENGTH;
++
++ macaddr = (UCHAR *) poid_par_priv->information_buf ;
++
++ RT_TRACE(_module_rtl871x_ioctl_c_,_drv_notice_,
++ ("OID_RT_PRO_ADD_STA_INFO: addr="MAC_FMT"\n", MAC_ARG(macaddr) ));
++
++ _irqlevel_changed_(&oldirql, LOWER);
++
++ psta = rtw_get_stainfo(&Adapter->stapriv, macaddr);
++
++ if (psta == NULL) { // the sta have been in sta_info_queue => do nothing
++ psta = rtw_alloc_stainfo(&Adapter->stapriv, macaddr);
++
++ if (psta == NULL) {
++ RT_TRACE(_module_rtl871x_ioctl_c_,_drv_err_,("Can't alloc sta_info when OID_RT_PRO_ADD_STA_INFO\n"));
++ status = NDIS_STATUS_FAILURE;
++ }
++ } else { //(between drv has received this event before and fw have not yet to set key to CAM_ENTRY)
++ RT_TRACE(_module_rtl871x_ioctl_c_, _drv_err_,
++ ("Error: OID_RT_PRO_ADD_STA_INFO: sta has been in sta_hash_queue \n"));
++ }
++
++ _irqlevel_changed_(&oldirql, RAISE);
++
++ return status;
++#else
++ return 0;
++#endif
++}
++//------------------------------------------------------------------------------
++NDIS_STATUS oid_rt_pro_dele_sta_info_hdl(struct oid_par_priv *poid_par_priv)
++{
++#if 0
++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++#ifdef PLATFORM_OS_XP
++ _irqL oldirql;
++#endif
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++
++ struct sta_info *psta = NULL;
++ UCHAR *macaddr;
++
++
++ if (poid_par_priv->type_of_oid != SET_OID)
++ return NDIS_STATUS_NOT_ACCEPTED;
++
++ *poid_par_priv->bytes_needed = ETH_ALEN;
++ if (poid_par_priv->information_buf_len < *poid_par_priv->bytes_needed)
++ return NDIS_STATUS_INVALID_LENGTH;
++
++ macaddr = (UCHAR *) poid_par_priv->information_buf ;
++ RT_TRACE(_module_rtl871x_ioctl_c_,_drv_notice_,
++ ("+OID_RT_PRO_ADD_STA_INFO: addr="MAC_FMT"\n", MAC_ARG(macaddr) ));
++
++ psta = rtw_get_stainfo(&Adapter->stapriv, macaddr);
++ if (psta != NULL) {
++ _enter_critical(&(Adapter->stapriv.sta_hash_lock), &irqL);
++ rtw_free_stainfo(Adapter, psta);
++ _exit_critical(&(Adapter->stapriv.sta_hash_lock), &irqL);
++ }
++
++ return status;
++#else
++ return 0;
++#endif
++}
++//------------------------------------------------------------------------------
++#if 0
++#include <sdio_osintf.h>
++static u32 mp_query_drv_var(_adapter *padapter, u8 offset, u32 var)
++{
++#ifdef CONFIG_SDIO_HCI
++
++ if (offset == 1) {
++ u16 tmp_blk_num;
++ tmp_blk_num = rtw_read16(padapter, SDIO_RX0_RDYBLK_NUM);
++ RT_TRACE(_module_mp_, _drv_err_, ("Query Information, mp_query_drv_var SDIO_RX0_RDYBLK_NUM=0x%x adapter_to_dvobj(padapter)->rxblknum=0x%x\n", tmp_blk_num, adapter_to_dvobj(padapter)->rxblknum));
++ if (adapter_to_dvobj(padapter)->rxblknum != tmp_blk_num) {
++ RT_TRACE(_module_mp_,_drv_err_, ("Query Information, mp_query_drv_var call recv rx\n"));
++ // sd_recv_rxfifo(padapter);
++ }
++ }
++
++#if 0
++ if(offset <=100){ //For setting data rate and query data rate
++ if(offset==100){ //For query data rate
++ RT_TRACE(_module_mp_, _drv_emerg_, ("\n mp_query_drv_var: offset(%d): query rate=0x%.2x \n",offset,padapter->registrypriv.tx_rate));
++ var=padapter->registrypriv.tx_rate;
++
++ }
++ else if(offset<0x1d){ //For setting data rate
++ padapter->registrypriv.tx_rate=offset;
++ var=padapter->registrypriv.tx_rate;
++ padapter->registrypriv.use_rate=_TRUE;
++ RT_TRACE(_module_mp_, _drv_emerg_, ("\n mp_query_drv_var: offset(%d): set rate=0x%.2x \n",offset,padapter->registrypriv.tx_rate));
++ }
++ else{ //not use the data rate
++ padapter->registrypriv.use_rate=_FALSE;
++ RT_TRACE(_module_mp_, _drv_emerg_, ("\n mp_query_drv_var: offset(%d) out of rate range\n",offset));
++ }
++ }
++ else if (offset<=110){ //for setting debug level
++ RT_TRACE(_module_mp_, _drv_emerg_, (" mp_query_drv_var: offset(%d) for set debug level\n",offset));
++ if(offset==110){ //For query data rate
++ RT_TRACE(_module_mp_, _drv_emerg_, (" mp_query_drv_var: offset(%d): query dbg level=0x%.2x \n",offset,padapter->registrypriv.dbg_level));
++ padapter->registrypriv.dbg_level=GlobalDebugLevel;
++ var=padapter->registrypriv.dbg_level;
++ }
++ else if(offset<110 && offset>100){
++ RT_TRACE(_module_mp_, _drv_emerg_, (" mp_query_drv_var: offset(%d): set dbg level=0x%.2x \n",offset,offset-100));
++ padapter->registrypriv.dbg_level=GlobalDebugLevel=offset-100;
++ var=padapter->registrypriv.dbg_level;
++ RT_TRACE(_module_mp_, _drv_emerg_, (" mp_query_drv_var(_drv_emerg_): offset(%d): set dbg level=0x%.2x \n",offset,GlobalDebugLevel));
++ RT_TRACE(_module_mp_, _drv_alert_, (" mp_query_drv_var(_drv_alert_): offset(%d): set dbg level=0x%.2x \n",offset,GlobalDebugLevel));
++ RT_TRACE(_module_mp_, _drv_crit_, (" mp_query_drv_var(_drv_crit_): offset(%d): set dbg level=0x%.2x \n",offset,GlobalDebugLevel));
++ RT_TRACE(_module_mp_, _drv_err_, (" mp_query_drv_var(_drv_err_): offset(%d): set dbg level=0x%.2x \n",offset,GlobalDebugLevel));
++ RT_TRACE(_module_mp_, _drv_warning_, (" mp_query_drv_var(_drv_warning_): offset(%d): set dbg level=0x%.2x \n",offset,GlobalDebugLevel));
++ RT_TRACE(_module_mp_, _drv_notice_, (" mp_query_drv_var(_drv_notice_): offset(%d): set dbg level=0x%.2x \n",offset,GlobalDebugLevel));
++ RT_TRACE(_module_mp_, _drv_info_, (" mp_query_drv_var(_drv_info_): offset(%d): set dbg level=0x%.2x \n",offset,GlobalDebugLevel));
++ RT_TRACE(_module_mp_, _drv_debug_, (" mp_query_drv_var(_drv_debug_): offset(%d): set dbg level=0x%.2x \n",offset,GlobalDebugLevel));
++
++ }
++ }
++ else if(offset >110 &&offset <116){
++ if(115==offset){
++ RT_TRACE(_module_mp_, _drv_emerg_, (" mp_query_drv_var(_drv_emerg_): offset(%d): query TRX access type: [tx_block_mode=%x,rx_block_mode=%x]\n",\
++ offset, adapter_to_dvobj(padapter)->tx_block_mode, adapter_to_dvobj(padapter)->rx_block_mode));
++ }
++ else {
++ switch(offset){
++ case 111:
++ adapter_to_dvobj(padapter)->tx_block_mode=1;
++ adapter_to_dvobj(padapter)->rx_block_mode=1;
++ RT_TRACE(_module_mp_, _drv_emerg_, \
++ (" mp_query_drv_var(_drv_emerg_): offset(%d): SET TRX access type:(TX block/RX block) [tx_block_mode=%x,rx_block_mode=%x]\n",\
++ offset, adapter_to_dvobj(padapter)->tx_block_mode, adapter_to_dvobj(padapter)->rx_block_mode));
++ break;
++ case 112:
++ adapter_to_dvobj(padapter)->tx_block_mode=1;
++ adapter_to_dvobj(padapter)->rx_block_mode=0;
++ RT_TRACE(_module_mp_, _drv_emerg_, \
++ (" mp_query_drv_var(_drv_emerg_): offset(%d): SET TRX access type:(TX block/RX byte) [tx_block_mode=%x,rx_block_mode=%x]\n",\
++ offset, adapter_to_dvobj(padapter)->tx_block_mode, adapter_to_dvobj(padapter)->rx_block_mode));
++ break;
++ case 113:
++ adapter_to_dvobj(padapter)->tx_block_mode=0;
++ adapter_to_dvobj(padapter)->rx_block_mode=1;
++ RT_TRACE(_module_mp_, _drv_emerg_, \
++ (" mp_query_drv_var(_drv_emerg_): offset(%d): SET TRX access type:(TX byte/RX block) [tx_block_mode=%x,rx_block_mode=%x]\n",\
++ offset, adapter_to_dvobj(padapter)->tx_block_mode, adapter_to_dvobj(padapter)->rx_block_mode));
++ break;
++ case 114:
++ adapter_to_dvobj(padapter)->tx_block_mode=0;
++ adapter_to_dvobj(padapter)->rx_block_mode=0;
++ RT_TRACE(_module_mp_, _drv_emerg_, \
++ (" mp_query_drv_var(_drv_emerg_): offset(%d): SET TRX access type:(TX byte/RX byte) [tx_block_mode=%x,rx_block_mode=%x]\n",\
++ offset, adapter_to_dvobj(padapter)->tx_block_mode, adapter_to_dvobj(padapter)->rx_block_mode));
++ break;
++ default :
++ break;
++
++ }
++
++ }
++
++ }
++ else if(offset>=127){
++ u64 prnt_dbg_comp;
++ u8 chg_idx;
++ u64 tmp_dbg_comp;
++ chg_idx=offset-0x80;
++ tmp_dbg_comp=BIT(chg_idx);
++ prnt_dbg_comp=padapter->registrypriv.dbg_component= GlobalDebugComponents;
++ RT_TRACE(_module_mp_, _drv_emerg_, (" 1: mp_query_drv_var: offset(%d;0x%x):for dbg conpoment prnt_dbg_comp=0x%.16x GlobalDebugComponents=0x%.16x padapter->registrypriv.dbg_component=0x%.16x\n",offset,offset,prnt_dbg_comp,GlobalDebugComponents,padapter->registrypriv.dbg_component));
++ if(offset==127){
++ // prnt_dbg_comp=padapter->registrypriv.dbg_component= GlobalDebugComponents;
++ var=(u32)(padapter->registrypriv.dbg_component);
++ RT_TRACE(0xffffffff, _drv_emerg_, ("2: mp_query_drv_var: offset(%d;0x%x):for query dbg conpoment=0x%x(l) 0x%x(h) GlobalDebugComponents=0x%x(l) 0x%x(h) \n",offset,offset,padapter->registrypriv.dbg_component,prnt_dbg_comp));
++ prnt_dbg_comp=GlobalDebugComponents;
++ RT_TRACE(0xffffffff, _drv_emerg_, ("2-1: mp_query_drv_var: offset(%d;0x%x):for query dbg conpoment=0x%x(l) 0x%x(h) GlobalDebugComponents=0x%x(l) 0x%x(h)\n",offset,offset,padapter->registrypriv.dbg_component,prnt_dbg_comp));
++ prnt_dbg_comp=GlobalDebugComponents=padapter->registrypriv.dbg_component;
++ RT_TRACE(0xffffffff, _drv_emerg_, ("2-2: mp_query_drv_var: offset(%d;0x%x):for query dbg conpoment=0x%x(l) 0x%x(h) GlobalDebugComponents=0x%x(l) 0x%x(h)\n",offset,offset,padapter->registrypriv.dbg_component,prnt_dbg_comp));
++
++ }
++ else{
++ RT_TRACE(0xffffffff, _drv_emerg_, ("3: mp_query_drv_var: offset(%d;0x%x):for query dbg conpoment=0x%x(l) 0x%x(h) GlobalDebugComponents=0x%x(l) 0x%x(h) chg_idx=%d\n",offset,offset,padapter->registrypriv.dbg_component,prnt_dbg_comp,chg_idx));
++ prnt_dbg_comp=GlobalDebugComponents;
++ RT_TRACE(0xffffffff, _drv_emerg_,("3-1: mp_query_drv_var: offset(%d;0x%x):for query dbg conpoment=0x%x(l) 0x%x(h) GlobalDebugComponents=0x%x(l) 0x%x(h) chg_idx=%d\n",offset,offset,padapter->registrypriv.dbg_component,prnt_dbg_comp,chg_idx));// ("3-1: mp_query_drv_var: offset(%d;0x%x):before set dbg conpoment=0x%x chg_idx=%d or0x%x BIT(chg_idx[%d]=0x%x)\n",offset,offset,prnt_dbg_comp,chg_idx,chg_idx,(chg_idx),tmp_dbg_comp)
++ prnt_dbg_comp=GlobalDebugComponents=padapter->registrypriv.dbg_component;
++ RT_TRACE(0xffffffff, _drv_emerg_, ("3-2: mp_query_drv_var: offset(%d;0x%x):for query dbg conpoment=0x%x(l) 0x%x(h) GlobalDebugComponents=0x%x(l) 0x%x(h)\n",offset,offset,padapter->registrypriv.dbg_component,prnt_dbg_comp));
++
++ if(GlobalDebugComponents&tmp_dbg_comp){
++ //this bit is already set, now clear it
++ GlobalDebugComponents=GlobalDebugComponents&(~tmp_dbg_comp);
++ }
++ else{
++ //this bit is not set, now set it.
++ GlobalDebugComponents =GlobalDebugComponents|tmp_dbg_comp;
++ }
++ RT_TRACE(0xffffffff, _drv_emerg_, ("4: mp_query_drv_var: offset(%d;0x%x):before set dbg conpoment tmp_dbg_comp=0x%x GlobalDebugComponents=0x%x(l) 0x%x(h)",offset,offset,tmp_dbg_comp,prnt_dbg_comp));
++ prnt_dbg_comp=GlobalDebugComponents;
++ RT_TRACE(0xffffffff, _drv_emerg_, ("4-1: mp_query_drv_var: offset(%d;0x%x):before set dbg conpoment tmp_dbg_comp=0x%x GlobalDebugComponents=0x%x(l) 0x%x(h)",offset,offset,tmp_dbg_comp,prnt_dbg_comp));
++
++ RT_TRACE(_module_rtl871x_xmit_c_, _drv_emerg_, ("0: mp_query_drv_var(_module_rtl871x_xmit_c_:0): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,prnt_dbg_comp));
++ RT_TRACE(_module_xmit_osdep_c_, _drv_emerg_, ("1: mp_query_drv_var(_module_xmit_osdep_c_:1): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents));
++ RT_TRACE(_module_rtl871x_recv_c_, _drv_emerg_, ("2: mp_query_drv_var(_module_rtl871x_recv_c_:2): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents));
++ RT_TRACE(_module_recv_osdep_c_, _drv_emerg_, ("3: mp_query_drv_var(_module_recv_osdep_c_:3): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents));
++ RT_TRACE(_module_rtl871x_mlme_c_, _drv_emerg_, ("4: mp_query_drv_var(_module_rtl871x_mlme_c_:4): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents));
++ RT_TRACE(_module_mlme_osdep_c_, _drv_emerg_, (" 5:mp_query_drv_var(_module_mlme_osdep_c_:5): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents));
++ RT_TRACE(_module_rtl871x_sta_mgt_c_, _drv_emerg_, ("6: mp_query_drv_var(_module_rtl871x_sta_mgt_c_:6): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents));
++ RT_TRACE(_module_rtl871x_cmd_c_, _drv_emerg_, ("7: mp_query_drv_var(_module_rtl871x_cmd_c_:7): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents));
++ RT_TRACE(_module_cmd_osdep_c_, _drv_emerg_, ("8: mp_query_drv_var(_module_cmd_osdep_c_:8): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents));
++ RT_TRACE(_module_rtl871x_io_c_, _drv_emerg_, ("9: mp_query_drv_var(_module_rtl871x_io_c_:9): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents));
++ RT_TRACE(_module_io_osdep_c_, _drv_emerg_, ("10: mp_query_drv_var(_module_io_osdep_c_:10): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents));
++ RT_TRACE(_module_os_intfs_c_, _drv_emerg_, ("11: mp_query_drv_var(_module_os_intfs_c_:11): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents));
++ RT_TRACE(_module_rtl871x_security_c_, _drv_emerg_, ("12: mp_query_drv_var(_module_rtl871x_security_c_:12): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents));
++ RT_TRACE(_module_rtl871x_eeprom_c_, _drv_emerg_, ("13: mp_query_drv_var(_module_rtl871x_eeprom_c_:13): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents));
++ RT_TRACE(_module_hal_init_c_, _drv_emerg_, ("14: mp_query_drv_var(_module_hal_init_c_:14): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents));
++ RT_TRACE(_module_hci_hal_init_c_, _drv_emerg_, ("15: mp_query_drv_var(_module_hci_hal_init_c_:15): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents));
++ RT_TRACE(_module_rtl871x_ioctl_c_, _drv_emerg_, ("16: mp_query_drv_var(_module_rtl871x_ioctl_c_:16): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents));
++ RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_emerg_, ("17: mp_query_drv_var(_module_rtl871x_ioctl_set_c_:17): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents));
++ RT_TRACE(_module_rtl871x_ioctl_query_c_, _drv_emerg_, ("18: mp_query_drv_var(_module_rtl871x_ioctl_query_c_:18): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents));
++ RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_emerg_, ("19: mp_query_drv_var(_module_rtl871x_pwrctrl_c_:19): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents));
++ RT_TRACE(_module_hci_intfs_c_, _drv_emerg_, ("20: mp_query_drv_var(_module_hci_intfs_c_:20): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents));
++ RT_TRACE(_module_hci_ops_c_, _drv_emerg_, ("21: mp_query_drv_var(_module_hci_ops_c_:21): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents));
++ RT_TRACE(_module_osdep_service_c_, _drv_emerg_, ("22: mp_query_drv_var(_module_osdep_service_c_:22): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents));
++ RT_TRACE(_module_mp_, _drv_emerg_, ("23: mp_query_drv_var(_module_mp_:23): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents));
++ RT_TRACE(_module_hci_ops_os_c_, _drv_emerg_, ("24: mp_query_drv_var(_module_hci_ops_os_c_:24): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents));
++ var=(u32)(GlobalDebugComponents);
++ //GlobalDebugComponents=padapter->registrypriv.dbg_component;
++ RT_TRACE(0xffffffff, _drv_emerg_, (" ==mp_query_drv_var(_module_mp_): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents));
++
++ }
++ }
++ else{
++ RT_TRACE(_module_mp_, _drv_emerg_, ("\n mp_query_drv_var: offset(%d) >110\n",offset));
++ }
++#endif
++#endif
++
++ return var;
++}
++#endif
++
++NDIS_STATUS oid_rt_pro_query_dr_variable_hdl(struct oid_par_priv *poid_par_priv)
++{
++#if 0
++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++#ifdef PLATFORM_OS_XP
++ _irqL oldirql;
++#endif
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++
++ DR_VARIABLE_STRUCT *pdrv_var;
++
++
++ if (poid_par_priv->type_of_oid != QUERY_OID)
++ return NDIS_STATUS_NOT_ACCEPTED;
++
++ *poid_par_priv->bytes_needed = sizeof(DR_VARIABLE_STRUCT);
++ if (poid_par_priv->information_buf_len < *poid_par_priv->bytes_needed)
++ return NDIS_STATUS_INVALID_LENGTH;
++
++ RT_TRACE(_module_mp_, _drv_notice_, ("+Query Information, OID_RT_PRO_QUERY_DR_VARIABLE\n"));
++
++ pdrv_var = (struct _DR_VARIABLE_STRUCT_ *)poid_par_priv->information_buf;
++
++ _irqlevel_changed_(&oldirql, LOWER);
++ pdrv_var->variable = mp_query_drv_var(Adapter, pdrv_var->offset, pdrv_var->variable);
++ _irqlevel_changed_(&oldirql, RAISE);
++
++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
++
++ RT_TRACE(_module_mp_, _drv_notice_,
++ ("-oid_rt_pro_query_dr_variable_hdl: offset=0x%x valule=0x%x\n",
++ pdrv_var->offset, pdrv_var->variable));
++
++ return status;
++#else
++ return 0;
++#endif
++}
++//------------------------------------------------------------------------------
++NDIS_STATUS oid_rt_pro_rx_packet_type_hdl(struct oid_par_priv *poid_par_priv)
++{
++#if 0
++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++
++ RT_TRACE(_module_mp_, _drv_err_, ("oid_rt_pro_rx_packet_type_hdl...................\n"));
++
++ if (poid_par_priv->information_buf_len < sizeof (UCHAR)) {
++ status = NDIS_STATUS_INVALID_LENGTH;
++ *poid_par_priv->bytes_needed = sizeof(UCHAR);
++ return status;
++ }
++
++ if (poid_par_priv->type_of_oid == SET_OID) {
++ Adapter->mppriv.rx_with_status = *(UCHAR *) poid_par_priv->information_buf;
++ RT_TRACE(_module_rtl871x_ioctl_c_,_drv_err_, ("Query Information, OID_RT_PRO_RX_PACKET_TYPE:%d \n",\
++ Adapter->mppriv.rx_with_status));
++
++ //*(u32 *)&Adapter->eeprompriv.mac_addr[0]=rtw_read32(Adapter, 0x10250050);
++ //*(u16 *)&Adapter->eeprompriv.mac_addr[4]=rtw_read16(Adapter, 0x10250054);
++ RT_TRACE(_module_rtl871x_ioctl_c_,_drv_err_,("MAC addr=0x%x:0x%x:0x%x:0x%x:0x%x:0x%x \n",
++ Adapter->eeprompriv.mac_addr[0],Adapter->eeprompriv.mac_addr[1],Adapter->eeprompriv.mac_addr[2],\
++ Adapter->eeprompriv.mac_addr[3],Adapter->eeprompriv.mac_addr[4],Adapter->eeprompriv.mac_addr[5]));
++
++ }
++ else {
++ *(UCHAR *) poid_par_priv->information_buf = Adapter->mppriv.rx_with_status;
++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
++
++ RT_TRACE(_module_rtl871x_ioctl_c_,_drv_err_, ("Query Information, OID_RT_PRO_RX_PACKET_TYPE:%d \n", \
++ Adapter->mppriv.rx_with_status));
++
++ //*(u32 *)&Adapter->eeprompriv.mac_addr[0]=rtw_read32(Adapter, 0x10250050);
++ //*(u16 *)&Adapter->eeprompriv.mac_addr[4]=rtw_read16(Adapter, 0x10250054);
++ RT_TRACE(_module_rtl871x_ioctl_c_,_drv_err_,("MAC addr=0x%x:0x%x:0x%x:0x%x:0x%x:0x%x \n",
++ Adapter->eeprompriv.mac_addr[0],Adapter->eeprompriv.mac_addr[1],Adapter->eeprompriv.mac_addr[2],\
++ Adapter->eeprompriv.mac_addr[3],Adapter->eeprompriv.mac_addr[4],Adapter->eeprompriv.mac_addr[5]));
++ }
++#endif
++
++ return NDIS_STATUS_SUCCESS;
++}
++//------------------------------------------------------------------------------
++NDIS_STATUS oid_rt_pro_read_efuse_hdl(struct oid_par_priv *poid_par_priv)
++{
++#ifdef PLATFORM_OS_XP
++ _irqL oldirql;
++#endif
++ PEFUSE_ACCESS_STRUCT pefuse;
++ u8 *data;
++ u16 addr = 0, cnts = 0, max_available_size = 0;
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++_func_enter_;
++
++ if (poid_par_priv->type_of_oid != QUERY_OID)
++ return NDIS_STATUS_NOT_ACCEPTED;
++
++ if (poid_par_priv->information_buf_len < sizeof(EFUSE_ACCESS_STRUCT))
++ return NDIS_STATUS_INVALID_LENGTH;
++
++ pefuse = (PEFUSE_ACCESS_STRUCT)poid_par_priv->information_buf;
++ addr = pefuse->start_addr;
++ cnts = pefuse->cnts;
++ data = pefuse->data;
++
++ RT_TRACE(_module_mp_, _drv_notice_,
++ ("+oid_rt_pro_read_efuse_hd: buf_len=%ld addr=%d cnts=%d\n",
++ poid_par_priv->information_buf_len, addr, cnts));
++
++ EFUSE_GetEfuseDefinition(Adapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, (PVOID)&max_available_size, _FALSE);
++
++ if ((addr + cnts) > max_available_size) {
++ RT_TRACE(_module_mp_, _drv_err_, ("!oid_rt_pro_read_efuse_hdl: parameter error!\n"));
++ return NDIS_STATUS_NOT_ACCEPTED;
++ }
++
++ _irqlevel_changed_(&oldirql, LOWER);
++ if (rtw_efuse_access(Adapter, _FALSE, addr, cnts, data) == _FAIL) {
++ RT_TRACE(_module_mp_, _drv_err_, ("!oid_rt_pro_read_efuse_hdl: rtw_efuse_access FAIL!\n"));
++ status = NDIS_STATUS_FAILURE;
++ } else
++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
++ _irqlevel_changed_(&oldirql, RAISE);
++
++_func_exit_;
++
++ return status;
++}
++//------------------------------------------------------------------------------
++NDIS_STATUS oid_rt_pro_write_efuse_hdl(struct oid_par_priv *poid_par_priv)
++{
++#ifdef PLATFORM_OS_XP
++ _irqL oldirql;
++#endif
++ PEFUSE_ACCESS_STRUCT pefuse;
++ u8 *data;
++ u16 addr = 0, cnts = 0, max_available_size = 0;
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++
++_func_enter_;
++
++ if (poid_par_priv->type_of_oid != SET_OID)
++ return NDIS_STATUS_NOT_ACCEPTED;
++
++ pefuse = (PEFUSE_ACCESS_STRUCT)poid_par_priv->information_buf;
++ addr = pefuse->start_addr;
++ cnts = pefuse->cnts;
++ data = pefuse->data;
++
++ RT_TRACE(_module_mp_, _drv_notice_,
++ ("+oid_rt_pro_write_efuse_hdl: buf_len=%ld addr=0x%04x cnts=%d\n",
++ poid_par_priv->information_buf_len, addr, cnts));
++
++ EFUSE_GetEfuseDefinition(Adapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, (PVOID)&max_available_size, _FALSE);
++
++ if ((addr + cnts) > max_available_size) {
++ RT_TRACE(_module_mp_, _drv_err_, ("!oid_rt_pro_write_efuse_hdl: parameter error"));
++ return NDIS_STATUS_NOT_ACCEPTED;
++ }
++
++ _irqlevel_changed_(&oldirql, LOWER);
++ if (rtw_efuse_access(Adapter, _TRUE, addr, cnts, data) == _FAIL)
++ status = NDIS_STATUS_FAILURE;
++ _irqlevel_changed_(&oldirql, RAISE);
++
++_func_exit_;
++
++ return status;
++}
++//------------------------------------------------------------------------------
++NDIS_STATUS oid_rt_pro_rw_efuse_pgpkt_hdl(struct oid_par_priv *poid_par_priv)
++{
++#ifdef PLATFORM_OS_XP
++ _irqL oldirql;
++#endif
++ PPGPKT_STRUCT ppgpkt;
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++_func_enter_;
++
++// RT_TRACE(_module_mp_, _drv_info_, ("+oid_rt_pro_rw_efuse_pgpkt_hdl\n"));
++
++ *poid_par_priv->bytes_rw = 0;
++
++ if (poid_par_priv->information_buf_len < sizeof(PGPKT_STRUCT))
++ return NDIS_STATUS_INVALID_LENGTH;
++
++ ppgpkt = (PPGPKT_STRUCT)poid_par_priv->information_buf;
++
++ _irqlevel_changed_(&oldirql, LOWER);
++
++ if (poid_par_priv->type_of_oid == QUERY_OID)
++ {
++ RT_TRACE(_module_mp_, _drv_notice_,
++ ("oid_rt_pro_rw_efuse_pgpkt_hdl: Read offset=0x%x\n",\
++ ppgpkt->offset));
++
++ Efuse_PowerSwitch(Adapter, _FALSE, _TRUE);
++ if (Efuse_PgPacketRead(Adapter, ppgpkt->offset, ppgpkt->data, _FALSE) == _TRUE)
++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
++ else
++ status = NDIS_STATUS_FAILURE;
++ Efuse_PowerSwitch(Adapter, _FALSE, _FALSE);
++ } else {
++ RT_TRACE(_module_mp_, _drv_notice_,
++ ("oid_rt_pro_rw_efuse_pgpkt_hdl: Write offset=0x%x word_en=0x%x\n",\
++ ppgpkt->offset, ppgpkt->word_en));
++
++ Efuse_PowerSwitch(Adapter, _TRUE, _TRUE);
++ if (Efuse_PgPacketWrite(Adapter, ppgpkt->offset, ppgpkt->word_en, ppgpkt->data, _FALSE) == _TRUE)
++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
++ else
++ status = NDIS_STATUS_FAILURE;
++ Efuse_PowerSwitch(Adapter, _TRUE, _FALSE);
++ }
++
++ _irqlevel_changed_(&oldirql, RAISE);
++
++ RT_TRACE(_module_mp_, _drv_info_,
++ ("-oid_rt_pro_rw_efuse_pgpkt_hdl: status=0x%08X\n", status));
++
++_func_exit_;
++
++ return status;
++}
++//------------------------------------------------------------------------------
++NDIS_STATUS oid_rt_get_efuse_current_size_hdl(struct oid_par_priv *poid_par_priv)
++{
++#ifdef PLATFORM_OS_XP
++ _irqL oldirql;
++#endif
++ u16 size;
++ u8 ret;
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++_func_enter_;
++
++ if (poid_par_priv->type_of_oid != QUERY_OID)
++ return NDIS_STATUS_NOT_ACCEPTED;
++
++ if (poid_par_priv->information_buf_len <sizeof(u32))
++ return NDIS_STATUS_INVALID_LENGTH;
++
++ _irqlevel_changed_(&oldirql, LOWER);
++ ret = efuse_GetCurrentSize(Adapter, &size);
++ _irqlevel_changed_(&oldirql, RAISE);
++ if (ret == _SUCCESS) {
++ *(u32*)poid_par_priv->information_buf = size;
++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
++ } else
++ status = NDIS_STATUS_FAILURE;
++
++_func_exit_;
++
++ return status;
++}
++//------------------------------------------------------------------------------
++NDIS_STATUS oid_rt_get_efuse_max_size_hdl(struct oid_par_priv *poid_par_priv)
++{
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++_func_enter_;
++
++ if (poid_par_priv->type_of_oid != QUERY_OID)
++ return NDIS_STATUS_NOT_ACCEPTED;
++
++ if (poid_par_priv->information_buf_len < sizeof(u32))
++ return NDIS_STATUS_INVALID_LENGTH;
++
++ *(u32*)poid_par_priv->information_buf = efuse_GetMaxSize(Adapter);
++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
++
++ RT_TRACE(_module_mp_, _drv_info_,
++ ("-oid_rt_get_efuse_max_size_hdl: size=%d status=0x%08X\n",
++ *(int*)poid_par_priv->information_buf, status));
++
++_func_exit_;
++
++ return status;
++}
++//------------------------------------------------------------------------------
++NDIS_STATUS oid_rt_pro_efuse_hdl(struct oid_par_priv *poid_par_priv)
++{
++ NDIS_STATUS status;
++
++_func_enter_;
++
++ RT_TRACE(_module_mp_, _drv_info_, ("+oid_rt_pro_efuse_hdl\n"));
++
++ if (poid_par_priv->type_of_oid == QUERY_OID)
++ status = oid_rt_pro_read_efuse_hdl(poid_par_priv);
++ else
++ status = oid_rt_pro_write_efuse_hdl(poid_par_priv);
++
++ RT_TRACE(_module_mp_, _drv_info_, ("-oid_rt_pro_efuse_hdl: status=0x%08X\n", status));
++
++_func_exit_;
++
++ return status;
++}
++//------------------------------------------------------------------------------
++NDIS_STATUS oid_rt_pro_efuse_map_hdl(struct oid_par_priv *poid_par_priv)
++{
++#ifdef PLATFORM_OS_XP
++ _irqL oldirql;
++#endif
++ u8 *data;
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
++ u16 mapLen=0;
++
++_func_enter_;
++
++ RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_efuse_map_hdl\n"));
++
++ EFUSE_GetEfuseDefinition(Adapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (PVOID)&mapLen, _FALSE);
++
++ *poid_par_priv->bytes_rw = 0;
++
++ if (poid_par_priv->information_buf_len < mapLen)
++ return NDIS_STATUS_INVALID_LENGTH;
++
++ data = (u8*)poid_par_priv->information_buf;
++
++ _irqlevel_changed_(&oldirql, LOWER);
++
++ if (poid_par_priv->type_of_oid == QUERY_OID)
++ {
++ RT_TRACE(_module_mp_, _drv_info_,
++ ("oid_rt_pro_efuse_map_hdl: READ\n"));
++
++ if (rtw_efuse_map_read(Adapter, 0, mapLen, data) == _SUCCESS)
++ *poid_par_priv->bytes_rw = mapLen;
++ else {
++ RT_TRACE(_module_mp_, _drv_err_,
++ ("oid_rt_pro_efuse_map_hdl: READ fail\n"));
++ status = NDIS_STATUS_FAILURE;
++ }
++ } else {
++ // SET_OID
++ RT_TRACE(_module_mp_, _drv_info_,
++ ("oid_rt_pro_efuse_map_hdl: WRITE\n"));
++
++ if (rtw_efuse_map_write(Adapter, 0, mapLen, data) == _SUCCESS)
++ *poid_par_priv->bytes_rw = mapLen;
++ else {
++ RT_TRACE(_module_mp_, _drv_err_,
++ ("oid_rt_pro_efuse_map_hdl: WRITE fail\n"));
++ status = NDIS_STATUS_FAILURE;
++ }
++ }
++
++ _irqlevel_changed_(&oldirql, RAISE);
++
++ RT_TRACE(_module_mp_, _drv_info_,
++ ("-oid_rt_pro_efuse_map_hdl: status=0x%08X\n", status));
++
++_func_exit_;
++
++ return status;
++}
++
++NDIS_STATUS oid_rt_set_crystal_cap_hdl(struct oid_par_priv *poid_par_priv)
++{
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++#if 0
++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++#ifdef PLATFORM_OS_XP
++ _irqL oldirql;
++#endif
++
++ u32 crystal_cap = 0;
++
++_func_enter_;
++
++ if (poid_par_priv->type_of_oid != SET_OID)
++ return NDIS_STATUS_NOT_ACCEPTED;
++
++ if (poid_par_priv->information_buf_len <sizeof(u32))
++ return NDIS_STATUS_INVALID_LENGTH;
++
++ crystal_cap = *((u32*)poid_par_priv->information_buf);//4
++ if (crystal_cap > 0xf)
++ return NDIS_STATUS_NOT_ACCEPTED;
++
++ Adapter->mppriv.curr_crystalcap = crystal_cap;
++
++ _irqlevel_changed_(&oldirql,LOWER);
++ SetCrystalCap(Adapter);
++ _irqlevel_changed_(&oldirql,RAISE);
++
++_func_exit_;
++
++#endif
++ return status;
++}
++
++NDIS_STATUS oid_rt_set_rx_packet_type_hdl(struct oid_par_priv *poid_par_priv)
++{
++#ifdef PLATFORM_OS_XP
++ _irqL oldirql;
++#endif
++ u8 rx_pkt_type;
++// u32 rcr_val32;
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++// PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++_func_enter_;
++
++ RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_set_rx_packet_type_hdl\n"));
++
++ if (poid_par_priv->type_of_oid != SET_OID)
++ return NDIS_STATUS_NOT_ACCEPTED;
++
++ if (poid_par_priv->information_buf_len < sizeof(u8))
++ return NDIS_STATUS_INVALID_LENGTH;
++
++ rx_pkt_type = *((u8*)poid_par_priv->information_buf);//4
++
++ RT_TRACE(_module_mp_, _drv_info_, ("rx_pkt_type: %x\n",rx_pkt_type ));
++#if 0
++ _irqlevel_changed_(&oldirql, LOWER);
++#if 0
++ rcr_val8 = rtw_read8(Adapter, 0x10250048);//RCR
++ rcr_val8 &= ~(RCR_AB|RCR_AM|RCR_APM|RCR_AAP);
++
++ if(rx_pkt_type == RX_PKT_BROADCAST){
++ rcr_val8 |= (RCR_AB | RCR_ACRC32 );
++ }
++ else if(rx_pkt_type == RX_PKT_DEST_ADDR){
++ rcr_val8 |= (RCR_AAP| RCR_AM |RCR_ACRC32);
++ }
++ else if(rx_pkt_type == RX_PKT_PHY_MATCH){
++ rcr_val8 |= (RCR_APM|RCR_ACRC32);
++ }
++ else{
++ rcr_val8 &= ~(RCR_AAP|RCR_APM|RCR_AM|RCR_AB|RCR_ACRC32);
++ }
++ rtw_write8(padapter, 0x10250048,rcr_val8);
++#else
++ rcr_val32 = rtw_read32(padapter, RCR);//RCR = 0x10250048
++ rcr_val32 &= ~(RCR_CBSSID|RCR_AB|RCR_AM|RCR_APM|RCR_AAP);
++#if 0
++ if(rx_pkt_type == RX_PKT_BROADCAST){
++ rcr_val32 |= (RCR_AB|RCR_AM|RCR_APM|RCR_AAP|RCR_ACRC32);
++ }
++ else if(rx_pkt_type == RX_PKT_DEST_ADDR){
++ //rcr_val32 |= (RCR_CBSSID|RCR_AAP|RCR_AM|RCR_ACRC32);
++ rcr_val32 |= (RCR_CBSSID|RCR_APM|RCR_ACRC32);
++ }
++ else if(rx_pkt_type == RX_PKT_PHY_MATCH){
++ rcr_val32 |= (RCR_APM|RCR_ACRC32);
++ //rcr_val32 |= (RCR_AAP|RCR_ACRC32);
++ }
++ else{
++ rcr_val32 &= ~(RCR_AAP|RCR_APM|RCR_AM|RCR_AB|RCR_ACRC32);
++ }
++#else
++ switch (rx_pkt_type)
++ {
++ case RX_PKT_BROADCAST :
++ rcr_val32 |= (RCR_AB|RCR_AM|RCR_APM|RCR_AAP|RCR_ACRC32);
++ break;
++ case RX_PKT_DEST_ADDR :
++ rcr_val32 |= (RCR_AB|RCR_AM|RCR_APM|RCR_AAP|RCR_ACRC32);
++ break;
++ case RX_PKT_PHY_MATCH:
++ rcr_val32 |= (RCR_APM|RCR_ACRC32);
++ break;
++ default:
++ rcr_val32 &= ~(RCR_AAP|RCR_APM|RCR_AM|RCR_AB|RCR_ACRC32);
++ break;
++ }
++
++ if (rx_pkt_type == RX_PKT_DEST_ADDR) {
++ padapter->mppriv.check_mp_pkt = 1;
++ } else {
++ padapter->mppriv.check_mp_pkt = 0;
++ }
++#endif
++ rtw_write32(padapter, RCR, rcr_val32);
++
++#endif
++ _irqlevel_changed_(&oldirql, RAISE);
++#endif
++_func_exit_;
++
++ return status;
++}
++
++NDIS_STATUS oid_rt_pro_set_tx_agc_offset_hdl(struct oid_par_priv *poid_par_priv)
++{
++#if 0
++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++#ifdef PLATFORM_OS_XP
++ _irqL oldirql;
++#endif
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++
++ u32 txagc;
++
++_func_enter_;
++
++ if (poid_par_priv->type_of_oid != SET_OID)
++ return NDIS_STATUS_NOT_ACCEPTED;
++
++ if (poid_par_priv->information_buf_len < sizeof(u32))
++ return NDIS_STATUS_INVALID_LENGTH;
++
++ txagc = *(u32*)poid_par_priv->information_buf;
++ RT_TRACE(_module_mp_, _drv_info_,
++ ("oid_rt_pro_set_tx_agc_offset_hdl: 0x%08x\n", txagc));
++
++ _irqlevel_changed_(&oldirql, LOWER);
++ SetTxAGCOffset(Adapter, txagc);
++ _irqlevel_changed_(&oldirql, RAISE);
++
++_func_exit_;
++
++ return status;
++#else
++ return 0;
++#endif
++}
++
++NDIS_STATUS oid_rt_pro_set_pkt_test_mode_hdl(struct oid_par_priv *poid_par_priv)
++{
++#if 0
++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
++
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++
++ struct mlme_priv *pmlmepriv = &Adapter->mlmepriv;
++ struct mp_priv *pmppriv = &Adapter->mppriv;
++ u32 type;
++
++_func_enter_;
++
++ if (poid_par_priv->type_of_oid != SET_OID)
++ return NDIS_STATUS_NOT_ACCEPTED;
++
++ if (poid_par_priv->information_buf_len <sizeof(u32))
++ return NDIS_STATUS_INVALID_LENGTH;
++
++ type = *(u32*)poid_par_priv->information_buf;
++
++ if (_LOOPBOOK_MODE_ == type) {
++ pmppriv->mode = type;
++ set_fwstate(pmlmepriv, WIFI_MP_LPBK_STATE); //append txdesc
++ RT_TRACE(_module_mp_, _drv_info_, ("test mode change to loopback mode:0x%08x.\n", get_fwstate(pmlmepriv)));
++ } else if (_2MAC_MODE_ == type){
++ pmppriv->mode = type;
++ _clr_fwstate_(pmlmepriv, WIFI_MP_LPBK_STATE);
++ RT_TRACE(_module_mp_, _drv_info_, ("test mode change to 2mac mode:0x%08x.\n", get_fwstate(pmlmepriv)));
++ } else
++ status = NDIS_STATUS_NOT_ACCEPTED;
++
++_func_exit_;
++
++ return status;
++#else
++ return 0;
++#endif
++}
++
++unsigned int mp_ioctl_xmit_packet_hdl(struct oid_par_priv *poid_par_priv)
++{
++ PMP_XMIT_PARM pparm;
++ PADAPTER padapter;
++ struct mp_priv *pmp_priv;
++ struct pkt_attrib *pattrib;
++
++ RT_TRACE(_module_mp_, _drv_notice_, ("+%s\n", __func__));
++
++ pparm = (PMP_XMIT_PARM)poid_par_priv->information_buf;
++ padapter = (PADAPTER)poid_par_priv->adapter_context;
++ pmp_priv = &padapter->mppriv;
++
++ if (poid_par_priv->type_of_oid == QUERY_OID) {
++ pparm->enable = !pmp_priv->tx.stop;
++ pparm->count = pmp_priv->tx.sended;
++ } else {
++ if (pparm->enable == 0) {
++ pmp_priv->tx.stop = 1;
++ } else if (pmp_priv->tx.stop == 1) {
++ pmp_priv->tx.stop = 0;
++ pmp_priv->tx.count = pparm->count;
++ pmp_priv->tx.payload = pparm->payload_type;
++ pattrib = &pmp_priv->tx.attrib;
++ pattrib->pktlen = pparm->length;
++ _rtw_memcpy(pattrib->dst, pparm->da, ETH_ALEN);
++ SetPacketTx(padapter);
++ } else
++ return NDIS_STATUS_FAILURE;
++ }
++
++ return NDIS_STATUS_SUCCESS;
++}
++
++#if 0
++unsigned int mp_ioctl_xmit_packet_hdl(struct oid_par_priv *poid_par_priv)
++{
++ unsigned char *pframe, *pmp_pkt;
++ struct ethhdr *pethhdr;
++ struct pkt_attrib *pattrib;
++ struct rtw_ieee80211_hdr *pwlanhdr;
++ unsigned short *fctrl;
++ int llc_sz, payload_len;
++ struct mp_xmit_frame *pxframe= NULL;
++ struct mp_xmit_packet *pmp_xmitpkt = (struct mp_xmit_packet*)param;
++ u8 addr3[] = {0x02, 0xE0, 0x4C, 0x87, 0x66, 0x55};
++
++// DBG_871X("+mp_ioctl_xmit_packet_hdl\n");
++
++ pxframe = alloc_mp_xmitframe(&padapter->mppriv);
++ if (pxframe == NULL)
++ {
++ DEBUG_ERR(("Can't alloc pmpframe %d:%s\n", __LINE__, __FILE__));
++ return -1;
++ }
++
++ //mp_xmit_pkt
++ payload_len = pmp_xmitpkt->len - 14;
++ pmp_pkt = (unsigned char*)pmp_xmitpkt->mem;
++ pethhdr = (struct ethhdr *)pmp_pkt;
++
++ //DBG_871X("payload_len=%d, pkt_mem=0x%x\n", pmp_xmitpkt->len, (void*)pmp_xmitpkt->mem);
++
++ //DBG_871X("pxframe=0x%x\n", (void*)pxframe);
++ //DBG_871X("pxframe->mem=0x%x\n", (void*)pxframe->mem);
++
++ //update attribute
++ pattrib = &pxframe->attrib;
++ memset((u8 *)(pattrib), 0, sizeof (struct pkt_attrib));
++ pattrib->pktlen = pmp_xmitpkt->len;
++ pattrib->ether_type = ntohs(pethhdr->h_proto);
++ pattrib->hdrlen = 24;
++ pattrib->nr_frags = 1;
++ pattrib->priority = 0;
++#ifndef CONFIG_MP_LINUX
++ if(IS_MCAST(pethhdr->h_dest))
++ pattrib->mac_id = 4;
++ else
++ pattrib->mac_id = 5;
++#else
++ pattrib->mac_id = 5;
++#endif
++
++ //
++ memset(pxframe->mem, 0 , WLANHDR_OFFSET);
++ pframe = (u8 *)(pxframe->mem) + WLANHDR_OFFSET;
++
++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++ fctrl = &(pwlanhdr->frame_ctl);
++ *(fctrl) = 0;
++ SetFrameSubType(pframe, WIFI_DATA);
++
++ _rtw_memcpy(pwlanhdr->addr1, pethhdr->h_dest, ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr2, pethhdr->h_source, ETH_ALEN);
++
++ _rtw_memcpy(pwlanhdr->addr3, addr3, ETH_ALEN);
++
++ pwlanhdr->seq_ctl = 0;
++ pframe += pattrib->hdrlen;
++
++ llc_sz= rtw_put_snap(pframe, pattrib->ether_type);
++ pframe += llc_sz;
++
++ _rtw_memcpy(pframe, (void*)(pmp_pkt+14), payload_len);
++
++ pattrib->last_txcmdsz = pattrib->hdrlen + llc_sz + payload_len;
++
++ DEBUG_INFO(("issuing mp_xmit_frame, tx_len=%d, ether_type=0x%x\n", pattrib->last_txcmdsz, pattrib->ether_type));
++ xmit_mp_frame(padapter, pxframe);
++
++ return _SUCCESS;
++}
++#endif
++//------------------------------------------------------------------------------
++NDIS_STATUS oid_rt_set_power_down_hdl(struct oid_par_priv *poid_par_priv)
++{
++#ifdef PLATFORM_OS_XP
++ _irqL oldirql;
++#endif
++ u8 bpwrup;
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++#ifdef PLATFORM_LINUX
++#ifdef CONFIG_SDIO_HCI
++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
++#endif
++#endif
++
++_func_enter_;
++
++ if (poid_par_priv->type_of_oid != SET_OID) {
++ status = NDIS_STATUS_NOT_ACCEPTED;
++ return status;
++ }
++
++ RT_TRACE(_module_mp_, _drv_info_,
++ ("\n ===> Setoid_rt_set_power_down_hdl.\n"));
++
++ _irqlevel_changed_(&oldirql, LOWER);
++
++ bpwrup = *(u8 *)poid_par_priv->information_buf;
++ //CALL the power_down function
++#ifdef PLATFORM_LINUX
++#ifdef CONFIG_SDIO_HCI
++ dev_power_down(padapter,bpwrup);
++#endif
++#endif
++ _irqlevel_changed_(&oldirql, RAISE);
++
++ //DEBUG_ERR(("\n <=== Query OID_RT_PRO_READ_REGISTER.
++ // Add:0x%08x Width:%d Value:0x%08x\n",RegRWStruct->offset,RegRWStruct->width,RegRWStruct->value));
++
++_func_exit_;
++
++ return status;
++}
++//------------------------------------------------------------------------------
++NDIS_STATUS oid_rt_get_power_mode_hdl(struct oid_par_priv *poid_par_priv)
++{
++#if 0
++ NDIS_STATUS status = NDIS_STATUS_SUCCESS;
++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
++//#ifdef PLATFORM_OS_XP
++// _irqL oldirql;
++//#endif
++
++_func_enter_;
++
++ if (poid_par_priv->type_of_oid != QUERY_OID) {
++ status = NDIS_STATUS_NOT_ACCEPTED;
++ return status;
++ }
++ if (poid_par_priv->information_buf_len < sizeof(u32)) {
++ status = NDIS_STATUS_INVALID_LENGTH;
++ return status;
++ }
++
++ RT_TRACE(_module_mp_, _drv_info_,
++ ("\n ===> oid_rt_get_power_mode_hdl.\n"));
++
++// _irqlevel_changed_(&oldirql, LOWER);
++ *(int*)poid_par_priv->information_buf = Adapter->registrypriv.low_power ? POWER_LOW : POWER_NORMAL;
++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
++// _irqlevel_changed_(&oldirql, RAISE);
++
++_func_exit_;
++
++ return status;
++#else
++ return 0;
++#endif
++}
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/core/rtw_p2p.c linux-xbian-rpi/drivers/net/wireless/rtl8192cu/core/rtw_p2p.c
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/core/rtw_p2p.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/core/rtw_p2p.c 2015-07-28 01:20:58.305654202 +0200
+@@ -0,0 +1,5293 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#define _RTW_P2P_C_
++
++#include <drv_types.h>
++#include <rtw_p2p.h>
++#include <wifi.h>
++
++#ifdef CONFIG_P2P
++
++int rtw_p2p_is_channel_list_ok( u8 desired_ch, u8* ch_list, u8 ch_cnt )
++{
++ int found = 0, i = 0;
++
++ for( i = 0; i < ch_cnt; i++ )
++ {
++ if ( ch_list[ i ] == desired_ch )
++ {
++ found = 1;
++ break;
++ }
++ }
++ return( found );
++}
++
++int is_any_client_associated(_adapter *padapter)
++{
++ return padapter->stapriv.asoc_list_cnt ? _TRUE : _FALSE;
++}
++
++static u32 go_add_group_info_attr(struct wifidirect_info *pwdinfo, u8 *pbuf)
++{
++ _irqL irqL;
++ _list *phead, *plist;
++ u32 len=0;
++ u16 attr_len = 0;
++ u8 tmplen, *pdata_attr, *pstart, *pcur;
++ struct sta_info *psta = NULL;
++ _adapter *padapter = pwdinfo->padapter;
++ struct sta_priv *pstapriv = &padapter->stapriv;
++
++ DBG_871X("%s\n", __FUNCTION__);
++
++ pdata_attr = rtw_zmalloc(MAX_P2P_IE_LEN);
++
++ pstart = pdata_attr;
++ pcur = pdata_attr;
++
++ _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++ phead = &pstapriv->asoc_list;
++ plist = get_next(phead);
++
++ //look up sta asoc_queue
++ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE)
++ {
++ psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);
++
++ plist = get_next(plist);
++
++
++ if(psta->is_p2p_device)
++ {
++ tmplen = 0;
++
++ pcur++;
++
++ //P2P device address
++ _rtw_memcpy(pcur, psta->dev_addr, ETH_ALEN);
++ pcur += ETH_ALEN;
++
++ //P2P interface address
++ _rtw_memcpy(pcur, psta->hwaddr, ETH_ALEN);
++ pcur += ETH_ALEN;
++
++ *pcur = psta->dev_cap;
++ pcur++;
++
++ //*(u16*)(pcur) = cpu_to_be16(psta->config_methods);
++ RTW_PUT_BE16(pcur, psta->config_methods);
++ pcur += 2;
++
++ _rtw_memcpy(pcur, psta->primary_dev_type, 8);
++ pcur += 8;
++
++ *pcur = psta->num_of_secdev_type;
++ pcur++;
++
++ _rtw_memcpy(pcur, psta->secdev_types_list, psta->num_of_secdev_type*8);
++ pcur += psta->num_of_secdev_type*8;
++
++ if(psta->dev_name_len>0)
++ {
++ //*(u16*)(pcur) = cpu_to_be16( WPS_ATTR_DEVICE_NAME );
++ RTW_PUT_BE16(pcur, WPS_ATTR_DEVICE_NAME);
++ pcur += 2;
++
++ //*(u16*)(pcur) = cpu_to_be16( psta->dev_name_len );
++ RTW_PUT_BE16(pcur, psta->dev_name_len);
++ pcur += 2;
++
++ _rtw_memcpy(pcur, psta->dev_name, psta->dev_name_len);
++ pcur += psta->dev_name_len;
++ }
++
++
++ tmplen = (u8)(pcur-pstart);
++
++ *pstart = (tmplen-1);
++
++ attr_len += tmplen;
++
++ //pstart += tmplen;
++ pstart = pcur;
++
++ }
++
++
++ }
++ _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++
++ if(attr_len>0)
++ {
++ len = rtw_set_p2p_attr_content(pbuf, P2P_ATTR_GROUP_INFO, attr_len, pdata_attr);
++ }
++
++ rtw_mfree(pdata_attr, MAX_P2P_IE_LEN);
++
++ return len;
++
++}
++
++static void issue_group_disc_req(struct wifidirect_info *pwdinfo, u8 *da)
++{
++ struct xmit_frame *pmgntframe;
++ struct pkt_attrib *pattrib;
++ unsigned char *pframe;
++ struct rtw_ieee80211_hdr *pwlanhdr;
++ unsigned short *fctrl;
++ _adapter *padapter = pwdinfo->padapter;
++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++ unsigned char category = RTW_WLAN_CATEGORY_P2P;//P2P action frame
++ u32 p2poui = cpu_to_be32(P2POUI);
++ u8 oui_subtype = P2P_GO_DISC_REQUEST;
++ u8 dialogToken=0;
++
++ DBG_871X("[%s]\n", __FUNCTION__);
++
++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL)
++ {
++ return;
++ }
++
++ //update attribute
++ pattrib = &pmgntframe->attrib;
++ update_mgntframe_attrib(padapter, pattrib);
++
++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++ fctrl = &(pwlanhdr->frame_ctl);
++ *(fctrl) = 0;
++
++ _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr2, pwdinfo->interface_addr, ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr3, pwdinfo->interface_addr, ETH_ALEN);
++
++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
++ pmlmeext->mgnt_seq++;
++ SetFrameSubType(pframe, WIFI_ACTION);
++
++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
++ pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++
++ //Build P2P action frame header
++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
++ pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen));
++ pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen));
++ pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen));
++
++ //there is no IE in this P2P action frame
++
++ pattrib->last_txcmdsz = pattrib->pktlen;
++
++ dump_mgntframe(padapter, pmgntframe);
++
++}
++
++static void issue_p2p_devdisc_resp(struct wifidirect_info *pwdinfo, u8 *da, u8 status, u8 dialogToken)
++{
++ struct xmit_frame *pmgntframe;
++ struct pkt_attrib *pattrib;
++ unsigned char *pframe;
++ struct rtw_ieee80211_hdr *pwlanhdr;
++ unsigned short *fctrl;
++ _adapter *padapter = pwdinfo->padapter;
++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++ unsigned char category = RTW_WLAN_CATEGORY_PUBLIC;
++ u8 action = P2P_PUB_ACTION_ACTION;
++ u32 p2poui = cpu_to_be32(P2POUI);
++ u8 oui_subtype = P2P_DEVDISC_RESP;
++ u8 p2pie[8] = { 0x00 };
++ u32 p2pielen = 0;
++
++ DBG_871X("[%s]\n", __FUNCTION__);
++
++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL)
++ {
++ return;
++ }
++
++ //update attribute
++ pattrib = &pmgntframe->attrib;
++ update_mgntframe_attrib(padapter, pattrib);
++
++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++ fctrl = &(pwlanhdr->frame_ctl);
++ *(fctrl) = 0;
++
++ _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr2, pwdinfo->device_addr, ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr3, pwdinfo->device_addr, ETH_ALEN);
++
++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
++ pmlmeext->mgnt_seq++;
++ SetFrameSubType(pframe, WIFI_ACTION);
++
++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
++ pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++
++ //Build P2P public action frame header
++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
++ pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));
++ pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen));
++ pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen));
++ pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen));
++
++
++ //Build P2P IE
++ // P2P OUI
++ p2pielen = 0;
++ p2pie[ p2pielen++ ] = 0x50;
++ p2pie[ p2pielen++ ] = 0x6F;
++ p2pie[ p2pielen++ ] = 0x9A;
++ p2pie[ p2pielen++ ] = 0x09; // WFA P2P v1.0
++
++ // P2P_ATTR_STATUS
++ p2pielen += rtw_set_p2p_attr_content(&p2pie[p2pielen], P2P_ATTR_STATUS, 1, &status);
++
++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, p2pie, &pattrib->pktlen);
++
++ pattrib->last_txcmdsz = pattrib->pktlen;
++
++ dump_mgntframe(padapter, pmgntframe);
++
++}
++
++static void issue_p2p_provision_resp(struct wifidirect_info *pwdinfo, u8* raddr, u8* frame_body, u16 config_method)
++{
++ _adapter *padapter = pwdinfo->padapter;
++ unsigned char category = RTW_WLAN_CATEGORY_PUBLIC;
++ u8 action = P2P_PUB_ACTION_ACTION;
++ u8 dialogToken = frame_body[7]; // The Dialog Token of provisioning discovery request frame.
++ u32 p2poui = cpu_to_be32(P2POUI);
++ u8 oui_subtype = P2P_PROVISION_DISC_RESP;
++ u8 wpsie[ 100 ] = { 0x00 };
++ u8 wpsielen = 0;
++#ifdef CONFIG_WFD
++ u32 wfdielen = 0;
++#endif //CONFIG_WFD
++
++ struct xmit_frame *pmgntframe;
++ struct pkt_attrib *pattrib;
++ unsigned char *pframe;
++ struct rtw_ieee80211_hdr *pwlanhdr;
++ unsigned short *fctrl;
++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++
++
++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL)
++ {
++ return;
++ }
++
++ //update attribute
++ pattrib = &pmgntframe->attrib;
++ update_mgntframe_attrib(padapter, pattrib);
++
++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++ fctrl = &(pwlanhdr->frame_ctl);
++ *(fctrl) = 0;
++
++ _rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr3, myid(&(padapter->eeprompriv)), ETH_ALEN);
++
++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
++ pmlmeext->mgnt_seq++;
++ SetFrameSubType(pframe, WIFI_ACTION);
++
++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
++ pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++
++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
++ pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));
++ pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen));
++ pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen));
++ pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen));
++
++ wpsielen = 0;
++ // WPS OUI
++ //*(u32*) ( wpsie ) = cpu_to_be32( WPSOUI );
++ RTW_PUT_BE32(wpsie, WPSOUI);
++ wpsielen += 4;
++
++#if 0
++ // WPS version
++ // Type:
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_VER1 );
++ wpsielen += 2;
++
++ // Length:
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0001 );
++ wpsielen += 2;
++
++ // Value:
++ wpsie[wpsielen++] = WPS_VERSION_1; // Version 1.0
++#endif
++
++ // Config Method
++ // Type:
++ //*(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_CONF_METHOD );
++ RTW_PUT_BE16(wpsie + wpsielen, WPS_ATTR_CONF_METHOD);
++ wpsielen += 2;
++
++ // Length:
++ //*(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0002 );
++ RTW_PUT_BE16(wpsie + wpsielen, 0x0002);
++ wpsielen += 2;
++
++ // Value:
++ //*(u16*) ( wpsie + wpsielen ) = cpu_to_be16( config_method );
++ RTW_PUT_BE16(wpsie + wpsielen, config_method);
++ wpsielen += 2;
++
++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen );
++
++#ifdef CONFIG_WFD
++ wfdielen = build_provdisc_resp_wfd_ie(pwdinfo, pframe);
++ pframe += wfdielen;
++ pattrib->pktlen += wfdielen;
++#endif //CONFIG_WFD
++
++ pattrib->last_txcmdsz = pattrib->pktlen;
++
++ dump_mgntframe(padapter, pmgntframe);
++
++ return;
++
++}
++
++static void issue_p2p_presence_resp(struct wifidirect_info *pwdinfo, u8 *da, u8 status, u8 dialogToken)
++{
++ struct xmit_frame *pmgntframe;
++ struct pkt_attrib *pattrib;
++ unsigned char *pframe;
++ struct rtw_ieee80211_hdr *pwlanhdr;
++ unsigned short *fctrl;
++ _adapter *padapter = pwdinfo->padapter;
++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++ unsigned char category = RTW_WLAN_CATEGORY_P2P;//P2P action frame
++ u32 p2poui = cpu_to_be32(P2POUI);
++ u8 oui_subtype = P2P_PRESENCE_RESPONSE;
++ u8 p2pie[ MAX_P2P_IE_LEN] = { 0x00 };
++ u8 noa_attr_content[32] = { 0x00 };
++ u32 p2pielen = 0;
++
++ DBG_871X("[%s]\n", __FUNCTION__);
++
++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL)
++ {
++ return;
++ }
++
++ //update attribute
++ pattrib = &pmgntframe->attrib;
++ update_mgntframe_attrib(padapter, pattrib);
++
++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++ fctrl = &(pwlanhdr->frame_ctl);
++ *(fctrl) = 0;
++
++ _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr2, pwdinfo->interface_addr, ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr3, pwdinfo->interface_addr, ETH_ALEN);
++
++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
++ pmlmeext->mgnt_seq++;
++ SetFrameSubType(pframe, WIFI_ACTION);
++
++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
++ pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++
++ //Build P2P action frame header
++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
++ pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen));
++ pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen));
++ pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen));
++
++
++ //Add P2P IE header
++ // P2P OUI
++ p2pielen = 0;
++ p2pie[ p2pielen++ ] = 0x50;
++ p2pie[ p2pielen++ ] = 0x6F;
++ p2pie[ p2pielen++ ] = 0x9A;
++ p2pie[ p2pielen++ ] = 0x09; // WFA P2P v1.0
++
++ //Add Status attribute in P2P IE
++ p2pielen += rtw_set_p2p_attr_content(&p2pie[p2pielen], P2P_ATTR_STATUS, 1, &status);
++
++ //Add NoA attribute in P2P IE
++ noa_attr_content[0] = 0x1;//index
++ noa_attr_content[1] = 0x0;//CTWindow and OppPS Parameters
++
++ //todo: Notice of Absence Descriptor(s)
++
++ p2pielen += rtw_set_p2p_attr_content(&p2pie[p2pielen], P2P_ATTR_NOA, 2, noa_attr_content);
++
++
++
++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, p2pie, &(pattrib->pktlen));
++
++
++ pattrib->last_txcmdsz = pattrib->pktlen;
++
++ dump_mgntframe(padapter, pmgntframe);
++
++}
++
++u32 build_beacon_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)
++{
++ u8 p2pie[ MAX_P2P_IE_LEN] = { 0x00 };
++ u16 capability=0;
++ u32 len=0, p2pielen = 0;
++
++
++ // P2P OUI
++ p2pielen = 0;
++ p2pie[ p2pielen++ ] = 0x50;
++ p2pie[ p2pielen++ ] = 0x6F;
++ p2pie[ p2pielen++ ] = 0x9A;
++ p2pie[ p2pielen++ ] = 0x09; // WFA P2P v1.0
++
++
++ // According to the P2P Specification, the beacon frame should contain 3 P2P attributes
++ // 1. P2P Capability
++ // 2. P2P Device ID
++ // 3. Notice of Absence ( NOA )
++
++ // P2P Capability ATTR
++ // Type:
++ // Length:
++ // Value:
++ // Device Capability Bitmap, 1 byte
++ // Be able to participate in additional P2P Groups and
++ // support the P2P Invitation Procedure
++ // Group Capability Bitmap, 1 byte
++ capability = P2P_DEVCAP_INVITATION_PROC|P2P_DEVCAP_CLIENT_DISCOVERABILITY;
++ capability |= ((P2P_GRPCAP_GO | P2P_GRPCAP_INTRABSS) << 8);
++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_PROVISIONING_ING))
++ capability |= (P2P_GRPCAP_GROUP_FORMATION<<8);
++
++ capability = cpu_to_le16(capability);
++
++ p2pielen += rtw_set_p2p_attr_content(&p2pie[p2pielen], P2P_ATTR_CAPABILITY, 2, (u8*)&capability);
++
++
++ // P2P Device ID ATTR
++ p2pielen += rtw_set_p2p_attr_content(&p2pie[p2pielen], P2P_ATTR_DEVICE_ID, ETH_ALEN, pwdinfo->device_addr);
++
++
++ // Notice of Absence ATTR
++ // Type:
++ // Length:
++ // Value:
++
++ //go_add_noa_attr(pwdinfo);
++
++
++ pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &len);
++
++
++ return len;
++
++}
++
++#ifdef CONFIG_WFD
++u32 build_beacon_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)
++{
++ u8 wfdie[ MAX_WFD_IE_LEN] = { 0x00 };
++ u32 len=0, wfdielen = 0;
++ _adapter *padapter = pwdinfo->padapter;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct wifi_display_info* pwfd_info = padapter->wdinfo.wfd_info;
++
++ // WFD OUI
++ wfdielen = 0;
++ wfdie[ wfdielen++ ] = 0x50;
++ wfdie[ wfdielen++ ] = 0x6F;
++ wfdie[ wfdielen++ ] = 0x9A;
++ wfdie[ wfdielen++ ] = 0x0A; // WFA WFD v1.0
++
++ // Commented by Albert 20110812
++ // According to the WFD Specification, the beacon frame should contain 4 WFD attributes
++ // 1. WFD Device Information
++ // 2. Associated BSSID
++ // 3. Coupled Sink Information
++
++
++ // WFD Device Information ATTR
++ // Type:
++ wfdie[ wfdielen++ ] = WFD_ATTR_DEVICE_INFO;
++
++ // Length:
++ // Note: In the WFD specification, the size of length field is 2.
++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
++ wfdielen += 2;
++
++ // Value1:
++ // WFD device information
++
++ if ( P2P_ROLE_GO == pwdinfo->role )
++ {
++ if ( is_any_client_associated( pwdinfo->padapter ) )
++ {
++ // WFD primary sink + WiFi Direct mode + WSD (WFD Service Discovery)
++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_WSD );
++ }
++ else
++ {
++ // WFD primary sink + available for WFD session + WiFi Direct mode + WSD (WFD Service Discovery)
++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD );
++ }
++
++ }
++ else
++ {
++ // WFD primary sink + available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery )
++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD );
++ }
++
++ wfdielen += 2;
++
++ // Value2:
++ // Session Management Control Port
++ // Default TCP port for RTSP messages is 554
++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport );
++ wfdielen += 2;
++
++ // Value3:
++ // WFD Device Maximum Throughput
++ // 300Mbps is the maximum throughput
++ RTW_PUT_BE16(wfdie + wfdielen, 300);
++ wfdielen += 2;
++
++ // Associated BSSID ATTR
++ // Type:
++ wfdie[ wfdielen++ ] = WFD_ATTR_ASSOC_BSSID;
++
++ // Length:
++ // Note: In the WFD specification, the size of length field is 2.
++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
++ wfdielen += 2;
++
++ // Value:
++ // Associated BSSID
++ if ( check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE )
++ {
++ _rtw_memcpy( wfdie + wfdielen, &pmlmepriv->assoc_bssid[ 0 ], ETH_ALEN );
++ }
++ else
++ {
++ _rtw_memset( wfdie + wfdielen, 0x00, ETH_ALEN );
++ }
++
++ wfdielen += ETH_ALEN;
++
++ // Coupled Sink Information ATTR
++ // Type:
++ wfdie[ wfdielen++ ] = WFD_ATTR_COUPLED_SINK_INFO;
++
++ // Length:
++ // Note: In the WFD specification, the size of length field is 2.
++ RTW_PUT_BE16(wfdie + wfdielen, 0x0007);
++ wfdielen += 2;
++
++ // Value:
++ // Coupled Sink Status bitmap
++ // Not coupled/available for Coupling
++ wfdie[ wfdielen++ ] = 0;
++ // MAC Addr.
++ wfdie[ wfdielen++ ] = 0;
++ wfdie[ wfdielen++ ] = 0;
++ wfdie[ wfdielen++ ] = 0;
++ wfdie[ wfdielen++ ] = 0;
++ wfdie[ wfdielen++ ] = 0;
++ wfdie[ wfdielen++ ] = 0;
++
++ pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len);
++
++ return len;
++
++}
++
++u32 build_probe_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)
++{
++ u8 wfdie[ MAX_WFD_IE_LEN] = { 0x00 };
++ u32 len=0, wfdielen = 0;
++ _adapter *padapter = pwdinfo->padapter;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct wifi_display_info* pwfd_info = padapter->wdinfo.wfd_info;
++
++ // WFD OUI
++ wfdielen = 0;
++ wfdie[ wfdielen++ ] = 0x50;
++ wfdie[ wfdielen++ ] = 0x6F;
++ wfdie[ wfdielen++ ] = 0x9A;
++ wfdie[ wfdielen++ ] = 0x0A; // WFA WFD v1.0
++
++ // Commented by Albert 20110812
++ // According to the WFD Specification, the probe request frame should contain 4 WFD attributes
++ // 1. WFD Device Information
++ // 2. Associated BSSID
++ // 3. Coupled Sink Information
++
++
++ // WFD Device Information ATTR
++ // Type:
++ wfdie[ wfdielen++ ] = WFD_ATTR_DEVICE_INFO;
++
++ // Length:
++ // Note: In the WFD specification, the size of length field is 2.
++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
++ wfdielen += 2;
++
++ // Value1:
++ // WFD device information
++
++ if ( 1 == pwdinfo->wfd_tdls_enable )
++ {
++ // WFD primary sink + available for WFD session + WiFi TDLS mode + WSC ( WFD Service Discovery )
++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type |
++ WFD_DEVINFO_SESSION_AVAIL |
++ WFD_DEVINFO_WSD |
++ WFD_DEVINFO_PC_TDLS );
++ }
++ else
++ {
++ // WFD primary sink + available for WFD session + WiFi Direct mode + WSC ( WFD Service Discovery )
++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type |
++ WFD_DEVINFO_SESSION_AVAIL |
++ WFD_DEVINFO_WSD );
++ }
++
++ wfdielen += 2;
++
++ // Value2:
++ // Session Management Control Port
++ // Default TCP port for RTSP messages is 554
++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport );
++ wfdielen += 2;
++
++ // Value3:
++ // WFD Device Maximum Throughput
++ // 300Mbps is the maximum throughput
++ RTW_PUT_BE16(wfdie + wfdielen, 300);
++ wfdielen += 2;
++
++ // Associated BSSID ATTR
++ // Type:
++ wfdie[ wfdielen++ ] = WFD_ATTR_ASSOC_BSSID;
++
++ // Length:
++ // Note: In the WFD specification, the size of length field is 2.
++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
++ wfdielen += 2;
++
++ // Value:
++ // Associated BSSID
++ if ( check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE )
++ {
++ _rtw_memcpy( wfdie + wfdielen, &pmlmepriv->assoc_bssid[ 0 ], ETH_ALEN );
++ }
++ else
++ {
++ _rtw_memset( wfdie + wfdielen, 0x00, ETH_ALEN );
++ }
++
++ wfdielen += ETH_ALEN;
++
++ // Coupled Sink Information ATTR
++ // Type:
++ wfdie[ wfdielen++ ] = WFD_ATTR_COUPLED_SINK_INFO;
++
++ // Length:
++ // Note: In the WFD specification, the size of length field is 2.
++ RTW_PUT_BE16(wfdie + wfdielen, 0x0007);
++ wfdielen += 2;
++
++ // Value:
++ // Coupled Sink Status bitmap
++ // Not coupled/available for Coupling
++ wfdie[ wfdielen++ ] = 0;
++ // MAC Addr.
++ wfdie[ wfdielen++ ] = 0;
++ wfdie[ wfdielen++ ] = 0;
++ wfdie[ wfdielen++ ] = 0;
++ wfdie[ wfdielen++ ] = 0;
++ wfdie[ wfdielen++ ] = 0;
++ wfdie[ wfdielen++ ] = 0;
++
++ pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len);
++
++ return len;
++
++}
++
++u32 build_probe_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, u8 tunneled)
++{
++ u8 wfdie[ MAX_WFD_IE_LEN] = { 0x00 };
++ u32 len=0, wfdielen = 0;
++ _adapter *padapter = pwdinfo->padapter;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct wifi_display_info* pwfd_info = padapter->wdinfo.wfd_info;
++
++ // WFD OUI
++ wfdielen = 0;
++ wfdie[ wfdielen++ ] = 0x50;
++ wfdie[ wfdielen++ ] = 0x6F;
++ wfdie[ wfdielen++ ] = 0x9A;
++ wfdie[ wfdielen++ ] = 0x0A; // WFA WFD v1.0
++
++ // Commented by Albert 20110812
++ // According to the WFD Specification, the probe response frame should contain 4 WFD attributes
++ // 1. WFD Device Information
++ // 2. Associated BSSID
++ // 3. Coupled Sink Information
++ // 4. WFD Session Information
++
++
++ // WFD Device Information ATTR
++ // Type:
++ wfdie[ wfdielen++ ] = WFD_ATTR_DEVICE_INFO;
++
++ // Length:
++ // Note: In the WFD specification, the size of length field is 2.
++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
++ wfdielen += 2;
++
++ // Value1:
++ // WFD device information
++ // WFD primary sink + available for WFD session + WiFi Direct mode
++
++ if ( _TRUE == pwdinfo->session_available )
++ {
++ if ( P2P_ROLE_GO == pwdinfo->role )
++ {
++ if ( is_any_client_associated( pwdinfo->padapter ) )
++ {
++ if ( pwdinfo->wfd_tdls_enable )
++ {
++ // TDLS mode + WSD ( WFD Service Discovery )
++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_HDCP_SUPPORT);
++ }
++ else
++ {
++ // WiFi Direct mode + WSD ( WFD Service Discovery )
++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_HDCP_SUPPORT);
++ }
++ }
++ else
++ {
++ if ( pwdinfo->wfd_tdls_enable )
++ {
++ // available for WFD session + TDLS mode + WSD ( WFD Service Discovery )
++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD | WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_HDCP_SUPPORT);
++ }
++ else
++ {
++ // available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery )
++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD | WFD_DEVINFO_HDCP_SUPPORT);
++ }
++ }
++ }
++ else
++ {
++ if ( pwdinfo->wfd_tdls_enable )
++ {
++ // available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery )
++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD | WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_HDCP_SUPPORT);
++ }
++ else
++ {
++
++ // available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery )
++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD | WFD_DEVINFO_HDCP_SUPPORT);
++ }
++ }
++ }
++ else
++ {
++ if ( pwdinfo->wfd_tdls_enable )
++ {
++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_WSD |WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_HDCP_SUPPORT);
++ }
++ else
++ {
++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_HDCP_SUPPORT);
++ }
++
++ }
++
++ wfdielen += 2;
++
++ // Value2:
++ // Session Management Control Port
++ // Default TCP port for RTSP messages is 554
++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport );
++ wfdielen += 2;
++
++ // Value3:
++ // WFD Device Maximum Throughput
++ // 300Mbps is the maximum throughput
++ RTW_PUT_BE16(wfdie + wfdielen, 300);
++ wfdielen += 2;
++
++ // Associated BSSID ATTR
++ // Type:
++ wfdie[ wfdielen++ ] = WFD_ATTR_ASSOC_BSSID;
++
++ // Length:
++ // Note: In the WFD specification, the size of length field is 2.
++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
++ wfdielen += 2;
++
++ // Value:
++ // Associated BSSID
++ if ( check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE )
++ {
++ _rtw_memcpy( wfdie + wfdielen, &pmlmepriv->assoc_bssid[ 0 ], ETH_ALEN );
++ }
++ else
++ {
++ _rtw_memset( wfdie + wfdielen, 0x00, ETH_ALEN );
++ }
++
++ wfdielen += ETH_ALEN;
++
++ // Coupled Sink Information ATTR
++ // Type:
++ wfdie[ wfdielen++ ] = WFD_ATTR_COUPLED_SINK_INFO;
++
++ // Length:
++ // Note: In the WFD specification, the size of length field is 2.
++ RTW_PUT_BE16(wfdie + wfdielen, 0x0007);
++ wfdielen += 2;
++
++ // Value:
++ // Coupled Sink Status bitmap
++ // Not coupled/available for Coupling
++ wfdie[ wfdielen++ ] = 0;
++ // MAC Addr.
++ wfdie[ wfdielen++ ] = 0;
++ wfdie[ wfdielen++ ] = 0;
++ wfdie[ wfdielen++ ] = 0;
++ wfdie[ wfdielen++ ] = 0;
++ wfdie[ wfdielen++ ] = 0;
++ wfdie[ wfdielen++ ] = 0;
++
++ if ( P2P_ROLE_GO == pwdinfo->role )
++ {
++ // WFD Session Information ATTR
++ // Type:
++ wfdie[ wfdielen++ ] = WFD_ATTR_SESSION_INFO;
++
++ // Length:
++ // Note: In the WFD specification, the size of length field is 2.
++ RTW_PUT_BE16(wfdie + wfdielen, 0x0000);
++ wfdielen += 2;
++
++ // Todo: to add the list of WFD device info descriptor in WFD group.
++
++ }
++#ifdef CONFIG_CONCURRENT_MODE
++#ifdef CONFIG_TDLS
++ if ( ( tunneled == 0 ) && ( padapter->pbuddy_adapter->wdinfo.wfd_tdls_enable == 1 ) )
++ {
++ // Alternative MAC Address ATTR
++ // Type:
++ wfdie[ wfdielen++ ] = WFD_ATTR_ALTER_MAC;
++
++ // Length:
++ // Note: In the WFD specification, the size of length field is 2.
++ RTW_PUT_BE16(wfdie + wfdielen, ETH_ALEN );
++ wfdielen += 2;
++
++ // Value:
++ // Alternative MAC Address
++ _rtw_memcpy( wfdie + wfdielen, &padapter->pbuddy_adapter->eeprompriv.mac_addr[ 0 ], ETH_ALEN );
++ // This mac address is used to make the WFD session when TDLS is enable.
++
++ wfdielen += ETH_ALEN;
++ }
++#endif // CONFIG_TDLS
++#endif // CONFIG_CONCURRENT_MODE
++
++ pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len);
++
++ return len;
++
++}
++
++u32 build_assoc_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)
++{
++ u8 wfdie[ MAX_WFD_IE_LEN] = { 0x00 };
++ u32 len=0, wfdielen = 0;
++ _adapter *padapter = NULL;
++ struct mlme_priv *pmlmepriv = NULL;
++ struct wifi_display_info *pwfd_info = NULL;
++
++ // WFD OUI
++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) || rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE))
++ {
++ return 0;
++ }
++
++ padapter = pwdinfo->padapter;
++ pmlmepriv = &padapter->mlmepriv;
++ pwfd_info = padapter->wdinfo.wfd_info;
++
++ wfdielen = 0;
++ wfdie[ wfdielen++ ] = 0x50;
++ wfdie[ wfdielen++ ] = 0x6F;
++ wfdie[ wfdielen++ ] = 0x9A;
++ wfdie[ wfdielen++ ] = 0x0A; // WFA WFD v1.0
++
++ // Commented by Albert 20110812
++ // According to the WFD Specification, the probe request frame should contain 4 WFD attributes
++ // 1. WFD Device Information
++ // 2. Associated BSSID
++ // 3. Coupled Sink Information
++
++
++ // WFD Device Information ATTR
++ // Type:
++ wfdie[ wfdielen++ ] = WFD_ATTR_DEVICE_INFO;
++
++ // Length:
++ // Note: In the WFD specification, the size of length field is 2.
++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
++ wfdielen += 2;
++
++ // Value1:
++ // WFD device information
++ // WFD primary sink + available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery )
++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD );
++ wfdielen += 2;
++
++ // Value2:
++ // Session Management Control Port
++ // Default TCP port for RTSP messages is 554
++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport );
++ wfdielen += 2;
++
++ // Value3:
++ // WFD Device Maximum Throughput
++ // 300Mbps is the maximum throughput
++ RTW_PUT_BE16(wfdie + wfdielen, 300);
++ wfdielen += 2;
++
++ // Associated BSSID ATTR
++ // Type:
++ wfdie[ wfdielen++ ] = WFD_ATTR_ASSOC_BSSID;
++
++ // Length:
++ // Note: In the WFD specification, the size of length field is 2.
++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
++ wfdielen += 2;
++
++ // Value:
++ // Associated BSSID
++ if ( check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE )
++ {
++ _rtw_memcpy( wfdie + wfdielen, &pmlmepriv->assoc_bssid[ 0 ], ETH_ALEN );
++ }
++ else
++ {
++ _rtw_memset( wfdie + wfdielen, 0x00, ETH_ALEN );
++ }
++
++ wfdielen += ETH_ALEN;
++
++ // Coupled Sink Information ATTR
++ // Type:
++ wfdie[ wfdielen++ ] = WFD_ATTR_COUPLED_SINK_INFO;
++
++ // Length:
++ // Note: In the WFD specification, the size of length field is 2.
++ RTW_PUT_BE16(wfdie + wfdielen, 0x0007);
++ wfdielen += 2;
++
++ // Value:
++ // Coupled Sink Status bitmap
++ // Not coupled/available for Coupling
++ wfdie[ wfdielen++ ] = 0;
++ // MAC Addr.
++ wfdie[ wfdielen++ ] = 0;
++ wfdie[ wfdielen++ ] = 0;
++ wfdie[ wfdielen++ ] = 0;
++ wfdie[ wfdielen++ ] = 0;
++ wfdie[ wfdielen++ ] = 0;
++ wfdie[ wfdielen++ ] = 0;
++
++ pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len);
++
++ return len;
++
++}
++
++u32 build_assoc_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)
++{
++ u8 wfdie[ MAX_WFD_IE_LEN] = { 0x00 };
++ u32 len=0, wfdielen = 0;
++ _adapter *padapter = pwdinfo->padapter;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct wifi_display_info* pwfd_info = padapter->wdinfo.wfd_info;
++
++ // WFD OUI
++ wfdielen = 0;
++ wfdie[ wfdielen++ ] = 0x50;
++ wfdie[ wfdielen++ ] = 0x6F;
++ wfdie[ wfdielen++ ] = 0x9A;
++ wfdie[ wfdielen++ ] = 0x0A; // WFA WFD v1.0
++
++ // Commented by Albert 20110812
++ // According to the WFD Specification, the probe request frame should contain 4 WFD attributes
++ // 1. WFD Device Information
++ // 2. Associated BSSID
++ // 3. Coupled Sink Information
++
++
++ // WFD Device Information ATTR
++ // Type:
++ wfdie[ wfdielen++ ] = WFD_ATTR_DEVICE_INFO;
++
++ // Length:
++ // Note: In the WFD specification, the size of length field is 2.
++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
++ wfdielen += 2;
++
++ // Value1:
++ // WFD device information
++ // WFD primary sink + available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery )
++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD );
++ wfdielen += 2;
++
++ // Value2:
++ // Session Management Control Port
++ // Default TCP port for RTSP messages is 554
++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport );
++ wfdielen += 2;
++
++ // Value3:
++ // WFD Device Maximum Throughput
++ // 300Mbps is the maximum throughput
++ RTW_PUT_BE16(wfdie + wfdielen, 300);
++ wfdielen += 2;
++
++ // Associated BSSID ATTR
++ // Type:
++ wfdie[ wfdielen++ ] = WFD_ATTR_ASSOC_BSSID;
++
++ // Length:
++ // Note: In the WFD specification, the size of length field is 2.
++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
++ wfdielen += 2;
++
++ // Value:
++ // Associated BSSID
++ if ( check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE )
++ {
++ _rtw_memcpy( wfdie + wfdielen, &pmlmepriv->assoc_bssid[ 0 ], ETH_ALEN );
++ }
++ else
++ {
++ _rtw_memset( wfdie + wfdielen, 0x00, ETH_ALEN );
++ }
++
++ wfdielen += ETH_ALEN;
++
++ // Coupled Sink Information ATTR
++ // Type:
++ wfdie[ wfdielen++ ] = WFD_ATTR_COUPLED_SINK_INFO;
++
++ // Length:
++ // Note: In the WFD specification, the size of length field is 2.
++ RTW_PUT_BE16(wfdie + wfdielen, 0x0007);
++ wfdielen += 2;
++
++ // Value:
++ // Coupled Sink Status bitmap
++ // Not coupled/available for Coupling
++ wfdie[ wfdielen++ ] = 0;
++ // MAC Addr.
++ wfdie[ wfdielen++ ] = 0;
++ wfdie[ wfdielen++ ] = 0;
++ wfdie[ wfdielen++ ] = 0;
++ wfdie[ wfdielen++ ] = 0;
++ wfdie[ wfdielen++ ] = 0;
++ wfdie[ wfdielen++ ] = 0;
++
++ pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len);
++
++ return len;
++
++}
++
++u32 build_nego_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)
++{
++ u8 wfdie[ MAX_WFD_IE_LEN] = { 0x00 };
++ u32 len=0, wfdielen = 0;
++ _adapter *padapter = pwdinfo->padapter;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct wifi_display_info* pwfd_info = padapter->wdinfo.wfd_info;
++
++ // WFD OUI
++ wfdielen = 0;
++ wfdie[ wfdielen++ ] = 0x50;
++ wfdie[ wfdielen++ ] = 0x6F;
++ wfdie[ wfdielen++ ] = 0x9A;
++ wfdie[ wfdielen++ ] = 0x0A; // WFA WFD v1.0
++
++ // Commented by Albert 20110825
++ // According to the WFD Specification, the negotiation request frame should contain 3 WFD attributes
++ // 1. WFD Device Information
++ // 2. Associated BSSID ( Optional )
++ // 3. Local IP Adress ( Optional )
++
++
++ // WFD Device Information ATTR
++ // Type:
++ wfdie[ wfdielen++ ] = WFD_ATTR_DEVICE_INFO;
++
++ // Length:
++ // Note: In the WFD specification, the size of length field is 2.
++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
++ wfdielen += 2;
++
++ // Value1:
++ // WFD device information
++ // WFD primary sink + WiFi Direct mode + WSD ( WFD Service Discovery ) + WFD Session Available
++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_SESSION_AVAIL);
++ wfdielen += 2;
++
++ // Value2:
++ // Session Management Control Port
++ // Default TCP port for RTSP messages is 554
++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport );
++ wfdielen += 2;
++
++ // Value3:
++ // WFD Device Maximum Throughput
++ // 300Mbps is the maximum throughput
++ RTW_PUT_BE16(wfdie + wfdielen, 300);
++ wfdielen += 2;
++
++ // Associated BSSID ATTR
++ // Type:
++ wfdie[ wfdielen++ ] = WFD_ATTR_ASSOC_BSSID;
++
++ // Length:
++ // Note: In the WFD specification, the size of length field is 2.
++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
++ wfdielen += 2;
++
++ // Value:
++ // Associated BSSID
++ if ( check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE )
++ {
++ _rtw_memcpy( wfdie + wfdielen, &pmlmepriv->assoc_bssid[ 0 ], ETH_ALEN );
++ }
++ else
++ {
++ _rtw_memset( wfdie + wfdielen, 0x00, ETH_ALEN );
++ }
++
++ wfdielen += ETH_ALEN;
++
++ // Coupled Sink Information ATTR
++ // Type:
++ wfdie[ wfdielen++ ] = WFD_ATTR_COUPLED_SINK_INFO;
++
++ // Length:
++ // Note: In the WFD specification, the size of length field is 2.
++ RTW_PUT_BE16(wfdie + wfdielen, 0x0007);
++ wfdielen += 2;
++
++ // Value:
++ // Coupled Sink Status bitmap
++ // Not coupled/available for Coupling
++ wfdie[ wfdielen++ ] = 0;
++ // MAC Addr.
++ wfdie[ wfdielen++ ] = 0;
++ wfdie[ wfdielen++ ] = 0;
++ wfdie[ wfdielen++ ] = 0;
++ wfdie[ wfdielen++ ] = 0;
++ wfdie[ wfdielen++ ] = 0;
++ wfdie[ wfdielen++ ] = 0;
++
++ pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len);
++
++ return len;
++
++}
++
++u32 build_nego_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)
++{
++ u8 wfdie[ MAX_WFD_IE_LEN] = { 0x00 };
++ u32 len=0, wfdielen = 0;
++ _adapter *padapter = pwdinfo->padapter;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct wifi_display_info* pwfd_info = padapter->wdinfo.wfd_info;
++
++ // WFD OUI
++ wfdielen = 0;
++ wfdie[ wfdielen++ ] = 0x50;
++ wfdie[ wfdielen++ ] = 0x6F;
++ wfdie[ wfdielen++ ] = 0x9A;
++ wfdie[ wfdielen++ ] = 0x0A; // WFA WFD v1.0
++
++ // Commented by Albert 20110825
++ // According to the WFD Specification, the negotiation request frame should contain 3 WFD attributes
++ // 1. WFD Device Information
++ // 2. Associated BSSID ( Optional )
++ // 3. Local IP Adress ( Optional )
++
++
++ // WFD Device Information ATTR
++ // Type:
++ wfdie[ wfdielen++ ] = WFD_ATTR_DEVICE_INFO;
++
++ // Length:
++ // Note: In the WFD specification, the size of length field is 2.
++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
++ wfdielen += 2;
++
++ // Value1:
++ // WFD device information
++ // WFD primary sink + WiFi Direct mode + WSD ( WFD Service Discovery ) + WFD Session Available
++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_SESSION_AVAIL);
++ wfdielen += 2;
++
++ // Value2:
++ // Session Management Control Port
++ // Default TCP port for RTSP messages is 554
++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport );
++ wfdielen += 2;
++
++ // Value3:
++ // WFD Device Maximum Throughput
++ // 300Mbps is the maximum throughput
++ RTW_PUT_BE16(wfdie + wfdielen, 300);
++ wfdielen += 2;
++
++ // Associated BSSID ATTR
++ // Type:
++ wfdie[ wfdielen++ ] = WFD_ATTR_ASSOC_BSSID;
++
++ // Length:
++ // Note: In the WFD specification, the size of length field is 2.
++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
++ wfdielen += 2;
++
++ // Value:
++ // Associated BSSID
++ if ( check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE )
++ {
++ _rtw_memcpy( wfdie + wfdielen, &pmlmepriv->assoc_bssid[ 0 ], ETH_ALEN );
++ }
++ else
++ {
++ _rtw_memset( wfdie + wfdielen, 0x00, ETH_ALEN );
++ }
++
++ wfdielen += ETH_ALEN;
++
++ // Coupled Sink Information ATTR
++ // Type:
++ wfdie[ wfdielen++ ] = WFD_ATTR_COUPLED_SINK_INFO;
++
++ // Length:
++ // Note: In the WFD specification, the size of length field is 2.
++ RTW_PUT_BE16(wfdie + wfdielen, 0x0007);
++ wfdielen += 2;
++
++ // Value:
++ // Coupled Sink Status bitmap
++ // Not coupled/available for Coupling
++ wfdie[ wfdielen++ ] = 0;
++ // MAC Addr.
++ wfdie[ wfdielen++ ] = 0;
++ wfdie[ wfdielen++ ] = 0;
++ wfdie[ wfdielen++ ] = 0;
++ wfdie[ wfdielen++ ] = 0;
++ wfdie[ wfdielen++ ] = 0;
++ wfdie[ wfdielen++ ] = 0;
++
++
++ pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len);
++
++ return len;
++
++}
++
++u32 build_nego_confirm_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)
++{
++ u8 wfdie[ MAX_WFD_IE_LEN] = { 0x00 };
++ u32 len=0, wfdielen = 0;
++ _adapter *padapter = pwdinfo->padapter;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct wifi_display_info* pwfd_info = padapter->wdinfo.wfd_info;
++
++ // WFD OUI
++ wfdielen = 0;
++ wfdie[ wfdielen++ ] = 0x50;
++ wfdie[ wfdielen++ ] = 0x6F;
++ wfdie[ wfdielen++ ] = 0x9A;
++ wfdie[ wfdielen++ ] = 0x0A; // WFA WFD v1.0
++
++ // Commented by Albert 20110825
++ // According to the WFD Specification, the negotiation request frame should contain 3 WFD attributes
++ // 1. WFD Device Information
++ // 2. Associated BSSID ( Optional )
++ // 3. Local IP Adress ( Optional )
++
++
++ // WFD Device Information ATTR
++ // Type:
++ wfdie[ wfdielen++ ] = WFD_ATTR_DEVICE_INFO;
++
++ // Length:
++ // Note: In the WFD specification, the size of length field is 2.
++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
++ wfdielen += 2;
++
++ // Value1:
++ // WFD device information
++ // WFD primary sink + WiFi Direct mode + WSD ( WFD Service Discovery ) + WFD Session Available
++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_SESSION_AVAIL);
++ wfdielen += 2;
++
++ // Value2:
++ // Session Management Control Port
++ // Default TCP port for RTSP messages is 554
++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport );
++ wfdielen += 2;
++
++ // Value3:
++ // WFD Device Maximum Throughput
++ // 300Mbps is the maximum throughput
++ RTW_PUT_BE16(wfdie + wfdielen, 300);
++ wfdielen += 2;
++
++ // Associated BSSID ATTR
++ // Type:
++ wfdie[ wfdielen++ ] = WFD_ATTR_ASSOC_BSSID;
++
++ // Length:
++ // Note: In the WFD specification, the size of length field is 2.
++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
++ wfdielen += 2;
++
++ // Value:
++ // Associated BSSID
++ if ( check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE )
++ {
++ _rtw_memcpy( wfdie + wfdielen, &pmlmepriv->assoc_bssid[ 0 ], ETH_ALEN );
++ }
++ else
++ {
++ _rtw_memset( wfdie + wfdielen, 0x00, ETH_ALEN );
++ }
++
++ wfdielen += ETH_ALEN;
++
++ // Coupled Sink Information ATTR
++ // Type:
++ wfdie[ wfdielen++ ] = WFD_ATTR_COUPLED_SINK_INFO;
++
++ // Length:
++ // Note: In the WFD specification, the size of length field is 2.
++ RTW_PUT_BE16(wfdie + wfdielen, 0x0007);
++ wfdielen += 2;
++
++ // Value:
++ // Coupled Sink Status bitmap
++ // Not coupled/available for Coupling
++ wfdie[ wfdielen++ ] = 0;
++ // MAC Addr.
++ wfdie[ wfdielen++ ] = 0;
++ wfdie[ wfdielen++ ] = 0;
++ wfdie[ wfdielen++ ] = 0;
++ wfdie[ wfdielen++ ] = 0;
++ wfdie[ wfdielen++ ] = 0;
++ wfdie[ wfdielen++ ] = 0;
++
++
++ pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len);
++
++ return len;
++
++}
++
++u32 build_invitation_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)
++{
++ u8 wfdie[ MAX_WFD_IE_LEN] = { 0x00 };
++ u32 len=0, wfdielen = 0;
++ _adapter *padapter = pwdinfo->padapter;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct wifi_display_info* pwfd_info = padapter->wdinfo.wfd_info;
++
++ // WFD OUI
++ wfdielen = 0;
++ wfdie[ wfdielen++ ] = 0x50;
++ wfdie[ wfdielen++ ] = 0x6F;
++ wfdie[ wfdielen++ ] = 0x9A;
++ wfdie[ wfdielen++ ] = 0x0A; // WFA WFD v1.0
++
++ // Commented by Albert 20110825
++ // According to the WFD Specification, the provision discovery request frame should contain 3 WFD attributes
++ // 1. WFD Device Information
++ // 2. Associated BSSID ( Optional )
++ // 3. Local IP Adress ( Optional )
++
++
++ // WFD Device Information ATTR
++ // Type:
++ wfdie[ wfdielen++ ] = WFD_ATTR_DEVICE_INFO;
++
++ // Length:
++ // Note: In the WFD specification, the size of length field is 2.
++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
++ wfdielen += 2;
++
++ // Value1:
++ // WFD device information
++ // WFD primary sink + available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery )
++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD );
++ wfdielen += 2;
++
++ // Value2:
++ // Session Management Control Port
++ // Default TCP port for RTSP messages is 554
++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport );
++ wfdielen += 2;
++
++ // Value3:
++ // WFD Device Maximum Throughput
++ // 300Mbps is the maximum throughput
++ RTW_PUT_BE16(wfdie + wfdielen, 300);
++ wfdielen += 2;
++
++ // Associated BSSID ATTR
++ // Type:
++ wfdie[ wfdielen++ ] = WFD_ATTR_ASSOC_BSSID;
++
++ // Length:
++ // Note: In the WFD specification, the size of length field is 2.
++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
++ wfdielen += 2;
++
++ // Value:
++ // Associated BSSID
++ if ( check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE )
++ {
++ _rtw_memcpy( wfdie + wfdielen, &pmlmepriv->assoc_bssid[ 0 ], ETH_ALEN );
++ }
++ else
++ {
++ _rtw_memset( wfdie + wfdielen, 0x00, ETH_ALEN );
++ }
++
++ wfdielen += ETH_ALEN;
++
++ // Coupled Sink Information ATTR
++ // Type:
++ wfdie[ wfdielen++ ] = WFD_ATTR_COUPLED_SINK_INFO;
++
++ // Length:
++ // Note: In the WFD specification, the size of length field is 2.
++ RTW_PUT_BE16(wfdie + wfdielen, 0x0007);
++ wfdielen += 2;
++
++ // Value:
++ // Coupled Sink Status bitmap
++ // Not coupled/available for Coupling
++ wfdie[ wfdielen++ ] = 0;
++ // MAC Addr.
++ wfdie[ wfdielen++ ] = 0;
++ wfdie[ wfdielen++ ] = 0;
++ wfdie[ wfdielen++ ] = 0;
++ wfdie[ wfdielen++ ] = 0;
++ wfdie[ wfdielen++ ] = 0;
++ wfdie[ wfdielen++ ] = 0;
++
++ if ( P2P_ROLE_GO == pwdinfo->role )
++ {
++ // WFD Session Information ATTR
++ // Type:
++ wfdie[ wfdielen++ ] = WFD_ATTR_SESSION_INFO;
++
++ // Length:
++ // Note: In the WFD specification, the size of length field is 2.
++ RTW_PUT_BE16(wfdie + wfdielen, 0x0000);
++ wfdielen += 2;
++
++ // Todo: to add the list of WFD device info descriptor in WFD group.
++
++ }
++
++ pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len);
++
++ return len;
++
++}
++
++u32 build_invitation_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)
++{
++ u8 wfdie[ MAX_WFD_IE_LEN] = { 0x00 };
++ u32 len=0, wfdielen = 0;
++ _adapter *padapter = pwdinfo->padapter;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct wifi_display_info* pwfd_info = padapter->wdinfo.wfd_info;
++
++ // WFD OUI
++ wfdielen = 0;
++ wfdie[ wfdielen++ ] = 0x50;
++ wfdie[ wfdielen++ ] = 0x6F;
++ wfdie[ wfdielen++ ] = 0x9A;
++ wfdie[ wfdielen++ ] = 0x0A; // WFA WFD v1.0
++
++ // Commented by Albert 20110825
++ // According to the WFD Specification, the provision discovery request frame should contain 3 WFD attributes
++ // 1. WFD Device Information
++ // 2. Associated BSSID ( Optional )
++ // 3. Local IP Adress ( Optional )
++
++
++ // WFD Device Information ATTR
++ // Type:
++ wfdie[ wfdielen++ ] = WFD_ATTR_DEVICE_INFO;
++
++ // Length:
++ // Note: In the WFD specification, the size of length field is 2.
++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
++ wfdielen += 2;
++
++ // Value1:
++ // WFD device information
++ // WFD primary sink + available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery )
++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD );
++ wfdielen += 2;
++
++ // Value2:
++ // Session Management Control Port
++ // Default TCP port for RTSP messages is 554
++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport );
++ wfdielen += 2;
++
++ // Value3:
++ // WFD Device Maximum Throughput
++ // 300Mbps is the maximum throughput
++ RTW_PUT_BE16(wfdie + wfdielen, 300);
++ wfdielen += 2;
++
++ // Associated BSSID ATTR
++ // Type:
++ wfdie[ wfdielen++ ] = WFD_ATTR_ASSOC_BSSID;
++
++ // Length:
++ // Note: In the WFD specification, the size of length field is 2.
++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
++ wfdielen += 2;
++
++ // Value:
++ // Associated BSSID
++ if ( check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE )
++ {
++ _rtw_memcpy( wfdie + wfdielen, &pmlmepriv->assoc_bssid[ 0 ], ETH_ALEN );
++ }
++ else
++ {
++ _rtw_memset( wfdie + wfdielen, 0x00, ETH_ALEN );
++ }
++
++ wfdielen += ETH_ALEN;
++
++ // Coupled Sink Information ATTR
++ // Type:
++ wfdie[ wfdielen++ ] = WFD_ATTR_COUPLED_SINK_INFO;
++
++ // Length:
++ // Note: In the WFD specification, the size of length field is 2.
++ RTW_PUT_BE16(wfdie + wfdielen, 0x0007);
++ wfdielen += 2;
++
++ // Value:
++ // Coupled Sink Status bitmap
++ // Not coupled/available for Coupling
++ wfdie[ wfdielen++ ] = 0;
++ // MAC Addr.
++ wfdie[ wfdielen++ ] = 0;
++ wfdie[ wfdielen++ ] = 0;
++ wfdie[ wfdielen++ ] = 0;
++ wfdie[ wfdielen++ ] = 0;
++ wfdie[ wfdielen++ ] = 0;
++ wfdie[ wfdielen++ ] = 0;
++
++ if ( P2P_ROLE_GO == pwdinfo->role )
++ {
++ // WFD Session Information ATTR
++ // Type:
++ wfdie[ wfdielen++ ] = WFD_ATTR_SESSION_INFO;
++
++ // Length:
++ // Note: In the WFD specification, the size of length field is 2.
++ RTW_PUT_BE16(wfdie + wfdielen, 0x0000);
++ wfdielen += 2;
++
++ // Todo: to add the list of WFD device info descriptor in WFD group.
++
++ }
++
++ pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len);
++
++ return len;
++
++}
++
++u32 build_provdisc_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)
++{
++ u8 wfdie[ MAX_WFD_IE_LEN] = { 0x00 };
++ u32 len=0, wfdielen = 0;
++ _adapter *padapter = pwdinfo->padapter;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct wifi_display_info* pwfd_info = padapter->wdinfo.wfd_info;
++
++ // WFD OUI
++ wfdielen = 0;
++ wfdie[ wfdielen++ ] = 0x50;
++ wfdie[ wfdielen++ ] = 0x6F;
++ wfdie[ wfdielen++ ] = 0x9A;
++ wfdie[ wfdielen++ ] = 0x0A; // WFA WFD v1.0
++
++ // Commented by Albert 20110825
++ // According to the WFD Specification, the provision discovery request frame should contain 3 WFD attributes
++ // 1. WFD Device Information
++ // 2. Associated BSSID ( Optional )
++ // 3. Local IP Adress ( Optional )
++
++
++ // WFD Device Information ATTR
++ // Type:
++ wfdie[ wfdielen++ ] = WFD_ATTR_DEVICE_INFO;
++
++ // Length:
++ // Note: In the WFD specification, the size of length field is 2.
++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
++ wfdielen += 2;
++
++ // Value1:
++ // WFD device information
++ // WFD primary sink + available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery )
++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD );
++ wfdielen += 2;
++
++ // Value2:
++ // Session Management Control Port
++ // Default TCP port for RTSP messages is 554
++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport );
++ wfdielen += 2;
++
++ // Value3:
++ // WFD Device Maximum Throughput
++ // 300Mbps is the maximum throughput
++ RTW_PUT_BE16(wfdie + wfdielen, 300);
++ wfdielen += 2;
++
++ // Associated BSSID ATTR
++ // Type:
++ wfdie[ wfdielen++ ] = WFD_ATTR_ASSOC_BSSID;
++
++ // Length:
++ // Note: In the WFD specification, the size of length field is 2.
++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
++ wfdielen += 2;
++
++ // Value:
++ // Associated BSSID
++ if ( check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE )
++ {
++ _rtw_memcpy( wfdie + wfdielen, &pmlmepriv->assoc_bssid[ 0 ], ETH_ALEN );
++ }
++ else
++ {
++ _rtw_memset( wfdie + wfdielen, 0x00, ETH_ALEN );
++ }
++
++ wfdielen += ETH_ALEN;
++
++ // Coupled Sink Information ATTR
++ // Type:
++ wfdie[ wfdielen++ ] = WFD_ATTR_COUPLED_SINK_INFO;
++
++ // Length:
++ // Note: In the WFD specification, the size of length field is 2.
++ RTW_PUT_BE16(wfdie + wfdielen, 0x0007);
++ wfdielen += 2;
++
++ // Value:
++ // Coupled Sink Status bitmap
++ // Not coupled/available for Coupling
++ wfdie[ wfdielen++ ] = 0;
++ // MAC Addr.
++ wfdie[ wfdielen++ ] = 0;
++ wfdie[ wfdielen++ ] = 0;
++ wfdie[ wfdielen++ ] = 0;
++ wfdie[ wfdielen++ ] = 0;
++ wfdie[ wfdielen++ ] = 0;
++ wfdie[ wfdielen++ ] = 0;
++
++
++ pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len);
++
++ return len;
++
++}
++
++u32 build_provdisc_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)
++{
++ u8 wfdie[ MAX_WFD_IE_LEN] = { 0x00 };
++ u32 len=0, wfdielen = 0;
++ _adapter *padapter = pwdinfo->padapter;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct wifi_display_info* pwfd_info = padapter->wdinfo.wfd_info;
++
++ // WFD OUI
++ wfdielen = 0;
++ wfdie[ wfdielen++ ] = 0x50;
++ wfdie[ wfdielen++ ] = 0x6F;
++ wfdie[ wfdielen++ ] = 0x9A;
++ wfdie[ wfdielen++ ] = 0x0A; // WFA WFD v1.0
++
++ // Commented by Albert 20110825
++ // According to the WFD Specification, the provision discovery response frame should contain 3 WFD attributes
++ // 1. WFD Device Information
++ // 2. Associated BSSID ( Optional )
++ // 3. Local IP Adress ( Optional )
++
++
++ // WFD Device Information ATTR
++ // Type:
++ wfdie[ wfdielen++ ] = WFD_ATTR_DEVICE_INFO;
++
++ // Length:
++ // Note: In the WFD specification, the size of length field is 2.
++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
++ wfdielen += 2;
++
++ // Value1:
++ // WFD device information
++ // WFD primary sink + available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery )
++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD );
++ wfdielen += 2;
++
++ // Value2:
++ // Session Management Control Port
++ // Default TCP port for RTSP messages is 554
++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport );
++ wfdielen += 2;
++
++ // Value3:
++ // WFD Device Maximum Throughput
++ // 300Mbps is the maximum throughput
++ RTW_PUT_BE16(wfdie + wfdielen, 300);
++ wfdielen += 2;
++
++ // Associated BSSID ATTR
++ // Type:
++ wfdie[ wfdielen++ ] = WFD_ATTR_ASSOC_BSSID;
++
++ // Length:
++ // Note: In the WFD specification, the size of length field is 2.
++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
++ wfdielen += 2;
++
++ // Value:
++ // Associated BSSID
++ if ( check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE )
++ {
++ _rtw_memcpy( wfdie + wfdielen, &pmlmepriv->assoc_bssid[ 0 ], ETH_ALEN );
++ }
++ else
++ {
++ _rtw_memset( wfdie + wfdielen, 0x00, ETH_ALEN );
++ }
++
++ wfdielen += ETH_ALEN;
++
++ // Coupled Sink Information ATTR
++ // Type:
++ wfdie[ wfdielen++ ] = WFD_ATTR_COUPLED_SINK_INFO;
++
++ // Length:
++ // Note: In the WFD specification, the size of length field is 2.
++ RTW_PUT_BE16(wfdie + wfdielen, 0x0007);
++ wfdielen += 2;
++
++ // Value:
++ // Coupled Sink Status bitmap
++ // Not coupled/available for Coupling
++ wfdie[ wfdielen++ ] = 0;
++ // MAC Addr.
++ wfdie[ wfdielen++ ] = 0;
++ wfdie[ wfdielen++ ] = 0;
++ wfdie[ wfdielen++ ] = 0;
++ wfdie[ wfdielen++ ] = 0;
++ wfdie[ wfdielen++ ] = 0;
++ wfdie[ wfdielen++ ] = 0;
++
++ pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len);
++
++ return len;
++
++}
++
++#endif //CONFIG_WFD
++
++u32 build_probe_resp_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)
++{
++ u8 p2pie[ MAX_P2P_IE_LEN] = { 0x00 };
++ u32 len=0, p2pielen = 0;
++#ifdef CONFIG_INTEL_WIDI
++ struct mlme_priv *pmlmepriv = &(pwdinfo->padapter->mlmepriv);
++ u8 zero_array_check[L2SDTA_SERVICE_VE_LEN] = { 0x00 };
++ u8 widi_version = 0, i = 0;
++
++ if( _rtw_memcmp( pmlmepriv->sa_ext, zero_array_check, L2SDTA_SERVICE_VE_LEN ) == _FALSE )
++ {
++ widi_version = 35;
++ }
++ else if( pmlmepriv->num_p2p_sdt != 0 )
++ {
++ widi_version = 40;
++ }
++#endif //CONFIG_INTEL_WIDI
++
++ // P2P OUI
++ p2pielen = 0;
++ p2pie[ p2pielen++ ] = 0x50;
++ p2pie[ p2pielen++ ] = 0x6F;
++ p2pie[ p2pielen++ ] = 0x9A;
++ p2pie[ p2pielen++ ] = 0x09; // WFA P2P v1.0
++
++ // Commented by Albert 20100907
++ // According to the P2P Specification, the probe response frame should contain 5 P2P attributes
++ // 1. P2P Capability
++ // 2. Extended Listen Timing
++ // 3. Notice of Absence ( NOA ) ( Only GO needs this )
++ // 4. Device Info
++ // 5. Group Info ( Only GO need this )
++
++ // P2P Capability ATTR
++ // Type:
++ p2pie[ p2pielen++ ] = P2P_ATTR_CAPABILITY;
++
++ // Length:
++ //*(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0002 );
++ RTW_PUT_LE16(p2pie + p2pielen, 0x0002);
++ p2pielen += 2;
++
++ // Value:
++ // Device Capability Bitmap, 1 byte
++ p2pie[ p2pielen++ ] = DMP_P2P_DEVCAP_SUPPORT;
++
++ // Group Capability Bitmap, 1 byte
++ if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO))
++ {
++ p2pie[ p2pielen ] = (P2P_GRPCAP_GO | P2P_GRPCAP_INTRABSS);
++
++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_PROVISIONING_ING))
++ p2pie[ p2pielen ] |= P2P_GRPCAP_GROUP_FORMATION;
++
++ p2pielen++;
++ }
++ else if ( rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE) )
++ {
++ // Group Capability Bitmap, 1 byte
++ if ( pwdinfo->persistent_supported )
++ p2pie[ p2pielen++ ] = P2P_GRPCAP_PERSISTENT_GROUP | DMP_P2P_GRPCAP_SUPPORT;
++ else
++ p2pie[ p2pielen++ ] = DMP_P2P_GRPCAP_SUPPORT;
++
++ }
++
++ // Extended Listen Timing ATTR
++ // Type:
++ p2pie[ p2pielen++ ] = P2P_ATTR_EX_LISTEN_TIMING;
++
++ // Length:
++ //*(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0004 );
++ RTW_PUT_LE16(p2pie + p2pielen, 0x0004);
++ p2pielen += 2;
++
++ // Value:
++ // Availability Period
++ //*(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0xFFFF );
++ RTW_PUT_LE16(p2pie + p2pielen, 0xFFFF);
++ p2pielen += 2;
++
++ // Availability Interval
++ //*(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0xFFFF );
++ RTW_PUT_LE16(p2pie + p2pielen, 0xFFFF);
++ p2pielen += 2;
++
++
++ // Notice of Absence ATTR
++ // Type:
++ // Length:
++ // Value:
++ if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO))
++ {
++ //go_add_noa_attr(pwdinfo);
++ }
++
++ // Device Info ATTR
++ // Type:
++ p2pie[ p2pielen++ ] = P2P_ATTR_DEVICE_INFO;
++
++ // Length:
++ // 21 -> P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes)
++ // + NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes)
++ //*(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 21 + pwdinfo->device_name_len );
++#ifdef CONFIG_INTEL_WIDI
++ if( widi_version == 35 )
++ {
++ RTW_PUT_LE16(p2pie + p2pielen, 21 + 8 + pwdinfo->device_name_len);
++ }
++ else if( widi_version == 40 )
++ {
++ RTW_PUT_LE16(p2pie + p2pielen, 21 + 8 * pmlmepriv->num_p2p_sdt + pwdinfo->device_name_len);
++ }
++ else
++#endif //CONFIG_INTEL_WIDI
++ RTW_PUT_LE16(p2pie + p2pielen, 21 + pwdinfo->device_name_len);
++ p2pielen += 2;
++
++ // Value:
++ // P2P Device Address
++ _rtw_memcpy( p2pie + p2pielen, pwdinfo->device_addr, ETH_ALEN );
++ p2pielen += ETH_ALEN;
++
++ // Config Method
++ // This field should be big endian. Noted by P2P specification.
++ //*(u16*) ( p2pie + p2pielen ) = cpu_to_be16( pwdinfo->supported_wps_cm );
++ RTW_PUT_BE16(p2pie + p2pielen, pwdinfo->supported_wps_cm);
++ p2pielen += 2;
++
++#ifdef CONFIG_INTEL_WIDI
++ if( widi_version == 40 )
++ {
++ // Primary Device Type
++ // Category ID
++ //*(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_CID_MULIT_MEDIA );
++ RTW_PUT_BE16(p2pie + p2pielen, pmlmepriv->p2p_pdt_cid );
++ p2pielen += 2;
++
++ // OUI
++ //*(u32*) ( p2pie + p2pielen ) = cpu_to_be32( WPSOUI );
++ RTW_PUT_BE32(p2pie + p2pielen, WPSOUI);
++ p2pielen += 4;
++
++ // Sub Category ID
++ //*(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_SCID_MEDIA_SERVER );
++ RTW_PUT_BE16(p2pie + p2pielen, pmlmepriv->p2p_pdt_scid);
++ p2pielen += 2;
++ }
++ else
++#endif //CONFIG_INTEL_WIDI
++ {
++ // Primary Device Type
++ // Category ID
++ //*(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_CID_MULIT_MEDIA );
++ RTW_PUT_BE16(p2pie + p2pielen, WPS_PDT_CID_MULIT_MEDIA);
++ p2pielen += 2;
++
++ // OUI
++ //*(u32*) ( p2pie + p2pielen ) = cpu_to_be32( WPSOUI );
++ RTW_PUT_BE32(p2pie + p2pielen, WPSOUI);
++ p2pielen += 4;
++
++ // Sub Category ID
++ //*(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_SCID_MEDIA_SERVER );
++ RTW_PUT_BE16(p2pie + p2pielen, WPS_PDT_SCID_MEDIA_SERVER);
++ p2pielen += 2;
++ }
++
++ // Number of Secondary Device Types
++#ifdef CONFIG_INTEL_WIDI
++ if( widi_version == 35 )
++ {
++ p2pie[ p2pielen++ ] = 0x01;
++
++ RTW_PUT_BE16(p2pie + p2pielen, WPS_PDT_CID_DISPLAYS);
++ p2pielen += 2;
++
++ RTW_PUT_BE32(p2pie + p2pielen, INTEL_DEV_TYPE_OUI);
++ p2pielen += 4;
++
++ RTW_PUT_BE16(p2pie + p2pielen, P2P_SCID_WIDI_CONSUMER_SINK);
++ p2pielen += 2;
++ }
++ else if( widi_version == 40 )
++ {
++ p2pie[ p2pielen++ ] = pmlmepriv->num_p2p_sdt;
++ for( ; i < pmlmepriv->num_p2p_sdt; i++ )
++ {
++ RTW_PUT_BE16(p2pie + p2pielen, pmlmepriv->p2p_sdt_cid[i]);
++ p2pielen += 2;
++
++ RTW_PUT_BE32(p2pie + p2pielen, INTEL_DEV_TYPE_OUI);
++ p2pielen += 4;
++
++ RTW_PUT_BE16(p2pie + p2pielen, pmlmepriv->p2p_sdt_scid[i]);
++ p2pielen += 2;
++ }
++ }
++ else
++#endif //CONFIG_INTEL_WIDI
++ p2pie[ p2pielen++ ] = 0x00; // No Secondary Device Type List
++
++ // Device Name
++ // Type:
++ //*(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_ATTR_DEVICE_NAME );
++ RTW_PUT_BE16(p2pie + p2pielen, WPS_ATTR_DEVICE_NAME);
++ p2pielen += 2;
++
++ // Length:
++ //*(u16*) ( p2pie + p2pielen ) = cpu_to_be16( pwdinfo->device_name_len );
++ RTW_PUT_BE16(p2pie + p2pielen, pwdinfo->device_name_len);
++ p2pielen += 2;
++
++ // Value:
++ _rtw_memcpy( p2pie + p2pielen, pwdinfo->device_name, pwdinfo->device_name_len );
++ p2pielen += pwdinfo->device_name_len;
++
++ // Group Info ATTR
++ // Type:
++ // Length:
++ // Value:
++ if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO))
++ {
++ p2pielen += go_add_group_info_attr(pwdinfo, p2pie + p2pielen);
++ }
++
++
++ pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &len);
++
++
++ return len;
++
++}
++
++u32 build_prov_disc_request_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, u8* pssid, u8 ussidlen, u8* pdev_raddr )
++{
++ u8 p2pie[ MAX_P2P_IE_LEN] = { 0x00 };
++ u32 len=0, p2pielen = 0;
++
++ // P2P OUI
++ p2pielen = 0;
++ p2pie[ p2pielen++ ] = 0x50;
++ p2pie[ p2pielen++ ] = 0x6F;
++ p2pie[ p2pielen++ ] = 0x9A;
++ p2pie[ p2pielen++ ] = 0x09; // WFA P2P v1.0
++
++ // Commented by Albert 20110301
++ // According to the P2P Specification, the provision discovery request frame should contain 3 P2P attributes
++ // 1. P2P Capability
++ // 2. Device Info
++ // 3. Group ID ( When joining an operating P2P Group )
++
++ // P2P Capability ATTR
++ // Type:
++ p2pie[ p2pielen++ ] = P2P_ATTR_CAPABILITY;
++
++ // Length:
++ //*(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0002 );
++ RTW_PUT_LE16(p2pie + p2pielen, 0x0002);
++ p2pielen += 2;
++
++ // Value:
++ // Device Capability Bitmap, 1 byte
++ p2pie[ p2pielen++ ] = DMP_P2P_DEVCAP_SUPPORT;
++
++ // Group Capability Bitmap, 1 byte
++ if ( pwdinfo->persistent_supported )
++ p2pie[ p2pielen++ ] = P2P_GRPCAP_PERSISTENT_GROUP | DMP_P2P_GRPCAP_SUPPORT;
++ else
++ p2pie[ p2pielen++ ] = DMP_P2P_GRPCAP_SUPPORT;
++
++
++ // Device Info ATTR
++ // Type:
++ p2pie[ p2pielen++ ] = P2P_ATTR_DEVICE_INFO;
++
++ // Length:
++ // 21 -> P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes)
++ // + NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes)
++ //*(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 21 + pwdinfo->device_name_len );
++ RTW_PUT_LE16(p2pie + p2pielen, 21 + pwdinfo->device_name_len);
++ p2pielen += 2;
++
++ // Value:
++ // P2P Device Address
++ _rtw_memcpy( p2pie + p2pielen, pwdinfo->device_addr, ETH_ALEN );
++ p2pielen += ETH_ALEN;
++
++ // Config Method
++ // This field should be big endian. Noted by P2P specification.
++ if ( pwdinfo->ui_got_wps_info == P2P_GOT_WPSINFO_PBC )
++ {
++ //*(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_CONFIG_METHOD_PBC );
++ RTW_PUT_BE16(p2pie + p2pielen, WPS_CONFIG_METHOD_PBC);
++ }
++ else
++ {
++ //*(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_CONFIG_METHOD_DISPLAY );
++ RTW_PUT_BE16(p2pie + p2pielen, WPS_CONFIG_METHOD_DISPLAY);
++ }
++
++ p2pielen += 2;
++
++ // Primary Device Type
++ // Category ID
++ //*(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_CID_MULIT_MEDIA );
++ RTW_PUT_BE16(p2pie + p2pielen, WPS_PDT_CID_MULIT_MEDIA);
++ p2pielen += 2;
++
++ // OUI
++ //*(u32*) ( p2pie + p2pielen ) = cpu_to_be32( WPSOUI );
++ RTW_PUT_BE32(p2pie + p2pielen, WPSOUI);
++ p2pielen += 4;
++
++ // Sub Category ID
++ //*(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_SCID_MEDIA_SERVER );
++ RTW_PUT_BE16(p2pie + p2pielen, WPS_PDT_SCID_MEDIA_SERVER);
++ p2pielen += 2;
++
++ // Number of Secondary Device Types
++ p2pie[ p2pielen++ ] = 0x00; // No Secondary Device Type List
++
++ // Device Name
++ // Type:
++ //*(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_ATTR_DEVICE_NAME );
++ RTW_PUT_BE16(p2pie + p2pielen, WPS_ATTR_DEVICE_NAME);
++ p2pielen += 2;
++
++ // Length:
++ //*(u16*) ( p2pie + p2pielen ) = cpu_to_be16( pwdinfo->device_name_len );
++ RTW_PUT_BE16(p2pie + p2pielen, pwdinfo->device_name_len);
++ p2pielen += 2;
++
++ // Value:
++ _rtw_memcpy( p2pie + p2pielen, pwdinfo->device_name, pwdinfo->device_name_len );
++ p2pielen += pwdinfo->device_name_len;
++
++ if ( rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT) )
++ {
++ // Added by Albert 2011/05/19
++ // In this case, the pdev_raddr is the device address of the group owner.
++
++ // P2P Group ID ATTR
++ // Type:
++ p2pie[ p2pielen++ ] = P2P_ATTR_GROUP_ID;
++
++ // Length:
++ //*(u16*) ( p2pie + p2pielen ) = cpu_to_le16( ETH_ALEN + ussidlen );
++ RTW_PUT_LE16(p2pie + p2pielen, ETH_ALEN + ussidlen);
++ p2pielen += 2;
++
++ // Value:
++ _rtw_memcpy( p2pie + p2pielen, pdev_raddr, ETH_ALEN );
++ p2pielen += ETH_ALEN;
++
++ _rtw_memcpy( p2pie + p2pielen, pssid, ussidlen );
++ p2pielen += ussidlen;
++
++ }
++
++ pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &len);
++
++
++ return len;
++
++}
++
++
++u32 build_assoc_resp_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, u8 status_code)
++{
++ u8 p2pie[ MAX_P2P_IE_LEN] = { 0x00 };
++ u32 len=0, p2pielen = 0;
++
++ // P2P OUI
++ p2pielen = 0;
++ p2pie[ p2pielen++ ] = 0x50;
++ p2pie[ p2pielen++ ] = 0x6F;
++ p2pie[ p2pielen++ ] = 0x9A;
++ p2pie[ p2pielen++ ] = 0x09; // WFA P2P v1.0
++
++ // According to the P2P Specification, the Association response frame should contain 2 P2P attributes
++ // 1. Status
++ // 2. Extended Listen Timing (optional)
++
++
++ // Status ATTR
++ p2pielen += rtw_set_p2p_attr_content(&p2pie[p2pielen], P2P_ATTR_STATUS, 1, &status_code);
++
++
++ // Extended Listen Timing ATTR
++ // Type:
++ // Length:
++ // Value:
++
++
++ pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &len);
++
++ return len;
++
++}
++
++u32 build_deauth_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)
++{
++ u32 len=0;
++
++ return len;
++}
++
++u32 process_probe_req_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pframe, uint len)
++{
++ u8 *p;
++ u32 ret=_FALSE;
++ u8 *p2pie;
++ u32 p2pielen = 0;
++ int ssid_len=0, rate_cnt = 0;
++
++ p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + _PROBEREQ_IE_OFFSET_, _SUPPORTEDRATES_IE_, (int *)&rate_cnt,
++ len - WLAN_HDR_A3_LEN - _PROBEREQ_IE_OFFSET_);
++
++ if ( rate_cnt <= 4 )
++ {
++ int i, g_rate =0;
++
++ for( i = 0; i < rate_cnt; i++ )
++ {
++ if ( ( ( *( p + 2 + i ) & 0xff ) != 0x02 ) &&
++ ( ( *( p + 2 + i ) & 0xff ) != 0x04 ) &&
++ ( ( *( p + 2 + i ) & 0xff ) != 0x0B ) &&
++ ( ( *( p + 2 + i ) & 0xff ) != 0x16 ) )
++ {
++ g_rate = 1;
++ }
++ }
++
++ if ( g_rate == 0 )
++ {
++ // There is no OFDM rate included in SupportedRates IE of this probe request frame
++ // The driver should response this probe request.
++ return ret;
++ }
++ }
++ else
++ {
++ // rate_cnt > 4 means the SupportRates IE contains the OFDM rate because the count of CCK rates are 4.
++ // We should proceed the following check for this probe request.
++ }
++
++ // Added comments by Albert 20100906
++ // There are several items we should check here.
++ // 1. This probe request frame must contain the P2P IE. (Done)
++ // 2. This probe request frame must contain the wildcard SSID. (Done)
++ // 3. Wildcard BSSID. (Todo)
++ // 4. Destination Address. ( Done in mgt_dispatcher function )
++ // 5. Requested Device Type in WSC IE. (Todo)
++ // 6. Device ID attribute in P2P IE. (Todo)
++
++ p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + _PROBEREQ_IE_OFFSET_, _SSID_IE_, (int *)&ssid_len,
++ len - WLAN_HDR_A3_LEN - _PROBEREQ_IE_OFFSET_);
++
++ ssid_len &= 0xff; // Just last 1 byte is valid for ssid len of the probe request
++ if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE) || rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO))
++ {
++ if((p2pie=rtw_get_p2p_ie( pframe + WLAN_HDR_A3_LEN + _PROBEREQ_IE_OFFSET_ , len - WLAN_HDR_A3_LEN - _PROBEREQ_IE_OFFSET_ , NULL, &p2pielen)))
++ {
++ if ( (p != NULL) && _rtw_memcmp( ( void * ) ( p+2 ), ( void * ) pwdinfo->p2p_wildcard_ssid , 7 ))
++ {
++ //todo:
++ //Check Requested Device Type attributes in WSC IE.
++ //Check Device ID attribute in P2P IE
++
++ ret = _TRUE;
++ }
++ else if ( (p != NULL) && ( ssid_len == 0 ) )
++ {
++ ret = _TRUE;
++ }
++ }
++ else
++ {
++ //non -p2p device
++ }
++
++ }
++
++
++ return ret;
++
++}
++
++u32 process_assoc_req_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pframe, uint len, struct sta_info *psta)
++{
++ u8 status_code = P2P_STATUS_SUCCESS;
++ u8 *pbuf, *pattr_content=NULL;
++ u32 attr_contentlen = 0;
++ u16 cap_attr=0;
++ unsigned short frame_type, ie_offset=0;
++ u8 * ies;
++ u32 ies_len;
++ u8 * p2p_ie;
++ u32 p2p_ielen = 0;
++
++ if(!rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO))
++ return P2P_STATUS_FAIL_REQUEST_UNABLE;
++
++ frame_type = GetFrameSubType(pframe);
++ if (frame_type == WIFI_ASSOCREQ)
++ {
++ ie_offset = _ASOCREQ_IE_OFFSET_;
++ }
++ else // WIFI_REASSOCREQ
++ {
++ ie_offset = _REASOCREQ_IE_OFFSET_;
++ }
++
++ ies = pframe + WLAN_HDR_A3_LEN + ie_offset;
++ ies_len = len - WLAN_HDR_A3_LEN - ie_offset;
++
++ p2p_ie = rtw_get_p2p_ie(ies , ies_len , NULL, &p2p_ielen);
++
++ if ( !p2p_ie )
++ {
++ DBG_8192C( "[%s] P2P IE not Found!!\n", __FUNCTION__ );
++ status_code = P2P_STATUS_FAIL_INVALID_PARAM;
++ }
++ else
++ {
++ DBG_8192C( "[%s] P2P IE Found!!\n", __FUNCTION__ );
++ }
++
++ while ( p2p_ie )
++ {
++ //Check P2P Capability ATTR
++ if( rtw_get_p2p_attr_content( p2p_ie, p2p_ielen, P2P_ATTR_CAPABILITY, (u8*)&cap_attr, (uint*) &attr_contentlen) )
++ {
++ DBG_8192C( "[%s] Got P2P Capability Attr!!\n", __FUNCTION__ );
++ cap_attr = le16_to_cpu(cap_attr);
++ psta->dev_cap = cap_attr&0xff;
++ }
++
++ //Check Extended Listen Timing ATTR
++
++
++ //Check P2P Device Info ATTR
++ if(rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_DEVICE_INFO, NULL, (uint*)&attr_contentlen))
++ {
++ DBG_8192C( "[%s] Got P2P DEVICE INFO Attr!!\n", __FUNCTION__ );
++ pattr_content = pbuf = rtw_zmalloc(attr_contentlen);
++ if(pattr_content)
++ {
++ u8 num_of_secdev_type;
++ u16 dev_name_len;
++
++
++ rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_DEVICE_INFO , pattr_content, (uint*)&attr_contentlen);
++
++ _rtw_memcpy(psta->dev_addr, pattr_content, ETH_ALEN);//P2P Device Address
++
++ pattr_content += ETH_ALEN;
++
++ _rtw_memcpy(&psta->config_methods, pattr_content, 2);//Config Methods
++ psta->config_methods = be16_to_cpu(psta->config_methods);
++
++ pattr_content += 2;
++
++ _rtw_memcpy(psta->primary_dev_type, pattr_content, 8);
++
++ pattr_content += 8;
++
++ num_of_secdev_type = *pattr_content;
++ pattr_content += 1;
++
++ if(num_of_secdev_type==0)
++ {
++ psta->num_of_secdev_type = 0;
++ }
++ else
++ {
++ u32 len;
++
++ psta->num_of_secdev_type = num_of_secdev_type;
++
++ len = (sizeof(psta->secdev_types_list)<(num_of_secdev_type*8)) ? (sizeof(psta->secdev_types_list)) : (num_of_secdev_type*8);
++
++ _rtw_memcpy(psta->secdev_types_list, pattr_content, len);
++
++ pattr_content += (num_of_secdev_type*8);
++ }
++
++
++ //dev_name_len = attr_contentlen - ETH_ALEN - 2 - 8 - 1 - (num_of_secdev_type*8);
++ psta->dev_name_len=0;
++ if(WPS_ATTR_DEVICE_NAME == be16_to_cpu(*(u16*)pattr_content))
++ {
++ dev_name_len = be16_to_cpu(*(u16*)(pattr_content+2));
++
++ psta->dev_name_len = (sizeof(psta->dev_name)<dev_name_len) ? sizeof(psta->dev_name):dev_name_len;
++
++ _rtw_memcpy(psta->dev_name, pattr_content+4, psta->dev_name_len);
++ }
++
++ rtw_mfree(pbuf, attr_contentlen);
++
++ }
++
++ }
++
++ //Get the next P2P IE
++ p2p_ie = rtw_get_p2p_ie(p2p_ie+p2p_ielen, ies_len -(p2p_ie -ies + p2p_ielen), NULL, &p2p_ielen);
++
++ }
++
++ return status_code;
++
++}
++
++u32 process_p2p_devdisc_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint len)
++{
++ u8 *frame_body;
++ u8 status, dialogToken;
++ struct sta_info *psta = NULL;
++ _adapter *padapter = pwdinfo->padapter;
++ struct sta_priv *pstapriv = &padapter->stapriv;
++ u8 *p2p_ie;
++ u32 p2p_ielen = 0;
++
++ frame_body = (unsigned char *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr));
++
++ dialogToken = frame_body[7];
++ status = P2P_STATUS_FAIL_UNKNOWN_P2PGROUP;
++
++ if ( (p2p_ie=rtw_get_p2p_ie( frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, NULL, &p2p_ielen)) )
++ {
++ u8 groupid[ 38 ] = { 0x00 };
++ u8 dev_addr[ETH_ALEN] = { 0x00 };
++ u32 attr_contentlen = 0;
++
++ if(rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GROUP_ID, groupid, &attr_contentlen))
++ {
++ if(_rtw_memcmp(pwdinfo->device_addr, groupid, ETH_ALEN) &&
++ _rtw_memcmp(pwdinfo->p2p_group_ssid, groupid+ETH_ALEN, pwdinfo->p2p_group_ssid_len))
++ {
++ attr_contentlen=0;
++ if(rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_DEVICE_ID, dev_addr, &attr_contentlen))
++ {
++ _irqL irqL;
++ _list *phead, *plist;
++
++ _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++ phead = &pstapriv->asoc_list;
++ plist = get_next(phead);
++
++ //look up sta asoc_queue
++ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE)
++ {
++ psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);
++
++ plist = get_next(plist);
++
++ if(psta->is_p2p_device && (psta->dev_cap&P2P_DEVCAP_CLIENT_DISCOVERABILITY) &&
++ _rtw_memcmp(psta->dev_addr, dev_addr, ETH_ALEN))
++ {
++
++ //_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++ //issue GO Discoverability Request
++ issue_group_disc_req(pwdinfo, psta->hwaddr);
++ //_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++
++ status = P2P_STATUS_SUCCESS;
++
++ break;
++ }
++ else
++ {
++ status = P2P_STATUS_FAIL_INFO_UNAVAILABLE;
++ }
++
++ }
++ _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++
++ }
++ else
++ {
++ status = P2P_STATUS_FAIL_INVALID_PARAM;
++ }
++
++ }
++ else
++ {
++ status = P2P_STATUS_FAIL_INVALID_PARAM;
++ }
++
++ }
++
++ }
++
++
++ //issue Device Discoverability Response
++ issue_p2p_devdisc_resp(pwdinfo, GetAddr2Ptr(pframe), status, dialogToken);
++
++
++ return (status==P2P_STATUS_SUCCESS) ? _TRUE:_FALSE;
++
++}
++
++u32 process_p2p_devdisc_resp(struct wifidirect_info *pwdinfo, u8 *pframe, uint len)
++{
++ return _TRUE;
++}
++
++u8 process_p2p_provdisc_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint len )
++{
++ u8 *frame_body;
++ u8 *wpsie;
++ uint wps_ielen = 0, attr_contentlen = 0;
++ u16 uconfig_method = 0;
++
++
++ frame_body = (pframe + sizeof(struct rtw_ieee80211_hdr_3addr));
++
++ if ( (wpsie=rtw_get_wps_ie( frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, NULL, &wps_ielen)) )
++ {
++ if ( rtw_get_wps_attr_content( wpsie, wps_ielen, WPS_ATTR_CONF_METHOD , ( u8* ) &uconfig_method, &attr_contentlen) )
++ {
++ uconfig_method = be16_to_cpu( uconfig_method );
++ switch( uconfig_method )
++ {
++ case WPS_CM_DISPLYA:
++ {
++ _rtw_memcpy( pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "dis", 3 );
++ break;
++ }
++ case WPS_CM_LABEL:
++ {
++ _rtw_memcpy( pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "lab", 3 );
++ break;
++ }
++ case WPS_CM_PUSH_BUTTON:
++ {
++ _rtw_memcpy( pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "pbc", 3 );
++ break;
++ }
++ case WPS_CM_KEYPAD:
++ {
++ _rtw_memcpy( pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "pad", 3 );
++ break;
++ }
++ }
++ issue_p2p_provision_resp( pwdinfo, GetAddr2Ptr(pframe), frame_body, uconfig_method);
++ }
++ }
++ DBG_871X( "[%s] config method = %s\n", __FUNCTION__, pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req );
++ return _TRUE;
++
++}
++
++u8 process_p2p_provdisc_resp(struct wifidirect_info *pwdinfo, u8 *pframe)
++{
++
++ return _TRUE;
++}
++
++u8 rtw_p2p_get_peer_ch_list(struct wifidirect_info *pwdinfo, u8 *ch_content, u8 ch_cnt, u8 *peer_ch_list)
++{
++ u8 i = 0, j = 0;
++ u8 temp = 0;
++ u8 ch_no = 0;
++ ch_content += 3;
++ ch_cnt -= 3;
++
++ while( ch_cnt > 0)
++ {
++ ch_content += 1;
++ ch_cnt -= 1;
++ temp = *ch_content;
++ for( i = 0 ; i < temp ; i++, j++ )
++ {
++ peer_ch_list[j] = *( ch_content + 1 + i );
++ }
++ ch_content += (temp + 1);
++ ch_cnt -= (temp + 1);
++ ch_no += temp ;
++ }
++
++ return ch_no;
++}
++
++u8 rtw_p2p_check_peer_oper_ch(struct mlme_ext_priv *pmlmeext, u8 ch)
++{
++ u8 i = 0;
++
++ for( i = 0; i < pmlmeext->max_chan_nums; i++ )
++ {
++ if ( pmlmeext->channel_set[ i ].ChannelNum == ch )
++ {
++ return _SUCCESS;
++ }
++ }
++
++ return _FAIL;
++}
++
++u8 rtw_p2p_ch_inclusion(struct mlme_ext_priv *pmlmeext, u8 *peer_ch_list, u8 peer_ch_num, u8 *ch_list_inclusioned)
++{
++ int i = 0, j = 0, temp = 0;
++ u8 ch_no = 0;
++
++ for( i = 0; i < peer_ch_num; i++ )
++ {
++ for( j = temp; j < pmlmeext->max_chan_nums; j++ )
++ {
++ if( *( peer_ch_list + i ) == pmlmeext->channel_set[ j ].ChannelNum )
++ {
++ ch_list_inclusioned[ ch_no++ ] = *( peer_ch_list + i );
++ temp = j;
++ break;
++ }
++ }
++ }
++
++ return ch_no;
++}
++
++u8 process_p2p_group_negotation_req( struct wifidirect_info *pwdinfo, u8 *pframe, uint len )
++{
++ _adapter *padapter = pwdinfo->padapter;
++ u8 result = P2P_STATUS_SUCCESS;
++ u32 p2p_ielen = 0, wps_ielen = 0;
++ u8 * ies;
++ u32 ies_len;
++ u8 *p2p_ie;
++ u8 *wpsie;
++ u16 wps_devicepassword_id = 0x0000;
++ uint wps_devicepassword_id_len = 0;
++#ifdef CONFIG_WFD
++ u8 wfd_ie[ 128 ] = { 0x00 };
++ u32 wfd_ielen = 0;
++#ifdef CONFIG_TDLS
++ struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
++#endif // CONFIG_TDLS
++#endif // CONFIG_WFD
++#ifdef CONFIG_CONCURRENT_MODE
++ _adapter *pbuddy_adapter = pwdinfo->padapter->pbuddy_adapter;
++ struct wifidirect_info *pbuddy_wdinfo = &pbuddy_adapter->wdinfo;
++ struct mlme_priv *pbuddy_mlmepriv = &pbuddy_adapter->mlmepriv;
++ struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv;
++#endif
++
++ if ( (wpsie=rtw_get_wps_ie( pframe + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, NULL, &wps_ielen)) )
++ {
++ // Commented by Kurt 20120113
++ // If some device wants to do p2p handshake without sending prov_disc_req
++ // We have to get peer_req_cm from here.
++ if(_rtw_memcmp( pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "000", 3) )
++ {
++ rtw_get_wps_attr_content( wpsie, wps_ielen, WPS_ATTR_DEVICE_PWID, (u8*) &wps_devicepassword_id, &wps_devicepassword_id_len);
++ wps_devicepassword_id = be16_to_cpu( wps_devicepassword_id );
++
++ if ( wps_devicepassword_id == WPS_DPID_USER_SPEC )
++ {
++ _rtw_memcpy( pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "dis", 3 );
++ }
++ else if ( wps_devicepassword_id == WPS_DPID_REGISTRAR_SPEC )
++ {
++ _rtw_memcpy( pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "pad", 3 );
++ }
++ else
++ {
++ _rtw_memcpy( pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "pbc", 3 );
++ }
++ }
++ }
++ else
++ {
++ DBG_871X( "[%s] WPS IE not Found!!\n", __FUNCTION__ );
++ result = P2P_STATUS_FAIL_INCOMPATIBLE_PARAM;
++ rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL);
++ return( result );
++ }
++
++ if ( pwdinfo->ui_got_wps_info == P2P_NO_WPSINFO )
++ {
++ result = P2P_STATUS_FAIL_INFO_UNAVAILABLE;
++ rtw_p2p_set_state(pwdinfo, P2P_STATE_TX_INFOR_NOREADY);
++ return( result );
++ }
++
++ ies = pframe + _PUBLIC_ACTION_IE_OFFSET_;
++ ies_len = len - _PUBLIC_ACTION_IE_OFFSET_;
++
++ p2p_ie = rtw_get_p2p_ie( ies, ies_len, NULL, &p2p_ielen );
++
++ if ( !p2p_ie )
++ {
++ DBG_871X( "[%s] P2P IE not Found!!\n", __FUNCTION__ );
++ result = P2P_STATUS_FAIL_INCOMPATIBLE_PARAM;
++ rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL);
++ }
++
++ while ( p2p_ie )
++ {
++ u8 attr_content = 0x00;
++ u32 attr_contentlen = 0;
++ u8 ch_content[100] = { 0x00 };
++ uint ch_cnt = 0;
++ u8 peer_ch_list[100] = { 0x00 };
++ u8 peer_ch_num = 0;
++ u8 ch_list_inclusioned[100] = { 0x00 };
++ u8 ch_num_inclusioned = 0;
++ u16 cap_attr;
++
++ rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_ING);
++
++ //Check P2P Capability ATTR
++ if(rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CAPABILITY, (u8*)&cap_attr, (uint*)&attr_contentlen) )
++ {
++ cap_attr = le16_to_cpu(cap_attr);
++
++#if defined(CONFIG_WFD) && defined(CONFIG_TDLS)
++ if(!(cap_attr & P2P_GRPCAP_INTRABSS) )
++ ptdlsinfo->ap_prohibited = _TRUE;
++#endif //defined(CONFIG_WFD) && defined(CONFIG_TDLS)
++ }
++
++ if ( rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GO_INTENT , &attr_content, &attr_contentlen) )
++ {
++ DBG_871X( "[%s] GO Intent = %d, tie = %d\n", __FUNCTION__, attr_content >> 1, attr_content & 0x01 );
++ pwdinfo->peer_intent = attr_content; // include both intent and tie breaker values.
++
++ if ( pwdinfo->intent == ( pwdinfo->peer_intent >> 1 ) )
++ {
++ // Try to match the tie breaker value
++ if ( pwdinfo->intent == P2P_MAX_INTENT )
++ {
++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE);
++ result = P2P_STATUS_FAIL_BOTH_GOINTENT_15;
++ }
++ else
++ {
++ if ( attr_content & 0x01 )
++ {
++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT);
++ }
++ else
++ {
++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO);
++ }
++ }
++ }
++ else if ( pwdinfo->intent > ( pwdinfo->peer_intent >> 1 ) )
++ {
++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO);
++ }
++ else
++ {
++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT);
++ }
++
++ if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO))
++ {
++ // Store the group id information.
++ _rtw_memcpy( pwdinfo->groupid_info.go_device_addr, pwdinfo->device_addr, ETH_ALEN );
++ _rtw_memcpy( pwdinfo->groupid_info.ssid, pwdinfo->nego_ssid, pwdinfo->nego_ssidlen );
++ }
++ }
++
++
++ attr_contentlen = 0;
++ if ( rtw_get_p2p_attr_content( p2p_ie, p2p_ielen, P2P_ATTR_INTENTED_IF_ADDR, pwdinfo->p2p_peer_interface_addr, &attr_contentlen ) )
++ {
++ if ( attr_contentlen != ETH_ALEN )
++ {
++ _rtw_memset( pwdinfo->p2p_peer_interface_addr, 0x00, ETH_ALEN );
++ }
++ }
++
++ if ( rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CH_LIST, ch_content, &ch_cnt) )
++ {
++ peer_ch_num = rtw_p2p_get_peer_ch_list(pwdinfo, ch_content, ch_cnt, peer_ch_list);
++ ch_num_inclusioned = rtw_p2p_ch_inclusion(&padapter->mlmeextpriv, peer_ch_list, peer_ch_num, ch_list_inclusioned);
++
++ if( ch_num_inclusioned == 0)
++ {
++ DBG_871X( "[%s] No common channel in channel list!\n", __FUNCTION__ );
++ result = P2P_STATUS_FAIL_NO_COMMON_CH;
++ rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL);
++ break;
++ }
++
++ if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO))
++ {
++ if ( !rtw_p2p_is_channel_list_ok( pwdinfo->operating_channel,
++ ch_list_inclusioned, ch_num_inclusioned) )
++ {
++#ifdef CONFIG_CONCURRENT_MODE
++ if ( check_buddy_fwstate(padapter, _FW_LINKED ) )
++ {
++ DBG_871X( "[%s] desired channel NOT Found!\n", __FUNCTION__ );
++ result = P2P_STATUS_FAIL_NO_COMMON_CH;
++ rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL);
++ break;
++ }
++ else
++#endif //CONFIG_CONCURRENT_MODE
++ {
++ u8 operatingch_info[5] = { 0x00 }, peer_operating_ch = 0;
++ attr_contentlen = 0;
++
++ if ( rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, operatingch_info, &attr_contentlen) )
++ {
++ peer_operating_ch = operatingch_info[4];
++ }
++
++ if ( rtw_p2p_is_channel_list_ok( peer_operating_ch,
++ ch_list_inclusioned, ch_num_inclusioned) )
++ {
++ /**
++ * Change our operating channel as peer's for compatibility.
++ */
++ pwdinfo->operating_channel = peer_operating_ch;
++ DBG_871X( "[%s] Change op ch to %02x as peer's\n", __FUNCTION__, pwdinfo->operating_channel);
++ }
++ else
++ {
++ // Take first channel of ch_list_inclusioned as operating channel
++ pwdinfo->operating_channel = ch_list_inclusioned[0];
++ DBG_871X( "[%s] Change op ch to %02x\n", __FUNCTION__, pwdinfo->operating_channel);
++ }
++ }
++
++ }
++ }
++ }
++
++ //Get the next P2P IE
++ p2p_ie = rtw_get_p2p_ie(p2p_ie+p2p_ielen, ies_len -(p2p_ie -ies + p2p_ielen), NULL, &p2p_ielen);
++ }
++
++#ifdef CONFIG_WFD
++ // Added by Albert 20110823
++ // Try to get the TCP port information when receiving the negotiation request.
++ if ( rtw_get_wfd_ie( pframe + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, wfd_ie, &wfd_ielen ) )
++ {
++ u8 attr_content[ 10 ] = { 0x00 };
++ u32 attr_contentlen = 0;
++
++ DBG_871X( "[%s] WFD IE Found!!\n", __FUNCTION__ );
++ rtw_get_wfd_attr_content( wfd_ie, wfd_ielen, WFD_ATTR_DEVICE_INFO, attr_content, &attr_contentlen);
++ if ( attr_contentlen )
++ {
++ pwdinfo->wfd_info->peer_rtsp_ctrlport = RTW_GET_BE16( attr_content + 2 );
++ DBG_871X( "[%s] Peer PORT NUM = %d\n", __FUNCTION__, pwdinfo->wfd_info->peer_rtsp_ctrlport );
++ }
++ }
++#endif // CONFIG_WFD
++
++ return( result );
++}
++
++u8 process_p2p_group_negotation_resp( struct wifidirect_info *pwdinfo, u8 *pframe, uint len )
++{
++ _adapter *padapter = pwdinfo->padapter;
++ u8 result = P2P_STATUS_SUCCESS;
++ u32 p2p_ielen, wps_ielen;
++ u8 * ies;
++ u32 ies_len;
++ u8 * p2p_ie;
++#ifdef CONFIG_WFD
++ u8 wfd_ie[ 128 ] = { 0x00 };
++ u32 wfd_ielen = 0;
++#ifdef CONFIG_TDLS
++ struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
++#endif // CONFIG_TDLS
++#endif // CONFIG_WFD
++
++ ies = pframe + _PUBLIC_ACTION_IE_OFFSET_;
++ ies_len = len - _PUBLIC_ACTION_IE_OFFSET_;
++
++ // Be able to know which one is the P2P GO and which one is P2P client.
++
++ if ( rtw_get_wps_ie( ies, ies_len, NULL, &wps_ielen) )
++ {
++
++ }
++ else
++ {
++ DBG_871X( "[%s] WPS IE not Found!!\n", __FUNCTION__ );
++ result = P2P_STATUS_FAIL_INCOMPATIBLE_PARAM;
++ rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL);
++ }
++
++ p2p_ie = rtw_get_p2p_ie( ies, ies_len, NULL, &p2p_ielen );
++ if ( !p2p_ie )
++ {
++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE);
++ rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL);
++ result = P2P_STATUS_FAIL_INCOMPATIBLE_PARAM;
++ }
++ else
++ {
++
++ u8 attr_content = 0x00;
++ u32 attr_contentlen = 0;
++ u8 operatingch_info[5] = { 0x00 };
++ uint ch_cnt = 0;
++ u8 ch_content[100] = { 0x00 };
++ u8 groupid[ 38 ];
++ u16 cap_attr;
++ u8 peer_ch_list[100] = { 0x00 };
++ u8 peer_ch_num = 0;
++ u8 ch_list_inclusioned[100] = { 0x00 };
++ u8 ch_num_inclusioned = 0;
++
++ while ( p2p_ie ) // Found the P2P IE.
++ {
++
++ //Check P2P Capability ATTR
++ if(rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CAPABILITY, (u8*)&cap_attr, (uint*)&attr_contentlen) )
++ {
++ cap_attr = le16_to_cpu(cap_attr);
++#if defined(CONFIG_WFD) && defined(CONFIG_TDLS)
++ if(!(cap_attr & P2P_GRPCAP_INTRABSS) )
++ ptdlsinfo->ap_prohibited = _TRUE;
++#endif //defined(CONFIG_WFD) && defined(CONFIG_TDLS)
++ }
++
++ rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_STATUS, &attr_content, &attr_contentlen);
++ if ( attr_contentlen == 1 )
++ {
++ DBG_871X( "[%s] Status = %d\n", __FUNCTION__, attr_content );
++ if ( attr_content == P2P_STATUS_SUCCESS )
++ {
++ // Do nothing.
++ }
++ else
++ {
++ if ( P2P_STATUS_FAIL_INFO_UNAVAILABLE == attr_content ) {
++ rtw_p2p_set_state(pwdinfo, P2P_STATE_RX_INFOR_NOREADY);
++ } else {
++ rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL);
++ }
++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE);
++ result = attr_content;
++ break;
++ }
++ }
++
++ // Try to get the peer's interface address
++ attr_contentlen = 0;
++ if ( rtw_get_p2p_attr_content( p2p_ie, p2p_ielen, P2P_ATTR_INTENTED_IF_ADDR, pwdinfo->p2p_peer_interface_addr, &attr_contentlen ) )
++ {
++ if ( attr_contentlen != ETH_ALEN )
++ {
++ _rtw_memset( pwdinfo->p2p_peer_interface_addr, 0x00, ETH_ALEN );
++ }
++ }
++
++ // Try to get the peer's intent and tie breaker value.
++ attr_content = 0x00;
++ attr_contentlen = 0;
++ if ( rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GO_INTENT , &attr_content, &attr_contentlen) )
++ {
++ DBG_871X( "[%s] GO Intent = %d, tie = %d\n", __FUNCTION__, attr_content >> 1, attr_content & 0x01 );
++ pwdinfo->peer_intent = attr_content; // include both intent and tie breaker values.
++
++ if ( pwdinfo->intent == ( pwdinfo->peer_intent >> 1 ) )
++ {
++ // Try to match the tie breaker value
++ if ( pwdinfo->intent == P2P_MAX_INTENT )
++ {
++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE);
++ result = P2P_STATUS_FAIL_BOTH_GOINTENT_15;
++ rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL);
++ }
++ else
++ {
++ rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK);
++ rtw_p2p_set_pre_state(pwdinfo, P2P_STATE_GONEGO_OK);
++ if ( attr_content & 0x01 )
++ {
++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT);
++ }
++ else
++ {
++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO);
++ }
++ }
++ }
++ else if ( pwdinfo->intent > ( pwdinfo->peer_intent >> 1 ) )
++ {
++ rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK);
++ rtw_p2p_set_pre_state(pwdinfo, P2P_STATE_GONEGO_OK);
++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO);
++ }
++ else
++ {
++ rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK);
++ rtw_p2p_set_pre_state(pwdinfo, P2P_STATE_GONEGO_OK);
++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT);
++ }
++
++ if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO))
++ {
++ // Store the group id information.
++ _rtw_memcpy( pwdinfo->groupid_info.go_device_addr, pwdinfo->device_addr, ETH_ALEN );
++ _rtw_memcpy( pwdinfo->groupid_info.ssid, pwdinfo->nego_ssid, pwdinfo->nego_ssidlen );
++
++ }
++ }
++
++ // Try to get the operation channel information
++
++ attr_contentlen = 0;
++ if ( rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, operatingch_info, &attr_contentlen))
++ {
++ DBG_871X( "[%s] Peer's operating channel = %d\n", __FUNCTION__, operatingch_info[4] );
++ pwdinfo->peer_operating_ch = operatingch_info[4];
++ }
++
++ // Try to get the channel list information
++ if ( rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CH_LIST, pwdinfo->channel_list_attr, &pwdinfo->channel_list_attr_len ) )
++ {
++ DBG_871X( "[%s] channel list attribute found, len = %d\n", __FUNCTION__, pwdinfo->channel_list_attr_len );
++
++ peer_ch_num = rtw_p2p_get_peer_ch_list(pwdinfo, pwdinfo->channel_list_attr, pwdinfo->channel_list_attr_len, peer_ch_list);
++ ch_num_inclusioned = rtw_p2p_ch_inclusion(&padapter->mlmeextpriv, peer_ch_list, peer_ch_num, ch_list_inclusioned);
++
++ if( ch_num_inclusioned == 0)
++ {
++ DBG_871X( "[%s] No common channel in channel list!\n", __FUNCTION__ );
++ result = P2P_STATUS_FAIL_NO_COMMON_CH;
++ rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL);
++ break;
++ }
++
++ if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO))
++ {
++ if ( !rtw_p2p_is_channel_list_ok( pwdinfo->operating_channel,
++ ch_list_inclusioned, ch_num_inclusioned) )
++ {
++#ifdef CONFIG_CONCURRENT_MODE
++ if ( check_buddy_fwstate(padapter, _FW_LINKED ) )
++ {
++ DBG_871X( "[%s] desired channel NOT Found!\n", __FUNCTION__ );
++ result = P2P_STATUS_FAIL_NO_COMMON_CH;
++ rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL);
++ break;
++ }
++ else
++#endif //CONFIG_CONCURRENT_MODE
++ {
++ u8 operatingch_info[5] = { 0x00 }, peer_operating_ch = 0;
++ attr_contentlen = 0;
++
++ if ( rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, operatingch_info, &attr_contentlen) )
++ {
++ peer_operating_ch = operatingch_info[4];
++ }
++
++ if ( rtw_p2p_is_channel_list_ok( peer_operating_ch,
++ ch_list_inclusioned, ch_num_inclusioned) )
++ {
++ /**
++ * Change our operating channel as peer's for compatibility.
++ */
++ pwdinfo->operating_channel = peer_operating_ch;
++ DBG_871X( "[%s] Change op ch to %02x as peer's\n", __FUNCTION__, pwdinfo->operating_channel);
++ }
++ else
++ {
++ // Take first channel of ch_list_inclusioned as operating channel
++ pwdinfo->operating_channel = ch_list_inclusioned[0];
++ DBG_871X( "[%s] Change op ch to %02x\n", __FUNCTION__, pwdinfo->operating_channel);
++ }
++ }
++
++ }
++ }
++
++ }
++ else
++ {
++ DBG_871X( "[%s] channel list attribute not found!\n", __FUNCTION__);
++ }
++
++ // Try to get the group id information if peer is GO
++ attr_contentlen = 0;
++ _rtw_memset( groupid, 0x00, 38 );
++ if ( rtw_get_p2p_attr_content( p2p_ie, p2p_ielen, P2P_ATTR_GROUP_ID, groupid, &attr_contentlen) )
++ {
++ _rtw_memcpy( pwdinfo->groupid_info.go_device_addr, &groupid[0], ETH_ALEN );
++ _rtw_memcpy( pwdinfo->groupid_info.ssid, &groupid[6], attr_contentlen - ETH_ALEN );
++ }
++
++ //Get the next P2P IE
++ p2p_ie = rtw_get_p2p_ie(p2p_ie+p2p_ielen, ies_len -(p2p_ie -ies + p2p_ielen), NULL, &p2p_ielen);
++ }
++
++ }
++
++#ifdef CONFIG_WFD
++ // Added by Albert 20111122
++ // Try to get the TCP port information when receiving the negotiation response.
++ if ( rtw_get_wfd_ie( pframe + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, wfd_ie, &wfd_ielen ) )
++ {
++ u8 attr_content[ 10 ] = { 0x00 };
++ u32 attr_contentlen = 0;
++
++ DBG_8192C( "[%s] WFD IE Found!!\n", __FUNCTION__ );
++ rtw_get_wfd_attr_content( wfd_ie, wfd_ielen, WFD_ATTR_DEVICE_INFO, attr_content, &attr_contentlen);
++ if ( attr_contentlen )
++ {
++ pwdinfo->wfd_info->peer_rtsp_ctrlport = RTW_GET_BE16( attr_content + 2 );
++ DBG_8192C( "[%s] Peer PORT NUM = %d\n", __FUNCTION__, pwdinfo->wfd_info->peer_rtsp_ctrlport );
++ }
++ }
++#endif // CONFIG_WFD
++
++ return( result );
++
++}
++
++u8 process_p2p_group_negotation_confirm( struct wifidirect_info *pwdinfo, u8 *pframe, uint len )
++{
++ u8 * ies;
++ u32 ies_len;
++ u8 * p2p_ie;
++ u32 p2p_ielen = 0;
++ u8 result = P2P_STATUS_SUCCESS;
++ ies = pframe + _PUBLIC_ACTION_IE_OFFSET_;
++ ies_len = len - _PUBLIC_ACTION_IE_OFFSET_;
++
++ p2p_ie = rtw_get_p2p_ie( ies, ies_len, NULL, &p2p_ielen );
++ while ( p2p_ie ) // Found the P2P IE.
++ {
++ u8 attr_content = 0x00, operatingch_info[5] = { 0x00 };
++ u8 groupid[ 38 ] = { 0x00 };
++ u32 attr_contentlen = 0;
++
++ pwdinfo->negotiation_dialog_token = 1;
++ rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_STATUS, &attr_content, &attr_contentlen);
++ if ( attr_contentlen == 1 )
++ {
++ DBG_871X( "[%s] Status = %d\n", __FUNCTION__, attr_content );
++ result = attr_content;
++
++ if ( attr_content == P2P_STATUS_SUCCESS )
++ {
++ u8 bcancelled = 0;
++
++ _cancel_timer( &pwdinfo->restore_p2p_state_timer, &bcancelled );
++
++ // Commented by Albert 20100911
++ // Todo: Need to handle the case which both Intents are the same.
++ rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK);
++ rtw_p2p_set_pre_state(pwdinfo, P2P_STATE_GONEGO_OK);
++ if ( ( pwdinfo->intent ) > ( pwdinfo->peer_intent >> 1 ) )
++ {
++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO);
++ }
++ else if ( ( pwdinfo->intent ) < ( pwdinfo->peer_intent >> 1 ) )
++ {
++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT);
++ }
++ else
++ {
++ // Have to compare the Tie Breaker
++ if ( pwdinfo->peer_intent & 0x01 )
++ {
++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT);
++ }
++ else
++ {
++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO);
++ }
++ }
++
++#ifdef CONFIG_CONCURRENT_MODE
++ if ( check_buddy_fwstate(pwdinfo->padapter , _FW_LINKED ) )
++ {
++ // Switch back to the AP channel soon.
++ _set_timer( &pwdinfo->ap_p2p_switch_timer, 100 );
++ }
++#endif
++ }
++ else
++ {
++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE);
++ rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL);
++ break;
++ }
++ }
++
++ // Try to get the group id information
++ attr_contentlen = 0;
++ _rtw_memset( groupid, 0x00, 38 );
++ if ( rtw_get_p2p_attr_content( p2p_ie, p2p_ielen, P2P_ATTR_GROUP_ID, groupid, &attr_contentlen) )
++ {
++ DBG_871X( "[%s] Ssid = %s, ssidlen = %d\n", __FUNCTION__, &groupid[ETH_ALEN], (u32)strlen(&groupid[ETH_ALEN]) );
++ _rtw_memcpy( pwdinfo->groupid_info.go_device_addr, &groupid[0], ETH_ALEN );
++ _rtw_memcpy( pwdinfo->groupid_info.ssid, &groupid[6], attr_contentlen - ETH_ALEN );
++ }
++
++ attr_contentlen = 0;
++ if ( rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, operatingch_info, &attr_contentlen) )
++ {
++ DBG_871X( "[%s] Peer's operating channel = %d\n", __FUNCTION__, operatingch_info[4] );
++ pwdinfo->peer_operating_ch = operatingch_info[4];
++ }
++
++ //Get the next P2P IE
++ p2p_ie = rtw_get_p2p_ie(p2p_ie+p2p_ielen, ies_len -(p2p_ie -ies + p2p_ielen), NULL, &p2p_ielen);
++
++ }
++
++ return( result );
++}
++
++u8 process_p2p_presence_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint len)
++{
++ u8 *frame_body;
++ u8 dialogToken=0;
++ u8 status = P2P_STATUS_SUCCESS;
++
++ frame_body = (unsigned char *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr));
++
++ dialogToken = frame_body[6];
++
++ //todo: check NoA attribute
++
++ issue_p2p_presence_resp(pwdinfo, GetAddr2Ptr(pframe), status, dialogToken);
++
++ return _TRUE;
++}
++
++void find_phase_handler( _adapter* padapter )
++{
++ struct wifidirect_info *pwdinfo = &padapter->wdinfo;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ NDIS_802_11_SSID ssid;
++ _irqL irqL;
++ u8 _status = 0;
++
++_func_enter_;
++
++ _rtw_memset((unsigned char*)&ssid, 0, sizeof(NDIS_802_11_SSID));
++ _rtw_memcpy(ssid.Ssid, pwdinfo->p2p_wildcard_ssid, P2P_WILDCARD_SSID_LEN );
++ ssid.SsidLength = P2P_WILDCARD_SSID_LEN;
++
++ rtw_p2p_set_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH);
++
++ _enter_critical_bh(&pmlmepriv->lock, &irqL);
++ _status = rtw_sitesurvey_cmd(padapter, &ssid, 1, NULL, 0);
++ _exit_critical_bh(&pmlmepriv->lock, &irqL);
++
++
++_func_exit_;
++}
++
++void p2p_concurrent_handler( _adapter* padapter );
++
++void restore_p2p_state_handler( _adapter* padapter )
++{
++ struct wifidirect_info *pwdinfo = &padapter->wdinfo;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++
++_func_enter_;
++
++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING) || rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_FAIL))
++ {
++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE);
++ }
++
++#ifdef CONFIG_CONCURRENT_MODE
++ if ( check_buddy_fwstate(padapter, _FW_LINKED ) )
++ {
++ _adapter *pbuddy_adapter = padapter->pbuddy_adapter;
++ struct mlme_priv *pbuddy_mlmepriv = &pbuddy_adapter->mlmepriv;
++ struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv;
++
++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_PROVISION_DIS_REQ) || rtw_p2p_chk_state(pwdinfo, P2P_STATE_RX_PROVISION_DIS_RSP))
++ {
++ set_channel_bwmode(padapter, pbuddy_mlmeext->cur_channel, pbuddy_mlmeext->cur_ch_offset, pbuddy_mlmeext->cur_bwmode);
++
++ issue_nulldata(pbuddy_adapter, NULL, 0, 3, 500);
++ }
++ }
++#endif
++
++ rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo));
++
++ if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE))
++ {
++#ifdef CONFIG_CONCURRENT_MODE
++ p2p_concurrent_handler( padapter );
++#else
++ // In the P2P client mode, the driver should not switch back to its listen channel
++ // because this P2P client should stay at the operating channel of P2P GO.
++ set_channel_bwmode( padapter, pwdinfo->listen_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HT_CHANNEL_WIDTH_20);
++#endif
++ }
++_func_exit_;
++}
++
++void pre_tx_invitereq_handler( _adapter* padapter )
++{
++ struct wifidirect_info *pwdinfo = &padapter->wdinfo;
++ u8 val8 = 1;
++_func_enter_;
++
++ set_channel_bwmode(padapter, pwdinfo->invitereq_info.peer_ch, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HT_CHANNEL_WIDTH_20);
++ rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));
++ issue_probereq_p2p(padapter, NULL);
++ _set_timer( &pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT );
++
++_func_exit_;
++}
++
++void pre_tx_provdisc_handler( _adapter* padapter )
++{
++ struct wifidirect_info *pwdinfo = &padapter->wdinfo;
++ u8 val8 = 1;
++_func_enter_;
++
++ set_channel_bwmode(padapter, pwdinfo->tx_prov_disc_info.peer_channel_num[0], HAL_PRIME_CHNL_OFFSET_DONT_CARE, HT_CHANNEL_WIDTH_20);
++ rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));
++ issue_probereq_p2p(padapter, NULL);
++ _set_timer( &pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT );
++
++_func_exit_;
++}
++
++void pre_tx_negoreq_handler( _adapter* padapter )
++{
++ struct wifidirect_info *pwdinfo = &padapter->wdinfo;
++ u8 val8 = 1;
++_func_enter_;
++
++ set_channel_bwmode(padapter, pwdinfo->nego_req_info.peer_channel_num[0], HAL_PRIME_CHNL_OFFSET_DONT_CARE, HT_CHANNEL_WIDTH_20);
++ rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));
++ issue_probereq_p2p(padapter, NULL);
++ _set_timer( &pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT );
++
++_func_exit_;
++}
++
++#ifdef CONFIG_CONCURRENT_MODE
++void p2p_concurrent_handler( _adapter* padapter )
++{
++ struct wifidirect_info *pwdinfo = &padapter->wdinfo;
++ //_adapter *pbuddy_adapter = padapter->pbuddy_adapter;
++ //struct wifidirect_info *pbuddy_wdinfo = &pbuddy_adapter->wdinfo;
++ //struct mlme_priv *pbuddy_mlmepriv = &pbuddy_adapter->mlmepriv;
++ //struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv;
++ u8 val8;
++_func_enter_;
++
++ if ( check_buddy_fwstate(padapter, _FW_LINKED ) )
++ {
++ PADAPTER pbuddy_adapter = padapter->pbuddy_adapter;
++ struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv;
++
++ pwdinfo->operating_channel = pbuddy_mlmeext->cur_channel;
++
++ if( pwdinfo->driver_interface == DRIVER_CFG80211 )
++ {
++ DBG_871X("%s, switch ch back to buddy's cur_channel=%d\n", __func__, pbuddy_mlmeext->cur_channel);
++
++ set_channel_bwmode(padapter, pbuddy_mlmeext->cur_channel, pbuddy_mlmeext->cur_ch_offset, pbuddy_mlmeext->cur_bwmode);
++
++ issue_nulldata(pbuddy_adapter, NULL, 0, 3, 500);
++ }
++ else if( pwdinfo->driver_interface == DRIVER_WEXT )
++ {
++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE))
++ {
++ // Now, the driver stays on the AP's channel.
++ // If the pwdinfo->ext_listen_period = 0, that means the P2P listen state is not available on listen channel.
++ if ( pwdinfo->ext_listen_period > 0 )
++ {
++ DBG_8192C( "[%s] P2P_STATE_IDLE, ext_listen_period = %d\n", __FUNCTION__, pwdinfo->ext_listen_period );
++
++ if ( pbuddy_mlmeext->cur_channel != pwdinfo->listen_channel )
++ {
++ // Will switch to listen channel so that need to send the NULL data with PW bit to AP.
++ issue_nulldata(pbuddy_adapter, NULL, 1, 3, 500);
++ set_channel_bwmode(padapter, pwdinfo->listen_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HT_CHANNEL_WIDTH_20);
++ }
++
++ rtw_p2p_set_state(pwdinfo, P2P_STATE_LISTEN);
++ val8 = 1;
++ rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));
++
++ // Todo: To check the value of pwdinfo->ext_listen_period is equal to 0 or not.
++ _set_timer( &pwdinfo->ap_p2p_switch_timer, pwdinfo->ext_listen_period );
++ }
++ }
++ else if ( rtw_p2p_chk_state(pwdinfo, P2P_STATE_LISTEN) ||
++ rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_FAIL) ||
++ ( rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING) && pwdinfo->nego_req_info.benable == _FALSE ) ||
++ rtw_p2p_chk_state(pwdinfo, P2P_STATE_RX_PROVISION_DIS_REQ) )
++ {
++ // Now, the driver is in the listen state of P2P mode.
++ DBG_8192C( "[%s] P2P_STATE_IDLE, ext_listen_interval = %d\n", __FUNCTION__, pwdinfo->ext_listen_interval );
++
++ // Commented by Albert 2012/11/01
++ // If the AP's channel is the same as the listen channel, we should still be in the listen state
++ // Other P2P device is still able to find this device out even this device is in the AP's channel.
++ // So, configure this device to be able to receive the probe request frame and set it to listen state.
++ if ( pbuddy_mlmeext->cur_channel != pwdinfo->listen_channel )
++ {
++ set_channel_bwmode(padapter, pbuddy_mlmeext->cur_channel, pbuddy_mlmeext->cur_ch_offset, pbuddy_mlmeext->cur_bwmode);
++ val8 = 0;
++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));
++ rtw_p2p_set_state(pwdinfo, P2P_STATE_IDLE);
++ issue_nulldata(pbuddy_adapter, NULL, 0, 3, 500);
++ }
++
++ // Todo: To check the value of pwdinfo->ext_listen_interval is equal to 0 or not.
++ _set_timer( &pwdinfo->ap_p2p_switch_timer, pwdinfo->ext_listen_interval );
++ }
++ else if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_OK))
++ {
++ // The driver had finished the P2P handshake successfully.
++ val8 = 0;
++ rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));
++ set_channel_bwmode(padapter, pbuddy_mlmeext->cur_channel, pbuddy_mlmeext->cur_ch_offset, pbuddy_mlmeext->cur_bwmode);
++ issue_nulldata(pbuddy_adapter, NULL, 0, 3, 500);
++ }
++ else if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_PROVISION_DIS_REQ))
++ {
++ val8 = 1;
++ set_channel_bwmode(padapter, pwdinfo->tx_prov_disc_info.peer_channel_num[0], HAL_PRIME_CHNL_OFFSET_DONT_CARE, HT_CHANNEL_WIDTH_20);
++ rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));
++ issue_probereq_p2p(padapter, NULL);
++ _set_timer( &pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT );
++ }
++ else if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING) && pwdinfo->nego_req_info.benable == _TRUE)
++ {
++ val8 = 1;
++ set_channel_bwmode(padapter, pwdinfo->nego_req_info.peer_channel_num[0], HAL_PRIME_CHNL_OFFSET_DONT_CARE, HT_CHANNEL_WIDTH_20);
++ rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));
++ issue_probereq_p2p(padapter, NULL);
++ _set_timer( &pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT );
++ }
++ else if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_INVITE_REQ ) && pwdinfo->invitereq_info.benable == _TRUE)
++ {
++ /*
++ val8 = 1;
++ set_channel_bwmode(padapter, , HAL_PRIME_CHNL_OFFSET_DONT_CARE, HT_CHANNEL_WIDTH_20);
++ rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));
++ issue_probereq_p2p(padapter, NULL);
++ _set_timer( &pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT );
++ */
++ }
++ }
++ }
++ else
++ {
++ set_channel_bwmode( padapter, pwdinfo->listen_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HT_CHANNEL_WIDTH_20);
++ }
++
++_func_exit_;
++}
++#endif
++
++#ifdef CONFIG_IOCTL_CFG80211
++static void ro_ch_handler(_adapter *padapter)
++{
++ struct cfg80211_wifidirect_info *pcfg80211_wdinfo = &padapter->cfg80211_wdinfo;
++ struct wifidirect_info *pwdinfo = &padapter->wdinfo;
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ u8 ch, bw, offset;
++_func_enter_;
++
++ if (rtw_get_ch_setting_union(padapter, &ch, &bw, &offset) != 0) {
++ if (0)
++ DBG_871X(FUNC_ADPT_FMT" back to linked union - ch:%u, bw:%u, offset:%u\n",
++ FUNC_ADPT_ARG(padapter), ch, bw, offset);
++ }
++ else if (wdev_to_priv(padapter->rtw_wdev)->p2p_enabled && pwdinfo->listen_channel) {
++ ch = pwdinfo->listen_channel;
++ bw = HT_CHANNEL_WIDTH_20;
++ offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++ if (0)
++ DBG_871X(FUNC_ADPT_FMT" back to listen ch - ch:%u, bw:%u, offset:%u\n",
++ FUNC_ADPT_ARG(padapter), ch, bw, offset);
++ }
++ else {
++ ch = pcfg80211_wdinfo->restore_channel;
++ bw = HT_CHANNEL_WIDTH_20;
++ offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++ if (0)
++ DBG_871X(FUNC_ADPT_FMT" back to restore ch - ch:%u, bw:%u, offset:%u\n",
++ FUNC_ADPT_ARG(padapter), ch, bw, offset);
++ }
++
++ set_channel_bwmode(padapter, ch, offset, bw);
++
++ rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo));
++#ifdef CONFIG_DEBUG_CFG80211
++ DBG_871X("%s, role=%d, p2p_state=%d\n", __func__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo));
++#endif
++
++ pcfg80211_wdinfo->is_ro_ch = _FALSE;
++
++ DBG_871X("cfg80211_remain_on_channel_expired\n");
++
++ rtw_cfg80211_remain_on_channel_expired(padapter,
++ pcfg80211_wdinfo->remain_on_ch_cookie,
++ &pcfg80211_wdinfo->remain_on_ch_channel,
++ pcfg80211_wdinfo->remain_on_ch_type, GFP_KERNEL);
++
++_func_exit_;
++}
++
++static void ro_ch_timer_process (void *FunctionContext)
++{
++ _adapter *adapter = (_adapter *)FunctionContext;
++ struct rtw_wdev_priv *pwdev_priv = wdev_to_priv(adapter->rtw_wdev);
++
++ //printk("%s \n", __FUNCTION__);
++
++#ifdef CONFIG_CONCURRENT_MODE
++ ATOMIC_SET(&pwdev_priv->ro_ch_to, 1);
++#endif
++
++ p2p_protocol_wk_cmd( adapter, P2P_RO_CH_WK);
++}
++
++static void rtw_change_p2pie_op_ch(_adapter *padapter, const u8 *frame_body, u32 len, u8 ch)
++{
++ u8 *ies, *p2p_ie;
++ u32 ies_len, p2p_ielen;
++ PADAPTER pbuddy_adapter = padapter->pbuddy_adapter;
++ struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv;
++
++ ies = (u8*)(frame_body + _PUBLIC_ACTION_IE_OFFSET_);
++ ies_len = len - _PUBLIC_ACTION_IE_OFFSET_;
++
++ p2p_ie = rtw_get_p2p_ie( ies, ies_len, NULL, &p2p_ielen );
++
++ while ( p2p_ie ) {
++ u32 attr_contentlen = 0;
++ u8 *pattr = NULL;
++
++ //Check P2P_ATTR_OPERATING_CH
++ attr_contentlen = 0;
++ pattr = NULL;
++ if((pattr = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, (uint*)&attr_contentlen))!=NULL)
++ {
++ *(pattr+4) = ch;
++ }
++
++ //Get the next P2P IE
++ p2p_ie = rtw_get_p2p_ie(p2p_ie+p2p_ielen, ies_len -(p2p_ie -ies + p2p_ielen), NULL, &p2p_ielen);
++ }
++}
++
++static void rtw_change_p2pie_ch_list(_adapter *padapter, const u8 *frame_body, u32 len, u8 ch)
++{
++ u8 *ies, *p2p_ie;
++ u32 ies_len, p2p_ielen;
++ PADAPTER pbuddy_adapter = padapter->pbuddy_adapter;
++ struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv;
++
++ ies = (u8*)(frame_body + _PUBLIC_ACTION_IE_OFFSET_);
++ ies_len = len - _PUBLIC_ACTION_IE_OFFSET_;
++
++ p2p_ie = rtw_get_p2p_ie( ies, ies_len, NULL, &p2p_ielen );
++
++ while (p2p_ie) {
++ u32 attr_contentlen = 0;
++ u8 *pattr = NULL;
++
++ //Check P2P_ATTR_CH_LIST
++ if ((pattr=rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CH_LIST, NULL, (uint*)&attr_contentlen))!=NULL) {
++ int i;
++ u32 num_of_ch;
++ u8 *pattr_temp = pattr + 3 ;
++
++ attr_contentlen -= 3;
++
++ while (attr_contentlen>0) {
++ num_of_ch = *(pattr_temp+1);
++
++ for(i=0; i<num_of_ch; i++)
++ *(pattr_temp+2+i) = ch;
++
++ pattr_temp += (2+num_of_ch);
++ attr_contentlen -= (2+num_of_ch);
++ }
++ }
++
++ //Get the next P2P IE
++ p2p_ie = rtw_get_p2p_ie(p2p_ie+p2p_ielen, ies_len -(p2p_ie -ies + p2p_ielen), NULL, &p2p_ielen);
++ }
++}
++
++static bool rtw_chk_p2pie_ch_list_with_buddy(_adapter *padapter, const u8 *frame_body, u32 len)
++{
++ bool fit = _FALSE;
++#ifdef CONFIG_CONCURRENT_MODE
++ u8 *ies, *p2p_ie;
++ u32 ies_len, p2p_ielen;
++ PADAPTER pbuddy_adapter = padapter->pbuddy_adapter;
++ struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv;
++ u8 buddy_ch = pbuddy_mlmeext->cur_channel;
++
++ ies = (u8*)(frame_body + _PUBLIC_ACTION_IE_OFFSET_);
++ ies_len = len - _PUBLIC_ACTION_IE_OFFSET_;
++
++ p2p_ie = rtw_get_p2p_ie( ies, ies_len, NULL, &p2p_ielen );
++
++ while (p2p_ie) {
++ u32 attr_contentlen = 0;
++ u8 *pattr = NULL;
++
++ //Check P2P_ATTR_CH_LIST
++ if ((pattr=rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CH_LIST, NULL, (uint*)&attr_contentlen))!=NULL) {
++ int i;
++ u32 num_of_ch;
++ u8 *pattr_temp = pattr + 3 ;
++
++ attr_contentlen -= 3;
++
++ while (attr_contentlen>0) {
++ num_of_ch = *(pattr_temp+1);
++
++ for(i=0; i<num_of_ch; i++) {
++ if (*(pattr_temp+2+i) == buddy_ch) {
++ DBG_871X(FUNC_ADPT_FMT" ch_list fit buddy_ch:%u\n", FUNC_ADPT_ARG(padapter), buddy_ch);
++ fit = _TRUE;
++ break;
++ }
++ }
++
++ pattr_temp += (2+num_of_ch);
++ attr_contentlen -= (2+num_of_ch);
++ }
++ }
++
++ //Get the next P2P IE
++ p2p_ie = rtw_get_p2p_ie(p2p_ie+p2p_ielen, ies_len -(p2p_ie -ies + p2p_ielen), NULL, &p2p_ielen);
++ }
++#endif
++ return fit;
++}
++
++static bool rtw_chk_p2pie_op_ch_with_buddy(_adapter *padapter, const u8 *frame_body, u32 len)
++{
++ bool fit = _FALSE;
++#ifdef CONFIG_CONCURRENT_MODE
++ u8 *ies, *p2p_ie;
++ u32 ies_len, p2p_ielen;
++ PADAPTER pbuddy_adapter = padapter->pbuddy_adapter;
++ struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv;
++ u8 buddy_ch = pbuddy_mlmeext->cur_channel;
++
++ ies = (u8*)(frame_body + _PUBLIC_ACTION_IE_OFFSET_);
++ ies_len = len - _PUBLIC_ACTION_IE_OFFSET_;
++
++ p2p_ie = rtw_get_p2p_ie( ies, ies_len, NULL, &p2p_ielen );
++
++ while (p2p_ie) {
++ u32 attr_contentlen = 0;
++ u8 *pattr = NULL;
++
++ //Check P2P_ATTR_OPERATING_CH
++ attr_contentlen = 0;
++ pattr = NULL;
++ if((pattr = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, (uint*)&attr_contentlen))!=NULL) {
++ if (*(pattr+4) == buddy_ch) {
++ DBG_871X(FUNC_ADPT_FMT" op_ch fit buddy_ch:%u\n", FUNC_ADPT_ARG(padapter), buddy_ch);
++ fit = _TRUE;
++ break;
++ }
++ }
++
++ //Get the next P2P IE
++ p2p_ie = rtw_get_p2p_ie(p2p_ie+p2p_ielen, ies_len -(p2p_ie -ies + p2p_ielen), NULL, &p2p_ielen);
++ }
++#endif
++ return fit;
++}
++
++static void rtw_cfg80211_adjust_p2pie_channel(_adapter *padapter, const u8 *frame_body, u32 len)
++{
++#ifdef CONFIG_CONCURRENT_MODE
++ u8 *ies, *p2p_ie;
++ u32 ies_len, p2p_ielen;
++ PADAPTER pbuddy_adapter = padapter->pbuddy_adapter;
++ struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv;
++
++ ies = (u8*)(frame_body + _PUBLIC_ACTION_IE_OFFSET_);
++ ies_len = len - _PUBLIC_ACTION_IE_OFFSET_;
++
++ p2p_ie = rtw_get_p2p_ie( ies, ies_len, NULL, &p2p_ielen );
++
++ while ( p2p_ie )
++ {
++ u32 attr_contentlen = 0;
++ u8 *pattr = NULL;
++
++ //Check P2P_ATTR_CH_LIST
++ if((pattr=rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CH_LIST, NULL, (uint*)&attr_contentlen))!=NULL)
++ {
++ int i;
++ u32 num_of_ch;
++ u8 *pattr_temp = pattr + 3 ;
++
++ attr_contentlen -= 3;
++
++ while(attr_contentlen>0)
++ {
++ num_of_ch = *(pattr_temp+1);
++
++ for(i=0; i<num_of_ch; i++)
++ *(pattr_temp+2+i) = pbuddy_mlmeext->cur_channel;//forcing to the same channel
++
++ pattr_temp += (2+num_of_ch);
++ attr_contentlen -= (2+num_of_ch);
++ }
++ }
++
++ //Check P2P_ATTR_OPERATING_CH
++ attr_contentlen = 0;
++ pattr = NULL;
++ if((pattr = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, (uint*)&attr_contentlen))!=NULL)
++ {
++ *(pattr+4) = pbuddy_mlmeext->cur_channel;//forcing to the same channel
++ }
++
++ //Get the next P2P IE
++ p2p_ie = rtw_get_p2p_ie(p2p_ie+p2p_ielen, ies_len -(p2p_ie -ies + p2p_ielen), NULL, &p2p_ielen);
++
++ }
++
++#endif
++}
++
++#ifdef CONFIG_WFD
++void rtw_append_wfd_ie(_adapter *padapter, u8 *buf, u32* len)
++{
++ unsigned char *frame_body;
++ u8 category, action, OUI_Subtype, dialogToken=0;
++ u32 wfdielen = 0;
++ struct rtw_wdev_priv *pwdev_priv = wdev_to_priv(padapter->rtw_wdev);
++
++ frame_body = (unsigned char *)(buf + sizeof(struct rtw_ieee80211_hdr_3addr));
++ category = frame_body[0];
++
++ if(category == RTW_WLAN_CATEGORY_PUBLIC)
++ {
++ action = frame_body[1];
++ if (action == ACT_PUBLIC_VENDOR
++ && _rtw_memcmp(frame_body+2, P2P_OUI, 4) == _TRUE
++ )
++ {
++ OUI_Subtype = frame_body[6];
++ dialogToken = frame_body[7];
++ switch( OUI_Subtype )//OUI Subtype
++ {
++ case P2P_GO_NEGO_REQ:
++ {
++ wfdielen = build_nego_req_wfd_ie( &padapter->wdinfo, buf + ( *len ) );
++ (*len) += wfdielen;
++ break;
++ }
++ case P2P_GO_NEGO_RESP:
++ {
++ wfdielen = build_nego_resp_wfd_ie( &padapter->wdinfo, buf + ( *len ) );
++ (*len) += wfdielen;
++ break;
++ }
++ case P2P_GO_NEGO_CONF:
++ {
++ wfdielen = build_nego_confirm_wfd_ie( &padapter->wdinfo, buf + ( *len ) );
++ (*len) += wfdielen;
++ break;
++ }
++ case P2P_INVIT_REQ:
++ {
++ wfdielen = build_invitation_req_wfd_ie( &padapter->wdinfo, buf + ( *len ) );
++ (*len) += wfdielen;
++ break;
++ }
++ case P2P_INVIT_RESP:
++ {
++ wfdielen = build_invitation_resp_wfd_ie( &padapter->wdinfo, buf + ( *len ) );
++ (*len) += wfdielen;
++ break;
++ }
++ case P2P_DEVDISC_REQ:
++ break;
++ case P2P_DEVDISC_RESP:
++
++ break;
++ case P2P_PROVISION_DISC_REQ:
++ {
++ wfdielen = build_provdisc_req_wfd_ie( &padapter->wdinfo, buf + ( *len ) );
++ (*len) += wfdielen;
++ break;
++ }
++ case P2P_PROVISION_DISC_RESP:
++ {
++ wfdielen = build_provdisc_resp_wfd_ie( &padapter->wdinfo, buf + ( *len ) );
++ (*len) += wfdielen;
++ break;
++ }
++ default:
++
++ break;
++ }
++
++ }
++
++ }
++ else if(category == RTW_WLAN_CATEGORY_P2P)
++ {
++ OUI_Subtype = frame_body[5];
++ dialogToken = frame_body[6];
++
++#ifdef CONFIG_DEBUG_CFG80211
++ DBG_871X("ACTION_CATEGORY_P2P: OUI=0x%x, OUI_Subtype=%d, dialogToken=%d\n",
++ cpu_to_be32( *( ( u32* ) ( frame_body + 1 ) ) ), OUI_Subtype, dialogToken);
++#endif
++
++ switch(OUI_Subtype)
++ {
++ case P2P_NOTICE_OF_ABSENCE:
++
++ break;
++ case P2P_PRESENCE_REQUEST:
++
++ break;
++ case P2P_PRESENCE_RESPONSE:
++
++ break;
++ case P2P_GO_DISC_REQUEST:
++
++ break;
++ default:
++
++ break;
++ }
++
++ }
++ else
++ {
++ DBG_871X("%s, action frame category=%d\n", __func__, category);
++ //is_p2p_frame = (-1);
++ }
++
++ return;
++}
++#endif
++
++u8 *dump_p2p_attr_ch_list(u8 *p2p_ie, uint p2p_ielen, u8 *buf, u32 buf_len)
++{
++ uint attr_contentlen = 0;
++ u8 *pattr = NULL;
++ int w_sz = 0;
++ u8 ch_cnt = 0;
++ u8 ch_list[40];
++ bool continuous = _FALSE;
++
++ if ((pattr=rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CH_LIST, NULL, &attr_contentlen))!=NULL) {
++ int i, j;
++ u32 num_of_ch;
++ u8 *pattr_temp = pattr + 3 ;
++
++ attr_contentlen -= 3;
++
++ _rtw_memset(ch_list, 0, 40);
++
++ while (attr_contentlen>0) {
++ num_of_ch = *(pattr_temp+1);
++
++ for(i=0; i<num_of_ch; i++) {
++ for (j=0;j<ch_cnt;j++) {
++ if (ch_list[j] == *(pattr_temp+2+i))
++ break;
++ }
++ if (j>=ch_cnt)
++ ch_list[ch_cnt++] = *(pattr_temp+2+i);
++
++ }
++
++ pattr_temp += (2+num_of_ch);
++ attr_contentlen -= (2+num_of_ch);
++ }
++
++ for (j=0;j<ch_cnt;j++) {
++ if (j == 0) {
++ w_sz += snprintf(buf+w_sz, buf_len-w_sz, "%u", ch_list[j]);
++ } else if (ch_list[j] - ch_list[j-1] != 1) {
++ w_sz += snprintf(buf+w_sz, buf_len-w_sz, ", %u", ch_list[j]);
++ } else if (j != ch_cnt-1 && ch_list[j+1] - ch_list[j] == 1) {
++ /* empty */
++ } else {
++ w_sz += snprintf(buf+w_sz, buf_len-w_sz, "-%u", ch_list[j]);
++ }
++ }
++ }
++ return buf;
++}
++
++/*
++ * return _TRUE if requester is GO, _FALSE if responder is GO
++ */
++bool rtw_p2p_nego_intent_compare(u8 req, u8 resp)
++{
++ if (req>>1 == resp >>1)
++ return req&0x01 ? _TRUE : _FALSE;
++ else if (req>>1 > resp>>1)
++ return _TRUE;
++ else
++ return _FALSE;
++}
++
++int rtw_p2p_check_frames(_adapter *padapter, const u8 *buf, u32 len, u8 tx)
++{
++ int is_p2p_frame = (-1);
++ unsigned char *frame_body;
++ u8 category, action, OUI_Subtype, dialogToken=0;
++ u8 *p2p_ie = NULL;
++ uint p2p_ielen = 0;
++ struct rtw_wdev_priv *pwdev_priv = wdev_to_priv(padapter->rtw_wdev);
++ int status = -1;
++ u8 ch_list_buf[128] = {'\0'};
++ int op_ch = -1;
++ int listen_ch = -1;
++ u8 intent = 0;
++
++ frame_body = (unsigned char *)(buf + sizeof(struct rtw_ieee80211_hdr_3addr));
++ category = frame_body[0];
++ //just for check
++ if(category == RTW_WLAN_CATEGORY_PUBLIC)
++ {
++ action = frame_body[1];
++ if (action == ACT_PUBLIC_VENDOR
++ && _rtw_memcmp(frame_body+2, P2P_OUI, 4) == _TRUE
++ )
++ {
++ OUI_Subtype = frame_body[6];
++ dialogToken = frame_body[7];
++ is_p2p_frame = OUI_Subtype;
++ #ifdef CONFIG_DEBUG_CFG80211
++ DBG_871X("ACTION_CATEGORY_PUBLIC: ACT_PUBLIC_VENDOR, OUI=0x%x, OUI_Subtype=%d, dialogToken=%d\n",
++ cpu_to_be32( *( ( u32* ) ( frame_body + 2 ) ) ), OUI_Subtype, dialogToken);
++ #endif
++
++ p2p_ie = rtw_get_p2p_ie(
++ (u8 *)buf+sizeof(struct rtw_ieee80211_hdr_3addr)+_PUBLIC_ACTION_IE_OFFSET_,
++ len-sizeof(struct rtw_ieee80211_hdr_3addr)-_PUBLIC_ACTION_IE_OFFSET_,
++ NULL, &p2p_ielen);
++
++ switch( OUI_Subtype )//OUI Subtype
++ {
++ u8 *cont;
++ uint cont_len;
++ case P2P_GO_NEGO_REQ:
++ {
++ struct rtw_wdev_nego_info* nego_info = &pwdev_priv->nego_info;
++
++ if (tx) {
++ #ifdef CONFIG_DRV_ISSUE_PROV_REQ // IOT FOR S2
++ if(pwdev_priv->provdisc_req_issued == _FALSE) {
++ rtw_cfg80211_issue_p2p_provision_request(padapter, buf, len);
++ pwdev_priv->provdisc_req_issued = _TRUE;
++ rtw_msleep_os(200);
++ }
++ #endif //CONFIG_DRV_ISSUE_PROV_REQ
++
++ #ifdef CONFIG_CONCURRENT_MODE
++ if(check_buddy_fwstate(padapter, _FW_LINKED))
++ rtw_cfg80211_adjust_p2pie_channel(padapter, frame_body, len-sizeof(struct rtw_ieee80211_hdr_3addr));
++ #endif
++ }
++
++ if ((cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, &cont_len)))
++ op_ch = *(cont+4);
++ if ((cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_LISTEN_CH, NULL, &cont_len)))
++ listen_ch = *(cont+4);
++ if ((cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GO_INTENT, NULL, &cont_len)))
++ intent = *cont;
++
++ if (nego_info->token != dialogToken)
++ rtw_wdev_nego_info_init(nego_info);
++
++ _rtw_memcpy(nego_info->peer_mac, tx ? GetAddr1Ptr(buf) : GetAddr2Ptr(buf), ETH_ALEN);
++ nego_info->active = tx ? 1 : 0;
++ nego_info->token = dialogToken;
++ nego_info->req_op_ch = op_ch;
++ nego_info->req_listen_ch = listen_ch;
++ nego_info->req_intent = intent;
++ nego_info->state = 0;
++
++ dump_p2p_attr_ch_list(p2p_ie, p2p_ielen, ch_list_buf, 128);
++ DBG_871X("RTW_%s:P2P_GO_NEGO_REQ, dialogToken=%d, intent:%u%s, listen_ch:%d, op_ch:%d, ch_list:%s\n",
++ (tx==_TRUE)?"Tx":"Rx", dialogToken, (intent>>1), intent&0x1 ? "+" : "-", listen_ch, op_ch, ch_list_buf);
++
++ if (!tx) {
++ #ifdef CONFIG_CONCURRENT_MODE
++ if(check_buddy_fwstate(padapter, _FW_LINKED)
++ && rtw_chk_p2pie_ch_list_with_buddy(padapter, frame_body, len-sizeof(struct rtw_ieee80211_hdr_3addr)) == _FALSE)
++ {
++ DBG_871X(FUNC_ADPT_FMT" ch_list has no intersect with buddy\n", FUNC_ADPT_ARG(padapter));
++ rtw_change_p2pie_ch_list(padapter, frame_body, len-sizeof(struct rtw_ieee80211_hdr_3addr), 0);
++ }
++ #endif
++ }
++
++ break;
++ }
++ case P2P_GO_NEGO_RESP:
++ {
++ struct rtw_wdev_nego_info* nego_info = &pwdev_priv->nego_info;
++
++ if (tx) {
++ #ifdef CONFIG_CONCURRENT_MODE
++ if(check_buddy_fwstate(padapter, _FW_LINKED))
++ rtw_cfg80211_adjust_p2pie_channel(padapter, frame_body, len-sizeof(struct rtw_ieee80211_hdr_3addr));
++ #endif
++ }
++
++ if ((cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, &cont_len)))
++ op_ch = *(cont+4);
++ if ((cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GO_INTENT, NULL, &cont_len)))
++ intent = *cont;
++ if ((cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_STATUS, NULL, &cont_len)))
++ status = *cont;
++
++ if (nego_info->token == dialogToken && nego_info->state == 0
++ && _rtw_memcmp(nego_info->peer_mac, tx ? GetAddr1Ptr(buf) : GetAddr2Ptr(buf), ETH_ALEN) == _TRUE
++ ) {
++ nego_info->status = (status==-1) ? 0xff : status;
++ nego_info->rsp_op_ch= op_ch;
++ nego_info->rsp_intent = intent;
++ nego_info->state = 1;
++ if (status != 0)
++ nego_info->token = 0; /* init */
++ }
++
++ dump_p2p_attr_ch_list(p2p_ie, p2p_ielen, ch_list_buf, 128);
++ DBG_871X("RTW_%s:P2P_GO_NEGO_RESP, dialogToken=%d, intent:%u%s, status:%d, op_ch:%d, ch_list:%s\n",
++ (tx==_TRUE)?"Tx":"Rx", dialogToken, (intent>>1), intent&0x1 ? "+" : "-", status, op_ch, ch_list_buf);
++
++ if (!tx) {
++ pwdev_priv->provdisc_req_issued = _FALSE;
++ #ifdef CONFIG_CONCURRENT_MODE
++ if(check_buddy_fwstate(padapter, _FW_LINKED)
++ && rtw_chk_p2pie_ch_list_with_buddy(padapter, frame_body, len-sizeof(struct rtw_ieee80211_hdr_3addr)) == _FALSE)
++ {
++ DBG_871X(FUNC_ADPT_FMT" ch_list has no intersect with buddy\n", FUNC_ADPT_ARG(padapter));
++ rtw_change_p2pie_ch_list(padapter, frame_body, len-sizeof(struct rtw_ieee80211_hdr_3addr), 0);
++ }
++ #endif
++ }
++
++ break;
++ }
++ case P2P_GO_NEGO_CONF:
++ {
++ struct rtw_wdev_nego_info* nego_info = &pwdev_priv->nego_info;
++ bool is_go = _FALSE;
++
++ if (tx) {
++ #ifdef CONFIG_CONCURRENT_MODE
++ if(check_buddy_fwstate(padapter, _FW_LINKED))
++ rtw_cfg80211_adjust_p2pie_channel(padapter, frame_body, len-sizeof(struct rtw_ieee80211_hdr_3addr));
++ #endif
++ }
++
++ if ((cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, &cont_len)))
++ op_ch = *(cont+4);
++ if ((cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_STATUS, NULL, &cont_len)))
++ status = *cont;
++
++ if (nego_info->token == dialogToken && nego_info->state == 1
++ && _rtw_memcmp(nego_info->peer_mac, tx ? GetAddr1Ptr(buf) : GetAddr2Ptr(buf), ETH_ALEN) == _TRUE
++ ) {
++ nego_info->status = (status==-1) ? 0xff : status;
++ nego_info->conf_op_ch = (op_ch==-1) ? 0 : op_ch;
++ nego_info->state = 2;
++
++ if (status == 0) {
++ if (rtw_p2p_nego_intent_compare(nego_info->req_intent, nego_info->rsp_intent) && tx)
++ is_go = _TRUE;
++ }
++
++ nego_info->token = 0; /* init */
++ }
++
++ dump_p2p_attr_ch_list(p2p_ie, p2p_ielen, ch_list_buf, 128);
++ DBG_871X("RTW_%s:P2P_GO_NEGO_CONF, dialogToken=%d, status:%d, op_ch:%d, ch_list:%s\n",
++ (tx==_TRUE)?"Tx":"Rx", dialogToken, status, op_ch, ch_list_buf);
++
++ if (!tx) {
++ }
++
++ break;
++ }
++ case P2P_INVIT_REQ:
++ {
++ struct rtw_wdev_invit_info* invit_info = &pwdev_priv->invit_info;
++ int flags = -1;
++
++ if (tx) {
++ #ifdef CONFIG_CONCURRENT_MODE
++ if(check_buddy_fwstate(padapter, _FW_LINKED))
++ rtw_cfg80211_adjust_p2pie_channel(padapter, frame_body, len-sizeof(struct rtw_ieee80211_hdr_3addr));
++ #endif
++ }
++
++ if ((cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_INVITATION_FLAGS, NULL, &cont_len)))
++ flags = *cont;
++ if ((cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, &cont_len)))
++ op_ch = *(cont+4);
++
++ if (invit_info->token != dialogToken)
++ rtw_wdev_invit_info_init(invit_info);
++
++ _rtw_memcpy(invit_info->peer_mac, tx ? GetAddr1Ptr(buf) : GetAddr2Ptr(buf), ETH_ALEN);
++ invit_info->active = tx ? 1 : 0;
++ invit_info->token = dialogToken;
++ invit_info->flags = (flags==-1) ? 0x0 : flags;
++ invit_info->req_op_ch= op_ch;
++ invit_info->state = 0;
++
++ dump_p2p_attr_ch_list(p2p_ie, p2p_ielen, ch_list_buf, 128);
++ DBG_871X("RTW_%s:P2P_INVIT_REQ, dialogToken=%d, flags:0x%02x, op_ch:%d, ch_list:%s\n",
++ (tx==_TRUE)?"Tx":"Rx", dialogToken, flags, op_ch, ch_list_buf);
++
++ if (!tx) {
++ #ifdef CONFIG_CONCURRENT_MODE
++ if(check_buddy_fwstate(padapter, _FW_LINKED)) {
++ if (op_ch != -1 && rtw_chk_p2pie_op_ch_with_buddy(padapter, frame_body, len-sizeof(struct rtw_ieee80211_hdr_3addr)) == _FALSE) {
++ DBG_871X(FUNC_ADPT_FMT" op_ch:%u has no intersect with buddy\n", FUNC_ADPT_ARG(padapter), op_ch);
++ rtw_change_p2pie_ch_list(padapter, frame_body, len-sizeof(struct rtw_ieee80211_hdr_3addr), 0);
++ } else if (rtw_chk_p2pie_ch_list_with_buddy(padapter, frame_body, len-sizeof(struct rtw_ieee80211_hdr_3addr)) == _FALSE) {
++ DBG_871X(FUNC_ADPT_FMT" ch_list has no intersect with buddy\n", FUNC_ADPT_ARG(padapter));
++ rtw_change_p2pie_ch_list(padapter, frame_body, len-sizeof(struct rtw_ieee80211_hdr_3addr), 0);
++ }
++ }
++ #endif
++ }
++
++ break;
++ }
++ case P2P_INVIT_RESP:
++ {
++ struct rtw_wdev_invit_info* invit_info = &pwdev_priv->invit_info;
++
++ if (tx) {
++ #ifdef CONFIG_CONCURRENT_MODE
++ if(check_buddy_fwstate(padapter, _FW_LINKED))
++ rtw_cfg80211_adjust_p2pie_channel(padapter, frame_body, len-sizeof(struct rtw_ieee80211_hdr_3addr));
++ #endif
++ }
++
++ if ((cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_STATUS, NULL, &cont_len)))
++ {
++#ifdef CONFIG_P2P_INVITE_IOT
++ if(tx && *cont==7)
++ {
++ DBG_871X("TX_P2P_INVITE_RESP, status is no common channel, change to unknown group\n");
++ *cont = 8; //unknow group status
++ }
++#endif //CONFIG_P2P_INVITE_IOT
++ status = *cont;
++ }
++ if ((cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, &cont_len)))
++ op_ch = *(cont+4);
++
++ if (invit_info->token == dialogToken && invit_info->state == 0
++ && _rtw_memcmp(invit_info->peer_mac, tx ? GetAddr1Ptr(buf) : GetAddr2Ptr(buf), ETH_ALEN) == _TRUE
++ ) {
++ invit_info->status = (status==-1) ? 0xff : status;
++ invit_info->rsp_op_ch= op_ch;
++ invit_info->state = 1;
++ invit_info->token = 0; /* init */
++ }
++
++ dump_p2p_attr_ch_list(p2p_ie, p2p_ielen, ch_list_buf, 128);
++ DBG_871X("RTW_%s:P2P_INVIT_RESP, dialogToken=%d, status:%d, op_ch:%d, ch_list:%s\n",
++ (tx==_TRUE)?"Tx":"Rx", dialogToken, status, op_ch, ch_list_buf);
++
++ if (!tx) {
++ }
++
++ break;
++ }
++ case P2P_DEVDISC_REQ:
++ DBG_871X("RTW_%s:P2P_DEVDISC_REQ, dialogToken=%d\n", (tx==_TRUE)?"Tx":"Rx", dialogToken);
++ break;
++ case P2P_DEVDISC_RESP:
++ cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_STATUS, NULL, &cont_len);
++ DBG_871X("RTW_%s:P2P_DEVDISC_RESP, dialogToken=%d, status:%d\n", (tx==_TRUE)?"Tx":"Rx", dialogToken, cont?*cont:-1);
++ break;
++ case P2P_PROVISION_DISC_REQ:
++ {
++ size_t frame_body_len = len - sizeof(struct rtw_ieee80211_hdr_3addr);
++ u8 *p2p_ie;
++ uint p2p_ielen = 0;
++ uint contentlen = 0;
++
++ DBG_871X("RTW_%s:P2P_PROVISION_DISC_REQ, dialogToken=%d\n", (tx==_TRUE)?"Tx":"Rx", dialogToken);
++
++ //if(tx)
++ {
++ pwdev_priv->provdisc_req_issued = _FALSE;
++
++ if( (p2p_ie=rtw_get_p2p_ie( frame_body + _PUBLIC_ACTION_IE_OFFSET_, frame_body_len - _PUBLIC_ACTION_IE_OFFSET_, NULL, &p2p_ielen)))
++ {
++
++ if(rtw_get_p2p_attr_content( p2p_ie, p2p_ielen, P2P_ATTR_GROUP_ID, NULL, &contentlen))
++ {
++ pwdev_priv->provdisc_req_issued = _FALSE;//case: p2p_client join p2p GO
++ }
++ else
++ {
++ #ifdef CONFIG_DEBUG_CFG80211
++ DBG_871X("provdisc_req_issued is _TRUE\n");
++ #endif //CONFIG_DEBUG_CFG80211
++ pwdev_priv->provdisc_req_issued = _TRUE;//case: p2p_devices connection before Nego req.
++ }
++
++ }
++ }
++ }
++ break;
++ case P2P_PROVISION_DISC_RESP:
++ DBG_871X("RTW_%s:P2P_PROVISION_DISC_RESP, dialogToken=%d\n", (tx==_TRUE)?"Tx":"Rx", dialogToken);
++ break;
++ default:
++ DBG_871X("RTW_%s:OUI_Subtype=%d, dialogToken=%d\n", (tx==_TRUE)?"Tx":"Rx", OUI_Subtype, dialogToken);
++ break;
++ }
++
++ }
++
++ }
++ else if(category == RTW_WLAN_CATEGORY_P2P)
++ {
++ OUI_Subtype = frame_body[5];
++ dialogToken = frame_body[6];
++
++ #ifdef CONFIG_DEBUG_CFG80211
++ DBG_871X("ACTION_CATEGORY_P2P: OUI=0x%x, OUI_Subtype=%d, dialogToken=%d\n",
++ cpu_to_be32( *( ( u32* ) ( frame_body + 1 ) ) ), OUI_Subtype, dialogToken);
++ #endif
++
++ is_p2p_frame = OUI_Subtype;
++
++ switch(OUI_Subtype)
++ {
++ case P2P_NOTICE_OF_ABSENCE:
++ DBG_871X("RTW_%s:P2P_NOTICE_OF_ABSENCE, dialogToken=%d\n", (tx==_TRUE)?"TX":"RX", dialogToken);
++ break;
++ case P2P_PRESENCE_REQUEST:
++ DBG_871X("RTW_%s:P2P_PRESENCE_REQUEST, dialogToken=%d\n", (tx==_TRUE)?"TX":"RX", dialogToken);
++ break;
++ case P2P_PRESENCE_RESPONSE:
++ DBG_871X("RTW_%s:P2P_PRESENCE_RESPONSE, dialogToken=%d\n", (tx==_TRUE)?"TX":"RX", dialogToken);
++ break;
++ case P2P_GO_DISC_REQUEST:
++ DBG_871X("RTW_%s:P2P_GO_DISC_REQUEST, dialogToken=%d\n", (tx==_TRUE)?"TX":"RX", dialogToken);
++ break;
++ default:
++ DBG_871X("RTW_%s:OUI_Subtype=%d, dialogToken=%d\n", (tx==_TRUE)?"TX":"RX", OUI_Subtype, dialogToken);
++ break;
++ }
++
++ }
++ else
++ {
++ DBG_871X("RTW_%s:action frame category=%d\n", (tx==_TRUE)?"TX":"RX", category);
++ }
++
++ return is_p2p_frame;
++}
++
++void rtw_init_cfg80211_wifidirect_info( _adapter* padapter)
++{
++ struct cfg80211_wifidirect_info *pcfg80211_wdinfo = &padapter->cfg80211_wdinfo;
++
++ _rtw_memset(pcfg80211_wdinfo, 0x00, sizeof(struct cfg80211_wifidirect_info) );
++
++ _init_timer( &pcfg80211_wdinfo->remain_on_ch_timer, padapter->pnetdev, ro_ch_timer_process, padapter );
++}
++#endif //CONFIG_IOCTL_CFG80211
++
++void p2p_protocol_wk_hdl(_adapter *padapter, int intCmdType)
++{
++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo);
++
++_func_enter_;
++
++ switch(intCmdType)
++ {
++ case P2P_FIND_PHASE_WK:
++ {
++ find_phase_handler( padapter );
++ break;
++ }
++ case P2P_RESTORE_STATE_WK:
++ {
++ restore_p2p_state_handler( padapter );
++ break;
++ }
++ case P2P_PRE_TX_PROVDISC_PROCESS_WK:
++ {
++#ifdef CONFIG_CONCURRENT_MODE
++ if ( check_buddy_fwstate(padapter, _FW_LINKED ) )
++ {
++ p2p_concurrent_handler( padapter );
++ }
++ else
++ {
++ pre_tx_provdisc_handler( padapter );
++ }
++#else
++ pre_tx_provdisc_handler( padapter );
++#endif
++ break;
++ }
++ case P2P_PRE_TX_INVITEREQ_PROCESS_WK:
++ {
++#ifdef CONFIG_CONCURRENT_MODE
++ if ( check_buddy_fwstate(padapter, _FW_LINKED ) )
++ {
++ p2p_concurrent_handler( padapter );
++ }
++ else
++ {
++ pre_tx_invitereq_handler( padapter );
++ }
++#else
++ pre_tx_invitereq_handler( padapter );
++#endif
++ break;
++ }
++ case P2P_PRE_TX_NEGOREQ_PROCESS_WK:
++ {
++#ifdef CONFIG_CONCURRENT_MODE
++ if ( check_buddy_fwstate(padapter, _FW_LINKED ) )
++ {
++ p2p_concurrent_handler( padapter );
++ }
++ else
++ {
++ pre_tx_negoreq_handler( padapter );
++ }
++#else
++ pre_tx_negoreq_handler( padapter );
++#endif
++ break;
++ }
++#ifdef CONFIG_P2P
++#ifdef CONFIG_CONCURRENT_MODE
++ case P2P_AP_P2P_CH_SWITCH_PROCESS_WK:
++ {
++ p2p_concurrent_handler( padapter );
++ break;
++ }
++#endif
++#endif
++#ifdef CONFIG_IOCTL_CFG80211
++ case P2P_RO_CH_WK:
++ {
++ ro_ch_handler( padapter );
++ break;
++ }
++#endif //CONFIG_IOCTL_CFG80211
++
++ }
++
++_func_exit_;
++}
++
++#ifdef CONFIG_P2P_PS
++void process_p2p_ps_ie(PADAPTER padapter, u8 *IEs, u32 IELength)
++{
++ u8 * ies;
++ u32 ies_len;
++ u8 * p2p_ie;
++ u32 p2p_ielen = 0;
++ u8 noa_attr[MAX_P2P_IE_LEN] = { 0x00 };// NoA length should be n*(13) + 2
++ u32 attr_contentlen = 0;
++
++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo );
++ u8 find_p2p = _FALSE, find_p2p_ps = _FALSE;
++ u8 noa_offset, noa_num, noa_index;
++
++_func_enter_;
++
++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
++ {
++ return;
++ }
++
++#ifdef CONFIG_CONCURRENT_MODE
++ if(padapter->iface_type != IFACE_PORT0)
++ return;
++#endif
++ if(IELength <= _BEACON_IE_OFFSET_)
++ return;
++
++ ies = IEs + _BEACON_IE_OFFSET_;
++ ies_len = IELength - _BEACON_IE_OFFSET_;
++
++ p2p_ie = rtw_get_p2p_ie( ies, ies_len, NULL, &p2p_ielen);
++
++ while(p2p_ie)
++ {
++ find_p2p = _TRUE;
++ // Get Notice of Absence IE.
++ if(rtw_get_p2p_attr_content( p2p_ie, p2p_ielen, P2P_ATTR_NOA, noa_attr, &attr_contentlen))
++ {
++ find_p2p_ps = _TRUE;
++ noa_index = noa_attr[0];
++
++ if( (pwdinfo->p2p_ps_mode == P2P_PS_NONE) ||
++ (noa_index != pwdinfo->noa_index) )// if index change, driver should reconfigure related setting.
++ {
++ pwdinfo->noa_index = noa_index;
++ pwdinfo->opp_ps = noa_attr[1] >> 7;
++ pwdinfo->ctwindow = noa_attr[1] & 0x7F;
++
++ noa_offset = 2;
++ noa_num = 0;
++ // NoA length should be n*(13) + 2
++ if(attr_contentlen > 2)
++ {
++ while(noa_offset < attr_contentlen)
++ {
++ //_rtw_memcpy(&wifidirect_info->noa_count[noa_num], &noa_attr[noa_offset], 1);
++ pwdinfo->noa_count[noa_num] = noa_attr[noa_offset];
++ noa_offset += 1;
++
++ _rtw_memcpy(&pwdinfo->noa_duration[noa_num], &noa_attr[noa_offset], 4);
++ noa_offset += 4;
++
++ _rtw_memcpy(&pwdinfo->noa_interval[noa_num], &noa_attr[noa_offset], 4);
++ noa_offset += 4;
++
++ _rtw_memcpy(&pwdinfo->noa_start_time[noa_num], &noa_attr[noa_offset], 4);
++ noa_offset += 4;
++
++ noa_num++;
++ }
++ }
++ pwdinfo->noa_num = noa_num;
++
++ if( pwdinfo->opp_ps == 1 )
++ {
++ pwdinfo->p2p_ps_mode = P2P_PS_CTWINDOW;
++ // driver should wait LPS for entering CTWindow
++ if(padapter->pwrctrlpriv.bFwCurrentInPSMode == _TRUE)
++ {
++ p2p_ps_wk_cmd(padapter, P2P_PS_ENABLE, 1);
++ }
++ }
++ else if( pwdinfo->noa_num > 0 )
++ {
++ pwdinfo->p2p_ps_mode = P2P_PS_NOA;
++ p2p_ps_wk_cmd(padapter, P2P_PS_ENABLE, 1);
++ }
++ else if( pwdinfo->p2p_ps_mode > P2P_PS_NONE)
++ {
++ p2p_ps_wk_cmd(padapter, P2P_PS_DISABLE, 1);
++ }
++ }
++
++ break; // find target, just break.
++ }
++
++ //Get the next P2P IE
++ p2p_ie = rtw_get_p2p_ie(p2p_ie+p2p_ielen, ies_len -(p2p_ie -ies + p2p_ielen), NULL, &p2p_ielen);
++
++ }
++
++ if(find_p2p == _TRUE)
++ {
++ if( (pwdinfo->p2p_ps_mode > P2P_PS_NONE) && (find_p2p_ps == _FALSE) )
++ {
++ p2p_ps_wk_cmd(padapter, P2P_PS_DISABLE, 1);
++ }
++ }
++
++_func_exit_;
++}
++
++void p2p_ps_wk_hdl(_adapter *padapter, u8 p2p_ps_state)
++{
++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo);
++
++_func_enter_;
++
++ switch(p2p_ps_state)
++ {
++ case P2P_PS_DISABLE:
++ pwdinfo->p2p_ps_state = p2p_ps_state;
++
++ rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_P2P_PS_OFFLOAD, (u8 *)(&p2p_ps_state));
++
++ pwdinfo->noa_index = 0;
++ pwdinfo->ctwindow = 0;
++ pwdinfo->opp_ps = 0;
++ pwdinfo->noa_num = 0;
++ pwdinfo->p2p_ps_mode = P2P_PS_NONE;
++ if(padapter->pwrctrlpriv.bFwCurrentInPSMode == _TRUE)
++ {
++ if(pwrpriv->smart_ps == 0)
++ {
++ pwrpriv->smart_ps = 2;
++ rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_PWRMODE, (u8 *)(&(padapter->pwrctrlpriv.pwr_mode)));
++ }
++ }
++ break;
++ case P2P_PS_ENABLE:
++ if (pwdinfo->p2p_ps_mode > P2P_PS_NONE) {
++ pwdinfo->p2p_ps_state = p2p_ps_state;
++
++ if( pwdinfo->ctwindow > 0 )
++ {
++ if(pwrpriv->smart_ps != 0)
++ {
++ pwrpriv->smart_ps = 0;
++ DBG_871X("%s(): Enter CTW, change SmartPS\n", __FUNCTION__);
++ rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_PWRMODE, (u8 *)(&(padapter->pwrctrlpriv.pwr_mode)));
++ }
++ }
++ rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_P2P_PS_OFFLOAD, (u8 *)(&p2p_ps_state));
++ }
++ break;
++ case P2P_PS_SCAN:
++ case P2P_PS_SCAN_DONE:
++ case P2P_PS_ALLSTASLEEP:
++ if (pwdinfo->p2p_ps_mode > P2P_PS_NONE) {
++ pwdinfo->p2p_ps_state = p2p_ps_state;
++ rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_P2P_PS_OFFLOAD, (u8 *)(&p2p_ps_state));
++ }
++ break;
++ default:
++ break;
++ }
++
++_func_exit_;
++}
++
++u8 p2p_ps_wk_cmd(_adapter*padapter, u8 p2p_ps_state, u8 enqueue)
++{
++ struct cmd_obj *ph2c;
++ struct drvextra_cmd_parm *pdrvextra_cmd_parm;
++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo);
++ struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
++ u8 res = _SUCCESS;
++
++_func_enter_;
++
++ if ( rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)
++#ifdef CONFIG_CONCURRENT_MODE
++ || (padapter->iface_type != IFACE_PORT0)
++#endif
++ )
++ {
++ return res;
++ }
++
++ if(enqueue)
++ {
++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj));
++ if(ph2c==NULL){
++ res= _FAIL;
++ goto exit;
++ }
++
++ pdrvextra_cmd_parm = (struct drvextra_cmd_parm*)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
++ if(pdrvextra_cmd_parm==NULL){
++ rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));
++ res= _FAIL;
++ goto exit;
++ }
++
++ pdrvextra_cmd_parm->ec_id = P2P_PS_WK_CID;
++ pdrvextra_cmd_parm->type_size = p2p_ps_state;
++ pdrvextra_cmd_parm->pbuf = NULL;
++
++ init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));
++
++ res = rtw_enqueue_cmd(pcmdpriv, ph2c);
++ }
++ else
++ {
++ p2p_ps_wk_hdl(padapter, p2p_ps_state);
++ }
++
++exit:
++
++_func_exit_;
++
++ return res;
++
++}
++#endif // CONFIG_P2P_PS
++
++static void reset_ch_sitesurvey_timer_process (void *FunctionContext)
++{
++ _adapter *adapter = (_adapter *)FunctionContext;
++ struct wifidirect_info *pwdinfo = &adapter->wdinfo;
++
++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
++ return;
++
++ DBG_871X( "[%s] In\n", __FUNCTION__ );
++ // Reset the operation channel information
++ pwdinfo->rx_invitereq_info.operation_ch[0] = 0;
++#ifdef P2P_OP_CHECK_SOCIAL_CH
++ pwdinfo->rx_invitereq_info.operation_ch[1] = 0;
++ pwdinfo->rx_invitereq_info.operation_ch[2] = 0;
++ pwdinfo->rx_invitereq_info.operation_ch[3] = 0;
++#endif //P2P_OP_CHECK_SOCIAL_CH
++ pwdinfo->rx_invitereq_info.scan_op_ch_only = 0;
++}
++
++static void reset_ch_sitesurvey_timer_process2 (void *FunctionContext)
++{
++ _adapter *adapter = (_adapter *)FunctionContext;
++ struct wifidirect_info *pwdinfo = &adapter->wdinfo;
++
++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
++ return;
++
++ DBG_871X( "[%s] In\n", __FUNCTION__ );
++ // Reset the operation channel information
++ pwdinfo->p2p_info.operation_ch[0] = 0;
++#ifdef P2P_OP_CHECK_SOCIAL_CH
++ pwdinfo->p2p_info.operation_ch[1] = 0;
++ pwdinfo->p2p_info.operation_ch[2] = 0;
++ pwdinfo->p2p_info.operation_ch[3] = 0;
++#endif //P2P_OP_CHECK_SOCIAL_CH
++ pwdinfo->p2p_info.scan_op_ch_only = 0;
++}
++
++static void restore_p2p_state_timer_process (void *FunctionContext)
++{
++ _adapter *adapter = (_adapter *)FunctionContext;
++ struct wifidirect_info *pwdinfo = &adapter->wdinfo;
++
++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
++ return;
++
++ p2p_protocol_wk_cmd( adapter, P2P_RESTORE_STATE_WK );
++}
++
++static void pre_tx_scan_timer_process (void *FunctionContext)
++{
++ _adapter *adapter = (_adapter *) FunctionContext;
++ struct wifidirect_info *pwdinfo = &adapter->wdinfo;
++ _irqL irqL;
++ struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
++ u8 _status = 0;
++
++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
++ return;
++
++ _enter_critical_bh(&pmlmepriv->lock, &irqL);
++
++ // Commented by Albert 20110805
++ // Todo: Use the issuing probe request directly instead of using the rtw_sitesurvey_cmd!!
++
++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_PROVISION_DIS_REQ))
++ {
++ if ( _TRUE == pwdinfo->tx_prov_disc_info.benable ) // the provision discovery request frame is trigger to send or not
++ {
++ p2p_protocol_wk_cmd( adapter, P2P_PRE_TX_PROVDISC_PROCESS_WK );
++ //issue_probereq_p2p(adapter, NULL);
++ //_set_timer( &pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT );
++ }
++ }
++ else if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING))
++ {
++ if ( _TRUE == pwdinfo->nego_req_info.benable )
++ {
++ p2p_protocol_wk_cmd( adapter, P2P_PRE_TX_NEGOREQ_PROCESS_WK );
++ //issue_probereq_p2p(adapter, NULL);
++ //_set_timer( &pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT );
++ }
++ }
++ else if ( rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_INVITE_REQ ) )
++ {
++ if ( _TRUE == pwdinfo->invitereq_info.benable )
++ {
++ p2p_protocol_wk_cmd( adapter, P2P_PRE_TX_INVITEREQ_PROCESS_WK );
++ }
++ }
++ else
++ {
++ DBG_8192C( "[%s] p2p_state is %d, ignore!!\n", __FUNCTION__, rtw_p2p_state(pwdinfo) );
++ }
++
++ _exit_critical_bh(&pmlmepriv->lock, &irqL);
++}
++
++static void find_phase_timer_process (void *FunctionContext)
++{
++ _adapter *adapter = (_adapter *)FunctionContext;
++ struct wifidirect_info *pwdinfo = &adapter->wdinfo;
++
++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
++ return;
++
++ adapter->wdinfo.find_phase_state_exchange_cnt++;
++
++ p2p_protocol_wk_cmd( adapter, P2P_FIND_PHASE_WK );
++}
++
++#ifdef CONFIG_CONCURRENT_MODE
++void ap_p2p_switch_timer_process (void *FunctionContext)
++{
++ _adapter *adapter = (_adapter *)FunctionContext;
++ struct wifidirect_info *pwdinfo = &adapter->wdinfo;
++#ifdef CONFIG_IOCTL_CFG80211
++ struct rtw_wdev_priv *pwdev_priv = wdev_to_priv(adapter->rtw_wdev);
++#endif
++
++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
++ return;
++
++#ifdef CONFIG_IOCTL_CFG80211
++ ATOMIC_SET(&pwdev_priv->switch_ch_to, 1);
++#endif
++
++ p2p_protocol_wk_cmd( adapter, P2P_AP_P2P_CH_SWITCH_PROCESS_WK );
++}
++#endif
++
++void reset_global_wifidirect_info( _adapter* padapter )
++{
++ struct wifidirect_info *pwdinfo;
++
++ pwdinfo = &padapter->wdinfo;
++ pwdinfo->persistent_supported = 0;
++ pwdinfo->session_available = _TRUE;
++ pwdinfo->wfd_tdls_enable = 0;
++ pwdinfo->wfd_tdls_weaksec = 0;
++}
++
++#ifdef CONFIG_WFD
++int rtw_init_wifi_display_info(_adapter* padapter)
++{
++ int res = _SUCCESS;
++ struct wifi_display_info *pwfd_info = &padapter->wfd_info;
++
++ // Used in P2P and TDLS
++ pwfd_info->rtsp_ctrlport = 554;
++ pwfd_info->peer_rtsp_ctrlport = 0; // Reset to 0
++ pwfd_info->wfd_enable = _FALSE;
++ pwfd_info->wfd_device_type = WFD_DEVINFO_PSINK;
++ pwfd_info->scan_result_type = SCAN_RESULT_P2P_ONLY;
++
++ // Used in P2P
++ pwfd_info->peer_session_avail = _TRUE;
++ pwfd_info->wfd_pc = _FALSE;
++
++ // Used in TDLS
++ _rtw_memset( pwfd_info->ip_address, 0x00, 4 );
++ _rtw_memset( pwfd_info->peer_ip_address, 0x00, 4 );
++ return res;
++
++}
++#endif //CONFIG_WFD
++
++void rtw_init_wifidirect_timers(_adapter* padapter)
++{
++ struct wifidirect_info *pwdinfo = &padapter->wdinfo;
++
++ _init_timer( &pwdinfo->find_phase_timer, padapter->pnetdev, find_phase_timer_process, padapter );
++ _init_timer( &pwdinfo->restore_p2p_state_timer, padapter->pnetdev, restore_p2p_state_timer_process, padapter );
++ _init_timer( &pwdinfo->pre_tx_scan_timer, padapter->pnetdev, pre_tx_scan_timer_process, padapter );
++ _init_timer( &pwdinfo->reset_ch_sitesurvey, padapter->pnetdev, reset_ch_sitesurvey_timer_process, padapter );
++ _init_timer( &pwdinfo->reset_ch_sitesurvey2, padapter->pnetdev, reset_ch_sitesurvey_timer_process2, padapter );
++#ifdef CONFIG_CONCURRENT_MODE
++ _init_timer( &pwdinfo->ap_p2p_switch_timer, padapter->pnetdev, ap_p2p_switch_timer_process, padapter );
++#endif
++}
++
++void rtw_init_wifidirect_addrs(_adapter* padapter, u8 *dev_addr, u8 *iface_addr)
++{
++#ifdef CONFIG_P2P
++ struct wifidirect_info *pwdinfo = &padapter->wdinfo;
++
++ /*init device&interface address */
++ if (dev_addr) {
++ _rtw_memcpy(pwdinfo->device_addr, dev_addr, ETH_ALEN);
++ }
++ if (iface_addr) {
++ _rtw_memcpy(pwdinfo->interface_addr, iface_addr, ETH_ALEN);
++ }
++#endif
++}
++
++void init_wifidirect_info( _adapter* padapter, enum P2P_ROLE role)
++{
++ struct wifidirect_info *pwdinfo;
++#ifdef CONFIG_WFD
++ struct wifi_display_info *pwfd_info = &padapter->wfd_info;
++#endif
++#ifdef CONFIG_CONCURRENT_MODE
++ _adapter *pbuddy_adapter = padapter->pbuddy_adapter;
++ struct wifidirect_info *pbuddy_wdinfo;
++ struct mlme_priv *pbuddy_mlmepriv;
++ struct mlme_ext_priv *pbuddy_mlmeext;
++#endif
++
++ pwdinfo = &padapter->wdinfo;
++
++ pwdinfo->padapter = padapter;
++
++ // 1, 6, 11 are the social channel defined in the WiFi Direct specification.
++ pwdinfo->social_chan[0] = 1;
++ pwdinfo->social_chan[1] = 6;
++ pwdinfo->social_chan[2] = 11;
++ pwdinfo->social_chan[3] = 0; // channel 0 for scanning ending in site survey function.
++
++#ifdef CONFIG_CONCURRENT_MODE
++ if (pbuddy_adapter) {
++ pbuddy_wdinfo = &pbuddy_adapter->wdinfo;
++ pbuddy_mlmepriv = &pbuddy_adapter->mlmepriv;
++ pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv;
++ }
++
++ if ( ( check_buddy_fwstate(padapter, _FW_LINKED ) == _TRUE ) &&
++ ( ( pbuddy_mlmeext->cur_channel == 1) || ( pbuddy_mlmeext->cur_channel == 6 ) || ( pbuddy_mlmeext->cur_channel == 11 ) )
++ )
++ {
++ // Use the AP's channel as the listen channel
++ // This will avoid the channel switch between AP's channel and listen channel.
++ pwdinfo->listen_channel = pbuddy_mlmeext->cur_channel;
++ }
++ else
++#endif //CONFIG_CONCURRENT_MODE
++ {
++ // Use the channel 11 as the listen channel
++ pwdinfo->listen_channel = 11;
++ }
++
++ if (role == P2P_ROLE_DEVICE)
++ {
++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE);
++ #ifdef CONFIG_CONCURRENT_MODE
++ if ( check_buddy_fwstate(padapter, _FW_LINKED ) == _TRUE )
++ {
++ rtw_p2p_set_state(pwdinfo, P2P_STATE_IDLE);
++ }
++ else
++ #endif
++ {
++ rtw_p2p_set_state(pwdinfo, P2P_STATE_LISTEN);
++ }
++ pwdinfo->intent = 1;
++ rtw_p2p_set_pre_state(pwdinfo, P2P_STATE_LISTEN);
++ }
++ else if (role == P2P_ROLE_CLIENT)
++ {
++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT);
++ rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK);
++ pwdinfo->intent = 1;
++ rtw_p2p_set_pre_state(pwdinfo, P2P_STATE_GONEGO_OK);
++ }
++ else if (role == P2P_ROLE_GO)
++ {
++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO);
++ rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK);
++ pwdinfo->intent = 15;
++ rtw_p2p_set_pre_state(pwdinfo, P2P_STATE_GONEGO_OK);
++ }
++
++// Use the OFDM rate in the P2P probe response frame. ( 6(B), 9(B), 12, 18, 24, 36, 48, 54 )
++ pwdinfo->support_rate[0] = 0x8c; // 6(B)
++ pwdinfo->support_rate[1] = 0x92; // 9(B)
++ pwdinfo->support_rate[2] = 0x18; // 12
++ pwdinfo->support_rate[3] = 0x24; // 18
++ pwdinfo->support_rate[4] = 0x30; // 24
++ pwdinfo->support_rate[5] = 0x48; // 36
++ pwdinfo->support_rate[6] = 0x60; // 48
++ pwdinfo->support_rate[7] = 0x6c; // 54
++
++ _rtw_memcpy( ( void* ) pwdinfo->p2p_wildcard_ssid, "DIRECT-", 7 );
++
++ _rtw_memset( pwdinfo->device_name, 0x00, WPS_MAX_DEVICE_NAME_LEN );
++ pwdinfo->device_name_len = 0;
++
++ _rtw_memset( &pwdinfo->invitereq_info, 0x00, sizeof( struct tx_invite_req_info ) );
++ pwdinfo->invitereq_info.token = 3; // Token used for P2P invitation request frame.
++
++ _rtw_memset( &pwdinfo->inviteresp_info, 0x00, sizeof( struct tx_invite_resp_info ) );
++ pwdinfo->inviteresp_info.token = 0;
++
++ pwdinfo->profileindex = 0;
++ _rtw_memset( &pwdinfo->profileinfo[ 0 ], 0x00, sizeof( struct profile_info ) * P2P_MAX_PERSISTENT_GROUP_NUM );
++
++ rtw_p2p_findphase_ex_set(pwdinfo, P2P_FINDPHASE_EX_NONE);
++
++ pwdinfo->listen_dwell = ( u8 ) (( rtw_get_current_time() % 3 ) + 1);
++ //DBG_8192C( "[%s] listen_dwell time is %d00ms\n", __FUNCTION__, pwdinfo->listen_dwell );
++
++ _rtw_memset( &pwdinfo->tx_prov_disc_info, 0x00, sizeof( struct tx_provdisc_req_info ) );
++ pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_NONE;
++
++ _rtw_memset( &pwdinfo->nego_req_info, 0x00, sizeof( struct tx_nego_req_info ) );
++
++ pwdinfo->device_password_id_for_nego = WPS_DPID_PBC;
++ pwdinfo->negotiation_dialog_token = 1;
++
++ _rtw_memset( pwdinfo->nego_ssid, 0x00, WLAN_SSID_MAXLEN );
++ pwdinfo->nego_ssidlen = 0;
++
++ pwdinfo->ui_got_wps_info = P2P_NO_WPSINFO;
++#ifdef CONFIG_WFD
++ pwdinfo->supported_wps_cm = WPS_CONFIG_METHOD_DISPLAY | WPS_CONFIG_METHOD_PBC;
++ pwdinfo->wfd_info = pwfd_info;
++#else
++ pwdinfo->supported_wps_cm = WPS_CONFIG_METHOD_DISPLAY | WPS_CONFIG_METHOD_PBC | WPS_CONFIG_METHOD_KEYPAD;
++#endif //CONFIG_WFD
++ pwdinfo->channel_list_attr_len = 0;
++ _rtw_memset( pwdinfo->channel_list_attr, 0x00, 100 );
++
++ _rtw_memset( pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, 0x00, 4 );
++ _rtw_memset( pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, '0', 3 );
++ _rtw_memset( &pwdinfo->groupid_info, 0x00, sizeof( struct group_id_info ) );
++#ifdef CONFIG_CONCURRENT_MODE
++#ifdef CONFIG_IOCTL_CFG80211
++ pwdinfo->ext_listen_interval = 1000; //The interval to be available with legacy AP during p2p0-find/scan
++ pwdinfo->ext_listen_period = 3000; //The time period to be available for P2P during nego
++#else //!CONFIG_IOCTL_CFG80211
++ //pwdinfo->ext_listen_interval = 3000;
++ //pwdinfo->ext_listen_period = 400;
++ pwdinfo->ext_listen_interval = 1000;
++ pwdinfo->ext_listen_period = 1000;
++#endif //!CONFIG_IOCTL_CFG80211
++#endif
++
++// Commented by Kurt 20130319
++// For WiDi purpose: Use CFG80211 interface but controled WFD/RDS frame by driver itself.
++#ifdef CONFIG_IOCTL_CFG80211
++ pwdinfo->driver_interface = DRIVER_CFG80211;
++#else
++ pwdinfo->driver_interface = DRIVER_WEXT;
++#endif //CONFIG_IOCTL_CFG80211
++
++ pwdinfo->wfd_tdls_enable = 0;
++ _rtw_memset( pwdinfo->p2p_peer_interface_addr, 0x00, ETH_ALEN );
++ _rtw_memset( pwdinfo->p2p_peer_device_addr, 0x00, ETH_ALEN );
++
++ pwdinfo->rx_invitereq_info.operation_ch[0] = 0;
++ pwdinfo->rx_invitereq_info.operation_ch[1] = 0; // Used to indicate the scan end in site survey function
++#ifdef P2P_OP_CHECK_SOCIAL_CH
++ pwdinfo->rx_invitereq_info.operation_ch[2] = 0;
++ pwdinfo->rx_invitereq_info.operation_ch[3] = 0;
++ pwdinfo->rx_invitereq_info.operation_ch[4] = 0;
++#endif //P2P_OP_CHECK_SOCIAL_CH
++ pwdinfo->rx_invitereq_info.scan_op_ch_only = 0;
++ pwdinfo->p2p_info.operation_ch[0] = 0;
++ pwdinfo->p2p_info.operation_ch[1] = 0; // Used to indicate the scan end in site survey function
++#ifdef P2P_OP_CHECK_SOCIAL_CH
++ pwdinfo->p2p_info.operation_ch[2] = 0;
++ pwdinfo->p2p_info.operation_ch[3] = 0;
++ pwdinfo->p2p_info.operation_ch[4] = 0;
++#endif //P2P_OP_CHECK_SOCIAL_CH
++ pwdinfo->p2p_info.scan_op_ch_only = 0;
++}
++
++#ifdef CONFIG_DBG_P2P
++
++/**
++ * rtw_p2p_role_txt - Get the p2p role name as a text string
++ * @role: P2P role
++ * Returns: The state name as a printable text string
++ */
++const char * rtw_p2p_role_txt(enum P2P_ROLE role)
++{
++ switch (role) {
++ case P2P_ROLE_DISABLE:
++ return "P2P_ROLE_DISABLE";
++ case P2P_ROLE_DEVICE:
++ return "P2P_ROLE_DEVICE";
++ case P2P_ROLE_CLIENT:
++ return "P2P_ROLE_CLIENT";
++ case P2P_ROLE_GO:
++ return "P2P_ROLE_GO";
++ default:
++ return "UNKNOWN";
++ }
++}
++
++/**
++ * rtw_p2p_state_txt - Get the p2p state name as a text string
++ * @state: P2P state
++ * Returns: The state name as a printable text string
++ */
++const char * rtw_p2p_state_txt(enum P2P_STATE state)
++{
++ switch (state) {
++ case P2P_STATE_NONE:
++ return "P2P_STATE_NONE";
++ case P2P_STATE_IDLE:
++ return "P2P_STATE_IDLE";
++ case P2P_STATE_LISTEN:
++ return "P2P_STATE_LISTEN";
++ case P2P_STATE_SCAN:
++ return "P2P_STATE_SCAN";
++ case P2P_STATE_FIND_PHASE_LISTEN:
++ return "P2P_STATE_FIND_PHASE_LISTEN";
++ case P2P_STATE_FIND_PHASE_SEARCH:
++ return "P2P_STATE_FIND_PHASE_SEARCH";
++ case P2P_STATE_TX_PROVISION_DIS_REQ:
++ return "P2P_STATE_TX_PROVISION_DIS_REQ";
++ case P2P_STATE_RX_PROVISION_DIS_RSP:
++ return "P2P_STATE_RX_PROVISION_DIS_RSP";
++ case P2P_STATE_RX_PROVISION_DIS_REQ:
++ return "P2P_STATE_RX_PROVISION_DIS_REQ";
++ case P2P_STATE_GONEGO_ING:
++ return "P2P_STATE_GONEGO_ING";
++ case P2P_STATE_GONEGO_OK:
++ return "P2P_STATE_GONEGO_OK";
++ case P2P_STATE_GONEGO_FAIL:
++ return "P2P_STATE_GONEGO_FAIL";
++ case P2P_STATE_RECV_INVITE_REQ_MATCH:
++ return "P2P_STATE_RECV_INVITE_REQ_MATCH";
++ case P2P_STATE_PROVISIONING_ING:
++ return "P2P_STATE_PROVISIONING_ING";
++ case P2P_STATE_PROVISIONING_DONE:
++ return "P2P_STATE_PROVISIONING_DONE";
++ case P2P_STATE_TX_INVITE_REQ:
++ return "P2P_STATE_TX_INVITE_REQ";
++ case P2P_STATE_RX_INVITE_RESP_OK:
++ return "P2P_STATE_RX_INVITE_RESP_OK";
++ case P2P_STATE_RECV_INVITE_REQ_DISMATCH:
++ return "P2P_STATE_RECV_INVITE_REQ_DISMATCH";
++ case P2P_STATE_RECV_INVITE_REQ_GO:
++ return "P2P_STATE_RECV_INVITE_REQ_GO";
++ case P2P_STATE_RECV_INVITE_REQ_JOIN:
++ return "P2P_STATE_RECV_INVITE_REQ_JOIN";
++ case P2P_STATE_RX_INVITE_RESP_FAIL:
++ return "P2P_STATE_RX_INVITE_RESP_FAIL";
++ case P2P_STATE_RX_INFOR_NOREADY:
++ return "P2P_STATE_RX_INFOR_NOREADY";
++ case P2P_STATE_TX_INFOR_NOREADY:
++ return "P2P_STATE_TX_INFOR_NOREADY";
++ default:
++ return "UNKNOWN";
++ }
++}
++
++void dbg_rtw_p2p_set_state(struct wifidirect_info *wdinfo, enum P2P_STATE state, const char *caller, int line)
++{
++ if(!_rtw_p2p_chk_state(wdinfo, state)) {
++ enum P2P_STATE old_state = _rtw_p2p_state(wdinfo);
++ _rtw_p2p_set_state(wdinfo, state);
++ DBG_871X("[CONFIG_DBG_P2P]%s:%d set_state from %s to %s\n", caller, line
++ , rtw_p2p_state_txt(old_state), rtw_p2p_state_txt(_rtw_p2p_state(wdinfo))
++ );
++ } else {
++ DBG_871X("[CONFIG_DBG_P2P]%s:%d set_state to same state %s\n", caller, line
++ , rtw_p2p_state_txt(_rtw_p2p_state(wdinfo))
++ );
++ }
++}
++void dbg_rtw_p2p_set_pre_state(struct wifidirect_info *wdinfo, enum P2P_STATE state, const char *caller, int line)
++{
++ if(_rtw_p2p_pre_state(wdinfo) != state) {
++ enum P2P_STATE old_state = _rtw_p2p_pre_state(wdinfo);
++ _rtw_p2p_set_pre_state(wdinfo, state);
++ DBG_871X("[CONFIG_DBG_P2P]%s:%d set_pre_state from %s to %s\n", caller, line
++ , rtw_p2p_state_txt(old_state), rtw_p2p_state_txt(_rtw_p2p_pre_state(wdinfo))
++ );
++ } else {
++ DBG_871X("[CONFIG_DBG_P2P]%s:%d set_pre_state to same state %s\n", caller, line
++ , rtw_p2p_state_txt(_rtw_p2p_pre_state(wdinfo))
++ );
++ }
++}
++#if 0
++void dbg_rtw_p2p_restore_state(struct wifidirect_info *wdinfo, const char *caller, int line)
++{
++ if(wdinfo->pre_p2p_state != -1) {
++ DBG_871X("[CONFIG_DBG_P2P]%s:%d restore from %s to %s\n", caller, line
++ , p2p_state_str[wdinfo->p2p_state], p2p_state_str[wdinfo->pre_p2p_state]
++ );
++ _rtw_p2p_restore_state(wdinfo);
++ } else {
++ DBG_871X("[CONFIG_DBG_P2P]%s:%d restore no pre state, cur state %s\n", caller, line
++ , p2p_state_str[wdinfo->p2p_state]
++ );
++ }
++}
++#endif
++void dbg_rtw_p2p_set_role(struct wifidirect_info *wdinfo, enum P2P_ROLE role, const char *caller, int line)
++{
++ if(wdinfo->role != role) {
++ enum P2P_ROLE old_role = wdinfo->role;
++ _rtw_p2p_set_role(wdinfo, role);
++ DBG_871X("[CONFIG_DBG_P2P]%s:%d set_role from %s to %s\n", caller, line
++ , rtw_p2p_role_txt(old_role), rtw_p2p_role_txt(wdinfo->role)
++ );
++ } else {
++ DBG_871X("[CONFIG_DBG_P2P]%s:%d set_role to same role %s\n", caller, line
++ , rtw_p2p_role_txt(wdinfo->role)
++ );
++ }
++}
++#endif //CONFIG_DBG_P2P
++
++
++int rtw_p2p_enable(_adapter *padapter, enum P2P_ROLE role)
++{
++ int ret = _SUCCESS;
++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo);
++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
++
++ if (role == P2P_ROLE_DEVICE || role == P2P_ROLE_CLIENT|| role == P2P_ROLE_GO)
++ {
++ u8 channel, ch_offset;
++ u16 bwmode;
++
++#ifdef CONFIG_CONCURRENT_MODE
++ _adapter *pbuddy_adapter = padapter->pbuddy_adapter;
++ struct wifidirect_info *pbuddy_wdinfo = &pbuddy_adapter->wdinfo;
++ // Commented by Albert 2011/12/30
++ // The driver just supports 1 P2P group operation.
++ // So, this function will do nothing if the buddy adapter had enabled the P2P function.
++ if(!rtw_p2p_chk_state(pbuddy_wdinfo, P2P_STATE_NONE))
++ {
++ // The buddy adapter had enabled the P2P function.
++ return ret;
++ }
++#endif //CONFIG_CONCURRENT_MODE
++
++ //leave IPS/Autosuspend
++ if (_FAIL == rtw_pwr_wakeup(padapter)) {
++ ret = _FAIL;
++ goto exit;
++ }
++
++
++ // Added by Albert 2011/03/22
++ // In the P2P mode, the driver should not support the b mode.
++ // So, the Tx packet shouldn't use the CCK rate
++ update_tx_basic_rate(padapter, WIRELESS_11AGN);
++
++ //Enable P2P function
++ init_wifidirect_info(padapter, role);
++ }
++ else if (role == P2P_ROLE_DISABLE)
++ {
++#ifdef CONFIG_INTEL_WIDI
++ if( padapter->mlmepriv.p2p_reject_disable == _TRUE )
++ return ret;
++#endif //CONFIG_INTEL_WIDI
++
++ if (_FAIL == rtw_pwr_wakeup(padapter)) {
++ ret = _FAIL;
++ goto exit;
++ }
++
++ //Disable P2P function
++ if(!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
++ {
++ _cancel_timer_ex( &pwdinfo->find_phase_timer );
++ _cancel_timer_ex( &pwdinfo->restore_p2p_state_timer );
++ _cancel_timer_ex( &pwdinfo->pre_tx_scan_timer);
++ _cancel_timer_ex( &pwdinfo->reset_ch_sitesurvey);
++ _cancel_timer_ex( &pwdinfo->reset_ch_sitesurvey2);
++ reset_ch_sitesurvey_timer_process( padapter );
++ reset_ch_sitesurvey_timer_process2( padapter );
++ #ifdef CONFIG_CONCURRENT_MODE
++ _cancel_timer_ex( &pwdinfo->ap_p2p_switch_timer);
++ #endif
++ rtw_p2p_set_state(pwdinfo, P2P_STATE_NONE);
++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_DISABLE);
++ _rtw_memset(&pwdinfo->rx_prov_disc_info, 0x00, sizeof(struct rx_provdisc_req_info));
++ }
++
++ //Restore to initial setting.
++ update_tx_basic_rate(padapter, padapter->registrypriv.wireless_mode);
++
++#ifdef CONFIG_INTEL_WIDI
++ rtw_reset_widi_info(padapter);
++#endif //CONFIG_INTEL_WIDI
++
++ //For WiDi purpose.
++#ifdef CONFIG_IOCTL_CFG80211
++ pwdinfo->driver_interface = DRIVER_CFG80211;
++#else
++ pwdinfo->driver_interface = DRIVER_WEXT;
++#endif //CONFIG_IOCTL_CFG80211
++
++ }
++
++exit:
++ return ret;
++}
++
++#endif //CONFIG_P2P
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/core/rtw_pwrctrl.c linux-xbian-rpi/drivers/net/wireless/rtl8192cu/core/rtw_pwrctrl.c
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/core/rtw_pwrctrl.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/core/rtw_pwrctrl.c 2015-07-28 01:20:58.305654202 +0200
+@@ -0,0 +1,1538 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#define _RTW_PWRCTRL_C_
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++#include <osdep_intf.h>
++
++
++#ifdef CONFIG_IPS
++void _ips_enter(_adapter * padapter)
++{
++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
++
++ pwrpriv->bips_processing = _TRUE;
++
++ // syn ips_mode with request
++ pwrpriv->ips_mode = pwrpriv->ips_mode_req;
++
++ pwrpriv->ips_enter_cnts++;
++ DBG_871X("==>ips_enter cnts:%d\n",pwrpriv->ips_enter_cnts);
++
++ if(rf_off == pwrpriv->change_rfpwrstate)
++ {
++ if(pwrpriv->ips_mode == IPS_LEVEL_2)
++ pwrpriv->bkeepfwalive = _TRUE;
++
++ rtw_ips_pwr_down(padapter);
++ pwrpriv->rf_pwrstate = rf_off;
++ }
++ pwrpriv->bips_processing = _FALSE;
++
++}
++
++void ips_enter(_adapter * padapter)
++{
++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
++
++ _enter_pwrlock(&pwrpriv->lock);
++ _ips_enter(padapter);
++ _exit_pwrlock(&pwrpriv->lock);
++}
++
++int _ips_leave(_adapter * padapter)
++{
++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
++ int result = _SUCCESS;
++
++ if((pwrpriv->rf_pwrstate == rf_off) &&(!pwrpriv->bips_processing))
++ {
++ pwrpriv->bips_processing = _TRUE;
++ pwrpriv->change_rfpwrstate = rf_on;
++ pwrpriv->ips_leave_cnts++;
++ DBG_871X("==>ips_leave cnts:%d\n",pwrpriv->ips_leave_cnts);
++
++ if ((result = rtw_ips_pwr_up(padapter)) == _SUCCESS) {
++ pwrpriv->rf_pwrstate = rf_on;
++ }
++
++ DBG_871X("==> ips_leave.....LED(0x%08x)...\n",rtw_read32(padapter,0x4c));
++ pwrpriv->bips_processing = _FALSE;
++
++ pwrpriv->bkeepfwalive = _FALSE;
++ }
++
++ return result;
++}
++
++int ips_leave(_adapter * padapter)
++{
++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
++ int ret;
++
++ _enter_pwrlock(&pwrpriv->lock);
++ ret = _ips_leave(padapter);
++ _exit_pwrlock(&pwrpriv->lock);
++
++ return ret;
++}
++#endif /* CONFIG_IPS */
++
++#ifdef CONFIG_AUTOSUSPEND
++extern void autosuspend_enter(_adapter* padapter);
++extern int autoresume_enter(_adapter* padapter);
++#endif
++
++#ifdef SUPPORT_HW_RFOFF_DETECTED
++int rtw_hw_suspend(_adapter *padapter );
++int rtw_hw_resume(_adapter *padapter);
++#endif
++
++bool rtw_pwr_unassociated_idle(_adapter *adapter)
++{
++ _adapter *buddy = adapter->pbuddy_adapter;
++ struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
++#ifdef CONFIG_P2P
++ struct wifidirect_info *pwdinfo = &(adapter->wdinfo);
++#ifdef CONFIG_IOCTL_CFG80211
++ struct cfg80211_wifidirect_info *pcfg80211_wdinfo = &adapter->cfg80211_wdinfo;
++#endif
++#endif
++
++ bool ret = _FALSE;
++
++ if (adapter->pwrctrlpriv.ips_deny_time >= rtw_get_current_time()) {
++ //DBG_871X("%s ips_deny_time\n", __func__);
++ goto exit;
++ }
++
++ if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE|WIFI_SITE_MONITOR)
++ || check_fwstate(pmlmepriv, WIFI_UNDER_LINKING|WIFI_UNDER_WPS)
++ || check_fwstate(pmlmepriv, WIFI_AP_STATE)
++ || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE|WIFI_ADHOC_STATE)
++ #if defined(CONFIG_P2P) && defined(CONFIG_IOCTL_CFG80211) && defined(CONFIG_P2P_IPS)
++ || pcfg80211_wdinfo->is_ro_ch
++ #elif defined(CONFIG_P2P)
++ || !rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)
++ #endif
++ ) {
++ goto exit;
++ }
++
++ /* consider buddy, if exist */
++ if (buddy) {
++ struct mlme_priv *b_pmlmepriv = &(buddy->mlmepriv);
++ #ifdef CONFIG_P2P
++ struct wifidirect_info *b_pwdinfo = &(buddy->wdinfo);
++ #ifdef CONFIG_IOCTL_CFG80211
++ struct cfg80211_wifidirect_info *b_pcfg80211_wdinfo = &buddy->cfg80211_wdinfo;
++ #endif
++ #endif
++
++ if (check_fwstate(b_pmlmepriv, WIFI_ASOC_STATE|WIFI_SITE_MONITOR)
++ || check_fwstate(b_pmlmepriv, WIFI_UNDER_LINKING|WIFI_UNDER_WPS)
++ || check_fwstate(b_pmlmepriv, WIFI_AP_STATE)
++ || check_fwstate(b_pmlmepriv, WIFI_ADHOC_MASTER_STATE|WIFI_ADHOC_STATE)
++ #if defined(CONFIG_P2P) && defined(CONFIG_IOCTL_CFG80211) && defined(CONFIG_P2P_IPS)
++ || b_pcfg80211_wdinfo->is_ro_ch
++ #elif defined(CONFIG_P2P)
++ || !rtw_p2p_chk_state(b_pwdinfo, P2P_STATE_NONE)
++ #endif
++ ) {
++ goto exit;
++ }
++ }
++
++#ifdef CONFIG_INTEL_PROXIM
++ if(adapter->proximity.proxim_on==_TRUE){
++ return;
++ }
++#endif
++
++ ret = _TRUE;
++
++exit:
++ return ret;
++}
++
++#if defined (PLATFORM_LINUX)||defined (PLATFORM_FREEBSD)
++void rtw_ps_processor(_adapter*padapter)
++{
++#ifdef CONFIG_P2P
++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo );
++#endif //CONFIG_P2P
++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++#ifdef SUPPORT_HW_RFOFF_DETECTED
++ rt_rf_power_state rfpwrstate;
++#endif //SUPPORT_HW_RFOFF_DETECTED
++
++ pwrpriv->ps_processing = _TRUE;
++
++#ifdef SUPPORT_HW_RFOFF_DETECTED
++ if(pwrpriv->bips_processing == _TRUE)
++ goto exit;
++
++ //DBG_871X("==> fw report state(0x%x)\n",rtw_read8(padapter,0x1ca));
++ if(padapter->pwrctrlpriv.bHWPwrPindetect)
++ {
++ #ifdef CONFIG_AUTOSUSPEND
++ if(padapter->registrypriv.usbss_enable)
++ {
++ if(pwrpriv->rf_pwrstate == rf_on)
++ {
++ if(padapter->net_closed == _TRUE)
++ pwrpriv->ps_flag = _TRUE;
++
++ rfpwrstate = RfOnOffDetect(padapter);
++ DBG_871X("@@@@- #1 %s==> rfstate:%s \n",__FUNCTION__,(rfpwrstate==rf_on)?"rf_on":"rf_off");
++ if(rfpwrstate!= pwrpriv->rf_pwrstate)
++ {
++ if(rfpwrstate == rf_off)
++ {
++ pwrpriv->change_rfpwrstate = rf_off;
++
++ pwrpriv->bkeepfwalive = _TRUE;
++ pwrpriv->brfoffbyhw = _TRUE;
++
++ autosuspend_enter(padapter);
++ }
++ }
++ }
++ }
++ else
++ #endif //CONFIG_AUTOSUSPEND
++ {
++ rfpwrstate = RfOnOffDetect(padapter);
++ DBG_871X("@@@@- #2 %s==> rfstate:%s \n",__FUNCTION__,(rfpwrstate==rf_on)?"rf_on":"rf_off");
++
++ if(rfpwrstate!= pwrpriv->rf_pwrstate)
++ {
++ if(rfpwrstate == rf_off)
++ {
++ pwrpriv->change_rfpwrstate = rf_off;
++ pwrpriv->brfoffbyhw = _TRUE;
++ padapter->bCardDisableWOHSM = _TRUE;
++ rtw_hw_suspend(padapter );
++ }
++ else
++ {
++ pwrpriv->change_rfpwrstate = rf_on;
++ rtw_hw_resume(padapter );
++ }
++ DBG_871X("current rf_pwrstate(%s)\n",(pwrpriv->rf_pwrstate == rf_off)?"rf_off":"rf_on");
++ }
++ }
++ pwrpriv->pwr_state_check_cnts ++;
++ }
++#endif //SUPPORT_HW_RFOFF_DETECTED
++
++ if (pwrpriv->ips_mode_req == IPS_NONE
++ #ifdef CONFIG_CONCURRENT_MODE
++ || padapter->pbuddy_adapter->pwrctrlpriv.ips_mode_req == IPS_NONE
++ #endif
++ )
++ goto exit;
++
++ if (rtw_pwr_unassociated_idle(padapter) == _FALSE)
++ goto exit;
++
++ if((pwrpriv->rf_pwrstate == rf_on) && ((pwrpriv->pwr_state_check_cnts%4)==0))
++ {
++ DBG_871X("==>%s .fw_state(%x)\n",__FUNCTION__,get_fwstate(pmlmepriv));
++ pwrpriv->change_rfpwrstate = rf_off;
++
++ #ifdef CONFIG_AUTOSUSPEND
++ if(padapter->registrypriv.usbss_enable)
++ {
++ if(pwrpriv->bHWPwrPindetect)
++ pwrpriv->bkeepfwalive = _TRUE;
++
++ if(padapter->net_closed == _TRUE)
++ pwrpriv->ps_flag = _TRUE;
++
++ padapter->bCardDisableWOHSM = _TRUE;
++ autosuspend_enter(padapter);
++ }
++ else if(pwrpriv->bHWPwrPindetect)
++ {
++ }
++ else
++ #endif //CONFIG_AUTOSUSPEND
++ {
++ #ifdef CONFIG_IPS
++ ips_enter(padapter);
++ #endif
++ }
++ }
++exit:
++ rtw_set_pwr_state_check_timer(&padapter->pwrctrlpriv);
++ pwrpriv->ps_processing = _FALSE;
++ return;
++}
++
++void pwr_state_check_handler(void *FunctionContext);
++void pwr_state_check_handler(void *FunctionContext)
++{
++ _adapter *padapter = (_adapter *)FunctionContext;
++ rtw_ps_cmd(padapter);
++}
++#endif
++
++
++#ifdef CONFIG_LPS
++/*
++ *
++ * Parameters
++ * padapter
++ * pslv power state level, only could be PS_STATE_S0 ~ PS_STATE_S4
++ *
++ */
++void rtw_set_rpwm(PADAPTER padapter, u8 pslv)
++{
++ u8 rpwm;
++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
++
++_func_enter_;
++
++ pslv = PS_STATE(pslv);
++
++ if (pwrpriv->rpwm == pslv) {
++ RT_TRACE(_module_rtl871x_pwrctrl_c_,_drv_err_,
++ ("%s: Already set rpwm[0x%02x]!\n", __FUNCTION__, pslv));
++ return;
++ }
++
++ if ((padapter->bDriverStopped == _TRUE) ||
++ (padapter->bSurpriseRemoved == _TRUE)) {
++ RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_err_,
++ ("%s: bDriverStopped(%d) bSurpriseRemoved(%d)\n",
++ __FUNCTION__, padapter->bDriverStopped, padapter->bSurpriseRemoved));
++ return;
++ }
++
++ rpwm = pslv | pwrpriv->tog;
++#ifdef CONFIG_LPS_LCLK
++ if ((pwrpriv->cpwm < PS_STATE_S2) && (pslv >= PS_STATE_S2))
++ rpwm |= PS_ACK;
++#endif
++ RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_notice_,
++ ("rtw_set_rpwm: rpwm=0x%02x cpwm=0x%02x\n", rpwm, pwrpriv->cpwm));
++
++ pwrpriv->rpwm = pslv;
++
++ rtw_hal_set_hwreg(padapter, HW_VAR_SET_RPWM, (u8 *)(&rpwm));
++
++ pwrpriv->tog += 0x80;
++
++ if (!(rpwm & PS_ACK)) pwrpriv->cpwm = pslv;
++
++_func_exit_;
++}
++
++u8 PS_RDY_CHECK(_adapter * padapter);
++u8 PS_RDY_CHECK(_adapter * padapter)
++{
++ u32 curr_time, delta_time;
++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++
++ curr_time = rtw_get_current_time();
++
++ delta_time = curr_time -pwrpriv->DelayLPSLastTimeStamp;
++
++ if(delta_time < LPS_DELAY_TIME)
++ {
++ return _FALSE;
++ }
++
++ if ((check_fwstate(pmlmepriv, _FW_LINKED) == _FALSE) ||
++ (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE) ||
++ (check_fwstate(pmlmepriv, WIFI_UNDER_WPS) == _TRUE) ||
++ (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) ||
++ (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) ||
++ (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) )
++ return _FALSE;
++
++ if(_TRUE == pwrpriv->bInSuspend )
++ return _FALSE;
++
++ if( (padapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) && (padapter->securitypriv.binstallGrpkey == _FALSE) )
++ {
++ DBG_871X("Group handshake still in progress !!!\n");
++ return _FALSE;
++ }
++
++#ifdef CONFIG_IOCTL_CFG80211
++ if (!rtw_cfg80211_pwr_mgmt(padapter))
++ return _FALSE;
++#endif
++
++ return _TRUE;
++}
++
++void rtw_set_ps_mode(PADAPTER padapter, u8 ps_mode, u8 smart_ps)
++{
++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
++#ifdef CONFIG_P2P
++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo );
++#endif //CONFIG_P2P
++#ifdef CONFIG_TDLS
++ struct sta_priv *pstapriv = &padapter->stapriv;
++ _irqL irqL;
++ int i, j;
++ _list *plist, *phead;
++ struct sta_info *ptdls_sta;
++#endif //CONFIG_TDLS
++
++_func_enter_;
++
++ RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_notice_,
++ ("%s: PowerMode=%d Smart_PS=%d\n",
++ __FUNCTION__, ps_mode, smart_ps));
++
++ if(ps_mode > PM_Card_Disable) {
++ RT_TRACE(_module_rtl871x_pwrctrl_c_,_drv_err_,("ps_mode:%d error\n", ps_mode));
++ return;
++ }
++
++ if((pwrpriv->pwr_mode == ps_mode) &&
++ (pwrpriv->smart_ps == smart_ps)){
++ return;
++ }
++
++ //if(pwrpriv->pwr_mode == PS_MODE_ACTIVE)
++ if(ps_mode == PS_MODE_ACTIVE)
++ {
++#ifdef CONFIG_P2P_PS
++ if(pwdinfo->opp_ps == 0)
++#endif // CONFIG_P2P_PS
++ {
++#ifdef CONFIG_LPS_LCLK
++ _enter_pwrlock(&pwrpriv->lock);
++#endif
++ DBG_871X("rtw_set_ps_mode(): Busy Traffic , Leave 802.11 power save..\n");
++
++#ifdef CONFIG_TDLS
++ _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
++
++ for(i=0; i< NUM_STA; i++)
++ {
++ phead = &(pstapriv->sta_hash[i]);
++ plist = get_next(phead);
++
++ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE)
++ {
++ ptdls_sta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
++
++ if( ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE )
++ issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta, 0);
++ plist = get_next(plist);
++ }
++ }
++
++ _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
++#endif //CONFIG_TDLS
++
++ pwrpriv->smart_ps = smart_ps;
++ pwrpriv->pwr_mode = ps_mode;
++
++ rtw_set_rpwm(padapter, PS_STATE_S4);
++#ifdef CONFIG_LPS_LCLK
++{
++ u32 n = 0;
++ while (pwrpriv->cpwm != PS_STATE_S4) {
++ n++;
++ if (n == 10000) break;
++ if (padapter->bSurpriseRemoved == _TRUE) break;
++ rtw_msleep_os(1);
++ }
++ if (n == 10000)
++ printk(KERN_ERR "%s: wait CPWM to S4 too long! cpwm=0x%02x\n", __func__, pwrpriv->cpwm);
++}
++#endif
++ rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_PWRMODE, (u8 *)(&ps_mode));
++ pwrpriv->bFwCurrentInPSMode = _FALSE;
++#ifdef CONFIG_LPS_LCLK
++ _exit_pwrlock(&pwrpriv->lock);
++#endif
++ }
++ }
++ else
++ {
++ if(PS_RDY_CHECK(padapter))
++ {
++#ifdef CONFIG_LPS_LCLK
++ _enter_pwrlock(&pwrpriv->lock);
++#endif
++ DBG_871X("rtw_set_ps_mode(): Enter 802.11 power save mode...\n");
++
++#ifdef CONFIG_TDLS
++ _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
++
++ for(i=0; i< NUM_STA; i++)
++ {
++ phead = &(pstapriv->sta_hash[i]);
++ plist = get_next(phead);
++
++ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE)
++ {
++ ptdls_sta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
++
++ if( ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE )
++ issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta, 1);
++ plist = get_next(plist);
++ }
++ }
++
++ _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
++#endif //CONFIG_TDLS
++
++ pwrpriv->smart_ps = smart_ps;
++ pwrpriv->pwr_mode = ps_mode;
++ pwrpriv->bFwCurrentInPSMode = _TRUE;
++ rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_PWRMODE, (u8 *)(&ps_mode));
++#ifdef CONFIG_P2P_PS
++ // Set CTWindow after LPS
++ if(pwdinfo->opp_ps == 1)
++ p2p_ps_wk_cmd(padapter, P2P_PS_ENABLE, 0);
++#endif // CONFIG_P2P_PS
++#ifdef CONFIG_LPS_LCLK
++ if (pwrpriv->alives == 0)
++ rtw_set_rpwm(padapter, PS_STATE_S0);
++#else
++ rtw_set_rpwm(padapter, PS_STATE_S2);
++#endif
++#ifdef CONFIG_LPS_LCLK
++ _exit_pwrlock(&pwrpriv->lock);
++#endif
++ }
++ //else
++ //{
++ // pwrpriv->pwr_mode = PS_MODE_ACTIVE;
++ //}
++ }
++
++_func_exit_;
++}
++
++
++//
++// Description:
++// Enter the leisure power save mode.
++//
++void LPS_Enter(PADAPTER padapter)
++{
++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ _adapter *buddy = padapter->pbuddy_adapter;
++
++_func_enter_;
++
++// DBG_871X("+LeisurePSEnter\n");
++
++#ifdef CONFIG_CONCURRENT_MODE
++ if (padapter->iface_type != IFACE_PORT0)
++ return; /* Skip power saving for concurrent mode port 1*/
++
++ /* consider buddy, if exist */
++ if (buddy) {
++ struct mlme_priv *b_pmlmepriv = &(buddy->mlmepriv);
++ #ifdef CONFIG_P2P
++ struct wifidirect_info *b_pwdinfo = &(buddy->wdinfo);
++ #ifdef CONFIG_IOCTL_CFG80211
++ struct cfg80211_wifidirect_info *b_pcfg80211_wdinfo = &buddy->cfg80211_wdinfo;
++ #endif
++ #endif
++
++ if (check_fwstate(b_pmlmepriv, WIFI_ASOC_STATE|WIFI_SITE_MONITOR)
++ || check_fwstate(b_pmlmepriv, WIFI_UNDER_LINKING|WIFI_UNDER_WPS)
++ || check_fwstate(b_pmlmepriv, WIFI_AP_STATE)
++ || check_fwstate(b_pmlmepriv, WIFI_ADHOC_MASTER_STATE|WIFI_ADHOC_STATE)
++ #if defined(CONFIG_P2P) && defined(CONFIG_IOCTL_CFG80211) && defined(CONFIG_P2P_IPS)
++ || b_pcfg80211_wdinfo->is_ro_ch
++ #elif defined(CONFIG_P2P)
++ || !rtw_p2p_chk_state(b_pwdinfo, P2P_STATE_NONE)
++ #endif
++ || rtw_is_scan_deny(buddy)
++ ) {
++ return;
++ }
++ }
++#endif
++
++#ifdef CONFIG_INTEL_PROXIM
++ if(padapter->proximity.proxim_on==_TRUE){
++ return;
++ }
++#endif
++ if ( (check_fwstate(pmlmepriv, _FW_LINKED) == _FALSE) ||
++ (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE) ||
++ (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) ||
++ (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) ||
++ (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) )
++ return;
++
++ if(_TRUE == pwrpriv->bInSuspend )
++ return ;
++
++ if (pwrpriv->bLeisurePs)
++ {
++ // Idle for a while if we connect to AP a while ago.
++ if(pwrpriv->LpsIdleCount >= 2) // 4 Sec
++ {
++ if(pwrpriv->pwr_mode == PS_MODE_ACTIVE)
++ {
++ rtw_set_ps_mode(padapter, pwrpriv->power_mgnt, 2);
++ }
++ }
++ else
++ pwrpriv->LpsIdleCount++;
++ }
++
++// DBG_871X("-LeisurePSEnter\n");
++
++_func_exit_;
++}
++
++
++//
++// Description:
++// Leave the leisure power save mode.
++//
++void LPS_Leave(PADAPTER padapter)
++{
++#define LPS_LEAVE_TIMEOUT_MS 100
++
++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
++ u32 start_time;
++ BOOLEAN bAwake = _FALSE;
++
++_func_enter_;
++
++// DBG_871X("+LeisurePSLeave\n");
++
++#ifdef CONFIG_CONCURRENT_MODE
++ if (padapter->iface_type != IFACE_PORT0)
++ return; /* Skip power saving for concurrent mode port 1*/
++#endif
++
++ if (pwrpriv->bLeisurePs)
++ {
++ if(pwrpriv->pwr_mode != PS_MODE_ACTIVE)
++ {
++ rtw_set_ps_mode(padapter, PS_MODE_ACTIVE, 0);
++
++ if(pwrpriv->pwr_mode == PS_MODE_ACTIVE)
++ {
++ start_time = rtw_get_current_time();
++ while(1)
++ {
++ rtw_hal_get_hwreg(padapter, HW_VAR_FWLPS_RF_ON, (u8 *)(&bAwake));
++
++ if(bAwake || padapter->bSurpriseRemoved)
++ break;
++
++ if(rtw_get_passing_time_ms(start_time)>LPS_LEAVE_TIMEOUT_MS)
++ {
++ DBG_871X("Wait for FW LPS leave more than %u ms!!!\n", LPS_LEAVE_TIMEOUT_MS);
++ break;
++ }
++ rtw_usleep_os(100);
++ }
++ }
++ }
++ }
++
++
++// DBG_871X("-LeisurePSLeave\n");
++
++_func_exit_;
++}
++
++#endif
++
++//
++// Description: Leave all power save mode: LPS, FwLPS, IPS if needed.
++// Move code to function by tynli. 2010.03.26.
++//
++void LeaveAllPowerSaveMode(IN PADAPTER Adapter)
++{
++ struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv);
++
++_func_enter_;
++
++ //DBG_871X("%s.....\n",__FUNCTION__);
++ if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)
++ { //connect
++#ifdef CONFIG_P2P_PS
++ p2p_ps_wk_cmd(Adapter, P2P_PS_DISABLE, 0);
++#endif // CONFIG_P2P_PS
++#ifdef CONFIG_LPS
++ //DBG_871X("==> leave LPS.......\n");
++ LPS_Leave(Adapter);
++#endif
++ }
++ else
++ {
++ if(Adapter->pwrctrlpriv.rf_pwrstate== rf_off)
++ {
++ #ifdef CONFIG_AUTOSUSPEND
++ if(Adapter->registrypriv.usbss_enable)
++ {
++ #if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,35))
++ usb_disable_autosuspend(adapter_to_dvobj(Adapter)->pusbdev);
++ #elif (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,22) && LINUX_VERSION_CODE<=KERNEL_VERSION(2,6,34))
++ adapter_to_dvobj(Adapter)->pusbdev->autosuspend_disabled = Adapter->bDisableAutosuspend;//autosuspend disabled by the user
++ #endif
++ }
++ else
++ #endif
++ {
++ /*
++ #ifdef CONFIG_IPS
++ if(_FALSE == ips_leave(Adapter))
++ {
++ DBG_871X("======> ips_leave fail.............\n");
++ }
++ #endif
++ */
++ }
++ }
++ }
++
++_func_exit_;
++}
++
++#ifdef CONFIG_LPS_LCLK
++/*
++ * Caller:ISR handler...
++ *
++ * This will be called when CPWM interrupt is up.
++ *
++ * using to update cpwn of drv; and drv willl make a decision to up or down pwr level
++ */
++void cpwm_int_hdl(
++ PADAPTER padapter,
++ struct reportpwrstate_parm *preportpwrstate)
++{
++ struct pwrctrl_priv *pwrpriv;
++
++
++_func_enter_;
++
++ pwrpriv = &padapter->pwrctrlpriv;
++#if 0
++ if (pwrpriv->cpwm_tog == (preportpwrstate->state & PS_TOGGLE)) {
++ RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_err_,
++ ("cpwm_int_hdl: tog(old)=0x%02x cpwm(new)=0x%02x toggle bit didn't change!?\n",
++ pwrpriv->cpwm_tog, preportpwrstate->state));
++ goto exit;
++ }
++#endif
++// _enter_pwrlock(&pwrpriv->lock);
++
++ pwrpriv->cpwm = PS_STATE(preportpwrstate->state);
++ pwrpriv->cpwm_tog = preportpwrstate->state & PS_TOGGLE;
++
++ if (pwrpriv->cpwm >= PS_STATE_S2) {
++ if (pwrpriv->alives & CMD_ALIVE)
++ _rtw_up_sema(&padapter->cmdpriv.cmd_queue_sema);
++
++ if (pwrpriv->alives & XMIT_ALIVE)
++ _rtw_up_sema(&padapter->xmitpriv.xmit_sema);
++ }
++
++// _exit_pwrlock(&pwrpriv->lock);
++
++exit:
++ RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_notice_,
++ ("cpwm_int_hdl: cpwm=0x%02x\n", pwrpriv->cpwm));
++
++_func_exit_;
++}
++
++__inline static void register_task_alive(struct pwrctrl_priv *pwrctrl, u32 tag)
++{
++ pwrctrl->alives |= tag;
++}
++
++__inline static void unregister_task_alive(struct pwrctrl_priv *pwrctrl, u32 tag)
++{
++ pwrctrl->alives &= ~tag;
++}
++
++/*
++ * Caller: rtw_xmit_thread
++ *
++ * Check if the fw_pwrstate is okay for xmit.
++ * If not (cpwm is less than S3), then the sub-routine
++ * will raise the cpwm to be greater than or equal to S3.
++ *
++ * Calling Context: Passive
++ *
++ * Return Value:
++ * _SUCCESS rtw_xmit_thread can write fifo/txcmd afterwards.
++ * _FAIL rtw_xmit_thread can not do anything.
++ */
++s32 rtw_register_tx_alive(PADAPTER padapter)
++{
++ s32 res;
++ struct pwrctrl_priv *pwrctrl;
++
++_func_enter_;
++
++ res = _SUCCESS;
++ pwrctrl = &padapter->pwrctrlpriv;
++
++ _enter_pwrlock(&pwrctrl->lock);
++
++ register_task_alive(pwrctrl, XMIT_ALIVE);
++
++ if (pwrctrl->bFwCurrentInPSMode == _TRUE)
++ {
++ RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_err_,
++ ("rtw_register_tx_alive: cpwm=0x%02x alives=0x%08x\n",
++ pwrctrl->cpwm, pwrctrl->alives));
++
++ if (pwrctrl->cpwm < PS_STATE_S2) {
++ if (pwrctrl->rpwm < PS_STATE_S2)
++ rtw_set_rpwm(padapter, PS_STATE_S2);
++ res = _FAIL;
++ }
++ }
++
++ _exit_pwrlock(&pwrctrl->lock);
++
++_func_exit_;
++
++ return res;
++}
++
++/*
++ * Caller: rtw_cmd_thread
++ *
++ * Check if the fw_pwrstate is okay for issuing cmd.
++ * If not (cpwm should be is less than S2), then the sub-routine
++ * will raise the cpwm to be greater than or equal to S2.
++ *
++ * Calling Context: Passive
++ *
++ * Return Value:
++ * _SUCCESS rtw_cmd_thread can issue cmds to firmware afterwards.
++ * _FAIL rtw_cmd_thread can not do anything.
++ */
++s32 rtw_register_cmd_alive(PADAPTER padapter)
++{
++ s32 res;
++ struct pwrctrl_priv *pwrctrl;
++
++_func_enter_;
++
++ res = _SUCCESS;
++ pwrctrl = &padapter->pwrctrlpriv;
++
++ _enter_pwrlock(&pwrctrl->lock);
++
++ register_task_alive(pwrctrl, CMD_ALIVE);
++
++ if (pwrctrl->bFwCurrentInPSMode == _TRUE)
++ {
++ RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_notice_,
++ ("rtw_register_cmd_alive: cpwm=0x%02x alives=0x%08x\n",
++ pwrctrl->cpwm, pwrctrl->alives));
++
++ if (pwrctrl->cpwm < PS_STATE_S2) {
++ if (pwrctrl->rpwm < PS_STATE_S2)
++ rtw_set_rpwm(padapter, PS_STATE_S2);
++ res = _FAIL;
++ }
++ }
++
++ _exit_pwrlock(&pwrctrl->lock);
++
++_func_exit_;
++
++ return res;
++}
++
++/*
++ * Caller: rx_isr
++ *
++ * Calling Context: Dispatch/ISR
++ *
++ * Return Value:
++ * _SUCCESS
++ * _FAIL
++ */
++s32 rtw_register_rx_alive(PADAPTER padapter)
++{
++ struct pwrctrl_priv *pwrctrl;
++
++_func_enter_;
++
++ pwrctrl = &padapter->pwrctrlpriv;
++
++ _enter_pwrlock(&pwrctrl->lock);
++
++ register_task_alive(pwrctrl, RECV_ALIVE);
++ RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_notice_,
++ ("rtw_register_rx_alive: cpwm=0x%02x alives=0x%08x\n",
++ pwrctrl->cpwm, pwrctrl->alives));
++
++ _exit_pwrlock(&pwrctrl->lock);
++
++_func_exit_;
++
++ return _SUCCESS;
++}
++
++/*
++ * Caller: evt_isr or evt_thread
++ *
++ * Calling Context: Dispatch/ISR or Passive
++ *
++ * Return Value:
++ * _SUCCESS
++ * _FAIL
++ */
++s32 rtw_register_evt_alive(PADAPTER padapter)
++{
++ struct pwrctrl_priv *pwrctrl;
++
++_func_enter_;
++
++ pwrctrl = &padapter->pwrctrlpriv;
++
++ _enter_pwrlock(&pwrctrl->lock);
++
++ register_task_alive(pwrctrl, EVT_ALIVE);
++ RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_notice_,
++ ("rtw_register_evt_alive: cpwm=0x%02x alives=0x%08x\n",
++ pwrctrl->cpwm, pwrctrl->alives));
++
++ _exit_pwrlock(&pwrctrl->lock);
++
++_func_exit_;
++
++ return _SUCCESS;
++}
++
++/*
++ * Caller: ISR
++ *
++ * If ISR's txdone,
++ * No more pkts for TX,
++ * Then driver shall call this fun. to power down firmware again.
++ */
++void rtw_unregister_tx_alive(PADAPTER padapter)
++{
++ struct pwrctrl_priv *pwrctrl;
++
++_func_enter_;
++
++ pwrctrl = &padapter->pwrctrlpriv;
++
++ _enter_pwrlock(&pwrctrl->lock);
++
++ unregister_task_alive(pwrctrl, XMIT_ALIVE);
++
++ if ((pwrctrl->pwr_mode != PS_MODE_ACTIVE) &&
++ (pwrctrl->bFwCurrentInPSMode == _TRUE))
++ {
++ if ((pwrctrl->alives == 0) &&
++ (pwrctrl->cpwm > PS_STATE_S0))
++ {
++ rtw_set_rpwm(padapter, PS_STATE_S0);
++ }
++
++ RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_notice_,
++ ("rtw_unregister_tx_alive: cpwm=0x%02x alives=0x%08x\n",
++ pwrctrl->cpwm, pwrctrl->alives));
++ }
++
++ _exit_pwrlock(&pwrctrl->lock);
++
++_func_exit_;
++}
++
++/*
++ * Caller: ISR
++ *
++ * If all commands have been done,
++ * and no more command to do,
++ * then driver shall call this fun. to power down firmware again.
++ */
++void rtw_unregister_cmd_alive(PADAPTER padapter)
++{
++ struct pwrctrl_priv *pwrctrl;
++
++_func_enter_;
++
++ pwrctrl = &padapter->pwrctrlpriv;
++
++ _enter_pwrlock(&pwrctrl->lock);
++
++ unregister_task_alive(pwrctrl, CMD_ALIVE);
++
++ if ((pwrctrl->pwr_mode != PS_MODE_ACTIVE) &&
++ (pwrctrl->bFwCurrentInPSMode == _TRUE))
++ {
++ if ((pwrctrl->alives == 0) &&
++ (pwrctrl->cpwm > PS_STATE_S0))
++ {
++ rtw_set_rpwm(padapter, PS_STATE_S0);
++ }
++
++ RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_notice_,
++ ("rtw_unregister_cmd_alive: cpwm=0x%02x alives=0x%08x\n",
++ pwrctrl->cpwm, pwrctrl->alives));
++ }
++
++ _exit_pwrlock(&pwrctrl->lock);
++
++_func_exit_;
++}
++
++/*
++ * Caller: ISR
++ */
++void rtw_unregister_rx_alive(PADAPTER padapter)
++{
++ struct pwrctrl_priv *pwrctrl;
++
++_func_enter_;
++
++ pwrctrl = &padapter->pwrctrlpriv;
++
++ _enter_pwrlock(&pwrctrl->lock);
++
++ unregister_task_alive(pwrctrl, RECV_ALIVE);
++
++ RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_notice_,
++ ("rtw_unregister_rx_alive: cpwm=0x%02x alives=0x%08x\n",
++ pwrctrl->cpwm, pwrctrl->alives));
++
++ _exit_pwrlock(&pwrctrl->lock);
++
++_func_exit_;
++}
++
++void rtw_unregister_evt_alive(PADAPTER padapter)
++{
++ struct pwrctrl_priv *pwrctrl;
++
++_func_enter_;
++
++ pwrctrl = &padapter->pwrctrlpriv;
++
++ unregister_task_alive(pwrctrl, EVT_ALIVE);
++
++ RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_notice_,
++ ("rtw_unregister_evt_alive: cpwm=0x%02x alives=0x%08x\n",
++ pwrctrl->cpwm, pwrctrl->alives));
++
++ _exit_pwrlock(&pwrctrl->lock);
++
++_func_exit_;
++}
++#endif /* CONFIG_LPS_LCLK */
++
++#ifdef CONFIG_RESUME_IN_WORKQUEUE
++static void resume_workitem_callback(struct work_struct *work);
++#endif //CONFIG_RESUME_IN_WORKQUEUE
++
++void rtw_init_pwrctrl_priv(PADAPTER padapter)
++{
++ struct pwrctrl_priv *pwrctrlpriv = &padapter->pwrctrlpriv;
++
++_func_enter_;
++
++#ifdef PLATFORM_WINDOWS
++ pwrctrlpriv->pnp_current_pwr_state=NdisDeviceStateD0;
++#endif
++
++ _init_pwrlock(&pwrctrlpriv->lock);
++ pwrctrlpriv->rf_pwrstate = rf_on;
++ pwrctrlpriv->ips_enter_cnts=0;
++ pwrctrlpriv->ips_leave_cnts=0;
++
++ pwrctrlpriv->ips_mode = padapter->registrypriv.ips_mode;
++ pwrctrlpriv->ips_mode_req = padapter->registrypriv.ips_mode;
++
++ pwrctrlpriv->pwr_state_check_interval = RTW_PWR_STATE_CHK_INTERVAL;
++ pwrctrlpriv->pwr_state_check_cnts = 0;
++ pwrctrlpriv->bInternalAutoSuspend = _FALSE;
++ pwrctrlpriv->bInSuspend = _FALSE;
++ pwrctrlpriv->bkeepfwalive = _FALSE;
++
++#ifdef CONFIG_AUTOSUSPEND
++#ifdef SUPPORT_HW_RFOFF_DETECTED
++ pwrctrlpriv->pwr_state_check_interval = (pwrctrlpriv->bHWPwrPindetect) ?1000:2000;
++#endif
++#endif
++
++ pwrctrlpriv->LpsIdleCount = 0;
++ //pwrctrlpriv->FWCtrlPSMode =padapter->registrypriv.power_mgnt;// PS_MODE_MIN;
++ pwrctrlpriv->power_mgnt =padapter->registrypriv.power_mgnt;// PS_MODE_MIN;
++ pwrctrlpriv->bLeisurePs = (PS_MODE_ACTIVE != pwrctrlpriv->power_mgnt)?_TRUE:_FALSE;
++
++ pwrctrlpriv->bFwCurrentInPSMode = _FALSE;
++
++ pwrctrlpriv->cpwm = PS_STATE_S4;
++
++ pwrctrlpriv->pwr_mode = PS_MODE_ACTIVE;
++
++
++ pwrctrlpriv->smart_ps = 0;
++
++ pwrctrlpriv->tog = 0x80;
++
++#ifdef PLATFORM_LINUX
++ _init_timer(&(pwrctrlpriv->pwr_state_check_timer), padapter->pnetdev, pwr_state_check_handler, (u8 *)padapter);
++#endif
++
++ #ifdef CONFIG_RESUME_IN_WORKQUEUE
++ _init_workitem(&pwrctrlpriv->resume_work, resume_workitem_callback, NULL);
++ pwrctrlpriv->rtw_workqueue = create_singlethread_workqueue("rtw_workqueue");
++ #endif //CONFIG_RESUME_IN_WORKQUEUE
++
++ #if defined(CONFIG_HAS_EARLYSUSPEND) || defined(CONFIG_ANDROID_POWER)
++ pwrctrlpriv->early_suspend.suspend = NULL;
++ rtw_register_early_suspend(pwrctrlpriv);
++ #endif //CONFIG_HAS_EARLYSUSPEND || CONFIG_ANDROID_POWER
++
++
++_func_exit_;
++
++}
++
++
++void rtw_free_pwrctrl_priv(PADAPTER adapter)
++{
++ struct pwrctrl_priv *pwrctrlpriv = &adapter->pwrctrlpriv;
++
++_func_enter_;
++
++ //_rtw_memset((unsigned char *)pwrctrlpriv, 0, sizeof(struct pwrctrl_priv));
++
++
++ #ifdef CONFIG_RESUME_IN_WORKQUEUE
++ if (pwrctrlpriv->rtw_workqueue) {
++ flush_workqueue(pwrctrlpriv->rtw_workqueue);
++ destroy_workqueue(pwrctrlpriv->rtw_workqueue);
++ }
++ #endif
++
++
++ #if defined(CONFIG_HAS_EARLYSUSPEND) || defined(CONFIG_ANDROID_POWER)
++ rtw_unregister_early_suspend(pwrctrlpriv);
++ #endif //CONFIG_HAS_EARLYSUSPEND || CONFIG_ANDROID_POWER
++
++ _free_pwrlock(&pwrctrlpriv->lock);
++
++_func_exit_;
++}
++
++#ifdef CONFIG_RESUME_IN_WORKQUEUE
++#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI)
++extern int rtw_resume_process(_adapter *padapter);
++#endif
++static void resume_workitem_callback(struct work_struct *work)
++{
++ struct pwrctrl_priv *pwrpriv = container_of(work, struct pwrctrl_priv, resume_work);
++ _adapter *adapter = container_of(pwrpriv, _adapter, pwrctrlpriv);
++
++ DBG_871X("%s\n",__FUNCTION__);
++
++ #if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI)
++ rtw_resume_process(adapter);
++ #endif
++
++}
++
++void rtw_resume_in_workqueue(struct pwrctrl_priv *pwrpriv)
++{
++ // accquire system's suspend lock preventing from falliing asleep while resume in workqueue
++ rtw_lock_suspend();
++
++ #if 1
++ queue_work(pwrpriv->rtw_workqueue, &pwrpriv->resume_work);
++ #else
++ _set_workitem(&pwrpriv->resume_work);
++ #endif
++}
++#endif //CONFIG_RESUME_IN_WORKQUEUE
++
++#if defined(CONFIG_HAS_EARLYSUSPEND) || defined(CONFIG_ANDROID_POWER)
++inline bool rtw_is_earlysuspend_registered(struct pwrctrl_priv *pwrpriv)
++{
++ return (pwrpriv->early_suspend.suspend) ? _TRUE : _FALSE;
++}
++
++inline bool rtw_is_do_late_resume(struct pwrctrl_priv *pwrpriv)
++{
++ return (pwrpriv->do_late_resume) ? _TRUE : _FALSE;
++}
++
++inline void rtw_set_do_late_resume(struct pwrctrl_priv *pwrpriv, bool enable)
++{
++ pwrpriv->do_late_resume = enable;
++}
++#endif
++
++#ifdef CONFIG_HAS_EARLYSUSPEND
++#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI)
++extern int rtw_resume_process(_adapter *padapter);
++#endif
++static void rtw_early_suspend(struct early_suspend *h)
++{
++ struct pwrctrl_priv *pwrpriv = container_of(h, struct pwrctrl_priv, early_suspend);
++ DBG_871X("%s\n",__FUNCTION__);
++
++ rtw_set_do_late_resume(pwrpriv, _FALSE);
++}
++
++static void rtw_late_resume(struct early_suspend *h)
++{
++ struct pwrctrl_priv *pwrpriv = container_of(h, struct pwrctrl_priv, early_suspend);
++ _adapter *adapter = container_of(pwrpriv, _adapter, pwrctrlpriv);
++
++ DBG_871X("%s\n",__FUNCTION__);
++ if(pwrpriv->do_late_resume) {
++ #if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI)
++ rtw_set_do_late_resume(pwrpriv, _FALSE);
++ rtw_resume_process(adapter);
++ #endif
++ }
++}
++
++void rtw_register_early_suspend(struct pwrctrl_priv *pwrpriv)
++{
++ _adapter *adapter = container_of(pwrpriv, _adapter, pwrctrlpriv);
++
++#if defined(CONFIG_CONCURRENT_MODE)
++ if (adapter->adapter_type != PRIMARY_ADAPTER)
++ return;
++#endif
++
++ DBG_871X("%s\n", __FUNCTION__);
++
++ //jeff: set the early suspend level before blank screen, so we wll do late resume after scree is lit
++ pwrpriv->early_suspend.level = EARLY_SUSPEND_LEVEL_BLANK_SCREEN - 20;
++ pwrpriv->early_suspend.suspend = rtw_early_suspend;
++ pwrpriv->early_suspend.resume = rtw_late_resume;
++ register_early_suspend(&pwrpriv->early_suspend);
++
++
++}
++
++void rtw_unregister_early_suspend(struct pwrctrl_priv *pwrpriv)
++{
++ _adapter *adapter = container_of(pwrpriv, _adapter, pwrctrlpriv);
++
++#if defined(CONFIG_CONCURRENT_MODE)
++ if (adapter->adapter_type != PRIMARY_ADAPTER)
++ return;
++#endif
++
++ DBG_871X("%s\n", __FUNCTION__);
++
++ rtw_set_do_late_resume(pwrpriv, _FALSE);
++
++ if (pwrpriv->early_suspend.suspend)
++ unregister_early_suspend(&pwrpriv->early_suspend);
++
++ pwrpriv->early_suspend.suspend = NULL;
++ pwrpriv->early_suspend.resume = NULL;
++}
++#endif //CONFIG_HAS_EARLYSUSPEND
++
++#ifdef CONFIG_ANDROID_POWER
++#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI)
++extern int rtw_resume_process(PADAPTER padapter);
++#endif
++static void rtw_early_suspend(android_early_suspend_t *h)
++{
++ struct pwrctrl_priv *pwrpriv = container_of(h, struct pwrctrl_priv, early_suspend);
++ DBG_871X("%s\n",__FUNCTION__);
++
++ rtw_set_do_late_resume(pwrpriv, _FALSE);
++}
++
++static void rtw_late_resume(android_early_suspend_t *h)
++{
++ struct pwrctrl_priv *pwrpriv = container_of(h, struct pwrctrl_priv, early_suspend);
++ _adapter *adapter = container_of(pwrpriv, _adapter, pwrctrlpriv);
++
++ DBG_871X("%s\n",__FUNCTION__);
++ if(pwrpriv->do_late_resume) {
++ #if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI)
++ rtw_set_do_late_resume(pwrpriv, _FALSE);
++ rtw_resume_process(adapter);
++ #endif
++ }
++}
++
++void rtw_register_early_suspend(struct pwrctrl_priv *pwrpriv)
++{
++ _adapter *adapter = container_of(pwrpriv, _adapter, pwrctrlpriv);
++
++#if defined(CONFIG_CONCURRENT_MODE)
++ if (adapter->adapter_type != PRIMARY_ADAPTER)
++ return;
++#endif
++
++ DBG_871X("%s\n", __FUNCTION__);
++
++ //jeff: set the early suspend level before blank screen, so we wll do late resume after scree is lit
++ pwrpriv->early_suspend.level = ANDROID_EARLY_SUSPEND_LEVEL_BLANK_SCREEN - 20;
++ pwrpriv->early_suspend.suspend = rtw_early_suspend;
++ pwrpriv->early_suspend.resume = rtw_late_resume;
++ android_register_early_suspend(&pwrpriv->early_suspend);
++}
++
++void rtw_unregister_early_suspend(struct pwrctrl_priv *pwrpriv)
++{
++ _adapter *adapter = container_of(pwrpriv, _adapter, pwrctrlpriv);
++
++#if defined(CONFIG_CONCURRENT_MODE)
++ if (adapter->adapter_type != PRIMARY_ADAPTER)
++ return;
++#endif
++
++ DBG_871X("%s\n", __FUNCTION__);
++
++ rtw_set_do_late_resume(pwrpriv, _FALSE);
++
++ if (pwrpriv->early_suspend.suspend)
++ android_unregister_early_suspend(&pwrpriv->early_suspend);
++
++ pwrpriv->early_suspend.suspend = NULL;
++ pwrpriv->early_suspend.resume = NULL;
++}
++#endif //CONFIG_ANDROID_POWER
++
++u8 rtw_interface_ps_func(_adapter *padapter,HAL_INTF_PS_FUNC efunc_id,u8* val)
++{
++ u8 bResult = _TRUE;
++
++ rtw_hal_intf_ps_func(padapter,efunc_id,val);
++
++ return bResult;
++}
++
++
++inline void rtw_set_ips_deny(_adapter *padapter, u32 ms)
++{
++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
++ pwrpriv->ips_deny_time = rtw_get_current_time() + rtw_ms_to_systime(ms);
++}
++
++/*
++* rtw_pwr_wakeup - Wake the NIC up from: 1)IPS. 2)USB autosuspend
++* @adapter: pointer to _adapter structure
++* @ips_deffer_ms: the ms wiil prevent from falling into IPS after wakeup
++* Return _SUCCESS or _FAIL
++*/
++int _rtw_pwr_wakeup(_adapter *padapter, u32 ips_deffer_ms, const char *caller)
++{
++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ int ret = _SUCCESS;
++ u32 start = rtw_get_current_time();
++
++#ifdef CONFIG_CONCURRENT_MODE
++ if (padapter->pbuddy_adapter)
++ LeaveAllPowerSaveMode(padapter->pbuddy_adapter);
++
++ if ((padapter->isprimary == _FALSE) && padapter->pbuddy_adapter){
++ padapter = padapter->pbuddy_adapter;
++ pwrpriv = &padapter->pwrctrlpriv;
++ pmlmepriv = &padapter->mlmepriv;
++ }
++#endif
++
++ if (pwrpriv->ips_deny_time < rtw_get_current_time() + rtw_ms_to_systime(ips_deffer_ms))
++ pwrpriv->ips_deny_time = rtw_get_current_time() + rtw_ms_to_systime(ips_deffer_ms);
++
++ if (pwrpriv->ps_processing) {
++ DBG_871X("%s wait ps_processing...\n", __func__);
++ while (pwrpriv->ps_processing && rtw_get_passing_time_ms(start) <= 3000)
++ rtw_msleep_os(10);
++ if (pwrpriv->ps_processing)
++ DBG_871X("%s wait ps_processing timeout\n", __func__);
++ else
++ DBG_871X("%s wait ps_processing done\n", __func__);
++ }
++
++#ifdef DBG_CONFIG_ERROR_DETECT
++ if (rtw_hal_sreset_inprogress(padapter)) {
++ DBG_871X("%s wait sreset_inprogress...\n", __func__);
++ while (rtw_hal_sreset_inprogress(padapter) && rtw_get_passing_time_ms(start) <= 4000)
++ rtw_msleep_os(10);
++ if (rtw_hal_sreset_inprogress(padapter))
++ DBG_871X("%s wait sreset_inprogress timeout\n", __func__);
++ else
++ DBG_871X("%s wait sreset_inprogress done\n", __func__);
++ }
++#endif
++
++ if (pwrpriv->bInternalAutoSuspend == _FALSE && pwrpriv->bInSuspend) {
++ DBG_871X("%s wait bInSuspend...\n", __func__);
++ while (pwrpriv->bInSuspend
++ && ((rtw_get_passing_time_ms(start) <= 3000 && !rtw_is_do_late_resume(pwrpriv))
++ || (rtw_get_passing_time_ms(start) <= 500 && rtw_is_do_late_resume(pwrpriv)))
++ ) {
++ rtw_msleep_os(10);
++ }
++ if (pwrpriv->bInSuspend)
++ DBG_871X("%s wait bInSuspend timeout\n", __func__);
++ else
++ DBG_871X("%s wait bInSuspend done\n", __func__);
++ }
++
++ //System suspend is not allowed to wakeup
++ if((pwrpriv->bInternalAutoSuspend == _FALSE) && (_TRUE == pwrpriv->bInSuspend )){
++ ret = _FAIL;
++ goto exit;
++ }
++
++ //block???
++ if((pwrpriv->bInternalAutoSuspend == _TRUE) && (padapter->net_closed == _TRUE)) {
++ ret = _FAIL;
++ goto exit;
++ }
++
++ //I think this should be check in IPS, LPS, autosuspend functions...
++ if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)
++ {
++ ret = _SUCCESS;
++ goto exit;
++ }
++
++ if(rf_off == pwrpriv->rf_pwrstate )
++ {
++#ifdef CONFIG_USB_HCI
++#ifdef CONFIG_AUTOSUSPEND
++ if(pwrpriv->brfoffbyhw==_TRUE)
++ {
++ DBG_8192C("hw still in rf_off state ...........\n");
++ ret = _FAIL;
++ goto exit;
++ }
++ else if(padapter->registrypriv.usbss_enable)
++ {
++ DBG_8192C("%s call autoresume_enter....\n",__FUNCTION__);
++ if(_FAIL == autoresume_enter(padapter))
++ {
++ DBG_8192C("======> autoresume fail.............\n");
++ ret = _FAIL;
++ goto exit;
++ }
++ }
++ else
++#endif
++#endif
++ {
++#ifdef CONFIG_IPS
++ DBG_8192C("%s call ips_leave....\n",__FUNCTION__);
++ if(_FAIL == ips_leave(padapter))
++ {
++ DBG_8192C("======> ips_leave fail.............\n");
++ ret = _FAIL;
++ goto exit;
++ }
++#endif
++ }
++ }
++
++ //TODO: the following checking need to be merged...
++ if(padapter->bDriverStopped
++ || !padapter->bup
++ || !padapter->hw_init_completed
++ ){
++ DBG_8192C("%s: bDriverStopped=%d, bup=%d, hw_init_completed=%u\n"
++ , caller
++ , padapter->bDriverStopped
++ , padapter->bup
++ , padapter->hw_init_completed);
++ ret= _FALSE;
++ goto exit;
++ }
++
++exit:
++ if (pwrpriv->ips_deny_time < rtw_get_current_time() + rtw_ms_to_systime(ips_deffer_ms))
++ pwrpriv->ips_deny_time = rtw_get_current_time() + rtw_ms_to_systime(ips_deffer_ms);
++ return ret;
++
++}
++
++int rtw_pm_set_lps(_adapter *padapter, u8 mode)
++{
++ int ret = 0;
++ struct pwrctrl_priv *pwrctrlpriv = &padapter->pwrctrlpriv;
++
++ if ( mode < PS_MODE_NUM )
++ {
++ if(pwrctrlpriv->power_mgnt !=mode)
++ {
++ if(PS_MODE_ACTIVE == mode)
++ {
++ LeaveAllPowerSaveMode(padapter);
++ }
++ else
++ {
++ pwrctrlpriv->LpsIdleCount = 2;
++ }
++ pwrctrlpriv->power_mgnt = mode;
++ pwrctrlpriv->bLeisurePs = (PS_MODE_ACTIVE != pwrctrlpriv->power_mgnt)?_TRUE:_FALSE;
++ }
++ }
++ else
++ {
++ ret = -EINVAL;
++ }
++
++ return ret;
++}
++
++int rtw_pm_set_ips(_adapter *padapter, u8 mode)
++{
++ struct pwrctrl_priv *pwrctrlpriv = &padapter->pwrctrlpriv;
++
++ if( mode == IPS_NORMAL || mode == IPS_LEVEL_2 ) {
++ rtw_ips_mode_req(pwrctrlpriv, mode);
++ DBG_871X("%s %s\n", __FUNCTION__, mode == IPS_NORMAL?"IPS_NORMAL":"IPS_LEVEL_2");
++ return 0;
++ }
++ else if(mode ==IPS_NONE){
++ rtw_ips_mode_req(pwrctrlpriv, mode);
++ DBG_871X("%s %s\n", __FUNCTION__, "IPS_NONE");
++ if((padapter->bSurpriseRemoved ==0)&&(_FAIL == rtw_pwr_wakeup(padapter)) )
++ return -EFAULT;
++ }
++ else {
++ return -EINVAL;
++ }
++ return 0;
++}
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/core/rtw_recv.c linux-xbian-rpi/drivers/net/wireless/rtl8192cu/core/rtw_recv.c
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/core/rtw_recv.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/core/rtw_recv.c 2015-07-28 01:20:58.305654202 +0200
+@@ -0,0 +1,4286 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#define _RTW_RECV_C_
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++#include <recv_osdep.h>
++#include <mlme_osdep.h>
++#include <ip.h>
++#include <if_ether.h>
++#include <ethernet.h>
++
++#ifdef CONFIG_USB_HCI
++#include <usb_ops.h>
++#endif
++
++#if defined (PLATFORM_LINUX) && defined (PLATFORM_WINDOWS)
++
++#error "Shall be Linux or Windows, but not both!\n"
++
++#endif
++
++#include <wifi.h>
++#include <circ_buf.h>
++
++#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
++void rtw_signal_stat_timer_hdl(RTW_TIMER_HDL_ARGS);
++#endif //CONFIG_NEW_SIGNAL_STAT_PROCESS
++
++
++void _rtw_init_sta_recv_priv(struct sta_recv_priv *psta_recvpriv)
++{
++
++
++_func_enter_;
++
++ _rtw_memset((u8 *)psta_recvpriv, 0, sizeof (struct sta_recv_priv));
++
++ _rtw_spinlock_init(&psta_recvpriv->lock);
++
++ //for(i=0; i<MAX_RX_NUMBLKS; i++)
++ // _rtw_init_queue(&psta_recvpriv->blk_strms[i]);
++
++ _rtw_init_queue(&psta_recvpriv->defrag_q);
++
++_func_exit_;
++
++}
++
++sint _rtw_init_recv_priv(struct recv_priv *precvpriv, _adapter *padapter)
++{
++ sint i;
++
++ union recv_frame *precvframe;
++
++ sint res=_SUCCESS;
++
++_func_enter_;
++
++ // We don't need to memset padapter->XXX to zero, because adapter is allocated by rtw_zvmalloc().
++ //_rtw_memset((unsigned char *)precvpriv, 0, sizeof (struct recv_priv));
++
++ _rtw_spinlock_init(&precvpriv->lock);
++
++ _rtw_init_queue(&precvpriv->free_recv_queue);
++ _rtw_init_queue(&precvpriv->recv_pending_queue);
++ _rtw_init_queue(&precvpriv->uc_swdec_pending_queue);
++
++ precvpriv->adapter = padapter;
++
++ precvpriv->free_recvframe_cnt = NR_RECVFRAME;
++
++ rtw_os_recv_resource_init(precvpriv, padapter);
++
++ precvpriv->pallocated_frame_buf = rtw_zvmalloc(NR_RECVFRAME * sizeof(union recv_frame) + RXFRAME_ALIGN_SZ);
++
++ if(precvpriv->pallocated_frame_buf==NULL){
++ res= _FAIL;
++ goto exit;
++ }
++ //_rtw_memset(precvpriv->pallocated_frame_buf, 0, NR_RECVFRAME * sizeof(union recv_frame) + RXFRAME_ALIGN_SZ);
++
++ precvpriv->precv_frame_buf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(precvpriv->pallocated_frame_buf), RXFRAME_ALIGN_SZ);
++ //precvpriv->precv_frame_buf = precvpriv->pallocated_frame_buf + RXFRAME_ALIGN_SZ -
++ // ((SIZE_PTR) (precvpriv->pallocated_frame_buf) &(RXFRAME_ALIGN_SZ-1));
++
++ precvframe = (union recv_frame*) precvpriv->precv_frame_buf;
++
++
++ for(i=0; i < NR_RECVFRAME ; i++)
++ {
++ _rtw_init_listhead(&(precvframe->u.list));
++
++ rtw_list_insert_tail(&(precvframe->u.list), &(precvpriv->free_recv_queue.queue));
++
++ res = rtw_os_recv_resource_alloc(padapter, precvframe);
++
++ precvframe->u.hdr.adapter =padapter;
++ precvframe++;
++
++ }
++
++#ifdef CONFIG_USB_HCI
++
++ precvpriv->rx_pending_cnt=1;
++
++ _rtw_init_sema(&precvpriv->allrxreturnevt, 0);
++
++#endif
++
++ res = rtw_hal_init_recv_priv(padapter);
++
++ precvpriv->recvbuf_skb_alloc_fail_cnt = 0;
++ precvpriv->recvbuf_null_cnt = 0;
++ precvpriv->read_port_complete_EINPROGRESS_cnt = 0;
++ precvpriv->read_port_complete_other_urb_err_cnt = 0;
++
++#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
++ #ifdef PLATFORM_LINUX
++ _init_timer(&precvpriv->signal_stat_timer, padapter->pnetdev, RTW_TIMER_HDL_NAME(signal_stat), padapter);
++ #elif defined(PLATFORM_OS_CE) || defined(PLATFORM_WINDOWS)
++ _init_timer(&precvpriv->signal_stat_timer, padapter->hndis_adapter, RTW_TIMER_HDL_NAME(signal_stat), padapter);
++ #endif
++
++ precvpriv->signal_stat_sampling_interval = 1000; //ms
++ //precvpriv->signal_stat_converging_constant = 5000; //ms
++
++ rtw_set_signal_stat_timer(precvpriv);
++#endif //CONFIG_NEW_SIGNAL_STAT_PROCESS
++
++exit:
++
++_func_exit_;
++
++ return res;
++
++}
++
++void rtw_mfree_recv_priv_lock(struct recv_priv *precvpriv);
++void rtw_mfree_recv_priv_lock(struct recv_priv *precvpriv)
++{
++ _rtw_spinlock_free(&precvpriv->lock);
++#ifdef CONFIG_RECV_THREAD_MODE
++ _rtw_free_sema(&precvpriv->recv_sema);
++ _rtw_free_sema(&precvpriv->terminate_recvthread_sema);
++#endif
++
++ _rtw_spinlock_free(&precvpriv->free_recv_queue.lock);
++ _rtw_spinlock_free(&precvpriv->recv_pending_queue.lock);
++
++ _rtw_spinlock_free(&precvpriv->free_recv_buf_queue.lock);
++
++#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX
++ _rtw_spinlock_free(&precvpriv->recv_buf_pending_queue.lock);
++#endif // CONFIG_USE_USB_BUFFER_ALLOC_RX
++}
++
++void _rtw_free_recv_priv (struct recv_priv *precvpriv)
++{
++ _adapter *padapter = precvpriv->adapter;
++
++_func_enter_;
++
++ rtw_free_uc_swdec_pending_queue(padapter);
++
++ rtw_mfree_recv_priv_lock(precvpriv);
++
++ rtw_os_recv_resource_free(precvpriv);
++
++ if(precvpriv->pallocated_frame_buf) {
++ rtw_vmfree(precvpriv->pallocated_frame_buf, NR_RECVFRAME * sizeof(union recv_frame) + RXFRAME_ALIGN_SZ);
++ }
++
++ rtw_hal_free_recv_priv(padapter);
++
++_func_exit_;
++
++}
++
++union recv_frame *_rtw_alloc_recvframe (_queue *pfree_recv_queue)
++{
++
++ union recv_frame *precvframe;
++ _list *plist, *phead;
++ _adapter *padapter;
++ struct recv_priv *precvpriv;
++_func_enter_;
++
++ if(_rtw_queue_empty(pfree_recv_queue) == _TRUE)
++ {
++ precvframe = NULL;
++ }
++ else
++ {
++ phead = get_list_head(pfree_recv_queue);
++
++ plist = get_next(phead);
++
++ precvframe = LIST_CONTAINOR(plist, union recv_frame, u);
++
++ rtw_list_delete(&precvframe->u.hdr.list);
++ padapter=precvframe->u.hdr.adapter;
++ if(padapter !=NULL){
++ precvpriv=&padapter->recvpriv;
++ if(pfree_recv_queue == &precvpriv->free_recv_queue)
++ precvpriv->free_recvframe_cnt--;
++ }
++ }
++
++_func_exit_;
++
++ return precvframe;
++
++}
++
++union recv_frame *rtw_alloc_recvframe (_queue *pfree_recv_queue)
++{
++ _irqL irqL;
++ union recv_frame *precvframe;
++
++ _enter_critical_bh(&pfree_recv_queue->lock, &irqL);
++
++ precvframe = _rtw_alloc_recvframe(pfree_recv_queue);
++
++ _exit_critical_bh(&pfree_recv_queue->lock, &irqL);
++
++ return precvframe;
++}
++
++void rtw_init_recvframe(union recv_frame *precvframe, struct recv_priv *precvpriv)
++{
++ /* Perry: This can be removed */
++ _rtw_init_listhead(&precvframe->u.hdr.list);
++
++ precvframe->u.hdr.len=0;
++}
++
++int rtw_free_recvframe(union recv_frame *precvframe, _queue *pfree_recv_queue)
++{
++ _irqL irqL;
++ _adapter *padapter=precvframe->u.hdr.adapter;
++ struct recv_priv *precvpriv = &padapter->recvpriv;
++
++_func_enter_;
++
++#ifdef CONFIG_CONCURRENT_MODE
++ if(padapter->adapter_type > PRIMARY_ADAPTER)
++ {
++ padapter = padapter->pbuddy_adapter;//get primary_padapter
++ precvpriv = &padapter->recvpriv;
++ pfree_recv_queue = &precvpriv->free_recv_queue;
++ precvframe->u.hdr.adapter = padapter;
++ }
++#endif
++
++
++#ifdef PLATFORM_WINDOWS
++ rtw_os_read_port(padapter, precvframe->u.hdr.precvbuf);
++#endif
++
++#if defined(PLATFORM_LINUX) || defined(PLATFORM_FREEBSD)
++
++ if(precvframe->u.hdr.pkt)
++ {
++#ifdef CONFIG_BSD_RX_USE_MBUF
++ m_freem(precvframe->u.hdr.pkt);
++#else // CONFIG_BSD_RX_USE_MBUF
++ rtw_skb_free(precvframe->u.hdr.pkt);//free skb by driver
++#endif // CONFIG_BSD_RX_USE_MBUF
++ precvframe->u.hdr.pkt = NULL;
++ }
++
++#endif //defined(PLATFORM_LINUX) || defined(PLATFORM_FREEBSD)
++
++ _enter_critical_bh(&pfree_recv_queue->lock, &irqL);
++
++ rtw_list_delete(&(precvframe->u.hdr.list));
++
++ rtw_list_insert_tail(&(precvframe->u.hdr.list), get_list_head(pfree_recv_queue));
++
++ if(padapter !=NULL){
++ if(pfree_recv_queue == &precvpriv->free_recv_queue)
++ precvpriv->free_recvframe_cnt++;
++ }
++
++ _exit_critical_bh(&pfree_recv_queue->lock, &irqL);
++
++_func_exit_;
++
++ return _SUCCESS;
++
++}
++
++
++
++
++sint _rtw_enqueue_recvframe(union recv_frame *precvframe, _queue *queue)
++{
++
++ _adapter *padapter=precvframe->u.hdr.adapter;
++ struct recv_priv *precvpriv = &padapter->recvpriv;
++
++_func_enter_;
++
++ //_rtw_init_listhead(&(precvframe->u.hdr.list));
++ rtw_list_delete(&(precvframe->u.hdr.list));
++
++
++ rtw_list_insert_tail(&(precvframe->u.hdr.list), get_list_head(queue));
++
++ if (padapter != NULL) {
++ if (queue == &precvpriv->free_recv_queue)
++ precvpriv->free_recvframe_cnt++;
++ }
++
++_func_exit_;
++
++ return _SUCCESS;
++}
++
++sint rtw_enqueue_recvframe(union recv_frame *precvframe, _queue *queue)
++{
++ sint ret;
++ _irqL irqL;
++
++ //_spinlock(&pfree_recv_queue->lock);
++ _enter_critical_bh(&queue->lock, &irqL);
++ ret = _rtw_enqueue_recvframe(precvframe, queue);
++ //_rtw_spinunlock(&pfree_recv_queue->lock);
++ _exit_critical_bh(&queue->lock, &irqL);
++
++ return ret;
++}
++
++/*
++sint rtw_enqueue_recvframe(union recv_frame *precvframe, _queue *queue)
++{
++ return rtw_free_recvframe(precvframe, queue);
++}
++*/
++
++
++
++
++/*
++caller : defrag ; recvframe_chk_defrag in recv_thread (passive)
++pframequeue: defrag_queue : will be accessed in recv_thread (passive)
++
++using spinlock to protect
++
++*/
++
++void rtw_free_recvframe_queue(_queue *pframequeue, _queue *pfree_recv_queue)
++{
++ union recv_frame *precvframe;
++ _list *plist, *phead;
++
++_func_enter_;
++ _rtw_spinlock(&pframequeue->lock);
++
++ phead = get_list_head(pframequeue);
++ plist = get_next(phead);
++
++ while(rtw_end_of_queue_search(phead, plist) == _FALSE)
++ {
++ precvframe = LIST_CONTAINOR(plist, union recv_frame, u);
++
++ plist = get_next(plist);
++
++ //rtw_list_delete(&precvframe->u.hdr.list); // will do this in rtw_free_recvframe()
++
++ rtw_free_recvframe(precvframe, pfree_recv_queue);
++ }
++
++ _rtw_spinunlock(&pframequeue->lock);
++
++_func_exit_;
++
++}
++
++u32 rtw_free_uc_swdec_pending_queue(_adapter *adapter)
++{
++ u32 cnt = 0;
++ union recv_frame *pending_frame;
++ while((pending_frame=rtw_alloc_recvframe(&adapter->recvpriv.uc_swdec_pending_queue))) {
++ rtw_free_recvframe(pending_frame, &adapter->recvpriv.free_recv_queue);
++ DBG_871X("%s: dequeue uc_swdec_pending_queue\n", __func__);
++ cnt++;
++ }
++
++ return cnt;
++}
++
++
++sint rtw_enqueue_recvbuf_to_head(struct recv_buf *precvbuf, _queue *queue)
++{
++ _irqL irqL;
++
++ _enter_critical(&queue->lock, &irqL);
++
++ rtw_list_delete(&precvbuf->list);
++ rtw_list_insert_head(&precvbuf->list, get_list_head(queue));
++
++ _exit_critical(&queue->lock, &irqL);
++
++ return _SUCCESS;
++}
++
++sint rtw_enqueue_recvbuf(struct recv_buf *precvbuf, _queue *queue)
++{
++ _irqL irqL;
++
++ _enter_critical(&queue->lock, &irqL);
++
++ rtw_list_delete(&precvbuf->list);
++
++ rtw_list_insert_tail(&precvbuf->list, get_list_head(queue));
++
++ _exit_critical(&queue->lock, &irqL);
++
++
++ return _SUCCESS;
++
++}
++
++struct recv_buf *rtw_dequeue_recvbuf (_queue *queue)
++{
++ _irqL irqL;
++ struct recv_buf *precvbuf;
++ _list *plist, *phead;
++
++ _enter_critical(&queue->lock, &irqL);
++
++ if(_rtw_queue_empty(queue) == _TRUE)
++ {
++ precvbuf = NULL;
++ }
++ else
++ {
++ phead = get_list_head(queue);
++
++ plist = get_next(phead);
++
++ precvbuf = LIST_CONTAINOR(plist, struct recv_buf, list);
++
++ rtw_list_delete(&precvbuf->list);
++
++ }
++
++ _exit_critical(&queue->lock, &irqL);
++
++
++ return precvbuf;
++
++}
++
++sint recvframe_chkmic(_adapter *adapter, union recv_frame *precvframe);
++sint recvframe_chkmic(_adapter *adapter, union recv_frame *precvframe){
++
++ sint i,res=_SUCCESS;
++ u32 datalen;
++ u8 miccode[8];
++ u8 bmic_err=_FALSE,brpt_micerror = _TRUE;
++ u8 *pframe, *payload,*pframemic;
++ u8 *mickey;
++ //u8 *iv,rxdata_key_idx=0;
++ struct sta_info *stainfo;
++ struct rx_pkt_attrib *prxattrib=&precvframe->u.hdr.attrib;
++ struct security_priv *psecuritypriv=&adapter->securitypriv;
++
++ struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++_func_enter_;
++
++ stainfo=rtw_get_stainfo(&adapter->stapriv ,&prxattrib->ta[0]);
++
++ if(prxattrib->encrypt ==_TKIP_)
++ {
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("\n recvframe_chkmic:prxattrib->encrypt ==_TKIP_\n"));
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("\n recvframe_chkmic:da=0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x\n",
++ prxattrib->ra[0],prxattrib->ra[1],prxattrib->ra[2],prxattrib->ra[3],prxattrib->ra[4],prxattrib->ra[5]));
++
++ //calculate mic code
++ if(stainfo!= NULL)
++ {
++ if(IS_MCAST(prxattrib->ra))
++ {
++ //mickey=&psecuritypriv->dot118021XGrprxmickey.skey[0];
++ //iv = precvframe->u.hdr.rx_data+prxattrib->hdrlen;
++ //rxdata_key_idx =( ((iv[3])>>6)&0x3) ;
++ mickey=&psecuritypriv->dot118021XGrprxmickey[prxattrib->key_index].skey[0];
++
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("\n recvframe_chkmic: bcmc key \n"));
++ //DBG_871X("\n recvframe_chkmic: bcmc key psecuritypriv->dot118021XGrpKeyid(%d),pmlmeinfo->key_index(%d) ,recv key_id(%d)\n",
++ // psecuritypriv->dot118021XGrpKeyid,pmlmeinfo->key_index,rxdata_key_idx);
++
++ if(psecuritypriv->binstallGrpkey==_FALSE)
++ {
++ res=_FAIL;
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("\n recvframe_chkmic:didn't install group key!!!!!!!!!!\n"));
++ DBG_871X("\n recvframe_chkmic:didn't install group key!!!!!!!!!!\n");
++ goto exit;
++ }
++ }
++ else{
++ mickey=&stainfo->dot11tkiprxmickey.skey[0];
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("\n recvframe_chkmic: unicast key \n"));
++ }
++
++ datalen=precvframe->u.hdr.len-prxattrib->hdrlen-prxattrib->iv_len-prxattrib->icv_len-8;//icv_len included the mic code
++ pframe=precvframe->u.hdr.rx_data;
++ payload=pframe+prxattrib->hdrlen+prxattrib->iv_len;
++
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("\n prxattrib->iv_len=%d prxattrib->icv_len=%d\n",prxattrib->iv_len,prxattrib->icv_len));
++
++ //rtw_seccalctkipmic(&stainfo->dot11tkiprxmickey.skey[0],pframe,payload, datalen ,&miccode[0],(unsigned char)prxattrib->priority); //care the length of the data
++
++ rtw_seccalctkipmic(mickey,pframe,payload, datalen ,&miccode[0],(unsigned char)prxattrib->priority); //care the length of the data
++
++ pframemic=payload+datalen;
++
++ bmic_err=_FALSE;
++
++ for(i=0;i<8;i++){
++ if(miccode[i] != *(pframemic+i)){
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("recvframe_chkmic:miccode[%d](%02x) != *(pframemic+%d)(%02x) ",i,miccode[i],i,*(pframemic+i)));
++ bmic_err=_TRUE;
++ }
++ }
++
++
++ if(bmic_err==_TRUE){
++
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("\n *(pframemic-8)-*(pframemic-1)=0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x\n",
++ *(pframemic-8),*(pframemic-7),*(pframemic-6),*(pframemic-5),*(pframemic-4),*(pframemic-3),*(pframemic-2),*(pframemic-1)));
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("\n *(pframemic-16)-*(pframemic-9)=0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x\n",
++ *(pframemic-16),*(pframemic-15),*(pframemic-14),*(pframemic-13),*(pframemic-12),*(pframemic-11),*(pframemic-10),*(pframemic-9)));
++
++ {
++ uint i;
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("\n ======demp packet (len=%d)======\n",precvframe->u.hdr.len));
++ for(i=0;i<precvframe->u.hdr.len;i=i+8){
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x",
++ *(precvframe->u.hdr.rx_data+i),*(precvframe->u.hdr.rx_data+i+1),
++ *(precvframe->u.hdr.rx_data+i+2),*(precvframe->u.hdr.rx_data+i+3),
++ *(precvframe->u.hdr.rx_data+i+4),*(precvframe->u.hdr.rx_data+i+5),
++ *(precvframe->u.hdr.rx_data+i+6),*(precvframe->u.hdr.rx_data+i+7)));
++ }
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("\n ======demp packet end [len=%d]======\n",precvframe->u.hdr.len));
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("\n hrdlen=%d, \n",prxattrib->hdrlen));
++ }
++
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("ra=0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x psecuritypriv->binstallGrpkey=%d ",
++ prxattrib->ra[0],prxattrib->ra[1],prxattrib->ra[2],
++ prxattrib->ra[3],prxattrib->ra[4],prxattrib->ra[5],psecuritypriv->binstallGrpkey));
++
++ // double check key_index for some timing issue ,
++ // cannot compare with psecuritypriv->dot118021XGrpKeyid also cause timing issue
++ if((IS_MCAST(prxattrib->ra)==_TRUE) && (prxattrib->key_index != pmlmeinfo->key_index ))
++ brpt_micerror = _FALSE;
++
++ if(brpt_micerror == _TRUE)
++ {
++ rtw_handle_tkip_mic_err(adapter,(u8)IS_MCAST(prxattrib->ra));
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,(" mic error :prxattrib->bdecrypted=%d \n", brpt_micerror));
++ DBG_871X(" mic error :brpt_micerror=%d\n", brpt_micerror);
++ }
++
++ res=_FAIL;
++
++ }
++ else{
++ //mic checked ok
++ if((psecuritypriv->bcheck_grpkey ==_FALSE)&&(IS_MCAST(prxattrib->ra)==_TRUE)){
++ psecuritypriv->bcheck_grpkey =_TRUE;
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("psecuritypriv->bcheck_grpkey =_TRUE"));
++ }
++ }
++
++ }
++ else
++ {
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("recvframe_chkmic: rtw_get_stainfo==NULL!!!\n"));
++ }
++
++ recvframe_pull_tail(precvframe, 8);
++
++ }
++
++exit:
++
++_func_exit_;
++
++ return res;
++
++}
++
++//decrypt and set the ivlen,icvlen of the recv_frame
++union recv_frame * decryptor(_adapter *padapter,union recv_frame *precv_frame);
++union recv_frame * decryptor(_adapter *padapter,union recv_frame *precv_frame)
++{
++
++ struct rx_pkt_attrib *prxattrib = &precv_frame->u.hdr.attrib;
++ struct security_priv *psecuritypriv=&padapter->securitypriv;
++ union recv_frame *return_packet=precv_frame;
++ u32 res=_SUCCESS;
++_func_enter_;
++
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("prxstat->decrypted=%x prxattrib->encrypt = 0x%03x\n",prxattrib->bdecrypted,prxattrib->encrypt));
++
++ if(prxattrib->encrypt>0)
++ {
++ u8 *iv = precv_frame->u.hdr.rx_data+prxattrib->hdrlen;
++ prxattrib->key_index = ( ((iv[3])>>6)&0x3) ;
++
++ if(prxattrib->key_index > WEP_KEYS)
++ {
++ DBG_871X("prxattrib->key_index(%d) > WEP_KEYS \n", prxattrib->key_index);
++
++ switch(prxattrib->encrypt){
++ case _WEP40_:
++ case _WEP104_:
++ prxattrib->key_index = psecuritypriv->dot11PrivacyKeyIndex;
++ break;
++ case _TKIP_:
++ case _AES_:
++ default:
++ prxattrib->key_index = psecuritypriv->dot118021XGrpKeyid;
++ break;
++ }
++ }
++ }
++
++ if((prxattrib->encrypt>0) && ((prxattrib->bdecrypted==0) ||(psecuritypriv->sw_decrypt==_TRUE)))
++ {
++
++#ifdef CONFIG_CONCURRENT_MODE
++ if(!IS_MCAST(prxattrib->ra))//bc/mc packets use sw decryption for concurrent mode
++#endif
++ psecuritypriv->hw_decrypted=_FALSE;
++
++ #ifdef DBG_RX_DECRYPTOR
++ DBG_871X("prxstat->bdecrypted:%d, prxattrib->encrypt:%d, Setting psecuritypriv->hw_decrypted = %d\n"
++ , prxattrib->bdecrypted ,prxattrib->encrypt, psecuritypriv->hw_decrypted);
++ #endif
++
++ switch(prxattrib->encrypt){
++ case _WEP40_:
++ case _WEP104_:
++ rtw_wep_decrypt(padapter, (u8 *)precv_frame);
++ break;
++ case _TKIP_:
++ res = rtw_tkip_decrypt(padapter, (u8 *)precv_frame);
++ break;
++ case _AES_:
++ res = rtw_aes_decrypt(padapter, (u8 * )precv_frame);
++ break;
++ default:
++ break;
++ }
++ }
++ else if(prxattrib->bdecrypted==1
++ && prxattrib->encrypt >0
++ && (psecuritypriv->busetkipkey==1 || prxattrib->encrypt !=_TKIP_ )
++ )
++ {
++#if 0
++ if((prxstat->icv==1)&&(prxattrib->encrypt!=_AES_))
++ {
++ psecuritypriv->hw_decrypted=_FALSE;
++
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("psecuritypriv->hw_decrypted=_FALSE"));
++
++ rtw_free_recvframe(precv_frame, &padapter->recvpriv.free_recv_queue);
++
++ return_packet=NULL;
++
++ }
++ else
++#endif
++ {
++ psecuritypriv->hw_decrypted=_TRUE;
++ #ifdef DBG_RX_DECRYPTOR
++ DBG_871X("prxstat->bdecrypted:%d, prxattrib->encrypt:%d, Setting psecuritypriv->hw_decrypted = %d\n"
++ , prxattrib->bdecrypted ,prxattrib->encrypt, psecuritypriv->hw_decrypted);
++ #endif
++
++ }
++ }
++ else {
++ #ifdef DBG_RX_DECRYPTOR
++ DBG_871X("prxstat->bdecrypted:%d, prxattrib->encrypt:%d, psecuritypriv->hw_decrypted:%d\n"
++ , prxattrib->bdecrypted ,prxattrib->encrypt, psecuritypriv->hw_decrypted);
++ #endif
++ }
++
++ if(res == _FAIL)
++ {
++ rtw_free_recvframe(return_packet,&padapter->recvpriv.free_recv_queue);
++ return_packet = NULL;
++
++ }
++ //recvframe_chkmic(adapter, precv_frame); //move to recvframme_defrag function
++
++_func_exit_;
++
++ return return_packet;
++
++}
++//###set the security information in the recv_frame
++union recv_frame * portctrl(_adapter *adapter,union recv_frame * precv_frame);
++union recv_frame * portctrl(_adapter *adapter,union recv_frame * precv_frame)
++{
++ u8 *psta_addr,*ptr;
++ uint auth_alg;
++ struct recv_frame_hdr *pfhdr;
++ struct sta_info * psta;
++ struct sta_priv *pstapriv ;
++ union recv_frame * prtnframe;
++ u16 ether_type=0;
++ u16 eapol_type = 0x888e;//for Funia BD's WPA issue
++ struct rx_pkt_attrib *pattrib = & precv_frame->u.hdr.attrib;
++
++_func_enter_;
++
++ pstapriv = &adapter->stapriv;
++ ptr = get_recvframe_data(precv_frame);
++ pfhdr = &precv_frame->u.hdr;
++ psta_addr = pfhdr->attrib.ta;
++ psta = rtw_get_stainfo(pstapriv, psta_addr);
++
++ auth_alg = adapter->securitypriv.dot11AuthAlgrthm;
++
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("########portctrl:adapter->securitypriv.dot11AuthAlgrthm= 0x%d\n",adapter->securitypriv.dot11AuthAlgrthm));
++
++ if(auth_alg==2)
++ {
++ if ((psta!=NULL) && (psta->ieee8021x_blocked))
++ {
++ //blocked
++ //only accept EAPOL frame
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("########portctrl:psta->ieee8021x_blocked==1\n"));
++
++ prtnframe=precv_frame;
++
++ //get ether_type
++ ptr=ptr+pfhdr->attrib.hdrlen+pfhdr->attrib.iv_len+LLC_HEADER_SIZE;
++ _rtw_memcpy(&ether_type,ptr, 2);
++ ether_type= ntohs((unsigned short )ether_type);
++
++ if (ether_type == eapol_type) {
++ prtnframe=precv_frame;
++ }
++ else {
++ //free this frame
++ rtw_free_recvframe(precv_frame, &adapter->recvpriv.free_recv_queue);
++ prtnframe=NULL;
++ }
++ }
++ else
++ {
++ //allowed
++ //check decryption status, and decrypt the frame if needed
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("########portctrl:psta->ieee8021x_blocked==0\n"));
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("portctrl:precv_frame->hdr.attrib.privacy=%x\n",precv_frame->u.hdr.attrib.privacy));
++
++ if(pattrib->bdecrypted==0)
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("portctrl:prxstat->decrypted=%x\n", pattrib->bdecrypted));
++
++ prtnframe=precv_frame;
++ //check is the EAPOL frame or not (Rekey)
++ if(ether_type == eapol_type){
++
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("########portctrl:ether_type == 0x888e\n"));
++ //check Rekey
++
++ prtnframe=precv_frame;
++ }
++ else{
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("########portctrl:ether_type = 0x%.4x\n",ether_type));
++ }
++ }
++ }
++ else
++ {
++ prtnframe=precv_frame;
++ }
++
++_func_exit_;
++
++ return prtnframe;
++
++}
++
++sint recv_decache(union recv_frame *precv_frame, u8 bretry, struct stainfo_rxcache *prxcache);
++sint recv_decache(union recv_frame *precv_frame, u8 bretry, struct stainfo_rxcache *prxcache)
++{
++ sint tid = precv_frame->u.hdr.attrib.priority;
++
++ u16 seq_ctrl = ( (precv_frame->u.hdr.attrib.seq_num&0xffff) << 4) |
++ (precv_frame->u.hdr.attrib.frag_num & 0xf);
++
++_func_enter_;
++
++ if(tid>15)
++ {
++ RT_TRACE(_module_rtl871x_recv_c_, _drv_notice_, ("recv_decache, (tid>15)! seq_ctrl=0x%x, tid=0x%x\n", seq_ctrl, tid));
++
++ return _FAIL;
++ }
++
++ if(1)//if(bretry)
++ {
++ if(seq_ctrl == prxcache->tid_rxseq[tid])
++ {
++ RT_TRACE(_module_rtl871x_recv_c_, _drv_notice_, ("recv_decache, seq_ctrl=0x%x, tid=0x%x, tid_rxseq=0x%x\n", seq_ctrl, tid, prxcache->tid_rxseq[tid]));
++
++ return _FAIL;
++ }
++ }
++
++ prxcache->tid_rxseq[tid] = seq_ctrl;
++
++_func_exit_;
++
++ return _SUCCESS;
++
++}
++
++void process_pwrbit_data(_adapter *padapter, union recv_frame *precv_frame);
++void process_pwrbit_data(_adapter *padapter, union recv_frame *precv_frame)
++{
++#ifdef CONFIG_AP_MODE
++ unsigned char pwrbit;
++ u8 *ptr = precv_frame->u.hdr.rx_data;
++ struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;
++ struct sta_priv *pstapriv = &padapter->stapriv;
++ struct sta_info *psta=NULL;
++
++ psta = rtw_get_stainfo(pstapriv, pattrib->src);
++
++ pwrbit = GetPwrMgt(ptr);
++
++ if(psta)
++ {
++ if(pwrbit)
++ {
++ if(!(psta->state & WIFI_SLEEP_STATE))
++ {
++ //psta->state |= WIFI_SLEEP_STATE;
++ //pstapriv->sta_dz_bitmap |= BIT(psta->aid);
++
++ stop_sta_xmit(padapter, psta);
++
++ //DBG_871X("to sleep, sta_dz_bitmap=%x\n", pstapriv->sta_dz_bitmap);
++ }
++ }
++ else
++ {
++ if(psta->state & WIFI_SLEEP_STATE)
++ {
++ //psta->state ^= WIFI_SLEEP_STATE;
++ //pstapriv->sta_dz_bitmap &= ~BIT(psta->aid);
++
++ wakeup_sta_to_xmit(padapter, psta);
++
++ //DBG_871X("to wakeup, sta_dz_bitmap=%x\n", pstapriv->sta_dz_bitmap);
++ }
++ }
++
++ }
++
++#endif
++}
++
++void process_wmmps_data(_adapter *padapter, union recv_frame *precv_frame);
++void process_wmmps_data(_adapter *padapter, union recv_frame *precv_frame)
++{
++#ifdef CONFIG_AP_MODE
++ struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;
++ struct sta_priv *pstapriv = &padapter->stapriv;
++ struct sta_info *psta=NULL;
++
++ psta = rtw_get_stainfo(pstapriv, pattrib->src);
++
++ if(!psta) return;
++
++#ifdef CONFIG_TDLS
++ if( !(psta->tdls_sta_state & TDLS_LINKED_STATE ) )
++ {
++#endif //CONFIG_TDLS
++
++ if(!psta->qos_option)
++ return;
++
++ if(!(psta->qos_info&0xf))
++ return;
++
++#ifdef CONFIG_TDLS
++ }
++#endif //CONFIG_TDLS
++
++ if(psta->state&WIFI_SLEEP_STATE)
++ {
++ u8 wmmps_ac=0;
++
++ switch(pattrib->priority)
++ {
++ case 1:
++ case 2:
++ wmmps_ac = psta->uapsd_bk&BIT(1);
++ break;
++ case 4:
++ case 5:
++ wmmps_ac = psta->uapsd_vi&BIT(1);
++ break;
++ case 6:
++ case 7:
++ wmmps_ac = psta->uapsd_vo&BIT(1);
++ break;
++ case 0:
++ case 3:
++ default:
++ wmmps_ac = psta->uapsd_be&BIT(1);
++ break;
++ }
++
++ if(wmmps_ac)
++ {
++ if(psta->sleepq_ac_len>0)
++ {
++ //process received triggered frame
++ xmit_delivery_enabled_frames(padapter, psta);
++ }
++ else
++ {
++ //issue one qos null frame with More data bit = 0 and the EOSP bit set (=1)
++ issue_qos_nulldata(padapter, psta->hwaddr, (u16)pattrib->priority, 0, 0);
++ }
++ }
++
++ }
++
++
++#endif
++
++}
++
++#ifdef CONFIG_TDLS
++sint OnTDLS(_adapter *adapter, union recv_frame *precv_frame)
++{
++ struct rx_pkt_attrib *pattrib = & precv_frame->u.hdr.attrib;
++ sint ret = _SUCCESS;
++ u8 *paction = get_recvframe_data(precv_frame);
++ u8 category_field = 1;
++#ifdef CONFIG_WFD
++ u8 WFA_OUI[3] = { 0x50, 0x6f, 0x9a };
++#endif //CONFIG_WFD
++ struct tdls_info *ptdlsinfo = &(adapter->tdlsinfo);
++
++ //point to action field
++ paction+=pattrib->hdrlen
++ + pattrib->iv_len
++ + SNAP_SIZE
++ + ETH_TYPE_LEN
++ + PAYLOAD_TYPE_LEN
++ + category_field;
++
++ if(ptdlsinfo->enable == 0)
++ {
++ DBG_871X("recv tdls frame, "
++ "but tdls haven't enabled\n");
++ ret = _FAIL;
++ return ret;
++ }
++
++ switch(*paction){
++ case TDLS_SETUP_REQUEST:
++ DBG_871X("recv tdls setup request frame\n");
++ ret=On_TDLS_Setup_Req(adapter, precv_frame);
++ break;
++ case TDLS_SETUP_RESPONSE:
++ DBG_871X("recv tdls setup response frame\n");
++ ret=On_TDLS_Setup_Rsp(adapter, precv_frame);
++ break;
++ case TDLS_SETUP_CONFIRM:
++ DBG_871X("recv tdls setup confirm frame\n");
++ ret=On_TDLS_Setup_Cfm(adapter, precv_frame);
++ break;
++ case TDLS_TEARDOWN:
++ DBG_871X("recv tdls teardown, free sta_info\n");
++ ret=On_TDLS_Teardown(adapter, precv_frame);
++ break;
++ case TDLS_DISCOVERY_REQUEST:
++ DBG_871X("recv tdls discovery request frame\n");
++ ret=On_TDLS_Dis_Req(adapter, precv_frame);
++ break;
++ case TDLS_PEER_TRAFFIC_RESPONSE:
++ DBG_871X("recv tdls peer traffic response frame\n");
++ ret=On_TDLS_Peer_Traffic_Rsp(adapter, precv_frame);
++ break;
++ case TDLS_CHANNEL_SWITCH_REQUEST:
++ DBG_871X("recv tdls channel switch request frame\n");
++ ret=On_TDLS_Ch_Switch_Req(adapter, precv_frame);
++ break;
++ case TDLS_CHANNEL_SWITCH_RESPONSE:
++ DBG_871X("recv tdls channel switch response frame\n");
++ ret=On_TDLS_Ch_Switch_Rsp(adapter, precv_frame);
++ break;
++#ifdef CONFIG_WFD
++ case 0x50: //First byte of WFA OUI
++ if( _rtw_memcmp(WFA_OUI, (paction), 3) )
++ {
++ if( *(paction + 3) == 0x04) //Probe request frame
++ {
++ //WFDTDLS: for sigma test, do not setup direct link automatically
++ ptdlsinfo->dev_discovered = 1;
++ DBG_871X("recv tunneled probe request frame\n");
++ issue_tunneled_probe_rsp(adapter, precv_frame);
++ }
++ if( *(paction + 3) == 0x05) //Probe response frame
++ {
++ //WFDTDLS: for sigma test, do not setup direct link automatically
++ ptdlsinfo->dev_discovered = 1;
++ DBG_871X("recv tunneled probe response frame\n");
++ }
++ }
++ break;
++#endif //CONFIG_WFD
++ default:
++ DBG_871X("receive TDLS frame but not supported\n");
++ ret=_FAIL;
++ break;
++ }
++
++exit:
++ return ret;
++
++}
++#endif //CONFIG_TDLS
++
++void count_rx_stats(_adapter *padapter, union recv_frame *prframe, struct sta_info*sta);
++void count_rx_stats(_adapter *padapter, union recv_frame *prframe, struct sta_info*sta)
++{
++ int sz;
++ struct sta_info *psta = NULL;
++ struct stainfo_stats *pstats = NULL;
++ struct rx_pkt_attrib *pattrib = & prframe->u.hdr.attrib;
++ struct recv_priv *precvpriv = &padapter->recvpriv;
++
++ sz = get_recvframe_len(prframe);
++ precvpriv->rx_bytes += sz;
++
++ padapter->mlmepriv.LinkDetectInfo.NumRxOkInPeriod++;
++
++ if( (!MacAddr_isBcst(pattrib->dst)) && (!IS_MCAST(pattrib->dst))){
++ padapter->mlmepriv.LinkDetectInfo.NumRxUnicastOkInPeriod++;
++ }
++
++ if(sta)
++ psta = sta;
++ else
++ psta = prframe->u.hdr.psta;
++
++ if(psta)
++ {
++ pstats = &psta->sta_stats;
++
++ pstats->rx_data_pkts++;
++ pstats->rx_bytes += sz;
++ }
++
++}
++
++sint sta2sta_data_frame(
++ _adapter *adapter,
++ union recv_frame *precv_frame,
++ struct sta_info**psta
++);
++sint sta2sta_data_frame(
++ _adapter *adapter,
++ union recv_frame *precv_frame,
++ struct sta_info**psta
++)
++{
++ u8 *ptr = precv_frame->u.hdr.rx_data;
++ sint ret = _SUCCESS;
++ struct rx_pkt_attrib *pattrib = & precv_frame->u.hdr.attrib;
++ struct sta_priv *pstapriv = &adapter->stapriv;
++ struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
++ u8 *mybssid = get_bssid(pmlmepriv);
++ u8 *myhwaddr = myid(&adapter->eeprompriv);
++ u8 * sta_addr = NULL;
++ sint bmcast = IS_MCAST(pattrib->dst);
++
++#ifdef CONFIG_TDLS
++ struct tdls_info *ptdlsinfo = &adapter->tdlsinfo;
++ struct sta_info *ptdls_sta=NULL;
++ u8 *psnap_type=ptr+pattrib->hdrlen + pattrib->iv_len+SNAP_SIZE;
++ u8 *pframe_body = psnap_type + ETH_TYPE_LEN + PAYLOAD_TYPE_LEN;
++#endif //CONFIG_TDLS
++
++_func_enter_;
++
++ if ((check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) ||
++ (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE))
++ {
++
++ // filter packets that SA is myself or multicast or broadcast
++ if (_rtw_memcmp(myhwaddr, pattrib->src, ETH_ALEN)){
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,(" SA==myself \n"));
++ ret= _FAIL;
++ goto exit;
++ }
++
++ if( (!_rtw_memcmp(myhwaddr, pattrib->dst, ETH_ALEN)) && (!bmcast) ){
++ ret= _FAIL;
++ goto exit;
++ }
++
++ if( _rtw_memcmp(pattrib->bssid, "\x0\x0\x0\x0\x0\x0", ETH_ALEN) ||
++ _rtw_memcmp(mybssid, "\x0\x0\x0\x0\x0\x0", ETH_ALEN) ||
++ (!_rtw_memcmp(pattrib->bssid, mybssid, ETH_ALEN)) ) {
++ ret= _FAIL;
++ goto exit;
++ }
++
++ sta_addr = pattrib->src;
++
++ }
++ else if(check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)
++ {
++#ifdef CONFIG_TDLS
++ //direct link data transfer
++ if(ptdlsinfo->setup_state == TDLS_LINKED_STATE){
++ ptdls_sta = rtw_get_stainfo(pstapriv, pattrib->src);
++ if(ptdls_sta==NULL)
++ {
++ ret=_FAIL;
++ goto exit;
++ }
++ else if(ptdls_sta->tdls_sta_state&TDLS_LINKED_STATE)
++ {
++ //drop QoS-SubType Data, including QoS NULL, excluding QoS-Data
++ if( (GetFrameSubType(ptr) & WIFI_QOS_DATA_TYPE )== WIFI_QOS_DATA_TYPE)
++ {
++ if(GetFrameSubType(ptr)&(BIT(4)|BIT(5)|BIT(6)))
++ {
++ DBG_871X("drop QoS-Sybtype Data\n");
++ ret= _FAIL;
++ goto exit;
++ }
++ }
++ // filter packets that SA is myself or multicast or broadcast
++ if (_rtw_memcmp(myhwaddr, pattrib->src, ETH_ALEN)){
++ ret= _FAIL;
++ goto exit;
++ }
++ // da should be for me
++ if((!_rtw_memcmp(myhwaddr, pattrib->dst, ETH_ALEN))&& (!bmcast))
++ {
++ ret= _FAIL;
++ goto exit;
++ }
++ // check BSSID
++ if( _rtw_memcmp(pattrib->bssid, "\x0\x0\x0\x0\x0\x0", ETH_ALEN) ||
++ _rtw_memcmp(mybssid, "\x0\x0\x0\x0\x0\x0", ETH_ALEN) ||
++ (!_rtw_memcmp(pattrib->bssid, mybssid, ETH_ALEN)) )
++ {
++ ret= _FAIL;
++ goto exit;
++ }
++
++ //process UAPSD tdls sta
++ process_pwrbit_data(adapter, precv_frame);
++
++ // if NULL-frame, check pwrbit
++ if ((GetFrameSubType(ptr)) == WIFI_DATA_NULL)
++ {
++ //NULL-frame with pwrbit=1, buffer_STA should buffer frames for sleep_STA
++ if(GetPwrMgt(ptr))
++ {
++ DBG_871X("TDLS: recv peer null frame with pwr bit 1\n");
++ ptdls_sta->tdls_sta_state|=TDLS_PEER_SLEEP_STATE;
++ }
++ // it would be triggered when we are off channel and receiving NULL DATA
++ // we can confirm that peer STA is at off channel
++ else if(ptdls_sta->tdls_sta_state&TDLS_CH_SWITCH_ON_STATE)
++ {
++ if((ptdls_sta->tdls_sta_state & TDLS_PEER_AT_OFF_STATE) != TDLS_PEER_AT_OFF_STATE)
++ {
++ issue_nulldata_to_TDLS_peer_STA(adapter, ptdls_sta, 0);
++ ptdls_sta->tdls_sta_state |= TDLS_PEER_AT_OFF_STATE;
++ On_TDLS_Peer_Traffic_Rsp(adapter, precv_frame);
++ }
++ }
++
++ ret= _FAIL;
++ goto exit;
++ }
++ //receive some of all TDLS management frames, process it at ON_TDLS
++ if((_rtw_memcmp(psnap_type, SNAP_ETH_TYPE_TDLS, 2))){
++ ret= OnTDLS(adapter, precv_frame);
++ goto exit;
++ }
++
++ }
++
++ sta_addr = pattrib->src;
++
++ }
++ else
++#endif //CONFIG_TDLS
++ {
++ // For Station mode, sa and bssid should always be BSSID, and DA is my mac-address
++ if(!_rtw_memcmp(pattrib->bssid, pattrib->src, ETH_ALEN) )
++ {
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("bssid != TA under STATION_MODE; drop pkt\n"));
++ ret= _FAIL;
++ goto exit;
++ }
++
++ sta_addr = pattrib->bssid;
++ }
++ }
++ else if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE)
++ {
++ if (bmcast)
++ {
++ // For AP mode, if DA == MCAST, then BSSID should be also MCAST
++ if (!IS_MCAST(pattrib->bssid)){
++ ret= _FAIL;
++ goto exit;
++ }
++ }
++ else // not mc-frame
++ {
++ // For AP mode, if DA is non-MCAST, then it must be BSSID, and bssid == BSSID
++ if(!_rtw_memcmp(pattrib->bssid, pattrib->dst, ETH_ALEN)) {
++ ret= _FAIL;
++ goto exit;
++ }
++
++ sta_addr = pattrib->src;
++ }
++
++ }
++ else if(check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE)
++ {
++ _rtw_memcpy(pattrib->dst, GetAddr1Ptr(ptr), ETH_ALEN);
++ _rtw_memcpy(pattrib->src, GetAddr2Ptr(ptr), ETH_ALEN);
++ _rtw_memcpy(pattrib->bssid, GetAddr3Ptr(ptr), ETH_ALEN);
++ _rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN);
++ _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
++
++ sta_addr = mybssid;
++ }
++ else
++ {
++ ret = _FAIL;
++ }
++
++
++
++ if(bmcast)
++ *psta = rtw_get_bcmc_stainfo(adapter);
++ else
++ *psta = rtw_get_stainfo(pstapriv, sta_addr); // get ap_info
++
++#ifdef CONFIG_TDLS
++ if(ptdls_sta != NULL)
++ *psta = ptdls_sta;
++#endif //CONFIG_TDLS
++
++
++ if (*psta == NULL) {
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("can't get psta under sta2sta_data_frame ; drop pkt\n"));
++#ifdef CONFIG_MP_INCLUDED
++ if(check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE)
++ adapter->mppriv.rx_pktloss++;
++#endif
++ ret= _FAIL;
++ goto exit;
++ }
++
++exit:
++_func_exit_;
++ return ret;
++
++}
++
++sint ap2sta_data_frame(
++ _adapter *adapter,
++ union recv_frame *precv_frame,
++ struct sta_info**psta );
++sint ap2sta_data_frame(
++ _adapter *adapter,
++ union recv_frame *precv_frame,
++ struct sta_info**psta )
++{
++ u8 *ptr = precv_frame->u.hdr.rx_data;
++ struct rx_pkt_attrib *pattrib = & precv_frame->u.hdr.attrib;
++ sint ret = _SUCCESS;
++ struct sta_priv *pstapriv = &adapter->stapriv;
++ struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
++ u8 *mybssid = get_bssid(pmlmepriv);
++ u8 *myhwaddr = myid(&adapter->eeprompriv);
++ sint bmcast = IS_MCAST(pattrib->dst);
++
++_func_enter_;
++
++ if ((check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)
++ && (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE
++ || check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == _TRUE )
++ )
++ {
++
++ // filter packets that SA is myself or multicast or broadcast
++ if (_rtw_memcmp(myhwaddr, pattrib->src, ETH_ALEN)){
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,(" SA==myself \n"));
++ #ifdef DBG_RX_DROP_FRAME
++ DBG_871X("DBG_RX_DROP_FRAME %s SA=%x:%x:%x:%x:%x:%x, myhwaddr= %x:%x:%x:%x:%x:%x\n", __FUNCTION__,
++ pattrib->src[0], pattrib->src[1], pattrib->src[2],
++ pattrib->src[3], pattrib->src[4], pattrib->src[5],
++ *(myhwaddr), *(myhwaddr+1), *(myhwaddr+2),
++ *(myhwaddr+3), *(myhwaddr+4), *(myhwaddr+5));
++ #endif
++ ret= _FAIL;
++ goto exit;
++ }
++
++ // da should be for me
++ if((!_rtw_memcmp(myhwaddr, pattrib->dst, ETH_ALEN))&& (!bmcast))
++ {
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,
++ (" ap2sta_data_frame: compare DA fail; DA="MAC_FMT"\n", MAC_ARG(pattrib->dst)));
++ #ifdef DBG_RX_DROP_FRAME
++ DBG_871X("DBG_RX_DROP_FRAME %s DA="MAC_FMT"\n", __func__, MAC_ARG(pattrib->dst));
++ #endif
++ ret= _FAIL;
++ goto exit;
++ }
++
++
++ // check BSSID
++ if( _rtw_memcmp(pattrib->bssid, "\x0\x0\x0\x0\x0\x0", ETH_ALEN) ||
++ _rtw_memcmp(mybssid, "\x0\x0\x0\x0\x0\x0", ETH_ALEN) ||
++ (!_rtw_memcmp(pattrib->bssid, mybssid, ETH_ALEN)) )
++ {
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,
++ (" ap2sta_data_frame: compare BSSID fail ; BSSID="MAC_FMT"\n", MAC_ARG(pattrib->bssid)));
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("mybssid="MAC_FMT"\n", MAC_ARG(mybssid)));
++ #ifdef DBG_RX_DROP_FRAME
++ DBG_871X("DBG_RX_DROP_FRAME %s BSSID="MAC_FMT", mybssid="MAC_FMT"\n",
++ __FUNCTION__, MAC_ARG(pattrib->bssid), MAC_ARG(mybssid));
++ DBG_871X( "this adapter = %d, buddy adapter = %d\n", adapter->adapter_type, adapter->pbuddy_adapter->adapter_type );
++ #endif
++
++ if(!bmcast)
++ {
++ DBG_871X("issue_deauth to the nonassociated ap=" MAC_FMT " for the reason(7)\n", MAC_ARG(pattrib->bssid));
++ issue_deauth(adapter, pattrib->bssid, WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA);
++ }
++
++ ret= _FAIL;
++ goto exit;
++ }
++
++ if(bmcast)
++ *psta = rtw_get_bcmc_stainfo(adapter);
++ else
++ *psta = rtw_get_stainfo(pstapriv, pattrib->bssid); // get ap_info
++
++ if (*psta == NULL) {
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("ap2sta: can't get psta under STATION_MODE ; drop pkt\n"));
++ #ifdef DBG_RX_DROP_FRAME
++ DBG_871X("DBG_RX_DROP_FRAME %s can't get psta under STATION_MODE ; drop pkt\n", __FUNCTION__);
++ #endif
++ ret= _FAIL;
++ goto exit;
++ }
++
++ if ((GetFrameSubType(ptr) & WIFI_QOS_DATA_TYPE) == WIFI_QOS_DATA_TYPE) {
++ }
++
++ if (GetFrameSubType(ptr) & BIT(6)) {
++ /* No data, will not indicate to upper layer, temporily count it here */
++ count_rx_stats(adapter, precv_frame, *psta);
++ ret = RTW_RX_HANDLED;
++ goto exit;
++ }
++
++ }
++ else if ((check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE) &&
++ (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) )
++ {
++ _rtw_memcpy(pattrib->dst, GetAddr1Ptr(ptr), ETH_ALEN);
++ _rtw_memcpy(pattrib->src, GetAddr2Ptr(ptr), ETH_ALEN);
++ _rtw_memcpy(pattrib->bssid, GetAddr3Ptr(ptr), ETH_ALEN);
++ _rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN);
++ _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
++
++ //
++ _rtw_memcpy(pattrib->bssid, mybssid, ETH_ALEN);
++
++
++ *psta = rtw_get_stainfo(pstapriv, pattrib->bssid); // get sta_info
++ if (*psta == NULL) {
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("can't get psta under MP_MODE ; drop pkt\n"));
++ #ifdef DBG_RX_DROP_FRAME
++ DBG_871X("DBG_RX_DROP_FRAME %s can't get psta under WIFI_MP_STATE ; drop pkt\n", __FUNCTION__);
++ #endif
++ ret= _FAIL;
++ goto exit;
++ }
++
++
++ }
++ else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE)
++ {
++ /* Special case */
++ ret = RTW_RX_HANDLED;
++ goto exit;
++ }
++ else
++ {
++ if(_rtw_memcmp(myhwaddr, pattrib->dst, ETH_ALEN)&& (!bmcast))
++ {
++ *psta = rtw_get_stainfo(pstapriv, pattrib->bssid); // get sta_info
++ if (*psta == NULL)
++ {
++ DBG_871X("issue_deauth to the ap=" MAC_FMT " for the reason(7)\n", MAC_ARG(pattrib->bssid));
++
++ issue_deauth(adapter, pattrib->bssid, WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA);
++ }
++ }
++
++ ret = _FAIL;
++ #ifdef DBG_RX_DROP_FRAME
++ DBG_871X("DBG_RX_DROP_FRAME %s fw_state:0x%x\n", __FUNCTION__, get_fwstate(pmlmepriv));
++ #endif
++ }
++
++exit:
++
++_func_exit_;
++
++ return ret;
++
++}
++
++sint sta2ap_data_frame(
++ _adapter *adapter,
++ union recv_frame *precv_frame,
++ struct sta_info**psta );
++sint sta2ap_data_frame(
++ _adapter *adapter,
++ union recv_frame *precv_frame,
++ struct sta_info**psta )
++{
++ u8 *ptr = precv_frame->u.hdr.rx_data;
++ struct rx_pkt_attrib *pattrib = & precv_frame->u.hdr.attrib;
++ struct sta_priv *pstapriv = &adapter->stapriv;
++ struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
++ unsigned char *mybssid = get_bssid(pmlmepriv);
++ sint ret=_SUCCESS;
++
++_func_enter_;
++
++ if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE)
++ {
++ //For AP mode, RA=BSSID, TX=STA(SRC_ADDR), A3=DST_ADDR
++ if(!_rtw_memcmp(pattrib->bssid, mybssid, ETH_ALEN))
++ {
++ ret= _FAIL;
++ goto exit;
++ }
++
++ *psta = rtw_get_stainfo(pstapriv, pattrib->src);
++ if (*psta == NULL)
++ {
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("can't get psta under AP_MODE; drop pkt\n"));
++ DBG_871X("issue_deauth to sta=" MAC_FMT " for the reason(7)\n", MAC_ARG(pattrib->src));
++
++ issue_deauth(adapter, pattrib->src, WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA);
++
++ ret = RTW_RX_HANDLED;
++ goto exit;
++ }
++
++ process_pwrbit_data(adapter, precv_frame);
++
++ if ((GetFrameSubType(ptr) & WIFI_QOS_DATA_TYPE) == WIFI_QOS_DATA_TYPE) {
++ process_wmmps_data(adapter, precv_frame);
++ }
++
++ if (GetFrameSubType(ptr) & BIT(6)) {
++ /* No data, will not indicate to upper layer, temporily count it here */
++ count_rx_stats(adapter, precv_frame, *psta);
++ ret = RTW_RX_HANDLED;
++ goto exit;
++ }
++ }
++ else {
++ u8 *myhwaddr = myid(&adapter->eeprompriv);
++ if (!_rtw_memcmp(pattrib->ra, myhwaddr, ETH_ALEN)) {
++ ret = RTW_RX_HANDLED;
++ goto exit;
++ }
++ DBG_871X("issue_deauth to sta=" MAC_FMT " for the reason(7)\n", MAC_ARG(pattrib->src));
++ issue_deauth(adapter, pattrib->src, WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA);
++ ret = RTW_RX_HANDLED;
++ goto exit;
++ }
++
++exit:
++
++_func_exit_;
++
++ return ret;
++
++}
++
++sint validate_recv_ctrl_frame(_adapter *padapter, union recv_frame *precv_frame);
++sint validate_recv_ctrl_frame(_adapter *padapter, union recv_frame *precv_frame)
++{
++#ifdef CONFIG_AP_MODE
++ struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;
++ struct sta_priv *pstapriv = &padapter->stapriv;
++ u8 *pframe = precv_frame->u.hdr.rx_data;
++ //uint len = precv_frame->u.hdr.len;
++
++ //DBG_871X("+validate_recv_ctrl_frame\n");
++
++ if (GetFrameType(pframe) != WIFI_CTRL_TYPE)
++ {
++ return _FAIL;
++ }
++
++ //receive the frames that ra(a1) is my address
++ if (!_rtw_memcmp(GetAddr1Ptr(pframe), myid(&padapter->eeprompriv), ETH_ALEN))
++ {
++ return _FAIL;
++ }
++
++ //only handle ps-poll
++ if(GetFrameSubType(pframe) == WIFI_PSPOLL)
++ {
++ u16 aid;
++ u8 wmmps_ac=0;
++ struct sta_info *psta=NULL;
++
++ aid = GetAid(pframe);
++ psta = rtw_get_stainfo(pstapriv, GetAddr2Ptr(pframe));
++
++ if((psta==NULL) || (psta->aid!=aid))
++ {
++ return _FAIL;
++ }
++
++ //for rx pkt statistics
++ psta->sta_stats.rx_ctrl_pkts++;
++
++ switch(pattrib->priority)
++ {
++ case 1:
++ case 2:
++ wmmps_ac = psta->uapsd_bk&BIT(0);
++ break;
++ case 4:
++ case 5:
++ wmmps_ac = psta->uapsd_vi&BIT(0);
++ break;
++ case 6:
++ case 7:
++ wmmps_ac = psta->uapsd_vo&BIT(0);
++ break;
++ case 0:
++ case 3:
++ default:
++ wmmps_ac = psta->uapsd_be&BIT(0);
++ break;
++ }
++
++ if(wmmps_ac)
++ return _FAIL;
++
++ if(psta->state & WIFI_STA_ALIVE_CHK_STATE)
++ {
++ DBG_871X("%s alive check-rx ps-poll\n", __func__);
++ psta->expire_to = pstapriv->expire_to;
++ psta->state ^= WIFI_STA_ALIVE_CHK_STATE;
++ }
++
++ if((psta->state&WIFI_SLEEP_STATE) && (pstapriv->sta_dz_bitmap&BIT(psta->aid)))
++ {
++ _irqL irqL;
++ _list *xmitframe_plist, *xmitframe_phead;
++ struct xmit_frame *pxmitframe=NULL;
++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++
++ //_enter_critical_bh(&psta->sleep_q.lock, &irqL);
++ _enter_critical_bh(&pxmitpriv->lock, &irqL);
++
++ xmitframe_phead = get_list_head(&psta->sleep_q);
++ xmitframe_plist = get_next(xmitframe_phead);
++
++ if ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE)
++ {
++ pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list);
++
++ xmitframe_plist = get_next(xmitframe_plist);
++
++ rtw_list_delete(&pxmitframe->list);
++
++ psta->sleepq_len--;
++
++ if(psta->sleepq_len>0)
++ pxmitframe->attrib.mdata = 1;
++ else
++ pxmitframe->attrib.mdata = 0;
++
++ pxmitframe->attrib.triggered = 1;
++
++ //DBG_871X("handling ps-poll, q_len=%d, tim=%x\n", psta->sleepq_len, pstapriv->tim_bitmap);
++
++#if 0
++ _exit_critical_bh(&psta->sleep_q.lock, &irqL);
++ if(rtw_hal_xmit(padapter, pxmitframe) == _TRUE)
++ {
++ rtw_os_xmit_complete(padapter, pxmitframe);
++ }
++ _enter_critical_bh(&psta->sleep_q.lock, &irqL);
++#endif
++ rtw_hal_xmitframe_enqueue(padapter, pxmitframe);
++
++ if(psta->sleepq_len==0)
++ {
++ pstapriv->tim_bitmap &= ~BIT(psta->aid);
++
++ //DBG_871X("after handling ps-poll, tim=%x\n", pstapriv->tim_bitmap);
++
++ //upate BCN for TIM IE
++ //update_BCNTIM(padapter);
++ update_beacon(padapter, _TIM_IE_, NULL, _FALSE);
++ }
++
++ //_exit_critical_bh(&psta->sleep_q.lock, &irqL);
++ _exit_critical_bh(&pxmitpriv->lock, &irqL);
++
++ }
++ else
++ {
++ //_exit_critical_bh(&psta->sleep_q.lock, &irqL);
++ _exit_critical_bh(&pxmitpriv->lock, &irqL);
++
++ //DBG_871X("no buffered packets to xmit\n");
++ if(pstapriv->tim_bitmap&BIT(psta->aid))
++ {
++ if(psta->sleepq_len==0)
++ {
++ DBG_871X("no buffered packets to xmit\n");
++
++ //issue nulldata with More data bit = 0 to indicate we have no buffered packets
++ issue_nulldata(padapter, psta->hwaddr, 0, 0, 0);
++ }
++ else
++ {
++ DBG_871X("error!psta->sleepq_len=%d\n", psta->sleepq_len);
++ psta->sleepq_len=0;
++ }
++
++ pstapriv->tim_bitmap &= ~BIT(psta->aid);
++
++ //upate BCN for TIM IE
++ //update_BCNTIM(padapter);
++ update_beacon(padapter, _TIM_IE_, NULL, _FALSE);
++ }
++
++ }
++
++ }
++
++ }
++
++#endif
++
++ return _FAIL;
++
++}
++
++union recv_frame* recvframe_chk_defrag(PADAPTER padapter, union recv_frame *precv_frame);
++sint validate_recv_mgnt_frame(PADAPTER padapter, union recv_frame *precv_frame);
++sint validate_recv_mgnt_frame(PADAPTER padapter, union recv_frame *precv_frame)
++{
++ //struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
++
++ RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("+validate_recv_mgnt_frame\n"));
++
++#if 0
++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE)
++ {
++#ifdef CONFIG_NATIVEAP_MLME
++ mgt_dispatcher(padapter, precv_frame);
++#else
++ rtw_hostapd_mlme_rx(padapter, precv_frame);
++#endif
++ }
++ else
++ {
++ mgt_dispatcher(padapter, precv_frame);
++ }
++#endif
++
++ precv_frame = recvframe_chk_defrag(padapter, precv_frame);
++ if (precv_frame == NULL) {
++ RT_TRACE(_module_rtl871x_recv_c_, _drv_notice_,("%s: fragment packet\n",__FUNCTION__));
++ return _SUCCESS;
++ }
++
++ {
++ //for rx pkt statistics
++ struct sta_info *psta = rtw_get_stainfo(&padapter->stapriv, GetAddr2Ptr(precv_frame->u.hdr.rx_data));
++ if (psta) {
++ psta->sta_stats.rx_mgnt_pkts++;
++ if (GetFrameSubType(precv_frame->u.hdr.rx_data) == WIFI_BEACON)
++ psta->sta_stats.rx_beacon_pkts++;
++ else if (GetFrameSubType(precv_frame->u.hdr.rx_data) == WIFI_PROBEREQ)
++ psta->sta_stats.rx_probereq_pkts++;
++ else if (GetFrameSubType(precv_frame->u.hdr.rx_data) == WIFI_PROBERSP) {
++ if (_rtw_memcmp(padapter->eeprompriv.mac_addr, GetAddr1Ptr(precv_frame->u.hdr.rx_data), ETH_ALEN) == _TRUE)
++ psta->sta_stats.rx_probersp_pkts++;
++ else if (is_broadcast_mac_addr(GetAddr1Ptr(precv_frame->u.hdr.rx_data))
++ || is_multicast_mac_addr(GetAddr1Ptr(precv_frame->u.hdr.rx_data)))
++ psta->sta_stats.rx_probersp_bm_pkts++;
++ else
++ psta->sta_stats.rx_probersp_uo_pkts++;
++ }
++ }
++ }
++
++#ifdef CONFIG_INTEL_PROXIM
++ if(padapter->proximity.proxim_on==_TRUE)
++ {
++ struct rx_pkt_attrib * pattrib=&precv_frame->u.hdr.attrib;
++ struct recv_stat* prxstat=( struct recv_stat * ) precv_frame->u.hdr.rx_head ;
++ u8 * pda,*psa,*pbssid,*ptr;
++ ptr=precv_frame->u.hdr.rx_data;
++ pda = get_da(ptr);
++ psa = get_sa(ptr);
++ pbssid = get_hdr_bssid(ptr);
++
++
++ _rtw_memcpy(pattrib->dst, pda, ETH_ALEN);
++ _rtw_memcpy(pattrib->src, psa, ETH_ALEN);
++
++ _rtw_memcpy(pattrib->bssid, pbssid, ETH_ALEN);
++
++ switch(pattrib->to_fr_ds)
++ {
++ case 0:
++ _rtw_memcpy(pattrib->ra, pda, ETH_ALEN);
++ _rtw_memcpy(pattrib->ta, psa, ETH_ALEN);
++ break;
++
++ case 1:
++ _rtw_memcpy(pattrib->ra, pda, ETH_ALEN);
++ _rtw_memcpy(pattrib->ta, pbssid, ETH_ALEN);
++ break;
++
++ case 2:
++ _rtw_memcpy(pattrib->ra, pbssid, ETH_ALEN);
++ _rtw_memcpy(pattrib->ta, psa, ETH_ALEN);
++ break;
++
++ case 3:
++ _rtw_memcpy(pattrib->ra, GetAddr1Ptr(ptr), ETH_ALEN);
++ _rtw_memcpy(pattrib->ta, GetAddr2Ptr(ptr), ETH_ALEN);
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,(" case 3\n"));
++ break;
++
++ default:
++ break;
++
++ }
++ pattrib->priority=0;
++ pattrib->hdrlen = pattrib->to_fr_ds==3 ? 30 : 24;
++
++ padapter->proximity.proxim_rx(padapter,precv_frame);
++ }
++#endif
++ mgt_dispatcher(padapter, precv_frame);
++
++ return _SUCCESS;
++
++}
++
++sint validate_recv_data_frame(_adapter *adapter, union recv_frame *precv_frame);
++sint validate_recv_data_frame(_adapter *adapter, union recv_frame *precv_frame)
++{
++ u8 bretry;
++ u8 *psa, *pda, *pbssid;
++ struct sta_info *psta = NULL;
++ u8 *ptr = precv_frame->u.hdr.rx_data;
++ struct rx_pkt_attrib *pattrib = & precv_frame->u.hdr.attrib;
++ struct security_priv *psecuritypriv = &adapter->securitypriv;
++ sint ret = _SUCCESS;
++#ifdef CONFIG_TDLS
++ struct tdls_info *ptdlsinfo = &adapter->tdlsinfo;
++#endif //CONFIG_TDLS
++
++_func_enter_;
++
++ bretry = GetRetry(ptr);
++ pda = get_da(ptr);
++ psa = get_sa(ptr);
++ pbssid = get_hdr_bssid(ptr);
++
++ if(pbssid == NULL){
++ ret= _FAIL;
++ goto exit;
++ }
++
++ _rtw_memcpy(pattrib->dst, pda, ETH_ALEN);
++ _rtw_memcpy(pattrib->src, psa, ETH_ALEN);
++
++ _rtw_memcpy(pattrib->bssid, pbssid, ETH_ALEN);
++
++ switch(pattrib->to_fr_ds)
++ {
++ case 0:
++ _rtw_memcpy(pattrib->ra, pda, ETH_ALEN);
++ _rtw_memcpy(pattrib->ta, psa, ETH_ALEN);
++ ret = sta2sta_data_frame(adapter, precv_frame, &psta);
++ break;
++
++ case 1:
++ _rtw_memcpy(pattrib->ra, pda, ETH_ALEN);
++ _rtw_memcpy(pattrib->ta, pbssid, ETH_ALEN);
++ ret = ap2sta_data_frame(adapter, precv_frame, &psta);
++ break;
++
++ case 2:
++ _rtw_memcpy(pattrib->ra, pbssid, ETH_ALEN);
++ _rtw_memcpy(pattrib->ta, psa, ETH_ALEN);
++ ret = sta2ap_data_frame(adapter, precv_frame, &psta);
++ break;
++
++ case 3:
++ _rtw_memcpy(pattrib->ra, GetAddr1Ptr(ptr), ETH_ALEN);
++ _rtw_memcpy(pattrib->ta, GetAddr2Ptr(ptr), ETH_ALEN);
++ ret =_FAIL;
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,(" case 3\n"));
++ break;
++
++ default:
++ ret =_FAIL;
++ break;
++
++ }
++
++ if(ret ==_FAIL){
++ #ifdef DBG_RX_DROP_FRAME
++ DBG_871X("DBG_RX_DROP_FRAME %s case:%d, res:%d\n", __FUNCTION__, pattrib->to_fr_ds, ret);
++ #endif
++ goto exit;
++ } else if (ret == RTW_RX_HANDLED) {
++ goto exit;
++ }
++
++
++ if(psta==NULL){
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,(" after to_fr_ds_chk; psta==NULL \n"));
++ ret= _FAIL;
++ goto exit;
++ }
++
++ //psta->rssi = prxcmd->rssi;
++ //psta->signal_quality= prxcmd->sq;
++ precv_frame->u.hdr.psta = psta;
++
++
++ pattrib->amsdu=0;
++ pattrib->ack_policy = 0;
++ //parsing QC field
++ if(pattrib->qos == 1)
++ {
++ pattrib->priority = GetPriority((ptr + 24));
++ pattrib->ack_policy = GetAckpolicy((ptr + 24));
++ pattrib->amsdu = GetAMsdu((ptr + 24));
++ pattrib->hdrlen = pattrib->to_fr_ds==3 ? 32 : 26;
++
++ if(pattrib->priority!=0 && pattrib->priority!=3)
++ {
++ adapter->recvpriv.bIsAnyNonBEPkts = _TRUE;
++ }
++ }
++ else
++ {
++ pattrib->priority=0;
++ pattrib->hdrlen = pattrib->to_fr_ds==3 ? 30 : 24;
++ }
++
++
++ if(pattrib->order)//HT-CTRL 11n
++ {
++ pattrib->hdrlen += 4;
++ }
++
++ precv_frame->u.hdr.preorder_ctrl = &psta->recvreorder_ctrl[pattrib->priority];
++
++ // decache, drop duplicate recv packets
++ if(recv_decache(precv_frame, bretry, &psta->sta_recvpriv.rxcache) == _FAIL)
++ {
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("decache : drop pkt\n"));
++ ret= _FAIL;
++ goto exit;
++ }
++
++#if 0
++ if(psta->tdls_sta_state & TDLS_LINKED_STATE )
++ {
++ if(psta->dot118021XPrivacy==_AES_)
++ pattrib->encrypt=psta->dot118021XPrivacy;
++ }
++#endif //CONFIG_TDLS
++
++ if(pattrib->privacy){
++
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("validate_recv_data_frame:pattrib->privacy=%x\n", pattrib->privacy));
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("\n ^^^^^^^^^^^IS_MCAST(pattrib->ra(0x%02x))=%d^^^^^^^^^^^^^^^6\n", pattrib->ra[0],IS_MCAST(pattrib->ra)));
++
++#ifdef CONFIG_TDLS
++ if((psta->tdls_sta_state & TDLS_LINKED_STATE) && (psta->dot118021XPrivacy==_AES_))
++ {
++ pattrib->encrypt=psta->dot118021XPrivacy;
++ }
++ else
++#endif //CONFIG_TDLS
++ GET_ENCRY_ALGO(psecuritypriv, psta, pattrib->encrypt, IS_MCAST(pattrib->ra));
++
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("\n pattrib->encrypt=%d\n",pattrib->encrypt));
++
++ SET_ICE_IV_LEN(pattrib->iv_len, pattrib->icv_len, pattrib->encrypt);
++ }
++ else
++ {
++ pattrib->encrypt = 0;
++ pattrib->iv_len = pattrib->icv_len = 0;
++ }
++
++exit:
++
++_func_exit_;
++
++ return ret;
++}
++
++#ifdef CONFIG_IEEE80211W
++static sint validate_80211w_mgmt(_adapter *adapter, union recv_frame *precv_frame)
++{
++ struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
++ struct rx_pkt_attrib *pattrib = & precv_frame->u.hdr.attrib;
++ u8 *ptr = precv_frame->u.hdr.rx_data;
++ u8 type;
++ u8 subtype;
++
++ type = GetFrameType(ptr);
++ subtype = GetFrameSubType(ptr); //bit(7)~bit(2)
++
++ //only support station mode
++ if(check_fwstate(pmlmepriv, WIFI_STATION_STATE) && check_fwstate(pmlmepriv, _FW_LINKED)
++ && adapter->securitypriv.binstallBIPkey == _TRUE)
++ {
++ //unicast management frame decrypt
++ if(pattrib->privacy && !(IS_MCAST(GetAddr1Ptr(ptr))) &&
++ (subtype == WIFI_DEAUTH || subtype == WIFI_DISASSOC || subtype == WIFI_ACTION))
++ {
++ u8 *ppp, *mgmt_DATA;
++ u32 data_len=0;
++ ppp = GetAddr2Ptr(ptr);
++
++ pattrib->bdecrypted = 0;
++ pattrib->encrypt = _AES_;
++ pattrib->hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++ //set iv and icv length
++ SET_ICE_IV_LEN(pattrib->iv_len, pattrib->icv_len, pattrib->encrypt);
++ _rtw_memcpy(pattrib->ra, GetAddr1Ptr(ptr), ETH_ALEN);
++ _rtw_memcpy(pattrib->ta, GetAddr2Ptr(ptr), ETH_ALEN);
++ //actual management data frame body
++ data_len = pattrib->pkt_len - pattrib->hdrlen - pattrib->iv_len - pattrib->icv_len;
++ mgmt_DATA = rtw_zmalloc(data_len);
++ if(mgmt_DATA == NULL)
++ {
++ DBG_871X("%s mgmt allocate fail !!!!!!!!!\n", __FUNCTION__);
++ goto validate_80211w_fail;
++ }
++ /*//dump the packet content before decrypt
++ {
++ int pp;
++ printk("pattrib->pktlen = %d =>", pattrib->pkt_len);
++ for(pp=0;pp< pattrib->pkt_len; pp++)
++ printk(" %02x ", ptr[pp]);
++ printk("\n");
++ }*/
++
++ precv_frame = decryptor(adapter, precv_frame);
++ //save actual management data frame body
++ _rtw_memcpy(mgmt_DATA, ptr+pattrib->hdrlen+pattrib->iv_len, data_len);
++ //overwrite the iv field
++ _rtw_memcpy(ptr+pattrib->hdrlen, mgmt_DATA, data_len);
++ //remove the iv and icv length
++ pattrib->pkt_len = pattrib->pkt_len - pattrib->iv_len - pattrib->icv_len;
++ rtw_mfree(mgmt_DATA, data_len);
++ /*//print packet content after decryption
++ {
++ int pp;
++ printk("after decryption pattrib->pktlen = %d @@=>", pattrib->pkt_len);
++ for(pp=0;pp< pattrib->pkt_len; pp++)
++ printk(" %02x ", ptr[pp]);
++ printk("\n");
++ }*/
++ if(!precv_frame)
++ {
++ DBG_871X("%s mgmt descrypt fail !!!!!!!!!\n", __FUNCTION__);
++ goto validate_80211w_fail;
++ }
++ }
++ else if(IS_MCAST(GetAddr1Ptr(ptr)) &&
++ (subtype == WIFI_DEAUTH || subtype == WIFI_DISASSOC))
++ {
++ sint BIP_ret = _SUCCESS;
++ //verify BIP MME IE of broadcast/multicast de-auth/disassoc packet
++ BIP_ret = rtw_BIP_verify(adapter, (u8 * )precv_frame);
++ if(BIP_ret == _FAIL)
++ {
++ //DBG_871X("802.11w BIP verify fail\n");
++ goto validate_80211w_fail;
++ }
++ else if(BIP_ret == RTW_RX_HANDLED)
++ {
++ //DBG_871X("802.11w recv none protected packet\n");
++ //issue sa query request
++ issue_action_SA_Query(adapter, NULL, 0, 0);
++ goto validate_80211w_fail;
++ }
++ }//802.11w protect
++ else
++ {
++ if(subtype == WIFI_ACTION)
++ {
++ //according 802.11-2012 standard, these five types are not robust types
++ if( ptr[WLAN_HDR_A3_LEN] != RTW_WLAN_CATEGORY_PUBLIC &&
++ ptr[WLAN_HDR_A3_LEN] != RTW_WLAN_CATEGORY_HT &&
++ ptr[WLAN_HDR_A3_LEN] != RTW_WLAN_CATEGORY_UNPROTECTED_WNM &&
++ ptr[WLAN_HDR_A3_LEN] != RTW_WLAN_CATEGORY_SELF_PROTECTED &&
++ ptr[WLAN_HDR_A3_LEN] != RTW_WLAN_CATEGORY_P2P)
++ {
++ DBG_871X("action frame category=%d should robust\n", ptr[WLAN_HDR_A3_LEN]);
++ goto validate_80211w_fail;
++ }
++ }
++ else if(subtype == WIFI_DEAUTH || subtype == WIFI_DISASSOC)
++ {
++ DBG_871X("802.11w recv none protected packet\n");
++ //issue sa query request
++ issue_action_SA_Query(adapter, NULL, 0, 0);
++ goto validate_80211w_fail;
++ }
++ }
++ }
++ return _SUCCESS;
++
++validate_80211w_fail:
++ return _FAIL;
++
++}
++#endif //CONFIG_IEEE80211W
++
++sint validate_recv_frame(_adapter *adapter, union recv_frame *precv_frame);
++sint validate_recv_frame(_adapter *adapter, union recv_frame *precv_frame)
++{
++ //shall check frame subtype, to / from ds, da, bssid
++
++ //then call check if rx seq/frag. duplicated.
++
++ u8 type;
++ u8 subtype;
++ sint retval = _SUCCESS;
++
++ struct rx_pkt_attrib *pattrib = & precv_frame->u.hdr.attrib;
++
++ u8 *ptr = precv_frame->u.hdr.rx_data;
++ u8 ver =(unsigned char) (*ptr)&0x3 ;
++#ifdef CONFIG_FIND_BEST_CHANNEL
++ struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
++#endif
++
++#ifdef CONFIG_TDLS
++ struct tdls_info *ptdlsinfo = &adapter->tdlsinfo;
++#endif //CONFIG_TDLS
++
++_func_enter_;
++
++
++#ifdef CONFIG_FIND_BEST_CHANNEL
++ if (pmlmeext->sitesurvey_res.state == SCAN_PROCESS) {
++ int ch_set_idx = rtw_ch_set_search_ch(pmlmeext->channel_set, rtw_get_oper_ch(adapter));
++ if (ch_set_idx >= 0)
++ pmlmeext->channel_set[ch_set_idx].rx_count++;
++ }
++#endif
++
++#ifdef CONFIG_TDLS
++ if(ptdlsinfo->ch_sensing==1 && ptdlsinfo->cur_channel !=0){
++ ptdlsinfo->collect_pkt_num[ptdlsinfo->cur_channel-1]++;
++ }
++#endif //CONFIG_TDLS
++
++#ifdef RTK_DMP_PLATFORM
++ if ( 0 )
++ {
++ DBG_871X("++\n");
++ {
++ int i;
++ for(i=0; i<64;i=i+8)
++ DBG_871X("%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:", *(ptr+i),
++ *(ptr+i+1), *(ptr+i+2) ,*(ptr+i+3) ,*(ptr+i+4),*(ptr+i+5), *(ptr+i+6), *(ptr+i+7));
++
++ }
++ DBG_871X("--\n");
++ }
++#endif //RTK_DMP_PLATFORM
++
++ //add version chk
++ if(ver!=0){
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("validate_recv_data_frame fail! (ver!=0)\n"));
++ retval= _FAIL;
++ goto exit;
++ }
++
++ type = GetFrameType(ptr);
++ subtype = GetFrameSubType(ptr); //bit(7)~bit(2)
++
++ pattrib->to_fr_ds = get_tofr_ds(ptr);
++
++ pattrib->frag_num = GetFragNum(ptr);
++ pattrib->seq_num = GetSequence(ptr);
++
++ pattrib->pw_save = GetPwrMgt(ptr);
++ pattrib->mfrag = GetMFrag(ptr);
++ pattrib->mdata = GetMData(ptr);
++ pattrib->privacy = GetPrivacy(ptr);
++ pattrib->order = GetOrder(ptr);
++#if 0 //for debug
++
++if(pHalData->bDumpRxPkt ==1){
++ int i;
++ DBG_871X("############################# \n");
++
++ for(i=0; i<64;i=i+8)
++ DBG_871X("%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:\n", *(ptr+i),
++ *(ptr+i+1), *(ptr+i+2) ,*(ptr+i+3) ,*(ptr+i+4),*(ptr+i+5), *(ptr+i+6), *(ptr+i+7));
++ DBG_871X("############################# \n");
++}
++else if(pHalData->bDumpRxPkt ==2){
++ if(type== WIFI_MGT_TYPE){
++ int i;
++ DBG_871X("############################# \n");
++
++ for(i=0; i<64;i=i+8)
++ DBG_871X("%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:\n", *(ptr+i),
++ *(ptr+i+1), *(ptr+i+2) ,*(ptr+i+3) ,*(ptr+i+4),*(ptr+i+5), *(ptr+i+6), *(ptr+i+7));
++ DBG_871X("############################# \n");
++ }
++}
++else if(pHalData->bDumpRxPkt ==3){
++ if(type== WIFI_DATA_TYPE){
++ int i;
++ DBG_871X("############################# \n");
++
++ for(i=0; i<64;i=i+8)
++ DBG_871X("%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:\n", *(ptr+i),
++ *(ptr+i+1), *(ptr+i+2) ,*(ptr+i+3) ,*(ptr+i+4),*(ptr+i+5), *(ptr+i+6), *(ptr+i+7));
++ DBG_871X("############################# \n");
++ }
++}
++
++#endif
++ switch (type)
++ {
++ case WIFI_MGT_TYPE: //mgnt
++#ifdef CONFIG_IEEE80211W
++ if(validate_80211w_mgmt(adapter, precv_frame) == _FAIL)
++ {
++ retval = _FAIL;
++ break;
++ }
++#endif //CONFIG_IEEE80211W
++
++ retval = validate_recv_mgnt_frame(adapter, precv_frame);
++ if (retval == _FAIL)
++ {
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("validate_recv_mgnt_frame fail\n"));
++ }
++ retval = _FAIL; // only data frame return _SUCCESS
++ break;
++ case WIFI_CTRL_TYPE: //ctrl
++ retval = validate_recv_ctrl_frame(adapter, precv_frame);
++ if (retval == _FAIL)
++ {
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("validate_recv_ctrl_frame fail\n"));
++ }
++ retval = _FAIL; // only data frame return _SUCCESS
++ break;
++ case WIFI_DATA_TYPE: //data
++ rtw_led_control(adapter, LED_CTL_RX);
++ pattrib->qos = (subtype & BIT(7))? 1:0;
++ retval = validate_recv_data_frame(adapter, precv_frame);
++ if (retval == _FAIL)
++ {
++ struct recv_priv *precvpriv = &adapter->recvpriv;
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("validate_recv_data_frame fail\n"));
++ precvpriv->rx_drop++;
++ }
++ break;
++ default:
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("validate_recv_data_frame fail! type=0x%x\n", type));
++ #ifdef DBG_RX_DROP_FRAME
++ DBG_871X("DBG_RX_DROP_FRAME validate_recv_data_frame fail! type=0x%x\n", type);
++ #endif
++ retval = _FAIL;
++ break;
++ }
++
++exit:
++
++_func_exit_;
++
++ return retval;
++}
++
++
++//remove the wlanhdr and add the eth_hdr
++#if 1
++
++sint wlanhdr_to_ethhdr ( union recv_frame *precvframe);
++sint wlanhdr_to_ethhdr ( union recv_frame *precvframe)
++{
++ sint rmv_len;
++ u16 eth_type, len;
++ u8 bsnaphdr;
++ u8 *psnap_type;
++ struct ieee80211_snap_hdr *psnap;
++
++ sint ret=_SUCCESS;
++ _adapter *adapter =precvframe->u.hdr.adapter;
++ struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
++
++ u8 *ptr = get_recvframe_data(precvframe) ; // point to frame_ctrl field
++ struct rx_pkt_attrib *pattrib = & precvframe->u.hdr.attrib;
++
++_func_enter_;
++
++ if(pattrib->encrypt){
++ recvframe_pull_tail(precvframe, pattrib->icv_len);
++ }
++
++ psnap=(struct ieee80211_snap_hdr *)(ptr+pattrib->hdrlen + pattrib->iv_len);
++ psnap_type=ptr+pattrib->hdrlen + pattrib->iv_len+SNAP_SIZE;
++ /* convert hdr + possible LLC headers into Ethernet header */
++ //eth_type = (psnap_type[0] << 8) | psnap_type[1];
++ if((_rtw_memcmp(psnap, rtw_rfc1042_header, SNAP_SIZE) &&
++ (_rtw_memcmp(psnap_type, SNAP_ETH_TYPE_IPX, 2) == _FALSE) &&
++ (_rtw_memcmp(psnap_type, SNAP_ETH_TYPE_APPLETALK_AARP, 2)==_FALSE) )||
++ //eth_type != ETH_P_AARP && eth_type != ETH_P_IPX) ||
++ _rtw_memcmp(psnap, rtw_bridge_tunnel_header, SNAP_SIZE)){
++ /* remove RFC1042 or Bridge-Tunnel encapsulation and replace EtherType */
++ bsnaphdr = _TRUE;
++ }
++ else {
++ /* Leave Ethernet header part of hdr and full payload */
++ bsnaphdr = _FALSE;
++ }
++
++ rmv_len = pattrib->hdrlen + pattrib->iv_len +(bsnaphdr?SNAP_SIZE:0);
++ len = precvframe->u.hdr.len - rmv_len;
++
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("\n===pattrib->hdrlen: %x, pattrib->iv_len:%x ===\n\n", pattrib->hdrlen, pattrib->iv_len));
++
++ _rtw_memcpy(&eth_type, ptr+rmv_len, 2);
++ eth_type= ntohs((unsigned short )eth_type); //pattrib->ether_type
++ pattrib->eth_type = eth_type;
++
++ if ((check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE))
++ {
++ ptr += rmv_len ;
++ *ptr = 0x87;
++ *(ptr+1) = 0x12;
++
++ eth_type = 0x8712;
++ // append rx status for mp test packets
++ ptr = recvframe_pull(precvframe, (rmv_len-sizeof(struct ethhdr)+2)-24);
++ _rtw_memcpy(ptr, get_rxmem(precvframe), 24);
++ ptr+=24;
++ }
++ else {
++ ptr = recvframe_pull(precvframe, (rmv_len-sizeof(struct ethhdr)+ (bsnaphdr?2:0)));
++ }
++
++ _rtw_memcpy(ptr, pattrib->dst, ETH_ALEN);
++ _rtw_memcpy(ptr+ETH_ALEN, pattrib->src, ETH_ALEN);
++
++ if(!bsnaphdr) {
++ len = htons(len);
++ _rtw_memcpy(ptr+12, &len, 2);
++ }
++
++_func_exit_;
++ return ret;
++
++}
++
++#else
++
++sint wlanhdr_to_ethhdr ( union recv_frame *precvframe)
++{
++ sint rmv_len;
++ u16 eth_type;
++ u8 bsnaphdr;
++ u8 *psnap_type;
++ struct ieee80211_snap_hdr *psnap;
++
++ sint ret=_SUCCESS;
++ _adapter *adapter =precvframe->u.hdr.adapter;
++ struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
++
++ u8* ptr = get_recvframe_data(precvframe) ; // point to frame_ctrl field
++ struct rx_pkt_attrib *pattrib = & precvframe->u.hdr.attrib;
++ struct _vlan *pvlan = NULL;
++
++_func_enter_;
++
++ psnap=(struct ieee80211_snap_hdr *)(ptr+pattrib->hdrlen + pattrib->iv_len);
++ psnap_type=ptr+pattrib->hdrlen + pattrib->iv_len+SNAP_SIZE;
++ if (psnap->dsap==0xaa && psnap->ssap==0xaa && psnap->ctrl==0x03)
++ {
++ if (_rtw_memcmp(psnap->oui, oui_rfc1042, WLAN_IEEE_OUI_LEN))
++ bsnaphdr=_TRUE;//wlan_pkt_format = WLAN_PKT_FORMAT_SNAP_RFC1042;
++ else if (_rtw_memcmp(psnap->oui, SNAP_HDR_APPLETALK_DDP, WLAN_IEEE_OUI_LEN) &&
++ _rtw_memcmp(psnap_type, SNAP_ETH_TYPE_APPLETALK_DDP, 2) )
++ bsnaphdr=_TRUE; //wlan_pkt_format = WLAN_PKT_FORMAT_APPLETALK;
++ else if (_rtw_memcmp( psnap->oui, oui_8021h, WLAN_IEEE_OUI_LEN))
++ bsnaphdr=_TRUE; //wlan_pkt_format = WLAN_PKT_FORMAT_SNAP_TUNNEL;
++ else {
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("drop pkt due to invalid frame format!\n"));
++ ret= _FAIL;
++ goto exit;
++ }
++
++ } else
++ bsnaphdr=_FALSE;//wlan_pkt_format = WLAN_PKT_FORMAT_OTHERS;
++
++ rmv_len = pattrib->hdrlen + pattrib->iv_len +(bsnaphdr?SNAP_SIZE:0);
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("===pattrib->hdrlen: %x, pattrib->iv_len:%x ===\n", pattrib->hdrlen, pattrib->iv_len));
++
++ if (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE)
++ {
++ ptr += rmv_len ;
++ *ptr = 0x87;
++ *(ptr+1) = 0x12;
++
++ //back to original pointer
++ ptr -= rmv_len;
++ }
++
++ ptr += rmv_len ;
++
++ _rtw_memcpy(&eth_type, ptr, 2);
++ eth_type= ntohs((unsigned short )eth_type); //pattrib->ether_type
++ ptr +=2;
++
++ if(pattrib->encrypt){
++ recvframe_pull_tail(precvframe, pattrib->icv_len);
++ }
++
++ if(eth_type == 0x8100) //vlan
++ {
++ pvlan = (struct _vlan *) ptr;
++
++ //eth_type = get_vlan_encap_proto(pvlan);
++ //eth_type = pvlan->h_vlan_encapsulated_proto;//?
++ rmv_len += 4;
++ ptr+=4;
++ }
++
++ if(eth_type==0x0800)//ip
++ {
++ //struct iphdr* piphdr = (struct iphdr*) ptr;
++ //__u8 tos = (unsigned char)(pattrib->priority & 0xff);
++
++ //piphdr->tos = tos;
++
++ //if (piphdr->protocol == 0x06)
++ //{
++ // RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("@@@===recv tcp len:%d @@@===\n", precvframe->u.hdr.len));
++ //}
++ }
++ else if(eth_type==0x8712)// append rx status for mp test packets
++ {
++ //ptr -= 16;
++ //_rtw_memcpy(ptr, get_rxmem(precvframe), 16);
++ }
++ else
++ {
++#ifdef PLATFORM_OS_XP
++ NDIS_PACKET_8021Q_INFO VlanPriInfo;
++ UINT32 UserPriority = precvframe->u.hdr.attrib.priority;
++ UINT32 VlanID = (pvlan!=NULL ? get_vlan_id(pvlan) : 0 );
++
++ VlanPriInfo.Value = // Get current value.
++ NDIS_PER_PACKET_INFO_FROM_PACKET(precvframe->u.hdr.pkt, Ieee8021QInfo);
++
++ VlanPriInfo.TagHeader.UserPriority = UserPriority;
++ VlanPriInfo.TagHeader.VlanId = VlanID ;
++
++ VlanPriInfo.TagHeader.CanonicalFormatId = 0; // Should be zero.
++ VlanPriInfo.TagHeader.Reserved = 0; // Should be zero.
++ NDIS_PER_PACKET_INFO_FROM_PACKET(precvframe->u.hdr.pkt, Ieee8021QInfo) = VlanPriInfo.Value;
++#endif
++ }
++
++ if(eth_type==0x8712)// append rx status for mp test packets
++ {
++ ptr = recvframe_pull(precvframe, (rmv_len-sizeof(struct ethhdr)+2)-24);
++ _rtw_memcpy(ptr, get_rxmem(precvframe), 24);
++ ptr+=24;
++ }
++ else
++ ptr = recvframe_pull(precvframe, (rmv_len-sizeof(struct ethhdr)+2));
++
++ _rtw_memcpy(ptr, pattrib->dst, ETH_ALEN);
++ _rtw_memcpy(ptr+ETH_ALEN, pattrib->src, ETH_ALEN);
++
++ eth_type = htons((unsigned short)eth_type) ;
++ _rtw_memcpy(ptr+12, &eth_type, 2);
++
++exit:
++
++_func_exit_;
++
++ return ret;
++}
++#endif
++
++
++#ifdef CONFIG_SDIO_HCI
++#ifdef PLATFORM_LINUX
++static void recvframe_expand_pkt(
++ PADAPTER padapter,
++ union recv_frame *prframe)
++{
++ struct recv_frame_hdr *pfhdr;
++ _pkt *ppkt;
++ u8 shift_sz;
++ u32 alloc_sz;
++
++
++ pfhdr = &prframe->u.hdr;
++
++ // 6 is for IP header 8 bytes alignment in QoS packet case.
++ if (pfhdr->attrib.qos)
++ shift_sz = 6;
++ else
++ shift_sz = 0;
++
++ // for first fragment packet, need to allocate
++ // (1536 + RXDESC_SIZE + drvinfo_sz) to reassemble packet
++ // 8 is for skb->data 8 bytes alignment.
++// alloc_sz = _RND(1536 + RXDESC_SIZE + pfhdr->attrib.drvinfosize + shift_sz + 8, 128);
++ alloc_sz = 1664; // round (1536 + 24 + 32 + shift_sz + 8) to 128 bytes alignment
++
++ //3 1. alloc new skb
++ // prepare extra space for 4 bytes alignment
++ ppkt = rtw_skb_alloc(alloc_sz);
++
++ if (!ppkt) return; // no way to expand
++
++ //3 2. Prepare new skb to replace & release old skb
++ // force ppkt->data at 8-byte alignment address
++ skb_reserve(ppkt, 8 - ((SIZE_PTR)ppkt->data & 7));
++ // force ip_hdr at 8-byte alignment address according to shift_sz
++ skb_reserve(ppkt, shift_sz);
++
++ // copy data to new pkt
++ _rtw_memcpy(skb_put(ppkt, pfhdr->len), pfhdr->rx_data, pfhdr->len);
++
++ rtw_skb_free(pfhdr->pkt);
++
++ // attach new pkt to recvframe
++ pfhdr->pkt = ppkt;
++ pfhdr->rx_head = ppkt->head;
++ pfhdr->rx_data = ppkt->data;
++ pfhdr->rx_tail = skb_tail_pointer(ppkt);
++ pfhdr->rx_end = skb_end_pointer(ppkt);
++}
++#else
++#warning "recvframe_expand_pkt not implement, defrag may crash system"
++#endif
++#endif
++
++//perform defrag
++union recv_frame * recvframe_defrag(_adapter *adapter,_queue *defrag_q);
++union recv_frame * recvframe_defrag(_adapter *adapter,_queue *defrag_q)
++{
++ _list *plist, *phead;
++ u8 *data,wlanhdr_offset;
++ u8 curfragnum;
++ struct recv_frame_hdr *pfhdr,*pnfhdr;
++ union recv_frame* prframe, *pnextrframe;
++ _queue *pfree_recv_queue;
++
++_func_enter_;
++
++ curfragnum=0;
++ pfree_recv_queue=&adapter->recvpriv.free_recv_queue;
++
++ phead = get_list_head(defrag_q);
++ plist = get_next(phead);
++ prframe = LIST_CONTAINOR(plist, union recv_frame, u);
++ pfhdr=&prframe->u.hdr;
++ rtw_list_delete(&(prframe->u.list));
++
++ if(curfragnum!=pfhdr->attrib.frag_num)
++ {
++ //the first fragment number must be 0
++ //free the whole queue
++ rtw_free_recvframe(prframe, pfree_recv_queue);
++ rtw_free_recvframe_queue(defrag_q, pfree_recv_queue);
++
++ return NULL;
++ }
++
++#ifdef CONFIG_SDIO_HCI
++ recvframe_expand_pkt(adapter, prframe);
++#endif
++
++ curfragnum++;
++
++ plist= get_list_head(defrag_q);
++
++ plist = get_next(plist);
++
++ data=get_recvframe_data(prframe);
++
++ while(rtw_end_of_queue_search(phead, plist) == _FALSE)
++ {
++ pnextrframe = LIST_CONTAINOR(plist, union recv_frame , u);
++ pnfhdr=&pnextrframe->u.hdr;
++
++
++ //check the fragment sequence (2nd ~n fragment frame)
++
++ if(curfragnum!=pnfhdr->attrib.frag_num)
++ {
++ //the fragment number must be increasing (after decache)
++ //release the defrag_q & prframe
++ rtw_free_recvframe(prframe, pfree_recv_queue);
++ rtw_free_recvframe_queue(defrag_q, pfree_recv_queue);
++ return NULL;
++ }
++
++ curfragnum++;
++
++ //copy the 2nd~n fragment frame's payload to the first fragment
++ //get the 2nd~last fragment frame's payload
++
++ wlanhdr_offset = pnfhdr->attrib.hdrlen + pnfhdr->attrib.iv_len;
++
++ recvframe_pull(pnextrframe, wlanhdr_offset);
++
++ //append to first fragment frame's tail (if privacy frame, pull the ICV)
++ recvframe_pull_tail(prframe, pfhdr->attrib.icv_len);
++
++ //memcpy
++ _rtw_memcpy(pfhdr->rx_tail, pnfhdr->rx_data, pnfhdr->len);
++
++ recvframe_put(prframe, pnfhdr->len);
++
++ pfhdr->attrib.icv_len=pnfhdr->attrib.icv_len;
++ plist = get_next(plist);
++
++ };
++
++ //free the defrag_q queue and return the prframe
++ rtw_free_recvframe_queue(defrag_q, pfree_recv_queue);
++
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("Performance defrag!!!!!\n"));
++
++_func_exit_;
++
++ return prframe;
++}
++
++//check if need to defrag, if needed queue the frame to defrag_q
++union recv_frame* recvframe_chk_defrag(PADAPTER padapter, union recv_frame *precv_frame)
++{
++ u8 ismfrag;
++ u8 fragnum;
++ u8 *psta_addr;
++ struct recv_frame_hdr *pfhdr;
++ struct sta_info *psta;
++ struct sta_priv *pstapriv;
++ _list *phead;
++ union recv_frame *prtnframe = NULL;
++ _queue *pfree_recv_queue, *pdefrag_q;
++
++_func_enter_;
++
++ pstapriv = &padapter->stapriv;
++
++ pfhdr = &precv_frame->u.hdr;
++
++ pfree_recv_queue = &padapter->recvpriv.free_recv_queue;
++
++ //need to define struct of wlan header frame ctrl
++ ismfrag = pfhdr->attrib.mfrag;
++ fragnum = pfhdr->attrib.frag_num;
++
++ psta_addr = pfhdr->attrib.ta;
++ psta = rtw_get_stainfo(pstapriv, psta_addr);
++ if (psta == NULL)
++ {
++ u8 type = GetFrameType(pfhdr->rx_data);
++ if (type != WIFI_DATA_TYPE) {
++ psta = rtw_get_bcmc_stainfo(padapter);
++ pdefrag_q = &psta->sta_recvpriv.defrag_q;
++ } else
++ pdefrag_q = NULL;
++ }
++ else
++ pdefrag_q = &psta->sta_recvpriv.defrag_q;
++
++ if ((ismfrag==0) && (fragnum==0))
++ {
++ prtnframe = precv_frame;//isn't a fragment frame
++ }
++
++ if (ismfrag==1)
++ {
++ //0~(n-1) fragment frame
++ //enqueue to defraf_g
++ if(pdefrag_q != NULL)
++ {
++ if(fragnum==0)
++ {
++ //the first fragment
++ if(_rtw_queue_empty(pdefrag_q) == _FALSE)
++ {
++ //free current defrag_q
++ rtw_free_recvframe_queue(pdefrag_q, pfree_recv_queue);
++ }
++ }
++
++
++ //Then enqueue the 0~(n-1) fragment into the defrag_q
++
++ //_rtw_spinlock(&pdefrag_q->lock);
++ phead = get_list_head(pdefrag_q);
++ rtw_list_insert_tail(&pfhdr->list, phead);
++ //_rtw_spinunlock(&pdefrag_q->lock);
++
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("Enqueuq: ismfrag = %d, fragnum= %d\n", ismfrag,fragnum));
++
++ prtnframe=NULL;
++
++ }
++ else
++ {
++ //can't find this ta's defrag_queue, so free this recv_frame
++ rtw_free_recvframe(precv_frame, pfree_recv_queue);
++ prtnframe=NULL;
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("Free because pdefrag_q ==NULL: ismfrag = %d, fragnum= %d\n", ismfrag, fragnum));
++ }
++
++ }
++
++ if((ismfrag==0)&&(fragnum!=0))
++ {
++ //the last fragment frame
++ //enqueue the last fragment
++ if(pdefrag_q != NULL)
++ {
++ //_rtw_spinlock(&pdefrag_q->lock);
++ phead = get_list_head(pdefrag_q);
++ rtw_list_insert_tail(&pfhdr->list,phead);
++ //_rtw_spinunlock(&pdefrag_q->lock);
++
++ //call recvframe_defrag to defrag
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("defrag: ismfrag = %d, fragnum= %d\n", ismfrag, fragnum));
++ precv_frame = recvframe_defrag(padapter, pdefrag_q);
++ prtnframe=precv_frame;
++
++ }
++ else
++ {
++ //can't find this ta's defrag_queue, so free this recv_frame
++ rtw_free_recvframe(precv_frame, pfree_recv_queue);
++ prtnframe=NULL;
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("Free because pdefrag_q ==NULL: ismfrag = %d, fragnum= %d\n", ismfrag,fragnum));
++ }
++
++ }
++
++
++ if((prtnframe!=NULL)&&(prtnframe->u.hdr.attrib.privacy))
++ {
++ //after defrag we must check tkip mic code
++ if(recvframe_chkmic(padapter, prtnframe)==_FAIL)
++ {
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("recvframe_chkmic(padapter, prtnframe)==_FAIL\n"));
++ rtw_free_recvframe(prtnframe,pfree_recv_queue);
++ prtnframe=NULL;
++ }
++ }
++
++_func_exit_;
++
++ return prtnframe;
++
++}
++
++#define ENDIAN_FREE 1
++
++int amsdu_to_msdu(_adapter *padapter, union recv_frame *prframe);
++int amsdu_to_msdu(_adapter *padapter, union recv_frame *prframe)
++{
++#if defined (PLATFORM_LINUX) || defined (PLATFORM_FREEBSD) //for amsdu TP improvement,Creator: Thomas
++ int a_len, padding_len;
++ u16 eth_type, nSubframe_Length;
++ u8 nr_subframes, i;
++ unsigned char *pdata;
++ struct rx_pkt_attrib *pattrib;
++#ifndef PLATFORM_FREEBSD
++ unsigned char *data_ptr;
++ _pkt *sub_skb,*subframes[MAX_SUBFRAME_COUNT];
++#endif //PLATFORM_FREEBSD
++ struct recv_priv *precvpriv = &padapter->recvpriv;
++ _queue *pfree_recv_queue = &(precvpriv->free_recv_queue);
++ int ret = _SUCCESS;
++#ifdef PLATFORM_FREEBSD
++ struct mbuf *sub_m=NULL, *subframes[MAX_SUBFRAME_COUNT];
++ u8 *ptr,offset;
++#endif //PLATFORM_FREEBSD
++ nr_subframes = 0;
++
++ pattrib = &prframe->u.hdr.attrib;
++
++ recvframe_pull(prframe, prframe->u.hdr.attrib.hdrlen);
++
++ if(prframe->u.hdr.attrib.iv_len >0)
++ {
++ recvframe_pull(prframe, prframe->u.hdr.attrib.iv_len);
++ }
++
++ a_len = prframe->u.hdr.len;
++
++ pdata = prframe->u.hdr.rx_data;
++
++ while(a_len > ETH_HLEN) {
++
++ /* Offset 12 denote 2 mac address */
++#ifdef ENDIAN_FREE
++ //nSubframe_Length = ntohs(*((u16*)(pdata + 12)));
++ nSubframe_Length = RTW_GET_BE16(pdata + 12);
++#else // ENDIAN_FREE
++ nSubframe_Length = *((u16*)(pdata + 12));
++ //==m==>change the length order
++ nSubframe_Length = (nSubframe_Length>>8) + (nSubframe_Length<<8);
++ //ntohs(nSubframe_Length);
++#endif // ENDIAN_FREE
++
++ if( a_len < (ETHERNET_HEADER_SIZE + nSubframe_Length) ) {
++ DBG_871X("nRemain_Length is %d and nSubframe_Length is : %d\n",a_len,nSubframe_Length);
++ goto exit;
++ }
++
++#ifndef PLATFORM_FREEBSD
++ /* move the data point to data content */
++ pdata += ETH_HLEN;
++ a_len -= ETH_HLEN;
++
++ /* Allocate new skb for releasing to upper layer */
++#ifdef CONFIG_SKB_COPY
++ sub_skb = rtw_skb_alloc(nSubframe_Length + 12);
++ if(sub_skb)
++ {
++ skb_reserve(sub_skb, 12);
++ data_ptr = (u8 *)skb_put(sub_skb, nSubframe_Length);
++ _rtw_memcpy(data_ptr, pdata, nSubframe_Length);
++ }
++ else
++#endif // CONFIG_SKB_COPY
++ {
++ sub_skb = rtw_skb_clone(prframe->u.hdr.pkt);
++ if(sub_skb)
++ {
++ sub_skb->data = pdata;
++ sub_skb->len = nSubframe_Length;
++ skb_set_tail_pointer(sub_skb, nSubframe_Length);
++ }
++ else
++ {
++ DBG_871X("rtw_skb_clone() Fail!!! , nr_subframes = %d\n",nr_subframes);
++ break;
++ }
++ }
++
++#else // PLATFORM_FREEBSD
++
++ //PLATFORM_FREEBSD
++ //Allocate a mbuff,
++ //sub_m =m_devget(pdata, nSubframe_Length+12, 12, padapter->pifp,NULL);
++ sub_m =m_devget(pdata, nSubframe_Length+ETH_HLEN, ETHER_ALIGN, padapter->pifp,NULL);
++
++ pdata += ETH_HLEN;
++ a_len -= ETH_HLEN;
++#endif // PLATFORM_FREEBSD
++
++#ifndef PLATFORM_FREEBSD
++ //sub_skb->dev = padapter->pnetdev;
++ subframes[nr_subframes++] = sub_skb;
++#else //PLATFORM_FREEBSD
++ //PLATFORM_FREEBSD
++ subframes[nr_subframes++] = sub_m;
++#endif //PLATFORM_FREEBSD
++
++ if(nr_subframes >= MAX_SUBFRAME_COUNT) {
++ DBG_871X("ParseSubframe(): Too many Subframes! Packets dropped!\n");
++ break;
++ }
++
++ pdata += nSubframe_Length;
++ a_len -= nSubframe_Length;
++ if(a_len != 0) {
++ padding_len = 4 - ((nSubframe_Length + ETH_HLEN) & (4-1));
++ if(padding_len == 4) {
++ padding_len = 0;
++ }
++
++ if(a_len < padding_len) {
++ goto exit;
++ }
++ pdata += padding_len;
++ a_len -= padding_len;
++ }
++ }
++
++ for(i=0; i<nr_subframes; i++){
++#ifndef PLATFORM_FREEBSD
++ sub_skb = subframes[i];
++ /* convert hdr + possible LLC headers into Ethernet header */
++#ifdef ENDIAN_FREE
++ //eth_type = ntohs(*(u16*)&sub_skb->data[6]);
++ eth_type = RTW_GET_BE16(&sub_skb->data[6]);
++#else // ENDIAN_FREE
++ eth_type = (sub_skb->data[6] << 8) | sub_skb->data[7];
++#endif // ENDIAN_FREE
++ if (sub_skb->len >= 8 &&
++ ((_rtw_memcmp(sub_skb->data, rtw_rfc1042_header, SNAP_SIZE) &&
++ eth_type != ETH_P_AARP && eth_type != ETH_P_IPX) ||
++ _rtw_memcmp(sub_skb->data, rtw_bridge_tunnel_header, SNAP_SIZE) )) {
++ /* remove RFC1042 or Bridge-Tunnel encapsulation and replace EtherType */
++ skb_pull(sub_skb, SNAP_SIZE);
++ _rtw_memcpy(skb_push(sub_skb, ETH_ALEN), pattrib->src, ETH_ALEN);
++ _rtw_memcpy(skb_push(sub_skb, ETH_ALEN), pattrib->dst, ETH_ALEN);
++ } else {
++ u16 len;
++ /* Leave Ethernet header part of hdr and full payload */
++ len = htons(sub_skb->len);
++ _rtw_memcpy(skb_push(sub_skb, 2), &len, 2);
++ _rtw_memcpy(skb_push(sub_skb, ETH_ALEN), pattrib->src, ETH_ALEN);
++ _rtw_memcpy(skb_push(sub_skb, ETH_ALEN), pattrib->dst, ETH_ALEN);
++ }
++
++ /* Indicat the packets to upper layer */
++ if (sub_skb) {
++ //memset(sub_skb->cb, 0, sizeof(sub_skb->cb));
++
++#ifdef CONFIG_BR_EXT
++ // Insert NAT2.5 RX here!
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ void *br_port = NULL;
++
++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35))
++ br_port = padapter->pnetdev->br_port;
++#else // (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35))
++ rcu_read_lock();
++ br_port = rcu_dereference(padapter->pnetdev->rx_handler_data);
++ rcu_read_unlock();
++#endif // (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35))
++
++
++ if( br_port && (check_fwstate(pmlmepriv, WIFI_STATION_STATE|WIFI_ADHOC_STATE) == _TRUE) )
++ {
++ int nat25_handle_frame(_adapter *priv, struct sk_buff *skb);
++ if (nat25_handle_frame(padapter, sub_skb) == -1) {
++ //priv->ext_stats.rx_data_drops++;
++ //DEBUG_ERR("RX DROP: nat25_handle_frame fail!\n");
++ //return FAIL;
++
++#if 1
++ // bypass this frame to upper layer!!
++#else
++ rtw_skb_free(sub_skb);
++ continue;
++#endif
++ }
++ }
++#endif // CONFIG_BR_EXT
++
++ sub_skb->protocol = eth_type_trans(sub_skb, padapter->pnetdev);
++ sub_skb->dev = padapter->pnetdev;
++
++#ifdef CONFIG_TCP_CSUM_OFFLOAD_RX
++ if ( (pattrib->tcpchk_valid == 1) && (pattrib->tcp_chkrpt == 1) ) {
++ sub_skb->ip_summed = CHECKSUM_UNNECESSARY;
++ } else {
++ sub_skb->ip_summed = CHECKSUM_NONE;
++ }
++#else /* !CONFIG_TCP_CSUM_OFFLOAD_RX */
++ sub_skb->ip_summed = CHECKSUM_NONE;
++#endif //CONFIG_TCP_CSUM_OFFLOAD_RX
++
++ rtw_netif_rx(padapter->pnetdev, sub_skb);
++ }
++#else //PLATFORM_FREEBSD
++
++ //PLATFORM_FREEBSD
++ sub_m = subframes[i];
++ ptr=mtod(sub_m, u8 *);
++ offset=ETH_HLEN;
++ /* convert hdr + possible LLC headers into Ethernet header */
++#ifdef ENDIAN_FREE
++ eth_type = ntohs(*(u16*)&ptr[offset+6]);
++#else // ENDIAN_FREE
++ eth_type = ( ptr[offset+6] << 8) | ptr[offset+7];
++#endif // ENDIAN_FREE
++ if (sub_m->m_pkthdr.len >= ETH_HLEN+8 &&
++ ((_rtw_memcmp(ptr+ETH_HLEN, rtw_rfc1042_header, SNAP_SIZE) &&
++ eth_type != ETH_P_AARP && eth_type != ETH_P_IPX) ||
++ _rtw_memcmp(ptr+ETH_HLEN, rtw_bridge_tunnel_header, SNAP_SIZE) )) {
++ /* remove RFC1042 or Bridge-Tunnel encapsulation and replace EtherType */
++ offset+=SNAP_SIZE;
++ _rtw_memcpy(&ptr[offset-ETH_ALEN], pattrib->src, ETH_ALEN);
++ offset-=ETH_ALEN;
++ _rtw_memcpy(&ptr[offset-ETH_ALEN], pattrib->dst, ETH_ALEN);
++ offset-=ETH_ALEN;
++ } else {
++ u16 len;
++ /* Leave Ethernet header part of hdr and full payload */
++ len = htons(sub_m->m_pkthdr.len-offset);
++ _rtw_memcpy(&ptr[offset- 2], &len, 2);
++ offset-=2;
++ _rtw_memcpy(&ptr[offset-ETH_ALEN], pattrib->src, ETH_ALEN);
++ offset-=ETH_ALEN;
++ _rtw_memcpy(&ptr[offset-ETH_ALEN], pattrib->dst, ETH_ALEN);
++ offset-=ETH_ALEN;
++ }
++
++ m_adj(sub_m,offset);
++
++ /* Indicat the packets to upper layer */
++ if (sub_m) {
++
++#if 0
++#ifdef CONFIG_TCP_CSUM_OFFLOAD_RX
++ if ( (pattrib->tcpchk_valid == 1) && (pattrib->tcp_chkrpt == 1) ) {
++ sub_skb->ip_summed = CHECKSUM_UNNECESSARY;
++ } else {
++ sub_skb->ip_summed = CHECKSUM_NONE;
++ }
++#else /* !CONFIG_TCP_CSUM_OFFLOAD_RX */
++ sub_skb->ip_summed = CHECKSUM_NONE;
++#endif //CONFIG_TCP_CSUM_OFFLOAD_RX
++#endif //0
++
++ if ( ((u32)(mtod(sub_m, caddr_t) + 14) % 4) != 0)
++ printf("%s()-%d: mtod(sub_m) = %p\n", __FUNCTION__, __LINE__, mtod(sub_m, caddr_t));
++#ifdef CONFIG_RX_INDICATE_QUEUE
++ IF_ENQUEUE(&precvpriv->rx_indicate_queue, sub_m);
++ if (_IF_QLEN(&precvpriv->rx_indicate_queue) <= 1) {
++ taskqueue_enqueue(taskqueue_thread, &precvpriv->rx_indicate_tasklet);
++ }
++#else // CONFIG_RX_INDICATE_QUEUE
++ (*padapter->pifp->if_input)(padapter->pifp, sub_m);
++#endif // CONFIG_RX_INDICATE_QUEUE
++ }
++
++#endif //PLATFORM_FREEBSD
++ }
++
++exit:
++
++ prframe->u.hdr.len=0;
++ rtw_free_recvframe(prframe, pfree_recv_queue);//free this recv_frame
++
++ return ret;
++#else // || defined (PLATFORM_LINUX) || defined (PLATFORM_FREEBSD)
++#ifdef PLATFORM_WINDOWS
++ _irqL irql;
++#endif //PLATFORM_WINDOWS
++ unsigned char *ptr, *pdata, *pbuf, *psnap_type;
++ union recv_frame *pnrframe, *pnrframe_new;
++ int a_len, mv_len, padding_len;
++ u16 eth_type, type_len;
++ u8 bsnaphdr;
++ struct ieee80211_snap_hdr *psnap;
++ struct _vlan *pvlan;
++ struct recv_priv *precvpriv = &padapter->recvpriv;
++ _queue *pfree_recv_queue = &(precvpriv->free_recv_queue);
++ int ret = _SUCCESS;
++#ifdef PLATFORM_WINDOWS
++ struct recv_buf *precvbuf = prframe->u.hdr.precvbuf;
++#endif //PLATFORM_WINDOWS
++ a_len = prframe->u.hdr.len - prframe->u.hdr.attrib.hdrlen;
++
++ recvframe_pull(prframe, prframe->u.hdr.attrib.hdrlen);
++
++ if(prframe->u.hdr.attrib.iv_len >0)
++ {
++ recvframe_pull(prframe, prframe->u.hdr.attrib.iv_len);
++ }
++
++ pdata = prframe->u.hdr.rx_data;
++
++ prframe->u.hdr.len=0;
++
++ pnrframe = prframe;
++
++
++ do{
++
++ mv_len=0;
++ pnrframe->u.hdr.rx_data = pnrframe->u.hdr.rx_tail = pdata;
++ ptr = pdata;
++
++
++ _rtw_memcpy(pnrframe->u.hdr.attrib.dst, ptr, ETH_ALEN);
++ ptr+=ETH_ALEN;
++ _rtw_memcpy(pnrframe->u.hdr.attrib.src, ptr, ETH_ALEN);
++ ptr+=ETH_ALEN;
++
++ _rtw_memcpy(&type_len, ptr, 2);
++ type_len= ntohs((unsigned short )type_len);
++ ptr +=2;
++ mv_len += ETH_HLEN;
++
++ recvframe_put(pnrframe, type_len+ETH_HLEN);//update tail;
++
++ if(pnrframe->u.hdr.rx_data >= pnrframe->u.hdr.rx_tail || type_len<8)
++ {
++ //panic("pnrframe->u.hdr.rx_data >= pnrframe->u.hdr.rx_tail || type_len<8\n");
++
++ rtw_free_recvframe(pnrframe, pfree_recv_queue);
++
++ goto exit;
++ }
++
++ psnap=(struct ieee80211_snap_hdr *)(ptr);
++ psnap_type=ptr+SNAP_SIZE;
++ if (psnap->dsap==0xaa && psnap->ssap==0xaa && psnap->ctrl==0x03)
++ {
++ if ( _rtw_memcmp(psnap->oui, oui_rfc1042, WLAN_IEEE_OUI_LEN))
++ {
++ bsnaphdr=_TRUE;//wlan_pkt_format = WLAN_PKT_FORMAT_SNAP_RFC1042;
++ }
++ else if (_rtw_memcmp(psnap->oui, SNAP_HDR_APPLETALK_DDP, WLAN_IEEE_OUI_LEN) &&
++ _rtw_memcmp(psnap_type, SNAP_ETH_TYPE_APPLETALK_DDP, 2) )
++ {
++ bsnaphdr=_TRUE; //wlan_pkt_format = WLAN_PKT_FORMAT_APPLETALK;
++ }
++ else if (_rtw_memcmp( psnap->oui, oui_8021h, WLAN_IEEE_OUI_LEN))
++ {
++ bsnaphdr=_TRUE; //wlan_pkt_format = WLAN_PKT_FORMAT_SNAP_TUNNEL;
++ }
++ else
++ {
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("drop pkt due to invalid frame format!\n"));
++
++ //KeBugCheckEx(0x87123333, 0xe0, 0x4c, 0x87, 0xdd);
++
++ //panic("0x87123333, 0xe0, 0x4c, 0x87, 0xdd\n");
++
++ rtw_free_recvframe(pnrframe, pfree_recv_queue);
++
++ goto exit;
++ }
++
++ }
++ else
++ {
++ bsnaphdr=_FALSE;//wlan_pkt_format = WLAN_PKT_FORMAT_OTHERS;
++ }
++
++ ptr += (bsnaphdr?SNAP_SIZE:0);
++ _rtw_memcpy(&eth_type, ptr, 2);
++ eth_type= ntohs((unsigned short )eth_type); //pattrib->ether_type
++
++ mv_len+= 2+(bsnaphdr?SNAP_SIZE:0);
++ ptr += 2;//now move to iphdr;
++
++ pvlan = NULL;
++ if(eth_type == 0x8100) //vlan
++ {
++ pvlan = (struct _vlan *)ptr;
++ ptr+=4;
++ mv_len+=4;
++ }
++
++ if(eth_type==0x0800)//ip
++ {
++ struct iphdr* piphdr = (struct iphdr*)ptr;
++
++
++ if (piphdr->protocol == 0x06)
++ {
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("@@@===recv tcp len:%d @@@===\n", pnrframe->u.hdr.len));
++ }
++ }
++#ifdef PLATFORM_OS_XP
++ else
++ {
++ NDIS_PACKET_8021Q_INFO VlanPriInfo;
++ UINT32 UserPriority = pnrframe->u.hdr.attrib.priority;
++ UINT32 VlanID = (pvlan!=NULL ? get_vlan_id(pvlan) : 0 );
++
++ VlanPriInfo.Value = // Get current value.
++ NDIS_PER_PACKET_INFO_FROM_PACKET(pnrframe->u.hdr.pkt, Ieee8021QInfo);
++
++ VlanPriInfo.TagHeader.UserPriority = UserPriority;
++ VlanPriInfo.TagHeader.VlanId = VlanID;
++
++ VlanPriInfo.TagHeader.CanonicalFormatId = 0; // Should be zero.
++ VlanPriInfo.TagHeader.Reserved = 0; // Should be zero.
++ NDIS_PER_PACKET_INFO_FROM_PACKET(pnrframe->u.hdr.pkt, Ieee8021QInfo) = VlanPriInfo.Value;
++
++ }
++#endif //PLATFORM_OS_XP
++
++ pbuf = recvframe_pull(pnrframe, (mv_len-sizeof(struct ethhdr)));
++
++ _rtw_memcpy(pbuf, pnrframe->u.hdr.attrib.dst, ETH_ALEN);
++ _rtw_memcpy(pbuf+ETH_ALEN, pnrframe->u.hdr.attrib.src, ETH_ALEN);
++
++ eth_type = htons((unsigned short)eth_type) ;
++ _rtw_memcpy(pbuf+12, &eth_type, 2);
++
++ padding_len = (4) - ((type_len + ETH_HLEN)&(4-1));
++
++ a_len -= (type_len + ETH_HLEN + padding_len) ;
++
++
++#if 0
++
++ if(a_len > ETH_HLEN)
++ {
++ pnrframe_new = rtw_alloc_recvframe(pfree_recv_queue);
++ if(pnrframe_new)
++ {
++ _pkt *pskb_copy;
++ unsigned int copy_len = pnrframe->u.hdr.len;
++
++ _rtw_init_listhead(&pnrframe_new->u.hdr.list);
++
++ pskb_copy = rtw_skb_alloc(copy_len+64);
++
++ if(pskb_copy==NULL)
++ {
++ DBG_871X("amsdu_to_msdu:can not all(ocate memory for skb copy\n");
++ }
++
++ pnrframe_new->u.hdr.pkt = pskb_copy;
++
++ _rtw_memcpy(pskb_copy->data, pnrframe->u.hdr.rx_data, copy_len);
++
++ pnrframe_new->u.hdr.rx_data = pnrframe->u.hdr.rx_data;
++ pnrframe_new->u.hdr.rx_tail = pnrframe->u.hdr.rx_data + copy_len;
++
++
++ if ((padapter->bDriverStopped ==_FALSE)&&( padapter->bSurpriseRemoved==_FALSE))
++ {
++ rtw_recv_indicatepkt(padapter, pnrframe_new);//indicate this recv_frame
++ }
++ else
++ {
++ rtw_free_recvframe(pnrframe_new, pfree_recv_queue);//free this recv_frame
++ }
++
++ }
++ else
++ {
++ DBG_871X("amsdu_to_msdu:can not allocate memory for pnrframe_new\n");
++ }
++
++ }
++ else
++ {
++ if ((padapter->bDriverStopped ==_FALSE)&&( padapter->bSurpriseRemoved==_FALSE))
++ {
++ rtw_recv_indicatepkt(padapter, pnrframe);//indicate this recv_frame
++ }
++ else
++ {
++ rtw_free_recvframe(pnrframe, pfree_recv_queue);//free this recv_frame
++ }
++
++ pnrframe = NULL;
++
++ }
++
++#else // 0
++
++ //padding_len = (4) - ((type_len + ETH_HLEN)&(4-1));
++
++ //a_len -= (type_len + ETH_HLEN + padding_len) ;
++
++ pnrframe_new = NULL;
++
++
++ if(a_len > ETH_HLEN)
++ {
++ pnrframe_new = rtw_alloc_recvframe(pfree_recv_queue);
++
++ if(pnrframe_new)
++ {
++
++
++ //pnrframe_new->u.hdr.precvbuf = precvbuf;//precvbuf is assigned before call rtw_init_recvframe()
++ //rtw_init_recvframe(pnrframe_new, precvpriv);
++ {
++#ifdef PLATFORM_LINUX
++ _pkt *pskb = pnrframe->u.hdr.pkt;
++#endif //PLATFORM_LINUX
++ _rtw_init_listhead(&pnrframe_new->u.hdr.list);
++
++ pnrframe_new->u.hdr.len=0;
++
++#ifdef PLATFORM_LINUX
++ if(pskb)
++ {
++ pnrframe_new->u.hdr.pkt = rtw_skb_clone(pskb);
++ }
++#endif //PLATFORM_LINUX
++
++ }
++
++ pdata += (type_len + ETH_HLEN + padding_len);
++ pnrframe_new->u.hdr.rx_head = pnrframe_new->u.hdr.rx_data = pnrframe_new->u.hdr.rx_tail = pdata;
++ pnrframe_new->u.hdr.rx_end = pdata + a_len + padding_len;//
++
++#ifdef PLATFORM_WINDOWS
++ pnrframe_new->u.hdr.precvbuf=precvbuf;
++ _enter_critical_bh(&precvbuf->recvbuf_lock, &irql);
++ precvbuf->ref_cnt++;
++ _exit_critical_bh(&precvbuf->recvbuf_lock, &irql);
++#endif //PLATFORM_WINDOWS
++
++ }
++ else
++ {
++ //panic("pnrframe_new=%x\n", pnrframe_new);
++ }
++ }
++
++
++ if ((padapter->bDriverStopped ==_FALSE)&&( padapter->bSurpriseRemoved==_FALSE) )
++ {
++ rtw_recv_indicatepkt(padapter, pnrframe);//indicate this recv_frame
++ }
++ else
++ {
++ rtw_free_recvframe(pnrframe, pfree_recv_queue);//free this recv_frame
++ }
++
++
++ pnrframe = NULL;
++ if(pnrframe_new)
++ {
++ pnrframe = pnrframe_new;
++ }
++
++
++#endif // end defined (PLATFORM_LINUX) || defined (PLATFORM_FREEBSD)
++
++ }while(pnrframe);
++
++exit:
++
++ return ret;
++#endif
++}
++
++int check_indicate_seq(struct recv_reorder_ctrl *preorder_ctrl, u16 seq_num);
++int check_indicate_seq(struct recv_reorder_ctrl *preorder_ctrl, u16 seq_num)
++{
++ u8 wsize = preorder_ctrl->wsize_b;
++ u16 wend = (preorder_ctrl->indicate_seq + wsize -1) & 0xFFF;//% 4096;
++
++ // Rx Reorder initialize condition.
++ if (preorder_ctrl->indicate_seq == 0xFFFF)
++ {
++ preorder_ctrl->indicate_seq = seq_num;
++ #ifdef DBG_RX_SEQ
++ DBG_871X("DBG_RX_SEQ %s:%d init IndicateSeq: %d, NewSeq: %d\n", __FUNCTION__, __LINE__,
++ preorder_ctrl->indicate_seq, seq_num);
++ #endif
++
++ //DbgPrint("check_indicate_seq, 1st->indicate_seq=%d\n", precvpriv->indicate_seq);
++ }
++
++ //DbgPrint("enter->check_indicate_seq(): IndicateSeq: %d, NewSeq: %d\n", precvpriv->indicate_seq, seq_num);
++
++ // Drop out the packet which SeqNum is smaller than WinStart
++ if( SN_LESS(seq_num, preorder_ctrl->indicate_seq) )
++ {
++ //RT_TRACE(COMP_RX_REORDER, DBG_LOUD, ("CheckRxTsIndicateSeq(): Packet Drop! IndicateSeq: %d, NewSeq: %d\n", pTS->RxIndicateSeq, NewSeqNum));
++ //DbgPrint("CheckRxTsIndicateSeq(): Packet Drop! IndicateSeq: %d, NewSeq: %d\n", precvpriv->indicate_seq, seq_num);
++
++ #ifdef DBG_RX_DROP_FRAME
++ DBG_871X("%s IndicateSeq: %d > NewSeq: %d\n", __FUNCTION__,
++ preorder_ctrl->indicate_seq, seq_num);
++ #endif
++
++
++ return _FALSE;
++ }
++
++ //
++ // Sliding window manipulation. Conditions includes:
++ // 1. Incoming SeqNum is equal to WinStart =>Window shift 1
++ // 2. Incoming SeqNum is larger than the WinEnd => Window shift N
++ //
++ if( SN_EQUAL(seq_num, preorder_ctrl->indicate_seq) )
++ {
++ preorder_ctrl->indicate_seq = (preorder_ctrl->indicate_seq + 1) & 0xFFF;
++ #ifdef DBG_RX_SEQ
++ DBG_871X("DBG_RX_SEQ %s:%d SN_EQUAL IndicateSeq: %d, NewSeq: %d\n", __FUNCTION__, __LINE__,
++ preorder_ctrl->indicate_seq, seq_num);
++ #endif
++ }
++ else if(SN_LESS(wend, seq_num))
++ {
++ //RT_TRACE(COMP_RX_REORDER, DBG_LOUD, ("CheckRxTsIndicateSeq(): Window Shift! IndicateSeq: %d, NewSeq: %d\n", pTS->RxIndicateSeq, NewSeqNum));
++ //DbgPrint("CheckRxTsIndicateSeq(): Window Shift! IndicateSeq: %d, NewSeq: %d\n", precvpriv->indicate_seq, seq_num);
++
++ // boundary situation, when seq_num cross 0xFFF
++ if(seq_num >= (wsize - 1))
++ preorder_ctrl->indicate_seq = seq_num + 1 -wsize;
++ else
++ preorder_ctrl->indicate_seq = 0xFFF - (wsize - (seq_num + 1)) + 1;
++
++ #ifdef DBG_RX_SEQ
++ DBG_871X("DBG_RX_SEQ %s:%d SN_LESS(wend, seq_num) IndicateSeq: %d, NewSeq: %d\n", __FUNCTION__, __LINE__,
++ preorder_ctrl->indicate_seq, seq_num);
++ #endif
++ }
++
++ //DbgPrint("exit->check_indicate_seq(): IndicateSeq: %d, NewSeq: %d\n", precvpriv->indicate_seq, seq_num);
++
++ return _TRUE;
++}
++
++int enqueue_reorder_recvframe(struct recv_reorder_ctrl *preorder_ctrl, union recv_frame *prframe);
++int enqueue_reorder_recvframe(struct recv_reorder_ctrl *preorder_ctrl, union recv_frame *prframe)
++{
++ struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib;
++ _queue *ppending_recvframe_queue = &preorder_ctrl->pending_recvframe_queue;
++ _list *phead, *plist;
++ union recv_frame *pnextrframe;
++ struct rx_pkt_attrib *pnextattrib;
++
++ //DbgPrint("+enqueue_reorder_recvframe()\n");
++
++ //_enter_critical_ex(&ppending_recvframe_queue->lock, &irql);
++ //_rtw_spinlock_ex(&ppending_recvframe_queue->lock);
++
++
++ phead = get_list_head(ppending_recvframe_queue);
++ plist = get_next(phead);
++
++ while(rtw_end_of_queue_search(phead, plist) == _FALSE)
++ {
++ pnextrframe = LIST_CONTAINOR(plist, union recv_frame, u);
++ pnextattrib = &pnextrframe->u.hdr.attrib;
++
++ if(SN_LESS(pnextattrib->seq_num, pattrib->seq_num))
++ {
++ plist = get_next(plist);
++ }
++ else if( SN_EQUAL(pnextattrib->seq_num, pattrib->seq_num))
++ {
++ //Duplicate entry is found!! Do not insert current entry.
++ //RT_TRACE(COMP_RX_REORDER, DBG_TRACE, ("InsertRxReorderList(): Duplicate packet is dropped!! IndicateSeq: %d, NewSeq: %d\n", pTS->RxIndicateSeq, SeqNum));
++
++ //_exit_critical_ex(&ppending_recvframe_queue->lock, &irql);
++
++ return _FALSE;
++ }
++ else
++ {
++ break;
++ }
++
++ //DbgPrint("enqueue_reorder_recvframe():while\n");
++
++ }
++
++
++ //_enter_critical_ex(&ppending_recvframe_queue->lock, &irql);
++ //_rtw_spinlock_ex(&ppending_recvframe_queue->lock);
++
++ rtw_list_delete(&(prframe->u.hdr.list));
++
++ rtw_list_insert_tail(&(prframe->u.hdr.list), plist);
++
++ //_rtw_spinunlock_ex(&ppending_recvframe_queue->lock);
++ //_exit_critical_ex(&ppending_recvframe_queue->lock, &irql);
++
++
++ //RT_TRACE(COMP_RX_REORDER, DBG_TRACE, ("InsertRxReorderList(): Pkt insert into buffer!! IndicateSeq: %d, NewSeq: %d\n", pTS->RxIndicateSeq, SeqNum));
++ return _TRUE;
++
++}
++
++int recv_indicatepkts_in_order(_adapter *padapter, struct recv_reorder_ctrl *preorder_ctrl, int bforced);
++int recv_indicatepkts_in_order(_adapter *padapter, struct recv_reorder_ctrl *preorder_ctrl, int bforced)
++{
++ //_irqL irql;
++ //u8 bcancelled;
++ _list *phead, *plist;
++ union recv_frame *prframe;
++ struct rx_pkt_attrib *pattrib;
++ //u8 index = 0;
++ int bPktInBuf = _FALSE;
++ struct recv_priv *precvpriv = &padapter->recvpriv;
++ _queue *ppending_recvframe_queue = &preorder_ctrl->pending_recvframe_queue;
++
++ //DbgPrint("+recv_indicatepkts_in_order\n");
++
++ //_enter_critical_ex(&ppending_recvframe_queue->lock, &irql);
++ //_rtw_spinlock_ex(&ppending_recvframe_queue->lock);
++
++ phead = get_list_head(ppending_recvframe_queue);
++ plist = get_next(phead);
++
++#if 0
++ // Check if there is any other indication thread running.
++ if(pTS->RxIndicateState == RXTS_INDICATE_PROCESSING)
++ return;
++#endif
++
++ // Handling some condition for forced indicate case.
++ if(bforced==_TRUE)
++ {
++ if(rtw_is_list_empty(phead))
++ {
++ // _exit_critical_ex(&ppending_recvframe_queue->lock, &irql);
++ //_rtw_spinunlock_ex(&ppending_recvframe_queue->lock);
++ return _TRUE;
++ }
++
++ prframe = LIST_CONTAINOR(plist, union recv_frame, u);
++ pattrib = &prframe->u.hdr.attrib;
++ preorder_ctrl->indicate_seq = pattrib->seq_num;
++ #ifdef DBG_RX_SEQ
++ DBG_871X("DBG_RX_SEQ %s:%d IndicateSeq: %d, NewSeq: %d\n", __FUNCTION__, __LINE__,
++ preorder_ctrl->indicate_seq, pattrib->seq_num);
++ #endif
++ }
++
++ // Prepare indication list and indication.
++ // Check if there is any packet need indicate.
++ while(!rtw_is_list_empty(phead))
++ {
++
++ prframe = LIST_CONTAINOR(plist, union recv_frame, u);
++ pattrib = &prframe->u.hdr.attrib;
++
++ if(!SN_LESS(preorder_ctrl->indicate_seq, pattrib->seq_num))
++ {
++ RT_TRACE(_module_rtl871x_recv_c_, _drv_notice_,
++ ("recv_indicatepkts_in_order: indicate=%d seq=%d amsdu=%d\n",
++ preorder_ctrl->indicate_seq, pattrib->seq_num, pattrib->amsdu));
++
++#if 0
++ // This protect buffer from overflow.
++ if(index >= REORDER_WIN_SIZE)
++ {
++ RT_ASSERT(FALSE, ("IndicateRxReorderList(): Buffer overflow!! \n"));
++ bPktInBuf = TRUE;
++ break;
++ }
++#endif
++
++ plist = get_next(plist);
++ rtw_list_delete(&(prframe->u.hdr.list));
++
++ if(SN_EQUAL(preorder_ctrl->indicate_seq, pattrib->seq_num))
++ {
++ preorder_ctrl->indicate_seq = (preorder_ctrl->indicate_seq + 1) & 0xFFF;
++ #ifdef DBG_RX_SEQ
++ DBG_871X("DBG_RX_SEQ %s:%d IndicateSeq: %d, NewSeq: %d\n", __FUNCTION__, __LINE__,
++ preorder_ctrl->indicate_seq, pattrib->seq_num);
++ #endif
++ }
++
++#if 0
++ index++;
++ if(index==1)
++ {
++ //Cancel previous pending timer.
++ //PlatformCancelTimer(Adapter, &pTS->RxPktPendingTimer);
++ if(bforced!=_TRUE)
++ {
++ //DBG_871X("_cancel_timer(&preorder_ctrl->reordering_ctrl_timer, &bcancelled);\n");
++ _cancel_timer(&preorder_ctrl->reordering_ctrl_timer, &bcancelled);
++ }
++ }
++#endif
++
++ //Set this as a lock to make sure that only one thread is indicating packet.
++ //pTS->RxIndicateState = RXTS_INDICATE_PROCESSING;
++
++ // Indicate packets
++ //RT_ASSERT((index<=REORDER_WIN_SIZE), ("RxReorderIndicatePacket(): Rx Reorder buffer full!! \n"));
++
++
++ //indicate this recv_frame
++ //DbgPrint("recv_indicatepkts_in_order, indicate_seq=%d, seq_num=%d\n", precvpriv->indicate_seq, pattrib->seq_num);
++ if(!pattrib->amsdu)
++ {
++ //DBG_871X("recv_indicatepkts_in_order, amsdu!=1, indicate_seq=%d, seq_num=%d\n", preorder_ctrl->indicate_seq, pattrib->seq_num);
++
++ if ((padapter->bDriverStopped == _FALSE) &&
++ (padapter->bSurpriseRemoved == _FALSE))
++ {
++
++ rtw_recv_indicatepkt(padapter, prframe);//indicate this recv_frame
++
++ }
++ }
++ else if(pattrib->amsdu==1)
++ {
++ if(amsdu_to_msdu(padapter, prframe)!=_SUCCESS)
++ {
++ rtw_free_recvframe(prframe, &precvpriv->free_recv_queue);
++ }
++ }
++ else
++ {
++ //error condition;
++ }
++
++
++ //Update local variables.
++ bPktInBuf = _FALSE;
++
++ }
++ else
++ {
++ bPktInBuf = _TRUE;
++ break;
++ }
++
++ //DbgPrint("recv_indicatepkts_in_order():while\n");
++
++ }
++
++ //_rtw_spinunlock_ex(&ppending_recvframe_queue->lock);
++ //_exit_critical_ex(&ppending_recvframe_queue->lock, &irql);
++
++/*
++ //Release the indication lock and set to new indication step.
++ if(bPktInBuf)
++ {
++ // Set new pending timer.
++ //pTS->RxIndicateState = RXTS_INDICATE_REORDER;
++ //PlatformSetTimer(Adapter, &pTS->RxPktPendingTimer, pHTInfo->RxReorderPendingTime);
++ //DBG_871X("_set_timer(&preorder_ctrl->reordering_ctrl_timer, REORDER_WAIT_TIME)\n");
++ _set_timer(&preorder_ctrl->reordering_ctrl_timer, REORDER_WAIT_TIME);
++ }
++ else
++ {
++ //pTS->RxIndicateState = RXTS_INDICATE_IDLE;
++ }
++*/
++ //_exit_critical_ex(&ppending_recvframe_queue->lock, &irql);
++
++ //return _TRUE;
++ return bPktInBuf;
++
++}
++
++int recv_indicatepkt_reorder(_adapter *padapter, union recv_frame *prframe);
++int recv_indicatepkt_reorder(_adapter *padapter, union recv_frame *prframe)
++{
++ _irqL irql;
++ int retval = _SUCCESS;
++ struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib;
++ struct recv_reorder_ctrl *preorder_ctrl = prframe->u.hdr.preorder_ctrl;
++ _queue *ppending_recvframe_queue = &preorder_ctrl->pending_recvframe_queue;
++
++ if(!pattrib->amsdu)
++ {
++ //s1.
++ wlanhdr_to_ethhdr(prframe);
++
++ //if ((pattrib->qos!=1) /*|| pattrib->priority!=0 || IS_MCAST(pattrib->ra)*/
++ // || (pattrib->eth_type==0x0806) || (pattrib->ack_policy!=0))
++ if (pattrib->qos!=1)
++ {
++ if ((padapter->bDriverStopped == _FALSE) &&
++ (padapter->bSurpriseRemoved == _FALSE))
++ {
++ RT_TRACE(_module_rtl871x_recv_c_, _drv_alert_, ("@@@@ recv_indicatepkt_reorder -recv_func recv_indicatepkt\n" ));
++
++ rtw_recv_indicatepkt(padapter, prframe);
++ return _SUCCESS;
++
++ }
++
++ #ifdef DBG_RX_DROP_FRAME
++ DBG_871X("DBG_RX_DROP_FRAME %s pattrib->qos !=1\n", __FUNCTION__);
++ #endif
++
++ return _FAIL;
++
++ }
++
++ if (preorder_ctrl->enable == _FALSE)
++ {
++ //indicate this recv_frame
++ preorder_ctrl->indicate_seq = pattrib->seq_num;
++ #ifdef DBG_RX_SEQ
++ DBG_871X("DBG_RX_SEQ %s:%d IndicateSeq: %d, NewSeq: %d\n", __FUNCTION__, __LINE__,
++ preorder_ctrl->indicate_seq, pattrib->seq_num);
++ #endif
++
++ rtw_recv_indicatepkt(padapter, prframe);
++
++ preorder_ctrl->indicate_seq = (preorder_ctrl->indicate_seq + 1)%4096;
++ #ifdef DBG_RX_SEQ
++ DBG_871X("DBG_RX_SEQ %s:%d IndicateSeq: %d, NewSeq: %d\n", __FUNCTION__, __LINE__,
++ preorder_ctrl->indicate_seq, pattrib->seq_num);
++ #endif
++
++ return _SUCCESS;
++ }
++
++#ifndef CONFIG_RECV_REORDERING_CTRL
++ //indicate this recv_frame
++ rtw_recv_indicatepkt(padapter, prframe);
++ return _SUCCESS;
++#endif
++
++ }
++ else if(pattrib->amsdu==1) //temp filter -> means didn't support A-MSDUs in a A-MPDU
++ {
++ if (preorder_ctrl->enable == _FALSE)
++ {
++ preorder_ctrl->indicate_seq = pattrib->seq_num;
++ #ifdef DBG_RX_SEQ
++ DBG_871X("DBG_RX_SEQ %s:%d IndicateSeq: %d, NewSeq: %d\n", __FUNCTION__, __LINE__,
++ preorder_ctrl->indicate_seq, pattrib->seq_num);
++ #endif
++
++ retval = amsdu_to_msdu(padapter, prframe);
++
++ preorder_ctrl->indicate_seq = (preorder_ctrl->indicate_seq + 1)%4096;
++ #ifdef DBG_RX_SEQ
++ DBG_871X("DBG_RX_SEQ %s:%d IndicateSeq: %d, NewSeq: %d\n", __FUNCTION__, __LINE__,
++ preorder_ctrl->indicate_seq, pattrib->seq_num);
++ #endif
++
++ if(retval != _SUCCESS){
++ #ifdef DBG_RX_DROP_FRAME
++ DBG_871X("DBG_RX_DROP_FRAME %s amsdu_to_msdu fail\n", __FUNCTION__);
++ #endif
++ }
++
++ return retval;
++ }
++ }
++ else
++ {
++
++ }
++
++ _enter_critical_bh(&ppending_recvframe_queue->lock, &irql);
++
++ RT_TRACE(_module_rtl871x_recv_c_, _drv_notice_,
++ ("recv_indicatepkt_reorder: indicate=%d seq=%d\n",
++ preorder_ctrl->indicate_seq, pattrib->seq_num));
++
++ //s2. check if winstart_b(indicate_seq) needs to been updated
++ if(!check_indicate_seq(preorder_ctrl, pattrib->seq_num))
++ {
++ //pHTInfo->RxReorderDropCounter++;
++ //ReturnRFDList(Adapter, pRfd);
++ //RT_TRACE(COMP_RX_REORDER, DBG_TRACE, ("RxReorderIndicatePacket() ==> Packet Drop!!\n"));
++ //_exit_critical_ex(&ppending_recvframe_queue->lock, &irql);
++ //return _FAIL;
++
++ #ifdef DBG_RX_DROP_FRAME
++ DBG_871X("DBG_RX_DROP_FRAME %s check_indicate_seq fail\n", __FUNCTION__);
++ #endif
++#if 0
++ rtw_recv_indicatepkt(padapter, prframe);
++
++ _exit_critical_bh(&ppending_recvframe_queue->lock, &irql);
++
++ goto _success_exit;
++#else
++ goto _err_exit;
++#endif
++ }
++
++
++ //s3. Insert all packet into Reorder Queue to maintain its ordering.
++ if(!enqueue_reorder_recvframe(preorder_ctrl, prframe))
++ {
++ //DbgPrint("recv_indicatepkt_reorder, enqueue_reorder_recvframe fail!\n");
++ //_exit_critical_ex(&ppending_recvframe_queue->lock, &irql);
++ //return _FAIL;
++ #ifdef DBG_RX_DROP_FRAME
++ DBG_871X("DBG_RX_DROP_FRAME %s enqueue_reorder_recvframe fail\n", __FUNCTION__);
++ #endif
++ goto _err_exit;
++ }
++
++
++ //s4.
++ // Indication process.
++ // After Packet dropping and Sliding Window shifting as above, we can now just indicate the packets
++ // with the SeqNum smaller than latest WinStart and buffer other packets.
++ //
++ // For Rx Reorder condition:
++ // 1. All packets with SeqNum smaller than WinStart => Indicate
++ // 2. All packets with SeqNum larger than or equal to WinStart => Buffer it.
++ //
++
++ //recv_indicatepkts_in_order(padapter, preorder_ctrl, _TRUE);
++ if(recv_indicatepkts_in_order(padapter, preorder_ctrl, _FALSE)==_TRUE)
++ {
++ _set_timer(&preorder_ctrl->reordering_ctrl_timer, REORDER_WAIT_TIME);
++ _exit_critical_bh(&ppending_recvframe_queue->lock, &irql);
++ }
++ else
++ {
++ _exit_critical_bh(&ppending_recvframe_queue->lock, &irql);
++ _cancel_timer_ex(&preorder_ctrl->reordering_ctrl_timer);
++ }
++
++
++_success_exit:
++
++ return _SUCCESS;
++
++_err_exit:
++
++ _exit_critical_bh(&ppending_recvframe_queue->lock, &irql);
++
++ return _FAIL;
++}
++
++
++void rtw_reordering_ctrl_timeout_handler(void *pcontext)
++{
++ _irqL irql;
++ struct recv_reorder_ctrl *preorder_ctrl = (struct recv_reorder_ctrl *)pcontext;
++ _adapter *padapter = preorder_ctrl->padapter;
++ _queue *ppending_recvframe_queue = &preorder_ctrl->pending_recvframe_queue;
++
++
++ if(padapter->bDriverStopped ||padapter->bSurpriseRemoved)
++ {
++ return;
++ }
++
++ //DBG_871X("+rtw_reordering_ctrl_timeout_handler()=>\n");
++
++ _enter_critical_bh(&ppending_recvframe_queue->lock, &irql);
++
++ if(recv_indicatepkts_in_order(padapter, preorder_ctrl, _TRUE)==_TRUE)
++ {
++ _set_timer(&preorder_ctrl->reordering_ctrl_timer, REORDER_WAIT_TIME);
++ }
++
++ _exit_critical_bh(&ppending_recvframe_queue->lock, &irql);
++
++}
++
++int process_recv_indicatepkts(_adapter *padapter, union recv_frame *prframe);
++int process_recv_indicatepkts(_adapter *padapter, union recv_frame *prframe)
++{
++ int retval = _SUCCESS;
++ //struct recv_priv *precvpriv = &padapter->recvpriv;
++ //struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++#ifdef CONFIG_TDLS
++ struct sta_info *psta = prframe->u.hdr.psta;
++#endif //CONFIG_TDLS
++
++#ifdef CONFIG_80211N_HT
++
++ struct ht_priv *phtpriv = &pmlmepriv->htpriv;
++
++#ifdef CONFIG_TDLS
++ if( (phtpriv->ht_option==_TRUE) ||
++ ((psta->tdls_sta_state & TDLS_LINKED_STATE) &&
++ (psta->htpriv.ht_option==_TRUE) &&
++ (psta->htpriv.ampdu_enable==_TRUE))) //B/G/N Mode
++#else
++ if(phtpriv->ht_option==_TRUE) //B/G/N Mode
++#endif //CONFIG_TDLS
++ {
++ //prframe->u.hdr.preorder_ctrl = &precvpriv->recvreorder_ctrl[pattrib->priority];
++
++ if(recv_indicatepkt_reorder(padapter, prframe)!=_SUCCESS)// including perform A-MPDU Rx Ordering Buffer Control
++ {
++ #ifdef DBG_RX_DROP_FRAME
++ DBG_871X("DBG_RX_DROP_FRAME %s recv_indicatepkt_reorder error!\n", __FUNCTION__);
++ #endif
++
++ if ((padapter->bDriverStopped == _FALSE) &&
++ (padapter->bSurpriseRemoved == _FALSE))
++ {
++ retval = _FAIL;
++ return retval;
++ }
++ }
++ }
++ else //B/G mode
++#endif
++ {
++ retval=wlanhdr_to_ethhdr (prframe);
++ if(retval != _SUCCESS)
++ {
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("wlanhdr_to_ethhdr: drop pkt \n"));
++ #ifdef DBG_RX_DROP_FRAME
++ DBG_871X("DBG_RX_DROP_FRAME %s wlanhdr_to_ethhdr error!\n", __FUNCTION__);
++ #endif
++ return retval;
++ }
++
++ if ((padapter->bDriverStopped ==_FALSE)&&( padapter->bSurpriseRemoved==_FALSE))
++ {
++ //indicate this recv_frame
++ RT_TRACE(_module_rtl871x_recv_c_, _drv_notice_, ("@@@@ process_recv_indicatepkts- recv_func recv_indicatepkt\n" ));
++ rtw_recv_indicatepkt(padapter, prframe);
++
++
++ }
++ else
++ {
++ RT_TRACE(_module_rtl871x_recv_c_, _drv_notice_, ("@@@@ process_recv_indicatepkts- recv_func free_indicatepkt\n" ));
++
++ RT_TRACE(_module_rtl871x_recv_c_, _drv_notice_, ("recv_func:bDriverStopped(%d) OR bSurpriseRemoved(%d)", padapter->bDriverStopped, padapter->bSurpriseRemoved));
++ retval = _FAIL;
++ return retval;
++ }
++
++ }
++
++ return retval;
++
++}
++
++int recv_func_prehandle(_adapter *padapter, union recv_frame *rframe)
++{
++ int ret = _SUCCESS;
++ struct rx_pkt_attrib *pattrib = &rframe->u.hdr.attrib;
++ struct recv_priv *precvpriv = &padapter->recvpriv;
++ _queue *pfree_recv_queue = &padapter->recvpriv.free_recv_queue;
++
++#ifdef CONFIG_MP_INCLUDED
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++#endif //CONFIG_MP_INCLUDED
++
++#ifdef CONFIG_MP_INCLUDED
++ if ((check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE))//&&(padapter->mppriv.check_mp_pkt == 0))
++ {
++ if (pattrib->crc_err == 1)
++ padapter->mppriv.rx_crcerrpktcount++;
++ else
++ padapter->mppriv.rx_pktcount++;
++
++ if (check_fwstate(pmlmepriv, WIFI_MP_LPBK_STATE) == _FALSE) {
++ RT_TRACE(_module_rtl871x_recv_c_, _drv_alert_, ("MP - Not in loopback mode , drop pkt \n"));
++ ret = _FAIL;
++ rtw_free_recvframe(rframe, pfree_recv_queue);//free this recv_frame
++ goto exit;
++ }
++ }
++#endif
++
++ //check the frame crtl field and decache
++ ret = validate_recv_frame(padapter, rframe);
++ if (ret != _SUCCESS)
++ {
++ RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("recv_func: validate_recv_frame fail! drop pkt\n"));
++ rtw_free_recvframe(rframe, pfree_recv_queue);//free this recv_frame
++ goto exit;
++ }
++
++exit:
++ return ret;
++}
++
++int recv_func_posthandle(_adapter *padapter, union recv_frame *prframe)
++{
++ int ret = _SUCCESS;
++ union recv_frame *orig_prframe = prframe;
++ struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib;
++ struct recv_priv *precvpriv = &padapter->recvpriv;
++ _queue *pfree_recv_queue = &padapter->recvpriv.free_recv_queue;
++
++#ifdef CONFIG_MP_INCLUDED
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++#endif //CONFIG_MP_INCLUDED
++
++#ifdef CONFIG_TDLS
++ u8 *psnap_type, *pcategory;
++ struct sta_info *ptdls_sta = NULL;
++#endif //CONFIG_TDLS
++
++
++ // DATA FRAME
++ rtw_led_control(padapter, LED_CTL_RX);
++
++ prframe = decryptor(padapter, prframe);
++ if (prframe == NULL) {
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("decryptor: drop pkt\n"));
++ #ifdef DBG_RX_DROP_FRAME
++ DBG_871X("DBG_RX_DROP_FRAME %s decryptor: drop pkt\n", __FUNCTION__);
++ #endif
++ ret = _FAIL;
++ goto _recv_data_drop;
++ }
++
++#if 0
++ if ( padapter->adapter_type == PRIMARY_ADAPTER )
++ {
++ DBG_871X("+++\n");
++ {
++ int i;
++ u8 *ptr = get_recvframe_data(prframe);
++ for(i=0; i<140;i=i+8)
++ DBG_871X("%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:", *(ptr+i),
++ *(ptr+i+1), *(ptr+i+2) ,*(ptr+i+3) ,*(ptr+i+4),*(ptr+i+5), *(ptr+i+6), *(ptr+i+7));
++
++ }
++ DBG_871X("---\n");
++ }
++#endif //RTK_DMP_PLATFORM
++
++#ifdef CONFIG_TDLS
++ //check TDLS frame
++ psnap_type = get_recvframe_data(orig_prframe);
++ psnap_type+=pattrib->hdrlen + pattrib->iv_len+SNAP_SIZE;
++ pcategory = psnap_type + ETH_TYPE_LEN + PAYLOAD_TYPE_LEN;
++
++ if((_rtw_memcmp(psnap_type, SNAP_ETH_TYPE_TDLS, ETH_TYPE_LEN)) &&
++ ((*pcategory==RTW_WLAN_CATEGORY_TDLS) || (*pcategory==RTW_WLAN_CATEGORY_P2P))){
++ ret = OnTDLS(padapter, prframe); //all of functions will return _FAIL
++ goto _exit_recv_func;
++ }
++#endif //CONFIG_TDLS
++
++ prframe = recvframe_chk_defrag(padapter, prframe);
++ if(prframe==NULL) {
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("recvframe_chk_defrag: drop pkt\n"));
++ #ifdef DBG_RX_DROP_FRAME
++ DBG_871X("DBG_RX_DROP_FRAME %s recvframe_chk_defrag: drop pkt\n", __FUNCTION__);
++ #endif
++ goto _recv_data_drop;
++ }
++
++ prframe=portctrl(padapter, prframe);
++ if (prframe == NULL) {
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("portctrl: drop pkt \n"));
++ #ifdef DBG_RX_DROP_FRAME
++ DBG_871X("DBG_RX_DROP_FRAME %s portctrl: drop pkt\n", __FUNCTION__);
++ #endif
++ ret = _FAIL;
++ goto _recv_data_drop;
++ }
++
++#ifdef CONFIG_TDLS
++ if(padapter->tdlsinfo.setup_state == TDLS_LINKED_STATE)
++ ptdls_sta = rtw_get_stainfo(&padapter->stapriv, pattrib->src);
++ count_rx_stats(padapter, prframe, ptdls_sta);
++#else
++ count_rx_stats(padapter, prframe, NULL);
++#endif //CONFIG_TDLS
++
++#ifdef CONFIG_80211N_HT
++
++ ret = process_recv_indicatepkts(padapter, prframe);
++ if (ret != _SUCCESS)
++ {
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("recv_func: process_recv_indicatepkts fail! \n"));
++ #ifdef DBG_RX_DROP_FRAME
++ DBG_871X("DBG_RX_DROP_FRAME %s recv_func: process_recv_indicatepkts fail!\n", __FUNCTION__);
++ #endif
++ rtw_free_recvframe(orig_prframe, pfree_recv_queue);//free this recv_frame
++ goto _recv_data_drop;
++ }
++
++#else // CONFIG_80211N_HT
++
++ if (!pattrib->amsdu)
++ {
++ ret = wlanhdr_to_ethhdr (prframe);
++ if (ret != _SUCCESS)
++ {
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("wlanhdr_to_ethhdr: drop pkt \n"));
++ #ifdef DBG_RX_DROP_FRAME
++ DBG_871X("DBG_RX_DROP_FRAME %s wlanhdr_to_ethhdr: drop pkt\n", __FUNCTION__);
++ #endif
++ rtw_free_recvframe(orig_prframe, pfree_recv_queue);//free this recv_frame
++ goto _recv_data_drop;
++ }
++
++ if ((padapter->bDriverStopped == _FALSE) && (padapter->bSurpriseRemoved == _FALSE))
++ {
++ RT_TRACE(_module_rtl871x_recv_c_, _drv_alert_, ("@@@@ recv_func: recv_func rtw_recv_indicatepkt\n" ));
++ //indicate this recv_frame
++ ret = rtw_recv_indicatepkt(padapter, prframe);
++ if (ret != _SUCCESS)
++ {
++ #ifdef DBG_RX_DROP_FRAME
++ DBG_871X("DBG_RX_DROP_FRAME %s rtw_recv_indicatepkt fail!\n", __FUNCTION__);
++ #endif
++ goto _recv_data_drop;
++ }
++ }
++ else
++ {
++ RT_TRACE(_module_rtl871x_recv_c_, _drv_alert_, ("@@@@ recv_func: rtw_free_recvframe\n" ));
++ RT_TRACE(_module_rtl871x_recv_c_, _drv_debug_, ("recv_func:bDriverStopped(%d) OR bSurpriseRemoved(%d)", padapter->bDriverStopped, padapter->bSurpriseRemoved));
++ #ifdef DBG_RX_DROP_FRAME
++ DBG_871X("DBG_RX_DROP_FRAME %s ecv_func:bDriverStopped(%d) OR bSurpriseRemoved(%d)\n", __FUNCTION__,
++ padapter->bDriverStopped, padapter->bSurpriseRemoved);
++ #endif
++ ret = _FAIL;
++ rtw_free_recvframe(orig_prframe, pfree_recv_queue); //free this recv_frame
++ }
++
++ }
++ else if(pattrib->amsdu==1)
++ {
++
++ ret = amsdu_to_msdu(padapter, prframe);
++ if(ret != _SUCCESS)
++ {
++ #ifdef DBG_RX_DROP_FRAME
++ DBG_871X("DBG_RX_DROP_FRAME %s amsdu_to_msdu fail\n", __FUNCTION__);
++ #endif
++ rtw_free_recvframe(orig_prframe, pfree_recv_queue);
++ goto _recv_data_drop;
++ }
++ }
++ else
++ {
++ #ifdef DBG_RX_DROP_FRAME
++ DBG_871X("DBG_RX_DROP_FRAME %s what is this condition??\n", __FUNCTION__);
++ #endif
++ goto _recv_data_drop;
++ }
++#endif // CONFIG_80211N_HT
++
++_exit_recv_func:
++ return ret;
++
++_recv_data_drop:
++ precvpriv->rx_drop++;
++ return ret;
++}
++
++
++int recv_func(_adapter *padapter, union recv_frame *rframe);
++int recv_func(_adapter *padapter, union recv_frame *rframe)
++{
++ int ret;
++ struct rx_pkt_attrib *prxattrib = &rframe->u.hdr.attrib;
++ struct recv_priv *recvpriv = &padapter->recvpriv;
++ struct security_priv *psecuritypriv=&padapter->securitypriv;
++ struct mlme_priv *mlmepriv = &padapter->mlmepriv;
++
++ /* check if need to handle uc_swdec_pending_queue*/
++ if (check_fwstate(mlmepriv, WIFI_STATION_STATE) && psecuritypriv->busetkipkey)
++ {
++ union recv_frame *pending_frame;
++ _irqL irqL;
++
++ while((pending_frame=rtw_alloc_recvframe(&padapter->recvpriv.uc_swdec_pending_queue))) {
++ if (recv_func_posthandle(padapter, pending_frame) == _SUCCESS)
++ DBG_871X("%s: dequeue uc_swdec_pending_queue\n", __func__);
++ }
++ }
++
++ ret = recv_func_prehandle(padapter, rframe);
++
++ if(ret == _SUCCESS) {
++
++ /* check if need to enqueue into uc_swdec_pending_queue*/
++ if (check_fwstate(mlmepriv, WIFI_STATION_STATE) &&
++ !IS_MCAST(prxattrib->ra) && prxattrib->encrypt>0 &&
++ (prxattrib->bdecrypted == 0 ||psecuritypriv->sw_decrypt == _TRUE) &&
++ !is_wep_enc(psecuritypriv->dot11PrivacyAlgrthm) &&
++ !psecuritypriv->busetkipkey) {
++ rtw_enqueue_recvframe(rframe, &padapter->recvpriv.uc_swdec_pending_queue);
++ DBG_871X("%s: no key, enqueue uc_swdec_pending_queue\n", __func__);
++ goto exit;
++ }
++
++ ret = recv_func_posthandle(padapter, rframe);
++ }
++
++exit:
++ return ret;
++}
++
++
++s32 rtw_recv_entry(union recv_frame *precvframe)
++{
++ _adapter *padapter;
++ struct recv_priv *precvpriv;
++ s32 ret=_SUCCESS;
++
++_func_enter_;
++
++// RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("+rtw_recv_entry\n"));
++
++ padapter = precvframe->u.hdr.adapter;
++
++ precvpriv = &padapter->recvpriv;
++
++
++ if ((ret = recv_func(padapter, precvframe)) == _FAIL)
++ {
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("rtw_recv_entry: recv_func return fail!!!\n"));
++ goto _recv_entry_drop;
++ }
++
++
++ precvpriv->rx_pkts++;
++
++_func_exit_;
++
++ return ret;
++
++_recv_entry_drop:
++
++#ifdef CONFIG_MP_INCLUDED
++ padapter->mppriv.rx_pktloss = precvpriv->rx_drop;
++#endif
++
++ //RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("_recv_entry_drop\n"));
++
++_func_exit_;
++
++ return ret;
++}
++
++#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
++void rtw_signal_stat_timer_hdl(RTW_TIMER_HDL_ARGS){
++ _adapter *adapter = (_adapter *)FunctionContext;
++ struct recv_priv *recvpriv = &adapter->recvpriv;
++
++ u32 tmp_s, tmp_q;
++ u8 avg_signal_strength = 0;
++ u8 avg_signal_qual = 0;
++ u32 num_signal_strength = 0;
++ u32 num_signal_qual = 0;
++ u8 _alpha = 3; // this value is based on converging_constant = 5000 and sampling_interval = 1000
++
++ if(adapter->recvpriv.is_signal_dbg) {
++ //update the user specific value, signal_strength_dbg, to signal_strength, rssi
++ adapter->recvpriv.signal_strength= adapter->recvpriv.signal_strength_dbg;
++ adapter->recvpriv.rssi=(s8)translate_percentage_to_dbm((u8)adapter->recvpriv.signal_strength_dbg);
++ } else {
++
++ if(recvpriv->signal_strength_data.update_req == 0) {// update_req is clear, means we got rx
++ avg_signal_strength = recvpriv->signal_strength_data.avg_val;
++ num_signal_strength = recvpriv->signal_strength_data.total_num;
++ // after avg_vals are accquired, we can re-stat the signal values
++ recvpriv->signal_strength_data.update_req = 1;
++ }
++
++ if(recvpriv->signal_qual_data.update_req == 0) {// update_req is clear, means we got rx
++ avg_signal_qual = recvpriv->signal_qual_data.avg_val;
++ num_signal_qual = recvpriv->signal_qual_data.total_num;
++ // after avg_vals are accquired, we can re-stat the signal values
++ recvpriv->signal_qual_data.update_req = 1;
++ }
++
++ if (num_signal_strength == 0) {
++ if (rtw_get_on_cur_ch_time(adapter) == 0
++ || rtw_get_passing_time_ms(rtw_get_on_cur_ch_time(adapter)) < 2 * adapter->mlmeextpriv.mlmext_info.bcn_interval
++ ) {
++ goto set_timer;
++ }
++ }
++
++ if(check_fwstate(&adapter->mlmepriv, _FW_UNDER_SURVEY) == _TRUE
++ || check_fwstate(&adapter->mlmepriv, _FW_LINKED) == _FALSE
++ ) {
++ goto set_timer;
++ }
++
++ #ifdef CONFIG_CONCURRENT_MODE
++ if (check_buddy_fwstate(adapter, _FW_UNDER_SURVEY) == _TRUE)
++ goto set_timer;
++ #endif
++
++ //update value of signal_strength, rssi, signal_qual
++ tmp_s = (avg_signal_strength+(_alpha-1)*recvpriv->signal_strength);
++ if(tmp_s %_alpha)
++ tmp_s = tmp_s/_alpha + 1;
++ else
++ tmp_s = tmp_s/_alpha;
++ if(tmp_s>100)
++ tmp_s = 100;
++
++ tmp_q = (avg_signal_qual+(_alpha-1)*recvpriv->signal_qual);
++ if(tmp_q %_alpha)
++ tmp_q = tmp_q/_alpha + 1;
++ else
++ tmp_q = tmp_q/_alpha;
++ if(tmp_q>100)
++ tmp_q = 100;
++
++ recvpriv->signal_strength = tmp_s;
++ recvpriv->rssi = (s8)translate_percentage_to_dbm(tmp_s);
++ recvpriv->signal_qual = tmp_q;
++
++ #if defined(DBG_RX_SIGNAL_DISPLAY_PROCESSING) && 1
++ DBG_871X(FUNC_ADPT_FMT" signal_strength:%3u, rssi:%3d, signal_qual:%3u"
++ ", num_signal_strength:%u, num_signal_qual:%u"
++ ", on_cur_ch_ms:%d"
++ "\n"
++ , FUNC_ADPT_ARG(adapter)
++ , recvpriv->signal_strength
++ , recvpriv->rssi
++ , recvpriv->signal_qual
++ , num_signal_strength, num_signal_qual
++ , rtw_get_on_cur_ch_time(adapter) ? rtw_get_passing_time_ms(rtw_get_on_cur_ch_time(adapter)) : 0
++ );
++ #endif
++ }
++
++set_timer:
++ rtw_set_signal_stat_timer(recvpriv);
++
++}
++#endif //CONFIG_NEW_SIGNAL_STAT_PROCESS
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/core/rtw_rf.c linux-xbian-rpi/drivers/net/wireless/rtl8192cu/core/rtw_rf.c
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/core/rtw_rf.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/core/rtw_rf.c 2015-07-28 01:20:58.305654202 +0200
+@@ -0,0 +1,94 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#define _RTW_RF_C_
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++#include <recv_osdep.h>
++#include <xmit_osdep.h>
++
++
++struct ch_freq {
++ u32 channel;
++ u32 frequency;
++};
++
++struct ch_freq ch_freq_map[] = {
++ {1, 2412},{2, 2417},{3, 2422},{4, 2427},{5, 2432},
++ {6, 2437},{7, 2442},{8, 2447},{9, 2452},{10, 2457},
++ {11, 2462},{12, 2467},{13, 2472},{14, 2484},
++ /* UNII */
++ {36, 5180},{40, 5200},{44, 5220},{48, 5240},{52, 5260},
++ {56, 5280},{60, 5300},{64, 5320},{149, 5745},{153, 5765},
++ {157, 5785},{161, 5805},{165, 5825},{167, 5835},{169, 5845},
++ {171, 5855},{173, 5865},
++ /* HiperLAN2 */
++ {100, 5500},{104, 5520},{108, 5540},{112, 5560},{116, 5580},
++ {120, 5600},{124, 5620},{128, 5640},{132, 5660},{136, 5680},
++ {140, 5700},
++ /* Japan MMAC */
++ {34, 5170},{38, 5190},{42, 5210},{46, 5230},
++ /* Japan */
++ {184, 4920},{188, 4940},{192, 4960},{196, 4980},
++ {208, 5040},/* Japan, means J08 */
++ {212, 5060},/* Japan, means J12 */
++ {216, 5080},/* Japan, means J16 */
++};
++
++int ch_freq_map_num = (sizeof(ch_freq_map) / sizeof(struct ch_freq));
++
++u32 rtw_ch2freq(u32 channel)
++{
++ u8 i;
++ u32 freq = 0;
++
++ for (i = 0; i < ch_freq_map_num; i++)
++ {
++ if (channel == ch_freq_map[i].channel)
++ {
++ freq = ch_freq_map[i].frequency;
++ break;
++ }
++ }
++ if (i == ch_freq_map_num)
++ freq = 2412;
++
++ return freq;
++}
++
++u32 rtw_freq2ch(u32 freq)
++{
++ u8 i;
++ u32 ch = 0;
++
++ for (i = 0; i < ch_freq_map_num; i++)
++ {
++ if (freq == ch_freq_map[i].frequency)
++ {
++ ch = ch_freq_map[i].channel;
++ break;
++ }
++ }
++ if (i == ch_freq_map_num)
++ ch = 1;
++
++ return ch;
++}
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/core/rtw_security.c linux-xbian-rpi/drivers/net/wireless/rtl8192cu/core/rtw_security.c
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/core/rtw_security.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/core/rtw_security.c 2015-07-28 01:20:58.305654202 +0200
+@@ -0,0 +1,3114 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#define _RTW_SECURITY_C_
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++#include <wifi.h>
++#include <osdep_intf.h>
++
++
++//=====WEP related=====
++
++#define CRC32_POLY 0x04c11db7
++
++struct arc4context
++{
++ u32 x;
++ u32 y;
++ u8 state[256];
++};
++
++
++static void arcfour_init(struct arc4context *parc4ctx, u8 * key,u32 key_len)
++{
++ u32 t, u;
++ u32 keyindex;
++ u32 stateindex;
++ u8 * state;
++ u32 counter;
++_func_enter_;
++ state = parc4ctx->state;
++ parc4ctx->x = 0;
++ parc4ctx->y = 0;
++ for (counter = 0; counter < 256; counter++)
++ state[counter] = (u8)counter;
++ keyindex = 0;
++ stateindex = 0;
++ for (counter = 0; counter < 256; counter++)
++ {
++ t = state[counter];
++ stateindex = (stateindex + key[keyindex] + t) & 0xff;
++ u = state[stateindex];
++ state[stateindex] = (u8)t;
++ state[counter] = (u8)u;
++ if (++keyindex >= key_len)
++ keyindex = 0;
++ }
++_func_exit_;
++}
++static u32 arcfour_byte( struct arc4context *parc4ctx)
++{
++ u32 x;
++ u32 y;
++ u32 sx, sy;
++ u8 * state;
++_func_enter_;
++ state = parc4ctx->state;
++ x = (parc4ctx->x + 1) & 0xff;
++ sx = state[x];
++ y = (sx + parc4ctx->y) & 0xff;
++ sy = state[y];
++ parc4ctx->x = x;
++ parc4ctx->y = y;
++ state[y] = (u8)sx;
++ state[x] = (u8)sy;
++_func_exit_;
++ return state[(sx + sy) & 0xff];
++}
++
++
++static void arcfour_encrypt( struct arc4context *parc4ctx,
++ u8 * dest,
++ u8 * src,
++ u32 len)
++{
++ u32 i;
++_func_enter_;
++ for (i = 0; i < len; i++)
++ dest[i] = src[i] ^ (unsigned char)arcfour_byte(parc4ctx);
++_func_exit_;
++}
++
++static sint bcrc32initialized = 0;
++static u32 crc32_table[256];
++
++
++static u8 crc32_reverseBit( u8 data)
++{
++ return( (u8)((data<<7)&0x80) | ((data<<5)&0x40) | ((data<<3)&0x20) | ((data<<1)&0x10) | ((data>>1)&0x08) | ((data>>3)&0x04) | ((data>>5)&0x02) | ((data>>7)&0x01) );
++}
++
++static void crc32_init(void)
++{
++_func_enter_;
++ if (bcrc32initialized == 1)
++ goto exit;
++ else{
++ sint i, j;
++ u32 c;
++ u8 *p=(u8 *)&c, *p1;
++ u8 k;
++
++ c = 0x12340000;
++
++ for (i = 0; i < 256; ++i)
++ {
++ k = crc32_reverseBit((u8)i);
++ for (c = ((u32)k) << 24, j = 8; j > 0; --j){
++ c = c & 0x80000000 ? (c << 1) ^ CRC32_POLY : (c << 1);
++ }
++ p1 = (u8 *)&crc32_table[i];
++
++ p1[0] = crc32_reverseBit(p[3]);
++ p1[1] = crc32_reverseBit(p[2]);
++ p1[2] = crc32_reverseBit(p[1]);
++ p1[3] = crc32_reverseBit(p[0]);
++ }
++ bcrc32initialized= 1;
++ }
++exit:
++_func_exit_;
++}
++
++static u32 getcrc32(u8 *buf, sint len)
++{
++ u8 *p;
++ u32 crc;
++_func_enter_;
++ if (bcrc32initialized == 0) crc32_init();
++
++ crc = 0xffffffff; /* preload shift register, per CRC-32 spec */
++
++ for (p = buf; len > 0; ++p, --len)
++ {
++ crc = crc32_table[ (crc ^ *p) & 0xff] ^ (crc >> 8);
++ }
++_func_exit_;
++ return ~crc; /* transmit complement, per CRC-32 spec */
++}
++
++
++/*
++ Need to consider the fragment situation
++*/
++void rtw_wep_encrypt(_adapter *padapter, u8 *pxmitframe)
++{ // exclude ICV
++
++ unsigned char crc[4];
++ struct arc4context mycontext;
++
++ sint curfragnum,length;
++ u32 keylength;
++
++ u8 *pframe, *payload,*iv; //,*wepkey
++ u8 wepkey[16];
++ struct pkt_attrib *pattrib = &((struct xmit_frame*)pxmitframe)->attrib;
++ struct security_priv *psecuritypriv=&padapter->securitypriv;
++ struct xmit_priv *pxmitpriv=&padapter->xmitpriv;
++
++_func_enter_;
++
++
++ if(((struct xmit_frame*)pxmitframe)->buf_addr==NULL)
++ return;
++
++#ifdef CONFIG_USB_TX_AGGREGATION
++ pframe = ((struct xmit_frame*)pxmitframe)->buf_addr + TXDESC_SIZE +
++ (((struct xmit_frame*)pxmitframe)->pkt_offset * PACKET_OFFSET_SZ);
++#else
++ pframe = ((struct xmit_frame*)pxmitframe)->buf_addr + TXDESC_OFFSET;
++#endif
++
++ //start to encrypt each fragment
++ if((pattrib->encrypt==_WEP40_)||(pattrib->encrypt==_WEP104_))
++ {
++ keylength=psecuritypriv->dot11DefKeylen[psecuritypriv->dot11PrivacyKeyIndex];
++
++ for(curfragnum=0;curfragnum<pattrib->nr_frags;curfragnum++)
++ {
++ iv=pframe+pattrib->hdrlen;
++ _rtw_memcpy(&wepkey[0], iv, 3);
++ _rtw_memcpy(&wepkey[3], &psecuritypriv->dot11DefKey[psecuritypriv->dot11PrivacyKeyIndex].skey[0],keylength);
++ payload=pframe+pattrib->iv_len+pattrib->hdrlen;
++
++ if((curfragnum+1)==pattrib->nr_frags)
++ { //the last fragment
++
++ length=pattrib->last_txcmdsz-pattrib->hdrlen-pattrib->iv_len- pattrib->icv_len;
++
++ *((u32 *)crc)=cpu_to_le32(getcrc32(payload,length));
++
++ arcfour_init(&mycontext, wepkey,3+keylength);
++ arcfour_encrypt(&mycontext, payload, payload, length);
++ arcfour_encrypt(&mycontext, payload+length, crc, 4);
++
++ }
++ else
++ {
++ length=pxmitpriv->frag_len-pattrib->hdrlen-pattrib->iv_len-pattrib->icv_len ;
++ *((u32 *)crc)=cpu_to_le32(getcrc32(payload,length));
++ arcfour_init(&mycontext, wepkey,3+keylength);
++ arcfour_encrypt(&mycontext, payload, payload, length);
++ arcfour_encrypt(&mycontext, payload+length, crc, 4);
++
++ pframe+=pxmitpriv->frag_len;
++ pframe=(u8 *)RND4((SIZE_PTR)(pframe));
++
++ }
++
++ }
++
++ }
++
++_func_exit_;
++
++}
++
++void rtw_wep_decrypt(_adapter *padapter, u8 *precvframe)
++{
++ // exclude ICV
++ u8 crc[4];
++ struct arc4context mycontext;
++ sint length;
++ u32 keylength;
++ u8 *pframe, *payload,*iv,wepkey[16];
++ u8 keyindex;
++ struct rx_pkt_attrib *prxattrib = &(((union recv_frame*)precvframe)->u.hdr.attrib);
++ struct security_priv *psecuritypriv=&padapter->securitypriv;
++
++_func_enter_;
++
++ pframe=(unsigned char *)((union recv_frame*)precvframe)->u.hdr.rx_data;
++
++ //start to decrypt recvframe
++ if((prxattrib->encrypt==_WEP40_)||(prxattrib->encrypt==_WEP104_))
++ {
++ iv=pframe+prxattrib->hdrlen;
++ //keyindex=(iv[3]&0x3);
++ keyindex = prxattrib->key_index;
++ keylength=psecuritypriv->dot11DefKeylen[keyindex];
++ _rtw_memcpy(&wepkey[0], iv, 3);
++ //_rtw_memcpy(&wepkey[3], &psecuritypriv->dot11DefKey[psecuritypriv->dot11PrivacyKeyIndex].skey[0],keylength);
++ _rtw_memcpy(&wepkey[3], &psecuritypriv->dot11DefKey[keyindex].skey[0],keylength);
++ length= ((union recv_frame *)precvframe)->u.hdr.len-prxattrib->hdrlen-prxattrib->iv_len;
++
++ payload=pframe+prxattrib->iv_len+prxattrib->hdrlen;
++
++ //decrypt payload include icv
++ arcfour_init(&mycontext, wepkey,3+keylength);
++ arcfour_encrypt(&mycontext, payload, payload, length);
++
++ //calculate icv and compare the icv
++ *((u32 *)crc)=le32_to_cpu(getcrc32(payload,length-4));
++
++ if(crc[3]!=payload[length-1] || crc[2]!=payload[length-2] || crc[1]!=payload[length-3] || crc[0]!=payload[length-4])
++ {
++ RT_TRACE(_module_rtl871x_security_c_,_drv_err_,("rtw_wep_decrypt:icv error crc[3](%x)!=payload[length-1](%x) || crc[2](%x)!=payload[length-2](%x) || crc[1](%x)!=payload[length-3](%x) || crc[0](%x)!=payload[length-4](%x)\n",
++ crc[3],payload[length-1],crc[2],payload[length-2],crc[1],payload[length-3],crc[0],payload[length-4]));
++ }
++
++ }
++
++_func_exit_;
++
++ return;
++
++}
++
++//3 =====TKIP related=====
++
++static u32 secmicgetuint32( u8 * p )
++// Convert from Byte[] to Us4Byte32 in a portable way
++{
++ s32 i;
++ u32 res = 0;
++_func_enter_;
++ for( i=0; i<4; i++ )
++ {
++ res |= ((u32)(*p++)) << (8*i);
++ }
++_func_exit_;
++ return res;
++}
++
++static void secmicputuint32( u8 * p, u32 val )
++// Convert from Us4Byte32 to Byte[] in a portable way
++{
++ long i;
++_func_enter_;
++ for( i=0; i<4; i++ )
++ {
++ *p++ = (u8) (val & 0xff);
++ val >>= 8;
++ }
++_func_exit_;
++}
++
++static void secmicclear(struct mic_data *pmicdata)
++{
++// Reset the state to the empty message.
++_func_enter_;
++ pmicdata->L = pmicdata->K0;
++ pmicdata->R = pmicdata->K1;
++ pmicdata->nBytesInM = 0;
++ pmicdata->M = 0;
++_func_exit_;
++}
++
++void rtw_secmicsetkey(struct mic_data *pmicdata, u8 * key )
++{
++ // Set the key
++_func_enter_;
++ pmicdata->K0 = secmicgetuint32( key );
++ pmicdata->K1 = secmicgetuint32( key + 4 );
++ // and reset the message
++ secmicclear(pmicdata);
++_func_exit_;
++}
++
++void rtw_secmicappendbyte(struct mic_data *pmicdata, u8 b )
++{
++_func_enter_;
++ // Append the byte to our word-sized buffer
++ pmicdata->M |= ((unsigned long)b) << (8*pmicdata->nBytesInM);
++ pmicdata->nBytesInM++;
++ // Process the word if it is full.
++ if( pmicdata->nBytesInM >= 4 )
++ {
++ pmicdata->L ^= pmicdata->M;
++ pmicdata->R ^= ROL32( pmicdata->L, 17 );
++ pmicdata->L += pmicdata->R;
++ pmicdata->R ^= ((pmicdata->L & 0xff00ff00) >> 8) | ((pmicdata->L & 0x00ff00ff) << 8);
++ pmicdata->L += pmicdata->R;
++ pmicdata->R ^= ROL32( pmicdata->L, 3 );
++ pmicdata->L += pmicdata->R;
++ pmicdata->R ^= ROR32( pmicdata->L, 2 );
++ pmicdata->L += pmicdata->R;
++ // Clear the buffer
++ pmicdata->M = 0;
++ pmicdata->nBytesInM = 0;
++ }
++_func_exit_;
++}
++
++void rtw_secmicappend(struct mic_data *pmicdata, u8 * src, u32 nbytes )
++{
++_func_enter_;
++ // This is simple
++ while( nbytes > 0 )
++ {
++ rtw_secmicappendbyte(pmicdata, *src++ );
++ nbytes--;
++ }
++_func_exit_;
++}
++
++void rtw_secgetmic(struct mic_data *pmicdata, u8 * dst )
++{
++_func_enter_;
++ // Append the minimum padding
++ rtw_secmicappendbyte(pmicdata, 0x5a );
++ rtw_secmicappendbyte(pmicdata, 0 );
++ rtw_secmicappendbyte(pmicdata, 0 );
++ rtw_secmicappendbyte(pmicdata, 0 );
++ rtw_secmicappendbyte(pmicdata, 0 );
++ // and then zeroes until the length is a multiple of 4
++ while( pmicdata->nBytesInM != 0 )
++ {
++ rtw_secmicappendbyte(pmicdata, 0 );
++ }
++ // The appendByte function has already computed the result.
++ secmicputuint32( dst, pmicdata->L );
++ secmicputuint32( dst+4, pmicdata->R );
++ // Reset to the empty message.
++ secmicclear(pmicdata);
++_func_exit_;
++}
++
++
++void rtw_seccalctkipmic(u8 * key,u8 *header,u8 *data,u32 data_len,u8 *mic_code, u8 pri)
++{
++
++ struct mic_data micdata;
++ u8 priority[4]={0x0,0x0,0x0,0x0};
++_func_enter_;
++ rtw_secmicsetkey(&micdata, key);
++ priority[0]=pri;
++
++ /* Michael MIC pseudo header: DA, SA, 3 x 0, Priority */
++ if(header[1]&1){ //ToDS==1
++ rtw_secmicappend(&micdata, &header[16], 6); //DA
++ if(header[1]&2) //From Ds==1
++ rtw_secmicappend(&micdata, &header[24], 6);
++ else
++ rtw_secmicappend(&micdata, &header[10], 6);
++ }
++ else{ //ToDS==0
++ rtw_secmicappend(&micdata, &header[4], 6); //DA
++ if(header[1]&2) //From Ds==1
++ rtw_secmicappend(&micdata, &header[16], 6);
++ else
++ rtw_secmicappend(&micdata, &header[10], 6);
++
++ }
++ rtw_secmicappend(&micdata, &priority[0], 4);
++
++
++ rtw_secmicappend(&micdata, data, data_len);
++
++ rtw_secgetmic(&micdata,mic_code);
++_func_exit_;
++}
++
++
++
++
++/* macros for extraction/creation of unsigned char/unsigned short values */
++#define RotR1(v16) ((((v16) >> 1) & 0x7FFF) ^ (((v16) & 1) << 15))
++#define Lo8(v16) ((u8)( (v16) & 0x00FF))
++#define Hi8(v16) ((u8)(((v16) >> 8) & 0x00FF))
++#define Lo16(v32) ((u16)( (v32) & 0xFFFF))
++#define Hi16(v32) ((u16)(((v32) >>16) & 0xFFFF))
++#define Mk16(hi,lo) ((lo) ^ (((u16)(hi)) << 8))
++
++/* select the Nth 16-bit word of the temporal key unsigned char array TK[] */
++#define TK16(N) Mk16(tk[2*(N)+1],tk[2*(N)])
++
++/* S-box lookup: 16 bits --> 16 bits */
++#define _S_(v16) (Sbox1[0][Lo8(v16)] ^ Sbox1[1][Hi8(v16)])
++
++/* fixed algorithm "parameters" */
++#define PHASE1_LOOP_CNT 8 /* this needs to be "big enough" */
++#define TA_SIZE 6 /* 48-bit transmitter address */
++#define TK_SIZE 16 /* 128-bit temporal key */
++#define P1K_SIZE 10 /* 80-bit Phase1 key */
++#define RC4_KEY_SIZE 16 /* 128-bit RC4KEY (104 bits unknown) */
++
++
++/* 2-unsigned char by 2-unsigned char subset of the full AES S-box table */
++static const unsigned short Sbox1[2][256]= /* Sbox for hash (can be in ROM) */
++{ {
++ 0xC6A5,0xF884,0xEE99,0xF68D,0xFF0D,0xD6BD,0xDEB1,0x9154,
++ 0x6050,0x0203,0xCEA9,0x567D,0xE719,0xB562,0x4DE6,0xEC9A,
++ 0x8F45,0x1F9D,0x8940,0xFA87,0xEF15,0xB2EB,0x8EC9,0xFB0B,
++ 0x41EC,0xB367,0x5FFD,0x45EA,0x23BF,0x53F7,0xE496,0x9B5B,
++ 0x75C2,0xE11C,0x3DAE,0x4C6A,0x6C5A,0x7E41,0xF502,0x834F,
++ 0x685C,0x51F4,0xD134,0xF908,0xE293,0xAB73,0x6253,0x2A3F,
++ 0x080C,0x9552,0x4665,0x9D5E,0x3028,0x37A1,0x0A0F,0x2FB5,
++ 0x0E09,0x2436,0x1B9B,0xDF3D,0xCD26,0x4E69,0x7FCD,0xEA9F,
++ 0x121B,0x1D9E,0x5874,0x342E,0x362D,0xDCB2,0xB4EE,0x5BFB,
++ 0xA4F6,0x764D,0xB761,0x7DCE,0x527B,0xDD3E,0x5E71,0x1397,
++ 0xA6F5,0xB968,0x0000,0xC12C,0x4060,0xE31F,0x79C8,0xB6ED,
++ 0xD4BE,0x8D46,0x67D9,0x724B,0x94DE,0x98D4,0xB0E8,0x854A,
++ 0xBB6B,0xC52A,0x4FE5,0xED16,0x86C5,0x9AD7,0x6655,0x1194,
++ 0x8ACF,0xE910,0x0406,0xFE81,0xA0F0,0x7844,0x25BA,0x4BE3,
++ 0xA2F3,0x5DFE,0x80C0,0x058A,0x3FAD,0x21BC,0x7048,0xF104,
++ 0x63DF,0x77C1,0xAF75,0x4263,0x2030,0xE51A,0xFD0E,0xBF6D,
++ 0x814C,0x1814,0x2635,0xC32F,0xBEE1,0x35A2,0x88CC,0x2E39,
++ 0x9357,0x55F2,0xFC82,0x7A47,0xC8AC,0xBAE7,0x322B,0xE695,
++ 0xC0A0,0x1998,0x9ED1,0xA37F,0x4466,0x547E,0x3BAB,0x0B83,
++ 0x8CCA,0xC729,0x6BD3,0x283C,0xA779,0xBCE2,0x161D,0xAD76,
++ 0xDB3B,0x6456,0x744E,0x141E,0x92DB,0x0C0A,0x486C,0xB8E4,
++ 0x9F5D,0xBD6E,0x43EF,0xC4A6,0x39A8,0x31A4,0xD337,0xF28B,
++ 0xD532,0x8B43,0x6E59,0xDAB7,0x018C,0xB164,0x9CD2,0x49E0,
++ 0xD8B4,0xACFA,0xF307,0xCF25,0xCAAF,0xF48E,0x47E9,0x1018,
++ 0x6FD5,0xF088,0x4A6F,0x5C72,0x3824,0x57F1,0x73C7,0x9751,
++ 0xCB23,0xA17C,0xE89C,0x3E21,0x96DD,0x61DC,0x0D86,0x0F85,
++ 0xE090,0x7C42,0x71C4,0xCCAA,0x90D8,0x0605,0xF701,0x1C12,
++ 0xC2A3,0x6A5F,0xAEF9,0x69D0,0x1791,0x9958,0x3A27,0x27B9,
++ 0xD938,0xEB13,0x2BB3,0x2233,0xD2BB,0xA970,0x0789,0x33A7,
++ 0x2DB6,0x3C22,0x1592,0xC920,0x8749,0xAAFF,0x5078,0xA57A,
++ 0x038F,0x59F8,0x0980,0x1A17,0x65DA,0xD731,0x84C6,0xD0B8,
++ 0x82C3,0x29B0,0x5A77,0x1E11,0x7BCB,0xA8FC,0x6DD6,0x2C3A,
++ },
++
++
++ { /* second half of table is unsigned char-reversed version of first! */
++ 0xA5C6,0x84F8,0x99EE,0x8DF6,0x0DFF,0xBDD6,0xB1DE,0x5491,
++ 0x5060,0x0302,0xA9CE,0x7D56,0x19E7,0x62B5,0xE64D,0x9AEC,
++ 0x458F,0x9D1F,0x4089,0x87FA,0x15EF,0xEBB2,0xC98E,0x0BFB,
++ 0xEC41,0x67B3,0xFD5F,0xEA45,0xBF23,0xF753,0x96E4,0x5B9B,
++ 0xC275,0x1CE1,0xAE3D,0x6A4C,0x5A6C,0x417E,0x02F5,0x4F83,
++ 0x5C68,0xF451,0x34D1,0x08F9,0x93E2,0x73AB,0x5362,0x3F2A,
++ 0x0C08,0x5295,0x6546,0x5E9D,0x2830,0xA137,0x0F0A,0xB52F,
++ 0x090E,0x3624,0x9B1B,0x3DDF,0x26CD,0x694E,0xCD7F,0x9FEA,
++ 0x1B12,0x9E1D,0x7458,0x2E34,0x2D36,0xB2DC,0xEEB4,0xFB5B,
++ 0xF6A4,0x4D76,0x61B7,0xCE7D,0x7B52,0x3EDD,0x715E,0x9713,
++ 0xF5A6,0x68B9,0x0000,0x2CC1,0x6040,0x1FE3,0xC879,0xEDB6,
++ 0xBED4,0x468D,0xD967,0x4B72,0xDE94,0xD498,0xE8B0,0x4A85,
++ 0x6BBB,0x2AC5,0xE54F,0x16ED,0xC586,0xD79A,0x5566,0x9411,
++ 0xCF8A,0x10E9,0x0604,0x81FE,0xF0A0,0x4478,0xBA25,0xE34B,
++ 0xF3A2,0xFE5D,0xC080,0x8A05,0xAD3F,0xBC21,0x4870,0x04F1,
++ 0xDF63,0xC177,0x75AF,0x6342,0x3020,0x1AE5,0x0EFD,0x6DBF,
++ 0x4C81,0x1418,0x3526,0x2FC3,0xE1BE,0xA235,0xCC88,0x392E,
++ 0x5793,0xF255,0x82FC,0x477A,0xACC8,0xE7BA,0x2B32,0x95E6,
++ 0xA0C0,0x9819,0xD19E,0x7FA3,0x6644,0x7E54,0xAB3B,0x830B,
++ 0xCA8C,0x29C7,0xD36B,0x3C28,0x79A7,0xE2BC,0x1D16,0x76AD,
++ 0x3BDB,0x5664,0x4E74,0x1E14,0xDB92,0x0A0C,0x6C48,0xE4B8,
++ 0x5D9F,0x6EBD,0xEF43,0xA6C4,0xA839,0xA431,0x37D3,0x8BF2,
++ 0x32D5,0x438B,0x596E,0xB7DA,0x8C01,0x64B1,0xD29C,0xE049,
++ 0xB4D8,0xFAAC,0x07F3,0x25CF,0xAFCA,0x8EF4,0xE947,0x1810,
++ 0xD56F,0x88F0,0x6F4A,0x725C,0x2438,0xF157,0xC773,0x5197,
++ 0x23CB,0x7CA1,0x9CE8,0x213E,0xDD96,0xDC61,0x860D,0x850F,
++ 0x90E0,0x427C,0xC471,0xAACC,0xD890,0x0506,0x01F7,0x121C,
++ 0xA3C2,0x5F6A,0xF9AE,0xD069,0x9117,0x5899,0x273A,0xB927,
++ 0x38D9,0x13EB,0xB32B,0x3322,0xBBD2,0x70A9,0x8907,0xA733,
++ 0xB62D,0x223C,0x9215,0x20C9,0x4987,0xFFAA,0x7850,0x7AA5,
++ 0x8F03,0xF859,0x8009,0x171A,0xDA65,0x31D7,0xC684,0xB8D0,
++ 0xC382,0xB029,0x775A,0x111E,0xCB7B,0xFCA8,0xD66D,0x3A2C,
++ }
++};
++
++ /*
++**********************************************************************
++* Routine: Phase 1 -- generate P1K, given TA, TK, IV32
++*
++* Inputs:
++* tk[] = temporal key [128 bits]
++* ta[] = transmitter's MAC address [ 48 bits]
++* iv32 = upper 32 bits of IV [ 32 bits]
++* Output:
++* p1k[] = Phase 1 key [ 80 bits]
++*
++* Note:
++* This function only needs to be called every 2**16 packets,
++* although in theory it could be called every packet.
++*
++**********************************************************************
++*/
++static void phase1(u16 *p1k,const u8 *tk,const u8 *ta,u32 iv32)
++{
++ sint i;
++_func_enter_;
++ /* Initialize the 80 bits of P1K[] from IV32 and TA[0..5] */
++ p1k[0] = Lo16(iv32);
++ p1k[1] = Hi16(iv32);
++ p1k[2] = Mk16(ta[1],ta[0]); /* use TA[] as little-endian */
++ p1k[3] = Mk16(ta[3],ta[2]);
++ p1k[4] = Mk16(ta[5],ta[4]);
++
++ /* Now compute an unbalanced Feistel cipher with 80-bit block */
++ /* size on the 80-bit block P1K[], using the 128-bit key TK[] */
++ for (i=0; i < PHASE1_LOOP_CNT ;i++)
++ { /* Each add operation here is mod 2**16 */
++ p1k[0] += _S_(p1k[4] ^ TK16((i&1)+0));
++ p1k[1] += _S_(p1k[0] ^ TK16((i&1)+2));
++ p1k[2] += _S_(p1k[1] ^ TK16((i&1)+4));
++ p1k[3] += _S_(p1k[2] ^ TK16((i&1)+6));
++ p1k[4] += _S_(p1k[3] ^ TK16((i&1)+0));
++ p1k[4] += (unsigned short)i; /* avoid "slide attacks" */
++ }
++_func_exit_;
++}
++
++
++/*
++**********************************************************************
++* Routine: Phase 2 -- generate RC4KEY, given TK, P1K, IV16
++*
++* Inputs:
++* tk[] = Temporal key [128 bits]
++* p1k[] = Phase 1 output key [ 80 bits]
++* iv16 = low 16 bits of IV counter [ 16 bits]
++* Output:
++* rc4key[] = the key used to encrypt the packet [128 bits]
++*
++* Note:
++* The value {TA,IV32,IV16} for Phase1/Phase2 must be unique
++* across all packets using the same key TK value. Then, for a
++* given value of TK[], this TKIP48 construction guarantees that
++* the final RC4KEY value is unique across all packets.
++*
++* Suggested implementation optimization: if PPK[] is "overlaid"
++* appropriately on RC4KEY[], there is no need for the final
++* for loop below that copies the PPK[] result into RC4KEY[].
++*
++**********************************************************************
++*/
++static void phase2(u8 *rc4key,const u8 *tk,const u16 *p1k,u16 iv16)
++{
++ sint i;
++ u16 PPK[6]; /* temporary key for mixing */
++_func_enter_;
++ /* Note: all adds in the PPK[] equations below are mod 2**16 */
++ for (i=0;i<5;i++) PPK[i]=p1k[i]; /* first, copy P1K to PPK */
++ PPK[5] = p1k[4] +iv16; /* next, add in IV16 */
++
++ /* Bijective non-linear mixing of the 96 bits of PPK[0..5] */
++ PPK[0] += _S_(PPK[5] ^ TK16(0)); /* Mix key in each "round" */
++ PPK[1] += _S_(PPK[0] ^ TK16(1));
++ PPK[2] += _S_(PPK[1] ^ TK16(2));
++ PPK[3] += _S_(PPK[2] ^ TK16(3));
++ PPK[4] += _S_(PPK[3] ^ TK16(4));
++ PPK[5] += _S_(PPK[4] ^ TK16(5)); /* Total # S-box lookups == 6 */
++
++ /* Final sweep: bijective, "linear". Rotates kill LSB correlations */
++ PPK[0] += RotR1(PPK[5] ^ TK16(6));
++ PPK[1] += RotR1(PPK[0] ^ TK16(7)); /* Use all of TK[] in Phase2 */
++ PPK[2] += RotR1(PPK[1]);
++ PPK[3] += RotR1(PPK[2]);
++ PPK[4] += RotR1(PPK[3]);
++ PPK[5] += RotR1(PPK[4]);
++ /* Note: At this point, for a given key TK[0..15], the 96-bit output */
++ /* value PPK[0..5] is guaranteed to be unique, as a function */
++ /* of the 96-bit "input" value {TA,IV32,IV16}. That is, P1K */
++ /* is now a keyed permutation of {TA,IV32,IV16}. */
++
++ /* Set RC4KEY[0..3], which includes "cleartext" portion of RC4 key */
++ rc4key[0] = Hi8(iv16); /* RC4KEY[0..2] is the WEP IV */
++ rc4key[1] =(Hi8(iv16) | 0x20) & 0x7F; /* Help avoid weak (FMS) keys */
++ rc4key[2] = Lo8(iv16);
++ rc4key[3] = Lo8((PPK[5] ^ TK16(0)) >> 1);
++
++
++ /* Copy 96 bits of PPK[0..5] to RC4KEY[4..15] (little-endian) */
++ for (i=0;i<6;i++)
++ {
++ rc4key[4+2*i] = Lo8(PPK[i]);
++ rc4key[5+2*i] = Hi8(PPK[i]);
++ }
++_func_exit_;
++}
++
++
++//The hlen isn't include the IV
++u32 rtw_tkip_encrypt(_adapter *padapter, u8 *pxmitframe)
++{ // exclude ICV
++ u16 pnl;
++ u32 pnh;
++ u8 rc4key[16];
++ u8 ttkey[16];
++ u8 crc[4];
++ struct arc4context mycontext;
++ sint curfragnum,length;
++ u32 prwskeylen;
++
++ u8 *pframe, *payload,*iv,*prwskey;
++ union pn48 dot11txpn;
++ struct sta_info *stainfo;
++ struct pkt_attrib *pattrib = &((struct xmit_frame *)pxmitframe)->attrib;
++ struct security_priv *psecuritypriv=&padapter->securitypriv;
++ struct xmit_priv *pxmitpriv=&padapter->xmitpriv;
++ u32 res=_SUCCESS;
++_func_enter_;
++
++ if(((struct xmit_frame*)pxmitframe)->buf_addr==NULL)
++ return _FAIL;
++
++#ifdef CONFIG_USB_TX_AGGREGATION
++ pframe = ((struct xmit_frame*)pxmitframe)->buf_addr + TXDESC_SIZE +
++ (((struct xmit_frame*)pxmitframe)->pkt_offset * PACKET_OFFSET_SZ);
++#else
++ pframe = ((struct xmit_frame*)pxmitframe)->buf_addr + TXDESC_OFFSET;
++#endif
++
++ //4 start to encrypt each fragment
++ if(pattrib->encrypt==_TKIP_){
++
++ if(pattrib->psta)
++ {
++ stainfo = pattrib->psta;
++ }
++ else
++ {
++ DBG_871X("%s, call rtw_get_stainfo()\n", __func__);
++ stainfo=rtw_get_stainfo(&padapter->stapriv ,&pattrib->ra[0] );
++ }
++
++ if (stainfo!=NULL){
++
++ if(!(stainfo->state &_FW_LINKED))
++ {
++ DBG_871X("%s, psta->state(0x%x) != _FW_LINKED\n", __func__, stainfo->state);
++ return _FAIL;
++ }
++
++ RT_TRACE(_module_rtl871x_security_c_,_drv_err_,("rtw_tkip_encrypt: stainfo!=NULL!!!\n"));
++
++ if(IS_MCAST(pattrib->ra))
++ {
++ prwskey=psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey;
++ }
++ else
++ {
++ prwskey=&stainfo->dot118021x_UncstKey.skey[0];
++ }
++
++ prwskeylen=16;
++
++ for(curfragnum=0;curfragnum<pattrib->nr_frags;curfragnum++){
++ iv=pframe+pattrib->hdrlen;
++ payload=pframe+pattrib->iv_len+pattrib->hdrlen;
++
++ GET_TKIP_PN(iv, dot11txpn);
++
++ pnl=(u16)(dot11txpn.val);
++ pnh=(u32)(dot11txpn.val>>16);
++
++ phase1((u16 *)&ttkey[0],prwskey,&pattrib->ta[0],pnh);
++
++ phase2(&rc4key[0],prwskey,(u16 *)&ttkey[0],pnl);
++
++ if((curfragnum+1)==pattrib->nr_frags){ //4 the last fragment
++ length=pattrib->last_txcmdsz-pattrib->hdrlen-pattrib->iv_len- pattrib->icv_len;
++ RT_TRACE(_module_rtl871x_security_c_,_drv_info_,("pattrib->iv_len =%x, pattrib->icv_len =%x\n", pattrib->iv_len,pattrib->icv_len));
++ *((u32 *)crc)=cpu_to_le32(getcrc32(payload,length));/* modified by Amy*/
++
++ arcfour_init(&mycontext, rc4key,16);
++ arcfour_encrypt(&mycontext, payload, payload, length);
++ arcfour_encrypt(&mycontext, payload+length, crc, 4);
++
++ }
++ else{
++ length=pxmitpriv->frag_len-pattrib->hdrlen-pattrib->iv_len-pattrib->icv_len ;
++ *((u32 *)crc)=cpu_to_le32(getcrc32(payload,length));/* modified by Amy*/
++ arcfour_init(&mycontext,rc4key,16);
++ arcfour_encrypt(&mycontext, payload, payload, length);
++ arcfour_encrypt(&mycontext, payload+length, crc, 4);
++
++ pframe+=pxmitpriv->frag_len;
++ pframe=(u8 *)RND4((SIZE_PTR)(pframe));
++
++ }
++ }
++
++
++ }
++ else{
++ RT_TRACE(_module_rtl871x_security_c_,_drv_err_,("rtw_tkip_encrypt: stainfo==NULL!!!\n"));
++ DBG_871X("%s, psta==NUL\n", __func__);
++ res=_FAIL;
++ }
++
++ }
++_func_exit_;
++ return res;
++
++}
++
++
++//The hlen isn't include the IV
++u32 rtw_tkip_decrypt(_adapter *padapter, u8 *precvframe)
++{ // exclude ICV
++ u16 pnl;
++ u32 pnh;
++ u8 rc4key[16];
++ u8 ttkey[16];
++ u8 crc[4];
++ struct arc4context mycontext;
++ sint length;
++ u32 prwskeylen;
++
++ u8 *pframe, *payload,*iv,*prwskey;
++ union pn48 dot11txpn;
++ struct sta_info *stainfo;
++ struct rx_pkt_attrib *prxattrib = &((union recv_frame *)precvframe)->u.hdr.attrib;
++ struct security_priv *psecuritypriv=&padapter->securitypriv;
++// struct recv_priv *precvpriv=&padapter->recvpriv;
++ u32 res=_SUCCESS;
++
++_func_enter_;
++
++ pframe=(unsigned char *)((union recv_frame*)precvframe)->u.hdr.rx_data;
++
++ //4 start to decrypt recvframe
++ if(prxattrib->encrypt==_TKIP_){
++
++ stainfo=rtw_get_stainfo(&padapter->stapriv ,&prxattrib->ta[0] );
++ if (stainfo!=NULL){
++
++ if(IS_MCAST(prxattrib->ra))
++ {
++ static u32 start = 0;
++ static u32 no_gkey_bc_cnt = 0;
++ static u32 no_gkey_mc_cnt = 0;
++
++ if(psecuritypriv->binstallGrpkey==_FALSE)
++ {
++ res=_FAIL;
++
++ if (start == 0)
++ start = rtw_get_current_time();
++
++ if (is_broadcast_mac_addr(prxattrib->ra))
++ no_gkey_bc_cnt++;
++ else
++ no_gkey_mc_cnt++;
++
++ if (rtw_get_passing_time_ms(start) > 1000) {
++ if (no_gkey_bc_cnt || no_gkey_mc_cnt) {
++ DBG_871X_LEVEL(_drv_always_, FUNC_ADPT_FMT" no_gkey_bc_cnt:%u, no_gkey_mc_cnt:%u\n",
++ FUNC_ADPT_ARG(padapter), no_gkey_bc_cnt, no_gkey_mc_cnt);
++ }
++ start = rtw_get_current_time();
++ no_gkey_bc_cnt = 0;
++ no_gkey_mc_cnt = 0;
++ }
++ goto exit;
++ }
++
++ if (no_gkey_bc_cnt || no_gkey_mc_cnt) {
++ DBG_871X_LEVEL(_drv_always_, FUNC_ADPT_FMT" gkey installed. no_gkey_bc_cnt:%u, no_gkey_mc_cnt:%u\n",
++ FUNC_ADPT_ARG(padapter), no_gkey_bc_cnt, no_gkey_mc_cnt);
++ }
++ start = 0;
++ no_gkey_bc_cnt = 0;
++ no_gkey_mc_cnt = 0;
++
++ //DBG_871X("rx bc/mc packets, to perform sw rtw_tkip_decrypt\n");
++ //prwskey = psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey;
++ prwskey = psecuritypriv->dot118021XGrpKey[prxattrib->key_index].skey;
++ prwskeylen=16;
++ }
++ else
++ {
++ RT_TRACE(_module_rtl871x_security_c_,_drv_err_,("rtw_tkip_decrypt: stainfo!=NULL!!!\n"));
++ prwskey=&stainfo->dot118021x_UncstKey.skey[0];
++ prwskeylen=16;
++ }
++
++ iv=pframe+prxattrib->hdrlen;
++ payload=pframe+prxattrib->iv_len+prxattrib->hdrlen;
++ length= ((union recv_frame *)precvframe)->u.hdr.len-prxattrib->hdrlen-prxattrib->iv_len;
++
++ GET_TKIP_PN(iv, dot11txpn);
++
++ pnl=(u16)(dot11txpn.val);
++ pnh=(u32)(dot11txpn.val>>16);
++
++ phase1((u16 *)&ttkey[0],prwskey,&prxattrib->ta[0],pnh);
++ phase2(&rc4key[0],prwskey,(unsigned short *)&ttkey[0],pnl);
++
++ //4 decrypt payload include icv
++
++ arcfour_init(&mycontext, rc4key,16);
++ arcfour_encrypt(&mycontext, payload, payload, length);
++
++ *((u32 *)crc)=le32_to_cpu(getcrc32(payload,length-4));
++
++ if(crc[3]!=payload[length-1] || crc[2]!=payload[length-2] || crc[1]!=payload[length-3] || crc[0]!=payload[length-4])
++ {
++ RT_TRACE(_module_rtl871x_security_c_,_drv_err_,("rtw_wep_decrypt:icv error crc[3](%x)!=payload[length-1](%x) || crc[2](%x)!=payload[length-2](%x) || crc[1](%x)!=payload[length-3](%x) || crc[0](%x)!=payload[length-4](%x)\n",
++ crc[3],payload[length-1],crc[2],payload[length-2],crc[1],payload[length-3],crc[0],payload[length-4]));
++ res=_FAIL;
++ }
++
++
++ }
++ else{
++ RT_TRACE(_module_rtl871x_security_c_,_drv_err_,("rtw_tkip_decrypt: stainfo==NULL!!!\n"));
++ res=_FAIL;
++ }
++
++ }
++_func_exit_;
++exit:
++ return res;
++
++}
++
++
++//3 =====AES related=====
++
++
++
++#define MAX_MSG_SIZE 2048
++/*****************************/
++/******** SBOX Table *********/
++/*****************************/
++
++ static u8 sbox_table[256] =
++ {
++ 0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5,
++ 0x30, 0x01, 0x67, 0x2b, 0xfe, 0xd7, 0xab, 0x76,
++ 0xca, 0x82, 0xc9, 0x7d, 0xfa, 0x59, 0x47, 0xf0,
++ 0xad, 0xd4, 0xa2, 0xaf, 0x9c, 0xa4, 0x72, 0xc0,
++ 0xb7, 0xfd, 0x93, 0x26, 0x36, 0x3f, 0xf7, 0xcc,
++ 0x34, 0xa5, 0xe5, 0xf1, 0x71, 0xd8, 0x31, 0x15,
++ 0x04, 0xc7, 0x23, 0xc3, 0x18, 0x96, 0x05, 0x9a,
++ 0x07, 0x12, 0x80, 0xe2, 0xeb, 0x27, 0xb2, 0x75,
++ 0x09, 0x83, 0x2c, 0x1a, 0x1b, 0x6e, 0x5a, 0xa0,
++ 0x52, 0x3b, 0xd6, 0xb3, 0x29, 0xe3, 0x2f, 0x84,
++ 0x53, 0xd1, 0x00, 0xed, 0x20, 0xfc, 0xb1, 0x5b,
++ 0x6a, 0xcb, 0xbe, 0x39, 0x4a, 0x4c, 0x58, 0xcf,
++ 0xd0, 0xef, 0xaa, 0xfb, 0x43, 0x4d, 0x33, 0x85,
++ 0x45, 0xf9, 0x02, 0x7f, 0x50, 0x3c, 0x9f, 0xa8,
++ 0x51, 0xa3, 0x40, 0x8f, 0x92, 0x9d, 0x38, 0xf5,
++ 0xbc, 0xb6, 0xda, 0x21, 0x10, 0xff, 0xf3, 0xd2,
++ 0xcd, 0x0c, 0x13, 0xec, 0x5f, 0x97, 0x44, 0x17,
++ 0xc4, 0xa7, 0x7e, 0x3d, 0x64, 0x5d, 0x19, 0x73,
++ 0x60, 0x81, 0x4f, 0xdc, 0x22, 0x2a, 0x90, 0x88,
++ 0x46, 0xee, 0xb8, 0x14, 0xde, 0x5e, 0x0b, 0xdb,
++ 0xe0, 0x32, 0x3a, 0x0a, 0x49, 0x06, 0x24, 0x5c,
++ 0xc2, 0xd3, 0xac, 0x62, 0x91, 0x95, 0xe4, 0x79,
++ 0xe7, 0xc8, 0x37, 0x6d, 0x8d, 0xd5, 0x4e, 0xa9,
++ 0x6c, 0x56, 0xf4, 0xea, 0x65, 0x7a, 0xae, 0x08,
++ 0xba, 0x78, 0x25, 0x2e, 0x1c, 0xa6, 0xb4, 0xc6,
++ 0xe8, 0xdd, 0x74, 0x1f, 0x4b, 0xbd, 0x8b, 0x8a,
++ 0x70, 0x3e, 0xb5, 0x66, 0x48, 0x03, 0xf6, 0x0e,
++ 0x61, 0x35, 0x57, 0xb9, 0x86, 0xc1, 0x1d, 0x9e,
++ 0xe1, 0xf8, 0x98, 0x11, 0x69, 0xd9, 0x8e, 0x94,
++ 0x9b, 0x1e, 0x87, 0xe9, 0xce, 0x55, 0x28, 0xdf,
++ 0x8c, 0xa1, 0x89, 0x0d, 0xbf, 0xe6, 0x42, 0x68,
++ 0x41, 0x99, 0x2d, 0x0f, 0xb0, 0x54, 0xbb, 0x16
++ };
++
++/*****************************/
++/**** Function Prototypes ****/
++/*****************************/
++
++static void bitwise_xor(u8 *ina, u8 *inb, u8 *out);
++static void construct_mic_iv(
++ u8 *mic_header1,
++ sint qc_exists,
++ sint a4_exists,
++ u8 *mpdu,
++ uint payload_length,
++ u8 * pn_vector,
++ uint frtype);// add for CONFIG_IEEE80211W, none 11w also can use
++static void construct_mic_header1(
++ u8 *mic_header1,
++ sint header_length,
++ u8 *mpdu,
++ uint frtype);// add for CONFIG_IEEE80211W, none 11w also can use
++static void construct_mic_header2(
++ u8 *mic_header2,
++ u8 *mpdu,
++ sint a4_exists,
++ sint qc_exists);
++static void construct_ctr_preload(
++ u8 *ctr_preload,
++ sint a4_exists,
++ sint qc_exists,
++ u8 *mpdu,
++ u8 *pn_vector,
++ sint c,
++ uint frtype);// add for CONFIG_IEEE80211W, none 11w also can use
++static void xor_128(u8 *a, u8 *b, u8 *out);
++static void xor_32(u8 *a, u8 *b, u8 *out);
++static u8 sbox(u8 a);
++static void next_key(u8 *key, sint round);
++static void byte_sub(u8 *in, u8 *out);
++static void shift_row(u8 *in, u8 *out);
++static void mix_column(u8 *in, u8 *out);
++#ifndef PLATFORM_FREEBSD
++static void add_round_key( u8 *shiftrow_in,
++ u8 *mcol_in,
++ u8 *block_in,
++ sint round,
++ u8 *out);
++#endif //PLATFORM_FREEBSD
++static void aes128k128d(u8 *key, u8 *data, u8 *ciphertext);
++
++
++/****************************************/
++/* aes128k128d() */
++/* Performs a 128 bit AES encrypt with */
++/* 128 bit data. */
++/****************************************/
++static void xor_128(u8 *a, u8 *b, u8 *out)
++{
++ sint i;
++_func_enter_;
++ for (i=0;i<16; i++)
++ {
++ out[i] = a[i] ^ b[i];
++ }
++_func_exit_;
++}
++
++
++static void xor_32(u8 *a, u8 *b, u8 *out)
++{
++ sint i;
++_func_enter_;
++ for (i=0;i<4; i++)
++ {
++ out[i] = a[i] ^ b[i];
++ }
++_func_exit_;
++}
++
++
++static u8 sbox(u8 a)
++{
++ return sbox_table[(sint)a];
++}
++
++
++static void next_key(u8 *key, sint round)
++{
++ u8 rcon;
++ u8 sbox_key[4];
++ u8 rcon_table[12] =
++ {
++ 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80,
++ 0x1b, 0x36, 0x36, 0x36
++ };
++_func_enter_;
++ sbox_key[0] = sbox(key[13]);
++ sbox_key[1] = sbox(key[14]);
++ sbox_key[2] = sbox(key[15]);
++ sbox_key[3] = sbox(key[12]);
++
++ rcon = rcon_table[round];
++
++ xor_32(&key[0], sbox_key, &key[0]);
++ key[0] = key[0] ^ rcon;
++
++ xor_32(&key[4], &key[0], &key[4]);
++ xor_32(&key[8], &key[4], &key[8]);
++ xor_32(&key[12], &key[8], &key[12]);
++_func_exit_;
++}
++
++
++static void byte_sub(u8 *in, u8 *out)
++{
++ sint i;
++_func_enter_;
++ for (i=0; i< 16; i++)
++ {
++ out[i] = sbox(in[i]);
++ }
++_func_exit_;
++}
++
++
++static void shift_row(u8 *in, u8 *out)
++{
++_func_enter_;
++ out[0] = in[0];
++ out[1] = in[5];
++ out[2] = in[10];
++ out[3] = in[15];
++ out[4] = in[4];
++ out[5] = in[9];
++ out[6] = in[14];
++ out[7] = in[3];
++ out[8] = in[8];
++ out[9] = in[13];
++ out[10] = in[2];
++ out[11] = in[7];
++ out[12] = in[12];
++ out[13] = in[1];
++ out[14] = in[6];
++ out[15] = in[11];
++_func_exit_;
++}
++
++
++static void mix_column(u8 *in, u8 *out)
++{
++ sint i;
++ u8 add1b[4];
++ u8 add1bf7[4];
++ u8 rotl[4];
++ u8 swap_halfs[4];
++ u8 andf7[4];
++ u8 rotr[4];
++ u8 temp[4];
++ u8 tempb[4];
++_func_enter_;
++ for (i=0 ; i<4; i++)
++ {
++ if ((in[i] & 0x80)== 0x80)
++ add1b[i] = 0x1b;
++ else
++ add1b[i] = 0x00;
++ }
++
++ swap_halfs[0] = in[2]; /* Swap halfs */
++ swap_halfs[1] = in[3];
++ swap_halfs[2] = in[0];
++ swap_halfs[3] = in[1];
++
++ rotl[0] = in[3]; /* Rotate left 8 bits */
++ rotl[1] = in[0];
++ rotl[2] = in[1];
++ rotl[3] = in[2];
++
++ andf7[0] = in[0] & 0x7f;
++ andf7[1] = in[1] & 0x7f;
++ andf7[2] = in[2] & 0x7f;
++ andf7[3] = in[3] & 0x7f;
++
++ for (i = 3; i>0; i--) /* logical shift left 1 bit */
++ {
++ andf7[i] = andf7[i] << 1;
++ if ((andf7[i-1] & 0x80) == 0x80)
++ {
++ andf7[i] = (andf7[i] | 0x01);
++ }
++ }
++ andf7[0] = andf7[0] << 1;
++ andf7[0] = andf7[0] & 0xfe;
++
++ xor_32(add1b, andf7, add1bf7);
++
++ xor_32(in, add1bf7, rotr);
++
++ temp[0] = rotr[0]; /* Rotate right 8 bits */
++ rotr[0] = rotr[1];
++ rotr[1] = rotr[2];
++ rotr[2] = rotr[3];
++ rotr[3] = temp[0];
++
++ xor_32(add1bf7, rotr, temp);
++ xor_32(swap_halfs, rotl,tempb);
++ xor_32(temp, tempb, out);
++_func_exit_;
++}
++
++
++static void aes128k128d(u8 *key, u8 *data, u8 *ciphertext)
++{
++ sint round;
++ sint i;
++ u8 intermediatea[16];
++ u8 intermediateb[16];
++ u8 round_key[16];
++_func_enter_;
++ for(i=0; i<16; i++) round_key[i] = key[i];
++
++ for (round = 0; round < 11; round++)
++ {
++ if (round == 0)
++ {
++ xor_128(round_key, data, ciphertext);
++ next_key(round_key, round);
++ }
++ else if (round == 10)
++ {
++ byte_sub(ciphertext, intermediatea);
++ shift_row(intermediatea, intermediateb);
++ xor_128(intermediateb, round_key, ciphertext);
++ }
++ else /* 1 - 9 */
++ {
++ byte_sub(ciphertext, intermediatea);
++ shift_row(intermediatea, intermediateb);
++ mix_column(&intermediateb[0], &intermediatea[0]);
++ mix_column(&intermediateb[4], &intermediatea[4]);
++ mix_column(&intermediateb[8], &intermediatea[8]);
++ mix_column(&intermediateb[12], &intermediatea[12]);
++ xor_128(intermediatea, round_key, ciphertext);
++ next_key(round_key, round);
++ }
++ }
++_func_exit_;
++}
++
++
++/************************************************/
++/* construct_mic_iv() */
++/* Builds the MIC IV from header fields and PN */
++/* Baron think the function is construct CCM */
++/* nonce */
++/************************************************/
++static void construct_mic_iv(
++ u8 *mic_iv,
++ sint qc_exists,
++ sint a4_exists,
++ u8 *mpdu,
++ uint payload_length,
++ u8 *pn_vector,
++ uint frtype// add for CONFIG_IEEE80211W, none 11w also can use
++ )
++{
++ sint i;
++_func_enter_;
++ mic_iv[0] = 0x59;
++ if (qc_exists && a4_exists) mic_iv[1] = mpdu[30] & 0x0f; /* QoS_TC */
++ if (qc_exists && !a4_exists) mic_iv[1] = mpdu[24] & 0x0f; /* mute bits 7-4 */
++ if (!qc_exists) mic_iv[1] = 0x00;
++#ifdef CONFIG_IEEE80211W
++ //802.11w management frame should set management bit(4)
++ if(frtype == WIFI_MGT_TYPE)
++ mic_iv[1] |= BIT(4);
++#endif //CONFIG_IEEE80211W
++ for (i = 2; i < 8; i++)
++ mic_iv[i] = mpdu[i + 8]; /* mic_iv[2:7] = A2[0:5] = mpdu[10:15] */
++ #ifdef CONSISTENT_PN_ORDER
++ for (i = 8; i < 14; i++)
++ mic_iv[i] = pn_vector[i - 8]; /* mic_iv[8:13] = PN[0:5] */
++ #else
++ for (i = 8; i < 14; i++)
++ mic_iv[i] = pn_vector[13 - i]; /* mic_iv[8:13] = PN[5:0] */
++ #endif
++ mic_iv[14] = (unsigned char) (payload_length / 256);
++ mic_iv[15] = (unsigned char) (payload_length % 256);
++_func_exit_;
++}
++
++
++/************************************************/
++/* construct_mic_header1() */
++/* Builds the first MIC header block from */
++/* header fields. */
++/* Build AAD SC,A1,A2 */
++/************************************************/
++static void construct_mic_header1(
++ u8 *mic_header1,
++ sint header_length,
++ u8 *mpdu,
++ uint frtype// add for CONFIG_IEEE80211W, none 11w also can use
++ )
++{
++_func_enter_;
++ mic_header1[0] = (u8)((header_length - 2) / 256);
++ mic_header1[1] = (u8)((header_length - 2) % 256);
++#ifdef CONFIG_IEEE80211W
++ //802.11w management frame don't AND subtype bits 4,5,6 of frame control field
++ if(frtype == WIFI_MGT_TYPE)
++ mic_header1[2] = mpdu[0];
++ else
++#endif //CONFIG_IEEE80211W
++ mic_header1[2] = mpdu[0] & 0xcf; /* Mute CF poll & CF ack bits */
++
++ mic_header1[3] = mpdu[1] & 0xc7; /* Mute retry, more data and pwr mgt bits */
++ mic_header1[4] = mpdu[4]; /* A1 */
++ mic_header1[5] = mpdu[5];
++ mic_header1[6] = mpdu[6];
++ mic_header1[7] = mpdu[7];
++ mic_header1[8] = mpdu[8];
++ mic_header1[9] = mpdu[9];
++ mic_header1[10] = mpdu[10]; /* A2 */
++ mic_header1[11] = mpdu[11];
++ mic_header1[12] = mpdu[12];
++ mic_header1[13] = mpdu[13];
++ mic_header1[14] = mpdu[14];
++ mic_header1[15] = mpdu[15];
++_func_exit_;
++}
++
++
++/************************************************/
++/* construct_mic_header2() */
++/* Builds the last MIC header block from */
++/* header fields. */
++/************************************************/
++static void construct_mic_header2(
++ u8 *mic_header2,
++ u8 *mpdu,
++ sint a4_exists,
++ sint qc_exists
++ )
++{
++ sint i;
++_func_enter_;
++ for (i = 0; i<16; i++) mic_header2[i]=0x00;
++
++ mic_header2[0] = mpdu[16]; /* A3 */
++ mic_header2[1] = mpdu[17];
++ mic_header2[2] = mpdu[18];
++ mic_header2[3] = mpdu[19];
++ mic_header2[4] = mpdu[20];
++ mic_header2[5] = mpdu[21];
++
++ //mic_header2[6] = mpdu[22] & 0xf0; /* SC */
++ mic_header2[6] = 0x00;
++ mic_header2[7] = 0x00; /* mpdu[23]; */
++
++
++ if (!qc_exists && a4_exists)
++ {
++ for (i=0;i<6;i++) mic_header2[8+i] = mpdu[24+i]; /* A4 */
++
++ }
++
++ if (qc_exists && !a4_exists)
++ {
++ mic_header2[8] = mpdu[24] & 0x0f; /* mute bits 15 - 4 */
++ mic_header2[9] = mpdu[25] & 0x00;
++ }
++
++ if (qc_exists && a4_exists)
++ {
++ for (i=0;i<6;i++) mic_header2[8+i] = mpdu[24+i]; /* A4 */
++
++ mic_header2[14] = mpdu[30] & 0x0f;
++ mic_header2[15] = mpdu[31] & 0x00;
++ }
++
++_func_exit_;
++}
++
++
++/************************************************/
++/* construct_mic_header2() */
++/* Builds the last MIC header block from */
++/* header fields. */
++/* Baron think the function is construct CCM */
++/* nonce */
++/************************************************/
++static void construct_ctr_preload(
++ u8 *ctr_preload,
++ sint a4_exists,
++ sint qc_exists,
++ u8 *mpdu,
++ u8 *pn_vector,
++ sint c,
++ uint frtype // add for CONFIG_IEEE80211W, none 11w also can use
++ )
++{
++ sint i = 0;
++_func_enter_;
++ for (i=0; i<16; i++) ctr_preload[i] = 0x00;
++ i = 0;
++
++ ctr_preload[0] = 0x01; /* flag */
++ if (qc_exists && a4_exists)
++ ctr_preload[1] = mpdu[30] & 0x0f; /* QoC_Control */
++ if (qc_exists && !a4_exists)
++ ctr_preload[1] = mpdu[24] & 0x0f;
++#ifdef CONFIG_IEEE80211W
++ //802.11w management frame should set management bit(4)
++ if(frtype == WIFI_MGT_TYPE)
++ ctr_preload[1] |= BIT(4);
++#endif //CONFIG_IEEE80211W
++ for (i = 2; i < 8; i++)
++ ctr_preload[i] = mpdu[i + 8]; /* ctr_preload[2:7] = A2[0:5] = mpdu[10:15] */
++ #ifdef CONSISTENT_PN_ORDER
++ for (i = 8; i < 14; i++)
++ ctr_preload[i] = pn_vector[i - 8]; /* ctr_preload[8:13] = PN[0:5] */
++ #else
++ for (i = 8; i < 14; i++)
++ ctr_preload[i] = pn_vector[13 - i]; /* ctr_preload[8:13] = PN[5:0] */
++ #endif
++ ctr_preload[14] = (unsigned char) (c / 256); /* Ctr */
++ ctr_preload[15] = (unsigned char) (c % 256);
++_func_exit_;
++}
++
++
++/************************************/
++/* bitwise_xor() */
++/* A 128 bit, bitwise exclusive or */
++/************************************/
++static void bitwise_xor(u8 *ina, u8 *inb, u8 *out)
++{
++ sint i;
++_func_enter_;
++ for (i=0; i<16; i++)
++ {
++ out[i] = ina[i] ^ inb[i];
++ }
++_func_exit_;
++}
++
++
++static sint aes_cipher(u8 *key, uint hdrlen,
++ u8 *pframe, uint plen)
++{
++// /*static*/ unsigned char message[MAX_MSG_SIZE];
++ uint qc_exists, a4_exists, i, j, payload_remainder,
++ num_blocks, payload_index;
++
++ u8 pn_vector[6];
++ u8 mic_iv[16];
++ u8 mic_header1[16];
++ u8 mic_header2[16];
++ u8 ctr_preload[16];
++
++ /* Intermediate Buffers */
++ u8 chain_buffer[16];
++ u8 aes_out[16];
++ u8 padded_buffer[16];
++ u8 mic[8];
++// uint offset = 0;
++ uint frtype = GetFrameType(pframe);
++ uint frsubtype = GetFrameSubType(pframe);
++
++_func_enter_;
++ frsubtype=frsubtype>>4;
++
++
++ _rtw_memset((void *)mic_iv, 0, 16);
++ _rtw_memset((void *)mic_header1, 0, 16);
++ _rtw_memset((void *)mic_header2, 0, 16);
++ _rtw_memset((void *)ctr_preload, 0, 16);
++ _rtw_memset((void *)chain_buffer, 0, 16);
++ _rtw_memset((void *)aes_out, 0, 16);
++ _rtw_memset((void *)padded_buffer, 0, 16);
++
++ if ((hdrlen == WLAN_HDR_A3_LEN )||(hdrlen == WLAN_HDR_A3_QOS_LEN))
++ a4_exists = 0;
++ else
++ a4_exists = 1;
++
++ if (
++ ((frtype|frsubtype) == WIFI_DATA_CFACK) ||
++ ((frtype|frsubtype) == WIFI_DATA_CFPOLL)||
++ ((frtype|frsubtype) == WIFI_DATA_CFACKPOLL))
++ {
++ qc_exists = 1;
++ if(hdrlen != WLAN_HDR_A3_QOS_LEN){
++
++ hdrlen += 2;
++ }
++ }
++ // add for CONFIG_IEEE80211W, none 11w also can use
++ else if ((frtype == WIFI_DATA) &&
++ ((frsubtype == 0x08) ||
++ (frsubtype == 0x09)||
++ (frsubtype == 0x0a)||
++ (frsubtype == 0x0b)))
++ {
++ if(hdrlen != WLAN_HDR_A3_QOS_LEN){
++
++ hdrlen += 2;
++ }
++ qc_exists = 1;
++ }
++ else
++ qc_exists = 0;
++
++ pn_vector[0]=pframe[hdrlen];
++ pn_vector[1]=pframe[hdrlen+1];
++ pn_vector[2]=pframe[hdrlen+4];
++ pn_vector[3]=pframe[hdrlen+5];
++ pn_vector[4]=pframe[hdrlen+6];
++ pn_vector[5]=pframe[hdrlen+7];
++
++ construct_mic_iv(
++ mic_iv,
++ qc_exists,
++ a4_exists,
++ pframe, //message,
++ plen,
++ pn_vector,
++ frtype // add for CONFIG_IEEE80211W, none 11w also can use
++ );
++
++ construct_mic_header1(
++ mic_header1,
++ hdrlen,
++ pframe, //message
++ frtype // add for CONFIG_IEEE80211W, none 11w also can use
++ );
++ construct_mic_header2(
++ mic_header2,
++ pframe, //message,
++ a4_exists,
++ qc_exists
++ );
++
++
++ payload_remainder = plen % 16;
++ num_blocks = plen / 16;
++
++ /* Find start of payload */
++ payload_index = (hdrlen + 8);
++
++ /* Calculate MIC */
++ aes128k128d(key, mic_iv, aes_out);
++ bitwise_xor(aes_out, mic_header1, chain_buffer);
++ aes128k128d(key, chain_buffer, aes_out);
++ bitwise_xor(aes_out, mic_header2, chain_buffer);
++ aes128k128d(key, chain_buffer, aes_out);
++
++ for (i = 0; i < num_blocks; i++)
++ {
++ bitwise_xor(aes_out, &pframe[payload_index], chain_buffer);//bitwise_xor(aes_out, &message[payload_index], chain_buffer);
++
++ payload_index += 16;
++ aes128k128d(key, chain_buffer, aes_out);
++ }
++
++ /* Add on the final payload block if it needs padding */
++ if (payload_remainder > 0)
++ {
++ for (j = 0; j < 16; j++) padded_buffer[j] = 0x00;
++ for (j = 0; j < payload_remainder; j++)
++ {
++ padded_buffer[j] = pframe[payload_index++];//padded_buffer[j] = message[payload_index++];
++ }
++ bitwise_xor(aes_out, padded_buffer, chain_buffer);
++ aes128k128d(key, chain_buffer, aes_out);
++
++ }
++
++ for (j = 0 ; j < 8; j++) mic[j] = aes_out[j];
++
++ /* Insert MIC into payload */
++ for (j = 0; j < 8; j++)
++ pframe[payload_index+j] = mic[j]; //message[payload_index+j] = mic[j];
++
++ payload_index = hdrlen + 8;
++ for (i=0; i< num_blocks; i++)
++ {
++ construct_ctr_preload(
++ ctr_preload,
++ a4_exists,
++ qc_exists,
++ pframe, //message,
++ pn_vector,
++ i+1,
++ frtype); // add for CONFIG_IEEE80211W, none 11w also can use
++ aes128k128d(key, ctr_preload, aes_out);
++ bitwise_xor(aes_out, &pframe[payload_index], chain_buffer);//bitwise_xor(aes_out, &message[payload_index], chain_buffer);
++ for (j=0; j<16;j++) pframe[payload_index++] = chain_buffer[j];//for (j=0; j<16;j++) message[payload_index++] = chain_buffer[j];
++ }
++
++ if (payload_remainder > 0) /* If there is a short final block, then pad it,*/
++ { /* encrypt it and copy the unpadded part back */
++ construct_ctr_preload(
++ ctr_preload,
++ a4_exists,
++ qc_exists,
++ pframe, //message,
++ pn_vector,
++ num_blocks+1,
++ frtype); // add for CONFIG_IEEE80211W, none 11w also can use
++
++ for (j = 0; j < 16; j++) padded_buffer[j] = 0x00;
++ for (j = 0; j < payload_remainder; j++)
++ {
++ padded_buffer[j] = pframe[payload_index+j];//padded_buffer[j] = message[payload_index+j];
++ }
++ aes128k128d(key, ctr_preload, aes_out);
++ bitwise_xor(aes_out, padded_buffer, chain_buffer);
++ for (j=0; j<payload_remainder;j++) pframe[payload_index++] = chain_buffer[j];//for (j=0; j<payload_remainder;j++) message[payload_index++] = chain_buffer[j];
++ }
++
++ /* Encrypt the MIC */
++ construct_ctr_preload(
++ ctr_preload,
++ a4_exists,
++ qc_exists,
++ pframe, //message,
++ pn_vector,
++ 0,
++ frtype); // add for CONFIG_IEEE80211W, none 11w also can use
++
++ for (j = 0; j < 16; j++) padded_buffer[j] = 0x00;
++ for (j = 0; j < 8; j++)
++ {
++ padded_buffer[j] = pframe[j+hdrlen+8+plen];//padded_buffer[j] = message[j+hdrlen+8+plen];
++ }
++
++ aes128k128d(key, ctr_preload, aes_out);
++ bitwise_xor(aes_out, padded_buffer, chain_buffer);
++ for (j=0; j<8;j++) pframe[payload_index++] = chain_buffer[j];//for (j=0; j<8;j++) message[payload_index++] = chain_buffer[j];
++_func_exit_;
++ return _SUCCESS;
++}
++
++
++
++
++u32 rtw_aes_encrypt(_adapter *padapter, u8 *pxmitframe)
++{ // exclude ICV
++
++
++ /*static*/
++// unsigned char message[MAX_MSG_SIZE];
++
++ /* Intermediate Buffers */
++ sint curfragnum,length;
++ u32 prwskeylen;
++ u8 *pframe,*prwskey; //, *payload,*iv
++ struct sta_info *stainfo=NULL;
++ struct pkt_attrib *pattrib = &((struct xmit_frame *)pxmitframe)->attrib;
++ struct security_priv *psecuritypriv=&padapter->securitypriv;
++ struct xmit_priv *pxmitpriv=&padapter->xmitpriv;
++
++// uint offset = 0;
++ u32 res=_SUCCESS;
++_func_enter_;
++
++ if(((struct xmit_frame*)pxmitframe)->buf_addr==NULL)
++ return _FAIL;
++
++#ifdef CONFIG_USB_TX_AGGREGATION
++ pframe = ((struct xmit_frame*)pxmitframe)->buf_addr + TXDESC_SIZE +
++ (((struct xmit_frame*)pxmitframe)->pkt_offset * PACKET_OFFSET_SZ);
++#else
++ pframe = ((struct xmit_frame*)pxmitframe)->buf_addr + TXDESC_OFFSET;
++#endif
++
++ //4 start to encrypt each fragment
++ if((pattrib->encrypt==_AES_)){
++
++ if(pattrib->psta)
++ {
++ stainfo = pattrib->psta;
++ }
++ else
++ {
++ DBG_871X("%s, call rtw_get_stainfo()\n", __func__);
++ stainfo=rtw_get_stainfo(&padapter->stapriv ,&pattrib->ra[0] );
++ }
++
++ if (stainfo!=NULL){
++
++ if(!(stainfo->state &_FW_LINKED))
++ {
++ DBG_871X("%s, psta->state(0x%x) != _FW_LINKED\n", __func__, stainfo->state);
++ return _FAIL;
++ }
++
++ RT_TRACE(_module_rtl871x_security_c_,_drv_err_,("rtw_aes_encrypt: stainfo!=NULL!!!\n"));
++
++ if(IS_MCAST(pattrib->ra))
++ {
++ prwskey=psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey;
++ }
++ else
++ {
++ prwskey=&stainfo->dot118021x_UncstKey.skey[0];
++ }
++
++#ifdef CONFIG_TDLS //swencryption
++ {
++ struct sta_info *ptdls_sta;
++ ptdls_sta=rtw_get_stainfo(&padapter->stapriv ,&pattrib->dst[0] );
++ if((ptdls_sta != NULL) && (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE) )
++ {
++ DBG_871X("[%s] for tdls link\n", __FUNCTION__);
++ prwskey=&ptdls_sta->tpk.tk[0];
++ }
++ }
++#endif //CONFIG_TDLS
++
++ prwskeylen=16;
++
++ for(curfragnum=0;curfragnum<pattrib->nr_frags;curfragnum++){
++
++ if((curfragnum+1)==pattrib->nr_frags){ //4 the last fragment
++ length=pattrib->last_txcmdsz-pattrib->hdrlen-pattrib->iv_len- pattrib->icv_len;
++
++ aes_cipher(prwskey,pattrib->hdrlen,pframe, length);
++ }
++ else{
++ length=pxmitpriv->frag_len-pattrib->hdrlen-pattrib->iv_len-pattrib->icv_len ;
++
++ aes_cipher(prwskey,pattrib->hdrlen,pframe, length);
++ pframe+=pxmitpriv->frag_len;
++ pframe=(u8*)RND4((SIZE_PTR)(pframe));
++
++ }
++ }
++
++
++ }
++ else{
++ RT_TRACE(_module_rtl871x_security_c_,_drv_err_,("rtw_aes_encrypt: stainfo==NULL!!!\n"));
++ DBG_871X("%s, psta==NUL\n", __func__);
++ res=_FAIL;
++ }
++
++ }
++
++
++
++_func_exit_;
++ return res;
++}
++
++static sint aes_decipher(u8 *key, uint hdrlen,
++ u8 *pframe, uint plen)
++{
++ static u8 message[MAX_MSG_SIZE];
++ uint qc_exists, a4_exists, i, j, payload_remainder,
++ num_blocks, payload_index;
++ sint res = _SUCCESS;
++ u8 pn_vector[6];
++ u8 mic_iv[16];
++ u8 mic_header1[16];
++ u8 mic_header2[16];
++ u8 ctr_preload[16];
++
++ /* Intermediate Buffers */
++ u8 chain_buffer[16];
++ u8 aes_out[16];
++ u8 padded_buffer[16];
++ u8 mic[8];
++
++
++// uint offset = 0;
++ uint frtype = GetFrameType(pframe);
++ uint frsubtype = GetFrameSubType(pframe);
++_func_enter_;
++ frsubtype=frsubtype>>4;
++
++
++ _rtw_memset((void *)mic_iv, 0, 16);
++ _rtw_memset((void *)mic_header1, 0, 16);
++ _rtw_memset((void *)mic_header2, 0, 16);
++ _rtw_memset((void *)ctr_preload, 0, 16);
++ _rtw_memset((void *)chain_buffer, 0, 16);
++ _rtw_memset((void *)aes_out, 0, 16);
++ _rtw_memset((void *)padded_buffer, 0, 16);
++
++ //start to decrypt the payload
++
++ num_blocks = (plen-8) / 16; //(plen including LLC, payload_length and mic )
++
++ payload_remainder = (plen-8) % 16;
++
++ pn_vector[0] = pframe[hdrlen];
++ pn_vector[1] = pframe[hdrlen+1];
++ pn_vector[2] = pframe[hdrlen+4];
++ pn_vector[3] = pframe[hdrlen+5];
++ pn_vector[4] = pframe[hdrlen+6];
++ pn_vector[5] = pframe[hdrlen+7];
++
++ if ((hdrlen == WLAN_HDR_A3_LEN )||(hdrlen == WLAN_HDR_A3_QOS_LEN))
++ a4_exists = 0;
++ else
++ a4_exists = 1;
++
++ if (
++ ((frtype|frsubtype) == WIFI_DATA_CFACK) ||
++ ((frtype|frsubtype) == WIFI_DATA_CFPOLL)||
++ ((frtype|frsubtype) == WIFI_DATA_CFACKPOLL))
++ {
++ qc_exists = 1;
++ if(hdrlen != WLAN_HDR_A3_QOS_LEN){
++
++ hdrlen += 2;
++ }
++ }//only for data packet . add for CONFIG_IEEE80211W, none 11w also can use
++ else if ((frtype == WIFI_DATA) &&
++ ((frsubtype == 0x08) ||
++ (frsubtype == 0x09)||
++ (frsubtype == 0x0a)||
++ (frsubtype == 0x0b)))
++ {
++ if(hdrlen != WLAN_HDR_A3_QOS_LEN){
++
++ hdrlen += 2;
++ }
++ qc_exists = 1;
++ }
++ else
++ qc_exists = 0;
++
++
++ // now, decrypt pframe with hdrlen offset and plen long
++
++ payload_index = hdrlen + 8; // 8 is for extiv
++
++ for (i=0; i< num_blocks; i++)
++ {
++ construct_ctr_preload(
++ ctr_preload,
++ a4_exists,
++ qc_exists,
++ pframe,
++ pn_vector,
++ i+1,
++ frtype // add for CONFIG_IEEE80211W, none 11w also can use
++ );
++
++ aes128k128d(key, ctr_preload, aes_out);
++ bitwise_xor(aes_out, &pframe[payload_index], chain_buffer);
++
++ for (j=0; j<16;j++) pframe[payload_index++] = chain_buffer[j];
++ }
++
++ if (payload_remainder > 0) /* If there is a short final block, then pad it,*/
++ { /* encrypt it and copy the unpadded part back */
++ construct_ctr_preload(
++ ctr_preload,
++ a4_exists,
++ qc_exists,
++ pframe,
++ pn_vector,
++ num_blocks+1,
++ frtype // add for CONFIG_IEEE80211W, none 11w also can use
++ );
++
++ for (j = 0; j < 16; j++) padded_buffer[j] = 0x00;
++ for (j = 0; j < payload_remainder; j++)
++ {
++ padded_buffer[j] = pframe[payload_index+j];
++ }
++ aes128k128d(key, ctr_preload, aes_out);
++ bitwise_xor(aes_out, padded_buffer, chain_buffer);
++ for (j=0; j<payload_remainder;j++) pframe[payload_index++] = chain_buffer[j];
++ }
++
++ //start to calculate the mic
++
++ _rtw_memcpy((void *)message, pframe, (hdrlen +plen+8)); //8 is for ext iv len
++
++
++ pn_vector[0]=pframe[hdrlen];
++ pn_vector[1]=pframe[hdrlen+1];
++ pn_vector[2]=pframe[hdrlen+4];
++ pn_vector[3]=pframe[hdrlen+5];
++ pn_vector[4]=pframe[hdrlen+6];
++ pn_vector[5]=pframe[hdrlen+7];
++
++
++
++ construct_mic_iv(
++ mic_iv,
++ qc_exists,
++ a4_exists,
++ message,
++ plen-8,
++ pn_vector,
++ frtype // add for CONFIG_IEEE80211W, none 11w also can use
++ );
++
++ construct_mic_header1(
++ mic_header1,
++ hdrlen,
++ message,
++ frtype // add for CONFIG_IEEE80211W, none 11w also can use
++ );
++ construct_mic_header2(
++ mic_header2,
++ message,
++ a4_exists,
++ qc_exists
++ );
++
++
++ payload_remainder = (plen-8) % 16;
++ num_blocks = (plen-8) / 16;
++
++ /* Find start of payload */
++ payload_index = (hdrlen + 8);
++
++ /* Calculate MIC */
++ aes128k128d(key, mic_iv, aes_out);
++ bitwise_xor(aes_out, mic_header1, chain_buffer);
++ aes128k128d(key, chain_buffer, aes_out);
++ bitwise_xor(aes_out, mic_header2, chain_buffer);
++ aes128k128d(key, chain_buffer, aes_out);
++
++ for (i = 0; i < num_blocks; i++)
++ {
++ bitwise_xor(aes_out, &message[payload_index], chain_buffer);
++
++ payload_index += 16;
++ aes128k128d(key, chain_buffer, aes_out);
++ }
++
++ /* Add on the final payload block if it needs padding */
++ if (payload_remainder > 0)
++ {
++ for (j = 0; j < 16; j++) padded_buffer[j] = 0x00;
++ for (j = 0; j < payload_remainder; j++)
++ {
++ padded_buffer[j] = message[payload_index++];
++ }
++ bitwise_xor(aes_out, padded_buffer, chain_buffer);
++ aes128k128d(key, chain_buffer, aes_out);
++
++ }
++
++ for (j = 0 ; j < 8; j++) mic[j] = aes_out[j];
++
++ /* Insert MIC into payload */
++ for (j = 0; j < 8; j++)
++ message[payload_index+j] = mic[j];
++
++ payload_index = hdrlen + 8;
++ for (i=0; i< num_blocks; i++)
++ {
++ construct_ctr_preload(
++ ctr_preload,
++ a4_exists,
++ qc_exists,
++ message,
++ pn_vector,
++ i+1,
++ frtype); // add for CONFIG_IEEE80211W, none 11w also can use
++ aes128k128d(key, ctr_preload, aes_out);
++ bitwise_xor(aes_out, &message[payload_index], chain_buffer);
++ for (j=0; j<16;j++) message[payload_index++] = chain_buffer[j];
++ }
++
++ if (payload_remainder > 0) /* If there is a short final block, then pad it,*/
++ { /* encrypt it and copy the unpadded part back */
++ construct_ctr_preload(
++ ctr_preload,
++ a4_exists,
++ qc_exists,
++ message,
++ pn_vector,
++ num_blocks+1,
++ frtype); // add for CONFIG_IEEE80211W, none 11w also can use
++
++ for (j = 0; j < 16; j++) padded_buffer[j] = 0x00;
++ for (j = 0; j < payload_remainder; j++)
++ {
++ padded_buffer[j] = message[payload_index+j];
++ }
++ aes128k128d(key, ctr_preload, aes_out);
++ bitwise_xor(aes_out, padded_buffer, chain_buffer);
++ for (j=0; j<payload_remainder;j++) message[payload_index++] = chain_buffer[j];
++ }
++
++ /* Encrypt the MIC */
++ construct_ctr_preload(
++ ctr_preload,
++ a4_exists,
++ qc_exists,
++ message,
++ pn_vector,
++ 0,
++ frtype); // add for CONFIG_IEEE80211W, none 11w also can use
++
++ for (j = 0; j < 16; j++) padded_buffer[j] = 0x00;
++ for (j = 0; j < 8; j++)
++ {
++ padded_buffer[j] = message[j+hdrlen+8+plen-8];
++ }
++
++ aes128k128d(key, ctr_preload, aes_out);
++ bitwise_xor(aes_out, padded_buffer, chain_buffer);
++ for (j=0; j<8;j++) message[payload_index++] = chain_buffer[j];
++
++ //compare the mic
++ for(i=0;i<8;i++){
++ if(pframe[hdrlen+8+plen-8+i] != message[hdrlen+8+plen-8+i])
++ {
++ RT_TRACE(_module_rtl871x_security_c_,_drv_err_,("aes_decipher:mic check error mic[%d]: pframe(%x) != message(%x) \n",
++ i,pframe[hdrlen+8+plen-8+i],message[hdrlen+8+plen-8+i]));
++ DBG_871X("aes_decipher:mic check error mic[%d]: pframe(%x) != message(%x) \n",
++ i,pframe[hdrlen+8+plen-8+i],message[hdrlen+8+plen-8+i]);
++ res = _FAIL;
++ }
++ }
++
++ if(res == _FAIL)
++ {
++ int gg=0;
++ for(gg=0; gg < 32; gg++)
++ DBG_871X(" [%d]=%02x ", gg, pframe[gg]);
++ DBG_871X("error packet header \n");
++ }
++
++_func_exit_;
++ return res;
++}
++
++u32 rtw_aes_decrypt(_adapter *padapter, u8 *precvframe)
++{ // exclude ICV
++
++
++ /*static*/
++// unsigned char message[MAX_MSG_SIZE];
++
++
++ /* Intermediate Buffers */
++
++
++ sint length;
++ u8 *pframe,*prwskey; //, *payload,*iv
++ struct sta_info *stainfo;
++ struct rx_pkt_attrib *prxattrib = &((union recv_frame *)precvframe)->u.hdr.attrib;
++ struct security_priv *psecuritypriv=&padapter->securitypriv;
++// struct recv_priv *precvpriv=&padapter->recvpriv;
++ u32 res=_SUCCESS;
++_func_enter_;
++ pframe=(unsigned char *)((union recv_frame*)precvframe)->u.hdr.rx_data;
++ //4 start to encrypt each fragment
++ if((prxattrib->encrypt==_AES_)){
++
++ stainfo=rtw_get_stainfo(&padapter->stapriv ,&prxattrib->ta[0] );
++ if (stainfo!=NULL){
++ RT_TRACE(_module_rtl871x_security_c_,_drv_err_,("rtw_aes_decrypt: stainfo!=NULL!!!\n"));
++
++ if(IS_MCAST(prxattrib->ra))
++ {
++ //in concurrent we should use sw descrypt in group key, so we remove this message
++ //DBG_871X("rx bc/mc packets, to perform sw rtw_aes_decrypt\n");
++ //prwskey = psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey;
++ if(psecuritypriv->binstallGrpkey==_FALSE)
++ {
++ res=_FAIL;
++ DBG_8192C("%s:rx bc/mc packets,but didn't install group key!!!!!!!!!!\n",__FUNCTION__);
++ goto exit;
++ }
++ prwskey = psecuritypriv->dot118021XGrpKey[prxattrib->key_index].skey;
++
++ if(psecuritypriv->dot118021XGrpKeyid != prxattrib->key_index)
++ {
++ DBG_871X("not match packet_index=%d, install_index=%d \n"
++ , prxattrib->key_index, psecuritypriv->dot118021XGrpKeyid);
++ res=_FAIL;
++ goto exit;
++ }
++ }
++ else
++ {
++ prwskey=&stainfo->dot118021x_UncstKey.skey[0];
++ }
++
++ length= ((union recv_frame *)precvframe)->u.hdr.len-prxattrib->hdrlen-prxattrib->iv_len;
++ /*// add for CONFIG_IEEE80211W, debug
++ if(0)
++ printk("@@@@@@@@@@@@@@@@@@ length=%d, prxattrib->hdrlen=%d, prxattrib->pkt_len=%d \n"
++ , length, prxattrib->hdrlen, prxattrib->pkt_len);
++ if(0)
++ {
++ int no;
++ //test print PSK
++ printk("PSK key below:\n");
++ for(no=0;no<16;no++)
++ printk(" %02x ", prwskey[no]);
++ printk("\n");
++ }
++ if(0)
++ {
++ int no;
++ //test print PSK
++ printk("frame:\n");
++ for(no=0;no<prxattrib->pkt_len;no++)
++ printk(" %02x ", pframe[no]);
++ printk("\n");
++ }*/
++
++ res= aes_decipher(prwskey,prxattrib->hdrlen,pframe, length);
++ }
++ else{
++ RT_TRACE(_module_rtl871x_security_c_,_drv_err_,("rtw_aes_encrypt: stainfo==NULL!!!\n"));
++ res=_FAIL;
++ }
++
++ }
++_func_exit_;
++exit:
++ return res;
++}
++
++#ifdef CONFIG_IEEE80211W
++u32 rtw_BIP_verify(_adapter *padapter, u8 *precvframe)
++{
++ struct rx_pkt_attrib *pattrib = &((union recv_frame *)precvframe)->u.hdr.attrib;
++ u8 *pframe;
++ u8 *BIP_AAD, *p;
++ u32 res=_FAIL;
++ uint len, ori_len;
++ struct rtw_ieee80211_hdr *pwlanhdr;
++ u8 mic[16];
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ ori_len = pattrib->pkt_len-WLAN_HDR_A3_LEN+BIP_AAD_SIZE;
++ BIP_AAD = rtw_zmalloc(ori_len);
++
++ if(BIP_AAD == NULL)
++ {
++ DBG_871X("BIP AAD allocate fail\n");
++ return _FAIL;
++ }
++ //PKT start
++ pframe=(unsigned char *)((union recv_frame*)precvframe)->u.hdr.rx_data;
++ //mapping to wlan header
++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++ //save the frame body + MME
++ _rtw_memcpy(BIP_AAD+BIP_AAD_SIZE, pframe+WLAN_HDR_A3_LEN, pattrib->pkt_len-WLAN_HDR_A3_LEN);
++ //find MME IE pointer
++ p = rtw_get_ie(BIP_AAD+BIP_AAD_SIZE, _MME_IE_, &len, pattrib->pkt_len-WLAN_HDR_A3_LEN);
++ //Baron
++ if(p)
++ {
++ u16 keyid=0;
++ u64 temp_ipn=0;
++ //save packet number
++ _rtw_memcpy(&temp_ipn, p+4, 6);
++ temp_ipn = le64_to_cpu(temp_ipn);
++ //BIP packet number should bigger than previous BIP packet
++ if(temp_ipn <= pmlmeext->mgnt_80211w_IPN_rx)
++ {
++ DBG_871X("replay BIP packet\n");
++ goto BIP_exit;
++ }
++ //copy key index
++ _rtw_memcpy(&keyid, p+2, 2);
++ keyid = le16_to_cpu(keyid);
++ if(keyid != padapter->securitypriv.dot11wBIPKeyid)
++ {
++ DBG_871X("BIP key index error!\n");
++ goto BIP_exit;
++ }
++ //clear the MIC field of MME to zero
++ _rtw_memset(p+2+len-8, 0, 8);
++
++ //conscruct AAD, copy frame control field
++ _rtw_memcpy(BIP_AAD, &pwlanhdr->frame_ctl, 2);
++ ClearRetry(BIP_AAD);
++ ClearPwrMgt(BIP_AAD);
++ ClearMData(BIP_AAD);
++ //conscruct AAD, copy address 1 to address 3
++ _rtw_memcpy(BIP_AAD+2, pwlanhdr->addr1, 18);
++
++ if(omac1_aes_128(padapter->securitypriv.dot11wBIPKey[padapter->securitypriv.dot11wBIPKeyid].skey
++ , BIP_AAD, ori_len, mic))
++ goto BIP_exit;
++
++ /*//management packet content
++ {
++ int pp;
++ DBG_871X("pkt: ");
++ for(pp=0;pp< pattrib->pkt_len; pp++)
++ printk(" %02x ", pframe[pp]);
++ DBG_871X("\n");
++ //BIP AAD + management frame body + MME(MIC is zero)
++ DBG_871X("AAD+PKT: ");
++ for(pp=0;pp< ori_len; pp++)
++ DBG_871X(" %02x ", BIP_AAD[pp]);
++ DBG_871X("\n");
++ //show the MIC result
++ DBG_871X("mic: ");
++ for(pp=0;pp<16; pp++)
++ DBG_871X(" %02x ", mic[pp]);
++ DBG_871X("\n");
++ }
++ */
++ //MIC field should be last 8 bytes of packet (packet without FCS)
++ if(_rtw_memcmp(mic, pframe+pattrib->pkt_len-8, 8))
++ {
++ pmlmeext->mgnt_80211w_IPN_rx = temp_ipn;
++ res=_SUCCESS;
++ }
++ else
++ DBG_871X("BIP MIC error!\n");
++
++ }
++ else
++ res = RTW_RX_HANDLED;
++BIP_exit:
++
++ rtw_mfree(BIP_AAD, ori_len);
++ return res;
++}
++#endif //CONFIG_IEEE80211W
++
++#ifndef PLATFORM_FREEBSD
++/* compress 512-bits */
++static int sha256_compress(struct sha256_state *md, unsigned char *buf)
++{
++ u32 S[8], W[64], t0, t1;
++ u32 t;
++ int i;
++
++ /* copy state into S */
++ for (i = 0; i < 8; i++) {
++ S[i] = md->state[i];
++ }
++
++ /* copy the state into 512-bits into W[0..15] */
++ for (i = 0; i < 16; i++)
++ W[i] = WPA_GET_BE32(buf + (4 * i));
++
++ /* fill W[16..63] */
++ for (i = 16; i < 64; i++) {
++ W[i] = Gamma1(W[i - 2]) + W[i - 7] + Gamma0(W[i - 15]) +
++ W[i - 16];
++ }
++
++ /* Compress */
++#define RND(a,b,c,d,e,f,g,h,i) \
++ t0 = h + Sigma1(e) + Ch(e, f, g) + K[i] + W[i]; \
++ t1 = Sigma0(a) + Maj(a, b, c); \
++ d += t0; \
++ h = t0 + t1;
++
++ for (i = 0; i < 64; ++i) {
++ RND(S[0], S[1], S[2], S[3], S[4], S[5], S[6], S[7], i);
++ t = S[7]; S[7] = S[6]; S[6] = S[5]; S[5] = S[4];
++ S[4] = S[3]; S[3] = S[2]; S[2] = S[1]; S[1] = S[0]; S[0] = t;
++ }
++
++ /* feedback */
++ for (i = 0; i < 8; i++) {
++ md->state[i] = md->state[i] + S[i];
++ }
++ return 0;
++}
++
++/* Initialize the hash state */
++static void sha256_init(struct sha256_state *md)
++{
++ md->curlen = 0;
++ md->length = 0;
++ md->state[0] = 0x6A09E667UL;
++ md->state[1] = 0xBB67AE85UL;
++ md->state[2] = 0x3C6EF372UL;
++ md->state[3] = 0xA54FF53AUL;
++ md->state[4] = 0x510E527FUL;
++ md->state[5] = 0x9B05688CUL;
++ md->state[6] = 0x1F83D9ABUL;
++ md->state[7] = 0x5BE0CD19UL;
++}
++
++/**
++ Process a block of memory though the hash
++ @param md The hash state
++ @param in The data to hash
++ @param inlen The length of the data (octets)
++ @return CRYPT_OK if successful
++*/
++static int sha256_process(struct sha256_state *md, unsigned char *in,
++ unsigned long inlen)
++{
++ unsigned long n;
++#define block_size 64
++
++ if (md->curlen > sizeof(md->buf))
++ return -1;
++
++ while (inlen > 0) {
++ if (md->curlen == 0 && inlen >= block_size) {
++ if (sha256_compress(md, (unsigned char *) in) < 0)
++ return -1;
++ md->length += block_size * 8;
++ in += block_size;
++ inlen -= block_size;
++ } else {
++ n = MIN(inlen, (block_size - md->curlen));
++ _rtw_memcpy(md->buf + md->curlen, in, n);
++ md->curlen += n;
++ in += n;
++ inlen -= n;
++ if (md->curlen == block_size) {
++ if (sha256_compress(md, md->buf) < 0)
++ return -1;
++ md->length += 8 * block_size;
++ md->curlen = 0;
++ }
++ }
++ }
++
++ return 0;
++}
++
++
++/**
++ Terminate the hash to get the digest
++ @param md The hash state
++ @param out [out] The destination of the hash (32 bytes)
++ @return CRYPT_OK if successful
++*/
++static int sha256_done(struct sha256_state *md, unsigned char *out)
++{
++ int i;
++
++ if (md->curlen >= sizeof(md->buf))
++ return -1;
++
++ /* increase the length of the message */
++ md->length += md->curlen * 8;
++
++ /* append the '1' bit */
++ md->buf[md->curlen++] = (unsigned char) 0x80;
++
++ /* if the length is currently above 56 bytes we append zeros
++ * then compress. Then we can fall back to padding zeros and length
++ * encoding like normal.
++ */
++ if (md->curlen > 56) {
++ while (md->curlen < 64) {
++ md->buf[md->curlen++] = (unsigned char) 0;
++ }
++ sha256_compress(md, md->buf);
++ md->curlen = 0;
++ }
++
++ /* pad upto 56 bytes of zeroes */
++ while (md->curlen < 56) {
++ md->buf[md->curlen++] = (unsigned char) 0;
++ }
++
++ /* store length */
++ WPA_PUT_BE64(md->buf + 56, md->length);
++ sha256_compress(md, md->buf);
++
++ /* copy output */
++ for (i = 0; i < 8; i++)
++ WPA_PUT_BE32(out + (4 * i), md->state[i]);
++
++ return 0;
++}
++
++/**
++ * sha256_vector - SHA256 hash for data vector
++ * @num_elem: Number of elements in the data vector
++ * @addr: Pointers to the data areas
++ * @len: Lengths of the data blocks
++ * @mac: Buffer for the hash
++ * Returns: 0 on success, -1 of failure
++ */
++static int sha256_vector(size_t num_elem, u8 *addr[], size_t *len,
++ u8 *mac)
++{
++ struct sha256_state ctx;
++ size_t i;
++
++ sha256_init(&ctx);
++ for (i = 0; i < num_elem; i++)
++ if (sha256_process(&ctx, addr[i], len[i]))
++ return -1;
++ if (sha256_done(&ctx, mac))
++ return -1;
++ return 0;
++}
++
++static u8 os_strlen(const char *s)
++{
++ const char *p = s;
++ while (*p)
++ p++;
++ return p - s;
++}
++
++static int os_memcmp(void *s1, void *s2, u8 n)
++{
++ unsigned char *p1 = s1, *p2 = s2;
++
++ if (n == 0)
++ return 0;
++
++ while (*p1 == *p2) {
++ p1++;
++ p2++;
++ n--;
++ if (n == 0)
++ return 0;
++ }
++
++ return *p1 - *p2;
++}
++
++/**
++ * hmac_sha256_vector - HMAC-SHA256 over data vector (RFC 2104)
++ * @key: Key for HMAC operations
++ * @key_len: Length of the key in bytes
++ * @num_elem: Number of elements in the data vector
++ * @addr: Pointers to the data areas
++ * @len: Lengths of the data blocks
++ * @mac: Buffer for the hash (32 bytes)
++ */
++static void hmac_sha256_vector(u8 *key, size_t key_len, size_t num_elem,
++ u8 *addr[], size_t *len, u8 *mac)
++{
++ unsigned char k_pad[64]; /* padding - key XORd with ipad/opad */
++ unsigned char tk[32];
++ u8 *_addr[6];
++ size_t _len[6], i;
++
++ if (num_elem > 5) {
++ /*
++ * Fixed limit on the number of fragments to avoid having to
++ * allocate memory (which could fail).
++ */
++ return;
++ }
++
++ /* if key is longer than 64 bytes reset it to key = SHA256(key) */
++ if (key_len > 64) {
++ sha256_vector(1, &key, &key_len, tk);
++ key = tk;
++ key_len = 32;
++ }
++
++ /* the HMAC_SHA256 transform looks like:
++ *
++ * SHA256(K XOR opad, SHA256(K XOR ipad, text))
++ *
++ * where K is an n byte key
++ * ipad is the byte 0x36 repeated 64 times
++ * opad is the byte 0x5c repeated 64 times
++ * and text is the data being protected */
++
++ /* start out by storing key in ipad */
++ _rtw_memset(k_pad, 0, sizeof(k_pad));
++ _rtw_memcpy(k_pad, key, key_len);
++ /* XOR key with ipad values */
++ for (i = 0; i < 64; i++)
++ k_pad[i] ^= 0x36;
++
++ /* perform inner SHA256 */
++ _addr[0] = k_pad;
++ _len[0] = 64;
++ for (i = 0; i < num_elem; i++) {
++ _addr[i + 1] = addr[i];
++ _len[i + 1] = len[i];
++ }
++ sha256_vector(1 + num_elem, _addr, _len, mac);
++
++ _rtw_memset(k_pad, 0, sizeof(k_pad));
++ _rtw_memcpy(k_pad, key, key_len);
++ /* XOR key with opad values */
++ for (i = 0; i < 64; i++)
++ k_pad[i] ^= 0x5c;
++
++ /* perform outer SHA256 */
++ _addr[0] = k_pad;
++ _len[0] = 64;
++ _addr[1] = mac;
++ _len[1] = 32;
++ sha256_vector(2, _addr, _len, mac);
++}
++#endif //PLATFORM_FREEBSD
++/**
++ * sha256_prf - SHA256-based Pseudo-Random Function (IEEE 802.11r, 8.5.1.5.2)
++ * @key: Key for PRF
++ * @key_len: Length of the key in bytes
++ * @label: A unique label for each purpose of the PRF
++ * @data: Extra data to bind into the key
++ * @data_len: Length of the data
++ * @buf: Buffer for the generated pseudo-random key
++ * @buf_len: Number of bytes of key to generate
++ *
++ * This function is used to derive new, cryptographically separate keys from a
++ * given key.
++ */
++#ifndef PLATFORM_FREEBSD //Baron
++static void sha256_prf(u8 *key, size_t key_len, char *label,
++ u8 *data, size_t data_len, u8 *buf, size_t buf_len)
++{
++ u16 counter = 1;
++ size_t pos, plen;
++ u8 hash[SHA256_MAC_LEN];
++ u8 *addr[4];
++ size_t len[4];
++ u8 counter_le[2], length_le[2];
++
++ addr[0] = counter_le;
++ len[0] = 2;
++ addr[1] = (u8 *) label;
++ len[1] = os_strlen(label);
++ addr[2] = data;
++ len[2] = data_len;
++ addr[3] = length_le;
++ len[3] = sizeof(length_le);
++
++ WPA_PUT_LE16(length_le, buf_len * 8);
++ pos = 0;
++ while (pos < buf_len) {
++ plen = buf_len - pos;
++ WPA_PUT_LE16(counter_le, counter);
++ if (plen >= SHA256_MAC_LEN) {
++ hmac_sha256_vector(key, key_len, 4, addr, len,
++ &buf[pos]);
++ pos += SHA256_MAC_LEN;
++ } else {
++ hmac_sha256_vector(key, key_len, 4, addr, len, hash);
++ _rtw_memcpy(&buf[pos], hash, plen);
++ break;
++ }
++ counter++;
++ }
++}
++#endif //PLATFORM_FREEBSD Baron
++
++/* AES tables*/
++const u32 Te0[256] = {
++ 0xc66363a5U, 0xf87c7c84U, 0xee777799U, 0xf67b7b8dU,
++ 0xfff2f20dU, 0xd66b6bbdU, 0xde6f6fb1U, 0x91c5c554U,
++ 0x60303050U, 0x02010103U, 0xce6767a9U, 0x562b2b7dU,
++ 0xe7fefe19U, 0xb5d7d762U, 0x4dababe6U, 0xec76769aU,
++ 0x8fcaca45U, 0x1f82829dU, 0x89c9c940U, 0xfa7d7d87U,
++ 0xeffafa15U, 0xb25959ebU, 0x8e4747c9U, 0xfbf0f00bU,
++ 0x41adadecU, 0xb3d4d467U, 0x5fa2a2fdU, 0x45afafeaU,
++ 0x239c9cbfU, 0x53a4a4f7U, 0xe4727296U, 0x9bc0c05bU,
++ 0x75b7b7c2U, 0xe1fdfd1cU, 0x3d9393aeU, 0x4c26266aU,
++ 0x6c36365aU, 0x7e3f3f41U, 0xf5f7f702U, 0x83cccc4fU,
++ 0x6834345cU, 0x51a5a5f4U, 0xd1e5e534U, 0xf9f1f108U,
++ 0xe2717193U, 0xabd8d873U, 0x62313153U, 0x2a15153fU,
++ 0x0804040cU, 0x95c7c752U, 0x46232365U, 0x9dc3c35eU,
++ 0x30181828U, 0x379696a1U, 0x0a05050fU, 0x2f9a9ab5U,
++ 0x0e070709U, 0x24121236U, 0x1b80809bU, 0xdfe2e23dU,
++ 0xcdebeb26U, 0x4e272769U, 0x7fb2b2cdU, 0xea75759fU,
++ 0x1209091bU, 0x1d83839eU, 0x582c2c74U, 0x341a1a2eU,
++ 0x361b1b2dU, 0xdc6e6eb2U, 0xb45a5aeeU, 0x5ba0a0fbU,
++ 0xa45252f6U, 0x763b3b4dU, 0xb7d6d661U, 0x7db3b3ceU,
++ 0x5229297bU, 0xdde3e33eU, 0x5e2f2f71U, 0x13848497U,
++ 0xa65353f5U, 0xb9d1d168U, 0x00000000U, 0xc1eded2cU,
++ 0x40202060U, 0xe3fcfc1fU, 0x79b1b1c8U, 0xb65b5bedU,
++ 0xd46a6abeU, 0x8dcbcb46U, 0x67bebed9U, 0x7239394bU,
++ 0x944a4adeU, 0x984c4cd4U, 0xb05858e8U, 0x85cfcf4aU,
++ 0xbbd0d06bU, 0xc5efef2aU, 0x4faaaae5U, 0xedfbfb16U,
++ 0x864343c5U, 0x9a4d4dd7U, 0x66333355U, 0x11858594U,
++ 0x8a4545cfU, 0xe9f9f910U, 0x04020206U, 0xfe7f7f81U,
++ 0xa05050f0U, 0x783c3c44U, 0x259f9fbaU, 0x4ba8a8e3U,
++ 0xa25151f3U, 0x5da3a3feU, 0x804040c0U, 0x058f8f8aU,
++ 0x3f9292adU, 0x219d9dbcU, 0x70383848U, 0xf1f5f504U,
++ 0x63bcbcdfU, 0x77b6b6c1U, 0xafdada75U, 0x42212163U,
++ 0x20101030U, 0xe5ffff1aU, 0xfdf3f30eU, 0xbfd2d26dU,
++ 0x81cdcd4cU, 0x180c0c14U, 0x26131335U, 0xc3ecec2fU,
++ 0xbe5f5fe1U, 0x359797a2U, 0x884444ccU, 0x2e171739U,
++ 0x93c4c457U, 0x55a7a7f2U, 0xfc7e7e82U, 0x7a3d3d47U,
++ 0xc86464acU, 0xba5d5de7U, 0x3219192bU, 0xe6737395U,
++ 0xc06060a0U, 0x19818198U, 0x9e4f4fd1U, 0xa3dcdc7fU,
++ 0x44222266U, 0x542a2a7eU, 0x3b9090abU, 0x0b888883U,
++ 0x8c4646caU, 0xc7eeee29U, 0x6bb8b8d3U, 0x2814143cU,
++ 0xa7dede79U, 0xbc5e5ee2U, 0x160b0b1dU, 0xaddbdb76U,
++ 0xdbe0e03bU, 0x64323256U, 0x743a3a4eU, 0x140a0a1eU,
++ 0x924949dbU, 0x0c06060aU, 0x4824246cU, 0xb85c5ce4U,
++ 0x9fc2c25dU, 0xbdd3d36eU, 0x43acacefU, 0xc46262a6U,
++ 0x399191a8U, 0x319595a4U, 0xd3e4e437U, 0xf279798bU,
++ 0xd5e7e732U, 0x8bc8c843U, 0x6e373759U, 0xda6d6db7U,
++ 0x018d8d8cU, 0xb1d5d564U, 0x9c4e4ed2U, 0x49a9a9e0U,
++ 0xd86c6cb4U, 0xac5656faU, 0xf3f4f407U, 0xcfeaea25U,
++ 0xca6565afU, 0xf47a7a8eU, 0x47aeaee9U, 0x10080818U,
++ 0x6fbabad5U, 0xf0787888U, 0x4a25256fU, 0x5c2e2e72U,
++ 0x381c1c24U, 0x57a6a6f1U, 0x73b4b4c7U, 0x97c6c651U,
++ 0xcbe8e823U, 0xa1dddd7cU, 0xe874749cU, 0x3e1f1f21U,
++ 0x964b4bddU, 0x61bdbddcU, 0x0d8b8b86U, 0x0f8a8a85U,
++ 0xe0707090U, 0x7c3e3e42U, 0x71b5b5c4U, 0xcc6666aaU,
++ 0x904848d8U, 0x06030305U, 0xf7f6f601U, 0x1c0e0e12U,
++ 0xc26161a3U, 0x6a35355fU, 0xae5757f9U, 0x69b9b9d0U,
++ 0x17868691U, 0x99c1c158U, 0x3a1d1d27U, 0x279e9eb9U,
++ 0xd9e1e138U, 0xebf8f813U, 0x2b9898b3U, 0x22111133U,
++ 0xd26969bbU, 0xa9d9d970U, 0x078e8e89U, 0x339494a7U,
++ 0x2d9b9bb6U, 0x3c1e1e22U, 0x15878792U, 0xc9e9e920U,
++ 0x87cece49U, 0xaa5555ffU, 0x50282878U, 0xa5dfdf7aU,
++ 0x038c8c8fU, 0x59a1a1f8U, 0x09898980U, 0x1a0d0d17U,
++ 0x65bfbfdaU, 0xd7e6e631U, 0x844242c6U, 0xd06868b8U,
++ 0x824141c3U, 0x299999b0U, 0x5a2d2d77U, 0x1e0f0f11U,
++ 0x7bb0b0cbU, 0xa85454fcU, 0x6dbbbbd6U, 0x2c16163aU,
++};
++const u32 Td0[256] = {
++ 0x51f4a750U, 0x7e416553U, 0x1a17a4c3U, 0x3a275e96U,
++ 0x3bab6bcbU, 0x1f9d45f1U, 0xacfa58abU, 0x4be30393U,
++ 0x2030fa55U, 0xad766df6U, 0x88cc7691U, 0xf5024c25U,
++ 0x4fe5d7fcU, 0xc52acbd7U, 0x26354480U, 0xb562a38fU,
++ 0xdeb15a49U, 0x25ba1b67U, 0x45ea0e98U, 0x5dfec0e1U,
++ 0xc32f7502U, 0x814cf012U, 0x8d4697a3U, 0x6bd3f9c6U,
++ 0x038f5fe7U, 0x15929c95U, 0xbf6d7aebU, 0x955259daU,
++ 0xd4be832dU, 0x587421d3U, 0x49e06929U, 0x8ec9c844U,
++ 0x75c2896aU, 0xf48e7978U, 0x99583e6bU, 0x27b971ddU,
++ 0xbee14fb6U, 0xf088ad17U, 0xc920ac66U, 0x7dce3ab4U,
++ 0x63df4a18U, 0xe51a3182U, 0x97513360U, 0x62537f45U,
++ 0xb16477e0U, 0xbb6bae84U, 0xfe81a01cU, 0xf9082b94U,
++ 0x70486858U, 0x8f45fd19U, 0x94de6c87U, 0x527bf8b7U,
++ 0xab73d323U, 0x724b02e2U, 0xe31f8f57U, 0x6655ab2aU,
++ 0xb2eb2807U, 0x2fb5c203U, 0x86c57b9aU, 0xd33708a5U,
++ 0x302887f2U, 0x23bfa5b2U, 0x02036abaU, 0xed16825cU,
++ 0x8acf1c2bU, 0xa779b492U, 0xf307f2f0U, 0x4e69e2a1U,
++ 0x65daf4cdU, 0x0605bed5U, 0xd134621fU, 0xc4a6fe8aU,
++ 0x342e539dU, 0xa2f355a0U, 0x058ae132U, 0xa4f6eb75U,
++ 0x0b83ec39U, 0x4060efaaU, 0x5e719f06U, 0xbd6e1051U,
++ 0x3e218af9U, 0x96dd063dU, 0xdd3e05aeU, 0x4de6bd46U,
++ 0x91548db5U, 0x71c45d05U, 0x0406d46fU, 0x605015ffU,
++ 0x1998fb24U, 0xd6bde997U, 0x894043ccU, 0x67d99e77U,
++ 0xb0e842bdU, 0x07898b88U, 0xe7195b38U, 0x79c8eedbU,
++ 0xa17c0a47U, 0x7c420fe9U, 0xf8841ec9U, 0x00000000U,
++ 0x09808683U, 0x322bed48U, 0x1e1170acU, 0x6c5a724eU,
++ 0xfd0efffbU, 0x0f853856U, 0x3daed51eU, 0x362d3927U,
++ 0x0a0fd964U, 0x685ca621U, 0x9b5b54d1U, 0x24362e3aU,
++ 0x0c0a67b1U, 0x9357e70fU, 0xb4ee96d2U, 0x1b9b919eU,
++ 0x80c0c54fU, 0x61dc20a2U, 0x5a774b69U, 0x1c121a16U,
++ 0xe293ba0aU, 0xc0a02ae5U, 0x3c22e043U, 0x121b171dU,
++ 0x0e090d0bU, 0xf28bc7adU, 0x2db6a8b9U, 0x141ea9c8U,
++ 0x57f11985U, 0xaf75074cU, 0xee99ddbbU, 0xa37f60fdU,
++ 0xf701269fU, 0x5c72f5bcU, 0x44663bc5U, 0x5bfb7e34U,
++ 0x8b432976U, 0xcb23c6dcU, 0xb6edfc68U, 0xb8e4f163U,
++ 0xd731dccaU, 0x42638510U, 0x13972240U, 0x84c61120U,
++ 0x854a247dU, 0xd2bb3df8U, 0xaef93211U, 0xc729a16dU,
++ 0x1d9e2f4bU, 0xdcb230f3U, 0x0d8652ecU, 0x77c1e3d0U,
++ 0x2bb3166cU, 0xa970b999U, 0x119448faU, 0x47e96422U,
++ 0xa8fc8cc4U, 0xa0f03f1aU, 0x567d2cd8U, 0x223390efU,
++ 0x87494ec7U, 0xd938d1c1U, 0x8ccaa2feU, 0x98d40b36U,
++ 0xa6f581cfU, 0xa57ade28U, 0xdab78e26U, 0x3fadbfa4U,
++ 0x2c3a9de4U, 0x5078920dU, 0x6a5fcc9bU, 0x547e4662U,
++ 0xf68d13c2U, 0x90d8b8e8U, 0x2e39f75eU, 0x82c3aff5U,
++ 0x9f5d80beU, 0x69d0937cU, 0x6fd52da9U, 0xcf2512b3U,
++ 0xc8ac993bU, 0x10187da7U, 0xe89c636eU, 0xdb3bbb7bU,
++ 0xcd267809U, 0x6e5918f4U, 0xec9ab701U, 0x834f9aa8U,
++ 0xe6956e65U, 0xaaffe67eU, 0x21bccf08U, 0xef15e8e6U,
++ 0xbae79bd9U, 0x4a6f36ceU, 0xea9f09d4U, 0x29b07cd6U,
++ 0x31a4b2afU, 0x2a3f2331U, 0xc6a59430U, 0x35a266c0U,
++ 0x744ebc37U, 0xfc82caa6U, 0xe090d0b0U, 0x33a7d815U,
++ 0xf104984aU, 0x41ecdaf7U, 0x7fcd500eU, 0x1791f62fU,
++ 0x764dd68dU, 0x43efb04dU, 0xccaa4d54U, 0xe49604dfU,
++ 0x9ed1b5e3U, 0x4c6a881bU, 0xc12c1fb8U, 0x4665517fU,
++ 0x9d5eea04U, 0x018c355dU, 0xfa877473U, 0xfb0b412eU,
++ 0xb3671d5aU, 0x92dbd252U, 0xe9105633U, 0x6dd64713U,
++ 0x9ad7618cU, 0x37a10c7aU, 0x59f8148eU, 0xeb133c89U,
++ 0xcea927eeU, 0xb761c935U, 0xe11ce5edU, 0x7a47b13cU,
++ 0x9cd2df59U, 0x55f2733fU, 0x1814ce79U, 0x73c737bfU,
++ 0x53f7cdeaU, 0x5ffdaa5bU, 0xdf3d6f14U, 0x7844db86U,
++ 0xcaaff381U, 0xb968c43eU, 0x3824342cU, 0xc2a3405fU,
++ 0x161dc372U, 0xbce2250cU, 0x283c498bU, 0xff0d9541U,
++ 0x39a80171U, 0x080cb3deU, 0xd8b4e49cU, 0x6456c190U,
++ 0x7bcb8461U, 0xd532b670U, 0x486c5c74U, 0xd0b85742U,
++};
++const u8 Td4s[256] = {
++ 0x52U, 0x09U, 0x6aU, 0xd5U, 0x30U, 0x36U, 0xa5U, 0x38U,
++ 0xbfU, 0x40U, 0xa3U, 0x9eU, 0x81U, 0xf3U, 0xd7U, 0xfbU,
++ 0x7cU, 0xe3U, 0x39U, 0x82U, 0x9bU, 0x2fU, 0xffU, 0x87U,
++ 0x34U, 0x8eU, 0x43U, 0x44U, 0xc4U, 0xdeU, 0xe9U, 0xcbU,
++ 0x54U, 0x7bU, 0x94U, 0x32U, 0xa6U, 0xc2U, 0x23U, 0x3dU,
++ 0xeeU, 0x4cU, 0x95U, 0x0bU, 0x42U, 0xfaU, 0xc3U, 0x4eU,
++ 0x08U, 0x2eU, 0xa1U, 0x66U, 0x28U, 0xd9U, 0x24U, 0xb2U,
++ 0x76U, 0x5bU, 0xa2U, 0x49U, 0x6dU, 0x8bU, 0xd1U, 0x25U,
++ 0x72U, 0xf8U, 0xf6U, 0x64U, 0x86U, 0x68U, 0x98U, 0x16U,
++ 0xd4U, 0xa4U, 0x5cU, 0xccU, 0x5dU, 0x65U, 0xb6U, 0x92U,
++ 0x6cU, 0x70U, 0x48U, 0x50U, 0xfdU, 0xedU, 0xb9U, 0xdaU,
++ 0x5eU, 0x15U, 0x46U, 0x57U, 0xa7U, 0x8dU, 0x9dU, 0x84U,
++ 0x90U, 0xd8U, 0xabU, 0x00U, 0x8cU, 0xbcU, 0xd3U, 0x0aU,
++ 0xf7U, 0xe4U, 0x58U, 0x05U, 0xb8U, 0xb3U, 0x45U, 0x06U,
++ 0xd0U, 0x2cU, 0x1eU, 0x8fU, 0xcaU, 0x3fU, 0x0fU, 0x02U,
++ 0xc1U, 0xafU, 0xbdU, 0x03U, 0x01U, 0x13U, 0x8aU, 0x6bU,
++ 0x3aU, 0x91U, 0x11U, 0x41U, 0x4fU, 0x67U, 0xdcU, 0xeaU,
++ 0x97U, 0xf2U, 0xcfU, 0xceU, 0xf0U, 0xb4U, 0xe6U, 0x73U,
++ 0x96U, 0xacU, 0x74U, 0x22U, 0xe7U, 0xadU, 0x35U, 0x85U,
++ 0xe2U, 0xf9U, 0x37U, 0xe8U, 0x1cU, 0x75U, 0xdfU, 0x6eU,
++ 0x47U, 0xf1U, 0x1aU, 0x71U, 0x1dU, 0x29U, 0xc5U, 0x89U,
++ 0x6fU, 0xb7U, 0x62U, 0x0eU, 0xaaU, 0x18U, 0xbeU, 0x1bU,
++ 0xfcU, 0x56U, 0x3eU, 0x4bU, 0xc6U, 0xd2U, 0x79U, 0x20U,
++ 0x9aU, 0xdbU, 0xc0U, 0xfeU, 0x78U, 0xcdU, 0x5aU, 0xf4U,
++ 0x1fU, 0xddU, 0xa8U, 0x33U, 0x88U, 0x07U, 0xc7U, 0x31U,
++ 0xb1U, 0x12U, 0x10U, 0x59U, 0x27U, 0x80U, 0xecU, 0x5fU,
++ 0x60U, 0x51U, 0x7fU, 0xa9U, 0x19U, 0xb5U, 0x4aU, 0x0dU,
++ 0x2dU, 0xe5U, 0x7aU, 0x9fU, 0x93U, 0xc9U, 0x9cU, 0xefU,
++ 0xa0U, 0xe0U, 0x3bU, 0x4dU, 0xaeU, 0x2aU, 0xf5U, 0xb0U,
++ 0xc8U, 0xebU, 0xbbU, 0x3cU, 0x83U, 0x53U, 0x99U, 0x61U,
++ 0x17U, 0x2bU, 0x04U, 0x7eU, 0xbaU, 0x77U, 0xd6U, 0x26U,
++ 0xe1U, 0x69U, 0x14U, 0x63U, 0x55U, 0x21U, 0x0cU, 0x7dU,
++};
++const u8 rcons[] = {
++ 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1B, 0x36
++ /* for 128-bit blocks, Rijndael never uses more than 10 rcon values */
++};
++
++/**
++ * Expand the cipher key into the encryption key schedule.
++ *
++ * @return the number of rounds for the given cipher key size.
++ */
++#ifndef PLATFORM_FREEBSD //Baron
++static void rijndaelKeySetupEnc(u32 rk[/*44*/], const u8 cipherKey[])
++{
++ int i;
++ u32 temp;
++
++ rk[0] = GETU32(cipherKey );
++ rk[1] = GETU32(cipherKey + 4);
++ rk[2] = GETU32(cipherKey + 8);
++ rk[3] = GETU32(cipherKey + 12);
++ for (i = 0; i < 10; i++) {
++ temp = rk[3];
++ rk[4] = rk[0] ^
++ TE421(temp) ^ TE432(temp) ^ TE443(temp) ^ TE414(temp) ^
++ RCON(i);
++ rk[5] = rk[1] ^ rk[4];
++ rk[6] = rk[2] ^ rk[5];
++ rk[7] = rk[3] ^ rk[6];
++ rk += 4;
++ }
++}
++
++static void rijndaelEncrypt(u32 rk[/*44*/], u8 pt[16], u8 ct[16])
++{
++ u32 s0, s1, s2, s3, t0, t1, t2, t3;
++ int Nr = 10;
++#ifndef FULL_UNROLL
++ int r;
++#endif /* ?FULL_UNROLL */
++
++ /*
++ * map byte array block to cipher state
++ * and add initial round key:
++ */
++ s0 = GETU32(pt ) ^ rk[0];
++ s1 = GETU32(pt + 4) ^ rk[1];
++ s2 = GETU32(pt + 8) ^ rk[2];
++ s3 = GETU32(pt + 12) ^ rk[3];
++
++#define ROUND(i,d,s) \
++d##0 = TE0(s##0) ^ TE1(s##1) ^ TE2(s##2) ^ TE3(s##3) ^ rk[4 * i]; \
++d##1 = TE0(s##1) ^ TE1(s##2) ^ TE2(s##3) ^ TE3(s##0) ^ rk[4 * i + 1]; \
++d##2 = TE0(s##2) ^ TE1(s##3) ^ TE2(s##0) ^ TE3(s##1) ^ rk[4 * i + 2]; \
++d##3 = TE0(s##3) ^ TE1(s##0) ^ TE2(s##1) ^ TE3(s##2) ^ rk[4 * i + 3]
++
++#ifdef FULL_UNROLL
++
++ ROUND(1,t,s);
++ ROUND(2,s,t);
++ ROUND(3,t,s);
++ ROUND(4,s,t);
++ ROUND(5,t,s);
++ ROUND(6,s,t);
++ ROUND(7,t,s);
++ ROUND(8,s,t);
++ ROUND(9,t,s);
++
++ rk += Nr << 2;
++
++#else /* !FULL_UNROLL */
++
++ /* Nr - 1 full rounds: */
++ r = Nr >> 1;
++ for (;;) {
++ ROUND(1,t,s);
++ rk += 8;
++ if (--r == 0)
++ break;
++ ROUND(0,s,t);
++ }
++
++#endif /* ?FULL_UNROLL */
++
++#undef ROUND
++
++ /*
++ * apply last round and
++ * map cipher state to byte array block:
++ */
++ s0 = TE41(t0) ^ TE42(t1) ^ TE43(t2) ^ TE44(t3) ^ rk[0];
++ PUTU32(ct , s0);
++ s1 = TE41(t1) ^ TE42(t2) ^ TE43(t3) ^ TE44(t0) ^ rk[1];
++ PUTU32(ct + 4, s1);
++ s2 = TE41(t2) ^ TE42(t3) ^ TE43(t0) ^ TE44(t1) ^ rk[2];
++ PUTU32(ct + 8, s2);
++ s3 = TE41(t3) ^ TE42(t0) ^ TE43(t1) ^ TE44(t2) ^ rk[3];
++ PUTU32(ct + 12, s3);
++}
++
++static void * aes_encrypt_init(u8 *key, size_t len)
++{
++ u32 *rk;
++ if (len != 16)
++ return NULL;
++ rk = (u32*)rtw_malloc(AES_PRIV_SIZE);
++ if (rk == NULL)
++ return NULL;
++ rijndaelKeySetupEnc(rk, key);
++ return rk;
++}
++
++static void aes_128_encrypt(void *ctx, u8 *plain, u8 *crypt)
++{
++ rijndaelEncrypt(ctx, plain, crypt);
++}
++
++
++static void gf_mulx(u8 *pad)
++{
++ int i, carry;
++
++ carry = pad[0] & 0x80;
++ for (i = 0; i < AES_BLOCK_SIZE - 1; i++)
++ pad[i] = (pad[i] << 1) | (pad[i + 1] >> 7);
++ pad[AES_BLOCK_SIZE - 1] <<= 1;
++ if (carry)
++ pad[AES_BLOCK_SIZE - 1] ^= 0x87;
++}
++
++static void aes_encrypt_deinit(void *ctx)
++{
++ _rtw_memset(ctx, 0, AES_PRIV_SIZE);
++ rtw_mfree(ctx, AES_PRIV_SIZE);
++}
++
++
++/**
++ * omac1_aes_128_vector - One-Key CBC MAC (OMAC1) hash with AES-128
++ * @key: 128-bit key for the hash operation
++ * @num_elem: Number of elements in the data vector
++ * @addr: Pointers to the data areas
++ * @len: Lengths of the data blocks
++ * @mac: Buffer for MAC (128 bits, i.e., 16 bytes)
++ * Returns: 0 on success, -1 on failure
++ *
++ * This is a mode for using block cipher (AES in this case) for authentication.
++ * OMAC1 was standardized with the name CMAC by NIST in a Special Publication
++ * (SP) 800-38B.
++ */
++static int omac1_aes_128_vector(u8 *key, size_t num_elem,
++ u8 *addr[], size_t *len, u8 *mac)
++{
++ void *ctx;
++ u8 cbc[AES_BLOCK_SIZE], pad[AES_BLOCK_SIZE];
++ u8 *pos, *end;
++ size_t i, e, left, total_len;
++
++ ctx = aes_encrypt_init(key, 16);
++ if (ctx == NULL)
++ return -1;
++ _rtw_memset(cbc, 0, AES_BLOCK_SIZE);
++
++ total_len = 0;
++ for (e = 0; e < num_elem; e++)
++ total_len += len[e];
++ left = total_len;
++
++ e = 0;
++ pos = addr[0];
++ end = pos + len[0];
++
++ while (left >= AES_BLOCK_SIZE) {
++ for (i = 0; i < AES_BLOCK_SIZE; i++) {
++ cbc[i] ^= *pos++;
++ if (pos >= end) {
++ e++;
++ pos = addr[e];
++ end = pos + len[e];
++ }
++ }
++ if (left > AES_BLOCK_SIZE)
++ aes_128_encrypt(ctx, cbc, cbc);
++ left -= AES_BLOCK_SIZE;
++ }
++
++ _rtw_memset(pad, 0, AES_BLOCK_SIZE);
++ aes_128_encrypt(ctx, pad, pad);
++ gf_mulx(pad);
++
++ if (left || total_len == 0) {
++ for (i = 0; i < left; i++) {
++ cbc[i] ^= *pos++;
++ if (pos >= end) {
++ e++;
++ pos = addr[e];
++ end = pos + len[e];
++ }
++ }
++ cbc[left] ^= 0x80;
++ gf_mulx(pad);
++ }
++
++ for (i = 0; i < AES_BLOCK_SIZE; i++)
++ pad[i] ^= cbc[i];
++ aes_128_encrypt(ctx, pad, mac);
++ aes_encrypt_deinit(ctx);
++ return 0;
++}
++
++
++/**
++ * omac1_aes_128 - One-Key CBC MAC (OMAC1) hash with AES-128 (aka AES-CMAC)
++ * @key: 128-bit key for the hash operation
++ * @data: Data buffer for which a MAC is determined
++ * @data_len: Length of data buffer in bytes
++ * @mac: Buffer for MAC (128 bits, i.e., 16 bytes)
++ * Returns: 0 on success, -1 on failure
++ *
++ * This is a mode for using block cipher (AES in this case) for authentication.
++ * OMAC1 was standardized with the name CMAC by NIST in a Special Publication
++ * (SP) 800-38B.
++ */ //modify for CONFIG_IEEE80211W
++int omac1_aes_128(u8 *key, u8 *data, size_t data_len, u8 *mac)
++{
++ return omac1_aes_128_vector(key, 1, &data, &data_len, mac);
++}
++#endif //PLATFORM_FREEBSD Baron
++
++#ifdef CONFIG_TDLS
++void wpa_tdls_generate_tpk(_adapter *padapter, struct sta_info *psta)
++{
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ u8 *SNonce = psta->SNonce;
++ u8 *ANonce = psta->ANonce;
++
++ u8 key_input[SHA256_MAC_LEN];
++ u8 *nonce[2];
++ size_t len[2];
++ u8 data[3 * ETH_ALEN];
++
++ /* IEEE Std 802.11z-2010 8.5.9.1:
++ * TPK-Key-Input = SHA-256(min(SNonce, ANonce) || max(SNonce, ANonce))
++ */
++ len[0] = 32;
++ len[1] = 32;
++ if (os_memcmp(SNonce, ANonce, 32) < 0) {
++ nonce[0] = SNonce;
++ nonce[1] = ANonce;
++ } else {
++ nonce[0] = ANonce;
++ nonce[1] = SNonce;
++ }
++
++ sha256_vector(2, nonce, len, key_input);
++
++ /*
++ * TPK-Key-Data = KDF-N_KEY(TPK-Key-Input, "TDLS PMK",
++ * min(MAC_I, MAC_R) || max(MAC_I, MAC_R) || BSSID || N_KEY)
++ * TODO: is N_KEY really included in KDF Context and if so, in which
++ * presentation format (little endian 16-bit?) is it used? It gets
++ * added by the KDF anyway..
++ */
++
++ if (os_memcmp(myid(&(padapter->eeprompriv)), psta->hwaddr, ETH_ALEN) < 0) {
++ _rtw_memcpy(data, myid(&(padapter->eeprompriv)), ETH_ALEN);
++ _rtw_memcpy(data + ETH_ALEN, psta->hwaddr, ETH_ALEN);
++ } else {
++ _rtw_memcpy(data, psta->hwaddr, ETH_ALEN);
++ _rtw_memcpy(data + ETH_ALEN, myid(&(padapter->eeprompriv)), ETH_ALEN);
++ }
++ _rtw_memcpy(data + 2 * ETH_ALEN, get_bssid(pmlmepriv), ETH_ALEN);
++
++ sha256_prf(key_input, SHA256_MAC_LEN, "TDLS PMK", data, sizeof(data), (u8 *) &psta->tpk, sizeof(psta->tpk));
++
++
++}
++
++/**
++ * wpa_tdls_ftie_mic - Calculate TDLS FTIE MIC
++ * @kck: TPK-KCK
++ * @lnkid: Pointer to the beginning of Link Identifier IE
++ * @rsnie: Pointer to the beginning of RSN IE used for handshake
++ * @timeoutie: Pointer to the beginning of Timeout IE used for handshake
++ * @ftie: Pointer to the beginning of FT IE
++ * @mic: Pointer for writing MIC
++ *
++ * Calculate MIC for TDLS frame.
++ */
++int wpa_tdls_ftie_mic(u8 *kck, u8 trans_seq,
++ u8 *lnkid, u8 *rsnie, u8 *timeoutie, u8 *ftie,
++ u8 *mic)
++{
++ u8 *buf, *pos;
++ struct wpa_tdls_ftie *_ftie;
++ struct wpa_tdls_lnkid *_lnkid;
++ int ret;
++ int len = 2 * ETH_ALEN + 1 + 2 + lnkid[1] + 2 + rsnie[1] +
++ 2 + timeoutie[1] + 2 + ftie[1];
++ buf = rtw_zmalloc(len);
++ if (!buf) {
++ DBG_871X("TDLS: No memory for MIC calculation\n");
++ return -1;
++ }
++
++ pos = buf;
++ _lnkid = (struct wpa_tdls_lnkid *) lnkid;
++ /* 1) TDLS initiator STA MAC address */
++ _rtw_memcpy(pos, _lnkid->init_sta, ETH_ALEN);
++ pos += ETH_ALEN;
++ /* 2) TDLS responder STA MAC address */
++ _rtw_memcpy(pos, _lnkid->resp_sta, ETH_ALEN);
++ pos += ETH_ALEN;
++ /* 3) Transaction Sequence number */
++ *pos++ = trans_seq;
++ /* 4) Link Identifier IE */
++ _rtw_memcpy(pos, lnkid, 2 + lnkid[1]);
++ pos += 2 + lnkid[1];
++ /* 5) RSN IE */
++ _rtw_memcpy(pos, rsnie, 2 + rsnie[1]);
++ pos += 2 + rsnie[1];
++ /* 6) Timeout Interval IE */
++ _rtw_memcpy(pos, timeoutie, 2 + timeoutie[1]);
++ pos += 2 + timeoutie[1];
++ /* 7) FTIE, with the MIC field of the FTIE set to 0 */
++ _rtw_memcpy(pos, ftie, 2 + ftie[1]);
++ _ftie = (struct wpa_tdls_ftie *) pos;
++ _rtw_memset(_ftie->mic, 0, TDLS_MIC_LEN);
++ pos += 2 + ftie[1];
++
++ ret = omac1_aes_128(kck, buf, pos - buf, mic);
++ rtw_mfree(buf, len);
++ return ret;
++
++}
++
++int tdls_verify_mic(u8 *kck, u8 trans_seq,
++ u8 *lnkid, u8 *rsnie, u8 *timeoutie, u8 *ftie)
++{
++ u8 *buf, *pos;
++ int len;
++ u8 mic[16];
++ int ret;
++ u8 *rx_ftie, *tmp_ftie;
++
++ if (lnkid == NULL || rsnie == NULL ||
++ timeoutie == NULL || ftie == NULL){
++ return 0;
++ }
++
++ len = 2 * ETH_ALEN + 1 + 2 + 18 + 2 + *(rsnie+1) + 2 + *(timeoutie+1) + 2 + *(ftie+1);
++
++ buf = rtw_zmalloc(len);
++ if (buf == NULL)
++ return 0;
++
++ pos = buf;
++ /* 1) TDLS initiator STA MAC address */
++ _rtw_memcpy(pos, lnkid + ETH_ALEN + 2, ETH_ALEN);
++ pos += ETH_ALEN;
++ /* 2) TDLS responder STA MAC address */
++ _rtw_memcpy(pos, lnkid + 2 * ETH_ALEN + 2, ETH_ALEN);
++ pos += ETH_ALEN;
++ /* 3) Transaction Sequence number */
++ *pos++ = trans_seq;
++ /* 4) Link Identifier IE */
++ _rtw_memcpy(pos, lnkid, 2 + 18);
++ pos += 2 + 18;
++ /* 5) RSN IE */
++ _rtw_memcpy(pos, rsnie, 2 + *(rsnie+1));
++ pos += 2 + *(rsnie+1);
++ /* 6) Timeout Interval IE */
++ _rtw_memcpy(pos, timeoutie, 2 + *(timeoutie+1));
++ pos += 2 + *(timeoutie+1);
++ /* 7) FTIE, with the MIC field of the FTIE set to 0 */
++ _rtw_memcpy(pos, ftie, 2 + *(ftie+1));
++ pos += 2;
++ tmp_ftie = (u8 *) (pos+2);
++ _rtw_memset(tmp_ftie, 0, 16);
++ pos += *(ftie+1);
++
++ ret = omac1_aes_128(kck, buf, pos - buf, mic);
++ rtw_mfree(buf, len);
++ if (ret)
++ return 0;
++ rx_ftie = ftie+4;
++
++ if (os_memcmp(mic, rx_ftie, 16) == 0) {
++ //Valid MIC
++ return 1;
++ }
++
++ //Invalid MIC
++ DBG_871X( "[%s] Invalid MIC\n", __FUNCTION__);
++ return 0;
++
++}
++#endif //CONFIG_TDLS
++
++#ifdef PLATFORM_WINDOWS
++void rtw_use_tkipkey_handler (
++ IN PVOID SystemSpecific1,
++ IN PVOID FunctionContext,
++ IN PVOID SystemSpecific2,
++ IN PVOID SystemSpecific3
++ )
++#endif
++#ifdef PLATFORM_LINUX
++void rtw_use_tkipkey_handler(void *FunctionContext)
++#endif
++#ifdef PLATFORM_FREEBSD
++void rtw_use_tkipkey_handler(void *FunctionContext)
++#endif
++{
++ _adapter *padapter = (_adapter *)FunctionContext;
++
++
++_func_enter_;
++
++ RT_TRACE(_module_rtl871x_security_c_,_drv_err_,("^^^rtw_use_tkipkey_handler ^^^\n"));
++
++/*
++ if(padapter->bDriverStopped ||padapter->bSurpriseRemoved){
++ RT_TRACE(_module_rtl871x_security_c_,_drv_err_,("^^^rtw_use_tkipkey_handler (padapter->bDriverStopped %d)(padapter->bSurpriseRemoved %d)^^^\n",padapter->bDriverStopped,padapter->bSurpriseRemoved));
++
++ return;
++ }
++ */
++
++ padapter->securitypriv.busetkipkey=_TRUE;
++
++ RT_TRACE(_module_rtl871x_security_c_,_drv_err_,("^^^rtw_use_tkipkey_handler padapter->securitypriv.busetkipkey=%d^^^\n",padapter->securitypriv.busetkipkey));
++
++_func_exit_;
++
++}
++
++/* Restore HW wep key setting according to key_mask */
++void rtw_sec_restore_wep_key(_adapter *adapter)
++{
++ struct security_priv* securitypriv=&(adapter->securitypriv);
++ sint keyid;
++
++ if((_WEP40_ == securitypriv->dot11PrivacyAlgrthm) ||(_WEP104_ == securitypriv->dot11PrivacyAlgrthm)) {
++ for(keyid=0;keyid<4;keyid++){
++ if(securitypriv->key_mask & BIT(keyid)){
++ if(keyid == securitypriv->dot11PrivacyKeyIndex)
++ rtw_set_key(adapter,securitypriv, keyid, 1);
++ else
++ rtw_set_key(adapter,securitypriv, keyid, 0);
++ }
++ }
++ }
++}
++
++u8 rtw_handle_tkip_countermeasure(_adapter* adapter, const char *caller)
++{
++ struct security_priv* securitypriv=&(adapter->securitypriv);
++ u8 status = _SUCCESS;
++
++ if (securitypriv->btkip_countermeasure == _TRUE) {
++ u32 passing_ms = rtw_get_passing_time_ms(securitypriv->btkip_countermeasure_time);
++ if (passing_ms > 60*1000) {
++ LOG_LEVEL(_drv_info_, "%s("ADPT_FMT") countermeasure time:%ds > 60s \n",
++ caller, ADPT_ARG(adapter), passing_ms/1000);
++ securitypriv->btkip_countermeasure = _FALSE;
++ securitypriv->btkip_countermeasure_time = 0;
++ } else {
++ LOG_LEVEL(_drv_warning_, "%s("ADPT_FMT") countermeasure time:%ds < 60s \n",
++ caller, ADPT_ARG(adapter), passing_ms/1000);
++ status = _FAIL;
++ }
++ }
++
++ return status;
++}
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/core/rtw_sreset.c linux-xbian-rpi/drivers/net/wireless/rtl8192cu/core/rtw_sreset.c
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/core/rtw_sreset.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/core/rtw_sreset.c 2015-07-28 01:20:58.305654202 +0200
+@@ -0,0 +1,351 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++
++#include<rtw_sreset.h>
++
++void sreset_init_value(_adapter *padapter)
++{
++#if defined(DBG_CONFIG_ERROR_DETECT)
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++ struct sreset_priv *psrtpriv = &pHalData->srestpriv;
++
++ _rtw_mutex_init(&psrtpriv->silentreset_mutex);
++ psrtpriv->silent_reset_inprogress = _FALSE;
++ psrtpriv->Wifi_Error_Status = WIFI_STATUS_SUCCESS;
++ psrtpriv->last_tx_time =0;
++ psrtpriv->last_tx_complete_time =0;
++#endif
++}
++void sreset_reset_value(_adapter *padapter)
++{
++#if defined(DBG_CONFIG_ERROR_DETECT)
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++ struct sreset_priv *psrtpriv = &pHalData->srestpriv;
++
++ psrtpriv->silent_reset_inprogress = _FALSE;
++ psrtpriv->Wifi_Error_Status = WIFI_STATUS_SUCCESS;
++ psrtpriv->last_tx_time =0;
++ psrtpriv->last_tx_complete_time =0;
++#endif
++}
++
++u8 sreset_get_wifi_status(_adapter *padapter)
++{
++#if defined(DBG_CONFIG_ERROR_DETECT)
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++ struct sreset_priv *psrtpriv = &pHalData->srestpriv;
++
++ u8 status = WIFI_STATUS_SUCCESS;
++ u32 val32 = 0;
++ _irqL irqL;
++ if(psrtpriv->silent_reset_inprogress == _TRUE)
++ {
++ return status;
++ }
++ val32 =rtw_read32(padapter,REG_TXDMA_STATUS);
++ if(val32==0xeaeaeaea){
++ psrtpriv->Wifi_Error_Status = WIFI_IF_NOT_EXIST;
++ }
++ else if(val32!=0){
++ DBG_8192C("txdmastatu(%x)\n",val32);
++ psrtpriv->Wifi_Error_Status = WIFI_MAC_TXDMA_ERROR;
++ }
++
++ if(WIFI_STATUS_SUCCESS !=psrtpriv->Wifi_Error_Status)
++ {
++ DBG_8192C("==>%s error_status(0x%x) \n",__FUNCTION__,psrtpriv->Wifi_Error_Status);
++ status = (psrtpriv->Wifi_Error_Status &( ~(USB_READ_PORT_FAIL|USB_WRITE_PORT_FAIL)));
++ }
++ DBG_8192C("==> %s wifi_status(0x%x)\n",__FUNCTION__,status);
++
++ //status restore
++ psrtpriv->Wifi_Error_Status = WIFI_STATUS_SUCCESS;
++
++ return status;
++#else
++ return WIFI_STATUS_SUCCESS;
++#endif
++}
++
++void sreset_set_wifi_error_status(_adapter *padapter, u32 status)
++{
++#if defined(DBG_CONFIG_ERROR_DETECT)
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++ pHalData->srestpriv.Wifi_Error_Status = status;
++#endif
++}
++
++void sreset_set_trigger_point(_adapter *padapter, s32 tgp)
++{
++#if defined(DBG_CONFIG_ERROR_DETECT)
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++ pHalData->srestpriv.dbg_trigger_point = tgp;
++#endif
++}
++
++bool sreset_inprogress(_adapter *padapter)
++{
++#if defined(DBG_CONFIG_ERROR_RESET)
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++ return pHalData->srestpriv.silent_reset_inprogress;
++#else
++ return _FALSE;
++#endif
++}
++
++void sreset_restore_security_station(_adapter *padapter)
++{
++ u8 EntryId = 0;
++ struct mlme_priv *mlmepriv = &padapter->mlmepriv;
++ struct sta_priv * pstapriv = &padapter->stapriv;
++ struct sta_info *psta;
++ struct security_priv* psecuritypriv=&(padapter->securitypriv);
++ struct mlme_ext_info *pmlmeinfo = &padapter->mlmeextpriv.mlmext_info;
++
++ {
++ u8 val8;
++
++ if (pmlmeinfo->auth_algo == dot11AuthAlgrthm_8021X) {
++ val8 = 0xcc;
++ #ifdef CONFIG_WAPI_SUPPORT
++ } else if (padapter->wapiInfo.bWapiEnable && pmlmeinfo->auth_algo == dot11AuthAlgrthm_WAPI) {
++ //Disable TxUseDefaultKey, RxUseDefaultKey, RxBroadcastUseDefaultKey.
++ val8 = 0x4c;
++ #endif
++ } else {
++ val8 = 0xcf;
++ }
++ rtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, (u8 *)(&val8));
++ }
++
++ #if 0
++ if ( ( padapter->securitypriv.dot11PrivacyAlgrthm == _WEP40_ ) ||
++ ( padapter->securitypriv.dot11PrivacyAlgrthm == _WEP104_ ))
++ {
++
++ for(EntryId=0; EntryId<4; EntryId++)
++ {
++ if(EntryId == psecuritypriv->dot11PrivacyKeyIndex)
++ rtw_set_key(padapter,&padapter->securitypriv, EntryId, 1);
++ else
++ rtw_set_key(padapter,&padapter->securitypriv, EntryId, 0);
++ }
++
++ }
++ else
++ #endif
++ if((padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_) ||
++ (padapter->securitypriv.dot11PrivacyAlgrthm == _AES_))
++ {
++ psta = rtw_get_stainfo(pstapriv, get_bssid(mlmepriv));
++ if (psta == NULL) {
++ //DEBUG_ERR( ("Set wpa_set_encryption: Obtain Sta_info fail \n"));
++ }
++ else
++ {
++ //pairwise key
++ rtw_setstakey_cmd(padapter, (unsigned char *)psta, _TRUE);
++ //group key
++ rtw_set_key(padapter,&padapter->securitypriv,padapter->securitypriv.dot118021XGrpKeyid, 0);
++ }
++ }
++}
++
++void sreset_restore_network_station(_adapter *padapter)
++{
++ struct mlme_priv *mlmepriv = &padapter->mlmepriv;
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++
++ #if 0
++ {
++ //=======================================================
++ // reset related register of Beacon control
++
++ //set MSR to nolink
++ Set_MSR(padapter, _HW_STATE_NOLINK_);
++ // reject all data frame
++ rtw_write16(padapter, REG_RXFLTMAP2,0x00);
++ //reset TSF
++ rtw_write8(padapter, REG_DUAL_TSF_RST, (BIT(0)|BIT(1)));
++
++ // disable update TSF
++ SetBcnCtrlReg(padapter, BIT(4), 0);
++
++ //=======================================================
++ }
++ #endif
++
++ rtw_setopmode_cmd(padapter, Ndis802_11Infrastructure);
++
++ {
++ u8 threshold;
++ #ifdef CONFIG_USB_HCI
++ // TH=1 => means that invalidate usb rx aggregation
++ // TH=0 => means that validate usb rx aggregation, use init value.
++ if(mlmepriv->htpriv.ht_option) {
++ if(padapter->registrypriv.wifi_spec==1)
++ threshold = 1;
++ else
++ threshold = 0;
++ rtw_hal_set_hwreg(padapter, HW_VAR_RXDMA_AGG_PG_TH, (u8 *)(&threshold));
++ } else {
++ threshold = 1;
++ rtw_hal_set_hwreg(padapter, HW_VAR_RXDMA_AGG_PG_TH, (u8 *)(&threshold));
++ }
++ #endif
++ }
++
++ set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode);
++
++ //disable dynamic functions, such as high power, DIG
++ //Switch_DM_Func(padapter, DYNAMIC_FUNC_DISABLE, _FALSE);
++
++ rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, pmlmeinfo->network.MacAddress);
++
++ {
++ u8 join_type = 0;
++ rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type));
++ }
++
++ Set_MSR(padapter, (pmlmeinfo->state & 0x3));
++
++ mlmeext_joinbss_event_callback(padapter, 1);
++ //restore Sequence No.
++ rtw_write8(padapter,0x4dc,padapter->xmitpriv.nqos_ssn);
++
++ sreset_restore_security_station(padapter);
++}
++
++void sreset_restore_network_status(_adapter *padapter)
++{
++ struct mlme_priv *mlmepriv = &padapter->mlmepriv;
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++
++ if (check_fwstate(mlmepriv, WIFI_STATION_STATE)) {
++ DBG_871X(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_STATION_STATE\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv));
++ sreset_restore_network_station(padapter);
++ } else if (check_fwstate(mlmepriv, WIFI_AP_STATE)) {
++ DBG_871X(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_AP_STATE\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv));
++ rtw_ap_restore_network(padapter);
++ } else if (check_fwstate(mlmepriv, WIFI_ADHOC_STATE)) {
++ DBG_871X(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_ADHOC_STATE\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv));
++ } else {
++ DBG_871X(FUNC_ADPT_FMT" fwstate:0x%08x - ???\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv));
++ }
++}
++
++void sreset_stop_adapter(_adapter *padapter)
++{
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++
++ if (padapter == NULL)
++ return;
++
++ DBG_871X(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
++
++ if (!rtw_netif_queue_stopped(padapter->pnetdev))
++ rtw_netif_stop_queue(padapter->pnetdev);
++
++ rtw_cancel_all_timer(padapter);
++
++ /* TODO: OS and HCI independent */
++ #if defined(PLATFORM_LINUX) && defined(CONFIG_USB_HCI)
++ tasklet_kill(&pxmitpriv->xmit_tasklet);
++ #endif
++
++ if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY))
++ rtw_scan_abort(padapter);
++
++ if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING))
++ _rtw_join_timeout_handler(padapter);
++
++}
++
++void sreset_start_adapter(_adapter *padapter)
++{
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++
++ if (padapter == NULL)
++ return;
++
++ DBG_871X(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
++
++ if (check_fwstate(pmlmepriv, _FW_LINKED)) {
++ sreset_restore_network_status(padapter);
++ }
++
++ /* TODO: OS and HCI independent */
++ #if defined(PLATFORM_LINUX) && defined(CONFIG_USB_HCI)
++ tasklet_hi_schedule(&pxmitpriv->xmit_tasklet);
++ #endif
++
++ _set_timer(&padapter->mlmepriv.dynamic_chk_timer, 2000);
++
++ if (rtw_netif_queue_stopped(padapter->pnetdev))
++ rtw_netif_wake_queue(padapter->pnetdev);
++
++}
++
++void sreset_reset(_adapter *padapter)
++{
++#ifdef DBG_CONFIG_ERROR_RESET
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++ struct sreset_priv *psrtpriv = &pHalData->srestpriv;
++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++ _irqL irqL;
++ u32 start = rtw_get_current_time();
++
++ DBG_871X("%s\n", __FUNCTION__);
++
++ psrtpriv->Wifi_Error_Status = WIFI_STATUS_SUCCESS;
++
++ _enter_pwrlock(&pwrpriv->lock);
++
++ psrtpriv->silent_reset_inprogress = _TRUE;
++ pwrpriv->change_rfpwrstate = rf_off;
++
++ sreset_stop_adapter(padapter);
++ #ifdef CONFIG_CONCURRENT_MODE
++ sreset_stop_adapter(padapter->pbuddy_adapter);
++ #endif
++
++ #ifdef CONFIG_IPS
++ _ips_enter(padapter);
++ _ips_leave(padapter);
++ #endif
++
++ sreset_start_adapter(padapter);
++ #ifdef CONFIG_CONCURRENT_MODE
++ sreset_start_adapter(padapter->pbuddy_adapter);
++ #endif
++
++ psrtpriv->silent_reset_inprogress = _FALSE;
++
++ _exit_pwrlock(&pwrpriv->lock);
++
++ DBG_871X("%s done in %d ms\n", __FUNCTION__, rtw_get_passing_time_ms(start));
++#endif
++}
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/core/rtw_sta_mgt.c linux-xbian-rpi/drivers/net/wireless/rtl8192cu/core/rtw_sta_mgt.c
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/core/rtw_sta_mgt.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/core/rtw_sta_mgt.c 2015-07-28 01:20:58.305654202 +0200
+@@ -0,0 +1,847 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#define _RTW_STA_MGT_C_
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++#include <recv_osdep.h>
++#include <xmit_osdep.h>
++#include <mlme_osdep.h>
++
++
++#if defined (PLATFORM_LINUX) && defined (PLATFORM_WINDOWS)
++
++#error "Shall be Linux or Windows, but not both!\n"
++
++#endif
++
++#include <sta_info.h>
++
++void _rtw_init_stainfo(struct sta_info *psta);
++void _rtw_init_stainfo(struct sta_info *psta)
++{
++
++_func_enter_;
++
++ _rtw_memset((u8 *)psta, 0, sizeof (struct sta_info));
++
++ _rtw_spinlock_init(&psta->lock);
++ _rtw_init_listhead(&psta->list);
++ _rtw_init_listhead(&psta->hash_list);
++ //_rtw_init_listhead(&psta->asoc_list);
++ //_rtw_init_listhead(&psta->sleep_list);
++ //_rtw_init_listhead(&psta->wakeup_list);
++
++ _rtw_init_queue(&psta->sleep_q);
++ psta->sleepq_len = 0;
++
++ _rtw_init_sta_xmit_priv(&psta->sta_xmitpriv);
++ _rtw_init_sta_recv_priv(&psta->sta_recvpriv);
++
++#ifdef CONFIG_AP_MODE
++
++ _rtw_init_listhead(&psta->asoc_list);
++
++ _rtw_init_listhead(&psta->auth_list);
++
++ psta->expire_to = 0;
++
++ psta->flags = 0;
++
++ psta->capability = 0;
++
++ psta->bpairwise_key_installed = _FALSE;
++
++
++#ifdef CONFIG_NATIVEAP_MLME
++ psta->nonerp_set = 0;
++ psta->no_short_slot_time_set = 0;
++ psta->no_short_preamble_set = 0;
++ psta->no_ht_gf_set = 0;
++ psta->no_ht_set = 0;
++ psta->ht_20mhz_set = 0;
++#endif
++
++#ifdef CONFIG_TX_MCAST2UNI
++ psta->under_exist_checking = 0;
++#endif // CONFIG_TX_MCAST2UNI
++
++ psta->keep_alive_trycnt = 0;
++
++#endif // CONFIG_AP_MODE
++
++_func_exit_;
++
++}
++
++u32 _rtw_init_sta_priv(struct sta_priv *pstapriv)
++{
++ struct sta_info *psta;
++ s32 i;
++
++_func_enter_;
++
++ pstapriv->pallocated_stainfo_buf = rtw_zvmalloc (sizeof(struct sta_info) * NUM_STA+ 4);
++
++ if(!pstapriv->pallocated_stainfo_buf)
++ return _FAIL;
++
++ pstapriv->pstainfo_buf = pstapriv->pallocated_stainfo_buf + 4 -
++ ((SIZE_PTR)(pstapriv->pallocated_stainfo_buf ) & 3);
++
++ _rtw_init_queue(&pstapriv->free_sta_queue);
++
++ _rtw_spinlock_init(&pstapriv->sta_hash_lock);
++
++ //_rtw_init_queue(&pstapriv->asoc_q);
++ pstapriv->asoc_sta_count = 0;
++ _rtw_init_queue(&pstapriv->sleep_q);
++ _rtw_init_queue(&pstapriv->wakeup_q);
++
++ psta = (struct sta_info *)(pstapriv->pstainfo_buf);
++
++
++ for(i = 0; i < NUM_STA; i++)
++ {
++ _rtw_init_stainfo(psta);
++
++ _rtw_init_listhead(&(pstapriv->sta_hash[i]));
++
++ rtw_list_insert_tail(&psta->list, get_list_head(&pstapriv->free_sta_queue));
++
++ psta++;
++ }
++
++
++
++#ifdef CONFIG_AP_MODE
++
++ pstapriv->sta_dz_bitmap = 0;
++ pstapriv->tim_bitmap = 0;
++
++ _rtw_init_listhead(&pstapriv->asoc_list);
++ _rtw_init_listhead(&pstapriv->auth_list);
++ _rtw_spinlock_init(&pstapriv->asoc_list_lock);
++ _rtw_spinlock_init(&pstapriv->auth_list_lock);
++ pstapriv->asoc_list_cnt = 0;
++ pstapriv->auth_list_cnt = 0;
++
++ pstapriv->auth_to = 3; // 3*2 = 6 sec
++ pstapriv->assoc_to = 3;
++ //pstapriv->expire_to = 900;// 900*2 = 1800 sec = 30 min, expire after no any traffic.
++ //pstapriv->expire_to = 30;// 30*2 = 60 sec = 1 min, expire after no any traffic.
++#ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK
++ pstapriv->expire_to = 3; // 3*2 = 6 sec
++#else
++ pstapriv->expire_to = 60;// 60*2 = 120 sec = 2 min, expire after no any traffic.
++#endif
++ pstapriv->max_num_sta = NUM_STA;
++
++#endif
++
++_func_exit_;
++
++ return _SUCCESS;
++
++}
++
++inline int rtw_stainfo_offset(struct sta_priv *stapriv, struct sta_info *sta)
++{
++ int offset = (((u8 *)sta) - stapriv->pstainfo_buf)/sizeof(struct sta_info);
++
++ if (!stainfo_offset_valid(offset))
++ DBG_871X("%s invalid offset(%d), out of range!!!", __func__, offset);
++
++ return offset;
++}
++
++inline struct sta_info *rtw_get_stainfo_by_offset(struct sta_priv *stapriv, int offset)
++{
++ if (!stainfo_offset_valid(offset))
++ DBG_871X("%s invalid offset(%d), out of range!!!", __func__, offset);
++
++ return (struct sta_info *)(stapriv->pstainfo_buf + offset * sizeof(struct sta_info));
++}
++
++void _rtw_free_sta_xmit_priv_lock(struct sta_xmit_priv *psta_xmitpriv);
++void _rtw_free_sta_xmit_priv_lock(struct sta_xmit_priv *psta_xmitpriv)
++{
++_func_enter_;
++
++ _rtw_spinlock_free(&psta_xmitpriv->lock);
++
++ _rtw_spinlock_free(&(psta_xmitpriv->be_q.sta_pending.lock));
++ _rtw_spinlock_free(&(psta_xmitpriv->bk_q.sta_pending.lock));
++ _rtw_spinlock_free(&(psta_xmitpriv->vi_q.sta_pending.lock));
++ _rtw_spinlock_free(&(psta_xmitpriv->vo_q.sta_pending.lock));
++_func_exit_;
++}
++
++static void _rtw_free_sta_recv_priv_lock(struct sta_recv_priv *psta_recvpriv)
++{
++_func_enter_;
++
++ _rtw_spinlock_free(&psta_recvpriv->lock);
++
++ _rtw_spinlock_free(&(psta_recvpriv->defrag_q.lock));
++
++_func_exit_;
++
++}
++
++void rtw_mfree_stainfo(struct sta_info *psta);
++void rtw_mfree_stainfo(struct sta_info *psta)
++{
++_func_enter_;
++
++ if(&psta->lock != NULL)
++ _rtw_spinlock_free(&psta->lock);
++
++ _rtw_free_sta_xmit_priv_lock(&psta->sta_xmitpriv);
++ _rtw_free_sta_recv_priv_lock(&psta->sta_recvpriv);
++
++_func_exit_;
++}
++
++
++// this function is used to free the memory of lock || sema for all stainfos
++void rtw_mfree_all_stainfo(struct sta_priv *pstapriv );
++void rtw_mfree_all_stainfo(struct sta_priv *pstapriv )
++{
++ _irqL irqL;
++ _list *plist, *phead;
++ struct sta_info *psta = NULL;
++
++_func_enter_;
++
++ _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
++
++ phead = get_list_head(&pstapriv->free_sta_queue);
++ plist = get_next(phead);
++
++ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE)
++ {
++ psta = LIST_CONTAINOR(plist, struct sta_info ,list);
++ plist = get_next(plist);
++
++ rtw_mfree_stainfo(psta);
++ }
++
++ _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
++
++_func_exit_;
++
++}
++
++void rtw_mfree_sta_priv_lock(struct sta_priv *pstapriv);
++void rtw_mfree_sta_priv_lock(struct sta_priv *pstapriv)
++{
++#ifdef CONFIG_AP_MODE
++ struct wlan_acl_pool *pacl_list = &pstapriv->acl_list;
++#endif
++
++ rtw_mfree_all_stainfo(pstapriv); //be done before free sta_hash_lock
++
++ _rtw_spinlock_free(&pstapriv->free_sta_queue.lock);
++
++ _rtw_spinlock_free(&pstapriv->sta_hash_lock);
++ _rtw_spinlock_free(&pstapriv->wakeup_q.lock);
++ _rtw_spinlock_free(&pstapriv->sleep_q.lock);
++
++#ifdef CONFIG_AP_MODE
++ _rtw_spinlock_free(&pstapriv->asoc_list_lock);
++ _rtw_spinlock_free(&pstapriv->auth_list_lock);
++ _rtw_spinlock_free(&pacl_list->acl_node_q.lock);
++#endif
++
++}
++
++u32 _rtw_free_sta_priv(struct sta_priv *pstapriv)
++{
++ _irqL irqL;
++ _list *phead, *plist;
++ struct sta_info *psta = NULL;
++ struct recv_reorder_ctrl *preorder_ctrl;
++ int index;
++
++_func_enter_;
++ if(pstapriv){
++
++ /* delete all reordering_ctrl_timer */
++ _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
++ for(index = 0; index < NUM_STA; index++)
++ {
++ phead = &(pstapriv->sta_hash[index]);
++ plist = get_next(phead);
++
++ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE)
++ {
++ int i;
++ psta = LIST_CONTAINOR(plist, struct sta_info ,hash_list);
++ plist = get_next(plist);
++
++ for(i=0; i < 16 ; i++)
++ {
++ preorder_ctrl = &psta->recvreorder_ctrl[i];
++ _cancel_timer_ex(&preorder_ctrl->reordering_ctrl_timer);
++ }
++ }
++ }
++ _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
++ /*===============================*/
++
++ rtw_mfree_sta_priv_lock(pstapriv);
++
++ if(pstapriv->pallocated_stainfo_buf) {
++ rtw_vmfree(pstapriv->pallocated_stainfo_buf, sizeof(struct sta_info)*NUM_STA+4);
++ }
++ }
++
++_func_exit_;
++ return _SUCCESS;
++}
++
++
++//struct sta_info *rtw_alloc_stainfo(_queue *pfree_sta_queue, unsigned char *hwaddr)
++struct sta_info *rtw_alloc_stainfo(struct sta_priv *pstapriv, u8 *hwaddr)
++{
++ _irqL irqL, irqL2;
++ uint tmp_aid;
++ s32 index;
++ _list *phash_list;
++ struct sta_info *psta;
++ _queue *pfree_sta_queue;
++ struct recv_reorder_ctrl *preorder_ctrl;
++ int i = 0;
++ u16 wRxSeqInitialValue = 0xffff;
++
++_func_enter_;
++
++ pfree_sta_queue = &pstapriv->free_sta_queue;
++
++ //_enter_critical_bh(&(pfree_sta_queue->lock), &irqL);
++ _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL2);
++
++ if (_rtw_queue_empty(pfree_sta_queue) == _TRUE)
++ {
++ //_exit_critical_bh(&(pfree_sta_queue->lock), &irqL);
++ _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL2);
++ psta = NULL;
++ }
++ else
++ {
++ psta = LIST_CONTAINOR(get_next(&pfree_sta_queue->queue), struct sta_info, list);
++
++ rtw_list_delete(&(psta->list));
++
++ //_exit_critical_bh(&(pfree_sta_queue->lock), &irqL);
++
++ tmp_aid = psta->aid;
++
++ _rtw_init_stainfo(psta);
++
++ _rtw_memcpy(psta->hwaddr, hwaddr, ETH_ALEN);
++
++ index = wifi_mac_hash(hwaddr);
++
++ RT_TRACE(_module_rtl871x_sta_mgt_c_,_drv_info_,("rtw_alloc_stainfo: index = %x", index));
++
++ if(index >= NUM_STA){
++ RT_TRACE(_module_rtl871x_sta_mgt_c_,_drv_err_,("ERROR=> rtw_alloc_stainfo: index >= NUM_STA"));
++ psta= NULL;
++ goto exit;
++ }
++ phash_list = &(pstapriv->sta_hash[index]);
++
++ //_enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL2);
++
++ rtw_list_insert_tail(&psta->hash_list, phash_list);
++
++ pstapriv->asoc_sta_count ++ ;
++
++ //_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL2);
++
++// Commented by Albert 2009/08/13
++// For the SMC router, the sequence number of first packet of WPS handshake will be 0.
++// In this case, this packet will be dropped by recv_decache function if we use the 0x00 as the default value for tid_rxseq variable.
++// So, we initialize the tid_rxseq variable as the 0xffff.
++
++ for( i = 0; i < 16; i++ )
++ {
++ _rtw_memcpy( &psta->sta_recvpriv.rxcache.tid_rxseq[ i ], &wRxSeqInitialValue, 2 );
++ }
++
++ RT_TRACE(_module_rtl871x_sta_mgt_c_,_drv_info_,("alloc number_%d stainfo with hwaddr = %x %x %x %x %x %x \n",
++ pstapriv->asoc_sta_count , hwaddr[0], hwaddr[1], hwaddr[2],hwaddr[3],hwaddr[4],hwaddr[5]));
++
++ init_addba_retry_timer(pstapriv->padapter, psta);
++
++#ifdef CONFIG_TDLS
++ psta->padapter = pstapriv->padapter;
++ init_TPK_timer(pstapriv->padapter, psta);
++ init_ch_switch_timer(pstapriv->padapter, psta);
++ init_base_ch_timer(pstapriv->padapter, psta);
++ init_off_ch_timer(pstapriv->padapter, psta);
++ init_handshake_timer(pstapriv->padapter, psta);
++ init_tdls_alive_timer(pstapriv->padapter, psta);
++#endif //CONFIG_TDLS
++
++ //for A-MPDU Rx reordering buffer control
++ for(i=0; i < 16 ; i++)
++ {
++ preorder_ctrl = &psta->recvreorder_ctrl[i];
++
++ preorder_ctrl->padapter = pstapriv->padapter;
++
++ preorder_ctrl->enable = _FALSE;
++
++ preorder_ctrl->indicate_seq = 0xffff;
++ #ifdef DBG_RX_SEQ
++ DBG_871X("DBG_RX_SEQ %s:%d IndicateSeq: %d\n", __FUNCTION__, __LINE__,
++ preorder_ctrl->indicate_seq);
++ #endif
++ preorder_ctrl->wend_b= 0xffff;
++ //preorder_ctrl->wsize_b = (NR_RECVBUFF-2);
++ preorder_ctrl->wsize_b = 64;//64;
++
++ _rtw_init_queue(&preorder_ctrl->pending_recvframe_queue);
++
++ rtw_init_recv_timer(preorder_ctrl);
++ }
++
++
++ //init for DM
++ psta->rssi_stat.UndecoratedSmoothedPWDB = 0;
++ psta->rssi_stat.UndecoratedSmoothedCCK = (-1);
++
++ /* init for the sequence number of received management frame */
++ psta->RxMgmtFrameSeqNum = 0xffff;
++ }
++
++exit:
++
++ _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL2);
++
++_func_exit_;
++
++ return psta;
++
++
++}
++
++
++// using pstapriv->sta_hash_lock to protect
++u32 rtw_free_stainfo(_adapter *padapter , struct sta_info *psta)
++{
++ int i;
++ _irqL irqL0;
++ _queue *pfree_sta_queue;
++ struct recv_reorder_ctrl *preorder_ctrl;
++ struct sta_xmit_priv *pstaxmitpriv;
++ struct xmit_priv *pxmitpriv= &padapter->xmitpriv;
++ struct sta_priv *pstapriv = &padapter->stapriv;
++ struct hw_xmit *phwxmit;
++
++
++_func_enter_;
++
++ if (psta == NULL)
++ goto exit;
++
++
++ _enter_critical_bh(&psta->lock, &irqL0);
++ psta->state &= ~_FW_LINKED;
++ _exit_critical_bh(&psta->lock, &irqL0);
++
++ pfree_sta_queue = &pstapriv->free_sta_queue;
++
++
++ pstaxmitpriv = &psta->sta_xmitpriv;
++
++ //rtw_list_delete(&psta->sleep_list);
++
++ //rtw_list_delete(&psta->wakeup_list);
++
++ _enter_critical_bh(&pxmitpriv->lock, &irqL0);
++
++ rtw_free_xmitframe_queue(pxmitpriv, &psta->sleep_q);
++ psta->sleepq_len = 0;
++
++ //vo
++ //_enter_critical_bh(&(pxmitpriv->vo_pending.lock), &irqL0);
++ rtw_free_xmitframe_queue( pxmitpriv, &pstaxmitpriv->vo_q.sta_pending);
++ rtw_list_delete(&(pstaxmitpriv->vo_q.tx_pending));
++ phwxmit = pxmitpriv->hwxmits;
++ phwxmit->accnt -= pstaxmitpriv->vo_q.qcnt;
++ pstaxmitpriv->vo_q.qcnt = 0;
++ //_exit_critical_bh(&(pxmitpriv->vo_pending.lock), &irqL0);
++
++ //vi
++ //_enter_critical_bh(&(pxmitpriv->vi_pending.lock), &irqL0);
++ rtw_free_xmitframe_queue( pxmitpriv, &pstaxmitpriv->vi_q.sta_pending);
++ rtw_list_delete(&(pstaxmitpriv->vi_q.tx_pending));
++ phwxmit = pxmitpriv->hwxmits+1;
++ phwxmit->accnt -= pstaxmitpriv->vi_q.qcnt;
++ pstaxmitpriv->vi_q.qcnt = 0;
++ //_exit_critical_bh(&(pxmitpriv->vi_pending.lock), &irqL0);
++
++ //be
++ //_enter_critical_bh(&(pxmitpriv->be_pending.lock), &irqL0);
++ rtw_free_xmitframe_queue( pxmitpriv, &pstaxmitpriv->be_q.sta_pending);
++ rtw_list_delete(&(pstaxmitpriv->be_q.tx_pending));
++ phwxmit = pxmitpriv->hwxmits+2;
++ phwxmit->accnt -= pstaxmitpriv->be_q.qcnt;
++ pstaxmitpriv->be_q.qcnt = 0;
++ //_exit_critical_bh(&(pxmitpriv->be_pending.lock), &irqL0);
++
++ //bk
++ //_enter_critical_bh(&(pxmitpriv->bk_pending.lock), &irqL0);
++ rtw_free_xmitframe_queue( pxmitpriv, &pstaxmitpriv->bk_q.sta_pending);
++ rtw_list_delete(&(pstaxmitpriv->bk_q.tx_pending));
++ phwxmit = pxmitpriv->hwxmits+3;
++ phwxmit->accnt -= pstaxmitpriv->bk_q.qcnt;
++ pstaxmitpriv->bk_q.qcnt = 0;
++ //_exit_critical_bh(&(pxmitpriv->bk_pending.lock), &irqL0);
++
++ _exit_critical_bh(&pxmitpriv->lock, &irqL0);
++
++ rtw_list_delete(&psta->hash_list);
++ RT_TRACE(_module_rtl871x_sta_mgt_c_,_drv_err_,("\n free number_%d stainfo with hwaddr = 0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x \n",pstapriv->asoc_sta_count , psta->hwaddr[0], psta->hwaddr[1], psta->hwaddr[2],psta->hwaddr[3],psta->hwaddr[4],psta->hwaddr[5]));
++ pstapriv->asoc_sta_count --;
++
++
++ // re-init sta_info; 20061114 // will be init in alloc_stainfo
++ //_rtw_init_sta_xmit_priv(&psta->sta_xmitpriv);
++ //_rtw_init_sta_recv_priv(&psta->sta_recvpriv);
++
++ _cancel_timer_ex(&psta->addba_retry_timer);
++
++#ifdef CONFIG_TDLS
++ _cancel_timer_ex(&psta->TPK_timer);
++ _cancel_timer_ex(&psta->option_timer);
++ _cancel_timer_ex(&psta->base_ch_timer);
++ _cancel_timer_ex(&psta->off_ch_timer);
++ _cancel_timer_ex(&psta->alive_timer1);
++ _cancel_timer_ex(&psta->alive_timer2);
++#endif //CONFIG_TDLS
++
++ //for A-MPDU Rx reordering buffer control, cancel reordering_ctrl_timer
++ for(i=0; i < 16 ; i++)
++ {
++ _irqL irqL;
++ _list *phead, *plist;
++ union recv_frame *prframe;
++ _queue *ppending_recvframe_queue;
++ _queue *pfree_recv_queue = &padapter->recvpriv.free_recv_queue;
++
++ preorder_ctrl = &psta->recvreorder_ctrl[i];
++
++ _cancel_timer_ex(&preorder_ctrl->reordering_ctrl_timer);
++
++
++ ppending_recvframe_queue = &preorder_ctrl->pending_recvframe_queue;
++
++ _enter_critical_bh(&ppending_recvframe_queue->lock, &irqL);
++
++ phead = get_list_head(ppending_recvframe_queue);
++ plist = get_next(phead);
++
++ while(!rtw_is_list_empty(phead))
++ {
++ prframe = LIST_CONTAINOR(plist, union recv_frame, u);
++
++ plist = get_next(plist);
++
++ rtw_list_delete(&(prframe->u.hdr.list));
++
++ rtw_free_recvframe(prframe, pfree_recv_queue);
++ }
++
++ _exit_critical_bh(&ppending_recvframe_queue->lock, &irqL);
++
++ }
++
++
++#ifdef CONFIG_AP_MODE
++
++/*
++ _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL0);
++ rtw_list_delete(&psta->asoc_list);
++ _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL0);
++*/
++ _enter_critical_bh(&pstapriv->auth_list_lock, &irqL0);
++ if (!rtw_is_list_empty(&psta->auth_list)) {
++ rtw_list_delete(&psta->auth_list);
++ pstapriv->auth_list_cnt--;
++ }
++ _exit_critical_bh(&pstapriv->auth_list_lock, &irqL0);
++
++ psta->expire_to = 0;
++
++ psta->sleepq_ac_len = 0;
++ psta->qos_info = 0;
++
++ psta->max_sp_len = 0;
++ psta->uapsd_bk = 0;
++ psta->uapsd_be = 0;
++ psta->uapsd_vi = 0;
++ psta->uapsd_vo = 0;
++
++ psta->has_legacy_ac = 0;
++
++#ifdef CONFIG_NATIVEAP_MLME
++
++ pstapriv->sta_dz_bitmap &=~BIT(psta->aid);
++ pstapriv->tim_bitmap &=~BIT(psta->aid);
++
++ //rtw_indicate_sta_disassoc_event(padapter, psta);
++
++ if ((psta->aid >0)&&(pstapriv->sta_aid[psta->aid - 1] == psta))
++ {
++ pstapriv->sta_aid[psta->aid - 1] = NULL;
++ psta->aid = 0;
++ }
++
++#endif // CONFIG_NATIVEAP_MLME
++
++#ifdef CONFIG_TX_MCAST2UNI
++ psta->under_exist_checking = 0;
++#endif // CONFIG_TX_MCAST2UNI
++
++#endif // CONFIG_AP_MODE
++
++ _rtw_spinlock_free(&psta->lock);
++
++ //_enter_critical_bh(&(pfree_sta_queue->lock), &irqL0);
++ rtw_list_insert_tail(&psta->list, get_list_head(pfree_sta_queue));
++ //_exit_critical_bh(&(pfree_sta_queue->lock), &irqL0);
++
++exit:
++
++_func_exit_;
++
++ return _SUCCESS;
++
++}
++
++// free all stainfo which in sta_hash[all]
++void rtw_free_all_stainfo(_adapter *padapter)
++{
++ _irqL irqL;
++ _list *plist, *phead;
++ s32 index;
++ struct sta_info *psta = NULL;
++ struct sta_priv *pstapriv = &padapter->stapriv;
++ struct sta_info* pbcmc_stainfo =rtw_get_bcmc_stainfo( padapter);
++
++_func_enter_;
++
++ if(pstapriv->asoc_sta_count==1)
++ goto exit;
++
++ _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
++
++ for(index=0; index< NUM_STA; index++)
++ {
++ phead = &(pstapriv->sta_hash[index]);
++ plist = get_next(phead);
++
++ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE)
++ {
++ psta = LIST_CONTAINOR(plist, struct sta_info ,hash_list);
++
++ plist = get_next(plist);
++
++ if(pbcmc_stainfo!=psta)
++ rtw_free_stainfo(padapter , psta);
++
++ }
++ }
++
++ _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
++
++exit:
++
++_func_exit_;
++
++}
++
++/* any station allocated can be searched by hash list */
++struct sta_info *rtw_get_stainfo(struct sta_priv *pstapriv, u8 *hwaddr)
++{
++
++ _irqL irqL;
++
++ _list *plist, *phead;
++
++ struct sta_info *psta = NULL;
++
++ u32 index;
++
++ u8 *addr;
++
++ u8 bc_addr[ETH_ALEN] = {0xff,0xff,0xff,0xff,0xff,0xff};
++
++_func_enter_;
++
++ if(hwaddr==NULL)
++ return NULL;
++
++ if(IS_MCAST(hwaddr))
++ {
++ addr = bc_addr;
++ }
++ else
++ {
++ addr = hwaddr;
++ }
++
++ index = wifi_mac_hash(addr);
++
++ _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
++
++ phead = &(pstapriv->sta_hash[index]);
++ plist = get_next(phead);
++
++
++ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE)
++ {
++
++ psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
++
++ if ((_rtw_memcmp(psta->hwaddr, addr, ETH_ALEN))== _TRUE)
++ { // if found the matched address
++ break;
++ }
++ psta=NULL;
++ plist = get_next(plist);
++ }
++
++ _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
++_func_exit_;
++ return psta;
++
++}
++
++u32 rtw_init_bcmc_stainfo(_adapter* padapter)
++{
++
++ struct sta_info *psta;
++ struct tx_servq *ptxservq;
++ u32 res=_SUCCESS;
++ NDIS_802_11_MAC_ADDRESS bcast_addr= {0xff,0xff,0xff,0xff,0xff,0xff};
++
++ struct sta_priv *pstapriv = &padapter->stapriv;
++ //_queue *pstapending = &padapter->xmitpriv.bm_pending;
++
++_func_enter_;
++
++ psta = rtw_alloc_stainfo(pstapriv, bcast_addr);
++
++ if(psta==NULL){
++ res=_FAIL;
++ RT_TRACE(_module_rtl871x_sta_mgt_c_,_drv_err_,("rtw_alloc_stainfo fail"));
++ goto exit;
++ }
++
++ // default broadcast & multicast use macid 1
++ psta->mac_id = 1;
++
++ ptxservq= &(psta->sta_xmitpriv.be_q);
++
++/*
++ _enter_critical(&pstapending->lock, &irqL0);
++
++ if (rtw_is_list_empty(&ptxservq->tx_pending))
++ rtw_list_insert_tail(&ptxservq->tx_pending, get_list_head(pstapending));
++
++ _exit_critical(&pstapending->lock, &irqL0);
++*/
++
++exit:
++_func_exit_;
++ return _SUCCESS;
++
++}
++
++
++struct sta_info* rtw_get_bcmc_stainfo(_adapter* padapter)
++{
++ struct sta_info *psta;
++ struct sta_priv *pstapriv = &padapter->stapriv;
++ u8 bc_addr[ETH_ALEN] = {0xff,0xff,0xff,0xff,0xff,0xff};
++_func_enter_;
++ psta = rtw_get_stainfo(pstapriv, bc_addr);
++_func_exit_;
++ return psta;
++
++}
++
++u8 rtw_access_ctrl(_adapter *padapter, u8 *mac_addr)
++{
++ u8 res = _TRUE;
++#ifdef CONFIG_AP_MODE
++ _irqL irqL;
++ _list *plist, *phead;
++ struct rtw_wlan_acl_node *paclnode;
++ u8 match = _FALSE;
++ struct sta_priv *pstapriv = &padapter->stapriv;
++ struct wlan_acl_pool *pacl_list = &pstapriv->acl_list;
++ _queue *pacl_node_q =&pacl_list->acl_node_q;
++
++ _enter_critical_bh(&(pacl_node_q->lock), &irqL);
++ phead = get_list_head(pacl_node_q);
++ plist = get_next(phead);
++ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE)
++ {
++ paclnode = LIST_CONTAINOR(plist, struct rtw_wlan_acl_node, list);
++ plist = get_next(plist);
++
++ if(_rtw_memcmp(paclnode->addr, mac_addr, ETH_ALEN))
++ {
++ if(paclnode->valid == _TRUE)
++ {
++ match = _TRUE;
++ break;
++ }
++ }
++ }
++ _exit_critical_bh(&(pacl_node_q->lock), &irqL);
++
++
++ if(pacl_list->mode == 1)//accept unless in deny list
++ {
++ res = (match == _TRUE) ? _FALSE:_TRUE;
++ }
++ else if(pacl_list->mode == 2)//deny unless in accept list
++ {
++ res = (match == _TRUE) ? _TRUE:_FALSE;
++ }
++ else
++ {
++ res = _TRUE;
++ }
++
++#endif
++
++ return res;
++
++}
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/core/rtw_tdls.c linux-xbian-rpi/drivers/net/wireless/rtl8192cu/core/rtw_tdls.c
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/core/rtw_tdls.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/core/rtw_tdls.c 2015-07-28 01:20:58.305654202 +0200
+@@ -0,0 +1,2940 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#define _RTW_TDLS_C_
++
++#include <drv_types.h>
++#include <ethernet.h>
++#include <rtw_tdls.h>
++#include <wifi.h>
++
++#ifdef CONFIG_TDLS
++extern unsigned char MCS_rate_2R[16];
++extern unsigned char MCS_rate_1R[16];
++extern void process_wmmps_data(_adapter *padapter, union recv_frame *precv_frame);
++extern s32 rtw_dump_xframe(_adapter *padapter, struct xmit_frame *pxmitframe);
++
++void rtw_reset_tdls_info(_adapter* padapter)
++{
++ struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
++
++ ptdlsinfo->ap_prohibited = _FALSE;
++ ptdlsinfo->setup_state = TDLS_STATE_NONE;
++ ptdlsinfo->sta_cnt = 0;
++ ptdlsinfo->sta_maximum = _FALSE;
++ ptdlsinfo->macid_index= 6;
++ ptdlsinfo->clear_cam= 0;
++ ptdlsinfo->ch_sensing = 0;
++ ptdlsinfo->cur_channel = 0;
++ ptdlsinfo->candidate_ch = 1; //when inplement channel switching, default candidate channel is 1
++ ptdlsinfo->watchdog_count = 0;
++ ptdlsinfo->dev_discovered = 0;
++
++#ifdef CONFIG_WFD
++ ptdlsinfo->wfd_info = &padapter->wfd_info;
++#endif //CONFIG_WFD
++}
++
++int rtw_init_tdls_info(_adapter* padapter)
++{
++ int res = _SUCCESS;
++ struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
++
++ ptdlsinfo->enable = 1;
++ rtw_reset_tdls_info(padapter);
++
++ _rtw_spinlock_init(&ptdlsinfo->cmd_lock);
++ _rtw_spinlock_init(&ptdlsinfo->hdl_lock);
++
++ return res;
++
++}
++
++void rtw_free_tdls_info(struct tdls_info *ptdlsinfo)
++{
++ _rtw_spinlock_free(&ptdlsinfo->cmd_lock);
++ _rtw_spinlock_free(&ptdlsinfo->hdl_lock);
++
++ _rtw_memset(ptdlsinfo, 0, sizeof(struct tdls_info) );
++
++}
++
++void issue_nulldata_to_TDLS_peer_STA(_adapter *padapter, struct sta_info *ptdls_sta, unsigned int power_mode)
++{
++ struct xmit_frame *pmgntframe;
++ struct pkt_attrib *pattrib;
++ unsigned char *pframe;
++ struct rtw_ieee80211_hdr *pwlanhdr;
++ unsigned short *fctrl;
++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++
++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL)
++ {
++ return;
++ }
++
++ //update attribute
++ pattrib = &pmgntframe->attrib;
++ update_mgntframe_attrib(padapter, pattrib);
++
++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++ fctrl = &(pwlanhdr->frame_ctl);
++ *(fctrl) = 0;
++// SetToDs(fctrl);
++ if (power_mode)
++ {
++ SetPwrMgt(fctrl);
++ }
++
++ _rtw_memcpy(pwlanhdr->addr1, ptdls_sta->hwaddr, ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
++
++ ptdls_sta->sta_xmitpriv.txseq_tid[pattrib->priority]++;
++ ptdls_sta->sta_xmitpriv.txseq_tid[pattrib->priority] &= 0xFFF;
++ pattrib->seqnum = ptdls_sta->sta_xmitpriv.txseq_tid[pattrib->priority];
++ SetSeqNum(pwlanhdr, pattrib->seqnum);
++
++ SetFrameSubType(pframe, WIFI_DATA_NULL);
++
++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
++ pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++
++ pattrib->last_txcmdsz = pattrib->pktlen;
++ dump_mgntframe(padapter, pmgntframe);
++
++ return;
++}
++
++s32 update_tdls_attrib(_adapter *padapter, struct pkt_attrib *pattrib)
++{
++
++ struct sta_info *psta = NULL;
++ struct sta_priv *pstapriv = &padapter->stapriv;
++ struct security_priv *psecuritypriv = &padapter->securitypriv;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct qos_priv *pqospriv= &pmlmepriv->qospriv;
++
++ s32 res=_SUCCESS;
++ sint bmcast;
++
++ bmcast = IS_MCAST(pattrib->ra);
++
++ psta = rtw_get_stainfo(pstapriv, pattrib->ra);
++ if (psta == NULL) {
++ res =_FAIL;
++ goto exit;
++ }
++
++ pattrib->mac_id = psta->mac_id;
++
++ pattrib->psta = psta;
++
++ pattrib->ack_policy = 0;
++ // get ether_hdr_len
++ pattrib->pkt_hdrlen = ETH_HLEN;//(pattrib->ether_type == 0x8100) ? (14 + 4 ): 14; //vlan tag
++
++ if (pqospriv->qos_option && psta->qos_option) {
++ pattrib->priority = 1; //tdls management frame should be AC_BK
++ pattrib->hdrlen = WLAN_HDR_A3_QOS_LEN;
++ pattrib->subtype = WIFI_QOS_DATA_TYPE;
++ } else {
++ pattrib->hdrlen = WLAN_HDR_A3_LEN;
++ pattrib->subtype = WIFI_DATA_TYPE;
++ pattrib->priority = 0;
++ }
++
++ if (psta->ieee8021x_blocked == _TRUE)
++ {
++ pattrib->encrypt = 0;
++ }
++ else
++ {
++ GET_ENCRY_ALGO(psecuritypriv, psta, pattrib->encrypt, bmcast);
++
++ switch(psecuritypriv->dot11AuthAlgrthm)
++ {
++ case dot11AuthAlgrthm_Open:
++ case dot11AuthAlgrthm_Shared:
++ case dot11AuthAlgrthm_Auto:
++ pattrib->key_idx = (u8)psecuritypriv->dot11PrivacyKeyIndex;
++ break;
++ case dot11AuthAlgrthm_8021X:
++ pattrib->key_idx = 0;
++ break;
++ default:
++ pattrib->key_idx = 0;
++ break;
++ }
++ }
++
++ switch (pattrib->encrypt)
++ {
++ case _WEP40_:
++ case _WEP104_:
++ pattrib->iv_len = 4;
++ pattrib->icv_len = 4;
++ break;
++ case _TKIP_:
++ pattrib->iv_len = 8;
++ pattrib->icv_len = 4;
++ if(padapter->securitypriv.busetkipkey==_FAIL)
++ {
++ res =_FAIL;
++ goto exit;
++ }
++ break;
++ case _AES_:
++ pattrib->iv_len = 8;
++ pattrib->icv_len = 8;
++ break;
++ default:
++ pattrib->iv_len = 0;
++ pattrib->icv_len = 0;
++ break;
++ }
++
++ if (pattrib->encrypt &&
++ ((padapter->securitypriv.sw_encrypt == _TRUE) || (psecuritypriv->hw_decrypted == _FALSE)))
++ {
++ pattrib->bswenc = _TRUE;
++ } else {
++ pattrib->bswenc = _FALSE;
++ }
++
++ //qos_en, ht_en, init rate, ,bw, ch_offset, sgi
++ pattrib->qos_en = psta->qos_option;
++ pattrib->ht_en = psta->htpriv.ht_option;
++ pattrib->raid = psta->raid;
++ pattrib->bwmode = psta->htpriv.bwmode;
++ pattrib->ch_offset = psta->htpriv.ch_offset;
++ pattrib->sgi= psta->htpriv.sgi;
++ pattrib->ampdu_en = _FALSE;
++
++ //if(pattrib->ht_en && psta->htpriv.ampdu_enable)
++ //{
++ // if(psta->htpriv.agg_enable_bitmap & BIT(pattrib->priority))
++ // pattrib->ampdu_en = _TRUE;
++ //}
++
++exit:
++
++ return res;
++}
++
++void free_tdls_sta(_adapter *padapter, struct sta_info *ptdls_sta)
++{
++ struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
++ struct sta_priv *pstapriv = &padapter->stapriv;
++ _irqL irqL;
++
++ //free peer sta_info
++ _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL);
++ if(ptdlsinfo->sta_cnt != 0)
++ ptdlsinfo->sta_cnt--;
++ _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);
++ if( ptdlsinfo->sta_cnt < (NUM_STA - 2) ) // -2: AP + BC/MC sta
++ {
++ ptdlsinfo->sta_maximum = _FALSE;
++ _rtw_memset( &ptdlsinfo->ss_record, 0x00, sizeof(struct tdls_ss_record) );
++ }
++ //ready to clear cam
++ if(ptdls_sta->mac_id!=0){
++ ptdlsinfo->clear_cam=ptdls_sta->mac_id;
++ rtw_setstakey_cmd(padapter, (u8 *)ptdls_sta, _TRUE);
++ }
++
++ if(ptdlsinfo->sta_cnt==0){
++ rtw_tdls_cmd(padapter, myid(&(padapter->eeprompriv)), TDLS_RS_RCR);
++ ptdlsinfo->setup_state=TDLS_STATE_NONE;
++ }
++ else
++ DBG_871X("Remain tdls sta:%02x\n", ptdlsinfo->sta_cnt);
++
++ rtw_free_stainfo(padapter, ptdls_sta);
++
++}
++
++// cam entry will be the same as mac_id
++void rtw_tdls_set_mac_id(struct tdls_info *ptdlsinfo, struct sta_info *ptdls_sta)
++{
++ if(ptdls_sta->mac_id==0)
++ {
++ ptdls_sta->mac_id = ptdlsinfo->macid_index;
++ if( (++ptdlsinfo->macid_index) > (NUM_STA -2) )
++ ptdlsinfo->macid_index= TDLS_INI_MACID_ENTRY;
++ }
++}
++
++//TDLS encryption(if needed) will always be CCMP
++void rtw_tdls_set_key(_adapter *adapter, struct rx_pkt_attrib *prx_pkt_attrib, struct sta_info *ptdls_sta)
++{
++ if(prx_pkt_attrib->encrypt)
++ {
++ ptdls_sta->dot118021XPrivacy=_AES_;
++ rtw_setstakey_cmd(adapter, (u8*)ptdls_sta, _TRUE);
++ }
++}
++
++void rtw_tdls_process_ht_cap(_adapter *adapter, struct sta_info *ptdls_sta, u8 *data, u8 Length)
++{
++ /* save HT capabilities in the sta object */
++ _rtw_memset(&ptdls_sta->htpriv.ht_cap, 0, sizeof(struct rtw_ieee80211_ht_cap));
++ if (data && Length >= sizeof(struct rtw_ieee80211_ht_cap) )
++ {
++ ptdls_sta->flags |= WLAN_STA_HT;
++
++ ptdls_sta->flags |= WLAN_STA_WME;
++
++ _rtw_memcpy(&ptdls_sta->htpriv.ht_cap, data, sizeof(struct rtw_ieee80211_ht_cap));
++
++ } else
++ ptdls_sta->flags &= ~WLAN_STA_HT;
++
++ if(ptdls_sta->flags & WLAN_STA_HT)
++ {
++ if(adapter->registrypriv.ht_enable == _TRUE)
++ {
++ ptdls_sta->htpriv.ht_option = _TRUE;
++ }
++ else
++ {
++ ptdls_sta->htpriv.ht_option = _FALSE;
++ ptdls_sta->stat_code = _STATS_FAILURE_;
++ }
++ }
++
++ //HT related cap
++ if(ptdls_sta->htpriv.ht_option)
++ {
++ //check if sta supports rx ampdu
++ if(adapter->registrypriv.ampdu_enable==1)
++ ptdls_sta->htpriv.ampdu_enable = _TRUE;
++
++ //check if sta support s Short GI
++ if(ptdls_sta->htpriv.ht_cap.cap_info & cpu_to_le16(IEEE80211_HT_CAP_SGI_20|IEEE80211_HT_CAP_SGI_40))
++ {
++ ptdls_sta->htpriv.sgi = _TRUE;
++ }
++
++ // bwmode would still followed AP's setting
++ if(ptdls_sta->htpriv.ht_cap.cap_info & cpu_to_le16(IEEE80211_HT_CAP_SUP_WIDTH))
++ {
++ ptdls_sta->htpriv.bwmode = adapter->mlmeextpriv.cur_bwmode;
++ ptdls_sta->htpriv.ch_offset = adapter->mlmeextpriv.cur_ch_offset;
++ }
++ }
++}
++
++u8 *rtw_tdls_set_ht_cap(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattrib)
++{
++ struct rtw_ieee80211_ht_cap ht_capie;
++ u8 rf_type;
++
++ //HT capabilities
++ _rtw_memset(&ht_capie, 0, sizeof(struct rtw_ieee80211_ht_cap));
++
++ ht_capie.cap_info = IEEE80211_HT_CAP_SUP_WIDTH |IEEE80211_HT_CAP_SGI_20 |IEEE80211_HT_CAP_SM_PS |
++ IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_TX_STBC |IEEE80211_HT_CAP_DSSSCCK40;
++
++ {
++ u32 rx_packet_offset, max_recvbuf_sz;
++ rtw_hal_get_def_var(padapter, HAL_DEF_RX_PACKET_OFFSET, &rx_packet_offset);
++ rtw_hal_get_def_var(padapter, HAL_DEF_MAX_RECVBUF_SZ, &max_recvbuf_sz);
++ if(max_recvbuf_sz-rx_packet_offset>(8191-256))
++ ht_capie.cap_info = ht_capie.cap_info |IEEE80211_HT_CAP_MAX_AMSDU;
++ }
++
++ ht_capie.ampdu_params_info = (IEEE80211_HT_CAP_AMPDU_FACTOR&0x03);
++
++ rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));
++ switch(rf_type)
++ {
++ case RF_1T1R:
++ ht_capie.cap_info |= 0x0100;//RX STBC One spatial stream
++ _rtw_memcpy(ht_capie.supp_mcs_set, MCS_rate_1R, 16);
++ break;
++
++ case RF_2T2R:
++ case RF_1T2R:
++ default:
++ ht_capie.cap_info|= 0x0200;//RX STBC two spatial stream
++ _rtw_memcpy(ht_capie.supp_mcs_set, MCS_rate_2R, 16);
++ break;
++ }
++
++ return(rtw_set_ie(pframe, _HT_CAPABILITY_IE_,
++ sizeof(struct rtw_ieee80211_ht_cap), (unsigned char*)&ht_capie, &(pattrib->pktlen)));
++}
++
++u8 *rtw_tdls_set_sup_ch(struct mlme_ext_priv *pmlmeext, u8 *pframe, struct pkt_attrib *pattrib)
++{
++ u8 sup_ch[ 30 * 2 ] = { 0x00 }, sup_ch_idx = 0, idx_5g = 2; //For supported channel
++ do{
++ if( pmlmeext->channel_set[sup_ch_idx].ChannelNum <= 14 )
++ {
++ sup_ch[0] = 1; //First channel number
++ sup_ch[1] = pmlmeext->channel_set[sup_ch_idx].ChannelNum; //Number of channel
++ }
++ else
++ {
++ sup_ch[idx_5g++] = pmlmeext->channel_set[sup_ch_idx].ChannelNum;
++ sup_ch[idx_5g++] = 1;
++ }
++
++ sup_ch_idx++;
++ }
++ while( pmlmeext->channel_set[sup_ch_idx].ChannelNum != 0 );
++ return(rtw_set_ie(pframe, _SUPPORTED_CH_IE_, idx_5g, sup_ch, &(pattrib->pktlen)));
++}
++
++#ifdef CONFIG_WFD
++void rtw_tdls_process_wfd_ie(struct tdls_info *ptdlsinfo, u8 *ptr, u8 length)
++{
++ u8 wfd_ie[ 128 ] = { 0x00 };
++ u32 wfd_ielen = 0;
++ u32 wfd_offset = 0;
++ // Try to get the TCP port information when receiving the negotiation response.
++ //
++
++ wfd_offset = 0;
++ wfd_offset = rtw_get_wfd_ie( ptr + wfd_offset, length - wfd_offset, wfd_ie, &wfd_ielen );
++ while( wfd_offset )
++ {
++ u8 attr_content[ 10 ] = { 0x00 };
++ u32 attr_contentlen = 0;
++ int i;
++
++ DBG_871X( "[%s] WFD IE Found!!\n", __FUNCTION__ );
++ rtw_get_wfd_attr_content( wfd_ie, wfd_ielen, WFD_ATTR_DEVICE_INFO, attr_content, &attr_contentlen);
++ if ( attr_contentlen )
++ {
++ ptdlsinfo->wfd_info->peer_rtsp_ctrlport = RTW_GET_BE16( attr_content + 2 );
++ DBG_871X( "[%s] Peer PORT NUM = %d\n", __FUNCTION__, ptdlsinfo->wfd_info->peer_rtsp_ctrlport );
++ }
++
++ _rtw_memset( attr_content, 0x00, 10);
++ attr_contentlen = 0;
++ rtw_get_wfd_attr_content( wfd_ie, wfd_ielen, WFD_ATTR_LOCAL_IP_ADDR, attr_content, &attr_contentlen);
++ if ( attr_contentlen )
++ {
++ _rtw_memcpy(ptdlsinfo->wfd_info->peer_ip_address, ( attr_content + 1 ), 4);
++ DBG_871X( "[%s] Peer IP = %02u.%02u.%02u.%02u \n", __FUNCTION__,
++ ptdlsinfo->wfd_info->peer_ip_address[0], ptdlsinfo->wfd_info->peer_ip_address[1],
++ ptdlsinfo->wfd_info->peer_ip_address[2], ptdlsinfo->wfd_info->peer_ip_address[3]
++ );
++ }
++ wfd_offset = rtw_get_wfd_ie( ptr + wfd_offset, length - wfd_offset, wfd_ie, &wfd_ielen );
++ }
++}
++
++void issue_tunneled_probe_req(_adapter *padapter)
++{
++ struct xmit_frame *pmgntframe;
++ struct pkt_attrib *pattrib;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
++ u8 baddr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
++
++ DBG_871X("[%s]\n", __FUNCTION__);
++
++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL)
++ {
++ return;
++ }
++
++ //update attribute
++ pattrib = &pmgntframe->attrib;
++
++ pmgntframe->frame_tag = DATA_FRAMETAG;
++ pattrib->ether_type = 0x890d;
++ pattrib->pctrl =0;
++
++ _rtw_memcpy(pattrib->dst, baddr, ETH_ALEN);
++
++ _rtw_memcpy(pattrib->src, myid(&(padapter->eeprompriv)), ETH_ALEN);
++
++ _rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN);
++ _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
++
++ update_tdls_attrib(padapter, pattrib);
++ pattrib->qsel=pattrib->priority;
++ if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, TUNNELED_PROBE_REQ) != _SUCCESS) {
++ rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf);
++ rtw_free_xmitframe(pxmitpriv, pmgntframe);
++ goto exit;
++ }
++ rtw_dump_xframe(padapter, pmgntframe);
++
++exit:
++
++ return;
++}
++
++void issue_tunneled_probe_rsp(_adapter *padapter, union recv_frame *precv_frame)
++{
++ struct xmit_frame *pmgntframe;
++ struct pkt_attrib *pattrib;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
++ struct rx_pkt_attrib *rx_pkt_pattrib = &precv_frame->u.hdr.attrib;
++
++ DBG_871X("[%s]\n", __FUNCTION__);
++
++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL)
++ {
++ return;
++ }
++
++ //update attribute
++ pattrib = &pmgntframe->attrib;
++
++ pmgntframe->frame_tag = DATA_FRAMETAG;
++ pattrib->ether_type = 0x890d;
++ pattrib->pctrl =0;
++
++ _rtw_memcpy(pattrib->dst, rx_pkt_pattrib->src, ETH_ALEN);
++
++ _rtw_memcpy(pattrib->src, myid(&(padapter->eeprompriv)), ETH_ALEN);
++
++ _rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN);
++ _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
++
++ update_tdls_attrib(padapter, pattrib);
++ pattrib->qsel=pattrib->priority;
++ if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, TUNNELED_PROBE_RSP) != _SUCCESS) {
++ rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf);
++ rtw_free_xmitframe(pxmitpriv, pmgntframe);
++ goto exit;
++ }
++ rtw_dump_xframe(padapter, pmgntframe);
++
++exit:
++
++ return;
++}
++#endif //CONFIG_WFD
++
++void issue_tdls_setup_req(_adapter *padapter, u8 *mac_addr)
++{
++ struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
++ struct xmit_frame *pmgntframe;
++ struct pkt_attrib *pattrib;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
++ struct sta_priv *pstapriv = &padapter->stapriv;
++ struct sta_info *ptdls_sta= NULL;
++ _irqL irqL;
++ static u8 dialogtoken = 0;
++ u32 timeout_interval= TPK_RESEND_COUNT * 1000; //retry timer should set at least 301 sec, using TPK_count counting 301 times.
++
++ if(ptdlsinfo->ap_prohibited == _TRUE)
++ goto exit;
++
++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL)
++ {
++ return;
++ }
++
++ //update attribute
++ pattrib = &pmgntframe->attrib;
++
++ pmgntframe->frame_tag = DATA_FRAMETAG;
++ pattrib->ether_type = 0x890d;
++ pattrib->pctrl =0;
++
++ _rtw_memcpy(pattrib->dst, mac_addr, ETH_ALEN);
++ _rtw_memcpy(pattrib->src, myid(&(padapter->eeprompriv)), ETH_ALEN);
++
++ _rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN);
++ _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
++
++ update_tdls_attrib(padapter, pattrib);
++
++ //init peer sta_info
++ ptdls_sta = rtw_get_stainfo(pstapriv, mac_addr);
++ if(ptdls_sta==NULL)
++ {
++ ptdls_sta = rtw_alloc_stainfo(pstapriv, mac_addr);
++ if(ptdls_sta)
++ {
++ _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL);
++ if(!(ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE))
++ ptdlsinfo->sta_cnt++;
++ _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);
++ if( ptdlsinfo->sta_cnt == (NUM_STA - 2) ) // -2: AP + BC/MC sta
++ {
++ ptdlsinfo->sta_maximum = _TRUE;
++ }
++ }
++ else
++ {
++ rtw_free_xmitbuf(pxmitpriv,pmgntframe->pxmitbuf);
++ rtw_free_xmitframe(pxmitpriv, pmgntframe);
++ goto exit;
++ }
++ }
++
++ if(ptdls_sta){
++ ptdls_sta->tdls_sta_state |= TDLS_RESPONDER_STATE;
++ //for tdls; ptdls_sta->aid is used to fill dialogtoken
++ ptdls_sta->dialog = dialogtoken;
++ dialogtoken = (dialogtoken+1)%256;
++ ptdls_sta->TDLS_PeerKey_Lifetime = timeout_interval;
++ _set_timer( &ptdls_sta->handshake_timer, TDLS_HANDSHAKE_TIME );
++ }
++
++ pattrib->qsel=pattrib->priority;
++ if(rtw_xmit_tdls_coalesce(padapter, pmgntframe, TDLS_SETUP_REQUEST) !=_SUCCESS ){
++ rtw_free_xmitbuf(pxmitpriv,pmgntframe->pxmitbuf);
++ rtw_free_xmitframe(pxmitpriv, pmgntframe);
++ goto exit;
++ }
++ rtw_dump_xframe(padapter, pmgntframe);
++
++exit:
++
++ return;
++}
++
++void issue_tdls_teardown(_adapter *padapter, u8 *mac_addr)
++{
++ struct xmit_frame *pmgntframe;
++ struct pkt_attrib *pattrib;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
++ struct sta_priv *pstapriv = &padapter->stapriv;
++ struct sta_info *ptdls_sta=NULL;
++ _irqL irqL;
++
++ ptdls_sta = rtw_get_stainfo(pstapriv, mac_addr);
++ if(ptdls_sta==NULL){
++ DBG_871X("issue tdls teardown unsuccessful\n");
++ return;
++ }else{
++ ptdls_sta->tdls_sta_state=TDLS_STATE_NONE;
++ }
++
++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL)
++ {
++ return;
++ }
++
++ //update attribute
++ pattrib = &pmgntframe->attrib;
++
++ pmgntframe->frame_tag = DATA_FRAMETAG;
++ pattrib->ether_type = 0x890d;
++ pattrib->pctrl =0;
++
++ _rtw_memcpy(pattrib->dst, mac_addr, ETH_ALEN);
++ _rtw_memcpy(pattrib->src, myid(&(padapter->eeprompriv)), ETH_ALEN);
++
++ _rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN);
++ _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
++
++ update_tdls_attrib(padapter, pattrib);
++ pattrib->qsel=pattrib->priority;
++ if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, TDLS_TEARDOWN) != _SUCCESS) {
++ rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf);
++ rtw_free_xmitframe(pxmitpriv, pmgntframe);
++ goto exit;
++ }
++ rtw_dump_xframe(padapter, pmgntframe);
++
++ if(ptdls_sta->tdls_sta_state & TDLS_CH_SWITCH_ON_STATE){
++ rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CS_OFF);
++ }
++
++ if( ptdls_sta->timer_flag == 1 )
++ {
++ _enter_critical_bh(&(padapter->tdlsinfo.hdl_lock), &irqL);
++ ptdls_sta->timer_flag = 2;
++ _exit_critical_bh(&(padapter->tdlsinfo.hdl_lock), &irqL);
++ }
++ else
++ rtw_tdls_cmd(padapter, mac_addr, TDLS_FREE_STA );
++
++
++exit:
++
++ return;
++}
++
++void issue_tdls_dis_req(_adapter *padapter, u8 *mac_addr)
++{
++ struct xmit_frame *pmgntframe;
++ struct pkt_attrib *pattrib;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
++ u8 baddr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
++
++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL)
++ {
++ return;
++ }
++
++ //update attribute
++ pattrib = &pmgntframe->attrib;
++
++ pmgntframe->frame_tag = DATA_FRAMETAG;
++ pattrib->ether_type = 0x890d;
++ pattrib->pctrl =0;
++
++ if(mac_addr == NULL)
++ _rtw_memcpy(pattrib->dst, baddr, ETH_ALEN);
++ else
++ _rtw_memcpy(pattrib->dst, mac_addr, ETH_ALEN);
++
++ _rtw_memcpy(pattrib->src, myid(&(padapter->eeprompriv)), ETH_ALEN);
++
++ _rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN);
++ _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
++
++ update_tdls_attrib(padapter, pattrib);
++ pattrib->qsel=pattrib->priority;
++ if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, TDLS_DISCOVERY_REQUEST) != _SUCCESS) {
++ rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf);
++ rtw_free_xmitframe(pxmitpriv, pmgntframe);
++ goto exit;
++ }
++ rtw_dump_xframe(padapter, pmgntframe);
++ DBG_871X("issue tdls dis req\n");
++
++exit:
++
++ return;
++}
++
++void issue_tdls_setup_rsp(_adapter *padapter, union recv_frame *precv_frame)
++{
++ struct xmit_frame *pmgntframe;
++ struct pkt_attrib *pattrib;
++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ struct rx_pkt_attrib *rx_pkt_pattrib = &precv_frame->u.hdr.attrib;
++ _irqL irqL;
++
++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL)
++ {
++ return;
++ }
++
++ //update attribute
++ pattrib = &pmgntframe->attrib;
++
++ pmgntframe->frame_tag = DATA_FRAMETAG;
++ pattrib->ether_type = 0x890d;
++ pattrib->pctrl =0;
++
++ _rtw_memcpy(pattrib->dst, rx_pkt_pattrib->src, ETH_ALEN);
++ _rtw_memcpy(pattrib->src, myid(&(padapter->eeprompriv)), ETH_ALEN);
++
++ _rtw_memcpy(pattrib->ra, rx_pkt_pattrib->bssid, ETH_ALEN);
++ _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
++
++ update_tdls_attrib(padapter, pattrib);
++ pattrib->qsel=pattrib->priority;
++ if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, TDLS_SETUP_RESPONSE) != _SUCCESS) {
++ rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf);
++ rtw_free_xmitframe(pxmitpriv, pmgntframe);
++ goto exit;
++ }
++ rtw_dump_xframe(padapter, pmgntframe);
++
++exit:
++
++ return;
++
++}
++
++void issue_tdls_setup_cfm(_adapter *padapter, union recv_frame *precv_frame)
++{
++ struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
++ struct xmit_frame *pmgntframe;
++ struct pkt_attrib *pattrib;
++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
++ struct sta_info *ptdls_sta=NULL;
++ _irqL irqL;
++
++ struct rx_pkt_attrib *rx_pkt_pattrib = & precv_frame->u.hdr.attrib;
++
++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL)
++ {
++ return;
++ }
++
++ //update attribute
++ pattrib = &pmgntframe->attrib;
++
++ pmgntframe->frame_tag = DATA_FRAMETAG;
++ pattrib->ether_type = 0x890d;
++ pattrib->pctrl =0;
++
++ _rtw_memcpy(pattrib->dst, rx_pkt_pattrib->src, ETH_ALEN);
++ _rtw_memcpy(pattrib->src, myid(&(padapter->eeprompriv)), ETH_ALEN);
++
++ _rtw_memcpy(pattrib->ra, rx_pkt_pattrib->bssid, ETH_ALEN);
++ _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
++
++ update_tdls_attrib(padapter, pattrib);
++ pattrib->qsel=pattrib->priority;
++ if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, TDLS_SETUP_CONFIRM) != _SUCCESS) {
++ rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf);
++ rtw_free_xmitframe(pxmitpriv, pmgntframe);
++ goto exit;
++ }
++
++ rtw_dump_xframe(padapter, pmgntframe);
++
++exit:
++
++ return;
++
++}
++
++//TDLS Discovery Response frame is a management action frame
++void issue_tdls_dis_rsp(_adapter *padapter, union recv_frame *precv_frame, u8 dialog)
++{
++ struct xmit_frame *pmgntframe;
++ struct pkt_attrib *pattrib;
++ unsigned char *pframe;
++ struct rtw_ieee80211_hdr *pwlanhdr;
++ unsigned short *fctrl;
++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++
++ struct rx_pkt_attrib *rx_pkt_pattrib = &precv_frame->u.hdr.attrib;
++
++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL)
++ {
++ return;
++ }
++
++ //update attribute
++ pattrib = &pmgntframe->attrib;
++ update_mgntframe_attrib(padapter, pattrib);
++
++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++ fctrl = &(pwlanhdr->frame_ctl);
++ *(fctrl) = 0;
++
++ // unicast probe request frame
++ _rtw_memcpy(pwlanhdr->addr1, rx_pkt_pattrib->src, ETH_ALEN);
++ _rtw_memcpy(pattrib->dst, pwlanhdr->addr1, ETH_ALEN);
++
++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN);
++ _rtw_memcpy(pattrib->src, pwlanhdr->addr2, ETH_ALEN);
++
++ _rtw_memcpy(pwlanhdr->addr3, rx_pkt_pattrib->bssid, ETH_ALEN);
++ _rtw_memcpy(pattrib->ra, pwlanhdr->addr3, ETH_ALEN);
++
++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
++ pmlmeext->mgnt_seq++;
++ SetFrameSubType(pframe, WIFI_ACTION);
++
++ pframe += sizeof (struct rtw_ieee80211_hdr_3addr);
++ pattrib->pktlen = sizeof (struct rtw_ieee80211_hdr_3addr);
++
++ rtw_build_tdls_dis_rsp_ies(padapter, pmgntframe, pframe, dialog);
++
++ pattrib->nr_frags = 1;
++ pattrib->last_txcmdsz = pattrib->pktlen;
++
++ dump_mgntframe(padapter, pmgntframe);
++
++ return;
++}
++
++void issue_tdls_peer_traffic_indication(_adapter *padapter, struct sta_info *ptdls_sta)
++{
++ struct xmit_frame *pmgntframe;
++ struct pkt_attrib *pattrib;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
++
++ static u8 dialogtoken=0;
++
++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL)
++ {
++ return;
++ }
++
++ //update attribute
++ pattrib = &pmgntframe->attrib;
++
++ pmgntframe->frame_tag = DATA_FRAMETAG;
++ pattrib->ether_type = 0x890d;
++ pattrib->pctrl =0;
++
++ _rtw_memcpy(pattrib->dst, ptdls_sta->hwaddr, ETH_ALEN);
++ _rtw_memcpy(pattrib->src, myid(&(padapter->eeprompriv)), ETH_ALEN);
++
++ _rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN);
++ _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
++
++ //for tdls; pattrib->nr_frags is used to fill dialogtoken
++ ptdls_sta->dialog = dialogtoken;
++ dialogtoken = (dialogtoken+1)%256;
++ //PTI frame's priority should be AC_VO
++ pattrib->priority = 7;
++
++ update_tdls_attrib(padapter, pattrib);
++ pattrib->qsel=pattrib->priority;
++ if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, TDLS_PEER_TRAFFIC_INDICATION) != _SUCCESS) {
++ rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf);
++ rtw_free_xmitframe(pxmitpriv, pmgntframe);
++ goto exit;
++ }
++ rtw_dump_xframe(padapter, pmgntframe);
++
++exit:
++
++ return;
++}
++
++void issue_tdls_ch_switch_req(_adapter *padapter, u8 *mac_addr)
++{
++ struct xmit_frame *pmgntframe;
++ struct pkt_attrib *pattrib;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
++
++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL)
++ {
++ return;
++ }
++
++ //update attribute
++ pattrib = &pmgntframe->attrib;
++
++ pmgntframe->frame_tag = DATA_FRAMETAG;
++ pattrib->ether_type = 0x890d;
++ pattrib->pctrl =0;
++
++ _rtw_memcpy(pattrib->dst, mac_addr, ETH_ALEN);
++ _rtw_memcpy(pattrib->src, myid(&(padapter->eeprompriv)), ETH_ALEN);
++
++ _rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN);
++ _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
++
++ update_tdls_attrib(padapter, pattrib);
++
++ pattrib->qsel=pattrib->priority;
++ if(rtw_xmit_tdls_coalesce(padapter, pmgntframe, TDLS_CHANNEL_SWITCH_REQUEST) !=_SUCCESS ){
++ rtw_free_xmitbuf(pxmitpriv,pmgntframe->pxmitbuf);
++ rtw_free_xmitframe(pxmitpriv, pmgntframe);
++ goto exit;
++ }
++ rtw_dump_xframe(padapter, pmgntframe);
++
++exit:
++
++ return;
++}
++
++void issue_tdls_ch_switch_rsp(_adapter *padapter, u8 *mac_addr)
++{
++ struct xmit_frame *pmgntframe;
++ struct pkt_attrib *pattrib;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
++
++ _irqL irqL;
++
++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL)
++ {
++ return;
++ }
++
++ //update attribute
++ pattrib = &pmgntframe->attrib;
++
++ pmgntframe->frame_tag = DATA_FRAMETAG;
++ pattrib->ether_type = 0x890d;
++ pattrib->pctrl =0;
++
++ _rtw_memcpy(pattrib->dst, mac_addr, ETH_ALEN);
++ _rtw_memcpy(pattrib->src, myid(&(padapter->eeprompriv)), ETH_ALEN);
++
++ _rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN);
++ _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
++
++ update_tdls_attrib(padapter, pattrib);
++
++ pattrib->qsel=pattrib->priority;
++/*
++ _enter_critical_bh(&pxmitpriv->lock, &irqL);
++ if(xmitframe_enqueue_for_tdls_sleeping_sta(padapter, pmgntframe)==_TRUE){
++ _exit_critical_bh(&pxmitpriv->lock, &irqL);
++ return _FALSE;
++ }
++*/
++ if(rtw_xmit_tdls_coalesce(padapter, pmgntframe, TDLS_CHANNEL_SWITCH_RESPONSE) !=_SUCCESS ){
++ rtw_free_xmitbuf(pxmitpriv,pmgntframe->pxmitbuf);
++ rtw_free_xmitframe(pxmitpriv, pmgntframe);
++ goto exit;
++ }
++ rtw_dump_xframe(padapter, pmgntframe);
++
++exit:
++
++ return;
++}
++
++sint On_TDLS_Dis_Rsp(_adapter *adapter, union recv_frame *precv_frame)
++{
++ struct sta_info *ptdls_sta = NULL, *psta = rtw_get_stainfo(&(adapter->stapriv), get_bssid(&(adapter->mlmepriv)));
++ struct recv_priv *precvpriv = &(adapter->recvpriv);
++ u8 *ptr = precv_frame->u.hdr.rx_data, *psa;
++ struct rx_pkt_attrib *pattrib = &(precv_frame->u.hdr.attrib);
++ struct tdls_info *ptdlsinfo = &(adapter->tdlsinfo);
++ u8 empty_addr[ETH_ALEN] = { 0x00 };
++ int UndecoratedSmoothedPWDB;
++
++
++ //WFDTDLS: for sigma test, not to setup direct link automatically
++ ptdlsinfo->dev_discovered = 1;
++
++#ifdef CONFIG_TDLS_AUTOSETUP
++ psa = get_sa(ptr);
++ ptdls_sta = rtw_get_stainfo(&(adapter->stapriv), psa);
++
++ if(ptdls_sta != NULL)
++ {
++ ptdls_sta->tdls_sta_state |= TDLS_ALIVE_STATE;
++
++ //Record the tdls sta with lowest signal strength
++ if( (ptdlsinfo->sta_maximum == _TRUE) && (ptdls_sta->alive_count >= 1) )
++ {
++ if( _rtw_memcmp(ptdlsinfo->ss_record.macaddr, empty_addr, ETH_ALEN) )
++ {
++ _rtw_memcpy(ptdlsinfo->ss_record.macaddr, psa, ETH_ALEN);
++ ptdlsinfo->ss_record.RxPWDBAll = pattrib->RxPWDBAll;
++ }
++ else
++ {
++ if( ptdlsinfo->ss_record.RxPWDBAll < pattrib->RxPWDBAll )
++ {
++ _rtw_memcpy(ptdlsinfo->ss_record.macaddr, psa, ETH_ALEN);
++ ptdlsinfo->ss_record.RxPWDBAll = pattrib->RxPWDBAll;
++ }
++ }
++ }
++
++ }
++ else
++ {
++ if( ptdlsinfo->sta_maximum == _TRUE)
++ {
++ if( _rtw_memcmp( ptdlsinfo->ss_record.macaddr, empty_addr, ETH_ALEN ) )
++ {
++ //All traffics are busy, do not set up another direct link.
++ return _FAIL;
++ }
++ else
++ {
++ if( pattrib->RxPWDBAll > ptdlsinfo->ss_record.RxPWDBAll )
++ {
++ issue_tdls_teardown(adapter, ptdlsinfo->ss_record.macaddr);
++ }
++ else
++ {
++ return _FAIL;
++ }
++ }
++ }
++
++ rtw_hal_get_def_var(adapter, HAL_DEF_UNDERCORATEDSMOOTHEDPWDB, &UndecoratedSmoothedPWDB);
++
++ if( pattrib->RxPWDBAll + TDLS_SIGNAL_THRESH >= UndecoratedSmoothedPWDB);
++ {
++ DBG_871X("pattrib->RxPWDBAll=%d, pdmpriv->UndecoratedSmoothedPWDB=%d\n", pattrib->RxPWDBAll, UndecoratedSmoothedPWDB);
++ issue_tdls_setup_req(adapter, psa);
++ }
++ }
++#endif //CONFIG_TDLS_AUTOSETUP
++
++ return _SUCCESS;
++}
++
++sint On_TDLS_Setup_Req(_adapter *adapter, union recv_frame *precv_frame)
++{
++ struct tdls_info *ptdlsinfo = &adapter->tdlsinfo;
++ u8 *psa, *pmyid;
++ struct sta_info *ptdls_sta= NULL;
++ struct sta_priv *pstapriv = &adapter->stapriv;
++ u8 *ptr = precv_frame->u.hdr.rx_data;
++ struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
++ struct security_priv *psecuritypriv = &adapter->securitypriv;
++ _irqL irqL;
++ struct rx_pkt_attrib *prx_pkt_attrib = &precv_frame->u.hdr.attrib;
++ u8 *prsnie, *ppairwise_cipher;
++ u8 i, k, pairwise_count;
++ u8 ccmp_have=0, rsnie_have=0;
++ u16 j;
++ u8 SNonce[32];
++ u32 *timeout_interval;
++ sint parsing_length; //frame body length, without icv_len
++ PNDIS_802_11_VARIABLE_IEs pIE;
++ u8 FIXED_IE = 5;
++ unsigned char supportRate[16];
++ int supportRateNum = 0;
++
++ psa = get_sa(ptr);
++ ptdls_sta = rtw_get_stainfo(pstapriv, psa);
++
++ pmyid=myid(&(adapter->eeprompriv));
++ ptr +=prx_pkt_attrib->hdrlen + prx_pkt_attrib->iv_len+LLC_HEADER_SIZE+TYPE_LENGTH_FIELD_SIZE+1;
++ parsing_length= ((union recv_frame *)precv_frame)->u.hdr.len
++ -prx_pkt_attrib->hdrlen
++ -prx_pkt_attrib->iv_len
++ -prx_pkt_attrib->icv_len
++ -LLC_HEADER_SIZE
++ -ETH_TYPE_LEN
++ -PAYLOAD_TYPE_LEN
++ -FIXED_IE;
++
++ if(ptdlsinfo->ap_prohibited == _TRUE)
++ {
++ goto exit;
++ }
++
++ if(ptdls_sta==NULL){
++ ptdls_sta = rtw_alloc_stainfo(pstapriv, psa);
++ }else{
++ if(ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE){
++ //If the direct link is already set up
++ //Process as re-setup after tear down
++ DBG_871X("re-setup a direct link\n");
++ }
++ //already receiving TDLS setup request
++ else if(ptdls_sta->tdls_sta_state & TDLS_INITIATOR_STATE){
++ DBG_871X("receive duplicated TDLS setup request frame in handshaking\n");
++ goto exit;
++ }
++ //When receiving and sending setup_req to the same link at the same time, STA with higher MAC_addr would be initiator
++ //following is to check out MAC_addr
++ else if(ptdls_sta->tdls_sta_state & TDLS_RESPONDER_STATE){
++ DBG_871X("receive setup_req after sending setup_req\n");
++ for (i=0;i<6;i++){
++ if(*(pmyid+i)==*(psa+i)){
++ }
++ else if(*(pmyid+i)>*(psa+i)){
++ goto exit;
++ }else if(*(pmyid+i)<*(psa+i)){
++ ptdls_sta->tdls_sta_state=TDLS_INITIATOR_STATE;
++ break;
++ }
++ }
++ }
++ }
++
++ if(ptdls_sta)
++ {
++ ptdls_sta->dialog = *(ptr+2); //copy dialog token
++ ptdls_sta->stat_code = 0;
++
++ //parsing information element
++ for(j=FIXED_IE; j<parsing_length;){
++
++ pIE = (PNDIS_802_11_VARIABLE_IEs)(ptr+ j);
++
++ switch (pIE->ElementID)
++ {
++ case _SUPPORTEDRATES_IE_:
++ _rtw_memcpy(supportRate, pIE->data, pIE->Length);
++ supportRateNum = pIE->Length;
++ break;
++ case _COUNTRY_IE_:
++ break;
++ case _EXT_SUPPORTEDRATES_IE_:
++ if(supportRateNum<=sizeof(supportRate))
++ {
++ _rtw_memcpy(supportRate+supportRateNum, pIE->data, pIE->Length);
++ supportRateNum += pIE->Length;
++ }
++ break;
++ case _SUPPORTED_CH_IE_:
++ break;
++ case _RSN_IE_2_:
++ rsnie_have=1;
++ if(prx_pkt_attrib->encrypt){
++ prsnie=(u8*)pIE;
++ //check whether initiator STA has CCMP pairwise_cipher.
++ ppairwise_cipher=prsnie+10;
++ _rtw_memcpy(&pairwise_count, (u16*)(ppairwise_cipher-2), 1);
++ for(k=0;k<pairwise_count;k++){
++ if(_rtw_memcmp( ppairwise_cipher+4*k, RSN_CIPHER_SUITE_CCMP, 4)==_TRUE)
++ ccmp_have=1;
++ }
++ if(ccmp_have==0){
++ //invalid contents of RSNIE
++ ptdls_sta->stat_code=72;
++ }
++ }
++ break;
++ case _EXT_CAP_IE_:
++ break;
++ case _VENDOR_SPECIFIC_IE_:
++ break;
++ case _FTIE_:
++ if(prx_pkt_attrib->encrypt)
++ _rtw_memcpy(SNonce, (ptr+j+52), 32);
++ break;
++ case _TIMEOUT_ITVL_IE_:
++ if(prx_pkt_attrib->encrypt)
++ timeout_interval = (u32 *)(ptr+j+3);
++ break;
++ case _RIC_Descriptor_IE_:
++ break;
++ case _HT_CAPABILITY_IE_:
++ rtw_tdls_process_ht_cap(adapter, ptdls_sta, pIE->data, pIE->Length);
++ break;
++ case EID_BSSCoexistence:
++ break;
++ case _LINK_ID_IE_:
++ if(_rtw_memcmp(get_bssid(pmlmepriv), pIE->data, 6) == _FALSE)
++ {
++ //not in the same BSS
++ ptdls_sta->stat_code=7;
++ }
++ break;
++ default:
++ break;
++ }
++
++ j += (pIE->Length + 2);
++
++ }
++
++ //update station supportRate
++ ptdls_sta->bssratelen = supportRateNum;
++ _rtw_memcpy(ptdls_sta->bssrateset, supportRate, supportRateNum);
++
++ //check status code
++ //if responder STA has/hasn't security on AP, but request hasn't/has RSNIE, it should reject
++ if(ptdls_sta->stat_code == 0 )
++ {
++ if(rsnie_have && (prx_pkt_attrib->encrypt==0)){
++ //security disabled
++ ptdls_sta->stat_code = 5;
++ }else if(rsnie_have==0 && (prx_pkt_attrib->encrypt)){
++ //request haven't RSNIE
++ ptdls_sta->stat_code = 38;
++ }
++
++#ifdef CONFIG_WFD
++ //WFD test plan version 0.18.2 test item 5.1.5
++ //SoUT does not use TDLS if AP uses weak security
++ if ( adapter->wdinfo.wfd_tdls_enable )
++ {
++ if(rsnie_have && (prx_pkt_attrib->encrypt != _AES_))
++ {
++ ptdls_sta->stat_code = 5;
++ }
++ }
++#endif //CONFIG_WFD
++ }
++
++ ptdls_sta->tdls_sta_state|= TDLS_INITIATOR_STATE;
++ if(prx_pkt_attrib->encrypt){
++ _rtw_memcpy(ptdls_sta->SNonce, SNonce, 32);
++ _rtw_memcpy(&(ptdls_sta->TDLS_PeerKey_Lifetime), timeout_interval, 4);
++ }
++ _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL);
++ if(!(ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE))
++ ptdlsinfo->sta_cnt++;
++ _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);
++ if( ptdlsinfo->sta_cnt == (NUM_STA - 2) ) // -2: AP + BC/MC sta
++ {
++ ptdlsinfo->sta_maximum = _TRUE;
++ }
++
++#ifdef CONFIG_WFD
++ rtw_tdls_process_wfd_ie(ptdlsinfo, ptr + FIXED_IE, parsing_length - FIXED_IE);
++#endif // CONFIG_WFD
++
++ }
++ else
++ {
++ goto exit;
++ }
++
++ issue_tdls_setup_rsp(adapter, precv_frame);
++
++ if(ptdls_sta->stat_code==0)
++ {
++ _set_timer( &ptdls_sta->handshake_timer, TDLS_HANDSHAKE_TIME);
++ }
++ else //status code!=0 ; setup unsuccess
++ {
++ free_tdls_sta(adapter, ptdls_sta);
++ }
++
++exit:
++
++ return _FAIL;
++}
++
++sint On_TDLS_Setup_Rsp(_adapter *adapter, union recv_frame *precv_frame)
++{
++ struct tdls_info *ptdlsinfo = &adapter->tdlsinfo;
++ struct sta_info *ptdls_sta= NULL;
++ struct sta_priv *pstapriv = &adapter->stapriv;
++ u8 *ptr = precv_frame->u.hdr.rx_data;
++ _irqL irqL;
++ struct rx_pkt_attrib *prx_pkt_attrib = &precv_frame->u.hdr.attrib;
++ u8 *psa;
++ u16 stat_code;
++ sint parsing_length; //frame body length, without icv_len
++ PNDIS_802_11_VARIABLE_IEs pIE;
++ u8 FIXED_IE =7;
++ u8 *pftie, *ptimeout_ie, *plinkid_ie, *prsnie, *pftie_mic, *ppairwise_cipher;
++ u16 pairwise_count, j, k;
++ u8 verify_ccmp=0;
++ unsigned char supportRate[16];
++ int supportRateNum = 0;
++
++ psa = get_sa(ptr);
++ ptdls_sta = rtw_get_stainfo(pstapriv, psa);
++
++ if ( NULL == ptdls_sta )
++ {
++ return _FAIL;
++ }
++
++ ptr +=prx_pkt_attrib->hdrlen + prx_pkt_attrib->iv_len+LLC_HEADER_SIZE+TYPE_LENGTH_FIELD_SIZE+1;
++ parsing_length= ((union recv_frame *)precv_frame)->u.hdr.len
++ -prx_pkt_attrib->hdrlen
++ -prx_pkt_attrib->iv_len
++ -prx_pkt_attrib->icv_len
++ -LLC_HEADER_SIZE
++ -TYPE_LENGTH_FIELD_SIZE
++ -1
++ -FIXED_IE;
++
++ _rtw_memcpy(&stat_code, ptr+2, 2);
++
++ if(stat_code!=0)
++ {
++ DBG_871X( "[%s] status_code = %d, free_tdls_sta\n", __FUNCTION__, stat_code );
++ free_tdls_sta(adapter, ptdls_sta);
++ return _FAIL;
++ }
++
++ stat_code = 0;
++
++ //parsing information element
++ for(j=FIXED_IE; j<parsing_length;)
++ {
++ pIE = (PNDIS_802_11_VARIABLE_IEs)(ptr+ j);
++
++ switch (pIE->ElementID)
++ {
++ case _SUPPORTEDRATES_IE_:
++ _rtw_memcpy(supportRate, pIE->data, pIE->Length);
++ supportRateNum = pIE->Length;
++ break;
++ case _COUNTRY_IE_:
++ break;
++ case _EXT_SUPPORTEDRATES_IE_:
++ if(supportRateNum<=sizeof(supportRate))
++ {
++ _rtw_memcpy(supportRate+supportRateNum, pIE->data, pIE->Length);
++ supportRateNum += pIE->Length;
++ }
++ break;
++ case _SUPPORTED_CH_IE_:
++ break;
++ case _RSN_IE_2_:
++ prsnie=(u8*)pIE;
++ //check whether responder STA has CCMP pairwise_cipher.
++ ppairwise_cipher=prsnie+10;
++ _rtw_memcpy(&pairwise_count, (u16*)(ppairwise_cipher-2), 2);
++ for(k=0;k<pairwise_count;k++){
++ if(_rtw_memcmp( ppairwise_cipher+4*k, RSN_CIPHER_SUITE_CCMP, 4)==_TRUE)
++ verify_ccmp=1;
++ }
++ case _EXT_CAP_IE_:
++ break;
++ case _VENDOR_SPECIFIC_IE_:
++ break;
++ case _FTIE_:
++ pftie=(u8*)pIE;
++ _rtw_memcpy(ptdls_sta->ANonce, (ptr+j+20), 32);
++ break;
++ case _TIMEOUT_ITVL_IE_:
++ ptimeout_ie=(u8*)pIE;
++ break;
++ case _RIC_Descriptor_IE_:
++ break;
++ case _HT_CAPABILITY_IE_:
++ rtw_tdls_process_ht_cap(adapter, ptdls_sta, pIE->data, pIE->Length);
++ break;
++ case EID_BSSCoexistence:
++ break;
++ case _LINK_ID_IE_:
++ plinkid_ie=(u8*)pIE;
++ break;
++ default:
++ break;
++ }
++
++ j += (pIE->Length + 2);
++
++ }
++
++ //update station supportRate
++ ptdls_sta->bssratelen = supportRateNum;
++ _rtw_memcpy(ptdls_sta->bssrateset, supportRate, supportRateNum);
++
++#ifdef CONFIG_WFD
++ rtw_tdls_process_wfd_ie(ptdlsinfo, ptr + FIXED_IE, parsing_length - FIXED_IE);
++#endif // CONFIG_WFD
++
++ if(stat_code != 0)
++ {
++ ptdls_sta->stat_code = stat_code;
++ }
++ else
++ {
++ if(prx_pkt_attrib->encrypt)
++ {
++ if(verify_ccmp==1)
++ {
++ wpa_tdls_generate_tpk(adapter, ptdls_sta);
++ ptdls_sta->stat_code=0;
++ if(tdls_verify_mic(ptdls_sta->tpk.kck, 2, plinkid_ie, prsnie, ptimeout_ie, pftie)==0) //0: Invalid, 1: valid
++ {
++ free_tdls_sta(adapter, ptdls_sta);
++ return _FAIL;
++ }
++ }
++ else
++ {
++ ptdls_sta->stat_code=72; //invalide contents of RSNIE
++ }
++
++ }else{
++ ptdls_sta->stat_code=0;
++ }
++ }
++
++ DBG_871X("issue_tdls_setup_cfm\n");
++ issue_tdls_setup_cfm(adapter, precv_frame);
++
++ if(ptdls_sta->stat_code==0)
++ {
++ ptdlsinfo->setup_state = TDLS_LINKED_STATE;
++
++ if( ptdls_sta->tdls_sta_state & TDLS_RESPONDER_STATE )
++ {
++ ptdls_sta->tdls_sta_state |= TDLS_LINKED_STATE;
++ _cancel_timer_ex( &ptdls_sta->handshake_timer);
++#ifdef CONFIG_TDLS_AUTOCHECKALIVE
++ _set_timer( &ptdls_sta->alive_timer1, TDLS_ALIVE_TIMER_PH1);
++#endif //CONFIG_TDLS_AUTOSETUP
++ }
++
++ rtw_tdls_set_mac_id(ptdlsinfo, ptdls_sta);
++ rtw_tdls_set_key(adapter, prx_pkt_attrib, ptdls_sta);
++
++ rtw_tdls_cmd(adapter, ptdls_sta->hwaddr, TDLS_WRCR);
++
++ }
++ else //status code!=0 ; setup unsuccessful
++ {
++ free_tdls_sta(adapter, ptdls_sta);
++ }
++
++ return _FAIL;
++
++}
++
++sint On_TDLS_Setup_Cfm(_adapter *adapter, union recv_frame *precv_frame)
++{
++ struct tdls_info *ptdlsinfo = &adapter->tdlsinfo;
++ struct sta_info *ptdls_sta= NULL;
++ struct sta_priv *pstapriv = &adapter->stapriv;
++ u8 *ptr = precv_frame->u.hdr.rx_data;
++ _irqL irqL;
++ struct rx_pkt_attrib *prx_pkt_attrib = &precv_frame->u.hdr.attrib;
++ u8 *psa;
++ u16 stat_code;
++ sint parsing_length;
++ PNDIS_802_11_VARIABLE_IEs pIE;
++ u8 FIXED_IE =5;
++ u8 *pftie, *ptimeout_ie, *plinkid_ie, *prsnie, *pftie_mic, *ppairwise_cipher;
++ u16 j, pairwise_count;
++
++ psa = get_sa(ptr);
++ ptdls_sta = rtw_get_stainfo(pstapriv, psa);
++
++ ptr +=prx_pkt_attrib->hdrlen + prx_pkt_attrib->iv_len+LLC_HEADER_SIZE+TYPE_LENGTH_FIELD_SIZE+1;
++ parsing_length= ((union recv_frame *)precv_frame)->u.hdr.len
++ -prx_pkt_attrib->hdrlen
++ -prx_pkt_attrib->iv_len
++ -prx_pkt_attrib->icv_len
++ -LLC_HEADER_SIZE
++ -ETH_TYPE_LEN
++ -PAYLOAD_TYPE_LEN
++ -FIXED_IE;
++ _rtw_memcpy(&stat_code, ptr+2, 2);
++
++ if(stat_code!=0){
++ DBG_871X( "[%s] stat_code = %d\n, free_tdls_sta", __FUNCTION__, stat_code );
++ free_tdls_sta(adapter, ptdls_sta);
++ return _FAIL;
++ }
++
++ if(prx_pkt_attrib->encrypt){
++ //parsing information element
++ for(j=FIXED_IE; j<parsing_length;){
++
++ pIE = (PNDIS_802_11_VARIABLE_IEs)(ptr+ j);
++
++ switch (pIE->ElementID)
++ {
++ case _RSN_IE_2_:
++ prsnie=(u8*)pIE;
++ break;
++ case _VENDOR_SPECIFIC_IE_:
++ break;
++ case _FTIE_:
++ pftie=(u8*)pIE;
++ break;
++ case _TIMEOUT_ITVL_IE_:
++ ptimeout_ie=(u8*)pIE;
++ break;
++ case _HT_EXTRA_INFO_IE_:
++ break;
++ case _LINK_ID_IE_:
++ plinkid_ie=(u8*)pIE;
++ break;
++ default:
++ break;
++ }
++
++ j += (pIE->Length + 2);
++
++ }
++
++ //verify mic in FTIE MIC field
++ if(tdls_verify_mic(ptdls_sta->tpk.kck, 3, plinkid_ie, prsnie, ptimeout_ie, pftie)==0){ //0: Invalid, 1: Valid
++ free_tdls_sta(adapter, ptdls_sta);
++ return _FAIL;
++ }
++
++ }
++
++ ptdlsinfo->setup_state = TDLS_LINKED_STATE;
++ if( ptdls_sta->tdls_sta_state & TDLS_INITIATOR_STATE )
++ {
++ ptdls_sta->tdls_sta_state|=TDLS_LINKED_STATE;
++ _cancel_timer_ex( &ptdls_sta->handshake_timer);
++#ifdef CONFIG_TDLS_AUTOCHECKALIVE
++ _set_timer( &ptdls_sta->alive_timer1, TDLS_ALIVE_TIMER_PH1);
++#endif //CONFIG_TDLS_AUTOCHECKALIVE
++ }
++
++ rtw_tdls_set_mac_id(ptdlsinfo, ptdls_sta);
++ rtw_tdls_set_key(adapter, prx_pkt_attrib, ptdls_sta);
++
++ rtw_tdls_cmd(adapter, ptdls_sta->hwaddr, TDLS_WRCR);
++
++ return _FAIL;
++
++}
++
++sint On_TDLS_Dis_Req(_adapter *adapter, union recv_frame *precv_frame)
++{
++ struct rx_pkt_attrib *prx_pkt_attrib = &precv_frame->u.hdr.attrib;
++ struct sta_priv *pstapriv = &adapter->stapriv;
++ struct sta_info *psta_ap;
++ u8 *ptr = precv_frame->u.hdr.rx_data;
++ sint parsing_length; //frame body length, without icv_len
++ PNDIS_802_11_VARIABLE_IEs pIE;
++ u8 FIXED_IE = 3, *dst, *pdialog = NULL;
++ u16 j;
++
++ ptr +=prx_pkt_attrib->hdrlen + prx_pkt_attrib->iv_len + LLC_HEADER_SIZE+TYPE_LENGTH_FIELD_SIZE + 1;
++ pdialog=ptr+2;
++
++ parsing_length= ((union recv_frame *)precv_frame)->u.hdr.len
++ -prx_pkt_attrib->hdrlen
++ -prx_pkt_attrib->iv_len
++ -prx_pkt_attrib->icv_len
++ -LLC_HEADER_SIZE
++ -TYPE_LENGTH_FIELD_SIZE
++ -1
++ -FIXED_IE;
++
++ //parsing information element
++ for(j=FIXED_IE; j<parsing_length;){
++
++ pIE = (PNDIS_802_11_VARIABLE_IEs)(ptr+ j);
++
++ switch (pIE->ElementID)
++ {
++ case _LINK_ID_IE_:
++ psta_ap = rtw_get_stainfo(pstapriv, pIE->data);
++ if(psta_ap == NULL)
++ {
++ goto exit;
++ }
++ dst = pIE->data + 12;
++ if( (MacAddr_isBcst(dst) == _FALSE) && (_rtw_memcmp(myid(&(adapter->eeprompriv)), dst, 6) == _FALSE) )
++ {
++ goto exit;
++ }
++ break;
++ default:
++ break;
++ }
++
++ j += (pIE->Length + 2);
++
++ }
++
++ //check frame contents
++
++ issue_tdls_dis_rsp(adapter, precv_frame, *(pdialog) );
++
++exit:
++
++ return _FAIL;
++
++}
++
++sint On_TDLS_Teardown(_adapter *adapter, union recv_frame *precv_frame)
++{
++ u8 *psa;
++ u8 *ptr = precv_frame->u.hdr.rx_data;
++ struct rx_pkt_attrib *prx_pkt_attrib = &precv_frame->u.hdr.attrib;
++ struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ struct sta_priv *pstapriv = &adapter->stapriv;
++ struct sta_info *ptdls_sta= NULL;
++ _irqL irqL;
++
++ psa = get_sa(ptr);
++
++ ptdls_sta = rtw_get_stainfo(pstapriv, psa);
++ if(ptdls_sta!=NULL){
++ if(ptdls_sta->tdls_sta_state & TDLS_CH_SWITCH_ON_STATE){
++ rtw_tdls_cmd(adapter, ptdls_sta->hwaddr, TDLS_CS_OFF);
++ }
++ free_tdls_sta(adapter, ptdls_sta);
++ }
++
++ return _FAIL;
++
++}
++
++u8 TDLS_check_ch_state(uint state){
++ if( (state & TDLS_CH_SWITCH_ON_STATE) &&
++ (state & TDLS_AT_OFF_CH_STATE) &&
++ (state & TDLS_PEER_AT_OFF_STATE) ){
++
++ if(state & TDLS_PEER_SLEEP_STATE)
++ return 2; //U-APSD + ch. switch
++ else
++ return 1; //ch. switch
++ }else
++ return 0;
++}
++
++//we process buffered data for 1. U-APSD, 2. ch. switch, 3. U-APSD + ch. switch here
++sint On_TDLS_Peer_Traffic_Rsp(_adapter *adapter, union recv_frame *precv_frame)
++{
++ struct tdls_info *ptdlsinfo = &adapter->tdlsinfo;
++ struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
++ struct rx_pkt_attrib *pattrib = & precv_frame->u.hdr.attrib;
++ struct sta_priv *pstapriv = &adapter->stapriv;
++ //get peer sta infomation
++ struct sta_info *ptdls_sta = rtw_get_stainfo(pstapriv, pattrib->src);
++ u8 wmmps_ac=0, state=TDLS_check_ch_state(ptdls_sta->tdls_sta_state);
++ int i;
++
++ ptdls_sta->sta_stats.rx_data_pkts++;
++
++ //receive peer traffic response frame, sleeping STA wakes up
++ //ptdls_sta->tdls_sta_state &= ~(TDLS_PEER_SLEEP_STATE);
++ process_wmmps_data( adapter, precv_frame);
++
++ // if noticed peer STA wakes up by receiving peer traffic response
++ // and we want to do channel swtiching, then we will transmit channel switch request first
++ if(ptdls_sta->tdls_sta_state & TDLS_APSD_CHSW_STATE){
++ issue_tdls_ch_switch_req(adapter, pattrib->src);
++ ptdls_sta->tdls_sta_state &= ~(TDLS_APSD_CHSW_STATE);
++ return _FAIL;
++ }
++
++ //check 4-AC queue bit
++ if(ptdls_sta->uapsd_vo || ptdls_sta->uapsd_vi || ptdls_sta->uapsd_be || ptdls_sta->uapsd_bk)
++ wmmps_ac=1;
++
++ //if it's a direct link and have buffered frame
++ if(ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE){
++ if(wmmps_ac && state)
++ {
++ _irqL irqL;
++ _list *xmitframe_plist, *xmitframe_phead;
++ struct xmit_frame *pxmitframe=NULL;
++
++ _enter_critical_bh(&ptdls_sta->sleep_q.lock, &irqL);
++
++ xmitframe_phead = get_list_head(&ptdls_sta->sleep_q);
++ xmitframe_plist = get_next(xmitframe_phead);
++
++ //transmit buffered frames
++ while ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE)
++ {
++ pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list);
++ xmitframe_plist = get_next(xmitframe_plist);
++ rtw_list_delete(&pxmitframe->list);
++
++ ptdls_sta->sleepq_len--;
++ if(ptdls_sta->sleepq_len>0){
++ pxmitframe->attrib.mdata = 1;
++ pxmitframe->attrib.eosp = 0;
++ }else{
++ pxmitframe->attrib.mdata = 0;
++ pxmitframe->attrib.eosp = 1;
++ }
++ //pxmitframe->attrib.triggered = 1; //maybe doesn't need in TDLS
++ if(rtw_hal_xmit(adapter, pxmitframe) == _TRUE)
++ {
++ rtw_os_xmit_complete(adapter, pxmitframe);
++ }
++
++ }
++
++ if(ptdls_sta->sleepq_len==0)
++ {
++ DBG_871X("no buffered packets for tdls to xmit\n");
++ //on U-APSD + CH. switch state, when there is no buffered date to xmit,
++ // we should go back to base channel
++ if(state==2){
++ rtw_tdls_cmd(adapter, ptdls_sta->hwaddr, TDLS_CS_OFF);
++ }else if(ptdls_sta->tdls_sta_state&TDLS_SW_OFF_STATE){
++ ptdls_sta->tdls_sta_state &= ~(TDLS_SW_OFF_STATE);
++ ptdlsinfo->candidate_ch= pmlmeext->cur_channel;
++ issue_tdls_ch_switch_req(adapter, pattrib->src);
++ DBG_871X("issue tdls ch switch req back to base channel\n");
++ }
++
++ }
++ else
++ {
++ DBG_871X("error!psta->sleepq_len=%d\n", ptdls_sta->sleepq_len);
++ ptdls_sta->sleepq_len=0;
++ }
++
++ _exit_critical_bh(&ptdls_sta->sleep_q.lock, &irqL);
++
++ }
++
++ }
++
++ return _FAIL;
++}
++
++sint On_TDLS_Ch_Switch_Req(_adapter *adapter, union recv_frame *precv_frame)
++{
++ struct sta_info *ptdls_sta= NULL;
++ struct sta_priv *pstapriv = &adapter->stapriv;
++ u8 *ptr = precv_frame->u.hdr.rx_data;
++ struct rx_pkt_attrib *prx_pkt_attrib = &precv_frame->u.hdr.attrib;
++ u8 *psa;
++ sint parsing_length;
++ PNDIS_802_11_VARIABLE_IEs pIE;
++ u8 FIXED_IE =3;
++ u16 j;
++ struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
++
++ psa = get_sa(ptr);
++ ptdls_sta = rtw_get_stainfo(pstapriv, psa);
++
++ ptr +=prx_pkt_attrib->hdrlen + prx_pkt_attrib->iv_len+LLC_HEADER_SIZE+TYPE_LENGTH_FIELD_SIZE+1;
++ parsing_length= ((union recv_frame *)precv_frame)->u.hdr.len
++ -prx_pkt_attrib->hdrlen
++ -prx_pkt_attrib->iv_len
++ -prx_pkt_attrib->icv_len
++ -LLC_HEADER_SIZE
++ -ETH_TYPE_LEN
++ -PAYLOAD_TYPE_LEN
++ -FIXED_IE;
++
++ ptdls_sta->off_ch = *(ptr+2);
++
++ //parsing information element
++ for(j=FIXED_IE; j<parsing_length;){
++
++ pIE = (PNDIS_802_11_VARIABLE_IEs)(ptr+ j);
++
++ switch (pIE->ElementID)
++ {
++ case _COUNTRY_IE_:
++ break;
++ case _CH_SWTICH_ANNOUNCE_:
++ break;
++ case _LINK_ID_IE_:
++ break;
++ case _CH_SWITCH_TIMING_:
++ _rtw_memcpy(&ptdls_sta->ch_switch_time, pIE->data, 2);
++ _rtw_memcpy(&ptdls_sta->ch_switch_timeout, pIE->data+2, 2);
++ default:
++ break;
++ }
++
++ j += (pIE->Length + 2);
++
++ }
++
++ //todo: check status
++ ptdls_sta->stat_code=0;
++ ptdls_sta->tdls_sta_state |= TDLS_CH_SWITCH_ON_STATE;
++
++ issue_nulldata(adapter, NULL, 1, 0, 0);
++
++ issue_tdls_ch_switch_rsp(adapter, psa);
++
++ DBG_871X("issue tdls channel switch response\n");
++
++ if((ptdls_sta->tdls_sta_state & TDLS_CH_SWITCH_ON_STATE) && ptdls_sta->off_ch==pmlmeext->cur_channel){
++ DBG_871X("back to base channel %x\n", pmlmeext->cur_channel);
++ ptdls_sta->option=7;
++ rtw_tdls_cmd(adapter, ptdls_sta->hwaddr, TDLS_BASE_CH);
++ }else{
++ ptdls_sta->option=6;
++ rtw_tdls_cmd(adapter, ptdls_sta->hwaddr, TDLS_OFF_CH);
++ }
++ return _FAIL;
++}
++
++sint On_TDLS_Ch_Switch_Rsp(_adapter *adapter, union recv_frame *precv_frame)
++{
++ struct sta_info *ptdls_sta= NULL;
++ struct sta_priv *pstapriv = &adapter->stapriv;
++ u8 *ptr = precv_frame->u.hdr.rx_data;
++ struct rx_pkt_attrib *prx_pkt_attrib = &precv_frame->u.hdr.attrib;
++ u8 *psa;
++ sint parsing_length;
++ PNDIS_802_11_VARIABLE_IEs pIE;
++ u8 FIXED_IE =4;
++ u16 stat_code, j, switch_time, switch_timeout;
++ struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
++
++ psa = get_sa(ptr);
++ ptdls_sta = rtw_get_stainfo(pstapriv, psa);
++
++ //if channel switch is running and receiving Unsolicited TDLS Channel Switch Response,
++ //it will go back to base channel and terminate this channel switch procedure
++ if(ptdls_sta->tdls_sta_state & TDLS_CH_SWITCH_ON_STATE ){
++ if(pmlmeext->cur_channel==ptdls_sta->off_ch){
++ DBG_871X("back to base channel %x\n", pmlmeext->cur_channel);
++ ptdls_sta->option=7;
++ rtw_tdls_cmd(adapter, ptdls_sta->hwaddr, TDLS_OFF_CH);
++ }else{
++ DBG_871X("receive unsolicited channel switch response \n");
++ rtw_tdls_cmd(adapter, ptdls_sta->hwaddr, TDLS_CS_OFF);
++ }
++ return _FAIL;
++ }
++
++ //avoiding duplicated or unconditional ch. switch. rsp
++ if((ptdls_sta->tdls_sta_state & TDLS_CH_SW_INITIATOR_STATE) != TDLS_CH_SW_INITIATOR_STATE)
++ return _FAIL;
++
++ ptr +=prx_pkt_attrib->hdrlen + prx_pkt_attrib->iv_len+LLC_HEADER_SIZE+TYPE_LENGTH_FIELD_SIZE+1;
++ parsing_length= ((union recv_frame *)precv_frame)->u.hdr.len
++ -prx_pkt_attrib->hdrlen
++ -prx_pkt_attrib->iv_len
++ -prx_pkt_attrib->icv_len
++ -LLC_HEADER_SIZE
++ -ETH_TYPE_LEN
++ -PAYLOAD_TYPE_LEN
++ -FIXED_IE;
++
++ _rtw_memcpy(&stat_code, ptr+2, 2);
++
++ if(stat_code!=0){
++ return _FAIL;
++ }
++
++ //parsing information element
++ for(j=FIXED_IE; j<parsing_length;){
++
++ pIE = (PNDIS_802_11_VARIABLE_IEs)(ptr+ j);
++
++ switch (pIE->ElementID)
++ {
++ case _LINK_ID_IE_:
++ break;
++ case _CH_SWITCH_TIMING_:
++ _rtw_memcpy(&switch_time, pIE->data, 2);
++ if(switch_time > ptdls_sta->ch_switch_time)
++ _rtw_memcpy(&ptdls_sta->ch_switch_time, &switch_time, 2);
++
++ _rtw_memcpy(&switch_timeout, pIE->data+2, 2);
++ if(switch_timeout > ptdls_sta->ch_switch_timeout)
++ _rtw_memcpy(&ptdls_sta->ch_switch_timeout, &switch_timeout, 2);
++
++ default:
++ break;
++ }
++
++ j += (pIE->Length + 2);
++
++ }
++
++ ptdls_sta->tdls_sta_state &= ~(TDLS_CH_SW_INITIATOR_STATE);
++ ptdls_sta->tdls_sta_state |=TDLS_CH_SWITCH_ON_STATE;
++
++ //goto set_channel_workitem_callback()
++ ptdls_sta->option=6;
++ rtw_tdls_cmd(adapter, ptdls_sta->hwaddr, TDLS_OFF_CH);
++
++ return _FAIL;
++}
++
++#ifdef CONFIG_WFD
++void wfd_ie_tdls(_adapter * padapter, u8 *pframe, u32 *pktlen )
++{
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct wifi_display_info *pwfd_info = padapter->tdlsinfo.wfd_info;
++ u8 wfdie[ MAX_WFD_IE_LEN] = { 0x00 };
++ u32 wfdielen = 0;
++
++ // WFD OUI
++ wfdielen = 0;
++ wfdie[ wfdielen++ ] = 0x50;
++ wfdie[ wfdielen++ ] = 0x6F;
++ wfdie[ wfdielen++ ] = 0x9A;
++ wfdie[ wfdielen++ ] = 0x0A; // WFA WFD v1.0
++
++ // Commented by Albert 20110825
++ // According to the WFD Specification, the negotiation request frame should contain 3 WFD attributes
++ // 1. WFD Device Information
++ // 2. Associated BSSID ( Optional )
++ // 3. Local IP Adress ( Optional )
++
++ // WFD Device Information ATTR
++ // Type:
++ wfdie[ wfdielen++ ] = WFD_ATTR_DEVICE_INFO;
++
++ // Length:
++ // Note: In the WFD specification, the size of length field is 2.
++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
++ wfdielen += 2;
++
++ // Value1:
++ // WFD device information
++ // available for WFD session + Preferred TDLS + WSD ( WFD Service Discovery )
++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL
++ | WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_WSD);
++ wfdielen += 2;
++
++ // Value2:
++ // Session Management Control Port
++ // Default TCP port for RTSP messages is 554
++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport );
++ wfdielen += 2;
++
++ // Value3:
++ // WFD Device Maximum Throughput
++ // 300Mbps is the maximum throughput
++ RTW_PUT_BE16(wfdie + wfdielen, 300);
++ wfdielen += 2;
++
++ // Associated BSSID ATTR
++ // Type:
++ wfdie[ wfdielen++ ] = WFD_ATTR_ASSOC_BSSID;
++
++ // Length:
++ // Note: In the WFD specification, the size of length field is 2.
++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
++ wfdielen += 2;
++
++ // Value:
++ // Associated BSSID
++ if ( check_fwstate( pmlmepriv, _FW_LINKED) == _TRUE )
++ {
++ _rtw_memcpy( wfdie + wfdielen, &pmlmepriv->assoc_bssid[ 0 ], ETH_ALEN );
++ }
++ else
++ {
++ _rtw_memset( wfdie + wfdielen, 0x00, ETH_ALEN );
++ }
++
++ // Local IP Address ATTR
++ wfdie[ wfdielen++ ] = WFD_ATTR_LOCAL_IP_ADDR;
++
++ // Length:
++ // Note: In the WFD specification, the size of length field is 2.
++ RTW_PUT_BE16(wfdie + wfdielen, 0x0005);
++ wfdielen += 2;
++
++ // Version:
++ // 0x01: Version1;IPv4
++ wfdie[ wfdielen++ ] = 0x01;
++
++ // IPv4 Address
++ _rtw_memcpy( wfdie + wfdielen, pwfd_info->ip_address, 4 );
++ wfdielen += 4;
++
++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, pktlen);
++
++}
++#endif //CONFIG_WFD
++
++void rtw_build_tdls_setup_req_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe)
++{
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
++ struct pkt_attrib *pattrib = &pxmitframe->attrib;
++ struct registry_priv *pregistrypriv = &padapter->registrypriv;
++ struct sta_info *ptdls_sta=rtw_get_stainfo( (&padapter->stapriv) , pattrib->dst);
++
++ u8 payload_type = 0x02;
++ u8 category = RTW_WLAN_CATEGORY_TDLS;
++ u8 action = TDLS_SETUP_REQUEST;
++ u8 bssrate[NDIS_802_11_LENGTH_RATES_EX]; //Use NDIS_802_11_LENGTH_RATES_EX in order to call func.rtw_set_supported_rate
++ int bssrate_len = 0, i = 0 ;
++ u8 more_supportedrates = 0;
++ unsigned int ie_len;
++ u8 *p;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ u8 link_id_addr[18] = {0};
++ u8 iedata=0;
++ u8 sup_ch[ 30 * 2 ] = {0x00 }, sup_ch_idx = 0, idx_5g = 2; //For supported channel
++ u8 timeout_itvl[5]; //set timeout interval to maximum value
++ u32 time;
++
++ //SNonce
++ if(pattrib->encrypt){
++ for(i=0;i<8;i++){
++ time=rtw_get_current_time();
++ _rtw_memcpy(&ptdls_sta->SNonce[4*i], (u8 *)&time, 4);
++ }
++ }
++
++ //payload type
++ pframe = rtw_set_fixed_ie(pframe, 1, &(payload_type), &(pattrib->pktlen));
++ //category, action, dialog token
++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
++ pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));
++ pframe = rtw_set_fixed_ie(pframe, 1, &(ptdls_sta->dialog), &(pattrib->pktlen));
++
++ //capability
++ _rtw_memcpy(pframe, rtw_get_capability_from_ie(pmlmeinfo->network.IEs), 2);
++
++ if(pattrib->encrypt)
++ *pframe =*pframe | BIT(4);
++ pframe += 2;
++ pattrib->pktlen += 2;
++
++ //supported rates
++ rtw_set_supported_rate(bssrate, WIRELESS_11BG_24N);
++ bssrate_len = IEEE80211_CCK_RATE_LEN + IEEE80211_NUM_OFDM_RATESLEN;
++
++ if (bssrate_len > 8)
++ {
++ pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , 8, bssrate, &(pattrib->pktlen));
++ more_supportedrates = 1;
++ }
++ else
++ {
++ pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , bssrate_len , bssrate, &(pattrib->pktlen));
++ }
++
++ //country(optional)
++ //extended supported rates
++ if(more_supportedrates==1){
++ pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_ , (bssrate_len - 8), (bssrate + 8), &(pattrib->pktlen));
++ }
++
++ //supported channels
++ pframe = rtw_tdls_set_sup_ch(pmlmeext, pframe, pattrib);
++
++ // SRC IE
++ pframe = rtw_set_ie( pframe, _SRC_IE_, 16, TDLS_SRC, &(pattrib->pktlen));
++
++ //RSNIE
++ if(pattrib->encrypt)
++ pframe = rtw_set_ie(pframe, _RSN_IE_2_, 20, TDLS_RSNIE, &(pattrib->pktlen));
++
++ //extended capabilities
++ pframe = rtw_set_ie(pframe, _EXT_CAP_IE_ , 5, TDLS_EXT_CAPIE, &(pattrib->pktlen));
++
++ //QoS capability(WMM_IE)
++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, 7, TDLS_WMMIE, &(pattrib->pktlen));
++
++
++ if(pattrib->encrypt){
++ //FTIE
++ _rtw_memset(pframe, 0, 84); //All fields except SNonce shall be set to 0
++ _rtw_memset(pframe, _FTIE_, 1); //version
++ _rtw_memset((pframe+1), 82, 1); //length
++ _rtw_memcpy((pframe+52), ptdls_sta->SNonce, 32);
++ pframe += 84;
++ pattrib->pktlen += 84;
++
++ //Timeout interval
++ timeout_itvl[0]=0x02;
++ _rtw_memcpy(timeout_itvl+1, (u8 *)(&ptdls_sta->TDLS_PeerKey_Lifetime), 4);
++ pframe = rtw_set_ie(pframe, _TIMEOUT_ITVL_IE_, 5, timeout_itvl, &(pattrib->pktlen));
++ }
++
++ //Sup_reg_classes(optional)
++ //HT capabilities
++ pframe = rtw_tdls_set_ht_cap(padapter, pframe, pattrib);
++
++ //20/40 BSS coexistence
++ if(pmlmepriv->num_FortyMHzIntolerant>0)
++ iedata |= BIT(2);//20 MHz BSS Width Request
++ pframe = rtw_set_ie(pframe, EID_BSSCoexistence, 1, &iedata, &(pattrib->pktlen));
++
++ //Link identifier
++ _rtw_memcpy(link_id_addr, pattrib->ra, 6);
++ _rtw_memcpy((link_id_addr+6), pattrib->src, 6);
++ _rtw_memcpy((link_id_addr+12), pattrib->dst, 6);
++ pframe = rtw_set_ie(pframe, _LINK_ID_IE_, 18, link_id_addr, &(pattrib->pktlen));
++
++#ifdef CONFIG_WFD
++ wfd_ie_tdls( padapter, pframe, &(pattrib->pktlen) );
++#endif //CONFIG_WFD
++
++}
++
++void rtw_build_tdls_setup_rsp_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe)
++{
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ struct pkt_attrib *pattrib = &pxmitframe->attrib;
++ struct sta_info *ptdls_sta;
++ struct registry_priv *pregistrypriv = &padapter->registrypriv;
++
++ u8 payload_type = 0x02;
++ unsigned char category = RTW_WLAN_CATEGORY_TDLS;
++ unsigned char action = TDLS_SETUP_RESPONSE;
++ unsigned char bssrate[NDIS_802_11_LENGTH_RATES_EX];
++ int bssrate_len = 0;
++ u8 more_supportedrates = 0;
++ unsigned int ie_len;
++ unsigned char *p;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ u8 link_id_addr[18] = {0};
++ u8 iedata=0;
++ u8 timeout_itvl[5]; //setup response timeout interval will copy from request
++ u8 ANonce[32]; //maybe it can put in ontdls_req
++ u8 k; //for random ANonce
++ u8 *pftie, *ptimeout_ie, *plinkid_ie, *prsnie, *pftie_mic;
++ u32 time;
++
++ ptdls_sta = rtw_get_stainfo( &(padapter->stapriv) , pattrib->dst);
++
++ if(ptdls_sta == NULL )
++ {
++ DBG_871X("[%s] %d\n", __FUNCTION__, __LINE__);
++ return;
++ }
++
++ if(pattrib->encrypt){
++ for(k=0;k<8;k++){
++ time=rtw_get_current_time();
++ _rtw_memcpy(&ptdls_sta->ANonce[4*k], (u8*)&time, 4);
++ }
++ }
++
++ //payload type
++ pframe = rtw_set_fixed_ie(pframe, 1, &(payload_type), &(pattrib->pktlen));
++ //category, action, status code
++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
++ pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));
++ pframe = rtw_set_fixed_ie(pframe, 2, (u8 *)&ptdls_sta->stat_code, &(pattrib->pktlen));
++
++ if(ptdls_sta->stat_code!=0) //invalid setup request
++ {
++ DBG_871X("ptdls_sta->stat_code:%04x \n", ptdls_sta->stat_code);
++ return;
++ }
++
++ //dialog token
++ pframe = rtw_set_fixed_ie(pframe, 1, &(ptdls_sta->dialog), &(pattrib->pktlen));
++
++ //capability
++ _rtw_memcpy(pframe, rtw_get_capability_from_ie(pmlmeinfo->network.IEs), 2);
++
++ if(pattrib->encrypt )
++ *pframe =*pframe | BIT(4);
++ pframe += 2;
++ pattrib->pktlen += 2;
++
++ //supported rates
++ rtw_set_supported_rate(bssrate, WIRELESS_11BG_24N);
++ bssrate_len = IEEE80211_CCK_RATE_LEN + IEEE80211_NUM_OFDM_RATESLEN;
++
++ if (bssrate_len > 8)
++ {
++ pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , 8, bssrate, &(pattrib->pktlen));
++ more_supportedrates = 1;
++ }
++ else
++ {
++ pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , bssrate_len , bssrate, &(pattrib->pktlen));
++ }
++
++ //country(optional)
++ //extended supported rates
++ if(more_supportedrates==1){
++ pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_ , (bssrate_len - 8), (bssrate + 8), &(pattrib->pktlen));
++ }
++
++ //supported channels
++ pframe = rtw_tdls_set_sup_ch(pmlmeext, pframe, pattrib);
++
++ // SRC IE
++ pframe = rtw_set_ie(pframe, _SRC_IE_ , 16, TDLS_SRC, &(pattrib->pktlen));
++
++ //RSNIE
++ if(pattrib->encrypt){
++ prsnie = pframe;
++ pframe = rtw_set_ie(pframe, _RSN_IE_2_, 20, TDLS_RSNIE, &(pattrib->pktlen));
++ }
++
++ //extended capabilities
++ pframe = rtw_set_ie(pframe, _EXT_CAP_IE_ , 5, TDLS_EXT_CAPIE, &(pattrib->pktlen));
++
++ //QoS capability(WMM_IE)
++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, 7, TDLS_WMMIE, &(pattrib->pktlen));
++
++ if(pattrib->encrypt){
++ wpa_tdls_generate_tpk(padapter, ptdls_sta);
++
++ //FTIE
++ pftie = pframe;
++ pftie_mic = pframe+4;
++ _rtw_memset(pframe, 0, 84); //All fields except SNonce shall be set to 0
++ _rtw_memset(pframe, _FTIE_, 1); //version
++ _rtw_memset((pframe+1), 82, 1); //length
++ _rtw_memcpy((pframe+20), ptdls_sta->ANonce, 32);
++ _rtw_memcpy((pframe+52), ptdls_sta->SNonce, 32);
++ pframe += 84;
++ pattrib->pktlen += 84;
++
++ //Timeout interval
++ ptimeout_ie = pframe;
++ timeout_itvl[0]=0x02;
++ _rtw_memcpy(timeout_itvl+1, (u8 *)(&ptdls_sta->TDLS_PeerKey_Lifetime), 4);
++ pframe = rtw_set_ie(pframe, _TIMEOUT_ITVL_IE_, 5, timeout_itvl, &(pattrib->pktlen));
++ }
++
++ //Sup_reg_classes(optional)
++ //HT capabilities
++ pframe = rtw_tdls_set_ht_cap(padapter, pframe, pattrib);
++
++ //20/40 BSS coexistence
++ if(pmlmepriv->num_FortyMHzIntolerant>0)
++ iedata |= BIT(2);//20 MHz BSS Width Request
++ pframe = rtw_set_ie(pframe, EID_BSSCoexistence, 1, &iedata, &(pattrib->pktlen));
++
++ //Link identifier
++ plinkid_ie = pframe;
++ _rtw_memcpy(link_id_addr, pattrib->ra, 6);
++ _rtw_memcpy((link_id_addr+6), pattrib->dst, 6);
++ _rtw_memcpy((link_id_addr+12), pattrib->src, 6);
++ pframe = rtw_set_ie(pframe, _LINK_ID_IE_, 18, link_id_addr, &(pattrib->pktlen));
++
++ //fill FTIE mic
++ if(pattrib->encrypt)
++ wpa_tdls_ftie_mic(ptdls_sta->tpk.kck, 2, plinkid_ie, prsnie, ptimeout_ie, pftie, pftie_mic);
++
++#ifdef CONFIG_WFD
++ wfd_ie_tdls( padapter, pframe, &(pattrib->pktlen) );
++#endif //CONFIG_WFD
++
++}
++
++void rtw_build_tdls_setup_cfm_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe)
++{
++
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ struct pkt_attrib *pattrib = &pxmitframe->attrib;
++ struct sta_info *ptdls_sta=rtw_get_stainfo( (&padapter->stapriv) , pattrib->dst);
++
++ u8 payload_type = 0x02;
++ unsigned char category = RTW_WLAN_CATEGORY_TDLS;
++ unsigned char action = TDLS_SETUP_CONFIRM;
++ u8 more_supportedrates = 0;
++ unsigned int ie_len;
++ unsigned char *p;
++ u8 timeout_itvl[5]; //set timeout interval to maximum value
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ u8 link_id_addr[18] = {0};
++ u8 *pftie, *ptimeout_ie, *plinkid_ie, *prsnie, *pftie_mic;
++
++ //payload type
++ pframe = rtw_set_fixed_ie(pframe, 1, &(payload_type), &(pattrib->pktlen));
++ //category, action, status code, dialog token
++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
++ pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));
++ pframe = rtw_set_fixed_ie(pframe, 2, (u8 *)&ptdls_sta->stat_code, &(pattrib->pktlen));
++ pframe = rtw_set_fixed_ie(pframe, 1, &(ptdls_sta->dialog), &(pattrib->pktlen));
++
++ if(ptdls_sta->stat_code!=0) //invalid setup request
++ return;
++
++ //RSNIE
++ if(pattrib->encrypt){
++ prsnie = pframe;
++ pframe = rtw_set_ie(pframe, _RSN_IE_2_, 20, TDLS_RSNIE, &(pattrib->pktlen));
++ }
++
++ //EDCA param set; WMM param ele.
++ if(pattrib->encrypt){
++ //FTIE
++ pftie = pframe;
++ pftie_mic = pframe+4;
++ _rtw_memset(pframe, 0, 84); //All fields except SNonce shall be set to 0
++ _rtw_memset(pframe, _FTIE_, 1); //version
++ _rtw_memset((pframe+1), 82, 1); //length
++ _rtw_memcpy((pframe+20), ptdls_sta->ANonce, 32);
++ _rtw_memcpy((pframe+52), ptdls_sta->SNonce, 32);
++ pframe += 84;
++ pattrib->pktlen += 84;
++
++ //Timeout interval
++ ptimeout_ie = pframe;
++ timeout_itvl[0]=0x02;
++ _rtw_memcpy(timeout_itvl+1, (u8 *)(&ptdls_sta->TDLS_PeerKey_Lifetime), 4);
++ ptdls_sta->TPK_count=0;
++ _set_timer(&ptdls_sta->TPK_timer, ptdls_sta->TDLS_PeerKey_Lifetime/TPK_RESEND_COUNT);
++ pframe = rtw_set_ie(pframe, _TIMEOUT_ITVL_IE_, 5, timeout_itvl, &(pattrib->pktlen));
++ }
++
++ //HT operation; todo
++ //Link identifier
++ plinkid_ie = pframe;
++ _rtw_memcpy(link_id_addr, pattrib->ra, 6);
++ _rtw_memcpy((link_id_addr+6), pattrib->src, 6);
++ _rtw_memcpy((link_id_addr+12), pattrib->dst, 6);
++ pframe = rtw_set_ie(pframe, _LINK_ID_IE_, 18, link_id_addr, &(pattrib->pktlen));
++
++ //fill FTIE mic
++ if(pattrib->encrypt)
++ wpa_tdls_ftie_mic(ptdls_sta->tpk.kck, 3, plinkid_ie, prsnie, ptimeout_ie, pftie, pftie_mic);
++
++}
++
++void rtw_build_tdls_teardown_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe)
++{
++
++ struct pkt_attrib *pattrib = &pxmitframe->attrib;
++ u8 payload_type = 0x02;
++ unsigned char category = RTW_WLAN_CATEGORY_TDLS;
++ unsigned char action = TDLS_TEARDOWN;
++ u8 link_id_addr[18] = {0};
++
++ struct sta_info *ptdls_sta = rtw_get_stainfo( &(padapter->stapriv) , pattrib->dst);
++ struct sta_priv *pstapriv = &padapter->stapriv;
++
++ //payload type
++ pframe = rtw_set_fixed_ie(pframe, 1, &(payload_type), &(pattrib->pktlen));
++ //category, action, reason code
++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
++ pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));
++ pframe = rtw_set_fixed_ie(pframe, 1, (u8 *)&ptdls_sta->stat_code, &(pattrib->pktlen));
++
++ //Link identifier
++ if(ptdls_sta->tdls_sta_state & TDLS_INITIATOR_STATE){
++ _rtw_memcpy(link_id_addr, pattrib->ra, 6);
++ _rtw_memcpy((link_id_addr+6), pattrib->src, 6);
++ _rtw_memcpy((link_id_addr+12), pattrib->dst, 6);
++ }else if(ptdls_sta->tdls_sta_state & TDLS_RESPONDER_STATE){
++ _rtw_memcpy(link_id_addr, pattrib->ra, 6);
++ _rtw_memcpy((link_id_addr+6), pattrib->dst, 6);
++ _rtw_memcpy((link_id_addr+12), pattrib->src, 6);
++ }
++ pframe = rtw_set_ie(pframe, _LINK_ID_IE_, 18, link_id_addr, &(pattrib->pktlen));
++
++}
++
++void rtw_build_tdls_dis_req_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe)
++{
++
++ struct pkt_attrib *pattrib = &pxmitframe->attrib;
++ u8 payload_type = 0x02;
++ u8 category = RTW_WLAN_CATEGORY_TDLS;
++ u8 action = TDLS_DISCOVERY_REQUEST;
++ u8 link_id_addr[18] = {0};
++ static u8 dialogtoken=0;
++
++ //payload type
++ pframe = rtw_set_fixed_ie(pframe, 1, &(payload_type), &(pattrib->pktlen));
++ //category, action, reason code
++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
++ pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));
++ pframe = rtw_set_fixed_ie(pframe, 1, &(dialogtoken), &(pattrib->pktlen));
++ dialogtoken = (dialogtoken+1)%256;
++
++ //Link identifier
++ _rtw_memcpy(link_id_addr, pattrib->ra, 6);
++ _rtw_memcpy((link_id_addr+6), pattrib->src, 6);
++ _rtw_memcpy((link_id_addr+12), pattrib->dst, 6);
++ pframe = rtw_set_ie(pframe, _LINK_ID_IE_, 18, link_id_addr, &(pattrib->pktlen));
++
++}
++
++void rtw_build_tdls_dis_rsp_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe, u8 dialog)
++{
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
++ struct pkt_attrib *pattrib = &pxmitframe->attrib;
++ struct registry_priv *pregistrypriv = &padapter->registrypriv;
++
++ u8 category = RTW_WLAN_CATEGORY_PUBLIC;
++ u8 action = TDLS_DISCOVERY_RESPONSE;
++ u8 bssrate[NDIS_802_11_LENGTH_RATES_EX];
++ int bssrate_len = 0;
++ u8 more_supportedrates = 0;
++ u8 *p;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ u8 link_id_addr[18] = {0};
++ u8 iedata=0;
++ u8 timeout_itvl[5]; //set timeout interval to maximum value
++ u32 timeout_interval= TPK_RESEND_COUNT * 1000;
++
++ //category, action, dialog token
++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
++ pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));
++ pframe = rtw_set_fixed_ie(pframe, 1, &(dialog), &(pattrib->pktlen));
++
++ //capability
++ _rtw_memcpy(pframe, rtw_get_capability_from_ie(pmlmeinfo->network.IEs), 2);
++
++ if(pattrib->encrypt)
++ *pframe =*pframe | BIT(4);
++ pframe += 2;
++ pattrib->pktlen += 2;
++
++ //supported rates
++ rtw_set_supported_rate(bssrate, WIRELESS_11BG_24N);
++ bssrate_len = IEEE80211_CCK_RATE_LEN + IEEE80211_NUM_OFDM_RATESLEN;
++
++ if (bssrate_len > 8)
++ {
++ pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , 8, bssrate, &(pattrib->pktlen));
++ more_supportedrates = 1;
++ }
++ else
++ {
++ pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , bssrate_len , bssrate, &(pattrib->pktlen));
++ }
++
++ //extended supported rates
++ if(more_supportedrates==1){
++ pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_ , (bssrate_len - 8), (bssrate + 8), &(pattrib->pktlen));
++ }
++
++ //supported channels
++ pframe = rtw_tdls_set_sup_ch(pmlmeext, pframe, pattrib);
++
++ //RSNIE
++ if(pattrib->encrypt)
++ pframe = rtw_set_ie(pframe, _RSN_IE_2_, 20, TDLS_RSNIE, &(pattrib->pktlen));
++
++ //extended capability
++ pframe = rtw_set_ie(pframe, _EXT_CAP_IE_ , 5, TDLS_EXT_CAPIE, &(pattrib->pktlen));
++
++ if(pattrib->encrypt){
++ //FTIE
++ _rtw_memset(pframe, 0, 84); //All fields shall be set to 0
++ _rtw_memset(pframe, _FTIE_, 1); //version
++ _rtw_memset((pframe+1), 82, 1); //length
++ pframe += 84;
++ pattrib->pktlen += 84;
++
++ //Timeout interval
++ timeout_itvl[0]=0x02;
++ _rtw_memcpy(timeout_itvl+1, &timeout_interval, 4);
++ pframe = rtw_set_ie(pframe, _TIMEOUT_ITVL_IE_, 5, timeout_itvl, &(pattrib->pktlen));
++ }
++
++ //Sup_reg_classes(optional)
++ //HT capabilities
++ pframe = rtw_tdls_set_ht_cap(padapter, pframe, pattrib);
++
++ //20/40 BSS coexistence
++ if(pmlmepriv->num_FortyMHzIntolerant>0)
++ iedata |= BIT(2);//20 MHz BSS Width Request
++ pframe = rtw_set_ie(pframe, EID_BSSCoexistence, 1, &iedata, &(pattrib->pktlen));
++
++ //Link identifier
++ _rtw_memcpy(link_id_addr, pattrib->ra, 6);
++ _rtw_memcpy((link_id_addr+6), pattrib->dst, 6);
++ _rtw_memcpy((link_id_addr+12), pattrib->src, 6);
++ pframe = rtw_set_ie(pframe, _LINK_ID_IE_, 18, link_id_addr, &(pattrib->pktlen));
++
++}
++
++void rtw_build_tdls_peer_traffic_indication_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe)
++{
++
++ struct pkt_attrib *pattrib = &pxmitframe->attrib;
++ u8 payload_type = 0x02;
++ unsigned char category = RTW_WLAN_CATEGORY_TDLS;
++ unsigned char action = TDLS_PEER_TRAFFIC_INDICATION;
++
++ u8 link_id_addr[18] = {0};
++ u8 AC_queue=0;
++ struct sta_priv *pstapriv = &padapter->stapriv;
++ struct sta_info *ptdls_sta = rtw_get_stainfo(pstapriv, pattrib->dst);
++
++ //payload type
++ pframe = rtw_set_fixed_ie(pframe, 1, &(payload_type), &(pattrib->pktlen));
++ //category, action, reason code
++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
++ pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));
++ pframe = rtw_set_fixed_ie(pframe, 1, &(ptdls_sta->dialog), &(pattrib->pktlen));
++
++ //Link identifier
++ _rtw_memcpy(link_id_addr, pattrib->ra, 6);
++ _rtw_memcpy((link_id_addr+6), pattrib->src, 6);
++ _rtw_memcpy((link_id_addr+12), pattrib->dst, 6);
++ pframe = rtw_set_ie(pframe, _LINK_ID_IE_, 18, link_id_addr, &(pattrib->pktlen));
++
++ //PTI control
++ //PU buffer status
++ if(ptdls_sta->uapsd_bk&BIT(1))
++ AC_queue=BIT(0);
++ if(ptdls_sta->uapsd_be&BIT(1))
++ AC_queue=BIT(1);
++ if(ptdls_sta->uapsd_vi&BIT(1))
++ AC_queue=BIT(2);
++ if(ptdls_sta->uapsd_vo&BIT(1))
++ AC_queue=BIT(3);
++ pframe = rtw_set_ie(pframe, _PTI_BUFFER_STATUS_, 1, &AC_queue, &(pattrib->pktlen));
++
++}
++
++void rtw_build_tdls_ch_switch_req_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe)
++{
++
++ struct pkt_attrib *pattrib = &pxmitframe->attrib;
++ struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
++ u8 payload_type = 0x02;
++ unsigned char category = RTW_WLAN_CATEGORY_TDLS;
++ unsigned char action = TDLS_CHANNEL_SWITCH_REQUEST;
++ u8 link_id_addr[18] = {0};
++ struct sta_priv *pstapriv = &padapter->stapriv;
++ struct sta_info *ptdls_sta = rtw_get_stainfo(pstapriv, pattrib->dst);
++ u8 ch_switch_timing[4] = {0};
++ u16 switch_time= CH_SWITCH_TIME, switch_timeout=CH_SWITCH_TIMEOUT;
++
++ //payload type
++ pframe = rtw_set_fixed_ie(pframe, 1, &(payload_type), &(pattrib->pktlen));
++ //category, action, target_ch
++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
++ pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));
++ pframe = rtw_set_fixed_ie(pframe, 1, &(ptdlsinfo->candidate_ch), &(pattrib->pktlen));
++
++ //Link identifier
++ _rtw_memcpy(link_id_addr, pattrib->ra, 6);
++ _rtw_memcpy((link_id_addr+6), pattrib->src, 6);
++ _rtw_memcpy((link_id_addr+12), pattrib->dst, 6);
++ pframe = rtw_set_ie(pframe, _LINK_ID_IE_, 18, link_id_addr, &(pattrib->pktlen));
++
++ //ch switch timing
++ _rtw_memcpy(ch_switch_timing, &switch_time, 2);
++ _rtw_memcpy(ch_switch_timing+2, &switch_timeout, 2);
++ pframe = rtw_set_ie(pframe, _CH_SWITCH_TIMING_, 4, ch_switch_timing, &(pattrib->pktlen));
++
++ //update ch switch attrib to sta_info
++ ptdls_sta->off_ch=ptdlsinfo->candidate_ch;
++ ptdls_sta->ch_switch_time=switch_time;
++ ptdls_sta->ch_switch_timeout=switch_timeout;
++
++}
++
++void rtw_build_tdls_ch_switch_rsp_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe)
++{
++
++ struct pkt_attrib *pattrib = &pxmitframe->attrib;
++ u8 payload_type = 0x02;
++ unsigned char category = RTW_WLAN_CATEGORY_TDLS;
++ unsigned char action = TDLS_CHANNEL_SWITCH_RESPONSE;
++ u8 link_id_addr[18] = {0};
++ struct sta_priv *pstapriv = &padapter->stapriv;
++ struct sta_info *ptdls_sta = rtw_get_stainfo(pstapriv, pattrib->dst);
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
++ u8 ch_switch_timing[4] = {0};
++
++ //payload type
++ pframe = rtw_set_fixed_ie(pframe, 1, &(payload_type), &(pattrib->pktlen));
++ //category, action, status_code
++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
++ pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));
++ pframe = rtw_set_fixed_ie(pframe, 2, (u8 *)&ptdls_sta->stat_code, &(pattrib->pktlen));
++
++ //Link identifier
++ _rtw_memcpy(link_id_addr, pattrib->ra, 6);
++ _rtw_memcpy((link_id_addr+6), pattrib->src, 6);
++ _rtw_memcpy((link_id_addr+12), pattrib->dst, 6);
++ pframe = rtw_set_ie(pframe, _LINK_ID_IE_, 18, link_id_addr, &(pattrib->pktlen));
++
++ //ch switch timing
++ _rtw_memcpy(ch_switch_timing, &ptdls_sta->ch_switch_time, 2);
++ _rtw_memcpy(ch_switch_timing+2, &ptdls_sta->ch_switch_timeout, 2);
++ pframe = rtw_set_ie(pframe, _CH_SWITCH_TIMING_, 4, ch_switch_timing, &(pattrib->pktlen));
++
++}
++
++#ifdef CONFIG_WFD
++void rtw_build_tunneled_probe_req_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe)
++{
++
++ struct pkt_attrib *pattrib = &pxmitframe->attrib;
++ struct wifidirect_info *pwdinfo = &padapter->wdinfo;
++ struct wifidirect_info *pbuddy_wdinfo = &padapter->pbuddy_adapter->wdinfo;
++ u8 payload_type = 0x02;
++ u8 category = RTW_WLAN_CATEGORY_P2P;
++ u8 WFA_OUI[3] = { 0x50, 0x6f, 0x9a};
++ u8 probe_req = 4;
++ u8 wfdielen = 0;
++
++ //payload type
++ pframe = rtw_set_fixed_ie(pframe, 1, &(payload_type), &(pattrib->pktlen));
++ //category, OUI, frame_body_type
++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
++ pframe = rtw_set_fixed_ie(pframe, 3, WFA_OUI, &(pattrib->pktlen));
++ pframe = rtw_set_fixed_ie(pframe, 1, &(probe_req), &(pattrib->pktlen));
++
++ if(!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
++ {
++ wfdielen = build_probe_req_wfd_ie(pwdinfo, pframe);
++ pframe += wfdielen;
++ pattrib->pktlen += wfdielen;
++ }
++ else if(!rtw_p2p_chk_state(pbuddy_wdinfo, P2P_STATE_NONE))
++ {
++ wfdielen = build_probe_req_wfd_ie(pbuddy_wdinfo, pframe);
++ pframe += wfdielen;
++ pattrib->pktlen += wfdielen;
++ }
++
++}
++
++void rtw_build_tunneled_probe_rsp_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe)
++{
++
++ struct pkt_attrib *pattrib = &pxmitframe->attrib;
++ struct wifidirect_info *pwdinfo = &padapter->wdinfo;
++ struct wifidirect_info *pbuddy_wdinfo = &padapter->pbuddy_adapter->wdinfo;
++ u8 payload_type = 0x02;
++ u8 category = RTW_WLAN_CATEGORY_P2P;
++ u8 WFA_OUI[3] = { 0x50, 0x6f, 0x9a};
++ u8 probe_rsp = 5;
++ u8 wfdielen = 0;
++
++ //payload type
++ pframe = rtw_set_fixed_ie(pframe, 1, &(payload_type), &(pattrib->pktlen));
++ //category, OUI, frame_body_type
++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
++ pframe = rtw_set_fixed_ie(pframe, 3, WFA_OUI, &(pattrib->pktlen));
++ pframe = rtw_set_fixed_ie(pframe, 1, &(probe_rsp), &(pattrib->pktlen));
++
++ if(!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
++ {
++ wfdielen = build_probe_resp_wfd_ie(pwdinfo, pframe, 1);
++ pframe += wfdielen;
++ pattrib->pktlen += wfdielen;
++ }
++ else if(!rtw_p2p_chk_state(pbuddy_wdinfo, P2P_STATE_NONE))
++ {
++ wfdielen = build_probe_resp_wfd_ie(pbuddy_wdinfo, pframe, 1);
++ pframe += wfdielen;
++ pattrib->pktlen += wfdielen;
++ }
++
++}
++#endif //CONFIG_WFD
++
++void _TPK_timer_hdl(void *FunctionContext)
++{
++ struct sta_info *ptdls_sta = (struct sta_info *)FunctionContext;
++
++ ptdls_sta->TPK_count++;
++ //TPK_timer set 1000 as default
++ //retry timer should set at least 301 sec.
++ if(ptdls_sta->TPK_count==TPK_RESEND_COUNT){
++ ptdls_sta->TPK_count=0;
++ issue_tdls_setup_req(ptdls_sta->padapter, ptdls_sta->hwaddr);
++ }
++
++ _set_timer(&ptdls_sta->TPK_timer, ptdls_sta->TDLS_PeerKey_Lifetime/TPK_RESEND_COUNT);
++}
++
++void init_TPK_timer(_adapter *padapter, struct sta_info *psta)
++{
++ psta->padapter=padapter;
++
++ _init_timer(&psta->TPK_timer, padapter->pnetdev, _TPK_timer_hdl, psta);
++}
++
++// TDLS_DONE_CH_SEN: channel sensing and report candidate channel
++// TDLS_OFF_CH: first time set channel to off channel
++// TDLS_BASE_CH: when go back to the channel linked with AP, send null data to peer STA as an indication
++void _ch_switch_timer_hdl(void *FunctionContext)
++{
++
++ struct sta_info *ptdls_sta = (struct sta_info *)FunctionContext;
++ _adapter *padapter = ptdls_sta->padapter;
++
++ if( ptdls_sta->option == TDLS_DONE_CH_SEN ){
++ rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_DONE_CH_SEN);
++ }else if( ptdls_sta->option == TDLS_OFF_CH ){
++ issue_nulldata_to_TDLS_peer_STA(ptdls_sta->padapter, ptdls_sta, 0);
++ _set_timer(&ptdls_sta->base_ch_timer, 500);
++ }else if( ptdls_sta->option == TDLS_BASE_CH){
++ issue_nulldata_to_TDLS_peer_STA(ptdls_sta->padapter, ptdls_sta, 0);
++ }
++}
++
++void init_ch_switch_timer(_adapter *padapter, struct sta_info *psta)
++{
++ psta->padapter=padapter;
++ _init_timer(&psta->option_timer, padapter->pnetdev, _ch_switch_timer_hdl, psta);
++}
++
++void _base_ch_timer_hdl(void *FunctionContext)
++{
++ struct sta_info *ptdls_sta = (struct sta_info *)FunctionContext;
++ rtw_tdls_cmd(ptdls_sta->padapter, ptdls_sta->hwaddr, TDLS_P_OFF_CH);
++}
++
++void init_base_ch_timer(_adapter *padapter, struct sta_info *psta)
++{
++ psta->padapter=padapter;
++ _init_timer(&psta->base_ch_timer, padapter->pnetdev, _base_ch_timer_hdl, psta);
++}
++
++void _off_ch_timer_hdl(void *FunctionContext)
++{
++ struct sta_info *ptdls_sta = (struct sta_info *)FunctionContext;
++ rtw_tdls_cmd(ptdls_sta->padapter, ptdls_sta->hwaddr, TDLS_P_BASE_CH );
++}
++
++void init_off_ch_timer(_adapter *padapter, struct sta_info *psta)
++{
++ psta->padapter=padapter;
++ _init_timer(&psta->off_ch_timer, padapter->pnetdev, _off_ch_timer_hdl, psta);
++}
++
++void _tdls_handshake_timer_hdl(void *FunctionContext)
++{
++ struct sta_info *ptdls_sta = (struct sta_info *)FunctionContext;
++
++ if(ptdls_sta != NULL)
++ {
++ if( !(ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE) )
++ {
++ DBG_871X("tdls handshake time out\n");
++ free_tdls_sta(ptdls_sta->padapter, ptdls_sta);
++ }
++ }
++}
++
++void init_handshake_timer(_adapter *padapter, struct sta_info *psta)
++{
++ psta->padapter=padapter;
++ _init_timer(&psta->handshake_timer, padapter->pnetdev, _tdls_handshake_timer_hdl, psta);
++}
++
++//Check tdls peer sta alive.
++void _tdls_alive_timer_phase1_hdl(void *FunctionContext)
++{
++ _irqL irqL;
++ struct sta_info *ptdls_sta = (struct sta_info *)FunctionContext;
++ _adapter *padapter = ptdls_sta->padapter;
++ struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
++
++ _enter_critical_bh(&ptdlsinfo->hdl_lock, &irqL);
++ ptdls_sta->timer_flag = 1;
++ _exit_critical_bh(&ptdlsinfo->hdl_lock, &irqL);
++
++ ptdls_sta->tdls_sta_state &= (~TDLS_ALIVE_STATE);
++
++ DBG_871X("issue_tdls_dis_req to check alive\n");
++ issue_tdls_dis_req( padapter, ptdls_sta->hwaddr);
++ rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CKALV_PH1);
++ sta_update_last_rx_pkts(ptdls_sta);
++
++ if ( ptdls_sta->timer_flag == 2 )
++ rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_FREE_STA);
++ else
++ {
++ _enter_critical_bh(&ptdlsinfo->hdl_lock, &irqL);
++ ptdls_sta->timer_flag = 0;
++ _exit_critical_bh(&ptdlsinfo->hdl_lock, &irqL);
++ }
++
++}
++
++void _tdls_alive_timer_phase2_hdl(void *FunctionContext)
++{
++ _irqL irqL;
++ struct sta_info *ptdls_sta = (struct sta_info *)FunctionContext;
++ _adapter *padapter = ptdls_sta->padapter;
++ struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
++
++ _enter_critical_bh(&(ptdlsinfo->hdl_lock), &irqL);
++ ptdls_sta->timer_flag = 1;
++ _exit_critical_bh(&ptdlsinfo->hdl_lock, &irqL);
++
++ if( (ptdls_sta->tdls_sta_state & TDLS_ALIVE_STATE) &&
++ (sta_last_rx_pkts(ptdls_sta) + 3 <= sta_rx_pkts(ptdls_sta)) )
++ {
++ DBG_871X("TDLS STA ALIVE, ptdls_sta->sta_stats.last_rx_pkts:%llu, ptdls_sta->sta_stats.rx_pkts:%llu\n",
++ sta_last_rx_pkts(ptdls_sta), sta_rx_pkts(ptdls_sta));
++
++ ptdls_sta->alive_count = 0;
++ rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CKALV_PH2);
++ }
++ else
++ {
++ if( !(ptdls_sta->tdls_sta_state & TDLS_ALIVE_STATE) )
++ DBG_871X("TDLS STA TOO FAR\n");
++ if( !(sta_last_rx_pkts(ptdls_sta) + 3 <= sta_rx_pkts(ptdls_sta)))
++ DBG_871X("TDLS LINK WITH LOW TRAFFIC, ptdls_sta->sta_stats.last_rx_pkts:%llu, ptdls_sta->sta_stats.rx_pkts:%llu\n",
++ sta_last_rx_pkts(ptdls_sta), sta_rx_pkts(ptdls_sta));
++
++ ptdls_sta->alive_count++;
++ if( ptdls_sta->alive_count == TDLS_ALIVE_COUNT )
++ {
++ ptdls_sta->stat_code = _RSON_TDLS_TEAR_TOOFAR_;
++ issue_tdls_teardown(padapter, ptdls_sta->hwaddr);
++ }
++ else
++ {
++ rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CKALV_PH2);
++ }
++ }
++
++ if ( ptdls_sta->timer_flag == 2 )
++ rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_FREE_STA);
++ else
++ {
++ _enter_critical_bh(&(ptdlsinfo->hdl_lock), &irqL);
++ ptdls_sta->timer_flag = 0;
++ _exit_critical_bh(&ptdlsinfo->hdl_lock, &irqL);
++}
++
++}
++
++void init_tdls_alive_timer(_adapter *padapter, struct sta_info *psta)
++{
++ psta->padapter=padapter;
++ _init_timer(&psta->alive_timer1, padapter->pnetdev, _tdls_alive_timer_phase1_hdl, psta);
++ _init_timer(&psta->alive_timer2, padapter->pnetdev, _tdls_alive_timer_phase2_hdl, psta);
++}
++
++int update_sgi_tdls(_adapter *padapter, struct sta_info *psta)
++{
++ struct ht_priv *psta_ht = NULL;
++ psta_ht = &psta->htpriv;
++
++ if(psta_ht->ht_option)
++ {
++ return psta_ht->sgi;
++ }
++ else
++ return _FALSE;
++}
++
++u32 update_mask_tdls(_adapter *padapter, struct sta_info *psta)
++{
++ int i;
++ u8 rf_type, id;
++ unsigned char sta_band = 0;
++ unsigned char limit;
++ unsigned int tx_ra_bitmap=0;
++ struct ht_priv *psta_ht = NULL;
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ WLAN_BSSID_EX *pcur_network = (WLAN_BSSID_EX *)&pmlmepriv->cur_network.network;
++
++ psta_ht = &psta->htpriv;
++ //b/g mode ra_bitmap
++ for (i=0; i<sizeof(psta->bssrateset); i++)
++ {
++ if (psta->bssrateset[i])
++ tx_ra_bitmap |= rtw_get_bit_value_from_ieee_value(psta->bssrateset[i]&0x7f);
++ }
++
++ //n mode ra_bitmap
++ if(psta_ht->ht_option)
++ {
++ rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));
++ if(rf_type == RF_2T2R)
++ limit=16;// 2R
++ else
++ limit=8;// 1R
++
++ for (i=0; i<limit; i++) {
++ if (psta_ht->ht_cap.supp_mcs_set[i/8] & BIT(i%8))
++ tx_ra_bitmap |= BIT(i+12);
++ }
++ }
++
++ if ( pcur_network->Configuration.DSConfig > 14 ) {
++ // 5G band
++ if (tx_ra_bitmap & 0xffff000)
++ sta_band |= WIRELESS_11_5N | WIRELESS_11A;
++ else
++ sta_band |= WIRELESS_11A;
++ } else {
++ if (tx_ra_bitmap & 0xffff000)
++ sta_band |= WIRELESS_11_24N | WIRELESS_11G | WIRELESS_11B;
++ else if (tx_ra_bitmap & 0xff0)
++ sta_band |= WIRELESS_11G |WIRELESS_11B;
++ else
++ sta_band |= WIRELESS_11B;
++ }
++
++ id = networktype_to_raid(sta_band);
++ tx_ra_bitmap |= ((id<<28)&0xf0000000);
++ return tx_ra_bitmap;
++}
++
++#endif //CONFIG_TDLS
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/core/rtw_wlan_util.c linux-xbian-rpi/drivers/net/wireless/rtl8192cu/core/rtw_wlan_util.c
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/core/rtw_wlan_util.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/core/rtw_wlan_util.c 2015-07-28 01:20:58.305654202 +0200
+@@ -0,0 +1,2304 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#define _RTW_WLAN_UTIL_C_
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++#include <wifi.h>
++
++
++unsigned char ARTHEROS_OUI1[] = {0x00, 0x03, 0x7f};
++unsigned char ARTHEROS_OUI2[] = {0x00, 0x13, 0x74};
++
++unsigned char BROADCOM_OUI1[] = {0x00, 0x10, 0x18};
++unsigned char BROADCOM_OUI2[] = {0x00, 0x0a, 0xf7};
++unsigned char BROADCOM_OUI3[] = {0x00, 0x05, 0xb5};
++
++unsigned char CISCO_OUI[] = {0x00, 0x40, 0x96};
++unsigned char MARVELL_OUI[] = {0x00, 0x50, 0x43};
++unsigned char RALINK_OUI[] = {0x00, 0x0c, 0x43};
++unsigned char REALTEK_OUI[] = {0x00, 0xe0, 0x4c};
++unsigned char AIRGOCAP_OUI[] = {0x00, 0x0a, 0xf5};
++
++unsigned char REALTEK_96B_IE[] = {0x00, 0xe0, 0x4c, 0x02, 0x01, 0x20};
++
++extern unsigned char MCS_rate_2R[16];
++#ifdef CONFIG_DISABLE_MCS13TO15
++extern unsigned char MCS_rate_2R_MCS13TO15_OFF[16];
++#endif //CONFIG_DISABLE_MCS13TO15
++extern unsigned char MCS_rate_1R[16];
++extern unsigned char RTW_WPA_OUI[];
++extern unsigned char WPA_TKIP_CIPHER[4];
++extern unsigned char RSN_TKIP_CIPHER[4];
++
++#define R2T_PHY_DELAY (0)
++
++//#define WAIT_FOR_BCN_TO_MIN (3000)
++#define WAIT_FOR_BCN_TO_MIN (6000)
++#define WAIT_FOR_BCN_TO_MAX (20000)
++
++static u8 rtw_basic_rate_cck[4] = {
++ IEEE80211_CCK_RATE_1MB|IEEE80211_BASIC_RATE_MASK, IEEE80211_CCK_RATE_2MB|IEEE80211_BASIC_RATE_MASK,
++ IEEE80211_CCK_RATE_5MB|IEEE80211_BASIC_RATE_MASK, IEEE80211_CCK_RATE_11MB|IEEE80211_BASIC_RATE_MASK
++};
++
++static u8 rtw_basic_rate_ofdm[3] = {
++ IEEE80211_OFDM_RATE_6MB|IEEE80211_BASIC_RATE_MASK, IEEE80211_OFDM_RATE_12MB|IEEE80211_BASIC_RATE_MASK,
++ IEEE80211_OFDM_RATE_24MB|IEEE80211_BASIC_RATE_MASK
++};
++
++static u8 rtw_basic_rate_mix[7] = {
++ IEEE80211_CCK_RATE_1MB|IEEE80211_BASIC_RATE_MASK, IEEE80211_CCK_RATE_2MB|IEEE80211_BASIC_RATE_MASK,
++ IEEE80211_CCK_RATE_5MB|IEEE80211_BASIC_RATE_MASK, IEEE80211_CCK_RATE_11MB|IEEE80211_BASIC_RATE_MASK,
++ IEEE80211_OFDM_RATE_6MB|IEEE80211_BASIC_RATE_MASK, IEEE80211_OFDM_RATE_12MB|IEEE80211_BASIC_RATE_MASK,
++ IEEE80211_OFDM_RATE_24MB|IEEE80211_BASIC_RATE_MASK
++};
++
++
++int cckrates_included(unsigned char *rate, int ratelen)
++{
++ int i;
++
++ for(i = 0; i < ratelen; i++)
++ {
++ if ( (((rate[i]) & 0x7f) == 2) || (((rate[i]) & 0x7f) == 4) ||
++ (((rate[i]) & 0x7f) == 11) || (((rate[i]) & 0x7f) == 22) )
++ return _TRUE;
++ }
++
++ return _FALSE;
++
++}
++
++int cckratesonly_included(unsigned char *rate, int ratelen)
++{
++ int i;
++
++ for(i = 0; i < ratelen; i++)
++ {
++ if ( (((rate[i]) & 0x7f) != 2) && (((rate[i]) & 0x7f) != 4) &&
++ (((rate[i]) & 0x7f) != 11) && (((rate[i]) & 0x7f) != 22) )
++ return _FALSE;
++ }
++
++ return _TRUE;
++}
++
++unsigned char networktype_to_raid(unsigned char network_type)
++{
++ unsigned char raid;
++
++ switch(network_type)
++ {
++ case WIRELESS_11B:
++ raid = 6;
++ break;
++ case WIRELESS_11A:
++ case WIRELESS_11G:
++ raid = 5;
++ break;
++ case WIRELESS_11BG:
++ raid = 4;
++ break;
++ case WIRELESS_11_24N:
++ case WIRELESS_11_5N:
++ raid = 3;
++ break;
++ case WIRELESS_11A_5N:
++ case WIRELESS_11G_24N:
++ raid = 1;
++ break;
++ case WIRELESS_11BG_24N:
++ raid = 0;
++ break;
++ default:
++ raid = 4;
++ break;
++
++ }
++
++ return raid;
++
++}
++
++int judge_network_type(_adapter *padapter, unsigned char *rate, int ratelen)
++{
++ int network_type = 0;
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++
++
++ if(pmlmeext->cur_channel > 14)
++ {
++ if (pmlmeinfo->HT_enable)
++ {
++ network_type = WIRELESS_11_5N;
++ }
++
++ network_type |= WIRELESS_11A;
++ }
++ else
++ {
++ if (pmlmeinfo->HT_enable)
++ {
++ network_type = WIRELESS_11_24N;
++ }
++
++ if ((cckratesonly_included(rate, ratelen)) == _TRUE)
++ {
++ network_type |= WIRELESS_11B;
++ }
++ else if((cckrates_included(rate, ratelen)) == _TRUE)
++ {
++ network_type |= WIRELESS_11BG;
++ }
++ else
++ {
++ network_type |= WIRELESS_11G;
++ }
++ }
++
++ return network_type;
++}
++
++unsigned char ratetbl_val_2wifirate(unsigned char rate);
++unsigned char ratetbl_val_2wifirate(unsigned char rate)
++{
++ unsigned char val = 0;
++
++ switch (rate & 0x7f)
++ {
++ case 0:
++ val = IEEE80211_CCK_RATE_1MB;
++ break;
++
++ case 1:
++ val = IEEE80211_CCK_RATE_2MB;
++ break;
++
++ case 2:
++ val = IEEE80211_CCK_RATE_5MB;
++ break;
++
++ case 3:
++ val = IEEE80211_CCK_RATE_11MB;
++ break;
++
++ case 4:
++ val = IEEE80211_OFDM_RATE_6MB;
++ break;
++
++ case 5:
++ val = IEEE80211_OFDM_RATE_9MB;
++ break;
++
++ case 6:
++ val = IEEE80211_OFDM_RATE_12MB;
++ break;
++
++ case 7:
++ val = IEEE80211_OFDM_RATE_18MB;
++ break;
++
++ case 8:
++ val = IEEE80211_OFDM_RATE_24MB;
++ break;
++
++ case 9:
++ val = IEEE80211_OFDM_RATE_36MB;
++ break;
++
++ case 10:
++ val = IEEE80211_OFDM_RATE_48MB;
++ break;
++
++ case 11:
++ val = IEEE80211_OFDM_RATE_54MB;
++ break;
++
++ }
++
++ return val;
++
++}
++
++int is_basicrate(_adapter *padapter, unsigned char rate);
++int is_basicrate(_adapter *padapter, unsigned char rate)
++{
++ int i;
++ unsigned char val;
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++
++ for(i = 0; i < NumRates; i++)
++ {
++ val = pmlmeext->basicrate[i];
++
++ if ((val != 0xff) && (val != 0xfe))
++ {
++ if (rate == ratetbl_val_2wifirate(val))
++ {
++ return _TRUE;
++ }
++ }
++ }
++
++ return _FALSE;
++}
++
++unsigned int ratetbl2rateset(_adapter *padapter, unsigned char *rateset);
++unsigned int ratetbl2rateset(_adapter *padapter, unsigned char *rateset)
++{
++ int i;
++ unsigned char rate;
++ unsigned int len = 0;
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++
++ for (i = 0; i < NumRates; i++)
++ {
++ rate = pmlmeext->datarate[i];
++
++ switch (rate)
++ {
++ case 0xff:
++ return len;
++
++ case 0xfe:
++ continue;
++
++ default:
++ rate = ratetbl_val_2wifirate(rate);
++
++ if (is_basicrate(padapter, rate) == _TRUE)
++ {
++ rate |= IEEE80211_BASIC_RATE_MASK;
++ }
++
++ rateset[len] = rate;
++ len++;
++ break;
++ }
++ }
++ return len;
++}
++
++
++void get_rate_set(_adapter *padapter, unsigned char *pbssrate, int *bssrate_len)
++{
++ unsigned char supportedrates[NumRates];
++
++ _rtw_memset(supportedrates, 0, NumRates);
++ *bssrate_len = ratetbl2rateset(padapter, supportedrates);
++ _rtw_memcpy(pbssrate, supportedrates, *bssrate_len);
++}
++
++void UpdateBrateTbl(
++ IN PADAPTER Adapter,
++ IN u8 *mBratesOS
++)
++{
++ u8 i;
++ u8 rate;
++
++ // 1M, 2M, 5.5M, 11M, 6M, 12M, 24M are mandatory.
++ for(i=0;i<NDIS_802_11_LENGTH_RATES_EX;i++)
++ {
++ rate = mBratesOS[i] & 0x7f;
++ switch(rate)
++ {
++ case IEEE80211_CCK_RATE_1MB:
++ case IEEE80211_CCK_RATE_2MB:
++ case IEEE80211_CCK_RATE_5MB:
++ case IEEE80211_CCK_RATE_11MB:
++ case IEEE80211_OFDM_RATE_6MB:
++ case IEEE80211_OFDM_RATE_12MB:
++ case IEEE80211_OFDM_RATE_24MB:
++ mBratesOS[i] |= IEEE80211_BASIC_RATE_MASK;
++ break;
++ }
++ }
++
++}
++
++void UpdateBrateTblForSoftAP(u8 *bssrateset, u32 bssratelen)
++{
++ u8 i;
++ u8 rate;
++
++ for(i=0;i<bssratelen;i++)
++ {
++ rate = bssrateset[i] & 0x7f;
++ switch(rate)
++ {
++ case IEEE80211_CCK_RATE_1MB:
++ case IEEE80211_CCK_RATE_2MB:
++ case IEEE80211_CCK_RATE_5MB:
++ case IEEE80211_CCK_RATE_11MB:
++ bssrateset[i] |= IEEE80211_BASIC_RATE_MASK;
++ break;
++ }
++ }
++
++}
++
++void Save_DM_Func_Flag(_adapter *padapter)
++{
++ u8 bSaveFlag = _TRUE;
++
++#ifdef CONFIG_CONCURRENT_MODE
++ _adapter *pbuddy_adapter = padapter->pbuddy_adapter;
++ if(pbuddy_adapter)
++ rtw_hal_set_hwreg(pbuddy_adapter, HW_VAR_DM_FUNC_OP, (u8 *)(&bSaveFlag));
++#endif
++
++ rtw_hal_set_hwreg(padapter, HW_VAR_DM_FUNC_OP, (u8 *)(&bSaveFlag));
++
++}
++
++void Restore_DM_Func_Flag(_adapter *padapter)
++{
++ u8 bSaveFlag = _FALSE;
++#ifdef CONFIG_CONCURRENT_MODE
++ _adapter *pbuddy_adapter = padapter->pbuddy_adapter;
++ if(pbuddy_adapter)
++ rtw_hal_set_hwreg(pbuddy_adapter, HW_VAR_DM_FUNC_OP, (u8 *)(&bSaveFlag));
++#endif
++ rtw_hal_set_hwreg(padapter, HW_VAR_DM_FUNC_OP, (u8 *)(&bSaveFlag));
++}
++
++void Switch_DM_Func(_adapter *padapter, u8 mode, u8 enable)
++{
++#ifdef CONFIG_CONCURRENT_MODE
++ _adapter *pbuddy_adapter = padapter->pbuddy_adapter;
++#endif
++
++ if(enable == _TRUE)
++ {
++#ifdef CONFIG_CONCURRENT_MODE
++ if(pbuddy_adapter)
++ rtw_hal_set_hwreg(pbuddy_adapter, HW_VAR_DM_FUNC_SET, (u8 *)(&mode));
++#endif
++ rtw_hal_set_hwreg(padapter, HW_VAR_DM_FUNC_SET, (u8 *)(&mode));
++ }
++ else
++ {
++#ifdef CONFIG_CONCURRENT_MODE
++ if(pbuddy_adapter)
++ rtw_hal_set_hwreg(pbuddy_adapter, HW_VAR_DM_FUNC_CLR, (u8 *)(&mode));
++#endif
++ rtw_hal_set_hwreg(padapter, HW_VAR_DM_FUNC_CLR, (u8 *)(&mode));
++ }
++
++#if 0
++ u8 val8;
++
++ val8 = rtw_read8(padapter, FW_DYNAMIC_FUN_SWITCH);
++
++ if(enable == _TRUE)
++ {
++ rtw_write8(padapter, FW_DYNAMIC_FUN_SWITCH, (val8 | mode));
++ }
++ else
++ {
++ rtw_write8(padapter, FW_DYNAMIC_FUN_SWITCH, (val8 & mode));
++ }
++#endif
++
++}
++
++static void Set_NETYPE1_MSR(_adapter *padapter, u8 type)
++{
++ rtw_hal_set_hwreg(padapter, HW_VAR_MEDIA_STATUS1, (u8 *)(&type));
++}
++
++static void Set_NETYPE0_MSR(_adapter *padapter, u8 type)
++{
++ rtw_hal_set_hwreg(padapter, HW_VAR_MEDIA_STATUS, (u8 *)(&type));
++}
++
++void Set_MSR(_adapter *padapter, u8 type)
++{
++#ifdef CONFIG_CONCURRENT_MODE
++ if(padapter->iface_type == IFACE_PORT1)
++ {
++ Set_NETYPE1_MSR(padapter, type);
++ }
++ else
++#endif
++ {
++ Set_NETYPE0_MSR(padapter, type);
++ }
++}
++
++inline u8 rtw_get_oper_ch(_adapter *adapter)
++{
++ return adapter_to_dvobj(adapter)->oper_channel;
++}
++
++inline void rtw_set_oper_ch(_adapter *adapter, u8 ch)
++{
++ if (adapter_to_dvobj(adapter)->oper_channel != ch)
++ adapter_to_dvobj(adapter)->on_oper_ch_time = rtw_get_current_time();
++
++ adapter_to_dvobj(adapter)->oper_channel = ch;
++}
++
++inline u8 rtw_get_oper_bw(_adapter *adapter)
++{
++ return adapter_to_dvobj(adapter)->oper_bwmode;
++}
++
++inline void rtw_set_oper_bw(_adapter *adapter, u8 bw)
++{
++ adapter_to_dvobj(adapter)->oper_bwmode = bw;
++}
++
++inline u8 rtw_get_oper_choffset(_adapter *adapter)
++{
++ return adapter_to_dvobj(adapter)->oper_ch_offset;
++}
++
++inline void rtw_set_oper_choffset(_adapter *adapter, u8 offset)
++{
++ adapter_to_dvobj(adapter)->oper_ch_offset = offset;
++}
++
++inline u32 rtw_get_on_oper_ch_time(_adapter *adapter)
++{
++ return adapter_to_dvobj(adapter)->on_oper_ch_time;
++}
++
++inline u32 rtw_get_on_cur_ch_time(_adapter *adapter)
++{
++ if (adapter->mlmeextpriv.cur_channel == adapter_to_dvobj(adapter)->oper_channel)
++ return adapter_to_dvobj(adapter)->on_oper_ch_time;
++ else
++ return 0;
++}
++
++void SelectChannel(_adapter *padapter, unsigned char channel)
++{
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++
++#ifdef CONFIG_DUALMAC_CONCURRENT
++ //saved channel info
++ rtw_set_oper_ch(padapter, channel);
++ dc_SelectChannel(padapter, channel);
++#else //CONFIG_DUALMAC_CONCURRENT
++
++ _enter_critical_mutex(&(adapter_to_dvobj(padapter)->setch_mutex), NULL);
++
++ //saved channel info
++ rtw_set_oper_ch(padapter, channel);
++
++ rtw_hal_set_chan(padapter, channel);
++
++ _exit_critical_mutex(&(adapter_to_dvobj(padapter)->setch_mutex), NULL);
++
++#endif // CONFIG_DUALMAC_CONCURRENT
++}
++
++void SetBWMode(_adapter *padapter, unsigned short bwmode, unsigned char channel_offset)
++{
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++
++#ifdef CONFIG_DUALMAC_CONCURRENT
++ //saved bw info
++ rtw_set_oper_bw(padapter, bwmode);
++ rtw_set_oper_choffset(padapter, channel_offset);
++ dc_SetBWMode(padapter, bwmode, channel_offset);
++#else //CONFIG_DUALMAC_CONCURRENT
++
++ _enter_critical_mutex(&(adapter_to_dvobj(padapter)->setbw_mutex), NULL);
++
++ //saved bw info
++ rtw_set_oper_bw(padapter, bwmode);
++ rtw_set_oper_choffset(padapter, channel_offset);
++
++ rtw_hal_set_bwmode(padapter, (HT_CHANNEL_WIDTH)bwmode, channel_offset);
++
++ _exit_critical_mutex(&(adapter_to_dvobj(padapter)->setbw_mutex), NULL);
++
++#endif // CONFIG_DUALMAC_CONCURRENT
++}
++
++void set_channel_bwmode(_adapter *padapter, unsigned char channel, unsigned char channel_offset, unsigned short bwmode)
++{
++ u8 center_ch;
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++
++ if ( padapter->bNotifyChannelChange )
++ {
++ DBG_871X( "[%s] ch = %d, offset = %d, bwmode = %d\n", __FUNCTION__, channel, channel_offset, bwmode );
++ }
++
++ if((bwmode == HT_CHANNEL_WIDTH_20)||(channel_offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE))
++ {
++ //SelectChannel(padapter, channel);
++ center_ch = channel;
++ }
++ else
++ {
++ //switch to the proper channel
++ if (channel_offset == HAL_PRIME_CHNL_OFFSET_LOWER)
++ {
++ //SelectChannel(padapter, channel + 2);
++ center_ch = channel + 2;
++ }
++ else
++ {
++ //SelectChannel(padapter, channel - 2);
++ center_ch = channel - 2;
++ }
++ }
++
++ //set Channel , must be independant for correct co_ch value/
++#ifdef CONFIG_DUALMAC_CONCURRENT
++ //saved channel/bw info
++ rtw_set_oper_ch(padapter, channel);
++ rtw_set_oper_bw(padapter, bwmode);
++ rtw_set_oper_choffset(padapter, channel_offset);
++ dc_SelectChannel(padapter, center_ch);// set center channel
++#else //CONFIG_DUALMAC_CONCURRENT
++
++ _enter_critical_mutex(&(adapter_to_dvobj(padapter)->setch_mutex), NULL);
++
++ //saved channel/bw info
++ rtw_set_oper_ch(padapter, channel);
++ rtw_set_oper_bw(padapter, bwmode);
++ rtw_set_oper_choffset(padapter, channel_offset);
++
++ rtw_hal_set_chan(padapter, center_ch);
++
++ _exit_critical_mutex(&(adapter_to_dvobj(padapter)->setch_mutex), NULL);
++
++#endif // CONFIG_DUALMAC_CONCURRENT
++
++
++ //set BandWidth
++ SetBWMode(padapter, bwmode, channel_offset);
++
++}
++
++int get_bsstype(unsigned short capability)
++{
++ if (capability & BIT(0))
++ {
++ return WIFI_FW_AP_STATE;
++ }
++ else if (capability & BIT(1))
++ {
++ return WIFI_FW_ADHOC_STATE;
++ }
++ else
++ {
++ return 0;
++ }
++}
++
++__inline u8 *get_my_bssid(WLAN_BSSID_EX *pnetwork)
++{
++ return (pnetwork->MacAddress);
++}
++
++u16 get_beacon_interval(WLAN_BSSID_EX *bss)
++{
++ unsigned short val;
++ _rtw_memcpy((unsigned char *)&val, rtw_get_beacon_interval_from_ie(bss->IEs), 2);
++
++ return le16_to_cpu(val);
++
++}
++
++int is_client_associated_to_ap(_adapter *padapter)
++{
++ struct mlme_ext_priv *pmlmeext;
++ struct mlme_ext_info *pmlmeinfo;
++
++ if(!padapter)
++ return _FAIL;
++
++ pmlmeext = &padapter->mlmeextpriv;
++ pmlmeinfo = &(pmlmeext->mlmext_info);
++
++ if ((pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) && ((pmlmeinfo->state&0x03) == WIFI_FW_STATION_STATE))
++ {
++ return _TRUE;
++ }
++ else
++ {
++ return _FAIL;
++ }
++}
++
++int is_client_associated_to_ibss(_adapter *padapter)
++{
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++
++ if ((pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) && ((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE))
++ {
++ return _TRUE;
++ }
++ else
++ {
++ return _FAIL;
++ }
++}
++
++int is_IBSS_empty(_adapter *padapter)
++{
++ unsigned int i;
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++
++ for (i = IBSS_START_MAC_ID; i < NUM_STA; i++)
++ {
++ if (pmlmeinfo->FW_sta_info[i].status == 1)
++ {
++ return _FAIL;
++ }
++ }
++
++ return _TRUE;
++
++}
++
++unsigned int decide_wait_for_beacon_timeout(unsigned int bcn_interval)
++{
++ if ((bcn_interval << 2) < WAIT_FOR_BCN_TO_MIN)
++ {
++ return WAIT_FOR_BCN_TO_MIN;
++ }
++ else if ((bcn_interval << 2) > WAIT_FOR_BCN_TO_MAX)
++ {
++ return WAIT_FOR_BCN_TO_MAX;
++ }
++ else
++ {
++ return ((bcn_interval << 2));
++ }
++}
++
++void CAM_empty_entry(
++ PADAPTER Adapter,
++ u8 ucIndex
++)
++{
++ rtw_hal_set_hwreg(Adapter, HW_VAR_CAM_EMPTY_ENTRY, (u8 *)(&ucIndex));
++}
++
++void invalidate_cam_all(_adapter *padapter)
++{
++ rtw_hal_set_hwreg(padapter, HW_VAR_CAM_INVALID_ALL, 0);
++}
++#if 0
++static u32 _ReadCAM(_adapter *padapter ,u32 addr)
++{
++ u32 count = 0, cmd;
++ cmd = CAM_POLLINIG |addr ;
++ rtw_write32(padapter, RWCAM, cmd);
++
++ do{
++ if(0 == (rtw_read32(padapter,REG_CAMCMD) & CAM_POLLINIG)){
++ break;
++ }
++ }while(count++ < 100);
++
++ return rtw_read32(padapter,REG_CAMREAD);
++}
++void read_cam(_adapter *padapter ,u8 entry)
++{
++ u32 j,count = 0, addr, cmd;
++ addr = entry << 3;
++
++ printk("********* DUMP CAM Entry_#%02d***************\n",entry);
++ for (j = 0; j < 6; j++)
++ {
++ cmd = _ReadCAM(padapter ,addr+j);
++ printk("offset:0x%02x => 0x%08x \n",addr+j,cmd);
++ }
++ printk("*********************************\n");
++}
++#endif
++
++void write_cam(_adapter *padapter, u8 entry, u16 ctrl, u8 *mac, u8 *key)
++{
++ unsigned int i, val, addr;
++ //unsigned int cmd;
++ int j;
++ u32 cam_val[2];
++
++ addr = entry << 3;
++
++ for (j = 5; j >= 0; j--)
++ {
++ switch (j)
++ {
++ case 0:
++ val = (ctrl | (mac[0] << 16) | (mac[1] << 24) );
++ break;
++
++ case 1:
++ val = (mac[2] | ( mac[3] << 8) | (mac[4] << 16) | (mac[5] << 24));
++ break;
++
++ default:
++ i = (j - 2) << 2;
++ val = (key[i] | (key[i+1] << 8) | (key[i+2] << 16) | (key[i+3] << 24));
++ break;
++
++ }
++
++ cam_val[0] = val;
++ cam_val[1] = addr + (unsigned int)j;
++
++ rtw_hal_set_hwreg(padapter, HW_VAR_CAM_WRITE, (u8 *)cam_val);
++
++ //rtw_write32(padapter, WCAMI, val);
++
++ //cmd = CAM_POLLINIG | CAM_WRITE | (addr + j);
++ //rtw_write32(padapter, RWCAM, cmd);
++
++ //DBG_871X("%s=> cam write: %x, %x\n",__FUNCTION__, cmd, val);
++
++ }
++
++}
++
++void clear_cam_entry(_adapter *padapter, u8 entry)
++{
++#if 0
++ u32 addr, val=0;
++ u32 cam_val[2];
++
++ addr = entry << 3;
++
++
++ cam_val[0] = val;
++ cam_val[1] = addr + (unsigned int)0;
++
++ rtw_hal_set_hwreg(padapter, HW_VAR_CAM_WRITE, (u8 *)cam_val);
++
++
++
++ cam_val[0] = val;
++ cam_val[1] = addr + (unsigned int)1;
++
++ rtw_hal_set_hwreg(padapter, HW_VAR_CAM_WRITE, (u8 *)cam_val);
++#else
++
++ unsigned char null_sta[] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
++
++ unsigned char null_key[] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,0x00, 0x00, 0x00, 0x00,0x00, 0x00, 0x00, 0x00};
++
++ write_cam(padapter, entry, 0, null_sta, null_key);
++
++#endif
++}
++
++int allocate_fw_sta_entry(_adapter *padapter)
++{
++ unsigned int mac_id;
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++
++ for (mac_id = IBSS_START_MAC_ID; mac_id < NUM_STA; mac_id++)
++ {
++ if (pmlmeinfo->FW_sta_info[mac_id].status == 0)
++ {
++ pmlmeinfo->FW_sta_info[mac_id].status = 1;
++ pmlmeinfo->FW_sta_info[mac_id].retry = 0;
++ break;
++ }
++ }
++
++ return mac_id;
++}
++
++void flush_all_cam_entry(_adapter *padapter)
++{
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++
++#ifdef CONFIG_CONCURRENT_MODE
++
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++
++ //if(check_buddy_mlmeinfo_state(padapter, _HW_STATE_NOLINK_))
++ if(check_buddy_fwstate(padapter, _FW_LINKED) == _FALSE)
++ {
++ rtw_hal_set_hwreg(padapter, HW_VAR_CAM_INVALID_ALL, 0);
++ }
++ else
++ {
++ if(check_fwstate(pmlmepriv, WIFI_STATION_STATE))
++ {
++ struct sta_priv *pstapriv = &padapter->stapriv;
++ struct sta_info *psta;
++ u8 cam_id;//cam_entry
++
++ psta = rtw_get_stainfo(pstapriv, pmlmeinfo->network.MacAddress);
++ if(psta) {
++ if(psta->state & WIFI_AP_STATE)
++ {} //clear cam when ap free per sta_info
++ else {
++ if(psta->mac_id==2)
++ cam_id = 5;
++ else
++ cam_id = 4;
++ }
++ //clear_cam_entry(padapter, cam_id);
++ rtw_clearstakey_cmd(padapter, (u8*)psta, cam_id, _FALSE);
++ }
++ }
++ else if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE)
++ {
++ //clear cam when ap free per sta_info
++ }
++ }
++#else //CONFIG_CONCURRENT_MODE
++
++ rtw_hal_set_hwreg(padapter, HW_VAR_CAM_INVALID_ALL, 0);
++
++#endif //CONFIG_CONCURRENT_MODE
++
++ _rtw_memset((u8 *)(pmlmeinfo->FW_sta_info), 0, sizeof(pmlmeinfo->FW_sta_info));
++
++}
++
++#if defined(CONFIG_P2P) && defined(CONFIG_WFD)
++int WFD_info_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)
++{
++ struct registry_priv *pregpriv = &padapter->registrypriv;
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ struct wifidirect_info *pwdinfo;
++ u8 wfd_ie[ 128 ] = { 0x00 };
++ u32 wfd_ielen = 0;
++
++
++ pwdinfo = &padapter->wdinfo;
++ if ( rtw_get_wfd_ie( ( u8* ) pIE, pIE->Length, wfd_ie, &wfd_ielen ) )
++ {
++ u8 attr_content[ 10 ] = { 0x00 };
++ u32 attr_contentlen = 0;
++
++ printk( "[%s] Found WFD IE\n", __FUNCTION__ );
++ rtw_get_wfd_attr_content( wfd_ie, wfd_ielen, WFD_ATTR_DEVICE_INFO, attr_content, &attr_contentlen);
++ if ( attr_contentlen )
++ {
++ pwdinfo->wfd_info->peer_rtsp_ctrlport = RTW_GET_BE16( attr_content + 2 );
++ DBG_8192C( "[%s] Peer PORT NUM = %d\n", __FUNCTION__, pwdinfo->wfd_info->peer_rtsp_ctrlport );
++ return( _TRUE );
++ }
++ }
++ else
++ {
++ printk( "[%s] NO WFD IE\n", __FUNCTION__ );
++
++ }
++ return( _FAIL );
++}
++#endif
++
++int WMM_param_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)
++{
++ //struct registry_priv *pregpriv = &padapter->registrypriv;
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++
++ if(pmlmepriv->qospriv.qos_option==0)
++ {
++ pmlmeinfo->WMM_enable = 0;
++ return _FAIL;
++ }
++
++ pmlmeinfo->WMM_enable = 1;
++ _rtw_memcpy(&(pmlmeinfo->WMM_param), (pIE->data + 6), sizeof(struct WMM_para_element));
++ return _TRUE;
++
++ /*if (pregpriv->wifi_spec == 1)
++ {
++ if (pmlmeinfo->WMM_enable == 1)
++ {
++ //todo: compare the parameter set count & decide wheher to update or not
++ return _FAIL;
++ }
++ else
++ {
++ pmlmeinfo->WMM_enable = 1;
++ _rtw_rtw_memcpy(&(pmlmeinfo->WMM_param), (pIE->data + 6), sizeof(struct WMM_para_element));
++ return _TRUE;
++ }
++ }
++ else
++ {
++ pmlmeinfo->WMM_enable = 0;
++ return _FAIL;
++ }*/
++
++}
++
++void WMMOnAssocRsp(_adapter *padapter)
++{
++ u8 ACI, ACM, AIFS, ECWMin, ECWMax, aSifsTime;
++ u8 acm_mask;
++ u16 TXOP;
++ u32 acParm, i;
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++
++ if (pmlmeinfo->WMM_enable == 0)
++ {
++ padapter->mlmepriv.acm_mask = 0;
++ return;
++ }
++
++ acm_mask = 0;
++
++ if( pmlmeext->cur_wireless_mode == WIRELESS_11B)
++ aSifsTime = 10;
++ else
++ aSifsTime = 16;
++
++ for (i = 0; i < 4; i++)
++ {
++ ACI = (pmlmeinfo->WMM_param.ac_param[i].ACI_AIFSN >> 5) & 0x03;
++ ACM = (pmlmeinfo->WMM_param.ac_param[i].ACI_AIFSN >> 4) & 0x01;
++
++ //AIFS = AIFSN * slot time + SIFS - r2t phy delay
++ AIFS = (pmlmeinfo->WMM_param.ac_param[i].ACI_AIFSN & 0x0f) * pmlmeinfo->slotTime + aSifsTime;
++
++ ECWMin = (pmlmeinfo->WMM_param.ac_param[i].CW & 0x0f);
++ ECWMax = (pmlmeinfo->WMM_param.ac_param[i].CW & 0xf0) >> 4;
++ TXOP = le16_to_cpu(pmlmeinfo->WMM_param.ac_param[i].TXOP_limit);
++
++ acParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16);
++
++ switch (ACI)
++ {
++ case 0x0:
++ rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acParm));
++ acm_mask |= (ACM? BIT(1):0);
++ break;
++
++ case 0x1:
++ rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BK, (u8 *)(&acParm));
++ //acm_mask |= (ACM? BIT(0):0);
++ break;
++
++ case 0x2:
++ rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VI, (u8 *)(&acParm));
++ acm_mask |= (ACM? BIT(2):0);
++ break;
++
++ case 0x3:
++ rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VO, (u8 *)(&acParm));
++ acm_mask |= (ACM? BIT(3):0);
++ break;
++ }
++
++ DBG_871X("WMM(%x): %x, %x\n", ACI, ACM, acParm);
++ }
++
++ if(padapter->registrypriv.acm_method == 1)
++ rtw_hal_set_hwreg(padapter, HW_VAR_ACM_CTRL, (u8 *)(&acm_mask));
++ else
++ padapter->mlmepriv.acm_mask = acm_mask;
++
++ return;
++}
++
++static void bwmode_update_check(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)
++{
++ unsigned char new_bwmode;
++ unsigned char new_ch_offset;
++ struct HT_info_element *pHT_info;
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ struct registry_priv *pregistrypriv = &padapter->registrypriv;
++ struct ht_priv *phtpriv = &pmlmepriv->htpriv;
++ u8 cbw40_enable=0;
++
++ if(!pIE)
++ return;
++
++ if(phtpriv->ht_option == _FALSE) return;
++
++ if(pIE->Length > sizeof(struct HT_info_element))
++ return;
++
++ pHT_info = (struct HT_info_element *)pIE->data;
++
++ if (pmlmeext->cur_channel > 14) {
++ if (pregistrypriv->cbw40_enable & BIT(1))
++ cbw40_enable = 1;
++ } else {
++ if (pregistrypriv->cbw40_enable & BIT(0))
++ cbw40_enable = 1;
++ }
++
++ if((pHT_info->infos[0] & BIT(2)) && cbw40_enable )
++ {
++ new_bwmode = HT_CHANNEL_WIDTH_40;
++
++ switch (pHT_info->infos[0] & 0x3)
++ {
++ case 1:
++ new_ch_offset = HAL_PRIME_CHNL_OFFSET_LOWER;
++ break;
++
++ case 3:
++ new_ch_offset = HAL_PRIME_CHNL_OFFSET_UPPER;
++ break;
++
++ default:
++ new_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++ break;
++ }
++ }
++ else
++ {
++ new_bwmode = HT_CHANNEL_WIDTH_20;
++ new_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++ }
++
++
++ if((new_bwmode!= pmlmeext->cur_bwmode) || (new_ch_offset!=pmlmeext->cur_ch_offset))
++ {
++ pmlmeinfo->bwmode_updated = _TRUE;
++
++ pmlmeext->cur_bwmode = new_bwmode;
++ pmlmeext->cur_ch_offset = new_ch_offset;
++
++ //update HT info also
++ HT_info_handler(padapter, pIE);
++ }
++ else
++ {
++ pmlmeinfo->bwmode_updated = _FALSE;
++ }
++
++
++ if(_TRUE == pmlmeinfo->bwmode_updated)
++ {
++ struct sta_info *psta;
++ WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network);
++ struct sta_priv *pstapriv = &padapter->stapriv;
++
++ //set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode);
++
++
++ //update ap's stainfo
++ psta = rtw_get_stainfo(pstapriv, cur_network->MacAddress);
++ if(psta)
++ {
++ struct ht_priv *phtpriv_sta = &psta->htpriv;
++
++ if(phtpriv_sta->ht_option)
++ {
++ // bwmode
++ phtpriv_sta->bwmode = pmlmeext->cur_bwmode;
++ phtpriv_sta->ch_offset = pmlmeext->cur_ch_offset;
++ }
++ else
++ {
++ phtpriv_sta->bwmode = HT_CHANNEL_WIDTH_20;
++ phtpriv_sta->ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++ }
++
++ }
++
++ //pmlmeinfo->bwmode_updated = _FALSE;//bwmode_updated done, reset it!
++
++ }
++
++}
++
++void HT_caps_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)
++{
++ unsigned int i;
++ u8 rf_type;
++ u8 max_AMPDU_len, min_MPDU_spacing;
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct ht_priv *phtpriv = &pmlmepriv->htpriv;
++ struct registry_priv *pregistrypriv = &padapter->registrypriv;
++
++ if(pIE==NULL) return;
++
++ if(phtpriv->ht_option == _FALSE) return;
++
++ pmlmeinfo->HT_caps_enable = 1;
++
++ for (i = 0; i < (pIE->Length); i++)
++ {
++ if (i != 2)
++ {
++ // Commented by Albert 2010/07/12
++ // Got the endian issue here.
++ pmlmeinfo->HT_caps.u.HT_cap[i] &= (pIE->data[i]);
++ }
++ else
++ {
++ //modify from fw by Thomas 2010/11/17
++ if ((pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x3) > (pIE->data[i] & 0x3))
++ {
++ max_AMPDU_len = (pIE->data[i] & 0x3);
++ }
++ else
++ {
++ max_AMPDU_len = (pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x3);
++ }
++
++ if ((pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x1c) > (pIE->data[i] & 0x1c))
++ {
++ min_MPDU_spacing = (pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x1c);
++ }
++ else
++ {
++ min_MPDU_spacing = (pIE->data[i] & 0x1c);
++ }
++
++ pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para = max_AMPDU_len | min_MPDU_spacing;
++ }
++ }
++
++ // Commented by Albert 2010/07/12
++ // Have to handle the endian issue after copying.
++ // HT_ext_caps didn't be used yet.
++ pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info = le16_to_cpu( pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info );
++ pmlmeinfo->HT_caps.u.HT_cap_element.HT_ext_caps = le16_to_cpu( pmlmeinfo->HT_caps.u.HT_cap_element.HT_ext_caps );
++
++ rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));
++
++ //update the MCS rates
++ for (i = 0; i < 16; i++)
++ {
++ if((rf_type == RF_1T1R) || (rf_type == RF_1T2R))
++ {
++ pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate[i] &= MCS_rate_1R[i];
++ }
++ else
++ {
++ #ifdef CONFIG_DISABLE_MCS13TO15
++ if(pmlmeext->cur_bwmode == HT_CHANNEL_WIDTH_40 && (pregistrypriv->wifi_spec!=1))
++ pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate[i] &= MCS_rate_2R_MCS13TO15_OFF[i];
++ else
++ pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate[i] &= MCS_rate_2R[i];
++ #else
++ pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate[i] &= MCS_rate_2R[i];
++ #endif //CONFIG_DISABLE_MCS13TO15
++ }
++ #ifdef RTL8192C_RECONFIG_TO_1T1R
++ {
++ pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate[i] &= MCS_rate_1R[i];
++ }
++ #endif
++
++ if(pregistrypriv->special_rf_path)
++ pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate[i] &= MCS_rate_1R[i];
++
++ }
++
++ return;
++}
++
++void HT_info_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)
++{
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct ht_priv *phtpriv = &pmlmepriv->htpriv;
++
++ if(pIE==NULL) return;
++
++ if(phtpriv->ht_option == _FALSE) return;
++
++
++ if(pIE->Length > sizeof(struct HT_info_element))
++ return;
++
++ pmlmeinfo->HT_info_enable = 1;
++ _rtw_memcpy(&(pmlmeinfo->HT_info), pIE->data, pIE->Length);
++
++ return;
++}
++
++void HTOnAssocRsp(_adapter *padapter)
++{
++ unsigned char max_AMPDU_len;
++ unsigned char min_MPDU_spacing;
++ //struct registry_priv *pregpriv = &padapter->registrypriv;
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++
++ DBG_871X("%s\n", __FUNCTION__);
++
++ if ((pmlmeinfo->HT_info_enable) && (pmlmeinfo->HT_caps_enable))
++ {
++ pmlmeinfo->HT_enable = 1;
++ }
++ else
++ {
++ pmlmeinfo->HT_enable = 0;
++ //set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode);
++ return;
++ }
++
++ //handle A-MPDU parameter field
++ /*
++ AMPDU_para [1:0]:Max AMPDU Len => 0:8k , 1:16k, 2:32k, 3:64k
++ AMPDU_para [4:2]:Min MPDU Start Spacing
++ */
++ max_AMPDU_len = pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x03;
++
++ min_MPDU_spacing = (pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x1c) >> 2;
++
++ rtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_MIN_SPACE, (u8 *)(&min_MPDU_spacing));
++
++ rtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_FACTOR, (u8 *)(&max_AMPDU_len));
++
++#if 0 //move to rtw_update_ht_cap()
++ if ((pregpriv->cbw40_enable) &&
++ (pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info & BIT(1)) &&
++ (pmlmeinfo->HT_info.infos[0] & BIT(2)))
++ {
++ //switch to the 40M Hz mode accoring to the AP
++ pmlmeext->cur_bwmode = HT_CHANNEL_WIDTH_40;
++ switch ((pmlmeinfo->HT_info.infos[0] & 0x3))
++ {
++ case HT_EXTCHNL_OFFSET_UPPER:
++ pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_LOWER;
++ break;
++
++ case HT_EXTCHNL_OFFSET_LOWER:
++ pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_UPPER;
++ break;
++
++ default:
++ pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++ break;
++ }
++
++ //SelectChannel(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset);
++ }
++#endif
++
++ //set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode);
++
++#if 0 //move to rtw_update_ht_cap()
++ //
++ // Config SM Power Save setting
++ //
++ pmlmeinfo->SM_PS = (pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info & 0x0C) >> 2;
++ if(pmlmeinfo->SM_PS == WLAN_HT_CAP_SM_PS_STATIC)
++ {
++ /*u8 i;
++ //update the MCS rates
++ for (i = 0; i < 16; i++)
++ {
++ pmlmeinfo->HT_caps.HT_cap_element.MCS_rate[i] &= MCS_rate_1R[i];
++ }*/
++ DBG_871X("%s(): WLAN_HT_CAP_SM_PS_STATIC\n",__FUNCTION__);
++ }
++
++ //
++ // Config current HT Protection mode.
++ //
++ pmlmeinfo->HT_protection = pmlmeinfo->HT_info.infos[1] & 0x3;
++#endif
++
++}
++
++void ERP_IE_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)
++{
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++
++ if(pIE->Length>1)
++ return;
++
++ pmlmeinfo->ERP_enable = 1;
++ _rtw_memcpy(&(pmlmeinfo->ERP_IE), pIE->data, pIE->Length);
++}
++
++void VCS_update(_adapter *padapter, struct sta_info *psta)
++{
++ struct registry_priv *pregpriv = &padapter->registrypriv;
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++
++ switch (pregpriv->vrtl_carrier_sense)/* 0:off 1:on 2:auto */
++ {
++ case 0: //off
++ psta->rtsen = 0;
++ psta->cts2self = 0;
++ break;
++
++ case 1: //on
++ if (pregpriv->vcs_type == 1) /* 1:RTS/CTS 2:CTS to self */
++ {
++ psta->rtsen = 1;
++ psta->cts2self = 0;
++ }
++ else
++ {
++ psta->rtsen = 0;
++ psta->cts2self = 1;
++ }
++ break;
++
++ case 2: //auto
++ default:
++ if ((pmlmeinfo->ERP_enable) && (pmlmeinfo->ERP_IE & BIT(1)))
++ {
++ if (pregpriv->vcs_type == 1)
++ {
++ psta->rtsen = 1;
++ psta->cts2self = 0;
++ }
++ else
++ {
++ psta->rtsen = 0;
++ psta->cts2self = 1;
++ }
++ }
++ else
++ {
++ psta->rtsen = 0;
++ psta->cts2self = 0;
++ }
++ break;
++ }
++}
++
++#ifdef CONFIG_TDLS
++int check_ap_tdls_prohibited(u8 *pframe, u8 pkt_len)
++{
++ u8 tdls_prohibited_bit = 0x40; //bit(38); TDLS_prohibited
++
++ if(pkt_len < 5)
++ {
++ return _FALSE;
++ }
++
++ pframe += 4;
++ if( (*pframe) & tdls_prohibited_bit )
++ return _TRUE;
++
++ return _FALSE;
++}
++#endif //CONFIG_TDLS
++
++void update_beacon_info(_adapter *padapter, u8 *pframe, uint pkt_len, struct sta_info *psta)
++{
++ unsigned int i;
++ unsigned int len;
++ PNDIS_802_11_VARIABLE_IEs pIE;
++
++#ifdef CONFIG_TDLS
++ struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
++ u8 tdls_prohibited[] = { 0x00, 0x00, 0x00, 0x00, 0x10 }; //bit(38): TDLS_prohibited
++#endif //CONFIG_TDLS
++
++ len = pkt_len - (_BEACON_IE_OFFSET_ + WLAN_HDR_A3_LEN);
++
++ for (i = 0; i < len;)
++ {
++ pIE = (PNDIS_802_11_VARIABLE_IEs)(pframe + (_BEACON_IE_OFFSET_ + WLAN_HDR_A3_LEN) + i);
++
++ switch (pIE->ElementID)
++ {
++#if 0
++ case _VENDOR_SPECIFIC_IE_:
++ //todo: to update WMM paramter set while receiving beacon
++ if (_rtw_memcmp(pIE->data, WMM_PARA_OUI, 6)) //WMM
++ {
++ (WMM_param_handler(padapter, pIE))? WMMOnAssocRsp(padapter): 0;
++ }
++ break;
++#endif
++
++ case _HT_EXTRA_INFO_IE_: //HT info
++ //HT_info_handler(padapter, pIE);
++ bwmode_update_check(padapter, pIE);
++ break;
++
++ case _ERPINFO_IE_:
++ ERP_IE_handler(padapter, pIE);
++ VCS_update(padapter, psta);
++ break;
++
++#ifdef CONFIG_TDLS
++ case _EXT_CAP_IE_:
++ if( check_ap_tdls_prohibited(pIE->data, pIE->Length) == _TRUE )
++ ptdlsinfo->ap_prohibited = _TRUE;
++ break;
++#endif //CONFIG_TDLS
++ default:
++ break;
++ }
++
++ i += (pIE->Length + 2);
++ }
++}
++
++#ifdef CONFIG_DFS
++void process_csa_ie(_adapter *padapter, u8 *pframe, uint pkt_len)
++{
++ unsigned int i;
++ unsigned int len;
++ PNDIS_802_11_VARIABLE_IEs pIE;
++ u8 new_ch_no = 0;
++
++ len = pkt_len - (_BEACON_IE_OFFSET_ + WLAN_HDR_A3_LEN);
++
++ for (i = 0; i < len;)
++ {
++ pIE = (PNDIS_802_11_VARIABLE_IEs)(pframe + (_BEACON_IE_OFFSET_ + WLAN_HDR_A3_LEN) + i);
++
++ switch (pIE->ElementID)
++ {
++ case _CH_SWTICH_ANNOUNCE_:
++ _rtw_memcpy(&new_ch_no, pIE->data+1, 1);
++ rtw_set_csa_cmd(padapter, new_ch_no);
++ break;
++
++ default:
++ break;
++ }
++
++ i += (pIE->Length + 2);
++ }
++}
++#endif //CONFIG_DFS
++
++unsigned int is_ap_in_tkip(_adapter *padapter)
++{
++ u32 i;
++ PNDIS_802_11_VARIABLE_IEs pIE;
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network);
++
++ if (rtw_get_capability((WLAN_BSSID_EX *)cur_network) & WLAN_CAPABILITY_PRIVACY)
++ {
++ for (i = sizeof(NDIS_802_11_FIXED_IEs); i < pmlmeinfo->network.IELength;)
++ {
++ pIE = (PNDIS_802_11_VARIABLE_IEs)(pmlmeinfo->network.IEs + i);
++
++ switch (pIE->ElementID)
++ {
++ case _VENDOR_SPECIFIC_IE_:
++ if ((_rtw_memcmp(pIE->data, RTW_WPA_OUI, 4)) && (_rtw_memcmp((pIE->data + 12), WPA_TKIP_CIPHER, 4)))
++ {
++ return _TRUE;
++ }
++ break;
++
++ case _RSN_IE_2_:
++ if (_rtw_memcmp((pIE->data + 8), RSN_TKIP_CIPHER, 4))
++ {
++ return _TRUE;
++ }
++
++ default:
++ break;
++ }
++
++ i += (pIE->Length + 2);
++ }
++
++ return _FALSE;
++ }
++ else
++ {
++ return _FALSE;
++ }
++
++}
++
++int wifirate2_ratetbl_inx(unsigned char rate);
++int wifirate2_ratetbl_inx(unsigned char rate)
++{
++ int inx = 0;
++ rate = rate & 0x7f;
++
++ switch (rate)
++ {
++ case 54*2:
++ inx = 11;
++ break;
++
++ case 48*2:
++ inx = 10;
++ break;
++
++ case 36*2:
++ inx = 9;
++ break;
++
++ case 24*2:
++ inx = 8;
++ break;
++
++ case 18*2:
++ inx = 7;
++ break;
++
++ case 12*2:
++ inx = 6;
++ break;
++
++ case 9*2:
++ inx = 5;
++ break;
++
++ case 6*2:
++ inx = 4;
++ break;
++
++ case 11*2:
++ inx = 3;
++ break;
++ case 11:
++ inx = 2;
++ break;
++
++ case 2*2:
++ inx = 1;
++ break;
++
++ case 1*2:
++ inx = 0;
++ break;
++
++ }
++ return inx;
++}
++
++unsigned int update_basic_rate(unsigned char *ptn, unsigned int ptn_sz)
++{
++ unsigned int i, num_of_rate;
++ unsigned int mask = 0;
++
++ num_of_rate = (ptn_sz > NumRates)? NumRates: ptn_sz;
++
++ for (i = 0; i < num_of_rate; i++)
++ {
++ if ((*(ptn + i)) & 0x80)
++ {
++ mask |= 0x1 << wifirate2_ratetbl_inx(*(ptn + i));
++ }
++ }
++ return mask;
++}
++
++unsigned int update_supported_rate(unsigned char *ptn, unsigned int ptn_sz)
++{
++ unsigned int i, num_of_rate;
++ unsigned int mask = 0;
++
++ num_of_rate = (ptn_sz > NumRates)? NumRates: ptn_sz;
++
++ for (i = 0; i < num_of_rate; i++)
++ {
++ mask |= 0x1 << wifirate2_ratetbl_inx(*(ptn + i));
++ }
++
++ return mask;
++}
++
++unsigned int update_MSC_rate(struct HT_caps_element *pHT_caps)
++{
++ unsigned int mask = 0;
++
++ mask = ((pHT_caps->u.HT_cap_element.MCS_rate[0] << 12) | (pHT_caps->u.HT_cap_element.MCS_rate[1] << 20));
++
++ return mask;
++}
++
++int support_short_GI(_adapter *padapter, struct HT_caps_element *pHT_caps)
++{
++ unsigned char bit_offset;
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++
++ if (!(pmlmeinfo->HT_enable))
++ return _FAIL;
++
++ if ((pmlmeinfo->assoc_AP_vendor == ralinkAP))
++ return _FAIL;
++
++ bit_offset = (pmlmeext->cur_bwmode & HT_CHANNEL_WIDTH_40)? 6: 5;
++
++ if (pHT_caps->u.HT_cap_element.HT_caps_info & (0x1 << bit_offset))
++ {
++ return _SUCCESS;
++ }
++ else
++ {
++ return _FAIL;
++ }
++}
++
++unsigned char get_highest_rate_idx(u32 mask)
++{
++ int i;
++ unsigned char rate_idx=0;
++
++ for(i=27; i>=0; i--)
++ {
++ if(mask & BIT(i))
++ {
++ rate_idx = i;
++ break;
++ }
++ }
++
++ return rate_idx;
++}
++
++unsigned char get_highest_mcs_rate(struct HT_caps_element *pHT_caps);
++unsigned char get_highest_mcs_rate(struct HT_caps_element *pHT_caps)
++{
++ int i, mcs_rate;
++
++ mcs_rate = (pHT_caps->u.HT_cap_element.MCS_rate[0] | (pHT_caps->u.HT_cap_element.MCS_rate[1] << 8));
++
++ for (i = 15; i >= 0; i--)
++ {
++ if (mcs_rate & (0x1 << i))
++ {
++ break;
++ }
++ }
++
++ return i;
++}
++
++void Update_RA_Entry(_adapter *padapter, u32 mac_id)
++{
++ rtw_hal_update_ra_mask(padapter, mac_id);
++}
++
++void enable_rate_adaptive(_adapter *padapter, u32 mac_id);
++void enable_rate_adaptive(_adapter *padapter, u32 mac_id)
++{
++ Update_RA_Entry(padapter, mac_id);
++}
++
++void set_sta_rate(_adapter *padapter, struct sta_info *psta)
++{
++ //rate adaptive
++ enable_rate_adaptive(padapter, psta->mac_id);
++}
++
++// Update RRSR and Rate for USERATE
++void update_tx_basic_rate(_adapter *padapter, u8 wirelessmode)
++{
++ NDIS_802_11_RATES_EX supported_rates;
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++#ifdef CONFIG_P2P
++ struct wifidirect_info* pwdinfo = &padapter->wdinfo;
++
++ // Added by Albert 2011/03/22
++ // In the P2P mode, the driver should not support the b mode.
++ // So, the Tx packet shouldn't use the CCK rate
++ if(!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
++ return;
++#endif //CONFIG_P2P
++#ifdef CONFIG_INTEL_WIDI
++ if (padapter->mlmepriv.widi_state != INTEL_WIDI_STATE_NONE)
++ return;
++#endif //CONFIG_INTEL_WIDI
++
++ _rtw_memset(supported_rates, 0, NDIS_802_11_LENGTH_RATES_EX);
++
++ //clear B mod if current channel is in 5G band, avoid tx cck rate in 5G band.
++ if(pmlmeext->cur_channel > 14)
++ wirelessmode &= ~(WIRELESS_11B);
++
++ if ((wirelessmode & WIRELESS_11B) && (wirelessmode == WIRELESS_11B)) {
++ _rtw_memcpy(supported_rates, rtw_basic_rate_cck, 4);
++ } else if (wirelessmode & WIRELESS_11B) {
++ _rtw_memcpy(supported_rates, rtw_basic_rate_mix, 7);
++ } else {
++ _rtw_memcpy(supported_rates, rtw_basic_rate_ofdm, 3);
++ }
++
++ if (wirelessmode & WIRELESS_11B)
++ update_mgnt_tx_rate(padapter, IEEE80211_CCK_RATE_1MB);
++ else
++ update_mgnt_tx_rate(padapter, IEEE80211_OFDM_RATE_6MB);
++
++ rtw_hal_set_hwreg(padapter, HW_VAR_BASIC_RATE, supported_rates);
++}
++
++unsigned char check_assoc_AP(u8 *pframe, uint len)
++{
++ unsigned int i;
++ PNDIS_802_11_VARIABLE_IEs pIE;
++
++ for (i = sizeof(NDIS_802_11_FIXED_IEs); i < len;)
++ {
++ pIE = (PNDIS_802_11_VARIABLE_IEs)(pframe + i);
++
++ switch (pIE->ElementID)
++ {
++ case _VENDOR_SPECIFIC_IE_:
++ if ((_rtw_memcmp(pIE->data, ARTHEROS_OUI1, 3)) || (_rtw_memcmp(pIE->data, ARTHEROS_OUI2, 3)))
++ {
++ DBG_871X("link to Artheros AP\n");
++ return atherosAP;
++ }
++ else if ((_rtw_memcmp(pIE->data, BROADCOM_OUI1, 3))
++ || (_rtw_memcmp(pIE->data, BROADCOM_OUI2, 3))
++ || (_rtw_memcmp(pIE->data, BROADCOM_OUI2, 3)))
++ {
++ DBG_871X("link to Broadcom AP\n");
++ return broadcomAP;
++ }
++ else if (_rtw_memcmp(pIE->data, MARVELL_OUI, 3))
++ {
++ DBG_871X("link to Marvell AP\n");
++ return marvellAP;
++ }
++ else if (_rtw_memcmp(pIE->data, RALINK_OUI, 3))
++ {
++ DBG_871X("link to Ralink AP\n");
++ return ralinkAP;
++ }
++ else if (_rtw_memcmp(pIE->data, CISCO_OUI, 3))
++ {
++ DBG_871X("link to Cisco AP\n");
++ return ciscoAP;
++ }
++ else if (_rtw_memcmp(pIE->data, REALTEK_OUI, 3))
++ {
++ DBG_871X("link to Realtek 96B\n");
++ return realtekAP;
++ }
++ else if (_rtw_memcmp(pIE->data, AIRGOCAP_OUI,3))
++ {
++ DBG_871X("link to Airgo Cap\n");
++ return airgocapAP;
++ }
++ else
++ {
++ break;
++ }
++
++ default:
++ break;
++ }
++
++ i += (pIE->Length + 2);
++ }
++
++ DBG_871X("link to new AP\n");
++ return unknownAP;
++}
++
++void update_IOT_info(_adapter *padapter)
++{
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++
++ switch (pmlmeinfo->assoc_AP_vendor)
++ {
++ case marvellAP:
++ pmlmeinfo->turboMode_cts2self = 1;
++ pmlmeinfo->turboMode_rtsen = 0;
++ break;
++
++ case ralinkAP:
++ pmlmeinfo->turboMode_cts2self = 0;
++ pmlmeinfo->turboMode_rtsen = 1;
++ //disable high power
++ Switch_DM_Func(padapter, (~DYNAMIC_FUNC_HP), _FALSE);
++ break;
++ case realtekAP:
++ //rtw_write16(padapter, 0x4cc, 0xffff);
++ //rtw_write16(padapter, 0x546, 0x01c0);
++ //disable high power
++ Switch_DM_Func(padapter, (~DYNAMIC_FUNC_HP), _FALSE);
++ break;
++ default:
++ pmlmeinfo->turboMode_cts2self = 0;
++ pmlmeinfo->turboMode_rtsen = 1;
++ break;
++ }
++
++}
++
++void update_capinfo(PADAPTER Adapter, u16 updateCap)
++{
++ struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ BOOLEAN ShortPreamble;
++
++ // Check preamble mode, 2005.01.06, by rcnjko.
++ // Mark to update preamble value forever, 2008.03.18 by lanhsin
++ //if( pMgntInfo->RegPreambleMode == PREAMBLE_AUTO )
++ {
++
++ if(updateCap & cShortPreamble)
++ { // Short Preamble
++ if(pmlmeinfo->preamble_mode != PREAMBLE_SHORT) // PREAMBLE_LONG or PREAMBLE_AUTO
++ {
++ ShortPreamble = _TRUE;
++ pmlmeinfo->preamble_mode = PREAMBLE_SHORT;
++ rtw_hal_set_hwreg( Adapter, HW_VAR_ACK_PREAMBLE, (u8 *)&ShortPreamble );
++ }
++ }
++ else
++ { // Long Preamble
++ if(pmlmeinfo->preamble_mode != PREAMBLE_LONG) // PREAMBLE_SHORT or PREAMBLE_AUTO
++ {
++ ShortPreamble = _FALSE;
++ pmlmeinfo->preamble_mode = PREAMBLE_LONG;
++ rtw_hal_set_hwreg( Adapter, HW_VAR_ACK_PREAMBLE, (u8 *)&ShortPreamble );
++ }
++ }
++ }
++
++ if ( updateCap & cIBSS ) {
++ //Filen: See 802.11-2007 p.91
++ pmlmeinfo->slotTime = NON_SHORT_SLOT_TIME;
++ }
++ else
++ {
++ //Filen: See 802.11-2007 p.90
++ if( pmlmeext->cur_wireless_mode & (WIRELESS_11G | WIRELESS_11_24N))
++ {
++ if( (updateCap & cShortSlotTime) /* && (!(pMgntInfo->pHTInfo->RT2RT_HT_Mode & RT_HT_CAP_USE_LONG_PREAMBLE)) */)
++ { // Short Slot Time
++ if(pmlmeinfo->slotTime != SHORT_SLOT_TIME)
++ {
++ pmlmeinfo->slotTime = SHORT_SLOT_TIME;
++ }
++ }
++ else
++ { // Long Slot Time
++ if(pmlmeinfo->slotTime != NON_SHORT_SLOT_TIME)
++ {
++ pmlmeinfo->slotTime = NON_SHORT_SLOT_TIME;
++ }
++ }
++ }
++ else if( pmlmeext->cur_wireless_mode & (WIRELESS_11A | WIRELESS_11_5N))
++ {
++ pmlmeinfo->slotTime = SHORT_SLOT_TIME;
++ }
++ else
++ {
++ //B Mode
++ pmlmeinfo->slotTime = NON_SHORT_SLOT_TIME;
++ }
++ }
++
++ rtw_hal_set_hwreg( Adapter, HW_VAR_SLOT_TIME, &pmlmeinfo->slotTime );
++
++}
++
++void update_wireless_mode(_adapter *padapter)
++{
++ u8 init_rate=0;
++ int ratelen, network_type = 0;
++ u32 SIFS_Timer, mask;
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network);
++ unsigned char *rate = cur_network->SupportedRates;
++#ifdef CONFIG_CONCURRENT_MODE
++ _adapter *pbuddy_adapter = padapter->pbuddy_adapter;
++#endif //CONFIG_CONCURRENT_MODE
++
++ ratelen = rtw_get_rateset_len(cur_network->SupportedRates);
++
++ if ((pmlmeinfo->HT_info_enable) && (pmlmeinfo->HT_caps_enable))
++ {
++ pmlmeinfo->HT_enable = 1;
++ }
++
++ if(pmlmeext->cur_channel > 14)
++ {
++ if (pmlmeinfo->HT_enable)
++ {
++ network_type = WIRELESS_11_5N;
++ }
++
++ network_type |= WIRELESS_11A;
++ }
++ else
++ {
++ if (pmlmeinfo->HT_enable)
++ {
++ network_type = WIRELESS_11_24N;
++ }
++
++ if ((cckratesonly_included(rate, ratelen)) == _TRUE)
++ {
++ network_type |= WIRELESS_11B;
++ }
++ else if((cckrates_included(rate, ratelen)) == _TRUE)
++ {
++ network_type |= WIRELESS_11BG;
++ }
++ else
++ {
++ network_type |= WIRELESS_11G;
++ }
++ }
++
++ pmlmeext->cur_wireless_mode = network_type & padapter->registrypriv.wireless_mode;
++
++ //For STA mode, driver need to modify initial data rate, or MAC will use wrong tx rate.
++ //Modified by Thomas 2012-12-3
++ mask = update_supported_rate(cur_network->SupportedRates, ratelen);
++ init_rate = get_highest_rate_idx(mask)&0x3f;
++ rtw_hal_set_hwreg( padapter, HW_VAR_INIT_DATA_RATE, (u8 *)&init_rate);
++
++/*
++ if((pmlmeext->cur_wireless_mode==WIRELESS_11G) ||
++ (pmlmeext->cur_wireless_mode==WIRELESS_11BG))//WIRELESS_MODE_G)
++ SIFS_Timer = 0x0a0a;//CCK
++ else
++ SIFS_Timer = 0x0e0e;//pHalData->SifsTime; //OFDM
++*/
++
++ SIFS_Timer = 0x0a0a0808; //0x0808 -> for CCK, 0x0a0a -> for OFDM
++ //change this value if having IOT issues.
++
++ rtw_hal_set_hwreg( padapter, HW_VAR_RESP_SIFS, (u8 *)&SIFS_Timer);
++
++ if (pmlmeext->cur_wireless_mode & WIRELESS_11B)
++ update_mgnt_tx_rate(padapter, IEEE80211_CCK_RATE_1MB);
++ else
++ {
++ update_mgnt_tx_rate(padapter, IEEE80211_OFDM_RATE_6MB);
++#ifdef CONFIG_CONCURRENT_MODE
++ if(pbuddy_adapter && (pmlmeext->cur_wireless_mode & WIRELESS_11A))
++ update_mgnt_tx_rate(pbuddy_adapter, IEEE80211_OFDM_RATE_6MB);
++#endif //CONFIG_CONCURRENT_MODE
++ }
++}
++
++void fire_write_MAC_cmd(_adapter *padapter, unsigned int addr, unsigned int value);
++void fire_write_MAC_cmd(_adapter *padapter, unsigned int addr, unsigned int value)
++{
++#if 0
++ struct cmd_obj *ph2c;
++ struct reg_rw_parm *pwriteMacPara;
++ struct cmd_priv *pcmdpriv = &(padapter->cmdpriv);
++
++ if ((ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj))) == NULL)
++ {
++ return;
++ }
++
++ if ((pwriteMacPara = (struct reg_rw_parm*)rtw_malloc(sizeof(struct reg_rw_parm))) == NULL)
++ {
++ rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));
++ return;
++ }
++
++ pwriteMacPara->rw = 1;
++ pwriteMacPara->addr = addr;
++ pwriteMacPara->value = value;
++
++ init_h2fwcmd_w_parm_no_rsp(ph2c, pwriteMacPara, GEN_CMD_CODE(_Write_MACREG));
++ rtw_enqueue_cmd(pcmdpriv, ph2c);
++#endif
++}
++
++void update_bmc_sta_support_rate(_adapter *padapter, u32 mac_id)
++{
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++
++ if(pmlmeext->cur_wireless_mode & WIRELESS_11B)
++ {
++ // Only B, B/G, and B/G/N AP could use CCK rate
++ _rtw_memcpy((pmlmeinfo->FW_sta_info[mac_id].SupportedRates), rtw_basic_rate_cck, 4);
++ }
++ else
++ {
++ _rtw_memcpy((pmlmeinfo->FW_sta_info[mac_id].SupportedRates), rtw_basic_rate_ofdm, 3);
++ }
++}
++
++int update_sta_support_rate(_adapter *padapter, u8* pvar_ie, uint var_ie_len, int cam_idx)
++{
++ unsigned int ie_len;
++ PNDIS_802_11_VARIABLE_IEs pIE;
++ int supportRateNum = 0;
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++
++ pIE = (PNDIS_802_11_VARIABLE_IEs)rtw_get_ie(pvar_ie, _SUPPORTEDRATES_IE_, &ie_len, var_ie_len);
++ if (pIE == NULL)
++ {
++ return _FAIL;
++ }
++
++ _rtw_memcpy(pmlmeinfo->FW_sta_info[cam_idx].SupportedRates, pIE->data, ie_len);
++ supportRateNum = ie_len;
++
++ pIE = (PNDIS_802_11_VARIABLE_IEs)rtw_get_ie(pvar_ie, _EXT_SUPPORTEDRATES_IE_, &ie_len, var_ie_len);
++ if (pIE)
++ {
++ _rtw_memcpy((pmlmeinfo->FW_sta_info[cam_idx].SupportedRates + supportRateNum), pIE->data, ie_len);
++ }
++
++ return _SUCCESS;
++
++}
++
++void process_addba_req(_adapter *padapter, u8 *paddba_req, u8 *addr)
++{
++ struct sta_info *psta;
++ u16 tid, start_seq, param;
++ struct recv_reorder_ctrl *preorder_ctrl;
++ struct sta_priv *pstapriv = &padapter->stapriv;
++ struct ADDBA_request *preq = (struct ADDBA_request*)paddba_req;
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++
++ psta = rtw_get_stainfo(pstapriv, addr);
++
++ if(psta)
++ {
++ start_seq = le16_to_cpu(preq->BA_starting_seqctrl) >> 4;
++
++ param = le16_to_cpu(preq->BA_para_set);
++ tid = (param>>2)&0x0f;
++
++ preorder_ctrl = &psta->recvreorder_ctrl[tid];
++
++ #ifdef CONFIG_UPDATE_INDICATE_SEQ_WHILE_PROCESS_ADDBA_REQ
++ preorder_ctrl->indicate_seq = start_seq;
++ #ifdef DBG_RX_SEQ
++ DBG_871X("DBG_RX_SEQ %s:%d IndicateSeq: %d, start_seq: %d\n", __FUNCTION__, __LINE__,
++ preorder_ctrl->indicate_seq, start_seq);
++ #endif
++ #else
++ preorder_ctrl->indicate_seq = 0xffff;
++ #endif
++
++ preorder_ctrl->enable =(pmlmeinfo->bAcceptAddbaReq == _TRUE)? _TRUE :_FALSE;
++ }
++
++}
++
++void update_TSF(struct mlme_ext_priv *pmlmeext, u8 *pframe, uint len)
++{
++ u8* pIE;
++ u32 *pbuf;
++
++ pIE = pframe + sizeof(struct rtw_ieee80211_hdr_3addr);
++ pbuf = (u32*)pIE;
++
++ pmlmeext->TSFValue = le32_to_cpu(*(pbuf+1));
++
++ pmlmeext->TSFValue = pmlmeext->TSFValue << 32;
++
++ pmlmeext->TSFValue |= le32_to_cpu(*pbuf);
++}
++
++void correct_TSF(_adapter *padapter, struct mlme_ext_priv *pmlmeext)
++{
++ rtw_hal_set_hwreg(padapter, HW_VAR_CORRECT_TSF, 0);
++}
++
++void beacon_timing_control(_adapter *padapter)
++{
++ rtw_hal_bcn_related_reg_setting(padapter);
++}
++
++#if 0
++unsigned int setup_beacon_frame(_adapter *padapter, unsigned char *beacon_frame)
++{
++ unsigned short ATIMWindow;
++ unsigned char *pframe;
++ struct tx_desc *ptxdesc;
++ struct rtw_ieee80211_hdr *pwlanhdr;
++ unsigned short *fctrl;
++ unsigned int rate_len, len = 0;
++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network);
++ u8 bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
++
++ _rtw_memset(beacon_frame, 0, 256);
++
++ pframe = beacon_frame + TXDESC_SIZE;
++
++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++ fctrl = &(pwlanhdr->frame_ctl);
++ *(fctrl) = 0;
++
++ _rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(cur_network), ETH_ALEN);
++
++ SetFrameSubType(pframe, WIFI_BEACON);
++
++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
++ len = sizeof(struct rtw_ieee80211_hdr_3addr);
++
++ //timestamp will be inserted by hardware
++ pframe += 8;
++ len += 8;
++
++ // beacon interval: 2 bytes
++ _rtw_memcpy(pframe, (unsigned char *)(rtw_get_beacon_interval_from_ie(cur_network->IEs)), 2);
++
++ pframe += 2;
++ len += 2;
++
++ // capability info: 2 bytes
++ _rtw_memcpy(pframe, (unsigned char *)(rtw_get_capability_from_ie(cur_network->IEs)), 2);
++
++ pframe += 2;
++ len += 2;
++
++ // SSID
++ pframe = rtw_set_ie(pframe, _SSID_IE_, cur_network->Ssid.SsidLength, cur_network->Ssid.Ssid, &len);
++
++ // supported rates...
++ rate_len = rtw_get_rateset_len(cur_network->SupportedRates);
++ pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, ((rate_len > 8)? 8: rate_len), cur_network->SupportedRates, &len);
++
++ // DS parameter set
++ pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&(cur_network->Configuration.DSConfig), &len);
++
++ // IBSS Parameter Set...
++ //ATIMWindow = cur->Configuration.ATIMWindow;
++ ATIMWindow = 0;
++ pframe = rtw_set_ie(pframe, _IBSS_PARA_IE_, 2, (unsigned char *)(&ATIMWindow), &len);
++
++ //todo: ERP IE
++
++ // EXTERNDED SUPPORTED RATE
++ if (rate_len > 8)
++ {
++ pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (rate_len - 8), (cur_network->SupportedRates + 8), &len);
++ }
++
++ if ((len + TXDESC_SIZE) > 256)
++ {
++ //DBG_871X("marc: beacon frame too large\n");
++ return 0;
++ }
++
++ //fill the tx descriptor
++ ptxdesc = (struct tx_desc *)beacon_frame;
++
++ //offset 0
++ ptxdesc->txdw0 |= cpu_to_le32(len & 0x0000ffff);
++ ptxdesc->txdw0 |= cpu_to_le32(((TXDESC_SIZE + OFFSET_SZ) << OFFSET_SHT) & 0x00ff0000); //default = 32 bytes for TX Desc
++
++ //offset 4
++ ptxdesc->txdw1 |= cpu_to_le32((0x10 << QSEL_SHT) & 0x00001f00);
++
++ //offset 8
++ ptxdesc->txdw2 |= cpu_to_le32(BMC);
++ ptxdesc->txdw2 |= cpu_to_le32(BK);
++
++ //offset 16
++ ptxdesc->txdw4 = 0x80000000;
++
++ //offset 20
++ ptxdesc->txdw5 = 0x00000000; //1M
++
++ return (len + TXDESC_SIZE);
++}
++#endif
++
++static _adapter *pbuddy_padapter = NULL;
++
++int rtw_handle_dualmac(_adapter *adapter, bool init)
++{
++ int status = _SUCCESS;
++ struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++
++ if (!IS_HARDWARE_TYPE_8192D(adapter))
++ goto exit;
++
++ if (init) {
++ rtw_hal_get_def_var(adapter, HAL_DEF_DUAL_MAC_MODE, &dvobj->DualMacMode);
++ if (dvobj->DualMacMode == _TRUE) {
++ // temply disable IPS For 92D-VC
++ adapter->registrypriv.ips_mode = IPS_NONE;
++ }
++
++ /* For SMSP on 92DU-VC, driver do not probe another Interface. */
++ if ((dvobj->DualMacMode != _TRUE) && (dvobj->InterfaceNumber != 0)) {
++ DBG_871X("%s(): Do not init another Interface because SMSP\n",__FUNCTION__);
++ status = _FAIL;
++ goto exit;
++ }
++
++#ifndef CONFIG_CONCURRENT_MODE
++ if (dvobj->DualMacMode == _TRUE) {
++ if (pbuddy_padapter == NULL) {
++ pbuddy_padapter = adapter;
++ DBG_871X("%s(): pbuddy_padapter == NULL, Set pbuddy_padapter\n",__FUNCTION__);
++ } else {
++ adapter->pbuddy_adapter = pbuddy_padapter;
++ pbuddy_padapter->pbuddy_adapter = adapter;
++ // clear global value
++ pbuddy_padapter = NULL;
++ DBG_871X("%s(): pbuddy_padapter exist, Exchange Information\n",__FUNCTION__);
++ }
++ }
++
++#ifdef CONFIG_DUALMAC_CONCURRENT
++ if (dvobj->InterfaceNumber == 0) {
++ //set adapter_type/iface type
++ adapter->isprimary = _TRUE;
++ adapter->adapter_type = PRIMARY_ADAPTER;
++ adapter->iface_type = IFACE_PORT0;
++ DBG_871X("%s(): PRIMARY_ADAPTER\n",__FUNCTION__);
++ } else {
++ //set adapter_type/iface type
++ adapter->isprimary = _FALSE;
++ adapter->adapter_type = SECONDARY_ADAPTER;
++ adapter->iface_type = IFACE_PORT1;
++ DBG_871X("%s(): SECONDARY_ADAPTER\n",__FUNCTION__);
++ }
++#endif
++#endif
++ }else {
++ pbuddy_padapter = NULL;
++ }
++exit:
++ return status;
++}
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/core/rtw_xmit.c linux-xbian-rpi/drivers/net/wireless/rtl8192cu/core/rtw_xmit.c
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/core/rtw_xmit.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/core/rtw_xmit.c 2015-07-28 01:20:58.305654202 +0200
+@@ -0,0 +1,4155 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#define _RTW_XMIT_C_
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++#include <rtw_byteorder.h>
++#include <wifi.h>
++#include <osdep_intf.h>
++#include <circ_buf.h>
++#include <ip.h>
++
++#if defined (PLATFORM_LINUX) && defined (PLATFORM_WINDOWS)
++#error "Shall be Linux or Windows, but not both!\n"
++#endif
++
++#ifdef PLATFORM_WINDOWS
++#include <if_ether.h>
++#endif
++
++#ifdef CONFIG_USB_HCI
++#include <usb_ops.h>
++#endif
++
++
++static u8 P802_1H_OUI[P80211_OUI_LEN] = { 0x00, 0x00, 0xf8 };
++static u8 RFC1042_OUI[P80211_OUI_LEN] = { 0x00, 0x00, 0x00 };
++
++static void _init_txservq(struct tx_servq *ptxservq)
++{
++_func_enter_;
++ _rtw_init_listhead(&ptxservq->tx_pending);
++ _rtw_init_queue(&ptxservq->sta_pending);
++ ptxservq->qcnt = 0;
++_func_exit_;
++}
++
++
++void _rtw_init_sta_xmit_priv(struct sta_xmit_priv *psta_xmitpriv)
++{
++
++_func_enter_;
++
++ _rtw_memset((unsigned char *)psta_xmitpriv, 0, sizeof (struct sta_xmit_priv));
++
++ _rtw_spinlock_init(&psta_xmitpriv->lock);
++
++ //for(i = 0 ; i < MAX_NUMBLKS; i++)
++ // _init_txservq(&(psta_xmitpriv->blk_q[i]));
++
++ _init_txservq(&psta_xmitpriv->be_q);
++ _init_txservq(&psta_xmitpriv->bk_q);
++ _init_txservq(&psta_xmitpriv->vi_q);
++ _init_txservq(&psta_xmitpriv->vo_q);
++ _rtw_init_listhead(&psta_xmitpriv->legacy_dz);
++ _rtw_init_listhead(&psta_xmitpriv->apsd);
++
++_func_exit_;
++
++}
++
++s32 _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, _adapter *padapter)
++{
++ int i;
++ struct xmit_buf *pxmitbuf;
++ struct xmit_frame *pxframe;
++ sint res=_SUCCESS;
++
++_func_enter_;
++
++ // We don't need to memset padapter->XXX to zero, because adapter is allocated by rtw_zvmalloc().
++ //_rtw_memset((unsigned char *)pxmitpriv, 0, sizeof(struct xmit_priv));
++
++ _rtw_spinlock_init(&pxmitpriv->lock);
++ _rtw_spinlock_init(&pxmitpriv->lock_sctx);
++ _rtw_init_sema(&pxmitpriv->xmit_sema, 0);
++ _rtw_init_sema(&pxmitpriv->terminate_xmitthread_sema, 0);
++
++ /*
++ Please insert all the queue initializaiton using _rtw_init_queue below
++ */
++
++ pxmitpriv->adapter = padapter;
++
++ //for(i = 0 ; i < MAX_NUMBLKS; i++)
++ // _rtw_init_queue(&pxmitpriv->blk_strms[i]);
++
++ _rtw_init_queue(&pxmitpriv->be_pending);
++ _rtw_init_queue(&pxmitpriv->bk_pending);
++ _rtw_init_queue(&pxmitpriv->vi_pending);
++ _rtw_init_queue(&pxmitpriv->vo_pending);
++ _rtw_init_queue(&pxmitpriv->bm_pending);
++
++ //_rtw_init_queue(&pxmitpriv->legacy_dz_queue);
++ //_rtw_init_queue(&pxmitpriv->apsd_queue);
++
++ _rtw_init_queue(&pxmitpriv->free_xmit_queue);
++
++ /*
++ Please allocate memory with the sz = (struct xmit_frame) * NR_XMITFRAME,
++ and initialize free_xmit_frame below.
++ Please also apply free_txobj to link_up all the xmit_frames...
++ */
++
++ pxmitpriv->pallocated_frame_buf = rtw_zvmalloc(NR_XMITFRAME * sizeof(struct xmit_frame) + 4);
++
++ if (pxmitpriv->pallocated_frame_buf == NULL){
++ pxmitpriv->pxmit_frame_buf =NULL;
++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("alloc xmit_frame fail!\n"));
++ res= _FAIL;
++ goto exit;
++ }
++ pxmitpriv->pxmit_frame_buf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitpriv->pallocated_frame_buf), 4);
++ //pxmitpriv->pxmit_frame_buf = pxmitpriv->pallocated_frame_buf + 4 -
++ // ((SIZE_PTR) (pxmitpriv->pallocated_frame_buf) &3);
++
++ pxframe = (struct xmit_frame*) pxmitpriv->pxmit_frame_buf;
++
++ for (i = 0; i < NR_XMITFRAME; i++)
++ {
++ _rtw_init_listhead(&(pxframe->list));
++
++ pxframe->padapter = padapter;
++ pxframe->frame_tag = NULL_FRAMETAG;
++
++ pxframe->pkt = NULL;
++
++ pxframe->buf_addr = NULL;
++ pxframe->pxmitbuf = NULL;
++
++ rtw_list_insert_tail(&(pxframe->list), &(pxmitpriv->free_xmit_queue.queue));
++
++ pxframe++;
++ }
++
++ pxmitpriv->free_xmitframe_cnt = NR_XMITFRAME;
++
++ pxmitpriv->frag_len = MAX_FRAG_THRESHOLD;
++
++
++ //init xmit_buf
++ _rtw_init_queue(&pxmitpriv->free_xmitbuf_queue);
++ _rtw_init_queue(&pxmitpriv->pending_xmitbuf_queue);
++
++ pxmitpriv->pallocated_xmitbuf = rtw_zvmalloc(NR_XMITBUFF * sizeof(struct xmit_buf) + 4);
++
++ if (pxmitpriv->pallocated_xmitbuf == NULL){
++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("alloc xmit_buf fail!\n"));
++ res= _FAIL;
++ goto exit;
++ }
++
++ pxmitpriv->pxmitbuf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitpriv->pallocated_xmitbuf), 4);
++ //pxmitpriv->pxmitbuf = pxmitpriv->pallocated_xmitbuf + 4 -
++ // ((SIZE_PTR) (pxmitpriv->pallocated_xmitbuf) &3);
++
++ pxmitbuf = (struct xmit_buf*)pxmitpriv->pxmitbuf;
++
++ for (i = 0; i < NR_XMITBUFF; i++)
++ {
++ _rtw_init_listhead(&pxmitbuf->list);
++
++ pxmitbuf->priv_data = NULL;
++ pxmitbuf->padapter = padapter;
++ pxmitbuf->ext_tag = _FALSE;
++
++/*
++ pxmitbuf->pallocated_buf = rtw_zmalloc(MAX_XMITBUF_SZ + XMITBUF_ALIGN_SZ);
++ if (pxmitbuf->pallocated_buf == NULL)
++ {
++ res = _FAIL;
++ goto exit;
++ }
++
++ pxmitbuf->pbuf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitbuf->pallocated_buf), XMITBUF_ALIGN_SZ);
++ //pxmitbuf->pbuf = pxmitbuf->pallocated_buf + XMITBUF_ALIGN_SZ -((SIZE_PTR) (pxmitbuf->pallocated_buf) &(XMITBUF_ALIGN_SZ-1));
++*/
++
++ if((res=rtw_os_xmit_resource_alloc(padapter, pxmitbuf,(MAX_XMITBUF_SZ + XMITBUF_ALIGN_SZ))) == _FAIL) {
++ res= _FAIL;
++ goto exit;
++ }
++
++#ifdef CONFIG_SDIO_HCI
++ pxmitbuf->phead = pxmitbuf->pbuf;
++ pxmitbuf->pend = pxmitbuf->pbuf + MAX_XMITBUF_SZ;
++ pxmitbuf->len = 0;
++ pxmitbuf->pdata = pxmitbuf->ptail = pxmitbuf->phead;
++#endif
++
++ pxmitbuf->flags = XMIT_VO_QUEUE;
++
++ rtw_list_insert_tail(&pxmitbuf->list, &(pxmitpriv->free_xmitbuf_queue.queue));
++ #ifdef DBG_XMIT_BUF
++ pxmitbuf->no=i;
++ #endif
++
++ pxmitbuf++;
++
++ }
++
++ pxmitpriv->free_xmitbuf_cnt = NR_XMITBUFF;
++
++ /* init xframe_ext queue, the same count as extbuf */
++ _rtw_init_queue(&pxmitpriv->free_xframe_ext_queue);
++
++ pxmitpriv->xframe_ext_alloc_addr = rtw_zvmalloc(NR_XMIT_EXTBUFF * sizeof(struct xmit_frame) + 4);
++
++ if (pxmitpriv->xframe_ext_alloc_addr == NULL){
++ pxmitpriv->xframe_ext = NULL;
++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("alloc xframe_ext fail!\n"));
++ res= _FAIL;
++ goto exit;
++ }
++ pxmitpriv->xframe_ext = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitpriv->xframe_ext_alloc_addr), 4);
++ pxframe = (struct xmit_frame*)pxmitpriv->xframe_ext;
++
++ for (i = 0; i < NR_XMIT_EXTBUFF; i++) {
++ _rtw_init_listhead(&(pxframe->list));
++
++ pxframe->padapter = padapter;
++ pxframe->frame_tag = NULL_FRAMETAG;
++
++ pxframe->pkt = NULL;
++
++ pxframe->buf_addr = NULL;
++ pxframe->pxmitbuf = NULL;
++
++ pxframe->ext_tag = 1;
++
++ rtw_list_insert_tail(&(pxframe->list), &(pxmitpriv->free_xframe_ext_queue.queue));
++
++ pxframe++;
++ }
++ pxmitpriv->free_xframe_ext_cnt = NR_XMIT_EXTBUFF;
++
++ // Init xmit extension buff
++ _rtw_init_queue(&pxmitpriv->free_xmit_extbuf_queue);
++
++ pxmitpriv->pallocated_xmit_extbuf = rtw_zvmalloc(NR_XMIT_EXTBUFF * sizeof(struct xmit_buf) + 4);
++
++ if (pxmitpriv->pallocated_xmit_extbuf == NULL){
++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("alloc xmit_extbuf fail!\n"));
++ res= _FAIL;
++ goto exit;
++ }
++
++ pxmitpriv->pxmit_extbuf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitpriv->pallocated_xmit_extbuf), 4);
++
++ pxmitbuf = (struct xmit_buf*)pxmitpriv->pxmit_extbuf;
++
++ for (i = 0; i < NR_XMIT_EXTBUFF; i++)
++ {
++ _rtw_init_listhead(&pxmitbuf->list);
++
++ pxmitbuf->priv_data = NULL;
++ pxmitbuf->padapter = padapter;
++ pxmitbuf->ext_tag = _TRUE;
++
++/*
++ pxmitbuf->pallocated_buf = rtw_zmalloc(MAX_XMIT_EXTBUF_SZ);
++ if (pxmitbuf->pallocated_buf == NULL)
++ {
++ res = _FAIL;
++ goto exit;
++ }
++
++ pxmitbuf->pbuf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitbuf->pallocated_buf), 4);
++*/
++
++ if((res=rtw_os_xmit_resource_alloc(padapter, pxmitbuf,MAX_XMIT_EXTBUF_SZ + XMITBUF_ALIGN_SZ)) == _FAIL) {
++ res= _FAIL;
++ goto exit;
++ }
++
++#ifdef CONFIG_SDIO_HCI
++ pxmitbuf->phead = pxmitbuf->pbuf;
++ pxmitbuf->pend = pxmitbuf->pbuf + MAX_XMIT_EXTBUF_SZ;
++ pxmitbuf->len = 0;
++ pxmitbuf->pdata = pxmitbuf->ptail = pxmitbuf->phead;
++#endif
++
++ rtw_list_insert_tail(&pxmitbuf->list, &(pxmitpriv->free_xmit_extbuf_queue.queue));
++ #ifdef DBG_XMIT_BUF
++ pxmitbuf->no=i;
++ #endif
++ pxmitbuf++;
++
++ }
++
++ pxmitpriv->free_xmit_extbuf_cnt = NR_XMIT_EXTBUFF;
++
++ rtw_alloc_hwxmits(padapter);
++ rtw_init_hwxmits(pxmitpriv->hwxmits, pxmitpriv->hwxmit_entry);
++
++#ifdef CONFIG_USB_HCI
++ pxmitpriv->txirp_cnt=1;
++
++ _rtw_init_sema(&(pxmitpriv->tx_retevt), 0);
++
++ //per AC pending irp
++ pxmitpriv->beq_cnt = 0;
++ pxmitpriv->bkq_cnt = 0;
++ pxmitpriv->viq_cnt = 0;
++ pxmitpriv->voq_cnt = 0;
++#endif
++
++
++#ifdef CONFIG_XMIT_ACK
++ pxmitpriv->ack_tx = _FALSE;
++ _rtw_mutex_init(&pxmitpriv->ack_tx_mutex);
++ rtw_sctx_init(&pxmitpriv->ack_tx_ops, 0);
++#endif
++
++ rtw_hal_init_xmit_priv(padapter);
++
++exit:
++
++_func_exit_;
++
++ return res;
++}
++
++void rtw_mfree_xmit_priv_lock (struct xmit_priv *pxmitpriv);
++void rtw_mfree_xmit_priv_lock (struct xmit_priv *pxmitpriv)
++{
++ _rtw_spinlock_free(&pxmitpriv->lock);
++ _rtw_free_sema(&pxmitpriv->xmit_sema);
++ _rtw_free_sema(&pxmitpriv->terminate_xmitthread_sema);
++
++ _rtw_spinlock_free(&pxmitpriv->be_pending.lock);
++ _rtw_spinlock_free(&pxmitpriv->bk_pending.lock);
++ _rtw_spinlock_free(&pxmitpriv->vi_pending.lock);
++ _rtw_spinlock_free(&pxmitpriv->vo_pending.lock);
++ _rtw_spinlock_free(&pxmitpriv->bm_pending.lock);
++
++ //_rtw_spinlock_free(&pxmitpriv->legacy_dz_queue.lock);
++ //_rtw_spinlock_free(&pxmitpriv->apsd_queue.lock);
++
++ _rtw_spinlock_free(&pxmitpriv->free_xmit_queue.lock);
++ _rtw_spinlock_free(&pxmitpriv->free_xmitbuf_queue.lock);
++ _rtw_spinlock_free(&pxmitpriv->pending_xmitbuf_queue.lock);
++}
++
++
++void _rtw_free_xmit_priv (struct xmit_priv *pxmitpriv)
++{
++ int i;
++ _adapter *padapter = pxmitpriv->adapter;
++ struct xmit_frame *pxmitframe = (struct xmit_frame*) pxmitpriv->pxmit_frame_buf;
++ struct xmit_buf *pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmitbuf;
++
++ _func_enter_;
++
++ rtw_hal_free_xmit_priv(padapter);
++
++ rtw_mfree_xmit_priv_lock(pxmitpriv);
++
++ if(pxmitpriv->pxmit_frame_buf==NULL)
++ goto out;
++
++ for(i=0; i<NR_XMITFRAME; i++)
++ {
++ rtw_os_xmit_complete(padapter, pxmitframe);
++
++ pxmitframe++;
++ }
++
++ for(i=0; i<NR_XMITBUFF; i++)
++ {
++ rtw_os_xmit_resource_free(padapter, pxmitbuf,(MAX_XMITBUF_SZ + XMITBUF_ALIGN_SZ));
++
++ //if(pxmitbuf->pallocated_buf)
++ // rtw_mfree(pxmitbuf->pallocated_buf, MAX_XMITBUF_SZ + XMITBUF_ALIGN_SZ);
++
++ pxmitbuf++;
++ }
++
++ if(pxmitpriv->pallocated_frame_buf) {
++ rtw_vmfree(pxmitpriv->pallocated_frame_buf, NR_XMITFRAME * sizeof(struct xmit_frame) + 4);
++ }
++
++
++ if(pxmitpriv->pallocated_xmitbuf) {
++ rtw_vmfree(pxmitpriv->pallocated_xmitbuf, NR_XMITBUFF * sizeof(struct xmit_buf) + 4);
++ }
++
++ /* free xframe_ext queue, the same count as extbuf */
++ if ((pxmitframe = (struct xmit_frame*)pxmitpriv->xframe_ext)) {
++ for (i=0; i<NR_XMIT_EXTBUFF; i++) {
++ rtw_os_xmit_complete(padapter, pxmitframe);
++ pxmitframe++;
++ }
++ }
++ if (pxmitpriv->xframe_ext_alloc_addr)
++ rtw_vmfree(pxmitpriv->xframe_ext_alloc_addr, NR_XMIT_EXTBUFF * sizeof(struct xmit_frame) + 4);
++ _rtw_spinlock_free(&pxmitpriv->free_xframe_ext_queue.lock);
++
++ // free xmit extension buff
++ _rtw_spinlock_free(&pxmitpriv->free_xmit_extbuf_queue.lock);
++
++ pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmit_extbuf;
++ for(i=0; i<NR_XMIT_EXTBUFF; i++)
++ {
++ rtw_os_xmit_resource_free(padapter, pxmitbuf,(MAX_XMIT_EXTBUF_SZ + XMITBUF_ALIGN_SZ));
++
++ //if(pxmitbuf->pallocated_buf)
++ // rtw_mfree(pxmitbuf->pallocated_buf, MAX_XMIT_EXTBUF_SZ);
++
++ pxmitbuf++;
++ }
++
++ if(pxmitpriv->pallocated_xmit_extbuf) {
++ rtw_vmfree(pxmitpriv->pallocated_xmit_extbuf, NR_XMIT_EXTBUFF * sizeof(struct xmit_buf) + 4);
++ }
++
++ rtw_free_hwxmits(padapter);
++
++#ifdef CONFIG_XMIT_ACK
++ _rtw_mutex_free(&pxmitpriv->ack_tx_mutex);
++#endif
++
++out:
++
++_func_exit_;
++
++}
++
++static void update_attrib_vcs_info(_adapter *padapter, struct xmit_frame *pxmitframe)
++{
++ u32 sz;
++ struct pkt_attrib *pattrib = &pxmitframe->attrib;
++ struct sta_info *psta = pattrib->psta;
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++
++ if(pattrib->psta)
++ {
++ psta = pattrib->psta;
++ }
++ else
++ {
++ DBG_871X("%s, call rtw_get_stainfo()\n", __func__);
++ psta=rtw_get_stainfo(&padapter->stapriv ,&pattrib->ra[0] );
++ }
++
++ if(psta==NULL)
++ {
++ DBG_871X("%s, psta==NUL\n", __func__);
++ return;
++ }
++
++ if(!(psta->state &_FW_LINKED))
++ {
++ DBG_871X("%s, psta->state(0x%x) != _FW_LINKED\n", __func__, psta->state);
++ return;
++ }
++
++ if (pattrib->nr_frags != 1)
++ {
++ sz = padapter->xmitpriv.frag_len;
++ }
++ else //no frag
++ {
++ sz = pattrib->last_txcmdsz;
++ }
++
++ // (1) RTS_Threshold is compared to the MPDU, not MSDU.
++ // (2) If there are more than one frag in this MSDU, only the first frag uses protection frame.
++ // Other fragments are protected by previous fragment.
++ // So we only need to check the length of first fragment.
++ if(pmlmeext->cur_wireless_mode < WIRELESS_11_24N || padapter->registrypriv.wifi_spec)
++ {
++ if(sz > padapter->registrypriv.rts_thresh)
++ {
++ pattrib->vcs_mode = RTS_CTS;
++ }
++ else
++ {
++ if(psta->rtsen)
++ pattrib->vcs_mode = RTS_CTS;
++ else if(psta->cts2self)
++ pattrib->vcs_mode = CTS_TO_SELF;
++ else
++ pattrib->vcs_mode = NONE_VCS;
++ }
++ }
++ else
++ {
++ while (_TRUE)
++ {
++#if 0 //Todo
++ //check IOT action
++ if(pHTInfo->IOTAction & HT_IOT_ACT_FORCED_CTS2SELF)
++ {
++ pattrib->vcs_mode = CTS_TO_SELF;
++ pattrib->rts_rate = MGN_24M;
++ break;
++ }
++ else if(pHTInfo->IOTAction & (HT_IOT_ACT_FORCED_RTS|HT_IOT_ACT_PURE_N_MODE))
++ {
++ pattrib->vcs_mode = RTS_CTS;
++ pattrib->rts_rate = MGN_24M;
++ break;
++ }
++#endif
++
++ //IOT action
++ if((pmlmeinfo->assoc_AP_vendor == atherosAP) && (pattrib->ampdu_en==_TRUE) &&
++ (padapter->securitypriv.dot11PrivacyAlgrthm == _AES_ ))
++ {
++ pattrib->vcs_mode = CTS_TO_SELF;
++ break;
++ }
++
++
++ //check ERP protection
++ if(psta->rtsen || psta->cts2self)
++ {
++ if(psta->rtsen)
++ pattrib->vcs_mode = RTS_CTS;
++ else if(psta->cts2self)
++ pattrib->vcs_mode = CTS_TO_SELF;
++
++ break;
++ }
++
++ //check HT op mode
++ if(pattrib->ht_en)
++ {
++ u8 HTOpMode = pmlmeinfo->HT_protection;
++ if((pmlmeext->cur_bwmode && (HTOpMode == 2 || HTOpMode == 3)) ||
++ (!pmlmeext->cur_bwmode && HTOpMode == 3) )
++ {
++ pattrib->vcs_mode = RTS_CTS;
++ break;
++ }
++ }
++
++ //check rts
++ if(sz > padapter->registrypriv.rts_thresh)
++ {
++ pattrib->vcs_mode = RTS_CTS;
++ break;
++ }
++
++ //to do list: check MIMO power save condition.
++
++ //check AMPDU aggregation for TXOP
++ if(pattrib->ampdu_en==_TRUE)
++ {
++ pattrib->vcs_mode = RTS_CTS;
++ break;
++ }
++
++ pattrib->vcs_mode = NONE_VCS;
++ break;
++ }
++ }
++}
++
++static void update_attrib_phy_info(struct pkt_attrib *pattrib, struct sta_info *psta)
++{
++ /*if(psta->rtsen)
++ pattrib->vcs_mode = RTS_CTS;
++ else if(psta->cts2self)
++ pattrib->vcs_mode = CTS_TO_SELF;
++ else
++ pattrib->vcs_mode = NONE_VCS;*/
++
++ pattrib->mdata = 0;
++ pattrib->eosp = 0;
++ pattrib->triggered=0;
++
++ //qos_en, ht_en, init rate, ,bw, ch_offset, sgi
++ pattrib->qos_en = psta->qos_option;
++ pattrib->ht_en = psta->htpriv.ht_option;
++ pattrib->raid = psta->raid;
++ pattrib->bwmode = psta->htpriv.bwmode;
++ pattrib->ch_offset = psta->htpriv.ch_offset;
++ pattrib->sgi= psta->htpriv.sgi;
++ pattrib->ampdu_en = _FALSE;
++
++ //if(pattrib->ht_en && psta->htpriv.ampdu_enable)
++ //{
++ // if(psta->htpriv.agg_enable_bitmap & BIT(pattrib->priority))
++ // pattrib->ampdu_en = _TRUE;
++ //}
++
++
++ pattrib->retry_ctrl = _FALSE;
++
++}
++
++u8 qos_acm(u8 acm_mask, u8 priority)
++{
++ u8 change_priority = priority;
++
++ switch (priority)
++ {
++ case 0:
++ case 3:
++ if(acm_mask & BIT(1))
++ change_priority = 1;
++ break;
++ case 1:
++ case 2:
++ break;
++ case 4:
++ case 5:
++ if(acm_mask & BIT(2))
++ change_priority = 0;
++ break;
++ case 6:
++ case 7:
++ if(acm_mask & BIT(3))
++ change_priority = 5;
++ break;
++ default:
++ DBG_871X("qos_acm(): invalid pattrib->priority: %d!!!\n", priority);
++ break;
++ }
++
++ return change_priority;
++}
++
++static void set_qos(struct pkt_file *ppktfile, struct pkt_attrib *pattrib)
++{
++ struct ethhdr etherhdr;
++ struct iphdr ip_hdr;
++ s32 UserPriority = 0;
++
++
++ _rtw_open_pktfile(ppktfile->pkt, ppktfile);
++ _rtw_pktfile_read(ppktfile, (unsigned char*)&etherhdr, ETH_HLEN);
++
++ // get UserPriority from IP hdr
++ if (pattrib->ether_type == 0x0800) {
++ _rtw_pktfile_read(ppktfile, (u8*)&ip_hdr, sizeof(ip_hdr));
++// UserPriority = (ntohs(ip_hdr.tos) >> 5) & 0x3;
++ UserPriority = ip_hdr.tos >> 5;
++ } else if (pattrib->ether_type == 0x888e) {
++ // "When priority processing of data frames is supported,
++ // a STA's SME should send EAPOL-Key frames at the highest priority."
++ UserPriority = 7;
++ }
++
++ pattrib->priority = UserPriority;
++ pattrib->hdrlen = WLAN_HDR_A3_QOS_LEN;
++ pattrib->subtype = WIFI_QOS_DATA_TYPE;
++}
++
++static s32 update_attrib(_adapter *padapter, _pkt *pkt, struct pkt_attrib *pattrib)
++{
++ uint i;
++ struct pkt_file pktfile;
++ struct sta_info *psta = NULL;
++ struct ethhdr etherhdr;
++
++ sint bmcast;
++ struct sta_priv *pstapriv = &padapter->stapriv;
++ struct security_priv *psecuritypriv = &padapter->securitypriv;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct qos_priv *pqospriv= &pmlmepriv->qospriv;
++ sint res = _SUCCESS;
++
++ _func_enter_;
++
++ _rtw_open_pktfile(pkt, &pktfile);
++ i = _rtw_pktfile_read(&pktfile, (u8*)&etherhdr, ETH_HLEN);
++
++ pattrib->ether_type = ntohs(etherhdr.h_proto);
++
++
++ _rtw_memcpy(pattrib->dst, &etherhdr.h_dest, ETH_ALEN);
++ _rtw_memcpy(pattrib->src, &etherhdr.h_source, ETH_ALEN);
++
++ pattrib->pctrl = 0;
++
++ if ((check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) ||
++ (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)) {
++ _rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN);
++ _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
++ }
++ else if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) {
++ _rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN);
++ _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
++ }
++ else if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) {
++ _rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN);
++ _rtw_memcpy(pattrib->ta, get_bssid(pmlmepriv), ETH_ALEN);
++ }
++
++ pattrib->pktlen = pktfile.pkt_len;
++
++ if (ETH_P_IP == pattrib->ether_type)
++ {
++ // The following is for DHCP and ARP packet, we use cck1M to tx these packets and let LPS awake some time
++ // to prevent DHCP protocol fail
++ u8 tmp[24];
++ _rtw_pktfile_read(&pktfile, &tmp[0], 24);
++ pattrib->dhcp_pkt = 0;
++ if (pktfile.pkt_len > 282) {//MINIMUM_DHCP_PACKET_SIZE) {
++ if (ETH_P_IP == pattrib->ether_type) {// IP header
++ if (((tmp[21] == 68) && (tmp[23] == 67)) ||
++ ((tmp[21] == 67) && (tmp[23] == 68))) {
++ // 68 : UDP BOOTP client
++ // 67 : UDP BOOTP server
++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("======================update_attrib: get DHCP Packet \n"));
++ // Use low rate to send DHCP packet.
++ //if(pMgntInfo->IOTAction & HT_IOT_ACT_WA_IOT_Broadcom)
++ //{
++ // tcb_desc->DataRate = MgntQuery_TxRateExcludeCCKRates(ieee);//0xc;//ofdm 6m
++ // tcb_desc->bTxDisableRateFallBack = false;
++ //}
++ //else
++ // pTcb->DataRate = Adapter->MgntInfo.LowestBasicRate;
++ //RTPRINT(FDM, WA_IOT, ("DHCP TranslateHeader(), pTcb->DataRate = 0x%x\n", pTcb->DataRate));
++ pattrib->dhcp_pkt = 1;
++ }
++ }
++ }
++ }
++
++ if ( (pattrib->ether_type == 0x888e) || (pattrib->dhcp_pkt == 1) )
++ {
++ rtw_set_scan_deny(padapter, 3000);
++ }
++
++#ifdef CONFIG_LPS
++ // If EAPOL , ARP , OR DHCP packet, driver must be in active mode.
++ if ( (pattrib->ether_type == 0x0806) || (pattrib->ether_type == 0x888e) || (pattrib->dhcp_pkt == 1) )
++ {
++ rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_SPECIAL_PACKET, 1);
++ }
++#endif
++
++ bmcast = IS_MCAST(pattrib->ra);
++
++ // get sta_info
++ if (bmcast) {
++ psta = rtw_get_bcmc_stainfo(padapter);
++ } else {
++ psta = rtw_get_stainfo(pstapriv, pattrib->ra);
++ if (psta == NULL) { // if we cannot get psta => drrp the pkt
++ RT_TRACE(_module_rtl871x_xmit_c_, _drv_alert_, ("\nupdate_attrib => get sta_info fail, ra:" MAC_FMT"\n", MAC_ARG(pattrib->ra)));
++ #ifdef DBG_TX_DROP_FRAME
++ DBG_871X("DBG_TX_DROP_FRAME %s get sta_info fail, ra:" MAC_FMT"\n", __FUNCTION__, MAC_ARG(pattrib->ra));
++ #endif
++ res =_FAIL;
++ goto exit;
++ }
++ else if((check_fwstate(pmlmepriv, WIFI_AP_STATE)==_TRUE)&&(!(psta->state & _FW_LINKED)))
++ {
++ res =_FAIL;
++ goto exit;
++ }
++ }
++
++ if (psta)
++ {
++ pattrib->mac_id = psta->mac_id;
++ pattrib->psta = psta;
++ }
++ else
++ {
++ // if we cannot get psta => drop the pkt
++ RT_TRACE(_module_rtl871x_xmit_c_, _drv_alert_, ("\nupdate_attrib => get sta_info fail, ra:" MAC_FMT "\n", MAC_ARG(pattrib->ra)));
++ #ifdef DBG_TX_DROP_FRAME
++ DBG_871X("DBG_TX_DROP_FRAME %s get sta_info fail, ra:" MAC_FMT"\n", __FUNCTION__, MAC_ARG(pattrib->ra));
++ #endif
++ res = _FAIL;
++ goto exit;
++ }
++
++ pattrib->ack_policy = 0;
++ // get ether_hdr_len
++ pattrib->pkt_hdrlen = ETH_HLEN;//(pattrib->ether_type == 0x8100) ? (14 + 4 ): 14; //vlan tag
++
++ pattrib->hdrlen = WLAN_HDR_A3_LEN;
++ pattrib->subtype = WIFI_DATA_TYPE;
++ pattrib->priority = 0;
++
++ if (check_fwstate(pmlmepriv, WIFI_AP_STATE|WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE))
++ {
++ if(psta->qos_option)
++ set_qos(&pktfile, pattrib);
++ }
++ else
++ {
++ if(pqospriv->qos_option)
++ {
++ set_qos(&pktfile, pattrib);
++
++ if(pmlmepriv->acm_mask != 0)
++ {
++ pattrib->priority = qos_acm(pmlmepriv->acm_mask, pattrib->priority);
++ }
++ }
++ }
++
++ //pattrib->priority = 5; //force to used VI queue, for testing
++
++ if (psta->ieee8021x_blocked == _TRUE)
++ {
++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("\n psta->ieee8021x_blocked == _TRUE \n"));
++
++ pattrib->encrypt = 0;
++
++ if((pattrib->ether_type != 0x888e) && (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _FALSE))
++ {
++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("\npsta->ieee8021x_blocked == _TRUE, pattrib->ether_type(%.4x) != 0x888e\n",pattrib->ether_type));
++ #ifdef DBG_TX_DROP_FRAME
++ DBG_871X("DBG_TX_DROP_FRAME %s psta->ieee8021x_blocked == _TRUE, pattrib->ether_type(%.4x) != 0x888e\n", __FUNCTION__,pattrib->ether_type);
++ #endif
++ res = _FAIL;
++ goto exit;
++ }
++ }
++ else
++ {
++ GET_ENCRY_ALGO(psecuritypriv, psta, pattrib->encrypt, bmcast);
++
++ switch(psecuritypriv->dot11AuthAlgrthm)
++ {
++ case dot11AuthAlgrthm_Open:
++ case dot11AuthAlgrthm_Shared:
++ case dot11AuthAlgrthm_Auto:
++ pattrib->key_idx = (u8)psecuritypriv->dot11PrivacyKeyIndex;
++ break;
++ case dot11AuthAlgrthm_8021X:
++ if(bmcast)
++ pattrib->key_idx = (u8)psecuritypriv->dot118021XGrpKeyid;
++ else
++ pattrib->key_idx = 0;
++ break;
++ default:
++ pattrib->key_idx = 0;
++ break;
++ }
++
++
++ }
++
++ switch (pattrib->encrypt)
++ {
++ case _WEP40_:
++ case _WEP104_:
++ pattrib->iv_len = 4;
++ pattrib->icv_len = 4;
++ break;
++
++ case _TKIP_:
++ pattrib->iv_len = 8;
++ pattrib->icv_len = 4;
++
++ if(padapter->securitypriv.busetkipkey==_FAIL)
++ {
++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("\npadapter->securitypriv.busetkipkey(%d)==_FAIL drop packet\n", padapter->securitypriv.busetkipkey));
++ #ifdef DBG_TX_DROP_FRAME
++ DBG_871X("DBG_TX_DROP_FRAME %s padapter->securitypriv.busetkipkey(%d)==_FAIL drop packet\n", __FUNCTION__, padapter->securitypriv.busetkipkey);
++ #endif
++ res =_FAIL;
++ goto exit;
++ }
++
++ break;
++ case _AES_:
++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("\n pattrib->encrypt=%d (_AES_)\n",pattrib->encrypt));
++ pattrib->iv_len = 8;
++ pattrib->icv_len = 8;
++ break;
++
++ default:
++ pattrib->iv_len = 0;
++ pattrib->icv_len = 0;
++ break;
++ }
++
++ RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_,
++ ("update_attrib: encrypt=%d securitypriv.sw_encrypt=%d\n",
++ pattrib->encrypt, padapter->securitypriv.sw_encrypt));
++
++ if (pattrib->encrypt &&
++ ((padapter->securitypriv.sw_encrypt == _TRUE) || (psecuritypriv->hw_decrypted == _FALSE)))
++ {
++ pattrib->bswenc = _TRUE;
++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,
++ ("update_attrib: encrypt=%d securitypriv.hw_decrypted=%d bswenc=_TRUE\n",
++ pattrib->encrypt, padapter->securitypriv.sw_encrypt));
++ } else {
++ pattrib->bswenc = _FALSE;
++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("update_attrib: bswenc=_FALSE\n"));
++ }
++
++#ifdef CONFIG_CONCURRENT_MODE
++ if((pattrib->encrypt && bmcast) || (pattrib->encrypt ==_WEP40_) || (pattrib->encrypt ==_WEP104_))
++ {
++ pattrib->bswenc = _TRUE;//force using sw enc.
++ }
++#endif
++
++ rtw_set_tx_chksum_offload(pkt, pattrib);
++
++ update_attrib_phy_info(pattrib, psta);
++
++exit:
++
++_func_exit_;
++
++ return res;
++}
++
++static s32 xmitframe_addmic(_adapter *padapter, struct xmit_frame *pxmitframe){
++ sint curfragnum,length;
++ u8 *pframe, *payload,mic[8];
++ struct mic_data micdata;
++ struct sta_info *stainfo;
++ struct qos_priv *pqospriv= &(padapter->mlmepriv.qospriv);
++ struct pkt_attrib *pattrib = &pxmitframe->attrib;
++ struct security_priv *psecuritypriv=&padapter->securitypriv;
++ struct xmit_priv *pxmitpriv=&padapter->xmitpriv;
++ u8 priority[4]={0x0,0x0,0x0,0x0};
++ sint bmcst = IS_MCAST(pattrib->ra);
++
++ if(pattrib->psta)
++ {
++ stainfo = pattrib->psta;
++ }
++ else
++ {
++ DBG_871X("%s, call rtw_get_stainfo()\n", __func__);
++ stainfo=rtw_get_stainfo(&padapter->stapriv ,&pattrib->ra[0]);
++ }
++
++ if(stainfo==NULL)
++ {
++ DBG_871X("%s, psta==NUL\n", __func__);
++ return _FAIL;
++ }
++
++ if(!(stainfo->state &_FW_LINKED))
++ {
++ DBG_871X("%s, psta->state(0x%x) != _FW_LINKED\n", __func__, stainfo->state);
++ return _FAIL;
++ }
++
++_func_enter_;
++
++ if(pattrib->encrypt ==_TKIP_)//if(psecuritypriv->dot11PrivacyAlgrthm==_TKIP_PRIVACY_)
++ {
++ //encode mic code
++ if(stainfo!= NULL){
++ u8 null_key[16]={0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0};
++
++#ifdef CONFIG_USB_TX_AGGREGATION
++ pframe = pxmitframe->buf_addr + TXDESC_SIZE + (pxmitframe->pkt_offset * PACKET_OFFSET_SZ);
++#else
++ pframe = pxmitframe->buf_addr + TXDESC_OFFSET;
++#endif
++
++ if(bmcst)
++ {
++ if(_rtw_memcmp(psecuritypriv->dot118021XGrptxmickey[psecuritypriv->dot118021XGrpKeyid].skey, null_key, 16)==_TRUE){
++ //DbgPrint("\nxmitframe_addmic:stainfo->dot11tkiptxmickey==0\n");
++ //rtw_msleep_os(10);
++ return _FAIL;
++ }
++ //start to calculate the mic code
++ rtw_secmicsetkey(&micdata, psecuritypriv->dot118021XGrptxmickey[psecuritypriv->dot118021XGrpKeyid].skey);
++ }
++ else
++ {
++ if(_rtw_memcmp(&stainfo->dot11tkiptxmickey.skey[0],null_key, 16)==_TRUE){
++ //DbgPrint("\nxmitframe_addmic:stainfo->dot11tkiptxmickey==0\n");
++ //rtw_msleep_os(10);
++ return _FAIL;
++ }
++ //start to calculate the mic code
++ rtw_secmicsetkey(&micdata, &stainfo->dot11tkiptxmickey.skey[0]);
++ }
++
++ if(pframe[1]&1){ //ToDS==1
++ rtw_secmicappend(&micdata, &pframe[16], 6); //DA
++ if(pframe[1]&2) //From Ds==1
++ rtw_secmicappend(&micdata, &pframe[24], 6);
++ else
++ rtw_secmicappend(&micdata, &pframe[10], 6);
++ }
++ else{ //ToDS==0
++ rtw_secmicappend(&micdata, &pframe[4], 6); //DA
++ if(pframe[1]&2) //From Ds==1
++ rtw_secmicappend(&micdata, &pframe[16], 6);
++ else
++ rtw_secmicappend(&micdata, &pframe[10], 6);
++
++ }
++
++ //if(pqospriv->qos_option==1)
++ if(pattrib->qos_en)
++ priority[0]=(u8)pxmitframe->attrib.priority;
++
++
++ rtw_secmicappend(&micdata, &priority[0], 4);
++
++ payload=pframe;
++
++ for(curfragnum=0;curfragnum<pattrib->nr_frags;curfragnum++){
++ payload=(u8 *)RND4((SIZE_PTR)(payload));
++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("===curfragnum=%d, pframe= 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x,!!!\n",
++ curfragnum,*payload, *(payload+1),*(payload+2),*(payload+3),*(payload+4),*(payload+5),*(payload+6),*(payload+7)));
++
++ payload=payload+pattrib->hdrlen+pattrib->iv_len;
++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("curfragnum=%d pattrib->hdrlen=%d pattrib->iv_len=%d",curfragnum,pattrib->hdrlen,pattrib->iv_len));
++ if((curfragnum+1)==pattrib->nr_frags){
++ length=pattrib->last_txcmdsz-pattrib->hdrlen-pattrib->iv_len-( (pattrib->bswenc) ? pattrib->icv_len : 0);
++ rtw_secmicappend(&micdata, payload,length);
++ payload=payload+length;
++ }
++ else{
++ length=pxmitpriv->frag_len-pattrib->hdrlen-pattrib->iv_len-( (pattrib->bswenc) ? pattrib->icv_len : 0);
++ rtw_secmicappend(&micdata, payload, length);
++ payload=payload+length+pattrib->icv_len;
++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("curfragnum=%d length=%d pattrib->icv_len=%d",curfragnum,length,pattrib->icv_len));
++ }
++ }
++ rtw_secgetmic(&micdata,&(mic[0]));
++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("xmitframe_addmic: before add mic code!!!\n"));
++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("xmitframe_addmic: pattrib->last_txcmdsz=%d!!!\n",pattrib->last_txcmdsz));
++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("xmitframe_addmic: mic[0]=0x%.2x ,mic[1]=0x%.2x ,mic[2]=0x%.2x ,mic[3]=0x%.2x \n\
++ mic[4]=0x%.2x ,mic[5]=0x%.2x ,mic[6]=0x%.2x ,mic[7]=0x%.2x !!!!\n",
++ mic[0],mic[1],mic[2],mic[3],mic[4],mic[5],mic[6],mic[7]));
++ //add mic code and add the mic code length in last_txcmdsz
++
++ _rtw_memcpy(payload, &(mic[0]),8);
++ pattrib->last_txcmdsz+=8;
++
++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("\n ========last pkt========\n"));
++ payload=payload-pattrib->last_txcmdsz+8;
++ for(curfragnum=0;curfragnum<pattrib->last_txcmdsz;curfragnum=curfragnum+8)
++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,(" %.2x, %.2x, %.2x, %.2x, %.2x, %.2x, %.2x, %.2x ",
++ *(payload+curfragnum), *(payload+curfragnum+1), *(payload+curfragnum+2),*(payload+curfragnum+3),
++ *(payload+curfragnum+4),*(payload+curfragnum+5),*(payload+curfragnum+6),*(payload+curfragnum+7)));
++ }
++ else{
++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("xmitframe_addmic: rtw_get_stainfo==NULL!!!\n"));
++ }
++ }
++
++_func_exit_;
++
++ return _SUCCESS;
++}
++
++static s32 xmitframe_swencrypt(_adapter *padapter, struct xmit_frame *pxmitframe){
++
++ struct pkt_attrib *pattrib = &pxmitframe->attrib;
++ //struct security_priv *psecuritypriv=&padapter->securitypriv;
++
++_func_enter_;
++
++ //if((psecuritypriv->sw_encrypt)||(pattrib->bswenc))
++ if(pattrib->bswenc)
++ {
++ //DBG_871X("start xmitframe_swencrypt\n");
++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_alert_,("### xmitframe_swencrypt\n"));
++ switch(pattrib->encrypt){
++ case _WEP40_:
++ case _WEP104_:
++ rtw_wep_encrypt(padapter, (u8 *)pxmitframe);
++ break;
++ case _TKIP_:
++ rtw_tkip_encrypt(padapter, (u8 *)pxmitframe);
++ break;
++ case _AES_:
++ rtw_aes_encrypt(padapter, (u8 * )pxmitframe);
++ break;
++ default:
++ break;
++ }
++
++ } else {
++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_notice_,("### xmitframe_hwencrypt\n"));
++ }
++
++_func_exit_;
++
++ return _SUCCESS;
++}
++
++s32 rtw_make_wlanhdr (_adapter *padapter , u8 *hdr, struct pkt_attrib *pattrib)
++{
++ u16 *qc;
++
++ struct rtw_ieee80211_hdr *pwlanhdr = (struct rtw_ieee80211_hdr *)hdr;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct qos_priv *pqospriv = &pmlmepriv->qospriv;
++ u8 qos_option = _FALSE;
++#ifdef CONFIG_TDLS
++ struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
++ struct sta_priv *pstapriv = &padapter->stapriv;
++ struct sta_info *ptdls_sta=NULL, *psta_backup=NULL;
++ u8 direct_link=0;
++#endif //CONFIG_TDLS
++
++ sint res = _SUCCESS;
++ u16 *fctrl = &pwlanhdr->frame_ctl;
++
++ struct sta_info *psta;
++
++ sint bmcst = IS_MCAST(pattrib->ra);
++
++_func_enter_;
++
++ if (pattrib->psta) {
++ psta = pattrib->psta;
++ } else {
++ DBG_871X("%s, call rtw_get_stainfo()\n", __func__);
++ if(bmcst) {
++ psta = rtw_get_bcmc_stainfo(padapter);
++ } else {
++ psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra);
++ }
++ }
++
++ if(psta==NULL)
++ {
++ DBG_871X("%s, psta==NUL\n", __func__);
++ return _FAIL;
++ }
++
++ if(!(psta->state &_FW_LINKED))
++ {
++ DBG_871X("%s, psta->state(0x%x) != _FW_LINKED\n", __func__, psta->state);
++ return _FAIL;
++ }
++
++ _rtw_memset(hdr, 0, WLANHDR_OFFSET);
++
++ SetFrameSubType(fctrl, pattrib->subtype);
++
++ if (pattrib->subtype & WIFI_DATA_TYPE)
++ {
++ if ((check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)) {
++ //to_ds = 1, fr_ds = 0;
++#ifdef CONFIG_TDLS
++ if((ptdlsinfo->setup_state == TDLS_LINKED_STATE)){
++ ptdls_sta = rtw_get_stainfo(pstapriv, pattrib->dst);
++ if((ptdls_sta!=NULL)&&(ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE)&&(pattrib->ether_type!=0x0806)){
++ //TDLS data transfer, ToDS=0, FrDs=0
++ _rtw_memcpy(pwlanhdr->addr1, pattrib->dst, ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr2, pattrib->src, ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr3, get_bssid(pmlmepriv), ETH_ALEN);
++ direct_link=1;
++ }else{
++ // 1.Data transfer to AP
++ // 2.Arp pkt will relayed by AP
++ SetToDs(fctrl);
++ _rtw_memcpy(pwlanhdr->addr1, get_bssid(pmlmepriv), ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr2, pattrib->src, ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr3, pattrib->dst, ETH_ALEN);
++ }
++ }else
++#endif //CONFIG_TDLS
++ {
++ //Data transfer to AP
++ SetToDs(fctrl);
++ _rtw_memcpy(pwlanhdr->addr1, get_bssid(pmlmepriv), ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr2, pattrib->src, ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr3, pattrib->dst, ETH_ALEN);
++ }
++
++ if (pqospriv->qos_option)
++ qos_option = _TRUE;
++
++ }
++ else if ((check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) ) {
++ //to_ds = 0, fr_ds = 1;
++ SetFrDs(fctrl);
++ _rtw_memcpy(pwlanhdr->addr1, pattrib->dst, ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr2, get_bssid(pmlmepriv), ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr3, pattrib->src, ETH_ALEN);
++
++ if(psta->qos_option)
++ qos_option = _TRUE;
++ }
++ else if ((check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) ||
++ (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)) {
++ _rtw_memcpy(pwlanhdr->addr1, pattrib->dst, ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr2, pattrib->src, ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr3, get_bssid(pmlmepriv), ETH_ALEN);
++
++ if(psta->qos_option)
++ qos_option = _TRUE;
++ }
++ else {
++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("fw_state:%x is not allowed to xmit frame\n", get_fwstate(pmlmepriv)));
++ res = _FAIL;
++ goto exit;
++ }
++
++ if(pattrib->mdata)
++ SetMData(fctrl);
++
++ if (pattrib->encrypt)
++ SetPrivacy(fctrl);
++
++ if (qos_option)
++ {
++ qc = (unsigned short *)(hdr + pattrib->hdrlen - 2);
++
++ if (pattrib->priority)
++ SetPriority(qc, pattrib->priority);
++
++ SetEOSP(qc, pattrib->eosp);
++
++ SetAckpolicy(qc, pattrib->ack_policy);
++ }
++
++ //TODO: fill HT Control Field
++
++ //Update Seq Num will be handled by f/w
++ {
++ if(psta){
++#ifdef CONFIG_TDLS
++ if(direct_link==1)
++ {
++ psta_backup = psta;
++ psta = ptdls_sta;
++ }
++#endif //CONFIG_TDLS
++
++ psta->sta_xmitpriv.txseq_tid[pattrib->priority]++;
++ psta->sta_xmitpriv.txseq_tid[pattrib->priority] &= 0xFFF;
++
++ pattrib->seqnum = psta->sta_xmitpriv.txseq_tid[pattrib->priority];
++
++ SetSeqNum(hdr, pattrib->seqnum);
++
++
++ //check if enable ampdu
++ if(pattrib->ht_en && psta->htpriv.ampdu_enable)
++ {
++ if(psta->htpriv.agg_enable_bitmap & BIT(pattrib->priority))
++ pattrib->ampdu_en = _TRUE;
++ }
++
++ //re-check if enable ampdu by BA_starting_seqctrl
++ if(pattrib->ampdu_en == _TRUE)
++ {
++ u16 tx_seq;
++
++ tx_seq = psta->BA_starting_seqctrl[pattrib->priority & 0x0f];
++
++ //check BA_starting_seqctrl
++ if(SN_LESS(pattrib->seqnum, tx_seq))
++ {
++ //DBG_871X("tx ampdu seqnum(%d) < tx_seq(%d)\n", pattrib->seqnum, tx_seq);
++ pattrib->ampdu_en = _FALSE;//AGG BK
++ }
++ else if(SN_EQUAL(pattrib->seqnum, tx_seq))
++ {
++ psta->BA_starting_seqctrl[pattrib->priority & 0x0f] = (tx_seq+1)&0xfff;
++
++ pattrib->ampdu_en = _TRUE;//AGG EN
++ }
++ else
++ {
++ //DBG_871X("tx ampdu over run\n");
++ psta->BA_starting_seqctrl[pattrib->priority & 0x0f] = (pattrib->seqnum+1)&0xfff;
++ pattrib->ampdu_en = _TRUE;//AGG EN
++ }
++
++ }
++
++#ifdef CONFIG_TDLS
++ if(direct_link==1)
++ {
++ if (pattrib->encrypt){
++ pattrib->encrypt= _AES_;
++ pattrib->iv_len=8;
++ pattrib->icv_len=8;
++ }
++
++ //qos_en, ht_en, init rate, ,bw, ch_offset, sgi
++ //pattrib->qos_en = ptdls_sta->qos_option;
++ pattrib->ht_en = ptdls_sta->htpriv.ht_option;
++ pattrib->raid = ptdls_sta->raid;
++ pattrib->bwmode = ptdls_sta->htpriv.bwmode;
++ pattrib->ch_offset = ptdls_sta->htpriv.ch_offset;
++ pattrib->sgi= ptdls_sta->htpriv.sgi;
++
++ pattrib->mac_id = ptdls_sta->mac_id;
++
++ psta = psta_backup;
++ }
++#endif //CONFIG_TDLS
++
++ }
++ }
++
++ }
++ else
++ {
++
++ }
++
++exit:
++
++_func_exit_;
++
++ return res;
++}
++
++s32 rtw_txframes_pending(_adapter *padapter)
++{
++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++
++ return ((_rtw_queue_empty(&pxmitpriv->be_pending) == _FALSE) ||
++ (_rtw_queue_empty(&pxmitpriv->bk_pending) == _FALSE) ||
++ (_rtw_queue_empty(&pxmitpriv->vi_pending) == _FALSE) ||
++ (_rtw_queue_empty(&pxmitpriv->vo_pending) == _FALSE));
++}
++
++s32 rtw_txframes_sta_ac_pending(_adapter *padapter, struct pkt_attrib *pattrib)
++{
++ struct sta_info *psta;
++ struct tx_servq *ptxservq;
++ int priority = pattrib->priority;
++
++ if(pattrib->psta)
++ {
++ psta = pattrib->psta;
++ }
++ else
++ {
++ DBG_871X("%s, call rtw_get_stainfo()\n", __func__);
++ psta=rtw_get_stainfo(&padapter->stapriv ,&pattrib->ra[0]);
++ }
++
++ if(psta==NULL)
++ {
++ DBG_871X("%s, psta==NUL\n", __func__);
++ return 0;
++ }
++
++ if(!(psta->state &_FW_LINKED))
++ {
++ DBG_871X("%s, psta->state(0x%x) != _FW_LINKED\n", __func__, psta->state);
++ return 0;
++ }
++
++ switch(priority)
++ {
++ case 1:
++ case 2:
++ ptxservq = &(psta->sta_xmitpriv.bk_q);
++ break;
++ case 4:
++ case 5:
++ ptxservq = &(psta->sta_xmitpriv.vi_q);
++ break;
++ case 6:
++ case 7:
++ ptxservq = &(psta->sta_xmitpriv.vo_q);
++ break;
++ case 0:
++ case 3:
++ default:
++ ptxservq = &(psta->sta_xmitpriv.be_q);
++ break;
++
++ }
++
++ return ptxservq->qcnt;
++}
++
++#ifdef CONFIG_TDLS
++
++int rtw_build_tdls_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe, u8 action)
++{
++ int res=_SUCCESS;
++
++ switch(action){
++ case TDLS_SETUP_REQUEST:
++ rtw_build_tdls_setup_req_ies(padapter, pxmitframe, pframe);
++ break;
++ case TDLS_SETUP_RESPONSE:
++ rtw_build_tdls_setup_rsp_ies(padapter, pxmitframe, pframe);
++ break;
++ case TDLS_SETUP_CONFIRM:
++ rtw_build_tdls_setup_cfm_ies(padapter, pxmitframe, pframe);
++ break;
++ case TDLS_TEARDOWN:
++ rtw_build_tdls_teardown_ies(padapter, pxmitframe, pframe);
++ break;
++ case TDLS_DISCOVERY_REQUEST:
++ rtw_build_tdls_dis_req_ies(padapter, pxmitframe, pframe);
++ break;
++ case TDLS_PEER_TRAFFIC_INDICATION:
++ rtw_build_tdls_peer_traffic_indication_ies(padapter, pxmitframe, pframe);
++ break;
++ case TDLS_CHANNEL_SWITCH_REQUEST:
++ rtw_build_tdls_ch_switch_req_ies(padapter, pxmitframe, pframe);
++ break;
++ case TDLS_CHANNEL_SWITCH_RESPONSE:
++ rtw_build_tdls_ch_switch_rsp_ies(padapter, pxmitframe, pframe);
++ break;
++#ifdef CONFIG_WFD
++ case TUNNELED_PROBE_REQ:
++ rtw_build_tunneled_probe_req_ies(padapter, pxmitframe, pframe);
++ break;
++ case TUNNELED_PROBE_RSP:
++ rtw_build_tunneled_probe_rsp_ies(padapter, pxmitframe, pframe);
++ break;
++#endif //CONFIG_WFD
++ default:
++ res=_FAIL;
++ break;
++ }
++
++ return res;
++}
++
++s32 rtw_make_tdls_wlanhdr (_adapter *padapter , u8 *hdr, struct pkt_attrib *pattrib, u8 action)
++{
++ u16 *qc;
++ struct rtw_ieee80211_hdr *pwlanhdr = (struct rtw_ieee80211_hdr *)hdr;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct qos_priv *pqospriv = &pmlmepriv->qospriv;
++ struct sta_priv *pstapriv = &padapter->stapriv;
++ struct sta_info *psta=NULL, *ptdls_sta=NULL;
++ u8 tdls_seq=0, baddr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
++
++ sint res = _SUCCESS;
++ u16 *fctrl = &pwlanhdr->frame_ctl;
++
++_func_enter_;
++
++ _rtw_memset(hdr, 0, WLANHDR_OFFSET);
++
++ SetFrameSubType(fctrl, pattrib->subtype);
++
++ switch(action){
++ case TDLS_SETUP_REQUEST:
++ case TDLS_SETUP_RESPONSE:
++ case TDLS_SETUP_CONFIRM:
++ case TDLS_TEARDOWN: //directly to peer STA or via AP
++ case TDLS_PEER_TRAFFIC_INDICATION:
++ case TDLS_PEER_PSM_REQUEST: //directly to peer STA or via AP
++ case TUNNELED_PROBE_REQ:
++ case TUNNELED_PROBE_RSP:
++ SetToDs(fctrl);
++ _rtw_memcpy(pwlanhdr->addr1, get_bssid(pmlmepriv), ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr2, pattrib->src, ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr3, pattrib->dst, ETH_ALEN);
++ break;
++ case TDLS_CHANNEL_SWITCH_REQUEST:
++ case TDLS_CHANNEL_SWITCH_RESPONSE:
++ case TDLS_PEER_PSM_RESPONSE:
++ case TDLS_PEER_TRAFFIC_RESPONSE:
++ _rtw_memcpy(pwlanhdr->addr1, pattrib->dst, ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr2, pattrib->src, ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr3, get_bssid(pmlmepriv), ETH_ALEN);
++ tdls_seq=1;
++ break;
++ case TDLS_DISCOVERY_REQUEST: //unicast: directly to peer sta, Bcast: via AP
++ if(_rtw_memcmp(pattrib->dst, baddr, ETH_ALEN) )
++ {
++ SetToDs(fctrl);
++ _rtw_memcpy(pwlanhdr->addr1, get_bssid(pmlmepriv), ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr2, pattrib->src, ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr3, pattrib->dst, ETH_ALEN);
++ }
++ else
++ {
++ _rtw_memcpy(pwlanhdr->addr1, pattrib->dst, ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr2, pattrib->src, ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr3, get_bssid(pmlmepriv), ETH_ALEN);
++ tdls_seq=1;
++ }
++ break;
++ }
++
++ if (pattrib->encrypt)
++ SetPrivacy(fctrl);
++
++ if (pqospriv->qos_option)
++ {
++ qc = (unsigned short *)(hdr + pattrib->hdrlen - 2);
++ if (pattrib->priority)
++ SetPriority(qc, pattrib->priority);
++ SetAckpolicy(qc, pattrib->ack_policy);
++ }
++
++ psta = pattrib->psta;
++
++ // 1. update seq_num per link by sta_info
++ // 2. rewrite encrypt to _AES_, also rewrite iv_len, icv_len
++ if(tdls_seq==1){
++ ptdls_sta=rtw_get_stainfo(pstapriv, pattrib->dst);
++ if(ptdls_sta){
++ ptdls_sta->sta_xmitpriv.txseq_tid[pattrib->priority]++;
++ ptdls_sta->sta_xmitpriv.txseq_tid[pattrib->priority] &= 0xFFF;
++ pattrib->seqnum = ptdls_sta->sta_xmitpriv.txseq_tid[pattrib->priority];
++ SetSeqNum(hdr, pattrib->seqnum);
++
++ if (pattrib->encrypt){
++ pattrib->encrypt= _AES_;
++ pattrib->iv_len=8;
++ pattrib->icv_len=8;
++ }
++ }else{
++ res=_FAIL;
++ goto exit;
++ }
++ }else if(psta){
++ psta->sta_xmitpriv.txseq_tid[pattrib->priority]++;
++ psta->sta_xmitpriv.txseq_tid[pattrib->priority] &= 0xFFF;
++ pattrib->seqnum = psta->sta_xmitpriv.txseq_tid[pattrib->priority];
++ SetSeqNum(hdr, pattrib->seqnum);
++ }
++
++
++exit:
++
++_func_exit_;
++
++ return res;
++}
++
++s32 rtw_xmit_tdls_coalesce(_adapter * padapter, struct xmit_frame * pxmitframe, u8 action)
++{
++ s32 llc_sz;
++
++ u8 *pframe, *mem_start;
++
++ struct sta_info *psta;
++ struct sta_priv *pstapriv = &padapter->stapriv;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct pkt_attrib *pattrib = &pxmitframe->attrib;
++ u8 *pbuf_start;
++ s32 bmcst = IS_MCAST(pattrib->ra);
++ s32 res = _SUCCESS;
++
++_func_enter_;
++
++ if (pattrib->psta) {
++ psta = pattrib->psta;
++ } else {
++ if(bmcst) {
++ psta = rtw_get_bcmc_stainfo(padapter);
++ } else {
++ psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra);
++ }
++ }
++
++ if(psta==NULL)
++ return _FAIL;
++
++ if (pxmitframe->buf_addr == NULL)
++ return _FAIL;
++
++ pbuf_start = pxmitframe->buf_addr;
++ mem_start = pbuf_start + TXDESC_OFFSET;
++
++ if (rtw_make_tdls_wlanhdr(padapter, mem_start, pattrib, action) == _FAIL) {
++ res = _FAIL;
++ goto exit;
++ }
++
++ pframe = mem_start;
++ pframe += pattrib->hdrlen;
++
++ //adding icv, if necessary...
++ if (pattrib->iv_len)
++ {
++ if (psta != NULL)
++ {
++ switch(pattrib->encrypt)
++ {
++ case _WEP40_:
++ case _WEP104_:
++ WEP_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx);
++ break;
++ case _TKIP_:
++ if(bmcst)
++ TKIP_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx);
++ else
++ TKIP_IV(pattrib->iv, psta->dot11txpn, 0);
++ break;
++ case _AES_:
++ if(bmcst)
++ AES_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx);
++ else
++ AES_IV(pattrib->iv, psta->dot11txpn, 0);
++ break;
++ }
++ }
++
++ _rtw_memcpy(pframe, pattrib->iv, pattrib->iv_len);
++ pframe += pattrib->iv_len;
++
++ }
++
++ llc_sz = rtw_put_snap(pframe, pattrib->ether_type);
++ pframe += llc_sz;
++
++ //pattrib->pktlen will be counted in rtw_build_tdls_ies
++ pattrib->pktlen = 0;
++
++ rtw_build_tdls_ies(padapter, pxmitframe, pframe, action);
++
++ if ((pattrib->icv_len >0 )&& (pattrib->bswenc)) {
++ pframe += pattrib->pktlen;
++ _rtw_memcpy(pframe, pattrib->icv, pattrib->icv_len);
++ pframe += pattrib->icv_len;
++ }
++
++ pattrib->nr_frags = 1;
++ pattrib->last_txcmdsz = pattrib->hdrlen + pattrib->iv_len + llc_sz +
++ ((pattrib->bswenc) ? pattrib->icv_len : 0) + pattrib->pktlen;
++
++ if (xmitframe_addmic(padapter, pxmitframe) == _FAIL)
++ {
++ goto exit;
++ }
++
++ xmitframe_swencrypt(padapter, pxmitframe);
++
++ update_attrib_vcs_info(padapter, pxmitframe);
++
++exit:
++
++_func_exit_;
++
++ return res;
++}
++#endif //CONFIG_TDLS
++
++/*
++ * Calculate wlan 802.11 packet MAX size from pkt_attrib
++ * This function doesn't consider fragment case
++ */
++u32 rtw_calculate_wlan_pkt_size_by_attribue(struct pkt_attrib *pattrib)
++{
++ u32 len = 0;
++
++ len = pattrib->hdrlen + pattrib->iv_len; // WLAN Header and IV
++ len += SNAP_SIZE + sizeof(u16); // LLC
++ len += pattrib->pktlen;
++ if (pattrib->encrypt == _TKIP_) len += 8; // MIC
++ len += pattrib->icv_len; // ICV
++
++ return len;
++}
++
++/*
++
++This sub-routine will perform all the following:
++
++1. remove 802.3 header.
++2. create wlan_header, based on the info in pxmitframe
++3. append sta's iv/ext-iv
++4. append LLC
++5. move frag chunk from pframe to pxmitframe->mem
++6. apply sw-encrypt, if necessary.
++
++*/
++s32 rtw_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxmitframe)
++{
++ struct pkt_file pktfile;
++
++ s32 frg_inx, frg_len, mpdu_len, llc_sz, mem_sz;
++
++ SIZE_PTR addr;
++
++ u8 *pframe, *mem_start;
++
++ struct sta_info *psta;
++ //struct sta_priv *pstapriv = &padapter->stapriv;
++ //struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++
++ struct pkt_attrib *pattrib = &pxmitframe->attrib;
++
++ u8 *pbuf_start;
++
++ s32 bmcst = IS_MCAST(pattrib->ra);
++ s32 res = _SUCCESS;
++
++_func_enter_;
++
++ if (pattrib->psta)
++ {
++ psta = pattrib->psta;
++ } else
++ {
++ DBG_871X("%s, call rtw_get_stainfo()\n", __func__);
++ psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra);
++ }
++
++ if(psta==NULL)
++ {
++
++ DBG_871X("%s, psta==NUL\n", __func__);
++ return _FAIL;
++ }
++
++
++ if(!(psta->state &_FW_LINKED))
++ {
++ DBG_871X("%s, psta->state(0x%x) != _FW_LINKED\n", __func__, psta->state);
++ return _FAIL;
++ }
++
++ if (pxmitframe->buf_addr == NULL){
++ DBG_8192C("==> %s buf_addr==NULL \n",__FUNCTION__);
++ return _FAIL;
++ }
++
++ pbuf_start = pxmitframe->buf_addr;
++
++#ifdef CONFIG_USB_TX_AGGREGATION
++ mem_start = pbuf_start + TXDESC_SIZE + (pxmitframe->pkt_offset * PACKET_OFFSET_SZ);
++#else
++ mem_start = pbuf_start + TXDESC_OFFSET;
++#endif
++
++ if (rtw_make_wlanhdr(padapter, mem_start, pattrib) == _FAIL) {
++ RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("rtw_xmitframe_coalesce: rtw_make_wlanhdr fail; drop pkt\n"));
++ res = _FAIL;
++ goto exit;
++ }
++
++ _rtw_open_pktfile(pkt, &pktfile);
++ _rtw_pktfile_read(&pktfile, NULL, pattrib->pkt_hdrlen);
++
++ frg_inx = 0;
++ frg_len = pxmitpriv->frag_len - 4;//2346-4 = 2342
++
++ while (1)
++ {
++ llc_sz = 0;
++
++ mpdu_len = frg_len;
++
++ pframe = mem_start;
++
++ SetMFrag(mem_start);
++
++ pframe += pattrib->hdrlen;
++ mpdu_len -= pattrib->hdrlen;
++
++ //adding icv, if necessary...
++ if (pattrib->iv_len)
++ {
++ //if (check_fwstate(pmlmepriv, WIFI_MP_STATE))
++ // psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));
++ //else
++ // psta = rtw_get_stainfo(pstapriv, pattrib->ra);
++
++ if (psta != NULL)
++ {
++ switch(pattrib->encrypt)
++ {
++ case _WEP40_:
++ case _WEP104_:
++ WEP_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx);
++ break;
++ case _TKIP_:
++ if(bmcst)
++ TKIP_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx);
++ else
++ TKIP_IV(pattrib->iv, psta->dot11txpn, 0);
++ break;
++ case _AES_:
++ if(bmcst)
++ AES_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx);
++ else
++ AES_IV(pattrib->iv, psta->dot11txpn, 0);
++ break;
++ }
++ }
++
++ _rtw_memcpy(pframe, pattrib->iv, pattrib->iv_len);
++
++ RT_TRACE(_module_rtl871x_xmit_c_, _drv_notice_,
++ ("rtw_xmitframe_coalesce: keyid=%d pattrib->iv[3]=%.2x pframe=%.2x %.2x %.2x %.2x\n",
++ padapter->securitypriv.dot11PrivacyKeyIndex, pattrib->iv[3], *pframe, *(pframe+1), *(pframe+2), *(pframe+3)));
++
++ pframe += pattrib->iv_len;
++
++ mpdu_len -= pattrib->iv_len;
++ }
++
++ if (frg_inx == 0) {
++ llc_sz = rtw_put_snap(pframe, pattrib->ether_type);
++ pframe += llc_sz;
++ mpdu_len -= llc_sz;
++ }
++
++ if ((pattrib->icv_len >0) && (pattrib->bswenc)) {
++ mpdu_len -= pattrib->icv_len;
++ }
++
++
++ if (bmcst) {
++ // don't do fragment to broadcat/multicast packets
++ mem_sz = _rtw_pktfile_read(&pktfile, pframe, pattrib->pktlen);
++ } else {
++ mem_sz = _rtw_pktfile_read(&pktfile, pframe, mpdu_len);
++ }
++
++ pframe += mem_sz;
++
++ if ((pattrib->icv_len >0 )&& (pattrib->bswenc)) {
++ _rtw_memcpy(pframe, pattrib->icv, pattrib->icv_len);
++ pframe += pattrib->icv_len;
++ }
++
++ frg_inx++;
++
++ if (bmcst || (rtw_endofpktfile(&pktfile) == _TRUE))
++ {
++ pattrib->nr_frags = frg_inx;
++
++ pattrib->last_txcmdsz = pattrib->hdrlen + pattrib->iv_len + ((pattrib->nr_frags==1)? llc_sz:0) +
++ ((pattrib->bswenc) ? pattrib->icv_len : 0) + mem_sz;
++
++ ClearMFrag(mem_start);
++
++ break;
++ } else {
++ RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("%s: There're still something in packet!\n", __FUNCTION__));
++ }
++
++ addr = (SIZE_PTR)(pframe);
++
++ mem_start = (unsigned char *)RND4(addr) + TXDESC_OFFSET;
++ _rtw_memcpy(mem_start, pbuf_start + TXDESC_OFFSET, pattrib->hdrlen);
++ }
++
++ if (xmitframe_addmic(padapter, pxmitframe) == _FAIL)
++ {
++ RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("xmitframe_addmic(padapter, pxmitframe)==_FAIL\n"));
++ res = _FAIL;
++ goto exit;
++ }
++
++ xmitframe_swencrypt(padapter, pxmitframe);
++
++ if(bmcst == _FALSE)
++ update_attrib_vcs_info(padapter, pxmitframe);
++ else
++ pattrib->vcs_mode = NONE_VCS;
++
++exit:
++
++_func_exit_;
++
++ return res;
++}
++
++#ifdef CONFIG_IEEE80211W
++//broadcast or multicast management pkt use BIP, unicast management pkt use CCMP encryption
++s32 rtw_mgmt_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxmitframe)
++{
++ struct pkt_file pktfile;
++ s32 frg_inx, frg_len, mpdu_len, llc_sz, mem_sz;
++ SIZE_PTR addr;
++ u8 *pframe, *mem_start = NULL, *tmp_buf=NULL;
++ u8 hw_hdr_offset, subtype ;
++ struct sta_info *psta = NULL;
++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++ struct pkt_attrib *pattrib = &pxmitframe->attrib;
++ u8 *pbuf_start;
++ s32 bmcst = IS_MCAST(pattrib->ra);
++ s32 res = _FAIL;
++ u8 *BIP_AAD=NULL;
++ u8 *MGMT_body=NULL;
++
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct rtw_ieee80211_hdr *pwlanhdr;
++ u8 MME[_MME_IE_LENGTH_];
++
++ _irqL irqL;
++ u32 ori_len;
++ mem_start = pframe = (u8 *)(pxmitframe->buf_addr) + TXDESC_OFFSET;
++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++_func_enter_;
++ ori_len = BIP_AAD_SIZE+pattrib->pktlen;
++ tmp_buf = BIP_AAD = rtw_zmalloc(ori_len);
++ subtype = GetFrameSubType(pframe); //bit(7)~bit(2)
++
++ if(BIP_AAD == NULL)
++ return _FAIL;
++
++ _enter_critical_bh(&padapter->security_key_mutex, &irqL);
++
++ //only support station mode
++ if(!check_fwstate(pmlmepriv, WIFI_STATION_STATE) || !check_fwstate(pmlmepriv, _FW_LINKED))
++ goto xmitframe_coalesce_success;
++
++ //IGTK key is not install, it may not support 802.11w
++ if(padapter->securitypriv.binstallBIPkey != _TRUE)
++ {
++ DBG_871X("no instll BIP key\n");
++ goto xmitframe_coalesce_success;
++ }
++ //station mode doesn't need TX BIP, just ready the code
++ if(bmcst)
++ {
++ int frame_body_len;
++ u8 mic[16];
++
++ _rtw_memset(MME, 0, 18);
++
++ //other types doesn't need the BIP
++ if(GetFrameSubType(pframe) != WIFI_DEAUTH && GetFrameSubType(pframe) != WIFI_DISASSOC)
++ goto xmitframe_coalesce_fail;
++
++ MGMT_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr);
++ pframe += pattrib->pktlen;
++
++ //octent 0 and 1 is key index ,BIP keyid is 4 or 5, LSB only need octent 0
++ MME[0]=padapter->securitypriv.dot11wBIPKeyid;
++ //copy packet number
++ _rtw_memcpy(&MME[2], &pmlmeext->mgnt_80211w_IPN, 6);
++ //increase the packet number
++ pmlmeext->mgnt_80211w_IPN++;
++
++ //add MME IE with MIC all zero, MME string doesn't include element id and length
++ pframe = rtw_set_ie(pframe, _MME_IE_ , 16 , MME, &(pattrib->pktlen));
++ pattrib->last_txcmdsz = pattrib->pktlen;
++ // total frame length - header length
++ frame_body_len = pattrib->pktlen - sizeof(struct rtw_ieee80211_hdr_3addr);
++
++ //conscruct AAD, copy frame control field
++ _rtw_memcpy(BIP_AAD, &pwlanhdr->frame_ctl, 2);
++ ClearRetry(BIP_AAD);
++ ClearPwrMgt(BIP_AAD);
++ ClearMData(BIP_AAD);
++ //conscruct AAD, copy address 1 to address 3
++ _rtw_memcpy(BIP_AAD+2, pwlanhdr->addr1, 18);
++ //copy management fram body
++ _rtw_memcpy(BIP_AAD+BIP_AAD_SIZE, MGMT_body, frame_body_len);
++ /*//dump total packet include MME with zero MIC
++ {
++ int i;
++ printk("Total packet: ");
++ for(i=0; i < BIP_AAD_SIZE+frame_body_len; i++)
++ printk(" %02x ", BIP_AAD[i]);
++ printk("\n");
++ }*/
++ //calculate mic
++ if(omac1_aes_128(padapter->securitypriv.dot11wBIPKey[padapter->securitypriv.dot11wBIPKeyid].skey
++ , BIP_AAD, BIP_AAD_SIZE+frame_body_len, mic))
++ goto xmitframe_coalesce_fail;
++
++ /*//dump calculated mic result
++ {
++ int i;
++ printk("Calculated mic result: ");
++ for(i=0; i<16; i++)
++ printk(" %02x ", mic[i]);
++ printk("\n");
++ }*/
++ //copy right BIP mic value, total is 128bits, we use the 0~63 bits
++ _rtw_memcpy(pframe-8, mic, 8);
++ /*/dump all packet after mic ok
++ {
++ int pp;
++ printk("pattrib->pktlen = %d \n", pattrib->pktlen);
++ for(pp=0;pp< pattrib->pktlen; pp++)
++ printk(" %02x ", mem_start[pp]);
++ printk("\n");
++ }*/
++ }
++ else //unicast mgmt frame TX
++ {
++ //start to encrypt mgmt frame
++ if(subtype == WIFI_DEAUTH || subtype == WIFI_DISASSOC ||
++ subtype == WIFI_REASSOCREQ || subtype == WIFI_ACTION)
++ {
++ if (pattrib->psta)
++ psta = pattrib->psta;
++ else
++ {
++ psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra);
++ }
++
++ if(psta==NULL)
++ {
++
++ DBG_871X("%s, psta==NUL\n", __func__);
++ goto xmitframe_coalesce_fail;
++ }
++
++ if(!(psta->state & _FW_LINKED) || pxmitframe->buf_addr==NULL)
++ {
++ DBG_871X("%s, not _FW_LINKED or addr null\n", __func__);
++ goto xmitframe_coalesce_fail;
++ }
++
++ //DBG_871X("%s, action frame category=%d \n", __func__, pframe[WLAN_HDR_A3_LEN]);
++ //according 802.11-2012 standard, these five types are not robust types
++ if(subtype == WIFI_ACTION &&
++ (pframe[WLAN_HDR_A3_LEN] == RTW_WLAN_CATEGORY_PUBLIC ||
++ pframe[WLAN_HDR_A3_LEN] == RTW_WLAN_CATEGORY_HT ||
++ pframe[WLAN_HDR_A3_LEN] == RTW_WLAN_CATEGORY_UNPROTECTED_WNM ||
++ pframe[WLAN_HDR_A3_LEN] == RTW_WLAN_CATEGORY_SELF_PROTECTED ||
++ pframe[WLAN_HDR_A3_LEN] == RTW_WLAN_CATEGORY_P2P))
++ goto xmitframe_coalesce_fail;
++ //before encrypt dump the management packet content
++ /*{
++ int i;
++ printk("Management pkt: ");
++ for(i=0; i<pattrib->pktlen; i++)
++ printk(" %02x ", pframe[i]);
++ printk("=======\n");
++ }*/
++ if(pattrib->encrypt>0)
++ _rtw_memcpy(pattrib->dot118021x_UncstKey.skey, psta->dot118021x_UncstKey.skey, 16);
++ //bakeup original management packet
++ _rtw_memcpy(tmp_buf, pframe, pattrib->pktlen);
++ //move to data portion
++ pframe += pattrib->hdrlen;
++
++ //802.11w unicast management packet must be _AES_
++ pattrib->iv_len = 8;
++ //it's MIC of AES
++ pattrib->icv_len = 8;
++
++ switch(pattrib->encrypt)
++ {
++ case _AES_:
++ //set AES IV header
++ AES_IV(pattrib->iv, psta->dot11wtxpn, 0);
++ break;
++ default:
++ goto xmitframe_coalesce_fail;
++ }
++ //insert iv header into management frame
++ _rtw_memcpy(pframe, pattrib->iv, pattrib->iv_len);
++ pframe += pattrib->iv_len;
++ //copy mgmt data portion after CCMP header
++ _rtw_memcpy(pframe, tmp_buf+pattrib->hdrlen, pattrib->pktlen-pattrib->hdrlen);
++ //move pframe to end of mgmt pkt
++ pframe += pattrib->pktlen-pattrib->hdrlen;
++ //add 8 bytes CCMP IV header to length
++ pattrib->pktlen += pattrib->iv_len;
++ /*//dump management packet include AES IV header
++ {
++ int i;
++ printk("Management pkt + IV: ");
++ //for(i=0; i<pattrib->pktlen; i++)
++ //printk(" %02x ", mem_start[i]);
++ printk("@@@@@@@@@@@@@\n");
++ }*/
++
++ if ((pattrib->icv_len >0 )&& (pattrib->bswenc)) {
++ _rtw_memcpy(pframe, pattrib->icv, pattrib->icv_len);
++ pframe += pattrib->icv_len;
++ }
++ //add 8 bytes MIC
++ pattrib->pktlen += pattrib->icv_len;
++ //set final tx command size
++ pattrib->last_txcmdsz = pattrib->pktlen;
++
++ //set protected bit must be beofre SW encrypt
++ SetPrivacy(mem_start);
++ /*//dump management packet include AES header
++ {
++ int i;
++ printk("prepare to enc Management pkt + IV: ");
++ for(i=0; i<pattrib->pktlen; i++)
++ printk(" %02x ", mem_start[i]);
++ printk("@@@@@@@@@@@@@\n");
++ }*/
++ //software encrypt
++ xmitframe_swencrypt(padapter, pxmitframe);
++ }
++ }
++
++xmitframe_coalesce_success:
++ _exit_critical_bh(&padapter->security_key_mutex, &irqL);
++ rtw_mfree(BIP_AAD, ori_len);
++_func_exit_;
++ return _SUCCESS;
++
++xmitframe_coalesce_fail:
++ _exit_critical_bh(&padapter->security_key_mutex, &irqL);
++ rtw_mfree(BIP_AAD, ori_len);
++_func_exit_;
++
++ return _FAIL;
++}
++#endif //CONFIG_IEEE80211W
++
++/* Logical Link Control(LLC) SubNetwork Attachment Point(SNAP) header
++ * IEEE LLC/SNAP header contains 8 octets
++ * First 3 octets comprise the LLC portion
++ * SNAP portion, 5 octets, is divided into two fields:
++ * Organizationally Unique Identifier(OUI), 3 octets,
++ * type, defined by that organization, 2 octets.
++ */
++s32 rtw_put_snap(u8 *data, u16 h_proto)
++{
++ struct ieee80211_snap_hdr *snap;
++ u8 *oui;
++
++_func_enter_;
++
++ snap = (struct ieee80211_snap_hdr *)data;
++ snap->dsap = 0xaa;
++ snap->ssap = 0xaa;
++ snap->ctrl = 0x03;
++
++ if (h_proto == 0x8137 || h_proto == 0x80f3)
++ oui = P802_1H_OUI;
++ else
++ oui = RFC1042_OUI;
++
++ snap->oui[0] = oui[0];
++ snap->oui[1] = oui[1];
++ snap->oui[2] = oui[2];
++
++ *(u16 *)(data + SNAP_SIZE) = htons(h_proto);
++
++_func_exit_;
++
++ return SNAP_SIZE + sizeof(u16);
++}
++
++void rtw_update_protection(_adapter *padapter, u8 *ie, uint ie_len)
++{
++
++ uint protection;
++ u8 *perp;
++ sint erp_len;
++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++ struct registry_priv *pregistrypriv = &padapter->registrypriv;
++
++_func_enter_;
++
++ switch(pxmitpriv->vcs_setting)
++ {
++ case DISABLE_VCS:
++ pxmitpriv->vcs = NONE_VCS;
++ break;
++
++ case ENABLE_VCS:
++ break;
++
++ case AUTO_VCS:
++ default:
++ perp = rtw_get_ie(ie, _ERPINFO_IE_, &erp_len, ie_len);
++ if(perp == NULL)
++ {
++ pxmitpriv->vcs = NONE_VCS;
++ }
++ else
++ {
++ protection = (*(perp + 2)) & BIT(1);
++ if (protection)
++ {
++ if(pregistrypriv->vcs_type == RTS_CTS)
++ pxmitpriv->vcs = RTS_CTS;
++ else
++ pxmitpriv->vcs = CTS_TO_SELF;
++ }
++ else
++ pxmitpriv->vcs = NONE_VCS;
++ }
++
++ break;
++
++ }
++
++_func_exit_;
++
++}
++
++void rtw_count_tx_stats(_adapter *padapter, struct xmit_frame *pxmitframe, int sz)
++{
++ struct sta_info *psta = NULL;
++ struct stainfo_stats *pstats = NULL;
++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++
++ if((pxmitframe->frame_tag&0x0f) == DATA_FRAMETAG)
++ {
++ pxmitpriv->tx_bytes += sz;
++#ifdef CONFIG_USB_TX_AGGREGATION
++ pmlmepriv->LinkDetectInfo.NumTxOkInPeriod += pxmitframe->agg_num;
++#else
++ pmlmepriv->LinkDetectInfo.NumTxOkInPeriod++;
++#endif
++
++ psta = pxmitframe->attrib.psta;
++
++ if(psta)
++ {
++ pstats = &psta->sta_stats;
++#ifdef CONFIG_USB_TX_AGGREGATION
++ pstats->tx_pkts += pxmitframe->agg_num;
++#else
++ pstats->tx_pkts++;
++#endif
++ pstats->tx_bytes += sz;
++ }
++ }
++
++}
++
++struct xmit_buf *rtw_alloc_xmitbuf_ext(struct xmit_priv *pxmitpriv)
++{
++ _irqL irqL;
++ struct xmit_buf *pxmitbuf = NULL;
++ _list *plist, *phead;
++ _queue *pfree_queue = &pxmitpriv->free_xmit_extbuf_queue;
++
++_func_enter_;
++
++ _enter_critical(&pfree_queue->lock, &irqL);
++
++ if(_rtw_queue_empty(pfree_queue) == _TRUE) {
++ pxmitbuf = NULL;
++ } else {
++
++ phead = get_list_head(pfree_queue);
++
++ plist = get_next(phead);
++
++ pxmitbuf = LIST_CONTAINOR(plist, struct xmit_buf, list);
++
++ rtw_list_delete(&(pxmitbuf->list));
++ }
++
++ if (pxmitbuf != NULL)
++ {
++ pxmitpriv->free_xmit_extbuf_cnt--;
++ #ifdef DBG_XMIT_BUF
++ DBG_871X("DBG_XMIT_BUF ALLOC no=%d, free_xmit_extbuf_cnt=%d\n",pxmitbuf->no, pxmitpriv->free_xmit_extbuf_cnt);
++ #endif
++
++
++ pxmitbuf->priv_data = NULL;
++
++#ifdef CONFIG_SDIO_HCI
++ pxmitbuf->len = 0;
++ pxmitbuf->pdata = pxmitbuf->ptail = pxmitbuf->phead;
++#endif
++#ifdef CONFIG_PCI_HCI
++ pxmitbuf->len = 0;
++#endif
++
++ if (pxmitbuf->sctx) {
++ DBG_871X("%s pxmitbuf->sctx is not NULL\n", __func__);
++ rtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_BUF_ALLOC);
++ }
++
++ }
++
++ _exit_critical(&pfree_queue->lock, &irqL);
++
++_func_exit_;
++
++ return pxmitbuf;
++}
++
++s32 rtw_free_xmitbuf_ext(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf)
++{
++ _irqL irqL;
++ _queue *pfree_queue = &pxmitpriv->free_xmit_extbuf_queue;
++
++_func_enter_;
++
++ if(pxmitbuf==NULL)
++ {
++ return _FAIL;
++ }
++
++ _enter_critical(&pfree_queue->lock, &irqL);
++
++ rtw_list_delete(&pxmitbuf->list);
++
++ rtw_list_insert_tail(&(pxmitbuf->list), get_list_head(pfree_queue));
++ pxmitpriv->free_xmit_extbuf_cnt++;
++ #ifdef DBG_XMIT_BUF
++ DBG_871X("DBG_XMIT_BUF FREE no=%d, free_xmit_extbuf_cnt=%d\n",pxmitbuf->no ,pxmitpriv->free_xmit_extbuf_cnt);
++ #endif
++
++ _exit_critical(&pfree_queue->lock, &irqL);
++
++_func_exit_;
++
++ return _SUCCESS;
++}
++
++struct xmit_buf *rtw_alloc_xmitbuf(struct xmit_priv *pxmitpriv)
++{
++ _irqL irqL;
++ struct xmit_buf *pxmitbuf = NULL;
++ _list *plist, *phead;
++ _queue *pfree_xmitbuf_queue = &pxmitpriv->free_xmitbuf_queue;
++
++_func_enter_;
++
++ //DBG_871X("+rtw_alloc_xmitbuf\n");
++
++ _enter_critical(&pfree_xmitbuf_queue->lock, &irqL);
++
++ if(_rtw_queue_empty(pfree_xmitbuf_queue) == _TRUE) {
++ pxmitbuf = NULL;
++ } else {
++
++ phead = get_list_head(pfree_xmitbuf_queue);
++
++ plist = get_next(phead);
++
++ pxmitbuf = LIST_CONTAINOR(plist, struct xmit_buf, list);
++
++ rtw_list_delete(&(pxmitbuf->list));
++ }
++
++ if (pxmitbuf != NULL)
++ {
++ pxmitpriv->free_xmitbuf_cnt--;
++ #ifdef DBG_XMIT_BUF
++ DBG_871X("DBG_XMIT_BUF ALLOC no=%d, free_xmitbuf_cnt=%d\n",pxmitbuf->no, pxmitpriv->free_xmitbuf_cnt);
++ #endif
++ //DBG_871X("alloc, free_xmitbuf_cnt=%d\n", pxmitpriv->free_xmitbuf_cnt);
++
++ pxmitbuf->priv_data = NULL;
++
++#ifdef CONFIG_SDIO_HCI
++ pxmitbuf->len = 0;
++ pxmitbuf->pdata = pxmitbuf->ptail = pxmitbuf->phead;
++#endif
++#ifdef CONFIG_PCI_HCI
++ pxmitbuf->len = 0;
++#endif
++
++ if (pxmitbuf->sctx) {
++ DBG_871X("%s pxmitbuf->sctx is not NULL\n", __func__);
++ rtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_BUF_ALLOC);
++ }
++ }
++ #ifdef DBG_XMIT_BUF
++ else
++ {
++ DBG_871X("DBG_XMIT_BUF rtw_alloc_xmitbuf return NULL\n");
++ }
++ #endif
++
++ _exit_critical(&pfree_xmitbuf_queue->lock, &irqL);
++
++_func_exit_;
++
++ return pxmitbuf;
++}
++
++s32 rtw_free_xmitbuf(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf)
++{
++ _irqL irqL;
++ _queue *pfree_xmitbuf_queue = &pxmitpriv->free_xmitbuf_queue;
++
++_func_enter_;
++
++ //DBG_871X("+rtw_free_xmitbuf\n");
++
++ if(pxmitbuf==NULL)
++ {
++ return _FAIL;
++ }
++
++ if (pxmitbuf->sctx) {
++ DBG_871X("%s pxmitbuf->sctx is not NULL\n", __func__);
++ rtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_BUF_FREE);
++ }
++
++ if(pxmitbuf->ext_tag)
++ {
++ rtw_free_xmitbuf_ext(pxmitpriv, pxmitbuf);
++ }
++ else
++ {
++ _enter_critical(&pfree_xmitbuf_queue->lock, &irqL);
++
++ rtw_list_delete(&pxmitbuf->list);
++
++ rtw_list_insert_tail(&(pxmitbuf->list), get_list_head(pfree_xmitbuf_queue));
++
++ pxmitpriv->free_xmitbuf_cnt++;
++ //DBG_871X("FREE, free_xmitbuf_cnt=%d\n", pxmitpriv->free_xmitbuf_cnt);
++ #ifdef DBG_XMIT_BUF
++ DBG_871X("DBG_XMIT_BUF FREE no=%d, free_xmitbuf_cnt=%d\n",pxmitbuf->no ,pxmitpriv->free_xmitbuf_cnt);
++ #endif
++ _exit_critical(&pfree_xmitbuf_queue->lock, &irqL);
++ }
++
++_func_exit_;
++
++ return _SUCCESS;
++}
++
++void rtw_init_xmitframe(struct xmit_frame *pxframe)
++{
++ if (pxframe != NULL)//default value setting
++ {
++ pxframe->buf_addr = NULL;
++ pxframe->pxmitbuf = NULL;
++
++ _rtw_memset(&pxframe->attrib, 0, sizeof(struct pkt_attrib));
++ //pxframe->attrib.psta = NULL;
++
++ pxframe->frame_tag = DATA_FRAMETAG;
++
++#ifdef CONFIG_USB_HCI
++ pxframe->pkt = NULL;
++ pxframe->pkt_offset = 1;//default use pkt_offset to fill tx desc
++
++#ifdef CONFIG_USB_TX_AGGREGATION
++ pxframe->agg_num = 1;
++#endif
++
++#endif //#ifdef CONFIG_USB_HCI
++
++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
++ pxframe->pg_num = 1;
++ pxframe->agg_num = 1;
++#endif
++
++#ifdef CONFIG_XMIT_ACK
++ pxframe->ack_report = 0;
++#endif
++
++ }
++}
++
++/*
++Calling context:
++1. OS_TXENTRY
++2. RXENTRY (rx_thread or RX_ISR/RX_CallBack)
++
++If we turn on USE_RXTHREAD, then, no need for critical section.
++Otherwise, we must use _enter/_exit critical to protect free_xmit_queue...
++
++Must be very very cautious...
++
++*/
++struct xmit_frame *rtw_alloc_xmitframe(struct xmit_priv *pxmitpriv)//(_queue *pfree_xmit_queue)
++{
++ /*
++ Please remember to use all the osdep_service api,
++ and lock/unlock or _enter/_exit critical to protect
++ pfree_xmit_queue
++ */
++
++ _irqL irqL;
++ struct xmit_frame *pxframe = NULL;
++ _list *plist, *phead;
++ _queue *pfree_xmit_queue = &pxmitpriv->free_xmit_queue;
++#ifdef PLATFORM_LINUX
++ _adapter *padapter = pxmitpriv->adapter;
++#endif //PLATFORM_LINUX
++
++_func_enter_;
++
++ _enter_critical_bh(&pfree_xmit_queue->lock, &irqL);
++
++ if (_rtw_queue_empty(pfree_xmit_queue) == _TRUE) {
++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("rtw_alloc_xmitframe:%d\n", pxmitpriv->free_xmitframe_cnt));
++ pxframe = NULL;
++ } else {
++ phead = get_list_head(pfree_xmit_queue);
++
++ plist = get_next(phead);
++
++ pxframe = LIST_CONTAINOR(plist, struct xmit_frame, list);
++
++ rtw_list_delete(&(pxframe->list));
++ pxmitpriv->free_xmitframe_cnt--;
++ RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_, ("rtw_alloc_xmitframe():free_xmitframe_cnt=%d\n", pxmitpriv->free_xmitframe_cnt));
++ }
++
++#ifdef PLATFORM_LINUX
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35))
++ if(pxmitpriv->free_xmitframe_cnt==1)
++ {
++ if (!rtw_netif_queue_stopped(padapter->pnetdev))
++ rtw_netif_stop_queue(padapter->pnetdev);
++ }
++#endif
++#endif
++
++ _exit_critical_bh(&pfree_xmit_queue->lock, &irqL);
++
++ rtw_init_xmitframe(pxframe);
++
++_func_exit_;
++
++ return pxframe;
++}
++
++struct xmit_frame *rtw_alloc_xmitframe_ext(struct xmit_priv *pxmitpriv)
++{
++ _irqL irqL;
++ struct xmit_frame *pxframe = NULL;
++ _list *plist, *phead;
++ _queue *queue = &pxmitpriv->free_xframe_ext_queue;
++
++_func_enter_;
++
++ _enter_critical_bh(&queue->lock, &irqL);
++
++ if (_rtw_queue_empty(queue) == _TRUE) {
++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("rtw_alloc_xmitframe_ext:%d\n", pxmitpriv->free_xframe_ext_cnt));
++ pxframe = NULL;
++ } else {
++ phead = get_list_head(queue);
++ plist = get_next(phead);
++ pxframe = LIST_CONTAINOR(plist, struct xmit_frame, list);
++
++ rtw_list_delete(&(pxframe->list));
++ pxmitpriv->free_xframe_ext_cnt--;
++ RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_, ("rtw_alloc_xmitframe_ext():free_xmitframe_cnt=%d\n", pxmitpriv->free_xframe_ext_cnt));
++ }
++
++ _exit_critical_bh(&queue->lock, &irqL);
++
++ rtw_init_xmitframe(pxframe);
++
++_func_exit_;
++
++ return pxframe;
++}
++
++struct xmit_frame *rtw_alloc_xmitframe_once(struct xmit_priv *pxmitpriv)
++{
++ struct xmit_frame *pxframe = NULL;
++ u8 *alloc_addr;
++
++ alloc_addr = rtw_zmalloc(sizeof(struct xmit_frame) + 4);
++
++ if (alloc_addr == NULL)
++ goto exit;
++
++ pxframe = (struct xmit_frame *)N_BYTE_ALIGMENT((SIZE_PTR)(alloc_addr), 4);
++ pxframe->alloc_addr = alloc_addr;
++
++ pxframe->padapter = pxmitpriv->adapter;
++ pxframe->frame_tag = NULL_FRAMETAG;
++
++ pxframe->pkt = NULL;
++
++ pxframe->buf_addr = NULL;
++ pxframe->pxmitbuf = NULL;
++
++ rtw_init_xmitframe(pxframe);
++
++ DBG_871X("################## %s ##################\n", __func__);
++
++exit:
++ return pxframe;
++}
++
++s32 rtw_free_xmitframe(struct xmit_priv *pxmitpriv, struct xmit_frame *pxmitframe)
++{
++ _irqL irqL;
++ _queue *queue;
++ _adapter *padapter = pxmitpriv->adapter;
++ _pkt *pndis_pkt = NULL;
++
++_func_enter_;
++
++ if (pxmitframe == NULL) {
++ RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("======rtw_free_xmitframe():pxmitframe==NULL!!!!!!!!!!\n"));
++ goto exit;
++ }
++
++ if (pxmitframe->pkt){
++ pndis_pkt = pxmitframe->pkt;
++ pxmitframe->pkt = NULL;
++ }
++
++ if (pxmitframe->alloc_addr) {
++ DBG_871X("################## %s with alloc_addr ##################\n", __func__);
++ rtw_mfree(pxmitframe->alloc_addr, sizeof(struct xmit_frame) + 4);
++ goto check_pkt_complete;
++ }
++
++ if (pxmitframe->ext_tag == 0)
++ queue = &pxmitpriv->free_xmit_queue;
++ else if(pxmitframe->ext_tag == 1)
++ queue = &pxmitpriv->free_xframe_ext_queue;
++ else
++ {}
++
++ _enter_critical_bh(&queue->lock, &irqL);
++
++ rtw_list_delete(&pxmitframe->list);
++ rtw_list_insert_tail(&pxmitframe->list, get_list_head(queue));
++ if (pxmitframe->ext_tag == 0) {
++ pxmitpriv->free_xmitframe_cnt++;
++ RT_TRACE(_module_rtl871x_xmit_c_, _drv_debug_, ("rtw_free_xmitframe():free_xmitframe_cnt=%d\n", pxmitpriv->free_xmitframe_cnt));
++ } else if(pxmitframe->ext_tag == 1) {
++ pxmitpriv->free_xframe_ext_cnt++;
++ RT_TRACE(_module_rtl871x_xmit_c_, _drv_debug_, ("rtw_free_xmitframe():free_xframe_ext_cnt=%d\n", pxmitpriv->free_xframe_ext_cnt));
++ } else {
++ }
++
++ _exit_critical_bh(&queue->lock, &irqL);
++
++check_pkt_complete:
++
++ if(pndis_pkt)
++ rtw_os_pkt_complete(padapter, pndis_pkt);
++
++exit:
++
++_func_exit_;
++
++ return _SUCCESS;
++}
++
++void rtw_free_xmitframe_queue(struct xmit_priv *pxmitpriv, _queue *pframequeue)
++{
++ _irqL irqL;
++ _list *plist, *phead;
++ struct xmit_frame *pxmitframe;
++
++_func_enter_;
++
++ _enter_critical_bh(&(pframequeue->lock), &irqL);
++
++ phead = get_list_head(pframequeue);
++ plist = get_next(phead);
++
++ while (rtw_end_of_queue_search(phead, plist) == _FALSE)
++ {
++
++ pxmitframe = LIST_CONTAINOR(plist, struct xmit_frame, list);
++
++ plist = get_next(plist);
++
++ rtw_free_xmitframe(pxmitpriv,pxmitframe);
++
++ }
++ _exit_critical_bh(&(pframequeue->lock), &irqL);
++
++_func_exit_;
++}
++
++s32 rtw_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe)
++{
++ if (rtw_xmit_classifier(padapter, pxmitframe) == _FAIL)
++ {
++ RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_,
++ ("rtw_xmitframe_enqueue: drop xmit pkt for classifier fail\n"));
++// pxmitframe->pkt = NULL;
++ return _FAIL;
++ }
++
++ return _SUCCESS;
++}
++
++static struct xmit_frame *dequeue_one_xmitframe(struct xmit_priv *pxmitpriv, struct hw_xmit *phwxmit, struct tx_servq *ptxservq, _queue *pframe_queue)
++{
++ _list *xmitframe_plist, *xmitframe_phead;
++ struct xmit_frame *pxmitframe=NULL;
++
++ xmitframe_phead = get_list_head(pframe_queue);
++ xmitframe_plist = get_next(xmitframe_phead);
++
++ while ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE)
++ {
++ pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list);
++
++ xmitframe_plist = get_next(xmitframe_plist);
++
++/*#ifdef RTK_DMP_PLATFORM
++#ifdef CONFIG_USB_TX_AGGREGATION
++ if((ptxservq->qcnt>0) && (ptxservq->qcnt<=2))
++ {
++ pxmitframe = NULL;
++
++ tasklet_schedule(&pxmitpriv->xmit_tasklet);
++
++ break;
++ }
++#endif
++#endif*/
++ rtw_list_delete(&pxmitframe->list);
++
++ ptxservq->qcnt--;
++
++ break;
++
++ pxmitframe = NULL;
++
++ }
++
++ return pxmitframe;
++}
++
++struct xmit_frame* rtw_dequeue_xframe(struct xmit_priv *pxmitpriv, struct hw_xmit *phwxmit_i, sint entry)
++{
++ _irqL irqL0;
++ _list *sta_plist, *sta_phead;
++ struct hw_xmit *phwxmit;
++ struct tx_servq *ptxservq = NULL;
++ _queue *pframe_queue = NULL;
++ struct xmit_frame *pxmitframe = NULL;
++ _adapter *padapter = pxmitpriv->adapter;
++ struct registry_priv *pregpriv = &padapter->registrypriv;
++ int i, inx[4];
++#ifdef CONFIG_USB_HCI
++// int j, tmp, acirp_cnt[4];
++#endif
++
++_func_enter_;
++
++ inx[0] = 0; inx[1] = 1; inx[2] = 2; inx[3] = 3;
++
++ if(pregpriv->wifi_spec==1)
++ {
++ int j, tmp, acirp_cnt[4];
++#if 0
++ if(flags<XMIT_QUEUE_ENTRY)
++ {
++ //priority exchange according to the completed xmitbuf flags.
++ inx[flags] = 0;
++ inx[0] = flags;
++ }
++#endif
++
++#ifdef CONFIG_USB_HCI
++ //entry indx: 0->vo, 1->vi, 2->be, 3->bk.
++ acirp_cnt[0] = pxmitpriv->voq_cnt;
++ acirp_cnt[1] = pxmitpriv->viq_cnt;
++ acirp_cnt[2] = pxmitpriv->beq_cnt;
++ acirp_cnt[3] = pxmitpriv->bkq_cnt;
++
++ for(i=0; i<4; i++)
++ {
++ for(j=i+1; j<4; j++)
++ {
++ if(acirp_cnt[j]<acirp_cnt[i])
++ {
++ tmp = acirp_cnt[i];
++ acirp_cnt[i] = acirp_cnt[j];
++ acirp_cnt[j] = tmp;
++
++ tmp = inx[i];
++ inx[i] = inx[j];
++ inx[j] = tmp;
++ }
++ }
++ }
++#endif
++ }
++
++ _enter_critical_bh(&pxmitpriv->lock, &irqL0);
++
++ for(i = 0; i < entry; i++)
++ {
++ phwxmit = phwxmit_i + inx[i];
++
++ //_enter_critical_ex(&phwxmit->sta_queue->lock, &irqL0);
++
++ sta_phead = get_list_head(phwxmit->sta_queue);
++ sta_plist = get_next(sta_phead);
++
++ while ((rtw_end_of_queue_search(sta_phead, sta_plist)) == _FALSE)
++ {
++
++ ptxservq= LIST_CONTAINOR(sta_plist, struct tx_servq, tx_pending);
++
++ pframe_queue = &ptxservq->sta_pending;
++
++ pxmitframe = dequeue_one_xmitframe(pxmitpriv, phwxmit, ptxservq, pframe_queue);
++
++ if(pxmitframe)
++ {
++ phwxmit->accnt--;
++
++ //Remove sta node when there is no pending packets.
++ if(_rtw_queue_empty(pframe_queue)) //must be done after get_next and before break
++ rtw_list_delete(&ptxservq->tx_pending);
++
++ //_exit_critical_ex(&phwxmit->sta_queue->lock, &irqL0);
++
++ goto exit;
++ }
++
++ sta_plist = get_next(sta_plist);
++
++ }
++
++ //_exit_critical_ex(&phwxmit->sta_queue->lock, &irqL0);
++
++ }
++
++exit:
++
++ _exit_critical_bh(&pxmitpriv->lock, &irqL0);
++
++_func_exit_;
++
++ return pxmitframe;
++}
++
++#if 1
++struct tx_servq *rtw_get_sta_pending(_adapter *padapter, struct sta_info *psta, sint up, u8 *ac)
++{
++ struct tx_servq *ptxservq=NULL;
++
++_func_enter_;
++
++ switch (up)
++ {
++ case 1:
++ case 2:
++ ptxservq = &(psta->sta_xmitpriv.bk_q);
++ *(ac) = 3;
++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("rtw_get_sta_pending : BK \n"));
++ break;
++
++ case 4:
++ case 5:
++ ptxservq = &(psta->sta_xmitpriv.vi_q);
++ *(ac) = 1;
++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("rtw_get_sta_pending : VI\n"));
++ break;
++
++ case 6:
++ case 7:
++ ptxservq = &(psta->sta_xmitpriv.vo_q);
++ *(ac) = 0;
++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("rtw_get_sta_pending : VO \n"));
++ break;
++
++ case 0:
++ case 3:
++ default:
++ ptxservq = &(psta->sta_xmitpriv.be_q);
++ *(ac) = 2;
++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("rtw_get_sta_pending : BE \n"));
++ break;
++
++ }
++
++_func_exit_;
++
++ return ptxservq;
++}
++#else
++__inline static struct tx_servq *rtw_get_sta_pending
++ (_adapter *padapter, _queue **ppstapending, struct sta_info *psta, sint up)
++{
++ struct tx_servq *ptxservq;
++ struct hw_xmit *phwxmits = padapter->xmitpriv.hwxmits;
++
++_func_enter_;
++
++#ifdef CONFIG_RTL8711
++
++ if(IS_MCAST(psta->hwaddr))
++ {
++ ptxservq = &(psta->sta_xmitpriv.be_q); // we will use be_q to queue bc/mc frames in BCMC_stainfo
++ *ppstapending = &padapter->xmitpriv.bm_pending;
++ }
++ else
++#endif
++ {
++ switch (up)
++ {
++ case 1:
++ case 2:
++ ptxservq = &(psta->sta_xmitpriv.bk_q);
++ *ppstapending = &padapter->xmitpriv.bk_pending;
++ (phwxmits+3)->accnt++;
++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("rtw_get_sta_pending : BK \n"));
++ break;
++
++ case 4:
++ case 5:
++ ptxservq = &(psta->sta_xmitpriv.vi_q);
++ *ppstapending = &padapter->xmitpriv.vi_pending;
++ (phwxmits+1)->accnt++;
++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("rtw_get_sta_pending : VI\n"));
++ break;
++
++ case 6:
++ case 7:
++ ptxservq = &(psta->sta_xmitpriv.vo_q);
++ *ppstapending = &padapter->xmitpriv.vo_pending;
++ (phwxmits+0)->accnt++;
++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("rtw_get_sta_pending : VO \n"));
++ break;
++
++ case 0:
++ case 3:
++ default:
++ ptxservq = &(psta->sta_xmitpriv.be_q);
++ *ppstapending = &padapter->xmitpriv.be_pending;
++ (phwxmits+2)->accnt++;
++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("rtw_get_sta_pending : BE \n"));
++ break;
++
++ }
++
++ }
++
++_func_exit_;
++
++ return ptxservq;
++}
++#endif
++
++/*
++ * Will enqueue pxmitframe to the proper queue,
++ * and indicate it to xx_pending list.....
++ */
++s32 rtw_xmit_classifier(_adapter *padapter, struct xmit_frame *pxmitframe)
++{
++ //_irqL irqL0;
++ u8 ac_index;
++ struct sta_info *psta;
++ struct tx_servq *ptxservq;
++ struct pkt_attrib *pattrib = &pxmitframe->attrib;
++ struct sta_priv *pstapriv = &padapter->stapriv;
++ struct hw_xmit *phwxmits = padapter->xmitpriv.hwxmits;
++ sint res = _SUCCESS;
++
++_func_enter_;
++
++ if (pattrib->psta) {
++ psta = pattrib->psta;
++ } else {
++ DBG_871X("%s, call rtw_get_stainfo()\n", __func__);
++ psta = rtw_get_stainfo(pstapriv, pattrib->ra);
++ }
++
++ if (psta == NULL) {
++ res = _FAIL;
++ DBG_8192C("rtw_xmit_classifier: psta == NULL\n");
++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("rtw_xmit_classifier: psta == NULL\n"));
++ goto exit;
++ }
++
++ if(!(psta->state &_FW_LINKED))
++ {
++ DBG_871X("%s, psta->state(0x%x) != _FW_LINKED\n", __func__, psta->state);
++ return _FAIL;
++ }
++
++ ptxservq = rtw_get_sta_pending(padapter, psta, pattrib->priority, (u8 *)(&ac_index));
++
++ //_enter_critical(&pstapending->lock, &irqL0);
++
++ if (rtw_is_list_empty(&ptxservq->tx_pending)) {
++ rtw_list_insert_tail(&ptxservq->tx_pending, get_list_head(phwxmits[ac_index].sta_queue));
++ }
++
++ //_enter_critical(&ptxservq->sta_pending.lock, &irqL1);
++
++ rtw_list_insert_tail(&pxmitframe->list, get_list_head(&ptxservq->sta_pending));
++ ptxservq->qcnt++;
++ phwxmits[ac_index].accnt++;
++
++ //_exit_critical(&ptxservq->sta_pending.lock, &irqL1);
++
++ //_exit_critical(&pstapending->lock, &irqL0);
++
++exit:
++
++_func_exit_;
++
++ return res;
++}
++
++void rtw_alloc_hwxmits(_adapter *padapter)
++{
++ struct hw_xmit *hwxmits;
++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++
++ pxmitpriv->hwxmit_entry = HWXMIT_ENTRY;
++
++ pxmitpriv->hwxmits = (struct hw_xmit *)rtw_zmalloc(sizeof (struct hw_xmit) * pxmitpriv->hwxmit_entry);
++
++ hwxmits = pxmitpriv->hwxmits;
++
++ if(pxmitpriv->hwxmit_entry == 5)
++ {
++ //pxmitpriv->bmc_txqueue.head = 0;
++ //hwxmits[0] .phwtxqueue = &pxmitpriv->bmc_txqueue;
++ hwxmits[0] .sta_queue = &pxmitpriv->bm_pending;
++
++ //pxmitpriv->vo_txqueue.head = 0;
++ //hwxmits[1] .phwtxqueue = &pxmitpriv->vo_txqueue;
++ hwxmits[1] .sta_queue = &pxmitpriv->vo_pending;
++
++ //pxmitpriv->vi_txqueue.head = 0;
++ //hwxmits[2] .phwtxqueue = &pxmitpriv->vi_txqueue;
++ hwxmits[2] .sta_queue = &pxmitpriv->vi_pending;
++
++ //pxmitpriv->bk_txqueue.head = 0;
++ //hwxmits[3] .phwtxqueue = &pxmitpriv->bk_txqueue;
++ hwxmits[3] .sta_queue = &pxmitpriv->bk_pending;
++
++ //pxmitpriv->be_txqueue.head = 0;
++ //hwxmits[4] .phwtxqueue = &pxmitpriv->be_txqueue;
++ hwxmits[4] .sta_queue = &pxmitpriv->be_pending;
++
++ }
++ else if(pxmitpriv->hwxmit_entry == 4)
++ {
++
++ //pxmitpriv->vo_txqueue.head = 0;
++ //hwxmits[0] .phwtxqueue = &pxmitpriv->vo_txqueue;
++ hwxmits[0] .sta_queue = &pxmitpriv->vo_pending;
++
++ //pxmitpriv->vi_txqueue.head = 0;
++ //hwxmits[1] .phwtxqueue = &pxmitpriv->vi_txqueue;
++ hwxmits[1] .sta_queue = &pxmitpriv->vi_pending;
++
++ //pxmitpriv->be_txqueue.head = 0;
++ //hwxmits[2] .phwtxqueue = &pxmitpriv->be_txqueue;
++ hwxmits[2] .sta_queue = &pxmitpriv->be_pending;
++
++ //pxmitpriv->bk_txqueue.head = 0;
++ //hwxmits[3] .phwtxqueue = &pxmitpriv->bk_txqueue;
++ hwxmits[3] .sta_queue = &pxmitpriv->bk_pending;
++ }
++ else
++ {
++
++
++ }
++
++
++}
++
++void rtw_free_hwxmits(_adapter *padapter)
++{
++ struct hw_xmit *hwxmits;
++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++
++ hwxmits = pxmitpriv->hwxmits;
++ if(hwxmits)
++ rtw_mfree((u8 *)hwxmits, (sizeof (struct hw_xmit) * pxmitpriv->hwxmit_entry));
++}
++
++void rtw_init_hwxmits(struct hw_xmit *phwxmit, sint entry)
++{
++ sint i;
++_func_enter_;
++ for(i = 0; i < entry; i++, phwxmit++)
++ {
++ //_rtw_spinlock_init(&phwxmit->xmit_lock);
++ //_rtw_init_listhead(&phwxmit->pending);
++ //phwxmit->txcmdcnt = 0;
++ phwxmit->accnt = 0;
++ }
++_func_exit_;
++}
++
++#ifdef CONFIG_BR_EXT
++int rtw_br_client_tx(_adapter *padapter, struct sk_buff **pskb)
++{
++ struct sk_buff *skb = *pskb;
++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++ _irqL irqL;
++ //if(check_fwstate(pmlmepriv, WIFI_STATION_STATE|WIFI_ADHOC_STATE) == _TRUE)
++ {
++ void dhcp_flag_bcast(_adapter *priv, struct sk_buff *skb);
++ int res, is_vlan_tag=0, i, do_nat25=1;
++ unsigned short vlan_hdr=0;
++ void *br_port = NULL;
++
++ //mac_clone_handle_frame(priv, skb);
++
++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35))
++ br_port = padapter->pnetdev->br_port;
++#else // (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35))
++ rcu_read_lock();
++ br_port = rcu_dereference(padapter->pnetdev->rx_handler_data);
++ rcu_read_unlock();
++#endif // (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35))
++ _enter_critical_bh(&padapter->br_ext_lock, &irqL);
++ if ( !(skb->data[0] & 1) &&
++ br_port &&
++ memcmp(skb->data+MACADDRLEN, padapter->br_mac, MACADDRLEN) &&
++ *((unsigned short *)(skb->data+MACADDRLEN*2)) != __constant_htons(ETH_P_8021Q) &&
++ *((unsigned short *)(skb->data+MACADDRLEN*2)) == __constant_htons(ETH_P_IP) &&
++ !memcmp(padapter->scdb_mac, skb->data+MACADDRLEN, MACADDRLEN) && padapter->scdb_entry) {
++ memcpy(skb->data+MACADDRLEN, GET_MY_HWADDR(padapter), MACADDRLEN);
++ padapter->scdb_entry->ageing_timer = jiffies;
++ _exit_critical_bh(&padapter->br_ext_lock, &irqL);
++ }
++ else
++ //if (!priv->pmib->ethBrExtInfo.nat25_disable)
++ {
++// if (priv->dev->br_port &&
++// !memcmp(skb->data+MACADDRLEN, priv->br_mac, MACADDRLEN)) {
++#if 1
++ if (*((unsigned short *)(skb->data+MACADDRLEN*2)) == __constant_htons(ETH_P_8021Q)) {
++ is_vlan_tag = 1;
++ vlan_hdr = *((unsigned short *)(skb->data+MACADDRLEN*2+2));
++ for (i=0; i<6; i++)
++ *((unsigned short *)(skb->data+MACADDRLEN*2+2-i*2)) = *((unsigned short *)(skb->data+MACADDRLEN*2-2-i*2));
++ skb_pull(skb, 4);
++ }
++ //if SA == br_mac && skb== IP => copy SIP to br_ip ?? why
++ if (!memcmp(skb->data+MACADDRLEN, padapter->br_mac, MACADDRLEN) &&
++ (*((unsigned short *)(skb->data+MACADDRLEN*2)) == __constant_htons(ETH_P_IP)))
++ memcpy(padapter->br_ip, skb->data+WLAN_ETHHDR_LEN+12, 4);
++
++ if (*((unsigned short *)(skb->data+MACADDRLEN*2)) == __constant_htons(ETH_P_IP)) {
++ if (memcmp(padapter->scdb_mac, skb->data+MACADDRLEN, MACADDRLEN)) {
++ void *scdb_findEntry(_adapter *priv, unsigned char *macAddr, unsigned char *ipAddr);
++
++ if ((padapter->scdb_entry = (struct nat25_network_db_entry *)scdb_findEntry(padapter,
++ skb->data+MACADDRLEN, skb->data+WLAN_ETHHDR_LEN+12)) != NULL) {
++ memcpy(padapter->scdb_mac, skb->data+MACADDRLEN, MACADDRLEN);
++ memcpy(padapter->scdb_ip, skb->data+WLAN_ETHHDR_LEN+12, 4);
++ padapter->scdb_entry->ageing_timer = jiffies;
++ do_nat25 = 0;
++ }
++ }
++ else {
++ if (padapter->scdb_entry) {
++ padapter->scdb_entry->ageing_timer = jiffies;
++ do_nat25 = 0;
++ }
++ else {
++ memset(padapter->scdb_mac, 0, MACADDRLEN);
++ memset(padapter->scdb_ip, 0, 4);
++ }
++ }
++ }
++ _exit_critical_bh(&padapter->br_ext_lock, &irqL);
++#endif // 1
++ if (do_nat25)
++ {
++ int nat25_db_handle(_adapter *priv, struct sk_buff *skb, int method);
++ if (nat25_db_handle(padapter, skb, NAT25_CHECK) == 0) {
++ struct sk_buff *newskb;
++
++ if (is_vlan_tag) {
++ skb_push(skb, 4);
++ for (i=0; i<6; i++)
++ *((unsigned short *)(skb->data+i*2)) = *((unsigned short *)(skb->data+4+i*2));
++ *((unsigned short *)(skb->data+MACADDRLEN*2)) = __constant_htons(ETH_P_8021Q);
++ *((unsigned short *)(skb->data+MACADDRLEN*2+2)) = vlan_hdr;
++ }
++
++ newskb = rtw_skb_copy(skb);
++ if (newskb == NULL) {
++ //priv->ext_stats.tx_drops++;
++ DEBUG_ERR("TX DROP: rtw_skb_copy fail!\n");
++ //goto stop_proc;
++ return -1;
++ }
++ rtw_skb_free(skb);
++
++ *pskb = skb = newskb;
++ if (is_vlan_tag) {
++ vlan_hdr = *((unsigned short *)(skb->data+MACADDRLEN*2+2));
++ for (i=0; i<6; i++)
++ *((unsigned short *)(skb->data+MACADDRLEN*2+2-i*2)) = *((unsigned short *)(skb->data+MACADDRLEN*2-2-i*2));
++ skb_pull(skb, 4);
++ }
++ }
++
++ if (skb_is_nonlinear(skb))
++ DEBUG_ERR("%s(): skb_is_nonlinear!!\n", __FUNCTION__);
++
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18))
++ res = skb_linearize(skb, GFP_ATOMIC);
++#else // (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18))
++ res = skb_linearize(skb);
++#endif // (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18))
++ if (res < 0) {
++ DEBUG_ERR("TX DROP: skb_linearize fail!\n");
++ //goto free_and_stop;
++ return -1;
++ }
++
++ res = nat25_db_handle(padapter, skb, NAT25_INSERT);
++ if (res < 0) {
++ if (res == -2) {
++ //priv->ext_stats.tx_drops++;
++ DEBUG_ERR("TX DROP: nat25_db_handle fail!\n");
++ //goto free_and_stop;
++ return -1;
++
++ }
++ // we just print warning message and let it go
++ //DEBUG_WARN("%s()-%d: nat25_db_handle INSERT Warning!\n", __FUNCTION__, __LINE__);
++ //return -1; // return -1 will cause system crash on 2011/08/30!
++ return 0;
++ }
++ }
++
++ memcpy(skb->data+MACADDRLEN, GET_MY_HWADDR(padapter), MACADDRLEN);
++
++ dhcp_flag_bcast(padapter, skb);
++
++ if (is_vlan_tag) {
++ skb_push(skb, 4);
++ for (i=0; i<6; i++)
++ *((unsigned short *)(skb->data+i*2)) = *((unsigned short *)(skb->data+4+i*2));
++ *((unsigned short *)(skb->data+MACADDRLEN*2)) = __constant_htons(ETH_P_8021Q);
++ *((unsigned short *)(skb->data+MACADDRLEN*2+2)) = vlan_hdr;
++ }
++ }
++#if 0
++ else{
++ if (*((unsigned short *)(skb->data+MACADDRLEN*2)) == __constant_htons(ETH_P_8021Q)) {
++ is_vlan_tag = 1;
++ }
++
++ if(is_vlan_tag){
++ if(ICMPV6_MCAST_MAC(skb->data) && ICMPV6_PROTO1A_VALN(skb->data)){
++ memcpy(skb->data+MACADDRLEN, GET_MY_HWADDR(padapter), MACADDRLEN);
++ }
++ }else
++ {
++ if(ICMPV6_MCAST_MAC(skb->data) && ICMPV6_PROTO1A(skb->data)){
++ memcpy(skb->data+MACADDRLEN, GET_MY_HWADDR(padapter), MACADDRLEN);
++ }
++ }
++ }
++#endif // 0
++
++ // check if SA is equal to our MAC
++ if (memcmp(skb->data+MACADDRLEN, GET_MY_HWADDR(padapter), MACADDRLEN)) {
++ //priv->ext_stats.tx_drops++;
++ DEBUG_ERR("TX DROP: untransformed frame SA:%02X%02X%02X%02X%02X%02X!\n",
++ skb->data[6],skb->data[7],skb->data[8],skb->data[9],skb->data[10],skb->data[11]);
++ //goto free_and_stop;
++ return -1;
++ }
++ }
++ return 0;
++}
++#endif // CONFIG_BR_EXT
++
++static void do_queue_select(_adapter *padapter, struct pkt_attrib *pattrib)
++{
++ u8 qsel;
++
++ qsel = pattrib->priority;
++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("### do_queue_select priority=%d ,qsel = %d\n",pattrib->priority ,qsel));
++
++#ifdef CONFIG_CONCURRENT_MODE
++// if (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE)
++// qsel = 7;//
++#endif
++
++ pattrib->qsel = qsel;
++}
++
++/*
++ * The main transmit(tx) entry
++ *
++ * Return
++ * 1 enqueue
++ * 0 success, hardware will handle this xmit frame(packet)
++ * <0 fail
++ */
++s32 rtw_xmit(_adapter *padapter, _pkt **ppkt)
++{
++ static u32 start = 0;
++ static u32 drop_cnt = 0;
++#ifdef CONFIG_AP_MODE
++ _irqL irqL0;
++#endif
++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++ struct xmit_frame *pxmitframe = NULL;
++#ifdef CONFIG_BR_EXT
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ void *br_port = NULL;
++#endif // CONFIG_BR_EXT
++
++ s32 res;
++
++ if (start == 0)
++ start = rtw_get_current_time();
++
++ pxmitframe = rtw_alloc_xmitframe(pxmitpriv);
++
++ if (rtw_get_passing_time_ms(start) > 2000) {
++ if (drop_cnt)
++ DBG_871X("DBG_TX_DROP_FRAME %s no more pxmitframe, drop_cnt:%u\n", __FUNCTION__, drop_cnt);
++ start = rtw_get_current_time();
++ drop_cnt = 0;
++ }
++
++ if (pxmitframe == NULL) {
++ drop_cnt ++;
++ RT_TRACE(_module_xmit_osdep_c_, _drv_err_, ("rtw_xmit: no more pxmitframe\n"));
++ return -1;
++ }
++
++#ifdef CONFIG_BR_EXT
++
++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35))
++ br_port = padapter->pnetdev->br_port;
++#else // (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35))
++ rcu_read_lock();
++ br_port = rcu_dereference(padapter->pnetdev->rx_handler_data);
++ rcu_read_unlock();
++#endif // (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35))
++
++ if( br_port && check_fwstate(pmlmepriv, WIFI_STATION_STATE|WIFI_ADHOC_STATE) == _TRUE)
++ {
++ res = rtw_br_client_tx(padapter, ppkt);
++ if (res == -1)
++ {
++ rtw_free_xmitframe(pxmitpriv, pxmitframe);
++ return -1;
++ }
++ }
++
++#endif // CONFIG_BR_EXT
++
++ res = update_attrib(padapter, *ppkt, &pxmitframe->attrib);
++ if (res == _FAIL) {
++ RT_TRACE(_module_xmit_osdep_c_, _drv_err_, ("rtw_xmit: update attrib fail\n"));
++ #ifdef DBG_TX_DROP_FRAME
++ DBG_871X("DBG_TX_DROP_FRAME %s update attrib fail\n", __FUNCTION__);
++ #endif
++ rtw_free_xmitframe(pxmitpriv, pxmitframe);
++ return -1;
++ }
++ pxmitframe->pkt = *ppkt;
++
++ rtw_led_control(padapter, LED_CTL_TX);
++
++ do_queue_select(padapter, &pxmitframe->attrib);
++
++#if defined(CONFIG_AP_MODE) || defined(CONFIG_TDLS)
++ _enter_critical_bh(&pxmitpriv->lock, &irqL0);
++ if(xmitframe_enqueue_for_sleeping_sta(padapter, pxmitframe) == _TRUE)
++ {
++ _exit_critical_bh(&pxmitpriv->lock, &irqL0);
++ return 1;
++ }
++ _exit_critical_bh(&pxmitpriv->lock, &irqL0);
++#endif
++
++ if (rtw_hal_xmit(padapter, pxmitframe) == _FALSE)
++ return 1;
++
++ return 0;
++}
++
++#ifdef CONFIG_TDLS
++sint xmitframe_enqueue_for_tdls_sleeping_sta(_adapter *padapter, struct xmit_frame *pxmitframe)
++{
++ sint ret=_FALSE;
++
++ _irqL irqL;
++ struct sta_info *ptdls_sta=NULL;
++ struct sta_priv *pstapriv = &padapter->stapriv;
++ struct pkt_attrib *pattrib = &pxmitframe->attrib;
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++ int i;
++
++ ptdls_sta=rtw_get_stainfo(pstapriv, pattrib->dst);
++ if(ptdls_sta==NULL){
++ return ret;
++ }else if(ptdls_sta->tdls_sta_state&TDLS_LINKED_STATE){
++
++ if(pattrib->triggered==1)
++ {
++ ret = _TRUE;
++ return ret;
++ }
++
++ _enter_critical_bh(&ptdls_sta->sleep_q.lock, &irqL);
++
++ if(ptdls_sta->state&WIFI_SLEEP_STATE)
++ {
++ rtw_list_delete(&pxmitframe->list);
++
++ //_enter_critical_bh(&psta->sleep_q.lock, &irqL);
++
++ rtw_list_insert_tail(&pxmitframe->list, get_list_head(&ptdls_sta->sleep_q));
++
++ ptdls_sta->sleepq_len++;
++ ptdls_sta->sleepq_ac_len++;
++
++ //indicate 4-AC queue bit in TDLS peer traffic indication
++ switch(pattrib->priority)
++ {
++ case 1:
++ case 2:
++ ptdls_sta->uapsd_bk = ptdls_sta->uapsd_bk | BIT(1);
++ break;
++ case 4:
++ case 5:
++ ptdls_sta->uapsd_vi = ptdls_sta->uapsd_vi | BIT(1);
++ break;
++ case 6:
++ case 7:
++ ptdls_sta->uapsd_vo = ptdls_sta->uapsd_vo | BIT(1);
++ break;
++ case 0:
++ case 3:
++ default:
++ ptdls_sta->uapsd_be = ptdls_sta->uapsd_be | BIT(1);
++ break;
++ }
++
++ if(ptdls_sta->sleepq_len==1)
++ {
++ //transmit TDLS PTI via AP
++ rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_SD_PTI);
++ }
++ ret = _TRUE;
++
++ }
++
++ _exit_critical_bh(&ptdls_sta->sleep_q.lock, &irqL);
++ }
++
++ return ret;
++
++}
++#endif //CONFIG_TDLS
++
++#if defined(CONFIG_AP_MODE) || defined(CONFIG_TDLS)
++
++sint xmitframe_enqueue_for_sleeping_sta(_adapter *padapter, struct xmit_frame *pxmitframe)
++{
++ _irqL irqL;
++ sint ret=_FALSE;
++ struct sta_info *psta=NULL;
++ struct sta_priv *pstapriv = &padapter->stapriv;
++ struct pkt_attrib *pattrib = &pxmitframe->attrib;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ sint bmcst = IS_MCAST(pattrib->ra);
++#ifdef CONFIG_TDLS
++ struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
++
++ if( ptdlsinfo->setup_state == TDLS_LINKED_STATE )
++ {
++ ret = xmitframe_enqueue_for_tdls_sleeping_sta(padapter, pxmitframe);
++ return ret;
++ }
++#endif //CONFIG_TDLS
++
++ if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _FALSE)
++ return ret;
++
++ if(pattrib->psta)
++ {
++ psta = pattrib->psta;
++ }
++ else
++ {
++ DBG_871X("%s, call rtw_get_stainfo()\n", __func__);
++ psta=rtw_get_stainfo(pstapriv, pattrib->ra);
++ }
++
++ if(psta==NULL)
++ {
++ DBG_871X("%s, psta==NUL\n", __func__);
++ return _FALSE;
++ }
++
++ if(!(psta->state &_FW_LINKED))
++ {
++ DBG_871X("%s, psta->state(0x%x) != _FW_LINKED\n", __func__, psta->state);
++ return _FALSE;
++ }
++
++ if(pattrib->triggered==1)
++ {
++ //DBG_871X("directly xmit pspoll_triggered packet\n");
++
++ //pattrib->triggered=0;
++
++ if(bmcst)
++ pattrib->qsel = 0x11;//HIQ
++
++
++ return ret;
++ }
++
++
++ if(bmcst)
++ {
++ _enter_critical_bh(&psta->sleep_q.lock, &irqL);
++
++ if(pstapriv->sta_dz_bitmap)//if anyone sta is in ps mode
++ {
++ //pattrib->qsel = 0x11;//HIQ
++
++ rtw_list_delete(&pxmitframe->list);
++
++ //_enter_critical_bh(&psta->sleep_q.lock, &irqL);
++
++ rtw_list_insert_tail(&pxmitframe->list, get_list_head(&psta->sleep_q));
++
++ psta->sleepq_len++;
++
++ pstapriv->tim_bitmap |= BIT(0);//
++ pstapriv->sta_dz_bitmap |= BIT(0);
++
++ //DBG_871X("enqueue, sq_len=%d, tim=%x\n", psta->sleepq_len, pstapriv->tim_bitmap);
++
++ update_beacon(padapter, _TIM_IE_, NULL, _FALSE);//tx bc/mc packets after upate bcn
++
++ //_exit_critical_bh(&psta->sleep_q.lock, &irqL);
++
++ ret = _TRUE;
++
++ }
++
++ _exit_critical_bh(&psta->sleep_q.lock, &irqL);
++
++ return ret;
++
++ }
++
++
++ _enter_critical_bh(&psta->sleep_q.lock, &irqL);
++
++ if(psta->state&WIFI_SLEEP_STATE)
++ {
++ u8 wmmps_ac=0;
++
++ if(pstapriv->sta_dz_bitmap&BIT(psta->aid))
++ {
++ rtw_list_delete(&pxmitframe->list);
++
++ //_enter_critical_bh(&psta->sleep_q.lock, &irqL);
++
++ rtw_list_insert_tail(&pxmitframe->list, get_list_head(&psta->sleep_q));
++
++ psta->sleepq_len++;
++
++ switch(pattrib->priority)
++ {
++ case 1:
++ case 2:
++ wmmps_ac = psta->uapsd_bk&BIT(0);
++ break;
++ case 4:
++ case 5:
++ wmmps_ac = psta->uapsd_vi&BIT(0);
++ break;
++ case 6:
++ case 7:
++ wmmps_ac = psta->uapsd_vo&BIT(0);
++ break;
++ case 0:
++ case 3:
++ default:
++ wmmps_ac = psta->uapsd_be&BIT(0);
++ break;
++ }
++
++ if(wmmps_ac)
++ psta->sleepq_ac_len++;
++
++ if(((psta->has_legacy_ac) && (!wmmps_ac)) ||((!psta->has_legacy_ac)&&(wmmps_ac)))
++ {
++ pstapriv->tim_bitmap |= BIT(psta->aid);
++
++ //DBG_871X("enqueue, sq_len=%d, tim=%x\n", psta->sleepq_len, pstapriv->tim_bitmap);
++
++ if(psta->sleepq_len==1)
++ {
++ //DBG_871X("sleepq_len==1, update BCNTIM\n");
++ //upate BCN for TIM IE
++ update_beacon(padapter, _TIM_IE_, NULL, _FALSE);
++ }
++ }
++
++ //_exit_critical_bh(&psta->sleep_q.lock, &irqL);
++
++ //if(psta->sleepq_len > (NR_XMITFRAME>>3))
++ //{
++ // wakeup_sta_to_xmit(padapter, psta);
++ //}
++
++ ret = _TRUE;
++
++ }
++
++ }
++
++ _exit_critical_bh(&psta->sleep_q.lock, &irqL);
++
++ return ret;
++
++}
++
++static void dequeue_xmitframes_to_sleeping_queue(_adapter *padapter, struct sta_info *psta, _queue *pframequeue)
++{
++ sint ret;
++ _list *plist, *phead;
++ u8 ac_index;
++ struct tx_servq *ptxservq;
++ struct pkt_attrib *pattrib;
++ struct xmit_frame *pxmitframe;
++ struct hw_xmit *phwxmits = padapter->xmitpriv.hwxmits;
++
++ phead = get_list_head(pframequeue);
++ plist = get_next(phead);
++
++ while (rtw_end_of_queue_search(phead, plist) == _FALSE)
++ {
++ pxmitframe = LIST_CONTAINOR(plist, struct xmit_frame, list);
++
++ plist = get_next(plist);
++
++ ret = xmitframe_enqueue_for_sleeping_sta(padapter, pxmitframe);
++
++ if(_TRUE == ret)
++ {
++ pattrib = &pxmitframe->attrib;
++
++ ptxservq = rtw_get_sta_pending(padapter, psta, pattrib->priority, (u8 *)(&ac_index));
++
++ ptxservq->qcnt--;
++ phwxmits[ac_index].accnt--;
++ }
++ else
++ {
++ //DBG_871X("xmitframe_enqueue_for_sleeping_sta return _FALSE\n");
++ }
++
++ }
++
++}
++
++void stop_sta_xmit(_adapter *padapter, struct sta_info *psta)
++{
++ _irqL irqL0;
++ struct sta_info *psta_bmc;
++ struct sta_xmit_priv *pstaxmitpriv;
++ struct sta_priv *pstapriv = &padapter->stapriv;
++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++
++ pstaxmitpriv = &psta->sta_xmitpriv;
++
++ //for BC/MC Frames
++ psta_bmc = rtw_get_bcmc_stainfo(padapter);
++
++
++ _enter_critical_bh(&pxmitpriv->lock, &irqL0);
++
++ psta->state |= WIFI_SLEEP_STATE;
++
++#ifdef CONFIG_TDLS
++ if( !(psta->tdls_sta_state & TDLS_LINKED_STATE) )
++#endif //CONFIG_TDLS
++ pstapriv->sta_dz_bitmap |= BIT(psta->aid);
++
++
++
++ dequeue_xmitframes_to_sleeping_queue(padapter, psta, &pstaxmitpriv->vo_q.sta_pending);
++ rtw_list_delete(&(pstaxmitpriv->vo_q.tx_pending));
++
++
++ dequeue_xmitframes_to_sleeping_queue(padapter, psta, &pstaxmitpriv->vi_q.sta_pending);
++ rtw_list_delete(&(pstaxmitpriv->vi_q.tx_pending));
++
++
++ dequeue_xmitframes_to_sleeping_queue(padapter, psta, &pstaxmitpriv->be_q.sta_pending);
++ rtw_list_delete(&(pstaxmitpriv->be_q.tx_pending));
++
++
++ dequeue_xmitframes_to_sleeping_queue(padapter, psta, &pstaxmitpriv->bk_q.sta_pending);
++ rtw_list_delete(&(pstaxmitpriv->bk_q.tx_pending));
++
++#ifdef CONFIG_TDLS
++ if( !(psta->tdls_sta_state & TDLS_LINKED_STATE) )
++ {
++ if( psta_bmc != NULL )
++ {
++#endif //CONFIG_TDLS
++
++
++ //for BC/MC Frames
++ pstaxmitpriv = &psta_bmc->sta_xmitpriv;
++ dequeue_xmitframes_to_sleeping_queue(padapter, psta_bmc, &pstaxmitpriv->be_q.sta_pending);
++ rtw_list_delete(&(pstaxmitpriv->be_q.tx_pending));
++
++
++#ifdef CONFIG_TDLS
++ }
++ }
++#endif //CONFIG_TDLS
++ _exit_critical_bh(&pxmitpriv->lock, &irqL0);
++
++
++}
++
++void wakeup_sta_to_xmit(_adapter *padapter, struct sta_info *psta)
++{
++ _irqL irqL;
++ u8 update_mask=0, wmmps_ac=0;
++ struct sta_info *psta_bmc;
++ _list *xmitframe_plist, *xmitframe_phead;
++ struct xmit_frame *pxmitframe=NULL;
++ struct sta_priv *pstapriv = &padapter->stapriv;
++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++
++ psta_bmc = rtw_get_bcmc_stainfo(padapter);
++
++
++ //_enter_critical_bh(&psta->sleep_q.lock, &irqL);
++ _enter_critical_bh(&pxmitpriv->lock, &irqL);
++
++ xmitframe_phead = get_list_head(&psta->sleep_q);
++ xmitframe_plist = get_next(xmitframe_phead);
++
++ while ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE)
++ {
++ pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list);
++
++ xmitframe_plist = get_next(xmitframe_plist);
++
++ rtw_list_delete(&pxmitframe->list);
++
++ switch(pxmitframe->attrib.priority)
++ {
++ case 1:
++ case 2:
++ wmmps_ac = psta->uapsd_bk&BIT(1);
++ break;
++ case 4:
++ case 5:
++ wmmps_ac = psta->uapsd_vi&BIT(1);
++ break;
++ case 6:
++ case 7:
++ wmmps_ac = psta->uapsd_vo&BIT(1);
++ break;
++ case 0:
++ case 3:
++ default:
++ wmmps_ac = psta->uapsd_be&BIT(1);
++ break;
++ }
++
++ psta->sleepq_len--;
++ if(psta->sleepq_len>0)
++ pxmitframe->attrib.mdata = 1;
++ else
++ pxmitframe->attrib.mdata = 0;
++
++ if(wmmps_ac)
++ {
++ psta->sleepq_ac_len--;
++ if(psta->sleepq_ac_len>0)
++ {
++ pxmitframe->attrib.mdata = 1;
++ pxmitframe->attrib.eosp = 0;
++ }
++ else
++ {
++ pxmitframe->attrib.mdata = 0;
++ pxmitframe->attrib.eosp = 1;
++ }
++ }
++
++ pxmitframe->attrib.triggered = 1;
++
++/*
++ _exit_critical_bh(&psta->sleep_q.lock, &irqL);
++ if(rtw_hal_xmit(padapter, pxmitframe) == _TRUE)
++ {
++ rtw_os_xmit_complete(padapter, pxmitframe);
++ }
++ _enter_critical_bh(&psta->sleep_q.lock, &irqL);
++*/
++ rtw_hal_xmitframe_enqueue(padapter, pxmitframe);
++
++
++ }
++
++ //for BC/MC Frames
++ if(!psta_bmc)
++ goto _exit;
++
++ if((pstapriv->sta_dz_bitmap&0xfffe) == 0x0)//no any sta in ps mode
++ {
++ xmitframe_phead = get_list_head(&psta_bmc->sleep_q);
++ xmitframe_plist = get_next(xmitframe_phead);
++
++ while ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE)
++ {
++ pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list);
++
++ xmitframe_plist = get_next(xmitframe_plist);
++
++ rtw_list_delete(&pxmitframe->list);
++
++ psta_bmc->sleepq_len--;
++ if(psta_bmc->sleepq_len>0)
++ pxmitframe->attrib.mdata = 1;
++ else
++ pxmitframe->attrib.mdata = 0;
++
++
++ pxmitframe->attrib.triggered = 1;
++/*
++ _exit_critical_bh(&psta_bmc->sleep_q.lock, &irqL);
++ if(rtw_hal_xmit(padapter, pxmitframe) == _TRUE)
++ {
++ rtw_os_xmit_complete(padapter, pxmitframe);
++ }
++ _enter_critical_bh(&psta_bmc->sleep_q.lock, &irqL);
++
++*/
++ rtw_hal_xmitframe_enqueue(padapter, pxmitframe);
++
++ }
++
++ if(psta_bmc->sleepq_len==0)
++ {
++ pstapriv->tim_bitmap &= ~BIT(0);
++ pstapriv->sta_dz_bitmap &= ~BIT(0);
++
++ //DBG_871X("wakeup to xmit, qlen==0, update_BCNTIM, tim=%x\n", pstapriv->tim_bitmap);
++ //upate BCN for TIM IE
++ //update_BCNTIM(padapter);
++ update_mask |= BIT(1);
++ }
++
++ }
++
++ if(psta->sleepq_len==0)
++ {
++#ifdef CONFIG_TDLS
++ if( psta->tdls_sta_state & TDLS_LINKED_STATE )
++ {
++ if(psta->state&WIFI_SLEEP_STATE)
++ psta->state ^= WIFI_SLEEP_STATE;
++
++ goto _exit;
++ }
++#endif //CONFIG_TDLS
++ pstapriv->tim_bitmap &= ~BIT(psta->aid);
++
++ //DBG_871X("wakeup to xmit, qlen==0, update_BCNTIM, tim=%x\n", pstapriv->tim_bitmap);
++ //upate BCN for TIM IE
++ //update_BCNTIM(padapter);
++ update_mask = BIT(0);
++
++ if(psta->state&WIFI_SLEEP_STATE)
++ psta->state ^= WIFI_SLEEP_STATE;
++
++ if(psta->state & WIFI_STA_ALIVE_CHK_STATE)
++ {
++ psta->expire_to = pstapriv->expire_to;
++ psta->state ^= WIFI_STA_ALIVE_CHK_STATE;
++ }
++
++ pstapriv->sta_dz_bitmap &= ~BIT(psta->aid);
++ }
++
++_exit:
++
++ //_exit_critical_bh(&psta_bmc->sleep_q.lock, &irqL);
++ _exit_critical_bh(&pxmitpriv->lock, &irqL);
++
++ if(update_mask)
++ {
++ //update_BCNTIM(padapter);
++ //printk("%s => call update_beacon\n",__FUNCTION__);
++ update_beacon(padapter, _TIM_IE_, NULL, _FALSE);
++ }
++
++}
++
++void xmit_delivery_enabled_frames(_adapter *padapter, struct sta_info *psta)
++{
++ _irqL irqL;
++ u8 wmmps_ac=0;
++ _list *xmitframe_plist, *xmitframe_phead;
++ struct xmit_frame *pxmitframe=NULL;
++ struct sta_priv *pstapriv = &padapter->stapriv;
++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++
++
++ //_enter_critical_bh(&psta->sleep_q.lock, &irqL);
++ _enter_critical_bh(&pxmitpriv->lock, &irqL);
++
++ xmitframe_phead = get_list_head(&psta->sleep_q);
++ xmitframe_plist = get_next(xmitframe_phead);
++
++ while ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE)
++ {
++ pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list);
++
++ xmitframe_plist = get_next(xmitframe_plist);
++
++ switch(pxmitframe->attrib.priority)
++ {
++ case 1:
++ case 2:
++ wmmps_ac = psta->uapsd_bk&BIT(1);
++ break;
++ case 4:
++ case 5:
++ wmmps_ac = psta->uapsd_vi&BIT(1);
++ break;
++ case 6:
++ case 7:
++ wmmps_ac = psta->uapsd_vo&BIT(1);
++ break;
++ case 0:
++ case 3:
++ default:
++ wmmps_ac = psta->uapsd_be&BIT(1);
++ break;
++ }
++
++ if(!wmmps_ac)
++ continue;
++
++ rtw_list_delete(&pxmitframe->list);
++
++ psta->sleepq_len--;
++ psta->sleepq_ac_len--;
++
++ if(psta->sleepq_ac_len>0)
++ {
++ pxmitframe->attrib.mdata = 1;
++ pxmitframe->attrib.eosp = 0;
++ }
++ else
++ {
++ pxmitframe->attrib.mdata = 0;
++ pxmitframe->attrib.eosp = 1;
++ }
++
++ pxmitframe->attrib.triggered = 1;
++
++/*
++ if(rtw_hal_xmit(padapter, pxmitframe) == _TRUE)
++ {
++ rtw_os_xmit_complete(padapter, pxmitframe);
++ }
++*/
++ rtw_hal_xmitframe_enqueue(padapter, pxmitframe);
++
++ if((psta->sleepq_ac_len==0) && (!psta->has_legacy_ac) && (wmmps_ac))
++ {
++#ifdef CONFIG_TDLS
++ if(psta->tdls_sta_state & TDLS_LINKED_STATE )
++ {
++ //_exit_critical_bh(&psta->sleep_q.lock, &irqL);
++ _exit_critical_bh(&pxmitpriv->lock, &irqL);
++ return;
++ }
++#endif //CONFIG_TDLS
++ pstapriv->tim_bitmap &= ~BIT(psta->aid);
++
++ //DBG_871X("wakeup to xmit, qlen==0, update_BCNTIM, tim=%x\n", pstapriv->tim_bitmap);
++ //upate BCN for TIM IE
++ //update_BCNTIM(padapter);
++ update_beacon(padapter, _TIM_IE_, NULL, _FALSE);
++ //update_mask = BIT(0);
++ }
++
++ }
++
++ //_exit_critical_bh(&psta->sleep_q.lock, &irqL);
++ _exit_critical_bh(&pxmitpriv->lock, &irqL);
++
++}
++
++#endif
++
++void rtw_sctx_init(struct submit_ctx *sctx, int timeout_ms)
++{
++ sctx->timeout_ms = timeout_ms;
++ sctx->submit_time= rtw_get_current_time();
++#ifdef PLATFORM_LINUX /* TODO: add condition wating interface for other os */
++ init_completion(&sctx->done);
++#endif
++ sctx->status = RTW_SCTX_SUBMITTED;
++}
++
++int rtw_sctx_wait(struct submit_ctx *sctx)
++{
++ int ret = _FAIL;
++ unsigned long expire;
++ int status = 0;
++
++#ifdef PLATFORM_LINUX
++ expire= sctx->timeout_ms ? msecs_to_jiffies(sctx->timeout_ms) : MAX_SCHEDULE_TIMEOUT;
++ if (!wait_for_completion_timeout(&sctx->done, expire)) {
++ /* timeout, do something?? */
++ status = RTW_SCTX_DONE_TIMEOUT;
++ DBG_871X("%s timeout\n", __func__);
++ } else {
++ status = sctx->status;
++ }
++#endif
++
++ if (status == RTW_SCTX_DONE_SUCCESS) {
++ ret = _SUCCESS;
++ }
++
++ return ret;
++}
++
++bool rtw_sctx_chk_waring_status(int status)
++{
++ switch(status) {
++ case RTW_SCTX_DONE_UNKNOWN:
++ case RTW_SCTX_DONE_BUF_ALLOC:
++ case RTW_SCTX_DONE_BUF_FREE:
++
++ case RTW_SCTX_DONE_DRV_STOP:
++ case RTW_SCTX_DONE_DEV_REMOVE:
++ return _TRUE;
++ default:
++ return _FALSE;
++ }
++}
++
++void rtw_sctx_done_err(struct submit_ctx **sctx, int status)
++{
++ if (*sctx) {
++ if (rtw_sctx_chk_waring_status(status))
++ DBG_871X("%s status:%d\n", __func__, status);
++ (*sctx)->status = status;
++ #ifdef PLATFORM_LINUX
++ complete(&((*sctx)->done));
++ #endif
++ *sctx = NULL;
++ }
++}
++
++void rtw_sctx_done(struct submit_ctx **sctx)
++{
++ rtw_sctx_done_err(sctx, RTW_SCTX_DONE_SUCCESS);
++}
++
++#ifdef CONFIG_XMIT_ACK
++
++#ifdef CONFIG_XMIT_ACK_POLLING
++s32 c2h_evt_hdl(_adapter *adapter, struct c2h_evt_hdr *c2h_evt, c2h_id_filter filter);
++
++/**
++ * rtw_ack_tx_polling -
++ * @pxmitpriv: xmit_priv to address ack_tx_ops
++ * @timeout_ms: timeout msec
++ *
++ * Init ack_tx_ops and then do c2h_evt_hdl() and polling ack_tx_ops repeatedly
++ * till tx report or timeout
++ * Returns: _SUCCESS if TX report ok, _FAIL for others
++ */
++int rtw_ack_tx_polling(struct xmit_priv *pxmitpriv, u32 timeout_ms)
++{
++ int ret = _FAIL;
++ struct submit_ctx *pack_tx_ops = &pxmitpriv->ack_tx_ops;
++ _adapter *adapter = container_of(pxmitpriv, _adapter, xmitpriv);
++
++ pack_tx_ops->submit_time = rtw_get_current_time();
++ pack_tx_ops->timeout_ms = timeout_ms;
++ pack_tx_ops->status = RTW_SCTX_SUBMITTED;
++
++ do {
++ c2h_evt_hdl(adapter, NULL, rtw_hal_c2h_id_filter_ccx(adapter));
++ if (pack_tx_ops->status != RTW_SCTX_SUBMITTED)
++ break;
++
++ if (adapter->bDriverStopped) {
++ pack_tx_ops->status = RTW_SCTX_DONE_DRV_STOP;
++ break;
++ }
++ if (adapter->bSurpriseRemoved) {
++ pack_tx_ops->status = RTW_SCTX_DONE_DEV_REMOVE;
++ break;
++ }
++
++ rtw_msleep_os(10);
++ } while (rtw_get_passing_time_ms(pack_tx_ops->submit_time) < timeout_ms);
++
++ if (pack_tx_ops->status == RTW_SCTX_SUBMITTED) {
++ pack_tx_ops->status = RTW_SCTX_DONE_TIMEOUT;
++ DBG_871X("%s timeout\n", __func__);
++ }
++
++ if (pack_tx_ops->status == RTW_SCTX_DONE_SUCCESS)
++ ret = _SUCCESS;
++
++ return ret;
++}
++#endif
++
++int rtw_ack_tx_wait(struct xmit_priv *pxmitpriv, u32 timeout_ms)
++{
++#ifdef CONFIG_XMIT_ACK_POLLING
++ return rtw_ack_tx_polling(pxmitpriv, timeout_ms);
++#else
++ struct submit_ctx *pack_tx_ops = &pxmitpriv->ack_tx_ops;
++
++ pack_tx_ops->submit_time = rtw_get_current_time();
++ pack_tx_ops->timeout_ms = timeout_ms;
++ pack_tx_ops->status = RTW_SCTX_SUBMITTED;
++
++ return rtw_sctx_wait(pack_tx_ops);
++#endif
++}
++
++void rtw_ack_tx_done(struct xmit_priv *pxmitpriv, int status)
++{
++ struct submit_ctx *pack_tx_ops = &pxmitpriv->ack_tx_ops;
++
++ if (pxmitpriv->ack_tx) {
++ rtw_sctx_done_err(&pack_tx_ops, status);
++ } else {
++ DBG_871X("%s ack_tx not set\n", __func__);
++ }
++}
++#endif //CONFIG_XMIT_ACK
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/hal/dm.c linux-xbian-rpi/drivers/net/wireless/rtl8192cu/hal/dm.c
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/hal/dm.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/hal/dm.c 2015-07-28 01:20:58.305654202 +0200
+@@ -0,0 +1,313 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2013 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++
++#ifdef CONFIG_RTL8192C
++#include <rtl8192c_hal.h>
++#endif
++
++#ifdef CONFIG_RTL8192D
++#include <rtl8192d_hal.h>
++#endif
++
++bool rtw_adapter_linked(_adapter *adapter)
++{
++ bool linked = _FALSE;
++ struct mlme_priv *mlmepriv = &adapter->mlmepriv;
++
++ if( (check_fwstate(mlmepriv, WIFI_AP_STATE) == _TRUE) ||
++ (check_fwstate(mlmepriv, WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE) == _TRUE))
++ {
++ if(adapter->stapriv.asoc_sta_count > 2)
++ linked = _TRUE;
++ }
++ else{//Station mode
++ if(check_fwstate(mlmepriv, _FW_LINKED)== _TRUE)
++ linked = _TRUE;
++ }
++
++ return linked;
++}
++
++bool dm_linked(_adapter *adapter)
++{
++ bool linked;
++
++ if ((linked = rtw_adapter_linked(adapter)))
++ goto exit;
++
++#ifdef CONFIG_CONCURRENT_MODE
++ if ((adapter = adapter->pbuddy_adapter) == NULL)
++ goto exit;
++ linked = rtw_adapter_linked(adapter);
++#endif
++
++exit:
++ return linked;
++}
++
++#if 0
++void dm_enable_EDCCA(_adapter *adapter)
++{
++ // Enable EDCCA. The value is suggested by SD3 Wilson.
++
++ //
++ // Revised for ASUS 11b/g performance issues, suggested by BB Neil, 2012.04.13.
++ //
++ /*if((pDM_Odm->SupportICType == ODM_RTL8723A)&&(IS_WIRELESS_MODE_G(pAdapter)))
++ {
++ rtw_write8(adapter,rOFDM0_ECCAThreshold,0x00);
++ rtw_write8(adapter,rOFDM0_ECCAThreshold+2,0xFD);
++
++ }
++ else*/
++ {
++ rtw_write8(adapter,rOFDM0_ECCAThreshold,0x03);
++ rtw_write8(adapter,rOFDM0_ECCAThreshold+2,0x00);
++ }
++}
++
++void dm_disable_EDCCA(_adapter *adapter)
++{
++ // Disable EDCCA..
++ rtw_write8(adapter, rOFDM0_ECCAThreshold, 0x7f);
++ rtw_write8(adapter, rOFDM0_ECCAThreshold+2, 0x7f);
++}
++
++//
++// Description: According to initial gain value to determine to enable or disable EDCCA.
++//
++// Suggested by SD3 Wilson. Added by tynli. 2011.11.25.
++//
++void dm_dynamic_EDCCA(_adapter *pAdapter)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
++ struct dm_priv *dmpriv = &pHalData->dmpriv;
++ u8 RegC50, RegC58;
++
++ RegC50 = (u8)PHY_QueryBBReg(pAdapter, rOFDM0_XAAGCCore1, bMaskByte0);
++ RegC58 = (u8)PHY_QueryBBReg(pAdapter, rOFDM0_XBAGCCore1, bMaskByte0);
++
++
++ if((RegC50 > 0x28 && RegC58 > 0x28)
++ /*|| ((pDM_Odm->SupportICType == ODM_RTL8723A && IS_WIRELESS_MODE_G(pAdapter) && RegC50>0x26))
++ || (pDM_Odm->SupportICType == ODM_RTL8188E && RegC50 > 0x28)*/
++ )
++ {
++ if(!dmpriv->bPreEdccaEnable)
++ {
++ dm_enable_EDCCA(pAdapter);
++ dmpriv->bPreEdccaEnable = _TRUE;
++ }
++
++ }
++ else if((RegC50 < 0x25 && RegC58 < 0x25)
++ /*|| (pDM_Odm->SupportICType == ODM_RTL8188E && RegC50 < 0x25)*/
++ )
++ {
++ if(dmpriv->bPreEdccaEnable)
++ {
++ dm_disable_EDCCA(pAdapter);
++ dmpriv->bPreEdccaEnable = _FALSE;
++ }
++ }
++}
++#endif
++
++#define DM_ADAPTIVITY_VER "ADAPTIVITY_V001"
++
++int dm_adaptivity_get_parm_str(_adapter *pAdapter, char *buf, int len)
++{
++#ifdef CONFIG_DM_ADAPTIVITY
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
++ struct dm_priv *dmpriv = &pHalData->dmpriv;
++
++ return snprintf(buf, len, DM_ADAPTIVITY_VER"\n"
++ "TH_L2H_ini\tTH_EDCCA_HL_diff\tIGI_Base\tForceEDCCA\tAdapEn_RSSI\tIGI_LowerBound\n"
++ "0x%02x\t%d\t0x%02x\t%d\t%u\t%u\n",
++ (u8)dmpriv->TH_L2H_ini,
++ dmpriv->TH_EDCCA_HL_diff,
++ dmpriv->IGI_Base,
++ dmpriv->ForceEDCCA,
++ dmpriv->AdapEn_RSSI,
++ dmpriv->IGI_LowerBound
++ );
++#endif /* CONFIG_DM_ADAPTIVITY */
++ return 0;
++}
++
++void dm_adaptivity_set_parm(_adapter *pAdapter, s8 TH_L2H_ini, s8 TH_EDCCA_HL_diff,
++ s8 IGI_Base, bool ForceEDCCA, u8 AdapEn_RSSI, u8 IGI_LowerBound)
++{
++#ifdef CONFIG_DM_ADAPTIVITY
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
++ struct dm_priv *dmpriv = &pHalData->dmpriv;
++
++ dmpriv->TH_L2H_ini = TH_L2H_ini;
++ dmpriv->TH_EDCCA_HL_diff = TH_EDCCA_HL_diff;
++ dmpriv->IGI_Base = IGI_Base;
++ dmpriv->ForceEDCCA = ForceEDCCA;
++ dmpriv->AdapEn_RSSI = AdapEn_RSSI;
++ dmpriv->IGI_LowerBound = IGI_LowerBound;
++
++#endif /* CONFIG_DM_ADAPTIVITY */
++}
++
++void dm_adaptivity_init(_adapter *pAdapter)
++{
++#ifdef CONFIG_DM_ADAPTIVITY
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
++ struct dm_priv *dmpriv = &pHalData->dmpriv;
++
++ /*
++ if(pDM_Odm->SupportICType == ODM_RTL8723B)
++ {
++ pDM_Odm->TH_L2H_ini = 0xf8; // -8
++ }
++ if((pDM_Odm->SupportICType == ODM_RTL8192E)&&(pDM_Odm->SupportInterface == ODM_ITRF_PCIE))
++ {
++ pDM_Odm->TH_L2H_ini = 0xf0; // -16
++ }
++ else */
++ {
++ dmpriv->TH_L2H_ini = 0xf9; // -7
++ }
++
++ dmpriv->TH_EDCCA_HL_diff = 7;
++ dmpriv->IGI_Base = 0x32;
++ dmpriv->IGI_target = 0x1c;
++ dmpriv->ForceEDCCA = 0;
++ dmpriv->AdapEn_RSSI = 20;
++ dmpriv->IGI_LowerBound = 0;
++
++ //Reg524[11]=0 is easily to transmit packets during adaptivity test
++ PHY_SetBBReg(pAdapter, 0x524, BIT11, 1); // stop counting if EDCCA is asserted
++
++#endif /* CONFIG_DM_ADAPTIVITY */
++}
++
++void dm_adaptivity(_adapter *pAdapter)
++{
++#ifdef CONFIG_DM_ADAPTIVITY
++ s8 TH_L2H_dmc, TH_H2L_dmc;
++ s8 TH_L2H, TH_H2L, Diff, IGI_target;
++ u32 value32;
++ BOOLEAN EDCCA_State;
++
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
++ struct dm_priv *dmpriv = &pHalData->dmpriv;
++ DIG_T *pDigTable = &dmpriv->DM_DigTable;
++ u8 IGI = pDigTable->CurIGValue;
++ u8 RSSI_Min = pDigTable->Rssi_val_min;
++ HT_CHANNEL_WIDTH BandWidth = pHalData->CurrentChannelBW;
++
++ if (!(dmpriv->DMFlag & DYNAMIC_FUNC_ADAPTIVITY))
++ {
++ LOG_LEVEL(_drv_info_, "Go to odm_DynamicEDCCA() \n");
++ // Add by Neil Chen to enable edcca to MP Platform
++ // Adjust EDCCA.
++ /*if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
++ dm_dynamic_EDCCA(pAdapter);
++ */
++ return;
++ }
++ LOG_LEVEL(_drv_info_, "odm_Adaptivity() =====> \n");
++
++ LOG_LEVEL(_drv_info_, "ForceEDCCA=%d, IGI_Base=0x%x, TH_L2H_ini = %d, TH_EDCCA_HL_diff = %d, AdapEn_RSSI = %d\n",
++ dmpriv->ForceEDCCA, dmpriv->IGI_Base, dmpriv->TH_L2H_ini, dmpriv->TH_EDCCA_HL_diff, dmpriv->AdapEn_RSSI);
++
++ /*if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
++ PHY_SetBBReg(0x800, BIT10, 0); //ADC_mask enable
++ */
++
++ if(!dm_linked(pAdapter) || pHalData->CurrentChannel > 149) /* Band4 doesn't need adaptivity */
++ {
++ /*if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES)*/
++ {
++ PHY_SetBBReg(pAdapter,rOFDM0_ECCAThreshold, bMaskByte0, 0x7f);
++ PHY_SetBBReg(pAdapter,rOFDM0_ECCAThreshold, bMaskByte2, 0x7f);
++ }
++ /*else
++ {
++ ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIReadBack, 0xFFFF, (0x7f<<8) | 0x7f);
++ }*/
++ return;
++ }
++
++ if(!dmpriv->ForceEDCCA)
++ {
++ if(RSSI_Min > dmpriv->AdapEn_RSSI)
++ EDCCA_State = 1;
++ else if(RSSI_Min < (dmpriv->AdapEn_RSSI - 5))
++ EDCCA_State = 0;
++ }
++ else
++ EDCCA_State = 1;
++ //if((pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) && (*pDM_Odm->pBandType == BAND_ON_5G))
++ //IGI_target = pDM_Odm->IGI_Base;
++ //else
++ {
++
++ if(BandWidth == HT_CHANNEL_WIDTH_20) //CHANNEL_WIDTH_20
++ IGI_target = dmpriv->IGI_Base;
++ else if(BandWidth == HT_CHANNEL_WIDTH_40)
++ IGI_target = dmpriv->IGI_Base + 2;
++ /*else if(*pDM_Odm->pBandWidth == ODM_BW80M)
++ IGI_target = pDM_Odm->IGI_Base + 6;*/
++ else
++ IGI_target = dmpriv->IGI_Base;
++ }
++
++ dmpriv->IGI_target = (u8)IGI_target;
++
++ LOG_LEVEL(_drv_info_, "BandWidth=%s, IGI_target=0x%x, EDCCA_State=%d\n",
++ (BandWidth==HT_CHANNEL_WIDTH_40)?"40M":"20M", IGI_target, EDCCA_State);
++
++ if(EDCCA_State == 1)
++ {
++ Diff = IGI_target -(s8)IGI;
++ TH_L2H_dmc = dmpriv->TH_L2H_ini + Diff;
++ if(TH_L2H_dmc > 10) TH_L2H_dmc = 10;
++ TH_H2L_dmc = TH_L2H_dmc - dmpriv->TH_EDCCA_HL_diff;
++ }
++ else
++ {
++ TH_L2H_dmc = 0x7f;
++ TH_H2L_dmc = 0x7f;
++ }
++
++ LOG_LEVEL(_drv_info_, "IGI=0x%x, TH_L2H_dmc = %d, TH_H2L_dmc = %d\n",
++ IGI, TH_L2H_dmc, TH_H2L_dmc);
++
++ /*if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES)*/
++ {
++ PHY_SetBBReg(pAdapter,rOFDM0_ECCAThreshold, bMaskByte0, (u8)TH_L2H_dmc);
++ PHY_SetBBReg(pAdapter,rOFDM0_ECCAThreshold, bMaskByte2, (u8)TH_H2L_dmc);
++ }
++ /*else
++ PHY_SetBBReg(pAdapter, rFPGA0_XB_LSSIReadBack, 0xFFFF, ((u8)TH_H2L_dmc<<8) | (u8)TH_L2H_dmc);*/
++
++skip_dm:
++ return;
++#endif /* CONFIG_DM_ADAPTIVITY */
++}
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/hal/dm.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/hal/dm.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/hal/dm.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/hal/dm.h 2015-07-28 01:20:58.305654202 +0200
+@@ -0,0 +1,30 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2013 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++
++ #ifndef __DM_H__
++#define __DM_H__
++
++int dm_adaptivity_get_parm_str(_adapter *pAdapter, char *buf, int len);
++void dm_adaptivity_set_parm(_adapter *pAdapter, s8 TH_L2H_ini, s8 TH_EDCCA_HL_diff,
++ s8 IGI_Base, bool ForceEDCCA, u8 AdapEn_RSSI, u8 IGI_LowerBound);
++void dm_adaptivity_init(_adapter *pAdapter);
++void dm_adaptivity(_adapter *pAdapter);
++
++#endif /* __DM_H__ */
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/hal/hal_com.c linux-xbian-rpi/drivers/net/wireless/rtl8192cu/hal/hal_com.c
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/hal/hal_com.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/hal/hal_com.c 2015-07-28 01:20:58.309639981 +0200
+@@ -0,0 +1,370 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++#include <rtw_byteorder.h>
++
++#include <hal_intf.h>
++#include <hal_com.h>
++
++#ifdef CONFIG_RTL8192C
++#include <rtl8192c_hal.h>
++#endif
++#ifdef CONFIG_RTL8192D
++#include <rtl8192d_hal.h>
++#endif
++
++#define _HAL_COM_C_
++
++//============================================================
++// Global var
++//============================================================
++u32 OFDMSwingTable[OFDM_TABLE_SIZE_92D] = {
++ 0x7f8001fe, // 0, +6.0dB
++ 0x788001e2, // 1, +5.5dB
++ 0x71c001c7, // 2, +5.0dB
++ 0x6b8001ae, // 3, +4.5dB
++ 0x65400195, // 4, +4.0dB
++ 0x5fc0017f, // 5, +3.5dB
++ 0x5a400169, // 6, +3.0dB
++ 0x55400155, // 7, +2.5dB
++ 0x50800142, // 8, +2.0dB
++ 0x4c000130, // 9, +1.5dB
++ 0x47c0011f, // 10, +1.0dB
++ 0x43c0010f, // 11, +0.5dB
++ 0x40000100, // 12, +0dB
++ 0x3c8000f2, // 13, -0.5dB
++ 0x390000e4, // 14, -1.0dB
++ 0x35c000d7, // 15, -1.5dB
++ 0x32c000cb, // 16, -2.0dB
++ 0x300000c0, // 17, -2.5dB
++ 0x2d4000b5, // 18, -3.0dB
++ 0x2ac000ab, // 19, -3.5dB
++ 0x288000a2, // 20, -4.0dB
++ 0x26000098, // 21, -4.5dB
++ 0x24000090, // 22, -5.0dB
++ 0x22000088, // 23, -5.5dB
++ 0x20000080, // 24, -6.0dB
++ 0x1e400079, // 25, -6.5dB
++ 0x1c800072, // 26, -7.0dB
++ 0x1b00006c, // 27. -7.5dB
++ 0x19800066, // 28, -8.0dB
++ 0x18000060, // 29, -8.5dB
++ 0x16c0005b, // 30, -9.0dB
++ 0x15800056, // 31, -9.5dB
++ 0x14400051, // 32, -10.0dB
++ 0x1300004c, // 33, -10.5dB
++ 0x12000048, // 34, -11.0dB
++ 0x11000044, // 35, -11.5dB
++ 0x10000040, // 36, -12.0dB
++ 0x0f00003c,// 37, -12.5dB
++ 0x0e400039,// 38, -13.0dB
++ 0x0d800036,// 39, -13.5dB
++ 0x0cc00033,// 40, -14.0dB
++ 0x0c000030,// 41, -14.5dB
++ 0x0b40002d,// 42, -15.0dB
++};
++
++
++u8 CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8] = {
++ {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, // 0, +0dB
++ {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, // 1, -0.5dB
++ {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, // 2, -1.0dB
++ {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, // 3, -1.5dB
++ {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, // 4, -2.0dB
++ {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, // 5, -2.5dB
++ {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, // 6, -3.0dB
++ {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, // 7, -3.5dB
++ {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, // 8, -4.0dB
++ {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, // 9, -4.5dB
++ {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, // 10, -5.0dB
++ {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, // 11, -5.5dB
++ {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, // 12, -6.0dB
++ {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, // 13, -6.5dB
++ {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, // 14, -7.0dB
++ {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, // 15, -7.5dB
++ {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, // 16, -8.0dB
++ {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, // 17, -8.5dB
++ {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, // 18, -9.0dB
++ {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 19, -9.5dB
++ {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 20, -10.0dB
++ {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, // 21, -10.5dB
++ {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, // 22, -11.0dB
++ {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, // 23, -11.5dB
++ {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, // 24, -12.0dB
++ {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, // 25, -12.5dB
++ {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, // 26, -13.0dB
++ {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, // 27, -13.5dB
++ {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, // 28, -14.0dB
++ {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, // 29, -14.5dB
++ {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, // 30, -15.0dB
++ {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, // 31, -15.5dB
++ {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} // 32, -16.0dB
++};
++
++
++u8 CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8]= {
++ {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, // 0, +0dB
++ {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, // 1, -0.5dB
++ {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, // 2, -1.0dB
++ {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, // 3, -1.5dB
++ {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, // 4, -2.0dB
++ {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, // 5, -2.5dB
++ {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, // 6, -3.0dB
++ {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, // 7, -3.5dB
++ {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, // 8, -4.0dB
++ {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, // 9, -4.5dB
++ {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, // 10, -5.0dB
++ {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 11, -5.5dB
++ {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 12, -6.0dB
++ {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, // 13, -6.5dB
++ {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, // 14, -7.0dB
++ {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 15, -7.5dB
++ {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 16, -8.0dB
++ {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 17, -8.5dB
++ {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 18, -9.0dB
++ {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 19, -9.5dB
++ {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 20, -10.0dB
++ {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, // 21, -10.5dB
++ {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, // 22, -11.0dB
++ {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, // 23, -11.5dB
++ {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, // 24, -12.0dB
++ {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, // 25, -12.5dB
++ {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, // 26, -13.0dB
++ {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, // 27, -13.5dB
++ {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, // 28, -14.0dB
++ {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, // 29, -14.5dB
++ {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, // 30, -15.0dB
++ {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, // 31, -15.5dB
++ {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} // 32, -16.0dB
++};
++
++
++#ifdef CONFIG_CHIP_VER_INTEGRATION
++void dump_chip_info(HAL_VERSION ChipVersion)
++{
++ if(IS_81XXC(ChipVersion)){
++ DBG_871X("Chip Version Info: %s_",IS_92C_SERIAL(ChipVersion)?"CHIP_8192C":"CHIP_8188C");
++ }
++ else if(IS_92D(ChipVersion)){
++ DBG_871X("Chip Version Info: CHIP_8192D_");
++ }
++ else if(IS_8723_SERIES(ChipVersion)){
++ DBG_871X("Chip Version Info: CHIP_8723A_");
++ }
++ else if(IS_8188E(ChipVersion)){
++ DBG_871X("Chip Version Info: CHIP_8188E_");
++ }
++
++ DBG_871X("%s_",IS_NORMAL_CHIP(ChipVersion)?"Normal_Chip":"Test_Chip");
++ DBG_871X("%s_",IS_CHIP_VENDOR_TSMC(ChipVersion)?"TSMC":"UMC");
++ if(IS_A_CUT(ChipVersion)) DBG_871X("A_CUT_");
++ else if(IS_B_CUT(ChipVersion)) DBG_871X("B_CUT_");
++ else if(IS_C_CUT(ChipVersion)) DBG_871X("C_CUT_");
++ else if(IS_D_CUT(ChipVersion)) DBG_871X("D_CUT_");
++ else if(IS_E_CUT(ChipVersion)) DBG_871X("E_CUT_");
++ else DBG_871X("UNKNOWN_CUT(%d)_",ChipVersion.CUTVersion);
++
++ if(IS_1T1R(ChipVersion)) DBG_871X("1T1R_");
++ else if(IS_1T2R(ChipVersion)) DBG_871X("1T2R_");
++ else if(IS_2T2R(ChipVersion)) DBG_871X("2T2R_");
++ else DBG_871X("UNKNOWN_RFTYPE(%d)_",ChipVersion.RFType);
++
++
++ DBG_871X("RomVer(%d)\n",ChipVersion.ROMVer);
++}
++
++#endif
++
++#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80
++
++u8 //return the final channel plan decision
++hal_com_get_channel_plan(
++ IN PADAPTER padapter,
++ IN u8 hw_channel_plan, //channel plan from HW (efuse/eeprom)
++ IN u8 sw_channel_plan, //channel plan from SW (registry/module param)
++ IN u8 def_channel_plan, //channel plan used when the former two is invalid
++ IN BOOLEAN AutoLoadFail
++ )
++{
++ u8 swConfig;
++ u8 chnlPlan;
++
++ swConfig = _TRUE;
++ if (!AutoLoadFail)
++ {
++ if (!rtw_is_channel_plan_valid(sw_channel_plan))
++ swConfig = _FALSE;
++ if (hw_channel_plan & EEPROM_CHANNEL_PLAN_BY_HW_MASK)
++ swConfig = _FALSE;
++ }
++
++ if (swConfig == _TRUE)
++ chnlPlan = sw_channel_plan;
++ else
++ chnlPlan = hw_channel_plan & (~EEPROM_CHANNEL_PLAN_BY_HW_MASK);
++
++ if (!rtw_is_channel_plan_valid(chnlPlan))
++ chnlPlan = def_channel_plan;
++
++ return chnlPlan;
++}
++
++u8 MRateToHwRate(u8 rate)
++{
++ u8 ret = DESC_RATE1M;
++
++ switch(rate)
++ {
++ // CCK and OFDM non-HT rates
++ case IEEE80211_CCK_RATE_1MB: ret = DESC_RATE1M; break;
++ case IEEE80211_CCK_RATE_2MB: ret = DESC_RATE2M; break;
++ case IEEE80211_CCK_RATE_5MB: ret = DESC_RATE5_5M; break;
++ case IEEE80211_CCK_RATE_11MB: ret = DESC_RATE11M; break;
++ case IEEE80211_OFDM_RATE_6MB: ret = DESC_RATE6M; break;
++ case IEEE80211_OFDM_RATE_9MB: ret = DESC_RATE9M; break;
++ case IEEE80211_OFDM_RATE_12MB: ret = DESC_RATE12M; break;
++ case IEEE80211_OFDM_RATE_18MB: ret = DESC_RATE18M; break;
++ case IEEE80211_OFDM_RATE_24MB: ret = DESC_RATE24M; break;
++ case IEEE80211_OFDM_RATE_36MB: ret = DESC_RATE36M; break;
++ case IEEE80211_OFDM_RATE_48MB: ret = DESC_RATE48M; break;
++ case IEEE80211_OFDM_RATE_54MB: ret = DESC_RATE54M; break;
++
++ // HT rates since here
++ //case MGN_MCS0: ret = DESC_RATEMCS0; break;
++ //case MGN_MCS1: ret = DESC_RATEMCS1; break;
++ //case MGN_MCS2: ret = DESC_RATEMCS2; break;
++ //case MGN_MCS3: ret = DESC_RATEMCS3; break;
++ //case MGN_MCS4: ret = DESC_RATEMCS4; break;
++ //case MGN_MCS5: ret = DESC_RATEMCS5; break;
++ //case MGN_MCS6: ret = DESC_RATEMCS6; break;
++ //case MGN_MCS7: ret = DESC_RATEMCS7; break;
++
++ default: break;
++ }
++
++ return ret;
++}
++
++void HalSetBrateCfg(
++ IN PADAPTER Adapter,
++ IN u8 *mBratesOS,
++ OUT u16 *pBrateCfg)
++{
++ u8 i, is_brate, brate;
++
++ for(i=0;i<NDIS_802_11_LENGTH_RATES_EX;i++)
++ {
++ is_brate = mBratesOS[i] & IEEE80211_BASIC_RATE_MASK;
++ brate = mBratesOS[i] & 0x7f;
++
++ if( is_brate )
++ {
++ switch(brate)
++ {
++ case IEEE80211_CCK_RATE_1MB: *pBrateCfg |= RATE_1M; break;
++ case IEEE80211_CCK_RATE_2MB: *pBrateCfg |= RATE_2M; break;
++ case IEEE80211_CCK_RATE_5MB: *pBrateCfg |= RATE_5_5M;break;
++ case IEEE80211_CCK_RATE_11MB: *pBrateCfg |= RATE_11M; break;
++ case IEEE80211_OFDM_RATE_6MB: *pBrateCfg |= RATE_6M; break;
++ case IEEE80211_OFDM_RATE_9MB: *pBrateCfg |= RATE_9M; break;
++ case IEEE80211_OFDM_RATE_12MB: *pBrateCfg |= RATE_12M; break;
++ case IEEE80211_OFDM_RATE_18MB: *pBrateCfg |= RATE_18M; break;
++ case IEEE80211_OFDM_RATE_24MB: *pBrateCfg |= RATE_24M; break;
++ case IEEE80211_OFDM_RATE_36MB: *pBrateCfg |= RATE_36M; break;
++ case IEEE80211_OFDM_RATE_48MB: *pBrateCfg |= RATE_48M; break;
++ case IEEE80211_OFDM_RATE_54MB: *pBrateCfg |= RATE_54M; break;
++ }
++ }
++ }
++}
++
++void hal_init_macaddr(_adapter *adapter)
++{
++ rtw_hal_set_hwreg(adapter, HW_VAR_MAC_ADDR, adapter->eeprompriv.mac_addr);
++#ifdef CONFIG_CONCURRENT_MODE
++ if (adapter->pbuddy_adapter)
++ rtw_hal_set_hwreg(adapter->pbuddy_adapter, HW_VAR_MAC_ADDR, adapter->pbuddy_adapter->eeprompriv.mac_addr);
++#endif
++}
++
++/*
++* C2H event format:
++* Field TRIGGER CONTENT CMD_SEQ CMD_LEN CMD_ID
++* BITS [127:120] [119:16] [15:8] [7:4] [3:0]
++*/
++
++void c2h_evt_clear(_adapter *adapter)
++{
++ rtw_write8(adapter, REG_C2HEVT_CLEAR, C2H_EVT_HOST_CLOSE);
++}
++
++s32 c2h_evt_read(_adapter *adapter, u8 *buf)
++{
++ s32 ret = _FAIL;
++ struct c2h_evt_hdr *c2h_evt;
++ int i;
++ u8 trigger;
++
++ if (buf == NULL)
++ goto exit;
++
++ trigger = rtw_read8(adapter, REG_C2HEVT_CLEAR);
++
++ if (trigger == C2H_EVT_HOST_CLOSE) {
++ goto exit; /* Not ready */
++ } else if (trigger != C2H_EVT_FW_CLOSE) {
++ goto clear_evt; /* Not a valid value */
++ }
++
++ c2h_evt = (struct c2h_evt_hdr *)buf;
++
++ _rtw_memset(c2h_evt, 0, 16);
++
++ *buf = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL);
++ *(buf+1) = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL + 1);
++
++ RT_PRINT_DATA(_module_hal_init_c_, _drv_info_, "c2h_evt_read(): ",
++ &c2h_evt , sizeof(c2h_evt));
++
++ if (0) {
++ DBG_871X("%s id:%u, len:%u, seq:%u, trigger:0x%02x\n", __func__
++ , c2h_evt->id, c2h_evt->plen, c2h_evt->seq, trigger);
++ }
++
++ /* Read the content */
++ for (i = 0; i < c2h_evt->plen; i++)
++ c2h_evt->payload[i] = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL + sizeof(*c2h_evt) + i);
++
++ RT_PRINT_DATA(_module_hal_init_c_, _drv_info_, "c2h_evt_read(): Command Content:\n",
++ c2h_evt->payload, c2h_evt->plen);
++
++ ret = _SUCCESS;
++
++clear_evt:
++ /*
++ * Clear event to notify FW we have read the command.
++ * If this field isn't clear, the FW won't update the next command message.
++ */
++ c2h_evt_clear(adapter);
++exit:
++ return ret;
++}
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/hal/hal_intf.c linux-xbian-rpi/drivers/net/wireless/rtl8192cu/hal/hal_intf.c
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/hal/hal_intf.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/hal/hal_intf.c 2015-07-28 01:20:58.309639981 +0200
+@@ -0,0 +1,545 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++
++#define _HAL_INTF_C_
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++#include <rtw_byteorder.h>
++
++#include <hal_intf.h>
++
++#ifdef CONFIG_SDIO_HCI
++ #include <sdio_hal.h>
++#elif defined(CONFIG_USB_HCI)
++ #include <usb_hal.h>
++#elif defined(CONFIG_GSPI_HCI)
++ #include <gspi_hal.h>
++#endif
++
++void rtw_hal_chip_configure(_adapter *padapter)
++{
++ if(padapter->HalFunc.intf_chip_configure)
++ padapter->HalFunc.intf_chip_configure(padapter);
++}
++
++void rtw_hal_read_chip_info(_adapter *padapter)
++{
++ if(padapter->HalFunc.read_adapter_info)
++ padapter->HalFunc.read_adapter_info(padapter);
++}
++
++void rtw_hal_read_chip_version(_adapter *padapter)
++{
++ if(padapter->HalFunc.read_chip_version)
++ padapter->HalFunc.read_chip_version(padapter);
++}
++
++void rtw_hal_def_value_init(_adapter *padapter)
++{
++ if(padapter->HalFunc.init_default_value)
++ padapter->HalFunc.init_default_value(padapter);
++}
++
++void rtw_hal_free_data(_adapter *padapter)
++{
++ if(padapter->HalFunc.free_hal_data)
++ padapter->HalFunc.free_hal_data(padapter);
++}
++
++void rtw_hal_dm_init(_adapter *padapter)
++{
++ if(padapter->HalFunc.dm_init)
++ padapter->HalFunc.dm_init(padapter);
++}
++
++void rtw_hal_dm_deinit(_adapter *padapter)
++{
++ // cancel dm timer
++ if(padapter->HalFunc.dm_deinit)
++ padapter->HalFunc.dm_deinit(padapter);
++}
++
++void rtw_hal_sw_led_init(_adapter *padapter)
++{
++ if(padapter->HalFunc.InitSwLeds)
++ padapter->HalFunc.InitSwLeds(padapter);
++}
++
++void rtw_hal_sw_led_deinit(_adapter *padapter)
++{
++ if(padapter->HalFunc.DeInitSwLeds)
++ padapter->HalFunc.DeInitSwLeds(padapter);
++}
++
++uint rtw_hal_init(_adapter *padapter)
++{
++ uint status = _SUCCESS;
++
++ if(padapter->hw_init_completed == _TRUE)
++ {
++ DBG_871X("rtw_hal_init: hw_init_completed == _TRUE\n");
++ goto success;
++ }
++#ifdef CONFIG_DEINIT_BEFORE_INIT
++ status = padapter->HalFunc.hal_deinit(padapter);
++ if(status != _SUCCESS){
++ DBG_871X("rtw_hal_init: hal_deinit before hal_init FAIL !!\n");
++ goto fail;
++ }
++#endif
++
++#ifdef CONFIG_DUALMAC_CONCURRENT
++ // before init mac0, driver must init mac1 first to avoid usb rx error.
++ if((padapter->pbuddy_adapter != NULL) && (padapter->DualMacConcurrent == _TRUE)
++ && (padapter->adapter_type == PRIMARY_ADAPTER))
++ {
++ if(padapter->pbuddy_adapter->hw_init_completed == _TRUE)
++ {
++ DBG_871X("rtw_hal_init: pbuddy_adapter hw_init_completed == _TRUE\n");
++ }
++ else
++ {
++#ifdef CONFIG_DEINIT_BEFORE_INIT
++ status = padapter->HalFunc.hal_deinit(padapter->pbuddy_adapter);
++ if(status != _SUCCESS){
++ DBG_871X("rtw_hal_init: hal_deinit before hal_init FAIL !!(pbuddy_adapter)\n");
++ goto fail;
++ }
++#endif
++ status = padapter->HalFunc.hal_init(padapter->pbuddy_adapter);
++ if(status == _SUCCESS){
++ padapter->pbuddy_adapter->hw_init_completed = _TRUE;
++ }
++ else{
++ padapter->pbuddy_adapter->hw_init_completed = _FALSE;
++ RT_TRACE(_module_hal_init_c_,_drv_err_,("rtw_hal_init: hal__init fail(pbuddy_adapter)\n"));
++ goto fail;
++ }
++ }
++ }
++#else
++ if(adapter_to_dvobj(padapter)->DualMacMode == _TRUE)
++ {
++ if(padapter->pbuddy_adapter != NULL) {
++ if(padapter->pbuddy_adapter->hw_init_completed == _FALSE)
++ {
++#ifdef CONFIG_DEINIT_BEFORE_INIT
++ status = padapter->HalFunc.hal_deinit(padapter->pbuddy_adapter);
++ if(status != _SUCCESS){
++ DBG_871X("rtw_hal_init: hal_deinit before hal_init FAIL !!(pbuddy_adapter)\n");
++ goto fail;
++ }
++#endif
++ status = padapter->HalFunc.hal_init(padapter->pbuddy_adapter);
++ if(status == _SUCCESS){
++ padapter->pbuddy_adapter->hw_init_completed = _TRUE;
++ }
++ else{
++ padapter->pbuddy_adapter->hw_init_completed = _FALSE;
++ RT_TRACE(_module_hal_init_c_,_drv_err_,("rtw_hal_init: hal__init fail for another interface\n"));
++ }
++ }
++ }
++ }
++#endif
++
++ padapter->hw_init_completed=_FALSE;
++
++ status = padapter->HalFunc.hal_init(padapter);
++
++ if(status == _SUCCESS){
++ padapter->hw_init_completed = _TRUE;
++ }
++ else{
++ padapter->hw_init_completed = _FALSE;
++ RT_TRACE(_module_hal_init_c_,_drv_err_,("rtw_hal_init: hal__init fail\n"));
++ goto fail;
++ }
++
++success:
++
++ if (padapter->registrypriv.notch_filter == 1)
++ rtw_hal_notch_filter(padapter, 1);
++
++ rtw_hal_reset_security_engine(padapter);
++
++ rtw_sec_restore_wep_key(padapter);
++
++ init_hw_mlme_ext(padapter);
++
++fail:
++
++ RT_TRACE(_module_hal_init_c_,_drv_err_,("-rtl871x_hal_init:status=0x%x\n",status));
++
++ return status;
++}
++
++uint rtw_hal_deinit(_adapter *padapter)
++{
++ uint status = _SUCCESS;
++
++_func_enter_;
++
++ status = padapter->HalFunc.hal_deinit(padapter);
++
++ if(status == _SUCCESS){
++ padapter->hw_init_completed = _FALSE;
++ }
++ else
++ {
++ RT_TRACE(_module_hal_init_c_,_drv_err_,("\n rtw_hal_deinit: hal_init fail\n"));
++ }
++
++_func_exit_;
++
++ return status;
++}
++
++void rtw_hal_set_hwreg(_adapter *padapter, u8 variable, u8 *val)
++{
++ if (padapter->HalFunc.SetHwRegHandler)
++ padapter->HalFunc.SetHwRegHandler(padapter, variable, val);
++}
++
++void rtw_hal_get_hwreg(_adapter *padapter, u8 variable, u8 *val)
++{
++ if (padapter->HalFunc.GetHwRegHandler)
++ padapter->HalFunc.GetHwRegHandler(padapter, variable, val);
++}
++
++u8 rtw_hal_set_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, PVOID pValue)
++{
++ if(padapter->HalFunc.SetHalDefVarHandler)
++ return padapter->HalFunc.SetHalDefVarHandler(padapter,eVariable,pValue);
++ return _FAIL;
++}
++
++u8 rtw_hal_get_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, PVOID pValue)
++{
++ if(padapter->HalFunc.GetHalDefVarHandler)
++ return padapter->HalFunc.GetHalDefVarHandler(padapter,eVariable,pValue);
++ return _FAIL;
++}
++
++void rtw_hal_enable_interrupt(_adapter *padapter)
++{
++ if (padapter->HalFunc.enable_interrupt)
++ padapter->HalFunc.enable_interrupt(padapter);
++ else
++ DBG_871X("%s: HalFunc.enable_interrupt is NULL!\n", __FUNCTION__);
++
++}
++void rtw_hal_disable_interrupt(_adapter *padapter)
++{
++ if (padapter->HalFunc.disable_interrupt)
++ padapter->HalFunc.disable_interrupt(padapter);
++ else
++ DBG_871X("%s: HalFunc.disable_interrupt is NULL!\n", __FUNCTION__);
++
++}
++
++u32 rtw_hal_inirp_init(_adapter *padapter)
++{
++ u32 rst = _FAIL;
++ if(padapter->HalFunc.inirp_init)
++ rst = padapter->HalFunc.inirp_init(padapter);
++ else
++ DBG_871X(" %s HalFunc.inirp_init is NULL!!!\n",__FUNCTION__);
++ return rst;
++}
++
++u32 rtw_hal_inirp_deinit(_adapter *padapter)
++{
++
++ if(padapter->HalFunc.inirp_deinit)
++ return padapter->HalFunc.inirp_deinit(padapter);
++
++ return _FAIL;
++
++}
++
++u8 rtw_hal_intf_ps_func(_adapter *padapter,HAL_INTF_PS_FUNC efunc_id, u8* val)
++{
++ if(padapter->HalFunc.interface_ps_func)
++ return padapter->HalFunc.interface_ps_func(padapter,efunc_id,val);
++ return _FAIL;
++}
++
++s32 rtw_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe)
++{
++ if(padapter->HalFunc.hal_xmitframe_enqueue)
++ return padapter->HalFunc.hal_xmitframe_enqueue(padapter, pxmitframe);
++
++ return _FALSE;
++}
++
++s32 rtw_hal_xmit(_adapter *padapter, struct xmit_frame *pxmitframe)
++{
++ if(padapter->HalFunc.hal_xmit)
++ return padapter->HalFunc.hal_xmit(padapter, pxmitframe);
++
++ return _FALSE;
++}
++
++s32 rtw_hal_mgnt_xmit(_adapter *padapter, struct xmit_frame *pmgntframe)
++{
++ s32 ret = _FAIL;
++ unsigned char *pframe;
++ struct rtw_ieee80211_hdr *pwlanhdr;
++
++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++ _rtw_memcpy(pmgntframe->attrib.ra, pwlanhdr->addr1, ETH_ALEN);
++
++#ifdef CONFIG_IEEE80211W
++ if(padapter->securitypriv.binstallBIPkey == _TRUE)
++ {
++ if(IS_MCAST(pmgntframe->attrib.ra))
++ {
++ pmgntframe->attrib.encrypt = _BIP_;
++ //pmgntframe->attrib.bswenc = _TRUE;
++ }
++ else
++ {
++ pmgntframe->attrib.encrypt = _AES_;
++ pmgntframe->attrib.bswenc = _TRUE;
++ }
++ rtw_mgmt_xmitframe_coalesce(padapter, pmgntframe->pkt, pmgntframe);
++ }
++#endif //CONFIG_IEEE80211W
++
++ if(padapter->HalFunc.mgnt_xmit)
++ ret = padapter->HalFunc.mgnt_xmit(padapter, pmgntframe);
++ return ret;
++}
++
++s32 rtw_hal_init_xmit_priv(_adapter *padapter)
++{
++ if(padapter->HalFunc.init_xmit_priv != NULL)
++ return padapter->HalFunc.init_xmit_priv(padapter);
++ return _FAIL;
++}
++
++void rtw_hal_free_xmit_priv(_adapter *padapter)
++{
++ if(padapter->HalFunc.free_xmit_priv != NULL)
++ padapter->HalFunc.free_xmit_priv(padapter);
++}
++
++s32 rtw_hal_init_recv_priv(_adapter *padapter)
++{
++ if(padapter->HalFunc.init_recv_priv)
++ return padapter->HalFunc.init_recv_priv(padapter);
++
++ return _FAIL;
++}
++
++void rtw_hal_free_recv_priv(_adapter *padapter)
++{
++ if(padapter->HalFunc.free_recv_priv)
++ padapter->HalFunc.free_recv_priv(padapter);
++}
++
++void rtw_hal_update_ra_mask(_adapter *padapter, u32 mac_id)
++{
++ if(padapter->HalFunc.UpdateRAMaskHandler)
++ padapter->HalFunc.UpdateRAMaskHandler(padapter,mac_id);
++}
++
++void rtw_hal_add_ra_tid(_adapter *padapter, u32 bitmap, u8 arg)
++{
++ if(padapter->HalFunc.Add_RateATid)
++ padapter->HalFunc.Add_RateATid(padapter, bitmap, arg);
++}
++
++u32 rtw_hal_read_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask)
++{
++ u32 data = 0;
++ if (padapter->HalFunc.read_bbreg)
++ data = padapter->HalFunc.read_bbreg(padapter, RegAddr, BitMask);
++ return data;
++}
++
++void rtw_hal_write_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data)
++{
++ if (padapter->HalFunc.write_bbreg)
++ padapter->HalFunc.write_bbreg(padapter, RegAddr, BitMask, Data);
++}
++
++u32 rtw_hal_read_rfreg(_adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMask)
++{
++ u32 data = 0;
++ if (padapter->HalFunc.read_rfreg)
++ data = padapter->HalFunc.read_rfreg(padapter, eRFPath, RegAddr, BitMask);
++ return data;
++}
++
++void rtw_hal_write_rfreg(_adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMask, u32 Data)
++{
++ if (padapter->HalFunc.write_rfreg)
++ padapter->HalFunc.write_rfreg(padapter, eRFPath, RegAddr, BitMask, Data);
++}
++
++s32 rtw_hal_interrupt_handler(_adapter *padapter)
++{
++ if(padapter->HalFunc.interrupt_handler)
++ return padapter->HalFunc.interrupt_handler(padapter);
++ return _FAIL;
++}
++
++void rtw_hal_set_bwmode(_adapter *padapter, HT_CHANNEL_WIDTH Bandwidth, u8 Offset)
++{
++ if(padapter->HalFunc.set_bwmode_handler)
++ padapter->HalFunc.set_bwmode_handler(padapter, Bandwidth, Offset);
++}
++
++void rtw_hal_set_chan(_adapter *padapter, u8 channel)
++{
++ if(padapter->HalFunc.set_channel_handler)
++ padapter->HalFunc.set_channel_handler(padapter, channel);
++}
++
++void rtw_hal_dm_watchdog(_adapter *padapter)
++{
++ if(padapter->HalFunc.hal_dm_watchdog)
++ padapter->HalFunc.hal_dm_watchdog(padapter);
++}
++
++void rtw_hal_bcn_related_reg_setting(_adapter *padapter)
++{
++ if(padapter->HalFunc.SetBeaconRelatedRegistersHandler)
++ padapter->HalFunc.SetBeaconRelatedRegistersHandler(padapter);
++}
++
++#ifdef CONFIG_ANTENNA_DIVERSITY
++u8 rtw_hal_antdiv_before_linked(_adapter *padapter)
++{
++ if (padapter->HalFunc.AntDivBeforeLinkHandler)
++ return padapter->HalFunc.AntDivBeforeLinkHandler(padapter);
++ return _FALSE;
++}
++
++void rtw_hal_antdiv_rssi_compared(_adapter *padapter, WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src)
++{
++ if (padapter->HalFunc.AntDivCompareHandler)
++ padapter->HalFunc.AntDivCompareHandler(padapter, dst, src);
++}
++#endif
++
++#ifdef CONFIG_HOSTAPD_MLME
++s32 rtw_hal_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt)
++{
++ if (padapter->HalFunc.hostap_mgnt_xmit_entry)
++ return padapter->HalFunc.hostap_mgnt_xmit_entry(padapter, pkt);
++ return _FAIL;
++}
++#endif //CONFIG_HOSTAPD_MLME
++
++#ifdef DBG_CONFIG_ERROR_DETECT
++void rtw_hal_sreset_init(_adapter *padapter)
++{
++ if(padapter->HalFunc.sreset_init_value)
++ padapter->HalFunc.sreset_init_value(padapter);
++}
++
++void rtw_hal_sreset_reset(_adapter *padapter)
++{
++ padapter = GET_PRIMARY_ADAPTER(padapter);
++
++ if(padapter->HalFunc.silentreset)
++ padapter->HalFunc.silentreset(padapter);
++}
++
++void rtw_hal_sreset_reset_value(_adapter *padapter)
++{
++ if(padapter->HalFunc.sreset_reset_value)
++ padapter->HalFunc.sreset_reset_value(padapter);
++}
++
++void rtw_hal_sreset_xmit_status_check(_adapter *padapter)
++{
++#ifdef CONFIG_CONCURRENT_MODE
++ if (padapter->adapter_type != PRIMARY_ADAPTER)
++ return;
++#endif
++ if(padapter->HalFunc.sreset_xmit_status_check)
++ padapter->HalFunc.sreset_xmit_status_check(padapter);
++}
++
++void rtw_hal_sreset_linked_status_check(_adapter *padapter)
++{
++ if(padapter->HalFunc.sreset_linked_status_check)
++ padapter->HalFunc.sreset_linked_status_check(padapter);
++}
++
++u8 rtw_hal_sreset_get_wifi_status(_adapter *padapter)
++{
++ u8 status = 0;
++ if(padapter->HalFunc.sreset_get_wifi_status)
++ status = padapter->HalFunc.sreset_get_wifi_status(padapter);
++ return status;
++}
++
++bool rtw_hal_sreset_inprogress(_adapter *padapter)
++{
++ bool inprogress = _FALSE;
++
++ padapter = GET_PRIMARY_ADAPTER(padapter);
++
++ if(padapter->HalFunc.sreset_inprogress)
++ inprogress = padapter->HalFunc.sreset_inprogress(padapter);
++ return inprogress;
++}
++#endif //DBG_CONFIG_ERROR_DETECT
++
++#ifdef CONFIG_IOL
++int rtw_hal_iol_cmd(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms)
++{
++ if (adapter->HalFunc.IOL_exec_cmds_sync)
++ return adapter->HalFunc.IOL_exec_cmds_sync(adapter, xmit_frame, max_wating_ms);
++ return _FAIL;
++}
++#endif
++
++void rtw_hal_notch_filter(_adapter *adapter, bool enable)
++{
++ if(adapter->HalFunc.hal_notch_filter)
++ adapter->HalFunc.hal_notch_filter(adapter,enable);
++}
++
++void rtw_hal_reset_security_engine(_adapter * adapter)
++{
++ if(adapter->HalFunc.hal_reset_security_engine)
++ adapter->HalFunc.hal_reset_security_engine(adapter);
++}
++
++s32 rtw_hal_c2h_handler(_adapter *adapter, struct c2h_evt_hdr *c2h_evt)
++{
++ s32 ret = _FAIL;
++ if (adapter->HalFunc.c2h_handler)
++ ret = adapter->HalFunc.c2h_handler(adapter, c2h_evt);
++ return ret;
++}
++
++c2h_id_filter rtw_hal_c2h_id_filter_ccx(_adapter *adapter)
++{
++ return adapter->HalFunc.c2h_id_filter_ccx;
++}
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/hal/HalPwrSeqCmd.c linux-xbian-rpi/drivers/net/wireless/rtl8192cu/hal/HalPwrSeqCmd.c
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/hal/HalPwrSeqCmd.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/hal/HalPwrSeqCmd.c 2015-07-28 01:20:58.305654202 +0200
+@@ -0,0 +1,175 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++/*++
++Copyright (c) Realtek Semiconductor Corp. All rights reserved.
++
++Module Name:
++ HalPwrSeqCmd.c
++
++Abstract:
++ Implement HW Power sequence configuration CMD handling routine for Realtek devices.
++
++Major Change History:
++ When Who What
++ ---------- --------------- -------------------------------
++ 2011-10-26 Lucas Modify to be compatible with SD4-CE driver.
++ 2011-07-07 Roger Create.
++
++--*/
++#include <HalPwrSeqCmd.h>
++#include <sdio_ops.h>
++
++
++//
++// Description:
++// This routine deal with the Power Configuration CMDs parsing for RTL8723/RTL8188E Series IC.
++//
++// Assumption:
++// We should follow specific format which was released from HW SD.
++//
++// 2011.07.07, added by Roger.
++//
++u8 HalPwrSeqCmdParsing(
++ PADAPTER padapter,
++ u8 CutVersion,
++ u8 FabVersion,
++ u8 InterfaceType,
++ WLAN_PWR_CFG PwrSeqCmd[])
++{
++ WLAN_PWR_CFG PwrCfgCmd = {0};
++ u8 bPollingBit = _FALSE;
++ u32 AryIdx = 0;
++ u8 value = 0;
++ u32 offset = 0;
++ u32 pollingCount = 0; // polling autoload done.
++ u32 maxPollingCnt = 5000;
++
++ do {
++ PwrCfgCmd = PwrSeqCmd[AryIdx];
++
++ RT_TRACE(_module_hal_init_c_ , _drv_info_,
++ ("HalPwrSeqCmdParsing: offset(%#x) cut_msk(%#x) fab_msk(%#x) interface_msk(%#x) base(%#x) cmd(%#x) msk(%#x) value(%#x)\n",
++ GET_PWR_CFG_OFFSET(PwrCfgCmd),
++ GET_PWR_CFG_CUT_MASK(PwrCfgCmd),
++ GET_PWR_CFG_FAB_MASK(PwrCfgCmd),
++ GET_PWR_CFG_INTF_MASK(PwrCfgCmd),
++ GET_PWR_CFG_BASE(PwrCfgCmd),
++ GET_PWR_CFG_CMD(PwrCfgCmd),
++ GET_PWR_CFG_MASK(PwrCfgCmd),
++ GET_PWR_CFG_VALUE(PwrCfgCmd)));
++
++ //2 Only Handle the command whose FAB, CUT, and Interface are matched
++ if ((GET_PWR_CFG_FAB_MASK(PwrCfgCmd) & FabVersion) &&
++ (GET_PWR_CFG_CUT_MASK(PwrCfgCmd) & CutVersion) &&
++ (GET_PWR_CFG_INTF_MASK(PwrCfgCmd) & InterfaceType))
++ {
++ switch (GET_PWR_CFG_CMD(PwrCfgCmd))
++ {
++ case PWR_CMD_READ:
++ RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_READ\n"));
++ break;
++
++ case PWR_CMD_WRITE:
++ RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_WRITE\n"));
++ offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
++
++#ifdef CONFIG_SDIO_HCI
++ //
++ // <Roger_Notes> We should deal with interface specific address mapping for some interfaces, e.g., SDIO interface
++ // 2011.07.07.
++ //
++ if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
++ {
++ // Read Back SDIO Local value
++ value = SdioLocalCmd52Read1Byte(padapter, offset);
++
++ value &= ~(GET_PWR_CFG_MASK(PwrCfgCmd));
++ value |= (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd));
++
++ // Write Back SDIO Local value
++ SdioLocalCmd52Write1Byte(padapter, offset, value);
++ }
++ else
++#endif
++ {
++ // Read the value from system register
++ value = rtw_read8(padapter, offset);
++
++ value &= ~(GET_PWR_CFG_MASK(PwrCfgCmd));
++ value |= (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd));
++
++ // Write the value back to sytem register
++ rtw_write8(padapter, offset, value);
++ }
++ break;
++
++ case PWR_CMD_POLLING:
++ RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_POLLING\n"));
++
++ bPollingBit = _FALSE;
++ offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
++
++ do {
++#ifdef CONFIG_SDIO_HCI
++ if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
++ value = SdioLocalCmd52Read1Byte(padapter, offset);
++ else
++#endif
++ value = rtw_read8(padapter, offset);
++
++ value &= GET_PWR_CFG_MASK(PwrCfgCmd);
++ if (value == (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd)))
++ bPollingBit = _TRUE;
++ else
++ rtw_udelay_os(10);
++
++ if (pollingCount++ > maxPollingCnt) {
++ RT_TRACE(_module_hal_init_c_ , _drv_err_, ("Fail to polling Offset[%#x]\n", offset));
++ return _FALSE;
++ }
++ } while (!bPollingBit);
++
++ break;
++
++ case PWR_CMD_DELAY:
++ RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_DELAY\n"));
++ if (GET_PWR_CFG_VALUE(PwrCfgCmd) == PWRSEQ_DELAY_US)
++ rtw_udelay_os(GET_PWR_CFG_OFFSET(PwrCfgCmd));
++ else
++ rtw_udelay_os(GET_PWR_CFG_OFFSET(PwrCfgCmd)*1000);
++ break;
++
++ case PWR_CMD_END:
++ // When this command is parsed, end the process
++ RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_END\n"));
++ return _TRUE;
++ break;
++
++ default:
++ RT_TRACE(_module_hal_init_c_ , _drv_err_, ("HalPwrSeqCmdParsing: Unknown CMD!!\n"));
++ break;
++ }
++ }
++
++ AryIdx++;//Add Array Index
++ }while(1);
++
++ return _TRUE;
++}
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/hal/rtl8192c/rtl8192c_cmd.c linux-xbian-rpi/drivers/net/wireless/rtl8192cu/hal/rtl8192c/rtl8192c_cmd.c
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/hal/rtl8192c/rtl8192c_cmd.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/hal/rtl8192c/rtl8192c_cmd.c 2015-07-28 01:20:58.309639981 +0200
+@@ -0,0 +1,1154 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#define _RTL8192C_CMD_C_
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++#include <recv_osdep.h>
++#include <cmd_osdep.h>
++#include <mlme_osdep.h>
++#include <rtw_byteorder.h>
++#include <circ_buf.h>
++#include <rtw_ioctl_set.h>
++
++#include <rtl8192c_hal.h>
++
++
++#define RTL92C_MAX_H2C_BOX_NUMS 4
++#define RTL92C_MAX_CMD_LEN 5
++#define MESSAGE_BOX_SIZE 4
++#define EX_MESSAGE_BOX_SIZE 2
++
++static u8 _is_fw_read_cmd_down(_adapter* padapter, u8 msgbox_num)
++{
++ u8 read_down = _FALSE;
++ int retry_cnts = 100;
++
++ u8 valid;
++
++// DBG_8192C(" _is_fw_read_cmd_down ,isnormal_chip(%x),reg_1cc(%x),msg_box(%d)...\n",isvern,rtw_read8(padapter,REG_HMETFR),msgbox_num);
++
++ do{
++ valid = rtw_read8(padapter,REG_HMETFR) & BIT(msgbox_num);
++ if(0 == valid ){
++ read_down = _TRUE;
++ }
++ }while( (!read_down) && (retry_cnts--));
++
++ return read_down;
++
++}
++
++
++/*****************************************
++* H2C Msg format :
++*| 31 - 8 |7 | 6 - 0 |
++*| h2c_msg |Ext_bit |CMD_ID |
++*
++******************************************/
++int rtl8192c_FillH2CCmd(_adapter* padapter, u8 ElementID, u32 CmdLen, u8* pCmdBuffer)
++{
++ u8 bcmd_down = _FALSE;
++ int retry_cnts = 100;
++ u8 h2c_box_num;
++ u32 msgbox_addr;
++ u32 msgbox_ex_addr;
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++ u32 h2c_cmd = 0;
++ u16 h2c_cmd_ex = 0;
++ int ret = _FAIL;
++
++_func_enter_;
++
++ padapter = GET_PRIMARY_ADAPTER(padapter);
++ pHalData = GET_HAL_DATA(padapter);
++
++ if(padapter->bFWReady == _FALSE)
++ {
++ DBG_8192C("FillH2CCmd(): return H2C cmd because fw is not ready\n");
++ return ret;
++ }
++
++ _enter_critical_mutex(&(adapter_to_dvobj(padapter)->h2c_fwcmd_mutex), NULL);
++
++ if(!pCmdBuffer){
++ goto exit;
++ }
++ if(CmdLen > RTL92C_MAX_CMD_LEN){
++ goto exit;
++ }
++ //pay attention to if race condition happened in H2C cmd setting.
++ do{
++ h2c_box_num = pHalData->LastHMEBoxNum;
++
++ if(!_is_fw_read_cmd_down(padapter, h2c_box_num)){
++ DBG_8192C(" fw read cmd failed...\n");
++ goto exit;
++ }
++
++ if(CmdLen<=3)
++ {
++ _rtw_memcpy((u8*)(&h2c_cmd)+1, pCmdBuffer, CmdLen );
++ }
++ else{
++ _rtw_memcpy((u8*)(&h2c_cmd_ex), pCmdBuffer, EX_MESSAGE_BOX_SIZE);
++ _rtw_memcpy((u8*)(&h2c_cmd)+1, pCmdBuffer+2,( CmdLen-EX_MESSAGE_BOX_SIZE));
++ *(u8*)(&h2c_cmd) |= BIT(7);
++ }
++
++ *(u8*)(&h2c_cmd) |= ElementID;
++
++ if(h2c_cmd & BIT(7)){
++ msgbox_ex_addr = REG_HMEBOX_EXT_0 + (h2c_box_num *EX_MESSAGE_BOX_SIZE);
++ h2c_cmd_ex = cpu_to_le16( h2c_cmd_ex );
++ rtw_write16(padapter, msgbox_ex_addr, h2c_cmd_ex);
++ }
++ msgbox_addr =REG_HMEBOX_0 + (h2c_box_num *MESSAGE_BOX_SIZE);
++ h2c_cmd = cpu_to_le32( h2c_cmd );
++ rtw_write32(padapter,msgbox_addr, h2c_cmd);
++
++ bcmd_down = _TRUE;
++
++ // DBG_8192C("MSG_BOX:%d,CmdLen(%d), reg:0x%x =>h2c_cmd:0x%x, reg:0x%x =>h2c_cmd_ex:0x%x ..\n"
++ // ,pHalData->LastHMEBoxNum ,CmdLen,msgbox_addr,h2c_cmd,msgbox_ex_addr,h2c_cmd_ex);
++
++ pHalData->LastHMEBoxNum = (h2c_box_num+1) % RTL92C_MAX_H2C_BOX_NUMS ;
++
++ }while((!bcmd_down) && (retry_cnts--));
++/*
++ if(bcmd_down)
++ DBG_8192C("H2C Cmd exe down. \n" );
++ else
++ DBG_8192C("H2C Cmd exe failed. \n" );
++*/
++ ret = _SUCCESS;
++
++exit:
++
++ _exit_critical_mutex(&(adapter_to_dvobj(padapter)->h2c_fwcmd_mutex), NULL);
++
++_func_exit_;
++
++ return ret;
++
++}
++
++u8 rtl8192c_h2c_msg_hdl(_adapter *padapter, unsigned char *pbuf)
++{
++ u8 ElementID, CmdLen;
++ u8 *pCmdBuffer;
++ struct cmd_msg_parm *pcmdmsg;
++
++ if(!pbuf)
++ return H2C_PARAMETERS_ERROR;
++
++ pcmdmsg = (struct cmd_msg_parm*)pbuf;
++ ElementID = pcmdmsg->eid;
++ CmdLen = pcmdmsg->sz;
++ pCmdBuffer = pcmdmsg->buf;
++
++ rtl8192c_FillH2CCmd(padapter, ElementID, CmdLen, pCmdBuffer);
++
++ return H2C_SUCCESS;
++}
++
++#if defined(CONFIG_AUTOSUSPEND) && defined(SUPPORT_HW_RFOFF_DETECTED)
++u8 rtl8192c_set_FwSelectSuspend_cmd(_adapter *padapter ,u8 bfwpoll, u16 period)
++{
++ u8 res=_SUCCESS;
++ struct H2C_SS_RFOFF_PARAM param;
++ DBG_8192C("==>%s bfwpoll(%x)\n",__FUNCTION__,bfwpoll);
++ param.gpio_period = period;//Polling GPIO_11 period time
++ param.ROFOn = (_TRUE == bfwpoll)?1:0;
++ rtl8192c_FillH2CCmd(padapter, SELECTIVE_SUSPEND_ROF_CMD, sizeof(param), (u8*)(&param));
++ return res;
++}
++#endif //CONFIG_AUTOSUSPEND && SUPPORT_HW_RFOFF_DETECTED
++
++u8 rtl8192c_set_rssi_cmd(_adapter*padapter, u8 *param)
++{
++ u8 res=_SUCCESS;
++
++_func_enter_;
++
++ *((u32*) param ) = cpu_to_le32( *((u32*) param ) );
++
++ rtl8192c_FillH2CCmd(padapter, RSSI_SETTING_EID, 3, param);
++
++_func_exit_;
++
++ return res;
++}
++
++u8 rtl8192c_set_raid_cmd(_adapter*padapter, u32 mask, u8 arg)
++{
++ u8 buf[5];
++ u8 res=_SUCCESS;
++
++_func_enter_;
++
++ _rtw_memset(buf, 0, 5);
++ mask = cpu_to_le32( mask );
++ _rtw_memcpy(buf, &mask, 4);
++ buf[4] = arg;
++
++ rtl8192c_FillH2CCmd(padapter, MACID_CONFIG_EID, 5, buf);
++
++_func_exit_;
++
++ return res;
++
++}
++
++//bitmap[0:27] = tx_rate_bitmap
++//bitmap[28:31]= Rate Adaptive id
++//arg[0:4] = macid
++//arg[5] = Short GI
++void rtl8192c_Add_RateATid(PADAPTER pAdapter, u32 bitmap, u8 arg)
++{
++
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
++
++ if(pHalData->fw_ractrl == _TRUE)
++ {
++ rtl8192c_set_raid_cmd(pAdapter, bitmap, arg);
++ }
++ else
++ {
++ u8 macid, init_rate, shortGIrate=_FALSE;
++
++ init_rate = get_highest_rate_idx(bitmap&0x0fffffff)&0x3f;
++
++ macid = arg&0x1f;
++
++ shortGIrate = (arg&BIT(5)) ? _TRUE:_FALSE;
++
++ if (shortGIrate==_TRUE)
++ init_rate |= BIT(6);
++
++ rtw_write8(pAdapter, (REG_INIDATA_RATE_SEL+macid), (u8)init_rate);
++ }
++
++}
++
++void rtl8192c_set_FwPwrMode_cmd(_adapter*padapter, u8 Mode)
++{
++ SETPWRMODE_PARM H2CSetPwrMode;
++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
++
++_func_enter_;
++
++ DBG_871X("%s(): Mode = %d, SmartPS = %d\n", __FUNCTION__,Mode,pwrpriv->smart_ps);
++
++ H2CSetPwrMode.Mode = Mode;
++
++ H2CSetPwrMode.SmartPS = pwrpriv->smart_ps;
++
++ H2CSetPwrMode.BcnPassTime = 1;//pPSC->RegMaxLPSAwakeIntvl;
++
++ rtl8192c_FillH2CCmd(padapter, SET_PWRMODE_EID, sizeof(H2CSetPwrMode), (u8 *)&H2CSetPwrMode);
++
++_func_exit_;
++}
++
++void ConstructBeacon(_adapter *padapter, u8 *pframe, u32 *pLength)
++{
++ struct rtw_ieee80211_hdr *pwlanhdr;
++ u16 *fctrl;
++ u32 rate_len, pktlen;
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network);
++ u8 bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
++
++
++ //DBG_871X("%s\n", __FUNCTION__);
++
++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++ fctrl = &(pwlanhdr->frame_ctl);
++ *(fctrl) = 0;
++
++ _rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(cur_network), ETH_ALEN);
++
++ SetSeqNum(pwlanhdr, 0/*pmlmeext->mgnt_seq*/);
++ //pmlmeext->mgnt_seq++;
++ SetFrameSubType(pframe, WIFI_BEACON);
++
++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
++ pktlen = sizeof (struct rtw_ieee80211_hdr_3addr);
++
++ //timestamp will be inserted by hardware
++ pframe += 8;
++ pktlen += 8;
++
++ // beacon interval: 2 bytes
++ _rtw_memcpy(pframe, (unsigned char *)(rtw_get_beacon_interval_from_ie(cur_network->IEs)), 2);
++
++ pframe += 2;
++ pktlen += 2;
++
++ // capability info: 2 bytes
++ _rtw_memcpy(pframe, (unsigned char *)(rtw_get_capability_from_ie(cur_network->IEs)), 2);
++
++ pframe += 2;
++ pktlen += 2;
++
++ if( (pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE)
++ {
++ //DBG_871X("ie len=%d\n", cur_network->IELength);
++ pktlen += cur_network->IELength - sizeof(NDIS_802_11_FIXED_IEs);
++ _rtw_memcpy(pframe, cur_network->IEs+sizeof(NDIS_802_11_FIXED_IEs), pktlen);
++
++ goto _ConstructBeacon;
++ }
++
++ //below for ad-hoc mode
++
++ // SSID
++ pframe = rtw_set_ie(pframe, _SSID_IE_, cur_network->Ssid.SsidLength, cur_network->Ssid.Ssid, &pktlen);
++
++ // supported rates...
++ rate_len = rtw_get_rateset_len(cur_network->SupportedRates);
++ pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, ((rate_len > 8)? 8: rate_len), cur_network->SupportedRates, &pktlen);
++
++ // DS parameter set
++ pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&(cur_network->Configuration.DSConfig), &pktlen);
++
++ if( (pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE)
++ {
++ u32 ATIMWindow;
++ // IBSS Parameter Set...
++ //ATIMWindow = cur->Configuration.ATIMWindow;
++ ATIMWindow = 0;
++ pframe = rtw_set_ie(pframe, _IBSS_PARA_IE_, 2, (unsigned char *)(&ATIMWindow), &pktlen);
++ }
++
++
++ //todo: ERP IE
++
++
++ // EXTERNDED SUPPORTED RATE
++ if (rate_len > 8)
++ {
++ pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (rate_len - 8), (cur_network->SupportedRates + 8), &pktlen);
++ }
++
++
++ //todo:HT for adhoc
++
++_ConstructBeacon:
++
++ if ((pktlen + TXDESC_SIZE) > 512)
++ {
++ DBG_871X("beacon frame too large\n");
++ return;
++ }
++
++ *pLength = pktlen;
++
++ //DBG_871X("%s bcn_sz=%d\n", __FUNCTION__, pktlen);
++
++}
++
++void ConstructPSPoll(_adapter *padapter, u8 *pframe, u32 *pLength)
++{
++ struct rtw_ieee80211_hdr *pwlanhdr;
++ u16 *fctrl;
++ u32 pktlen;
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++
++ //DBG_871X("%s\n", __FUNCTION__);
++
++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++ // Frame control.
++ fctrl = &(pwlanhdr->frame_ctl);
++ *(fctrl) = 0;
++ SetPwrMgt(fctrl);
++ SetFrameSubType(pframe, WIFI_PSPOLL);
++
++ // AID.
++ SetDuration(pframe, (pmlmeinfo->aid | 0xc000));
++
++ // BSSID.
++ _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
++
++ // TA.
++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN);
++
++ *pLength = 16;
++}
++
++void ConstructNullFunctionData(_adapter *padapter, u8 *pframe, u32 *pLength, u8 *StaAddr, BOOLEAN bForcePowerSave)
++{
++ struct rtw_ieee80211_hdr *pwlanhdr;
++ u16 *fctrl;
++ u32 pktlen;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct wlan_network *cur_network = &pmlmepriv->cur_network;
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++
++ //DBG_871X("%s:%d\n", __FUNCTION__, bForcePowerSave);
++
++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++ fctrl = &(pwlanhdr->frame_ctl);
++ *(fctrl) = 0;
++ if (bForcePowerSave)
++ {
++ SetPwrMgt(fctrl);
++ }
++
++ switch(cur_network->network.InfrastructureMode)
++ {
++ case Ndis802_11Infrastructure:
++ SetToDs(fctrl);
++ _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr3, StaAddr, ETH_ALEN);
++ break;
++ case Ndis802_11APMode:
++ SetFrDs(fctrl);
++ _rtw_memcpy(pwlanhdr->addr1, StaAddr, ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr2, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr3, myid(&(padapter->eeprompriv)), ETH_ALEN);
++ break;
++ case Ndis802_11IBSS:
++ default:
++ _rtw_memcpy(pwlanhdr->addr1, StaAddr, ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
++ break;
++ }
++
++ SetSeqNum(pwlanhdr, 0);
++
++ SetFrameSubType(pframe, WIFI_DATA_NULL);
++
++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
++ pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++
++ *pLength = pktlen;
++}
++
++void ConstructProbeRsp(_adapter *padapter, u8 *pframe, u32 *pLength, u8 *StaAddr, BOOLEAN bHideSSID)
++{
++ struct rtw_ieee80211_hdr *pwlanhdr;
++ u16 *fctrl;
++ u8 *mac, *bssid;
++ u32 pktlen;
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network);
++
++
++ //DBG_871X("%s\n", __FUNCTION__);
++
++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++ mac = myid(&(padapter->eeprompriv));
++ bssid = cur_network->MacAddress;
++
++ fctrl = &(pwlanhdr->frame_ctl);
++ *(fctrl) = 0;
++ _rtw_memcpy(pwlanhdr->addr1, StaAddr, ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr3, bssid, ETH_ALEN);
++
++ SetSeqNum(pwlanhdr, 0);
++ SetFrameSubType(fctrl, WIFI_PROBERSP);
++
++ pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++ pframe += pktlen;
++
++ if(cur_network->IELength>MAX_IE_SZ)
++ return;
++
++ _rtw_memcpy(pframe, cur_network->IEs, cur_network->IELength);
++ pframe += cur_network->IELength;
++ pktlen += cur_network->IELength;
++
++ *pLength = pktlen;
++}
++
++//
++// Description: In normal chip, we should send some packet to Hw which will be used by Fw
++// in FW LPS mode. The function is to fill the Tx descriptor of this packets, then
++// Fw can tell Hw to send these packet derectly.
++// Added by tynli. 2009.10.15.
++//
++static VOID
++FillFakeTxDescriptor92C(
++ IN PADAPTER Adapter,
++ IN u8* pDesc,
++ IN u32 BufferLen,
++ IN BOOLEAN IsPsPoll
++)
++{
++ struct tx_desc *ptxdesc = (struct tx_desc *)pDesc;
++
++ // Clear all status
++ _rtw_memset(pDesc, 0, 32);
++
++ //offset 0
++ ptxdesc->txdw0 |= cpu_to_le32( OWN | FSG | LSG); //own, bFirstSeg, bLastSeg;
++
++ ptxdesc->txdw0 |= cpu_to_le32(((TXDESC_SIZE+OFFSET_SZ)<<OFFSET_SHT)&0x00ff0000); //32 bytes for TX Desc
++
++ ptxdesc->txdw0 |= cpu_to_le32(BufferLen&0x0000ffff); // Buffer size + command header
++
++ //offset 4
++ ptxdesc->txdw1 |= cpu_to_le32((QSLT_MGNT<<QSEL_SHT)&0x00001f00); // Fixed queue of Mgnt queue
++
++ //Set NAVUSEHDR to prevent Ps-poll AId filed to be changed to error vlaue by Hw.
++ if(IsPsPoll)
++ {
++ ptxdesc->txdw1 |= cpu_to_le32(NAVUSEHDR);
++ }
++ else
++ {
++ ptxdesc->txdw4 |= cpu_to_le32(BIT(7)); // Hw set sequence number
++ ptxdesc->txdw3 |= cpu_to_le32((8 <<28)); //set bit3 to 1. Suugested by TimChen. 2009.12.29.
++ }
++
++ //offset 16
++ ptxdesc->txdw4 |= cpu_to_le32(BIT(8));//driver uses rate
++
++#ifdef CONFIG_USB_HCI
++ // USB interface drop packet if the checksum of descriptor isn't correct.
++ // Using this checksum can let hardware recovery from packet bulk out error (e.g. Cancel URC, Bulk out error.).
++ rtl8192cu_cal_txdesc_chksum(ptxdesc);
++#endif
++
++ //RT_PRINT_DATA(COMP_CMD, DBG_TRACE, "TxFillCmdDesc8192C(): H2C Tx Cmd Content ----->\n", pDesc, TX_DESC_SIZE);
++}
++
++// To check if reserved page content is destroyed by beacon beacuse beacon is too large.
++// 2010.06.23. Added by tynli.
++VOID
++CheckFwRsvdPageContent(
++ IN PADAPTER Adapter
++)
++{
++ HAL_DATA_TYPE* pHalData = GET_HAL_DATA(Adapter);
++ u32 MaxBcnPageNum;
++
++ if(pHalData->FwRsvdPageStartOffset != 0)
++ {
++ /*MaxBcnPageNum = PageNum_128(pMgntInfo->MaxBeaconSize);
++ RT_ASSERT((MaxBcnPageNum <= pHalData->FwRsvdPageStartOffset),
++ ("CheckFwRsvdPageContent(): The reserved page content has been"\
++ "destroyed by beacon!!! MaxBcnPageNum(%d) FwRsvdPageStartOffset(%d)\n!",
++ MaxBcnPageNum, pHalData->FwRsvdPageStartOffset));*/
++ }
++}
++
++//
++// Description: Fill the reserved packets that FW will use to RSVD page.
++// Now we just send 4 types packet to rsvd page.
++// (1)Beacon, (2)Ps-poll, (3)Null data, (4)ProbeRsp.
++// Input:
++// bDLFinished - FALSE: At the first time we will send all the packets as a large packet to Hw,
++// so we need to set the packet length to total lengh.
++// TRUE: At the second time, we should send the first packet (default:beacon)
++// to Hw again and set the lengh in descriptor to the real beacon lengh.
++// 2009.10.15 by tynli.
++static void SetFwRsvdPagePkt(PADAPTER Adapter, BOOLEAN bDLFinished)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ struct xmit_frame *pmgntframe;
++ struct pkt_attrib *pattrib;
++ struct xmit_priv *pxmitpriv = &(Adapter->xmitpriv);
++ struct mlme_ext_priv *pmlmeext = &(Adapter->mlmeextpriv);
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ u32 BeaconLength, ProbeRspLength, PSPollLength, NullFunctionDataLength;
++ u8 *ReservedPagePacket;
++ u8 PageNum=0, U1bTmp, TxDescLen=0, TxDescOffset=0;
++ u16 BufIndex=0;
++ u32 TotalPacketLen;
++ RSVDPAGE_LOC RsvdPageLoc;
++ BOOLEAN bDLOK = _FALSE;
++
++ DBG_871X("%s\n", __FUNCTION__);
++
++ ReservedPagePacket = (u8*)rtw_malloc(1000);
++ if(ReservedPagePacket == NULL){
++ DBG_871X("%s(): alloc ReservedPagePacket fail !!!\n", __FUNCTION__);
++ return;
++ }
++
++ _rtw_memset(ReservedPagePacket, 0, 1000);
++
++ TxDescLen = 32;//TX_DESC_SIZE;
++
++#ifdef CONFIG_USB_HCI
++ BufIndex = TXDESC_OFFSET;
++ TxDescOffset = TxDescLen+8; //Shift index for 8 bytes because the dummy bytes in the first descipstor.
++#else
++ BufIndex = 0;
++ TxDescOffset = 0;
++#endif
++
++ //(1) beacon
++ ConstructBeacon(Adapter,&ReservedPagePacket[BufIndex],&BeaconLength);
++
++ //DBG_8192C("SetFwRsvdPagePkt(): HW_VAR_SET_TX_CMD: BCN\n", &ReservedPagePacket[BufIndex], (BeaconLength+BufIndex));
++
++//--------------------------------------------------------------------
++
++ // When we count the first page size, we need to reserve description size for the RSVD
++ // packet, it will be filled in front of the packet in TXPKTBUF.
++ U1bTmp = (u8)PageNum_128(BeaconLength+TxDescLen);
++ PageNum += U1bTmp;
++ // To reserved 2 pages for beacon buffer. 2010.06.24.
++ if(PageNum == 1)
++ PageNum+=1;
++ pHalData->FwRsvdPageStartOffset = PageNum;
++
++ BufIndex = (PageNum*128) + TxDescOffset;
++
++ //(2) ps-poll
++ ConstructPSPoll(Adapter, &ReservedPagePacket[BufIndex],&PSPollLength);
++
++ FillFakeTxDescriptor92C(Adapter, &ReservedPagePacket[BufIndex-TxDescLen], PSPollLength, _TRUE);
++
++ //DBG_8192C("SetFwRsvdPagePkt(): HW_VAR_SET_TX_CMD: PS-POLL\n", &ReservedPagePacket[BufIndex-TxDescLen], (PSPollLength+TxDescLen));
++
++ RsvdPageLoc.LocPsPoll = PageNum;
++
++//------------------------------------------------------------------
++
++ U1bTmp = (u8)PageNum_128(PSPollLength+TxDescLen);
++ PageNum += U1bTmp;
++
++ BufIndex = (PageNum*128) + TxDescOffset;
++
++ //(3) null data
++ ConstructNullFunctionData(
++ Adapter,
++ &ReservedPagePacket[BufIndex],
++ &NullFunctionDataLength,
++ get_my_bssid(&(pmlmeinfo->network)),
++ _FALSE);
++
++ FillFakeTxDescriptor92C(Adapter, &ReservedPagePacket[BufIndex-TxDescLen], NullFunctionDataLength, _FALSE);
++
++ RsvdPageLoc.LocNullData = PageNum;
++
++ //DBG_8192C("SetFwRsvdPagePkt(): HW_VAR_SET_TX_CMD: NULL DATA \n", &ReservedPagePacket[BufIndex-TxDescLen], (NullFunctionDataLength+TxDescLen));
++//------------------------------------------------------------------
++
++ U1bTmp = (u8)PageNum_128(NullFunctionDataLength+TxDescLen);
++ PageNum += U1bTmp;
++
++ BufIndex = (PageNum*128) + TxDescOffset;
++
++ //(4) probe response
++ ConstructProbeRsp(
++ Adapter,
++ &ReservedPagePacket[BufIndex],
++ &ProbeRspLength,
++ get_my_bssid(&(pmlmeinfo->network)),
++ _FALSE);
++
++ FillFakeTxDescriptor92C(Adapter, &ReservedPagePacket[BufIndex-TxDescLen], ProbeRspLength, _FALSE);
++
++ RsvdPageLoc.LocProbeRsp = PageNum;
++
++ //DBG_8192C("SetFwRsvdPagePkt(): HW_VAR_SET_TX_CMD: PROBE RSP \n", &ReservedPagePacket[BufIndex-TxDescLen], (ProbeRspLength-TxDescLen));
++
++//------------------------------------------------------------------
++
++ U1bTmp = (u8)PageNum_128(ProbeRspLength+TxDescLen);
++
++ PageNum += U1bTmp;
++
++ TotalPacketLen = (PageNum*128);
++
++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL)
++ {
++ return;
++ }
++
++ //update attribute
++ pattrib = &pmgntframe->attrib;
++ update_mgntframe_attrib(Adapter, pattrib);
++ pattrib->qsel = 0x10;
++ pattrib->pktlen = pattrib->last_txcmdsz = TotalPacketLen - TxDescLen;
++ _rtw_memcpy(pmgntframe->buf_addr, ReservedPagePacket, TotalPacketLen);
++
++ rtw_hal_mgnt_xmit(Adapter, pmgntframe);
++
++ bDLOK = _TRUE;
++
++ if(bDLOK)
++ {
++ DBG_871X("Set RSVD page location to Fw.\n");
++ rtl8192c_FillH2CCmd(Adapter, RSVD_PAGE_EID, sizeof(RsvdPageLoc), (u8 *)&RsvdPageLoc);
++ }
++
++ rtw_mfree(ReservedPagePacket,1000);
++
++}
++
++void rtl8192c_set_FwJoinBssReport_cmd(_adapter* padapter, u8 mstatus)
++{
++ JOINBSSRPT_PARM JoinBssRptParm;
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++
++_func_enter_;
++
++ DBG_871X("%s mstatus(%x)\n", __FUNCTION__,mstatus);
++
++ if(mstatus == 1)
++ {
++ BOOLEAN bRecover = _FALSE;
++
++ // We should set AID, correct TSF, HW seq enable before set JoinBssReport to Fw in 88/92C.
++ // Suggested by filen. Added by tynli.
++ rtw_write16(padapter, REG_BCN_PSR_RPT, (0xC000|pmlmeinfo->aid));
++ // Do not set TSF again here or vWiFi beacon DMA INT will not work.
++ //correct_TSF(padapter, pmlmeext);
++ // Hw sequende enable by dedault. 2010.06.23. by tynli.
++ //rtw_write16(padapter, REG_NQOS_SEQ, ((pmlmeext->mgnt_seq+100)&0xFFF));
++ //rtw_write8(padapter, REG_HWSEQ_CTRL, 0xFF);
++
++ //set REG_CR bit 8
++ //U1bTmp = rtw_read8(padapter, REG_CR+1);
++ rtw_write8(padapter, REG_CR+1, 0x03);
++
++ // Disable Hw protection for a time which revserd for Hw sending beacon.
++ // Fix download reserved page packet fail that access collision with the protection time.
++ // 2010.05.11. Added by tynli.
++ //SetBcnCtrlReg(padapter, 0, BIT3);
++ //SetBcnCtrlReg(padapter, BIT4, 0);
++ rtw_write8(padapter, REG_BCN_CTRL, rtw_read8(padapter, REG_BCN_CTRL)&(~BIT(3)));
++ rtw_write8(padapter, REG_BCN_CTRL, rtw_read8(padapter, REG_BCN_CTRL)|BIT(4));
++
++ // Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.
++ if(pHalData->RegFwHwTxQCtrl&BIT6)
++ bRecover = _TRUE;
++
++ // To tell Hw the packet is not a real beacon frame.
++ //U1bTmp = rtw_read8(padapter, REG_FWHW_TXQ_CTRL+2);
++ rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, (pHalData->RegFwHwTxQCtrl&(~BIT6)));
++ pHalData->RegFwHwTxQCtrl &= (~BIT6);
++ SetFwRsvdPagePkt(padapter, 0);
++
++ // 2010.05.11. Added by tynli.
++ //SetBcnCtrlReg(padapter, BIT3, 0);
++ //SetBcnCtrlReg(padapter, 0, BIT4);
++ rtw_write8(padapter, REG_BCN_CTRL, rtw_read8(padapter, REG_BCN_CTRL)|BIT(3));
++ rtw_write8(padapter, REG_BCN_CTRL, rtw_read8(padapter, REG_BCN_CTRL)&(~BIT(4)));
++
++ // To make sure that if there exists an adapter which would like to send beacon.
++ // If exists, the origianl value of 0x422[6] will be 1, we should check this to
++ // prevent from setting 0x422[6] to 0 after download reserved page, or it will cause
++ // the beacon cannot be sent by HW.
++ // 2010.06.23. Added by tynli.
++ if(bRecover)
++ {
++ rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, (pHalData->RegFwHwTxQCtrl|BIT6));
++ pHalData->RegFwHwTxQCtrl |= BIT6;
++ }
++
++ // Clear CR[8] or beacon packet will not be send to TxBuf anymore.
++ rtw_write8(padapter, REG_CR+1, 0x02);
++ }
++
++ JoinBssRptParm.OpMode = mstatus;
++
++ rtl8192c_FillH2CCmd(padapter, JOINBSS_RPT_EID, sizeof(JoinBssRptParm), (u8 *)&JoinBssRptParm);
++
++_func_exit_;
++}
++
++#ifdef CONFIG_P2P_PS
++void rtl8192c_set_p2p_ctw_period_cmd(_adapter* padapter, u8 ctwindow)
++{
++ struct P2P_PS_CTWPeriod_t p2p_ps_ctw;
++
++ p2p_ps_ctw.CTWPeriod = ctwindow;
++
++ rtl8192c_FillH2CCmd(padapter, P2P_PS_CTW_CMD_EID, 1, (u8 *)(&p2p_ps_ctw));
++
++}
++
++void rtl8192c_set_p2p_ps_offload_cmd(_adapter* padapter, u8 p2p_ps_state)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo );
++ struct P2P_PS_Offload_t *p2p_ps_offload = &pHalData->p2p_ps_offload;
++ u8 i;
++ u16 ctwindow;
++ u32 start_time, tsf_low;
++
++_func_enter_;
++
++ switch(p2p_ps_state)
++ {
++ case P2P_PS_DISABLE:
++ DBG_8192C("P2P_PS_DISABLE \n");
++ _rtw_memset(p2p_ps_offload, 0 ,1);
++ break;
++ case P2P_PS_ENABLE:
++ DBG_8192C("P2P_PS_ENABLE \n");
++ // update CTWindow value.
++ if( pwdinfo->ctwindow > 0 )
++ {
++ p2p_ps_offload->CTWindow_En = 1;
++ ctwindow = pwdinfo->ctwindow;
++ if(IS_HARDWARE_TYPE_8723A(padapter))
++ {
++ //rtw_write16(padapter, REG_ATIMWND, ctwindow);
++ }
++ else
++ {
++ rtl8192c_set_p2p_ctw_period_cmd(padapter, ctwindow);
++ }
++ }
++
++ // hw only support 2 set of NoA
++ for( i=0 ; i<pwdinfo->noa_num ; i++)
++ {
++ // To control the register setting for which NOA
++ rtw_write8(padapter, 0x5CF, (i << 4));
++ if(i == 0)
++ p2p_ps_offload->NoA0_En = 1;
++ else
++ p2p_ps_offload->NoA1_En = 1;
++
++ // config P2P NoA Descriptor Register
++ rtw_write32(padapter, 0x5E0, pwdinfo->noa_duration[i]);
++
++ rtw_write32(padapter, 0x5E4, pwdinfo->noa_interval[i]);
++
++ //Get Current TSF value
++ tsf_low = rtw_read32(padapter, REG_TSFTR);
++
++ start_time = pwdinfo->noa_start_time[i];
++ if(pwdinfo->noa_count[i] != 1)
++ {
++ while( start_time <= (tsf_low+(50*1024) ) )
++ {
++ start_time += pwdinfo->noa_interval[i];
++ if(pwdinfo->noa_count[i] != 255)
++ pwdinfo->noa_count[i]--;
++ }
++ }
++ //DBG_8192C("%s(): start_time = %x\n",__FUNCTION__,start_time);
++ rtw_write32(padapter, 0x5E8, start_time);
++
++ rtw_write8(padapter, 0x5EC, pwdinfo->noa_count[i]);
++ }
++
++ if( (pwdinfo->opp_ps == 1) || (pwdinfo->noa_num > 0) )
++ {
++ // rst p2p circuit
++ rtw_write8(padapter, REG_DUAL_TSF_RST, BIT(4));
++
++ p2p_ps_offload->Offload_En = 1;
++
++ if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO))
++ {
++ p2p_ps_offload->role= 1;
++ p2p_ps_offload->AllStaSleep = 0;
++ }
++ else
++ {
++ p2p_ps_offload->role= 0;
++ }
++
++ p2p_ps_offload->discovery = 0;
++ }
++ break;
++ case P2P_PS_SCAN:
++ DBG_8192C("P2P_PS_SCAN \n");
++ p2p_ps_offload->discovery = 1;
++ break;
++ case P2P_PS_SCAN_DONE:
++ DBG_8192C("P2P_PS_SCAN_DONE \n");
++ p2p_ps_offload->discovery = 0;
++ pwdinfo->p2p_ps_state = P2P_PS_ENABLE;
++ break;
++ default:
++ break;
++ }
++
++ rtl8192c_FillH2CCmd(padapter, P2P_PS_OFFLOAD_EID, 1, (u8 *)p2p_ps_offload);
++
++_func_exit_;
++
++}
++#endif // CONFIG_P2P_PS
++
++#ifdef CONFIG_IOL
++#include <rtw_iol.h>
++int rtl8192c_IOL_exec_cmds_sync(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms)
++{
++ IO_OFFLOAD_LOC IoOffloadLoc;
++ u32 start_time = rtw_get_current_time();
++ u32 passing_time_ms;
++ u8 polling_ret;
++ int ret = _FAIL;
++
++ if (rtw_IOL_append_END_cmd(xmit_frame) != _SUCCESS)
++ goto exit;
++
++ dump_mgntframe_and_wait(adapter, xmit_frame, max_wating_ms);
++
++ IoOffloadLoc.LocCmd = 0;
++ if(_SUCCESS != rtl8192c_FillH2CCmd(adapter, H2C_92C_IO_OFFLOAD, sizeof(IO_OFFLOAD_LOC), (u8 *)&IoOffloadLoc))
++ goto exit;
++
++ //polling if the IO offloading is done
++ while( (passing_time_ms=rtw_get_passing_time_ms(start_time)) <= max_wating_ms) {
++ #if 0 //C2H
++ if(0xff == rtw_read8(adapter, REG_C2HEVT_CLEAR))
++ break;
++ #else// 0x1c3
++ if(0x00 != (polling_ret=rtw_read8(adapter, 0x1c3)))
++ break;
++ #endif
++ rtw_msleep_os(5);
++ }
++ #if 0 //debug
++ DBG_871X("IOL %s, polling_ret:0x%02x, 0x1c0=0x%08x, 0x1c4=0x%08x, 0x1cc=0x%08x, 0x1e8=0x%08x, 0x130=0x%08x, 0x134=0x%08x\n"
++ , polling_ret==0xff?"success":"error"
++ , polling_ret
++ , rtw_read32(adapter, 0x1c0)
++ , rtw_read32(adapter, 0x1c4)
++ , rtw_read32(adapter, 0x1cc)
++ , rtw_read32(adapter, 0x1e8)
++ , rtw_read32(adapter, 0x130)
++ , rtw_read32(adapter, 0x134)
++ );
++ rtw_write32(adapter, 0x1c0, 0x0);
++ #endif
++
++ if(polling_ret == 0xff)
++ ret =_SUCCESS;
++ else {
++ DBG_871X("IOL %s, polling_ret:0x%02x\n"
++ //", 0x1c0=0x%08x, 0x1c4=0x%08x, 0x1cc=0x%08x, 0x1e8=0x%08x, 0x130=0x%08x, 0x134=0x%08x\n"
++ , polling_ret==0xff?"success":"error"
++ , polling_ret
++ //, rtw_read32(adapter, 0x1c0)
++ //, rtw_read32(adapter, 0x1c4)
++ //, rtw_read32(adapter, 0x1cc)
++ //, rtw_read32(adapter, 0x1e8)
++ //, rtw_read32(adapter, 0x130)
++ //, rtw_read32(adapter, 0x134)
++ );
++ #if 0 //debug
++ rtw_write16(adapter, 0x1c4, 0x0000);
++ rtw_msleep_os(10);
++ DBG_871X("after reset, 0x1c4=0x%08x\n", rtw_read32(adapter, 0x1c4));
++ #endif
++
++ }
++
++ {
++ #if 0 //C2H
++ u32 c2h_evt;
++ int i;
++ c2h_evt = rtw_read32(adapter, REG_C2HEVT_MSG_NORMAL);
++ DBG_871X("%s io-offloading complete, in %ums: 0x%08x\n", __FUNCTION__, passing_time_ms, c2h_evt);
++ rtw_write8(adapter, REG_C2HEVT_CLEAR, 0x0);
++ #else// 0x1c3
++ DBG_871X("IOL %s complete in %ums\n", __FUNCTION__, passing_time_ms);
++ rtw_write8(adapter, 0x1c3, 0x0);
++ #endif
++ }
++
++exit:
++ return ret;
++
++}
++#endif //CONFIG_IOL
++
++
++#ifdef CONFIG_BEACON_DISABLE_OFFLOAD
++/*
++ rtl8192c_dis_beacon_fun_cmd()
++ This function shall only be called by PORT1.
++ PORT0's beacon function can't be disabled, because it's used by RA function in FW/HW.
++
++ // Still has the REG_BCN_CTRL_1 modified by unknowned party issue in case of Primary Interface + PORT1 combination.
++*/
++u8 rtl8192c_dis_beacon_fun_cmd(_adapter* padapter)
++{
++ u8 buf[2];
++ u8 res=_SUCCESS;
++
++_func_enter_;
++
++ _rtw_memset(buf, 0, sizeof(buf));
++
++ if (padapter->iface_type == IFACE_PORT0) {
++ //buf[0] = 0x1;
++ DBG_871X("%s(): ERROR! padapter->iface_type = %d\n", __FUNCTION__, padapter->iface_type);
++ return _FAIL;
++ } else
++ buf[1] = 0x1;
++
++ rtl8192c_FillH2CCmd(padapter, H2C_92C_DISABLE_BCN_FUNC, 2, buf);
++
++_func_exit_;
++
++ return res;
++
++}
++#endif // CONFIG_BEACON_DISABLE_OFFLOAD
++
++
++#ifdef CONFIG_TSF_RESET_OFFLOAD
++/*
++ ask FW to Reset sync register at Beacon early interrupt
++*/
++u8 rtl8192c_reset_tsf(_adapter *padapter, u8 reset_port )
++{
++ u8 buf[2];
++ u8 res=_SUCCESS;
++
++_func_enter_;
++ if (IFACE_PORT0==reset_port) {
++ buf[0] = 0x1; buf[1] = 0;
++
++ } else{
++ buf[0] = 0x0; buf[1] = 0x1;
++ }
++ rtl8192c_FillH2CCmd(padapter, H2C_92C_RESET_TSF, 2, buf);
++_func_exit_;
++
++ return res;
++}
++
++int reset_tsf(PADAPTER Adapter, u8 reset_port )
++{
++ u8 reset_cnt_before = 0, reset_cnt_after = 0, loop_cnt = 0;
++ u32 reg_reset_tsf_cnt = (IFACE_PORT0==reset_port) ?
++ REG_FW_RESET_TSF_CNT_0:REG_FW_RESET_TSF_CNT_1;
++
++ rtw_scan_abort(Adapter->pbuddy_adapter); /* site survey will cause reset_tsf fail */
++ reset_cnt_after = reset_cnt_before = rtw_read8(Adapter,reg_reset_tsf_cnt);
++ rtl8192c_reset_tsf(Adapter, reset_port);
++
++ while ((reset_cnt_after == reset_cnt_before ) && (loop_cnt < 10)) {
++ rtw_msleep_os(100);
++ loop_cnt++;
++ reset_cnt_after = rtw_read8(Adapter, reg_reset_tsf_cnt);
++ }
++
++ return(loop_cnt >= 10) ? _FAIL : _TRUE;
++}
++
++
++#endif // CONFIG_TSF_RESET_OFFLOAD
++
++#ifdef CONFIG_WOWLAN
++
++void rtl8192c_set_wowlan_cmd(_adapter* padapter)
++{
++ u8 res=_SUCCESS;
++ SETWOWLAN_PARM pwowlan_parm;
++ struct pwrctrl_priv *pwrpriv=&padapter->pwrctrlpriv;
++
++_func_enter_;
++
++ pwowlan_parm.mode =0;
++ pwowlan_parm.gpio_index=0;
++ pwowlan_parm.gpio_duration=0;
++ pwowlan_parm.second_mode =0;
++ pwowlan_parm.reserve=0;
++
++ if(pwrpriv->wowlan_mode ==_TRUE){
++ pwowlan_parm.mode |=FW_WOWLAN_FUN_EN;
++ //printk("\n %s 1.pwowlan_parm.mode=0x%x \n",__FUNCTION__,pwowlan_parm.mode );
++ if(pwrpriv->wowlan_pattern ==_TRUE){
++ pwowlan_parm.mode |= FW_WOWLAN_PATTERN_MATCH;
++ //printk("\n %s 2.pwowlan_parm.mode=0x%x \n",__FUNCTION__,pwowlan_parm.mode );
++ }
++ if(pwrpriv->wowlan_magic ==_TRUE){
++ pwowlan_parm.mode |=FW_WOWLAN_MAGIC_PKT;
++ //printk("\n %s 3.pwowlan_parm.mode=0x%x \n",__FUNCTION__,pwowlan_parm.mode );
++ }
++ if(pwrpriv->wowlan_unicast ==_TRUE){
++ pwowlan_parm.mode |=FW_WOWLAN_UNICAST;
++ //printk("\n %s 4.pwowlan_parm.mode=0x%x \n",__FUNCTION__,pwowlan_parm.mode );
++ }
++ //WOWLAN_GPIO_ACTIVE means GPIO high active
++ //pwowlan_parm.mode |=FW_WOWLAN_GPIO_ACTIVE;
++ pwowlan_parm.mode |=FW_WOWLAN_REKEY_WAKEUP;
++ pwowlan_parm.mode |=FW_WOWLAN_DEAUTH_WAKEUP;
++
++ rtl8192c_set_FwJoinBssReport_cmd( padapter, 1);
++
++ //GPIO3
++ pwowlan_parm.gpio_index=3;
++
++ //duration unit is 64us
++ pwowlan_parm.gpio_duration=0xff;
++ //
++ pwowlan_parm.second_mode|=FW_WOWLAN_GPIO_WAKEUP_EN;
++ //printk("\n %s 5.pwowlan_parm.mode=0x%x \n",__FUNCTION__,pwowlan_parm.mode );
++ { u8 *ptr=(u8 *)&pwowlan_parm;
++ printk("\n %s H2C_WO_WLAN=%x %02x:%02x:%02x:%02x:%02x \n",__FUNCTION__,H2C_WO_WLAN_CMD,ptr[0],ptr[1],ptr[2],ptr[3],ptr[4] );
++ }
++ rtl8192c_FillH2CCmd(padapter, H2C_WO_WLAN_CMD, 4, (u8 *)&pwowlan_parm);
++
++ //keep alive period = 3 * 10 BCN interval
++ pwowlan_parm.mode =3;
++ pwowlan_parm.gpio_index=3;
++ rtl8192c_FillH2CCmd(padapter, KEEP_ALIVE_CONTROL_CMD, 2, (u8 *)&pwowlan_parm);
++ printk("%s after KEEP_ALIVE_CONTROL_CMD register 0x81=%x \n",__FUNCTION__,rtw_read8(padapter, 0x81));
++
++ pwowlan_parm.mode =1;
++ pwowlan_parm.gpio_index=0;
++ pwowlan_parm.gpio_duration=0;
++ rtl8192c_FillH2CCmd(padapter, DISCONNECT_DECISION_CTRL_CMD, 3, (u8 *)&pwowlan_parm);
++ printk("%s after DISCONNECT_DECISION_CTRL_CMD register 0x81=%x \n",__FUNCTION__,rtw_read8(padapter, 0x81));
++
++ //enable GPIO wakeup
++ pwowlan_parm.mode =1;
++ pwowlan_parm.gpio_index=0;
++ pwowlan_parm.gpio_duration=0;
++ rtl8192c_FillH2CCmd(padapter, REMOTE_WAKE_CTRL_CMD, 3, (u8 *)&pwowlan_parm);
++ }
++ else
++ rtl8192c_FillH2CCmd(padapter, H2C_WO_WLAN_CMD, 3, (u8 *)&pwowlan_parm);
++
++
++_func_exit_;
++
++ return ;
++
++}
++
++#endif //CONFIG_WOWLAN
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/hal/rtl8192c/rtl8192c_dm.c linux-xbian-rpi/drivers/net/wireless/rtl8192cu/hal/rtl8192c/rtl8192c_dm.c
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/hal/rtl8192c/rtl8192c_dm.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/hal/rtl8192c/rtl8192c_dm.c 2015-07-28 01:20:58.309639981 +0200
+@@ -0,0 +1,5055 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++//============================================================
++// Description:
++//
++// This file is for 92CE/92CU dynamic mechanism only
++//
++//
++//============================================================
++
++//============================================================
++// include files
++//============================================================
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++#include <rtw_byteorder.h>
++
++#include <rtl8192c_hal.h>
++#include "../dm.h"
++#ifdef CONFIG_INTEL_PROXIM
++#include "../proxim/intel_proxim.h"
++#endif
++//============================================================
++// Global var
++//============================================================
++static u32 EDCAParam[maxAP][3] =
++{ // UL DL
++ {0x5ea322, 0x00a630, 0x00a44f}, //atheros AP
++ {0x5ea32b, 0x5ea42b, 0x5e4322}, //broadcom AP
++ {0x3ea430, 0x00a630, 0x3ea44f}, //cisco AP
++ {0x5ea44f, 0x00a44f, 0x5ea42b}, //marvell AP
++ {0x5ea422, 0x00a44f, 0x00a44f}, //ralink AP
++ //{0x5ea44f, 0x5ea44f, 0x5ea44f}, //realtek AP
++ {0xa44f, 0x5ea44f, 0x5e431c}, //realtek AP
++ {0x5ea42b, 0xa630, 0x5e431c}, //airgocap AP
++ {0x5ea42b, 0x5ea42b, 0x5ea42b}, //unknown AP
++// {0x5e4322, 0x00a44f, 0x5ea44f}, //unknown AP
++};
++
++
++/*-----------------------------------------------------------------------------
++ * Function: dm_DIGInit()
++ *
++ * Overview: Set DIG scheme init value.
++ *
++ * Input: NONE
++ *
++ * Output: NONE
++ *
++ * Return: NONE
++ *
++ * Revised History:
++ * When Who Remark
++ *
++ *---------------------------------------------------------------------------*/
++static void dm_DIGInit(
++ IN PADAPTER pAdapter
++)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
++ struct dm_priv *pdmpriv = &pHalData->dmpriv;
++ DIG_T *pDigTable = &pdmpriv->DM_DigTable;
++
++
++ pDigTable->Dig_Enable_Flag = _TRUE;
++ pDigTable->Dig_Ext_Port_Stage = DIG_EXT_PORT_STAGE_MAX;
++
++ pDigTable->CurIGValue = 0x20;
++ pDigTable->PreIGValue = 0x0;
++
++ pDigTable->CurSTAConnectState = pDigTable->PreSTAConnectState = DIG_STA_DISCONNECT;
++ pDigTable->CurMultiSTAConnectState = DIG_MultiSTA_DISCONNECT;
++
++ pDigTable->RssiLowThresh = DM_DIG_THRESH_LOW;
++ pDigTable->RssiHighThresh = DM_DIG_THRESH_HIGH;
++
++ pDigTable->FALowThresh = DM_FALSEALARM_THRESH_LOW;
++ pDigTable->FAHighThresh = DM_FALSEALARM_THRESH_HIGH;
++
++
++ pDigTable->rx_gain_range_max = DM_DIG_MAX;
++ pDigTable->rx_gain_range_min = DM_DIG_MIN;
++ pDigTable->rx_gain_range_min_nolink = 0;
++
++ pDigTable->BackoffVal = DM_DIG_BACKOFF_DEFAULT;
++ pDigTable->BackoffVal_range_max = DM_DIG_BACKOFF_MAX;
++ pDigTable->BackoffVal_range_min = DM_DIG_BACKOFF_MIN;
++
++ pDigTable->PreCCKPDState = CCK_PD_STAGE_MAX;
++ pDigTable->CurCCKPDState = CCK_PD_STAGE_LowRssi;
++
++ pDigTable->ForbiddenIGI = DM_DIG_MIN;
++ pDigTable->LargeFAHit = 0;
++ pDigTable->Recover_cnt = 0;
++ pdmpriv->DIG_Dynamic_MIN = 0x25; //for FUNAI_TV
++}
++
++
++static u8 dm_initial_gain_MinPWDB(
++ IN PADAPTER pAdapter
++ )
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
++ struct dm_priv *pdmpriv = &pHalData->dmpriv;
++ DIG_T *pDigTable = &pdmpriv->DM_DigTable;
++ int Rssi_val_min = 0;
++
++ if((pDigTable->CurMultiSTAConnectState == DIG_MultiSTA_CONNECT) &&
++ (pDigTable->CurSTAConnectState == DIG_STA_CONNECT) )
++ {
++ if(pdmpriv->EntryMinUndecoratedSmoothedPWDB != 0)
++#ifdef CONFIG_CONCURRENT_MODE
++ Rssi_val_min = (pdmpriv->UndecoratedSmoothedPWDB+pdmpriv->EntryMinUndecoratedSmoothedPWDB)/2;
++#else
++ Rssi_val_min = (pdmpriv->EntryMinUndecoratedSmoothedPWDB > pdmpriv->UndecoratedSmoothedPWDB)?
++ pdmpriv->UndecoratedSmoothedPWDB:pdmpriv->EntryMinUndecoratedSmoothedPWDB;
++#endif //CONFIG_CONCURRENT_MODE
++ else
++ Rssi_val_min = pdmpriv->UndecoratedSmoothedPWDB;
++ }
++ else if(pDigTable->CurSTAConnectState == DIG_STA_CONNECT ||
++ pDigTable->CurSTAConnectState == DIG_STA_BEFORE_CONNECT)
++ Rssi_val_min = pdmpriv->UndecoratedSmoothedPWDB;
++ else if(pDigTable->CurMultiSTAConnectState == DIG_MultiSTA_CONNECT)
++ Rssi_val_min = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
++
++ //printk("%s CurMultiSTAConnectState(0x%02x) UndecoratedSmoothedPWDB(%d),EntryMinUndecoratedSmoothedPWDB(%d)\n"
++ //,__FUNCTION__,pDigTable->CurSTAConnectState,
++ //pdmpriv->UndecoratedSmoothedPWDB,pdmpriv->EntryMinUndecoratedSmoothedPWDB);
++
++ return (u8)Rssi_val_min;
++}
++
++
++static VOID
++dm_FalseAlarmCounterStatistics(
++ IN PADAPTER Adapter
++ )
++{
++ u32 ret_value;
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ struct dm_priv *pdmpriv = &pHalData->dmpriv;
++ PFALSE_ALARM_STATISTICS FalseAlmCnt = &(pdmpriv->FalseAlmCnt);
++#ifdef CONFIG_CONCURRENT_MODE
++ PADAPTER pbuddy_adapter = Adapter->pbuddy_adapter;
++#endif //CONFIG_CONCURRENT_MODE
++
++ ret_value = PHY_QueryBBReg(Adapter, rOFDM_PHYCounter1, bMaskDWord);
++ FalseAlmCnt->Cnt_Parity_Fail = ((ret_value&0xffff0000)>>16);
++
++ ret_value = PHY_QueryBBReg(Adapter, rOFDM_PHYCounter2, bMaskDWord);
++ FalseAlmCnt->Cnt_Rate_Illegal = (ret_value&0xffff);
++ FalseAlmCnt->Cnt_Crc8_fail = ((ret_value&0xffff0000)>>16);
++ ret_value = PHY_QueryBBReg(Adapter, rOFDM_PHYCounter3, bMaskDWord);
++ FalseAlmCnt->Cnt_Mcs_fail = (ret_value&0xffff);
++ ret_value = PHY_QueryBBReg(Adapter, rOFDM0_FrameSync, bMaskDWord);
++ FalseAlmCnt->Cnt_Fast_Fsync = (ret_value&0xffff);
++ FalseAlmCnt->Cnt_SB_Search_fail = ((ret_value&0xffff0000)>>16);
++
++ FalseAlmCnt->Cnt_Ofdm_fail = FalseAlmCnt->Cnt_Parity_Fail + FalseAlmCnt->Cnt_Rate_Illegal +
++ FalseAlmCnt->Cnt_Crc8_fail + FalseAlmCnt->Cnt_Mcs_fail+
++ FalseAlmCnt->Cnt_Fast_Fsync + FalseAlmCnt->Cnt_SB_Search_fail;
++
++
++ //hold cck counter
++ PHY_SetBBReg(Adapter, rCCK0_FalseAlarmReport, BIT(14), 1);
++
++ ret_value = PHY_QueryBBReg(Adapter, rCCK0_FACounterLower, bMaskByte0);
++ FalseAlmCnt->Cnt_Cck_fail = ret_value;
++
++ ret_value = PHY_QueryBBReg(Adapter, rCCK0_FACounterUpper, bMaskByte3);
++ FalseAlmCnt->Cnt_Cck_fail += (ret_value& 0xff)<<8;
++
++ FalseAlmCnt->Cnt_all = ( FalseAlmCnt->Cnt_Parity_Fail +
++ FalseAlmCnt->Cnt_Rate_Illegal +
++ FalseAlmCnt->Cnt_Crc8_fail +
++ FalseAlmCnt->Cnt_Mcs_fail +
++ FalseAlmCnt->Cnt_Cck_fail);
++
++ Adapter->recvpriv.FalseAlmCnt_all = FalseAlmCnt->Cnt_all;
++#ifdef CONFIG_CONCURRENT_MODE
++ if(pbuddy_adapter)
++ pbuddy_adapter->recvpriv.FalseAlmCnt_all = FalseAlmCnt->Cnt_all;
++#endif //CONFIG_CONCURRENT_MODE
++
++ //reset false alarm counter registers
++ PHY_SetBBReg(Adapter, rOFDM1_LSTF, 0x08000000, 1);
++ PHY_SetBBReg(Adapter, rOFDM1_LSTF, 0x08000000, 0);
++ //reset cck counter
++ PHY_SetBBReg(Adapter, rCCK0_FalseAlarmReport, 0x0000c000, 0);
++ //enable cck counter
++ PHY_SetBBReg(Adapter, rCCK0_FalseAlarmReport, 0x0000c000, 2);
++
++ //RT_TRACE( COMP_DIG, DBG_LOUD, ("Cnt_Parity_Fail = %ld, Cnt_Rate_Illegal = %ld, Cnt_Crc8_fail = %ld, Cnt_Mcs_fail = %ld\n",
++ // FalseAlmCnt->Cnt_Parity_Fail, FalseAlmCnt->Cnt_Rate_Illegal, FalseAlmCnt->Cnt_Crc8_fail, FalseAlmCnt->Cnt_Mcs_fail) );
++ //RT_TRACE( COMP_DIG, DBG_LOUD, ("Cnt_Ofdm_fail = %ld, Cnt_Cck_fail = %ld, Cnt_all = %ld\n",
++ // FalseAlmCnt->Cnt_Ofdm_fail, FalseAlmCnt->Cnt_Cck_fail, FalseAlmCnt->Cnt_all) );
++ //RT_TRACE( COMP_DIG, DBG_LOUD, ("Cnt_Ofdm_fail = %ld, Cnt_Cck_fail = %ld, Cnt_all = %ld\n",
++ // FalseAlmCnt->Cnt_Ofdm_fail, FalseAlmCnt->Cnt_Cck_fail, FalseAlmCnt->Cnt_all) );
++}
++
++
++static VOID
++DM_Write_DIG(
++ IN PADAPTER pAdapter
++ )
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
++ struct dm_priv *pdmpriv = &pHalData->dmpriv;
++ DIG_T *pDigTable = &pdmpriv->DM_DigTable;
++
++#ifdef CONFIG_CONCURRENT_MODE
++ if(rtw_buddy_adapter_up(pAdapter))
++ {
++ PADAPTER pbuddy_adapter = pAdapter->pbuddy_adapter;
++ PHAL_DATA_TYPE pbuddy_HalData = GET_HAL_DATA(pbuddy_adapter);
++ struct dm_priv *pbuddy_dmpriv = &pbuddy_HalData->dmpriv;
++ DIG_T *pbuddy_DigTable = &pbuddy_dmpriv->DM_DigTable;
++
++ //sync IGValue
++ pbuddy_DigTable->PreIGValue = pDigTable->PreIGValue;
++ pbuddy_DigTable->CurIGValue = pDigTable->CurIGValue;
++ }
++#endif //CONFIG_CONCURRENT_MODE
++
++
++ //RT_TRACE( COMP_DIG, DBG_LOUD, ("CurIGValue = 0x%lx, PreIGValue = 0x%lx, BackoffVal = %d\n",
++ // DM_DigTable.CurIGValue, DM_DigTable.PreIGValue, DM_DigTable.BackoffVal));
++
++ if (pDigTable->Dig_Enable_Flag == _FALSE)
++ {
++ //RT_TRACE( COMP_DIG, DBG_LOUD, ("DIG is disabled\n"));
++ pDigTable->PreIGValue = 0x17;
++ return;
++ }
++
++ if( (pDigTable->PreIGValue != pDigTable->CurIGValue) || ( pAdapter->bForceWriteInitGain ) )
++ {
++ // Set initial gain.
++ //PHY_SetBBReg(pAdapter, rOFDM0_XAAGCCore1, bMaskByte0, pDigTable->CurIGValue);
++ //PHY_SetBBReg(pAdapter, rOFDM0_XBAGCCore1, bMaskByte0, pDigTable->CurIGValue);
++ //printk("%s DIG(0x%02x)\n",__FUNCTION__,pDigTable->CurIGValue);
++
++#if defined CONFIG_WIDI_DIG_3E && defined CONFIG_INTEL_WIDI
++ if( pAdapter->mlmepriv.widi_enable == _TRUE )
++ {
++ PHY_SetBBReg(pAdapter, rOFDM0_XAAGCCore1, 0x7f, 0x3e);
++ PHY_SetBBReg(pAdapter, rOFDM0_XBAGCCore1, 0x7f, 0x3e);
++ }
++ else
++#endif //defined CONFIG_WIDI_DIG_3E && defined CONFIG_INTEL_WIDI
++ {
++ PHY_SetBBReg(pAdapter, rOFDM0_XAAGCCore1, 0x7f, pDigTable->CurIGValue);
++ PHY_SetBBReg(pAdapter, rOFDM0_XBAGCCore1, 0x7f, pDigTable->CurIGValue);
++ }
++ pDigTable->PreIGValue = pDigTable->CurIGValue;
++ }
++}
++
++
++static VOID
++dm_CtrlInitGainByFA(
++ IN PADAPTER pAdapter
++)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
++ struct dm_priv *pdmpriv = &pHalData->dmpriv;
++ DIG_T *pDigTable = &pdmpriv->DM_DigTable;
++ PFALSE_ALARM_STATISTICS FalseAlmCnt = &(pdmpriv->FalseAlmCnt);
++
++ u8 value_IGI = pDigTable->CurIGValue;
++
++ if(FalseAlmCnt->Cnt_all < DM_DIG_FA_TH0)
++ value_IGI --;
++ else if(FalseAlmCnt->Cnt_all < DM_DIG_FA_TH1)
++ value_IGI += 0;
++ else if(FalseAlmCnt->Cnt_all < DM_DIG_FA_TH2)
++ value_IGI ++;
++ else if(FalseAlmCnt->Cnt_all >= DM_DIG_FA_TH2)
++ value_IGI +=2;
++
++ if(value_IGI > DM_DIG_FA_UPPER)
++ value_IGI = DM_DIG_FA_UPPER;
++ if(value_IGI < DM_DIG_FA_LOWER)
++ value_IGI = DM_DIG_FA_LOWER;
++
++ if(FalseAlmCnt->Cnt_all > 10000)
++ value_IGI = DM_DIG_FA_UPPER;
++
++ pDigTable->CurIGValue = value_IGI;
++
++ DM_Write_DIG(pAdapter);
++
++}
++
++#ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV
++VOID dm_CtrlInitGainByRssi( IN PADAPTER pAdapter)
++{
++
++ u32 isBT;
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
++ struct dm_priv *pdmpriv = &pHalData->dmpriv;
++ DIG_T *pDigTable = &pdmpriv->DM_DigTable;
++ PFALSE_ALARM_STATISTICS FalseAlmCnt = &(pdmpriv->FalseAlmCnt);
++#ifdef CONFIG_DM_ADAPTIVITY
++ u8 Adap_IGI_Upper = pdmpriv->IGI_target + 30 + (u8) pdmpriv->TH_L2H_ini -(u8) pdmpriv->TH_EDCCA_HL_diff;
++#endif
++
++ //modify DIG upper bound
++ if((pDigTable->Rssi_val_min + 20) > DM_DIG_MAX )
++ pDigTable->rx_gain_range_max = DM_DIG_MAX;
++ else
++ pDigTable->rx_gain_range_max = pDigTable->Rssi_val_min + 20;
++
++ //modify DIG lower bound
++ if((FalseAlmCnt->Cnt_all > 500)&&(pdmpriv->DIG_Dynamic_MIN < 0x25))
++ pdmpriv->DIG_Dynamic_MIN++;
++ if((FalseAlmCnt->Cnt_all < 500)&&(pdmpriv->DIG_Dynamic_MIN > DM_DIG_MIN))
++ pdmpriv->DIG_Dynamic_MIN--;
++ if((pDigTable->Rssi_val_min < 8) && (pdmpriv->DIG_Dynamic_MIN > DM_DIG_MIN))
++ pdmpriv->DIG_Dynamic_MIN--;
++
++ //modify DIG lower bound, deal with abnorally large false alarm
++ if(FalseAlmCnt->Cnt_all > 10000)
++ {
++ //RT_TRACE(COMP_DIG, DBG_LOUD, ("dm_DIG(): Abnornally false alarm case. \n"));
++ pDigTable->LargeFAHit++;
++ if(pDigTable->ForbiddenIGI < pDigTable->CurIGValue)
++ {
++ pDigTable->ForbiddenIGI = pDigTable->CurIGValue;
++ pDigTable->LargeFAHit = 1;
++ }
++ if(pDigTable->LargeFAHit >= 3)
++ {
++ if((pDigTable->ForbiddenIGI+1) >pDigTable->rx_gain_range_max)
++ pDigTable->rx_gain_range_min = pDigTable->rx_gain_range_max;
++ else
++ pDigTable->rx_gain_range_min = (pDigTable->ForbiddenIGI + 1);
++ pDigTable->Recover_cnt = 3600; //3600=2hr
++ }
++ }
++ else
++ {
++ //Recovery mechanism for IGI lower bound
++ if(pDigTable->Recover_cnt != 0){
++ pDigTable->Recover_cnt --;
++ }
++ else
++ {
++ if(pDigTable->LargeFAHit == 0 )
++ {
++ if((pDigTable->ForbiddenIGI -1) < pdmpriv->DIG_Dynamic_MIN) //DM_DIG_MIN)
++ {
++ pDigTable->ForbiddenIGI = pdmpriv->DIG_Dynamic_MIN; //DM_DIG_MIN;
++ pDigTable->rx_gain_range_min = pdmpriv->DIG_Dynamic_MIN; //DM_DIG_MIN;
++ }
++ else
++ {
++ pDigTable->ForbiddenIGI --;
++ pDigTable->rx_gain_range_min = (pDigTable->ForbiddenIGI + 1);
++ }
++ }
++ else if(pDigTable->LargeFAHit == 3 )
++ {
++ pDigTable->LargeFAHit = 0;
++ }
++ }
++ }
++ #ifdef CONFIG_USB_HCI
++ if(FalseAlmCnt->Cnt_all < 250)
++ {
++#endif
++ //DBG_8192C("===> dm_CtrlInitGainByRssi, Enter DIG by SS mode\n");
++
++ isBT = rtw_read8(pAdapter, 0x4fd) & 0x01;
++
++ if(!isBT){
++
++ if(FalseAlmCnt->Cnt_all > pDigTable->FAHighThresh)
++ {
++ if((pDigTable->BackoffVal -2) < pDigTable->BackoffVal_range_min)
++ pDigTable->BackoffVal = pDigTable->BackoffVal_range_min;
++ else
++ pDigTable->BackoffVal -= 2;
++ }
++ else if(FalseAlmCnt->Cnt_all < pDigTable->FALowThresh)
++ {
++ if((pDigTable->BackoffVal+2) > pDigTable->BackoffVal_range_max)
++ pDigTable->BackoffVal = pDigTable->BackoffVal_range_max;
++ else
++ pDigTable->BackoffVal +=2;
++ }
++ }
++ else
++ pDigTable->BackoffVal = DM_DIG_BACKOFF_DEFAULT;
++
++ pDigTable->CurIGValue = pDigTable->Rssi_val_min+10-pDigTable->BackoffVal;
++
++ //DBG_8192C("Rssi_val_min = %x BackoffVal %x\n",pDigTable->Rssi_val_min, pDigTable->BackoffVal);
++#ifdef CONFIG_USB_HCI
++ }
++ else
++ {
++ //DBG_8192C("===> dm_CtrlInitGainByRssi, Enter DIG by FA mode\n");
++ //DBG_8192C("RSSI = 0x%x", pDigTable->Rssi_val_min);
++
++ //Adjust initial gain by false alarm
++ if(FalseAlmCnt->Cnt_all > 1000)
++ pDigTable->CurIGValue = pDigTable ->PreIGValue+2;
++ else if (FalseAlmCnt->Cnt_all > 750)
++ pDigTable->CurIGValue = pDigTable->PreIGValue+1;
++ else if(FalseAlmCnt->Cnt_all < 500)
++ pDigTable->CurIGValue = pDigTable->PreIGValue-1;
++ }
++#endif
++
++ //Check initial gain by upper/lower bound
++ if(pDigTable->CurIGValue >pDigTable->rx_gain_range_max)
++ pDigTable->CurIGValue = pDigTable->rx_gain_range_max;
++
++ if(pDigTable->CurIGValue < pDigTable->rx_gain_range_min)
++ pDigTable->CurIGValue = pDigTable->rx_gain_range_min;
++
++#ifdef CONFIG_DM_ADAPTIVITY
++ if(pdmpriv->DMFlag & DYNAMIC_FUNC_ADAPTIVITY)
++ {
++ if(pDigTable->CurIGValue > Adap_IGI_Upper)
++ pDigTable->CurIGValue = Adap_IGI_Upper;
++
++ if(pdmpriv->IGI_LowerBound != 0)
++ {
++ if(pDigTable->CurIGValue < pdmpriv->IGI_LowerBound)
++ pDigTable->CurIGValue = pdmpriv->IGI_LowerBound;
++ }
++ LOG_LEVEL(_drv_info_, FUNC_ADPT_FMT": pdmpriv->IGI_LowerBound = %d\n",
++ FUNC_ADPT_ARG(pAdapter), pdmpriv->IGI_LowerBound);
++ }
++#endif /* CONFIG_DM_ADAPTIVITY */
++
++ //printk("%s => rx_gain_range_max(0x%02x) rx_gain_range_min(0x%02x)\n",__FUNCTION__,
++ // pDigTable->rx_gain_range_max,pDigTable->rx_gain_range_min);
++ //printk("%s CurIGValue(0x%02x) <====\n",__FUNCTION__,pDigTable->CurIGValue );
++
++ DM_Write_DIG(pAdapter);
++
++}
++#else
++static VOID dm_CtrlInitGainByRssi(IN PADAPTER pAdapter)
++{
++ u32 isBT;
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
++ struct dm_priv *pdmpriv = &pHalData->dmpriv;
++ DIG_T *pDigTable = &pdmpriv->DM_DigTable;
++ PFALSE_ALARM_STATISTICS FalseAlmCnt = &(pdmpriv->FalseAlmCnt);
++ u8 RSSI_tmp = dm_initial_gain_MinPWDB(pAdapter);
++#ifdef CONFIG_DM_ADAPTIVITY
++ u8 Adap_IGI_Upper = pdmpriv->IGI_target + 30 + (u8) pdmpriv->TH_L2H_ini -(u8) pdmpriv->TH_EDCCA_HL_diff;
++#endif
++
++ //modify DIG upper bound
++ if((pDigTable->Rssi_val_min + 20) > DM_DIG_MAX )
++ pDigTable->rx_gain_range_max = DM_DIG_MAX;
++ else
++ pDigTable->rx_gain_range_max = pDigTable->Rssi_val_min + 20;
++ //printk("%s Rssi_val_min(0x%02x),rx_gain_range_max(0x%02x)\n",__FUNCTION__,pDigTable->Rssi_val_min,pDigTable->rx_gain_range_max);
++ //modify DIG lower bound, deal with abnorally large false alarm
++ if(FalseAlmCnt->Cnt_all > 10000)
++ {
++ //RT_TRACE(COMP_DIG, DBG_LOUD, ("dm_DIG(): Abnornally false alarm case. \n"));
++
++ pDigTable->LargeFAHit++;
++ if(pDigTable->ForbiddenIGI < pDigTable->CurIGValue)
++ {
++ pDigTable->ForbiddenIGI = pDigTable->CurIGValue;
++ pDigTable->LargeFAHit = 1;
++ }
++
++ if(pDigTable->LargeFAHit >= 3)
++ {
++ if((pDigTable->ForbiddenIGI+1) > pDigTable->rx_gain_range_max)
++ pDigTable->rx_gain_range_min = pDigTable->rx_gain_range_max;
++ else
++ pDigTable->rx_gain_range_min = (pDigTable->ForbiddenIGI + 1);
++ pDigTable->Recover_cnt = 3600; //3600=2hr
++ }
++ }
++ else
++ {
++ //Recovery mechanism for IGI lower bound
++ if(pDigTable->Recover_cnt != 0)
++ pDigTable->Recover_cnt --;
++ else
++ {
++ if(pDigTable->LargeFAHit == 0 )
++ {
++ if((pDigTable->ForbiddenIGI -1) < DM_DIG_MIN)
++ {
++ pDigTable->ForbiddenIGI = DM_DIG_MIN;
++ pDigTable->rx_gain_range_min = DM_DIG_MIN;
++ }
++ else
++ {
++ pDigTable->ForbiddenIGI --;
++ pDigTable->rx_gain_range_min = (pDigTable->ForbiddenIGI + 1);
++ }
++ }
++ else if(pDigTable->LargeFAHit == 3 )
++ {
++ pDigTable->LargeFAHit = 0;
++ }
++ }
++ }
++
++ //RT_TRACE(COMP_DIG, DBG_LOUD, ("DM_DigTable.ForbiddenIGI = 0x%x, DM_DigTable.LargeFAHit = 0x%x\n",pDigTable->ForbiddenIGI, pDigTable->LargeFAHit));
++ //RT_TRACE(COMP_DIG, DBG_LOUD, ("DM_DigTable.rx_gain_range_max = 0x%x, DM_DigTable.rx_gain_range_min = 0x%x\n",pDigTable->rx_gain_range_max, pDigTable->rx_gain_range_min));
++
++#ifdef CONFIG_USB_HCI
++ if(FalseAlmCnt->Cnt_all < 250)
++ {
++#endif
++ //DBG_8192C("===> dm_CtrlInitGainByRssi, Enter DIG by SS mode\n");
++
++ isBT = rtw_read8(pAdapter, 0x4fd) & 0x01;
++
++ if(!isBT){
++
++ if(FalseAlmCnt->Cnt_all > pDigTable->FAHighThresh)
++ {
++ if((pDigTable->BackoffVal -2) < pDigTable->BackoffVal_range_min)
++ pDigTable->BackoffVal = pDigTable->BackoffVal_range_min;
++ else
++ pDigTable->BackoffVal -= 2;
++ }
++ else if(FalseAlmCnt->Cnt_all < pDigTable->FALowThresh)
++ {
++ if((pDigTable->BackoffVal+2) > pDigTable->BackoffVal_range_max)
++ pDigTable->BackoffVal = pDigTable->BackoffVal_range_max;
++ else
++ pDigTable->BackoffVal +=2;
++ }
++ }
++ else
++ pDigTable->BackoffVal = DM_DIG_BACKOFF_DEFAULT;
++
++ pDigTable->CurIGValue = pDigTable->Rssi_val_min+10-pDigTable->BackoffVal;
++
++ //DBG_8192C("Rssi_val_min = %x BackoffVal %x\n",pDigTable->Rssi_val_min, pDigTable->BackoffVal);
++#ifdef CONFIG_USB_HCI
++ }
++ else
++ {
++ //DBG_8192C("===> dm_CtrlInitGainByRssi, Enter DIG by FA mode\n");
++ //DBG_8192C("RSSI = 0x%x", pDigTable->Rssi_val_min);
++
++ //Adjust initial gain by false alarm
++ if(FalseAlmCnt->Cnt_all > 1000)
++ pDigTable->CurIGValue = pDigTable ->PreIGValue+2;
++ else if (FalseAlmCnt->Cnt_all > 750)
++ pDigTable->CurIGValue = pDigTable->PreIGValue+1;
++ else if(FalseAlmCnt->Cnt_all < 500)
++ pDigTable->CurIGValue = pDigTable->PreIGValue-1;
++ }
++#endif
++
++ if(RSSI_tmp <= DM_DIG_MIN)
++ pDigTable->rx_gain_range_min = DM_DIG_MIN;
++ else if(RSSI_tmp >= DM_DIG_MAX)
++ pDigTable->rx_gain_range_min = DM_DIG_MAX;
++ else
++ pDigTable->rx_gain_range_min = RSSI_tmp;
++
++
++ //Check initial gain by upper/lower bound
++ if(pDigTable->CurIGValue >pDigTable->rx_gain_range_max)
++ pDigTable->CurIGValue = pDigTable->rx_gain_range_max;
++
++ if(pDigTable->CurIGValue < pDigTable->rx_gain_range_min)
++ pDigTable->CurIGValue = pDigTable->rx_gain_range_min;
++
++#ifdef CONFIG_DM_ADAPTIVITY
++ if(pdmpriv->DMFlag & DYNAMIC_FUNC_ADAPTIVITY)
++ {
++ if(pDigTable->CurIGValue > Adap_IGI_Upper)
++ pDigTable->CurIGValue = Adap_IGI_Upper;
++
++ if(pdmpriv->IGI_LowerBound != 0)
++ {
++ if(pDigTable->CurIGValue < pdmpriv->IGI_LowerBound)
++ pDigTable->CurIGValue = pdmpriv->IGI_LowerBound;
++ }
++ LOG_LEVEL(_drv_info_, FUNC_ADPT_FMT": pdmpriv->IGI_LowerBound = %d\n",
++ FUNC_ADPT_ARG(pAdapter), pdmpriv->IGI_LowerBound);
++ }
++#endif /* CONFIG_DM_ADAPTIVITY */
++
++ //printk("%s => rx_gain_range_max(0x%02x) rx_gain_range_min(0x%02x)\n",__FUNCTION__,
++ // pDigTable->rx_gain_range_max,pDigTable->rx_gain_range_min);
++ //printk("%s CurIGValue(0x%02x) <====\n",__FUNCTION__,pDigTable->CurIGValue );
++
++ DM_Write_DIG(pAdapter);
++
++}
++#endif
++
++static VOID
++dm_initial_gain_Multi_STA(
++ IN PADAPTER pAdapter)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
++ struct dm_priv *pdmpriv = &pHalData->dmpriv;
++ struct mlme_priv *pmlmepriv = &(pAdapter->mlmepriv);
++ DIG_T *pDigTable = &pdmpriv->DM_DigTable;
++ int rssi_strength = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
++ BOOLEAN bMulti_STA = _FALSE;
++
++#ifdef CONFIG_CONCURRENT_MODE
++ //AP Mode
++ if(check_buddy_fwstate(pAdapter, WIFI_AP_STATE) == _TRUE && (rssi_strength !=0))
++ {
++ bMulti_STA = _TRUE;
++ }
++ else if(pDigTable->CurMultiSTAConnectState == DIG_MultiSTA_CONNECT && rssi_strength==0) //STA+STA MODE
++ {
++ bMulti_STA = _TRUE;
++ rssi_strength = pdmpriv->UndecoratedSmoothedPWDB;
++ }
++#endif //CONFIG_CONCURRENT_MODE
++
++
++ //ADHOC and AP Mode
++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE|WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE) == _TRUE)
++ {
++ bMulti_STA = _TRUE;
++ }
++
++
++ if((bMulti_STA == _FALSE)
++ || (pDigTable->CurSTAConnectState == DIG_STA_DISCONNECT))
++ {
++ pdmpriv->binitialized = _FALSE;
++ pDigTable->Dig_Ext_Port_Stage = DIG_EXT_PORT_STAGE_MAX;
++ return;
++ }
++ else if(pdmpriv->binitialized == _FALSE)
++ {
++ pdmpriv->binitialized = _TRUE;
++ pDigTable->Dig_Ext_Port_Stage = DIG_EXT_PORT_STAGE_0;
++ pDigTable->CurIGValue = 0x20;
++ DM_Write_DIG(pAdapter);
++ }
++
++ // Initial gain control by ap mode
++ if(pDigTable->CurMultiSTAConnectState == DIG_MultiSTA_CONNECT)
++ {
++ if ( (rssi_strength < pDigTable->RssiLowThresh) &&
++ (pDigTable->Dig_Ext_Port_Stage != DIG_EXT_PORT_STAGE_1))
++ {
++ // Set to dig value to 0x20 for Luke's opinion after disable dig
++ if(pDigTable->Dig_Ext_Port_Stage == DIG_EXT_PORT_STAGE_2)
++ {
++ pDigTable->CurIGValue = 0x20;
++ DM_Write_DIG(pAdapter);
++ }
++ pDigTable->Dig_Ext_Port_Stage = DIG_EXT_PORT_STAGE_1;
++ }
++ else if (rssi_strength > pDigTable->RssiHighThresh)
++ {
++ pDigTable->Dig_Ext_Port_Stage = DIG_EXT_PORT_STAGE_2;
++ dm_CtrlInitGainByFA(pAdapter);
++ }
++ }
++ else if(pDigTable->Dig_Ext_Port_Stage != DIG_EXT_PORT_STAGE_0)
++ {
++ pDigTable->Dig_Ext_Port_Stage = DIG_EXT_PORT_STAGE_0;
++ pDigTable->CurIGValue = 0x20;
++ DM_Write_DIG(pAdapter);
++ }
++
++ //RT_TRACE( COMP_DIG, DBG_LOUD, ("CurMultiSTAConnectState = %x Dig_Ext_Port_Stage %x\n",
++ // DM_DigTable.CurMultiSTAConnectState, DM_DigTable.Dig_Ext_Port_Stage));
++}
++
++static VOID
++dm_initial_gain_STA_beforelinked(
++ IN PADAPTER pAdapter)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
++ struct dm_priv *pdmpriv = &pHalData->dmpriv;
++ DIG_T *pDigTable = &pdmpriv->DM_DigTable;
++ PFALSE_ALARM_STATISTICS pFalseAlmCnt = &(pdmpriv->FalseAlmCnt);
++
++ //CurrentIGI = pDM_DigTable->rx_gain_range_min;//pDM_DigTable->CurIGValue = pDM_DigTable->rx_gain_range_min
++ //ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DIG BeforeLink\n"));
++ //2012.03.30 LukeLee: enable DIG before link but with very high thresholds
++ // Updated by Albert 2012/09/27
++ // Copy the same rule from 8192du code.
++ if( pFalseAlmCnt->Cnt_all > 2000 )
++ pDigTable->CurIGValue += 2;
++ else if ( ( pFalseAlmCnt->Cnt_all > 1000 ) && ( pFalseAlmCnt->Cnt_all <= 1000 ) )
++ pDigTable->CurIGValue += 1;
++ else if(pFalseAlmCnt->Cnt_all < 500)
++ pDigTable->CurIGValue -= 1;
++
++ //Check initial gain by upper/lower bound
++ if(pDigTable->CurIGValue >pDigTable->rx_gain_range_max)
++ pDigTable->CurIGValue = pDigTable->rx_gain_range_max;
++
++ if(pDigTable->CurIGValue < pDigTable->rx_gain_range_min)
++ pDigTable->CurIGValue = pDigTable->rx_gain_range_min;
++
++ printk("%s ==> FalseAlmCnt->Cnt_all:%d CurIGValue:0x%02x \n",__FUNCTION__,pFalseAlmCnt->Cnt_all ,pDigTable->CurIGValue);
++}
++
++static VOID
++dm_initial_gain_STA(
++ IN PADAPTER pAdapter)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
++ struct dm_priv *pdmpriv = &pHalData->dmpriv;
++ DIG_T *pDigTable = &pdmpriv->DM_DigTable;
++
++ //RT_TRACE( COMP_DIG, DBG_LOUD, ("PreSTAConnectState = %x, CurSTAConnectState = %x\n",
++ // DM_DigTable.PreSTAConnectState, DM_DigTable.CurSTAConnectState));
++
++
++ if(pDigTable->PreSTAConnectState == pDigTable->CurSTAConnectState||
++ pDigTable->CurSTAConnectState == DIG_STA_BEFORE_CONNECT ||
++ pDigTable->CurSTAConnectState == DIG_STA_CONNECT)
++ {
++ // beforeconnect -> beforeconnect or connect -> connect
++ // (dis)connect -> beforeconnect
++ // disconnect -> connecct or beforeconnect -> connect
++ if(pDigTable->CurSTAConnectState != DIG_STA_DISCONNECT)
++ {
++ pDigTable->Rssi_val_min = dm_initial_gain_MinPWDB(pAdapter);
++ dm_CtrlInitGainByRssi(pAdapter);
++ }
++#if 0
++ else if((wdev_to_priv(pAdapter->rtw_wdev))->p2p_enabled == _TRUE
++ && pAdapter->wdinfo.driver_interface == DRIVER_CFG80211)
++ {
++ //pDigTable->CurIGValue = 0x30;
++ DM_Write_DIG(pAdapter);
++ }
++#endif
++ else{ // pDigTable->CurSTAConnectState == DIG_STA_DISCONNECT
++ #ifdef CONFIG_BEFORE_LINKED_DIG
++ //printk("%s==> ##1 CurIGI(0x%02x),PreIGValue(0x%02x) \n",__FUNCTION__,pDigTable->CurIGValue,pDigTable->PreIGValue );
++ dm_initial_gain_STA_beforelinked(pAdapter);
++ DM_Write_DIG(pAdapter);
++ #endif //CONFIG_BEFORE_LINKED_DIG
++ }
++ }
++ else
++ {
++ // connect -> disconnect or beforeconnect -> disconnect
++ pDigTable->Rssi_val_min = 0;
++ pDigTable->Dig_Ext_Port_Stage = DIG_EXT_PORT_STAGE_MAX;
++ pDigTable->BackoffVal = DM_DIG_BACKOFF_DEFAULT;
++ pDigTable->CurIGValue = 0x20;
++ pDigTable->PreIGValue = 0;
++ #ifdef CONFIG_BEFORE_LINKED_DIG
++ //printk("%s==> ##2 CurIGI(0x%02x),PreIGValue(0x%02x) \n",__FUNCTION__,pDigTable->CurIGValue,pDigTable->PreIGValue );
++ dm_initial_gain_STA_beforelinked(pAdapter);
++ #endif //CONFIG_BEFORE_LINKED_DIG
++
++
++ DM_Write_DIG(pAdapter);
++ }
++
++}
++
++
++static void dm_CCK_PacketDetectionThresh(
++ IN PADAPTER pAdapter)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
++ struct dm_priv *pdmpriv = &pHalData->dmpriv;
++ PFALSE_ALARM_STATISTICS FalseAlmCnt = &(pdmpriv->FalseAlmCnt);
++ DIG_T *pDigTable = &pdmpriv->DM_DigTable;
++
++ if(pDigTable->CurSTAConnectState == DIG_STA_CONNECT)
++ {
++ pDigTable->Rssi_val_min = dm_initial_gain_MinPWDB(pAdapter);
++ if(pDigTable->PreCCKPDState == CCK_PD_STAGE_LowRssi)
++ {
++ if(pDigTable->Rssi_val_min <= 25)
++ pDigTable->CurCCKPDState = CCK_PD_STAGE_LowRssi;
++ else
++ pDigTable->CurCCKPDState = CCK_PD_STAGE_HighRssi;
++ }
++ else{
++ if(pDigTable->Rssi_val_min <= 20)
++ pDigTable->CurCCKPDState = CCK_PD_STAGE_LowRssi;
++ else
++ pDigTable->CurCCKPDState = CCK_PD_STAGE_HighRssi;
++ }
++ }
++ else
++ pDigTable->CurCCKPDState=CCK_PD_STAGE_MAX;
++
++ if(pDigTable->PreCCKPDState != pDigTable->CurCCKPDState)
++ {
++ if((pDigTable->CurCCKPDState == CCK_PD_STAGE_LowRssi)||
++ (pDigTable->CurCCKPDState == CCK_PD_STAGE_MAX))
++ {
++ PHY_SetBBReg(pAdapter, rCCK0_CCA, bMaskByte2, 0x83);
++
++ //PHY_SetBBReg(pAdapter, rCCK0_System, bMaskByte1, 0x40);
++ //if(IS_92C_SERIAL(pHalData->VersionID))
++ //PHY_SetBBReg(pAdapter, rCCK0_FalseAlarmReport , bMaskByte2, 0xd7);
++ }
++ else
++ {
++ PHY_SetBBReg(pAdapter, rCCK0_CCA, bMaskByte2, 0xcd);
++ //PHY_SetBBReg(pAdapter,rCCK0_System, bMaskByte1, 0x47);
++ //if(IS_92C_SERIAL(pHalData->VersionID))
++ //PHY_SetBBReg(pAdapter, rCCK0_FalseAlarmReport , bMaskByte2, 0xd3);
++ }
++
++ pDigTable->PreCCKPDState = pDigTable->CurCCKPDState;
++ }
++
++ //RT_TRACE( COMP_DIG, DBG_LOUD, ("CCKPDStage=%x\n",pDigTable->CurCCKPDState));
++ //RT_TRACE( COMP_DIG, DBG_LOUD, ("is92C=%x\n",IS_92C_SERIAL(pHalData->VersionID)));
++
++}
++
++
++static void
++dm_CtrlInitGainByTwoPort(
++ IN PADAPTER pAdapter)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
++ struct dm_priv *pdmpriv = &pHalData->dmpriv;
++ struct mlme_priv *pmlmepriv = &(pAdapter->mlmepriv);
++ DIG_T *pDigTable = &pdmpriv->DM_DigTable;
++
++ if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE)
++ {
++#ifdef CONFIG_IOCTL_CFG80211
++ if((wdev_to_priv(pAdapter->rtw_wdev))->p2p_enabled == _TRUE)
++ {
++ }
++ else
++#endif
++ return;
++ }
++
++ // Decide the current status and if modify initial gain or not
++ if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == _TRUE)
++ {
++ pDigTable->CurSTAConnectState = DIG_STA_BEFORE_CONNECT;
++ }
++ else if(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)
++ {
++ pDigTable->CurSTAConnectState = DIG_STA_CONNECT;
++ }
++ else
++ {
++ pDigTable->CurSTAConnectState = DIG_STA_DISCONNECT;
++ }
++
++
++ pDigTable->CurMultiSTAConnectState = DIG_MultiSTA_DISCONNECT;
++ if(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE) == _TRUE)
++ {
++ if((is_IBSS_empty(pAdapter)==_FAIL) && (pAdapter->stapriv.asoc_sta_count > 2))
++ pDigTable->CurMultiSTAConnectState = DIG_MultiSTA_CONNECT;
++ }
++
++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE)
++ {
++ if(pAdapter->stapriv.asoc_sta_count > 2)
++ pDigTable->CurMultiSTAConnectState = DIG_MultiSTA_CONNECT;
++ }
++
++#ifdef CONFIG_CONCURRENT_MODE
++ if(check_buddy_fwstate(pAdapter, WIFI_AP_STATE) == _TRUE)
++ {
++ PADAPTER pbuddy_adapter = pAdapter->pbuddy_adapter;
++
++ if(pbuddy_adapter->stapriv.asoc_sta_count > 2)
++ {
++ pDigTable->CurSTAConnectState = DIG_STA_CONNECT;
++ pDigTable->CurMultiSTAConnectState = DIG_MultiSTA_CONNECT;
++ }
++ }
++ else if(check_buddy_fwstate(pAdapter, WIFI_STATION_STATE) == _TRUE &&
++ check_buddy_fwstate(pAdapter, _FW_LINKED) == _TRUE)
++ {
++ pDigTable->CurSTAConnectState = DIG_STA_CONNECT;
++
++ }
++#endif //CONFIG_CONCURRENT_MODE
++
++
++ dm_initial_gain_STA(pAdapter);
++ dm_initial_gain_Multi_STA(pAdapter);
++ //Baron temp DIG solution for DMP
++ //dm_CtrlInitGainByFA(pAdapter);
++
++ dm_CCK_PacketDetectionThresh(pAdapter);
++
++ pDigTable->PreSTAConnectState = pDigTable->CurSTAConnectState;
++
++}
++
++
++static void dm_DIG(
++ IN PADAPTER pAdapter)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
++ struct dm_priv *pdmpriv = &pHalData->dmpriv;
++ DIG_T *pDigTable = &pdmpriv->DM_DigTable;
++
++ //Read 0x0c50; Initial gain
++ pDigTable->PreIGValue = (u8)PHY_QueryBBReg(pAdapter, rOFDM0_XAAGCCore1, bMaskByte0);
++
++ //RTPRINT(FDM, DM_Monitor, ("dm_DIG() ==>\n"));
++
++ if(pdmpriv->bDMInitialGainEnable == _FALSE)
++ return;
++
++ //if(pDigTable->Dig_Enable_Flag == _FALSE)
++ // return;
++
++ if(!(pdmpriv->DMFlag & DYNAMIC_FUNC_DIG))
++ return;
++
++ //RTPRINT(FDM, DM_Monitor, ("dm_DIG() progress \n"));
++
++ dm_CtrlInitGainByTwoPort(pAdapter);
++
++ //RTPRINT(FDM, DM_Monitor, ("dm_DIG() <==\n"));
++}
++
++static void dm_SavePowerIndex(IN PADAPTER Adapter)
++{
++ u8 index;
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ struct dm_priv *pdmpriv = &pHalData->dmpriv;
++ u32 Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
++
++ for(index = 0; index< 6; index++)
++ pdmpriv->PowerIndex_backup[index] = rtw_read8(Adapter, Power_Index_REG[index]);
++}
++
++static void dm_RestorePowerIndex(IN PADAPTER Adapter)
++{
++ u8 index;
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ struct dm_priv *pdmpriv = &pHalData->dmpriv;
++ u32 Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
++
++ for(index = 0; index< 6; index++)
++ rtw_write8(Adapter, Power_Index_REG[index], pdmpriv->PowerIndex_backup[index]);
++}
++
++static void dm_WritePowerIndex(
++ IN PADAPTER Adapter,
++ IN u8 Value)
++{
++ u8 index;
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ u32 Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
++
++ for(index = 0; index< 6; index++)
++ rtw_write8(Adapter, Power_Index_REG[index], Value);
++}
++
++static void dm_InitDynamicTxPower(IN PADAPTER Adapter)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ struct dm_priv *pdmpriv = &pHalData->dmpriv;
++
++#ifdef CONFIG_USB_HCI
++#ifdef CONFIG_INTEL_PROXIM
++ if((pHalData->BoardType == BOARD_USB_High_PA)||(Adapter->proximity.proxim_support==_TRUE))
++#else
++ if(pHalData->BoardType == BOARD_USB_High_PA)
++#endif
++ {
++ dm_SavePowerIndex(Adapter);
++ pdmpriv->bDynamicTxPowerEnable = _TRUE;
++ }
++ else
++#else
++ pdmpriv->bDynamicTxPowerEnable = _FALSE;
++#endif
++
++ pdmpriv->LastDTPLvl = TxHighPwrLevel_Normal;
++ pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
++}
++
++
++static void dm_DynamicTxPower(IN PADAPTER Adapter)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ struct dm_priv *pdmpriv = &pHalData->dmpriv;
++ struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv);
++ struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
++ int UndecoratedSmoothedPWDB;
++
++ if(!pdmpriv->bDynamicTxPowerEnable)
++ return;
++
++ // If dynamic high power is disabled.
++ if(!(pdmpriv->DMFlag & DYNAMIC_FUNC_HP) )
++ {
++ pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
++ return;
++ }
++
++ // STA not connected and AP not connected
++ if((check_fwstate(pmlmepriv, _FW_LINKED) != _TRUE) &&
++ (pdmpriv->EntryMinUndecoratedSmoothedPWDB == 0))
++ {
++ //RT_TRACE(COMP_HIPWR, DBG_LOUD, ("Not connected to any \n"));
++ pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
++
++ //the LastDTPlvl should reset when disconnect,
++ //otherwise the tx power level wouldn't change when disconnect and connect again.
++ // Maddest 20091220.
++ pdmpriv->LastDTPLvl=TxHighPwrLevel_Normal;
++ return;
++ }
++#ifdef CONFIG_INTEL_PROXIM
++ if(Adapter->proximity.proxim_on== _TRUE){
++ struct proximity_priv *prox_priv=Adapter->proximity.proximity_priv;
++ // Intel set fixed tx power
++ printk("\n %s Adapter->proximity.proxim_on=%d prox_priv->proxim_modeinfo->power_output=%d \n",__FUNCTION__,Adapter->proximity.proxim_on,prox_priv->proxim_modeinfo->power_output);
++ if(prox_priv!=NULL){
++ if(prox_priv->proxim_modeinfo->power_output> 0)
++
++ {
++ switch(prox_priv->proxim_modeinfo->power_output){
++ case 1:
++ pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_100;
++ printk("TxHighPwrLevel_100\n");
++ break;
++ case 2:
++ pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_70;
++ printk("TxHighPwrLevel_70\n");
++ break;
++ case 3:
++ pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_50;
++ printk("TxHighPwrLevel_50\n");
++ break;
++ case 4:
++ pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_35;
++ printk("TxHighPwrLevel_35\n");
++ break;
++ case 5:
++ pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_15;
++ printk("TxHighPwrLevel_15\n");
++ break;
++ default:
++ pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_100;
++ printk("TxHighPwrLevel_100\n");
++ break;
++ }
++ }
++ }
++ }
++ else
++#endif
++{
++ if(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) // Default port
++ {
++ //todo: AP Mode
++ if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) ||
++ (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE))
++ {
++ UndecoratedSmoothedPWDB = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
++ //RT_TRACE(COMP_HIPWR, DBG_LOUD, ("AP Client PWDB = 0x%x \n", UndecoratedSmoothedPWDB));
++ }
++ else
++ {
++ UndecoratedSmoothedPWDB = pdmpriv->UndecoratedSmoothedPWDB;
++ //RT_TRACE(COMP_HIPWR, DBG_LOUD, ("STA Default Port PWDB = 0x%x \n", UndecoratedSmoothedPWDB));
++ }
++ }
++ else // associated entry pwdb
++ {
++ UndecoratedSmoothedPWDB = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
++ //RT_TRACE(COMP_HIPWR, DBG_LOUD, ("AP Ext Port PWDB = 0x%x \n", UndecoratedSmoothedPWDB));
++ }
++
++ if(UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL2)
++ {
++ pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Level2;
++ //RT_TRACE(COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x0)\n"));
++ }
++ else if((UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL2-3)) &&
++ (UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL1) )
++ {
++ pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Level1;
++ //RT_TRACE(COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x10)\n"));
++ }
++ else if(UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL1-5))
++ {
++ pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
++ //RT_TRACE(COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Normal\n"));
++ }
++}
++ if( (pdmpriv->DynamicTxHighPowerLvl != pdmpriv->LastDTPLvl) )
++ {
++ PHY_SetTxPowerLevel8192C(Adapter, pHalData->CurrentChannel);
++ if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Normal) // HP1 -> Normal or HP2 -> Normal
++ dm_RestorePowerIndex(Adapter);
++ else if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1)
++ dm_WritePowerIndex(Adapter, 0x14);
++ else if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2)
++ dm_WritePowerIndex(Adapter, 0x10);
++ }
++ pdmpriv->LastDTPLvl = pdmpriv->DynamicTxHighPowerLvl;
++
++}
++
++
++static VOID
++DM_ChangeDynamicInitGainThresh(
++ IN PADAPTER pAdapter,
++ IN u32 DM_Type,
++ IN u32 DM_Value)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
++ struct dm_priv *pdmpriv = &pHalData->dmpriv;
++ DIG_T *pDigTable = &pdmpriv->DM_DigTable;
++
++ if (DM_Type == DIG_TYPE_THRESH_HIGH)
++ {
++ pDigTable->RssiHighThresh = DM_Value;
++ }
++ else if (DM_Type == DIG_TYPE_THRESH_LOW)
++ {
++ pDigTable->RssiLowThresh = DM_Value;
++ }
++ else if (DM_Type == DIG_TYPE_ENABLE)
++ {
++ pDigTable->Dig_Enable_Flag = _TRUE;
++ }
++ else if (DM_Type == DIG_TYPE_DISABLE)
++ {
++ pDigTable->Dig_Enable_Flag = _FALSE;
++ }
++ else if (DM_Type == DIG_TYPE_BACKOFF)
++ {
++ if(DM_Value > 30)
++ DM_Value = 30;
++ pDigTable->BackoffVal = (u8)DM_Value;
++ }
++ else if(DM_Type == DIG_TYPE_RX_GAIN_MIN)
++ {
++ if(DM_Value == 0)
++ DM_Value = 0x1;
++ pDigTable->rx_gain_range_min = (u8)DM_Value;
++ }
++ else if(DM_Type == DIG_TYPE_RX_GAIN_MAX)
++ {
++ if(DM_Value > 0x50)
++ DM_Value = 0x50;
++ pDigTable->rx_gain_range_max = (u8)DM_Value;
++ }
++} /* DM_ChangeDynamicInitGainThresh */
++
++
++static VOID PWDB_Monitor(
++ IN PADAPTER Adapter
++ )
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ struct dm_priv *pdmpriv = &pHalData->dmpriv;
++ int i;
++ int tmpEntryMaxPWDB=0, tmpEntryMinPWDB=0xff;
++ u8 sta_cnt=0;
++ u32 PWDB_rssi[NUM_STA]={0};//[0~15]:MACID, [16~31]:PWDB_rssi
++
++ if(check_fwstate(&Adapter->mlmepriv, _FW_LINKED) != _TRUE)
++ return;
++
++
++ if(check_fwstate(&Adapter->mlmepriv, WIFI_AP_STATE|WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE) == _TRUE)
++ {
++ _irqL irqL;
++ _list *plist, *phead;
++ struct sta_info *psta;
++ struct sta_priv *pstapriv = &Adapter->stapriv;
++ u8 bcast_addr[ETH_ALEN]= {0xff,0xff,0xff,0xff,0xff,0xff};
++
++ _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
++
++ for(i=0; i< NUM_STA; i++)
++ {
++ phead = &(pstapriv->sta_hash[i]);
++ plist = get_next(phead);
++
++ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE)
++ {
++ psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
++
++ plist = get_next(plist);
++
++ if(_rtw_memcmp(psta ->hwaddr, bcast_addr, ETH_ALEN) ||
++ _rtw_memcmp(psta->hwaddr, myid(&Adapter->eeprompriv), ETH_ALEN))
++ continue;
++
++ if(psta->state & WIFI_ASOC_STATE)
++ {
++
++ if(psta->rssi_stat.UndecoratedSmoothedPWDB < tmpEntryMinPWDB)
++ tmpEntryMinPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB;
++
++ if(psta->rssi_stat.UndecoratedSmoothedPWDB > tmpEntryMaxPWDB)
++ tmpEntryMaxPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB;
++
++ PWDB_rssi[sta_cnt++] = (psta->mac_id | (psta->rssi_stat.UndecoratedSmoothedPWDB<<16));
++ }
++
++ }
++
++ }
++
++ _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
++
++
++
++ if(pHalData->fw_ractrl == _TRUE)
++ {
++ // Report every sta's RSSI to FW
++ for(i=0; i< sta_cnt; i++)
++ {
++ rtl8192c_set_rssi_cmd(Adapter, (u8*)&PWDB_rssi[i]);
++ }
++ }
++
++ }
++
++
++
++ if(tmpEntryMaxPWDB != 0) // If associated entry is found
++ {
++ pdmpriv->EntryMaxUndecoratedSmoothedPWDB = tmpEntryMaxPWDB;
++ }
++ else
++ {
++ pdmpriv->EntryMaxUndecoratedSmoothedPWDB = 0;
++ }
++
++ if(tmpEntryMinPWDB != 0xff) // If associated entry is found
++ {
++ pdmpriv->EntryMinUndecoratedSmoothedPWDB = tmpEntryMinPWDB;
++ }
++ else
++ {
++ pdmpriv->EntryMinUndecoratedSmoothedPWDB = 0;
++ }
++
++
++ if(check_fwstate(&Adapter->mlmepriv, WIFI_STATION_STATE) == _TRUE)
++ {
++
++ if(pHalData->fw_ractrl == _TRUE)
++ {
++ u32 param = (u32)(pdmpriv->UndecoratedSmoothedPWDB<<16);
++
++ param |= 0;//macid=0 for sta mode;
++
++ rtl8192c_set_rssi_cmd(Adapter, (u8*)&param);
++ }
++ }
++
++}
++
++
++static void
++DM_InitEdcaTurbo(
++ IN PADAPTER Adapter
++ )
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++
++ pHalData->bCurrentTurboEDCA = _FALSE;
++ Adapter->recvpriv.bIsAnyNonBEPkts = _FALSE;
++
++}
++
++
++static void
++dm_CheckEdcaTurbo(
++ IN PADAPTER Adapter
++ )
++{
++ u32 trafficIndex;
++ u32 edca_param;
++ u64 cur_tx_bytes = 0;
++ u64 cur_rx_bytes = 0;
++ u8 bbtchange = _FALSE;
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ struct dm_priv *pdmpriv = &pHalData->dmpriv;
++ struct xmit_priv *pxmitpriv = &(Adapter->xmitpriv);
++ struct recv_priv *precvpriv = &(Adapter->recvpriv);
++ struct registry_priv *pregpriv = &Adapter->registrypriv;
++ struct mlme_ext_priv *pmlmeext = &(Adapter->mlmeextpriv);
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++#ifdef CONFIG_BT_COEXIST
++ struct btcoexist_priv *pbtpriv = &(pHalData->bt_coexist);
++#endif
++
++
++ if ((pregpriv->wifi_spec == 1) || (pmlmeinfo->HT_enable == 0))
++ {
++ goto dm_CheckEdcaTurbo_EXIT;
++ }
++
++ if (pmlmeinfo->assoc_AP_vendor >= maxAP)
++ {
++ goto dm_CheckEdcaTurbo_EXIT;
++ }
++
++#ifdef CONFIG_BT_COEXIST
++ if(pbtpriv->BT_Coexist)
++ {
++ if( (pbtpriv->BT_EDCA[UP_LINK]!=0) || (pbtpriv->BT_EDCA[DOWN_LINK]!=0))
++ {
++ bbtchange = _TRUE;
++ }
++ }
++#endif
++
++ // Check if the status needs to be changed.
++ if((bbtchange) || (!precvpriv->bIsAnyNonBEPkts) )
++ {
++ cur_tx_bytes = pxmitpriv->tx_bytes - pxmitpriv->last_tx_bytes;
++ cur_rx_bytes = precvpriv->rx_bytes - precvpriv->last_rx_bytes;
++
++ //traffic, TX or RX
++ if((pmlmeinfo->assoc_AP_vendor == ralinkAP)||(pmlmeinfo->assoc_AP_vendor == atherosAP))
++ {
++ if (cur_tx_bytes > (cur_rx_bytes << 2))
++ { // Uplink TP is present.
++ trafficIndex = UP_LINK;
++ }
++ else
++ { // Balance TP is present.
++ trafficIndex = DOWN_LINK;
++ }
++ }
++ else
++ {
++ if (cur_rx_bytes > (cur_tx_bytes << 2))
++ { // Downlink TP is present.
++ trafficIndex = DOWN_LINK;
++ }
++ else
++ { // Balance TP is present.
++ trafficIndex = UP_LINK;
++ }
++ }
++
++ if ((pdmpriv->prv_traffic_idx != trafficIndex) || (!pHalData->bCurrentTurboEDCA))
++ {
++#ifdef CONFIG_BT_COEXIST
++ if(_TRUE == bbtchange)
++ {
++ edca_param = pbtpriv->BT_EDCA[trafficIndex];
++ }
++ else
++#endif
++ {
++#if 0
++ //adjust EDCA parameter for BE queue
++ edca_param = EDCAParam[pmlmeinfo->assoc_AP_vendor][trafficIndex];
++#else
++
++ if((pmlmeinfo->assoc_AP_vendor == ciscoAP) && (pmlmeext->cur_wireless_mode & WIRELESS_11_24N))
++ {
++ edca_param = EDCAParam[pmlmeinfo->assoc_AP_vendor][trafficIndex];
++ }
++ else
++ {
++ edca_param = EDCAParam[unknownAP][trafficIndex];
++ }
++#endif
++ }
++
++#ifdef CONFIG_PCI_HCI
++ if(IS_92C_SERIAL(pHalData->VersionID))
++ {
++ edca_param = 0x60a42b;
++ }
++ else
++ {
++ edca_param = 0x6ea42b;
++ }
++#endif
++ rtw_write32(Adapter, REG_EDCA_BE_PARAM, edca_param);
++
++ pdmpriv->prv_traffic_idx = trafficIndex;
++ }
++
++ pHalData->bCurrentTurboEDCA = _TRUE;
++ }
++ else
++ {
++ //
++ // Turn Off EDCA turbo here.
++ // Restore original EDCA according to the declaration of AP.
++ //
++ if(pHalData->bCurrentTurboEDCA)
++ {
++ rtw_write32(Adapter, REG_EDCA_BE_PARAM, pHalData->AcParam_BE);
++ pHalData->bCurrentTurboEDCA = _FALSE;
++ }
++ }
++
++dm_CheckEdcaTurbo_EXIT:
++ // Set variables for next time.
++ precvpriv->bIsAnyNonBEPkts = _FALSE;
++ pxmitpriv->last_tx_bytes = pxmitpriv->tx_bytes;
++ precvpriv->last_rx_bytes = precvpriv->rx_bytes;
++
++}
++
++#define DPK_DELTA_MAPPING_NUM 13
++#define index_mapping_HP_NUM 15
++
++static VOID
++dm_TXPowerTrackingCallback_ThermalMeter_92C(
++ IN PADAPTER Adapter)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ struct dm_priv *pdmpriv = &pHalData->dmpriv;
++ u8 ThermalValue = 0, delta, delta_LCK, delta_IQK, delta_HP, TimeOut = 100;
++ int ele_A, ele_D, TempCCk, X, value32;
++ int Y, ele_C;
++ s8 OFDM_index[2], CCK_index = 0, OFDM_index_old[2], CCK_index_old = 0;
++ int i = 0;
++ BOOLEAN is2T = IS_92C_SERIAL(pHalData->VersionID);
++
++#if MP_DRIVER == 1
++ PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx);
++ u8 *TxPwrLevel = pMptCtx->TxPwrLevel;
++#endif
++ u8 OFDM_min_index = 6, rf; //OFDM BB Swing should be less than +3.0dB, which is required by Arthur
++#if 0
++ u32 DPK_delta_mapping[2][DPK_DELTA_MAPPING_NUM] = {
++ {0x1c, 0x1c, 0x1d, 0x1d, 0x1e,
++ 0x1f, 0x00, 0x00, 0x01, 0x01,
++ 0x02, 0x02, 0x03},
++ {0x1c, 0x1d, 0x1e, 0x1e, 0x1e,
++ 0x1f, 0x00, 0x00, 0x01, 0x02,
++ 0x02, 0x03, 0x03}};
++#endif
++#ifdef CONFIG_USB_HCI
++ u8 ThermalValue_HP_count = 0;
++ u32 ThermalValue_HP = 0;
++ s32 index_mapping_HP[index_mapping_HP_NUM] = {
++ 0, 1, 3, 4, 6,
++ 7, 9, 10, 12, 13,
++ 15, 16, 18, 19, 21
++ };
++
++ s8 index_HP;
++#endif
++
++ pdmpriv->TXPowerTrackingCallbackCnt++; //cosa add for debug
++ pdmpriv->bTXPowerTrackingInit = _TRUE;
++
++ if(pHalData->CurrentChannel == 14 && !pdmpriv->bCCKinCH14)
++ pdmpriv->bCCKinCH14 = _TRUE;
++ else if(pHalData->CurrentChannel != 14 && pdmpriv->bCCKinCH14)
++ pdmpriv->bCCKinCH14 = _FALSE;
++
++ //DBG_8192C("===>dm_TXPowerTrackingCallback_ThermalMeter_92C\n");
++
++ ThermalValue = (u8)PHY_QueryRFReg(Adapter, RF_PATH_A, RF_T_METER, 0x1f); // 0x24: RF Reg[4:0]
++
++ //DBG_8192C("\n\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n",ThermalValue,pdmpriv->ThermalValue, pHalData->EEPROMThermalMeter);
++
++ rtl8192c_PHY_APCalibrate(Adapter, (ThermalValue - pHalData->EEPROMThermalMeter));
++
++ if(is2T)
++ rf = 2;
++ else
++ rf = 1;
++
++ if(ThermalValue)
++ {
++// if(!pHalData->ThermalValue)
++ {
++ //Query OFDM path A default setting
++ ele_D = PHY_QueryBBReg(Adapter, rOFDM0_XATxIQImbalance, bMaskDWord)&bMaskOFDM_D;
++ for(i=0; i<OFDM_TABLE_SIZE_92C; i++) //find the index
++ {
++ if(ele_D == (OFDMSwingTable[i]&bMaskOFDM_D))
++ {
++ OFDM_index_old[0] = (u8)i;
++ //DBG_8192C("Initial pathA ele_D reg0x%x = 0x%x, OFDM_index=0x%x\n", rOFDM0_XATxIQImbalance, ele_D, OFDM_index_old[0]);
++ break;
++ }
++ }
++
++ //Query OFDM path B default setting
++ if(is2T)
++ {
++ ele_D = PHY_QueryBBReg(Adapter, rOFDM0_XBTxIQImbalance, bMaskDWord)&bMaskOFDM_D;
++ for(i=0; i<OFDM_TABLE_SIZE_92C; i++) //find the index
++ {
++ if(ele_D == (OFDMSwingTable[i]&bMaskOFDM_D))
++ {
++ OFDM_index_old[1] = (u8)i;
++ //DBG_8192C("Initial pathB ele_D reg0x%x = 0x%x, OFDM_index=0x%x\n",rOFDM0_XBTxIQImbalance, ele_D, OFDM_index_old[1]);
++ break;
++ }
++ }
++ }
++
++ //Query CCK default setting From 0xa24
++ TempCCk = PHY_QueryBBReg(Adapter, rCCK0_TxFilter2, bMaskDWord)&bMaskCCK;
++ for(i=0 ; i<CCK_TABLE_SIZE ; i++)
++ {
++ if(pdmpriv->bCCKinCH14)
++ {
++ if(_rtw_memcmp((void*)&TempCCk, (void*)&CCKSwingTable_Ch14[i][2], 4)==_TRUE)
++ {
++ CCK_index_old =(u8)i;
++ //DBG_8192C("Initial reg0x%x = 0x%x, CCK_index=0x%x, ch 14 %d\n", rCCK0_TxFilter2, TempCCk, CCK_index_old, pdmpriv->bCCKinCH14);
++ break;
++ }
++ }
++ else
++ {
++ if(_rtw_memcmp((void*)&TempCCk, (void*)&CCKSwingTable_Ch1_Ch13[i][2], 4)==_TRUE)
++ {
++ CCK_index_old =(u8)i;
++ //DBG_8192C("Initial reg0x%x = 0x%x, CCK_index=0x%x, ch14 %d\n", rCCK0_TxFilter2, TempCCk, CCK_index_old, pdmpriv->bCCKinCH14);
++ break;
++ }
++ }
++ }
++
++ if(!pdmpriv->ThermalValue)
++ {
++ pdmpriv->ThermalValue = pHalData->EEPROMThermalMeter;
++ pdmpriv->ThermalValue_LCK = ThermalValue;
++ pdmpriv->ThermalValue_IQK = ThermalValue;
++ pdmpriv->ThermalValue_DPK = pHalData->EEPROMThermalMeter;
++
++#ifdef CONFIG_USB_HCI
++ for(i = 0; i < rf; i++)
++ pdmpriv->OFDM_index_HP[i] = pdmpriv->OFDM_index[i] = OFDM_index_old[i];
++ pdmpriv->CCK_index_HP = pdmpriv->CCK_index = CCK_index_old;
++#else
++ for(i = 0; i < rf; i++)
++ pdmpriv->OFDM_index[i] = OFDM_index_old[i];
++ pdmpriv->CCK_index = CCK_index_old;
++#endif
++ }
++
++#ifdef CONFIG_USB_HCI
++ if(pHalData->BoardType == BOARD_USB_High_PA)
++ {
++ pdmpriv->ThermalValue_HP[pdmpriv->ThermalValue_HP_index] = ThermalValue;
++ pdmpriv->ThermalValue_HP_index++;
++ if(pdmpriv->ThermalValue_HP_index == HP_THERMAL_NUM)
++ pdmpriv->ThermalValue_HP_index = 0;
++
++ for(i = 0; i < HP_THERMAL_NUM; i++)
++ {
++ if(pdmpriv->ThermalValue_HP[i])
++ {
++ ThermalValue_HP += pdmpriv->ThermalValue_HP[i];
++ ThermalValue_HP_count++;
++ }
++ }
++
++ if(ThermalValue_HP_count)
++ ThermalValue = (u8)(ThermalValue_HP / ThermalValue_HP_count);
++ }
++#endif
++ }
++
++ delta = (ThermalValue > pdmpriv->ThermalValue)?(ThermalValue - pdmpriv->ThermalValue):(pdmpriv->ThermalValue - ThermalValue);
++#ifdef CONFIG_USB_HCI
++ if(pHalData->BoardType == BOARD_USB_High_PA)
++ {
++ if(pdmpriv->bDoneTxpower)
++ delta_HP = (ThermalValue > pdmpriv->ThermalValue)?(ThermalValue - pdmpriv->ThermalValue):(pdmpriv->ThermalValue - ThermalValue);
++ else
++ delta_HP = ThermalValue > pHalData->EEPROMThermalMeter?(ThermalValue - pHalData->EEPROMThermalMeter):(pHalData->EEPROMThermalMeter - ThermalValue);
++ }
++ else
++#endif
++ {
++ delta_HP = 0;
++ }
++ delta_LCK = (ThermalValue > pdmpriv->ThermalValue_LCK)?(ThermalValue - pdmpriv->ThermalValue_LCK):(pdmpriv->ThermalValue_LCK - ThermalValue);
++ delta_IQK = (ThermalValue > pdmpriv->ThermalValue_IQK)?(ThermalValue - pdmpriv->ThermalValue_IQK):(pdmpriv->ThermalValue_IQK - ThermalValue);
++
++ //DBG_8192C("Readback Thermal Meter = 0x%lx pre thermal meter 0x%lx EEPROMthermalmeter 0x%lx delta 0x%lx delta_LCK 0x%lx delta_IQK 0x%lx\n", ThermalValue, pHalData->ThermalValue, pHalData->EEPROMThermalMeter, delta, delta_LCK, delta_IQK);
++
++ if(delta_LCK > 1)
++ {
++ pdmpriv->ThermalValue_LCK = ThermalValue;
++ rtl8192c_PHY_LCCalibrate(Adapter);
++ }
++
++ if((delta > 0 || delta_HP > 0) && pdmpriv->TxPowerTrackControl)
++ {
++#ifdef CONFIG_USB_HCI
++ if(pHalData->BoardType == BOARD_USB_High_PA)
++ {
++ pdmpriv->bDoneTxpower = _TRUE;
++ delta_HP = ThermalValue > pHalData->EEPROMThermalMeter?(ThermalValue - pHalData->EEPROMThermalMeter):(pHalData->EEPROMThermalMeter - ThermalValue);
++
++ if(delta_HP > index_mapping_HP_NUM-1)
++ index_HP = index_mapping_HP[index_mapping_HP_NUM-1];
++ else
++ index_HP = index_mapping_HP[delta_HP];
++
++ if(ThermalValue > pHalData->EEPROMThermalMeter) //set larger Tx power
++ {
++ for(i = 0; i < rf; i++)
++ OFDM_index[i] = pdmpriv->OFDM_index_HP[i] - index_HP;
++ CCK_index = pdmpriv->CCK_index_HP -index_HP;
++ }
++ else
++ {
++ for(i = 0; i < rf; i++)
++ OFDM_index[i] = pdmpriv->OFDM_index_HP[i] + index_HP;
++ CCK_index = pdmpriv->CCK_index_HP + index_HP;
++ }
++
++ delta_HP = (ThermalValue > pdmpriv->ThermalValue)?(ThermalValue - pdmpriv->ThermalValue):(pdmpriv->ThermalValue - ThermalValue);
++
++ }
++ else
++#endif
++ {
++ if(ThermalValue > pdmpriv->ThermalValue)
++ {
++ for(i = 0; i < rf; i++)
++ pdmpriv->OFDM_index[i] -= delta;
++ pdmpriv->CCK_index -= delta;
++ }
++ else
++ {
++ for(i = 0; i < rf; i++)
++ pdmpriv->OFDM_index[i] += delta;
++ pdmpriv->CCK_index += delta;
++ }
++ }
++
++ /*if(is2T)
++ {
++ DBG_8192C("temp OFDM_A_index=0x%x, OFDM_B_index=0x%x, CCK_index=0x%x\n",
++ pdmpriv->OFDM_index[0], pdmpriv->OFDM_index[1], pdmpriv->CCK_index);
++ }
++ else
++ {
++ DBG_8192C("temp OFDM_A_index=0x%x, CCK_index=0x%x\n",
++ pdmpriv->OFDM_index[0], pdmpriv->CCK_index);
++ }*/
++
++ //no adjust
++#ifdef CONFIG_USB_HCI
++ if(pHalData->BoardType != BOARD_USB_High_PA)
++#endif
++ {
++ if(ThermalValue > pHalData->EEPROMThermalMeter)
++ {
++ for(i = 0; i < rf; i++)
++ OFDM_index[i] = pdmpriv->OFDM_index[i]+1;
++ CCK_index = pdmpriv->CCK_index+1;
++ }
++ else
++ {
++ for(i = 0; i < rf; i++)
++ OFDM_index[i] = pdmpriv->OFDM_index[i];
++ CCK_index = pdmpriv->CCK_index;
++ }
++
++#if MP_DRIVER == 1
++ for(i = 0; i < rf; i++)
++ {
++ if(TxPwrLevel[i] >=0 && TxPwrLevel[i] <=26)
++ {
++ if(ThermalValue > pHalData->EEPROMThermalMeter)
++ {
++ if (delta < 5)
++ OFDM_index[i] -= 1;
++ else
++ OFDM_index[i] -= 2;
++ }
++ else if(delta > 5 && ThermalValue < pHalData->EEPROMThermalMeter)
++ {
++ OFDM_index[i] += 1;
++ }
++ }
++ else if (TxPwrLevel[i] >= 27 && TxPwrLevel[i] <= 32 && ThermalValue > pHalData->EEPROMThermalMeter)
++ {
++ if (delta < 5)
++ OFDM_index[i] -= 1;
++ else
++ OFDM_index[i] -= 2;
++ }
++ else if (TxPwrLevel[i] >= 32 && TxPwrLevel[i] <= 38 && ThermalValue > pHalData->EEPROMThermalMeter && delta > 5)
++ {
++ OFDM_index[i] -= 1;
++ }
++ }
++
++ {
++ if(TxPwrLevel[i] >=0 && TxPwrLevel[i] <=26)
++ {
++ if(ThermalValue > pHalData->EEPROMThermalMeter)
++ {
++ if (delta < 5)
++ CCK_index -= 1;
++ else
++ CCK_index -= 2;
++ }
++ else if(delta > 5 && ThermalValue < pHalData->EEPROMThermalMeter)
++ {
++ CCK_index += 1;
++ }
++ }
++ else if (TxPwrLevel[i] >= 27 && TxPwrLevel[i] <= 32 && ThermalValue > pHalData->EEPROMThermalMeter)
++ {
++ if (delta < 5)
++ CCK_index -= 1;
++ else
++ CCK_index -= 2;
++ }
++ else if (TxPwrLevel[i] >= 32 && TxPwrLevel[i] <= 38 && ThermalValue > pHalData->EEPROMThermalMeter && delta > 5)
++ {
++ CCK_index -= 1;
++ }
++ }
++#endif
++ }
++
++ for(i = 0; i < rf; i++)
++ {
++ if(OFDM_index[i] > (OFDM_TABLE_SIZE_92C-1))
++ OFDM_index[i] = (OFDM_TABLE_SIZE_92C-1);
++ else if (OFDM_index[i] < OFDM_min_index)
++ OFDM_index[i] = OFDM_min_index;
++ }
++
++ if(CCK_index > (CCK_TABLE_SIZE-1))
++ CCK_index = (CCK_TABLE_SIZE-1);
++ else if (CCK_index < 0)
++ CCK_index = 0;
++
++ /*if(is2T)
++ {
++ DBG_8192C("new OFDM_A_index=0x%x, OFDM_B_index=0x%x, CCK_index=0x%x\n",
++ OFDM_index[0], OFDM_index[1], CCK_index);
++ }
++ else
++ {
++ DBG_8192C("new OFDM_A_index=0x%x, CCK_index=0x%x\n",
++ OFDM_index[0], CCK_index);
++ }*/
++ }
++
++ if(pdmpriv->TxPowerTrackControl && (delta != 0 || delta_HP != 0))
++ {
++ //Adujst OFDM Ant_A according to IQK result
++ ele_D = (OFDMSwingTable[OFDM_index[0]] & 0xFFC00000)>>22;
++ X = pdmpriv->RegE94;
++ Y = pdmpriv->RegE9C;
++
++ if(X != 0)
++ {
++ if ((X & 0x00000200) != 0)
++ X = X | 0xFFFFFC00;
++ ele_A = ((X * ele_D)>>8)&0x000003FF;
++
++ //new element C = element D x Y
++ if ((Y & 0x00000200) != 0)
++ Y = Y | 0xFFFFFC00;
++ ele_C = ((Y * ele_D)>>8)&0x000003FF;
++
++ //wirte new elements A, C, D to regC80 and regC94, element B is always 0
++ value32 = (ele_D<<22)|((ele_C&0x3F)<<16)|ele_A;
++ PHY_SetBBReg(Adapter, rOFDM0_XATxIQImbalance, bMaskDWord, value32);
++
++ value32 = (ele_C&0x000003C0)>>6;
++ PHY_SetBBReg(Adapter, rOFDM0_XCTxAFE, bMaskH4Bits, value32);
++
++ value32 = ((X * ele_D)>>7)&0x01;
++ PHY_SetBBReg(Adapter, rOFDM0_ECCAThreshold, BIT31, value32);
++
++ value32 = ((Y * ele_D)>>7)&0x01;
++ PHY_SetBBReg(Adapter, rOFDM0_ECCAThreshold, BIT29, value32);
++
++ }
++ else
++ {
++ PHY_SetBBReg(Adapter, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable[OFDM_index[0]]);
++ PHY_SetBBReg(Adapter, rOFDM0_XCTxAFE, bMaskH4Bits, 0x00);
++ PHY_SetBBReg(Adapter, rOFDM0_ECCAThreshold, BIT31|BIT29, 0x00);
++ }
++
++ //RTPRINT(FINIT, INIT_IQK, ("TxPwrTracking path A: X = 0x%x, Y = 0x%x ele_A = 0x%x ele_C = 0x%x ele_D = 0x%x\n", X, Y, ele_A, ele_C, ele_D));
++
++ //Adjust CCK according to IQK result
++ if(!pdmpriv->bCCKinCH14){
++ rtw_write8(Adapter, 0xa22, CCKSwingTable_Ch1_Ch13[CCK_index][0]);
++ rtw_write8(Adapter, 0xa23, CCKSwingTable_Ch1_Ch13[CCK_index][1]);
++ rtw_write8(Adapter, 0xa24, CCKSwingTable_Ch1_Ch13[CCK_index][2]);
++ rtw_write8(Adapter, 0xa25, CCKSwingTable_Ch1_Ch13[CCK_index][3]);
++ rtw_write8(Adapter, 0xa26, CCKSwingTable_Ch1_Ch13[CCK_index][4]);
++ rtw_write8(Adapter, 0xa27, CCKSwingTable_Ch1_Ch13[CCK_index][5]);
++ rtw_write8(Adapter, 0xa28, CCKSwingTable_Ch1_Ch13[CCK_index][6]);
++ rtw_write8(Adapter, 0xa29, CCKSwingTable_Ch1_Ch13[CCK_index][7]);
++ }
++ else{
++ rtw_write8(Adapter, 0xa22, CCKSwingTable_Ch14[CCK_index][0]);
++ rtw_write8(Adapter, 0xa23, CCKSwingTable_Ch14[CCK_index][1]);
++ rtw_write8(Adapter, 0xa24, CCKSwingTable_Ch14[CCK_index][2]);
++ rtw_write8(Adapter, 0xa25, CCKSwingTable_Ch14[CCK_index][3]);
++ rtw_write8(Adapter, 0xa26, CCKSwingTable_Ch14[CCK_index][4]);
++ rtw_write8(Adapter, 0xa27, CCKSwingTable_Ch14[CCK_index][5]);
++ rtw_write8(Adapter, 0xa28, CCKSwingTable_Ch14[CCK_index][6]);
++ rtw_write8(Adapter, 0xa29, CCKSwingTable_Ch14[CCK_index][7]);
++ }
++
++ if(is2T)
++ {
++ ele_D = (OFDMSwingTable[(u8)OFDM_index[1]] & 0xFFC00000)>>22;
++
++ //new element A = element D x X
++ X = pdmpriv->RegEB4;
++ Y = pdmpriv->RegEBC;
++
++ if(X != 0){
++ if ((X & 0x00000200) != 0) //consider minus
++ X = X | 0xFFFFFC00;
++ ele_A = ((X * ele_D)>>8)&0x000003FF;
++
++ //new element C = element D x Y
++ if ((Y & 0x00000200) != 0)
++ Y = Y | 0xFFFFFC00;
++ ele_C = ((Y * ele_D)>>8)&0x00003FF;
++
++ //wirte new elements A, C, D to regC88 and regC9C, element B is always 0
++ value32=(ele_D<<22)|((ele_C&0x3F)<<16) |ele_A;
++ PHY_SetBBReg(Adapter, rOFDM0_XBTxIQImbalance, bMaskDWord, value32);
++
++ value32 = (ele_C&0x000003C0)>>6;
++ PHY_SetBBReg(Adapter, rOFDM0_XDTxAFE, bMaskH4Bits, value32);
++
++ value32 = ((X * ele_D)>>7)&0x01;
++ PHY_SetBBReg(Adapter, rOFDM0_ECCAThreshold, BIT27, value32);
++
++ value32 = ((Y * ele_D)>>7)&0x01;
++ PHY_SetBBReg(Adapter, rOFDM0_ECCAThreshold, BIT25, value32);
++
++ }
++ else{
++ PHY_SetBBReg(Adapter, rOFDM0_XBTxIQImbalance, bMaskDWord, OFDMSwingTable[OFDM_index[1]]);
++ PHY_SetBBReg(Adapter, rOFDM0_XDTxAFE, bMaskH4Bits, 0x00);
++ PHY_SetBBReg(Adapter, rOFDM0_ECCAThreshold, BIT27|BIT25, 0x00);
++ }
++
++ //DBG_8192C("TxPwrTracking path B: X = 0x%x, Y = 0x%x ele_A = 0x%x ele_C = 0x%x ele_D = 0x%x\n", X, Y, ele_A, ele_C, ele_D);
++ }
++
++ /*
++ DBG_8192C("TxPwrTracking 0xc80 = 0x%x, 0xc94 = 0x%x RF 0x24 = 0x%x\n", \
++ PHY_QueryBBReg(Adapter, 0xc80, bMaskDWord),\
++ PHY_QueryBBReg(Adapter, 0xc94, bMaskDWord), \
++ PHY_QueryRFReg(Adapter, RF_PATH_A, 0x24, bMaskDWord));
++ */
++ }
++
++#if MP_DRIVER == 1
++ if(delta_IQK > 1)
++#else
++ if(delta_IQK > 3)
++#endif
++ {
++ pdmpriv->ThermalValue_IQK = ThermalValue;
++ rtl8192c_PHY_IQCalibrate(Adapter,_FALSE);
++ }
++
++ //update thermal meter value
++ if(pdmpriv->TxPowerTrackControl)
++ pdmpriv->ThermalValue = ThermalValue;
++
++ }
++
++ //DBG_8192C("<===dm_TXPowerTrackingCallback_ThermalMeter_92C\n");
++
++ pdmpriv->TXPowercount = 0;
++
++}
++
++
++static VOID
++dm_InitializeTXPowerTracking_ThermalMeter(
++ IN PADAPTER Adapter)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ struct dm_priv *pdmpriv = &pHalData->dmpriv;
++
++ //pMgntInfo->bTXPowerTracking = _TRUE;
++ pdmpriv->TXPowercount = 0;
++ pdmpriv->bTXPowerTrackingInit = _FALSE;
++ pdmpriv->ThermalValue = 0;
++
++#if (MP_DRIVER != 1) //for mp driver, turn off txpwrtracking as default
++ pdmpriv->TxPowerTrackControl = _TRUE;
++#endif
++
++ MSG_8192C("pdmpriv->TxPowerTrackControl = %d\n", pdmpriv->TxPowerTrackControl);
++}
++
++
++static VOID
++DM_InitializeTXPowerTracking(
++ IN PADAPTER Adapter)
++{
++ dm_InitializeTXPowerTracking_ThermalMeter(Adapter);
++}
++
++//
++// Description:
++// - Dispatch TxPower Tracking direct call ONLY for 92s.
++// - We shall NOT schedule Workitem within PASSIVE LEVEL, which will cause system resource
++// leakage under some platform.
++//
++// Assumption:
++// PASSIVE_LEVEL when this routine is called.
++//
++// Added by Roger, 2009.06.18.
++//
++static VOID
++DM_TXPowerTracking92CDirectCall(
++ IN PADAPTER Adapter)
++{
++ dm_TXPowerTrackingCallback_ThermalMeter_92C(Adapter);
++}
++
++static VOID
++dm_CheckTXPowerTracking_ThermalMeter(
++ IN PADAPTER Adapter)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ struct dm_priv *pdmpriv = &pHalData->dmpriv;
++ //u1Byte TxPowerCheckCnt = 5; //10 sec
++
++ //if(!pMgntInfo->bTXPowerTracking /*|| (!pdmpriv->TxPowerTrackControl && pdmpriv->bAPKdone)*/)
++ if(!(pdmpriv->DMFlag & DYNAMIC_FUNC_SS))
++ {
++ return;
++ }
++
++ if(!pdmpriv->TM_Trigger) //at least delay 1 sec
++ {
++ //pHalData->TxPowerCheckCnt++; //cosa add for debug
++ PHY_SetRFReg(Adapter, RF_PATH_A, RF_T_METER, bRFRegOffsetMask, 0x60);
++ //DBG_8192C("Trigger 92C Thermal Meter!!\n");
++
++ pdmpriv->TM_Trigger = 1;
++ return;
++
++ }
++ else
++ {
++ //DBG_8192C("Schedule TxPowerTracking direct call!!\n");
++ DM_TXPowerTracking92CDirectCall(Adapter); //Using direct call is instead, added by Roger, 2009.06.18.
++ pdmpriv->TM_Trigger = 0;
++ }
++
++}
++
++
++VOID
++rtl8192c_dm_CheckTXPowerTracking(
++ IN PADAPTER Adapter)
++{
++ dm_CheckTXPowerTracking_ThermalMeter(Adapter);
++}
++
++#ifdef CONFIG_BT_COEXIST
++static BOOLEAN BT_BTStateChange(PADAPTER Adapter)
++{
++ PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
++ struct btcoexist_priv *pbtpriv = &(pHalData->bt_coexist);
++ struct registry_priv *registry_par = &Adapter->registrypriv;
++
++ struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv);
++
++ u32 Polling, Ratio_Tx, Ratio_PRI;
++ u32 BT_Tx, BT_PRI;
++ u8 BT_State;
++ static u8 ServiceTypeCnt = 0;
++ u8 CurServiceType;
++ static u8 LastServiceType = BT_Idle;
++
++ if(check_fwstate(pmlmepriv, _FW_LINKED) == _FALSE)
++ return _FALSE;
++
++ BT_State = rtw_read8(Adapter, 0x4fd);
++/*
++ temp = PlatformEFIORead4Byte(Adapter, 0x488);
++ BT_Tx = (u2Byte)(((temp<<8)&0xff00)+((temp>>8)&0xff));
++ BT_PRI = (u2Byte)(((temp>>8)&0xff00)+((temp>>24)&0xff));
++
++ temp = PlatformEFIORead4Byte(Adapter, 0x48c);
++ Polling = ((temp<<8)&0xff000000) + ((temp>>8)&0x00ff0000) +
++ ((temp<<8)&0x0000ff00) + ((temp>>8)&0x000000ff);
++
++*/
++ BT_Tx = rtw_read32(Adapter, 0x488);
++
++ DBG_8192C("Ratio 0x488 =%x\n", BT_Tx);
++ BT_Tx =BT_Tx & 0x00ffffff;
++ //RTPRINT(FBT, BT_TRACE, ("Ratio BT_Tx =%x\n", BT_Tx));
++
++ BT_PRI = rtw_read32(Adapter, 0x48c);
++
++ DBG_8192C("Ratio 0x48c =%x\n", BT_PRI);
++ BT_PRI =BT_PRI & 0x00ffffff;
++ //RTPRINT(FBT, BT_TRACE, ("Ratio BT_PRI =%x\n", BT_PRI));
++
++
++ Polling = rtw_read32(Adapter, 0x490);
++ //RTPRINT(FBT, BT_TRACE, ("Ratio 0x490 =%x\n", Polling));
++
++
++ if(BT_Tx==0xffffffff && BT_PRI==0xffffffff && Polling==0xffffffff && BT_State==0xff)
++ return _FALSE;
++
++ BT_State &= BIT0;
++
++ if(BT_State != pbtpriv->BT_CUR_State)
++ {
++ pbtpriv->BT_CUR_State = BT_State;
++
++ if(registry_par->bt_sco == 3)
++ {
++ ServiceTypeCnt = 0;
++
++ pbtpriv->BT_Service = BT_Idle;
++
++ DBG_8192C("BT_%s\n", BT_State?"ON":"OFF");
++
++ BT_State = BT_State |
++ ((pbtpriv->BT_Ant_isolation==1)?0:BIT1) |BIT2;
++
++ rtw_write8(Adapter, 0x4fd, BT_State);
++ DBG_8192C("BT set 0x4fd to %x\n", BT_State);
++ }
++
++ return _TRUE;
++ }
++ DBG_8192C("bRegBT_Sco = %d\n",registry_par->bt_sco);
++
++ Ratio_Tx = BT_Tx*1000/Polling;
++ Ratio_PRI = BT_PRI*1000/Polling;
++
++ pbtpriv->Ratio_Tx=Ratio_Tx;
++ pbtpriv->Ratio_PRI=Ratio_PRI;
++
++ DBG_8192C("Ratio_Tx=%d\n", Ratio_Tx);
++ DBG_8192C("Ratio_PRI=%d\n", Ratio_PRI);
++
++
++ if(BT_State && registry_par->bt_sco==3)
++ {
++ DBG_8192C("bt_sco ==3 Follow Counter\n");
++// if(BT_Tx==0xffff && BT_PRI==0xffff && Polling==0xffffffff)
++// {
++// ServiceTypeCnt = 0;
++// return FALSE;
++// }
++// else
++ {
++ /*
++ Ratio_Tx = BT_Tx*1000/Polling;
++ Ratio_PRI = BT_PRI*1000/Polling;
++
++ pHalData->bt_coexist.Ratio_Tx=Ratio_Tx;
++ pHalData->bt_coexist.Ratio_PRI=Ratio_PRI;
++
++ RTPRINT(FBT, BT_TRACE, ("Ratio_Tx=%d\n", Ratio_Tx));
++ RTPRINT(FBT, BT_TRACE, ("Ratio_PRI=%d\n", Ratio_PRI));
++
++ */
++ if((Ratio_Tx < 30) && (Ratio_PRI < 30))
++ CurServiceType = BT_Idle;
++ else if((Ratio_PRI > 110) && (Ratio_PRI < 250))
++ CurServiceType = BT_SCO;
++ else if((Ratio_Tx >= 200)&&(Ratio_PRI >= 200))
++ CurServiceType = BT_Busy;
++ else if((Ratio_Tx >=350) && (Ratio_Tx < 500))
++ CurServiceType = BT_OtherBusy;
++ else if(Ratio_Tx >=500)
++ CurServiceType = BT_PAN;
++ else
++ CurServiceType=BT_OtherAction;
++ }
++
++/* if(pHalData->bt_coexist.bStopCount)
++ {
++ ServiceTypeCnt=0;
++ pHalData->bt_coexist.bStopCount=FALSE;
++ }
++*/
++// if(CurServiceType == BT_OtherBusy)
++ {
++ ServiceTypeCnt=2;
++ LastServiceType=CurServiceType;
++ }
++#if 0
++ else if(CurServiceType == LastServiceType)
++ {
++ if(ServiceTypeCnt<3)
++ ServiceTypeCnt++;
++ }
++ else
++ {
++ ServiceTypeCnt = 0;
++ LastServiceType = CurServiceType;
++ }
++#endif
++
++ if(ServiceTypeCnt==2)
++ {
++ pbtpriv->BT_Service = LastServiceType;
++ BT_State = BT_State |
++ ((pbtpriv->BT_Ant_isolation==1)?0:BIT1) |
++ //((pbtpriv->BT_Service==BT_SCO)?0:BIT2);
++ ((pbtpriv->BT_Service!=BT_Idle)?0:BIT2);
++
++ //if(pbtpriv->BT_Service==BT_Busy)
++ // BT_State&= ~(BIT2);
++
++ if(pbtpriv->BT_Service==BT_SCO)
++ {
++ DBG_8192C("BT TYPE Set to ==> BT_SCO\n");
++ }
++ else if(pbtpriv->BT_Service==BT_Idle)
++ {
++ DBG_8192C("BT TYPE Set to ==> BT_Idle\n");
++ }
++ else if(pbtpriv->BT_Service==BT_OtherAction)
++ {
++ DBG_8192C("BT TYPE Set to ==> BT_OtherAction\n");
++ }
++ else if(pbtpriv->BT_Service==BT_Busy)
++ {
++ DBG_8192C("BT TYPE Set to ==> BT_Busy\n");
++ }
++ else if(pbtpriv->BT_Service==BT_PAN)
++ {
++ DBG_8192C("BT TYPE Set to ==> BT_PAN\n");
++ }
++ else
++ {
++ DBG_8192C("BT TYPE Set to ==> BT_OtherBusy\n");
++ }
++
++ //Add interrupt migration when bt is not in idel state (no traffic).
++ //suggestion by Victor.
++ if(pbtpriv->BT_Service!=BT_Idle)//EDCA_VI_PARAM modify
++ {
++
++ rtw_write16(Adapter, 0x504, 0x0ccc);
++ rtw_write8(Adapter, 0x506, 0x54);
++ rtw_write8(Adapter, 0x507, 0x54);
++
++ }
++ else
++ {
++ rtw_write8(Adapter, 0x506, 0x00);
++ rtw_write8(Adapter, 0x507, 0x00);
++ }
++
++ rtw_write8(Adapter, 0x4fd, BT_State);
++ DBG_8192C("BT_SCO set 0x4fd to %x\n", BT_State);
++ return _TRUE;
++ }
++ }
++
++ return _FALSE;
++
++}
++
++static BOOLEAN
++BT_WifiConnectChange(
++ IN PADAPTER Adapter
++ )
++{
++ struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv);
++// PMGNT_INFO pMgntInfo = &Adapter->MgntInfo;
++ static BOOLEAN bMediaConnect = _FALSE;
++
++ //if(!pMgntInfo->bMediaConnect || MgntRoamingInProgress(pMgntInfo))
++ if(check_fwstate(pmlmepriv, _FW_LINKED) == _FALSE)
++ {
++ bMediaConnect = _FALSE;
++ }
++ else
++ {
++ if(!bMediaConnect)
++ {
++ bMediaConnect = _TRUE;
++ return _TRUE;
++ }
++ bMediaConnect = _TRUE;
++ }
++
++ return _FALSE;
++}
++
++#define BT_RSSI_STATE_NORMAL_POWER BIT0
++#define BT_RSSI_STATE_AMDPU_OFF BIT1
++#define BT_RSSI_STATE_SPECIAL_LOW BIT2
++#define BT_RSSI_STATE_BG_EDCA_LOW BIT3
++
++static s32 GET_UNDECORATED_AVERAGE_RSSI(PADAPTER Adapter)
++{
++ PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
++ struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv);
++ struct dm_priv *pdmpriv = &pHalData->dmpriv;
++ s32 average_rssi;
++
++ if(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE|WIFI_AP_STATE))
++ {
++ average_rssi = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
++ }
++ else
++ {
++ average_rssi = pdmpriv->UndecoratedSmoothedPWDB;
++ }
++ return average_rssi;
++}
++
++static u8 BT_RssiStateChange(
++ IN PADAPTER Adapter
++ )
++{
++ PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
++ struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv);
++ struct btcoexist_priv *pbtpriv = &(pHalData->bt_coexist);
++ struct dm_priv *pdmpriv = &pHalData->dmpriv;
++ //PMGNT_INFO pMgntInfo = &Adapter->MgntInfo;
++ s32 UndecoratedSmoothedPWDB;
++ u8 CurrBtRssiState = 0x00;
++
++
++
++
++ //if(pMgntInfo->bMediaConnect) // Default port
++ if(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)
++ {
++ UndecoratedSmoothedPWDB = GET_UNDECORATED_AVERAGE_RSSI(Adapter);
++ }
++ else // associated entry pwdb
++ {
++ if(pdmpriv->EntryMinUndecoratedSmoothedPWDB == 0)
++ UndecoratedSmoothedPWDB = 100; // No any RSSI information. Assume to be MAX.
++ else
++ UndecoratedSmoothedPWDB = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
++ }
++
++ // Check RSSI to determine HighPower/NormalPower state for BT coexistence.
++ if(UndecoratedSmoothedPWDB >= 67)
++ CurrBtRssiState &= (~BT_RSSI_STATE_NORMAL_POWER);
++ else if(UndecoratedSmoothedPWDB < 62)
++ CurrBtRssiState |= BT_RSSI_STATE_NORMAL_POWER;
++
++ // Check RSSI to determine AMPDU setting for BT coexistence.
++ if(UndecoratedSmoothedPWDB >= 40)
++ CurrBtRssiState &= (~BT_RSSI_STATE_AMDPU_OFF);
++ else if(UndecoratedSmoothedPWDB <= 32)
++ CurrBtRssiState |= BT_RSSI_STATE_AMDPU_OFF;
++
++ // Marked RSSI state. It will be used to determine BT coexistence setting later.
++ if(UndecoratedSmoothedPWDB < 35)
++ CurrBtRssiState |= BT_RSSI_STATE_SPECIAL_LOW;
++ else
++ CurrBtRssiState &= (~BT_RSSI_STATE_SPECIAL_LOW);
++
++ // Check BT state related to BT_Idle in B/G mode.
++ if(UndecoratedSmoothedPWDB < 15)
++ CurrBtRssiState |= BT_RSSI_STATE_BG_EDCA_LOW;
++ else
++ CurrBtRssiState &= (~BT_RSSI_STATE_BG_EDCA_LOW);
++
++ if(CurrBtRssiState != pbtpriv->BtRssiState)
++ {
++ pbtpriv->BtRssiState = CurrBtRssiState;
++ return _TRUE;
++ }
++ else
++ {
++ return _FALSE;
++ }
++}
++
++static void dm_BTCoexist(PADAPTER Adapter )
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ struct dm_priv *pdmpriv = &pHalData->dmpriv;
++ struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv);
++ struct mlme_ext_info *pmlmeinfo = &Adapter->mlmeextpriv.mlmext_info;
++ struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
++
++ struct btcoexist_priv *pbtpriv = &(pHalData->bt_coexist);
++ //PMGNT_INFO pMgntInfo = &Adapter->MgntInfo;
++ //PRT_HIGH_THROUGHPUT pHTInfo = GET_HT_INFO(pMgntInfo);
++
++ //PRX_TS_RECORD pRxTs = NULL;
++ u8 BT_gpio_mux;
++
++ BOOLEAN bWifiConnectChange, bBtStateChange,bRssiStateChange;
++
++ if(pbtpriv->bCOBT == _FALSE) return;
++
++ if(!( pdmpriv->DMFlag & DYNAMIC_FUNC_BT)) return;
++
++ if( (pbtpriv->BT_Coexist) &&(pbtpriv->BT_CoexistType == BT_CSR_BC4) && (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _FALSE) )
++ {
++ bWifiConnectChange = BT_WifiConnectChange(Adapter);
++ bBtStateChange = BT_BTStateChange(Adapter);
++ bRssiStateChange = BT_RssiStateChange(Adapter);
++
++ DBG_8192C("bWifiConnectChange %d, bBtStateChange %d,bRssiStateChange %d\n",
++ bWifiConnectChange,bBtStateChange,bRssiStateChange);
++
++ // add by hpfan for debug message
++ BT_gpio_mux = rtw_read8(Adapter, REG_GPIO_MUXCFG);
++ DBG_8192C("BTCoexit Reg_0x40 (%2x)\n", BT_gpio_mux);
++
++ if( bWifiConnectChange ||bBtStateChange ||bRssiStateChange )
++ {
++ if(pbtpriv->BT_CUR_State)
++ {
++
++ // Do not allow receiving A-MPDU aggregation.
++ if(pbtpriv->BT_Ampdu)// 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU.
++ {
++
++ if(pmlmeinfo->assoc_AP_vendor == ciscoAP)
++ {
++ if(pbtpriv->BT_Service!=BT_Idle)
++ {
++ if(pmlmeinfo->bAcceptAddbaReq)
++ {
++ DBG_8192C("BT_Disallow AMPDU \n");
++ pmlmeinfo->bAcceptAddbaReq = _FALSE;
++ send_delba(Adapter,0, get_my_bssid(&(pmlmeinfo->network)));
++ }
++ }
++ else
++ {
++ if(!pmlmeinfo->bAcceptAddbaReq)
++ {
++ DBG_8192C("BT_Allow AMPDU RSSI >=40\n");
++ pmlmeinfo->bAcceptAddbaReq = _TRUE;
++ }
++ }
++ }
++ else
++ {
++ if(!pmlmeinfo->bAcceptAddbaReq)
++ {
++ DBG_8192C("BT_Allow AMPDU BT Idle\n");
++ pmlmeinfo->bAcceptAddbaReq = _TRUE;
++ }
++ }
++ }
++
++#if 0
++ else if((pHalData->bt_coexist.BT_Service==BT_SCO) || (pHalData->bt_coexist.BT_Service==BT_Busy))
++ {
++ if(pHalData->bt_coexist.BtRssiState & BT_RSSI_STATE_AMDPU_OFF)
++ {
++ if(pMgntInfo->bBT_Ampdu && pHTInfo->bAcceptAddbaReq)
++ {
++ RTPRINT(FBT, BT_TRACE, ("BT_Disallow AMPDU RSSI <=32\n"));
++ pHTInfo->bAcceptAddbaReq = FALSE;
++ if(GetTs(Adapter, (PTS_COMMON_INFO*)(&pRxTs), pMgntInfo->Bssid, 0, RX_DIR, FALSE))
++ TsInitDelBA(Adapter, (PTS_COMMON_INFO)pRxTs, RX_DIR);
++ }
++ }
++ else
++ {
++ if(pMgntInfo->bBT_Ampdu && !pHTInfo->bAcceptAddbaReq)
++ {
++ RTPRINT(FBT, BT_TRACE, ("BT_Allow AMPDU RSSI >=40\n"));
++ pHTInfo->bAcceptAddbaReq = TRUE;
++ }
++ }
++ }
++ else
++ {
++ if(pMgntInfo->bBT_Ampdu && !pHTInfo->bAcceptAddbaReq)
++ {
++ RTPRINT(FBT, BT_TRACE, ("BT_Allow AMPDU BT not in SCO or BUSY\n"));
++ pHTInfo->bAcceptAddbaReq = TRUE;
++ }
++ }
++#endif
++
++ if(pbtpriv->BT_Ant_isolation)
++ {
++ DBG_8192C("BT_IsolationLow\n");
++
++// 20100427 Joseph: Do not adjust Rate adaptive for BT coexist suggested by SD3.
++#if 0
++ RTPRINT(FBT, BT_TRACE, ("BT_Update Rate table\n"));
++ if(pMgntInfo->bUseRAMask)
++ {
++ // 20100407 Joseph: Fix rate adaptive modification for BT coexist.
++ // This fix is not complete yet. It shall also consider VWifi and Adhoc case,
++ // which connect with multiple STAs.
++ Adapter->HalFunc.UpdateHalRAMaskHandler(
++ Adapter,
++ FALSE,
++ 0,
++ NULL,
++ NULL,
++ pMgntInfo->RateAdaptive.RATRState,
++ RAMask_Normal);
++ }
++ else
++ {
++ Adapter->HalFunc.UpdateHalRATRTableHandler(
++ Adapter,
++ &pMgntInfo->dot11OperationalRateSet,
++ pMgntInfo->dot11HTOperationalRateSet,NULL);
++ }
++#endif
++
++ // 20100415 Joseph: Modify BT coexist mechanism suggested by Yaying.
++ // Now we only enable HW BT coexist when BT in "Busy" state.
++ if(1)//pMgntInfo->LinkDetectInfo.NumRecvDataInPeriod >= 20)
++ {
++ if((pmlmeinfo->assoc_AP_vendor == ciscoAP) &&
++ pbtpriv->BT_Service==BT_OtherAction)
++ {
++ DBG_8192C("BT_Turn ON Coexist\n");
++ rtw_write8(Adapter, REG_GPIO_MUXCFG, 0xa0);
++ }
++ else
++ {
++ if((pbtpriv->BT_Service==BT_Busy) &&
++ (pbtpriv->BtRssiState & BT_RSSI_STATE_NORMAL_POWER))
++ {
++ DBG_8192C("BT_Turn ON Coexist\n");
++ rtw_write8(Adapter, REG_GPIO_MUXCFG, 0xa0);
++ }
++ else if((pbtpriv->BT_Service==BT_OtherAction) &&
++ (pbtpriv->BtRssiState & BT_RSSI_STATE_SPECIAL_LOW))
++ {
++ DBG_8192C("BT_Turn ON Coexist\n");
++ rtw_write8(Adapter, REG_GPIO_MUXCFG, 0xa0);
++ }
++ else if(pbtpriv->BT_Service==BT_PAN)
++ {
++ DBG_8192C("BT_Turn ON Coexist\n");
++ rtw_write8(Adapter, REG_GPIO_MUXCFG, 0x00);
++ }
++ else
++ {
++ DBG_8192C("BT_Turn OFF Coexist\n");
++ rtw_write8(Adapter, REG_GPIO_MUXCFG, 0x00);
++ }
++ }
++ }
++ else
++ {
++ DBG_8192C("BT: There is no Wifi traffic!! Turn off Coexist\n");
++ rtw_write8(Adapter, REG_GPIO_MUXCFG, 0x00);
++ }
++
++ if(1)//pMgntInfo->LinkDetectInfo.NumRecvDataInPeriod >= 20)
++ {
++ if(pbtpriv->BT_Service==BT_PAN)
++ {
++ DBG_8192C("BT_Turn ON Coexist(Reg0x44 = 0x10100)\n");
++ rtw_write32(Adapter, REG_GPIO_PIN_CTRL, 0x10100);
++ }
++ else
++ {
++ DBG_8192C("BT_Turn OFF Coexist(Reg0x44 = 0x0)\n");
++ rtw_write32(Adapter, REG_GPIO_PIN_CTRL, 0x0);
++ }
++ }
++ else
++ {
++ DBG_8192C("BT: There is no Wifi traffic!! Turn off Coexist(Reg0x44 = 0x0)\n");
++ rtw_write32(Adapter, REG_GPIO_PIN_CTRL, 0x0);
++ }
++
++ // 20100430 Joseph: Integrate the BT coexistence EDCA tuning here.
++ if(pbtpriv->BtRssiState & BT_RSSI_STATE_NORMAL_POWER)
++ {
++ if(pbtpriv->BT_Service==BT_OtherBusy)
++ {
++ //pbtpriv->BtEdcaUL = 0x5ea72b;
++ //pbtpriv->BtEdcaDL = 0x5ea72b;
++ pbtpriv->BT_EDCA[UP_LINK] = 0x5ea72b;
++ pbtpriv->BT_EDCA[DOWN_LINK] = 0x5ea72b;
++
++ DBG_8192C("BT in BT_OtherBusy state Tx (%d) >350 parameter(0x%x) = 0x%x\n", pbtpriv->Ratio_Tx ,REG_EDCA_BE_PARAM, 0x5ea72b);
++ }
++ else if(pbtpriv->BT_Service==BT_Busy)
++ {
++ //pbtpriv->BtEdcaUL = 0x5eb82f;
++ //pbtpriv->BtEdcaDL = 0x5eb82f;
++
++ pbtpriv->BT_EDCA[UP_LINK] = 0x5eb82f;
++ pbtpriv->BT_EDCA[DOWN_LINK] = 0x5eb82f;
++
++ DBG_8192C("BT in BT_Busy state parameter(0x%x) = 0x%x\n", REG_EDCA_BE_PARAM, 0x5eb82f);
++ }
++ else if(pbtpriv->BT_Service==BT_SCO)
++ {
++ if(pbtpriv->Ratio_Tx>160)
++ {
++ //pbtpriv->BtEdcaUL = 0x5ea72f;
++ //pbtpriv->BtEdcaDL = 0x5ea72f;
++ pbtpriv->BT_EDCA[UP_LINK] = 0x5ea72f;
++ pbtpriv->BT_EDCA[DOWN_LINK] = 0x5ea72f;
++ DBG_8192C("BT in BT_SCO state Tx (%d) >160 parameter(0x%x) = 0x%x\n",pbtpriv->Ratio_Tx, REG_EDCA_BE_PARAM, 0x5ea72f);
++ }
++ else
++ {
++ //pbtpriv->BtEdcaUL = 0x5ea32b;
++ //pbtpriv->BtEdcaDL = 0x5ea42b;
++
++ pbtpriv->BT_EDCA[UP_LINK] = 0x5ea32b;
++ pbtpriv->BT_EDCA[DOWN_LINK] = 0x5ea42b;
++
++ DBG_8192C("BT in BT_SCO state Tx (%d) <160 parameter(0x%x) = 0x%x\n", pbtpriv->Ratio_Tx,REG_EDCA_BE_PARAM, 0x5ea32f);
++ }
++ }
++ else
++ {
++ // BT coexistence mechanism does not control EDCA parameter.
++ //pbtpriv->BtEdcaUL = 0;
++ //pbtpriv->BtEdcaDL = 0;
++
++ pbtpriv->BT_EDCA[UP_LINK] = 0;
++ pbtpriv->BT_EDCA[DOWN_LINK] = 0;
++ DBG_8192C("BT in State %d and parameter(0x%x) use original setting.\n",pbtpriv->BT_Service, REG_EDCA_BE_PARAM);
++ }
++
++ if((pbtpriv->BT_Service!=BT_Idle) &&
++ (pmlmeext->cur_wireless_mode == WIRELESS_MODE_G) &&
++ (pbtpriv->BtRssiState & BT_RSSI_STATE_BG_EDCA_LOW))
++ {
++ //pbtpriv->BtEdcaUL = 0x5eb82b;
++ //pbtpriv->BtEdcaDL = 0x5eb82b;
++
++ pbtpriv->BT_EDCA[UP_LINK] = 0x5eb82b;
++ pbtpriv->BT_EDCA[DOWN_LINK] = 0x5eb82b;
++
++ DBG_8192C("BT set parameter(0x%x) = 0x%x\n", REG_EDCA_BE_PARAM, 0x5eb82b);
++ }
++ }
++ else
++ {
++ // BT coexistence mechanism does not control EDCA parameter.
++ //pbtpriv->BtEdcaUL = 0;
++ //pbtpriv->BtEdcaDL = 0;
++
++ pbtpriv->BT_EDCA[UP_LINK] = 0;
++ pbtpriv->BT_EDCA[DOWN_LINK] = 0;
++ }
++
++ // 20100415 Joseph: Set RF register 0x1E and 0x1F for BT coexist suggested by Yaying.
++ if(pbtpriv->BT_Service!=BT_Idle)
++ {
++ DBG_8192C("BT Set RfReg0x1E[7:4] = 0x%x \n", 0xf);
++ PHY_SetRFReg(Adapter, PathA, 0x1e, 0xf0, 0xf);
++ //RTPRINT(FBT, BT_TRACE, ("BT Set RfReg0x1E[7:4] = 0x%x \n", 0xf));
++ //PHY_SetRFReg(Adapter, PathA, 0x1f, 0xf0, 0xf);
++ }
++ else
++ {
++ DBG_8192C("BT Set RfReg0x1E[7:4] = 0x%x \n",pbtpriv->BtRfRegOrigin1E);
++ PHY_SetRFReg(Adapter, PathA, 0x1e, 0xf0, pbtpriv->BtRfRegOrigin1E);
++ //RTPRINT(FBT, BT_TRACE, ("BT Set RfReg0x1F[7:4] = 0x%x \n", pHalData->bt_coexist.BtRfRegOrigin1F));
++ //PHY_SetRFReg(Adapter, PathA, 0x1f, 0xf0, pHalData->bt_coexist.BtRfRegOrigin1F);
++ }
++ }
++ else
++ {
++ DBG_8192C("BT_IsolationHigh\n");
++ // Do nothing.
++ }
++ }
++ else
++ {
++
++ if(pbtpriv->BT_Ampdu && !pmlmeinfo->bAcceptAddbaReq)
++ {
++ DBG_8192C("BT_Allow AMPDU bt is off\n");
++ pmlmeinfo->bAcceptAddbaReq = _TRUE;
++ }
++
++ DBG_8192C("BT_Turn OFF Coexist bt is off \n");
++ rtw_write8(Adapter, REG_GPIO_MUXCFG, 0x00);
++
++ DBG_8192C("BT Set RfReg0x1E[7:4] = 0x%x \n", pbtpriv->BtRfRegOrigin1E);
++ PHY_SetRFReg(Adapter, PathA, 0x1e, 0xf0, pbtpriv->BtRfRegOrigin1E);
++ //RTPRINT(FBT, BT_TRACE, ("BT Set RfReg0x1F[7:4] = 0x%x \n", pHalData->bt_coexist.BtRfRegOrigin1F));
++ //PHY_SetRFReg(Adapter, PathA, 0x1f, 0xf0, pHalData->bt_coexist.BtRfRegOrigin1F);
++
++ // BT coexistence mechanism does not control EDCA parameter since BT is disabled.
++ //pbtpriv->BtEdcaUL = 0;
++ //pbtpriv->BtEdcaDL = 0;
++ pbtpriv->BT_EDCA[UP_LINK] = 0;
++ pbtpriv->BT_EDCA[DOWN_LINK] = 0;
++
++
++// 20100427 Joseph: Do not adjust Rate adaptive for BT coexist suggested by SD3.
++#if 0
++ RTPRINT(FBT, BT_TRACE, ("BT_Update Rate table\n"));
++ if(pMgntInfo->bUseRAMask)
++ {
++ // 20100407 Joseph: Fix rate adaptive modification for BT coexist.
++ // This fix is not complete yet. It shall also consider VWifi and Adhoc case,
++ // which connect with multiple STAs.
++ Adapter->HalFunc.UpdateHalRAMaskHandler(
++ Adapter,
++ FALSE,
++ 0,
++ NULL,
++ NULL,
++ pMgntInfo->RateAdaptive.RATRState,
++ RAMask_Normal);
++ }
++ else
++ {
++ Adapter->HalFunc.UpdateHalRATRTableHandler(
++ Adapter,
++ &pMgntInfo->dot11OperationalRateSet,
++ pMgntInfo->dot11HTOperationalRateSet,NULL);
++ }
++#endif
++ }
++ }
++ }
++}
++
++static void dm_InitBtCoexistDM( PADAPTER Adapter)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ struct btcoexist_priv *pbtpriv = &(pHalData->bt_coexist);
++
++ if( !pbtpriv->BT_Coexist ) return;
++
++ pbtpriv->BtRfRegOrigin1E = (u8)PHY_QueryRFReg(Adapter, PathA, 0x1e, 0xf0);
++ pbtpriv->BtRfRegOrigin1F = (u8)PHY_QueryRFReg(Adapter, PathA, 0x1f, 0xf0);
++}
++
++void rtl8192c_set_dm_bt_coexist(_adapter *padapter, u8 bStart)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ struct btcoexist_priv *pbtpriv = &(pHalData->bt_coexist);
++
++ pbtpriv->bCOBT = bStart;
++ send_delba(padapter,0, get_my_bssid(&(pmlmeinfo->network)));
++ send_delba(padapter,1, get_my_bssid(&(pmlmeinfo->network)));
++
++}
++
++void rtl8192c_issue_delete_ba(_adapter *padapter, u8 dir)
++{
++ struct mlme_ext_info *pmlmeinfo = &padapter->mlmeextpriv.mlmext_info;
++ DBG_8192C("issue_delete_ba : %s...\n",(dir==0)?"RX_DIR":"TX_DIR");
++ send_delba(padapter,dir, get_my_bssid(&(pmlmeinfo->network)));
++}
++
++#endif
++
++#if 0//def CONFIG_PCI_HCI
++
++BOOLEAN
++BT_BTStateChange(
++ IN PADAPTER Adapter
++ )
++{
++ PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
++ PMGNT_INFO pMgntInfo = &Adapter->MgntInfo;
++
++ u4Byte temp, Polling, Ratio_Tx, Ratio_PRI;
++ u4Byte BT_Tx, BT_PRI;
++ u1Byte BT_State;
++ static u1Byte ServiceTypeCnt = 0;
++ u1Byte CurServiceType;
++ static u1Byte LastServiceType = BT_Idle;
++
++ if(!pMgntInfo->bMediaConnect)
++ return FALSE;
++
++ BT_State = PlatformEFIORead1Byte(Adapter, 0x4fd);
++/*
++ temp = PlatformEFIORead4Byte(Adapter, 0x488);
++ BT_Tx = (u2Byte)(((temp<<8)&0xff00)+((temp>>8)&0xff));
++ BT_PRI = (u2Byte)(((temp>>8)&0xff00)+((temp>>24)&0xff));
++
++ temp = PlatformEFIORead4Byte(Adapter, 0x48c);
++ Polling = ((temp<<8)&0xff000000) + ((temp>>8)&0x00ff0000) +
++ ((temp<<8)&0x0000ff00) + ((temp>>8)&0x000000ff);
++
++*/
++ BT_Tx = PlatformEFIORead4Byte(Adapter, 0x488);
++
++ RTPRINT(FBT, BT_TRACE, ("Ratio 0x488 =%x\n", BT_Tx));
++ BT_Tx =BT_Tx & 0x00ffffff;
++ //RTPRINT(FBT, BT_TRACE, ("Ratio BT_Tx =%x\n", BT_Tx));
++
++ BT_PRI = PlatformEFIORead4Byte(Adapter, 0x48c);
++
++ RTPRINT(FBT, BT_TRACE, ("Ratio Ratio 0x48c =%x\n", BT_PRI));
++ BT_PRI =BT_PRI & 0x00ffffff;
++ //RTPRINT(FBT, BT_TRACE, ("Ratio BT_PRI =%x\n", BT_PRI));
++
++
++ Polling = PlatformEFIORead4Byte(Adapter, 0x490);
++ //RTPRINT(FBT, BT_TRACE, ("Ratio 0x490 =%x\n", Polling));
++
++
++ if(BT_Tx==0xffffffff && BT_PRI==0xffffffff && Polling==0xffffffffff && BT_State==0xff)
++ return FALSE;
++
++ BT_State &= BIT0;
++
++ if(BT_State != pHalData->bt_coexist.BT_CUR_State)
++ {
++ pHalData->bt_coexist.BT_CUR_State = BT_State;
++
++ if(pMgntInfo->bRegBT_Sco == 3)
++ {
++ ServiceTypeCnt = 0;
++
++ pHalData->bt_coexist.BT_Service = BT_Idle;
++
++ RTPRINT(FBT, BT_TRACE, ("BT_%s\n", BT_State?"ON":"OFF"));
++
++ BT_State = BT_State |
++ ((pHalData->bt_coexist.BT_Ant_isolation==1)?0:BIT1) |BIT2;
++
++ PlatformEFIOWrite1Byte(Adapter, 0x4fd, BT_State);
++ RTPRINT(FBT, BT_TRACE, ("BT set 0x4fd to %x\n", BT_State));
++ }
++
++ return TRUE;
++ }
++ RTPRINT(FBT, BT_TRACE, ("bRegBT_Sco %d\n", pMgntInfo->bRegBT_Sco));
++
++ Ratio_Tx = BT_Tx*1000/Polling;
++ Ratio_PRI = BT_PRI*1000/Polling;
++
++ pHalData->bt_coexist.Ratio_Tx=Ratio_Tx;
++ pHalData->bt_coexist.Ratio_PRI=Ratio_PRI;
++
++ RTPRINT(FBT, BT_TRACE, ("Ratio_Tx=%d\n", Ratio_Tx));
++ RTPRINT(FBT, BT_TRACE, ("Ratio_PRI=%d\n", Ratio_PRI));
++
++
++ if(BT_State && pMgntInfo->bRegBT_Sco==3)
++ {
++ RTPRINT(FBT, BT_TRACE, ("bRegBT_Sco ==3 Follow Counter\n"));
++// if(BT_Tx==0xffff && BT_PRI==0xffff && Polling==0xffffffff)
++// {
++// ServiceTypeCnt = 0;
++// return FALSE;
++// }
++// else
++ {
++ /*
++ Ratio_Tx = BT_Tx*1000/Polling;
++ Ratio_PRI = BT_PRI*1000/Polling;
++
++ pHalData->bt_coexist.Ratio_Tx=Ratio_Tx;
++ pHalData->bt_coexist.Ratio_PRI=Ratio_PRI;
++
++ RTPRINT(FBT, BT_TRACE, ("Ratio_Tx=%d\n", Ratio_Tx));
++ RTPRINT(FBT, BT_TRACE, ("Ratio_PRI=%d\n", Ratio_PRI));
++
++ */
++ if((Ratio_Tx <= 50) && (Ratio_PRI <= 50))
++ CurServiceType = BT_Idle;
++ else if((Ratio_PRI > 150) && (Ratio_PRI < 200))
++ CurServiceType = BT_SCO;
++ else if((Ratio_Tx >= 200)&&(Ratio_PRI >= 200))
++ CurServiceType = BT_Busy;
++ else if(Ratio_Tx >= 350)
++ CurServiceType = BT_OtherBusy;
++ else
++ CurServiceType=BT_OtherAction;
++
++ }
++/* if(pHalData->bt_coexist.bStopCount)
++ {
++ ServiceTypeCnt=0;
++ pHalData->bt_coexist.bStopCount=FALSE;
++ }
++*/
++ if(CurServiceType == BT_OtherBusy)
++ {
++ ServiceTypeCnt=2;
++ LastServiceType=CurServiceType;
++ }
++ else if(CurServiceType == LastServiceType)
++ {
++ if(ServiceTypeCnt<3)
++ ServiceTypeCnt++;
++ }
++ else
++ {
++ ServiceTypeCnt = 0;
++ LastServiceType = CurServiceType;
++ }
++
++ if(ServiceTypeCnt==2)
++ {
++ pHalData->bt_coexist.BT_Service = LastServiceType;
++ BT_State = BT_State |
++ ((pHalData->bt_coexist.BT_Ant_isolation==1)?0:BIT1) |
++ ((pHalData->bt_coexist.BT_Service==BT_SCO)?0:BIT2);
++
++ if(pHalData->bt_coexist.BT_Service==BT_Busy)
++ BT_State&= ~(BIT2);
++
++ if(pHalData->bt_coexist.BT_Service==BT_SCO)
++ {
++ RTPRINT(FBT, BT_TRACE, ("BT TYPE Set to ==> BT_SCO\n"));
++ }
++ else if(pHalData->bt_coexist.BT_Service==BT_Idle)
++ {
++ RTPRINT(FBT, BT_TRACE, ("BT TYPE Set to ==> BT_Idle\n"));
++ }
++ else if(pHalData->bt_coexist.BT_Service==BT_OtherAction)
++ {
++ RTPRINT(FBT, BT_TRACE, ("BT TYPE Set to ==> BT_OtherAction\n"));
++ }
++ else if(pHalData->bt_coexist.BT_Service==BT_Busy)
++ {
++ RTPRINT(FBT, BT_TRACE, ("BT TYPE Set to ==> BT_Busy\n"));
++ }
++ else
++ {
++ RTPRINT(FBT, BT_TRACE, ("BT TYPE Set to ==> BT_OtherBusy\n"));
++ }
++
++ //Add interrupt migration when bt is not in idel state (no traffic).
++ //suggestion by Victor.
++ if(pHalData->bt_coexist.BT_Service!=BT_Idle)
++ {
++
++ PlatformEFIOWrite2Byte(Adapter, 0x504, 0x0ccc);
++ PlatformEFIOWrite1Byte(Adapter, 0x506, 0x54);
++ PlatformEFIOWrite1Byte(Adapter, 0x507, 0x54);
++
++ }
++ else
++ {
++ PlatformEFIOWrite1Byte(Adapter, 0x506, 0x00);
++ PlatformEFIOWrite1Byte(Adapter, 0x507, 0x00);
++ }
++
++ PlatformEFIOWrite1Byte(Adapter, 0x4fd, BT_State);
++ RTPRINT(FBT, BT_TRACE, ("BT_SCO set 0x4fd to %x\n", BT_State));
++ return TRUE;
++ }
++ }
++
++ return FALSE;
++
++}
++
++BOOLEAN
++BT_WifiConnectChange(
++ IN PADAPTER Adapter
++ )
++{
++ PMGNT_INFO pMgntInfo = &Adapter->MgntInfo;
++ static BOOLEAN bMediaConnect = FALSE;
++
++ if(!pMgntInfo->bMediaConnect || MgntRoamingInProgress(pMgntInfo))
++ {
++ bMediaConnect = FALSE;
++ }
++ else
++ {
++ if(!bMediaConnect)
++ {
++ bMediaConnect = TRUE;
++ return TRUE;
++ }
++ bMediaConnect = TRUE;
++ }
++
++ return FALSE;
++}
++
++BOOLEAN
++BT_RSSIChangeWithAMPDU(
++ IN PADAPTER Adapter
++ )
++{
++ PMGNT_INFO pMgntInfo = &Adapter->MgntInfo;
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++
++ if(!Adapter->pNdisCommon->bRegBT_Ampdu || !Adapter->pNdisCommon->bRegAcceptAddbaReq)
++ return FALSE;
++
++ RTPRINT(FBT, BT_TRACE, ("RSSI is %d\n",pHalData->UndecoratedSmoothedPWDB));
++
++ if((pHalData->UndecoratedSmoothedPWDB<=32) && pMgntInfo->pHTInfo->bAcceptAddbaReq)
++ {
++ RTPRINT(FBT, BT_TRACE, ("BT_Disallow AMPDU RSSI <=32 Need change\n"));
++ return TRUE;
++
++ }
++ else if((pHalData->UndecoratedSmoothedPWDB>=40) && !pMgntInfo->pHTInfo->bAcceptAddbaReq )
++ {
++ RTPRINT(FBT, BT_TRACE, ("BT_Allow AMPDU RSSI >=40, Need change\n"));
++ return TRUE;
++ }
++ else
++ return FALSE;
++
++}
++
++
++VOID
++dm_BTCoexist(
++ IN PADAPTER Adapter
++ )
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ PMGNT_INFO pMgntInfo = &Adapter->MgntInfo;
++ static u1Byte LastTxPowerLvl = 0xff;
++ PRX_TS_RECORD pRxTs = NULL;
++
++ BOOLEAN bWifiConnectChange, bBtStateChange,bRSSIChangeWithAMPDU;
++
++ if( (pHalData->bt_coexist.BluetoothCoexist) &&
++ (pHalData->bt_coexist.BT_CoexistType == BT_CSR_BC4) &&
++ (!ACTING_AS_AP(Adapter)) )
++ {
++ bWifiConnectChange = BT_WifiConnectChange(Adapter);
++ bBtStateChange = BT_BTStateChange(Adapter);
++ bRSSIChangeWithAMPDU = BT_RSSIChangeWithAMPDU(Adapter);
++ RTPRINT(FBT, BT_TRACE, ("bWifiConnectChange %d, bBtStateChange %d,LastTxPowerLvl %x, DynamicTxHighPowerLvl %x\n",
++ bWifiConnectChange,bBtStateChange,LastTxPowerLvl,pHalData->DynamicTxHighPowerLvl));
++ if( bWifiConnectChange ||bBtStateChange ||
++ (LastTxPowerLvl != pHalData->DynamicTxHighPowerLvl) ||bRSSIChangeWithAMPDU)
++ {
++ LastTxPowerLvl = pHalData->DynamicTxHighPowerLvl;
++
++ if(pHalData->bt_coexist.BT_CUR_State)
++ {
++ // Do not allow receiving A-MPDU aggregation.
++ if((pHalData->bt_coexist.BT_Service==BT_SCO) || (pHalData->bt_coexist.BT_Service==BT_Busy))
++ {
++ if(pHalData->UndecoratedSmoothedPWDB<=32)
++ {
++ if(Adapter->pNdisCommon->bRegBT_Ampdu && Adapter->pNdisCommon->bRegAcceptAddbaReq)
++ {
++ RTPRINT(FBT, BT_TRACE, ("BT_Disallow AMPDU RSSI <=32\n"));
++ pMgntInfo->pHTInfo->bAcceptAddbaReq = FALSE;
++ if(GetTs(Adapter, (PTS_COMMON_INFO*)(&pRxTs), pMgntInfo->Bssid, 0, RX_DIR, FALSE))
++ TsInitDelBA(Adapter, (PTS_COMMON_INFO)pRxTs, RX_DIR);
++ }
++ }
++ else if(pHalData->UndecoratedSmoothedPWDB>=40)
++ {
++ if(Adapter->pNdisCommon->bRegBT_Ampdu && Adapter->pNdisCommon->bRegAcceptAddbaReq)
++ {
++ RTPRINT(FBT, BT_TRACE, ("BT_Allow AMPDU RSSI >=40\n"));
++ pMgntInfo->pHTInfo->bAcceptAddbaReq = TRUE;
++ }
++ }
++ }
++ else
++ {
++ if(Adapter->pNdisCommon->bRegBT_Ampdu && Adapter->pNdisCommon->bRegAcceptAddbaReq)
++ {
++ RTPRINT(FBT, BT_TRACE, ("BT_Allow AMPDU BT not in SCO or BUSY\n"));
++ pMgntInfo->pHTInfo->bAcceptAddbaReq = TRUE;
++ }
++ }
++
++ if(pHalData->bt_coexist.BT_Ant_isolation)
++ {
++ RTPRINT(FBT, BT_TRACE, ("BT_IsolationLow\n"));
++ RTPRINT(FBT, BT_TRACE, ("BT_Update Rate table\n"));
++ Adapter->HalFunc.UpdateHalRATRTableHandler(
++ Adapter,
++ &pMgntInfo->dot11OperationalRateSet,
++ pMgntInfo->dot11HTOperationalRateSet,NULL);
++
++ if(pHalData->bt_coexist.BT_Service==BT_SCO)
++ {
++
++ RTPRINT(FBT, BT_TRACE, ("BT_Turn OFF Coexist with SCO \n"));
++ PlatformEFIOWrite1Byte(Adapter, REG_GPIO_MUXCFG, 0x14);
++ }
++ else if(pHalData->DynamicTxHighPowerLvl == TxHighPwrLevel_Normal)
++ {
++ RTPRINT(FBT, BT_TRACE, ("BT_Turn ON Coexist\n"));
++ PlatformEFIOWrite1Byte(Adapter, REG_GPIO_MUXCFG, 0xb4);
++ }
++ else
++ {
++ RTPRINT(FBT, BT_TRACE, ("BT_Turn OFF Coexist\n"));
++ PlatformEFIOWrite1Byte(Adapter, REG_GPIO_MUXCFG, 0x14);
++ }
++ }
++ else
++ {
++ RTPRINT(FBT, BT_TRACE, ("BT_IsolationHigh\n"));
++ // Do nothing.
++ }
++ }
++ else
++ {
++ if(Adapter->pNdisCommon->bRegBT_Ampdu && Adapter->pNdisCommon->bRegAcceptAddbaReq)
++ {
++ RTPRINT(FBT, BT_TRACE, ("BT_Allow AMPDU bt is off\n"));
++ pMgntInfo->pHTInfo->bAcceptAddbaReq = TRUE;
++ }
++
++ RTPRINT(FBT, BT_TRACE, ("BT_Turn OFF Coexist bt is off \n"));
++ PlatformEFIOWrite1Byte(Adapter, REG_GPIO_MUXCFG, 0x14);
++
++ RTPRINT(FBT, BT_TRACE, ("BT_Update Rate table\n"));
++ Adapter->HalFunc.UpdateHalRATRTableHandler(
++ Adapter,
++ &pMgntInfo->dot11OperationalRateSet,
++ pMgntInfo->dot11HTOperationalRateSet,NULL);
++ }
++ }
++ }
++}
++#endif
++
++
++/*-----------------------------------------------------------------------------
++ * Function: dm_CheckRfCtrlGPIO()
++ *
++ * Overview: Copy 8187B template for 9xseries.
++ *
++ * Input: NONE
++ *
++ * Output: NONE
++ *
++ * Return: NONE
++ *
++ * Revised History:
++ * When Who Remark
++ * 01/10/2008 MHC Create Version 0.
++ *
++ *---------------------------------------------------------------------------*/
++static VOID
++dm_CheckRfCtrlGPIO(
++ IN PADAPTER Adapter
++ )
++{
++#if 0
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++#if defined (CONFIG_USB_HCI) || defined (CONFIG_SDIO_HCI)
++ #ifdef CONFIG_USB_HCI
++ // 2010/08/12 MH Add for CU selective suspend.
++ PRT_USB_DEVICE pDevice = GET_RT_USB_DEVICE(Adapter);
++ #else
++ PRT_SDIO_DEVICE pDevice = GET_RT_SDIO_DEVICE(Adapter);
++ #endif
++#endif
++
++ if(!Adapter->MgntInfo.PowerSaveControl.bGpioRfSw)
++ return;
++
++ RTPRINT(FPWR, PWRHW, ("dm_CheckRfCtrlGPIO \n"));
++
++#if defined (CONFIG_USB_HCI) || defined (CONFIG_SDIO_HCI)
++ // Walk around for DTM test, we will not enable HW - radio on/off because r/w
++ // page 1 register before Lextra bus is enabled cause system fails when resuming
++ // from S4. 20080218, Emily
++ if(Adapter->bInHctTest)
++ return;
++
++//#if ((HAL_CODE_BASE == RTL8192_S) )
++ //Adapter->HalFunc.GPIOChangeRFHandler(Adapter, GPIORF_POLLING);
++//#else
++ // 2010/07/27 MH Only Minicard and support selective suspend, we can not turn off all MAC power to
++ // stop 8051. For dongle and minicard, we both support selective suspend mode.
++ //if(pDevice->RegUsbSS && Adapter->HalFunc.GetInterfaceSelectionHandler(Adapter) == INTF_SEL2_MINICARD)
++
++ //
++ // 2010/08/12 MH We support severl power consumption combination as below.
++ //
++ // Power consumption combination
++ // SS Enable: (LPS disable + IPS + SW/HW radio off)
++ // 1. Dongle + PDN (support HW radio off)
++ // 2. Dongle + Normal (No HW radio off)
++ // 3. MiniCard + PDN (support HW radio off)
++ // 4. MiniCard + Normal (support HW radio off)
++ //
++ // SS Disable: (LPS + IPS + SW/HW radio off)
++ // 1. Dongle + PDN (support HW radio off)
++ // 2. Dongle + Normal (No HW radio off)
++ // 3. MiniCard + PDN (support HW radio off)
++ // 4. MiniCard + Normal (support HW radio off)
++ //
++ // For Power down module detection. We need to read power register no matter
++ // dongle or minicard, we will add the item is the detection method.
++ //
++ //
++ //vivi add du case
++ if ((IS_HARDWARE_TYPE_8192CU(Adapter)||IS_HARDWARE_TYPE_8192DU(Adapter))
++ && pDevice->RegUsbSS)
++ {
++ RT_TRACE(COMP_RF, DBG_LOUD, ("USB SS Enabled\n"));
++ if (SUPPORT_HW_RADIO_DETECT(Adapter))
++ { // Support HW radio detection
++ RT_TRACE(COMP_RF, DBG_LOUD, ("USB Card Type 2/3/4 support GPIO Detect\n"));
++ GpioDetectTimerStart(Adapter);
++ }
++ else
++ { // Dongle does not support HW radio detection.?? In the fufure??
++ RT_TRACE(COMP_RF, DBG_LOUD, ("USB DONGLE Non-GPIO-Detect\n"));
++ }
++ }
++ else if (IS_HARDWARE_TYPE_8192CU(Adapter) ||
++ IS_HARDWARE_TYPE_8723AU(Adapter)||
++ IS_HARDWARE_TYPE_8192DU(Adapter) ||
++ IS_HARDWARE_TYPE_8723AS(Adapter))
++ { // Not support Selective suspend
++ RT_TRACE(COMP_RF, DBG_LOUD, ("USB SS Disable\n"));
++ if (SUPPORT_HW_RADIO_DETECT(Adapter))
++ {
++ RT_TRACE(COMP_RF, DBG_LOUD, ("USB Card Type 2/3/4 support GPIO Detect\n"));
++ PlatformScheduleWorkItem( &(pHalData->GPIOChangeRFWorkItem) );
++ }
++ else
++ {
++ RT_TRACE(COMP_RF, DBG_LOUD, ("USB DONGLE Non-GPIO-Detect\n"));
++ }
++ }
++ else
++ { // CE only support noemal HW radio detection now. Support timers GPIO detection in SE/CU.
++ PlatformScheduleWorkItem( &(pHalData->GPIOChangeRFWorkItem) );
++ }
++//#endif
++#else if defined CONFIG_PCI_HCI
++ if(Adapter->bInHctTest)
++ return;
++
++ // CE only support noemal HW radio detection now. We support timers GPIO detection in SE.
++ PlatformScheduleWorkItem( &(pHalData->GPIOChangeRFWorkItem) );
++#endif
++#endif
++} /* dm_CheckRfCtrlGPIO */
++
++static VOID
++dm_InitRateAdaptiveMask(
++ IN PADAPTER Adapter
++ )
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ struct dm_priv *pdmpriv = &pHalData->dmpriv;
++ PRATE_ADAPTIVE pRA = (PRATE_ADAPTIVE)&pdmpriv->RateAdaptive;
++
++ pRA->RATRState = DM_RATR_STA_INIT;
++ pRA->PreRATRState = DM_RATR_STA_INIT;
++
++ if (pdmpriv->DM_Type == DM_Type_ByDriver)
++ pdmpriv->bUseRAMask = _TRUE;
++ else
++ pdmpriv->bUseRAMask = _FALSE;
++}
++
++/*-----------------------------------------------------------------------------
++ * Function: dm_RefreshRateAdaptiveMask()
++ *
++ * Overview: Update rate table mask according to rssi
++ *
++ * Input: NONE
++ *
++ * Output: NONE
++ *
++ * Return: NONE
++ *
++ * Revised History:
++ * When Who Remark
++ * 05/27/2009 hpfan Create Version 0.
++ *
++ *---------------------------------------------------------------------------*/
++static VOID
++dm_RefreshRateAdaptiveMask( IN PADAPTER pAdapter)
++{
++#if 0
++ PADAPTER pTargetAdapter;
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
++ PMGNT_INFO pMgntInfo = &(ADJUST_TO_ADAPTIVE_ADAPTER(pAdapter, TRUE)->MgntInfo);
++ PRATE_ADAPTIVE pRA = (PRATE_ADAPTIVE)&pMgntInfo->RateAdaptive;
++ u4Byte LowRSSIThreshForRA = 0, HighRSSIThreshForRA = 0;
++
++ if(pAdapter->bDriverStopped)
++ {
++ RT_TRACE(COMP_RATR, DBG_TRACE, ("<---- dm_RefreshRateAdaptiveMask(): driver is going to unload\n"));
++ return;
++ }
++
++ if(!pMgntInfo->bUseRAMask)
++ {
++ RT_TRACE(COMP_RATR, DBG_LOUD, ("<---- dm_RefreshRateAdaptiveMask(): driver does not control rate adaptive mask\n"));
++ return;
++ }
++
++ // if default port is connected, update RA table for default port (infrastructure mode only)
++ if(pAdapter->MgntInfo.mAssoc && (!ACTING_AS_AP(pAdapter)))
++ {
++
++ // decide rastate according to rssi
++ switch (pRA->PreRATRState)
++ {
++ case DM_RATR_STA_HIGH:
++ HighRSSIThreshForRA = 50;
++ LowRSSIThreshForRA = 20;
++ break;
++
++ case DM_RATR_STA_MIDDLE:
++ HighRSSIThreshForRA = 55;
++ LowRSSIThreshForRA = 20;
++ break;
++
++ case DM_RATR_STA_LOW:
++ HighRSSIThreshForRA = 50;
++ LowRSSIThreshForRA = 25;
++ break;
++
++ default:
++ HighRSSIThreshForRA = 50;
++ LowRSSIThreshForRA = 20;
++ break;
++ }
++
++ if(pHalData->UndecoratedSmoothedPWDB > (s4Byte)HighRSSIThreshForRA)
++ pRA->RATRState = DM_RATR_STA_HIGH;
++ else if(pHalData->UndecoratedSmoothedPWDB > (s4Byte)LowRSSIThreshForRA)
++ pRA->RATRState = DM_RATR_STA_MIDDLE;
++ else
++ pRA->RATRState = DM_RATR_STA_LOW;
++
++ if(pRA->PreRATRState != pRA->RATRState)
++ {
++ RT_PRINT_ADDR(COMP_RATR, DBG_LOUD, ("Target AP addr : "), pMgntInfo->Bssid);
++ RT_TRACE(COMP_RATR, DBG_LOUD, ("RSSI = %d\n", pHalData->UndecoratedSmoothedPWDB));
++ RT_TRACE(COMP_RATR, DBG_LOUD, ("RSSI_LEVEL = %d\n", pRA->RATRState));
++ RT_TRACE(COMP_RATR, DBG_LOUD, ("PreState = %d, CurState = %d\n", pRA->PreRATRState, pRA->RATRState));
++ pAdapter->HalFunc.UpdateHalRAMaskHandler(
++ pAdapter,
++ FALSE,
++ 0,
++ NULL,
++ NULL,
++ pRA->RATRState);
++ pRA->PreRATRState = pRA->RATRState;
++ }
++ }
++
++ //
++ // The following part configure AP/VWifi/IBSS rate adaptive mask.
++ //
++ if(ACTING_AS_AP(pAdapter) || ACTING_AS_IBSS(pAdapter))
++ {
++ pTargetAdapter = pAdapter;
++ }
++ else
++ {
++ pTargetAdapter = ADJUST_TO_ADAPTIVE_ADAPTER(pAdapter, FALSE);
++ if(!ACTING_AS_AP(pTargetAdapter))
++ pTargetAdapter = NULL;
++ }
++
++ // if extension port (softap) is started, updaet RA table for more than one clients associate
++ if(pTargetAdapter != NULL)
++ {
++ int i;
++ PRT_WLAN_STA pEntry;
++ PRATE_ADAPTIVE pEntryRA;
++
++ for(i = 0; i < ASSOCIATE_ENTRY_NUM; i++)
++ {
++ if( pTargetAdapter->MgntInfo.AsocEntry[i].bUsed && pTargetAdapter->MgntInfo.AsocEntry[i].bAssociated)
++ {
++ pEntry = pTargetAdapter->MgntInfo.AsocEntry+i;
++ pEntryRA = &pEntry->RateAdaptive;
++
++ switch (pEntryRA->PreRATRState)
++ {
++ case DM_RATR_STA_HIGH:
++ {
++ HighRSSIThreshForRA = 50;
++ LowRSSIThreshForRA = 20;
++ }
++ break;
++
++ case DM_RATR_STA_MIDDLE:
++ {
++ HighRSSIThreshForRA = 55;
++ LowRSSIThreshForRA = 20;
++ }
++ break;
++
++ case DM_RATR_STA_LOW:
++ {
++ HighRSSIThreshForRA = 50;
++ LowRSSIThreshForRA = 25;
++ }
++ break;
++
++ default:
++ {
++ HighRSSIThreshForRA = 50;
++ LowRSSIThreshForRA = 20;
++ }
++ }
++
++ if(pEntry->rssi_stat.UndecoratedSmoothedPWDB > (s4Byte)HighRSSIThreshForRA)
++ pEntryRA->RATRState = DM_RATR_STA_HIGH;
++ else if(pEntry->rssi_stat.UndecoratedSmoothedPWDB > (s4Byte)LowRSSIThreshForRA)
++ pEntryRA->RATRState = DM_RATR_STA_MIDDLE;
++ else
++ pEntryRA->RATRState = DM_RATR_STA_LOW;
++
++ if(pEntryRA->PreRATRState != pEntryRA->RATRState)
++ {
++ RT_PRINT_ADDR(COMP_RATR, DBG_LOUD, ("AsocEntry addr : "), pEntry->MacAddr);
++ RT_TRACE(COMP_RATR, DBG_LOUD, ("RSSI = %d\n", pEntry->rssi_stat.UndecoratedSmoothedPWDB));
++ RT_TRACE(COMP_RATR, DBG_LOUD, ("RSSI_LEVEL = %d\n", pEntryRA->RATRState));
++ RT_TRACE(COMP_RATR, DBG_LOUD, ("PreState = %d, CurState = %d\n", pEntryRA->PreRATRState, pEntryRA->RATRState));
++ pAdapter->HalFunc.UpdateHalRAMaskHandler(
++ pTargetAdapter,
++ FALSE,
++ pEntry->AID+1,
++ pEntry->MacAddr,
++ pEntry,
++ pEntryRA->RATRState);
++ pEntryRA->PreRATRState = pEntryRA->RATRState;
++ }
++
++ }
++ }
++ }
++#endif
++}
++
++static VOID
++dm_CheckProtection(
++ IN PADAPTER Adapter
++ )
++{
++#if 0
++ PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo);
++ u1Byte CurRate, RateThreshold;
++
++ if(pMgntInfo->pHTInfo->bCurBW40MHz)
++ RateThreshold = MGN_MCS1;
++ else
++ RateThreshold = MGN_MCS3;
++
++ if(Adapter->TxStats.CurrentInitTxRate <= RateThreshold)
++ {
++ pMgntInfo->bDmDisableProtect = TRUE;
++ DbgPrint("Forced disable protect: %x\n", Adapter->TxStats.CurrentInitTxRate);
++ }
++ else
++ {
++ pMgntInfo->bDmDisableProtect = FALSE;
++ DbgPrint("Enable protect: %x\n", Adapter->TxStats.CurrentInitTxRate);
++ }
++#endif
++}
++
++static VOID
++dm_CheckStatistics(
++ IN PADAPTER Adapter
++ )
++{
++#if 0
++ if(!Adapter->MgntInfo.bMediaConnect)
++ return;
++
++ //2008.12.10 tynli Add for getting Current_Tx_Rate_Reg flexibly.
++ rtw_hal_get_hwreg( Adapter, HW_VAR_INIT_TX_RATE, (pu1Byte)(&Adapter->TxStats.CurrentInitTxRate) );
++
++ // Calculate current Tx Rate(Successful transmited!!)
++
++ // Calculate current Rx Rate(Successful received!!)
++
++ //for tx tx retry count
++ rtw_hal_get_hwreg( Adapter, HW_VAR_RETRY_COUNT, (pu1Byte)(&Adapter->TxStats.NumTxRetryCount) );
++#endif
++}
++
++static void dm_CheckPbcGPIO(_adapter *padapter)
++{
++ u8 tmp1byte;
++ u8 bPbcPressed = _FALSE;
++ int i=0;
++
++ if(!padapter->registrypriv.hw_wps_pbc)
++ return;
++
++ do
++ {
++ i++;
++#ifdef CONFIG_USB_HCI
++ tmp1byte = rtw_read8(padapter, GPIO_IO_SEL);
++ tmp1byte |= (HAL_8192C_HW_GPIO_WPS_BIT);
++ rtw_write8(padapter, GPIO_IO_SEL, tmp1byte); //enable GPIO[2] as output mode
++
++ tmp1byte &= ~(HAL_8192C_HW_GPIO_WPS_BIT);
++ rtw_write8(padapter, GPIO_IN, tmp1byte); //reset the floating voltage level
++
++ tmp1byte = rtw_read8(padapter, GPIO_IO_SEL);
++ tmp1byte &= ~(HAL_8192C_HW_GPIO_WPS_BIT);
++ rtw_write8(padapter, GPIO_IO_SEL, tmp1byte); //enable GPIO[2] as input mode
++
++ tmp1byte =rtw_read8(padapter, GPIO_IN);
++
++ if (tmp1byte == 0xff)
++ {
++ bPbcPressed = _FALSE;
++ break ;
++ }
++
++ if (tmp1byte&HAL_8192C_HW_GPIO_WPS_BIT)
++ {
++ bPbcPressed = _TRUE;
++
++ if(i<=3)
++ rtw_msleep_os(50);
++ }
++#else
++ tmp1byte = rtw_read8(padapter, GPIO_IN);
++ //RT_TRACE(COMP_IO, DBG_TRACE, ("dm_CheckPbcGPIO - %x\n", tmp1byte));
++
++ if (tmp1byte == 0xff || padapter->init_adpt_in_progress)
++ {
++ bPbcPressed = _FALSE;
++ break ;
++ }
++
++ if((tmp1byte&HAL_8192C_HW_GPIO_WPS_BIT)==0)
++ {
++ bPbcPressed = _TRUE;
++
++ if(i<=3)
++ rtw_msleep_os(50);
++ }
++#endif
++
++ }while(i<=3 && bPbcPressed == _TRUE);
++
++ if( _TRUE == bPbcPressed)
++ {
++ // Here we only set bPbcPressed to true
++ // After trigger PBC, the variable will be set to false
++ DBG_8192C("CheckPbcGPIO - PBC is pressed, try_cnt=%d\n", i-1);
++
++#ifdef RTK_DMP_PLATFORM
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,12))
++ kobject_uevent(&padapter->pnetdev->dev.kobj, KOBJ_NET_PBC);
++#else
++ kobject_hotplug(&padapter->pnetdev->class_dev.kobj, KOBJ_NET_PBC);
++#endif
++#else
++
++ if ( padapter->pid[0] == 0 )
++ { // 0 is the default value and it means the application monitors the HW PBC doesn't privde its pid to driver.
++ return;
++ }
++
++#ifdef PLATFORM_LINUX
++ rtw_signal_process(padapter->pid[0], SIGUSR1);
++#endif
++#endif
++ }
++}
++
++#ifdef CONFIG_PCI_HCI
++//
++// Description:
++// Perform interrupt migration dynamically to reduce CPU utilization.
++//
++// Assumption:
++// 1. Do not enable migration under WIFI test.
++//
++// Created by Roger, 2010.03.05.
++//
++VOID
++dm_InterruptMigration(
++ IN PADAPTER Adapter
++ )
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv);
++ BOOLEAN bCurrentIntMt, bCurrentACIntDisable;
++ BOOLEAN IntMtToSet = _FALSE;
++ BOOLEAN ACIntToSet = _FALSE;
++
++
++ // Retrieve current interrupt migration and Tx four ACs IMR settings first.
++ bCurrentIntMt = pHalData->bInterruptMigration;
++ bCurrentACIntDisable = pHalData->bDisableTxInt;
++
++ //
++ // <Roger_Notes> Currently we use busy traffic for reference instead of RxIntOK counts to prevent non-linear Rx statistics
++ // when interrupt migration is set before. 2010.03.05.
++ //
++ if(!Adapter->registrypriv.wifi_spec &&
++ (check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE) &&
++ pmlmepriv->LinkDetectInfo.bHigherBusyTraffic)
++ {
++ IntMtToSet = _TRUE;
++
++ // To check whether we should disable Tx interrupt or not.
++ if(pmlmepriv->LinkDetectInfo.bHigherBusyRxTraffic )
++ ACIntToSet = _TRUE;
++ }
++
++ //Update current settings.
++ if( bCurrentIntMt != IntMtToSet ){
++ DBG_8192C("%s(): Update interrrupt migration(%d)\n",__FUNCTION__,IntMtToSet);
++ if(IntMtToSet)
++ {
++ //
++ // <Roger_Notes> Set interrrupt migration timer and corresponging Tx/Rx counter.
++ // timer 25ns*0xfa0=100us for 0xf packets.
++ // 2010.03.05.
++ //
++ rtw_write32(Adapter, REG_INT_MIG, 0xff000fa0);// 0x306:Rx, 0x307:Tx
++ pHalData->bInterruptMigration = IntMtToSet;
++ }
++ else
++ {
++ // Reset all interrupt migration settings.
++ rtw_write32(Adapter, REG_INT_MIG, 0);
++ pHalData->bInterruptMigration = IntMtToSet;
++ }
++ }
++
++ /*if( bCurrentACIntDisable != ACIntToSet ){
++ DBG_8192C("%s(): Update AC interrrupt(%d)\n",__FUNCTION__,ACIntToSet);
++ if(ACIntToSet) // Disable four ACs interrupts.
++ {
++ //
++ // <Roger_Notes> Disable VO, VI, BE and BK four AC interrupts to gain more efficient CPU utilization.
++ // When extremely highly Rx OK occurs, we will disable Tx interrupts.
++ // 2010.03.05.
++ //
++ UpdateInterruptMask8192CE( Adapter, 0, RT_AC_INT_MASKS );
++ pHalData->bDisableTxInt = ACIntToSet;
++ }
++ else// Enable four ACs interrupts.
++ {
++ UpdateInterruptMask8192CE( Adapter, RT_AC_INT_MASKS, 0 );
++ pHalData->bDisableTxInt = ACIntToSet;
++ }
++ }*/
++
++}
++
++#endif
++
++//
++// Initialize GPIO setting registers
++//
++static void
++dm_InitGPIOSetting(
++ IN PADAPTER Adapter
++ )
++{
++ PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
++
++ u8 tmp1byte;
++
++ tmp1byte = rtw_read8(Adapter, REG_GPIO_MUXCFG);
++ tmp1byte &= (GPIOSEL_GPIO | ~GPIOSEL_ENBT);
++
++#ifdef CONFIG_BT_COEXIST
++ // UMB-B cut bug. We need to support the modification.
++ if (IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID) &&
++ pHalData->bt_coexist.BT_Coexist)
++ {
++ tmp1byte |= (BIT5);
++ }
++#endif
++ rtw_write8(Adapter, REG_GPIO_MUXCFG, tmp1byte);
++
++}
++
++static void update_EDCA_param(_adapter *padapter)
++{
++ u32 trafficIndex;
++ u32 edca_param;
++ u64 cur_tx_bytes = 0;
++ u64 cur_rx_bytes = 0;
++ PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
++ struct dm_priv *pdmpriv = &pHalData->dmpriv;
++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
++ struct recv_priv *precvpriv = &(padapter->recvpriv);
++ struct registry_priv *pregpriv = &padapter->registrypriv;
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++
++#ifdef CONFIG_BT_COEXIST
++ struct btcoexist_priv *pbtpriv = &(pHalData->bt_coexist);
++ u8 bbtchange = _FALSE;
++#endif
++
++
++ //DBG_871X("%s\n", __FUNCTION__);
++
++ //associated AP
++ if ((pregpriv->wifi_spec == 1) || (pmlmeinfo->HT_enable == 0))
++ {
++ return;
++ }
++
++ if (pmlmeinfo->assoc_AP_vendor >= maxAP)
++ {
++ return;
++ }
++
++ cur_tx_bytes = pxmitpriv->tx_bytes - pxmitpriv->last_tx_bytes;
++ cur_rx_bytes = precvpriv->rx_bytes - precvpriv->last_rx_bytes;
++
++ //traffic, TX or RX
++ if((pmlmeinfo->assoc_AP_vendor == ralinkAP)||(pmlmeinfo->assoc_AP_vendor == atherosAP))
++ {
++ if (cur_tx_bytes > (cur_rx_bytes << 2))
++ { // Uplink TP is present.
++ trafficIndex = UP_LINK;
++ }
++ else
++ { // Balance TP is present.
++ trafficIndex = DOWN_LINK;
++ }
++ }
++ else
++ {
++ if (cur_rx_bytes > (cur_tx_bytes << 2))
++ { // Downlink TP is present.
++ trafficIndex = DOWN_LINK;
++ }
++ else
++ { // Balance TP is present.
++ trafficIndex = UP_LINK;
++ }
++ }
++
++#ifdef CONFIG_BT_COEXIST
++ if(pbtpriv->BT_Coexist)
++ {
++ if( (pbtpriv->BT_EDCA[UP_LINK]!=0) || (pbtpriv->BT_EDCA[DOWN_LINK]!=0))
++ {
++ bbtchange = _TRUE;
++ }
++ }
++#endif
++
++ if (pdmpriv->prv_traffic_idx != trafficIndex)
++ {
++#if 0
++#ifdef CONFIG_BT_COEXIST
++ if(_TRUE == bbtchange)
++ rtw_write32(padapter, REG_EDCA_BE_PARAM, pbtpriv->BT_EDCA[trafficIndex]);
++ else
++#endif
++ //adjust EDCA parameter for BE queue
++ //fire_write_MAC_cmd(padapter, EDCA_BE_PARAM, EDCAParam[pmlmeinfo->assoc_AP_vendor][trafficIndex]);
++ rtw_write32(padapter, REG_EDCA_BE_PARAM, EDCAParam[pmlmeinfo->assoc_AP_vendor][trafficIndex]);
++
++#else
++ if((pmlmeinfo->assoc_AP_vendor == ciscoAP) && (pmlmeext->cur_wireless_mode & WIRELESS_11_24N))
++ {
++ edca_param = EDCAParam[pmlmeinfo->assoc_AP_vendor][trafficIndex];
++ }
++ else if((pmlmeinfo->assoc_AP_vendor == airgocapAP) &&
++ ((pmlmeext->cur_wireless_mode == WIRELESS_11G) ||(pmlmeext->cur_wireless_mode == WIRELESS_11BG)))
++ {
++ edca_param = EDCAParam[pmlmeinfo->assoc_AP_vendor][trafficIndex];
++ }
++ else
++ {
++ edca_param = EDCAParam[unknownAP][trafficIndex];
++ }
++
++#ifdef CONFIG_BT_COEXIST
++ if(_TRUE == bbtchange)
++ edca_param = pbtpriv->BT_EDCA[trafficIndex];
++#endif
++
++ rtw_write32(padapter, REG_EDCA_BE_PARAM, edca_param);
++#endif
++ pdmpriv->prv_traffic_idx = trafficIndex;
++ }
++
++//exit_update_EDCA_param:
++
++ pxmitpriv->last_tx_bytes = pxmitpriv->tx_bytes;
++ precvpriv->last_rx_bytes = precvpriv->rx_bytes;
++
++ return;
++}
++
++static void dm_InitDynamicBBPowerSaving(
++ IN PADAPTER Adapter
++ )
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ struct dm_priv *pdmpriv = &pHalData->dmpriv;
++ PS_T *pPSTable = &pdmpriv->DM_PSTable;
++
++ pPSTable->PreCCAState = CCA_MAX;
++ pPSTable->CurCCAState = CCA_MAX;
++ pPSTable->PreRFState = RF_MAX;
++ pPSTable->CurRFState = RF_MAX;
++ pPSTable->Rssi_val_min = 0;
++}
++
++static void dm_1R_CCA(
++ IN PADAPTER pAdapter)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
++ struct dm_priv *pdmpriv = &pHalData->dmpriv;
++ PS_T *pPSTable = &pdmpriv->DM_PSTable;
++
++ if(pPSTable->Rssi_val_min != 0)
++ {
++ if(pPSTable->PreCCAState == CCA_2R)
++ {
++ if(pPSTable->Rssi_val_min >= 35)
++ pPSTable->CurCCAState = CCA_1R;
++ else
++ pPSTable->CurCCAState = CCA_2R;
++ }
++ else{
++ if(pPSTable->Rssi_val_min <= 30)
++ pPSTable->CurCCAState = CCA_2R;
++ else
++ pPSTable->CurCCAState = CCA_1R;
++ }
++ }
++ else
++ pPSTable->CurCCAState=CCA_MAX;
++
++ if(pPSTable->PreCCAState != pPSTable->CurCCAState)
++ {
++ if(pPSTable->CurCCAState == CCA_1R)
++ {
++ if(pHalData->rf_type == RF_2T2R)
++ {
++ PHY_SetBBReg(pAdapter, rOFDM0_TRxPathEnable , bMaskByte0, 0x13);
++ PHY_SetBBReg(pAdapter, 0xe70, bMaskByte3, 0x20);
++ }
++ else
++ {
++ PHY_SetBBReg(pAdapter, rOFDM0_TRxPathEnable , bMaskByte0, 0x23);
++ PHY_SetBBReg(pAdapter, 0xe70, 0x7fc00000, 0x10c); // Set RegE70[30:22] = 9b'100001100
++ }
++ }
++ else
++ {
++ PHY_SetBBReg(pAdapter, rOFDM0_TRxPathEnable, bMaskByte0, 0x33);
++ PHY_SetBBReg(pAdapter,0xe70, bMaskByte3, 0x63);
++ }
++ pPSTable->PreCCAState = pPSTable->CurCCAState;
++ }
++ //DBG_8192C("dm_1R_CCA(): CCAStage=%x\n", pPSTable->CurCCAState);
++}
++
++void
++rtl8192c_dm_RF_Saving(
++ IN PADAPTER pAdapter,
++ IN u8 bForceInNormal
++ )
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
++ struct dm_priv *pdmpriv = &pHalData->dmpriv;
++ PS_T *pPSTable = &pdmpriv->DM_PSTable;
++
++ if(pdmpriv->initialize == 0){
++ pdmpriv->rf_saving_Reg874 = (PHY_QueryBBReg(pAdapter, rFPGA0_XCD_RFInterfaceSW, bMaskDWord)&0x1CC000)>>14;
++ pdmpriv->rf_saving_RegC70 = (PHY_QueryBBReg(pAdapter, rOFDM0_AGCParameter1, bMaskDWord)&BIT3)>>3;
++ pdmpriv->rf_saving_Reg85C = (PHY_QueryBBReg(pAdapter, rFPGA0_XCD_SwitchControl, bMaskDWord)&0xFF000000)>>24;
++ pdmpriv->rf_saving_RegA74 = (PHY_QueryBBReg(pAdapter, 0xa74, bMaskDWord)&0xF000)>>12;
++ //Reg818 = PHY_QueryBBReg(pAdapter, 0x818, bMaskDWord);
++ pdmpriv->initialize = 1;
++ }
++
++ if(!bForceInNormal)
++ {
++ if(pPSTable->Rssi_val_min != 0)
++ {
++
++ if(pPSTable->PreRFState == RF_Normal)
++ {
++ #ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV
++ if(pPSTable->Rssi_val_min >= 50)
++ #else
++ if(pPSTable->Rssi_val_min >= 30)
++ #endif
++ pPSTable->CurRFState = RF_Save;
++ else
++ pPSTable->CurRFState = RF_Normal;
++ }
++ else{
++ #ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV
++ if(pPSTable->Rssi_val_min <= 45)
++ #else
++ if(pPSTable->Rssi_val_min <= 25)
++ #endif
++ pPSTable->CurRFState = RF_Normal;
++ else
++ pPSTable->CurRFState = RF_Save;
++ }
++ }
++ else
++ pPSTable->CurRFState=RF_MAX;
++ }
++ else
++ {
++ pPSTable->CurRFState = RF_Normal;
++ }
++
++ if(pPSTable->PreRFState != pPSTable->CurRFState)
++ {
++ if(pPSTable->CurRFState == RF_Save)
++ {
++ PHY_SetBBReg(pAdapter, rFPGA0_XCD_RFInterfaceSW , 0x1C0000, 0x2); //Reg874[20:18]=3'b010
++ PHY_SetBBReg(pAdapter, rOFDM0_AGCParameter1, BIT3, 0); //RegC70[3]=1'b0
++ PHY_SetBBReg(pAdapter, rFPGA0_XCD_SwitchControl, 0xFF000000, 0x63); //Reg85C[31:24]=0x63
++ PHY_SetBBReg(pAdapter, rFPGA0_XCD_RFInterfaceSW, 0xC000, 0x2); //Reg874[15:14]=2'b10
++ PHY_SetBBReg(pAdapter, 0xa74, 0xF000, 0x3); //RegA75[7:4]=0x3
++ PHY_SetBBReg(pAdapter, 0x818, BIT28, 0x0); //Reg818[28]=1'b0
++ PHY_SetBBReg(pAdapter, 0x818, BIT28, 0x1); //Reg818[28]=1'b1
++ DBG_8192C("%s(): RF_Save\n", __FUNCTION__);
++ }
++ else
++ {
++ PHY_SetBBReg(pAdapter, rFPGA0_XCD_RFInterfaceSW , 0x1CC000, pdmpriv->rf_saving_Reg874);
++ PHY_SetBBReg(pAdapter, rOFDM0_AGCParameter1, BIT3, pdmpriv->rf_saving_RegC70);
++ PHY_SetBBReg(pAdapter, rFPGA0_XCD_SwitchControl, 0xFF000000, pdmpriv->rf_saving_Reg85C);
++ PHY_SetBBReg(pAdapter, 0xa74, 0xF000, pdmpriv->rf_saving_RegA74);
++ PHY_SetBBReg(pAdapter, 0x818, BIT28, 0x0);
++ DBG_8192C("%s(): RF_Normal\n", __FUNCTION__);
++ }
++ pPSTable->PreRFState = pPSTable->CurRFState;
++ }
++}
++
++static void
++dm_DynamicBBPowerSaving(
++IN PADAPTER pAdapter
++ )
++{
++
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
++ struct mlme_priv *pmlmepriv = &pAdapter->mlmepriv;
++ struct dm_priv *pdmpriv = &pHalData->dmpriv;
++ PS_T *pPSTable = &pdmpriv->DM_PSTable;
++
++ //1 1.Determine the minimum RSSI
++ if((check_fwstate(pmlmepriv, _FW_LINKED) != _TRUE) &&
++ (pdmpriv->EntryMinUndecoratedSmoothedPWDB == 0))
++ {
++ pPSTable->Rssi_val_min = 0;
++ //RT_TRACE(COMP_BB_POWERSAVING, DBG_LOUD, ("Not connected to any \n"));
++ }
++ if(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) // Default port
++ {
++ //if(ACTING_AS_AP(pAdapter) || pMgntInfo->mIbss)
++ if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) ||
++ (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE)) //todo: AP Mode
++ {
++ pPSTable->Rssi_val_min = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
++ //RT_TRACE(COMP_BB_POWERSAVING, DBG_LOUD, ("AP Client PWDB = 0x%lx \n", pPSTable->Rssi_val_min));
++ }
++ else
++ {
++ pPSTable->Rssi_val_min = pdmpriv->UndecoratedSmoothedPWDB;
++ //RT_TRACE(COMP_BB_POWERSAVING, DBG_LOUD, ("STA Default Port PWDB = 0x%lx \n", pPSTable->Rssi_val_min));
++ }
++ }
++ else // associated entry pwdb
++ {
++ pPSTable->Rssi_val_min = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
++ //RT_TRACE(COMP_BB_POWERSAVING, DBG_LOUD, ("AP Ext Port PWDB = 0x%lx \n", pPSTable->Rssi_val_min));
++ }
++
++ //1 2.Power Saving for 92C
++ if(IS_92C_SERIAL(pHalData->VersionID))
++ {
++ //dm_1R_CCA(pAdapter);
++ }
++
++ // 20100628 Joseph: Turn off BB power save for 88CE because it makesthroughput unstable.
++ // 20100831 Joseph: Turn ON BB power save again after modifying AGC delay from 900ns to 600ns.
++ //1 3.Power Saving for 88C
++ else
++ {
++ rtl8192c_dm_RF_Saving(pAdapter, _FALSE);
++ }
++}
++
++
++#ifdef CONFIG_ANTENNA_DIVERSITY
++// Add new function to reset the state of antenna diversity before link.
++//
++void SwAntDivResetBeforeLink8192C(IN PADAPTER Adapter)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ struct dm_priv *pdmpriv = &pHalData->dmpriv;
++ SWAT_T *pDM_SWAT_Table = &pdmpriv->DM_SWAT_Table;
++
++ pDM_SWAT_Table->SWAS_NoLink_State = 0;
++}
++
++// Compare RSSI for deciding antenna
++void SwAntDivCompare8192C(PADAPTER Adapter, WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++
++ if((0 != pHalData->AntDivCfg) && (!IS_92C_SERIAL(pHalData->VersionID)) )
++ {
++ //DBG_8192C("update_network=> orgRSSI(%d)(%d),newRSSI(%d)(%d)\n",dst->Rssi,query_rx_pwr_percentage(dst->Rssi),
++ // src->Rssi,query_rx_pwr_percentage(src->Rssi));
++ //select optimum_antenna for before linked =>For antenna diversity
++ if(dst->Rssi >= src->Rssi )//keep org parameter
++ {
++ src->Rssi = dst->Rssi;
++ src->PhyInfo.Optimum_antenna = dst->PhyInfo.Optimum_antenna;
++ }
++ }
++}
++
++// Add new function to reset the state of antenna diversity before link.
++u8 SwAntDivBeforeLink8192C(IN PADAPTER Adapter)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ struct dm_priv *pdmpriv = &pHalData->dmpriv;
++ SWAT_T *pDM_SWAT_Table = &pdmpriv->DM_SWAT_Table;
++ struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv);
++
++ // Condition that does not need to use antenna diversity.
++ if(IS_92C_SERIAL(pHalData->VersionID) ||(pHalData->AntDivCfg==0))
++ {
++ //DBG_8192C("SwAntDivBeforeLink8192C(): No AntDiv Mechanism.\n");
++ return _FALSE;
++ }
++
++ if(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)
++ {
++ pDM_SWAT_Table->SWAS_NoLink_State = 0;
++ return _FALSE;
++ }
++ // Since driver is going to set BB register, it shall check if there is another thread controlling BB/RF.
++/*
++ if(pHalData->eRFPowerState!=eRfOn || pMgntInfo->RFChangeInProgress || pMgntInfo->bMediaConnect)
++ {
++
++
++ RT_TRACE(COMP_SWAS, DBG_LOUD,
++ ("SwAntDivCheckBeforeLink8192C(): RFChangeInProgress(%x), eRFPowerState(%x)\n",
++ pMgntInfo->RFChangeInProgress,
++ pHalData->eRFPowerState));
++
++ pDM_SWAT_Table->SWAS_NoLink_State = 0;
++
++ return FALSE;
++ }
++*/
++
++ if(pDM_SWAT_Table->SWAS_NoLink_State == 0){
++ //switch channel
++ pDM_SWAT_Table->SWAS_NoLink_State = 1;
++ pDM_SWAT_Table->CurAntenna = (pDM_SWAT_Table->CurAntenna==Antenna_A)?Antenna_B:Antenna_A;
++
++ //PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300, pDM_SWAT_Table->CurAntenna);
++ rtw_antenna_select_cmd(Adapter, pDM_SWAT_Table->CurAntenna, _FALSE);
++ //DBG_8192C("%s change antenna to ANT_( %s ).....\n",__FUNCTION__, (pDM_SWAT_Table->CurAntenna==Antenna_A)?"A":"B");
++ return _TRUE;
++ }
++ else
++ {
++ pDM_SWAT_Table->SWAS_NoLink_State = 0;
++ return _FALSE;
++ }
++
++
++
++}
++#endif
++#ifdef CONFIG_SW_ANTENNA_DIVERSITY
++//
++// 20100514 Luke/Joseph:
++// Add new function to reset antenna diversity state after link.
++//
++void
++SwAntDivRestAfterLink8192C(
++ IN PADAPTER Adapter
++ )
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ struct dm_priv *pdmpriv = &pHalData->dmpriv;
++ SWAT_T *pDM_SWAT_Table = &pdmpriv->DM_SWAT_Table;
++
++ if(IS_92C_SERIAL(pHalData->VersionID) ||(pHalData->AntDivCfg==0))
++ return;
++
++ //DBG_8192C("======> SwAntDivRestAfterLink <========== \n");
++ pHalData->RSSI_cnt_A= 0;
++ pHalData->RSSI_cnt_B= 0;
++ pHalData->RSSI_test = _FALSE;
++
++ pDM_SWAT_Table->try_flag = 0xff;
++ pDM_SWAT_Table->RSSI_Trying = 0;
++ pDM_SWAT_Table->SelectAntennaMap=0xAA;
++ pDM_SWAT_Table->CurAntenna = pHalData->CurAntenna;
++ pDM_SWAT_Table->PreAntenna = pHalData->CurAntenna;
++
++ pdmpriv->lastTxOkCnt=0;
++ pdmpriv->lastRxOkCnt=0;
++
++ pdmpriv->TXByteCnt_A=0;
++ pdmpriv->TXByteCnt_B=0;
++ pdmpriv->RXByteCnt_A=0;
++ pdmpriv->RXByteCnt_B=0;
++ pdmpriv->DoubleComfirm=0;
++ pdmpriv->TrafficLoad = TRAFFIC_LOW;
++
++}
++
++
++//
++// 20100514 Luke/Joseph:
++// Add new function for antenna diversity after link.
++// This is the main function of antenna diversity after link.
++// This function is called in HalDmWatchDog() and dm_SW_AntennaSwitchCallback().
++// HalDmWatchDog() calls this function with SWAW_STEP_PEAK to initialize the antenna test.
++// In SWAW_STEP_PEAK, another antenna and a 500ms timer will be set for testing.
++// After 500ms, dm_SW_AntennaSwitchCallback() calls this function to compare the signal just
++// listened on the air with the RSSI of original antenna.
++// It chooses the antenna with better RSSI.
++// There is also a aged policy for error trying. Each error trying will cost more 5 seconds waiting
++// penalty to get next try.
++//
++static VOID
++dm_SW_AntennaSwitch(
++ PADAPTER Adapter,
++ u8 Step
++)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ struct dm_priv *pdmpriv = &pHalData->dmpriv;
++ SWAT_T *pDM_SWAT_Table = &pdmpriv->DM_SWAT_Table;
++ s32 curRSSI=100, RSSI_A, RSSI_B;
++ u64 curTxOkCnt, curRxOkCnt;
++ u64 CurByteCnt = 0, PreByteCnt = 0;
++ u8 nextAntenna = 0;
++ u8 Score_A=0, Score_B=0;
++ u8 i;
++
++ // Condition that does not need to use antenna diversity.
++ if(IS_92C_SERIAL(pHalData->VersionID) ||(pHalData->AntDivCfg==0))
++ {
++ //RT_TRACE(COMP_SWAS, DBG_LOUD, ("dm_SW_AntennaSwitch(): No AntDiv Mechanism.\n"));
++ return;
++ }
++ // If dynamic ant_div is disabled.
++ if(!(pdmpriv->DMFlag & DYNAMIC_FUNC_ANT_DIV) )
++ {
++ return;
++ }
++
++ if (check_fwstate(&Adapter->mlmepriv, _FW_LINKED) ==_FALSE)
++ return;
++#if 0 //to do
++ // Radio off: Status reset to default and return.
++ if(pHalData->eRFPowerState==eRfOff)
++ {
++ SwAntDivRestAfterLink(Adapter);
++ return;
++ }
++#endif
++ //DBG_8192C("\n............................ %s.........................\n",__FUNCTION__);
++ // Handling step mismatch condition.
++ // Peak step is not finished at last time. Recover the variable and check again.
++ if( Step != pDM_SWAT_Table->try_flag )
++ {
++ SwAntDivRestAfterLink8192C(Adapter);
++ }
++
++
++ if(pDM_SWAT_Table->try_flag == 0xff)
++ {
++#if 0
++ // Select RSSI checking target
++ if(pMgntInfo->mAssoc && !ACTING_AS_AP(Adapter))
++ {
++ // Target: Infrastructure mode AP.
++ pHalData->RSSI_target = NULL;
++ RT_TRACE(COMP_SWAS, DBG_LOUD, ("dm_SW_AntennaSwitch(): RSSI_target is DEF AP!\n"));
++ }
++ else
++ {
++ u8 index = 0;
++ PRT_WLAN_STA pEntry = NULL;
++ PADAPTER pTargetAdapter = NULL;
++
++ if( pMgntInfo->mIbss || ACTING_AS_AP(Adapter) )
++ {
++ // Target: AP/IBSS peer.
++ pTargetAdapter = Adapter;
++ }
++ else if(ACTING_AS_AP(ADJUST_TO_ADAPTIVE_ADAPTER(Adapter, FALSE)))
++ {
++ // Target: VWIFI peer.
++ pTargetAdapter = ADJUST_TO_ADAPTIVE_ADAPTER(Adapter, FALSE);
++ }
++
++ if(pTargetAdapter != NULL)
++ {
++ for(index=0; index<ASSOCIATE_ENTRY_NUM; index++)
++ {
++ pEntry = AsocEntry_EnumStation(pTargetAdapter, index);
++ if(pEntry != NULL)
++ {
++ if(pEntry->bAssociated)
++ break;
++ }
++ }
++ }
++
++ if(pEntry == NULL)
++ {
++ SwAntDivRestAfterLink(Adapter);
++ RT_TRACE(COMP_SWAS, DBG_LOUD, ("dm_SW_AntennaSwitch(): No Link.\n"));
++ return;
++ }
++ else
++ {
++ pHalData->RSSI_target = pEntry;
++ RT_TRACE(COMP_SWAS, DBG_LOUD, ("dm_SW_AntennaSwitch(): RSSI_target is PEER STA\n"));
++ }
++ }
++
++
++#endif
++
++ pHalData->RSSI_cnt_A= 0;
++ pHalData->RSSI_cnt_B= 0;
++ pDM_SWAT_Table->try_flag = 0;
++ // DBG_8192C("dm_SW_AntennaSwitch(): Set try_flag to 0 prepare for peak!\n");
++ return;
++ }
++ else
++ {
++ curTxOkCnt = Adapter->xmitpriv.tx_bytes - pdmpriv->lastTxOkCnt;
++ curRxOkCnt = Adapter->recvpriv.rx_bytes - pdmpriv->lastRxOkCnt;
++
++ pdmpriv->lastTxOkCnt = Adapter->xmitpriv.tx_bytes ;
++ pdmpriv->lastRxOkCnt = Adapter->recvpriv.rx_bytes ;
++
++ if(pDM_SWAT_Table->try_flag == 1)
++ {
++ if(pDM_SWAT_Table->CurAntenna == Antenna_A)
++ {
++ pdmpriv->TXByteCnt_A += curTxOkCnt;
++ pdmpriv->RXByteCnt_A += curRxOkCnt;
++ //DBG_8192C("##### TXByteCnt_A(%lld) , RXByteCnt_A(%lld) ####\n",pdmpriv->TXByteCnt_A,pdmpriv->RXByteCnt_A);
++ }
++ else
++ {
++ pdmpriv->TXByteCnt_B += curTxOkCnt;
++ pdmpriv->RXByteCnt_B += curRxOkCnt;
++ //DBG_8192C("##### TXByteCnt_B(%lld) , RXByteCnt_B(%lld) ####\n",pdmpriv->TXByteCnt_B,pdmpriv->RXByteCnt_B);
++ }
++
++ nextAntenna = (pDM_SWAT_Table->CurAntenna == Antenna_A)? Antenna_B : Antenna_A;
++ pDM_SWAT_Table->RSSI_Trying--;
++ //DBG_8192C("RSSI_Trying = %d\n",pDM_SWAT_Table->RSSI_Trying);
++
++ if(pDM_SWAT_Table->RSSI_Trying == 0)
++ {
++ CurByteCnt = (pDM_SWAT_Table->CurAntenna == Antenna_A)? (pdmpriv->TXByteCnt_A+pdmpriv->RXByteCnt_A) : (pdmpriv->TXByteCnt_B+pdmpriv->RXByteCnt_B);
++ PreByteCnt = (pDM_SWAT_Table->CurAntenna == Antenna_A)? (pdmpriv->TXByteCnt_B+pdmpriv->RXByteCnt_B) : (pdmpriv->TXByteCnt_A+pdmpriv->RXByteCnt_A);
++
++ //DBG_8192C("CurByteCnt = %lld\n", CurByteCnt);
++ //DBG_8192C("PreByteCnt = %lld\n",PreByteCnt);
++
++ if(pdmpriv->TrafficLoad == TRAFFIC_HIGH)
++ {
++ PreByteCnt = PreByteCnt*9; //normalize:Cur=90ms:Pre=10ms
++ }
++ else if(pdmpriv->TrafficLoad == TRAFFIC_LOW)
++ {
++ //CurByteCnt = CurByteCnt/2;
++ CurByteCnt = CurByteCnt>>1;//normalize:100ms:50ms
++ }
++
++
++ //DBG_8192C("After DIV=>CurByteCnt = %lld\n", CurByteCnt);
++ //DBG_8192C("PreByteCnt = %lld\n",PreByteCnt);
++
++ if(pHalData->RSSI_cnt_A > 0)
++ RSSI_A = pHalData->RSSI_sum_A/pHalData->RSSI_cnt_A;
++ else
++ RSSI_A = 0;
++ if(pHalData->RSSI_cnt_B > 0)
++ RSSI_B = pHalData->RSSI_sum_B/pHalData->RSSI_cnt_B;
++ else
++ RSSI_B = 0;
++
++ curRSSI = (pDM_SWAT_Table->CurAntenna == Antenna_A)? RSSI_A : RSSI_B;
++ pDM_SWAT_Table->PreRSSI = (pDM_SWAT_Table->CurAntenna == Antenna_A)? RSSI_B : RSSI_A;
++ //DBG_8192C("Luke:PreRSSI = %d, CurRSSI = %d\n",pDM_SWAT_Table->PreRSSI, curRSSI);
++ //DBG_8192C("SWAS: preAntenna= %s, curAntenna= %s \n",
++ //(pDM_SWAT_Table->PreAntenna == Antenna_A?"A":"B"), (pDM_SWAT_Table->CurAntenna == Antenna_A?"A":"B"));
++ //DBG_8192C("Luke:RSSI_A= %d, RSSI_cnt_A = %d, RSSI_B= %d, RSSI_cnt_B = %d\n",
++ //RSSI_A, pHalData->RSSI_cnt_A, RSSI_B, pHalData->RSSI_cnt_B);
++ }
++
++ }
++ else
++ {
++
++ if(pHalData->RSSI_cnt_A > 0)
++ RSSI_A = pHalData->RSSI_sum_A/pHalData->RSSI_cnt_A;
++ else
++ RSSI_A = 0;
++ if(pHalData->RSSI_cnt_B > 0)
++ RSSI_B = pHalData->RSSI_sum_B/pHalData->RSSI_cnt_B;
++ else
++ RSSI_B = 0;
++ curRSSI = (pDM_SWAT_Table->CurAntenna == Antenna_A)? RSSI_A : RSSI_B;
++ pDM_SWAT_Table->PreRSSI = (pDM_SWAT_Table->PreAntenna == Antenna_A)? RSSI_A : RSSI_B;
++ //DBG_8192C("Ekul:PreRSSI = %d, CurRSSI = %d\n", pDM_SWAT_Table->PreRSSI, curRSSI);
++ //DBG_8192C("SWAS: preAntenna= %s, curAntenna= %s \n",
++ //(pDM_SWAT_Table->PreAntenna == Antenna_A?"A":"B"), (pDM_SWAT_Table->CurAntenna == Antenna_A?"A":"B"));
++
++ //DBG_8192C("Ekul:RSSI_A= %d, RSSI_cnt_A = %d, RSSI_B= %d, RSSI_cnt_B = %d\n",
++ // RSSI_A, pHalData->RSSI_cnt_A, RSSI_B, pHalData->RSSI_cnt_B);
++ //RT_TRACE(COMP_SWAS, DBG_LOUD, ("Ekul:curTxOkCnt = %d\n", curTxOkCnt));
++ //RT_TRACE(COMP_SWAS, DBG_LOUD, ("Ekul:curRxOkCnt = %d\n", curRxOkCnt));
++ }
++
++ //1 Trying State
++ if((pDM_SWAT_Table->try_flag == 1)&&(pDM_SWAT_Table->RSSI_Trying == 0))
++ {
++
++ if(pDM_SWAT_Table->TestMode == TP_MODE)
++ {
++ //DBG_8192C("SWAS: TestMode = TP_MODE\n");
++ //DBG_8192C("TRY:CurByteCnt = %lld\n", CurByteCnt);
++ //DBG_8192C("TRY:PreByteCnt = %lld\n",PreByteCnt);
++ if(CurByteCnt < PreByteCnt)
++ {
++ if(pDM_SWAT_Table->CurAntenna == Antenna_A)
++ pDM_SWAT_Table->SelectAntennaMap=pDM_SWAT_Table->SelectAntennaMap<<1;
++ else
++ pDM_SWAT_Table->SelectAntennaMap=(pDM_SWAT_Table->SelectAntennaMap<<1)+1;
++ }
++ else
++ {
++ if(pDM_SWAT_Table->CurAntenna == Antenna_A)
++ pDM_SWAT_Table->SelectAntennaMap=(pDM_SWAT_Table->SelectAntennaMap<<1)+1;
++ else
++ pDM_SWAT_Table->SelectAntennaMap=pDM_SWAT_Table->SelectAntennaMap<<1;
++ }
++ for (i= 0; i<8; i++)
++ {
++ if(((pDM_SWAT_Table->SelectAntennaMap>>i)&BIT0) == 1)
++ Score_A++;
++ else
++ Score_B++;
++ }
++ //DBG_8192C("SelectAntennaMap=%x\n ",pDM_SWAT_Table->SelectAntennaMap);
++ //DBG_8192C("Score_A=%d, Score_B=%d\n", Score_A, Score_B);
++
++ if(pDM_SWAT_Table->CurAntenna == Antenna_A)
++ {
++ nextAntenna = (Score_A > Score_B)?Antenna_A:Antenna_B;
++ }
++ else
++ {
++ nextAntenna = (Score_B > Score_A)?Antenna_B:Antenna_A;
++ }
++ //RT_TRACE(COMP_SWAS, DBG_LOUD, ("nextAntenna=%s\n",(nextAntenna==Antenna_A)?"A":"B"));
++ //RT_TRACE(COMP_SWAS, DBG_LOUD, ("preAntenna= %s, curAntenna= %s \n",
++ //(DM_SWAT_Table.PreAntenna == Antenna_A?"A":"B"), (DM_SWAT_Table.CurAntenna == Antenna_A?"A":"B")));
++
++ if(nextAntenna != pDM_SWAT_Table->CurAntenna)
++ {
++ //DBG_8192C("SWAS: Switch back to another antenna\n");
++ }
++ else
++ {
++ //DBG_8192C("SWAS: current anntena is good\n");
++ }
++ }
++
++ if(pDM_SWAT_Table->TestMode == RSSI_MODE)
++ {
++ //DBG_8192C("SWAS: TestMode = RSSI_MODE\n");
++ pDM_SWAT_Table->SelectAntennaMap=0xAA;
++ if(curRSSI < pDM_SWAT_Table->PreRSSI) //Current antenna is worse than previous antenna
++ {
++ //DBG_8192C("SWAS: Switch back to another antenna\n");
++ nextAntenna = (pDM_SWAT_Table->CurAntenna == Antenna_A)? Antenna_B : Antenna_A;
++ }
++ else // current anntena is good
++ {
++ nextAntenna = pDM_SWAT_Table->CurAntenna;
++ //DBG_8192C("SWAS: current anntena is good\n");
++ }
++ }
++ pDM_SWAT_Table->try_flag = 0;
++ pHalData->RSSI_test = _FALSE;
++ pHalData->RSSI_sum_A = 0;
++ pHalData->RSSI_cnt_A = 0;
++ pHalData->RSSI_sum_B = 0;
++ pHalData->RSSI_cnt_B = 0;
++ pdmpriv->TXByteCnt_A = 0;
++ pdmpriv->TXByteCnt_B = 0;
++ pdmpriv->RXByteCnt_A = 0;
++ pdmpriv->RXByteCnt_B = 0;
++
++ }
++
++ //1 Normal State
++ else if(pDM_SWAT_Table->try_flag == 0)
++ {
++ if(pdmpriv->TrafficLoad == TRAFFIC_HIGH)
++ {
++ if(((curTxOkCnt+curRxOkCnt)>>1) > 1875000)
++ pdmpriv->TrafficLoad = TRAFFIC_HIGH;
++ else
++ pdmpriv->TrafficLoad = TRAFFIC_LOW;
++ }
++ else if(pdmpriv->TrafficLoad == TRAFFIC_LOW)
++ {
++ if(((curTxOkCnt+curRxOkCnt)>>1) > 1875000)
++ pdmpriv->TrafficLoad = TRAFFIC_HIGH;
++ else
++ pdmpriv->TrafficLoad = TRAFFIC_LOW;
++ }
++ if(pdmpriv->TrafficLoad == TRAFFIC_HIGH)
++ pDM_SWAT_Table->bTriggerAntennaSwitch = 0;
++ //DBG_8192C("Normal:TrafficLoad = %lld\n", curTxOkCnt+curRxOkCnt);
++
++ //Prepare To Try Antenna
++ nextAntenna = (pDM_SWAT_Table->CurAntenna == Antenna_A)? Antenna_B : Antenna_A;
++ pDM_SWAT_Table->try_flag = 1;
++ pHalData->RSSI_test = _TRUE;
++ if((curRxOkCnt+curTxOkCnt) > 1000)
++ {
++ pDM_SWAT_Table->RSSI_Trying = 4;
++ pDM_SWAT_Table->TestMode = TP_MODE;
++ }
++ else
++ {
++ pDM_SWAT_Table->RSSI_Trying = 2;
++ pDM_SWAT_Table->TestMode = RSSI_MODE;
++
++ }
++ //DBG_8192C("SWAS: Normal State -> Begin Trying! TestMode=%s\n",(pDM_SWAT_Table->TestMode == TP_MODE)?"TP":"RSSI");
++
++
++ pHalData->RSSI_sum_A = 0;
++ pHalData->RSSI_cnt_A = 0;
++ pHalData->RSSI_sum_B = 0;
++ pHalData->RSSI_cnt_B = 0;
++ }
++ }
++
++ //1 4.Change TRX antenna
++ if(nextAntenna != pDM_SWAT_Table->CurAntenna)
++ {
++ //DBG_8192C("@@@@@@@@ SWAS: Change TX Antenna!\n ");
++ rtw_antenna_select_cmd(Adapter, nextAntenna, 1);
++ }
++
++ //1 5.Reset Statistics
++ pDM_SWAT_Table->PreAntenna = pDM_SWAT_Table->CurAntenna;
++ pDM_SWAT_Table->CurAntenna = nextAntenna;
++ pDM_SWAT_Table->PreRSSI = curRSSI;
++
++
++ //1 6.Set next timer
++
++ if(pDM_SWAT_Table->RSSI_Trying == 0)
++ return;
++
++ if(pDM_SWAT_Table->RSSI_Trying%2 == 0)
++ {
++ if(pDM_SWAT_Table->TestMode == TP_MODE)
++ {
++ if(pdmpriv->TrafficLoad == TRAFFIC_HIGH)
++ {
++ _set_timer(&pdmpriv->SwAntennaSwitchTimer,10 ); //ms
++ //DBG_8192C("dm_SW_AntennaSwitch(): Test another antenna for 10 ms\n");
++ }
++ else if(pdmpriv->TrafficLoad == TRAFFIC_LOW)
++ {
++ _set_timer(&pdmpriv->SwAntennaSwitchTimer, 50 ); //ms
++ //DBG_8192C("dm_SW_AntennaSwitch(): Test another antenna for 50 ms\n");
++ }
++ }
++ else
++ {
++ _set_timer(&pdmpriv->SwAntennaSwitchTimer, 500 ); //ms
++ //DBG_8192C("dm_SW_AntennaSwitch(): Test another antenna for 500 ms\n");
++ }
++ }
++ else
++ {
++ if(pDM_SWAT_Table->TestMode == TP_MODE)
++ {
++ if(pdmpriv->TrafficLoad == TRAFFIC_HIGH)
++ _set_timer(&pdmpriv->SwAntennaSwitchTimer,90 ); //ms
++ else if(pdmpriv->TrafficLoad == TRAFFIC_LOW)
++ _set_timer(&pdmpriv->SwAntennaSwitchTimer,100 ); //ms
++ }
++ else
++ {
++ _set_timer(&pdmpriv->SwAntennaSwitchTimer,500 ); //ms
++ //DBG_8192C("dm_SW_AntennaSwitch(): Test another antenna for 500 ms\n");
++ }
++ }
++
++// RT_TRACE(COMP_SWAS, DBG_LOUD, ("SWAS: -----The End-----\n "));
++
++}
++
++//
++// 20100514 Luke/Joseph:
++// Callback function for 500ms antenna test trying.
++//
++static void dm_SW_AntennaSwitchCallback(void *FunctionContext)
++{
++ _adapter *padapter = (_adapter *)FunctionContext;
++
++ if(padapter->net_closed == _TRUE)
++ return;
++ // Only
++ dm_SW_AntennaSwitch(padapter, SWAW_STEP_DETERMINE);
++}
++
++
++//
++// 20100722
++// This function is used to gather the RSSI information for antenna testing.
++// It selects the RSSI of the peer STA that we want to know.
++//
++void SwAntDivRSSICheck8192C(_adapter *padapter ,u32 RxPWDBAll)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct dm_priv *pdmpriv = &pHalData->dmpriv;
++
++ SWAT_T *pDM_SWAT_Table = &pdmpriv->DM_SWAT_Table;
++
++ if(IS_92C_SERIAL(pHalData->VersionID) ||pHalData->AntDivCfg==0)
++ return;
++
++ if(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)
++ {
++ if(pDM_SWAT_Table->CurAntenna == Antenna_A)
++ {
++ pHalData->RSSI_sum_A += RxPWDBAll;
++ pHalData->RSSI_cnt_A++;
++ }
++ else
++ {
++ pHalData->RSSI_sum_B+= RxPWDBAll;
++ pHalData->RSSI_cnt_B++;
++
++ }
++ //DBG_8192C("%s Ant_(%s),RSSI_sum(%d),RSSI_cnt(%d)\n",__FUNCTION__,(2==pHalData->CurAntenna)?"A":"B",pHalData->RSSI_sum,pHalData->RSSI_cnt);
++ }
++
++}
++
++
++
++static VOID
++dm_SW_AntennaSwitchInit(
++ IN PADAPTER Adapter
++ )
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ struct dm_priv *pdmpriv = &pHalData->dmpriv;
++ SWAT_T *pDM_SWAT_Table = &pdmpriv->DM_SWAT_Table;
++
++ pHalData->RSSI_sum_A = 0;
++ pHalData->RSSI_sum_B = 0;
++ pHalData->RSSI_cnt_A = 0;
++ pHalData->RSSI_cnt_B = 0;
++
++ pDM_SWAT_Table->CurAntenna = pHalData->CurAntenna;
++ pDM_SWAT_Table->PreAntenna = pHalData->CurAntenna;
++ pDM_SWAT_Table->try_flag = 0xff;
++ pDM_SWAT_Table->PreRSSI = 0;
++ pDM_SWAT_Table->bTriggerAntennaSwitch = 0;
++ pDM_SWAT_Table->SelectAntennaMap=0xAA;
++
++ // Move the timer initialization to InitializeVariables function.
++ //PlatformInitializeTimer(Adapter, &pMgntInfo->SwAntennaSwitchTimer, (RT_TIMER_CALL_BACK)dm_SW_AntennaSwitchCallback, NULL, "SwAntennaSwitchTimer");
++}
++
++#endif
++
++//#define RSSI_CCK 0
++//#define RSSI_OFDM 1
++static void dm_RSSIMonitorInit(
++ IN PADAPTER Adapter
++)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ struct dm_priv *pdmpriv = &pHalData->dmpriv;
++ pdmpriv->OFDM_Pkt_Cnt = 0;
++ pdmpriv->RSSI_Select = RSSI_DEFAULT;
++}
++
++static void dm_RSSIMonitorCheck(
++ IN PADAPTER Adapter
++)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ struct dm_priv *pdmpriv = &pHalData->dmpriv;
++ struct mlme_priv *pmlmepriv = &Adapter->mlmepriv;
++
++ if(check_fwstate(pmlmepriv, _FW_LINKED) == _FALSE)
++ return;
++
++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE |WIFI_ADHOC_STATE) == _TRUE )
++ {
++ if(Adapter->stapriv.asoc_sta_count < 2)
++ return;
++ }
++
++ if(pdmpriv->OFDM_Pkt_Cnt == 0)
++ pdmpriv->RSSI_Select = RSSI_CCK;
++ else
++ pdmpriv->RSSI_Select = RSSI_OFDM;
++
++ pdmpriv->OFDM_Pkt_Cnt = 0;
++ //DBG_8192C("RSSI_Select=%s OFDM_Pkt_Cnt(%d)\n",
++ //(pdmpriv->RSSI_Select == RSSI_OFDM)?"RSSI_OFDM":"RSSI_CCK",
++ //pdmpriv->OFDM_Pkt_Cnt);
++}
++
++//============================================================
++// functions
++//============================================================
++void rtl8192c_init_dm_priv(IN PADAPTER Adapter)
++{
++ PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
++ struct dm_priv *pdmpriv = &pHalData->dmpriv;
++
++ //_rtw_memset(pdmpriv, 0, sizeof(struct dm_priv));
++
++#ifdef CONFIG_SW_ANTENNA_DIVERSITY
++ _init_timer(&(pdmpriv->SwAntennaSwitchTimer), Adapter->pnetdev , dm_SW_AntennaSwitchCallback, Adapter);
++#endif
++}
++
++void rtl8192c_deinit_dm_priv(IN PADAPTER Adapter)
++{
++ PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
++ struct dm_priv *pdmpriv = &pHalData->dmpriv;
++
++#ifdef CONFIG_SW_ANTENNA_DIVERSITY
++ _cancel_timer_ex(&pdmpriv->SwAntennaSwitchTimer);
++#endif
++}
++#ifdef CONFIG_HW_ANTENNA_DIVERSITY
++void dm_InitHybridAntDiv(IN PADAPTER Adapter)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++
++ if(IS_92C_SERIAL(pHalData->VersionID) ||pHalData->AntDivCfg==0)
++ return;
++
++ //Set OFDM HW RX Antenna Diversity
++ PHY_SetBBReg(Adapter,0xc50, BIT7, 1); //Enable Hardware antenna switch
++ PHY_SetBBReg(Adapter,0x870, BIT9|BIT8, 0); //Enable hardware control of "ANT_SEL" & "ANT_SELB"
++ PHY_SetBBReg(Adapter,0xCA4, BIT11, 0); //Switch to another antenna by checking pwdb threshold
++ PHY_SetBBReg(Adapter,0xCA4, 0x7FF, 0x080); //Pwdb threshold=8dB
++ PHY_SetBBReg(Adapter,0xC54, BIT23, 1); //Decide final antenna by comparing 2 antennas' pwdb
++ PHY_SetBBReg(Adapter,0x874, BIT23, 0); //No update ANTSEL during GNT_BT=1
++ PHY_SetBBReg(Adapter,0x80C, BIT21, 1); //TX atenna selection from tx_info
++ //Set CCK HW RX Antenna Diversity
++ PHY_SetBBReg(Adapter,0xA00, BIT15, 1);//Enable antenna diversity
++ PHY_SetBBReg(Adapter,0xA0C, BIT4, 0); //Antenna diversity decision period = 32 sample
++ PHY_SetBBReg(Adapter,0xA0C, 0xf, 0xf); //Threshold for antenna diversity. Check another antenna power if input power < ANT_lim*4
++ PHY_SetBBReg(Adapter,0xA10, BIT13, 1); //polarity ana_A=1 and ana_B=0
++ PHY_SetBBReg(Adapter,0xA14, 0x1f, 0x8); //default antenna power = inpwr*(0.5 + r_ant_step/16)
++
++ pHalData->CCK_Ant1_Cnt = 0;
++ pHalData->CCK_Ant2_Cnt = 0;
++ pHalData->OFDM_Ant1_Cnt = 0;
++ pHalData->OFDM_Ant2_Cnt = 0;
++}
++
++
++#define RxDefaultAnt1 0x65a9
++#define RxDefaultAnt2 0x569a
++
++void dm_SelectRXDefault(IN PADAPTER Adapter)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++
++ if(IS_92C_SERIAL(pHalData->VersionID) ||pHalData->AntDivCfg==0)
++ return;
++
++ //DbgPrint(" Ant1_Cnt=%d, Ant2_Cnt=%d\n", pHalData->Ant1_Cnt, pHalData->Ant2_Cnt);
++ //DBG_8192C(" CCK_Ant1_Cnt = %d, CCK_Ant2_Cnt = %d\n", pHalData->CCK_Ant1_Cnt, pHalData->CCK_Ant2_Cnt);
++ //DBG_8192C(" OFDM_Ant1_Cnt = %d, OFDM_Ant2_Cnt = %d\n", pHalData->OFDM_Ant1_Cnt, pHalData->OFDM_Ant2_Cnt);
++ if((pHalData->OFDM_Ant1_Cnt == 0) && (pHalData->OFDM_Ant2_Cnt == 0))
++ {
++ if((pHalData->CCK_Ant1_Cnt + pHalData->CCK_Ant2_Cnt) >=10 )
++ {
++ if(pHalData->CCK_Ant1_Cnt > (5*pHalData->CCK_Ant2_Cnt))
++ {
++ DBG_8192C(" RX Default = Ant1\n");
++ PHY_SetBBReg(Adapter, 0x858, 0xFFFF, RxDefaultAnt1);
++ }
++ else if(pHalData->CCK_Ant2_Cnt > (5*pHalData->CCK_Ant1_Cnt))
++ {
++ DBG_8192C(" RX Default = Ant2\n");
++ PHY_SetBBReg(Adapter, 0x858, 0xFFFF, RxDefaultAnt2);
++ }
++ else if(pHalData->CCK_Ant1_Cnt > pHalData->CCK_Ant2_Cnt)
++ {
++ DBG_8192C(" RX Default = Ant2\n");
++ PHY_SetBBReg(Adapter, 0x858, 0xFFFF, RxDefaultAnt2);
++ }
++ else
++ {
++ DBG_8192C(" RX Default = Ant1\n");
++ PHY_SetBBReg(Adapter, 0x858, 0xFFFF, RxDefaultAnt1);
++ }
++ pHalData->CCK_Ant1_Cnt = 0;
++ pHalData->CCK_Ant2_Cnt = 0;
++ pHalData->OFDM_Ant1_Cnt = 0;
++ pHalData->OFDM_Ant2_Cnt = 0;
++ }
++ }
++ else
++ {
++ if(pHalData->OFDM_Ant1_Cnt > pHalData->OFDM_Ant2_Cnt)
++ {
++ DBG_8192C(" RX Default = Ant1\n");
++ PHY_SetBBReg(Adapter, 0x858, 0xFFFF, RxDefaultAnt1);
++ }
++ else
++ {
++ DBG_8192C(" RX Default = Ant2\n");
++ PHY_SetBBReg(Adapter, 0x858, 0xFFFF, RxDefaultAnt2);
++ }
++ pHalData->CCK_Ant1_Cnt = 0;
++ pHalData->CCK_Ant2_Cnt = 0;
++ pHalData->OFDM_Ant1_Cnt = 0;
++ pHalData->OFDM_Ant2_Cnt = 0;
++ }
++
++
++}
++
++#endif
++
++void
++rtl8192c_InitHalDm(
++ IN PADAPTER Adapter
++ )
++{
++ PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
++ struct dm_priv *pdmpriv = &pHalData->dmpriv;
++ u8 i;
++
++#ifdef CONFIG_USB_HCI
++ dm_InitGPIOSetting(Adapter);
++#endif
++
++ pdmpriv->DM_Type = DM_Type_ByDriver;
++ pdmpriv->DMFlag = DYNAMIC_FUNC_DISABLE;
++ pdmpriv->UndecoratedSmoothedPWDB = (-1);
++ pdmpriv->UndecoratedSmoothedCCK = (-1);
++
++
++ //.1 DIG INIT
++ pdmpriv->bDMInitialGainEnable = _TRUE;
++ pdmpriv->DMFlag |= DYNAMIC_FUNC_DIG;
++ dm_DIGInit(Adapter);
++
++ //.2 DynamicTxPower INIT
++ pdmpriv->DMFlag |= DYNAMIC_FUNC_HP;
++ dm_InitDynamicTxPower(Adapter);
++
++ //.3
++ DM_InitEdcaTurbo(Adapter);
++
++ //.4 RateAdaptive INIT
++ dm_InitRateAdaptiveMask(Adapter);
++
++ //.5 Tx Power Tracking Init.
++ pdmpriv->DMFlag |= DYNAMIC_FUNC_SS;
++ DM_InitializeTXPowerTracking(Adapter);
++
++#ifdef CONFIG_BT_COEXIST
++ pdmpriv->DMFlag |= DYNAMIC_FUNC_BT;
++ dm_InitBtCoexistDM(Adapter);
++#endif
++
++ dm_InitDynamicBBPowerSaving(Adapter);
++
++#ifdef CONFIG_SW_ANTENNA_DIVERSITY
++ pdmpriv->DMFlag |= DYNAMIC_FUNC_ANT_DIV;
++ dm_SW_AntennaSwitchInit(Adapter);
++#endif
++
++#ifdef CONFIG_HW_ANTENNA_DIVERSITY
++ pdmpriv->DMFlag |= DYNAMIC_FUNC_ANT_DIV;
++ dm_InitHybridAntDiv(Adapter);
++#endif
++
++ dm_RSSIMonitorInit(Adapter);
++
++ pdmpriv->DMFlag_tmp = pdmpriv->DMFlag;
++
++ // Save REG_INIDATA_RATE_SEL value for TXDESC.
++ for(i = 0 ; i<32 ; i++)
++ {
++ pdmpriv->INIDATA_RATE[i] = rtw_read8(Adapter, REG_INIDATA_RATE_SEL+i) & 0x3f;
++ }
++
++#ifdef CONFIG_DM_ADAPTIVITY
++ pdmpriv->DMFlag |= DYNAMIC_FUNC_ADAPTIVITY;
++ dm_adaptivity_init(Adapter);
++#endif
++
++}
++
++#ifdef CONFIG_CONCURRENT_MODE
++static void FindMinimumRSSI(PADAPTER Adapter)
++{
++ PHAL_DATA_TYPE pbuddy_HalData;
++ struct dm_priv *pbuddy_dmpriv;
++ PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
++ struct dm_priv *pdmpriv = &pHalData->dmpriv;
++ PADAPTER pbuddy_adapter = Adapter->pbuddy_adapter;
++ struct mlme_priv *pmlmepriv = &Adapter->mlmepriv;
++
++ if(!rtw_buddy_adapter_up(Adapter))
++ return;
++
++ pbuddy_HalData = GET_HAL_DATA(pbuddy_adapter);
++ pbuddy_dmpriv = &pbuddy_HalData->dmpriv;
++
++ //get min. [PWDB] when both interfaces are connected
++ if((check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE
++ && Adapter->stapriv.asoc_sta_count > 2
++ && check_buddy_fwstate(Adapter, _FW_LINKED)) ||
++ (check_buddy_fwstate(Adapter, WIFI_AP_STATE) == _TRUE
++ && pbuddy_adapter->stapriv.asoc_sta_count > 2
++ && check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) ||
++ (check_fwstate(pmlmepriv, WIFI_STATION_STATE)
++ && check_fwstate(pmlmepriv, _FW_LINKED)
++ && check_buddy_fwstate(Adapter,WIFI_STATION_STATE)
++ && check_buddy_fwstate(Adapter,_FW_LINKED)))
++ {
++ if(pdmpriv->UndecoratedSmoothedPWDB > pbuddy_dmpriv->UndecoratedSmoothedPWDB)
++ pdmpriv->UndecoratedSmoothedPWDB = pbuddy_dmpriv->UndecoratedSmoothedPWDB;
++ }//primary interface is not connected
++ else if((check_buddy_fwstate(Adapter, WIFI_AP_STATE) == _TRUE
++ && pbuddy_adapter->stapriv.asoc_sta_count > 2) ||
++ (check_buddy_fwstate(Adapter,WIFI_STATION_STATE)
++ && check_buddy_fwstate(Adapter,_FW_LINKED)))
++ {
++ pdmpriv->UndecoratedSmoothedPWDB = pbuddy_dmpriv->UndecoratedSmoothedPWDB;
++ }
++ //secondary is not connected
++ else if((check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE
++ && Adapter->stapriv.asoc_sta_count > 2) ||
++ (check_fwstate(pmlmepriv, WIFI_STATION_STATE)
++ && check_fwstate(pmlmepriv, _FW_LINKED)))
++ {
++ pbuddy_dmpriv->UndecoratedSmoothedPWDB = 0;
++ }
++ //both interfaces are not connected
++ else
++ {
++ pdmpriv->UndecoratedSmoothedPWDB = 0;
++ pbuddy_dmpriv->UndecoratedSmoothedPWDB = 0;
++ }
++
++ //primary interface is ap mode
++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE && Adapter->stapriv.asoc_sta_count > 2)
++ {
++ pbuddy_dmpriv->EntryMinUndecoratedSmoothedPWDB = 0;
++ }//secondary interface is ap mode
++ else if(check_buddy_fwstate(Adapter, WIFI_AP_STATE) == _TRUE && pbuddy_adapter->stapriv.asoc_sta_count > 2)
++ {
++ pdmpriv->EntryMinUndecoratedSmoothedPWDB = pbuddy_dmpriv->EntryMinUndecoratedSmoothedPWDB;
++ }
++ else //both interfaces are not ap mode
++ {
++ pdmpriv->EntryMinUndecoratedSmoothedPWDB = pbuddy_dmpriv->EntryMinUndecoratedSmoothedPWDB = 0;
++ }
++
++}
++
++#endif //CONFIG_CONCURRENT_MODE
++
++VOID
++rtl8192c_HalDmWatchDog(
++ IN PADAPTER Adapter
++ )
++{
++ BOOLEAN bFwCurrentInPSMode = _FALSE;
++ BOOLEAN bFwPSAwake = _TRUE;
++ u8 hw_init_completed = _FALSE;
++ PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
++ struct dm_priv *pdmpriv = &pHalData->dmpriv;
++ struct mlme_priv *pmlmepriv = &Adapter->mlmepriv;
++#ifdef CONFIG_CONCURRENT_MODE
++ PADAPTER pbuddy_adapter = Adapter->pbuddy_adapter;
++#endif //CONFIG_CONCURRENT_MODE
++
++ #if defined(CONFIG_CONCURRENT_MODE)
++ if (Adapter->isprimary == _FALSE && pbuddy_adapter) {
++ hw_init_completed = pbuddy_adapter->hw_init_completed;
++ } else
++ #endif
++ {
++ hw_init_completed = Adapter->hw_init_completed;
++ }
++
++ if (hw_init_completed == _FALSE)
++ goto skip_dm;
++
++#ifdef CONFIG_LPS
++ #if defined(CONFIG_CONCURRENT_MODE)
++ if (Adapter->iface_type != IFACE_PORT0 && pbuddy_adapter) {
++ bFwCurrentInPSMode = pbuddy_adapter->pwrctrlpriv.bFwCurrentInPSMode;
++ rtw_hal_get_hwreg(pbuddy_adapter, HW_VAR_FWLPS_RF_ON, (u8 *)(&bFwPSAwake));
++ } else
++ #endif
++ {
++ bFwCurrentInPSMode = Adapter->pwrctrlpriv.bFwCurrentInPSMode;
++ rtw_hal_get_hwreg(Adapter, HW_VAR_FWLPS_RF_ON, (u8 *)(&bFwPSAwake));
++ }
++#endif
++
++#ifdef CONFIG_P2P_PS
++ // Fw is under p2p powersaving mode, driver should stop dynamic mechanism.
++ // modifed by thomas. 2011.06.11.
++ if(Adapter->wdinfo.p2p_ps_mode)
++ bFwPSAwake = _FALSE;
++#endif // CONFIG_P2P_PS
++
++ // Stop dynamic mechanism when:
++ // 1. RF is OFF. (No need to do DM.)
++ // 2. Fw is under power saving mode for FwLPS. (Prevent from SW/FW I/O racing.)
++ // 3. IPS workitem is scheduled. (Prevent from IPS sequence to be swapped with DM.
++ // Sometimes DM execution time is longer than 100ms such that the assertion
++ // in MgntActSet_RF_State() called by InactivePsWorkItem will be triggered by
++ // wating to long for RFChangeInProgress.)
++ // 4. RFChangeInProgress is TRUE. (Prevent from broken by IPS/HW/SW Rf off.)
++ // Noted by tynli. 2010.06.01.
++ //if(rfState == eRfOn)
++ if( (hw_init_completed == _TRUE)
++ && ((!bFwCurrentInPSMode) && bFwPSAwake))
++ {
++ //
++ // Calculate Tx/Rx statistics.
++ //
++ dm_CheckStatistics(Adapter);
++
++ //
++ // For PWDB monitor and record some value for later use.
++ //
++ PWDB_Monitor(Adapter);
++
++ dm_RSSIMonitorCheck(Adapter);
++
++#ifdef CONFIG_CONCURRENT_MODE
++ if(Adapter->adapter_type > PRIMARY_ADAPTER)
++ goto _record_initrate;
++
++ FindMinimumRSSI(Adapter);
++#endif
++
++ //
++ // Dynamic Initial Gain mechanism.
++ //
++ dm_FalseAlarmCounterStatistics(Adapter);
++ dm_DIG(Adapter);
++ dm_adaptivity(Adapter);
++
++ //
++ //Dynamic BB Power Saving Mechanism
++ //
++ dm_DynamicBBPowerSaving(Adapter);
++
++ //
++ // Dynamic Tx Power mechanism.
++ //
++ dm_DynamicTxPower(Adapter);
++
++ //
++ // Tx Power Tracking.
++ //
++#if MP_DRIVER == 0
++#ifdef CONFIG_BUSY_TRAFFIC_SKIP_PWR_TRACK
++ if(pmlmepriv->LinkDetectInfo.bBusyTraffic == _FALSE)
++#endif //CONFIG_BUSY_TRAFFIC_SKIP_PWR_TRACK
++#endif
++ rtl8192c_dm_CheckTXPowerTracking(Adapter);
++
++ //
++ // Rate Adaptive by Rx Signal Strength mechanism.
++ //
++ dm_RefreshRateAdaptiveMask(Adapter);
++
++#ifdef CONFIG_BT_COEXIST
++ //BT-Coexist
++ dm_BTCoexist(Adapter);
++#endif
++
++ // EDCA turbo
++ //update the EDCA paramter according to the Tx/RX mode
++ //update_EDCA_param(Adapter);
++ dm_CheckEdcaTurbo(Adapter);
++
++ //
++ // Dynamically switch RTS/CTS protection.
++ //
++ //dm_CheckProtection(Adapter);
++
++#ifdef CONFIG_SW_ANTENNA_DIVERSITY
++ //
++ // Software Antenna diversity
++ //
++ dm_SW_AntennaSwitch(Adapter, SWAW_STEP_PEAK);
++#endif
++
++#ifdef CONFIG_HW_ANTENNA_DIVERSITY
++ //Hybrid Antenna Diversity
++ dm_SelectRXDefault(Adapter);
++#endif
++
++#ifdef CONFIG_PCI_HCI
++ // 20100630 Joseph: Disable Interrupt Migration mechanism temporarily because it degrades Rx throughput.
++ // Tx Migration settings.
++ //dm_InterruptMigration(Adapter);
++
++ //if(Adapter->HalFunc.TxCheckStuckHandler(Adapter))
++ // PlatformScheduleWorkItem(&(GET_HAL_DATA(Adapter)->HalResetWorkItem));
++#endif
++
++
++_record_initrate:
++
++ // Read REG_INIDATA_RATE_SEL value for TXDESC.
++ if(check_fwstate(&Adapter->mlmepriv, WIFI_STATION_STATE) == _TRUE)
++ {
++ pdmpriv->INIDATA_RATE[0] = rtw_read8(Adapter, REG_INIDATA_RATE_SEL) & 0x3f;
++
++#ifdef CONFIG_TDLS
++ if(Adapter->tdlsinfo.setup_state == TDLS_LINKED_STATE)
++ {
++ u8 i=1;
++ for(; i < (Adapter->tdlsinfo.macid_index) ; i++)
++ {
++ pdmpriv->INIDATA_RATE[i] = rtw_read8(Adapter, (REG_INIDATA_RATE_SEL+i)) & 0x3f;
++ }
++ }
++#endif //CONFIG_TDLS
++
++ }
++ else
++ {
++ u8 i;
++ for(i=1 ; i < (Adapter->stapriv.asoc_sta_count + 1); i++)
++ {
++ pdmpriv->INIDATA_RATE[i] = rtw_read8(Adapter, (REG_INIDATA_RATE_SEL+i)) & 0x3f;
++ }
++ }
++ }
++
++skip_dm:
++
++ // Check GPIO to determine current RF on/off and Pbc status.
++ // Check Hardware Radio ON/OFF or not
++ //if(Adapter->MgntInfo.PowerSaveControl.bGpioRfSw)
++ //{
++ //RTPRINT(FPWR, PWRHW, ("dm_CheckRfCtrlGPIO \n"));
++ // dm_CheckRfCtrlGPIO(Adapter);
++ //}
++
++#ifdef CONFIG_PCI_HCI
++ if(pHalData->bGpioHwWpsPbc)
++#endif
++ {
++ dm_CheckPbcGPIO(Adapter); // Add by hpfan 2008-03-11
++ }
++
++}
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/hal/rtl8192c/rtl8192c_hal_init.c linux-xbian-rpi/drivers/net/wireless/rtl8192cu/hal/rtl8192c/rtl8192c_hal_init.c
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/hal/rtl8192c/rtl8192c_hal_init.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/hal/rtl8192c/rtl8192c_hal_init.c 2015-07-28 01:20:58.309639981 +0200
+@@ -0,0 +1,3627 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++
++#define _RTL8192C_HAL_INIT_C_
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++#include <rtw_byteorder.h>
++#include <rtw_efuse.h>
++
++#include <rtl8192c_hal.h>
++
++#ifdef CONFIG_USB_HCI
++#include <usb_hal.h>
++#endif
++
++#ifdef CONFIG_PCI_HCI
++#include <pci_hal.h>
++#endif
++
++static BOOLEAN
++hal_EfusePgPacketWrite2ByteHeader(
++ IN PADAPTER pAdapter,
++ IN u8 efuseType,
++ IN u16 *pAddr,
++ IN PPGPKT_STRUCT pTargetPkt,
++ IN BOOLEAN bPseudoTest);
++static BOOLEAN
++hal_EfusePgPacketWrite1ByteHeader(
++ IN PADAPTER pAdapter,
++ IN u8 efuseType,
++ IN u16 *pAddr,
++ IN PPGPKT_STRUCT pTargetPkt,
++ IN BOOLEAN bPseudoTest);
++static BOOLEAN
++hal_EfusePgPacketWriteData(
++ IN PADAPTER pAdapter,
++ IN u8 efuseType,
++ IN u16 *pAddr,
++ IN PPGPKT_STRUCT pTargetPkt,
++ IN BOOLEAN bPseudoTest);
++static BOOLEAN
++hal_EfusePgPacketWrite_BT(
++ IN PADAPTER pAdapter,
++ IN u8 offset,
++ IN u8 word_en,
++ IN u8 *pData,
++ IN BOOLEAN bPseudoTest);
++
++static VOID
++_FWDownloadEnable(
++ IN PADAPTER Adapter,
++ IN BOOLEAN enable
++ )
++{
++ u8 tmp;
++
++ if(enable)
++ {
++ #ifdef DBG_SHOW_MCUFWDL_BEFORE_51_ENABLE
++ {
++ u8 val;
++ if( (val=rtw_read8(Adapter, REG_MCUFWDL)))
++ DBG_871X("DBG_SHOW_MCUFWDL_BEFORE_51_ENABLE %s:%d REG_MCUFWDL:0x%02x\n", __FUNCTION__, __LINE__, val);
++ }
++ #endif
++
++ // 8051 enable
++ tmp = rtw_read8(Adapter, REG_SYS_FUNC_EN+1);
++ rtw_write8(Adapter, REG_SYS_FUNC_EN+1, tmp|0x04);
++
++ // MCU firmware download enable.
++ tmp = rtw_read8(Adapter, REG_MCUFWDL);
++ rtw_write8(Adapter, REG_MCUFWDL, tmp|0x01);
++
++ // 8051 reset
++ tmp = rtw_read8(Adapter, REG_MCUFWDL+2);
++ rtw_write8(Adapter, REG_MCUFWDL+2, tmp&0xf7);
++ }
++ else
++ {
++ // MCU firmware download enable.
++ tmp = rtw_read8(Adapter, REG_MCUFWDL);
++ rtw_write8(Adapter, REG_MCUFWDL, tmp&0xfe);
++
++ // Reserved for fw extension.
++ rtw_write8(Adapter, REG_MCUFWDL+1, 0x00);
++ }
++}
++
++
++#define MAX_REG_BOLCK_SIZE 196
++#define MIN_REG_BOLCK_SIZE 8
++
++static int
++_BlockWrite(
++ IN PADAPTER Adapter,
++ IN PVOID buffer,
++ IN u32 size
++ )
++{
++ int ret = _SUCCESS;
++
++#ifdef CONFIG_PCI_HCI
++ u32 blockSize = sizeof(u32); // Use 4-byte write to download FW
++ u8 *bufferPtr = (u8 *)buffer;
++ u32 *pu4BytePtr = (u32 *)buffer;
++ u32 i, offset, blockCount, remainSize;
++ u8 remainFW[4] = {0, 0, 0, 0};
++ u8 *p = NULL;
++
++ blockCount = size / blockSize;
++ remainSize = size % blockSize;
++
++ for(i = 0 ; i < blockCount ; i++){
++ offset = i * blockSize;
++ rtw_write32(Adapter, (FW_8192C_START_ADDRESS + offset), cpu_to_le32(*(pu4BytePtr + i)));
++ }
++
++ p = (u8*)((u32*)(bufferPtr + blockCount * blockSize));
++ if(remainSize){
++ switch (remainSize) {
++ case 0:
++ break;
++ case 3:
++ remainFW[2]=*(p+2);
++ case 2:
++ remainFW[1]=*(p+1);
++ case 1:
++ remainFW[0]=*(p);
++ ret = rtw_write32(Adapter, (FW_8192C_START_ADDRESS + blockCount * blockSize),
++ le32_to_cpu(*(u32*)remainFW));
++ }
++ return ret;
++ }
++#else
++
++#ifdef SUPPORTED_BLOCK_IO
++ u32 blockSize = MAX_REG_BOLCK_SIZE; // Use 196-byte write to download FW
++ u32 blockSize2 = MIN_REG_BOLCK_SIZE;
++#else
++ u32 blockSize = sizeof(u32); // Use 4-byte write to download FW
++ u32* pu4BytePtr = (u32*)buffer;
++ u32 blockSize2 = sizeof(u8);
++#endif
++ u8* bufferPtr = (u8*)buffer;
++ u32 i, offset = 0, offset2, blockCount, remainSize, remainSize2;
++
++ blockCount = size / blockSize;
++ remainSize = size % blockSize;
++
++ for(i = 0 ; i < blockCount ; i++){
++ offset = i * blockSize;
++ #ifdef SUPPORTED_BLOCK_IO
++ ret = rtw_writeN(Adapter, (FW_8192C_START_ADDRESS + offset), blockSize, (bufferPtr + offset));
++ #else
++ ret = rtw_write32(Adapter, (FW_8192C_START_ADDRESS + offset), le32_to_cpu(*(pu4BytePtr + i)));
++ #endif
++
++ if(ret == _FAIL)
++ goto exit;
++ }
++
++ if(remainSize){
++ #if defined(SUPPORTED_BLOCK_IO) && defined(DBG_BLOCK_WRITE_ISSUE) //Can this be enabled?
++ offset = blockCount * blockSize;
++ ret = rtw_writeN(Adapter, (FW_8192C_START_ADDRESS + offset), remainSize, (bufferPtr + offset));
++ goto exit;
++ #endif
++ offset2 = blockCount * blockSize;
++ blockCount = remainSize / blockSize2;
++ remainSize2 = remainSize % blockSize2;
++
++ for(i = 0 ; i < blockCount ; i++){
++ offset = offset2 + i * blockSize2;
++ #ifdef SUPPORTED_BLOCK_IO
++ ret = rtw_writeN(Adapter, (FW_8192C_START_ADDRESS + offset), blockSize2, (bufferPtr + offset));
++ #else
++ ret = rtw_write8(Adapter, (FW_8192C_START_ADDRESS + offset ), *(bufferPtr + offset));
++ #endif
++
++ if(ret == _FAIL)
++ goto exit;
++ }
++
++ if(remainSize2)
++ {
++ offset += blockSize2;
++ bufferPtr += offset;
++
++ for(i = 0 ; i < remainSize2 ; i++){
++ ret = rtw_write8(Adapter, (FW_8192C_START_ADDRESS + offset + i), *(bufferPtr + i));
++
++ if(ret == _FAIL)
++ goto exit;
++ }
++ }
++ }
++#endif
++
++exit:
++ return ret;
++}
++
++static int
++_PageWrite(
++ IN PADAPTER Adapter,
++ IN u32 page,
++ IN PVOID buffer,
++ IN u32 size
++ )
++{
++ u8 value8;
++ u8 u8Page = (u8) (page & 0x07) ;
++
++ value8 = (rtw_read8(Adapter, REG_MCUFWDL+2)& 0xF8 ) | u8Page ;
++ rtw_write8(Adapter, REG_MCUFWDL+2,value8);
++ return _BlockWrite(Adapter,buffer,size);
++}
++
++static VOID
++_FillDummy(
++ u8* pFwBuf,
++ u32* pFwLen
++ )
++{
++ u32 FwLen = *pFwLen;
++ u8 remain = (u8)(FwLen%4);
++ remain = (remain==0)?0:(4-remain);
++
++ while(remain>0)
++ {
++ pFwBuf[FwLen] = 0;
++ FwLen++;
++ remain--;
++ }
++
++ *pFwLen = FwLen;
++}
++
++static int
++_WriteFW(
++ IN PADAPTER Adapter,
++ IN PVOID buffer,
++ IN u32 size
++ )
++{
++ // Since we need dynamic decide method of dwonload fw, so we call this function to get chip version.
++ // We can remove _ReadChipVersion from ReadAdapterInfo8192C later.
++
++ int ret = _SUCCESS;
++ u32 pageNums,remainSize ;
++ u32 page,offset;
++ u8* bufferPtr = (u8*)buffer;
++
++#ifdef CONFIG_PCI_HCI
++ // 20100120 Joseph: Add for 88CE normal chip.
++ // Fill in zero to make firmware image to dword alignment.
++// _FillDummy(bufferPtr, &size);
++#endif
++
++ pageNums = size / MAX_PAGE_SIZE ;
++ //RT_ASSERT((pageNums <= 4), ("Page numbers should not greater then 4 \n"));
++ remainSize = size % MAX_PAGE_SIZE;
++
++ for(page = 0; page < pageNums; page++){
++ offset = page *MAX_PAGE_SIZE;
++ ret = _PageWrite(Adapter,page, (bufferPtr+offset),MAX_PAGE_SIZE);
++
++ if(ret == _FAIL)
++ goto exit;
++ }
++ if(remainSize){
++ offset = pageNums *MAX_PAGE_SIZE;
++ page = pageNums;
++ ret = _PageWrite(Adapter,page, (bufferPtr+offset),remainSize);
++
++ if(ret == _FAIL)
++ goto exit;
++ }
++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("_WriteFW Done- for Normal chip.\n"));
++
++exit:
++ return ret;
++}
++
++static int _FWFreeToGo(
++ IN PADAPTER Adapter
++ )
++{
++ u32 counter = 0;
++ u32 value32;
++ u32 restarted = _FALSE;
++
++ // polling CheckSum report
++ do{
++ value32 = rtw_read32(Adapter, REG_MCUFWDL);
++ }while((counter ++ < POLLING_READY_TIMEOUT_COUNT) && (!(value32 & FWDL_ChkSum_rpt)));
++
++ if(counter >= POLLING_READY_TIMEOUT_COUNT){
++ DBG_8192C("chksum report faill ! REG_MCUFWDL:0x%08x\n",value32);
++ return _FAIL;
++ } else {
++ //DBG_8192C("chksum report success ! REG_MCUFWDL:0x%08x, counter:%u\n",value32, counter);
++ }
++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("Checksum report OK ! REG_MCUFWDL:0x%08x .\n",value32));
++
++
++ value32 = rtw_read32(Adapter, REG_MCUFWDL);
++ value32 |= MCUFWDL_RDY;
++ value32 &= ~WINTINI_RDY;
++ rtw_write32(Adapter, REG_MCUFWDL, value32);
++
++
++POLLING_FW_READY:
++ // polling for FW ready
++ counter = 0;
++ do
++ {
++ if(rtw_read32(Adapter, REG_MCUFWDL) & WINTINI_RDY){
++ //RT_TRACE(COMP_INIT, DBG_SERIOUS, ("Polling FW ready success!! REG_MCUFWDL:0x%08x .\n",PlatformIORead4Byte(Adapter, REG_MCUFWDL)) );
++ return _SUCCESS;
++ }
++ rtw_udelay_os(5);
++ }while(counter++ < POLLING_READY_TIMEOUT_COUNT);
++
++ DBG_8192C("Polling FW ready fail!! REG_MCUFWDL:0x%08x .\n", rtw_read32(Adapter, REG_MCUFWDL));
++
++ if(restarted == _FALSE) {
++ u8 tmp = rtw_read8(Adapter, REG_SYS_FUNC_EN+1);
++ DBG_8192C("Reset 51 write8 REG_SYS_FUNC_EN:0x%04x\n", tmp & ~BIT2);
++ rtw_write8(Adapter, REG_SYS_FUNC_EN+1, tmp & ~BIT2);
++ DBG_8192C("Reset 51 write8 REG_SYS_FUNC_EN:0x%04x\n", tmp|BIT2);
++ rtw_write8(Adapter, REG_SYS_FUNC_EN+1, tmp|BIT2);
++ restarted = _TRUE;
++ goto POLLING_FW_READY;
++ }
++
++
++ return _FAIL;
++
++}
++
++
++VOID
++rtl8192c_FirmwareSelfReset(
++ IN PADAPTER Adapter
++)
++{
++ u8 u1bTmp;
++ u8 Delay = 100;
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++
++ if((pHalData->FirmwareVersion > 0x21) ||
++ (pHalData->FirmwareVersion == 0x21 &&
++ pHalData->FirmwareSubVersion >= 0x01)) // after 88C Fw v33.1
++ {
++ //0x1cf=0x20. Inform 8051 to reset. 2009.12.25. tynli_test
++ rtw_write8(Adapter, REG_HMETFR+3, 0x20);
++
++ u1bTmp = rtw_read8(Adapter, REG_SYS_FUNC_EN+1);
++ while(u1bTmp&BIT2)
++ {
++ Delay--;
++ if(Delay == 0)
++ break;
++ rtw_udelay_os(50);
++ u1bTmp = rtw_read8(Adapter, REG_SYS_FUNC_EN+1);
++ }
++
++ if((u1bTmp&BIT2) && (Delay == 0))
++ {
++ DBG_8192C("FirmwareDownload92C():fw reset by itself Fail!!!!!! 0x03 = %x\n", u1bTmp);
++ //RT_ASSERT(FALSE, ("PowerOffAdapter8192CE(): 0x03 = %x\n", u1bTmp));
++ #ifdef DBG_SHOW_MCUFWDL_BEFORE_51_ENABLE
++ {
++ u8 val;
++ if( (val=rtw_read8(Adapter, REG_MCUFWDL)))
++ DBG_871X("DBG_SHOW_MCUFWDL_BEFORE_51_ENABLE %s:%d REG_MCUFWDL:0x%02x\n", __FUNCTION__, __LINE__, val);
++ }
++ #endif
++ rtw_write8(Adapter,REG_SYS_FUNC_EN+1,(rtw_read8(Adapter, REG_SYS_FUNC_EN+1)&~BIT2));
++ }
++
++ DBG_8192C("%s =====> 8051 reset success (%d) .\n", __FUNCTION__ ,Delay);
++ }
++}
++
++#ifdef CONFIG_FILE_FWIMG
++extern char *rtw_fw_file_path;
++u8 FwBuffer8192C[FW_8192C_SIZE];
++#endif //CONFIG_FILE_FWIMG
++//
++// Description:
++// Download 8192C firmware code.
++//
++//
++int FirmwareDownload92C(
++ IN PADAPTER Adapter,
++ IN BOOLEAN bUsedWoWLANFw
++)
++{
++ int rtStatus = _SUCCESS;
++ u8 writeFW_retry = 0;
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ s8 R92CFwImageFileName_TSMC[] ={RTL8192C_FW_TSMC_IMG};
++ s8 R92CFwImageFileName_UMC[] ={RTL8192C_FW_UMC_IMG};
++ s8 R92CFwImageFileName_UMC_B[] ={RTL8192C_FW_UMC_B_IMG};
++#ifdef CONFIG_WOWLAN
++ s8 R92CFwImageFileName_TSMC_WW[] ={RTL8192C_FW_TSMC_WW_IMG};
++ s8 R92CFwImageFileName_UMC_WW[] ={RTL8192C_FW_UMC_WW_IMG};
++ s8 R92CFwImageFileName_UMC_B_WW[] ={RTL8192C_FW_UMC_B_WW_IMG};
++#endif //CONFIG_WOWLAN
++
++ //s8 R8723FwImageFileName_UMC[] ={RTL8723_FW_UMC_IMG};
++ u8* FwImage = NULL;
++ u32 FwImageLen = 0;
++ char* pFwImageFileName;
++#ifdef CONFIG_WOWLAN
++ u8* FwImageWoWLAN;
++ u32 FwImageWoWLANLen;
++ char* pFwImageFileName_WoWLAN;
++#endif //CONFIG_WOWLAN
++ u8* pucMappedFile = NULL;
++ //vivi, merge 92c and 92s into one driver, 20090817
++ //vivi modify this temply, consider it later!!!!!!!!
++ //PRT_FIRMWARE pFirmware = GET_FIRMWARE_819X(Adapter);
++ //PRT_FIRMWARE_92C pFirmware = GET_FIRMWARE_8192C(Adapter);
++ PRT_FIRMWARE_92C pFirmware = NULL;
++ PRT_8192C_FIRMWARE_HDR pFwHdr = NULL;
++ u8 *pFirmwareBuf;
++ u32 FirmwareLen;
++
++ pFirmware = (PRT_FIRMWARE_92C)rtw_zvmalloc(sizeof(RT_FIRMWARE_92C));
++
++ if(!pFirmware)
++ {
++ rtStatus = _FAIL;
++ goto Exit;
++ }
++
++ if(IS_VENDOR_UMC_A_CUT(pHalData->VersionID) && !IS_92C_SERIAL(pHalData->VersionID))
++ {
++ pFwImageFileName = R92CFwImageFileName_UMC;
++ FwImage = Rtl819XFwUMCACutImageArray;
++ FwImageLen = UMCACutImgArrayLength;
++#ifdef CONFIG_WOWLAN
++ pFwImageFileName_WoWLAN = R92CFwImageFileName_UMC_WW;
++ FwImageWoWLAN= Rtl8192C_FwUMCWWImageArray;
++ FwImageWoWLANLen =UMCACutWWImgArrayLength ;
++#endif //CONFIG_WOWLAN
++ DBG_8192C(" ===> FirmwareDownload91C() fw:Rtl819XFwImageArray_UMC\n");
++ }
++ else if(IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID))
++ {
++ // The ROM code of UMC B-cut Fw is the same as TSMC. by tynli. 2011.01.14.
++ pFwImageFileName = R92CFwImageFileName_UMC_B;
++ FwImage = Rtl819XFwUMCBCutImageArray;
++ FwImageLen = UMCBCutImgArrayLength;
++#ifdef CONFIG_WOWLAN
++ pFwImageFileName_WoWLAN = R92CFwImageFileName_UMC_B_WW;
++ FwImageWoWLAN= Rtl8192C_FwUMCBCutWWImageArray;
++ FwImageWoWLANLen =UMCBCutWWImgArrayLength ;
++#endif //CONFIG_WOWLAN
++
++ DBG_8192C(" ===> FirmwareDownload91C() fw:Rtl819XFwImageArray_UMC_B\n");
++ }
++ else
++ {
++ pFwImageFileName = R92CFwImageFileName_TSMC;
++ FwImage = Rtl819XFwTSMCImageArray;
++ FwImageLen = TSMCImgArrayLength;
++#ifdef CONFIG_WOWLAN
++ pFwImageFileName_WoWLAN = R92CFwImageFileName_TSMC_WW;
++ FwImageWoWLAN= Rtl8192C_FwTSMCWWImageArray;
++ FwImageWoWLANLen =TSMCWWImgArrayLength ;
++#endif //CONFIG_WOWLAN
++ DBG_8192C(" ===> FirmwareDownload91C() fw:Rtl819XFwImageArray_TSMC\n");
++ }
++
++ //RT_TRACE(COMP_INIT, DBG_LOUD, (" ===> FirmwareDownload91C() fw:%s\n", pFwImageFileName));
++
++ #ifdef CONFIG_FILE_FWIMG
++ if(rtw_is_file_readable(rtw_fw_file_path) == _TRUE)
++ {
++ DBG_871X("%s accquire FW from file:%s\n", __FUNCTION__, rtw_fw_file_path);
++ pFirmware->eFWSource = FW_SOURCE_IMG_FILE; // We should decided by Reg.
++ }
++ else
++ #endif //CONFIG_FILE_FWIMG
++ {
++ DBG_871X("%s accquire FW from embedded image\n", __FUNCTION__);
++ pFirmware->eFWSource = FW_SOURCE_HEADER_FILE;
++ }
++
++
++ switch(pFirmware->eFWSource)
++ {
++ case FW_SOURCE_IMG_FILE:
++
++ #ifdef CONFIG_FILE_FWIMG
++ rtStatus = rtw_retrive_from_file(rtw_fw_file_path, FwBuffer8192C, FW_8192C_SIZE);
++ pFirmware->ulFwLength = rtStatus>=0?rtStatus:0;
++ pFirmware->szFwBuffer = FwBuffer8192C;
++ #endif //CONFIG_FILE_FWIMG
++
++ if(pFirmware->ulFwLength <= 0)
++ {
++ rtStatus = _FAIL;
++ goto Exit;
++ }
++ break;
++ case FW_SOURCE_HEADER_FILE:
++ if(FwImageLen > FW_8192C_SIZE){
++ rtStatus = _FAIL;
++ //RT_TRACE(COMP_INIT, DBG_SERIOUS, ("Firmware size exceed 0x%X. Check it.\n", FW_8192C_SIZE) );
++ DBG_871X("Firmware size exceed 0x%X. Check it.\n", FW_8192C_SIZE);
++ goto Exit;
++ }
++
++ pFirmware->szFwBuffer = FwImage;
++ pFirmware->ulFwLength = FwImageLen;
++#ifdef CONFIG_WOWLAN
++ {
++ pFirmware->szWoWLANFwBuffer=FwImageWoWLAN;
++ pFirmware->ulWoWLANFwLength = FwImageWoWLANLen;
++ }
++#endif //CONFIG_WOWLAN
++
++ break;
++ }
++
++#ifdef CONFIG_WOWLAN
++ if(bUsedWoWLANFw) {
++ pFirmwareBuf = pFirmware->szWoWLANFwBuffer;
++ FirmwareLen = pFirmware->ulWoWLANFwLength;
++ pFwHdr = (PRT_8192C_FIRMWARE_HDR)pFirmware->szWoWLANFwBuffer;
++ }
++ else
++#endif //CONFIG_WOWLAN
++ {
++ #ifdef DBG_FW_STORE_FILE_PATH //used to store firmware to file...
++ if(pFirmware->ulFwLength > 0)
++ {
++ rtw_store_to_file(DBG_FW_STORE_FILE_PATH, pFirmware->szFwBuffer, pFirmware->ulFwLength);
++ }
++ #endif
++
++ pFirmwareBuf = pFirmware->szFwBuffer;
++ FirmwareLen = pFirmware->ulFwLength;
++
++ // To Check Fw header. Added by tynli. 2009.12.04.
++ pFwHdr = (PRT_8192C_FIRMWARE_HDR)pFirmware->szFwBuffer;
++ }
++ pHalData->FirmwareVersion = le16_to_cpu(pFwHdr->Version);
++ pHalData->FirmwareSubVersion = le16_to_cpu(pFwHdr->Subversion);
++
++ //RT_TRACE(COMP_INIT, DBG_LOUD, (" FirmwareVersion(%#x), Signature(%#x)\n",
++ // Adapter->MgntInfo.FirmwareVersion, pFwHdr->Signature));
++
++ DBG_8192C("fw_ver=v%d, fw_subver=%d, sig=0x%x\n",
++ pHalData->FirmwareVersion, pHalData->FirmwareSubVersion, le16_to_cpu(pFwHdr->Signature)&0xFFF0);
++
++ if(IS_FW_HEADER_EXIST(pFwHdr))
++ {
++ //RT_TRACE(COMP_INIT, DBG_LOUD,("Shift 32 bytes for FW header!!\n"));
++ pFirmwareBuf = pFirmwareBuf + 32;
++ FirmwareLen = FirmwareLen -32;
++ }
++
++ // Suggested by Filen. If 8051 is running in RAM code, driver should inform Fw to reset by itself,
++ // or it will cause download Fw fail. 2010.02.01. by tynli.
++ if(rtw_read8(Adapter, REG_MCUFWDL)&BIT7) //8051 RAM code
++ {
++ rtl8192c_FirmwareSelfReset(Adapter);
++ rtw_write8(Adapter, REG_MCUFWDL, 0x00);
++ }
++
++
++ _FWDownloadEnable(Adapter, _TRUE);
++ while(1) {
++ u8 tmp8;
++ tmp8 = rtw_read8(Adapter, REG_MCUFWDL);
++
++ //reset the FWDL chksum
++ rtw_write8(Adapter, REG_MCUFWDL, tmp8|FWDL_ChkSum_rpt);
++
++ //tmp8 = rtw_read8(Adapter, REG_MCUFWDL);
++ //DBG_8192C("Before _WriteFW, REG_MCUFWDL:0x%02x, writeFW_retry:%u\n", tmp8, writeFW_retry);
++
++ rtStatus = _WriteFW(Adapter, pFirmwareBuf, FirmwareLen);
++
++ //tmp8 = rtw_read8(Adapter, REG_MCUFWDL);
++ //DBG_8192C("After _WriteFW, REG_MCUFWDL:0x%02x, rtStatus:%d\n", tmp8, rtStatus);
++
++ if(rtStatus == _SUCCESS || ++writeFW_retry>3)
++ break;
++ }
++ _FWDownloadEnable(Adapter, _FALSE);
++
++ if(_SUCCESS != rtStatus){
++ DBG_8192C("DL Firmware failed!\n");
++ goto Exit;
++ }
++
++ rtStatus = _FWFreeToGo(Adapter);
++ if(_SUCCESS != rtStatus){
++ DBG_8192C("DL Firmware failed!\n");
++ goto Exit;
++ }
++ //RT_TRACE(COMP_INIT, DBG_LOUD, (" Firmware is ready to run!\n"));
++
++Exit:
++
++ if(pFirmware) {
++ rtw_vmfree((u8*)pFirmware, sizeof(RT_FIRMWARE_92C));
++ }
++
++ //RT_TRACE(COMP_INIT, DBG_LOUD, (" <=== FirmwareDownload91C()\n"));
++ return rtStatus;
++
++}
++
++VOID
++InitializeFirmwareVars92C(
++ IN PADAPTER Adapter
++)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++
++ // Init Fw LPS related.
++ Adapter->pwrctrlpriv.bFwCurrentInPSMode = _FALSE;
++
++ //Init H2C counter. by tynli. 2009.12.09.
++ pHalData->LastHMEBoxNum = 0;
++}
++
++#ifdef CONFIG_WOWLAN
++//===========================================
++
++//
++// Description: Prepare some information to Fw for WoWLAN.
++// (1) Download wowlan Fw.
++// (2) Download RSVD page packets.
++// (3) Enable AP offload if needed.
++//
++// 2011.04.12 by tynli.
++//
++VOID
++SetFwRelatedForWoWLAN8192CU(
++ IN PADAPTER padapter,
++ IN u8 bHostIsGoingtoSleep
++)
++{
++ int status=_FAIL;
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++ u8 bRecover = _FALSE;
++
++ if(bHostIsGoingtoSleep)
++ {
++ //
++ // 1. Before WoWLAN we need to re-download WoWLAN Fw.
++ //
++ status = FirmwareDownload92C(padapter, bHostIsGoingtoSleep);
++ if(status != _SUCCESS)
++ {
++ DBG_8192C("ConfigFwRelatedForWoWLAN8192CU(): Re-Download Firmware failed!!\n");
++ return;
++ }
++ else
++ {
++ DBG_8192C("ConfigFwRelatedForWoWLAN8192CU(): Re-Download Firmware Success !!\n");
++ }
++
++ //
++ // 2. Re-Init the variables about Fw related setting.
++ //
++ InitializeFirmwareVars92C(padapter);
++
++
++ }
++}
++#endif // CONFIG_WOWLAN
++
++#ifdef CONFIG_BT_COEXIST
++static void _update_bt_param(_adapter *padapter)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++ struct btcoexist_priv *pbtpriv = &(pHalData->bt_coexist);
++ struct registry_priv *registry_par = &padapter->registrypriv;
++
++ if(2 != registry_par->bt_iso)
++ pbtpriv->BT_Ant_isolation = registry_par->bt_iso;// 0:Low, 1:High, 2:From Efuse
++
++ if(registry_par->bt_sco == 1) // 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter, 4.Busy, 5.OtherBusy
++ pbtpriv->BT_Service = BT_OtherAction;
++ else if(registry_par->bt_sco==2)
++ pbtpriv->BT_Service = BT_SCO;
++ else if(registry_par->bt_sco==4)
++ pbtpriv->BT_Service = BT_Busy;
++ else if(registry_par->bt_sco==5)
++ pbtpriv->BT_Service = BT_OtherBusy;
++ else
++ pbtpriv->BT_Service = BT_Idle;
++
++ pbtpriv->BT_Ampdu = registry_par->bt_ampdu;
++ pbtpriv->bCOBT = _TRUE;
++#if 1
++ DBG_8192C("BT Coexistance = %s\n", (pbtpriv->BT_Coexist==_TRUE)?"enable":"disable");
++ if(pbtpriv->BT_Coexist)
++ {
++ if(pbtpriv->BT_Ant_Num == Ant_x2)
++ {
++ DBG_8192C("BlueTooth BT_Ant_Num = Antx2\n");
++ }
++ else if(pbtpriv->BT_Ant_Num == Ant_x1)
++ {
++ DBG_8192C("BlueTooth BT_Ant_Num = Antx1\n");
++ }
++ switch(pbtpriv->BT_CoexistType)
++ {
++ case BT_2Wire:
++ DBG_8192C("BlueTooth BT_CoexistType = BT_2Wire\n");
++ break;
++ case BT_ISSC_3Wire:
++ DBG_8192C("BlueTooth BT_CoexistType = BT_ISSC_3Wire\n");
++ break;
++ case BT_Accel:
++ DBG_8192C("BlueTooth BT_CoexistType = BT_Accel\n");
++ break;
++ case BT_CSR_BC4:
++ DBG_8192C("BlueTooth BT_CoexistType = BT_CSR_BC4\n");
++ break;
++ case BT_RTL8756:
++ DBG_8192C("BlueTooth BT_CoexistType = BT_RTL8756\n");
++ break;
++ default:
++ DBG_8192C("BlueTooth BT_CoexistType = Unknown\n");
++ break;
++ }
++ DBG_8192C("BlueTooth BT_Ant_isolation = %d\n", pbtpriv->BT_Ant_isolation);
++
++
++ switch(pbtpriv->BT_Service)
++ {
++ case BT_OtherAction:
++ DBG_8192C("BlueTooth BT_Service = BT_OtherAction\n");
++ break;
++ case BT_SCO:
++ DBG_8192C("BlueTooth BT_Service = BT_SCO\n");
++ break;
++ case BT_Busy:
++ DBG_8192C("BlueTooth BT_Service = BT_Busy\n");
++ break;
++ case BT_OtherBusy:
++ DBG_8192C("BlueTooth BT_Service = BT_OtherBusy\n");
++ break;
++ default:
++ DBG_8192C("BlueTooth BT_Service = BT_Idle\n");
++ break;
++ }
++
++ DBG_8192C("BT_RadioSharedType = 0x%x\n", pbtpriv->BT_RadioSharedType);
++ }
++#endif
++
++}
++
++
++#define GET_BT_COEXIST(priv) (&priv->bt_coexist)
++
++void rtl8192c_ReadBluetoothCoexistInfo(
++ IN PADAPTER Adapter,
++ IN u8* PROMContent,
++ IN BOOLEAN AutoloadFail
++ )
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ struct btcoexist_priv *pbtpriv = &(pHalData->bt_coexist);
++ u8 rf_opt4;
++
++ if(AutoloadFail){
++ pbtpriv->BT_Coexist = _FALSE;
++ pbtpriv->BT_CoexistType= BT_2Wire;
++ pbtpriv->BT_Ant_Num = Ant_x2;
++ pbtpriv->BT_Ant_isolation= 0;
++ pbtpriv->BT_RadioSharedType = BT_Radio_Shared;
++ return;
++ }
++
++ pbtpriv->BT_Coexist = (((PROMContent[EEPROM_RF_OPT1]&BOARD_TYPE_NORMAL_MASK)>>5) == BOARD_USB_COMBO)?_TRUE:_FALSE; // bit [7:5]
++ rf_opt4 = PROMContent[EEPROM_RF_OPT4];
++ pbtpriv->BT_CoexistType = ((rf_opt4&0xe)>>1); // bit [3:1]
++ pbtpriv->BT_Ant_Num = (rf_opt4&0x1); // bit [0]
++ pbtpriv->BT_Ant_isolation = ((rf_opt4&0x10)>>4); // bit [4]
++ pbtpriv->BT_RadioSharedType = ((rf_opt4&0x20)>>5); // bit [5]
++
++ _update_bt_param(Adapter);
++
++}
++#endif
++
++VERSION_8192C
++rtl8192c_ReadChipVersion(
++ IN PADAPTER Adapter
++ )
++{
++ u32 value32;
++ //VERSION_8192C version;
++ u32 ChipVersion=0;
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++
++ value32 = rtw_read32(Adapter, REG_SYS_CFG);
++
++ if (value32 & TRP_VAUX_EN)
++ {
++#if 0
++ // Test chip.
++ if(IS_HARDWARE_TYPE_8723A(Adapter)) {
++ ChipVersion |= ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : 0);
++ ChipVersion |= ((value32 & BT_FUNC) ? CHIP_8723: 0); // RTL8723 with BT function.
++ }
++ else {
++ version = (value32 & TYPE_ID) ?VERSION_TEST_CHIP_92C :VERSION_TEST_CHIP_88C;
++ }
++#else
++ // tynli_test. 2011.01.10.
++ if(IS_HARDWARE_TYPE_8192C(Adapter))
++ {
++ ChipVersion = (value32 & TYPE_ID) ? VERSION_TEST_CHIP_92C : VERSION_TEST_CHIP_88C;
++ }
++ else
++ {
++ ChipVersion |= ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : 0);
++ ChipVersion |= ((value32 & BT_FUNC) ? CHIP_8723: 0); // RTL8723 with BT function.
++ }
++#endif
++ }
++ else
++ {
++#if 0
++ // Normal mass production chip.
++ ChipVersion = NORMAL_CHIP;
++#if !RTL8723_FPGA_TRUE_PHY_VERIFICATION
++ ChipVersion |= ((value32 & TYPE_ID) ? CHIP_92C : 0);
++#endif
++ ChipVersion |= ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : 0);
++ ChipVersion |= ((value32 & BT_FUNC) ? CHIP_8723: 0); // RTL8723 with BT function.
++ if(IS_8723_SERIES(ChipVersion))
++ {
++ if(IS_VENDOR_UMC(ChipVersion))
++ ChipVersion |= ((value32 & CHIP_VER_RTL_MASK) ? CHIP_VENDOR_UMC_B_CUT : 0);
++ }
++ else
++ {
++ // Mark out by tynli. UMC B-cut IC will not set the SYS_CFG[19] to UMC
++ // because we do not want the custmor to know. 2011.01.11.
++ //if(IS_VENDOR_UMC(ChipVersion))
++ {
++ // To check the value of B-cut. by tynli. 2011.01.11.
++ u1bTmp = (u1Byte)((value32 & CHIP_VER_RTL_MASK)>>12);
++ if(u1bTmp == 1)
++ { // B-cut
++ ChipVersion |= CHIP_VENDOR_UMC_B_CUT;
++ }
++ }
++ }
++#else
++ // Normal mass production chip.
++ ChipVersion = NORMAL_CHIP;
++//#if !RTL8723_FPGA_TRUE_PHY_VERIFICATION
++ ChipVersion |= ((value32 & TYPE_ID) ? RF_TYPE_2T2R : 0); //92c
++//#endif
++ ChipVersion |= ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : 0);
++ ChipVersion |= ((value32 & BT_FUNC) ? CHIP_8723: 0); // RTL8723 with BT function.
++ if(IS_HARDWARE_TYPE_8192C(Adapter))
++ {
++ // 88/92C UMC B-cut IC will not set the SYS_CFG[19] to UMC
++ // because we do not want the custmor to know. by tynli. 2011.01.17.
++ //MSG_8192C("mask result = 0x%x is_UMC %d chipversion 0x%x\n", (value32 & CHIP_VER_RTL_MASK), IS_CHIP_VENDOR_UMC(ChipVersion), ChipVersion);
++ if((!IS_CHIP_VENDOR_UMC(ChipVersion) )&& (value32 & CHIP_VER_RTL_MASK))
++ {
++ //MSG_8192C("chip mask result = 0x%x\n", ((value32 & CHIP_VER_RTL_MASK) | CHIP_VENDOR_UMC));
++ ChipVersion |= ((value32 & CHIP_VER_RTL_MASK) | CHIP_VENDOR_UMC); // IC version (CUT)
++ //MSG_8192C("chip version = 0x%x\n", ChipVersion);
++ }
++ }
++ else
++ {
++ if(IS_CHIP_VENDOR_UMC(ChipVersion))
++ ChipVersion |= ((value32 & CHIP_VER_RTL_MASK)); // IC version (CUT)
++ }
++
++ if(IS_92C_SERIAL(ChipVersion))
++ {
++ value32 = rtw_read32(Adapter, REG_HPON_FSM);
++ ChipVersion |= ((CHIP_BONDING_IDENTIFIER(value32) == CHIP_BONDING_92C_1T2R) ? RF_TYPE_1T2R : 0);
++ }
++ else if(IS_8723_SERIES(ChipVersion))
++ {
++ //RT_ASSERT(IS_HARDWARE_TYPE_8723A(Adapter), ("Incorrect chip version!!\n"));
++ value32 = rtw_read32(Adapter, REG_GPIO_OUTSTS);
++ ChipVersion |= ((value32 & RF_RL_ID)>>20); //ROM code version.
++ }
++#endif
++
++ }
++
++ //version = (VERSION_8192C)ChipVersion;
++
++ // For multi-function consideration. Added by Roger, 2010.10.06.
++ if(IS_8723_SERIES(ChipVersion))
++ {
++ pHalData->MultiFunc = RT_MULTI_FUNC_NONE;
++ value32 = rtw_read32(Adapter, REG_MULTI_FUNC_CTRL);
++ pHalData->MultiFunc =(RT_MULTI_FUNC) (pHalData->MultiFunc| ((value32 & WL_FUNC_EN) ? RT_MULTI_FUNC_WIFI : 0) );
++ pHalData->MultiFunc =(RT_MULTI_FUNC) (pHalData->MultiFunc| ((value32 & BT_FUNC_EN) ? RT_MULTI_FUNC_BT : 0) );
++ pHalData->MultiFunc =(RT_MULTI_FUNC) (pHalData->MultiFunc| ((value32 & GPS_FUNC_EN) ? RT_MULTI_FUNC_GPS : 0) );
++ pHalData->PolarityCtl = ((value32 & WL_HWPDN_SL) ? RT_POLARITY_HIGH_ACT : RT_POLARITY_LOW_ACT);
++ //MSG_8192C("ReadChipVersion(): MultiFunc(%x), PolarityCtl(%x) \n", pHalData->MultiFunc, pHalData->PolarityCtl);
++
++ //For regulator mode. by tynli. 2011.01.14
++ pHalData->RegulatorMode = ((value32 & TRP_BT_EN) ? RT_LDO_REGULATOR : RT_SWITCHING_REGULATOR);
++ //MSG_8192C("ReadChipVersion(): RegulatorMode(%x) \n", pHalData->RegulatorMode);
++ }
++
++//#if DBG
++#if 1
++ switch(ChipVersion)
++ {
++ case VERSION_NORMAL_TSMC_CHIP_92C_1T2R:
++ MSG_8192C("Chip Version ID: VERSION_NORMAL_TSMC_CHIP_92C_1T2R.\n");
++ break;
++ case VERSION_NORMAL_TSMC_CHIP_92C:
++ MSG_8192C("Chip Version ID: VERSION_NORMAL_TSMC_CHIP_92C.\n");
++ break;
++ case VERSION_NORMAL_TSMC_CHIP_88C:
++ MSG_8192C("Chip Version ID: VERSION_NORMAL_TSMC_CHIP_88C.\n");
++ break;
++ case VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT:
++ MSG_8192C("Chip Version ID: VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT.\n");
++ break;
++ case VERSION_NORMAL_UMC_CHIP_92C_A_CUT:
++ MSG_8192C("Chip Version ID: VERSION_NORMAL_UMC_CHIP_92C_A_CUT.\n");
++ break;
++ case VERSION_NORMAL_UMC_CHIP_88C_A_CUT:
++ MSG_8192C("Chip Version ID: VERSION_NORMAL_UMC_CHIP_88C_A_CUT.\n");
++ break;
++ case VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT:
++ MSG_8192C("Chip Version ID: VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT.\n");
++ break;
++ case VERSION_NORMAL_UMC_CHIP_92C_B_CUT:
++ MSG_8192C("Chip Version ID: VERSION_NORMAL_UMC_CHIP_92C_B_CUT.\n");
++ break;
++ case VERSION_NORMAL_UMC_CHIP_88C_B_CUT:
++ MSG_8192C("Chip Version ID: VERSION_NORMAL_UMC_CHIP_88C_B_CUT.\n");
++ break;
++ case VERSION_TEST_CHIP_92C:
++ MSG_8192C("Chip Version ID: VERSION_TEST_CHIP_92C.\n");
++ break;
++ case VERSION_TEST_CHIP_88C:
++ MSG_8192C("Chip Version ID: VERSION_TEST_CHIP_88C.\n");
++ break;
++ case VERSION_TEST_UMC_CHIP_8723:
++ MSG_8192C("Chip Version ID: VERSION_TEST_UMC_CHIP_8723.\n");
++ break;
++ case VERSION_NORMAL_UMC_CHIP_8723_1T1R_A_CUT:
++ MSG_8192C("Chip Version ID: VERSION_NORMA_UMC_CHIP_8723_1T1R_A_CUT.\n");
++ break;
++ case VERSION_NORMAL_UMC_CHIP_8723_1T1R_B_CUT:
++ MSG_8192C("Chip Version ID: VERSION_NORMA_UMC_CHIP_8723_1T1R_B_CUT.\n");
++ break;
++ default:
++ MSG_8192C("Chip Version ID: ???????????????.\n");
++ break;
++ }
++#endif
++
++ pHalData->VersionID = ChipVersion;
++
++ if(IS_1T2R(ChipVersion))
++ pHalData->rf_type = RF_1T2R;
++ else if(IS_2T2R(ChipVersion))
++ pHalData->rf_type = RF_2T2R;
++ else if(IS_8723_SERIES(ChipVersion))
++ pHalData->rf_type = RF_1T1R;
++ else
++ pHalData->rf_type = RF_1T1R;
++
++ MSG_8192C("RF_Type is %x!!\n", pHalData->rf_type);
++
++ return ChipVersion;
++}
++
++void
++rtl8192c_EfuseParseChnlPlan(
++ IN PADAPTER padapter,
++ IN u8* hwinfo,
++ IN BOOLEAN AutoLoadFail
++ )
++{
++ padapter->mlmepriv.ChannelPlan = hal_com_get_channel_plan(
++ padapter
++ , hwinfo?hwinfo[EEPROM_CHANNEL_PLAN]:0xFF
++ , padapter->registrypriv.channel_plan
++ , RT_CHANNEL_DOMAIN_WORLD_WIDE_13
++ , AutoLoadFail
++ );
++
++ DBG_871X("mlmepriv.ChannelPlan = 0x%02x\n", padapter->mlmepriv.ChannelPlan);
++}
++
++u8 GetEEPROMSize8192C(PADAPTER Adapter)
++{
++ u8 size = 0;
++ u32 curRCR;
++
++ curRCR = rtw_read16(Adapter, REG_9346CR);
++ size = (curRCR & BOOT_FROM_EEPROM) ? 6 : 4; // 6: EEPROM used is 93C46, 4: boot from E-Fuse.
++
++ MSG_8192C("EEPROM type is %s\n", size==4 ? "E-FUSE" : "93C46");
++
++ return size;
++}
++
++void rtl8192c_free_hal_data(_adapter * padapter)
++{
++_func_enter_;
++
++ DBG_8192C("=====> rtl8192c_free_hal_data =====\n");
++
++ if(padapter->HalData)
++ rtw_mfree(padapter->HalData, sizeof(HAL_DATA_TYPE));
++ DBG_8192C("<===== rtl8192c_free_hal_data =====\n");
++
++_func_exit_;
++}
++
++//===========================================================
++// Efuse related code
++//===========================================================
++enum{
++ VOLTAGE_V25 = 0x03,
++ LDOE25_SHIFT = 28 ,
++ };
++
++static VOID
++hal_EfusePowerSwitch_RTL8192C(
++ IN PADAPTER pAdapter,
++ IN u8 bWrite,
++ IN u8 PwrState)
++{
++ u8 tempval;
++ u16 tmpV16;
++
++ if (PwrState == _TRUE)
++ {
++ // 1.2V Power: From VDDON with Power Cut(0x0000h[15]), defualt valid
++ tmpV16 = rtw_read16(pAdapter,REG_SYS_ISO_CTRL);
++ if( ! (tmpV16 & PWC_EV12V ) ){
++ tmpV16 |= PWC_EV12V ;
++ rtw_write16(pAdapter,REG_SYS_ISO_CTRL,tmpV16);
++ }
++ // Reset: 0x0000h[28], default valid
++ tmpV16 = rtw_read16(pAdapter,REG_SYS_FUNC_EN);
++ if( !(tmpV16 & FEN_ELDR) ){
++ tmpV16 |= FEN_ELDR ;
++ rtw_write16(pAdapter,REG_SYS_FUNC_EN,tmpV16);
++ }
++
++ // Clock: Gated(0x0008h[5]) 8M(0x0008h[1]) clock from ANA, default valid
++ tmpV16 = rtw_read16(pAdapter,REG_SYS_CLKR);
++ if( (!(tmpV16 & LOADER_CLK_EN) ) ||(!(tmpV16 & ANA8M) ) ){
++ tmpV16 |= (LOADER_CLK_EN |ANA8M ) ;
++ rtw_write16(pAdapter,REG_SYS_CLKR,tmpV16);
++ }
++
++ if(bWrite == _TRUE)
++ {
++ // Enable LDO 2.5V before read/write action
++ tempval = rtw_read8(pAdapter, EFUSE_TEST+3);
++ tempval &= 0x0F;
++ tempval |= (VOLTAGE_V25 << 4);
++ rtw_write8(pAdapter, EFUSE_TEST+3, (tempval | 0x80));
++ }
++ }
++ else
++ {
++ if(bWrite == _TRUE){
++ // Disable LDO 2.5V after read/write action
++ tempval = rtw_read8(pAdapter, EFUSE_TEST+3);
++ rtw_write8(pAdapter, EFUSE_TEST+3, (tempval & 0x7F));
++ }
++ }
++}
++
++static VOID
++hal_EfusePowerSwitch_RTL8723(
++ IN PADAPTER pAdapter,
++ IN u8 bWrite,
++ IN u8 PwrState)
++{
++ u8 tempval;
++ u16 tmpV16;
++
++ if (PwrState == _TRUE)
++ {
++ rtw_write8(pAdapter, REG_EFUSE_ACCESS, EFUSE_ACCESS_ON);
++
++ // 1.2V Power: From VDDON with Power Cut(0x0000h[15]), defualt valid
++ tmpV16 = rtw_read16(pAdapter,REG_SYS_ISO_CTRL);
++ if( ! (tmpV16 & PWC_EV12V ) ){
++ tmpV16 |= PWC_EV12V ;
++ rtw_write16(pAdapter,REG_SYS_ISO_CTRL,tmpV16);
++ }
++ // Reset: 0x0000h[28], default valid
++ tmpV16 = rtw_read16(pAdapter,REG_SYS_FUNC_EN);
++ if( !(tmpV16 & FEN_ELDR) ){
++ tmpV16 |= FEN_ELDR ;
++ rtw_write16(pAdapter,REG_SYS_FUNC_EN,tmpV16);
++ }
++
++ // Clock: Gated(0x0008h[5]) 8M(0x0008h[1]) clock from ANA, default valid
++ tmpV16 = rtw_read16(pAdapter,REG_SYS_CLKR);
++ if( (!(tmpV16 & LOADER_CLK_EN) ) ||(!(tmpV16 & ANA8M) ) ){
++ tmpV16 |= (LOADER_CLK_EN |ANA8M ) ;
++ rtw_write16(pAdapter,REG_SYS_CLKR,tmpV16);
++ }
++
++ if(bWrite == _TRUE)
++ {
++ // Enable LDO 2.5V before read/write action
++ tempval = rtw_read8(pAdapter, EFUSE_TEST+3);
++ tempval &= 0x0F;
++ tempval |= (VOLTAGE_V25 << 4);
++ rtw_write8(pAdapter, EFUSE_TEST+3, (tempval | 0x80));
++ }
++ }
++ else
++ {
++ rtw_write8(pAdapter, REG_EFUSE_ACCESS, EFUSE_ACCESS_OFF);
++
++ if(bWrite == _TRUE){
++ // Disable LDO 2.5V after read/write action
++ tempval = rtw_read8(pAdapter, EFUSE_TEST+3);
++ rtw_write8(pAdapter, EFUSE_TEST+3, (tempval & 0x7F));
++ }
++ }
++}
++
++static VOID
++rtl8192c_EfusePowerSwitch(
++ IN PADAPTER pAdapter,
++ IN u8 bWrite,
++ IN u8 PwrState)
++{
++ if(IS_HARDWARE_TYPE_8192C(pAdapter))
++ {
++ hal_EfusePowerSwitch_RTL8192C(pAdapter, bWrite, PwrState);
++ }
++ else if(IS_HARDWARE_TYPE_8723A(pAdapter))
++ {
++ hal_EfusePowerSwitch_RTL8723(pAdapter, bWrite, PwrState);
++ }
++}
++
++static VOID
++ReadEFuse_RTL8192C(
++ PADAPTER Adapter,
++ u16 _offset,
++ u16 _size_byte,
++ u8 *pbuf,
++ IN BOOLEAN bPseudoTest
++ )
++{
++ u8 efuseTbl[EFUSE_MAP_LEN];
++ u8 rtemp8[1];
++ u16 eFuse_Addr = 0;
++ u8 offset, wren;
++ u16 i, j;
++ u16 eFuseWord[EFUSE_MAX_SECTION][EFUSE_MAX_WORD_UNIT];
++ u16 efuse_utilized = 0;
++ u8 efuse_usage = 0;
++
++ //
++ // Do NOT excess total size of EFuse table. Added by Roger, 2008.11.10.
++ //
++ if((_offset + _size_byte)>EFUSE_MAP_LEN)
++ {// total E-Fuse table is 128bytes
++ //DBG_8192C("ReadEFuse_RTL8192C(): Invalid offset(%#x) with read bytes(%#x)!!\n",_offset, _size_byte);
++ return;
++ }
++
++ // 0. Refresh efuse init map as all oxFF.
++ for (i = 0; i < EFUSE_MAX_SECTION; i++)
++ for (j = 0; j < EFUSE_MAX_WORD_UNIT; j++)
++ eFuseWord[i][j] = 0xFFFF;
++
++
++ //
++ // 1. Read the first byte to check if efuse is empty!!!
++ //
++ //
++ ReadEFuseByte(Adapter, eFuse_Addr, rtemp8, bPseudoTest);
++ if(*rtemp8 != 0xFF)
++ {
++ efuse_utilized++;
++ //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Addr=%d\n", eFuse_Addr));
++ eFuse_Addr++;
++ }
++
++ //
++ // 2. Read real efuse content. Filter PG header and every section data.
++ //
++ while((*rtemp8 != 0xFF) && (eFuse_Addr < EFUSE_REAL_CONTENT_LEN))
++ {
++ // Check PG header for section num.
++ offset = ((*rtemp8 >> 4) & 0x0f);
++
++ if(offset < EFUSE_MAX_SECTION)
++ {
++ // Get word enable value from PG header
++ wren = (*rtemp8 & 0x0f);
++ //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Offset-%d Worden=%x\n", offset, wren));
++
++ for(i=0; i<EFUSE_MAX_WORD_UNIT; i++)
++ {
++ // Check word enable condition in the section
++ if(!(wren & 0x01))
++ {
++ //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Addr=%d\n", eFuse_Addr));
++ ReadEFuseByte(Adapter, eFuse_Addr, rtemp8, bPseudoTest); eFuse_Addr++;
++ efuse_utilized++;
++ eFuseWord[offset][i] = (*rtemp8 & 0xff);
++
++
++ if(eFuse_Addr >= EFUSE_REAL_CONTENT_LEN)
++ break;
++
++ //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Addr=%d\n", eFuse_Addr));
++ ReadEFuseByte(Adapter, eFuse_Addr, rtemp8, bPseudoTest); eFuse_Addr++;
++ efuse_utilized++;
++ eFuseWord[offset][i] |= (((u16)*rtemp8 << 8) & 0xff00);
++
++ if(eFuse_Addr >= EFUSE_REAL_CONTENT_LEN)
++ break;
++ }
++
++ wren >>= 1;
++
++ }
++ }
++
++ //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Addr=%d\n", eFuse_Addr));
++ // Read next PG header
++ ReadEFuseByte(Adapter, eFuse_Addr, rtemp8, bPseudoTest);
++ if(*rtemp8 != 0xFF && (eFuse_Addr < 512))
++ {
++ efuse_utilized++;
++ eFuse_Addr++;
++ }
++ }
++
++ //
++ // 3. Collect 16 sections and 4 word unit into Efuse map.
++ //
++ for(i=0; i<EFUSE_MAX_SECTION; i++)
++ {
++ for(j=0; j<EFUSE_MAX_WORD_UNIT; j++)
++ {
++ efuseTbl[(i*8)+(j*2)]=(eFuseWord[i][j] & 0xff);
++ efuseTbl[(i*8)+((j*2)+1)]=((eFuseWord[i][j] >> 8) & 0xff);
++ }
++ }
++
++ //
++ // 4. Copy from Efuse map to output pointer memory!!!
++ //
++ for(i=0; i<_size_byte; i++)
++ {
++ pbuf[i] = efuseTbl[_offset+i];
++ }
++
++ //
++ // 5. Calculate Efuse utilization.
++ //
++ efuse_usage = (u8)((efuse_utilized*100)/EFUSE_REAL_CONTENT_LEN);
++ rtw_hal_set_hwreg(Adapter, HW_VAR_EFUSE_BYTES, (u8 *)&efuse_utilized);
++ //rtw_hal_set_hwreg(Adapter, HW_VAR_EFUSE_USAGE, (pu1Byte)&efuse_usage);
++}
++
++static VOID
++ReadEFuse_RTL8723(
++ PADAPTER Adapter,
++ u16 _offset,
++ u16 _size_byte,
++ u8 *pbuf,
++ IN BOOLEAN bPseudoTest
++ )
++{
++ u8 efuseTbl[EFUSE_MAP_LEN_8723];
++ u16 eFuse_Addr = 0;
++ u8 offset = 0, wden = 0;
++ u16 i, j;
++ u16 eFuseWord[EFUSE_MAX_SECTION_8723][EFUSE_MAX_WORD_UNIT];
++ u16 efuse_utilized = 0;
++ u8 efuse_usage = 0;
++ u8 offset_2_0=0;
++ u8 efuseHeader=0, efuseExtHdr=0, efuseData=0;
++ //
++ // Do NOT excess total size of EFuse table. Added by Roger, 2008.11.10.
++ //
++ if((_offset + _size_byte)>EFUSE_MAP_LEN_8723)
++ {
++ //RT_TRACE(COMP_EFUSE, DBG_LOUD, ("ReadEFuse_RTL8723(): Invalid offset(%#x) with read bytes(%#x)!!\n",_offset, _size_byte));
++ return;
++ }
++
++ // 0. Refresh efuse init map as all oxFF.
++ for (i = 0; i < EFUSE_MAX_SECTION_8723; i++)
++ for (j = 0; j < EFUSE_MAX_WORD_UNIT; j++)
++ eFuseWord[i][j] = 0xFFFF;
++
++ //
++ // 1. Read the first byte to check if efuse is empty!!!
++ //
++ //
++ ReadEFuseByte(Adapter, eFuse_Addr++, &efuseHeader, bPseudoTest);
++
++ if(efuseHeader != 0xFF)
++ {
++ efuse_utilized++;
++ }
++ else
++ {
++ //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("EFUSE is empty\n"));
++ return;
++ }
++
++
++ //
++ // 2. Read real efuse content. Filter PG header and every section data.
++ //
++ while((efuseHeader != 0xFF) && AVAILABLE_EFUSE_ADDR(eFuse_Addr))
++ {
++ //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("efuse[%d]=%x\n", eFuse_Addr-1, efuseHeader));
++
++ // Check PG header for section num.
++ if(EXT_HEADER(efuseHeader)) //extended header
++ {
++ offset_2_0 = GET_HDR_OFFSET_2_0(efuseHeader);
++ //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("extended header offset_2_0=%x\n", offset_2_0));
++
++ ReadEFuseByte(Adapter, eFuse_Addr++, &efuseExtHdr, bPseudoTest);
++
++ //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("efuse[%d]=%x\n", eFuse_Addr-1, efuseExtHdr));
++
++ if(efuseExtHdr != 0xff)
++ {
++ efuse_utilized++;
++ if(ALL_WORDS_DISABLED(efuseExtHdr))
++ {
++ ReadEFuseByte(Adapter, eFuse_Addr++, &efuseHeader, bPseudoTest);
++ if(efuseHeader != 0xff)
++ {
++ efuse_utilized++;
++ }
++ continue;
++ }
++ else
++ {
++ offset = ((efuseExtHdr & 0xF0) >> 1) | offset_2_0;
++ wden = (efuseExtHdr & 0x0F);
++ }
++ }
++ else
++ {
++ //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Error condition, extended = 0xff\n"));
++ // We should handle this condition.
++ }
++ }
++ else
++ {
++ offset = ((efuseHeader >> 4) & 0x0f);
++ wden = (efuseHeader & 0x0f);
++ }
++
++ if(offset < EFUSE_MAX_SECTION_8723)
++ {
++ // Get word enable value from PG header
++ //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Offset-%d Worden=%x\n", offset, wden));
++
++ for(i=0; i<EFUSE_MAX_WORD_UNIT; i++)
++ {
++ // Check word enable condition in the section
++ if(!(wden & (0x01<<i)))
++ {
++ ReadEFuseByte(Adapter, eFuse_Addr++, &efuseData, bPseudoTest);
++ //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("efuse[%d]=%x\n", eFuse_Addr-1, efuseData));
++ efuse_utilized++;
++ eFuseWord[offset][i] = (efuseData & 0xff);
++
++ if(!AVAILABLE_EFUSE_ADDR(eFuse_Addr))
++ break;
++
++ ReadEFuseByte(Adapter, eFuse_Addr++, &efuseData, bPseudoTest);
++ //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("efuse[%d]=%x\n", eFuse_Addr-1, efuseData));
++ efuse_utilized++;
++ eFuseWord[offset][i] |= (((u16)efuseData << 8) & 0xff00);
++
++ if(!AVAILABLE_EFUSE_ADDR(eFuse_Addr))
++ break;
++ }
++ }
++ }
++
++ // Read next PG header
++ ReadEFuseByte(Adapter, eFuse_Addr++, &efuseHeader, bPseudoTest);
++
++ if(efuseHeader != 0xFF)
++ {
++ efuse_utilized++;
++ }
++ }
++
++ //
++ // 3. Collect 16 sections and 4 word unit into Efuse map.
++ //
++ for(i=0; i<EFUSE_MAX_SECTION_8723; i++)
++ {
++ for(j=0; j<EFUSE_MAX_WORD_UNIT; j++)
++ {
++ efuseTbl[(i*8)+(j*2)]=(eFuseWord[i][j] & 0xff);
++ efuseTbl[(i*8)+((j*2)+1)]=((eFuseWord[i][j] >> 8) & 0xff);
++ }
++ }
++
++ //
++ // 4. Copy from Efuse map to output pointer memory!!!
++ //
++ for(i=0; i<_size_byte; i++)
++ {
++ pbuf[i] = efuseTbl[_offset+i];
++ }
++
++ //
++ // 5. Calculate Efuse utilization.
++ //
++ efuse_usage = (u8)((efuse_utilized*100)/EFUSE_REAL_CONTENT_LEN);
++ rtw_hal_set_hwreg(Adapter, HW_VAR_EFUSE_BYTES, (u8 *)&efuse_utilized);
++ //rtw_hal_set_hwreg(Adapter, HW_VAR_EFUSE_USAGE, (pu1Byte)&efuse_usage);
++}
++
++static BOOLEAN
++Hal_EfuseSwitchToBank(
++ IN PADAPTER pAdapter,
++ IN u8 bank,
++ IN BOOLEAN bPseudoTest
++ )
++{
++ BOOLEAN bRet = _FALSE;
++ u32 value32=0;
++
++ //RTPRINT(FEEPROM, EFUSE_PG, ("Efuse switch bank to %d\n", bank));
++ if(bPseudoTest)
++ {
++ fakeEfuseBank = bank;
++ bRet = _TRUE;
++ }
++ else
++ {
++ if(IS_HARDWARE_TYPE_8723A(pAdapter) &&
++ INCLUDE_MULTI_FUNC_BT(pAdapter))
++ {
++ value32 = rtw_read32(pAdapter, EFUSE_TEST);
++ bRet = _TRUE;
++ switch(bank)
++ {
++ case 0:
++ value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0);
++ break;
++ case 1:
++ value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_0);
++ break;
++ case 2:
++ value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_1);
++ break;
++ case 3:
++ value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_2);
++ break;
++ default:
++ value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0);
++ bRet = _FALSE;
++ break;
++ }
++ rtw_write32(pAdapter, EFUSE_TEST, value32);
++ }
++ else
++ bRet = _TRUE;
++ }
++ return bRet;
++}
++
++static VOID
++ReadEFuse_BT(
++ PADAPTER Adapter,
++ u16 _offset,
++ u16 _size_byte,
++ u8 *pbuf,
++ IN BOOLEAN bPseudoTest
++ )
++{
++ u8 *efuseTbl;
++ u16 eFuse_Addr = 0;
++ u8 offset = 0, wden = 0;
++ u16 i, j;
++ u16 **eFuseWord;
++ u16 efuse_utilized = 0;
++ u8 efuse_usage = 0;
++ u8 offset_2_0=0;
++ u8 efuseHeader=0, efuseExtHdr=0, efuseData=0;
++ u8 bank=0;
++ BOOLEAN bCheckNextBank=_FALSE;
++
++ efuseTbl = rtw_malloc(EFUSE_BT_MAP_LEN);
++ if(efuseTbl == NULL){
++ DBG_8192C("efuseTbl malloc fail !\n");
++ return;
++ }
++
++ eFuseWord = (u16 **)rtw_zmalloc(sizeof(u16 *)*EFUSE_BT_MAX_SECTION);
++ if(eFuseWord == NULL){
++ DBG_8192C("eFuseWord malloc fail !\n");
++ return;
++ }
++ else{
++ for(i=0;i<EFUSE_BT_MAX_SECTION;i++){
++ eFuseWord[i]= (u16 *)rtw_zmalloc(sizeof(u16)*EFUSE_MAX_WORD_UNIT);
++ if(eFuseWord[i]==NULL){
++ DBG_8192C("eFuseWord[] malloc fail !\n");
++ return;
++ }
++ }
++ }
++
++ //
++ // Do NOT excess total size of EFuse table. Added by Roger, 2008.11.10.
++ //
++ if((_offset + _size_byte)>EFUSE_BT_MAP_LEN)
++ {
++ //RT_TRACE(COMP_EFUSE, DBG_LOUD, ("ReadEFuse_BT(): Invalid offset(%#x) with read bytes(%#x)!!\n",_offset, _size_byte));
++ return;
++ }
++
++ // 0. Refresh efuse init map as all oxFF.
++ for (i = 0; i < EFUSE_BT_MAX_SECTION; i++)
++ for (j = 0; j < EFUSE_MAX_WORD_UNIT; j++)
++ eFuseWord[i][j] = 0xFFFF;
++
++ for(bank=1; bank<EFUSE_MAX_BANK; bank++)
++ {
++ if(!Hal_EfuseSwitchToBank(Adapter, bank, bPseudoTest))
++ {
++ //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Hal_EfuseSwitchToBank() Fail!!\n"));
++ return;
++ }
++ eFuse_Addr = 0;
++ //
++ // 1. Read the first byte to check if efuse is empty!!!
++ //
++ ReadEFuseByte(Adapter, eFuse_Addr++, &efuseHeader, bPseudoTest);
++
++ if(efuseHeader != 0xFF)
++ {
++ efuse_utilized++;
++ }
++ else
++ {
++ //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("EFUSE is empty\n"));
++ return;
++ }
++ //
++ // 2. Read real efuse content. Filter PG header and every section data.
++ //
++ while((efuseHeader != 0xFF) && AVAILABLE_EFUSE_ADDR(eFuse_Addr))
++ {
++ //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("efuse[%d]=0x%02x (header)\n", (((bank-1)*EFUSE_REAL_CONTENT_LEN)+eFuse_Addr-1), efuseHeader));
++
++ // Check PG header for section num.
++ if(EXT_HEADER(efuseHeader)) //extended header
++ {
++ offset_2_0 = GET_HDR_OFFSET_2_0(efuseHeader);
++ //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("extended header offset_2_0=%x\n", offset_2_0));
++
++ ReadEFuseByte(Adapter, eFuse_Addr++, &efuseExtHdr, bPseudoTest);
++
++ //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("efuse[%d]=0x%02x (ext header)\n", (((bank-1)*EFUSE_REAL_CONTENT_LEN)+eFuse_Addr-1), efuseExtHdr));
++
++ if(efuseExtHdr != 0xff)
++ {
++ efuse_utilized++;
++ if(ALL_WORDS_DISABLED(efuseExtHdr))
++ {
++ ReadEFuseByte(Adapter, eFuse_Addr++, &efuseHeader, bPseudoTest);
++ if(efuseHeader != 0xff)
++ {
++ efuse_utilized++;
++ }
++ continue;
++ }
++ else
++ {
++ offset = ((efuseExtHdr & 0xF0) >> 1) | offset_2_0;
++ wden = (efuseExtHdr & 0x0F);
++ }
++ }
++ else
++ {
++ //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Error condition, extended = 0xff\n"));
++ // We should handle this condition.
++ }
++ }
++ else
++ {
++ offset = ((efuseHeader >> 4) & 0x0f);
++ wden = (efuseHeader & 0x0f);
++ }
++
++ if(offset < EFUSE_BT_MAX_SECTION)
++ {
++ // Get word enable value from PG header
++ //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Offset-%d Worden=%x\n", offset, wden));
++
++ for(i=0; i<EFUSE_MAX_WORD_UNIT; i++)
++ {
++ // Check word enable condition in the section
++ if(!(wden & (0x01<<i)))
++ {
++ ReadEFuseByte(Adapter, eFuse_Addr++, &efuseData, bPseudoTest);
++ //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("efuse[%d]=0x%02x\n", (((bank-1)*EFUSE_REAL_CONTENT_LEN)+eFuse_Addr-1), efuseData));
++ efuse_utilized++;
++ eFuseWord[offset][i] = (efuseData & 0xff);
++
++ if(!AVAILABLE_EFUSE_ADDR(eFuse_Addr))
++ break;
++
++ ReadEFuseByte(Adapter, eFuse_Addr++, &efuseData, bPseudoTest);
++ //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("efuse[%d]=0x%02x\n", (((bank-1)*EFUSE_REAL_CONTENT_LEN)+eFuse_Addr-1), efuseData));
++ efuse_utilized++;
++ eFuseWord[offset][i] |= (((u16)efuseData << 8) & 0xff00);
++
++ if(!AVAILABLE_EFUSE_ADDR(eFuse_Addr))
++ break;
++ }
++ }
++ }
++
++ // Read next PG header
++ ReadEFuseByte(Adapter, eFuse_Addr++, &efuseHeader, bPseudoTest);
++
++ if(efuseHeader != 0xFF)
++ {
++ efuse_utilized++;
++ }
++ else
++ {
++ if((eFuse_Addr + EFUSE_PROTECT_BYTES_BANK) >= EFUSE_REAL_CONTENT_LEN)
++ bCheckNextBank = _TRUE;
++ else
++ bCheckNextBank = _FALSE;
++ }
++ }
++ if(!bCheckNextBank)
++ {
++ //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Stop to check next bank\n"));
++ break;
++ }
++ }
++
++ // switch bank back to bank 0 for later BT and wifi use.
++ Hal_EfuseSwitchToBank(Adapter, 0, bPseudoTest);
++
++ //
++ // 3. Collect 16 sections and 4 word unit into Efuse map.
++ //
++ for(i=0; i<EFUSE_BT_MAX_SECTION; i++)
++ {
++ for(j=0; j<EFUSE_MAX_WORD_UNIT; j++)
++ {
++ efuseTbl[(i*8)+(j*2)]=(eFuseWord[i][j] & 0xff);
++ efuseTbl[(i*8)+((j*2)+1)]=((eFuseWord[i][j] >> 8) & 0xff);
++ }
++ }
++
++ //
++ // 4. Copy from Efuse map to output pointer memory!!!
++ //
++ for(i=0; i<_size_byte; i++)
++ {
++ pbuf[i] = efuseTbl[_offset+i];
++ }
++
++ //
++ // 5. Calculate Efuse utilization.
++ //
++ efuse_usage = (u8)((efuse_utilized*100)/EFUSE_BT_REAL_CONTENT_LEN);
++ if(bPseudoTest)
++ {
++ fakeBTEfuseUsedBytes = (EFUSE_REAL_CONTENT_LEN*(bank-1))+eFuse_Addr-1;
++ }
++ else
++ {
++ BTEfuseUsedBytes = (EFUSE_REAL_CONTENT_LEN*(bank-1))+eFuse_Addr-1;
++ }
++
++ for(i=0;i<EFUSE_BT_MAX_SECTION;i++)
++ rtw_mfree((u8 *)eFuseWord[i], sizeof(u16)*EFUSE_MAX_WORD_UNIT);
++ rtw_mfree((u8 *)eFuseWord, sizeof(u16 *)*EFUSE_BT_MAX_SECTION);
++ rtw_mfree(efuseTbl, EFUSE_BT_MAP_LEN);
++}
++
++
++static VOID
++ReadEFuseByIC(
++ PADAPTER Adapter,
++ u8 efuseType,
++ u16 _offset,
++ u16 _size_byte,
++ u8 *pbuf,
++ IN BOOLEAN bPseudoTest
++ )
++{
++ if(efuseType == EFUSE_WIFI)
++ {
++ if(IS_HARDWARE_TYPE_8192C(Adapter))
++ {
++ ReadEFuse_RTL8192C(Adapter, _offset, _size_byte, pbuf, bPseudoTest);
++ }
++ else if(IS_HARDWARE_TYPE_8723A(Adapter))
++ {
++ ReadEFuse_RTL8723(Adapter, _offset, _size_byte, pbuf, bPseudoTest);
++ }
++ }
++ else
++ ReadEFuse_BT(Adapter, _offset, _size_byte, pbuf, bPseudoTest);
++}
++
++static VOID
++ReadEFuse_Pseudo(
++ PADAPTER Adapter,
++ u8 efuseType,
++ u16 _offset,
++ u16 _size_byte,
++ u8 *pbuf,
++ IN BOOLEAN bPseudoTest
++ )
++{
++ if(efuseType == EFUSE_WIFI)
++ ReadEFuse_RTL8723(Adapter, _offset, _size_byte, pbuf, bPseudoTest);
++ else
++ ReadEFuse_BT(Adapter, _offset, _size_byte, pbuf, bPseudoTest);
++}
++
++static VOID
++rtl8192c_ReadEFuse(
++ PADAPTER Adapter,
++ u8 efuseType,
++ u16 _offset,
++ u16 _size_byte,
++ u8 *pbuf,
++ IN BOOLEAN bPseudoTest
++ )
++{
++ if(bPseudoTest)
++ {
++ ReadEFuse_Pseudo(Adapter, efuseType, _offset, _size_byte, pbuf, bPseudoTest);
++ }
++ else
++ {
++ ReadEFuseByIC(Adapter, efuseType, _offset, _size_byte, pbuf, bPseudoTest);
++ }
++}
++
++static VOID
++Hal_EFUSEGetEfuseDefinition(
++ IN PADAPTER pAdapter,
++ IN u8 efuseType,
++ IN u8 type,
++ OUT PVOID *pOut
++ )
++{
++ switch(type)
++ {
++ case TYPE_EFUSE_MAX_SECTION:
++ {
++ u8 *pMax_section;
++ pMax_section = (u8 *)pOut;
++
++ if(efuseType == EFUSE_WIFI)
++ {
++ if(IS_HARDWARE_TYPE_8192C(pAdapter))
++ {
++ *pMax_section = EFUSE_MAX_SECTION;
++ }
++ else if(IS_HARDWARE_TYPE_8723A(pAdapter))
++ {
++ *pMax_section = EFUSE_MAX_SECTION_8723;
++ }
++ }
++ else
++ *pMax_section = EFUSE_BT_MAX_SECTION;
++ }
++ break;
++ case TYPE_EFUSE_REAL_CONTENT_LEN:
++ {
++ u16 *pu2Tmp;
++ pu2Tmp = (u16 *)pOut;
++ if(efuseType == EFUSE_WIFI)
++ *pu2Tmp = EFUSE_REAL_CONTENT_LEN;
++ else
++ *pu2Tmp = EFUSE_BT_REAL_CONTENT_LEN;
++ }
++ break;
++ case TYPE_AVAILABLE_EFUSE_BYTES_BANK:
++ {
++ u16 *pu2Tmp;
++ pu2Tmp = (u16 *)pOut;
++ if(efuseType == EFUSE_WIFI)
++ *pu2Tmp = (u16)(EFUSE_REAL_CONTENT_LEN-EFUSE_OOB_PROTECT_BYTES);
++ else
++ *pu2Tmp = (u16)(EFUSE_REAL_CONTENT_LEN-EFUSE_PROTECT_BYTES_BANK);
++ }
++ break;
++ case TYPE_AVAILABLE_EFUSE_BYTES_TOTAL:
++ {
++ u16 *pu2Tmp;
++ pu2Tmp = (u16 *)pOut;
++ if(efuseType == EFUSE_WIFI)
++ *pu2Tmp = (u16)(EFUSE_REAL_CONTENT_LEN-EFUSE_OOB_PROTECT_BYTES);
++ else
++ *pu2Tmp = (u16)(EFUSE_BT_REAL_CONTENT_LEN-(EFUSE_PROTECT_BYTES_BANK*3));
++ }
++ break;
++ case TYPE_EFUSE_MAP_LEN:
++ {
++ u16 *pu2Tmp;
++ pu2Tmp = (u16 *)pOut;
++
++ if(efuseType == EFUSE_WIFI)
++ {
++ if(IS_HARDWARE_TYPE_8192C(pAdapter))
++ {
++ *pu2Tmp = (u16)EFUSE_MAP_LEN;
++ }
++ else if(IS_HARDWARE_TYPE_8723A(pAdapter))
++ {
++ *pu2Tmp = (u16)EFUSE_MAP_LEN_8723;
++ }
++ }
++ else
++ *pu2Tmp = (u16)EFUSE_BT_MAP_LEN;
++ }
++ break;
++ case TYPE_EFUSE_PROTECT_BYTES_BANK:
++ {
++ u8 *pu1Tmp;
++ pu1Tmp = (u8 *)pOut;
++ if(efuseType == EFUSE_WIFI)
++ *pu1Tmp = (u8)(EFUSE_OOB_PROTECT_BYTES);
++ else
++ *pu1Tmp = (u8)(EFUSE_PROTECT_BYTES_BANK);
++ }
++ break;
++ default:
++ {
++ u8 *pu1Tmp;
++ pu1Tmp = (u8 *)pOut;
++ *pu1Tmp = 0;
++ }
++ break;
++ }
++}
++
++static VOID
++Hal_EFUSEGetEfuseDefinition_Pseudo(
++ IN PADAPTER pAdapter,
++ IN u8 efuseType,
++ IN u8 type,
++ OUT PVOID *pOut
++ )
++{
++ switch(type)
++ {
++ case TYPE_EFUSE_MAX_SECTION:
++ {
++ u8 *pMax_section;
++ pMax_section = (u8 *)pOut;
++ if(efuseType == EFUSE_WIFI)
++ *pMax_section = EFUSE_MAX_SECTION_8723;
++ else
++ *pMax_section = EFUSE_BT_MAX_SECTION;
++ }
++ break;
++ case TYPE_EFUSE_REAL_CONTENT_LEN:
++ {
++ u16 *pu2Tmp;
++ pu2Tmp = (u16 *)pOut;
++ if(efuseType == EFUSE_WIFI)
++ *pu2Tmp = EFUSE_REAL_CONTENT_LEN;
++ else
++ *pu2Tmp = EFUSE_BT_REAL_CONTENT_LEN;
++ }
++ break;
++ case TYPE_AVAILABLE_EFUSE_BYTES_BANK:
++ {
++ u16 *pu2Tmp;
++ pu2Tmp = (u16 *)pOut;
++ if(efuseType == EFUSE_WIFI)
++ *pu2Tmp = (u16)(EFUSE_REAL_CONTENT_LEN-EFUSE_OOB_PROTECT_BYTES);
++ else
++ *pu2Tmp = (u16)(EFUSE_REAL_CONTENT_LEN-EFUSE_PROTECT_BYTES_BANK);
++ }
++ break;
++ case TYPE_AVAILABLE_EFUSE_BYTES_TOTAL:
++ {
++ u16 *pu2Tmp;
++ pu2Tmp = (u16 *)pOut;
++ if(efuseType == EFUSE_WIFI)
++ *pu2Tmp = (u16)(EFUSE_REAL_CONTENT_LEN-EFUSE_OOB_PROTECT_BYTES);
++ else
++ *pu2Tmp = (u16)(EFUSE_BT_REAL_CONTENT_LEN-(EFUSE_PROTECT_BYTES_BANK*3));
++ }
++ break;
++ case TYPE_EFUSE_MAP_LEN:
++ {
++ u16 *pu2Tmp;
++ pu2Tmp = (u16 *)pOut;
++ if(efuseType == EFUSE_WIFI)
++ *pu2Tmp = (u16)EFUSE_MAP_LEN_8723;
++ else
++ *pu2Tmp = (u16)EFUSE_BT_MAP_LEN;
++ }
++ break;
++ case TYPE_EFUSE_PROTECT_BYTES_BANK:
++ {
++ u8 *pu1Tmp;
++ pu1Tmp = (u8 *)pOut;
++ if(efuseType == EFUSE_WIFI)
++ *pu1Tmp = (u8)(EFUSE_OOB_PROTECT_BYTES);
++ else
++ *pu1Tmp = (u8)(EFUSE_PROTECT_BYTES_BANK);
++ }
++ break;
++ default:
++ {
++ u8 *pu1Tmp;
++ pu1Tmp = (u8 *)pOut;
++ *pu1Tmp = 0;
++ }
++ break;
++ }
++}
++
++static VOID
++rtl8192c_EFUSE_GetEfuseDefinition(
++ IN PADAPTER pAdapter,
++ IN u8 efuseType,
++ IN u8 type,
++ OUT PVOID *pOut,
++ IN BOOLEAN bPseudoTest
++ )
++{
++ if(bPseudoTest)
++ {
++ Hal_EFUSEGetEfuseDefinition_Pseudo(pAdapter, efuseType, type, pOut);
++ }
++ else
++ {
++ Hal_EFUSEGetEfuseDefinition(pAdapter, efuseType, type, pOut);
++ }
++}
++
++static u8
++Hal_EfuseWordEnableDataWrite( IN PADAPTER pAdapter,
++ IN u16 efuse_addr,
++ IN u8 word_en,
++ IN u8 *data,
++ IN BOOLEAN bPseudoTest)
++{
++ u16 tmpaddr = 0;
++ u16 start_addr = efuse_addr;
++ u8 badworden = 0x0F;
++ u8 tmpdata[8];
++
++ _rtw_memset((PVOID)tmpdata, 0xff, PGPKT_DATA_SIZE);
++ //RT_TRACE(COMP_EFUSE, DBG_LOUD, ("word_en = %x efuse_addr=%x\n", word_en, efuse_addr));
++
++ if(!(word_en&BIT0))
++ {
++ tmpaddr = start_addr;
++ efuse_OneByteWrite(pAdapter,start_addr++, data[0], bPseudoTest);
++ efuse_OneByteWrite(pAdapter,start_addr++, data[1], bPseudoTest);
++
++ efuse_OneByteRead(pAdapter,tmpaddr, &tmpdata[0], bPseudoTest);
++ efuse_OneByteRead(pAdapter,tmpaddr+1, &tmpdata[1], bPseudoTest);
++ if((data[0]!=tmpdata[0])||(data[1]!=tmpdata[1])){
++ badworden &= (~BIT0);
++ }
++ }
++ if(!(word_en&BIT1))
++ {
++ tmpaddr = start_addr;
++ efuse_OneByteWrite(pAdapter,start_addr++, data[2], bPseudoTest);
++ efuse_OneByteWrite(pAdapter,start_addr++, data[3], bPseudoTest);
++
++ efuse_OneByteRead(pAdapter,tmpaddr , &tmpdata[2], bPseudoTest);
++ efuse_OneByteRead(pAdapter,tmpaddr+1, &tmpdata[3], bPseudoTest);
++ if((data[2]!=tmpdata[2])||(data[3]!=tmpdata[3])){
++ badworden &=( ~BIT1);
++ }
++ }
++ if(!(word_en&BIT2))
++ {
++ tmpaddr = start_addr;
++ efuse_OneByteWrite(pAdapter,start_addr++, data[4], bPseudoTest);
++ efuse_OneByteWrite(pAdapter,start_addr++, data[5], bPseudoTest);
++
++ efuse_OneByteRead(pAdapter,tmpaddr, &tmpdata[4], bPseudoTest);
++ efuse_OneByteRead(pAdapter,tmpaddr+1, &tmpdata[5], bPseudoTest);
++ if((data[4]!=tmpdata[4])||(data[5]!=tmpdata[5])){
++ badworden &=( ~BIT2);
++ }
++ }
++ if(!(word_en&BIT3))
++ {
++ tmpaddr = start_addr;
++ efuse_OneByteWrite(pAdapter,start_addr++, data[6], bPseudoTest);
++ efuse_OneByteWrite(pAdapter,start_addr++, data[7], bPseudoTest);
++
++ efuse_OneByteRead(pAdapter,tmpaddr, &tmpdata[6], bPseudoTest);
++ efuse_OneByteRead(pAdapter,tmpaddr+1, &tmpdata[7], bPseudoTest);
++ if((data[6]!=tmpdata[6])||(data[7]!=tmpdata[7])){
++ badworden &=( ~BIT3);
++ }
++ }
++ return badworden;
++}
++
++static u8
++Hal_EfuseWordEnableDataWrite_Pseudo( IN PADAPTER pAdapter,
++ IN u16 efuse_addr,
++ IN u8 word_en,
++ IN u8 *data,
++ IN BOOLEAN bPseudoTest)
++{
++ u8 ret=0;
++
++ ret = Hal_EfuseWordEnableDataWrite(pAdapter, efuse_addr, word_en, data, bPseudoTest);
++
++ return ret;
++}
++
++static u8
++rtl8192c_Efuse_WordEnableDataWrite( IN PADAPTER pAdapter,
++ IN u16 efuse_addr,
++ IN u8 word_en,
++ IN u8 *data,
++ IN BOOLEAN bPseudoTest)
++{
++ u8 ret=0;
++
++ if(bPseudoTest)
++ {
++ ret = Hal_EfuseWordEnableDataWrite_Pseudo(pAdapter, efuse_addr, word_en, data, bPseudoTest);
++ }
++ else
++ {
++ ret = Hal_EfuseWordEnableDataWrite(pAdapter, efuse_addr, word_en, data, bPseudoTest);
++ }
++
++ return ret;
++}
++
++
++static u16
++hal_EfuseGetCurrentSize_8192C(IN PADAPTER pAdapter,
++ IN BOOLEAN bPseudoTest)
++{
++ int bContinual = _TRUE;
++
++ u16 efuse_addr = 0;
++ u8 hoffset=0,hworden=0;
++ u8 efuse_data,word_cnts=0;
++
++ while ( bContinual &&
++ efuse_OneByteRead(pAdapter, efuse_addr ,&efuse_data, bPseudoTest) &&
++ (efuse_addr < EFUSE_REAL_CONTENT_LEN) )
++ {
++ if(efuse_data!=0xFF)
++ {
++ hoffset = (efuse_data>>4) & 0x0F;
++ hworden = efuse_data & 0x0F;
++ word_cnts = Efuse_CalculateWordCnts(hworden);
++ //read next header
++ efuse_addr = efuse_addr + (word_cnts*2)+1;
++ }
++ else
++ {
++ bContinual = _FALSE ;
++ }
++ }
++
++ return efuse_addr;
++}
++
++static u16
++Hal_EfuseGetCurrentSize_BT(IN PADAPTER pAdapter,
++ IN BOOLEAN bPseudoTest)
++{
++ int bContinual = _TRUE;
++ u16 efuse_addr = 0;
++ u8 hoffset=0,hworden=0;
++ u8 efuse_data,word_cnts=0;
++ u8 bank=0, startBank=0;
++ u16 retU2=0;
++ u32 total_efuse_used=0;
++
++ if(bPseudoTest)
++ {
++ efuse_addr = (u16)((fakeBTEfuseUsedBytes%EFUSE_REAL_CONTENT_LEN));
++ startBank = (u8)(1+(fakeBTEfuseUsedBytes/EFUSE_REAL_CONTENT_LEN));
++ }
++ else
++ {
++ efuse_addr = (u16)((BTEfuseUsedBytes%EFUSE_REAL_CONTENT_LEN));
++ startBank = (u8)(1+(BTEfuseUsedBytes/EFUSE_REAL_CONTENT_LEN));
++ }
++
++ if((startBank < 1) || (startBank >= EFUSE_MAX_BANK))
++ DBG_8192C("Error, bank error, bank=%d\n", bank);
++
++ //RTPRINT(FEEPROM, EFUSE_PG, ("Hal_EfuseGetCurrentSize_BT(), start bank=%d, start_efuse_addr = %d\n", startBank, efuse_addr));
++
++ for(bank=startBank; bank<EFUSE_MAX_BANK; bank++)
++ {
++ if(!Hal_EfuseSwitchToBank(pAdapter, bank, bPseudoTest))
++ break;
++ else
++ {
++ bContinual = _TRUE;
++ if(bank != startBank) // only when bank is switched we have to reset the efuse_addr.
++ efuse_addr = 0;
++ }
++
++ while ( bContinual &&
++ efuse_OneByteRead(pAdapter, efuse_addr ,&efuse_data, bPseudoTest) &&
++ AVAILABLE_EFUSE_ADDR(efuse_addr))
++ {
++ if(efuse_data!=0xFF)
++ {
++ if((efuse_data&0x1F) == 0x0F) //extended header
++ {
++ hoffset = efuse_data;
++ efuse_addr++;
++ efuse_OneByteRead(pAdapter, efuse_addr ,&efuse_data, bPseudoTest);
++ if((efuse_data & 0x0F) == 0x0F)
++ {
++ efuse_addr++;
++ continue;
++ }
++ else
++ {
++ hoffset = ((hoffset & 0xE0) >> 5) | ((efuse_data & 0xF0) >> 1);
++ hworden = efuse_data & 0x0F;
++ }
++ }
++ else
++ {
++ hoffset = (efuse_data>>4) & 0x0F;
++ hworden = efuse_data & 0x0F;
++ }
++ word_cnts = Efuse_CalculateWordCnts(hworden);
++ //read next header
++ efuse_addr = efuse_addr + (word_cnts*2)+1;
++ }
++ else
++ {
++ bContinual = _FALSE ;
++ }
++ }
++
++ // Check if we need to check next bank efuse
++ if(efuse_addr < (EFUSE_REAL_CONTENT_LEN-EFUSE_PROTECT_BYTES_BANK))
++ {
++ break;// don't need to check next bank.
++ }
++ }
++
++ retU2 = ((bank-1)*EFUSE_REAL_CONTENT_LEN)+efuse_addr;
++ if(bPseudoTest)
++ {
++ fakeBTEfuseUsedBytes = retU2;
++ //RTPRINT(FEEPROM, EFUSE_PG, ("Hal_EfuseGetCurrentSize_BT(), return %d\n", fakeBTEfuseUsedBytes));
++ }
++ else
++ {
++ BTEfuseUsedBytes = retU2;
++ //RTPRINT(FEEPROM, EFUSE_PG, ("Hal_EfuseGetCurrentSize_BT(), return %d\n", BTEfuseUsedBytes));
++ }
++
++ return retU2;
++}
++
++
++static u16
++hal_EfuseGetCurrentSize_8723(IN PADAPTER pAdapter,
++ IN BOOLEAN bPseudoTest)
++{
++ int bContinual = _TRUE;
++
++ u16 efuse_addr = 0;
++ u8 hoffset=0,hworden=0;
++ u8 efuse_data,word_cnts=0;
++
++ if(bPseudoTest)
++ {
++ efuse_addr = (u16)(fakeEfuseUsedBytes);
++ }
++ else
++ {
++ rtw_hal_get_hwreg(pAdapter, HW_VAR_EFUSE_BYTES, (u8 *)&efuse_addr);
++ }
++ //RTPRINT(FEEPROM, EFUSE_PG, ("hal_EfuseGetCurrentSize_8723(), start_efuse_addr = %d\n", efuse_addr));
++
++ while ( bContinual &&
++ efuse_OneByteRead(pAdapter, efuse_addr ,&efuse_data, bPseudoTest) &&
++ AVAILABLE_EFUSE_ADDR(efuse_addr))
++ {
++ if(efuse_data!=0xFF)
++ {
++ if((efuse_data&0x1F) == 0x0F) //extended header
++ {
++ hoffset = efuse_data;
++ efuse_addr++;
++ efuse_OneByteRead(pAdapter, efuse_addr ,&efuse_data, bPseudoTest);
++ if((efuse_data & 0x0F) == 0x0F)
++ {
++ efuse_addr++;
++ continue;
++ }
++ else
++ {
++ hoffset = ((hoffset & 0xE0) >> 5) | ((efuse_data & 0xF0) >> 1);
++ hworden = efuse_data & 0x0F;
++ }
++ }
++ else
++ {
++ hoffset = (efuse_data>>4) & 0x0F;
++ hworden = efuse_data & 0x0F;
++ }
++ word_cnts = Efuse_CalculateWordCnts(hworden);
++ //read next header
++ efuse_addr = efuse_addr + (word_cnts*2)+1;
++ }
++ else
++ {
++ bContinual = _FALSE ;
++ }
++ }
++
++ if(bPseudoTest)
++ {
++ fakeEfuseUsedBytes = efuse_addr;
++ //RTPRINT(FEEPROM, EFUSE_PG, ("hal_EfuseGetCurrentSize_8723(), return %d\n", fakeEfuseUsedBytes));
++ }
++ else
++ {
++ rtw_hal_set_hwreg(pAdapter, HW_VAR_EFUSE_BYTES, (u8 *)&efuse_addr);
++ //RTPRINT(FEEPROM, EFUSE_PG, ("hal_EfuseGetCurrentSize_8723(), return %d\n", efuse_addr));
++ }
++
++ return efuse_addr;
++}
++
++static u16
++Hal_EfuseGetCurrentSize_Pseudo(IN PADAPTER pAdapter,
++ IN BOOLEAN bPseudoTest)
++{
++ u16 ret=0;
++
++ ret = hal_EfuseGetCurrentSize_8723(pAdapter, bPseudoTest);
++
++ return ret;
++}
++
++static u16
++rtl8192c_EfuseGetCurrentSize(
++ IN PADAPTER pAdapter,
++ IN u8 efuseType,
++ IN BOOLEAN bPseudoTest)
++{
++ u16 ret=0;
++
++ if(efuseType == EFUSE_WIFI)
++ {
++ if(bPseudoTest)
++ {
++ ret = Hal_EfuseGetCurrentSize_Pseudo(pAdapter, bPseudoTest);
++ }
++ else
++ {
++ if(IS_HARDWARE_TYPE_8192C(pAdapter))
++ {
++ ret = hal_EfuseGetCurrentSize_8192C(pAdapter, bPseudoTest);
++ }
++ else if(IS_HARDWARE_TYPE_8723A(pAdapter))
++ {
++ ret = hal_EfuseGetCurrentSize_8723(pAdapter, bPseudoTest);
++ }
++ }
++ }
++ else
++ {
++ ret = Hal_EfuseGetCurrentSize_BT(pAdapter, bPseudoTest);
++ }
++
++ return ret;
++}
++
++static int
++hal_EfusePgPacketRead_8192C( IN PADAPTER pAdapter,
++ IN u8 offset,
++ IN u8 *data,
++ IN BOOLEAN bPseudoTest)
++{
++ u8 ReadState = PG_STATE_HEADER;
++
++ int bContinual = _TRUE;
++ int bDataEmpty = _TRUE ;
++
++ u8 efuse_data,word_cnts=0;
++ u16 efuse_addr = 0;
++ u8 hoffset=0,hworden=0;
++ u8 tmpidx=0;
++ u8 tmpdata[8];
++
++ if(data==NULL) return _FALSE;
++ if(offset>15) return _FALSE;
++
++
++ _rtw_memset((PVOID)data, 0xff, sizeof(u8)*PGPKT_DATA_SIZE);
++ _rtw_memset((PVOID)tmpdata, 0xff, sizeof(u8)*PGPKT_DATA_SIZE);
++
++ //
++ // <Roger_TODO> Efuse has been pre-programmed dummy 5Bytes at the end of Efuse by CP.
++ // Skip dummy parts to prevent unexpected data read from Efuse.
++ // By pass right now. 2009.02.19.
++ //
++ while(bContinual && (efuse_addr < EFUSE_REAL_CONTENT_LEN) )
++ {
++ //------- Header Read -------------
++ if(ReadState & PG_STATE_HEADER)
++ {
++ if(efuse_OneByteRead(pAdapter, efuse_addr ,&efuse_data, bPseudoTest)&&(efuse_data!=0xFF)){
++ hoffset = (efuse_data>>4) & 0x0F;
++ hworden = efuse_data & 0x0F;
++ word_cnts = Efuse_CalculateWordCnts(hworden);
++ bDataEmpty = _TRUE ;
++
++ if(hoffset==offset){
++ for(tmpidx = 0;tmpidx< word_cnts*2 ;tmpidx++){
++ if(efuse_OneByteRead(pAdapter, efuse_addr+1+tmpidx ,&efuse_data, bPseudoTest) ){
++ tmpdata[tmpidx] = efuse_data;
++ if(efuse_data!=0xff){
++ bDataEmpty = _FALSE;
++ }
++ }
++ }
++ if(bDataEmpty==_FALSE){
++ ReadState = PG_STATE_DATA;
++ }else{//read next header
++ efuse_addr = efuse_addr + (word_cnts*2)+1;
++ ReadState = PG_STATE_HEADER;
++ }
++ }
++ else{//read next header
++ efuse_addr = efuse_addr + (word_cnts*2)+1;
++ ReadState = PG_STATE_HEADER;
++ }
++
++ }
++ else{
++ bContinual = _FALSE ;
++ }
++ }
++ //------- Data section Read -------------
++ else if(ReadState & PG_STATE_DATA)
++ {
++ efuse_WordEnableDataRead(hworden,tmpdata,data);
++ efuse_addr = efuse_addr + (word_cnts*2)+1;
++ ReadState = PG_STATE_HEADER;
++ }
++
++ }
++
++ if( (data[0]==0xff) &&(data[1]==0xff) && (data[2]==0xff) && (data[3]==0xff) &&
++ (data[4]==0xff) &&(data[5]==0xff) && (data[6]==0xff) && (data[7]==0xff))
++ return _FALSE;
++ else
++ return _TRUE;
++
++}
++
++static int
++hal_EfusePgPacketRead_8723( IN PADAPTER pAdapter,
++ IN u8 offset,
++ IN u8 *data,
++ IN BOOLEAN bPseudoTest)
++{
++ u8 ReadState = PG_STATE_HEADER;
++
++ int bContinual = _TRUE;
++ int bDataEmpty = _TRUE ;
++
++ u8 efuse_data,word_cnts=0;
++ u16 efuse_addr = 0;
++ u8 hoffset=0,hworden=0;
++ u8 tmpidx=0;
++ u8 tmpdata[8];
++ u8 max_section=0;
++ u8 tmp_header = 0;
++
++ EFUSE_GetEfuseDefinition(pAdapter, EFUSE_WIFI, TYPE_EFUSE_MAX_SECTION, (PVOID)&max_section, bPseudoTest);
++
++ if(data==NULL)
++ return _FALSE;
++ if(offset>max_section)
++ return _FALSE;
++
++ _rtw_memset((PVOID)data, 0xff, sizeof(u8)*PGPKT_DATA_SIZE);
++ _rtw_memset((PVOID)tmpdata, 0xff, sizeof(u8)*PGPKT_DATA_SIZE);
++
++
++ //
++ // <Roger_TODO> Efuse has been pre-programmed dummy 5Bytes at the end of Efuse by CP.
++ // Skip dummy parts to prevent unexpected data read from Efuse.
++ // By pass right now. 2009.02.19.
++ //
++ while(bContinual && AVAILABLE_EFUSE_ADDR(efuse_addr) )
++ {
++ //------- Header Read -------------
++ if(ReadState & PG_STATE_HEADER)
++ {
++ if(efuse_OneByteRead(pAdapter, efuse_addr ,&efuse_data, bPseudoTest)&&(efuse_data!=0xFF))
++ {
++ if(EXT_HEADER(efuse_data))
++ {
++ tmp_header = efuse_data;
++ efuse_addr++;
++ efuse_OneByteRead(pAdapter, efuse_addr ,&efuse_data, bPseudoTest);
++ if(!ALL_WORDS_DISABLED(efuse_data))
++ {
++ hoffset = ((tmp_header & 0xE0) >> 5) | ((efuse_data & 0xF0) >> 1);
++ hworden = efuse_data & 0x0F;
++ }
++ else
++ {
++ DBG_8192C("Error, All words disabled\n");
++ efuse_addr++;
++ continue;
++ }
++ }
++ else
++ {
++ hoffset = (efuse_data>>4) & 0x0F;
++ hworden = efuse_data & 0x0F;
++ }
++ word_cnts = Efuse_CalculateWordCnts(hworden);
++ bDataEmpty = _TRUE ;
++
++ if(hoffset==offset)
++ {
++ for(tmpidx = 0;tmpidx< word_cnts*2 ;tmpidx++)
++ {
++ if(efuse_OneByteRead(pAdapter, efuse_addr+1+tmpidx ,&efuse_data, bPseudoTest) )
++ {
++ tmpdata[tmpidx] = efuse_data;
++ if(efuse_data!=0xff)
++ {
++ bDataEmpty = _FALSE;
++ }
++ }
++ }
++ if(bDataEmpty==_FALSE){
++ ReadState = PG_STATE_DATA;
++ }else{//read next header
++ efuse_addr = efuse_addr + (word_cnts*2)+1;
++ ReadState = PG_STATE_HEADER;
++ }
++ }
++ else{//read next header
++ efuse_addr = efuse_addr + (word_cnts*2)+1;
++ ReadState = PG_STATE_HEADER;
++ }
++
++ }
++ else{
++ bContinual = _FALSE ;
++ }
++ }
++ //------- Data section Read -------------
++ else if(ReadState & PG_STATE_DATA)
++ {
++ efuse_WordEnableDataRead(hworden,tmpdata,data);
++ efuse_addr = efuse_addr + (word_cnts*2)+1;
++ ReadState = PG_STATE_HEADER;
++ }
++
++ }
++
++ if( (data[0]==0xff) &&(data[1]==0xff) && (data[2]==0xff) && (data[3]==0xff) &&
++ (data[4]==0xff) &&(data[5]==0xff) && (data[6]==0xff) && (data[7]==0xff))
++ return _FALSE;
++ else
++ return _TRUE;
++
++}
++
++static int
++Hal_EfusePgPacketRead( IN PADAPTER pAdapter,
++ IN u8 offset,
++ IN u8 *data,
++ IN BOOLEAN bPseudoTest)
++{
++ int ret=0;
++
++ if(IS_HARDWARE_TYPE_8192C(pAdapter))
++ {
++ ret = hal_EfusePgPacketRead_8192C(pAdapter, offset, data, bPseudoTest);
++ }
++ else if(IS_HARDWARE_TYPE_8723A(pAdapter))
++ {
++ ret = hal_EfusePgPacketRead_8723(pAdapter, offset, data, bPseudoTest);
++ }
++
++ return ret;
++}
++
++static int
++Hal_EfusePgPacketRead_Pseudo( IN PADAPTER pAdapter,
++ IN u8 offset,
++ IN u8 *data,
++ IN BOOLEAN bPseudoTest)
++{
++ int ret=0;
++
++ ret = hal_EfusePgPacketRead_8723(pAdapter, offset, data, bPseudoTest);
++
++ return ret;
++}
++
++static int
++rtl8192c_Efuse_PgPacketRead( IN PADAPTER pAdapter,
++ IN u8 offset,
++ IN u8 *data,
++ IN BOOLEAN bPseudoTest)
++{
++ int ret=0;
++
++ if(bPseudoTest)
++ {
++ ret = Hal_EfusePgPacketRead_Pseudo(pAdapter, offset, data, bPseudoTest);
++ }
++ else
++ {
++ ret = Hal_EfusePgPacketRead(pAdapter, offset, data, bPseudoTest);
++ }
++
++ return ret;
++}
++
++static BOOLEAN
++hal_EfuseFixHeaderProcess(
++ IN PADAPTER pAdapter,
++ IN u8 efuseType,
++ IN PPGPKT_STRUCT pFixPkt,
++ IN u16 *pAddr,
++ IN BOOLEAN bPseudoTest
++)
++{
++ u8 originaldata[8], badworden=0;
++ u16 efuse_addr=*pAddr;
++ u32 PgWriteSuccess=0;
++
++ _rtw_memset((PVOID)originaldata, 0xff, 8);
++
++ if(Efuse_PgPacketRead(pAdapter, pFixPkt->offset, originaldata, bPseudoTest))
++ { //check if data exist
++ badworden = Efuse_WordEnableDataWrite(pAdapter, efuse_addr+1, pFixPkt->word_en, originaldata, bPseudoTest);
++
++ if(badworden != 0xf) // write fail
++ {
++ if(efuseType == EFUSE_WIFI)
++ PgWriteSuccess = Efuse_PgPacketWrite(pAdapter, pFixPkt->offset, badworden, originaldata, bPseudoTest);
++ else
++ PgWriteSuccess = hal_EfusePgPacketWrite_BT(pAdapter, pFixPkt->offset, badworden, originaldata, bPseudoTest);
++ if(!PgWriteSuccess)
++ return _FALSE;
++ else
++ efuse_addr = Efuse_GetCurrentSize(pAdapter, efuseType, bPseudoTest);
++ }
++ else
++ {
++ efuse_addr = efuse_addr + (pFixPkt->word_cnts*2) +1;
++ }
++ }
++ else
++ {
++ efuse_addr = efuse_addr + (pFixPkt->word_cnts*2) +1;
++ }
++ *pAddr = efuse_addr;
++ return _TRUE;
++}
++
++static BOOLEAN
++hal_EfusePgPacketWrite2ByteHeader(
++ IN PADAPTER pAdapter,
++ IN u8 efuseType,
++ IN u16 *pAddr,
++ IN PPGPKT_STRUCT pTargetPkt,
++ IN BOOLEAN bPseudoTest)
++{
++ BOOLEAN bRet=_FALSE, bContinual=_TRUE;
++ u16 efuse_addr=*pAddr, efuse_max_available_len=0;
++ u8 pg_header=0, tmp_header=0, pg_header_temp=0;
++ u8 repeatcnt=0;
++
++ //RTPRINT(FEEPROM, EFUSE_PG, ("Wirte 2byte header\n"));
++ EFUSE_GetEfuseDefinition(pAdapter, efuseType, TYPE_AVAILABLE_EFUSE_BYTES_BANK, (PVOID)&efuse_max_available_len, bPseudoTest);
++
++ while(efuse_addr < efuse_max_available_len)
++ {
++ pg_header = ((pTargetPkt->offset & 0x07) << 5) | 0x0F;
++ //RTPRINT(FEEPROM, EFUSE_PG, ("pg_header = 0x%x\n", pg_header));
++ efuse_OneByteWrite(pAdapter, efuse_addr, pg_header, bPseudoTest);
++ efuse_OneByteRead(pAdapter, efuse_addr, &tmp_header, bPseudoTest);
++
++ while(tmp_header == 0xFF)
++ {
++ if(repeatcnt++ > EFUSE_REPEAT_THRESHOLD_)
++ {
++ //RTPRINT(FEEPROM, EFUSE_PG, ("Repeat over limit for pg_header!!\n"));
++ return _FALSE;
++ }
++
++ efuse_OneByteWrite(pAdapter, efuse_addr, pg_header, bPseudoTest);
++ efuse_OneByteRead(pAdapter, efuse_addr, &tmp_header, bPseudoTest);
++ }
++
++ //to write ext_header
++ if(tmp_header == pg_header)
++ {
++ efuse_addr++;
++ pg_header_temp = pg_header;
++ pg_header = ((pTargetPkt->offset & 0x78) << 1) | pTargetPkt->word_en;
++
++ efuse_OneByteWrite(pAdapter, efuse_addr, pg_header, bPseudoTest);
++ efuse_OneByteRead(pAdapter, efuse_addr, &tmp_header, bPseudoTest);
++
++ while(tmp_header == 0xFF)
++ {
++ if(repeatcnt++ > EFUSE_REPEAT_THRESHOLD_)
++ {
++ //RTPRINT(FEEPROM, EFUSE_PG, ("Repeat over limit for ext_header!!\n"));
++ return _FALSE;
++ }
++
++ efuse_OneByteWrite(pAdapter, efuse_addr, pg_header, bPseudoTest);
++ efuse_OneByteRead(pAdapter, efuse_addr, &tmp_header, bPseudoTest);
++ }
++
++ if((tmp_header & 0x0F) == 0x0F) //word_en PG fail
++ {
++ if(repeatcnt++ > EFUSE_REPEAT_THRESHOLD_)
++ {
++ //RTPRINT(FEEPROM, EFUSE_PG, ("Repeat over limit for word_en!!\n"));
++ return _FALSE;
++ }
++ else
++ {
++ efuse_addr++;
++ continue;
++ }
++ }
++ else if(pg_header != tmp_header) //offset PG fail
++ {
++ PGPKT_STRUCT fixPkt;
++ //RTPRINT(FEEPROM, EFUSE_PG, ("Error condition for offset PG fail, need to cover the existed data\n"));
++ fixPkt.offset = ((pg_header_temp & 0xE0) >> 5) | ((tmp_header & 0xF0) >> 1);
++ fixPkt.word_en = tmp_header & 0x0F;
++ fixPkt.word_cnts = Efuse_CalculateWordCnts(fixPkt.word_en);
++ if(!hal_EfuseFixHeaderProcess(pAdapter, efuseType, &fixPkt, &efuse_addr, bPseudoTest))
++ return _FALSE;
++ }
++ else
++ {
++ bRet = _TRUE;
++ break;
++ }
++ }
++ else if ((tmp_header & 0x1F) == 0x0F) //wrong extended header
++ {
++ efuse_addr+=2;
++ continue;
++ }
++ }
++
++ *pAddr = efuse_addr;
++ return bRet;
++}
++
++static BOOLEAN
++hal_EfusePgPacketWrite1ByteHeader(
++ IN PADAPTER pAdapter,
++ IN u8 efuseType,
++ IN u16 *pAddr,
++ IN PPGPKT_STRUCT pTargetPkt,
++ IN BOOLEAN bPseudoTest)
++{
++ BOOLEAN bRet=_FALSE;
++ u8 pg_header=0, tmp_header=0;
++ u16 efuse_addr=*pAddr;
++ u8 repeatcnt=0;
++
++ //RTPRINT(FEEPROM, EFUSE_PG, ("Wirte 1byte header\n"));
++ pg_header = ((pTargetPkt->offset << 4) & 0xf0) |pTargetPkt->word_en;
++
++ efuse_OneByteWrite(pAdapter, efuse_addr, pg_header, bPseudoTest);
++ efuse_OneByteRead(pAdapter, efuse_addr, &tmp_header, bPseudoTest);
++
++ while(tmp_header == 0xFF)
++ {
++ if(repeatcnt++ > EFUSE_REPEAT_THRESHOLD_)
++ {
++ return _FALSE;
++ }
++ efuse_OneByteWrite(pAdapter,efuse_addr, pg_header, bPseudoTest);
++ efuse_OneByteRead(pAdapter,efuse_addr, &tmp_header, bPseudoTest);
++ }
++
++ if(pg_header == tmp_header)
++ {
++ bRet = _TRUE;
++ }
++ else
++ {
++ PGPKT_STRUCT fixPkt;
++ //RTPRINT(FEEPROM, EFUSE_PG, ("Error condition for fixed PG packet, need to cover the existed data\n"));
++ fixPkt.offset = (tmp_header>>4) & 0x0F;
++ fixPkt.word_en = tmp_header & 0x0F;
++ fixPkt.word_cnts = Efuse_CalculateWordCnts(fixPkt.word_en);
++ if(!hal_EfuseFixHeaderProcess(pAdapter, efuseType, &fixPkt, &efuse_addr, bPseudoTest))
++ return _FALSE;
++ }
++
++ *pAddr = efuse_addr;
++ return bRet;
++}
++
++static BOOLEAN
++hal_EfusePgPacketWriteData(
++ IN PADAPTER pAdapter,
++ IN u8 efuseType,
++ IN u16 *pAddr,
++ IN PPGPKT_STRUCT pTargetPkt,
++ IN BOOLEAN bPseudoTest)
++{
++ BOOLEAN bRet=_FALSE;
++ u16 efuse_addr=*pAddr;
++ u8 badworden=0;
++ u32 PgWriteSuccess=0;
++
++ badworden = 0x0f;
++ badworden = Efuse_WordEnableDataWrite(pAdapter, efuse_addr+1, pTargetPkt->word_en, pTargetPkt->data, bPseudoTest);
++ if(badworden == 0x0F)
++ {
++ // write ok
++ //RTPRINT(FEEPROM, EFUSE_PG, ("hal_EfusePgPacketWriteData ok!!\n"));
++ return _TRUE;
++ }
++ else
++ {
++ //RTPRINT(FEEPROM, EFUSE_PG, ("hal_EfusePgPacketWriteData Fail!!\n"));
++ //reorganize other pg packet
++ if(efuseType == EFUSE_WIFI)
++ PgWriteSuccess = Efuse_PgPacketWrite(pAdapter, pTargetPkt->offset, badworden, pTargetPkt->data, bPseudoTest);
++ else
++ PgWriteSuccess = hal_EfusePgPacketWrite_BT(pAdapter, pTargetPkt->offset, badworden, pTargetPkt->data, bPseudoTest);
++ if(!PgWriteSuccess)
++ return _FALSE;
++ else
++ return _TRUE;
++ }
++
++ return bRet;
++}
++
++static BOOLEAN
++hal_EfusePgPacketWriteHeader(
++ IN PADAPTER pAdapter,
++ IN u8 efuseType,
++ IN u16 *pAddr,
++ IN PPGPKT_STRUCT pTargetPkt,
++ IN BOOLEAN bPseudoTest)
++{
++ BOOLEAN bRet=_FALSE;
++
++ if(pTargetPkt->offset >= EFUSE_MAX_SECTION_BASE)
++ {
++ bRet = hal_EfusePgPacketWrite2ByteHeader(pAdapter, efuseType, pAddr, pTargetPkt, bPseudoTest);
++ }
++ else
++ {
++ bRet = hal_EfusePgPacketWrite1ByteHeader(pAdapter, efuseType, pAddr, pTargetPkt, bPseudoTest);
++ }
++
++ return bRet;
++}
++
++static BOOLEAN
++hal_EfusePgCheckAvailableAddr(
++ IN PADAPTER pAdapter,
++ IN u8 efuseType,
++ IN BOOLEAN bPseudoTest
++ )
++{
++ u16 efuse_max_available_len=0;
++
++ EFUSE_GetEfuseDefinition(pAdapter, efuseType, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, (PVOID)&efuse_max_available_len, bPseudoTest);
++ //RTPRINT(FEEPROM, EFUSE_PG, ("efuse_max_available_len = %d\n", efuse_max_available_len));
++
++ if(Efuse_GetCurrentSize(pAdapter, efuseType, bPseudoTest) >= efuse_max_available_len)
++ {
++ //RTPRINT(FEEPROM, EFUSE_PG, ("hal_EfusePgCheckAvailableAddr error!!\n"));
++ return _FALSE;
++ }
++ return _TRUE;
++}
++
++static VOID
++hal_EfuseConstructPGPkt(
++ IN u8 offset,
++ IN u8 word_en,
++ IN u8 *pData,
++ IN PPGPKT_STRUCT pTargetPkt
++
++)
++{
++ _rtw_memset((PVOID)pTargetPkt->data, 0xFF, sizeof(u8)*8);
++ pTargetPkt->offset = offset;
++ pTargetPkt->word_en= word_en;
++ efuse_WordEnableDataRead(word_en, pData, pTargetPkt->data);
++ pTargetPkt->word_cnts = Efuse_CalculateWordCnts(pTargetPkt->word_en);
++
++ //RTPRINT(FEEPROM, EFUSE_PG, ("hal_EfuseConstructPGPkt(), targetPkt, offset=%d, word_en=0x%x, word_cnts=%d\n", pTargetPkt->offset, pTargetPkt->word_en, pTargetPkt->word_cnts));
++}
++
++static BOOLEAN
++hal_EfuseCheckIfDatafollowed(
++ IN PADAPTER pAdapter,
++ IN u8 word_cnts,
++ IN u16 startAddr,
++ IN BOOLEAN bPseudoTest
++ )
++{
++ BOOLEAN bRet=_FALSE;
++ u8 i, efuse_data;
++
++ for(i=0; i<(word_cnts*2) ; i++)
++ {
++ if(efuse_OneByteRead(pAdapter, (startAddr+i) ,&efuse_data, bPseudoTest)&&(efuse_data != 0xFF))
++ bRet = _TRUE;
++ }
++
++ return bRet;
++}
++
++static BOOLEAN
++wordEnMatched(
++ IN PPGPKT_STRUCT pTargetPkt,
++ IN PPGPKT_STRUCT pCurPkt,
++ IN u8 *pWden
++)
++{
++ u8 match_word_en = 0x0F; // default all words are disabled
++ u8 i;
++
++ // check if the same words are enabled both target and current PG packet
++ if( ((pTargetPkt->word_en & BIT0) == 0) &&
++ ((pCurPkt->word_en & BIT0) == 0) )
++ {
++ match_word_en &= ~BIT0; // enable word 0
++ }
++ if( ((pTargetPkt->word_en & BIT1) == 0) &&
++ ((pCurPkt->word_en & BIT1) == 0) )
++ {
++ match_word_en &= ~BIT1; // enable word 1
++ }
++ if( ((pTargetPkt->word_en & BIT2) == 0) &&
++ ((pCurPkt->word_en & BIT2) == 0) )
++ {
++ match_word_en &= ~BIT2; // enable word 2
++ }
++ if( ((pTargetPkt->word_en & BIT3) == 0) &&
++ ((pCurPkt->word_en & BIT3) == 0) )
++ {
++ match_word_en &= ~BIT3; // enable word 3
++ }
++
++ *pWden = match_word_en;
++
++ if(match_word_en != 0xf)
++ return _TRUE;
++ else
++ return _FALSE;
++}
++
++static BOOLEAN
++hal_EfusePartialWriteCheck(
++ IN PADAPTER pAdapter,
++ IN u8 efuseType,
++ IN u16 *pAddr,
++ IN PPGPKT_STRUCT pTargetPkt,
++ IN BOOLEAN bPseudoTest
++ )
++{
++ BOOLEAN bRet=_FALSE;
++ u8 i, efuse_data=0, cur_header=0;
++ u8 new_wden=0, matched_wden=0, badworden=0;
++ u16 startAddr=0, efuse_max_available_len=0, efuse_max=0;
++ PGPKT_STRUCT curPkt;
++
++ EFUSE_GetEfuseDefinition(pAdapter, efuseType, TYPE_AVAILABLE_EFUSE_BYTES_BANK, (PVOID)&efuse_max_available_len, bPseudoTest);
++ EFUSE_GetEfuseDefinition(pAdapter, efuseType, TYPE_EFUSE_REAL_CONTENT_LEN, (PVOID)&efuse_max, bPseudoTest);
++
++ if(efuseType == EFUSE_WIFI)
++ {
++ if(bPseudoTest)
++ {
++ startAddr = (u16)(fakeEfuseUsedBytes%EFUSE_REAL_CONTENT_LEN);
++ }
++ else
++ {
++ rtw_hal_get_hwreg(pAdapter, HW_VAR_EFUSE_BYTES, (u8 *)&startAddr);
++ startAddr%=EFUSE_REAL_CONTENT_LEN;
++ }
++ }
++ else
++ {
++ if(bPseudoTest)
++ {
++ startAddr = (u16)(fakeBTEfuseUsedBytes%EFUSE_REAL_CONTENT_LEN);
++ }
++ else
++ {
++ startAddr = (u16)(BTEfuseUsedBytes%EFUSE_REAL_CONTENT_LEN);
++ }
++ }
++ //RTPRINT(FEEPROM, EFUSE_PG, ("hal_EfusePartialWriteCheck(), startAddr=%d\n", startAddr));
++
++ while(1)
++ {
++ if(startAddr >= efuse_max_available_len)
++ {
++ bRet = _FALSE;
++ break;
++ }
++
++ if(efuse_OneByteRead(pAdapter, startAddr, &efuse_data, bPseudoTest) && (efuse_data!=0xFF))
++ {
++ if(EXT_HEADER(efuse_data))
++ {
++ cur_header = efuse_data;
++ startAddr++;
++ efuse_OneByteRead(pAdapter, startAddr, &efuse_data, bPseudoTest);
++ if(ALL_WORDS_DISABLED(efuse_data))
++ {
++ //RTPRINT(FEEPROM, EFUSE_PG, ("Error condition, all words disabled"));
++ bRet = _FALSE;
++ break;
++ }
++ else
++ {
++ curPkt.offset = ((cur_header & 0xE0) >> 5) | ((efuse_data & 0xF0) >> 1);
++ curPkt.word_en = efuse_data & 0x0F;
++ }
++ }
++ else
++ {
++ cur_header = efuse_data;
++ curPkt.offset = (cur_header>>4) & 0x0F;
++ curPkt.word_en = cur_header & 0x0F;
++ }
++
++ curPkt.word_cnts = Efuse_CalculateWordCnts(curPkt.word_en);
++ // if same header is found but no data followed
++ // write some part of data followed by the header.
++ if( (curPkt.offset == pTargetPkt->offset) &&
++ (!hal_EfuseCheckIfDatafollowed(pAdapter, curPkt.word_cnts, startAddr+1, bPseudoTest)) &&
++ wordEnMatched(pTargetPkt, &curPkt, &matched_wden) )
++ {
++ //RTPRINT(FEEPROM, EFUSE_PG, ("Need to partial write data by the previous wrote header\n"));
++ // Here to write partial data
++ badworden = Efuse_WordEnableDataWrite(pAdapter, startAddr+1, matched_wden, pTargetPkt->data, bPseudoTest);
++ if(badworden != 0x0F)
++ {
++ u32 PgWriteSuccess=0;
++ // if write fail on some words, write these bad words again
++ if(efuseType == EFUSE_WIFI)
++ PgWriteSuccess = Efuse_PgPacketWrite(pAdapter, pTargetPkt->offset, badworden, pTargetPkt->data, bPseudoTest);
++ else
++ PgWriteSuccess = hal_EfusePgPacketWrite_BT(pAdapter, pTargetPkt->offset, badworden, pTargetPkt->data, bPseudoTest);
++
++ if(!PgWriteSuccess)
++ {
++ bRet = _FALSE; // write fail, return
++ break;
++ }
++ }
++ // partial write ok, update the target packet for later use
++ for(i=0; i<4; i++)
++ {
++ if((matched_wden & (0x1<<i)) == 0) // this word has been written
++ {
++ pTargetPkt->word_en |= (0x1<<i); // disable the word
++ }
++ }
++ pTargetPkt->word_cnts = Efuse_CalculateWordCnts(pTargetPkt->word_en);
++ }
++ // read from next header
++ startAddr = startAddr + (curPkt.word_cnts*2) +1;
++ }
++ else
++ {
++ // not used header, 0xff
++ *pAddr = startAddr;
++ //RTPRINT(FEEPROM, EFUSE_PG, ("Started from unused header offset=%d\n", startAddr));
++ bRet = _TRUE;
++ break;
++ }
++ }
++ return bRet;
++}
++
++static BOOLEAN
++hal_EfusePgPacketWrite_BT(
++ IN PADAPTER pAdapter,
++ IN u8 offset,
++ IN u8 word_en,
++ IN u8 *pData,
++ IN BOOLEAN bPseudoTest
++ )
++{
++ PGPKT_STRUCT targetPkt;
++ u16 startAddr=0;
++ u8 efuseType=EFUSE_BT;
++
++ if(!hal_EfusePgCheckAvailableAddr(pAdapter, efuseType, bPseudoTest))
++ return _FALSE;
++
++ hal_EfuseConstructPGPkt(offset, word_en, pData, &targetPkt);
++
++ if(!hal_EfusePartialWriteCheck(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
++ return _FALSE;
++
++ if(!hal_EfusePgPacketWriteHeader(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
++ return _FALSE;
++
++ if(!hal_EfusePgPacketWriteData(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
++ return _FALSE;
++
++ return _TRUE;
++}
++
++static BOOLEAN
++hal_EfusePgPacketWrite_8723(
++ IN PADAPTER pAdapter,
++ IN u8 offset,
++ IN u8 word_en,
++ IN u8 *pData,
++ IN BOOLEAN bPseudoTest
++ )
++{
++ PGPKT_STRUCT targetPkt;
++ u16 startAddr=0;
++ u8 efuseType=EFUSE_WIFI;
++
++ if(!hal_EfusePgCheckAvailableAddr(pAdapter, efuseType, bPseudoTest))
++ return _FALSE;
++
++ hal_EfuseConstructPGPkt(offset, word_en, pData, &targetPkt);
++
++ if(!hal_EfusePartialWriteCheck(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
++ return _FALSE;
++
++ if(!hal_EfusePgPacketWriteHeader(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
++ return _FALSE;
++
++ if(!hal_EfusePgPacketWriteData(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
++ return _FALSE;
++
++ return _TRUE;
++}
++
++static int
++hal_EfusePgPacketWrite_8192C(IN PADAPTER pAdapter,
++ IN u8 offset,
++ IN u8 word_en,
++ IN u8 *data,
++ IN BOOLEAN bPseudoTest)
++{
++ u8 WriteState = PG_STATE_HEADER;
++
++ int bContinual = _TRUE,bDataEmpty=_TRUE, bResult = _TRUE;
++ u16 efuse_addr = 0;
++ u8 efuse_data;
++
++ u8 pg_header = 0;
++
++ u8 tmp_word_cnts=0,target_word_cnts=0;
++ u8 tmp_header,match_word_en,tmp_word_en;
++
++ PGPKT_STRUCT target_pkt;
++ PGPKT_STRUCT tmp_pkt;
++
++ u8 originaldata[sizeof(u8)*8];
++ u8 tmpindex = 0,badworden = 0x0F;
++
++ static int repeat_times = 0;
++ u8 efuseType=EFUSE_WIFI;
++
++ //
++ // <Roger_Notes> Efuse has been pre-programmed dummy 5Bytes at the end of Efuse by CP.
++ // So we have to prevent unexpected data string connection, which will cause
++ // incorrect data auto-load from HW. The total size is equal or smaller than 498bytes
++ // (i.e., offset 0~497, and dummy 1bytes) expected after CP test.
++ // 2009.02.19.
++ //
++ if( Efuse_GetCurrentSize(pAdapter, efuseType, bPseudoTest) >= (EFUSE_REAL_CONTENT_LEN-EFUSE_OOB_PROTECT_BYTES))
++ {
++ //RTPRINT(FEEPROM, EFUSE_PG, ("hal_EfusePgPacketWrite_8192C(), over size\n"));
++ return _FALSE;
++ }
++
++ // Init the 8 bytes content as 0xff
++ target_pkt.offset = offset;
++ target_pkt.word_en= word_en;
++
++ _rtw_memset((PVOID)target_pkt.data, 0xFF, sizeof(u8)*8);
++
++ efuse_WordEnableDataRead(word_en,data,target_pkt.data);
++ target_word_cnts = Efuse_CalculateWordCnts(target_pkt.word_en);
++
++ //efuse_reg_ctrl(pAdapter,_TRUE);//power on
++ //RTPRINT(FEEPROM, EFUSE_PG, ("EFUSE Power ON\n"));
++
++ //
++ // <Roger_Notes> Efuse has been pre-programmed dummy 5Bytes at the end of Efuse by CP.
++ // So we have to prevent unexpected data string connection, which will cause
++ // incorrect data auto-load from HW. Dummy 1bytes is additional.
++ // 2009.02.19.
++ //
++ while( bContinual && (efuse_addr < (EFUSE_REAL_CONTENT_LEN-EFUSE_OOB_PROTECT_BYTES)) )
++ {
++
++ if(WriteState==PG_STATE_HEADER)
++ {
++ bDataEmpty=_TRUE;
++ badworden = 0x0F;
++ //************ so *******************
++ //RTPRINT(FEEPROM, EFUSE_PG, ("EFUSE PG_STATE_HEADER\n"));
++ if ( efuse_OneByteRead(pAdapter, efuse_addr ,&efuse_data, bPseudoTest) &&
++ (efuse_data!=0xFF))
++ {
++ tmp_header = efuse_data;
++
++ tmp_pkt.offset = (tmp_header>>4) & 0x0F;
++ tmp_pkt.word_en = tmp_header & 0x0F;
++ tmp_word_cnts = Efuse_CalculateWordCnts(tmp_pkt.word_en);
++
++ //************ so-1 *******************
++ if(tmp_pkt.offset != target_pkt.offset)
++ {
++ efuse_addr = efuse_addr + (tmp_word_cnts*2) +1; //Next pg_packet
++ #if (EFUSE_ERROE_HANDLE == 1)
++ WriteState = PG_STATE_HEADER;
++ #endif
++ }
++ else
++ {
++ //************ so-2 *******************
++ for(tmpindex=0 ; tmpindex<(tmp_word_cnts*2) ; tmpindex++)
++ {
++ if(efuse_OneByteRead(pAdapter, (efuse_addr+1+tmpindex) ,&efuse_data, bPseudoTest)&&(efuse_data != 0xFF)){
++ bDataEmpty = _FALSE;
++ }
++ }
++ //************ so-2-1 *******************
++ if(bDataEmpty == _FALSE)
++ {
++ efuse_addr = efuse_addr + (tmp_word_cnts*2) +1; //Next pg_packet
++ #if (EFUSE_ERROE_HANDLE == 1)
++ WriteState=PG_STATE_HEADER;
++ #endif
++ }
++ else
++ {//************ so-2-2 *******************
++ match_word_en = 0x0F;
++ if( !( (target_pkt.word_en&BIT0)|(tmp_pkt.word_en&BIT0) ))
++ {
++ match_word_en &= (~BIT0);
++ }
++ if( !( (target_pkt.word_en&BIT1)|(tmp_pkt.word_en&BIT1) ))
++ {
++ match_word_en &= (~BIT1);
++ }
++ if( !( (target_pkt.word_en&BIT2)|(tmp_pkt.word_en&BIT2) ))
++ {
++ match_word_en &= (~BIT2);
++ }
++ if( !( (target_pkt.word_en&BIT3)|(tmp_pkt.word_en&BIT3) ))
++ {
++ match_word_en &= (~BIT3);
++ }
++
++ //************ so-2-2-A *******************
++ if((match_word_en&0x0F)!=0x0F)
++ {
++ badworden = Efuse_WordEnableDataWrite(pAdapter,efuse_addr+1, tmp_pkt.word_en ,target_pkt.data, bPseudoTest);
++
++ //************ so-2-2-A-1 *******************
++ //############################
++ if(0x0F != (badworden&0x0F))
++ {
++ u8 reorg_offset = offset;
++ u8 reorg_worden=badworden;
++ Efuse_PgPacketWrite(pAdapter,reorg_offset,reorg_worden,originaldata, bPseudoTest);
++ }
++ //############################
++
++ tmp_word_en = 0x0F;
++ if( (target_pkt.word_en&BIT0)^(match_word_en&BIT0) )
++ {
++ tmp_word_en &= (~BIT0);
++ }
++ if( (target_pkt.word_en&BIT1)^(match_word_en&BIT1) )
++ {
++ tmp_word_en &= (~BIT1);
++ }
++ if( (target_pkt.word_en&BIT2)^(match_word_en&BIT2) )
++ {
++ tmp_word_en &= (~BIT2);
++ }
++ if( (target_pkt.word_en&BIT3)^(match_word_en&BIT3) )
++ {
++ tmp_word_en &=(~BIT3);
++ }
++
++ //************ so-2-2-A-2 *******************
++ if((tmp_word_en&0x0F)!=0x0F){
++ //reorganize other pg packet
++ //efuse_addr = efuse_addr + (2*tmp_word_cnts) +1;//next pg packet addr
++ efuse_addr = Efuse_GetCurrentSize(pAdapter, efuseType, bPseudoTest);
++ //===========================
++ target_pkt.offset = offset;
++ target_pkt.word_en= tmp_word_en;
++ //===========================
++ }else{
++ bContinual = _FALSE;
++ }
++ #if (EFUSE_ERROE_HANDLE == 1)
++ WriteState=PG_STATE_HEADER;
++ repeat_times++;
++ if(repeat_times>EFUSE_REPEAT_THRESHOLD_){
++ bContinual = _FALSE;
++ bResult = _FALSE;
++ }
++ #endif
++ }
++ else{//************ so-2-2-B *******************
++ //reorganize other pg packet
++ efuse_addr = efuse_addr + (2*tmp_word_cnts) +1;//next pg packet addr
++ //===========================
++ target_pkt.offset = offset;
++ target_pkt.word_en= target_pkt.word_en;
++ //===========================
++ #if (EFUSE_ERROE_HANDLE == 1)
++ WriteState=PG_STATE_HEADER;
++ #endif
++ }
++ }
++ }
++ //RTPRINT(FEEPROM, EFUSE_PG, ("EFUSE PG_STATE_HEADER-1\n"));
++ }
++ else //************ s1: header == oxff *******************
++ {
++ pg_header = ((target_pkt.offset << 4)&0xf0) |target_pkt.word_en;
++
++ efuse_OneByteWrite(pAdapter,efuse_addr, pg_header, bPseudoTest);
++ efuse_OneByteRead(pAdapter,efuse_addr, &tmp_header, bPseudoTest);
++
++ if(tmp_header == pg_header)
++ { //************ s1-1*******************
++ WriteState = PG_STATE_DATA;
++ }
++ #if (EFUSE_ERROE_HANDLE == 1)
++ else if(tmp_header == 0xFF){//************ s1-3: if Write or read func doesn't work *******************
++ //efuse_addr doesn't change
++ WriteState = PG_STATE_HEADER;
++ repeat_times++;
++ if(repeat_times>EFUSE_REPEAT_THRESHOLD_){
++ bContinual = _FALSE;
++ bResult = _FALSE;
++ }
++ }
++ #endif
++ else
++ {//************ s1-2 : fixed the header procedure *******************
++ tmp_pkt.offset = (tmp_header>>4) & 0x0F;
++ tmp_pkt.word_en= tmp_header & 0x0F;
++ tmp_word_cnts = Efuse_CalculateWordCnts(tmp_pkt.word_en);
++
++ //************ s1-2-A :cover the exist data *******************
++ //memset(originaldata,0xff,sizeof(UINT8)*8);
++ _rtw_memset((PVOID)originaldata, 0xff, sizeof(u8)*8);
++
++ if(Efuse_PgPacketRead( pAdapter, tmp_pkt.offset,originaldata, bPseudoTest))
++ { //check if data exist
++ //efuse_reg_ctrl(pAdapter,_TRUE);//power on
++ badworden = Efuse_WordEnableDataWrite(pAdapter,efuse_addr+1,tmp_pkt.word_en,originaldata, bPseudoTest);
++ //############################
++ if(0x0F != (badworden&0x0F))
++ {
++ u8 reorg_offset = tmp_pkt.offset;
++ u8 reorg_worden=badworden;
++ Efuse_PgPacketWrite(pAdapter,reorg_offset,reorg_worden,originaldata, bPseudoTest);
++ efuse_addr = Efuse_GetCurrentSize(pAdapter, efuseType, bPseudoTest);
++ }
++ //############################
++ else{
++ efuse_addr = efuse_addr + (tmp_word_cnts*2) +1; //Next pg_packet
++ }
++ }
++ //************ s1-2-B: wrong address*******************
++ else
++ {
++ efuse_addr = efuse_addr + (tmp_word_cnts*2) +1; //Next pg_packet
++ }
++
++ #if (EFUSE_ERROE_HANDLE == 1)
++ WriteState=PG_STATE_HEADER;
++ repeat_times++;
++ if(repeat_times>EFUSE_REPEAT_THRESHOLD_){
++ bContinual = _FALSE;
++ bResult = _FALSE;
++ }
++ #endif
++
++ //RTPRINT(FEEPROM, EFUSE_PG, ("EFUSE PG_STATE_HEADER-2\n"));
++ }
++
++ }
++
++ }
++ //write data state
++ else if(WriteState==PG_STATE_DATA)
++ { //************ s1-1 *******************
++ //RTPRINT(FEEPROM, EFUSE_PG, ("EFUSE PG_STATE_DATA\n"));
++ badworden = 0x0f;
++ badworden = Efuse_WordEnableDataWrite(pAdapter,efuse_addr+1,target_pkt.word_en,target_pkt.data, bPseudoTest);
++ if((badworden&0x0F)==0x0F)
++ { //************ s1-1-A *******************
++ bContinual = _FALSE;
++ }
++ else
++ {//reorganize other pg packet //************ s1-1-B *******************
++ efuse_addr = efuse_addr + (2*target_word_cnts) +1;//next pg packet addr
++
++ //===========================
++ target_pkt.offset = offset;
++ target_pkt.word_en= badworden;
++ target_word_cnts = Efuse_CalculateWordCnts(target_pkt.word_en);
++ //===========================
++ #if (EFUSE_ERROE_HANDLE == 1)
++ WriteState=PG_STATE_HEADER;
++ repeat_times++;
++ if(repeat_times>EFUSE_REPEAT_THRESHOLD_){
++ bContinual = _FALSE;
++ bResult = _FALSE;
++ }
++ #endif
++ //RTPRINT(FEEPROM, EFUSE_PG, ("EFUSE PG_STATE_HEADER-3\n"));
++ }
++ }
++ }
++
++ if(efuse_addr >= (EFUSE_REAL_CONTENT_LEN-EFUSE_OOB_PROTECT_BYTES))
++ {
++ //RT_TRACE(COMP_EFUSE, DBG_LOUD, ("hal_EfusePgPacketWrite_8192C(): efuse_addr(%#x) Out of size!!\n", efuse_addr));
++ }
++ //efuse_reg_ctrl(pAdapter,_FALSE);//power off
++
++ return _TRUE;
++}
++
++static int
++Hal_EfusePgPacketWrite_Pseudo(IN PADAPTER pAdapter,
++ IN u8 offset,
++ IN u8 word_en,
++ IN u8 *data,
++ IN BOOLEAN bPseudoTest)
++{
++ int ret;
++
++ ret = hal_EfusePgPacketWrite_8723(pAdapter, offset, word_en, data, bPseudoTest);
++
++ return ret;
++}
++
++static int
++Hal_EfusePgPacketWrite(IN PADAPTER pAdapter,
++ IN u8 offset,
++ IN u8 word_en,
++ IN u8 *data,
++ IN BOOLEAN bPseudoTest)
++{
++ int ret=0;
++
++ if(IS_HARDWARE_TYPE_8192C(pAdapter))
++ {
++ ret = hal_EfusePgPacketWrite_8192C(pAdapter, offset, word_en, data, bPseudoTest);
++ }
++ else if(IS_HARDWARE_TYPE_8723A(pAdapter))
++ {
++ ret = hal_EfusePgPacketWrite_8723(pAdapter, offset, word_en, data, bPseudoTest);
++ }
++
++ return ret;
++}
++
++static int
++rtl8192c_Efuse_PgPacketWrite(IN PADAPTER pAdapter,
++ IN u8 offset,
++ IN u8 word_en,
++ IN u8 *data,
++ IN BOOLEAN bPseudoTest)
++{
++ int ret;
++
++ if(bPseudoTest)
++ {
++ ret = Hal_EfusePgPacketWrite_Pseudo(pAdapter, offset, word_en, data, bPseudoTest);
++ }
++ else
++ {
++ ret = Hal_EfusePgPacketWrite(pAdapter, offset, word_en, data, bPseudoTest);
++ }
++ return ret;
++}
++
++VOID
++rtl8192c_EfuseParseIDCode(
++ IN PADAPTER pAdapter,
++ IN u8 *hwinfo
++ )
++{
++ EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(pAdapter);
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
++ u16 i,EEPROMId;
++
++ // Checl 0x8129 again for making sure autoload status!!
++ EEPROMId = *((u16 *)&hwinfo[0]);
++ if( le16_to_cpu(EEPROMId) != RTL_EEPROM_ID)
++ {
++ DBG_8192C("EEPROM ID(%#x) is invalid!!\n", EEPROMId);
++ pEEPROM->bautoload_fail_flag = _TRUE;
++ }
++ else
++ {
++ pEEPROM->bautoload_fail_flag = _FALSE;
++ }
++
++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("EEPROM ID = 0x%4x\n", EEPROMId));
++}
++
++void rtl8192c_read_chip_version(PADAPTER pAdapter)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
++ pHalData->VersionID = rtl8192c_ReadChipVersion(pAdapter);
++}
++
++void hal_notch_filter_8192c(_adapter *adapter, bool enable)
++{
++ if (enable) {
++ DBG_871X("Enable notch filter\n");
++ rtw_write8(adapter, rOFDM0_RxDSP+1, rtw_read8(adapter, rOFDM0_RxDSP+1) | BIT1);
++ } else {
++ DBG_871X("Disable notch filter\n");
++ rtw_write8(adapter, rOFDM0_RxDSP+1, rtw_read8(adapter, rOFDM0_RxDSP+1) & ~BIT1);
++ }
++}
++
++void hal_reset_security_engine_8192c(_adapter * adapter)
++{
++ rtw_write8(adapter, 0x522, 0xFF);
++ rtw_write8(adapter, 0x21, 0x35);
++ rtw_usleep_os(300);
++ rtw_write8(adapter, 0x101, rtw_read8(adapter,0x101)&~0x02);
++ rtw_write8(adapter, 0x101, rtw_read8(adapter,0x101)|0x02);
++ rtw_write8(adapter, 0x21, 0x55);
++ rtw_write8(adapter, 0x522, 0x00);
++}
++
++s32 c2h_id_filter_ccx_8192c(u8 id)
++{
++ s32 ret = _FALSE;
++ if (id == C2H_CCX_TX_RPT)
++ ret = _TRUE;
++
++ return ret;
++}
++
++static s32 c2h_handler_8192c(_adapter *padapter, struct c2h_evt_hdr *c2h_evt)
++{
++ s32 ret = _SUCCESS;
++ u8 i = 0;
++
++ if (c2h_evt == NULL) {
++ DBG_8192C("%s c2h_evt is NULL\n",__FUNCTION__);
++ ret = _FAIL;
++ goto exit;
++ }
++
++ switch (c2h_evt->id) {
++ case C2H_CCX_TX_RPT:
++ handle_txrpt_ccx_8192c(padapter, c2h_evt->payload);
++ break;
++ default:
++ ret = _FAIL;
++ break;
++ }
++
++exit:
++ return ret;
++}
++
++void rtl8192c_set_hal_ops(struct hal_ops *pHalFunc)
++{
++ pHalFunc->free_hal_data = &rtl8192c_free_hal_data;
++
++ pHalFunc->dm_init = &rtl8192c_init_dm_priv;
++ pHalFunc->dm_deinit = &rtl8192c_deinit_dm_priv;
++ pHalFunc->read_chip_version = &rtl8192c_read_chip_version;
++
++ pHalFunc->set_bwmode_handler = &PHY_SetBWMode8192C;
++ pHalFunc->set_channel_handler = &PHY_SwChnl8192C;
++
++ pHalFunc->hal_dm_watchdog = &rtl8192c_HalDmWatchDog;
++
++ pHalFunc->Add_RateATid = &rtl8192c_Add_RateATid;
++
++#ifdef CONFIG_ANTENNA_DIVERSITY
++ pHalFunc->AntDivBeforeLinkHandler = &SwAntDivBeforeLink8192C;
++ pHalFunc->AntDivCompareHandler = &SwAntDivCompare8192C;
++#endif
++
++ pHalFunc->read_bbreg = &rtl8192c_PHY_QueryBBReg;
++ pHalFunc->write_bbreg = &rtl8192c_PHY_SetBBReg;
++ pHalFunc->read_rfreg = &rtl8192c_PHY_QueryRFReg;
++ pHalFunc->write_rfreg = &rtl8192c_PHY_SetRFReg;
++
++ //Efuse related function
++ pHalFunc->EfusePowerSwitch = &rtl8192c_EfusePowerSwitch;
++ pHalFunc->ReadEFuse = &rtl8192c_ReadEFuse;
++ pHalFunc->EFUSEGetEfuseDefinition = &rtl8192c_EFUSE_GetEfuseDefinition;
++ pHalFunc->EfuseGetCurrentSize = &rtl8192c_EfuseGetCurrentSize;
++ pHalFunc->Efuse_PgPacketRead = &rtl8192c_Efuse_PgPacketRead;
++ pHalFunc->Efuse_PgPacketWrite = &rtl8192c_Efuse_PgPacketWrite;
++ pHalFunc->Efuse_WordEnableDataWrite = &rtl8192c_Efuse_WordEnableDataWrite;
++
++#ifdef DBG_CONFIG_ERROR_DETECT
++ pHalFunc->sreset_init_value = &sreset_init_value;
++ pHalFunc->sreset_reset_value = &sreset_reset_value;
++ pHalFunc->silentreset = &sreset_reset;
++ pHalFunc->sreset_xmit_status_check = &rtl8192c_sreset_xmit_status_check;
++ pHalFunc->sreset_linked_status_check = &rtl8192c_sreset_linked_status_check;
++ pHalFunc->sreset_get_wifi_status = &sreset_get_wifi_status;
++ pHalFunc->sreset_inprogress= &sreset_inprogress;
++#endif
++
++#ifdef CONFIG_IOL
++ pHalFunc->IOL_exec_cmds_sync = &rtl8192c_IOL_exec_cmds_sync;
++#endif
++ pHalFunc->hal_notch_filter = &hal_notch_filter_8192c;
++ pHalFunc->hal_reset_security_engine = hal_reset_security_engine_8192c;
++
++ pHalFunc->c2h_handler = c2h_handler_8192c;
++ pHalFunc->c2h_id_filter_ccx = c2h_id_filter_ccx_8192c;
++}
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/hal/rtl8192c/rtl8192c_mp.c linux-xbian-rpi/drivers/net/wireless/rtl8192cu/hal/rtl8192c/rtl8192c_mp.c
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/hal/rtl8192c/rtl8192c_mp.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/hal/rtl8192c/rtl8192c_mp.c 2015-07-28 01:20:58.309639981 +0200
+@@ -0,0 +1,1207 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#define _RTL8192C_MP_C_
++#ifdef CONFIG_MP_INCLUDED
++
++#include <drv_types.h>
++#include <rtw_mp.h>
++
++#ifdef CONFIG_RTL8192C
++#include <rtl8192c_hal.h>
++#endif
++
++
++
++s32 Hal_SetPowerTracking(PADAPTER padapter, u8 enable)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++ struct dm_priv *pdmpriv = &pHalData->dmpriv;
++
++
++ if (!netif_running(padapter->pnetdev)) {
++ RT_TRACE(_module_mp_, _drv_warning_, ("SetPowerTracking! Fail: interface not opened!\n"));
++ return _FAIL;
++ }
++
++ if (check_fwstate(&padapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {
++ RT_TRACE(_module_mp_, _drv_warning_, ("SetPowerTracking! Fail: not in MP mode!\n"));
++ return _FAIL;
++ }
++
++ if (enable)
++ pdmpriv->TxPowerTrackControl = _TRUE;
++ else
++ pdmpriv->TxPowerTrackControl = _FALSE;
++
++ return _SUCCESS;
++}
++
++void Hal_GetPowerTracking(PADAPTER padapter, u8 *enable)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++ struct dm_priv *pdmpriv = &pHalData->dmpriv;
++
++
++ *enable = pdmpriv->TxPowerTrackControl;
++}
++
++static void Hal_disable_dm(PADAPTER padapter)
++{
++ u8 v8;
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++ struct dm_priv *pdmpriv = &pHalData->dmpriv;
++
++
++ //3 1. disable firmware dynamic mechanism
++ // disable Power Training, Rate Adaptive
++ v8 = rtw_read8(padapter, REG_BCN_CTRL);
++ v8 &= ~EN_BCN_FUNCTION;
++ rtw_write8(padapter, REG_BCN_CTRL, v8);
++
++ //3 2. disable driver dynamic mechanism
++ // disable Dynamic Initial Gain
++ // disable High Power
++ // disable Power Tracking
++ Switch_DM_Func(padapter, DYNAMIC_FUNC_DISABLE, _FALSE);
++
++ // enable APK, LCK and IQK but disable power tracking
++ pdmpriv->TxPowerTrackControl = _FALSE;
++ Switch_DM_Func(padapter, DYNAMIC_FUNC_SS, _TRUE);
++}
++
++/*-----------------------------------------------------------------------------
++ * Function: mpt_SwitchRfSetting
++ *
++ * Overview: Change RF Setting when we siwthc channel/rate/BW for MP.
++ *
++ * Input: IN PADAPTER pAdapter
++ *
++ * Output: NONE
++ *
++ * Return: NONE
++ *
++ * Revised History:
++ * When Who Remark
++ * 01/08/2009 MHC Suggestion from SD3 Willis for 92S series.
++ * 01/09/2009 MHC Add CCK modification for 40MHZ. Suggestion from SD3.
++ *
++ *---------------------------------------------------------------------------*/
++void Hal_mpt_SwitchRfSetting(PADAPTER pAdapter)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
++ struct mp_priv *pmp = &pAdapter->mppriv;
++ u8 ChannelToSw = pmp->channel, eRFPath = RF_PATH_A;
++ u8 ulRateIdx = pmp->rateidx;
++ u8 ulbandwidth = pmp->bandwidth;
++ PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
++ BOOLEAN bInteralPA = _FALSE;
++ u32 value = 0;
++
++#ifdef CONFIG_USB_HCI
++ if (IS_92C_SERIAL(pHalData->VersionID))
++ {
++ //92CE-VAU (92cu mCard)
++ if( BOARD_MINICARD == pHalData->BoardType)
++ {
++ if (ulRateIdx < MPT_RATE_6M) // CCK rate
++ {
++ write_rfreg(pAdapter, 0, RF_SYN_G2, 0x0F400);
++ }
++ else //OFDM~MCS rate
++ {
++ write_rfreg(pAdapter, 0, RF_SYN_G2, 0x4F000);
++ }
++ }
++ else //92CU dongle
++ {
++ if (ulRateIdx < MPT_RATE_6M) // CCK rate
++ {
++ write_rfreg(pAdapter, 0, RF_SYN_G2, 0x0F400);
++ }
++ else if (ChannelToSw & BIT0) // OFDM rate, odd number channel
++ {
++ write_rfreg(pAdapter, 0, RF_SYN_G2, 0x4F200);
++ }
++ else if (ChannelToSw == 4) // OFDM rate, even number channel
++ {
++ write_rfreg(pAdapter, 0, RF_SYN_G2, 0x28200);
++ write_rfreg(pAdapter, 0, RF_SYN_G6, 0xe0004);
++ write_rfreg(pAdapter, 0, RF_SYN_G7, 0x709);
++ rtw_msleep_os(1);
++ write_rfreg(pAdapter, 0, RF_SYN_G7, 0x4B333);
++ }
++ else if(ChannelToSw == 10) // OFDM rate, even number channel
++ {
++ write_rfreg(pAdapter, 0, RF_SYN_G2, 0x28000);
++ write_rfreg(pAdapter, 0, RF_SYN_G6, 0xe000A);
++ write_rfreg(pAdapter, 0, RF_SYN_G7, 0x709);
++ rtw_msleep_os(1);
++ write_rfreg(pAdapter, 0, RF_SYN_G7, 0x7B333);
++ }
++ else if(ChannelToSw == 12) // OFDM rate, even number channel
++ {
++ write_rfreg(pAdapter, 0, RF_SYN_G2, 0x28200);
++ write_rfreg(pAdapter, 0, RF_SYN_G6, 0xe000C);
++ write_rfreg(pAdapter, 0, RF_SYN_G7, 0x50B);
++ rtw_msleep_os(1);
++ write_rfreg(pAdapter, 0, RF_SYN_G7, 0x4B333);
++ }
++ else
++ {
++ write_rfreg(pAdapter, 0, RF_SYN_G2, 0x4F200);
++ }
++ }
++ }
++ else //88cu
++ {
++
++ //mcard interface
++
++ if( BOARD_MINICARD == pHalData->BoardType)
++ {
++ if (ulRateIdx < MPT_RATE_6M) // CCK rate
++ {
++ write_rfreg(pAdapter, 0, RF_SYN_G2, 0x0F400);
++ }
++ else //OFDM~MCS rate
++ {
++ write_rfreg(pAdapter, 0, RF_SYN_G2, 0x4F200);
++ }
++
++ if(ChannelToSw == 6 || ChannelToSw == 8)
++ {
++ write_bbreg(pAdapter, rOFDM0_XAAGCCore1, bMaskByte0, 0x22);
++ write_bbreg(pAdapter, rOFDM0_XBAGCCore1, bMaskByte0, 0x22);
++ write_bbreg(pAdapter, rOFDM0_RxDetector1, bMaskByte0, 0x4F);
++ }
++ else
++ {
++ write_bbreg(pAdapter, rOFDM0_XAAGCCore1, bMaskByte0, 0x20);
++ write_bbreg(pAdapter, rOFDM0_XBAGCCore1, bMaskByte0, 0x20);
++ write_bbreg(pAdapter, rOFDM0_RxDetector1, bMaskByte0, pMptCtx->backup0xc30);
++ }
++ }
++ else
++ {
++ if (ulRateIdx < MPT_RATE_6M) // CCK rate
++ {
++ write_rfreg(pAdapter, 0, RF_SYN_G2, 0x0F400);
++ }
++ else if (ChannelToSw & BIT0) // OFDM rate, odd number channel
++ {
++ write_rfreg(pAdapter, 0, RF_SYN_G2, 0x4F200);
++ }
++ else
++ {
++ write_rfreg(pAdapter, 0, RF_SYN_G2, 0x4F000);
++ }
++ }
++ }
++
++#else //PCI_INTERFACE
++
++ if (ulRateIdx < MPT_RATE_6M) // CCK rate
++ {
++ write_rfreg(pAdapter, 0, RF_SYN_G2, 0x0F400);
++ }
++ else //OFDM~MCS rate
++ {
++ write_rfreg(pAdapter, 0, RF_SYN_G2, 0x4F000);
++ }
++ //88CE
++ if(!IS_92C_SERIAL(pHalData->VersionID))
++ {
++ if(ChannelToSw == 6 || ChannelToSw == 8)
++ {
++ write_bbreg(pAdapter, rOFDM0_XAAGCCore1, bMaskByte0, 0x22);
++ write_bbreg(pAdapter, rOFDM0_XBAGCCore1, bMaskByte0, 0x22);
++ write_bbreg(pAdapter, rOFDM0_RxDetector1, bMaskByte0, 0x4F);
++ }
++ else
++ {
++ write_bbreg(pAdapter, rOFDM0_XAAGCCore1, bMaskByte0, pMptCtx->backup0xc50);
++ write_bbreg(pAdapter, rOFDM0_XBAGCCore1, bMaskByte0, pMptCtx->backup0xc58);
++ write_bbreg(pAdapter, rOFDM0_RxDetector1, bMaskByte0, pMptCtx->backup0xc30);
++ }
++ }
++
++#endif //CONFIG_USB_HCI
++
++
++}
++/*---------------------------hal\rtl8192c\MPT_Phy.c---------------------------*/
++
++/*---------------------------hal\rtl8192c\MPT_HelperFunc.c---------------------------*/
++void Hal_MPT_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14)
++{
++ u32 TempVal = 0, TempVal2 = 0, TempVal3 = 0;
++ u32 CurrCCKSwingVal = 0, CCKSwingIndex = 12;
++ u8 i;
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++
++
++ // get current cck swing value and check 0xa22 & 0xa23 later to match the table.
++ CurrCCKSwingVal = read_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord);
++
++ if (!bInCH14)
++ {
++ // Readback the current bb cck swing value and compare with the table to
++ // get the current swing index
++ for (i = 0; i < CCK_TABLE_SIZE; i++)
++ {
++ if (((CurrCCKSwingVal&0xff) == (u32)CCKSwingTable_Ch1_Ch13[i][0]) &&
++ (((CurrCCKSwingVal&0xff00)>>8) == (u32)CCKSwingTable_Ch1_Ch13[i][1]))
++ {
++ CCKSwingIndex = i;
++// RT_TRACE(COMP_INIT, DBG_LOUD,("Ch1~13, Current reg0x%x = 0x%lx, CCKSwingIndex=0x%x\n",
++// (rCCK0_TxFilter1+2), CurrCCKSwingVal, CCKSwingIndex));
++ break;
++ }
++ }
++
++ //Write 0xa22 0xa23
++ TempVal = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][0] +
++ (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][1]<<8) ;
++
++
++ //Write 0xa24 ~ 0xa27
++ TempVal2 = 0;
++ TempVal2 = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][2] +
++ (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][3]<<8) +
++ (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][4]<<16 )+
++ (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][5]<<24);
++
++ //Write 0xa28 0xa29
++ TempVal3 = 0;
++ TempVal3 = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][6] +
++ (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][7]<<8) ;
++ }
++ else
++ {
++ for (i = 0; i < CCK_TABLE_SIZE; i++)
++ {
++ if (((CurrCCKSwingVal&0xff) == (u32)CCKSwingTable_Ch14[i][0]) &&
++ (((CurrCCKSwingVal&0xff00)>>8) == (u32)CCKSwingTable_Ch14[i][1]))
++ {
++ CCKSwingIndex = i;
++// RT_TRACE(COMP_INIT, DBG_LOUD,("Ch14, Current reg0x%x = 0x%lx, CCKSwingIndex=0x%x\n",
++// (rCCK0_TxFilter1+2), CurrCCKSwingVal, CCKSwingIndex));
++ break;
++ }
++ }
++
++ //Write 0xa22 0xa23
++ TempVal = CCKSwingTable_Ch14[CCKSwingIndex][0] +
++ (CCKSwingTable_Ch14[CCKSwingIndex][1]<<8) ;
++
++ //Write 0xa24 ~ 0xa27
++ TempVal2 = 0;
++ TempVal2 = CCKSwingTable_Ch14[CCKSwingIndex][2] +
++ (CCKSwingTable_Ch14[CCKSwingIndex][3]<<8) +
++ (CCKSwingTable_Ch14[CCKSwingIndex][4]<<16 )+
++ (CCKSwingTable_Ch14[CCKSwingIndex][5]<<24);
++
++ //Write 0xa28 0xa29
++ TempVal3 = 0;
++ TempVal3 = CCKSwingTable_Ch14[CCKSwingIndex][6] +
++ (CCKSwingTable_Ch14[CCKSwingIndex][7]<<8) ;
++ }
++
++ write_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord, TempVal);
++ write_bbreg(Adapter, rCCK0_TxFilter2, bMaskDWord, TempVal2);
++ write_bbreg(Adapter, rCCK0_DebugPort, bMaskLWord, TempVal3);
++}
++
++void Hal_MPT_CCKTxPowerAdjustbyIndex(PADAPTER pAdapter, BOOLEAN beven)
++{
++ s32 TempCCk;
++ u8 CCK_index, CCK_index_old;
++ u8 Action = 0; //0: no action, 1: even->odd, 2:odd->even
++ u8 TimeOut = 100;
++ s32 i = 0;
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
++ PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.MptCtx;
++
++
++ if (!IS_92C_SERIAL(pHalData->VersionID))
++ return;
++#if 0
++ while(PlatformAtomicExchange(&Adapter->IntrCCKRefCount, TRUE) == TRUE)
++ {
++ PlatformSleepUs(100);
++ TimeOut--;
++ if(TimeOut <= 0)
++ {
++ RTPRINT(FINIT, INIT_TxPower,
++ ("!!!MPT_CCKTxPowerAdjustbyIndex Wait for check CCK gain index too long!!!\n" ));
++ break;
++ }
++ }
++#endif
++ if (beven && !pMptCtx->bMptIndexEven) //odd->even
++ {
++ Action = 2;
++ pMptCtx->bMptIndexEven = _TRUE;
++ }
++ else if (!beven && pMptCtx->bMptIndexEven) //even->odd
++ {
++ Action = 1;
++ pMptCtx->bMptIndexEven = _FALSE;
++ }
++
++ if (Action != 0)
++ {
++ //Query CCK default setting From 0xa24
++ TempCCk = read_bbreg(pAdapter, rCCK0_TxFilter2, bMaskDWord) & bMaskCCK;
++ for (i = 0; i < CCK_TABLE_SIZE; i++)
++ {
++ if (pHalData->dmpriv.bCCKinCH14)
++ {
++ if (_rtw_memcmp((void*)&TempCCk, (void*)&CCKSwingTable_Ch14[i][2], 4) == _TRUE)
++ {
++ CCK_index_old = (u8) i;
++// RTPRINT(FINIT, INIT_TxPower,("MPT_CCKTxPowerAdjustbyIndex: Initial reg0x%x = 0x%lx, CCK_index=0x%x, ch 14 %d\n",
++// rCCK0_TxFilter2, TempCCk, CCK_index_old, pHalData->bCCKinCH14));
++ break;
++ }
++ }
++ else
++ {
++ if (_rtw_memcmp((void*)&TempCCk, (void*)&CCKSwingTable_Ch1_Ch13[i][2], 4) == _TRUE)
++ {
++ CCK_index_old = (u8) i;
++// RTPRINT(FINIT, INIT_TxPower,("MPT_CCKTxPowerAdjustbyIndex: Initial reg0x%x = 0x%lx, CCK_index=0x%x, ch14 %d\n",
++// rCCK0_TxFilter2, TempCCk, CCK_index_old, pHalData->bCCKinCH14));
++ break;
++ }
++ }
++ }
++
++ if (Action == 1)
++ CCK_index = CCK_index_old - 1;
++ else
++ CCK_index = CCK_index_old + 1;
++
++// RTPRINT(FINIT, INIT_TxPower,("MPT_CCKTxPowerAdjustbyIndex: new CCK_index=0x%x\n",
++// CCK_index));
++
++ //Adjust CCK according to gain index
++ if (!pHalData->dmpriv.bCCKinCH14) {
++ rtw_write8(pAdapter, 0xa22, CCKSwingTable_Ch1_Ch13[CCK_index][0]);
++ rtw_write8(pAdapter, 0xa23, CCKSwingTable_Ch1_Ch13[CCK_index][1]);
++ rtw_write8(pAdapter, 0xa24, CCKSwingTable_Ch1_Ch13[CCK_index][2]);
++ rtw_write8(pAdapter, 0xa25, CCKSwingTable_Ch1_Ch13[CCK_index][3]);
++ rtw_write8(pAdapter, 0xa26, CCKSwingTable_Ch1_Ch13[CCK_index][4]);
++ rtw_write8(pAdapter, 0xa27, CCKSwingTable_Ch1_Ch13[CCK_index][5]);
++ rtw_write8(pAdapter, 0xa28, CCKSwingTable_Ch1_Ch13[CCK_index][6]);
++ rtw_write8(pAdapter, 0xa29, CCKSwingTable_Ch1_Ch13[CCK_index][7]);
++ } else {
++ rtw_write8(pAdapter, 0xa22, CCKSwingTable_Ch14[CCK_index][0]);
++ rtw_write8(pAdapter, 0xa23, CCKSwingTable_Ch14[CCK_index][1]);
++ rtw_write8(pAdapter, 0xa24, CCKSwingTable_Ch14[CCK_index][2]);
++ rtw_write8(pAdapter, 0xa25, CCKSwingTable_Ch14[CCK_index][3]);
++ rtw_write8(pAdapter, 0xa26, CCKSwingTable_Ch14[CCK_index][4]);
++ rtw_write8(pAdapter, 0xa27, CCKSwingTable_Ch14[CCK_index][5]);
++ rtw_write8(pAdapter, 0xa28, CCKSwingTable_Ch14[CCK_index][6]);
++ rtw_write8(pAdapter, 0xa29, CCKSwingTable_Ch14[CCK_index][7]);
++ }
++ }
++#if 0
++ RTPRINT(FINIT, INIT_TxPower,
++ ("MPT_CCKTxPowerAdjustbyIndex 0xa20=%x\n", PlatformEFIORead4Byte(Adapter, 0xa20)));
++
++ PlatformAtomicExchange(&Adapter->IntrCCKRefCount, FALSE);
++#endif
++}
++/*---------------------------hal\rtl8192c\MPT_HelperFunc.c---------------------------*/
++
++/*
++ * SetChannel
++ * Description
++ * Use H2C command to change channel,
++ * not only modify rf register, but also other setting need to be done.
++ */
++void Hal_SetChannel(PADAPTER pAdapter)
++{
++#if 0
++ struct mp_priv *pmp = &pAdapter->mppriv;
++
++// SelectChannel(pAdapter, pmp->channel);
++ set_channel_bwmode(pAdapter, pmp->channel, pmp->channel_offset, pmp->bandwidth);
++#else
++ u8 eRFPath;
++
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
++ struct mp_priv *pmp = &pAdapter->mppriv;
++ u8 channel = pmp->channel;
++ u8 bandwidth = pmp->bandwidth;
++ u8 rate = pmp->rateidx;
++
++
++ // set RF channel register
++ for (eRFPath = 0; eRFPath < pHalData->NumTotalRFPath; eRFPath++)
++ {
++ if(IS_HARDWARE_TYPE_8192D(pAdapter))
++ _write_rfreg(pAdapter, (RF_RADIO_PATH_E)eRFPath, rRfChannel, 0xFF, channel);
++ else
++ _write_rfreg(pAdapter, eRFPath, rRfChannel, 0x3FF, channel);
++ }
++ Hal_mpt_SwitchRfSetting(pAdapter);
++
++ SelectChannel(pAdapter, channel);
++
++ if (pHalData->CurrentChannel == 14 && !pHalData->dmpriv.bCCKinCH14) {
++ pHalData->dmpriv.bCCKinCH14 = _TRUE;
++ Hal_MPT_CCKTxPowerAdjust(pAdapter, pHalData->dmpriv.bCCKinCH14);
++ }
++ else if (pHalData->CurrentChannel != 14 && pHalData->dmpriv.bCCKinCH14) {
++ pHalData->dmpriv.bCCKinCH14 = _FALSE;
++ Hal_MPT_CCKTxPowerAdjust(pAdapter, pHalData->dmpriv.bCCKinCH14);
++ }
++
++#endif
++}
++
++/*
++ * Notice
++ * Switch bandwitdth may change center frequency(channel)
++ */
++void Hal_SetBandwidth(PADAPTER pAdapter)
++{
++ struct mp_priv *pmp = &pAdapter->mppriv;
++
++
++ SetBWMode(pAdapter, pmp->bandwidth, pmp->prime_channel_offset);
++ Hal_mpt_SwitchRfSetting(pAdapter);
++}
++
++void Hal_SetCCKTxPower(PADAPTER pAdapter, u8 *TxPower)
++{
++ u32 tmpval = 0;
++
++
++ // rf-A cck tx power
++ write_bbreg(pAdapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, TxPower[RF_PATH_A]);
++ tmpval = (TxPower[RF_PATH_A]<<16) | (TxPower[RF_PATH_A]<<8) | TxPower[RF_PATH_A];
++ write_bbreg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval);
++
++ // rf-B cck tx power
++ write_bbreg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, TxPower[RF_PATH_B]);
++ tmpval = (TxPower[RF_PATH_B]<<16) | (TxPower[RF_PATH_B]<<8) | TxPower[RF_PATH_B];
++ write_bbreg(pAdapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, tmpval);
++
++ RT_TRACE(_module_mp_, _drv_notice_,
++ ("-SetCCKTxPower: A[0x%02x] B[0x%02x]\n",
++ TxPower[RF_PATH_A], TxPower[RF_PATH_B]));
++}
++
++void Hal_SetOFDMTxPower(PADAPTER pAdapter, u8 *TxPower)
++{
++ u32 TxAGC = 0;
++ u8 tmpval = 0;
++ PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.MptCtx;
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
++
++
++ // HT Tx-rf(A)
++ tmpval = TxPower[RF_PATH_A];
++ TxAGC = (tmpval<<24) | (tmpval<<16) | (tmpval<<8) | tmpval;
++
++ write_bbreg(pAdapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC);
++ write_bbreg(pAdapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC);
++ write_bbreg(pAdapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC);
++ write_bbreg(pAdapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC);
++ write_bbreg(pAdapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC);
++ write_bbreg(pAdapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC);
++
++ // HT Tx-rf(B)
++ tmpval = TxPower[RF_PATH_B];
++ TxAGC = (tmpval<<24) | (tmpval<<16) | (tmpval<<8) | tmpval;
++
++ write_bbreg(pAdapter, rTxAGC_B_Rate18_06, bMaskDWord, TxAGC);
++ write_bbreg(pAdapter, rTxAGC_B_Rate54_24, bMaskDWord, TxAGC);
++ write_bbreg(pAdapter, rTxAGC_B_Mcs03_Mcs00, bMaskDWord, TxAGC);
++ write_bbreg(pAdapter, rTxAGC_B_Mcs07_Mcs04, bMaskDWord, TxAGC);
++ write_bbreg(pAdapter, rTxAGC_B_Mcs11_Mcs08, bMaskDWord, TxAGC);
++ write_bbreg(pAdapter, rTxAGC_B_Mcs15_Mcs12, bMaskDWord, TxAGC);
++
++ RT_TRACE(_module_mp_, _drv_notice_,
++ ("-SetOFDMTxPower: A[0x%02x] B[0x%02x]\n",
++ TxPower[RF_PATH_A], TxPower[RF_PATH_B]));
++}
++
++void Hal_SetAntennaPathPower(PADAPTER pAdapter)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
++ u8 TxPowerLevel[MAX_RF_PATH_NUMS];
++ u8 rfPath;
++
++ TxPowerLevel[RF_PATH_A] = pAdapter->mppriv.txpoweridx;
++ TxPowerLevel[RF_PATH_B] = pAdapter->mppriv.txpoweridx_b;
++
++ switch (pAdapter->mppriv.antenna_tx)
++ {
++ case ANTENNA_A:
++ default:
++ rfPath = RF_PATH_A;
++ break;
++ case ANTENNA_B:
++ rfPath = RF_PATH_B;
++ break;
++ case ANTENNA_C:
++ rfPath = RF_PATH_C;
++ break;
++ }
++
++ switch (pHalData->rf_chip)
++ {
++ case RF_8225:
++ case RF_8256:
++ case RF_6052:
++ Hal_SetCCKTxPower(pAdapter, TxPowerLevel);
++ if (pAdapter->mppriv.rateidx < MPT_RATE_6M) // CCK rate
++ Hal_MPT_CCKTxPowerAdjustbyIndex(pAdapter, TxPowerLevel[rfPath]%2 == 0);
++ Hal_SetOFDMTxPower(pAdapter, TxPowerLevel);
++ break;
++
++ default:
++ break;
++ }
++}
++
++void Hal_SetTxPower(PADAPTER pAdapter)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
++ u8 TxPower = pAdapter->mppriv.txpoweridx;
++ u8 TxPowerLevel[MAX_RF_PATH_NUMS];
++ u8 rf, rfPath;
++
++ for (rf = 0; rf < MAX_RF_PATH_NUMS; rf++) {
++ TxPowerLevel[rf] = TxPower;
++ }
++
++ switch (pAdapter->mppriv.antenna_tx)
++ {
++ case ANTENNA_A:
++ default:
++ rfPath = RF_PATH_A;
++ break;
++ case ANTENNA_B:
++ rfPath = RF_PATH_B;
++ break;
++ case ANTENNA_C:
++ rfPath = RF_PATH_C;
++ break;
++ }
++
++ switch (pHalData->rf_chip)
++ {
++ // 2008/09/12 MH Test only !! We enable the TX power tracking for MP!!!!!
++ // We should call normal driver API later!!
++ case RF_8225:
++ case RF_8256:
++ case RF_6052:
++ Hal_SetCCKTxPower(pAdapter, TxPowerLevel);
++ if (pAdapter->mppriv.rateidx < MPT_RATE_6M) // CCK rate
++ Hal_MPT_CCKTxPowerAdjustbyIndex(pAdapter, TxPowerLevel[rfPath]%2 == 0);
++ Hal_SetOFDMTxPower(pAdapter, TxPowerLevel);
++ break;
++
++ default:
++ break;
++ }
++
++// SetCCKTxPower(pAdapter, TxPower);
++// SetOFDMTxPower(pAdapter, TxPower);
++}
++
++void Hal_SetTxAGCOffset(PADAPTER pAdapter, u32 ulTxAGCOffset)
++{
++ u32 TxAGCOffset_B, TxAGCOffset_C, TxAGCOffset_D,tmpAGC;
++
++ TxAGCOffset_B = (ulTxAGCOffset&0x000000ff);
++ TxAGCOffset_C = ((ulTxAGCOffset&0x0000ff00)>>8);
++ TxAGCOffset_D = ((ulTxAGCOffset&0x00ff0000)>>16);
++
++ tmpAGC = (TxAGCOffset_D<<8 | TxAGCOffset_C<<4 | TxAGCOffset_B);
++ write_bbreg(pAdapter, rFPGA0_TxGainStage,
++ (bXBTxAGC|bXCTxAGC|bXDTxAGC), tmpAGC);
++}
++
++void Hal_SetDataRate(PADAPTER pAdapter)
++{
++ Hal_mpt_SwitchRfSetting(pAdapter);
++}
++
++#if !defined (CONFIG_RTL8192C) && !defined (CONFIG_RTL8192D)
++/*------------------------------Define structure----------------------------*/
++typedef struct _R_ANTENNA_SELECT_OFDM {
++ u32 r_tx_antenna:4;
++ u32 r_ant_l:4;
++ u32 r_ant_non_ht:4;
++ u32 r_ant_ht1:4;
++ u32 r_ant_ht2:4;
++ u32 r_ant_ht_s1:4;
++ u32 r_ant_non_ht_s1:4;
++ u32 OFDM_TXSC:2;
++ u32 Reserved:2;
++}R_ANTENNA_SELECT_OFDM;
++
++typedef struct _R_ANTENNA_SELECT_CCK {
++ u8 r_cckrx_enable_2:2;
++ u8 r_cckrx_enable:2;
++ u8 r_ccktx_enable:4;
++}R_ANTENNA_SELECT_CCK;
++#endif
++
++void Hal_SetAntenna(PADAPTER pAdapter)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
++
++ R_ANTENNA_SELECT_OFDM *p_ofdm_tx; /* OFDM Tx register */
++ R_ANTENNA_SELECT_CCK *p_cck_txrx;
++
++ u8 r_rx_antenna_ofdm = 0, r_ant_select_cck_val = 0;
++ u8 chgTx = 0, chgRx = 0;
++ u32 r_ant_sel_cck_val = 0, r_ant_select_ofdm_val = 0, r_ofdm_tx_en_val = 0;
++
++
++ p_ofdm_tx = (R_ANTENNA_SELECT_OFDM *)&r_ant_select_ofdm_val;
++ p_cck_txrx = (R_ANTENNA_SELECT_CCK *)&r_ant_select_cck_val;
++
++ p_ofdm_tx->r_ant_ht1 = 0x1;
++ p_ofdm_tx->r_ant_ht2 = 0x2; // Second TX RF path is A
++ p_ofdm_tx->r_ant_non_ht = 0x3; // 0x1+0x2=0x3
++
++ switch (pAdapter->mppriv.antenna_tx)
++ {
++ case ANTENNA_A:
++ p_ofdm_tx->r_tx_antenna = 0x1;
++ r_ofdm_tx_en_val = 0x1;
++ p_ofdm_tx->r_ant_l = 0x1;
++ p_ofdm_tx->r_ant_ht_s1 = 0x1;
++ p_ofdm_tx->r_ant_non_ht_s1 = 0x1;
++ p_cck_txrx->r_ccktx_enable = 0x8;
++ chgTx = 1;
++
++ // From SD3 Willis suggestion !!! Set RF A=TX and B as standby
++// if (IS_HARDWARE_TYPE_8192S(pAdapter))
++ {
++ write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
++ write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 1);
++ r_ofdm_tx_en_val = 0x3;
++
++ // Power save
++ //cosa r_ant_select_ofdm_val = 0x11111111;
++
++ // We need to close RFB by SW control
++ if (pHalData->rf_type == RF_2T2R)
++ {
++ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);
++ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 1);
++ PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);
++ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1);
++ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 0);
++ }
++ }
++ break;
++
++ case ANTENNA_B:
++ p_ofdm_tx->r_tx_antenna = 0x2;
++ r_ofdm_tx_en_val = 0x2;
++ p_ofdm_tx->r_ant_l = 0x2;
++ p_ofdm_tx->r_ant_ht_s1 = 0x2;
++ p_ofdm_tx->r_ant_non_ht_s1 = 0x2;
++ p_cck_txrx->r_ccktx_enable = 0x4;
++ chgTx = 1;
++
++ // From SD3 Willis suggestion !!! Set RF A as standby
++ //if (IS_HARDWARE_TYPE_8192S(pAdapter))
++ {
++ PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 1);
++ PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
++// r_ofdm_tx_en_val = 0x3;
++
++ // Power save
++ //cosa r_ant_select_ofdm_val = 0x22222222;
++
++ // 2008/10/31 MH From SD3 Willi's suggestion. We must read RF 1T table.
++ // 2009/01/08 MH From Sd3 Willis. We need to close RFA by SW control
++ if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_1T2R)
++ {
++ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 1);
++ PHY_SetBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, BIT10, 0);
++ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0);
++// PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);
++ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 0);
++ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1);
++ }
++ }
++ break;
++
++ case ANTENNA_AB: // For 8192S
++ p_ofdm_tx->r_tx_antenna = 0x3;
++ r_ofdm_tx_en_val = 0x3;
++ p_ofdm_tx->r_ant_l = 0x3;
++ p_ofdm_tx->r_ant_ht_s1 = 0x3;
++ p_ofdm_tx->r_ant_non_ht_s1 = 0x3;
++ p_cck_txrx->r_ccktx_enable = 0xC;
++ chgTx = 1;
++
++ // From SD3 Willis suggestion !!! Set RF B as standby
++ //if (IS_HARDWARE_TYPE_8192S(pAdapter))
++ {
++ PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
++ PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
++
++ // Disable Power save
++ //cosa r_ant_select_ofdm_val = 0x3321333;
++#if 0
++ // 2008/10/31 MH From SD3 Willi's suggestion. We must read RFA 2T table.
++ if ((pHalData->VersionID == VERSION_8192S_ACUT)) // For RTL8192SU A-Cut only, by Roger, 2008.11.07.
++ {
++ mpt_RFConfigFromPreParaArrary(pAdapter, 1, RF_PATH_A);
++ }
++#endif
++ // 2009/01/08 MH From Sd3 Willis. We need to enable RFA/B by SW control
++ if (pHalData->rf_type == RF_2T2R)
++ {
++ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);
++ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0);
++// PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);
++ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1);
++ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1);
++ }
++ }
++ break;
++
++ default:
++ break;
++ }
++
++ //
++ // r_rx_antenna_ofdm, bit0=A, bit1=B, bit2=C, bit3=D
++ // r_cckrx_enable : CCK default, 0=A, 1=B, 2=C, 3=D
++ // r_cckrx_enable_2 : CCK option, 0=A, 1=B, 2=C, 3=D
++ //
++ switch (pAdapter->mppriv.antenna_rx)
++ {
++ case ANTENNA_A:
++ r_rx_antenna_ofdm = 0x1; // A
++ p_cck_txrx->r_cckrx_enable = 0x0; // default: A
++ p_cck_txrx->r_cckrx_enable_2 = 0x0; // option: A
++ chgRx = 1;
++ break;
++
++ case ANTENNA_B:
++ r_rx_antenna_ofdm = 0x2; // B
++ p_cck_txrx->r_cckrx_enable = 0x1; // default: B
++ p_cck_txrx->r_cckrx_enable_2 = 0x1; // option: B
++ chgRx = 1;
++ break;
++
++ case ANTENNA_AB:
++ r_rx_antenna_ofdm = 0x3; // AB
++ p_cck_txrx->r_cckrx_enable = 0x0; // default:A
++ p_cck_txrx->r_cckrx_enable_2 = 0x1; // option:B
++ chgRx = 1;
++ break;
++
++ default:
++ break;
++ }
++
++ if (chgTx && chgRx)
++ {
++ switch(pHalData->rf_chip)
++ {
++ case RF_8225:
++ case RF_8256:
++ case RF_6052:
++ //r_ant_sel_cck_val = r_ant_select_cck_val;
++ PHY_SetBBReg(pAdapter, rFPGA1_TxInfo, 0x7fffffff, r_ant_select_ofdm_val); //OFDM Tx
++ PHY_SetBBReg(pAdapter, rFPGA0_TxInfo, 0x0000000f, r_ofdm_tx_en_val); //OFDM Tx
++ PHY_SetBBReg(pAdapter, rOFDM0_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm); //OFDM Rx
++ PHY_SetBBReg(pAdapter, rOFDM1_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm); //OFDM Rx
++ PHY_SetBBReg(pAdapter, rCCK0_AFESetting, bMaskByte3, r_ant_select_cck_val);//r_ant_sel_cck_val); //CCK TxRx
++
++ break;
++
++ default:
++ break;
++ }
++ }
++
++ RT_TRACE(_module_mp_, _drv_notice_, ("-SwitchAntenna: finished\n"));
++}
++
++s32 Hal_SetThermalMeter(PADAPTER pAdapter, u8 target_ther)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
++
++
++ if (!netif_running(pAdapter->pnetdev)) {
++ RT_TRACE(_module_mp_, _drv_warning_, ("SetThermalMeter! Fail: interface not opened!\n"));
++ return _FAIL;
++ }
++
++ if (check_fwstate(&pAdapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {
++ RT_TRACE(_module_mp_, _drv_warning_, ("SetThermalMeter: Fail! not in MP mode!\n"));
++ return _FAIL;
++ }
++
++ target_ther &= 0xff;
++ if (target_ther < 0x07)
++ target_ther = 0x07;
++ else if (target_ther > 0x1d)
++ target_ther = 0x1d;
++
++ pHalData->EEPROMThermalMeter = target_ther;
++
++ return _SUCCESS;
++}
++
++void Hal_TriggerRFThermalMeter(PADAPTER pAdapter)
++{
++
++ write_rfreg(pAdapter, RF_PATH_A, RF_T_METER, 0x60); // 0x24: RF Reg[6:5]
++
++// RT_TRACE(_module_mp_,_drv_alert_, ("TriggerRFThermalMeter() finished.\n" ));
++}
++
++u8 Hal_ReadRFThermalMeter(PADAPTER pAdapter)
++{
++ u32 ThermalValue = 0;
++
++ ThermalValue = _read_rfreg(pAdapter, RF_PATH_A, RF_T_METER, 0x1F); // 0x24: RF Reg[4:0]
++// RT_TRACE(_module_mp_, _drv_alert_, ("ThermalValue = 0x%x\n", ThermalValue));
++ return (u8)ThermalValue;
++}
++
++void Hal_GetThermalMeter(PADAPTER pAdapter, u8 *value)
++{
++#if 0
++ fw_cmd(pAdapter, IOCMD_GET_THERMAL_METER);
++ rtw_msleep_os(1000);
++ fw_cmd_data(pAdapter, value, 1);
++ *value &= 0xFF;
++#else
++
++ Hal_TriggerRFThermalMeter(pAdapter);
++ rtw_msleep_os(1000);
++ *value = Hal_ReadRFThermalMeter(pAdapter);
++#endif
++}
++
++void Hal_SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
++ pAdapter->mppriv.MptCtx.bSingleCarrier = bStart;
++ if (bStart)// Start Single Carrier.
++ {
++ RT_TRACE(_module_mp_,_drv_alert_, ("SetSingleCarrierTx: test start\n"));
++ // 1. if OFDM block on?
++ if(!read_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
++ write_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);//set OFDM block on
++
++ {
++ // 2. set CCK test mode off, set to CCK normal mode
++ write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, bDisable);
++ // 3. turn on scramble setting
++ write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable);
++ }
++ // 4. Turn On Single Carrier Tx and turn off the other test modes.
++ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
++ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bEnable);
++ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
++#ifdef CONFIG_RTL8192C
++ // 5. Disable TX power saving at STF & LLTF
++ write_bbreg(pAdapter, rOFDM1_LSTF, BIT22, 1);
++#endif
++ }
++ else// Stop Single Carrier.
++ {
++ RT_TRACE(_module_mp_,_drv_alert_, ("SetSingleCarrierTx: test stop\n"));
++
++ // Turn off all test modes.
++ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
++ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
++ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
++#ifdef CONFIG_RTL8192C
++ // Cancel disable TX power saving at STF&LLTF
++ write_bbreg(pAdapter, rOFDM1_LSTF, BIT22, 0);
++#endif
++ //Delay 10 ms //delay_ms(10);
++ rtw_msleep_os(10);
++
++ //BB Reset
++ write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
++ write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
++ }
++}
++
++
++void Hal_SetSingleToneTx(PADAPTER pAdapter, u8 bStart)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
++ BOOLEAN is92C = IS_92C_SERIAL(pHalData->VersionID);
++
++ u8 rfPath;
++
++ switch (pAdapter->mppriv.antenna_tx)
++ {
++ case ANTENNA_A:
++ default:
++ rfPath = RF_PATH_A;
++ break;
++ case ANTENNA_B:
++ rfPath = RF_PATH_B;
++ break;
++ case ANTENNA_C:
++ rfPath = RF_PATH_C;
++ break;
++ }
++
++ pAdapter->mppriv.MptCtx.bSingleTone = bStart;
++ if (bStart)// Start Single Tone.
++ {
++ RT_TRACE(_module_mp_,_drv_alert_, ("SetSingleToneTx: test start\n"));
++ write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x0);
++ write_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x0);
++
++ if (is92C)
++ {
++ _write_rfreg(pAdapter, RF_PATH_A, 0x21, BIT19, 0x01);
++ rtw_usleep_os(100);
++ if (rfPath == RF_PATH_A)
++ write_rfreg(pAdapter, RF_PATH_B, 0x00, 0x10000); // PAD all on.
++ else if (rfPath == RF_PATH_B)
++ write_rfreg(pAdapter, RF_PATH_A, 0x00, 0x10000); // PAD all on.
++ } else {
++ write_rfreg(pAdapter, rfPath, 0x21, 0xd4000);
++ rtw_usleep_os(100);
++ }
++
++ write_rfreg(pAdapter, rfPath, 0x00, 0x2001f); // PAD all on.
++ rtw_usleep_os(100);
++ }
++ else// Stop Single Tone.
++ {
++ RT_TRACE(_module_mp_,_drv_alert_, ("SetSingleToneTx: test stop\n"));
++ write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x1);
++ write_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
++
++ if (is92C) {
++ _write_rfreg(pAdapter, RF_PATH_A, 0x21, BIT19, 0x00);
++ rtw_usleep_os(100);
++ write_rfreg(pAdapter, RF_PATH_A, 0x00, 0x32d75); // PAD all on.
++ write_rfreg(pAdapter, RF_PATH_B, 0x00, 0x32d75); // PAD all on.
++ rtw_usleep_os(100);
++ } else {
++ write_rfreg(pAdapter, rfPath, 0x21, 0x54000);
++ rtw_usleep_os(100);
++
++ write_rfreg(pAdapter, rfPath, 0x00, 0x30000); // PAD all on.
++ rtw_usleep_os(100);
++ }
++ }
++
++}
++
++
++void Hal_SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart)
++{
++ pAdapter->mppriv.MptCtx.bCarrierSuppression = bStart;
++ if (bStart) // Start Carrier Suppression.
++ {
++ RT_TRACE(_module_mp_,_drv_alert_, ("SetCarrierSuppressionTx: test start\n"));
++ //if(pMgntInfo->dot11CurrentWirelessMode == WIRELESS_MODE_B)
++ if (pAdapter->mppriv.rateidx <= MPT_RATE_11M)
++ {
++ // 1. if CCK block on?
++ if(!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn))
++ write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);//set CCK block on
++
++ //Turn Off All Test Mode
++ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
++ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
++ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
++
++ write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); //transmit mode
++ write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x0); //turn off scramble setting
++
++ //Set CCK Tx Test Rate
++ //PHY_SetBBReg(pAdapter, rCCK0_System, bCCKTxRate, pMgntInfo->ForcedDataRate);
++ write_bbreg(pAdapter, rCCK0_System, bCCKTxRate, 0x0); //Set FTxRate to 1Mbps
++ }
++ }
++ else// Stop Carrier Suppression.
++ {
++ RT_TRACE(_module_mp_,_drv_alert_, ("SetCarrierSuppressionTx: test stop\n"));
++ //if(pMgntInfo->dot11CurrentWirelessMode == WIRELESS_MODE_B)
++ if (pAdapter->mppriv.rateidx <= MPT_RATE_11M ) {
++ write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); //normal mode
++ write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x1); //turn on scramble setting
++
++ //BB Reset
++ write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
++ write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
++ }
++ }
++ //DbgPrint("\n MPT_ProSetCarrierSupp() is finished. \n");
++}
++
++void Hal_SetCCKContinuousTx(PADAPTER pAdapter, u8 bStart)
++{
++ u32 cckrate;
++
++ if (bStart)
++ {
++ RT_TRACE(_module_mp_, _drv_alert_,
++ ("SetCCKContinuousTx: test start\n"));
++
++ // 1. if CCK block on?
++ if(!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn))
++ write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);//set CCK block on
++
++ //Turn Off All Test Mode
++ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
++ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
++ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
++ //Set CCK Tx Test Rate
++ #if 0
++ switch(pAdapter->mppriv.rateidx)
++ {
++ case 2:
++ cckrate = 0;
++ break;
++ case 4:
++ cckrate = 1;
++ break;
++ case 11:
++ cckrate = 2;
++ break;
++ case 22:
++ cckrate = 3;
++ break;
++ default:
++ cckrate = 0;
++ break;
++ }
++ #else
++ cckrate = pAdapter->mppriv.rateidx;
++ #endif
++ write_bbreg(pAdapter, rCCK0_System, bCCKTxRate, cckrate);
++ write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); //transmit mode
++ write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable); //turn on scramble setting
++
++#ifdef CONFIG_RTL8192C
++ // Patch for CCK 11M waveform
++ if (cckrate == MPT_RATE_1M)
++ write_bbreg(pAdapter, 0xA71, BIT(6), bDisable);
++ else
++ write_bbreg(pAdapter, 0xA71, BIT(6), bEnable);
++#endif
++
++ }
++ else {
++ RT_TRACE(_module_mp_, _drv_info_,
++ ("SetCCKContinuousTx: test stop\n"));
++
++ write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); //normal mode
++ write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable); //turn on scramble setting
++
++ //BB Reset
++ write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
++ write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
++ }
++
++ pAdapter->mppriv.MptCtx.bCckContTx = bStart;
++ pAdapter->mppriv.MptCtx.bOfdmContTx = _FALSE;
++}/* mpt_StartCckContTx */
++
++void Hal_SetOFDMContinuousTx(PADAPTER pAdapter, u8 bStart)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
++
++ if (bStart) {
++ RT_TRACE(_module_mp_, _drv_info_, ("SetOFDMContinuousTx: test start\n"));
++ // 1. if OFDM block on?
++ if(!read_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
++ write_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);//set OFDM block on
++ {
++
++ // 2. set CCK test mode off, set to CCK normal mode
++ write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, bDisable);
++
++ // 3. turn on scramble setting
++ write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable);
++ }
++ // 4. Turn On Continue Tx and turn off the other test modes.
++ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bEnable);
++ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
++ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
++ } else {
++ RT_TRACE(_module_mp_,_drv_info_, ("SetOFDMContinuousTx: test stop\n"));
++ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
++ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
++ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
++ //Delay 10 ms
++ rtw_msleep_os(10);
++ //BB Reset
++ write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
++ write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
++ }
++
++ pAdapter->mppriv.MptCtx.bCckContTx = _FALSE;
++ pAdapter->mppriv.MptCtx.bOfdmContTx = bStart;
++}/* mpt_StartOfdmContTx */
++
++void Hal_SetContinuousTx(PADAPTER pAdapter, u8 bStart)
++{
++#if 0
++ // ADC turn off [bit24-21] adc port0 ~ port1
++ if (bStart) {
++ write_bbreg(pAdapter, rRx_Wait_CCCA, read_bbreg(pAdapter, rRx_Wait_CCCA) & 0xFE1FFFFF);
++ rtw_usleep_os(100);
++ }
++#endif
++ RT_TRACE(_module_mp_, _drv_info_,
++ ("SetContinuousTx: rate:%d\n", pAdapter->mppriv.rateidx));
++
++ pAdapter->mppriv.MptCtx.bStartContTx = bStart;
++ if (pAdapter->mppriv.rateidx <= MPT_RATE_11M)
++ {
++ Hal_SetCCKContinuousTx(pAdapter, bStart);
++ }
++ else if ((pAdapter->mppriv.rateidx >= MPT_RATE_6M) &&
++ (pAdapter->mppriv.rateidx <= MPT_RATE_MCS15))
++ {
++ Hal_SetOFDMContinuousTx(pAdapter, bStart);
++ }
++#if 0
++ // ADC turn on [bit24-21] adc port0 ~ port1
++ if (!bStart) {
++ write_bbreg(pAdapter, rRx_Wait_CCCA, read_bbreg(pAdapter, rRx_Wait_CCCA) | 0x01E00000);
++ }
++#endif
++}
++
++#endif // CONFIG_MP_INCLUDE
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/hal/rtl8192c/rtl8192c_phycfg.c linux-xbian-rpi/drivers/net/wireless/rtl8192cu/hal/rtl8192c/rtl8192c_phycfg.c
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/hal/rtl8192c/rtl8192c_phycfg.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/hal/rtl8192c/rtl8192c_phycfg.c 2015-07-28 01:20:58.309639981 +0200
+@@ -0,0 +1,4840 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++/******************************************************************************
++
++ Module: rtl8192c_phycfg.c
++
++ Note: Merge 92SE/SU PHY config as below
++ 1. BB register R/W API
++ 2. RF register R/W API
++ 3. Initial BB/RF/MAC config by reading BB/MAC/RF txt.
++ 3. Power setting API
++ 4. Channel switch API
++ 5. Initial gain switch API.
++ 6. Other BB/MAC/RF API.
++
++ Function: PHY: Extern function, phy: local function
++
++ Export: PHY_FunctionName
++
++ Abbrev: NONE
++
++ History:
++ Data Who Remark
++ 08/08/2008 MHC 1. Port from 9x series phycfg.c
++ 2. Reorganize code arch and ad description.
++ 3. Collect similar function.
++ 4. Seperate extern/local API.
++ 08/12/2008 MHC We must merge or move USB PHY relative function later.
++ 10/07/2008 MHC Add IQ calibration for PHY.(Only 1T2R mode now!!!)
++ 11/06/2008 MHC Add TX Power index PG file to config in 0xExx register
++ area to map with EEPROM/EFUSE tx pwr index.
++
++******************************************************************************/
++#define _HAL_8192C_PHYCFG_C_
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++#include <rtw_byteorder.h>
++
++#ifdef CONFIG_IOL
++#include <rtw_iol.h>
++#endif
++
++#include <rtl8192c_hal.h>
++
++
++/*---------------------------Define Local Constant---------------------------*/
++/* Channel switch:The size of command tables for switch channel*/
++#define MAX_PRECMD_CNT 16
++#define MAX_RFDEPENDCMD_CNT 16
++#define MAX_POSTCMD_CNT 16
++
++#define MAX_DOZE_WAITING_TIMES_9x 64
++
++/*---------------------------Define Local Constant---------------------------*/
++
++
++/*------------------------Define global variable-----------------------------*/
++
++/*------------------------Define local variable------------------------------*/
++
++
++/*--------------------Define export function prototype-----------------------*/
++// Please refer to header file
++/*--------------------Define export function prototype-----------------------*/
++
++/*----------------------------Function Body----------------------------------*/
++//
++// 1. BB register R/W API
++//
++
++/**
++* Function: phy_CalculateBitShift
++*
++* OverView: Get shifted position of the BitMask
++*
++* Input:
++* u4Byte BitMask,
++*
++* Output: none
++* Return: u4Byte Return the shift bit bit position of the mask
++*/
++static u32
++phy_CalculateBitShift(
++ u32 BitMask
++ )
++{
++ u32 i;
++
++ for(i=0; i<=31; i++)
++ {
++ if ( ((BitMask>>i) & 0x1 ) == 1)
++ break;
++ }
++
++ return (i);
++}
++
++
++/**
++* Function: PHY_QueryBBReg
++*
++* OverView: Read "sepcific bits" from BB register
++*
++* Input:
++* PADAPTER Adapter,
++* u4Byte RegAddr, //The target address to be readback
++* u4Byte BitMask //The target bit position in the target address
++* //to be readback
++* Output: None
++* Return: u4Byte Data //The readback register value
++* Note: This function is equal to "GetRegSetting" in PHY programming guide
++*/
++u32
++rtl8192c_PHY_QueryBBReg(
++ IN PADAPTER Adapter,
++ IN u32 RegAddr,
++ IN u32 BitMask
++ )
++{
++ u32 ReturnValue = 0, OriginalValue, BitShift;
++ u16 BBWaitCounter = 0;
++
++#if (DISABLE_BB_RF == 1)
++ return 0;
++#endif
++
++ //RT_TRACE(COMP_RF, DBG_TRACE, ("--->PHY_QueryBBReg(): RegAddr(%#lx), BitMask(%#lx)\n", RegAddr, BitMask));
++
++ OriginalValue = rtw_read32(Adapter, RegAddr);
++ BitShift = phy_CalculateBitShift(BitMask);
++ ReturnValue = (OriginalValue & BitMask) >> BitShift;
++
++ //RTPRINT(FPHY, PHY_BBR, ("BBR MASK=0x%lx Addr[0x%lx]=0x%lx\n", BitMask, RegAddr, OriginalValue));
++ //RT_TRACE(COMP_RF, DBG_TRACE, ("<---PHY_QueryBBReg(): RegAddr(%#lx), BitMask(%#lx), OriginalValue(%#lx)\n", RegAddr, BitMask, OriginalValue));
++
++ return (ReturnValue);
++
++}
++
++
++/**
++* Function: PHY_SetBBReg
++*
++* OverView: Write "Specific bits" to BB register (page 8~)
++*
++* Input:
++* PADAPTER Adapter,
++* u4Byte RegAddr, //The target address to be modified
++* u4Byte BitMask //The target bit position in the target address
++* //to be modified
++* u4Byte Data //The new register value in the target bit position
++* //of the target address
++*
++* Output: None
++* Return: None
++* Note: This function is equal to "PutRegSetting" in PHY programming guide
++*/
++
++VOID
++rtl8192c_PHY_SetBBReg(
++ IN PADAPTER Adapter,
++ IN u32 RegAddr,
++ IN u32 BitMask,
++ IN u32 Data
++ )
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ //u16 BBWaitCounter = 0;
++ u32 OriginalValue, BitShift;
++
++#if (DISABLE_BB_RF == 1)
++ return;
++#endif
++
++ //RT_TRACE(COMP_RF, DBG_TRACE, ("--->PHY_SetBBReg(): RegAddr(%#lx), BitMask(%#lx), Data(%#lx)\n", RegAddr, BitMask, Data));
++
++ if(BitMask!= bMaskDWord){//if not "double word" write
++ OriginalValue = rtw_read32(Adapter, RegAddr);
++ BitShift = phy_CalculateBitShift(BitMask);
++ Data = ((OriginalValue & (~BitMask)) | ((Data << BitShift) & BitMask));
++ }
++
++ rtw_write32(Adapter, RegAddr, Data);
++
++ //RTPRINT(FPHY, PHY_BBW, ("BBW MASK=0x%lx Addr[0x%lx]=0x%lx\n", BitMask, RegAddr, Data));
++ //RT_TRACE(COMP_RF, DBG_TRACE, ("<---PHY_SetBBReg(): RegAddr(%#lx), BitMask(%#lx), Data(%#lx)\n", RegAddr, BitMask, Data));
++
++}
++
++
++//
++// 2. RF register R/W API
++//
++
++/*-----------------------------------------------------------------------------
++ * Function: phy_FwRFSerialRead()
++ *
++ * Overview: We support firmware to execute RF-R/W.
++ *
++ * Input: NONE
++ *
++ * Output: NONE
++ *
++ * Return: NONE
++ *
++ * Revised History:
++ * When Who Remark
++ * 01/21/2008 MHC Create Version 0.
++ *
++ *---------------------------------------------------------------------------*/
++static u32
++phy_FwRFSerialRead(
++ IN PADAPTER Adapter,
++ IN RF_RADIO_PATH_E eRFPath,
++ IN u32 Offset )
++{
++ u32 retValue = 0;
++ //RT_ASSERT(FALSE,("deprecate!\n"));
++ return (retValue);
++
++} /* phy_FwRFSerialRead */
++
++
++/*-----------------------------------------------------------------------------
++ * Function: phy_FwRFSerialWrite()
++ *
++ * Overview: We support firmware to execute RF-R/W.
++ *
++ * Input: NONE
++ *
++ * Output: NONE
++ *
++ * Return: NONE
++ *
++ * Revised History:
++ * When Who Remark
++ * 01/21/2008 MHC Create Version 0.
++ *
++ *---------------------------------------------------------------------------*/
++static VOID
++phy_FwRFSerialWrite(
++ IN PADAPTER Adapter,
++ IN RF_RADIO_PATH_E eRFPath,
++ IN u32 Offset,
++ IN u32 Data )
++{
++ //RT_ASSERT(FALSE,("deprecate!\n"));
++}
++
++
++/**
++* Function: phy_RFSerialRead
++*
++* OverView: Read regster from RF chips
++*
++* Input:
++* PADAPTER Adapter,
++* RF_RADIO_PATH_E eRFPath, //Radio path of A/B/C/D
++* u4Byte Offset, //The target address to be read
++*
++* Output: None
++* Return: u4Byte reback value
++* Note: Threre are three types of serial operations:
++* 1. Software serial write
++* 2. Hardware LSSI-Low Speed Serial Interface
++* 3. Hardware HSSI-High speed
++* serial write. Driver need to implement (1) and (2).
++* This function is equal to the combination of RF_ReadReg() and RFLSSIRead()
++*/
++static u32
++phy_RFSerialRead(
++ IN PADAPTER Adapter,
++ IN RF_RADIO_PATH_E eRFPath,
++ IN u32 Offset
++ )
++{
++ u32 retValue = 0;
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ BB_REGISTER_DEFINITION_T *pPhyReg = &pHalData->PHYRegDef[eRFPath];
++ u32 NewOffset;
++ u32 tmplong,tmplong2;
++ u8 RfPiEnable=0;
++#if 0
++ if(pHalData->RFChipID == RF_8225 && Offset > 0x24) //36 valid regs
++ return retValue;
++ if(pHalData->RFChipID == RF_8256 && Offset > 0x2D) //45 valid regs
++ return retValue;
++#endif
++ //
++ // Make sure RF register offset is correct
++ //
++ Offset &= 0x3f;
++
++ //
++ // Switch page for 8256 RF IC
++ //
++ NewOffset = Offset;
++
++ // 2009/06/17 MH We can not execute IO for power save or other accident mode.
++ //if(RT_CANNOT_IO(Adapter))
++ //{
++ // RTPRINT(FPHY, PHY_RFR, ("phy_RFSerialRead return all one\n"));
++ // return 0xFFFFFFFF;
++ //}
++
++ // For 92S LSSI Read RFLSSIRead
++ // For RF A/B write 0x824/82c(does not work in the future)
++ // We must use 0x824 for RF A and B to execute read trigger
++ tmplong = PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2, bMaskDWord);
++ if(eRFPath == RF_PATH_A)
++ tmplong2 = tmplong;
++ else
++ tmplong2 = PHY_QueryBBReg(Adapter, pPhyReg->rfHSSIPara2, bMaskDWord);
++
++ tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset<<23) | bLSSIReadEdge; //T65 RF
++
++ PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2, bMaskDWord, tmplong&(~bLSSIReadEdge));
++ rtw_udelay_os(10);// PlatformStallExecution(10);
++
++ PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, bMaskDWord, tmplong2);
++ rtw_udelay_os(100);//PlatformStallExecution(100);
++
++ PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2, bMaskDWord, tmplong|bLSSIReadEdge);
++ rtw_udelay_os(10);//PlatformStallExecution(10);
++
++ if(eRFPath == RF_PATH_A)
++ RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter1, BIT8);
++ else if(eRFPath == RF_PATH_B)
++ RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XB_HSSIParameter1, BIT8);
++
++ if(RfPiEnable)
++ { // Read from BBreg8b8, 12 bits for 8190, 20bits for T65 RF
++ retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBackPi, bLSSIReadBackData);
++ //DBG_8192C("Readback from RF-PI : 0x%x\n", retValue);
++ }
++ else
++ { //Read from BBreg8a0, 12 bits for 8190, 20 bits for T65 RF
++ retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBack, bLSSIReadBackData);
++ //DBG_8192C("Readback from RF-SI : 0x%x\n", retValue);
++ }
++ //DBG_8192C("RFR-%d Addr[0x%x]=0x%x\n", eRFPath, pPhyReg->rfLSSIReadBack, retValue);
++
++ return retValue;
++
++}
++
++
++
++/**
++* Function: phy_RFSerialWrite
++*
++* OverView: Write data to RF register (page 8~)
++*
++* Input:
++* PADAPTER Adapter,
++* RF_RADIO_PATH_E eRFPath, //Radio path of A/B/C/D
++* u4Byte Offset, //The target address to be read
++* u4Byte Data //The new register Data in the target bit position
++* //of the target to be read
++*
++* Output: None
++* Return: None
++* Note: Threre are three types of serial operations:
++* 1. Software serial write
++* 2. Hardware LSSI-Low Speed Serial Interface
++* 3. Hardware HSSI-High speed
++* serial write. Driver need to implement (1) and (2).
++* This function is equal to the combination of RF_ReadReg() and RFLSSIRead()
++ *
++ * Note: For RF8256 only
++ * The total count of RTL8256(Zebra4) register is around 36 bit it only employs
++ * 4-bit RF address. RTL8256 uses "register mode control bit" (Reg00[12], Reg00[10])
++ * to access register address bigger than 0xf. See "Appendix-4 in PHY Configuration
++ * programming guide" for more details.
++ * Thus, we define a sub-finction for RTL8526 register address conversion
++ * ===========================================================
++ * Register Mode RegCTL[1] RegCTL[0] Note
++ * (Reg00[12]) (Reg00[10])
++ * ===========================================================
++ * Reg_Mode0 0 x Reg 0 ~15(0x0 ~ 0xf)
++ * ------------------------------------------------------------------
++ * Reg_Mode1 1 0 Reg 16 ~30(0x1 ~ 0xf)
++ * ------------------------------------------------------------------
++ * Reg_Mode2 1 1 Reg 31 ~ 45(0x1 ~ 0xf)
++ * ------------------------------------------------------------------
++ *
++ * 2008/09/02 MH Add 92S RF definition
++ *
++ *
++ *
++*/
++static VOID
++phy_RFSerialWrite(
++ IN PADAPTER Adapter,
++ IN RF_RADIO_PATH_E eRFPath,
++ IN u32 Offset,
++ IN u32 Data
++ )
++{
++ u32 DataAndAddr = 0;
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ BB_REGISTER_DEFINITION_T *pPhyReg = &pHalData->PHYRegDef[eRFPath];
++ u32 NewOffset;
++
++#if 0
++ //<Roger_TODO> We should check valid regs for RF_6052 case.
++ if(pHalData->RFChipID == RF_8225 && Offset > 0x24) //36 valid regs
++ return;
++ if(pHalData->RFChipID == RF_8256 && Offset > 0x2D) //45 valid regs
++ return;
++#endif
++
++ // 2009/06/17 MH We can not execute IO for power save or other accident mode.
++ //if(RT_CANNOT_IO(Adapter))
++ //{
++ // RTPRINT(FPHY, PHY_RFW, ("phy_RFSerialWrite stop\n"));
++ // return;
++ //}
++
++ Offset &= 0x3f;
++
++ //
++ // Shadow Update
++ //
++ //PHY_RFShadowWrite(Adapter, eRFPath, Offset, Data);
++
++ //
++ // Switch page for 8256 RF IC
++ //
++ NewOffset = Offset;
++
++ //
++ // Put write addr in [5:0] and write data in [31:16]
++ //
++ //DataAndAddr = (Data<<16) | (NewOffset&0x3f);
++ DataAndAddr = ((NewOffset<<20) | (Data&0x000fffff)) & 0x0fffffff; // T65 RF
++
++ //
++ // Write Operation
++ //
++ PHY_SetBBReg(Adapter, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
++ //RTPRINT(FPHY, PHY_RFW, ("RFW-%d Addr[0x%lx]=0x%lx\n", eRFPath, pPhyReg->rf3wireOffset, DataAndAddr));
++
++}
++
++
++/**
++* Function: PHY_QueryRFReg
++*
++* OverView: Query "Specific bits" to RF register (page 8~)
++*
++* Input:
++* PADAPTER Adapter,
++* RF_RADIO_PATH_E eRFPath, //Radio path of A/B/C/D
++* u4Byte RegAddr, //The target address to be read
++* u4Byte BitMask //The target bit position in the target address
++* //to be read
++*
++* Output: None
++* Return: u4Byte Readback value
++* Note: This function is equal to "GetRFRegSetting" in PHY programming guide
++*/
++u32
++rtl8192c_PHY_QueryRFReg(
++ IN PADAPTER Adapter,
++ IN RF_RADIO_PATH_E eRFPath,
++ IN u32 RegAddr,
++ IN u32 BitMask
++ )
++{
++ u32 Original_Value, Readback_Value, BitShift;
++ //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ //u8 RFWaitCounter = 0;
++ //_irqL irqL;
++
++#if (DISABLE_BB_RF == 1)
++ return 0;
++#endif
++
++ //RT_TRACE(COMP_RF, DBG_TRACE, ("--->PHY_QueryRFReg(): RegAddr(%#lx), eRFPath(%#x), BitMask(%#lx)\n", RegAddr, eRFPath,BitMask));
++
++#ifdef CONFIG_USB_HCI
++ //PlatformAcquireMutex(&pHalData->mxRFOperate);
++#else
++ //_enter_critical(&pHalData->rf_lock, &irqL);
++#endif
++
++
++ Original_Value = phy_RFSerialRead(Adapter, eRFPath, RegAddr);
++
++ BitShift = phy_CalculateBitShift(BitMask);
++ Readback_Value = (Original_Value & BitMask) >> BitShift;
++
++#ifdef CONFIG_USB_HCI
++ //PlatformReleaseMutex(&pHalData->mxRFOperate);
++#else
++ //_exit_critical(&pHalData->rf_lock, &irqL);
++#endif
++
++
++ //RTPRINT(FPHY, PHY_RFR, ("RFR-%d MASK=0x%lx Addr[0x%lx]=0x%lx\n", eRFPath, BitMask, RegAddr, Original_Value));//BitMask(%#lx),BitMask,
++ //RT_TRACE(COMP_RF, DBG_TRACE, ("<---PHY_QueryRFReg(): RegAddr(%#lx), eRFPath(%#x), Original_Value(%#lx)\n",
++ // RegAddr, eRFPath, Original_Value));
++
++ return (Readback_Value);
++}
++
++/**
++* Function: PHY_SetRFReg
++*
++* OverView: Write "Specific bits" to RF register (page 8~)
++*
++* Input:
++* PADAPTER Adapter,
++* RF_RADIO_PATH_E eRFPath, //Radio path of A/B/C/D
++* u4Byte RegAddr, //The target address to be modified
++* u4Byte BitMask //The target bit position in the target address
++* //to be modified
++* u4Byte Data //The new register Data in the target bit position
++* //of the target address
++*
++* Output: None
++* Return: None
++* Note: This function is equal to "PutRFRegSetting" in PHY programming guide
++*/
++VOID
++rtl8192c_PHY_SetRFReg(
++ IN PADAPTER Adapter,
++ IN RF_RADIO_PATH_E eRFPath,
++ IN u32 RegAddr,
++ IN u32 BitMask,
++ IN u32 Data
++ )
++{
++
++ //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ //u1Byte RFWaitCounter = 0;
++ u32 Original_Value, BitShift;
++ //_irqL irqL;
++
++#if (DISABLE_BB_RF == 1)
++ return;
++#endif
++
++ //RT_TRACE(COMP_RF, DBG_TRACE, ("--->PHY_SetRFReg(): RegAddr(%#lx), BitMask(%#lx), Data(%#lx), eRFPath(%#x)\n",
++ // RegAddr, BitMask, Data, eRFPath));
++ //RTPRINT(FINIT, INIT_RF, ("PHY_SetRFReg(): RegAddr(%#lx), BitMask(%#lx), Data(%#lx), eRFPath(%#x)\n",
++ // RegAddr, BitMask, Data, eRFPath));
++
++
++#ifdef CONFIG_USB_HCI
++ //PlatformAcquireMutex(&pHalData->mxRFOperate);
++#else
++ //_enter_critical(&pHalData->rf_lock, &irqL);
++#endif
++
++
++ // RF data is 12 bits only
++ if (BitMask != bRFRegOffsetMask)
++ {
++ Original_Value = phy_RFSerialRead(Adapter, eRFPath, RegAddr);
++ BitShift = phy_CalculateBitShift(BitMask);
++ Data = ((Original_Value & (~BitMask)) | (Data<< BitShift));
++ }
++
++ phy_RFSerialWrite(Adapter, eRFPath, RegAddr, Data);
++
++
++
++#ifdef CONFIG_USB_HCI
++ //PlatformReleaseMutex(&pHalData->mxRFOperate);
++#else
++ //_exit_critical(&pHalData->rf_lock, &irqL);
++#endif
++
++ //PHY_QueryRFReg(Adapter,eRFPath,RegAddr,BitMask);
++ //RT_TRACE(COMP_RF, DBG_TRACE, ("<---PHY_SetRFReg(): RegAddr(%#lx), BitMask(%#lx), Data(%#lx), eRFPath(%#x)\n",
++ // RegAddr, BitMask, Data, eRFPath));
++
++}
++
++
++//
++// 3. Initial MAC/BB/RF config by reading MAC/BB/RF txt.
++//
++
++/*-----------------------------------------------------------------------------
++ * Function: phy_ConfigMACWithParaFile()
++ *
++ * Overview: This function read BB parameters from general file format, and do register
++ * Read/Write
++ *
++ * Input: PADAPTER Adapter
++ * ps1Byte pFileName
++ *
++ * Output: NONE
++ *
++ * Return: RT_STATUS_SUCCESS: configuration file exist
++ *
++ * Note: The format of MACPHY_REG.txt is different from PHY and RF.
++ * [Register][Mask][Value]
++ *---------------------------------------------------------------------------*/
++static int
++phy_ConfigMACWithParaFile(
++ IN PADAPTER Adapter,
++ IN u8* pFileName
++)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++
++ int rtStatus = _SUCCESS;
++
++ return rtStatus;
++}
++
++/*-----------------------------------------------------------------------------
++ * Function: phy_ConfigMACWithHeaderFile()
++ *
++ * Overview: This function read BB parameters from Header file we gen, and do register
++ * Read/Write
++ *
++ * Input: PADAPTER Adapter
++ * ps1Byte pFileName
++ *
++ * Output: NONE
++ *
++ * Return: RT_STATUS_SUCCESS: configuration file exist
++ *
++ * Note: The format of MACPHY_REG.txt is different from PHY and RF.
++ * [Register][Mask][Value]
++ *---------------------------------------------------------------------------*/
++static int
++phy_ConfigMACWithHeaderFile(
++ IN PADAPTER Adapter
++)
++{
++ u32 i = 0;
++ u32 ArrayLength = 0;
++ u32* ptrArray;
++ //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++
++ //2008.11.06 Modified by tynli.
++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("Read Rtl819XMACPHY_Array\n"));
++ ArrayLength = MAC_2T_ArrayLength;
++ ptrArray = Rtl819XMAC_Array;
++
++#ifdef CONFIG_IOL_MAC
++ if(rtw_IOL_applied(Adapter))
++ {
++ struct xmit_frame *xmit_frame;
++ if((xmit_frame=rtw_IOL_accquire_xmit_frame(Adapter)) == NULL)
++ return _FAIL;
++
++ for(i = 0 ;i < ArrayLength;i=i+2){ // Add by tynli for 2 column
++ rtw_IOL_append_WB_cmd(xmit_frame, ptrArray[i], (u8)ptrArray[i+1]);
++ }
++
++ return rtw_IOL_exec_cmds_sync(Adapter, xmit_frame, 1000);
++ }
++ else
++#endif
++ {
++ for(i = 0 ;i < ArrayLength;i=i+2){ // Add by tynli for 2 column
++ rtw_write8(Adapter, ptrArray[i], (u8)ptrArray[i+1]);
++ }
++ }
++
++ return _SUCCESS;
++
++}
++
++
++/*-----------------------------------------------------------------------------
++ * Function: PHY_MACConfig8192C
++ *
++ * Overview: Condig MAC by header file or parameter file.
++ *
++ * Input: NONE
++ *
++ * Output: NONE
++ *
++ * Return: NONE
++ *
++ * Revised History:
++ * When Who Remark
++ * 08/12/2008 MHC Create Version 0.
++ *
++ *---------------------------------------------------------------------------*/
++int
++PHY_MACConfig8192C(
++ IN PADAPTER Adapter
++ )
++{
++ int rtStatus = _SUCCESS;
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ s8 *pszMACRegFile;
++ s8 sz88CMACRegFile[] = RTL8188C_PHY_MACREG;
++ s8 sz92CMACRegFile[] = RTL8192C_PHY_MACREG;
++ BOOLEAN is92C = IS_92C_SERIAL(pHalData->VersionID);
++
++ if(is92C)
++ pszMACRegFile = sz92CMACRegFile;
++ else
++ pszMACRegFile = sz88CMACRegFile;
++
++ //
++ // Config MAC
++ //
++#ifdef CONFIG_EMBEDDED_FWIMG
++ rtStatus = phy_ConfigMACWithHeaderFile(Adapter);
++#else
++
++ // Not make sure EEPROM, add later
++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("Read MACREG.txt\n"));
++ rtStatus = phy_ConfigMACWithParaFile(Adapter, pszMACRegFile);
++#endif
++
++#ifdef CONFIG_PCI_HCI
++ //this switching setting cause some 8192cu hw have redownload fw fail issue
++ //improve 2-stream TX EVM by Jenyu
++ if(is92C)
++ rtw_write8(Adapter, REG_SPS0_CTRL+3,0x71);
++#endif
++
++
++ // 2010.07.13 AMPDU aggregation number 9
++ //rtw_write16(Adapter, REG_MAX_AGGR_NUM, MAX_AGGR_NUM);
++ rtw_write8(Adapter, REG_MAX_AGGR_NUM, 0x0A); //By tynli. 2010.11.18.
++#ifdef CONFIG_USB_HCI
++ if(is92C && (BOARD_USB_DONGLE == pHalData->BoardType))
++ rtw_write8(Adapter, 0x40,0x04);
++#endif
++
++ return rtStatus;
++
++}
++
++
++/**
++* Function: phy_InitBBRFRegisterDefinition
++*
++* OverView: Initialize Register definition offset for Radio Path A/B/C/D
++*
++* Input:
++* PADAPTER Adapter,
++*
++* Output: None
++* Return: None
++* Note: The initialization value is constant and it should never be changes
++*/
++static VOID
++phy_InitBBRFRegisterDefinition(
++ IN PADAPTER Adapter
++)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++
++ // RF Interface Sowrtware Control
++ pHalData->PHYRegDef[RF_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 LSBs if read 32-bit from 0x870
++ pHalData->PHYRegDef[RF_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872)
++ pHalData->PHYRegDef[RF_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 LSBs if read 32-bit from 0x874
++ pHalData->PHYRegDef[RF_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876)
++
++ // RF Interface Readback Value
++ pHalData->PHYRegDef[RF_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; // 16 LSBs if read 32-bit from 0x8E0
++ pHalData->PHYRegDef[RF_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2)
++ pHalData->PHYRegDef[RF_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 LSBs if read 32-bit from 0x8E4
++ pHalData->PHYRegDef[RF_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6)
++
++ // RF Interface Output (and Enable)
++ pHalData->PHYRegDef[RF_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x860
++ pHalData->PHYRegDef[RF_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x864
++
++ // RF Interface (Output and) Enable
++ pHalData->PHYRegDef[RF_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862)
++ pHalData->PHYRegDef[RF_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866)
++
++ //Addr of LSSI. Wirte RF register by driver
++ pHalData->PHYRegDef[RF_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; //LSSI Parameter
++ pHalData->PHYRegDef[RF_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
++
++ // RF parameter
++ pHalData->PHYRegDef[RF_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter; //BB Band Select
++ pHalData->PHYRegDef[RF_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter;
++ pHalData->PHYRegDef[RF_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter;
++ pHalData->PHYRegDef[RF_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter;
++
++ // Tx AGC Gain Stage (same for all path. Should we remove this?)
++ pHalData->PHYRegDef[RF_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
++ pHalData->PHYRegDef[RF_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
++ pHalData->PHYRegDef[RF_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
++ pHalData->PHYRegDef[RF_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
++
++ // Tranceiver A~D HSSI Parameter-1
++ pHalData->PHYRegDef[RF_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; //wire control parameter1
++ pHalData->PHYRegDef[RF_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1; //wire control parameter1
++
++ // Tranceiver A~D HSSI Parameter-2
++ pHalData->PHYRegDef[RF_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; //wire control parameter2
++ pHalData->PHYRegDef[RF_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; //wire control parameter2
++
++ // RF switch Control
++ pHalData->PHYRegDef[RF_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl; //TR/Ant switch control
++ pHalData->PHYRegDef[RF_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl;
++ pHalData->PHYRegDef[RF_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl;
++ pHalData->PHYRegDef[RF_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl;
++
++ // AGC control 1
++ pHalData->PHYRegDef[RF_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1;
++ pHalData->PHYRegDef[RF_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;
++ pHalData->PHYRegDef[RF_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1;
++ pHalData->PHYRegDef[RF_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1;
++
++ // AGC control 2
++ pHalData->PHYRegDef[RF_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2;
++ pHalData->PHYRegDef[RF_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2;
++ pHalData->PHYRegDef[RF_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2;
++ pHalData->PHYRegDef[RF_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2;
++
++ // RX AFE control 1
++ pHalData->PHYRegDef[RF_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance;
++ pHalData->PHYRegDef[RF_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
++ pHalData->PHYRegDef[RF_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance;
++ pHalData->PHYRegDef[RF_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance;
++
++ // RX AFE control 1
++ pHalData->PHYRegDef[RF_PATH_A].rfRxAFE = rOFDM0_XARxAFE;
++ pHalData->PHYRegDef[RF_PATH_B].rfRxAFE = rOFDM0_XBRxAFE;
++ pHalData->PHYRegDef[RF_PATH_C].rfRxAFE = rOFDM0_XCRxAFE;
++ pHalData->PHYRegDef[RF_PATH_D].rfRxAFE = rOFDM0_XDRxAFE;
++
++ // Tx AFE control 1
++ pHalData->PHYRegDef[RF_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance;
++ pHalData->PHYRegDef[RF_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
++ pHalData->PHYRegDef[RF_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance;
++ pHalData->PHYRegDef[RF_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance;
++
++ // Tx AFE control 2
++ pHalData->PHYRegDef[RF_PATH_A].rfTxAFE = rOFDM0_XATxAFE;
++ pHalData->PHYRegDef[RF_PATH_B].rfTxAFE = rOFDM0_XBTxAFE;
++ pHalData->PHYRegDef[RF_PATH_C].rfTxAFE = rOFDM0_XCTxAFE;
++ pHalData->PHYRegDef[RF_PATH_D].rfTxAFE = rOFDM0_XDTxAFE;
++
++ // Tranceiver LSSI Readback SI mode
++ pHalData->PHYRegDef[RF_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
++ pHalData->PHYRegDef[RF_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
++ pHalData->PHYRegDef[RF_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;
++ pHalData->PHYRegDef[RF_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
++
++ // Tranceiver LSSI Readback PI mode
++ pHalData->PHYRegDef[RF_PATH_A].rfLSSIReadBackPi = TransceiverA_HSPI_Readback;
++ pHalData->PHYRegDef[RF_PATH_B].rfLSSIReadBackPi = TransceiverB_HSPI_Readback;
++ //pHalData->PHYRegDef[RF_PATH_C].rfLSSIReadBackPi = rFPGA0_XC_LSSIReadBack;
++ //pHalData->PHYRegDef[RF_PATH_D].rfLSSIReadBackPi = rFPGA0_XD_LSSIReadBack;
++
++}
++
++
++/*-----------------------------------------------------------------------------
++ * Function: phy_ConfigBBWithParaFile()
++ *
++ * Overview: This function read BB parameters from general file format, and do register
++ * Read/Write
++ *
++ * Input: PADAPTER Adapter
++ * ps1Byte pFileName
++ *
++ * Output: NONE
++ *
++ * Return: RT_STATUS_SUCCESS: configuration file exist
++ * 2008/11/06 MH For 92S we do not support silent reset now. Disable
++ * parameter file compare!!!!!!??
++ *
++ *---------------------------------------------------------------------------*/
++static int
++phy_ConfigBBWithParaFile(
++ IN PADAPTER Adapter,
++ IN u8* pFileName
++)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++
++ int rtStatus = _SUCCESS;
++
++ return rtStatus;
++}
++
++
++
++//****************************************
++// The following is for High Power PA
++//****************************************
++VOID
++phy_ConfigBBExternalPA(
++ IN PADAPTER Adapter
++)
++{
++#ifdef CONFIG_USB_HCI
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ u16 i=0;
++ u32 temp=0;
++
++ if(!pHalData->ExternalPA)
++ {
++ return;
++ }
++
++ // 2010/10/19 MH According to Jenyu/EEChou 's opinion, we need not to execute the
++ // same code as SU. It is already updated in PHY_REG_1T_HP.txt.
++#if 0
++ PHY_SetBBReg(Adapter, 0xee8, BIT28, 1);
++ temp = PHY_QueryBBReg(Adapter, 0x860, bMaskDWord);
++ temp |= (BIT26|BIT21|BIT10|BIT5);
++ PHY_SetBBReg(Adapter, 0x860, bMaskDWord, temp);
++ PHY_SetBBReg(Adapter, 0x870, BIT10, 0);
++ PHY_SetBBReg(Adapter, 0xc80, bMaskDWord, 0x20000080);
++ PHY_SetBBReg(Adapter, 0xc88, bMaskDWord, 0x40000100);
++#endif
++
++#endif
++}
++
++/*-----------------------------------------------------------------------------
++ * Function: phy_ConfigBBWithHeaderFile()
++ *
++ * Overview: This function read BB parameters from general file format, and do register
++ * Read/Write
++ *
++ * Input: PADAPTER Adapter
++ * u1Byte ConfigType 0 => PHY_CONFIG
++ * 1 =>AGC_TAB
++ *
++ * Output: NONE
++ *
++ * Return: RT_STATUS_SUCCESS: configuration file exist
++ *
++ *---------------------------------------------------------------------------*/
++static int
++phy_ConfigBBWithHeaderFile(
++ IN PADAPTER Adapter,
++ IN u8 ConfigType
++)
++{
++ int i;
++ u32* Rtl819XPHY_REGArray_Table;
++ u32* Rtl819XAGCTAB_Array_Table;
++ u16 PHY_REGArrayLen, AGCTAB_ArrayLen;
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ int ret = _SUCCESS;
++
++ //
++ // 2009.11.24. Modified by tynli.
++ //
++ if(IS_92C_SERIAL(pHalData->VersionID))
++ {
++ AGCTAB_ArrayLen = AGCTAB_2TArrayLength;
++ Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_2TArray;
++ PHY_REGArrayLen = PHY_REG_2TArrayLength;
++ Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_2TArray;
++#ifdef CONFIG_USB_HCI
++ if(pHalData->BoardType == BOARD_MINICARD )
++ {
++ PHY_REGArrayLen = PHY_REG_2T_mCardArrayLength;
++ Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_2T_mCardArray;
++ }
++#endif
++ }
++ else
++ {
++ AGCTAB_ArrayLen = AGCTAB_1TArrayLength;
++ Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_1TArray;
++ PHY_REGArrayLen = PHY_REG_1TArrayLength;
++ Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1TArray;
++#ifdef CONFIG_USB_HCI
++ if(pHalData->BoardType == BOARD_MINICARD )
++ {
++ PHY_REGArrayLen = PHY_REG_1T_mCardArrayLength;
++ Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T_mCardArray;
++ }
++ else if(pHalData->BoardType == BOARD_USB_High_PA)
++ {
++ AGCTAB_ArrayLen = AGCTAB_1T_HPArrayLength;
++ Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_1T_HPArray;
++ PHY_REGArrayLen = PHY_REG_1T_HPArrayLength;
++ Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T_HPArray;
++ }
++#endif
++ }
++
++ if(ConfigType == BaseBand_Config_PHY_REG)
++ {
++ #ifdef CONFIG_IOL_BB_PHY_REG
++ if(rtw_IOL_applied(Adapter))
++ {
++ struct xmit_frame *xmit_frame;
++ u32 tmp_value;
++
++ if((xmit_frame=rtw_IOL_accquire_xmit_frame(Adapter)) == NULL) {
++ ret = _FAIL;
++ goto exit;
++ }
++
++ for(i=0;i<PHY_REGArrayLen;i=i+2)
++ {
++ tmp_value=Rtl819XPHY_REGArray_Table[i+1];
++
++ if (Rtl819XPHY_REGArray_Table[i] == 0xfe)
++ rtw_IOL_append_DELAY_MS_cmd(xmit_frame, 50);
++ else if (Rtl819XPHY_REGArray_Table[i] == 0xfd)
++ rtw_IOL_append_DELAY_MS_cmd(xmit_frame, 5);
++ else if (Rtl819XPHY_REGArray_Table[i] == 0xfc)
++ rtw_IOL_append_DELAY_MS_cmd(xmit_frame, 1);
++ else if (Rtl819XPHY_REGArray_Table[i] == 0xfb)
++ rtw_IOL_append_DELAY_US_cmd(xmit_frame, 50);
++ else if (Rtl819XPHY_REGArray_Table[i] == 0xfa)
++ rtw_IOL_append_DELAY_US_cmd(xmit_frame, 5);
++ else if (Rtl819XPHY_REGArray_Table[i] == 0xf9)
++ rtw_IOL_append_DELAY_US_cmd(xmit_frame, 1);
++
++ rtw_IOL_append_WD_cmd(xmit_frame, Rtl819XPHY_REGArray_Table[i], tmp_value);
++ //RT_TRACE(COMP_INIT, DBG_TRACE, ("The Rtl819XPHY_REGArray_Table[0] is %lx Rtl819XPHY_REGArray[1] is %lx \n",Rtl819XPHY_REGArray_Table[i], Rtl819XPHY_REGArray_Table[i+1]));
++ }
++
++ ret = rtw_IOL_exec_cmds_sync(Adapter, xmit_frame, 1000);
++ }
++ else
++ #endif
++ {
++ for(i=0;i<PHY_REGArrayLen;i=i+2)
++ {
++ if (Rtl819XPHY_REGArray_Table[i] == 0xfe){
++ #ifdef CONFIG_LONG_DELAY_ISSUE
++ rtw_msleep_os(50);
++ #else
++ rtw_mdelay_os(50);
++ #endif
++ }
++ else if (Rtl819XPHY_REGArray_Table[i] == 0xfd)
++ rtw_mdelay_os(5);
++ else if (Rtl819XPHY_REGArray_Table[i] == 0xfc)
++ rtw_mdelay_os(1);
++ else if (Rtl819XPHY_REGArray_Table[i] == 0xfb)
++ rtw_udelay_os(50);
++ else if (Rtl819XPHY_REGArray_Table[i] == 0xfa)
++ rtw_udelay_os(5);
++ else if (Rtl819XPHY_REGArray_Table[i] == 0xf9)
++ rtw_udelay_os(1);
++
++ PHY_SetBBReg(Adapter, Rtl819XPHY_REGArray_Table[i], bMaskDWord, Rtl819XPHY_REGArray_Table[i+1]);
++
++ // Add 1us delay between BB/RF register setting.
++ rtw_udelay_os(1);
++
++ //RT_TRACE(COMP_INIT, DBG_TRACE, ("The Rtl819XPHY_REGArray_Table[0] is %lx Rtl819XPHY_REGArray[1] is %lx \n",Rtl819XPHY_REGArray_Table[i], Rtl819XPHY_REGArray_Table[i+1]));
++ }
++ }
++
++ // for External PA
++ phy_ConfigBBExternalPA(Adapter);
++ }
++ else if(ConfigType == BaseBand_Config_AGC_TAB)
++ {
++ #ifdef CONFIG_IOL_BB_AGC_TAB
++ if(rtw_IOL_applied(Adapter))
++ {
++ struct xmit_frame *xmit_frame;
++
++ if((xmit_frame=rtw_IOL_accquire_xmit_frame(Adapter)) == NULL) {
++ ret = _FAIL;
++ goto exit;
++ }
++
++ for(i=0;i<AGCTAB_ArrayLen;i=i+2)
++ {
++ rtw_IOL_append_WD_cmd(xmit_frame, Rtl819XAGCTAB_Array_Table[i], Rtl819XAGCTAB_Array_Table[i+1]);
++ //RT_TRACE(COMP_INIT, DBG_TRACE, ("The Rtl819XAGCTAB_Array_Table[0] is %lx Rtl819XPHY_REGArray[1] is %lx \n",Rtl819XAGCTAB_Array_Table[i], Rtl819XAGCTAB_Array_Table[i+1]));
++ }
++
++ ret = rtw_IOL_exec_cmds_sync(Adapter, xmit_frame, 1000);
++ }
++ else
++ #endif
++ {
++ for(i=0;i<AGCTAB_ArrayLen;i=i+2)
++ {
++ PHY_SetBBReg(Adapter, Rtl819XAGCTAB_Array_Table[i], bMaskDWord, Rtl819XAGCTAB_Array_Table[i+1]);
++
++ // Add 1us delay between BB/RF register setting.
++ rtw_udelay_os(1);
++
++ //RT_TRACE(COMP_INIT, DBG_TRACE, ("The Rtl819XAGCTAB_Array_Table[0] is %lx Rtl819XPHY_REGArray[1] is %lx \n",Rtl819XAGCTAB_Array_Table[i], Rtl819XAGCTAB_Array_Table[i+1]));
++ }
++ }
++ }
++
++exit:
++ return ret;
++
++}
++
++
++VOID
++storePwrIndexDiffRateOffset(
++ IN PADAPTER Adapter,
++ IN u32 RegAddr,
++ IN u32 BitMask,
++ IN u32 Data
++ )
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++
++ if(RegAddr == rTxAGC_A_Rate18_06)
++ {
++ pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][0] = Data;
++ //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][0] = 0x%lx\n", pHalData->pwrGroupCnt,
++ // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][0]));
++ }
++ if(RegAddr == rTxAGC_A_Rate54_24)
++ {
++ pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][1] = Data;
++ //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][1] = 0x%lx\n", pHalData->pwrGroupCnt,
++ // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][1]));
++ }
++ if(RegAddr == rTxAGC_A_CCK1_Mcs32)
++ {
++ pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][6] = Data;
++ //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][6] = 0x%lx\n", pHalData->pwrGroupCnt,
++ // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][6]));
++ }
++ if(RegAddr == rTxAGC_B_CCK11_A_CCK2_11 && BitMask == 0xffffff00)
++ {
++ pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][7] = Data;
++ //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][7] = 0x%lx\n", pHalData->pwrGroupCnt,
++ // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][7]));
++ }
++ if(RegAddr == rTxAGC_A_Mcs03_Mcs00)
++ {
++ pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][2] = Data;
++ //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][2] = 0x%lx\n", pHalData->pwrGroupCnt,
++ // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][2]));
++ }
++ if(RegAddr == rTxAGC_A_Mcs07_Mcs04)
++ {
++ pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][3] = Data;
++ //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][3] = 0x%lx\n", pHalData->pwrGroupCnt,
++ // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][3]));
++ }
++ if(RegAddr == rTxAGC_A_Mcs11_Mcs08)
++ {
++ pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][4] = Data;
++ //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][4] = 0x%lx\n", pHalData->pwrGroupCnt,
++ // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][4]));
++ }
++ if(RegAddr == rTxAGC_A_Mcs15_Mcs12)
++ {
++ pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][5] = Data;
++ //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][5] = 0x%lx\n", pHalData->pwrGroupCnt,
++ // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][5]));
++ }
++ if(RegAddr == rTxAGC_B_Rate18_06)
++ {
++ pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][8] = Data;
++ //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][8] = 0x%lx\n", pHalData->pwrGroupCnt,
++ // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][8]));
++ }
++ if(RegAddr == rTxAGC_B_Rate54_24)
++ {
++ pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][9] = Data;
++ //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][9] = 0x%lx\n", pHalData->pwrGroupCnt,
++ // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][9]));
++ }
++ if(RegAddr == rTxAGC_B_CCK1_55_Mcs32)
++ {
++ pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][14] = Data;
++ //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][14] = 0x%lx\n", pHalData->pwrGroupCnt,
++ // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][14]));
++ }
++ if(RegAddr == rTxAGC_B_CCK11_A_CCK2_11 && BitMask == 0x000000ff)
++ {
++ pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][15] = Data;
++ //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][15] = 0x%lx\n", pHalData->pwrGroupCnt,
++ // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][15]));
++ }
++ if(RegAddr == rTxAGC_B_Mcs03_Mcs00)
++ {
++ pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][10] = Data;
++ //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][10] = 0x%lx\n", pHalData->pwrGroupCnt,
++ // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][10]));
++ }
++ if(RegAddr == rTxAGC_B_Mcs07_Mcs04)
++ {
++ pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][11] = Data;
++ //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][11] = 0x%lx\n", pHalData->pwrGroupCnt,
++ // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][11]));
++ }
++ if(RegAddr == rTxAGC_B_Mcs11_Mcs08)
++ {
++ pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][12] = Data;
++ //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][12] = 0x%lx\n", pHalData->pwrGroupCnt,
++ // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][12]));
++ }
++ if(RegAddr == rTxAGC_B_Mcs15_Mcs12)
++ {
++ pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][13] = Data;
++ //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][13] = 0x%lx\n", pHalData->pwrGroupCnt,
++ // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][13]));
++ pHalData->pwrGroupCnt++;
++ }
++}
++/*-----------------------------------------------------------------------------
++ * Function: phy_ConfigBBWithPgParaFile
++ *
++ * Overview:
++ *
++ * Input: NONE
++ *
++ * Output: NONE
++ *
++ * Return: NONE
++ *
++ * Revised History:
++ * When Who Remark
++ * 11/06/2008 MHC Create Version 0.
++ * 2009/07/29 tynli (porting from 92SE branch)2009/03/11 Add copy parameter file to buffer for silent reset
++ *---------------------------------------------------------------------------*/
++static int
++phy_ConfigBBWithPgParaFile(
++ IN PADAPTER Adapter,
++ IN u8* pFileName)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++
++ int rtStatus = _SUCCESS;
++
++
++ return rtStatus;
++
++} /* phy_ConfigBBWithPgParaFile */
++
++
++/*-----------------------------------------------------------------------------
++ * Function: phy_ConfigBBWithPgHeaderFile
++ *
++ * Overview: Config PHY_REG_PG array
++ *
++ * Input: NONE
++ *
++ * Output: NONE
++ *
++ * Return: NONE
++ *
++ * Revised History:
++ * When Who Remark
++ * 11/06/2008 MHC Add later!!!!!!.. Please modify for new files!!!!
++ * 11/10/2008 tynli Modify to mew files.
++ *---------------------------------------------------------------------------*/
++static int
++phy_ConfigBBWithPgHeaderFile(
++ IN PADAPTER Adapter,
++ IN u8 ConfigType)
++{
++ int i;
++ u32* Rtl819XPHY_REGArray_Table_PG;
++ u16 PHY_REGArrayPGLen;
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++
++ // Default: pHalData->RF_Type = RF_2T2R.
++ PHY_REGArrayPGLen = PHY_REG_Array_PGLength;
++ Rtl819XPHY_REGArray_Table_PG = Rtl819XPHY_REG_Array_PG;
++
++#ifdef CONFIG_USB_HCI
++// 2010/10/19 Chiyoko According to Alex/Willson opinion, VAU/dongle can share the same PHY_REG_PG.txt
++/*
++ if(pHalData->BoardType == BOARD_MINICARD )
++ {
++ PHY_REGArrayPGLen = PHY_REG_Array_PG_mCardLength;
++ Rtl819XPHY_REGArray_Table_PG = Rtl819XPHY_REG_Array_PG_mCard;
++ }
++ else */if(pHalData->BoardType ==BOARD_USB_High_PA )
++ {
++ PHY_REGArrayPGLen = PHY_REG_Array_PG_HPLength;
++ Rtl819XPHY_REGArray_Table_PG = Rtl819XPHY_REG_Array_PG_HP;
++ }
++#endif
++
++ if(ConfigType == BaseBand_Config_PHY_REG)
++ {
++ for(i=0;i<PHY_REGArrayPGLen;i=i+3)
++ {
++ #if 0 //without IO, no delay is neeeded...
++ if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfe){
++ #ifdef CONFIG_LONG_DELAY_ISSUE
++ rtw_msleep_os(50);
++ #else
++ rtw_mdelay_os(50);
++ #endif
++ }
++ else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfd)
++ rtw_mdelay_os(5);
++ else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfc)
++ rtw_mdelay_os(1);
++ else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfb)
++ rtw_udelay_os(50);
++ else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfa)
++ rtw_udelay_os(5);
++ else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xf9)
++ rtw_udelay_os(1);
++ //PHY_SetBBReg(Adapter, Rtl819XPHY_REGArray_Table_PG[i], Rtl819XPHY_REGArray_Table_PG[i+1], Rtl819XPHY_REGArray_Table_PG[i+2]);
++ #endif
++
++ storePwrIndexDiffRateOffset(Adapter, Rtl819XPHY_REGArray_Table_PG[i],
++ Rtl819XPHY_REGArray_Table_PG[i+1],
++ Rtl819XPHY_REGArray_Table_PG[i+2]);
++ //RT_TRACE(COMP_SEND, DBG_TRACE, ("The Rtl819XPHY_REGArray_Table_PG[0] is %lx Rtl819XPHY_REGArray_Table_PG[1] is %lx \n",Rtl819XPHY_REGArray_Table_PG[i], Rtl819XPHY_REGArray_Table_PG[i+1]));
++ }
++ }
++ else
++ {
++
++ //RT_TRACE(COMP_SEND, DBG_LOUD, ("phy_ConfigBBWithPgHeaderFile(): ConfigType != BaseBand_Config_PHY_REG\n"));
++ }
++
++ return _SUCCESS;
++
++} /* phy_ConfigBBWithPgHeaderFile */
++
++#if (MP_DRIVER == 1)
++
++/*-----------------------------------------------------------------------------
++ * Function: phy_ConfigBBWithMpParaFile()
++ *
++ * Overview: This function read BB parameters from general file format, and do register
++ * Read/Write
++ *
++ * Input: PADAPTER Adapter
++ * ps1Byte pFileName
++ *
++ * Output: NONE
++ *
++ * Return: RT_STATUS_SUCCESS: configuration file exist
++ * 2008/11/06 MH For 92S we do not support silent reset now. Disable
++ * parameter file compare!!!!!!??
++ *
++ *---------------------------------------------------------------------------*/
++static int
++phy_ConfigBBWithMpParaFile(
++ IN PADAPTER Adapter,
++ IN u8* pFileName
++)
++{
++#if 1
++ int rtStatus = _SUCCESS;
++#else
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ s4Byte nLinesRead, ithLine;
++ RT_STATUS rtStatus = RT_STATUS_SUCCESS;
++ ps1Byte szLine;
++ u4Byte u4bRegOffset, u4bRegMask, u4bRegValue;
++ u4Byte u4bMove;
++
++ if(ADAPTER_TEST_STATUS_FLAG(Adapter, ADAPTER_STATUS_FIRST_INIT))
++ {
++ rtStatus = PlatformReadFile(
++ Adapter,
++ pFileName,
++ (pu1Byte)(pHalData->BufOfLines),
++ MAX_LINES_HWCONFIG_TXT,
++ MAX_BYTES_LINE_HWCONFIG_TXT,
++ &nLinesRead
++ );
++ if(rtStatus == RT_STATUS_SUCCESS)
++ {
++ PlatformMoveMemory(pHalData->BufOfLines6, pHalData->BufOfLines, nLinesRead*MAX_BYTES_LINE_HWCONFIG_TXT);
++ pHalData->nLinesRead6 = nLinesRead;
++ }
++ else
++ {
++ // Temporarily skip PHY_REG_MP.txt if file does not exist.
++ pHalData->nLinesRead6 = 0;
++ RT_TRACE(COMP_INIT, DBG_LOUD, ("No matched file \r\n"));
++ return RT_STATUS_SUCCESS;
++ }
++ }
++ else
++ {
++ PlatformMoveMemory(pHalData->BufOfLines, pHalData->BufOfLines6, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT);
++ nLinesRead = pHalData->nLinesRead6;
++ rtStatus = RT_STATUS_SUCCESS;
++ }
++
++
++ if(rtStatus == RT_STATUS_SUCCESS)
++ {
++ RT_TRACE(COMP_INIT, DBG_LOUD, ("phy_ConfigBBWithMpParaFile(): read %s ok\n", pFileName));
++
++ for(ithLine = 0; ithLine < nLinesRead; ithLine++)
++ {
++ szLine = pHalData->BufOfLines[ithLine];
++
++ if(!IsCommentString(szLine))
++ {
++ // Get 1st hex value as register offset.
++ if(GetHexValueFromString(szLine, &u4bRegOffset, &u4bMove))
++ {
++ if(u4bRegOffset == 0xff)
++ { // Ending.
++ break;
++ }
++ else if (u4bRegOffset == 0xfe)
++ delay_ms(50);
++ else if (u4bRegOffset == 0xfd)
++ delay_ms(5);
++ else if (u4bRegOffset == 0xfc)
++ delay_ms(1);
++ else if (u4bRegOffset == 0xfb)
++ PlatformStallExecution(50);
++ else if (u4bRegOffset == 0xfa)
++ PlatformStallExecution(5);
++ else if (u4bRegOffset == 0xf9)
++ PlatformStallExecution(1);
++
++ // Get 2nd hex value as register value.
++ szLine += u4bMove;
++ if(GetHexValueFromString(szLine, &u4bRegValue, &u4bMove))
++ {
++ RT_TRACE(COMP_FPGA, DBG_TRACE, ("[ADDR]%03lX=%08lX\n", u4bRegOffset, u4bRegValue));
++ PHY_SetBBReg(Adapter, u4bRegOffset, bMaskDWord, u4bRegValue);
++
++ // Add 1us delay between BB/RF register setting.
++ PlatformStallExecution(1);
++ }
++ }
++ }
++ }
++ }
++ else
++ {
++ RT_TRACE(COMP_INIT, DBG_LOUD, ("phy_ConfigBBWithMpParaFile(): Failed%s\n", pFileName));
++ }
++#endif
++
++ return rtStatus;
++}
++
++/*-----------------------------------------------------------------------------
++ * Function: phy_ConfigBBWithMpHeaderFile
++ *
++ * Overview: Config PHY_REG_MP array
++ *
++ * Input: NONE
++ *
++ * Output: NONE
++ *
++ * Return: NONE
++ *
++ * Revised History:
++ * When Who Remark
++ * 02/04/2010 chiyokolin Modify to new files.
++ *---------------------------------------------------------------------------*/
++static int
++phy_ConfigBBWithMpHeaderFile(
++ IN PADAPTER Adapter,
++ IN u1Byte ConfigType)
++{
++ int i;
++ u32* Rtl8192CPHY_REGArray_Table_MP;
++ u16 PHY_REGArrayMPLen;
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++
++ PHY_REGArrayMPLen = PHY_REG_Array_MPLength;
++ Rtl8192CPHY_REGArray_Table_MP = Rtl819XPHY_REG_Array_MP;
++
++ if(ConfigType == BaseBand_Config_PHY_REG)
++ {
++ for(i=0;i<PHY_REGArrayMPLen;i=i+2)
++ {
++ if (Rtl8192CPHY_REGArray_Table_MP[i] == 0xfe) {
++ #ifdef CONFIG_LONG_DELAY_ISSUE
++ rtw_msleep_os(50);
++ #else
++ rtw_mdelay_os(50);
++ #endif
++ }
++ else if (Rtl8192CPHY_REGArray_Table_MP[i] == 0xfd)
++ rtw_mdelay_os(5);
++ else if (Rtl8192CPHY_REGArray_Table_MP[i] == 0xfc)
++ rtw_mdelay_os(1);
++ else if (Rtl8192CPHY_REGArray_Table_MP[i] == 0xfb) {
++ #ifdef CONFIG_LONG_DELAY_ISSUE
++ rtw_msleep_os(50);
++ #else
++ rtw_mdelay_os(50);
++ #endif
++ }
++ else if (Rtl8192CPHY_REGArray_Table_MP[i] == 0xfa)
++ rtw_mdelay_os(5);
++ else if (Rtl8192CPHY_REGArray_Table_MP[i] == 0xf9)
++ rtw_mdelay_os(1);
++ PHY_SetBBReg(Adapter, Rtl8192CPHY_REGArray_Table_MP[i], bMaskDWord, Rtl8192CPHY_REGArray_Table_MP[i+1]);
++
++ // Add 1us delay between BB/RF register setting.
++ rtw_mdelay_os(1);
++
++// RT_TRACE(COMP_INIT, DBG_TRACE, ("The Rtl8192CPHY_REGArray_Table_MP[%d] is %lx Rtl8192CPHY_REGArray_Table_MP[%d] is %lx \n", i, i+1, Rtl8192CPHY_REGArray_Table_MP[i], Rtl8192CPHY_REGArray_Table_MP[i+1]));
++ }
++ }
++ else
++ {
++// RT_TRACE(COMP_SEND, DBG_LOUD, ("phy_ConfigBBWithMpHeaderFile(): ConfigType != BaseBand_Config_PHY_REG\n"));
++ }
++
++ return _SUCCESS;
++} /* phy_ConfigBBWithMpHeaderFile */
++
++#endif // #if (MP_DRIVER == 1)
++
++static VOID
++phy_BB8192C_Config_1T(
++ IN PADAPTER Adapter
++ )
++{
++#if 0
++ //for path - A
++ PHY_SetBBReg(Adapter, rFPGA0_TxInfo, 0x3, 0x1);
++ PHY_SetBBReg(Adapter, rFPGA1_TxInfo, 0x0303, 0x0101);
++ PHY_SetBBReg(Adapter, 0xe74, 0x0c000000, 0x1);
++ PHY_SetBBReg(Adapter, 0xe78, 0x0c000000, 0x1);
++ PHY_SetBBReg(Adapter, 0xe7c, 0x0c000000, 0x1);
++ PHY_SetBBReg(Adapter, 0xe80, 0x0c000000, 0x1);
++ PHY_SetBBReg(Adapter, 0xe88, 0x0c000000, 0x1);
++#endif
++ //for path - B
++ PHY_SetBBReg(Adapter, rFPGA0_TxInfo, 0x3, 0x2);
++ PHY_SetBBReg(Adapter, rFPGA1_TxInfo, 0x300033, 0x200022);
++
++ // 20100519 Joseph: Add for 1T2R config. Suggested by Kevin, Jenyu and Yunan.
++ PHY_SetBBReg(Adapter, rCCK0_AFESetting, bMaskByte3, 0x45);
++ PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, bMaskByte0, 0x23);
++ PHY_SetBBReg(Adapter, rOFDM0_AGCParameter1, 0x30, 0x1); // B path first AGC
++
++ PHY_SetBBReg(Adapter, 0xe74, 0x0c000000, 0x2);
++ PHY_SetBBReg(Adapter, 0xe78, 0x0c000000, 0x2);
++ PHY_SetBBReg(Adapter, 0xe7c, 0x0c000000, 0x2);
++ PHY_SetBBReg(Adapter, 0xe80, 0x0c000000, 0x2);
++ PHY_SetBBReg(Adapter, 0xe88, 0x0c000000, 0x2);
++
++
++}
++
++// Joseph test: new initialize order!!
++// Test only!! This part need to be re-organized.
++// Now it is just for 8256.
++static int
++phy_BB8190_Config_HardCode(
++ IN PADAPTER Adapter
++ )
++{
++ //RT_ASSERT(FALSE, ("This function is not implement yet!! \n"));
++ return _SUCCESS;
++}
++
++static int
++phy_BB8192C_Config_ParaFile(
++ IN PADAPTER Adapter
++ )
++{
++ EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(Adapter);
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ int rtStatus = _SUCCESS;
++
++ u8 szBBRegPgFile[] = RTL819X_PHY_REG_PG;
++
++ u8 sz88CBBRegFile[] = RTL8188C_PHY_REG;
++ u8 sz88CAGCTableFile[] = RTL8188C_AGC_TAB;
++
++ u8 sz92CBBRegFile[] = RTL8192C_PHY_REG;
++ u8 sz92CAGCTableFile[] = RTL8192C_AGC_TAB;
++
++ u8 *pszBBRegFile, *pszAGCTableFile, *pszBBRegMpFile;
++
++ //RT_TRACE(COMP_INIT, DBG_TRACE, ("==>phy_BB8192S_Config_ParaFile\n"));
++
++ if(IS_92C_SERIAL(pHalData->VersionID)){
++ pszBBRegFile=(u8*)&sz92CBBRegFile ;
++ pszAGCTableFile =(u8*)&sz92CAGCTableFile;
++ }
++ else{
++ pszBBRegFile=(u8*)&sz88CBBRegFile ;
++ pszAGCTableFile =(u8*)&sz88CAGCTableFile;
++ }
++
++ //
++ // 1. Read PHY_REG.TXT BB INIT!!
++ // We will seperate as 88C / 92C according to chip version
++ //
++#ifdef CONFIG_EMBEDDED_FWIMG
++ rtStatus = phy_ConfigBBWithHeaderFile(Adapter, BaseBand_Config_PHY_REG);
++#else
++ // No matter what kind of CHIP we always read PHY_REG.txt. We must copy different
++ // type of parameter files to phy_reg.txt at first.
++ rtStatus = phy_ConfigBBWithParaFile(Adapter,pszBBRegFile);
++#endif
++
++ if(rtStatus != _SUCCESS){
++ //RT_TRACE(COMP_INIT, DBG_SERIOUS, ("phy_BB8192S_Config_ParaFile():Write BB Reg Fail!!"));
++ goto phy_BB8190_Config_ParaFile_Fail;
++ }
++
++#if MP_DRIVER == 1
++ //
++ // 1.1 Read PHY_REG_MP.TXT BB INIT!!
++ // We will seperate as 88C / 92C according to chip version
++ //
++#ifdef CONFIG_EMBEDDED_FWIMG
++ rtStatus = phy_ConfigBBWithMpHeaderFile(Adapter, BaseBand_Config_PHY_REG);
++#else
++ // No matter what kind of CHIP we always read PHY_REG.txt. We must copy different
++ // type of parameter files to phy_reg.txt at first.
++ rtStatus = phy_ConfigBBWithMpParaFile(Adapter, pszBBRegMpFile);
++#endif
++
++ if(rtStatus != _SUCCESS){
++// RT_TRACE(COMP_INIT, DBG_SERIOUS, ("phy_BB8192S_Config_ParaFile():Write BB Reg MP Fail!!"));
++ goto phy_BB8190_Config_ParaFile_Fail;
++ }
++#endif // #if (MP_DRIVER == 1)
++
++ //
++ // 20100318 Joseph: Config 2T2R to 1T2R if necessary.
++ //
++ if(pHalData->rf_type == RF_1T2R)
++ {
++ phy_BB8192C_Config_1T(Adapter);
++ DBG_8192C("phy_BB8192C_Config_ParaFile():Config to 1T!!\n");
++ }
++
++ //
++ // 2. If EEPROM or EFUSE autoload OK, We must config by PHY_REG_PG.txt
++ //
++ if (pEEPROM->bautoload_fail_flag == _FALSE)
++ {
++ pHalData->pwrGroupCnt = 0;
++
++#ifdef CONFIG_EMBEDDED_FWIMG
++ rtStatus = phy_ConfigBBWithPgHeaderFile(Adapter, BaseBand_Config_PHY_REG);
++#else
++ rtStatus = phy_ConfigBBWithPgParaFile(Adapter, (u8*)&szBBRegPgFile);
++#endif
++ }
++
++ if(rtStatus != _SUCCESS){
++ //RT_TRACE(COMP_INIT, DBG_SERIOUS, ("phy_BB8192S_Config_ParaFile():BB_PG Reg Fail!!"));
++ goto phy_BB8190_Config_ParaFile_Fail;
++ }
++
++ //
++ // 3. BB AGC table Initialization
++ //
++#ifdef CONFIG_EMBEDDED_FWIMG
++ rtStatus = phy_ConfigBBWithHeaderFile(Adapter, BaseBand_Config_AGC_TAB);
++#else
++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("phy_BB8192S_Config_ParaFile AGC_TAB.txt\n"));
++ rtStatus = phy_ConfigBBWithParaFile(Adapter, pszAGCTableFile);
++#endif
++
++ if(rtStatus != _SUCCESS){
++ //RT_TRACE(COMP_FPGA, DBG_SERIOUS, ("phy_BB8192S_Config_ParaFile():AGC Table Fail\n"));
++ goto phy_BB8190_Config_ParaFile_Fail;
++ }
++
++ // Check if the CCK HighPower is turned ON.
++ // This is used to calculate PWDB.
++ pHalData->bCckHighPower = (BOOLEAN)(PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2, 0x200));
++
++phy_BB8190_Config_ParaFile_Fail:
++
++ return rtStatus;
++}
++
++
++int
++PHY_BBConfig8192C(
++ IN PADAPTER Adapter
++ )
++{
++ int rtStatus = _SUCCESS;
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ u32 RegVal;
++ u8 TmpU1B=0;
++ u8 value8;
++
++ phy_InitBBRFRegisterDefinition(Adapter);
++
++ if(IS_HARDWARE_TYPE_8723A(Adapter))
++ {
++ // Suggested by Scott. tynli_test. 2010.12.30.
++ //1. 0x28[1] = 1
++ TmpU1B = rtw_read8(Adapter, REG_AFE_PLL_CTRL);
++ rtw_udelay_os(2);
++ rtw_write8(Adapter, REG_AFE_PLL_CTRL, (TmpU1B|BIT1));
++ rtw_udelay_os(2);
++
++ //2. 0x29[7:0] = 0xFF
++ rtw_write8(Adapter, REG_AFE_PLL_CTRL+1, 0xff);
++ rtw_udelay_os(2);
++
++ //3. 0x02[1:0] = 2b'11
++ TmpU1B = rtw_read8(Adapter, REG_SYS_FUNC_EN);
++ rtw_write8(Adapter, REG_SYS_FUNC_EN, (TmpU1B|FEN_BB_GLB_RSTn|FEN_BBRSTB));
++
++ //undo clock gated
++ rtw_write32(Adapter, rFPGA0_XCD_RFParameter, rtw_read32(Adapter, rFPGA0_XCD_RFParameter)&(~BIT31));
++
++ //4. 0x25[6] = 0
++ TmpU1B = rtw_read8(Adapter, REG_AFE_XTAL_CTRL+1);
++ rtw_write8(Adapter, REG_AFE_XTAL_CTRL+1, (TmpU1B&(~BIT6)));
++
++ //5. 0x24[20] = 0 //Advised by SD3 Alex Wang. 2011.02.09.
++ TmpU1B = rtw_read8(Adapter, REG_AFE_XTAL_CTRL+2);
++ rtw_write8(Adapter, REG_AFE_XTAL_CTRL+2, (TmpU1B&(~BIT4)));
++
++ //6. 0x1f[7:0] = 0x07
++ rtw_write8(Adapter, REG_RF_CTRL, 0x07);
++ }
++ else
++ {
++ // Enable BB and RF
++ RegVal = rtw_read16(Adapter, REG_SYS_FUNC_EN);
++ rtw_write16(Adapter, REG_SYS_FUNC_EN, (u16)(RegVal|BIT13|BIT0|BIT1));
++
++ // 20090923 Joseph: Advised by Steven and Jenyu. Power sequence before init RF.
++ rtw_write8(Adapter, REG_AFE_PLL_CTRL, 0x83);
++ rtw_write8(Adapter, REG_AFE_PLL_CTRL+1, 0xdb);
++
++ rtw_write8(Adapter, REG_RF_CTRL, RF_EN|RF_RSTB|RF_SDMRSTB);
++
++#ifdef CONFIG_USB_HCI
++ rtw_write8(Adapter, REG_SYS_FUNC_EN, FEN_USBA | FEN_USBD | FEN_BB_GLB_RSTn | FEN_BBRSTB);
++#else
++ rtw_write8(Adapter, REG_SYS_FUNC_EN, FEN_PPLL|FEN_PCIEA|FEN_DIO_PCIE|FEN_BB_GLB_RSTn|FEN_BBRSTB);
++#endif
++
++ //undo clock gated
++ rtw_write32(Adapter, rFPGA0_XCD_RFParameter, rtw_read32(Adapter, rFPGA0_XCD_RFParameter)&(~BIT31));
++
++ // 2009/10/21 by SD1 Jong. Modified by tynli. Not in Documented in V8.1.
++#ifdef CONFIG_USB_HCI
++ //To Fix MAC loopback mode fail. Suggested by SD4 Johnny. 2010.03.23.
++ rtw_write8(Adapter, REG_LDOHCI12_CTRL, 0x0f);
++ rtw_write8(Adapter, 0x15, 0xe9);
++#endif
++
++ rtw_write8(Adapter, REG_AFE_XTAL_CTRL+1, 0x80);
++
++#ifdef CONFIG_PCI_HCI
++ // Force use left antenna by default for 88C.
++ // if(!IS_92C_SERIAL(pHalData->VersionID) || IS_92C_1T2R(pHalData->VersionID))
++ if(Adapter->ledpriv.LedStrategy != SW_LED_MODE10)
++ {
++ RegVal = rtw_read32(Adapter, REG_LEDCFG0);
++ rtw_write32(Adapter, REG_LEDCFG0, RegVal|BIT23);
++ }
++#endif
++ }
++
++ //
++ // Config BB and AGC
++ //
++ rtStatus = phy_BB8192C_Config_ParaFile(Adapter);
++#if 0
++ switch(Adapter->MgntInfo.bRegHwParaFile)
++ {
++ case 0:
++ phy_BB8190_Config_HardCode(Adapter);
++ break;
++
++ case 1:
++ rtStatus = phy_BB8192C_Config_ParaFile(Adapter);
++ break;
++
++ case 2:
++ // Partial Modify.
++ phy_BB8190_Config_HardCode(Adapter);
++ phy_BB8192C_Config_ParaFile(Adapter);
++ break;
++
++ default:
++ phy_BB8190_Config_HardCode(Adapter);
++ break;
++ }
++#endif
++#ifdef CONFIG_USB_HCI
++ if(IS_HARDWARE_TYPE_8192CU(Adapter)&&IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)
++ &&(pHalData->BoardType == BOARD_USB_High_PA))
++ rtw_write8(Adapter, 0xc72, 0x50);
++#endif
++
++ return rtStatus;
++}
++
++
++int
++PHY_RFConfig8192C(
++ IN PADAPTER Adapter
++ )
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ int rtStatus = _SUCCESS;
++
++ //
++ // RF config
++ //
++ rtStatus = PHY_RF6052_Config8192C(Adapter);
++#if 0
++ switch(pHalData->rf_chip)
++ {
++ case RF_6052:
++ rtStatus = PHY_RF6052_Config(Adapter);
++ break;
++ case RF_8225:
++ rtStatus = PHY_RF8225_Config(Adapter);
++ break;
++ case RF_8256:
++ rtStatus = PHY_RF8256_Config(Adapter);
++ break;
++ case RF_8258:
++ break;
++ case RF_PSEUDO_11N:
++ rtStatus = PHY_RF8225_Config(Adapter);
++ break;
++ default: //for MacOs Warning: "RF_TYPE_MIN" not handled in switch
++ break;
++ }
++#endif
++ return rtStatus;
++}
++
++
++/*-----------------------------------------------------------------------------
++ * Function: PHY_ConfigRFWithParaFile()
++ *
++ * Overview: This function read RF parameters from general file format, and do RF 3-wire
++ *
++ * Input: PADAPTER Adapter
++ * ps1Byte pFileName
++ * RF_RADIO_PATH_E eRFPath
++ *
++ * Output: NONE
++ *
++ * Return: RT_STATUS_SUCCESS: configuration file exist
++ *
++ * Note: Delay may be required for RF configuration
++ *---------------------------------------------------------------------------*/
++int
++rtl8192c_PHY_ConfigRFWithParaFile(
++ IN PADAPTER Adapter,
++ IN u8* pFileName,
++ RF_RADIO_PATH_E eRFPath
++)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++
++ int rtStatus = _SUCCESS;
++
++
++ return rtStatus;
++
++}
++
++//****************************************
++// The following is for High Power PA
++//****************************************
++#define HighPowerRadioAArrayLen 22
++//This is for High power PA
++u32 Rtl8192S_HighPower_RadioA_Array[HighPowerRadioAArrayLen] = {
++0x013,0x00029ea4,
++0x013,0x00025e74,
++0x013,0x00020ea4,
++0x013,0x0001ced0,
++0x013,0x00019f40,
++0x013,0x00014e70,
++0x013,0x000106a0,
++0x013,0x0000c670,
++0x013,0x000082a0,
++0x013,0x00004270,
++0x013,0x00000240,
++};
++
++int
++PHY_ConfigRFExternalPA(
++ IN PADAPTER Adapter,
++ RF_RADIO_PATH_E eRFPath
++)
++{
++ int rtStatus = _SUCCESS;
++#ifdef CONFIG_USB_HCI
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ u16 i=0;
++
++ if(!pHalData->ExternalPA)
++ {
++ return rtStatus;
++ }
++
++ // 2010/10/19 MH According to Jenyu/EEChou 's opinion, we need not to execute the
++ // same code as SU. It is already updated in radio_a_1T_HP.txt.
++#if 0
++ //add for SU High Power PA
++ for(i = 0;i<HighPowerRadioAArrayLen; i=i+2)
++ {
++ RT_TRACE(COMP_INIT, DBG_LOUD, ("External PA, write RF 0x%lx=0x%lx\n", Rtl8192S_HighPower_RadioA_Array[i], Rtl8192S_HighPower_RadioA_Array[i+1]));
++ PHY_SetRFReg(Adapter, eRFPath, Rtl8192S_HighPower_RadioA_Array[i], bRFRegOffsetMask, Rtl8192S_HighPower_RadioA_Array[i+1]);
++ }
++#endif
++
++#endif
++ return rtStatus;
++}
++//****************************************
++/*-----------------------------------------------------------------------------
++ * Function: PHY_ConfigRFWithHeaderFile()
++ *
++ * Overview: This function read RF parameters from general file format, and do RF 3-wire
++ *
++ * Input: PADAPTER Adapter
++ * ps1Byte pFileName
++ * RF_RADIO_PATH_E eRFPath
++ *
++ * Output: NONE
++ *
++ * Return: RT_STATUS_SUCCESS: configuration file exist
++ *
++ * Note: Delay may be required for RF configuration
++ *---------------------------------------------------------------------------*/
++int
++rtl8192c_PHY_ConfigRFWithHeaderFile(
++ IN PADAPTER Adapter,
++ RF_RADIO_PATH_E eRFPath
++)
++{
++
++ int i;
++ int rtStatus = _SUCCESS;
++ u32* Rtl819XRadioA_Array_Table;
++ u32* Rtl819XRadioB_Array_Table;
++ u16 RadioA_ArrayLen,RadioB_ArrayLen;
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++
++ //
++ // 2009.11.24. Modified by tynli.
++ //
++ if(IS_92C_SERIAL(pHalData->VersionID))
++ {
++ RadioA_ArrayLen = RadioA_2TArrayLength;
++ Rtl819XRadioA_Array_Table = Rtl819XRadioA_2TArray;
++ RadioB_ArrayLen = RadioB_2TArrayLength;
++ Rtl819XRadioB_Array_Table = Rtl819XRadioB_2TArray;
++ }
++ else
++ {
++ RadioA_ArrayLen = RadioA_1TArrayLength;
++ Rtl819XRadioA_Array_Table = Rtl819XRadioA_1TArray;
++ RadioB_ArrayLen = RadioB_1TArrayLength;
++ Rtl819XRadioB_Array_Table = Rtl819XRadioB_1TArray;
++#ifdef CONFIG_USB_HCI
++ if( BOARD_MINICARD == pHalData->BoardType )
++ {
++ RadioA_ArrayLen = RadioA_1T_mCardArrayLength;
++ Rtl819XRadioA_Array_Table = Rtl819XRadioA_1T_mCardArray;
++ RadioB_ArrayLen = RadioB_1T_mCardArrayLength;
++ Rtl819XRadioB_Array_Table = Rtl819XRadioB_1T_mCardArray;
++ }
++ else if( BOARD_USB_High_PA == pHalData->BoardType )
++ {
++ RadioA_ArrayLen = RadioA_1T_HPArrayLength;
++ Rtl819XRadioA_Array_Table = Rtl819XRadioA_1T_HPArray;
++ }
++#endif
++ }
++
++ switch(eRFPath){
++ case RF_PATH_A:
++ #ifdef CONFIG_IOL_RF_RF90_PATH_A
++ if(rtw_IOL_applied(Adapter))
++ {
++ struct xmit_frame *xmit_frame;
++ if((xmit_frame=rtw_IOL_accquire_xmit_frame(Adapter)) == NULL) {
++ rtStatus = _FAIL;
++ goto exit;
++ }
++
++ for(i = 0;i<RadioA_ArrayLen; i=i+2)
++ {
++ if(Rtl819XRadioA_Array_Table[i] == 0xfe)
++ rtw_IOL_append_DELAY_MS_cmd(xmit_frame, 50);
++ else if (Rtl819XRadioA_Array_Table[i] == 0xfd)
++ rtw_IOL_append_DELAY_MS_cmd(xmit_frame, 5);
++ else if (Rtl819XRadioA_Array_Table[i] == 0xfc)
++ rtw_IOL_append_DELAY_MS_cmd(xmit_frame, 1);
++ else if (Rtl819XRadioA_Array_Table[i] == 0xfb)
++ rtw_IOL_append_DELAY_US_cmd(xmit_frame, 50);
++ else if (Rtl819XRadioA_Array_Table[i] == 0xfa)
++ rtw_IOL_append_DELAY_US_cmd(xmit_frame, 5);
++ else if (Rtl819XRadioA_Array_Table[i] == 0xf9)
++ rtw_IOL_append_DELAY_US_cmd(xmit_frame, 1);
++ else
++ {
++ BB_REGISTER_DEFINITION_T *pPhyReg = &pHalData->PHYRegDef[eRFPath];
++ u32 NewOffset = 0;
++ u32 DataAndAddr = 0;
++
++ NewOffset = Rtl819XRadioA_Array_Table[i] & 0x3f;
++ DataAndAddr = ((NewOffset<<20) | (Rtl819XRadioA_Array_Table[i+1]&0x000fffff)) & 0x0fffffff; // T65 RF
++ rtw_IOL_append_WD_cmd(xmit_frame, pPhyReg->rf3wireOffset, DataAndAddr);
++ }
++ }
++ rtStatus = rtw_IOL_exec_cmds_sync(Adapter, xmit_frame, 1000);
++ }
++ else
++ #endif
++ {
++ for(i = 0;i<RadioA_ArrayLen; i=i+2)
++ {
++ if(Rtl819XRadioA_Array_Table[i] == 0xfe) {
++ #ifdef CONFIG_LONG_DELAY_ISSUE
++ rtw_msleep_os(50);
++ #else
++ rtw_mdelay_os(50);
++ #endif
++ }
++ else if (Rtl819XRadioA_Array_Table[i] == 0xfd)
++ rtw_mdelay_os(5);
++ else if (Rtl819XRadioA_Array_Table[i] == 0xfc)
++ rtw_mdelay_os(1);
++ else if (Rtl819XRadioA_Array_Table[i] == 0xfb)
++ rtw_udelay_os(50);
++ else if (Rtl819XRadioA_Array_Table[i] == 0xfa)
++ rtw_udelay_os(5);
++ else if (Rtl819XRadioA_Array_Table[i] == 0xf9)
++ rtw_udelay_os(1);
++ else
++ {
++ PHY_SetRFReg(Adapter, eRFPath, Rtl819XRadioA_Array_Table[i], bRFRegOffsetMask, Rtl819XRadioA_Array_Table[i+1]);
++ // Add 1us delay between BB/RF register setting.
++ rtw_udelay_os(1);
++ }
++ }
++ }
++
++ //Add for High Power PA
++ PHY_ConfigRFExternalPA(Adapter, eRFPath);
++ break;
++ case RF_PATH_B:
++ #ifdef CONFIG_IOL_RF_RF90_PATH_B
++ if(rtw_IOL_applied(Adapter))
++ {
++ struct xmit_frame *xmit_frame;
++ if((xmit_frame=rtw_IOL_accquire_xmit_frame(Adapter)) == NULL) {
++ rtStatus = _FAIL;
++ goto exit;
++ }
++
++ for(i = 0;i<RadioB_ArrayLen; i=i+2)
++ {
++ if(Rtl819XRadioB_Array_Table[i] == 0xfe)
++ rtw_IOL_append_DELAY_MS_cmd(xmit_frame, 50);
++ else if (Rtl819XRadioB_Array_Table[i] == 0xfd)
++ rtw_IOL_append_DELAY_MS_cmd(xmit_frame, 5);
++ else if (Rtl819XRadioB_Array_Table[i] == 0xfc)
++ rtw_IOL_append_DELAY_MS_cmd(xmit_frame, 1);
++ else if (Rtl819XRadioB_Array_Table[i] == 0xfb)
++ rtw_IOL_append_DELAY_US_cmd(xmit_frame, 50);
++ else if (Rtl819XRadioB_Array_Table[i] == 0xfa)
++ rtw_IOL_append_DELAY_US_cmd(xmit_frame, 5);
++ else if (Rtl819XRadioB_Array_Table[i] == 0xf9)
++ rtw_IOL_append_DELAY_US_cmd(xmit_frame, 1);
++ else
++ {
++ BB_REGISTER_DEFINITION_T *pPhyReg = &pHalData->PHYRegDef[eRFPath];
++ u32 NewOffset = 0;
++ u32 DataAndAddr = 0;
++
++ NewOffset = Rtl819XRadioB_Array_Table[i] & 0x3f;
++ DataAndAddr = ((NewOffset<<20) | (Rtl819XRadioB_Array_Table[i+1]&0x000fffff)) & 0x0fffffff; // T65 RF
++ rtw_IOL_append_WD_cmd(xmit_frame, pPhyReg->rf3wireOffset, DataAndAddr);
++ }
++ }
++ rtStatus = rtw_IOL_exec_cmds_sync(Adapter, xmit_frame, 1000);
++ }
++ else
++ #endif
++ {
++ for(i = 0;i<RadioB_ArrayLen; i=i+2)
++ {
++ if(Rtl819XRadioB_Array_Table[i] == 0xfe)
++ { // Deay specific ms. Only RF configuration require delay.
++#if 0//#ifdef CONFIG_USB_HCI
++ #ifdef CONFIG_LONG_DELAY_ISSUE
++ rtw_msleep_os(1000);
++ #else
++ rtw_mdelay_os(1000);
++ #endif
++#else
++ #ifdef CONFIG_LONG_DELAY_ISSUE
++ rtw_msleep_os(50);
++ #else
++ rtw_mdelay_os(50);
++ #endif
++#endif
++ }
++ else if (Rtl819XRadioB_Array_Table[i] == 0xfd)
++ rtw_mdelay_os(5);
++ else if (Rtl819XRadioB_Array_Table[i] == 0xfc)
++ rtw_mdelay_os(1);
++ else if (Rtl819XRadioB_Array_Table[i] == 0xfb)
++ rtw_udelay_os(50);
++ else if (Rtl819XRadioB_Array_Table[i] == 0xfa)
++ rtw_udelay_os(5);
++ else if (Rtl819XRadioB_Array_Table[i] == 0xf9)
++ rtw_udelay_os(1);
++ else
++ {
++ PHY_SetRFReg(Adapter, eRFPath, Rtl819XRadioB_Array_Table[i], bRFRegOffsetMask, Rtl819XRadioB_Array_Table[i+1]);
++ // Add 1us delay between BB/RF register setting.
++ rtw_udelay_os(1);
++ }
++ }
++ }
++
++ break;
++ case RF_PATH_C:
++ break;
++ case RF_PATH_D:
++ break;
++ }
++
++exit:
++ return rtStatus;
++
++}
++
++
++/*-----------------------------------------------------------------------------
++ * Function: PHY_CheckBBAndRFOK()
++ *
++ * Overview: This function is write register and then readback to make sure whether
++ * BB[PHY0, PHY1], RF[Patha, path b, path c, path d] is Ok
++ *
++ * Input: PADAPTER Adapter
++ * HW90_BLOCK_E CheckBlock
++ * RF_RADIO_PATH_E eRFPath // it is used only when CheckBlock is HW90_BLOCK_RF
++ *
++ * Output: NONE
++ *
++ * Return: RT_STATUS_SUCCESS: PHY is OK
++ *
++ * Note: This function may be removed in the ASIC
++ *---------------------------------------------------------------------------*/
++int
++PHY_CheckBBAndRFOK(
++ IN PADAPTER Adapter,
++ IN HW90_BLOCK_E CheckBlock,
++ IN RF_RADIO_PATH_E eRFPath
++ )
++{
++ int rtStatus = _SUCCESS;
++
++ u32 i, CheckTimes = 4,ulRegRead = 0;
++
++ u32 WriteAddr[4];
++ u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f};
++
++ // Initialize register address offset to be checked
++ WriteAddr[HW90_BLOCK_MAC] = 0x100;
++ WriteAddr[HW90_BLOCK_PHY0] = 0x900;
++ WriteAddr[HW90_BLOCK_PHY1] = 0x800;
++ WriteAddr[HW90_BLOCK_RF] = 0x3;
++
++ for(i=0 ; i < CheckTimes ; i++)
++ {
++
++ //
++ // Write Data to register and readback
++ //
++ switch(CheckBlock)
++ {
++ case HW90_BLOCK_MAC:
++ //RT_ASSERT(FALSE, ("PHY_CheckBBRFOK(): Never Write 0x100 here!"));
++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("PHY_CheckBBRFOK(): Never Write 0x100 here!\n"));
++ break;
++
++ case HW90_BLOCK_PHY0:
++ case HW90_BLOCK_PHY1:
++ rtw_write32(Adapter, WriteAddr[CheckBlock], WriteData[i]);
++ ulRegRead = rtw_read32(Adapter, WriteAddr[CheckBlock]);
++ break;
++
++ case HW90_BLOCK_RF:
++ // When initialization, we want the delay function(delay_ms(), delay_us()
++ // ==> actually we call PlatformStallExecution()) to do NdisStallExecution()
++ // [busy wait] instead of NdisMSleep(). So we acquire RT_INITIAL_SPINLOCK
++ // to run at Dispatch level to achive it.
++ //cosa PlatformAcquireSpinLock(Adapter, RT_INITIAL_SPINLOCK);
++ WriteData[i] &= 0xfff;
++ PHY_SetRFReg(Adapter, eRFPath, WriteAddr[HW90_BLOCK_RF], bRFRegOffsetMask, WriteData[i]);
++ // TODO: we should not delay for such a long time. Ask SD3
++ rtw_mdelay_os(10);
++ ulRegRead = PHY_QueryRFReg(Adapter, eRFPath, WriteAddr[HW90_BLOCK_RF], bMaskDWord);
++ rtw_mdelay_os(10);
++ //cosa PlatformReleaseSpinLock(Adapter, RT_INITIAL_SPINLOCK);
++ break;
++
++ default:
++ rtStatus = _FAIL;
++ break;
++ }
++
++
++ //
++ // Check whether readback data is correct
++ //
++ if(ulRegRead != WriteData[i])
++ {
++ //RT_TRACE(COMP_FPGA, DBG_LOUD, ("ulRegRead: %lx, WriteData: %lx \n", ulRegRead, WriteData[i]));
++ rtStatus = _FAIL;
++ break;
++ }
++ }
++
++ return rtStatus;
++}
++
++
++VOID
++rtl8192c_PHY_GetHWRegOriginalValue(
++ IN PADAPTER Adapter
++ )
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++
++ // read rx initial gain
++ pHalData->DefaultInitialGain[0] = (u8)PHY_QueryBBReg(Adapter, rOFDM0_XAAGCCore1, bMaskByte0);
++ pHalData->DefaultInitialGain[1] = (u8)PHY_QueryBBReg(Adapter, rOFDM0_XBAGCCore1, bMaskByte0);
++ pHalData->DefaultInitialGain[2] = (u8)PHY_QueryBBReg(Adapter, rOFDM0_XCAGCCore1, bMaskByte0);
++ pHalData->DefaultInitialGain[3] = (u8)PHY_QueryBBReg(Adapter, rOFDM0_XDAGCCore1, bMaskByte0);
++ //RT_TRACE(COMP_INIT, DBG_LOUD,
++ //("Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x) \n",
++ //pHalData->DefaultInitialGain[0], pHalData->DefaultInitialGain[1],
++ //pHalData->DefaultInitialGain[2], pHalData->DefaultInitialGain[3]));
++
++ // read framesync
++ pHalData->framesync = (u8)PHY_QueryBBReg(Adapter, rOFDM0_RxDetector3, bMaskByte0);
++ pHalData->framesyncC34 = PHY_QueryBBReg(Adapter, rOFDM0_RxDetector2, bMaskDWord);
++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("Default framesync (0x%x) = 0x%x \n",
++ // rOFDM0_RxDetector3, pHalData->framesync));
++}
++
++
++//
++// Description:
++// Map dBm into Tx power index according to
++// current HW model, for example, RF and PA, and
++// current wireless mode.
++// By Bruce, 2008-01-29.
++//
++static u8
++phy_DbmToTxPwrIdx(
++ IN PADAPTER Adapter,
++ IN WIRELESS_MODE WirelessMode,
++ IN int PowerInDbm
++ )
++{
++ u8 TxPwrIdx = 0;
++ int Offset = 0;
++
++
++ //
++ // Tested by MP, we found that CCK Index 0 equals to 8dbm, OFDM legacy equals to
++ // 3dbm, and OFDM HT equals to 0dbm repectively.
++ // Note:
++ // The mapping may be different by different NICs. Do not use this formula for what needs accurate result.
++ // By Bruce, 2008-01-29.
++ //
++ switch(WirelessMode)
++ {
++ case WIRELESS_MODE_B:
++ Offset = -7;
++ break;
++
++ case WIRELESS_MODE_G:
++ case WIRELESS_MODE_N_24G:
++ Offset = -8;
++ break;
++ default:
++ Offset = -8;
++ break;
++ }
++
++ if((PowerInDbm - Offset) > 0)
++ {
++ TxPwrIdx = (u8)((PowerInDbm - Offset) * 2);
++ }
++ else
++ {
++ TxPwrIdx = 0;
++ }
++
++ // Tx Power Index is too large.
++ if(TxPwrIdx > MAX_TXPWR_IDX_NMODE_92S)
++ TxPwrIdx = MAX_TXPWR_IDX_NMODE_92S;
++
++ return TxPwrIdx;
++}
++
++//
++// Description:
++// Map Tx power index into dBm according to
++// current HW model, for example, RF and PA, and
++// current wireless mode.
++// By Bruce, 2008-01-29.
++//
++int
++phy_TxPwrIdxToDbm(
++ IN PADAPTER Adapter,
++ IN WIRELESS_MODE WirelessMode,
++ IN u8 TxPwrIdx
++ )
++{
++ int Offset = 0;
++ int PwrOutDbm = 0;
++
++ //
++ // Tested by MP, we found that CCK Index 0 equals to -7dbm, OFDM legacy equals to -8dbm.
++ // Note:
++ // The mapping may be different by different NICs. Do not use this formula for what needs accurate result.
++ // By Bruce, 2008-01-29.
++ //
++ switch(WirelessMode)
++ {
++ case WIRELESS_MODE_B:
++ Offset = -7;
++ break;
++
++ case WIRELESS_MODE_G:
++ case WIRELESS_MODE_N_24G:
++ Offset = -8;
++ default:
++ Offset = -8;
++ break;
++ }
++
++ PwrOutDbm = TxPwrIdx / 2 + Offset; // Discard the decimal part.
++
++ return PwrOutDbm;
++}
++
++
++/*-----------------------------------------------------------------------------
++ * Function: GetTxPowerLevel8190()
++ *
++ * Overview: This function is export to "common" moudule
++ *
++ * Input: PADAPTER Adapter
++ * psByte Power Level
++ *
++ * Output: NONE
++ *
++ * Return: NONE
++ *
++ *---------------------------------------------------------------------------*/
++VOID
++PHY_GetTxPowerLevel8192C(
++ IN PADAPTER Adapter,
++ OUT u32* powerlevel
++ )
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ u8 TxPwrLevel = 0;
++ int TxPwrDbm;
++
++ //
++ // Because the Tx power indexes are different, we report the maximum of them to
++ // meet the CCX TPC request. By Bruce, 2008-01-31.
++ //
++
++ // CCK
++ TxPwrLevel = pHalData->CurrentCckTxPwrIdx;
++ TxPwrDbm = phy_TxPwrIdxToDbm(Adapter, WIRELESS_MODE_B, TxPwrLevel);
++
++ // Legacy OFDM
++ TxPwrLevel = pHalData->CurrentOfdm24GTxPwrIdx + pHalData->LegacyHTTxPowerDiff;
++
++ // Compare with Legacy OFDM Tx power.
++ if(phy_TxPwrIdxToDbm(Adapter, WIRELESS_MODE_G, TxPwrLevel) > TxPwrDbm)
++ TxPwrDbm = phy_TxPwrIdxToDbm(Adapter, WIRELESS_MODE_G, TxPwrLevel);
++
++ // HT OFDM
++ TxPwrLevel = pHalData->CurrentOfdm24GTxPwrIdx;
++
++ // Compare with HT OFDM Tx power.
++ if(phy_TxPwrIdxToDbm(Adapter, WIRELESS_MODE_N_24G, TxPwrLevel) > TxPwrDbm)
++ TxPwrDbm = phy_TxPwrIdxToDbm(Adapter, WIRELESS_MODE_N_24G, TxPwrLevel);
++
++ *powerlevel = TxPwrDbm;
++}
++
++
++static void getTxPowerIndex(
++ IN PADAPTER Adapter,
++ IN u8 channel,
++ IN OUT u8* cckPowerLevel,
++ IN OUT u8* ofdmPowerLevel
++ )
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ u8 index = (channel -1);
++ // 1. CCK
++ cckPowerLevel[RF_PATH_A] = pHalData->TxPwrLevelCck[RF_PATH_A][index]; //RF-A
++ cckPowerLevel[RF_PATH_B] = pHalData->TxPwrLevelCck[RF_PATH_B][index]; //RF-B
++
++ // 2. OFDM for 1S or 2S
++ if (GET_RF_TYPE(Adapter) == RF_1T2R || GET_RF_TYPE(Adapter) == RF_1T1R)
++ {
++ // Read HT 40 OFDM TX power
++ ofdmPowerLevel[RF_PATH_A] = pHalData->TxPwrLevelHT40_1S[RF_PATH_A][index];
++ ofdmPowerLevel[RF_PATH_B] = pHalData->TxPwrLevelHT40_1S[RF_PATH_B][index];
++ }
++ else if (GET_RF_TYPE(Adapter) == RF_2T2R)
++ {
++ // Read HT 40 OFDM TX power
++ ofdmPowerLevel[RF_PATH_A] = pHalData->TxPwrLevelHT40_2S[RF_PATH_A][index];
++ ofdmPowerLevel[RF_PATH_B] = pHalData->TxPwrLevelHT40_2S[RF_PATH_B][index];
++ }
++ //RTPRINT(FPHY, PHY_TXPWR, ("Channel-%d, set tx power index !!\n", channel));
++}
++
++static void ccxPowerIndexCheck(
++ IN PADAPTER Adapter,
++ IN u8 channel,
++ IN OUT u8* cckPowerLevel,
++ IN OUT u8* ofdmPowerLevel
++ )
++{
++#if 0
++ PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo);
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ PRT_CCX_INFO pCcxInfo = GET_CCX_INFO(pMgntInfo);
++
++ //
++ // CCX 2 S31, AP control of client transmit power:
++ // 1. We shall not exceed Cell Power Limit as possible as we can.
++ // 2. Tolerance is +/- 5dB.
++ // 3. 802.11h Power Contraint takes higher precedence over CCX Cell Power Limit.
++ //
++ // TODO:
++ // 1. 802.11h power contraint
++ //
++ // 071011, by rcnjko.
++ //
++ if( pMgntInfo->OpMode == RT_OP_MODE_INFRASTRUCTURE &&
++ pMgntInfo->mAssoc &&
++ pCcxInfo->bUpdateCcxPwr &&
++ pCcxInfo->bWithCcxCellPwr &&
++ channel == pMgntInfo->dot11CurrentChannelNumber)
++ {
++ u1Byte CckCellPwrIdx = phy_DbmToTxPwrIdx(Adapter, WIRELESS_MODE_B, pCcxInfo->CcxCellPwr);
++ u1Byte LegacyOfdmCellPwrIdx = phy_DbmToTxPwrIdx(Adapter, WIRELESS_MODE_G, pCcxInfo->CcxCellPwr);
++ u1Byte OfdmCellPwrIdx = phy_DbmToTxPwrIdx(Adapter, WIRELESS_MODE_N_24G, pCcxInfo->CcxCellPwr);
++
++ RT_TRACE(COMP_TXAGC, DBG_LOUD,
++ ("CCX Cell Limit: %d dbm => CCK Tx power index : %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",
++ pCcxInfo->CcxCellPwr, CckCellPwrIdx, LegacyOfdmCellPwrIdx, OfdmCellPwrIdx));
++ RT_TRACE(COMP_TXAGC, DBG_LOUD,
++ ("EEPROM channel(%d) => CCK Tx power index: %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",
++ channel, cckPowerLevel[0], ofdmPowerLevel[0] + pHalData->LegacyHTTxPowerDiff, ofdmPowerLevel[0]));
++
++ // CCK
++ if(cckPowerLevel[0] > CckCellPwrIdx)
++ cckPowerLevel[0] = CckCellPwrIdx;
++ // Legacy OFDM, HT OFDM
++ if(ofdmPowerLevel[0] + pHalData->LegacyHTTxPowerDiff > LegacyOfdmCellPwrIdx)
++ {
++ if((OfdmCellPwrIdx - pHalData->LegacyHTTxPowerDiff) > 0)
++ {
++ ofdmPowerLevel[0] = OfdmCellPwrIdx - pHalData->LegacyHTTxPowerDiff;
++ }
++ else
++ {
++ ofdmPowerLevel[0] = 0;
++ }
++ }
++
++ RT_TRACE(COMP_TXAGC, DBG_LOUD,
++ ("Altered CCK Tx power index : %d, Legacy OFDM Tx power index: %d, OFDM Tx power index: %d\n",
++ cckPowerLevel[0], ofdmPowerLevel[0] + pHalData->LegacyHTTxPowerDiff, ofdmPowerLevel[0]));
++ }
++
++ pHalData->CurrentCckTxPwrIdx = cckPowerLevel[0];
++ pHalData->CurrentOfdm24GTxPwrIdx = ofdmPowerLevel[0];
++
++ RT_TRACE(COMP_TXAGC, DBG_LOUD,
++ ("PHY_SetTxPowerLevel8192S(): CCK Tx power index : %d, Legacy OFDM Tx power index: %d, OFDM Tx power index: %d\n",
++ cckPowerLevel[0], ofdmPowerLevel[0] + pHalData->LegacyHTTxPowerDiff, ofdmPowerLevel[0]));
++#endif
++}
++/*-----------------------------------------------------------------------------
++ * Function: SetTxPowerLevel8190()
++ *
++ * Overview: This function is export to "HalCommon" moudule
++ * We must consider RF path later!!!!!!!
++ *
++ * Input: PADAPTER Adapter
++ * u1Byte channel
++ *
++ * Output: NONE
++ *
++ * Return: NONE
++ * 2008/11/04 MHC We remove EEPROM_93C56.
++ * We need to move CCX relative code to independet file.
++ * 2009/01/21 MHC Support new EEPROM format from SD3 requirement.
++ *
++ *---------------------------------------------------------------------------*/
++VOID
++PHY_SetTxPowerLevel8192C(
++ IN PADAPTER Adapter,
++ IN u8 channel
++ )
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ u8 cckPowerLevel[2], ofdmPowerLevel[2]; // [0]:RF-A, [1]:RF-B
++
++#if(MP_DRIVER == 1)
++ return;
++#endif
++
++ if(pHalData->bTXPowerDataReadFromEEPORM == _FALSE)
++ return;
++
++ getTxPowerIndex(Adapter, channel, &cckPowerLevel[0], &ofdmPowerLevel[0]);
++ //RTPRINT(FPHY, PHY_TXPWR, ("Channel-%d, cckPowerLevel (A / B) = 0x%x / 0x%x, ofdmPowerLevel (A / B) = 0x%x / 0x%x\n",
++ // channel, cckPowerLevel[0], cckPowerLevel[1], ofdmPowerLevel[0], ofdmPowerLevel[1]));
++
++ ccxPowerIndexCheck(Adapter, channel, &cckPowerLevel[0], &ofdmPowerLevel[0]);
++
++ rtl8192c_PHY_RF6052SetCckTxPower(Adapter, &cckPowerLevel[0]);
++ rtl8192c_PHY_RF6052SetOFDMTxPower(Adapter, &ofdmPowerLevel[0], channel);
++
++#if 0
++ switch(pHalData->rf_chip)
++ {
++ case RF_8225:
++ PHY_SetRF8225CckTxPower(Adapter, cckPowerLevel[0]);
++ PHY_SetRF8225OfdmTxPower(Adapter, ofdmPowerLevel[0]);
++ break;
++
++ case RF_8256:
++ PHY_SetRF8256CCKTxPower(Adapter, cckPowerLevel[0]);
++ PHY_SetRF8256OFDMTxPower(Adapter, ofdmPowerLevel[0]);
++ break;
++
++ case RF_6052:
++ PHY_RF6052SetCckTxPower(Adapter, &cckPowerLevel[0]);
++ PHY_RF6052SetOFDMTxPower(Adapter, &ofdmPowerLevel[0], channel);
++ break;
++
++ case RF_8258:
++ break;
++ }
++#endif
++
++}
++
++
++//
++// Description:
++// Update transmit power level of all channel supported.
++//
++// TODO:
++// A mode.
++// By Bruce, 2008-02-04.
++//
++BOOLEAN
++PHY_UpdateTxPowerDbm8192C(
++ IN PADAPTER Adapter,
++ IN int powerInDbm
++ )
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ u8 idx;
++ u8 rf_path;
++
++ // TODO: A mode Tx power.
++ u8 CckTxPwrIdx = phy_DbmToTxPwrIdx(Adapter, WIRELESS_MODE_B, powerInDbm);
++ u8 OfdmTxPwrIdx = phy_DbmToTxPwrIdx(Adapter, WIRELESS_MODE_N_24G, powerInDbm);
++
++ if(OfdmTxPwrIdx - pHalData->LegacyHTTxPowerDiff > 0)
++ OfdmTxPwrIdx -= pHalData->LegacyHTTxPowerDiff;
++ else
++ OfdmTxPwrIdx = 0;
++
++ //RT_TRACE(COMP_TXAGC, DBG_LOUD, ("PHY_UpdateTxPowerDbm8192S(): %ld dBm , CckTxPwrIdx = %d, OfdmTxPwrIdx = %d\n", powerInDbm, CckTxPwrIdx, OfdmTxPwrIdx));
++
++ for(idx = 0; idx < 14; idx++)
++ {
++ for (rf_path = 0; rf_path < 2; rf_path++)
++ {
++ pHalData->TxPwrLevelCck[rf_path][idx] = CckTxPwrIdx;
++ pHalData->TxPwrLevelHT40_1S[rf_path][idx] =
++ pHalData->TxPwrLevelHT40_2S[rf_path][idx] = OfdmTxPwrIdx;
++ }
++ }
++
++ //Adapter->HalFunc.SetTxPowerLevelHandler(Adapter, pHalData->CurrentChannel);//gtest:todo
++
++ return _TRUE;
++}
++
++
++/*
++ Description:
++ When beacon interval is changed, the values of the
++ hw registers should be modified.
++ By tynli, 2008.10.24.
++
++*/
++
++
++void
++rtl8192c_PHY_SetBeaconHwReg(
++ IN PADAPTER Adapter,
++ IN u16 BeaconInterval
++ )
++{
++
++}
++
++
++VOID
++PHY_ScanOperationBackup8192C(
++ IN PADAPTER Adapter,
++ IN u8 Operation
++ )
++{
++#if 0
++ IO_TYPE IoType;
++
++ if(!Adapter->bDriverStopped)
++ {
++ switch(Operation)
++ {
++ case SCAN_OPT_BACKUP:
++ IoType = IO_CMD_PAUSE_DM_BY_SCAN;
++ rtw_hal_set_hwreg(Adapter,HW_VAR_IO_CMD, (pu1Byte)&IoType);
++
++ break;
++
++ case SCAN_OPT_RESTORE:
++ IoType = IO_CMD_RESUME_DM_BY_SCAN;
++ rtw_hal_set_hwreg(Adapter,HW_VAR_IO_CMD, (pu1Byte)&IoType);
++ break;
++
++ default:
++ RT_TRACE(COMP_SCAN, DBG_LOUD, ("Unknown Scan Backup Operation. \n"));
++ break;
++ }
++ }
++#endif
++}
++
++/*-----------------------------------------------------------------------------
++ * Function: PHY_SetBWModeCallback8192C()
++ *
++ * Overview: Timer callback function for SetSetBWMode
++ *
++ * Input: PRT_TIMER pTimer
++ *
++ * Output: NONE
++ *
++ * Return: NONE
++ *
++ * Note: (1) We do not take j mode into consideration now
++ * (2) Will two workitem of "switch channel" and "switch channel bandwidth" run
++ * concurrently?
++ *---------------------------------------------------------------------------*/
++static VOID
++_PHY_SetBWMode92C(
++ IN PADAPTER Adapter
++)
++{
++// PADAPTER Adapter = (PADAPTER)pTimer->Adapter;
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ u8 regBwOpMode;
++ u8 regRRSR_RSC;
++
++ //return;
++
++ // Added it for 20/40 mhz switch time evaluation by guangan 070531
++ //u4Byte NowL, NowH;
++ //u8Byte BeginTime, EndTime;
++
++ /*RT_TRACE(COMP_SCAN, DBG_LOUD, ("==>PHY_SetBWModeCallback8192C() Switch to %s bandwidth\n", \
++ pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz"))*/
++
++ if(pHalData->rf_chip == RF_PSEUDO_11N)
++ {
++ //pHalData->SetBWModeInProgress= _FALSE;
++ return;
++ }
++
++ // There is no 40MHz mode in RF_8225.
++ if(pHalData->rf_chip==RF_8225)
++ return;
++
++ if(Adapter->bDriverStopped)
++ return;
++
++ // Added it for 20/40 mhz switch time evaluation by guangan 070531
++ //NowL = PlatformEFIORead4Byte(Adapter, TSFR);
++ //NowH = PlatformEFIORead4Byte(Adapter, TSFR+4);
++ //BeginTime = ((u8Byte)NowH << 32) + NowL;
++
++ //3//
++ //3//<1>Set MAC register
++ //3//
++ //Adapter->HalFunc.SetBWModeHandler();
++
++ regBwOpMode = rtw_read8(Adapter, REG_BWOPMODE);
++ regRRSR_RSC = rtw_read8(Adapter, REG_RRSR+2);
++ //regBwOpMode = rtw_hal_get_hwreg(Adapter,HW_VAR_BWMODE,(pu1Byte)&regBwOpMode);
++
++ switch(pHalData->CurrentChannelBW)
++ {
++ case HT_CHANNEL_WIDTH_20:
++ regBwOpMode |= BW_OPMODE_20MHZ;
++ // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
++ rtw_write8(Adapter, REG_BWOPMODE, regBwOpMode);
++ break;
++
++ case HT_CHANNEL_WIDTH_40:
++ regBwOpMode &= ~BW_OPMODE_20MHZ;
++ // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
++ rtw_write8(Adapter, REG_BWOPMODE, regBwOpMode);
++
++ regRRSR_RSC = (regRRSR_RSC&0x90) |(pHalData->nCur40MhzPrimeSC<<5);
++ rtw_write8(Adapter, REG_RRSR+2, regRRSR_RSC);
++ break;
++
++ default:
++ /*RT_TRACE(COMP_DBG, DBG_LOUD, ("PHY_SetBWModeCallback8192C():
++ unknown Bandwidth: %#X\n",pHalData->CurrentChannelBW));*/
++ break;
++ }
++
++ //3//
++ //3//<2>Set PHY related register
++ //3//
++ switch(pHalData->CurrentChannelBW)
++ {
++ /* 20 MHz channel*/
++ case HT_CHANNEL_WIDTH_20:
++ PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x0);
++ PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x0);
++ PHY_SetBBReg(Adapter, rFPGA0_AnalogParameter2, BIT10, 1);
++
++ break;
++
++
++ /* 40 MHz channel*/
++ case HT_CHANNEL_WIDTH_40:
++ PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x1);
++ PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x1);
++
++ // Set Control channel to upper or lower. These settings are required only for 40MHz
++ PHY_SetBBReg(Adapter, rCCK0_System, bCCKSideBand, (pHalData->nCur40MhzPrimeSC>>1));
++ PHY_SetBBReg(Adapter, rOFDM1_LSTF, 0xC00, pHalData->nCur40MhzPrimeSC);
++ PHY_SetBBReg(Adapter, rFPGA0_AnalogParameter2, BIT10, 0);
++
++ PHY_SetBBReg(Adapter, 0x818, (BIT26|BIT27), (pHalData->nCur40MhzPrimeSC==HAL_PRIME_CHNL_OFFSET_LOWER)?2:1);
++
++ break;
++
++
++
++ default:
++ /*RT_TRACE(COMP_DBG, DBG_LOUD, ("PHY_SetBWModeCallback8192C(): unknown Bandwidth: %#X\n"\
++ ,pHalData->CurrentChannelBW));*/
++ break;
++
++ }
++ //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315
++
++ // Added it for 20/40 mhz switch time evaluation by guangan 070531
++ //NowL = PlatformEFIORead4Byte(Adapter, TSFR);
++ //NowH = PlatformEFIORead4Byte(Adapter, TSFR+4);
++ //EndTime = ((u8Byte)NowH << 32) + NowL;
++ //RT_TRACE(COMP_SCAN, DBG_LOUD, ("SetBWModeCallback8190Pci: time of SetBWMode = %I64d us!\n", (EndTime - BeginTime)));
++
++ //3<3>Set RF related register
++ switch(pHalData->rf_chip)
++ {
++ case RF_8225:
++ //PHY_SetRF8225Bandwidth(Adapter, pHalData->CurrentChannelBW);
++ break;
++
++ case RF_8256:
++ // Please implement this function in Hal8190PciPhy8256.c
++ //PHY_SetRF8256Bandwidth(Adapter, pHalData->CurrentChannelBW);
++ break;
++
++ case RF_8258:
++ // Please implement this function in Hal8190PciPhy8258.c
++ // PHY_SetRF8258Bandwidth();
++ break;
++
++ case RF_PSEUDO_11N:
++ // Do Nothing
++ break;
++
++ case RF_6052:
++ rtl8192c_PHY_RF6052SetBandwidth(Adapter, pHalData->CurrentChannelBW);
++ break;
++
++ default:
++ //RT_ASSERT(FALSE, ("Unknown RFChipID: %d\n", pHalData->RFChipID));
++ break;
++ }
++
++ //pHalData->SetBWModeInProgress= FALSE;
++
++ //RT_TRACE(COMP_SCAN, DBG_LOUD, ("<==PHY_SetBWModeCallback8192C() \n" ));
++}
++
++
++ /*-----------------------------------------------------------------------------
++ * Function: SetBWMode8190Pci()
++ *
++ * Overview: This function is export to "HalCommon" moudule
++ *
++ * Input: PADAPTER Adapter
++ * HT_CHANNEL_WIDTH Bandwidth //20M or 40M
++ *
++ * Output: NONE
++ *
++ * Return: NONE
++ *
++ * Note: We do not take j mode into consideration now
++ *---------------------------------------------------------------------------*/
++VOID
++PHY_SetBWMode8192C(
++ IN PADAPTER Adapter,
++ IN HT_CHANNEL_WIDTH Bandwidth, // 20M or 40M
++ IN unsigned char Offset // Upper, Lower, or Don't care
++)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ HT_CHANNEL_WIDTH tmpBW= pHalData->CurrentChannelBW;
++ // Modified it for 20/40 mhz switch by guangan 070531
++ //PMGNT_INFO pMgntInfo=&Adapter->MgntInfo;
++
++ //return;
++
++ //if(pHalData->SwChnlInProgress)
++// if(pMgntInfo->bScanInProgress)
++// {
++// RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SetBWMode8192C() %s Exit because bScanInProgress!\n",
++// Bandwidth == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz"));
++// return;
++// }
++
++// if(pHalData->SetBWModeInProgress)
++// {
++// // Modified it for 20/40 mhz switch by guangan 070531
++// RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SetBWMode8192C() %s cancel last timer because SetBWModeInProgress!\n",
++// Bandwidth == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz"));
++// PlatformCancelTimer(Adapter, &pHalData->SetBWModeTimer);
++// //return;
++// }
++
++ //if(pHalData->SetBWModeInProgress)
++ // return;
++
++ //pHalData->SetBWModeInProgress= TRUE;
++
++ pHalData->CurrentChannelBW = Bandwidth;
++
++#if 0
++ if(Offset==HT_EXTCHNL_OFFSET_LOWER)
++ pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
++ else if(Offset==HT_EXTCHNL_OFFSET_UPPER)
++ pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
++ else
++ pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++#else
++ pHalData->nCur40MhzPrimeSC = Offset;
++#endif
++
++ if((!Adapter->bDriverStopped) && (!Adapter->bSurpriseRemoved))
++ {
++#ifdef USE_WORKITEM
++ //PlatformScheduleWorkItem(&(pHalData->SetBWModeWorkItem));
++#else
++ #if 0
++ //PlatformSetTimer(Adapter, &(pHalData->SetBWModeTimer), 0);
++ #else
++ _PHY_SetBWMode92C(Adapter);
++ #endif
++#endif
++ }
++ else
++ {
++ //RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SetBWMode8192C() SetBWModeInProgress FALSE driver sleep or unload\n"));
++ //pHalData->SetBWModeInProgress= FALSE;
++ pHalData->CurrentChannelBW = tmpBW;
++ }
++
++}
++
++
++static void _PHY_SwChnl8192C(PADAPTER Adapter, u8 channel)
++{
++ u8 eRFPath;
++ u32 param1, param2;
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++
++ if ( Adapter->bNotifyChannelChange )
++ {
++ DBG_871X( "[%s] ch = %d\n", __FUNCTION__, channel );
++ }
++
++ //s1. pre common command - CmdID_SetTxPowerLevel
++ PHY_SetTxPowerLevel8192C(Adapter, channel);
++
++ //s2. RF dependent command - CmdID_RF_WriteReg, param1=RF_CHNLBW, param2=channel
++ param1 = RF_CHNLBW;
++ param2 = channel;
++ for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
++ {
++ pHalData->RfRegChnlVal[eRFPath] = ((pHalData->RfRegChnlVal[eRFPath] & 0xfffffc00) | param2);
++ PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)eRFPath, param1, bRFRegOffsetMask, pHalData->RfRegChnlVal[eRFPath]);
++ }
++
++
++ //s3. post common command - CmdID_End, None
++
++}
++
++VOID
++PHY_SwChnl8192C( // Call after initialization
++ IN PADAPTER Adapter,
++ IN u8 channel
++ )
++{
++ //PADAPTER Adapter = ADJUST_TO_ADAPTIVE_ADAPTER(pAdapter, _TRUE);
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ u8 tmpchannel = pHalData->CurrentChannel;
++ BOOLEAN bResult = _TRUE;
++
++ if(pHalData->rf_chip == RF_PSEUDO_11N)
++ {
++ //pHalData->SwChnlInProgress=FALSE;
++ return; //return immediately if it is peudo-phy
++ }
++
++ //if(pHalData->SwChnlInProgress)
++ // return;
++
++ //if(pHalData->SetBWModeInProgress)
++ // return;
++
++ //--------------------------------------------
++ switch(pHalData->CurrentWirelessMode)
++ {
++ case WIRELESS_MODE_A:
++ case WIRELESS_MODE_N_5G:
++ //RT_ASSERT((channel>14), ("WIRELESS_MODE_A but channel<=14"));
++ break;
++
++ case WIRELESS_MODE_B:
++ //RT_ASSERT((channel<=14), ("WIRELESS_MODE_B but channel>14"));
++ break;
++
++ case WIRELESS_MODE_G:
++ case WIRELESS_MODE_N_24G:
++ //RT_ASSERT((channel<=14), ("WIRELESS_MODE_G but channel>14"));
++ break;
++
++ default:
++ //RT_ASSERT(FALSE, ("Invalid WirelessMode(%#x)!!\n", pHalData->CurrentWirelessMode));
++ break;
++ }
++ //--------------------------------------------
++
++ //pHalData->SwChnlInProgress = TRUE;
++ if(channel == 0)
++ channel = 1;
++
++ pHalData->CurrentChannel=channel;
++
++ //pHalData->SwChnlStage=0;
++ //pHalData->SwChnlStep=0;
++
++ if((!Adapter->bDriverStopped) && (!Adapter->bSurpriseRemoved))
++ {
++#ifdef USE_WORKITEM
++ //bResult = PlatformScheduleWorkItem(&(pHalData->SwChnlWorkItem));
++#else
++ #if 0
++ //PlatformSetTimer(Adapter, &(pHalData->SwChnlTimer), 0);
++ #else
++ _PHY_SwChnl8192C(Adapter, channel);
++ #endif
++#endif
++ if(bResult)
++ {
++ //RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SwChnl8192C SwChnlInProgress TRUE schdule workitem done\n"));
++ }
++ else
++ {
++ //RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SwChnl8192C SwChnlInProgress FALSE schdule workitem error\n"));
++ //if(IS_HARDWARE_TYPE_8192SU(Adapter))
++ //{
++ // pHalData->SwChnlInProgress = FALSE;
++ pHalData->CurrentChannel = tmpchannel;
++ //}
++ }
++
++ }
++ else
++ {
++ //RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SwChnl8192C SwChnlInProgress FALSE driver sleep or unload\n"));
++ //if(IS_HARDWARE_TYPE_8192SU(Adapter))
++ //{
++ // pHalData->SwChnlInProgress = FALSE;
++ pHalData->CurrentChannel = tmpchannel;
++ //}
++ }
++}
++
++
++static BOOLEAN
++phy_SwChnlStepByStep(
++ IN PADAPTER Adapter,
++ IN u8 channel,
++ IN u8 *stage,
++ IN u8 *step,
++ OUT u32 *delay
++ )
++{
++#if 0
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ PCHANNEL_ACCESS_SETTING pChnlAccessSetting;
++ SwChnlCmd PreCommonCmd[MAX_PRECMD_CNT];
++ u4Byte PreCommonCmdCnt;
++ SwChnlCmd PostCommonCmd[MAX_POSTCMD_CNT];
++ u4Byte PostCommonCmdCnt;
++ SwChnlCmd RfDependCmd[MAX_RFDEPENDCMD_CNT];
++ u4Byte RfDependCmdCnt;
++ SwChnlCmd *CurrentCmd;
++ u1Byte eRFPath;
++ u4Byte RfTXPowerCtrl;
++ BOOLEAN bAdjRfTXPowerCtrl = _FALSE;
++
++
++ RT_ASSERT((Adapter != NULL), ("Adapter should not be NULL\n"));
++#if(MP_DRIVER != 1)
++ RT_ASSERT(IsLegalChannel(Adapter, channel), ("illegal channel: %d\n", channel));
++#endif
++ RT_ASSERT((pHalData != NULL), ("pHalData should not be NULL\n"));
++
++ pChnlAccessSetting = &Adapter->MgntInfo.Info8185.ChannelAccessSetting;
++ RT_ASSERT((pChnlAccessSetting != NULL), ("pChnlAccessSetting should not be NULL\n"));
++
++ //for(eRFPath = RF_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
++ //for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
++ //{
++ // <1> Fill up pre common command.
++ PreCommonCmdCnt = 0;
++ phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
++ CmdID_SetTxPowerLevel, 0, 0, 0);
++ phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
++ CmdID_End, 0, 0, 0);
++
++ // <2> Fill up post common command.
++ PostCommonCmdCnt = 0;
++
++ phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++, MAX_POSTCMD_CNT,
++ CmdID_End, 0, 0, 0);
++
++ // <3> Fill up RF dependent command.
++ RfDependCmdCnt = 0;
++ switch( pHalData->RFChipID )
++ {
++ case RF_8225:
++ RT_ASSERT((channel >= 1 && channel <= 14), ("illegal channel for Zebra: %d\n", channel));
++ // 2008/09/04 MH Change channel.
++ if(channel==14) channel++;
++ phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
++ CmdID_RF_WriteReg, rZebra1_Channel, (0x10+channel-1), 10);
++ phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
++ CmdID_End, 0, 0, 0);
++ break;
++
++ case RF_8256:
++ // TEST!! This is not the table for 8256!!
++ RT_ASSERT((channel >= 1 && channel <= 14), ("illegal channel for Zebra: %d\n", channel));
++ phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
++ CmdID_RF_WriteReg, rRfChannel, channel, 10);
++ phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
++ CmdID_End, 0, 0, 0);
++ break;
++
++ case RF_6052:
++ RT_ASSERT((channel >= 1 && channel <= 14), ("illegal channel for Zebra: %d\n", channel));
++ phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
++ CmdID_RF_WriteReg, RF_CHNLBW, channel, 10);
++ phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
++ CmdID_End, 0, 0, 0);
++
++ break;
++
++ case RF_8258:
++ break;
++
++ // For FPGA two MAC verification
++ case RF_PSEUDO_11N:
++ return TRUE;
++ default:
++ RT_ASSERT(FALSE, ("Unknown RFChipID: %d\n", pHalData->RFChipID));
++ return FALSE;
++ break;
++ }
++
++
++ do{
++ switch(*stage)
++ {
++ case 0:
++ CurrentCmd=&PreCommonCmd[*step];
++ break;
++ case 1:
++ CurrentCmd=&RfDependCmd[*step];
++ break;
++ case 2:
++ CurrentCmd=&PostCommonCmd[*step];
++ break;
++ }
++
++ if(CurrentCmd->CmdID==CmdID_End)
++ {
++ if((*stage)==2)
++ {
++ return TRUE;
++ }
++ else
++ {
++ (*stage)++;
++ (*step)=0;
++ continue;
++ }
++ }
++
++ switch(CurrentCmd->CmdID)
++ {
++ case CmdID_SetTxPowerLevel:
++ PHY_SetTxPowerLevel8192C(Adapter,channel);
++ break;
++ case CmdID_WritePortUlong:
++ PlatformEFIOWrite4Byte(Adapter, CurrentCmd->Para1, CurrentCmd->Para2);
++ break;
++ case CmdID_WritePortUshort:
++ PlatformEFIOWrite2Byte(Adapter, CurrentCmd->Para1, (u2Byte)CurrentCmd->Para2);
++ break;
++ case CmdID_WritePortUchar:
++ PlatformEFIOWrite1Byte(Adapter, CurrentCmd->Para1, (u1Byte)CurrentCmd->Para2);
++ break;
++ case CmdID_RF_WriteReg: // Only modify channel for the register now !!!!!
++ for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
++ {
++#if 1
++ pHalData->RfRegChnlVal[eRFPath] = ((pHalData->RfRegChnlVal[eRFPath] & 0xfffffc00) | CurrentCmd->Para2);
++ PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bRFRegOffsetMask, pHalData->RfRegChnlVal[eRFPath]);
++#else
++ PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bRFRegOffsetMask, (CurrentCmd->Para2));
++#endif
++ }
++ break;
++ }
++
++ break;
++ }while(TRUE);
++ //cosa }/*for(Number of RF paths)*/
++
++ (*delay)=CurrentCmd->msDelay;
++ (*step)++;
++ return FALSE;
++#endif
++ return _TRUE;
++}
++
++
++static BOOLEAN
++phy_SetSwChnlCmdArray(
++ SwChnlCmd* CmdTable,
++ u32 CmdTableIdx,
++ u32 CmdTableSz,
++ SwChnlCmdID CmdID,
++ u32 Para1,
++ u32 Para2,
++ u32 msDelay
++ )
++{
++ SwChnlCmd* pCmd;
++
++ if(CmdTable == NULL)
++ {
++ //RT_ASSERT(FALSE, ("phy_SetSwChnlCmdArray(): CmdTable cannot be NULL.\n"));
++ return _FALSE;
++ }
++ if(CmdTableIdx >= CmdTableSz)
++ {
++ //RT_ASSERT(FALSE,
++ // ("phy_SetSwChnlCmdArray(): Access invalid index, please check size of the table, CmdTableIdx:%ld, CmdTableSz:%ld\n",
++ // CmdTableIdx, CmdTableSz));
++ return _FALSE;
++ }
++
++ pCmd = CmdTable + CmdTableIdx;
++ pCmd->CmdID = CmdID;
++ pCmd->Para1 = Para1;
++ pCmd->Para2 = Para2;
++ pCmd->msDelay = msDelay;
++
++ return _TRUE;
++}
++
++
++static void
++phy_FinishSwChnlNow( // We should not call this function directly
++ IN PADAPTER Adapter,
++ IN u8 channel
++ )
++{
++#if 0
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ u32 delay;
++
++ while(!phy_SwChnlStepByStep(Adapter,channel,&pHalData->SwChnlStage,&pHalData->SwChnlStep,&delay))
++ {
++ if(delay>0)
++ rtw_mdelay_os(delay);
++ }
++#endif
++}
++
++
++
++//
++// Description:
++// Switch channel synchronously. Called by SwChnlByDelayHandler.
++//
++// Implemented by Bruce, 2008-02-14.
++// The following procedure is operted according to SwChanlCallback8190Pci().
++// However, this procedure is performed synchronously which should be running under
++// passive level.
++//
++VOID
++PHY_SwChnlPhy8192C( // Only called during initialize
++ IN PADAPTER Adapter,
++ IN u8 channel
++ )
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++
++ //RT_TRACE(COMP_SCAN | COMP_RM, DBG_LOUD, ("==>PHY_SwChnlPhy8192S(), switch from channel %d to channel %d.\n", pHalData->CurrentChannel, channel));
++
++ // Cannot IO.
++ //if(RT_CANNOT_IO(Adapter))
++ // return;
++
++ // Channel Switching is in progress.
++ //if(pHalData->SwChnlInProgress)
++ // return;
++
++ //return immediately if it is peudo-phy
++ if(pHalData->rf_chip == RF_PSEUDO_11N)
++ {
++ //pHalData->SwChnlInProgress=FALSE;
++ return;
++ }
++
++ //pHalData->SwChnlInProgress = TRUE;
++ if( channel == 0)
++ channel = 1;
++
++ pHalData->CurrentChannel=channel;
++
++ //pHalData->SwChnlStage = 0;
++ //pHalData->SwChnlStep = 0;
++
++ phy_FinishSwChnlNow(Adapter,channel);
++
++ //pHalData->SwChnlInProgress = FALSE;
++}
++
++
++//
++// Description:
++// Configure H/W functionality to enable/disable Monitor mode.
++// Note, because we possibly need to configure BB and RF in this function,
++// so caller should in PASSIVE_LEVEL. 080118, by rcnjko.
++//
++VOID
++PHY_SetMonitorMode8192C(
++ IN PADAPTER pAdapter,
++ IN BOOLEAN bEnableMonitorMode
++ )
++{
++#if 0
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
++ BOOLEAN bFilterOutNonAssociatedBSSID = FALSE;
++
++ //2 Note: we may need to stop antenna diversity.
++ if(bEnableMonitorMode)
++ {
++ bFilterOutNonAssociatedBSSID = FALSE;
++ RT_TRACE(COMP_RM, DBG_LOUD, ("PHY_SetMonitorMode8192S(): enable monitor mode\n"));
++
++ pHalData->bInMonitorMode = TRUE;
++ pAdapter->HalFunc.AllowAllDestAddrHandler(pAdapter, TRUE, TRUE);
++ rtw_hal_set_hwreg(pAdapter, HW_VAR_CHECK_BSSID, (pu1Byte)&bFilterOutNonAssociatedBSSID);
++ }
++ else
++ {
++ bFilterOutNonAssociatedBSSID = TRUE;
++ RT_TRACE(COMP_RM, DBG_LOUD, ("PHY_SetMonitorMode8192S(): disable monitor mode\n"));
++
++ pAdapter->HalFunc.AllowAllDestAddrHandler(pAdapter, FALSE, TRUE);
++ pHalData->bInMonitorMode = FALSE;
++ rtw_hal_set_hwreg(pAdapter, HW_VAR_CHECK_BSSID, (pu1Byte)&bFilterOutNonAssociatedBSSID);
++ }
++#endif
++}
++
++
++/*-----------------------------------------------------------------------------
++ * Function: PHYCheckIsLegalRfPath8190Pci()
++ *
++ * Overview: Check different RF type to execute legal judgement. If RF Path is illegal
++ * We will return false.
++ *
++ * Input: NONE
++ *
++ * Output: NONE
++ *
++ * Return: NONE
++ *
++ * Revised History:
++ * When Who Remark
++ * 11/15/2007 MHC Create Version 0.
++ *
++ *---------------------------------------------------------------------------*/
++BOOLEAN
++PHY_CheckIsLegalRfPath8192C(
++ IN PADAPTER pAdapter,
++ IN u32 eRFPath)
++{
++// HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
++ BOOLEAN rtValue = _TRUE;
++
++ // NOt check RF Path now.!
++#if 0
++ if (pHalData->RF_Type == RF_1T2R && eRFPath != RF_PATH_A)
++ {
++ rtValue = FALSE;
++ }
++ if (pHalData->RF_Type == RF_1T2R && eRFPath != RF_PATH_A)
++ {
++
++ }
++#endif
++ return rtValue;
++
++} /* PHY_CheckIsLegalRfPath8192C */
++
++//-------------------------------------------------------------------------
++//
++// IQK
++//
++//-------------------------------------------------------------------------
++#define MAX_TOLERANCE 5
++#define IQK_DELAY_TIME 1 //ms
++
++static u8 //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK
++_PHY_PathA_IQK(
++ IN PADAPTER pAdapter,
++ IN BOOLEAN configPathB
++ )
++{
++ u32 regEAC, regE94, regE9C, regEA4;
++ u8 result = 0x00;
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
++
++ //RTPRINT(FINIT, INIT_IQK, ("Path A IQK!\n"));
++
++ //path-A IQK setting
++ //RTPRINT(FINIT, INIT_IQK, ("Path-A IQK setting!\n"));
++ PHY_SetBBReg(pAdapter, rTx_IQK_Tone_A, bMaskDWord, 0x10008c1f);
++ PHY_SetBBReg(pAdapter, rRx_IQK_Tone_A, bMaskDWord, 0x10008c1f);
++ PHY_SetBBReg(pAdapter, rTx_IQK_PI_A, bMaskDWord, 0x82140102);
++
++ PHY_SetBBReg(pAdapter, rRx_IQK_PI_A, bMaskDWord, configPathB ? 0x28160202 :
++ IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202:0x28160502);
++
++ //path-B IQK setting
++ if(configPathB)
++ {
++ PHY_SetBBReg(pAdapter, rTx_IQK_Tone_B, bMaskDWord, 0x10008c22);
++ PHY_SetBBReg(pAdapter, rRx_IQK_Tone_B, bMaskDWord, 0x10008c22);
++ PHY_SetBBReg(pAdapter, rTx_IQK_PI_B, bMaskDWord, 0x82140102);
++ PHY_SetBBReg(pAdapter, rRx_IQK_PI_B, bMaskDWord, 0x28160202);
++ }
++
++ //LO calibration setting
++ //RTPRINT(FINIT, INIT_IQK, ("LO calibration setting!\n"));
++ PHY_SetBBReg(pAdapter, rIQK_AGC_Rsp, bMaskDWord, 0x001028d1);
++
++ //One shot, path A LOK & IQK
++ //RTPRINT(FINIT, INIT_IQK, ("One shot, path A LOK & IQK!\n"));
++ PHY_SetBBReg(pAdapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
++ PHY_SetBBReg(pAdapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
++
++ // delay x ms
++ //RTPRINT(FINIT, INIT_IQK, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME));
++ rtw_udelay_os(IQK_DELAY_TIME*1000);//PlatformStallExecution(IQK_DELAY_TIME*1000);
++
++ // Check failed
++ regEAC = PHY_QueryBBReg(pAdapter, rRx_Power_After_IQK_A_2, bMaskDWord);
++ //RTPRINT(FINIT, INIT_IQK, ("0xeac = 0x%x\n", regEAC));
++ regE94 = PHY_QueryBBReg(pAdapter, rTx_Power_Before_IQK_A, bMaskDWord);
++ //RTPRINT(FINIT, INIT_IQK, ("0xe94 = 0x%x\n", regE94));
++ regE9C= PHY_QueryBBReg(pAdapter, rTx_Power_After_IQK_A, bMaskDWord);
++ //RTPRINT(FINIT, INIT_IQK, ("0xe9c = 0x%x\n", regE9C));
++ regEA4= PHY_QueryBBReg(pAdapter, rRx_Power_Before_IQK_A_2, bMaskDWord);
++ //RTPRINT(FINIT, INIT_IQK, ("0xea4 = 0x%x\n", regEA4));
++
++ if(!(regEAC & BIT28) &&
++ (((regE94 & 0x03FF0000)>>16) != 0x142) &&
++ (((regE9C & 0x03FF0000)>>16) != 0x42) )
++ result |= 0x01;
++ else //if Tx not OK, ignore Rx
++ return result;
++
++ if(!(regEAC & BIT27) && //if Tx is OK, check whether Rx is OK
++ (((regEA4 & 0x03FF0000)>>16) != 0x132) &&
++ (((regEAC & 0x03FF0000)>>16) != 0x36))
++ result |= 0x02;
++ else
++ DBG_8192C("Path A Rx IQK fail!!\n");
++
++ return result;
++
++
++}
++
++static u8 //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK
++_PHY_PathB_IQK(
++ IN PADAPTER pAdapter
++ )
++{
++ u32 regEAC, regEB4, regEBC, regEC4, regECC;
++ u8 result = 0x00;
++ //RTPRINT(FINIT, INIT_IQK, ("Path B IQK!\n"));
++
++ //One shot, path B LOK & IQK
++ //RTPRINT(FINIT, INIT_IQK, ("One shot, path A LOK & IQK!\n"));
++ PHY_SetBBReg(pAdapter, rIQK_AGC_Cont, bMaskDWord, 0x00000002);
++ PHY_SetBBReg(pAdapter, rIQK_AGC_Cont, bMaskDWord, 0x00000000);
++
++ // delay x ms
++ //RTPRINT(FINIT, INIT_IQK, ("Delay %d ms for One shot, path B LOK & IQK.\n", IQK_DELAY_TIME));
++ rtw_udelay_os(IQK_DELAY_TIME*1000);//PlatformStallExecution(IQK_DELAY_TIME*1000);
++
++ // Check failed
++ regEAC = PHY_QueryBBReg(pAdapter, rRx_Power_After_IQK_A_2, bMaskDWord);
++ //RTPRINT(FINIT, INIT_IQK, ("0xeac = 0x%x\n", regEAC));
++ regEB4 = PHY_QueryBBReg(pAdapter, rTx_Power_Before_IQK_B, bMaskDWord);
++ //RTPRINT(FINIT, INIT_IQK, ("0xeb4 = 0x%x\n", regEB4));
++ regEBC= PHY_QueryBBReg(pAdapter, rTx_Power_After_IQK_B, bMaskDWord);
++ //RTPRINT(FINIT, INIT_IQK, ("0xebc = 0x%x\n", regEBC));
++ regEC4= PHY_QueryBBReg(pAdapter, rRx_Power_Before_IQK_B_2, bMaskDWord);
++ //RTPRINT(FINIT, INIT_IQK, ("0xec4 = 0x%x\n", regEC4));
++ regECC= PHY_QueryBBReg(pAdapter, rRx_Power_After_IQK_B_2, bMaskDWord);
++ //RTPRINT(FINIT, INIT_IQK, ("0xecc = 0x%x\n", regECC));
++
++ if(!(regEAC & BIT31) &&
++ (((regEB4 & 0x03FF0000)>>16) != 0x142) &&
++ (((regEBC & 0x03FF0000)>>16) != 0x42))
++ result |= 0x01;
++ else
++ return result;
++
++ if(!(regEAC & BIT30) &&
++ (((regEC4 & 0x03FF0000)>>16) != 0x132) &&
++ (((regECC & 0x03FF0000)>>16) != 0x36))
++ result |= 0x02;
++ else
++ DBG_8192C("Path B Rx IQK fail!!\n");
++
++
++ return result;
++
++}
++
++static VOID
++_PHY_PathAFillIQKMatrix(
++ IN PADAPTER pAdapter,
++ IN BOOLEAN bIQKOK,
++ IN int result[][8],
++ IN u8 final_candidate,
++ IN BOOLEAN bTxOnly
++ )
++{
++ u32 Oldval_0, X, TX0_A, reg;
++ s32 Y, TX0_C;
++
++ DBG_8192C("Path A IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed");
++
++ if(final_candidate == 0xFF)
++ return;
++ else if(bIQKOK)
++ {
++ Oldval_0 = (PHY_QueryBBReg(pAdapter, rOFDM0_XATxIQImbalance, bMaskDWord) >> 22) & 0x3FF;
++
++ X = result[final_candidate][0];
++ if ((X & 0x00000200) != 0)
++ X = X | 0xFFFFFC00;
++ TX0_A = (X * Oldval_0) >> 8;
++ //RTPRINT(FINIT, INIT_IQK, ("X = 0x%lx, TX0_A = 0x%lx, Oldval_0 0x%lx\n", X, TX0_A, Oldval_0));
++ PHY_SetBBReg(pAdapter, rOFDM0_XATxIQImbalance, 0x3FF, TX0_A);
++ PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT(31), ((X* Oldval_0>>7) & 0x1));
++
++ Y = result[final_candidate][1];
++ if ((Y & 0x00000200) != 0)
++ Y = Y | 0xFFFFFC00;
++ TX0_C = (Y * Oldval_0) >> 8;
++ //RTPRINT(FINIT, INIT_IQK, ("Y = 0x%lx, TX = 0x%lx\n", Y, TX0_C));
++ PHY_SetBBReg(pAdapter, rOFDM0_XCTxAFE, 0xF0000000, ((TX0_C&0x3C0)>>6));
++ PHY_SetBBReg(pAdapter, rOFDM0_XATxIQImbalance, 0x003F0000, (TX0_C&0x3F));
++ PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT(29), ((Y* Oldval_0>>7) & 0x1));
++
++ if(bTxOnly)
++ {
++ DBG_8192C("_PHY_PathAFillIQKMatrix only Tx OK\n");
++ return;
++ }
++
++ reg = result[final_candidate][2];
++ PHY_SetBBReg(pAdapter, rOFDM0_XARxIQImbalance, 0x3FF, reg);
++
++ reg = result[final_candidate][3] & 0x3F;
++ PHY_SetBBReg(pAdapter, rOFDM0_XARxIQImbalance, 0xFC00, reg);
++
++ reg = (result[final_candidate][3] >> 6) & 0xF;
++ PHY_SetBBReg(pAdapter, rOFDM0_RxIQExtAnta, 0xF0000000, reg);
++ }
++}
++
++static VOID
++_PHY_PathBFillIQKMatrix(
++ IN PADAPTER pAdapter,
++ IN BOOLEAN bIQKOK,
++ IN int result[][8],
++ IN u8 final_candidate,
++ IN BOOLEAN bTxOnly //do Tx only
++ )
++{
++ u32 Oldval_1, X, TX1_A, reg;
++ s32 Y, TX1_C;
++
++ DBG_8192C("Path B IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed");
++
++ if(final_candidate == 0xFF)
++ return;
++ else if(bIQKOK)
++ {
++ Oldval_1 = (PHY_QueryBBReg(pAdapter, rOFDM0_XBTxIQImbalance, bMaskDWord) >> 22) & 0x3FF;
++
++ X = result[final_candidate][4];
++ if ((X & 0x00000200) != 0)
++ X = X | 0xFFFFFC00;
++ TX1_A = (X * Oldval_1) >> 8;
++ //RTPRINT(FINIT, INIT_IQK, ("X = 0x%lx, TX1_A = 0x%lx\n", X, TX1_A));
++ PHY_SetBBReg(pAdapter, rOFDM0_XBTxIQImbalance, 0x3FF, TX1_A);
++ PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT(27), ((X* Oldval_1>>7) & 0x1));
++
++ Y = result[final_candidate][5];
++ if ((Y & 0x00000200) != 0)
++ Y = Y | 0xFFFFFC00;
++ TX1_C = (Y * Oldval_1) >> 8;
++ //RTPRINT(FINIT, INIT_IQK, ("Y = 0x%lx, TX1_C = 0x%lx\n", Y, TX1_C));
++ PHY_SetBBReg(pAdapter, rOFDM0_XDTxAFE, 0xF0000000, ((TX1_C&0x3C0)>>6));
++ PHY_SetBBReg(pAdapter, rOFDM0_XBTxIQImbalance, 0x003F0000, (TX1_C&0x3F));
++ PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT(25), ((Y* Oldval_1>>7) & 0x1));
++
++ if(bTxOnly)
++ return;
++
++ reg = result[final_candidate][6];
++ PHY_SetBBReg(pAdapter, rOFDM0_XBRxIQImbalance, 0x3FF, reg);
++
++ reg = result[final_candidate][7] & 0x3F;
++ PHY_SetBBReg(pAdapter, rOFDM0_XBRxIQImbalance, 0xFC00, reg);
++
++ reg = (result[final_candidate][7] >> 6) & 0xF;
++ PHY_SetBBReg(pAdapter, rOFDM0_AGCRSSITable, 0x0000F000, reg);
++ }
++}
++
++static VOID
++_PHY_SaveADDARegisters(
++ IN PADAPTER pAdapter,
++ IN u32* ADDAReg,
++ IN u32* ADDABackup,
++ IN u32 RegisterNum
++ )
++{
++ u32 i;
++
++ //RTPRINT(FINIT, INIT_IQK, ("Save ADDA parameters.\n"));
++ for( i = 0 ; i < RegisterNum ; i++){
++ ADDABackup[i] = PHY_QueryBBReg(pAdapter, ADDAReg[i], bMaskDWord);
++ }
++}
++
++static VOID
++_PHY_SaveMACRegisters(
++ IN PADAPTER pAdapter,
++ IN u32* MACReg,
++ IN u32* MACBackup
++ )
++{
++ u32 i;
++
++ //RTPRINT(FINIT, INIT_IQK, ("Save MAC parameters.\n"));
++ for( i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++){
++ MACBackup[i] =rtw_read8(pAdapter, MACReg[i]);
++ }
++ MACBackup[i] = rtw_read32(pAdapter, MACReg[i]);
++
++}
++
++static VOID
++_PHY_ReloadADDARegisters(
++ IN PADAPTER pAdapter,
++ IN u32* ADDAReg,
++ IN u32* ADDABackup,
++ IN u32 RegiesterNum
++ )
++{
++ u32 i;
++
++ //RTPRINT(FINIT, INIT_IQK, ("Reload ADDA power saving parameters !\n"));
++ for(i = 0 ; i < RegiesterNum ; i++){
++ PHY_SetBBReg(pAdapter, ADDAReg[i], bMaskDWord, ADDABackup[i]);
++ }
++}
++
++static VOID
++_PHY_ReloadMACRegisters(
++ IN PADAPTER pAdapter,
++ IN u32* MACReg,
++ IN u32* MACBackup
++ )
++{
++ u32 i;
++
++ //RTPRINT(FINIT, INIT_IQK, ("Reload MAC parameters !\n"));
++ for(i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++){
++ rtw_write8(pAdapter, MACReg[i], (u8)MACBackup[i]);
++ }
++ rtw_write32(pAdapter, MACReg[i], MACBackup[i]);
++}
++
++static VOID
++_PHY_PathADDAOn(
++ IN PADAPTER pAdapter,
++ IN u32* ADDAReg,
++ IN BOOLEAN isPathAOn,
++ IN BOOLEAN is2T
++ )
++{
++ u32 pathOn;
++ u32 i;
++
++ //RTPRINT(FINIT, INIT_IQK, ("ADDA ON.\n"));
++
++ pathOn = isPathAOn ? 0x04db25a4 : 0x0b1b25a4;
++ if(_FALSE == is2T){
++ pathOn = 0x0bdb25a0;
++ PHY_SetBBReg(pAdapter, ADDAReg[0], bMaskDWord, 0x0b1b25a0);
++ }
++ else{
++ PHY_SetBBReg(pAdapter, ADDAReg[0], bMaskDWord, pathOn);
++ }
++
++ for( i = 1 ; i < IQK_ADDA_REG_NUM ; i++){
++ PHY_SetBBReg(pAdapter, ADDAReg[i], bMaskDWord, pathOn);
++ }
++
++}
++
++static VOID
++_PHY_MACSettingCalibration(
++ IN PADAPTER pAdapter,
++ IN u32* MACReg,
++ IN u32* MACBackup
++ )
++{
++ u32 i = 0;
++
++ //RTPRINT(FINIT, INIT_IQK, ("MAC settings for Calibration.\n"));
++
++ rtw_write8(pAdapter, MACReg[i], 0x3F);
++
++ for(i = 1 ; i < (IQK_MAC_REG_NUM - 1); i++){
++ rtw_write8(pAdapter, MACReg[i], (u8)(MACBackup[i]&(~BIT3)));
++ }
++ rtw_write8(pAdapter, MACReg[i], (u8)(MACBackup[i]&(~BIT5)));
++
++}
++
++static VOID
++_PHY_PathAStandBy(
++ IN PADAPTER pAdapter
++ )
++{
++ //RTPRINT(FINIT, INIT_IQK, ("Path-A standby mode!\n"));
++
++ PHY_SetBBReg(pAdapter, rFPGA0_IQK, bMaskDWord, 0x0);
++ PHY_SetBBReg(pAdapter, 0x840, bMaskDWord, 0x00010000);
++ PHY_SetBBReg(pAdapter, rFPGA0_IQK, bMaskDWord, 0x80800000);
++}
++
++static VOID
++_PHY_PIModeSwitch(
++ IN PADAPTER pAdapter,
++ IN BOOLEAN PIMode
++ )
++{
++ u32 mode;
++
++ //RTPRINT(FINIT, INIT_IQK, ("BB Switch to %s mode!\n", (PIMode ? "PI" : "SI")));
++
++ mode = PIMode ? 0x01000100 : 0x01000000;
++ PHY_SetBBReg(pAdapter, 0x820, bMaskDWord, mode);
++ PHY_SetBBReg(pAdapter, 0x828, bMaskDWord, mode);
++}
++
++/*
++return _FALSE => do IQK again
++*/
++static BOOLEAN
++_PHY_SimularityCompare(
++ IN PADAPTER pAdapter,
++ IN int result[][8],
++ IN u8 c1,
++ IN u8 c2
++ )
++{
++ u32 i, j, diff, SimularityBitMap, bound = 0;
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
++ u8 final_candidate[2] = {0xFF, 0xFF}; //for path A and path B
++ BOOLEAN bResult = _TRUE, is2T = IS_92C_SERIAL( pHalData->VersionID);
++
++ if(is2T)
++ bound = 8;
++ else
++ bound = 4;
++
++ SimularityBitMap = 0;
++
++ for( i = 0; i < bound; i++ )
++ {
++ diff = (result[c1][i] > result[c2][i]) ? (result[c1][i] - result[c2][i]) : (result[c2][i] - result[c1][i]);
++ if (diff > MAX_TOLERANCE)
++ {
++ if((i == 2 || i == 6) && !SimularityBitMap)
++ {
++ if(result[c1][i]+result[c1][i+1] == 0)
++ final_candidate[(i/4)] = c2;
++ else if (result[c2][i]+result[c2][i+1] == 0)
++ final_candidate[(i/4)] = c1;
++ else
++ SimularityBitMap = SimularityBitMap|(1<<i);
++ }
++ else
++ SimularityBitMap = SimularityBitMap|(1<<i);
++ }
++ }
++
++ if ( SimularityBitMap == 0)
++ {
++ for( i = 0; i < (bound/4); i++ )
++ {
++ if(final_candidate[i] != 0xFF)
++ {
++ for( j = i*4; j < (i+1)*4-2; j++)
++ result[3][j] = result[final_candidate[i]][j];
++ bResult = _FALSE;
++ }
++ }
++ return bResult;
++ }
++ else if (!(SimularityBitMap & 0x0F)) //path A OK
++ {
++ for(i = 0; i < 4; i++)
++ result[3][i] = result[c1][i];
++ return _FALSE;
++ }
++ else if (!(SimularityBitMap & 0xF0) && is2T) //path B OK
++ {
++ for(i = 4; i < 8; i++)
++ result[3][i] = result[c1][i];
++ return _FALSE;
++ }
++ else
++ return _FALSE;
++
++}
++
++static VOID
++_PHY_IQCalibrate(
++ IN PADAPTER pAdapter,
++ IN int result[][8],
++ IN u8 t,
++ IN BOOLEAN is2T
++ )
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
++ struct dm_priv *pdmpriv = &pHalData->dmpriv;
++ u32 i;
++ u8 PathAOK, PathBOK;
++ u32 ADDA_REG[IQK_ADDA_REG_NUM] = {
++ rFPGA0_XCD_SwitchControl, rBlue_Tooth,
++ rRx_Wait_CCA, rTx_CCK_RFON,
++ rTx_CCK_BBON, rTx_OFDM_RFON,
++ rTx_OFDM_BBON, rTx_To_Rx,
++ rTx_To_Tx, rRx_CCK,
++ rRx_OFDM, rRx_Wait_RIFS,
++ rRx_TO_Rx, rStandby,
++ rSleep, rPMPD_ANAEN };
++
++ u32 IQK_MAC_REG[IQK_MAC_REG_NUM] = {
++ REG_TXPAUSE, REG_BCN_CTRL,
++ REG_BCN_CTRL_1, REG_GPIO_MUXCFG};
++
++ u32 IQK_BB_REG_92C[IQK_BB_REG_NUM] = {
++ rOFDM0_TRxPathEnable, rOFDM0_TRMuxPar,
++ rFPGA0_XCD_RFInterfaceSW, rConfig_AntA, rConfig_AntB,
++ rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE,
++ rFPGA0_XB_RFInterfaceOE, rFPGA0_RFMOD
++ };
++
++#if MP_DRIVER
++ const u32 retryCount = 9;
++#else
++ const u32 retryCount = 2;
++#endif
++
++ // Note: IQ calibration must be performed after loading
++ // PHY_REG.txt , and radio_a, radio_b.txt
++
++ u32 bbvalue;
++
++ if(t==0)
++ {
++ bbvalue = PHY_QueryBBReg(pAdapter, rFPGA0_RFMOD, bMaskDWord);
++ //RTPRINT(FINIT, INIT_IQK, ("PHY_IQCalibrate()==>0x%08lx\n",bbvalue));
++
++ //RTPRINT(FINIT, INIT_IQK, ("IQ Calibration for %s\n", (is2T ? "2T2R" : "1T1R")));
++
++ // Save ADDA parameters, turn Path A ADDA on
++ _PHY_SaveADDARegisters(pAdapter, ADDA_REG, pdmpriv->ADDA_backup,IQK_ADDA_REG_NUM);
++ _PHY_SaveMACRegisters(pAdapter, IQK_MAC_REG, pdmpriv->IQK_MAC_backup);
++ _PHY_SaveADDARegisters(pAdapter, IQK_BB_REG_92C, pdmpriv->IQK_BB_backup, IQK_BB_REG_NUM);
++ }
++ _PHY_PathADDAOn(pAdapter, ADDA_REG, _TRUE, is2T);
++
++ if(t==0)
++ {
++ pdmpriv->bRfPiEnable = (u8)PHY_QueryBBReg(pAdapter, rFPGA0_XA_HSSIParameter1, BIT(8));
++ }
++
++ if(!pdmpriv->bRfPiEnable){
++ // Switch BB to PI mode to do IQ Calibration.
++ _PHY_PIModeSwitch(pAdapter, _TRUE);
++ }
++
++ PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, BIT24, 0x00);
++ PHY_SetBBReg(pAdapter, rOFDM0_TRxPathEnable, bMaskDWord, 0x03a05600);
++ PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, bMaskDWord, 0x000800e4);
++ PHY_SetBBReg(pAdapter, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22204000);
++ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0x01);
++ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0x01);
++ PHY_SetBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, BIT10, 0x00);
++ PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0x00);
++
++ if(is2T)
++ {
++ PHY_SetBBReg(pAdapter, rFPGA0_XA_LSSIParameter, bMaskDWord, 0x00010000);
++ PHY_SetBBReg(pAdapter, rFPGA0_XB_LSSIParameter, bMaskDWord, 0x00010000);
++ }
++
++ //MAC settings
++ _PHY_MACSettingCalibration(pAdapter, IQK_MAC_REG, pdmpriv->IQK_MAC_backup);
++
++ //Page B init
++ PHY_SetBBReg(pAdapter, rConfig_AntA, bMaskDWord, 0x00080000);
++
++ if(is2T)
++ {
++ PHY_SetBBReg(pAdapter, rConfig_AntB, bMaskDWord, 0x00080000);
++ }
++
++ // IQ calibration setting
++ //RTPRINT(FINIT, INIT_IQK, ("IQK setting!\n"));
++ PHY_SetBBReg(pAdapter, rFPGA0_IQK, bMaskDWord, 0x80800000);
++ PHY_SetBBReg(pAdapter, rTx_IQK, bMaskDWord, 0x01007c00);
++ PHY_SetBBReg(pAdapter, rRx_IQK, bMaskDWord, 0x01004800);
++
++ for(i = 0 ; i < retryCount ; i++){
++ PathAOK = _PHY_PathA_IQK(pAdapter, is2T);
++ if(PathAOK == 0x03){
++ DBG_8192C("Path A IQK Success!!\n");
++ result[t][0] = (PHY_QueryBBReg(pAdapter, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16;
++ result[t][1] = (PHY_QueryBBReg(pAdapter, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16;
++ result[t][2] = (PHY_QueryBBReg(pAdapter, rRx_Power_Before_IQK_A_2, bMaskDWord)&0x3FF0000)>>16;
++ result[t][3] = (PHY_QueryBBReg(pAdapter, rRx_Power_After_IQK_A_2, bMaskDWord)&0x3FF0000)>>16;
++ break;
++ }
++ else if (i == (retryCount-1) && PathAOK == 0x01) //Tx IQK OK
++ {
++ DBG_8192C("Path A IQK Only Tx Success!!\n");
++
++ result[t][0] = (PHY_QueryBBReg(pAdapter, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16;
++ result[t][1] = (PHY_QueryBBReg(pAdapter, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16;
++ }
++ }
++
++ if(0x00 == PathAOK){
++ DBG_8192C("Path A IQK failed!!\n");
++ }
++
++ if(is2T){
++ _PHY_PathAStandBy(pAdapter);
++
++ // Turn Path B ADDA on
++ _PHY_PathADDAOn(pAdapter, ADDA_REG, _FALSE, is2T);
++
++ for(i = 0 ; i < retryCount ; i++){
++ PathBOK = _PHY_PathB_IQK(pAdapter);
++ if(PathBOK == 0x03){
++ DBG_8192C("Path B IQK Success!!\n");
++ result[t][4] = (PHY_QueryBBReg(pAdapter, rTx_Power_Before_IQK_B, bMaskDWord)&0x3FF0000)>>16;
++ result[t][5] = (PHY_QueryBBReg(pAdapter, rTx_Power_After_IQK_B, bMaskDWord)&0x3FF0000)>>16;
++ result[t][6] = (PHY_QueryBBReg(pAdapter, rRx_Power_Before_IQK_B_2, bMaskDWord)&0x3FF0000)>>16;
++ result[t][7] = (PHY_QueryBBReg(pAdapter, rRx_Power_After_IQK_B_2, bMaskDWord)&0x3FF0000)>>16;
++ break;
++ }
++ else if (i == (retryCount - 1) && PathBOK == 0x01) //Tx IQK OK
++ {
++ DBG_8192C("Path B Only Tx IQK Success!!\n");
++ result[t][4] = (PHY_QueryBBReg(pAdapter, rTx_Power_Before_IQK_B, bMaskDWord)&0x3FF0000)>>16;
++ result[t][5] = (PHY_QueryBBReg(pAdapter, rTx_Power_After_IQK_B, bMaskDWord)&0x3FF0000)>>16;
++ }
++ }
++
++ if(0x00 == PathBOK){
++ DBG_8192C("Path B IQK failed!!\n");
++ }
++ }
++
++ //Back to BB mode, load original value
++ //RTPRINT(FINIT, INIT_IQK, ("IQK:Back to BB mode, load original value!\n"));
++ PHY_SetBBReg(pAdapter, rFPGA0_IQK, bMaskDWord, 0);
++
++ if(t!=0)
++ {
++ if(!pdmpriv->bRfPiEnable){
++ // Switch back BB to SI mode after finish IQ Calibration.
++ _PHY_PIModeSwitch(pAdapter, _FALSE);
++ }
++
++ // Reload ADDA power saving parameters
++ _PHY_ReloadADDARegisters(pAdapter, ADDA_REG, pdmpriv->ADDA_backup, IQK_ADDA_REG_NUM);
++
++ // Reload MAC parameters
++ _PHY_ReloadMACRegisters(pAdapter, IQK_MAC_REG, pdmpriv->IQK_MAC_backup);
++
++ // Reload BB parameters
++ _PHY_ReloadADDARegisters(pAdapter, IQK_BB_REG_92C, pdmpriv->IQK_BB_backup, IQK_BB_REG_NUM);
++
++ // Restore RX initial gain
++ PHY_SetBBReg(pAdapter, rFPGA0_XA_LSSIParameter, bMaskDWord, 0x00032ed3);
++ if(is2T){
++ PHY_SetBBReg(pAdapter, rFPGA0_XB_LSSIParameter, bMaskDWord, 0x00032ed3);
++ }
++
++ //load 0xe30 IQC default value
++ PHY_SetBBReg(pAdapter, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00);
++ PHY_SetBBReg(pAdapter, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00);
++
++ }
++ //RTPRINT(FINIT, INIT_IQK, ("_PHY_IQCalibrate() <==\n"));
++
++}
++
++
++static VOID
++_PHY_LCCalibrate(
++ IN PADAPTER pAdapter,
++ IN BOOLEAN is2T
++ )
++{
++ u8 tmpReg;
++ u32 RF_Amode = 0, RF_Bmode = 0, LC_Cal;
++
++ //Check continuous TX and Packet TX
++ tmpReg = rtw_read8(pAdapter, 0xd03);
++
++ if((tmpReg&0x70) != 0) //Deal with contisuous TX case
++ rtw_write8(pAdapter, 0xd03, tmpReg&0x8F); //disable all continuous TX
++ else // Deal with Packet TX case
++ rtw_write8(pAdapter, REG_TXPAUSE, 0xFF); // block all queues
++
++ if((tmpReg&0x70) != 0)
++ {
++ //1. Read original RF mode
++ //Path-A
++ RF_Amode = PHY_QueryRFReg(pAdapter, RF_PATH_A, RF_AC, bMask12Bits);
++
++ //Path-B
++ if(is2T)
++ RF_Bmode = PHY_QueryRFReg(pAdapter, RF_PATH_B, RF_AC, bMask12Bits);
++
++ //2. Set RF mode = standby mode
++ //Path-A
++ PHY_SetRFReg(pAdapter, RF_PATH_A, RF_AC, bMask12Bits, (RF_Amode&0x8FFFF)|0x10000);
++
++ //Path-B
++ if(is2T)
++ PHY_SetRFReg(pAdapter, RF_PATH_B, RF_AC, bMask12Bits, (RF_Bmode&0x8FFFF)|0x10000);
++ }
++
++ //3. Read RF reg18
++ LC_Cal = PHY_QueryRFReg(pAdapter, RF_PATH_A, RF_CHNLBW, bMask12Bits);
++
++ //4. Set LC calibration begin
++ PHY_SetRFReg(pAdapter, RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal|0x08000);
++
++ #ifdef CONFIG_LONG_DELAY_ISSUE
++ rtw_msleep_os(100);
++ #else
++ rtw_mdelay_os(100);
++ #endif
++
++ //Restore original situation
++ if((tmpReg&0x70) != 0) //Deal with contisuous TX case
++ {
++ //Path-A
++ rtw_write8(pAdapter, 0xd03, tmpReg);
++ PHY_SetRFReg(pAdapter, RF_PATH_A, RF_AC, bMask12Bits, RF_Amode);
++
++ //Path-B
++ if(is2T)
++ PHY_SetRFReg(pAdapter, RF_PATH_B, RF_AC, bMask12Bits, RF_Bmode);
++ }
++ else // Deal with Packet TX case
++ {
++ rtw_write8(pAdapter, REG_TXPAUSE, 0x00);
++ }
++
++}
++
++
++//Analog Pre-distortion calibration
++#define APK_BB_REG_NUM 8
++#define APK_CURVE_REG_NUM 4
++#define PATH_NUM 2
++
++static VOID
++_PHY_APCalibrate(
++ IN PADAPTER pAdapter,
++ IN char delta,
++ IN BOOLEAN is2T
++ )
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
++ struct dm_priv *pdmpriv = &pHalData->dmpriv;
++
++ u32 regD[PATH_NUM];
++ u32 tmpReg, index, offset, i, apkbound;
++ u8 path, pathbound = PATH_NUM;
++ u32 BB_backup[APK_BB_REG_NUM];
++ u32 BB_REG[APK_BB_REG_NUM] = {
++ rFPGA1_TxBlock, rOFDM0_TRxPathEnable,
++ rFPGA0_RFMOD, rOFDM0_TRMuxPar,
++ rFPGA0_XCD_RFInterfaceSW, rFPGA0_XAB_RFInterfaceSW,
++ rFPGA0_XA_RFInterfaceOE, rFPGA0_XB_RFInterfaceOE };
++ u32 BB_AP_MODE[APK_BB_REG_NUM] = {
++ 0x00000020, 0x00a05430, 0x02040000,
++ 0x000800e4, 0x00204000 };
++ u32 BB_normal_AP_MODE[APK_BB_REG_NUM] = {
++ 0x00000020, 0x00a05430, 0x02040000,
++ 0x000800e4, 0x22204000 };
++
++ u32 AFE_backup[IQK_ADDA_REG_NUM];
++ u32 AFE_REG[IQK_ADDA_REG_NUM] = {
++ rFPGA0_XCD_SwitchControl, rBlue_Tooth,
++ rRx_Wait_CCA, rTx_CCK_RFON,
++ rTx_CCK_BBON, rTx_OFDM_RFON,
++ rTx_OFDM_BBON, rTx_To_Rx,
++ rTx_To_Tx, rRx_CCK,
++ rRx_OFDM, rRx_Wait_RIFS,
++ rRx_TO_Rx, rStandby,
++ rSleep, rPMPD_ANAEN };
++
++ u32 MAC_backup[IQK_MAC_REG_NUM];
++ u32 MAC_REG[IQK_MAC_REG_NUM] = {
++ REG_TXPAUSE, REG_BCN_CTRL,
++ REG_BCN_CTRL_1, REG_GPIO_MUXCFG};
++
++ u32 APK_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = {
++ {0x0852c, 0x1852c, 0x5852c, 0x1852c, 0x5852c},
++ {0x2852e, 0x0852e, 0x3852e, 0x0852e, 0x0852e}
++ };
++
++ u32 APK_normal_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = {
++ {0x0852c, 0x0a52c, 0x3a52c, 0x5a52c, 0x5a52c}, //path settings equal to path b settings
++ {0x0852c, 0x0a52c, 0x5a52c, 0x5a52c, 0x5a52c}
++ };
++
++ u32 APK_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = {
++ {0x52019, 0x52014, 0x52013, 0x5200f, 0x5208d},
++ {0x5201a, 0x52019, 0x52016, 0x52033, 0x52050}
++ };
++
++ u32 APK_normal_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = {
++ {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}, //path settings equal to path b settings
++ {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}
++ };
++#if 0
++ u32 APK_RF_value_A[PATH_NUM][APK_BB_REG_NUM] = {
++ {0x1adb0, 0x1adb0, 0x1ada0, 0x1ad90, 0x1ad80},
++ {0x00fb0, 0x00fb0, 0x00fa0, 0x00f90, 0x00f80}
++ };
++#endif
++ u32 AFE_on_off[PATH_NUM] = {
++ 0x04db25a4, 0x0b1b25a4}; //path A on path B off / path A off path B on
++
++ u32 APK_offset[PATH_NUM] = {
++ rConfig_AntA, rConfig_AntB};
++
++ u32 APK_normal_offset[PATH_NUM] = {
++ rConfig_Pmpd_AntA, rConfig_Pmpd_AntB};
++
++ u32 APK_value[PATH_NUM] = {
++ 0x92fc0000, 0x12fc0000};
++
++ u32 APK_normal_value[PATH_NUM] = {
++ 0x92680000, 0x12680000};
++
++ char APK_delta_mapping[APK_BB_REG_NUM][13] = {
++ {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},
++ {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},
++ {-6, -4, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},
++ {-1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6},
++ {-11, -9, -7, -5, -3, -1, 0, 0, 0, 0, 0, 0, 0}
++ };
++
++ u32 APK_normal_setting_value_1[13] = {
++ 0x01017018, 0xf7ed8f84, 0x1b1a1816, 0x2522201e, 0x322e2b28,
++ 0x433f3a36, 0x5b544e49, 0x7b726a62, 0xa69a8f84, 0xdfcfc0b3,
++ 0x12680000, 0x00880000, 0x00880000
++ };
++
++ u32 APK_normal_setting_value_2[16] = {
++ 0x01c7021d, 0x01670183, 0x01000123, 0x00bf00e2, 0x008d00a3,
++ 0x0068007b, 0x004d0059, 0x003a0042, 0x002b0031, 0x001f0025,
++ 0x0017001b, 0x00110014, 0x000c000f, 0x0009000b, 0x00070008,
++ 0x00050006
++ };
++
++ u32 APK_result[PATH_NUM][APK_BB_REG_NUM]; //val_1_1a, val_1_2a, val_2a, val_3a, val_4a
++ //u32 AP_curve[PATH_NUM][APK_CURVE_REG_NUM];
++
++ int BB_offset, delta_V, delta_offset;
++
++#if (MP_DRIVER == 1)
++ PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.MptCtx;
++
++ pMptCtx->APK_bound[0] = 45;
++ pMptCtx->APK_bound[1] = 52;
++#endif
++
++ //RTPRINT(FINIT, INIT_IQK, ("==>PHY_APCalibrate() delta %d\n", delta));
++
++ //RTPRINT(FINIT, INIT_IQK, ("AP Calibration for %s %s\n", (is2T ? "2T2R" : "1T1R"), (isNormal ? "Normal chip" : "Test chip")));
++
++ if(!is2T)
++ pathbound = 1;
++
++ //2 FOR NORMAL CHIP SETTINGS
++
++// Temporarily do not allow normal driver to do the following settings because these offset
++// and value will cause RF internal PA to be unpredictably disabled by HW, such that RF Tx signal
++// will disappear after disable/enable card many times on 88CU. RF SD and DD have not find the
++// root cause, so we remove these actions temporarily. Added by tynli and SD3 Allen. 2010.05.31.
++#if (MP_DRIVER != 1)
++ return;
++#endif
++
++ //settings adjust for normal chip
++ for(index = 0; index < PATH_NUM; index ++)
++ {
++ APK_offset[index] = APK_normal_offset[index];
++ APK_value[index] = APK_normal_value[index];
++ AFE_on_off[index] = 0x6fdb25a4;
++ }
++
++ for(index = 0; index < APK_BB_REG_NUM; index ++)
++ {
++ for(path = 0; path < pathbound; path++)
++ {
++ APK_RF_init_value[path][index] = APK_normal_RF_init_value[path][index];
++ APK_RF_value_0[path][index] = APK_normal_RF_value_0[path][index];
++ }
++ BB_AP_MODE[index] = BB_normal_AP_MODE[index];
++ }
++
++ apkbound = 6;
++
++ //save BB default value
++ for(index = 0; index < APK_BB_REG_NUM ; index++)
++ {
++ if(index == 0) //skip
++ continue;
++ BB_backup[index] = PHY_QueryBBReg(pAdapter, BB_REG[index], bMaskDWord);
++ }
++
++ //save MAC default value
++ _PHY_SaveMACRegisters(pAdapter, MAC_REG, MAC_backup);
++
++ //save AFE default value
++ _PHY_SaveADDARegisters(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
++
++ for(path = 0; path < pathbound; path++)
++ {
++ if(path == RF_PATH_A)
++ {
++ //path A APK
++ //load APK setting
++ //path-A
++ offset = rPdp_AntA;
++ for(index = 0; index < 11; index ++)
++ {
++ PHY_SetBBReg(pAdapter, offset, bMaskDWord, APK_normal_setting_value_1[index]);
++ //RTPRINT(FINIT, INIT_IQK, ("PHY_APCalibrate() offset 0x%x value 0x%x\n", offset, PHY_QueryBBReg(pAdapter, offset, bMaskDWord)));
++
++ offset += 0x04;
++ }
++
++ PHY_SetBBReg(pAdapter, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000);
++
++ offset = rConfig_AntA;
++ for(; index < 13; index ++)
++ {
++ PHY_SetBBReg(pAdapter, offset, bMaskDWord, APK_normal_setting_value_1[index]);
++ //RTPRINT(FINIT, INIT_IQK, ("PHY_APCalibrate() offset 0x%x value 0x%x\n", offset, PHY_QueryBBReg(pAdapter, offset, bMaskDWord)));
++
++ offset += 0x04;
++ }
++
++ //page-B1
++ PHY_SetBBReg(pAdapter, rFPGA0_IQK, bMaskDWord, 0x40000000);
++
++ //path A
++ offset = rPdp_AntA;
++ for(index = 0; index < 16; index++)
++ {
++ PHY_SetBBReg(pAdapter, offset, bMaskDWord, APK_normal_setting_value_2[index]);
++ //RTPRINT(FINIT, INIT_IQK, ("PHY_APCalibrate() offset 0x%x value 0x%x\n", offset, PHY_QueryBBReg(pAdapter, offset, bMaskDWord)));
++
++ offset += 0x04;
++ }
++ PHY_SetBBReg(pAdapter, rFPGA0_IQK, bMaskDWord, 0x00000000);
++ }
++ else if(path == RF_PATH_B)
++ {
++ //path B APK
++ //load APK setting
++ //path-B
++ offset = rPdp_AntB;
++ for(index = 0; index < 10; index ++)
++ {
++ PHY_SetBBReg(pAdapter, offset, bMaskDWord, APK_normal_setting_value_1[index]);
++ //RTPRINT(FINIT, INIT_IQK, ("PHY_APCalibrate() offset 0x%x value 0x%x\n", offset, PHY_QueryBBReg(pAdapter, offset, bMaskDWord)));
++
++ offset += 0x04;
++ }
++ PHY_SetBBReg(pAdapter, rConfig_Pmpd_AntA, bMaskDWord, 0x12680000);
++
++ PHY_SetBBReg(pAdapter, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000);
++
++ offset = rConfig_AntA;
++ index = 11;
++ for(; index < 13; index ++) //offset 0xb68, 0xb6c
++ {
++ PHY_SetBBReg(pAdapter, offset, bMaskDWord, APK_normal_setting_value_1[index]);
++ //RTPRINT(FINIT, INIT_IQK, ("PHY_APCalibrate() offset 0x%x value 0x%x\n", offset, PHY_QueryBBReg(pAdapter, offset, bMaskDWord)));
++
++ offset += 0x04;
++ }
++
++ //page-B1
++ PHY_SetBBReg(pAdapter, rFPGA0_IQK, bMaskDWord, 0x40000000);
++
++ //path B
++ offset = 0xb60;
++ for(index = 0; index < 16; index++)
++ {
++ PHY_SetBBReg(pAdapter, offset, bMaskDWord, APK_normal_setting_value_2[index]);
++ //RTPRINT(FINIT, INIT_IQK, ("PHY_APCalibrate() offset 0x%x value 0x%x\n", offset, PHY_QueryBBReg(pAdapter, offset, bMaskDWord)));
++
++ offset += 0x04;
++ }
++ PHY_SetBBReg(pAdapter, rFPGA0_IQK, bMaskDWord, 0x00000000);
++ }
++
++ //save RF default value
++ regD[path] = PHY_QueryRFReg(pAdapter, (RF_RADIO_PATH_E)path, RF_TXBIAS_A, bRFRegOffsetMask);
++
++ //Path A AFE all on, path B AFE All off or vise versa
++ for(index = 0; index < IQK_ADDA_REG_NUM ; index++)
++ PHY_SetBBReg(pAdapter, AFE_REG[index], bMaskDWord, AFE_on_off[path]);
++ //RTPRINT(FINIT, INIT_IQK, ("PHY_APCalibrate() offset 0xe70 %x\n", PHY_QueryBBReg(pAdapter, 0xe70, bMaskDWord)));
++
++ //BB to AP mode
++ if(path == 0)
++ {
++ for(index = 0; index < APK_BB_REG_NUM ; index++)
++ {
++ if(index == 0) //skip
++ continue;
++ else if (index < 5)
++ PHY_SetBBReg(pAdapter, BB_REG[index], bMaskDWord, BB_AP_MODE[index]);
++ else if (BB_REG[index] == 0x870)
++ PHY_SetBBReg(pAdapter, BB_REG[index], bMaskDWord, BB_backup[index]|BIT10|BIT26);
++ else
++ PHY_SetBBReg(pAdapter, BB_REG[index], BIT10, 0x0);
++ }
++ PHY_SetBBReg(pAdapter, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00);
++ PHY_SetBBReg(pAdapter, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00);
++ }
++ else //path B
++ {
++ PHY_SetBBReg(pAdapter, rTx_IQK_Tone_B, bMaskDWord, 0x01008c00);
++ PHY_SetBBReg(pAdapter, rRx_IQK_Tone_B, bMaskDWord, 0x01008c00);
++ }
++
++ //RTPRINT(FINIT, INIT_IQK, ("PHY_APCalibrate() offset 0x800 %x\n", PHY_QueryBBReg(pAdapter, 0x800, bMaskDWord)));
++
++ //MAC settings
++ _PHY_MACSettingCalibration(pAdapter, MAC_REG, MAC_backup);
++
++ if(path == RF_PATH_A) //Path B to standby mode
++ {
++ PHY_SetRFReg(pAdapter, RF_PATH_B, RF_AC, bRFRegOffsetMask, 0x10000);
++ }
++ else //Path A to standby mode
++ {
++ PHY_SetRFReg(pAdapter, RF_PATH_A, RF_AC, bRFRegOffsetMask, 0x10000);
++ PHY_SetRFReg(pAdapter, RF_PATH_A, RF_MODE1, bRFRegOffsetMask, 0x1000f);
++ PHY_SetRFReg(pAdapter, RF_PATH_A, RF_MODE2, bRFRegOffsetMask, 0x20103);
++ }
++
++ delta_offset = ((delta+14)/2);
++ if(delta_offset < 0)
++ delta_offset = 0;
++ else if (delta_offset > 12)
++ delta_offset = 12;
++
++ //AP calibration
++ for(index = 0; index < APK_BB_REG_NUM; index++)
++ {
++ if(index != 1) //only DO PA11+PAD01001, AP RF setting
++ continue;
++
++ tmpReg = APK_RF_init_value[path][index];
++#if 1
++ if(!pdmpriv->bAPKThermalMeterIgnore)
++ {
++ BB_offset = (tmpReg & 0xF0000) >> 16;
++
++ if(!(tmpReg & BIT15)) //sign bit 0
++ {
++ BB_offset = -BB_offset;
++ }
++
++ delta_V = APK_delta_mapping[index][delta_offset];
++
++ BB_offset += delta_V;
++
++ //RTPRINT(FINIT, INIT_IQK, ("PHY_APCalibrate() APK num %d delta_V %d delta_offset %d\n", index, delta_V, delta_offset));
++
++ if(BB_offset < 0)
++ {
++ tmpReg = tmpReg & (~BIT15);
++ BB_offset = -BB_offset;
++ }
++ else
++ {
++ tmpReg = tmpReg | BIT15;
++ }
++ tmpReg = (tmpReg & 0xFFF0FFFF) | (BB_offset << 16);
++ }
++#endif
++
++#ifdef CONFIG_PCI_HCI
++ if(IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID))
++ PHY_SetRFReg(pAdapter, (RF_RADIO_PATH_E)path, RF_IPA_A, bRFRegOffsetMask, 0x894ae);
++ else
++#endif
++ PHY_SetRFReg(pAdapter, (RF_RADIO_PATH_E)path, RF_IPA_A, bRFRegOffsetMask, 0x8992e);
++ //RTPRINT(FINIT, INIT_IQK, ("PHY_APCalibrate() offset 0xc %x\n", PHY_QueryRFReg(pAdapter, (RF_RADIO_PATH_E)path, 0xc, bMaskDWord)));
++ PHY_SetRFReg(pAdapter, (RF_RADIO_PATH_E)path, RF_AC, bRFRegOffsetMask, APK_RF_value_0[path][index]);
++ //RTPRINT(FINIT, INIT_IQK, ("PHY_APCalibrate() offset 0x0 %x\n", PHY_QueryRFReg(pAdapter, (RF_RADIO_PATH_E)path, 0x0, bMaskDWord)));
++ PHY_SetRFReg(pAdapter, (RF_RADIO_PATH_E)path, RF_TXBIAS_A, bRFRegOffsetMask, tmpReg);
++ //RTPRINT(FINIT, INIT_IQK, ("PHY_APCalibrate() offset 0xd %x\n", PHY_QueryRFReg(pAdapter, (RF_RADIO_PATH_E)path, 0xd, bMaskDWord)));
++
++ // PA11+PAD01111, one shot
++ i = 0;
++ do
++ {
++ PHY_SetBBReg(pAdapter, rFPGA0_IQK, bMaskDWord, 0x80000000);
++ {
++ PHY_SetBBReg(pAdapter, APK_offset[path], bMaskDWord, APK_value[0]);
++ //RTPRINT(FINIT, INIT_IQK, ("PHY_APCalibrate() offset 0x%x value 0x%x\n", APK_offset[path], PHY_QueryBBReg(pAdapter, APK_offset[path], bMaskDWord)));
++ rtw_mdelay_os(3);
++ PHY_SetBBReg(pAdapter, APK_offset[path], bMaskDWord, APK_value[1]);
++ //RTPRINT(FINIT, INIT_IQK, ("PHY_APCalibrate() offset 0x%x value 0x%x\n", APK_offset[path], PHY_QueryBBReg(pAdapter, APK_offset[path], bMaskDWord)));
++ #ifdef CONFIG_LONG_DELAY_ISSUE
++ rtw_msleep_os(20);
++ #else
++ rtw_mdelay_os(20);
++ #endif
++ }
++ PHY_SetBBReg(pAdapter, rFPGA0_IQK, bMaskDWord, 0x00000000);
++
++ if(path == RF_PATH_A)
++ tmpReg = PHY_QueryBBReg(pAdapter, rAPK, 0x03E00000);
++ else
++ tmpReg = PHY_QueryBBReg(pAdapter, rAPK, 0xF8000000);
++ //RTPRINT(FINIT, INIT_IQK, ("PHY_APCalibrate() offset 0xbd8[25:21] %x\n", tmpReg));
++
++ i++;
++ }
++ while(tmpReg > apkbound && i < 4);
++
++ APK_result[path][index] = tmpReg;
++ }
++ }
++
++ //reload MAC default value
++ _PHY_ReloadMACRegisters(pAdapter, MAC_REG, MAC_backup);
++
++ //reload BB default value
++ for(index = 0; index < APK_BB_REG_NUM ; index++)
++ {
++ if(index == 0) //skip
++ continue;
++ PHY_SetBBReg(pAdapter, BB_REG[index], bMaskDWord, BB_backup[index]);
++ }
++
++ //reload AFE default value
++ _PHY_ReloadADDARegisters(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
++
++ //reload RF path default value
++ for(path = 0; path < pathbound; path++)
++ {
++ PHY_SetRFReg(pAdapter, (RF_RADIO_PATH_E)path, RF_TXBIAS_A, bRFRegOffsetMask, regD[path]);
++ if(path == RF_PATH_B)
++ {
++ PHY_SetRFReg(pAdapter, RF_PATH_A, RF_MODE1, bRFRegOffsetMask, 0x1000f);
++ PHY_SetRFReg(pAdapter, RF_PATH_A, RF_MODE2, bRFRegOffsetMask, 0x20101);
++ }
++
++ //note no index == 0
++ if (APK_result[path][1] > 6)
++ APK_result[path][1] = 6;
++ //RTPRINT(FINIT, INIT_IQK, ("apk path %d result %d 0x%x \t", path, 1, APK_result[path][1]));
++ }
++
++ //RTPRINT(FINIT, INIT_IQK, ("\n"));
++
++
++ for(path = 0; path < pathbound; path++)
++ {
++ PHY_SetRFReg(pAdapter, (RF_RADIO_PATH_E)path, RF_BS_PA_APSET_G1_G4, bRFRegOffsetMask,
++ ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (APK_result[path][1] << 5) | APK_result[path][1]));
++ if(path == RF_PATH_A)
++ PHY_SetRFReg(pAdapter, (RF_RADIO_PATH_E)path, RF_BS_PA_APSET_G5_G8, bRFRegOffsetMask,
++ ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x00 << 5) | 0x05));
++ else
++ PHY_SetRFReg(pAdapter, (RF_RADIO_PATH_E)path, RF_BS_PA_APSET_G5_G8, bRFRegOffsetMask,
++ ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x02 << 5) | 0x05));
++ PHY_SetRFReg(pAdapter, (RF_RADIO_PATH_E)path, RF_BS_PA_APSET_G9_G11, bRFRegOffsetMask,
++ ((0x08 << 15) | (0x08 << 10) | (0x08 << 5) | 0x08));
++ }
++
++ pdmpriv->bAPKdone = _TRUE;
++
++ //RTPRINT(FINIT, INIT_IQK, ("<==PHY_APCalibrate()\n"));
++}
++
++static VOID _PHY_SetRFPathSwitch(
++ IN PADAPTER pAdapter,
++ IN BOOLEAN bMain,
++ IN BOOLEAN is2T
++ )
++{
++ u8 u1bTmp;
++
++ if(!pAdapter->hw_init_completed)
++ {
++ u1bTmp = rtw_read8(pAdapter, REG_LEDCFG2) | BIT7;
++ rtw_write8(pAdapter, REG_LEDCFG2, u1bTmp);
++ //PHY_SetBBReg(pAdapter, REG_LEDCFG0, BIT23, 0x01);
++ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT13, 0x01);
++ }
++
++ if(is2T)
++ {
++ if(bMain)
++ PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x1); //92C_Path_A
++ else
++ PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x2); //BT
++ }
++ else
++ {
++
++ if(bMain)
++ PHY_SetBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, 0x300, 0x2); //Main
++ else
++ PHY_SetBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, 0x300, 0x1); //Aux
++ }
++
++}
++
++//return value TRUE => Main; FALSE => Aux
++
++static BOOLEAN _PHY_QueryRFPathSwitch(
++ IN PADAPTER pAdapter,
++ IN BOOLEAN is2T
++ )
++{
++// if(is2T)
++// return _TRUE;
++
++ if(!pAdapter->hw_init_completed)
++ {
++ PHY_SetBBReg(pAdapter, REG_LEDCFG0, BIT23, 0x01);
++ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT13, 0x01);
++ }
++
++ if(is2T)
++ {
++ if(PHY_QueryBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6) == 0x01)
++ return _TRUE;
++ else
++ return _FALSE;
++ }
++ else
++ {
++ if(PHY_QueryBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, 0x300) == 0x02)
++ return _TRUE;
++ else
++ return _FALSE;
++ }
++}
++
++VOID
++rtl8192c_PHY_IQCalibrate(
++ IN PADAPTER pAdapter,
++ IN BOOLEAN bReCovery
++ )
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
++ struct dm_priv *pdmpriv = &pHalData->dmpriv;
++ s32 result[4][8]; //last is final result
++ u8 i, final_candidate;
++ BOOLEAN bPathAOK, bPathBOK;
++ s32 RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC, RegTmp = 0;
++ BOOLEAN is12simular, is13simular, is23simular;
++ BOOLEAN bStartContTx = _FALSE, bSingleTone = _FALSE, bCarrierSuppression = _FALSE;
++ u32 IQK_BB_REG_92C[IQK_BB_REG_NUM] = {
++ rOFDM0_XARxIQImbalance, rOFDM0_XBRxIQImbalance,
++ rOFDM0_ECCAThreshold, rOFDM0_AGCRSSITable,
++ rOFDM0_XATxIQImbalance, rOFDM0_XBTxIQImbalance,
++ rOFDM0_XCTxAFE, rOFDM0_XDTxAFE,
++ rOFDM0_RxIQExtAnta};
++
++
++#if MP_DRIVER == 1
++ bStartContTx = pAdapter->mppriv.MptCtx.bStartContTx;
++ bSingleTone = pAdapter->mppriv.MptCtx.bSingleTone;
++ bCarrierSuppression = pAdapter->mppriv.MptCtx.bCarrierSuppression;
++#endif
++
++ //ignore IQK when continuous Tx
++ if(bStartContTx || bSingleTone || bCarrierSuppression)
++ return;
++
++#if DISABLE_BB_RF
++ return;
++#endif
++
++ if(bReCovery)
++ {
++ _PHY_ReloadADDARegisters(pAdapter, IQK_BB_REG_92C, pdmpriv->IQK_BB_backup_recover, 9);
++ return;
++ }
++ DBG_8192C("IQK:Start!!!\n");
++
++ for(i = 0; i < 8; i++)
++ {
++ result[0][i] = 0;
++ result[1][i] = 0;
++ result[2][i] = 0;
++ result[3][i] = 0;
++ }
++ final_candidate = 0xff;
++ bPathAOK = _FALSE;
++ bPathBOK = _FALSE;
++ is12simular = _FALSE;
++ is23simular = _FALSE;
++ is13simular = _FALSE;
++
++ for (i=0; i<3; i++)
++ {
++ if(IS_92C_SERIAL( pHalData->VersionID)){
++ _PHY_IQCalibrate(pAdapter, result, i, _TRUE);
++ }
++ else{
++ // For 88C 1T1R
++ _PHY_IQCalibrate(pAdapter, result, i, _FALSE);
++ }
++
++ if(i == 1)
++ {
++ is12simular = _PHY_SimularityCompare(pAdapter, result, 0, 1);
++ if(is12simular)
++ {
++ final_candidate = 0;
++ break;
++ }
++ }
++
++ if(i == 2)
++ {
++ is13simular = _PHY_SimularityCompare(pAdapter, result, 0, 2);
++ if(is13simular)
++ {
++ final_candidate = 0;
++ break;
++ }
++
++ is23simular = _PHY_SimularityCompare(pAdapter, result, 1, 2);
++ if(is23simular)
++ final_candidate = 1;
++ else
++ {
++ for(i = 0; i < 8; i++)
++ RegTmp += result[3][i];
++
++ if(RegTmp != 0)
++ final_candidate = 3;
++ else
++ final_candidate = 0xFF;
++ }
++ }
++ }
++
++ for (i=0; i<4; i++)
++ {
++ RegE94 = result[i][0];
++ RegE9C = result[i][1];
++ RegEA4 = result[i][2];
++ RegEAC = result[i][3];
++ RegEB4 = result[i][4];
++ RegEBC = result[i][5];
++ RegEC4 = result[i][6];
++ RegECC = result[i][7];
++ //RTPRINT(FINIT, INIT_IQK, ("IQK: RegE94=%lx RegE9C=%lx RegEA4=%lx RegEAC=%lx RegEB4=%lx RegEBC=%lx RegEC4=%lx RegECC=%lx\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC));
++ }
++
++ if(final_candidate != 0xff)
++ {
++ pdmpriv->RegE94 = RegE94 = result[final_candidate][0];
++ pdmpriv->RegE9C = RegE9C = result[final_candidate][1];
++ RegEA4 = result[final_candidate][2];
++ RegEAC = result[final_candidate][3];
++ pdmpriv->RegEB4 = RegEB4 = result[final_candidate][4];
++ pdmpriv->RegEBC = RegEBC = result[final_candidate][5];
++ RegEC4 = result[final_candidate][6];
++ RegECC = result[final_candidate][7];
++ DBG_8192C("IQK: final_candidate is %x\n", final_candidate);
++ DBG_8192C("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC);
++ bPathAOK = bPathBOK = _TRUE;
++ }
++ else
++ {
++ RegE94 = RegEB4 = pdmpriv->RegE94 = pdmpriv->RegEB4 = 0x100; //X default value
++ RegE9C = RegEBC = pdmpriv->RegE9C = pdmpriv->RegEBC = 0x0; //Y default value
++ }
++
++ if((RegE94 != 0)/*&&(RegEA4 != 0)*/)
++ _PHY_PathAFillIQKMatrix(pAdapter, bPathAOK, result, final_candidate, (RegEA4 == 0));
++
++ if(IS_92C_SERIAL( pHalData->VersionID)){
++ if((RegEB4 != 0)/*&&(RegEC4 != 0)*/)
++ _PHY_PathBFillIQKMatrix(pAdapter, bPathBOK, result, final_candidate, (RegEC4 == 0));
++ }
++
++ _PHY_SaveADDARegisters(pAdapter, IQK_BB_REG_92C, pdmpriv->IQK_BB_backup_recover, 9);
++
++}
++
++
++VOID
++rtl8192c_PHY_LCCalibrate(
++ IN PADAPTER pAdapter
++ )
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
++ struct mlme_ext_priv *pmlmeext = &pAdapter->mlmeextpriv;
++ BOOLEAN bStartContTx = _FALSE, bSingleTone = _FALSE, bCarrierSuppression = _FALSE;
++
++#if MP_DRIVER == 1
++ bStartContTx = pAdapter->mppriv.MptCtx.bStartContTx;
++ bSingleTone = pAdapter->mppriv.MptCtx.bSingleTone;
++ bCarrierSuppression = pAdapter->mppriv.MptCtx.bCarrierSuppression;
++#endif
++
++#if DISABLE_BB_RF
++ return;
++#endif
++
++ //ignore IQK when continuous Tx
++ if(bStartContTx || bSingleTone || bCarrierSuppression)
++ return;
++
++ if(pmlmeext->sitesurvey_res.state == SCAN_PROCESS)
++ return;
++
++ if(IS_92C_SERIAL( pHalData->VersionID)){
++ _PHY_LCCalibrate(pAdapter, _TRUE);
++ }
++ else{
++ // For 88C 1T1R
++ _PHY_LCCalibrate(pAdapter, _FALSE);
++ }
++}
++
++VOID
++rtl8192c_PHY_APCalibrate(
++ IN PADAPTER pAdapter,
++ IN char delta
++ )
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
++ struct dm_priv *pdmpriv = &pHalData->dmpriv;
++
++ //default disable APK, because Tx NG issue, suggest by Jenyu, 2011.11.25
++ return;
++
++#if DISABLE_BB_RF
++ return;
++#endif
++
++ if(pdmpriv->bAPKdone)
++ return;
++
++ if(IS_92C_SERIAL( pHalData->VersionID)){
++ _PHY_APCalibrate(pAdapter, delta, _TRUE);
++ }
++ else{
++ // For 88C 1T1R
++ _PHY_APCalibrate(pAdapter, delta, _FALSE);
++ }
++}
++
++VOID rtl8192c_PHY_SetRFPathSwitch(
++ IN PADAPTER pAdapter,
++ IN BOOLEAN bMain
++ )
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
++
++#if DISABLE_BB_RF
++ return;
++#endif
++
++ if(IS_92C_SERIAL( pHalData->VersionID)){
++ _PHY_SetRFPathSwitch(pAdapter, bMain, _TRUE);
++ }
++ else{
++ // For 88C 1T1R
++ _PHY_SetRFPathSwitch(pAdapter, bMain, _FALSE);
++ }
++}
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/hal/rtl8192c/rtl8192c_rf6052.c linux-xbian-rpi/drivers/net/wireless/rtl8192cu/hal/rtl8192c/rtl8192c_rf6052.c
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/hal/rtl8192c/rtl8192c_rf6052.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/hal/rtl8192c/rtl8192c_rf6052.c 2015-07-28 01:20:58.309639981 +0200
+@@ -0,0 +1,1030 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++/******************************************************************************
++ *
++ *
++ * Module: rtl8192c_rf6052.c ( Source C File)
++ *
++ * Note: Provide RF 6052 series relative API.
++ *
++ * Function:
++ *
++ * Export:
++ *
++ * Abbrev:
++ *
++ * History:
++ * Data Who Remark
++ *
++ * 09/25/2008 MHC Create initial version.
++ * 11/05/2008 MHC Add API for tw power setting.
++ *
++ *
++******************************************************************************/
++
++#define _RTL8192C_RF6052_C_
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++#include <rtw_byteorder.h>
++
++#include <rtl8192c_hal.h>
++
++/*---------------------------Define Local Constant---------------------------*/
++// Define local structure for debug!!!!!
++typedef struct RF_Shadow_Compare_Map {
++ // Shadow register value
++ u32 Value;
++ // Compare or not flag
++ u8 Compare;
++ // Record If it had ever modified unpredicted
++ u8 ErrorOrNot;
++ // Recorver Flag
++ u8 Recorver;
++ //
++ u8 Driver_Write;
++}RF_SHADOW_T;
++/*---------------------------Define Local Constant---------------------------*/
++
++
++/*------------------------Define global variable-----------------------------*/
++/*------------------------Define global variable-----------------------------*/
++
++
++/*------------------------Define local variable------------------------------*/
++// 2008/11/20 MH For Debug only, RF
++//static RF_SHADOW_T RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG] = {0};
++static RF_SHADOW_T RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG];
++/*------------------------Define local variable------------------------------*/
++
++
++/*-----------------------------------------------------------------------------
++ * Function: RF_ChangeTxPath
++ *
++ * Overview: For RL6052, we must change some RF settign for 1T or 2T.
++ *
++ * Input: u2Byte DataRate // 0x80-8f, 0x90-9f
++ *
++ * Output: NONE
++ *
++ * Return: NONE
++ *
++ * Revised History:
++ * When Who Remark
++ * 09/25/2008 MHC Create Version 0.
++ * Firmwaer support the utility later.
++ *
++ *---------------------------------------------------------------------------*/
++void rtl8192c_RF_ChangeTxPath( IN PADAPTER Adapter,
++ IN u16 DataRate)
++{
++// We do not support gain table change inACUT now !!!! Delete later !!!
++#if 0//(RTL92SE_FPGA_VERIFY == 0)
++ static u1Byte RF_Path_Type = 2; // 1 = 1T 2= 2T
++ static u4Byte tx_gain_tbl1[6]
++ = {0x17f50, 0x11f40, 0x0cf30, 0x08720, 0x04310, 0x00100};
++ static u4Byte tx_gain_tbl2[6]
++ = {0x15ea0, 0x10e90, 0x0c680, 0x08250, 0x04040, 0x00030};
++ u1Byte i;
++
++ if (RF_Path_Type == 2 && (DataRate&0xF) <= 0x7)
++ {
++ // Set TX SYNC power G2G3 loop filter
++ PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
++ RF_TXPA_G2, bRFRegOffsetMask, 0x0f000);
++ PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
++ RF_TXPA_G3, bRFRegOffsetMask, 0xeacf1);
++
++ // Change TX AGC gain table
++ for (i = 0; i < 6; i++)
++ PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
++ RF_TX_AGC, bRFRegOffsetMask, tx_gain_tbl1[i]);
++
++ // Set PA to high value
++ PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
++ RF_TXPA_G2, bRFRegOffsetMask, 0x01e39);
++ }
++ else if (RF_Path_Type == 1 && (DataRate&0xF) >= 0x8)
++ {
++ // Set TX SYNC power G2G3 loop filter
++ PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
++ RF_TXPA_G2, bRFRegOffsetMask, 0x04440);
++ PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
++ RF_TXPA_G3, bRFRegOffsetMask, 0xea4f1);
++
++ // Change TX AGC gain table
++ for (i = 0; i < 6; i++)
++ PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
++ RF_TX_AGC, bRFRegOffsetMask, tx_gain_tbl2[i]);
++
++ // Set PA low gain
++ PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
++ RF_TXPA_G2, bRFRegOffsetMask, 0x01e19);
++ }
++#endif
++
++} /* RF_ChangeTxPath */
++
++
++/*-----------------------------------------------------------------------------
++ * Function: PHY_RF6052SetBandwidth()
++ *
++ * Overview: This function is called by SetBWModeCallback8190Pci() only
++ *
++ * Input: PADAPTER Adapter
++ * WIRELESS_BANDWIDTH_E Bandwidth //20M or 40M
++ *
++ * Output: NONE
++ *
++ * Return: NONE
++ *
++ * Note: For RF type 0222D
++ *---------------------------------------------------------------------------*/
++VOID
++rtl8192c_PHY_RF6052SetBandwidth(
++ IN PADAPTER Adapter,
++ IN HT_CHANNEL_WIDTH Bandwidth) //20M or 40M
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++
++ switch(Bandwidth)
++ {
++ case HT_CHANNEL_WIDTH_20:
++ pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff) | 0x0400);
++ PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]);
++ break;
++
++ case HT_CHANNEL_WIDTH_40:
++ pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff));
++ PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]);
++ break;
++
++ default:
++ //RT_TRACE(COMP_DBG, DBG_LOUD, ("PHY_SetRF8225Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth ));
++ break;
++ }
++
++}
++
++
++/*-----------------------------------------------------------------------------
++ * Function: PHY_RF6052SetCckTxPower
++ *
++ * Overview:
++ *
++ * Input: NONE
++ *
++ * Output: NONE
++ *
++ * Return: NONE
++ *
++ * Revised History:
++ * When Who Remark
++ * 11/05/2008 MHC Simulate 8192series..
++ *
++ *---------------------------------------------------------------------------*/
++
++VOID
++rtl8192c_PHY_RF6052SetCckTxPower(
++ IN PADAPTER Adapter,
++ IN u8* pPowerlevel)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ struct mlme_priv *pmlmepriv = &Adapter->mlmepriv;
++ struct dm_priv *pdmpriv = &pHalData->dmpriv;
++ struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
++ //PMGNT_INFO pMgntInfo=&Adapter->MgntInfo;
++ u32 TxAGC[2]={0, 0}, tmpval=0;
++ BOOLEAN TurboScanOff = _FALSE;
++ u8 idx1, idx2;
++ u8* ptr;
++
++ // 2010/10/18 MH Accorsing to SD3 eechou's suggestion, we need to disable turbo scan for RU.
++ // Otherwise, external PA will be broken if power index > 0x20.
++#ifdef CONFIG_USB_HCI
++ if (pHalData->EEPROMRegulatory != 0 || pHalData->ExternalPA)
++#else
++ if (pHalData->EEPROMRegulatory != 0)
++#endif
++ {
++ //DbgPrint("TurboScanOff=1 EEPROMRegulatory=%d ExternalPA=%d\n", pHalData->EEPROMRegulatory, pHalData->ExternalPA);
++ TurboScanOff = _TRUE;
++ }
++
++ if(pmlmeext->sitesurvey_res.state == SCAN_PROCESS)
++ {
++ TxAGC[RF_PATH_A] = 0x3f3f3f3f;
++ TxAGC[RF_PATH_B] = 0x3f3f3f3f;
++
++ TurboScanOff = _TRUE;//disable turbo scan
++
++ if(TurboScanOff)
++ {
++ for(idx1=RF_PATH_A; idx1<=RF_PATH_B; idx1++)
++ {
++ TxAGC[idx1] =
++ pPowerlevel[idx1] | (pPowerlevel[idx1]<<8) |
++ (pPowerlevel[idx1]<<16) | (pPowerlevel[idx1]<<24);
++#ifdef CONFIG_USB_HCI
++ // 2010/10/18 MH For external PA module. We need to limit power index to be less than 0x20.
++ if (TxAGC[idx1] > 0x20 && pHalData->ExternalPA)
++ TxAGC[idx1] = 0x20;
++#endif
++ }
++ }
++ }
++ else
++ {
++// 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism.
++// Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism.
++// In the future, two mechanism shall be separated from each other and maintained independantly. Thanks for Lanhsin's reminder.
++ if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1)
++ {
++ TxAGC[RF_PATH_A] = 0x10101010;
++ TxAGC[RF_PATH_B] = 0x10101010;
++ }
++ else if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2)
++ {
++ TxAGC[RF_PATH_A] = 0x00000000;
++ TxAGC[RF_PATH_B] = 0x00000000;
++ }
++ else
++ {
++ for(idx1=RF_PATH_A; idx1<=RF_PATH_B; idx1++)
++ {
++ TxAGC[idx1] =
++ pPowerlevel[idx1] | (pPowerlevel[idx1]<<8) |
++ (pPowerlevel[idx1]<<16) | (pPowerlevel[idx1]<<24);
++ }
++
++ if(pHalData->EEPROMRegulatory==0)
++ {
++ tmpval = (pHalData->MCSTxPowerLevelOriginalOffset[0][6]) +
++ (pHalData->MCSTxPowerLevelOriginalOffset[0][7]<<8);
++ TxAGC[RF_PATH_A] += tmpval;
++
++ tmpval = (pHalData->MCSTxPowerLevelOriginalOffset[0][14]) +
++ (pHalData->MCSTxPowerLevelOriginalOffset[0][15]<<24);
++ TxAGC[RF_PATH_B] += tmpval;
++ }
++ }
++ }
++
++ for(idx1=RF_PATH_A; idx1<=RF_PATH_B; idx1++)
++ {
++ ptr = (u8*)(&(TxAGC[idx1]));
++ for(idx2=0; idx2<4; idx2++)
++ {
++ if(*ptr > RF6052_MAX_TX_PWR)
++ *ptr = RF6052_MAX_TX_PWR;
++ ptr++;
++ }
++ }
++
++ // rf-A cck tx power
++ tmpval = TxAGC[RF_PATH_A]&0xff;
++ PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, tmpval);
++ //RTPRINT(FPHY, PHY_TXPWR, ("CCK PWR 1M (rf-A) = 0x%x (reg 0x%x)\n", tmpval, rTxAGC_A_CCK1_Mcs32));
++ tmpval = TxAGC[RF_PATH_A]>>8;
++ PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval);
++ //RTPRINT(FPHY, PHY_TXPWR, ("CCK PWR 2~11M (rf-A) = 0x%x (reg 0x%x)\n", tmpval, rTxAGC_B_CCK11_A_CCK2_11));
++
++ // rf-B cck tx power
++ tmpval = TxAGC[RF_PATH_B]>>24;
++ PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, tmpval);
++ //RTPRINT(FPHY, PHY_TXPWR, ("CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n", tmpval, rTxAGC_B_CCK11_A_CCK2_11));
++ tmpval = TxAGC[RF_PATH_B]&0x00ffffff;
++ PHY_SetBBReg(Adapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, tmpval);
++ //RTPRINT(FPHY, PHY_TXPWR, ("CCK PWR 1~5.5M (rf-B) = 0x%x (reg 0x%x)\n",
++ // tmpval, rTxAGC_B_CCK1_55_Mcs32));
++
++} /* PHY_RF6052SetCckTxPower */
++
++//
++// powerbase0 for OFDM rates
++// powerbase1 for HT MCS rates
++//
++static void getPowerBase(
++ IN PADAPTER Adapter,
++ IN u8* pPowerLevel,
++ IN u8 Channel,
++ IN OUT u32* OfdmBase,
++ IN OUT u32* MCSBase
++ )
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ u32 powerBase0, powerBase1;
++ u8 Legacy_pwrdiff=0;
++ s8 HT20_pwrdiff=0;
++ u8 i, powerlevel[2];
++
++ for(i=0; i<2; i++)
++ {
++ powerlevel[i] = pPowerLevel[i];
++ Legacy_pwrdiff = pHalData->TxPwrLegacyHtDiff[i][Channel-1];
++ powerBase0 = powerlevel[i] + Legacy_pwrdiff;
++
++ powerBase0 = (powerBase0<<24) | (powerBase0<<16) |(powerBase0<<8) |powerBase0;
++ *(OfdmBase+i) = powerBase0;
++ //RTPRINT(FPHY, PHY_TXPWR, (" [OFDM power base index rf(%c) = 0x%x]\n", ((i==0)?'A':'B'), *(OfdmBase+i)));
++ }
++
++ for(i=0; i<2; i++)
++ {
++ //Check HT20 to HT40 diff
++ if(pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
++ {
++ HT20_pwrdiff = pHalData->TxPwrHt20Diff[i][Channel-1];
++ powerlevel[i] += HT20_pwrdiff;
++ }
++ powerBase1 = powerlevel[i];
++ powerBase1 = (powerBase1<<24) | (powerBase1<<16) |(powerBase1<<8) |powerBase1;
++ *(MCSBase+i) = powerBase1;
++ //RTPRINT(FPHY, PHY_TXPWR, (" [MCS power base index rf(%c) = 0x%x]\n", ((i==0)?'A':'B'), *(MCSBase+i)));
++ }
++}
++
++static void getTxPowerWriteValByRegulatory(
++ IN PADAPTER Adapter,
++ IN u8 Channel,
++ IN u8 index,
++ IN u32* powerBase0,
++ IN u32* powerBase1,
++ OUT u32* pOutWriteVal
++ )
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ struct dm_priv *pdmpriv = &pHalData->dmpriv;
++ u8 i, chnlGroup, pwr_diff_limit[4];
++ u32 writeVal, customer_limit, rf;
++
++ //
++ // Index 0 & 1= legacy OFDM, 2-5=HT_MCS rate
++ //
++ for(rf=0; rf<2; rf++)
++ {
++ switch(pHalData->EEPROMRegulatory)
++ {
++ case 0: // Realtek better performance
++ // increase power diff defined by Realtek for large power
++ chnlGroup = 0;
++ //RTPRINT(FPHY, PHY_TXPWR, ("MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n",
++ // chnlGroup, index, pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)]));
++ writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] +
++ ((index<2)?powerBase0[rf]:powerBase1[rf]);
++ //RTPRINT(FPHY, PHY_TXPWR, ("RTK better performance, writeVal(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal));
++ break;
++ case 1: // Realtek regulatory
++ // increase power diff defined by Realtek for regulatory
++ {
++ if(pHalData->pwrGroupCnt == 1)
++ chnlGroup = 0;
++ if(pHalData->pwrGroupCnt >= 3)
++ {
++ if(Channel <= 3)
++ chnlGroup = 0;
++ else if(Channel >= 4 && Channel <= 9)
++ chnlGroup = 1;
++ else if(Channel > 9)
++ chnlGroup = 2;
++
++ if(pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
++ chnlGroup++;
++ else
++ chnlGroup+=4;
++ }
++ //RTPRINT(FPHY, PHY_TXPWR, ("MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n",
++ //chnlGroup, index, pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)]));
++ writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] +
++ ((index<2)?powerBase0[rf]:powerBase1[rf]);
++ //RTPRINT(FPHY, PHY_TXPWR, ("Realtek regulatory, 20MHz, writeVal(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal));
++ }
++ break;
++ case 2: // Better regulatory
++ // don't increase any power diff
++ writeVal = ((index<2)?powerBase0[rf]:powerBase1[rf]);
++ //RTPRINT(FPHY, PHY_TXPWR, ("Better regulatory, writeVal(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal));
++ break;
++ case 3: // Customer defined power diff.
++ // increase power diff defined by customer.
++ chnlGroup = 0;
++ //RTPRINT(FPHY, PHY_TXPWR, ("MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n",
++ // chnlGroup, index, pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)]));
++
++ if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_40)
++ {
++ //RTPRINT(FPHY, PHY_TXPWR, ("customer's limit, 40MHz rf(%c) = 0x%x\n",
++ // ((rf==0)?'A':'B'), pHalData->PwrGroupHT40[rf][Channel-1]));
++ }
++ else
++ {
++ //RTPRINT(FPHY, PHY_TXPWR, ("customer's limit, 20MHz rf(%c) = 0x%x\n",
++ // ((rf==0)?'A':'B'), pHalData->PwrGroupHT20[rf][Channel-1]));
++ }
++ for (i=0; i<4; i++)
++ {
++ pwr_diff_limit[i] = (u8)((pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)]&(0x7f<<(i*8)))>>(i*8));
++ if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_40)
++ {
++ if(pwr_diff_limit[i] > pHalData->PwrGroupHT40[rf][Channel-1])
++ pwr_diff_limit[i] = pHalData->PwrGroupHT40[rf][Channel-1];
++ }
++ else
++ {
++ if(pwr_diff_limit[i] > pHalData->PwrGroupHT20[rf][Channel-1])
++ pwr_diff_limit[i] = pHalData->PwrGroupHT20[rf][Channel-1];
++ }
++ }
++ customer_limit = (pwr_diff_limit[3]<<24) | (pwr_diff_limit[2]<<16) |
++ (pwr_diff_limit[1]<<8) | (pwr_diff_limit[0]);
++ //RTPRINT(FPHY, PHY_TXPWR, ("Customer's limit rf(%c) = 0x%x\n", ((rf==0)?'A':'B'), customer_limit));
++
++ writeVal = customer_limit + ((index<2)?powerBase0[rf]:powerBase1[rf]);
++ //RTPRINT(FPHY, PHY_TXPWR, ("Customer, writeVal rf(%c)= 0x%x\n", ((rf==0)?'A':'B'), writeVal));
++ break;
++ default:
++ chnlGroup = 0;
++ writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] +
++ ((index<2)?powerBase0[rf]:powerBase1[rf]);
++ //RTPRINT(FPHY, PHY_TXPWR, ("RTK better performance, writeVal rf(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal));
++ break;
++ }
++
++// 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism.
++// Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism.
++// In the future, two mechanism shall be separated from each other and maintained independantly. Thanks for Lanhsin's reminder.
++
++ if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1)
++ writeVal = 0x14141414;
++ else if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2)
++ writeVal = 0x00000000;
++
++
++ // 20100628 Joseph: High power mode for BT-Coexist mechanism.
++ // This mechanism is only applied when Driver-Highpower-Mechanism is OFF.
++ if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT1)
++ {
++ //RTPRINT(FBT, BT_TRACE, ("Tx Power (-6)\n"));
++ writeVal = writeVal - 0x06060606;
++ }
++ else if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT2)
++ {
++ //RTPRINT(FBT, BT_TRACE, ("Tx Power (-0)\n"));
++ writeVal = writeVal;
++ }
++ *(pOutWriteVal+rf) = writeVal;
++ }
++}
++
++static void writeOFDMPowerReg(
++ IN PADAPTER Adapter,
++ IN u8 index,
++ IN u32* pValue
++ )
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ u16 RegOffset_A[6] = { rTxAGC_A_Rate18_06, rTxAGC_A_Rate54_24,
++ rTxAGC_A_Mcs03_Mcs00, rTxAGC_A_Mcs07_Mcs04,
++ rTxAGC_A_Mcs11_Mcs08, rTxAGC_A_Mcs15_Mcs12};
++ u16 RegOffset_B[6] = { rTxAGC_B_Rate18_06, rTxAGC_B_Rate54_24,
++ rTxAGC_B_Mcs03_Mcs00, rTxAGC_B_Mcs07_Mcs04,
++ rTxAGC_B_Mcs11_Mcs08, rTxAGC_B_Mcs15_Mcs12};
++ u8 i, rf, pwr_val[4];
++ u32 writeVal;
++ u16 RegOffset;
++
++ for(rf=0; rf<2; rf++)
++ {
++ writeVal = pValue[rf];
++ for(i=0; i<4; i++)
++ {
++ pwr_val[i] = (u8)((writeVal & (0x7f<<(i*8)))>>(i*8));
++ if (pwr_val[i] > RF6052_MAX_TX_PWR)
++ pwr_val[i] = RF6052_MAX_TX_PWR;
++ }
++ writeVal = (pwr_val[3]<<24) | (pwr_val[2]<<16) |(pwr_val[1]<<8) |pwr_val[0];
++
++ if(rf == 0)
++ RegOffset = RegOffset_A[index];
++ else
++ RegOffset = RegOffset_B[index];
++
++ PHY_SetBBReg(Adapter, RegOffset, bMaskDWord, writeVal);
++ //RTPRINT(FPHY, PHY_TXPWR, ("Set 0x%x = %08x\n", RegOffset, writeVal));
++
++ // 201005115 Joseph: Set Tx Power diff for Tx power training mechanism.
++ if(((pHalData->rf_type == RF_2T2R) &&
++ (RegOffset == rTxAGC_A_Mcs15_Mcs12 || RegOffset == rTxAGC_B_Mcs15_Mcs12))||
++ ((pHalData->rf_type != RF_2T2R) &&
++ (RegOffset == rTxAGC_A_Mcs07_Mcs04 || RegOffset == rTxAGC_B_Mcs07_Mcs04)) )
++ {
++ writeVal = pwr_val[3];
++ if(RegOffset == rTxAGC_A_Mcs15_Mcs12 || RegOffset == rTxAGC_A_Mcs07_Mcs04)
++ RegOffset = 0xc90;
++ if(RegOffset == rTxAGC_B_Mcs15_Mcs12 || RegOffset == rTxAGC_B_Mcs07_Mcs04)
++ RegOffset = 0xc98;
++ for(i=0; i<3; i++)
++ {
++ if(i!=2)
++ writeVal = (writeVal>8)?(writeVal-8):0;
++ else
++ writeVal = (writeVal>6)?(writeVal-6):0;
++ rtw_write8(Adapter, (u32)(RegOffset+i), (u8)writeVal);
++ }
++ }
++ }
++}
++/*-----------------------------------------------------------------------------
++ * Function: PHY_RF6052SetOFDMTxPower
++ *
++ * Overview: For legacy and HY OFDM, we must read EEPROM TX power index for
++ * different channel and read original value in TX power register area from
++ * 0xe00. We increase offset and original value to be correct tx pwr.
++ *
++ * Input: NONE
++ *
++ * Output: NONE
++ *
++ * Return: NONE
++ *
++ * Revised History:
++ * When Who Remark
++ * 11/05/2008 MHC Simulate 8192 series method.
++ * 01/06/2009 MHC 1. Prevent Path B tx power overflow or underflow dure to
++ * A/B pwr difference or legacy/HT pwr diff.
++ * 2. We concern with path B legacy/HT OFDM difference.
++ * 01/22/2009 MHC Support new EPRO format from SD3.
++ *
++ *---------------------------------------------------------------------------*/
++VOID
++rtl8192c_PHY_RF6052SetOFDMTxPower(
++ IN PADAPTER Adapter,
++ IN u8* pPowerLevel,
++ IN u8 Channel)
++{
++ //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ u32 writeVal[2], powerBase0[2], powerBase1[2];
++ u8 index = 0;
++
++ getPowerBase(Adapter, pPowerLevel, Channel, &powerBase0[0], &powerBase1[0]);
++
++ for(index=0; index<6; index++)
++ {
++ getTxPowerWriteValByRegulatory(Adapter, Channel, index,
++ &powerBase0[0], &powerBase1[0], &writeVal[0]);
++
++ writeOFDMPowerReg(Adapter, index, &writeVal[0]);
++ }
++
++}
++
++
++static VOID
++phy_RF6052_Config_HardCode(
++ IN PADAPTER Adapter
++ )
++{
++
++ // Set Default Bandwidth to 20M
++ //Adapter->HalFunc .SetBWModeHandler(Adapter, HT_CHANNEL_WIDTH_20);
++
++ // TODO: Set Default Channel to channel one for RTL8225
++
++}
++
++static int
++phy_RF6052_Config_ParaFile(
++ IN PADAPTER Adapter
++ )
++{
++ u32 u4RegValue;
++ u8 eRFPath;
++ BB_REGISTER_DEFINITION_T *pPhyReg;
++
++ int rtStatus = _SUCCESS;
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ static char sz88CRadioAFile[] = RTL8188C_PHY_RADIO_A;
++ static char sz88CRadioBFile[] = RTL8188C_PHY_RADIO_B;
++#ifdef CONFIG_USB_HCI
++ static char sz88CRadioAFile_mCard[] = RTL8188C_PHY_RADIO_A_mCard;
++ static char sz88CRadioBFile_mCard[] = RTL8188C_PHY_RADIO_B_mCard;
++ static char sz88CRadioAFile_HP[] = RTL8188C_PHY_RADIO_A_HP;
++#endif
++ static char sz92CRadioAFile[] = RTL8192C_PHY_RADIO_A;
++ static char sz92CRadioBFile[] = RTL8192C_PHY_RADIO_B;
++ static char sz8723RadioAFile[] = RTL8723_PHY_RADIO_A;
++ static char sz8723RadioBFile[] = RTL8723_PHY_RADIO_B;
++ char *pszRadioAFile, *pszRadioBFile;
++
++
++ if(IS_HARDWARE_TYPE_8192C(Adapter))
++ {
++ if(IS_92C_SERIAL( pHalData->VersionID))// 88c's IPA is different from 92c's
++ {
++ pszRadioAFile = sz92CRadioAFile;
++ pszRadioBFile = sz92CRadioBFile;
++ }
++ else
++ {
++ pszRadioAFile = sz88CRadioAFile;
++ pszRadioBFile = sz88CRadioBFile;
++#ifdef CONFIG_USB_HCI
++ if( BOARD_MINICARD == pHalData->BoardType)
++ {
++ pszRadioAFile = sz88CRadioAFile_mCard;
++ pszRadioBFile = sz88CRadioBFile_mCard;
++ }
++ else if( BOARD_USB_High_PA == pHalData->BoardType)
++ {
++ pszRadioAFile = sz88CRadioAFile_HP;
++ }
++#endif
++ }
++ }
++ else if(IS_HARDWARE_TYPE_8723A(Adapter))
++ {
++ pszRadioAFile = sz8723RadioAFile;
++ pszRadioBFile = sz8723RadioBFile;
++ }
++
++ //3//-----------------------------------------------------------------
++ //3// <2> Initialize RF
++ //3//-----------------------------------------------------------------
++ //for(eRFPath = RF_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
++ for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
++ {
++
++ pPhyReg = &pHalData->PHYRegDef[eRFPath];
++
++ /*----Store original RFENV control type----*/
++ switch(eRFPath)
++ {
++ case RF_PATH_A:
++ case RF_PATH_C:
++ u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV);
++ break;
++ case RF_PATH_B :
++ case RF_PATH_D:
++ u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16);
++ break;
++ }
++
++ /*----Set RF_ENV enable----*/
++ PHY_SetBBReg(Adapter, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1);
++ rtw_udelay_os(1);//PlatformStallExecution(1);
++
++ /*----Set RF_ENV output high----*/
++ PHY_SetBBReg(Adapter, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);
++ rtw_udelay_os(1);//PlatformStallExecution(1);
++
++ /* Set bit number of Address and Data for RF register */
++ PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); // Set 1 to 4 bits for 8255
++ rtw_udelay_os(1);//PlatformStallExecution(1);
++
++ PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); // Set 0 to 12 bits for 8255
++ rtw_udelay_os(1);//PlatformStallExecution(1);
++
++ /*----Initialize RF fom connfiguration file----*/
++ switch(eRFPath)
++ {
++ case RF_PATH_A:
++#ifdef CONFIG_EMBEDDED_FWIMG
++ rtStatus= rtl8192c_PHY_ConfigRFWithHeaderFile(Adapter,(RF_RADIO_PATH_E)eRFPath);
++#else
++ rtStatus = rtl8192c_PHY_ConfigRFWithParaFile(Adapter, pszRadioAFile, (RF_RADIO_PATH_E)eRFPath);
++#endif
++ break;
++ case RF_PATH_B:
++#ifdef CONFIG_EMBEDDED_FWIMG
++ rtStatus = rtl8192c_PHY_ConfigRFWithHeaderFile(Adapter,(RF_RADIO_PATH_E)eRFPath);
++#else
++ rtStatus = rtl8192c_PHY_ConfigRFWithParaFile(Adapter, pszRadioBFile, (RF_RADIO_PATH_E)eRFPath);
++#endif
++ break;
++ case RF_PATH_C:
++ break;
++ case RF_PATH_D:
++ break;
++ }
++
++ /*----Restore RFENV control type----*/;
++ switch(eRFPath)
++ {
++ case RF_PATH_A:
++ case RF_PATH_C:
++ PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue);
++ break;
++ case RF_PATH_B :
++ case RF_PATH_D:
++ PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue);
++ break;
++ }
++
++ if(rtStatus != _SUCCESS){
++ //RT_TRACE(COMP_FPGA, DBG_LOUD, ("phy_RF6052_Config_ParaFile():Radio[%d] Fail!!", eRFPath));
++ goto phy_RF6052_Config_ParaFile_Fail;
++ }
++
++ }
++
++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("<---phy_RF6052_Config_ParaFile()\n"));
++ return rtStatus;
++
++phy_RF6052_Config_ParaFile_Fail:
++ return rtStatus;
++}
++
++
++int
++PHY_RF6052_Config8192C(
++ IN PADAPTER Adapter)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ int rtStatus = _SUCCESS;
++
++ //
++ // Initialize general global value
++ //
++ // TODO: Extend RF_PATH_C and RF_PATH_D in the future
++ if(pHalData->rf_type == RF_1T1R)
++ pHalData->NumTotalRFPath = 1;
++ else
++ pHalData->NumTotalRFPath = 2;
++
++ //
++ // Config BB and RF
++ //
++ rtStatus = phy_RF6052_Config_ParaFile(Adapter);
++#if 0
++ switch( Adapter->MgntInfo.bRegHwParaFile )
++ {
++ case 0:
++ phy_RF6052_Config_HardCode(Adapter);
++ break;
++
++ case 1:
++ rtStatus = phy_RF6052_Config_ParaFile(Adapter);
++ break;
++
++ case 2:
++ // Partial Modify.
++ phy_RF6052_Config_HardCode(Adapter);
++ phy_RF6052_Config_ParaFile(Adapter);
++ break;
++
++ default:
++ phy_RF6052_Config_HardCode(Adapter);
++ break;
++ }
++#endif
++ return rtStatus;
++
++}
++
++
++//
++// ==> RF shadow Operation API Code Section!!!
++//
++/*-----------------------------------------------------------------------------
++ * Function: PHY_RFShadowRead
++ * PHY_RFShadowWrite
++ * PHY_RFShadowCompare
++ * PHY_RFShadowRecorver
++ * PHY_RFShadowCompareAll
++ * PHY_RFShadowRecorverAll
++ * PHY_RFShadowCompareFlagSet
++ * PHY_RFShadowRecorverFlagSet
++ *
++ * Overview: When we set RF register, we must write shadow at first.
++ * When we are running, we must compare shadow abd locate error addr.
++ * Decide to recorver or not.
++ *
++ * Input: NONE
++ *
++ * Output: NONE
++ *
++ * Return: NONE
++ *
++ * Revised History:
++ * When Who Remark
++ * 11/20/2008 MHC Create Version 0.
++ *
++ *---------------------------------------------------------------------------*/
++u32
++PHY_RFShadowRead(
++ IN PADAPTER Adapter,
++ IN RF_RADIO_PATH_E eRFPath,
++ IN u32 Offset)
++{
++ return RF_Shadow[eRFPath][Offset].Value;
++
++} /* PHY_RFShadowRead */
++
++
++VOID
++PHY_RFShadowWrite(
++ IN PADAPTER Adapter,
++ IN RF_RADIO_PATH_E eRFPath,
++ IN u32 Offset,
++ IN u32 Data)
++{
++ RF_Shadow[eRFPath][Offset].Value = (Data & bRFRegOffsetMask);
++ RF_Shadow[eRFPath][Offset].Driver_Write = _TRUE;
++
++} /* PHY_RFShadowWrite */
++
++
++BOOLEAN
++PHY_RFShadowCompare(
++ IN PADAPTER Adapter,
++ IN RF_RADIO_PATH_E eRFPath,
++ IN u32 Offset)
++{
++ u32 reg;
++ // Check if we need to check the register
++ if (RF_Shadow[eRFPath][Offset].Compare == _TRUE)
++ {
++ reg = PHY_QueryRFReg(Adapter, eRFPath, Offset, bRFRegOffsetMask);
++ // Compare shadow and real rf register for 20bits!!
++ if (RF_Shadow[eRFPath][Offset].Value != reg)
++ {
++ // Locate error position.
++ RF_Shadow[eRFPath][Offset].ErrorOrNot = _TRUE;
++ //RT_TRACE(COMP_INIT, DBG_LOUD,
++ //("PHY_RFShadowCompare RF-%d Addr%02lx Err = %05lx\n",
++ //eRFPath, Offset, reg));
++ }
++ return RF_Shadow[eRFPath][Offset].ErrorOrNot ;
++ }
++ return _FALSE;
++} /* PHY_RFShadowCompare */
++
++
++VOID
++PHY_RFShadowRecorver(
++ IN PADAPTER Adapter,
++ IN RF_RADIO_PATH_E eRFPath,
++ IN u32 Offset)
++{
++ // Check if the address is error
++ if (RF_Shadow[eRFPath][Offset].ErrorOrNot == _TRUE)
++ {
++ // Check if we need to recorver the register.
++ if (RF_Shadow[eRFPath][Offset].Recorver == _TRUE)
++ {
++ PHY_SetRFReg(Adapter, eRFPath, Offset, bRFRegOffsetMask,
++ RF_Shadow[eRFPath][Offset].Value);
++ //RT_TRACE(COMP_INIT, DBG_LOUD,
++ //("PHY_RFShadowRecorver RF-%d Addr%02lx=%05lx",
++ //eRFPath, Offset, RF_Shadow[eRFPath][Offset].Value));
++ }
++ }
++
++} /* PHY_RFShadowRecorver */
++
++
++VOID
++PHY_RFShadowCompareAll(
++ IN PADAPTER Adapter)
++{
++ u32 eRFPath;
++ u32 Offset;
++
++ for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++)
++ {
++ for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++)
++ {
++ PHY_RFShadowCompare(Adapter, (RF_RADIO_PATH_E)eRFPath, Offset);
++ }
++ }
++
++} /* PHY_RFShadowCompareAll */
++
++
++VOID
++PHY_RFShadowRecorverAll(
++ IN PADAPTER Adapter)
++{
++ u32 eRFPath;
++ u32 Offset;
++
++ for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++)
++ {
++ for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++)
++ {
++ PHY_RFShadowRecorver(Adapter, (RF_RADIO_PATH_E)eRFPath, Offset);
++ }
++ }
++
++} /* PHY_RFShadowRecorverAll */
++
++
++VOID
++PHY_RFShadowCompareFlagSet(
++ IN PADAPTER Adapter,
++ IN RF_RADIO_PATH_E eRFPath,
++ IN u32 Offset,
++ IN u8 Type)
++{
++ // Set True or False!!!
++ RF_Shadow[eRFPath][Offset].Compare = Type;
++
++} /* PHY_RFShadowCompareFlagSet */
++
++
++VOID
++PHY_RFShadowRecorverFlagSet(
++ IN PADAPTER Adapter,
++ IN RF_RADIO_PATH_E eRFPath,
++ IN u32 Offset,
++ IN u8 Type)
++{
++ // Set True or False!!!
++ RF_Shadow[eRFPath][Offset].Recorver= Type;
++
++} /* PHY_RFShadowRecorverFlagSet */
++
++
++VOID
++PHY_RFShadowCompareFlagSetAll(
++ IN PADAPTER Adapter)
++{
++ u32 eRFPath;
++ u32 Offset;
++
++ for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++)
++ {
++ for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++)
++ {
++ // 2008/11/20 MH For S3S4 test, we only check reg 26/27 now!!!!
++ if (Offset != 0x26 && Offset != 0x27)
++ PHY_RFShadowCompareFlagSet(Adapter, (RF_RADIO_PATH_E)eRFPath, Offset, _FALSE);
++ else
++ PHY_RFShadowCompareFlagSet(Adapter, (RF_RADIO_PATH_E)eRFPath, Offset, _TRUE);
++ }
++ }
++
++} /* PHY_RFShadowCompareFlagSetAll */
++
++
++VOID
++PHY_RFShadowRecorverFlagSetAll(
++ IN PADAPTER Adapter)
++{
++ u32 eRFPath;
++ u32 Offset;
++
++ for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++)
++ {
++ for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++)
++ {
++ // 2008/11/20 MH For S3S4 test, we only check reg 26/27 now!!!!
++ if (Offset != 0x26 && Offset != 0x27)
++ PHY_RFShadowRecorverFlagSet(Adapter, (RF_RADIO_PATH_E)eRFPath, Offset, _FALSE);
++ else
++ PHY_RFShadowRecorverFlagSet(Adapter, (RF_RADIO_PATH_E)eRFPath, Offset, _TRUE);
++ }
++ }
++
++} /* PHY_RFShadowCompareFlagSetAll */
++
++VOID
++PHY_RFShadowRefresh(
++ IN PADAPTER Adapter)
++{
++ u32 eRFPath;
++ u32 Offset;
++
++ for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++)
++ {
++ for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++)
++ {
++ RF_Shadow[eRFPath][Offset].Value = 0;
++ RF_Shadow[eRFPath][Offset].Compare = _FALSE;
++ RF_Shadow[eRFPath][Offset].Recorver = _FALSE;
++ RF_Shadow[eRFPath][Offset].ErrorOrNot = _FALSE;
++ RF_Shadow[eRFPath][Offset].Driver_Write = _FALSE;
++ }
++ }
++
++} /* PHY_RFShadowRead */
++
++/* End of HalRf6052.c */
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/hal/rtl8192c/rtl8192c_rxdesc.c linux-xbian-rpi/drivers/net/wireless/rtl8192cu/hal/rtl8192c/rtl8192c_rxdesc.c
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/hal/rtl8192c/rtl8192c_rxdesc.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/hal/rtl8192c/rtl8192c_rxdesc.c 2015-07-28 01:20:58.309639981 +0200
+@@ -0,0 +1,874 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#define _RTL8192C_REDESC_C_
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++#include <rtl8192c_hal.h>
++
++static u8 evm_db2percentage(s8 value)
++{
++ //
++ // -33dB~0dB to 0%~99%
++ //
++ s8 ret_val;
++
++ ret_val = value;
++ //ret_val /= 2;
++
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("EVMdbToPercentage92S Value=%d / %x \n", ret_val, ret_val));
++
++ if(ret_val >= 0)
++ ret_val = 0;
++ if(ret_val <= -33)
++ ret_val = -33;
++
++ ret_val = 0 - ret_val;
++ ret_val*=3;
++
++ if(ret_val == 99)
++ ret_val = 100;
++
++ return(ret_val);
++}
++
++
++static s32 signal_scale_mapping(_adapter *padapter, s32 cur_sig )
++{
++ s32 ret_sig;
++
++#ifdef CONFIG_USB_HCI
++ if(cur_sig >= 51 && cur_sig <= 100)
++ {
++ ret_sig = 100;
++ }
++ else if(cur_sig >= 41 && cur_sig <= 50)
++ {
++ ret_sig = 80 + ((cur_sig - 40)*2);
++ }
++ else if(cur_sig >= 31 && cur_sig <= 40)
++ {
++ ret_sig = 66 + (cur_sig - 30);
++ }
++ else if(cur_sig >= 21 && cur_sig <= 30)
++ {
++ ret_sig = 54 + (cur_sig - 20);
++ }
++ else if(cur_sig >= 10 && cur_sig <= 20)
++ {
++ ret_sig = 42 + (((cur_sig - 10) * 2) / 3);
++ }
++ else if(cur_sig >= 5 && cur_sig <= 9)
++ {
++ ret_sig = 22 + (((cur_sig - 5) * 3) / 2);
++ }
++ else if(cur_sig >= 1 && cur_sig <= 4)
++ {
++ ret_sig = 6 + (((cur_sig - 1) * 3) / 2);
++ }
++ else
++ {
++ ret_sig = cur_sig;
++ }
++#else
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++
++ if(pHalData->CustomerID == RT_CID_819x_Lenovo)
++ {
++ // Step 1. Scale mapping.
++ // 20100611 Joseph: Re-tunning RSSI presentation for Lenovo.
++ // 20100426 Joseph: Modify Signal strength mapping.
++ // This modification makes the RSSI indication similar to Intel solution.
++ // 20100414 Joseph: Tunning RSSI for Lenovo according to RTL8191SE.
++ if(cur_sig >= 54 && cur_sig <= 100)
++ {
++ ret_sig = 100;
++ }
++ else if(cur_sig>=42 && cur_sig <= 53 )
++ {
++ ret_sig = 95;
++ }
++ else if(cur_sig>=36 && cur_sig <= 41 )
++ {
++ ret_sig = 74 + ((cur_sig - 36) *20)/6;
++ }
++ else if(cur_sig>=33 && cur_sig <= 35 )
++ {
++ ret_sig = 65 + ((cur_sig - 33) *8)/2;
++ }
++ else if(cur_sig>=18 && cur_sig <= 32 )
++ {
++ ret_sig = 62 + ((cur_sig - 18) *2)/15;
++ }
++ else if(cur_sig>=15 && cur_sig <= 17 )
++ {
++ ret_sig = 33 + ((cur_sig - 15) *28)/2;
++ }
++ else if(cur_sig>=10 && cur_sig <= 14 )
++ {
++ ret_sig = 39;
++ }
++ else if(cur_sig>=8 && cur_sig <= 9 )
++ {
++ ret_sig = 33;
++ }
++ else if(cur_sig <= 8 )
++ {
++ ret_sig = 19;
++ }
++ }
++ else
++ {
++ // Step 1. Scale mapping.
++ if(cur_sig >= 61 && cur_sig <= 100)
++ {
++ ret_sig = 90 + ((cur_sig - 60) / 4);
++ }
++ else if(cur_sig >= 41 && cur_sig <= 60)
++ {
++ ret_sig = 78 + ((cur_sig - 40) / 2);
++ }
++ else if(cur_sig >= 31 && cur_sig <= 40)
++ {
++ ret_sig = 66 + (cur_sig - 30);
++ }
++ else if(cur_sig >= 21 && cur_sig <= 30)
++ {
++ ret_sig = 54 + (cur_sig - 20);
++ }
++ else if(cur_sig >= 5 && cur_sig <= 20)
++ {
++ ret_sig = 42 + (((cur_sig - 5) * 2) / 3);
++ }
++ else if(cur_sig == 4)
++ {
++ ret_sig = 36;
++ }
++ else if(cur_sig == 3)
++ {
++ ret_sig = 27;
++ }
++ else if(cur_sig == 2)
++ {
++ ret_sig = 18;
++ }
++ else if(cur_sig == 1)
++ {
++ ret_sig = 9;
++ }
++ else
++ {
++ ret_sig = cur_sig;
++ }
++ }
++#endif
++
++ return ret_sig;
++}
++
++
++static s32 translate2dbm(u8 signal_strength_idx)
++{
++ s32 signal_power; // in dBm.
++
++
++ // Translate to dBm (x=0.5y-95).
++ signal_power = (s32)((signal_strength_idx + 1) >> 1);
++ signal_power -= 95;
++
++ return signal_power;
++}
++
++static void query_rx_phy_status(union recv_frame *prframe, struct phy_stat *pphy_stat)
++{
++ PHY_STS_OFDM_8192CD_T *pOfdm_buf;
++ PHY_STS_CCK_8192CD_T *pCck_buf;
++ u8 i, max_spatial_stream, evm;
++ s8 rx_pwr[4], rx_pwr_all = 0;
++ u8 pwdb_all;
++ u32 rssi,total_rssi=0;
++ u8 bcck_rate=0, rf_rx_num = 0, cck_highpwr = 0;
++ _adapter *padapter = prframe->u.hdr.adapter;
++ struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib;
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++ struct dm_priv *pdmpriv = &pHalData->dmpriv;
++ u8 tmp_rxsnr;
++ s8 rx_snrX;
++
++#ifdef CONFIG_HW_ANTENNA_DIVERSITY
++ PHY_RX_DRIVER_INFO_8192CD *pDrvInfo = ((PHY_RX_DRIVER_INFO_8192CD *)pphy_stat);
++ u8 bant1_sel = (pDrvInfo->ANTSEL == 1)?_TRUE:_FALSE;
++#endif
++
++ // Record it for next packet processing
++ bcck_rate=(pattrib->mcs_rate<=3? 1:0);
++
++ if(bcck_rate) //CCK
++ {
++ u8 report;
++#ifdef CONFIG_HW_ANTENNA_DIVERSITY
++ if(bant1_sel == _TRUE)
++ pHalData->CCK_Ant1_Cnt++;
++ else
++ pHalData->CCK_Ant2_Cnt++;
++#endif
++
++ // CCK Driver info Structure is not the same as OFDM packet.
++ pCck_buf = (PHY_STS_CCK_8192CD_T *)pphy_stat;
++ //Adapter->RxStats.NumQryPhyStatusCCK++;
++
++ //
++ // (1)Hardware does not provide RSSI for CCK
++ // (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive)
++ //
++
++ if(padapter->pwrctrlpriv.rf_pwrstate == rf_on)
++ cck_highpwr = (u8)pHalData->bCckHighPower;
++ else
++ cck_highpwr = _FALSE;
++
++ if(!cck_highpwr)
++ {
++ report = pCck_buf->cck_agc_rpt&0xc0;
++ report = report>>6;
++ switch(report)
++ {
++ // 03312009 modified by cosa
++ // Modify the RF RNA gain value to -40, -20, -2, 14 by Jenyu's suggestion
++ // Note: different RF with the different RNA gain.
++ case 0x3:
++ rx_pwr_all = (-46) - (pCck_buf->cck_agc_rpt & 0x3e);
++ break;
++ case 0x2:
++ rx_pwr_all = (-26) - (pCck_buf->cck_agc_rpt & 0x3e);
++ break;
++ case 0x1:
++ rx_pwr_all = (-12) - (pCck_buf->cck_agc_rpt & 0x3e);
++ break;
++ case 0x0:
++ rx_pwr_all = (16) - (pCck_buf->cck_agc_rpt & 0x3e);
++ break;
++ }
++ }
++ else
++ {
++ report = pCck_buf->cck_agc_rpt & 0x60;
++ report = report>>5;
++ switch(report)
++ {
++ case 0x3:
++ rx_pwr_all = (-46) - ((pCck_buf->cck_agc_rpt & 0x1f)<<1) ;
++ break;
++ case 0x2:
++ rx_pwr_all = (-26)- ((pCck_buf->cck_agc_rpt & 0x1f)<<1);
++ break;
++ case 0x1:
++ rx_pwr_all = (-12) - ((pCck_buf->cck_agc_rpt & 0x1f)<<1) ;
++ break;
++ case 0x0:
++ rx_pwr_all = (16) - ((pCck_buf->cck_agc_rpt & 0x1f)<<1) ;
++ break;
++ }
++ }
++
++ pwdb_all= query_rx_pwr_percentage(rx_pwr_all);
++ if(pHalData->CustomerID == RT_CID_819x_Lenovo)
++ {
++ // CCK gain is smaller than OFDM/MCS gain,
++ // so we add gain diff by experiences, the val is 6
++ pwdb_all+=6;
++ if(pwdb_all > 100)
++ pwdb_all = 100;
++ // modify the offset to make the same gain index with OFDM.
++ if(pwdb_all > 34 && pwdb_all <= 42)
++ pwdb_all -= 2;
++ else if(pwdb_all > 26 && pwdb_all <= 34)
++ pwdb_all -= 6;
++ else if(pwdb_all > 14 && pwdb_all <= 26)
++ pwdb_all -= 8;
++ else if(pwdb_all > 4 && pwdb_all <= 14)
++ pwdb_all -= 4;
++ }
++
++ pattrib->RxPWDBAll = pwdb_all; //for DIG/rate adaptive
++ pattrib->RecvSignalPower = rx_pwr_all; //dBM
++ padapter->recvpriv.rxpwdb = rx_pwr_all;
++ //
++ // (3) Get Signal Quality (EVM)
++ //
++ //if(bPacketMatchBSSID)
++ {
++ u8 sq;
++
++ if(pHalData->CustomerID == RT_CID_819x_Lenovo)
++ {
++ // mapping to 5 bars for vista signal strength
++ // signal quality in driver will be displayed to signal strength
++ // in vista.
++ if(pwdb_all >= 50)
++ sq = 100;
++ else if(pwdb_all >= 35 && pwdb_all < 50)
++ sq = 80;
++ else if(pwdb_all >= 22 && pwdb_all < 35)
++ sq = 60;
++ else if(pwdb_all >= 18 && pwdb_all < 22)
++ sq = 40;
++ else
++ sq = 20;
++ }
++ else
++ {
++ if(pwdb_all> 40)
++ {
++ sq = 100;
++ }
++ else
++ {
++ sq = pCck_buf->SQ_rpt;
++
++ if(pCck_buf->SQ_rpt > 64)
++ sq = 0;
++ else if (pCck_buf->SQ_rpt < 20)
++ sq= 100;
++ else
++ sq = ((64-sq) * 100) / 44;
++
++ }
++ }
++
++ pattrib->signal_qual=sq;
++ pattrib->rx_mimo_signal_qual[0]=sq;
++ pattrib->rx_mimo_signal_qual[1]=(-1);
++ }
++
++ }
++ else //OFDM/HT
++ {
++#ifdef CONFIG_HW_ANTENNA_DIVERSITY
++ if(bant1_sel == _TRUE)
++ pHalData->OFDM_Ant1_Cnt++;
++ else
++ pHalData->OFDM_Ant2_Cnt++;
++#endif
++ pdmpriv->OFDM_Pkt_Cnt++;
++
++ pOfdm_buf = (PHY_STS_OFDM_8192CD_T *)pphy_stat;
++
++ //
++ // (1)Get RSSI per-path
++ //
++ for(i=0; i<pHalData->NumTotalRFPath; i++)
++ {
++ // 2008/01/30 MH we will judge RF RX path now.
++ if (pHalData->bRFPathRxEnable[i])
++ rf_rx_num++;
++ //else
++ //continue;
++
++ rx_pwr[i] = ((pOfdm_buf->trsw_gain_X[i]&0x3F)*2) - 110;
++ padapter->recvpriv.RxRssi[i] = rx_pwr[i];
++ /* Translate DBM to percentage. */
++ pattrib->rx_rssi[i] = rssi = query_rx_pwr_percentage(rx_pwr[i]);
++ total_rssi += rssi;
++
++ RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("RF-%d RXPWR=%x RSSI=%d\n", i, rx_pwr[i], rssi));
++
++ //Get Rx snr value in DB
++ tmp_rxsnr = pOfdm_buf->rxsnr_X[i];
++ rx_snrX = (s8)(tmp_rxsnr);
++ rx_snrX >>= 1;
++ padapter->recvpriv.RxSNRdB[i] = (int)rx_snrX;
++ pattrib->rx_snr[i]=pOfdm_buf->rxsnr_X[i];
++ /* Record Signal Strength for next packet */
++ //if(bPacketMatchBSSID)
++ {
++ //pRfd->Status.RxMIMOSignalStrength[i] =(u1Byte) RSSI;
++
++ //The following is for lenovo signal strength in vista
++ if(pHalData->CustomerID == RT_CID_819x_Lenovo)
++ {
++ u8 sq;
++
++ if(i == 0)
++ {
++ // mapping to 5 bars for vista signal strength
++ // signal quality in driver will be displayed to signal strength
++ // in vista.
++ if(rssi >= 50)
++ sq = 100;
++ else if(rssi >= 35 && rssi < 50)
++ sq = 80;
++ else if(rssi >= 22 && rssi < 35)
++ sq = 60;
++ else if(rssi >= 18 && rssi < 22)
++ sq = 40;
++ else
++ sq = 20;
++ //DbgPrint("ofdm/mcs RSSI=%d\n", RSSI);
++ //pRfd->Status.SignalQuality = SQ;
++ //DbgPrint("ofdm/mcs SQ = %d\n", pRfd->Status.SignalQuality);
++ }
++ }
++ }
++ }
++
++
++ //
++ // (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive),average
++ //
++ rx_pwr_all = (((pOfdm_buf->pwdb_all ) >> 1 )& 0x7f) -110;//for OFDM Average RSSI
++ pwdb_all = query_rx_pwr_percentage(rx_pwr_all);
++
++ RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("PWDB_ALL=%d\n", pwdb_all));
++
++ pattrib->RxPWDBAll = pwdb_all; //for DIG/rate adaptive
++ pattrib->RecvSignalPower = rx_pwr_all;//dBM
++ padapter->recvpriv.rxpwdb = rx_pwr_all;
++ //
++ // (3)EVM of HT rate
++ //
++ if(pHalData->CustomerID != RT_CID_819x_Lenovo)
++ {
++ if(pattrib->rxht && pattrib->mcs_rate >=20 && pattrib->mcs_rate<=27)
++ max_spatial_stream = 2; //both spatial stream make sense
++ else
++ max_spatial_stream = 1; //only spatial stream 1 makes sense
++
++ for(i=0; i<max_spatial_stream; i++)
++ {
++ // Do not use shift operation like "rx_evmX >>= 1" because the compilor of free build environment
++ // fill most significant bit to "zero" when doing shifting operation which may change a negative
++ // value to positive one, then the dbm value (which is supposed to be negative) is not correct anymore.
++ evm = evm_db2percentage( (pOfdm_buf->rxevm_X[i]/*/ 2*/));//dbm
++
++ RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("RXRATE=%x RXEVM=%x EVM=%s%d\n",
++ pattrib->mcs_rate, pOfdm_buf->rxevm_X[i], "%",evm));
++
++ //if(bPacketMatchBSSID)
++ {
++ if(i==0) // Fill value in RFD, Get the first spatial stream only
++ {
++ pattrib->signal_qual = (u8)(evm & 0xff);
++ }
++ pattrib->rx_mimo_signal_qual[i] = (u8)(evm & 0xff);
++ }
++ }
++
++ }
++
++ //
++ // 4. Record rx statistics for debug
++ //
++
++ }
++
++
++ //UI BSS List signal strength(in percentage), make it good looking, from 0~100.
++ //It is assigned to the BSS List in GetValueFromBeaconOrProbeRsp().
++ if(bcck_rate)
++ {
++ pattrib->signal_strength=(u8)signal_scale_mapping(padapter, pwdb_all);
++ }
++ else
++ {
++ if (rf_rx_num != 0)
++ {
++ pattrib->signal_strength= (u8)(signal_scale_mapping(padapter, total_rssi/=rf_rx_num));
++ }
++ }
++ //DBG_8192C("%s,rx_pwr_all(%d),RxPWDBAll(%d)\n",__FUNCTION__,rx_pwr_all,pattrib->RxPWDBAll);
++
++}
++
++
++static void process_rssi(_adapter *padapter,union recv_frame *prframe)
++{
++ u32 last_rssi, tmp_val;
++ struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib;
++#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
++ struct signal_stat * signal_stat = &padapter->recvpriv.signal_strength_data;
++#endif //CONFIG_NEW_SIGNAL_STAT_PROCESS
++
++ //DBG_8192C("process_rssi=> pattrib->rssil(%d) signal_strength(%d)\n ",pattrib->RecvSignalPower,pattrib->signal_strength);
++ //if(pRfd->Status.bPacketToSelf || pRfd->Status.bPacketBeacon)
++ {
++
++ #ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
++ if(signal_stat->update_req) {
++ signal_stat->total_num = 0;
++ signal_stat->total_val = 0;
++ signal_stat->update_req = 0;
++ }
++
++ signal_stat->total_num++;
++ signal_stat->total_val += pattrib->signal_strength;
++ signal_stat->avg_val = signal_stat->total_val / signal_stat->total_num;
++ #else //CONFIG_NEW_SIGNAL_STAT_PROCESS
++
++ //Adapter->RxStats.RssiCalculateCnt++; //For antenna Test
++ if(padapter->recvpriv.signal_strength_data.total_num++ >= PHY_RSSI_SLID_WIN_MAX)
++ {
++ padapter->recvpriv.signal_strength_data.total_num = PHY_RSSI_SLID_WIN_MAX;
++ last_rssi = padapter->recvpriv.signal_strength_data.elements[padapter->recvpriv.signal_strength_data.index];
++ padapter->recvpriv.signal_strength_data.total_val -= last_rssi;
++ }
++ padapter->recvpriv.signal_strength_data.total_val +=pattrib->signal_strength;
++
++ padapter->recvpriv.signal_strength_data.elements[padapter->recvpriv.signal_strength_data.index++] = pattrib->signal_strength;
++ if(padapter->recvpriv.signal_strength_data.index >= PHY_RSSI_SLID_WIN_MAX)
++ padapter->recvpriv.signal_strength_data.index = 0;
++
++
++ tmp_val = padapter->recvpriv.signal_strength_data.total_val/padapter->recvpriv.signal_strength_data.total_num;
++
++ if(padapter->recvpriv.is_signal_dbg) {
++ padapter->recvpriv.signal_strength= padapter->recvpriv.signal_strength_dbg;
++ padapter->recvpriv.rssi=(s8)translate2dbm((u8)padapter->recvpriv.signal_strength_dbg);
++ } else {
++ padapter->recvpriv.signal_strength= tmp_val;
++ padapter->recvpriv.rssi=(s8)translate2dbm((u8)tmp_val);
++ }
++
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("UI RSSI = %d, ui_rssi.TotalVal = %d, ui_rssi.TotalNum = %d\n", tmp_val, padapter->recvpriv.signal_strength_data.total_val,padapter->recvpriv.signal_strength_data.total_num));
++ #endif //CONFIG_NEW_SIGNAL_STAT_PROCESS
++ }
++
++}// Process_UI_RSSI_8192C
++
++
++static void process_PWDB(_adapter *padapter, union recv_frame *prframe)
++{
++ int UndecoratedSmoothedPWDB;
++ int UndecoratedSmoothedCCK;
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++ struct dm_priv *pdmpriv = &pHalData->dmpriv;
++ struct rx_pkt_attrib *pattrib= &prframe->u.hdr.attrib;
++ struct sta_info *psta = prframe->u.hdr.psta;
++ u8 isCCKrate=(pattrib->mcs_rate<=3? 1:0);
++
++
++ if(psta)
++ {
++ UndecoratedSmoothedPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB;
++ UndecoratedSmoothedCCK = psta->rssi_stat.UndecoratedSmoothedCCK;
++ }
++ else
++ {
++ UndecoratedSmoothedPWDB = pdmpriv->UndecoratedSmoothedPWDB;
++ UndecoratedSmoothedCCK = pdmpriv->UndecoratedSmoothedCCK;
++ }
++
++ //if(pRfd->Status.bPacketToSelf || pRfd->Status.bPacketBeacon)
++
++ if(!isCCKrate)
++ {
++ // Process OFDM RSSI
++ if(UndecoratedSmoothedPWDB < 0) // initialize
++ {
++ UndecoratedSmoothedPWDB = pattrib->RxPWDBAll;
++ }
++
++ if(pattrib->RxPWDBAll > (u32)UndecoratedSmoothedPWDB)
++ {
++ UndecoratedSmoothedPWDB =
++ ( ((UndecoratedSmoothedPWDB)*(Rx_Smooth_Factor-1)) +
++ (pattrib->RxPWDBAll)) /(Rx_Smooth_Factor);
++
++ UndecoratedSmoothedPWDB = UndecoratedSmoothedPWDB + 1;
++ }
++ else
++ {
++ UndecoratedSmoothedPWDB =
++ ( ((UndecoratedSmoothedPWDB)*(Rx_Smooth_Factor-1)) +
++ (pattrib->RxPWDBAll)) /(Rx_Smooth_Factor);
++ }
++ }
++ else
++ {
++ // Process CCK RSSI
++ if(UndecoratedSmoothedCCK < 0) // initialize
++ {
++ UndecoratedSmoothedCCK = pattrib->RxPWDBAll;
++ }
++
++ if(pattrib->RxPWDBAll > (u32)UndecoratedSmoothedCCK)
++ {
++ UndecoratedSmoothedCCK =
++ ( ((UndecoratedSmoothedCCK)*(Rx_Smooth_Factor-1)) +
++ (pattrib->RxPWDBAll)) /(Rx_Smooth_Factor);
++
++ UndecoratedSmoothedCCK = UndecoratedSmoothedCCK + 1;
++ }
++ else
++ {
++ UndecoratedSmoothedCCK =
++ ( ((UndecoratedSmoothedCCK)*(Rx_Smooth_Factor-1)) +
++ (pattrib->RxPWDBAll)) /(Rx_Smooth_Factor);
++ }
++ }
++
++
++ if(psta)
++ {
++ //psta->UndecoratedSmoothedPWDB = UndecoratedSmoothedPWDB;//todo:
++ pdmpriv->UndecoratedSmoothedPWDB = UndecoratedSmoothedPWDB;
++
++ if(pdmpriv->RSSI_Select == RSSI_OFDM){
++ psta->rssi_stat.UndecoratedSmoothedPWDB = UndecoratedSmoothedPWDB;
++ }
++ else if(pdmpriv->RSSI_Select == RSSI_CCK){
++ psta->rssi_stat.UndecoratedSmoothedPWDB = UndecoratedSmoothedCCK;
++ }
++ else{
++ if(UndecoratedSmoothedPWDB <0 )
++ pdmpriv->UndecoratedSmoothedPWDB = UndecoratedSmoothedCCK;
++ else
++ pdmpriv->UndecoratedSmoothedPWDB = UndecoratedSmoothedPWDB;
++ }
++ psta->rssi_stat.UndecoratedSmoothedCCK = UndecoratedSmoothedCCK;
++ }
++ else
++ {
++ //pdmpriv->UndecoratedSmoothedPWDB = UndecoratedSmoothedPWDB;
++
++ if(pdmpriv->RSSI_Select == RSSI_OFDM){
++ pdmpriv->UndecoratedSmoothedPWDB = UndecoratedSmoothedPWDB;
++ }
++ else if(pdmpriv->RSSI_Select == RSSI_CCK){
++ pdmpriv->UndecoratedSmoothedPWDB = UndecoratedSmoothedCCK;
++ }
++ else {
++ if(UndecoratedSmoothedPWDB <0 )
++ pdmpriv->UndecoratedSmoothedPWDB = UndecoratedSmoothedCCK;
++ else
++ pdmpriv->UndecoratedSmoothedPWDB = UndecoratedSmoothedPWDB;
++
++ }
++ pdmpriv->UndecoratedSmoothedCCK = UndecoratedSmoothedCCK;
++ }
++
++ //UpdateRxSignalStatistics8192C(padapter, prframe);
++
++}
++
++
++static void process_link_qual(_adapter *padapter,union recv_frame *prframe)
++{
++ u32 last_evm=0, tmpVal;
++ struct rx_pkt_attrib *pattrib;
++#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
++ struct signal_stat * signal_stat;
++#endif //CONFIG_NEW_SIGNAL_STAT_PROCESS
++
++ if(prframe == NULL || padapter==NULL){
++ return;
++ }
++
++ pattrib = &prframe->u.hdr.attrib;
++#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
++ signal_stat = &padapter->recvpriv.signal_qual_data;
++#endif //CONFIG_NEW_SIGNAL_STAT_PROCESS
++
++ //DBG_8192C("process_link_qual=> pattrib->signal_qual(%d)\n ",pattrib->signal_qual);
++
++#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
++ if(signal_stat->update_req) {
++ signal_stat->total_num = 0;
++ signal_stat->total_val = 0;
++ signal_stat->update_req = 0;
++ }
++
++ signal_stat->total_num++;
++ signal_stat->total_val += pattrib->signal_qual;
++ signal_stat->avg_val = signal_stat->total_val / signal_stat->total_num;
++
++#else //CONFIG_NEW_SIGNAL_STAT_PROCESS
++ if(pattrib->signal_qual != 0)
++ {
++ //
++ // 1. Record the general EVM to the sliding window.
++ //
++ if(padapter->recvpriv.signal_qual_data.total_num++ >= PHY_LINKQUALITY_SLID_WIN_MAX)
++ {
++ padapter->recvpriv.signal_qual_data.total_num = PHY_LINKQUALITY_SLID_WIN_MAX;
++ last_evm = padapter->recvpriv.signal_qual_data.elements[padapter->recvpriv.signal_qual_data.index];
++ padapter->recvpriv.signal_qual_data.total_val -= last_evm;
++ }
++ padapter->recvpriv.signal_qual_data.total_val += pattrib->signal_qual;
++
++ padapter->recvpriv.signal_qual_data.elements[padapter->recvpriv.signal_qual_data.index++] = pattrib->signal_qual;
++ if(padapter->recvpriv.signal_qual_data.index >= PHY_LINKQUALITY_SLID_WIN_MAX)
++ padapter->recvpriv.signal_qual_data.index = 0;
++
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("Total SQ=%d pattrib->signal_qual= %d\n", padapter->recvpriv.signal_qual_data.total_val, pattrib->signal_qual));
++
++ // <1> Showed on UI for user, in percentage.
++ tmpVal = padapter->recvpriv.signal_qual_data.total_val/padapter->recvpriv.signal_qual_data.total_num;
++ padapter->recvpriv.signal_qual=(u8)tmpVal;
++
++ }
++ else
++ {
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,(" pattrib->signal_qual =%d\n", pattrib->signal_qual));
++ }
++#endif //CONFIG_NEW_SIGNAL_STAT_PROCESS
++
++}// Process_UiLinkQuality8192S
++
++
++static void process_phy_info(_adapter *padapter, union recv_frame *prframe)
++{
++ union recv_frame *precvframe = (union recv_frame *)prframe;
++
++#ifdef CONFIG_SW_ANTENNA_DIVERSITY
++ // If we switch to the antenna for testing, the signal strength
++ // of the packets in this time shall not be counted into total receiving power.
++ // This prevents error counting Rx signal strength and affecting other dynamic mechanism.
++
++ // Select the packets to do RSSI checking for antenna switching.
++ SwAntDivRSSICheck8192C(padapter, precvframe->u.hdr.attrib.RxPWDBAll);
++
++ if(GET_HAL_DATA(padapter)->RSSI_test == _TRUE)
++ return;
++#endif
++ //
++ // Check RSSI
++ //
++ process_rssi(padapter, precvframe);
++ //
++ // Check PWDB.
++ //
++ process_PWDB(padapter, precvframe);
++ //
++ // Check EVM
++ //
++ process_link_qual(padapter, precvframe);
++
++}
++
++
++void rtl8192c_translate_rx_signal_stuff(union recv_frame *precvframe, struct phy_stat *pphy_info)
++{
++ struct rx_pkt_attrib *pattrib = &precvframe->u.hdr.attrib;
++ _adapter *padapter = precvframe->u.hdr.adapter;
++ u8 bPacketMatchBSSID =_FALSE;
++ u8 bPacketToSelf = _FALSE;
++ u8 bPacketBeacon = _FALSE;
++
++ if((pattrib->physt) && (pphy_info != NULL))
++ {
++ bPacketMatchBSSID = ((!IsFrameTypeCtrl(precvframe->u.hdr.rx_data)) && !(pattrib->icv_err) && !(pattrib->crc_err) &&
++ _rtw_memcmp(get_hdr_bssid(precvframe->u.hdr.rx_data), get_my_bssid(&padapter->mlmeextpriv.mlmext_info.network), ETH_ALEN));
++
++
++ bPacketToSelf = bPacketMatchBSSID && (_rtw_memcmp(get_da(precvframe->u.hdr.rx_data), myid(&padapter->eeprompriv), ETH_ALEN));
++
++ bPacketBeacon =bPacketMatchBSSID && (GetFrameSubType(precvframe->u.hdr.rx_data) == WIFI_BEACON);
++
++ query_rx_phy_status(precvframe, pphy_info);
++
++ precvframe->u.hdr.psta = NULL;
++ if(bPacketMatchBSSID && check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE)
++ {
++ u8 *sa;
++ struct sta_info *psta=NULL;
++ struct sta_priv *pstapriv = &padapter->stapriv;
++
++ sa = get_sa(precvframe->u.hdr.rx_data);
++
++ psta = rtw_get_stainfo(pstapriv, sa);
++ if(psta)
++ {
++ precvframe->u.hdr.psta = psta;
++ process_phy_info(padapter, precvframe);
++ }
++ }
++ else if(bPacketToSelf || bPacketBeacon)
++ {
++ if(check_fwstate(&padapter->mlmepriv, WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE) == _TRUE)
++ {
++ u8 *sa;
++ struct sta_info *psta=NULL;
++ struct sta_priv *pstapriv = &padapter->stapriv;
++
++ sa = get_sa(precvframe->u.hdr.rx_data);
++
++ psta = rtw_get_stainfo(pstapriv, sa);
++ if(psta)
++ {
++ precvframe->u.hdr.psta = psta;
++ }
++ }
++
++ process_phy_info(padapter, precvframe);
++ }
++ }
++}
++
++void rtl8192c_query_rx_desc_status(union recv_frame *precvframe, struct recv_stat *pdesc)
++{
++ struct rx_pkt_attrib *pattrib = &precvframe->u.hdr.attrib;
++
++ //Offset 0
++ pattrib->physt = (u8)((le32_to_cpu(pdesc->rxdw0) >> 26) & 0x1);
++ pattrib->pkt_len = (u16)(le32_to_cpu(pdesc->rxdw0)&0x00003fff);
++ pattrib->drvinfo_sz = (u8)((le32_to_cpu(pdesc->rxdw0) >> 16) & 0xf) * 8;//uint 2^3 = 8 bytes
++
++ pattrib->shift_sz = (u8)((le32_to_cpu(pdesc->rxdw0) >> 24) & 0x3);
++
++ pattrib->crc_err = (u8)((le32_to_cpu(pdesc->rxdw0) >> 14) & 0x1);
++ pattrib->icv_err = (u8)((le32_to_cpu(pdesc->rxdw0) >> 15) & 0x1);
++ pattrib->qos = (u8)(( le32_to_cpu( pdesc->rxdw0 ) >> 23) & 0x1);// Qos data, wireless lan header length is 26
++ pattrib->bdecrypted = (le32_to_cpu(pdesc->rxdw0) & BIT(27))? 0:1;
++
++ //Offset 4
++ pattrib->mfrag = (u8)((le32_to_cpu(pdesc->rxdw1) >> 27) & 0x1);//more fragment bit
++
++ //Offset 8
++ pattrib->frag_num = (u8)((le32_to_cpu(pdesc->rxdw2) >> 12) & 0xf);//fragmentation number
++
++ //Offset 12
++#ifdef CONFIG_TCP_CSUM_OFFLOAD_RX
++ if ( le32_to_cpu(pdesc->rxdw3) & BIT(13)){
++ pattrib->tcpchk_valid = 1; // valid
++ if ( le32_to_cpu(pdesc->rxdw3) & BIT(11) ) {
++ pattrib->tcp_chkrpt = 1; // correct
++ //DBG_8192C("tcp csum ok\n");
++ }
++ else
++ pattrib->tcp_chkrpt = 0; // incorrect
++
++ if ( le32_to_cpu(pdesc->rxdw3) & BIT(12) )
++ pattrib->ip_chkrpt = 1; // correct
++ else
++ pattrib->ip_chkrpt = 0; // incorrect
++ }
++ else {
++ pattrib->tcpchk_valid = 0; // invalid
++ }
++#endif
++
++ pattrib->mcs_rate=(u8)((le32_to_cpu(pdesc->rxdw3))&0x3f);
++ pattrib->rxht=(u8)((le32_to_cpu(pdesc->rxdw3) >>6)&0x1);
++ pattrib->sgi=(u8)((le32_to_cpu(pdesc->rxdw3) >>8)&0x1);
++ //Offset 16
++ //Offset 20
++
++}
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/hal/rtl8192c/rtl8192c_sreset.c linux-xbian-rpi/drivers/net/wireless/rtl8192cu/hal/rtl8192c/rtl8192c_sreset.c
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/hal/rtl8192c/rtl8192c_sreset.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/hal/rtl8192c/rtl8192c_sreset.c 2015-07-28 01:20:58.309639981 +0200
+@@ -0,0 +1,93 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#include <rtl8192c_sreset.h>
++#include <rtl8192c_hal.h>
++#ifdef DBG_CONFIG_ERROR_DETECT
++void rtl8192c_sreset_xmit_status_check(_adapter *padapter)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++ struct sreset_priv *psrtpriv = &pHalData->srestpriv;
++
++ unsigned long current_time;
++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++ unsigned int diff_time;
++ u32 txdma_status;
++ if( (txdma_status=rtw_read32(padapter, REG_TXDMA_STATUS)) !=0x00){
++ DBG_871X("%s REG_TXDMA_STATUS:0x%08x\n", __FUNCTION__, txdma_status);
++ rtw_hal_sreset_reset(padapter);
++ }
++
++ //total xmit irp = 4
++ //DBG_8192C("==>%s free_xmitbuf_cnt(%d),txirp_cnt(%d)\n",__FUNCTION__,pxmitpriv->free_xmitbuf_cnt,pxmitpriv->txirp_cnt);
++ //if(pxmitpriv->txirp_cnt == NR_XMITBUFF+1)
++ current_time = rtw_get_current_time();
++
++ if(0 == pxmitpriv->free_xmitbuf_cnt || 0 == pxmitpriv->free_xmit_extbuf_cnt) {
++
++ diff_time = rtw_get_passing_time_ms(psrtpriv->last_tx_time);
++
++ if (diff_time > 2000) {
++ if (psrtpriv->last_tx_complete_time == 0) {
++ psrtpriv->last_tx_complete_time = current_time;
++ }
++ else{
++ diff_time = rtw_get_passing_time_ms(psrtpriv->last_tx_complete_time);
++ if (diff_time > 4000) {
++ //padapter->Wifi_Error_Status = WIFI_TX_HANG;
++ DBG_871X("%s tx hang\n", __FUNCTION__);
++ rtw_hal_sreset_reset(padapter);
++ }
++ }
++ }
++ }
++
++ if (psrtpriv->dbg_trigger_point == SRESET_TGP_XMIT_STATUS) {
++ psrtpriv->dbg_trigger_point = SRESET_TGP_NULL;
++ rtw_hal_sreset_reset(padapter);
++ return;
++ }
++}
++void rtl8192c_sreset_linked_status_check(_adapter *padapter)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++ struct sreset_priv *psrtpriv = &pHalData->srestpriv;
++
++ u32 regc50,regc58,reg824,reg800;
++ regc50 = rtw_read32(padapter,0xc50);
++ regc58 = rtw_read32(padapter,0xc58);
++ reg824 = rtw_read32(padapter,0x824);
++ reg800 = rtw_read32(padapter,0x800);
++ if( ((regc50&0xFFFFFF00)!= 0x69543400)||
++ ((regc58&0xFFFFFF00)!= 0x69543400)||
++ (((reg824&0xFFFFFF00)!= 0x00390000)&&(((reg824&0xFFFFFF00)!= 0x80390000)))||
++ ( ((reg800&0xFFFFFF00)!= 0x03040000)&&((reg800&0xFFFFFF00)!= 0x83040000)))
++ {
++ DBG_8192C("%s regc50:0x%08x, regc58:0x%08x, reg824:0x%08x, reg800:0x%08x,\n", __FUNCTION__,
++ regc50, regc58, reg824, reg800);
++ rtw_hal_sreset_reset(padapter);
++ }
++
++ if (psrtpriv->dbg_trigger_point == SRESET_TGP_LINK_STATUS) {
++ psrtpriv->dbg_trigger_point = SRESET_TGP_NULL;
++ rtw_hal_sreset_reset(padapter);
++ return;
++ }
++}
++#endif
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/hal/rtl8192c/rtl8192c_xmit.c linux-xbian-rpi/drivers/net/wireless/rtl8192cu/hal/rtl8192c/rtl8192c_xmit.c
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/hal/rtl8192c/rtl8192c_xmit.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/hal/rtl8192c/rtl8192c_xmit.c 2015-07-28 01:20:58.309639981 +0200
+@@ -0,0 +1,62 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#define _RTL8192C_XMIT_C_
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++#include <rtl8192c_hal.h>
++
++#ifdef CONFIG_XMIT_ACK
++void dump_txrpt_ccx_8192c(void *buf)
++{
++ struct txrpt_ccx_8192c *txrpt_ccx = buf;
++
++ DBG_871X("%s:\n"
++ "retry_cnt:%u, rsvd_0:%u, rts_retry_cnt:%u, rsvd_1:%u\n"
++ "ccx_qtime:%u, missed_pkt_num:%u, rsvd_4:%u\n"
++ "mac_id:%u, des1_fragssn:%u\n"
++ "rpt_pkt_num:%u, pkt_drop:%u, lifetime_over:%u, retry_over:%u\n"
++ "edca_tx_queue:%u, rsvd_7:%u, bmc:%u, pkt_ok:%u, init_ccx:%u\n"
++ , __func__
++ , txrpt_ccx->retry_cnt, txrpt_ccx->rsvd_0, txrpt_ccx->rts_retry_cnt, txrpt_ccx->rsvd_1
++ , txrpt_ccx_qtime_8192c(txrpt_ccx), txrpt_ccx->missed_pkt_num, txrpt_ccx->rsvd_4
++ , txrpt_ccx->mac_id, txrpt_ccx->des1_fragssn
++ , txrpt_ccx->rpt_pkt_num, txrpt_ccx->pkt_drop, txrpt_ccx->lifetime_over, txrpt_ccx->retry_over
++ , txrpt_ccx->edca_tx_queue, txrpt_ccx->rsvd_7, txrpt_ccx->bmc, txrpt_ccx->pkt_ok, txrpt_ccx->int_ccx
++ );
++}
++
++void handle_txrpt_ccx_8192c(_adapter *adapter, void *buf)
++{
++ struct txrpt_ccx_8192c *txrpt_ccx = buf;
++
++ #ifdef DBG_CCX
++ dump_txrpt_ccx_8192c(buf);
++ #endif
++
++ if (txrpt_ccx->int_ccx) {
++ if (txrpt_ccx->pkt_ok)
++ rtw_ack_tx_done(&adapter->xmitpriv, RTW_SCTX_DONE_SUCCESS);
++ else
++ rtw_ack_tx_done(&adapter->xmitpriv, RTW_SCTX_DONE_CCX_PKT_FAIL);
++ }
++}
++#endif //CONFIG_XMIT_ACK
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/hal/rtl8192c/usb/Hal8192CUHWImg.c linux-xbian-rpi/drivers/net/wireless/rtl8192cu/hal/rtl8192c/usb/Hal8192CUHWImg.c
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/hal/rtl8192c/usb/Hal8192CUHWImg.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/hal/rtl8192c/usb/Hal8192CUHWImg.c 2015-07-28 01:20:58.313625760 +0200
+@@ -0,0 +1,8757 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++
++/*Created on 2011/ 6/15, 5:45*/
++
++#include <basic_types.h>
++#include "Hal8192CUHWImg.h"
++
++#ifdef CONFIG_BT_COEXISTENCE
++// =================== v84 TSMC COMMON 2012-04-13 =======================
++u8 Rtl8192CUFwTSMCImgArray[TSMCImgArrayLength] = {
++0xc1,0x88,0x02,0x00,0x54,0x00,0x01,0x00,0x04,0x13,0x11,0x07,0x3a,0x3d,0x00,0x00,
++0x58,0x97,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x02,0x43,0xba,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x02,0x50,0xa1,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x02,0x57,0x91,0x00,0x00,0x00,0x00,0x00,0xa1,0xe8,0x00,0x00,0x00,
++0x05,0x04,0x03,0x02,0x00,0x03,0x06,0x05,0x04,0x03,0x00,0x04,0x06,0x05,0x04,0x02,
++0x00,0x04,0x08,0x07,0x06,0x04,0x00,0x06,0x0a,0x09,0x08,0x06,0x00,0x08,0x0a,0x09,
++0x08,0x04,0x00,0x08,0x0a,0x09,0x08,0x02,0x00,0x08,0x0a,0x09,0x08,0x00,0x00,0x08,
++0x12,0x11,0x10,0x08,0x00,0x10,0x1a,0x19,0x18,0x10,0x00,0x18,0x22,0x21,0x20,0x18,
++0x00,0x20,0x22,0x21,0x20,0x10,0x00,0x20,0x22,0x21,0x20,0x08,0x00,0x20,0x22,0x21,
++0x1c,0x08,0x00,0x20,0x22,0x21,0x14,0x08,0x00,0x20,0x22,0x20,0x18,0x08,0x00,0x20,
++0x31,0x30,0x20,0x10,0x00,0x30,0x31,0x30,0x18,0x00,0x00,0x30,0x31,0x2f,0x10,0x10,
++0x00,0x30,0x31,0x2c,0x10,0x10,0x00,0x30,0x31,0x28,0x10,0x00,0x00,0x30,0x31,0x20,
++0x10,0x00,0x00,0x30,0x31,0x10,0x10,0x00,0x00,0x30,0x04,0x04,0x04,0x05,0x04,0x04,
++0x04,0x05,0x05,0x05,0x06,0x06,0x04,0x04,0x04,0x05,0x05,0x05,0x06,0x06,0x04,0x04,
++0x05,0x05,0x05,0x05,0x06,0x06,0x04,0x04,0x05,0x05,0x05,0x05,0x06,0x07,0x0a,0x0b,
++0x0d,0x10,0x04,0x05,0x05,0x06,0x06,0x09,0x0c,0x11,0x08,0x08,0x09,0x09,0x0a,0x0c,
++0x10,0x11,0x04,0x04,0x04,0x05,0x04,0x04,0x05,0x07,0x07,0x07,0x08,0x0a,0x04,0x04,
++0x04,0x04,0x06,0x0a,0x0b,0x0d,0x05,0x05,0x07,0x07,0x08,0x0b,0x0d,0x0f,0x04,0x04,
++0x04,0x05,0x07,0x07,0x09,0x09,0x0c,0x0e,0x10,0x12,0x04,0x04,0x05,0x05,0x06,0x0a,
++0x11,0x13,0x09,0x09,0x09,0x09,0x0c,0x0e,0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x24,0x26,0x2a,0x18,0x1a,0x1d,0x1f,0x21,0x27,0x29,0x2a,0x00,0x00,
++0x00,0x1f,0x23,0x28,0x2a,0x2c,0x00,0x04,0x00,0x04,0x00,0x08,0x00,0x10,0x00,0x18,
++0x00,0x24,0x00,0x30,0x00,0x48,0x00,0x60,0x00,0x90,0x00,0xc0,0x00,0xd8,0x00,0x50,
++0x00,0x78,0x00,0xa0,0x00,0xc8,0x01,0x40,0x01,0x90,0x01,0xe0,0x02,0x30,0x01,0x2c,
++0x01,0x40,0x01,0xe0,0x02,0xd0,0x03,0xe8,0x04,0xb0,0x06,0x40,0x07,0xd0,0x00,0x02,
++0x00,0x02,0x00,0x04,0x00,0x08,0x00,0x0c,0x00,0x12,0x00,0x18,0x00,0x24,0x00,0x30,
++0x00,0x48,0x00,0x60,0x00,0x6c,0x00,0x28,0x00,0x3c,0x00,0x50,0x00,0x64,0x00,0xa0,
++0x00,0xc8,0x00,0xf0,0x01,0x18,0x00,0x64,0x00,0xa0,0x00,0xf0,0x01,0x68,0x01,0xf4,
++0x02,0x58,0x03,0x20,0x03,0xe8,0x02,0x02,0x02,0x02,0x02,0x02,0x03,0x03,0x04,0x04,
++0x05,0x07,0x04,0x04,0x07,0x0a,0x0a,0x0c,0x0c,0x12,0x05,0x07,0x07,0x08,0x0b,0x12,
++0x24,0x3c,0x01,0x01,0x01,0x01,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x01,0x02,
++0x03,0x04,0x05,0x06,0x07,0x08,0x05,0x06,0x07,0x08,0x09,0x0a,0x0b,0x0c,0x20,0x1e,
++0x1c,0x18,0x10,0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0xbb,0x01,0x0c,0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe0,0x22,0x50,
++0x06,0xe9,0x25,0x82,0xf8,0xe6,0x22,0xbb,0xfe,0x06,0xe9,0x25,0x82,0xf8,0xe2,0x22,
++0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe4,0x93,0x22,0xbb,0x01,0x06,
++0x89,0x82,0x8a,0x83,0xf0,0x22,0x50,0x02,0xf7,0x22,0xbb,0xfe,0x01,0xf3,0x22,0xf8,
++0xbb,0x01,0x0d,0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe8,0xf0,0x22,
++0x50,0x06,0xe9,0x25,0x82,0xc8,0xf6,0x22,0xbb,0xfe,0x05,0xe9,0x25,0x82,0xc8,0xf2,
++0x22,0xc5,0xf0,0xf8,0xa3,0xe0,0x28,0xf0,0xc5,0xf0,0xf8,0xe5,0x82,0x15,0x82,0x70,
++0x02,0x15,0x83,0xe0,0x38,0xf0,0x22,0xbb,0x01,0x0a,0x89,0x82,0x8a,0x83,0xe0,0xf5,
++0xf0,0xa3,0xe0,0x22,0x50,0x06,0x87,0xf0,0x09,0xe7,0x19,0x22,0xbb,0xfe,0x07,0xe3,
++0xf5,0xf0,0x09,0xe3,0x19,0x22,0x89,0x82,0x8a,0x83,0xe4,0x93,0xf5,0xf0,0x74,0x01,
++0x93,0x22,0xbb,0x01,0x10,0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe0,
++0xf5,0xf0,0xa3,0xe0,0x22,0x50,0x09,0xe9,0x25,0x82,0xf8,0x86,0xf0,0x08,0xe6,0x22,
++0xbb,0xfe,0x0a,0xe9,0x25,0x82,0xf8,0xe2,0xf5,0xf0,0x08,0xe2,0x22,0xe5,0x83,0x2a,
++0xf5,0x83,0xe9,0x93,0xf5,0xf0,0xa3,0xe9,0x93,0x22,0xbb,0x01,0x0a,0x89,0x82,0x8a,
++0x83,0xf0,0xe5,0xf0,0xa3,0xf0,0x22,0x50,0x06,0xf7,0x09,0xa7,0xf0,0x19,0x22,0xbb,
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++0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe8,0xf0,0xe5,0xf0,0xa3,0xf0,0x22,0x50,0x09,
++0xe9,0x25,0x82,0xc8,0xf6,0x08,0xa6,0xf0,0x22,0xbb,0xfe,0x09,0xe9,0x25,0x82,0xc8,
++0xf2,0xe5,0xf0,0x08,0xf2,0x22,0xef,0x4b,0xff,0xee,0x4a,0xfe,0xed,0x49,0xfd,0xec,
++0x48,0xfc,0x22,0xe0,0xfc,0xa3,0xe0,0xfd,0xa3,0xe0,0xfe,0xa3,0xe0,0xff,0x22,0xa4,
++0x25,0x82,0xf5,0x82,0xe5,0xf0,0x35,0x83,0xf5,0x83,0x22,0xe0,0xfb,0xa3,0xe0,0xfa,
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++0x15,0x82,0x70,0x02,0x15,0x83,0xe0,0xfa,0x38,0xf0,0x22,0xeb,0xf0,0xa3,0xea,0xf0,
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++0x02,0x93,0x68,0x60,0xef,0xa3,0xa3,0xa3,0x80,0xdf,0x02,0x43,0xf8,0x02,0x48,0x29,
++0xe4,0x93,0xa3,0xf8,0xe4,0x93,0xa3,0x40,0x03,0xf6,0x80,0x01,0xf2,0x08,0xdf,0xf4,
++0x80,0x29,0xe4,0x93,0xa3,0xf8,0x54,0x07,0x24,0x0c,0xc8,0xc3,0x33,0xc4,0x54,0x0f,
++0x44,0x20,0xc8,0x83,0x40,0x04,0xf4,0x56,0x80,0x01,0x46,0xf6,0xdf,0xe4,0x80,0x0b,
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++0xbc,0xa3,0xff,0x54,0x3f,0x30,0xe5,0x09,0x54,0x1f,0xfe,0xe4,0x93,0xa3,0x60,0x01,
++0x0e,0xcf,0x54,0xc0,0x25,0xe0,0x60,0xa8,0x40,0xb8,0xe4,0x93,0xa3,0xfa,0xe4,0x93,
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++0x9e,0x5d,0xe0,0x90,0x9e,0x86,0xf0,0xe4,0xfb,0xfd,0x7f,0x54,0x7e,0x01,0xd3,0x10,
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++0x3c,0x74,0x08,0xf0,0xe4,0x90,0x9e,0x85,0xf0,0x90,0x9e,0x5b,0xe0,0x90,0x9e,0x86,
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++0x90,0x06,0x92,0x74,0x02,0xf0,0x90,0x9e,0x63,0x14,0xf0,0xe5,0x61,0x54,0x0f,0xc3,
++0x94,0x0c,0x50,0x03,0x12,0x54,0xe3,0x22,0x8f,0x82,0x8e,0x83,0xa3,0xa3,0xa3,0xe4,
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++0x02,0x09,0xe0,0xff,0x7d,0x01,0xf1,0x79,0x90,0x04,0x1f,0x74,0x20,0xf0,0x22,0x22,
++0x22,0x22,0x00,0x02,0x45,0x03,0x02,0x45,0x06,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,
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++0xe4,0x75,0xf0,0x01,0x71,0x74,0x12,0x29,0xd9,0xff,0x90,0x9e,0x87,0xe4,0x75,0xf0,
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++0x92,0xaf,0x22,0x90,0x9e,0x11,0x12,0x2a,0x8b,0x00,0x00,0x00,0x00,0x90,0x06,0xa9,
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++0x91,0xcb,0x90,0x9e,0x10,0xe0,0x30,0xe6,0x13,0x43,0x64,0x01,0x90,0x9e,0x66,0xe0,
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++0x9e,0x10,0xe0,0x30,0xe7,0x16,0x43,0x64,0x02,0xe4,0x90,0x9e,0x85,0x91,0x4e,0x90,
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++0x34,0x30,0xe0,0x06,0x90,0x01,0x3c,0x74,0x01,0xf0,0xe5,0x34,0x30,0xe1,0x09,0x90,
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++0x90,0x01,0x5b,0x74,0x05,0xf0,0x90,0x06,0x92,0x74,0x01,0xf0,0x80,0x07,0x90,0x9e,
++0x64,0xe4,0xf0,0x91,0xcb,0xe5,0x34,0x30,0xe3,0x38,0x90,0x01,0x3c,0x74,0x08,0xf0,
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++0x90,0x9e,0x86,0xf0,0xe4,0xfb,0xfd,0x7f,0x5c,0x7e,0x01,0x91,0x5e,0x90,0x01,0x5f,
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++0x7b,0x5c,0x90,0x9e,0x43,0xe0,0x70,0x03,0x12,0x7c,0x5f,0x12,0x73,0x85,0x80,0xb6,
++0x90,0x01,0x3c,0x74,0xff,0xf0,0xa3,0xf0,0xa3,0xf0,0x90,0x01,0x34,0xf0,0xa3,0xf0,
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++0xff,0x7f,0x56,0x31,0x05,0x7d,0xff,0x7f,0x57,0x80,0x0a,0xf0,0x90,0x00,0x45,0xe0,
++0x54,0xfe,0xfd,0x7f,0x45,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x8f,0x82,0x75,0x83,
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++0x90,0x00,0x55,0xe0,0x5f,0xf5,0x3d,0x90,0x00,0x52,0xe0,0xff,0x90,0x00,0x56,0xe0,
++0x5f,0xf5,0x3e,0xe5,0x3d,0x30,0xe4,0x06,0x90,0x00,0x55,0x74,0x10,0xf0,0xe5,0x3d,
++0x30,0xe5,0x06,0x90,0x00,0x55,0x74,0x20,0xf0,0xe5,0x3d,0x30,0xe6,0x1b,0x90,0x00,
++0x55,0x74,0x40,0xf0,0x90,0x9e,0x42,0xe0,0x54,0x03,0xff,0xbf,0x03,0x0b,0x90,0x9e,
++0x3f,0xe0,0x60,0x05,0x7f,0x01,0x12,0x49,0x1a,0xe5,0x3d,0x30,0xe7,0x15,0x90,0x00,
++0x55,0x74,0x80,0xf0,0x90,0x9e,0x42,0xe0,0x54,0x03,0xff,0xbf,0x03,0x05,0x7f,0x02,
++0x12,0x49,0x1a,0xe5,0x3e,0x30,0xe0,0x06,0x90,0x00,0x56,0x74,0x01,0xf0,0xe5,0x3e,
++0x30,0xe1,0x06,0x90,0x00,0x56,0x74,0x02,0xf0,0xe5,0x3e,0x30,0xe2,0x06,0x90,0x00,
++0x56,0x74,0x04,0xf0,0xe5,0x3e,0x30,0xe3,0x06,0x90,0x00,0x56,0x74,0x08,0xf0,0x90,
++0x01,0xc4,0x74,0x91,0xf0,0x74,0x57,0xa3,0xf0,0xd0,0x07,0xd0,0x06,0xd0,0x05,0xd0,
++0x04,0xd0,0x03,0xd0,0x02,0xd0,0x01,0xd0,0x00,0xd0,0xd0,0xd0,0x82,0xd0,0x83,0xd0,
++0xf0,0xd0,0xe0,0x32,0x90,0x01,0xcc,0xe0,0x54,0x0f,0x90,0x9e,0x19,0xf0,0x90,0x9e,
++0x19,0xe0,0xfd,0x70,0x02,0x21,0xb5,0x90,0x9e,0xae,0xe0,0xff,0x74,0x01,0x7e,0x00,
++0xa8,0x07,0x08,0x80,0x05,0xc3,0x33,0xce,0x33,0xce,0xd8,0xf9,0xff,0xef,0x5d,0x70,
++0x02,0x21,0xae,0x90,0x9e,0xae,0xe0,0x75,0xf0,0x04,0x90,0x01,0xd0,0x12,0x43,0x5f,
++0xe0,0x90,0x9e,0x1a,0xf0,0x75,0x23,0x01,0x75,0x24,0x9e,0x75,0x25,0x1a,0x75,0x26,
++0x01,0x7b,0x01,0x7a,0x9e,0x79,0x1b,0x12,0x45,0x09,0x90,0x9e,0x1b,0xe0,0xff,0xc4,
++0x13,0x13,0x13,0x54,0x01,0x90,0x9e,0xae,0x30,0xe0,0x59,0xe0,0x75,0xf0,0x02,0x90,
++0x00,0x88,0x12,0x43,0x5f,0xe0,0x90,0x9e,0x1c,0xf0,0x90,0x9e,0xae,0xe0,0x75,0xf0,
++0x02,0x90,0x00,0x89,0x12,0x43,0x5f,0xe0,0x90,0x9e,0x1d,0xf0,0x90,0x9e,0xae,0xe0,
++0x75,0xf0,0x04,0x90,0x01,0xd1,0x12,0x43,0x5f,0xe0,0x90,0x9e,0x1e,0xf0,0x90,0x9e,
++0xae,0xe0,0x75,0xf0,0x04,0x90,0x01,0xd2,0x12,0x43,0x5f,0xe0,0x90,0x9e,0x1f,0xf0,
++0x90,0x9e,0xae,0xe0,0x75,0xf0,0x04,0x90,0x01,0xd3,0x12,0x43,0x5f,0xe0,0x90,0x9e,
++0x20,0xf0,0x80,0x33,0xe0,0x75,0xf0,0x04,0x90,0x01,0xd1,0x12,0x43,0x5f,0xe0,0x90,
++0x9e,0x1c,0xf0,0x90,0x9e,0xae,0xe0,0x75,0xf0,0x04,0x90,0x01,0xd2,0x12,0x43,0x5f,
++0xe0,0x90,0x9e,0x1d,0xf0,0x90,0x9e,0xae,0xe0,0x75,0xf0,0x04,0x90,0x01,0xd3,0x12,
++0x43,0x5f,0xe0,0x90,0x9e,0x1e,0xf0,0xef,0x54,0x7f,0xff,0x7b,0x01,0x7a,0x9e,0x79,
++0x1c,0x31,0xb6,0x90,0x9e,0x19,0xe0,0xff,0x90,0x9e,0xae,0xe0,0xfe,0x74,0x01,0xa8,
++0x06,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xf4,0x5f,0x90,0x9e,0x19,0xf0,0x90,0x9e,
++0xae,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0x90,0x01,
++0xcc,0xf0,0x90,0x9e,0xae,0xe0,0x04,0xf0,0xe0,0x54,0x03,0xf0,0x01,0x7e,0x90,0x01,
++0xc6,0xe0,0x44,0x02,0xf0,0x22,0x90,0x9e,0x21,0x12,0x43,0x8b,0xef,0x12,0x43,0x94,
++0x59,0xfc,0x01,0x59,0xf4,0x02,0x5a,0x20,0x03,0x5a,0x29,0x05,0x5a,0x32,0x06,0x5a,
++0x7e,0x07,0x5a,0x3a,0x09,0x5a,0x43,0x0b,0x5a,0x4c,0x0c,0x5a,0x55,0x0d,0x5a,0x5e,
++0x0e,0x5a,0x67,0x1b,0x5a,0x6f,0x1c,0x5a,0x05,0x2d,0x5a,0x0e,0x2e,0x5a,0x17,0x3b,
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++0x43,0x6b,0x02,0x71,0xd0,0x90,0x9e,0x21,0x12,0x43,0x6b,0x02,0x72,0x0b,0x90,0x9e,
++0x21,0x12,0x43,0x6b,0x02,0x72,0x53,0x90,0x9e,0x21,0x12,0x43,0x6b,0x02,0x72,0x8c,
++0x90,0x9e,0x21,0x12,0x43,0x6b,0x02,0x72,0xb6,0x90,0x9e,0x21,0x12,0x43,0x6b,0x02,
++0x70,0x4a,0x90,0x9e,0x21,0x12,0x43,0x6b,0x80,0x45,0x90,0x9e,0x21,0x12,0x43,0x6b,
++0x02,0x72,0xfe,0x90,0x9e,0x21,0x12,0x43,0x6b,0x02,0x70,0xa2,0x90,0x9e,0x21,0x12,
++0x43,0x6b,0x02,0x49,0xc2,0x90,0x9e,0x21,0x12,0x43,0x6b,0x02,0x7b,0x29,0x90,0x9e,
++0x21,0x12,0x43,0x6b,0x02,0x4a,0xfc,0x90,0x9e,0x21,0x12,0x43,0x6b,0xe1,0xef,0x90,
++0x9e,0x21,0x12,0x43,0x6b,0xe1,0xd1,0x90,0x01,0xc6,0xe0,0x44,0x01,0xf0,0x22,0x90,
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++0xfd,0xaf,0x06,0x90,0x9e,0x24,0xef,0xf0,0xa3,0xed,0xf0,0xa3,0x12,0x43,0x8b,0x90,
++0x9e,0x26,0x12,0x43,0x6b,0x90,0x00,0x03,0x12,0x42,0x20,0x54,0xf0,0xc4,0x54,0x0f,
++0x90,0x9e,0x29,0xf0,0x90,0x00,0x04,0x12,0x42,0x20,0x54,0x40,0xc4,0x13,0x13,0x54,
++0x03,0x90,0x9e,0x2a,0xf0,0x90,0x9e,0x24,0xe0,0xff,0x75,0xf0,0x09,0x90,0x96,0x46,
++0x12,0x43,0x5f,0xad,0x82,0xac,0x83,0x90,0x9e,0x2b,0xec,0xf0,0xa3,0xed,0xf0,0xef,
++0x75,0xf0,0x09,0xa4,0x24,0x44,0xf9,0x74,0x96,0x35,0xf0,0xfa,0x7b,0x01,0xa3,0x12,
++0x43,0x8b,0x90,0x9e,0x26,0x12,0x43,0x6b,0x90,0x00,0x03,0x12,0x42,0x20,0x54,0x0f,
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++0x6b,0x90,0x00,0x02,0x12,0x42,0x20,0xff,0x90,0x9e,0x2d,0x12,0x43,0x6b,0x90,0x00,
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++0x20,0xff,0x90,0x9e,0x2b,0xe0,0xfc,0xa3,0xe0,0xfd,0xf5,0x82,0x8c,0x83,0xef,0xf0,
++0x12,0x29,0xd9,0x8d,0x82,0x8c,0x83,0xa3,0xf0,0x90,0x9e,0x29,0xe0,0xfe,0x90,0x9e,
++0x24,0xe0,0xff,0x24,0x82,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xee,0xf0,0x90,0x9e,
++0x25,0xe0,0xfe,0x75,0xf0,0x09,0xef,0x90,0x96,0x4a,0x12,0x43,0x5f,0xee,0xf0,0x75,
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++0x25,0xe0,0x24,0xc6,0xf5,0x82,0xe4,0x34,0x9b,0xaf,0x82,0xf5,0x16,0x8f,0x17,0xe5,
++0x14,0x75,0xf0,0x02,0xa4,0x24,0x02,0xf9,0x74,0x95,0x35,0xf0,0x75,0x18,0x01,0xf5,
++0x19,0x89,0x1a,0x75,0xf0,0x09,0xe5,0x14,0x90,0x96,0x46,0x12,0x43,0x5f,0xaf,0x82,
++0x85,0x83,0x1b,0x8f,0x1c,0xe5,0x14,0x75,0xf0,0x09,0xa4,0x24,0x44,0xf9,0x74,0x96,
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++0x34,0x95,0xf5,0x83,0xe0,0x12,0x43,0x94,0x5c,0x0d,0x00,0x5c,0x22,0x01,0x5c,0x37,
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++0x5c,0xf2,0x0d,0x5d,0x1f,0x0e,0x5d,0x4c,0x0f,0x00,0x00,0x5d,0x80,0xe5,0x14,0x25,
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++0x80,0x3c,0xe5,0x14,0x25,0xe0,0x24,0xc6,0xf5,0x82,0xe4,0x34,0x9b,0xf5,0x83,0x74,
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++0x34,0x9b,0xf5,0x83,0x74,0xf0,0xf0,0xa3,0x74,0x05,0x80,0x12,0xe5,0x14,0x25,0xe0,
++0x24,0xc6,0xf5,0x82,0xe4,0x34,0x9b,0xf5,0x83,0x74,0xf0,0xf0,0xa3,0xe4,0xf0,0xe5,
++0x14,0x25,0xe0,0x24,0x02,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0x74,0x0f,0xf0,0xa3,
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++0x14,0x25,0xe0,0x24,0xc6,0xf5,0x82,0xe4,0x34,0x9b,0xf5,0x83,0xe4,0xf0,0xa3,0x74,
++0x0d,0xf0,0xe5,0x14,0x25,0xe0,0x24,0x02,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xe4,
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++0x42,0x4d,0x90,0x04,0x46,0xe0,0xab,0x18,0xaa,0x19,0xa9,0x1a,0x90,0x00,0x01,0x12,
++0x42,0x5f,0x90,0x04,0x45,0xe0,0x85,0x17,0x82,0x85,0x16,0x83,0xf0,0x90,0x04,0x44,
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++0x04,0x49,0xe0,0x85,0x17,0x82,0x85,0x16,0x83,0xf0,0x90,0x04,0x48,0x80,0x58,0x90,
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++0xab,0x18,0xaa,0x19,0xa9,0x1a,0x90,0x00,0x01,0x12,0x42,0x5f,0x90,0x04,0x4d,0xe0,
++0x85,0x17,0x82,0x85,0x16,0x83,0xf0,0x90,0x04,0x4c,0x80,0x2b,0x90,0x04,0x53,0xe0,
++0xab,0x18,0xaa,0x19,0xa9,0x1a,0x12,0x42,0x4d,0x90,0x04,0x52,0xe0,0xab,0x18,0xaa,
++0x19,0xa9,0x1a,0x90,0x00,0x01,0x12,0x42,0x5f,0x90,0x04,0x51,0xe0,0x85,0x17,0x82,
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++0xab,0x18,0xaa,0x19,0xa9,0x1a,0xc0,0x03,0xc0,0x02,0xc0,0x01,0x12,0x29,0xd9,0xff,
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++0x12,0x42,0x4d,0xab,0x18,0xe5,0x1a,0x24,0x01,0xf9,0xe4,0x35,0x19,0xfa,0xc0,0x03,
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++0x82,0x85,0x16,0x83,0xc0,0x83,0xc0,0x82,0xe0,0xff,0x85,0x1c,0x82,0x85,0x1b,0x83,
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++0x95,0xf5,0x83,0xe0,0xfe,0xa3,0xe0,0x4e,0x60,0x3b,0x75,0x15,0x0b,0x74,0x01,0x7e,
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++0x25,0xe0,0x24,0x02,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xe0,0x5e,0xfe,0xa3,0xe0,
++0x5f,0x4e,0x60,0x06,0xe5,0x15,0x24,0x10,0x80,0x5d,0x15,0x15,0xe5,0x15,0xc3,0x94,
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++0xa8,0x15,0x08,0x80,0x05,0xc3,0x33,0xce,0x33,0xce,0xd8,0xf9,0xff,0xe5,0x14,0x25,
++0xe0,0x24,0xc6,0xf5,0x82,0xe4,0x34,0x9b,0xf5,0x83,0xe0,0x5e,0xfe,0xa3,0xe0,0x5f,
++0x4e,0x60,0x08,0x90,0x9e,0x30,0xe5,0x15,0xf0,0x80,0x10,0x15,0x15,0xe5,0x15,0xc3,
++0x94,0x00,0x50,0xc8,0x80,0x05,0xe4,0x90,0x9e,0x30,0xf0,0xe5,0x14,0x25,0xe0,0x24,
++0xc6,0xf5,0x82,0xe4,0x34,0x9b,0xf5,0x83,0xe0,0xfe,0xa3,0xe0,0x4e,0x60,0x3b,0xe4,
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++0x90,0x9e,0x4a,0xe0,0x70,0x19,0x90,0x9e,0x4d,0xe0,0x70,0x13,0x90,0x9e,0x4b,0xe0,
++0x70,0x0d,0x90,0x9e,0x4e,0xe0,0x70,0x07,0x90,0x04,0xfd,0xe0,0x54,0xfe,0xf0,0x90,
++0x9e,0x49,0xe0,0x90,0x04,0x44,0xf0,0x90,0x9e,0x4a,0xe0,0x90,0x04,0x45,0xf0,0x90,
++0x9e,0x4b,0xe0,0x90,0x04,0x46,0xf0,0xa3,0xe4,0xf0,0x90,0x9e,0x4c,0xe0,0x90,0x04,
++0x48,0xf0,0x90,0x9e,0x4d,0xe0,0x90,0x04,0x49,0xf0,0x90,0x9e,0x4e,0xe0,0x90,0x04,
++0x4a,0xf0,0xa3,0xe4,0xf0,0x90,0x9e,0x35,0xe0,0x90,0x04,0x4c,0xf0,0x90,0x9e,0x36,
++0xe0,0x90,0x04,0x4d,0xf0,0x90,0x9e,0x37,0xe0,0x90,0x04,0x4e,0xf0,0x90,0x9e,0x38,
++0xe0,0x90,0x04,0x4f,0xf0,0xe4,0x90,0x9e,0x3a,0xf0,0x90,0x9e,0x35,0x04,0xf0,0xe4,
++0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0x90,0x9e,0x49,0xf0,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,
++0xa3,0xf0,0xa3,0xf0,0x90,0x05,0x60,0xe0,0x90,0x9e,0x19,0xf0,0x90,0x05,0x61,0xe0,
++0x90,0x9e,0x1a,0xf0,0x90,0x05,0x62,0xe0,0x90,0x9e,0x1b,0xf0,0x90,0x05,0x63,0xe0,
++0x90,0x9e,0x1c,0xf0,0x90,0x9e,0x52,0xe0,0xff,0x90,0x9e,0x1c,0xe0,0xfe,0xd3,0x9f,
++0x50,0x0b,0x90,0x9e,0x52,0xe0,0xc3,0x9e,0xd3,0x94,0x01,0x40,0x11,0x90,0x9e,0x40,
++0xe0,0xb4,0x01,0x02,0x80,0x03,0x90,0x9e,0x44,0xe0,0xff,0x12,0x4c,0xf0,0x22,0x90,
++0x9e,0x53,0xe0,0x64,0x01,0x60,0x08,0x90,0x9e,0x41,0xe0,0x60,0x02,0xa1,0x36,0x90,
++0x9e,0x35,0xe0,0xc3,0x94,0xff,0x50,0x05,0xe0,0x04,0xf0,0x80,0x3b,0x90,0x9e,0x36,
++0xe0,0xc3,0x94,0xff,0x50,0x06,0xe0,0x04,0xf0,0xe4,0x80,0x28,0x90,0x9e,0x37,0xe0,
++0xc3,0x94,0xff,0x50,0x0a,0xe0,0x04,0xf0,0xe4,0x90,0x9e,0x36,0xf0,0x80,0x15,0x90,
++0x9e,0x38,0xe0,0xc3,0x94,0xff,0x50,0x10,0xe0,0x04,0xf0,0xe4,0x90,0x9e,0x37,0xf0,
++0x90,0x9e,0x36,0xf0,0x90,0x9e,0x35,0xf0,0x90,0x00,0x44,0xe0,0x54,0x0c,0x60,0x76,
++0xe0,0x30,0xe2,0x32,0x90,0x9e,0x49,0xe0,0xc3,0x94,0xff,0x50,0x05,0xe0,0x04,0xf0,
++0x80,0x24,0x90,0x9e,0x4a,0xe0,0xc3,0x94,0xff,0x50,0x06,0xe0,0x04,0xf0,0xe4,0x80,
++0x11,0x90,0x9e,0x4b,0xe0,0xc3,0x94,0xff,0x50,0x0c,0xe0,0x04,0xf0,0xe4,0x90,0x9e,
++0x4a,0xf0,0x90,0x9e,0x49,0xf0,0x90,0x00,0x44,0xe0,0x30,0xe3,0x32,0x90,0x9e,0x4c,
++0xe0,0xc3,0x94,0xff,0x50,0x05,0xe0,0x04,0xf0,0x80,0x24,0x90,0x9e,0x4d,0xe0,0xc3,
++0x94,0xff,0x50,0x06,0xe0,0x04,0xf0,0xe4,0x80,0x11,0x90,0x9e,0x4e,0xe0,0xc3,0x94,
++0xff,0x50,0x0c,0xe0,0x04,0xf0,0xe4,0x90,0x9e,0x4d,0xf0,0x90,0x9e,0x4c,0xf0,0x90,
++0x04,0xfd,0xe0,0x44,0x01,0xf0,0x22,0x00,0x37,0xda,};
++
++// =================== v79 UMC A Cut COMMON 2011-10-06 =====================
++u8 Rtl8192CUFwUMCACutImgArray[UMCACutImgArrayLength] = {
++0xc1,0x88,0x02,0x00,0x4f,0x00,0x00,0x00,0x0a,0x06,0x18,0x09,0x58,0x3f,0x01,0x00,
++0x61,0x80,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x02,0x43,0xba,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x02,0x5a,0x45,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x02,0x5f,0xfb,0x00,0x00,0x00,0x00,0x00,0xa1,0xdf,0x00,0x00,0x00,
++0x05,0x04,0x03,0x02,0x00,0x03,0x06,0x05,0x04,0x03,0x00,0x04,0x06,0x05,0x04,0x02,
++0x00,0x04,0x08,0x07,0x06,0x04,0x00,0x06,0x0a,0x09,0x08,0x06,0x00,0x08,0x0a,0x09,
++0x08,0x04,0x00,0x08,0x0a,0x09,0x08,0x02,0x00,0x08,0x0a,0x09,0x08,0x00,0x00,0x08,
++0x12,0x11,0x10,0x08,0x00,0x10,0x1a,0x19,0x18,0x10,0x00,0x18,0x22,0x21,0x20,0x18,
++0x00,0x20,0x22,0x21,0x20,0x10,0x00,0x20,0x22,0x21,0x20,0x08,0x00,0x20,0x22,0x21,
++0x1c,0x08,0x00,0x20,0x22,0x21,0x14,0x08,0x00,0x20,0x22,0x20,0x18,0x08,0x00,0x20,
++0x31,0x30,0x20,0x10,0x00,0x30,0x31,0x30,0x18,0x00,0x00,0x30,0x31,0x2f,0x10,0x10,
++0x00,0x30,0x31,0x2c,0x10,0x10,0x00,0x30,0x31,0x28,0x10,0x00,0x00,0x30,0x31,0x20,
++0x10,0x00,0x00,0x30,0x31,0x10,0x10,0x00,0x00,0x30,0x04,0x04,0x04,0x05,0x04,0x04,
++0x04,0x05,0x05,0x05,0x06,0x06,0x04,0x04,0x04,0x05,0x05,0x05,0x06,0x06,0x04,0x04,
++0x05,0x05,0x05,0x05,0x06,0x06,0x04,0x04,0x05,0x05,0x05,0x05,0x06,0x07,0x0a,0x0b,
++0x0d,0x10,0x04,0x05,0x05,0x06,0x06,0x09,0x0c,0x11,0x08,0x08,0x09,0x09,0x0a,0x0c,
++0x10,0x11,0x04,0x04,0x04,0x05,0x04,0x04,0x05,0x07,0x07,0x07,0x08,0x0a,0x04,0x04,
++0x04,0x04,0x06,0x0a,0x0b,0x0d,0x05,0x05,0x07,0x07,0x08,0x0b,0x0d,0x0f,0x04,0x04,
++0x04,0x05,0x07,0x07,0x09,0x09,0x0c,0x0e,0x10,0x12,0x04,0x04,0x05,0x05,0x06,0x0a,
++0x11,0x13,0x09,0x09,0x09,0x09,0x0c,0x0e,0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x24,0x26,0x2a,0x18,0x1a,0x1d,0x1f,0x21,0x27,0x29,0x2a,0x00,0x00,
++0x00,0x1f,0x23,0x28,0x2a,0x2c,0x00,0x04,0x00,0x04,0x00,0x08,0x00,0x10,0x00,0x18,
++0x00,0x24,0x00,0x30,0x00,0x48,0x00,0x60,0x00,0x90,0x00,0xc0,0x00,0xd8,0x00,0x50,
++0x00,0x78,0x00,0xa0,0x00,0xc8,0x01,0x40,0x01,0x90,0x01,0xe0,0x02,0x30,0x01,0x2c,
++0x01,0x40,0x01,0xe0,0x02,0xd0,0x03,0xe8,0x04,0xb0,0x06,0x40,0x07,0xd0,0x00,0x02,
++0x00,0x02,0x00,0x04,0x00,0x08,0x00,0x0c,0x00,0x12,0x00,0x18,0x00,0x24,0x00,0x30,
++0x00,0x48,0x00,0x60,0x00,0x6c,0x00,0x28,0x00,0x3c,0x00,0x50,0x00,0x64,0x00,0xa0,
++0x00,0xc8,0x00,0xf0,0x01,0x18,0x00,0x64,0x00,0xa0,0x00,0xf0,0x01,0x68,0x01,0xf4,
++0x02,0x58,0x03,0x20,0x03,0xe8,0x02,0x02,0x02,0x02,0x02,0x02,0x03,0x03,0x04,0x04,
++0x05,0x07,0x04,0x04,0x07,0x0a,0x0a,0x0c,0x0c,0x12,0x05,0x07,0x07,0x08,0x0b,0x12,
++0x24,0x3c,0x01,0x01,0x01,0x01,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x01,0x02,
++0x03,0x04,0x05,0x06,0x07,0x08,0x05,0x06,0x07,0x08,0x09,0x0a,0x0b,0x0c,0x20,0x1e,
++0x1c,0x18,0x10,0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0xbb,0x01,0x0c,0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe0,0x22,0x50,
++0x06,0xe9,0x25,0x82,0xf8,0xe6,0x22,0xbb,0xfe,0x06,0xe9,0x25,0x82,0xf8,0xe2,0x22,
++0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe4,0x93,0x22,0xbb,0x01,0x06,
++0x89,0x82,0x8a,0x83,0xf0,0x22,0x50,0x02,0xf7,0x22,0xbb,0xfe,0x01,0xf3,0x22,0xf8,
++0xbb,0x01,0x0d,0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe8,0xf0,0x22,
++0x50,0x06,0xe9,0x25,0x82,0xc8,0xf6,0x22,0xbb,0xfe,0x05,0xe9,0x25,0x82,0xc8,0xf2,
++0x22,0xc5,0xf0,0xf8,0xa3,0xe0,0x28,0xf0,0xc5,0xf0,0xf8,0xe5,0x82,0x15,0x82,0x70,
++0x02,0x15,0x83,0xe0,0x38,0xf0,0x22,0xbb,0x01,0x0a,0x89,0x82,0x8a,0x83,0xe0,0xf5,
++0xf0,0xa3,0xe0,0x22,0x50,0x06,0x87,0xf0,0x09,0xe7,0x19,0x22,0xbb,0xfe,0x07,0xe3,
++0xf5,0xf0,0x09,0xe3,0x19,0x22,0x89,0x82,0x8a,0x83,0xe4,0x93,0xf5,0xf0,0x74,0x01,
++0x93,0x22,0xbb,0x01,0x10,0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe0,
++0xf5,0xf0,0xa3,0xe0,0x22,0x50,0x09,0xe9,0x25,0x82,0xf8,0x86,0xf0,0x08,0xe6,0x22,
++0xbb,0xfe,0x0a,0xe9,0x25,0x82,0xf8,0xe2,0xf5,0xf0,0x08,0xe2,0x22,0xe5,0x83,0x2a,
++0xf5,0x83,0xe9,0x93,0xf5,0xf0,0xa3,0xe9,0x93,0x22,0xbb,0x01,0x0a,0x89,0x82,0x8a,
++0x83,0xf0,0xe5,0xf0,0xa3,0xf0,0x22,0x50,0x06,0xf7,0x09,0xa7,0xf0,0x19,0x22,0xbb,
++0xfe,0x06,0xf3,0xe5,0xf0,0x09,0xf3,0x19,0x22,0xf8,0xbb,0x01,0x11,0xe5,0x82,0x29,
++0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe8,0xf0,0xe5,0xf0,0xa3,0xf0,0x22,0x50,0x09,
++0xe9,0x25,0x82,0xc8,0xf6,0x08,0xa6,0xf0,0x22,0xbb,0xfe,0x09,0xe9,0x25,0x82,0xc8,
++0xf2,0xe5,0xf0,0x08,0xf2,0x22,0xef,0x4b,0xff,0xee,0x4a,0xfe,0xed,0x49,0xfd,0xec,
++0x48,0xfc,0x22,0xe0,0xfc,0xa3,0xe0,0xfd,0xa3,0xe0,0xfe,0xa3,0xe0,0xff,0x22,0xa4,
++0x25,0x82,0xf5,0x82,0xe5,0xf0,0x35,0x83,0xf5,0x83,0x22,0xe0,0xfb,0xa3,0xe0,0xfa,
++0xa3,0xe0,0xf9,0x22,0xf8,0xe0,0xfb,0xa3,0xa3,0xe0,0xf9,0x25,0xf0,0xf0,0xe5,0x82,
++0x15,0x82,0x70,0x02,0x15,0x83,0xe0,0xfa,0x38,0xf0,0x22,0xeb,0xf0,0xa3,0xea,0xf0,
++0xa3,0xe9,0xf0,0x22,0xd0,0x83,0xd0,0x82,0xf8,0xe4,0x93,0x70,0x12,0x74,0x01,0x93,
++0x70,0x0d,0xa3,0xa3,0x93,0xf8,0x74,0x01,0x93,0xf5,0x82,0x88,0x83,0xe4,0x73,0x74,
++0x02,0x93,0x68,0x60,0xef,0xa3,0xa3,0xa3,0x80,0xdf,0x02,0x43,0xf8,0x02,0x50,0xa9,
++0xe4,0x93,0xa3,0xf8,0xe4,0x93,0xa3,0x40,0x03,0xf6,0x80,0x01,0xf2,0x08,0xdf,0xf4,
++0x80,0x29,0xe4,0x93,0xa3,0xf8,0x54,0x07,0x24,0x0c,0xc8,0xc3,0x33,0xc4,0x54,0x0f,
++0x44,0x20,0xc8,0x83,0x40,0x04,0xf4,0x56,0x80,0x01,0x46,0xf6,0xdf,0xe4,0x80,0x0b,
++0x01,0x02,0x04,0x08,0x10,0x20,0x40,0x80,0x90,0x44,0x3d,0xe4,0x7e,0x01,0x93,0x60,
++0xbc,0xa3,0xff,0x54,0x3f,0x30,0xe5,0x09,0x54,0x1f,0xfe,0xe4,0x93,0xa3,0x60,0x01,
++0x0e,0xcf,0x54,0xc0,0x25,0xe0,0x60,0xa8,0x40,0xb8,0xe4,0x93,0xa3,0xfa,0xe4,0x93,
++0xa3,0xf8,0xe4,0x93,0xa3,0xc8,0xc5,0x82,0xc8,0xca,0xc5,0x83,0xca,0xf0,0xa3,0xc8,
++0xc5,0x82,0xc8,0xca,0xc5,0x83,0xca,0xdf,0xe9,0xde,0xe7,0x80,0xbe,0x41,0x9e,0x66,
++0x00,0x41,0x9e,0xae,0x00,0x41,0x9e,0x4d,0x80,0x41,0x9e,0x4e,0x80,0x41,0x9e,0xb0,
++0x00,0x00,0xf0,0x90,0x9e,0x57,0xe0,0x90,0x9e,0x8a,0xf0,0xe4,0xfb,0xfd,0x7f,0x54,
++0x7e,0x01,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x90,0x9e,0x88,0xeb,0xf0,0xa3,0xe0,
++0xfb,0xa3,0xe0,0xf5,0x44,0xe4,0xf5,0x45,0x12,0x30,0x62,0xd0,0xd0,0x92,0xaf,0x22,
++0x90,0x01,0x5f,0xe4,0xf0,0x90,0x01,0x3c,0x74,0x08,0xf0,0xe4,0x90,0x9e,0x89,0xf0,
++0x90,0x9e,0x55,0xe0,0x90,0x9e,0x8a,0xf0,0xe4,0xfb,0xfd,0x7f,0x5c,0x7e,0x01,0x91,
++0x62,0x90,0x01,0x5f,0x74,0x05,0xf0,0x90,0x06,0x92,0x74,0x02,0xf0,0x90,0x9e,0x5c,
++0x14,0xf0,0x90,0x9e,0x5e,0xe0,0x54,0x0f,0xc3,0x94,0x0c,0x50,0x02,0xf1,0x16,0x22,
++0x8f,0x82,0x8e,0x83,0xa3,0xa3,0xa3,0xe4,0xf0,0x22,0xe4,0xf5,0x22,0x7f,0x60,0x7e,
++0x01,0x80,0xed,0x90,0x9e,0x60,0xe0,0xff,0x7d,0x01,0xe1,0x1a,0xb1,0xb1,0xbf,0x01,
++0x0f,0x90,0x9e,0x68,0xe0,0xff,0xe4,0xfd,0xf1,0xfe,0x90,0x04,0x1f,0x74,0x20,0xf0,
++0x22,0x90,0x01,0xca,0xe5,0x25,0xf0,0xef,0x60,0x03,0x12,0x4f,0x2a,0x22,0x22,0x22,
++0x22,0x22,0x00,0x02,0x60,0x8d,0x02,0x60,0x94,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,
++0x8b,0x1b,0x8a,0x1c,0x89,0x1d,0x90,0x9e,0x8b,0x71,0x8b,0xab,0x1e,0xaa,0x1f,0xa9,
++0x20,0x90,0x9e,0x8e,0x71,0x8b,0xaf,0x21,0x15,0x21,0xef,0x60,0x1b,0x90,0x9e,0x8e,
++0xe4,0x75,0xf0,0x01,0x71,0x74,0x12,0x24,0x62,0xff,0x90,0x9e,0x8b,0xe4,0x75,0xf0,
++0x01,0x71,0x74,0xef,0x51,0x4d,0x80,0xde,0xab,0x1b,0xaa,0x1c,0xa9,0x1d,0xd0,0xd0,
++0x92,0xaf,0x22,0x90,0x06,0xa9,0xe0,0xf5,0x50,0x54,0xc0,0x70,0x0d,0x90,0x9e,0x63,
++0xe0,0x54,0xfe,0xf0,0xe0,0x54,0xfd,0xf0,0x91,0xd3,0xe5,0x50,0x30,0xe6,0x17,0x90,
++0x9e,0x63,0xe0,0x44,0x01,0xf0,0x90,0x9e,0x61,0xe0,0x64,0x02,0x60,0x04,0x91,0xdc,
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++0x9e,0x3f,0xe0,0xff,0x24,0x82,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xee,0xf0,0x90,
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++0xff,0x50,0x06,0xe0,0x04,0xf0,0xe4,0x80,0x11,0x90,0x9e,0x29,0xe0,0xc3,0x94,0xff,
++0x50,0x0c,0xe0,0x04,0xf0,0xe4,0x90,0x9e,0x28,0xf0,0x90,0x9e,0x27,0xf0,0x90,0x04,
++0xfd,0xe0,0x44,0x01,0xf0,0x22,0xf5,0x67,};
++
++// =================== v84 UMC B Cut COMMON 2012-04-13 =====================
++u8 Rtl8192CUFwUMCBCutImgArray[UMCBCutImgArrayLength] = {
++0xc2,0x88,0x02,0x00,0x54,0x00,0x01,0x00,0x04,0x13,0x11,0x08,0x26,0x3d,0x01,0x00,
++0x58,0x97,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x02,0x43,0xba,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x02,0x50,0xa1,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x02,0x57,0x91,0x00,0x00,0x00,0x00,0x00,0xa1,0xe8,0x00,0x00,0x00,
++0x05,0x04,0x03,0x02,0x00,0x03,0x06,0x05,0x04,0x03,0x00,0x04,0x06,0x05,0x04,0x02,
++0x00,0x04,0x08,0x07,0x06,0x04,0x00,0x06,0x0a,0x09,0x08,0x06,0x00,0x08,0x0a,0x09,
++0x08,0x04,0x00,0x08,0x0a,0x09,0x08,0x02,0x00,0x08,0x0a,0x09,0x08,0x00,0x00,0x08,
++0x12,0x11,0x10,0x08,0x00,0x10,0x1a,0x19,0x18,0x10,0x00,0x18,0x22,0x21,0x20,0x18,
++0x00,0x20,0x22,0x21,0x20,0x10,0x00,0x20,0x22,0x21,0x20,0x08,0x00,0x20,0x22,0x21,
++0x1c,0x08,0x00,0x20,0x22,0x21,0x14,0x08,0x00,0x20,0x22,0x20,0x18,0x08,0x00,0x20,
++0x31,0x30,0x20,0x10,0x00,0x30,0x31,0x30,0x18,0x00,0x00,0x30,0x31,0x2f,0x10,0x10,
++0x00,0x30,0x31,0x2c,0x10,0x10,0x00,0x30,0x31,0x28,0x10,0x00,0x00,0x30,0x31,0x20,
++0x10,0x00,0x00,0x30,0x31,0x10,0x10,0x00,0x00,0x30,0x04,0x04,0x04,0x05,0x04,0x04,
++0x04,0x05,0x05,0x05,0x06,0x06,0x04,0x04,0x04,0x05,0x05,0x05,0x06,0x06,0x04,0x04,
++0x05,0x05,0x05,0x05,0x06,0x06,0x04,0x04,0x05,0x05,0x05,0x05,0x06,0x07,0x0a,0x0b,
++0x0d,0x10,0x04,0x05,0x05,0x06,0x06,0x09,0x0c,0x11,0x08,0x08,0x09,0x09,0x0a,0x0c,
++0x10,0x11,0x04,0x04,0x04,0x05,0x04,0x04,0x05,0x07,0x07,0x07,0x08,0x0a,0x04,0x04,
++0x04,0x04,0x06,0x0a,0x0b,0x0d,0x05,0x05,0x07,0x07,0x08,0x0b,0x0d,0x0f,0x04,0x04,
++0x04,0x05,0x07,0x07,0x09,0x09,0x0c,0x0e,0x10,0x12,0x04,0x04,0x05,0x05,0x06,0x0a,
++0x11,0x13,0x09,0x09,0x09,0x09,0x0c,0x0e,0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x24,0x26,0x2a,0x18,0x1a,0x1d,0x1f,0x21,0x27,0x29,0x2a,0x00,0x00,
++0x00,0x1f,0x23,0x28,0x2a,0x2c,0x00,0x04,0x00,0x04,0x00,0x08,0x00,0x10,0x00,0x18,
++0x00,0x24,0x00,0x30,0x00,0x48,0x00,0x60,0x00,0x90,0x00,0xc0,0x00,0xd8,0x00,0x50,
++0x00,0x78,0x00,0xa0,0x00,0xc8,0x01,0x40,0x01,0x90,0x01,0xe0,0x02,0x30,0x01,0x2c,
++0x01,0x40,0x01,0xe0,0x02,0xd0,0x03,0xe8,0x04,0xb0,0x06,0x40,0x07,0xd0,0x00,0x02,
++0x00,0x02,0x00,0x04,0x00,0x08,0x00,0x0c,0x00,0x12,0x00,0x18,0x00,0x24,0x00,0x30,
++0x00,0x48,0x00,0x60,0x00,0x6c,0x00,0x28,0x00,0x3c,0x00,0x50,0x00,0x64,0x00,0xa0,
++0x00,0xc8,0x00,0xf0,0x01,0x18,0x00,0x64,0x00,0xa0,0x00,0xf0,0x01,0x68,0x01,0xf4,
++0x02,0x58,0x03,0x20,0x03,0xe8,0x02,0x02,0x02,0x02,0x02,0x02,0x03,0x03,0x04,0x04,
++0x05,0x07,0x04,0x04,0x07,0x0a,0x0a,0x0c,0x0c,0x12,0x05,0x07,0x07,0x08,0x0b,0x12,
++0x24,0x3c,0x01,0x01,0x01,0x01,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x01,0x02,
++0x03,0x04,0x05,0x06,0x07,0x08,0x05,0x06,0x07,0x08,0x09,0x0a,0x0b,0x0c,0x20,0x1e,
++0x1c,0x18,0x10,0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0xbb,0x01,0x0c,0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe0,0x22,0x50,
++0x06,0xe9,0x25,0x82,0xf8,0xe6,0x22,0xbb,0xfe,0x06,0xe9,0x25,0x82,0xf8,0xe2,0x22,
++0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe4,0x93,0x22,0xbb,0x01,0x06,
++0x89,0x82,0x8a,0x83,0xf0,0x22,0x50,0x02,0xf7,0x22,0xbb,0xfe,0x01,0xf3,0x22,0xf8,
++0xbb,0x01,0x0d,0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe8,0xf0,0x22,
++0x50,0x06,0xe9,0x25,0x82,0xc8,0xf6,0x22,0xbb,0xfe,0x05,0xe9,0x25,0x82,0xc8,0xf2,
++0x22,0xc5,0xf0,0xf8,0xa3,0xe0,0x28,0xf0,0xc5,0xf0,0xf8,0xe5,0x82,0x15,0x82,0x70,
++0x02,0x15,0x83,0xe0,0x38,0xf0,0x22,0xbb,0x01,0x0a,0x89,0x82,0x8a,0x83,0xe0,0xf5,
++0xf0,0xa3,0xe0,0x22,0x50,0x06,0x87,0xf0,0x09,0xe7,0x19,0x22,0xbb,0xfe,0x07,0xe3,
++0xf5,0xf0,0x09,0xe3,0x19,0x22,0x89,0x82,0x8a,0x83,0xe4,0x93,0xf5,0xf0,0x74,0x01,
++0x93,0x22,0xbb,0x01,0x10,0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe0,
++0xf5,0xf0,0xa3,0xe0,0x22,0x50,0x09,0xe9,0x25,0x82,0xf8,0x86,0xf0,0x08,0xe6,0x22,
++0xbb,0xfe,0x0a,0xe9,0x25,0x82,0xf8,0xe2,0xf5,0xf0,0x08,0xe2,0x22,0xe5,0x83,0x2a,
++0xf5,0x83,0xe9,0x93,0xf5,0xf0,0xa3,0xe9,0x93,0x22,0xbb,0x01,0x0a,0x89,0x82,0x8a,
++0x83,0xf0,0xe5,0xf0,0xa3,0xf0,0x22,0x50,0x06,0xf7,0x09,0xa7,0xf0,0x19,0x22,0xbb,
++0xfe,0x06,0xf3,0xe5,0xf0,0x09,0xf3,0x19,0x22,0xf8,0xbb,0x01,0x11,0xe5,0x82,0x29,
++0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe8,0xf0,0xe5,0xf0,0xa3,0xf0,0x22,0x50,0x09,
++0xe9,0x25,0x82,0xc8,0xf6,0x08,0xa6,0xf0,0x22,0xbb,0xfe,0x09,0xe9,0x25,0x82,0xc8,
++0xf2,0xe5,0xf0,0x08,0xf2,0x22,0xef,0x4b,0xff,0xee,0x4a,0xfe,0xed,0x49,0xfd,0xec,
++0x48,0xfc,0x22,0xe0,0xfc,0xa3,0xe0,0xfd,0xa3,0xe0,0xfe,0xa3,0xe0,0xff,0x22,0xa4,
++0x25,0x82,0xf5,0x82,0xe5,0xf0,0x35,0x83,0xf5,0x83,0x22,0xe0,0xfb,0xa3,0xe0,0xfa,
++0xa3,0xe0,0xf9,0x22,0xf8,0xe0,0xfb,0xa3,0xa3,0xe0,0xf9,0x25,0xf0,0xf0,0xe5,0x82,
++0x15,0x82,0x70,0x02,0x15,0x83,0xe0,0xfa,0x38,0xf0,0x22,0xeb,0xf0,0xa3,0xea,0xf0,
++0xa3,0xe9,0xf0,0x22,0xd0,0x83,0xd0,0x82,0xf8,0xe4,0x93,0x70,0x12,0x74,0x01,0x93,
++0x70,0x0d,0xa3,0xa3,0x93,0xf8,0x74,0x01,0x93,0xf5,0x82,0x88,0x83,0xe4,0x73,0x74,
++0x02,0x93,0x68,0x60,0xef,0xa3,0xa3,0xa3,0x80,0xdf,0x02,0x43,0xf8,0x02,0x48,0x29,
++0xe4,0x93,0xa3,0xf8,0xe4,0x93,0xa3,0x40,0x03,0xf6,0x80,0x01,0xf2,0x08,0xdf,0xf4,
++0x80,0x29,0xe4,0x93,0xa3,0xf8,0x54,0x07,0x24,0x0c,0xc8,0xc3,0x33,0xc4,0x54,0x0f,
++0x44,0x20,0xc8,0x83,0x40,0x04,0xf4,0x56,0x80,0x01,0x46,0xf6,0xdf,0xe4,0x80,0x0b,
++0x01,0x02,0x04,0x08,0x10,0x20,0x40,0x80,0x90,0x44,0x3d,0xe4,0x7e,0x01,0x93,0x60,
++0xbc,0xa3,0xff,0x54,0x3f,0x30,0xe5,0x09,0x54,0x1f,0xfe,0xe4,0x93,0xa3,0x60,0x01,
++0x0e,0xcf,0x54,0xc0,0x25,0xe0,0x60,0xa8,0x40,0xb8,0xe4,0x93,0xa3,0xfa,0xe4,0x93,
++0xa3,0xf8,0xe4,0x93,0xa3,0xc8,0xc5,0x82,0xc8,0xca,0xc5,0x83,0xca,0xf0,0xa3,0xc8,
++0xc5,0x82,0xc8,0xca,0xc5,0x83,0xca,0xdf,0xe9,0xde,0xe7,0x80,0xbe,0x41,0x9e,0x77,
++0x00,0x41,0x9e,0xae,0x00,0x41,0x9e,0x54,0x80,0x41,0x9e,0xb0,0x00,0x00,0xf0,0x90,
++0x9e,0x5d,0xe0,0x90,0x9e,0x86,0xf0,0xe4,0xfb,0xfd,0x7f,0x54,0x7e,0x01,0xd3,0x10,
++0xaf,0x01,0xc3,0xc0,0xd0,0x90,0x9e,0x85,0xe0,0xfb,0xa3,0xe0,0xf5,0x44,0xe4,0xf5,
++0x45,0x12,0x35,0xab,0xd0,0xd0,0x92,0xaf,0x22,0x90,0x01,0x5f,0xe4,0xf0,0x90,0x01,
++0x3c,0x74,0x08,0xf0,0xe4,0x90,0x9e,0x85,0xf0,0x90,0x9e,0x5b,0xe0,0x90,0x9e,0x86,
++0xf0,0xe4,0xfb,0xfd,0x7f,0x5c,0x7e,0x01,0x91,0x5e,0x90,0x01,0x5f,0x74,0x05,0xf0,
++0x90,0x06,0x92,0x74,0x02,0xf0,0x90,0x9e,0x63,0x14,0xf0,0xe5,0x61,0x54,0x0f,0xc3,
++0x94,0x0c,0x50,0x03,0x12,0x54,0xe3,0x22,0x8f,0x82,0x8e,0x83,0xa3,0xa3,0xa3,0xe4,
++0xf0,0x22,0xe4,0xf5,0x65,0x7f,0x60,0x7e,0x01,0x80,0xed,0x7d,0x01,0xaf,0x62,0x02,
++0x54,0xe7,0xb1,0xb0,0xbf,0x01,0x12,0x90,0x9e,0x79,0xe0,0xff,0xe4,0xfd,0xf1,0x79,
++0x12,0x5f,0xf7,0x90,0x04,0x1f,0x74,0x20,0xf0,0x22,0xb1,0xb0,0xbf,0x01,0x0f,0x90,
++0x02,0x09,0xe0,0xff,0x7d,0x01,0xf1,0x79,0x90,0x04,0x1f,0x74,0x20,0xf0,0x22,0x22,
++0x22,0x22,0x00,0x02,0x45,0x03,0x02,0x45,0x06,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,
++0x8b,0x20,0x8a,0x21,0x89,0x22,0x90,0x9e,0x87,0x71,0x8b,0xab,0x23,0xaa,0x24,0xa9,
++0x25,0x90,0x9e,0x8a,0x71,0x8b,0xaf,0x26,0x15,0x26,0xef,0x60,0x1b,0x90,0x9e,0x8a,
++0xe4,0x75,0xf0,0x01,0x71,0x74,0x12,0x29,0xd9,0xff,0x90,0x9e,0x87,0xe4,0x75,0xf0,
++0x01,0x71,0x74,0xef,0x51,0x4d,0x80,0xde,0xab,0x20,0xaa,0x21,0xa9,0x22,0xd0,0xd0,
++0x92,0xaf,0x22,0x90,0x9e,0x11,0x12,0x2a,0x8b,0x00,0x00,0x00,0x00,0x90,0x06,0xa9,
++0xe0,0x90,0x9e,0x10,0xf0,0xe0,0x54,0xc0,0x70,0x08,0x53,0x64,0xfe,0x53,0x64,0xfd,
++0x91,0xcb,0x90,0x9e,0x10,0xe0,0x30,0xe6,0x13,0x43,0x64,0x01,0x90,0x9e,0x66,0xe0,
++0x64,0x02,0x60,0x04,0x91,0xd2,0x80,0x07,0x91,0x79,0x80,0x03,0x53,0x64,0xfe,0x90,
++0x9e,0x10,0xe0,0x30,0xe7,0x16,0x43,0x64,0x02,0xe4,0x90,0x9e,0x85,0x91,0x4e,0x90,
++0x01,0x57,0x74,0x05,0xf0,0x90,0x9e,0x67,0x74,0x01,0xf0,0x22,0x53,0x64,0xfd,0x22,
++0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x90,0x01,0xc4,0x74,0xb0,0xf0,0x74,0x45,0xa3,
++0xf0,0x90,0x04,0x1d,0xe0,0x60,0x1a,0x90,0x05,0x22,0xe0,0x54,0x90,0x60,0x07,0x90,
++0x01,0xc6,0xe0,0x44,0x40,0xf0,0x90,0x01,0xc7,0xe0,0x30,0xe1,0xe4,0x7f,0x00,0x80,
++0x02,0x7f,0x01,0xd0,0xd0,0x92,0xaf,0x22,0xc0,0xe0,0xc0,0xf0,0xc0,0x83,0xc0,0x82,
++0xc0,0xd0,0x75,0xd0,0x00,0xc0,0x00,0xc0,0x01,0xc0,0x02,0xc0,0x03,0xc0,0x04,0xc0,
++0x05,0xc0,0x06,0xc0,0x07,0x75,0x13,0x00,0x90,0x01,0xc4,0x74,0xe8,0xf0,0x74,0x45,
++0xa3,0xf0,0x53,0x91,0xdf,0x90,0x01,0x3c,0xe0,0x55,0x30,0xf5,0x34,0xa3,0xe0,0x55,
++0x31,0xf5,0x35,0xa3,0xe0,0x55,0x32,0xf5,0x36,0xa3,0xe0,0x55,0x33,0xf5,0x37,0xe5,
++0x34,0x30,0xe0,0x06,0x90,0x01,0x3c,0x74,0x01,0xf0,0xe5,0x34,0x30,0xe1,0x09,0x90,
++0x01,0x3c,0x74,0x02,0xf0,0x12,0x61,0xc9,0xe5,0x34,0x30,0xe2,0x38,0x90,0x01,0x3c,
++0x74,0x04,0xf0,0x90,0x06,0x92,0xe0,0x30,0xe0,0x24,0x90,0x9e,0x85,0xe4,0xf0,0x90,
++0x9e,0x5b,0xe0,0x90,0x9e,0x86,0xf0,0xe4,0xfb,0xfd,0x7f,0x58,0x7e,0x01,0x91,0x5e,
++0x90,0x01,0x5b,0x74,0x05,0xf0,0x90,0x06,0x92,0x74,0x01,0xf0,0x80,0x07,0x90,0x9e,
++0x64,0xe4,0xf0,0x91,0xcb,0xe5,0x34,0x30,0xe3,0x38,0x90,0x01,0x3c,0x74,0x08,0xf0,
++0x90,0x06,0x92,0xe0,0x30,0xe1,0x24,0x90,0x9e,0x85,0xe4,0xf0,0x90,0x9e,0x5b,0xe0,
++0x90,0x9e,0x86,0xf0,0xe4,0xfb,0xfd,0x7f,0x5c,0x7e,0x01,0x91,0x5e,0x90,0x01,0x5f,
++0x74,0x05,0xf0,0x90,0x06,0x92,0x74,0x02,0xf0,0x80,0x07,0x90,0x9e,0x63,0xe4,0xf0,
++0x91,0xcb,0xe5,0x34,0x30,0xe4,0x09,0x90,0x01,0x3c,0x74,0x10,0xf0,0x12,0x4b,0xfb,
++0xe5,0x34,0x30,0xe5,0x09,0x90,0x01,0x3c,0x74,0x20,0xf0,0x12,0x4c,0x3d,0xe5,0x35,
++0x30,0xe0,0x44,0x90,0x01,0x3d,0x74,0x01,0xf0,0x90,0x01,0x2f,0xe0,0x44,0x7f,0xf0,
++0x90,0x00,0x83,0xe0,0x54,0x0f,0xf5,0x13,0xb4,0x01,0x02,0x80,0x1c,0xe5,0x13,0xb4,
++0x02,0x05,0x90,0x00,0x83,0x80,0x12,0xe5,0x13,0xb4,0x04,0x05,0x90,0x00,0x83,0x80,
++0x08,0xe5,0x13,0xb4,0x0c,0x06,0x90,0x00,0x83,0xe0,0xf5,0x62,0x90,0x01,0xbb,0xe5,
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++0x9e,0x98,0xe0,0x30,0xe0,0x09,0x90,0x9e,0x9a,0xe4,0xf0,0xa3,0x74,0x80,0xf0,0x90,
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++0xf0,0x90,0x9e,0x27,0xe0,0xfc,0xa3,0xe0,0xfd,0xec,0xfb,0x8d,0x44,0xe4,0xf5,0x45,
++0x7d,0x01,0x7f,0x60,0x7e,0x01,0x02,0x35,0xab,0x90,0x01,0xca,0xe5,0x68,0xf0,0xef,
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++0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x90,0x9e,0xb2,0xef,0xf0,0xd3,0x94,0x07,
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++0xff,0x90,0x00,0x46,0xb1,0x42,0x90,0x9e,0xb2,0xe0,0xfd,0x74,0x01,0x7e,0x00,0xa8,
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++0x07,0xb1,0x5d,0xef,0x60,0x26,0xb1,0xa5,0xe5,0x61,0x54,0x0f,0xff,0xbf,0x04,0x0c,
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++0x64,0x01,0x60,0x08,0x90,0x01,0xb9,0x74,0x01,0xf0,0x80,0x30,0x90,0x9e,0x64,0xe0,
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++0x40,0x2e,0x80,0x1f,0x90,0x96,0x43,0xe0,0xff,0xb4,0x01,0x0b,0x90,0x9e,0x1a,0xe0,
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++0x03,0x40,0x0d,0x90,0x9a,0x84,0x74,0x01,0xf0,0x80,0x05,0xe4,0x90,0x9a,0x84,0xf0,
++0x74,0x84,0x25,0x14,0xf5,0x82,0xe4,0x34,0x98,0xf5,0x83,0xe0,0xf5,0x1e,0x74,0x44,
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++0x90,0x80,0x85,0x12,0x2a,0x8b,0x20,0xdb,0x25,0xa4,0x7f,0xd8,0x7e,0x0e,0x12,0x2f,
++0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x00,0x1b,0x25,0xa4,0x7f,0xdc,0x7e,0x0e,0x12,
++0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x00,0x1b,0x25,0xa4,0x7f,0xe0,0x7e,0x0e,
++0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x24,0xdb,0x25,0xa4,0x7f,0xec,0x7e,
++0x0e,0x12,0x2f,0xd9,0x7f,0x04,0x7e,0x0c,0x12,0x27,0xde,0x90,0x9e,0xa8,0x12,0x2a,
++0x7f,0x90,0x9e,0xa8,0x12,0x43,0x53,0xe4,0xff,0xec,0x90,0x9e,0xa8,0x12,0x2a,0x7f,
++0x90,0x9e,0xa8,0x12,0x43,0x53,0xef,0x44,0x11,0xff,0xec,0x90,0x9e,0xa8,0x12,0x2a,
++0x7f,0x90,0x9e,0xa8,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x04,0x7e,
++0x0c,0x12,0x2f,0xd9,0x7f,0x04,0x7e,0x0d,0x12,0x27,0xde,0x90,0x9e,0xa8,0x12,0x2a,
++0x7f,0x90,0x9e,0xa8,0x12,0x43,0x53,0xef,0x54,0xf0,0xff,0xec,0x90,0x9e,0xa8,0x12,
++0x2a,0x7f,0x90,0x9e,0xa8,0x12,0x43,0x53,0xef,0x44,0x01,0xff,0xec,0x90,0x9e,0xa8,
++0x12,0x2a,0x7f,0x90,0x9e,0xa8,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,
++0x04,0x7e,0x0d,0x12,0x2f,0xd9,0x7f,0x0c,0x7e,0x09,0x12,0x27,0xde,0x90,0x9e,0xa8,
++0x12,0x2a,0x7f,0x90,0x9e,0xa8,0x12,0x43,0x53,0xe4,0xff,0xec,0x90,0x9e,0xa8,0x12,
++0x2a,0x7f,0x90,0x9e,0xa8,0x12,0x43,0x53,0xef,0x44,0x11,0xff,0xec,0x90,0x9e,0xa8,
++0x12,0x2a,0x7f,0x90,0x9e,0xa8,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,
++0x0c,0x7e,0x09,0x12,0x2f,0xd9,0x7f,0x0c,0x7e,0x09,0x12,0x27,0xde,0x90,0x9e,0xa8,
++0x12,0x2a,0x7f,0x90,0x9e,0xa8,0x12,0x43,0x53,0xed,0x54,0x0f,0xfd,0xec,0x54,0xf0,
++0xfc,0x90,0x9e,0xa8,0x12,0x2a,0x7f,0x90,0x9e,0xa8,0x12,0x43,0x53,0xed,0x44,0x10,
++0xfd,0xec,0x44,0x01,0xfc,0x90,0x9e,0xa8,0x12,0x2a,0x7f,0x90,0x9e,0xa8,0x12,0x43,
++0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x0c,0x7e,0x09,0x12,0x2f,0xd9,0x7f,0x04,
++0x7e,0x08,0x12,0x27,0xde,0x90,0x9e,0xa8,0x12,0x2a,0x7f,0x90,0x9e,0xa8,0x12,0x43,
++0x53,0xef,0x54,0xf0,0xff,0xec,0x90,0x9e,0xa8,0x12,0x2a,0x7f,0x90,0x9e,0xa8,0x12,
++0x43,0x53,0xef,0x44,0x01,0xff,0xec,0x90,0x9e,0xa8,0x12,0x2a,0x7f,0x90,0x9e,0xa8,
++0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x04,0x7e,0x08,0x12,0x2f,0xd9,
++0xe4,0x90,0x9e,0x0f,0xf0,0x22,0x90,0x00,0x02,0x12,0x42,0x20,0x90,0x9e,0x43,0xf0,
++0xe0,0x60,0x04,0xe0,0xf4,0x70,0x21,0xa2,0xaf,0xe4,0x33,0xf5,0x14,0xc2,0xaf,0x90,
++0x00,0x47,0xe0,0x54,0xfb,0xfd,0x7f,0x47,0x12,0x49,0x05,0x7d,0x40,0x7f,0x01,0x12,
++0x36,0xaf,0xe5,0x14,0x24,0xff,0x92,0xaf,0x22,0x90,0x9e,0x3a,0xe0,0xc3,0x94,0x14,
++0x50,0x05,0xe0,0x04,0xf0,0x81,0x01,0x90,0x9e,0x3a,0xe0,0x64,0x14,0x60,0x02,0x81,
++0x01,0x90,0x9e,0x49,0xe0,0x70,0x25,0x90,0x9e,0x4c,0xe0,0x70,0x1f,0x90,0x9e,0x4a,
++0xe0,0x70,0x19,0x90,0x9e,0x4d,0xe0,0x70,0x13,0x90,0x9e,0x4b,0xe0,0x70,0x0d,0x90,
++0x9e,0x4e,0xe0,0x70,0x07,0x90,0x04,0xfd,0xe0,0x54,0xfe,0xf0,0x90,0x9e,0x49,0xe0,
++0x90,0x04,0x44,0xf0,0x90,0x9e,0x4a,0xe0,0x90,0x04,0x45,0xf0,0x90,0x9e,0x4b,0xe0,
++0x90,0x04,0x46,0xf0,0xa3,0xe4,0xf0,0x90,0x9e,0x4c,0xe0,0x90,0x04,0x48,0xf0,0x90,
++0x9e,0x4d,0xe0,0x90,0x04,0x49,0xf0,0x90,0x9e,0x4e,0xe0,0x90,0x04,0x4a,0xf0,0xa3,
++0xe4,0xf0,0x90,0x9e,0x35,0xe0,0x90,0x04,0x4c,0xf0,0x90,0x9e,0x36,0xe0,0x90,0x04,
++0x4d,0xf0,0x90,0x9e,0x37,0xe0,0x90,0x04,0x4e,0xf0,0x90,0x9e,0x38,0xe0,0x90,0x04,
++0x4f,0xf0,0xe4,0x90,0x9e,0x3a,0xf0,0x90,0x9e,0x35,0x04,0xf0,0xe4,0xa3,0xf0,0xa3,
++0xf0,0xa3,0xf0,0x90,0x9e,0x49,0xf0,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0xa3,
++0xf0,0x90,0x05,0x60,0xe0,0x90,0x9e,0x19,0xf0,0x90,0x05,0x61,0xe0,0x90,0x9e,0x1a,
++0xf0,0x90,0x05,0x62,0xe0,0x90,0x9e,0x1b,0xf0,0x90,0x05,0x63,0xe0,0x90,0x9e,0x1c,
++0xf0,0x90,0x9e,0x52,0xe0,0xff,0x90,0x9e,0x1c,0xe0,0xfe,0xd3,0x9f,0x50,0x0b,0x90,
++0x9e,0x52,0xe0,0xc3,0x9e,0xd3,0x94,0x01,0x40,0x11,0x90,0x9e,0x40,0xe0,0xb4,0x01,
++0x02,0x80,0x03,0x90,0x9e,0x44,0xe0,0xff,0x12,0x4c,0xf0,0x22,0x90,0x9e,0x53,0xe0,
++0x64,0x01,0x60,0x08,0x90,0x9e,0x41,0xe0,0x60,0x02,0xa1,0x23,0x90,0x9e,0x35,0xe0,
++0xc3,0x94,0xff,0x50,0x05,0xe0,0x04,0xf0,0x80,0x3b,0x90,0x9e,0x36,0xe0,0xc3,0x94,
++0xff,0x50,0x06,0xe0,0x04,0xf0,0xe4,0x80,0x28,0x90,0x9e,0x37,0xe0,0xc3,0x94,0xff,
++0x50,0x0a,0xe0,0x04,0xf0,0xe4,0x90,0x9e,0x36,0xf0,0x80,0x15,0x90,0x9e,0x38,0xe0,
++0xc3,0x94,0xff,0x50,0x10,0xe0,0x04,0xf0,0xe4,0x90,0x9e,0x37,0xf0,0x90,0x9e,0x36,
++0xf0,0x90,0x9e,0x35,0xf0,0x90,0x00,0x44,0xe0,0x54,0x0c,0x60,0x76,0xe0,0x30,0xe2,
++0x32,0x90,0x9e,0x49,0xe0,0xc3,0x94,0xff,0x50,0x05,0xe0,0x04,0xf0,0x80,0x24,0x90,
++0x9e,0x4a,0xe0,0xc3,0x94,0xff,0x50,0x06,0xe0,0x04,0xf0,0xe4,0x80,0x11,0x90,0x9e,
++0x4b,0xe0,0xc3,0x94,0xff,0x50,0x0c,0xe0,0x04,0xf0,0xe4,0x90,0x9e,0x4a,0xf0,0x90,
++0x9e,0x49,0xf0,0x90,0x00,0x44,0xe0,0x30,0xe3,0x32,0x90,0x9e,0x4c,0xe0,0xc3,0x94,
++0xff,0x50,0x05,0xe0,0x04,0xf0,0x80,0x24,0x90,0x9e,0x4d,0xe0,0xc3,0x94,0xff,0x50,
++0x06,0xe0,0x04,0xf0,0xe4,0x80,0x11,0x90,0x9e,0x4e,0xe0,0xc3,0x94,0xff,0x50,0x0c,
++0xe0,0x04,0xf0,0xe4,0x90,0x9e,0x4d,0xf0,0x90,0x9e,0x4c,0xf0,0x90,0x04,0xfd,0xe0,
++0x44,0x01,0xf0,0x22,0x68,0x4c,};
++#else
++// =================== v88 TSMC P2PPS with CCX report C2H 2012-12-05 =======================
++u8 Rtl8192CUFwTSMCImgArray[TSMCImgArrayLength] = {
++0xC1, 0x88, 0x02, 0x05, 0x58, 0x00, 0x02, 0x00, 0x12, 0x05, 0x17, 0x12, 0xDE, 0x3E, 0x00, 0x00,
++0x94, 0x18, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x02, 0x46, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x02, 0x60, 0xF2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x02, 0x68, 0x91, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x4B, 0x87, 0x00, 0x00,
++0x05, 0x04, 0x03, 0x02, 0x00, 0x03, 0x06, 0x05, 0x04, 0x03, 0x00, 0x04, 0x06, 0x05, 0x04, 0x02,
++0x00, 0x04, 0x08, 0x07, 0x06, 0x04, 0x00, 0x06, 0x0A, 0x09, 0x08, 0x06, 0x00, 0x08, 0x0A, 0x09,
++0x08, 0x04, 0x00, 0x08, 0x0A, 0x09, 0x08, 0x02, 0x00, 0x08, 0x0A, 0x09, 0x08, 0x00, 0x00, 0x08,
++0x12, 0x11, 0x10, 0x08, 0x00, 0x10, 0x1A, 0x19, 0x18, 0x10, 0x00, 0x18, 0x22, 0x21, 0x20, 0x18,
++0x00, 0x20, 0x22, 0x21, 0x20, 0x10, 0x00, 0x20, 0x22, 0x21, 0x20, 0x08, 0x00, 0x20, 0x22, 0x21,
++0x1C, 0x08, 0x00, 0x20, 0x22, 0x21, 0x14, 0x08, 0x00, 0x20, 0x22, 0x20, 0x18, 0x08, 0x00, 0x20,
++0x31, 0x30, 0x20, 0x10, 0x00, 0x30, 0x31, 0x30, 0x18, 0x00, 0x00, 0x30, 0x31, 0x2F, 0x10, 0x10,
++0x00, 0x30, 0x31, 0x2C, 0x10, 0x10, 0x00, 0x30, 0x31, 0x28, 0x10, 0x00, 0x00, 0x30, 0x31, 0x20,
++0x10, 0x00, 0x00, 0x30, 0x31, 0x10, 0x10, 0x00, 0x00, 0x30, 0x04, 0x04, 0x04, 0x05, 0x04, 0x04,
++0x05, 0x07, 0x07, 0x07, 0x08, 0x0A, 0x04, 0x04, 0x04, 0x04, 0x06, 0x0A, 0x0B, 0x0D, 0x05, 0x05,
++0x07, 0x07, 0x08, 0x0B, 0x0D, 0x0F, 0x04, 0x04, 0x04, 0x05, 0x07, 0x07, 0x09, 0x09, 0x0C, 0x0E,
++0x10, 0x12, 0x06, 0x07, 0x09, 0x0A, 0x0C, 0x0E, 0x11, 0x13, 0x09, 0x09, 0x09, 0x09, 0x0C, 0x0E,
++0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x24, 0x26, 0x2A, 0x18, 0x1A,
++0x1D, 0x1F, 0x21, 0x27, 0x29, 0x2A, 0x00, 0x00, 0x00, 0x1F, 0x23, 0x28, 0x2A, 0x2C, 0x00, 0x04,
++0x00, 0x04, 0x00, 0x08, 0x00, 0x10, 0x00, 0x18, 0x00, 0x24, 0x00, 0x30, 0x00, 0x48, 0x00, 0x60,
++0x00, 0x90, 0x00, 0xC0, 0x00, 0xD8, 0x00, 0x50, 0x00, 0x78, 0x00, 0xA0, 0x00, 0xC8, 0x01, 0x40,
++0x01, 0x90, 0x01, 0xE0, 0x02, 0x30, 0x01, 0x2C, 0x01, 0x40, 0x01, 0xE0, 0x02, 0xD0, 0x03, 0xE8,
++0x04, 0xB0, 0x06, 0x40, 0x07, 0xD0, 0x00, 0x02, 0x00, 0x02, 0x00, 0x04, 0x00, 0x08, 0x00, 0x0C,
++0x00, 0x12, 0x00, 0x18, 0x00, 0x24, 0x00, 0x30, 0x00, 0x48, 0x00, 0x60, 0x00, 0x6C, 0x00, 0x28,
++0x00, 0x3C, 0x00, 0x50, 0x00, 0x64, 0x00, 0xA0, 0x00, 0xC8, 0x00, 0xF0, 0x01, 0x18, 0x00, 0x64,
++0x00, 0xA0, 0x00, 0xF0, 0x01, 0x68, 0x01, 0xF4, 0x02, 0x58, 0x03, 0x20, 0x03, 0xE8, 0x02, 0x02,
++0x02, 0x02, 0x02, 0x02, 0x03, 0x03, 0x04, 0x04, 0x05, 0x07, 0x02, 0x03, 0x04, 0x0A, 0x0C, 0x0E,
++0x10, 0x12, 0x05, 0x07, 0x07, 0x08, 0x0B, 0x12, 0x24, 0x3C, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02,
++0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x05, 0x06,
++0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x20, 0x1E, 0x1C, 0x18, 0x10, 0x18, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0xBB, 0x01, 0x0C, 0xE5, 0x82, 0x29, 0xF5, 0x82, 0xE5, 0x83, 0x3A, 0xF5, 0x83, 0xE0, 0x22, 0x50,
++0x06, 0xE9, 0x25, 0x82, 0xF8, 0xE6, 0x22, 0xBB, 0xFE, 0x06, 0xE9, 0x25, 0x82, 0xF8, 0xE2, 0x22,
++0xE5, 0x82, 0x29, 0xF5, 0x82, 0xE5, 0x83, 0x3A, 0xF5, 0x83, 0xE4, 0x93, 0x22, 0xBB, 0x01, 0x06,
++0x89, 0x82, 0x8A, 0x83, 0xF0, 0x22, 0x50, 0x02, 0xF7, 0x22, 0xBB, 0xFE, 0x01, 0xF3, 0x22, 0xF8,
++0xBB, 0x01, 0x0D, 0xE5, 0x82, 0x29, 0xF5, 0x82, 0xE5, 0x83, 0x3A, 0xF5, 0x83, 0xE8, 0xF0, 0x22,
++0x50, 0x06, 0xE9, 0x25, 0x82, 0xC8, 0xF6, 0x22, 0xBB, 0xFE, 0x05, 0xE9, 0x25, 0x82, 0xC8, 0xF2,
++0x22, 0xC5, 0xF0, 0xF8, 0xA3, 0xE0, 0x28, 0xF0, 0xC5, 0xF0, 0xF8, 0xE5, 0x82, 0x15, 0x82, 0x70,
++0x02, 0x15, 0x83, 0xE0, 0x38, 0xF0, 0x22, 0xBB, 0x01, 0x0A, 0x89, 0x82, 0x8A, 0x83, 0xE0, 0xF5,
++0xF0, 0xA3, 0xE0, 0x22, 0x50, 0x06, 0x87, 0xF0, 0x09, 0xE7, 0x19, 0x22, 0xBB, 0xFE, 0x07, 0xE3,
++0xF5, 0xF0, 0x09, 0xE3, 0x19, 0x22, 0x89, 0x82, 0x8A, 0x83, 0xE4, 0x93, 0xF5, 0xF0, 0x74, 0x01,
++0x93, 0x22, 0xBB, 0x01, 0x10, 0xE5, 0x82, 0x29, 0xF5, 0x82, 0xE5, 0x83, 0x3A, 0xF5, 0x83, 0xE0,
++0xF5, 0xF0, 0xA3, 0xE0, 0x22, 0x50, 0x09, 0xE9, 0x25, 0x82, 0xF8, 0x86, 0xF0, 0x08, 0xE6, 0x22,
++0xBB, 0xFE, 0x0A, 0xE9, 0x25, 0x82, 0xF8, 0xE2, 0xF5, 0xF0, 0x08, 0xE2, 0x22, 0xE5, 0x83, 0x2A,
++0xF5, 0x83, 0xE9, 0x93, 0xF5, 0xF0, 0xA3, 0xE9, 0x93, 0x22, 0xBB, 0x01, 0x0A, 0x89, 0x82, 0x8A,
++0x83, 0xF0, 0xE5, 0xF0, 0xA3, 0xF0, 0x22, 0x50, 0x06, 0xF7, 0x09, 0xA7, 0xF0, 0x19, 0x22, 0xBB,
++0xFE, 0x06, 0xF3, 0xE5, 0xF0, 0x09, 0xF3, 0x19, 0x22, 0xF8, 0xBB, 0x01, 0x11, 0xE5, 0x82, 0x29,
++0xF5, 0x82, 0xE5, 0x83, 0x3A, 0xF5, 0x83, 0xE8, 0xF0, 0xE5, 0xF0, 0xA3, 0xF0, 0x22, 0x50, 0x09,
++0xE9, 0x25, 0x82, 0xC8, 0xF6, 0x08, 0xA6, 0xF0, 0x22, 0xBB, 0xFE, 0x09, 0xE9, 0x25, 0x82, 0xC8,
++0xF2, 0xE5, 0xF0, 0x08, 0xF2, 0x22, 0xEF, 0x4B, 0xFF, 0xEE, 0x4A, 0xFE, 0xED, 0x49, 0xFD, 0xEC,
++0x48, 0xFC, 0x22, 0xE0, 0xFC, 0xA3, 0xE0, 0xFD, 0xA3, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF, 0x22, 0xA4,
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++0x8B, 0x20, 0x12, 0x43, 0x53, 0x90, 0x80, 0x85, 0x12, 0x2A, 0x7F, 0x7F, 0x04, 0x7E, 0x0C, 0x12,
++0x2F, 0xD9, 0x90, 0x8B, 0x24, 0x12, 0x43, 0x53, 0x90, 0x80, 0x85, 0x12, 0x2A, 0x7F, 0x7F, 0x00,
++0x7E, 0x08, 0x12, 0x2F, 0xD9, 0x90, 0x8B, 0x28, 0x12, 0x43, 0x53, 0x90, 0x80, 0x85, 0x12, 0x2A,
++0x7F, 0x7F, 0x70, 0x7E, 0x0E, 0x12, 0x2F, 0xD9, 0x90, 0x80, 0x59, 0x12, 0x2A, 0x8B, 0x00, 0x03,
++0x2D, 0x95, 0xE4, 0xFD, 0xFF, 0x12, 0x34, 0x81, 0x90, 0x8B, 0x09, 0xE0, 0xB4, 0x01, 0x11, 0x90,
++0x80, 0x59, 0x12, 0x2A, 0x8B, 0x00, 0x03, 0x2D, 0x95, 0xE4, 0xFD, 0x7F, 0x01, 0x12, 0x34, 0x81,
++0x22, 0x90, 0x8B, 0x2D, 0xE0, 0x64, 0x06, 0x60, 0x3C, 0xE5, 0x22, 0x54, 0x0F, 0x14, 0x60, 0x2E,
++0x14, 0x60, 0x1E, 0x24, 0xFE, 0x60, 0x0E, 0x24, 0xF8, 0x70, 0x2A, 0xE4, 0x90, 0x8B, 0x2D, 0xF0,
++0x90, 0x05, 0x22, 0xF0, 0x22, 0x90, 0x8B, 0x2D, 0x74, 0x01, 0xF0, 0x90, 0x05, 0x22, 0xE4, 0xF0,
++0x22, 0x90, 0x8B, 0x2D, 0x74, 0x03, 0xF0, 0x90, 0x05, 0x22, 0x74, 0xFF, 0xF0, 0x22, 0x90, 0x01,
++0xC6, 0xE0, 0x44, 0x08, 0xF0, 0x22, 0xAE, 0x07, 0xE4, 0xFF, 0x12, 0x4D, 0xE0, 0xEF, 0x60, 0x18,
++0x90, 0x8B, 0x2C, 0xE0, 0xC4, 0x13, 0x13, 0x54, 0x03, 0x20, 0xE0, 0x0C, 0xAF, 0x06, 0x7D, 0x01,
++0x12, 0x45, 0xA2, 0xB1, 0xC1, 0x7F, 0x01, 0x22, 0x7F, 0x00, 0x22, 0x90, 0x01, 0x57, 0xE0, 0x60,
++0x3C, 0x90, 0x01, 0x57, 0xE4, 0xF0, 0x90, 0x01, 0x3C, 0x74, 0x02, 0xF0, 0x90, 0x8B, 0x1B, 0xE0,
++0x60, 0x07, 0xE4, 0xF0, 0x53, 0x25, 0xFD, 0x80, 0x24, 0x90, 0x8B, 0x0C, 0xE0, 0x04, 0xF0, 0x53,
++0x25, 0xEF, 0x90, 0x8B, 0x10, 0xE0, 0xFF, 0x90, 0x8B, 0x0C, 0xE0, 0xD3, 0x9F, 0x40, 0x0E, 0xE5,
++0x21, 0xB4, 0x01, 0x09, 0x90, 0x8B, 0x0D, 0xE0, 0x70, 0x03, 0xE0, 0x04, 0xF0, 0x90, 0x01, 0x5B,
++0xE0, 0x60, 0x10, 0x90, 0x01, 0x5B, 0xE4, 0xF0, 0x90, 0x01, 0x3C, 0x74, 0x04, 0xF0, 0xE4, 0x90,
++0x8B, 0x18, 0xF0, 0x90, 0x01, 0x5F, 0xE0, 0x60, 0x10, 0x90, 0x01, 0x5F, 0xE4, 0xF0, 0x90, 0x01,
++0x3C, 0x74, 0x08, 0xF0, 0xE4, 0x90, 0x8B, 0x17, 0xF0, 0x22, 0xE4, 0x90, 0x8B, 0x4F, 0xF0, 0xA3,
++0xF0, 0x90, 0x05, 0xF8, 0xE0, 0x70, 0x0F, 0xA3, 0xE0, 0x70, 0x0B, 0xA3, 0xE0, 0x70, 0x07, 0xA3,
++0xE0, 0x70, 0x03, 0x7F, 0x01, 0x22, 0xD3, 0x90, 0x8B, 0x50, 0xE0, 0x94, 0xE8, 0x90, 0x8B, 0x4F,
++0xE0, 0x94, 0x03, 0x40, 0x03, 0x7F, 0x00, 0x22, 0x7F, 0x32, 0x7E, 0x00, 0x12, 0x37, 0x54, 0x90,
++0x8B, 0x4F, 0xE4, 0x75, 0xF0, 0x01, 0x12, 0x42, 0x81, 0x80, 0xC6, 0x00, 0x92, 0x00};
++
++// =================== v88 UMC A Cut P2PPS with CCX report C2H 2012-12-05 =====================
++u8 Rtl8192CUFwUMCACutImgArray[UMCACutImgArrayLength] = {
++0xC1, 0x88, 0x02, 0x05, 0x58, 0x00, 0x02, 0x00, 0x12, 0x05, 0x17, 0x11, 0xDE, 0x3E, 0x01, 0x00,
++0x94, 0x18, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x02, 0x46, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x02, 0x60, 0xF2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x02, 0x68, 0x91, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x4B, 0x87, 0x00, 0x00,
++0x05, 0x04, 0x03, 0x02, 0x00, 0x03, 0x06, 0x05, 0x04, 0x03, 0x00, 0x04, 0x06, 0x05, 0x04, 0x02,
++0x00, 0x04, 0x08, 0x07, 0x06, 0x04, 0x00, 0x06, 0x0A, 0x09, 0x08, 0x06, 0x00, 0x08, 0x0A, 0x09,
++0x08, 0x04, 0x00, 0x08, 0x0A, 0x09, 0x08, 0x02, 0x00, 0x08, 0x0A, 0x09, 0x08, 0x00, 0x00, 0x08,
++0x12, 0x11, 0x10, 0x08, 0x00, 0x10, 0x1A, 0x19, 0x18, 0x10, 0x00, 0x18, 0x22, 0x21, 0x20, 0x18,
++0x00, 0x20, 0x22, 0x21, 0x20, 0x10, 0x00, 0x20, 0x22, 0x21, 0x20, 0x08, 0x00, 0x20, 0x22, 0x21,
++0x1C, 0x08, 0x00, 0x20, 0x22, 0x21, 0x14, 0x08, 0x00, 0x20, 0x22, 0x20, 0x18, 0x08, 0x00, 0x20,
++0x31, 0x30, 0x20, 0x10, 0x00, 0x30, 0x31, 0x30, 0x18, 0x00, 0x00, 0x30, 0x31, 0x2F, 0x10, 0x10,
++0x00, 0x30, 0x31, 0x2C, 0x10, 0x10, 0x00, 0x30, 0x31, 0x28, 0x10, 0x00, 0x00, 0x30, 0x31, 0x20,
++0x10, 0x00, 0x00, 0x30, 0x31, 0x10, 0x10, 0x00, 0x00, 0x30, 0x04, 0x04, 0x04, 0x05, 0x04, 0x04,
++0x05, 0x07, 0x07, 0x07, 0x08, 0x0A, 0x04, 0x04, 0x04, 0x04, 0x06, 0x0A, 0x0B, 0x0D, 0x05, 0x05,
++0x07, 0x07, 0x08, 0x0B, 0x0D, 0x0F, 0x04, 0x04, 0x04, 0x05, 0x07, 0x07, 0x09, 0x09, 0x0C, 0x0E,
++0x10, 0x12, 0x06, 0x07, 0x09, 0x0A, 0x0C, 0x0E, 0x11, 0x13, 0x09, 0x09, 0x09, 0x09, 0x0C, 0x0E,
++0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x24, 0x26, 0x2A, 0x18, 0x1A,
++0x1D, 0x1F, 0x21, 0x27, 0x29, 0x2A, 0x00, 0x00, 0x00, 0x1F, 0x23, 0x28, 0x2A, 0x2C, 0x00, 0x04,
++0x00, 0x04, 0x00, 0x08, 0x00, 0x10, 0x00, 0x18, 0x00, 0x24, 0x00, 0x30, 0x00, 0x48, 0x00, 0x60,
++0x00, 0x90, 0x00, 0xC0, 0x00, 0xD8, 0x00, 0x50, 0x00, 0x78, 0x00, 0xA0, 0x00, 0xC8, 0x01, 0x40,
++0x01, 0x90, 0x01, 0xE0, 0x02, 0x30, 0x01, 0x2C, 0x01, 0x40, 0x01, 0xE0, 0x02, 0xD0, 0x03, 0xE8,
++0x04, 0xB0, 0x06, 0x40, 0x07, 0xD0, 0x00, 0x02, 0x00, 0x02, 0x00, 0x04, 0x00, 0x08, 0x00, 0x0C,
++0x00, 0x12, 0x00, 0x18, 0x00, 0x24, 0x00, 0x30, 0x00, 0x48, 0x00, 0x60, 0x00, 0x6C, 0x00, 0x28,
++0x00, 0x3C, 0x00, 0x50, 0x00, 0x64, 0x00, 0xA0, 0x00, 0xC8, 0x00, 0xF0, 0x01, 0x18, 0x00, 0x64,
++0x00, 0xA0, 0x00, 0xF0, 0x01, 0x68, 0x01, 0xF4, 0x02, 0x58, 0x03, 0x20, 0x03, 0xE8, 0x02, 0x02,
++0x02, 0x02, 0x02, 0x02, 0x03, 0x03, 0x04, 0x04, 0x05, 0x07, 0x02, 0x03, 0x04, 0x0A, 0x0C, 0x0E,
++0x10, 0x12, 0x05, 0x07, 0x07, 0x08, 0x0B, 0x12, 0x24, 0x3C, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02,
++0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x05, 0x06,
++0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x20, 0x1E, 0x1C, 0x18, 0x10, 0x18, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0xBB, 0x01, 0x0C, 0xE5, 0x82, 0x29, 0xF5, 0x82, 0xE5, 0x83, 0x3A, 0xF5, 0x83, 0xE0, 0x22, 0x50,
++0x06, 0xE9, 0x25, 0x82, 0xF8, 0xE6, 0x22, 0xBB, 0xFE, 0x06, 0xE9, 0x25, 0x82, 0xF8, 0xE2, 0x22,
++0xE5, 0x82, 0x29, 0xF5, 0x82, 0xE5, 0x83, 0x3A, 0xF5, 0x83, 0xE4, 0x93, 0x22, 0xBB, 0x01, 0x06,
++0x89, 0x82, 0x8A, 0x83, 0xF0, 0x22, 0x50, 0x02, 0xF7, 0x22, 0xBB, 0xFE, 0x01, 0xF3, 0x22, 0xF8,
++0xBB, 0x01, 0x0D, 0xE5, 0x82, 0x29, 0xF5, 0x82, 0xE5, 0x83, 0x3A, 0xF5, 0x83, 0xE8, 0xF0, 0x22,
++0x50, 0x06, 0xE9, 0x25, 0x82, 0xC8, 0xF6, 0x22, 0xBB, 0xFE, 0x05, 0xE9, 0x25, 0x82, 0xC8, 0xF2,
++0x22, 0xC5, 0xF0, 0xF8, 0xA3, 0xE0, 0x28, 0xF0, 0xC5, 0xF0, 0xF8, 0xE5, 0x82, 0x15, 0x82, 0x70,
++0x02, 0x15, 0x83, 0xE0, 0x38, 0xF0, 0x22, 0xBB, 0x01, 0x0A, 0x89, 0x82, 0x8A, 0x83, 0xE0, 0xF5,
++0xF0, 0xA3, 0xE0, 0x22, 0x50, 0x06, 0x87, 0xF0, 0x09, 0xE7, 0x19, 0x22, 0xBB, 0xFE, 0x07, 0xE3,
++0xF5, 0xF0, 0x09, 0xE3, 0x19, 0x22, 0x89, 0x82, 0x8A, 0x83, 0xE4, 0x93, 0xF5, 0xF0, 0x74, 0x01,
++0x93, 0x22, 0xBB, 0x01, 0x10, 0xE5, 0x82, 0x29, 0xF5, 0x82, 0xE5, 0x83, 0x3A, 0xF5, 0x83, 0xE0,
++0xF5, 0xF0, 0xA3, 0xE0, 0x22, 0x50, 0x09, 0xE9, 0x25, 0x82, 0xF8, 0x86, 0xF0, 0x08, 0xE6, 0x22,
++0xBB, 0xFE, 0x0A, 0xE9, 0x25, 0x82, 0xF8, 0xE2, 0xF5, 0xF0, 0x08, 0xE2, 0x22, 0xE5, 0x83, 0x2A,
++0xF5, 0x83, 0xE9, 0x93, 0xF5, 0xF0, 0xA3, 0xE9, 0x93, 0x22, 0xBB, 0x01, 0x0A, 0x89, 0x82, 0x8A,
++0x83, 0xF0, 0xE5, 0xF0, 0xA3, 0xF0, 0x22, 0x50, 0x06, 0xF7, 0x09, 0xA7, 0xF0, 0x19, 0x22, 0xBB,
++0xFE, 0x06, 0xF3, 0xE5, 0xF0, 0x09, 0xF3, 0x19, 0x22, 0xF8, 0xBB, 0x01, 0x11, 0xE5, 0x82, 0x29,
++0xF5, 0x82, 0xE5, 0x83, 0x3A, 0xF5, 0x83, 0xE8, 0xF0, 0xE5, 0xF0, 0xA3, 0xF0, 0x22, 0x50, 0x09,
++0xE9, 0x25, 0x82, 0xC8, 0xF6, 0x08, 0xA6, 0xF0, 0x22, 0xBB, 0xFE, 0x09, 0xE9, 0x25, 0x82, 0xC8,
++0xF2, 0xE5, 0xF0, 0x08, 0xF2, 0x22, 0xEF, 0x4B, 0xFF, 0xEE, 0x4A, 0xFE, 0xED, 0x49, 0xFD, 0xEC,
++0x48, 0xFC, 0x22, 0xE0, 0xFC, 0xA3, 0xE0, 0xFD, 0xA3, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF, 0x22, 0xA4,
++0x25, 0x82, 0xF5, 0x82, 0xE5, 0xF0, 0x35, 0x83, 0xF5, 0x83, 0x22, 0xE0, 0xFB, 0xA3, 0xE0, 0xFA,
++0xA3, 0xE0, 0xF9, 0x22, 0xF8, 0xE0, 0xFB, 0xA3, 0xA3, 0xE0, 0xF9, 0x25, 0xF0, 0xF0, 0xE5, 0x82,
++0x15, 0x82, 0x70, 0x02, 0x15, 0x83, 0xE0, 0xFA, 0x38, 0xF0, 0x22, 0xEB, 0xF0, 0xA3, 0xEA, 0xF0,
++0xA3, 0xE9, 0xF0, 0x22, 0xD0, 0x83, 0xD0, 0x82, 0xF8, 0xE4, 0x93, 0x70, 0x12, 0x74, 0x01, 0x93,
++0x70, 0x0D, 0xA3, 0xA3, 0x93, 0xF8, 0x74, 0x01, 0x93, 0xF5, 0x82, 0x88, 0x83, 0xE4, 0x73, 0x74,
++0x02, 0x93, 0x68, 0x60, 0xEF, 0xA3, 0xA3, 0xA3, 0x80, 0xDF, 0xD0, 0x83, 0xD0, 0x82, 0xF8, 0xE4,
++0x93, 0x70, 0x12, 0x74, 0x01, 0x93, 0x70, 0x0D, 0xA3, 0xA3, 0x93, 0xF8, 0x74, 0x01, 0x93, 0xF5,
++0x82, 0x88, 0x83, 0xE4, 0x73, 0x74, 0x02, 0x93, 0xB5, 0xF0, 0x06, 0x74, 0x03, 0x93, 0x68, 0x60,
++0xE9, 0xA3, 0xA3, 0xA3, 0xA3, 0x80, 0xD8, 0xE4, 0x90, 0x8A, 0xC5, 0xF0, 0xE5, 0x24, 0x70, 0x03,
++0x02, 0x44, 0x9D, 0xE5, 0x21, 0x64, 0x01, 0x60, 0x03, 0x02, 0x44, 0x9D, 0xE5, 0x24, 0x14, 0x60,
++0x29, 0x24, 0xFD, 0x60, 0x25, 0x24, 0x02, 0x24, 0xFB, 0x50, 0x02, 0x80, 0x23, 0x90, 0x8B, 0x0B,
++0xE0, 0x14, 0xF0, 0xE0, 0x60, 0x04, 0xA3, 0xE0, 0x60, 0x16, 0x90, 0x8B, 0x0B, 0xE0, 0x70, 0x0A,
++0x90, 0x8B, 0x19, 0xE0, 0x90, 0x8B, 0x0B, 0xF0, 0x80, 0x00, 0x90, 0x8A, 0xC5, 0x74, 0x01, 0xF0,
++0x90, 0x8B, 0x2C, 0xE0, 0x30, 0xE0, 0x16, 0xA3, 0xE0, 0xB4, 0x06, 0x05, 0xE4, 0x90, 0x8A, 0xC5,
++0xF0, 0xE4, 0xFF, 0x12, 0x4D, 0xE0, 0xEF, 0x70, 0x04, 0x90, 0x8A, 0xC5, 0xF0, 0x90, 0x8A, 0xC5,
++0xE0, 0x60, 0x4A, 0x43, 0x25, 0x10, 0xE4, 0x90, 0x8B, 0x3D, 0xF0, 0x90, 0x8B, 0x0C, 0xE0, 0x75,
++0xF0, 0x03, 0xA4, 0xFF, 0x90, 0x8B, 0x15, 0xE0, 0x2F, 0x90, 0x8B, 0x3E, 0xF0, 0xE4, 0xFB, 0xFD,
++0x7F, 0x54, 0x7E, 0x01, 0x12, 0x4B, 0x6C, 0x90, 0x01, 0x57, 0x74, 0x05, 0xF0, 0xE5, 0x22, 0x54,
++0x0F, 0xC3, 0x94, 0x04, 0x50, 0x07, 0x7D, 0x01, 0x7F, 0x04, 0x12, 0x45, 0xA2, 0x90, 0x8B, 0x2C,
++0xE0, 0x30, 0xE0, 0x09, 0x12, 0x7D, 0xC1, 0x90, 0x05, 0x22, 0x74, 0xFF, 0xF0, 0x22, 0xE4, 0xF5,
++0x25, 0xF5, 0x24, 0x75, 0x23, 0x0C, 0x75, 0x22, 0x0C, 0x90, 0x8B, 0x1A, 0xF0, 0x90, 0x8B, 0x18,
++0xF0, 0x90, 0x8B, 0x17, 0xF0, 0x90, 0x8B, 0x19, 0x04, 0xF0, 0x90, 0x8B, 0x0B, 0xF0, 0xE4, 0x90,
++0x8B, 0x1B, 0xF0, 0x90, 0x8B, 0x0D, 0xF0, 0x90, 0x8B, 0x15, 0x74, 0x05, 0xF0, 0xE4, 0x90, 0x8B,
++0x0C, 0xF0, 0x90, 0x8B, 0x13, 0xF0, 0xA3, 0x74, 0x03, 0xF0, 0x90, 0x8B, 0x10, 0xF0, 0xA3, 0x74,
++0x05, 0xF0, 0x90, 0x8B, 0x0F, 0x74, 0x14, 0xF0, 0x90, 0x8B, 0x16, 0x74, 0x05, 0xF0, 0xE4, 0x90,
++0x8B, 0x0E, 0xF0, 0x90, 0x8B, 0x0A, 0xF0, 0x90, 0x8B, 0x08, 0xF0, 0x90, 0x8B, 0x12, 0xF0, 0x22,
++0x7F, 0x00, 0x22, 0x02, 0x45, 0x03, 0x02, 0x45, 0x06, 0x8E, 0x64, 0x8F, 0x65, 0xAD, 0x65, 0xAC,
++0x64, 0xAF, 0x63, 0x12, 0x4A, 0x5B, 0xAF, 0x65, 0xAE, 0x64, 0x90, 0x04, 0x80, 0xE0, 0x54, 0x0F,
++0xFD, 0xAC, 0x07, 0x74, 0x11, 0x2C, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x44, 0x01,
++0xF0, 0x74, 0x11, 0x2C, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x54, 0xFB, 0xF0, 0xAC,
++0x07, 0x74, 0x16, 0x2C, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x44, 0xFA, 0xF0, 0x74,
++0x15, 0x2C, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x44, 0x1F, 0xF0, 0xAC, 0x07, 0x74,
++0x06, 0x2C, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x44, 0x0F, 0xF0, 0x90, 0x04, 0x53,
++0xE4, 0xF0, 0x90, 0x04, 0x52, 0xF0, 0x90, 0x04, 0x51, 0x74, 0xFF, 0xF0, 0x90, 0x04, 0x50, 0x74,
++0xFD, 0xF0, 0x74, 0x14, 0x2C, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x54, 0xC0, 0x4D,
++0xFD, 0x74, 0x14, 0x2F, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xED, 0xF0, 0x22, 0x7D, 0x01,
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++0xA3, 0xF0, 0xED, 0x64, 0x02, 0x60, 0x04, 0xED, 0xB4, 0x03, 0x15, 0x90, 0x8B, 0x2C, 0xE0, 0x54,
++0xFE, 0xF0, 0x54, 0xFB, 0xF0, 0xE4, 0xA3, 0xF0, 0xA3, 0xF0, 0xA3, 0xF0, 0xA3, 0xF0, 0xA3, 0xF0,
++0x22, 0x12, 0x24, 0x62, 0x90, 0x8B, 0x38, 0xF0, 0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0,
++0x90, 0x8A, 0xFD, 0xE0, 0x90, 0x8A, 0xE8, 0xF0, 0x90, 0x8A, 0xFE, 0xE0, 0xFF, 0xA3, 0xE0, 0x90,
++0x8A, 0xE9, 0xCF, 0xF0, 0xA3, 0xEF, 0xF0, 0xE4, 0x90, 0x8A, 0xE4, 0xF0, 0x90, 0x8A, 0xE4, 0xE0,
++0xFF, 0x24, 0x00, 0xF5, 0x82, 0xE4, 0x34, 0x8B, 0xF5, 0x83, 0xE0, 0xFE, 0x74, 0xEB, 0x2F, 0xF5,
++0x82, 0xE4, 0x34, 0x8A, 0xF5, 0x83, 0xEE, 0xF0, 0x90, 0x8A, 0xE4, 0xE0, 0x04, 0xF0, 0xE0, 0xB4,
++0x04, 0xDA, 0x90, 0x8A, 0xE8, 0xE0, 0x12, 0x43, 0x94, 0x78, 0xF8, 0x00, 0x7A, 0x6B, 0x01, 0x79,
++0x01, 0x02, 0x79, 0x01, 0x03, 0x79, 0x01, 0x04, 0x7A, 0x6B, 0x05, 0x7A, 0x35, 0x80, 0x7A, 0x4E,
++0x81, 0x7A, 0x6B, 0x82, 0x00, 0x00, 0x7A, 0x67, 0x90, 0x8A, 0xEE, 0xE0, 0xFF, 0x51, 0x72, 0x41,
++0x6B, 0x90, 0x8A, 0xE8, 0xE0, 0xFF, 0xB4, 0x02, 0x08, 0x90, 0x8A, 0xE5, 0x74, 0x01, 0xF0, 0x80,
++0x0F, 0xEF, 0x90, 0x8A, 0xE5, 0xB4, 0x03, 0x05, 0x74, 0x02, 0xF0, 0x80, 0x03, 0x74, 0x04, 0xF0,
++0xC3, 0x90, 0x8A, 0xE9, 0xE0, 0x94, 0x08, 0x50, 0x78, 0xE4, 0x90, 0x8A, 0xE4, 0xF0, 0x90, 0x8A,
++0xE5, 0xE0, 0xFF, 0x90, 0x8A, 0xE4, 0xE0, 0xC3, 0x9F, 0x40, 0x02, 0x41, 0x6B, 0x90, 0x8A, 0xE9,
++0xE0, 0xFE, 0xA3, 0xE0, 0xFF, 0xC3, 0xEE, 0x94, 0x01, 0x90, 0x8A, 0xE4, 0xE0, 0x50, 0x1F, 0xFE,
++0x2F, 0xFF, 0xEE, 0xFD, 0xC3, 0x74, 0x03, 0x9D, 0xFD, 0xE4, 0x94, 0x00, 0xFC, 0x74, 0xEB, 0x2D,
++0xF5, 0x82, 0x74, 0x8A, 0x3C, 0xF5, 0x83, 0xE0, 0xFD, 0x12, 0x51, 0x88, 0x80, 0x2B, 0xFF, 0xFD,
++0xC3, 0x74, 0x03, 0x9D, 0xFD, 0xE4, 0x94, 0x00, 0xFC, 0x74, 0xEB, 0x2D, 0xF5, 0x82, 0x74, 0x8A,
++0x3C, 0xF5, 0x83, 0xE0, 0xFE, 0xEF, 0xFD, 0x90, 0x8A, 0xEA, 0xE0, 0x2D, 0xFD, 0x90, 0x8A, 0xE9,
++0xE0, 0x34, 0x00, 0x8D, 0x82, 0xF5, 0x83, 0xEE, 0xF0, 0x90, 0x8A, 0xE4, 0xE0, 0x04, 0xF0, 0x80,
++0x8D, 0xC3, 0x90, 0x8A, 0xE9, 0xE0, 0x94, 0x10, 0x40, 0x02, 0x41, 0x6B, 0x90, 0x8A, 0xE8, 0xE0,
++0x64, 0x04, 0x60, 0x02, 0x41, 0x6B, 0x90, 0x8A, 0xEC, 0xE0, 0xFF, 0xE4, 0xFC, 0xFD, 0xFE, 0x78,
++0x10, 0x12, 0x24, 0xF5, 0xC0, 0x04, 0xC0, 0x05, 0xC0, 0x06, 0xC0, 0x07, 0x90, 0x8A, 0xEB, 0xE0,
++0xFF, 0xE4, 0xFC, 0xFD, 0xFE, 0x78, 0x18, 0x12, 0x24, 0xF5, 0xD0, 0x03, 0xD0, 0x02, 0xD0, 0x01,
++0xD0, 0x00, 0x12, 0x43, 0x46, 0xC0, 0x04, 0xC0, 0x05, 0xC0, 0x06, 0xC0, 0x07, 0x90, 0x8A, 0xED,
++0xE0, 0xFF, 0xE4, 0xFC, 0xFD, 0xFE, 0x78, 0x08, 0x12, 0x24, 0xF5, 0xD0, 0x03, 0xD0, 0x02, 0xD0,
++0x01, 0xD0, 0x00, 0x12, 0x43, 0x46, 0xA8, 0x04, 0xA9, 0x05, 0xAA, 0x06, 0xAB, 0x07, 0xA3, 0xE0,
++0xFF, 0xE4, 0xFC, 0xFD, 0xFE, 0x12, 0x43, 0x46, 0xA3, 0x12, 0x25, 0x08, 0x90, 0x8A, 0xEF, 0x12,
++0x43, 0x53, 0x90, 0x80, 0x96, 0x12, 0x25, 0x08, 0x90, 0x8A, 0xE9, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF,
++0x12, 0x2B, 0x08, 0x80, 0x36, 0x90, 0x8A, 0xED, 0xE0, 0xFE, 0xA3, 0xE0, 0x24, 0x00, 0xFF, 0xE4,
++0x3E, 0xFE, 0x90, 0x8A, 0xE6, 0xF0, 0xA3, 0xEF, 0xF0, 0x12, 0x32, 0x15, 0x80, 0x1D, 0x90, 0x8A,
++0xED, 0xE0, 0xFE, 0xA3, 0xE0, 0x24, 0x00, 0xFF, 0xE4, 0x3E, 0xFE, 0x90, 0x8A, 0xE6, 0xF0, 0xA3,
++0xEF, 0xF0, 0x12, 0x31, 0x82, 0x80, 0x04, 0x7F, 0x00, 0x80, 0x02, 0x7F, 0x01, 0xD0, 0xD0, 0x92,
++0xAF, 0x22, 0x8F, 0x0F, 0xE4, 0x90, 0x8A, 0xF3, 0xF0, 0xE5, 0x0F, 0x14, 0xFE, 0x90, 0x8A, 0xF3,
++0xE0, 0xFF, 0xC3, 0x9E, 0x50, 0x0E, 0xEF, 0x04, 0xFD, 0x12, 0x2D, 0x4D, 0x90, 0x8A, 0xF3, 0xE0,
++0x04, 0xF0, 0x80, 0xE5, 0xE5, 0x0F, 0x14, 0xFF, 0x7D, 0xFF, 0x12, 0x2D, 0x4D, 0x90, 0x8A, 0xF3,
++0xE5, 0x0F, 0xF0, 0x90, 0x8A, 0xF3, 0xE0, 0xC3, 0x94, 0xFF, 0x50, 0x0F, 0xE0, 0xFF, 0x04, 0xFD,
++0x12, 0x2D, 0x4D, 0x90, 0x8A, 0xF3, 0xE0, 0x04, 0xF0, 0x80, 0xE8, 0xAD, 0x0F, 0x7F, 0xFF, 0x02,
++0x2D, 0x4D, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0xE4, 0x90, 0x8A, 0xDD, 0xF0, 0xA3, 0x74,
++0x04, 0xF0, 0xA3, 0xE4, 0xF0, 0x90, 0x8A, 0xE2, 0xF0, 0xA3, 0xF0, 0x90, 0x02, 0x09, 0xE0, 0x90,
++0x8A, 0xE1, 0xF0, 0x12, 0x24, 0x62, 0xFF, 0x90, 0x8A, 0xE1, 0xE0, 0x2F, 0x90, 0x8A, 0xE0, 0xF0,
++0x30, 0xE0, 0x0B, 0x90, 0x8A, 0xDB, 0xE4, 0xF0, 0xA3, 0x74, 0x80, 0xF0, 0x80, 0x07, 0xE4, 0x90,
++0x8A, 0xDB, 0xF0, 0xA3, 0xF0, 0x90, 0x8A, 0xE0, 0xE0, 0xC3, 0x13, 0x90, 0xFD, 0x10, 0xF0, 0x90,
++0x8A, 0xDD, 0xE0, 0x24, 0x20, 0xF0, 0x90, 0x8A, 0xDB, 0xA3, 0xE0, 0xFD, 0xA3, 0xE0, 0xFC, 0x2D,
++0xFF, 0x24, 0x01, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x90, 0x8A, 0xFD, 0xF0, 0x74,
++0x02, 0x2F, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0xFE, 0xEC, 0x2D, 0x24, 0x03, 0xF5,
++0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x24, 0x00, 0xFF, 0xE4, 0x3E, 0x90, 0x8A, 0xFE, 0xF0,
++0xA3, 0xEF, 0xF0, 0x90, 0x8A, 0xDA, 0x74, 0x04, 0xF0, 0x90, 0x8A, 0xDB, 0xA3, 0xE0, 0xFF, 0xA3,
++0xE0, 0x2F, 0xFF, 0x90, 0x8A, 0xDA, 0xE0, 0xFE, 0x2F, 0x24, 0x00, 0xF5, 0x82, 0xE4, 0x34, 0xFC,
++0xF5, 0x83, 0xE0, 0xFF, 0x74, 0xFC, 0x2E, 0xF5, 0x82, 0xE4, 0x34, 0x8A, 0xF5, 0x83, 0xEF, 0xF0,
++0x90, 0x8A, 0xDA, 0xE0, 0x04, 0xF0, 0xE0, 0xB4, 0x08, 0xCF, 0x11, 0x89, 0xEF, 0x70, 0x45, 0x90,
++0x01, 0xC3, 0xE0, 0x60, 0x2B, 0xC3, 0x90, 0x8A, 0xE3, 0xE0, 0x94, 0xE8, 0x90, 0x8A, 0xE2, 0xE0,
++0x94, 0x03, 0x40, 0x09, 0x90, 0x01, 0xC6, 0xE0, 0x44, 0x10, 0xF0, 0x80, 0x79, 0x90, 0x8A, 0xE2,
++0xE4, 0x75, 0xF0, 0x01, 0x12, 0x42, 0x81, 0x7F, 0x0A, 0x7E, 0x00, 0x12, 0x32, 0x15, 0x80, 0xCF,
++0x90, 0x01, 0xC6, 0xE0, 0x90, 0x01, 0xC3, 0x30, 0xE2, 0x05, 0x74, 0xFE, 0xF0, 0x80, 0x57, 0x74,
++0xFF, 0xF0, 0x80, 0x52, 0x90, 0x8A, 0xDD, 0xE0, 0xB4, 0x78, 0x2E, 0xE4, 0xF0, 0x90, 0x8A, 0xE0,
++0xE0, 0x04, 0xF0, 0x90, 0x8A, 0xDB, 0xE0, 0x70, 0x04, 0xA3, 0xE0, 0x64, 0x80, 0x90, 0x8A, 0xDB,
++0x70, 0x05, 0xF0, 0xA3, 0xF0, 0x80, 0x06, 0xE4, 0xF0, 0xA3, 0x74, 0x80, 0xF0, 0x90, 0x8A, 0xE0,
++0xE0, 0xC3, 0x13, 0x90, 0xFD, 0x10, 0xF0, 0x80, 0x07, 0x90, 0x8A, 0xDD, 0xE0, 0x24, 0x08, 0xF0,
++0x90, 0x8A, 0xDE, 0x74, 0xFF, 0xF5, 0xF0, 0x12, 0x42, 0x81, 0x90, 0x8A, 0xDE, 0xE0, 0x70, 0x02,
++0xA3, 0xE0, 0x60, 0x02, 0x61, 0x16, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0x12, 0x24, 0x62, 0x90, 0x8B,
++0x05, 0xF0, 0x90, 0x00, 0x01, 0x12, 0x42, 0x20, 0x90, 0x8B, 0x06, 0xF0, 0x22, 0xE4, 0xF5, 0x61,
++0x22, 0x91, 0x4A, 0x90, 0x8B, 0x33, 0x74, 0x02, 0xF0, 0x22, 0x90, 0x05, 0x22, 0x74, 0xFF, 0xF0,
++0x7F, 0x78, 0x7E, 0x08, 0x12, 0x22, 0x65, 0x90, 0x8B, 0x1C, 0x12, 0x25, 0x08, 0x7F, 0x04, 0x7E,
++0x0C, 0x12, 0x22, 0x65, 0x90, 0x8B, 0x20, 0x12, 0x25, 0x08, 0x7F, 0x00, 0x7E, 0x08, 0x12, 0x22,
++0x65, 0x90, 0x8B, 0x24, 0x12, 0x25, 0x08, 0x90, 0x8B, 0x09, 0xE0, 0x90, 0x8B, 0x1C, 0xB4, 0x01,
++0x0D, 0x12, 0x43, 0x53, 0xEF, 0x54, 0xC7, 0xFF, 0xED, 0x54, 0xC7, 0xFD, 0x80, 0x07, 0x12, 0x43,
++0x53, 0xEF, 0x54, 0xC7, 0xFF, 0xEC, 0x90, 0x80, 0x96, 0x12, 0x25, 0x08, 0x7F, 0x78, 0x7E, 0x08,
++0x12, 0x2B, 0x08, 0x90, 0x8B, 0x20, 0x12, 0x43, 0x53, 0xEF, 0x54, 0x0F, 0xFF, 0xEC, 0x90, 0x80,
++0x96, 0x12, 0x25, 0x08, 0x7F, 0x04, 0x7E, 0x0C, 0x12, 0x2B, 0x08, 0x90, 0x8B, 0x24, 0x12, 0x43,
++0x53, 0xEF, 0x44, 0x02, 0xFF, 0xEC, 0x90, 0x80, 0x96, 0x12, 0x25, 0x08, 0x7F, 0x00, 0x7E, 0x08,
++0x12, 0x2B, 0x08, 0x7F, 0x70, 0x7E, 0x0E, 0x12, 0x22, 0x65, 0x90, 0x8B, 0x28, 0x12, 0x25, 0x08,
++0x90, 0x80, 0x96, 0x12, 0x25, 0x14, 0x00, 0x1B, 0x25, 0xA0, 0x7F, 0x70, 0x7E, 0x0E, 0x12, 0x2B,
++0x08, 0x90, 0x80, 0x68, 0x12, 0x25, 0x14, 0x00, 0x00, 0x00, 0x00, 0xE4, 0xFD, 0xFF, 0x12, 0x30,
++0x2C, 0x90, 0x8B, 0x09, 0xE0, 0xB4, 0x01, 0x11, 0x90, 0x80, 0x68, 0x12, 0x25, 0x14, 0x00, 0x00,
++0x00, 0x00, 0xE4, 0xFD, 0x7F, 0x01, 0x12, 0x30, 0x2C, 0x90, 0x00, 0x11, 0xE0, 0x54, 0xF6, 0xF0,
++0x02, 0x52, 0x0E, 0x91, 0x50, 0x90, 0x8B, 0x33, 0x74, 0x02, 0xF0, 0x22, 0x90, 0x05, 0x22, 0x74,
++0xFF, 0xF0, 0x90, 0x8B, 0x33, 0x74, 0x04, 0xF0, 0x22, 0xB1, 0x42, 0x90, 0x8B, 0x33, 0x74, 0x04,
++0xF0, 0x22, 0x90, 0x00, 0x11, 0xE0, 0x44, 0x09, 0xF0, 0x12, 0x52, 0x0E, 0x90, 0x8B, 0x1C, 0x12,
++0x43, 0x53, 0x90, 0x80, 0x96, 0x12, 0x25, 0x08, 0x7F, 0x78, 0x7E, 0x08, 0x12, 0x2B, 0x08, 0x90,
++0x8B, 0x20, 0x12, 0x43, 0x53, 0x90, 0x80, 0x96, 0x12, 0x25, 0x08, 0x7F, 0x04, 0x7E, 0x0C, 0x12,
++0x2B, 0x08, 0x90, 0x8B, 0x24, 0x12, 0x43, 0x53, 0x90, 0x80, 0x96, 0x12, 0x25, 0x08, 0x7F, 0x00,
++0x7E, 0x08, 0x12, 0x2B, 0x08, 0x90, 0x8B, 0x28, 0x12, 0x43, 0x53, 0x90, 0x80, 0x96, 0x12, 0x25,
++0x08, 0x7F, 0x70, 0x7E, 0x0E, 0x12, 0x2B, 0x08, 0x90, 0x80, 0x68, 0x12, 0x25, 0x14, 0x00, 0x03,
++0x2D, 0x95, 0xE4, 0xFD, 0xFF, 0x12, 0x30, 0x2C, 0x90, 0x8B, 0x09, 0xE0, 0xB4, 0x01, 0x11, 0x90,
++0x80, 0x68, 0x12, 0x25, 0x14, 0x00, 0x03, 0x2D, 0x95, 0xE4, 0xFD, 0x7F, 0x01, 0x12, 0x30, 0x2C,
++0x22, 0x90, 0x8B, 0x2D, 0xE0, 0x64, 0x06, 0x60, 0x3C, 0xE5, 0x22, 0x54, 0x0F, 0x14, 0x60, 0x2E,
++0x14, 0x60, 0x1E, 0x24, 0xFE, 0x60, 0x0E, 0x24, 0xF8, 0x70, 0x2A, 0xE4, 0x90, 0x8B, 0x2D, 0xF0,
++0x90, 0x05, 0x22, 0xF0, 0x22, 0x90, 0x8B, 0x2D, 0x74, 0x01, 0xF0, 0x90, 0x05, 0x22, 0xE4, 0xF0,
++0x22, 0x90, 0x8B, 0x2D, 0x74, 0x03, 0xF0, 0x90, 0x05, 0x22, 0x74, 0xFF, 0xF0, 0x22, 0x90, 0x01,
++0xC6, 0xE0, 0x44, 0x08, 0xF0, 0x22, 0xAE, 0x07, 0xE4, 0xFF, 0x12, 0x4D, 0xE0, 0xEF, 0x60, 0x18,
++0x90, 0x8B, 0x2C, 0xE0, 0xC4, 0x13, 0x13, 0x54, 0x03, 0x20, 0xE0, 0x0C, 0xAF, 0x06, 0x7D, 0x01,
++0x12, 0x45, 0xA2, 0xB1, 0xC1, 0x7F, 0x01, 0x22, 0x7F, 0x00, 0x22, 0x90, 0x01, 0x57, 0xE0, 0x60,
++0x3C, 0x90, 0x01, 0x57, 0xE4, 0xF0, 0x90, 0x01, 0x3C, 0x74, 0x02, 0xF0, 0x90, 0x8B, 0x1B, 0xE0,
++0x60, 0x07, 0xE4, 0xF0, 0x53, 0x25, 0xFD, 0x80, 0x24, 0x90, 0x8B, 0x0C, 0xE0, 0x04, 0xF0, 0x53,
++0x25, 0xEF, 0x90, 0x8B, 0x10, 0xE0, 0xFF, 0x90, 0x8B, 0x0C, 0xE0, 0xD3, 0x9F, 0x40, 0x0E, 0xE5,
++0x21, 0xB4, 0x01, 0x09, 0x90, 0x8B, 0x0D, 0xE0, 0x70, 0x03, 0xE0, 0x04, 0xF0, 0x90, 0x01, 0x5B,
++0xE0, 0x60, 0x10, 0x90, 0x01, 0x5B, 0xE4, 0xF0, 0x90, 0x01, 0x3C, 0x74, 0x04, 0xF0, 0xE4, 0x90,
++0x8B, 0x18, 0xF0, 0x90, 0x01, 0x5F, 0xE0, 0x60, 0x10, 0x90, 0x01, 0x5F, 0xE4, 0xF0, 0x90, 0x01,
++0x3C, 0x74, 0x08, 0xF0, 0xE4, 0x90, 0x8B, 0x17, 0xF0, 0x22, 0xE4, 0x90, 0x8B, 0x4F, 0xF0, 0xA3,
++0xF0, 0x90, 0x05, 0xF8, 0xE0, 0x70, 0x0F, 0xA3, 0xE0, 0x70, 0x0B, 0xA3, 0xE0, 0x70, 0x07, 0xA3,
++0xE0, 0x70, 0x03, 0x7F, 0x01, 0x22, 0xD3, 0x90, 0x8B, 0x50, 0xE0, 0x94, 0xE8, 0x90, 0x8B, 0x4F,
++0xE0, 0x94, 0x03, 0x40, 0x03, 0x7F, 0x00, 0x22, 0x7F, 0x32, 0x7E, 0x00, 0x12, 0x32, 0x15, 0x90,
++0x8B, 0x4F, 0xE4, 0x75, 0xF0, 0x01, 0x12, 0x42, 0x81, 0x80, 0xC6, 0x00, 0xFB, 0x98};
++
++// =================== v88 UMC B Cut P2PPS with CCX report C2H 2012-12-05 =====================
++u8 Rtl8192CUFwUMCBCutImgArray[UMCBCutImgArrayLength] = {
++0xC2, 0x88, 0x02, 0x05, 0x58, 0x00, 0x02, 0x00, 0x12, 0x05, 0x17, 0x10, 0xC0, 0x3E, 0x01, 0x00,
++0x94, 0x18, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x02, 0x46, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x02, 0x60, 0xF3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x02, 0x67, 0x5B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x4B, 0x87, 0x00, 0x00,
++0x05, 0x04, 0x03, 0x02, 0x00, 0x03, 0x06, 0x05, 0x04, 0x03, 0x00, 0x04, 0x06, 0x05, 0x04, 0x02,
++0x00, 0x04, 0x08, 0x07, 0x06, 0x04, 0x00, 0x06, 0x0A, 0x09, 0x08, 0x06, 0x00, 0x08, 0x0A, 0x09,
++0x08, 0x04, 0x00, 0x08, 0x0A, 0x09, 0x08, 0x02, 0x00, 0x08, 0x0A, 0x09, 0x08, 0x00, 0x00, 0x08,
++0x12, 0x11, 0x10, 0x08, 0x00, 0x10, 0x1A, 0x19, 0x18, 0x10, 0x00, 0x18, 0x22, 0x21, 0x20, 0x18,
++0x00, 0x20, 0x22, 0x21, 0x20, 0x10, 0x00, 0x20, 0x22, 0x21, 0x20, 0x08, 0x00, 0x20, 0x22, 0x21,
++0x1C, 0x08, 0x00, 0x20, 0x22, 0x21, 0x14, 0x08, 0x00, 0x20, 0x22, 0x20, 0x18, 0x08, 0x00, 0x20,
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++0xC7, 0xFF, 0xEC, 0x90, 0x80, 0x85, 0x12, 0x2A, 0x7F, 0x7F, 0x78, 0x7E, 0x08, 0x12, 0x2F, 0xD9,
++0x90, 0x8B, 0x20, 0x12, 0x43, 0x53, 0xEF, 0x54, 0x0F, 0xFF, 0xEC, 0x90, 0x80, 0x85, 0x12, 0x2A,
++0x7F, 0x7F, 0x04, 0x7E, 0x0C, 0x12, 0x2F, 0xD9, 0x90, 0x8B, 0x24, 0x12, 0x43, 0x53, 0xEF, 0x44,
++0x02, 0xFF, 0xEC, 0x90, 0x80, 0x85, 0x12, 0x2A, 0x7F, 0x7F, 0x00, 0x7E, 0x08, 0x12, 0x2F, 0xD9,
++0x7F, 0x70, 0x7E, 0x0E, 0x12, 0x27, 0xDE, 0x90, 0x8B, 0x28, 0x12, 0x2A, 0x7F, 0x90, 0x80, 0x85,
++0x12, 0x2A, 0x8B, 0x00, 0x1B, 0x25, 0xA0, 0x7F, 0x70, 0x7E, 0x0E, 0x12, 0x2F, 0xD9, 0x90, 0x80,
++0x59, 0x12, 0x2A, 0x8B, 0x00, 0x00, 0x00, 0x00, 0xE4, 0xFD, 0xFF, 0x12, 0x34, 0x81, 0x90, 0x8B,
++0x09, 0xE0, 0xB4, 0x01, 0x11, 0x90, 0x80, 0x59, 0x12, 0x2A, 0x8B, 0x00, 0x00, 0x00, 0x00, 0xE4,
++0xFD, 0x7F, 0x01, 0x12, 0x34, 0x81, 0x22, 0x51, 0x6D, 0x90, 0x8B, 0x33, 0x74, 0x02, 0xF0, 0x22,
++0x51, 0x67, 0x90, 0x8B, 0x2D, 0x74, 0x04, 0xF0, 0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0,
++0x90, 0x8B, 0x2D, 0xE0, 0xFE, 0x6F, 0x70, 0x02, 0xA1, 0x15, 0xEF, 0x12, 0x43, 0x94, 0x7B, 0x77,
++0x00, 0x7B, 0xB1, 0x01, 0x7B, 0xF7, 0x02, 0x7C, 0x31, 0x03, 0x7C, 0x69, 0x04, 0x7C, 0xA2, 0x05,
++0x7C, 0xDD, 0x06, 0x00, 0x00, 0x7D, 0x15, 0xEE, 0xB4, 0x04, 0x06, 0x7F, 0x01, 0xB1, 0x48, 0xA1,
++0x15, 0x90, 0x8B, 0x2D, 0xE0, 0xFF, 0xB4, 0x05, 0x04, 0xB1, 0x24, 0xA1, 0x15, 0xEF, 0xB4, 0x06,
++0x06, 0x7F, 0x01, 0xB1, 0x39, 0x80, 0x16, 0x90, 0x8B, 0x2D, 0xE0, 0xB4, 0x03, 0x06, 0x7F, 0x01,
++0xB1, 0x1A, 0x80, 0x09, 0x90, 0x8B, 0x2D, 0xE0, 0xB4, 0x02, 0x02, 0xB1, 0x2E, 0xB1, 0x6B, 0xA1,
++0x15, 0x90, 0x8B, 0x2D, 0xE0, 0xB4, 0x04, 0x06, 0x7F, 0x01, 0xB1, 0x48, 0x80, 0x09, 0x90, 0x8B,
++0x2D, 0xE0, 0xB4, 0x05, 0x02, 0xB1, 0x24, 0x90, 0x8B, 0x2D, 0xE0, 0x70, 0x04, 0xB1, 0x61, 0xA1,
++0x15, 0x90, 0x8B, 0x2D, 0xE0, 0xFE, 0xB4, 0x06, 0x06, 0x7F, 0x01, 0xB1, 0x39, 0xA1, 0x15, 0xEE,
++0xB4, 0x03, 0x06, 0x7F, 0x01, 0xB1, 0x1A, 0xA1, 0x15, 0x90, 0x8B, 0x2D, 0xE0, 0x64, 0x02, 0x60,
++0x02, 0xA1, 0x15, 0xB1, 0x2E, 0xA1, 0x15, 0x90, 0x8B, 0x2D, 0xE0, 0xB4, 0x04, 0x06, 0x7F, 0x01,
++0xB1, 0x48, 0x80, 0x09, 0x90, 0x8B, 0x2D, 0xE0, 0xB4, 0x05, 0x02, 0xB1, 0x24, 0x90, 0x8B, 0x2D,
++0xE0, 0x70, 0x04, 0xB1, 0x61, 0x80, 0x16, 0x90, 0x8B, 0x2D, 0xE0, 0xFE, 0xB4, 0x06, 0x06, 0x7F,
++0x01, 0xB1, 0x39, 0x80, 0x08, 0xEE, 0xB4, 0x03, 0x04, 0x7F, 0x01, 0xB1, 0x1A, 0xB1, 0x8D, 0xA1,
++0x15, 0x90, 0x8B, 0x2D, 0xE0, 0xB4, 0x04, 0x06, 0x7F, 0x01, 0xB1, 0x48, 0x80, 0x09, 0x90, 0x8B,
++0x2D, 0xE0, 0xB4, 0x05, 0x02, 0xB1, 0x24, 0x90, 0x8B, 0x2D, 0xE0, 0x70, 0x04, 0xB1, 0x61, 0x80,
++0x14, 0x90, 0x8B, 0x2D, 0xE0, 0xFE, 0xB4, 0x06, 0x06, 0xE4, 0xFF, 0xB1, 0x39, 0x80, 0x06, 0xEE,
++0xB4, 0x02, 0x02, 0xB1, 0x2E, 0xB1, 0x76, 0xA1, 0x15, 0x90, 0x8B, 0x2D, 0xE0, 0xFE, 0xB4, 0x06,
++0x06, 0xE4, 0xFF, 0xB1, 0x39, 0x80, 0x13, 0xEE, 0xB4, 0x03, 0x06, 0x7F, 0x01, 0xB1, 0x1A, 0x80,
++0x09, 0x90, 0x8B, 0x2D, 0xE0, 0xB4, 0x02, 0x02, 0xB1, 0x2E, 0x90, 0x8B, 0x2D, 0xE0, 0xB4, 0x01,
++0x04, 0xB1, 0x6B, 0x80, 0x09, 0x90, 0x8B, 0x2D, 0xE0, 0xB4, 0x05, 0x02, 0xB1, 0x24, 0x71, 0x40,
++0x80, 0x73, 0x90, 0x8B, 0x2D, 0xE0, 0xFE, 0xB4, 0x06, 0x06, 0xE4, 0xFF, 0xB1, 0x39, 0x80, 0x13,
++0xEE, 0xB4, 0x03, 0x06, 0x7F, 0x01, 0xB1, 0x1A, 0x80, 0x09, 0x90, 0x8B, 0x2D, 0xE0, 0xB4, 0x02,
++0x02, 0xB1, 0x2E, 0x90, 0x8B, 0x2D, 0xE0, 0xB4, 0x01, 0x04, 0xB1, 0x6B, 0x80, 0x0B, 0x90, 0x8B,
++0x2D, 0xE0, 0xB4, 0x04, 0x04, 0x7F, 0x01, 0xB1, 0x48, 0xB1, 0x80, 0x80, 0x38, 0x90, 0x8B, 0x2D,
++0xE0, 0xB4, 0x04, 0x06, 0x7F, 0x01, 0xB1, 0x48, 0x80, 0x09, 0x90, 0x8B, 0x2D, 0xE0, 0xB4, 0x05,
++0x02, 0xB1, 0x24, 0x90, 0x8B, 0x2D, 0xE0, 0x70, 0x04, 0xB1, 0x61, 0x80, 0x16, 0x90, 0x8B, 0x2D,
++0xE0, 0xB4, 0x03, 0x06, 0xE4, 0xFF, 0xB1, 0x1A, 0x80, 0x09, 0x90, 0x8B, 0x2D, 0xE0, 0xB4, 0x02,
++0x02, 0xB1, 0x2E, 0xB1, 0x9A, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0x12, 0x4A, 0xB2, 0x90, 0x8B, 0x2D,
++0x74, 0x01, 0xF0, 0x22, 0x90, 0x05, 0x22, 0xE4, 0xF0, 0x90, 0x8B, 0x2D, 0xF0, 0x22, 0x90, 0x05,
++0x22, 0xE4, 0xF0, 0x90, 0x8B, 0x2D, 0x04, 0xF0, 0x22, 0xEF, 0x60, 0x05, 0x90, 0x05, 0x22, 0xE4,
++0xF0, 0x90, 0x8B, 0x2D, 0x74, 0x01, 0xF0, 0x22, 0x90, 0x8B, 0x56, 0xEF, 0xF0, 0x12, 0x4F, 0xED,
++0x90, 0x8B, 0x56, 0xE0, 0x60, 0x05, 0x90, 0x05, 0x22, 0xE4, 0xF0, 0xE4, 0x90, 0x8B, 0x2D, 0xF0,
++0x22, 0x12, 0x4A, 0xCC, 0x90, 0x8B, 0x2D, 0x74, 0x01, 0xF0, 0x22, 0x7F, 0x01, 0x12, 0x4A, 0x7C,
++0xE4, 0x90, 0x8B, 0x2D, 0xF0, 0x22, 0x12, 0x4A, 0x32, 0x90, 0x8B, 0x2D, 0x74, 0x03, 0xF0, 0x22,
++0x90, 0x05, 0x22, 0x74, 0xFF, 0xF0, 0x90, 0x8B, 0x2D, 0x74, 0x05, 0xF0, 0x22, 0x90, 0x05, 0x22,
++0x74, 0xFF, 0xF0, 0x90, 0x8B, 0x2D, 0x74, 0x02, 0xF0, 0x22, 0x90, 0x05, 0x22, 0x74, 0x6F, 0xF0,
++0x90, 0x8B, 0x2D, 0x74, 0x06, 0xF0, 0x22, 0x90, 0x05, 0x22, 0x74, 0xFF, 0xF0, 0x90, 0x8B, 0x33,
++0x74, 0x04, 0xF0, 0x22, 0x12, 0x4F, 0xED, 0x90, 0x8B, 0x33, 0x74, 0x04, 0xF0, 0x22, 0x90, 0x01,
++0x57, 0xE0, 0x60, 0x3C, 0x90, 0x01, 0x57, 0xE4, 0xF0, 0x90, 0x01, 0x3C, 0x74, 0x02, 0xF0, 0x90,
++0x8B, 0x1B, 0xE0, 0x60, 0x07, 0xE4, 0xF0, 0x53, 0x25, 0xFD, 0x80, 0x24, 0x90, 0x8B, 0x0C, 0xE0,
++0x04, 0xF0, 0x53, 0x25, 0xEF, 0x90, 0x8B, 0x10, 0xE0, 0xFF, 0x90, 0x8B, 0x0C, 0xE0, 0xD3, 0x9F,
++0x40, 0x0E, 0xE5, 0x21, 0xB4, 0x01, 0x09, 0x90, 0x8B, 0x0D, 0xE0, 0x70, 0x03, 0xE0, 0x04, 0xF0,
++0x90, 0x01, 0x5B, 0xE0, 0x60, 0x10, 0x90, 0x01, 0x5B, 0xE4, 0xF0, 0x90, 0x01, 0x3C, 0x74, 0x04,
++0xF0, 0xE4, 0x90, 0x8B, 0x18, 0xF0, 0x90, 0x01, 0x5F, 0xE0, 0x60, 0x10, 0x90, 0x01, 0x5F, 0xE4,
++0xF0, 0x90, 0x01, 0x3C, 0x74, 0x08, 0xF0, 0xE4, 0x90, 0x8B, 0x17, 0xF0, 0x22, 0xE4, 0x90, 0x8B,
++0x4F, 0xF0, 0xA3, 0xF0, 0x90, 0x05, 0xF8, 0xE0, 0x70, 0x0F, 0xA3, 0xE0, 0x70, 0x0B, 0xA3, 0xE0,
++0x70, 0x07, 0xA3, 0xE0, 0x70, 0x03, 0x7F, 0x01, 0x22, 0xD3, 0x90, 0x8B, 0x50, 0xE0, 0x94, 0xE8,
++0x90, 0x8B, 0x4F, 0xE0, 0x94, 0x03, 0x40, 0x03, 0x7F, 0x00, 0x22, 0x7F, 0x32, 0x7E, 0x00, 0x12,
++0x37, 0x54, 0x90, 0x8B, 0x4F, 0xE4, 0x75, 0xF0, 0x01, 0x12, 0x42, 0x81, 0x80, 0xC6, 0x8F, 0x0F,
++0xE4, 0x90, 0x8A, 0xF3, 0xF0, 0xE5, 0x0F, 0x14, 0xFE, 0x90, 0x8A, 0xF3, 0xE0, 0xFF, 0xC3, 0x9E,
++0x50, 0x0E, 0xEF, 0x04, 0xFD, 0x12, 0x34, 0xB7, 0x90, 0x8A, 0xF3, 0xE0, 0x04, 0xF0, 0x80, 0xE5,
++0xE5, 0x0F, 0x14, 0xFF, 0x7D, 0xFF, 0x12, 0x34, 0xB7, 0x90, 0x8A, 0xF3, 0xE5, 0x0F, 0xF0, 0x90,
++0x8A, 0xF3, 0xE0, 0xC3, 0x94, 0xFF, 0x50, 0x0F, 0xE0, 0xFF, 0x04, 0xFD, 0x12, 0x34, 0xB7, 0x90,
++0x8A, 0xF3, 0xE0, 0x04, 0xF0, 0x80, 0xE8, 0xAD, 0x0F, 0x7F, 0xFF, 0x02, 0x34, 0xB7, 0xDC, 0xD3,
++};
++#endif
++
++//8188C_Formal_All_PHYforMP_111117 2011-11-23
++//8192C_Formal_92CU_PHYforMP_110817 2011-11-23
++
++u32 Rtl8192CUPHY_REG_2TArray[PHY_REG_2TArrayLength] = {
++0x024,0x0011800f,
++0x028,0x00ffdb83,
++0x800,0x80040002,
++0x804,0x00000003,
++0x808,0x0000fc00,
++0x80c,0x0000000a,
++0x810,0x10000330, //for Broadcom AP IOT
++0x814,0x020c3d10,
++0x818,0x02200385,
++0x81c,0x00000000,
++0x820,0x01000100,
++0x824,0x00390004,
++0x828,0x01000100,
++0x82c,0x00390004,
++0x830,0x27272727,
++0x834,0x27272727,
++0x838,0x27272727,
++0x83c,0x27272727,
++0x840,0x00010000,
++0x844,0x00010000,
++0x848,0x27272727,
++0x84c,0x27272727,
++0x850,0x00000000,
++0x854,0x00000000,
++0x858,0x569a569a,
++0x85c,0x0c1b25a4,
++0x860,0x66e60230,
++0x864,0x061f0130,
++0x868,0x27272727,
++0x86c,0x2b2b2b27,
++0x870,0x07000700,
++0x874,0x22184000,
++0x878,0x08080808,
++0x87c,0x00000000,
++0x880,0xc0083070,
++0x884,0x000004d5,
++0x888,0x00000000,
++0x88c,0xcc0000c0,
++0x890,0x00000800,
++0x894,0xfffffffe,
++0x898,0x40302010,
++0x89c,0x00706050,
++0x900,0x00000000,
++0x904,0x00000023,
++0x908,0x00000000,
++0x90c,0x81121313,
++0xa00,0x00d047c8,
++0xa04,0x80ff000c,
++0xa08,0x8c838300,
++0xa0c,0x2e68120f,
++0xa10,0x9500bb78,
++0xa14,0x11144028,
++0xa18,0x00881117,
++0xa1c,0x89140f00,
++0xa20,0x1a1b0000,
++0xa24,0x090e1317,
++0xa28,0x00000204,
++0xa2c,0x00d30000,
++0xa70,0x101fbf00,
++0xa74,0x00000007,
++0xc00,0x48071d40,
++0xc04,0x03a05633,
++0xc08,0x000000e4,
++0xc0c,0x6c6c6c6c,
++0xc10,0x08800000,
++0xc14,0x40000100,
++0xc18,0x08800000,
++0xc1c,0x40000100,
++0xc20,0x00000000,
++0xc24,0x00000000,
++0xc28,0x00000000,
++0xc2c,0x00000000,
++0xc30,0x69e9ac44,
++0xc34,0x469652cf,
++0xc38,0x49795994,
++0xc3c,0x0a97971c,
++0xc40,0x1f7c403f,
++0xc44,0x000100b7,
++0xc48,0xec020107,
++0xc4c,0x007f037f,
++0xc50,0x69543420,
++0xc54,0x43bc0094,
++0xc58,0x69543420,
++0xc5c,0x433c0094,
++0xc60,0x00000000,
++0xc64,0x5116848b,
++0xc68,0x47c00bff,
++0xc6c,0x00000036,
++0xc70,0x2c7f000d,
++0xc74,0x2186115b,
++0xc78,0x0000001f,
++0xc7c,0x00b99612,
++0xc80,0x40000100,
++0xc84,0x20f60000,
++0xc88,0x40000100,
++0xc8c,0xa0e40000,
++0xc90,0x00121820,
++0xc94,0x00000000,
++0xc98,0x00121820,
++0xc9c,0x00007f7f,
++0xca0,0x00000000,
++0xca4,0x00000080,
++0xca8,0x00000000,
++0xcac,0x00000000,
++0xcb0,0x00000000,
++0xcb4,0x00000000,
++0xcb8,0x00000000,
++0xcbc,0x28000000,
++0xcc0,0x00000000,
++0xcc4,0x00000000,
++0xcc8,0x00000000,
++0xccc,0x00000000,
++0xcd0,0x00000000,
++0xcd4,0x00000000,
++0xcd8,0x64b22427,
++0xcdc,0x00766932,
++0xce0,0x00222222,
++0xce4,0x00000000,
++0xce8,0x37644302,
++0xcec,0x2f97d40c,
++0xd00,0x00080740,
++0xd04,0x00020403,
++0xd08,0x0000907f,
++0xd0c,0x20010201,
++0xd10,0xa0633333,
++0xd14,0x3333bc43,
++0xd18,0x7a8f5b6b,
++0xd2c,0xcc979975,
++0xd30,0x00000000,
++0xd34,0x80608000,
++0xd38,0x00000000,
++0xd3c,0x00027293,
++0xd40,0x00000000,
++0xd44,0x00000000,
++0xd48,0x00000000,
++0xd4c,0x00000000,
++0xd50,0x6437140a,
++0xd54,0x00000000,
++0xd58,0x00000000,
++0xd5c,0x30032064,
++0xd60,0x4653de68,
++0xd64,0x04518a3c,
++0xd68,0x00002101,
++0xd6c,0x2a201c16,
++0xd70,0x1812362e,
++0xd74,0x322c2220,
++0xd78,0x000e3c24,
++0xe00,0x2a2a2a2a,
++0xe04,0x2a2a2a2a,
++0xe08,0x03902a2a,
++0xe10,0x2a2a2a2a,
++0xe14,0x2a2a2a2a,
++0xe18,0x2a2a2a2a,
++0xe1c,0x2a2a2a2a,
++0xe28,0x00000000,
++0xe30,0x1000dc1f,
++0xe34,0x10008c1f,
++0xe38,0x02140102,
++0xe3c,0x681604c2,
++0xe40,0x01007c00,
++0xe44,0x01004800,
++0xe48,0xfb000000,
++0xe4c,0x000028d1,
++0xe50,0x1000dc1f,
++0xe54,0x10008c1f,
++0xe58,0x02140102,
++0xe5c,0x28160d05,
++0xe60,0x00000010,
++0xe68,0x001b25a4,
++0xe6c,0x63db25a4,
++0xe70,0x63db25a4,
++0xe74,0x0c1b25a4,
++0xe78,0x0c1b25a4,
++0xe7c,0x0c1b25a4,
++0xe80,0x0c1b25a4,
++0xe84,0x63db25a4,
++0xe88,0x0c1b25a4,
++0xe8c,0x63db25a4,
++0xed0,0x63db25a4,
++0xed4,0x63db25a4,
++0xed8,0x63db25a4,
++0xedc,0x001b25a4,
++0xee0,0x001b25a4,
++0xeec,0x6fdb25a4,
++0xf14,0x00000003,
++0xf4c,0x00000000,
++0xf00,0x00000300,
++};
++
++u32 Rtl8192CUPHY_REG_1TArray[PHY_REG_1TArrayLength] = {
++0x024,0x0011800f,
++0x028,0x00ffdb83,
++0x800,0x80040000,
++0x804,0x00000001,
++0x808,0x0000fc00,
++0x80c,0x0000000a,
++0x810,0x10000330, //for Broadcom AP IOT
++0x814,0x020c3d10,
++0x818,0x02200385,
++0x81c,0x00000000,
++0x820,0x01000100,
++0x824,0x00390004,
++0x828,0x00000000,
++0x82c,0x00000000,
++0x830,0x00000000,
++0x834,0x00000000,
++0x838,0x00000000,
++0x83c,0x00000000,
++0x840,0x00010000,
++0x844,0x00000000,
++0x848,0x00000000,
++0x84c,0x00000000,
++0x850,0x00000000,
++0x854,0x00000000,
++0x858,0x569a569a,
++0x85c,0x001b25a4,
++0x860,0x66e60230,
++0x864,0x061f0130,
++0x868,0x00000000,
++0x86c,0x32323200,
++0x870,0x07000700,
++0x874,0x22004000,
++0x878,0x00000808,
++0x87c,0x00000000,
++0x880,0xc0083070,
++0x884,0x000004d5,
++0x888,0x00000000,
++0x88c,0xccc000c0,
++0x890,0x00000800,
++0x894,0xfffffffe,
++0x898,0x40302010,
++0x89c,0x00706050,
++0x900,0x00000000,
++0x904,0x00000023,
++0x908,0x00000000,
++0x90c,0x81121111,
++0xa00,0x00d047c8,
++0xa04,0x80ff000c,
++0xa08,0x8c838300,
++0xa0c,0x2e68120f,
++0xa10,0x9500bb78,
++0xa14,0x11144028,
++0xa18,0x00881117,
++0xa1c,0x89140f00,
++0xa20,0x1a1b0000,
++0xa24,0x090e1317,
++0xa28,0x00000204,
++0xa2c,0x00d30000,
++0xa70,0x101fbf00,
++0xa74,0x00000007,
++0xc00,0x48071d40,
++0xc04,0x03a05611,
++0xc08,0x000000e4,
++0xc0c,0x6c6c6c6c,
++0xc10,0x08800000,
++0xc14,0x40000100,
++0xc18,0x08800000,
++0xc1c,0x40000100,
++0xc20,0x00000000,
++0xc24,0x00000000,
++0xc28,0x00000000,
++0xc2c,0x00000000,
++0xc30,0x69e9ac44,
++0xc34,0x469652cf,
++0xc38,0x49795994,
++0xc3c,0x0a97971c,
++0xc40,0x1f7c403f,
++0xc44,0x000100b7,
++0xc48,0xec020107,
++0xc4c,0x007f037f,
++0xc50,0x69543420,
++0xc54,0x43bc0094,
++0xc58,0x69543420,
++0xc5c,0x433c0094,
++0xc60,0x00000000,
++0xc64,0x5116848b,
++0xc68,0x47c00bff,
++0xc6c,0x00000036,
++0xc70,0x2c7f000d,
++0xc74,0x018610db,
++0xc78,0x0000001f,
++0xc7c,0x00b91612,
++0xc80,0x40000100,
++0xc84,0x20f60000,
++0xc88,0x40000100,
++0xc8c,0x20200000,
++0xc90,0x00121820,
++0xc94,0x00000000,
++0xc98,0x00121820,
++0xc9c,0x00007f7f,
++0xca0,0x00000000,
++0xca4,0x00000080,
++0xca8,0x00000000,
++0xcac,0x00000000,
++0xcb0,0x00000000,
++0xcb4,0x00000000,
++0xcb8,0x00000000,
++0xcbc,0x28000000,
++0xcc0,0x00000000,
++0xcc4,0x00000000,
++0xcc8,0x00000000,
++0xccc,0x00000000,
++0xcd0,0x00000000,
++0xcd4,0x00000000,
++0xcd8,0x64b22427,
++0xcdc,0x00766932,
++0xce0,0x00222222,
++0xce4,0x00000000,
++0xce8,0x37644302,
++0xcec,0x2f97d40c,
++0xd00,0x00000740,
++0xd04,0x00020401,
++0xd08,0x0000907f,
++0xd0c,0x20010201,
++0xd10,0xa0633333,
++0xd14,0x3333bc43,
++0xd18,0x7a8f5b6b,
++0xd2c,0xcc979975,
++0xd30,0x00000000,
++0xd34,0x80608000,
++0xd38,0x00000000,
++0xd3c,0x00027293,
++0xd40,0x00000000,
++0xd44,0x00000000,
++0xd48,0x00000000,
++0xd4c,0x00000000,
++0xd50,0x6437140a,
++0xd54,0x00000000,
++0xd58,0x00000000,
++0xd5c,0x30032064,
++0xd60,0x4653de68,
++0xd64,0x04518a3c,
++0xd68,0x00002101,
++0xd6c,0x2a201c16,
++0xd70,0x1812362e,
++0xd74,0x322c2220,
++0xd78,0x000e3c24,
++0xe00,0x2a2a2a2a,
++0xe04,0x2a2a2a2a,
++0xe08,0x03902a2a,
++0xe10,0x2a2a2a2a,
++0xe14,0x2a2a2a2a,
++0xe18,0x2a2a2a2a,
++0xe1c,0x2a2a2a2a,
++0xe28,0x00000000,
++0xe30,0x1000dc1f,
++0xe34,0x10008c1f,
++0xe38,0x02140102,
++0xe3c,0x681604c2,
++0xe40,0x01007c00,
++0xe44,0x01004800,
++0xe48,0xfb000000,
++0xe4c,0x000028d1,
++0xe50,0x1000dc1f,
++0xe54,0x10008c1f,
++0xe58,0x02140102,
++0xe5c,0x28160d05,
++0xe60,0x00000008,
++0xe68,0x001b25a4,
++0xe6c,0x631b25a0,
++0xe70,0x631b25a0,
++0xe74,0x081b25a0,
++0xe78,0x081b25a0,
++0xe7c,0x081b25a0,
++0xe80,0x081b25a0,
++0xe84,0x631b25a0,
++0xe88,0x081b25a0,
++0xe8c,0x631b25a0,
++0xed0,0x631b25a0,
++0xed4,0x631b25a0,
++0xed8,0x631b25a0,
++0xedc,0x001b25a0,
++0xee0,0x001b25a0,
++0xeec,0x6b1b25a0,
++0xf14,0x00000003,
++0xf4c,0x00000000,
++0xf00,0x00000300,
++};
++
++u32 Rtl8192CUPHY_ChangeTo_1T1RArray[PHY_ChangeTo_1T1RArrayLength] = {
++0x0, };
++
++u32 Rtl8192CUPHY_ChangeTo_1T2RArray[PHY_ChangeTo_1T2RArrayLength] = {
++0x0, };
++
++u32 Rtl8192CUPHY_ChangeTo_2T2RArray[PHY_ChangeTo_2T2RArrayLength] = {
++0x0, };
++
++u32 Rtl8192CUPHY_REG_Array_PG[PHY_REG_Array_PGLength] = {
++0xe00,0xffffffff,0x07090c0c,
++0xe04,0xffffffff,0x01020405,
++0xe08,0x0000ff00,0x00000000,
++0x86c,0xffffff00,0x00000000,
++0xe10,0xffffffff,0x0b0c0c0e,
++0xe14,0xffffffff,0x01030506,
++0xe18,0xffffffff,0x0b0c0d0e,
++0xe1c,0xffffffff,0x01030509,
++0x830,0xffffffff,0x07090c0c,
++0x834,0xffffffff,0x01020405,
++0x838,0xffffff00,0x00000000,
++0x86c,0x000000ff,0x00000000,
++0x83c,0xffffffff,0x0b0c0d0e,
++0x848,0xffffffff,0x01030509,
++0x84c,0xffffffff,0x0b0c0d0e,
++0x868,0xffffffff,0x01030509,
++0xe00,0xffffffff,0x00000000,
++0xe04,0xffffffff,0x00000000,
++0xe08,0x0000ff00,0x00000000,
++0x86c,0xffffff00,0x00000000,
++0xe10,0xffffffff,0x00000000,
++0xe14,0xffffffff,0x00000000,
++0xe18,0xffffffff,0x00000000,
++0xe1c,0xffffffff,0x00000000,
++0x830,0xffffffff,0x00000000,
++0x834,0xffffffff,0x00000000,
++0x838,0xffffff00,0x00000000,
++0x86c,0x000000ff,0x00000000,
++0x83c,0xffffffff,0x00000000,
++0x848,0xffffffff,0x00000000,
++0x84c,0xffffffff,0x00000000,
++0x868,0xffffffff,0x00000000,
++0xe00,0xffffffff,0x04040404,
++0xe04,0xffffffff,0x00020204,
++0xe08,0x0000ff00,0x00000000,
++0x86c,0xffffff00,0x00000000,
++0xe10,0xffffffff,0x06060606,
++0xe14,0xffffffff,0x00020406,
++0xe18,0xffffffff,0x00000000,
++0xe1c,0xffffffff,0x00000000,
++0x830,0xffffffff,0x04040404,
++0x834,0xffffffff,0x00020204,
++0x838,0xffffff00,0x00000000,
++0x86c,0x000000ff,0x00000000,
++0x83c,0xffffffff,0x06060606,
++0x848,0xffffffff,0x00020406,
++0x84c,0xffffffff,0x00000000,
++0x868,0xffffffff,0x00000000,
++0xe00,0xffffffff,0x00000000,
++0xe04,0xffffffff,0x00000000,
++0xe08,0x0000ff00,0x00000000,
++0x86c,0xffffff00,0x00000000,
++0xe10,0xffffffff,0x00000000,
++0xe14,0xffffffff,0x00000000,
++0xe18,0xffffffff,0x00000000,
++0xe1c,0xffffffff,0x00000000,
++0x830,0xffffffff,0x00000000,
++0x834,0xffffffff,0x00000000,
++0x838,0xffffff00,0x00000000,
++0x86c,0x000000ff,0x00000000,
++0x83c,0xffffffff,0x00000000,
++0x848,0xffffffff,0x00000000,
++0x84c,0xffffffff,0x00000000,
++0x868,0xffffffff,0x00000000,
++0xe00,0xffffffff,0x00000000,
++0xe04,0xffffffff,0x00000000,
++0xe08,0x0000ff00,0x00000000,
++0x86c,0xffffff00,0x00000000,
++0xe10,0xffffffff,0x00000000,
++0xe14,0xffffffff,0x00000000,
++0xe18,0xffffffff,0x00000000,
++0xe1c,0xffffffff,0x00000000,
++0x830,0xffffffff,0x00000000,
++0x834,0xffffffff,0x00000000,
++0x838,0xffffff00,0x00000000,
++0x86c,0x000000ff,0x00000000,
++0x83c,0xffffffff,0x00000000,
++0x848,0xffffffff,0x00000000,
++0x84c,0xffffffff,0x00000000,
++0x868,0xffffffff,0x00000000,
++0xe00,0xffffffff,0x04040404,
++0xe04,0xffffffff,0x00020204,
++0xe08,0x0000ff00,0x00000000,
++0x86c,0xffffff00,0x00000000,
++0xe10,0xffffffff,0x00000000,
++0xe14,0xffffffff,0x00000000,
++0xe18,0xffffffff,0x00000000,
++0xe1c,0xffffffff,0x00000000,
++0x830,0xffffffff,0x04040404,
++0x834,0xffffffff,0x00020204,
++0x838,0xffffff00,0x00000000,
++0x86c,0x000000ff,0x00000000,
++0x83c,0xffffffff,0x00000000,
++0x848,0xffffffff,0x00000000,
++0x84c,0xffffffff,0x00000000,
++0x868,0xffffffff,0x00000000,
++0xe00,0xffffffff,0x00000000,
++0xe04,0xffffffff,0x00000000,
++0xe08,0x0000ff00,0x00000000,
++0x86c,0xffffff00,0x00000000,
++0xe10,0xffffffff,0x00000000,
++0xe14,0xffffffff,0x00000000,
++0xe18,0xffffffff,0x00000000,
++0xe1c,0xffffffff,0x00000000,
++0x830,0xffffffff,0x00000000,
++0x834,0xffffffff,0x00000000,
++0x838,0xffffff00,0x00000000,
++0x86c,0x000000ff,0x00000000,
++0x83c,0xffffffff,0x00000000,
++0x848,0xffffffff,0x00000000,
++0x84c,0xffffffff,0x00000000,
++0x868,0xffffffff,0x00000000,
++};
++
++u32 Rtl8192CUPHY_REG_Array_PG_mCard[PHY_REG_Array_PG_mCardLength] = {
++0xe00,0xffffffff,0x0a0c0c0c,
++0xe04,0xffffffff,0x02040608,
++0xe08,0x0000ff00,0x00000000,
++0x86c,0xffffff00,0x00000000,
++0xe10,0xffffffff,0x0a0c0d0e,
++0xe14,0xffffffff,0x02040608,
++0xe18,0xffffffff,0x0a0c0d0e,
++0xe1c,0xffffffff,0x02040608,
++0x830,0xffffffff,0x0a0c0c0c,
++0x834,0xffffffff,0x02040608,
++0x838,0xffffff00,0x00000000,
++0x86c,0x000000ff,0x00000000,
++0x83c,0xffffffff,0x0a0c0d0e,
++0x848,0xffffffff,0x02040608,
++0x84c,0xffffffff,0x0a0c0d0e,
++0x868,0xffffffff,0x02040608,
++0xe00,0xffffffff,0x00000000,
++0xe04,0xffffffff,0x00000000,
++0xe08,0x0000ff00,0x00000000,
++0x86c,0xffffff00,0x00000000,
++0xe10,0xffffffff,0x00000000,
++0xe14,0xffffffff,0x00000000,
++0xe18,0xffffffff,0x00000000,
++0xe1c,0xffffffff,0x00000000,
++0x830,0xffffffff,0x00000000,
++0x834,0xffffffff,0x00000000,
++0x838,0xffffff00,0x00000000,
++0x86c,0x000000ff,0x00000000,
++0x83c,0xffffffff,0x00000000,
++0x848,0xffffffff,0x00000000,
++0x84c,0xffffffff,0x00000000,
++0x868,0xffffffff,0x00000000,
++0xe00,0xffffffff,0x04040404,
++0xe04,0xffffffff,0x00020204,
++0xe08,0x0000ff00,0x00000000,
++0x86c,0xffffff00,0x00000000,
++0xe10,0xffffffff,0x06060606,
++0xe14,0xffffffff,0x00020406,
++0xe18,0xffffffff,0x00000000,
++0xe1c,0xffffffff,0x00000000,
++0x830,0xffffffff,0x04040404,
++0x834,0xffffffff,0x00020204,
++0x838,0xffffff00,0x00000000,
++0x86c,0x000000ff,0x00000000,
++0x83c,0xffffffff,0x06060606,
++0x848,0xffffffff,0x00020406,
++0x84c,0xffffffff,0x00000000,
++0x868,0xffffffff,0x00000000,
++0xe00,0xffffffff,0x00000000,
++0xe04,0xffffffff,0x00000000,
++0xe08,0x0000ff00,0x00000000,
++0x86c,0xffffff00,0x00000000,
++0xe10,0xffffffff,0x00000000,
++0xe14,0xffffffff,0x00000000,
++0xe18,0xffffffff,0x00000000,
++0xe1c,0xffffffff,0x00000000,
++0x830,0xffffffff,0x00000000,
++0x834,0xffffffff,0x00000000,
++0x838,0xffffff00,0x00000000,
++0x86c,0x000000ff,0x00000000,
++0x83c,0xffffffff,0x00000000,
++0x848,0xffffffff,0x00000000,
++0x84c,0xffffffff,0x00000000,
++0x868,0xffffffff,0x00000000,
++0xe00,0xffffffff,0x00000000,
++0xe04,0xffffffff,0x00000000,
++0xe08,0x0000ff00,0x00000000,
++0x86c,0xffffff00,0x00000000,
++0xe10,0xffffffff,0x00000000,
++0xe14,0xffffffff,0x00000000,
++0xe18,0xffffffff,0x00000000,
++0xe1c,0xffffffff,0x00000000,
++0x830,0xffffffff,0x00000000,
++0x834,0xffffffff,0x00000000,
++0x838,0xffffff00,0x00000000,
++0x86c,0x000000ff,0x00000000,
++0x83c,0xffffffff,0x00000000,
++0x848,0xffffffff,0x00000000,
++0x84c,0xffffffff,0x00000000,
++0x868,0xffffffff,0x00000000,
++0xe00,0xffffffff,0x04040404,
++0xe04,0xffffffff,0x00020204,
++0xe08,0x0000ff00,0x00000000,
++0x86c,0xffffff00,0x00000000,
++0xe10,0xffffffff,0x00000000,
++0xe14,0xffffffff,0x00000000,
++0xe18,0xffffffff,0x00000000,
++0xe1c,0xffffffff,0x00000000,
++0x830,0xffffffff,0x04040404,
++0x834,0xffffffff,0x00020204,
++0x838,0xffffff00,0x00000000,
++0x86c,0x000000ff,0x00000000,
++0x83c,0xffffffff,0x00000000,
++0x848,0xffffffff,0x00000000,
++0x84c,0xffffffff,0x00000000,
++0x868,0xffffffff,0x00000000,
++0xe00,0xffffffff,0x00000000,
++0xe04,0xffffffff,0x00000000,
++0xe08,0x0000ff00,0x00000000,
++0x86c,0xffffff00,0x00000000,
++0xe10,0xffffffff,0x00000000,
++0xe14,0xffffffff,0x00000000,
++0xe18,0xffffffff,0x00000000,
++0xe1c,0xffffffff,0x00000000,
++0x830,0xffffffff,0x00000000,
++0x834,0xffffffff,0x00000000,
++0x838,0xffffff00,0x00000000,
++0x86c,0x000000ff,0x00000000,
++0x83c,0xffffffff,0x00000000,
++0x848,0xffffffff,0x00000000,
++0x84c,0xffffffff,0x00000000,
++0x868,0xffffffff,0x00000000,
++};
++
++u32 Rtl8192CUPHY_REG_Array_MP[PHY_REG_Array_MPLength] = {
++0xc30,0x69e9ac4a,
++0xc3c,0x0a979718,
++};
++
++u32 Rtl8192CUPHY_REG_1T_HPArray[PHY_REG_1T_HPArrayLength] = {
++0x024,0x0011800f,
++0x028,0x00ffdb83,
++0x040,0x000c0004,
++0x800,0x80040000,
++0x804,0x00000001,
++0x808,0x0000fc00,
++0x80c,0x0000000a,
++0x810,0x10000330, //for Broadcom AP IOT
++0x814,0x020c3d10,
++0x818,0x02200385,
++0x81c,0x00000000,
++0x820,0x01000100,
++0x824,0x00390204,
++0x828,0x00000000,
++0x82c,0x00000000,
++0x830,0x00000000,
++0x834,0x00000000,
++0x838,0x00000000,
++0x83c,0x00000000,
++0x840,0x00010000,
++0x844,0x00000000,
++0x848,0x00000000,
++0x84c,0x00000000,
++0x850,0x00000000,
++0x854,0x00000000,
++0x858,0x569a569a,
++0x85c,0x001b25a4,
++0x860,0x66e60230,
++0x864,0x061f0130,
++0x868,0x00000000,
++0x86c,0x20202000,
++0x870,0x03000300,
++0x874,0x22004000,
++0x878,0x00000808,
++0x87c,0x00ffc3f1,
++0x880,0xc0083070,
++0x884,0x000004d5,
++0x888,0x00000000,
++0x88c,0xccc000c0,
++0x890,0x00000800,
++0x894,0xfffffffe,
++0x898,0x40302010,
++0x89c,0x00706050,
++0x900,0x00000000,
++0x904,0x00000023,
++0x908,0x00000000,
++0x90c,0x81121111,
++0xa00,0x00d047c8,
++0xa04,0x80ff000c,
++0xa08,0x8c838300,
++0xa0c,0x2e68120f,
++0xa10,0x9500bb78,
++0xa14,0x11144028,
++0xa18,0x00881117,
++0xa1c,0x89140f00,
++0xa20,0x15160000,
++0xa24,0x070b0f12,
++0xa28,0x00000104,
++0xa2c,0x00d30000,
++0xa70,0x101fbf00,
++0xa74,0x00000007,
++0xc00,0x48071d40,
++0xc04,0x03a05611,
++0xc08,0x000000e4,
++0xc0c,0x6c6c6c6c,
++0xc10,0x08800000,
++0xc14,0x40000100,
++0xc18,0x08800000,
++0xc1c,0x40000100,
++0xc20,0x00000000,
++0xc24,0x00000000,
++0xc28,0x00000000,
++0xc2c,0x00000000,
++0xc30,0x69e9ac44,
++0xc34,0x469652cf,
++0xc38,0x49795994,
++0xc3c,0x0a97971c,
++0xc40,0x1f7c403f,
++0xc44,0x000100b7,
++0xc48,0xec020107,
++0xc4c,0x007f037f,
++0xc50,0x6954342e,
++0xc54,0x43bc0094,
++0xc58,0x6954342f,
++0xc5c,0x433c0094,
++0xc60,0x00000000,
++0xc64,0x5116848b,
++0xc68,0x47c00bff,
++0xc6c,0x00000036,
++0xc70,0x2c46000d,
++0xc74,0x018610db,
++0xc78,0x0000001f,
++0xc7c,0x00b91612,
++0xc80,0x24000090,
++0xc84,0x20f60000,
++0xc88,0x24000090,
++0xc8c,0x20200000,
++0xc90,0x00121820,
++0xc94,0x00000000,
++0xc98,0x00121820,
++0xc9c,0x00007f7f,
++0xca0,0x00000000,
++0xca4,0x00000080,
++0xca8,0x00000000,
++0xcac,0x00000000,
++0xcb0,0x00000000,
++0xcb4,0x00000000,
++0xcb8,0x00000000,
++0xcbc,0x28000000,
++0xcc0,0x00000000,
++0xcc4,0x00000000,
++0xcc8,0x00000000,
++0xccc,0x00000000,
++0xcd0,0x00000000,
++0xcd4,0x00000000,
++0xcd8,0x64b22427,
++0xcdc,0x00766932,
++0xce0,0x00222222,
++0xce4,0x00000000,
++0xce8,0x37644302,
++0xcec,0x2f97d40c,
++0xd00,0x00000740,
++0xd04,0x00020401,
++0xd08,0x0000907f,
++0xd0c,0x20010201,
++0xd10,0xa0633333,
++0xd14,0x3333bc43,
++0xd18,0x7a8f5b6b,
++0xd2c,0xcc979975,
++0xd30,0x00000000,
++0xd34,0x80608000,
++0xd38,0x00000000,
++0xd3c,0x00027293,
++0xd40,0x00000000,
++0xd44,0x00000000,
++0xd48,0x00000000,
++0xd4c,0x00000000,
++0xd50,0x6437140a,
++0xd54,0x00000000,
++0xd58,0x00000000,
++0xd5c,0x30032064,
++0xd60,0x4653de68,
++0xd64,0x04518a3c,
++0xd68,0x00002101,
++0xd6c,0x2a201c16,
++0xd70,0x1812362e,
++0xd74,0x322c2220,
++0xd78,0x000e3c24,
++0xe00,0x24242424,
++0xe04,0x24242424,
++0xe08,0x03902024,
++0xe10,0x24242424,
++0xe14,0x24242424,
++0xe18,0x24242424,
++0xe1c,0x24242424,
++0xe28,0x00000000,
++0xe30,0x1000dc1f,
++0xe34,0x10008c1f,
++0xe38,0x02140102,
++0xe3c,0x681604c2,
++0xe40,0x01007c00,
++0xe44,0x01004800,
++0xe48,0xfb000000,
++0xe4c,0x000028d1,
++0xe50,0x1000dc1f,
++0xe54,0x10008c1f,
++0xe58,0x02140102,
++0xe5c,0x28160d05,
++0xe60,0x00000008,
++0xe68,0x001b25a4,
++0xe6c,0x631b25a0,
++0xe70,0x631b25a0,
++0xe74,0x081b25a0,
++0xe78,0x081b25a0,
++0xe7c,0x081b25a0,
++0xe80,0x081b25a0,
++0xe84,0x631b25a0,
++0xe88,0x081b25a0,
++0xe8c,0x631b25a0,
++0xed0,0x631b25a0,
++0xed4,0x631b25a0,
++0xed8,0x631b25a0,
++0xedc,0x001b25a0,
++0xee0,0x001b25a0,
++0xeec,0x6b1b25a0,
++0xee8,0x31555448,
++0xf14,0x00000003,
++0xf4c,0x00000000,
++0xf00,0x00000300,
++};
++
++u32 Rtl8192CUPHY_REG_1T_mCardArray[PHY_REG_1T_mCardArrayLength] = {
++0x024,0x0011800d,
++0x028,0x00ffdb83,
++0x800,0x80040000,
++0x804,0x00000001,
++0x808,0x0000fc00,
++0x80c,0x0000000a,
++0x810,0x10000330, //for Broadcom AP IOT
++0x814,0x020c3d10,
++0x818,0x02200385,
++0x81c,0x00000000,
++0x820,0x01000100,
++0x824,0x00390004,
++0x828,0x00000000,
++0x82c,0x00000000,
++0x830,0x00000000,
++0x834,0x00000000,
++0x838,0x00000000,
++0x83c,0x00000000,
++0x840,0x00010000,
++0x844,0x00000000,
++0x848,0x00000000,
++0x84c,0x00000000,
++0x850,0x00000000,
++0x854,0x00000000,
++0x858,0x569a569a,
++0x85c,0x001b25a4,
++0x860,0x66e60230,
++0x864,0x061f0130,
++0x868,0x00000000,
++0x86c,0x32323200,
++0x870,0x07000700,
++0x874,0x22004000,
++0x878,0x00000808,
++0x87c,0x00000000,
++0x880,0xc0083070,
++0x884,0x000004d5,
++0x888,0x00000000,
++0x88c,0xccc000c0,
++0x890,0x00000800,
++0x894,0xfffffffe,
++0x898,0x40302010,
++0x89c,0x00706050,
++0x900,0x00000000,
++0x904,0x00000023,
++0x908,0x00000000,
++0x90c,0x81121111,
++0xa00,0x00d047c8,
++0xa04,0x80ff000c,
++0xa08,0x8c838300,
++0xa0c,0x2e68120f,
++0xa10,0x9500bb78,
++0xa14,0x11144028,
++0xa18,0x00881117,
++0xa1c,0x89140f00,
++0xa20,0x1a1b0000,
++0xa24,0x090e1317,
++0xa28,0x00000204,
++0xa2c,0x00d30000,
++0xa70,0x101fbf00,
++0xa74,0x00000007,
++0xc00,0x48071d40,
++0xc04,0x03a05611,
++0xc08,0x000000e4,
++0xc0c,0x6c6c6c6c,
++0xc10,0x08800000,
++0xc14,0x40000100,
++0xc18,0x08800000,
++0xc1c,0x40000100,
++0xc20,0x00000000,
++0xc24,0x00000000,
++0xc28,0x00000000,
++0xc2c,0x00000000,
++0xc30,0x69e9ac44,
++0xc34,0x469652cf,
++0xc38,0x49795994,
++0xc3c,0x0a97971c,
++0xc40,0x1f7c403f,
++0xc44,0x000100b7,
++0xc48,0xec020107,
++0xc4c,0x007f037f,
++0xc50,0x69543420,
++0xc54,0x43bc0094,
++0xc58,0x69543420,
++0xc5c,0x433c0094,
++0xc60,0x00000000,
++0xc64,0x5116848b,
++0xc68,0x47c00bff,
++0xc6c,0x00000036,
++0xc70,0x2c7f000d,
++0xc74,0x018610db,
++0xc78,0x0000001f,
++0xc7c,0x00b91612,
++0xc80,0x40000100,
++0xc84,0x20f60000,
++0xc88,0x40000100,
++0xc8c,0x20200000,
++0xc90,0x00121820,
++0xc94,0x00000000,
++0xc98,0x00121820,
++0xc9c,0x00007f7f,
++0xca0,0x00000000,
++0xca4,0x00000080,
++0xca8,0x00000000,
++0xcac,0x00000000,
++0xcb0,0x00000000,
++0xcb4,0x00000000,
++0xcb8,0x00000000,
++0xcbc,0x28000000,
++0xcc0,0x00000000,
++0xcc4,0x00000000,
++0xcc8,0x00000000,
++0xccc,0x00000000,
++0xcd0,0x00000000,
++0xcd4,0x00000000,
++0xcd8,0x64b22427,
++0xcdc,0x00766932,
++0xce0,0x00222222,
++0xce4,0x00000000,
++0xce8,0x37644302,
++0xcec,0x2f97d40c,
++0xd00,0x00000740,
++0xd04,0x00020401,
++0xd08,0x0000907f,
++0xd0c,0x20010201,
++0xd10,0xa0633333,
++0xd14,0x3333bc43,
++0xd18,0x7a8f5b6b,
++0xd2c,0xcc979975,
++0xd30,0x00000000,
++0xd34,0x80608000,
++0xd38,0x00000000,
++0xd3c,0x00027293,
++0xd40,0x00000000,
++0xd44,0x00000000,
++0xd48,0x00000000,
++0xd4c,0x00000000,
++0xd50,0x6437140a,
++0xd54,0x00000000,
++0xd58,0x00000000,
++0xd5c,0x30032064,
++0xd60,0x4653de68,
++0xd64,0x04518a3c,
++0xd68,0x00002101,
++0xd6c,0x2a201c16,
++0xd70,0x1812362e,
++0xd74,0x322c2220,
++0xd78,0x000e3c24,
++0xe00,0x2a2a2a2a,
++0xe04,0x2a2a2a2a,
++0xe08,0x03902a2a,
++0xe10,0x2a2a2a2a,
++0xe14,0x2a2a2a2a,
++0xe18,0x2a2a2a2a,
++0xe1c,0x2a2a2a2a,
++0xe28,0x00000000,
++0xe30,0x1000dc1f,
++0xe34,0x10008c1f,
++0xe38,0x02140102,
++0xe3c,0x681604c2,
++0xe40,0x01007c00,
++0xe44,0x01004800,
++0xe48,0xfb000000,
++0xe4c,0x000028d1,
++0xe50,0x1000dc1f,
++0xe54,0x10008c1f,
++0xe58,0x02140102,
++0xe5c,0x28160d05,
++0xe60,0x00000008,
++0xe68,0x001b25a4,
++0xe6c,0x631b25a0,
++0xe70,0x631b25a0,
++0xe74,0x081b25a0,
++0xe78,0x081b25a0,
++0xe7c,0x081b25a0,
++0xe80,0x081b25a0,
++0xe84,0x631b25a0,
++0xe88,0x081b25a0,
++0xe8c,0x631b25a0,
++0xed0,0x631b25a0,
++0xed4,0x631b25a0,
++0xed8,0x631b25a0,
++0xedc,0x001b25a0,
++0xee0,0x001b25a0,
++0xeec,0x6b1b25a0,
++0xf14,0x00000003,
++0xf4c,0x00000000,
++0xf00,0x00000300,
++};
++
++u32 Rtl8192CUPHY_REG_2T_mCardArray[PHY_REG_2T_mCardArrayLength] = {
++0x024,0x0011800d,
++0x028,0x00ffdb83,
++0x800,0x80040002,
++0x804,0x00000003,
++0x808,0x0000fc00,
++0x80c,0x0000000a,
++0x810,0x10000330, //for Broadcom AP IOT
++0x814,0x020c3d10,
++0x818,0x02200385,
++0x81c,0x00000000,
++0x820,0x01000100,
++0x824,0x00390004,
++0x828,0x01000100,
++0x82c,0x00390004,
++0x830,0x27272727,
++0x834,0x27272727,
++0x838,0x27272727,
++0x83c,0x27272727,
++0x840,0x00010000,
++0x844,0x00010000,
++0x848,0x27272727,
++0x84c,0x27272727,
++0x850,0x00000000,
++0x854,0x00000000,
++0x858,0x569a569a,
++0x85c,0x0c1b25a4,
++0x860,0x66e60230,
++0x864,0x061f0130,
++0x868,0x27272727,
++0x86c,0x2b2b2b27,
++0x870,0x07000700,
++0x874,0x22184000,
++0x878,0x08080808,
++0x87c,0x00000000,
++0x880,0xc0083070,
++0x884,0x000004d5,
++0x888,0x00000000,
++0x88c,0xcc0000c0,
++0x890,0x00000800,
++0x894,0xfffffffe,
++0x898,0x40302010,
++0x89c,0x00706050,
++0x900,0x00000000,
++0x904,0x00000023,
++0x908,0x00000000,
++0x90c,0x81121313,
++0xa00,0x00d047c8,
++0xa04,0x80ff000c,
++0xa08,0x8c838300,
++0xa0c,0x2e68120f,
++0xa10,0x9500bb78,
++0xa14,0x11144028,
++0xa18,0x00881117,
++0xa1c,0x89140f00,
++0xa20,0x1a1b0000,
++0xa24,0x090e1317,
++0xa28,0x00000204,
++0xa2c,0x00d30000,
++0xa70,0x101fbf00,
++0xa74,0x00000007,
++0xc00,0x48071d40,
++0xc04,0x03a05633,
++0xc08,0x000000e4,
++0xc0c,0x6c6c6c6c,
++0xc10,0x08800000,
++0xc14,0x40000100,
++0xc18,0x08800000,
++0xc1c,0x40000100,
++0xc20,0x00000000,
++0xc24,0x00000000,
++0xc28,0x00000000,
++0xc2c,0x00000000,
++0xc30,0x69e9ac44,
++0xc34,0x469652cf,
++0xc38,0x49795994,
++0xc3c,0x0a97971c,
++0xc40,0x1f7c403f,
++0xc44,0x000100b7,
++0xc48,0xec020107,
++0xc4c,0x007f037f,
++0xc50,0x69543420,
++0xc54,0x43bc0094,
++0xc58,0x69543420,
++0xc5c,0x433c0094,
++0xc60,0x00000000,
++0xc64,0x5116848b,
++0xc68,0x47c00bff,
++0xc6c,0x00000036,
++0xc70,0x2c7f000d,
++0xc74,0x218610db,
++0xc78,0x0000001f,
++0xc7c,0x00b91612,
++0xc80,0x40000100,
++0xc84,0x20f60000,
++0xc88,0x40000100,
++0xc8c,0xa0e40000,
++0xc90,0x00121820,
++0xc94,0x00000000,
++0xc98,0x00121820,
++0xc9c,0x00007f7f,
++0xca0,0x00000000,
++0xca4,0x00000080,
++0xca8,0x00000000,
++0xcac,0x00000000,
++0xcb0,0x00000000,
++0xcb4,0x00000000,
++0xcb8,0x00000000,
++0xcbc,0x28000000,
++0xcc0,0x00000000,
++0xcc4,0x00000000,
++0xcc8,0x00000000,
++0xccc,0x00000000,
++0xcd0,0x00000000,
++0xcd4,0x00000000,
++0xcd8,0x64b22427,
++0xcdc,0x00766932,
++0xce0,0x00222222,
++0xce4,0x00000000,
++0xce8,0x37644302,
++0xcec,0x2f97d40c,
++0xd00,0x00080740,
++0xd04,0x00020403,
++0xd08,0x0000907f,
++0xd0c,0x20010201,
++0xd10,0xa0633333,
++0xd14,0x3333bc43,
++0xd18,0x7a8f5b6b,
++0xd2c,0xcc979975,
++0xd30,0x00000000,
++0xd34,0x80608000,
++0xd38,0x00000000,
++0xd3c,0x00027293,
++0xd40,0x00000000,
++0xd44,0x00000000,
++0xd48,0x00000000,
++0xd4c,0x00000000,
++0xd50,0x6437140a,
++0xd54,0x00000000,
++0xd58,0x00000000,
++0xd5c,0x30032064,
++0xd60,0x4653de68,
++0xd64,0x04518a3c,
++0xd68,0x00002101,
++0xd6c,0x2a201c16,
++0xd70,0x1812362e,
++0xd74,0x322c2220,
++0xd78,0x000e3c24,
++0xe00,0x2a2a2a2a,
++0xe04,0x2a2a2a2a,
++0xe08,0x03902a2a,
++0xe10,0x2a2a2a2a,
++0xe14,0x2a2a2a2a,
++0xe18,0x2a2a2a2a,
++0xe1c,0x2a2a2a2a,
++0xe28,0x00000000,
++0xe30,0x1000dc1f,
++0xe34,0x10008c1f,
++0xe38,0x02140102,
++0xe3c,0x681604c2,
++0xe40,0x01007c00,
++0xe44,0x01004800,
++0xe48,0xfb000000,
++0xe4c,0x000028d1,
++0xe50,0x1000dc1f,
++0xe54,0x10008c1f,
++0xe58,0x02140102,
++0xe5c,0x28160d05,
++0xe60,0x00000010,
++0xe68,0x001b25a4,
++0xe6c,0x63db25a4,
++0xe70,0x63db25a4,
++0xe74,0x0c1b25a4,
++0xe78,0x0c1b25a4,
++0xe7c,0x0c1b25a4,
++0xe80,0x0c1b25a4,
++0xe84,0x63db25a4,
++0xe88,0x0c1b25a4,
++0xe8c,0x63db25a4,
++0xed0,0x63db25a4,
++0xed4,0x63db25a4,
++0xed8,0x63db25a4,
++0xedc,0x001b25a4,
++0xee0,0x001b25a4,
++0xeec,0x6fdb25a4,
++0xf14,0x00000003,
++0xf4c,0x00000000,
++0xf00,0x00000300,
++};
++
++u32 Rtl8192CUPHY_REG_Array_PG_HP[PHY_REG_Array_PG_HPLength] = {
++0xe00,0xffffffff,0x06080808,
++0xe04,0xffffffff,0x00040406,
++0xe08,0x0000ff00,0x00000000,
++0x86c,0xffffff00,0x00000000,
++0xe10,0xffffffff,0x04060608,
++0xe14,0xffffffff,0x00020204,
++0xe18,0xffffffff,0x04060608,
++0xe1c,0xffffffff,0x00020204,
++0x830,0xffffffff,0x06080808,
++0x834,0xffffffff,0x00040406,
++0x838,0xffffff00,0x00000000,
++0x86c,0x000000ff,0x00000000,
++0x83c,0xffffffff,0x04060608,
++0x848,0xffffffff,0x00020204,
++0x84c,0xffffffff,0x04060608,
++0x868,0xffffffff,0x00020204,
++0xe00,0xffffffff,0x00000000,
++0xe04,0xffffffff,0x00000000,
++0xe08,0x0000ff00,0x00000000,
++0x86c,0xffffff00,0x00000000,
++0xe10,0xffffffff,0x00000000,
++0xe14,0xffffffff,0x00000000,
++0xe18,0xffffffff,0x00000000,
++0xe1c,0xffffffff,0x00000000,
++0x830,0xffffffff,0x00000000,
++0x834,0xffffffff,0x00000000,
++0x838,0xffffff00,0x00000000,
++0x86c,0x000000ff,0x00000000,
++0x83c,0xffffffff,0x00000000,
++0x848,0xffffffff,0x00000000,
++0x84c,0xffffffff,0x00000000,
++0x868,0xffffffff,0x00000000,
++0xe00,0xffffffff,0x00000000,
++0xe04,0xffffffff,0x00000000,
++0xe08,0x0000ff00,0x00000000,
++0x86c,0xffffff00,0x00000000,
++0xe10,0xffffffff,0x00000000,
++0xe14,0xffffffff,0x00000000,
++0xe18,0xffffffff,0x00000000,
++0xe1c,0xffffffff,0x00000000,
++0x830,0xffffffff,0x00000000,
++0x834,0xffffffff,0x00000000,
++0x838,0xffffff00,0x00000000,
++0x86c,0x000000ff,0x00000000,
++0x83c,0xffffffff,0x00000000,
++0x848,0xffffffff,0x00000000,
++0x84c,0xffffffff,0x00000000,
++0x868,0xffffffff,0x00000000,
++0xe00,0xffffffff,0x00000000,
++0xe04,0xffffffff,0x00000000,
++0xe08,0x0000ff00,0x00000000,
++0x86c,0xffffff00,0x00000000,
++0xe10,0xffffffff,0x00000000,
++0xe14,0xffffffff,0x00000000,
++0xe18,0xffffffff,0x00000000,
++0xe1c,0xffffffff,0x00000000,
++0x830,0xffffffff,0x00000000,
++0x834,0xffffffff,0x00000000,
++0x838,0xffffff00,0x00000000,
++0x86c,0x000000ff,0x00000000,
++0x83c,0xffffffff,0x00000000,
++0x848,0xffffffff,0x00000000,
++0x84c,0xffffffff,0x00000000,
++0x868,0xffffffff,0x00000000,
++0xe00,0xffffffff,0x00000000,
++0xe04,0xffffffff,0x00000000,
++0xe08,0x0000ff00,0x00000000,
++0x86c,0xffffff00,0x00000000,
++0xe10,0xffffffff,0x00000000,
++0xe14,0xffffffff,0x00000000,
++0xe18,0xffffffff,0x00000000,
++0xe1c,0xffffffff,0x00000000,
++0x830,0xffffffff,0x00000000,
++0x834,0xffffffff,0x00000000,
++0x838,0xffffff00,0x00000000,
++0x86c,0x000000ff,0x00000000,
++0x83c,0xffffffff,0x00000000,
++0x848,0xffffffff,0x00000000,
++0x84c,0xffffffff,0x00000000,
++0x868,0xffffffff,0x00000000,
++0xe00,0xffffffff,0x00000000,
++0xe04,0xffffffff,0x00000000,
++0xe08,0x0000ff00,0x00000000,
++0x86c,0xffffff00,0x00000000,
++0xe10,0xffffffff,0x00000000,
++0xe14,0xffffffff,0x00000000,
++0xe18,0xffffffff,0x00000000,
++0xe1c,0xffffffff,0x00000000,
++0x830,0xffffffff,0x00000000,
++0x834,0xffffffff,0x00000000,
++0x838,0xffffff00,0x00000000,
++0x86c,0x000000ff,0x00000000,
++0x83c,0xffffffff,0x00000000,
++0x848,0xffffffff,0x00000000,
++0x84c,0xffffffff,0x00000000,
++0x868,0xffffffff,0x00000000,
++0xe00,0xffffffff,0x00000000,
++0xe04,0xffffffff,0x00000000,
++0xe08,0x0000ff00,0x00000000,
++0x86c,0xffffff00,0x00000000,
++0xe10,0xffffffff,0x00000000,
++0xe14,0xffffffff,0x00000000,
++0xe18,0xffffffff,0x00000000,
++0xe1c,0xffffffff,0x00000000,
++0x830,0xffffffff,0x00000000,
++0x834,0xffffffff,0x00000000,
++0x838,0xffffff00,0x00000000,
++0x86c,0x000000ff,0x00000000,
++0x83c,0xffffffff,0x00000000,
++0x848,0xffffffff,0x00000000,
++0x84c,0xffffffff,0x00000000,
++0x868,0xffffffff,0x00000000,
++};
++
++u32 Rtl8192CURadioA_2TArray[RadioA_2TArrayLength] = {
++0x000,0x00030159,
++0x001,0x00031284,
++0x002,0x00098000,
++0x003,0x00018c63,
++0x004,0x000210e7,
++0x009,0x0002044f,
++0x00a,0x0001adb1,
++0x00b,0x00054867,
++0x00c,0x0008992e,
++0x00d,0x0000e52c,
++0x00e,0x00039ce7,
++0x00f,0x00000451,
++0x019,0x00000000,
++0x01a,0x00010255,
++0x01b,0x00060a00,
++0x01c,0x000fc378,
++0x01d,0x000a1250,
++0x01e,0x0004445f,
++0x01f,0x00080001,
++0x020,0x0000b614,
++0x021,0x0006c000,
++0x022,0x00000000,
++0x023,0x00001558,
++0x024,0x00000060,
++0x025,0x00000483,
++0x026,0x0004f000,
++0x027,0x000ec7d9,
++0x028,0x000577c0,
++0x029,0x00004783,
++0x02a,0x00000001,
++0x02b,0x00021334,
++0x02a,0x00000000,
++0x02b,0x00000054,
++0x02a,0x00000001,
++0x02b,0x00000808,
++0x02b,0x00053333,
++0x02c,0x0000000c,
++0x02a,0x00000002,
++0x02b,0x00000808,
++0x02b,0x0005b333,
++0x02c,0x0000000d,
++0x02a,0x00000003,
++0x02b,0x00000808,
++0x02b,0x00063333,
++0x02c,0x0000000d,
++0x02a,0x00000004,
++0x02b,0x00000808,
++0x02b,0x0006b333,
++0x02c,0x0000000d,
++0x02a,0x00000005,
++0x02b,0x00000808,
++0x02b,0x00073333,
++0x02c,0x0000000d,
++0x02a,0x00000006,
++0x02b,0x00000709,
++0x02b,0x0005b333,
++0x02c,0x0000000d,
++0x02a,0x00000007,
++0x02b,0x00000709,
++0x02b,0x00063333,
++0x02c,0x0000000d,
++0x02a,0x00000008,
++0x02b,0x0000060a,
++0x02b,0x0004b333,
++0x02c,0x0000000d,
++0x02a,0x00000009,
++0x02b,0x0000060a,
++0x02b,0x00053333,
++0x02c,0x0000000d,
++0x02a,0x0000000a,
++0x02b,0x0000060a,
++0x02b,0x0005b333,
++0x02c,0x0000000d,
++0x02a,0x0000000b,
++0x02b,0x0000060a,
++0x02b,0x00063333,
++0x02c,0x0000000d,
++0x02a,0x0000000c,
++0x02b,0x0000060a,
++0x02b,0x0006b333,
++0x02c,0x0000000d,
++0x02a,0x0000000d,
++0x02b,0x0000060a,
++0x02b,0x00073333,
++0x02c,0x0000000d,
++0x02a,0x0000000e,
++0x02b,0x0000050b,
++0x02b,0x00066666,
++0x02c,0x0000001a,
++0x02a,0x000e0000,
++0x010,0x0004000f,
++0x011,0x000e31fc,
++0x010,0x0006000f,
++0x011,0x000ff9f8,
++0x010,0x0002000f,
++0x011,0x000203f9,
++0x010,0x0003000f,
++0x011,0x000ff500,
++0x010,0x00000000,
++0x011,0x00000000,
++0x010,0x0008000f,
++0x011,0x0003f100,
++0x010,0x0009000f,
++0x011,0x00023100,
++0x012,0x00032000,
++0x012,0x00071000,
++0x012,0x000b0000,
++0x012,0x000fc000,
++0x013,0x000287b3,
++0x013,0x000244b7,
++0x013,0x000204ab,
++0x013,0x0001c49f,
++0x013,0x00018493,
++0x013,0x0001429b,
++0x013,0x00010299,
++0x013,0x0000c29c,
++0x013,0x000081a0,
++0x013,0x000040ac,
++0x013,0x00000020,
++0x014,0x0001944c,
++0x014,0x00059444,
++0x014,0x0009944c,
++0x014,0x000d9444,
++0x015,0x0000f424,
++0x015,0x0004f424,
++0x015,0x0008f424,
++0x015,0x000cf424,
++0x016,0x000e0330,
++0x016,0x000a0330,
++0x016,0x00060330,
++0x016,0x00020330,
++0x000,0x00010159,
++0x018,0x0000f401,
++0x0fe,0x00000000,
++0x0fe,0x00000000,
++0x01f,0x00080003,
++0x0fe,0x00000000,
++0x0fe,0x00000000,
++0x01e,0x00044457,
++0x01f,0x00080000,
++0x000,0x00030159,
++};
++
++u32 Rtl8192CURadioB_2TArray[RadioB_2TArrayLength] = {
++0x000,0x00030159,
++0x001,0x00031284,
++0x002,0x00098000,
++0x003,0x00018c63,
++0x004,0x000210e7,
++0x009,0x0002044f,
++0x00a,0x0001adb1,
++0x00b,0x00054867,
++0x00c,0x0008992e,
++0x00d,0x0000e52c,
++0x00e,0x00039ce7,
++0x00f,0x00000451,
++0x012,0x00032000,
++0x012,0x00071000,
++0x012,0x000b0000,
++0x012,0x000fc000,
++0x013,0x000287af,
++0x013,0x000244b7,
++0x013,0x000204ab,
++0x013,0x0001c49f,
++0x013,0x00018493,
++0x013,0x00014297,
++0x013,0x00010295,
++0x013,0x0000c298,
++0x013,0x0000819c,
++0x013,0x000040a8,
++0x013,0x0000001c,
++0x014,0x0001944c,
++0x014,0x00059444,
++0x014,0x0009944c,
++0x014,0x000d9444,
++0x015,0x0000f424,
++0x015,0x0004f424,
++0x015,0x0008f424,
++0x015,0x000cf424,
++0x016,0x000e0330,
++0x016,0x000a0330,
++0x016,0x00060330,
++0x016,0x00020330,
++};
++
++u32 Rtl8192CURadioA_1TArray[RadioA_1TArrayLength] = {
++0x000,0x00030159,
++0x001,0x00031284,
++0x002,0x00098000,
++0x003,0x00018c63,
++0x004,0x000210e7,
++0x009,0x0002044f,
++0x00a,0x0001adb1,
++0x00b,0x00054867,
++0x00c,0x0008992e,
++0x00d,0x0000e52c,
++0x00e,0x00039ce7,
++0x00f,0x00000451,
++0x019,0x00000000,
++0x01a,0x00010255,
++0x01b,0x00060a00,
++0x01c,0x000fc378,
++0x01d,0x000a1250,
++0x01e,0x0004445f,
++0x01f,0x00080001,
++0x020,0x0000b614,
++0x021,0x0006c000,
++0x022,0x00000000,
++0x023,0x00001558,
++0x024,0x00000060,
++0x025,0x00000483,
++0x026,0x0004f000,
++0x027,0x000ec7d9,
++0x028,0x000577c0,
++0x029,0x00004783,
++0x02a,0x00000001,
++0x02b,0x00021334,
++0x02a,0x00000000,
++0x02b,0x00000054,
++0x02a,0x00000001,
++0x02b,0x00000808,
++0x02b,0x00053333,
++0x02c,0x0000000c,
++0x02a,0x00000002,
++0x02b,0x00000808,
++0x02b,0x0005b333,
++0x02c,0x0000000d,
++0x02a,0x00000003,
++0x02b,0x00000808,
++0x02b,0x00063333,
++0x02c,0x0000000d,
++0x02a,0x00000004,
++0x02b,0x00000808,
++0x02b,0x0006b333,
++0x02c,0x0000000d,
++0x02a,0x00000005,
++0x02b,0x00000808,
++0x02b,0x00073333,
++0x02c,0x0000000d,
++0x02a,0x00000006,
++0x02b,0x00000709,
++0x02b,0x0005b333,
++0x02c,0x0000000d,
++0x02a,0x00000007,
++0x02b,0x00000709,
++0x02b,0x00063333,
++0x02c,0x0000000d,
++0x02a,0x00000008,
++0x02b,0x0000060a,
++0x02b,0x0004b333,
++0x02c,0x0000000d,
++0x02a,0x00000009,
++0x02b,0x0000060a,
++0x02b,0x00053333,
++0x02c,0x0000000d,
++0x02a,0x0000000a,
++0x02b,0x0000060a,
++0x02b,0x0005b333,
++0x02c,0x0000000d,
++0x02a,0x0000000b,
++0x02b,0x0000060a,
++0x02b,0x00063333,
++0x02c,0x0000000d,
++0x02a,0x0000000c,
++0x02b,0x0000060a,
++0x02b,0x0006b333,
++0x02c,0x0000000d,
++0x02a,0x0000000d,
++0x02b,0x0000060a,
++0x02b,0x00073333,
++0x02c,0x0000000d,
++0x02a,0x0000000e,
++0x02b,0x0000050b,
++0x02b,0x00066666,
++0x02c,0x0000001a,
++0x02a,0x000e0000,
++0x010,0x0004000f,
++0x011,0x000e31fc,
++0x010,0x0006000f,
++0x011,0x000ff9f8,
++0x010,0x0002000f,
++0x011,0x000203f9,
++0x010,0x0003000f,
++0x011,0x000ff500,
++0x010,0x00000000,
++0x011,0x00000000,
++0x010,0x0008000f,
++0x011,0x0003f100,
++0x010,0x0009000f,
++0x011,0x00023100,
++0x012,0x00032000,
++0x012,0x00071000,
++0x012,0x000b0000,
++0x012,0x000fc000,
++0x013,0x000287b3,
++0x013,0x000244b7,
++0x013,0x000204ab,
++0x013,0x0001c49f,
++0x013,0x00018493,
++0x013,0x0001429b,
++0x013,0x00010299,
++0x013,0x0000c29c,
++0x013,0x000081a0,
++0x013,0x000040ac,
++0x013,0x00000020,
++0x014,0x0001944c,
++0x014,0x00059444,
++0x014,0x0009944c,
++0x014,0x000d9444,
++0x015,0x0000f405,
++0x015,0x0004f405,
++0x015,0x0008f405,
++0x015,0x000cf405,
++0x016,0x000e0330,
++0x016,0x000a0330,
++0x016,0x00060330,
++0x016,0x00020330,
++0x000,0x00010159,
++0x018,0x0000f401,
++0x0fe,0x00000000,
++0x0fe,0x00000000,
++0x01f,0x00080003,
++0x0fe,0x00000000,
++0x0fe,0x00000000,
++0x01e,0x00044457,
++0x01f,0x00080000,
++0x000,0x00030159,
++};
++
++u32 Rtl8192CURadioB_1TArray[RadioB_1TArrayLength] = {
++0x0, };
++
++
++u32 Rtl8192CURadioA_2T_mCardArray[RadioA_2T_mCardArrayLength] = {
++0x000,0x00030159,
++0x001,0x00031284,
++0x002,0x00098000,
++0x003,0x00018c63,
++0x004,0x000210e7,
++0x009,0x0002044f,
++0x00a,0x0001adb1,
++0x00b,0x00054867,
++0x00c,0x0008992e,
++0x00d,0x0000e52c,
++0x00e,0x00039ce7,
++0x00f,0x00000451,
++0x019,0x00000000,
++0x01a,0x00010255,
++0x01b,0x00060a00,
++0x01c,0x000fc378,
++0x01d,0x000a1250,
++0x01e,0x0004445f,
++0x01f,0x00080001,
++0x020,0x0000b614,
++0x021,0x0006c000,
++0x022,0x00000000,
++0x023,0x00001558,
++0x024,0x00000060,
++0x025,0x00000483,
++0x026,0x0004f000,
++0x027,0x000ec7d9,
++0x028,0x000577c0,
++0x029,0x00004783,
++0x02a,0x00000001,
++0x02b,0x00021334,
++0x02a,0x00000000,
++0x02b,0x00000054,
++0x02a,0x00000001,
++0x02b,0x00000808,
++0x02b,0x00053333,
++0x02c,0x0000000c,
++0x02a,0x00000002,
++0x02b,0x00000808,
++0x02b,0x0005b333,
++0x02c,0x0000000d,
++0x02a,0x00000003,
++0x02b,0x00000808,
++0x02b,0x00063333,
++0x02c,0x0000000d,
++0x02a,0x00000004,
++0x02b,0x00000808,
++0x02b,0x0006b333,
++0x02c,0x0000000d,
++0x02a,0x00000005,
++0x02b,0x00000808,
++0x02b,0x00073333,
++0x02c,0x0000000d,
++0x02a,0x00000006,
++0x02b,0x00000709,
++0x02b,0x0005b333,
++0x02c,0x0000000d,
++0x02a,0x00000007,
++0x02b,0x00000709,
++0x02b,0x00063333,
++0x02c,0x0000000d,
++0x02a,0x00000008,
++0x02b,0x0000060a,
++0x02b,0x0004b333,
++0x02c,0x0000000d,
++0x02a,0x00000009,
++0x02b,0x0000060a,
++0x02b,0x00053333,
++0x02c,0x0000000d,
++0x02a,0x0000000a,
++0x02b,0x0000060a,
++0x02b,0x0005b333,
++0x02c,0x0000000d,
++0x02a,0x0000000b,
++0x02b,0x0000060a,
++0x02b,0x00063333,
++0x02c,0x0000000d,
++0x02a,0x0000000c,
++0x02b,0x0000060a,
++0x02b,0x0006b333,
++0x02c,0x0000000d,
++0x02a,0x0000000d,
++0x02b,0x0000060a,
++0x02b,0x00073333,
++0x02c,0x0000000d,
++0x02a,0x0000000e,
++0x02b,0x0000050b,
++0x02b,0x00066666,
++0x02c,0x0000001a,
++0x02a,0x000e0000,
++0x010,0x0004000f,
++0x011,0x000e31fc,
++0x010,0x0006000f,
++0x011,0x000ff9f8,
++0x010,0x0002000f,
++0x011,0x000203f9,
++0x010,0x0003000f,
++0x011,0x000ff500,
++0x010,0x00000000,
++0x011,0x00000000,
++0x010,0x0008000f,
++0x011,0x0003f100,
++0x010,0x0009000f,
++0x011,0x00023100,
++0x012,0x00032000,
++0x012,0x00071000,
++0x012,0x000b0000,
++0x012,0x000fc000,
++0x013,0x000287b3,
++0x013,0x000244b7,
++0x013,0x000204ab,
++0x013,0x0001c49f,
++0x013,0x00018493,
++0x013,0x0001429b,
++0x013,0x00010299,
++0x013,0x0000c29c,
++0x013,0x000081a0,
++0x013,0x000040ac,
++0x013,0x00000020,
++0x014,0x0001944c,
++0x014,0x00059444,
++0x014,0x0009944c,
++0x014,0x000d9444,
++0x015,0x0000f424,
++0x015,0x0004f424,
++0x015,0x0008f424,
++0x015,0x000cf424,
++0x016,0x000e0330,
++0x016,0x000a0330,
++0x016,0x00060330,
++0x016,0x00020330,
++0x000,0x00010159,
++0x018,0x0000f401,
++0x0fe,0x00000000,
++0x0fe,0x00000000,
++0x01f,0x00080003,
++0x0fe,0x00000000,
++0x0fe,0x00000000,
++0x01e,0x00044457,
++0x01f,0x00080000,
++0x000,0x00030159,
++};
++
++u32 Rtl8192CURadioB_2T_mCardArray[RadioB_2T_mCardArrayLength] = {
++0x000,0x00030159,
++0x001,0x00031284,
++0x002,0x00098000,
++0x003,0x00018c63,
++0x004,0x000210e7,
++0x009,0x0002044f,
++0x00a,0x0001adb1,
++0x00b,0x00054867,
++0x00c,0x0008992e,
++0x00d,0x0000e52c,
++0x00e,0x00039ce7,
++0x00f,0x00000451,
++0x012,0x00032000,
++0x012,0x00071000,
++0x012,0x000b0000,
++0x012,0x000fc000,
++0x013,0x000287af,
++0x013,0x000244b7,
++0x013,0x000204ab,
++0x013,0x0001c49f,
++0x013,0x00018493,
++0x013,0x00014297,
++0x013,0x00010295,
++0x013,0x0000c298,
++0x013,0x0000819c,
++0x013,0x000040a8,
++0x013,0x0000001c,
++0x014,0x0001944c,
++0x014,0x00059444,
++0x014,0x0009944c,
++0x014,0x000d9444,
++0x015,0x0000f424,
++0x015,0x0004f424,
++0x015,0x0008f424,
++0x015,0x000cf424,
++0x016,0x000e0330,
++0x016,0x000a0330,
++0x016,0x00060330,
++0x016,0x00020330,
++};
++
++u32 Rtl8192CURadioA_1T_mCardArray[RadioA_1T_mCardArrayLength] = {
++0x000,0x00030159,
++0x001,0x00031284,
++0x002,0x00098000,
++0x003,0x00018c63,
++0x004,0x000210e7,
++0x009,0x0002044f,
++0x00a,0x0001adb1,
++0x00b,0x00054867,
++0x00c,0x0008992e,
++0x00d,0x0000e52c,
++0x00e,0x00039ce7,
++0x00f,0x00000451,
++0x019,0x00000000,
++0x01a,0x00010255,
++0x01b,0x00060a00,
++0x01c,0x000fc378,
++0x01d,0x000a1250,
++0x01e,0x0004445f,
++0x01f,0x00080001,
++0x020,0x0000b614,
++0x021,0x0006c000,
++0x022,0x00000000,
++0x023,0x00001558,
++0x024,0x00000060,
++0x025,0x00000483,
++0x026,0x0004f200,
++0x027,0x000ec7d9,
++0x028,0x000577c0,
++0x029,0x00004783,
++0x02a,0x00000001,
++0x02b,0x00021334,
++0x02a,0x00000000,
++0x02b,0x00000054,
++0x02a,0x00000001,
++0x02b,0x00000808,
++0x02b,0x00053333,
++0x02c,0x0000000c,
++0x02a,0x00000002,
++0x02b,0x00000808,
++0x02b,0x0005b333,
++0x02c,0x0000000d,
++0x02a,0x00000003,
++0x02b,0x00000808,
++0x02b,0x00063333,
++0x02c,0x0000000d,
++0x02a,0x00000004,
++0x02b,0x00000808,
++0x02b,0x0006b333,
++0x02c,0x0000000d,
++0x02a,0x00000005,
++0x02b,0x00000808,
++0x02b,0x00073333,
++0x02c,0x0000000d,
++0x02a,0x00000006,
++0x02b,0x00000709,
++0x02b,0x0005b333,
++0x02c,0x0000000d,
++0x02a,0x00000007,
++0x02b,0x00000709,
++0x02b,0x00063333,
++0x02c,0x0000000d,
++0x02a,0x00000008,
++0x02b,0x0000060a,
++0x02b,0x0004b333,
++0x02c,0x0000000d,
++0x02a,0x00000009,
++0x02b,0x0000060a,
++0x02b,0x00053333,
++0x02c,0x0000000d,
++0x02a,0x0000000a,
++0x02b,0x0000060a,
++0x02b,0x0005b333,
++0x02c,0x0000000d,
++0x02a,0x0000000b,
++0x02b,0x0000060a,
++0x02b,0x00063333,
++0x02c,0x0000000d,
++0x02a,0x0000000c,
++0x02b,0x0000060a,
++0x02b,0x0006b333,
++0x02c,0x0000000d,
++0x02a,0x0000000d,
++0x02b,0x0000060a,
++0x02b,0x00073333,
++0x02c,0x0000000d,
++0x02a,0x0000000e,
++0x02b,0x0000050b,
++0x02b,0x00066666,
++0x02c,0x0000001a,
++0x02a,0x000e0000,
++0x010,0x0004000f,
++0x011,0x000e31fc,
++0x010,0x0006000f,
++0x011,0x000ff9f8,
++0x010,0x0002000f,
++0x011,0x000203f9,
++0x010,0x0003000f,
++0x011,0x000ff500,
++0x010,0x00000000,
++0x011,0x00000000,
++0x010,0x0008000f,
++0x011,0x0003f100,
++0x010,0x0009000f,
++0x011,0x00023100,
++0x012,0x00032000,
++0x012,0x00071000,
++0x012,0x000b0000,
++0x012,0x000fc000,
++0x013,0x000287b3,
++0x013,0x000244b7,
++0x013,0x000204ab,
++0x013,0x0001c49f,
++0x013,0x00018493,
++0x013,0x0001429b,
++0x013,0x00010299,
++0x013,0x0000c29c,
++0x013,0x000081a0,
++0x013,0x000040ac,
++0x013,0x00000020,
++0x014,0x0001944c,
++0x014,0x00059444,
++0x014,0x0009944c,
++0x014,0x000d9444,
++0x015,0x0000f424,
++0x015,0x0004f424,
++0x015,0x0008f424,
++0x015,0x000cf424,
++0x016,0x000e0330,
++0x016,0x000a0330,
++0x016,0x00060330,
++0x016,0x00020330,
++0x000,0x00010159,
++0x018,0x0000f401,
++0x0fe,0x00000000,
++0x0fe,0x00000000,
++0x01f,0x00080003,
++0x0fe,0x00000000,
++0x0fe,0x00000000,
++0x01e,0x00044457,
++0x01f,0x00080000,
++0x000,0x00030159,
++};
++
++u32 Rtl8192CURadioB_1T_mCardArray[RadioB_1T_mCardArrayLength] = {
++0x0, };
++
++u32 Rtl8192CURadioA_1T_HPArray[RadioA_1T_HPArrayLength] = {
++0x000,0x00030159,
++0x001,0x00031284,
++0x002,0x00098000,
++0x003,0x00018c63,
++0x004,0x000210e7,
++0x009,0x0002044f,
++0x00a,0x0001adb0,
++0x00b,0x00054867,
++0x00c,0x0008992e,
++0x00d,0x0000e529,
++0x00e,0x00039ce7,
++0x00f,0x00000451,
++0x019,0x00000000,
++0x01a,0x00000255,
++0x01b,0x00060a00,
++0x01c,0x000fc378,
++0x01d,0x000a1250,
++0x01e,0x0004445f,
++0x01f,0x00080001,
++0x020,0x0000b614,
++0x021,0x0006c000,
++0x022,0x0000083c,
++0x023,0x00001558,
++0x024,0x00000060,
++0x025,0x00000483,
++0x026,0x0004f000,
++0x027,0x000ec7d9,
++0x028,0x000977c0,
++0x029,0x00004783,
++0x02a,0x00000001,
++0x02b,0x00021334,
++0x02a,0x00000000,
++0x02b,0x00000054,
++0x02a,0x00000001,
++0x02b,0x00000808,
++0x02b,0x00053333,
++0x02c,0x0000000c,
++0x02a,0x00000002,
++0x02b,0x00000808,
++0x02b,0x0005b333,
++0x02c,0x0000000d,
++0x02a,0x00000003,
++0x02b,0x00000808,
++0x02b,0x00063333,
++0x02c,0x0000000d,
++0x02a,0x00000004,
++0x02b,0x00000808,
++0x02b,0x0006b333,
++0x02c,0x0000000d,
++0x02a,0x00000005,
++0x02b,0x00000808,
++0x02b,0x00073333,
++0x02c,0x0000000d,
++0x02a,0x00000006,
++0x02b,0x00000709,
++0x02b,0x0005b333,
++0x02c,0x0000000d,
++0x02a,0x00000007,
++0x02b,0x00000709,
++0x02b,0x00063333,
++0x02c,0x0000000d,
++0x02a,0x00000008,
++0x02b,0x0000060a,
++0x02b,0x0004b333,
++0x02c,0x0000000d,
++0x02a,0x00000009,
++0x02b,0x0000060a,
++0x02b,0x00053333,
++0x02c,0x0000000d,
++0x02a,0x0000000a,
++0x02b,0x0000060a,
++0x02b,0x0005b333,
++0x02c,0x0000000d,
++0x02a,0x0000000b,
++0x02b,0x0000060a,
++0x02b,0x00063333,
++0x02c,0x0000000d,
++0x02a,0x0000000c,
++0x02b,0x0000060a,
++0x02b,0x0006b333,
++0x02c,0x0000000d,
++0x02a,0x0000000d,
++0x02b,0x0000060a,
++0x02b,0x00073333,
++0x02c,0x0000000d,
++0x02a,0x0000000e,
++0x02b,0x0000050b,
++0x02b,0x00066666,
++0x02c,0x0000001a,
++0x02a,0x000e0000,
++0x010,0x0004000f,
++0x011,0x000e31fc,
++0x010,0x0006000f,
++0x011,0x000ff9f8,
++0x010,0x0002000f,
++0x011,0x000203f9,
++0x010,0x0003000f,
++0x011,0x000ff500,
++0x010,0x00000000,
++0x011,0x00000000,
++0x010,0x0008000f,
++0x011,0x0003f100,
++0x010,0x0009000f,
++0x011,0x00023100,
++0x012,0x000d8000,
++0x012,0x00090000,
++0x012,0x00051000,
++0x012,0x00012000,
++0x013,0x00028fb4,
++0x013,0x00024fa8,
++0x013,0x000207a4,
++0x013,0x0001c3b0,
++0x013,0x000183a4,
++0x013,0x00014398,
++0x013,0x000101a4,
++0x013,0x0000c198,
++0x013,0x000080a4,
++0x013,0x00004098,
++0x013,0x00000000,
++0x014,0x0001944c,
++0x014,0x00059444,
++0x014,0x0009944c,
++0x014,0x000d9444,
++0x015,0x0000f405,
++0x015,0x0004f405,
++0x015,0x0008f405,
++0x015,0x000cf405,
++0x016,0x000e0330,
++0x016,0x000a0330,
++0x016,0x00060330,
++0x016,0x00020330,
++0x000,0x00010159,
++0x018,0x0000f401,
++0x0fe,0x00000000,
++0x0fe,0x00000000,
++0x01f,0x00080003,
++0x0fe,0x00000000,
++0x0fe,0x00000000,
++0x01e,0x00044457,
++0x01f,0x00080000,
++0x000,0x00030159,
++};
++
++u32 Rtl8192CURadioB_GM_Array[RadioB_GM_ArrayLength] = {
++0x0, };
++
++// MAC reg V14 - 2011-11-23
++u32 Rtl8192CUMAC_2T_Array[MAC_2T_ArrayLength] = {
++0x420,0x00000080,
++0x423,0x00000000,
++0x430,0x00000000,
++0x431,0x00000000,
++0x432,0x00000000,
++0x433,0x00000001,
++0x434,0x00000004,
++0x435,0x00000005,
++0x436,0x00000006,
++0x437,0x00000007,
++0x438,0x00000000,
++0x439,0x00000000,
++0x43a,0x00000000,
++0x43b,0x00000001,
++0x43c,0x00000004,
++0x43d,0x00000005,
++0x43e,0x00000006,
++0x43f,0x00000007,
++0x440,0x0000005d,
++0x441,0x00000001,
++0x442,0x00000000,
++0x444,0x00000015,
++0x445,0x000000f0,
++0x446,0x0000000f,
++0x447,0x00000000,
++0x458,0x00000041,
++0x459,0x000000a8,
++0x45a,0x00000072,
++0x45b,0x000000b9,
++0x460,0x00000066,
++0x461,0x00000066,
++0x462,0x00000008,
++0x463,0x00000003,
++0x4c8,0x000000ff,
++0x4c9,0x00000008,
++0x4cc,0x000000ff,
++0x4cd,0x000000ff,
++0x4ce,0x00000001,
++0x500,0x00000026,
++0x501,0x000000a2,
++0x502,0x0000002f,
++0x503,0x00000000,
++0x504,0x00000028,
++0x505,0x000000a3,
++0x506,0x0000005e,
++0x507,0x00000000,
++0x508,0x0000002b,
++0x509,0x000000a4,
++0x50a,0x0000005e,
++0x50b,0x00000000,
++0x50c,0x0000004f,
++0x50d,0x000000a4,
++0x50e,0x00000000,
++0x50f,0x00000000,
++0x512,0x0000001c,
++0x514,0x0000000a,
++0x515,0x00000010,
++0x516,0x0000000a,
++0x517,0x00000010,
++0x51a,0x00000016,
++0x524,0x0000000f,
++0x525,0x0000004f,
++0x546,0x00000040,
++0x547,0x00000000,
++0x550,0x00000010,
++0x551,0x00000010,
++0x559,0x00000002,
++0x55a,0x00000002,
++0x55d,0x000000ff,
++0x605,0x00000030,
++0x608,0x0000000e,
++0x609,0x0000002a,
++0x652,0x00000020,
++0x652,0x00000020,
++0x63c,0x00000008,
++0x63d,0x00000008,
++0x63e,0x0000000c,
++0x63f,0x0000000c,
++0x66e,0x00000005,
++0x700,0x00000021,
++0x701,0x00000043,
++0x702,0x00000065,
++0x703,0x00000087,
++0x708,0x00000021,
++0x709,0x00000043,
++0x70a,0x00000065,
++0x70b,0x00000087,
++};
++
++u32 Rtl8192CUMACPHY_Array_PG[MACPHY_Array_PGLength] = {
++0x0, };
++
++u32 Rtl8192CUAGCTAB_2TArray[AGCTAB_2TArrayLength] = {
++0xc78,0x7b000001,
++0xc78,0x7b010001,
++0xc78,0x7b020001,
++0xc78,0x7b030001,
++0xc78,0x7b040001,
++0xc78,0x7b050001,
++0xc78,0x7a060001,
++0xc78,0x79070001,
++0xc78,0x78080001,
++0xc78,0x77090001,
++0xc78,0x760a0001,
++0xc78,0x750b0001,
++0xc78,0x740c0001,
++0xc78,0x730d0001,
++0xc78,0x720e0001,
++0xc78,0x710f0001,
++0xc78,0x70100001,
++0xc78,0x6f110001,
++0xc78,0x6e120001,
++0xc78,0x6d130001,
++0xc78,0x6c140001,
++0xc78,0x6b150001,
++0xc78,0x6a160001,
++0xc78,0x69170001,
++0xc78,0x68180001,
++0xc78,0x67190001,
++0xc78,0x661a0001,
++0xc78,0x651b0001,
++0xc78,0x641c0001,
++0xc78,0x631d0001,
++0xc78,0x621e0001,
++0xc78,0x611f0001,
++0xc78,0x60200001,
++0xc78,0x49210001,
++0xc78,0x48220001,
++0xc78,0x47230001,
++0xc78,0x46240001,
++0xc78,0x45250001,
++0xc78,0x44260001,
++0xc78,0x43270001,
++0xc78,0x42280001,
++0xc78,0x41290001,
++0xc78,0x402a0001,
++0xc78,0x262b0001,
++0xc78,0x252c0001,
++0xc78,0x242d0001,
++0xc78,0x232e0001,
++0xc78,0x222f0001,
++0xc78,0x21300001,
++0xc78,0x20310001,
++0xc78,0x06320001,
++0xc78,0x05330001,
++0xc78,0x04340001,
++0xc78,0x03350001,
++0xc78,0x02360001,
++0xc78,0x01370001,
++0xc78,0x00380001,
++0xc78,0x00390001,
++0xc78,0x003a0001,
++0xc78,0x003b0001,
++0xc78,0x003c0001,
++0xc78,0x003d0001,
++0xc78,0x003e0001,
++0xc78,0x003f0001,
++0xc78,0x7b400001,
++0xc78,0x7b410001,
++0xc78,0x7b420001,
++0xc78,0x7b430001,
++0xc78,0x7b440001,
++0xc78,0x7b450001,
++0xc78,0x7a460001,
++0xc78,0x79470001,
++0xc78,0x78480001,
++0xc78,0x77490001,
++0xc78,0x764a0001,
++0xc78,0x754b0001,
++0xc78,0x744c0001,
++0xc78,0x734d0001,
++0xc78,0x724e0001,
++0xc78,0x714f0001,
++0xc78,0x70500001,
++0xc78,0x6f510001,
++0xc78,0x6e520001,
++0xc78,0x6d530001,
++0xc78,0x6c540001,
++0xc78,0x6b550001,
++0xc78,0x6a560001,
++0xc78,0x69570001,
++0xc78,0x68580001,
++0xc78,0x67590001,
++0xc78,0x665a0001,
++0xc78,0x655b0001,
++0xc78,0x645c0001,
++0xc78,0x635d0001,
++0xc78,0x625e0001,
++0xc78,0x615f0001,
++0xc78,0x60600001,
++0xc78,0x49610001,
++0xc78,0x48620001,
++0xc78,0x47630001,
++0xc78,0x46640001,
++0xc78,0x45650001,
++0xc78,0x44660001,
++0xc78,0x43670001,
++0xc78,0x42680001,
++0xc78,0x41690001,
++0xc78,0x406a0001,
++0xc78,0x266b0001,
++0xc78,0x256c0001,
++0xc78,0x246d0001,
++0xc78,0x236e0001,
++0xc78,0x226f0001,
++0xc78,0x21700001,
++0xc78,0x20710001,
++0xc78,0x06720001,
++0xc78,0x05730001,
++0xc78,0x04740001,
++0xc78,0x03750001,
++0xc78,0x02760001,
++0xc78,0x01770001,
++0xc78,0x00780001,
++0xc78,0x00790001,
++0xc78,0x007a0001,
++0xc78,0x007b0001,
++0xc78,0x007c0001,
++0xc78,0x007d0001,
++0xc78,0x007e0001,
++0xc78,0x007f0001,
++0xc78,0x3800001e,
++0xc78,0x3801001e,
++0xc78,0x3802001e,
++0xc78,0x3803001e,
++0xc78,0x3804001e,
++0xc78,0x3805001e,
++0xc78,0x3806001e,
++0xc78,0x3807001e,
++0xc78,0x3808001e,
++0xc78,0x3c09001e,
++0xc78,0x3e0a001e,
++0xc78,0x400b001e,
++0xc78,0x440c001e,
++0xc78,0x480d001e,
++0xc78,0x4c0e001e,
++0xc78,0x500f001e,
++0xc78,0x5210001e,
++0xc78,0x5611001e,
++0xc78,0x5a12001e,
++0xc78,0x5e13001e,
++0xc78,0x6014001e,
++0xc78,0x6015001e,
++0xc78,0x6016001e,
++0xc78,0x6217001e,
++0xc78,0x6218001e,
++0xc78,0x6219001e,
++0xc78,0x621a001e,
++0xc78,0x621b001e,
++0xc78,0x621c001e,
++0xc78,0x621d001e,
++0xc78,0x621e001e,
++0xc78,0x621f001e,
++};
++
++u32 Rtl8192CUAGCTAB_1TArray[AGCTAB_1TArrayLength] = {
++0xc78,0x7b000001,
++0xc78,0x7b010001,
++0xc78,0x7b020001,
++0xc78,0x7b030001,
++0xc78,0x7b040001,
++0xc78,0x7b050001,
++0xc78,0x7a060001,
++0xc78,0x79070001,
++0xc78,0x78080001,
++0xc78,0x77090001,
++0xc78,0x760a0001,
++0xc78,0x750b0001,
++0xc78,0x740c0001,
++0xc78,0x730d0001,
++0xc78,0x720e0001,
++0xc78,0x710f0001,
++0xc78,0x70100001,
++0xc78,0x6f110001,
++0xc78,0x6e120001,
++0xc78,0x6d130001,
++0xc78,0x6c140001,
++0xc78,0x6b150001,
++0xc78,0x6a160001,
++0xc78,0x69170001,
++0xc78,0x68180001,
++0xc78,0x67190001,
++0xc78,0x661a0001,
++0xc78,0x651b0001,
++0xc78,0x641c0001,
++0xc78,0x631d0001,
++0xc78,0x621e0001,
++0xc78,0x611f0001,
++0xc78,0x60200001,
++0xc78,0x49210001,
++0xc78,0x48220001,
++0xc78,0x47230001,
++0xc78,0x46240001,
++0xc78,0x45250001,
++0xc78,0x44260001,
++0xc78,0x43270001,
++0xc78,0x42280001,
++0xc78,0x41290001,
++0xc78,0x402a0001,
++0xc78,0x262b0001,
++0xc78,0x252c0001,
++0xc78,0x242d0001,
++0xc78,0x232e0001,
++0xc78,0x222f0001,
++0xc78,0x21300001,
++0xc78,0x20310001,
++0xc78,0x06320001,
++0xc78,0x05330001,
++0xc78,0x04340001,
++0xc78,0x03350001,
++0xc78,0x02360001,
++0xc78,0x01370001,
++0xc78,0x00380001,
++0xc78,0x00390001,
++0xc78,0x003a0001,
++0xc78,0x003b0001,
++0xc78,0x003c0001,
++0xc78,0x003d0001,
++0xc78,0x003e0001,
++0xc78,0x003f0001,
++0xc78,0x7b400001,
++0xc78,0x7b410001,
++0xc78,0x7b420001,
++0xc78,0x7b430001,
++0xc78,0x7b440001,
++0xc78,0x7b450001,
++0xc78,0x7a460001,
++0xc78,0x79470001,
++0xc78,0x78480001,
++0xc78,0x77490001,
++0xc78,0x764a0001,
++0xc78,0x754b0001,
++0xc78,0x744c0001,
++0xc78,0x734d0001,
++0xc78,0x724e0001,
++0xc78,0x714f0001,
++0xc78,0x70500001,
++0xc78,0x6f510001,
++0xc78,0x6e520001,
++0xc78,0x6d530001,
++0xc78,0x6c540001,
++0xc78,0x6b550001,
++0xc78,0x6a560001,
++0xc78,0x69570001,
++0xc78,0x68580001,
++0xc78,0x67590001,
++0xc78,0x665a0001,
++0xc78,0x655b0001,
++0xc78,0x645c0001,
++0xc78,0x635d0001,
++0xc78,0x625e0001,
++0xc78,0x615f0001,
++0xc78,0x60600001,
++0xc78,0x49610001,
++0xc78,0x48620001,
++0xc78,0x47630001,
++0xc78,0x46640001,
++0xc78,0x45650001,
++0xc78,0x44660001,
++0xc78,0x43670001,
++0xc78,0x42680001,
++0xc78,0x41690001,
++0xc78,0x406a0001,
++0xc78,0x266b0001,
++0xc78,0x256c0001,
++0xc78,0x246d0001,
++0xc78,0x236e0001,
++0xc78,0x226f0001,
++0xc78,0x21700001,
++0xc78,0x20710001,
++0xc78,0x06720001,
++0xc78,0x05730001,
++0xc78,0x04740001,
++0xc78,0x03750001,
++0xc78,0x02760001,
++0xc78,0x01770001,
++0xc78,0x00780001,
++0xc78,0x00790001,
++0xc78,0x007a0001,
++0xc78,0x007b0001,
++0xc78,0x007c0001,
++0xc78,0x007d0001,
++0xc78,0x007e0001,
++0xc78,0x007f0001,
++0xc78,0x3800001e,
++0xc78,0x3801001e,
++0xc78,0x3802001e,
++0xc78,0x3803001e,
++0xc78,0x3804001e,
++0xc78,0x3805001e,
++0xc78,0x3806001e,
++0xc78,0x3807001e,
++0xc78,0x3808001e,
++0xc78,0x3c09001e,
++0xc78,0x3e0a001e,
++0xc78,0x400b001e,
++0xc78,0x440c001e,
++0xc78,0x480d001e,
++0xc78,0x4c0e001e,
++0xc78,0x500f001e,
++0xc78,0x5210001e,
++0xc78,0x5611001e,
++0xc78,0x5a12001e,
++0xc78,0x5e13001e,
++0xc78,0x6014001e,
++0xc78,0x6015001e,
++0xc78,0x6016001e,
++0xc78,0x6217001e,
++0xc78,0x6218001e,
++0xc78,0x6219001e,
++0xc78,0x621a001e,
++0xc78,0x621b001e,
++0xc78,0x621c001e,
++0xc78,0x621d001e,
++0xc78,0x621e001e,
++0xc78,0x621f001e,
++};
++
++u32 Rtl8192CUAGCTAB_1T_HPArray[AGCTAB_1T_HPArrayLength] = {
++0xc78,0x7b000001,
++0xc78,0x7b010001,
++0xc78,0x7b020001,
++0xc78,0x7b030001,
++0xc78,0x7b040001,
++0xc78,0x7b050001,
++0xc78,0x7b060001,
++0xc78,0x7b070001,
++0xc78,0x7b080001,
++0xc78,0x7a090001,
++0xc78,0x790a0001,
++0xc78,0x780b0001,
++0xc78,0x770c0001,
++0xc78,0x760d0001,
++0xc78,0x750e0001,
++0xc78,0x740f0001,
++0xc78,0x73100001,
++0xc78,0x72110001,
++0xc78,0x71120001,
++0xc78,0x70130001,
++0xc78,0x6f140001,
++0xc78,0x6e150001,
++0xc78,0x6d160001,
++0xc78,0x6c170001,
++0xc78,0x6b180001,
++0xc78,0x6a190001,
++0xc78,0x691a0001,
++0xc78,0x681b0001,
++0xc78,0x671c0001,
++0xc78,0x661d0001,
++0xc78,0x651e0001,
++0xc78,0x641f0001,
++0xc78,0x63200001,
++0xc78,0x62210001,
++0xc78,0x61220001,
++0xc78,0x60230001,
++0xc78,0x46240001,
++0xc78,0x45250001,
++0xc78,0x44260001,
++0xc78,0x43270001,
++0xc78,0x42280001,
++0xc78,0x41290001,
++0xc78,0x402a0001,
++0xc78,0x262b0001,
++0xc78,0x252c0001,
++0xc78,0x242d0001,
++0xc78,0x232e0001,
++0xc78,0x222f0001,
++0xc78,0x21300001,
++0xc78,0x20310001,
++0xc78,0x06320001,
++0xc78,0x05330001,
++0xc78,0x04340001,
++0xc78,0x03350001,
++0xc78,0x02360001,
++0xc78,0x01370001,
++0xc78,0x00380001,
++0xc78,0x00390001,
++0xc78,0x003a0001,
++0xc78,0x003b0001,
++0xc78,0x003c0001,
++0xc78,0x003d0001,
++0xc78,0x003e0001,
++0xc78,0x003f0001,
++0xc78,0x7b400001,
++0xc78,0x7b410001,
++0xc78,0x7b420001,
++0xc78,0x7b430001,
++0xc78,0x7b440001,
++0xc78,0x7b450001,
++0xc78,0x7b460001,
++0xc78,0x7b470001,
++0xc78,0x7b480001,
++0xc78,0x7a490001,
++0xc78,0x794a0001,
++0xc78,0x784b0001,
++0xc78,0x774c0001,
++0xc78,0x764d0001,
++0xc78,0x754e0001,
++0xc78,0x744f0001,
++0xc78,0x73500001,
++0xc78,0x72510001,
++0xc78,0x71520001,
++0xc78,0x70530001,
++0xc78,0x6f540001,
++0xc78,0x6e550001,
++0xc78,0x6d560001,
++0xc78,0x6c570001,
++0xc78,0x6b580001,
++0xc78,0x6a590001,
++0xc78,0x695a0001,
++0xc78,0x685b0001,
++0xc78,0x675c0001,
++0xc78,0x665d0001,
++0xc78,0x655e0001,
++0xc78,0x645f0001,
++0xc78,0x63600001,
++0xc78,0x62610001,
++0xc78,0x61620001,
++0xc78,0x60630001,
++0xc78,0x46640001,
++0xc78,0x45650001,
++0xc78,0x44660001,
++0xc78,0x43670001,
++0xc78,0x42680001,
++0xc78,0x41690001,
++0xc78,0x406a0001,
++0xc78,0x266b0001,
++0xc78,0x256c0001,
++0xc78,0x246d0001,
++0xc78,0x236e0001,
++0xc78,0x226f0001,
++0xc78,0x21700001,
++0xc78,0x20710001,
++0xc78,0x06720001,
++0xc78,0x05730001,
++0xc78,0x04740001,
++0xc78,0x03750001,
++0xc78,0x02760001,
++0xc78,0x01770001,
++0xc78,0x00780001,
++0xc78,0x00790001,
++0xc78,0x007a0001,
++0xc78,0x007b0001,
++0xc78,0x007c0001,
++0xc78,0x007d0001,
++0xc78,0x007e0001,
++0xc78,0x007f0001,
++0xc78,0x3800001e,
++0xc78,0x3801001e,
++0xc78,0x3802001e,
++0xc78,0x3803001e,
++0xc78,0x3804001e,
++0xc78,0x3805001e,
++0xc78,0x3806001e,
++0xc78,0x3807001e,
++0xc78,0x3808001e,
++0xc78,0x3c09001e,
++0xc78,0x3e0a001e,
++0xc78,0x400b001e,
++0xc78,0x440c001e,
++0xc78,0x480d001e,
++0xc78,0x4c0e001e,
++0xc78,0x500f001e,
++0xc78,0x5210001e,
++0xc78,0x5611001e,
++0xc78,0x5a12001e,
++0xc78,0x5e13001e,
++0xc78,0x6014001e,
++0xc78,0x6015001e,
++0xc78,0x6016001e,
++0xc78,0x6217001e,
++0xc78,0x6218001e,
++0xc78,0x6219001e,
++0xc78,0x621a001e,
++0xc78,0x621b001e,
++0xc78,0x621c001e,
++0xc78,0x621d001e,
++0xc78,0x621e001e,
++0xc78,0x621f001e,
++};
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/hal/rtl8192c/usb/Hal8192CUHWImg_wowlan.c linux-xbian-rpi/drivers/net/wireless/rtl8192cu/hal/rtl8192c/usb/Hal8192CUHWImg_wowlan.c
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/hal/rtl8192c/usb/Hal8192CUHWImg_wowlan.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/hal/rtl8192c/usb/Hal8192CUHWImg_wowlan.c 2015-07-28 01:20:58.313625760 +0200
+@@ -0,0 +1,2557 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++/*Created on 2011/11/ 8, 14:15*/
++
++#include <basic_types.h>
++#include "Hal8192CUHWImg_wowlan.h"
++
++
++u8 Rtl8192CUFwTSMCWWImgArray[TSMCWWImgArrayLength] = {
++0xc1,0x88,0x02,0x00,0x51,0x00,0x00,0x00,0x03,0x23,0x16,0x43,0x72,0x34,0x00,0x00,
++0x58,0x92,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x02,0x43,0x9d,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x02,0x57,0xcb,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x02,0x5c,0xb6,0x00,0x00,0x00,0x00,0x00,0x02,0x5d,0x99,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0xbb,0x01,0x0c,0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe0,0x22,0x50,
++0x06,0xe9,0x25,0x82,0xf8,0xe6,0x22,0xbb,0xfe,0x06,0xe9,0x25,0x82,0xf8,0xe2,0x22,
++0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe4,0x93,0x22,0xbb,0x01,0x06,
++0x89,0x82,0x8a,0x83,0xf0,0x22,0x50,0x02,0xf7,0x22,0xbb,0xfe,0x01,0xf3,0x22,0xf8,
++0xbb,0x01,0x0d,0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe8,0xf0,0x22,
++0x50,0x06,0xe9,0x25,0x82,0xc8,0xf6,0x22,0xbb,0xfe,0x05,0xe9,0x25,0x82,0xc8,0xf2,
++0x22,0xc5,0xf0,0xf8,0xa3,0xe0,0x28,0xf0,0xc5,0xf0,0xf8,0xe5,0x82,0x15,0x82,0x70,
++0x02,0x15,0x83,0xe0,0x38,0xf0,0x22,0xbb,0x01,0x10,0xe5,0x82,0x29,0xf5,0x82,0xe5,
++0x83,0x3a,0xf5,0x83,0xe0,0xf5,0xf0,0xa3,0xe0,0x22,0x50,0x09,0xe9,0x25,0x82,0xf8,
++0x86,0xf0,0x08,0xe6,0x22,0xbb,0xfe,0x0a,0xe9,0x25,0x82,0xf8,0xe2,0xf5,0xf0,0x08,
++0xe2,0x22,0xe5,0x83,0x2a,0xf5,0x83,0xe9,0x93,0xf5,0xf0,0xa3,0xe9,0x93,0x22,0xf8,
++0xbb,0x01,0x11,0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe8,0xf0,0xe5,
++0xf0,0xa3,0xf0,0x22,0x50,0x09,0xe9,0x25,0x82,0xc8,0xf6,0x08,0xa6,0xf0,0x22,0xbb,
++0xfe,0x09,0xe9,0x25,0x82,0xc8,0xf2,0xe5,0xf0,0x08,0xf2,0x22,0xef,0x4b,0xff,0xee,
++0x4a,0xfe,0xed,0x49,0xfd,0xec,0x48,0xfc,0x22,0xe0,0xfc,0xa3,0xe0,0xfd,0xa3,0xe0,
++0xfe,0xa3,0xe0,0xff,0x22,0xa4,0x25,0x82,0xf5,0x82,0xe5,0xf0,0x35,0x83,0xf5,0x83,
++0x22,0xe0,0xfb,0xa3,0xe0,0xfa,0xa3,0xe0,0xf9,0x22,0xf8,0xe0,0xfb,0xa3,0xa3,0xe0,
++0xf9,0x25,0xf0,0xf0,0xe5,0x82,0x15,0x82,0x70,0x02,0x15,0x83,0xe0,0xfa,0x38,0xf0,
++0x22,0xeb,0xf0,0xa3,0xea,0xf0,0xa3,0xe9,0xf0,0x22,0xd0,0x83,0xd0,0x82,0xf8,0xe4,
++0x93,0x70,0x12,0x74,0x01,0x93,0x70,0x0d,0xa3,0xa3,0x93,0xf8,0x74,0x01,0x93,0xf5,
++0x82,0x88,0x83,0xe4,0x73,0x74,0x02,0x93,0x68,0x60,0xef,0xa3,0xa3,0xa3,0x80,0xdf,
++0xd0,0x83,0xd0,0x82,0xf8,0xe4,0x93,0x70,0x12,0x74,0x01,0x93,0x70,0x0d,0xa3,0xa3,
++0x93,0xf8,0x74,0x01,0x93,0xf5,0x82,0x88,0x83,0xe4,0x73,0x74,0x02,0x93,0xb5,0xf0,
++0x06,0x74,0x03,0x93,0x68,0x60,0xe9,0xa3,0xa3,0xa3,0xa3,0x80,0xd8,0x02,0x43,0xdb,
++0x02,0x50,0x2a,0xe4,0x93,0xa3,0xf8,0xe4,0x93,0xa3,0x40,0x03,0xf6,0x80,0x01,0xf2,
++0x08,0xdf,0xf4,0x80,0x29,0xe4,0x93,0xa3,0xf8,0x54,0x07,0x24,0x0c,0xc8,0xc3,0x33,
++0xc4,0x54,0x0f,0x44,0x20,0xc8,0x83,0x40,0x04,0xf4,0x56,0x80,0x01,0x46,0xf6,0xdf,
++0xe4,0x80,0x0b,0x01,0x02,0x04,0x08,0x10,0x20,0x40,0x80,0x90,0x44,0x20,0xe4,0x7e,
++0x01,0x93,0x60,0xbc,0xa3,0xff,0x54,0x3f,0x30,0xe5,0x09,0x54,0x1f,0xfe,0xe4,0x93,
++0xa3,0x60,0x01,0x0e,0xcf,0x54,0xc0,0x25,0xe0,0x60,0xa8,0x40,0xb8,0xe4,0x93,0xa3,
++0xfa,0xe4,0x93,0xa3,0xf8,0xe4,0x93,0xa3,0xc8,0xc5,0x82,0xc8,0xca,0xc5,0x83,0xca,
++0xf0,0xa3,0xc8,0xc5,0x82,0xc8,0xca,0xc5,0x83,0xca,0xdf,0xe9,0xde,0xe7,0x80,0xbe,
++0x41,0x91,0x40,0x00,0x41,0x91,0x9c,0x00,0x41,0x91,0x23,0x80,0x41,0x91,0x24,0x80,
++0x41,0x91,0x9e,0x00,0x41,0x91,0x52,0x00,0x41,0x91,0x93,0x00,0x41,0x91,0x91,0x00,
++0x41,0x91,0x90,0x00,0x41,0x91,0x92,0x00,0x00,0xf0,0x90,0x91,0x30,0xe0,0x90,0x91,
++0x67,0xf0,0xe4,0xfb,0xfd,0x7f,0x54,0x7e,0x01,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,
++0x90,0x91,0x65,0xeb,0xf0,0xa3,0xe0,0xfb,0xa3,0xe0,0xf5,0x44,0xe4,0xf5,0x45,0x12,
++0x35,0xab,0xd0,0xd0,0x92,0xaf,0x22,0x90,0x01,0x5f,0xe4,0xf0,0x90,0x01,0x3c,0x74,
++0x08,0xf0,0xe4,0x90,0x91,0x66,0xf0,0x90,0x91,0x2d,0xe0,0x90,0x91,0x67,0xf0,0xe4,
++0xfb,0xfd,0x7f,0x5c,0x7e,0x01,0x91,0x59,0x90,0x01,0x5f,0x74,0x05,0xf0,0x90,0x06,
++0x92,0x74,0x02,0xf0,0x90,0x91,0x36,0x14,0xf0,0xe5,0x6e,0x54,0x0f,0xc3,0x94,0x0c,
++0x50,0x02,0xf1,0x23,0x22,0x90,0x02,0x84,0xef,0xf0,0xa3,0xee,0xf0,0xa3,0x74,0x05,
++0xf0,0x22,0x7d,0x01,0xaf,0x6f,0xe1,0x27,0xf1,0xe6,0xbf,0x01,0x10,0x90,0x91,0x42,
++0xe0,0xff,0xe4,0xfd,0x12,0x48,0x22,0x90,0x04,0x1f,0x74,0x20,0xf0,0x22,0x8f,0x82,
++0x8e,0x83,0xa3,0xa3,0xa3,0xe4,0xf0,0x22,0xe4,0xf5,0x72,0x7f,0x60,0x7e,0x01,0x80,
++0xed,0x7f,0x00,0x22,0x90,0x91,0x53,0xe0,0x54,0xfe,0xf0,0x02,0x50,0xd6,0x22,0xe4,
++0xf5,0x75,0x22,0x02,0x5f,0xe2,0x02,0x5f,0xe9,0xef,0x8e,0xf0,0x71,0x70,0x45,0x26,
++0x00,0x40,0x45,0x4e,0x00,0x80,0x45,0x79,0x01,0x00,0x45,0x8d,0x02,0x00,0x45,0xa5,
++0x04,0x00,0x00,0x00,0x45,0xc2,0xed,0x54,0x3f,0x70,0x04,0xfe,0xff,0x80,0x04,0x7e,
++0x00,0x7f,0x40,0xef,0x2d,0xff,0xee,0x3c,0xfe,0xef,0x78,0x06,0xce,0xc3,0x13,0xce,
++0x13,0xd8,0xf9,0x78,0x06,0xc3,0x33,0xce,0x33,0xce,0xd8,0xf9,0x80,0x26,0xed,0x54,
++0x7f,0x70,0x04,0xfe,0xff,0x80,0x04,0x7e,0x00,0x7f,0x80,0xef,0x2d,0xff,0xee,0x3c,
++0xfe,0xef,0x78,0x07,0xce,0xc3,0x13,0xce,0x13,0xd8,0xf9,0x78,0x07,0xc3,0x33,0xce,
++0x33,0xce,0xd8,0xf9,0xfd,0xac,0x06,0x80,0x49,0xed,0x70,0x04,0xfe,0xff,0x80,0x04,
++0x7e,0x01,0x7f,0x00,0xef,0x2d,0xee,0x3c,0x7d,0x00,0xfc,0x80,0x35,0xec,0x54,0x01,
++0x4d,0x70,0x04,0xfe,0xff,0x80,0x04,0x7e,0x02,0x7f,0x00,0xef,0x2d,0xee,0x3c,0xc3,
++0x13,0x7d,0x00,0x80,0x1a,0xec,0x54,0x03,0x4d,0x70,0x04,0xfe,0xff,0x80,0x04,0x7e,
++0x04,0x7f,0x00,0xef,0x2d,0xee,0x3c,0x13,0x13,0x54,0x3f,0x7d,0x00,0x25,0xe0,0x25,
++0xe0,0xfc,0xae,0x04,0xaf,0x05,0x22,0x90,0x91,0x09,0x12,0x2a,0x8b,0x00,0x00,0x00,
++0x00,0x90,0x06,0xa9,0xe0,0x90,0x91,0x08,0xf0,0xe0,0x54,0xc0,0x70,0x0a,0x53,0x71,
++0xfe,0x53,0x71,0xfd,0x91,0xc2,0x80,0x47,0x90,0x91,0x26,0xe0,0x60,0x41,0x90,0x91,
++0x38,0xe0,0x70,0x3b,0x90,0x91,0x38,0x74,0x01,0xf0,0x7f,0x00,0x7e,0x08,0x12,0x27,
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++0x2a,0x7f,0x7f,0x80,0x7e,0x08,0x12,0x2f,0xd9,0x90,0x00,0x45,0xe0,0x44,0x20,0xfd,
++0x7f,0x45,0x71,0xee,0x90,0x00,0x45,0xe0,0x44,0x10,0xfd,0x7f,0x45,0x71,0xee,0x90,
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++0x62,0xe0,0x90,0x91,0x05,0xf0,0x90,0x05,0x63,0xe0,0x90,0x91,0x06,0xf0,0xa2,0xaf,
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++0x90,0x90,0xf4,0xe0,0x70,0x02,0xa1,0xb2,0x90,0x90,0xf8,0xe0,0x70,0x02,0xa1,0xb2,
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++0x90,0x91,0x1c,0xe0,0x24,0xff,0x92,0xaf,0x71,0xe5,0x90,0x00,0x46,0xe0,0x44,0x01,
++0xfd,0x7f,0x46,0x71,0xee,0x90,0x90,0xed,0xe0,0x60,0x15,0x90,0x90,0xf9,0x12,0x43,
++0x09,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x80,0x7e,0x08,0x12,0x2f,0xd9,0x80,0x06,
++0x90,0x05,0x22,0x74,0x7f,0xf0,0x90,0x00,0x45,0xe0,0x54,0xef,0xfd,0x7f,0x45,0x71,
++0xee,0x90,0x05,0x87,0xe0,0x64,0x80,0xf0,0x90,0x91,0x03,0xe0,0x90,0x05,0x84,0xf0,
++0x90,0x91,0x04,0xe0,0x90,0x05,0x85,0xf0,0x90,0x91,0x05,0xe0,0x90,0x05,0x86,0xf0,
++0x90,0x91,0x06,0xe0,0x90,0x05,0x87,0xf0,0xa2,0xaf,0xe4,0x33,0x90,0x91,0x1c,0xf0,
++0xc2,0xaf,0x90,0x01,0x3c,0xe0,0x44,0x20,0xf0,0x7d,0x20,0xe4,0xff,0x12,0x37,0x00,
++0x80,0x2b,0x90,0x90,0xf5,0xe0,0x70,0x2d,0x90,0x91,0x07,0x71,0xe4,0x90,0x00,0x46,
++0xe0,0x54,0xfe,0xfd,0x7f,0x46,0x71,0xee,0x90,0x05,0x22,0xe4,0xf0,0xa2,0xaf,0x33,
++0x90,0x91,0x1c,0xf0,0xc2,0xaf,0x7d,0x20,0xe4,0xff,0x12,0x36,0x92,0x90,0x91,0x1c,
++0xe0,0x24,0xff,0x92,0xaf,0x22,0x8b,0x0e,0x8a,0x0f,0x89,0x10,0x90,0x00,0x02,0x12,
++0x42,0x20,0x90,0x90,0xf6,0xf0,0xe0,0x30,0xe0,0x4b,0x90,0x90,0xed,0x74,0x01,0xf0,
++0x7f,0x80,0x7e,0x08,0x12,0x27,0xde,0x90,0x90,0xef,0x12,0x2a,0x7f,0xab,0x0e,0xaa,
++0x0f,0xa9,0x10,0x90,0x00,0x01,0x12,0x42,0x20,0xff,0xe4,0xfc,0xfd,0xfe,0x78,0x1a,
++0x12,0x2a,0x6c,0xa8,0x04,0xa9,0x05,0xaa,0x06,0xab,0x07,0x90,0x90,0xef,0x12,0x43,
++0x09,0xec,0x54,0x03,0xfc,0x12,0x42,0xfc,0x90,0x90,0xf9,0x12,0x2a,0x7f,0x90,0x05,
++0x22,0xe4,0xf0,0x80,0x2d,0xe4,0x90,0x90,0xed,0xf0,0x7f,0x80,0x7e,0x08,0x12,0x27,
++0xde,0xec,0x54,0x03,0xfc,0xec,0x44,0xc0,0xfc,0x90,0x90,0xef,0x12,0x2a,0x7f,0x90,
++0x90,0xef,0x12,0x43,0x09,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x80,0x7e,0x08,0x12,
++0x2f,0xd9,0x90,0x90,0xf6,0xe0,0x30,0xe1,0x19,0x7d,0x0c,0x7f,0x47,0x71,0xee,0x90,
++0x00,0x48,0xe0,0x44,0x0c,0xfd,0x7f,0x48,0x71,0xee,0x90,0x00,0x46,0xe0,0x44,0x10,
++0x80,0x1c,0x90,0x00,0x47,0xe0,0x54,0xf3,0xfd,0x7f,0x47,0x71,0xee,0x90,0x00,0x48,
++0xe0,0x54,0xf3,0xfd,0x7f,0x48,0x71,0xee,0x90,0x00,0x46,0xe0,0x54,0xef,0xfd,0x7f,
++0x46,0x71,0xee,0xe4,0x90,0x90,0xf3,0xf0,0x22,0x90,0x01,0x3c,0x74,0xff,0xf0,0xa3,
++0xf0,0xa3,0xf0,0x90,0x01,0x34,0xf0,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0xfd,0x7f,0x54,
++0x71,0xee,0x7d,0xff,0x7f,0x55,0x71,0xee,0x7d,0xff,0x7f,0x56,0x71,0xee,0x7d,0xff,
++0x7f,0x57,0x61,0xee,0x90,0x01,0x30,0xe4,0xf0,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0x90,
++0x01,0x38,0xf0,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0xfd,0x7f,0x50,0x71,0xee,0xe4,0xfd,
++0x7f,0x51,0x71,0xee,0xe4,0xfd,0x7f,0x52,0x71,0xee,0xe4,0xfd,0x7f,0x53,0x61,0xee,
++0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x90,0x91,0x22,0xed,0xf0,0x90,0x91,0x21,0xef,
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++0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xf4,0xff,0x90,0x00,0x47,0xe0,
++0x5f,0xf0,0x80,0x17,0x90,0x91,0x21,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,
++0xc3,0x33,0xd8,0xfc,0xff,0x90,0x00,0x47,0xe0,0x4f,0xf0,0x51,0xe6,0x90,0x91,0x21,
++0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xf4,0xff,0x90,
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++0x91,0x21,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xc4,
++0x54,0xf0,0xf4,0xff,0x90,0x00,0x43,0xe0,0x5f,0xf0,0x80,0x1a,0x90,0x91,0x21,0xe0,
++0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xc4,0x54,0xf0,0xff,
++0x90,0x00,0x43,0xe0,0x4f,0xf0,0x51,0xe6,0x90,0x91,0x21,0xe0,0xff,0x74,0x01,0xa8,
++0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xf4,0xff,0x90,0x00,0x43,0xe0,0x5f,0xf0,
++0x51,0xe6,0xd0,0xd0,0x92,0xaf,0x22,0x90,0x00,0x49,0xe0,0x90,0x91,0x9f,0xf0,0xe0,
++0x54,0x0f,0xf0,0x44,0xf0,0xfd,0x7f,0x49,0x71,0xee,0x90,0x91,0x9f,0xe0,0x44,0xb0,
++0xfd,0x7f,0x49,0x61,0xee,0x12,0x47,0xe6,0xbf,0x01,0x10,0x90,0x02,0x09,0xe0,0xff,
++0x7d,0x01,0x12,0x48,0x22,0x90,0x04,0x1f,0x74,0x20,0xf0,0x22,0x75,0x28,0x33,0xe4,
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++0x91,0x51,0xef,0xf0,0xf1,0x60,0x90,0x91,0x3d,0xee,0xf0,0xa3,0xef,0xf0,0xe4,0xf5,
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++0x71,0x97,0xe5,0x57,0x30,0xe4,0x0a,0xc2,0xaf,0x53,0x57,0xef,0xd2,0xaf,0x12,0x60,
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++0x7f,0xf0,0xa3,0x74,0x0a,0xf0,0x22,0x90,0x06,0x34,0xe0,0x60,0x25,0x14,0x70,0x1b,
++0x7b,0x01,0x7a,0x06,0x79,0x35,0x7f,0xf9,0x7e,0x01,0x12,0x67,0xe4,0xbf,0x01,0x09,
++0x90,0x06,0x35,0xe0,0x54,0x0f,0xf0,0x80,0x04,0x80,0x00,0xe1,0x17,0xe4,0x90,0x06,
++0x34,0xf0,0x22,0x90,0x91,0x56,0xe0,0x54,0xfe,0xf0,0xe0,0x54,0x7f,0xf0,0x90,0x01,
++0x17,0xe0,0xfe,0x90,0x01,0x16,0xe0,0x7c,0x00,0x24,0x00,0xff,0xec,0x3e,0x90,0x91,
++0x5c,0xf0,0xa3,0xef,0xf0,0x90,0x01,0x04,0xe0,0x54,0x0f,0x90,0x91,0x1c,0xf0,0xe0,
++0xff,0x74,0x40,0x7e,0x00,0xa8,0x07,0x08,0x80,0x05,0xc3,0x33,0xce,0x33,0xce,0xd8,
++0xf9,0x90,0x91,0x5b,0xf0,0xee,0x90,0x91,0x5a,0xf0,0x90,0x91,0x5e,0xe0,0x54,0xfe,
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++0x90,0x06,0x09,0xe0,0x54,0xfe,0xf0,0x90,0x02,0x86,0xe0,0x44,0x04,0xf0,0x43,0x57,
++0x04,0x7d,0x08,0xe4,0xff,0x12,0x36,0xe6,0x80,0x12,0x7d,0x08,0xe4,0xff,0x12,0x36,
++0x75,0x90,0x02,0x86,0xe0,0x54,0xfb,0xf0,0x31,0xf1,0x31,0x13,0xd0,0xd0,0x92,0xaf,
++0x22,0x90,0x06,0x90,0xe4,0xf0,0x21,0x5a,0x90,0x91,0x19,0x12,0x43,0x41,0xef,0x12,
++0x43,0x4a,0x52,0x30,0x01,0x52,0x39,0x02,0x52,0x5b,0x03,0x52,0x64,0x09,0x52,0x6c,
++0x0c,0x52,0x75,0x0d,0x52,0x7d,0x0e,0x52,0x8e,0x1a,0x52,0x96,0x2c,0x52,0x41,0x2d,
++0x52,0x4a,0x2e,0x52,0x9e,0x30,0x52,0x53,0x3b,0x52,0x86,0x3c,0x00,0x00,0x52,0xa6,
++0x90,0x91,0x19,0x12,0x43,0x21,0x02,0x64,0x72,0x90,0x91,0x19,0x12,0x43,0x21,0xc1,
++0xf5,0x90,0x91,0x19,0x12,0x43,0x21,0x02,0x65,0x8d,0x90,0x91,0x19,0x12,0x43,0x21,
++0x02,0x65,0xd5,0x90,0x91,0x19,0x12,0x43,0x21,0xe1,0x4b,0x90,0x91,0x19,0x12,0x43,
++0x21,0x02,0x66,0x0e,0x90,0x91,0x19,0x12,0x43,0x21,0x80,0x42,0x90,0x91,0x19,0x12,
++0x43,0x21,0x02,0x4c,0xab,0x90,0x91,0x19,0x12,0x43,0x21,0xe1,0x98,0x90,0x91,0x19,
++0x12,0x43,0x21,0x02,0x4d,0xe6,0x90,0x91,0x19,0x12,0x43,0x21,0x21,0x90,0x90,0x91,
++0x19,0x12,0x43,0x21,0xa1,0x9b,0x90,0x91,0x19,0x12,0x43,0x21,0x81,0x7a,0x90,0x91,
++0x19,0x12,0x43,0x21,0xe1,0x78,0x90,0x01,0xc6,0xe0,0x44,0x01,0xf0,0x22,0xd3,0x10,
++0xaf,0x01,0xc3,0xc0,0xd0,0x90,0x91,0x1c,0x12,0x43,0x41,0x90,0x91,0x1c,0x12,0x43,
++0x21,0x90,0x00,0x01,0x12,0x42,0x97,0xfa,0xe5,0xf0,0x24,0x00,0xff,0xe4,0x3a,0xfe,
++0x90,0x91,0x1c,0x12,0x43,0x21,0x90,0x00,0x01,0xee,0x8f,0xf0,0x12,0x42,0xcf,0x12,
++0x29,0xd9,0xff,0x60,0x2c,0xb5,0x72,0x16,0x90,0x91,0x1c,0x12,0x43,0x21,0x90,0x00,
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++0x1c,0x12,0x43,0x21,0x90,0x00,0x01,0x12,0x42,0x97,0xff,0xae,0xf0,0x71,0x26,0x80,
++0x10,0x90,0x91,0x1c,0x12,0x43,0x21,0x12,0x29,0xd9,0x65,0x72,0x60,0x03,0x12,0x44,
++0xe8,0xd0,0xd0,0x92,0xaf,0x22,0x90,0x91,0x1f,0xee,0xf0,0xa3,0xef,0xf0,0x75,0x72,
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++0x12,0x4f,0x10,0x71,0x6a,0xe4,0xff,0x71,0xcc,0xe4,0xf5,0x76,0x90,0x01,0xc9,0xe5,
++0x76,0xf0,0x90,0x91,0x1f,0xe0,0xfc,0xa3,0xe0,0xfd,0xec,0xfb,0x8d,0x44,0xe4,0xf5,
++0x45,0x7d,0x01,0x7f,0x60,0x7e,0x01,0x02,0x35,0xab,0x7f,0x0b,0x71,0xd9,0xef,0x65,
++0x75,0x60,0x10,0xe5,0x75,0xb4,0x01,0x05,0xe4,0xf5,0x75,0x80,0x03,0x75,0x75,0x01,
++0x7f,0x01,0x22,0x7f,0x00,0x22,0xe5,0x72,0x64,0x01,0x70,0x3f,0x71,0x6a,0xbf,0x01,
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++0xee,0x90,0x00,0x44,0xe0,0x54,0xfb,0xfd,0x7f,0x44,0x12,0x4b,0xee,0x90,0x00,0x46,
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++0x01,0xc9,0xe5,0x76,0xf0,0xb4,0x01,0x03,0x12,0x4f,0xd7,0x22,0x90,0x01,0xca,0xe5,
++0x75,0xf0,0xef,0x60,0x03,0x12,0x4f,0xd7,0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,
++0x90,0x91,0xa0,0xef,0xf0,0xd3,0x94,0x07,0x50,0x47,0xe0,0xff,0x74,0x01,0xa8,0x07,
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++0x4a,0xe6,0x90,0x91,0xa0,0xe0,0xfd,0x74,0x01,0x7e,0x00,0xa8,0x05,0x08,0x80,0x05,
++0xc3,0x33,0xce,0x33,0xce,0xd8,0xf9,0xff,0x90,0x00,0x44,0xe0,0xfb,0xe4,0xfe,0xef,
++0x5b,0xa8,0x05,0x08,0x80,0x06,0xce,0xa2,0xe7,0x13,0xce,0x13,0xd8,0xf8,0xff,0x80,
++0x44,0x90,0x91,0xa0,0xe0,0x24,0xf8,0xf0,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,
++0x02,0xc3,0x33,0xd8,0xfc,0x12,0x4a,0xde,0x90,0x91,0xa0,0xe0,0xfd,0x74,0x01,0x7e,
++0x00,0xa8,0x05,0x08,0x80,0x05,0xc3,0x33,0xce,0x33,0xce,0xd8,0xf9,0xff,0x90,0x00,
++0x42,0xe0,0xfb,0xe4,0xfe,0xef,0x5b,0xa8,0x05,0x08,0x80,0x06,0xce,0xa2,0xe7,0x13,
++0xce,0x13,0xd8,0xf8,0xff,0xd0,0xd0,0x92,0xaf,0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0,
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++0x70,0x70,0x02,0x81,0xb5,0xe5,0x6d,0x64,0x01,0x70,0x7a,0xe5,0x70,0x14,0x60,0x2b,
++0x24,0xfd,0x60,0x27,0x24,0x02,0x24,0xfb,0x50,0x02,0x80,0x21,0x90,0x91,0x27,0xe0,
++0x14,0xf0,0xe0,0x60,0x04,0xa3,0xe0,0x60,0x14,0x90,0x91,0x27,0xe0,0x70,0x08,0x90,
++0x91,0x39,0xe0,0x90,0x91,0x27,0xf0,0x7b,0x01,0x80,0x02,0x7b,0x01,0xeb,0x60,0x45,
++0x43,0x71,0x10,0xe4,0x90,0x91,0x66,0xf0,0x90,0x91,0x3a,0xe0,0x75,0xf0,0x05,0xa4,
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++0x6e,0x54,0x0f,0xc3,0x94,0x04,0x50,0x07,0x7d,0x01,0x7f,0x04,0x12,0x47,0x27,0x90,
++0x91,0x2e,0xe0,0x60,0x10,0x90,0x91,0x2c,0xe0,0x90,0x07,0x78,0x60,0x04,0x74,0x0d,
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++0x74,0x01,0xf0,0xe5,0x3e,0x30,0xe1,0x06,0x90,0x00,0x56,0x74,0x02,0xf0,0xe5,0x3e,
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++0xd9,0x90,0x90,0xe4,0x12,0x43,0x09,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x70,0x7e,
++0x0e,0x12,0x2f,0xd9,0x90,0x80,0x59,0x12,0x2a,0x8b,0x00,0x03,0x2d,0x95,0xe4,0xfd,
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++0x8b,0x00,0x03,0x2d,0x95,0xe4,0xfd,0x7f,0x01,0x12,0x34,0x81,0x22,0x8f,0x77,0xe4,
++0x90,0x91,0x96,0xf0,0xa3,0xf0,0x90,0x01,0x09,0xe0,0x7f,0x00,0x30,0xe7,0x02,0x7f,
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++0x7e,0x0e,0x12,0x27,0xde,0x90,0x90,0x88,0x12,0x2a,0x7f,0x7f,0x70,0x7e,0x0e,0x12,
++0x27,0xde,0x90,0x90,0x8c,0x12,0x2a,0x7f,0x7f,0x74,0x7e,0x0e,0x12,0x27,0xde,0x90,
++0x90,0x90,0x12,0x2a,0x7f,0x7f,0x78,0x7e,0x0e,0x12,0x27,0xde,0x90,0x90,0x94,0x12,
++0x2a,0x7f,0x7f,0x7c,0x7e,0x0e,0x12,0x27,0xde,0x90,0x90,0x98,0x12,0x2a,0x7f,0x7f,
++0x80,0x7e,0x0e,0x12,0x27,0xde,0x90,0x90,0x9c,0x12,0x2a,0x7f,0x7f,0x84,0x7e,0x0e,
++0x12,0x27,0xde,0x90,0x90,0xa0,0x12,0x2a,0x7f,0x7f,0x88,0x7e,0x0e,0x12,0x27,0xde,
++0x90,0x90,0xa4,0x12,0x2a,0x7f,0x7f,0x8c,0x7e,0x0e,0x12,0x27,0xde,0x90,0x90,0xa8,
++0x12,0x2a,0x7f,0x7f,0xd0,0x7e,0x0e,0x12,0x27,0xde,0x90,0x90,0xac,0x12,0x2a,0x7f,
++0x7f,0xd4,0x7e,0x0e,0x12,0x27,0xde,0x90,0x90,0xb0,0x12,0x2a,0x7f,0x7f,0xd8,0x7e,
++0x0e,0x12,0x27,0xde,0x90,0x90,0xb4,0x12,0x2a,0x7f,0x7f,0xdc,0x7e,0x0e,0x12,0x27,
++0xde,0x90,0x90,0xb8,0x12,0x2a,0x7f,0x7f,0xe0,0x7e,0x0e,0x12,0x27,0xde,0x90,0x90,
++0xbc,0x12,0x2a,0x7f,0x7f,0xec,0x7e,0x0e,0x12,0x27,0xde,0x90,0x90,0xc0,0x12,0x2a,
++0x7f,0x7f,0x04,0x7e,0x0c,0x12,0x27,0xde,0x90,0x90,0xc4,0x12,0x2a,0x7f,0x7f,0x04,
++0x7e,0x0d,0x12,0x27,0xde,0x90,0x90,0xc8,0x12,0x2a,0x7f,0x7f,0x0c,0x7e,0x09,0x12,
++0x27,0xde,0x90,0x90,0xcc,0x12,0x2a,0x7f,0x7f,0x04,0x7e,0x08,0x12,0x27,0xde,0x90,
++0x90,0xd0,0x12,0x2a,0x7f,0x7f,0x8c,0x7e,0x08,0x12,0x27,0xde,0x90,0x91,0x88,0x12,
++0x2a,0x7f,0x90,0x91,0x88,0x12,0x43,0x09,0xed,0x44,0xc0,0xfd,0xec,0x90,0x91,0x88,
++0x12,0x2a,0x7f,0x90,0x91,0x88,0x12,0x43,0x09,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,
++0x8c,0x7e,0x08,0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x00,0x01,0x00,0x00,
++0x7f,0x44,0x7e,0x08,0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x00,0xdb,0x25,
++0xa4,0x7f,0x5c,0x7e,0x08,0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x20,0xdb,
++0x25,0xa4,0x7f,0x6c,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x20,
++0xdb,0x25,0xa4,0x7f,0x70,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,
++0x04,0x1b,0x25,0xa4,0x7f,0x74,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,
++0x8b,0x04,0x1b,0x25,0xa4,0x7f,0x78,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,
++0x2a,0x8b,0x04,0x1b,0x25,0xa4,0x7f,0x7c,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x80,0x85,
++0x12,0x2a,0x8b,0x04,0x1b,0x25,0xa4,0x7f,0x80,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x80,
++0x85,0x12,0x2a,0x8b,0x63,0xdb,0x25,0xa4,0x7f,0x84,0x7e,0x0e,0x12,0x2f,0xd9,0x90,
++0x80,0x85,0x12,0x2a,0x8b,0x04,0x1b,0x25,0xa4,0x7f,0x88,0x7e,0x0e,0x12,0x2f,0xd9,
++0x90,0x80,0x85,0x12,0x2a,0x8b,0x20,0xdb,0x25,0xa4,0x7f,0x8c,0x7e,0x0e,0x12,0x2f,
++0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x20,0xdb,0x25,0xa4,0x7f,0xd0,0x7e,0x0e,0x12,
++0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x20,0xdb,0x25,0xa4,0x7f,0xd4,0x7e,0x0e,
++0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x20,0xdb,0x25,0xa4,0x7f,0xd8,0x7e,
++0x0e,0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x00,0x1b,0x25,0xa4,0x7f,0xdc,
++0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x00,0x1b,0x25,0xa4,0x7f,
++0xe0,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x24,0xdb,0x25,0xa4,
++0x7f,0xec,0x7e,0x0e,0x12,0x2f,0xd9,0x7f,0x04,0x7e,0x0c,0x12,0x27,0xde,0x90,0x91,
++0x88,0x12,0x2a,0x7f,0x90,0x91,0x88,0x12,0x43,0x09,0xe4,0xff,0xec,0x90,0x91,0x88,
++0x12,0x2a,0x7f,0x90,0x91,0x88,0x12,0x43,0x09,0xef,0x44,0x11,0xff,0xec,0x90,0x91,
++0x88,0x12,0x2a,0x7f,0x90,0x91,0x88,0x12,0x43,0x09,0x90,0x80,0x85,0x12,0x2a,0x7f,
++0x7f,0x04,0x7e,0x0c,0x12,0x2f,0xd9,0x7f,0x04,0x7e,0x0d,0x12,0x27,0xde,0x90,0x91,
++0x88,0x12,0x2a,0x7f,0x90,0x91,0x88,0x12,0x43,0x09,0xef,0x54,0xf0,0xff,0xec,0x90,
++0x91,0x88,0x12,0x2a,0x7f,0x90,0x91,0x88,0x12,0x43,0x09,0xef,0x44,0x01,0xff,0xec,
++0x90,0x91,0x88,0x12,0x2a,0x7f,0x90,0x91,0x88,0x12,0x43,0x09,0x90,0x80,0x85,0x12,
++0x2a,0x7f,0x7f,0x04,0x7e,0x0d,0x12,0x2f,0xd9,0x7f,0x0c,0x7e,0x09,0x12,0x27,0xde,
++0x90,0x91,0x88,0x12,0x2a,0x7f,0x90,0x91,0x88,0x12,0x43,0x09,0xe4,0xff,0xec,0x90,
++0x91,0x88,0x12,0x2a,0x7f,0x90,0x91,0x88,0x12,0x43,0x09,0xef,0x44,0x11,0xff,0xec,
++0x90,0x91,0x88,0x12,0x2a,0x7f,0x90,0x91,0x88,0x12,0x43,0x09,0x90,0x80,0x85,0x12,
++0x2a,0x7f,0x7f,0x0c,0x7e,0x09,0x12,0x2f,0xd9,0x7f,0x0c,0x7e,0x09,0x12,0x27,0xde,
++0x90,0x91,0x88,0x12,0x2a,0x7f,0x90,0x91,0x88,0x12,0x43,0x09,0xed,0x54,0x0f,0xfd,
++0xec,0x54,0xf0,0xfc,0x90,0x91,0x88,0x12,0x2a,0x7f,0x90,0x91,0x88,0x12,0x43,0x09,
++0xed,0x44,0x10,0xfd,0xec,0x44,0x01,0xfc,0x90,0x91,0x88,0x12,0x2a,0x7f,0x90,0x91,
++0x88,0x12,0x43,0x09,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x0c,0x7e,0x09,0x12,0x2f,
++0xd9,0x7f,0x04,0x7e,0x08,0x12,0x27,0xde,0x90,0x91,0x88,0x12,0x2a,0x7f,0x90,0x91,
++0x88,0x12,0x43,0x09,0xef,0x54,0xf0,0xff,0xec,0x90,0x91,0x88,0x12,0x2a,0x7f,0x90,
++0x91,0x88,0x12,0x43,0x09,0xef,0x44,0x01,0xff,0xec,0x90,0x91,0x88,0x12,0x2a,0x7f,
++0x90,0x91,0x88,0x12,0x43,0x09,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x04,0x7e,0x08,
++0x12,0x2f,0xd9,0xe4,0x90,0x90,0xe8,0xf0,0x22,0xe4,0xfd,0x7f,0x45,0x12,0x4b,0xee,
++0x90,0x04,0xfd,0xe4,0xf0,0xa3,0xf0,0x90,0x90,0xf7,0xf0,0x90,0x90,0xfd,0xf0,0x90,
++0x91,0x00,0xf0,0x90,0x90,0xfe,0xf0,0x90,0x91,0x01,0xf0,0x90,0x90,0xff,0xf0,0x90,
++0x91,0x02,0xf0,0x90,0x90,0xe9,0x04,0xf0,0xe4,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0x90,
++0x90,0xee,0xf0,0x90,0x90,0xf3,0xf0,0x90,0x90,0xf5,0xf0,0x90,0x91,0x07,0xf0,0x90,
++0x90,0xf8,0xf0,0x90,0x90,0xf4,0xf0,0x90,0x90,0xed,0xf0,0x90,0x00,0x51,0xe0,0x44,
++0xc0,0xfd,0x7f,0x51,0x02,0x4b,0xee,0x90,0x05,0x60,0xe0,0x90,0x91,0x03,0xf0,0x90,
++0x05,0x61,0xe0,0x90,0x91,0x04,0xf0,0x90,0x05,0x62,0xe0,0x90,0x91,0x05,0xf0,0x90,
++0x05,0x63,0xe0,0x90,0x91,0x06,0xf0,0xc3,0x74,0xff,0x9f,0xfe,0x90,0x91,0x04,0xe0,
++0xd3,0x9e,0x40,0x1e,0xe0,0x2f,0xf0,0xa3,0xe0,0xb4,0xff,0x0f,0xe4,0xf0,0xa3,0xe0,
++0xb4,0xff,0x03,0xe4,0xf0,0x22,0x90,0x91,0x06,0x80,0x03,0x90,0x91,0x05,0xe0,0x04,
++0xf0,0x22,0x90,0x91,0x04,0xe0,0x2f,0xf0,0x22,0x90,0x90,0xf5,0xe0,0x64,0x01,0x60,
++0x02,0xe1,0x6e,0x90,0x00,0x46,0xe0,0x44,0x01,0xfd,0x7f,0x46,0x12,0x4b,0xee,0x90,
++0x91,0x07,0xe0,0x70,0x32,0x90,0x90,0xed,0xe0,0x60,0x15,0x90,0x90,0xf9,0x12,0x43,
++0x09,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x80,0x7e,0x08,0x12,0x2f,0xd9,0x80,0x06,
++0x90,0x05,0x22,0x74,0x7f,0xf0,0x90,0x90,0xf4,0xe0,0xff,0xd1,0x67,0x90,0x91,0x07,
++0x74,0x01,0x12,0x4b,0xe4,0x80,0x40,0x90,0x91,0x07,0xe0,0x64,0x01,0x70,0x38,0x90,
++0x90,0xf8,0xe0,0xff,0xd1,0x67,0xe4,0x90,0x91,0x07,0xf0,0x90,0x00,0x45,0xe0,0x44,
++0x01,0xfd,0x7f,0x45,0x12,0x4b,0xee,0x90,0x90,0xed,0xe0,0x60,0x15,0x90,0x90,0xef,
++0x12,0x43,0x09,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x80,0x7e,0x08,0x12,0x2f,0xd9,
++0x80,0x05,0x90,0x05,0x22,0xe4,0xf0,0x90,0x05,0x87,0xe0,0x64,0x80,0xf0,0x90,0x91,
++0x03,0xe0,0x90,0x05,0x84,0xf0,0x90,0x91,0x04,0xe0,0x90,0x05,0x85,0xf0,0x90,0x91,
++0x05,0xe0,0x90,0x05,0x86,0xf0,0x90,0x91,0x06,0xe0,0x90,0x05,0x87,0xf0,0x22,0x90,
++0x90,0xee,0xe0,0xc3,0x94,0x14,0x50,0x06,0xe0,0x04,0xf0,0x02,0x70,0x29,0x90,0x90,
++0xee,0xe0,0x64,0x14,0x60,0x03,0x02,0x70,0x29,0x90,0x90,0xfd,0xe0,0x70,0x25,0x90,
++0x91,0x00,0xe0,0x70,0x1f,0x90,0x90,0xfe,0xe0,0x70,0x19,0x90,0x91,0x01,0xe0,0x70,
++0x13,0x90,0x90,0xff,0xe0,0x70,0x0d,0x90,0x91,0x02,0xe0,0x70,0x07,0x90,0x04,0xfd,
++0xe0,0x54,0xfe,0xf0,0x90,0x90,0xfd,0xe0,0x90,0x04,0x44,0xf0,0x90,0x90,0xfe,0xe0,
++0x90,0x04,0x45,0xf0,0x90,0x90,0xff,0xe0,0x90,0x04,0x46,0xf0,0xa3,0xe4,0xf0,0x90,
++0x91,0x00,0xe0,0x90,0x04,0x48,0xf0,0x90,0x91,0x01,0xe0,0x90,0x04,0x49,0xf0,0x90,
++0x91,0x02,0xe0,0x90,0x04,0x4a,0xf0,0xa3,0xe4,0xf0,0x90,0x90,0xe9,0xe0,0x90,0x04,
++0x4c,0xf0,0x90,0x90,0xea,0xe0,0x90,0x04,0x4d,0xf0,0x90,0x90,0xeb,0xe0,0x90,0x04,
++0x4e,0xf0,0x90,0x90,0xec,0xe0,0x90,0x04,0x4f,0xf0,0xe4,0x90,0x90,0xee,0xf0,0x90,
++0x90,0xe9,0x04,0xf0,0xe4,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0x90,0x90,0xfd,0xf0,0xa3,
++0xf0,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0x90,0x05,0x60,0xe0,0x90,0x91,0x8c,
++0xf0,0x90,0x05,0x61,0xe0,0x90,0x91,0x8d,0xf0,0x90,0x05,0x62,0xe0,0x90,0x91,0x8e,
++0xf0,0x90,0x05,0x63,0xe0,0x90,0x91,0x8f,0xf0,0x90,0x91,0x06,0xe0,0xff,0x90,0x91,
++0x8f,0xe0,0xfe,0xd3,0x9f,0x50,0x0b,0x90,0x91,0x06,0xe0,0xc3,0x9e,0xd3,0x94,0x01,
++0x40,0x11,0x90,0x90,0xf4,0xe0,0xb4,0x01,0x02,0x80,0x03,0x90,0x90,0xf8,0xe0,0xff,
++0x12,0x6e,0x67,0x22,0x90,0x91,0x07,0xe0,0x64,0x01,0x60,0x08,0x90,0x90,0xf5,0xe0,
++0x60,0x02,0x21,0x4b,0x90,0x90,0xe9,0xe0,0xc3,0x94,0xff,0x50,0x05,0xe0,0x04,0xf0,
++0x80,0x3b,0x90,0x90,0xea,0xe0,0xc3,0x94,0xff,0x50,0x06,0xe0,0x04,0xf0,0xe4,0x80,
++0x28,0x90,0x90,0xeb,0xe0,0xc3,0x94,0xff,0x50,0x0a,0xe0,0x04,0xf0,0xe4,0x90,0x90,
++0xea,0xf0,0x80,0x15,0x90,0x90,0xec,0xe0,0xc3,0x94,0xff,0x50,0x10,0xe0,0x04,0xf0,
++0xe4,0x90,0x90,0xeb,0xf0,0x90,0x90,0xea,0xf0,0x90,0x90,0xe9,0xf0,0x90,0x00,0x44,
++0xe0,0x54,0x0c,0x60,0x76,0xe0,0x30,0xe2,0x32,0x90,0x90,0xfd,0xe0,0xc3,0x94,0xff,
++0x50,0x05,0xe0,0x04,0xf0,0x80,0x24,0x90,0x90,0xfe,0xe0,0xc3,0x94,0xff,0x50,0x06,
++0xe0,0x04,0xf0,0xe4,0x80,0x11,0x90,0x90,0xff,0xe0,0xc3,0x94,0xff,0x50,0x0c,0xe0,
++0x04,0xf0,0xe4,0x90,0x90,0xfe,0xf0,0x90,0x90,0xfd,0xf0,0x90,0x00,0x44,0xe0,0x30,
++0xe3,0x32,0x90,0x91,0x00,0xe0,0xc3,0x94,0xff,0x50,0x05,0xe0,0x04,0xf0,0x80,0x24,
++0x90,0x91,0x01,0xe0,0xc3,0x94,0xff,0x50,0x06,0xe0,0x04,0xf0,0xe4,0x80,0x11,0x90,
++0x91,0x02,0xe0,0xc3,0x94,0xff,0x50,0x0c,0xe0,0x04,0xf0,0xe4,0x90,0x91,0x01,0xf0,
++0x90,0x91,0x00,0xf0,0x90,0x04,0xfd,0xe0,0x44,0x01,0xf0,0x22,0x90,0x06,0x90,0xe0,
++0x44,0x01,0xf0,0x90,0x91,0x61,0xe0,0x30,0xe0,0x3c,0x90,0x91,0x5f,0xe0,0xff,0x90,
++0x91,0x5e,0xe0,0xfe,0xc4,0x13,0x54,0x01,0xfd,0x12,0x4a,0xf6,0x90,0x91,0x60,0xe0,
++0x75,0xf0,0x20,0xa4,0xff,0xae,0xf0,0x12,0x37,0x54,0x90,0x91,0x5e,0xe0,0xc4,0x13,
++0x54,0x07,0x30,0xe0,0x07,0xa3,0xe0,0xff,0xe4,0xfd,0x80,0x07,0x90,0x91,0x5f,0xe0,
++0xff,0x7d,0x01,0x12,0x4a,0xf6,0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0xe4,0x90,
++0x91,0x19,0xf0,0xa3,0x74,0x08,0xf0,0xa3,0xf0,0xe4,0xa3,0xf0,0x90,0x01,0x1f,0xe0,
++0xfe,0x90,0x01,0x1e,0xe0,0x7c,0x00,0x24,0x00,0xff,0xec,0x3e,0x90,0x91,0x11,0xf0,
++0xa3,0xef,0xf0,0x90,0x02,0x87,0xe0,0x90,0x91,0x18,0xf0,0x90,0x91,0x56,0xe0,0x20,
++0xe0,0x02,0x61,0xc4,0xe4,0x90,0x91,0x17,0xf0,0x90,0x91,0x18,0xe0,0xff,0x90,0x91,
++0x17,0xe0,0xc3,0x9f,0x40,0x02,0x61,0xc4,0x90,0x91,0x11,0xe0,0xfc,0xa3,0xe0,0xfd,
++0xec,0xff,0x90,0xfd,0x11,0xf0,0x90,0x91,0x1c,0xef,0xf0,0x74,0x02,0x2d,0xf5,0x82,
++0xe4,0x34,0xfb,0xf5,0x83,0xe0,0x54,0x0f,0xfc,0x33,0x33,0x33,0x54,0xf8,0xff,0xed,
++0x24,0x18,0x2f,0x90,0x91,0x15,0xf0,0xe0,0x24,0x00,0xf5,0x82,0xe4,0x34,0xfb,0xf5,
++0x83,0xe0,0x54,0xfc,0x90,0x91,0x16,0xf0,0x74,0x01,0x2d,0xf5,0x82,0xe4,0x34,0xfb,
++0xf5,0x83,0xe0,0xfe,0x74,0x00,0x2d,0xf5,0x82,0xe4,0x34,0xfb,0xf5,0x83,0xe0,0x7a,
++0x00,0x24,0x00,0xff,0xea,0x3e,0x54,0x3f,0xab,0x07,0xfa,0x90,0x91,0x13,0xf0,0xa3,
++0xeb,0xf0,0xaf,0x04,0xef,0x75,0xf0,0x08,0xa4,0x24,0x18,0xff,0xe4,0x35,0xf0,0xfe,
++0xef,0x2b,0xfb,0xee,0x3a,0xfa,0x90,0x91,0x5a,0xe0,0xfe,0xa3,0xe0,0xff,0xad,0x03,
++0xac,0x02,0x12,0x45,0x09,0xaa,0x06,0xab,0x07,0x90,0x91,0x15,0xe0,0x24,0x00,0xf5,
++0x82,0xe4,0x34,0xfb,0xf5,0x83,0xe0,0x30,0xe7,0x08,0x90,0x91,0x19,0x74,0x02,0xf0,
++0x80,0x05,0xe4,0x90,0x91,0x19,0xf0,0xaf,0x03,0x90,0x91,0x11,0xea,0x8f,0xf0,0x12,
++0x42,0x81,0x90,0x91,0x5c,0xe0,0xfe,0xa3,0xe0,0xff,0x90,0x91,0x11,0xe0,0xfc,0xa3,
++0xe0,0xfd,0xd3,0x9f,0xec,0x9e,0x40,0x1b,0x90,0x91,0x5d,0xe0,0x24,0x01,0xff,0x90,
++0x91,0x5c,0xe0,0x34,0x00,0xfe,0xc3,0xed,0x9f,0xff,0xec,0x9e,0x90,0x91,0x11,0xf0,
++0xa3,0xef,0xf0,0x90,0x91,0x16,0xe0,0xff,0x24,0x40,0x60,0x04,0x24,0x20,0x70,0x27,
++0x90,0x91,0x5e,0xe0,0xfe,0xc4,0x13,0x13,0x13,0x54,0x01,0x20,0xe0,0x02,0x61,0x9c,
++0xef,0x90,0x00,0x81,0xb4,0xa0,0x05,0xe0,0x44,0x04,0x80,0x03,0xe0,0x44,0x08,0xfd,
++0x7f,0x81,0x12,0x4b,0xee,0x61,0x95,0x90,0x91,0x5e,0xe0,0xc4,0x13,0x13,0x54,0x03,
++0x20,0xe0,0x02,0x61,0x9c,0x90,0x91,0x15,0xe0,0xff,0x24,0x00,0xf5,0x82,0xe4,0x34,
++0xfb,0xf5,0x83,0xe0,0x54,0x0c,0x64,0x08,0x70,0x72,0x90,0x91,0x19,0xe0,0xfe,0xef,
++0x2e,0xff,0xa3,0xe0,0x2f,0xff,0x24,0x1e,0xf5,0x82,0xe4,0x34,0xfb,0xf5,0x83,0xe0,
++0x64,0x88,0x70,0x58,0x74,0x1f,0x2f,0xf5,0x82,0xe4,0x34,0xfb,0xf5,0x83,0xe0,0x64,
++0x8e,0x70,0x49,0x90,0x91,0x19,0xe0,0xff,0x90,0x91,0x15,0xe0,0x2f,0xff,0x90,0x91,
++0x1a,0xe0,0x2f,0xff,0xa3,0xe0,0x2f,0xff,0x24,0x19,0xf5,0x82,0xe4,0x34,0xfb,0xf5,
++0x83,0xe0,0x64,0x03,0x70,0x26,0x74,0x1e,0x2f,0xf5,0x82,0xe4,0x34,0xfb,0xf5,0x83,
++0xe0,0x90,0x00,0x81,0x30,0xe3,0x05,0xe0,0x44,0x01,0x80,0x03,0xe0,0x44,0x02,0xfd,
++0x7f,0x81,0x12,0x4b,0xee,0x90,0x91,0x56,0xe0,0x44,0x80,0xf0,0x90,0x91,0x56,0xe0,
++0xff,0xc4,0x13,0x13,0x13,0x54,0x01,0x30,0xe0,0x02,0x31,0x4c,0x71,0xc9,0xbf,0x01,
++0x13,0x90,0x91,0x11,0xe0,0xfe,0xa3,0xe0,0xff,0x12,0x44,0xb5,0x90,0x91,0x17,0xe0,
++0x04,0xf0,0x21,0xd9,0xd0,0xd0,0x92,0xaf,0x22,0x90,0x91,0x56,0xe0,0xc4,0x13,0x13,
++0x13,0x54,0x01,0x30,0xe0,0x11,0xe0,0x44,0x80,0xf0,0x90,0x91,0x5e,0xe0,0xc4,0x54,
++0x0f,0x20,0xe0,0x03,0x7f,0x00,0x22,0x7f,0x01,0x22,0x8f,0x1f,0xe4,0x90,0x91,0x22,
++0xf0,0xe5,0x1f,0x14,0xfe,0x90,0x91,0x22,0xe0,0xff,0xc3,0x9e,0x50,0x0e,0xef,0x04,
++0xfd,0x12,0x34,0xb7,0x90,0x91,0x22,0xe0,0x04,0xf0,0x80,0xe5,0xe5,0x1f,0x14,0xff,
++0x7d,0xff,0x12,0x34,0xb7,0x90,0x91,0x22,0xe5,0x1f,0xf0,0x90,0x91,0x22,0xe0,0xc3,
++0x94,0xff,0x50,0x0f,0xe0,0xff,0x04,0xfd,0x12,0x34,0xb7,0x90,0x91,0x22,0xe0,0x04,
++0xf0,0x80,0xe8,0xad,0x1f,0x7f,0xff,0x02,0x34,0xb7,0xc3,0xee,0x94,0x01,0x40,0x0a,
++0x0d,0xed,0x13,0x90,0xfd,0x10,0xf0,0xe4,0x2f,0xff,0x22,0xc3,0xee,0x94,0x01,0x40,
++0x1e,0x90,0xfd,0x11,0xe0,0xb5,0x05,0x14,0x90,0x01,0x17,0xe0,0xb5,0x05,0x07,0x90,
++0xfd,0x11,0xe4,0xf0,0x80,0x06,0xed,0x04,0x90,0xfd,0x11,0xf0,0xe4,0x2f,0xff,0x22,
++0x0f,0x75,};
++
++u8 Rtl8192CUFwUMCACutWWImgArray[UMCACutWWImgArrayLength] = {
++0xc1,0x88,0x02,0x00,0x51,0x00,0x00,0x00,0x03,0x23,0x16,0x44,0x72,0x34,0x01,0x00,
++0x58,0x92,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x02,0x43,0x9d,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x02,0x57,0xcb,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x02,0x5c,0xb6,0x00,0x00,0x00,0x00,0x00,0x02,0x5d,0x99,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0xbb,0x01,0x0c,0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe0,0x22,0x50,
++0x06,0xe9,0x25,0x82,0xf8,0xe6,0x22,0xbb,0xfe,0x06,0xe9,0x25,0x82,0xf8,0xe2,0x22,
++0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe4,0x93,0x22,0xbb,0x01,0x06,
++0x89,0x82,0x8a,0x83,0xf0,0x22,0x50,0x02,0xf7,0x22,0xbb,0xfe,0x01,0xf3,0x22,0xf8,
++0xbb,0x01,0x0d,0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe8,0xf0,0x22,
++0x50,0x06,0xe9,0x25,0x82,0xc8,0xf6,0x22,0xbb,0xfe,0x05,0xe9,0x25,0x82,0xc8,0xf2,
++0x22,0xc5,0xf0,0xf8,0xa3,0xe0,0x28,0xf0,0xc5,0xf0,0xf8,0xe5,0x82,0x15,0x82,0x70,
++0x02,0x15,0x83,0xe0,0x38,0xf0,0x22,0xbb,0x01,0x10,0xe5,0x82,0x29,0xf5,0x82,0xe5,
++0x83,0x3a,0xf5,0x83,0xe0,0xf5,0xf0,0xa3,0xe0,0x22,0x50,0x09,0xe9,0x25,0x82,0xf8,
++0x86,0xf0,0x08,0xe6,0x22,0xbb,0xfe,0x0a,0xe9,0x25,0x82,0xf8,0xe2,0xf5,0xf0,0x08,
++0xe2,0x22,0xe5,0x83,0x2a,0xf5,0x83,0xe9,0x93,0xf5,0xf0,0xa3,0xe9,0x93,0x22,0xf8,
++0xbb,0x01,0x11,0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe8,0xf0,0xe5,
++0xf0,0xa3,0xf0,0x22,0x50,0x09,0xe9,0x25,0x82,0xc8,0xf6,0x08,0xa6,0xf0,0x22,0xbb,
++0xfe,0x09,0xe9,0x25,0x82,0xc8,0xf2,0xe5,0xf0,0x08,0xf2,0x22,0xef,0x4b,0xff,0xee,
++0x4a,0xfe,0xed,0x49,0xfd,0xec,0x48,0xfc,0x22,0xe0,0xfc,0xa3,0xe0,0xfd,0xa3,0xe0,
++0xfe,0xa3,0xe0,0xff,0x22,0xa4,0x25,0x82,0xf5,0x82,0xe5,0xf0,0x35,0x83,0xf5,0x83,
++0x22,0xe0,0xfb,0xa3,0xe0,0xfa,0xa3,0xe0,0xf9,0x22,0xf8,0xe0,0xfb,0xa3,0xa3,0xe0,
++0xf9,0x25,0xf0,0xf0,0xe5,0x82,0x15,0x82,0x70,0x02,0x15,0x83,0xe0,0xfa,0x38,0xf0,
++0x22,0xeb,0xf0,0xa3,0xea,0xf0,0xa3,0xe9,0xf0,0x22,0xd0,0x83,0xd0,0x82,0xf8,0xe4,
++0x93,0x70,0x12,0x74,0x01,0x93,0x70,0x0d,0xa3,0xa3,0x93,0xf8,0x74,0x01,0x93,0xf5,
++0x82,0x88,0x83,0xe4,0x73,0x74,0x02,0x93,0x68,0x60,0xef,0xa3,0xa3,0xa3,0x80,0xdf,
++0xd0,0x83,0xd0,0x82,0xf8,0xe4,0x93,0x70,0x12,0x74,0x01,0x93,0x70,0x0d,0xa3,0xa3,
++0x93,0xf8,0x74,0x01,0x93,0xf5,0x82,0x88,0x83,0xe4,0x73,0x74,0x02,0x93,0xb5,0xf0,
++0x06,0x74,0x03,0x93,0x68,0x60,0xe9,0xa3,0xa3,0xa3,0xa3,0x80,0xd8,0x02,0x43,0xdb,
++0x02,0x50,0x2a,0xe4,0x93,0xa3,0xf8,0xe4,0x93,0xa3,0x40,0x03,0xf6,0x80,0x01,0xf2,
++0x08,0xdf,0xf4,0x80,0x29,0xe4,0x93,0xa3,0xf8,0x54,0x07,0x24,0x0c,0xc8,0xc3,0x33,
++0xc4,0x54,0x0f,0x44,0x20,0xc8,0x83,0x40,0x04,0xf4,0x56,0x80,0x01,0x46,0xf6,0xdf,
++0xe4,0x80,0x0b,0x01,0x02,0x04,0x08,0x10,0x20,0x40,0x80,0x90,0x44,0x20,0xe4,0x7e,
++0x01,0x93,0x60,0xbc,0xa3,0xff,0x54,0x3f,0x30,0xe5,0x09,0x54,0x1f,0xfe,0xe4,0x93,
++0xa3,0x60,0x01,0x0e,0xcf,0x54,0xc0,0x25,0xe0,0x60,0xa8,0x40,0xb8,0xe4,0x93,0xa3,
++0xfa,0xe4,0x93,0xa3,0xf8,0xe4,0x93,0xa3,0xc8,0xc5,0x82,0xc8,0xca,0xc5,0x83,0xca,
++0xf0,0xa3,0xc8,0xc5,0x82,0xc8,0xca,0xc5,0x83,0xca,0xdf,0xe9,0xde,0xe7,0x80,0xbe,
++0x41,0x91,0x40,0x00,0x41,0x91,0x9c,0x00,0x41,0x91,0x23,0x80,0x41,0x91,0x24,0x80,
++0x41,0x91,0x9e,0x00,0x41,0x91,0x52,0x00,0x41,0x91,0x93,0x00,0x41,0x91,0x91,0x00,
++0x41,0x91,0x90,0x00,0x41,0x91,0x92,0x00,0x00,0xf0,0x90,0x91,0x30,0xe0,0x90,0x91,
++0x67,0xf0,0xe4,0xfb,0xfd,0x7f,0x54,0x7e,0x01,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,
++0x90,0x91,0x65,0xeb,0xf0,0xa3,0xe0,0xfb,0xa3,0xe0,0xf5,0x44,0xe4,0xf5,0x45,0x12,
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++0x80,0x1a,0x90,0x91,0x9a,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,
++0xd8,0xfc,0xc4,0x54,0xf0,0xf4,0xff,0x90,0x00,0x42,0xe0,0x5f,0xf0,0x51,0xe6,0xd0,
++0xd0,0x92,0xaf,0x22,0xf0,0x90,0x00,0x45,0xe0,0x54,0xfe,0xfd,0x7f,0x45,0xd3,0x10,
++0xaf,0x01,0xc3,0xc0,0xd0,0x8f,0x82,0x75,0x83,0x00,0xed,0xf0,0x51,0xe6,0xd0,0xd0,
++0x92,0xaf,0x22,0xef,0x14,0x60,0x30,0x14,0x60,0x66,0x24,0x02,0x60,0x02,0x81,0xaa,
++0x90,0x90,0xf3,0x74,0x02,0xf0,0x90,0x00,0x48,0xe0,0x44,0x0c,0xfd,0x7f,0x48,0x71,
++0xee,0x90,0x00,0x47,0xe0,0x44,0x08,0xfd,0x7f,0x47,0x71,0xee,0x90,0x00,0x45,0xe0,
++0x44,0x10,0xfd,0x7f,0x45,0x80,0x71,0xe4,0x90,0x90,0xf3,0xf0,0x90,0x90,0xef,0x12,
++0x43,0x09,0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0x80,0x7e,0x08,0x12,0x2b,0x08,0x90,
++0x00,0x45,0xe0,0x44,0xef,0xfd,0x7f,0x45,0x71,0xee,0x90,0x00,0x45,0xe0,0x54,0xef,
++0xfd,0x7f,0x45,0x71,0xee,0x90,0x00,0x46,0xe0,0x44,0x10,0xfd,0x7f,0x46,0x80,0x38,
++0x90,0x90,0xf3,0x74,0x01,0xf0,0x90,0x90,0xf9,0x12,0x43,0x09,0x90,0x80,0x96,0x12,
++0x25,0x08,0x7f,0x80,0x7e,0x08,0x12,0x2b,0x08,0x90,0x00,0x45,0xe0,0x44,0x20,0xfd,
++0x7f,0x45,0x71,0xee,0x90,0x00,0x45,0xe0,0x44,0x10,0xfd,0x7f,0x45,0x71,0xee,0x90,
++0x00,0x46,0xe0,0x44,0x10,0xfd,0x7f,0x46,0x71,0xee,0x22,0x90,0x00,0x02,0x12,0x42,
++0x20,0x90,0x90,0xf5,0xf0,0x90,0x00,0x01,0x12,0x42,0x20,0x25,0xe0,0x25,0xe0,0x90,
++0x90,0xf4,0xf0,0x12,0x24,0x62,0x25,0xe0,0x25,0xe0,0x90,0x90,0xf8,0xf0,0x90,0x05,
++0x60,0xe0,0x90,0x91,0x03,0xf0,0x90,0x05,0x61,0xe0,0x90,0x91,0x04,0xf0,0x90,0x05,
++0x62,0xe0,0x90,0x91,0x05,0xf0,0x90,0x05,0x63,0xe0,0x90,0x91,0x06,0xf0,0xa2,0xaf,
++0xe4,0x33,0x90,0x91,0x1c,0xf0,0xc2,0xaf,0x90,0x90,0xf4,0xe0,0xff,0x12,0x6e,0x67,
++0x90,0x91,0x1c,0xe0,0x24,0xff,0x92,0xaf,0x90,0x90,0xf5,0xe0,0x70,0x02,0xa1,0xb2,
++0x90,0x90,0xf4,0xe0,0x70,0x02,0xa1,0xb2,0x90,0x90,0xf8,0xe0,0x70,0x02,0xa1,0xb2,
++0xa2,0xaf,0xe4,0x33,0x90,0x91,0x1c,0xf0,0xc2,0xaf,0x90,0x91,0x07,0x74,0x01,0xf0,
++0x90,0x91,0x1c,0xe0,0x24,0xff,0x92,0xaf,0x71,0xe5,0x90,0x00,0x46,0xe0,0x44,0x01,
++0xfd,0x7f,0x46,0x71,0xee,0x90,0x90,0xed,0xe0,0x60,0x15,0x90,0x90,0xf9,0x12,0x43,
++0x09,0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0x80,0x7e,0x08,0x12,0x2b,0x08,0x80,0x06,
++0x90,0x05,0x22,0x74,0x7f,0xf0,0x90,0x00,0x45,0xe0,0x54,0xef,0xfd,0x7f,0x45,0x71,
++0xee,0x90,0x05,0x87,0xe0,0x64,0x80,0xf0,0x90,0x91,0x03,0xe0,0x90,0x05,0x84,0xf0,
++0x90,0x91,0x04,0xe0,0x90,0x05,0x85,0xf0,0x90,0x91,0x05,0xe0,0x90,0x05,0x86,0xf0,
++0x90,0x91,0x06,0xe0,0x90,0x05,0x87,0xf0,0xa2,0xaf,0xe4,0x33,0x90,0x91,0x1c,0xf0,
++0xc2,0xaf,0x90,0x01,0x3c,0xe0,0x44,0x20,0xf0,0x7d,0x20,0xe4,0xff,0x12,0x31,0xb7,
++0x80,0x2b,0x90,0x90,0xf5,0xe0,0x70,0x2d,0x90,0x91,0x07,0x71,0xe4,0x90,0x00,0x46,
++0xe0,0x54,0xfe,0xfd,0x7f,0x46,0x71,0xee,0x90,0x05,0x22,0xe4,0xf0,0xa2,0xaf,0x33,
++0x90,0x91,0x1c,0xf0,0xc2,0xaf,0x7d,0x20,0xe4,0xff,0x12,0x31,0x49,0x90,0x91,0x1c,
++0xe0,0x24,0xff,0x92,0xaf,0x22,0x8b,0x0e,0x8a,0x0f,0x89,0x10,0x90,0x00,0x02,0x12,
++0x42,0x20,0x90,0x90,0xf6,0xf0,0xe0,0x30,0xe0,0x4b,0x90,0x90,0xed,0x74,0x01,0xf0,
++0x7f,0x80,0x7e,0x08,0x12,0x22,0x65,0x90,0x90,0xef,0x12,0x25,0x08,0xab,0x0e,0xaa,
++0x0f,0xa9,0x10,0x90,0x00,0x01,0x12,0x42,0x20,0xff,0xe4,0xfc,0xfd,0xfe,0x78,0x1a,
++0x12,0x24,0xf5,0xa8,0x04,0xa9,0x05,0xaa,0x06,0xab,0x07,0x90,0x90,0xef,0x12,0x43,
++0x09,0xec,0x54,0x03,0xfc,0x12,0x42,0xfc,0x90,0x90,0xf9,0x12,0x25,0x08,0x90,0x05,
++0x22,0xe4,0xf0,0x80,0x2d,0xe4,0x90,0x90,0xed,0xf0,0x7f,0x80,0x7e,0x08,0x12,0x22,
++0x65,0xec,0x54,0x03,0xfc,0xec,0x44,0xc0,0xfc,0x90,0x90,0xef,0x12,0x25,0x08,0x90,
++0x90,0xef,0x12,0x43,0x09,0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0x80,0x7e,0x08,0x12,
++0x2b,0x08,0x90,0x90,0xf6,0xe0,0x30,0xe1,0x19,0x7d,0x0c,0x7f,0x47,0x71,0xee,0x90,
++0x00,0x48,0xe0,0x44,0x0c,0xfd,0x7f,0x48,0x71,0xee,0x90,0x00,0x46,0xe0,0x44,0x10,
++0x80,0x1c,0x90,0x00,0x47,0xe0,0x54,0xf3,0xfd,0x7f,0x47,0x71,0xee,0x90,0x00,0x48,
++0xe0,0x54,0xf3,0xfd,0x7f,0x48,0x71,0xee,0x90,0x00,0x46,0xe0,0x54,0xef,0xfd,0x7f,
++0x46,0x71,0xee,0xe4,0x90,0x90,0xf3,0xf0,0x22,0x90,0x01,0x3c,0x74,0xff,0xf0,0xa3,
++0xf0,0xa3,0xf0,0x90,0x01,0x34,0xf0,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0xfd,0x7f,0x54,
++0x71,0xee,0x7d,0xff,0x7f,0x55,0x71,0xee,0x7d,0xff,0x7f,0x56,0x71,0xee,0x7d,0xff,
++0x7f,0x57,0x61,0xee,0x90,0x01,0x30,0xe4,0xf0,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0x90,
++0x01,0x38,0xf0,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0xfd,0x7f,0x50,0x71,0xee,0xe4,0xfd,
++0x7f,0x51,0x71,0xee,0xe4,0xfd,0x7f,0x52,0x71,0xee,0xe4,0xfd,0x7f,0x53,0x61,0xee,
++0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x90,0x91,0x22,0xed,0xf0,0x90,0x91,0x21,0xef,
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++0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xf4,0xff,0x90,0x00,0x47,0xe0,
++0x5f,0xf0,0x80,0x17,0x90,0x91,0x21,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,
++0xc3,0x33,0xd8,0xfc,0xff,0x90,0x00,0x47,0xe0,0x4f,0xf0,0x51,0xe6,0x90,0x91,0x21,
++0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xf4,0xff,0x90,
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++0x91,0x21,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xc4,
++0x54,0xf0,0xf4,0xff,0x90,0x00,0x43,0xe0,0x5f,0xf0,0x80,0x1a,0x90,0x91,0x21,0xe0,
++0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xc4,0x54,0xf0,0xff,
++0x90,0x00,0x43,0xe0,0x4f,0xf0,0x51,0xe6,0x90,0x91,0x21,0xe0,0xff,0x74,0x01,0xa8,
++0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xf4,0xff,0x90,0x00,0x43,0xe0,0x5f,0xf0,
++0x51,0xe6,0xd0,0xd0,0x92,0xaf,0x22,0x90,0x00,0x49,0xe0,0x90,0x91,0x9f,0xf0,0xe0,
++0x54,0x0f,0xf0,0x44,0xf0,0xfd,0x7f,0x49,0x71,0xee,0x90,0x91,0x9f,0xe0,0x44,0xb0,
++0xfd,0x7f,0x49,0x61,0xee,0x12,0x47,0xe6,0xbf,0x01,0x10,0x90,0x02,0x09,0xe0,0xff,
++0x7d,0x01,0x12,0x48,0x22,0x90,0x04,0x1f,0x74,0x20,0xf0,0x22,0x75,0x28,0x33,0xe4,
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++0xf0,0x75,0x8e,0x02,0xf1,0x25,0xd1,0xe8,0x90,0x91,0x4f,0xef,0xf0,0xf1,0x0b,0x90,
++0x91,0x51,0xef,0xf0,0xf1,0x60,0x90,0x91,0x3d,0xee,0xf0,0xa3,0xef,0xf0,0xe4,0xf5,
++0x57,0xf1,0x02,0x12,0x61,0xc4,0x12,0x2e,0x01,0x12,0x44,0xff,0x11,0x0c,0xf1,0x36,
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++0x91,0x10,0xe5,0xd9,0xf0,0x12,0x4e,0xb9,0xc2,0xaf,0x90,0x00,0x80,0xe0,0x44,0x40,
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++0x64,0x01,0xf0,0x24,0x2a,0x90,0x01,0xc4,0xf0,0x74,0x50,0xa3,0xf0,0xe5,0x57,0x30,
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++0x71,0x97,0xe5,0x57,0x30,0xe4,0x0a,0xc2,0xaf,0x53,0x57,0xef,0xd2,0xaf,0x12,0x60,
++0x2d,0x90,0x90,0xf7,0xe0,0x70,0x03,0x12,0x70,0x74,0x11,0xe7,0x90,0x91,0x3f,0xe0,
++0x90,0x01,0xba,0xf0,0x80,0xb6,0xe4,0x90,0x91,0x55,0xf0,0x90,0x91,0x53,0xe0,0x54,
++0x7f,0xf0,0xa3,0x74,0x0a,0xf0,0x22,0x90,0x06,0x34,0xe0,0x60,0x25,0x14,0x70,0x1b,
++0x7b,0x01,0x7a,0x06,0x79,0x35,0x7f,0xf9,0x7e,0x01,0x12,0x67,0xe4,0xbf,0x01,0x09,
++0x90,0x06,0x35,0xe0,0x54,0x0f,0xf0,0x80,0x04,0x80,0x00,0xe1,0x17,0xe4,0x90,0x06,
++0x34,0xf0,0x22,0x90,0x91,0x56,0xe0,0x54,0xfe,0xf0,0xe0,0x54,0x7f,0xf0,0x90,0x01,
++0x17,0xe0,0xfe,0x90,0x01,0x16,0xe0,0x7c,0x00,0x24,0x00,0xff,0xec,0x3e,0x90,0x91,
++0x5c,0xf0,0xa3,0xef,0xf0,0x90,0x01,0x04,0xe0,0x54,0x0f,0x90,0x91,0x1c,0xf0,0xe0,
++0xff,0x74,0x40,0x7e,0x00,0xa8,0x07,0x08,0x80,0x05,0xc3,0x33,0xce,0x33,0xce,0xd8,
++0xf9,0x90,0x91,0x5b,0xf0,0xee,0x90,0x91,0x5a,0xf0,0x90,0x91,0x5e,0xe0,0x54,0xfe,
++0xf0,0xe0,0x54,0xfd,0xf0,0xe0,0x54,0xfb,0xf0,0xe0,0x54,0xf7,0xf0,0xe0,0x54,0xef,
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++0xa3,0xf0,0xa3,0xe0,0x54,0xfe,0xf0,0xe0,0x54,0xfd,0xf0,0xe0,0x54,0xf7,0xf0,0x22,
++0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x12,0x24,0x62,0x54,0x01,0xff,0x90,0x91,0x56,
++0xe0,0x54,0xfe,0x4f,0xf0,0x90,0x00,0x01,0x12,0x42,0x20,0x90,0x91,0x57,0xf0,0x90,
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++0x90,0x06,0x09,0xe0,0x54,0xfe,0xf0,0x90,0x02,0x86,0xe0,0x44,0x04,0xf0,0x43,0x57,
++0x04,0x7d,0x08,0xe4,0xff,0x12,0x31,0x9d,0x80,0x12,0x7d,0x08,0xe4,0xff,0x12,0x31,
++0x2c,0x90,0x02,0x86,0xe0,0x54,0xfb,0xf0,0x31,0xf1,0x31,0x13,0xd0,0xd0,0x92,0xaf,
++0x22,0x90,0x06,0x90,0xe4,0xf0,0x21,0x5a,0x90,0x91,0x19,0x12,0x43,0x41,0xef,0x12,
++0x43,0x4a,0x52,0x30,0x01,0x52,0x39,0x02,0x52,0x5b,0x03,0x52,0x64,0x09,0x52,0x6c,
++0x0c,0x52,0x75,0x0d,0x52,0x7d,0x0e,0x52,0x8e,0x1a,0x52,0x96,0x2c,0x52,0x41,0x2d,
++0x52,0x4a,0x2e,0x52,0x9e,0x30,0x52,0x53,0x3b,0x52,0x86,0x3c,0x00,0x00,0x52,0xa6,
++0x90,0x91,0x19,0x12,0x43,0x21,0x02,0x64,0x72,0x90,0x91,0x19,0x12,0x43,0x21,0xc1,
++0xf5,0x90,0x91,0x19,0x12,0x43,0x21,0x02,0x65,0x8d,0x90,0x91,0x19,0x12,0x43,0x21,
++0x02,0x65,0xd5,0x90,0x91,0x19,0x12,0x43,0x21,0xe1,0x4b,0x90,0x91,0x19,0x12,0x43,
++0x21,0x02,0x66,0x0e,0x90,0x91,0x19,0x12,0x43,0x21,0x80,0x42,0x90,0x91,0x19,0x12,
++0x43,0x21,0x02,0x4c,0xab,0x90,0x91,0x19,0x12,0x43,0x21,0xe1,0x98,0x90,0x91,0x19,
++0x12,0x43,0x21,0x02,0x4d,0xe6,0x90,0x91,0x19,0x12,0x43,0x21,0x21,0x90,0x90,0x91,
++0x19,0x12,0x43,0x21,0xa1,0x9b,0x90,0x91,0x19,0x12,0x43,0x21,0x81,0x7a,0x90,0x91,
++0x19,0x12,0x43,0x21,0xe1,0x78,0x90,0x01,0xc6,0xe0,0x44,0x01,0xf0,0x22,0xd3,0x10,
++0xaf,0x01,0xc3,0xc0,0xd0,0x90,0x91,0x1c,0x12,0x43,0x41,0x90,0x91,0x1c,0x12,0x43,
++0x21,0x90,0x00,0x01,0x12,0x42,0x97,0xfa,0xe5,0xf0,0x24,0x00,0xff,0xe4,0x3a,0xfe,
++0x90,0x91,0x1c,0x12,0x43,0x21,0x90,0x00,0x01,0xee,0x8f,0xf0,0x12,0x42,0xcf,0x12,
++0x24,0x62,0xff,0x60,0x2c,0xb5,0x72,0x16,0x90,0x91,0x1c,0x12,0x43,0x21,0x90,0x00,
++0x01,0x12,0x42,0x97,0x65,0x74,0x70,0x04,0xe5,0x73,0x65,0xf0,0x60,0x23,0x90,0x91,
++0x1c,0x12,0x43,0x21,0x90,0x00,0x01,0x12,0x42,0x97,0xff,0xae,0xf0,0x71,0x26,0x80,
++0x10,0x90,0x91,0x1c,0x12,0x43,0x21,0x12,0x24,0x62,0x65,0x72,0x60,0x03,0x12,0x44,
++0xe8,0xd0,0xd0,0x92,0xaf,0x22,0x90,0x91,0x1f,0xee,0xf0,0xa3,0xef,0xf0,0x75,0x72,
++0x01,0x8e,0x73,0xf5,0x74,0xe4,0xfd,0x7f,0x0b,0x12,0x4f,0x10,0xe4,0xfd,0x7f,0x02,
++0x12,0x4f,0x10,0x71,0x6a,0xe4,0xff,0x71,0xcc,0xe4,0xf5,0x76,0x90,0x01,0xc9,0xe5,
++0x76,0xf0,0x90,0x91,0x1f,0xe0,0xfc,0xa3,0xe0,0xfd,0xec,0xfb,0x8d,0x44,0xe4,0xf5,
++0x45,0x7d,0x01,0x7f,0x60,0x7e,0x01,0x02,0x30,0x62,0x7f,0x0b,0x71,0xd9,0xef,0x65,
++0x75,0x60,0x10,0xe5,0x75,0xb4,0x01,0x05,0xe4,0xf5,0x75,0x80,0x03,0x75,0x75,0x01,
++0x7f,0x01,0x22,0x7f,0x00,0x22,0xe5,0x72,0x64,0x01,0x70,0x3f,0x71,0x6a,0xbf,0x01,
++0x04,0x7f,0x01,0x71,0xcc,0x90,0x00,0x46,0xe0,0x44,0x04,0xfd,0x7f,0x46,0x12,0x4b,
++0xee,0x90,0x00,0x44,0xe0,0x54,0xfb,0xfd,0x7f,0x44,0x12,0x4b,0xee,0x90,0x00,0x46,
++0xe0,0x54,0xfb,0xfd,0x7f,0x46,0x12,0x4b,0xee,0x7f,0x02,0x71,0xd9,0x8f,0x76,0x90,
++0x01,0xc9,0xe5,0x76,0xf0,0xb4,0x01,0x03,0x12,0x4f,0xd7,0x22,0x90,0x01,0xca,0xe5,
++0x75,0xf0,0xef,0x60,0x03,0x12,0x4f,0xd7,0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,
++0x90,0x91,0xa0,0xef,0xf0,0xd3,0x94,0x07,0x50,0x47,0xe0,0xff,0x74,0x01,0xa8,0x07,
++0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xf4,0xff,0x90,0x00,0x46,0xe0,0x5f,0xf0,0x12,
++0x4a,0xe6,0x90,0x91,0xa0,0xe0,0xfd,0x74,0x01,0x7e,0x00,0xa8,0x05,0x08,0x80,0x05,
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++0x5b,0xa8,0x05,0x08,0x80,0x06,0xce,0xa2,0xe7,0x13,0xce,0x13,0xd8,0xf8,0xff,0x80,
++0x44,0x90,0x91,0xa0,0xe0,0x24,0xf8,0xf0,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,
++0x02,0xc3,0x33,0xd8,0xfc,0x12,0x4a,0xde,0x90,0x91,0xa0,0xe0,0xfd,0x74,0x01,0x7e,
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++0x42,0xe0,0xfb,0xe4,0xfe,0xef,0x5b,0xa8,0x05,0x08,0x80,0x06,0xce,0xa2,0xe7,0x13,
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++0x75,0x0f,0x80,0x80,0x05,0xe4,0xf5,0x0e,0xf5,0x0f,0xe5,0x13,0xc3,0x13,0x90,0xfd,
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++0x83,0xe0,0xfe,0x74,0x46,0x2f,0xf5,0x82,0xe4,0x34,0x91,0xf5,0x83,0xee,0xf0,0x0f,
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++0x74,0x08,0x25,0x10,0xf5,0x10,0xe5,0x12,0x15,0x12,0x70,0x02,0x15,0x11,0xe5,0x12,
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++0x90,0x91,0x5e,0xe0,0x54,0xfd,0x4e,0xf0,0xef,0x54,0x08,0xff,0xe0,0x54,0xf7,0x4f,
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++0x90,0x91,0x5e,0xe0,0x54,0xbf,0x4e,0xf0,0xef,0x54,0x80,0xff,0xe0,0x54,0x7f,0x4f,
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++0x91,0x53,0xe0,0x54,0xfe,0x4e,0xf0,0xef,0xc3,0x13,0x30,0xe0,0x0a,0x90,0x00,0x01,
++0x12,0x42,0x20,0x90,0x91,0x54,0xf0,0x22,0x90,0x00,0x02,0x12,0x42,0x20,0x90,0x90,
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++0x74,0x01,0xf0,0x85,0xd9,0x54,0xe5,0x70,0x14,0x24,0xfd,0x50,0x02,0x80,0x48,0x90,
++0x91,0x3b,0xe0,0x60,0x3a,0x90,0x01,0x5b,0xe4,0xf0,0x90,0x01,0x3c,0x74,0x04,0xf0,
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++0x30,0xbf,0x01,0x03,0x12,0x44,0xc2,0xe5,0x2c,0x30,0xe1,0x20,0x90,0x01,0x34,0x74,
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++0x5c,0x85,0xd6,0x5d,0x85,0xd7,0x5e,0x85,0xd9,0x5f,0x71,0x5c,0xe5,0x2c,0x30,0xe3,
++0x10,0x90,0x01,0x34,0x74,0x08,0xf0,0x90,0x91,0x56,0xe0,0x30,0xe0,0x03,0x43,0x57,
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++0x90,0x01,0x36,0xf0,0x91,0x23,0x51,0x87,0x90,0x91,0x50,0xe4,0xf0,0xe5,0x2e,0x30,
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++0x30,0xe2,0x19,0x90,0x01,0x36,0x74,0x04,0xf0,0x90,0x91,0x3a,0xe4,0xf0,0x90,0x05,
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++0x36,0x74,0x10,0xf0,0xe5,0x6d,0xb4,0x01,0x20,0xe5,0x70,0x60,0x1c,0x90,0x01,0x57,
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++0xe6,0x1b,0x90,0x01,0x36,0x74,0x40,0xf0,0xe5,0x6d,0xb4,0x01,0x10,0xe5,0x70,0x60,
++0x0c,0x53,0x71,0xfe,0xe5,0x71,0x54,0x07,0x70,0x03,0x12,0x44,0xc2,0xe5,0x2f,0x30,
++0xe1,0x08,0x90,0x01,0x37,0x74,0x02,0xf0,0x71,0x7e,0x74,0xcb,0x04,0x90,0x01,0xc4,
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++0x02,0xd0,0x01,0xd0,0x00,0xd0,0xd0,0xd0,0x82,0xd0,0x83,0xd0,0xf0,0xd0,0xe0,0x32,
++0x90,0x04,0x1b,0xe0,0x54,0x7f,0x64,0x7f,0x7f,0x01,0x60,0x02,0x7f,0x00,0x22,0x51,
++0x30,0xef,0x64,0x01,0x60,0x08,0x90,0x01,0xb9,0x74,0x01,0xf0,0x80,0x30,0x90,0x91,
++0x37,0xe0,0x60,0x08,0x90,0x01,0xb9,0x74,0x02,0xf0,0x80,0x22,0x90,0x91,0x36,0xe0,
++0x60,0x08,0x90,0x01,0xb9,0x74,0x04,0xf0,0x80,0x14,0xe5,0x6f,0x54,0x0f,0xd3,0x94,
++0x04,0x40,0x08,0x90,0x01,0xb9,0x74,0x08,0xf0,0x80,0x03,0x7f,0x01,0x22,0x90,0x01,
++0xb8,0x74,0x08,0xf0,0x7f,0x00,0x22,0x90,0x91,0x53,0xe0,0x30,0xe0,0x49,0xe5,0x6d,
++0x64,0x01,0x70,0x43,0x90,0x91,0x52,0xe0,0x04,0xf0,0xe5,0x70,0x64,0x03,0x60,0x05,
++0xe5,0x70,0xb4,0x06,0x0d,0x90,0x91,0x52,0xe0,0xff,0x74,0x01,0xd3,0x9f,0x50,0x14,
++0x80,0x07,0x90,0x91,0x52,0xe0,0xb4,0x0a,0x0b,0x90,0x91,0x55,0xe0,0x04,0xf0,0xe4,
++0x90,0x91,0x52,0xf0,0x90,0x91,0x55,0xe0,0xff,0x90,0x91,0x54,0xe0,0xb5,0x07,0x07,
++0x71,0x4e,0xe4,0x90,0x91,0x55,0xf0,0x22,0xe5,0x6d,0x64,0x01,0x70,0x63,0xe5,0x70,
++0x60,0x5f,0xe5,0x70,0x64,0x02,0x60,0x06,0xe5,0x70,0x64,0x05,0x70,0x27,0x90,0x06,
++0xab,0xe0,0x90,0x91,0x27,0xf0,0x90,0x06,0xaa,0xe0,0x90,0x91,0x39,0xf0,0x90,0x91,
++0x27,0xe0,0x70,0x07,0x90,0x91,0x39,0xe0,0xff,0x80,0x05,0x90,0x91,0x27,0xe0,0xff,
++0x90,0x91,0x27,0xef,0xf0,0x90,0x91,0x29,0xe0,0x60,0x03,0xe0,0x14,0xf0,0xe4,0x90,
++0x91,0x28,0xf0,0x90,0x01,0x57,0xf0,0x90,0x01,0x3c,0x74,0x02,0xf0,0x53,0x71,0xfd,
++0x53,0x71,0xef,0xe5,0x70,0x14,0x24,0xfd,0x50,0x02,0x80,0x03,0x12,0x45,0xc7,0x71,
++0x42,0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0xd0,0xd0,0x92,0xaf,0x22,0xe5,0x6e,
++0x30,0xe3,0x04,0xe4,0xff,0x80,0x02,0x7f,0x01,0x02,0x47,0xc9,0x90,0x91,0x08,0xe0,
++0x54,0xf0,0x44,0x03,0xf0,0x54,0x0f,0x44,0x80,0xf0,0x7b,0x00,0x7a,0x00,0x79,0x58,
++0x90,0x91,0x71,0x12,0x43,0x41,0x0b,0x7a,0x91,0x79,0x08,0x02,0x46,0xb7,0x90,0x91,
++0x80,0x12,0x25,0x14,0x00,0x00,0x00,0x00,0xe5,0x70,0x14,0x24,0xfd,0x50,0x02,0x80,
++0x21,0x90,0x91,0x3b,0xe0,0x60,0x06,0x7d,0x01,0x7f,0x0c,0x80,0x0d,0xe5,0x6e,0x54,
++0x0f,0xc3,0x94,0x04,0x50,0x07,0x7d,0x01,0x7f,0x04,0x12,0x47,0x27,0xe4,0xff,0x12,
++0x48,0xb3,0x22,0x51,0x30,0xef,0x64,0x01,0x60,0x08,0x90,0x01,0xb9,0x74,0x01,0xf0,
++0x80,0x58,0xe5,0x71,0x54,0x03,0x60,0x08,0x90,0x01,0xb9,0x74,0x02,0xf0,0x80,0x4a,
++0xe5,0x6f,0x54,0x0f,0xd3,0x94,0x02,0x40,0x08,0x90,0x01,0xb9,0x74,0x04,0xf0,0x80,
++0x39,0xe5,0x71,0x30,0xe2,0x08,0x90,0x01,0xb9,0x74,0x08,0xf0,0x80,0x2c,0xe5,0x71,
++0x30,0xe4,0x08,0x90,0x01,0xb9,0x74,0x10,0xf0,0x80,0x1f,0x90,0x91,0x29,0xe0,0x60,
++0x08,0x90,0x01,0xb9,0x74,0x20,0xf0,0x80,0x11,0x90,0x91,0x31,0xe0,0x60,0x08,0x90,
++0x01,0xb9,0x74,0x80,0xf0,0x80,0x03,0x7f,0x01,0x22,0x90,0x01,0xb8,0x74,0x04,0xf0,
++0x7f,0x00,0x22,0xe4,0xfb,0x90,0x91,0x78,0x12,0x25,0x14,0x00,0x00,0x00,0x00,0xe5,
++0x70,0x70,0x02,0x81,0xb5,0xe5,0x6d,0x64,0x01,0x70,0x7a,0xe5,0x70,0x14,0x60,0x2b,
++0x24,0xfd,0x60,0x27,0x24,0x02,0x24,0xfb,0x50,0x02,0x80,0x21,0x90,0x91,0x27,0xe0,
++0x14,0xf0,0xe0,0x60,0x04,0xa3,0xe0,0x60,0x14,0x90,0x91,0x27,0xe0,0x70,0x08,0x90,
++0x91,0x39,0xe0,0x90,0x91,0x27,0xf0,0x7b,0x01,0x80,0x02,0x7b,0x01,0xeb,0x60,0x45,
++0x43,0x71,0x10,0xe4,0x90,0x91,0x66,0xf0,0x90,0x91,0x3a,0xe0,0x75,0xf0,0x05,0xa4,
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++0x6e,0x54,0x0f,0xc3,0x94,0x04,0x50,0x07,0x7d,0x01,0x7f,0x04,0x12,0x47,0x27,0x90,
++0x91,0x2e,0xe0,0x60,0x10,0x90,0x91,0x2c,0xe0,0x90,0x07,0x78,0x60,0x04,0x74,0x0d,
++0xf0,0x22,0x74,0x09,0xf0,0x22,0xc0,0xe0,0xc0,0xf0,0xc0,0x83,0xc0,0x82,0xc0,0xd0,
++0x75,0xd0,0x00,0xc0,0x00,0xc0,0x01,0xc0,0x02,0xc0,0x03,0xc0,0x04,0xc0,0x05,0xc0,
++0x06,0xc0,0x07,0x90,0x01,0xc4,0x74,0xb6,0xf0,0x74,0x5c,0xa3,0xf0,0x53,0x91,0xef,
++0x90,0x00,0x51,0xe0,0xff,0x90,0x00,0x55,0xe0,0x5f,0xf5,0x3d,0x90,0x00,0x52,0xe0,
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++0x74,0x10,0xf0,0xe5,0x3d,0x30,0xe5,0x06,0x90,0x00,0x55,0x74,0x20,0xf0,0xe5,0x3d,
++0x30,0xe6,0x1b,0x90,0x00,0x55,0x74,0x40,0xf0,0x90,0x90,0xf6,0xe0,0x54,0x03,0xff,
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++0x30,0xe7,0x15,0x90,0x00,0x55,0x74,0x80,0xf0,0x90,0x90,0xf6,0xe0,0x54,0x03,0xff,
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++0x74,0x01,0xf0,0xe5,0x3e,0x30,0xe1,0x06,0x90,0x00,0x56,0x74,0x02,0xf0,0xe5,0x3e,
++0x30,0xe2,0x06,0x90,0x00,0x56,0x74,0x04,0xf0,0xe5,0x3e,0x30,0xe3,0x06,0x90,0x00,
++0x56,0x74,0x08,0xf0,0x90,0x01,0xc4,0x74,0xb6,0xf0,0x74,0x5c,0xa3,0xf0,0xd0,0x07,
++0xd0,0x06,0xd0,0x05,0xd0,0x04,0xd0,0x03,0xd0,0x02,0xd0,0x01,0xd0,0x00,0xd0,0xd0,
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++0x5d,0xa3,0xf0,0x53,0x91,0xdf,0x90,0x01,0x3c,0xe0,0x55,0x30,0xf5,0x34,0xa3,0xe0,
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++0x74,0x04,0xf0,0x90,0x06,0x92,0xe0,0x30,0xe0,0x25,0x90,0x91,0x66,0xe4,0xf0,0x90,
++0x91,0x2d,0xe0,0x90,0x91,0x67,0xf0,0xe4,0xfb,0xfd,0x7f,0x58,0x7e,0x01,0x12,0x44,
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++0x91,0x37,0xe4,0xf0,0x12,0x44,0xc2,0xe5,0x34,0x30,0xe3,0x3a,0x90,0x01,0x3c,0x74,
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++0x90,0x01,0x5f,0x74,0x05,0xf0,0x90,0x06,0x92,0x74,0x02,0xf0,0x80,0x08,0x90,0x91,
++0x36,0xe4,0xf0,0x12,0x44,0xc2,0xe5,0x34,0x30,0xe4,0x09,0x90,0x01,0x3c,0x74,0x10,
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++0x6e,0xb9,0xe5,0x35,0x30,0xe0,0x5a,0x90,0x01,0x3d,0x74,0x01,0xf0,0x90,0x01,0x2f,
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++0x30,0xe0,0x03,0xa3,0x80,0x03,0x90,0x01,0xbd,0xe0,0x04,0xf0,0xf1,0x38,0x12,0x44,
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++0x06,0xd0,0x05,0xd0,0x04,0xd0,0x03,0xd0,0x02,0xd0,0x01,0xd0,0x00,0xd0,0xd0,0xd0,
++0x82,0xd0,0x83,0xd0,0xf0,0xd0,0xe0,0x32,0xe5,0x6f,0x30,0xe6,0x19,0xe5,0x6f,0x54,
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++0x91,0x24,0xf0,0x53,0x6f,0xbf,0x22,0xe4,0x90,0x91,0x0d,0xf0,0xe5,0x70,0x70,0x02,
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++0x33,0xfc,0x90,0x91,0x3a,0xe0,0xb5,0x05,0x06,0xe4,0xb5,0x04,0x02,0x80,0x12,0xef,
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++0x0d,0xe5,0x6d,0xb4,0x01,0x0b,0xa3,0xe0,0x70,0x07,0xe0,0x04,0xf0,0x22,0x12,0x44,
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++0x91,0x12,0xe0,0x94,0x20,0x90,0x91,0x11,0xe0,0x94,0x03,0x40,0x0a,0x90,0x01,0xc6,
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++0x90,0x91,0x9c,0xe0,0xff,0x74,0x01,0x7e,0x00,0xa8,0x07,0x08,0x80,0x05,0xc3,0x33,
++0xce,0x33,0xce,0xd8,0xf9,0xff,0xef,0x5d,0x70,0x02,0x21,0x68,0x90,0x91,0x9c,0xe0,
++0x75,0xf0,0x04,0x90,0x01,0xd0,0x12,0x43,0x15,0xe0,0x90,0x91,0x12,0xf0,0x75,0x63,
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++0x12,0x46,0x6d,0x90,0x91,0x13,0xe0,0xff,0xc4,0x13,0x13,0x13,0x54,0x01,0x90,0x91,
++0x9c,0x30,0xe0,0x59,0xe0,0x75,0xf0,0x02,0x90,0x00,0x88,0x12,0x43,0x15,0xe0,0x90,
++0x91,0x14,0xf0,0x90,0x91,0x9c,0xe0,0x75,0xf0,0x02,0x90,0x00,0x89,0x12,0x43,0x15,
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++0x43,0x15,0xe0,0x90,0x91,0x16,0xf0,0x90,0x91,0x9c,0xe0,0x75,0xf0,0x04,0x90,0x01,
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++0x90,0x01,0xd3,0x12,0x43,0x15,0xe0,0x90,0x91,0x18,0xf0,0x80,0x33,0xe0,0x75,0xf0,
++0x04,0x90,0x01,0xd1,0x12,0x43,0x15,0xe0,0x90,0x91,0x14,0xf0,0x90,0x91,0x9c,0xe0,
++0x75,0xf0,0x04,0x90,0x01,0xd2,0x12,0x43,0x15,0xe0,0x90,0x91,0x15,0xf0,0x90,0x91,
++0x9c,0xe0,0x75,0xf0,0x04,0x90,0x01,0xd3,0x12,0x43,0x15,0xe0,0x90,0x91,0x16,0xf0,
++0xef,0x54,0x7f,0xff,0x7b,0x01,0x7a,0x91,0x79,0x14,0x12,0x51,0xf8,0x90,0x91,0x11,
++0xe0,0xff,0x90,0x91,0x9c,0xe0,0xfe,0x74,0x01,0xa8,0x06,0x08,0x80,0x02,0xc3,0x33,
++0xd8,0xfc,0xf4,0x5f,0x90,0x91,0x11,0xf0,0x90,0x91,0x9c,0xe0,0xff,0x74,0x01,0xa8,
++0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0x90,0x01,0xcc,0xf0,0x90,0x91,0x9c,0xe0,
++0x04,0xf0,0xe0,0x54,0x03,0xf0,0x01,0x37,0x90,0x01,0xc6,0xe0,0x44,0x02,0xf0,0x22,
++0xad,0x07,0x74,0x11,0x2d,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0,0x44,0x01,0xf0,
++0x90,0x04,0x80,0xe0,0x54,0x0f,0xfc,0x74,0x14,0x2d,0xf5,0x82,0xe4,0x34,0xfc,0xf5,
++0x83,0xe0,0x54,0xc0,0x4c,0xfd,0x74,0x14,0x2f,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,
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++0xf0,0x90,0x05,0x61,0xe0,0x90,0x91,0x8d,0xf0,0x90,0x05,0x62,0xe0,0x90,0x91,0x8e,
++0xf0,0x90,0x05,0x63,0xe0,0x90,0x91,0x8f,0xf0,0x90,0x91,0x06,0xe0,0xff,0x90,0x91,
++0x8f,0xe0,0xfe,0xd3,0x9f,0x50,0x0b,0x90,0x91,0x06,0xe0,0xc3,0x9e,0xd3,0x94,0x01,
++0x40,0x11,0x90,0x90,0xf4,0xe0,0xb4,0x01,0x02,0x80,0x03,0x90,0x90,0xf8,0xe0,0xff,
++0x12,0x6e,0x67,0x22,0x90,0x91,0x07,0xe0,0x64,0x01,0x60,0x08,0x90,0x90,0xf5,0xe0,
++0x60,0x02,0x21,0x4b,0x90,0x90,0xe9,0xe0,0xc3,0x94,0xff,0x50,0x05,0xe0,0x04,0xf0,
++0x80,0x3b,0x90,0x90,0xea,0xe0,0xc3,0x94,0xff,0x50,0x06,0xe0,0x04,0xf0,0xe4,0x80,
++0x28,0x90,0x90,0xeb,0xe0,0xc3,0x94,0xff,0x50,0x0a,0xe0,0x04,0xf0,0xe4,0x90,0x90,
++0xea,0xf0,0x80,0x15,0x90,0x90,0xec,0xe0,0xc3,0x94,0xff,0x50,0x10,0xe0,0x04,0xf0,
++0xe4,0x90,0x90,0xeb,0xf0,0x90,0x90,0xea,0xf0,0x90,0x90,0xe9,0xf0,0x90,0x00,0x44,
++0xe0,0x54,0x0c,0x60,0x76,0xe0,0x30,0xe2,0x32,0x90,0x90,0xfd,0xe0,0xc3,0x94,0xff,
++0x50,0x05,0xe0,0x04,0xf0,0x80,0x24,0x90,0x90,0xfe,0xe0,0xc3,0x94,0xff,0x50,0x06,
++0xe0,0x04,0xf0,0xe4,0x80,0x11,0x90,0x90,0xff,0xe0,0xc3,0x94,0xff,0x50,0x0c,0xe0,
++0x04,0xf0,0xe4,0x90,0x90,0xfe,0xf0,0x90,0x90,0xfd,0xf0,0x90,0x00,0x44,0xe0,0x30,
++0xe3,0x32,0x90,0x91,0x00,0xe0,0xc3,0x94,0xff,0x50,0x05,0xe0,0x04,0xf0,0x80,0x24,
++0x90,0x91,0x01,0xe0,0xc3,0x94,0xff,0x50,0x06,0xe0,0x04,0xf0,0xe4,0x80,0x11,0x90,
++0x91,0x02,0xe0,0xc3,0x94,0xff,0x50,0x0c,0xe0,0x04,0xf0,0xe4,0x90,0x91,0x01,0xf0,
++0x90,0x91,0x00,0xf0,0x90,0x04,0xfd,0xe0,0x44,0x01,0xf0,0x22,0x90,0x06,0x90,0xe0,
++0x44,0x01,0xf0,0x90,0x91,0x61,0xe0,0x30,0xe0,0x3c,0x90,0x91,0x5f,0xe0,0xff,0x90,
++0x91,0x5e,0xe0,0xfe,0xc4,0x13,0x54,0x01,0xfd,0x12,0x4a,0xf6,0x90,0x91,0x60,0xe0,
++0x75,0xf0,0x20,0xa4,0xff,0xae,0xf0,0x12,0x32,0x15,0x90,0x91,0x5e,0xe0,0xc4,0x13,
++0x54,0x07,0x30,0xe0,0x07,0xa3,0xe0,0xff,0xe4,0xfd,0x80,0x07,0x90,0x91,0x5f,0xe0,
++0xff,0x7d,0x01,0x12,0x4a,0xf6,0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0xe4,0x90,
++0x91,0x19,0xf0,0xa3,0x74,0x08,0xf0,0xa3,0xf0,0xe4,0xa3,0xf0,0x90,0x01,0x1f,0xe0,
++0xfe,0x90,0x01,0x1e,0xe0,0x7c,0x00,0x24,0x00,0xff,0xec,0x3e,0x90,0x91,0x11,0xf0,
++0xa3,0xef,0xf0,0x90,0x02,0x87,0xe0,0x90,0x91,0x18,0xf0,0x90,0x91,0x56,0xe0,0x20,
++0xe0,0x02,0x61,0xc4,0xe4,0x90,0x91,0x17,0xf0,0x90,0x91,0x18,0xe0,0xff,0x90,0x91,
++0x17,0xe0,0xc3,0x9f,0x40,0x02,0x61,0xc4,0x90,0x91,0x11,0xe0,0xfc,0xa3,0xe0,0xfd,
++0xec,0xff,0x90,0xfd,0x11,0xf0,0x90,0x91,0x1c,0xef,0xf0,0x74,0x02,0x2d,0xf5,0x82,
++0xe4,0x34,0xfb,0xf5,0x83,0xe0,0x54,0x0f,0xfc,0x33,0x33,0x33,0x54,0xf8,0xff,0xed,
++0x24,0x18,0x2f,0x90,0x91,0x15,0xf0,0xe0,0x24,0x00,0xf5,0x82,0xe4,0x34,0xfb,0xf5,
++0x83,0xe0,0x54,0xfc,0x90,0x91,0x16,0xf0,0x74,0x01,0x2d,0xf5,0x82,0xe4,0x34,0xfb,
++0xf5,0x83,0xe0,0xfe,0x74,0x00,0x2d,0xf5,0x82,0xe4,0x34,0xfb,0xf5,0x83,0xe0,0x7a,
++0x00,0x24,0x00,0xff,0xea,0x3e,0x54,0x3f,0xab,0x07,0xfa,0x90,0x91,0x13,0xf0,0xa3,
++0xeb,0xf0,0xaf,0x04,0xef,0x75,0xf0,0x08,0xa4,0x24,0x18,0xff,0xe4,0x35,0xf0,0xfe,
++0xef,0x2b,0xfb,0xee,0x3a,0xfa,0x90,0x91,0x5a,0xe0,0xfe,0xa3,0xe0,0xff,0xad,0x03,
++0xac,0x02,0x12,0x45,0x09,0xaa,0x06,0xab,0x07,0x90,0x91,0x15,0xe0,0x24,0x00,0xf5,
++0x82,0xe4,0x34,0xfb,0xf5,0x83,0xe0,0x30,0xe7,0x08,0x90,0x91,0x19,0x74,0x02,0xf0,
++0x80,0x05,0xe4,0x90,0x91,0x19,0xf0,0xaf,0x03,0x90,0x91,0x11,0xea,0x8f,0xf0,0x12,
++0x42,0x81,0x90,0x91,0x5c,0xe0,0xfe,0xa3,0xe0,0xff,0x90,0x91,0x11,0xe0,0xfc,0xa3,
++0xe0,0xfd,0xd3,0x9f,0xec,0x9e,0x40,0x1b,0x90,0x91,0x5d,0xe0,0x24,0x01,0xff,0x90,
++0x91,0x5c,0xe0,0x34,0x00,0xfe,0xc3,0xed,0x9f,0xff,0xec,0x9e,0x90,0x91,0x11,0xf0,
++0xa3,0xef,0xf0,0x90,0x91,0x16,0xe0,0xff,0x24,0x40,0x60,0x04,0x24,0x20,0x70,0x27,
++0x90,0x91,0x5e,0xe0,0xfe,0xc4,0x13,0x13,0x13,0x54,0x01,0x20,0xe0,0x02,0x61,0x9c,
++0xef,0x90,0x00,0x81,0xb4,0xa0,0x05,0xe0,0x44,0x04,0x80,0x03,0xe0,0x44,0x08,0xfd,
++0x7f,0x81,0x12,0x4b,0xee,0x61,0x95,0x90,0x91,0x5e,0xe0,0xc4,0x13,0x13,0x54,0x03,
++0x20,0xe0,0x02,0x61,0x9c,0x90,0x91,0x15,0xe0,0xff,0x24,0x00,0xf5,0x82,0xe4,0x34,
++0xfb,0xf5,0x83,0xe0,0x54,0x0c,0x64,0x08,0x70,0x72,0x90,0x91,0x19,0xe0,0xfe,0xef,
++0x2e,0xff,0xa3,0xe0,0x2f,0xff,0x24,0x1e,0xf5,0x82,0xe4,0x34,0xfb,0xf5,0x83,0xe0,
++0x64,0x88,0x70,0x58,0x74,0x1f,0x2f,0xf5,0x82,0xe4,0x34,0xfb,0xf5,0x83,0xe0,0x64,
++0x8e,0x70,0x49,0x90,0x91,0x19,0xe0,0xff,0x90,0x91,0x15,0xe0,0x2f,0xff,0x90,0x91,
++0x1a,0xe0,0x2f,0xff,0xa3,0xe0,0x2f,0xff,0x24,0x19,0xf5,0x82,0xe4,0x34,0xfb,0xf5,
++0x83,0xe0,0x64,0x03,0x70,0x26,0x74,0x1e,0x2f,0xf5,0x82,0xe4,0x34,0xfb,0xf5,0x83,
++0xe0,0x90,0x00,0x81,0x30,0xe3,0x05,0xe0,0x44,0x01,0x80,0x03,0xe0,0x44,0x02,0xfd,
++0x7f,0x81,0x12,0x4b,0xee,0x90,0x91,0x56,0xe0,0x44,0x80,0xf0,0x90,0x91,0x56,0xe0,
++0xff,0xc4,0x13,0x13,0x13,0x54,0x01,0x30,0xe0,0x02,0x31,0x4c,0x71,0xc9,0xbf,0x01,
++0x13,0x90,0x91,0x11,0xe0,0xfe,0xa3,0xe0,0xff,0x12,0x44,0xb5,0x90,0x91,0x17,0xe0,
++0x04,0xf0,0x21,0xd9,0xd0,0xd0,0x92,0xaf,0x22,0x90,0x91,0x56,0xe0,0xc4,0x13,0x13,
++0x13,0x54,0x01,0x30,0xe0,0x11,0xe0,0x44,0x80,0xf0,0x90,0x91,0x5e,0xe0,0xc4,0x54,
++0x0f,0x20,0xe0,0x03,0x7f,0x00,0x22,0x7f,0x01,0x22,0x8f,0x1f,0xe4,0x90,0x91,0x22,
++0xf0,0xe5,0x1f,0x14,0xfe,0x90,0x91,0x22,0xe0,0xff,0xc3,0x9e,0x50,0x0e,0xef,0x04,
++0xfd,0x12,0x2d,0x4d,0x90,0x91,0x22,0xe0,0x04,0xf0,0x80,0xe5,0xe5,0x1f,0x14,0xff,
++0x7d,0xff,0x12,0x2d,0x4d,0x90,0x91,0x22,0xe5,0x1f,0xf0,0x90,0x91,0x22,0xe0,0xc3,
++0x94,0xff,0x50,0x0f,0xe0,0xff,0x04,0xfd,0x12,0x2d,0x4d,0x90,0x91,0x22,0xe0,0x04,
++0xf0,0x80,0xe8,0xad,0x1f,0x7f,0xff,0x02,0x2d,0x4d,0xc3,0xee,0x94,0x01,0x40,0x0a,
++0x0d,0xed,0x13,0x90,0xfd,0x10,0xf0,0xe4,0x2f,0xff,0x22,0xc3,0xee,0x94,0x01,0x40,
++0x1e,0x90,0xfd,0x11,0xe0,0xb5,0x05,0x14,0x90,0x01,0x17,0xe0,0xb5,0x05,0x07,0x90,
++0xfd,0x11,0xe4,0xf0,0x80,0x06,0xed,0x04,0x90,0xfd,0x11,0xf0,0xe4,0x2f,0xff,0x22,
++0x14,0x25,};
++
++
++
++u8 Rtl8192CUFwUMCBCutWWImgArray[UMCBCutWWImgArrayLength] = {
++0xc2,0x88,0x02,0x00,0x51,0x00,0x00,0x00,0x03,0x23,0x16,0x45,0x66,0x34,0x01,0x00,
++0x58,0x92,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x02,0x43,0x9d,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x02,0x4a,0x22,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x02,0x57,0xe1,0x00,0x00,0x00,0x00,0x00,0x02,0x58,0xc4,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++0xbb,0x01,0x0c,0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe0,0x22,0x50,
++0x06,0xe9,0x25,0x82,0xf8,0xe6,0x22,0xbb,0xfe,0x06,0xe9,0x25,0x82,0xf8,0xe2,0x22,
++0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe4,0x93,0x22,0xbb,0x01,0x06,
++0x89,0x82,0x8a,0x83,0xf0,0x22,0x50,0x02,0xf7,0x22,0xbb,0xfe,0x01,0xf3,0x22,0xf8,
++0xbb,0x01,0x0d,0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe8,0xf0,0x22,
++0x50,0x06,0xe9,0x25,0x82,0xc8,0xf6,0x22,0xbb,0xfe,0x05,0xe9,0x25,0x82,0xc8,0xf2,
++0x22,0xc5,0xf0,0xf8,0xa3,0xe0,0x28,0xf0,0xc5,0xf0,0xf8,0xe5,0x82,0x15,0x82,0x70,
++0x02,0x15,0x83,0xe0,0x38,0xf0,0x22,0xbb,0x01,0x10,0xe5,0x82,0x29,0xf5,0x82,0xe5,
++0x83,0x3a,0xf5,0x83,0xe0,0xf5,0xf0,0xa3,0xe0,0x22,0x50,0x09,0xe9,0x25,0x82,0xf8,
++0x86,0xf0,0x08,0xe6,0x22,0xbb,0xfe,0x0a,0xe9,0x25,0x82,0xf8,0xe2,0xf5,0xf0,0x08,
++0xe2,0x22,0xe5,0x83,0x2a,0xf5,0x83,0xe9,0x93,0xf5,0xf0,0xa3,0xe9,0x93,0x22,0xf8,
++0xbb,0x01,0x11,0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe8,0xf0,0xe5,
++0xf0,0xa3,0xf0,0x22,0x50,0x09,0xe9,0x25,0x82,0xc8,0xf6,0x08,0xa6,0xf0,0x22,0xbb,
++0xfe,0x09,0xe9,0x25,0x82,0xc8,0xf2,0xe5,0xf0,0x08,0xf2,0x22,0xef,0x4b,0xff,0xee,
++0x4a,0xfe,0xed,0x49,0xfd,0xec,0x48,0xfc,0x22,0xe0,0xfc,0xa3,0xe0,0xfd,0xa3,0xe0,
++0xfe,0xa3,0xe0,0xff,0x22,0xa4,0x25,0x82,0xf5,0x82,0xe5,0xf0,0x35,0x83,0xf5,0x83,
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++0x2c,0x90,0x01,0x36,0xe0,0x55,0x2a,0xf5,0x2e,0xa3,0xe0,0x55,0x2b,0xf5,0x2f,0xe5,
++0x2c,0x30,0xe0,0x5a,0x90,0x01,0x34,0x74,0x01,0xf0,0x85,0xd9,0x54,0xe5,0x70,0x14,
++0x24,0xfd,0x50,0x02,0x80,0x48,0x90,0x91,0x3b,0xe0,0x60,0x3a,0x90,0x01,0x5b,0xe4,
++0xf0,0x90,0x01,0x3c,0x74,0x04,0xf0,0x91,0x89,0xef,0x64,0x01,0x70,0x30,0x90,0x91,
++0x66,0xf0,0x90,0x91,0x2d,0xe0,0x90,0x91,0x67,0xf0,0xe4,0xfb,0xfd,0x7f,0x58,0x7e,
++0x01,0x12,0x44,0x59,0x90,0x01,0x5b,0x74,0x05,0xf0,0x90,0x06,0x92,0x74,0x01,0xf0,
++0x90,0x91,0x37,0xf0,0x80,0x08,0x91,0x89,0xbf,0x01,0x03,0x12,0x44,0xc2,0xe5,0x2c,
++0x30,0xe1,0x21,0x90,0x01,0x34,0x74,0x02,0xf0,0x85,0xd1,0x58,0x85,0xd2,0x59,0x85,
++0xd3,0x5a,0x85,0xd4,0x5b,0x85,0xd5,0x5c,0x85,0xd6,0x5d,0x85,0xd7,0x5e,0x85,0xd9,
++0x5f,0x12,0x64,0x66,0xe5,0x2c,0x30,0xe3,0x10,0x90,0x01,0x34,0x74,0x08,0xf0,0x90,
++0x91,0x56,0xe0,0x30,0xe0,0x03,0x43,0x57,0x04,0xe5,0x2c,0x30,0xe4,0x09,0x90,0x01,
++0x34,0x74,0x10,0xf0,0x43,0x57,0x10,0xe5,0x2c,0x30,0xe5,0x24,0x90,0x01,0xcf,0xe0,
++0x30,0xe5,0x1d,0xe0,0x54,0xdf,0xf0,0x90,0x01,0x34,0x74,0x20,0xf0,0x75,0xa8,0x00,
++0x75,0xe8,0x00,0xd1,0x65,0x90,0x00,0x03,0xe0,0x54,0xfb,0xf0,0x91,0xa0,0x80,0xfe,
++0xe5,0x2c,0x30,0xe6,0x06,0x90,0x01,0x34,0x74,0x40,0xf0,0xe5,0x2e,0x30,0xe0,0x15,
++0x90,0x91,0x50,0x74,0x01,0xf0,0x90,0x01,0x36,0xf0,0x12,0x63,0x2e,0x12,0x70,0xee,
++0x90,0x91,0x50,0xe4,0xf0,0xe5,0x2e,0x30,0xe1,0x3b,0x90,0x01,0x36,0x74,0x02,0xf0,
++0x43,0x57,0x40,0x90,0x01,0x02,0xe0,0x54,0x03,0x64,0x01,0x70,0x28,0x90,0x01,0x37,
++0xe0,0x30,0xe0,0x0a,0x74,0x01,0xf0,0x90,0x91,0x40,0xe4,0xf0,0x80,0x17,0x90,0x91,
++0x40,0xe0,0x04,0xf0,0xe0,0xc3,0x94,0x0a,0x40,0x0b,0xe4,0xf0,0x90,0x04,0x19,0xe0,
++0x30,0xe0,0x02,0x51,0x0c,0xe5,0x2e,0x30,0xe2,0x1a,0x90,0x01,0x36,0x74,0x04,0xf0,
++0x90,0x91,0x3a,0xe4,0xf0,0x90,0x05,0x58,0x74,0x03,0xf0,0x12,0x62,0xb8,0x90,0x91,
++0x3f,0xe0,0x04,0xf0,0xe5,0x2e,0x30,0xe3,0x28,0x90,0x01,0x36,0x74,0x08,0xf0,0xe5,
++0x6d,0x64,0x01,0x70,0x1c,0xe5,0x70,0x60,0x18,0x90,0x01,0x57,0xe4,0xf0,0x90,0x01,
++0x3c,0x74,0x02,0xf0,0x90,0x91,0x66,0xe4,0x12,0x44,0x49,0x90,0x01,0x57,0x74,0x05,
++0xf0,0xe5,0x2e,0x30,0xe4,0x2b,0x90,0x01,0x36,0x74,0x10,0xf0,0xe5,0x6d,0xb4,0x01,
++0x20,0xe5,0x70,0x60,0x1c,0x90,0x01,0x57,0xe4,0xf0,0x90,0x01,0x3c,0x74,0x02,0xf0,
++0x90,0x91,0x3c,0xe4,0xf0,0x53,0x71,0xfd,0xe5,0x71,0x54,0x07,0x70,0x03,0x12,0x44,
++0xc2,0xe5,0x2e,0x30,0xe5,0x1f,0x90,0x01,0x36,0x74,0x20,0xf0,0xe5,0x6d,0xb4,0x01,
++0x14,0xe5,0x70,0x60,0x10,0x90,0x91,0x3b,0xe0,0x64,0x02,0x60,0x05,0x12,0x44,0xc8,
++0x80,0x03,0x12,0x44,0x77,0xe5,0x2e,0x30,0xe6,0x1b,0x90,0x01,0x36,0x74,0x40,0xf0,
++0xe5,0x6d,0xb4,0x01,0x10,0xe5,0x70,0x60,0x0c,0x53,0x71,0xfe,0xe5,0x71,0x54,0x07,
++0x70,0x03,0x12,0x44,0xc2,0xe5,0x2f,0x30,0xe1,0x09,0x90,0x01,0x37,0x74,0x02,0xf0,
++0x12,0x64,0x31,0x74,0x22,0x04,0x90,0x01,0xc4,0xf0,0x74,0x4a,0xa3,0xf0,0xd0,0x07,
++0xd0,0x06,0xd0,0x05,0xd0,0x04,0xd0,0x03,0xd0,0x02,0xd0,0x01,0xd0,0x00,0xd0,0xd0,
++0xd0,0x82,0xd0,0x83,0xd0,0xf0,0xd0,0xe0,0x32,0x90,0x04,0x1b,0xe0,0x54,0x7f,0x64,
++0x7f,0x7f,0x01,0x60,0x02,0x7f,0x00,0x22,0xf4,0xff,0x90,0x00,0x43,0xe0,0x5f,0xf0,
++0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x7f,0x10,0xdf,0xfe,0xd0,0xd0,0x92,0xaf,0x22,
++0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x90,0x91,0x9b,0xed,0xf0,0x90,0x91,0x9a,0xef,
++0xf0,0xd3,0x94,0x07,0x50,0x63,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,
++0x33,0xd8,0xfc,0xf4,0xff,0x90,0x00,0x47,0xe0,0x5f,0xf0,0x91,0xa0,0x90,0x91,0x9a,
++0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xff,0x90,0x00,
++0x46,0xe0,0x4f,0xf0,0x91,0xa0,0x90,0x91,0x9b,0xe0,0x60,0x16,0x90,0x91,0x9a,0xe0,
++0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xff,0x90,0x00,0x45,
++0x80,0x66,0x90,0x91,0x9a,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,
++0xd8,0xfc,0xf4,0xff,0x90,0x00,0x45,0x80,0x6b,0x90,0x91,0x9a,0xe0,0x24,0xf8,0xf0,
++0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xc4,0x54,0xf0,
++0x91,0x98,0x90,0x91,0x9a,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,
++0xd8,0xfc,0xff,0x90,0x00,0x43,0xe0,0x4f,0xf0,0x91,0xa0,0x90,0x91,0x9b,0xe0,0x60,
++0x1b,0x90,0x91,0x9a,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,
++0xfc,0xc4,0x54,0xf0,0xff,0x90,0x00,0x42,0xe0,0x4f,0x80,0x1a,0x90,0x91,0x9a,0xe0,
++0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xc4,0x54,0xf0,0xf4,
++0xff,0x90,0x00,0x42,0xe0,0x5f,0xf0,0x91,0xa0,0xd0,0xd0,0x92,0xaf,0x22,0xf0,0x90,
++0x00,0x45,0xe0,0x54,0xfe,0xfd,0x7f,0x45,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x8f,
++0x82,0x75,0x83,0x00,0xed,0xf0,0x91,0xa0,0xd0,0xd0,0x92,0xaf,0x22,0xef,0x14,0x60,
++0x30,0x14,0x60,0x66,0x24,0x02,0x60,0x02,0xc1,0x64,0x90,0x90,0xf3,0x74,0x02,0xf0,
++0x90,0x00,0x48,0xe0,0x44,0x0c,0xfd,0x7f,0x48,0xb1,0xa8,0x90,0x00,0x47,0xe0,0x44,
++0x08,0xfd,0x7f,0x47,0xb1,0xa8,0x90,0x00,0x45,0xe0,0x44,0x10,0xfd,0x7f,0x45,0x80,
++0x71,0xe4,0x90,0x90,0xf3,0xf0,0x90,0x90,0xef,0x12,0x43,0x09,0x90,0x80,0x85,0x12,
++0x2a,0x7f,0x7f,0x80,0x7e,0x08,0x12,0x2f,0xd9,0x90,0x00,0x45,0xe0,0x44,0xef,0xfd,
++0x7f,0x45,0xb1,0xa8,0x90,0x00,0x45,0xe0,0x54,0xef,0xfd,0x7f,0x45,0xb1,0xa8,0x90,
++0x00,0x46,0xe0,0x44,0x10,0xfd,0x7f,0x46,0x80,0x38,0x90,0x90,0xf3,0x74,0x01,0xf0,
++0x90,0x90,0xf9,0x12,0x43,0x09,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x80,0x7e,0x08,
++0x12,0x2f,0xd9,0x90,0x00,0x45,0xe0,0x44,0x20,0xfd,0x7f,0x45,0xb1,0xa8,0x90,0x00,
++0x45,0xe0,0x44,0x10,0xfd,0x7f,0x45,0xb1,0xa8,0x90,0x00,0x46,0xe0,0x44,0x10,0xfd,
++0x7f,0x46,0xb1,0xa8,0x22,0x90,0x01,0x30,0xe4,0xf0,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,
++0x90,0x01,0x38,0xf0,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0xfd,0x7f,0x50,0xb1,0xa8,0xe4,
++0xfd,0x7f,0x51,0xb1,0xa8,0xe4,0xfd,0x7f,0x52,0xb1,0xa8,0xe4,0xfd,0x7f,0x53,0xa1,
++0xa8,0x8b,0x0e,0x8a,0x0f,0x89,0x10,0x90,0x00,0x02,0x12,0x42,0x20,0x90,0x90,0xf6,
++0xf0,0xe0,0x30,0xe0,0x4b,0x90,0x90,0xed,0x74,0x01,0xf0,0x7f,0x80,0x7e,0x08,0x12,
++0x27,0xde,0x90,0x90,0xef,0x12,0x2a,0x7f,0xab,0x0e,0xaa,0x0f,0xa9,0x10,0x90,0x00,
++0x01,0x12,0x42,0x20,0xff,0xe4,0xfc,0xfd,0xfe,0x78,0x1a,0x12,0x2a,0x6c,0xa8,0x04,
++0xa9,0x05,0xaa,0x06,0xab,0x07,0x90,0x90,0xef,0x12,0x43,0x09,0xec,0x54,0x03,0xfc,
++0x12,0x42,0xfc,0x90,0x90,0xf9,0x12,0x2a,0x7f,0x90,0x05,0x22,0xe4,0xf0,0x80,0x2d,
++0xe4,0x90,0x90,0xed,0xf0,0x7f,0x80,0x7e,0x08,0x12,0x27,0xde,0xec,0x54,0x03,0xfc,
++0xec,0x44,0xc0,0xfc,0x90,0x90,0xef,0x12,0x2a,0x7f,0x90,0x90,0xef,0x12,0x43,0x09,
++0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x80,0x7e,0x08,0x12,0x2f,0xd9,0x90,0x90,0xf6,
++0xe0,0x30,0xe1,0x19,0x7d,0x0c,0x7f,0x47,0xb1,0xa8,0x90,0x00,0x48,0xe0,0x44,0x0c,
++0xfd,0x7f,0x48,0xb1,0xa8,0x90,0x00,0x46,0xe0,0x44,0x10,0x80,0x1c,0x90,0x00,0x47,
++0xe0,0x54,0xf3,0xfd,0x7f,0x47,0xb1,0xa8,0x90,0x00,0x48,0xe0,0x54,0xf3,0xfd,0x7f,
++0x48,0xb1,0xa8,0x90,0x00,0x46,0xe0,0x54,0xef,0xfd,0x7f,0x46,0xb1,0xa8,0xe4,0x90,
++0x90,0xf3,0xf0,0x22,0x90,0x01,0x3c,0x74,0xff,0xf0,0xa3,0xf0,0xa3,0xf0,0x90,0x01,
++0x34,0xf0,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0xfd,0x7f,0x54,0xb1,0xa8,0x7d,0xff,0x7f,
++0x55,0xb1,0xa8,0x7d,0xff,0x7f,0x56,0xb1,0xa8,0x7d,0xff,0x7f,0x57,0xa1,0xa8,0xe5,
++0x72,0x64,0x01,0x70,0x3e,0x12,0x54,0x41,0xbf,0x01,0x05,0x7f,0x01,0x12,0x56,0xe7,
++0x90,0x00,0x46,0xe0,0x44,0x04,0xfd,0x7f,0x46,0xb1,0xa8,0x90,0x00,0x44,0xe0,0x54,
++0xfb,0xfd,0x7f,0x44,0xb1,0xa8,0x90,0x00,0x46,0xe0,0x54,0xfb,0xfd,0x7f,0x46,0xb1,
++0xa8,0x7f,0x02,0x12,0x6f,0x09,0x8f,0x76,0x90,0x01,0xc9,0xe5,0x76,0xf0,0xb4,0x01,
++0x02,0xf1,0xd4,0x22,0x90,0x00,0x49,0xe0,0x90,0x91,0x9f,0xf0,0xe0,0x54,0x0f,0xf0,
++0x44,0xf0,0xfd,0x7f,0x49,0xb1,0xa8,0x90,0x91,0x9f,0xe0,0x44,0xb0,0xfd,0x7f,0x49,
++0xa1,0xa8,0xe4,0x90,0x91,0x3c,0xf0,0x90,0x91,0x28,0xf0,0xf5,0x71,0x22,0x75,0x28,
++0x33,0xe4,0xf5,0x29,0x75,0x2a,0x07,0xf5,0x2b,0x90,0x01,0x30,0xe5,0x28,0xf0,0xa3,
++0xe5,0x29,0xf0,0xa3,0xe5,0x2a,0xf0,0xa3,0xe5,0x2b,0xf0,0x22,0x75,0x30,0x1f,0x75,
++0x31,0x01,0xe4,0xf5,0x32,0x90,0x01,0x38,0xe5,0x30,0xf0,0xa3,0xe5,0x31,0xf0,0xa3,
++0xe5,0x32,0xf0,0x22,0xe4,0x90,0x91,0x0e,0xf0,0xa3,0xf0,0x75,0x8e,0x02,0xf1,0x02,
++0xd1,0xb4,0x90,0x91,0x4f,0xef,0xf0,0xd1,0xdb,0x90,0x91,0x51,0xef,0xf0,0xf1,0x3d,
++0x90,0x91,0x3d,0xee,0xf0,0xa3,0xef,0xf0,0xe4,0xf5,0x57,0xd1,0xd2,0x12,0x60,0x37,
++0x12,0x32,0x3d,0xd1,0xc1,0x12,0x4f,0xfe,0xf1,0x13,0xd1,0xcb,0x11,0x1c,0x12,0x44,
++0xff,0x31,0x23,0x11,0xdf,0x12,0x6f,0xaa,0x90,0x91,0x10,0xe5,0xd9,0xf0,0x12,0x4f,
++0x64,0xc2,0xaf,0x90,0x00,0x80,0xe0,0x44,0x40,0xf0,0x12,0x4c,0xa0,0x75,0xe8,0x03,
++0x43,0xa8,0x85,0xd2,0xaf,0x90,0x91,0x0e,0xe0,0x64,0x01,0xf0,0x24,0x34,0x90,0x01,
++0xc4,0xf0,0x74,0x50,0xa3,0xf0,0xe5,0x57,0x30,0xe2,0x10,0x12,0x5e,0x63,0xbf,0x01,
++0x0a,0xc2,0xaf,0x53,0x57,0xfb,0xd2,0xaf,0x12,0x71,0x8a,0xe5,0x57,0x30,0xe4,0x0a,
++0xc2,0xaf,0x53,0x57,0xef,0xd2,0xaf,0x12,0x5e,0xa0,0x90,0x90,0xf7,0xe0,0x70,0x03,
++0x12,0x70,0x08,0x11,0xf7,0x90,0x91,0x3f,0xe0,0x90,0x01,0xba,0xf0,0x80,0xb6,0x90,
++0x91,0x53,0xe0,0x54,0xfe,0xf0,0xe4,0x90,0x91,0x55,0xf0,0x90,0x91,0x53,0xe0,0x54,
++0x7f,0xf0,0xa3,0x74,0x0a,0xf0,0x22,0x90,0x06,0x34,0xe0,0x60,0x25,0x14,0x70,0x1b,
++0x7b,0x01,0x7a,0x06,0x79,0x35,0x7f,0xf9,0x7e,0x01,0x12,0x68,0x1a,0xbf,0x01,0x09,
++0x90,0x06,0x35,0xe0,0x54,0x0f,0xf0,0x80,0x04,0x80,0x00,0xc1,0xf4,0xe4,0x90,0x06,
++0x34,0xf0,0x22,0x90,0x91,0x56,0xe0,0x54,0xfe,0xf0,0xe0,0x54,0x7f,0xf0,0x90,0x01,
++0x17,0xe0,0xfe,0x90,0x01,0x16,0xe0,0x7c,0x00,0x24,0x00,0xff,0xec,0x3e,0x90,0x91,
++0x5c,0xf0,0xa3,0xef,0xf0,0x90,0x01,0x04,0xe0,0x54,0x0f,0x90,0x91,0x1c,0xf0,0xe0,
++0xff,0x74,0x40,0x7e,0x00,0xa8,0x07,0x08,0x80,0x05,0xc3,0x33,0xce,0x33,0xce,0xd8,
++0xf9,0x90,0x91,0x5b,0xf0,0xee,0x90,0x91,0x5a,0xf0,0x90,0x91,0x5e,0xe0,0x54,0xfe,
++0xf0,0xe0,0x54,0xfd,0xf0,0xe0,0x54,0xfb,0xf0,0xe0,0x54,0xf7,0xf0,0xe0,0x54,0xef,
++0xf0,0xe0,0x54,0xdf,0xf0,0xe0,0x54,0xbf,0xf0,0xe0,0x54,0x7f,0xf0,0xe4,0xa3,0xf0,
++0xa3,0xf0,0xa3,0xe0,0x54,0xfe,0xf0,0xe0,0x54,0xfd,0xf0,0xe0,0x54,0xf7,0xf0,0x22,
++0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x12,0x29,0xd9,0x54,0x01,0xff,0x90,0x91,0x56,
++0xe0,0x54,0xfe,0x4f,0xf0,0x90,0x00,0x01,0x12,0x42,0x20,0x90,0x91,0x57,0xf0,0x90,
++0x00,0x02,0x12,0x42,0x20,0x90,0x91,0x58,0xf0,0x90,0x91,0x56,0xe0,0x30,0xe0,0x1a,
++0x90,0x06,0x09,0xe0,0x54,0xfe,0xf0,0x90,0x02,0x86,0xe0,0x44,0x04,0xf0,0x43,0x57,
++0x04,0x7d,0x08,0xe4,0xff,0x12,0x36,0xe6,0x80,0x12,0x7d,0x08,0xe4,0xff,0x12,0x36,
++0x75,0x90,0x02,0x86,0xe0,0x54,0xfb,0xf0,0x51,0x01,0x31,0x23,0xd0,0xd0,0x92,0xaf,
++0x22,0x90,0x06,0x90,0xe4,0xf0,0x21,0x6a,0x90,0x91,0x19,0x12,0x43,0x41,0xef,0x12,
++0x43,0x4a,0x52,0x40,0x01,0x52,0x49,0x02,0x52,0x6a,0x03,0x52,0x73,0x09,0x52,0x7b,
++0x0c,0x52,0x84,0x0d,0x52,0x8c,0x0e,0x52,0x9d,0x1a,0x52,0xa5,0x2c,0x52,0x51,0x2d,
++0x52,0x5a,0x2e,0x52,0xad,0x30,0x52,0x62,0x3b,0x52,0x95,0x3c,0x00,0x00,0x52,0xb5,
++0x90,0x91,0x19,0x12,0x43,0x21,0x02,0x64,0xde,0x90,0x91,0x19,0x12,0x43,0x21,0xc1,
++0xc5,0x90,0x91,0x19,0x12,0x43,0x21,0x02,0x65,0xf9,0x90,0x91,0x19,0x12,0x43,0x21,
++0xe1,0xa8,0x90,0x91,0x19,0x12,0x43,0x21,0xe1,0x28,0x90,0x91,0x19,0x12,0x43,0x21,
++0x02,0x66,0x41,0x90,0x91,0x19,0x12,0x43,0x21,0x80,0x42,0x90,0x91,0x19,0x12,0x43,
++0x21,0x02,0x5d,0x16,0x90,0x91,0x19,0x12,0x43,0x21,0xe1,0x75,0x90,0x91,0x19,0x12,
++0x43,0x21,0x02,0x4e,0x91,0x90,0x91,0x19,0x12,0x43,0x21,0x21,0xa0,0x90,0x91,0x19,
++0x12,0x43,0x21,0xa1,0x7f,0x90,0x91,0x19,0x12,0x43,0x21,0x81,0x5e,0x90,0x91,0x19,
++0x12,0x43,0x21,0xe1,0x55,0x90,0x01,0xc6,0xe0,0x44,0x01,0xf0,0x22,0xd3,0x10,0xaf,
++0x01,0xc3,0xc0,0xd0,0x90,0x91,0x1c,0x12,0x43,0x41,0x90,0x91,0x1c,0x12,0x43,0x21,
++0x90,0x00,0x01,0x12,0x42,0x97,0xfa,0xe5,0xf0,0x24,0x00,0xff,0xe4,0x3a,0xfe,0x90,
++0x91,0x1c,0x12,0x43,0x21,0x90,0x00,0x01,0xee,0x8f,0xf0,0x12,0x42,0xcf,0x12,0x29,
++0xd9,0xff,0x60,0x2c,0xb5,0x72,0x16,0x90,0x91,0x1c,0x12,0x43,0x21,0x90,0x00,0x01,
++0x12,0x42,0x97,0x65,0x74,0x70,0x04,0xe5,0x73,0x65,0xf0,0x60,0x23,0x90,0x91,0x1c,
++0x12,0x43,0x21,0x90,0x00,0x01,0x12,0x42,0x97,0xff,0xae,0xf0,0x71,0x35,0x80,0x10,
++0x90,0x91,0x1c,0x12,0x43,0x21,0x12,0x29,0xd9,0x65,0x72,0x60,0x03,0x12,0x44,0xe8,
++0xd0,0xd0,0x92,0xaf,0x22,0x90,0x91,0x1f,0xee,0xf0,0xa3,0xef,0xf0,0x75,0x72,0x01,
++0x8e,0x73,0xf5,0x74,0xe4,0xfd,0x7f,0x0b,0x71,0x77,0xe4,0xfd,0x7f,0x02,0x71,0x77,
++0x91,0x41,0xe4,0xff,0xd1,0xe7,0xe4,0xf5,0x76,0x90,0x01,0xc9,0xe5,0x76,0xf0,0x90,
++0x91,0x1f,0xe0,0xfc,0xa3,0xe0,0xfd,0xec,0xfb,0x8d,0x44,0xe4,0xf5,0x45,0x7d,0x01,
++0x7f,0x60,0x7e,0x01,0x02,0x35,0xab,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x90,0x91,
++0x22,0xed,0xf0,0x90,0x91,0x21,0xef,0xf0,0xd3,0x94,0x07,0x50,0x4f,0xa3,0xe0,0x70,
++0x1a,0x90,0x91,0x21,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,
++0xfc,0xf4,0xff,0x90,0x00,0x47,0xe0,0x5f,0xf0,0x80,0x17,0x90,0x91,0x21,0xe0,0xff,
++0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xff,0x90,0x00,0x47,0xe0,
++0x4f,0xf0,0x12,0x4c,0xa0,0x90,0x91,0x21,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,
++0x02,0xc3,0x33,0xd8,0xfc,0xf4,0xff,0x90,0x00,0x46,0x80,0x5a,0x90,0x91,0x21,0xe0,
++0x24,0xf8,0xf0,0xa3,0xe0,0x70,0x1d,0x90,0x91,0x21,0xe0,0xff,0x74,0x01,0xa8,0x07,
++0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xc4,0x54,0xf0,0xf4,0xff,0x90,0x00,0x43,0xe0,
++0x5f,0xf0,0x80,0x1a,0x90,0x91,0x21,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,
++0xc3,0x33,0xd8,0xfc,0xc4,0x54,0xf0,0xff,0x90,0x00,0x43,0xe0,0x4f,0xf0,0x12,0x4c,
++0xa0,0x90,0x91,0x21,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,
++0xfc,0xf4,0xff,0x90,0x00,0x43,0xe0,0x5f,0xf0,0x12,0x4c,0xa0,0xd0,0xd0,0x92,0xaf,
++0x22,0x7f,0x0b,0x12,0x6f,0x09,0xef,0x65,0x75,0x60,0x10,0xe5,0x75,0xb4,0x01,0x05,
++0xe4,0xf5,0x75,0x80,0x03,0x75,0x75,0x01,0x7f,0x01,0x22,0x7f,0x00,0x22,0xd3,0x10,
++0xaf,0x01,0xc3,0xc0,0xd0,0xe4,0xf5,0x10,0x75,0x11,0x04,0xf5,0x12,0xf5,0x14,0xf5,
++0x15,0x90,0x02,0x09,0xe0,0xff,0x12,0x29,0xd9,0xfe,0xef,0x2e,0xf5,0x13,0x30,0xe0,
++0x08,0x75,0x0e,0x00,0x75,0x0f,0x80,0x80,0x05,0xe4,0xf5,0x0e,0xf5,0x0f,0xe5,0x13,
++0xc3,0x13,0x90,0xfd,0x10,0xf0,0x74,0x20,0x25,0x10,0xf5,0x10,0xad,0x0f,0xe5,0x10,
++0x2d,0xff,0x24,0x01,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0,0x90,0x91,0x47,0xf0,
++0x74,0x02,0x2f,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0,0xfe,0xe5,0x10,0x2d,0x24,
++0x03,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0,0x24,0x00,0xff,0xe4,0x3e,0x90,0x91,
++0x48,0xf0,0xa3,0xef,0xf0,0x7f,0x04,0xe5,0x10,0x25,0x0f,0x2f,0x24,0x00,0xf5,0x82,
++0xe4,0x34,0xfc,0xf5,0x83,0xe0,0xfe,0x74,0x46,0x2f,0xf5,0x82,0xe4,0x34,0x91,0xf5,
++0x83,0xee,0xf0,0x0f,0xbf,0x08,0xe0,0x12,0x66,0x89,0xef,0x70,0x3f,0x90,0x01,0xc3,
++0xe0,0x60,0x25,0xc3,0xe5,0x15,0x94,0xe8,0xe5,0x14,0x94,0x03,0x40,0x09,0x90,0x01,
++0xc6,0xe0,0x44,0x10,0xf0,0x80,0x63,0x05,0x15,0xe5,0x15,0x70,0x02,0x05,0x14,0x7f,
++0x0a,0x7e,0x00,0x12,0x37,0x54,0x80,0xd5,0x90,0x01,0xc6,0xe0,0x90,0x01,0xc3,0x30,
++0xe2,0x05,0x74,0xfe,0xf0,0x80,0x43,0x74,0xff,0xf0,0x80,0x3e,0xe5,0x10,0xb4,0x78,
++0x23,0xe4,0xf5,0x10,0x05,0x13,0xe5,0x0f,0x64,0x80,0x45,0x0e,0x70,0x06,0xf5,0x0e,
++0xf5,0x0f,0x80,0x06,0x75,0x0e,0x00,0x75,0x0f,0x80,0xe5,0x13,0xc3,0x13,0x90,0xfd,
++0x10,0xf0,0x80,0x06,0x74,0x08,0x25,0x10,0xf5,0x10,0xe5,0x12,0x15,0x12,0x70,0x02,
++0x15,0x11,0xe5,0x12,0x45,0x11,0x60,0x02,0x81,0x9c,0xd0,0xd0,0x92,0xaf,0x22,0x90,
++0x91,0x1c,0x12,0x43,0x41,0x12,0x29,0xd9,0xff,0x54,0x01,0xfe,0x90,0x91,0x5e,0xe0,
++0x54,0xfe,0x4e,0xf0,0xef,0x54,0x04,0xff,0xe0,0x54,0xfb,0x4f,0xf0,0x12,0x29,0xd9,
++0xff,0x54,0x02,0xfe,0x90,0x91,0x5e,0xe0,0x54,0xfd,0x4e,0xf0,0xef,0x54,0x08,0xff,
++0xe0,0x54,0xf7,0x4f,0xf0,0x12,0x29,0xd9,0xff,0x54,0x10,0xfe,0x90,0x91,0x5e,0xe0,
++0x54,0xef,0x4e,0xf0,0xef,0x54,0x20,0xff,0xe0,0x54,0xdf,0x4f,0xf0,0x12,0x29,0xd9,
++0xff,0x54,0x40,0xfe,0x90,0x91,0x5e,0xe0,0x54,0xbf,0x4e,0xf0,0xef,0x54,0x80,0xff,
++0xe0,0x54,0x7f,0x4f,0xf0,0x90,0x00,0x02,0x12,0x42,0x20,0x90,0x91,0x60,0xf0,0x90,
++0x00,0x01,0x12,0x42,0x20,0x90,0x91,0x5f,0xf0,0x90,0x00,0x03,0x12,0x42,0x20,0xff,
++0x54,0x01,0xfe,0x90,0x91,0x61,0xe0,0x54,0xfe,0x4e,0xf0,0xef,0x54,0x02,0xff,0xe0,
++0x54,0xfd,0x4f,0xf0,0x90,0x00,0x03,0x12,0x42,0x20,0x54,0x04,0xff,0x90,0x91,0x61,
++0xe0,0x54,0xfb,0x4f,0xf0,0x90,0x91,0x5e,0xe0,0x54,0x01,0x90,0x01,0xb8,0xf0,0x90,
++0x91,0x5e,0xe0,0xff,0xc4,0x13,0x54,0x01,0x90,0x01,0xb9,0xf0,0x90,0x91,0x61,0xe0,
++0x54,0x01,0x90,0x01,0xba,0xf0,0xa3,0x74,0xff,0xf0,0x12,0x29,0xd9,0x20,0xe0,0x02,
++0x41,0x01,0xe4,0xfd,0x7f,0x81,0x12,0x4d,0xa8,0x90,0x91,0x1c,0x12,0x43,0x21,0x12,
++0x29,0xd9,0xff,0xc3,0x13,0x30,0xe0,0x07,0x90,0x06,0x90,0xe0,0x44,0x02,0xf0,0xef,
++0x13,0x13,0x54,0x3f,0x30,0xe0,0x07,0x90,0x06,0x90,0xe0,0x44,0x04,0xf0,0x12,0x29,
++0xd9,0x13,0x13,0x13,0x54,0x1f,0x30,0xe0,0x07,0x90,0x06,0x90,0xe0,0x44,0x08,0xf0,
++0x90,0x91,0x61,0xe0,0x30,0xe0,0x1c,0x90,0x91,0x5e,0xe0,0xc4,0x13,0x54,0x07,0x30,
++0xe0,0x07,0xa3,0xe0,0xff,0xe4,0xfd,0x80,0x07,0x90,0x91,0x5f,0xe0,0xff,0x7d,0x01,
++0x12,0x4c,0xb0,0x22,0x90,0x00,0x02,0xe0,0x54,0xe0,0x7f,0x01,0x60,0x02,0x7f,0x00,
++0x22,0xe4,0xf5,0x75,0x22,0x12,0x29,0xd9,0xf5,0x6d,0x22,0x90,0x01,0x64,0x74,0xa0,
++0xf0,0x22,0x90,0x91,0x51,0xe0,0x90,0x90,0xe8,0xf0,0x22,0x90,0x00,0xf3,0xe0,0x7f,
++0x00,0x30,0xe3,0x02,0x7f,0x01,0x22,0x90,0x01,0xca,0xe5,0x75,0xf0,0xef,0x60,0x03,
++0x12,0x4f,0xd4,0x22,0x90,0x06,0x34,0x74,0xff,0xf0,0xe4,0xa3,0xf0,0xa3,0xf0,0xa3,
++0xf0,0x22,0xe4,0x90,0x91,0x4e,0xf0,0x90,0x00,0x80,0xe0,0x44,0x80,0xfd,0x7f,0x80,
++0x02,0x4d,0xa8,0x90,0x00,0xf3,0xe0,0x30,0xe2,0x0d,0x90,0x05,0x41,0x74,0x10,0xf0,
++0x90,0x05,0x5a,0xf0,0xa3,0xe4,0xf0,0x22,0x12,0x29,0xd9,0x60,0x02,0x80,0x01,0xe4,
++0x90,0x91,0x31,0xf0,0x90,0x91,0x31,0xe0,0x90,0x01,0xe7,0xf0,0x22,0x90,0x91,0x51,
++0xe0,0xb4,0x01,0x0c,0x90,0x00,0xf2,0xe0,0x30,0xe7,0x05,0x7e,0xfd,0x7f,0x33,0x22,
++0x7e,0xfd,0x7f,0x2f,0x22,0x12,0x29,0xd9,0xff,0x54,0x01,0xfe,0x90,0x91,0x53,0xe0,
++0x54,0xfe,0x4e,0xf0,0xef,0xc3,0x13,0x30,0xe0,0x0a,0x90,0x00,0x01,0x12,0x42,0x20,
++0x90,0x91,0x54,0xf0,0x22,0x90,0x00,0x02,0x12,0x42,0x20,0x90,0x90,0xf7,0xf0,0xe0,
++0x60,0x04,0xe0,0xf4,0x70,0x21,0xa2,0xaf,0xe4,0x33,0xf5,0x0e,0xc2,0xaf,0x90,0x00,
++0x47,0xe0,0x54,0xfb,0xfd,0x7f,0x47,0x12,0x4d,0xa8,0x7d,0x40,0x7f,0x01,0x12,0x36,
++0xaf,0xe5,0x0e,0x24,0xff,0x92,0xaf,0x22,0x12,0x29,0xd9,0x30,0xe0,0x19,0xc3,0x13,
++0x54,0x7f,0x90,0x91,0x34,0xf0,0x90,0x00,0x01,0x12,0x42,0x20,0xff,0x90,0x91,0x32,
++0xe4,0xf0,0xa3,0xef,0xf0,0x80,0x0f,0x90,0x91,0x34,0x74,0x07,0xf0,0x90,0x91,0x32,
++0xe4,0xf0,0xa3,0x74,0x03,0xf0,0x90,0x91,0x32,0xe0,0xa3,0xe0,0x90,0x05,0x58,0xf0,
++0x22,0xc0,0xe0,0xc0,0xf0,0xc0,0x83,0xc0,0x82,0xc0,0xd0,0x75,0xd0,0x00,0xc0,0x00,
++0xc0,0x01,0xc0,0x02,0xc0,0x03,0xc0,0x04,0xc0,0x05,0xc0,0x06,0xc0,0x07,0x90,0x01,
++0xc4,0x74,0xe1,0xf0,0x74,0x57,0xa3,0xf0,0x53,0x91,0xef,0x90,0x00,0x51,0xe0,0xff,
++0x90,0x00,0x55,0xe0,0x5f,0xf5,0x3d,0x90,0x00,0x52,0xe0,0xff,0x90,0x00,0x56,0xe0,
++0x5f,0xf5,0x3e,0xe5,0x3d,0x30,0xe4,0x06,0x90,0x00,0x55,0x74,0x10,0xf0,0xe5,0x3d,
++0x30,0xe5,0x06,0x90,0x00,0x55,0x74,0x20,0xf0,0xe5,0x3d,0x30,0xe6,0x1b,0x90,0x00,
++0x55,0x74,0x40,0xf0,0x90,0x90,0xf6,0xe0,0x54,0x03,0xff,0xbf,0x03,0x0b,0x90,0x90,
++0xf3,0xe0,0x60,0x05,0x7f,0x01,0x12,0x4d,0xbd,0xe5,0x3d,0x30,0xe7,0x15,0x90,0x00,
++0x55,0x74,0x80,0xf0,0x90,0x90,0xf6,0xe0,0x54,0x03,0xff,0xbf,0x03,0x05,0x7f,0x02,
++0x12,0x4d,0xbd,0xe5,0x3e,0x30,0xe0,0x06,0x90,0x00,0x56,0x74,0x01,0xf0,0xe5,0x3e,
++0x30,0xe1,0x06,0x90,0x00,0x56,0x74,0x02,0xf0,0xe5,0x3e,0x30,0xe2,0x06,0x90,0x00,
++0x56,0x74,0x04,0xf0,0xe5,0x3e,0x30,0xe3,0x06,0x90,0x00,0x56,0x74,0x08,0xf0,0x90,
++0x01,0xc4,0x74,0xe1,0xf0,0x74,0x57,0xa3,0xf0,0xd0,0x07,0xd0,0x06,0xd0,0x05,0xd0,
++0x04,0xd0,0x03,0xd0,0x02,0xd0,0x01,0xd0,0x00,0xd0,0xd0,0xd0,0x82,0xd0,0x83,0xd0,
++0xf0,0xd0,0xe0,0x32,0xc0,0xe0,0xc0,0xf0,0xc0,0x83,0xc0,0x82,0xc0,0xd0,0x75,0xd0,
++0x00,0xc0,0x00,0xc0,0x01,0xc0,0x02,0xc0,0x03,0xc0,0x04,0xc0,0x05,0xc0,0x06,0xc0,
++0x07,0x75,0x0d,0x00,0x90,0x01,0xc4,0x74,0xc4,0xf0,0x74,0x58,0xa3,0xf0,0x53,0x91,
++0xdf,0x90,0x01,0x3c,0xe0,0x55,0x30,0xf5,0x34,0xa3,0xe0,0x55,0x31,0xf5,0x35,0xa3,
++0xe0,0x55,0x32,0xf5,0x36,0xa3,0xe0,0x55,0x33,0xf5,0x37,0xe5,0x34,0x30,0xe0,0x06,
++0x90,0x01,0x3c,0x74,0x01,0xf0,0xe5,0x34,0x30,0xe1,0x08,0x90,0x01,0x3c,0x74,0x02,
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++0xf0,0xa3,0x74,0x03,0xf0,0x90,0x91,0x2f,0x74,0x0a,0xf0,0xa3,0x74,0x05,0xf0,0x90,
++0x91,0x2d,0x74,0x14,0xf0,0x90,0x91,0x35,0x74,0x05,0xf0,0xe4,0x90,0x91,0x2b,0xf0,
++0x90,0x91,0x25,0xf0,0x90,0x91,0x50,0xf0,0x90,0x91,0x31,0xf0,0x90,0x91,0x3a,0xf0,
++0x90,0x91,0x26,0xf0,0x90,0x91,0x38,0xf0,0x90,0x91,0x2e,0xf0,0x90,0x91,0x2c,0xf0,
++0x22,0x12,0x4c,0x89,0xef,0x64,0x01,0x60,0x08,0x90,0x01,0xb9,0x74,0x01,0xf0,0x80,
++0x30,0x90,0x91,0x37,0xe0,0x60,0x08,0x90,0x01,0xb9,0x74,0x02,0xf0,0x80,0x22,0x90,
++0x91,0x36,0xe0,0x60,0x08,0x90,0x01,0xb9,0x74,0x04,0xf0,0x80,0x14,0xe5,0x6f,0x54,
++0x0f,0xd3,0x94,0x04,0x40,0x08,0x90,0x01,0xb9,0x74,0x08,0xf0,0x80,0x03,0x7f,0x01,
++0x22,0x90,0x01,0xb8,0x74,0x08,0xf0,0x7f,0x00,0x22,0x12,0x4c,0x89,0xef,0x64,0x01,
++0x60,0x08,0x90,0x01,0xb9,0x74,0x01,0xf0,0x80,0x58,0xe5,0x71,0x54,0x03,0x60,0x08,
++0x90,0x01,0xb9,0x74,0x02,0xf0,0x80,0x4a,0xe5,0x6f,0x54,0x0f,0xd3,0x94,0x02,0x40,
++0x08,0x90,0x01,0xb9,0x74,0x04,0xf0,0x80,0x39,0xe5,0x71,0x30,0xe2,0x08,0x90,0x01,
++0xb9,0x74,0x08,0xf0,0x80,0x2c,0xe5,0x71,0x30,0xe4,0x08,0x90,0x01,0xb9,0x74,0x10,
++0xf0,0x80,0x1f,0x90,0x91,0x29,0xe0,0x60,0x08,0x90,0x01,0xb9,0x74,0x20,0xf0,0x80,
++0x11,0x90,0x91,0x31,0xe0,0x60,0x08,0x90,0x01,0xb9,0x74,0x80,0xf0,0x80,0x03,0x7f,
++0x01,0x22,0x90,0x01,0xb8,0x74,0x04,0xf0,0x7f,0x00,0x22,0x90,0x06,0x04,0xe0,0x54,
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++0x6e,0xf0,0x43,0x6e,0x0c,0x22,0x90,0x91,0x9d,0xef,0xf0,0x31,0x9f,0x90,0x91,0x9d,
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++0x90,0xd8,0x12,0x43,0x09,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x78,0x7e,0x08,0x12,
++0x2f,0xd9,0x90,0x90,0xdc,0x12,0x43,0x09,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x04,
++0x7e,0x0c,0x12,0x2f,0xd9,0x90,0x90,0xe0,0x12,0x43,0x09,0x90,0x80,0x85,0x12,0x2a,
++0x7f,0x7f,0x00,0x7e,0x08,0x12,0x2f,0xd9,0x90,0x90,0xe4,0x12,0x43,0x09,0x90,0x80,
++0x85,0x12,0x2a,0x7f,0x7f,0x70,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x80,0x59,0x12,0x2a,
++0x8b,0x00,0x03,0x2d,0x95,0xe4,0xfd,0xff,0x12,0x34,0x81,0x90,0x91,0x51,0xe0,0xb4,
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++0x12,0x34,0x81,0x22,0x8f,0x77,0xe4,0x90,0x91,0x96,0xf0,0xa3,0xf0,0x90,0x01,0x09,
++0xe0,0x7f,0x00,0x30,0xe7,0x02,0x7f,0x01,0xef,0x65,0x77,0x60,0x3e,0xc3,0x90,0x91,
++0x97,0xe0,0x94,0x88,0x90,0x91,0x96,0xe0,0x94,0x13,0x40,0x08,0x90,0x01,0xc6,0xe0,
++0x44,0x80,0xf0,0x22,0x90,0x91,0x96,0xe4,0x75,0xf0,0x01,0x12,0x42,0x81,0x7f,0x14,
++0x7e,0x00,0x12,0x37,0x54,0xd3,0x90,0x91,0x97,0xe0,0x94,0x32,0x90,0x91,0x96,0xe0,
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++0x78,0x12,0x47,0xe6,0xef,0x64,0x01,0x70,0x2e,0x90,0x91,0x44,0x12,0x48,0x1e,0xe5,
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++0x27,0xe0,0x70,0x07,0x90,0x91,0x39,0xe0,0xff,0x80,0x05,0x90,0x91,0x27,0xe0,0xff,
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++0x22,0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0xd0,0xd0,0x92,0xaf,0x22,0xe4,0xfb,
++0x90,0x91,0x78,0x12,0x2a,0x8b,0x00,0x00,0x00,0x00,0xe5,0x70,0x70,0x02,0x61,0xc0,
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++0x71,0x10,0xe4,0x90,0x91,0x66,0xf0,0x90,0x91,0x3a,0xe0,0x75,0xf0,0x05,0xa4,0xff,
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++0x78,0x60,0x05,0x74,0x0d,0xf0,0x80,0x03,0x74,0x09,0xf0,0x90,0x05,0x22,0xe4,0xf0,
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++0xe5,0x6e,0x54,0x0f,0xc3,0x94,0x04,0x50,0x07,0x7d,0x01,0x7f,0x04,0x12,0x47,0x27,
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++0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x60,0x7e,0x08,0x12,0x2f,0xd9,0x90,0x91,0x1f,
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++0x90,0x01,0xe6,0xf0,0xd0,0xd0,0x92,0xaf,0x22,0x90,0x00,0x02,0x12,0x42,0x20,0xff,
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++0x22,0x90,0x02,0x09,0xe0,0xfd,0x12,0x29,0xd9,0xfe,0xaf,0x05,0xed,0x2e,0x90,0x91,
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++0x42,0x20,0xff,0xed,0x2f,0x90,0x91,0x44,0xf0,0x90,0x00,0x04,0x12,0x42,0x20,0xff,
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++0x90,0x91,0x47,0xe0,0x90,0x91,0x1d,0xf0,0x90,0x91,0x48,0xe0,0xf5,0x19,0xa3,0xe0,
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++0x90,0x91,0x1d,0xe0,0x12,0x43,0x4a,0x66,0xe6,0x00,0x68,0x13,0x01,0x66,0xee,0x02,
++0x66,0xee,0x03,0x66,0xee,0x04,0x68,0x13,0x05,0x67,0xe3,0x80,0x67,0xf9,0x81,0x68,
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++0x91,0x1c,0xb4,0x03,0x05,0x74,0x02,0xf0,0x80,0x03,0x74,0x04,0xf0,0xc3,0xe5,0x19,
++0x94,0x08,0x50,0x4a,0xe4,0xf5,0x16,0x90,0x91,0x1c,0xe0,0xff,0xe5,0x16,0xc3,0x9f,
++0x40,0x03,0x02,0x68,0x13,0xc3,0xe5,0x19,0x94,0x01,0x50,0x14,0xe5,0x16,0x25,0x1a,
++0xff,0xc3,0x74,0x03,0x95,0x16,0x24,0x1b,0xf8,0xe6,0xfd,0x12,0x4d,0xa8,0x80,0x1a,
++0xc3,0x74,0x03,0x95,0x16,0x24,0x1b,0xf8,0xe6,0xff,0xe5,0x16,0x7c,0x00,0x25,0x1a,
++0xfd,0xec,0x35,0x19,0x8d,0x82,0xf5,0x83,0xef,0xf0,0x05,0x16,0x80,0xb9,0xc3,0xe5,
++0x19,0x94,0x10,0x40,0x03,0x02,0x68,0x13,0x90,0x91,0x1d,0xe0,0x64,0x04,0x60,0x03,
++0x02,0x68,0x13,0xaf,0x1c,0xfc,0xfd,0xfe,0x78,0x10,0x12,0x2a,0x6c,0xc0,0x04,0xc0,
++0x05,0xc0,0x06,0xc0,0x07,0xaf,0x1b,0xe4,0xfc,0xfd,0xfe,0x78,0x18,0x12,0x2a,0x6c,
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++0xec,0x54,0xf0,0xfc,0x90,0x91,0x88,0x12,0x2a,0x7f,0x90,0x91,0x88,0x12,0x43,0x09,
++0xed,0x44,0x10,0xfd,0xec,0x44,0x01,0xfc,0x90,0x91,0x88,0x12,0x2a,0x7f,0x90,0x91,
++0x88,0x12,0x43,0x09,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x0c,0x7e,0x09,0x12,0x2f,
++0xd9,0x7f,0x04,0x7e,0x08,0x12,0x27,0xde,0x90,0x91,0x88,0x12,0x2a,0x7f,0x90,0x91,
++0x88,0x12,0x43,0x09,0xef,0x54,0xf0,0xff,0xec,0x90,0x91,0x88,0x12,0x2a,0x7f,0x90,
++0x91,0x88,0x12,0x43,0x09,0xef,0x44,0x01,0xff,0xec,0x90,0x91,0x88,0x12,0x2a,0x7f,
++0x90,0x91,0x88,0x12,0x43,0x09,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x04,0x7e,0x08,
++0x12,0x2f,0xd9,0xe4,0x90,0x90,0xe8,0xf0,0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,
++0x90,0x91,0xa0,0xef,0xf0,0xd3,0x94,0x07,0x50,0x47,0xe0,0xff,0x74,0x01,0xa8,0x07,
++0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xf4,0xff,0x90,0x00,0x46,0xe0,0x5f,0xf0,0x12,
++0x4c,0xa0,0x90,0x91,0xa0,0xe0,0xfd,0x74,0x01,0x7e,0x00,0xa8,0x05,0x08,0x80,0x05,
++0xc3,0x33,0xce,0x33,0xce,0xd8,0xf9,0xff,0x90,0x00,0x44,0xe0,0xfb,0xe4,0xfe,0xef,
++0x5b,0xa8,0x05,0x08,0x80,0x06,0xce,0xa2,0xe7,0x13,0xce,0x13,0xd8,0xf8,0xff,0x80,
++0x44,0x90,0x91,0xa0,0xe0,0x24,0xf8,0xf0,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,
++0x02,0xc3,0x33,0xd8,0xfc,0x12,0x4c,0x98,0x90,0x91,0xa0,0xe0,0xfd,0x74,0x01,0x7e,
++0x00,0xa8,0x05,0x08,0x80,0x05,0xc3,0x33,0xce,0x33,0xce,0xd8,0xf9,0xff,0x90,0x00,
++0x42,0xe0,0xfb,0xe4,0xfe,0xef,0x5b,0xa8,0x05,0x08,0x80,0x06,0xce,0xa2,0xe7,0x13,
++0xce,0x13,0xd8,0xf8,0xff,0xd0,0xd0,0x92,0xaf,0x22,0xe4,0xfd,0x7f,0x45,0x12,0x4d,
++0xa8,0x90,0x04,0xfd,0xe4,0xf0,0xa3,0xf0,0x90,0x90,0xf7,0xf0,0x90,0x90,0xfd,0xf0,
++0x90,0x91,0x00,0xf0,0x90,0x90,0xfe,0xf0,0x90,0x91,0x01,0xf0,0x90,0x90,0xff,0xf0,
++0x90,0x91,0x02,0xf0,0x90,0x90,0xe9,0x04,0xf0,0xe4,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,
++0x90,0x90,0xee,0xf0,0x90,0x90,0xf3,0xf0,0x90,0x90,0xf5,0xf0,0x90,0x91,0x07,0xf0,
++0x90,0x90,0xf8,0xf0,0x90,0x90,0xf4,0xf0,0x90,0x90,0xed,0xf0,0x90,0x00,0x51,0xe0,
++0x44,0xc0,0xfd,0x7f,0x51,0x02,0x4d,0xa8,0x90,0x91,0x07,0xe0,0x64,0x01,0x60,0x08,
++0x90,0x90,0xf5,0xe0,0x60,0x02,0x01,0xdf,0x90,0x90,0xe9,0xe0,0xc3,0x94,0xff,0x50,
++0x05,0xe0,0x04,0xf0,0x80,0x3b,0x90,0x90,0xea,0xe0,0xc3,0x94,0xff,0x50,0x06,0xe0,
++0x04,0xf0,0xe4,0x80,0x28,0x90,0x90,0xeb,0xe0,0xc3,0x94,0xff,0x50,0x0a,0xe0,0x04,
++0xf0,0xe4,0x90,0x90,0xea,0xf0,0x80,0x15,0x90,0x90,0xec,0xe0,0xc3,0x94,0xff,0x50,
++0x10,0xe0,0x04,0xf0,0xe4,0x90,0x90,0xeb,0xf0,0x90,0x90,0xea,0xf0,0x90,0x90,0xe9,
++0xf0,0x90,0x00,0x44,0xe0,0x54,0x0c,0x60,0x76,0xe0,0x30,0xe2,0x32,0x90,0x90,0xfd,
++0xe0,0xc3,0x94,0xff,0x50,0x05,0xe0,0x04,0xf0,0x80,0x24,0x90,0x90,0xfe,0xe0,0xc3,
++0x94,0xff,0x50,0x06,0xe0,0x04,0xf0,0xe4,0x80,0x11,0x90,0x90,0xff,0xe0,0xc3,0x94,
++0xff,0x50,0x0c,0xe0,0x04,0xf0,0xe4,0x90,0x90,0xfe,0xf0,0x90,0x90,0xfd,0xf0,0x90,
++0x00,0x44,0xe0,0x30,0xe3,0x32,0x90,0x91,0x00,0xe0,0xc3,0x94,0xff,0x50,0x05,0xe0,
++0x04,0xf0,0x80,0x24,0x90,0x91,0x01,0xe0,0xc3,0x94,0xff,0x50,0x06,0xe0,0x04,0xf0,
++0xe4,0x80,0x11,0x90,0x91,0x02,0xe0,0xc3,0x94,0xff,0x50,0x0c,0xe0,0x04,0xf0,0xe4,
++0x90,0x91,0x01,0xf0,0x90,0x91,0x00,0xf0,0x90,0x04,0xfd,0xe0,0x44,0x01,0xf0,0x22,
++0xe5,0x6e,0x30,0xe3,0x04,0xe4,0xff,0x80,0x02,0x7f,0x01,0x02,0x47,0xc9,0x90,0x91,
++0x53,0xe0,0x30,0xe0,0x49,0xe5,0x6d,0x64,0x01,0x70,0x43,0x90,0x91,0x52,0xe0,0x04,
++0xf0,0xe5,0x70,0x64,0x03,0x60,0x05,0xe5,0x70,0xb4,0x06,0x0d,0x90,0x91,0x52,0xe0,
++0xff,0x74,0x01,0xd3,0x9f,0x50,0x14,0x80,0x07,0x90,0x91,0x52,0xe0,0xb4,0x0a,0x0b,
++0x90,0x91,0x55,0xe0,0x04,0xf0,0xe4,0x90,0x91,0x52,0xf0,0x90,0x91,0x55,0xe0,0xff,
++0x90,0x91,0x54,0xe0,0xb5,0x07,0x07,0x11,0xe0,0xe4,0x90,0x91,0x55,0xf0,0x22,0x90,
++0x06,0x90,0xe0,0x44,0x01,0xf0,0x90,0x91,0x61,0xe0,0x30,0xe0,0x3c,0x90,0x91,0x5f,
++0xe0,0xff,0x90,0x91,0x5e,0xe0,0xfe,0xc4,0x13,0x54,0x01,0xfd,0x12,0x4c,0xb0,0x90,
++0x91,0x60,0xe0,0x75,0xf0,0x20,0xa4,0xff,0xae,0xf0,0x12,0x37,0x54,0x90,0x91,0x5e,
++0xe0,0xc4,0x13,0x54,0x07,0x30,0xe0,0x07,0xa3,0xe0,0xff,0xe4,0xfd,0x80,0x07,0x90,
++0x91,0x5f,0xe0,0xff,0x7d,0x01,0x12,0x4c,0xb0,0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0,
++0xd0,0xe4,0x90,0x91,0x19,0xf0,0xa3,0x74,0x08,0xf0,0xa3,0xf0,0xe4,0xa3,0xf0,0x90,
++0x01,0x1f,0xe0,0xfe,0x90,0x01,0x1e,0xe0,0x7c,0x00,0x24,0x00,0xff,0xec,0x3e,0x90,
++0x91,0x11,0xf0,0xa3,0xef,0xf0,0x90,0x02,0x87,0xe0,0x90,0x91,0x18,0xf0,0x90,0x91,
++0x56,0xe0,0x20,0xe0,0x02,0x61,0xb7,0xe4,0x90,0x91,0x17,0xf0,0x90,0x91,0x18,0xe0,
++0xff,0x90,0x91,0x17,0xe0,0xc3,0x9f,0x40,0x02,0x61,0xb7,0x90,0x91,0x11,0xe0,0xfc,
++0xa3,0xe0,0xfd,0xec,0xff,0x90,0xfd,0x11,0xf0,0x90,0x91,0x1c,0xef,0xf0,0x74,0x02,
++0x2d,0xf5,0x82,0xe4,0x34,0xfb,0xf5,0x83,0xe0,0x54,0x0f,0xfc,0x33,0x33,0x33,0x54,
++0xf8,0xff,0xed,0x24,0x18,0x2f,0x90,0x91,0x15,0xf0,0xe0,0x24,0x00,0xf5,0x82,0xe4,
++0x34,0xfb,0xf5,0x83,0xe0,0x54,0xfc,0x90,0x91,0x16,0xf0,0x74,0x01,0x2d,0xf5,0x82,
++0xe4,0x34,0xfb,0xf5,0x83,0xe0,0xfe,0x74,0x00,0x2d,0xf5,0x82,0xe4,0x34,0xfb,0xf5,
++0x83,0xe0,0x7a,0x00,0x24,0x00,0xff,0xea,0x3e,0x54,0x3f,0xab,0x07,0xfa,0x90,0x91,
++0x13,0xf0,0xa3,0xeb,0xf0,0xaf,0x04,0xef,0x75,0xf0,0x08,0xa4,0x24,0x18,0xff,0xe4,
++0x35,0xf0,0xfe,0xef,0x2b,0xfb,0xee,0x3a,0xfa,0x90,0x91,0x5a,0xe0,0xfe,0xa3,0xe0,
++0xff,0xad,0x03,0xac,0x02,0x12,0x45,0x09,0xaa,0x06,0xab,0x07,0x90,0x91,0x15,0xe0,
++0x24,0x00,0xf5,0x82,0xe4,0x34,0xfb,0xf5,0x83,0xe0,0x30,0xe7,0x08,0x90,0x91,0x19,
++0x74,0x02,0xf0,0x80,0x05,0xe4,0x90,0x91,0x19,0xf0,0xaf,0x03,0x90,0x91,0x11,0xea,
++0x8f,0xf0,0x12,0x42,0x81,0x90,0x91,0x5c,0xe0,0xfe,0xa3,0xe0,0xff,0x90,0x91,0x11,
++0xe0,0xfc,0xa3,0xe0,0xfd,0xd3,0x9f,0xec,0x9e,0x40,0x1b,0x90,0x91,0x5d,0xe0,0x24,
++0x01,0xff,0x90,0x91,0x5c,0xe0,0x34,0x00,0xfe,0xc3,0xed,0x9f,0xff,0xec,0x9e,0x90,
++0x91,0x11,0xf0,0xa3,0xef,0xf0,0x90,0x91,0x16,0xe0,0xff,0x24,0x40,0x60,0x04,0x24,
++0x20,0x70,0x27,0x90,0x91,0x5e,0xe0,0xfe,0xc4,0x13,0x13,0x13,0x54,0x01,0x20,0xe0,
++0x02,0x61,0x8f,0xef,0x90,0x00,0x81,0xb4,0xa0,0x05,0xe0,0x44,0x04,0x80,0x03,0xe0,
++0x44,0x08,0xfd,0x7f,0x81,0x12,0x4d,0xa8,0x61,0x88,0x90,0x91,0x5e,0xe0,0xc4,0x13,
++0x13,0x54,0x03,0x20,0xe0,0x02,0x61,0x8f,0x90,0x91,0x15,0xe0,0xff,0x24,0x00,0xf5,
++0x82,0xe4,0x34,0xfb,0xf5,0x83,0xe0,0x54,0x0c,0x64,0x08,0x70,0x72,0x90,0x91,0x19,
++0xe0,0xfe,0xef,0x2e,0xff,0xa3,0xe0,0x2f,0xff,0x24,0x1e,0xf5,0x82,0xe4,0x34,0xfb,
++0xf5,0x83,0xe0,0x64,0x88,0x70,0x58,0x74,0x1f,0x2f,0xf5,0x82,0xe4,0x34,0xfb,0xf5,
++0x83,0xe0,0x64,0x8e,0x70,0x49,0x90,0x91,0x19,0xe0,0xff,0x90,0x91,0x15,0xe0,0x2f,
++0xff,0x90,0x91,0x1a,0xe0,0x2f,0xff,0xa3,0xe0,0x2f,0xff,0x24,0x19,0xf5,0x82,0xe4,
++0x34,0xfb,0xf5,0x83,0xe0,0x64,0x03,0x70,0x26,0x74,0x1e,0x2f,0xf5,0x82,0xe4,0x34,
++0xfb,0xf5,0x83,0xe0,0x90,0x00,0x81,0x30,0xe3,0x05,0xe0,0x44,0x01,0x80,0x03,0xe0,
++0x44,0x02,0xfd,0x7f,0x81,0x12,0x4d,0xa8,0x90,0x91,0x56,0xe0,0x44,0x80,0xf0,0x90,
++0x91,0x56,0xe0,0xff,0xc4,0x13,0x13,0x13,0x54,0x01,0x30,0xe0,0x02,0x31,0x3f,0x71,
++0xbc,0xbf,0x01,0x13,0x90,0x91,0x11,0xe0,0xfe,0xa3,0xe0,0xff,0x12,0x44,0xb5,0x90,
++0x91,0x17,0xe0,0x04,0xf0,0x21,0xcc,0xd0,0xd0,0x92,0xaf,0x22,0x90,0x91,0x56,0xe0,
++0xc4,0x13,0x13,0x13,0x54,0x01,0x30,0xe0,0x11,0xe0,0x44,0x80,0xf0,0x90,0x91,0x5e,
++0xe0,0xc4,0x54,0x0f,0x20,0xe0,0x03,0x7f,0x00,0x22,0x7f,0x01,0x22,0x8f,0x1f,0xe4,
++0x90,0x91,0x22,0xf0,0xe5,0x1f,0x14,0xfe,0x90,0x91,0x22,0xe0,0xff,0xc3,0x9e,0x50,
++0x0e,0xef,0x04,0xfd,0x12,0x34,0xb7,0x90,0x91,0x22,0xe0,0x04,0xf0,0x80,0xe5,0xe5,
++0x1f,0x14,0xff,0x7d,0xff,0x12,0x34,0xb7,0x90,0x91,0x22,0xe5,0x1f,0xf0,0x90,0x91,
++0x22,0xe0,0xc3,0x94,0xff,0x50,0x0f,0xe0,0xff,0x04,0xfd,0x12,0x34,0xb7,0x90,0x91,
++0x22,0xe0,0x04,0xf0,0x80,0xe8,0xad,0x1f,0x7f,0xff,0x02,0x34,0xb7,0xc3,0xee,0x94,
++0x01,0x40,0x0a,0x0d,0xed,0x13,0x90,0xfd,0x10,0xf0,0xe4,0x2f,0xff,0x22,0xc3,0xee,
++0x94,0x01,0x40,0x1e,0x90,0xfd,0x11,0xe0,0xb5,0x05,0x14,0x90,0x01,0x17,0xe0,0xb5,
++0x05,0x07,0x90,0xfd,0x11,0xe4,0xf0,0x80,0x06,0xed,0x04,0x90,0xfd,0x11,0xf0,0xe4,
++0x2f,0xff,0x22,0x00,0x18,0x58,};
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/hal/rtl8192c/usb/rtl8192cu_led.c linux-xbian-rpi/drivers/net/wireless/rtl8192cu/hal/rtl8192c/usb/rtl8192cu_led.c
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/hal/rtl8192c/usb/rtl8192cu_led.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/hal/rtl8192c/usb/rtl8192cu_led.c 2015-07-28 01:20:58.313625760 +0200
+@@ -0,0 +1,2674 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++
++#include "drv_types.h"
++#include "rtl8192c_hal.h"
++
++//================================================================================
++// Constant.
++//================================================================================
++
++//
++// Default LED behavior.
++//
++#define LED_BLINK_NORMAL_INTERVAL 100
++#define LED_BLINK_SLOWLY_INTERVAL 200
++#define LED_BLINK_LONG_INTERVAL 400
++
++#define LED_BLINK_NO_LINK_INTERVAL_ALPHA 1000
++#define LED_BLINK_LINK_INTERVAL_ALPHA 500 //500
++#define LED_BLINK_SCAN_INTERVAL_ALPHA 180 //150
++#define LED_BLINK_FASTER_INTERVAL_ALPHA 50
++#define LED_BLINK_WPS_SUCESS_INTERVAL_ALPHA 5000
++
++//================================================================================
++// LED object.
++//================================================================================
++
++
++//================================================================================
++// Prototype of protected function.
++//================================================================================
++
++
++static void
++BlinkTimerCallback(
++ unsigned long data
++ );
++
++static void
++BlinkWorkItemCallback(
++ struct work_struct *work
++ );
++
++//
++// Description:
++// Reset blinking status of LED_871x object.
++//
++static void
++ResetLedStatus(PLED_871x pLed) {
++ pLed->CurrLedState = RTW_LED_OFF; // Current LED state.
++ pLed->bLedOn = _FALSE; // true if LED is ON, false if LED is OFF.
++
++ pLed->bLedBlinkInProgress = _FALSE; // true if it is blinking, false o.w..
++ pLed->bLedNoLinkBlinkInProgress = _FALSE;
++ pLed->bLedLinkBlinkInProgress = _FALSE;
++ pLed->bLedStartToLinkBlinkInProgress = _FALSE;
++ pLed->bLedScanBlinkInProgress = _FALSE;
++ pLed->bLedWPSBlinkInProgress = _FALSE;
++ pLed->BlinkTimes = 0; // Number of times to toggle led state for blinking.
++ pLed->BlinkingLedState = LED_UNKNOWN; // Next state for blinking, either RTW_LED_ON or RTW_LED_OFF are.
++}
++
++//================================================================================
++// LED_819xUsb routines.
++//================================================================================
++
++//
++// Description:
++// Initialize an LED_871x object.
++//
++static void
++InitLed871x(
++ _adapter *padapter,
++ PLED_871x pLed,
++ LED_PIN_871x LedPin
++ )
++{
++ pLed->padapter = padapter;
++ pLed->LedPin = LedPin;
++
++ ResetLedStatus(pLed);
++
++ _init_timer(&(pLed->BlinkTimer), padapter->pnetdev, BlinkTimerCallback, pLed);
++ _init_workitem(&(pLed->BlinkWorkItem), BlinkWorkItemCallback, pLed);
++}
++
++
++//
++// Description:
++// DeInitialize an LED_871x object.
++//
++static void
++DeInitLed871x(
++ PLED_871x pLed
++ )
++{
++ //call _cancel_workitem_sync(&(pLed->BlinkWorkItem))
++ //before _cancel_timer_ex(&(pLed->BlinkTimer)) to
++ //avoid led timer restarting when driver is removed
++
++ _cancel_workitem_sync(&(pLed->BlinkWorkItem));
++
++ _cancel_timer_ex(&(pLed->BlinkTimer));
++
++ // We should reset bLedBlinkInProgress if we cancel the LedControlTimer, 2005.03.10, by rcnjko.
++ ResetLedStatus(pLed);
++}
++
++//
++// Description:
++// Turn on LED according to LedPin specified.
++//
++static void
++SwLedOn(
++ _adapter *padapter,
++ PLED_871x pLed
++)
++{
++ u8 LedCfg;
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++
++ if( (padapter->bSurpriseRemoved == _TRUE) || ( padapter->bDriverStopped == _TRUE))
++ {
++ return;
++ }
++
++ if( (BOARD_MINICARD == pHalData->BoardType )||
++ (BOARD_USB_SOLO == pHalData->BoardType)||
++ (BOARD_USB_COMBO == pHalData->BoardType))
++ {
++ LedCfg = rtw_read8(padapter, REG_LEDCFG2);
++ switch(pLed->LedPin)
++ {
++ case LED_PIN_GPIO0:
++ break;
++
++ case LED_PIN_LED0:
++ rtw_write8(padapter, REG_LEDCFG2, (LedCfg&0xf0)|BIT5|BIT6); // SW control led0 on.
++ break;
++
++ case LED_PIN_LED1:
++ rtw_write8(padapter, REG_LEDCFG2, (LedCfg&0x0f)|BIT5); // SW control led1 on.
++ break;
++
++ default:
++ break;
++
++ }
++ }
++ else
++ {
++ switch(pLed->LedPin)
++ {
++ case LED_PIN_GPIO0:
++ break;
++
++ case LED_PIN_LED0:
++#ifdef CONFIG_SW_ANTENNA_DIVERSITY
++ if(pHalData->AntDivCfg)
++ {
++ LedCfg = rtw_read8(padapter, REG_LEDCFG2);
++ rtw_write8(padapter, REG_LEDCFG2, (LedCfg&0xe0)|BIT7|BIT6|BIT5); // SW control led0 on.
++ //RT_TRACE(COMP_LED, DBG_LOUD, ("SwLedOn LED0 0x%x\n", PlatformEFIORead4Byte(Adapter, REG_LEDCFG2)));
++ }
++ else
++#endif
++ {
++ LedCfg = rtw_read8(padapter, REG_LEDCFG0);
++ rtw_write8(padapter,REG_LEDCFG0, LedCfg&0x70); // SW control led0 on.
++ //RT_TRACE(COMP_LED, DBG_LOUD, ("SwLedOn LED0 0x%lx\n", PlatformEFIORead4Byte(Adapter, REG_LEDCFG0)));
++ }
++ break;
++
++ case LED_PIN_LED1:
++ LedCfg = rtw_read8(padapter,(REG_LEDCFG1));
++ rtw_write8(padapter,(REG_LEDCFG1), LedCfg&0x70); // SW control led1 on.
++ //RT_TRACE(COMP_LED, DBG_LOUD, ("SwLedOn LED1 0x%lx\n", PlatformEFIORead4Byte(Adapter, REG_LEDCFG0)));
++
++ break;
++
++ default:
++ break;
++ }
++ }
++ pLed->bLedOn = _TRUE;
++
++}
++
++
++//
++// Description:
++// Turn off LED according to LedPin specified.
++//
++static void
++SwLedOff(
++ _adapter *padapter,
++ PLED_871x pLed
++)
++{
++ u8 LedCfg;
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++
++ if((padapter->bSurpriseRemoved == _TRUE) || ( padapter->bDriverStopped == _TRUE))
++ {
++ goto exit;
++ }
++
++ if( (BOARD_MINICARD == pHalData->BoardType )||
++ (BOARD_USB_SOLO == pHalData->BoardType)||
++ (BOARD_USB_COMBO == pHalData->BoardType))
++ {
++ LedCfg = rtw_read8(padapter, REG_LEDCFG2);//0x4E
++
++ switch(pLed->LedPin)
++ {
++
++ case LED_PIN_GPIO0:
++ break;
++
++ case LED_PIN_LED0:
++ if(BOARD_USB_COMBO == pHalData->BoardType)
++ {
++ LedCfg &= 0x90; // Set to software control.
++ rtw_write8(padapter, REG_LEDCFG2, (LedCfg|BIT3));
++ LedCfg = rtw_read8(padapter, REG_MAC_PINMUX_CFG);
++ LedCfg &= 0xFE;
++ rtw_write8(padapter, REG_MAC_PINMUX_CFG, LedCfg);
++ }
++ else
++ {
++ LedCfg &= 0xf0; // Set to software control.
++ if(pHalData->bLedOpenDrain == _TRUE) // Open-drain arrangement for controlling the LED
++ rtw_write8(padapter, REG_LEDCFG2, (LedCfg|BIT1|BIT5|BIT6));
++ else
++ rtw_write8(padapter, REG_LEDCFG2, (LedCfg|BIT3|BIT5|BIT6));
++ }
++ break;
++
++ case LED_PIN_LED1:
++ LedCfg &= 0x0f; // Set to software control.
++ rtw_write8(padapter, REG_LEDCFG2, (LedCfg|BIT3));
++ break;
++
++ default:
++ break;
++ }
++ }
++ else
++ {
++ switch(pLed->LedPin)
++ {
++ case LED_PIN_GPIO0:
++ break;
++
++ case LED_PIN_LED0:
++#ifdef CONFIG_SW_ANTENNA_DIVERSITY
++ if(pHalData->AntDivCfg)
++ {
++ LedCfg = rtw_read8(padapter, REG_LEDCFG2);
++ LedCfg &= 0xe0; // Set to software control.
++ rtw_write8(padapter, REG_LEDCFG2, (LedCfg|BIT3|BIT7|BIT6|BIT5));
++ //RT_TRACE(COMP_LED, DBG_LOUD, ("SwLedOff LED0 0x%x\n", PlatformEFIORead4Byte(Adapter, REG_LEDCFG2)));
++ }
++ else
++#endif
++ {
++ LedCfg = rtw_read8(padapter, REG_LEDCFG0);
++ LedCfg &= 0x70; // Set to software control.
++ rtw_write8(padapter, REG_LEDCFG0, (LedCfg|BIT3));
++ //RT_TRACE(COMP_LED, DBG_LOUD, ("SwLedOff LED0 0x%lx\n", PlatformEFIORead4Byte(Adapter, REG_LEDCFG0)));
++ }
++ break;
++
++ case LED_PIN_LED1:
++ LedCfg = rtw_read8(padapter, (REG_LEDCFG1));
++ LedCfg &= 0x70; // Set to software control.
++ rtw_write8(padapter, (REG_LEDCFG1), (LedCfg|BIT3));
++ //RT_TRACE(COMP_LED, DBG_LOUD, ("SwLedOff LED1 0x%lx\n", PlatformEFIORead4Byte(Adapter, REG_LEDCFG0)));
++ break;
++
++ default:
++ break;
++ }
++ }
++
++exit:
++ pLed->bLedOn = _FALSE;
++
++}
++
++//================================================================================
++// Interface to manipulate LED objects.
++//================================================================================
++
++
++//
++// Description:
++// Implementation of LED blinking behavior.
++// It toggle off LED and schedule corresponding timer if necessary.
++//
++static void
++SwLedBlink(
++ PLED_871x pLed
++ )
++{
++ _adapter *padapter = pLed->padapter;
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ u8 bStopBlinking = _FALSE;
++
++ // Change LED according to BlinkingLedState specified.
++ if( pLed->BlinkingLedState == RTW_LED_ON )
++ {
++ SwLedOn(padapter, pLed);
++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (%d): turn on\n", pLed->BlinkTimes));
++ }
++ else
++ {
++ SwLedOff(padapter, pLed);
++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,( "Blinktimes (%d): turn off\n", pLed->BlinkTimes));
++ }
++
++ // Determine if we shall change LED state again.
++ pLed->BlinkTimes--;
++ switch(pLed->CurrLedState)
++ {
++
++ case LED_BLINK_NORMAL:
++ if(pLed->BlinkTimes == 0)
++ {
++ bStopBlinking = _TRUE;
++ }
++ break;
++
++ case LED_BLINK_StartToBlink:
++ if( check_fwstate(pmlmepriv, _FW_LINKED) && check_fwstate(pmlmepriv, WIFI_STATION_STATE) )
++ {
++ bStopBlinking = _TRUE;
++ }
++ if( check_fwstate(pmlmepriv, _FW_LINKED) &&
++ (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)) )
++ {
++ bStopBlinking = _TRUE;
++ }
++ else if(pLed->BlinkTimes == 0)
++ {
++ bStopBlinking = _TRUE;
++ }
++ break;
++
++ case LED_BLINK_WPS:
++ if( pLed->BlinkTimes == 0 )
++ {
++ bStopBlinking = _TRUE;
++ }
++ break;
++
++
++ default:
++ bStopBlinking = _TRUE;
++ break;
++
++ }
++
++ if(bStopBlinking)
++ {
++ //if( padapter->pwrctrlpriv.cpwm >= PS_STATE_S2)
++ if(0)
++ {
++ SwLedOff(padapter, pLed);
++ }
++ else if( (check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE) && (pLed->bLedOn == _FALSE))
++ {
++ SwLedOn(padapter, pLed);
++ }
++ else if( (check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE) && pLed->bLedOn == _TRUE)
++ {
++ SwLedOff(padapter, pLed);
++ }
++
++ pLed->BlinkTimes = 0;
++ pLed->bLedBlinkInProgress = _FALSE;
++ }
++ else
++ {
++ // Assign LED state to toggle.
++ if( pLed->BlinkingLedState == RTW_LED_ON )
++ pLed->BlinkingLedState = RTW_LED_OFF;
++ else
++ pLed->BlinkingLedState = RTW_LED_ON;
++
++ // Schedule a timer to toggle LED state.
++ switch( pLed->CurrLedState )
++ {
++ case LED_BLINK_NORMAL:
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL);
++ break;
++
++ case LED_BLINK_SLOWLY:
++ case LED_BLINK_StartToBlink:
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL);
++ break;
++
++ case LED_BLINK_WPS:
++ {
++ if( pLed->BlinkingLedState == RTW_LED_ON )
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_LONG_INTERVAL);
++ else
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_LONG_INTERVAL);
++ }
++ break;
++
++ default:
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL);
++ break;
++ }
++ }
++}
++
++
++static void
++SwLedBlink1(
++ PLED_871x pLed
++ )
++{
++ _adapter *padapter = pLed->padapter;
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++ struct led_priv *ledpriv = &(padapter->ledpriv);
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ PLED_871x pLed1 = &(ledpriv->SwLed1);
++ u8 bStopBlinking = _FALSE;
++
++ if(pHalData->EEPROMCustomerID == RT_CID_819x_CAMEO)
++ pLed = &(ledpriv->SwLed1);
++
++ // Change LED according to BlinkingLedState specified.
++ if( pLed->BlinkingLedState == RTW_LED_ON )
++ {
++ SwLedOn(padapter, pLed);
++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,( "Blinktimes (%d): turn on\n", pLed->BlinkTimes));
++ }
++ else
++ {
++ SwLedOff(padapter, pLed);
++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (%d): turn off\n", pLed->BlinkTimes));
++ }
++
++
++ if(pHalData->EEPROMCustomerID == RT_CID_DEFAULT)
++ {
++ if(check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE)
++ {
++ if(!pLed1->bSWLedCtrl)
++ {
++ SwLedOn(padapter, pLed1);
++ pLed1->bSWLedCtrl = _TRUE;
++ }
++ else if(!pLed1->bLedOn)
++ SwLedOn(padapter, pLed1);
++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (): turn on pLed1\n"));
++ }
++ else
++ {
++ if(!pLed1->bSWLedCtrl)
++ {
++ SwLedOff(padapter, pLed1);
++ pLed1->bSWLedCtrl = _TRUE;
++ }
++ else if(pLed1->bLedOn)
++ SwLedOff(padapter, pLed1);
++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (): turn off pLed1\n"));
++ }
++ }
++
++
++ if( padapter->pwrctrlpriv.rf_pwrstate != rf_on )
++ {
++ SwLedOff(padapter, pLed);
++ ResetLedStatus(pLed);
++ return;
++ }
++
++
++ switch(pLed->CurrLedState)
++ {
++ case LED_BLINK_SLOWLY:
++ if( pLed->bLedOn )
++ pLed->BlinkingLedState = RTW_LED_OFF;
++ else
++ pLed->BlinkingLedState = RTW_LED_ON;
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA);
++ break;
++
++ case LED_BLINK_NORMAL:
++ if( pLed->bLedOn )
++ pLed->BlinkingLedState = RTW_LED_OFF;
++ else
++ pLed->BlinkingLedState = RTW_LED_ON;
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_LINK_INTERVAL_ALPHA);
++ break;
++
++ case LED_SCAN_BLINK:
++ pLed->BlinkTimes--;
++ if( pLed->BlinkTimes == 0 )
++ {
++ bStopBlinking = _TRUE;
++ }
++
++ if(bStopBlinking)
++ {
++ if(check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE)
++ {
++ pLed->bLedLinkBlinkInProgress = _TRUE;
++ pLed->CurrLedState = LED_BLINK_NORMAL;
++ if( pLed->bLedOn )
++ pLed->BlinkingLedState = RTW_LED_OFF;
++ else
++ pLed->BlinkingLedState = RTW_LED_ON;
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_LINK_INTERVAL_ALPHA);
++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("CurrLedState %d\n", pLed->CurrLedState));
++
++ }
++ else if(check_fwstate(pmlmepriv, _FW_LINKED)== _FALSE)
++ {
++ pLed->bLedNoLinkBlinkInProgress = _TRUE;
++ pLed->CurrLedState = LED_BLINK_SLOWLY;
++ if( pLed->bLedOn )
++ pLed->BlinkingLedState = RTW_LED_OFF;
++ else
++ pLed->BlinkingLedState = RTW_LED_ON;
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA);
++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("CurrLedState %d\n", pLed->CurrLedState));
++ }
++ pLed->bLedScanBlinkInProgress = _FALSE;
++ }
++ else
++ {
++ if( pLed->bLedOn )
++ pLed->BlinkingLedState = RTW_LED_OFF;
++ else
++ pLed->BlinkingLedState = RTW_LED_ON;
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA);
++ }
++ break;
++
++ case LED_TXRX_BLINK:
++ pLed->BlinkTimes--;
++ if( pLed->BlinkTimes == 0 )
++ {
++ bStopBlinking = _TRUE;
++ }
++ if(bStopBlinking)
++ {
++ if(check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE)
++ {
++ pLed->bLedLinkBlinkInProgress = _TRUE;
++ pLed->CurrLedState = LED_BLINK_NORMAL;
++ if( pLed->bLedOn )
++ pLed->BlinkingLedState = RTW_LED_OFF;
++ else
++ pLed->BlinkingLedState = RTW_LED_ON;
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_LINK_INTERVAL_ALPHA);
++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("CurrLedState %d\n", pLed->CurrLedState));
++ }
++ else if(check_fwstate(pmlmepriv, _FW_LINKED)== _FALSE)
++ {
++ pLed->bLedNoLinkBlinkInProgress = _TRUE;
++ pLed->CurrLedState = LED_BLINK_SLOWLY;
++ if( pLed->bLedOn )
++ pLed->BlinkingLedState = RTW_LED_OFF;
++ else
++ pLed->BlinkingLedState = RTW_LED_ON;
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA);
++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("CurrLedState %d\n", pLed->CurrLedState));
++ }
++ pLed->BlinkTimes = 0;
++ pLed->bLedBlinkInProgress = _FALSE;
++ }
++ else
++ {
++ if( pLed->bLedOn )
++ pLed->BlinkingLedState = RTW_LED_OFF;
++ else
++ pLed->BlinkingLedState = RTW_LED_ON;
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA);
++ }
++ break;
++
++ case LED_BLINK_WPS:
++ if( pLed->bLedOn )
++ pLed->BlinkingLedState = RTW_LED_OFF;
++ else
++ pLed->BlinkingLedState = RTW_LED_ON;
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA);
++ break;
++
++ case LED_BLINK_WPS_STOP: //WPS success
++ if(pLed->BlinkingLedState == RTW_LED_ON)
++ bStopBlinking = _FALSE;
++ else
++ bStopBlinking = _TRUE;
++
++ if(bStopBlinking)
++ {
++ pLed->bLedLinkBlinkInProgress = _TRUE;
++ pLed->CurrLedState = LED_BLINK_NORMAL;
++ if( pLed->bLedOn )
++ pLed->BlinkingLedState = RTW_LED_OFF;
++ else
++ pLed->BlinkingLedState = RTW_LED_ON;
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_LINK_INTERVAL_ALPHA);
++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("CurrLedState %d\n", pLed->CurrLedState));
++
++ pLed->bLedWPSBlinkInProgress = _FALSE;
++ }
++ else
++ {
++ pLed->BlinkingLedState = RTW_LED_OFF;
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_WPS_SUCESS_INTERVAL_ALPHA);
++ }
++ break;
++
++ default:
++ break;
++ }
++
++}
++
++static void
++SwLedBlink2(
++ PLED_871x pLed
++ )
++{
++ _adapter *padapter = pLed->padapter;
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ u8 bStopBlinking = _FALSE;
++
++ // Change LED according to BlinkingLedState specified.
++ if( pLed->BlinkingLedState == RTW_LED_ON)
++ {
++ SwLedOn(padapter, pLed);
++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (%d): turn on\n", pLed->BlinkTimes));
++ }
++ else
++ {
++ SwLedOff(padapter, pLed);
++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (%d): turn off\n", pLed->BlinkTimes));
++ }
++
++ switch(pLed->CurrLedState)
++ {
++ case LED_SCAN_BLINK:
++ pLed->BlinkTimes--;
++ if( pLed->BlinkTimes == 0 )
++ {
++ bStopBlinking = _TRUE;
++ }
++
++ if(bStopBlinking)
++ {
++ if( padapter->pwrctrlpriv.rf_pwrstate != rf_on )
++ {
++ SwLedOff(padapter, pLed);
++ }
++ else if(check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE)
++ {
++ pLed->CurrLedState = RTW_LED_ON;
++ pLed->BlinkingLedState = RTW_LED_ON;
++ SwLedOn(padapter, pLed);
++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("stop scan blink CurrLedState %d\n", pLed->CurrLedState));
++
++ }
++ else if(check_fwstate(pmlmepriv, _FW_LINKED)== _FALSE)
++ {
++ pLed->CurrLedState = RTW_LED_OFF;
++ pLed->BlinkingLedState = RTW_LED_OFF;
++ SwLedOff(padapter, pLed);
++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("stop scan blink CurrLedState %d\n", pLed->CurrLedState));
++ }
++ pLed->bLedScanBlinkInProgress = _FALSE;
++ }
++ else
++ {
++ if( padapter->pwrctrlpriv.rf_pwrstate != rf_on )
++ {
++ SwLedOff(padapter, pLed);
++ }
++ else
++ {
++ if( pLed->bLedOn )
++ pLed->BlinkingLedState = RTW_LED_OFF;
++ else
++ pLed->BlinkingLedState = RTW_LED_ON;
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA);
++ }
++ }
++ break;
++
++ case LED_TXRX_BLINK:
++ pLed->BlinkTimes--;
++ if( pLed->BlinkTimes == 0 )
++ {
++ bStopBlinking = _TRUE;
++ }
++ if(bStopBlinking)
++ {
++ if( padapter->pwrctrlpriv.rf_pwrstate != rf_on )
++ {
++ SwLedOff(padapter, pLed);
++ }
++ else if(check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE)
++ {
++ pLed->CurrLedState = RTW_LED_ON;
++ pLed->BlinkingLedState = RTW_LED_ON;
++ SwLedOn(padapter, pLed);
++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("stop CurrLedState %d\n", pLed->CurrLedState));
++
++ }
++ else if(check_fwstate(pmlmepriv, _FW_LINKED)== _FALSE)
++ {
++ pLed->CurrLedState = RTW_LED_OFF;
++ pLed->BlinkingLedState = RTW_LED_OFF;
++ SwLedOff(padapter, pLed);
++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("stop CurrLedState %d\n", pLed->CurrLedState));
++ }
++ pLed->bLedBlinkInProgress = _FALSE;
++ }
++ else
++ {
++ if( padapter->pwrctrlpriv.rf_pwrstate != rf_on )
++ {
++ SwLedOff(padapter, pLed);
++ }
++ else
++ {
++ if( pLed->bLedOn )
++ pLed->BlinkingLedState = RTW_LED_OFF;
++ else
++ pLed->BlinkingLedState = RTW_LED_ON;
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA);
++ }
++ }
++ break;
++
++ default:
++ break;
++ }
++
++}
++
++static void
++SwLedBlink3(
++ PLED_871x pLed
++ )
++{
++ _adapter *padapter = pLed->padapter;
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ u8 bStopBlinking = _FALSE;
++
++ // Change LED according to BlinkingLedState specified.
++ if( pLed->BlinkingLedState == RTW_LED_ON )
++ {
++ SwLedOn(padapter, pLed);
++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (%d): turn on\n", pLed->BlinkTimes));
++ }
++ else
++ {
++ if(pLed->CurrLedState != LED_BLINK_WPS_STOP)
++ SwLedOff(padapter, pLed);
++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (%d): turn off\n", pLed->BlinkTimes));
++ }
++
++ switch(pLed->CurrLedState)
++ {
++ case LED_SCAN_BLINK:
++ pLed->BlinkTimes--;
++ if( pLed->BlinkTimes == 0 )
++ {
++ bStopBlinking = _TRUE;
++ }
++
++ if(bStopBlinking)
++ {
++ if( padapter->pwrctrlpriv.rf_pwrstate != rf_on )
++ {
++ SwLedOff(padapter, pLed);
++ }
++ else if(check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE)
++ {
++ pLed->CurrLedState = RTW_LED_ON;
++ pLed->BlinkingLedState = RTW_LED_ON;
++ if( !pLed->bLedOn )
++ SwLedOn(padapter, pLed);
++
++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("CurrLedState %d\n", pLed->CurrLedState));
++ }
++ else if(check_fwstate(pmlmepriv, _FW_LINKED)== _FALSE)
++ {
++ pLed->CurrLedState = RTW_LED_OFF;
++ pLed->BlinkingLedState = RTW_LED_OFF;
++ if( pLed->bLedOn )
++ SwLedOff(padapter, pLed);
++
++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("CurrLedState %d\n", pLed->CurrLedState));
++ }
++ pLed->bLedScanBlinkInProgress = _FALSE;
++ }
++ else
++ {
++ if( padapter->pwrctrlpriv.rf_pwrstate != rf_on )
++ {
++ SwLedOff(padapter, pLed);
++ }
++ else
++ {
++ if( pLed->bLedOn )
++ pLed->BlinkingLedState = RTW_LED_OFF;
++ else
++ pLed->BlinkingLedState = RTW_LED_ON;
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA);
++ }
++ }
++ break;
++
++ case LED_TXRX_BLINK:
++ pLed->BlinkTimes--;
++ if( pLed->BlinkTimes == 0 )
++ {
++ bStopBlinking = _TRUE;
++ }
++ if(bStopBlinking)
++ {
++ if( padapter->pwrctrlpriv.rf_pwrstate != rf_on )
++ {
++ SwLedOff(padapter, pLed);
++ }
++ else if(check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE)
++ {
++ pLed->CurrLedState = RTW_LED_ON;
++ pLed->BlinkingLedState = RTW_LED_ON;
++
++ if( !pLed->bLedOn )
++ SwLedOn(padapter, pLed);
++
++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("CurrLedState %d\n", pLed->CurrLedState));
++ }
++ else if(check_fwstate(pmlmepriv, _FW_LINKED)== _FALSE)
++ {
++ pLed->CurrLedState = RTW_LED_OFF;
++ pLed->BlinkingLedState = RTW_LED_OFF;
++
++ if( pLed->bLedOn )
++ SwLedOff(padapter, pLed);
++
++
++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("CurrLedState %d\n", pLed->CurrLedState));
++ }
++ pLed->bLedBlinkInProgress = _FALSE;
++ }
++ else
++ {
++ if( padapter->pwrctrlpriv.rf_pwrstate != rf_on )
++ {
++ SwLedOff(padapter, pLed);
++ }
++ else
++ {
++ if( pLed->bLedOn )
++ pLed->BlinkingLedState = RTW_LED_OFF;
++ else
++ pLed->BlinkingLedState = RTW_LED_ON;
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA);
++ }
++ }
++ break;
++
++ case LED_BLINK_WPS:
++ if( pLed->bLedOn )
++ pLed->BlinkingLedState = RTW_LED_OFF;
++ else
++ pLed->BlinkingLedState = RTW_LED_ON;
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA);
++ break;
++
++ case LED_BLINK_WPS_STOP: //WPS success
++ if(pLed->BlinkingLedState == RTW_LED_ON)
++ {
++ pLed->BlinkingLedState = RTW_LED_OFF;
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_WPS_SUCESS_INTERVAL_ALPHA);
++ bStopBlinking = _FALSE;
++ }
++ else
++ {
++ bStopBlinking = _TRUE;
++ }
++
++ if(bStopBlinking)
++ {
++ if( padapter->pwrctrlpriv.rf_pwrstate != rf_on )
++ {
++ SwLedOff(padapter, pLed);
++ }
++ else
++ {
++ pLed->CurrLedState = RTW_LED_ON;
++ pLed->BlinkingLedState = RTW_LED_ON;
++ SwLedOn(padapter, pLed);
++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("CurrLedState %d\n", pLed->CurrLedState));
++ }
++ pLed->bLedWPSBlinkInProgress = _FALSE;
++ }
++ break;
++
++
++ default:
++ break;
++ }
++
++}
++
++
++static void
++SwLedBlink4(
++ PLED_871x pLed
++ )
++{
++ _adapter *padapter = pLed->padapter;
++ struct led_priv *ledpriv = &(padapter->ledpriv);
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ PLED_871x pLed1 = &(ledpriv->SwLed1);
++ u8 bStopBlinking = _FALSE;
++
++ // Change LED according to BlinkingLedState specified.
++ if( pLed->BlinkingLedState == RTW_LED_ON )
++ {
++ SwLedOn(padapter, pLed);
++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (%d): turn on\n", pLed->BlinkTimes));
++ }
++ else
++ {
++ SwLedOff(padapter, pLed);
++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (%d): turn off\n", pLed->BlinkTimes));
++ }
++
++ if(!pLed1->bLedWPSBlinkInProgress && pLed1->BlinkingLedState == LED_UNKNOWN)
++ {
++ pLed1->BlinkingLedState = RTW_LED_OFF;
++ pLed1->CurrLedState = RTW_LED_OFF;
++ SwLedOff(padapter, pLed1);
++ }
++
++ switch(pLed->CurrLedState)
++ {
++ case LED_BLINK_SLOWLY:
++ if( pLed->bLedOn )
++ pLed->BlinkingLedState = RTW_LED_OFF;
++ else
++ pLed->BlinkingLedState = RTW_LED_ON;
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA);
++ break;
++
++ case LED_BLINK_StartToBlink:
++ if( pLed->bLedOn )
++ {
++ pLed->BlinkingLedState = RTW_LED_OFF;
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL);
++ }
++ else
++ {
++ pLed->BlinkingLedState = RTW_LED_ON;
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL);
++ }
++ break;
++
++ case LED_SCAN_BLINK:
++ pLed->BlinkTimes--;
++ if( pLed->BlinkTimes == 0 )
++ {
++ bStopBlinking = _FALSE;
++ }
++
++ if(bStopBlinking)
++ {
++ if( padapter->pwrctrlpriv.rf_pwrstate != rf_on && padapter->pwrctrlpriv.rfoff_reason > RF_CHANGE_BY_PS)
++ {
++ SwLedOff(padapter, pLed);
++ }
++ else
++ {
++ pLed->bLedNoLinkBlinkInProgress = _FALSE;
++ pLed->CurrLedState = LED_BLINK_SLOWLY;
++ if( pLed->bLedOn )
++ pLed->BlinkingLedState = RTW_LED_OFF;
++ else
++ pLed->BlinkingLedState = RTW_LED_ON;
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA);
++ }
++ pLed->bLedScanBlinkInProgress = _FALSE;
++ }
++ else
++ {
++ if( padapter->pwrctrlpriv.rf_pwrstate != rf_on && padapter->pwrctrlpriv.rfoff_reason > RF_CHANGE_BY_PS)
++ {
++ SwLedOff(padapter, pLed);
++ }
++ else
++ {
++ if( pLed->bLedOn )
++ pLed->BlinkingLedState = RTW_LED_OFF;
++ else
++ pLed->BlinkingLedState = RTW_LED_ON;
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA);
++ }
++ }
++ break;
++
++ case LED_TXRX_BLINK:
++ pLed->BlinkTimes--;
++ if( pLed->BlinkTimes == 0 )
++ {
++ bStopBlinking = _TRUE;
++ }
++ if(bStopBlinking)
++ {
++ if( padapter->pwrctrlpriv.rf_pwrstate != rf_on && padapter->pwrctrlpriv.rfoff_reason > RF_CHANGE_BY_PS)
++ {
++ SwLedOff(padapter, pLed);
++ }
++ else
++ {
++ pLed->bLedNoLinkBlinkInProgress = _TRUE;
++ pLed->CurrLedState = LED_BLINK_SLOWLY;
++ if( pLed->bLedOn )
++ pLed->BlinkingLedState = RTW_LED_OFF;
++ else
++ pLed->BlinkingLedState = RTW_LED_ON;
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA);
++ }
++ pLed->bLedBlinkInProgress = _FALSE;
++ }
++ else
++ {
++ if( padapter->pwrctrlpriv.rf_pwrstate != rf_on && padapter->pwrctrlpriv.rfoff_reason > RF_CHANGE_BY_PS)
++ {
++ SwLedOff(padapter, pLed);
++ }
++ else
++ {
++ if( pLed->bLedOn )
++ pLed->BlinkingLedState = RTW_LED_OFF;
++ else
++ pLed->BlinkingLedState = RTW_LED_ON;
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA);
++ }
++ }
++ break;
++
++ case LED_BLINK_WPS:
++ if( pLed->bLedOn )
++ {
++ pLed->BlinkingLedState = RTW_LED_OFF;
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL);
++ }
++ else
++ {
++ pLed->BlinkingLedState = RTW_LED_ON;
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL);
++ }
++ break;
++
++ case LED_BLINK_WPS_STOP: //WPS authentication fail
++ if( pLed->bLedOn )
++ pLed->BlinkingLedState = RTW_LED_OFF;
++ else
++ pLed->BlinkingLedState = RTW_LED_ON;
++
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL);
++ break;
++
++ case LED_BLINK_WPS_STOP_OVERLAP: //WPS session overlap
++ pLed->BlinkTimes--;
++ if(pLed->BlinkTimes == 0)
++ {
++ if(pLed->bLedOn)
++ {
++ pLed->BlinkTimes = 1;
++ }
++ else
++ {
++ bStopBlinking = _TRUE;
++ }
++ }
++
++ if(bStopBlinking)
++ {
++ pLed->BlinkTimes = 10;
++ pLed->BlinkingLedState = RTW_LED_ON;
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_LINK_INTERVAL_ALPHA);
++ }
++ else
++ {
++ if( pLed->bLedOn )
++ pLed->BlinkingLedState = RTW_LED_OFF;
++ else
++ pLed->BlinkingLedState = RTW_LED_ON;
++
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL);
++ }
++ break;
++
++
++ default:
++ break;
++ }
++
++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("SwLedBlink4 CurrLedState %d\n", pLed->CurrLedState));
++
++
++}
++
++static void
++SwLedBlink5(
++ PLED_871x pLed
++ )
++{
++ _adapter *padapter = pLed->padapter;
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ u8 bStopBlinking = _FALSE;
++
++ // Change LED according to BlinkingLedState specified.
++ if( pLed->BlinkingLedState == RTW_LED_ON )
++ {
++ SwLedOn(padapter, pLed);
++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (%d): turn on\n", pLed->BlinkTimes));
++ }
++ else
++ {
++ SwLedOff(padapter, pLed);
++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (%d): turn off\n", pLed->BlinkTimes));
++ }
++
++ switch(pLed->CurrLedState)
++ {
++ case LED_SCAN_BLINK:
++ pLed->BlinkTimes--;
++ if( pLed->BlinkTimes == 0 )
++ {
++ bStopBlinking = _TRUE;
++ }
++
++ if(bStopBlinking)
++ {
++ if( padapter->pwrctrlpriv.rf_pwrstate != rf_on && padapter->pwrctrlpriv.rfoff_reason > RF_CHANGE_BY_PS)
++ {
++ pLed->CurrLedState = RTW_LED_OFF;
++ pLed->BlinkingLedState = RTW_LED_OFF;
++ if(pLed->bLedOn)
++ SwLedOff(padapter, pLed);
++ }
++ else
++ { pLed->CurrLedState = RTW_LED_ON;
++ pLed->BlinkingLedState = RTW_LED_ON;
++ if(!pLed->bLedOn)
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA);
++ }
++
++ pLed->bLedScanBlinkInProgress = _FALSE;
++ }
++ else
++ {
++ if( padapter->pwrctrlpriv.rf_pwrstate != rf_on && padapter->pwrctrlpriv.rfoff_reason > RF_CHANGE_BY_PS)
++ {
++ SwLedOff(padapter, pLed);
++ }
++ else
++ {
++ if( pLed->bLedOn )
++ pLed->BlinkingLedState = RTW_LED_OFF;
++ else
++ pLed->BlinkingLedState = RTW_LED_ON;
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA);
++ }
++ }
++ break;
++
++
++ case LED_TXRX_BLINK:
++ pLed->BlinkTimes--;
++ if( pLed->BlinkTimes == 0 )
++ {
++ bStopBlinking = _TRUE;
++ }
++
++ if(bStopBlinking)
++ {
++ if( padapter->pwrctrlpriv.rf_pwrstate != rf_on && padapter->pwrctrlpriv.rfoff_reason > RF_CHANGE_BY_PS)
++ {
++ pLed->CurrLedState = RTW_LED_OFF;
++ pLed->BlinkingLedState = RTW_LED_OFF;
++ if(pLed->bLedOn)
++ SwLedOff(padapter, pLed);
++ }
++ else
++ {
++ pLed->CurrLedState = RTW_LED_ON;
++ pLed->BlinkingLedState = RTW_LED_ON;
++ if(!pLed->bLedOn)
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA);
++ }
++
++ pLed->bLedBlinkInProgress = _FALSE;
++ }
++ else
++ {
++ if( padapter->pwrctrlpriv.rf_pwrstate != rf_on && padapter->pwrctrlpriv.rfoff_reason > RF_CHANGE_BY_PS)
++ {
++ SwLedOff(padapter, pLed);
++ }
++ else
++ {
++ if( pLed->bLedOn )
++ pLed->BlinkingLedState = RTW_LED_OFF;
++ else
++ pLed->BlinkingLedState = RTW_LED_ON;
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA);
++ }
++ }
++ break;
++
++ default:
++ break;
++ }
++
++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("SwLedBlink5 CurrLedState %d\n", pLed->CurrLedState));
++
++
++}
++
++static void
++SwLedBlink6(
++ PLED_871x pLed
++ )
++{
++ _adapter *padapter = pLed->padapter;
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ u8 bStopBlinking = _FALSE;
++
++ // Change LED according to BlinkingLedState specified.
++ if( pLed->BlinkingLedState == RTW_LED_ON )
++ {
++ SwLedOn(padapter, pLed);
++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (%d): turn on\n", pLed->BlinkTimes));
++ }
++ else
++ {
++ SwLedOff(padapter, pLed);
++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (%d): turn off\n", pLed->BlinkTimes));
++ }
++
++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("<==== blink6\n"));
++}
++
++
++//
++// Description:
++// Callback function of LED BlinkTimer,
++// it just schedules to corresponding BlinkWorkItem.
++//
++static void
++BlinkTimerCallback(
++ unsigned long data
++ )
++{
++ PLED_871x pLed = (PLED_871x)data;
++ _adapter *padapter = pLed->padapter;
++
++ //DBG_871X("%s\n", __FUNCTION__);
++
++ if( (padapter->bSurpriseRemoved == _TRUE) || ( padapter->bDriverStopped == _TRUE))
++ {
++ //DBG_871X("%s bSurpriseRemoved:%d, bDriverStopped:%d\n", __FUNCTION__, padapter->bSurpriseRemoved, padapter->bDriverStopped);
++ return;
++ }
++
++#ifdef CONFIG_LED_HANDLED_BY_CMD_THREAD
++ rtw_led_blink_cmd(padapter, pLed);
++#else
++ _set_workitem(&(pLed->BlinkWorkItem));
++#endif
++}
++
++//
++// Description:
++// Handler function of LED Blinking.
++// We dispatch acture LED blink action according to LedStrategy.
++//
++void BlinkHandler(PLED_871x pLed)
++{
++ struct led_priv *ledpriv = &(pLed->padapter->ledpriv);
++ _adapter *padapter = pLed->padapter;
++
++ //DBG_871X("%s (%s:%d)\n",__FUNCTION__, current->comm, current->pid);
++
++ if( (padapter->bSurpriseRemoved == _TRUE) || ( padapter->bDriverStopped == _TRUE))
++ {
++ //DBG_871X("%s bSurpriseRemoved:%d, bDriverStopped:%d\n", __FUNCTION__, padapter->bSurpriseRemoved, padapter->bDriverStopped);
++ return;
++ }
++
++ switch(ledpriv->LedStrategy)
++ {
++ case SW_LED_MODE0:
++ SwLedBlink(pLed);
++ break;
++
++ case SW_LED_MODE1:
++ SwLedBlink1(pLed);
++ break;
++
++ case SW_LED_MODE2:
++ SwLedBlink2(pLed);
++ break;
++
++ case SW_LED_MODE3:
++ SwLedBlink3(pLed);
++ break;
++
++ case SW_LED_MODE4:
++ SwLedBlink4(pLed);
++ break;
++
++ case SW_LED_MODE5:
++ SwLedBlink5(pLed);
++ break;
++
++ case SW_LED_MODE6:
++ SwLedBlink6(pLed);
++ break;
++
++ default:
++ //RT_TRACE(COMP_LED, DBG_LOUD, ("BlinkWorkItemCallback 0x%x \n", pHalData->LedStrategy));
++ //SwLedBlink(pLed);
++ break;
++ }
++}
++
++//
++// Description:
++// Callback function of LED BlinkWorkItem.
++// We dispatch acture LED blink action according to LedStrategy.
++//
++static void BlinkWorkItemCallback(struct work_struct *work)
++{
++ PLED_871x pLed = container_of(work, LED_871x, BlinkWorkItem);
++ BlinkHandler(pLed);
++}
++
++
++
++//================================================================================
++// Default LED behavior.
++//================================================================================
++
++//
++// Description:
++// Implement each led action for SW_LED_MODE0.
++// This is default strategy.
++//
++static void
++SwLedControlMode0(
++ _adapter *padapter,
++ LED_CTL_MODE LedAction
++)
++{
++ struct led_priv *ledpriv = &(padapter->ledpriv);
++ PLED_871x pLed = &(ledpriv->SwLed1);
++
++ // Decide led state
++ switch(LedAction)
++ {
++ case LED_CTL_TX:
++ case LED_CTL_RX:
++ if( pLed->bLedBlinkInProgress == _FALSE )
++ {
++ pLed->bLedBlinkInProgress = _TRUE;
++
++ pLed->CurrLedState = LED_BLINK_NORMAL;
++ pLed->BlinkTimes = 2;
++
++ if( pLed->bLedOn )
++ pLed->BlinkingLedState = RTW_LED_OFF;
++ else
++ pLed->BlinkingLedState = RTW_LED_ON;
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL);
++ }
++ break;
++
++ case LED_CTL_START_TO_LINK:
++ if( pLed->bLedBlinkInProgress == _FALSE )
++ {
++ pLed->bLedBlinkInProgress = _TRUE;
++
++ pLed->CurrLedState = LED_BLINK_StartToBlink;
++ pLed->BlinkTimes = 24;
++
++ if( pLed->bLedOn )
++ pLed->BlinkingLedState = RTW_LED_OFF;
++ else
++ pLed->BlinkingLedState = RTW_LED_ON;
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL);
++ }
++ else
++ {
++ pLed->CurrLedState = LED_BLINK_StartToBlink;
++ }
++ break;
++
++ case LED_CTL_LINK:
++ pLed->CurrLedState = RTW_LED_ON;
++ if( pLed->bLedBlinkInProgress == _FALSE )
++ {
++ SwLedOn(padapter, pLed);
++ }
++ break;
++
++ case LED_CTL_NO_LINK:
++ pLed->CurrLedState = RTW_LED_OFF;
++ if( pLed->bLedBlinkInProgress == _FALSE )
++ {
++ SwLedOff(padapter, pLed);
++ }
++ break;
++
++ case LED_CTL_POWER_OFF:
++ pLed->CurrLedState = RTW_LED_OFF;
++ if(pLed->bLedBlinkInProgress)
++ {
++ _cancel_timer_ex(&(pLed->BlinkTimer));
++ pLed->bLedBlinkInProgress = _FALSE;
++ }
++ SwLedOff(padapter, pLed);
++ break;
++
++ case LED_CTL_START_WPS:
++ if( pLed->bLedBlinkInProgress == _FALSE || pLed->CurrLedState == RTW_LED_ON)
++ {
++ pLed->bLedBlinkInProgress = _TRUE;
++
++ pLed->CurrLedState = LED_BLINK_WPS;
++ pLed->BlinkTimes = 20;
++
++ if( pLed->bLedOn )
++ {
++ pLed->BlinkingLedState = RTW_LED_OFF;
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_LONG_INTERVAL);
++ }
++ else
++ {
++ pLed->BlinkingLedState = RTW_LED_ON;
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_LONG_INTERVAL);
++ }
++ }
++ break;
++
++ case LED_CTL_STOP_WPS:
++ if(pLed->bLedBlinkInProgress)
++ {
++ pLed->CurrLedState = RTW_LED_OFF;
++ _cancel_timer_ex(&(pLed->BlinkTimer));
++ pLed->bLedBlinkInProgress = _FALSE;
++ }
++ break;
++
++
++ default:
++ break;
++ }
++
++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Led %d\n", pLed->CurrLedState));
++
++}
++
++ //ALPHA, added by chiyoko, 20090106
++static void
++SwLedControlMode1(
++ _adapter *padapter,
++ LED_CTL_MODE LedAction
++)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++ struct led_priv *ledpriv = &(padapter->ledpriv);
++ PLED_871x pLed = &(ledpriv->SwLed0);
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++
++ if(pHalData->EEPROMCustomerID == RT_CID_819x_CAMEO)
++ pLed = &(ledpriv->SwLed1);
++
++ switch(LedAction)
++ {
++ case LED_CTL_POWER_ON:
++ case LED_CTL_START_TO_LINK:
++ case LED_CTL_NO_LINK:
++ if( pLed->bLedNoLinkBlinkInProgress == _FALSE )
++ {
++ if(pLed->CurrLedState == LED_SCAN_BLINK || IS_LED_WPS_BLINKING(pLed))
++ {
++ return;
++ }
++ if( pLed->bLedLinkBlinkInProgress == _TRUE )
++ {
++ _cancel_timer_ex(&(pLed->BlinkTimer));
++ pLed->bLedLinkBlinkInProgress = _FALSE;
++ }
++ if(pLed->bLedBlinkInProgress ==_TRUE)
++ {
++ _cancel_timer_ex(&(pLed->BlinkTimer));
++ pLed->bLedBlinkInProgress = _FALSE;
++ }
++
++ pLed->bLedNoLinkBlinkInProgress = _TRUE;
++ pLed->CurrLedState = LED_BLINK_SLOWLY;
++ if( pLed->bLedOn )
++ pLed->BlinkingLedState = RTW_LED_OFF;
++ else
++ pLed->BlinkingLedState = RTW_LED_ON;
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA);
++ }
++ break;
++
++ case LED_CTL_LINK:
++ if( pLed->bLedLinkBlinkInProgress == _FALSE )
++ {
++ if(pLed->CurrLedState == LED_SCAN_BLINK || IS_LED_WPS_BLINKING(pLed))
++ {
++ return;
++ }
++ if(pLed->bLedNoLinkBlinkInProgress == _TRUE)
++ {
++ _cancel_timer_ex(&(pLed->BlinkTimer));
++ pLed->bLedNoLinkBlinkInProgress = _FALSE;
++ }
++ if(pLed->bLedBlinkInProgress ==_TRUE)
++ {
++ _cancel_timer_ex(&(pLed->BlinkTimer));
++ pLed->bLedBlinkInProgress = _FALSE;
++ }
++ pLed->bLedLinkBlinkInProgress = _TRUE;
++ pLed->CurrLedState = LED_BLINK_NORMAL;
++ if( pLed->bLedOn )
++ pLed->BlinkingLedState = RTW_LED_OFF;
++ else
++ pLed->BlinkingLedState = RTW_LED_ON;
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_LINK_INTERVAL_ALPHA);
++ }
++ break;
++
++ case LED_CTL_SITE_SURVEY:
++ if((pmlmepriv->LinkDetectInfo.bBusyTraffic) && (check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE))
++ ;
++ else if(pLed->bLedScanBlinkInProgress ==_FALSE)
++ {
++ if(IS_LED_WPS_BLINKING(pLed))
++ return;
++
++ if(pLed->bLedNoLinkBlinkInProgress == _TRUE)
++ {
++ _cancel_timer_ex(&(pLed->BlinkTimer));
++ pLed->bLedNoLinkBlinkInProgress = _FALSE;
++ }
++ if( pLed->bLedLinkBlinkInProgress == _TRUE )
++ {
++ _cancel_timer_ex(&(pLed->BlinkTimer));
++ pLed->bLedLinkBlinkInProgress = _FALSE;
++ }
++ if(pLed->bLedBlinkInProgress ==_TRUE)
++ {
++ _cancel_timer_ex(&(pLed->BlinkTimer));
++ pLed->bLedBlinkInProgress = _FALSE;
++ }
++ pLed->bLedScanBlinkInProgress = _TRUE;
++ pLed->CurrLedState = LED_SCAN_BLINK;
++ pLed->BlinkTimes = 24;
++ if( pLed->bLedOn )
++ pLed->BlinkingLedState = RTW_LED_OFF;
++ else
++ pLed->BlinkingLedState = RTW_LED_ON;
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA);
++ }
++ break;
++
++ case LED_CTL_TX:
++ case LED_CTL_RX:
++ if(pLed->bLedBlinkInProgress ==_FALSE)
++ {
++ if(pLed->CurrLedState == LED_SCAN_BLINK || IS_LED_WPS_BLINKING(pLed))
++ {
++ return;
++ }
++ if(pLed->bLedNoLinkBlinkInProgress == _TRUE)
++ {
++ _cancel_timer_ex(&(pLed->BlinkTimer));
++ pLed->bLedNoLinkBlinkInProgress = _FALSE;
++ }
++ if( pLed->bLedLinkBlinkInProgress == _TRUE )
++ {
++ _cancel_timer_ex(&(pLed->BlinkTimer));
++ pLed->bLedLinkBlinkInProgress = _FALSE;
++ }
++ pLed->bLedBlinkInProgress = _TRUE;
++ pLed->CurrLedState = LED_TXRX_BLINK;
++ pLed->BlinkTimes = 2;
++ if( pLed->bLedOn )
++ pLed->BlinkingLedState = RTW_LED_OFF;
++ else
++ pLed->BlinkingLedState = RTW_LED_ON;
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA);
++ }
++ break;
++
++ case LED_CTL_START_WPS: //wait until xinpin finish
++ case LED_CTL_START_WPS_BOTTON:
++ if(pLed->bLedWPSBlinkInProgress ==_FALSE)
++ {
++ if(pLed->bLedNoLinkBlinkInProgress == _TRUE)
++ {
++ _cancel_timer_ex(&(pLed->BlinkTimer));
++ pLed->bLedNoLinkBlinkInProgress = _FALSE;
++ }
++ if( pLed->bLedLinkBlinkInProgress == _TRUE )
++ {
++ _cancel_timer_ex(&(pLed->BlinkTimer));
++ pLed->bLedLinkBlinkInProgress = _FALSE;
++ }
++ if(pLed->bLedBlinkInProgress ==_TRUE)
++ {
++ _cancel_timer_ex(&(pLed->BlinkTimer));
++ pLed->bLedBlinkInProgress = _FALSE;
++ }
++ if(pLed->bLedScanBlinkInProgress ==_TRUE)
++ {
++ _cancel_timer_ex(&(pLed->BlinkTimer));
++ pLed->bLedScanBlinkInProgress = _FALSE;
++ }
++ pLed->bLedWPSBlinkInProgress = _TRUE;
++ pLed->CurrLedState = LED_BLINK_WPS;
++ if( pLed->bLedOn )
++ pLed->BlinkingLedState = RTW_LED_OFF;
++ else
++ pLed->BlinkingLedState = RTW_LED_ON;
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA);
++ }
++ break;
++
++
++ case LED_CTL_STOP_WPS:
++ if(pLed->bLedNoLinkBlinkInProgress == _TRUE)
++ {
++ _cancel_timer_ex(&(pLed->BlinkTimer));
++ pLed->bLedNoLinkBlinkInProgress = _FALSE;
++ }
++ if( pLed->bLedLinkBlinkInProgress == _TRUE )
++ {
++ _cancel_timer_ex(&(pLed->BlinkTimer));
++ pLed->bLedLinkBlinkInProgress = _FALSE;
++ }
++ if(pLed->bLedBlinkInProgress ==_TRUE)
++ {
++ _cancel_timer_ex(&(pLed->BlinkTimer));
++ pLed->bLedBlinkInProgress = _FALSE;
++ }
++ if(pLed->bLedScanBlinkInProgress ==_TRUE)
++ {
++ _cancel_timer_ex(&(pLed->BlinkTimer));
++ pLed->bLedScanBlinkInProgress = _FALSE;
++ }
++ if(pLed->bLedWPSBlinkInProgress)
++ {
++ _cancel_timer_ex(&(pLed->BlinkTimer));
++ }
++ else
++ {
++ pLed->bLedWPSBlinkInProgress = _TRUE;
++ }
++
++ pLed->CurrLedState = LED_BLINK_WPS_STOP;
++ if(pLed->bLedOn)
++ {
++ pLed->BlinkingLedState = RTW_LED_OFF;
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_WPS_SUCESS_INTERVAL_ALPHA);
++ }
++ else
++ {
++ pLed->BlinkingLedState = RTW_LED_ON;
++ _set_timer(&(pLed->BlinkTimer), 0);
++ }
++ break;
++
++ case LED_CTL_STOP_WPS_FAIL:
++ if(pLed->bLedWPSBlinkInProgress)
++ {
++ _cancel_timer_ex(&(pLed->BlinkTimer));
++ pLed->bLedWPSBlinkInProgress = _FALSE;
++ }
++
++ pLed->bLedNoLinkBlinkInProgress = _TRUE;
++ pLed->CurrLedState = LED_BLINK_SLOWLY;
++ if( pLed->bLedOn )
++ pLed->BlinkingLedState = RTW_LED_OFF;
++ else
++ pLed->BlinkingLedState = RTW_LED_ON;
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA);
++ break;
++
++ case LED_CTL_POWER_OFF:
++ pLed->CurrLedState = RTW_LED_OFF;
++ pLed->BlinkingLedState = RTW_LED_OFF;
++ if( pLed->bLedNoLinkBlinkInProgress)
++ {
++ _cancel_timer_ex(&(pLed->BlinkTimer));
++ pLed->bLedNoLinkBlinkInProgress = _FALSE;
++ }
++ if( pLed->bLedLinkBlinkInProgress)
++ {
++ _cancel_timer_ex(&(pLed->BlinkTimer));
++ pLed->bLedLinkBlinkInProgress = _FALSE;
++ }
++ if( pLed->bLedBlinkInProgress)
++ {
++ _cancel_timer_ex(&(pLed->BlinkTimer));
++ pLed->bLedBlinkInProgress = _FALSE;
++ }
++ if( pLed->bLedWPSBlinkInProgress )
++ {
++ _cancel_timer_ex(&(pLed->BlinkTimer));
++ pLed->bLedWPSBlinkInProgress = _FALSE;
++ }
++ if( pLed->bLedScanBlinkInProgress)
++ {
++ _cancel_timer_ex(&(pLed->BlinkTimer));
++ pLed->bLedScanBlinkInProgress = _FALSE;
++ }
++
++ SwLedOff(padapter, pLed);
++ break;
++
++ default:
++ break;
++
++ }
++
++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Led %d\n", pLed->CurrLedState));
++}
++
++ //Arcadyan/Sitecom , added by chiyoko, 20090216
++static void
++SwLedControlMode2(
++ _adapter *padapter,
++ LED_CTL_MODE LedAction
++)
++{
++ struct led_priv *ledpriv = &(padapter->ledpriv);
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ PLED_871x pLed = &(ledpriv->SwLed0);
++
++ switch(LedAction)
++ {
++ case LED_CTL_SITE_SURVEY:
++ if(pmlmepriv->LinkDetectInfo.bBusyTraffic)
++ ;
++ else if(pLed->bLedScanBlinkInProgress ==_FALSE)
++ {
++ if(IS_LED_WPS_BLINKING(pLed))
++ return;
++
++ if(pLed->bLedBlinkInProgress ==_TRUE)
++ {
++ _cancel_timer_ex(&(pLed->BlinkTimer));
++ pLed->bLedBlinkInProgress = _FALSE;
++ }
++ pLed->bLedScanBlinkInProgress = _TRUE;
++ pLed->CurrLedState = LED_SCAN_BLINK;
++ pLed->BlinkTimes = 24;
++ if( pLed->bLedOn )
++ pLed->BlinkingLedState = RTW_LED_OFF;
++ else
++ pLed->BlinkingLedState = RTW_LED_ON;
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA);
++ }
++ break;
++
++ case LED_CTL_TX:
++ case LED_CTL_RX:
++ if((pLed->bLedBlinkInProgress ==_FALSE) && (check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE))
++ {
++ if(pLed->CurrLedState == LED_SCAN_BLINK || IS_LED_WPS_BLINKING(pLed))
++ {
++ return;
++ }
++
++ pLed->bLedBlinkInProgress = _TRUE;
++ pLed->CurrLedState = LED_TXRX_BLINK;
++ pLed->BlinkTimes = 2;
++ if( pLed->bLedOn )
++ pLed->BlinkingLedState = RTW_LED_OFF;
++ else
++ pLed->BlinkingLedState = RTW_LED_ON;
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA);
++ }
++ break;
++
++ case LED_CTL_LINK:
++ pLed->CurrLedState = RTW_LED_ON;
++ pLed->BlinkingLedState = RTW_LED_ON;
++ if( pLed->bLedBlinkInProgress)
++ {
++ _cancel_timer_ex(&(pLed->BlinkTimer));
++ pLed->bLedBlinkInProgress = _FALSE;
++ }
++ if( pLed->bLedScanBlinkInProgress)
++ {
++ _cancel_timer_ex(&(pLed->BlinkTimer));
++ pLed->bLedScanBlinkInProgress = _FALSE;
++ }
++
++ _set_timer(&(pLed->BlinkTimer), 0);
++ break;
++
++ case LED_CTL_START_WPS: //wait until xinpin finish
++ case LED_CTL_START_WPS_BOTTON:
++ if(pLed->bLedWPSBlinkInProgress ==_FALSE)
++ {
++ if(pLed->bLedBlinkInProgress ==_TRUE)
++ {
++ _cancel_timer_ex(&(pLed->BlinkTimer));
++ pLed->bLedBlinkInProgress = _FALSE;
++ }
++ if(pLed->bLedScanBlinkInProgress ==_TRUE)
++ {
++ _cancel_timer_ex(&(pLed->BlinkTimer));
++ pLed->bLedScanBlinkInProgress = _FALSE;
++ }
++ pLed->bLedWPSBlinkInProgress = _TRUE;
++ pLed->CurrLedState = RTW_LED_ON;
++ pLed->BlinkingLedState = RTW_LED_ON;
++ _set_timer(&(pLed->BlinkTimer), 0);
++ }
++ break;
++
++ case LED_CTL_STOP_WPS:
++ pLed->bLedWPSBlinkInProgress = _FALSE;
++ if(padapter->pwrctrlpriv.rf_pwrstate != rf_on)
++ {
++ SwLedOff(padapter, pLed);
++ }
++ else
++ {
++ pLed->CurrLedState = RTW_LED_ON;
++ pLed->BlinkingLedState = RTW_LED_ON;
++ _set_timer(&(pLed->BlinkTimer), 0);
++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("CurrLedState %d\n", pLed->CurrLedState));
++ }
++ break;
++
++ case LED_CTL_STOP_WPS_FAIL:
++ pLed->bLedWPSBlinkInProgress = _FALSE;
++ if(padapter->pwrctrlpriv.rf_pwrstate != rf_on)
++ {
++ SwLedOff(padapter, pLed);
++ }
++ else
++ {
++ pLed->CurrLedState = RTW_LED_OFF;
++ pLed->BlinkingLedState = RTW_LED_OFF;
++ _set_timer(&(pLed->BlinkTimer), 0);
++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("CurrLedState %d\n", pLed->CurrLedState));
++ }
++ break;
++
++ case LED_CTL_START_TO_LINK:
++ case LED_CTL_NO_LINK:
++ if(!IS_LED_BLINKING(pLed))
++ {
++ pLed->CurrLedState = RTW_LED_OFF;
++ pLed->BlinkingLedState = RTW_LED_OFF;
++ _set_timer(&(pLed->BlinkTimer), 0);
++ }
++ break;
++
++ case LED_CTL_POWER_OFF:
++ pLed->CurrLedState = RTW_LED_OFF;
++ pLed->BlinkingLedState = RTW_LED_OFF;
++ if( pLed->bLedBlinkInProgress)
++ {
++ _cancel_timer_ex(&(pLed->BlinkTimer));
++ pLed->bLedBlinkInProgress = _FALSE;
++ }
++ if( pLed->bLedScanBlinkInProgress)
++ {
++ _cancel_timer_ex(&(pLed->BlinkTimer));
++ pLed->bLedScanBlinkInProgress = _FALSE;
++ }
++ if( pLed->bLedWPSBlinkInProgress )
++ {
++ _cancel_timer_ex(&(pLed->BlinkTimer));
++ pLed->bLedWPSBlinkInProgress = _FALSE;
++ }
++
++ _set_timer(&(pLed->BlinkTimer), 0);
++ break;
++
++ default:
++ break;
++
++ }
++
++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("CurrLedState %d\n", pLed->CurrLedState));
++}
++
++ //COREGA, added by chiyoko, 20090316
++ static void
++ SwLedControlMode3(
++ _adapter *padapter,
++ LED_CTL_MODE LedAction
++)
++{
++ struct led_priv *ledpriv = &(padapter->ledpriv);
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ PLED_871x pLed = &(ledpriv->SwLed0);
++
++ switch(LedAction)
++ {
++ case LED_CTL_SITE_SURVEY:
++ if(pmlmepriv->LinkDetectInfo.bBusyTraffic)
++ ;
++ else if(pLed->bLedScanBlinkInProgress ==_FALSE)
++ {
++ if(IS_LED_WPS_BLINKING(pLed))
++ return;
++
++ if(pLed->bLedBlinkInProgress ==_TRUE)
++ {
++ _cancel_timer_ex(&(pLed->BlinkTimer));
++ pLed->bLedBlinkInProgress = _FALSE;
++ }
++ pLed->bLedScanBlinkInProgress = _TRUE;
++ pLed->CurrLedState = LED_SCAN_BLINK;
++ pLed->BlinkTimes = 24;
++ if( pLed->bLedOn )
++ pLed->BlinkingLedState = RTW_LED_OFF;
++ else
++ pLed->BlinkingLedState = RTW_LED_ON;
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA);
++ }
++ break;
++
++ case LED_CTL_TX:
++ case LED_CTL_RX:
++ if((pLed->bLedBlinkInProgress ==_FALSE) && (check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE))
++ {
++ if(pLed->CurrLedState == LED_SCAN_BLINK || IS_LED_WPS_BLINKING(pLed))
++ {
++ return;
++ }
++
++ pLed->bLedBlinkInProgress = _TRUE;
++ pLed->CurrLedState = LED_TXRX_BLINK;
++ pLed->BlinkTimes = 2;
++ if( pLed->bLedOn )
++ pLed->BlinkingLedState = RTW_LED_OFF;
++ else
++ pLed->BlinkingLedState = RTW_LED_ON;
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA);
++ }
++ break;
++
++ case LED_CTL_LINK:
++ if(IS_LED_WPS_BLINKING(pLed))
++ return;
++
++ pLed->CurrLedState = RTW_LED_ON;
++ pLed->BlinkingLedState = RTW_LED_ON;
++ if( pLed->bLedBlinkInProgress)
++ {
++ _cancel_timer_ex(&(pLed->BlinkTimer));
++ pLed->bLedBlinkInProgress = _FALSE;
++ }
++ if( pLed->bLedScanBlinkInProgress)
++ {
++ _cancel_timer_ex(&(pLed->BlinkTimer));
++ pLed->bLedScanBlinkInProgress = _FALSE;
++ }
++
++ _set_timer(&(pLed->BlinkTimer), 0);
++ break;
++
++ case LED_CTL_START_WPS: //wait until xinpin finish
++ case LED_CTL_START_WPS_BOTTON:
++ if(pLed->bLedWPSBlinkInProgress ==_FALSE)
++ {
++ if(pLed->bLedBlinkInProgress ==_TRUE)
++ {
++ _cancel_timer_ex(&(pLed->BlinkTimer));
++ pLed->bLedBlinkInProgress = _FALSE;
++ }
++ if(pLed->bLedScanBlinkInProgress ==_TRUE)
++ {
++ _cancel_timer_ex(&(pLed->BlinkTimer));
++ pLed->bLedScanBlinkInProgress = _FALSE;
++ }
++ pLed->bLedWPSBlinkInProgress = _TRUE;
++ pLed->CurrLedState = LED_BLINK_WPS;
++ if( pLed->bLedOn )
++ pLed->BlinkingLedState = RTW_LED_OFF;
++ else
++ pLed->BlinkingLedState = RTW_LED_ON;
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA);
++ }
++ break;
++
++ case LED_CTL_STOP_WPS:
++ if(pLed->bLedWPSBlinkInProgress)
++ {
++ _cancel_timer_ex(&(pLed->BlinkTimer));
++ pLed->bLedWPSBlinkInProgress = _FALSE;
++ }
++ else
++ {
++ pLed->bLedWPSBlinkInProgress = _TRUE;
++ }
++
++ pLed->CurrLedState = LED_BLINK_WPS_STOP;
++ if(pLed->bLedOn)
++ {
++ pLed->BlinkingLedState = RTW_LED_OFF;
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_WPS_SUCESS_INTERVAL_ALPHA);
++ }
++ else
++ {
++ pLed->BlinkingLedState = RTW_LED_ON;
++ _set_timer(&(pLed->BlinkTimer), 0);
++ }
++
++ break;
++
++ case LED_CTL_STOP_WPS_FAIL:
++ if(pLed->bLedWPSBlinkInProgress)
++ {
++ _cancel_timer_ex(&(pLed->BlinkTimer));
++ pLed->bLedWPSBlinkInProgress = _FALSE;
++ }
++
++ pLed->CurrLedState = RTW_LED_OFF;
++ pLed->BlinkingLedState = RTW_LED_OFF;
++ _set_timer(&(pLed->BlinkTimer), 0);
++ break;
++
++ case LED_CTL_START_TO_LINK:
++ case LED_CTL_NO_LINK:
++ if(!IS_LED_BLINKING(pLed))
++ {
++ pLed->CurrLedState = RTW_LED_OFF;
++ pLed->BlinkingLedState = RTW_LED_OFF;
++ _set_timer(&(pLed->BlinkTimer), 0);
++ }
++ break;
++
++ case LED_CTL_POWER_OFF:
++ pLed->CurrLedState = RTW_LED_OFF;
++ pLed->BlinkingLedState = RTW_LED_OFF;
++ if( pLed->bLedBlinkInProgress)
++ {
++ _cancel_timer_ex(&(pLed->BlinkTimer));
++ pLed->bLedBlinkInProgress = _FALSE;
++ }
++ if( pLed->bLedScanBlinkInProgress)
++ {
++ _cancel_timer_ex(&(pLed->BlinkTimer));
++ pLed->bLedScanBlinkInProgress = _FALSE;
++ }
++ if( pLed->bLedWPSBlinkInProgress )
++ {
++ _cancel_timer_ex(&(pLed->BlinkTimer));
++ pLed->bLedWPSBlinkInProgress = _FALSE;
++ }
++
++ _set_timer(&(pLed->BlinkTimer), 0);
++ break;
++
++ default:
++ break;
++
++ }
++
++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("CurrLedState %d\n", pLed->CurrLedState));
++}
++
++
++ //Edimax-Belkin, added by chiyoko, 20090413
++static void
++SwLedControlMode4(
++ _adapter *padapter,
++ LED_CTL_MODE LedAction
++)
++{
++ struct led_priv *ledpriv = &(padapter->ledpriv);
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ PLED_871x pLed = &(ledpriv->SwLed0);
++ PLED_871x pLed1 = &(ledpriv->SwLed1);
++
++ switch(LedAction)
++ {
++ case LED_CTL_START_TO_LINK:
++ if(pLed1->bLedWPSBlinkInProgress)
++ {
++ pLed1->bLedWPSBlinkInProgress = _FALSE;
++ _cancel_timer_ex(&(pLed1->BlinkTimer));
++
++ pLed1->BlinkingLedState = RTW_LED_OFF;
++ pLed1->CurrLedState = RTW_LED_OFF;
++
++ if(pLed1->bLedOn)
++ _set_timer(&(pLed->BlinkTimer), 0);
++ }
++
++ if( pLed->bLedStartToLinkBlinkInProgress == _FALSE )
++ {
++ if(pLed->CurrLedState == LED_SCAN_BLINK || IS_LED_WPS_BLINKING(pLed))
++ {
++ return;
++ }
++ if(pLed->bLedBlinkInProgress ==_TRUE)
++ {
++ _cancel_timer_ex(&(pLed->BlinkTimer));
++ pLed->bLedBlinkInProgress = _FALSE;
++ }
++ if(pLed->bLedNoLinkBlinkInProgress ==_TRUE)
++ {
++ _cancel_timer_ex(&(pLed->BlinkTimer));
++ pLed->bLedNoLinkBlinkInProgress = _FALSE;
++ }
++
++ pLed->bLedStartToLinkBlinkInProgress = _TRUE;
++ pLed->CurrLedState = LED_BLINK_StartToBlink;
++ if( pLed->bLedOn )
++ {
++ pLed->BlinkingLedState = RTW_LED_OFF;
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL);
++ }
++ else
++ {
++ pLed->BlinkingLedState = RTW_LED_ON;
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL);
++ }
++ }
++ break;
++
++ case LED_CTL_LINK:
++ case LED_CTL_NO_LINK:
++ //LED1 settings
++ if(LedAction == LED_CTL_LINK)
++ {
++ if(pLed1->bLedWPSBlinkInProgress)
++ {
++ pLed1->bLedWPSBlinkInProgress = _FALSE;
++ _cancel_timer_ex(&(pLed1->BlinkTimer));
++
++ pLed1->BlinkingLedState = RTW_LED_OFF;
++ pLed1->CurrLedState = RTW_LED_OFF;
++
++ if(pLed1->bLedOn)
++ _set_timer(&(pLed->BlinkTimer), 0);
++ }
++ }
++
++ if( pLed->bLedNoLinkBlinkInProgress == _FALSE )
++ {
++ if(pLed->CurrLedState == LED_SCAN_BLINK || IS_LED_WPS_BLINKING(pLed))
++ {
++ return;
++ }
++ if(pLed->bLedBlinkInProgress ==_TRUE)
++ {
++ _cancel_timer_ex(&(pLed->BlinkTimer));
++ pLed->bLedBlinkInProgress = _FALSE;
++ }
++
++ pLed->bLedNoLinkBlinkInProgress = _TRUE;
++ pLed->CurrLedState = LED_BLINK_SLOWLY;
++ if( pLed->bLedOn )
++ pLed->BlinkingLedState = RTW_LED_OFF;
++ else
++ pLed->BlinkingLedState = RTW_LED_ON;
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA);
++ }
++ break;
++
++ case LED_CTL_SITE_SURVEY:
++ if((pmlmepriv->LinkDetectInfo.bBusyTraffic) && (check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE))
++ ;
++ else if(pLed->bLedScanBlinkInProgress ==_FALSE)
++ {
++ if(IS_LED_WPS_BLINKING(pLed))
++ return;
++
++ if(pLed->bLedNoLinkBlinkInProgress == _TRUE)
++ {
++ _cancel_timer_ex(&(pLed->BlinkTimer));
++ pLed->bLedNoLinkBlinkInProgress = _FALSE;
++ }
++ if(pLed->bLedBlinkInProgress ==_TRUE)
++ {
++ _cancel_timer_ex(&(pLed->BlinkTimer));
++ pLed->bLedBlinkInProgress = _FALSE;
++ }
++ pLed->bLedScanBlinkInProgress = _TRUE;
++ pLed->CurrLedState = LED_SCAN_BLINK;
++ pLed->BlinkTimes = 24;
++ if( pLed->bLedOn )
++ pLed->BlinkingLedState = RTW_LED_OFF;
++ else
++ pLed->BlinkingLedState = RTW_LED_ON;
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA);
++ }
++ break;
++
++ case LED_CTL_TX:
++ case LED_CTL_RX:
++ if(pLed->bLedBlinkInProgress ==_FALSE)
++ {
++ if(pLed->CurrLedState == LED_SCAN_BLINK || IS_LED_WPS_BLINKING(pLed))
++ {
++ return;
++ }
++ if(pLed->bLedNoLinkBlinkInProgress == _TRUE)
++ {
++ _cancel_timer_ex(&(pLed->BlinkTimer));
++ pLed->bLedNoLinkBlinkInProgress = _FALSE;
++ }
++ pLed->bLedBlinkInProgress = _TRUE;
++ pLed->CurrLedState = LED_TXRX_BLINK;
++ pLed->BlinkTimes = 2;
++ if( pLed->bLedOn )
++ pLed->BlinkingLedState = RTW_LED_OFF;
++ else
++ pLed->BlinkingLedState = RTW_LED_ON;
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA);
++ }
++ break;
++
++ case LED_CTL_START_WPS: //wait until xinpin finish
++ case LED_CTL_START_WPS_BOTTON:
++ if(pLed1->bLedWPSBlinkInProgress)
++ {
++ pLed1->bLedWPSBlinkInProgress = _FALSE;
++ _cancel_timer_ex(&(pLed1->BlinkTimer));
++
++ pLed1->BlinkingLedState = RTW_LED_OFF;
++ pLed1->CurrLedState = RTW_LED_OFF;
++
++ if(pLed1->bLedOn)
++ _set_timer(&(pLed->BlinkTimer), 0);
++ }
++
++ if(pLed->bLedWPSBlinkInProgress ==_FALSE)
++ {
++ if(pLed->bLedNoLinkBlinkInProgress == _TRUE)
++ {
++ _cancel_timer_ex(&(pLed->BlinkTimer));
++ pLed->bLedNoLinkBlinkInProgress = _FALSE;
++ }
++ if(pLed->bLedBlinkInProgress ==_TRUE)
++ {
++ _cancel_timer_ex(&(pLed->BlinkTimer));
++ pLed->bLedBlinkInProgress = _FALSE;
++ }
++ if(pLed->bLedScanBlinkInProgress ==_TRUE)
++ {
++ _cancel_timer_ex(&(pLed->BlinkTimer));
++ pLed->bLedScanBlinkInProgress = _FALSE;
++ }
++ pLed->bLedWPSBlinkInProgress = _TRUE;
++ pLed->CurrLedState = LED_BLINK_WPS;
++ if( pLed->bLedOn )
++ {
++ pLed->BlinkingLedState = RTW_LED_OFF;
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL);
++ }
++ else
++ {
++ pLed->BlinkingLedState = RTW_LED_ON;
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL);
++ }
++ }
++ break;
++
++ case LED_CTL_STOP_WPS: //WPS connect success
++ if(pLed->bLedWPSBlinkInProgress)
++ {
++ _cancel_timer_ex(&(pLed->BlinkTimer));
++ pLed->bLedWPSBlinkInProgress = _FALSE;
++ }
++
++ pLed->bLedNoLinkBlinkInProgress = _TRUE;
++ pLed->CurrLedState = LED_BLINK_SLOWLY;
++ if( pLed->bLedOn )
++ pLed->BlinkingLedState = RTW_LED_OFF;
++ else
++ pLed->BlinkingLedState = RTW_LED_ON;
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA);
++
++ break;
++
++ case LED_CTL_STOP_WPS_FAIL: //WPS authentication fail
++ if(pLed->bLedWPSBlinkInProgress)
++ {
++ _cancel_timer_ex(&(pLed->BlinkTimer));
++ pLed->bLedWPSBlinkInProgress = _FALSE;
++ }
++
++ pLed->bLedNoLinkBlinkInProgress = _TRUE;
++ pLed->CurrLedState = LED_BLINK_SLOWLY;
++ if( pLed->bLedOn )
++ pLed->BlinkingLedState = RTW_LED_OFF;
++ else
++ pLed->BlinkingLedState = RTW_LED_ON;
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA);
++
++ //LED1 settings
++ if(pLed1->bLedWPSBlinkInProgress)
++ _cancel_timer_ex(&(pLed1->BlinkTimer));
++ else
++ pLed1->bLedWPSBlinkInProgress = _TRUE;
++
++ pLed1->CurrLedState = LED_BLINK_WPS_STOP;
++ if( pLed1->bLedOn )
++ pLed1->BlinkingLedState = RTW_LED_OFF;
++ else
++ pLed1->BlinkingLedState = RTW_LED_ON;
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL);
++
++ break;
++
++ case LED_CTL_STOP_WPS_FAIL_OVERLAP: //WPS session overlap
++ if(pLed->bLedWPSBlinkInProgress)
++ {
++ _cancel_timer_ex(&(pLed->BlinkTimer));
++ pLed->bLedWPSBlinkInProgress = _FALSE;
++ }
++
++ pLed->bLedNoLinkBlinkInProgress = _TRUE;
++ pLed->CurrLedState = LED_BLINK_SLOWLY;
++ if( pLed->bLedOn )
++ pLed->BlinkingLedState = RTW_LED_OFF;
++ else
++ pLed->BlinkingLedState = RTW_LED_ON;
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA);
++
++ //LED1 settings
++ if(pLed1->bLedWPSBlinkInProgress)
++ _cancel_timer_ex(&(pLed1->BlinkTimer));
++ else
++ pLed1->bLedWPSBlinkInProgress = _TRUE;
++
++ pLed1->CurrLedState = LED_BLINK_WPS_STOP_OVERLAP;
++ pLed1->BlinkTimes = 10;
++ if( pLed1->bLedOn )
++ pLed1->BlinkingLedState = RTW_LED_OFF;
++ else
++ pLed1->BlinkingLedState = RTW_LED_ON;
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL);
++
++ break;
++
++ case LED_CTL_POWER_OFF:
++ pLed->CurrLedState = RTW_LED_OFF;
++ pLed->BlinkingLedState = RTW_LED_OFF;
++
++ if( pLed->bLedNoLinkBlinkInProgress)
++ {
++ _cancel_timer_ex(&(pLed->BlinkTimer));
++ pLed->bLedNoLinkBlinkInProgress = _FALSE;
++ }
++ if( pLed->bLedLinkBlinkInProgress)
++ {
++ _cancel_timer_ex(&(pLed->BlinkTimer));
++ pLed->bLedLinkBlinkInProgress = _FALSE;
++ }
++ if( pLed->bLedBlinkInProgress)
++ {
++ _cancel_timer_ex(&(pLed->BlinkTimer));
++ pLed->bLedBlinkInProgress = _FALSE;
++ }
++ if( pLed->bLedWPSBlinkInProgress )
++ {
++ _cancel_timer_ex(&(pLed->BlinkTimer));
++ pLed->bLedWPSBlinkInProgress = _FALSE;
++ }
++ if( pLed->bLedScanBlinkInProgress)
++ {
++ _cancel_timer_ex(&(pLed->BlinkTimer));
++ pLed->bLedScanBlinkInProgress = _FALSE;
++ }
++ if( pLed->bLedStartToLinkBlinkInProgress)
++ {
++ _cancel_timer_ex(&(pLed->BlinkTimer));
++ pLed->bLedStartToLinkBlinkInProgress = _FALSE;
++ }
++
++ if( pLed1->bLedWPSBlinkInProgress )
++ {
++ _cancel_timer_ex(&(pLed1->BlinkTimer));
++ pLed1->bLedWPSBlinkInProgress = _FALSE;
++ }
++
++ pLed1->BlinkingLedState = LED_UNKNOWN;
++ SwLedOff(padapter, pLed);
++ SwLedOff(padapter, pLed1);
++ break;
++
++ default:
++ break;
++
++ }
++
++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Led %d\n", pLed->CurrLedState));
++}
++
++
++
++ //Sercomm-Belkin, added by chiyoko, 20090415
++static void
++SwLedControlMode5(
++ _adapter *padapter,
++ LED_CTL_MODE LedAction
++)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++ struct led_priv *ledpriv = &(padapter->ledpriv);
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ PLED_871x pLed = &(ledpriv->SwLed0);
++
++ if(pHalData->EEPROMCustomerID == RT_CID_819x_CAMEO)
++ pLed = &(ledpriv->SwLed1);
++
++ switch(LedAction)
++ {
++ case LED_CTL_POWER_ON:
++ case LED_CTL_NO_LINK:
++ case LED_CTL_LINK: //solid blue
++ pLed->CurrLedState = RTW_LED_ON;
++ pLed->BlinkingLedState = RTW_LED_ON;
++
++ _set_timer(&(pLed->BlinkTimer), 0);
++ break;
++
++ case LED_CTL_SITE_SURVEY:
++ if((pmlmepriv->LinkDetectInfo.bBusyTraffic) && (check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE))
++ ;
++ else if(pLed->bLedScanBlinkInProgress ==_FALSE)
++ {
++ if(pLed->bLedBlinkInProgress ==_TRUE)
++ {
++ _cancel_timer_ex(&(pLed->BlinkTimer));
++ pLed->bLedBlinkInProgress = _FALSE;
++ }
++ pLed->bLedScanBlinkInProgress = _TRUE;
++ pLed->CurrLedState = LED_SCAN_BLINK;
++ pLed->BlinkTimes = 24;
++ if( pLed->bLedOn )
++ pLed->BlinkingLedState = RTW_LED_OFF;
++ else
++ pLed->BlinkingLedState = RTW_LED_ON;
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA);
++ }
++ break;
++
++ case LED_CTL_TX:
++ case LED_CTL_RX:
++ if(pLed->bLedBlinkInProgress ==_FALSE)
++ {
++ if(pLed->CurrLedState == LED_SCAN_BLINK)
++ {
++ return;
++ }
++ pLed->bLedBlinkInProgress = _TRUE;
++ pLed->CurrLedState = LED_TXRX_BLINK;
++ pLed->BlinkTimes = 2;
++ if( pLed->bLedOn )
++ pLed->BlinkingLedState = RTW_LED_OFF;
++ else
++ pLed->BlinkingLedState = RTW_LED_ON;
++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA);
++ }
++ break;
++
++ case LED_CTL_POWER_OFF:
++ pLed->CurrLedState = RTW_LED_OFF;
++ pLed->BlinkingLedState = RTW_LED_OFF;
++
++ if( pLed->bLedBlinkInProgress)
++ {
++ _cancel_timer_ex(&(pLed->BlinkTimer));
++ pLed->bLedBlinkInProgress = _FALSE;
++ }
++
++ SwLedOff(padapter, pLed);
++ break;
++
++ default:
++ break;
++
++ }
++
++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Led %d\n", pLed->CurrLedState));
++}
++
++ //WNC-Corega, added by chiyoko, 20090902
++static void
++SwLedControlMode6(
++ _adapter *padapter,
++ LED_CTL_MODE LedAction
++)
++{
++ struct led_priv *ledpriv = &(padapter->ledpriv);
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ PLED_871x pLed0 = &(ledpriv->SwLed0);
++
++ switch(LedAction)
++ {
++ case LED_CTL_POWER_ON:
++ case LED_CTL_LINK:
++ case LED_CTL_NO_LINK:
++ _cancel_timer_ex(&(pLed0->BlinkTimer));
++ pLed0->CurrLedState = RTW_LED_ON;
++ pLed0->BlinkingLedState = RTW_LED_ON;
++ _set_timer(&(pLed0->BlinkTimer), 0);
++ break;
++
++ case LED_CTL_POWER_OFF:
++ SwLedOff(padapter, pLed0);
++ break;
++
++ default:
++ break;
++ }
++
++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("ledcontrol 6 Led %d\n", pLed0->CurrLedState));
++}
++
++
++//
++// Description:
++// Dispatch LED action according to pHalData->LedStrategy.
++//
++static void
++LedControl871x(
++ _adapter *padapter,
++ LED_CTL_MODE LedAction
++ )
++{
++ struct led_priv *ledpriv = &(padapter->ledpriv);
++
++ if( (padapter->bSurpriseRemoved == _TRUE) || ( padapter->bDriverStopped == _TRUE)
++ ||(padapter->hw_init_completed == _FALSE) )
++ {
++ return;
++ }
++
++
++ if( ledpriv->bRegUseLed == _FALSE)
++ return;
++
++ //if (!priv->up)
++ // return;
++
++ //if(priv->bInHctTest)
++ // return;
++
++ if( (padapter->pwrctrlpriv.rf_pwrstate != rf_on &&
++ padapter->pwrctrlpriv.rfoff_reason > RF_CHANGE_BY_PS) &&
++ (LedAction == LED_CTL_TX || LedAction == LED_CTL_RX ||
++ LedAction == LED_CTL_SITE_SURVEY ||
++ LedAction == LED_CTL_LINK ||
++ LedAction == LED_CTL_NO_LINK ||
++ LedAction == LED_CTL_POWER_ON) )
++ {
++ return;
++ }
++
++ switch(ledpriv->LedStrategy)
++ {
++ case SW_LED_MODE0:
++ //SwLedControlMode0(padapter, LedAction);
++ break;
++
++ case SW_LED_MODE1:
++ SwLedControlMode1(padapter, LedAction);
++ break;
++ case SW_LED_MODE2:
++ SwLedControlMode2(padapter, LedAction);
++ break;
++
++ case SW_LED_MODE3:
++ SwLedControlMode3(padapter, LedAction);
++ break;
++
++ case SW_LED_MODE4:
++ SwLedControlMode4(padapter, LedAction);
++ break;
++
++ case SW_LED_MODE5:
++ SwLedControlMode5(padapter, LedAction);
++ break;
++
++ case SW_LED_MODE6:
++ SwLedControlMode6(padapter, LedAction);
++ break;
++
++ default:
++ break;
++ }
++
++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("LedStrategy:%d, LedAction %d\n", ledpriv->LedStrategy,LedAction));
++}
++
++//
++// Description:
++// Initialize all LED_871x objects.
++//
++void
++rtl8192cu_InitSwLeds(
++ _adapter *padapter
++ )
++{
++ struct led_priv *pledpriv = &(padapter->ledpriv);
++
++ pledpriv->LedControlHandler = LedControl871x;
++
++ InitLed871x(padapter, &(pledpriv->SwLed0), LED_PIN_LED0);
++
++ InitLed871x(padapter,&(pledpriv->SwLed1), LED_PIN_LED1);
++}
++
++
++//
++// Description:
++// DeInitialize all LED_819xUsb objects.
++//
++void
++rtl8192cu_DeInitSwLeds(
++ _adapter *padapter
++ )
++{
++ struct led_priv *ledpriv = &(padapter->ledpriv);
++
++ DeInitLed871x( &(ledpriv->SwLed0) );
++ DeInitLed871x( &(ledpriv->SwLed1) );
++}
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/hal/rtl8192c/usb/rtl8192cu_recv.c linux-xbian-rpi/drivers/net/wireless/rtl8192cu/hal/rtl8192c/usb/rtl8192cu_recv.c
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/hal/rtl8192c/usb/rtl8192cu_recv.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/hal/rtl8192c/usb/rtl8192cu_recv.c 2015-07-28 01:20:58.313625760 +0200
+@@ -0,0 +1,227 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#define _RTL8192CU_RECV_C_
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++#include <recv_osdep.h>
++#include <mlme_osdep.h>
++#include <ip.h>
++#include <if_ether.h>
++#include <ethernet.h>
++
++#include <usb_ops.h>
++
++#if defined (PLATFORM_LINUX) && defined (PLATFORM_WINDOWS)
++
++#error "Shall be Linux or Windows, but not both!\n"
++
++#endif
++
++#include <wifi.h>
++#include <circ_buf.h>
++
++#include <rtl8192c_hal.h>
++
++
++void rtl8192cu_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf)
++{
++
++ precvbuf->transfer_len = 0;
++
++ precvbuf->len = 0;
++
++ precvbuf->ref_cnt = 0;
++
++ if(precvbuf->pbuf)
++ {
++ precvbuf->pdata = precvbuf->phead = precvbuf->ptail = precvbuf->pbuf;
++ precvbuf->pend = precvbuf->pdata + MAX_RECVBUF_SZ;
++ }
++
++}
++
++int rtl8192cu_init_recv_priv(_adapter *padapter)
++{
++ struct recv_priv *precvpriv = &padapter->recvpriv;
++ int i, res = _SUCCESS;
++ struct recv_buf *precvbuf;
++
++#ifdef CONFIG_RECV_THREAD_MODE
++ _rtw_init_sema(&precvpriv->recv_sema, 0);//will be removed
++ _rtw_init_sema(&precvpriv->terminate_recvthread_sema, 0);//will be removed
++#endif
++
++#ifdef PLATFORM_LINUX
++ tasklet_init(&precvpriv->recv_tasklet,
++ (void(*)(unsigned long))rtl8192cu_recv_tasklet,
++ (unsigned long)padapter);
++#endif
++
++#ifdef CONFIG_USB_INTERRUPT_IN_PIPE
++#ifdef PLATFORM_LINUX
++ precvpriv->int_in_urb = usb_alloc_urb(0, GFP_KERNEL);
++ if(precvpriv->int_in_urb == NULL){
++ DBG_8192C("alloc_urb for interrupt in endpoint fail !!!!\n");
++ }
++#endif
++ precvpriv->int_in_buf = rtw_zmalloc(sizeof(INTERRUPT_MSG_FORMAT_EX));
++ if(precvpriv->int_in_buf == NULL){
++ DBG_8192C("alloc_mem for interrupt in endpoint fail !!!!\n");
++ }
++#endif
++
++ //init recv_buf
++ _rtw_init_queue(&precvpriv->free_recv_buf_queue);
++
++#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX
++ _rtw_init_queue(&precvpriv->recv_buf_pending_queue);
++#endif // CONFIG_USE_USB_BUFFER_ALLOC_RX
++
++ precvpriv->pallocated_recv_buf = rtw_zmalloc(NR_RECVBUFF *sizeof(struct recv_buf) + 4);
++ if(precvpriv->pallocated_recv_buf==NULL){
++ res= _FAIL;
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("alloc recv_buf fail!\n"));
++ goto exit;
++ }
++ _rtw_memset(precvpriv->pallocated_recv_buf, 0, NR_RECVBUFF *sizeof(struct recv_buf) + 4);
++
++ precvpriv->precv_buf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(precvpriv->pallocated_recv_buf), 4);
++ //precvpriv->precv_buf = precvpriv->pallocated_recv_buf + 4 -
++ // ((uint) (precvpriv->pallocated_recv_buf) &(4-1));
++
++
++ precvbuf = (struct recv_buf*)precvpriv->precv_buf;
++
++ for(i=0; i < NR_RECVBUFF ; i++)
++ {
++ _rtw_init_listhead(&precvbuf->list);
++
++ _rtw_spinlock_init(&precvbuf->recvbuf_lock);
++
++ precvbuf->alloc_sz = MAX_RECVBUF_SZ;
++
++ res = rtw_os_recvbuf_resource_alloc(padapter, precvbuf);
++ if(res==_FAIL)
++ break;
++
++ precvbuf->ref_cnt = 0;
++ precvbuf->adapter =padapter;
++
++
++ //rtw_list_insert_tail(&precvbuf->list, &(precvpriv->free_recv_buf_queue.queue));
++
++ precvbuf++;
++
++ }
++
++ precvpriv->free_recv_buf_queue_cnt = NR_RECVBUFF;
++
++#ifdef PLATFORM_LINUX
++
++ skb_queue_head_init(&precvpriv->rx_skb_queue);
++
++#ifdef CONFIG_PREALLOC_RECV_SKB
++ {
++ int i;
++ SIZE_PTR tmpaddr=0;
++ SIZE_PTR alignment=0;
++ struct sk_buff *pskb=NULL;
++
++ skb_queue_head_init(&precvpriv->free_recv_skb_queue);
++
++ for(i=0; i<NR_PREALLOC_RECV_SKB; i++)
++ {
++ pskb = rtw_skb_alloc(MAX_RECVBUF_SZ + RECVBUFF_ALIGN_SZ);
++
++ if(pskb)
++ {
++ pskb->dev = padapter->pnetdev;
++
++ tmpaddr = (SIZE_PTR)pskb->data;
++ alignment = tmpaddr & (RECVBUFF_ALIGN_SZ-1);
++ skb_reserve(pskb, (RECVBUFF_ALIGN_SZ - alignment));
++
++ skb_queue_tail(&precvpriv->free_recv_skb_queue, pskb);
++ }
++
++ pskb=NULL;
++
++ }
++ }
++#endif
++
++#endif
++
++exit:
++
++ return res;
++
++}
++
++void rtl8192cu_free_recv_priv (_adapter *padapter)
++{
++ int i;
++ struct recv_buf *precvbuf;
++ struct recv_priv *precvpriv = &padapter->recvpriv;
++
++ precvbuf = (struct recv_buf *)precvpriv->precv_buf;
++
++ for(i=0; i < NR_RECVBUFF ; i++)
++ {
++ rtw_os_recvbuf_resource_free(padapter, precvbuf);
++ precvbuf++;
++ }
++
++ if(precvpriv->pallocated_recv_buf)
++ rtw_mfree(precvpriv->pallocated_recv_buf, NR_RECVBUFF *sizeof(struct recv_buf) + 4);
++
++#ifdef CONFIG_USB_INTERRUPT_IN_PIPE
++#ifdef PLATFORM_LINUX
++ if(precvpriv->int_in_urb)
++ {
++ usb_free_urb(precvpriv->int_in_urb);
++ }
++#endif
++ if(precvpriv->int_in_buf)
++ rtw_mfree(precvpriv->int_in_buf, sizeof(INTERRUPT_MSG_FORMAT_EX));
++#endif
++
++#ifdef PLATFORM_LINUX
++
++ if (skb_queue_len(&precvpriv->rx_skb_queue)) {
++ DBG_8192C(KERN_WARNING "rx_skb_queue not empty\n");
++ }
++
++ rtw_skb_queue_purge(&precvpriv->rx_skb_queue);
++
++#ifdef CONFIG_PREALLOC_RECV_SKB
++
++ if (skb_queue_len(&precvpriv->free_recv_skb_queue)) {
++ DBG_8192C(KERN_WARNING "free_recv_skb_queue not empty, %d\n", skb_queue_len(&precvpriv->free_recv_skb_queue));
++ }
++
++ rtw_skb_queue_purge(&precvpriv->free_recv_skb_queue);
++
++#endif
++
++#endif
++
++}
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/hal/rtl8192c/usb/rtl8192cu_xmit.c linux-xbian-rpi/drivers/net/wireless/rtl8192cu/hal/rtl8192c/usb/rtl8192cu_xmit.c
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/hal/rtl8192c/usb/rtl8192cu_xmit.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/hal/rtl8192c/usb/rtl8192cu_xmit.c 2015-07-28 01:20:58.313625760 +0200
+@@ -0,0 +1,1149 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#define _RTL8192C_XMIT_C_
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++#include <rtw_byteorder.h>
++#include <wifi.h>
++#include <osdep_intf.h>
++#include <circ_buf.h>
++#include <usb_ops.h>
++#include <rtl8192c_hal.h>
++
++#if defined (PLATFORM_LINUX) && defined (PLATFORM_WINDOWS)
++#error "Shall be Linux or Windows, but not both!\n"
++#endif
++
++
++s32 rtl8192cu_init_xmit_priv(_adapter *padapter)
++{
++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++
++#ifdef PLATFORM_LINUX
++ tasklet_init(&pxmitpriv->xmit_tasklet,
++ (void(*)(unsigned long))rtl8192cu_xmit_tasklet,
++ (unsigned long)padapter);
++#endif
++ return _SUCCESS;
++}
++
++void rtl8192cu_free_xmit_priv(_adapter *padapter)
++{
++}
++
++u32 rtw_get_ff_hwaddr(struct xmit_frame *pxmitframe)
++{
++ u32 addr;
++ struct pkt_attrib *pattrib = &pxmitframe->attrib;
++
++ switch(pattrib->qsel)
++ {
++ case 0:
++ case 3:
++ addr = BE_QUEUE_INX;
++ break;
++ case 1:
++ case 2:
++ addr = BK_QUEUE_INX;
++ break;
++ case 4:
++ case 5:
++ addr = VI_QUEUE_INX;
++ break;
++ case 6:
++ case 7:
++ addr = VO_QUEUE_INX;
++ break;
++ case 0x10:
++ addr = BCN_QUEUE_INX;
++ break;
++ case 0x11://BC/MC in PS (HIQ)
++ addr = HIGH_QUEUE_INX;
++ break;
++ case 0x12:
++ addr = MGT_QUEUE_INX;
++ break;
++ default:
++ addr = BE_QUEUE_INX;
++ break;
++
++ }
++
++ return addr;
++
++}
++
++int urb_zero_packet_chk(_adapter *padapter, int sz)
++{
++ int blnSetTxDescOffset;
++ struct dvobj_priv *pdvobj = adapter_to_dvobj(padapter);
++
++ if ( pdvobj->ishighspeed )
++ {
++ if ( ( (sz + TXDESC_SIZE) % 512 ) == 0 ) {
++ blnSetTxDescOffset = 1;
++ } else {
++ blnSetTxDescOffset = 0;
++ }
++ }
++ else
++ {
++ if ( ( (sz + TXDESC_SIZE) % 64 ) == 0 ) {
++ blnSetTxDescOffset = 1;
++ } else {
++ blnSetTxDescOffset = 0;
++ }
++ }
++
++ return blnSetTxDescOffset;
++
++}
++
++void rtl8192cu_cal_txdesc_chksum(struct tx_desc *ptxdesc)
++{
++ u16 *usPtr = (u16*)ptxdesc;
++ u32 count = 16; // (32 bytes / 2 bytes per XOR) => 16 times
++ u32 index;
++ u16 checksum = 0;
++
++ //Clear first
++ ptxdesc->txdw7 &= cpu_to_le32(0xffff0000);
++
++ for(index = 0 ; index < count ; index++){
++ checksum = checksum ^ le16_to_cpu(*(usPtr + index));
++ }
++
++ ptxdesc->txdw7 |= cpu_to_le32(0x0000ffff&checksum);
++
++}
++
++void fill_txdesc_sectype(struct pkt_attrib *pattrib, struct tx_desc *ptxdesc)
++{
++ if ((pattrib->encrypt > 0) && !pattrib->bswenc)
++ {
++ switch (pattrib->encrypt)
++ {
++ //SEC_TYPE
++ case _WEP40_:
++ case _WEP104_:
++ ptxdesc->txdw1 |= cpu_to_le32((0x01<<22)&0x00c00000);
++ break;
++ case _TKIP_:
++ case _TKIP_WTMIC_:
++ //ptxdesc->txdw1 |= cpu_to_le32((0x02<<22)&0x00c00000);
++ ptxdesc->txdw1 |= cpu_to_le32((0x01<<22)&0x00c00000);
++ break;
++ case _AES_:
++ ptxdesc->txdw1 |= cpu_to_le32((0x03<<22)&0x00c00000);
++ break;
++ case _NO_PRIVACY_:
++ default:
++ break;
++
++ }
++
++ }
++
++}
++
++static void fill_txdesc_vcs(struct pkt_attrib *pattrib, u32 *pdw)
++{
++ //DBG_8192C("cvs_mode=%d\n", pattrib->vcs_mode);
++
++ switch(pattrib->vcs_mode)
++ {
++ case RTS_CTS:
++ *pdw |= cpu_to_le32(BIT(12));
++ break;
++ case CTS_TO_SELF:
++ *pdw |= cpu_to_le32(BIT(11));
++ break;
++ case NONE_VCS:
++ default:
++ break;
++ }
++
++ if(pattrib->vcs_mode) {
++ *pdw |= cpu_to_le32(BIT(13));
++
++ // Set RTS BW
++ if(pattrib->ht_en)
++ {
++ *pdw |= (pattrib->bwmode&HT_CHANNEL_WIDTH_40)? cpu_to_le32(BIT(27)):0;
++
++ if(pattrib->ch_offset == HAL_PRIME_CHNL_OFFSET_LOWER)
++ *pdw |= cpu_to_le32((0x01<<28)&0x30000000);
++ else if(pattrib->ch_offset == HAL_PRIME_CHNL_OFFSET_UPPER)
++ *pdw |= cpu_to_le32((0x02<<28)&0x30000000);
++ else if(pattrib->ch_offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE)
++ *pdw |= 0;
++ else
++ *pdw |= cpu_to_le32((0x03<<28)&0x30000000);
++ }
++ }
++}
++
++static void fill_txdesc_phy(struct pkt_attrib *pattrib, u32 *pdw)
++{
++ //DBG_8192C("bwmode=%d, ch_off=%d\n", pattrib->bwmode, pattrib->ch_offset);
++
++ if(pattrib->ht_en)
++ {
++ *pdw |= (pattrib->bwmode&HT_CHANNEL_WIDTH_40)? cpu_to_le32(BIT(25)):0;
++
++ if(pattrib->ch_offset == HAL_PRIME_CHNL_OFFSET_LOWER)
++ *pdw |= cpu_to_le32((0x01<<20)&0x00300000);
++ else if(pattrib->ch_offset == HAL_PRIME_CHNL_OFFSET_UPPER)
++ *pdw |= cpu_to_le32((0x02<<20)&0x00300000);
++ else if(pattrib->ch_offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE)
++ *pdw |= 0;
++ else
++ *pdw |= cpu_to_le32((0x03<<20)&0x00300000);
++ }
++}
++
++static s32 update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem, s32 sz, u8 bagg_pkt)
++{
++ int pull=0;
++ uint qsel;
++ _adapter *padapter = pxmitframe->padapter;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct pkt_attrib *pattrib = &pxmitframe->attrib;
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++ struct dm_priv *pdmpriv = &pHalData->dmpriv;
++ struct tx_desc *ptxdesc = (struct tx_desc *)pmem;
++ struct ht_priv *phtpriv = &pmlmepriv->htpriv;
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ sint bmcst = IS_MCAST(pattrib->ra);
++#ifdef CONFIG_P2P
++ struct wifidirect_info* pwdinfo = &padapter->wdinfo;
++#endif //CONFIG_P2P
++
++#ifndef CONFIG_USE_USB_BUFFER_ALLOC_TX
++ if((_FALSE == bagg_pkt) && (urb_zero_packet_chk(padapter, sz)==0))
++ {
++ ptxdesc = (struct tx_desc *)(pmem+PACKET_OFFSET_SZ);
++ pull = 1;
++ pxmitframe->pkt_offset --;
++ }
++#endif // CONFIG_USE_USB_BUFFER_ALLOC_TX
++
++ _rtw_memset(ptxdesc, 0, sizeof(struct tx_desc));
++
++ if((pxmitframe->frame_tag&0x0f) == DATA_FRAMETAG)
++ {
++ //DBG_8192C("pxmitframe->frame_tag == DATA_FRAMETAG\n");
++
++ //offset 4
++ ptxdesc->txdw1 |= cpu_to_le32(pattrib->mac_id&0x1f);
++
++ qsel = (uint)(pattrib->qsel & 0x0000001f);
++ ptxdesc->txdw1 |= cpu_to_le32((qsel << QSEL_SHT) & 0x00001f00);
++
++ ptxdesc->txdw1 |= cpu_to_le32((pattrib->raid<< 16) & 0x000f0000);
++
++ fill_txdesc_sectype(pattrib, ptxdesc);
++
++ if(pattrib->ampdu_en==_TRUE)
++ ptxdesc->txdw1 |= cpu_to_le32(BIT(5));//AGG EN
++ else
++ ptxdesc->txdw1 |= cpu_to_le32(BIT(6));//AGG BK
++
++ //offset 8
++
++
++ //offset 12
++ ptxdesc->txdw3 |= cpu_to_le32((pattrib->seqnum<<16)&0xffff0000);
++
++
++ //offset 16 , offset 20
++ if (pattrib->qos_en)
++ ptxdesc->txdw4 |= cpu_to_le32(BIT(6));//QoS
++
++ if ((pattrib->ether_type != 0x888e) && (pattrib->ether_type != 0x0806) && (pattrib->dhcp_pkt != 1))
++ {
++ //Non EAP & ARP & DHCP type data packet
++
++ fill_txdesc_vcs(pattrib, &ptxdesc->txdw4);
++ fill_txdesc_phy(pattrib, &ptxdesc->txdw4);
++
++ ptxdesc->txdw4 |= cpu_to_le32(0x00000008);//RTS Rate=24M
++ ptxdesc->txdw5 |= cpu_to_le32(0x0001ff00);//
++ //ptxdesc->txdw5 |= cpu_to_le32(0x0000000b);//DataRate - 54M
++
++ //use REG_INIDATA_RATE_SEL value
++ ptxdesc->txdw5 |= cpu_to_le32(pdmpriv->INIDATA_RATE[pattrib->mac_id]);
++
++ if(0)//for driver dbg
++ {
++ ptxdesc->txdw4 |= cpu_to_le32(BIT(8));//driver uses rate
++
++ if(pattrib->ht_en)
++ ptxdesc->txdw5 |= cpu_to_le32(BIT(6));//SGI
++
++ ptxdesc->txdw5 |= cpu_to_le32(0x00000013);//init rate - mcs7
++ }
++
++ }
++ else
++ {
++ // EAP data packet and ARP packet.
++ // Use the 1M data rate to send the EAP/ARP packet.
++ // This will maybe make the handshake smooth.
++
++ ptxdesc->txdw1 |= cpu_to_le32(BIT(6));//AGG BK
++
++ ptxdesc->txdw4 |= cpu_to_le32(BIT(8));//driver uses rate
++
++ if (pmlmeinfo->preamble_mode == PREAMBLE_SHORT)
++ ptxdesc->txdw4 |= cpu_to_le32(BIT(24));// DATA_SHORT
++
++ ptxdesc->txdw5 |= cpu_to_le32(MRateToHwRate(pmlmeext->tx_rate));
++ }
++
++ //offset 24
++#ifdef CONFIG_TCP_CSUM_OFFLOAD_TX
++ if ( pattrib->hw_tcp_csum == 1 ) {
++ // ptxdesc->txdw6 = 0; // clear TCP_CHECKSUM and IP_CHECKSUM. It's zero already!!
++ u8 ip_hdr_offset = 32 + pattrib->hdrlen + pattrib->iv_len + 8;
++ ptxdesc->txdw7 = (1 << 31) | (ip_hdr_offset << 16);
++ DBG_8192C("ptxdesc->txdw7 = %08x\n", ptxdesc->txdw7);
++ }
++#endif
++ }
++ else if((pxmitframe->frame_tag&0x0f)== MGNT_FRAMETAG)
++ {
++ //DBG_8192C("pxmitframe->frame_tag == MGNT_FRAMETAG\n");
++
++ //offset 4
++ ptxdesc->txdw1 |= cpu_to_le32(pattrib->mac_id&0x1f);
++
++ qsel = (uint)(pattrib->qsel&0x0000001f);
++ ptxdesc->txdw1 |= cpu_to_le32((qsel<<QSEL_SHT)&0x00001f00);
++
++ ptxdesc->txdw1 |= cpu_to_le32((pattrib->raid<< 16) & 0x000f0000);
++
++ //fill_txdesc_sectype(pattrib, ptxdesc);
++
++ //offset 8
++#ifdef CONFIG_XMIT_ACK
++ //CCX-TXRPT ack for xmit mgmt frames.
++ if (pxmitframe->ack_report) {
++ ptxdesc->txdw2 |= cpu_to_le32(BIT(19));
++ #ifdef DBG_CCX
++ DBG_871X("%s set ccx\n", __func__);
++ #endif
++ }
++#endif //CONFIG_XMIT_ACK
++
++ //offset 12
++ ptxdesc->txdw3 |= cpu_to_le32((pattrib->seqnum<<16)&0xffff0000);
++
++ //offset 16
++ ptxdesc->txdw4 |= cpu_to_le32(BIT(8));//driver uses rate
++
++ //offset 20
++ ptxdesc->txdw5 |= cpu_to_le32(BIT(17));//retry limit enable
++ if(pattrib->retry_ctrl == _TRUE)
++ {
++#ifdef CONFIG_P2P
++ if(!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
++ {
++#ifdef CONFIG_INTEL_WIDI
++ if(padapter->mlmepriv.widi_enable == _TRUE)
++ ptxdesc->txdw5 |= cpu_to_le32(0x00180000);//retry limit = 6
++ else
++#endif //CONFIG_INTEL_WIDI
++ ptxdesc->txdw5 |= cpu_to_le32(0x00080000);//retry limit = 2
++ }
++ else
++#endif //CONFIG_P2P
++ ptxdesc->txdw5 |= cpu_to_le32(0x00180000);//retry limit = 6
++ }
++ else
++ ptxdesc->txdw5 |= cpu_to_le32(0x00300000);//retry limit = 12
++
++#ifdef CONFIG_INTEL_PROXIM
++ if((padapter->proximity.proxim_on==_TRUE)&&(pattrib->intel_proxim==_TRUE)){
++ printk("\n %s pattrib->rate=%d\n",__FUNCTION__,pattrib->rate);
++ ptxdesc->txdw5 |= cpu_to_le32( pattrib->rate);
++ }
++ else
++#endif
++ {
++ ptxdesc->txdw5 |= cpu_to_le32(MRateToHwRate(pmlmeext->tx_rate));
++ }
++ }
++ else if((pxmitframe->frame_tag&0x0f) == TXAGG_FRAMETAG)
++ {
++ DBG_8192C("pxmitframe->frame_tag == TXAGG_FRAMETAG\n");
++ }
++#ifdef CONFIG_MP_INCLUDED
++ else if((pxmitframe->frame_tag&0x0f) == MP_FRAMETAG)
++ {
++ fill_txdesc_for_mp(padapter, ptxdesc);
++ }
++#endif
++ else
++ {
++ DBG_8192C("pxmitframe->frame_tag = %d\n", pxmitframe->frame_tag);
++
++ //offset 4
++ ptxdesc->txdw1 |= cpu_to_le32((4)&0x1f);//CAM_ID(MAC_ID)
++
++ ptxdesc->txdw1 |= cpu_to_le32((6<< 16) & 0x000f0000);//raid
++
++ //offset 8
++
++ //offset 12
++ ptxdesc->txdw3 |= cpu_to_le32((pattrib->seqnum<<16)&0xffff0000);
++
++ //offset 16
++ ptxdesc->txdw4 |= cpu_to_le32(BIT(8));//driver uses rate
++
++ //offset 20
++ ptxdesc->txdw5 |= cpu_to_le32(MRateToHwRate(pmlmeext->tx_rate));
++ }
++
++ // 2009.11.05. tynli_test. Suggested by SD4 Filen for FW LPS.
++ // (1) The sequence number of each non-Qos frame / broadcast / multicast /
++ // mgnt frame should be controled by Hw because Fw will also send null data
++ // which we cannot control when Fw LPS enable.
++ // --> default enable non-Qos data sequense number. 2010.06.23. by tynli.
++ // (2) Enable HW SEQ control for beacon packet, because we use Hw beacon.
++ // (3) Use HW Qos SEQ to control the seq num of Ext port non-Qos packets.
++ // 2010.06.23. Added by tynli.
++ if(!pattrib->qos_en)
++ {
++ ptxdesc->txdw4 |= cpu_to_le32(BIT(7)); // Hw set sequence number
++ ptxdesc->txdw3 |= cpu_to_le32((8 <<28)); //set bit3 to 1. Suugested by TimChen. 2009.12.29.
++ }
++
++ //offset 0
++ ptxdesc->txdw0 |= cpu_to_le32(sz&0x0000ffff);
++ ptxdesc->txdw0 |= cpu_to_le32(OWN | FSG | LSG);
++ ptxdesc->txdw0 |= cpu_to_le32(((TXDESC_SIZE+OFFSET_SZ)<<OFFSET_SHT)&0x00ff0000);//32 bytes for TX Desc
++
++ if(bmcst)
++ {
++ ptxdesc->txdw0 |= cpu_to_le32(BIT(24));
++ }
++
++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("offset0-txdesc=0x%x\n", ptxdesc->txdw0));
++
++ //offset 4
++ // pkt_offset, unit:8 bytes padding
++ if (pxmitframe->pkt_offset > 0)
++ ptxdesc->txdw1 |= cpu_to_le32((pxmitframe->pkt_offset << 26) & 0x7c000000);
++
++#ifdef CONFIG_USB_TX_AGGREGATION
++ if (pxmitframe->agg_num > 1)
++ ptxdesc->txdw5 |= cpu_to_le32((pxmitframe->agg_num << 24) & 0xff000000);
++#endif
++
++ rtl8192cu_cal_txdesc_chksum(ptxdesc);
++
++ return pull;
++
++}
++
++static s32 rtw_dump_xframe(_adapter *padapter, struct xmit_frame *pxmitframe)
++{
++ s32 ret = _SUCCESS;
++ s32 inner_ret = _SUCCESS;
++ int t, sz, w_sz, pull=0;
++ u8 *mem_addr;
++ u32 ff_hwaddr;
++ struct xmit_buf *pxmitbuf = pxmitframe->pxmitbuf;
++ struct pkt_attrib *pattrib = &pxmitframe->attrib;
++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++ struct security_priv *psecuritypriv = &padapter->securitypriv;
++
++ if ((pxmitframe->frame_tag == DATA_FRAMETAG) &&
++ (pxmitframe->attrib.ether_type != 0x0806) &&
++ (pxmitframe->attrib.ether_type != 0x888e) &&
++ (pxmitframe->attrib.dhcp_pkt != 1))
++ {
++ rtw_issue_addbareq_cmd(padapter, pxmitframe);
++ }
++
++ mem_addr = pxmitframe->buf_addr;
++
++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("rtw_dump_xframe()\n"));
++
++ for (t = 0; t < pattrib->nr_frags; t++)
++ {
++ if (inner_ret != _SUCCESS && ret == _SUCCESS)
++ ret = _FAIL;
++
++ if (t != (pattrib->nr_frags - 1))
++ {
++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("pattrib->nr_frags=%d\n", pattrib->nr_frags));
++
++ sz = pxmitpriv->frag_len;
++ sz = sz - 4 - (psecuritypriv->sw_encrypt ? 0 : pattrib->icv_len);
++ }
++ else //no frag
++ {
++ sz = pattrib->last_txcmdsz;
++ }
++
++ pull = update_txdesc(pxmitframe, mem_addr, sz, _FALSE);
++
++ if(pull)
++ {
++ mem_addr += PACKET_OFFSET_SZ; //pull txdesc head
++
++ //pxmitbuf ->pbuf = mem_addr;
++ pxmitframe->buf_addr = mem_addr;
++
++ w_sz = sz + TXDESC_SIZE;
++ }
++ else
++ {
++ w_sz = sz + TXDESC_SIZE + PACKET_OFFSET_SZ;
++ }
++
++ ff_hwaddr = rtw_get_ff_hwaddr(pxmitframe);
++
++ inner_ret = rtw_write_port(padapter, ff_hwaddr, w_sz, (unsigned char*)pxmitbuf);
++
++ rtw_count_tx_stats(padapter, pxmitframe, sz);
++
++
++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("rtw_write_port, w_sz=%d\n", w_sz));
++ //DBG_8192C("rtw_write_port, w_sz=%d, sz=%d, txdesc_sz=%d, tid=%d\n", w_sz, sz, w_sz-sz, pattrib->priority);
++
++ mem_addr += w_sz;
++
++ mem_addr = (u8 *)RND4(((SIZE_PTR)(mem_addr)));
++
++ }
++
++ rtw_free_xmitframe(pxmitpriv, pxmitframe);
++
++ if (ret != _SUCCESS)
++ rtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_UNKNOWN);
++
++ return ret;
++}
++
++#ifdef CONFIG_USB_TX_AGGREGATION
++static u32 xmitframe_need_length(struct xmit_frame *pxmitframe)
++{
++ struct pkt_attrib *pattrib = &pxmitframe->attrib;
++
++ u32 len = 0;
++
++ // no consider fragement
++ len = pattrib->hdrlen + pattrib->iv_len +
++ SNAP_SIZE + sizeof(u16) +
++ pattrib->pktlen +
++ ((pattrib->bswenc) ? pattrib->icv_len : 0);
++
++ if(pattrib->encrypt ==_TKIP_)
++ len += 8;
++
++ return len;
++}
++
++#define IDEA_CONDITION 1 // check all packets before enqueue
++s32 rtl8192cu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++ struct xmit_frame *pxmitframe = NULL;
++ struct xmit_frame *pfirstframe = NULL;
++
++ // aggregate variable
++ struct hw_xmit *phwxmit;
++ struct sta_info *psta = NULL;
++ struct tx_servq *ptxservq = NULL;
++
++ _irqL irqL;
++ _list *xmitframe_plist = NULL, *xmitframe_phead = NULL;
++
++ u32 pbuf; // next pkt address
++ u32 pbuf_tail; // last pkt tail
++ u32 len; // packet length, except TXDESC_SIZE and PKT_OFFSET
++
++ u32 bulkSize = pHalData->UsbBulkOutSize;
++ u8 descCount;
++ u32 bulkPtr;
++
++ // dump frame variable
++ u32 ff_hwaddr;
++
++#ifndef IDEA_CONDITION
++ int res = _SUCCESS;
++#endif
++
++ RT_TRACE(_module_rtl8192c_xmit_c_, _drv_info_, ("+xmitframe_complete\n"));
++
++
++ // check xmitbuffer is ok
++ if (pxmitbuf == NULL) {
++ pxmitbuf = rtw_alloc_xmitbuf(pxmitpriv);
++ if (pxmitbuf == NULL) return _FALSE;
++ }
++
++
++ //3 1. pick up first frame
++ do {
++ rtw_free_xmitframe(pxmitpriv, pxmitframe);
++
++ pxmitframe = rtw_dequeue_xframe(pxmitpriv, pxmitpriv->hwxmits, pxmitpriv->hwxmit_entry);
++ if (pxmitframe == NULL) {
++ // no more xmit frame, release xmit buffer
++ rtw_free_xmitbuf(pxmitpriv, pxmitbuf);
++ return _FALSE;
++ }
++
++
++#ifndef IDEA_CONDITION
++ if (pxmitframe->frame_tag != DATA_FRAMETAG) {
++ RT_TRACE(_module_rtl8192c_xmit_c_, _drv_err_,
++ ("xmitframe_complete: frame tag(%d) is not DATA_FRAMETAG(%d)!\n",
++ pxmitframe->frame_tag, DATA_FRAMETAG));
++// rtw_free_xmitframe(pxmitpriv, pxmitframe);
++ continue;
++ }
++
++ // TID 0~15
++ if ((pxmitframe->attrib.priority < 0) ||
++ (pxmitframe->attrib.priority > 15)) {
++ RT_TRACE(_module_rtl8192c_xmit_c_, _drv_err_,
++ ("xmitframe_complete: TID(%d) should be 0~15!\n",
++ pxmitframe->attrib.priority));
++// rtw_free_xmitframe(pxmitpriv, pxmitframe);
++ continue;
++ }
++#endif
++
++ pxmitframe->pxmitbuf = pxmitbuf;
++ pxmitframe->buf_addr = pxmitbuf->pbuf;
++ pxmitbuf->priv_data = pxmitframe;
++
++ //pxmitframe->agg_num = 1; // alloc xmitframe should assign to 1.
++ pxmitframe->pkt_offset = 1; // first frame of aggregation, reserve offset
++
++
++ if (rtw_xmitframe_coalesce(padapter, pxmitframe->pkt, pxmitframe) == _FALSE) {
++ DBG_871X("%s coalesce 1st xmitframe failed \n",__FUNCTION__);
++ continue;
++ }
++
++
++ // always return ndis_packet after rtw_xmitframe_coalesce
++ rtw_os_xmit_complete(padapter, pxmitframe);
++
++ break;
++ } while (1);
++
++ //3 2. aggregate same priority and same DA(AP or STA) frames
++ pfirstframe = pxmitframe;
++ len = xmitframe_need_length(pfirstframe) + TXDESC_OFFSET;
++ pbuf_tail = len;
++ pbuf = _RND8(pbuf_tail);
++
++ // check pkt amount in one bluk
++ descCount = 0;
++ bulkPtr = bulkSize;
++ if (pbuf < bulkPtr)
++ descCount++;
++ else {
++ descCount = 0;
++ bulkPtr = ((pbuf / bulkSize) + 1) * bulkSize; // round to next bulkSize
++ }
++
++ // dequeue same priority packet from station tx queue
++ psta = pfirstframe->attrib.psta;
++ switch (pfirstframe->attrib.priority) {
++ case 1:
++ case 2:
++ ptxservq = &(psta->sta_xmitpriv.bk_q);
++ phwxmit = pxmitpriv->hwxmits + 3;
++ break;
++
++ case 4:
++ case 5:
++ ptxservq = &(psta->sta_xmitpriv.vi_q);
++ phwxmit = pxmitpriv->hwxmits + 1;
++ break;
++
++ case 6:
++ case 7:
++ ptxservq = &(psta->sta_xmitpriv.vo_q);
++ phwxmit = pxmitpriv->hwxmits;
++ break;
++
++ case 0:
++ case 3:
++ default:
++ ptxservq = &(psta->sta_xmitpriv.be_q);
++ phwxmit = pxmitpriv->hwxmits + 2;
++ break;
++ }
++
++ _enter_critical_bh(&pxmitpriv->lock, &irqL);
++
++ xmitframe_phead = get_list_head(&ptxservq->sta_pending);
++ xmitframe_plist = get_next(xmitframe_phead);
++ while (rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist) == _FALSE)
++ {
++ pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list);
++ xmitframe_plist = get_next(xmitframe_plist);
++
++ len = xmitframe_need_length(pxmitframe) + TXDESC_SIZE; // no offset
++ if (pbuf + len > MAX_XMITBUF_SZ) break;
++
++ rtw_list_delete(&pxmitframe->list);
++ ptxservq->qcnt--;
++ phwxmit->accnt--;
++
++#ifndef IDEA_CONDITION
++ // suppose only data frames would be in queue
++ if (pxmitframe->frame_tag != DATA_FRAMETAG) {
++ RT_TRACE(_module_rtl8192c_xmit_c_, _drv_err_,
++ ("xmitframe_complete: frame tag(%d) is not DATA_FRAMETAG(%d)!\n",
++ pxmitframe->frame_tag, DATA_FRAMETAG));
++ rtw_free_xmitframe(pxmitpriv, pxmitframe);
++ continue;
++ }
++
++ // TID 0~15
++ if ((pxmitframe->attrib.priority < 0) ||
++ (pxmitframe->attrib.priority > 15)) {
++ RT_TRACE(_module_rtl8192c_xmit_c_, _drv_err_,
++ ("xmitframe_complete: TID(%d) should be 0~15!\n",
++ pxmitframe->attrib.priority));
++ rtw_free_xmitframe(pxmitpriv, pxmitframe);
++ continue;
++ }
++#endif
++
++// pxmitframe->pxmitbuf = pxmitbuf;
++ pxmitframe->buf_addr = pxmitbuf->pbuf + pbuf;
++
++ pxmitframe->agg_num = 0; // not first frame of aggregation
++ pxmitframe->pkt_offset = 0; // not first frame of aggregation, no need to reserve offset
++
++ if (rtw_xmitframe_coalesce(padapter, pxmitframe->pkt, pxmitframe) == _FALSE) {
++ DBG_871X("%s coalesce failed \n",__FUNCTION__);
++ rtw_free_xmitframe(pxmitpriv, pxmitframe);
++ continue;
++ }
++
++ // always return ndis_packet after rtw_xmitframe_coalesce
++ rtw_os_xmit_complete(padapter, pxmitframe);
++
++ // (len - TXDESC_SIZE) == pxmitframe->attrib.last_txcmdsz
++ update_txdesc(pxmitframe, pxmitframe->buf_addr, pxmitframe->attrib.last_txcmdsz, _TRUE);
++
++ // don't need xmitframe any more
++ rtw_free_xmitframe(pxmitpriv, pxmitframe);
++
++ // handle pointer and stop condition
++ pbuf_tail = pbuf + len;
++ pbuf = _RND8(pbuf_tail);
++
++ pfirstframe->agg_num++;
++ if (MAX_TX_AGG_PACKET_NUMBER == pfirstframe->agg_num)
++ break;
++
++ if (pbuf < bulkPtr) {
++ descCount++;
++ if (descCount == pHalData->UsbTxAggDescNum)
++ break;
++ } else {
++ descCount = 0;
++ bulkPtr = ((pbuf / bulkSize) + 1) * bulkSize;
++ }
++ }
++ if (_rtw_queue_empty(&ptxservq->sta_pending) == _TRUE)
++ rtw_list_delete(&ptxservq->tx_pending);
++
++ _exit_critical_bh(&pxmitpriv->lock, &irqL);
++
++ if ((pfirstframe->attrib.ether_type != 0x0806) &&
++ (pfirstframe->attrib.ether_type != 0x888e) &&
++ (pfirstframe->attrib.dhcp_pkt != 1))
++ {
++ rtw_issue_addbareq_cmd(padapter, pfirstframe);
++ }
++
++#ifndef CONFIG_USE_USB_BUFFER_ALLOC_TX
++ //3 3. update first frame txdesc
++ if ((pbuf_tail % bulkSize) == 0) {
++ // remove pkt_offset
++ pbuf_tail -= PACKET_OFFSET_SZ;
++ pfirstframe->buf_addr += PACKET_OFFSET_SZ;
++ pfirstframe->pkt_offset = 0;
++ }
++#endif // CONFIG_USE_USB_BUFFER_ALLOC_TX
++ update_txdesc(pfirstframe, pfirstframe->buf_addr, pfirstframe->attrib.last_txcmdsz, _TRUE);
++
++ //3 4. write xmit buffer to USB FIFO
++ ff_hwaddr = rtw_get_ff_hwaddr(pfirstframe);
++
++ // xmit address == ((xmit_frame*)pxmitbuf->priv_data)->buf_addr
++ rtw_write_port(padapter, ff_hwaddr, pbuf_tail, (u8*)pxmitbuf);
++
++
++ //3 5. update statisitc
++ pbuf_tail -= (pfirstframe->agg_num * TXDESC_SIZE);
++ if (pfirstframe->pkt_offset == 1) pbuf_tail -= PACKET_OFFSET_SZ;
++
++ rtw_count_tx_stats(padapter, pfirstframe, pbuf_tail);
++
++ rtw_free_xmitframe(pxmitpriv, pfirstframe);
++
++ return _TRUE;
++}
++
++#else
++
++s32 rtl8192cu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf)
++{
++
++ struct hw_xmit *phwxmits;
++ sint hwentry;
++ struct xmit_frame *pxmitframe=NULL;
++ int res=_SUCCESS, xcnt = 0;
++
++ phwxmits = pxmitpriv->hwxmits;
++ hwentry = pxmitpriv->hwxmit_entry;
++
++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("xmitframe_complete()\n"));
++
++ if(pxmitbuf==NULL)
++ {
++ pxmitbuf = rtw_alloc_xmitbuf(pxmitpriv);
++ if(!pxmitbuf)
++ {
++ return _FALSE;
++ }
++ }
++
++
++ do
++ {
++ pxmitframe = rtw_dequeue_xframe(pxmitpriv, phwxmits, hwentry);
++
++ if(pxmitframe)
++ {
++ pxmitframe->pxmitbuf = pxmitbuf;
++
++ pxmitframe->buf_addr = pxmitbuf->pbuf;
++
++ pxmitbuf->priv_data = pxmitframe;
++
++ if((pxmitframe->frame_tag&0x0f) == DATA_FRAMETAG)
++ {
++ if(pxmitframe->attrib.priority<=15)//TID0~15
++ {
++ res = rtw_xmitframe_coalesce(padapter, pxmitframe->pkt, pxmitframe);
++ }
++
++ rtw_os_xmit_complete(padapter, pxmitframe);//always return ndis_packet after rtw_xmitframe_coalesce
++ }
++
++
++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("xmitframe_complete(): rtw_dump_xframe\n"));
++
++
++ if(res == _SUCCESS)
++ {
++ rtw_dump_xframe(padapter, pxmitframe);
++ }
++ else
++ {
++ rtw_free_xmitbuf(pxmitpriv, pxmitbuf);
++ rtw_free_xmitframe(pxmitpriv, pxmitframe);
++ }
++
++ xcnt++;
++
++ }
++ else
++ {
++ rtw_free_xmitbuf(pxmitpriv, pxmitbuf);
++ return _FALSE;
++ }
++
++ break;
++
++ }while(0/*xcnt < (NR_XMITFRAME >> 3)*/);
++
++ return _TRUE;
++
++}
++#endif
++
++
++
++static s32 xmitframe_direct(_adapter *padapter, struct xmit_frame *pxmitframe)
++{
++ s32 res = _SUCCESS;
++
++
++ res = rtw_xmitframe_coalesce(padapter, pxmitframe->pkt, pxmitframe);
++ if (res == _SUCCESS) {
++ rtw_dump_xframe(padapter, pxmitframe);
++ }
++
++ return res;
++}
++
++/*
++ * Return
++ * _TRUE dump packet directly
++ * _FALSE enqueue packet
++ */
++static s32 pre_xmitframe(_adapter *padapter, struct xmit_frame *pxmitframe)
++{
++ _irqL irqL;
++ s32 res;
++ struct xmit_buf *pxmitbuf = NULL;
++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++ struct pkt_attrib *pattrib = &pxmitframe->attrib;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++
++
++ _enter_critical_bh(&pxmitpriv->lock, &irqL);
++
++
++ if (rtw_txframes_sta_ac_pending(padapter, pattrib) > 0)
++ goto enqueue;
++
++
++ if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY|_FW_UNDER_LINKING) == _TRUE)
++ goto enqueue;
++
++#ifdef CONFIG_CONCURRENT_MODE
++ if (check_buddy_fwstate(padapter, _FW_UNDER_SURVEY|_FW_UNDER_LINKING) == _TRUE)
++ goto enqueue;
++#endif
++
++ pxmitbuf = rtw_alloc_xmitbuf(pxmitpriv);
++ if (pxmitbuf == NULL)
++ goto enqueue;
++
++ _exit_critical_bh(&pxmitpriv->lock, &irqL);
++
++ pxmitframe->pxmitbuf = pxmitbuf;
++ pxmitframe->buf_addr = pxmitbuf->pbuf;
++ pxmitbuf->priv_data = pxmitframe;
++
++ if (xmitframe_direct(padapter, pxmitframe) != _SUCCESS) {
++ rtw_free_xmitbuf(pxmitpriv, pxmitbuf);
++ rtw_free_xmitframe(pxmitpriv, pxmitframe);
++ }
++
++ return _TRUE;
++
++enqueue:
++ res = rtw_xmitframe_enqueue(padapter, pxmitframe);
++ _exit_critical_bh(&pxmitpriv->lock, &irqL);
++
++ if (res != _SUCCESS) {
++ RT_TRACE(_module_xmit_osdep_c_, _drv_err_, ("pre_xmitframe: enqueue xmitframe fail\n"));
++ rtw_free_xmitframe(pxmitpriv, pxmitframe);
++
++ // Trick, make the statistics correct
++ pxmitpriv->tx_pkts--;
++ pxmitpriv->tx_drop++;
++ return _TRUE;
++ }
++
++ return _FALSE;
++}
++
++s32 rtl8192cu_mgnt_xmit(_adapter *padapter, struct xmit_frame *pmgntframe)
++{
++ return rtw_dump_xframe(padapter, pmgntframe);
++}
++
++/*
++ * Return
++ * _TRUE dump packet directly ok
++ * _FALSE temporary can't transmit packets to hardware
++ */
++s32 rtl8192cu_hal_xmit(_adapter *padapter, struct xmit_frame *pxmitframe)
++{
++ return pre_xmitframe(padapter, pxmitframe);
++}
++
++s32 rtl8192cu_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe)
++{
++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++ s32 err;
++
++ if ((err=rtw_xmitframe_enqueue(padapter, pxmitframe)) != _SUCCESS)
++ {
++ rtw_free_xmitframe(pxmitpriv, pxmitframe);
++
++ // Trick, make the statistics correct
++ pxmitpriv->tx_pkts--;
++ pxmitpriv->tx_drop++;
++ }
++ else
++ {
++#ifdef PLATFORM_LINUX
++ tasklet_hi_schedule(&pxmitpriv->xmit_tasklet);
++#endif
++ }
++
++ return err;
++
++}
++
++#ifdef CONFIG_HOSTAPD_MLME
++
++static void rtl8192cu_hostap_mgnt_xmit_cb(struct urb *urb)
++{
++#ifdef PLATFORM_LINUX
++ struct sk_buff *skb = (struct sk_buff *)urb->context;
++
++ //DBG_8192C("%s\n", __FUNCTION__);
++
++ rtw_skb_free(skb);
++#endif
++}
++
++s32 rtl8192cu_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt)
++{
++#ifdef PLATFORM_LINUX
++ u16 fc;
++ int rc, len, pipe;
++ unsigned int bmcst, tid, qsel;
++ struct sk_buff *skb, *pxmit_skb;
++ struct urb *urb;
++ unsigned char *pxmitbuf;
++ struct tx_desc *ptxdesc;
++ struct rtw_ieee80211_hdr *tx_hdr;
++ struct hostapd_priv *phostapdpriv = padapter->phostapdpriv;
++ struct net_device *pnetdev = padapter->pnetdev;
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++ struct dvobj_priv *pdvobj = adapter_to_dvobj(padapter);
++
++
++ //DBG_8192C("%s\n", __FUNCTION__);
++
++ skb = pkt;
++
++ len = skb->len;
++ tx_hdr = (struct rtw_ieee80211_hdr *)(skb->data);
++ fc = le16_to_cpu(tx_hdr->frame_ctl);
++ bmcst = IS_MCAST(tx_hdr->addr1);
++
++ if ((fc & RTW_IEEE80211_FCTL_FTYPE) != RTW_IEEE80211_FTYPE_MGMT)
++ goto _exit;
++
++ pxmit_skb = rtw_skb_alloc(len + TXDESC_SIZE);
++
++ if(!pxmit_skb)
++ goto _exit;
++
++ pxmitbuf = pxmit_skb->data;
++
++ urb = usb_alloc_urb(0, GFP_ATOMIC);
++ if (!urb) {
++ goto _exit;
++ }
++
++ // ----- fill tx desc -----
++ ptxdesc = (struct tx_desc *)pxmitbuf;
++ _rtw_memset(ptxdesc, 0, sizeof(*ptxdesc));
++
++ //offset 0
++ ptxdesc->txdw0 |= cpu_to_le32(len&0x0000ffff);
++ ptxdesc->txdw0 |= cpu_to_le32(((TXDESC_SIZE+OFFSET_SZ)<<OFFSET_SHT)&0x00ff0000);//default = 32 bytes for TX Desc
++ ptxdesc->txdw0 |= cpu_to_le32(OWN | FSG | LSG);
++
++ if(bmcst)
++ {
++ ptxdesc->txdw0 |= cpu_to_le32(BIT(24));
++ }
++
++ //offset 4
++ ptxdesc->txdw1 |= cpu_to_le32(0x00);//MAC_ID
++
++ ptxdesc->txdw1 |= cpu_to_le32((0x12<<QSEL_SHT)&0x00001f00);
++
++ ptxdesc->txdw1 |= cpu_to_le32((0x06<< 16) & 0x000f0000);//b mode
++
++ //offset 8
++
++ //offset 12
++ ptxdesc->txdw3 |= cpu_to_le32((le16_to_cpu(tx_hdr->seq_ctl)<<16)&0xffff0000);
++
++ //offset 16
++ ptxdesc->txdw4 |= cpu_to_le32(BIT(8));//driver uses rate
++
++ //offset 20
++
++
++ //HW append seq
++ ptxdesc->txdw4 |= cpu_to_le32(BIT(7)); // Hw set sequence number
++ ptxdesc->txdw3 |= cpu_to_le32((8 <<28)); //set bit3 to 1. Suugested by TimChen. 2009.12.29.
++
++
++ rtl8192cu_cal_txdesc_chksum(ptxdesc);
++ // ----- end of fill tx desc -----
++
++ //
++ skb_put(pxmit_skb, len + TXDESC_SIZE);
++ pxmitbuf = pxmitbuf + TXDESC_SIZE;
++ _rtw_memcpy(pxmitbuf, skb->data, len);
++
++ //DBG_8192C("mgnt_xmit, len=%x\n", pxmit_skb->len);
++
++
++ // ----- prepare urb for submit -----
++
++ //translate DMA FIFO addr to pipehandle
++ //pipe = ffaddr2pipehdl(pdvobj, MGT_QUEUE_INX);
++ pipe = usb_sndbulkpipe(pdvobj->pusbdev, pHalData->Queue2EPNum[(u8)MGT_QUEUE_INX]&0x0f);
++
++ usb_fill_bulk_urb(urb, pdvobj->pusbdev, pipe,
++ pxmit_skb->data, pxmit_skb->len, rtl8192cu_hostap_mgnt_xmit_cb, pxmit_skb);
++
++ urb->transfer_flags |= URB_ZERO_PACKET;
++ usb_anchor_urb(urb, &phostapdpriv->anchored);
++ rc = usb_submit_urb(urb, GFP_ATOMIC);
++ if (rc < 0) {
++ usb_unanchor_urb(urb);
++ kfree_skb(skb);
++ }
++ usb_free_urb(urb);
++
++
++_exit:
++
++ rtw_skb_free(skb);
++
++#endif
++
++ return 0;
++
++}
++#endif
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/hal/rtl8192c/usb/usb_halinit.c linux-xbian-rpi/drivers/net/wireless/rtl8192cu/hal/rtl8192c/usb/usb_halinit.c
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/hal/rtl8192c/usb/usb_halinit.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/hal/rtl8192c/usb/usb_halinit.c 2015-07-28 01:20:58.313625760 +0200
+@@ -0,0 +1,6260 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#define _HCI_HAL_INIT_C_
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++#include <rtw_efuse.h>
++
++#include <rtl8192c_hal.h>
++#include <rtl8192c_led.h>
++
++#ifdef DBG_CONFIG_ERROR_DETECT
++#include "rtl8192c_sreset.h"
++#endif
++
++#ifdef CONFIG_IOL
++#include <rtw_iol.h>
++#endif
++
++#if defined (PLATFORM_LINUX) && defined (PLATFORM_WINDOWS)
++
++#error "Shall be Linux or Windows, but not both!\n"
++
++#endif
++
++#ifndef CONFIG_USB_HCI
++
++#error "CONFIG_USB_HCI shall be on!\n"
++
++#endif
++
++#include <usb_ops.h>
++#include <usb_hal.h>
++#include <usb_osintf.h>
++
++#if DISABLE_BB_RF
++ #define HAL_MAC_ENABLE 0
++ #define HAL_BB_ENABLE 0
++ #define HAL_RF_ENABLE 0
++#else
++ #define HAL_MAC_ENABLE 1
++ #define HAL_BB_ENABLE 1
++ #define HAL_RF_ENABLE 1
++#endif
++
++//endpoint number 1,2,3,4,5
++// bult in : 1
++// bult out: 2 (High)
++// bult out: 3 (Normal) for 3 out_ep, (Low) for 2 out_ep
++// interrupt in: 4
++// bult out: 5 (Low) for 3 out_ep
++
++
++static VOID
++_OneOutEpMapping(
++ IN HAL_DATA_TYPE *pHalData
++ )
++{
++ //only endpoint number 0x02
++
++ pHalData->Queue2EPNum[0] = pHalData->RtBulkOutPipe[0];//VO
++ pHalData->Queue2EPNum[1] = pHalData->RtBulkOutPipe[0];//VI
++ pHalData->Queue2EPNum[2] = pHalData->RtBulkOutPipe[0];//BE
++ pHalData->Queue2EPNum[3] = pHalData->RtBulkOutPipe[0];//BK
++
++ pHalData->Queue2EPNum[4] = pHalData->RtBulkOutPipe[0];//BCN
++ pHalData->Queue2EPNum[5] = pHalData->RtBulkOutPipe[0];//MGT
++ pHalData->Queue2EPNum[6] = pHalData->RtBulkOutPipe[0];//HIGH
++ pHalData->Queue2EPNum[7] = pHalData->RtBulkOutPipe[0];//TXCMD
++}
++
++
++static VOID
++_TwoOutEpMapping(
++ IN HAL_DATA_TYPE *pHalData,
++ IN BOOLEAN bWIFICfg
++ )
++{
++
++/*
++#define VO_QUEUE_INX 0
++#define VI_QUEUE_INX 1
++#define BE_QUEUE_INX 2
++#define BK_QUEUE_INX 3
++#define BCN_QUEUE_INX 4
++#define MGT_QUEUE_INX 5
++#define HIGH_QUEUE_INX 6
++#define TXCMD_QUEUE_INX 7
++*/
++ if(bWIFICfg){ // Normal chip && wmm
++
++ // BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA
++ //{ 0, 1, 0, 1, 0, 0, 0, 0, 0 };
++ //0:H(end_number=0x02), 1:L (end_number=0x03)
++
++ pHalData->Queue2EPNum[0] = pHalData->RtBulkOutPipe[1];//VO
++ pHalData->Queue2EPNum[1] = pHalData->RtBulkOutPipe[0];//VI
++ pHalData->Queue2EPNum[2] = pHalData->RtBulkOutPipe[1];//BE
++ pHalData->Queue2EPNum[3] = pHalData->RtBulkOutPipe[0];//BK
++
++ pHalData->Queue2EPNum[4] = pHalData->RtBulkOutPipe[0];//BCN
++ pHalData->Queue2EPNum[5] = pHalData->RtBulkOutPipe[0];//MGT
++ pHalData->Queue2EPNum[6] = pHalData->RtBulkOutPipe[0];//HIGH
++ pHalData->Queue2EPNum[7] = pHalData->RtBulkOutPipe[0];//TXCMD
++ }
++ else{//typical setting
++
++ //BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA
++ //{ 1, 1, 0, 0, 0, 0, 0, 0, 0 };
++ //0:H(end_number=0x02), 1:L (end_number=0x03)
++
++ pHalData->Queue2EPNum[0] = pHalData->RtBulkOutPipe[0];//VO
++ pHalData->Queue2EPNum[1] = pHalData->RtBulkOutPipe[0];//VI
++ pHalData->Queue2EPNum[2] = pHalData->RtBulkOutPipe[1];//BE
++ pHalData->Queue2EPNum[3] = pHalData->RtBulkOutPipe[1];//BK
++
++ pHalData->Queue2EPNum[4] = pHalData->RtBulkOutPipe[0];//BCN
++ pHalData->Queue2EPNum[5] = pHalData->RtBulkOutPipe[0];//MGT
++ pHalData->Queue2EPNum[6] = pHalData->RtBulkOutPipe[0];//HIGH
++ pHalData->Queue2EPNum[7] = pHalData->RtBulkOutPipe[0];//TXCMD
++ }
++
++}
++
++
++static VOID _ThreeOutEpMapping(
++ IN HAL_DATA_TYPE *pHalData,
++ IN BOOLEAN bWIFICfg
++ )
++{
++ if(bWIFICfg){//for WMM
++
++ // BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA
++ //{ 1, 2, 1, 0, 0, 0, 0, 0, 0 };
++ //0:H(end_number=0x02), 1:N(end_number=0x03), 2:L (end_number=0x05)
++
++ pHalData->Queue2EPNum[0] = pHalData->RtBulkOutPipe[0];//VO
++ pHalData->Queue2EPNum[1] = pHalData->RtBulkOutPipe[1];//VI
++ pHalData->Queue2EPNum[2] = pHalData->RtBulkOutPipe[2];//BE
++ pHalData->Queue2EPNum[3] = pHalData->RtBulkOutPipe[1];//BK
++
++ pHalData->Queue2EPNum[4] = pHalData->RtBulkOutPipe[0];//BCN
++ pHalData->Queue2EPNum[5] = pHalData->RtBulkOutPipe[0];//MGT
++ pHalData->Queue2EPNum[6] = pHalData->RtBulkOutPipe[0];//HIGH
++ pHalData->Queue2EPNum[7] = pHalData->RtBulkOutPipe[0];//TXCMD
++ }
++ else{//typical setting
++
++ // BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA
++ //{ 2, 2, 1, 0, 0, 0, 0, 0, 0 };
++ //0:H(end_number=0x02), 1:N(end_number=0x03), 2:L (end_number=0x05)
++ pHalData->Queue2EPNum[0] = pHalData->RtBulkOutPipe[0];//VO
++ pHalData->Queue2EPNum[1] = pHalData->RtBulkOutPipe[1];//VI
++ pHalData->Queue2EPNum[2] = pHalData->RtBulkOutPipe[2];//BE
++ pHalData->Queue2EPNum[3] = pHalData->RtBulkOutPipe[2];//BK
++
++ pHalData->Queue2EPNum[4] = pHalData->RtBulkOutPipe[0];//BCN
++ pHalData->Queue2EPNum[5] = pHalData->RtBulkOutPipe[0];//MGT
++ pHalData->Queue2EPNum[6] = pHalData->RtBulkOutPipe[0];//HIGH
++ pHalData->Queue2EPNum[7] = pHalData->RtBulkOutPipe[0];//TXCMD
++ }
++
++}
++
++static BOOLEAN
++_MappingOutEP(
++ IN PADAPTER pAdapter,
++ IN u8 NumOutPipe
++ )
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
++ struct registry_priv *pregistrypriv = &pAdapter->registrypriv;
++
++ BOOLEAN bWIFICfg = (pregistrypriv->wifi_spec) ?_TRUE:_FALSE;
++
++ BOOLEAN result = _TRUE;
++
++ switch(NumOutPipe)
++ {
++ case 2:
++ _TwoOutEpMapping(pHalData, bWIFICfg);
++ break;
++ case 3:
++ _ThreeOutEpMapping(pHalData, bWIFICfg);
++ break;
++ case 1:
++ _OneOutEpMapping(pHalData);
++ break;
++ default:
++ result = _FALSE;
++ break;
++ }
++
++ return result;
++
++}
++
++static VOID
++_ConfigChipOutEP(
++ IN PADAPTER pAdapter,
++ IN u8 NumOutPipe
++ )
++{
++ u8 value8;
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
++
++ pHalData->OutEpQueueSel = 0;
++ pHalData->OutEpNumber = 0;
++
++ // Normal and High queue
++ value8 = rtw_read8(pAdapter, (REG_NORMAL_SIE_EP + 1));
++
++ if(value8 & USB_NORMAL_SIE_EP_MASK){
++ pHalData->OutEpQueueSel |= TX_SELE_HQ;
++ pHalData->OutEpNumber++;
++ }
++
++#ifdef CONFIG_USB_ONE_OUT_EP
++ return;
++#endif
++
++ if((value8 >> USB_NORMAL_SIE_EP_SHIFT) & USB_NORMAL_SIE_EP_MASK){
++ pHalData->OutEpQueueSel |= TX_SELE_NQ;
++ pHalData->OutEpNumber++;
++ }
++
++ // Low queue
++ value8 = rtw_read8(pAdapter, (REG_NORMAL_SIE_EP + 2));
++ if(value8 & USB_NORMAL_SIE_EP_MASK){
++ pHalData->OutEpQueueSel |= TX_SELE_LQ;
++ pHalData->OutEpNumber++;
++ }
++
++ // TODO: Error recovery for this case
++ //RT_ASSERT((NumOutPipe == pHalData->OutEpNumber), ("Out EP number isn't match! %d(Descriptor) != %d (SIE reg)\n", (u4Byte)NumOutPipe, (u4Byte)pHalData->OutEpNumber));
++
++}
++
++static BOOLEAN HalUsbSetQueuePipeMapping8192CUsb(
++ IN PADAPTER pAdapter,
++ IN u8 NumInPipe,
++ IN u8 NumOutPipe
++ )
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
++ BOOLEAN result = _FALSE;
++
++ _ConfigChipOutEP(pAdapter, NumOutPipe);
++
++ #ifndef CONFIG_USB_ONE_OUT_EP
++ // Normal chip with one IN and one OUT doesn't have interrupt IN EP.
++ if(1 == pHalData->OutEpNumber){
++ if(1 != NumInPipe){
++ return result;
++ }
++ }
++ #endif
++ result = _MappingOutEP(pAdapter, NumOutPipe);
++
++ return result;
++
++}
++
++void rtl8192cu_interface_configure(_adapter *padapter)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++ struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
++
++ if (pdvobjpriv->ishighspeed == _TRUE)
++ {
++ pHalData->UsbBulkOutSize = USB_HIGH_SPEED_BULK_SIZE;//512 bytes
++ }
++ else
++ {
++ pHalData->UsbBulkOutSize = USB_FULL_SPEED_BULK_SIZE;//64 bytes
++ }
++
++ pHalData->interfaceIndex = pdvobjpriv->InterfaceNumber;
++ pHalData->RtBulkInPipe = pdvobjpriv->ep_num[0];
++ pHalData->RtBulkOutPipe[0] = pdvobjpriv->ep_num[1];
++ pHalData->RtBulkOutPipe[1] = pdvobjpriv->ep_num[2];
++ pHalData->RtIntInPipe = pdvobjpriv->ep_num[3];
++ pHalData->RtBulkOutPipe[2] = pdvobjpriv->ep_num[4];
++
++#ifdef CONFIG_USB_TX_AGGREGATION
++ pHalData->UsbTxAggMode = 1;
++ pHalData->UsbTxAggDescNum = 0x6; // only 4 bits
++#endif
++
++#ifdef CONFIG_USB_RX_AGGREGATION
++ pHalData->UsbRxAggMode = USB_RX_AGG_DMA;// USB_RX_AGG_DMA;
++ pHalData->UsbRxAggBlockCount = 8; //unit : 512b
++ pHalData->UsbRxAggBlockTimeout = 0x6;
++ pHalData->UsbRxAggPageCount = 48; //uint :128 b //0x0A; // 10 = MAX_RX_DMA_BUFFER_SIZE/2/pHalData->UsbBulkOutSize
++ pHalData->UsbRxAggPageTimeout = 0x4; //6, absolute time = 34ms/(2^6)
++#endif
++
++ HalUsbSetQueuePipeMapping8192CUsb(padapter, pdvobjpriv->RtNumInPipes,
++ #ifdef CONFIG_USB_ONE_OUT_EP
++ 1
++ #else
++ pdvobjpriv->RtNumOutPipes
++ #endif
++ );
++
++}
++
++static u8 _InitPowerOn(_adapter *padapter)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++ u8 ret = _SUCCESS;
++ u16 value16=0;
++ u8 value8 = 0;
++ u32 value32 = 0;
++
++ // polling autoload done.
++ u32 pollingCount = 0;
++
++ do
++ {
++ if(rtw_read8(padapter, REG_APS_FSMCO) & PFM_ALDN){
++ //RT_TRACE(COMP_INIT,DBG_LOUD,("Autoload Done!\n"));
++ break;
++ }
++
++ if(pollingCount++ > POLLING_READY_TIMEOUT_COUNT){
++ //RT_TRACE(COMP_INIT,DBG_SERIOUS,("Failed to polling REG_APS_FSMCO[PFM_ALDN] done!\n"));
++ return _FAIL;
++ }
++
++ }while(_TRUE);
++
++
++// For hardware power on sequence.
++
++ //0. RSV_CTRL 0x1C[7:0] = 0x00 // unlock ISO/CLK/Power control register
++ rtw_write8(padapter, REG_RSV_CTRL, 0x0);
++ // Power on when re-enter from IPS/Radio off/card disable
++ rtw_write8(padapter, REG_SPS0_CTRL, 0x2b);//enable SPS into PWM mode
++/*
++ value16 = PlatformIORead2Byte(Adapter, REG_AFE_XTAL_CTRL);//enable AFE clock
++ value16 &= (~XTAL_GATE_AFE);
++ PlatformIOWrite2Byte(Adapter,REG_AFE_XTAL_CTRL, value16 );
++*/
++
++ rtw_udelay_os(100);//PlatformSleepUs(150);//this is not necessary when initially power on
++
++ value8 = rtw_read8(padapter, REG_LDOV12D_CTRL);
++ if(0== (value8 & LDV12_EN) ){
++ value8 |= LDV12_EN;
++ rtw_write8(padapter, REG_LDOV12D_CTRL, value8);
++ //RT_TRACE(COMP_INIT, DBG_LOUD, (" power-on :REG_LDOV12D_CTRL Reg0x21:0x%02x.\n",value8));
++ rtw_udelay_os(100);//PlatformSleepUs(100);//this is not necessary when initially power on
++ value8 = rtw_read8(padapter, REG_SYS_ISO_CTRL);
++ value8 &= ~ISO_MD2PP;
++ rtw_write8(padapter, REG_SYS_ISO_CTRL, value8);
++ }
++
++ // auto enable WLAN
++ pollingCount = 0;
++ value16 = rtw_read16(padapter, REG_APS_FSMCO);
++ value16 |= APFM_ONMAC;
++ rtw_write16(padapter, REG_APS_FSMCO, value16);
++
++ do
++ {
++ if(0 == (rtw_read16(padapter, REG_APS_FSMCO) & APFM_ONMAC)){
++ //RT_TRACE(COMP_INIT,DBG_LOUD,("MAC auto ON okay!\n"));
++ break;
++ }
++
++ if(pollingCount++ > POLLING_READY_TIMEOUT_COUNT){
++ //RT_TRACE(COMP_INIT,DBG_SERIOUS,("Failed to polling REG_APS_FSMCO[APFM_ONMAC] done!\n"));
++ return _FAIL;
++ }
++
++ }while(_TRUE);
++
++ //Enable Radio ,GPIO ,and LED function
++ rtw_write16(padapter,REG_APS_FSMCO,0x0812);
++
++#ifdef CONFIG_AUTOSUSPEND
++ //for usb Combo card ,BT
++ if((BOARD_USB_COMBO == pHalData->BoardType)&&(padapter->registrypriv.usbss_enable))
++ {
++ value32 = rtw_read32(padapter, REG_APS_FSMCO);
++ value32 |= (SOP_ABG|SOP_AMB|XOP_BTCK);
++ rtw_write32(padapter, REG_APS_FSMCO, value32);
++ }
++#endif
++
++ // release RF digital isolation
++ value16 = rtw_read16(padapter, REG_SYS_ISO_CTRL);
++ value16 &= ~ISO_DIOR;
++ rtw_write16(padapter, REG_SYS_ISO_CTRL, value16);
++
++ // Enable MAC DMA/WMAC/SCHEDULE/SEC block
++ value16 = rtw_read16(padapter, REG_CR);
++ value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN
++ | PROTOCOL_EN | SCHEDULE_EN | MACTXEN | MACRXEN | ENSEC);
++ rtw_write16(padapter, REG_CR, value16);
++
++ //tynli_test for suspend mode.
++ {
++ rtw_write8(padapter, 0xfe10, 0x19);
++ }
++
++ // 2010/11/22 MH For slim combo debug mode check.
++ if (pHalData->BoardType == BOARD_USB_COMBO)
++ {
++ if (pHalData->SlimComboDbg == _TRUE)
++ {
++ DBG_8192C("SlimComboDbg == TRUE\n");
++
++ // 1. SIC?Test Mode ¤¤, Debug Ports ·|¦Û°Ê Enable, ©Ò¥H Driver ¤W¨Ó«á,
++ // ­nÃö±¼½Ð³]©w 0x 00[7] -> "1", ±N¥¦ Disable. effect if not: power consumption increase
++ rtw_write8(padapter, REG_SYS_ISO_CTRL, rtw_read8(padapter, REG_SYS_ISO_CTRL)|BIT7);
++
++ // 2. SIC?Test Mode ¤¤, GPIO-8?·| report Power State ©Ò¥H Driver ¤W¨Ó«á, ½Ð³]©w? 0x04[6] -> "1" ±N¥¦ Disable
++ // effect if not: GPIO-8 could not be GPIO or LED function
++ rtw_write8(padapter, REG_APS_FSMCO, rtw_read8(padapter, REG_APS_FSMCO)|BIT6);
++
++ // 3. SIC Test Mode ¤¤, EESK, EECS ·| report?Host Clock status, ©Ò¥H Driver ¤W¨Ó«á, ½Ð³]©w? 0x40[4] -> "1" ±N¥¦¤Á¦¨ EEPROM ¨Ï¥Î Pin (autoload still from Efuse)
++ // effect if not:power consumption increase
++ value8 = rtw_read8(padapter, REG_GPIO_MUXCFG)|BIT4 ;
++ #ifdef CONFIG_BT_COEXIST
++ // 2011/01/26 MH UMB-B cut bug. We need to support the modification.
++ if (IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID) &&
++ pHalData->bt_coexist.BT_Coexist)
++ {
++ value8 |= (BIT5);
++ }
++ #endif
++ rtw_write8(padapter, REG_GPIO_MUXCFG,value8 );
++
++
++ // 4. SIC Test Mode ¤¤,?SIC Debug ports ·|¦Û°Ê Enable , ©Ò¥H Driver ¤W¨Ó«á°¨¤W, ½Ð³]©w? 0x40[15:11] -> ¡§0x00¡¨, ±N¥¦Disable
++ // 4.1Two Steps setting for safety: 0x40[15,13,12, 11] -> "0", then ?0x40[14] -> "0"
++ // effect if not: Host could not transfer packets, and GPIO-3,2 will occupied by SIC then Co-exist could not work.
++ rtw_write16(padapter, REG_GPIO_MUXCFG, (rtw_read16(padapter, REG_GPIO_MUXCFG)&0x07FF)|BIT14);
++ rtw_write16(padapter, REG_GPIO_MUXCFG, rtw_read16(padapter, REG_GPIO_MUXCFG)&0x07FF);
++ }
++ }
++
++
++ // 2011/02/18 To Fix RU LNA power leakage problem. We need to execute below below in
++ // Adapter init and halt sequence. Accordingto EEchou's opinion, we can enable the ability for all
++ // IC. According to Johnny's opinion, only RU will meet the condition.
++ if (IS_HARDWARE_TYPE_8192C(padapter) && (pHalData->BoardType == BOARD_USB_High_PA))
++ rtw_write32(padapter, rFPGA0_XCD_RFParameter, rtw_read32(padapter, rFPGA0_XCD_RFParameter)&(~BIT1));
++ return ret;
++
++}
++
++
++static void _dbg_dump_macreg(_adapter *padapter)
++{
++ u32 offset = 0;
++ u32 val32 = 0;
++ u32 index =0 ;
++ for(index=0;index<64;index++)
++ {
++ offset = index*4;
++ val32 = rtw_read32(padapter,offset);
++ DBG_8192C("offset : 0x%02x ,val:0x%08x\n",offset,val32);
++ }
++}
++
++
++static void _InitPABias(_adapter *padapter)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++ u8 pa_setting;
++ BOOLEAN is92C = IS_92C_SERIAL(pHalData->VersionID);
++
++ //FIXED PA current issue
++ //efuse_one_byte_read(padapter, 0x1FA, &pa_setting);
++ pa_setting = EFUSE_Read1Byte(padapter, 0x1FA);
++
++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("_InitPABias 0x1FA 0x%x \n",pa_setting));
++
++ if(!(pa_setting & BIT0))
++ {
++ PHY_SetRFReg(padapter, RF_PATH_A, 0x15, 0x0FFFFF, 0x0F406);
++ PHY_SetRFReg(padapter, RF_PATH_A, 0x15, 0x0FFFFF, 0x4F406);
++ PHY_SetRFReg(padapter, RF_PATH_A, 0x15, 0x0FFFFF, 0x8F406);
++ PHY_SetRFReg(padapter, RF_PATH_A, 0x15, 0x0FFFFF, 0xCF406);
++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("PA BIAS path A\n"));
++ }
++
++ if(!(pa_setting & BIT1) && is92C)
++ {
++ PHY_SetRFReg(padapter,RF_PATH_B, 0x15, 0x0FFFFF, 0x0F406);
++ PHY_SetRFReg(padapter,RF_PATH_B, 0x15, 0x0FFFFF, 0x4F406);
++ PHY_SetRFReg(padapter,RF_PATH_B, 0x15, 0x0FFFFF, 0x8F406);
++ PHY_SetRFReg(padapter,RF_PATH_B, 0x15, 0x0FFFFF, 0xCF406);
++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("PA BIAS path B\n"));
++ }
++
++ if(!(pa_setting & BIT4))
++ {
++ pa_setting = rtw_read8(padapter, 0x16);
++ pa_setting &= 0x0F;
++ rtw_write8(padapter, 0x16, pa_setting | 0x90);
++ }
++}
++#ifdef CONFIG_BT_COEXIST
++static void _InitBTCoexist(_adapter *padapter)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++ struct btcoexist_priv *pbtpriv = &(pHalData->bt_coexist);
++ u8 u1Tmp;
++
++ if(pbtpriv->BT_Coexist && pbtpriv->BT_CoexistType == BT_CSR_BC4)
++ {
++
++#if MP_DRIVER != 1
++ if(pbtpriv->BT_Ant_isolation)
++ {
++ rtw_write8( padapter,REG_GPIO_MUXCFG, 0xa0);
++ DBG_8192C("BT write 0x%x = 0x%x\n", REG_GPIO_MUXCFG, 0xa0);
++ }
++#endif
++
++ u1Tmp = rtw_read8(padapter, 0x4fd) & BIT0;
++ u1Tmp = u1Tmp |
++ ((pbtpriv->BT_Ant_isolation==1)?0:BIT1) |
++ ((pbtpriv->BT_Service==BT_SCO)?0:BIT2);
++ rtw_write8( padapter, 0x4fd, u1Tmp);
++ DBG_8192C("BT write 0x%x = 0x%x for non-isolation\n", 0x4fd, u1Tmp);
++
++
++ rtw_write32(padapter, REG_BT_COEX_TABLE+4, 0xaaaa9aaa);
++ DBG_8192C("BT write 0x%x = 0x%x\n", REG_BT_COEX_TABLE+4, 0xaaaa9aaa);
++
++ rtw_write32(padapter, REG_BT_COEX_TABLE+8, 0xffbd0040);
++ DBG_8192C("BT write 0x%x = 0x%x\n", REG_BT_COEX_TABLE+8, 0xffbd0040);
++
++ rtw_write32(padapter, REG_BT_COEX_TABLE+0xc, 0x40000010);
++ DBG_8192C("BT write 0x%x = 0x%x\n", REG_BT_COEX_TABLE+0xc, 0x40000010);
++
++ //Config to 1T1R
++ u1Tmp = rtw_read8(padapter,rOFDM0_TRxPathEnable);
++ u1Tmp &= ~(BIT1);
++ rtw_write8( padapter, rOFDM0_TRxPathEnable, u1Tmp);
++ DBG_8192C("BT write 0xC04 = 0x%x\n", u1Tmp);
++
++ u1Tmp = rtw_read8(padapter, rOFDM1_TRxPathEnable);
++ u1Tmp &= ~(BIT1);
++ rtw_write8( padapter, rOFDM1_TRxPathEnable, u1Tmp);
++ DBG_8192C("BT write 0xD04 = 0x%x\n", u1Tmp);
++
++ }
++}
++#endif
++
++//-------------------------------------------------------------------------
++//
++// LLT R/W/Init function
++//
++//-------------------------------------------------------------------------
++static u8 _LLTWrite(
++ IN PADAPTER Adapter,
++ IN u32 address,
++ IN u32 data
++ )
++{
++ u8 status = _SUCCESS;
++ int count = 0;
++ u32 value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
++
++ rtw_write32(Adapter, REG_LLT_INIT, value);
++
++ //polling
++ do{
++
++ value = rtw_read32(Adapter, REG_LLT_INIT);
++ if(_LLT_NO_ACTIVE == _LLT_OP_VALUE(value)){
++ break;
++ }
++
++ if(count > POLLING_LLT_THRESHOLD){
++ //RT_TRACE(COMP_INIT,DBG_SERIOUS,("Failed to polling write LLT done at address %d!\n", address));
++ status = _FAIL;
++ break;
++ }
++ }while(count++);
++
++ return status;
++
++}
++
++
++static u8 _LLTRead(
++ IN PADAPTER Adapter,
++ IN u32 address
++ )
++{
++ int count = 0;
++ u32 value = _LLT_INIT_ADDR(address) | _LLT_OP(_LLT_READ_ACCESS);
++
++ rtw_write32(Adapter, REG_LLT_INIT, value);
++
++ //polling and get value
++ do{
++
++ value = rtw_read32(Adapter, REG_LLT_INIT);
++ if(_LLT_NO_ACTIVE == _LLT_OP_VALUE(value)){
++ return (u8)value;
++ }
++
++ if(count > POLLING_LLT_THRESHOLD){
++ //RT_TRACE(COMP_INIT,DBG_SERIOUS,("Failed to polling read LLT done at address %d!\n", address));
++ break;
++ }
++ }while(count++);
++
++ return 0xFF;
++
++}
++
++
++static u8 InitLLTTable(
++ IN PADAPTER Adapter,
++ IN u32 boundary
++ )
++{
++ u8 status = _SUCCESS;
++ u32 i;
++
++#ifdef CONFIG_IOL_LLT
++ if(rtw_IOL_applied(Adapter))
++ {
++ struct xmit_frame *xmit_frame;
++ if((xmit_frame=rtw_IOL_accquire_xmit_frame(Adapter)) == NULL)
++ return _FAIL;
++
++ rtw_IOL_append_LLT_cmd(xmit_frame, boundary);
++ status = rtw_IOL_exec_cmds_sync(Adapter, xmit_frame, 1000);
++ }
++ else
++#endif
++ {
++ for(i = 0 ; i < (boundary - 1) ; i++){
++ status = _LLTWrite(Adapter, i , i + 1);
++ if(_SUCCESS != status){
++ return status;
++ }
++ }
++
++ // end of list
++ status = _LLTWrite(Adapter, (boundary - 1), 0xFF);
++ if(_SUCCESS != status){
++ return status;
++ }
++
++ // Make the other pages as ring buffer
++ // This ring buffer is used as beacon buffer if we config this MAC as two MAC transfer.
++ // Otherwise used as local loopback buffer.
++ for(i = boundary ; i < LAST_ENTRY_OF_TX_PKT_BUFFER ; i++){
++ status = _LLTWrite(Adapter, i, (i + 1));
++ if(_SUCCESS != status){
++ return status;
++ }
++ }
++
++ // Let last entry point to the start entry of ring buffer
++ status = _LLTWrite(Adapter, LAST_ENTRY_OF_TX_PKT_BUFFER, boundary);
++ if(_SUCCESS != status){
++ return status;
++ }
++ }
++
++ return status;
++
++}
++
++
++//---------------------------------------------------------------
++//
++// MAC init functions
++//
++//---------------------------------------------------------------
++static VOID
++_SetMacID(
++ IN PADAPTER Adapter, u8* MacID
++ )
++{
++ u32 i;
++ for(i=0 ; i< MAC_ADDR_LEN ; i++){
++#ifdef CONFIG_CONCURRENT_MODE
++ if(Adapter->iface_type == IFACE_PORT1)
++ rtw_write32(Adapter, REG_MACID1+i, MacID[i]);
++ else
++#endif
++ rtw_write32(Adapter, REG_MACID+i, MacID[i]);
++ }
++}
++
++static VOID
++_SetBSSID(
++ IN PADAPTER Adapter, u8* BSSID
++ )
++{
++ u32 i;
++ for(i=0 ; i< MAC_ADDR_LEN ; i++){
++#ifdef CONFIG_CONCURRENT_MODE
++ if(Adapter->iface_type == IFACE_PORT1)
++ rtw_write32(Adapter, REG_BSSID1+i, BSSID[i]);
++ else
++#endif
++ rtw_write32(Adapter, REG_BSSID+i, BSSID[i]);
++ }
++}
++
++
++// Shall USB interface init this?
++static VOID
++_InitInterrupt(
++ IN PADAPTER Adapter
++ )
++{
++ u32 value32;
++
++ // HISR - turn all on
++ value32 = 0xFFFFFFFF;
++ rtw_write32(Adapter, REG_HISR, value32);
++
++ // HIMR - turn all on
++ rtw_write32(Adapter, REG_HIMR, value32);
++}
++
++
++static VOID
++_InitQueueReservedPage(
++ IN PADAPTER Adapter
++ )
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ struct registry_priv *pregistrypriv = &Adapter->registrypriv;
++
++ u32 outEPNum = (u32)pHalData->OutEpNumber;
++ u32 numHQ = 0;
++ u32 numLQ = 0;
++ u32 numNQ = 0;
++ u32 numPubQ;
++ u32 value32;
++ u8 value8;
++ BOOLEAN bWiFiConfig = pregistrypriv->wifi_spec;
++ //u32 txQPageNum, txQPageUnit,txQRemainPage;
++
++ { //for WMM
++ //RT_ASSERT((outEPNum>=2), ("for WMM ,number of out-ep must more than or equal to 2!\n"));
++
++ if(pHalData->OutEpQueueSel & TX_SELE_HQ){
++ numHQ = (bWiFiConfig)?WMM_NORMAL_PAGE_NUM_HPQ:NORMAL_PAGE_NUM_HPQ;
++ }
++
++ if(pHalData->OutEpQueueSel & TX_SELE_LQ){
++ numLQ = (bWiFiConfig)?WMM_NORMAL_PAGE_NUM_LPQ:NORMAL_PAGE_NUM_LPQ;
++ }
++ // NOTE: This step shall be proceed before writting REG_RQPN.
++ if(pHalData->OutEpQueueSel & TX_SELE_NQ){
++ numNQ = (bWiFiConfig)?WMM_NORMAL_PAGE_NUM_NPQ:NORMAL_PAGE_NUM_NPQ;
++ }
++ value8 = (u8)_NPQ(numNQ);
++ rtw_write8(Adapter, REG_RQPN_NPQ, value8);
++
++ if (bWiFiConfig)
++ numPubQ = WMM_NORMAL_TX_TOTAL_PAGE_NUMBER - numHQ - numLQ - numNQ;
++ else
++ numPubQ = TX_TOTAL_PAGE_NUMBER - numHQ - numLQ - numNQ;
++ }
++
++ // TX DMA
++ value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN;
++ rtw_write32(Adapter, REG_RQPN, value32);
++}
++
++static VOID
++_InitTxBufferBoundary(
++ IN PADAPTER Adapter
++ )
++{
++ struct registry_priv *pregistrypriv = &Adapter->registrypriv;
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++
++ u8 txpktbuf_bndy;
++
++ if(!pregistrypriv->wifi_spec){
++ txpktbuf_bndy = TX_PAGE_BOUNDARY;
++ }
++ else{//for WMM
++ txpktbuf_bndy = WMM_NORMAL_TX_PAGE_BOUNDARY;
++ }
++
++ rtw_write8(Adapter, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
++ rtw_write8(Adapter, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
++ rtw_write8(Adapter, REG_TXPKTBUF_WMAC_LBK_BF_HD, txpktbuf_bndy);
++ rtw_write8(Adapter, REG_TRXFF_BNDY, txpktbuf_bndy);
++#if 1
++ rtw_write8(Adapter, REG_TDECTRL+1, txpktbuf_bndy);
++#else
++ txdmactrl = PlatformIORead2Byte(Adapter, REG_TDECTRL);
++ txdmactrl &= ~BCN_HEAD_MASK;
++ txdmactrl |= BCN_HEAD(txpktbuf_bndy);
++ PlatformIOWrite2Byte(Adapter, REG_TDECTRL, txdmactrl);
++#endif
++}
++
++static VOID
++_InitPageBoundary(
++ IN PADAPTER Adapter
++ )
++{
++ // RX Page Boundary
++ //srand(static_cast<unsigned int>(time(NULL)) );
++ u16 rxff_bndy = 0x27FF;//(rand() % 1) ? 0x27FF : 0x23FF;
++
++ rtw_write16(Adapter, (REG_TRXFF_BNDY + 2), rxff_bndy);
++
++ // TODO: ?? shall we set tx boundary?
++}
++
++
++static VOID
++_InitNormalChipRegPriority(
++ IN PADAPTER Adapter,
++ IN u16 beQ,
++ IN u16 bkQ,
++ IN u16 viQ,
++ IN u16 voQ,
++ IN u16 mgtQ,
++ IN u16 hiQ
++ )
++{
++ u16 value16 = (rtw_read16(Adapter, REG_TRXDMA_CTRL) & 0x7);
++
++ value16 |= _TXDMA_BEQ_MAP(beQ) | _TXDMA_BKQ_MAP(bkQ) |
++ _TXDMA_VIQ_MAP(viQ) | _TXDMA_VOQ_MAP(voQ) |
++ _TXDMA_MGQ_MAP(mgtQ)| _TXDMA_HIQ_MAP(hiQ);
++
++ rtw_write16(Adapter, REG_TRXDMA_CTRL, value16);
++}
++
++static VOID
++_InitNormalChipOneOutEpPriority(
++ IN PADAPTER Adapter
++ )
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++
++ u16 value = 0;
++ switch(pHalData->OutEpQueueSel)
++ {
++ case TX_SELE_HQ:
++ value = QUEUE_HIGH;
++ break;
++ case TX_SELE_LQ:
++ value = QUEUE_LOW;
++ break;
++ case TX_SELE_NQ:
++ value = QUEUE_NORMAL;
++ break;
++ default:
++ //RT_ASSERT(FALSE,("Shall not reach here!\n"));
++ break;
++ }
++
++ _InitNormalChipRegPriority(Adapter,
++ value,
++ value,
++ value,
++ value,
++ value,
++ value
++ );
++
++}
++
++static VOID
++_InitNormalChipTwoOutEpPriority(
++ IN PADAPTER Adapter
++ )
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ struct registry_priv *pregistrypriv = &Adapter->registrypriv;
++ u16 beQ,bkQ,viQ,voQ,mgtQ,hiQ;
++
++
++ u16 valueHi = 0;
++ u16 valueLow = 0;
++
++ switch(pHalData->OutEpQueueSel)
++ {
++ case (TX_SELE_HQ | TX_SELE_LQ):
++ valueHi = QUEUE_HIGH;
++ valueLow = QUEUE_LOW;
++ break;
++ case (TX_SELE_NQ | TX_SELE_LQ):
++ valueHi = QUEUE_NORMAL;
++ valueLow = QUEUE_LOW;
++ break;
++ case (TX_SELE_HQ | TX_SELE_NQ):
++ valueHi = QUEUE_HIGH;
++ valueLow = QUEUE_NORMAL;
++ break;
++ default:
++ //RT_ASSERT(FALSE,("Shall not reach here!\n"));
++ break;
++ }
++
++ if(!pregistrypriv->wifi_spec ){
++ beQ = valueLow;
++ bkQ = valueLow;
++ viQ = valueHi;
++ voQ = valueHi;
++ mgtQ = valueHi;
++ hiQ = valueHi;
++ }
++ else{//for WMM ,CONFIG_OUT_EP_WIFI_MODE
++ beQ = valueLow;
++ bkQ = valueHi;
++ viQ = valueHi;
++ voQ = valueLow;
++ mgtQ = valueHi;
++ hiQ = valueHi;
++ }
++
++ _InitNormalChipRegPriority(Adapter,beQ,bkQ,viQ,voQ,mgtQ,hiQ);
++
++}
++
++static VOID
++_InitNormalChipThreeOutEpPriority(
++ IN PADAPTER Adapter
++ )
++{
++ struct registry_priv *pregistrypriv = &Adapter->registrypriv;
++ u16 beQ,bkQ,viQ,voQ,mgtQ,hiQ;
++
++ if(!pregistrypriv->wifi_spec ){// typical setting
++ beQ = QUEUE_LOW;
++ bkQ = QUEUE_LOW;
++ viQ = QUEUE_NORMAL;
++ voQ = QUEUE_HIGH;
++ mgtQ = QUEUE_HIGH;
++ hiQ = QUEUE_HIGH;
++ }
++ else{// for WMM
++ beQ = QUEUE_LOW;
++ bkQ = QUEUE_NORMAL;
++ viQ = QUEUE_NORMAL;
++ voQ = QUEUE_HIGH;
++ mgtQ = QUEUE_HIGH;
++ hiQ = QUEUE_HIGH;
++ }
++ _InitNormalChipRegPriority(Adapter,beQ,bkQ,viQ,voQ,mgtQ,hiQ);
++}
++
++static VOID
++_InitNormalChipQueuePriority(
++ IN PADAPTER Adapter
++ )
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++
++ switch(pHalData->OutEpNumber)
++ {
++ case 1:
++ _InitNormalChipOneOutEpPriority(Adapter);
++ break;
++ case 2:
++ _InitNormalChipTwoOutEpPriority(Adapter);
++ break;
++ case 3:
++ _InitNormalChipThreeOutEpPriority(Adapter);
++ break;
++ default:
++ //RT_ASSERT(FALSE,("Shall not reach here!\n"));
++ break;
++ }
++
++
++}
++
++static VOID
++_InitQueuePriority(
++ IN PADAPTER Adapter
++ )
++{
++ _InitNormalChipQueuePriority(Adapter);
++}
++
++static VOID
++_InitHardwareDropIncorrectBulkOut(
++ IN PADAPTER Adapter
++ )
++{
++ u32 value32 = rtw_read32(Adapter, REG_TXDMA_OFFSET_CHK);
++ value32 |= DROP_DATA_EN;
++ rtw_write32(Adapter, REG_TXDMA_OFFSET_CHK, value32);
++}
++
++static VOID
++_InitNetworkType(
++ IN PADAPTER Adapter
++ )
++{
++ u32 value32;
++
++ value32 = rtw_read32(Adapter, REG_CR);
++
++ // TODO: use the other function to set network type
++#if RTL8191C_FPGA_NETWORKTYPE_ADHOC
++ value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AD_HOC);
++#else
++ value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AP);
++#endif
++ rtw_write32(Adapter, REG_CR, value32);
++// RASSERT(pIoBase->rtw_read8(REG_CR + 2) == 0x2);
++}
++
++static VOID
++_InitTransferPageSize(
++ IN PADAPTER Adapter
++ )
++{
++ // Tx page size is always 128.
++
++ u8 value8;
++ value8 = _PSRX(PBP_128) | _PSTX(PBP_128);
++ rtw_write8(Adapter, REG_PBP, value8);
++}
++
++static VOID
++_InitDriverInfoSize(
++ IN PADAPTER Adapter,
++ IN u8 drvInfoSize
++ )
++{
++ rtw_write8(Adapter,REG_RX_DRVINFO_SZ, drvInfoSize);
++}
++
++static VOID
++_InitWMACSetting(
++ IN PADAPTER Adapter
++ )
++{
++ //u4Byte value32;
++ //u16 value16;
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++
++ //pHalData->ReceiveConfig = AAP | APM | AM | AB | APP_ICV | ADF | AMF | APP_FCS | HTC_LOC_CTRL | APP_MIC | APP_PHYSTS;
++ //pHalData->ReceiveConfig = RCR_AAP | RCR_APM | RCR_AM | RCR_AB |RCR_CBSSID_DATA| RCR_CBSSID_BCN| RCR_APP_ICV | RCR_AMF | RCR_HTC_LOC_CTRL | RCR_APP_MIC | RCR_APP_PHYSTS;
++ // don't turn on AAP, it will allow all packets to driver
++ pHalData->ReceiveConfig = RCR_APM | RCR_AM | RCR_AB |RCR_CBSSID_DATA| RCR_CBSSID_BCN| RCR_APP_ICV | RCR_AMF | RCR_HTC_LOC_CTRL | RCR_APP_MIC | RCR_APP_PHYSTS;
++
++#if (0 == RTL8192C_RX_PACKET_NO_INCLUDE_CRC)
++ pHalData->ReceiveConfig |= ACRC32;
++#endif
++
++ // some REG_RCR will be modified later by phy_ConfigMACWithHeaderFile()
++ rtw_write32(Adapter, REG_RCR, pHalData->ReceiveConfig);
++
++ // Accept all multicast address
++ rtw_write32(Adapter, REG_MAR, 0xFFFFFFFF);
++ rtw_write32(Adapter, REG_MAR + 4, 0xFFFFFFFF);
++
++
++ // Accept all data frames
++ //value16 = 0xFFFF;
++ //rtw_write16(Adapter, REG_RXFLTMAP2, value16);
++
++ // 2010.09.08 hpfan
++ // Since ADF is removed from RCR, ps-poll will not be indicate to driver,
++ // RxFilterMap should mask ps-poll to gurantee AP mode can rx ps-poll.
++ //value16 = 0x400;
++ //rtw_write16(Adapter, REG_RXFLTMAP1, value16);
++
++ // Accept all management frames
++ //value16 = 0xFFFF;
++ //rtw_write16(Adapter, REG_RXFLTMAP0, value16);
++
++ //enable RX_SHIFT bits
++ //rtw_write8(Adapter, REG_TRXDMA_CTRL, rtw_read8(Adapter, REG_TRXDMA_CTRL)|BIT(1));
++
++}
++
++static VOID
++_InitAdaptiveCtrl(
++ IN PADAPTER Adapter
++ )
++{
++ u16 value16;
++ u32 value32;
++
++ // Response Rate Set
++ value32 = rtw_read32(Adapter, REG_RRSR);
++ value32 &= ~RATE_BITMAP_ALL;
++ value32 |= RATE_RRSR_CCK_ONLY_1M;
++ rtw_write32(Adapter, REG_RRSR, value32);
++
++ // CF-END Threshold
++ //m_spIoBase->rtw_write8(REG_CFEND_TH, 0x1);
++
++ // SIFS (used in NAV)
++ value16 = _SPEC_SIFS_CCK(0x10) | _SPEC_SIFS_OFDM(0x10);
++ rtw_write16(Adapter, REG_SPEC_SIFS, value16);
++
++ // Retry Limit
++ value16 = _LRL(0x30) | _SRL(0x30);
++ rtw_write16(Adapter, REG_RL, value16);
++
++}
++
++static VOID
++_InitRateFallback(
++ IN PADAPTER Adapter
++ )
++{
++ // Set Data Auto Rate Fallback Retry Count register.
++ rtw_write32(Adapter, REG_DARFRC, 0x00000000);
++ rtw_write32(Adapter, REG_DARFRC+4, 0x10080404);
++ rtw_write32(Adapter, REG_RARFRC, 0x04030201);
++ rtw_write32(Adapter, REG_RARFRC+4, 0x08070605);
++
++}
++
++
++static VOID
++_InitEDCA(
++ IN PADAPTER Adapter
++ )
++{
++ // Set Spec SIFS (used in NAV)
++ rtw_write16(Adapter,REG_SPEC_SIFS, 0x100a);
++ rtw_write16(Adapter,REG_MAC_SPEC_SIFS, 0x100a);
++
++ //REG514:SIFS_CCK_CTX
++ //REG515:SIFS_OFDM_CTX
++ //REG516:SIFS_CCK_TRX
++ //REG517:SIFS_OFDM_TRX
++
++ // Set SIFS for CCK_CTS and OFDM_CTX
++ rtw_write16(Adapter,REG_SIFS_CTX, 0x100a);
++
++ // Set SIFS for CCK_TRX and OFDM_TRX
++ rtw_write16(Adapter,REG_SIFS_TRX, 0x100a);
++
++ // TXOP
++ rtw_write32(Adapter, REG_EDCA_BE_PARAM, 0x005EA42B);
++ rtw_write32(Adapter, REG_EDCA_BK_PARAM, 0x0000A44F);
++ rtw_write32(Adapter, REG_EDCA_VI_PARAM, 0x005EA324);
++ rtw_write32(Adapter, REG_EDCA_VO_PARAM, 0x002FA226);
++}
++
++
++static VOID
++_InitBeaconMaxError(
++ IN PADAPTER Adapter,
++ IN BOOLEAN InfraMode
++ )
++{
++#ifdef RTL8192CU_ADHOC_WORKAROUND_SETTING
++ rtw_write8(Adapter, REG_BCN_MAX_ERR, 0xFF);
++#else
++ //rtw_write8(Adapter, REG_BCN_MAX_ERR, (InfraMode ? 0xFF : 0x10));
++#endif
++}
++
++
++#ifdef CONFIG_LED
++static void _InitHWLed(PADAPTER Adapter)
++{
++ struct led_priv *pledpriv = &(Adapter->ledpriv);
++
++ if( pledpriv->LedStrategy != HW_LED)
++ return;
++
++// HW led control
++// to do ....
++//must consider cases of antenna diversity/ commbo card/solo card/mini card
++
++}
++#endif //CONFIG_LED
++
++static VOID
++_InitRDGSetting(
++ IN PADAPTER Adapter
++ )
++{
++ rtw_write8(Adapter,REG_RD_CTRL,0xFF);
++ rtw_write16(Adapter, REG_RD_NAV_NXT, 0x200);
++ rtw_write8(Adapter,REG_RD_RESP_PKT_TH,0x05);
++}
++
++static VOID
++_InitRxSetting(
++ IN PADAPTER Adapter
++ )
++{
++ rtw_write32(Adapter, REG_MACID, 0x87654321);
++ rtw_write32(Adapter, 0x0700, 0x87654321);
++}
++
++static VOID
++_InitRetryFunction(
++ IN PADAPTER Adapter
++ )
++{
++ u8 value8;
++
++ value8 = rtw_read8(Adapter, REG_FWHW_TXQ_CTRL);
++ value8 |= EN_AMPDU_RTY_NEW;
++ rtw_write8(Adapter, REG_FWHW_TXQ_CTRL, value8);
++
++ // Set ACK timeout
++ rtw_write8(Adapter, REG_ACKTO, 0x40);
++}
++
++/*-----------------------------------------------------------------------------
++ * Function: usb_AggSettingTxUpdate()
++ *
++ * Overview: Seperate TX/RX parameters update independent for TP detection and
++ * dynamic TX/RX aggreagtion parameters update.
++ *
++ * Input: PADAPTER
++ *
++ * Output/Return: NONE
++ *
++ * Revised History:
++ * When Who Remark
++ * 12/10/2010 MHC Seperate to smaller function.
++ *
++ *---------------------------------------------------------------------------*/
++static VOID
++usb_AggSettingTxUpdate(
++ IN PADAPTER Adapter
++ )
++{
++#ifdef CONFIG_USB_TX_AGGREGATION
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ //PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo);
++ u32 value32;
++
++ if(Adapter->registrypriv.wifi_spec)
++ pHalData->UsbTxAggMode = _FALSE;
++
++ if(pHalData->UsbTxAggMode){
++ value32 = rtw_read32(Adapter, REG_TDECTRL);
++ value32 = value32 & ~(BLK_DESC_NUM_MASK << BLK_DESC_NUM_SHIFT);
++ value32 |= ((pHalData->UsbTxAggDescNum & BLK_DESC_NUM_MASK) << BLK_DESC_NUM_SHIFT);
++
++ rtw_write32(Adapter, REG_TDECTRL, value32);
++ }
++
++#endif
++} // usb_AggSettingTxUpdate
++
++
++/*-----------------------------------------------------------------------------
++ * Function: usb_AggSettingRxUpdate()
++ *
++ * Overview: Seperate TX/RX parameters update independent for TP detection and
++ * dynamic TX/RX aggreagtion parameters update.
++ *
++ * Input: PADAPTER
++ *
++ * Output/Return: NONE
++ *
++ * Revised History:
++ * When Who Remark
++ * 12/10/2010 MHC Seperate to smaller function.
++ *
++ *---------------------------------------------------------------------------*/
++static VOID
++usb_AggSettingRxUpdate(
++ IN PADAPTER Adapter
++ )
++{
++#ifdef CONFIG_USB_RX_AGGREGATION
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ //PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo);
++ u8 valueDMA;
++ u8 valueUSB;
++
++ valueDMA = rtw_read8(Adapter, REG_TRXDMA_CTRL);
++ valueUSB = rtw_read8(Adapter, REG_USB_SPECIAL_OPTION);
++
++ switch(pHalData->UsbRxAggMode)
++ {
++ case USB_RX_AGG_DMA:
++ valueDMA |= RXDMA_AGG_EN;
++ valueUSB &= ~USB_AGG_EN;
++ break;
++ case USB_RX_AGG_USB:
++ valueDMA &= ~RXDMA_AGG_EN;
++ valueUSB |= USB_AGG_EN;
++ break;
++ case USB_RX_AGG_MIX:
++ valueDMA |= RXDMA_AGG_EN;
++ valueUSB |= USB_AGG_EN;
++ break;
++ case USB_RX_AGG_DISABLE:
++ default:
++ valueDMA &= ~RXDMA_AGG_EN;
++ valueUSB &= ~USB_AGG_EN;
++ break;
++ }
++
++ rtw_write8(Adapter, REG_TRXDMA_CTRL, valueDMA);
++ rtw_write8(Adapter, REG_USB_SPECIAL_OPTION, valueUSB);
++
++ switch(pHalData->UsbRxAggMode)
++ {
++ case USB_RX_AGG_DMA:
++ rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH, pHalData->UsbRxAggPageCount);
++ rtw_write8(Adapter, REG_USB_DMA_AGG_TO, pHalData->UsbRxAggPageTimeout);
++ break;
++ case USB_RX_AGG_USB:
++ rtw_write8(Adapter, REG_USB_AGG_TH, pHalData->UsbRxAggBlockCount);
++ rtw_write8(Adapter, REG_USB_AGG_TO, pHalData->UsbRxAggBlockTimeout);
++ break;
++ case USB_RX_AGG_MIX:
++ rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH, pHalData->UsbRxAggPageCount);
++ rtw_write8(Adapter, REG_USB_DMA_AGG_TO, pHalData->UsbRxAggPageTimeout);
++ rtw_write8(Adapter, REG_USB_AGG_TH, pHalData->UsbRxAggBlockCount);
++ rtw_write8(Adapter, REG_USB_AGG_TO, pHalData->UsbRxAggBlockTimeout);
++ break;
++ case USB_RX_AGG_DISABLE:
++ default:
++ // TODO:
++ break;
++ }
++
++ switch(PBP_128)
++ {
++ case PBP_128:
++ pHalData->HwRxPageSize = 128;
++ break;
++ case PBP_64:
++ pHalData->HwRxPageSize = 64;
++ break;
++ case PBP_256:
++ pHalData->HwRxPageSize = 256;
++ break;
++ case PBP_512:
++ pHalData->HwRxPageSize = 512;
++ break;
++ case PBP_1024:
++ pHalData->HwRxPageSize = 1024;
++ break;
++ default:
++ //RT_ASSERT(FALSE, ("RX_PAGE_SIZE_REG_VALUE definition is incorrect!\n"));
++ break;
++ }
++#endif
++} // usb_AggSettingRxUpdate
++
++static VOID
++InitUsbAggregationSetting(
++ IN PADAPTER Adapter
++ )
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++
++ // Tx aggregation setting
++ usb_AggSettingTxUpdate(Adapter);
++
++ // Rx aggregation setting
++ usb_AggSettingRxUpdate(Adapter);
++
++ // 201/12/10 MH Add for USB agg mode dynamic switch.
++ pHalData->UsbRxHighSpeedMode = _FALSE;
++}
++
++/*-----------------------------------------------------------------------------
++ * Function: USB_AggModeSwitch()
++ *
++ * Overview: When RX traffic is more than 40M, we need to adjust some parameters to increase
++ * RX speed by increasing batch indication size. This will decrease TCP ACK speed, we
++ * need to monitor the influence of FTP/network share.
++ * For TX mode, we are still ubder investigation.
++ *
++ * Input: PADAPTER
++ *
++ * Output: NONE
++ *
++ * Return: NONE
++ *
++ * Revised History:
++ * When Who Remark
++ * 12/10/2010 MHC Create Version 0.
++ *
++ *---------------------------------------------------------------------------*/
++VOID
++USB_AggModeSwitch(
++ IN PADAPTER Adapter
++ )
++{
++#if 0
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv);
++
++ //pHalData->UsbRxHighSpeedMode = FALSE;
++ // How to measure the RX speed? We assume that when traffic is more than
++ if (pMgntInfo->bRegAggDMEnable == _FALSE)
++ {
++ return; // Inf not support.
++ }
++
++
++ if (pmlmepriv->LinkDetectInfo.bHigherBusyTraffic == _TRUE &&
++ pHalData->UsbRxHighSpeedMode == _FALSE)
++ {
++ pHalData->UsbRxHighSpeedMode = _TRUE;
++ DBG_8192C("UsbAggModeSwitchCheck to HIGH\n");
++ }
++ else if (pmlmepriv->LinkDetectInfo.bHigherBusyTraffic == _FALSE &&
++ pHalData->UsbRxHighSpeedMode == _TRUE)
++ {
++ pHalData->UsbRxHighSpeedMode = _FALSE;
++ DBG_8192C("UsbAggModeSwitchCheck to LOW\n");
++ }
++ else
++ {
++ return;
++ }
++
++ // 2010/12/10 MH Add for USB Aggregation judgement we need to
++ //if( pMgntInfo->LinkDetectInfo.NumRxOkInPeriod > 4000 ||
++ // pMgntInfo->LinkDetectInfo.NumTxOkInPeriod > 4000 )
++
++#ifdef CONFIG_USB_TX_AGGREGATION
++ //usb_AggSettingTxUpdate(Adapter);
++#endif
++
++#ifdef CONFIG_USB_RX_AGGREGATION
++ if (pHalData->UsbRxHighSpeedMode == _TRUE)
++ {
++ // 2010/12/10 MH The parameter is tested by SD1 engineer and SD3 channel emulator.
++ // USB mode
++ pHalData->UsbRxAggBlockCount = 40;
++ pHalData->UsbRxAggBlockTimeout = 5;
++ // Mix mode
++ pHalData->UsbRxAggPageCount = 72;
++ pHalData->UsbRxAggPageTimeout = 6;
++ }
++ else
++ {
++ // USB mode
++ pHalData->UsbRxAggBlockCount = pMgntInfo->RegUsbRxAggBlockCount;
++ pHalData->UsbRxAggBlockTimeout = pMgntInfo->RegUsbRxAggBlockTimeout;
++ // Mix mode
++ pHalData->UsbRxAggPageCount = pMgntInfo->RegUsbRxAggPageCount;
++ pHalData->UsbRxAggPageTimeout = pMgntInfo->RegUsbRxAggPageTimeout;
++ }
++#endif
++#endif
++} // USB_AggModeSwitch
++
++static VOID
++_InitOperationMode(
++ IN PADAPTER Adapter
++ )
++{
++#if 0//gtest
++ PHAL_DATA_8192CUSB pHalData = GetHalData8192CUsb(Adapter);
++ u1Byte regBwOpMode = 0;
++ u4Byte regRATR = 0, regRRSR = 0;
++
++
++ //1 This part need to modified according to the rate set we filtered!!
++ //
++ // Set RRSR, RATR, and REG_BWOPMODE registers
++ //
++ switch(Adapter->RegWirelessMode)
++ {
++ case WIRELESS_MODE_B:
++ regBwOpMode = BW_OPMODE_20MHZ;
++ regRATR = RATE_ALL_CCK;
++ regRRSR = RATE_ALL_CCK;
++ break;
++ case WIRELESS_MODE_A:
++ ASSERT(FALSE);
++#if 0
++ regBwOpMode = BW_OPMODE_5G |BW_OPMODE_20MHZ;
++ regRATR = RATE_ALL_OFDM_AG;
++ regRRSR = RATE_ALL_OFDM_AG;
++#endif
++ break;
++ case WIRELESS_MODE_G:
++ regBwOpMode = BW_OPMODE_20MHZ;
++ regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
++ regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
++ break;
++ case WIRELESS_MODE_AUTO:
++ if (Adapter->bInHctTest)
++ {
++ regBwOpMode = BW_OPMODE_20MHZ;
++ regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
++ regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
++ }
++ else
++ {
++ regBwOpMode = BW_OPMODE_20MHZ;
++ regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
++ regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
++ }
++ break;
++ case WIRELESS_MODE_N_24G:
++ // It support CCK rate by default.
++ // CCK rate will be filtered out only when associated AP does not support it.
++ regBwOpMode = BW_OPMODE_20MHZ;
++ regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
++ regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
++ break;
++ case WIRELESS_MODE_N_5G:
++ ASSERT(FALSE);
++#if 0
++ regBwOpMode = BW_OPMODE_5G;
++ regRATR = RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
++ regRRSR = RATE_ALL_OFDM_AG;
++#endif
++ break;
++ }
++
++ // Ziv ????????
++ //PlatformEFIOWrite4Byte(Adapter, REG_INIRTS_RATE_SEL, regRRSR);
++ PlatformEFIOWrite1Byte(Adapter, REG_BWOPMODE, regBwOpMode);
++
++ // For Min Spacing configuration.
++ switch(pHalData->RF_Type)
++ {
++ case RF_1T2R:
++ case RF_1T1R:
++ RT_TRACE(COMP_INIT, DBG_LOUD, ("Initializeadapter: RF_Type%s\n", (pHalData->RF_Type==RF_1T1R? "(1T1R)":"(1T2R)")));
++ Adapter->MgntInfo.MinSpaceCfg = (MAX_MSS_DENSITY_1T<<3);
++ break;
++ case RF_2T2R:
++ case RF_2T2R_GREEN:
++ RT_TRACE(COMP_INIT, DBG_LOUD, ("Initializeadapter:RF_Type(2T2R)\n"));
++ Adapter->MgntInfo.MinSpaceCfg = (MAX_MSS_DENSITY_2T<<3);
++ break;
++ }
++
++ PlatformEFIOWrite1Byte(Adapter, REG_AMPDU_MIN_SPACE, Adapter->MgntInfo.MinSpaceCfg);
++#endif
++}
++
++
++ static VOID
++_InitBeaconParameters(
++ IN PADAPTER Adapter
++ )
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++
++ rtw_write16(Adapter, REG_BCN_CTRL, 0x1010);
++
++ // TODO: Remove these magic number
++ rtw_write16(Adapter, REG_TBTT_PROHIBIT,0x6404);// ms
++
++ rtw_write8(Adapter, REG_DRVERLYINT, DRIVER_EARLY_INT_TIME);// 5ms
++ rtw_write8(Adapter, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME); // 2ms
++
++ // Suggested by designer timchen. Change beacon AIFS to the largest number
++ // beacause test chip does not contension before sending beacon. by tynli. 2009.11.03
++ rtw_write16(Adapter, REG_BCNTCFG, 0x660F);
++}
++
++static VOID
++_InitRFType(
++ IN PADAPTER Adapter
++ )
++{
++ struct registry_priv *pregpriv = &Adapter->registrypriv;
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ BOOLEAN is92CU = IS_92C_SERIAL(pHalData->VersionID);
++
++#if DISABLE_BB_RF
++ pHalData->rf_chip = RF_PSEUDO_11N;
++ return;
++#endif
++
++ pHalData->rf_chip = RF_6052;
++
++ if(_FALSE == is92CU){
++ pHalData->rf_type = RF_1T1R;
++ DBG_8192C("Set RF Chip ID to RF_6052 and RF type to 1T1R.\n");
++ return;
++ }
++
++ // TODO: Consider that EEPROM set 92CU to 1T1R later.
++ // Force to overwrite setting according to chip version. Ignore EEPROM setting.
++ //pHalData->RF_Type = is92CU ? RF_2T2R : RF_1T1R;
++ MSG_8192C("Set RF Chip ID to RF_6052 and RF type to %d.\n", pHalData->rf_type);
++
++}
++
++static VOID _InitAdhocWorkaroundParams(IN PADAPTER Adapter)
++{
++#if RTL8192CU_ADHOC_WORKAROUND_SETTING
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ pHalData->RegBcnCtrlVal = rtw_read8(Adapter, REG_BCN_CTRL);
++ pHalData->RegTxPause = rtw_read8(Adapter, REG_TXPAUSE);
++ pHalData->RegFwHwTxQCtrl = rtw_read8(Adapter, REG_FWHW_TXQ_CTRL+2);
++ pHalData->RegReg542 = rtw_read8(Adapter, REG_TBTT_PROHIBIT+2);
++#endif
++}
++
++static VOID
++_BeaconFunctionEnable(
++ IN PADAPTER Adapter,
++ IN BOOLEAN Enable,
++ IN BOOLEAN Linked
++ )
++{
++ rtw_write8(Adapter, REG_BCN_CTRL, (BIT4 | BIT3 | BIT1));
++ //SetBcnCtrlReg(Adapter, (BIT4 | BIT3 | BIT1), 0x00);
++ //RT_TRACE(COMP_BEACON, DBG_LOUD, ("_BeaconFunctionEnable 0x550 0x%x\n", PlatformEFIORead1Byte(Adapter, 0x550)));
++
++ rtw_write8(Adapter, REG_RD_CTRL+1, 0x6F);
++}
++
++
++// Set CCK and OFDM Block "ON"
++static VOID _BBTurnOnBlock(
++ IN PADAPTER Adapter
++ )
++{
++#if (DISABLE_BB_RF)
++ return;
++#endif
++
++ PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bCCKEn, 0x1);
++ PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
++}
++
++static VOID _RfPowerSave(
++ IN PADAPTER Adapter
++ )
++{
++#if 0
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo);
++ u1Byte eRFPath;
++
++#if (DISABLE_BB_RF)
++ return;
++#endif
++
++ if(pMgntInfo->RegRfOff == TRUE){ // User disable RF via registry.
++ RT_TRACE((COMP_INIT|COMP_RF), DBG_LOUD, ("InitializeAdapter8192CUsb(): Turn off RF for RegRfOff.\n"));
++ MgntActSet_RF_State(Adapter, eRfOff, RF_CHANGE_BY_SW);
++ // Those action will be discard in MgntActSet_RF_State because off the same state
++ for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
++ PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)eRFPath, 0x4, 0xC00, 0x0);
++ }
++ else if(pMgntInfo->RfOffReason > RF_CHANGE_BY_PS){ // H/W or S/W RF OFF before sleep.
++ RT_TRACE((COMP_INIT|COMP_RF), DBG_LOUD, ("InitializeAdapter8192CUsb(): Turn off RF for RfOffReason(%ld).\n", pMgntInfo->RfOffReason));
++ MgntActSet_RF_State(Adapter, eRfOff, pMgntInfo->RfOffReason);
++ }
++ else{
++ pHalData->eRFPowerState = eRfOn;
++ pMgntInfo->RfOffReason = 0;
++ if(Adapter->bInSetPower || Adapter->bResetInProgress)
++ PlatformUsbEnableInPipes(Adapter);
++ RT_TRACE((COMP_INIT|COMP_RF), DBG_LOUD, ("InitializeAdapter8192CUsb(): RF is on.\n"));
++ }
++#endif
++}
++
++enum {
++ Antenna_Lfet = 1,
++ Antenna_Right = 2,
++};
++
++static VOID
++_InitAntenna_Selection(IN PADAPTER Adapter)
++{
++
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++
++ if(pHalData->AntDivCfg==0)
++ return;
++ DBG_8192C("==> %s ....\n",__FUNCTION__);
++
++ if((RF_1T1R == pHalData->rf_type))
++ {
++ rtw_write32(Adapter, REG_LEDCFG0, rtw_read32(Adapter, REG_LEDCFG0)|BIT23);
++ PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, BIT13, 0x01);
++
++ if(PHY_QueryBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300) == Antenna_A)
++ pHalData->CurAntenna = Antenna_A;
++ else
++ pHalData->CurAntenna = Antenna_B;
++ DBG_8192C("%s,Cur_ant:(%x)%s\n",__FUNCTION__,pHalData->CurAntenna,(pHalData->CurAntenna == Antenna_A)?"Antenna_A":"Antenna_B");
++
++}
++
++
++}
++//
++// 2010/08/09 MH Add for power down check.
++//
++static BOOLEAN
++HalDetectPwrDownMode(
++ IN PADAPTER Adapter
++ )
++{
++ u8 tmpvalue;
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ struct pwrctrl_priv *pwrctrlpriv = &Adapter->pwrctrlpriv;
++
++ EFUSE_ShadowRead(Adapter, 1, EEPROM_RF_OPT3, (u32 *)&tmpvalue);
++
++ // 2010/08/25 MH INF priority > PDN Efuse value.
++ if(tmpvalue & BIT4 && pwrctrlpriv->reg_pdnmode)
++ {
++ pHalData->pwrdown = _TRUE;
++ }
++ else
++ {
++ pHalData->pwrdown = _FALSE;
++ }
++
++ DBG_8192C("HalDetectPwrDownMode(): PDN=%d\n", pHalData->pwrdown);
++ return pHalData->pwrdown;
++
++} // HalDetectPwrDownMode
++
++
++//
++// 2010/08/26 MH Add for selective suspend mode check.
++// If Efuse 0x0e bit1 is not enabled, we can not support selective suspend for Minicard and
++// slim card.
++//
++static VOID
++HalDetectSelectiveSuspendMode(
++ IN PADAPTER Adapter
++ )
++{
++ u8 tmpvalue;
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(Adapter);
++
++ // If support HW radio detect, we need to enable WOL ability, otherwise, we
++ // can not use FW to notify host the power state switch.
++
++ EFUSE_ShadowRead(Adapter, 1, EEPROM_USB_OPTIONAL1, (u32 *)&tmpvalue);
++
++ DBG_8192C("HalDetectSelectiveSuspendMode(): SS ");
++ if(tmpvalue & BIT1)
++ {
++ DBG_8192C("Enable\n");
++ }
++ else
++ {
++ DBG_8192C("Disable\n");
++ pdvobjpriv->RegUsbSS = _FALSE;
++ }
++
++ // 2010/09/01 MH According to Dongle Selective Suspend INF. We can switch SS mode.
++ if (pdvobjpriv->RegUsbSS && !SUPPORT_HW_RADIO_DETECT(pHalData))
++ {
++ //PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo);
++
++ //if (!pMgntInfo->bRegDongleSS)
++ //{
++ // RT_TRACE(COMP_INIT, DBG_LOUD, ("Dongle disable SS\n"));
++ pdvobjpriv->RegUsbSS = _FALSE;
++ //}
++ }
++} // HalDetectSelectiveSuspendMode
++/*-----------------------------------------------------------------------------
++ * Function: HwSuspendModeEnable92Cu()
++ *
++ * Overview: HW suspend mode switch.
++ *
++ * Input: NONE
++ *
++ * Output: NONE
++ *
++ * Return: NONE
++ *
++ * Revised History:
++ * When Who Remark
++ * 08/23/2010 MHC HW suspend mode switch test..
++ *---------------------------------------------------------------------------*/
++static VOID
++HwSuspendModeEnable92Cu(
++ IN PADAPTER pAdapter,
++ IN u8 Type
++ )
++{
++ //PRT_USB_DEVICE pDevice = GET_RT_USB_DEVICE(pAdapter);
++ u16 reg = rtw_read16(pAdapter, REG_GPIO_MUXCFG);
++
++ //if (!pDevice->RegUsbSS)
++ {
++ return;
++ }
++
++ //
++ // 2010/08/23 MH According to Alfred's suggestion, we need to to prevent HW
++ // to enter suspend mode automatically. Otherwise, it will shut down major power
++ // domain and 8051 will stop. When we try to enter selective suspend mode, we
++ // need to prevent HW to enter D2 mode aumotmatically. Another way, Host will
++ // issue a S10 signal to power domain. Then it will cleat SIC setting(from Yngli).
++ // We need to enable HW suspend mode when enter S3/S4 or disable. We need
++ // to disable HW suspend mode for IPS/radio_off.
++ //
++ //RT_TRACE(COMP_RF, DBG_LOUD, ("HwSuspendModeEnable92Cu = %d\n", Type));
++ if (Type == _FALSE)
++ {
++ reg |= BIT14;
++ //RT_TRACE(COMP_RF, DBG_LOUD, ("REG_GPIO_MUXCFG = %x\n", reg));
++ rtw_write16(pAdapter, REG_GPIO_MUXCFG, reg);
++ reg |= BIT12;
++ //RT_TRACE(COMP_RF, DBG_LOUD, ("REG_GPIO_MUXCFG = %x\n", reg));
++ rtw_write16(pAdapter, REG_GPIO_MUXCFG, reg);
++ }
++ else
++ {
++ reg &= (~BIT12);
++ rtw_write16(pAdapter, REG_GPIO_MUXCFG, reg);
++ reg &= (~BIT14);
++ rtw_write16(pAdapter, REG_GPIO_MUXCFG, reg);
++ }
++
++} // HwSuspendModeEnable92Cu
++rt_rf_power_state RfOnOffDetect(IN PADAPTER pAdapter )
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
++ u8 val8;
++ rt_rf_power_state rfpowerstate = rf_off;
++
++ if(pAdapter->pwrctrlpriv.bHWPowerdown)
++ {
++ val8 = rtw_read8(pAdapter, REG_HSISR);
++ DBG_8192C("pwrdown, 0x5c(BIT7)=%02x\n", val8);
++ rfpowerstate = (val8 & BIT7) ? rf_off: rf_on;
++ }
++ else // rf on/off
++ {
++ rtw_write8( pAdapter, REG_MAC_PINMUX_CFG,rtw_read8(pAdapter, REG_MAC_PINMUX_CFG)&~(BIT3));
++ val8 = rtw_read8(pAdapter, REG_GPIO_IO_SEL);
++ DBG_8192C("GPIO_IN=%02x\n", val8);
++ rfpowerstate = (val8 & BIT3) ? rf_on : rf_off;
++ }
++ return rfpowerstate;
++} // HalDetectPwrDownMode
++
++void _ps_open_RF(_adapter *padapter);
++
++
++u32 rtl8192cu_hal_init(PADAPTER Adapter)
++{
++ u8 val8 = 0;
++ u32 boundary, status = _SUCCESS;
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ struct pwrctrl_priv *pwrctrlpriv = &Adapter->pwrctrlpriv;
++ struct registry_priv *pregistrypriv = &Adapter->registrypriv;
++ u8 is92C = IS_92C_SERIAL(pHalData->VersionID);
++ rt_rf_power_state eRfPowerStateToSet;
++#ifdef CONFIG_BT_COEXIST
++ struct btcoexist_priv *pbtpriv = &(pHalData->bt_coexist);
++#endif
++
++ u32 init_start_time = rtw_get_current_time();
++
++
++#ifdef DBG_HAL_INIT_PROFILING
++
++ enum HAL_INIT_STAGES {
++ HAL_INIT_STAGES_BEGIN = 0,
++ HAL_INIT_STAGES_INIT_PW_ON,
++ HAL_INIT_STAGES_MISC01,
++ HAL_INIT_STAGES_DOWNLOAD_FW,
++ HAL_INIT_STAGES_INIT_LLTT,
++ HAL_INIT_STAGES_MAC,
++ HAL_INIT_STAGES_MISC02,
++ HAL_INIT_STAGES_BB,
++ HAL_INIT_STAGES_RF,
++ HAL_INIT_STAGES_TURN_ON_BLOCK,
++ HAL_INIT_STAGES_INIT_SECURITY,
++ HAL_INIT_STAGES_MISC11,
++ //HAL_INIT_STAGES_RF_PS,
++ HAL_INIT_STAGES_IQK,
++ HAL_INIT_STAGES_PW_TRACK,
++ HAL_INIT_STAGES_LCK,
++ HAL_INIT_STAGES_MISC21,
++ HAL_INIT_STAGES_INIT_PABIAS,
++ HAL_INIT_STAGES_BT_COEXIST,
++ //HAL_INIT_STAGES_ANTENNA_SEL,
++ HAL_INIT_STAGES_INIT_HAL_DM,
++ HAL_INIT_STAGES_MISC31,
++ HAL_INIT_STAGES_END,
++ HAL_INIT_STAGES_NUM
++ };
++
++ char * hal_init_stages_str[] = {
++ "HAL_INIT_STAGES_BEGIN",
++ "HAL_INIT_STAGES_INIT_PW_ON",
++ "HAL_INIT_STAGES_MISC01",
++ "HAL_INIT_STAGES_DOWNLOAD_FW",
++ "HAL_INIT_STAGES_INIT_LLTT",
++ "HAL_INIT_STAGES_MAC",
++ "HAL_INIT_STAGES_MISC02",
++ "HAL_INIT_STAGES_BB",
++ "HAL_INIT_STAGES_RF",
++ "HAL_INIT_STAGES_TURN_ON_BLOCK",
++ "HAL_INIT_STAGES_INIT_SECURITY",
++ "HAL_INIT_STAGES_MISC11",
++ //"HAL_INIT_STAGES_RF_PS",
++ "HAL_INIT_STAGES_IQK",
++ "HAL_INIT_STAGES_PW_TRACK",
++ "HAL_INIT_STAGES_LCK",
++ "HAL_INIT_STAGES_MISC21",
++ "HAL_INIT_STAGES_INIT_PABIAS",
++ "HAL_INIT_STAGES_BT_COEXIST",
++ //"HAL_INIT_STAGES_ANTENNA_SEL",
++ "HAL_INIT_STAGES_INIT_HAL_DM",
++ "HAL_INIT_STAGES_MISC31",
++ "HAL_INIT_STAGES_END",
++ };
++
++ int hal_init_profiling_i;
++ u32 hal_init_stages_timestamp[HAL_INIT_STAGES_NUM]; //used to record the time of each stage's starting point
++
++ for(hal_init_profiling_i=0;hal_init_profiling_i<HAL_INIT_STAGES_NUM;hal_init_profiling_i++)
++ hal_init_stages_timestamp[hal_init_profiling_i]=0;
++
++ #define HAL_INIT_PROFILE_TAG(stage) hal_init_stages_timestamp[(stage)]=rtw_get_current_time();
++#else
++ #define HAL_INIT_PROFILE_TAG(stage) do {} while(0)
++#endif //DBG_HAL_INIT_PROFILING
++
++
++
++_func_enter_;
++
++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BEGIN);
++ if(Adapter->pwrctrlpriv.bkeepfwalive)
++ {
++ _ps_open_RF(Adapter);
++
++ if(pHalData->bIQKInitialized ){
++ rtl8192c_PHY_IQCalibrate(Adapter,_TRUE);
++ }
++ else{
++ rtl8192c_PHY_IQCalibrate(Adapter,_FALSE);
++ pHalData->bIQKInitialized = _TRUE;
++ }
++ rtl8192c_dm_CheckTXPowerTracking(Adapter);
++ rtl8192c_PHY_LCCalibrate(Adapter);
++
++ goto exit;
++ }
++
++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_PW_ON);
++ status = _InitPowerOn(Adapter);
++ if(status == _FAIL){
++ RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("Failed to init power on!\n"));
++ goto exit;
++ }
++
++
++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC01);
++ _InitQueueReservedPage(Adapter);
++ _InitTxBufferBoundary(Adapter);
++ _InitQueuePriority(Adapter);
++ _InitPageBoundary(Adapter);
++ _InitTransferPageSize(Adapter);
++
++
++#if ENABLE_USB_DROP_INCORRECT_OUT
++ _InitHardwareDropIncorrectBulkOut(Adapter);
++#endif
++
++ if(pHalData->bRDGEnable){
++ _InitRDGSetting(Adapter);
++ }
++
++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_DOWNLOAD_FW);
++#if (1 == MP_DRIVER)
++ _InitRxSetting(Adapter);
++ // Don't Download Firmware
++ Adapter->bFWReady = _FALSE;
++#elif RTL8192CU_FW_DOWNLOAD_ENABLE
++ status = FirmwareDownload92C(Adapter,_FALSE);
++ if(status != _SUCCESS)
++ {
++ Adapter->bFWReady = _FALSE;
++ pHalData->fw_ractrl = _FALSE;
++ DBG_8192C("fw download fail!\n");
++ goto exit;
++ }
++ else
++ {
++ Adapter->bFWReady = _TRUE;
++ pHalData->fw_ractrl = _TRUE;
++ DBG_8192C("fw download ok!\n");
++ }
++#endif
++
++ InitializeFirmwareVars92C(Adapter);
++
++ if(pwrctrlpriv->reg_rfoff == _TRUE){
++ pwrctrlpriv->rf_pwrstate = rf_off;
++ }
++
++ // 2010/08/09 MH We need to check if we need to turnon or off RF after detecting
++ // HW GPIO pin. Before PHY_RFConfig8192C.
++ //HalDetectPwrDownMode(Adapter);
++ // 2010/08/26 MH If Efuse does not support sective suspend then disable the function.
++ //HalDetectSelectiveSuspendMode(Adapter);
++
++ // Set RF type for BB/RF configuration
++ _InitRFType(Adapter);//->_ReadRFType()
++
++ // Save target channel
++ // <Roger_Notes> Current Channel will be updated again later.
++ pHalData->CurrentChannel = 6;//default set to 6
++
++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_LLTT);
++ if(!pregistrypriv->wifi_spec){
++ boundary = TX_PAGE_BOUNDARY;
++ }
++ else{// for WMM
++ boundary = WMM_NORMAL_TX_PAGE_BOUNDARY;
++ }
++ status = InitLLTTable(Adapter, boundary);
++ if(status == _FAIL){
++ RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("Failed to init LLT table\n"));
++ goto exit;
++ }
++
++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MAC);
++#if (HAL_MAC_ENABLE == 1)
++ status = PHY_MACConfig8192C(Adapter);
++ if(status == _FAIL)
++ {
++ goto exit;
++ }
++#endif
++
++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC02);
++ // Get Rx PHY status in order to report RSSI and others.
++ _InitDriverInfoSize(Adapter, DRVINFO_SZ);
++
++ _InitInterrupt(Adapter);
++ hal_init_macaddr(Adapter);//set mac_address
++ _InitNetworkType(Adapter);//set msr
++ _InitWMACSetting(Adapter);
++ _InitAdaptiveCtrl(Adapter);
++ _InitEDCA(Adapter);
++ _InitRateFallback(Adapter);
++ _InitRetryFunction(Adapter);
++ InitUsbAggregationSetting(Adapter);
++ _InitOperationMode(Adapter);//todo
++ _InitBeaconParameters(Adapter);
++ _InitBeaconMaxError(Adapter, _TRUE);
++
++#if defined(CONFIG_CONCURRENT_MODE) || defined(CONFIG_TX_MCAST2UNI)
++
++#ifdef CONFIG_CHECK_AC_LIFETIME
++ // Enable lifetime check for the four ACs
++ rtw_write8(Adapter, REG_LIFETIME_EN, 0x0F);
++#endif // CONFIG_CHECK_AC_LIFETIME
++
++#ifdef CONFIG_TX_MCAST2UNI
++ rtw_write16(Adapter, REG_PKT_VO_VI_LIFE_TIME, 0x0400); // unit: 256us. 256ms
++ rtw_write16(Adapter, REG_PKT_BE_BK_LIFE_TIME, 0x0400); // unit: 256us. 256ms
++#else // CONFIG_TX_MCAST2UNI
++ rtw_write16(Adapter, REG_PKT_VO_VI_LIFE_TIME, 0x3000); // unit: 256us. 3s
++ rtw_write16(Adapter, REG_PKT_BE_BK_LIFE_TIME, 0x3000); // unit: 256us. 3s
++#endif // CONFIG_TX_MCAST2UNI
++#endif // CONFIG_CONCURRENT_MODE || CONFIG_TX_MCAST2UNI
++
++
++#ifdef CONFIG_LED
++ _InitHWLed(Adapter);
++#endif //CONFIG_LED
++
++ //
++ //d. Initialize BB related configurations.
++ //
++
++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BB);
++#if (HAL_BB_ENABLE == 1)
++ status = PHY_BBConfig8192C(Adapter);
++ if(status == _FAIL)
++ {
++ goto exit;
++ }
++#endif
++
++ // 92CU use 3-wire to r/w RF
++ //pHalData->Rf_Mode = RF_OP_By_SW_3wire;
++
++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_RF);
++#if (HAL_RF_ENABLE == 1)
++ status = PHY_RFConfig8192C(Adapter);
++ if(status == _FAIL)
++ {
++ goto exit;
++ }
++
++ if(IS_VENDOR_UMC_A_CUT(pHalData->VersionID) && !IS_92C_SERIAL(pHalData->VersionID))
++ {
++ PHY_SetRFReg(Adapter, RF_PATH_A, RF_RX_G1, bMaskDWord, 0x30255);
++ PHY_SetRFReg(Adapter, RF_PATH_A, RF_RX_G2, bMaskDWord, 0x50a00);
++ }
++#endif
++
++ //
++ // Joseph Note: Keep RfRegChnlVal for later use.
++ //
++ pHalData->RfRegChnlVal[0] = PHY_QueryRFReg(Adapter, (RF_RADIO_PATH_E)0, RF_CHNLBW, bRFRegOffsetMask);
++ pHalData->RfRegChnlVal[1] = PHY_QueryRFReg(Adapter, (RF_RADIO_PATH_E)1, RF_CHNLBW, bRFRegOffsetMask);
++
++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_TURN_ON_BLOCK);
++ _BBTurnOnBlock(Adapter);
++ //NicIFSetMacAddress(padapter, padapter->PermanentAddress);
++
++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_SECURITY);
++ invalidate_cam_all(Adapter);
++
++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC11);
++ // 2010/12/17 MH We need to set TX power according to EFUSE content at first.
++ PHY_SetTxPowerLevel8192C(Adapter, pHalData->CurrentChannel);
++
++// Move by Neo for USB SS to below setp
++//_RfPowerSave(Adapter);
++
++ if (!IS_92C_SERIAL( pHalData->VersionID) && (pHalData->AntDivCfg!=0))
++ { //for 88CU ,1T1R
++ _InitAntenna_Selection(Adapter);
++ }
++
++
++ //
++ // Disable BAR, suggested by Scott
++ // 2010.04.09 add by hpfan
++ //
++ rtw_write32(Adapter, REG_BAR_MODE_CTRL, 0x0201ffff);
++
++ // HW SEQ CTRL
++ //set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM.
++ rtw_write8(Adapter,REG_HWSEQ_CTRL, 0xFF);
++
++ if(pregistrypriv->wifi_spec)
++ rtw_write16(Adapter,REG_FAST_EDCA_CTRL ,0);
++
++ //Nav limit , suggest by scott
++ rtw_write8(Adapter, 0x652, 0x0);
++
++#if (MP_DRIVER == 1)
++ Adapter->mppriv.channel = pHalData->CurrentChannel;
++ MPT_InitializeAdapter(Adapter, Adapter->mppriv.channel);
++#else
++ //
++ // 2010/08/11 MH Merge from 8192SE for Minicard init. We need to confirm current radio status
++ // and then decide to enable RF or not.!!!??? For Selective suspend mode. We may not
++ // call init_adapter. May cause some problem??
++ //
++ // Fix the bug that Hw/Sw radio off before S3/S4, the RF off action will not be executed
++ // in MgntActSet_RF_State() after wake up, because the value of pHalData->eRFPowerState
++ // is the same as eRfOff, we should change it to eRfOn after we config RF parameters.
++ // Added by tynli. 2010.03.30.
++ pwrctrlpriv->rf_pwrstate = rf_on;
++
++#if 0 //to do
++ RT_CLEAR_PS_LEVEL(pwrctrlpriv, RT_RF_OFF_LEVL_HALT_NIC);
++#if 1 //Todo
++ // 20100326 Joseph: Copy from GPIOChangeRFWorkItemCallBack() function to check HW radio on/off.
++ // 20100329 Joseph: Revise and integrate the HW/SW radio off code in initialization.
++
++ eRfPowerStateToSet = (rt_rf_power_state) RfOnOffDetect(Adapter);
++ pwrctrlpriv->rfoff_reason |= eRfPowerStateToSet==rf_on ? RF_CHANGE_BY_INIT : RF_CHANGE_BY_HW;
++ pwrctrlpriv->rfoff_reason |= (pwrctrlpriv->reg_rfoff) ? RF_CHANGE_BY_SW : 0;
++
++ if(pwrctrlpriv->rfoff_reason&RF_CHANGE_BY_HW)
++ pwrctrlpriv->b_hw_radio_off = _TRUE;
++
++ DBG_8192C("eRfPowerStateToSet=%d\n", eRfPowerStateToSet);
++
++ if(pwrctrlpriv->reg_rfoff == _TRUE)
++ { // User disable RF via registry.
++ DBG_8192C("InitializeAdapter8192CU(): Turn off RF for RegRfOff.\n");
++ //MgntActSet_RF_State(Adapter, rf_off, RF_CHANGE_BY_SW, _TRUE);
++
++ // Those action will be discard in MgntActSet_RF_State because off the same state
++ //for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
++ //PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)eRFPath, 0x4, 0xC00, 0x0);
++ }
++ else if(pwrctrlpriv->rfoff_reason > RF_CHANGE_BY_PS)
++ { // H/W or S/W RF OFF before sleep.
++ DBG_8192C(" Turn off RF for RfOffReason(%x) ----------\n", pwrctrlpriv->rfoff_reason);
++ //pwrctrlpriv->rfoff_reason = RF_CHANGE_BY_INIT;
++ pwrctrlpriv->rf_pwrstate = rf_on;
++ //MgntActSet_RF_State(Adapter, rf_off, pwrctrlpriv->rfoff_reason, _TRUE);
++ }
++ else
++ {
++ // Perform GPIO polling to find out current RF state. added by Roger, 2010.04.09.
++ if(pHalData->BoardType == BOARD_MINICARD /*&& (Adapter->MgntInfo.PowerSaveControl.bGpioRfSw)*/)
++ {
++ DBG_8192C("InitializeAdapter8192CU(): RF=%d \n", eRfPowerStateToSet);
++ if (eRfPowerStateToSet == rf_off)
++ {
++ //MgntActSet_RF_State(Adapter, rf_off, RF_CHANGE_BY_HW, _TRUE);
++ pwrctrlpriv->b_hw_radio_off = _TRUE;
++ }
++ else
++ {
++ pwrctrlpriv->rf_pwrstate = rf_off;
++ pwrctrlpriv->rfoff_reason = RF_CHANGE_BY_INIT;
++ pwrctrlpriv->b_hw_radio_off = _FALSE;
++ //MgntActSet_RF_State(Adapter, rf_on, pwrctrlpriv->rfoff_reason, _TRUE);
++ }
++ }
++ else
++ {
++ pwrctrlpriv->rf_pwrstate = rf_off;
++ pwrctrlpriv->rfoff_reason = RF_CHANGE_BY_INIT;
++ //MgntActSet_RF_State(Adapter, rf_on, pwrctrlpriv->rfoff_reason, _TRUE);
++ }
++
++ pwrctrlpriv->rfoff_reason = 0;
++ pwrctrlpriv->b_hw_radio_off = _FALSE;
++ pwrctrlpriv->rf_pwrstate = rf_on;
++ rtw_led_control(Adapter, LED_CTL_POWER_ON);
++
++ }
++
++ // 2010/-8/09 MH For power down module, we need to enable register block contrl reg at 0x1c.
++ // Then enable power down control bit of register 0x04 BIT4 and BIT15 as 1.
++ if(pHalData->pwrdown && eRfPowerStateToSet == rf_off)
++ {
++ // Enable register area 0x0-0xc.
++ rtw_write8(Adapter, REG_RSV_CTRL, 0x0);
++
++ //
++ // <Roger_Notes> We should configure HW PDn source for WiFi ONLY, and then
++ // our HW will be set in power-down mode if PDn source from all functions are configured.
++ // 2010.10.06.
++ //
++ //if(IS_HARDWARE_TYPE_8723AU(Adapter))
++ //{
++ // u1bTmp = rtw_read8(Adapter, REG_MULTI_FUNC_CTRL);
++ // rtw_write8(Adapter, REG_MULTI_FUNC_CTRL, (u1bTmp|WL_HWPDN_EN));
++ //}
++ //else
++ //{
++ rtw_write16(Adapter, REG_APS_FSMCO, 0x8812);
++ //}
++ }
++ //DrvIFIndicateCurrentPhyStatus(Adapter); // 2010/08/17 MH Disable to prevent BSOD.
++#endif
++#endif
++
++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_IQK);
++ // 2010/08/26 MH Merge from 8192CE.
++ if(pwrctrlpriv->rf_pwrstate == rf_on)
++ {
++ if(pHalData->bIQKInitialized ){
++ rtl8192c_PHY_IQCalibrate(Adapter,_TRUE);
++ }
++ else
++ {
++ rtl8192c_PHY_IQCalibrate(Adapter,_FALSE);
++ pHalData->bIQKInitialized = _TRUE;
++ }
++
++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_PW_TRACK);
++ rtl8192c_dm_CheckTXPowerTracking(Adapter);
++
++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_LCK);
++ rtl8192c_PHY_LCCalibrate(Adapter);
++ }
++#endif /* #if (MP_DRIVER == 1) */
++
++
++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC21);
++#if RTL8192CU_ADHOC_WORKAROUND_SETTING
++ _InitAdhocWorkaroundParams(Adapter);
++#endif
++
++
++#ifdef USB_INTERFERENCE_ISSUE
++ //fixed USB interface interference issue
++ rtw_write8(Adapter, 0xfe40, 0xe0);
++ rtw_write8(Adapter, 0xfe41, 0x8d);
++ rtw_write8(Adapter, 0xfe42, 0x80);
++ rtw_write32(Adapter,0x20c,0xfd0320);
++#if 1
++ //2011/01/07 ,suggest by Johnny,for solved the problem that too many protocol error on USB bus
++ if(!IS_VENDOR_UMC_A_CUT(pHalData->VersionID) )//&& !IS_92C_SERIAL(pHalData->VersionID))// TSMC , 8188
++ {
++ // 0xE6=0x94
++ rtw_write8(Adapter, 0xFE40, 0xE6);
++ rtw_write8(Adapter, 0xFE41, 0x94);
++ rtw_write8(Adapter, 0xFE42, 0x80);
++
++ // 0xE0=0x19
++ rtw_write8(Adapter, 0xFE40, 0xE0);
++ rtw_write8(Adapter, 0xFE41, 0x19);
++ rtw_write8(Adapter, 0xFE42, 0x80);
++
++ // 0xE5=0x91
++ rtw_write8(Adapter, 0xFE40, 0xE5);
++ rtw_write8(Adapter, 0xFE41, 0x91);
++ rtw_write8(Adapter, 0xFE42, 0x80);
++
++ // 0xE2=0x81
++ rtw_write8(Adapter, 0xFE40, 0xE2);
++ rtw_write8(Adapter, 0xFE41, 0x81);
++ rtw_write8(Adapter, 0xFE42, 0x80);
++
++ }
++
++#endif
++#endif //USB_INTERFERENCE_ISSUE
++
++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_PABIAS);
++ _InitPABias(Adapter);
++
++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BT_COEXIST);
++#ifdef CONFIG_BT_COEXIST
++ _InitBTCoexist(Adapter);
++#endif
++
++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_HAL_DM);
++ rtl8192c_InitHalDm(Adapter);
++
++ // 2010/08/23 MH According to Alfred's suggestion, we need to to prevent HW enter
++ // suspend mode automatically.
++ //HwSuspendModeEnable92Cu(Adapter, _FALSE);
++
++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC31);
++ rtw_write8(Adapter, 0x15, 0xe9);//suggest by Johnny for lower temperature
++
++ rtw_write8(Adapter, 0xc87, 0x50);//suggest by Jackson for CCA
++
++ //_dbg_dump_macreg(padapter);
++
++ rtw_write16(Adapter, REG_BCN_CTRL, 0x1818); // For 2 PORT TSF SYNC
++
++
++
++#ifdef CONFIG_XMIT_ACK
++ //ack for xmit mgmt frames.
++ rtw_write32(Adapter, REG_FWHW_TXQ_CTRL, rtw_read32(Adapter, REG_FWHW_TXQ_CTRL)|BIT(12));
++#endif //CONFIG_XMIT_ACK
++
++exit:
++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_END);
++
++ DBG_871X("%s in %dms\n", __FUNCTION__, rtw_get_passing_time_ms(init_start_time));
++
++ #ifdef DBG_HAL_INIT_PROFILING
++ hal_init_stages_timestamp[HAL_INIT_STAGES_END]=rtw_get_current_time();
++
++ for(hal_init_profiling_i=0;hal_init_profiling_i<HAL_INIT_STAGES_NUM-1;hal_init_profiling_i++) {
++ DBG_871X("DBG_HAL_INIT_PROFILING: %35s, %u, %5u, %5u\n"
++ , hal_init_stages_str[hal_init_profiling_i]
++ , hal_init_stages_timestamp[hal_init_profiling_i]
++ , (hal_init_stages_timestamp[hal_init_profiling_i+1]-hal_init_stages_timestamp[hal_init_profiling_i])
++ , rtw_get_time_interval_ms(hal_init_stages_timestamp[hal_init_profiling_i], hal_init_stages_timestamp[hal_init_profiling_i+1])
++ );
++ }
++ #endif
++
++
++_func_exit_;
++
++ return status;
++}
++
++
++#define SYNC_SD7_20110802_phy_SsPwrSwitch92CU
++#ifdef SYNC_SD7_20110802_phy_SsPwrSwitch92CU
++
++VOID
++phy_SsPwrSwitch92CU(
++ IN PADAPTER Adapter,
++ IN rt_rf_power_state eRFPowerState,
++ IN int bRegSSPwrLvl
++ )
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ u8 value8;
++
++ switch( eRFPowerState )
++ {
++ case rf_on:
++ if (bRegSSPwrLvl == 1)
++ {
++ // 1. Enable MAC Clock. Can not be enabled now.
++ //WriteXBYTE(REG_SYS_CLKR+1, ReadXBYTE(REG_SYS_CLKR+1) | BIT(3));
++
++ // 2. Force PWM, Enable SPS18_LDO_Marco_Block
++ rtw_write8(Adapter, REG_SPS0_CTRL,
++ rtw_read8(Adapter, REG_SPS0_CTRL) | (BIT0|BIT3));
++
++ // 3. restore BB, AFE control register.
++ //RF
++ if (pHalData->rf_type == RF_2T2R)
++ PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, 0x380038, 1);
++ else
++ PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, 0x38, 1);
++ PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, 0xf0, 1);
++ PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT1, 0);
++
++ //AFE
++ //DbgPrint("0x0e70 = %x\n", Adapter->PS_BBRegBackup[PSBBREG_AFE0]);
++ //PHY_SetBBReg(Adapter, 0x0e70, bMaskDWord ,Adapter->PS_BBRegBackup[PSBBREG_AFE0] );
++ //PHY_SetBBReg(Adapter, 0x0e70, bMaskDWord ,0x631B25A0 );
++ if (pHalData->rf_type == RF_2T2R)
++ PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord ,0x63DB25A0 );
++ else if (pHalData->rf_type == RF_1T1R)
++ PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord ,0x631B25A0 );
++
++ // 4. issue 3-wire command that RF set to Rx idle mode. This is used to re-write the RX idle mode.
++ // We can only prvide a usual value instead and then HW will modify the value by itself.
++ PHY_SetRFReg(Adapter,RF_PATH_A, 0, bRFRegOffsetMask,0x32D95);
++ if (pHalData->rf_type == RF_2T2R)
++ {
++ PHY_SetRFReg(Adapter,RF_PATH_B, 0, bRFRegOffsetMask,0x32D95);
++ }
++ }
++ else // Level 2 or others.
++ {
++ //h. AFE_PLL_CTRL 0x28[7:0] = 0x80 //disable AFE PLL
++ rtw_write8(Adapter, REG_AFE_PLL_CTRL, 0x81);
++
++ // i. AFE_XTAL_CTRL 0x24[15:0] = 0x880F //gated AFE DIG_CLOCK
++ rtw_write16(Adapter, REG_AFE_XTAL_CTRL, 0x800F);
++ rtw_mdelay_os(1);
++
++ // 1. Enable MAC Clock. Can not be enabled now.
++ //WriteXBYTE(REG_SYS_CLKR+1, ReadXBYTE(REG_SYS_CLKR+1) | BIT(3));
++
++ // 2. Force PWM, Enable SPS18_LDO_Marco_Block
++ rtw_write8(Adapter, REG_SPS0_CTRL,
++ rtw_read8(Adapter, REG_SPS0_CTRL) | (BIT0|BIT3));
++
++ // 3. restore BB, AFE control register.
++ //RF
++ if (pHalData->rf_type == RF_2T2R)
++ PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, 0x380038, 1);
++ else
++ PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, 0x38, 1);
++ PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, 0xf0, 1);
++ PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT1, 0);
++
++ //AFE
++ if (pHalData->rf_type == RF_2T2R)
++ PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord ,0x63DB25A0 );
++ else if (pHalData->rf_type == RF_1T1R)
++ PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord ,0x631B25A0 );
++
++ // 4. issue 3-wire command that RF set to Rx idle mode. This is used to re-write the RX idle mode.
++ // We can only prvide a usual value instead and then HW will modify the value by itself.
++ PHY_SetRFReg(Adapter,RF_PATH_A, 0, bRFRegOffsetMask,0x32D95);
++ if (pHalData->rf_type == RF_2T2R)
++ {
++ PHY_SetRFReg(Adapter,RF_PATH_B, 0, bRFRegOffsetMask,0x32D95);
++ }
++
++ // 5. gated MAC Clock
++ //WriteXBYTE(REG_SYS_CLKR+1, ReadXBYTE(REG_SYS_CLKR+1) & ~(BIT(3)));
++ //PlatformEFIOWrite1Byte(Adapter, REG_SYS_CLKR+1, PlatformEFIORead1Byte(Adapter, REG_SYS_CLKR+1)|(BIT3));
++
++ {
++ //u8 eRFPath = RF_PATH_A,value8 = 0, retry = 0;
++ u8 bytetmp;
++ //PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)eRFPath, 0x0, bMaskByte0, 0x0);
++ // 2010/08/12 MH Add for B path under SS test.
++ //if (pHalData->RF_Type == RF_2T2R)
++ //PHY_SetRFReg(Adapter, RF_PATH_B, 0x0, bMaskByte0, 0x0);
++
++ bytetmp = rtw_read8(Adapter, REG_APSD_CTRL);
++ rtw_write8(Adapter, REG_APSD_CTRL, bytetmp & ~BIT6);
++
++ rtw_mdelay_os(10);
++
++ // Set BB reset at first
++ rtw_write8(Adapter, REG_SYS_FUNC_EN, 0x17 );//0x16
++ //undo clock gated
++ rtw_write32(Adapter, rFPGA0_XCD_RFParameter, rtw_read32(Adapter, rFPGA0_XCD_RFParameter)&(~BIT31));
++ // Enable TX
++ rtw_write8(Adapter, REG_TXPAUSE, 0x0);
++ }
++ //Adapter->HalFunc.InitializeAdapterHandler(Adapter, Adapter->MgntInfo.dot11CurrentChannelNumber);
++ //CardSelectiveSuspendLeave(Adapter);
++ }
++
++ break;
++
++ case rf_sleep:
++ case rf_off:
++ value8 = rtw_read8(Adapter, REG_SPS0_CTRL) ;
++ if (IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID))
++ value8 &= ~(BIT0);
++ else
++ value8 &= ~(BIT0|BIT3);
++ if (bRegSSPwrLvl == 1)
++ {
++ //RT_TRACE(COMP_POWER, DBG_LOUD, ("SS LVL1\n"));
++ // Disable RF and BB only for SelectSuspend.
++
++ // 1. Set BB/RF to shutdown.
++ // (1) Reg878[5:3]= 0 // RF rx_code for preamble power saving
++ // (2)Reg878[21:19]= 0 //Turn off RF-B
++ // (3) RegC04[7:4]= 0 // turn off all paths for packet detection
++ // (4) Reg800[1] = 1 // enable preamble power saving
++ Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF0] = PHY_QueryBBReg(Adapter, rFPGA0_XAB_RFParameter, bMaskDWord);
++ Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF1] = PHY_QueryBBReg(Adapter, rOFDM0_TRxPathEnable, bMaskDWord);
++ Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF2] = PHY_QueryBBReg(Adapter, rFPGA0_RFMOD, bMaskDWord);
++ if (pHalData->rf_type == RF_2T2R)
++ {
++ PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, 0x380038, 0);
++ }
++ else if (pHalData->rf_type == RF_1T1R)
++ {
++ PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, 0x38, 0);
++ }
++ PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, 0xf0, 0);
++ PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT1,1);
++
++ // 2 .AFE control register to power down. bit[30:22]
++ Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_AFE0] = PHY_QueryBBReg(Adapter, rRx_Wait_CCA, bMaskDWord);
++ if (pHalData->rf_type == RF_2T2R)
++ PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord ,0x00DB25A0);
++ else if (pHalData->rf_type == RF_1T1R)
++ PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord ,0x001B25A0);
++
++ // 3. issue 3-wire command that RF set to power down.
++ PHY_SetRFReg(Adapter,RF_PATH_A, 0, bRFRegOffsetMask,0);
++ if (pHalData->rf_type == RF_2T2R)
++ {
++ PHY_SetRFReg(Adapter,RF_PATH_B, 0, bRFRegOffsetMask,0);
++ }
++
++ // 4. Force PFM , disable SPS18_LDO_Marco_Block
++ rtw_write8(Adapter, REG_SPS0_CTRL, value8);
++
++ // 5. gated MAC Clock
++ //WriteXBYTE(REG_SYS_CLKR+1, ReadXBYTE(REG_SYS_CLKR+1) & ~(BIT(3)));
++ }
++ else // Level 2 or others.
++ {
++ //RT_TRACE(COMP_POWER, DBG_LOUD, ("SS LVL2\n"));
++ {
++ u8 eRFPath = RF_PATH_A,value8 = 0;
++ rtw_write8(Adapter, REG_TXPAUSE, 0xFF);
++ PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)eRFPath, 0x0, bMaskByte0, 0x0);
++ // 2010/08/12 MH Add for B path under SS test.
++ //if (pHalData->RF_Type == RF_2T2R)
++ //PHY_SetRFReg(Adapter, RF_PATH_B, 0x0, bMaskByte0, 0x0);
++
++ value8 |= APSDOFF;
++ rtw_write8(Adapter, REG_APSD_CTRL, value8);//0x40
++
++ // After switch APSD, we need to delay for stability
++ rtw_mdelay_os(10);
++ //before BB reset should do clock gated
++ rtw_write32(Adapter, rFPGA0_XCD_RFParameter, rtw_read32(Adapter, rFPGA0_XCD_RFParameter)|(BIT31));
++ // Set BB reset at first
++ value8 = 0 ;
++ value8 |=( FEN_USBD | FEN_USBA | FEN_BB_GLB_RSTn);
++ rtw_write8(Adapter, REG_SYS_FUNC_EN,value8 );//0x16
++ }
++
++ // Disable RF and BB only for SelectSuspend.
++
++ // 1. Set BB/RF to shutdown.
++ // (1) Reg878[5:3]= 0 // RF rx_code for preamble power saving
++ // (2)Reg878[21:19]= 0 //Turn off RF-B
++ // (3) RegC04[7:4]= 0 // turn off all paths for packet detection
++ // (4) Reg800[1] = 1 // enable preamble power saving
++ Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF0] = PHY_QueryBBReg(Adapter, rFPGA0_XAB_RFParameter, bMaskDWord);
++ Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF1] = PHY_QueryBBReg(Adapter, rOFDM0_TRxPathEnable, bMaskDWord);
++ Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF2] = PHY_QueryBBReg(Adapter, rFPGA0_RFMOD, bMaskDWord);
++ if (pHalData->rf_type == RF_2T2R)
++ {
++ PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, 0x380038, 0);
++ }
++ else if (pHalData->rf_type == RF_1T1R)
++ {
++ PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, 0x38, 0);
++ }
++ PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, 0xf0, 0);
++ PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT1,1);
++
++ // 2 .AFE control register to power down. bit[30:22]
++ Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_AFE0] = PHY_QueryBBReg(Adapter, rRx_Wait_CCA, bMaskDWord);
++ if (pHalData->rf_type == RF_2T2R)
++ PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord ,0x00DB25A0);
++ else if (pHalData->rf_type == RF_1T1R)
++ PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord ,0x001B25A0);
++
++ // 3. issue 3-wire command that RF set to power down.
++ PHY_SetRFReg(Adapter,RF_PATH_A, 0, bRFRegOffsetMask,0);
++ if (pHalData->rf_type == RF_2T2R)
++ {
++ PHY_SetRFReg(Adapter,RF_PATH_B, 0, bRFRegOffsetMask,0);
++ }
++
++ // 4. Force PFM , disable SPS18_LDO_Marco_Block
++ rtw_write8(Adapter, REG_SPS0_CTRL, value8);
++
++ // 2010/10/13 MH/Isaachsu exchange sequence.
++ //h. AFE_PLL_CTRL 0x28[7:0] = 0x80 //disable AFE PLL
++ rtw_write8(Adapter, REG_AFE_PLL_CTRL, 0x80);
++ rtw_mdelay_os(1);
++
++ // i. AFE_XTAL_CTRL 0x24[15:0] = 0x880F //gated AFE DIG_CLOCK
++ rtw_write16(Adapter, REG_AFE_XTAL_CTRL, 0xA80F);
++
++ // 5. gated MAC Clock
++ //WriteXBYTE(REG_SYS_CLKR+1, ReadXBYTE(REG_SYS_CLKR+1) & ~(BIT(3)));
++ //PlatformEFIOWrite1Byte(Adapter, REG_SYS_CLKR+1, PlatformEFIORead1Byte(Adapter, REG_SYS_CLKR+1)& ~(BIT3))
++
++ //CardSelectiveSuspendEnter(Adapter);
++ }
++
++ break;
++
++ default:
++ break;
++ }
++
++} // phy_PowerSwitch92CU
++
++void _ps_open_RF(_adapter *padapter) {
++ //here call with bRegSSPwrLvl 1, bRegSSPwrLvl 2 needs to be verified
++ phy_SsPwrSwitch92CU(padapter, rf_on, 1);
++}
++
++void _ps_close_RF(_adapter *padapter){
++ //here call with bRegSSPwrLvl 1, bRegSSPwrLvl 2 needs to be verified
++ phy_SsPwrSwitch92CU(padapter, rf_off, 1);
++}
++#endif //SYNC_SD7_20110802_phy_SsPwrSwitch92CU
++
++
++
++static VOID
++_DisableGPIO(
++ IN PADAPTER Adapter
++ )
++{
++/***************************************
++j. GPIO_PIN_CTRL 0x44[31:0]=0x000 //
++k. Value = GPIO_PIN_CTRL[7:0]
++l. GPIO_PIN_CTRL 0x44[31:0] = 0x00FF0000 | (value <<8); //write external PIN level
++m. GPIO_MUXCFG 0x42 [15:0] = 0x0780
++n. LEDCFG 0x4C[15:0] = 0x8080
++***************************************/
++ u8 value8;
++ u16 value16;
++ u32 value32;
++
++ //1. Disable GPIO[7:0]
++ rtw_write16(Adapter, REG_GPIO_PIN_CTRL+2, 0x0000);
++ value32 = rtw_read32(Adapter, REG_GPIO_PIN_CTRL) & 0xFFFF00FF;
++ value8 = (u8) (value32&0x000000FF);
++ value32 |= ((value8<<8) | 0x00FF0000);
++ rtw_write32(Adapter, REG_GPIO_PIN_CTRL, value32);
++
++ //2. Disable GPIO[10:8]
++ rtw_write8(Adapter, REG_GPIO_MUXCFG+3, 0x00);
++ value16 = rtw_read16(Adapter, REG_GPIO_MUXCFG+2) & 0xFF0F;
++ value8 = (u8) (value16&0x000F);
++ value16 |= ((value8<<4) | 0x0780);
++ rtw_write16(Adapter, REG_GPIO_MUXCFG+2, value16);
++
++ //3. Disable LED0 & 1
++ rtw_write16(Adapter, REG_LEDCFG0, 0x8080);
++
++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("======> Disable GPIO and LED.\n"));
++
++} //end of _DisableGPIO()
++
++static VOID
++_ResetFWDownloadRegister(
++ IN PADAPTER Adapter
++ )
++{
++ u32 value32;
++
++ value32 = rtw_read32(Adapter, REG_MCUFWDL);
++ value32 &= ~(MCUFWDL_EN | MCUFWDL_RDY);
++ rtw_write32(Adapter, REG_MCUFWDL, value32);
++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("Reset FW download register.\n"));
++}
++
++
++static int
++_DisableRF_AFE(
++ IN PADAPTER Adapter
++ )
++{
++ int rtStatus = _SUCCESS;
++ u32 pollingCount = 0;
++ u8 value8;
++
++ //disable RF/ AFE AD/DA
++ value8 = APSDOFF;
++ rtw_write8(Adapter, REG_APSD_CTRL, value8);
++
++
++#if (RTL8192CU_ASIC_VERIFICATION)
++
++ do
++ {
++ if(rtw_read8(Adapter, REG_APSD_CTRL) & APSDOFF_STATUS){
++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("Disable RF, AFE, AD, DA Done!\n"));
++ break;
++ }
++
++ if(pollingCount++ > POLLING_READY_TIMEOUT_COUNT){
++ //RT_TRACE(COMP_INIT, DBG_SERIOUS, ("Failed to polling APSDOFF_STATUS done!\n"));
++ return _FAIL;
++ }
++
++ }while(_TRUE);
++
++#endif
++
++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("Disable RF, AFE,AD, DA.\n"));
++ return rtStatus;
++
++}
++
++static VOID
++_ResetBB(
++ IN PADAPTER Adapter
++ )
++{
++ u16 value16;
++
++ //before BB reset should do clock gated
++ rtw_write32(Adapter, rFPGA0_XCD_RFParameter, rtw_read32(Adapter, rFPGA0_XCD_RFParameter)|(BIT31));
++ //reset BB
++ value16 = rtw_read16(Adapter, REG_SYS_FUNC_EN);
++ value16 &= ~(FEN_BBRSTB | FEN_BB_GLB_RSTn);
++ rtw_write16(Adapter, REG_SYS_FUNC_EN, value16);
++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("Reset BB.\n"));
++}
++
++static VOID
++_ResetMCU(
++ IN PADAPTER Adapter
++ )
++{
++ u16 value16;
++
++ // reset MCU
++ value16 = rtw_read16(Adapter, REG_SYS_FUNC_EN);
++ value16 &= ~FEN_CPUEN;
++ rtw_write16(Adapter, REG_SYS_FUNC_EN, value16);
++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("Reset MCU.\n"));
++}
++
++static VOID
++_DisableMAC_AFE_PLL(
++ IN PADAPTER Adapter
++ )
++{
++ u32 value32;
++
++ //disable MAC/ AFE PLL
++ value32 = rtw_read32(Adapter, REG_APS_FSMCO);
++ value32 |= APDM_MAC;
++ rtw_write32(Adapter, REG_APS_FSMCO, value32);
++
++ value32 |= APFM_OFF;
++ rtw_write32(Adapter, REG_APS_FSMCO, value32);
++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("Disable MAC, AFE PLL.\n"));
++}
++
++static VOID
++_AutoPowerDownToHostOff(
++ IN PADAPTER Adapter
++ )
++{
++ u32 value32;
++ rtw_write8(Adapter, REG_SPS0_CTRL, 0x22);
++
++ value32 = rtw_read32(Adapter, REG_APS_FSMCO);
++
++ value32 |= APDM_HOST;//card disable
++ rtw_write32(Adapter, REG_APS_FSMCO, value32);
++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("Auto Power Down to Host-off state.\n"));
++
++ // set USB suspend
++ value32 = rtw_read32(Adapter, REG_APS_FSMCO);
++ value32 &= ~AFSM_PCIE;
++ rtw_write32(Adapter, REG_APS_FSMCO, value32);
++
++}
++
++static VOID
++_SetUsbSuspend(
++ IN PADAPTER Adapter
++ )
++{
++ u32 value32;
++
++ value32 = rtw_read32(Adapter, REG_APS_FSMCO);
++
++ // set USB suspend
++ value32 |= AFSM_HSUS;
++ rtw_write32(Adapter, REG_APS_FSMCO, value32);
++
++ //RT_ASSERT(0 == (rtw_read32(Adapter, REG_APS_FSMCO) & BIT(12)),(""));
++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("Set USB suspend.\n"));
++
++}
++
++static VOID
++_DisableRFAFEAndResetBB(
++ IN PADAPTER Adapter
++ )
++{
++/**************************************
++a. TXPAUSE 0x522[7:0] = 0xFF //Pause MAC TX queue
++b. RF path 0 offset 0x00 = 0x00 // disable RF
++c. APSD_CTRL 0x600[7:0] = 0x40
++d. SYS_FUNC_EN 0x02[7:0] = 0x16 //reset BB state machine
++e. SYS_FUNC_EN 0x02[7:0] = 0x14 //reset BB state machine
++***************************************/
++ u8 eRFPath = 0,value8 = 0;
++ rtw_write8(Adapter, REG_TXPAUSE, 0xFF);
++ PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)eRFPath, 0x0, bMaskByte0, 0x0);
++
++ value8 |= APSDOFF;
++ rtw_write8(Adapter, REG_APSD_CTRL, value8);//0x40
++ //before BB reset should do clock gated
++ rtw_write32(Adapter, rFPGA0_XCD_RFParameter, rtw_read32(Adapter, rFPGA0_XCD_RFParameter)|(BIT31));
++ value8 = 0 ;
++ value8 |=( FEN_USBD | FEN_USBA | FEN_BB_GLB_RSTn);
++ rtw_write8(Adapter, REG_SYS_FUNC_EN,value8 );//0x16
++
++ value8 &=( ~FEN_BB_GLB_RSTn );
++ rtw_write8(Adapter, REG_SYS_FUNC_EN, value8); //0x14
++
++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("======> RF off and reset BB.\n"));
++}
++
++static VOID
++_ResetDigitalProcedure1(
++ IN PADAPTER Adapter,
++ IN BOOLEAN bWithoutHWSM
++ )
++{
++
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++
++ if(pHalData->FirmwareVersion <= 0x20){
++ #if 0
++ /*****************************
++ f. SYS_FUNC_EN 0x03[7:0]=0x54 // reset MAC register, DCORE
++ g. MCUFWDL 0x80[7:0]=0 // reset MCU ready status
++ ******************************/
++ u4Byte value32 = 0;
++ PlatformIOWrite1Byte(Adapter, REG_SYS_FUNC_EN+1, 0x54);
++ PlatformIOWrite1Byte(Adapter, REG_MCUFWDL, 0);
++ #else
++ /*****************************
++ f. MCUFWDL 0x80[7:0]=0 // reset MCU ready status
++ g. SYS_FUNC_EN 0x02[10]= 0 // reset MCU register, (8051 reset)
++ h. SYS_FUNC_EN 0x02[15-12]= 5 // reset MAC register, DCORE
++ i. SYS_FUNC_EN 0x02[10]= 1 // enable MCU register, (8051 enable)
++ ******************************/
++ u16 valu16 = 0;
++ rtw_write8(Adapter, REG_MCUFWDL, 0);
++
++ valu16 = rtw_read16(Adapter, REG_SYS_FUNC_EN);
++ rtw_write16(Adapter, REG_SYS_FUNC_EN, (valu16 & (~FEN_CPUEN)));//reset MCU ,8051
++
++ valu16 = rtw_read16(Adapter, REG_SYS_FUNC_EN)&0x0FFF;
++ rtw_write16(Adapter, REG_SYS_FUNC_EN, (valu16 |(FEN_HWPDN|FEN_ELDR)));//reset MAC
++
++ #ifdef DBG_SHOW_MCUFWDL_BEFORE_51_ENABLE
++ {
++ u8 val;
++ if( (val=rtw_read8(Adapter, REG_MCUFWDL)))
++ DBG_871X("DBG_SHOW_MCUFWDL_BEFORE_51_ENABLE %s:%d REG_MCUFWDL:0x%02x\n", __FUNCTION__, __LINE__, val);
++ }
++ #endif
++
++
++ valu16 = rtw_read16(Adapter, REG_SYS_FUNC_EN);
++ rtw_write16(Adapter, REG_SYS_FUNC_EN, (valu16 | FEN_CPUEN));//enable MCU ,8051
++
++
++ #endif
++ }
++ else{
++ u8 retry_cnts = 0;
++
++ if(rtw_read8(Adapter, REG_MCUFWDL) & BIT1)
++ { //IF fw in RAM code, do reset
++
++ rtw_write8(Adapter, REG_MCUFWDL, 0);
++ if(Adapter->bFWReady){
++ // 2010/08/25 MH Accordign to RD alfred's suggestion, we need to disable other
++ // HRCV INT to influence 8051 reset.
++ rtw_write8(Adapter, REG_FWIMR, 0x20);
++
++ rtw_write8(Adapter, REG_HMETFR+3, 0x20);//8051 reset by self
++
++ while( (retry_cnts++ <100) && (FEN_CPUEN &rtw_read16(Adapter, REG_SYS_FUNC_EN)))
++ {
++ rtw_udelay_os(50);//PlatformStallExecution(50);//us
++ }
++
++ if(retry_cnts >= 100){
++ DBG_8192C("%s #####=> 8051 reset failed!.........................\n", __FUNCTION__);
++ // if 8051 reset fail we trigger GPIO 0 for LA
++ //PlatformEFIOWrite4Byte( Adapter,
++ // REG_GPIO_PIN_CTRL,
++ // 0x00010100);
++ // 2010/08/31 MH According to Filen's info, if 8051 reset fail, reset MAC directly.
++ rtw_write8(Adapter, REG_SYS_FUNC_EN+1, 0x50); //Reset MAC and Enable 8051
++ rtw_mdelay_os(10);
++ }
++ else {
++ //DBG_871X("%s =====> 8051 reset success (%d) .\n", __FUNCTION__, retry_cnts);
++ }
++ }
++ else {
++ DBG_871X("%s =====> 8051 in RAM but !Adapter->bFWReady\n", __FUNCTION__);
++ }
++ }
++ else{
++ //DBG_871X("%s =====> 8051 in ROM.\n", __FUNCTION__);
++ }
++
++ #ifdef DBG_SHOW_MCUFWDL_BEFORE_51_ENABLE
++ {
++ u8 val;
++ if( (val=rtw_read8(Adapter, REG_MCUFWDL)))
++ DBG_871X("DBG_SHOW_MCUFWDL_BEFORE_51_ENABLE %s:%d REG_MCUFWDL:0x%02x\n", __FUNCTION__, __LINE__, val);
++ }
++ #endif
++
++ rtw_write8(Adapter, REG_SYS_FUNC_EN+1, 0x54); //Reset MAC and Enable 8051
++ }
++
++ // Clear rpwm value for initial toggle bit trigger.
++ rtw_write8(Adapter, REG_USB_HRPWM, 0x00);
++
++ if(bWithoutHWSM){
++ /*****************************
++ Without HW auto state machine
++ g. SYS_CLKR 0x08[15:0] = 0x30A3 //disable MAC clock
++ h. AFE_PLL_CTRL 0x28[7:0] = 0x80 //disable AFE PLL
++ i. AFE_XTAL_CTRL 0x24[15:0] = 0x880F //gated AFE DIG_CLOCK
++ j. SYS_ISO_CTRL 0x00[7:0] = 0xF9 // isolated digital to PON
++ ******************************/
++ //rtw_write16(Adapter, REG_SYS_CLKR, 0x30A3);
++ rtw_write16(Adapter, REG_SYS_CLKR, 0x70A3);//modify to 0x70A3 by Scott.
++ rtw_write8(Adapter, REG_AFE_PLL_CTRL, 0x80);
++ rtw_write16(Adapter, REG_AFE_XTAL_CTRL, 0x880F);
++ rtw_write8(Adapter, REG_SYS_ISO_CTRL, 0xF9);
++ }
++ else
++ {
++ // Disable all RF/BB power
++ rtw_write8(Adapter, REG_RF_CTRL, 0x00);
++ }
++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("======> Reset Digital.\n"));
++
++}
++
++static VOID
++_ResetDigitalProcedure2(
++ IN PADAPTER Adapter
++)
++{
++/*****************************
++k. SYS_FUNC_EN 0x03[7:0] = 0x44 // disable ELDR runction
++l. SYS_CLKR 0x08[15:0] = 0x3083 // disable ELDR clock
++m. SYS_ISO_CTRL 0x01[7:0] = 0x83 // isolated ELDR to PON
++******************************/
++ //rtw_write8(Adapter, REG_SYS_FUNC_EN+1, 0x44);//marked by Scott.
++ //rtw_write16(Adapter, REG_SYS_CLKR, 0x3083);
++ //rtw_write8(Adapter, REG_SYS_ISO_CTRL+1, 0x83);
++
++ rtw_write16(Adapter, REG_SYS_CLKR, 0x70a3); //modify to 0x70a3 by Scott.
++ rtw_write8(Adapter, REG_SYS_ISO_CTRL+1, 0x82); //modify to 0x82 by Scott.
++}
++
++static VOID
++_DisableAnalog(
++ IN PADAPTER Adapter,
++ IN BOOLEAN bWithoutHWSM
++ )
++{
++ u16 value16 = 0;
++ u8 value8=0;
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++
++ if(bWithoutHWSM){
++ /*****************************
++ n. LDOA15_CTRL 0x20[7:0] = 0x04 // disable A15 power
++ o. LDOV12D_CTRL 0x21[7:0] = 0x54 // disable digital core power
++ r. When driver call disable, the ASIC will turn off remaining clock automatically
++ ******************************/
++
++ rtw_write8(Adapter, REG_LDOA15_CTRL, 0x04);
++ //PlatformIOWrite1Byte(Adapter, REG_LDOV12D_CTRL, 0x54);
++
++ value8 = rtw_read8(Adapter, REG_LDOV12D_CTRL);
++ value8 &= (~LDV12_EN);
++ rtw_write8(Adapter, REG_LDOV12D_CTRL, value8);
++ //RT_TRACE(COMP_INIT, DBG_LOUD, (" REG_LDOV12D_CTRL Reg0x21:0x%02x.\n",value8));
++ }
++
++/*****************************
++h. SPS0_CTRL 0x11[7:0] = 0x23 //enter PFM mode
++i. APS_FSMCO 0x04[15:0] = 0x4802 // set USB suspend
++******************************/
++
++
++ value8 = 0x23;
++ if (IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID))
++ value8 |= BIT3;
++
++ rtw_write8(Adapter, REG_SPS0_CTRL, value8);
++
++
++ if(bWithoutHWSM)
++ {
++ //value16 |= (APDM_HOST | /*AFSM_HSUS |*/PFM_ALDN);
++ // 2010/08/31 According to Filen description, we need to use HW to shut down 8051 automatically.
++ // Becasue suspend operatione need the asistance of 8051 to wait for 3ms.
++ value16 |= (APDM_HOST | AFSM_HSUS |PFM_ALDN);
++ }
++ else
++ {
++ value16 |= (APDM_HOST | AFSM_HSUS |PFM_ALDN);
++ }
++
++ rtw_write16(Adapter, REG_APS_FSMCO,value16 );//0x4802
++
++ rtw_write8(Adapter, REG_RSV_CTRL, 0x0e);
++
++ #if 0
++ //tynli_test for suspend mode.
++ if(!bWithoutHWSM){
++ rtw_write8(Adapter, 0xfe10, 0x19);
++ }
++#endif
++
++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("======> Disable Analog Reg0x04:0x%04x.\n",value16));
++}
++
++static int
++CardDisableHWSM( // HW Auto state machine
++ IN PADAPTER Adapter,
++ IN BOOLEAN resetMCU
++ )
++{
++ int rtStatus = _SUCCESS;
++ if(Adapter->bSurpriseRemoved){
++ return rtStatus;
++ }
++#if 1
++ //==== RF Off Sequence ====
++ _DisableRFAFEAndResetBB(Adapter);
++
++ // ==== Reset digital sequence ======
++ _ResetDigitalProcedure1(Adapter, _FALSE);
++
++ // ==== Pull GPIO PIN to balance level and LED control ======
++ _DisableGPIO(Adapter);
++
++ // ==== Disable analog sequence ===
++ _DisableAnalog(Adapter, _FALSE);
++
++ RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("======> Card disable finished.\n"));
++#else
++ _DisableGPIO(Adapter);
++
++ //reset FW download register
++ _ResetFWDownloadRegister(Adapter);
++
++
++ //disable RF/ AFE AD/DA
++ rtStatus = _DisableRF_AFE(Adapter);
++ if(RT_STATUS_SUCCESS != rtStatus){
++ RT_TRACE(COMP_INIT, DBG_SERIOUS, ("_DisableRF_AFE failed!\n"));
++ goto Exit;
++ }
++ _ResetBB(Adapter);
++
++ if(resetMCU){
++ _ResetMCU(Adapter);
++ }
++
++ _AutoPowerDownToHostOff(Adapter);
++ //_DisableMAC_AFE_PLL(Adapter);
++
++ _SetUsbSuspend(Adapter);
++Exit:
++#endif
++ return rtStatus;
++
++}
++
++static int
++CardDisableWithoutHWSM( // without HW Auto state machine
++ IN PADAPTER Adapter
++ )
++{
++ int rtStatus = _SUCCESS;
++
++ if(Adapter->bSurpriseRemoved){
++ return rtStatus;
++ }
++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("======> Card Disable Without HWSM .\n"));
++ //==== RF Off Sequence ====
++ _DisableRFAFEAndResetBB(Adapter);
++
++ // ==== Reset digital sequence ======
++ _ResetDigitalProcedure1(Adapter, _TRUE);
++
++ // ==== Pull GPIO PIN to balance level and LED control ======
++ _DisableGPIO(Adapter);
++
++ // ==== Reset digital sequence ======
++ _ResetDigitalProcedure2(Adapter);
++
++ // ==== Disable analog sequence ===
++ _DisableAnalog(Adapter, _TRUE);
++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("<====== Card Disable Without HWSM .\n"));
++ return rtStatus;
++}
++
++static void rtl8192cu_hw_power_down(_adapter *padapter)
++{
++ // 2010/-8/09 MH For power down module, we need to enable register block contrl reg at 0x1c.
++ // Then enable power down control bit of register 0x04 BIT4 and BIT15 as 1.
++
++ // Enable register area 0x0-0xc.
++ rtw_write8(padapter,REG_RSV_CTRL, 0x0);
++ rtw_write16(padapter, REG_APS_FSMCO, 0x8812);
++}
++
++u32 rtl8192cu_hal_deinit(PADAPTER Adapter)
++ {
++
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ DBG_8192C("==> %s \n",__FUNCTION__);
++ // 2011/02/18 To Fix RU LNA power leakage problem. We need to execute below below in
++ // Adapter init and halt sequence. Accordingto EEchou's opinion, we can enable the ability for all
++ // IC. Accord to johnny's opinion, only RU need the support.
++ if (IS_HARDWARE_TYPE_8192C(Adapter) && (pHalData->BoardType == BOARD_USB_High_PA))
++ rtw_write32(Adapter, rFPGA0_XCD_RFParameter, rtw_read32(Adapter, rFPGA0_XCD_RFParameter)|BIT1);
++
++ #ifdef SUPPORT_HW_RFOFF_DETECTED
++ DBG_8192C("bkeepfwalive(%x)\n",Adapter->pwrctrlpriv.bkeepfwalive);
++ if(Adapter->pwrctrlpriv.bkeepfwalive)
++ {
++ _ps_close_RF(Adapter);
++ if((Adapter->pwrctrlpriv.bHWPwrPindetect) && (Adapter->pwrctrlpriv.bHWPowerdown))
++ rtl8192cu_hw_power_down(Adapter);
++ }
++ else
++#endif
++ {
++ if( Adapter->bCardDisableWOHSM == _FALSE)
++ {
++ DBG_8192C("card disble HWSM...........\n");
++ CardDisableHWSM(Adapter, _FALSE);
++ }
++ else
++ {
++ DBG_8192C("card disble without HWSM...........\n");
++ CardDisableWithoutHWSM(Adapter); // without HW Auto state machine
++
++ if((Adapter->pwrctrlpriv.bHWPwrPindetect ) && (Adapter->pwrctrlpriv.bHWPowerdown))
++ rtl8192cu_hw_power_down(Adapter);
++ }
++ }
++
++ return _SUCCESS;
++ }
++
++
++unsigned int rtl8192cu_inirp_init(PADAPTER Adapter)
++{
++ u8 i;
++ struct recv_buf *precvbuf;
++ uint status;
++ struct dvobj_priv *pdev = adapter_to_dvobj(Adapter);
++ struct intf_hdl * pintfhdl=&Adapter->iopriv.intf;
++ struct recv_priv *precvpriv = &(Adapter->recvpriv);
++ u32 (*_read_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
++#ifdef CONFIG_USB_INTERRUPT_IN_PIPE
++ u32 (*_read_interrupt)(struct intf_hdl *pintfhdl, u32 addr);
++#endif
++
++_func_enter_;
++
++ _read_port = pintfhdl->io_ops._read_port;
++
++ status = _SUCCESS;
++
++ RT_TRACE(_module_hci_hal_init_c_,_drv_info_,("===> usb_inirp_init \n"));
++
++ precvpriv->ff_hwaddr = RECV_BULK_IN_ADDR;
++
++ //issue Rx irp to receive data
++ precvbuf = (struct recv_buf *)precvpriv->precv_buf;
++ for(i=0; i<NR_RECVBUFF; i++)
++ {
++ if(_read_port(pintfhdl, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf) == _FALSE )
++ {
++ RT_TRACE(_module_hci_hal_init_c_,_drv_err_,("usb_rx_init: usb_read_port error \n"));
++ status = _FAIL;
++ goto exit;
++ }
++
++ precvbuf++;
++ precvpriv->free_recv_buf_queue_cnt--;
++ }
++
++#ifdef CONFIG_USB_INTERRUPT_IN_PIPE
++ _read_interrupt = pintfhdl->io_ops._read_interrupt;
++ if(_read_interrupt(pintfhdl, RECV_INT_IN_ADDR) == _FALSE )
++ {
++ RT_TRACE(_module_hci_hal_init_c_,_drv_err_,("usb_rx_init: usb_read_interrupt error \n"));
++ status = _FAIL;
++ }
++#endif
++
++exit:
++
++ RT_TRACE(_module_hci_hal_init_c_,_drv_info_,("<=== usb_inirp_init \n"));
++
++_func_exit_;
++
++ return status;
++
++}
++
++unsigned int rtl8192cu_inirp_deinit(PADAPTER Adapter)
++{
++ RT_TRACE(_module_hci_hal_init_c_,_drv_info_,("\n ===> usb_rx_deinit \n"));
++
++ rtw_read_port_cancel(Adapter);
++
++ RT_TRACE(_module_hci_hal_init_c_,_drv_info_,("\n <=== usb_rx_deinit \n"));
++
++ return _SUCCESS;
++}
++
++
++//-------------------------------------------------------------------------
++//
++// EEPROM Power index mapping
++//
++//-------------------------------------------------------------------------
++
++ static VOID
++_ReadPowerValueFromPROM(
++ IN PTxPowerInfo pwrInfo,
++ IN u8* PROMContent,
++ IN BOOLEAN AutoLoadFail
++ )
++{
++ u32 rfPath, eeAddr, group;
++
++ _rtw_memset(pwrInfo, 0, sizeof(TxPowerInfo));
++
++ if(AutoLoadFail){
++ for(group = 0 ; group < CHANNEL_GROUP_MAX ; group++){
++ for(rfPath = 0 ; rfPath < RF_PATH_MAX ; rfPath++){
++ pwrInfo->CCKIndex[rfPath][group] = EEPROM_Default_TxPowerLevel;
++ pwrInfo->HT40_1SIndex[rfPath][group] = EEPROM_Default_TxPowerLevel;
++ pwrInfo->HT40_2SIndexDiff[rfPath][group]= EEPROM_Default_HT40_2SDiff;
++ pwrInfo->HT20IndexDiff[rfPath][group] = EEPROM_Default_HT20_Diff;
++ pwrInfo->OFDMIndexDiff[rfPath][group] = EEPROM_Default_LegacyHTTxPowerDiff;
++ pwrInfo->HT40MaxOffset[rfPath][group] = EEPROM_Default_HT40_PwrMaxOffset;
++ pwrInfo->HT20MaxOffset[rfPath][group] = EEPROM_Default_HT20_PwrMaxOffset;
++ }
++ }
++
++ pwrInfo->TSSI_A = EEPROM_Default_TSSI;
++ pwrInfo->TSSI_B = EEPROM_Default_TSSI;
++
++ return;
++ }
++
++ for(rfPath = 0 ; rfPath < RF_PATH_MAX ; rfPath++){
++ for(group = 0 ; group < CHANNEL_GROUP_MAX ; group++){
++ eeAddr = EEPROM_CCK_TX_PWR_INX + (rfPath * 3) + group;
++ pwrInfo->CCKIndex[rfPath][group] = PROMContent[eeAddr];
++
++ eeAddr = EEPROM_HT40_1S_TX_PWR_INX + (rfPath * 3) + group;
++ pwrInfo->HT40_1SIndex[rfPath][group] = PROMContent[eeAddr];
++ }
++ }
++
++ for(group = 0 ; group < CHANNEL_GROUP_MAX ; group++){
++ for(rfPath = 0 ; rfPath < RF_PATH_MAX ; rfPath++){
++ pwrInfo->HT40_2SIndexDiff[rfPath][group] =
++ (PROMContent[EEPROM_HT40_2S_TX_PWR_INX_DIFF + group] >> (rfPath * 4)) & 0xF;
++
++#if 1
++ pwrInfo->HT20IndexDiff[rfPath][group] =
++ (PROMContent[EEPROM_HT20_TX_PWR_INX_DIFF + group] >> (rfPath * 4)) & 0xF;
++ if(pwrInfo->HT20IndexDiff[rfPath][group] & BIT3) //4bit sign number to 8 bit sign number
++ pwrInfo->HT20IndexDiff[rfPath][group] |= 0xF0;
++#else
++ pwrInfo->HT20IndexDiff[rfPath][group] =
++ (PROMContent[EEPROM_HT20_TX_PWR_INX_DIFF + group] >> (rfPath * 4)) & 0xF;
++#endif
++
++ pwrInfo->OFDMIndexDiff[rfPath][group] =
++ (PROMContent[EEPROM_OFDM_TX_PWR_INX_DIFF+ group] >> (rfPath * 4)) & 0xF;
++
++ pwrInfo->HT40MaxOffset[rfPath][group] =
++ (PROMContent[EEPROM_HT40_MAX_PWR_OFFSET+ group] >> (rfPath * 4)) & 0xF;
++
++ pwrInfo->HT20MaxOffset[rfPath][group] =
++ (PROMContent[EEPROM_HT20_MAX_PWR_OFFSET+ group] >> (rfPath * 4)) & 0xF;
++ }
++ }
++
++ pwrInfo->TSSI_A = PROMContent[EEPROM_TSSI_A];
++ pwrInfo->TSSI_B = PROMContent[EEPROM_TSSI_B];
++
++}
++
++
++static u32
++_GetChannelGroup(
++ IN u32 channel
++ )
++{
++ //RT_ASSERT((channel < 14), ("Channel %d no is supported!\n"));
++
++ if(channel < 3){ // Channel 1~3
++ return 0;
++ }
++ else if(channel < 9){ // Channel 4~9
++ return 1;
++ }
++
++ return 2; // Channel 10~14
++}
++
++
++static VOID
++ReadTxPowerInfo(
++ IN PADAPTER Adapter,
++ IN u8* PROMContent,
++ IN BOOLEAN AutoLoadFail
++ )
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ TxPowerInfo pwrInfo;
++ u32 rfPath, ch, group;
++ u8 pwr, diff;
++
++ _ReadPowerValueFromPROM(&pwrInfo, PROMContent, AutoLoadFail);
++
++ if(!AutoLoadFail)
++ pHalData->bTXPowerDataReadFromEEPORM = _TRUE;
++
++ for(rfPath = 0 ; rfPath < RF_PATH_MAX ; rfPath++){
++ for(ch = 0 ; ch < CHANNEL_MAX_NUMBER ; ch++){
++ group = _GetChannelGroup(ch);
++
++ pHalData->TxPwrLevelCck[rfPath][ch] = pwrInfo.CCKIndex[rfPath][group];
++ pHalData->TxPwrLevelHT40_1S[rfPath][ch] = pwrInfo.HT40_1SIndex[rfPath][group];
++
++ pHalData->TxPwrHt20Diff[rfPath][ch] = pwrInfo.HT20IndexDiff[rfPath][group];
++ pHalData->TxPwrLegacyHtDiff[rfPath][ch] = pwrInfo.OFDMIndexDiff[rfPath][group];
++ pHalData->PwrGroupHT20[rfPath][ch] = pwrInfo.HT20MaxOffset[rfPath][group];
++ pHalData->PwrGroupHT40[rfPath][ch] = pwrInfo.HT40MaxOffset[rfPath][group];
++
++ pwr = pwrInfo.HT40_1SIndex[rfPath][group];
++ diff = pwrInfo.HT40_2SIndexDiff[rfPath][group];
++
++ pHalData->TxPwrLevelHT40_2S[rfPath][ch] = (pwr > diff) ? (pwr - diff) : 0;
++ }
++ }
++
++#if DBG
++
++ for(rfPath = 0 ; rfPath < RF_PATH_MAX ; rfPath++){
++ for(ch = 0 ; ch < CHANNEL_MAX_NUMBER ; ch++){
++ RTPRINT(FINIT, INIT_TxPower,
++ ("RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n",
++ rfPath, ch, pHalData->TxPwrLevelCck[rfPath][ch],
++ pHalData->TxPwrLevelHT40_1S[rfPath][ch],
++ pHalData->TxPwrLevelHT40_2S[rfPath][ch]));
++
++ }
++ }
++
++ for(ch = 0 ; ch < CHANNEL_MAX_NUMBER ; ch++){
++ RTPRINT(FINIT, INIT_TxPower, ("RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", ch, pHalData->TxPwrHt20Diff[RF_PATH_A][ch]));
++ }
++
++ for(ch = 0 ; ch < CHANNEL_MAX_NUMBER ; ch++){
++ RTPRINT(FINIT, INIT_TxPower, ("RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", ch, pHalData->TxPwrLegacyHtDiff[RF_PATH_A][ch]));
++ }
++
++ for(ch = 0 ; ch < CHANNEL_MAX_NUMBER ; ch++){
++ RTPRINT(FINIT, INIT_TxPower, ("RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", ch, pHalData->TxPwrHt20Diff[RF_PATH_B][ch]));
++ }
++
++ for(ch = 0 ; ch < CHANNEL_MAX_NUMBER ; ch++){
++ RTPRINT(FINIT, INIT_TxPower, ("RF-B Legacy to HT40 Diff[%d] = 0x%x\n", ch, pHalData->TxPwrLegacyHtDiff[RF_PATH_B][ch]));
++ }
++
++#endif
++ // 2010/10/19 MH Add Regulator recognize for CU.
++ if(!AutoLoadFail)
++ {
++ pHalData->EEPROMRegulatory = (PROMContent[RF_OPTION1]&0x7); //bit0~2
++ }
++ else
++ {
++ pHalData->EEPROMRegulatory = 0;
++ }
++ DBG_8192C("EEPROMRegulatory = 0x%x\n", pHalData->EEPROMRegulatory);
++
++}
++
++
++//-------------------------------------------------------------------
++//
++// EEPROM/EFUSE Content Parsing
++//
++//-------------------------------------------------------------------
++static void
++_ReadIDs(
++ IN PADAPTER Adapter,
++ IN u8* PROMContent,
++ IN BOOLEAN AutoloadFail
++ )
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++
++ if(_FALSE == AutoloadFail){
++ // VID, PID
++ pHalData->EEPROMVID = le16_to_cpu( *(u16 *)&PROMContent[EEPROM_VID]);
++ pHalData->EEPROMPID = le16_to_cpu( *(u16 *)&PROMContent[EEPROM_PID]);
++
++ // Customer ID, 0x00 and 0xff are reserved for Realtek.
++ pHalData->EEPROMCustomerID = *(u8 *)&PROMContent[EEPROM_CUSTOMER_ID];
++ pHalData->EEPROMSubCustomerID = *(u8 *)&PROMContent[EEPROM_SUBCUSTOMER_ID];
++
++ }
++ else{
++ pHalData->EEPROMVID = EEPROM_Default_VID;
++ pHalData->EEPROMPID = EEPROM_Default_PID;
++
++ // Customer ID, 0x00 and 0xff are reserved for Realtek.
++ pHalData->EEPROMCustomerID = EEPROM_Default_CustomerID;
++ pHalData->EEPROMSubCustomerID = EEPROM_Default_SubCustomerID;
++
++ }
++
++ // For customized behavior.
++ if((pHalData->EEPROMVID == 0x103C) && (pHalData->EEPROMVID == 0x1629))// HP Lite-On for RTL8188CUS Slim Combo.
++ pHalData->CustomerID = RT_CID_819x_HP;
++
++ // Decide CustomerID according to VID/DID or EEPROM
++ switch(pHalData->EEPROMCustomerID)
++ {
++ case EEPROM_CID_DEFAULT:
++ if((pHalData->EEPROMVID == 0x2001) && (pHalData->EEPROMPID == 0x3308))
++ pHalData->CustomerID = RT_CID_DLINK;
++ else if((pHalData->EEPROMVID == 0x2001) && (pHalData->EEPROMPID == 0x3309))
++ pHalData->CustomerID = RT_CID_DLINK;
++ else if((pHalData->EEPROMVID == 0x2001) && (pHalData->EEPROMPID == 0x330a))
++ pHalData->CustomerID = RT_CID_DLINK;
++ break;
++ case EEPROM_CID_WHQL:
++/*
++ Adapter->bInHctTest = TRUE;
++
++ pMgntInfo->bSupportTurboMode = FALSE;
++ pMgntInfo->bAutoTurboBy8186 = FALSE;
++
++ pMgntInfo->PowerSaveControl.bInactivePs = FALSE;
++ pMgntInfo->PowerSaveControl.bIPSModeBackup = FALSE;
++ pMgntInfo->PowerSaveControl.bLeisurePs = FALSE;
++
++ pMgntInfo->keepAliveLevel = 0;
++
++ Adapter->bUnloadDriverwhenS3S4 = FALSE;
++*/
++ break;
++ default:
++ pHalData->CustomerID = RT_CID_DEFAULT;
++ break;
++
++ }
++
++ MSG_8192C("EEPROMVID = 0x%04x\n", pHalData->EEPROMVID);
++ MSG_8192C("EEPROMPID = 0x%04x\n", pHalData->EEPROMPID);
++ MSG_8192C("EEPROMCustomerID : 0x%02x\n", pHalData->EEPROMCustomerID);
++ MSG_8192C("EEPROMSubCustomerID: 0x%02x\n", pHalData->EEPROMSubCustomerID);
++
++ MSG_8192C("RT_CustomerID: 0x%02x\n", pHalData->CustomerID);
++
++}
++
++
++static VOID
++_ReadMACAddress(
++ IN PADAPTER Adapter,
++ IN u8* PROMContent,
++ IN BOOLEAN AutoloadFail
++ )
++{
++ EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(Adapter);
++
++ if(_FALSE == AutoloadFail){
++ //Read Permanent MAC address and set value to hardware
++ _rtw_memcpy(pEEPROM->mac_addr, &PROMContent[EEPROM_MAC_ADDR], ETH_ALEN);
++ }
++ else{
++ //Random assigh MAC address
++ u8 sMacAddr[MAC_ADDR_LEN] = {0x00, 0xE0, 0x4C, 0x81, 0x92, 0x00};
++ //sMacAddr[5] = (u8)GetRandomNumber(1, 254);
++ _rtw_memcpy(pEEPROM->mac_addr, sMacAddr, ETH_ALEN);
++ }
++ DBG_8192C("%s MAC Address from EFUSE = "MAC_FMT"\n",__FUNCTION__, MAC_ARG(pEEPROM->mac_addr));
++ //NicIFSetMacAddress(Adapter, Adapter->PermanentAddress);
++ //RT_PRINT_ADDR(COMP_INIT|COMP_EFUSE, DBG_LOUD, "MAC Addr: %s", Adapter->PermanentAddress);
++
++}
++
++static VOID
++_ReadBoardType(
++ IN PADAPTER Adapter,
++ IN u8* PROMContent,
++ IN BOOLEAN AutoloadFail
++ )
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ u32 value32;
++ u8 boardType = BOARD_USB_DONGLE;
++
++ if(AutoloadFail){
++ if(IS_8723_SERIES(pHalData->VersionID))
++ pHalData->rf_type = RF_1T1R;
++ else
++ pHalData->rf_type = RF_2T2R;
++
++ pHalData->BluetoothCoexist = _FALSE;
++ pHalData->BoardType = boardType;
++ return;
++ }
++
++ boardType = PROMContent[EEPROM_NORMAL_BoardType];
++ boardType &= BOARD_TYPE_NORMAL_MASK;//bit[7:5]
++ boardType >>= 5;
++
++ pHalData->BoardType = boardType;
++ MSG_8192C("_ReadBoardType(%x)\n",pHalData->BoardType);
++
++ if (boardType == BOARD_USB_High_PA)
++ pHalData->ExternalPA = 1;
++}
++
++
++static VOID
++_ReadLEDSetting(
++ IN PADAPTER Adapter,
++ IN u8* PROMContent,
++ IN BOOLEAN AutoloadFail
++ )
++{
++ struct led_priv *pledpriv = &(Adapter->ledpriv);
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++#ifdef CONFIG_SW_LED
++ pledpriv->bRegUseLed = _TRUE;
++
++ //
++ // Led mode
++ //
++ switch(pHalData->CustomerID)
++ {
++ case RT_CID_DEFAULT:
++ pledpriv->LedStrategy = SW_LED_MODE1;
++ pledpriv->bRegUseLed = _TRUE;
++ break;
++
++ case RT_CID_819x_HP:
++ pledpriv->LedStrategy = SW_LED_MODE6;
++ break;
++
++ default:
++ pledpriv->LedStrategy = SW_LED_MODE1;
++ break;
++ }
++
++ if( BOARD_MINICARD == pHalData->BoardType )
++ {
++ pledpriv->LedStrategy = SW_LED_MODE6;
++ }
++ pHalData->bLedOpenDrain = _TRUE;// Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16.
++#else // HW LED
++ pledpriv->LedStrategy = HW_LED;
++#endif //CONFIG_SW_LED
++}
++
++static VOID
++_ReadThermalMeter(
++ IN PADAPTER Adapter,
++ IN u8* PROMContent,
++ IN BOOLEAN AutoloadFail
++ )
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ struct dm_priv *pdmpriv = &pHalData->dmpriv;
++ u8 tempval;
++
++ //
++ // ThermalMeter from EEPROM
++ //
++ if(!AutoloadFail)
++ tempval = PROMContent[EEPROM_THERMAL_METER];
++ else
++ tempval = EEPROM_Default_ThermalMeter;
++
++ pHalData->EEPROMThermalMeter = (tempval&0x1f); //[4:0]
++
++ if(pHalData->EEPROMThermalMeter == 0x1f || AutoloadFail)
++ pdmpriv->bAPKThermalMeterIgnore = _TRUE;
++
++#if 0
++ if(pHalData->EEPROMThermalMeter < 0x06 || pHalData->EEPROMThermalMeter > 0x1c)
++ pHalData->EEPROMThermalMeter = 0x12;
++#endif
++
++ pdmpriv->ThermalMeter[0] = pHalData->EEPROMThermalMeter;
++
++ //RTPRINT(FINIT, INIT_TxPower, ("ThermalMeter = 0x%x\n", pHalData->EEPROMThermalMeter));
++
++}
++
++static VOID
++_ReadRFSetting(
++ IN PADAPTER Adapter,
++ IN u8* PROMContent,
++ IN BOOLEAN AutoloadFail
++ )
++{
++}
++
++static void
++_ReadPROMVersion(
++ IN PADAPTER Adapter,
++ IN u8* PROMContent,
++ IN BOOLEAN AutoloadFail
++ )
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++
++ if(AutoloadFail){
++ pHalData->EEPROMVersion = EEPROM_Default_Version;
++ }
++ else{
++ pHalData->EEPROMVersion = *(u8 *)&PROMContent[EEPROM_VERSION];
++ }
++}
++
++static VOID
++readAntennaDiversity(
++ IN PADAPTER pAdapter,
++ IN u8 *hwinfo,
++ IN BOOLEAN AutoLoadFail
++ )
++{
++
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
++ struct registry_priv *registry_par = &pAdapter->registrypriv;
++
++ if(!AutoLoadFail)
++ {
++ // Antenna Diversity setting.
++ if(registry_par->antdiv_cfg == 2) // 2: From Efuse
++ pHalData->AntDivCfg = (hwinfo[EEPROM_RF_OPT1]&0x18)>>3;
++ else
++ pHalData->AntDivCfg = registry_par->antdiv_cfg ; // 0:OFF , 1:ON,
++
++ DBG_8192C("### AntDivCfg(%x)\n",pHalData->AntDivCfg);
++
++ //if(pHalData->EEPROMBluetoothCoexist!=0 && pHalData->EEPROMBluetoothAntNum==Ant_x1)
++ // pHalData->AntDivCfg = 0;
++ }
++ else
++ {
++ pHalData->AntDivCfg = 0;
++ }
++
++}
++
++static VOID
++hal_InitPGData(
++ IN PADAPTER pAdapter,
++ IN OUT u8 *PROMContent
++ )
++{
++ EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(pAdapter);
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
++ u32 i;
++ u16 value16;
++
++ if(_FALSE == pEEPROM->bautoload_fail_flag)
++ { // autoload OK.
++ if (_TRUE == pEEPROM->EepromOrEfuse)
++ {
++ // Read all Content from EEPROM or EFUSE.
++ for(i = 0; i < HWSET_MAX_SIZE; i += 2)
++ {
++ //value16 = EF2Byte(ReadEEprom(pAdapter, (u2Byte) (i>>1)));
++ //*((u16 *)(&PROMContent[i])) = value16;
++ }
++ }
++ else
++ {
++ // Read EFUSE real map to shadow.
++ EFUSE_ShadowMapUpdate(pAdapter, EFUSE_WIFI, _FALSE);
++ _rtw_memcpy((void*)PROMContent, (void*)pEEPROM->efuse_eeprom_data, HWSET_MAX_SIZE);
++ }
++ }
++ else
++ {//autoload fail
++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("AutoLoad Fail reported from CR9346!!\n"));
++ pEEPROM->bautoload_fail_flag = _TRUE;
++ //update to default value 0xFF
++ if (_FALSE == pEEPROM->EepromOrEfuse)
++ EFUSE_ShadowMapUpdate(pAdapter, EFUSE_WIFI, _FALSE);
++ }
++}
++// Read HW power down mode selection
++static void _ReadPSSetting(IN PADAPTER Adapter,IN u8*PROMContent,IN u8 AutoloadFail)
++{
++ if(AutoloadFail){
++ Adapter->pwrctrlpriv.bHWPowerdown = _FALSE;
++ Adapter->pwrctrlpriv.bSupportRemoteWakeup = _FALSE;
++ }
++ else {
++ //if(SUPPORT_HW_RADIO_DETECT(Adapter))
++ Adapter->pwrctrlpriv.bHWPwrPindetect = Adapter->registrypriv.hwpwrp_detect;
++ //else
++ //Adapter->pwrctrlpriv.bHWPwrPindetect = _FALSE;//dongle not support new
++
++
++ //hw power down mode selection , 0:rf-off / 1:power down
++
++ if(Adapter->registrypriv.hwpdn_mode==2)
++ Adapter->pwrctrlpriv.bHWPowerdown = (PROMContent[EEPROM_RF_OPT3] & BIT4);
++ else
++ Adapter->pwrctrlpriv.bHWPowerdown = Adapter->registrypriv.hwpdn_mode;
++#ifdef CONFIG_WOWLAN
++ // decide hw if support remote wakeup function
++ // if hw supported, 8051 (SIE) will generate WeakUP signal( D+/D- toggle) when autoresume
++ Adapter->pwrctrlpriv.bSupportRemoteWakeup = (PROMContent[EEPROM_TEST_USB_OPT] & BIT1)?_TRUE :_FALSE;
++#endif //CONFIG_WOWLAN
++
++ //if(SUPPORT_HW_RADIO_DETECT(Adapter))
++ //Adapter->registrypriv.usbss_enable = Adapter->pwrctrlpriv.bSupportRemoteWakeup ;
++
++ DBG_8192C("%s...bHWPwrPindetect(%x)-bHWPowerdown(%x) ,bSupportRemoteWakeup(%x)\n",__FUNCTION__,
++ Adapter->pwrctrlpriv.bHWPwrPindetect,Adapter->pwrctrlpriv.bHWPowerdown ,Adapter->pwrctrlpriv.bSupportRemoteWakeup);
++
++ DBG_8192C("### PS params=> power_mgnt(%x),usbss_enable(%x) ###\n",Adapter->registrypriv.power_mgnt,Adapter->registrypriv.usbss_enable);
++
++ }
++
++}
++
++static VOID
++readAdapterInfo_8192CU(
++ IN PADAPTER Adapter
++ )
++{
++ EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(Adapter);
++ PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
++ u8 PROMContent[HWSET_MAX_SIZE]={0};
++
++ hal_InitPGData(Adapter, PROMContent);
++ rtl8192c_EfuseParseIDCode(Adapter, PROMContent);
++
++ _ReadPROMVersion(Adapter, PROMContent, pEEPROM->bautoload_fail_flag);
++ _ReadIDs(Adapter, PROMContent, pEEPROM->bautoload_fail_flag);
++ _ReadMACAddress(Adapter, PROMContent, pEEPROM->bautoload_fail_flag);
++ ReadTxPowerInfo(Adapter, PROMContent, pEEPROM->bautoload_fail_flag);
++ _ReadBoardType(Adapter, PROMContent, pEEPROM->bautoload_fail_flag);
++
++#ifdef CONFIG_BT_COEXIST
++ //
++ // Read Bluetooth co-exist and initialize
++ //
++ rtl8192c_ReadBluetoothCoexistInfo(Adapter, PROMContent, pEEPROM->bautoload_fail_flag);
++#endif
++
++ rtl8192c_EfuseParseChnlPlan(Adapter, PROMContent, pEEPROM->bautoload_fail_flag);
++ _ReadThermalMeter(Adapter, PROMContent, pEEPROM->bautoload_fail_flag);
++ _ReadLEDSetting(Adapter, PROMContent, pEEPROM->bautoload_fail_flag);
++ _ReadRFSetting(Adapter, PROMContent, pEEPROM->bautoload_fail_flag);
++ _ReadPSSetting(Adapter, PROMContent, pEEPROM->bautoload_fail_flag);
++ readAntennaDiversity(Adapter, PROMContent, pEEPROM->bautoload_fail_flag);
++
++ //hal_CustomizedBehavior_8723U(Adapter);
++
++ Adapter->bDongle = (PROMContent[EEPROM_EASY_REPLACEMENT] == 1)? 0: 1;
++ DBG_8192C("%s(): REPLACEMENT = %x\n",__FUNCTION__,Adapter->bDongle);
++#ifdef CONFIG_INTEL_PROXIM
++ /* for intel proximity */
++ if (pHalData->rf_type== RF_1T1R) {
++ Adapter->proximity.proxim_support = _TRUE;
++ } else if (pHalData->rf_type== RF_2T2R) {
++ if ((pHalData->EEPROMPID == 0x8186) &&
++ (pHalData->EEPROMVID== 0x0bda))
++ Adapter->proximity.proxim_support = _TRUE;
++ } else {
++ Adapter->proximity.proxim_support = _FALSE;
++ }
++#endif //CONFIG_INTEL_PROXIM
++}
++
++static void _ReadPROMContent(
++ IN PADAPTER Adapter
++ )
++{
++ EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(Adapter);
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ u8 PROMContent[HWSET_MAX_SIZE]={0};
++ u8 eeValue;
++ u32 i;
++ u16 value16;
++
++ eeValue = rtw_read8(Adapter, REG_9346CR);
++ // To check system boot selection.
++ pEEPROM->EepromOrEfuse = (eeValue & BOOT_FROM_EEPROM) ? _TRUE : _FALSE;
++ pEEPROM->bautoload_fail_flag = (eeValue & EEPROM_EN) ? _FALSE : _TRUE;
++
++
++ DBG_8192C("Boot from %s, Autoload %s !\n", (pEEPROM->EepromOrEfuse ? "EEPROM" : "EFUSE"),
++ (pEEPROM->bautoload_fail_flag ? "Fail" : "OK") );
++
++ //pHalData->EEType = IS_BOOT_FROM_EEPROM(Adapter) ? EEPROM_93C46 : EEPROM_BOOT_EFUSE;
++
++ //if(IS_HARDWARE_TYPE_8723A(Adapter))
++ // readAdapterInfo_8723U(Adapter);
++ //else
++ readAdapterInfo_8192CU(Adapter);
++}
++
++
++static VOID
++_InitOtherVariable(
++ IN PADAPTER Adapter
++ )
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++
++
++ //if(Adapter->bInHctTest){
++ // pMgntInfo->PowerSaveControl.bInactivePs = FALSE;
++ // pMgntInfo->PowerSaveControl.bIPSModeBackup = FALSE;
++ // pMgntInfo->PowerSaveControl.bLeisurePs = FALSE;
++ // pMgntInfo->keepAliveLevel = 0;
++ //}
++
++ // 2009/06/10 MH For 92S 1*1=1R/ 1*2&2*2 use 2R. We default set 1*1 use radio A
++ // So if you want to use radio B. Please modify RF path enable bit for correct signal
++ // strength calculate.
++ if (pHalData->rf_type == RF_1T1R){
++ pHalData->bRFPathRxEnable[0] = _TRUE;
++ }
++ else{
++ pHalData->bRFPathRxEnable[0] = pHalData->bRFPathRxEnable[1] = _TRUE;
++ }
++
++}
++
++static VOID
++_ReadRFType(
++ IN PADAPTER Adapter
++ )
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++
++#if DISABLE_BB_RF
++ pHalData->rf_chip = RF_PSEUDO_11N;
++#else
++ pHalData->rf_chip = RF_6052;
++#endif
++}
++
++void _ReadSilmComboMode(PADAPTER Adapter)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++
++ pHalData->SlimComboDbg = _FALSE; // Default is not debug mode.
++
++ // 2010/11/22 MH We need to enter debug mode for TSMA and UMC A cut
++ if ((Adapter->chip_type == RTL8188C_8192C) &&
++ (pHalData->BoardType == BOARD_USB_COMBO))
++ {
++ switch (pHalData->VersionID)
++ {
++ case VERSION_NORMAL_TSMC_CHIP_88C:
++ case VERSION_NORMAL_TSMC_CHIP_92C:
++ case VERSION_NORMAL_TSMC_CHIP_92C_1T2R:
++ case VERSION_NORMAL_UMC_CHIP_88C_A_CUT:
++ case VERSION_NORMAL_UMC_CHIP_92C_A_CUT:
++ case VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT:
++ if ((rtw_read8(Adapter, REG_SYS_CFG+3) &0xF0) == 0x20)
++ pHalData->SlimComboDbg = _TRUE;
++
++ break;
++
++ case VERSION_NORMAL_UMC_CHIP_88C_B_CUT:
++ case VERSION_NORMAL_UMC_CHIP_92C_B_CUT:
++ case VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT:
++ // 2011/02/15 MH UNC-B cut ECO fail, we need to support slim combo debug mode.
++ if ((rtw_read8(Adapter, REG_SYS_CFG+3) &0xF0) == 0x20)
++ pHalData->SlimComboDbg = _TRUE;
++ break;
++
++ default:
++ break;
++ }
++
++ }
++
++}
++static int _ReadAdapterInfo8192CU(PADAPTER Adapter)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ u32 start=rtw_get_current_time();
++
++ MSG_8192C("====> ReadAdapterInfo8192C\n");
++
++ //Efuse_InitSomeVar(Adapter);
++
++ //if(IS_HARDWARE_TYPE_8723A(Adapter))
++ // _EfuseCellSel(Adapter);
++
++ _ReadRFType(Adapter);//rf_chip -> _InitRFType()
++ _ReadPROMContent(Adapter);
++
++ // 2010/10/25 MH THe function must be called after borad_type & IC-Version recognize.
++ _ReadSilmComboMode(Adapter);
++
++ _InitOtherVariable(Adapter);
++
++ //MSG_8192C("%s()(done), rf_chip=0x%x, rf_type=0x%x\n", __FUNCTION__, pHalData->rf_chip, pHalData->rf_type);
++
++ MSG_8192C("<==== ReadAdapterInfo8192C in %d ms\n", rtw_get_passing_time_ms(start));
++
++ return _SUCCESS;
++}
++
++
++static void ReadAdapterInfo8192CU(PADAPTER Adapter)
++{
++ // Read EEPROM size before call any EEPROM function
++ //Adapter->EepromAddressSize=Adapter->HalFunc.GetEEPROMSizeHandler(Adapter);
++ Adapter->EepromAddressSize = GetEEPROMSize8192C(Adapter);
++
++ _ReadAdapterInfo8192CU(Adapter);
++}
++
++
++#define GPIO_DEBUG_PORT_NUM 0
++static void rtl8192cu_trigger_gpio_0(_adapter *padapter)
++{
++
++ u32 gpioctrl;
++ DBG_8192C("==> trigger_gpio_0...\n");
++ rtw_write16_async(padapter,REG_GPIO_PIN_CTRL,0);
++ rtw_write8_async(padapter,REG_GPIO_PIN_CTRL+2,0xFF);
++ gpioctrl = (BIT(GPIO_DEBUG_PORT_NUM)<<24 )|(BIT(GPIO_DEBUG_PORT_NUM)<<16);
++ rtw_write32_async(padapter,REG_GPIO_PIN_CTRL,gpioctrl);
++ gpioctrl |= (BIT(GPIO_DEBUG_PORT_NUM)<<8);
++ rtw_write32_async(padapter,REG_GPIO_PIN_CTRL,gpioctrl);
++ DBG_8192C("<=== trigger_gpio_0...\n");
++
++}
++
++static void ResumeTxBeacon(_adapter *padapter)
++{
++ HAL_DATA_TYPE* pHalData = GET_HAL_DATA(padapter);
++
++ // 2010.03.01. Marked by tynli. No need to call workitem beacause we record the value
++ // which should be read from register to a global variable.
++
++ rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, (pHalData->RegFwHwTxQCtrl) | BIT6);
++ pHalData->RegFwHwTxQCtrl |= BIT6;
++}
++
++static void StopTxBeacon(_adapter *padapter)
++{
++ HAL_DATA_TYPE* pHalData = GET_HAL_DATA(padapter);
++
++ // 2010.03.01. Marked by tynli. No need to call workitem beacause we record the value
++ // which should be read from register to a global variable.
++
++ rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, (pHalData->RegFwHwTxQCtrl) & (~BIT6));
++ pHalData->RegFwHwTxQCtrl &= (~BIT6);
++
++ //todo: CheckFwRsvdPageContent(Adapter); // 2010.06.23. Added by tynli.
++
++}
++
++u16 CRC16(u8 data,u16 CRC)
++{
++ unsigned char shift_in,CRC_BIT15,DataBit,CRC_BIT11,CRC_BIT4 ;
++ int index;
++ unsigned short CRC_Result;
++
++ for(index=0;index<8;index++)
++ {
++ CRC_BIT15=((CRC&BIT15) ? 1:0);
++ DataBit =(data&(BIT0<<index) ? 1:0);
++ shift_in=CRC_BIT15^DataBit;
++ //printf("CRC_BIT15=%d, DataBit=%d, shift_in=%d \n",CRC_BIT15,DataBit,shift_in);
++
++ CRC_Result=CRC<<1;
++ //set BIT0
++ // printf("CRC =%x\n",CRC_Result);
++ //CRC bit 0 =shift_in,
++ if(shift_in==0)
++ {
++ CRC_Result&=(~BIT0);
++ }
++ else
++ {
++ CRC_Result|=BIT0;
++ }
++ //printf("CRC =%x\n",CRC_Result);
++
++ CRC_BIT11 = ((CRC&BIT11) ? 1:0)^shift_in;
++ if(CRC_BIT11==0)
++ {
++ CRC_Result&=(~BIT12);
++ }
++ else
++ {
++ CRC_Result|=BIT12;
++ }
++ //printf("bit12 CRC =%x\n",CRC_Result);
++
++ CRC_BIT4 = ((CRC&BIT4) ? 1:0)^shift_in;
++ if(CRC_BIT4==0)
++ {
++ CRC_Result&=(~BIT5);
++ }
++ else
++ {
++ CRC_Result|=BIT5;
++ }
++ //printf("bit5 CRC =%x\n",CRC_Result);
++
++ CRC=CRC_Result; //­«½Æ¨Ï¥Î¤W¤@¦¸ªºµ²ªG
++ }
++
++ return CRC;
++
++}
++
++
++/////////////////////////////////////////////////
++//
++//function name :calc_crc
++//
++//input : char* pattern , pattern size
++//
++//////////////////////////////////////////////////
++u16 calc_crc(u8 * pdata,int length)
++{
++// unsigned char data[2]={0xC6,0xAA};
++ u16 CRC=0xffff;
++ int i;
++
++ for(i=0;i<length;i++)
++ {
++ CRC=CRC16(pdata[i],CRC);
++ }
++
++ CRC=~CRC; //¨ú¸É¼Æ
++ printk("CRC =%x\n",CRC);
++ return CRC;
++}
++
++static void hw_var_set_opmode(PADAPTER Adapter, u8 variable, u8* val)
++{
++ u8 val8;
++ u8 mode = *((u8 *)val);
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++
++#ifdef CONFIG_CONCURRENT_MODE
++ if(Adapter->iface_type == IFACE_PORT1)
++ {
++ // disable Port1 TSF update
++ rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)|BIT(4));
++
++ // set net_type
++ val8 = rtw_read8(Adapter, MSR)&0x03;
++ val8 |= (mode<<2);
++ rtw_write8(Adapter, MSR, val8);
++
++ //reset TSF1
++ rtw_write8(Adapter, REG_DUAL_TSF_RST, BIT(1));
++
++ DBG_871X("%s()-%d mode = %d\n", __FUNCTION__, __LINE__, mode);
++
++ if((mode == _HW_STATE_STATION_) || (mode == _HW_STATE_NOLINK_))
++ {
++ if(!check_buddy_mlmeinfo_state(Adapter, WIFI_FW_AP_STATE))
++ {
++ StopTxBeacon(Adapter);
++ }
++
++ rtw_write8(Adapter,REG_BCN_CTRL_1, 0x19);//disable atim wnd
++ //rtw_write8(Adapter,REG_BCN_CTRL_1, 0x18);
++ }
++ else if((mode == _HW_STATE_ADHOC_) /*|| (mode == _HW_STATE_AP_)*/)
++ {
++ ResumeTxBeacon(Adapter);
++ rtw_write8(Adapter,REG_BCN_CTRL_1, 0x1a);
++ }
++ else if(mode == _HW_STATE_AP_)
++ {
++ ResumeTxBeacon(Adapter);
++
++ rtw_write8(Adapter, REG_BCN_CTRL_1, 0x12);
++
++ //Set RCR
++ //rtw_write32(padapter, REG_RCR, 0x70002a8e);//CBSSID_DATA must set to 0
++ rtw_write32(Adapter, REG_RCR, 0x7000228e);//CBSSID_DATA must set to 0
++ //enable to rx data frame
++ rtw_write16(Adapter, REG_RXFLTMAP2, 0xFFFF);
++ //enable to rx ps-poll
++ rtw_write16(Adapter, REG_RXFLTMAP1, 0x0400);
++
++ //Beacon Control related register for first time
++ rtw_write8(Adapter, REG_BCNDMATIM, 0x02); // 2ms
++ rtw_write8(Adapter, REG_DRVERLYINT, 0x05);// 5ms
++ //rtw_write8(Adapter, REG_BCN_MAX_ERR, 0xFF);
++ rtw_write8(Adapter, REG_ATIMWND_1, 0x0a); // 10ms for port1
++ rtw_write16(Adapter, REG_BCNTCFG, 0x00);
++ rtw_write16(Adapter, REG_TBTT_PROHIBIT, 0xff04);
++ rtw_write16(Adapter, REG_TSFTR_SYN_OFFSET, 0x7fff);// +32767 (~32ms)
++
++
++ //enable BCN1 Function for if2
++ //don't enable update TSF1 for if2 (due to TSF update when beacon/probe rsp are received)
++ rtw_write8(Adapter, REG_BCN_CTRL_1, (DIS_TSF_UDT0_NORMAL_CHIP|EN_BCN_FUNCTION | EN_TXBCN_RPT|BIT(1)));
++
++#ifdef CONFIG_CONCURRENT_MODE
++ if(check_buddy_fwstate(Adapter, WIFI_FW_NULL_STATE))
++ rtw_write8(Adapter, REG_BCN_CTRL,
++ rtw_read8(Adapter, REG_BCN_CTRL) & ~EN_BCN_FUNCTION);
++#endif
++
++ DBG_871X("%s()-%d: REG_BCN_CTRL_1 = %02x\n", __FUNCTION__, __LINE__, rtw_read8(Adapter, REG_BCN_CTRL_1));
++
++ //BCN1 TSF will sync to BCN0 TSF with offset(0x518) if if1_sta linked
++ //rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)|BIT(5));
++ //rtw_write8(Adapter, REG_DUAL_TSF_RST, BIT(3));
++
++ //dis BCN0 ATIM WND if if1 is station
++ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(0));
++#ifdef CONFIG_TSF_RESET_OFFLOAD
++ // Reset TSF for STA+AP concurrent mode
++ if ( check_buddy_fwstate(Adapter, (WIFI_STATION_STATE|WIFI_ASOC_STATE)) ) {
++ if (reset_tsf(Adapter, IFACE_PORT1) == _FALSE)
++ DBG_871X("ERROR! %s()-%d: Reset port1 TSF fail\n",
++ __FUNCTION__, __LINE__);
++ }
++#endif // CONFIG_TSF_RESET_OFFLOAD
++ }
++
++ }
++ else // (Adapter->iface_type == IFACE_PORT1)
++#endif //CONFIG_CONCURRENT_MODE
++ {
++ // disable Port0 TSF update
++ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(4));
++
++ // set net_type
++ val8 = rtw_read8(Adapter, MSR)&0x0c;
++ val8 |= mode;
++ rtw_write8(Adapter, MSR, val8);
++
++ //reset TSF0
++ rtw_write8(Adapter, REG_DUAL_TSF_RST, BIT(0));
++
++ DBG_871X("%s()-%d mode = %d\n", __FUNCTION__, __LINE__, mode);
++
++ if((mode == _HW_STATE_STATION_) || (mode == _HW_STATE_NOLINK_))
++ {
++#ifdef CONFIG_CONCURRENT_MODE
++ if(!check_buddy_mlmeinfo_state(Adapter, WIFI_FW_AP_STATE))
++#endif //CONFIG_CONCURRENT_MODE
++ {
++ StopTxBeacon(Adapter);
++ }
++
++ rtw_write8(Adapter,REG_BCN_CTRL, 0x19);//disable atim wnd
++ //rtw_write8(Adapter,REG_BCN_CTRL, 0x18);
++ }
++ else if((mode == _HW_STATE_ADHOC_) /*|| (mode == _HW_STATE_AP_)*/)
++ {
++ ResumeTxBeacon(Adapter);
++ rtw_write8(Adapter,REG_BCN_CTRL, 0x1a);
++ }
++ else if(mode == _HW_STATE_AP_)
++ {
++ ResumeTxBeacon(Adapter);
++
++ rtw_write8(Adapter, REG_BCN_CTRL, 0x12);
++
++ //Set RCR
++ //write32(padapter, REG_RCR, 0x70002a8e);//CBSSID_DATA must set to 0
++ rtw_write32(Adapter, REG_RCR, 0x7000228e);//CBSSID_DATA must set to 0
++ //enable to rx data frame
++ rtw_write16(Adapter, REG_RXFLTMAP2, 0xFFFF);
++ //enable to rx ps-poll
++ rtw_write16(Adapter, REG_RXFLTMAP1, 0x0400);
++
++ //Beacon Control related register for first time
++
++ rtw_write8(Adapter, REG_BCNDMATIM, 0x02); // 2ms
++ rtw_write8(Adapter, REG_DRVERLYINT, 0x05);// 5ms
++
++ //write8(Adapter, REG_BCN_MAX_ERR, 0xFF);
++ rtw_write8(Adapter, REG_ATIMWND, 0x0a); // 10ms for port0
++ rtw_write16(Adapter, REG_BCNTCFG, 0x00);
++ rtw_write16(Adapter, REG_TBTT_PROHIBIT, 0xff04);
++ rtw_write16(Adapter, REG_TSFTR_SYN_OFFSET, 0x7fff);// +32767 (~32ms)
++
++ //enable BCN0 Function for if1
++ //don't enable update TSF0 for if1 (due to TSF update when beacon/probe rsp are received)
++ rtw_write8(Adapter, REG_BCN_CTRL, (DIS_TSF_UDT0_NORMAL_CHIP|EN_BCN_FUNCTION | EN_TXBCN_RPT|BIT(1)));
++
++#ifdef CONFIG_CONCURRENT_MODE
++ if(check_buddy_fwstate(Adapter, WIFI_FW_NULL_STATE))
++ rtw_write8(Adapter, REG_BCN_CTRL_1,
++ rtw_read8(Adapter, REG_BCN_CTRL_1) & ~EN_BCN_FUNCTION);
++#endif
++ //BCN1 TSF will sync to BCN0 TSF with offset(0x518) if if1_sta linked
++ //only interface 2 as AP MODE need to sync
++ //rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)|BIT(5));
++
++
++ //dis BCN1 ATIM WND if if2 is station
++ rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)|BIT(0));
++#ifdef CONFIG_TSF_RESET_OFFLOAD
++ // Reset TSF for STA+AP concurrent mode
++ if ( check_buddy_fwstate(Adapter, (WIFI_STATION_STATE|WIFI_ASOC_STATE)) ) {
++ if (reset_tsf(Adapter, IFACE_PORT0) == _FALSE)
++ DBG_871X("ERROR! %s()-%d: Reset port0 TSF fail\n",
++ __FUNCTION__, __LINE__);
++ }
++#endif // CONFIG_TSF_RESET_OFFLOAD
++
++ }
++
++
++ }
++
++}
++
++static void hw_var_set_macaddr(PADAPTER Adapter, u8 variable, u8* val)
++{
++ u8 idx = 0;
++ u32 reg_macid;
++
++#ifdef CONFIG_CONCURRENT_MODE
++ if(Adapter->iface_type == IFACE_PORT1)
++ {
++ reg_macid = REG_MACID1;
++ }
++ else
++#endif
++ {
++ reg_macid = REG_MACID;
++ }
++
++ for(idx = 0 ; idx < 6; idx++)
++ {
++ rtw_write8(Adapter, (reg_macid+idx), val[idx]);
++ }
++
++}
++
++static void hw_var_set_bssid(PADAPTER Adapter, u8 variable, u8* val)
++{
++ u8 idx = 0;
++ u32 reg_bssid;
++
++#ifdef CONFIG_CONCURRENT_MODE
++ if(Adapter->iface_type == IFACE_PORT1)
++ {
++ reg_bssid = REG_BSSID1;
++ }
++ else
++#endif
++ {
++ reg_bssid = REG_BSSID;
++ }
++
++ for(idx = 0 ; idx < 6; idx++)
++ {
++ rtw_write8(Adapter, (reg_bssid+idx), val[idx]);
++ }
++
++}
++
++static void hw_var_set_bcn_func(PADAPTER Adapter, u8 variable, u8* val)
++{
++ u32 bcn_ctrl_reg;
++
++#ifdef CONFIG_CONCURRENT_MODE
++ if(Adapter->iface_type == IFACE_PORT1)
++ {
++ bcn_ctrl_reg = REG_BCN_CTRL_1;
++
++ if(*((u8 *)val))
++ {
++ rtw_write8(Adapter, bcn_ctrl_reg, (EN_BCN_FUNCTION | EN_TXBCN_RPT));
++ }
++ else
++ {
++ rtw_write8(Adapter, bcn_ctrl_reg, rtw_read8(Adapter, bcn_ctrl_reg)&(~(EN_BCN_FUNCTION | EN_TXBCN_RPT)));
++ }
++ }
++ else
++#endif
++ {
++ bcn_ctrl_reg = REG_BCN_CTRL;
++ if(*((u8 *)val))
++ {
++ rtw_write8(Adapter, bcn_ctrl_reg, (EN_BCN_FUNCTION | EN_TXBCN_RPT));
++ }
++ else
++ {
++ //rtw_write8(Adapter, bcn_ctrl_reg, rtw_read8(Adapter, bcn_ctrl_reg)&(~(EN_BCN_FUNCTION | EN_TXBCN_RPT)));
++ rtw_write8(Adapter, bcn_ctrl_reg, (rtw_read8(Adapter, bcn_ctrl_reg)&(~(EN_TXBCN_RPT))) | DIS_TSF_UDT0_NORMAL_CHIP);
++ }
++ }
++
++
++}
++
++#ifdef CONFIG_WOWLAN
++static int rtw_wowlan_set_pattern(_adapter *padapter ,u8* pbuf){
++ struct pwrctrl_priv *pwrpriv=&padapter->pwrctrlpriv;
++ int res=0,crc_idx;
++ u32 content=0,cmd=0;
++ u32 *pdata;
++ u8 config,crc,mc,bc,uc,idx,pattern_len,packet[200],packet_len,valid;
++ u16 crc_val=0,i;
++
++ config=pbuf[0];
++ bc=config & BIT(3)?1:0;
++ mc=config & BIT(4)?1:0;
++ uc=config & BIT(5)?1:0;
++ idx=config & 0x7;
++ crc=config & BIT(6)?1:0;
++ valid=config & BIT(7)?1:0;
++ pattern_len=pbuf[1];
++ packet_len=pattern_len*8;
++ pdata=(u32 *)pbuf;
++
++ // Write to the Wakeup CAM
++ //offset 0
++ if(pattern_len>=4){
++ content=pdata[1];
++ }
++ else{
++ content=0;
++ }
++ DBG_8192C("\nrtw_wowlan_set_pattern offset[0] content 0x%x [cpu_to_le32 0x%x]\n", content,__cpu_to_le32(content));
++ //rtw_write32(padapter, REG_WKFMCAM_RWD, __cpu_to_le32(content));
++ pwrpriv->wowlan_pattern_context[idx][0]= __cpu_to_le32(content);
++ //cmd=BIT(31)|BIT(16)|(idx+0);
++ //rtw_write32(padapter, REG_WKFMCAM_CMD, cmd);
++ //offset 4
++ if(pattern_len>=8){
++ content=pdata[2];
++ }
++ else{
++ content=0;
++ }
++ DBG_8192C("rtw_wowlan_set_pattern offset[4] content 0x%x [cpu_to_le32 0x%x]\n", content,__cpu_to_le32(content));
++ //rtw_write32(padapter, REG_WKFMCAM_RWD, __cpu_to_le32(content));
++ pwrpriv->wowlan_pattern_context[idx][1]= __cpu_to_le32(content);
++
++ //cmd=BIT(31)|BIT(16)|(idx+1);
++ //rtw_write32(padapter, REG_WKFMCAM_CMD, cmd);
++ //offset 8
++ if(pattern_len>=12){
++ content=pdata[3];
++ }
++ else{
++ content=0;
++ }
++ DBG_8192C("rtw_wowlan_set_pattern offset[8] content 0x%x [cpu_to_le32 0x%x]\n", content,__cpu_to_le32(content));
++ //rtw_write32(padapter, REG_WKFMCAM_RWD, __cpu_to_le32(content));
++ pwrpriv->wowlan_pattern_context[idx][2]= __cpu_to_le32(content);
++ //cmd=BIT(31)|BIT(16)|(idx+2);
++ //rtw_write32(padapter, REG_WKFMCAM_CMD, cmd);
++ //offset 12
++ if(pattern_len>=16){
++ content=pdata[4];
++ }
++ else{
++ content=0;
++ }
++ DBG_8192C("rtw_wowlan_set_pattern offset[12] content 0x%x [cpu_to_le32 0x%x]\n", content,__cpu_to_le32(content));
++ //rtw_write32(padapter, REG_WKFMCAM_RWD, __cpu_to_le32(content));
++ pwrpriv->wowlan_pattern_context[idx][3]= __cpu_to_le32(content);
++ //cmd=BIT(31)|BIT(16)|(idx+3);
++ //rtw_write32(padapter, REG_WKFMCAM_CMD, cmd);
++
++ if(crc){
++ // Have the CRC value
++ crc_val=*(u16 *)(&pbuf[2]);
++ DBG_8192C("rtw_wowlan_set_pattern crc_val 0x%x \n", crc_val);
++ crc_val=__cpu_to_le16(crc_val);
++ DBG_8192C("rtw_wowlan_set_pattern crc_val after 0x%x \n", crc_val);
++ }
++ else{
++ DBG_8192C("+rtw_wowlan_set_pattern crc=0[%x] Should calculate the CRC\n", crc);
++ // calculate the CRC the write to the Wakeup CAM
++ crc_idx=0;
++ for(i=0;i<packet_len;i++){
++ if(pbuf[4+(i/8)]&(0x01<<(i%8)))
++ {
++ packet[crc_idx++]=pbuf[20+i];
++ // printk("\n i=%d packet[i]=%x pbuf[20+i(%d)]=%x \n",i,packet[i],20+i,pbuf[20+i]);
++ }
++ }
++ crc_val=calc_crc(packet, crc_idx);
++ printk("+rtw_wowlan_set_pattern crc_val=0x%.8x \n", crc_val);
++
++ }
++
++ //offset 16
++ content=(valid<<31)| (bc<<26)|(mc<<25)|(uc<<24) |crc_val;
++ printk("rtw_wowlan_set_pattern offset[16] content 0x%x \n", content);
++ rtw_write32(padapter, REG_WKFMCAM_RWD,content);
++ pwrpriv->wowlan_pattern_context[idx][4]= content;
++ //cmd=BIT(31)|BIT(16)|(idx+4);
++ //rtw_write32(padapter, REG_WKFMCAM_CMD, cmd);
++ pwrpriv->wowlan_pattern_idx|=BIT(idx);
++
++_rtw_wowlan_set_pattern_exit:
++ return res;
++}
++
++
++
++void rtw_wowlan_reload_pattern(_adapter *padapter){
++ struct pwrctrl_priv *pwrpriv=&padapter->pwrctrlpriv;
++ u32 content=0,cmd=0;
++ u8 idx;
++
++ for (idx=0;idx<8;idx ++){
++ if(pwrpriv->wowlan_pattern_idx & BIT(idx)){
++ //offset 0
++ rtw_write32(padapter, REG_WKFMCAM_RWD, pwrpriv->wowlan_pattern_context[idx][0]);
++ cmd=BIT(31)|BIT(16)|(idx+0);
++ rtw_write32(padapter, REG_WKFMCAM_CMD, cmd);
++
++ //offset 4
++ rtw_write32(padapter, REG_WKFMCAM_RWD, pwrpriv->wowlan_pattern_context[idx][1]);
++ cmd=BIT(31)|BIT(16)|(idx+1);
++ rtw_write32(padapter, REG_WKFMCAM_CMD, cmd);
++
++ //offset 8
++ rtw_write32(padapter, REG_WKFMCAM_RWD, pwrpriv->wowlan_pattern_context[idx][2]);
++ cmd=BIT(31)|BIT(16)|(idx+2);
++ rtw_write32(padapter, REG_WKFMCAM_CMD, cmd);
++
++ //offset 12
++ rtw_write32(padapter, REG_WKFMCAM_RWD, pwrpriv->wowlan_pattern_context[idx][3]);
++ cmd=BIT(31)|BIT(16)|(idx+3);
++ rtw_write32(padapter, REG_WKFMCAM_CMD, cmd);
++
++ //offset 16
++ rtw_write32(padapter, REG_WKFMCAM_RWD, pwrpriv->wowlan_pattern_context[idx][4]);
++ cmd=BIT(31)|BIT(16)|(idx+4);
++ rtw_write32(padapter, REG_WKFMCAM_CMD, cmd);
++
++ }
++ printk("print WOWCAM idx =%d\n",idx);
++ cmd=BIT(31)|(idx+0);
++ rtw_write32(padapter, REG_WKFMCAM_CMD, cmd);
++ printk("print WOWCAM offset[0] =%x\n",rtw_read32(padapter, REG_WKFMCAM_RWD));
++ cmd=BIT(31)|(idx+1);
++ rtw_write32(padapter, REG_WKFMCAM_CMD, cmd);
++ printk("print WOWCAM offset[1] =%x\n",rtw_read32(padapter, REG_WKFMCAM_RWD));
++ cmd=BIT(31)|(idx+2);
++ rtw_write32(padapter, REG_WKFMCAM_CMD, cmd);
++ printk("print WOWCAM offset[2] =%x\n",rtw_read32(padapter, REG_WKFMCAM_RWD));
++ cmd=BIT(31)|(idx+3);
++ rtw_write32(padapter, REG_WKFMCAM_CMD, cmd);
++ printk("print WOWCAM offset[3] =%x\n",rtw_read32(padapter, REG_WKFMCAM_RWD));
++ cmd=BIT(31)|(idx+4);
++ rtw_write32(padapter, REG_WKFMCAM_CMD, cmd);
++ printk("print WOWCAM offset[4] =%x\n",rtw_read32(padapter, REG_WKFMCAM_RWD));
++
++
++ }
++}
++#endif //CONFIG_WOWLAN
++
++static void hw_var_set_correct_tsf(PADAPTER Adapter, u8 variable, u8* val)
++{
++#ifdef CONFIG_CONCURRENT_MODE
++ u64 tsf;
++ struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++
++ //tsf = pmlmeext->TSFValue - ((u32)pmlmeext->TSFValue % (pmlmeinfo->bcn_interval*1024)) -1024; //us
++ tsf = pmlmeext->TSFValue - rtw_modular64(pmlmeext->TSFValue, (pmlmeinfo->bcn_interval*1024)) -1024; //us
++
++ if(((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE))
++ {
++ //pHalData->RegTxPause |= STOP_BCNQ;BIT(6)
++ //rtw_write8(Adapter, REG_TXPAUSE, (rtw_read8(Adapter, REG_TXPAUSE)|BIT(6)));
++ StopTxBeacon(Adapter);
++ }
++
++ if(Adapter->iface_type == IFACE_PORT1)
++ {
++ //disable related TSF function
++ rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)&(~BIT(3)));
++
++ rtw_write32(Adapter, REG_TSFTR1, tsf);
++ rtw_write32(Adapter, REG_TSFTR1+4, tsf>>32);
++
++ //enable related TSF function
++ rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)|BIT(3));
++
++
++#ifdef CONFIG_TSF_RESET_OFFLOAD
++ // Update buddy port's TSF(TBTT) if it is SoftAP for beacon TX issue!
++ if ( (pmlmeinfo->state&0x03) == WIFI_FW_STATION_STATE
++ && check_buddy_fwstate(Adapter, WIFI_AP_STATE) ) {
++ if (reset_tsf(Adapter, IFACE_PORT0) == _FALSE)
++ DBG_871X("ERROR! %s()-%d: Reset port0 TSF fail\n",
++ __FUNCTION__, __LINE__);
++ }
++#endif // CONFIG_TSF_RESET_OFFLOAD
++
++ }
++ else // Adapter->iface_type == IFACE_PORT1
++ {
++ //disable related TSF function
++ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(3)));
++ // disable TSF update instead! May induce burst beacon TX
++ //rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(4));
++
++ rtw_write32(Adapter, REG_TSFTR, tsf);
++ rtw_write32(Adapter, REG_TSFTR+4, tsf>>32);
++
++ //enable related TSF function
++ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(3));
++ //rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(4)));
++
++ // Update buddy port's TSF if it is SoftAP for beacon TX issue!
++ if ( (pmlmeinfo->state&0x03) == WIFI_FW_STATION_STATE
++ && check_buddy_fwstate(Adapter, WIFI_AP_STATE)
++ ) {
++ //disable related TSF function
++ rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)&(~BIT(3)));
++ // disable TSF update instead!
++ //rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL_1)|BIT(4));
++
++ rtw_write32(Adapter, REG_TSFTR1, tsf);
++ rtw_write32(Adapter, REG_TSFTR1+4, tsf>>32);
++
++ //enable related TSF function
++ rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)|BIT(3));
++ //rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL_1)&(~BIT(4)));
++ }
++#ifdef CONFIG_TSF_RESET_OFFLOAD
++ // Update buddy port's TSF if it is SoftAP for beacon TX issue!
++ if ( (pmlmeinfo->state&0x03) == WIFI_FW_STATION_STATE
++ && check_buddy_fwstate(Adapter, WIFI_AP_STATE) ) {
++ if (reset_tsf(Adapter, IFACE_PORT1) == _FALSE)
++ DBG_871X("ERROR! %s()-%d: Reset port1 TSF fail\n",
++ __FUNCTION__, __LINE__);
++ }
++#endif // CONFIG_TSF_RESET_OFFLOAD
++ }
++
++ if(((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE))
++ {
++ //pHalData->RegTxPause &= (~STOP_BCNQ);
++ //rtw_write8(Adapter, REG_TXPAUSE, (rtw_read8(Adapter, REG_TXPAUSE)&(~BIT(6))));
++ ResumeTxBeacon(Adapter);
++ }
++#endif // CONFIG_CONCURRENT_MODE
++}
++
++static void hw_var_set_mlme_disconnect(PADAPTER Adapter, u8 variable, u8* val)
++{
++#ifdef CONFIG_CONCURRENT_MODE
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ PADAPTER pbuddy_adapter = Adapter->pbuddy_adapter;
++
++
++ if(check_buddy_mlmeinfo_state(Adapter, _HW_STATE_NOLINK_))
++ rtw_write16(Adapter, REG_RXFLTMAP2, 0x00);
++
++
++ if(Adapter->iface_type == IFACE_PORT1)
++ {
++ int i;
++ u8 reg_bcn_ctrl_1;
++
++ // a.Driver set 0x422 bit 6 =0
++ rtw_write8(Adapter, REG_FWHW_TXQ_CTRL+2, (pHalData->RegFwHwTxQCtrl) & (~BIT6));
++ pHalData->RegFwHwTxQCtrl &= (~BIT6);
++
++
++#ifdef CONFIG_BEACON_DISABLE_OFFLOAD
++ u8 reg_bcn_disable_cnt = rtw_read8(Adapter, REG_FW_BCN_DIS_CNT);
++ DBG_871X("%s()-%d: reg_bcn_disable_cnt=%02x\n", __FUNCTION__, __LINE__, reg_bcn_disable_cnt);
++
++ reg_bcn_ctrl_1 = rtw_read8(Adapter, REG_BCN_CTRL_1);
++ DBG_871X("%s()-%d: reg_bcn_ctrl_1=%02x\n", __FUNCTION__, __LINE__, reg_bcn_ctrl_1);
++
++ // b. driver set h2c cmd
++ rtl8192c_dis_beacon_fun_cmd(Adapter);
++
++ /*
++ // FW Job for port 0
++
++ c. 8051 set nettype to ap
++ d. 8051 check dma_int
++ e. 8051 set nettype to no_link
++ f.8051 dis_tsf_update 0x550 bit 4
++ g.8051 reset beacon function test count 0x553 bit0.
++ h.8051 disable beacon function 0x550 bit3
++ i. 8051 sent ready to driver
++
++ */
++
++ // The worst case is 100 + 15 ms
++ rtw_msleep_os(120);
++
++ for (i=0; i< 10; i++) {
++ reg_bcn_ctrl_1 = rtw_read8(Adapter, REG_BCN_CTRL_1);
++ if ( (reg_bcn_ctrl_1 & BIT(3)) == 0 ) {
++ //DBG_871X("%s()-%d: BEACON_DISABLE_OFFLOAD finished! reg=%02x\n", __FUNCTION__, __LINE__, reg);
++ break;
++ }
++ DBG_871X("%s()-%d: BEACON_DISABLE_OFFLOAD not finished! REG_BCN_CTRL_1=%02x\n", __FUNCTION__, __LINE__, reg_bcn_ctrl_1);
++ DBG_871X("%s()-%d: reg_bcn_disable_cnt=%02x\n", __FUNCTION__, __LINE__, rtw_read8(Adapter, REG_FW_BCN_DIS_CNT));
++ DBG_871X("%s()-%d: REG_BCN_CTRL=%02x\n", __FUNCTION__, __LINE__, rtw_read8(Adapter, REG_BCN_CTRL));
++ DBG_871X("%s()-%d: FWISR=%08x\n", __FUNCTION__, __LINE__, rtw_read32(Adapter, REG_FWISR));
++ rtw_msleep_os(100);
++ }
++ DBG_871X("%s()-%d: reg_bcn_disable_cnt=%02x\n", __FUNCTION__, __LINE__, rtw_read8(Adapter, REG_FW_BCN_DIS_CNT));
++ DBG_871X("%s()-%d: reg_bcn_ctrl_1=%02x\n", __FUNCTION__, __LINE__, reg_bcn_ctrl_1);
++
++#else // CONFIG_BEACON_DISABLE_OFFLOAD
++
++ //disable update TSF1
++ rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)|BIT(4));
++
++ //reset TSF1
++ rtw_write8(Adapter, REG_DUAL_TSF_RST, BIT(1));
++
++ // disable Port1's beacon function
++ rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)&(~BIT(3)));
++
++#endif // CONFIG_BEACON_DISABLE_OFFLOAD
++
++ // j, Driver set 0x422 bit 6 =1
++ rtw_write8(Adapter, REG_FWHW_TXQ_CTRL+2, (pHalData->RegFwHwTxQCtrl) | BIT6);
++ pHalData->RegFwHwTxQCtrl |= BIT6;
++
++ // k. re_download beacon pkt
++ if(check_buddy_mlmeinfo_state(Adapter, WIFI_FW_AP_STATE))
++ set_tx_beacon_cmd(pbuddy_adapter);
++
++
++ }
++ else // (Adapter->iface_type == IFACE_PORT1)
++ {
++ //disable update TSF
++ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(4));
++
++ //reset TSF
++ rtw_write8(Adapter, REG_DUAL_TSF_RST, BIT(0));
++
++ // Can't disable Port0's beacon function due to it is used by RA
++ }
++#endif
++}
++
++static void hw_var_set_mlme_sitesurvey(PADAPTER Adapter, u8 variable, u8* val)
++{
++ u32 value_rcr, rcr_clear_bit, reg_bcn_ctl;
++ u16 value_rxfltmap2;
++ struct mlme_priv *pmlmepriv=&(Adapter->mlmepriv);
++
++
++#ifdef CONFIG_CONCURRENT_MODE
++ if(Adapter->iface_type == IFACE_PORT1)
++ reg_bcn_ctl = REG_BCN_CTRL_1;
++ else
++#endif
++ reg_bcn_ctl = REG_BCN_CTRL;
++
++#ifdef CONFIG_FIND_BEST_CHANNEL
++
++ if( (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE)
++#ifdef CONFIG_CONCURRENT_MODE
++ || (check_buddy_fwstate(Adapter, WIFI_AP_STATE) == _TRUE)
++#endif
++#ifdef CONFIG_TDLS
++ // TDLS will clear RCR_CBSSID_DATA bit for connection.
++ || ( Adapter->tdlsinfo.setup_state & TDLS_LINKED_STATE )
++#endif // CONFIG_TDLS
++ )
++ {
++ rcr_clear_bit = RCR_CBSSID_BCN;
++ }
++ else
++ {
++ rcr_clear_bit = (RCR_CBSSID_BCN | RCR_CBSSID_DATA);
++ }
++
++ // Recieve all data frames
++ value_rxfltmap2 = 0xFFFF;
++
++#else /* CONFIG_FIND_BEST_CHANNEL */
++
++ rcr_clear_bit = RCR_CBSSID_BCN;
++
++ //config RCR to receive different BSSID & not to receive data frame
++ value_rxfltmap2 = 0;
++
++#endif /* CONFIG_FIND_BEST_CHANNEL */
++
++ value_rcr = rtw_read32(Adapter, REG_RCR);
++
++ if(*((u8 *)val))//under sitesurvey
++ {
++ value_rcr &= ~(rcr_clear_bit);
++ rtw_write32(Adapter, REG_RCR, value_rcr);
++
++ rtw_write16(Adapter, REG_RXFLTMAP2, value_rxfltmap2);
++
++ if (check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_ADHOC_STATE |WIFI_ADHOC_MASTER_STATE)) {
++ //disable update TSF
++ rtw_write8(Adapter, reg_bcn_ctl, rtw_read8(Adapter, reg_bcn_ctl)|BIT(4));
++ }
++
++#ifdef CONFIG_CONCURRENT_MODE
++ if(check_buddy_mlmeinfo_state(Adapter, WIFI_FW_AP_STATE) &&
++ check_buddy_fwstate(Adapter, _FW_LINKED))
++ {
++ StopTxBeacon(Adapter);
++ }
++#endif
++ }
++ else//sitesurvey done
++ {
++ if(check_fwstate(pmlmepriv, _FW_LINKED) || check_fwstate(pmlmepriv, WIFI_AP_STATE)
++#ifdef CONFIG_CONCURRENT_MODE
++ || check_buddy_fwstate(Adapter, _FW_LINKED) || check_buddy_fwstate(Adapter, WIFI_AP_STATE)
++#endif
++ )
++ {
++ //enable to rx data frame
++ rtw_write16(Adapter, REG_RXFLTMAP2,0xFFFF);
++ }
++
++ if (check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_ADHOC_STATE |WIFI_ADHOC_MASTER_STATE)) {
++ //enable update TSF
++ rtw_write8(Adapter, reg_bcn_ctl, rtw_read8(Adapter, reg_bcn_ctl)&(~BIT(4)));
++ }
++
++ value_rcr |= rcr_clear_bit;
++ rtw_write32(Adapter, REG_RCR, value_rcr);
++
++#ifdef CONFIG_CONCURRENT_MODE
++ if(check_buddy_mlmeinfo_state(Adapter, WIFI_FW_AP_STATE) &&
++ check_buddy_fwstate(Adapter, _FW_LINKED))
++ {
++ ResumeTxBeacon(Adapter);
++ }
++#endif
++ }
++}
++
++static void hw_var_set_mlme_join(PADAPTER Adapter, u8 variable, u8* val)
++{
++#ifdef CONFIG_CONCURRENT_MODE
++ u8 RetryLimit = 0x30;
++ u8 type = *((u8 *)val);
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ struct mlme_priv *pmlmepriv = &Adapter->mlmepriv;
++
++ if(type == 0) // prepare to join
++ {
++ if(check_buddy_mlmeinfo_state(Adapter, WIFI_FW_AP_STATE) &&
++ check_buddy_fwstate(Adapter, _FW_LINKED))
++ {
++ StopTxBeacon(Adapter);
++ }
++
++ //enable to rx data frame.Accept all data frame
++ //rtw_write32(padapter, REG_RCR, rtw_read32(padapter, REG_RCR)|RCR_ADF);
++ rtw_write16(Adapter, REG_RXFLTMAP2,0xFFFF);
++
++ if(check_buddy_mlmeinfo_state(Adapter, WIFI_FW_AP_STATE))
++ rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_CBSSID_BCN);
++ else
++ rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_CBSSID_DATA|RCR_CBSSID_BCN);
++
++ if(check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)
++ {
++ RetryLimit = (pHalData->CustomerID == RT_CID_CCX) ? 7 : 48;
++ }
++ else // Ad-hoc Mode
++ {
++ RetryLimit = 0x7;
++ }
++ }
++ else if(type == 1) //joinbss_event call back when join res < 0
++ {
++ if(check_buddy_mlmeinfo_state(Adapter, _HW_STATE_NOLINK_))
++ rtw_write16(Adapter, REG_RXFLTMAP2,0x00);
++
++ if(check_buddy_mlmeinfo_state(Adapter, WIFI_FW_AP_STATE) &&
++ check_buddy_fwstate(Adapter, _FW_LINKED))
++ {
++ ResumeTxBeacon(Adapter);
++
++ //reset TSF 1/2 after ResumeTxBeacon
++ //rtw_write8(Adapter, REG_DUAL_TSF_RST, BIT(1)|BIT(0));
++
++ }
++ }
++ else if(type == 2) //sta add event call back
++ {
++
++ //enable update TSF
++ if(Adapter->iface_type == IFACE_PORT1)
++ rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)&(~BIT(4)));
++ else
++ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(4)));
++
++
++ if(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE))
++ {
++ //fixed beacon issue for 8191su...........
++ rtw_write8(Adapter,0x542 ,0x02);
++ RetryLimit = 0x7;
++ }
++
++
++ if(check_buddy_mlmeinfo_state(Adapter, WIFI_FW_AP_STATE) &&
++ check_buddy_fwstate(Adapter, _FW_LINKED))
++ {
++ ResumeTxBeacon(Adapter);
++
++ //reset TSF 1/2 after ResumeTxBeacon
++ //rtw_write8(Adapter, REG_DUAL_TSF_RST, BIT(1)|BIT(0));
++ }
++
++ }
++
++ rtw_write16(Adapter, REG_RL, RetryLimit << RETRY_LIMIT_SHORT_SHIFT | RetryLimit << RETRY_LIMIT_LONG_SHIFT);
++
++#endif
++}
++
++void SetHwReg8192CU(PADAPTER Adapter, u8 variable, u8* val)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ struct dm_priv *pdmpriv = &pHalData->dmpriv;
++
++_func_enter_;
++
++ switch(variable)
++ {
++ case HW_VAR_MEDIA_STATUS:
++ {
++ u8 val8;
++
++ val8 = rtw_read8(Adapter, MSR)&0x0c;
++ val8 |= *((u8 *)val);
++ rtw_write8(Adapter, MSR, val8);
++ }
++ break;
++ case HW_VAR_MEDIA_STATUS1:
++ {
++ u8 val8;
++
++ val8 = rtw_read8(Adapter, MSR)&0x03;
++ val8 |= *((u8 *)val) <<2;
++ rtw_write8(Adapter, MSR, val8);
++ }
++ break;
++ case HW_VAR_SET_OPMODE:
++ hw_var_set_opmode(Adapter, variable, val);
++ break;
++ case HW_VAR_MAC_ADDR:
++ hw_var_set_macaddr(Adapter, variable, val);
++ break;
++ case HW_VAR_BSSID:
++ hw_var_set_bssid(Adapter, variable, val);
++ break;
++ case HW_VAR_BASIC_RATE:
++ {
++ u16 BrateCfg = 0;
++ u8 RateIndex = 0;
++
++ // 2007.01.16, by Emily
++ // Select RRSR (in Legacy-OFDM and CCK)
++ // For 8190, we select only 24M, 12M, 6M, 11M, 5.5M, 2M, and 1M from the Basic rate.
++ // We do not use other rates.
++ HalSetBrateCfg( Adapter, val, &BrateCfg );
++
++ //2011.03.30 add by Luke Lee
++ //CCK 2M ACK should be disabled for some BCM and Atheros AP IOT
++ //because CCK 2M has poor TXEVM
++ //CCK 5.5M & 11M ACK should be enabled for better performance
++
++ pHalData->BasicRateSet = BrateCfg = (BrateCfg |0xd) & 0x15d;
++
++ BrateCfg |= 0x01; // default enable 1M ACK rate
++
++ DBG_8192C("HW_VAR_BASIC_RATE: BrateCfg(%#x)\n", BrateCfg);
++
++ // Set RRSR rate table.
++ rtw_write8(Adapter, REG_RRSR, BrateCfg&0xff);
++ rtw_write8(Adapter, REG_RRSR+1, (BrateCfg>>8)&0xff);
++ rtw_write8(Adapter, REG_RRSR+2, rtw_read8(Adapter, REG_RRSR+2)&0xf0);
++
++ // Set RTS initial rate
++ while(BrateCfg > 0x1)
++ {
++ BrateCfg = (BrateCfg>> 1);
++ RateIndex++;
++ }
++ // Ziv - Check
++ rtw_write8(Adapter, REG_INIRTS_RATE_SEL, RateIndex);
++ }
++ break;
++ case HW_VAR_TXPAUSE:
++ rtw_write8(Adapter, REG_TXPAUSE, *((u8 *)val));
++ break;
++ case HW_VAR_BCN_FUNC:
++ hw_var_set_bcn_func(Adapter, variable, val);
++ break;
++ case HW_VAR_CORRECT_TSF:
++#ifdef CONFIG_CONCURRENT_MODE
++ hw_var_set_correct_tsf(Adapter, variable, val);
++#else
++ {
++ u64 tsf;
++ struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++
++ //tsf = pmlmeext->TSFValue - ((u32)pmlmeext->TSFValue % (pmlmeinfo->bcn_interval*1024)) -1024; //us
++ tsf = pmlmeext->TSFValue - rtw_modular64(pmlmeext->TSFValue, (pmlmeinfo->bcn_interval*1024)) -1024; //us
++
++ if(((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE))
++ {
++ //pHalData->RegTxPause |= STOP_BCNQ;BIT(6)
++ //rtw_write8(Adapter, REG_TXPAUSE, (rtw_read8(Adapter, REG_TXPAUSE)|BIT(6)));
++ StopTxBeacon(Adapter);
++ }
++
++ //disable related TSF function
++ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(3)));
++
++ rtw_write32(Adapter, REG_TSFTR, tsf);
++ rtw_write32(Adapter, REG_TSFTR+4, tsf>>32);
++
++ //enable related TSF function
++ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(3));
++
++
++ if(((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE))
++ {
++ //pHalData->RegTxPause &= (~STOP_BCNQ);
++ //rtw_write8(Adapter, REG_TXPAUSE, (rtw_read8(Adapter, REG_TXPAUSE)&(~BIT(6))));
++ ResumeTxBeacon(Adapter);
++ }
++ }
++#endif
++ break;
++ case HW_VAR_CHECK_BSSID:
++ if(*((u8 *)val))
++ {
++ rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_CBSSID_DATA|RCR_CBSSID_BCN);
++ }
++ else
++ {
++ u32 val32;
++
++ val32 = rtw_read32(Adapter, REG_RCR);
++ val32 &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN);
++ rtw_write32(Adapter, REG_RCR, val32);
++ }
++ break;
++ case HW_VAR_MLME_DISCONNECT:
++#ifdef CONFIG_CONCURRENT_MODE
++ hw_var_set_mlme_disconnect(Adapter, variable, val);
++#else
++ {
++ //Set RCR to not to receive data frame when NO LINK state
++ //rtw_write32(Adapter, REG_RCR, rtw_read32(padapter, REG_RCR) & ~RCR_ADF);
++ //reject all data frames
++ rtw_write16(Adapter, REG_RXFLTMAP2,0x00);
++
++ //reset TSF
++ rtw_write8(Adapter, REG_DUAL_TSF_RST, (BIT(0)|BIT(1)));
++
++ //disable update TSF
++ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(4));
++ }
++#endif
++ break;
++ case HW_VAR_MLME_SITESURVEY:
++ hw_var_set_mlme_sitesurvey(Adapter, variable, val);
++ break;
++ case HW_VAR_MLME_JOIN:
++#ifdef CONFIG_CONCURRENT_MODE
++ hw_var_set_mlme_join(Adapter, variable, val);
++#else
++ {
++ u8 RetryLimit = 0x30;
++ u8 type = *((u8 *)val);
++ struct mlme_priv *pmlmepriv = &Adapter->mlmepriv;
++
++ if(type == 0) // prepare to join
++ {
++ //enable to rx data frame.Accept all data frame
++ //rtw_write32(padapter, REG_RCR, rtw_read32(padapter, REG_RCR)|RCR_ADF);
++ rtw_write16(Adapter, REG_RXFLTMAP2,0xFFFF);
++
++ rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_CBSSID_DATA|RCR_CBSSID_BCN);
++
++ if(check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)
++ {
++ RetryLimit = (pHalData->CustomerID == RT_CID_CCX) ? 7 : 48;
++ }
++ else // Ad-hoc Mode
++ {
++ RetryLimit = 0x7;
++ }
++ }
++ else if(type == 1) //joinbss_event call back when join res < 0
++ {
++ rtw_write16(Adapter, REG_RXFLTMAP2,0x00);
++ }
++ else if(type == 2) //sta add event call back
++ {
++ //enable update TSF
++ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(4)));
++
++ if(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE))
++ {
++ //fixed beacon issue for 8191su...........
++ rtw_write8(Adapter,0x542 ,0x02);
++ RetryLimit = 0x7;
++ }
++ }
++
++ rtw_write16(Adapter, REG_RL, RetryLimit << RETRY_LIMIT_SHORT_SHIFT | RetryLimit << RETRY_LIMIT_LONG_SHIFT);
++ }
++#endif
++ break;
++
++ case HW_VAR_ON_RCR_AM:
++ rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_AM);
++ DBG_871X("%s, %d, RCR= %x \n", __FUNCTION__,__LINE__, rtw_read32(Adapter, REG_RCR));
++ break;
++ case HW_VAR_OFF_RCR_AM:
++ rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)& (~RCR_AM));
++ DBG_871X("%s, %d, RCR= %x \n", __FUNCTION__,__LINE__, rtw_read32(Adapter, REG_RCR));
++ break;
++
++ case HW_VAR_BEACON_INTERVAL:
++ rtw_write16(Adapter, REG_BCN_INTERVAL, *((u16 *)val));
++ break;
++ case HW_VAR_SLOT_TIME:
++ {
++ u8 u1bAIFS, aSifsTime;
++ struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++
++ rtw_write8(Adapter, REG_SLOT, val[0]);
++
++ if(pmlmeinfo->WMM_enable == 0)
++ {
++ if( pmlmeext->cur_wireless_mode == WIRELESS_11B)
++ aSifsTime = 10;
++ else
++ aSifsTime = 16;
++
++ u1bAIFS = aSifsTime + (2 * pmlmeinfo->slotTime);
++
++ // <Roger_EXP> Temporary removed, 2008.06.20.
++ rtw_write8(Adapter, REG_EDCA_VO_PARAM, u1bAIFS);
++ rtw_write8(Adapter, REG_EDCA_VI_PARAM, u1bAIFS);
++ rtw_write8(Adapter, REG_EDCA_BE_PARAM, u1bAIFS);
++ rtw_write8(Adapter, REG_EDCA_BK_PARAM, u1bAIFS);
++ }
++ }
++ break;
++ case HW_VAR_RESP_SIFS:
++ {
++#if 0
++ // SIFS for OFDM Data ACK
++ rtw_write8(Adapter, REG_SIFS_CTX+1, val[0]);
++ // SIFS for OFDM consecutive tx like CTS data!
++ rtw_write8(Adapter, REG_SIFS_TRX+1, val[1]);
++
++ rtw_write8(Adapter,REG_SPEC_SIFS+1, val[0]);
++ rtw_write8(Adapter,REG_MAC_SPEC_SIFS+1, val[0]);
++
++ // 20100719 Joseph: Revise SIFS setting due to Hardware register definition change.
++ rtw_write8(Adapter, REG_R2T_SIFS+1, val[0]); //0x08 - CCK
++ rtw_write8(Adapter, REG_T2T_SIFS+1, val[0]); //0x0e - OFDM
++#else
++ //SIFS_Timer = 0x0a0a0808;
++ //RESP_SIFS for CCK
++ rtw_write8(Adapter, REG_R2T_SIFS, val[0]); // SIFS_T2T_CCK (0x08)
++ rtw_write8(Adapter, REG_R2T_SIFS+1, val[1]); //SIFS_R2T_CCK(0x08)
++ //RESP_SIFS for OFDM
++ rtw_write8(Adapter, REG_T2T_SIFS, val[2]); //SIFS_T2T_OFDM (0x0a)
++ rtw_write8(Adapter, REG_T2T_SIFS+1, val[3]); //SIFS_R2T_OFDM(0x0a)
++#endif
++ }
++ break;
++ case HW_VAR_ACK_PREAMBLE:
++ {
++ u8 regTmp;
++ u8 bShortPreamble = *( (PBOOLEAN)val );
++ // Joseph marked out for Netgear 3500 TKIP channel 7 issue.(Temporarily)
++ regTmp = (pHalData->nCur40MhzPrimeSC)<<5;
++ //regTmp = 0;
++ if(bShortPreamble)
++ regTmp |= 0x80;
++
++ rtw_write8(Adapter, REG_RRSR+2, regTmp);
++ }
++ break;
++ case HW_VAR_SEC_CFG:
++#ifdef CONFIG_CONCURRENT_MODE
++ rtw_write8(Adapter, REG_SECCFG, 0x0c|BIT(5));// enable tx enc and rx dec engine, and no key search for MC/BC
++#else
++ rtw_write8(Adapter, REG_SECCFG, *((u8 *)val));
++#endif
++ break;
++ case HW_VAR_DM_FLAG:
++ pdmpriv->DMFlag = *((u8 *)val);
++ break;
++ case HW_VAR_DM_FUNC_OP:
++ if(val[0])
++ {// save dm flag
++ pdmpriv->DMFlag_tmp = pdmpriv->DMFlag;
++ }
++ else
++ {// restore dm flag
++ pdmpriv->DMFlag = pdmpriv->DMFlag_tmp;
++ }
++ break;
++ case HW_VAR_DM_FUNC_SET:
++ pdmpriv->DMFlag |= *((u8 *)val);
++ break;
++ case HW_VAR_DM_FUNC_CLR:
++ pdmpriv->DMFlag &= *((u8 *)val);
++ break;
++ case HW_VAR_CAM_EMPTY_ENTRY:
++ {
++ u8 ucIndex = *((u8 *)val);
++ u8 i;
++ u32 ulCommand=0;
++ u32 ulContent=0;
++ u32 ulEncAlgo=CAM_AES;
++
++ for(i=0;i<CAM_CONTENT_COUNT;i++)
++ {
++ // filled id in CAM config 2 byte
++ if( i == 0)
++ {
++ ulContent |=(ucIndex & 0x03) | ((u16)(ulEncAlgo)<<2);
++ //ulContent |= CAM_VALID;
++ }
++ else
++ {
++ ulContent = 0;
++ }
++ // polling bit, and No Write enable, and address
++ ulCommand= CAM_CONTENT_COUNT*ucIndex+i;
++ ulCommand= ulCommand | CAM_POLLINIG|CAM_WRITE;
++ // write content 0 is equall to mark invalid
++ rtw_write32(Adapter, WCAMI, ulContent); //delay_ms(40);
++ //RT_TRACE(COMP_SEC, DBG_LOUD, ("CAM_empty_entry(): WRITE A4: %lx \n",ulContent));
++ rtw_write32(Adapter, RWCAM, ulCommand); //delay_ms(40);
++ //RT_TRACE(COMP_SEC, DBG_LOUD, ("CAM_empty_entry(): WRITE A0: %lx \n",ulCommand));
++ }
++ }
++ break;
++ case HW_VAR_CAM_INVALID_ALL:
++ rtw_write32(Adapter, RWCAM, BIT(31)|BIT(30));
++ break;
++ case HW_VAR_CAM_WRITE:
++ {
++ u32 cmd;
++ u32 *cam_val = (u32 *)val;
++ rtw_write32(Adapter, WCAMI, cam_val[0]);
++
++ cmd = CAM_POLLINIG | CAM_WRITE | cam_val[1];
++ rtw_write32(Adapter, RWCAM, cmd);
++ }
++ break;
++ case HW_VAR_AC_PARAM_VO:
++ rtw_write32(Adapter, REG_EDCA_VO_PARAM, ((u32 *)(val))[0]);
++ break;
++ case HW_VAR_AC_PARAM_VI:
++ rtw_write32(Adapter, REG_EDCA_VI_PARAM, ((u32 *)(val))[0]);
++ break;
++ case HW_VAR_AC_PARAM_BE:
++ pHalData->AcParam_BE = ((u32 *)(val))[0];
++ rtw_write32(Adapter, REG_EDCA_BE_PARAM, ((u32 *)(val))[0]);
++ break;
++ case HW_VAR_AC_PARAM_BK:
++ rtw_write32(Adapter, REG_EDCA_BK_PARAM, ((u32 *)(val))[0]);
++ break;
++ case HW_VAR_ACM_CTRL:
++ {
++ u8 acm_ctrl = *((u8 *)val);
++ u8 AcmCtrl = rtw_read8( Adapter, REG_ACMHWCTRL);
++
++ if(acm_ctrl > 1)
++ AcmCtrl = AcmCtrl | 0x1;
++
++ if(acm_ctrl & BIT(3))
++ AcmCtrl |= AcmHw_VoqEn;
++ else
++ AcmCtrl &= (~AcmHw_VoqEn);
++
++ if(acm_ctrl & BIT(2))
++ AcmCtrl |= AcmHw_ViqEn;
++ else
++ AcmCtrl &= (~AcmHw_ViqEn);
++
++ if(acm_ctrl & BIT(1))
++ AcmCtrl |= AcmHw_BeqEn;
++ else
++ AcmCtrl &= (~AcmHw_BeqEn);
++
++ DBG_871X("[HW_VAR_ACM_CTRL] Write 0x%X\n", AcmCtrl );
++ rtw_write8(Adapter, REG_ACMHWCTRL, AcmCtrl );
++ }
++ break;
++ case HW_VAR_AMPDU_MIN_SPACE:
++ {
++ u8 MinSpacingToSet;
++ u8 SecMinSpace;
++
++ MinSpacingToSet = *((u8 *)val);
++ if(MinSpacingToSet <= 7)
++ {
++ switch(Adapter->securitypriv.dot11PrivacyAlgrthm)
++ {
++ case _NO_PRIVACY_:
++ case _AES_:
++ SecMinSpace = 0;
++ break;
++
++ case _WEP40_:
++ case _WEP104_:
++ case _TKIP_:
++ case _TKIP_WTMIC_:
++ SecMinSpace = 6;
++ break;
++ default:
++ SecMinSpace = 7;
++ break;
++ }
++
++ if(MinSpacingToSet < SecMinSpace){
++ MinSpacingToSet = SecMinSpace;
++ }
++
++ //RT_TRACE(COMP_MLME, DBG_LOUD, ("Set HW_VAR_AMPDU_MIN_SPACE: %#x\n", Adapter->MgntInfo.MinSpaceCfg));
++ rtw_write8(Adapter, REG_AMPDU_MIN_SPACE, (rtw_read8(Adapter, REG_AMPDU_MIN_SPACE) & 0xf8) | MinSpacingToSet);
++ }
++ }
++ break;
++ case HW_VAR_AMPDU_FACTOR:
++ {
++ u8 RegToSet_Normal[4]={0x41,0xa8,0x72, 0xb9};
++ u8 RegToSet_BT[4]={0x31,0x74,0x42, 0x97};
++ u8 FactorToSet;
++ u8 *pRegToSet;
++ u8 index = 0;
++
++#ifdef CONFIG_BT_COEXIST
++ if( (pHalData->bt_coexist.BT_Coexist) &&
++ (pHalData->bt_coexist.BT_CoexistType == BT_CSR_BC4) )
++ pRegToSet = RegToSet_BT; // 0x97427431;
++ else
++#endif
++ pRegToSet = RegToSet_Normal; // 0xb972a841;
++
++ FactorToSet = *((u8 *)val);
++ if(FactorToSet <= 3)
++ {
++ FactorToSet = (1<<(FactorToSet + 2));
++ if(FactorToSet>0xf)
++ FactorToSet = 0xf;
++
++ for(index=0; index<4; index++)
++ {
++ if((pRegToSet[index] & 0xf0) > (FactorToSet<<4))
++ pRegToSet[index] = (pRegToSet[index] & 0x0f) | (FactorToSet<<4);
++
++ if((pRegToSet[index] & 0x0f) > FactorToSet)
++ pRegToSet[index] = (pRegToSet[index] & 0xf0) | (FactorToSet);
++
++ rtw_write8(Adapter, (REG_AGGLEN_LMT+index), pRegToSet[index]);
++ }
++
++ //RT_TRACE(COMP_MLME, DBG_LOUD, ("Set HW_VAR_AMPDU_FACTOR: %#x\n", FactorToSet));
++ }
++ }
++ break;
++ case HW_VAR_RXDMA_AGG_PG_TH:
++ #ifdef CONFIG_USB_RX_AGGREGATION
++ {
++ u8 threshold = *((u8 *)val);
++ if( threshold == 0)
++ {
++ threshold = pHalData->UsbRxAggPageCount;
++ }
++ rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH, threshold);
++ }
++ #endif
++ break;
++ case HW_VAR_SET_RPWM:
++ rtw_write8(Adapter, REG_USB_HRPWM, *((u8 *)val));
++ break;
++ case HW_VAR_H2C_FW_PWRMODE:
++ {
++ u8 psmode = (*(u8 *)val);
++
++ // Forece leave RF low power mode for 1T1R to prevent conficting setting in Fw power
++ // saving sequence. 2010.06.07. Added by tynli. Suggested by SD3 yschang.
++ if( (psmode != PS_MODE_ACTIVE) && (!IS_92C_SERIAL(pHalData->VersionID)))
++ {
++ rtl8192c_dm_RF_Saving(Adapter, _TRUE);
++ }
++ rtl8192c_set_FwPwrMode_cmd(Adapter, psmode);
++ }
++ break;
++ case HW_VAR_H2C_FW_JOINBSSRPT:
++ {
++ u8 mstatus = (*(u8 *)val);
++ rtl8192c_set_FwJoinBssReport_cmd(Adapter, mstatus);
++ }
++ break;
++#ifdef CONFIG_P2P_PS
++ case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
++ {
++ u8 p2p_ps_state = (*(u8 *)val);
++ rtl8192c_set_p2p_ps_offload_cmd(Adapter, p2p_ps_state);
++ }
++ break;
++#endif // CONFIG_P2P_PS
++#ifdef CONFIG_TDLS
++ case HW_VAR_TDLS_WRCR:
++ rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)&(~ BIT(6) ));
++ break;
++ case HW_VAR_TDLS_INIT_CH_SEN:
++ {
++ rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)&(~ BIT(6) )&(~ BIT(7) ));
++ rtw_write16(Adapter, REG_RXFLTMAP2,0xffff);
++
++ //disable update TSF
++ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(4));
++ }
++ break;
++ case HW_VAR_TDLS_DONE_CH_SEN:
++ {
++ //enable update TSF
++ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~ BIT(4)));
++ rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|(BIT(7) ));
++ }
++ break;
++ case HW_VAR_TDLS_RS_RCR:
++ rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|(BIT(6)));
++ break;
++#endif //CONFIG_TDLS
++ case HW_VAR_INITIAL_GAIN:
++ {
++ DIG_T *pDigTable = &pdmpriv->DM_DigTable;
++ u32 rx_gain = ((u32 *)(val))[0];
++
++ if(rx_gain == 0xff){//restore rx gain
++ pDigTable->CurIGValue = pDigTable->BackupIGValue;
++ PHY_SetBBReg(Adapter, rOFDM0_XAAGCCore1, 0x7f,pDigTable->CurIGValue );
++ PHY_SetBBReg(Adapter, rOFDM0_XBAGCCore1, 0x7f,pDigTable->CurIGValue);
++ }
++ else{
++ pDigTable->BackupIGValue = pDigTable->CurIGValue;
++ PHY_SetBBReg(Adapter, rOFDM0_XAAGCCore1, 0x7f,rx_gain );
++ PHY_SetBBReg(Adapter, rOFDM0_XBAGCCore1, 0x7f,rx_gain);
++ pDigTable->CurIGValue = (u8)rx_gain;
++ }
++
++
++ }
++ break;
++ case HW_VAR_TRIGGER_GPIO_0:
++ rtl8192cu_trigger_gpio_0(Adapter);
++ break;
++#ifdef CONFIG_BT_COEXIST
++ case HW_VAR_BT_SET_COEXIST:
++ {
++ u8 bStart = (*(u8 *)val);
++ rtl8192c_set_dm_bt_coexist(Adapter, bStart);
++ }
++ break;
++ case HW_VAR_BT_ISSUE_DELBA:
++ {
++ u8 dir = (*(u8 *)val);
++ rtl8192c_issue_delete_ba(Adapter, dir);
++ }
++ break;
++#endif
++#ifdef CONFIG_SW_ANTENNA_DIVERSITY
++
++ case HW_VAR_ANTENNA_DIVERSITY_LINK:
++ SwAntDivRestAfterLink8192C(Adapter);
++ break;
++ case HW_VAR_ANTENNA_DIVERSITY_SELECT:
++ {
++ u8 Optimum_antenna = (*(u8 *)val);
++ //switch antenna to Optimum_antenna
++ // DBG_8192C("==> HW_VAR_ANTENNA_DIVERSITY_SELECT , Ant_(%s)\n",(Optimum_antenna==2)?"A":"B");
++ if(pHalData->CurAntenna != Optimum_antenna)
++ {
++ PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300, Optimum_antenna);
++ pHalData->CurAntenna = Optimum_antenna ;
++ //DBG_8192C("==> HW_VAR_ANTENNA_DIVERSITY_SELECT , Ant_(%s)\n",(Optimum_antenna==2)?"A":"B");
++ }
++ }
++ break;
++#endif
++ case HW_VAR_EFUSE_BYTES: // To set EFUE total used bytes, added by Roger, 2008.12.22.
++ pHalData->EfuseUsedBytes = *((u16 *)val);
++ break;
++ case HW_VAR_FIFO_CLEARN_UP:
++ {
++ #define RW_RELEASE_EN BIT18
++ #define RXDMA_IDLE BIT17
++
++ struct pwrctrl_priv *pwrpriv = &Adapter->pwrctrlpriv;
++ u8 trycnt = 100;
++
++ //pause tx
++ rtw_write8(Adapter,REG_TXPAUSE,0xff);
++
++ //keep sn
++ Adapter->xmitpriv.nqos_ssn = rtw_read16(Adapter,REG_NQOS_SEQ);
++
++ if(pwrpriv->bkeepfwalive != _TRUE)
++ {
++ //RX DMA stop
++ rtw_write32(Adapter,REG_RXPKT_NUM,(rtw_read32(Adapter,REG_RXPKT_NUM)|RW_RELEASE_EN));
++ do{
++ if(!(rtw_read32(Adapter,REG_RXPKT_NUM)&RXDMA_IDLE))
++ break;
++ }while(trycnt--);
++ if(trycnt ==0)
++ DBG_8192C("Stop RX DMA failed...... \n");
++
++ //RQPN Load 0
++ rtw_write16(Adapter,REG_RQPN_NPQ,0x0);
++ rtw_write32(Adapter,REG_RQPN,0x80000000);
++ rtw_mdelay_os(10);
++ }
++ }
++ break;
++ case HW_VAR_WOWLAN:
++#ifdef CONFIG_WOWLAN
++ {
++ struct wowlan_ioctl_param *poidparam;
++
++ int res;
++
++ poidparam = (struct wowlan_ioctl_param *)val;
++ switch (poidparam->subcode){
++ case WOWLAN_PATTERN_MATCH:
++ //Turn on the Pattern Match feature
++ DBG_8192C("\n PATTERN_MATCH poidparam->subcode_value=%d\n",poidparam->subcode_value);
++ if(poidparam->subcode_value==1){
++ //rtw_write8(Adapter, REG_WOW_CTRL, (rtw_read8(Adapter, REG_WOW_CTRL)|BIT(1)));
++ Adapter->pwrctrlpriv.wowlan_pattern=_TRUE;
++ DBG_8192C("%s Adapter->pwrctrlpriv.wowlan_pattern=%x\n",__FUNCTION__,Adapter->pwrctrlpriv.wowlan_pattern);
++ }
++ else{
++ //rtw_write8(Adapter, REG_WOW_CTRL, (rtw_read8(Adapter, REG_WOW_CTRL)&~BIT(1)));
++ Adapter->pwrctrlpriv.wowlan_pattern=_FALSE;
++ }
++ break;
++ case WOWLAN_MAGIC_PACKET:
++ //Turn on the Magic Packet feature
++ DBG_8192C("\n MAGIC_PACKET poidparam->subcode_value=%d\n",poidparam->subcode_value);
++ if(poidparam->subcode_value==1){
++ //rtw_write8(Adapter, REG_WOW_CTRL, (rtw_read8(Adapter, REG_WOW_CTRL)|BIT(2)));
++ Adapter->pwrctrlpriv.wowlan_magic=_TRUE;
++ DBG_8192C("%s Adapter->pwrctrlpriv.wowlan_magic=%x\n",__FUNCTION__,Adapter->pwrctrlpriv.wowlan_magic);
++ }
++ else{
++ //rtw_write8(Adapter, REG_WOW_CTRL, (rtw_read8(Adapter, REG_WOW_CTRL)&~BIT(2)));
++ Adapter->pwrctrlpriv.wowlan_magic=_FALSE;
++ }
++ break;
++ case WOWLAN_UNICAST:
++ //Turn on the Unicast wakeup feature
++ if(poidparam->subcode_value==1){
++ //rtw_write8(Adapter, REG_WOW_CTRL, (rtw_read8(Adapter, REG_WOW_CTRL)|BIT(3)));
++ Adapter->pwrctrlpriv.wowlan_unicast=_TRUE;
++ }
++ else{
++ //rtw_write8(Adapter, REG_WOW_CTRL, (rtw_read8(Adapter, REG_WOW_CTRL)&~BIT(3)));
++ Adapter->pwrctrlpriv.wowlan_unicast=_FALSE;
++ DBG_8192C("%s Adapter->pwrctrlpriv.wowlan_unicast=%x\n",__FUNCTION__,Adapter->pwrctrlpriv.wowlan_unicast);
++ }
++ break;
++ case WOWLAN_SET_PATTERN:
++ //Setting the Pattern for wowlan
++ res=rtw_wowlan_set_pattern(Adapter,poidparam->pattern);
++ if(res)
++ DBG_8192C("rtw_wowlan_set_pattern retern value=0x%x",res);
++ break;
++ case WOWLAN_DUMP_REG:
++ //dump the WKFMCAM and WOW_CTRL register
++ /*DBG_8192C("\n\n\n\n rtw_wowlan_ctrl: WOW_CTRL=0x%x \n",rtw_read8(Adapter, REG_WOW_CTRL));
++ DBG_8192C("print WKFMCAM index =%d ",poidparam->data[0]);
++ { int cmd=0,offset=0;
++ for(offset=0;offset<5;offset++){
++ cmd=BIT(31)|(poidparam->data[0]+offset);
++ rtw_write32(Adapter, REG_WKFMCAM_CMD, cmd);
++ DBG_8192C("offset[%d]=0x%.8x ",offset,rtw_read32(Adapter, REG_WKFMCAM_RWD));
++ DBG_8192C("offset[%d]=MSB 0x%x:0x%x:0x%x:0x%x ",offset,rtw_read8(Adapter, REG_WKFMCAM_RWD+3),rtw_read8(Adapter, REG_WKFMCAM_RWD+2),rtw_read8(Adapter, REG_WKFMCAM_RWD+1),rtw_read8(Adapter, REG_WKFMCAM_RWD));
++ }
++ }*/
++
++ break;
++ case WOWLAN_ENABLE:
++ SetFwRelatedForWoWLAN8192CU(Adapter, _TRUE);
++ //Set Pattern
++ if(Adapter->pwrctrlpriv.wowlan_pattern==_TRUE)
++ rtw_wowlan_reload_pattern(Adapter);
++ rtl8192c_set_wowlan_cmd(Adapter);
++ rtw_write8(Adapter, 0x6, rtw_read8(Adapter, 0x6)|BIT(3));
++ rtw_msleep_os(10);
++ //DBG_8192C(" \n REG_WOW_CTRL=0x%x \n",rtw_read8(Adapter, REG_WOW_CTRL));
++// if(rtw_read8(Adapter, REG_WOW_CTRL)==0)
++// rtw_write8(Adapter, REG_WOW_CTRL, (rtw_read8(Adapter, REG_WOW_CTRL)|BIT(1)|BIT(2)|BIT(3)));
++ //DBG_8192C(" \n REG_WOW_CTRL=0x%x \n",rtw_read8(Adapter, REG_WOW_CTRL));
++ break;
++
++ case WOWLAN_DISABLE:
++ Adapter->pwrctrlpriv.wowlan_mode=_FALSE;
++ rtl8192c_set_wowlan_cmd(Adapter);
++ rtw_msleep_os(10);
++ break;
++
++ case WOWLAN_STATUS:
++ poidparam->wakeup_reason = rtw_read8(Adapter, REG_WOWLAN_REASON);
++ DBG_8192C("wake on wlan reason 0x%02x\n", poidparam->wakeup_reason);
++ break;
++
++ default:
++ break;
++ }
++ if (Adapter->pwrctrlpriv.wowlan_unicast||Adapter->pwrctrlpriv.wowlan_magic || Adapter->pwrctrlpriv.wowlan_pattern)
++ Adapter->pwrctrlpriv.wowlan_mode =_TRUE;
++ else
++ Adapter->pwrctrlpriv.wowlan_mode =_FALSE;
++ }
++
++ break;
++#endif //CONFIG_WOWLAN
++ case HW_VAR_CHECK_TXBUF:
++#ifdef CONFIG_CONCURRENT_MODE
++ {
++ int i;
++ u8 RetryLimit = 0x01;
++
++ //rtw_write16(Adapter, REG_RL,0x0101);
++ rtw_write16(Adapter, REG_RL, RetryLimit << RETRY_LIMIT_SHORT_SHIFT | RetryLimit << RETRY_LIMIT_LONG_SHIFT);
++
++ for(i=0;i<1000;i++)
++ {
++ if(rtw_read32(Adapter, 0x200) != rtw_read32(Adapter, 0x204))
++ {
++ //DBG_871X("packet in tx packet buffer - 0x204=%x, 0x200=%x (%d)\n", rtw_read32(Adapter, 0x204), rtw_read32(Adapter, 0x200), i);
++ rtw_msleep_os(10);
++ }
++ else
++ {
++ DBG_871X("no packet in tx packet buffer (%d)\n", i);
++ break;
++ }
++ }
++
++ RetryLimit = 0x30;
++ rtw_write16(Adapter, REG_RL, RetryLimit << RETRY_LIMIT_SHORT_SHIFT | RetryLimit << RETRY_LIMIT_LONG_SHIFT);
++
++ }
++#endif
++ break;
++ case HW_VAR_BCN_VALID:
++ //BCN_VALID, BIT16 of REG_TDECTRL = BIT0 of REG_TDECTRL+2, write 1 to clear, Clear by sw
++ rtw_write8(Adapter, REG_TDECTRL+2, rtw_read8(Adapter, REG_TDECTRL+2) | BIT0);
++ break;
++ case HW_VAR_USB_RXAGG_PAGE_TO:
++ rtw_write8(Adapter, REG_USB_DMA_AGG_TO, *((u8 *)val));
++ break;
++ default:
++ break;
++ }
++
++_func_exit_;
++}
++
++void GetHwReg8192CU(PADAPTER Adapter, u8 variable, u8* val)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++
++_func_enter_;
++
++ switch(variable)
++ {
++ case HW_VAR_BASIC_RATE:
++ *((u16 *)(val)) = pHalData->BasicRateSet;
++ case HW_VAR_TXPAUSE:
++ val[0] = rtw_read8(Adapter, REG_TXPAUSE);
++ break;
++ case HW_VAR_BCN_VALID:
++ //BCN_VALID, BIT16 of REG_TDECTRL = BIT0 of REG_TDECTRL+2
++ val[0] = (BIT0 & rtw_read8(Adapter, REG_TDECTRL+2))?_TRUE:_FALSE;
++ break;
++ case HW_VAR_DM_FLAG:
++ val[0] = pHalData->dmpriv.DMFlag;
++ break;
++ case HW_VAR_RF_TYPE:
++ val[0] = pHalData->rf_type;
++ break;
++ case HW_VAR_FWLPS_RF_ON:
++ {
++ //When we halt NIC, we should check if FW LPS is leave.
++ u32 valRCR;
++
++ if(Adapter->pwrctrlpriv.rf_pwrstate == rf_off)
++ {
++ // If it is in HW/SW Radio OFF or IPS state, we do not check Fw LPS Leave,
++ // because Fw is unload.
++ val[0] = _TRUE;
++ }
++ else
++ {
++ valRCR = rtw_read32(Adapter, REG_RCR);
++ valRCR &= 0x00070000;
++ if(valRCR)
++ val[0] = _FALSE;
++ else
++ val[0] = _TRUE;
++ }
++ }
++ break;
++#ifdef CONFIG_ANTENNA_DIVERSITY
++ case HW_VAR_CURRENT_ANTENNA:
++ val[0] = pHalData->CurAntenna;
++ break;
++#endif
++ case HW_VAR_EFUSE_BYTES: // To get EFUE total used bytes, added by Roger, 2008.12.22.
++ *((u16 *)(val)) = pHalData->EfuseUsedBytes;
++ break;
++ case HW_VAR_VID:
++ *((u16 *)(val)) = pHalData->EEPROMVID;
++ break;
++ case HW_VAR_PID:
++ *((u16 *)(val)) = pHalData->EEPROMPID;
++ break;
++ default:
++ break;
++ }
++
++_func_exit_;
++}
++
++//
++// Description:
++// Query setting of specified variable.
++//
++u8
++GetHalDefVar8192CUsb(
++ IN PADAPTER Adapter,
++ IN HAL_DEF_VARIABLE eVariable,
++ IN PVOID pValue
++ )
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ u8 bResult = _TRUE;
++
++ switch(eVariable)
++ {
++ case HAL_DEF_UNDERCORATEDSMOOTHEDPWDB:
++#if 0 //trunk
++ {
++ struct mlme_priv *pmlmepriv = &Adapter->mlmepriv;
++ struct sta_priv * pstapriv = &Adapter->stapriv;
++ struct sta_info * psta;
++ psta = rtw_get_stainfo(pstapriv, pmlmepriv->cur_network.network.MacAddress);
++ if(psta)
++ {
++ *((int *)pValue) = psta->rssi_stat.UndecoratedSmoothedPWDB;
++ }
++ }
++#else //v4 branch
++ //if(check_fwstate(&Adapter->mlmepriv, WIFI_STATION_STATE) == _TRUE){
++ *((int *)pValue) = pHalData->dmpriv.UndecoratedSmoothedPWDB;
++ //}
++ //else{
++
++ //}
++#endif
++ break;
++ case HAL_DEF_IS_SUPPORT_ANT_DIV:
++ #ifdef CONFIG_ANTENNA_DIVERSITY
++ *((u8 *)pValue) = (IS_92C_SERIAL(pHalData->VersionID) ||(pHalData->AntDivCfg==0))?_FALSE:_TRUE;
++ #endif
++ break;
++ case HAL_DEF_CURRENT_ANTENNA:
++ #ifdef CONFIG_ANTENNA_DIVERSITY
++ *(( u8*)pValue) = pHalData->CurAntenna;
++ #endif
++ break;
++ case HAL_DEF_DRVINFO_SZ:
++ *(( u32*)pValue) = DRVINFO_SZ;
++ break;
++ case HAL_DEF_MAX_RECVBUF_SZ:
++ *(( u32*)pValue) = MAX_RECVBUF_SZ;
++ break;
++ case HAL_DEF_RX_PACKET_OFFSET:
++ *(( u32*)pValue) = RXDESC_SIZE + DRVINFO_SZ;
++ break;
++ case HAL_DEF_DBG_DUMP_RXPKT:
++ *(( u8*)pValue) = pHalData->bDumpRxPkt;
++ break;
++ case HAL_DEF_DBG_DM_FUNC:
++ *(( u8*)pValue) = pHalData->dmpriv.DMFlag;
++ break;
++ default:
++ //RT_TRACE(COMP_INIT, DBG_WARNING, ("GetHalDefVar8192CUsb(): Unkown variable: %d!\n", eVariable));
++ bResult = _FALSE;
++ break;
++ }
++
++ return bResult;
++}
++
++
++
++
++//
++// Description:
++// Change default setting of specified variable.
++//
++u8
++SetHalDefVar8192CUsb(
++ IN PADAPTER Adapter,
++ IN HAL_DEF_VARIABLE eVariable,
++ IN PVOID pValue
++ )
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++ u8 bResult = _TRUE;
++
++ switch(eVariable)
++ {
++ case HAL_DEF_DBG_DUMP_RXPKT:
++ pHalData->bDumpRxPkt = *(( u8*)pValue);
++ break;
++ case HAL_DEF_DBG_DM_FUNC:
++ {
++ u8 dm_func = *(( u8*)pValue);
++ struct dm_priv *pdmpriv = &pHalData->dmpriv;
++
++ if(dm_func == 0){ //disable all dynamic func
++ pdmpriv->DMFlag = DYNAMIC_FUNC_DISABLE;
++ DBG_8192C("==> Disable all dynamic function...\n");
++ }
++ else if(dm_func == 1){//disable DIG
++ pdmpriv->DMFlag &= (~DYNAMIC_FUNC_DIG);
++ DBG_8192C("==> Disable DIG...\n");
++ }
++ else if(dm_func == 2){//disable High power
++ pdmpriv->DMFlag &= (~DYNAMIC_FUNC_HP);
++ }
++ else if(dm_func == 3){//disable tx power tracking
++ pdmpriv->DMFlag &= (~DYNAMIC_FUNC_SS);
++ DBG_8192C("==> Disable tx power tracking...\n");
++ }
++ else if(dm_func == 4){//disable BT coexistence
++ pdmpriv->DMFlag &= (~DYNAMIC_FUNC_BT);
++ }
++ else if(dm_func == 5){//disable antenna diversity
++ pdmpriv->DMFlag &= (~DYNAMIC_FUNC_ANT_DIV);
++ }
++ else if(dm_func == 6){//turn on all dynamic func
++ if(!(pdmpriv->DMFlag & DYNAMIC_FUNC_DIG))
++ {
++ struct dm_priv *pdmpriv = &pHalData->dmpriv;
++ DIG_T *pDigTable = &pdmpriv->DM_DigTable;
++ pDigTable->PreIGValue = rtw_read8(Adapter,0xc50);
++ }
++
++ pdmpriv->DMFlag |= (DYNAMIC_FUNC_DIG|DYNAMIC_FUNC_HP|DYNAMIC_FUNC_SS|
++ DYNAMIC_FUNC_BT|DYNAMIC_FUNC_ANT_DIV) ;
++ DBG_8192C("==> Turn on all dynamic function...\n");
++ }
++ }
++ break;
++ default:
++ //RT_TRACE(COMP_INIT, DBG_TRACE, ("SetHalDefVar819xUsb(): Unkown variable: %d!\n", eVariable));
++ bResult = _FALSE;
++ break;
++ }
++
++ return bResult;
++}
++
++u32 _update_92cu_basic_rate(_adapter *padapter, unsigned int mask)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++#ifdef CONFIG_BT_COEXIST
++ struct btcoexist_priv *pbtpriv = &(pHalData->bt_coexist);
++#endif
++ unsigned int BrateCfg = 0;
++
++#ifdef CONFIG_BT_COEXIST
++ if( (pbtpriv->BT_Coexist) && (pbtpriv->BT_CoexistType == BT_CSR_BC4) )
++ {
++ BrateCfg = mask & 0x151;
++ //DBG_8192C("BT temp disable cck 2/5.5/11M, (0x%x = 0x%x)\n", REG_RRSR, BrateCfg & 0x151);
++ }
++ else
++#endif
++ {
++ if(pHalData->VersionID != VERSION_TEST_CHIP_88C)
++ BrateCfg = mask & 0x15F;
++ else //for 88CU 46PING setting, Disable CCK 2M, 5.5M, Others must tuning
++ BrateCfg = mask & 0x159;
++ }
++
++ BrateCfg |= 0x01; // default enable 1M ACK rate
++
++ return BrateCfg;
++}
++
++void _update_response_rate(_adapter *padapter,unsigned int mask)
++{
++ u8 RateIndex = 0;
++ // Set RRSR rate table.
++ rtw_write8(padapter, REG_RRSR, mask&0xff);
++ rtw_write8(padapter,REG_RRSR+1, (mask>>8)&0xff);
++
++
++ // Set RTS initial rate
++ while(mask > 0x1)
++ {
++ mask = (mask>> 1);
++ RateIndex++;
++ }
++ rtw_write8(padapter, REG_INIRTS_RATE_SEL, RateIndex);
++}
++
++void UpdateHalRAMask8192CUsb(PADAPTER padapter, u32 mac_id)
++{
++ //volatile unsigned int result;
++ u8 init_rate=0;
++ u8 networkType, raid;
++ u32 mask;
++ u8 shortGIrate = _FALSE;
++ int supportRateNum = 0;
++ struct sta_info *psta;
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++ struct dm_priv *pdmpriv = &pHalData->dmpriv;
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network);
++#ifdef CONFIG_BT_COEXIST
++ struct btcoexist_priv *pbtpriv = &(pHalData->bt_coexist);
++#endif
++
++ if (mac_id >= NUM_STA) //CAM_SIZE
++ {
++ return;
++ }
++
++ psta = pmlmeinfo->FW_sta_info[mac_id].psta;
++ if(psta == NULL)
++ {
++ return;
++ }
++
++ switch (mac_id)
++ {
++ case 0:// for infra mode
++#ifdef CONFIG_CONCURRENT_MODE
++ case 2:// first station uses macid=0, second station uses macid=2
++#endif
++ supportRateNum = rtw_get_rateset_len(cur_network->SupportedRates);
++ networkType = judge_network_type(padapter, cur_network->SupportedRates, supportRateNum) & 0xf;
++ //pmlmeext->cur_wireless_mode = networkType;
++ raid = networktype_to_raid(networkType);
++
++ mask = update_supported_rate(cur_network->SupportedRates, supportRateNum);
++ mask |= (pmlmeinfo->HT_enable)? update_MSC_rate(&(pmlmeinfo->HT_caps)): 0;
++ mask |= ((raid<<28)&0xf0000000);
++
++ if (support_short_GI(padapter, &(pmlmeinfo->HT_caps)))
++ {
++ shortGIrate = _TRUE;
++ }
++
++ break;
++
++ case 1://for broadcast/multicast
++ supportRateNum = rtw_get_rateset_len(pmlmeinfo->FW_sta_info[mac_id].SupportedRates);
++ if(pmlmeext->cur_wireless_mode & WIRELESS_11B)
++ networkType = WIRELESS_11B;
++ else
++ networkType = WIRELESS_11G;
++ raid = networktype_to_raid(networkType);
++
++ mask = update_basic_rate(cur_network->SupportedRates, supportRateNum);
++ mask |= ((raid<<28)&0xf0000000);
++
++ break;
++
++ default: //for each sta in IBSS
++#ifdef CONFIG_TDLS
++ if(psta->tdls_sta_state & TDLS_LINKED_STATE)
++ {
++ shortGIrate = update_sgi_tdls(padapter, psta);
++ mask = update_mask_tdls(padapter, psta);
++ raid = mask>>28;
++ break;
++ }
++ else
++#endif //CONFIG_TDLS
++ {
++ supportRateNum = rtw_get_rateset_len(pmlmeinfo->FW_sta_info[mac_id].SupportedRates);
++ networkType = judge_network_type(padapter, pmlmeinfo->FW_sta_info[mac_id].SupportedRates, supportRateNum) & 0xf;
++ //pmlmeext->cur_wireless_mode = networkType;
++ raid = networktype_to_raid(networkType);
++
++ mask = update_supported_rate(cur_network->SupportedRates, supportRateNum);
++ mask |= ((raid<<28)&0xf0000000);
++
++ //todo: support HT in IBSS
++
++ break;
++ }
++ }
++
++#ifdef CONFIG_BT_COEXIST
++ if( (pbtpriv->BT_Coexist) &&
++ (pbtpriv->BT_CoexistType == BT_CSR_BC4) &&
++ (pbtpriv->BT_CUR_State) &&
++ (pbtpriv->BT_Ant_isolation) &&
++ ((pbtpriv->BT_Service==BT_SCO)||
++ (pbtpriv->BT_Service==BT_Busy)) )
++ mask &= 0xffffcfc0;
++ else
++#endif
++ mask &=0xffffffff;
++
++
++ init_rate = get_highest_rate_idx(mask)&0x3f;
++
++ if(pHalData->fw_ractrl == _TRUE)
++ {
++ u8 arg = 0;
++
++ //arg = (cam_idx-4)&0x1f;//MACID
++ arg = mac_id&0x1f;//MACID
++
++ arg |= BIT(7);
++
++ if (shortGIrate==_TRUE)
++ arg |= BIT(5);
++
++ DBG_871X("update raid entry, mask=0x%x, arg=0x%x\n", mask, arg);
++ psta->ra_mask=mask;
++#ifdef CONFIG_INTEL_PROXIM
++ if(padapter->proximity.proxim_on ==_TRUE){
++ arg &= ~BIT(6);
++ }
++ else {
++ arg |= BIT(6);
++ }
++#endif //CONFIG_INTEL_PROXIM
++ rtl8192c_set_raid_cmd(padapter, mask, arg);
++
++ }
++ else
++ {
++ if (shortGIrate==_TRUE)
++ init_rate |= BIT(6);
++
++ rtw_write8(padapter, (REG_INIDATA_RATE_SEL+mac_id), init_rate);
++ }
++
++
++ //set ra_id
++ psta->raid = raid;
++ psta->init_rate = init_rate;
++
++ //set correct initial date rate for each mac_id
++ pdmpriv->INIDATA_RATE[mac_id] = init_rate;
++}
++
++void SetBeaconRelatedRegisters8192CUsb(PADAPTER padapter)
++{
++ u32 value32;
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++
++ //reset TSF, enable update TSF, correcting TSF On Beacon
++
++ //REG_BCN_INTERVAL
++ //REG_BCNDMATIM
++ //REG_ATIMWND
++ //REG_TBTT_PROHIBIT
++ //REG_DRVERLYINT
++ //REG_BCN_MAX_ERR
++ //REG_BCNTCFG //(0x510)
++ //REG_DUAL_TSF_RST
++ //REG_BCN_CTRL //(0x550)
++
++ //BCN interval
++ rtw_write16(padapter, REG_BCN_INTERVAL, pmlmeinfo->bcn_interval);
++ rtw_write8(padapter, REG_ATIMWND, 0x02);// 2ms
++
++ _InitBeaconParameters(padapter);
++
++ rtw_write8(padapter, REG_SLOT, 0x09);
++
++ value32 =rtw_read32(padapter, REG_TCR);
++ value32 &= ~TSFRST;
++ rtw_write32(padapter, REG_TCR, value32);
++
++ value32 |= TSFRST;
++ rtw_write32(padapter, REG_TCR, value32);
++
++ // NOTE: Fix test chip's bug (about contention windows's randomness)
++ rtw_write8(padapter, REG_RXTSF_OFFSET_CCK, 0x50);
++ rtw_write8(padapter, REG_RXTSF_OFFSET_OFDM, 0x50);
++
++ _BeaconFunctionEnable(padapter, _TRUE, _TRUE);
++
++ ResumeTxBeacon(padapter);
++
++ //rtw_write8(padapter, 0x422, rtw_read8(padapter, 0x422)|BIT(6));
++
++ //rtw_write8(padapter, 0x541, 0xff);
++
++ //rtw_write8(padapter, 0x542, rtw_read8(padapter, 0x541)|BIT(0));
++
++ rtw_write8(padapter, REG_BCN_CTRL, rtw_read8(padapter, REG_BCN_CTRL)|BIT(1));
++
++}
++
++static void rtl8192cu_init_default_value(_adapter * padapter)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++ struct pwrctrl_priv *pwrctrlpriv = &padapter->pwrctrlpriv;
++ struct dm_priv *pdmpriv = &pHalData->dmpriv;
++ u8 i;
++
++ //init default value
++ pHalData->fw_ractrl = _FALSE;
++ pHalData->bIQKInitialized = _FALSE;
++ if(!pwrctrlpriv->bkeepfwalive)
++ pHalData->LastHMEBoxNum = 0;
++
++ pHalData->bIQKInitialized = _FALSE;
++ //init dm default value
++ pdmpriv->TM_Trigger = 0;
++ pdmpriv->binitialized = _FALSE;
++ pdmpriv->prv_traffic_idx = 3;
++ pdmpriv->initialize = 0;
++
++ pdmpriv->ThermalValue_HP_index = 0;
++ for(i = 0; i < HP_THERMAL_NUM; i++)
++ pdmpriv->ThermalValue_HP[i] = 0;
++}
++
++static u8 rtl8192cu_ps_func(PADAPTER Adapter,HAL_INTF_PS_FUNC efunc_id, u8 *val)
++{
++ u8 bResult = _TRUE;
++ switch(efunc_id){
++
++ #if defined(CONFIG_AUTOSUSPEND) && defined(SUPPORT_HW_RFOFF_DETECTED)
++ case HAL_USB_SELECT_SUSPEND:
++ {
++ u8 bfwpoll = *(( u8*)val);
++ rtl8192c_set_FwSelectSuspend_cmd(Adapter,bfwpoll ,500);//note fw to support hw power down ping detect
++ }
++ break;
++ #endif //CONFIG_AUTOSUSPEND && SUPPORT_HW_RFOFF_DETECTED
++
++ default:
++ break;
++ }
++ return bResult;
++}
++
++void rtl8192cu_set_hal_ops(_adapter * padapter)
++{
++ struct hal_ops *pHalFunc = &padapter->HalFunc;
++
++_func_enter_;
++
++ padapter->HalData = rtw_zmalloc(sizeof(HAL_DATA_TYPE));
++ if(padapter->HalData == NULL){
++ DBG_8192C("cant not alloc memory for HAL DATA \n");
++ }
++ //_rtw_memset(padapter->HalData, 0, sizeof(HAL_DATA_TYPE));
++ padapter->hal_data_sz = sizeof(HAL_DATA_TYPE);
++
++ pHalFunc->hal_init = &rtl8192cu_hal_init;
++ pHalFunc->hal_deinit = &rtl8192cu_hal_deinit;
++
++ //pHalFunc->free_hal_data = &rtl8192c_free_hal_data;
++
++ pHalFunc->inirp_init = &rtl8192cu_inirp_init;
++ pHalFunc->inirp_deinit = &rtl8192cu_inirp_deinit;
++
++ pHalFunc->init_xmit_priv = &rtl8192cu_init_xmit_priv;
++ pHalFunc->free_xmit_priv = &rtl8192cu_free_xmit_priv;
++
++ pHalFunc->init_recv_priv = &rtl8192cu_init_recv_priv;
++ pHalFunc->free_recv_priv = &rtl8192cu_free_recv_priv;
++#ifdef CONFIG_SW_LED
++ pHalFunc->InitSwLeds = &rtl8192cu_InitSwLeds;
++ pHalFunc->DeInitSwLeds = &rtl8192cu_DeInitSwLeds;
++#else //case of hw led or no led
++ pHalFunc->InitSwLeds = NULL;
++ pHalFunc->DeInitSwLeds = NULL;
++#endif//CONFIG_SW_LED
++
++ //pHalFunc->dm_init = &rtl8192c_init_dm_priv;
++ //pHalFunc->dm_deinit = &rtl8192c_deinit_dm_priv;
++
++ pHalFunc->init_default_value = &rtl8192cu_init_default_value;
++ pHalFunc->intf_chip_configure = &rtl8192cu_interface_configure;
++ pHalFunc->read_adapter_info = &ReadAdapterInfo8192CU;
++
++ //pHalFunc->set_bwmode_handler = &PHY_SetBWMode8192C;
++ //pHalFunc->set_channel_handler = &PHY_SwChnl8192C;
++
++ //pHalFunc->hal_dm_watchdog = &rtl8192c_HalDmWatchDog;
++
++ pHalFunc->SetHwRegHandler = &SetHwReg8192CU;
++ pHalFunc->GetHwRegHandler = &GetHwReg8192CU;
++ pHalFunc->GetHalDefVarHandler = &GetHalDefVar8192CUsb;
++ pHalFunc->SetHalDefVarHandler = &SetHalDefVar8192CUsb;
++
++ pHalFunc->UpdateRAMaskHandler = &UpdateHalRAMask8192CUsb;
++ pHalFunc->SetBeaconRelatedRegistersHandler = &SetBeaconRelatedRegisters8192CUsb;
++
++ //pHalFunc->Add_RateATid = &rtl8192c_Add_RateATid;
++
++//#ifdef CONFIG_SW_ANTENNA_DIVERSITY
++ //pHalFunc->AntDivBeforeLinkHandler = &SwAntDivBeforeLink8192C;
++ //pHalFunc->AntDivCompareHandler = &SwAntDivCompare8192C;
++//#endif
++
++ pHalFunc->hal_xmit = &rtl8192cu_hal_xmit;
++ pHalFunc->mgnt_xmit = &rtl8192cu_mgnt_xmit;
++ pHalFunc->hal_xmitframe_enqueue = &rtl8192cu_hal_xmitframe_enqueue;
++
++ //pHalFunc->read_bbreg = &rtl8192c_PHY_QueryBBReg;
++ //pHalFunc->write_bbreg = &rtl8192c_PHY_SetBBReg;
++ //pHalFunc->read_rfreg = &rtl8192c_PHY_QueryRFReg;
++ //pHalFunc->write_rfreg = &rtl8192c_PHY_SetRFReg;
++
++#ifdef CONFIG_HOSTAPD_MLME
++ pHalFunc->hostap_mgnt_xmit_entry = &rtl8192cu_hostap_mgnt_xmit_entry;
++#endif
++ pHalFunc->interface_ps_func = &rtl8192cu_ps_func;
++
++ rtl8192c_set_hal_ops(pHalFunc);
++_func_exit_;
++
++}
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/hal/rtl8192c/usb/usb_ops_ce.c linux-xbian-rpi/drivers/net/wireless/rtl8192cu/hal/rtl8192c/usb/usb_ops_ce.c
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/hal/rtl8192c/usb/usb_ops_ce.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/hal/rtl8192c/usb/usb_ops_ce.c 2015-07-28 01:20:58.313625760 +0200
+@@ -0,0 +1,1205 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#define _HCI_OPS_OS_C_
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++#include <osdep_intf.h>
++
++#ifndef PLATFORM_OS_CE
++ #error "PLATFORM_OS_CE shall be set \n"
++#endif
++
++#ifndef CONFIG_USB_HCI
++ #error "CONFIG_USB_HCI shall be on!\n"
++#endif
++
++#include <usb_ops.h>
++#include <recv_osdep.h>
++
++#include <circ_buf.h>
++
++
++struct zero_bulkout_context
++{
++ void *pbuf;
++ void *purb;
++ void *pirp;
++ void *padapter;
++};
++
++
++
++#define PUSB_ERROR LPDWORD
++#define USBD_HALTED(Status) ((ULONG)(Status) >> 30 == 3)
++
++
++USB_PIPE ffaddr2pipehdl(struct dvobj_priv *pNdisCEDvice, u32 addr);
++
++
++static NTSTATUS usb_async_interrupt_in_complete( LPVOID Context );
++static NTSTATUS usb_async_interrupt_out_complete( LPVOID Context );
++
++DWORD usb_write_port_complete( LPVOID Context );
++DWORD usb_read_port_complete( LPVOID Context );
++
++void usb_read_mem(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem)
++{
++_func_enter_;
++ RT_TRACE( _module_hci_ops_os_c_, _drv_info_, ("%s(%u)\n",__FUNCTION__, __LINE__));
++_func_exit_;
++}
++
++
++
++BOOL
++CloseTransferHandle(
++ LPCUSB_FUNCS pUsbFuncs,
++ USB_TRANSFER hTransfer
++ )
++{
++ BOOL bRc = TRUE;
++
++ // This assert may fail on suprise remove,
++ // but should pass during normal I/O.
++ // ASSERT( pUsbFuncs->lpIsTransferComplete(hTransfer) );
++
++ // CloseTransfer aborts any pending transfers
++ if ( !pUsbFuncs->lpCloseTransfer(hTransfer) ) {
++
++ RT_TRACE( _module_hci_ops_os_c_, _drv_err_, ("*** CloseTransfer ERROR:%d ***\n", GetLastError()));
++ bRc = FALSE;
++ }
++
++ return bRc;
++}
++
++
++BOOL
++GetTransferStatus(
++ LPCUSB_FUNCS pUsbFuncs,
++ USB_TRANSFER hTransfer,
++ LPDWORD pBytesTransferred , // OPTIONAL returns number of bytes transferred
++ PUSB_ERROR pUsbError // returns USB error code
++ )
++{
++
++ BOOL bRc = TRUE;
++
++ if ( pUsbFuncs->lpGetTransferStatus(hTransfer, pBytesTransferred, pUsbError) ) {
++ if ( USB_NO_ERROR != *pUsbError ) {
++ RT_TRACE( _module_hci_ops_os_c_, _drv_err_, ("*** CloseTransfer ERROR:%d ***\n", GetLastError()));
++ RT_TRACE( _module_hci_ops_os_c_, _drv_err_, ("GetTransferStatus (BytesTransferred:%d, UsbError:0x%x)\n", pBytesTransferred?*pBytesTransferred:-1, pUsbError?*pUsbError:-1 ));
++ }
++ } else {
++ RT_TRACE( _module_hci_ops_os_c_, _drv_err_,("*** GetTransferStatus ERROR:%d ***\n", GetLastError()));
++ *pUsbError = USB_CANCELED_ERROR;
++ bRc = FALSE;
++ }
++
++ return bRc;
++}
++
++
++// The driver should never read RxCmd register. We have to set
++// RCR CMDHAT0 (bit6) to append Rx status before the Rx frame.
++//
++// |<-------- pBulkUrb->TransferBufferLength ------------>|
++// +------------------+-------------------+------------+
++// | Rx status (16 bytes) | Rx frame ..... | CRC(4 bytes) |
++// +------------------+-------------------+------------+
++// ^
++// ^pRfd->Buffer.VirtualAddress
++//
++/*! \brief USB RX IRP Complete Routine.
++ @param Context pointer of RT_RFD
++*/
++u32 usb_read_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem)
++{
++ struct intf_priv *pintfpriv = pintfhdl->pintfpriv;
++ struct dvobj_priv *pdvobj_priv = (struct dvobj_priv*)pintfpriv->intf_dev;
++ _adapter *adapter = (_adapter *)pdvobj_priv->padapter;
++
++ struct recv_priv *precvpriv = &adapter->recvpriv;
++
++ struct recv_buf *precvbuf = (struct recv_buf *)rmem;
++ DWORD dwErr = ERROR_SUCCESS ;
++ DWORD dwBytesTransferred = 0 ;
++ USB_TRANSFER hTransfer = NULL;
++ USB_PIPE hPipe;
++ LPCUSB_FUNCS usb_funcs_vp = pdvobj_priv->usb_extension._lpUsbFuncs;
++
++_func_enter_;
++ RT_TRACE( _module_hci_ops_os_c_, _drv_info_, ("usb_read_port(%u)\n", __LINE__));
++
++#if (CONFIG_PWRCTRL == 1)
++ if (adapter->pwrctrlpriv.pnp_bstop_trx)
++ {
++ return _FALSE;
++ }
++#endif
++
++ if(adapter->bDriverStopped || adapter->bSurpriseRemoved)
++ {
++ RT_TRACE(_module_hci_ops_os_c_, _drv_info_,("usb_read_port:( padapter->bDriverStopped ||padapter->bSurpriseRemoved)!!!\n"));
++ return _FALSE;
++ }
++
++ if(precvbuf !=NULL)
++ {
++
++ // get a recv buffer
++ rtl8192cu_init_recvbuf(adapter, precvbuf);
++
++
++
++ _rtw_spinlock(&precvpriv->lock);
++ precvpriv->rx_pending_cnt++;
++ precvbuf->irp_pending = _TRUE;
++ _rtw_spinunlock(&precvpriv->lock);
++
++
++ //translate DMA FIFO addr to pipehandle
++ hPipe = ffaddr2pipehdl(pdvobj_priv, addr);
++
++
++ RT_TRACE( _module_hci_ops_os_c_, _drv_info_, ("usb_read_port(%u)\n", __LINE__));
++
++ precvbuf->usb_transfer_read_port = (*usb_funcs_vp->lpIssueBulkTransfer)(
++ hPipe,
++ usb_read_port_complete,
++ precvbuf,
++ USB_IN_TRANSFER|USB_SHORT_TRANSFER_OK,
++ MAX_RECVBUF_SZ,
++ precvbuf->pbuf,
++ 0);
++
++
++ if(precvbuf->usb_transfer_read_port)
++ {
++
++ // GetTransferStatus(usb_funcs_vp, hTransfer, &dwBytesTransferred,&UsbRc);
++
++ // CloseTransferHandle(usb_funcs_vp, hTransfer);
++
++ }
++ else
++ {
++
++ dwErr = GetLastError();
++ //RT_TRACE( _module_hci_ops_os_c_, _drv_err_, ("usb_read_port ERROR : %d\n", dwErr));
++
++ }
++
++// if ( USB_NO_ERROR != UsbRc && ERROR_SUCCESS == dwErr) {
++// dwErr = ERROR_GEN_FAILURE;
++// }
++
++
++ if ( ERROR_SUCCESS != dwErr ) {
++
++ SetLastError(dwErr);
++ RT_TRACE( _module_hci_ops_os_c_, _drv_err_, ("usb_read_port ERROR : %d\n", dwErr));
++ }
++
++ RT_TRACE( _module_hci_ops_os_c_, _drv_info_, ("-usb_read_port(%u)\n", __LINE__));
++
++ }
++ else // if(precvbuf !=NULL)
++ {
++
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port:precv_frame ==NULL\n"));
++ }
++
++ return _TRUE;
++
++}
++
++DWORD usb_read_port_complete( PVOID context )
++{
++ struct recv_buf *precvbuf = (struct recv_buf *)context;
++ _adapter *adapter = (_adapter *)precvbuf->adapter;
++ struct recv_priv *precvpriv = &adapter->recvpriv;
++
++
++ struct intf_hdl *pintfhdl = &adapter->pio_queue->intf;
++ struct intf_priv *pintfpriv = pintfhdl->pintfpriv;
++ struct dvobj_priv *pdvobj_priv = (struct dvobj_priv*)pintfpriv->intf_dev;
++
++
++ LPCUSB_FUNCS usb_funcs_vp = pdvobj_priv->usb_extension._lpUsbFuncs;
++
++ DWORD dwBytesTransferred = 0;
++ DWORD dwErr = USB_CANCELED_ERROR;
++
++ uint isevt, *pbuf;
++ int fComplete =_FALSE;
++
++
++ RT_TRACE( _module_hci_ops_os_c_, _drv_info_, ("usb_read_port_complete(%u)\n", __LINE__));
++
++_func_enter_;
++
++
++ _rtw_spinlock_ex(&precvpriv->lock);
++ precvbuf->irp_pending=_FALSE;
++ precvpriv->rx_pending_cnt --;
++ _rtw_spinunlock_ex(&precvpriv->lock);
++
++
++#if 1
++
++ (*usb_funcs_vp->lpGetTransferStatus)(precvbuf->usb_transfer_read_port, &dwBytesTransferred, &dwErr);
++ fComplete = (*usb_funcs_vp->lpIsTransferComplete)(precvbuf->usb_transfer_read_port);
++ if(fComplete!=_TRUE)
++ {
++ RT_TRACE( _module_hci_ops_os_c_, _drv_err_, ("usb_read_port_complete CloseTransfer before complete\n"));
++ }
++ (*usb_funcs_vp->lpCloseTransfer)(precvbuf->usb_transfer_read_port);
++
++
++#endif
++
++
++ if(USB_NO_ERROR != dwErr)
++ RT_TRACE( _module_hci_ops_os_c_, _drv_err_, ("usb_read_port_complete Fail :%d\n",dwErr));
++
++ {
++
++ if ( dwBytesTransferred > MAX_RECVBUF_SZ || dwBytesTransferred < RXDESC_SIZE )
++ {
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,
++ ("\n usb_read_port_complete: (pbulkurb->TransferBufferLength > MAX_RECVBUF_SZ) || (pbulkurb->TransferBufferLength < RXDESC_SIZE): %d\n",dwBytesTransferred));
++ rtw_read_port(adapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf);
++
++ //usb_read_port(pintfhdl, 0, 0, (unsigned char *)precvframe);
++ }
++ else
++ {
++ precvbuf->transfer_len = dwBytesTransferred;
++
++ pbuf = (uint*)precvbuf->pbuf;
++
++ if((isevt = *(pbuf+1)&0x1ff) == 0x1ff)
++ {
++ RT_TRACE(_module_hci_ops_os_c_,_drv_info_,
++ ("\n usb_read_port_complete: get a event\n"));
++ rxcmd_event_hdl(adapter, pbuf);//rx c2h events
++
++ rtw_read_port(adapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf);
++ }
++ else
++ {
++ if(recvbuf2recvframe(adapter, precvbuf)==_FAIL)//rx packets
++ {
++ //precvbuf->reuse = _TRUE;
++ rtw_read_port(adapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf);
++ }
++ }
++ }
++ }
++
++ RT_TRACE( _module_hci_ops_os_c_, _drv_info_, ("-usb_read_port_complete(%u)\n", __LINE__));
++
++_func_exit_;
++ return ERROR_SUCCESS;
++// return STATUS_MORE_PROCESSING_REQUIRED;
++}
++
++void usb_read_port_cancel(_adapter *padapter){
++ RT_TRACE( _module_hci_ops_os_c_, _drv_info_, ("usb_read_port_cancel(%u)\n",__FUNCTION__, __LINE__));
++}
++
++DWORD usb_write_mem_complete( LPVOID Context )
++{
++ int fComplete =_FALSE;
++ DWORD dwBytes = 0;
++ DWORD dwErr = USB_CANCELED_ERROR;
++
++ _irqL irqL;
++ _list *head;
++ _list *plist;
++ struct io_req *pio_req;
++ struct io_queue *pio_q = (struct io_queue *) Context;
++ struct intf_hdl *pintf = &(pio_q->intf);
++ struct intf_priv *pintfpriv = pintf->pintfpriv;
++ _adapter *padapter = (_adapter *)pintf->adapter;
++ NTSTATUS status = STATUS_SUCCESS;
++ struct xmit_priv * pxmitpriv = &padapter->xmitpriv;
++
++ struct dvobj_priv * pdvobj_priv = (struct dvobj_priv*)pintfpriv->intf_dev;
++
++ USB_HANDLE usbHandle = pdvobj_priv->usb_extension._hDevice;
++ LPCUSB_FUNCS usb_funcs_vp = pdvobj_priv->usb_extension._lpUsbFuncs;
++
++ // get the head from the processing io_queue
++ head = &(pio_q->processing);
++
++_func_enter_;
++ RT_TRACE( _module_hci_ops_os_c_, _drv_info_, ("+usb_write_mem_complete %p\n", Context));
++
++#if 1
++ _enter_critical_bh(&(pio_q->lock), &irqL);
++
++
++ //free irp in processing list...
++ while(rtw_is_list_empty(head) != _TRUE)
++ {
++ plist = get_next(head);
++ rtw_list_delete(plist);
++ pio_req = LIST_CONTAINOR(plist, struct io_req, list);
++ _rtw_up_sema(&pio_req->sema);
++ }
++
++ _exit_critical_bh(&(pio_q->lock), &irqL);
++#endif
++
++
++#if 1
++
++ (*usb_funcs_vp->lpGetTransferStatus)(pio_req->usb_transfer_write_mem , &dwBytes, &dwErr);
++ fComplete = (*usb_funcs_vp->lpIsTransferComplete)(pio_req->usb_transfer_write_mem);
++ if(fComplete!=_TRUE)
++ {
++ RT_TRACE( _module_hci_ops_os_c_, _drv_err_, ("usb_write_mem_complete CloseTransfer before complete\n"));
++ }
++ (*usb_funcs_vp->lpCloseTransfer)(pio_req->usb_transfer_write_mem );
++
++#endif
++
++ RT_TRACE( _module_hci_ops_os_c_, _drv_info_, ("-usb_write_mem_complete\n"));
++
++_func_exit_;
++
++
++ return STATUS_MORE_PROCESSING_REQUIRED;
++
++}
++
++
++void usb_write_mem(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *wmem)
++{
++
++ NTSTATUS NtStatus = STATUS_SUCCESS;
++ USB_PIPE hPipe;
++ _irqL irqL;
++
++ int fComplete = _FALSE;
++ DWORD dwBytes = 0;
++ DWORD dwErr = USB_CANCELED_ERROR;
++
++
++ struct io_req *pio_req;
++
++ _adapter *adapter = (_adapter *)pintfhdl->adapter;
++ struct intf_priv *pintfpriv = pintfhdl->pintfpriv;
++ struct dvobj_priv * pdvobj_priv = (struct dvobj_priv*)pintfpriv->intf_dev;
++
++
++ struct xmit_priv *pxmitpriv = &adapter->xmitpriv;
++ struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
++
++ LPCUSB_FUNCS usb_funcs_vp = pdvobj_priv->usb_extension._lpUsbFuncs;
++
++
++_func_enter_;
++ RT_TRACE( _module_hci_ops_os_c_, _drv_info_, ("usb_write_mem(%u) pintfhdl %p wmem %p\n", __LINE__, pintfhdl, wmem));
++
++ // fetch a io_request from the io_queue
++ pio_req = alloc_ioreq(pio_queue);
++
++ if ((pio_req == NULL)||(adapter->bSurpriseRemoved))
++ {
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("async_irp_write32 : pio_req =0x%x adapter->bSurpriseRemoved=0x%x",pio_req,adapter->bSurpriseRemoved ));
++ goto exit;
++ }
++
++ _enter_critical_bh(&(pio_queue->lock), &irqL);
++
++
++ // insert the io_request into processing io_queue
++ rtw_list_insert_tail(&(pio_req->list),&(pio_queue->processing));
++
++
++ if((adapter->bDriverStopped) || (adapter->bSurpriseRemoved) ||(adapter->pwrctrlpriv.pnp_bstop_trx))
++ {
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("\npadapter->pwrctrlpriv.pnp_bstop_trx==_TRUE\n"));
++ goto exit;
++ }
++
++ //translate DMA FIFO addr to pipehandle
++ hPipe = ffaddr2pipehdl(pdvobj_priv, addr);
++
++ RT_TRACE( _module_hci_ops_os_c_, _drv_info_,("usb_write_mem(%u)\n",__LINE__));
++
++ pio_req->usb_transfer_write_mem = (*usb_funcs_vp->lpIssueBulkTransfer)(
++ hPipe,
++ usb_write_mem_complete,
++ pio_queue,
++ USB_OUT_TRANSFER,
++ cnt,
++ wmem,
++ 0);
++
++#if 0
++
++ (*usb_funcs_vp->lpGetTransferStatus)(pio_req->usb_transfer_write_mem , &dwBytes, &dwErr);
++
++ while( fComplete != _TRUE)
++ {
++ fComplete = (*usb_funcs_vp->lpIsTransferComplete)(pio_req->usb_transfer_write_mem);
++ if(fComplete==_TRUE)
++ {
++ (*usb_funcs_vp->lpCloseTransfer)(pio_req->usb_transfer_write_mem );
++ RT_TRACE( _module_hci_ops_os_c_, _drv_err_, ("usb_write_mem finished\n"));
++ break;
++ }
++ else
++ {
++ RT_TRACE( _module_hci_ops_os_c_, _drv_err_,
++ ("usb_write_mem not yet finished %X\n",
++ pio_req->usb_transfer_write_mem));
++ rtw_msleep_os(10);
++ }
++
++ }
++
++#endif
++
++
++// _rtw_down_sema(&pio_req->sema);
++
++ RT_TRACE( _module_hci_ops_os_c_, _drv_info_, ("-usb_write_mem(%X)\n",pio_req->usb_transfer_write_mem));
++
++ _exit_critical_bh(&(pio_queue->lock), &irqL);
++
++ _rtw_down_sema(&pio_req->sema);
++ free_ioreq(pio_req, pio_queue);
++
++exit:
++_func_exit_;
++ return;
++}
++
++u32 usb_write_cnt=0;
++u32 usb_complete_cnt=0;
++
++USB_PIPE ffaddr2pipehdl(struct dvobj_priv *pNdisCEDvice, u32 addr)
++{
++ USB_PIPE PipeHandle = NULL;
++ _adapter *padapter = pNdisCEDvice->padapter;
++
++
++ if(pNdisCEDvice->nr_endpoint == 11)
++ {
++ switch(addr)
++ {
++ case RTL8712_DMA_BEQ:
++ PipeHandle= padapter->halpriv.pipehdls_r8712[3] ;
++ break;
++ case RTL8712_DMA_BKQ:
++ PipeHandle= padapter->halpriv.pipehdls_r8712[4];
++ break;
++ case RTL8712_DMA_VIQ:
++ PipeHandle= padapter->halpriv.pipehdls_r8712[2];
++ break;
++ case RTL8712_DMA_VOQ:
++ PipeHandle= padapter->halpriv.pipehdls_r8712[1];
++ break;
++ case RTL8712_DMA_BCNQ:
++ PipeHandle= padapter->halpriv.pipehdls_r8712[6];
++ break;
++ case RTL8712_DMA_BMCQ: //HI Queue
++ PipeHandle= padapter->halpriv.pipehdls_r8712[7];
++ break;
++ case RTL8712_DMA_MGTQ:
++ PipeHandle= padapter->halpriv.pipehdls_r8712[8];
++ break;
++ case RTL8712_DMA_RX0FF:
++ PipeHandle= padapter->halpriv.pipehdls_r8712[0];
++ break;
++ case RTL8712_DMA_C2HCMD:
++ PipeHandle= padapter->halpriv.pipehdls_r8712[5];
++ break;
++ case RTL8712_DMA_H2CCMD:
++ PipeHandle= padapter->halpriv.pipehdls_r8712[9];
++ break;
++
++ }
++
++ }
++ else if(pNdisCEDvice->nr_endpoint == 6)
++ {
++ switch(addr)
++ {
++ case RTL8712_DMA_BEQ:
++ PipeHandle= padapter->halpriv.pipehdls_r8712[3];
++ break;
++ case RTL8712_DMA_BKQ:
++ PipeHandle= padapter->halpriv.pipehdls_r8712[4];
++ break;
++ case RTL8712_DMA_VIQ:
++ PipeHandle= padapter->halpriv.pipehdls_r8712[2];
++ break;
++ case RTL8712_DMA_VOQ:
++ PipeHandle= padapter->halpriv.pipehdls_r8712[1];
++ break;
++ case RTL8712_DMA_RX0FF:
++ case RTL8712_DMA_C2HCMD:
++ PipeHandle= padapter->halpriv.pipehdls_r8712[0];
++ break;
++ case RTL8712_DMA_H2CCMD:
++ case RTL8712_DMA_BCNQ:
++ case RTL8712_DMA_BMCQ:
++ case RTL8712_DMA_MGTQ:
++ PipeHandle= padapter->halpriv.pipehdls_r8712[5];
++ break;
++
++ }
++
++ }
++ else if(pNdisCEDvice->nr_endpoint == 4)
++ {
++ switch(addr)
++ {
++ case RTL8712_DMA_BEQ:
++ case RTL8712_DMA_BKQ:
++ PipeHandle= padapter->halpriv.pipehdls_r8712[2];
++ break;
++ case RTL8712_DMA_VIQ:
++ case RTL8712_DMA_VOQ:
++ PipeHandle= padapter->halpriv.pipehdls_r8712[1];
++ break;
++ case RTL8712_DMA_RX0FF:
++ case RTL8712_DMA_C2HCMD:
++ PipeHandle= padapter->halpriv.pipehdls_r8712[0];
++ break;
++ case RTL8712_DMA_H2CCMD:
++ case RTL8712_DMA_BCNQ:
++ case RTL8712_DMA_BMCQ:
++ case RTL8712_DMA_MGTQ:
++ PipeHandle= padapter->halpriv.pipehdls_r8712[3];
++ break;
++ }
++
++ }
++ else
++ {
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("ffaddr2pipehdl():nr_endpoint=%d error!\n", pNdisCEDvice->nr_endpoint));
++ }
++
++ return PipeHandle;
++
++}
++
++DWORD usb_bulkout_zero_complete( LPVOID pZeroContext )
++{
++ struct zero_bulkout_context *pcontext = (struct zero_bulkout_context *)pZeroContext;
++ _adapter * padapter = pcontext->padapter;
++ struct dvobj_priv * pdvobj_priv = (struct dvobj_priv *)&padapter->dvobjpriv;
++ LPCUSB_FUNCS usb_funcs_vp = pdvobj_priv->usb_extension._lpUsbFuncs;
++ struct xmit_priv * pxmitpriv = &padapter->xmitpriv;
++
++ int fComplete =_FALSE;
++ DWORD dwBytesTransferred = 0;
++ DWORD dwErr = USB_CANCELED_ERROR;
++
++_func_enter_;
++
++#if 1
++
++ (*usb_funcs_vp->lpGetTransferStatus)(pxmitpriv->usb_transfer_write_port, &dwBytesTransferred, &dwErr);
++ fComplete = (*usb_funcs_vp->lpIsTransferComplete)(pxmitpriv->usb_transfer_write_port);
++ if(fComplete!=_TRUE)
++ {
++ RT_TRACE( _module_hci_ops_os_c_, _drv_err_, ("usb_bulkout_zero_complete CloseTransfer before complete\n"));
++ }
++ (*usb_funcs_vp->lpCloseTransfer)(pxmitpriv->usb_transfer_write_port);
++
++#endif
++
++ if(pcontext)
++ {
++ if(pcontext->pbuf)
++ {
++ rtw_mfree(pcontext->pbuf, sizeof(int));
++ }
++
++ rtw_mfree((u8*)pcontext, sizeof(struct zero_bulkout_context));
++ }
++
++_func_exit_;
++
++ return ERROR_SUCCESS;
++
++
++}
++
++u32 usb_bulkout_zero(struct intf_hdl *pintfhdl, u32 addr)
++{
++ struct zero_bulkout_context *pcontext;
++ unsigned char *pbuf;
++ u8 len = 0 ;
++ _adapter *padapter = (_adapter *)pintfhdl->adapter;
++ struct dvobj_priv *pdvobj = (struct dvobj_priv *)&padapter->dvobjpriv;
++ struct xmit_priv * pxmitpriv = &padapter->xmitpriv;
++
++
++ LPCUSB_FUNCS usb_funcs_vp = pdvobj->usb_extension._lpUsbFuncs;
++
++ USB_PIPE hPipe;
++
++_func_enter_;
++
++ if((padapter->bDriverStopped) || (padapter->bSurpriseRemoved) ||(padapter->pwrctrlpriv.pnp_bstop_trx))
++ {
++ return _FAIL;
++ }
++
++
++ pcontext = (struct zero_bulkout_context *)rtw_zmalloc(sizeof(struct zero_bulkout_context));
++
++ pbuf = (unsigned char *)rtw_zmalloc(sizeof(int));
++
++ len = 0;
++
++ pcontext->pbuf = pbuf;
++ pcontext->purb = NULL;
++ pcontext->pirp = NULL;
++ pcontext->padapter = padapter;
++
++
++//translate DMA FIFO addr to pipehandle
++ hPipe = ffaddr2pipehdl(pdvobj, addr);
++
++
++
++
++ pxmitpriv->usb_transfer_write_port = (*usb_funcs_vp->lpIssueBulkTransfer)(
++ hPipe, usb_bulkout_zero_complete,
++ pcontext, USB_OUT_TRANSFER,
++ len, pbuf, 0);
++
++
++_func_exit_;
++
++ return _SUCCESS;
++
++}
++
++u32 usb_write_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *wmem)
++{
++
++ u32 i, bwritezero = _FALSE;
++ u32 ac_tag = addr;
++
++ u8* ptr;
++
++ struct intf_priv * pintfpriv = pintfhdl->pintfpriv;
++ struct dvobj_priv * pdvobj_priv = (struct dvobj_priv*)pintfpriv->intf_dev;
++ _adapter * padapter = pdvobj_priv->padapter;
++
++ struct xmit_priv * pxmitpriv = &padapter->xmitpriv;
++ struct xmit_frame * pxmitframe = (struct xmit_frame *)wmem;
++
++ LPCUSB_FUNCS usb_funcs_vp = pdvobj_priv->usb_extension._lpUsbFuncs;
++
++ USB_PIPE hPipe;
++
++ u32 bResult = _FALSE;
++
++_func_enter_;
++ RT_TRACE( _module_hci_ops_os_c_, _drv_info_, ("+usb_write_port\n"));
++
++#if (CONFIG_PWRCTRL == 1)
++ if(padapter->pwrctrlpriv.pnp_bstop_trx==_TRUE){
++ RT_TRACE( _module_hci_ops_os_c_, _drv_err_, ("\npadapter->pwrctrlpriv.pnp_bstop_trx==_TRUE\n"));
++
++ }
++#endif
++
++ if((padapter->bDriverStopped) || (padapter->bSurpriseRemoved) ||(padapter->pwrctrlpriv.pnp_bstop_trx))
++ {
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_write_port:( padapter->bDriverStopped ||padapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx)!!!\n"));
++ bResult = _FALSE;
++ goto exit;
++ }
++
++ RT_TRACE( _module_hci_ops_os_c_, _drv_info_, ("usb_write_port(%u)\n", __LINE__));
++
++ for(i=0; i<8; i++)
++ {
++ if(pxmitframe->bpending[i] == _FALSE)
++ {
++ _rtw_spinlock(&pxmitpriv->lock);
++ pxmitpriv->txirp_cnt++;
++ pxmitframe->bpending[i] = _TRUE;
++ _rtw_spinunlock(&pxmitpriv->lock);
++
++ pxmitframe->sz[i] = cnt;
++ pxmitframe->ac_tag[i] = ac_tag;
++
++ break;
++ }
++ }
++
++
++ //TODO:
++ if (pdvobj_priv->ishighspeed)
++ {
++ if(cnt> 0 && cnt%512 == 0)
++ {
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("ishighspeed, cnt=%d\n", cnt));
++ // cnt=cnt+1;
++ bwritezero = _TRUE;
++
++ }
++ }
++ else
++ {
++ if(cnt > 0 && cnt%64 == 0)
++ {
++ RT_TRACE(_module_hci_ops_os_c_,_drv_info_,("cnt=%d\n", cnt));
++ // cnt=cnt+1;
++ bwritezero = _TRUE;
++
++ }
++ }
++
++ RT_TRACE( _module_hci_ops_os_c_, _drv_info_, ("usb_write_port: pipe handle convert\n"));
++
++ //translate DMA FIFO addr to pipehandle
++ hPipe = ffaddr2pipehdl(pdvobj_priv, addr);
++
++
++#if 0
++ // for tx fifo, the maximum payload number is 8,
++ // we workaround this issue here by separate whole fifo into 8 segments.
++ if (cnt <= 500)
++ cnt = 500;
++#endif
++
++ RT_TRACE( _module_hci_ops_os_c_, _drv_info_,
++ ("usb_write_port(%u): pxmitframe %X pxmitframe->padapter %X\n",__LINE__, pxmitframe, pxmitframe->padapter));
++
++ pxmitpriv->usb_transfer_write_port = (*usb_funcs_vp->lpIssueBulkTransfer)(
++ hPipe, usb_write_port_complete,
++ pxmitframe, USB_OUT_TRANSFER,
++ cnt, pxmitframe->mem_addr, 0);
++
++ RT_TRACE( _module_hci_ops_os_c_, _drv_info_, ("%s(%u)\n",__FUNCTION__, __LINE__));
++
++ ptr=(u8 *)&pxmitframe->mem;
++
++#if 0
++ if (pdvobj_priv->ishighspeed)
++ {
++ ptr=ptr+512;
++ }
++ else
++ {
++ ptr=ptr+64;
++
++ }
++#endif
++ if(bwritezero == _TRUE)
++ {
++ usb_bulkout_zero(pintfhdl, addr);
++ }
++
++// if (!pxmitframe->usb_transfer_xmit)
++// padapter->bSurpriseRemoved=_TRUE;
++
++ RT_TRACE( _module_hci_ops_os_c_, _drv_info_, ("%s(%u)\n",__FUNCTION__, __LINE__));
++ bResult = _SUCCESS;
++
++exit:
++_func_exit_;
++ return bResult;
++}
++
++DWORD usb_write_port_complete( LPVOID Context )
++{
++
++// u8 *ptr;
++
++ struct xmit_frame * pxmitframe = (struct xmit_frame *) Context;
++ _adapter * padapter = pxmitframe->padapter;
++ struct dvobj_priv * pdvobj_priv = (struct dvobj_priv *)&padapter->dvobjpriv;
++ struct xmit_priv * pxmitpriv = &padapter->xmitpriv;
++ struct xmit_buf *pxmitbuf = pxmitframe->pxmitbuf;
++ LPCUSB_FUNCS usb_funcs_vp = pdvobj_priv->usb_extension._lpUsbFuncs;
++
++ int fComplete =_FALSE;
++ DWORD dwBytesTransferred = 0;
++ DWORD dwErr = USB_CANCELED_ERROR;
++
++ RT_TRACE( _module_hci_ops_os_c_, _drv_info_, ("%s(%u), pxmitframe %X\n",__FUNCTION__, __LINE__, Context));
++
++_func_enter_;
++
++ RT_TRACE(_module_hci_ops_os_c_,_drv_info_,("+usb_write_port_complete\n"));
++
++ _rtw_spinlock_ex(&pxmitpriv->lock);
++ pxmitpriv->txirp_cnt--;
++ _rtw_spinunlock_ex(&pxmitpriv->lock);
++
++ if(pxmitpriv->txirp_cnt==0){
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_write_port_complete: txirp_cnt== 0, set allrxreturnevt!\n"));
++ _rtw_up_sema(&(pxmitpriv->tx_retevt));
++ }
++
++
++ //not to consider tx fragment
++ rtw_free_xmitframe(pxmitpriv, pxmitframe);
++
++
++#if 1
++
++ (*usb_funcs_vp->lpGetTransferStatus)(pxmitpriv->usb_transfer_write_port, &dwBytesTransferred, &dwErr);
++ fComplete = (*usb_funcs_vp->lpIsTransferComplete)(pxmitpriv->usb_transfer_write_port);
++ if(fComplete!=_TRUE)
++ {
++ RT_TRACE( _module_hci_ops_os_c_, _drv_err_, ("usb_write_port_complete CloseTransfer before complete\n"));
++ }
++ (*usb_funcs_vp->lpCloseTransfer)(pxmitpriv->usb_transfer_write_port);
++
++#else
++
++ if((*usb_funcs_vp->lpIsTransferComplete)(pxmitpriv->usb_transfer_write_port))
++ {
++ (*usb_funcs_vp->lpCloseTransfer)(pxmitpriv->usb_transfer_write_port);
++ }
++
++#endif
++
++ RT_TRACE( _module_hci_ops_os_c_, _drv_info_,
++ ("%s(%u): pxmitpriv %X pxmitpriv->free_xmitframe_cnt %X pxmitframe->padapter %X pxmitframe->padapter %X\n",
++ __LINE__, pxmitpriv, pxmitpriv->free_xmitframe_cnt, pxmitframe->padapter));
++
++ rtl8192cu_xmitframe_complete(padapter, pxmitpriv, pxmitbuf);
++
++_func_exit_;
++
++ return STATUS_SUCCESS;
++}
++
++DWORD usb_write_scsi_complete(LPVOID pTxContext)
++{
++#ifndef PLATFORM_OS_CE
++ struct SCSI_BUFFER_ENTRY *psb_entry = (struct SCSI_BUFFER_ENTRY *)pTxContext;
++ _adapter *padapter = psb_entry->padapter;
++ struct SCSI_BUFFER *psb = padapter->pscsi_buf;
++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
++ struct dvobj_priv *pdvobj_priv = (struct dvobj_priv *)&padapter->dvobjpriv;
++ LPCUSB_FUNCS lpUsbFuncs = pdvobj_priv->pUsbExtension->_lpUsbFuncs;
++
++ int fComplete =_FALSE;
++ DWORD dwBytesTransferred = 0;
++ DWORD dwErr = USB_CANCELED_ERROR;
++
++_func_enter_;
++ RT_TRACE( _module_hci_ops_os_c_, _drv_info_, ("%s(%u): circ_space = %d\n",__FUNCTION__, __LINE__, CIRC_SPACE( psb->head,psb->tail, SCSI_BUFFER_NUMBER)));
++
++#if 1
++
++ (*lpUsbFuncs->lpGetTransferStatus)(psb_entry->usb_transfer_scsi_txcmd, &dwBytesTransferred, &dwErr);
++ fComplete = (*lpUsbFuncs->lpIsTransferComplete)(psb_entry->usb_transfer_scsi_txcmd);
++ if(fComplete!=_TRUE)
++ {
++ RT_TRACE( _module_hci_ops_os_c_, _drv_err_, ("usb_write_scsi_complete CloseTransfer before complete\n"));
++ }
++ (*lpUsbFuncs->lpCloseTransfer)(psb_entry->usb_transfer_scsi_txcmd);
++
++#else
++
++ if((*lpUsbFuncs->lpIsTransferComplete)(psb_entry->usb_transfer_scsi_txcmd))
++ (*lpUsbFuncs->lpCloseTransfer)(psb_entry->usb_transfer_scsi_txcmd);
++#endif
++
++ memset(psb_entry->entry_memory, 0, 8);
++
++ RT_TRACE( _module_hci_ops_os_c_, _drv_info_, ("%s(%u)\n",__FUNCTION__, __LINE__));
++ if((psb->tail+1)==SCSI_BUFFER_NUMBER)
++ psb->tail=0;
++ else
++ psb->tail++;
++
++ RT_TRACE( _module_hci_ops_os_c_, _drv_info_, ("%s(%u)\n",__FUNCTION__, __LINE__));
++ if(CIRC_CNT(psb->head,psb->tail,SCSI_BUFFER_NUMBER)==0){
++ RT_TRACE( _module_hci_ops_os_c_, _drv_info_, ("write_txcmd_scsififo_callback: up_sema\n"));
++ _rtw_up_sema(&pxmitpriv->xmit_sema);
++ }
++
++ RT_TRACE( _module_hci_ops_os_c_, _drv_info_, ("%s(%u)\n",__FUNCTION__, __LINE__));
++ if(padapter->bSurpriseRemoved) {
++ return STATUS_MORE_PROCESSING_REQUIRED;
++ }
++
++_func_exit_;
++#endif
++ RT_TRACE( _module_hci_ops_os_c_, _drv_info_, ("%s(%u)\n",__FUNCTION__, __LINE__));
++ return STATUS_MORE_PROCESSING_REQUIRED;
++}
++
++uint usb_write_scsi(struct intf_hdl *pintfhdl, u32 cnt, u8 *wmem)
++{
++
++#ifndef PLATFORM_OS_CE
++
++ _adapter *padapter = (_adapter *)pintfhdl->adapter;
++ struct dvobj_priv *pdev = (struct dvobj_priv*)&padapter->dvobjpriv;
++
++ struct SCSI_BUFFER *psb =padapter->pscsi_buf;
++ struct SCSI_BUFFER_ENTRY *psb_entry=LIST_CONTAINOR(wmem,struct SCSI_BUFFER_ENTRY,entry_memory);
++
++_func_enter_;
++ if(padapter->bSurpriseRemoved||padapter->bDriverStopped)
++ return 0;
++
++ RT_TRACE( _module_hci_ops_os_c_, _drv_info_, ("%s(%u)\n",__FUNCTION__, __LINE__));
++ psb_entry->usb_transfer_scsi_txcmd=pdev->pUsbExtension->_lpUsbFuncs->lpIssueBulkTransfer(
++ pdev->scsi_out_pipehandle,
++ usb_write_scsi_complete,
++ psb_entry,
++ USB_OUT_TRANSFER,
++ cnt,
++ wmem,
++ 0);
++
++_func_exit_;
++#endif
++
++ return _SUCCESS;
++}
++
++
++/*
++ */
++uint usb_init_intf_priv(struct intf_priv *pintfpriv)
++{
++ // get the dvobj_priv object
++ struct dvobj_priv * pNdisCEDvice = (struct dvobj_priv *) pintfpriv->intf_dev;
++
++ RT_TRACE( _module_hci_ops_os_c_, _drv_info_, ("%s(%u)\n",__FUNCTION__, __LINE__));
++ // set init intf_priv init status as _IOREADY
++ pintfpriv->intf_status = _IOREADY;
++
++ // determine the max io size by dvobj_priv.ishighspeed
++ if(pNdisCEDvice->ishighspeed)
++ pintfpriv->max_iosz = 128;
++ else
++ pintfpriv->max_iosz = 64;
++
++ // read/write size set as 0
++ pintfpriv->io_wsz = 0;
++ pintfpriv->io_rsz = 0;
++
++ // init io_rwmem buffer
++ pintfpriv->allocated_io_rwmem = rtw_zmalloc(pintfpriv->max_iosz +4);
++ if (pintfpriv->allocated_io_rwmem == NULL)
++ {
++ rtw_mfree((u8 *)(pintfpriv->allocated_io_rwmem), pintfpriv->max_iosz +4);
++ return _FAIL;
++ }
++ else
++ {
++ // word align the io_rwmem
++ pintfpriv->io_rwmem = pintfpriv->allocated_io_rwmem + 4 - ( (u32)(pintfpriv->allocated_io_rwmem) & 3);
++ }
++
++#ifndef PLATFORM_OS_CE
++
++ // init io_r_mem buffer
++ pintfpriv->allocated_io_r_mem = rtw_zmalloc(pintfpriv->max_iosz +4);
++ if (pintfpriv->allocated_io_r_mem == NULL)
++ {
++ rtw_mfree((u8 *)(pintfpriv->allocated_io_r_mem), pintfpriv->max_iosz +4);
++ return _FAIL;
++ }
++ else
++ {
++ // word align the io_rwmem
++ pintfpriv->io_r_mem = pintfpriv->allocated_io_r_mem + 4 - ( (u32)(pintfpriv->allocated_io_r_mem) & 3);
++ }
++#endif
++
++ return _SUCCESS;
++}
++
++void usb_unload_intf_priv(struct intf_priv *pintfpriv)
++{
++#ifndef PLATFORM_OS_CE
++
++ rtw_mfree((u8 *)(pintfpriv->allocated_io_rwmem), pintfpriv->max_iosz+4);
++ rtw_mfree((u8 *)(pintfpriv->allocated_io_r_mem), pintfpriv->max_iosz+4);
++#endif
++
++ RT_TRACE( _module_hci_ops_os_c_, _drv_info_, ("%s(%u)\n",__FUNCTION__, __LINE__));
++}
++
++
++
++void usb_write_port_cancel(_adapter *padapter)
++{
++
++ sint i,j;
++ struct dvobj_priv *pdev = &padapter->dvobjpriv;
++ struct xmit_priv *pxmitpriv=&padapter->xmitpriv;
++ struct xmit_frame *pxmitframe;
++
++ _rtw_spinlock(&pxmitpriv->lock);
++ pxmitpriv->txirp_cnt--; //decrease 1 for Initialize ++
++ _rtw_spinunlock(&pxmitpriv->lock);
++
++ if (pxmitpriv->txirp_cnt)
++ {
++ // Canceling Pending Recv Irp
++ pxmitframe= (struct xmit_frame *)pxmitpriv->pxmit_frame_buf;
++
++ for( i = 0; i < NR_XMITFRAME; i++ )
++ {
++ for(j=0;j<8;j++)
++ {
++ if (pxmitframe->bpending[j]==_TRUE)
++ {
++
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,(" usb_write_port_cancel() :IoCancelIrp\n"));
++
++ }
++ }
++
++ pxmitframe++;
++ }
++
++ _rtw_down_sema(&(pxmitpriv->tx_retevt));
++
++ }
++
++}
++
++DWORD usbctrl_vendorreq_complete(LPVOID lpvNotifyParameter)
++{
++ struct dvobj_priv *pdvobjpriv = (struct dvobj_priv*)lpvNotifyParameter;
++
++ RT_TRACE(_module_hci_ops_os_c_,_drv_debug_,("+usbctrl_vendorreq_complete\n"));
++
++ return STATUS_SUCCESS;
++}
++
++
++int usbctrl_vendorreq(struct intf_priv *pintfpriv, u8 request, u16 value, u16 index, void *pdata, u16 len, u8 requesttype)
++{
++ u8 ret=_TRUE;
++// NTSTATUS ntstatus;
++// int fComplete;
++// LPCUSB_DEVICE lpDeviceInfo;
++
++ struct dvobj_priv *pdvobjpriv = (struct dvobj_priv *)pintfpriv->intf_dev;
++
++ USB_TRANSFER usbTrans;
++ USB_DEVICE_REQUEST usb_device_req;
++ USB_HANDLE usbHandle = pdvobjpriv->usb_extension._hDevice;
++ LPCUSB_FUNCS usbFuncs = pdvobjpriv->usb_extension._lpUsbFuncs;
++
++ u32 transfer_flags = 0;
++
++ _func_enter_;
++
++ memset( &usb_device_req, 0, sizeof( USB_DEVICE_REQUEST ) );
++
++ if( 0x01 == requesttype )
++ {
++ usb_device_req.bmRequestType = USB_REQUEST_DEVICE_TO_HOST | USB_REQUEST_VENDOR | USB_REQUEST_FOR_DEVICE;
++ }
++ else
++ {
++ usb_device_req.bmRequestType = USB_REQUEST_HOST_TO_DEVICE | USB_REQUEST_VENDOR | USB_REQUEST_FOR_DEVICE;
++ }
++
++ usb_device_req.bRequest = request;
++ usb_device_req.wValue = value;
++ usb_device_req.wIndex = index;
++ usb_device_req.wLength = len;
++
++ if (requesttype == 0x01)
++ {
++ transfer_flags = USB_IN_TRANSFER;//read_in
++ }
++ else
++ {
++ transfer_flags= USB_OUT_TRANSFER;//write_out
++ }
++
++ RT_TRACE(_module_hci_ops_os_c_,_drv_debug_,("+usbctrl_vendorreq\n",__FUNCTION__,__LINE__));
++
++#if 0
++ // Remember to add callback for sync
++ usbTrans = (*usbFuncs->lpIssueVendorTransfer)(usbHandle,
++ usbctrl_vendorreq_complete, pdvobjpriv,
++ transfer_flags, &usb_device_req, pdata, 0);
++#else
++ // Remember to add callback for sync
++ usbTrans = (*usbFuncs->lpIssueVendorTransfer)(usbHandle,
++ NULL, 0,
++ transfer_flags, &usb_device_req, pdata, 0);
++#endif
++
++// rtw_usleep_os(10);
++
++ if ( usbTrans )
++ {
++ DWORD dwBytes = 0;
++ DWORD dwErr = USB_CANCELED_ERROR;
++ int fComplete;
++
++ (*usbFuncs->lpGetTransferStatus)(usbTrans, &dwBytes, &dwErr);
++
++ fComplete = (*usbFuncs->lpIsTransferComplete)(usbTrans);
++
++ if (fComplete== _TRUE)
++ {
++ (*usbFuncs->lpCloseTransfer)(usbTrans);
++ RT_TRACE(_module_hci_ops_os_c_,_drv_debug_,("usbctrl_vendorreq lpCloseTransfer\n"));
++ }
++
++ if ( dwErr != USB_NO_ERROR || fComplete != _TRUE)
++ {
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usbctrl_vendorreq lpCloseTransfer without complete\n"));
++ ret = _FALSE;
++ goto exit;
++ }
++ }
++ else
++ {
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usbctrl_vendorreq without usbTrans\n"));
++ ret = _FALSE;
++ goto exit;
++
++ }
++
++exit:
++ RT_TRACE(_module_hci_ops_os_c_,_drv_debug_,("-usbctrl_vendorreq\n"));
++_func_exit_;
++
++ return ret;
++
++}
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/hal/rtl8192c/usb/usb_ops_linux.c linux-xbian-rpi/drivers/net/wireless/rtl8192cu/hal/rtl8192c/usb/usb_ops_linux.c
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/hal/rtl8192c/usb/usb_ops_linux.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/hal/rtl8192c/usb/usb_ops_linux.c 2015-07-28 01:20:58.313625760 +0200
+@@ -0,0 +1,1535 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#define _HCI_OPS_OS_C_
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++#include <osdep_intf.h>
++#include <usb_ops.h>
++#include <circ_buf.h>
++#include <recv_osdep.h>
++#include <rtl8192c_hal.h>
++
++#if defined (PLATFORM_LINUX) && defined (PLATFORM_WINDOWS)
++
++#error "Shall be Linux or Windows, but not both!\n"
++
++#endif
++
++static int usbctrl_vendorreq(struct intf_hdl *pintfhdl, u8 request, u16 value, u16 index, void *pdata, u16 len, u8 requesttype)
++{
++ _adapter *padapter = pintfhdl->padapter;
++ struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
++ struct usb_device *udev = pdvobjpriv->pusbdev;
++
++ unsigned int pipe;
++ int status = 0;
++ u32 tmp_buflen=0;
++ u8 reqtype;
++ u8 *pIo_buf;
++ int vendorreq_times = 0;
++
++ #ifdef CONFIG_USB_VENDOR_REQ_BUFFER_DYNAMIC_ALLOCATE
++ u8 *tmp_buf;
++ #else // use stack memory
++ u8 tmp_buf[MAX_USB_IO_CTL_SIZE];
++ #endif
++
++#ifdef CONFIG_CONCURRENT_MODE
++ if(padapter->adapter_type > PRIMARY_ADAPTER)
++ {
++ padapter = padapter->pbuddy_adapter;
++ pdvobjpriv = adapter_to_dvobj(padapter);
++ udev = pdvobjpriv->pusbdev;
++ }
++#endif
++
++
++ //DBG_871X("%s %s:%d\n",__FUNCTION__, current->comm, current->pid);
++
++ if((padapter->bSurpriseRemoved) ||(padapter->pwrctrlpriv.pnp_bstop_trx)){
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usbctrl_vendorreq:(padapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx)!!!\n"));
++ status = -EPERM;
++ goto exit;
++ }
++
++ if(len>MAX_VENDOR_REQ_CMD_SIZE){
++ DBG_8192C( "[%s] Buffer len error ,vendor request failed\n", __FUNCTION__ );
++ status = -EINVAL;
++ goto exit;
++ }
++
++ #ifdef CONFIG_USB_VENDOR_REQ_MUTEX
++ _enter_critical_mutex(&pdvobjpriv->usb_vendor_req_mutex, NULL);
++ #endif
++
++
++ // Acquire IO memory for vendorreq
++#ifdef CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC
++ pIo_buf = pdvobjpriv->usb_vendor_req_buf;
++#else
++ #ifdef CONFIG_USB_VENDOR_REQ_BUFFER_DYNAMIC_ALLOCATE
++ tmp_buf = rtw_malloc( (u32) len + ALIGNMENT_UNIT);
++ tmp_buflen = (u32)len + ALIGNMENT_UNIT;
++ #else // use stack memory
++ tmp_buflen = MAX_USB_IO_CTL_SIZE;
++ #endif
++
++ // Added by Albert 2010/02/09
++ // For mstar platform, mstar suggests the address for USB IO should be 16 bytes alignment.
++ // Trying to fix it here.
++ pIo_buf = (tmp_buf==NULL)?NULL:tmp_buf + ALIGNMENT_UNIT -((SIZE_PTR)(tmp_buf) & 0x0f );
++#endif
++
++ if ( pIo_buf== NULL) {
++ DBG_8192C( "[%s] pIo_buf == NULL \n", __FUNCTION__ );
++ status = -ENOMEM;
++ goto release_mutex;
++ }
++
++ while(++vendorreq_times<= MAX_USBCTRL_VENDORREQ_TIMES)
++ {
++ _rtw_memset(pIo_buf, 0, len);
++
++ if (requesttype == 0x01)
++ {
++ pipe = usb_rcvctrlpipe(udev, 0);//read_in
++ reqtype = REALTEK_USB_VENQT_READ;
++ }
++ else
++ {
++ pipe = usb_sndctrlpipe(udev, 0);//write_out
++ reqtype = REALTEK_USB_VENQT_WRITE;
++ _rtw_memcpy( pIo_buf, pdata, len);
++ }
++
++ #if 0
++ //timeout test for firmware downloading
++ status = rtw_usb_control_msg(udev, pipe, request, reqtype, value, index, pIo_buf, len
++ , ((value >= FW_8192C_START_ADDRESS && value <= FW_8192C_END_ADDRESS) ||value!=0x1000) ?RTW_USB_CONTROL_MSG_TIMEOUT : RTW_USB_CONTROL_MSG_TIMEOUT_TEST
++ );
++ #else
++ status = rtw_usb_control_msg(udev, pipe, request, reqtype, value, index, pIo_buf, len, RTW_USB_CONTROL_MSG_TIMEOUT);
++ #endif
++
++ if ( status == len) // Success this control transfer.
++ {
++ rtw_reset_continual_urb_error(pdvobjpriv);
++ if ( requesttype == 0x01 )
++ { // For Control read transfer, we have to copy the read data from pIo_buf to pdata.
++ _rtw_memcpy( pdata, pIo_buf, len );
++ }
++ }
++ else { // error cases
++ DBG_8192C("reg 0x%x, usb %s %u fail, status:%d value=0x%x, vendorreq_times:%d\n"
++ , value,(requesttype == 0x01)?"read":"write" , len, status, *(u32*)pdata, vendorreq_times);
++
++ if (status < 0) {
++ if(status == (-ESHUTDOWN) || status == -ENODEV )
++ {
++ padapter->bSurpriseRemoved = _TRUE;
++ } else {
++ #ifdef DBG_CONFIG_ERROR_DETECT
++ {
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++ pHalData->srestpriv.Wifi_Error_Status = USB_VEN_REQ_CMD_FAIL;
++ }
++ #endif
++ }
++ }
++ else // status != len && status >= 0
++ {
++ if(status > 0) {
++ if ( requesttype == 0x01 )
++ { // For Control read transfer, we have to copy the read data from pIo_buf to pdata.
++ _rtw_memcpy( pdata, pIo_buf, len );
++ }
++ }
++ }
++
++ if(rtw_inc_and_chk_continual_urb_error(pdvobjpriv) == _TRUE ){
++ padapter->bSurpriseRemoved = _TRUE;
++ break;
++ }
++
++ }
++
++ // firmware download is checksumed, don't retry
++ if( (value >= FW_8192C_START_ADDRESS && value <= FW_8192C_END_ADDRESS) || status == len )
++ break;
++
++ }
++
++ // release IO memory used by vendorreq
++ #ifdef CONFIG_USB_VENDOR_REQ_BUFFER_DYNAMIC_ALLOCATE
++ rtw_mfree(tmp_buf, tmp_buflen);
++ #endif
++
++release_mutex:
++ #ifdef CONFIG_USB_VENDOR_REQ_MUTEX
++ _exit_critical_mutex(&pdvobjpriv->usb_vendor_req_mutex, NULL);
++ #endif
++exit:
++ return status;
++
++}
++
++static u8 usb_read8(struct intf_hdl *pintfhdl, u32 addr)
++{
++ u8 request;
++ u8 requesttype;
++ u16 wvalue;
++ u16 index;
++ u16 len;
++ u32 data=0;
++
++ _func_enter_;
++
++ request = 0x05;
++ requesttype = 0x01;//read_in
++ index = 0;//n/a
++
++ wvalue = (u16)(addr&0x0000ffff);
++ len = 1;
++
++ usbctrl_vendorreq(pintfhdl, request, wvalue, index, &data, len, requesttype);
++
++ _func_exit_;
++
++ return (u8)(le32_to_cpu(data)&0x0ff);
++
++}
++
++static u16 usb_read16(struct intf_hdl *pintfhdl, u32 addr)
++{
++ u8 request;
++ u8 requesttype;
++ u16 wvalue;
++ u16 index;
++ u16 len;
++ u32 data=0;
++
++ _func_enter_;
++
++ request = 0x05;
++ requesttype = 0x01;//read_in
++ index = 0;//n/a
++
++ wvalue = (u16)(addr&0x0000ffff);
++ len = 2;
++
++ usbctrl_vendorreq(pintfhdl, request, wvalue, index, &data, len, requesttype);
++
++ _func_exit_;
++
++ return (u16)(le32_to_cpu(data)&0xffff);
++
++}
++
++static u32 usb_read32(struct intf_hdl *pintfhdl, u32 addr)
++{
++ u8 request;
++ u8 requesttype;
++ u16 wvalue;
++ u16 index;
++ u16 len;
++ u32 data=0;
++
++ _func_enter_;
++
++ request = 0x05;
++ requesttype = 0x01;//read_in
++ index = 0;//n/a
++
++ wvalue = (u16)(addr&0x0000ffff);
++ len = 4;
++
++ usbctrl_vendorreq(pintfhdl, request, wvalue, index, &data, len, requesttype);
++
++ _func_exit_;
++
++ return le32_to_cpu(data);
++
++}
++
++static int usb_write8(struct intf_hdl *pintfhdl, u32 addr, u8 val)
++{
++ u8 request;
++ u8 requesttype;
++ u16 wvalue;
++ u16 index;
++ u16 len;
++ u32 data;
++ int ret;
++
++ _func_enter_;
++
++ request = 0x05;
++ requesttype = 0x00;//write_out
++ index = 0;//n/a
++
++ wvalue = (u16)(addr&0x0000ffff);
++ len = 1;
++
++ data = val;
++ data = cpu_to_le32(data&0x000000ff);
++
++ ret = usbctrl_vendorreq(pintfhdl, request, wvalue, index, &data, len, requesttype);
++
++ _func_exit_;
++
++ return ret;
++
++}
++
++static int usb_write16(struct intf_hdl *pintfhdl, u32 addr, u16 val)
++{
++ u8 request;
++ u8 requesttype;
++ u16 wvalue;
++ u16 index;
++ u16 len;
++ u32 data;
++ int ret;
++
++ _func_enter_;
++
++ request = 0x05;
++ requesttype = 0x00;//write_out
++ index = 0;//n/a
++
++ wvalue = (u16)(addr&0x0000ffff);
++ len = 2;
++
++ data = val;
++ data = cpu_to_le32(data&0x0000ffff);
++
++ ret = usbctrl_vendorreq(pintfhdl, request, wvalue, index, &data, len, requesttype);
++
++ _func_exit_;
++
++ return ret;
++
++}
++
++static int usb_write32(struct intf_hdl *pintfhdl, u32 addr, u32 val)
++{
++ u8 request;
++ u8 requesttype;
++ u16 wvalue;
++ u16 index;
++ u16 len;
++ u32 data;
++ int ret;
++
++ _func_enter_;
++
++ request = 0x05;
++ requesttype = 0x00;//write_out
++ index = 0;//n/a
++
++ wvalue = (u16)(addr&0x0000ffff);
++ len = 4;
++ data = cpu_to_le32(val);
++
++
++ ret =usbctrl_vendorreq(pintfhdl, request, wvalue, index, &data, len, requesttype);
++
++ _func_exit_;
++
++ return ret;
++
++}
++
++static int usb_writeN(struct intf_hdl *pintfhdl, u32 addr, u32 length, u8 *pdata)
++{
++ u8 request;
++ u8 requesttype;
++ u16 wvalue;
++ u16 index;
++ u16 len;
++ u8 buf[VENDOR_CMD_MAX_DATA_LEN]={0};
++ int ret;
++
++ _func_enter_;
++
++ request = 0x05;
++ requesttype = 0x00;//write_out
++ index = 0;//n/a
++
++ wvalue = (u16)(addr&0x0000ffff);
++ len = length;
++ _rtw_memcpy(buf, pdata, len );
++
++ ret = usbctrl_vendorreq(pintfhdl, request, wvalue, index, buf, len, requesttype);
++
++ _func_exit_;
++
++ return ret;
++
++}
++
++#ifdef CONFIG_USB_INTERRUPT_IN_PIPE
++static void usb_read_interrupt_complete(struct urb *purb, struct pt_regs *regs)
++{
++ int err;
++ _adapter *padapter = (_adapter *)purb->context;
++
++ if(purb->status==0)//SUCCESS
++ {
++ if (purb->actual_length > sizeof(INTERRUPT_MSG_FORMAT_EX))
++ {
++ DBG_8192C("usb_read_interrupt_complete: purb->actual_length > sizeof(INTERRUPT_MSG_FORMAT_EX) \n");
++ }
++
++ err = usb_submit_urb(purb, GFP_ATOMIC);
++ if((err) && (err != (-EPERM)))
++ {
++ DBG_8192C("cannot submit interrupt in-token(err = 0x%08x),urb_status = %d\n",err, purb->status);
++ }
++ }
++ else
++ {
++ DBG_8192C("###=> usb_read_interrupt_complete => urb status(%d)\n", purb->status);
++
++ switch(purb->status) {
++ case -EINVAL:
++ case -EPIPE:
++ case -ENODEV:
++ case -ESHUTDOWN:
++ //padapter->bSurpriseRemoved=_TRUE;
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete:bSurpriseRemoved=TRUE\n"));
++ case -ENOENT:
++ padapter->bDriverStopped=_TRUE;
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete:bDriverStopped=TRUE\n"));
++ break;
++ case -EPROTO:
++ break;
++ case -EINPROGRESS:
++ DBG_8192C("ERROR: URB IS IN PROGRESS!/n");
++ break;
++ default:
++ break;
++ }
++ }
++
++}
++
++static u32 usb_read_interrupt(struct intf_hdl *pintfhdl, u32 addr)
++{
++ int err;
++ unsigned int pipe;
++ u32 ret = _SUCCESS;
++ _adapter *adapter = pintfhdl->padapter;
++ struct dvobj_priv *pdvobj = adapter_to_dvobj(adapter);
++ struct recv_priv *precvpriv = &adapter->recvpriv;
++ struct usb_device *pusbd = pdvobj->pusbdev;
++
++_func_enter_;
++
++ //translate DMA FIFO addr to pipehandle
++ pipe = ffaddr2pipehdl(pdvobj, addr);
++
++ usb_fill_int_urb(precvpriv->int_in_urb, pusbd, pipe,
++ precvpriv->int_in_buf,
++ sizeof(INTERRUPT_MSG_FORMAT_EX),
++ usb_read_interrupt_complete,
++ adapter,
++ 1);
++
++ err = usb_submit_urb(precvpriv->int_in_urb, GFP_ATOMIC);
++ if((err) && (err != (-EPERM)))
++ {
++ DBG_8192C("cannot submit interrupt in-token(err = 0x%08x),urb_status = %d\n",err, precvpriv->int_in_urb->status);
++ ret = _FAIL;
++ }
++
++_func_exit_;
++
++ return ret;
++}
++#endif
++
++static s32 pre_recv_entry(union recv_frame *precvframe, struct recv_stat *prxstat, struct phy_stat *pphy_info)
++{
++ s32 ret=_SUCCESS;
++#ifdef CONFIG_CONCURRENT_MODE
++ u8 *primary_myid, *secondary_myid, *paddr1;
++ union recv_frame *precvframe_if2 = NULL;
++ _adapter *primary_padapter = precvframe->u.hdr.adapter;
++ _adapter *secondary_padapter = primary_padapter->pbuddy_adapter;
++ struct recv_priv *precvpriv = &primary_padapter->recvpriv;
++ _queue *pfree_recv_queue = &precvpriv->free_recv_queue;
++ u8 *pbuf = precvframe->u.hdr.rx_data;
++
++ if(!secondary_padapter)
++ return ret;
++
++ paddr1 = GetAddr1Ptr(precvframe->u.hdr.rx_data);
++
++ if(IS_MCAST(paddr1) == _FALSE)//unicast packets
++ {
++ //primary_myid = myid(&primary_padapter->eeprompriv);
++ secondary_myid = myid(&secondary_padapter->eeprompriv);
++
++ if(_rtw_memcmp(paddr1, secondary_myid, ETH_ALEN))
++ {
++ //change to secondary interface
++ precvframe->u.hdr.adapter = secondary_padapter;
++ }
++
++ //ret = recv_entry(precvframe);
++
++ }
++ else // Handle BC/MC Packets
++ {
++
++ u8 clone = _TRUE;
++#if 0
++ u8 type, subtype, *paddr2, *paddr3;
++
++ type = GetFrameType(pbuf);
++ subtype = GetFrameSubType(pbuf); //bit(7)~bit(2)
++
++ switch (type)
++ {
++ case WIFI_MGT_TYPE: //Handle BC/MC mgnt Packets
++ if(subtype == WIFI_BEACON)
++ {
++ paddr3 = GetAddr3Ptr(precvframe->u.hdr.rx_data);
++
++ if (check_fwstate(&secondary_padapter->mlmepriv, _FW_LINKED) &&
++ _rtw_memcmp(paddr3, get_bssid(&secondary_padapter->mlmepriv), ETH_ALEN))
++ {
++ //change to secondary interface
++ precvframe->u.hdr.adapter = secondary_padapter;
++ clone = _FALSE;
++ }
++
++ if(check_fwstate(&primary_padapter->mlmepriv, _FW_LINKED) &&
++ _rtw_memcmp(paddr3, get_bssid(&primary_padapter->mlmepriv), ETH_ALEN))
++ {
++ if(clone==_FALSE)
++ {
++ clone = _TRUE;
++ }
++ else
++ {
++ clone = _FALSE;
++ }
++
++ precvframe->u.hdr.adapter = primary_padapter;
++ }
++
++ if(check_fwstate(&primary_padapter->mlmepriv, _FW_UNDER_SURVEY|_FW_UNDER_LINKING) ||
++ check_fwstate(&secondary_padapter->mlmepriv, _FW_UNDER_SURVEY|_FW_UNDER_LINKING))
++ {
++ clone = _TRUE;
++ precvframe->u.hdr.adapter = primary_padapter;
++ }
++
++ }
++ else if(subtype == WIFI_PROBEREQ)
++ {
++ //probe req frame is only for interface2
++ //change to secondary interface
++ precvframe->u.hdr.adapter = secondary_padapter;
++ clone = _FALSE;
++ }
++ break;
++ case WIFI_CTRL_TYPE: // Handle BC/MC ctrl Packets
++
++ break;
++ case WIFI_DATA_TYPE: //Handle BC/MC data Packets
++ //Notes: AP MODE never rx BC/MC data packets
++
++ paddr2 = GetAddr2Ptr(precvframe->u.hdr.rx_data);
++
++ if(_rtw_memcmp(paddr2, get_bssid(&secondary_padapter->mlmepriv), ETH_ALEN))
++ {
++ //change to secondary interface
++ precvframe->u.hdr.adapter = secondary_padapter;
++ clone = _FALSE;
++ }
++
++ break;
++ default:
++
++ break;
++ }
++#endif
++
++ if(_TRUE == clone)
++ {
++ //clone/copy to if2
++ u8 shift_sz = 0;
++ u32 alloc_sz, skb_len;
++ _pkt *pkt_copy = NULL;
++ struct rx_pkt_attrib *pattrib = NULL;
++
++ precvframe_if2 = rtw_alloc_recvframe(pfree_recv_queue);
++ if(precvframe_if2)
++ {
++ precvframe_if2->u.hdr.adapter = secondary_padapter;
++
++ _rtw_init_listhead(&precvframe_if2->u.hdr.list);
++ precvframe_if2->u.hdr.precvbuf = NULL; //can't access the precvbuf for new arch.
++ precvframe_if2->u.hdr.len=0;
++
++ _rtw_memcpy(&precvframe_if2->u.hdr.attrib, &precvframe->u.hdr.attrib, sizeof(struct rx_pkt_attrib));
++
++ pattrib = &precvframe_if2->u.hdr.attrib;
++
++ // Modified by Albert 20101213
++ // For 8 bytes IP header alignment.
++ if (pattrib->qos) // Qos data, wireless lan header length is 26
++ {
++ shift_sz = 6;
++ }
++ else
++ {
++ shift_sz = 0;
++ }
++
++ skb_len = pattrib->pkt_len;
++
++ // for first fragment packet, driver need allocate 1536+drvinfo_sz+RXDESC_SIZE to defrag packet.
++ // modify alloc_sz for recvive crc error packet by thomas 2011-06-02
++ if((pattrib->mfrag == 1)&&(pattrib->frag_num == 0)){
++ //alloc_sz = 1664; //1664 is 128 alignment.
++ if(skb_len <= 1650)
++ alloc_sz = 1664;
++ else
++ alloc_sz = skb_len + 14;
++ }
++ else {
++ alloc_sz = skb_len;
++ // 6 is for IP header 8 bytes alignment in QoS packet case.
++ // 8 is for skb->data 4 bytes alignment.
++ alloc_sz += 14;
++ }
++
++ pkt_copy = rtw_skb_alloc(alloc_sz);
++
++ if(pkt_copy)
++ {
++ pkt_copy->dev = secondary_padapter->pnetdev;
++ precvframe_if2->u.hdr.pkt = pkt_copy;
++ precvframe_if2->u.hdr.rx_head = pkt_copy->data;
++ precvframe_if2->u.hdr.rx_end = pkt_copy->data + alloc_sz;
++ skb_reserve( pkt_copy, 8 - ((SIZE_PTR)( pkt_copy->data ) & 7 ));//force pkt_copy->data at 8-byte alignment address
++ skb_reserve( pkt_copy, shift_sz );//force ip_hdr at 8-byte alignment address according to shift_sz.
++ _rtw_memcpy(pkt_copy->data, pbuf, skb_len);
++ precvframe_if2->u.hdr.rx_data = precvframe_if2->u.hdr.rx_tail = pkt_copy->data;
++
++
++ recvframe_put(precvframe_if2, skb_len);
++ //recvframe_pull(precvframe_if2, drvinfo_sz + RXDESC_SIZE);
++
++ rtl8192c_translate_rx_signal_stuff(precvframe_if2, pphy_info);
++
++ ret = rtw_recv_entry(precvframe_if2);
++
++ } else {
++ rtw_free_recvframe(precvframe_if2, pfree_recv_queue);
++ DBG_8192C("%s()-%d: alloc_skb() failed!\n", __FUNCTION__, __LINE__);
++ }
++
++ }
++
++ }
++
++ }
++
++ rtl8192c_translate_rx_signal_stuff(precvframe, pphy_info);
++
++ ret = rtw_recv_entry(precvframe);
++
++#endif
++
++ return ret;
++
++}
++
++#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX
++static int recvbuf2recvframe(_adapter *padapter, struct recv_buf *precvbuf)
++{
++ u8 *pbuf;
++ u8 shift_sz = 0;
++ u16 pkt_cnt, drvinfo_sz;
++ u32 pkt_offset, skb_len, alloc_sz;
++ s32 transfer_len;
++ struct recv_stat *prxstat;
++ struct phy_stat *pphy_info = NULL;
++ _pkt *pkt_copy = NULL;
++ union recv_frame *precvframe = NULL;
++ struct rx_pkt_attrib *pattrib = NULL;
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++ struct recv_priv *precvpriv = &padapter->recvpriv;
++ _queue *pfree_recv_queue = &precvpriv->free_recv_queue;
++
++
++ transfer_len = (s32)precvbuf->transfer_len;
++ pbuf = precvbuf->pbuf;
++
++ prxstat = (struct recv_stat *)pbuf;
++ pkt_cnt = (le32_to_cpu(prxstat->rxdw2)>>16) & 0xff;
++
++#if 0 //temp remove when disable usb rx aggregation
++ if((pkt_cnt > 10) || (pkt_cnt < 1) || (transfer_len<RXDESC_SIZE) ||(pkt_len<=0))
++ {
++ return _FAIL;
++ }
++#endif
++
++ do{
++ RT_TRACE(_module_rtl871x_recv_c_, _drv_info_,
++ ("recvbuf2recvframe: rxdesc=offsset 0:0x%08x, 4:0x%08x, 8:0x%08x, C:0x%08x\n",
++ prxstat->rxdw0, prxstat->rxdw1, prxstat->rxdw2, prxstat->rxdw4));
++
++ prxstat = (struct recv_stat *)pbuf;
++
++ precvframe = rtw_alloc_recvframe(pfree_recv_queue);
++ if(precvframe==NULL)
++ {
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("recvbuf2recvframe: precvframe==NULL\n"));
++ DBG_8192C("%s()-%d: rtw_alloc_recvframe() failed! RX Drop!\n", __FUNCTION__, __LINE__);
++ goto _exit_recvbuf2recvframe;
++ }
++
++ _rtw_init_listhead(&precvframe->u.hdr.list);
++ precvframe->u.hdr.precvbuf = NULL; //can't access the precvbuf for new arch.
++ precvframe->u.hdr.len=0;
++
++ rtl8192c_query_rx_desc_status(precvframe, prxstat);
++
++ pattrib = &precvframe->u.hdr.attrib;
++ if(pattrib->physt)
++ {
++ pphy_info = (struct phy_stat *)(pbuf + RXDESC_OFFSET);
++ }
++
++ pkt_offset = RXDESC_SIZE + pattrib->drvinfo_sz + pattrib->shift_sz + pattrib->pkt_len;
++
++ if((pattrib->pkt_len<=0) || (pkt_offset>transfer_len))
++ {
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("recvbuf2recvframe: pkt_len<=0\n"));
++ DBG_8192C("%s()-%d: RX Warning!\n", __FUNCTION__, __LINE__);
++ rtw_free_recvframe(precvframe, pfree_recv_queue);
++ goto _exit_recvbuf2recvframe;
++ }
++
++ // Modified by Albert 20101213
++ // For 8 bytes IP header alignment.
++ if (pattrib->qos) // Qos data, wireless lan header length is 26
++ {
++ shift_sz = 6;
++ }
++ else
++ {
++ shift_sz = 0;
++ }
++
++ skb_len = pattrib->pkt_len;
++
++ // for first fragment packet, driver need allocate 1536+drvinfo_sz+RXDESC_SIZE to defrag packet.
++ // modify alloc_sz for recvive crc error packet by thomas 2011-06-02
++ if((pattrib->mfrag == 1)&&(pattrib->frag_num == 0)){
++ //alloc_sz = 1664; //1664 is 128 alignment.
++ if(skb_len <= 1650)
++ alloc_sz = 1664;
++ else
++ alloc_sz = skb_len + 14;
++ }
++ else {
++ alloc_sz = skb_len;
++ // 6 is for IP header 8 bytes alignment in QoS packet case.
++ // 8 is for skb->data 4 bytes alignment.
++ alloc_sz += 14;
++ }
++
++ pkt_copy = rtw_skb_alloc(alloc_sz);
++
++ if(pkt_copy)
++ {
++ pkt_copy->dev = padapter->pnetdev;
++ precvframe->u.hdr.pkt = pkt_copy;
++ precvframe->u.hdr.rx_head = pkt_copy->data;
++ precvframe->u.hdr.rx_end = pkt_copy->data + alloc_sz;
++ skb_reserve( pkt_copy, 8 - ((SIZE_PTR)( pkt_copy->data ) & 7 ));//force pkt_copy->data at 8-byte alignment address
++ skb_reserve( pkt_copy, shift_sz );//force ip_hdr at 8-byte alignment address according to shift_sz.
++ _rtw_memcpy(pkt_copy->data, (pbuf + pattrib->shift_sz + pattrib->drvinfo_sz + RXDESC_SIZE), skb_len);
++ precvframe->u.hdr.rx_data = precvframe->u.hdr.rx_tail = pkt_copy->data;
++ }
++ else
++ {
++ DBG_8192C("recvbuf2recvframe:can not allocate memory for skb copy\n");
++ //precvframe->u.hdr.pkt = rtw_skb_clone(pskb);
++ //precvframe->u.hdr.rx_head = precvframe->u.hdr.rx_data = precvframe->u.hdr.rx_tail = pbuf;
++ //precvframe->u.hdr.rx_end = pbuf + (pkt_offset>1612?pkt_offset:1612);
++
++ precvframe->u.hdr.pkt = NULL;
++ rtw_free_recvframe(precvframe, pfree_recv_queue);
++
++ goto _exit_recvbuf2recvframe;
++ }
++
++ recvframe_put(precvframe, skb_len);
++ //recvframe_pull(precvframe, drvinfo_sz + RXDESC_SIZE);
++
++#ifdef CONFIG_USB_RX_AGGREGATION
++ switch(pHalData->UsbRxAggMode)
++ {
++ case USB_RX_AGG_DMA:
++ case USB_RX_AGG_MIX:
++ pkt_offset = (u16)_RND128(pkt_offset);
++ break;
++ case USB_RX_AGG_USB:
++ pkt_offset = (u16)_RND4(pkt_offset);
++ break;
++ case USB_RX_AGG_DISABLE:
++ default:
++ break;
++ }
++#endif
++
++#ifdef CONFIG_CONCURRENT_MODE
++ if(rtw_buddy_adapter_up(padapter))
++ {
++ if(pre_recv_entry(precvframe, prxstat, pphy_info) != _SUCCESS)
++ {
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("recvbuf2recvframe: recv_entry(precvframe) != _SUCCESS\n"));
++ }
++ }
++ else
++ {
++ rtl8192c_translate_rx_signal_stuff(precvframe, pphy_info);
++ if(rtw_recv_entry(precvframe) != _SUCCESS)
++ {
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("recvbuf2recvframe: rtw_recv_entry(precvframe) != _SUCCESS\n"));
++ }
++ }
++
++#else
++ rtl8192c_translate_rx_signal_stuff(precvframe, pphy_info);
++ if(rtw_recv_entry(precvframe) != _SUCCESS)
++ {
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("recvbuf2recvframe: rtw_recv_entry(precvframe) != _SUCCESS\n"));
++ }
++#endif
++
++ pkt_cnt--;
++ transfer_len -= pkt_offset;
++ pbuf += pkt_offset;
++ precvframe = NULL;
++ pkt_copy = NULL;
++
++ if(transfer_len>0 && pkt_cnt==0)
++ pkt_cnt = (le32_to_cpu(prxstat->rxdw2)>>16) & 0xff;
++
++ }while((transfer_len>0) && (pkt_cnt>0));
++
++_exit_recvbuf2recvframe:
++
++ return _SUCCESS;
++}
++
++void rtl8192cu_recv_tasklet(void *priv)
++{
++ struct recv_buf *precvbuf = NULL;
++ _adapter *padapter = (_adapter*)priv;
++ struct recv_priv *precvpriv = &padapter->recvpriv;
++
++ while (NULL != (precvbuf = rtw_dequeue_recvbuf(&precvpriv->recv_buf_pending_queue)))
++ {
++ if ((padapter->bDriverStopped == _TRUE)||(padapter->bSurpriseRemoved== _TRUE))
++ {
++ DBG_8192C("recv_tasklet => bDriverStopped or bSurpriseRemoved \n");
++
++ break;
++ }
++
++
++ recvbuf2recvframe(padapter, precvbuf);
++
++ rtw_read_port(padapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf);
++ }
++
++}
++
++static void usb_read_port_complete(struct urb *purb, struct pt_regs *regs)
++{
++ struct recv_buf *precvbuf = (struct recv_buf *)purb->context;
++ _adapter *padapter =(_adapter *)precvbuf->adapter;
++ struct recv_priv *precvpriv = &padapter->recvpriv;
++
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete!!!\n"));
++
++ precvpriv->rx_pending_cnt --;
++
++ if(padapter->bSurpriseRemoved || padapter->bDriverStopped||padapter->bReadPortCancel)
++ {
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete:bDriverStopped(%d) OR bSurpriseRemoved(%d)\n", padapter->bDriverStopped, padapter->bSurpriseRemoved));
++
++ goto exit;
++ }
++
++ if(purb->status==0)//SUCCESS
++ {
++ if ((purb->actual_length > MAX_RECVBUF_SZ) || (purb->actual_length < RXDESC_SIZE))
++ {
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete: (purb->actual_length > MAX_RECVBUF_SZ) || (purb->actual_length < RXDESC_SIZE)\n"));
++
++ rtw_read_port(padapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf);
++ }
++ else
++ {
++ rtw_reset_continual_urb_error(adapter_to_dvobj(padapter));
++
++ precvbuf->transfer_len = purb->actual_length;
++
++ //rtw_enqueue_rx_transfer_buffer(precvpriv, rx_transfer_buf);
++ rtw_enqueue_recvbuf(precvbuf, &precvpriv->recv_buf_pending_queue);
++
++ tasklet_schedule(&precvpriv->recv_tasklet);
++ }
++ }
++ else
++ {
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete : purb->status(%d) != 0 \n", purb->status));
++
++ DBG_8192C("###=> usb_read_port_complete => urb status(%d)\n", purb->status);
++
++ if(rtw_inc_and_chk_continual_urb_error(adapter_to_dvobj(padapter)) == _TRUE ){
++ padapter->bSurpriseRemoved = _TRUE;
++ }
++
++ switch(purb->status) {
++ case -EINVAL:
++ case -EPIPE:
++ case -ENODEV:
++ case -ESHUTDOWN:
++ //padapter->bSurpriseRemoved=_TRUE;
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete:bSurpriseRemoved=TRUE\n"));
++ case -ENOENT:
++ padapter->bDriverStopped=_TRUE;
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete:bDriverStopped=TRUE\n"));
++ break;
++ case -EPROTO:
++ case -EILSEQ:
++ case -ETIME:
++ case -ECOMM:
++ case -EOVERFLOW:
++ #ifdef DBG_CONFIG_ERROR_DETECT
++ {
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++ pHalData->srestpriv.Wifi_Error_Status = USB_READ_PORT_FAIL;
++ }
++ #endif
++ rtw_read_port(padapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf);
++ break;
++ case -EINPROGRESS:
++ DBG_8192C("ERROR: URB IS IN PROGRESS!/n");
++ break;
++ default:
++ break;
++ }
++
++ }
++
++exit:
++
++_func_exit_;
++
++}
++
++static u32 usb_read_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem)
++{
++ int err;
++ unsigned int pipe;
++ u32 ret = _SUCCESS;
++ PURB purb = NULL;
++ struct recv_buf *precvbuf = (struct recv_buf *)rmem;
++ _adapter *adapter = pintfhdl->padapter;
++ struct dvobj_priv *pdvobj = adapter_to_dvobj(adapter);
++ struct recv_priv *precvpriv = &adapter->recvpriv;
++ struct usb_device *pusbd = pdvobj->pusbdev;
++
++_func_enter_;
++
++ if(adapter->bDriverStopped || adapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx)
++ {
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port:( padapter->bDriverStopped ||padapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx)!!!\n"));
++ return _FAIL;
++ }
++
++ if(precvbuf !=NULL)
++ {
++ rtl8192cu_init_recvbuf(adapter, precvbuf);
++
++ if(precvbuf->pbuf)
++ {
++ precvpriv->rx_pending_cnt++;
++
++ purb = precvbuf->purb;
++
++ //translate DMA FIFO addr to pipehandle
++ pipe = ffaddr2pipehdl(pdvobj, addr);
++
++ usb_fill_bulk_urb(purb, pusbd, pipe,
++ precvbuf->pbuf,
++ MAX_RECVBUF_SZ,
++ usb_read_port_complete,
++ precvbuf);//context is precvbuf
++
++ purb->transfer_dma = precvbuf->dma_transfer_addr;
++ purb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP;
++
++ err = usb_submit_urb(purb, GFP_ATOMIC);
++ if((err) && (err != (-EPERM)))
++ {
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("cannot submit rx in-token(err=0x%.8x), URB_STATUS =0x%.8x", err, purb->status));
++ DBG_8192C("cannot submit rx in-token(err = 0x%08x),urb_status = %d\n",err,purb->status);
++ ret = _FAIL;
++ }
++
++ }
++
++ }
++ else
++ {
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port:precvbuf ==NULL\n"));
++ ret = _FAIL;
++ }
++
++_func_exit_;
++
++ return ret;
++}
++#else // CONFIG_USE_USB_BUFFER_ALLOC_RX
++static int recvbuf2recvframe(_adapter *padapter, _pkt *pskb)
++{
++ u8 *pbuf;
++ u8 shift_sz = 0;
++ u16 pkt_cnt;
++ u32 pkt_offset, skb_len, alloc_sz;
++ s32 transfer_len;
++ struct recv_stat *prxstat;
++ struct phy_stat *pphy_info = NULL;
++ _pkt *pkt_copy = NULL;
++ union recv_frame *precvframe = NULL;
++ struct rx_pkt_attrib *pattrib = NULL;
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++ struct recv_priv *precvpriv = &padapter->recvpriv;
++ _queue *pfree_recv_queue = &precvpriv->free_recv_queue;
++
++
++ transfer_len = (s32)pskb->len;
++ pbuf = pskb->data;
++
++ prxstat = (struct recv_stat *)pbuf;
++ pkt_cnt = (le32_to_cpu(prxstat->rxdw2)>>16) & 0xff;
++
++#if 0 //temp remove when disable usb rx aggregation
++ if((pkt_cnt > 10) || (pkt_cnt < 1) || (transfer_len<RXDESC_SIZE) ||(pkt_len<=0))
++ {
++ return _FAIL;
++ }
++#endif
++
++ do{
++ RT_TRACE(_module_rtl871x_recv_c_, _drv_info_,
++ ("recvbuf2recvframe: rxdesc=offsset 0:0x%08x, 4:0x%08x, 8:0x%08x, C:0x%08x\n",
++ prxstat->rxdw0, prxstat->rxdw1, prxstat->rxdw2, prxstat->rxdw4));
++
++ prxstat = (struct recv_stat *)pbuf;
++
++ precvframe = rtw_alloc_recvframe(pfree_recv_queue);
++ if(precvframe==NULL)
++ {
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("recvbuf2recvframe: precvframe==NULL\n"));
++ DBG_8192C("%s()-%d: rtw_alloc_recvframe() failed! RX Drop!\n", __FUNCTION__, __LINE__);
++ goto _exit_recvbuf2recvframe;
++ }
++
++ _rtw_init_listhead(&precvframe->u.hdr.list);
++ precvframe->u.hdr.precvbuf = NULL; //can't access the precvbuf for new arch.
++ precvframe->u.hdr.len=0;
++
++ rtl8192c_query_rx_desc_status(precvframe, prxstat);
++
++ pattrib = &precvframe->u.hdr.attrib;
++ if(pattrib->physt)
++ {
++ pphy_info = (struct phy_stat *)(pbuf + RXDESC_OFFSET);
++ }
++
++ pkt_offset = RXDESC_SIZE + pattrib->drvinfo_sz + pattrib->shift_sz + pattrib->pkt_len;
++
++ if((pattrib->pkt_len<=0) || (pkt_offset>transfer_len))
++ {
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("recvbuf2recvframe: pkt_len<=0\n"));
++ DBG_8192C("%s()-%d: RX Warning!\n", __FUNCTION__, __LINE__);
++ rtw_free_recvframe(precvframe, pfree_recv_queue);
++ goto _exit_recvbuf2recvframe;
++ }
++
++ // Modified by Albert 20101213
++ // For 8 bytes IP header alignment.
++ if (pattrib->qos) // Qos data, wireless lan header length is 26
++ {
++ shift_sz = 6;
++ }
++ else
++ {
++ shift_sz = 0;
++ }
++
++ skb_len = pattrib->pkt_len;
++
++ // for first fragment packet, driver need allocate 1536+drvinfo_sz+RXDESC_SIZE to defrag packet.
++ // modify alloc_sz for recvive crc error packet by thomas 2011-06-02
++ if((pattrib->mfrag == 1)&&(pattrib->frag_num == 0)){
++ //alloc_sz = 1664; //1664 is 128 alignment.
++ if(skb_len <= 1650)
++ alloc_sz = 1664;
++ else
++ alloc_sz = skb_len + 14;
++ }
++ else {
++ alloc_sz = skb_len;
++ // 6 is for IP header 8 bytes alignment in QoS packet case.
++ // 8 is for skb->data 4 bytes alignment.
++ alloc_sz += 14;
++ }
++
++ pkt_copy = rtw_skb_alloc(alloc_sz);
++
++ if(pkt_copy)
++ {
++ pkt_copy->dev = padapter->pnetdev;
++ precvframe->u.hdr.pkt = pkt_copy;
++ precvframe->u.hdr.rx_head = pkt_copy->data;
++ precvframe->u.hdr.rx_end = pkt_copy->data + alloc_sz;
++ skb_reserve( pkt_copy, 8 - ((SIZE_PTR)( pkt_copy->data ) & 7 ));//force pkt_copy->data at 8-byte alignment address
++ skb_reserve( pkt_copy, shift_sz );//force ip_hdr at 8-byte alignment address according to shift_sz.
++ _rtw_memcpy(pkt_copy->data, (pbuf + pattrib->shift_sz + pattrib->drvinfo_sz + RXDESC_SIZE), skb_len);
++ precvframe->u.hdr.rx_data = precvframe->u.hdr.rx_tail = pkt_copy->data;
++
++ }
++ else
++ {
++ precvframe->u.hdr.pkt = rtw_skb_clone(pskb);
++ if(pkt_copy)
++ {
++ precvframe->u.hdr.rx_head = precvframe->u.hdr.rx_data = precvframe->u.hdr.rx_tail = pbuf;
++ precvframe->u.hdr.rx_end = pbuf + alloc_sz;
++ }
++ else
++ {
++ DBG_8192C("recvbuf2recvframe: rtw_skb_clone fail\n");
++ rtw_free_recvframe(precvframe, pfree_recv_queue);
++ goto _exit_recvbuf2recvframe;
++ }
++ }
++
++ recvframe_put(precvframe, skb_len);
++ //recvframe_pull(precvframe, drvinfo_sz + RXDESC_SIZE);
++
++#ifdef CONFIG_USB_RX_AGGREGATION
++ switch(pHalData->UsbRxAggMode)
++ {
++ case USB_RX_AGG_DMA:
++ case USB_RX_AGG_MIX:
++ pkt_offset = (u16)_RND128(pkt_offset);
++ break;
++ case USB_RX_AGG_USB:
++ pkt_offset = (u16)_RND4(pkt_offset);
++ break;
++ case USB_RX_AGG_DISABLE:
++ default:
++ break;
++ }
++#endif
++
++#ifdef CONFIG_CONCURRENT_MODE
++ if(rtw_buddy_adapter_up(padapter))
++ {
++ if(pre_recv_entry(precvframe, prxstat, pphy_info) != _SUCCESS)
++ {
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("recvbuf2recvframe: recv_entry(precvframe) != _SUCCESS\n"));
++ }
++ }
++ else
++ {
++ rtl8192c_translate_rx_signal_stuff(precvframe, pphy_info);
++ if(rtw_recv_entry(precvframe) != _SUCCESS)
++ {
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("recvbuf2recvframe: rtw_recv_entry(precvframe) != _SUCCESS\n"));
++ }
++ }
++
++#else
++ rtl8192c_translate_rx_signal_stuff(precvframe, pphy_info);
++ if(rtw_recv_entry(precvframe) != _SUCCESS)
++ {
++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("recvbuf2recvframe: rtw_recv_entry(precvframe) != _SUCCESS\n"));
++ }
++#endif
++
++ pkt_cnt--;
++ transfer_len -= pkt_offset;
++ pbuf += pkt_offset;
++ precvframe = NULL;
++ pkt_copy = NULL;
++
++ if(transfer_len>0 && pkt_cnt==0)
++ pkt_cnt = (le32_to_cpu(prxstat->rxdw2)>>16) & 0xff;
++
++ }while((transfer_len>0) && (pkt_cnt>0));
++
++_exit_recvbuf2recvframe:
++
++ return _SUCCESS;
++}
++
++void rtl8192cu_recv_tasklet(void *priv)
++{
++ _pkt *pskb;
++ _adapter *padapter = (_adapter*)priv;
++ struct recv_priv *precvpriv = &padapter->recvpriv;
++
++ while (NULL != (pskb = skb_dequeue(&precvpriv->rx_skb_queue)))
++ {
++ if ((padapter->bDriverStopped == _TRUE)||(padapter->bSurpriseRemoved== _TRUE))
++ {
++ DBG_8192C("recv_tasklet => bDriverStopped or bSurpriseRemoved \n");
++ rtw_skb_free(pskb);
++ break;
++ }
++
++ recvbuf2recvframe(padapter, pskb);
++
++#ifdef CONFIG_PREALLOC_RECV_SKB
++
++ skb_reset_tail_pointer(pskb);
++
++ pskb->len = 0;
++
++ skb_queue_tail(&precvpriv->free_recv_skb_queue, pskb);
++
++#else
++ rtw_skb_free(pskb);
++#endif
++
++ }
++
++}
++
++
++static void usb_read_port_complete(struct urb *purb, struct pt_regs *regs)
++{
++ _irqL irqL;
++ uint isevt, *pbuf;
++ struct recv_buf *precvbuf = (struct recv_buf *)purb->context;
++ _adapter *padapter =(_adapter *)precvbuf->adapter;
++ struct recv_priv *precvpriv = &padapter->recvpriv;
++
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete!!!\n"));
++
++ //_enter_critical(&precvpriv->lock, &irqL);
++ //precvbuf->irp_pending=_FALSE;
++ //precvpriv->rx_pending_cnt --;
++ //_exit_critical(&precvpriv->lock, &irqL);
++
++ precvpriv->rx_pending_cnt --;
++
++ //if(precvpriv->rx_pending_cnt== 0)
++ //{
++ // RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete: rx_pending_cnt== 0, set allrxreturnevt!\n"));
++ // _rtw_up_sema(&precvpriv->allrxreturnevt);
++ //}
++
++ if(padapter->bSurpriseRemoved || padapter->bDriverStopped||padapter->bReadPortCancel)
++ {
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete:bDriverStopped(%d) OR bSurpriseRemoved(%d)\n", padapter->bDriverStopped, padapter->bSurpriseRemoved));
++
++ #ifdef CONFIG_PREALLOC_RECV_SKB
++ precvbuf->reuse = _TRUE;
++ #else
++ if(precvbuf->pskb){
++ DBG_8192C("==> free skb(%p)\n",precvbuf->pskb);
++ rtw_skb_free(precvbuf->pskb);
++ }
++ #endif
++ DBG_8192C("%s()-%d: RX Warning! bDriverStopped(%d) OR bSurpriseRemoved(%d) bReadPortCancel(%d)\n",
++ __FUNCTION__, __LINE__,padapter->bDriverStopped, padapter->bSurpriseRemoved,padapter->bReadPortCancel);
++ goto exit;
++ }
++
++ if(purb->status==0)//SUCCESS
++ {
++ if ((purb->actual_length > MAX_RECVBUF_SZ) || (purb->actual_length < RXDESC_SIZE))
++ {
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete: (purb->actual_length > MAX_RECVBUF_SZ) || (purb->actual_length < RXDESC_SIZE)\n"));
++ precvbuf->reuse = _TRUE;
++ rtw_read_port(padapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf);
++ DBG_8192C("%s()-%d: RX Warning!\n", __FUNCTION__, __LINE__);
++ }
++ else
++ {
++ rtw_reset_continual_urb_error(adapter_to_dvobj(padapter));
++
++ precvbuf->transfer_len = purb->actual_length;
++ skb_put(precvbuf->pskb, purb->actual_length);
++ skb_queue_tail(&precvpriv->rx_skb_queue, precvbuf->pskb);
++
++ if (skb_queue_len(&precvpriv->rx_skb_queue)<=1)
++ tasklet_schedule(&precvpriv->recv_tasklet);
++
++ precvbuf->pskb = NULL;
++ precvbuf->reuse = _FALSE;
++ rtw_read_port(padapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf);
++ }
++ }
++ else
++ {
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete : purb->status(%d) != 0 \n", purb->status));
++
++ DBG_8192C("###=> usb_read_port_complete => urb status(%d)\n", purb->status);
++
++ if(rtw_inc_and_chk_continual_urb_error(adapter_to_dvobj(padapter)) == _TRUE ){
++ padapter->bSurpriseRemoved = _TRUE;
++ }
++
++ switch(purb->status) {
++ case -EINVAL:
++ case -EPIPE:
++ case -ENODEV:
++ case -ESHUTDOWN:
++ //padapter->bSurpriseRemoved=_TRUE;
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete:bSurpriseRemoved=TRUE\n"));
++ case -ENOENT:
++ padapter->bDriverStopped=_TRUE;
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete:bDriverStopped=TRUE\n"));
++ break;
++ case -EPROTO:
++ case -EILSEQ:
++ case -ETIME:
++ case -ECOMM:
++ case -EOVERFLOW:
++ #ifdef DBG_CONFIG_ERROR_DETECT
++ {
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++ pHalData->srestpriv.Wifi_Error_Status = USB_READ_PORT_FAIL;
++ }
++ #endif
++ precvbuf->reuse = _TRUE;
++ rtw_read_port(padapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf);
++ break;
++ case -EINPROGRESS:
++ precvpriv->read_port_complete_EINPROGRESS_cnt++;
++ DBG_8192C("ERROR: URB IS IN PROGRESS!/n");
++ break;
++ default:
++ precvpriv->read_port_complete_other_urb_err_cnt++;
++ break;
++ }
++
++ }
++
++exit:
++
++_func_exit_;
++
++}
++
++static u32 usb_read_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem)
++{
++ _irqL irqL;
++ int err;
++ unsigned int pipe;
++ SIZE_PTR tmpaddr=0;
++ SIZE_PTR alignment=0;
++ u32 ret = _SUCCESS;
++ PURB purb = NULL;
++ struct recv_buf *precvbuf = (struct recv_buf *)rmem;
++ _adapter *adapter = pintfhdl->padapter;
++ struct dvobj_priv *pdvobj = adapter_to_dvobj(adapter);
++ struct recv_priv *precvpriv = &adapter->recvpriv;
++ struct usb_device *pusbd = pdvobj->pusbdev;
++
++_func_enter_;
++
++ if(adapter->bDriverStopped || adapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx)
++ {
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port:( padapter->bDriverStopped ||padapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx)!!!\n"));
++ return _FAIL;
++ }
++
++#ifdef CONFIG_PREALLOC_RECV_SKB
++ if((precvbuf->reuse == _FALSE) || (precvbuf->pskb == NULL))
++ {
++ if (NULL != (precvbuf->pskb = skb_dequeue(&precvpriv->free_recv_skb_queue)))
++ {
++ precvbuf->reuse = _TRUE;
++ }
++ }
++#endif
++
++
++ if(precvbuf !=NULL)
++ {
++ rtl8192cu_init_recvbuf(adapter, precvbuf);
++
++ //re-assign for linux based on skb
++ if((precvbuf->reuse == _FALSE) || (precvbuf->pskb == NULL))
++ {
++ precvbuf->pskb = rtw_skb_alloc(MAX_RECVBUF_SZ + RECVBUFF_ALIGN_SZ);
++
++ if(precvbuf->pskb == NULL)
++ {
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("init_recvbuf(): alloc_skb fail!\n"));
++ precvpriv->recvbuf_skb_alloc_fail_cnt++;
++ return _FAIL;
++ }
++
++ tmpaddr = (SIZE_PTR)precvbuf->pskb->data;
++ alignment = tmpaddr & (RECVBUFF_ALIGN_SZ-1);
++ skb_reserve(precvbuf->pskb, (RECVBUFF_ALIGN_SZ - alignment));
++
++ precvbuf->phead = precvbuf->pskb->head;
++ precvbuf->pdata = precvbuf->pskb->data;
++ precvbuf->ptail = skb_tail_pointer(precvbuf->pskb);
++ precvbuf->pend = skb_end_pointer(precvbuf->pskb);
++ precvbuf->pbuf = precvbuf->pskb->data;
++ }
++ else//reuse skb
++ {
++ precvbuf->phead = precvbuf->pskb->head;
++ precvbuf->pdata = precvbuf->pskb->data;
++ precvbuf->ptail = skb_tail_pointer(precvbuf->pskb);
++ precvbuf->pend = skb_end_pointer(precvbuf->pskb);
++ precvbuf->pbuf = precvbuf->pskb->data;
++
++ precvbuf->reuse = _FALSE;
++ }
++
++ //_enter_critical(&precvpriv->lock, &irqL);
++ //precvpriv->rx_pending_cnt++;
++ //precvbuf->irp_pending = _TRUE;
++ //_exit_critical(&precvpriv->lock, &irqL);
++
++ precvpriv->rx_pending_cnt++;
++
++ purb = precvbuf->purb;
++
++ //translate DMA FIFO addr to pipehandle
++ pipe = ffaddr2pipehdl(pdvobj, addr);
++
++ usb_fill_bulk_urb(purb, pusbd, pipe,
++ precvbuf->pbuf,
++ MAX_RECVBUF_SZ,
++ usb_read_port_complete,
++ precvbuf);//context is precvbuf
++
++ err = usb_submit_urb(purb, GFP_ATOMIC);
++ if((err) && (err != (-EPERM)))
++ {
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("cannot submit rx in-token(err=0x%.8x), URB_STATUS =0x%.8x", err, purb->status));
++ DBG_8192C("cannot submit rx in-token(err = 0x%08x),urb_status = %d\n",err,purb->status);
++ ret = _FAIL;
++ }
++ }
++ else
++ {
++ precvpriv->recvbuf_null_cnt++;
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port:precvbuf ==NULL\n"));
++ ret = _FAIL;
++ }
++
++_func_exit_;
++
++ return ret;
++}
++#endif // CONFIG_USE_USB_BUFFER_ALLOC_RX
++
++void rtl8192cu_xmit_tasklet(void *priv)
++{
++ int ret = _FALSE;
++ _adapter *padapter = (_adapter*)priv;
++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++
++ if(check_fwstate(&padapter->mlmepriv, _FW_UNDER_SURVEY) == _TRUE)
++ return;
++
++ while(1)
++ {
++ if ((padapter->bDriverStopped == _TRUE)||(padapter->bSurpriseRemoved== _TRUE) || (padapter->bWritePortCancel == _TRUE))
++ {
++ DBG_8192C("xmit_tasklet => bDriverStopped or bSurpriseRemoved or bWritePortCancel\n");
++ break;
++ }
++
++ ret = rtl8192cu_xmitframe_complete(padapter, pxmitpriv, NULL);
++
++ if(ret==_FALSE)
++ break;
++
++ }
++
++}
++
++void rtl8192cu_set_intf_ops(struct _io_ops *pops)
++{
++ _func_enter_;
++
++ _rtw_memset((u8 *)pops, 0, sizeof(struct _io_ops));
++
++ pops->_read8 = &usb_read8;
++ pops->_read16 = &usb_read16;
++ pops->_read32 = &usb_read32;
++ pops->_read_mem = &usb_read_mem;
++ pops->_read_port = &usb_read_port;
++
++ pops->_write8 = &usb_write8;
++ pops->_write16 = &usb_write16;
++ pops->_write32 = &usb_write32;
++ pops->_writeN = &usb_writeN;
++
++#ifdef CONFIG_USB_SUPPORT_ASYNC_VDN_REQ
++ pops->_write8_async= &usb_async_write8;
++ pops->_write16_async = &usb_async_write16;
++ pops->_write32_async = &usb_async_write32;
++#endif
++ pops->_write_mem = &usb_write_mem;
++ pops->_write_port = &usb_write_port;
++
++ pops->_read_port_cancel = &usb_read_port_cancel;
++ pops->_write_port_cancel = &usb_write_port_cancel;
++
++#ifdef CONFIG_USB_INTERRUPT_IN_PIPE
++ pops->_read_interrupt = &usb_read_interrupt;
++#endif
++
++ _func_exit_;
++
++}
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/hal/rtl8192c/usb/usb_ops_xp.c linux-xbian-rpi/drivers/net/wireless/rtl8192cu/hal/rtl8192c/usb/usb_ops_xp.c
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/hal/rtl8192c/usb/usb_ops_xp.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/hal/rtl8192c/usb/usb_ops_xp.c 2015-07-28 01:20:58.313625760 +0200
+@@ -0,0 +1,1264 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#define _HCI_OPS_OS_C_
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++#include <osdep_intf.h>
++#include <circ_buf.h>
++
++#if defined (PLATFORM_LINUX) && defined (PLATFORM_WINDOWS)
++ #error "Shall be Linux or Windows, but not both!\n"
++#endif
++
++#ifndef CONFIG_USB_HCI
++ #error "CONFIG_USB_HCI shall be on!\n"
++#endif
++
++
++#include <usb.h>
++#include <usbdlib.h>
++#include <usbioctl.h>
++
++#include <usb_ops.h>
++#include <recv_osdep.h>
++
++#include <usb_osintf.h>
++
++
++struct zero_bulkout_context
++{
++ void *pbuf;
++ void *purb;
++ void *pirp;
++ void *padapter;
++};
++
++#define usb_write_cmd usb_write_mem
++#define usb_read_cmd usb_read_mem
++#define usb_write_cmd_complete usb_write_mem_complete
++//#define usb_read_cmd_complete usb_read_mem_complete
++
++
++
++uint usb_init_intf_priv(struct intf_priv *pintfpriv)
++{
++
++ PURB piorw_urb;
++ u8 NextDeviceStackSize;
++ struct dvobj_priv *pdev = (struct dvobj_priv *)pintfpriv->intf_dev;
++ _adapter * padapter=pdev->padapter;
++
++_func_enter_;
++
++ RT_TRACE(_module_hci_ops_os_c_,_drv_info_,("\n +usb_init_intf_priv\n"));
++
++ pintfpriv->intf_status = _IOREADY;
++
++ if(pdev->ishighspeed) pintfpriv->max_iosz = 128;
++ else pintfpriv->max_iosz = 64;
++
++
++ _init_timer(&pintfpriv->io_timer, padapter->hndis_adapter, io_irp_timeout_handler, pintfpriv);
++
++
++ RT_TRACE(_module_hci_ops_os_c_,_drv_info_,("usb_init_intf_priv:pintfpriv->max_iosz:%d\n",pintfpriv->max_iosz));
++
++ pintfpriv->io_wsz = 0;
++ pintfpriv->io_rsz = 0;
++
++ pintfpriv->allocated_io_rwmem = rtw_zmalloc(pintfpriv->max_iosz +4);
++
++ if (pintfpriv->allocated_io_rwmem == NULL){
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("\n usb_init_intf_priv:pintfpriv->allocated_io_rwmem == NULL\n"));
++ goto usb_init_intf_priv_fail;
++ }
++
++ pintfpriv->io_rwmem = pintfpriv->allocated_io_rwmem + 4 \
++ -( (u32)(pintfpriv->allocated_io_rwmem) & 3);
++
++
++
++ NextDeviceStackSize = (u8)pdev->nextdevstacksz;//pintfpriv->pUsbDevObj->StackSize + 1;
++
++ piorw_urb = (PURB)ExAllocatePool(NonPagedPool, sizeof(URB) );
++ if(piorw_urb == NULL)
++ goto usb_init_intf_priv_fail;
++
++ pintfpriv->piorw_urb = piorw_urb;
++
++ pintfpriv->piorw_irp = IoAllocateIrp(NextDeviceStackSize , FALSE);
++
++
++ pintfpriv->io_irp_cnt=1;
++ pintfpriv->bio_irp_pending=_FALSE;
++
++ _rtw_init_sema(&(pintfpriv->io_retevt), 0);//NdisInitializeEvent(&pintfpriv->io_irp_return_evt);
++
++_func_exit_;
++ return _SUCCESS;
++
++usb_init_intf_priv_fail:
++
++ if (pintfpriv->allocated_io_rwmem)
++ rtw_mfree((u8 *)(pintfpriv->allocated_io_rwmem), pintfpriv->max_iosz +4);
++
++ if(piorw_urb)
++ ExFreePool(piorw_urb);
++
++ RT_TRACE(_module_hci_ops_os_c_,_drv_info_,("\n -usb_init_intf_priv(usb_init_intf_priv_fail)\n"));
++
++_func_exit_;
++ return _FAIL;
++
++}
++
++void usb_unload_intf_priv(struct intf_priv *pintfpriv)
++{
++
++_func_enter_;
++
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("\n+usb_unload_intf_priv\n"));
++
++ rtw_mfree((u8 *)(pintfpriv->allocated_io_rwmem), pintfpriv->max_iosz+4);
++
++#ifdef PLATFORM_WINDOWS
++ if(pintfpriv->piorw_urb)
++ ExFreePool(pintfpriv->piorw_urb);
++
++ if(pintfpriv->piorw_irp)
++ IoFreeIrp(pintfpriv->piorw_irp);
++#endif
++
++
++#ifdef PLATFORM_LINUX
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("\npintfpriv->io_irp_cnt=%d\n",pintfpriv->io_irp_cnt));
++ pintfpriv->io_irp_cnt--;
++ if(pintfpriv->io_irp_cnt){
++ if(pintfpriv->bio_irp_pending==_TRUE){
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("\nkill iorw_urb\n"));
++ usb_kill_urb(pintfpriv->piorw_urb);
++ }
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("\n wait io_retevt\n"));
++ _rtw_down_sema(&(pintfpriv->io_retevt));
++ }
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("\n cancel io_urb ok\n"));
++#endif
++
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("\n-usb_unload_intf_priv\n"));
++
++_func_exit_;
++
++}
++
++void *ffaddr2pipehdl(struct dvobj_priv *pNdisCEDvice, u32 addr)
++{
++ HANDLE PipeHandle = NULL;
++ _adapter *padapter = pNdisCEDvice->padapter;
++
++
++ if(pNdisCEDvice->nr_endpoint == 11)
++ {
++ switch(addr)
++ {
++ case RTL8712_DMA_BEQ:
++ PipeHandle= padapter->halpriv.pipehdls_r8712[3] ;
++ break;
++ case RTL8712_DMA_BKQ:
++ PipeHandle= padapter->halpriv.pipehdls_r8712[4];
++ break;
++ case RTL8712_DMA_VIQ:
++ PipeHandle= padapter->halpriv.pipehdls_r8712[2];
++ break;
++ case RTL8712_DMA_VOQ:
++ PipeHandle= padapter->halpriv.pipehdls_r8712[1];
++ break;
++ case RTL8712_DMA_BCNQ:
++ PipeHandle= padapter->halpriv.pipehdls_r8712[6];
++ break;
++ case RTL8712_DMA_BMCQ: //HI Queue
++ PipeHandle= padapter->halpriv.pipehdls_r8712[7];
++ break;
++ case RTL8712_DMA_MGTQ:
++ PipeHandle= padapter->halpriv.pipehdls_r8712[8];
++ break;
++ case RTL8712_DMA_RX0FF:
++ PipeHandle= padapter->halpriv.pipehdls_r8712[0];
++ break;
++ case RTL8712_DMA_C2HCMD:
++ PipeHandle= padapter->halpriv.pipehdls_r8712[5];
++ break;
++ case RTL8712_DMA_H2CCMD:
++ PipeHandle= padapter->halpriv.pipehdls_r8712[9];
++ break;
++
++ }
++
++ }
++ else if(pNdisCEDvice->nr_endpoint == 6)
++ {
++ switch(addr)
++ {
++ case RTL8712_DMA_BEQ:
++ PipeHandle= padapter->halpriv.pipehdls_r8712[3];
++ break;
++ case RTL8712_DMA_BKQ:
++ PipeHandle= padapter->halpriv.pipehdls_r8712[4];
++ break;
++ case RTL8712_DMA_VIQ:
++ PipeHandle= padapter->halpriv.pipehdls_r8712[2];
++ break;
++ case RTL8712_DMA_VOQ:
++ PipeHandle= padapter->halpriv.pipehdls_r8712[1];
++ break;
++ case RTL8712_DMA_RX0FF:
++ case RTL8712_DMA_C2HCMD:
++ PipeHandle= padapter->halpriv.pipehdls_r8712[0];
++ break;
++ case RTL8712_DMA_H2CCMD:
++ case RTL8712_DMA_BCNQ:
++ case RTL8712_DMA_BMCQ:
++ case RTL8712_DMA_MGTQ:
++ PipeHandle= padapter->halpriv.pipehdls_r8712[5];
++ break;
++
++ }
++
++ }
++ else if(pNdisCEDvice->nr_endpoint == 4)
++ {
++ switch(addr)
++ {
++ case RTL8712_DMA_BEQ:
++ //case RTL8712_DMA_BKQ:
++ PipeHandle= padapter->halpriv.pipehdls_r8712[2];
++ break;
++ //case RTL8712_DMA_VIQ:
++ case RTL8712_DMA_VOQ:
++ PipeHandle= padapter->halpriv.pipehdls_r8712[1];
++ break;
++ case RTL8712_DMA_RX0FF:
++ case RTL8712_DMA_C2HCMD:
++ PipeHandle= padapter->halpriv.pipehdls_r8712[0];
++ break;
++ case RTL8712_DMA_H2CCMD:
++ case RTL8712_DMA_BCNQ:
++ case RTL8712_DMA_BMCQ:
++ case RTL8712_DMA_MGTQ:
++ PipeHandle= padapter->halpriv.pipehdls_r8712[3];
++ break;
++ }
++
++ }
++ else
++ {
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("ffaddr2pipehdl():nr_endpoint=%d error!\n", pNdisCEDvice->nr_endpoint));
++ }
++
++ return PipeHandle;
++
++}
++
++
++NTSTATUS usb_bulkout_zero_complete(
++ PDEVICE_OBJECT pUsbDevObj,
++ PIRP pIrp, void* pZeroContext)
++{
++ struct zero_bulkout_context *pcontext = (struct zero_bulkout_context *)pZeroContext;
++
++_func_enter_;
++
++ if(pcontext)
++ {
++ if(pcontext->pbuf)
++ {
++ ExFreePool(pcontext->pbuf);
++ }
++
++ if(pcontext->purb)
++ {
++ ExFreePool(pcontext->purb);
++ }
++
++ if(pcontext->pirp && (pIrp ==pcontext->pirp))
++ {
++ IoFreeIrp(pIrp);
++ }
++
++ ExFreePool(pcontext);
++ }
++
++_func_exit_;
++
++ return STATUS_MORE_PROCESSING_REQUIRED;
++
++
++}
++
++u32 usb_bulkout_zero(struct intf_hdl *pintfhdl, u32 addr)
++{
++ struct zero_bulkout_context *pcontext;
++ unsigned char *pbuf;
++ char NextDeviceStackSize, len;
++ PIO_STACK_LOCATION nextStack;
++ USBD_STATUS usbdstatus;
++ HANDLE PipeHandle;
++ PIRP pirp = NULL;
++ PURB purb = NULL;
++ NDIS_STATUS ndisStatus = NDIS_STATUS_SUCCESS;
++ _adapter *padapter = (_adapter *)pintfhdl->adapter;
++ struct dvobj_priv *pdvobj = (struct dvobj_priv *)&padapter->dvobjpriv;
++
++
++_func_enter_;
++
++ if((padapter->bDriverStopped) || (padapter->bSurpriseRemoved) ||(padapter->pwrctrlpriv.pnp_bstop_trx))
++ {
++ return _FAIL;
++ }
++
++ len = 0;
++ NextDeviceStackSize = (char)pdvobj->nextdevstacksz;
++
++ pcontext = (struct zero_bulkout_context *)ExAllocatePool(NonPagedPool, sizeof(struct zero_bulkout_context));
++ pbuf = (unsigned char *)ExAllocatePool(NonPagedPool, sizeof(int));
++ purb = (PURB)ExAllocatePool(NonPagedPool, sizeof(URB));
++ pirp = IoAllocateIrp(NextDeviceStackSize, FALSE);
++
++ pcontext->pbuf = pbuf;
++ pcontext->purb = purb;
++ pcontext->pirp = pirp;
++ pcontext->padapter = padapter;
++
++ //translate DMA FIFO addr to pipehandle
++ PipeHandle = ffaddr2pipehdl(pdvobj, addr);
++
++
++ // Build our URB for USBD
++ UsbBuildInterruptOrBulkTransferRequest(
++ purb,
++ sizeof(struct _URB_BULK_OR_INTERRUPT_TRANSFER),
++ PipeHandle,
++ pbuf,
++ NULL,
++ len,
++ 0,
++ NULL);
++
++ //
++ // call the calss driver to perform the operation
++ // pass the URB to the USB driver stack
++ //
++ nextStack = IoGetNextIrpStackLocation(pirp);
++ nextStack->MajorFunction = IRP_MJ_INTERNAL_DEVICE_CONTROL;
++ nextStack->Parameters.Others.Argument1 = purb;
++ nextStack->Parameters.DeviceIoControl.IoControlCode = IOCTL_INTERNAL_USB_SUBMIT_URB;
++
++ //Set Completion Routine
++ IoSetCompletionRoutine(pirp, // irp to use
++ usb_bulkout_zero_complete, // callback routine
++ pcontext, // context
++ TRUE, // call on success
++ TRUE, // call on error
++ TRUE); // call on cancel
++
++
++ // Call IoCallDriver to send the irp to the usb bus driver
++ //
++ ndisStatus = IoCallDriver(pdvobj->pnextdevobj, pirp);
++ usbdstatus = URB_STATUS(purb);
++
++ if( USBD_HALTED(usbdstatus) )
++ {
++ padapter->bDriverStopped=_TRUE;
++ padapter->bSurpriseRemoved=_TRUE;
++ }
++
++ //
++ // The usb bus driver should always return STATUS_PENDING when bulk out irp async
++ //
++ if ( ndisStatus != STATUS_PENDING )
++ {
++ return _FAIL;
++ }
++
++_func_exit_;
++
++ return _SUCCESS;
++
++}
++
++void usb_read_mem(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem)
++{
++ _func_enter_;
++
++
++
++ _func_exit_;
++}
++
++NTSTATUS usb_write_mem_complete(PDEVICE_OBJECT pUsbDevObj, PIRP piowrite_irp, PVOID pusb_cnxt)
++{
++
++ _irqL irqL;
++ _list *head, *plist;
++ struct io_req *pio_req;
++ struct io_queue *pio_q = (struct io_queue *) pusb_cnxt;
++ struct intf_hdl *pintf = &(pio_q->intf);
++ struct intf_priv *pintfpriv = pintf->pintfpriv;
++ _adapter *padapter = (_adapter *)pintf->adapter;
++ NTSTATUS status = STATUS_SUCCESS;
++
++ head = &(pio_q->processing);
++
++ _func_enter_;
++
++ _enter_critical_bh(&(pio_q->lock), &irqL);
++
++ pintfpriv->io_irp_cnt--;
++ if(pintfpriv->io_irp_cnt ==0){
++ _rtw_up_sema(&(pintfpriv->io_retevt));
++ }
++
++ pintfpriv->bio_irp_pending=_FALSE;
++
++ switch(piowrite_irp->IoStatus.Status)
++ {
++ case STATUS_SUCCESS:
++ break;
++
++ default:
++ padapter->bSurpriseRemoved=_TRUE;
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("\n usbAsynIntOutComplete:pioread_irp->IoStatus.Status !=STATUS_SUCCESS\n"));
++ break;
++ }
++
++ //free irp in processing list...
++ while(rtw_is_list_empty(head) != _TRUE)
++ {
++ plist = get_next(head);
++ rtw_list_delete(plist);
++ pio_req = LIST_CONTAINOR(plist, struct io_req, list);
++ _rtw_up_sema(&pio_req->sema);
++ }
++
++ _exit_critical_bh(&(pio_q->lock), &irqL);
++
++ _func_exit_;
++
++ return STATUS_MORE_PROCESSING_REQUIRED;
++
++}
++
++void usb_write_mem(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *wmem)
++{
++ u32 bwritezero;
++ _irqL irqL;
++ USBD_STATUS usbdstatus;
++ PIO_STACK_LOCATION nextStack;
++ HANDLE PipeHandle;
++ struct io_req *pio_req;
++
++ _adapter *adapter = (_adapter *)pintfhdl->adapter;
++ struct intf_priv *pintfpriv = pintfhdl->pintfpriv;
++ struct dvobj_priv *pdev = (struct dvobj_priv *)pintfpriv->intf_dev;
++ PURB piorw_urb = pintfpriv->piorw_urb;
++ PIRP piorw_irp = pintfpriv->piorw_irp;
++ struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
++ NTSTATUS NtStatus = STATUS_SUCCESS;
++
++ _func_enter_;
++
++ pio_req = alloc_ioreq(pio_queue);
++
++ if ((pio_req == NULL)||(adapter->bSurpriseRemoved)){
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("async_irp_write32 : pio_req =0x%x adapter->bSurpriseRemoved=0x%x",pio_req,adapter->bSurpriseRemoved ));
++ goto exit;
++ }
++
++ _enter_critical_bh(&(pio_queue->lock), &irqL);
++
++ rtw_list_insert_tail(&(pio_req->list),&(pio_queue->processing));
++
++
++#ifdef NDIS51_MINIPORT
++ IoReuseIrp(piorw_irp, STATUS_SUCCESS);
++#else
++ piorw_irp->Cancel = _FALSE;
++#endif
++
++ if((adapter->bDriverStopped) || (adapter->bSurpriseRemoved) ||(adapter->pwrctrlpriv.pnp_bstop_trx))
++ {
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("\npadapter->pwrctrlpriv.pnp_bstop_trx==_TRUE\n"));
++ _func_exit_;
++ return;
++ }
++
++ //translate DMA FIFO addr to pipehandle
++ PipeHandle = ffaddr2pipehdl(pdev, addr);
++
++
++ pintfpriv->io_irp_cnt++;
++ pintfpriv->bio_irp_pending=_TRUE;
++ // Build our URB for USBD
++ UsbBuildInterruptOrBulkTransferRequest(
++ piorw_urb,
++ sizeof(struct _URB_BULK_OR_INTERRUPT_TRANSFER),
++ PipeHandle,
++ (PVOID)wmem,
++ NULL,
++ cnt,
++ 0,
++ NULL);
++
++ //
++ // call the calss driver to perform the operation
++ // pass the URB to the USB driver stack
++ //
++ nextStack = IoGetNextIrpStackLocation(piorw_irp);
++ nextStack->MajorFunction = IRP_MJ_INTERNAL_DEVICE_CONTROL;
++ nextStack->Parameters.Others.Argument1 = (PURB)piorw_urb;
++ nextStack->Parameters.DeviceIoControl.IoControlCode = IOCTL_INTERNAL_USB_SUBMIT_URB;
++
++ IoSetCompletionRoutine(
++ piorw_irp, // irp to use
++ usb_write_mem_complete, // routine to call when irp is done
++ pio_queue, // context to pass routine
++ TRUE, // call on success
++ TRUE, // call on error
++ TRUE); // call on cancel
++
++ //
++ // Call IoCallDriver to send the irp to the usb port
++ //
++ NtStatus = IoCallDriver(pdev->pnextdevobj, piorw_irp);
++ usbdstatus = URB_STATUS(piorw_urb);
++
++ //
++ // The USB driver should always return STATUS_PENDING when
++ // it receives a write irp
++ //
++ if ((NtStatus != STATUS_PENDING) || USBD_HALTED(usbdstatus) ) {
++
++ if( USBD_HALTED(usbdstatus) ) {
++
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_write_mem():USBD_HALTED(usbdstatus)=%X!\n",USBD_HALTED(usbdstatus)) );
++ }
++ _func_exit_;
++ return;//STATUS_UNSUCCESSFUL;
++ }
++
++ _exit_critical_bh(&(pio_queue->lock), &irqL);
++
++ _rtw_down_sema(&pio_req->sema);
++ free_ioreq(pio_req, pio_queue);
++
++
++ bwritezero = _FALSE;
++ if (pdev->ishighspeed)
++ {
++ if(cnt> 0 && cnt%512 == 0)
++ bwritezero = _TRUE;
++
++ }
++ else
++ {
++ if(cnt > 0 && cnt%64 == 0)
++ bwritezero = _TRUE;
++ }
++
++
++ if(bwritezero == _TRUE)
++ {
++ usb_bulkout_zero(pintfhdl, addr);
++ }
++
++exit:
++
++ _func_exit_;
++
++}
++
++NTSTATUS usb_read_port_complete(PDEVICE_OBJECT pUsbDevObj, PIRP pIrp, PVOID context)
++{
++ uint isevt, *pbuf;
++ struct _URB_BULK_OR_INTERRUPT_TRANSFER *pbulkurb;
++ USBD_STATUS usbdstatus;
++ struct recv_buf *precvbuf = (struct recv_buf *)context;
++ _adapter *adapter =(_adapter *)precvbuf->adapter;
++ struct recv_priv *precvpriv = &adapter->recvpriv;
++ struct dvobj_priv *dev = (struct dvobj_priv *)&adapter->dvobjpriv;
++ PURB purb = precvbuf->purb;
++ struct intf_hdl *pintfhdl = &adapter->pio_queue->intf;
++
++ //RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete!!!\n"));
++
++ usbdstatus = URB_STATUS(purb);
++
++ _rtw_spinlock_ex(&precvpriv->lock);
++ precvbuf->irp_pending=_FALSE;
++ precvpriv->rx_pending_cnt --;
++ _rtw_spinunlock_ex(&precvpriv->lock);
++
++ if(precvpriv->rx_pending_cnt== 0) {
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete: rx_pending_cnt== 0, set allrxreturnevt!\n"));
++ _rtw_up_sema(&precvpriv->allrxreturnevt);
++ }
++
++
++ if( pIrp->Cancel == _TRUE ) {
++
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete: One IRP has been cancelled succesfully\n"));
++ return STATUS_MORE_PROCESSING_REQUIRED;
++ }
++ if(adapter->bSurpriseRemoved) {
++
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete:bDriverStopped(%d) OR bSurpriseRemoved(%d)", adapter->bDriverStopped, adapter->bSurpriseRemoved));
++ return STATUS_MORE_PROCESSING_REQUIRED;
++ }
++
++ switch(pIrp->IoStatus.Status)
++ {
++ case STATUS_SUCCESS:
++
++ pbulkurb = &(precvbuf->purb)->UrbBulkOrInterruptTransfer;
++ if((pbulkurb->TransferBufferLength >(MAX_RECVBUF_SZ)) || (pbulkurb->TransferBufferLength < RXDESC_SIZE) )
++ {
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("\n usb_read_port_complete: (pbulkurb->TransferBufferLength > MAX_RECVBUF_SZ) || (pbulkurb->TransferBufferLength < RXDESC_SIZE)\n"));
++ rtw_read_port(adapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf);
++ }
++ else
++ {
++ precvbuf->transfer_len = pbulkurb->TransferBufferLength;
++
++ pbuf = (uint*)precvbuf->pbuf;
++
++ if((isevt = *(pbuf+1)&0x1ff) == 0x1ff)
++ {
++ rxcmd_event_hdl(adapter, pbuf);//rx c2h events
++
++ rtw_read_port(adapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf);
++ }
++ else
++ {
++ if(recvbuf2recvframe(adapter, precvbuf)==_FAIL)//rx packets
++ {
++ //precvbuf->reuse = _TRUE;
++ rtw_read_port(adapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf);
++ }
++ }
++
++ }
++
++ break;
++
++ default:
++
++ if( !USBD_HALTED(usbdstatus) )
++ {
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("\n usb_read_port_complete():USBD_HALTED(usbdstatus)=%x (need to handle ) \n",USBD_HALTED(usbdstatus)));
++
++ }
++ else
++ {
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("\n usb_read_port_complete(): USBD_HALTED(usbdstatus)=%x \n\n", USBD_HALTED(usbdstatus)) );
++ adapter->bDriverStopped = _TRUE;
++ adapter->bSurpriseRemoved = _TRUE;
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete(): USBD_HALTED(usbdstatus)=%x \n\n", USBD_HALTED(usbdstatus))) ;
++ }
++
++ break;
++
++ }
++
++ return STATUS_MORE_PROCESSING_REQUIRED;
++
++}
++
++u32 usb_read_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem)
++{
++ u8 *pdata;
++ u16 size;
++ PURB purb;
++ PIRP pirp;
++ PIO_STACK_LOCATION nextStack;
++ NTSTATUS ntstatus;
++ USBD_STATUS usbdstatus;
++ HANDLE PipeHandle;
++ struct recv_buf *precvbuf = (struct recv_buf *)rmem;
++ struct intf_priv *pintfpriv = pintfhdl->pintfpriv;
++ struct dvobj_priv *pdev = (struct dvobj_priv *)pintfpriv->intf_dev;
++ _adapter *adapter = (_adapter *)pdev->padapter;
++ struct recv_priv *precvpriv = &adapter->recvpriv;
++ u32 bResult = _FALSE;
++
++_func_enter_;
++
++ if(adapter->bDriverStopped || adapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx) {
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port:( padapter->bDriverStopped ||padapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx)!!!\n"));
++ return bResult;
++ }
++
++ if(precvbuf !=NULL)
++ {
++
++ rtl8192cu_init_recvbuf(adapter, precvbuf);
++
++ _rtw_spinlock(&precvpriv->lock);
++ precvpriv->rx_pending_cnt++;
++ precvbuf->irp_pending = _TRUE;
++ _rtw_spinunlock(&precvpriv->lock);
++
++ pdata = (u8*)precvbuf->pbuf;
++
++ size = sizeof( struct _URB_BULK_OR_INTERRUPT_TRANSFER );
++ purb = precvbuf->purb;
++
++ //translate DMA FIFO addr to pipehandle
++ PipeHandle = ffaddr2pipehdl(pdev, addr);
++
++ UsbBuildInterruptOrBulkTransferRequest(
++ purb,
++ (USHORT)size,
++ PipeHandle,
++ pdata,
++ NULL,
++ MAX_RECVBUF_SZ,
++ USBD_TRANSFER_DIRECTION_IN | USBD_SHORT_TRANSFER_OK,
++ NULL
++ );
++
++ pirp = precvbuf->pirp;
++
++#if NDIS51_MINIPORT
++ IoReuseIrp(pirp, STATUS_SUCCESS);
++#else
++ pirp->Cancel = _FALSE;
++#endif
++
++ // call the class driver to perform the operation
++ // and pass the URB to the USB driver stack
++ nextStack = IoGetNextIrpStackLocation(pirp);
++ nextStack->Parameters.Others.Argument1 = purb;
++ nextStack->Parameters.DeviceIoControl.IoControlCode = IOCTL_INTERNAL_USB_SUBMIT_URB;
++ nextStack->MajorFunction = IRP_MJ_INTERNAL_DEVICE_CONTROL;
++
++ IoSetCompletionRoutine(
++ pirp, // irp to use
++ usb_read_port_complete, // routine to call when irp is done
++ precvbuf, // context to pass routine
++ TRUE, // call on success
++ TRUE, // call on error
++ TRUE); // call on cancel
++
++ //
++ // The IoCallDriver routine
++ // sends an IRP to the driver associated with a specified device object.
++ //
++ ntstatus = IoCallDriver(pdev->pnextdevobj, pirp);
++ usbdstatus = URB_STATUS(purb);
++
++ if( USBD_HALTED(usbdstatus) ) {
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("\n usb_read_port(): USBD_HALTED(usbdstatus=0x%.8x)=%.8x \n\n", usbdstatus, USBD_HALTED(usbdstatus)));
++ pdev->padapter->bDriverStopped=_TRUE;
++ pdev->padapter->bSurpriseRemoved=_TRUE;
++ }
++
++ if( ntstatus == STATUS_PENDING )
++ {
++ bResult = _TRUE;// The IRP is pended in USBD as we expected.
++ }
++ else {
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port(): IoCallDriver failed!!! IRP STATUS: %X\n", ntstatus));
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port(): IoCallDriver failed!!! USB STATUS: %X\n", usbdstatus));
++ }
++
++ }
++ else{
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port:precv_frame ==NULL\n"));
++ }
++
++_func_exit_;
++
++ return bResult;
++
++}
++
++void usb_read_port_cancel(_adapter *padapter)
++{
++ struct recv_buf *precvbuf;
++ sint i;
++ struct dvobj_priv *pdev = &padapter->dvobjpriv;
++ struct recv_priv *precvpriv=&padapter->recvpriv;
++
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("\n ==>usb_read_port_cancel\n"));
++
++ _rtw_spinlock(&precvpriv->lock);
++ precvpriv->rx_pending_cnt--; //decrease 1 for Initialize ++
++ _rtw_spinunlock(&precvpriv->lock);
++
++ if (precvpriv->rx_pending_cnt)
++ {
++ // Canceling Pending Recv Irp
++ precvbuf = (struct recv_buf *)precvpriv->precv_buf;
++
++ for( i = 0; i < NR_RECVBUFF; i++ )
++ {
++ if (precvbuf->irp_pending == _TRUE)
++ {
++ IoCancelIrp(precvbuf->pirp);
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_cancel() :IoCancelIrp\n"));
++ }
++
++ precvbuf++;
++ }
++
++ _rtw_down_sema(&precvpriv->allrxreturnevt);
++
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_cancel:down sema\n"));
++
++ }
++
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("<==usb_read_port_cancel\n"));
++
++}
++
++NTSTATUS usb_write_port_complete(
++ PDEVICE_OBJECT pUsbDevObj,
++ PIRP pIrp,
++ PVOID pTxContext
++)
++{
++ u32 i, bIrpSuccess, sz;
++ NTSTATUS status = STATUS_SUCCESS;
++ u8 *ptr;
++ struct xmit_frame *pxmitframe = (struct xmit_frame *) pTxContext;
++ struct xmit_buf *pxmitbuf = pxmitframe->pxmitbuf;
++ _adapter *padapter = pxmitframe->padapter;
++ struct dvobj_priv *pdev = (struct dvobj_priv *)&padapter->dvobjpriv;
++ struct io_queue *pio_queue = (struct io_queue *)padapter->pio_queue;
++ struct intf_hdl *pintfhdl = &(pio_queue->intf);
++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++
++_func_enter_;
++
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("+usb_write_port_complete\n"));
++
++ _rtw_spinlock_ex(&pxmitpriv->lock);
++ pxmitpriv->txirp_cnt--;
++ _rtw_spinunlock_ex(&pxmitpriv->lock);
++
++ if(pxmitpriv->txirp_cnt==0){
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_write_port_complete: txirp_cnt== 0, set allrxreturnevt!\n"));
++ _rtw_up_sema(&(pxmitpriv->tx_retevt));
++ }
++
++ status = pIrp->IoStatus.Status;
++
++ if( status == STATUS_SUCCESS )
++ bIrpSuccess = _TRUE;
++ else
++ bIrpSuccess = _FALSE;
++
++ if( pIrp->Cancel == _TRUE )
++ {
++ if(pxmitframe !=NULL)
++ {
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("\n usb_write_port_complete:pIrp->Cancel == _TRUE,(pxmitframe !=NULL\n"));
++ rtw_free_xmitframe(pxmitpriv, pxmitframe);
++ }
++
++ return STATUS_MORE_PROCESSING_REQUIRED;
++ }
++
++ if(padapter->bSurpriseRemoved)
++ {
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_write_port_complete:bDriverStopped(%d) OR bSurpriseRemoved(%d)", padapter->bDriverStopped, padapter->bSurpriseRemoved));
++ return STATUS_MORE_PROCESSING_REQUIRED;
++ }
++
++
++ //
++ // Send 0-byte here if necessary.
++ //
++ // <Note>
++ // 1. We MUST keep at most one IRP pending in each endpoint, otherwise USB host controler driver will hang.
++ // Besides, even 0-byte IRP shall be count into #IRP sent down, so, we send 0-byte here instead of TxFillDescriptor8187().
++ // 2. If we don't count 0-byte IRP into an #IRP sent down, Tx will stuck when we download files via BT and
++ // play online video on XP SP1 EHCU.
++ // 2005.12.26, by rcnjko.
++ //
++
++
++ for(i=0; i< 8; i++)
++ {
++ if(pIrp == pxmitframe->pxmit_irp[i])
++ {
++ pxmitframe->bpending[i] = _FALSE;//
++ //ac_tag = pxmitframe->ac_tag[i];
++ sz = pxmitframe->sz[i];
++ break;
++ }
++ }
++
++#if 0
++ pxmitframe->fragcnt--;
++ if(pxmitframe->fragcnt == 0)// if((pxmitframe->fragcnt == 0) && (pxmitframe->irpcnt == 8)){
++ {
++ //RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("\n usb_write_port_complete:pxmitframe->fragcnt == 0\n"));
++ rtw_free_xmitframe(pxmitpriv,pxmitframe);
++ }
++#else
++
++ //not to consider tx fragment
++ rtw_free_xmitframe(pxmitpriv, pxmitframe);
++
++#endif
++
++ rtl8192cu_xmitframe_complete(padapter, pxmitpriv, pxmitbuf);
++
++_func_exit_;
++
++ return STATUS_MORE_PROCESSING_REQUIRED;
++
++}
++
++u32 usb_write_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *wmem)
++{
++ u32 i, bwritezero;
++ u8 *ptr;
++ PIO_STACK_LOCATION nextStack;
++ USBD_STATUS usbdstatus;
++ HANDLE PipeHandle;
++ PIRP pirp = NULL;
++ PURB purb = NULL;
++ NDIS_STATUS ndisStatus = NDIS_STATUS_SUCCESS;
++ _adapter *padapter = (_adapter *)pintfhdl->adapter;
++ struct dvobj_priv *pNdisCEDvice = (struct dvobj_priv *)&padapter->dvobjpriv;
++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++ struct xmit_frame *pxmitframe = (struct xmit_frame *)wmem;
++
++_func_enter_;
++
++ if((padapter->bDriverStopped) || (padapter->bSurpriseRemoved) ||(padapter->pwrctrlpriv.pnp_bstop_trx))
++ {
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_write_port:( padapter->bDriverStopped ||padapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx)!!!\n"));
++ return _FAIL;
++ }
++
++
++ for(i=0; i<8; i++)
++ {
++ if(pxmitframe->bpending[i] == _FALSE)
++ {
++ _rtw_spinlock(&pxmitpriv->lock);
++ pxmitpriv->txirp_cnt++;
++ pxmitframe->bpending[i] = _TRUE;
++ _rtw_spinunlock(&pxmitpriv->lock);
++
++ pxmitframe->sz[i] = cnt;
++ purb = pxmitframe->pxmit_urb[i];
++ pirp = pxmitframe->pxmit_irp[i];
++
++ //pxmitframe->ac_tag[i] = ac_tag;
++
++ break;
++ }
++ }
++
++ bwritezero = _FALSE;
++ if (pNdisCEDvice->ishighspeed)
++ {
++ if(cnt> 0 && cnt%512 == 0)
++ {
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("ishighspeed, cnt=%d\n", cnt));
++ //cnt=cnt+1;
++ bwritezero = _TRUE;
++ }
++ }
++ else
++ {
++ if(cnt > 0 && cnt%64 == 0)
++ {
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("cnt=%d\n", cnt));
++ //cnt=cnt+1;
++ bwritezero = _TRUE;
++ }
++ }
++
++
++#ifdef NDIS51_MINIPORT
++ IoReuseIrp(pirp, STATUS_SUCCESS);
++#else
++ pirp->Cancel = _FALSE;
++#endif
++
++
++ //translate DMA FIFO addr to pipehandle
++ PipeHandle = ffaddr2pipehdl(pNdisCEDvice, addr);
++
++
++ // Build our URB for USBD
++ UsbBuildInterruptOrBulkTransferRequest(
++ purb,
++ sizeof(struct _URB_BULK_OR_INTERRUPT_TRANSFER),
++ PipeHandle,
++ pxmitframe->mem_addr,
++ NULL,
++ cnt,
++ 0,
++ NULL);
++
++ //
++ // call the calss driver to perform the operation
++ // pass the URB to the USB driver stack
++ //
++ nextStack = IoGetNextIrpStackLocation(pirp);
++ nextStack->MajorFunction = IRP_MJ_INTERNAL_DEVICE_CONTROL;
++ nextStack->Parameters.Others.Argument1 = purb;
++ nextStack->Parameters.DeviceIoControl.IoControlCode = IOCTL_INTERNAL_USB_SUBMIT_URB;
++
++ //Set Completion Routine
++ IoSetCompletionRoutine(pirp, // irp to use
++ usb_write_port_complete, // callback routine
++ pxmitframe, // context
++ TRUE, // call on success
++ TRUE, // call on error
++ TRUE); // call on cancel
++
++
++ // Call IoCallDriver to send the irp to the usb bus driver
++ //
++ ndisStatus = IoCallDriver(pNdisCEDvice->pnextdevobj, pirp);
++ usbdstatus = URB_STATUS(purb);
++
++ if( USBD_HALTED(usbdstatus) )
++ {
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("\n usb_write_port(): USBD_HALTED(usbdstatus)=%x set bDriverStopped TRUE!\n\n",USBD_HALTED(usbdstatus)) );
++ padapter->bDriverStopped=_TRUE;
++ padapter->bSurpriseRemoved=_TRUE;
++ }
++
++ //
++ // The usb bus driver should always return STATUS_PENDING when bulk out irp async
++ //
++ if ( ndisStatus != STATUS_PENDING )
++ {
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("\n usb_write_port(): ndisStatus(%x) != STATUS_PENDING!\n\n", ndisStatus));
++
++ _func_exit_;
++
++ return _FAIL;
++ }
++
++ if(bwritezero == _TRUE)
++ {
++ usb_bulkout_zero(pintfhdl, addr);
++ }
++
++
++_func_exit_;
++
++ return _SUCCESS;
++
++}
++
++
++void usb_write_port_cancel(_adapter *padapter)
++{
++
++ sint i,j;
++ struct dvobj_priv *pdev = &padapter->dvobjpriv;
++ struct xmit_priv *pxmitpriv=&padapter->xmitpriv;
++ struct xmit_frame *pxmitframe;
++
++ _rtw_spinlock(&pxmitpriv->lock);
++ pxmitpriv->txirp_cnt--; //decrease 1 for Initialize ++
++ _rtw_spinunlock(&pxmitpriv->lock);
++
++ if (pxmitpriv->txirp_cnt)
++ {
++ // Canceling Pending Recv Irp
++ pxmitframe= (struct xmit_frame *)pxmitpriv->pxmit_frame_buf;
++
++ for( i = 0; i < NR_XMITFRAME; i++ )
++ {
++ for(j=0;j<8;j++)
++ {
++ if (pxmitframe->bpending[j]==_TRUE)
++ {
++ IoCancelIrp(pxmitframe->pxmit_irp[j]);
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,(" usb_write_port_cancel() :IoCancelIrp\n"));
++
++ }
++ }
++
++ pxmitframe++;
++ }
++
++ _rtw_down_sema(&(pxmitpriv->tx_retevt));
++
++ }
++
++}
++
++
++/*! \brief Wrap the pUrb to an IRP and send this IRP to Bus Driver. Then wait for this IRP completion.
++ The Caller shall be at Passive Level.
++*/
++NTSTATUS sync_callusbd(struct dvobj_priv *pdvobjpriv, PURB purb)
++{
++
++ KEVENT kevent;
++ PIRP irp;
++ IO_STATUS_BLOCK iostatusblock;
++ PIO_STACK_LOCATION nextstack;
++ USBD_STATUS usbdstatus;
++ LARGE_INTEGER waittime;
++ NTSTATUS ntstatus = STATUS_SUCCESS;
++ _adapter *padapter = pdvobjpriv->padapter;
++
++
++ _func_enter_;
++
++// if(padapter->bDriverStopped) {
++// goto exit;
++// }
++
++ KeInitializeEvent(&kevent, NotificationEvent, _FALSE);
++ irp = IoBuildDeviceIoControlRequest(
++ IOCTL_INTERNAL_USB_SUBMIT_URB,
++ pdvobjpriv->pphysdevobj,//CEdevice->pUsbDevObj,
++ NULL,
++ 0,
++ NULL,
++ 0,
++ _TRUE,
++ &kevent,
++ &iostatusblock);
++
++ if(irp == NULL) {
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("SyncCallUSBD: memory alloc for irp failed\n"));
++ ntstatus=STATUS_INSUFFICIENT_RESOURCES;
++ goto exit;
++ }
++
++ nextstack = IoGetNextIrpStackLocation(irp);
++ if(nextstack == NULL)
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("IoGetNextIrpStackLocation fail\n"));
++
++ nextstack->Parameters.Others.Argument1 = purb;
++
++ // Issue an IRP for Sync IO.
++ ntstatus = IoCallDriver(pdvobjpriv->pphysdevobj, irp);
++ usbdstatus = URB_STATUS(purb);
++
++ if(ntstatus == STATUS_PENDING)
++ {
++ // Method 1
++ waittime.QuadPart = -10000 * 50000;
++ ntstatus = KeWaitForSingleObject(&kevent, Executive, KernelMode, _FALSE, &waittime); //8150 code
++
++ // Method 2
++ //ntStatus = KeWaitForSingleObject(&Kevent, Executive, KernelMode, FALSE, NULL); //DDK sample
++
++ usbdstatus = URB_STATUS(purb);
++
++ if(ntstatus == STATUS_TIMEOUT)
++ {
++ //usbdevice->nIoStuckCnt++;
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("SyncCallUSBD: TIMEOUT....5000ms\n"));
++
++ // Method 2
++ IoCancelIrp(irp);
++ ntstatus = KeWaitForSingleObject(&kevent, Executive, KernelMode, _FALSE, NULL); //DDK sample
++ usbdstatus = URB_STATUS(purb);
++
++ usbdstatus = USBD_STATUS_SUCCESS;
++ }
++
++ }
++
++exit:
++
++ _func_exit_;
++
++ return ntstatus;
++
++}
++int usbctrl_vendorreq(struct intf_priv *pintfpriv, u8 request, u16 value, u16 index, void *pdata, u16 len, u8 requesttype)
++{
++ PURB purb;
++ u8 ret;
++ unsigned long transferflags;
++ NTSTATUS ntstatus;
++
++ struct dvobj_priv *pdvobjpriv = (struct dvobj_priv *)pintfpriv->intf_dev;
++
++ _func_enter_;
++
++ ret=_TRUE;
++ purb = (PURB)ExAllocatePool(NonPagedPool, sizeof(struct _URB_CONTROL_VENDOR_OR_CLASS_REQUEST) );
++ if(purb == NULL) {
++
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usbctrl_vendorreq(): Failed to allocate urb !!!\n"));
++ ret =_FALSE;
++ goto exit;
++ }
++
++ if (requesttype == 0x01) {
++ transferflags = USBD_TRANSFER_DIRECTION_IN;//read_in
++ } else {
++ transferflags= 0;//write_out
++ }
++
++ UsbBuildVendorRequest(
++ purb, //Pointer to an URB that is to be formatted as a vendor or class request.
++ URB_FUNCTION_VENDOR_DEVICE, //Indicates the URB is a vendor-defined request for a USB device.
++ sizeof(struct _URB_CONTROL_VENDOR_OR_CLASS_REQUEST), //Specifies the length, in bytes, of the URB.
++ transferflags, //TransferFlags
++ 0, //ReservedBits
++ request, //Request
++ value, //Value
++ index, //Index
++ pdata, //TransferBuffer
++ NULL, //TransferBufferMDL
++ len, //TransferBufferLength
++ NULL //Link
++ );
++
++ ntstatus = sync_callusbd(pdvobjpriv, purb);
++ if(!NT_SUCCESS(ntstatus))
++ {
++ ExFreePool(purb);
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,(" usbctrl_vendorreq() : SOMETHING WRONG\n") );
++ ret = _FALSE;
++ goto exit;
++ }
++
++ ExFreePool(purb);
++
++exit:
++ _func_exit_;
++
++ return ret;
++
++}
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/ifcfg-wlan0 linux-xbian-rpi/drivers/net/wireless/rtl8192cu/ifcfg-wlan0
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/ifcfg-wlan0 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/ifcfg-wlan0 2015-07-28 01:20:58.313625760 +0200
+@@ -0,0 +1,4 @@
++#DHCP client
++DEVICE=wlan0
++BOOTPROTO=dhcp
++ONBOOT=yes
+\ No newline at end of file
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/autoconf.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/autoconf.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/autoconf.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/autoconf.h 2015-07-28 01:20:58.317611539 +0200
+@@ -0,0 +1,336 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++
++/*
++ * Public General Config
++ */
++#define AUTOCONF_INCLUDED
++#define RTL871X_MODULE_NAME "92CU"
++#define DRV_NAME "rtl8192cu"
++
++#define CONFIG_USB_HCI 1
++
++#define CONFIG_RTL8192C 1
++
++#define PLATFORM_LINUX 1
++
++//#define CONFIG_IOCTL_CFG80211 1
++#ifdef CONFIG_IOCTL_CFG80211
++ //#define RTW_USE_CFG80211_STA_EVENT /* Indecate new sta asoc through cfg80211_new_sta */
++ #define CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER
++ //#define CONFIG_DEBUG_CFG80211 1
++ //#define CONFIG_DRV_ISSUE_PROV_REQ // IOT FOR S2
++ #define CONFIG_SET_SCAN_DENY_TIMER
++#endif
++
++/*
++ * Internal General Config
++ */
++//#define CONFIG_PWRCTRL
++//#define CONFIG_H2CLBK
++
++#define CONFIG_EMBEDDED_FWIMG 1
++//#define CONFIG_FILE_FWIMG
++
++#ifdef CONFIG_WAKE_ON_WLAN
++#define CONFIG_WOWLAN 1
++#endif //CONFIG_WAKE_ON_WLAN
++
++#define CONFIG_R871X_TEST 1
++
++#define CONFIG_XMIT_ACK
++#ifdef CONFIG_XMIT_ACK
++ #define CONFIG_XMIT_ACK_POLLING
++ #define CONFIG_ACTIVE_KEEP_ALIVE_CHECK
++#endif
++
++#define CONFIG_80211N_HT 1
++
++#define CONFIG_RECV_REORDERING_CTRL 1
++
++//#define CONFIG_TCP_CSUM_OFFLOAD_RX 1
++
++//#define CONFIG_BEFORE_LINKED_DIG
++//#define CONFIG_DRVEXT_MODULE 1
++
++#ifndef CONFIG_MP_INCLUDED
++ #define CONFIG_IPS 1
++ #ifdef CONFIG_IPS
++ //#define CONFIG_IPS_LEVEL_2 1 //enable this to set default IPS mode to IPS_LEVEL_2
++ #endif
++
++ #define SUPPORT_HW_RFOFF_DETECTED 1
++
++ #define CONFIG_LPS 1
++ #define CONFIG_BT_COEXIST 1
++
++ //befor link
++ #define CONFIG_ANTENNA_DIVERSITY
++
++ //after link
++ #ifdef CONFIG_ANTENNA_DIVERSITY
++ #define CONFIG_SW_ANTENNA_DIVERSITY
++ //#define CONFIG_HW_ANTENNA_DIVERSITY
++ #endif
++
++ #define CONFIG_IOL
++#else //#ifndef CONFIG_MP_INCLUDED
++ #define CONFIG_MP_IWPRIV_SUPPORT 1
++#endif //#ifndef CONFIG_MP_INCLUDED
++
++#define CONFIG_AP_MODE 1
++#ifdef CONFIG_AP_MODE
++ #define CONFIG_NATIVEAP_MLME 1
++ #ifndef CONFIG_NATIVEAP_MLME
++ #define CONFIG_HOSTAPD_MLME 1
++ #endif
++ #define CONFIG_FIND_BEST_CHANNEL 1
++ //#define CONFIG_NO_WIRELESS_HANDLERS 1
++#endif
++
++// Added by Albert 20110314
++#define CONFIG_P2P 1
++#ifdef CONFIG_P2P
++ //Added by Albert 20110812
++ //The CONFIG_WFD is for supporting the Wi-Fi display
++ #define CONFIG_WFD
++
++ #ifndef CONFIG_WIFI_TEST
++ #define CONFIG_P2P_REMOVE_GROUP_INFO
++ #endif
++ //#define CONFIG_DBG_P2P
++
++ //#define CONFIG_P2P_PS
++ //#define CONFIG_P2P_IPS
++
++ #define P2P_OP_CHECK_SOCIAL_CH
++ // Added comment by Borg 2013/06/21
++ // Issue: Nexus 4 is hard to do miracast.
++ // Root Cause: After group formation,
++ // Nexus 4 is possible to be not at OP channel of Invitation Resp/Nego Confirm but at social channel.
++ // Patch: While scan OP channel,
++ // not only scan OP channel of Invitation Resp/Nego Confirm,
++ // but also scan social channel(1, 6, 11)
++#endif
++
++// Added by Kurt 20110511
++//#define CONFIG_TDLS 1
++#ifdef CONFIG_TDLS
++// #ifndef CONFIG_WFD
++// #define CONFIG_WFD 1
++// #endif
++// #define CONFIG_TDLS_AUTOSETUP 1
++// #define CONFIG_TDLS_AUTOCHECKALIVE 1
++#endif
++
++#define CONFIG_SKB_COPY 1//for amsdu
++
++#define CONFIG_LED
++#ifdef CONFIG_LED
++ #define CONFIG_SW_LED
++ #ifdef CONFIG_SW_LED
++ //#define CONFIG_LED_HANDLED_BY_CMD_THREAD
++ #endif
++#endif // CONFIG_LED
++
++
++
++#define USB_INTERFERENCE_ISSUE // this should be checked in all usb interface
++#define CONFIG_GLOBAL_UI_PID
++
++#define CONFIG_LAYER2_ROAMING
++#define CONFIG_LAYER2_ROAMING_RESUME
++//#define CONFIG_ADAPTOR_INFO_CACHING_FILE // now just applied on 8192cu only, should make it general...
++//#define CONFIG_RESUME_IN_WORKQUEUE
++//#define CONFIG_SET_SCAN_DENY_TIMER
++#define CONFIG_LONG_DELAY_ISSUE
++#define CONFIG_NEW_SIGNAL_STAT_PROCESS
++//#define CONFIG_SIGNAL_DISPLAY_DBM //display RX signal with dbm
++#define RTW_NOTCH_FILTER 0 /* 0:Disable, 1:Enable */
++#define CONFIG_DEAUTH_BEFORE_CONNECT
++
++#ifdef CONFIG_IOL
++ #define CONFIG_IOL_LLT
++ #define CONFIG_IOL_MAC
++ #define CONFIG_IOL_BB_PHY_REG
++ #define CONFIG_IOL_BB_AGC_TAB
++ #define CONFIG_IOL_RF_RF90_PATH_A
++ #define CONFIG_IOL_RF_RF90_PATH_B
++#endif
++
++#define CONFIG_BR_EXT 1 // Enable NAT2.5 support for STA mode interface with a L2 Bridge
++#ifdef CONFIG_BR_EXT
++#define CONFIG_BR_EXT_BRNAME "br0"
++#endif // CONFIG_BR_EXT
++
++#define CONFIG_TX_MCAST2UNI 1 // Support IP multicast->unicast
++//#define CONFIG_DM_ADAPTIVITY
++//#define CONFIG_CHECK_AC_LIFETIME 1 // Check packet lifetime of 4 ACs.
++
++//#define CONFIG_CONCURRENT_MODE 1
++#ifdef CONFIG_CONCURRENT_MODE
++ #define CONFIG_TSF_RESET_OFFLOAD 1 // For 2 PORT TSF SYNC.
++ //#define CONFIG_HWPORT_SWAP //Port0->Sec , Port1 -> Pri
++ //#define CONFIG_STA_MODE_SCAN_UNDER_AP_MODE
++ //#define CONFIG_MULTI_VIR_IFACES //besides primary&secondary interfaces, extend to support more interfaces
++#endif // CONFIG_CONCURRENT_MODE
++
++#define CONFIG_80211D
++
++/*
++ * Interface Related Config
++ */
++
++//#define CONFIG_USB_ONE_OUT_EP
++//#define CONFIG_USB_INTERRUPT_IN_PIPE 1
++
++#ifndef CONFIG_MINIMAL_MEMORY_USAGE
++ #define CONFIG_USB_TX_AGGREGATION 1
++ #define CONFIG_USB_RX_AGGREGATION 1
++#endif
++
++#define CONFIG_PREALLOC_RECV_SKB 1
++//#define CONFIG_REDUCE_USB_TX_INT 1 // Trade-off: Improve performance, but may cause TX URBs blocked by USB Host/Bus driver on few platforms.
++//#define CONFIG_EASY_REPLACEMENT 1
++
++/*
++ * CONFIG_USE_USB_BUFFER_ALLOC_XX uses Linux USB Buffer alloc API and is for Linux platform only now!
++ */
++//#define CONFIG_USE_USB_BUFFER_ALLOC_TX 1 // Trade-off: For TX path, improve stability on some platforms, but may cause performance degrade on other platforms.
++//#define CONFIG_USE_USB_BUFFER_ALLOC_RX 1 // For RX path
++#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX
++#undef CONFIG_PREALLOC_RECV_SKB
++#endif
++
++/*
++ * USB VENDOR REQ BUFFER ALLOCATION METHOD
++ * if not set we'll use function local variable (stack memory)
++ */
++//#define CONFIG_USB_VENDOR_REQ_BUFFER_DYNAMIC_ALLOCATE
++#define CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC
++
++#define CONFIG_USB_VENDOR_REQ_MUTEX
++#define CONFIG_VENDOR_REQ_RETRY
++
++//#define CONFIG_USB_SUPPORT_ASYNC_VDN_REQ 1
++
++
++/*
++ * HAL Related Config
++ */
++
++#define RTL8192C_RX_PACKET_NO_INCLUDE_CRC 1
++
++#define SUPPORTED_BLOCK_IO
++
++
++
++#define RTL8192CU_FW_DOWNLOAD_ENABLE 1
++
++#define CONFIG_ONLY_ONE_OUT_EP_TO_LOW 0
++
++#define CONFIG_OUT_EP_WIFI_MODE 0
++
++#define ENABLE_USB_DROP_INCORRECT_OUT 0
++
++#define RTL8192CU_ASIC_VERIFICATION 0 // For ASIC verification.
++
++#define RTL8192CU_ADHOC_WORKAROUND_SETTING 1
++
++#define DISABLE_BB_RF 0
++
++#define RTL8191C_FPGA_NETWORKTYPE_ADHOC 0
++
++#ifdef CONFIG_MP_INCLUDED
++ #define MP_DRIVER 1
++ #undef CONFIG_USB_TX_AGGREGATION
++ #undef CONFIG_USB_RX_AGGREGATION
++#else
++ #define MP_DRIVER 0
++#endif
++
++
++/*
++ * Platform Related Config
++ */
++#ifdef CONFIG_PLATFORM_MN10300
++#define CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV
++
++#if defined (CONFIG_SW_ANTENNA_DIVERSITY)
++ #undef CONFIG_SW_ANTENNA_DIVERSITY
++ #define CONFIG_HW_ANTENNA_DIVERSITY
++#endif
++
++#endif
++
++#ifdef CONFIG_WISTRON_PLATFORM
++
++#endif
++
++#ifdef CONFIG_PLATFORM_TI_DM365
++#define CONFIG_USE_USB_BUFFER_ALLOC_RX 1
++#endif
++
++#define CONFIG_ATTEMPT_TO_FIX_AP_BEACON_ERROR
++
++/*
++ * Debug Related Config
++ */
++//#define CONFIG_DEBUG_RTL871X
++
++#define DBG 0
++//#define CONFIG_DEBUG_RTL819X
++
++//#define CONFIG_PROC_DEBUG 1
++
++//#define DBG_IO
++//#define DBG_DELAY_OS
++//#define DBG_MEM_ALLOC
++//#define DBG_IOCTL
++
++//#define DBG_TX
++//#define DBG_XMIT_BUF
++//#define DBG_TX_DROP_FRAME
++
++//#define DBG_RX_DROP_FRAME
++//#define DBG_RX_SEQ
++//#define DBG_RX_SIGNAL_DISPLAY_PROCESSING
++//#define DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED "jeff-ap"
++
++//#define DBG_EXPIRATION_CHK
++
++
++//#define DBG_SHOW_MCUFWDL_BEFORE_51_ENABLE
++//#define DBG_ROAMING_TEST
++
++//#define DBG_HAL_INIT_PROFILING
++
++//#define DBG_MEMORY_LEAK 1
++
++#define DBG_CONFIG_ERROR_DETECT
++//#define DBG_CONFIG_ERROR_RESET
++
++//TX use 1 urb
++//#define CONFIG_SINGLE_XMIT_BUF
++//RX use 1 urb
++//#define CONFIG_SINGLE_RECV_BUF
++
++//turn off power tracking when traffic is busy
++//#define CONFIG_BUSY_TRAFFIC_SKIP_PWR_TRACK
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/basic_types.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/basic_types.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/basic_types.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/basic_types.h 2015-07-28 01:20:58.317611539 +0200
+@@ -0,0 +1,320 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef __BASIC_TYPES_H__
++#define __BASIC_TYPES_H__
++
++#include <drv_conf.h>
++
++
++#define SUCCESS 0
++#define FAIL (-1)
++
++#ifndef TRUE
++ #define _TRUE 1
++#else
++ #define _TRUE TRUE
++#endif
++
++#ifndef FALSE
++ #define _FALSE 0
++#else
++ #define _FALSE FALSE
++#endif
++
++#ifdef PLATFORM_WINDOWS
++
++ typedef signed char s8;
++ typedef unsigned char u8;
++
++ typedef signed short s16;
++ typedef unsigned short u16;
++
++ typedef signed long s32;
++ typedef unsigned long u32;
++
++ typedef unsigned int uint;
++ typedef signed int sint;
++
++
++ typedef signed long long s64;
++ typedef unsigned long long u64;
++
++ #ifdef NDIS50_MINIPORT
++
++ #define NDIS_MAJOR_VERSION 5
++ #define NDIS_MINOR_VERSION 0
++
++ #endif
++
++ #ifdef NDIS51_MINIPORT
++
++ #define NDIS_MAJOR_VERSION 5
++ #define NDIS_MINOR_VERSION 1
++
++ #endif
++
++ typedef NDIS_PROC proc_t;
++
++ typedef LONG atomic_t;
++
++#endif
++
++
++#ifdef PLATFORM_LINUX
++
++ #include <linux/types.h>
++ #define IN
++ #define OUT
++ #define VOID void
++ #define NDIS_OID uint
++ #define NDIS_STATUS uint
++
++ typedef signed int sint;
++
++ #ifndef PVOID
++ typedef void * PVOID;
++ //#define PVOID (void *)
++ #endif
++
++ #define UCHAR u8
++ #define USHORT u16
++ #define UINT u32
++ #define ULONG u32
++
++ typedef void (*proc_t)(void*);
++
++ typedef __kernel_size_t SIZE_T;
++ typedef __kernel_ssize_t SSIZE_T;
++ #define FIELD_OFFSET(s,field) ((SSIZE_T)&((s*)(0))->field)
++
++#endif
++
++
++#ifdef PLATFORM_FREEBSD
++
++ typedef signed char s8;
++ typedef unsigned char u8;
++
++ typedef signed short s16;
++ typedef unsigned short u16;
++
++ typedef signed int s32;
++ typedef unsigned int u32;
++
++ typedef unsigned int uint;
++ typedef signed int sint;
++ typedef long atomic_t;
++
++ typedef signed long long s64;
++ typedef unsigned long long u64;
++ #define IN
++ #define OUT
++ #define VOID void
++ #define NDIS_OID uint
++ #define NDIS_STATUS uint
++
++ #ifndef PVOID
++ typedef void * PVOID;
++ //#define PVOID (void *)
++ #endif
++ typedef u32 dma_addr_t;
++ #define UCHAR u8
++ #define USHORT u16
++ #define UINT u32
++ #define ULONG u32
++
++ typedef void (*proc_t)(void*);
++
++ typedef unsigned int __kernel_size_t;
++ typedef int __kernel_ssize_t;
++
++ typedef __kernel_size_t SIZE_T;
++ typedef __kernel_ssize_t SSIZE_T;
++ #define FIELD_OFFSET(s,field) ((SSIZE_T)&((s*)(0))->field)
++
++#endif
++
++#define MEM_ALIGNMENT_OFFSET (sizeof (SIZE_T))
++#define MEM_ALIGNMENT_PADDING (sizeof(SIZE_T) - 1)
++
++#define SIZE_PTR SIZE_T
++#define SSIZE_PTR SSIZE_T
++
++//port from fw by thomas
++// TODO: Belows are Sync from SD7-Driver. It is necessary to check correctness
++
++/*
++ * Call endian free function when
++ * 1. Read/write packet content.
++ * 2. Before write integer to IO.
++ * 3. After read integer from IO.
++*/
++
++//
++// Byte Swapping routine.
++//
++#define EF1Byte
++#define EF2Byte le16_to_cpu
++#define EF4Byte le32_to_cpu
++
++//
++// Read LE format data from memory
++//
++#define ReadEF1Byte(_ptr) EF1Byte(*((u8 *)(_ptr)))
++#define ReadEF2Byte(_ptr) EF2Byte(*((u16 *)(_ptr)))
++#define ReadEF4Byte(_ptr) EF4Byte(*((u32 *)(_ptr)))
++
++//
++// Write LE data to memory
++//
++#define WriteEF1Byte(_ptr, _val) (*((u8 *)(_ptr)))=EF1Byte(_val)
++#define WriteEF2Byte(_ptr, _val) (*((u16 *)(_ptr)))=EF2Byte(_val)
++#define WriteEF4Byte(_ptr, _val) (*((u32 *)(_ptr)))=EF4Byte(_val)
++
++//
++// Example:
++// BIT_LEN_MASK_32(0) => 0x00000000
++// BIT_LEN_MASK_32(1) => 0x00000001
++// BIT_LEN_MASK_32(2) => 0x00000003
++// BIT_LEN_MASK_32(32) => 0xFFFFFFFF
++//
++#define BIT_LEN_MASK_32(__BitLen) \
++ (0xFFFFFFFF >> (32 - (__BitLen)))
++//
++// Example:
++// BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003
++// BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000
++//
++#define BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen) \
++ (BIT_LEN_MASK_32(__BitLen) << (__BitOffset))
++
++//
++// Description:
++// Return 4-byte value in host byte ordering from
++// 4-byte pointer in litten-endian system.
++//
++#define LE_P4BYTE_TO_HOST_4BYTE(__pStart) \
++ (EF4Byte(*((u32 *)(__pStart))))
++
++//
++// Description:
++// Translate subfield (continuous bits in little-endian) of 4-byte value in litten byte to
++// 4-byte value in host byte ordering.
++//
++#define LE_BITS_TO_4BYTE(__pStart, __BitOffset, __BitLen) \
++ ( \
++ ( LE_P4BYTE_TO_HOST_4BYTE(__pStart) >> (__BitOffset) ) \
++ & \
++ BIT_LEN_MASK_32(__BitLen) \
++ )
++
++//
++// Description:
++// Mask subfield (continuous bits in little-endian) of 4-byte value in litten byte oredering
++// and return the result in 4-byte value in host byte ordering.
++//
++#define LE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \
++ ( \
++ LE_P4BYTE_TO_HOST_4BYTE(__pStart) \
++ & \
++ ( ~BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen) ) \
++ )
++
++//
++// Description:
++// Set subfield of little-endian 4-byte value to specified value.
++//
++#define SET_BITS_TO_LE_4BYTE(__pStart, __BitOffset, __BitLen, __Value) \
++ *((u32 *)(__pStart)) = \
++ EF4Byte( \
++ LE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \
++ | \
++ ( (((u32)__Value) & BIT_LEN_MASK_32(__BitLen)) << (__BitOffset) ) \
++ );
++
++
++#define BIT_LEN_MASK_16(__BitLen) \
++ (0xFFFF >> (16 - (__BitLen)))
++
++#define BIT_OFFSET_LEN_MASK_16(__BitOffset, __BitLen) \
++ (BIT_LEN_MASK_16(__BitLen) << (__BitOffset))
++
++#define LE_P2BYTE_TO_HOST_2BYTE(__pStart) \
++ (EF2Byte(*((u16 *)(__pStart))))
++
++#define LE_BITS_TO_2BYTE(__pStart, __BitOffset, __BitLen) \
++ ( \
++ ( LE_P2BYTE_TO_HOST_2BYTE(__pStart) >> (__BitOffset) ) \
++ & \
++ BIT_LEN_MASK_16(__BitLen) \
++ )
++
++#define LE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \
++ ( \
++ LE_P2BYTE_TO_HOST_2BYTE(__pStart) \
++ & \
++ ( ~BIT_OFFSET_LEN_MASK_16(__BitOffset, __BitLen) ) \
++ )
++
++#define SET_BITS_TO_LE_2BYTE(__pStart, __BitOffset, __BitLen, __Value) \
++ *((u16 *)(__pStart)) = \
++ EF2Byte( \
++ LE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \
++ | \
++ ( (((u16)__Value) & BIT_LEN_MASK_16(__BitLen)) << (__BitOffset) ) \
++ );
++
++#define BIT_LEN_MASK_8(__BitLen) \
++ (0xFF >> (8 - (__BitLen)))
++
++#define BIT_OFFSET_LEN_MASK_8(__BitOffset, __BitLen) \
++ (BIT_LEN_MASK_8(__BitLen) << (__BitOffset))
++
++#define LE_P1BYTE_TO_HOST_1BYTE(__pStart) \
++ (EF1Byte(*((u8 *)(__pStart))))
++
++#define LE_BITS_TO_1BYTE(__pStart, __BitOffset, __BitLen) \
++ ( \
++ ( LE_P1BYTE_TO_HOST_1BYTE(__pStart) >> (__BitOffset) ) \
++ & \
++ BIT_LEN_MASK_8(__BitLen) \
++ )
++
++#define LE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \
++ ( \
++ LE_P1BYTE_TO_HOST_1BYTE(__pStart) \
++ & \
++ ( ~BIT_OFFSET_LEN_MASK_8(__BitOffset, __BitLen) ) \
++ )
++
++#define SET_BITS_TO_LE_1BYTE(__pStart, __BitOffset, __BitLen, __Value) \
++ *((u8 *)(__pStart)) = \
++ EF1Byte( \
++ LE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \
++ | \
++ ( (((u8)__Value) & BIT_LEN_MASK_8(__BitLen)) << (__BitOffset) ) \
++ );
++
++// Get the N-bytes aligment offset from the current length
++#define N_BYTE_ALIGMENT(__Value, __Aligment) ((__Aligment == 1) ? (__Value) : (((__Value + __Aligment - 1) / __Aligment) * __Aligment))
++
++typedef unsigned char BOOLEAN,*PBOOLEAN;
++
++#endif //__BASIC_TYPES_H__
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/byteorder/big_endian.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/byteorder/big_endian.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/byteorder/big_endian.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/byteorder/big_endian.h 2015-07-28 01:20:58.317611539 +0200
+@@ -0,0 +1,87 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef _LINUX_BYTEORDER_BIG_ENDIAN_H
++#define _LINUX_BYTEORDER_BIG_ENDIAN_H
++
++#ifndef __BIG_ENDIAN
++#define __BIG_ENDIAN 4321
++#endif
++#ifndef __BIG_ENDIAN_BITFIELD
++#define __BIG_ENDIAN_BITFIELD
++#endif
++
++#include <byteorder/swab.h>
++
++#define __constant_htonl(x) ((__u32)(x))
++#define __constant_ntohl(x) ((__u32)(x))
++#define __constant_htons(x) ((__u16)(x))
++#define __constant_ntohs(x) ((__u16)(x))
++#define __constant_cpu_to_le64(x) ___constant_swab64((x))
++#define __constant_le64_to_cpu(x) ___constant_swab64((x))
++#define __constant_cpu_to_le32(x) ___constant_swab32((x))
++#define __constant_le32_to_cpu(x) ___constant_swab32((x))
++#define __constant_cpu_to_le16(x) ___constant_swab16((x))
++#define __constant_le16_to_cpu(x) ___constant_swab16((x))
++#define __constant_cpu_to_be64(x) ((__u64)(x))
++#define __constant_be64_to_cpu(x) ((__u64)(x))
++#define __constant_cpu_to_be32(x) ((__u32)(x))
++#define __constant_be32_to_cpu(x) ((__u32)(x))
++#define __constant_cpu_to_be16(x) ((__u16)(x))
++#define __constant_be16_to_cpu(x) ((__u16)(x))
++#define __cpu_to_le64(x) __swab64((x))
++#define __le64_to_cpu(x) __swab64((x))
++#define __cpu_to_le32(x) __swab32((x))
++#define __le32_to_cpu(x) __swab32((x))
++#define __cpu_to_le16(x) __swab16((x))
++#define __le16_to_cpu(x) __swab16((x))
++#define __cpu_to_be64(x) ((__u64)(x))
++#define __be64_to_cpu(x) ((__u64)(x))
++#define __cpu_to_be32(x) ((__u32)(x))
++#define __be32_to_cpu(x) ((__u32)(x))
++#define __cpu_to_be16(x) ((__u16)(x))
++#define __be16_to_cpu(x) ((__u16)(x))
++#define __cpu_to_le64p(x) __swab64p((x))
++#define __le64_to_cpup(x) __swab64p((x))
++#define __cpu_to_le32p(x) __swab32p((x))
++#define __le32_to_cpup(x) __swab32p((x))
++#define __cpu_to_le16p(x) __swab16p((x))
++#define __le16_to_cpup(x) __swab16p((x))
++#define __cpu_to_be64p(x) (*(__u64*)(x))
++#define __be64_to_cpup(x) (*(__u64*)(x))
++#define __cpu_to_be32p(x) (*(__u32*)(x))
++#define __be32_to_cpup(x) (*(__u32*)(x))
++#define __cpu_to_be16p(x) (*(__u16*)(x))
++#define __be16_to_cpup(x) (*(__u16*)(x))
++#define __cpu_to_le64s(x) __swab64s((x))
++#define __le64_to_cpus(x) __swab64s((x))
++#define __cpu_to_le32s(x) __swab32s((x))
++#define __le32_to_cpus(x) __swab32s((x))
++#define __cpu_to_le16s(x) __swab16s((x))
++#define __le16_to_cpus(x) __swab16s((x))
++#define __cpu_to_be64s(x) do {} while (0)
++#define __be64_to_cpus(x) do {} while (0)
++#define __cpu_to_be32s(x) do {} while (0)
++#define __be32_to_cpus(x) do {} while (0)
++#define __cpu_to_be16s(x) do {} while (0)
++#define __be16_to_cpus(x) do {} while (0)
++
++#include <byteorder/generic.h>
++
++#endif /* _LINUX_BYTEORDER_BIG_ENDIAN_H */
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/byteorder/generic.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/byteorder/generic.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/byteorder/generic.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/byteorder/generic.h 2015-07-28 01:20:58.317611539 +0200
+@@ -0,0 +1,212 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef _LINUX_BYTEORDER_GENERIC_H
++#define _LINUX_BYTEORDER_GENERIC_H
++
++/*
++ * linux/byteorder_generic.h
++ * Generic Byte-reordering support
++ *
++ * Francois-Rene Rideau <fare@tunes.org> 19970707
++ * gathered all the good ideas from all asm-foo/byteorder.h into one file,
++ * cleaned them up.
++ * I hope it is compliant with non-GCC compilers.
++ * I decided to put __BYTEORDER_HAS_U64__ in byteorder.h,
++ * because I wasn't sure it would be ok to put it in types.h
++ * Upgraded it to 2.1.43
++ * Francois-Rene Rideau <fare@tunes.org> 19971012
++ * Upgraded it to 2.1.57
++ * to please Linus T., replaced huge #ifdef's between little/big endian
++ * by nestedly #include'd files.
++ * Francois-Rene Rideau <fare@tunes.org> 19971205
++ * Made it to 2.1.71; now a facelift:
++ * Put files under include/linux/byteorder/
++ * Split swab from generic support.
++ *
++ * TODO:
++ * = Regular kernel maintainers could also replace all these manual
++ * byteswap macros that remain, disseminated among drivers,
++ * after some grep or the sources...
++ * = Linus might want to rename all these macros and files to fit his taste,
++ * to fit his personal naming scheme.
++ * = it seems that a few drivers would also appreciate
++ * nybble swapping support...
++ * = every architecture could add their byteswap macro in asm/byteorder.h
++ * see how some architectures already do (i386, alpha, ppc, etc)
++ * = cpu_to_beXX and beXX_to_cpu might some day need to be well
++ * distinguished throughout the kernel. This is not the case currently,
++ * since little endian, big endian, and pdp endian machines needn't it.
++ * But this might be the case for, say, a port of Linux to 20/21 bit
++ * architectures (and F21 Linux addict around?).
++ */
++
++/*
++ * The following macros are to be defined by <asm/byteorder.h>:
++ *
++ * Conversion of long and short int between network and host format
++ * ntohl(__u32 x)
++ * ntohs(__u16 x)
++ * htonl(__u32 x)
++ * htons(__u16 x)
++ * It seems that some programs (which? where? or perhaps a standard? POSIX?)
++ * might like the above to be functions, not macros (why?).
++ * if that's true, then detect them, and take measures.
++ * Anyway, the measure is: define only ___ntohl as a macro instead,
++ * and in a separate file, have
++ * unsigned long inline ntohl(x){return ___ntohl(x);}
++ *
++ * The same for constant arguments
++ * __constant_ntohl(__u32 x)
++ * __constant_ntohs(__u16 x)
++ * __constant_htonl(__u32 x)
++ * __constant_htons(__u16 x)
++ *
++ * Conversion of XX-bit integers (16- 32- or 64-)
++ * between native CPU format and little/big endian format
++ * 64-bit stuff only defined for proper architectures
++ * cpu_to_[bl]eXX(__uXX x)
++ * [bl]eXX_to_cpu(__uXX x)
++ *
++ * The same, but takes a pointer to the value to convert
++ * cpu_to_[bl]eXXp(__uXX x)
++ * [bl]eXX_to_cpup(__uXX x)
++ *
++ * The same, but change in situ
++ * cpu_to_[bl]eXXs(__uXX x)
++ * [bl]eXX_to_cpus(__uXX x)
++ *
++ * See asm-foo/byteorder.h for examples of how to provide
++ * architecture-optimized versions
++ *
++ */
++
++
++#if defined(PLATFORM_LINUX) || defined(PLATFORM_WINDOWS) || defined(PLATFORM_MPIXEL) || defined(PLATFORM_FREEBSD)
++/*
++ * inside the kernel, we can use nicknames;
++ * outside of it, we must avoid POSIX namespace pollution...
++ */
++#define cpu_to_le64 __cpu_to_le64
++#define le64_to_cpu __le64_to_cpu
++#define cpu_to_le32 __cpu_to_le32
++#define le32_to_cpu __le32_to_cpu
++#define cpu_to_le16 __cpu_to_le16
++#define le16_to_cpu __le16_to_cpu
++#define cpu_to_be64 __cpu_to_be64
++#define be64_to_cpu __be64_to_cpu
++#define cpu_to_be32 __cpu_to_be32
++#define be32_to_cpu __be32_to_cpu
++#define cpu_to_be16 __cpu_to_be16
++#define be16_to_cpu __be16_to_cpu
++#define cpu_to_le64p __cpu_to_le64p
++#define le64_to_cpup __le64_to_cpup
++#define cpu_to_le32p __cpu_to_le32p
++#define le32_to_cpup __le32_to_cpup
++#define cpu_to_le16p __cpu_to_le16p
++#define le16_to_cpup __le16_to_cpup
++#define cpu_to_be64p __cpu_to_be64p
++#define be64_to_cpup __be64_to_cpup
++#define cpu_to_be32p __cpu_to_be32p
++#define be32_to_cpup __be32_to_cpup
++#define cpu_to_be16p __cpu_to_be16p
++#define be16_to_cpup __be16_to_cpup
++#define cpu_to_le64s __cpu_to_le64s
++#define le64_to_cpus __le64_to_cpus
++#define cpu_to_le32s __cpu_to_le32s
++#define le32_to_cpus __le32_to_cpus
++#define cpu_to_le16s __cpu_to_le16s
++#define le16_to_cpus __le16_to_cpus
++#define cpu_to_be64s __cpu_to_be64s
++#define be64_to_cpus __be64_to_cpus
++#define cpu_to_be32s __cpu_to_be32s
++#define be32_to_cpus __be32_to_cpus
++#define cpu_to_be16s __cpu_to_be16s
++#define be16_to_cpus __be16_to_cpus
++#endif
++
++
++/*
++ * Handle ntohl and suches. These have various compatibility
++ * issues - like we want to give the prototype even though we
++ * also have a macro for them in case some strange program
++ * wants to take the address of the thing or something..
++ *
++ * Note that these used to return a "long" in libc5, even though
++ * long is often 64-bit these days.. Thus the casts.
++ *
++ * They have to be macros in order to do the constant folding
++ * correctly - if the argument passed into a inline function
++ * it is no longer constant according to gcc..
++ */
++
++#undef ntohl
++#undef ntohs
++#undef htonl
++#undef htons
++
++/*
++ * Do the prototypes. Somebody might want to take the
++ * address or some such sick thing..
++ */
++#if defined(PLATFORM_LINUX) || (defined (__GLIBC__) && __GLIBC__ >= 2)
++extern __u32 ntohl(__u32);
++extern __u32 htonl(__u32);
++#else //defined(PLATFORM_LINUX) || (defined (__GLIBC__) && __GLIBC__ >= 2)
++#ifndef PLATFORM_FREEBSD
++extern unsigned long int ntohl(unsigned long int);
++extern unsigned long int htonl(unsigned long int);
++#endif
++#endif
++#ifndef PLATFORM_FREEBSD
++extern unsigned short int ntohs(unsigned short int);
++extern unsigned short int htons(unsigned short int);
++#endif
++
++#if defined(__GNUC__) && (__GNUC__ >= 2) && defined(__OPTIMIZE__) || defined(PLATFORM_MPIXEL)
++
++#define ___htonl(x) __cpu_to_be32(x)
++#define ___htons(x) __cpu_to_be16(x)
++#define ___ntohl(x) __be32_to_cpu(x)
++#define ___ntohs(x) __be16_to_cpu(x)
++
++#if defined(PLATFORM_LINUX) || (defined (__GLIBC__) && __GLIBC__ >= 2)
++#define htonl(x) ___htonl(x)
++#define ntohl(x) ___ntohl(x)
++#else
++#define htonl(x) ((unsigned long)___htonl(x))
++#define ntohl(x) ((unsigned long)___ntohl(x))
++#endif
++#define htons(x) ___htons(x)
++#define ntohs(x) ___ntohs(x)
++
++#endif /* OPTIMIZE */
++
++
++#if defined (PLATFORM_WINDOWS)
++
++#define htonl(x) __cpu_to_be32(x)
++#define ntohl(x) __be32_to_cpu(x)
++#define htons(x) __cpu_to_be16(x)
++#define ntohs(x) __be16_to_cpu(x)
++
++
++#endif
++
++#endif /* _LINUX_BYTEORDER_GENERIC_H */
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/byteorder/little_endian.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/byteorder/little_endian.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/byteorder/little_endian.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/byteorder/little_endian.h 2015-07-28 01:20:58.317611539 +0200
+@@ -0,0 +1,89 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef _LINUX_BYTEORDER_LITTLE_ENDIAN_H
++#define _LINUX_BYTEORDER_LITTLE_ENDIAN_H
++
++#ifndef __LITTLE_ENDIAN
++#define __LITTLE_ENDIAN 1234
++#endif
++#ifndef __LITTLE_ENDIAN_BITFIELD
++#define __LITTLE_ENDIAN_BITFIELD
++#endif
++
++#include <byteorder/swab.h>
++
++#ifndef __constant_htonl
++#define __constant_htonl(x) ___constant_swab32((x))
++#define __constant_ntohl(x) ___constant_swab32((x))
++#define __constant_htons(x) ___constant_swab16((x))
++#define __constant_ntohs(x) ___constant_swab16((x))
++#define __constant_cpu_to_le64(x) ((__u64)(x))
++#define __constant_le64_to_cpu(x) ((__u64)(x))
++#define __constant_cpu_to_le32(x) ((__u32)(x))
++#define __constant_le32_to_cpu(x) ((__u32)(x))
++#define __constant_cpu_to_le16(x) ((__u16)(x))
++#define __constant_le16_to_cpu(x) ((__u16)(x))
++#define __constant_cpu_to_be64(x) ___constant_swab64((x))
++#define __constant_be64_to_cpu(x) ___constant_swab64((x))
++#define __constant_cpu_to_be32(x) ___constant_swab32((x))
++#define __constant_be32_to_cpu(x) ___constant_swab32((x))
++#define __constant_cpu_to_be16(x) ___constant_swab16((x))
++#define __constant_be16_to_cpu(x) ___constant_swab16((x))
++#define __cpu_to_le64(x) ((__u64)(x))
++#define __le64_to_cpu(x) ((__u64)(x))
++#define __cpu_to_le32(x) ((__u32)(x))
++#define __le32_to_cpu(x) ((__u32)(x))
++#define __cpu_to_le16(x) ((__u16)(x))
++#define __le16_to_cpu(x) ((__u16)(x))
++#define __cpu_to_be64(x) __swab64((x))
++#define __be64_to_cpu(x) __swab64((x))
++#define __cpu_to_be32(x) __swab32((x))
++#define __be32_to_cpu(x) __swab32((x))
++#define __cpu_to_be16(x) __swab16((x))
++#define __be16_to_cpu(x) __swab16((x))
++#define __cpu_to_le64p(x) (*(__u64*)(x))
++#define __le64_to_cpup(x) (*(__u64*)(x))
++#define __cpu_to_le32p(x) (*(__u32*)(x))
++#define __le32_to_cpup(x) (*(__u32*)(x))
++#define __cpu_to_le16p(x) (*(__u16*)(x))
++#define __le16_to_cpup(x) (*(__u16*)(x))
++#define __cpu_to_be64p(x) __swab64p((x))
++#define __be64_to_cpup(x) __swab64p((x))
++#define __cpu_to_be32p(x) __swab32p((x))
++#define __be32_to_cpup(x) __swab32p((x))
++#define __cpu_to_be16p(x) __swab16p((x))
++#define __be16_to_cpup(x) __swab16p((x))
++#define __cpu_to_le64s(x) do {} while (0)
++#define __le64_to_cpus(x) do {} while (0)
++#define __cpu_to_le32s(x) do {} while (0)
++#define __le32_to_cpus(x) do {} while (0)
++#define __cpu_to_le16s(x) do {} while (0)
++#define __le16_to_cpus(x) do {} while (0)
++#define __cpu_to_be64s(x) __swab64s((x))
++#define __be64_to_cpus(x) __swab64s((x))
++#define __cpu_to_be32s(x) __swab32s((x))
++#define __be32_to_cpus(x) __swab32s((x))
++#define __cpu_to_be16s(x) __swab16s((x))
++#define __be16_to_cpus(x) __swab16s((x))
++#endif // __constant_htonl
++
++#include <byteorder/generic.h>
++
++#endif /* _LINUX_BYTEORDER_LITTLE_ENDIAN_H */
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/byteorder/swabb.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/byteorder/swabb.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/byteorder/swabb.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/byteorder/swabb.h 2015-07-28 01:20:58.317611539 +0200
+@@ -0,0 +1,156 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef _LINUX_BYTEORDER_SWABB_H
++#define _LINUX_BYTEORDER_SWABB_H
++
++/*
++ * linux/byteorder/swabb.h
++ * SWAp Bytes Bizarrely
++ * swaHHXX[ps]?(foo)
++ *
++ * Support for obNUXIous pdp-endian and other bizarre architectures.
++ * Will Linux ever run on such ancient beasts? if not, this file
++ * will be but a programming pearl. Still, it's a reminder that we
++ * shouldn't be making too many assumptions when trying to be portable.
++ *
++ */
++
++/*
++ * Meaning of the names I chose (vaxlinux people feel free to correct them):
++ * swahw32 swap 16-bit half-words in a 32-bit word
++ * swahb32 swap 8-bit halves of each 16-bit half-word in a 32-bit word
++ *
++ * No 64-bit support yet. I don't know NUXI conventions for long longs.
++ * I guarantee it will be a mess when it's there, though :->
++ * It will be even worse if there are conflicting 64-bit conventions.
++ * Hopefully, no one ever used 64-bit objects on NUXI machines.
++ *
++ */
++
++#define ___swahw32(x) \
++({ \
++ __u32 __x = (x); \
++ ((__u32)( \
++ (((__u32)(__x) & (__u32)0x0000ffffUL) << 16) | \
++ (((__u32)(__x) & (__u32)0xffff0000UL) >> 16) )); \
++})
++#define ___swahb32(x) \
++({ \
++ __u32 __x = (x); \
++ ((__u32)( \
++ (((__u32)(__x) & (__u32)0x00ff00ffUL) << 8) | \
++ (((__u32)(__x) & (__u32)0xff00ff00UL) >> 8) )); \
++})
++
++#define ___constant_swahw32(x) \
++ ((__u32)( \
++ (((__u32)(x) & (__u32)0x0000ffffUL) << 16) | \
++ (((__u32)(x) & (__u32)0xffff0000UL) >> 16) ))
++#define ___constant_swahb32(x) \
++ ((__u32)( \
++ (((__u32)(x) & (__u32)0x00ff00ffUL) << 8) | \
++ (((__u32)(x) & (__u32)0xff00ff00UL) >> 8) ))
++
++/*
++ * provide defaults when no architecture-specific optimization is detected
++ */
++#ifndef __arch__swahw32
++# define __arch__swahw32(x) ___swahw32(x)
++#endif
++#ifndef __arch__swahb32
++# define __arch__swahb32(x) ___swahb32(x)
++#endif
++
++#ifndef __arch__swahw32p
++# define __arch__swahw32p(x) __swahw32(*(x))
++#endif
++#ifndef __arch__swahb32p
++# define __arch__swahb32p(x) __swahb32(*(x))
++#endif
++
++#ifndef __arch__swahw32s
++# define __arch__swahw32s(x) do { *(x) = __swahw32p((x)); } while (0)
++#endif
++#ifndef __arch__swahb32s
++# define __arch__swahb32s(x) do { *(x) = __swahb32p((x)); } while (0)
++#endif
++
++
++/*
++ * Allow constant folding
++ */
++#if defined(__GNUC__) && (__GNUC__ >= 2) && defined(__OPTIMIZE__)
++# define __swahw32(x) \
++(__builtin_constant_p((__u32)(x)) ? \
++ ___swahw32((x)) : \
++ __fswahw32((x)))
++# define __swahb32(x) \
++(__builtin_constant_p((__u32)(x)) ? \
++ ___swahb32((x)) : \
++ __fswahb32((x)))
++#else
++# define __swahw32(x) __fswahw32(x)
++# define __swahb32(x) __fswahb32(x)
++#endif /* OPTIMIZE */
++
++
++__inline static__ __const__ __u32 __fswahw32(__u32 x)
++{
++ return __arch__swahw32(x);
++}
++__inline static__ __u32 __swahw32p(__u32 *x)
++{
++ return __arch__swahw32p(x);
++}
++__inline static__ void __swahw32s(__u32 *addr)
++{
++ __arch__swahw32s(addr);
++}
++
++
++__inline static__ __const__ __u32 __fswahb32(__u32 x)
++{
++ return __arch__swahb32(x);
++}
++__inline static__ __u32 __swahb32p(__u32 *x)
++{
++ return __arch__swahb32p(x);
++}
++__inline static__ void __swahb32s(__u32 *addr)
++{
++ __arch__swahb32s(addr);
++}
++
++#ifdef __BYTEORDER_HAS_U64__
++/*
++ * Not supported yet
++ */
++#endif /* __BYTEORDER_HAS_U64__ */
++
++#if defined(PLATFORM_LINUX)
++#define swahw32 __swahw32
++#define swahb32 __swahb32
++#define swahw32p __swahw32p
++#define swahb32p __swahb32p
++#define swahw32s __swahw32s
++#define swahb32s __swahb32s
++#endif
++
++#endif /* _LINUX_BYTEORDER_SWABB_H */
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/byteorder/swab.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/byteorder/swab.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/byteorder/swab.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/byteorder/swab.h 2015-07-28 01:20:58.317611539 +0200
+@@ -0,0 +1,140 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef _LINUX_BYTEORDER_SWAB_H
++#define _LINUX_BYTEORDER_SWAB_H
++
++#if !defined(CONFIG_PLATFORM_MSTAR)
++#ifndef __u16
++typedef unsigned short __u16;
++#endif
++
++#ifndef __u32
++typedef unsigned int __u32;
++#endif
++
++#ifndef __u8
++typedef unsigned char __u8;
++#endif
++
++#ifndef __u64
++typedef unsigned long long __u64;
++#endif
++
++
++__inline static __u16 ___swab16(__u16 x)
++{
++ __u16 __x = x;
++ return
++ ((__u16)(
++ (((__u16)(__x) & (__u16)0x00ffU) << 8) |
++ (((__u16)(__x) & (__u16)0xff00U) >> 8) ));
++
++}
++
++__inline static __u32 ___swab32(__u32 x)
++{
++ __u32 __x = (x);
++ return ((__u32)(
++ (((__u32)(__x) & (__u32)0x000000ffUL) << 24) |
++ (((__u32)(__x) & (__u32)0x0000ff00UL) << 8) |
++ (((__u32)(__x) & (__u32)0x00ff0000UL) >> 8) |
++ (((__u32)(__x) & (__u32)0xff000000UL) >> 24) ));
++}
++
++__inline static __u64 ___swab64(__u64 x)
++{
++ __u64 __x = (x);
++
++ return
++ ((__u64)( \
++ (__u64)(((__u64)(__x) & (__u64)0x00000000000000ffULL) << 56) | \
++ (__u64)(((__u64)(__x) & (__u64)0x000000000000ff00ULL) << 40) | \
++ (__u64)(((__u64)(__x) & (__u64)0x0000000000ff0000ULL) << 24) | \
++ (__u64)(((__u64)(__x) & (__u64)0x00000000ff000000ULL) << 8) | \
++ (__u64)(((__u64)(__x) & (__u64)0x000000ff00000000ULL) >> 8) | \
++ (__u64)(((__u64)(__x) & (__u64)0x0000ff0000000000ULL) >> 24) | \
++ (__u64)(((__u64)(__x) & (__u64)0x00ff000000000000ULL) >> 40) | \
++ (__u64)(((__u64)(__x) & (__u64)0xff00000000000000ULL) >> 56) )); \
++}
++#endif // CONFIG_PLATFORM_MSTAR
++
++#ifndef __arch__swab16
++__inline static __u16 __arch__swab16(__u16 x)
++{
++ return ___swab16(x);
++}
++
++#endif
++
++#ifndef __arch__swab32
++__inline static __u32 __arch__swab32(__u32 x)
++{
++ __u32 __tmp = (x) ;
++ return ___swab32(__tmp);
++}
++#endif
++
++#ifndef __arch__swab64
++
++__inline static __u64 __arch__swab64(__u64 x)
++{
++ __u64 __tmp = (x) ;
++ return ___swab64(__tmp);
++}
++
++
++#endif
++
++#ifndef __swab16
++#define __swab16(x) __fswab16(x)
++#define __swab32(x) __fswab32(x)
++#define __swab64(x) __fswab64(x)
++#endif // __swab16
++
++#ifdef PLATFORM_FREEBSD
++__inline static __u16 __fswab16(__u16 x)
++#else
++__inline static const __u16 __fswab16(__u16 x)
++#endif //PLATFORM_FREEBSD
++{
++ return __arch__swab16(x);
++}
++#ifdef PLATFORM_FREEBSD
++__inline static __u32 __fswab32(__u32 x)
++#else
++__inline static const __u32 __fswab32(__u32 x)
++#endif //PLATFORM_FREEBSD
++{
++ return __arch__swab32(x);
++}
++
++#if defined(PLATFORM_LINUX) || defined(PLATFORM_WINDOWS)
++#define swab16 __swab16
++#define swab32 __swab32
++#define swab64 __swab64
++#define swab16p __swab16p
++#define swab32p __swab32p
++#define swab64p __swab64p
++#define swab16s __swab16s
++#define swab32s __swab32s
++#define swab64s __swab64s
++#endif
++
++#endif /* _LINUX_BYTEORDER_SWAB_H */
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/circ_buf.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/circ_buf.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/circ_buf.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/circ_buf.h 2015-07-28 01:20:58.317611539 +0200
+@@ -0,0 +1,27 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef __CIRC_BUF_H_
++#define __CIRC_BUF_H_ 1
++
++#define CIRC_CNT(head,tail,size) (((head) - (tail)) & ((size)-1))
++
++#define CIRC_SPACE(head,tail,size) CIRC_CNT((tail),((head)+1),(size))
++
++#endif //_CIRC_BUF_H_
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/cmd_osdep.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/cmd_osdep.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/cmd_osdep.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/cmd_osdep.h 2015-07-28 01:20:58.317611539 +0200
+@@ -0,0 +1,35 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef __CMD_OSDEP_H_
++#define __CMD_OSDEP_H_
++
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++
++extern sint _rtw_init_cmd_priv (struct cmd_priv *pcmdpriv);
++extern sint _rtw_init_evt_priv(struct evt_priv *pevtpriv);
++extern void _rtw_free_evt_priv (struct evt_priv *pevtpriv);
++extern void _rtw_free_cmd_priv (struct cmd_priv *pcmdpriv);
++extern sint _rtw_enqueue_cmd(_queue *queue, struct cmd_obj *obj);
++extern struct cmd_obj *_rtw_dequeue_cmd(_queue *queue);
++
++#endif
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/drv_conf.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/drv_conf.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/drv_conf.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/drv_conf.h 2015-07-28 01:20:58.317611539 +0200
+@@ -0,0 +1,77 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef __DRV_CONF_H__
++#define __DRV_CONF_H__
++#include "autoconf.h"
++
++#if defined (PLATFORM_LINUX) && defined (PLATFORM_WINDOWS)
++
++#error "Shall be Linux or Windows, but not both!\n"
++
++#endif
++
++//Older Android kernel doesn't has CONFIG_ANDROID defined,
++//add this to force CONFIG_ANDROID defined
++#ifdef CONFIG_PLATFORM_ANDROID
++#define CONFIG_ANDROID
++#endif
++
++#ifdef CONFIG_ANDROID
++//Some Android build will restart the UI while non-printable ascii is passed
++//between java and c/c++ layer (JNI). We force CONFIG_VALIDATE_SSID
++//for Android here. If you are sure there is no risk on your system about this,
++//mask this macro define to support non-printable ascii ssid.
++//#define CONFIG_VALIDATE_SSID
++
++//Android expect dbm as the rx signal strength unit
++#define CONFIG_SIGNAL_DISPLAY_DBM
++#endif
++
++#if defined(CONFIG_HAS_EARLYSUSPEND) && defined (CONFIG_RESUME_IN_WORKQUEUE)
++ #warning "You have CONFIG_HAS_EARLYSUSPEND enabled in your system, we disable CONFIG_RESUME_IN_WORKQUEUE automatically"
++ #undef CONFIG_RESUME_IN_WORKQUEUE
++#endif
++
++#if defined(CONFIG_ANDROID_POWER) && defined (CONFIG_RESUME_IN_WORKQUEUE)
++ #warning "You have CONFIG_ANDROID_POWER enabled in your system, we disable CONFIG_RESUME_IN_WORKQUEUE automatically"
++ #undef CONFIG_RESUME_IN_WORKQUEUE
++#endif
++
++#ifdef CONFIG_RESUME_IN_WORKQUEUE //this can be removed, because there is no case for this...
++ #if !defined( CONFIG_WAKELOCK) && !defined(CONFIG_ANDROID_POWER)
++ #error "enable CONFIG_RESUME_IN_WORKQUEUE without CONFIG_WAKELOCK or CONFIG_ANDROID_POWER will suffer from the danger of wifi's unfunctionality..."
++ #error "If you still want to enable CONFIG_RESUME_IN_WORKQUEUE in this case, mask this preprossor checking and GOOD LUCK..."
++ #endif
++#endif
++
++//About USB VENDOR REQ
++#if defined(CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC) && !defined(CONFIG_USB_VENDOR_REQ_MUTEX)
++ #warning "define CONFIG_USB_VENDOR_REQ_MUTEX for CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC automatically"
++ #define CONFIG_USB_VENDOR_REQ_MUTEX
++#endif
++#if defined(CONFIG_VENDOR_REQ_RETRY) && !defined(CONFIG_USB_VENDOR_REQ_MUTEX)
++ #warning "define CONFIG_USB_VENDOR_REQ_MUTEX for CONFIG_VENDOR_REQ_RETRY automatically"
++ #define CONFIG_USB_VENDOR_REQ_MUTEX
++#endif
++
++
++//#include <rtl871x_byteorder.h>
++
++#endif // __DRV_CONF_H__
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/drv_types_ce.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/drv_types_ce.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/drv_types_ce.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/drv_types_ce.h 2015-07-28 01:20:58.317611539 +0200
+@@ -0,0 +1,92 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef __DRV_TYPES_CE_H__
++#define __DRV_TYPES_CE_H__
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++
++#include <Sdcardddk.h>
++
++#define MAX_ACTIVE_REG_PATH 256
++
++#define MAX_MCAST_LIST_NUM 32
++
++
++
++//for ioctl
++#define MAKE_DRIVER_VERSION(_MainVer,_MinorVer) ((((u32)(_MainVer))<<16)+_MinorVer)
++
++#define NIC_HEADER_SIZE 14 //!< can be moved to typedef.h
++#define NIC_MAX_PACKET_SIZE 1514 //!< can be moved to typedef.h
++#define NIC_MAX_SEND_PACKETS 10 // max number of send packets the MiniportSendPackets function can accept, can be moved to typedef.h
++#define NIC_VENDOR_DRIVER_VERSION MAKE_DRIVER_VERSION(0,001) //!< can be moved to typedef.h
++#define NIC_MAX_PACKET_SIZE 1514 //!< can be moved to typedef.h
++
++typedef struct _MP_REG_ENTRY
++{
++
++ NDIS_STRING RegName; // variable name text
++ BOOLEAN bRequired; // 1 -> required, 0 -> optional
++
++ u8 Type; // NdisParameterInteger/NdisParameterHexInteger/NdisParameterStringle/NdisParameterMultiString
++ uint FieldOffset; // offset to MP_ADAPTER field
++ uint FieldSize; // size (in bytes) of the field
++
++#ifdef UNDER_AMD64
++ u64 Default;
++#else
++ u32 Default; // default value to use
++#endif
++
++ u32 Min; // minimum value allowed
++ u32 Max; // maximum value allowed
++} MP_REG_ENTRY, *PMP_REG_ENTRY;
++
++#ifdef CONFIG_USB_HCI
++typedef struct _USB_EXTENSION {
++ LPCUSB_FUNCS _lpUsbFuncs;
++ USB_HANDLE _hDevice;
++ PVOID pAdapter;
++
++#if 0
++ USB_ENDPOINT_DESCRIPTOR _endpACLIn;
++ USB_ENDPOINT_DESCRIPTOR _endpACLOutHigh;
++ USB_ENDPOINT_DESCRIPTOR _endpACLOutNormal;
++
++ USB_PIPE pPipeIn;
++ USB_PIPE pPipeOutNormal;
++ USB_PIPE pPipeOutHigh;
++#endif
++
++} USB_EXTENSION, *PUSB_EXTENSION;
++#endif
++
++
++typedef struct _OCTET_STRING{
++ u8 *Octet;
++ u16 Length;
++} OCTET_STRING, *POCTET_STRING;
++
++
++
++
++
++#endif
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/drv_types.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/drv_types.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/drv_types.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/drv_types.h 2015-07-28 01:20:58.317611539 +0200
+@@ -0,0 +1,661 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++/*-------------------------------------------------------------------------------
++
++ For type defines and data structure defines
++
++--------------------------------------------------------------------------------*/
++
++
++#ifndef __DRV_TYPES_H__
++#define __DRV_TYPES_H__
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <wlan_bssdef.h>
++
++
++#ifdef PLATFORM_OS_XP
++#include <drv_types_xp.h>
++#endif
++
++#ifdef PLATFORM_OS_CE
++#include <drv_types_ce.h>
++#endif
++
++#ifdef PLATFORM_LINUX
++#include <drv_types_linux.h>
++#endif
++
++enum _NIC_VERSION {
++
++ RTL8711_NIC,
++ RTL8712_NIC,
++ RTL8713_NIC,
++ RTL8716_NIC
++
++};
++
++enum{
++ UP_LINK,
++ DOWN_LINK,
++};
++typedef struct _ADAPTER _adapter, ADAPTER,*PADAPTER;
++
++#ifdef CONFIG_80211N_HT
++#include <rtw_ht.h>
++#endif
++
++#include <rtw_cmd.h>
++#include <wlan_bssdef.h>
++#include <rtw_security.h>
++#include <rtw_xmit.h>
++#include <rtw_recv.h>
++#include <hal_intf.h>
++#include <hal_com.h>
++#include <rtw_qos.h>
++#include <rtw_pwrctrl.h>
++#include <rtw_io.h>
++#include <rtw_eeprom.h>
++#include <sta_info.h>
++#include <rtw_mlme.h>
++#include <rtw_debug.h>
++#include <rtw_rf.h>
++#include <rtw_event.h>
++#include <rtw_led.h>
++#include <rtw_mlme_ext.h>
++#include <rtw_p2p.h>
++#include <rtw_tdls.h>
++#include <rtw_ap.h>
++
++#ifdef CONFIG_DRVEXT_MODULE
++#include <drvext_api.h>
++#endif
++
++#ifdef CONFIG_MP_INCLUDED
++#include <rtw_mp.h>
++#endif
++
++#ifdef CONFIG_BR_EXT
++#include <rtw_br_ext.h>
++#endif // CONFIG_BR_EXT
++
++#ifdef CONFIG_IOCTL_CFG80211
++ #include "ioctl_cfg80211.h"
++#endif //CONFIG_IOCTL_CFG80211
++
++#define SPEC_DEV_ID_NONE BIT(0)
++#define SPEC_DEV_ID_DISABLE_HT BIT(1)
++#define SPEC_DEV_ID_ENABLE_PS BIT(2)
++#define SPEC_DEV_ID_RF_CONFIG_1T1R BIT(3)
++#define SPEC_DEV_ID_RF_CONFIG_2T2R BIT(4)
++#define SPEC_DEV_ID_ASSIGN_IFNAME BIT(5)
++
++struct specific_device_id{
++
++ u32 flags;
++
++ u16 idVendor;
++ u16 idProduct;
++
++};
++
++struct registry_priv
++{
++ u8 chip_version;
++ u8 rfintfs;
++ u8 lbkmode;
++ u8 hci;
++ NDIS_802_11_SSID ssid;
++ u8 network_mode; //infra, ad-hoc, auto
++ u8 channel;//ad-hoc support requirement
++ u8 wireless_mode;//A, B, G, auto
++ u8 scan_mode;//active, passive
++ u8 radio_enable;
++ u8 preamble;//long, short, auto
++ u8 vrtl_carrier_sense;//Enable, Disable, Auto
++ u8 vcs_type;//RTS/CTS, CTS-to-self
++ u16 rts_thresh;
++ u16 frag_thresh;
++ u8 adhoc_tx_pwr;
++ u8 soft_ap;
++ u8 power_mgnt;
++ u8 ips_mode;
++ u8 smart_ps;
++ u8 long_retry_lmt;
++ u8 short_retry_lmt;
++ u16 busy_thresh;
++ u8 ack_policy;
++ u8 mp_mode;
++ u8 software_encrypt;
++ u8 software_decrypt;
++
++ u8 acm_method;
++ //UAPSD
++ u8 wmm_enable;
++ u8 uapsd_enable;
++ u8 uapsd_max_sp;
++ u8 uapsd_acbk_en;
++ u8 uapsd_acbe_en;
++ u8 uapsd_acvi_en;
++ u8 uapsd_acvo_en;
++
++ WLAN_BSSID_EX dev_network;
++
++#ifdef CONFIG_80211N_HT
++ u8 ht_enable;
++ u8 cbw40_enable;
++ u8 ampdu_enable;//for tx
++ u8 rx_stbc;
++ u8 ampdu_amsdu;//A-MPDU Supports A-MSDU is permitted
++#endif
++ u8 lowrate_two_xmit;
++
++ u8 rf_config ;
++ u8 low_power ;
++
++ u8 wifi_spec;// !turbo_mode
++
++ u8 channel_plan;
++#ifdef CONFIG_BT_COEXIST
++ u8 bt_iso;
++ u8 bt_sco;
++ u8 bt_ampdu;
++#endif
++ BOOLEAN bAcceptAddbaReq;
++
++ u8 antdiv_cfg;
++
++ u8 usbss_enable;//0:disable,1:enable
++ u8 hwpdn_mode;//0:disable,1:enable,2:decide by EFUSE config
++ u8 hwpwrp_detect;//0:disable,1:enable
++
++ u8 hw_wps_pbc;//0:disable,1:enable
++
++#ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE
++ char adaptor_info_caching_file_path[PATH_LENGTH_MAX];
++#endif
++
++#ifdef CONFIG_LAYER2_ROAMING
++ u8 max_roaming_times; // the max number driver will try to roaming
++#endif
++
++#ifdef CONFIG_IOL
++ bool force_iol; //enable iol without other concern
++#endif
++ u8 special_rf_path; //0: 2T2R ,1: only turn on path A 1T1R, 2: only turn on path B 1T1R
++ u8 mac_phy_mode; //0:by efuse, 1:smsp, 2:dmdp, 3:dmsp.
++
++#ifdef CONFIG_80211D
++ u8 enable80211d;
++#endif
++
++ u8 ifname[16];
++ u8 if2name[16];
++
++ u8 notch_filter;
++
++#ifdef CONFIG_MULTI_VIR_IFACES
++ u8 ext_iface_num;//primary/secondary iface is excluded
++#endif
++};
++
++
++//For registry parameters
++#define RGTRY_OFT(field) ((ULONG)FIELD_OFFSET(struct registry_priv,field))
++#define RGTRY_SZ(field) sizeof(((struct registry_priv*) 0)->field)
++#define BSSID_OFT(field) ((ULONG)FIELD_OFFSET(WLAN_BSSID_EX,field))
++#define BSSID_SZ(field) sizeof(((PWLAN_BSSID_EX) 0)->field)
++
++#define MAX_CONTINUAL_URB_ERR 4
++
++#ifdef CONFIG_SDIO_HCI
++#include <drv_types_sdio.h>
++#define INTF_DATA SDIO_DATA
++#endif
++
++#define GET_PRIMARY_ADAPTER(padapter) (((_adapter *)padapter)->dvobj->if1)
++
++#define GET_IFACE_NUMS(padapter) (((_adapter *)padapter)->dvobj->iface_nums)
++#define GET_ADAPTER(padapter, iface_id) (((_adapter *)padapter)->dvobj->padapters[iface_id])
++
++enum _IFACE_ID {
++ IFACE_ID0, //maping to PRIMARY_ADAPTER
++ IFACE_ID1, //maping to SECONDARY_ADAPTER
++ IFACE_ID2,
++ IFACE_ID3,
++ IFACE_ID_MAX,
++};
++
++struct dvobj_priv
++{
++ _adapter *if1; //PRIMARY_ADAPTER
++ _adapter *if2; //SECONDARY_ADAPTER
++
++ s32 processing_dev_remove;
++
++ //for local/global synchronization
++ _mutex hw_init_mutex;
++ _mutex h2c_fwcmd_mutex;
++ _mutex setch_mutex;
++ _mutex setbw_mutex;
++
++ unsigned char oper_channel; //saved channel info when call set_channel_bw
++ unsigned char oper_bwmode;
++ unsigned char oper_ch_offset;//PRIME_CHNL_OFFSET
++ u32 on_oper_ch_time;
++
++ //extend to support mulitu interface
++ //padapters[IFACE_ID0] == if1
++ //padapters[IFACE_ID1] == if2
++ _adapter *padapters[IFACE_ID_MAX];
++ u8 iface_nums; // total number of ifaces used runtime
++
++ //For 92D, DMDP have 2 interface.
++ u8 InterfaceNumber;
++ u8 NumInterfaces;
++ u8 DualMacMode;
++ u8 irq_alloc;
++
++/*-------- below is for SDIO INTERFACE --------*/
++
++#ifdef INTF_DATA
++ INTF_DATA intf_data;
++#endif
++
++/*-------- below is for USB INTERFACE --------*/
++
++#ifdef CONFIG_USB_HCI
++
++ u8 nr_endpoint;
++ u8 ishighspeed;
++ u8 RtNumInPipes;
++ u8 RtNumOutPipes;
++ int ep_num[5]; //endpoint number
++
++ int RegUsbSS;
++
++ _sema usb_suspend_sema;
++
++#ifdef CONFIG_USB_VENDOR_REQ_MUTEX
++ _mutex usb_vendor_req_mutex;
++#endif
++
++#ifdef CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC
++ u8 * usb_alloc_vendor_req_buf;
++ u8 * usb_vendor_req_buf;
++#endif
++
++#ifdef PLATFORM_WINDOWS
++ //related device objects
++ PDEVICE_OBJECT pphysdevobj;//pPhysDevObj;
++ PDEVICE_OBJECT pfuncdevobj;//pFuncDevObj;
++ PDEVICE_OBJECT pnextdevobj;//pNextDevObj;
++
++ u8 nextdevstacksz;//unsigned char NextDeviceStackSize; //= (CHAR)CEdevice->pUsbDevObj->StackSize + 1;
++
++ //urb for control diescriptor request
++
++#ifdef PLATFORM_OS_XP
++ struct _URB_CONTROL_DESCRIPTOR_REQUEST descriptor_urb;
++ PUSB_CONFIGURATION_DESCRIPTOR pconfig_descriptor;//UsbConfigurationDescriptor;
++#endif
++
++#ifdef PLATFORM_OS_CE
++ WCHAR active_path[MAX_ACTIVE_REG_PATH]; // adapter regpath
++ USB_EXTENSION usb_extension;
++
++ _nic_hdl pipehdls_r8192c[0x10];
++#endif
++
++ u32 config_descriptor_len;//ULONG UsbConfigurationDescriptorLength;
++#endif//PLATFORM_WINDOWS
++
++#ifdef PLATFORM_LINUX
++ struct usb_interface *pusbintf;
++ struct usb_device *pusbdev;
++#endif//PLATFORM_LINUX
++
++#ifdef PLATFORM_FREEBSD
++ struct usb_interface *pusbintf;
++ struct usb_device *pusbdev;
++#endif//PLATFORM_FREEBSD
++ ATOMIC_T continual_urb_error;
++#endif//CONFIG_USB_HCI
++
++/*-------- below is for PCIE INTERFACE --------*/
++
++#ifdef CONFIG_PCI_HCI
++
++#ifdef PLATFORM_LINUX
++ struct pci_dev *ppcidev;
++
++ //PCI MEM map
++ unsigned long pci_mem_end; /* shared mem end */
++ unsigned long pci_mem_start; /* shared mem start */
++
++ //PCI IO map
++ unsigned long pci_base_addr; /* device I/O address */
++
++ //PciBridge
++ struct pci_priv pcipriv;
++
++ u16 irqline;
++ u8 irq_enabled;
++ RT_ISR_CONTENT isr_content;
++ _lock irq_th_lock;
++
++ //ASPM
++ u8 const_pci_aspm;
++ u8 const_amdpci_aspm;
++ u8 const_hwsw_rfoff_d3;
++ u8 const_support_pciaspm;
++ // pci-e bridge */
++ u8 const_hostpci_aspm_setting;
++ // pci-e device */
++ u8 const_devicepci_aspm_setting;
++ u8 b_support_aspm; // If it supports ASPM, Offset[560h] = 0x40, otherwise Offset[560h] = 0x00.
++ u8 b_support_backdoor;
++ u8 bdma64;
++#endif//PLATFORM_LINUX
++
++#endif//CONFIG_PCI_HCI
++};
++
++#ifdef PLATFORM_LINUX
++static struct device *dvobj_to_dev(struct dvobj_priv *dvobj)
++{
++ /* todo: get interface type from dvobj and the return the dev accordingly */
++#ifdef RTW_DVOBJ_CHIP_HW_TYPE
++#endif
++
++#ifdef CONFIG_USB_HCI
++ return &dvobj->pusbintf->dev;
++#endif
++#ifdef CONFIG_SDIO_HCI
++ return &dvobj->intf_data.func->dev;
++#endif
++#ifdef CONFIG_PCI_HCI
++ return &dvobj->ppcidev->dev;
++#endif
++}
++#endif
++
++
++enum _IFACE_TYPE {
++ IFACE_PORT0, //mapping to port0 for C/D series chips
++ IFACE_PORT1, //mapping to port1 for C/D series chip
++ MAX_IFACE_PORT,
++};
++
++enum _ADAPTER_TYPE {
++ PRIMARY_ADAPTER,
++ SECONDARY_ADAPTER,
++ MAX_ADAPTER = 0xFF,
++};
++
++typedef enum _DRIVER_STATE{
++ DRIVER_NORMAL = 0,
++ DRIVER_DISAPPEAR = 1,
++ DRIVER_REPLACE_DONGLE = 2,
++}DRIVER_STATE;
++
++#ifdef CONFIG_INTEL_PROXIM
++struct proxim {
++ bool proxim_support;
++ bool proxim_on;
++
++ void *proximity_priv;
++ int (*proxim_rx)(_adapter *padapter,
++ union recv_frame *precv_frame);
++ u8 (*proxim_get_var)(_adapter* padapter, u8 type);
++};
++#endif //CONFIG_INTEL_PROXIM
++
++#ifdef RTL8723A_SDIO_LOOPBACK
++typedef struct loopbackdata
++{
++ _sema sema;
++ _thread_hdl_ lbkthread;
++ u8 bstop;
++ u32 cnt;
++ u16 size;
++ u16 txsize;
++ u8 txbuf[0x8000];
++ u16 rxsize;
++ u8 rxbuf[0x8000];
++ u8 msg[100];
++
++}LOOPBACKDATA, *PLOOPBACKDATA;
++#endif
++
++struct _ADAPTER{
++ int DriverState;// for disable driver using module, use dongle to replace module.
++ int pid[3];//process id from UI, 0:wps, 1:hostapd, 2:dhcpcd
++ int bDongle;//build-in module or external dongle
++ u16 chip_type;
++ u16 HardwareType;
++ u16 interface_type;//USB,SDIO,PCI
++
++ struct dvobj_priv *dvobj;
++ struct mlme_priv mlmepriv;
++ struct mlme_ext_priv mlmeextpriv;
++ struct cmd_priv cmdpriv;
++ struct evt_priv evtpriv;
++ //struct io_queue *pio_queue;
++ struct io_priv iopriv;
++ struct xmit_priv xmitpriv;
++ struct recv_priv recvpriv;
++ struct sta_priv stapriv;
++ struct security_priv securitypriv;
++ _lock security_key_mutex; // add for CONFIG_IEEE80211W, none 11w also can use
++ struct registry_priv registrypriv;
++ struct pwrctrl_priv pwrctrlpriv;
++ struct eeprom_priv eeprompriv;
++ struct led_priv ledpriv;
++
++#ifdef CONFIG_MP_INCLUDED
++ struct mp_priv mppriv;
++#endif
++
++#ifdef CONFIG_DRVEXT_MODULE
++ struct drvext_priv drvextpriv;
++#endif
++
++#ifdef CONFIG_AP_MODE
++ struct hostapd_priv *phostapdpriv;
++#endif
++
++#ifdef CONFIG_IOCTL_CFG80211
++#ifdef CONFIG_P2P
++ struct cfg80211_wifidirect_info cfg80211_wdinfo;
++#endif //CONFIG_P2P
++#endif //CONFIG_IOCTL_CFG80211
++ u32 setband;
++#ifdef CONFIG_P2P
++ struct wifidirect_info wdinfo;
++#endif //CONFIG_P2P
++
++#ifdef CONFIG_TDLS
++ struct tdls_info tdlsinfo;
++#endif //CONFIG_TDLS
++
++#ifdef CONFIG_WFD
++ struct wifi_display_info wfd_info;
++#endif //CONFIG_WFD
++
++ PVOID HalData;
++ u32 hal_data_sz;
++ struct hal_ops HalFunc;
++
++#ifdef CONFIG_BT_COEXIST
++ //struct btcoexist_priv bt_coexist;
++#endif
++ s32 bDriverStopped;
++ s32 bSurpriseRemoved;
++ s32 bCardDisableWOHSM;
++
++ u32 IsrContent;
++ u32 ImrContent;
++
++ u8 EepromAddressSize;
++ u8 hw_init_completed;
++ u8 bDriverIsGoingToUnload;
++ u8 init_adpt_in_progress;
++ u8 bHaltInProgress;
++
++ _thread_hdl_ cmdThread;
++ _thread_hdl_ evtThread;
++ _thread_hdl_ xmitThread;
++ _thread_hdl_ recvThread;
++
++#ifndef PLATFORM_LINUX
++ NDIS_STATUS (*dvobj_init)(struct dvobj_priv *dvobj);
++ void (*dvobj_deinit)(struct dvobj_priv *dvobj);
++#endif
++
++ void (*intf_start)(_adapter * adapter);
++ void (*intf_stop)(_adapter * adapter);
++
++#ifdef PLATFORM_WINDOWS
++ _nic_hdl hndis_adapter;//hNdisAdapter(NDISMiniportAdapterHandle);
++ _nic_hdl hndis_config;//hNdisConfiguration;
++ NDIS_STRING fw_img;
++
++ u32 NdisPacketFilter;
++ u8 MCList[MAX_MCAST_LIST_NUM][6];
++ u32 MCAddrCount;
++#endif //end of PLATFORM_WINDOWS
++
++
++#ifdef PLATFORM_LINUX
++ _nic_hdl pnetdev;
++
++ // used by rtw_rereg_nd_name related function
++ struct rereg_nd_name_data {
++ _nic_hdl old_pnetdev;
++ char old_ifname[IFNAMSIZ];
++ u8 old_ips_mode;
++ u8 old_bRegUseLed;
++ } rereg_nd_name_priv;
++
++ int bup;
++ struct net_device_stats stats;
++ struct iw_statistics iwstats;
++ struct proc_dir_entry *dir_dev;// for proc directory
++
++#ifdef CONFIG_IOCTL_CFG80211
++ struct wireless_dev *rtw_wdev;
++#endif //CONFIG_IOCTL_CFG80211
++
++#endif //end of PLATFORM_LINUX
++
++#ifdef PLATFORM_FREEBSD
++ _nic_hdl pifp;
++ int bup;
++ _lock glock;
++#endif //PLATFORM_FREEBSD
++ int net_closed;
++
++ u8 bFWReady;
++ u8 bReadPortCancel;
++ u8 bWritePortCancel;
++ u8 bRxRSSIDisplay;
++ // Added by Albert 2012/07/26
++ // The driver will write the initial gain everytime when running in the DM_Write_DIG function.
++ u8 bForceWriteInitGain;
++ // Added by Albert 2012/10/26
++ // The driver will show up the desired channel number when this flag is 1.
++ u8 bNotifyChannelChange;
++#ifdef CONFIG_P2P
++ // Added by Albert 2012/12/06
++ // The driver will show the current P2P status when the upper application reads it.
++ u8 bShowGetP2PState;
++#endif
++#ifdef CONFIG_AUTOSUSPEND
++ u8 bDisableAutosuspend;
++#endif
++
++ //pbuddy_adapter is used only in two inteface case, (iface_nums=2 in struct dvobj_priv)
++ //PRIMARY_ADAPTER's buddy is SECONDARY_ADAPTER
++ //SECONDARY_ADAPTER's buddy is PRIMARY_ADAPTER
++ //for iface_id > SECONDARY_ADAPTER(IFACE_ID1), refer to padapters[iface_id] in struct dvobj_priv
++ //and their pbuddy_adapter is PRIMARY_ADAPTER.
++ //for PRIMARY_ADAPTER(IFACE_ID0) can directly refer to if1 in struct dvobj_priv
++ _adapter *pbuddy_adapter;
++
++#if defined(CONFIG_CONCURRENT_MODE) || defined(CONFIG_DUALMAC_CONCURRENT)
++ u8 isprimary; //is primary adapter or not
++ //notes:
++ // if isprimary is true, the adapter_type value is 0, iface_id is IFACE_ID0 for PRIMARY_ADAPTER
++ // if isprimary is false, the adapter_type value is 1, iface_id is IFACE_ID1 for SECONDARY_ADAPTER
++ // refer to iface_id if iface_nums>2 and isprimary is false and the adapter_type value is 0xff.
++ u8 adapter_type;//used only in two inteface case(PRIMARY_ADAPTER and SECONDARY_ADAPTER) .
++ u8 iface_type; //interface port type, it depends on HW port
++#endif
++
++ //extend to support multi interface
++ //IFACE_ID0 is equals to PRIMARY_ADAPTER
++ //IFACE_ID1 is equals to SECONDARY_ADAPTER
++ u8 iface_id;
++
++#ifdef CONFIG_DUALMAC_CONCURRENT
++ u8 DualMacConcurrent; // 1: DMSP 0:DMDP
++#endif
++
++#ifdef CONFIG_BR_EXT
++ _lock br_ext_lock;
++ //unsigned int macclone_completed;
++ struct nat25_network_db_entry *nethash[NAT25_HASH_SIZE];
++ int pppoe_connection_in_progress;
++ unsigned char pppoe_addr[MACADDRLEN];
++ unsigned char scdb_mac[MACADDRLEN];
++ unsigned char scdb_ip[4];
++ struct nat25_network_db_entry *scdb_entry;
++ unsigned char br_mac[MACADDRLEN];
++ unsigned char br_ip[4];
++
++ struct br_ext_info ethBrExtInfo;
++#endif // CONFIG_BR_EXT
++
++#ifdef CONFIG_INTEL_PROXIM
++ /* intel Proximity, should be alloc mem
++ * in intel Proximity module and can only
++ * be used in intel Proximity mode */
++ struct proxim proximity;
++#endif //CONFIG_INTEL_PROXIM
++
++#ifdef RTL8723A_SDIO_LOOPBACK
++ PLOOPBACKDATA ploopback;
++#endif
++
++};
++
++#define adapter_to_dvobj(adapter) (adapter->dvobj)
++
++int rtw_handle_dualmac(_adapter *adapter, bool init);
++
++__inline static u8 *myid(struct eeprom_priv *peepriv)
++{
++ return (peepriv->mac_addr);
++}
++
++
++#endif //__DRV_TYPES_H__
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/drv_types_linux.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/drv_types_linux.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/drv_types_linux.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/drv_types_linux.h 2015-07-28 01:20:58.317611539 +0200
+@@ -0,0 +1,24 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef __DRV_TYPES_LINUX_H__
++#define __DRV_TYPES_LINUX_H__
++
++
++#endif
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/drv_types_sdio.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/drv_types_sdio.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/drv_types_sdio.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/drv_types_sdio.h 2015-07-28 01:20:58.317611539 +0200
+@@ -0,0 +1,69 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef __DRV_TYPES_SDIO_H__
++#define __DRV_TYPES_SDIO_H__
++
++#include <drv_conf.h>
++#include <basic_types.h>
++
++// SDIO Header Files
++#ifdef PLATFORM_LINUX
++#include <linux/mmc/sdio_func.h>
++#endif
++#ifdef PLATFORM_OS_XP
++#include <wdm.h>
++#include <ntddsd.h>
++#endif
++#ifdef PLATFORM_OS_CE
++#include <sdcardddk.h>
++#endif
++
++
++typedef struct sdio_data
++{
++ u8 func_number;
++
++ u8 tx_block_mode;
++ u8 rx_block_mode;
++ u32 block_transfer_len;
++
++#ifdef PLATFORM_LINUX
++ struct sdio_func *func;
++#endif
++
++#ifdef PLATFORM_OS_XP
++ PDEVICE_OBJECT pphysdevobj;
++ PDEVICE_OBJECT pfuncdevobj;
++ PDEVICE_OBJECT pnextdevobj;
++ SDBUS_INTERFACE_STANDARD sdbusinft;
++ u8 nextdevstacksz;
++#endif
++
++#ifdef PLATFORM_OS_CE
++ SD_DEVICE_HANDLE hDevice;
++ SD_CARD_RCA sd_rca;
++ SD_CARD_INTERFACE card_intf;
++ BOOLEAN enableIsarWithStatus;
++ WCHAR active_path[MAX_ACTIVE_REG_PATH];
++ SD_HOST_BLOCK_CAPABILITY sd_host_blk_cap;
++#endif
++} SDIO_DATA, *PSDIO_DATA;
++
++#endif
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/drv_types_xp.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/drv_types_xp.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/drv_types_xp.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/drv_types_xp.h 2015-07-28 01:20:58.317611539 +0200
+@@ -0,0 +1,94 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef __DRV_TYPES_XP_H__
++#define __DRV_TYPES_XP_H__
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++
++
++
++#define MAX_MCAST_LIST_NUM 32
++
++
++
++//for ioctl
++#define MAKE_DRIVER_VERSION(_MainVer,_MinorVer) ((((u32)(_MainVer))<<16)+_MinorVer)
++
++#define NIC_HEADER_SIZE 14 //!< can be moved to typedef.h
++#define NIC_MAX_PACKET_SIZE 1514 //!< can be moved to typedef.h
++#define NIC_MAX_SEND_PACKETS 10 // max number of send packets the MiniportSendPackets function can accept, can be moved to typedef.h
++#define NIC_VENDOR_DRIVER_VERSION MAKE_DRIVER_VERSION(0,001) //!< can be moved to typedef.h
++#define NIC_MAX_PACKET_SIZE 1514 //!< can be moved to typedef.h
++
++
++#undef ON_VISTA
++//added by Jackson
++#ifndef ON_VISTA
++//
++// Bus driver versions
++//
++
++#define SDBUS_DRIVER_VERSION_1 0x100
++#define SDBUS_DRIVER_VERSION_2 0x200
++
++#define SDP_FUNCTION_TYPE 4
++#define SDP_BUS_DRIVER_VERSION 5
++#define SDP_BUS_WIDTH 6
++#define SDP_BUS_CLOCK 7
++#define SDP_BUS_INTERFACE_CONTROL 8
++#define SDP_HOST_BLOCK_LENGTH 9
++#define SDP_FUNCTION_BLOCK_LENGTH 10
++#define SDP_FN0_BLOCK_LENGTH 11
++#define SDP_FUNCTION_INT_ENABLE 12
++#endif
++
++
++typedef struct _MP_REG_ENTRY
++{
++
++ NDIS_STRING RegName; // variable name text
++ BOOLEAN bRequired; // 1 -> required, 0 -> optional
++
++ u8 Type; // NdisParameterInteger/NdisParameterHexInteger/NdisParameterStringle/NdisParameterMultiString
++ uint FieldOffset; // offset to MP_ADAPTER field
++ uint FieldSize; // size (in bytes) of the field
++
++#ifdef UNDER_AMD64
++ u64 Default;
++#else
++ u32 Default; // default value to use
++#endif
++
++ u32 Min; // minimum value allowed
++ u32 Max; // maximum value allowed
++} MP_REG_ENTRY, *PMP_REG_ENTRY;
++
++
++typedef struct _OCTET_STRING{
++ u8 *Octet;
++ u16 Length;
++} OCTET_STRING, *POCTET_STRING;
++
++
++
++
++
++#endif
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/ethernet.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/ethernet.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/ethernet.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/ethernet.h 2015-07-28 01:20:58.317611539 +0200
+@@ -0,0 +1,41 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++/*! \file */
++#ifndef __INC_ETHERNET_H
++#define __INC_ETHERNET_H
++
++#define ETHERNET_ADDRESS_LENGTH 6 //!< Ethernet Address Length
++#define ETHERNET_HEADER_SIZE 14 //!< Ethernet Header Length
++#define LLC_HEADER_SIZE 6 //!< LLC Header Length
++#define TYPE_LENGTH_FIELD_SIZE 2 //!< Type/Length Size
++#define MINIMUM_ETHERNET_PACKET_SIZE 60 //!< Minimum Ethernet Packet Size
++#define MAXIMUM_ETHERNET_PACKET_SIZE 1514 //!< Maximum Ethernet Packet Size
++
++#define RT_ETH_IS_MULTICAST(_pAddr) ((((UCHAR *)(_pAddr))[0]&0x01)!=0) //!< Is Multicast Address?
++#define RT_ETH_IS_BROADCAST(_pAddr) ( \
++ ((UCHAR *)(_pAddr))[0]==0xff && \
++ ((UCHAR *)(_pAddr))[1]==0xff && \
++ ((UCHAR *)(_pAddr))[2]==0xff && \
++ ((UCHAR *)(_pAddr))[3]==0xff && \
++ ((UCHAR *)(_pAddr))[4]==0xff && \
++ ((UCHAR *)(_pAddr))[5]==0xff ) //!< Is Broadcast Address?
++
++
++#endif // #ifndef __INC_ETHERNET_H
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/h2clbk.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/h2clbk.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/h2clbk.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/h2clbk.h 2015-07-28 01:20:58.317611539 +0200
+@@ -0,0 +1,35 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++
++
++#define _H2CLBK_H_
++
++
++#include <rtl8711_spec.h>
++#include <TypeDef.h>
++
++
++void _lbk_cmd(PADAPTER Adapter);
++
++void _lbk_rsp(PADAPTER Adapter);
++
++void _lbk_evt(IN PADAPTER Adapter);
++
++void h2c_event_callback(unsigned char *dev, unsigned char *pbuf);
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/Hal8192CEHWImg.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/Hal8192CEHWImg.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/Hal8192CEHWImg.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/Hal8192CEHWImg.h 2015-07-28 01:20:58.317611539 +0200
+@@ -0,0 +1,85 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef __INC_HAL8192CE_FW_IMG_H
++#define __INC_HAL8192CE_FW_IMG_H
++
++#include <basic_types.h>
++
++/*Created on 2011/ 6/15, 5:45*/
++
++#ifdef CONFIG_BT_COEXISTENCE
++#define TSMCImgArrayLength 15706 //v84 TSMC COMMON 2012-04-13
++#else //#ifdef CONFIG_P2P
++#define TSMCImgArrayLength 16126 //v88 TSMC P2PPS with CCX report C2H 2012-12-05
++#endif
++extern u8 Rtl8192CEFwTSMCImgArray[TSMCImgArrayLength];
++
++#ifdef CONFIG_BT_COEXISTENCE
++#define UMCACutImgArrayLength 16248 //v79 UMC A Cut COMMON 2011-10-06
++#else //#ifdef CONFIG_P2P
++#define UMCACutImgArrayLength 16126 //v88 UMC A Cut P2PPS with CCX report C2H 2012-12-05
++#endif
++extern u8 Rtl8192CEFwUMCACutImgArray[UMCACutImgArrayLength];
++
++#ifdef CONFIG_BT_COEXISTENCE
++#define UMCBCutImgArrayLength 15686 //v84 UMC B Cut COMMON 2012-04-13
++#else //#ifdef CONFIG_P2P
++#define UMCBCutImgArrayLength 16096 //v88 UMC B Cut P2PPS with CCX report C2H 2012-12-05
++#endif
++extern u8 Rtl8192CEFwUMCBCutImgArray[UMCBCutImgArrayLength];
++
++//8192C_Formal_92CE_PHYforMP_110804 2011-11-23
++//8188C_Formal_88CE_PHYforMP_111117 2011-11-23
++
++#define PHY_REG_2TArrayLength 374
++extern u32 Rtl8192CEPHY_REG_2TArray[PHY_REG_2TArrayLength];
++#define PHY_REG_1TArrayLength 374
++extern u32 Rtl8192CEPHY_REG_1TArray[PHY_REG_1TArrayLength];
++#define PHY_ChangeTo_1T1RArrayLength 1
++extern u32 Rtl8192CEPHY_ChangeTo_1T1RArray[PHY_ChangeTo_1T1RArrayLength];
++#define PHY_ChangeTo_1T2RArrayLength 1
++extern u32 Rtl8192CEPHY_ChangeTo_1T2RArray[PHY_ChangeTo_1T2RArrayLength];
++#define PHY_ChangeTo_2T2RArrayLength 1
++extern u32 Rtl8192CEPHY_ChangeTo_2T2RArray[PHY_ChangeTo_2T2RArrayLength];
++#define PHY_REG_Array_PGLength 336
++extern u32 Rtl8192CEPHY_REG_Array_PG[PHY_REG_Array_PGLength];
++#define PHY_REG_Array_MPLength 4
++extern u32 Rtl8192CEPHY_REG_Array_MP[PHY_REG_Array_MPLength];
++#define RadioA_2TArrayLength 282
++extern u32 Rtl8192CERadioA_2TArray[RadioA_2TArrayLength];
++#define RadioB_2TArrayLength 78
++extern u32 Rtl8192CERadioB_2TArray[RadioB_2TArrayLength];
++#define RadioA_1TArrayLength 282
++extern u32 Rtl8192CERadioA_1TArray[RadioA_1TArrayLength];
++#define RadioB_1TArrayLength 1
++extern u32 Rtl8192CERadioB_1TArray[RadioB_1TArrayLength];
++#define RadioB_GM_ArrayLength 1
++extern u32 Rtl8192CERadioB_GM_Array[RadioB_GM_ArrayLength];
++// MAC reg V14 - 2011-11-23
++#define MAC_2T_ArrayLength 174
++extern u32 Rtl8192CEMAC_2T_Array[MAC_2T_ArrayLength];
++#define MACPHY_Array_PGLength 1
++extern u32 Rtl8192CEMACPHY_Array_PG[MACPHY_Array_PGLength];
++#define AGCTAB_2TArrayLength 320
++extern u32 Rtl8192CEAGCTAB_2TArray[AGCTAB_2TArrayLength];
++#define AGCTAB_1TArrayLength 320
++extern u32 Rtl8192CEAGCTAB_1TArray[AGCTAB_1TArrayLength];
++
++#endif //__INC_HAL8192CE_FW_IMG_H
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/Hal8192CPhyCfg.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/Hal8192CPhyCfg.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/Hal8192CPhyCfg.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/Hal8192CPhyCfg.h 2015-07-28 01:20:58.317611539 +0200
+@@ -0,0 +1,427 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++/*****************************************************************************
++ * Module: __INC_HAL8192CPHYCFG_H
++ *
++ *
++ * Note:
++ *
++ *
++ * Export: Constants, macro, functions(API), global variables(None).
++ *
++ * Abbrev:
++ *
++ * History:
++ * Data Who Remark
++ * 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h.
++ * 2. Reorganize code architecture.
++ *
++ *****************************************************************************/
++ /* Check to see if the file has been included already. */
++#ifndef __INC_HAL8192CPHYCFG_H
++#define __INC_HAL8192CPHYCFG_H
++
++
++/*--------------------------Define Parameters-------------------------------*/
++#define LOOP_LIMIT 5
++#define MAX_STALL_TIME 50 //us
++#define AntennaDiversityValue 0x80 //(Adapter->bSoftwareAntennaDiversity ? 0x00:0x80)
++#define MAX_TXPWR_IDX_NMODE_92S 63
++#define Reset_Cnt_Limit 3
++
++#define IQK_MAC_REG_NUM 4
++#define IQK_ADDA_REG_NUM 16
++#define IQK_BB_REG_NUM 9
++#define HP_THERMAL_NUM 8
++
++#ifdef CONFIG_PCI_HCI
++#define MAX_AGGR_NUM 0x0A0A
++#else
++#define MAX_AGGR_NUM 0x0909
++#endif
++
++#ifdef CONFIG_PCI_HCI
++#define SET_RTL8192SE_RF_SLEEP(_pAdapter) \
++{ \
++ u1Byte u1bTmp; \
++ u1bTmp = PlatformEFIORead1Byte(_pAdapter, REG_LDOV12D_CTRL); \
++ u1bTmp |= BIT0; \
++ PlatformEFIOWrite1Byte(_pAdapter, REG_LDOV12D_CTRL, u1bTmp); \
++ PlatformEFIOWrite1Byte(_pAdapter, REG_SPS_OCP_CFG, 0x0); \
++ PlatformEFIOWrite1Byte(_pAdapter, TXPAUSE, 0xFF); \
++ PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x57FC); \
++ delay_us(100); \
++ PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x77FC); \
++ PlatformEFIOWrite1Byte(_pAdapter, PHY_CCA, 0x0); \
++ delay_us(10); \
++ PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x37FC); \
++ delay_us(10); \
++ PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x77FC); \
++ delay_us(10); \
++ PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x57FC); \
++}
++#endif
++
++
++/*--------------------------Define Parameters-------------------------------*/
++
++
++/*------------------------------Define structure----------------------------*/
++typedef enum _SwChnlCmdID{
++ CmdID_End,
++ CmdID_SetTxPowerLevel,
++ CmdID_BBRegWrite10,
++ CmdID_WritePortUlong,
++ CmdID_WritePortUshort,
++ CmdID_WritePortUchar,
++ CmdID_RF_WriteReg,
++}SwChnlCmdID;
++
++
++/* 1. Switch channel related */
++typedef struct _SwChnlCmd{
++ SwChnlCmdID CmdID;
++ u32 Para1;
++ u32 Para2;
++ u32 msDelay;
++}SwChnlCmd;
++
++typedef enum _HW90_BLOCK{
++ HW90_BLOCK_MAC = 0,
++ HW90_BLOCK_PHY0 = 1,
++ HW90_BLOCK_PHY1 = 2,
++ HW90_BLOCK_RF = 3,
++ HW90_BLOCK_MAXIMUM = 4, // Never use this
++}HW90_BLOCK_E, *PHW90_BLOCK_E;
++
++#define RF_PATH_MAX 2
++
++#define CHANNEL_MAX_NUMBER 14 // 14 is the max channel number
++#define CHANNEL_GROUP_MAX 3 // ch1~3, ch4~9, ch10~14 total three groups
++
++typedef enum _WIRELESS_MODE {
++ WIRELESS_MODE_UNKNOWN = 0x00,
++ WIRELESS_MODE_A = 0x01,
++ WIRELESS_MODE_B = 0x02,
++ WIRELESS_MODE_G = 0x04,
++ WIRELESS_MODE_AUTO = 0x08,
++ WIRELESS_MODE_N_24G = 0x10,
++ WIRELESS_MODE_N_5G = 0x20
++} WIRELESS_MODE;
++
++typedef enum _BaseBand_Config_Type{
++ BaseBand_Config_PHY_REG = 0, //Radio Path A
++ BaseBand_Config_AGC_TAB = 1, //Radio Path B
++}BaseBand_Config_Type, *PBaseBand_Config_Type;
++
++
++typedef enum _PHY_Rate_Tx_Power_Offset_Area{
++ RA_OFFSET_LEGACY_OFDM1,
++ RA_OFFSET_LEGACY_OFDM2,
++ RA_OFFSET_HT_OFDM1,
++ RA_OFFSET_HT_OFDM2,
++ RA_OFFSET_HT_OFDM3,
++ RA_OFFSET_HT_OFDM4,
++ RA_OFFSET_HT_CCK,
++}RA_OFFSET_AREA,*PRA_OFFSET_AREA;
++
++
++/* BB/RF related */
++typedef enum _RF_TYPE_8190P{
++ RF_TYPE_MIN, // 0
++ RF_8225=1, // 1 11b/g RF for verification only
++ RF_8256=2, // 2 11b/g/n
++ RF_8258=3, // 3 11a/b/g/n RF
++ RF_6052=4, // 4 11b/g/n RF
++ //RF_6052=5, // 4 11b/g/n RF
++ // TODO: We sholud remove this psudo PHY RF after we get new RF.
++ RF_PSEUDO_11N=5, // 5, It is a temporality RF.
++}RF_TYPE_8190P_E,*PRF_TYPE_8190P_E;
++
++typedef struct _BB_REGISTER_DEFINITION{
++ u32 rfintfs; // set software control:
++ // 0x870~0x877[8 bytes]
++
++ u32 rfintfi; // readback data:
++ // 0x8e0~0x8e7[8 bytes]
++
++ u32 rfintfo; // output data:
++ // 0x860~0x86f [16 bytes]
++
++ u32 rfintfe; // output enable:
++ // 0x860~0x86f [16 bytes]
++
++ u32 rf3wireOffset; // LSSI data:
++ // 0x840~0x84f [16 bytes]
++
++ u32 rfLSSI_Select; // BB Band Select:
++ // 0x878~0x87f [8 bytes]
++
++ u32 rfTxGainStage; // Tx gain stage:
++ // 0x80c~0x80f [4 bytes]
++
++ u32 rfHSSIPara1; // wire parameter control1 :
++ // 0x820~0x823,0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes]
++
++ u32 rfHSSIPara2; // wire parameter control2 :
++ // 0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes]
++
++ u32 rfSwitchControl; //Tx Rx antenna control :
++ // 0x858~0x85f [16 bytes]
++
++ u32 rfAGCControl1; //AGC parameter control1 :
++ // 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes]
++
++ u32 rfAGCControl2; //AGC parameter control2 :
++ // 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes]
++
++ u32 rfRxIQImbalance; //OFDM Rx IQ imbalance matrix :
++ // 0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes]
++
++ u32 rfRxAFE; //Rx IQ DC ofset and Rx digital filter, Rx DC notch filter :
++ // 0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes]
++
++ u32 rfTxIQImbalance; //OFDM Tx IQ imbalance matrix
++ // 0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes]
++
++ u32 rfTxAFE; //Tx IQ DC Offset and Tx DFIR type
++ // 0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes]
++
++ u32 rfLSSIReadBack; //LSSI RF readback data SI mode
++ // 0x8a0~0x8af [16 bytes]
++
++ u32 rfLSSIReadBackPi; //LSSI RF readback data PI mode 0x8b8-8bc for Path A and B
++
++}BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T;
++
++#ifdef CONFIG_MP_INCLUDED
++typedef enum _ANTENNA_PATH{
++ ANTENNA_NONE = 0x00,
++ ANTENNA_D ,
++ ANTENNA_C ,
++ ANTENNA_CD ,
++ ANTENNA_B ,
++ ANTENNA_BD ,
++ ANTENNA_BC ,
++ ANTENNA_BCD ,
++ ANTENNA_A ,
++ ANTENNA_AD ,
++ ANTENNA_AC ,
++ ANTENNA_ACD ,
++ ANTENNA_AB ,
++ ANTENNA_ABD ,
++ ANTENNA_ABC ,
++ ANTENNA_ABCD
++} ANTENNA_PATH;
++#endif
++
++typedef struct _R_ANTENNA_SELECT_OFDM{
++ u32 r_tx_antenna:4;
++ u32 r_ant_l:4;
++ u32 r_ant_non_ht:4;
++ u32 r_ant_ht1:4;
++ u32 r_ant_ht2:4;
++ u32 r_ant_ht_s1:4;
++ u32 r_ant_non_ht_s1:4;
++ u32 OFDM_TXSC:2;
++ u32 Reserved:2;
++}R_ANTENNA_SELECT_OFDM;
++
++typedef struct _R_ANTENNA_SELECT_CCK{
++ u8 r_cckrx_enable_2:2;
++ u8 r_cckrx_enable:2;
++ u8 r_ccktx_enable:4;
++}R_ANTENNA_SELECT_CCK;
++
++/*------------------------------Define structure----------------------------*/
++
++
++/*------------------------Export global variable----------------------------*/
++/*------------------------Export global variable----------------------------*/
++
++
++/*------------------------Export Marco Definition---------------------------*/
++/*------------------------Export Marco Definition---------------------------*/
++
++
++/*--------------------------Exported Function prototype---------------------*/
++//
++// BB and RF register read/write
++//
++u32 rtl8192c_PHY_QueryBBReg( IN PADAPTER Adapter,
++ IN u32 RegAddr,
++ IN u32 BitMask );
++void rtl8192c_PHY_SetBBReg( IN PADAPTER Adapter,
++ IN u32 RegAddr,
++ IN u32 BitMask,
++ IN u32 Data );
++u32 rtl8192c_PHY_QueryRFReg( IN PADAPTER Adapter,
++ IN RF_RADIO_PATH_E eRFPath,
++ IN u32 RegAddr,
++ IN u32 BitMask );
++void rtl8192c_PHY_SetRFReg( IN PADAPTER Adapter,
++ IN RF_RADIO_PATH_E eRFPath,
++ IN u32 RegAddr,
++ IN u32 BitMask,
++ IN u32 Data );
++
++//
++// Initialization related function
++//
++/* MAC/BB/RF HAL config */
++int PHY_MACConfig8192C( IN PADAPTER Adapter );
++int PHY_BBConfig8192C( IN PADAPTER Adapter );
++int PHY_RFConfig8192C( IN PADAPTER Adapter );
++/* RF config */
++int rtl8192c_PHY_ConfigRFWithParaFile( IN PADAPTER Adapter,
++ IN u8* pFileName,
++ IN RF_RADIO_PATH_E eRFPath);
++int rtl8192c_PHY_ConfigRFWithHeaderFile( IN PADAPTER Adapter,
++ IN RF_RADIO_PATH_E eRFPath);
++
++/* BB/RF readback check for making sure init OK */
++int rtl8192c_PHY_CheckBBAndRFOK( IN PADAPTER Adapter,
++ IN HW90_BLOCK_E CheckBlock,
++ IN RF_RADIO_PATH_E eRFPath );
++/* Read initi reg value for tx power setting. */
++void rtl8192c_PHY_GetHWRegOriginalValue( IN PADAPTER Adapter );
++
++//
++// RF Power setting
++//
++//extern BOOLEAN PHY_SetRFPowerState(IN PADAPTER Adapter,
++// IN RT_RF_POWER_STATE eRFPowerState);
++
++//
++// BB TX Power R/W
++//
++void PHY_GetTxPowerLevel8192C( IN PADAPTER Adapter,
++ OUT u32* powerlevel );
++void PHY_SetTxPowerLevel8192C( IN PADAPTER Adapter,
++ IN u8 channel );
++BOOLEAN PHY_UpdateTxPowerDbm8192C( IN PADAPTER Adapter,
++ IN int powerInDbm );
++
++//
++VOID
++PHY_ScanOperationBackup8192C(IN PADAPTER Adapter,
++ IN u8 Operation );
++
++//
++// Switch bandwidth for 8192S
++//
++//extern void PHY_SetBWModeCallback8192C( IN PRT_TIMER pTimer );
++void PHY_SetBWMode8192C( IN PADAPTER pAdapter,
++ IN HT_CHANNEL_WIDTH ChnlWidth,
++ IN unsigned char Offset );
++
++//
++// Set FW CMD IO for 8192S.
++//
++//extern BOOLEAN HalSetIO8192C( IN PADAPTER Adapter,
++// IN IO_TYPE IOType);
++
++//
++// Set A2 entry to fw for 8192S
++//
++extern void FillA2Entry8192C( IN PADAPTER Adapter,
++ IN u8 index,
++ IN u8* val);
++
++
++//
++// channel switch related funciton
++//
++//extern void PHY_SwChnlCallback8192C( IN PRT_TIMER pTimer );
++void PHY_SwChnl8192C( IN PADAPTER pAdapter,
++ IN u8 channel );
++ // Call after initialization
++void PHY_SwChnlPhy8192C( IN PADAPTER pAdapter,
++ IN u8 channel );
++
++void ChkFwCmdIoDone( IN PADAPTER Adapter);
++
++#ifdef USE_WORKITEM
++//extern void SetIOWorkItemCallback( IN PVOID pContext );
++#else
++//extern void SetIOTimerCallback( IN PRT_TIMER pTimer);
++#endif
++
++//
++// BB/MAC/RF other monitor API
++//
++void PHY_SetMonitorMode8192C(IN PADAPTER pAdapter,
++ IN BOOLEAN bEnableMonitorMode );
++
++BOOLEAN PHY_CheckIsLegalRfPath8192C(IN PADAPTER pAdapter,
++ IN u32 eRFPath );
++
++//
++// IQ calibrate
++//
++VOID rtl8192c_PHY_IQCalibrate( IN PADAPTER pAdapter , IN BOOLEAN bReCovery);
++
++//
++// LC calibrate
++//
++VOID rtl8192c_PHY_LCCalibrate(IN PADAPTER pAdapter);
++
++//
++// AP calibrate
++//
++VOID rtl8192c_PHY_APCalibrate(IN PADAPTER pAdapter, IN char delta);
++
++VOID rtl8192c_PHY_SetRFPathSwitch(IN PADAPTER pAdapter, IN BOOLEAN bMain);
++
++//
++// Modify the value of the hw register when beacon interval be changed.
++//
++void
++rtl8192c_PHY_SetBeaconHwReg( IN PADAPTER Adapter,
++ IN u16 BeaconInterval );
++
++
++extern VOID
++PHY_SwitchEphyParameter(
++ IN PADAPTER Adapter
++ );
++
++extern VOID
++PHY_EnableHostClkReq(
++ IN PADAPTER Adapter
++ );
++
++BOOLEAN
++SetAntennaConfig92C(
++ IN PADAPTER Adapter,
++ IN u8 DefaultAnt
++ );
++
++
++/*--------------------------Exported Function prototype---------------------*/
++
++#define PHY_QueryBBReg(Adapter, RegAddr, BitMask) rtl8192c_PHY_QueryBBReg((Adapter), (RegAddr), (BitMask))
++#define PHY_SetBBReg(Adapter, RegAddr, BitMask, Data) rtl8192c_PHY_SetBBReg((Adapter), (RegAddr), (BitMask), (Data))
++#define PHY_QueryRFReg(Adapter, eRFPath, RegAddr, BitMask) rtl8192c_PHY_QueryRFReg((Adapter), (eRFPath), (RegAddr), (BitMask))
++#define PHY_SetRFReg(Adapter, eRFPath, RegAddr, BitMask, Data) rtl8192c_PHY_SetRFReg((Adapter), (eRFPath), (RegAddr), (BitMask), (Data))
++
++#define PHY_SetMacReg PHY_SetBBReg
++
++#endif // __INC_HAL8192CPHYCFG_H
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/Hal8192CPhyReg.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/Hal8192CPhyReg.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/Hal8192CPhyReg.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/Hal8192CPhyReg.h 2015-07-28 01:20:58.317611539 +0200
+@@ -0,0 +1,1122 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++/*****************************************************************************
++ *
++ * Module: __INC_HAL8192CPHYREG_H
++ *
++ *
++ * Note: 1. Define PMAC/BB register map
++ * 2. Define RF register map
++ * 3. PMAC/BB register bit mask.
++ * 4. RF reg bit mask.
++ * 5. Other BB/RF relative definition.
++ *
++ *
++ * Export: Constants, macro, functions(API), global variables(None).
++ *
++ * Abbrev:
++ *
++ * History:
++ * Data Who Remark
++ * 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h.
++ * 2. Reorganize code architecture.
++ * 09/25/2008 MH 1. Add RL6052 register definition
++ *
++ *****************************************************************************/
++#ifndef __INC_HAL8192CPHYREG_H
++#define __INC_HAL8192CPHYREG_H
++
++
++/*--------------------------Define Parameters-------------------------------*/
++
++//============================================================
++// 8192S Regsiter offset definition
++//============================================================
++
++//
++// BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
++// 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
++// 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
++// 3. RF register 0x00-2E
++// 4. Bit Mask for BB/RF register
++// 5. Other defintion for BB/RF R/W
++//
++
++
++//
++// 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
++// 1. Page1(0x100)
++//
++#define rPMAC_Reset 0x100
++#define rPMAC_TxStart 0x104
++#define rPMAC_TxLegacySIG 0x108
++#define rPMAC_TxHTSIG1 0x10c
++#define rPMAC_TxHTSIG2 0x110
++#define rPMAC_PHYDebug 0x114
++#define rPMAC_TxPacketNum 0x118
++#define rPMAC_TxIdle 0x11c
++#define rPMAC_TxMACHeader0 0x120
++#define rPMAC_TxMACHeader1 0x124
++#define rPMAC_TxMACHeader2 0x128
++#define rPMAC_TxMACHeader3 0x12c
++#define rPMAC_TxMACHeader4 0x130
++#define rPMAC_TxMACHeader5 0x134
++#define rPMAC_TxDataType 0x138
++#define rPMAC_TxRandomSeed 0x13c
++#define rPMAC_CCKPLCPPreamble 0x140
++#define rPMAC_CCKPLCPHeader 0x144
++#define rPMAC_CCKCRC16 0x148
++#define rPMAC_OFDMRxCRC32OK 0x170
++#define rPMAC_OFDMRxCRC32Er 0x174
++#define rPMAC_OFDMRxParityEr 0x178
++#define rPMAC_OFDMRxCRC8Er 0x17c
++#define rPMAC_CCKCRxRC16Er 0x180
++#define rPMAC_CCKCRxRC32Er 0x184
++#define rPMAC_CCKCRxRC32OK 0x188
++#define rPMAC_TxStatus 0x18c
++
++//
++// 2. Page2(0x200)
++//
++// The following two definition are only used for USB interface.
++#define RF_BB_CMD_ADDR 0x02c0 // RF/BB read/write command address.
++#define RF_BB_CMD_DATA 0x02c4 // RF/BB read/write command data.
++
++//
++// 3. Page8(0x800)
++//
++#define rFPGA0_RFMOD 0x800 //RF mode & CCK TxSC // RF BW Setting??
++
++#define rFPGA0_TxInfo 0x804 // Status report??
++#define rFPGA0_PSDFunction 0x808
++
++#define rFPGA0_TxGainStage 0x80c // Set TX PWR init gain?
++
++#define rFPGA0_RFTiming1 0x810 // Useless now
++#define rFPGA0_RFTiming2 0x814
++
++#define rFPGA0_XA_HSSIParameter1 0x820 // RF 3 wire register
++#define rFPGA0_XA_HSSIParameter2 0x824
++#define rFPGA0_XB_HSSIParameter1 0x828
++#define rFPGA0_XB_HSSIParameter2 0x82c
++#define rTxAGC_B_Rate18_06 0x830
++#define rTxAGC_B_Rate54_24 0x834
++#define rTxAGC_B_CCK1_55_Mcs32 0x838
++#define rTxAGC_B_Mcs03_Mcs00 0x83c
++
++#define rTxAGC_B_Mcs07_Mcs04 0x848
++#define rTxAGC_B_Mcs11_Mcs08 0x84c
++
++#define rFPGA0_XA_LSSIParameter 0x840
++#define rFPGA0_XB_LSSIParameter 0x844
++
++#define rFPGA0_RFWakeUpParameter 0x850 // Useless now
++#define rFPGA0_RFSleepUpParameter 0x854
++
++#define rFPGA0_XAB_SwitchControl 0x858 // RF Channel switch
++#define rFPGA0_XCD_SwitchControl 0x85c
++
++#define rFPGA0_XA_RFInterfaceOE 0x860 // RF Channel switch
++#define rFPGA0_XB_RFInterfaceOE 0x864
++
++#define rTxAGC_B_Mcs15_Mcs12 0x868
++#define rTxAGC_B_CCK11_A_CCK2_11 0x86c
++
++#define rFPGA0_XAB_RFInterfaceSW 0x870 // RF Interface Software Control
++#define rFPGA0_XCD_RFInterfaceSW 0x874
++
++#define rFPGA0_XAB_RFParameter 0x878 // RF Parameter
++#define rFPGA0_XCD_RFParameter 0x87c
++
++#define rFPGA0_AnalogParameter1 0x880 // Crystal cap setting RF-R/W protection for parameter4??
++#define rFPGA0_AnalogParameter2 0x884
++#define rFPGA0_AnalogParameter3 0x888 // Useless now
++#define rFPGA0_AnalogParameter4 0x88c
++
++#define rFPGA0_XA_LSSIReadBack 0x8a0 // Tranceiver LSSI Readback
++#define rFPGA0_XB_LSSIReadBack 0x8a4
++#define rFPGA0_XC_LSSIReadBack 0x8a8
++#define rFPGA0_XD_LSSIReadBack 0x8ac
++
++#define rFPGA0_PSDReport 0x8b4 // Useless now
++#define TransceiverA_HSPI_Readback 0x8b8 // Transceiver A HSPI Readback
++#define TransceiverB_HSPI_Readback 0x8bc // Transceiver B HSPI Readback
++#define rFPGA0_XAB_RFInterfaceRB 0x8e0 // Useless now // RF Interface Readback Value
++#define rFPGA0_XCD_RFInterfaceRB 0x8e4 // Useless now
++
++//
++// 4. Page9(0x900)
++//
++#define rFPGA1_RFMOD 0x900 //RF mode & OFDM TxSC // RF BW Setting??
++
++#define rFPGA1_TxBlock 0x904 // Useless now
++#define rFPGA1_DebugSelect 0x908 // Useless now
++#define rFPGA1_TxInfo 0x90c // Useless now // Status report??
++
++//
++// 5. PageA(0xA00)
++//
++// Set Control channel to upper or lower. These settings are required only for 40MHz
++#define rCCK0_System 0xa00
++
++#define rCCK0_AFESetting 0xa04 // Disable init gain now // Select RX path by RSSI
++#define rCCK0_CCA 0xa08 // Disable init gain now // Init gain
++
++#define rCCK0_RxAGC1 0xa0c //AGC default value, saturation level // Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series
++#define rCCK0_RxAGC2 0xa10 //AGC & DAGC
++
++#define rCCK0_RxHP 0xa14
++
++#define rCCK0_DSPParameter1 0xa18 //Timing recovery & Channel estimation threshold
++#define rCCK0_DSPParameter2 0xa1c //SQ threshold
++
++#define rCCK0_TxFilter1 0xa20
++#define rCCK0_TxFilter2 0xa24
++#define rCCK0_DebugPort 0xa28 //debug port and Tx filter3
++#define rCCK0_FalseAlarmReport 0xa2c //0xa2d useless now 0xa30-a4f channel report
++#define rCCK0_TRSSIReport 0xa50
++#define rCCK0_RxReport 0xa54 //0xa57
++#define rCCK0_FACounterLower 0xa5c //0xa5b
++#define rCCK0_FACounterUpper 0xa58 //0xa5c
++
++//
++// PageB(0xB00)
++//
++#define rPdp_AntA 0xb00
++#define rPdp_AntA_4 0xb04
++#define rConfig_Pmpd_AntA 0xb28
++#define rConfig_AntA 0xb68
++#define rConfig_AntB 0xb6c
++#define rPdp_AntB 0xb70
++#define rPdp_AntB_4 0xb74
++#define rConfig_Pmpd_AntB 0xb98
++#define rAPK 0xbd8
++
++//
++// 6. PageC(0xC00)
++//
++#define rOFDM0_LSTF 0xc00
++
++#define rOFDM0_TRxPathEnable 0xc04
++#define rOFDM0_TRMuxPar 0xc08
++#define rOFDM0_TRSWIsolation 0xc0c
++
++#define rOFDM0_XARxAFE 0xc10 //RxIQ DC offset, Rx digital filter, DC notch filter
++#define rOFDM0_XARxIQImbalance 0xc14 //RxIQ imblance matrix
++#define rOFDM0_XBRxAFE 0xc18
++#define rOFDM0_XBRxIQImbalance 0xc1c
++#define rOFDM0_XCRxAFE 0xc20
++#define rOFDM0_XCRxIQImbalance 0xc24
++#define rOFDM0_XDRxAFE 0xc28
++#define rOFDM0_XDRxIQImbalance 0xc2c
++
++#define rOFDM0_RxDetector1 0xc30 //PD,BW & SBD // DM tune init gain
++#define rOFDM0_RxDetector2 0xc34 //SBD & Fame Sync.
++#define rOFDM0_RxDetector3 0xc38 //Frame Sync.
++#define rOFDM0_RxDetector4 0xc3c //PD, SBD, Frame Sync & Short-GI
++
++#define rOFDM0_RxDSP 0xc40 //Rx Sync Path
++#define rOFDM0_CFOandDAGC 0xc44 //CFO & DAGC
++#define rOFDM0_CCADropThreshold 0xc48 //CCA Drop threshold
++#define rOFDM0_ECCAThreshold 0xc4c // energy CCA
++
++#define rOFDM0_XAAGCCore1 0xc50 // DIG
++#define rOFDM0_XAAGCCore2 0xc54
++#define rOFDM0_XBAGCCore1 0xc58
++#define rOFDM0_XBAGCCore2 0xc5c
++#define rOFDM0_XCAGCCore1 0xc60
++#define rOFDM0_XCAGCCore2 0xc64
++#define rOFDM0_XDAGCCore1 0xc68
++#define rOFDM0_XDAGCCore2 0xc6c
++
++#define rOFDM0_AGCParameter1 0xc70
++#define rOFDM0_AGCParameter2 0xc74
++#define rOFDM0_AGCRSSITable 0xc78
++#define rOFDM0_HTSTFAGC 0xc7c
++
++#define rOFDM0_XATxIQImbalance 0xc80 // TX PWR TRACK and DIG
++#define rOFDM0_XATxAFE 0xc84
++#define rOFDM0_XBTxIQImbalance 0xc88
++#define rOFDM0_XBTxAFE 0xc8c
++#define rOFDM0_XCTxIQImbalance 0xc90
++#define rOFDM0_XCTxAFE 0xc94
++#define rOFDM0_XDTxIQImbalance 0xc98
++#define rOFDM0_XDTxAFE 0xc9c
++
++#define rOFDM0_RxIQExtAnta 0xca0
++#define rOFDM0_TxCoeff1 0xca4
++#define rOFDM0_TxCoeff2 0xca8
++#define rOFDM0_TxCoeff3 0xcac
++#define rOFDM0_TxCoeff4 0xcb0
++#define rOFDM0_TxCoeff5 0xcb4
++#define rOFDM0_TxCoeff6 0xcb8
++#define rOFDM0_RxHPParameter 0xce0
++#define rOFDM0_TxPseudoNoiseWgt 0xce4
++#define rOFDM0_FrameSync 0xcf0
++#define rOFDM0_DFSReport 0xcf4
++
++//
++// 7. PageD(0xD00)
++//
++#define rOFDM1_LSTF 0xd00
++#define rOFDM1_TRxPathEnable 0xd04
++
++#define rOFDM1_CFO 0xd08 // No setting now
++#define rOFDM1_CSI1 0xd10
++#define rOFDM1_SBD 0xd14
++#define rOFDM1_CSI2 0xd18
++#define rOFDM1_CFOTracking 0xd2c
++#define rOFDM1_TRxMesaure1 0xd34
++#define rOFDM1_IntfDet 0xd3c
++#define rOFDM1_PseudoNoiseStateAB 0xd50
++#define rOFDM1_PseudoNoiseStateCD 0xd54
++#define rOFDM1_RxPseudoNoiseWgt 0xd58
++
++#define rOFDM_PHYCounter1 0xda0 //cca, parity fail
++#define rOFDM_PHYCounter2 0xda4 //rate illegal, crc8 fail
++#define rOFDM_PHYCounter3 0xda8 //MCS not support
++
++#define rOFDM_ShortCFOAB 0xdac // No setting now
++#define rOFDM_ShortCFOCD 0xdb0
++#define rOFDM_LongCFOAB 0xdb4
++#define rOFDM_LongCFOCD 0xdb8
++#define rOFDM_TailCFOAB 0xdbc
++#define rOFDM_TailCFOCD 0xdc0
++#define rOFDM_PWMeasure1 0xdc4
++#define rOFDM_PWMeasure2 0xdc8
++#define rOFDM_BWReport 0xdcc
++#define rOFDM_AGCReport 0xdd0
++#define rOFDM_RxSNR 0xdd4
++#define rOFDM_RxEVMCSI 0xdd8
++#define rOFDM_SIGReport 0xddc
++
++
++//
++// 8. PageE(0xE00)
++//
++#define rTxAGC_A_Rate18_06 0xe00
++#define rTxAGC_A_Rate54_24 0xe04
++#define rTxAGC_A_CCK1_Mcs32 0xe08
++#define rTxAGC_A_Mcs03_Mcs00 0xe10
++#define rTxAGC_A_Mcs07_Mcs04 0xe14
++#define rTxAGC_A_Mcs11_Mcs08 0xe18
++#define rTxAGC_A_Mcs15_Mcs12 0xe1c
++
++#define rFPGA0_IQK 0xe28
++#define rTx_IQK_Tone_A 0xe30
++#define rRx_IQK_Tone_A 0xe34
++#define rTx_IQK_PI_A 0xe38
++#define rRx_IQK_PI_A 0xe3c
++
++#define rTx_IQK 0xe40
++#define rRx_IQK 0xe44
++#define rIQK_AGC_Pts 0xe48
++#define rIQK_AGC_Rsp 0xe4c
++#define rTx_IQK_Tone_B 0xe50
++#define rRx_IQK_Tone_B 0xe54
++#define rTx_IQK_PI_B 0xe58
++#define rRx_IQK_PI_B 0xe5c
++#define rIQK_AGC_Cont 0xe60
++
++#define rBlue_Tooth 0xe6c
++#define rRx_Wait_CCA 0xe70
++#define rTx_CCK_RFON 0xe74
++#define rTx_CCK_BBON 0xe78
++#define rTx_OFDM_RFON 0xe7c
++#define rTx_OFDM_BBON 0xe80
++#define rTx_To_Rx 0xe84
++#define rTx_To_Tx 0xe88
++#define rRx_CCK 0xe8c
++
++#define rTx_Power_Before_IQK_A 0xe94
++#define rTx_Power_After_IQK_A 0xe9c
++
++#define rRx_Power_Before_IQK_A 0xea0
++#define rRx_Power_Before_IQK_A_2 0xea4
++#define rRx_Power_After_IQK_A 0xea8
++#define rRx_Power_After_IQK_A_2 0xeac
++
++#define rTx_Power_Before_IQK_B 0xeb4
++#define rTx_Power_After_IQK_B 0xebc
++
++#define rRx_Power_Before_IQK_B 0xec0
++#define rRx_Power_Before_IQK_B_2 0xec4
++#define rRx_Power_After_IQK_B 0xec8
++#define rRx_Power_After_IQK_B_2 0xecc
++
++#define rRx_OFDM 0xed0
++#define rRx_Wait_RIFS 0xed4
++#define rRx_TO_Rx 0xed8
++#define rStandby 0xedc
++#define rSleep 0xee0
++#define rPMPD_ANAEN 0xeec
++
++//
++// 7. RF Register 0x00-0x2E (RF 8256)
++// RF-0222D 0x00-3F
++//
++//Zebra1
++#define rZebra1_HSSIEnable 0x0 // Useless now
++#define rZebra1_TRxEnable1 0x1
++#define rZebra1_TRxEnable2 0x2
++#define rZebra1_AGC 0x4
++#define rZebra1_ChargePump 0x5
++#define rZebra1_Channel 0x7 // RF channel switch
++
++//#endif
++#define rZebra1_TxGain 0x8 // Useless now
++#define rZebra1_TxLPF 0x9
++#define rZebra1_RxLPF 0xb
++#define rZebra1_RxHPFCorner 0xc
++
++//Zebra4
++#define rGlobalCtrl 0 // Useless now
++#define rRTL8256_TxLPF 19
++#define rRTL8256_RxLPF 11
++
++//RTL8258
++#define rRTL8258_TxLPF 0x11 // Useless now
++#define rRTL8258_RxLPF 0x13
++#define rRTL8258_RSSILPF 0xa
++
++//
++// RL6052 Register definition
++//
++#define RF_AC 0x00 //
++
++#define RF_IQADJ_G1 0x01 //
++#define RF_IQADJ_G2 0x02 //
++#define RF_BS_PA_APSET_G1_G4 0x03
++#define RF_BS_PA_APSET_G5_G8 0x04
++#define RF_POW_TRSW 0x05 //
++
++#define RF_GAIN_RX 0x06 //
++#define RF_GAIN_TX 0x07 //
++
++#define RF_TXM_IDAC 0x08 //
++#define RF_IPA_G 0x09 //
++#define RF_TXBIAS_G 0x0A
++#define RF_TXPA_AG 0x0B
++#define RF_IPA_A 0x0C //
++#define RF_TXBIAS_A 0x0D
++#define RF_BS_PA_APSET_G9_G11 0x0E
++#define RF_BS_IQGEN 0x0F //
++
++#define RF_MODE1 0x10 //
++#define RF_MODE2 0x11 //
++
++#define RF_RX_AGC_HP 0x12 //
++#define RF_TX_AGC 0x13 //
++#define RF_BIAS 0x14 //
++#define RF_IPA 0x15 //
++#define RF_POW_ABILITY 0x17 //
++#define RF_MODE_AG 0x18 //
++#define rRfChannel 0x18 // RF channel and BW switch
++#define RF_CHNLBW 0x18 // RF channel and BW switch
++#define RF_TOP 0x19 //
++
++#define RF_RX_G1 0x1A //
++#define RF_RX_G2 0x1B //
++
++#define RF_RX_BB2 0x1C //
++#define RF_RX_BB1 0x1D //
++
++#define RF_RCK1 0x1E //
++#define RF_RCK2 0x1F //
++
++#define RF_TX_G1 0x20 //
++#define RF_TX_G2 0x21 //
++#define RF_TX_G3 0x22 //
++
++#define RF_TX_BB1 0x23 //
++
++#define RF_T_METER 0x24 //
++
++#define RF_SYN_G1 0x25 // RF TX Power control
++#define RF_SYN_G2 0x26 // RF TX Power control
++#define RF_SYN_G3 0x27 // RF TX Power control
++#define RF_SYN_G4 0x28 // RF TX Power control
++#define RF_SYN_G5 0x29 // RF TX Power control
++#define RF_SYN_G6 0x2A // RF TX Power control
++#define RF_SYN_G7 0x2B // RF TX Power control
++#define RF_SYN_G8 0x2C // RF TX Power control
++
++#define RF_RCK_OS 0x30 // RF TX PA control
++
++#define RF_TXPA_G1 0x31 // RF TX PA control
++#define RF_TXPA_G2 0x32 // RF TX PA control
++#define RF_TXPA_G3 0x33 // RF TX PA control
++
++//
++//Bit Mask
++//
++// 1. Page1(0x100)
++#define bBBResetB 0x100 // Useless now?
++#define bGlobalResetB 0x200
++#define bOFDMTxStart 0x4
++#define bCCKTxStart 0x8
++#define bCRC32Debug 0x100
++#define bPMACLoopback 0x10
++#define bTxLSIG 0xffffff
++#define bOFDMTxRate 0xf
++#define bOFDMTxReserved 0x10
++#define bOFDMTxLength 0x1ffe0
++#define bOFDMTxParity 0x20000
++#define bTxHTSIG1 0xffffff
++#define bTxHTMCSRate 0x7f
++#define bTxHTBW 0x80
++#define bTxHTLength 0xffff00
++#define bTxHTSIG2 0xffffff
++#define bTxHTSmoothing 0x1
++#define bTxHTSounding 0x2
++#define bTxHTReserved 0x4
++#define bTxHTAggreation 0x8
++#define bTxHTSTBC 0x30
++#define bTxHTAdvanceCoding 0x40
++#define bTxHTShortGI 0x80
++#define bTxHTNumberHT_LTF 0x300
++#define bTxHTCRC8 0x3fc00
++#define bCounterReset 0x10000
++#define bNumOfOFDMTx 0xffff
++#define bNumOfCCKTx 0xffff0000
++#define bTxIdleInterval 0xffff
++#define bOFDMService 0xffff0000
++#define bTxMACHeader 0xffffffff
++#define bTxDataInit 0xff
++#define bTxHTMode 0x100
++#define bTxDataType 0x30000
++#define bTxRandomSeed 0xffffffff
++#define bCCKTxPreamble 0x1
++#define bCCKTxSFD 0xffff0000
++#define bCCKTxSIG 0xff
++#define bCCKTxService 0xff00
++#define bCCKLengthExt 0x8000
++#define bCCKTxLength 0xffff0000
++#define bCCKTxCRC16 0xffff
++#define bCCKTxStatus 0x1
++#define bOFDMTxStatus 0x2
++
++#define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff))
++
++// 2. Page8(0x800)
++#define bRFMOD 0x1 // Reg 0x800 rFPGA0_RFMOD
++#define bJapanMode 0x2
++#define bCCKTxSC 0x30
++#define bCCKEn 0x1000000
++#define bOFDMEn 0x2000000
++
++#define bOFDMRxADCPhase 0x10000 // Useless now
++#define bOFDMTxDACPhase 0x40000
++#define bXATxAGC 0x3f
++
++#define bAntennaSelect 0x0300
++
++#define bXBTxAGC 0xf00 // Reg 80c rFPGA0_TxGainStage
++#define bXCTxAGC 0xf000
++#define bXDTxAGC 0xf0000
++
++#define bPAStart 0xf0000000 // Useless now
++#define bTRStart 0x00f00000
++#define bRFStart 0x0000f000
++#define bBBStart 0x000000f0
++#define bBBCCKStart 0x0000000f
++#define bPAEnd 0xf //Reg0x814
++#define bTREnd 0x0f000000
++#define bRFEnd 0x000f0000
++#define bCCAMask 0x000000f0 //T2R
++#define bR2RCCAMask 0x00000f00
++#define bHSSI_R2TDelay 0xf8000000
++#define bHSSI_T2RDelay 0xf80000
++#define bContTxHSSI 0x400 //chane gain at continue Tx
++#define bIGFromCCK 0x200
++#define bAGCAddress 0x3f
++#define bRxHPTx 0x7000
++#define bRxHPT2R 0x38000
++#define bRxHPCCKIni 0xc0000
++#define bAGCTxCode 0xc00000
++#define bAGCRxCode 0x300000
++
++#define b3WireDataLength 0x800 // Reg 0x820~84f rFPGA0_XA_HSSIParameter1
++#define b3WireAddressLength 0x400
++
++#define b3WireRFPowerDown 0x1 // Useless now
++//#define bHWSISelect 0x8
++#define b5GPAPEPolarity 0x40000000
++#define b2GPAPEPolarity 0x80000000
++#define bRFSW_TxDefaultAnt 0x3
++#define bRFSW_TxOptionAnt 0x30
++#define bRFSW_RxDefaultAnt 0x300
++#define bRFSW_RxOptionAnt 0x3000
++#define bRFSI_3WireData 0x1
++#define bRFSI_3WireClock 0x2
++#define bRFSI_3WireLoad 0x4
++#define bRFSI_3WireRW 0x8
++#define bRFSI_3Wire 0xf
++
++#define bRFSI_RFENV 0x10 // Reg 0x870 rFPGA0_XAB_RFInterfaceSW
++
++#define bRFSI_TRSW 0x20 // Useless now
++#define bRFSI_TRSWB 0x40
++#define bRFSI_ANTSW 0x100
++#define bRFSI_ANTSWB 0x200
++#define bRFSI_PAPE 0x400
++#define bRFSI_PAPE5G 0x800
++#define bBandSelect 0x1
++#define bHTSIG2_GI 0x80
++#define bHTSIG2_Smoothing 0x01
++#define bHTSIG2_Sounding 0x02
++#define bHTSIG2_Aggreaton 0x08
++#define bHTSIG2_STBC 0x30
++#define bHTSIG2_AdvCoding 0x40
++#define bHTSIG2_NumOfHTLTF 0x300
++#define bHTSIG2_CRC8 0x3fc
++#define bHTSIG1_MCS 0x7f
++#define bHTSIG1_BandWidth 0x80
++#define bHTSIG1_HTLength 0xffff
++#define bLSIG_Rate 0xf
++#define bLSIG_Reserved 0x10
++#define bLSIG_Length 0x1fffe
++#define bLSIG_Parity 0x20
++#define bCCKRxPhase 0x4
++
++#define bLSSIReadAddress 0x7f800000 // T65 RF
++
++#define bLSSIReadEdge 0x80000000 //LSSI "Read" edge signal
++
++#define bLSSIReadBackData 0xfffff // T65 RF
++
++#define bLSSIReadOKFlag 0x1000 // Useless now
++#define bCCKSampleRate 0x8 //0: 44MHz, 1:88MHz
++#define bRegulator0Standby 0x1
++#define bRegulatorPLLStandby 0x2
++#define bRegulator1Standby 0x4
++#define bPLLPowerUp 0x8
++#define bDPLLPowerUp 0x10
++#define bDA10PowerUp 0x20
++#define bAD7PowerUp 0x200
++#define bDA6PowerUp 0x2000
++#define bXtalPowerUp 0x4000
++#define b40MDClkPowerUP 0x8000
++#define bDA6DebugMode 0x20000
++#define bDA6Swing 0x380000
++
++#define bADClkPhase 0x4000000 // Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ
++
++#define b80MClkDelay 0x18000000 // Useless
++#define bAFEWatchDogEnable 0x20000000
++
++#define bXtalCap01 0xc0000000 // Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap
++#define bXtalCap23 0x3
++#define bXtalCap92x 0x0f000000
++#define bXtalCap 0x0f000000
++
++#define bIntDifClkEnable 0x400 // Useless
++#define bExtSigClkEnable 0x800
++#define bBandgapMbiasPowerUp 0x10000
++#define bAD11SHGain 0xc0000
++#define bAD11InputRange 0x700000
++#define bAD11OPCurrent 0x3800000
++#define bIPathLoopback 0x4000000
++#define bQPathLoopback 0x8000000
++#define bAFELoopback 0x10000000
++#define bDA10Swing 0x7e0
++#define bDA10Reverse 0x800
++#define bDAClkSource 0x1000
++#define bAD7InputRange 0x6000
++#define bAD7Gain 0x38000
++#define bAD7OutputCMMode 0x40000
++#define bAD7InputCMMode 0x380000
++#define bAD7Current 0xc00000
++#define bRegulatorAdjust 0x7000000
++#define bAD11PowerUpAtTx 0x1
++#define bDA10PSAtTx 0x10
++#define bAD11PowerUpAtRx 0x100
++#define bDA10PSAtRx 0x1000
++#define bCCKRxAGCFormat 0x200
++#define bPSDFFTSamplepPoint 0xc000
++#define bPSDAverageNum 0x3000
++#define bIQPathControl 0xc00
++#define bPSDFreq 0x3ff
++#define bPSDAntennaPath 0x30
++#define bPSDIQSwitch 0x40
++#define bPSDRxTrigger 0x400000
++#define bPSDTxTrigger 0x80000000
++#define bPSDSineToneScale 0x7f000000
++#define bPSDReport 0xffff
++
++// 3. Page9(0x900)
++#define bOFDMTxSC 0x30000000 // Useless
++#define bCCKTxOn 0x1
++#define bOFDMTxOn 0x2
++#define bDebugPage 0xfff //reset debug page and also HWord, LWord
++#define bDebugItem 0xff //reset debug page and LWord
++#define bAntL 0x10
++#define bAntNonHT 0x100
++#define bAntHT1 0x1000
++#define bAntHT2 0x10000
++#define bAntHT1S1 0x100000
++#define bAntNonHTS1 0x1000000
++
++// 4. PageA(0xA00)
++#define bCCKBBMode 0x3 // Useless
++#define bCCKTxPowerSaving 0x80
++#define bCCKRxPowerSaving 0x40
++
++#define bCCKSideBand 0x10 // Reg 0xa00 rCCK0_System 20/40 switch
++
++#define bCCKScramble 0x8 // Useless
++#define bCCKAntDiversity 0x8000
++#define bCCKCarrierRecovery 0x4000
++#define bCCKTxRate 0x3000
++#define bCCKDCCancel 0x0800
++#define bCCKISICancel 0x0400
++#define bCCKMatchFilter 0x0200
++#define bCCKEqualizer 0x0100
++#define bCCKPreambleDetect 0x800000
++#define bCCKFastFalseCCA 0x400000
++#define bCCKChEstStart 0x300000
++#define bCCKCCACount 0x080000
++#define bCCKcs_lim 0x070000
++#define bCCKBistMode 0x80000000
++#define bCCKCCAMask 0x40000000
++#define bCCKTxDACPhase 0x4
++#define bCCKRxADCPhase 0x20000000 //r_rx_clk
++#define bCCKr_cp_mode0 0x0100
++#define bCCKTxDCOffset 0xf0
++#define bCCKRxDCOffset 0xf
++#define bCCKCCAMode 0xc000
++#define bCCKFalseCS_lim 0x3f00
++#define bCCKCS_ratio 0xc00000
++#define bCCKCorgBit_sel 0x300000
++#define bCCKPD_lim 0x0f0000
++#define bCCKNewCCA 0x80000000
++#define bCCKRxHPofIG 0x8000
++#define bCCKRxIG 0x7f00
++#define bCCKLNAPolarity 0x800000
++#define bCCKRx1stGain 0x7f0000
++#define bCCKRFExtend 0x20000000 //CCK Rx Iinital gain polarity
++#define bCCKRxAGCSatLevel 0x1f000000
++#define bCCKRxAGCSatCount 0xe0
++#define bCCKRxRFSettle 0x1f //AGCsamp_dly
++#define bCCKFixedRxAGC 0x8000
++//#define bCCKRxAGCFormat 0x4000 //remove to HSSI register 0x824
++#define bCCKAntennaPolarity 0x2000
++#define bCCKTxFilterType 0x0c00
++#define bCCKRxAGCReportType 0x0300
++#define bCCKRxDAGCEn 0x80000000
++#define bCCKRxDAGCPeriod 0x20000000
++#define bCCKRxDAGCSatLevel 0x1f000000
++#define bCCKTimingRecovery 0x800000
++#define bCCKTxC0 0x3f0000
++#define bCCKTxC1 0x3f000000
++#define bCCKTxC2 0x3f
++#define bCCKTxC3 0x3f00
++#define bCCKTxC4 0x3f0000
++#define bCCKTxC5 0x3f000000
++#define bCCKTxC6 0x3f
++#define bCCKTxC7 0x3f00
++#define bCCKDebugPort 0xff0000
++#define bCCKDACDebug 0x0f000000
++#define bCCKFalseAlarmEnable 0x8000
++#define bCCKFalseAlarmRead 0x4000
++#define bCCKTRSSI 0x7f
++#define bCCKRxAGCReport 0xfe
++#define bCCKRxReport_AntSel 0x80000000
++#define bCCKRxReport_MFOff 0x40000000
++#define bCCKRxRxReport_SQLoss 0x20000000
++#define bCCKRxReport_Pktloss 0x10000000
++#define bCCKRxReport_Lockedbit 0x08000000
++#define bCCKRxReport_RateError 0x04000000
++#define bCCKRxReport_RxRate 0x03000000
++#define bCCKRxFACounterLower 0xff
++#define bCCKRxFACounterUpper 0xff000000
++#define bCCKRxHPAGCStart 0xe000
++#define bCCKRxHPAGCFinal 0x1c00
++#define bCCKRxFalseAlarmEnable 0x8000
++#define bCCKFACounterFreeze 0x4000
++#define bCCKTxPathSel 0x10000000
++#define bCCKDefaultRxPath 0xc000000
++#define bCCKOptionRxPath 0x3000000
++
++// 5. PageC(0xC00)
++#define bNumOfSTF 0x3 // Useless
++#define bShift_L 0xc0
++#define bGI_TH 0xc
++#define bRxPathA 0x1
++#define bRxPathB 0x2
++#define bRxPathC 0x4
++#define bRxPathD 0x8
++#define bTxPathA 0x1
++#define bTxPathB 0x2
++#define bTxPathC 0x4
++#define bTxPathD 0x8
++#define bTRSSIFreq 0x200
++#define bADCBackoff 0x3000
++#define bDFIRBackoff 0xc000
++#define bTRSSILatchPhase 0x10000
++#define bRxIDCOffset 0xff
++#define bRxQDCOffset 0xff00
++#define bRxDFIRMode 0x1800000
++#define bRxDCNFType 0xe000000
++#define bRXIQImb_A 0x3ff
++#define bRXIQImb_B 0xfc00
++#define bRXIQImb_C 0x3f0000
++#define bRXIQImb_D 0xffc00000
++#define bDC_dc_Notch 0x60000
++#define bRxNBINotch 0x1f000000
++#define bPD_TH 0xf
++#define bPD_TH_Opt2 0xc000
++#define bPWED_TH 0x700
++#define bIfMF_Win_L 0x800
++#define bPD_Option 0x1000
++#define bMF_Win_L 0xe000
++#define bBW_Search_L 0x30000
++#define bwin_enh_L 0xc0000
++#define bBW_TH 0x700000
++#define bED_TH2 0x3800000
++#define bBW_option 0x4000000
++#define bRatio_TH 0x18000000
++#define bWindow_L 0xe0000000
++#define bSBD_Option 0x1
++#define bFrame_TH 0x1c
++#define bFS_Option 0x60
++#define bDC_Slope_check 0x80
++#define bFGuard_Counter_DC_L 0xe00
++#define bFrame_Weight_Short 0x7000
++#define bSub_Tune 0xe00000
++#define bFrame_DC_Length 0xe000000
++#define bSBD_start_offset 0x30000000
++#define bFrame_TH_2 0x7
++#define bFrame_GI2_TH 0x38
++#define bGI2_Sync_en 0x40
++#define bSarch_Short_Early 0x300
++#define bSarch_Short_Late 0xc00
++#define bSarch_GI2_Late 0x70000
++#define bCFOAntSum 0x1
++#define bCFOAcc 0x2
++#define bCFOStartOffset 0xc
++#define bCFOLookBack 0x70
++#define bCFOSumWeight 0x80
++#define bDAGCEnable 0x10000
++#define bTXIQImb_A 0x3ff
++#define bTXIQImb_B 0xfc00
++#define bTXIQImb_C 0x3f0000
++#define bTXIQImb_D 0xffc00000
++#define bTxIDCOffset 0xff
++#define bTxQDCOffset 0xff00
++#define bTxDFIRMode 0x10000
++#define bTxPesudoNoiseOn 0x4000000
++#define bTxPesudoNoise_A 0xff
++#define bTxPesudoNoise_B 0xff00
++#define bTxPesudoNoise_C 0xff0000
++#define bTxPesudoNoise_D 0xff000000
++#define bCCADropOption 0x20000
++#define bCCADropThres 0xfff00000
++#define bEDCCA_H 0xf
++#define bEDCCA_L 0xf0
++#define bLambda_ED 0x300
++#define bRxInitialGain 0x7f
++#define bRxAntDivEn 0x80
++#define bRxAGCAddressForLNA 0x7f00
++#define bRxHighPowerFlow 0x8000
++#define bRxAGCFreezeThres 0xc0000
++#define bRxFreezeStep_AGC1 0x300000
++#define bRxFreezeStep_AGC2 0xc00000
++#define bRxFreezeStep_AGC3 0x3000000
++#define bRxFreezeStep_AGC0 0xc000000
++#define bRxRssi_Cmp_En 0x10000000
++#define bRxQuickAGCEn 0x20000000
++#define bRxAGCFreezeThresMode 0x40000000
++#define bRxOverFlowCheckType 0x80000000
++#define bRxAGCShift 0x7f
++#define bTRSW_Tri_Only 0x80
++#define bPowerThres 0x300
++#define bRxAGCEn 0x1
++#define bRxAGCTogetherEn 0x2
++#define bRxAGCMin 0x4
++#define bRxHP_Ini 0x7
++#define bRxHP_TRLNA 0x70
++#define bRxHP_RSSI 0x700
++#define bRxHP_BBP1 0x7000
++#define bRxHP_BBP2 0x70000
++#define bRxHP_BBP3 0x700000
++#define bRSSI_H 0x7f0000 //the threshold for high power
++#define bRSSI_Gen 0x7f000000 //the threshold for ant diversity
++#define bRxSettle_TRSW 0x7
++#define bRxSettle_LNA 0x38
++#define bRxSettle_RSSI 0x1c0
++#define bRxSettle_BBP 0xe00
++#define bRxSettle_RxHP 0x7000
++#define bRxSettle_AntSW_RSSI 0x38000
++#define bRxSettle_AntSW 0xc0000
++#define bRxProcessTime_DAGC 0x300000
++#define bRxSettle_HSSI 0x400000
++#define bRxProcessTime_BBPPW 0x800000
++#define bRxAntennaPowerShift 0x3000000
++#define bRSSITableSelect 0xc000000
++#define bRxHP_Final 0x7000000
++#define bRxHTSettle_BBP 0x7
++#define bRxHTSettle_HSSI 0x8
++#define bRxHTSettle_RxHP 0x70
++#define bRxHTSettle_BBPPW 0x80
++#define bRxHTSettle_Idle 0x300
++#define bRxHTSettle_Reserved 0x1c00
++#define bRxHTRxHPEn 0x8000
++#define bRxHTAGCFreezeThres 0x30000
++#define bRxHTAGCTogetherEn 0x40000
++#define bRxHTAGCMin 0x80000
++#define bRxHTAGCEn 0x100000
++#define bRxHTDAGCEn 0x200000
++#define bRxHTRxHP_BBP 0x1c00000
++#define bRxHTRxHP_Final 0xe0000000
++#define bRxPWRatioTH 0x3
++#define bRxPWRatioEn 0x4
++#define bRxMFHold 0x3800
++#define bRxPD_Delay_TH1 0x38
++#define bRxPD_Delay_TH2 0x1c0
++#define bRxPD_DC_COUNT_MAX 0x600
++//#define bRxMF_Hold 0x3800
++#define bRxPD_Delay_TH 0x8000
++#define bRxProcess_Delay 0xf0000
++#define bRxSearchrange_GI2_Early 0x700000
++#define bRxFrame_Guard_Counter_L 0x3800000
++#define bRxSGI_Guard_L 0xc000000
++#define bRxSGI_Search_L 0x30000000
++#define bRxSGI_TH 0xc0000000
++#define bDFSCnt0 0xff
++#define bDFSCnt1 0xff00
++#define bDFSFlag 0xf0000
++#define bMFWeightSum 0x300000
++#define bMinIdxTH 0x7f000000
++#define bDAFormat 0x40000
++#define bTxChEmuEnable 0x01000000
++#define bTRSWIsolation_A 0x7f
++#define bTRSWIsolation_B 0x7f00
++#define bTRSWIsolation_C 0x7f0000
++#define bTRSWIsolation_D 0x7f000000
++#define bExtLNAGain 0x7c00
++
++// 6. PageE(0xE00)
++#define bSTBCEn 0x4 // Useless
++#define bAntennaMapping 0x10
++#define bNss 0x20
++#define bCFOAntSumD 0x200
++#define bPHYCounterReset 0x8000000
++#define bCFOReportGet 0x4000000
++#define bOFDMContinueTx 0x10000000
++#define bOFDMSingleCarrier 0x20000000
++#define bOFDMSingleTone 0x40000000
++//#define bRxPath1 0x01
++//#define bRxPath2 0x02
++//#define bRxPath3 0x04
++//#define bRxPath4 0x08
++//#define bTxPath1 0x10
++//#define bTxPath2 0x20
++#define bHTDetect 0x100
++#define bCFOEn 0x10000
++#define bCFOValue 0xfff00000
++#define bSigTone_Re 0x3f
++#define bSigTone_Im 0x7f00
++#define bCounter_CCA 0xffff
++#define bCounter_ParityFail 0xffff0000
++#define bCounter_RateIllegal 0xffff
++#define bCounter_CRC8Fail 0xffff0000
++#define bCounter_MCSNoSupport 0xffff
++#define bCounter_FastSync 0xffff
++#define bShortCFO 0xfff
++#define bShortCFOTLength 12 //total
++#define bShortCFOFLength 11 //fraction
++#define bLongCFO 0x7ff
++#define bLongCFOTLength 11
++#define bLongCFOFLength 11
++#define bTailCFO 0x1fff
++#define bTailCFOTLength 13
++#define bTailCFOFLength 12
++#define bmax_en_pwdB 0xffff
++#define bCC_power_dB 0xffff0000
++#define bnoise_pwdB 0xffff
++#define bPowerMeasTLength 10
++#define bPowerMeasFLength 3
++#define bRx_HT_BW 0x1
++#define bRxSC 0x6
++#define bRx_HT 0x8
++#define bNB_intf_det_on 0x1
++#define bIntf_win_len_cfg 0x30
++#define bNB_Intf_TH_cfg 0x1c0
++#define bRFGain 0x3f
++#define bTableSel 0x40
++#define bTRSW 0x80
++#define bRxSNR_A 0xff
++#define bRxSNR_B 0xff00
++#define bRxSNR_C 0xff0000
++#define bRxSNR_D 0xff000000
++#define bSNREVMTLength 8
++#define bSNREVMFLength 1
++#define bCSI1st 0xff
++#define bCSI2nd 0xff00
++#define bRxEVM1st 0xff0000
++#define bRxEVM2nd 0xff000000
++#define bSIGEVM 0xff
++#define bPWDB 0xff00
++#define bSGIEN 0x10000
++
++#define bSFactorQAM1 0xf // Useless
++#define bSFactorQAM2 0xf0
++#define bSFactorQAM3 0xf00
++#define bSFactorQAM4 0xf000
++#define bSFactorQAM5 0xf0000
++#define bSFactorQAM6 0xf0000
++#define bSFactorQAM7 0xf00000
++#define bSFactorQAM8 0xf000000
++#define bSFactorQAM9 0xf0000000
++#define bCSIScheme 0x100000
++
++#define bNoiseLvlTopSet 0x3 // Useless
++#define bChSmooth 0x4
++#define bChSmoothCfg1 0x38
++#define bChSmoothCfg2 0x1c0
++#define bChSmoothCfg3 0xe00
++#define bChSmoothCfg4 0x7000
++#define bMRCMode 0x800000
++#define bTHEVMCfg 0x7000000
++
++#define bLoopFitType 0x1 // Useless
++#define bUpdCFO 0x40
++#define bUpdCFOOffData 0x80
++#define bAdvUpdCFO 0x100
++#define bAdvTimeCtrl 0x800
++#define bUpdClko 0x1000
++#define bFC 0x6000
++#define bTrackingMode 0x8000
++#define bPhCmpEnable 0x10000
++#define bUpdClkoLTF 0x20000
++#define bComChCFO 0x40000
++#define bCSIEstiMode 0x80000
++#define bAdvUpdEqz 0x100000
++#define bUChCfg 0x7000000
++#define bUpdEqz 0x8000000
++
++//Rx Pseduo noise
++#define bRxPesudoNoiseOn 0x20000000 // Useless
++#define bRxPesudoNoise_A 0xff
++#define bRxPesudoNoise_B 0xff00
++#define bRxPesudoNoise_C 0xff0000
++#define bRxPesudoNoise_D 0xff000000
++#define bPesudoNoiseState_A 0xffff
++#define bPesudoNoiseState_B 0xffff0000
++#define bPesudoNoiseState_C 0xffff
++#define bPesudoNoiseState_D 0xffff0000
++
++//7. RF Register
++//Zebra1
++#define bZebra1_HSSIEnable 0x8 // Useless
++#define bZebra1_TRxControl 0xc00
++#define bZebra1_TRxGainSetting 0x07f
++#define bZebra1_RxCorner 0xc00
++#define bZebra1_TxChargePump 0x38
++#define bZebra1_RxChargePump 0x7
++#define bZebra1_ChannelNum 0xf80
++#define bZebra1_TxLPFBW 0x400
++#define bZebra1_RxLPFBW 0x600
++
++//Zebra4
++#define bRTL8256RegModeCtrl1 0x100 // Useless
++#define bRTL8256RegModeCtrl0 0x40
++#define bRTL8256_TxLPFBW 0x18
++#define bRTL8256_RxLPFBW 0x600
++
++//RTL8258
++#define bRTL8258_TxLPFBW 0xc // Useless
++#define bRTL8258_RxLPFBW 0xc00
++#define bRTL8258_RSSILPFBW 0xc0
++
++
++//
++// Other Definition
++//
++
++//byte endable for sb_write
++#define bByte0 0x1 // Useless
++#define bByte1 0x2
++#define bByte2 0x4
++#define bByte3 0x8
++#define bWord0 0x3
++#define bWord1 0xc
++#define bDWord 0xf
++
++//for PutRegsetting & GetRegSetting BitMask
++#define bMaskByte0 0xff // Reg 0xc50 rOFDM0_XAAGCCore~0xC6f
++#define bMaskByte1 0xff00
++#define bMaskByte2 0xff0000
++#define bMaskByte3 0xff000000
++#define bMaskHWord 0xffff0000
++#define bMaskLWord 0x0000ffff
++#define bMaskDWord 0xffffffff
++#define bMask12Bits 0xfff
++#define bMaskH4Bits 0xf0000000
++#define bMaskOFDM_D 0xffc00000
++#define bMaskCCK 0x3f3f3f3f
++
++//for PutRFRegsetting & GetRFRegSetting BitMask
++//#define bMask12Bits 0xfffff // RF Reg mask bits
++//#define bMask20Bits 0xfffff // RF Reg mask bits T65 RF
++#define bRFRegOffsetMask 0xfffff
++
++#define bEnable 0x1 // Useless
++#define bDisable 0x0
++
++#define LeftAntenna 0x0 // Useless
++#define RightAntenna 0x1
++
++#define tCheckTxStatus 500 //500ms // Useless
++#define tUpdateRxCounter 100 //100ms
++
++#define rateCCK 0 // Useless
++#define rateOFDM 1
++#define rateHT 2
++
++//define Register-End
++#define bPMAC_End 0x1ff // Useless
++#define bFPGAPHY0_End 0x8ff
++#define bFPGAPHY1_End 0x9ff
++#define bCCKPHY0_End 0xaff
++#define bOFDMPHY0_End 0xcff
++#define bOFDMPHY1_End 0xdff
++
++//define max debug item in each debug page
++//#define bMaxItem_FPGA_PHY0 0x9
++//#define bMaxItem_FPGA_PHY1 0x3
++//#define bMaxItem_PHY_11B 0x16
++//#define bMaxItem_OFDM_PHY0 0x29
++//#define bMaxItem_OFDM_PHY1 0x0
++
++#define bPMACControl 0x0 // Useless
++#define bWMACControl 0x1
++#define bWNICControl 0x2
++
++#define PathA 0x0 // Useless
++#define PathB 0x1
++#define PathC 0x2
++#define PathD 0x3
++
++/*--------------------------Define Parameters-------------------------------*/
++
++
++#endif //__INC_HAL8192SPHYREG_H
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/Hal8192CUHWImg.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/Hal8192CUHWImg.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/Hal8192CUHWImg.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/Hal8192CUHWImg.h 2015-07-28 01:20:58.317611539 +0200
+@@ -0,0 +1,105 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef __INC_HAL8192CU_FW_IMG_H
++#define __INC_HAL8192CU_FW_IMG_H
++
++/*Created on 2011/ 6/15, 5:45*/
++
++#ifdef CONFIG_BT_COEXISTENCE
++#define TSMCImgArrayLength 15706 //v84 TSMC COMMON 2012-04-13
++#else //#ifdef CONFIG_P2P
++#define TSMCImgArrayLength 16126 //v88 TSMC P2PPS with CCX report C2H 2012-12-05
++#endif
++extern u8 Rtl8192CUFwTSMCImgArray[TSMCImgArrayLength];
++
++#ifdef CONFIG_BT_COEXISTENCE
++#define UMCACutImgArrayLength 16248 //v79 UMC A Cut COMMON 2011-10-06
++#else //#ifdef CONFIG_P2P
++#define UMCACutImgArrayLength 16126 //v88 UMC A Cut P2PPS with CCX report C2H 2012-12-05
++#endif
++extern u8 Rtl8192CUFwUMCACutImgArray[UMCACutImgArrayLength];
++
++#ifdef CONFIG_BT_COEXISTENCE
++#define UMCBCutImgArrayLength 15686 //v84 UMC B Cut COMMON 2012-04-13
++#else //#ifdef CONFIG_P2P
++#define UMCBCutImgArrayLength 16096 //v88 UMC B Cut P2PPS with CCX report C2H 2012-12-05
++#endif
++extern u8 Rtl8192CUFwUMCBCutImgArray[UMCBCutImgArrayLength];
++
++//8188C_Formal_All_PHYforMP_111117 2011-11-23
++//8192C_Formal_92CU_PHYforMP_110817 2011-11-23
++#define PHY_REG_2TArrayLength 374
++extern u32 Rtl8192CUPHY_REG_2TArray[PHY_REG_2TArrayLength];
++#define PHY_REG_1TArrayLength 374
++extern u32 Rtl8192CUPHY_REG_1TArray[PHY_REG_1TArrayLength];
++#define PHY_ChangeTo_1T1RArrayLength 1
++extern u32 Rtl8192CUPHY_ChangeTo_1T1RArray[PHY_ChangeTo_1T1RArrayLength];
++#define PHY_ChangeTo_1T2RArrayLength 1
++extern u32 Rtl8192CUPHY_ChangeTo_1T2RArray[PHY_ChangeTo_1T2RArrayLength];
++#define PHY_ChangeTo_2T2RArrayLength 1
++extern u32 Rtl8192CUPHY_ChangeTo_2T2RArray[PHY_ChangeTo_2T2RArrayLength];
++#define PHY_REG_Array_PGLength 336
++extern u32 Rtl8192CUPHY_REG_Array_PG[PHY_REG_Array_PGLength];
++#define PHY_REG_Array_PG_mCardLength 336
++extern u32 Rtl8192CUPHY_REG_Array_PG_mCard[PHY_REG_Array_PG_mCardLength];
++#define PHY_REG_Array_MPLength 4
++extern u32 Rtl8192CUPHY_REG_Array_MP[PHY_REG_Array_MPLength];
++#define PHY_REG_1T_HPArrayLength 378
++extern u32 Rtl8192CUPHY_REG_1T_HPArray[PHY_REG_1T_HPArrayLength];
++#define PHY_REG_1T_mCardArrayLength 374
++extern u32 Rtl8192CUPHY_REG_1T_mCardArray[PHY_REG_1T_mCardArrayLength];
++#define PHY_REG_2T_mCardArrayLength 374
++extern u32 Rtl8192CUPHY_REG_2T_mCardArray[PHY_REG_2T_mCardArrayLength];
++#define PHY_REG_Array_PG_HPLength 336
++extern u32 Rtl8192CUPHY_REG_Array_PG_HP[PHY_REG_Array_PG_HPLength];
++#define RadioA_2TArrayLength 282
++extern u32 Rtl8192CURadioA_2TArray[RadioA_2TArrayLength];
++#define RadioB_2TArrayLength 78
++extern u32 Rtl8192CURadioB_2TArray[RadioB_2TArrayLength];
++#define RadioA_1TArrayLength 282
++extern u32 Rtl8192CURadioA_1TArray[RadioA_1TArrayLength];
++#define RadioB_1TArrayLength 1
++extern u32 Rtl8192CURadioB_1TArray[RadioB_1TArrayLength];
++#define RadioA_2T_mCardArrayLength 282
++extern u32 Rtl8192CURadioA_2T_mCardArray[RadioA_2T_mCardArrayLength];
++#define RadioB_2T_mCardArrayLength 78
++extern u32 Rtl8192CURadioB_2T_mCardArray[RadioB_2T_mCardArrayLength];
++#define RadioA_1T_mCardArrayLength 282
++extern u32 Rtl8192CURadioA_1T_mCardArray[RadioA_1T_mCardArrayLength];
++#define RadioB_1T_mCardArrayLength 1
++extern u32 Rtl8192CURadioB_1T_mCardArray[RadioB_1T_mCardArrayLength];
++#define RadioA_1T_HPArrayLength 282
++extern u32 Rtl8192CURadioA_1T_HPArray[RadioA_1T_HPArrayLength];
++#define RadioB_GM_ArrayLength 1
++extern u32 Rtl8192CURadioB_GM_Array[RadioB_GM_ArrayLength];
++
++// MAC reg V14 - 2011-11-23
++#define MAC_2T_ArrayLength 174
++extern u32 Rtl8192CUMAC_2T_Array[MAC_2T_ArrayLength];
++#define MACPHY_Array_PGLength 1
++extern u32 Rtl8192CUMACPHY_Array_PG[MACPHY_Array_PGLength];
++#define AGCTAB_2TArrayLength 320
++extern u32 Rtl8192CUAGCTAB_2TArray[AGCTAB_2TArrayLength];
++#define AGCTAB_1TArrayLength 320
++extern u32 Rtl8192CUAGCTAB_1TArray[AGCTAB_1TArrayLength];
++#define AGCTAB_1T_HPArrayLength 320
++extern u32 Rtl8192CUAGCTAB_1T_HPArray[AGCTAB_1T_HPArrayLength];
++
++#endif //__INC_HAL8192CU_FW_IMG_H
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/Hal8192CUHWImg_wowlan.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/Hal8192CUHWImg_wowlan.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/Hal8192CUHWImg_wowlan.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/Hal8192CUHWImg_wowlan.h 2015-07-28 01:20:58.317611539 +0200
+@@ -0,0 +1,33 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef __INC_HAL8192CU_FW_IMG_WOWLAN_H
++#define __INC_HAL8192CU_FW_IMG_WOWLAN_H
++
++/*Created on 2011/11/ 8, 14:15*/
++
++
++#define TSMCWWImgArrayLength 13458
++extern u8 Rtl8192CUFwTSMCWWImgArray[TSMCWWImgArrayLength];
++#define UMCACutWWImgArrayLength 13458
++extern u8 Rtl8192CUFwUMCACutWWImgArray[UMCACutWWImgArrayLength];
++#define UMCBCutWWImgArrayLength 13446
++extern u8 Rtl8192CUFwUMCBCutWWImgArray[UMCBCutWWImgArrayLength];
++
++#endif //__INC_HAL8192CU_FW_IMG_WOWLAN_H
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/Hal8192DEHWImg.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/Hal8192DEHWImg.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/Hal8192DEHWImg.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/Hal8192DEHWImg.h 2015-07-28 01:20:58.317611539 +0200
+@@ -0,0 +1,66 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef __INC_HAL8192DE_FW_IMG_H
++#define __INC_HAL8192DE_FW_IMG_H
++
++#include <basic_types.h>
++
++/*Created on 2011/11/11, 8: 8*/
++
++#define Rtl8192DEImgArrayLength 32296
++extern const u8 Rtl8192DEFwImgArray[Rtl8192DEImgArrayLength];
++#define Rtl8192DEMainArrayLength 1
++extern const u8 Rtl8192DEFwMainArray[Rtl8192DEMainArrayLength];
++#define Rtl8192DEDataArrayLength 1
++extern const u8 Rtl8192DEFwDataArray[Rtl8192DEDataArrayLength];
++#define Rtl8192DEPHY_REG_2TArrayLength 372
++extern const u32 Rtl8192DEPHY_REG_2TArray[Rtl8192DEPHY_REG_2TArrayLength];
++#define Rtl8192DEPHY_REG_1TArrayLength 1
++extern const u32 Rtl8192DEPHY_REG_1TArray[Rtl8192DEPHY_REG_1TArrayLength];
++#define Rtl8192DEPHY_REG_Array_PGLength 624
++extern const u32 Rtl8192DEPHY_REG_Array_PG[Rtl8192DEPHY_REG_Array_PGLength];
++#define Rtl8192DEPHY_REG_Array_MPLength 12
++extern const u32 Rtl8192DEPHY_REG_Array_MP[Rtl8192DEPHY_REG_Array_MPLength];
++#define Rtl8192DERadioA_2TArrayLength 378
++extern const u32 Rtl8192DERadioA_2TArray[Rtl8192DERadioA_2TArrayLength];
++#define Rtl8192DERadioB_2TArrayLength 384
++extern const u32 Rtl8192DERadioB_2TArray[Rtl8192DERadioB_2TArrayLength];
++#define Rtl8192DERadioA_1TArrayLength 1
++extern const u32 Rtl8192DERadioA_1TArray[Rtl8192DERadioA_1TArrayLength];
++#define Rtl8192DERadioB_1TArrayLength 1
++extern const u32 Rtl8192DERadioB_1TArray[Rtl8192DERadioB_1TArrayLength];
++#define Rtl8192DERadioA_2T_intPAArrayLength 378
++extern const u32 Rtl8192DERadioA_2T_intPAArray[Rtl8192DERadioA_2T_intPAArrayLength];
++#define Rtl8192DERadioB_2T_intPAArrayLength 384
++extern const u32 Rtl8192DERadioB_2T_intPAArray[Rtl8192DERadioB_2T_intPAArrayLength];
++#define Rtl8192DEMAC_2T_ArrayLength 192
++extern const u32 Rtl8192DEMAC_2T_Array[Rtl8192DEMAC_2T_ArrayLength];
++#define Rtl8192DEAGCTAB_ArrayLength 386
++extern const u32 Rtl8192DEAGCTAB_Array[Rtl8192DEAGCTAB_ArrayLength];
++#define Rtl8192DEAGCTAB_5GArrayLength 194
++extern const u32 Rtl8192DEAGCTAB_5GArray[Rtl8192DEAGCTAB_5GArrayLength];
++#define Rtl8192DEAGCTAB_2GArrayLength 194
++extern const u32 Rtl8192DEAGCTAB_2GArray[Rtl8192DEAGCTAB_2GArrayLength];
++#define Rtl8192DEAGCTAB_2TArrayLength 1
++extern const u32 Rtl8192DEAGCTAB_2TArray[Rtl8192DEAGCTAB_2TArrayLength];
++#define Rtl8192DEAGCTAB_1TArrayLength 1
++extern const u32 Rtl8192DEAGCTAB_1TArray[Rtl8192DEAGCTAB_1TArrayLength];
++
++#endif //__INC_HAL8192CU_FW_IMG_H
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/Hal8192DPhyCfg.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/Hal8192DPhyCfg.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/Hal8192DPhyCfg.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/Hal8192DPhyCfg.h 2015-07-28 01:20:58.317611539 +0200
+@@ -0,0 +1,527 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++/*****************************************************************************
++ *
++ * Module: __INC_HAL8192DPHYCFG_H
++ *
++ *
++ * Note:
++ *
++ *
++ * Export: Constants, macro, functions(API), global variables(None).
++ *
++ * Abbrev:
++ *
++ * History:
++ * Data Who Remark
++ * 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h.
++ * 2. Reorganize code architecture.
++ *
++ *****************************************************************************/
++ /* Check to see if the file has been included already. */
++#ifndef __INC_HAL8192DPHYCFG_H
++#define __INC_HAL8192DPHYCFG_H
++
++
++/*--------------------------Define Parameters-------------------------------*/
++#define LOOP_LIMIT 5
++#define MAX_STALL_TIME 50 //us
++#define AntennaDiversityValue 0x80 //(Adapter->bSoftwareAntennaDiversity ? 0x00:0x80)
++#define MAX_TXPWR_IDX_NMODE_92S 63
++#define Reset_Cnt_Limit 3
++
++
++#define IQK_MAC_REG_NUM 4
++#define IQK_ADDA_REG_NUM 16
++#define IQK_BB_REG_NUM 10
++#define IQK_BB_REG_NUM_92C 9
++#define IQK_BB_REG_NUM_92D 10
++#define IQK_BB_REG_NUM_test 6
++#define index_mapping_NUM 13
++#define Rx_index_mapping_NUM 15
++#define AVG_THERMAL_NUM 8
++#define IQK_Matrix_REG_NUM 8
++#define IQK_Matrix_Settings_NUM 1+24+21
++
++#ifdef CONFIG_PCI_HCI
++#define SET_RTL8192SE_RF_SLEEP(_pAdapter) \
++{ \
++ u1Byte u1bTmp; \
++ u1bTmp = PlatformEFIORead1Byte(_pAdapter, REG_LDOV12D_CTRL); \
++ u1bTmp |= BIT0; \
++ PlatformEFIOWrite1Byte(_pAdapter, REG_LDOV12D_CTRL, u1bTmp); \
++ PlatformEFIOWrite1Byte(_pAdapter, REG_SPS_OCP_CFG, 0x0); \
++ PlatformEFIOWrite1Byte(_pAdapter, TXPAUSE, 0xFF); \
++ PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x57FC); \
++ delay_us(100); \
++ PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x77FC); \
++ PlatformEFIOWrite1Byte(_pAdapter, PHY_CCA, 0x0); \
++ delay_us(10); \
++ PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x37FC); \
++ delay_us(10); \
++ PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x77FC); \
++ delay_us(10); \
++ PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x57FC); \
++}
++#endif
++
++
++/*--------------------------Define Parameters-------------------------------*/
++
++
++/*------------------------------Define structure----------------------------*/
++typedef enum _SwChnlCmdID{
++ CmdID_End,
++ CmdID_SetTxPowerLevel,
++ CmdID_BBRegWrite10,
++ CmdID_WritePortUlong,
++ CmdID_WritePortUshort,
++ CmdID_WritePortUchar,
++ CmdID_RF_WriteReg,
++}SwChnlCmdID;
++
++
++/* 1. Switch channel related */
++typedef struct _SwChnlCmd{
++ SwChnlCmdID CmdID;
++ u32 Para1;
++ u32 Para2;
++ u32 msDelay;
++}SwChnlCmd;
++
++typedef enum _HW90_BLOCK{
++ HW90_BLOCK_MAC = 0,
++ HW90_BLOCK_PHY0 = 1,
++ HW90_BLOCK_PHY1 = 2,
++ HW90_BLOCK_RF = 3,
++ HW90_BLOCK_MAXIMUM = 4, // Never use this
++}HW90_BLOCK_E, *PHW90_BLOCK_E;
++
++//vivi added this for read parameter from header, 20100908
++typedef enum _RF_CONTENT{
++ radioa_txt = 0x1000,
++ radiob_txt = 0x1001,
++ radioc_txt = 0x1002,
++ radiod_txt = 0x1003
++} RF_CONTENT;
++
++#define RF_PATH_MAX 2
++
++typedef enum _WIRELESS_MODE {
++ WIRELESS_MODE_UNKNOWN = 0x00,
++ WIRELESS_MODE_A = 0x01,
++ WIRELESS_MODE_B = 0x02,
++ WIRELESS_MODE_G = 0x04,
++ WIRELESS_MODE_AUTO = 0x08,
++ WIRELESS_MODE_N_24G = 0x10,
++ WIRELESS_MODE_N_5G = 0x20
++} WIRELESS_MODE;
++
++
++#define CHANNEL_MAX_NUMBER 14+24+21 // 14 is the max channel number
++#define CHANNEL_GROUP_MAX 3+9 // ch1~3, ch4~9, ch10~14 total three groups
++#define MAX_PG_GROUP 13
++
++#define CHANNEL_GROUP_MAX_2G 3
++#define CHANNEL_GROUP_IDX_5GL 3
++#define CHANNEL_GROUP_IDX_5GM 6
++#define CHANNEL_GROUP_IDX_5GH 9
++#define CHANNEL_GROUP_MAX_5G 9
++#define CHANNEL_MAX_NUMBER_2G 14
++
++typedef enum _BaseBand_Config_Type{
++ BaseBand_Config_PHY_REG = 0, //Radio Path A
++ BaseBand_Config_AGC_TAB = 1, //Radio Path B
++}BaseBand_Config_Type, *PBaseBand_Config_Type;
++
++typedef enum _MACPHY_MODE_8192D{
++ SINGLEMAC_SINGLEPHY,
++ DUALMAC_DUALPHY,
++ DUALMAC_SINGLEPHY,
++}MACPHY_MODE_8192D,*PMACPHY_MODE_8192D;
++
++typedef enum _MACPHY_MODE_CHANGE_ACTION{
++ DMDP2DMSP = 0,
++ DMSP2DMDP = 1,
++ DMDP2SMSP = 2,
++ SMSP2DMDP = 3,
++ DMSP2SMSP = 4,
++ SMSP2DMSP = 5,
++ MAXACTION
++}MACPHY_MODE_CHANGE_ACTION,*PMACPHY_MODE_CHANGE_ACTION;
++
++typedef enum _BAND_TYPE{
++ BAND_ON_2_4G = 0,
++ BAND_ON_5G,
++ BAND_ON_BOTH,
++ BANDMAX
++}BAND_TYPE,*PBAND_TYPE;
++
++typedef enum _PHY_Rate_Tx_Power_Offset_Area{
++ RA_OFFSET_LEGACY_OFDM1,
++ RA_OFFSET_LEGACY_OFDM2,
++ RA_OFFSET_HT_OFDM1,
++ RA_OFFSET_HT_OFDM2,
++ RA_OFFSET_HT_OFDM3,
++ RA_OFFSET_HT_OFDM4,
++ RA_OFFSET_HT_CCK,
++}RA_OFFSET_AREA,*PRA_OFFSET_AREA;
++
++
++/* BB/RF related */
++typedef enum _RF_TYPE_8190P{
++ RF_TYPE_MIN, // 0
++ RF_8225=1, // 1 11b/g RF for verification only
++ RF_8256=2, // 2 11b/g/n
++ RF_8258=3, // 3 11a/b/g/n RF
++ RF_6052=4, // 4 11b/g/n RF
++ //RF_6052=5, // 4 11b/g/n RF
++ // TODO: We sholud remove this psudo PHY RF after we get new RF.
++ RF_PSEUDO_11N=5, // 5, It is a temporality RF.
++}RF_TYPE_8190P_E,*PRF_TYPE_8190P_E;
++
++typedef struct _BB_REGISTER_DEFINITION{
++ u32 rfintfs; // set software control:
++ // 0x870~0x877[8 bytes]
++
++ u32 rfintfi; // readback data:
++ // 0x8e0~0x8e7[8 bytes]
++
++ u32 rfintfo; // output data:
++ // 0x860~0x86f [16 bytes]
++
++ u32 rfintfe; // output enable:
++ // 0x860~0x86f [16 bytes]
++
++ u32 rf3wireOffset; // LSSI data:
++ // 0x840~0x84f [16 bytes]
++
++ u32 rfLSSI_Select; // BB Band Select:
++ // 0x878~0x87f [8 bytes]
++
++ u32 rfTxGainStage; // Tx gain stage:
++ // 0x80c~0x80f [4 bytes]
++
++ u32 rfHSSIPara1; // wire parameter control1 :
++ // 0x820~0x823,0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes]
++
++ u32 rfHSSIPara2; // wire parameter control2 :
++ // 0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes]
++
++ u32 rfSwitchControl; //Tx Rx antenna control :
++ // 0x858~0x85f [16 bytes]
++
++ u32 rfAGCControl1; //AGC parameter control1 :
++ // 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes]
++
++ u32 rfAGCControl2; //AGC parameter control2 :
++ // 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes]
++
++ u32 rfRxIQImbalance; //OFDM Rx IQ imbalance matrix :
++ // 0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes]
++
++ u32 rfRxAFE; //Rx IQ DC ofset and Rx digital filter, Rx DC notch filter :
++ // 0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes]
++
++ u32 rfTxIQImbalance; //OFDM Tx IQ imbalance matrix
++ // 0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes]
++
++ u32 rfTxAFE; //Tx IQ DC Offset and Tx DFIR type
++ // 0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes]
++
++ u32 rfLSSIReadBack; //LSSI RF readback data SI mode
++ // 0x8a0~0x8af [16 bytes]
++
++ u32 rfLSSIReadBackPi; //LSSI RF readback data PI mode 0x8b8-8bc for Path A and B
++
++}BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T;
++
++#ifdef CONFIG_MP_INCLUDED
++typedef enum _ANTENNA_PATH{
++ ANTENNA_NONE = 0x00,
++ ANTENNA_D ,
++ ANTENNA_C ,
++ ANTENNA_CD ,
++ ANTENNA_B ,
++ ANTENNA_BD ,
++ ANTENNA_BC ,
++ ANTENNA_BCD ,
++ ANTENNA_A ,
++ ANTENNA_AD ,
++ ANTENNA_AC ,
++ ANTENNA_ACD ,
++ ANTENNA_AB ,
++ ANTENNA_ABD ,
++ ANTENNA_ABC ,
++ ANTENNA_ABCD
++} ANTENNA_PATH;
++#endif
++
++typedef struct _R_ANTENNA_SELECT_OFDM{
++ u32 r_tx_antenna:4;
++ u32 r_ant_l:4;
++ u32 r_ant_non_ht:4;
++ u32 r_ant_ht1:4;
++ u32 r_ant_ht2:4;
++ u32 r_ant_ht_s1:4;
++ u32 r_ant_non_ht_s1:4;
++ u32 OFDM_TXSC:2;
++ u32 Reserved:2;
++}R_ANTENNA_SELECT_OFDM;
++
++typedef struct _R_ANTENNA_SELECT_CCK{
++ u8 r_cckrx_enable_2:2;
++ u8 r_cckrx_enable:2;
++ u8 r_ccktx_enable:4;
++}R_ANTENNA_SELECT_CCK;
++
++/*------------------------------Define structure----------------------------*/
++
++
++/*------------------------Export global variable----------------------------*/
++/*------------------------Export global variable----------------------------*/
++
++
++/*------------------------Export Marco Definition---------------------------*/
++/*------------------------Export Marco Definition---------------------------*/
++
++//Added for TX Power
++//u8 GetRightChnlPlace(u8 chnl);
++u8 rtl8192d_GetRightChnlPlaceforIQK(u8 chnl);
++u8 rtl8192d_getChnlGroupfromArray(u8 chnl);
++/*--------------------------Exported Function prototype---------------------*/
++//
++// BB and RF register read/write
++//
++void rtl8192d_PHY_SetBBReg1Byte( IN PADAPTER Adapter,
++ IN u32 RegAddr,
++ IN u32 BitMask,
++ IN u32 Data );
++u32 rtl8192d_PHY_QueryBBReg( IN PADAPTER Adapter,
++ IN u32 RegAddr,
++ IN u32 BitMask );
++void rtl8192d_PHY_SetBBReg( IN PADAPTER Adapter,
++ IN u32 RegAddr,
++ IN u32 BitMask,
++ IN u32 Data );
++u32 rtl8192d_PHY_QueryRFReg( IN PADAPTER Adapter,
++ IN RF_RADIO_PATH_E eRFPath,
++ IN u32 RegAddr,
++ IN u32 BitMask );
++void rtl8192d_PHY_SetRFReg( IN PADAPTER Adapter,
++ IN RF_RADIO_PATH_E eRFPath,
++ IN u32 RegAddr,
++ IN u32 BitMask,
++ IN u32 Data );
++
++//
++// Initialization related function
++//
++/* MAC/BB/RF HAL config */
++extern int PHY_MACConfig8192D( IN PADAPTER Adapter );
++extern int PHY_BBConfig8192D( IN PADAPTER Adapter );
++extern int PHY_RFConfig8192D( IN PADAPTER Adapter );
++/* RF config */
++int rtl8192d_PHY_ConfigRFWithParaFile( IN PADAPTER Adapter,
++ IN u8* pFileName,
++ IN RF_RADIO_PATH_E eRFPath);
++int rtl8192d_PHY_ConfigRFWithHeaderFile( IN PADAPTER Adapter,
++ IN RF_CONTENT Content,
++ IN RF_RADIO_PATH_E eRFPath);
++/* BB/RF readback check for making sure init OK */
++int rtl8192d_PHY_CheckBBAndRFOK( IN PADAPTER Adapter,
++ IN HW90_BLOCK_E CheckBlock,
++ IN RF_RADIO_PATH_E eRFPath );
++/* Read initi reg value for tx power setting. */
++void rtl8192d_PHY_GetHWRegOriginalValue( IN PADAPTER Adapter );
++
++//
++// RF Power setting
++//
++//extern BOOLEAN PHY_SetRFPowerState(IN PADAPTER Adapter,
++// IN RT_RF_POWER_STATE eRFPowerState);
++
++//
++// BB TX Power R/W
++//
++void PHY_GetTxPowerLevel8192D( IN PADAPTER Adapter,
++ OUT u32* powerlevel );
++void PHY_SetTxPowerLevel8192D( IN PADAPTER Adapter,
++ IN u8 channel );
++BOOLEAN PHY_UpdateTxPowerDbm8192D( IN PADAPTER Adapter,
++ IN int powerInDbm );
++
++//
++VOID
++PHY_ScanOperationBackup8192D(IN PADAPTER Adapter,
++ IN u8 Operation );
++
++//
++// Switch bandwidth for 8192S
++//
++//void PHY_SetBWModeCallback8192C( IN PRT_TIMER pTimer );
++void PHY_SetBWMode8192D( IN PADAPTER pAdapter,
++ IN HT_CHANNEL_WIDTH ChnlWidth,
++ IN unsigned char Offset );
++
++//
++// Set FW CMD IO for 8192S.
++//
++//extern BOOLEAN HalSetIO8192C( IN PADAPTER Adapter,
++// IN IO_TYPE IOType);
++
++//
++// Set A2 entry to fw for 8192S
++//
++extern void FillA2Entry8192C( IN PADAPTER Adapter,
++ IN u8 index,
++ IN u8* val);
++
++
++//
++// channel switch related funciton
++//
++//extern void PHY_SwChnlCallback8192C( IN PRT_TIMER pTimer );
++void PHY_SwChnl8192D( IN PADAPTER pAdapter,
++ IN u8 channel );
++ // Call after initialization
++void PHY_SwChnlPhy8192D( IN PADAPTER pAdapter,
++ IN u8 channel );
++
++extern void ChkFwCmdIoDone( IN PADAPTER Adapter);
++
++#ifdef USE_WORKITEM
++//extern void SetIOWorkItemCallback( IN PVOID pContext );
++#else
++//extern void SetIOTimerCallback( IN PRT_TIMER pTimer);
++#endif
++
++//
++// BB/MAC/RF other monitor API
++//
++void PHY_SetMonitorMode8192D(IN PADAPTER pAdapter,
++ IN BOOLEAN bEnableMonitorMode );
++
++BOOLEAN PHY_CheckIsLegalRfPath8192D(IN PADAPTER pAdapter,
++ IN u32 eRFPath );
++
++//
++// IQ calibrate
++//
++void rtl8192d_PHY_IQCalibrate( IN PADAPTER pAdapter);
++
++
++//
++// LC calibrate
++//
++void rtl8192d_PHY_LCCalibrate(IN PADAPTER pAdapter);
++
++//
++// AP calibrate
++//
++void rtl8192d_PHY_APCalibrate(IN PADAPTER pAdapter, IN char delta);
++
++
++//
++// Modify the value of the hw register when beacon interval be changed.
++//
++void
++rtl8192d_PHY_SetBeaconHwReg( IN PADAPTER Adapter,
++ IN u16 BeaconInterval );
++
++
++extern VOID
++PHY_SwitchEphyParameter(
++ IN PADAPTER Adapter
++ );
++
++extern VOID
++PHY_EnableHostClkReq(
++ IN PADAPTER Adapter
++ );
++
++BOOLEAN
++SetAntennaConfig92C(
++ IN PADAPTER Adapter,
++ IN u8 DefaultAnt
++ );
++
++VOID
++PHY_StopTRXBeforeChangeBand8192D(
++ PADAPTER Adapter
++);
++
++VOID
++PHY_UpdateBBRFConfiguration8192D(
++ IN PADAPTER Adapter,
++ IN BOOLEAN bisBandSwitch
++);
++
++VOID PHY_ReadMacPhyMode92D(
++ IN PADAPTER Adapter,
++ IN BOOLEAN AutoloadFail
++);
++
++VOID PHY_ConfigMacPhyMode92D(
++ IN PADAPTER Adapter
++);
++
++VOID PHY_ConfigMacPhyModeInfo92D(
++ IN PADAPTER Adapter
++);
++
++VOID PHY_ConfigMacCoexist_RFPage92D(
++ IN PADAPTER Adapter
++);
++
++VOID
++rtl8192d_PHY_InitRxSetting(
++ IN PADAPTER Adapter
++);
++
++VOID
++rtl8192d_PHY_ResetIQKResult(
++ IN PADAPTER Adapter
++);
++
++
++VOID
++rtl8192d_PHY_SetRFPathSwitch(IN PADAPTER pAdapter, IN BOOLEAN bMain);
++
++VOID
++HalChangeCCKStatus8192D(
++ IN PADAPTER Adapter,
++ IN BOOLEAN bCCKDisable
++);
++
++VOID
++PHY_InitPABias92D(IN PADAPTER Adapter);
++
++/*--------------------------Exported Function prototype---------------------*/
++
++#define PHY_SetBBReg1Byte(Adapter, RegAddr, BitMask, Data) rtl8192d_PHY_SetBBReg1Byte((Adapter), (RegAddr), (BitMask), (Data))
++#define PHY_QueryBBReg(Adapter, RegAddr, BitMask) rtl8192d_PHY_QueryBBReg((Adapter), (RegAddr), (BitMask))
++#define PHY_SetBBReg(Adapter, RegAddr, BitMask, Data) rtl8192d_PHY_SetBBReg((Adapter), (RegAddr), (BitMask), (Data))
++#define PHY_QueryRFReg(Adapter, eRFPath, RegAddr, BitMask) rtl8192d_PHY_QueryRFReg((Adapter), (eRFPath), (RegAddr), (BitMask))
++#define PHY_SetRFReg(Adapter, eRFPath, RegAddr, BitMask, Data) rtl8192d_PHY_SetRFReg((Adapter), (eRFPath), (RegAddr), (BitMask), (Data))
++
++#define PHY_SetMacReg PHY_SetBBReg
++
++#endif // __INC_HAL8192SPHYCFG_H
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/Hal8192DPhyReg.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/Hal8192DPhyReg.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/Hal8192DPhyReg.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/Hal8192DPhyReg.h 2015-07-28 01:20:58.317611539 +0200
+@@ -0,0 +1,1170 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++/*****************************************************************************
++ *
++ * Module: __INC_HAL8192DPHYREG_H
++ *
++ *
++ * Note: 1. Define PMAC/BB register map
++ * 2. Define RF register map
++ * 3. PMAC/BB register bit mask.
++ * 4. RF reg bit mask.
++ * 5. Other BB/RF relative definition.
++ *
++ *
++ * Export: Constants, macro, functions(API), global variables(None).
++ *
++ * Abbrev:
++ *
++ * History:
++ * Data Who Remark
++ * 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h.
++ * 2. Reorganize code architecture.
++ * 09/25/2008 MH 1. Add RL6052 register definition
++ *
++ *****************************************************************************/
++#ifndef __INC_HAL8192DPHYREG_H
++#define __INC_HAL8192DPHYREG_H
++
++
++/*--------------------------Define Parameters-------------------------------*/
++
++//============================================================
++// 8192S Regsiter offset definition
++//============================================================
++
++//
++// BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
++// 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
++// 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
++// 3. RF register 0x00-2E
++// 4. Bit Mask for BB/RF register
++// 5. Other defintion for BB/RF R/W
++//
++
++
++//
++// 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
++// 1. Page1(0x100)
++//
++#define rPMAC_Reset 0x100
++#define rPMAC_TxStart 0x104
++#define rPMAC_TxLegacySIG 0x108
++#define rPMAC_TxHTSIG1 0x10c
++#define rPMAC_TxHTSIG2 0x110
++#define rPMAC_PHYDebug 0x114
++#define rPMAC_TxPacketNum 0x118
++#define rPMAC_TxIdle 0x11c
++#define rPMAC_TxMACHeader0 0x120
++#define rPMAC_TxMACHeader1 0x124
++#define rPMAC_TxMACHeader2 0x128
++#define rPMAC_TxMACHeader3 0x12c
++#define rPMAC_TxMACHeader4 0x130
++#define rPMAC_TxMACHeader5 0x134
++#define rPMAC_TxDataType 0x138
++#define rPMAC_TxRandomSeed 0x13c
++#define rPMAC_CCKPLCPPreamble 0x140
++#define rPMAC_CCKPLCPHeader 0x144
++#define rPMAC_CCKCRC16 0x148
++#define rPMAC_OFDMRxCRC32OK 0x170
++#define rPMAC_OFDMRxCRC32Er 0x174
++#define rPMAC_OFDMRxParityEr 0x178
++#define rPMAC_OFDMRxCRC8Er 0x17c
++#define rPMAC_CCKCRxRC16Er 0x180
++#define rPMAC_CCKCRxRC32Er 0x184
++#define rPMAC_CCKCRxRC32OK 0x188
++#define rPMAC_TxStatus 0x18c
++
++//
++// 2. Page2(0x200)
++//
++// The following two definition are only used for USB interface.
++#define RF_BB_CMD_ADDR 0x02c0 // RF/BB read/write command address.
++#define RF_BB_CMD_DATA 0x02c4 // RF/BB read/write command data.
++
++//
++// 3. Page8(0x800)
++//
++#define rFPGA0_RFMOD 0x800 //RF mode & CCK TxSC // RF BW Setting??
++
++#define rFPGA0_TxInfo 0x804 // Status report??
++#define rFPGA0_PSDFunction 0x808
++
++#define rFPGA0_TxGainStage 0x80c // Set TX PWR init gain?
++
++#define rFPGA0_RFTiming1 0x810 // Useless now
++#define rFPGA0_RFTiming2 0x814
++
++#define rFPGA0_XA_HSSIParameter1 0x820 // RF 3 wire register
++#define rFPGA0_XA_HSSIParameter2 0x824
++#define rFPGA0_XB_HSSIParameter1 0x828
++#define rFPGA0_XB_HSSIParameter2 0x82c
++
++#define rFPGA0_XA_LSSIParameter 0x840
++#define rFPGA0_XB_LSSIParameter 0x844
++
++#define rFPGA0_RFWakeUpParameter 0x850 // Useless now
++#define rFPGA0_RFSleepUpParameter 0x854
++
++#define rFPGA0_XAB_SwitchControl 0x858 // RF Channel switch
++#define rFPGA0_XCD_SwitchControl 0x85c
++
++#define rFPGA0_XA_RFInterfaceOE 0x860 // RF Channel switch
++#define rFPGA0_XB_RFInterfaceOE 0x864
++
++#define rFPGA0_XAB_RFInterfaceSW 0x870 // RF Interface Software Control
++#define rFPGA0_XCD_RFInterfaceSW 0x874
++
++#define rFPGA0_XAB_RFParameter 0x878 // RF Parameter
++#define rFPGA0_XCD_RFParameter 0x87c
++
++#define rFPGA0_AnalogParameter1 0x880 // Crystal cap setting RF-R/W protection for parameter4??
++#define rFPGA0_AnalogParameter2 0x884
++#define rFPGA0_AnalogParameter3 0x888
++#define rFPGA0_AdDaClockEn 0x888 // enable ad/da clock1 for dual-phy
++#define rFPGA0_AnalogParameter4 0x88c
++
++#define rFPGA0_XA_LSSIReadBack 0x8a0 // Tranceiver LSSI Readback
++#define rFPGA0_XB_LSSIReadBack 0x8a4
++#define rFPGA0_XC_LSSIReadBack 0x8a8
++#define rFPGA0_XD_LSSIReadBack 0x8ac
++
++#define rFPGA0_PSDReport 0x8b4 // Useless now
++#define TransceiverA_HSPI_Readback 0x8b8 // Transceiver A HSPI Readback
++#define TransceiverB_HSPI_Readback 0x8bc // Transceiver B HSPI Readback
++#define rFPGA0_XAB_RFInterfaceRB 0x8e0 // Useless now // RF Interface Readback Value
++#define rFPGA0_XCD_RFInterfaceRB 0x8e4 // Useless now
++
++//
++// 4. Page9(0x900)
++//
++#define rFPGA1_RFMOD 0x900 //RF mode & OFDM TxSC // RF BW Setting??
++
++#define rFPGA1_TxBlock 0x904 // Useless now
++#define rFPGA1_DebugSelect 0x908 // Useless now
++#define rFPGA1_TxInfo 0x90c // Useless now // Status report??
++
++//
++// 5. PageA(0xA00)
++//
++// Set Control channel to upper or lower. These settings are required only for 40MHz
++#define rCCK0_System 0xa00
++
++#define rCCK0_AFESetting 0xa04 // Disable init gain now // Select RX path by RSSI
++#define rCCK0_CCA 0xa08 // Disable init gain now // Init gain
++
++#define rCCK0_RxAGC1 0xa0c //AGC default value, saturation level // Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series
++#define rCCK0_RxAGC2 0xa10 //AGC & DAGC
++
++#define rCCK0_RxHP 0xa14
++
++#define rCCK0_DSPParameter1 0xa18 //Timing recovery & Channel estimation threshold
++#define rCCK0_DSPParameter2 0xa1c //SQ threshold
++
++#define rCCK0_TxFilter1 0xa20
++#define rCCK0_TxFilter2 0xa24
++#define rCCK0_DebugPort 0xa28 //debug port and Tx filter3
++#define rCCK0_FalseAlarmReport 0xa2c //0xa2d useless now 0xa30-a4f channel report
++#define rCCK0_TRSSIReport 0xa50
++#define rCCK0_RxReport 0xa54 //0xa57
++#define rCCK0_FACounterLower 0xa5c //0xa5b
++#define rCCK0_FACounterUpper 0xa58 //0xa5c
++
++//
++// PageB(0xB00)
++//
++#define rPdp_AntA 0xb00
++#define rPdp_AntA_4 0xb04
++#define rPdp_AntA_8 0xb08
++#define rPdp_AntA_C 0xb0c
++#define rPdp_AntA_10 0xb10
++#define rPdp_AntA_14 0xb14
++#define rPdp_AntA_18 0xb18
++#define rPdp_AntA_1C 0xb1c
++#define rPdp_AntA_20 0xb20
++#define rPdp_AntA_24 0xb24
++
++#define rConfig_Pmpd_AntA 0xb28
++#define rConfig_ram64x16 0xb2c
++
++#define rBndA 0xb30
++#define rHssiPar 0xb34
++
++#define rConfig_AntA 0xb68
++#define rConfig_AntB 0xb6c
++
++#define rPdp_AntB 0xb70
++#define rPdp_AntB_4 0xb74
++#define rPdp_AntB_8 0xb78
++#define rPdp_AntB_C 0xb7c
++#define rPdp_AntB_10 0xb80
++#define rPdp_AntB_14 0xb84
++#define rPdp_AntB_18 0xb88
++#define rPdp_AntB_1C 0xb8c
++#define rPdp_AntB_20 0xb90
++#define rPdp_AntB_24 0xb94
++
++#define rConfig_Pmpd_AntB 0xb98
++
++#define rBndB 0xba0
++
++#define rAPK 0xbd8
++#define rPm_Rx0_AntA 0xbdc
++#define rPm_Rx1_AntA 0xbe0
++#define rPm_Rx2_AntA 0xbe4
++#define rPm_Rx3_AntA 0xbe8
++#define rPm_Rx0_AntB 0xbec
++#define rPm_Rx1_AntB 0xbf0
++#define rPm_Rx2_AntB 0xbf4
++#define rPm_Rx3_AntB 0xbf8
++
++//
++// 6. PageC(0xC00)
++//
++#define rOFDM0_LSTF 0xc00
++
++#define rOFDM0_TRxPathEnable 0xc04
++#define rOFDM0_TRMuxPar 0xc08
++#define rOFDM0_TRSWIsolation 0xc0c
++
++#define rOFDM0_XARxAFE 0xc10 //RxIQ DC offset, Rx digital filter, DC notch filter
++#define rOFDM0_XARxIQImbalance 0xc14 //RxIQ imblance matrix
++#define rOFDM0_XBRxAFE 0xc18
++#define rOFDM0_XBRxIQImbalance 0xc1c
++#define rOFDM0_XCRxAFE 0xc20
++#define rOFDM0_XCRxIQImbalance 0xc24
++#define rOFDM0_XDRxAFE 0xc28
++#define rOFDM0_XDRxIQImbalance 0xc2c
++
++#define rOFDM0_RxDetector1 0xc30 //PD,BW & SBD // DM tune init gain
++#define rOFDM0_RxDetector2 0xc34 //SBD & Fame Sync.
++#define rOFDM0_RxDetector3 0xc38 //Frame Sync.
++#define rOFDM0_RxDetector4 0xc3c //PD, SBD, Frame Sync & Short-GI
++
++#define rOFDM0_RxDSP 0xc40 //Rx Sync Path
++#define rOFDM0_CFOandDAGC 0xc44 //CFO & DAGC
++#define rOFDM0_CCADropThreshold 0xc48 //CCA Drop threshold
++#define rOFDM0_ECCAThreshold 0xc4c // energy CCA
++
++#define rOFDM0_XAAGCCore1 0xc50 // DIG
++#define rOFDM0_XAAGCCore2 0xc54
++#define rOFDM0_XBAGCCore1 0xc58
++#define rOFDM0_XBAGCCore2 0xc5c
++#define rOFDM0_XCAGCCore1 0xc60
++#define rOFDM0_XCAGCCore2 0xc64
++#define rOFDM0_XDAGCCore1 0xc68
++#define rOFDM0_XDAGCCore2 0xc6c
++
++#define rOFDM0_AGCParameter1 0xc70
++#define rOFDM0_AGCParameter2 0xc74
++#define rOFDM0_AGCRSSITable 0xc78
++#define rOFDM0_HTSTFAGC 0xc7c
++
++#define rOFDM0_XATxIQImbalance 0xc80 // TX PWR TRACK and DIG
++#define rOFDM0_XATxAFE 0xc84
++#define rOFDM0_XBTxIQImbalance 0xc88
++#define rOFDM0_XBTxAFE 0xc8c
++#define rOFDM0_XCTxIQImbalance 0xc90
++#define rOFDM0_XCTxAFE 0xc94
++#define rOFDM0_XDTxIQImbalance 0xc98
++#define rOFDM0_XDTxAFE 0xc9c
++
++#define rOFDM0_RxIQExtAnta 0xca0
++#define rOFDM0_TxCoeff1 0xca4
++#define rOFDM0_TxCoeff2 0xca8
++#define rOFDM0_TxCoeff3 0xcac
++#define rOFDM0_TxCoeff4 0xcb0
++#define rOFDM0_TxCoeff5 0xcb4
++#define rOFDM0_TxCoeff6 0xcb8
++#define rOFDM0_RxHPParameter 0xce0
++#define rOFDM0_TxPseudoNoiseWgt 0xce4
++#define rOFDM0_FrameSync 0xcf0
++#define rOFDM0_DFSReport 0xcf4
++
++//
++// 7. PageD(0xD00)
++//
++#define rOFDM1_LSTF 0xd00
++#define rOFDM1_TRxPathEnable 0xd04
++
++#define rOFDM1_CFO 0xd08 // No setting now
++#define rOFDM1_CSI1 0xd10
++#define rOFDM1_SBD 0xd14
++#define rOFDM1_CSI2 0xd18
++#define rOFDM1_CFOTracking 0xd2c
++#define rOFDM1_TRxMesaure1 0xd34
++#define rOFDM1_IntfDet 0xd3c
++#define rOFDM1_PseudoNoiseStateAB 0xd50
++#define rOFDM1_PseudoNoiseStateCD 0xd54
++#define rOFDM1_RxPseudoNoiseWgt 0xd58
++
++#define rOFDM_PHYCounter1 0xda0 //cca, parity fail
++#define rOFDM_PHYCounter2 0xda4 //rate illegal, crc8 fail
++#define rOFDM_PHYCounter3 0xda8 //MCS not support
++
++#define rOFDM_ShortCFOAB 0xdac // No setting now
++#define rOFDM_ShortCFOCD 0xdb0
++#define rOFDM_LongCFOAB 0xdb4
++#define rOFDM_LongCFOCD 0xdb8
++#define rOFDM_TailCFOAB 0xdbc
++#define rOFDM_TailCFOCD 0xdc0
++#define rOFDM_PWMeasure1 0xdc4
++#define rOFDM_PWMeasure2 0xdc8
++#define rOFDM_BWReport 0xdcc
++#define rOFDM_AGCReport 0xdd0
++#define rOFDM_RxSNR 0xdd4
++#define rOFDM_RxEVMCSI 0xdd8
++#define rOFDM_SIGReport 0xddc
++
++
++//
++// 8. PageE(0xE00)
++//
++#define rTxAGC_A_Rate18_06 0xe00
++#define rTxAGC_A_Rate54_24 0xe04
++#define rTxAGC_A_CCK1_Mcs32 0xe08
++#define rTxAGC_A_Mcs03_Mcs00 0xe10
++#define rTxAGC_A_Mcs07_Mcs04 0xe14
++#define rTxAGC_A_Mcs11_Mcs08 0xe18
++#define rTxAGC_A_Mcs15_Mcs12 0xe1c
++
++#define rTxAGC_B_Rate18_06 0x830
++#define rTxAGC_B_Rate54_24 0x834
++#define rTxAGC_B_CCK1_55_Mcs32 0x838
++#define rTxAGC_B_Mcs03_Mcs00 0x83c
++#define rTxAGC_B_Mcs07_Mcs04 0x848
++#define rTxAGC_B_Mcs11_Mcs08 0x84c
++#define rTxAGC_B_Mcs15_Mcs12 0x868
++#define rTxAGC_B_CCK11_A_CCK2_11 0x86c
++
++#define rFPGA0_IQK 0xe28
++#define rTx_IQK_Tone_A 0xe30
++#define rRx_IQK_Tone_A 0xe34
++#define rTx_IQK_PI_A 0xe38
++#define rRx_IQK_PI_A 0xe3c
++
++#define rTx_IQK 0xe40
++#define rRx_IQK 0xe44
++#define rIQK_AGC_Pts 0xe48
++#define rIQK_AGC_Rsp 0xe4c
++#define rTx_IQK_Tone_B 0xe50
++#define rRx_IQK_Tone_B 0xe54
++#define rTx_IQK_PI_B 0xe58
++#define rRx_IQK_PI_B 0xe5c
++#define rIQK_AGC_Cont 0xe60
++
++#define rBlue_Tooth 0xe6c
++#define rRx_Wait_CCA 0xe70
++#define rTx_CCK_RFON 0xe74
++#define rTx_CCK_BBON 0xe78
++#define rTx_OFDM_RFON 0xe7c
++#define rTx_OFDM_BBON 0xe80
++#define rTx_To_Rx 0xe84
++#define rTx_To_Tx 0xe88
++#define rRx_CCK 0xe8c
++
++#define rTx_Power_Before_IQK_A 0xe94
++#define rTx_Power_After_IQK_A 0xe9c
++
++#define rRx_Power_Before_IQK_A 0xea0
++#define rRx_Power_Before_IQK_A_2 0xea4
++#define rRx_Power_After_IQK_A 0xea8
++#define rRx_Power_After_IQK_A_2 0xeac
++
++#define rTx_Power_Before_IQK_B 0xeb4
++#define rTx_Power_After_IQK_B 0xebc
++
++#define rRx_Power_Before_IQK_B 0xec0
++#define rRx_Power_Before_IQK_B_2 0xec4
++#define rRx_Power_After_IQK_B 0xec8
++#define rRx_Power_After_IQK_B_2 0xecc
++
++#define rRx_OFDM 0xed0
++#define rRx_Wait_RIFS 0xed4
++#define rRx_TO_Rx 0xed8
++#define rStandby 0xedc
++#define rSleep 0xee0
++#define rPMPD_ANAEN 0xeec
++
++//
++// 7. RF Register 0x00-0x2E (RF 8256)
++// RF-0222D 0x00-3F
++//
++//Zebra1
++#define rZebra1_HSSIEnable 0x0 // Useless now
++#define rZebra1_TRxEnable1 0x1
++#define rZebra1_TRxEnable2 0x2
++#define rZebra1_AGC 0x4
++#define rZebra1_ChargePump 0x5
++#define rZebra1_Channel 0x7 // RF channel switch
++
++//#endif
++#define rZebra1_TxGain 0x8 // Useless now
++#define rZebra1_TxLPF 0x9
++#define rZebra1_RxLPF 0xb
++#define rZebra1_RxHPFCorner 0xc
++
++//Zebra4
++#define rGlobalCtrl 0 // Useless now
++#define rRTL8256_TxLPF 19
++#define rRTL8256_RxLPF 11
++
++//RTL8258
++#define rRTL8258_TxLPF 0x11 // Useless now
++#define rRTL8258_RxLPF 0x13
++#define rRTL8258_RSSILPF 0xa
++
++//
++// RL6052 Register definition
++//
++#define RF_AC 0x00 //
++
++#define RF_IQADJ_G1 0x01 //
++#define RF_IQADJ_G2 0x02 //
++#define RF_BS_PA_APSET_G1_G4 0x03
++#define RF_BS_PA_APSET_G5_G8 0x04
++#define RF_POW_TRSW 0x05 //
++
++#define RF_GAIN_RX 0x06 //
++#define RF_GAIN_TX 0x07 //
++
++#define RF_TXM_IDAC 0x08 //
++#define RF_IPA_G 0x09 //
++#define RF_TXBIAS_G 0x0A
++#define RF_TXPA_AG 0x0B
++#define RF_IPA_A 0x0C //
++#define RF_TXBIAS_A 0x0D
++#define RF_BS_PA_APSET_G9_G11 0x0E
++#define RF_BS_IQGEN 0x0F //
++
++#define RF_MODE1 0x10 //
++#define RF_MODE2 0x11 //
++
++#define RF_RX_AGC_HP 0x12 //
++#define RF_TX_AGC 0x13 //
++#define RF_BIAS 0x14 //
++#define RF_IPA 0x15 //
++#define RF_POW_ABILITY 0x17 //
++#define RF_MODE_AG 0x18 //
++#define rRfChannel 0x18 // RF channel and BW switch
++#define RF_CHNLBW 0x18 // RF channel and BW switch
++#define RF_TOP 0x19 //
++
++#define RF_RX_G1 0x1A //
++#define RF_RX_G2 0x1B //
++
++#define RF_RX_BB2 0x1C //
++#define RF_RX_BB1 0x1D //
++
++#define RF_RCK1 0x1E //
++#define RF_RCK2 0x1F //
++
++#define RF_TX_G1 0x20 //
++#define RF_TX_G2 0x21 //
++#define RF_TX_G3 0x22 //
++
++#define RF_TX_BB1 0x23 //
++
++#define RF_T_METER 0x42 //
++
++#define RF_SYN_G1 0x25 // RF TX Power control
++#define RF_SYN_G2 0x26 // RF TX Power control
++#define RF_SYN_G3 0x27 // RF TX Power control
++#define RF_SYN_G4 0x28 // RF TX Power control
++#define RF_SYN_G5 0x29 // RF TX Power control
++#define RF_SYN_G6 0x2A // RF TX Power control
++#define RF_SYN_G7 0x2B // RF TX Power control
++#define RF_SYN_G8 0x2C // RF TX Power control
++
++#define RF_RCK_OS 0x30 // RF TX PA control
++
++#define RF_TXPA_G1 0x31 // RF TX PA control
++#define RF_TXPA_G2 0x32 // RF TX PA control
++#define RF_TXPA_G3 0x33 // RF TX PA control
++#define RF_LOBF_9 0x38
++#define RF_RXRF_A3 0x3C //
++#define RF_TRSW 0x3F
++
++#define RF_TXRF_A2 0x41
++#define RF_TXPA_G4 0x46
++#define RF_TXPA_A4 0x4B
++
++//
++//Bit Mask
++//
++// 1. Page1(0x100)
++#define bBBResetB 0x100 // Useless now?
++#define bGlobalResetB 0x200
++#define bOFDMTxStart 0x4
++#define bCCKTxStart 0x8
++#define bCRC32Debug 0x100
++#define bPMACLoopback 0x10
++#define bTxLSIG 0xffffff
++#define bOFDMTxRate 0xf
++#define bOFDMTxReserved 0x10
++#define bOFDMTxLength 0x1ffe0
++#define bOFDMTxParity 0x20000
++#define bTxHTSIG1 0xffffff
++#define bTxHTMCSRate 0x7f
++#define bTxHTBW 0x80
++#define bTxHTLength 0xffff00
++#define bTxHTSIG2 0xffffff
++#define bTxHTSmoothing 0x1
++#define bTxHTSounding 0x2
++#define bTxHTReserved 0x4
++#define bTxHTAggreation 0x8
++#define bTxHTSTBC 0x30
++#define bTxHTAdvanceCoding 0x40
++#define bTxHTShortGI 0x80
++#define bTxHTNumberHT_LTF 0x300
++#define bTxHTCRC8 0x3fc00
++#define bCounterReset 0x10000
++#define bNumOfOFDMTx 0xffff
++#define bNumOfCCKTx 0xffff0000
++#define bTxIdleInterval 0xffff
++#define bOFDMService 0xffff0000
++#define bTxMACHeader 0xffffffff
++#define bTxDataInit 0xff
++#define bTxHTMode 0x100
++#define bTxDataType 0x30000
++#define bTxRandomSeed 0xffffffff
++#define bCCKTxPreamble 0x1
++#define bCCKTxSFD 0xffff0000
++#define bCCKTxSIG 0xff
++#define bCCKTxService 0xff00
++#define bCCKLengthExt 0x8000
++#define bCCKTxLength 0xffff0000
++#define bCCKTxCRC16 0xffff
++#define bCCKTxStatus 0x1
++#define bOFDMTxStatus 0x2
++
++#define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff))
++
++// 2. Page8(0x800)
++#define bRFMOD 0x1 // Reg 0x800 rFPGA0_RFMOD
++#define bJapanMode 0x2
++#define bCCKTxSC 0x30
++#define bCCKEn 0x1000000
++#define bOFDMEn 0x2000000
++
++#define bOFDMRxADCPhase 0x10000 // Useless now
++#define bOFDMTxDACPhase 0x40000
++#define bXATxAGC 0x3f
++
++#define bAntennaSelect 0x0300
++
++#define bXBTxAGC 0xf00 // Reg 80c rFPGA0_TxGainStage
++#define bXCTxAGC 0xf000
++#define bXDTxAGC 0xf0000
++
++#define bPAStart 0xf0000000 // Useless now
++#define bTRStart 0x00f00000
++#define bRFStart 0x0000f000
++#define bBBStart 0x000000f0
++#define bBBCCKStart 0x0000000f
++#define bPAEnd 0xf //Reg0x814
++#define bTREnd 0x0f000000
++#define bRFEnd 0x000f0000
++#define bCCAMask 0x000000f0 //T2R
++#define bR2RCCAMask 0x00000f00
++#define bHSSI_R2TDelay 0xf8000000
++#define bHSSI_T2RDelay 0xf80000
++#define bContTxHSSI 0x400 //chane gain at continue Tx
++#define bIGFromCCK 0x200
++#define bAGCAddress 0x3f
++#define bRxHPTx 0x7000
++#define bRxHPT2R 0x38000
++#define bRxHPCCKIni 0xc0000
++#define bAGCTxCode 0xc00000
++#define bAGCRxCode 0x300000
++
++#define b3WireDataLength 0x800 // Reg 0x820~84f rFPGA0_XA_HSSIParameter1
++#define b3WireAddressLength 0x400
++
++#define b3WireRFPowerDown 0x1 // Useless now
++//#define bHWSISelect 0x8
++#define b5GPAPEPolarity 0x40000000
++#define b2GPAPEPolarity 0x80000000
++#define bRFSW_TxDefaultAnt 0x3
++#define bRFSW_TxOptionAnt 0x30
++#define bRFSW_RxDefaultAnt 0x300
++#define bRFSW_RxOptionAnt 0x3000
++#define bRFSI_3WireData 0x1
++#define bRFSI_3WireClock 0x2
++#define bRFSI_3WireLoad 0x4
++#define bRFSI_3WireRW 0x8
++#define bRFSI_3Wire 0xf
++
++#define bRFSI_RFENV 0x10 // Reg 0x870 rFPGA0_XAB_RFInterfaceSW
++
++#define bRFSI_TRSW 0x20 // Useless now
++#define bRFSI_TRSWB 0x40
++#define bRFSI_ANTSW 0x100
++#define bRFSI_ANTSWB 0x200
++#define bRFSI_PAPE 0x400
++#define bRFSI_PAPE5G 0x800
++#define bBandSelect 0x1
++#define bHTSIG2_GI 0x80
++#define bHTSIG2_Smoothing 0x01
++#define bHTSIG2_Sounding 0x02
++#define bHTSIG2_Aggreaton 0x08
++#define bHTSIG2_STBC 0x30
++#define bHTSIG2_AdvCoding 0x40
++#define bHTSIG2_NumOfHTLTF 0x300
++#define bHTSIG2_CRC8 0x3fc
++#define bHTSIG1_MCS 0x7f
++#define bHTSIG1_BandWidth 0x80
++#define bHTSIG1_HTLength 0xffff
++#define bLSIG_Rate 0xf
++#define bLSIG_Reserved 0x10
++#define bLSIG_Length 0x1fffe
++#define bLSIG_Parity 0x20
++#define bCCKRxPhase 0x4
++
++#define bLSSIReadAddress 0x7f800000 // T65 RF
++
++#define bLSSIReadEdge 0x80000000 //LSSI "Read" edge signal
++
++#define bLSSIReadBackData 0xfffff // T65 RF
++
++#define bLSSIReadOKFlag 0x1000 // Useless now
++#define bCCKSampleRate 0x8 //0: 44MHz, 1:88MHz
++#define bRegulator0Standby 0x1
++#define bRegulatorPLLStandby 0x2
++#define bRegulator1Standby 0x4
++#define bPLLPowerUp 0x8
++#define bDPLLPowerUp 0x10
++#define bDA10PowerUp 0x20
++#define bAD7PowerUp 0x200
++#define bDA6PowerUp 0x2000
++#define bXtalPowerUp 0x4000
++#define b40MDClkPowerUP 0x8000
++#define bDA6DebugMode 0x20000
++#define bDA6Swing 0x380000
++
++#define bADClkPhase 0x4000000 // Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ
++
++#define b80MClkDelay 0x18000000 // Useless
++#define bAFEWatchDogEnable 0x20000000
++
++#define bXtalCap01 0xc0000000 // Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap
++#define bXtalCap23 0x3
++#define bXtalCap92x 0x0f000000
++#define bXtalCap 0x0f000000
++
++#define bIntDifClkEnable 0x400 // Useless
++#define bExtSigClkEnable 0x800
++#define bBandgapMbiasPowerUp 0x10000
++#define bAD11SHGain 0xc0000
++#define bAD11InputRange 0x700000
++#define bAD11OPCurrent 0x3800000
++#define bIPathLoopback 0x4000000
++#define bQPathLoopback 0x8000000
++#define bAFELoopback 0x10000000
++#define bDA10Swing 0x7e0
++#define bDA10Reverse 0x800
++#define bDAClkSource 0x1000
++#define bAD7InputRange 0x6000
++#define bAD7Gain 0x38000
++#define bAD7OutputCMMode 0x40000
++#define bAD7InputCMMode 0x380000
++#define bAD7Current 0xc00000
++#define bRegulatorAdjust 0x7000000
++#define bAD11PowerUpAtTx 0x1
++#define bDA10PSAtTx 0x10
++#define bAD11PowerUpAtRx 0x100
++#define bDA10PSAtRx 0x1000
++#define bCCKRxAGCFormat 0x200
++#define bPSDFFTSamplepPoint 0xc000
++#define bPSDAverageNum 0x3000
++#define bIQPathControl 0xc00
++#define bPSDFreq 0x3ff
++#define bPSDAntennaPath 0x30
++#define bPSDIQSwitch 0x40
++#define bPSDRxTrigger 0x400000
++#define bPSDTxTrigger 0x80000000
++#define bPSDSineToneScale 0x7f000000
++#define bPSDReport 0xffff
++
++// 3. Page9(0x900)
++#define bOFDMTxSC 0x30000000 // Useless
++#define bCCKTxOn 0x1
++#define bOFDMTxOn 0x2
++#define bDebugPage 0xfff //reset debug page and also HWord, LWord
++#define bDebugItem 0xff //reset debug page and LWord
++#define bAntL 0x10
++#define bAntNonHT 0x100
++#define bAntHT1 0x1000
++#define bAntHT2 0x10000
++#define bAntHT1S1 0x100000
++#define bAntNonHTS1 0x1000000
++
++// 4. PageA(0xA00)
++#define bCCKBBMode 0x3 // Useless
++#define bCCKTxPowerSaving 0x80
++#define bCCKRxPowerSaving 0x40
++
++#define bCCKSideBand 0x10 // Reg 0xa00 rCCK0_System 20/40 switch
++
++#define bCCKScramble 0x8 // Useless
++#define bCCKAntDiversity 0x8000
++#define bCCKCarrierRecovery 0x4000
++#define bCCKTxRate 0x3000
++#define bCCKDCCancel 0x0800
++#define bCCKISICancel 0x0400
++#define bCCKMatchFilter 0x0200
++#define bCCKEqualizer 0x0100
++#define bCCKPreambleDetect 0x800000
++#define bCCKFastFalseCCA 0x400000
++#define bCCKChEstStart 0x300000
++#define bCCKCCACount 0x080000
++#define bCCKcs_lim 0x070000
++#define bCCKBistMode 0x80000000
++#define bCCKCCAMask 0x40000000
++#define bCCKTxDACPhase 0x4
++#define bCCKRxADCPhase 0x20000000 //r_rx_clk
++#define bCCKr_cp_mode0 0x0100
++#define bCCKTxDCOffset 0xf0
++#define bCCKRxDCOffset 0xf
++#define bCCKCCAMode 0xc000
++#define bCCKFalseCS_lim 0x3f00
++#define bCCKCS_ratio 0xc00000
++#define bCCKCorgBit_sel 0x300000
++#define bCCKPD_lim 0x0f0000
++#define bCCKNewCCA 0x80000000
++#define bCCKRxHPofIG 0x8000
++#define bCCKRxIG 0x7f00
++#define bCCKLNAPolarity 0x800000
++#define bCCKRx1stGain 0x7f0000
++#define bCCKRFExtend 0x20000000 //CCK Rx Iinital gain polarity
++#define bCCKRxAGCSatLevel 0x1f000000
++#define bCCKRxAGCSatCount 0xe0
++#define bCCKRxRFSettle 0x1f //AGCsamp_dly
++#define bCCKFixedRxAGC 0x8000
++//#define bCCKRxAGCFormat 0x4000 //remove to HSSI register 0x824
++#define bCCKAntennaPolarity 0x2000
++#define bCCKTxFilterType 0x0c00
++#define bCCKRxAGCReportType 0x0300
++#define bCCKRxDAGCEn 0x80000000
++#define bCCKRxDAGCPeriod 0x20000000
++#define bCCKRxDAGCSatLevel 0x1f000000
++#define bCCKTimingRecovery 0x800000
++#define bCCKTxC0 0x3f0000
++#define bCCKTxC1 0x3f000000
++#define bCCKTxC2 0x3f
++#define bCCKTxC3 0x3f00
++#define bCCKTxC4 0x3f0000
++#define bCCKTxC5 0x3f000000
++#define bCCKTxC6 0x3f
++#define bCCKTxC7 0x3f00
++#define bCCKDebugPort 0xff0000
++#define bCCKDACDebug 0x0f000000
++#define bCCKFalseAlarmEnable 0x8000
++#define bCCKFalseAlarmRead 0x4000
++#define bCCKTRSSI 0x7f
++#define bCCKRxAGCReport 0xfe
++#define bCCKRxReport_AntSel 0x80000000
++#define bCCKRxReport_MFOff 0x40000000
++#define bCCKRxRxReport_SQLoss 0x20000000
++#define bCCKRxReport_Pktloss 0x10000000
++#define bCCKRxReport_Lockedbit 0x08000000
++#define bCCKRxReport_RateError 0x04000000
++#define bCCKRxReport_RxRate 0x03000000
++#define bCCKRxFACounterLower 0xff
++#define bCCKRxFACounterUpper 0xff000000
++#define bCCKRxHPAGCStart 0xe000
++#define bCCKRxHPAGCFinal 0x1c00
++#define bCCKRxFalseAlarmEnable 0x8000
++#define bCCKFACounterFreeze 0x4000
++#define bCCKTxPathSel 0x10000000
++#define bCCKDefaultRxPath 0xc000000
++#define bCCKOptionRxPath 0x3000000
++
++// 5. PageC(0xC00)
++#define bNumOfSTF 0x3 // Useless
++#define bShift_L 0xc0
++#define bGI_TH 0xc
++#define bRxPathA 0x1
++#define bRxPathB 0x2
++#define bRxPathC 0x4
++#define bRxPathD 0x8
++#define bTxPathA 0x1
++#define bTxPathB 0x2
++#define bTxPathC 0x4
++#define bTxPathD 0x8
++#define bTRSSIFreq 0x200
++#define bADCBackoff 0x3000
++#define bDFIRBackoff 0xc000
++#define bTRSSILatchPhase 0x10000
++#define bRxIDCOffset 0xff
++#define bRxQDCOffset 0xff00
++#define bRxDFIRMode 0x1800000
++#define bRxDCNFType 0xe000000
++#define bRXIQImb_A 0x3ff
++#define bRXIQImb_B 0xfc00
++#define bRXIQImb_C 0x3f0000
++#define bRXIQImb_D 0xffc00000
++#define bDC_dc_Notch 0x60000
++#define bRxNBINotch 0x1f000000
++#define bPD_TH 0xf
++#define bPD_TH_Opt2 0xc000
++#define bPWED_TH 0x700
++#define bIfMF_Win_L 0x800
++#define bPD_Option 0x1000
++#define bMF_Win_L 0xe000
++#define bBW_Search_L 0x30000
++#define bwin_enh_L 0xc0000
++#define bBW_TH 0x700000
++#define bED_TH2 0x3800000
++#define bBW_option 0x4000000
++#define bRatio_TH 0x18000000
++#define bWindow_L 0xe0000000
++#define bSBD_Option 0x1
++#define bFrame_TH 0x1c
++#define bFS_Option 0x60
++#define bDC_Slope_check 0x80
++#define bFGuard_Counter_DC_L 0xe00
++#define bFrame_Weight_Short 0x7000
++#define bSub_Tune 0xe00000
++#define bFrame_DC_Length 0xe000000
++#define bSBD_start_offset 0x30000000
++#define bFrame_TH_2 0x7
++#define bFrame_GI2_TH 0x38
++#define bGI2_Sync_en 0x40
++#define bSarch_Short_Early 0x300
++#define bSarch_Short_Late 0xc00
++#define bSarch_GI2_Late 0x70000
++#define bCFOAntSum 0x1
++#define bCFOAcc 0x2
++#define bCFOStartOffset 0xc
++#define bCFOLookBack 0x70
++#define bCFOSumWeight 0x80
++#define bDAGCEnable 0x10000
++#define bTXIQImb_A 0x3ff
++#define bTXIQImb_B 0xfc00
++#define bTXIQImb_C 0x3f0000
++#define bTXIQImb_D 0xffc00000
++#define bTxIDCOffset 0xff
++#define bTxQDCOffset 0xff00
++#define bTxDFIRMode 0x10000
++#define bTxPesudoNoiseOn 0x4000000
++#define bTxPesudoNoise_A 0xff
++#define bTxPesudoNoise_B 0xff00
++#define bTxPesudoNoise_C 0xff0000
++#define bTxPesudoNoise_D 0xff000000
++#define bCCADropOption 0x20000
++#define bCCADropThres 0xfff00000
++#define bEDCCA_H 0xf
++#define bEDCCA_L 0xf0
++#define bLambda_ED 0x300
++#define bRxInitialGain 0x7f
++#define bRxAntDivEn 0x80
++#define bRxAGCAddressForLNA 0x7f00
++#define bRxHighPowerFlow 0x8000
++#define bRxAGCFreezeThres 0xc0000
++#define bRxFreezeStep_AGC1 0x300000
++#define bRxFreezeStep_AGC2 0xc00000
++#define bRxFreezeStep_AGC3 0x3000000
++#define bRxFreezeStep_AGC0 0xc000000
++#define bRxRssi_Cmp_En 0x10000000
++#define bRxQuickAGCEn 0x20000000
++#define bRxAGCFreezeThresMode 0x40000000
++#define bRxOverFlowCheckType 0x80000000
++#define bRxAGCShift 0x7f
++#define bTRSW_Tri_Only 0x80
++#define bPowerThres 0x300
++#define bRxAGCEn 0x1
++#define bRxAGCTogetherEn 0x2
++#define bRxAGCMin 0x4
++#define bRxHP_Ini 0x7
++#define bRxHP_TRLNA 0x70
++#define bRxHP_RSSI 0x700
++#define bRxHP_BBP1 0x7000
++#define bRxHP_BBP2 0x70000
++#define bRxHP_BBP3 0x700000
++#define bRSSI_H 0x7f0000 //the threshold for high power
++#define bRSSI_Gen 0x7f000000 //the threshold for ant diversity
++#define bRxSettle_TRSW 0x7
++#define bRxSettle_LNA 0x38
++#define bRxSettle_RSSI 0x1c0
++#define bRxSettle_BBP 0xe00
++#define bRxSettle_RxHP 0x7000
++#define bRxSettle_AntSW_RSSI 0x38000
++#define bRxSettle_AntSW 0xc0000
++#define bRxProcessTime_DAGC 0x300000
++#define bRxSettle_HSSI 0x400000
++#define bRxProcessTime_BBPPW 0x800000
++#define bRxAntennaPowerShift 0x3000000
++#define bRSSITableSelect 0xc000000
++#define bRxHP_Final 0x7000000
++#define bRxHTSettle_BBP 0x7
++#define bRxHTSettle_HSSI 0x8
++#define bRxHTSettle_RxHP 0x70
++#define bRxHTSettle_BBPPW 0x80
++#define bRxHTSettle_Idle 0x300
++#define bRxHTSettle_Reserved 0x1c00
++#define bRxHTRxHPEn 0x8000
++#define bRxHTAGCFreezeThres 0x30000
++#define bRxHTAGCTogetherEn 0x40000
++#define bRxHTAGCMin 0x80000
++#define bRxHTAGCEn 0x100000
++#define bRxHTDAGCEn 0x200000
++#define bRxHTRxHP_BBP 0x1c00000
++#define bRxHTRxHP_Final 0xe0000000
++#define bRxPWRatioTH 0x3
++#define bRxPWRatioEn 0x4
++#define bRxMFHold 0x3800
++#define bRxPD_Delay_TH1 0x38
++#define bRxPD_Delay_TH2 0x1c0
++#define bRxPD_DC_COUNT_MAX 0x600
++//#define bRxMF_Hold 0x3800
++#define bRxPD_Delay_TH 0x8000
++#define bRxProcess_Delay 0xf0000
++#define bRxSearchrange_GI2_Early 0x700000
++#define bRxFrame_Guard_Counter_L 0x3800000
++#define bRxSGI_Guard_L 0xc000000
++#define bRxSGI_Search_L 0x30000000
++#define bRxSGI_TH 0xc0000000
++#define bDFSCnt0 0xff
++#define bDFSCnt1 0xff00
++#define bDFSFlag 0xf0000
++#define bMFWeightSum 0x300000
++#define bMinIdxTH 0x7f000000
++#define bDAFormat 0x40000
++#define bTxChEmuEnable 0x01000000
++#define bTRSWIsolation_A 0x7f
++#define bTRSWIsolation_B 0x7f00
++#define bTRSWIsolation_C 0x7f0000
++#define bTRSWIsolation_D 0x7f000000
++#define bExtLNAGain 0x7c00
++
++// 6. PageE(0xE00)
++#define bSTBCEn 0x4 // Useless
++#define bAntennaMapping 0x10
++#define bNss 0x20
++#define bCFOAntSumD 0x200
++#define bPHYCounterReset 0x8000000
++#define bCFOReportGet 0x4000000
++#define bOFDMContinueTx 0x10000000
++#define bOFDMSingleCarrier 0x20000000
++#define bOFDMSingleTone 0x40000000
++//#define bRxPath1 0x01
++//#define bRxPath2 0x02
++//#define bRxPath3 0x04
++//#define bRxPath4 0x08
++//#define bTxPath1 0x10
++//#define bTxPath2 0x20
++#define bHTDetect 0x100
++#define bCFOEn 0x10000
++#define bCFOValue 0xfff00000
++#define bSigTone_Re 0x3f
++#define bSigTone_Im 0x7f00
++#define bCounter_CCA 0xffff
++#define bCounter_ParityFail 0xffff0000
++#define bCounter_RateIllegal 0xffff
++#define bCounter_CRC8Fail 0xffff0000
++#define bCounter_MCSNoSupport 0xffff
++#define bCounter_FastSync 0xffff
++#define bShortCFO 0xfff
++#define bShortCFOTLength 12 //total
++#define bShortCFOFLength 11 //fraction
++#define bLongCFO 0x7ff
++#define bLongCFOTLength 11
++#define bLongCFOFLength 11
++#define bTailCFO 0x1fff
++#define bTailCFOTLength 13
++#define bTailCFOFLength 12
++#define bmax_en_pwdB 0xffff
++#define bCC_power_dB 0xffff0000
++#define bnoise_pwdB 0xffff
++#define bPowerMeasTLength 10
++#define bPowerMeasFLength 3
++#define bRx_HT_BW 0x1
++#define bRxSC 0x6
++#define bRx_HT 0x8
++#define bNB_intf_det_on 0x1
++#define bIntf_win_len_cfg 0x30
++#define bNB_Intf_TH_cfg 0x1c0
++#define bRFGain 0x3f
++#define bTableSel 0x40
++#define bTRSW 0x80
++#define bRxSNR_A 0xff
++#define bRxSNR_B 0xff00
++#define bRxSNR_C 0xff0000
++#define bRxSNR_D 0xff000000
++#define bSNREVMTLength 8
++#define bSNREVMFLength 1
++#define bCSI1st 0xff
++#define bCSI2nd 0xff00
++#define bRxEVM1st 0xff0000
++#define bRxEVM2nd 0xff000000
++#define bSIGEVM 0xff
++#define bPWDB 0xff00
++#define bSGIEN 0x10000
++
++#define bSFactorQAM1 0xf // Useless
++#define bSFactorQAM2 0xf0
++#define bSFactorQAM3 0xf00
++#define bSFactorQAM4 0xf000
++#define bSFactorQAM5 0xf0000
++#define bSFactorQAM6 0xf0000
++#define bSFactorQAM7 0xf00000
++#define bSFactorQAM8 0xf000000
++#define bSFactorQAM9 0xf0000000
++#define bCSIScheme 0x100000
++
++#define bNoiseLvlTopSet 0x3 // Useless
++#define bChSmooth 0x4
++#define bChSmoothCfg1 0x38
++#define bChSmoothCfg2 0x1c0
++#define bChSmoothCfg3 0xe00
++#define bChSmoothCfg4 0x7000
++#define bMRCMode 0x800000
++#define bTHEVMCfg 0x7000000
++
++#define bLoopFitType 0x1 // Useless
++#define bUpdCFO 0x40
++#define bUpdCFOOffData 0x80
++#define bAdvUpdCFO 0x100
++#define bAdvTimeCtrl 0x800
++#define bUpdClko 0x1000
++#define bFC 0x6000
++#define bTrackingMode 0x8000
++#define bPhCmpEnable 0x10000
++#define bUpdClkoLTF 0x20000
++#define bComChCFO 0x40000
++#define bCSIEstiMode 0x80000
++#define bAdvUpdEqz 0x100000
++#define bUChCfg 0x7000000
++#define bUpdEqz 0x8000000
++
++//Rx Pseduo noise
++#define bRxPesudoNoiseOn 0x20000000 // Useless
++#define bRxPesudoNoise_A 0xff
++#define bRxPesudoNoise_B 0xff00
++#define bRxPesudoNoise_C 0xff0000
++#define bRxPesudoNoise_D 0xff000000
++#define bPesudoNoiseState_A 0xffff
++#define bPesudoNoiseState_B 0xffff0000
++#define bPesudoNoiseState_C 0xffff
++#define bPesudoNoiseState_D 0xffff0000
++
++//7. RF Register
++//Zebra1
++#define bZebra1_HSSIEnable 0x8 // Useless
++#define bZebra1_TRxControl 0xc00
++#define bZebra1_TRxGainSetting 0x07f
++#define bZebra1_RxCorner 0xc00
++#define bZebra1_TxChargePump 0x38
++#define bZebra1_RxChargePump 0x7
++#define bZebra1_ChannelNum 0xf80
++#define bZebra1_TxLPFBW 0x400
++#define bZebra1_RxLPFBW 0x600
++
++//Zebra4
++#define bRTL8256RegModeCtrl1 0x100 // Useless
++#define bRTL8256RegModeCtrl0 0x40
++#define bRTL8256_TxLPFBW 0x18
++#define bRTL8256_RxLPFBW 0x600
++
++//RTL8258
++#define bRTL8258_TxLPFBW 0xc // Useless
++#define bRTL8258_RxLPFBW 0xc00
++#define bRTL8258_RSSILPFBW 0xc0
++
++
++//
++// Other Definition
++//
++
++//byte endable for sb_write
++#define bByte0 0x1 // Useless
++#define bByte1 0x2
++#define bByte2 0x4
++#define bByte3 0x8
++#define bWord0 0x3
++#define bWord1 0xc
++#define bDWord 0xf
++
++//for PutRegsetting & GetRegSetting BitMask
++#define bMaskByte0 0xff // Reg 0xc50 rOFDM0_XAAGCCore~0xC6f
++#define bMaskByte1 0xff00
++#define bMaskByte2 0xff0000
++#define bMaskByte3 0xff000000
++#define bMaskHWord 0xffff0000
++#define bMaskLWord 0x0000ffff
++#define bMaskDWord 0xffffffff
++#define bMask12Bits 0xfff
++#define bMaskH4Bits 0xf0000000
++#define bMaskOFDM_D 0xffc00000
++#define bMaskCCK 0x3f3f3f3f
++
++//for PutRFRegsetting & GetRFRegSetting BitMask
++//#define bMask12Bits 0xfffff // RF Reg mask bits
++//#define bMask20Bits 0xfffff // RF Reg mask bits T65 RF
++#define bRFRegOffsetMask 0xfffff
++//#define bRFRegOffsetMask 0xfff
++
++//MAC0 will wirte PHY1
++#define MAC0_ACCESS_PHY1 0x4000
++//MAC1 will wirte PHY0
++#define MAC1_ACCESS_PHY0 0x2000
++
++#define bEnable 0x1 // Useless
++#define bDisable 0x0
++
++#define LeftAntenna 0x0 // Useless
++#define RightAntenna 0x1
++
++#define tCheckTxStatus 500 //500ms // Useless
++#define tUpdateRxCounter 100 //100ms
++
++#define rateCCK 0 // Useless
++#define rateOFDM 1
++#define rateHT 2
++
++//define Register-End
++#define bPMAC_End 0x1ff // Useless
++#define bFPGAPHY0_End 0x8ff
++#define bFPGAPHY1_End 0x9ff
++#define bCCKPHY0_End 0xaff
++#define bOFDMPHY0_End 0xcff
++#define bOFDMPHY1_End 0xdff
++
++//define max debug item in each debug page
++//#define bMaxItem_FPGA_PHY0 0x9
++//#define bMaxItem_FPGA_PHY1 0x3
++//#define bMaxItem_PHY_11B 0x16
++//#define bMaxItem_OFDM_PHY0 0x29
++//#define bMaxItem_OFDM_PHY1 0x0
++
++#define bPMACControl 0x0 // Useless
++#define bWMACControl 0x1
++#define bWNICControl 0x2
++
++#define PathA 0x0 // Useless
++#define PathB 0x1
++#define PathC 0x2
++#define PathD 0x3
++
++/*--------------------------Define Parameters-------------------------------*/
++
++
++#endif //__INC_HAL8192SPHYREG_H
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/Hal8192DUHWImg.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/Hal8192DUHWImg.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/Hal8192DUHWImg.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/Hal8192DUHWImg.h 2015-07-28 01:20:58.317611539 +0200
+@@ -0,0 +1,66 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef __INC_HAL8192DU_FW_IMG_H
++#define __INC_HAL8192DU_FW_IMG_H
++
++#include <basic_types.h>
++
++/*Created on 2011/11/11, 8: 8*/
++
++#define Rtl8192DUImgArrayLength 31452
++extern const u8 Rtl8192DUFwImgArray[Rtl8192DUImgArrayLength];
++#define Rtl8192DUMainArrayLength 1
++extern const u8 Rtl8192DUFwMainArray[Rtl8192DUMainArrayLength];
++#define Rtl8192DUDataArrayLength 1
++extern const u8 Rtl8192DUFwDataArray[Rtl8192DUDataArrayLength];
++#define Rtl8192DUPHY_REG_2TArrayLength 372
++extern const u32 Rtl8192DUPHY_REG_2TArray[Rtl8192DUPHY_REG_2TArrayLength];
++#define Rtl8192DUPHY_REG_1TArrayLength 1
++extern const u32 Rtl8192DUPHY_REG_1TArray[Rtl8192DUPHY_REG_1TArrayLength];
++#define Rtl8192DUPHY_REG_Array_PGLength 624
++extern const u32 Rtl8192DUPHY_REG_Array_PG[Rtl8192DUPHY_REG_Array_PGLength];
++#define Rtl8192DUPHY_REG_Array_MPLength 14
++extern const u32 Rtl8192DUPHY_REG_Array_MP[Rtl8192DUPHY_REG_Array_MPLength];
++#define Rtl8192DURadioA_2TArrayLength 378
++extern const u32 Rtl8192DURadioA_2TArray[Rtl8192DURadioA_2TArrayLength];
++#define Rtl8192DURadioB_2TArrayLength 384
++extern const u32 Rtl8192DURadioB_2TArray[Rtl8192DURadioB_2TArrayLength];
++#define Rtl8192DURadioA_1TArrayLength 1
++extern const u32 Rtl8192DURadioA_1TArray[Rtl8192DURadioA_1TArrayLength];
++#define Rtl8192DURadioB_1TArrayLength 1
++extern const u32 Rtl8192DURadioB_1TArray[Rtl8192DURadioB_1TArrayLength];
++#define Rtl8192DURadioA_2T_intPAArrayLength 378
++extern const u32 Rtl8192DURadioA_2T_intPAArray[Rtl8192DURadioA_2T_intPAArrayLength];
++#define Rtl8192DURadioB_2T_intPAArrayLength 384
++extern const u32 Rtl8192DURadioB_2T_intPAArray[Rtl8192DURadioB_2T_intPAArrayLength];
++#define Rtl8192DUMAC_2T_ArrayLength 192
++extern const u32 Rtl8192DUMAC_2T_Array[Rtl8192DUMAC_2T_ArrayLength];
++#define Rtl8192DUAGCTAB_ArrayLength 386
++extern const u32 Rtl8192DUAGCTAB_Array[Rtl8192DUAGCTAB_ArrayLength];
++#define Rtl8192DUAGCTAB_5GArrayLength 194
++extern const u32 Rtl8192DUAGCTAB_5GArray[Rtl8192DUAGCTAB_5GArrayLength];
++#define Rtl8192DUAGCTAB_2GArrayLength 194
++extern const u32 Rtl8192DUAGCTAB_2GArray[Rtl8192DUAGCTAB_2GArrayLength];
++#define Rtl8192DUAGCTAB_2TArrayLength 1
++extern const u32 Rtl8192DUAGCTAB_2TArray[Rtl8192DUAGCTAB_2TArrayLength];
++#define Rtl8192DUAGCTAB_1TArrayLength 1
++extern const u32 Rtl8192DUAGCTAB_1TArray[Rtl8192DUAGCTAB_1TArrayLength];
++
++#endif //__INC_HAL8192CU_FW_IMG_H
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/Hal8192DUHWImg_wowlan.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/Hal8192DUHWImg_wowlan.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/Hal8192DUHWImg_wowlan.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/Hal8192DUHWImg_wowlan.h 2015-07-28 01:20:58.317611539 +0200
+@@ -0,0 +1,29 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef __INC_HAL8192DU_FW_IMG_WOWLAN_H
++#define __INC_HAL8192DU_FW_IMG_WOWLAN_H
++
++/*Created on 2011/11/ 8, 14:15*/
++
++
++#define DUWWImgArrayLength 24818
++extern u8 Rtl8192DUFwWWImgArray[DUWWImgArrayLength];
++
++#endif //__INC_HAL8192DU_FW_IMG_WOWLAN_H
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/hal_com.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/hal_com.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/hal_com.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/hal_com.h 2015-07-28 01:20:58.317611539 +0200
+@@ -0,0 +1,145 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef __HAL_COMMON_H__
++#define __HAL_COMMON_H__
++
++//CCK
++#define RATE_1M BIT(0)
++#define RATE_2M BIT(1)
++#define RATE_5_5M BIT(2)
++#define RATE_11M BIT(3)
++//OFDM
++#define RATE_6M BIT(4)
++#define RATE_9M BIT(5)
++#define RATE_12M BIT(6)
++#define RATE_18M BIT(7)
++#define RATE_24M BIT(8)
++#define RATE_36M BIT(9)
++#define RATE_48M BIT(10)
++#define RATE_54M BIT(11)
++//MCS 1 Spatial Stream
++#define RATE_MCS0 BIT(12)
++#define RATE_MCS1 BIT(13)
++#define RATE_MCS2 BIT(14)
++#define RATE_MCS3 BIT(15)
++#define RATE_MCS4 BIT(16)
++#define RATE_MCS5 BIT(17)
++#define RATE_MCS6 BIT(18)
++#define RATE_MCS7 BIT(19)
++//MCS 2 Spatial Stream
++#define RATE_MCS8 BIT(20)
++#define RATE_MCS9 BIT(21)
++#define RATE_MCS10 BIT(22)
++#define RATE_MCS11 BIT(23)
++#define RATE_MCS12 BIT(24)
++#define RATE_MCS13 BIT(25)
++#define RATE_MCS14 BIT(26)
++#define RATE_MCS15 BIT(27)
++
++// ALL CCK Rate
++#define RATE_ALL_CCK RATR_1M|RATR_2M|RATR_55M|RATR_11M
++#define RATE_ALL_OFDM_AG RATR_6M|RATR_9M|RATR_12M|RATR_18M|RATR_24M|\
++ RATR_36M|RATR_48M|RATR_54M
++#define RATE_ALL_OFDM_1SS RATR_MCS0|RATR_MCS1|RATR_MCS2|RATR_MCS3 |\
++ RATR_MCS4|RATR_MCS5|RATR_MCS6 |RATR_MCS7
++#define RATE_ALL_OFDM_2SS RATR_MCS8|RATR_MCS9 |RATR_MCS10|RATR_MCS11|\
++ RATR_MCS12|RATR_MCS13|RATR_MCS14|RATR_MCS15
++
++/*------------------------------ Tx Desc definition Macro ------------------------*/
++//#pragma mark -- Tx Desc related definition. --
++//----------------------------------------------------------------------------
++//-----------------------------------------------------------
++// Rate
++//-----------------------------------------------------------
++// CCK Rates, TxHT = 0
++#define DESC_RATE1M 0x00
++#define DESC_RATE2M 0x01
++#define DESC_RATE5_5M 0x02
++#define DESC_RATE11M 0x03
++
++// OFDM Rates, TxHT = 0
++#define DESC_RATE6M 0x04
++#define DESC_RATE9M 0x05
++#define DESC_RATE12M 0x06
++#define DESC_RATE18M 0x07
++#define DESC_RATE24M 0x08
++#define DESC_RATE36M 0x09
++#define DESC_RATE48M 0x0a
++#define DESC_RATE54M 0x0b
++
++// MCS Rates, TxHT = 1
++#define DESC_RATEMCS0 0x0c
++#define DESC_RATEMCS1 0x0d
++#define DESC_RATEMCS2 0x0e
++#define DESC_RATEMCS3 0x0f
++#define DESC_RATEMCS4 0x10
++#define DESC_RATEMCS5 0x11
++#define DESC_RATEMCS6 0x12
++#define DESC_RATEMCS7 0x13
++#define DESC_RATEMCS8 0x14
++#define DESC_RATEMCS9 0x15
++#define DESC_RATEMCS10 0x16
++#define DESC_RATEMCS11 0x17
++#define DESC_RATEMCS12 0x18
++#define DESC_RATEMCS13 0x19
++#define DESC_RATEMCS14 0x1a
++#define DESC_RATEMCS15 0x1b
++#define DESC_RATEMCS15_SG 0x1c
++#define DESC_RATEMCS32 0x20
++
++//============================================================
++// Global var
++//============================================================
++#define OFDM_TABLE_SIZE_92C 37
++#define OFDM_TABLE_SIZE_92D 43
++#define CCK_TABLE_SIZE 33
++
++extern u32 OFDMSwingTable[OFDM_TABLE_SIZE_92D] ;
++
++extern u8 CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8];
++
++extern u8 CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8];
++
++#ifdef CONFIG_CHIP_VER_INTEGRATION
++void dump_chip_info(HAL_VERSION ChipVersion);
++#endif
++
++u8 //return the final channel plan decision
++hal_com_get_channel_plan(
++ IN PADAPTER padapter,
++ IN u8 hw_channel_plan, //channel plan from HW (efuse/eeprom)
++ IN u8 sw_channel_plan, //channel plan from SW (registry/module param)
++ IN u8 def_channel_plan, //channel plan used when the former two is invalid
++ IN BOOLEAN AutoLoadFail
++ );
++
++void HalSetBrateCfg(
++ IN PADAPTER Adapter,
++ IN u8 *mBratesOS,
++ OUT u16 *pBrateCfg);
++
++u8 MRateToHwRate(u8 rate);
++
++void hal_init_macaddr(_adapter *adapter);
++
++void c2h_evt_clear(_adapter *adapter);
++s32 c2h_evt_read(_adapter *adapter, u8 *buf);
++
++#endif //__HAL_COMMON_H__
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/hal_intf.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/hal_intf.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/hal_intf.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/hal_intf.h 2015-07-28 01:20:58.317611539 +0200
+@@ -0,0 +1,431 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef __HAL_INTF_H__
++#define __HAL_INTF_H__
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++
++#ifdef CONFIG_PCI_HCI
++#include <pci_hal.h>
++#endif
++
++
++enum RTL871X_HCI_TYPE {
++
++ RTW_SDIO,
++ RTW_USB,
++ RTW_PCIE
++};
++
++enum _CHIP_TYPE {
++
++ NULL_CHIP_TYPE,
++ RTL8712_8188S_8191S_8192S,
++ RTL8188C_8192C,
++ RTL8192D,
++ RTL8723A,
++ RTL8188E,
++ MAX_CHIP_TYPE
++};
++
++
++typedef enum _HW_VARIABLES{
++ HW_VAR_MEDIA_STATUS,
++ HW_VAR_MEDIA_STATUS1,
++ HW_VAR_SET_OPMODE,
++ HW_VAR_MAC_ADDR,
++ HW_VAR_BSSID,
++ HW_VAR_INIT_RTS_RATE,
++ HW_VAR_INIT_DATA_RATE,
++ HW_VAR_BASIC_RATE,
++ HW_VAR_TXPAUSE,
++ HW_VAR_BCN_FUNC,
++ HW_VAR_CORRECT_TSF,
++ HW_VAR_CHECK_BSSID,
++ HW_VAR_MLME_DISCONNECT,
++ HW_VAR_MLME_SITESURVEY,
++ HW_VAR_MLME_JOIN,
++ HW_VAR_ON_RCR_AM,
++ HW_VAR_OFF_RCR_AM,
++ HW_VAR_BEACON_INTERVAL,
++ HW_VAR_SLOT_TIME,
++ HW_VAR_RESP_SIFS,
++ HW_VAR_ACK_PREAMBLE,
++ HW_VAR_SEC_CFG,
++ HW_VAR_BCN_VALID,
++ HW_VAR_RF_TYPE,
++ HW_VAR_DM_FLAG,
++ HW_VAR_DM_FUNC_OP,
++ HW_VAR_DM_FUNC_SET,
++ HW_VAR_DM_FUNC_CLR,
++ HW_VAR_DM_INIT_PWDB,
++ HW_VAR_CAM_EMPTY_ENTRY,
++ HW_VAR_CAM_INVALID_ALL,
++ HW_VAR_CAM_WRITE,
++ HW_VAR_CAM_READ,
++ HW_VAR_AC_PARAM_VO,
++ HW_VAR_AC_PARAM_VI,
++ HW_VAR_AC_PARAM_BE,
++ HW_VAR_AC_PARAM_BK,
++ HW_VAR_ACM_CTRL,
++ HW_VAR_AMPDU_MIN_SPACE,
++ HW_VAR_AMPDU_FACTOR,
++ HW_VAR_RXDMA_AGG_PG_TH,
++ HW_VAR_SET_RPWM,
++ HW_VAR_H2C_FW_PWRMODE,
++ HW_VAR_H2C_FW_JOINBSSRPT,
++ HW_VAR_FWLPS_RF_ON,
++ HW_VAR_H2C_FW_P2P_PS_OFFLOAD,
++ HW_VAR_TDLS_WRCR,
++ HW_VAR_TDLS_INIT_CH_SEN,
++ HW_VAR_TDLS_RS_RCR,
++ HW_VAR_TDLS_DONE_CH_SEN,
++ HW_VAR_INITIAL_GAIN,
++ HW_VAR_TRIGGER_GPIO_0,
++ HW_VAR_BT_SET_COEXIST,
++ HW_VAR_BT_ISSUE_DELBA,
++ HW_VAR_CURRENT_ANTENNA,
++ HW_VAR_ANTENNA_DIVERSITY_LINK,
++ HW_VAR_ANTENNA_DIVERSITY_SELECT,
++ HW_VAR_SWITCH_EPHY_WoWLAN,
++ HW_VAR_EFUSE_BYTES,
++ HW_VAR_FIFO_CLEARN_UP,
++ HW_VAR_CHECK_TXBUF,
++ HW_VAR_APFM_ON_MAC, //Auto FSM to Turn On, include clock, isolation, power control for MAC only
++ HW_VAR_WOWLAN,
++ HW_VAR_VID,
++ HW_VAR_PID,
++ HW_VAR_MBSSID_CAM_WRITE,
++ HW_VAR_MBSSID_CAM_CLEAR,
++ HW_VAR_RCR_MBSSID_EN,
++ HW_VAR_USB_RXAGG_PAGE_TO,
++}HW_VARIABLES;
++
++typedef enum _HAL_DEF_VARIABLE{
++ HAL_DEF_UNDERCORATEDSMOOTHEDPWDB,
++ HAL_DEF_IS_SUPPORT_ANT_DIV,
++ HAL_DEF_CURRENT_ANTENNA,
++ HAL_DEF_DRVINFO_SZ,
++ HAL_DEF_MAX_RECVBUF_SZ,
++ HAL_DEF_RX_PACKET_OFFSET,
++ HAL_DEF_DBG_DUMP_RXPKT,//for dbg
++ HAL_DEF_DBG_DM_FUNC,//for dbg
++ HAL_DEF_DUAL_MAC_MODE,
++}HAL_DEF_VARIABLE;
++
++typedef enum _HAL_INTF_PS_FUNC{
++ HAL_USB_SELECT_SUSPEND,
++ HAL_MAX_ID,
++}HAL_INTF_PS_FUNC;
++
++typedef s32 (*c2h_id_filter)(u8 id);
++
++struct hal_ops {
++ u32 (*hal_init)(PADAPTER Adapter);
++ u32 (*hal_deinit)(PADAPTER Adapter);
++
++ void (*free_hal_data)(PADAPTER Adapter);
++
++ u32 (*inirp_init)(PADAPTER Adapter);
++ u32 (*inirp_deinit)(PADAPTER Adapter);
++
++ s32 (*init_xmit_priv)(PADAPTER Adapter);
++ void (*free_xmit_priv)(PADAPTER Adapter);
++
++ s32 (*init_recv_priv)(PADAPTER Adapter);
++ void (*free_recv_priv)(PADAPTER Adapter);
++
++ void (*InitSwLeds)(PADAPTER Adapter);
++ void (*DeInitSwLeds)(PADAPTER Adapter);
++
++ void (*dm_init)(PADAPTER Adapter);
++ void (*dm_deinit)(PADAPTER Adapter);
++ void (*read_chip_version)(PADAPTER Adapter);
++
++ void (*init_default_value)(PADAPTER Adapter);
++
++ void (*intf_chip_configure)(PADAPTER Adapter);
++
++ void (*read_adapter_info)(PADAPTER Adapter);
++
++ void (*enable_interrupt)(PADAPTER Adapter);
++ void (*disable_interrupt)(PADAPTER Adapter);
++ s32 (*interrupt_handler)(PADAPTER Adapter);
++
++ void (*set_bwmode_handler)(PADAPTER Adapter, HT_CHANNEL_WIDTH Bandwidth, u8 Offset);
++ void (*set_channel_handler)(PADAPTER Adapter, u8 channel);
++
++ void (*hal_dm_watchdog)(PADAPTER Adapter);
++
++ void (*SetHwRegHandler)(PADAPTER Adapter, u8 variable,u8* val);
++ void (*GetHwRegHandler)(PADAPTER Adapter, u8 variable,u8* val);
++
++ u8 (*GetHalDefVarHandler)(PADAPTER Adapter, HAL_DEF_VARIABLE eVariable, PVOID pValue);
++ u8 (*SetHalDefVarHandler)(PADAPTER Adapter, HAL_DEF_VARIABLE eVariable, PVOID pValue);
++
++ void (*UpdateRAMaskHandler)(PADAPTER Adapter, u32 mac_id);
++ void (*SetBeaconRelatedRegistersHandler)(PADAPTER Adapter);
++
++ void (*Add_RateATid)(PADAPTER Adapter, u32 bitmap, u8 arg);
++
++#ifdef CONFIG_ANTENNA_DIVERSITY
++ u8 (*AntDivBeforeLinkHandler)(PADAPTER Adapter);
++ void (*AntDivCompareHandler)(PADAPTER Adapter, WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src);
++#endif
++ u8 (*interface_ps_func)(PADAPTER Adapter,HAL_INTF_PS_FUNC efunc_id, u8* val);
++
++ s32 (*hal_xmit)(PADAPTER Adapter, struct xmit_frame *pxmitframe);
++ s32 (*mgnt_xmit)(PADAPTER Adapter, struct xmit_frame *pmgntframe);
++ s32 (*hal_xmitframe_enqueue)(_adapter *padapter, struct xmit_frame *pxmitframe);
++
++ u32 (*read_bbreg)(PADAPTER Adapter, u32 RegAddr, u32 BitMask);
++ void (*write_bbreg)(PADAPTER Adapter, u32 RegAddr, u32 BitMask, u32 Data);
++ u32 (*read_rfreg)(PADAPTER Adapter, u32 eRFPath, u32 RegAddr, u32 BitMask);
++ void (*write_rfreg)(PADAPTER Adapter, u32 eRFPath, u32 RegAddr, u32 BitMask, u32 Data);
++
++#ifdef CONFIG_HOSTAPD_MLME
++ s32 (*hostap_mgnt_xmit_entry)(PADAPTER Adapter, _pkt *pkt);
++#endif
++ void (*EfusePowerSwitch)(PADAPTER pAdapter, u8 bWrite, u8 PwrState);
++ void (*ReadEFuse)(PADAPTER Adapter, u8 efuseType, u16 _offset, u16 _size_byte, u8 *pbuf, BOOLEAN bPseudoTest);
++ void (*EFUSEGetEfuseDefinition)(PADAPTER pAdapter, u8 efuseType, u8 type, PVOID *pOut, BOOLEAN bPseudoTest);
++ u16 (*EfuseGetCurrentSize)(PADAPTER pAdapter, u8 efuseType, BOOLEAN bPseudoTest);
++ int (*Efuse_PgPacketRead)(PADAPTER pAdapter, u8 offset, u8 *data, BOOLEAN bPseudoTest);
++ int (*Efuse_PgPacketWrite)(PADAPTER pAdapter, u8 offset, u8 word_en, u8 *data, BOOLEAN bPseudoTest);
++ u8 (*Efuse_WordEnableDataWrite)(PADAPTER pAdapter, u16 efuse_addr, u8 word_en, u8 *data, BOOLEAN bPseudoTest);
++
++#ifdef DBG_CONFIG_ERROR_DETECT
++ void (*sreset_init_value)(_adapter *padapter);
++ void (*sreset_reset_value)(_adapter *padapter);
++ void (*silentreset)(_adapter *padapter);
++ void (*sreset_xmit_status_check)(_adapter *padapter);
++ void (*sreset_linked_status_check) (_adapter *padapter);
++ u8 (*sreset_get_wifi_status)(_adapter *padapter);
++ bool (*sreset_inprogress)(_adapter *padapter);
++#endif
++
++#ifdef CONFIG_IOL
++ int (*IOL_exec_cmds_sync)(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms);
++#endif
++ void (*hal_notch_filter)(_adapter * adapter, bool enable);
++ void (*hal_reset_security_engine)(_adapter * adapter);
++
++ s32 (*c2h_handler)(_adapter *padapter, struct c2h_evt_hdr *c2h_evt);
++ c2h_id_filter c2h_id_filter_ccx;
++};
++
++typedef enum _RT_EEPROM_TYPE{
++ EEPROM_93C46,
++ EEPROM_93C56,
++ EEPROM_BOOT_EFUSE,
++}RT_EEPROM_TYPE,*PRT_EEPROM_TYPE;
++
++#define USB_HIGH_SPEED_BULK_SIZE 512
++#define USB_FULL_SPEED_BULK_SIZE 64
++
++#define RF_CHANGE_BY_INIT 0
++#define RF_CHANGE_BY_IPS BIT28
++#define RF_CHANGE_BY_PS BIT29
++#define RF_CHANGE_BY_HW BIT30
++#define RF_CHANGE_BY_SW BIT31
++
++typedef enum _HARDWARE_TYPE{
++ HARDWARE_TYPE_RTL8180,
++ HARDWARE_TYPE_RTL8185,
++ HARDWARE_TYPE_RTL8187,
++ HARDWARE_TYPE_RTL8188,
++ HARDWARE_TYPE_RTL8190P,
++ HARDWARE_TYPE_RTL8192E,
++ HARDWARE_TYPE_RTL819xU,
++ HARDWARE_TYPE_RTL8192SE,
++ HARDWARE_TYPE_RTL8192SU,
++ HARDWARE_TYPE_RTL8192CE,
++ HARDWARE_TYPE_RTL8192CU,
++ HARDWARE_TYPE_RTL8192DE,
++ HARDWARE_TYPE_RTL8192DU,
++ HARDWARE_TYPE_RTL8723AE,
++ HARDWARE_TYPE_RTL8723AU,
++ HARDWARE_TYPE_RTL8723AS,
++ HARDWARE_TYPE_RTL8188EE,
++ HARDWARE_TYPE_RTL8188EU,
++ HARDWARE_TYPE_RTL8188ES,
++ HARDWARE_TYPE_MAX,
++}HARDWARE_TYPE;
++
++//
++// RTL8192C Series
++//
++#define IS_HARDWARE_TYPE_8192CE(_Adapter) (((PADAPTER)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8192CE)
++#define IS_HARDWARE_TYPE_8192CU(_Adapter) (((PADAPTER)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8192CU)
++#define IS_HARDWARE_TYPE_8192C(_Adapter) \
++(IS_HARDWARE_TYPE_8192CE(_Adapter) || IS_HARDWARE_TYPE_8192CU(_Adapter))
++
++//
++// RTL8192D Series
++//
++#define IS_HARDWARE_TYPE_8192DE(_Adapter) (((PADAPTER)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8192DE)
++#define IS_HARDWARE_TYPE_8192DU(_Adapter) (((PADAPTER)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8192DU)
++#define IS_HARDWARE_TYPE_8192D(_Adapter) \
++(IS_HARDWARE_TYPE_8192DE(_Adapter) || IS_HARDWARE_TYPE_8192DU(_Adapter))
++
++//
++// RTL8723A Series
++//
++#define IS_HARDWARE_TYPE_8723AE(_Adapter) (((PADAPTER)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8723AE)
++#define IS_HARDWARE_TYPE_8723AU(_Adapter) (((PADAPTER)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8723AU)
++#define IS_HARDWARE_TYPE_8723AS(_Adapter) (((PADAPTER)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8723AS)
++#define IS_HARDWARE_TYPE_8723A(_Adapter) \
++(IS_HARDWARE_TYPE_8723AE(_Adapter) || IS_HARDWARE_TYPE_8723AU(_Adapter) || IS_HARDWARE_TYPE_8723AS(_Adapter))
++
++//
++// RTL8188E Series
++//
++#define IS_HARDWARE_TYPE_8188EE(_Adapter) (((PADAPTER)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8188EE)
++#define IS_HARDWARE_TYPE_8188EU(_Adapter) (((PADAPTER)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8188EU)
++#define IS_HARDWARE_TYPE_8188ES(_Adapter) (((PADAPTER)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8188ES)
++#define IS_HARDWARE_TYPE_8188E(_Adapter) \
++(IS_HARDWARE_TYPE_8188EE(_Adapter) || IS_HARDWARE_TYPE_8188EU(_Adapter) || IS_HARDWARE_TYPE_8188ES(_Adapter))
++
++
++typedef struct eeprom_priv EEPROM_EFUSE_PRIV, *PEEPROM_EFUSE_PRIV;
++#define GET_EEPROM_EFUSE_PRIV(priv) (&priv->eeprompriv)
++
++#ifdef CONFIG_WOWLAN
++typedef enum _wowlan_subcode{
++ WOWLAN_PATTERN_MATCH = 1,
++ WOWLAN_MAGIC_PACKET = 2,
++ WOWLAN_UNICAST = 3,
++ WOWLAN_SET_PATTERN = 4,
++ WOWLAN_DUMP_REG = 5,
++ WOWLAN_ENABLE = 6,
++ WOWLAN_DISABLE = 7,
++ WOWLAN_STATUS = 8,
++ WOWLAN_DEBUG_RELOAD_FW = 9,
++ WOWLAN_DEBUG_1 =10,
++ WOWLAN_DEBUG_2 =11
++}wowlan_subcode;
++
++struct wowlan_ioctl_param{
++ unsigned int subcode;
++ unsigned int subcode_value;
++ unsigned int wakeup_reason;
++ unsigned int len;
++ unsigned char pattern[0];
++};
++
++#define Rx_Pairwisekey BIT(0)
++#define Rx_GTK BIT(1)
++#define Rx_DisAssoc BIT(2)
++#define Rx_DeAuth BIT(3)
++#define FWDecisionDisconnect BIT(4)
++#define Rx_MagicPkt BIT(5)
++#define FinishBtFwPatch BIT(7)
++
++#endif // CONFIG_WOWLAN
++
++void rtw_hal_def_value_init(_adapter *padapter);
++void rtw_hal_free_data(_adapter *padapter);
++
++void rtw_hal_dm_init(_adapter *padapter);
++void rtw_hal_dm_deinit(_adapter *padapter);
++void rtw_hal_sw_led_init(_adapter *padapter);
++void rtw_hal_sw_led_deinit(_adapter *padapter);
++
++uint rtw_hal_init(_adapter *padapter);
++uint rtw_hal_deinit(_adapter *padapter);
++void rtw_hal_stop(_adapter *padapter);
++
++void rtw_hal_set_hwreg(PADAPTER padapter, u8 variable, u8 *val);
++void rtw_hal_get_hwreg(PADAPTER padapter, u8 variable, u8 *val);
++
++void rtw_hal_chip_configure(_adapter *padapter);
++void rtw_hal_read_chip_info(_adapter *padapter);
++void rtw_hal_read_chip_version(_adapter *padapter);
++
++u8 rtw_hal_set_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, PVOID pValue);
++u8 rtw_hal_get_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, PVOID pValue);
++
++void rtw_hal_enable_interrupt(_adapter *padapter);
++void rtw_hal_disable_interrupt(_adapter *padapter);
++
++u32 rtw_hal_inirp_init(_adapter *padapter);
++u32 rtw_hal_inirp_deinit(_adapter *padapter);
++
++u8 rtw_hal_intf_ps_func(_adapter *padapter,HAL_INTF_PS_FUNC efunc_id, u8* val);
++
++s32 rtw_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
++s32 rtw_hal_xmit(_adapter *padapter, struct xmit_frame *pxmitframe);
++s32 rtw_hal_mgnt_xmit(_adapter *padapter, struct xmit_frame *pmgntframe);
++
++s32 rtw_hal_init_xmit_priv(_adapter *padapter);
++void rtw_hal_free_xmit_priv(_adapter *padapter);
++
++s32 rtw_hal_init_recv_priv(_adapter *padapter);
++void rtw_hal_free_recv_priv(_adapter *padapter);
++
++void rtw_hal_update_ra_mask(_adapter *padapter, u32 mac_id);
++void rtw_hal_add_ra_tid(_adapter *padapter, u32 bitmap, u8 arg);
++
++void rtw_hal_bcn_related_reg_setting(_adapter *padapter);
++
++u32 rtw_hal_read_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask);
++void rtw_hal_write_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data);
++u32 rtw_hal_read_rfreg(_adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMask);
++void rtw_hal_write_rfreg(_adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMask, u32 Data);
++
++s32 rtw_hal_interrupt_handler(_adapter *padapter);
++
++void rtw_hal_set_bwmode(_adapter *padapter, HT_CHANNEL_WIDTH Bandwidth, u8 Offset);
++void rtw_hal_set_chan(_adapter *padapter, u8 channel);
++
++void rtw_hal_dm_watchdog(_adapter *padapter);
++
++#ifdef CONFIG_ANTENNA_DIVERSITY
++u8 rtw_hal_antdiv_before_linked(_adapter *padapter);
++void rtw_hal_antdiv_rssi_compared(_adapter *padapter, WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src);
++#endif
++
++#ifdef CONFIG_HOSTAPD_MLME
++s32 rtw_hal_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt);
++#endif
++
++#ifdef DBG_CONFIG_ERROR_DETECT
++void rtw_hal_sreset_init(_adapter *padapter);
++void rtw_hal_sreset_reset(_adapter *padapter);
++void rtw_hal_sreset_reset_value(_adapter *padapter);
++void rtw_hal_sreset_xmit_status_check(_adapter *padapter);
++void rtw_hal_sreset_linked_status_check(_adapter *padapter);
++u8 rtw_hal_sreset_get_wifi_status(_adapter *padapter);
++bool rtw_hal_sreset_inprogress(_adapter *padapter);
++#endif
++
++#ifdef CONFIG_IOL
++int rtw_hal_iol_cmd(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms);
++#endif
++
++void rtw_hal_notch_filter(_adapter * adapter, bool enable);
++void rtw_hal_reset_security_engine(_adapter * adapter);
++
++s32 rtw_hal_c2h_handler(_adapter *adapter, struct c2h_evt_hdr *c2h_evt);
++c2h_id_filter rtw_hal_c2h_id_filter_ccx(_adapter *adapter);
++
++#endif //__HAL_INTF_H__
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/HalPwrSeqCmd.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/HalPwrSeqCmd.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/HalPwrSeqCmd.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/HalPwrSeqCmd.h 2015-07-28 01:20:58.317611539 +0200
+@@ -0,0 +1,137 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef __HALPWRSEQCMD_H__
++#define __HALPWRSEQCMD_H__
++
++#include <drv_types.h>
++
++/*---------------------------------------------*/
++//3 The value of cmd: 4 bits
++/*---------------------------------------------*/
++#define PWR_CMD_READ 0x00
++ // offset: the read register offset
++ // msk: the mask of the read value
++ // value: N/A, left by 0
++ // note: dirver shall implement this function by read & msk
++
++#define PWR_CMD_WRITE 0x01
++ // offset: the read register offset
++ // msk: the mask of the write bits
++ // value: write value
++ // note: driver shall implement this cmd by read & msk after write
++
++#define PWR_CMD_POLLING 0x02
++ // offset: the read register offset
++ // msk: the mask of the polled value
++ // value: the value to be polled, masked by the msd field.
++ // note: driver shall implement this cmd by
++ // do{
++ // if( (Read(offset) & msk) == (value & msk) )
++ // break;
++ // } while(not timeout);
++
++#define PWR_CMD_DELAY 0x03
++ // offset: the value to delay
++ // msk: N/A
++ // value: the unit of delay, 0: us, 1: ms
++
++#define PWR_CMD_END 0x04
++ // offset: N/A
++ // msk: N/A
++ // value: N/A
++
++/*---------------------------------------------*/
++//3 The value of base: 4 bits
++/*---------------------------------------------*/
++ // define the base address of each block
++#define PWR_BASEADDR_MAC 0x00
++#define PWR_BASEADDR_USB 0x01
++#define PWR_BASEADDR_PCIE 0x02
++#define PWR_BASEADDR_SDIO 0x03
++
++/*---------------------------------------------*/
++//3 The value of interface_msk: 4 bits
++/*---------------------------------------------*/
++#define PWR_INTF_SDIO_MSK BIT(0)
++#define PWR_INTF_USB_MSK BIT(1)
++#define PWR_INTF_PCI_MSK BIT(2)
++#define PWR_INTF_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3))
++
++/*---------------------------------------------*/
++//3 The value of fab_msk: 4 bits
++/*---------------------------------------------*/
++#define PWR_FAB_TSMC_MSK BIT(0)
++#define PWR_FAB_UMC_MSK BIT(1)
++#define PWR_FAB_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3))
++
++/*---------------------------------------------*/
++//3 The value of cut_msk: 8 bits
++/*---------------------------------------------*/
++#define PWR_CUT_TESTCHIP_MSK BIT(0)
++#define PWR_CUT_A_MSK BIT(1)
++#define PWR_CUT_B_MSK BIT(2)
++#define PWR_CUT_C_MSK BIT(3)
++#define PWR_CUT_D_MSK BIT(4)
++#define PWR_CUT_E_MSK BIT(5)
++#define PWR_CUT_F_MSK BIT(6)
++#define PWR_CUT_G_MSK BIT(7)
++#define PWR_CUT_ALL_MSK 0xFF
++
++
++typedef enum _PWRSEQ_CMD_DELAY_UNIT_
++{
++ PWRSEQ_DELAY_US,
++ PWRSEQ_DELAY_MS,
++} PWRSEQ_DELAY_UNIT;
++
++typedef struct _WL_PWR_CFG_
++{
++ u16 offset;
++ u8 cut_msk;
++ u8 fab_msk:4;
++ u8 interface_msk:4;
++ u8 base:4;
++ u8 cmd:4;
++ u8 msk;
++ u8 value;
++} WLAN_PWR_CFG, *PWLAN_PWR_CFG;
++
++
++#define GET_PWR_CFG_OFFSET(__PWR_CMD) __PWR_CMD.offset
++#define GET_PWR_CFG_CUT_MASK(__PWR_CMD) __PWR_CMD.cut_msk
++#define GET_PWR_CFG_FAB_MASK(__PWR_CMD) __PWR_CMD.fab_msk
++#define GET_PWR_CFG_INTF_MASK(__PWR_CMD) __PWR_CMD.interface_msk
++#define GET_PWR_CFG_BASE(__PWR_CMD) __PWR_CMD.base
++#define GET_PWR_CFG_CMD(__PWR_CMD) __PWR_CMD.cmd
++#define GET_PWR_CFG_MASK(__PWR_CMD) __PWR_CMD.msk
++#define GET_PWR_CFG_VALUE(__PWR_CMD) __PWR_CMD.value
++
++
++//================================================================================
++// Prototype of protected function.
++//================================================================================
++u8 HalPwrSeqCmdParsing(
++ PADAPTER padapter,
++ u8 CutVersion,
++ u8 FabVersion,
++ u8 InterfaceType,
++ WLAN_PWR_CFG PwrCfgCmd[]);
++
++#endif
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/ieee80211_ext.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/ieee80211_ext.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/ieee80211_ext.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/ieee80211_ext.h 2015-07-28 01:20:58.317611539 +0200
+@@ -0,0 +1,476 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef __IEEE80211_EXT_H
++#define __IEEE80211_EXT_H
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++
++#define WMM_OUI_TYPE 2
++#define WMM_OUI_SUBTYPE_INFORMATION_ELEMENT 0
++#define WMM_OUI_SUBTYPE_PARAMETER_ELEMENT 1
++#define WMM_OUI_SUBTYPE_TSPEC_ELEMENT 2
++#define WMM_VERSION 1
++
++#define WPA_PROTO_WPA BIT(0)
++#define WPA_PROTO_RSN BIT(1)
++
++#define WPA_KEY_MGMT_IEEE8021X BIT(0)
++#define WPA_KEY_MGMT_PSK BIT(1)
++#define WPA_KEY_MGMT_NONE BIT(2)
++#define WPA_KEY_MGMT_IEEE8021X_NO_WPA BIT(3)
++#define WPA_KEY_MGMT_WPA_NONE BIT(4)
++
++
++#define WPA_CAPABILITY_PREAUTH BIT(0)
++#define WPA_CAPABILITY_MGMT_FRAME_PROTECTION BIT(6)
++#define WPA_CAPABILITY_PEERKEY_ENABLED BIT(9)
++
++
++#define PMKID_LEN 16
++
++
++#ifdef PLATFORM_LINUX
++struct wpa_ie_hdr {
++ u8 elem_id;
++ u8 len;
++ u8 oui[4]; /* 24-bit OUI followed by 8-bit OUI type */
++ u8 version[2]; /* little endian */
++}__attribute__ ((packed));
++
++struct rsn_ie_hdr {
++ u8 elem_id; /* WLAN_EID_RSN */
++ u8 len;
++ u8 version[2]; /* little endian */
++}__attribute__ ((packed));
++
++struct wme_ac_parameter {
++#if defined(CONFIG_LITTLE_ENDIAN)
++ /* byte 1 */
++ u8 aifsn:4,
++ acm:1,
++ aci:2,
++ reserved:1;
++
++ /* byte 2 */
++ u8 eCWmin:4,
++ eCWmax:4;
++#elif defined(CONFIG_BIG_ENDIAN)
++ /* byte 1 */
++ u8 reserved:1,
++ aci:2,
++ acm:1,
++ aifsn:4;
++
++ /* byte 2 */
++ u8 eCWmax:4,
++ eCWmin:4;
++#else
++#error "Please fix <endian.h>"
++#endif
++
++ /* bytes 3 & 4 */
++ u16 txopLimit;
++} __attribute__ ((packed));
++
++struct wme_parameter_element {
++ /* required fields for WME version 1 */
++ u8 oui[3];
++ u8 oui_type;
++ u8 oui_subtype;
++ u8 version;
++ u8 acInfo;
++ u8 reserved;
++ struct wme_ac_parameter ac[4];
++
++} __attribute__ ((packed));
++
++#endif
++
++#ifdef PLATFORM_WINDOWS
++
++#pragma pack(1)
++
++struct wpa_ie_hdr {
++ u8 elem_id;
++ u8 len;
++ u8 oui[4]; /* 24-bit OUI followed by 8-bit OUI type */
++ u8 version[2]; /* little endian */
++};
++
++struct rsn_ie_hdr {
++ u8 elem_id; /* WLAN_EID_RSN */
++ u8 len;
++ u8 version[2]; /* little endian */
++};
++
++#pragma pack()
++
++#endif
++
++#define WPA_PUT_LE16(a, val) \
++ do { \
++ (a)[1] = ((u16) (val)) >> 8; \
++ (a)[0] = ((u16) (val)) & 0xff; \
++ } while (0)
++
++#define WPA_PUT_BE32(a, val) \
++ do { \
++ (a)[0] = (u8) ((((u32) (val)) >> 24) & 0xff); \
++ (a)[1] = (u8) ((((u32) (val)) >> 16) & 0xff); \
++ (a)[2] = (u8) ((((u32) (val)) >> 8) & 0xff); \
++ (a)[3] = (u8) (((u32) (val)) & 0xff); \
++ } while (0)
++
++#define WPA_PUT_LE32(a, val) \
++ do { \
++ (a)[3] = (u8) ((((u32) (val)) >> 24) & 0xff); \
++ (a)[2] = (u8) ((((u32) (val)) >> 16) & 0xff); \
++ (a)[1] = (u8) ((((u32) (val)) >> 8) & 0xff); \
++ (a)[0] = (u8) (((u32) (val)) & 0xff); \
++ } while (0)
++
++#define RSN_SELECTOR_PUT(a, val) WPA_PUT_BE32((u8 *) (a), (val))
++//#define RSN_SELECTOR_PUT(a, val) WPA_PUT_LE32((u8 *) (a), (val))
++
++
++
++/* Action category code */
++enum ieee80211_category {
++ WLAN_CATEGORY_SPECTRUM_MGMT = 0,
++ WLAN_CATEGORY_QOS = 1,
++ WLAN_CATEGORY_DLS = 2,
++ WLAN_CATEGORY_BACK = 3,
++ WLAN_CATEGORY_HT = 7,
++ WLAN_CATEGORY_WMM = 17,
++};
++
++/* SPECTRUM_MGMT action code */
++enum ieee80211_spectrum_mgmt_actioncode {
++ WLAN_ACTION_SPCT_MSR_REQ = 0,
++ WLAN_ACTION_SPCT_MSR_RPRT = 1,
++ WLAN_ACTION_SPCT_TPC_REQ = 2,
++ WLAN_ACTION_SPCT_TPC_RPRT = 3,
++ WLAN_ACTION_SPCT_CHL_SWITCH = 4,
++ WLAN_ACTION_SPCT_EXT_CHL_SWITCH = 5,
++};
++
++/* BACK action code */
++enum ieee80211_back_actioncode {
++ WLAN_ACTION_ADDBA_REQ = 0,
++ WLAN_ACTION_ADDBA_RESP = 1,
++ WLAN_ACTION_DELBA = 2,
++};
++
++/* HT features action code */
++enum ieee80211_ht_actioncode {
++ WLAN_ACTION_NOTIFY_CH_WIDTH = 0,
++ WLAN_ACTION_SM_PS = 1,
++ WLAN_ACTION_PSPM = 2,
++ WLAN_ACTION_PCO_PHASE = 3,
++ WLAN_ACTION_MIMO_CSI_MX = 4,
++ WLAN_ACTION_MIMO_NONCP_BF = 5,
++ WLAN_ACTION_MIMP_CP_BF = 6,
++ WLAN_ACTION_ASEL_INDICATES_FB = 7,
++ WLAN_ACTION_HI_INFO_EXCHG = 8,
++};
++
++/* BACK (block-ack) parties */
++enum ieee80211_back_parties {
++ WLAN_BACK_RECIPIENT = 0,
++ WLAN_BACK_INITIATOR = 1,
++ WLAN_BACK_TIMER = 2,
++};
++
++#ifdef PLATFORM_LINUX
++
++struct ieee80211_mgmt {
++ u16 frame_control;
++ u16 duration;
++ u8 da[6];
++ u8 sa[6];
++ u8 bssid[6];
++ u16 seq_ctrl;
++ union {
++ struct {
++ u16 auth_alg;
++ u16 auth_transaction;
++ u16 status_code;
++ /* possibly followed by Challenge text */
++ u8 variable[0];
++ } __attribute__ ((packed)) auth;
++ struct {
++ u16 reason_code;
++ } __attribute__ ((packed)) deauth;
++ struct {
++ u16 capab_info;
++ u16 listen_interval;
++ /* followed by SSID and Supported rates */
++ u8 variable[0];
++ } __attribute__ ((packed)) assoc_req;
++ struct {
++ u16 capab_info;
++ u16 status_code;
++ u16 aid;
++ /* followed by Supported rates */
++ u8 variable[0];
++ } __attribute__ ((packed)) assoc_resp, reassoc_resp;
++ struct {
++ u16 capab_info;
++ u16 listen_interval;
++ u8 current_ap[6];
++ /* followed by SSID and Supported rates */
++ u8 variable[0];
++ } __attribute__ ((packed)) reassoc_req;
++ struct {
++ u16 reason_code;
++ } __attribute__ ((packed)) disassoc;
++ struct {
++ __le64 timestamp;
++ u16 beacon_int;
++ u16 capab_info;
++ /* followed by some of SSID, Supported rates,
++ * FH Params, DS Params, CF Params, IBSS Params, TIM */
++ u8 variable[0];
++ } __attribute__ ((packed)) beacon;
++ struct {
++ /* only variable items: SSID, Supported rates */
++ u8 variable[0];
++ } __attribute__ ((packed)) probe_req;
++ struct {
++ __le64 timestamp;
++ u16 beacon_int;
++ u16 capab_info;
++ /* followed by some of SSID, Supported rates,
++ * FH Params, DS Params, CF Params, IBSS Params */
++ u8 variable[0];
++ } __attribute__ ((packed)) probe_resp;
++ struct {
++ u8 category;
++ union {
++ struct {
++ u8 action_code;
++ u8 dialog_token;
++ u8 status_code;
++ u8 variable[0];
++ } __attribute__ ((packed)) wme_action;
++#if 0
++ struct{
++ u8 action_code;
++ u8 element_id;
++ u8 length;
++ struct ieee80211_channel_sw_ie sw_elem;
++ } __attribute__ ((packed)) chan_switch;
++ struct{
++ u8 action_code;
++ u8 dialog_token;
++ u8 element_id;
++ u8 length;
++ struct ieee80211_msrment_ie msr_elem;
++ } __attribute__ ((packed)) measurement;
++#endif
++ struct{
++ u8 action_code;
++ u8 dialog_token;
++ u16 capab;
++ u16 timeout;
++ u16 start_seq_num;
++ } __attribute__ ((packed)) addba_req;
++ struct{
++ u8 action_code;
++ u8 dialog_token;
++ u16 status;
++ u16 capab;
++ u16 timeout;
++ } __attribute__ ((packed)) addba_resp;
++ struct{
++ u8 action_code;
++ u16 params;
++ u16 reason_code;
++ } __attribute__ ((packed)) delba;
++ struct{
++ u8 action_code;
++ /* capab_info for open and confirm,
++ * reason for close
++ */
++ u16 aux;
++ /* Followed in plink_confirm by status
++ * code, AID and supported rates,
++ * and directly by supported rates in
++ * plink_open and plink_close
++ */
++ u8 variable[0];
++ } __attribute__ ((packed)) plink_action;
++ struct{
++ u8 action_code;
++ u8 variable[0];
++ } __attribute__ ((packed)) mesh_action;
++ } __attribute__ ((packed)) u;
++ } __attribute__ ((packed)) action;
++ } __attribute__ ((packed)) u;
++}__attribute__ ((packed));
++
++#endif
++
++
++#ifdef PLATFORM_WINDOWS
++
++#pragma pack(1)
++
++struct ieee80211_mgmt {
++ u16 frame_control;
++ u16 duration;
++ u8 da[6];
++ u8 sa[6];
++ u8 bssid[6];
++ u16 seq_ctrl;
++ union {
++ struct {
++ u16 auth_alg;
++ u16 auth_transaction;
++ u16 status_code;
++ /* possibly followed by Challenge text */
++ u8 variable[0];
++ } auth;
++ struct {
++ u16 reason_code;
++ } deauth;
++ struct {
++ u16 capab_info;
++ u16 listen_interval;
++ /* followed by SSID and Supported rates */
++ u8 variable[0];
++ } assoc_req;
++ struct {
++ u16 capab_info;
++ u16 status_code;
++ u16 aid;
++ /* followed by Supported rates */
++ u8 variable[0];
++ } assoc_resp, reassoc_resp;
++ struct {
++ u16 capab_info;
++ u16 listen_interval;
++ u8 current_ap[6];
++ /* followed by SSID and Supported rates */
++ u8 variable[0];
++ } reassoc_req;
++ struct {
++ u16 reason_code;
++ } disassoc;
++#if 0
++ struct {
++ __le64 timestamp;
++ u16 beacon_int;
++ u16 capab_info;
++ /* followed by some of SSID, Supported rates,
++ * FH Params, DS Params, CF Params, IBSS Params, TIM */
++ u8 variable[0];
++ } beacon;
++ struct {
++ /* only variable items: SSID, Supported rates */
++ u8 variable[0];
++ } probe_req;
++
++ struct {
++ __le64 timestamp;
++ u16 beacon_int;
++ u16 capab_info;
++ /* followed by some of SSID, Supported rates,
++ * FH Params, DS Params, CF Params, IBSS Params */
++ u8 variable[0];
++ } probe_resp;
++#endif
++ struct {
++ u8 category;
++ union {
++ struct {
++ u8 action_code;
++ u8 dialog_token;
++ u8 status_code;
++ u8 variable[0];
++ } wme_action;
++/*
++ struct{
++ u8 action_code;
++ u8 element_id;
++ u8 length;
++ struct ieee80211_channel_sw_ie sw_elem;
++ } chan_switch;
++ struct{
++ u8 action_code;
++ u8 dialog_token;
++ u8 element_id;
++ u8 length;
++ struct ieee80211_msrment_ie msr_elem;
++ } measurement;
++*/
++ struct{
++ u8 action_code;
++ u8 dialog_token;
++ u16 capab;
++ u16 timeout;
++ u16 start_seq_num;
++ } addba_req;
++ struct{
++ u8 action_code;
++ u8 dialog_token;
++ u16 status;
++ u16 capab;
++ u16 timeout;
++ } addba_resp;
++ struct{
++ u8 action_code;
++ u16 params;
++ u16 reason_code;
++ } delba;
++ struct{
++ u8 action_code;
++ /* capab_info for open and confirm,
++ * reason for close
++ */
++ u16 aux;
++ /* Followed in plink_confirm by status
++ * code, AID and supported rates,
++ * and directly by supported rates in
++ * plink_open and plink_close
++ */
++ u8 variable[0];
++ } plink_action;
++ struct{
++ u8 action_code;
++ u8 variable[0];
++ } mesh_action;
++ } u;
++ } action;
++ } u;
++} ;
++
++#pragma pack()
++
++#endif
++
++/* mgmt header + 1 byte category code */
++#define IEEE80211_MIN_ACTION_SIZE FIELD_OFFSET(struct ieee80211_mgmt, u.action.u)
++
++
++
++#endif
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/ieee80211.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/ieee80211.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/ieee80211.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/ieee80211.h 2015-07-28 01:20:58.317611539 +0200
+@@ -0,0 +1,1579 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef __IEEE80211_H
++#define __IEEE80211_H
++
++
++#ifndef CONFIG_RTL8711FW
++
++ #include <drv_conf.h>
++ #include <osdep_service.h>
++ #include <drv_types.h>
++ #include "wifi.h"
++
++ #if defined PLATFORM_OS_XP
++ #include <ntstrsafe.h>
++ #endif
++ #if defined PLATFORM_LINUX
++ #include <linux/wireless.h>
++ #endif
++#else
++
++ #include <list.h>
++
++#endif
++
++#define MGMT_QUEUE_NUM 5
++
++#define ETH_ALEN 6
++#define ETH_TYPE_LEN 2
++#define PAYLOAD_TYPE_LEN 1
++
++#ifdef CONFIG_AP_MODE
++
++#define RTL_IOCTL_HOSTAPD (SIOCIWFIRSTPRIV + 28)
++
++/* RTL871X_IOCTL_HOSTAPD ioctl() cmd: */
++enum {
++ RTL871X_HOSTAPD_FLUSH = 1,
++ RTL871X_HOSTAPD_ADD_STA = 2,
++ RTL871X_HOSTAPD_REMOVE_STA = 3,
++ RTL871X_HOSTAPD_GET_INFO_STA = 4,
++ /* REMOVED: PRISM2_HOSTAPD_RESET_TXEXC_STA = 5, */
++ RTL871X_HOSTAPD_GET_WPAIE_STA = 5,
++ RTL871X_SET_ENCRYPTION = 6,
++ RTL871X_GET_ENCRYPTION = 7,
++ RTL871X_HOSTAPD_SET_FLAGS_STA = 8,
++ RTL871X_HOSTAPD_GET_RID = 9,
++ RTL871X_HOSTAPD_SET_RID = 10,
++ RTL871X_HOSTAPD_SET_ASSOC_AP_ADDR = 11,
++ RTL871X_HOSTAPD_SET_GENERIC_ELEMENT = 12,
++ RTL871X_HOSTAPD_MLME = 13,
++ RTL871X_HOSTAPD_SCAN_REQ = 14,
++ RTL871X_HOSTAPD_STA_CLEAR_STATS = 15,
++ RTL871X_HOSTAPD_SET_BEACON=16,
++ RTL871X_HOSTAPD_SET_WPS_BEACON = 17,
++ RTL871X_HOSTAPD_SET_WPS_PROBE_RESP = 18,
++ RTL871X_HOSTAPD_SET_WPS_ASSOC_RESP = 19,
++ RTL871X_HOSTAPD_SET_HIDDEN_SSID = 20,
++ RTL871X_HOSTAPD_SET_MACADDR_ACL = 21,
++ RTL871X_HOSTAPD_ACL_ADD_STA = 22,
++ RTL871X_HOSTAPD_ACL_REMOVE_STA = 23,
++};
++
++/* STA flags */
++#define WLAN_STA_AUTH BIT(0)
++#define WLAN_STA_ASSOC BIT(1)
++#define WLAN_STA_PS BIT(2)
++#define WLAN_STA_TIM BIT(3)
++#define WLAN_STA_PERM BIT(4)
++#define WLAN_STA_AUTHORIZED BIT(5)
++#define WLAN_STA_PENDING_POLL BIT(6) /* pending activity poll not ACKed */
++#define WLAN_STA_SHORT_PREAMBLE BIT(7)
++#define WLAN_STA_PREAUTH BIT(8)
++#define WLAN_STA_WME BIT(9)
++#define WLAN_STA_MFP BIT(10)
++#define WLAN_STA_HT BIT(11)
++#define WLAN_STA_WPS BIT(12)
++#define WLAN_STA_MAYBE_WPS BIT(13)
++#define WLAN_STA_NONERP BIT(31)
++
++#endif
++
++#define IEEE_CMD_SET_WPA_PARAM 1
++#define IEEE_CMD_SET_WPA_IE 2
++#define IEEE_CMD_SET_ENCRYPTION 3
++#define IEEE_CMD_MLME 4
++
++#define IEEE_PARAM_WPA_ENABLED 1
++#define IEEE_PARAM_TKIP_COUNTERMEASURES 2
++#define IEEE_PARAM_DROP_UNENCRYPTED 3
++#define IEEE_PARAM_PRIVACY_INVOKED 4
++#define IEEE_PARAM_AUTH_ALGS 5
++#define IEEE_PARAM_IEEE_802_1X 6
++#define IEEE_PARAM_WPAX_SELECT 7
++
++#define AUTH_ALG_OPEN_SYSTEM 0x1
++#define AUTH_ALG_SHARED_KEY 0x2
++#define AUTH_ALG_LEAP 0x00000004
++
++#define IEEE_MLME_STA_DEAUTH 1
++#define IEEE_MLME_STA_DISASSOC 2
++
++#define IEEE_CRYPT_ERR_UNKNOWN_ALG 2
++#define IEEE_CRYPT_ERR_UNKNOWN_ADDR 3
++#define IEEE_CRYPT_ERR_CRYPT_INIT_FAILED 4
++#define IEEE_CRYPT_ERR_KEY_SET_FAILED 5
++#define IEEE_CRYPT_ERR_TX_KEY_SET_FAILED 6
++#define IEEE_CRYPT_ERR_CARD_CONF_FAILED 7
++
++
++#define IEEE_CRYPT_ALG_NAME_LEN 16
++
++#define WPA_CIPHER_NONE BIT(0)
++#define WPA_CIPHER_WEP40 BIT(1)
++#define WPA_CIPHER_WEP104 BIT(2)
++#define WPA_CIPHER_TKIP BIT(3)
++#define WPA_CIPHER_CCMP BIT(4)
++
++
++
++#define WPA_SELECTOR_LEN 4
++extern u8 RTW_WPA_OUI_TYPE[] ;
++extern u16 RTW_WPA_VERSION ;
++extern u8 WPA_AUTH_KEY_MGMT_NONE[];
++extern u8 WPA_AUTH_KEY_MGMT_UNSPEC_802_1X[];
++extern u8 WPA_AUTH_KEY_MGMT_PSK_OVER_802_1X[];
++extern u8 WPA_CIPHER_SUITE_NONE[];
++extern u8 WPA_CIPHER_SUITE_WEP40[];
++extern u8 WPA_CIPHER_SUITE_TKIP[];
++extern u8 WPA_CIPHER_SUITE_WRAP[];
++extern u8 WPA_CIPHER_SUITE_CCMP[];
++extern u8 WPA_CIPHER_SUITE_WEP104[];
++
++
++#define RSN_HEADER_LEN 4
++#define RSN_SELECTOR_LEN 4
++
++extern u16 RSN_VERSION_BSD;
++extern u8 RSN_AUTH_KEY_MGMT_UNSPEC_802_1X[];
++extern u8 RSN_AUTH_KEY_MGMT_PSK_OVER_802_1X[];
++extern u8 RSN_CIPHER_SUITE_NONE[];
++extern u8 RSN_CIPHER_SUITE_WEP40[];
++extern u8 RSN_CIPHER_SUITE_TKIP[];
++extern u8 RSN_CIPHER_SUITE_WRAP[];
++extern u8 RSN_CIPHER_SUITE_CCMP[];
++extern u8 RSN_CIPHER_SUITE_WEP104[];
++
++typedef enum _RATR_TABLE_MODE{
++ RATR_INX_WIRELESS_NGB = 0, // BGN 40 Mhz 2SS 1SS
++ RATR_INX_WIRELESS_NG = 1, // GN or N
++ RATR_INX_WIRELESS_NB = 2, // BGN 20 Mhz 2SS 1SS or BN
++ RATR_INX_WIRELESS_N = 3,
++ RATR_INX_WIRELESS_GB = 4,
++ RATR_INX_WIRELESS_G = 5,
++ RATR_INX_WIRELESS_B = 6,
++ RATR_INX_WIRELESS_MC = 7,
++ RATR_INX_WIRELESS_AC_N = 8,
++}RATR_TABLE_MODE, *PRATR_TABLE_MODE;
++
++enum NETWORK_TYPE
++{
++ WIRELESS_INVALID = 0,
++ //Sub-Element
++ WIRELESS_11B = BIT(0), // tx: cck only , rx: cck only, hw: cck
++ WIRELESS_11G = BIT(1), // tx: ofdm only, rx: ofdm & cck, hw: cck & ofdm
++ WIRELESS_11A = BIT(2), // tx: ofdm only, rx: ofdm only, hw: ofdm only
++ WIRELESS_11_24N = BIT(3), // tx: MCS only, rx: MCS & cck, hw: MCS & cck
++ WIRELESS_11_5N = BIT(4), // tx: MCS only, rx: MCS & ofdm, hw: ofdm only
++ //WIRELESS_AUTO = BIT(5),
++ WIRELESS_AC = BIT(6),
++
++ //Combination
++ WIRELESS_11BG = (WIRELESS_11B|WIRELESS_11G), // tx: cck & ofdm, rx: cck & ofdm & MCS, hw: cck & ofdm
++ WIRELESS_11G_24N = (WIRELESS_11G|WIRELESS_11_24N), // tx: ofdm & MCS, rx: ofdm & cck & MCS, hw: cck & ofdm
++ WIRELESS_11A_5N = (WIRELESS_11A|WIRELESS_11_5N), // tx: ofdm & MCS, rx: ofdm & MCS, hw: ofdm only
++ WIRELESS_11BG_24N = (WIRELESS_11B|WIRELESS_11G|WIRELESS_11_24N), // tx: ofdm & cck & MCS, rx: ofdm & cck & MCS, hw: ofdm & cck
++ WIRELESS_11AGN = (WIRELESS_11A|WIRELESS_11G|WIRELESS_11_24N|WIRELESS_11_5N), // tx: ofdm & MCS, rx: ofdm & MCS, hw: ofdm only
++ WIRELESS_11ABGN = (WIRELESS_11A|WIRELESS_11B|WIRELESS_11G|WIRELESS_11_24N|WIRELESS_11_5N),
++};
++
++#define SUPPORTED_24G_NETTYPE_MSK (WIRELESS_11B | WIRELESS_11G | WIRELESS_11_24N)
++#define SUPPORTED_5G_NETTYPE_MSK (WIRELESS_11A | WIRELESS_11_5N)
++
++#define IsSupported24G(NetType) ((NetType) & SUPPORTED_24G_NETTYPE_MSK ? _TRUE : _FALSE)
++#define IsSupported5G(NetType) ((NetType) & SUPPORTED_5G_NETTYPE_MSK ? _TRUE : _FALSE)
++
++#define IsEnableHWCCK(NetType) IsSupported24G(NetType)
++#define IsEnableHWOFDM(NetType) ((NetType) & (WIRELESS_11G|WIRELESS_11_24N|SUPPORTED_5G_NETTYPE_MSK) ? _TRUE : _FALSE)
++
++#define IsSupportedRxCCK(NetType) IsEnableHWCCK(NetType)
++#define IsSupportedRxOFDM(NetType) IsEnableHWOFDM(NetType)
++#define IsSupportedRxMCS(NetType) IsEnableHWOFDM(NetType)
++
++#define IsSupportedTxCCK(NetType) ((NetType) & (WIRELESS_11B) ? _TRUE : _FALSE)
++#define IsSupportedTxOFDM(NetType) ((NetType) & (WIRELESS_11G|WIRELESS_11A) ? _TRUE : _FALSE)
++#define IsSupportedTxMCS(NetType) ((NetType) & (WIRELESS_11_24N|WIRELESS_11_5N) ? _TRUE : _FALSE)
++
++
++typedef struct ieee_param {
++ u32 cmd;
++ u8 sta_addr[ETH_ALEN];
++ union {
++ struct {
++ u8 name;
++ u32 value;
++ } wpa_param;
++ struct {
++ u32 len;
++ u8 reserved[32];
++ u8 data[0];
++ } wpa_ie;
++ struct{
++ int command;
++ int reason_code;
++ } mlme;
++ struct {
++ u8 alg[IEEE_CRYPT_ALG_NAME_LEN];
++ u8 set_tx;
++ u32 err;
++ u8 idx;
++ u8 seq[8]; /* sequence counter (set: RX, get: TX) */
++ u16 key_len;
++ u8 key[0];
++ } crypt;
++#ifdef CONFIG_AP_MODE
++ struct {
++ u16 aid;
++ u16 capability;
++ int flags;
++ u8 tx_supp_rates[16];
++ struct rtw_ieee80211_ht_cap ht_cap;
++ } add_sta;
++ struct {
++ u8 reserved[2];//for set max_num_sta
++ u8 buf[0];
++ } bcn_ie;
++#endif
++
++ } u;
++}ieee_param;
++
++#ifdef CONFIG_AP_MODE
++typedef struct ieee_param_ex {
++ u32 cmd;
++ u8 sta_addr[ETH_ALEN];
++ u8 data[0];
++}ieee_param_ex;
++
++struct sta_data{
++ u16 aid;
++ u16 capability;
++ int flags;
++ u32 sta_set;
++ u8 tx_supp_rates[16];
++ u32 tx_supp_rates_len;
++ struct rtw_ieee80211_ht_cap ht_cap;
++ u64 rx_pkts;
++ u64 rx_bytes;
++ u64 rx_drops;
++ u64 tx_pkts;
++ u64 tx_bytes;
++ u64 tx_drops;
++};
++#endif
++
++
++#if WIRELESS_EXT < 17
++#define IW_QUAL_QUAL_INVALID 0x10
++#define IW_QUAL_LEVEL_INVALID 0x20
++#define IW_QUAL_NOISE_INVALID 0x40
++#define IW_QUAL_QUAL_UPDATED 0x1
++#define IW_QUAL_LEVEL_UPDATED 0x2
++#define IW_QUAL_NOISE_UPDATED 0x4
++#endif
++
++#define IEEE80211_DATA_LEN 2304
++/* Maximum size for the MA-UNITDATA primitive, 802.11 standard section
++ 6.2.1.1.2.
++
++ The figure in section 7.1.2 suggests a body size of up to 2312
++ bytes is allowed, which is a bit confusing, I suspect this
++ represents the 2304 bytes of real data, plus a possible 8 bytes of
++ WEP IV and ICV. (this interpretation suggested by Ramiro Barreiro) */
++
++
++#define IEEE80211_HLEN 30
++#define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN)
++
++
++/* this is stolen from ipw2200 driver */
++#define IEEE_IBSS_MAC_HASH_SIZE 31
++
++struct ieee_ibss_seq {
++ u8 mac[ETH_ALEN];
++ u16 seq_num;
++ u16 frag_num;
++ unsigned long packet_time;
++ _list list;
++};
++
++#if defined(PLATFORM_LINUX) || defined(CONFIG_RTL8711FW)||defined(PLATFORM_FREEBSD)
++
++struct rtw_ieee80211_hdr {
++ u16 frame_ctl;
++ u16 duration_id;
++ u8 addr1[ETH_ALEN];
++ u8 addr2[ETH_ALEN];
++ u8 addr3[ETH_ALEN];
++ u16 seq_ctl;
++ u8 addr4[ETH_ALEN];
++} __attribute__ ((packed));
++
++struct rtw_ieee80211_hdr_3addr {
++ u16 frame_ctl;
++ u16 duration_id;
++ u8 addr1[ETH_ALEN];
++ u8 addr2[ETH_ALEN];
++ u8 addr3[ETH_ALEN];
++ u16 seq_ctl;
++} __attribute__ ((packed));
++
++
++struct rtw_ieee80211_hdr_qos {
++ u16 frame_ctl;
++ u16 duration_id;
++ u8 addr1[ETH_ALEN];
++ u8 addr2[ETH_ALEN];
++ u8 addr3[ETH_ALEN];
++ u16 seq_ctl;
++ u8 addr4[ETH_ALEN];
++ u16 qc;
++} __attribute__ ((packed));
++
++struct rtw_ieee80211_hdr_3addr_qos {
++ u16 frame_ctl;
++ u16 duration_id;
++ u8 addr1[ETH_ALEN];
++ u8 addr2[ETH_ALEN];
++ u8 addr3[ETH_ALEN];
++ u16 seq_ctl;
++ u16 qc;
++} __attribute__ ((packed));
++
++struct eapol {
++ u8 snap[6];
++ u16 ethertype;
++ u8 version;
++ u8 type;
++ u16 length;
++} __attribute__ ((packed));
++
++#endif
++
++
++
++#ifdef PLATFORM_WINDOWS
++
++#pragma pack(1)
++struct rtw_ieee80211_hdr {
++ u16 frame_ctl;
++ u16 duration_id;
++ u8 addr1[ETH_ALEN];
++ u8 addr2[ETH_ALEN];
++ u8 addr3[ETH_ALEN];
++ u16 seq_ctl;
++ u8 addr4[ETH_ALEN];
++};
++
++struct rtw_ieee80211_hdr_3addr {
++ u16 frame_ctl;
++ u16 duration_id;
++ u8 addr1[ETH_ALEN];
++ u8 addr2[ETH_ALEN];
++ u8 addr3[ETH_ALEN];
++ u16 seq_ctl;
++};
++
++
++struct rtw_ieee80211_hdr_qos {
++ struct rtw_ieee80211_hdr wlan_hdr;
++ u16 qc;
++};
++
++struct rtw_ieee80211_hdr_3addr_qos {
++ struct rtw_ieee80211_hdr_3addr wlan_hdr;
++ u16 qc;
++};
++
++struct eapol {
++ u8 snap[6];
++ u16 ethertype;
++ u8 version;
++ u8 type;
++ u16 length;
++};
++#pragma pack()
++
++#endif
++
++
++
++enum eap_type {
++ EAP_PACKET = 0,
++ EAPOL_START,
++ EAPOL_LOGOFF,
++ EAPOL_KEY,
++ EAPOL_ENCAP_ASF_ALERT
++};
++
++#define IEEE80211_3ADDR_LEN 24
++#define IEEE80211_4ADDR_LEN 30
++#define IEEE80211_FCS_LEN 4
++
++#define MIN_FRAG_THRESHOLD 256U
++#define MAX_FRAG_THRESHOLD 2346U
++
++/* Frame control field constants */
++#define RTW_IEEE80211_FCTL_VERS 0x0003
++#define RTW_IEEE80211_FCTL_FTYPE 0x000c
++#define RTW_IEEE80211_FCTL_STYPE 0x00f0
++#define RTW_IEEE80211_FCTL_TODS 0x0100
++#define RTW_IEEE80211_FCTL_FROMDS 0x0200
++#define RTW_IEEE80211_FCTL_MOREFRAGS 0x0400
++#define RTW_IEEE80211_FCTL_RETRY 0x0800
++#define RTW_IEEE80211_FCTL_PM 0x1000
++#define RTW_IEEE80211_FCTL_MOREDATA 0x2000
++#define RTW_IEEE80211_FCTL_PROTECTED 0x4000
++#define RTW_IEEE80211_FCTL_ORDER 0x8000
++#define RTW_IEEE80211_FCTL_CTL_EXT 0x0f00
++
++#define RTW_IEEE80211_FTYPE_MGMT 0x0000
++#define RTW_IEEE80211_FTYPE_CTL 0x0004
++#define RTW_IEEE80211_FTYPE_DATA 0x0008
++#define RTW_IEEE80211_FTYPE_EXT 0x000c
++
++/* management */
++#define RTW_IEEE80211_STYPE_ASSOC_REQ 0x0000
++#define RTW_IEEE80211_STYPE_ASSOC_RESP 0x0010
++#define RTW_IEEE80211_STYPE_REASSOC_REQ 0x0020
++#define RTW_IEEE80211_STYPE_REASSOC_RESP 0x0030
++#define RTW_IEEE80211_STYPE_PROBE_REQ 0x0040
++#define RTW_IEEE80211_STYPE_PROBE_RESP 0x0050
++#define RTW_IEEE80211_STYPE_BEACON 0x0080
++#define RTW_IEEE80211_STYPE_ATIM 0x0090
++#define RTW_IEEE80211_STYPE_DISASSOC 0x00A0
++#define RTW_IEEE80211_STYPE_AUTH 0x00B0
++#define RTW_IEEE80211_STYPE_DEAUTH 0x00C0
++#define RTW_IEEE80211_STYPE_ACTION 0x00D0
++
++/* control */
++#define RTW_IEEE80211_STYPE_CTL_EXT 0x0060
++#define RTW_IEEE80211_STYPE_BACK_REQ 0x0080
++#define RTW_IEEE80211_STYPE_BACK 0x0090
++#define RTW_IEEE80211_STYPE_PSPOLL 0x00A0
++#define RTW_IEEE80211_STYPE_RTS 0x00B0
++#define RTW_IEEE80211_STYPE_CTS 0x00C0
++#define RTW_IEEE80211_STYPE_ACK 0x00D0
++#define RTW_IEEE80211_STYPE_CFEND 0x00E0
++#define RTW_IEEE80211_STYPE_CFENDACK 0x00F0
++
++/* data */
++#define RTW_IEEE80211_STYPE_DATA 0x0000
++#define RTW_IEEE80211_STYPE_DATA_CFACK 0x0010
++#define RTW_IEEE80211_STYPE_DATA_CFPOLL 0x0020
++#define RTW_IEEE80211_STYPE_DATA_CFACKPOLL 0x0030
++#define RTW_IEEE80211_STYPE_NULLFUNC 0x0040
++#define RTW_IEEE80211_STYPE_CFACK 0x0050
++#define RTW_IEEE80211_STYPE_CFPOLL 0x0060
++#define RTW_IEEE80211_STYPE_CFACKPOLL 0x0070
++#define RTW_IEEE80211_STYPE_QOS_DATA 0x0080
++#define RTW_IEEE80211_STYPE_QOS_DATA_CFACK 0x0090
++#define RTW_IEEE80211_STYPE_QOS_DATA_CFPOLL 0x00A0
++#define RTW_IEEE80211_STYPE_QOS_DATA_CFACKPOLL 0x00B0
++#define RTW_IEEE80211_STYPE_QOS_NULLFUNC 0x00C0
++#define RTW_IEEE80211_STYPE_QOS_CFACK 0x00D0
++#define RTW_IEEE80211_STYPE_QOS_CFPOLL 0x00E0
++#define RTW_IEEE80211_STYPE_QOS_CFACKPOLL 0x00F0
++
++/* sequence control field */
++#define RTW_IEEE80211_SCTL_FRAG 0x000F
++#define RTW_IEEE80211_SCTL_SEQ 0xFFF0
++
++
++#define RTW_ERP_INFO_NON_ERP_PRESENT BIT(0)
++#define RTW_ERP_INFO_USE_PROTECTION BIT(1)
++#define RTW_ERP_INFO_BARKER_PREAMBLE_MODE BIT(2)
++
++/* QoS,QOS */
++#define NORMAL_ACK 0
++#define NO_ACK 1
++#define NON_EXPLICIT_ACK 2
++#define BLOCK_ACK 3
++
++#ifndef ETH_P_PAE
++#define ETH_P_PAE 0x888E /* Port Access Entity (IEEE 802.1X) */
++#endif /* ETH_P_PAE */
++
++#define ETH_P_PREAUTH 0x88C7 /* IEEE 802.11i pre-authentication */
++
++#define ETH_P_ECONET 0x0018
++
++#ifndef ETH_P_80211_RAW
++#define ETH_P_80211_RAW (ETH_P_ECONET + 1)
++#endif
++
++/* IEEE 802.11 defines */
++
++#define P80211_OUI_LEN 3
++
++#if defined(PLATFORM_LINUX) || defined(CONFIG_RTL8711FW) || defined(PLATFORM_FREEBSD)
++
++struct ieee80211_snap_hdr {
++
++ u8 dsap; /* always 0xAA */
++ u8 ssap; /* always 0xAA */
++ u8 ctrl; /* always 0x03 */
++ u8 oui[P80211_OUI_LEN]; /* organizational universal id */
++
++} __attribute__ ((packed));
++
++#endif
++
++#ifdef PLATFORM_WINDOWS
++
++#pragma pack(1)
++struct ieee80211_snap_hdr {
++
++ u8 dsap; /* always 0xAA */
++ u8 ssap; /* always 0xAA */
++ u8 ctrl; /* always 0x03 */
++ u8 oui[P80211_OUI_LEN]; /* organizational universal id */
++
++};
++#pragma pack()
++
++#endif
++
++
++#define SNAP_SIZE sizeof(struct ieee80211_snap_hdr)
++
++#define WLAN_FC_GET_TYPE(fc) ((fc) & RTW_IEEE80211_FCTL_FTYPE)
++#define WLAN_FC_GET_STYPE(fc) ((fc) & RTW_IEEE80211_FCTL_STYPE)
++
++#define WLAN_QC_GET_TID(qc) ((qc) & 0x0f)
++
++#define WLAN_GET_SEQ_FRAG(seq) ((seq) & RTW_IEEE80211_SCTL_FRAG)
++#define WLAN_GET_SEQ_SEQ(seq) ((seq) & RTW_IEEE80211_SCTL_SEQ)
++
++/* Authentication algorithms */
++#define WLAN_AUTH_OPEN 0
++#define WLAN_AUTH_SHARED_KEY 1
++
++#define WLAN_AUTH_CHALLENGE_LEN 128
++
++#define WLAN_CAPABILITY_BSS (1<<0)
++#define WLAN_CAPABILITY_IBSS (1<<1)
++#define WLAN_CAPABILITY_CF_POLLABLE (1<<2)
++#define WLAN_CAPABILITY_CF_POLL_REQUEST (1<<3)
++#define WLAN_CAPABILITY_PRIVACY (1<<4)
++#define WLAN_CAPABILITY_SHORT_PREAMBLE (1<<5)
++#define WLAN_CAPABILITY_PBCC (1<<6)
++#define WLAN_CAPABILITY_CHANNEL_AGILITY (1<<7)
++#define WLAN_CAPABILITY_SHORT_SLOT (1<<10)
++
++/* Status codes */
++#define WLAN_STATUS_SUCCESS 0
++#define WLAN_STATUS_UNSPECIFIED_FAILURE 1
++#define WLAN_STATUS_CAPS_UNSUPPORTED 10
++#define WLAN_STATUS_REASSOC_NO_ASSOC 11
++#define WLAN_STATUS_ASSOC_DENIED_UNSPEC 12
++#define WLAN_STATUS_NOT_SUPPORTED_AUTH_ALG 13
++#define WLAN_STATUS_UNKNOWN_AUTH_TRANSACTION 14
++#define WLAN_STATUS_CHALLENGE_FAIL 15
++#define WLAN_STATUS_AUTH_TIMEOUT 16
++#define WLAN_STATUS_AP_UNABLE_TO_HANDLE_NEW_STA 17
++#define WLAN_STATUS_ASSOC_DENIED_RATES 18
++/* 802.11b */
++#define WLAN_STATUS_ASSOC_DENIED_NOSHORT 19
++#define WLAN_STATUS_ASSOC_DENIED_NOPBCC 20
++#define WLAN_STATUS_ASSOC_DENIED_NOAGILITY 21
++
++/* Reason codes */
++#define WLAN_REASON_UNSPECIFIED 1
++#define WLAN_REASON_PREV_AUTH_NOT_VALID 2
++#define WLAN_REASON_DEAUTH_LEAVING 3
++#define WLAN_REASON_DISASSOC_DUE_TO_INACTIVITY 4
++#define WLAN_REASON_DISASSOC_AP_BUSY 5
++#define WLAN_REASON_CLASS2_FRAME_FROM_NONAUTH_STA 6
++#define WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA 7
++#define WLAN_REASON_DISASSOC_STA_HAS_LEFT 8
++#define WLAN_REASON_STA_REQ_ASSOC_WITHOUT_AUTH 9
++#define WLAN_REASON_JOIN_WRONG_CHANNEL 65534
++#define WLAN_REASON_EXPIRATION_CHK 65535
++
++/* Information Element IDs */
++#define WLAN_EID_SSID 0
++#define WLAN_EID_SUPP_RATES 1
++#define WLAN_EID_FH_PARAMS 2
++#define WLAN_EID_DS_PARAMS 3
++#define WLAN_EID_CF_PARAMS 4
++#define WLAN_EID_TIM 5
++#define WLAN_EID_IBSS_PARAMS 6
++#define WLAN_EID_CHALLENGE 16
++/* EIDs defined by IEEE 802.11h - START */
++#define WLAN_EID_PWR_CONSTRAINT 32
++#define WLAN_EID_PWR_CAPABILITY 33
++#define WLAN_EID_TPC_REQUEST 34
++#define WLAN_EID_TPC_REPORT 35
++#define WLAN_EID_SUPPORTED_CHANNELS 36
++#define WLAN_EID_CHANNEL_SWITCH 37
++#define WLAN_EID_MEASURE_REQUEST 38
++#define WLAN_EID_MEASURE_REPORT 39
++#define WLAN_EID_QUITE 40
++#define WLAN_EID_IBSS_DFS 41
++/* EIDs defined by IEEE 802.11h - END */
++#define WLAN_EID_ERP_INFO 42
++#define WLAN_EID_HT_CAP 45
++#define WLAN_EID_RSN 48
++#define WLAN_EID_EXT_SUPP_RATES 50
++#define WLAN_EID_MOBILITY_DOMAIN 54
++#define WLAN_EID_FAST_BSS_TRANSITION 55
++#define WLAN_EID_TIMEOUT_INTERVAL 56
++#define WLAN_EID_RIC_DATA 57
++#define WLAN_EID_HT_OPERATION 61
++#define WLAN_EID_SECONDARY_CHANNEL_OFFSET 62
++#define WLAN_EID_20_40_BSS_COEXISTENCE 72
++#define WLAN_EID_20_40_BSS_INTOLERANT 73
++#define WLAN_EID_OVERLAPPING_BSS_SCAN_PARAMS 74
++#define WLAN_EID_MMIE 76
++#define WLAN_EID_VENDOR_SPECIFIC 221
++#define WLAN_EID_GENERIC (WLAN_EID_VENDOR_SPECIFIC)
++
++#define IEEE80211_MGMT_HDR_LEN 24
++#define IEEE80211_DATA_HDR3_LEN 24
++#define IEEE80211_DATA_HDR4_LEN 30
++
++
++#define IEEE80211_STATMASK_SIGNAL (1<<0)
++#define IEEE80211_STATMASK_RSSI (1<<1)
++#define IEEE80211_STATMASK_NOISE (1<<2)
++#define IEEE80211_STATMASK_RATE (1<<3)
++#define IEEE80211_STATMASK_WEMASK 0x7
++
++
++#define IEEE80211_CCK_MODULATION (1<<0)
++#define IEEE80211_OFDM_MODULATION (1<<1)
++
++#define IEEE80211_24GHZ_BAND (1<<0)
++#define IEEE80211_52GHZ_BAND (1<<1)
++
++#define IEEE80211_CCK_RATE_LEN 4
++#define IEEE80211_NUM_OFDM_RATESLEN 8
++
++
++#define IEEE80211_CCK_RATE_1MB 0x02
++#define IEEE80211_CCK_RATE_2MB 0x04
++#define IEEE80211_CCK_RATE_5MB 0x0B
++#define IEEE80211_CCK_RATE_11MB 0x16
++#define IEEE80211_OFDM_RATE_LEN 8
++#define IEEE80211_OFDM_RATE_6MB 0x0C
++#define IEEE80211_OFDM_RATE_9MB 0x12
++#define IEEE80211_OFDM_RATE_12MB 0x18
++#define IEEE80211_OFDM_RATE_18MB 0x24
++#define IEEE80211_OFDM_RATE_24MB 0x30
++#define IEEE80211_OFDM_RATE_36MB 0x48
++#define IEEE80211_OFDM_RATE_48MB 0x60
++#define IEEE80211_OFDM_RATE_54MB 0x6C
++#define IEEE80211_BASIC_RATE_MASK 0x80
++
++#define IEEE80211_CCK_RATE_1MB_MASK (1<<0)
++#define IEEE80211_CCK_RATE_2MB_MASK (1<<1)
++#define IEEE80211_CCK_RATE_5MB_MASK (1<<2)
++#define IEEE80211_CCK_RATE_11MB_MASK (1<<3)
++#define IEEE80211_OFDM_RATE_6MB_MASK (1<<4)
++#define IEEE80211_OFDM_RATE_9MB_MASK (1<<5)
++#define IEEE80211_OFDM_RATE_12MB_MASK (1<<6)
++#define IEEE80211_OFDM_RATE_18MB_MASK (1<<7)
++#define IEEE80211_OFDM_RATE_24MB_MASK (1<<8)
++#define IEEE80211_OFDM_RATE_36MB_MASK (1<<9)
++#define IEEE80211_OFDM_RATE_48MB_MASK (1<<10)
++#define IEEE80211_OFDM_RATE_54MB_MASK (1<<11)
++
++#define IEEE80211_CCK_RATES_MASK 0x0000000F
++#define IEEE80211_CCK_BASIC_RATES_MASK (IEEE80211_CCK_RATE_1MB_MASK | \
++ IEEE80211_CCK_RATE_2MB_MASK)
++#define IEEE80211_CCK_DEFAULT_RATES_MASK (IEEE80211_CCK_BASIC_RATES_MASK | \
++ IEEE80211_CCK_RATE_5MB_MASK | \
++ IEEE80211_CCK_RATE_11MB_MASK)
++
++#define IEEE80211_OFDM_RATES_MASK 0x00000FF0
++#define IEEE80211_OFDM_BASIC_RATES_MASK (IEEE80211_OFDM_RATE_6MB_MASK | \
++ IEEE80211_OFDM_RATE_12MB_MASK | \
++ IEEE80211_OFDM_RATE_24MB_MASK)
++#define IEEE80211_OFDM_DEFAULT_RATES_MASK (IEEE80211_OFDM_BASIC_RATES_MASK | \
++ IEEE80211_OFDM_RATE_9MB_MASK | \
++ IEEE80211_OFDM_RATE_18MB_MASK | \
++ IEEE80211_OFDM_RATE_36MB_MASK | \
++ IEEE80211_OFDM_RATE_48MB_MASK | \
++ IEEE80211_OFDM_RATE_54MB_MASK)
++#define IEEE80211_DEFAULT_RATES_MASK (IEEE80211_OFDM_DEFAULT_RATES_MASK | \
++ IEEE80211_CCK_DEFAULT_RATES_MASK)
++
++#define IEEE80211_NUM_OFDM_RATES 8
++#define IEEE80211_NUM_CCK_RATES 4
++#define IEEE80211_OFDM_SHIFT_MASK_A 4
++
++
++
++
++/* NOTE: This data is for statistical purposes; not all hardware provides this
++ * information for frames received. Not setting these will not cause
++ * any adverse affects. */
++struct ieee80211_rx_stats {
++ //u32 mac_time[2];
++ s8 rssi;
++ u8 signal;
++ u8 noise;
++ u8 received_channel;
++ u16 rate; /* in 100 kbps */
++ //u8 control;
++ u8 mask;
++ u8 freq;
++ u16 len;
++};
++
++/* IEEE 802.11 requires that STA supports concurrent reception of at least
++ * three fragmented frames. This define can be increased to support more
++ * concurrent frames, but it should be noted that each entry can consume about
++ * 2 kB of RAM and increasing cache size will slow down frame reassembly. */
++#define IEEE80211_FRAG_CACHE_LEN 4
++
++struct ieee80211_frag_entry {
++ u32 first_frag_time;
++ uint seq;
++ uint last_frag;
++ uint qos; //jackson
++ uint tid; //jackson
++ struct sk_buff *skb;
++ u8 src_addr[ETH_ALEN];
++ u8 dst_addr[ETH_ALEN];
++};
++
++#ifndef PLATFORM_FREEBSD //Baron BSD has already defined
++struct ieee80211_stats {
++ uint tx_unicast_frames;
++ uint tx_multicast_frames;
++ uint tx_fragments;
++ uint tx_unicast_octets;
++ uint tx_multicast_octets;
++ uint tx_deferred_transmissions;
++ uint tx_single_retry_frames;
++ uint tx_multiple_retry_frames;
++ uint tx_retry_limit_exceeded;
++ uint tx_discards;
++ uint rx_unicast_frames;
++ uint rx_multicast_frames;
++ uint rx_fragments;
++ uint rx_unicast_octets;
++ uint rx_multicast_octets;
++ uint rx_fcs_errors;
++ uint rx_discards_no_buffer;
++ uint tx_discards_wrong_sa;
++ uint rx_discards_undecryptable;
++ uint rx_message_in_msg_fragments;
++ uint rx_message_in_bad_msg_fragments;
++};
++#endif //PLATFORM_FREEBSD
++struct ieee80211_softmac_stats{
++ uint rx_ass_ok;
++ uint rx_ass_err;
++ uint rx_probe_rq;
++ uint tx_probe_rs;
++ uint tx_beacons;
++ uint rx_auth_rq;
++ uint rx_auth_rs_ok;
++ uint rx_auth_rs_err;
++ uint tx_auth_rq;
++ uint no_auth_rs;
++ uint no_ass_rs;
++ uint tx_ass_rq;
++ uint rx_ass_rq;
++ uint tx_probe_rq;
++ uint reassoc;
++ uint swtxstop;
++ uint swtxawake;
++};
++
++#define SEC_KEY_1 (1<<0)
++#define SEC_KEY_2 (1<<1)
++#define SEC_KEY_3 (1<<2)
++#define SEC_KEY_4 (1<<3)
++#define SEC_ACTIVE_KEY (1<<4)
++#define SEC_AUTH_MODE (1<<5)
++#define SEC_UNICAST_GROUP (1<<6)
++#define SEC_LEVEL (1<<7)
++#define SEC_ENABLED (1<<8)
++
++#define SEC_LEVEL_0 0 /* None */
++#define SEC_LEVEL_1 1 /* WEP 40 and 104 bit */
++#define SEC_LEVEL_2 2 /* Level 1 + TKIP */
++#define SEC_LEVEL_2_CKIP 3 /* Level 1 + CKIP */
++#define SEC_LEVEL_3 4 /* Level 2 + CCMP */
++
++#define WEP_KEYS 4
++#define WEP_KEY_LEN 13
++
++#ifdef CONFIG_IEEE80211W
++#define BIP_MAX_KEYID 5
++#define BIP_AAD_SIZE 20
++#endif //CONFIG_IEEE80211W
++
++#if defined(PLATFORM_LINUX) || defined(CONFIG_RTL8711FW)
++
++struct ieee80211_security {
++ u16 active_key:2,
++ enabled:1,
++ auth_mode:2,
++ auth_algo:4,
++ unicast_uses_group:1;
++ u8 key_sizes[WEP_KEYS];
++ u8 keys[WEP_KEYS][WEP_KEY_LEN];
++ u8 level;
++ u16 flags;
++} __attribute__ ((packed));
++
++#endif
++
++#ifdef PLATFORM_WINDOWS
++
++#pragma pack(1)
++struct ieee80211_security {
++ u16 active_key:2,
++ enabled:1,
++ auth_mode:2,
++ auth_algo:4,
++ unicast_uses_group:1;
++ u8 key_sizes[WEP_KEYS];
++ u8 keys[WEP_KEYS][WEP_KEY_LEN];
++ u8 level;
++ u16 flags;
++} ;
++#pragma pack()
++
++#endif
++
++/*
++
++ 802.11 data frame from AP
++
++ ,-------------------------------------------------------------------.
++Bytes | 2 | 2 | 6 | 6 | 6 | 2 | 0..2312 | 4 |
++ |------|------|---------|---------|---------|------|---------|------|
++Desc. | ctrl | dura | DA/RA | TA | SA | Sequ | frame | fcs |
++ | | tion | (BSSID) | | | ence | data | |
++ `-------------------------------------------------------------------'
++
++Total: 28-2340 bytes
++
++*/
++
++struct ieee80211_header_data {
++ u16 frame_ctl;
++ u16 duration_id;
++ u8 addr1[6];
++ u8 addr2[6];
++ u8 addr3[6];
++ u16 seq_ctrl;
++};
++
++#define BEACON_PROBE_SSID_ID_POSITION 12
++
++/* Management Frame Information Element Types */
++#define MFIE_TYPE_SSID 0
++#define MFIE_TYPE_RATES 1
++#define MFIE_TYPE_FH_SET 2
++#define MFIE_TYPE_DS_SET 3
++#define MFIE_TYPE_CF_SET 4
++#define MFIE_TYPE_TIM 5
++#define MFIE_TYPE_IBSS_SET 6
++#define MFIE_TYPE_CHALLENGE 16
++#define MFIE_TYPE_ERP 42
++#define MFIE_TYPE_RSN 48
++#define MFIE_TYPE_RATES_EX 50
++#define MFIE_TYPE_GENERIC 221
++
++#if defined(PLATFORM_LINUX) || defined(CONFIG_RTL8711FW)
++
++struct ieee80211_info_element_hdr {
++ u8 id;
++ u8 len;
++} __attribute__ ((packed));
++
++struct ieee80211_info_element {
++ u8 id;
++ u8 len;
++ u8 data[0];
++} __attribute__ ((packed));
++#endif
++
++#ifdef PLATFORM_WINDOWS
++
++#pragma pack(1)
++struct ieee80211_info_element_hdr {
++ u8 id;
++ u8 len;
++} ;
++
++struct ieee80211_info_element {
++ u8 id;
++ u8 len;
++ u8 data[0];
++} ;
++#pragma pack()
++
++#endif
++
++
++/*
++ * These are the data types that can make up management packets
++ *
++ u16 auth_algorithm;
++ u16 auth_sequence;
++ u16 beacon_interval;
++ u16 capability;
++ u8 current_ap[ETH_ALEN];
++ u16 listen_interval;
++ struct {
++ u16 association_id:14, reserved:2;
++ } __attribute__ ((packed));
++ u32 time_stamp[2];
++ u16 reason;
++ u16 status;
++*/
++
++#define IEEE80211_DEFAULT_TX_ESSID "Penguin"
++#define IEEE80211_DEFAULT_BASIC_RATE 10
++
++
++#if defined(PLATFORM_LINUX) || defined(CONFIG_RTL8711FW)
++
++
++struct ieee80211_authentication {
++ struct ieee80211_header_data header;
++ u16 algorithm;
++ u16 transaction;
++ u16 status;
++ //struct ieee80211_info_element_hdr info_element;
++} __attribute__ ((packed));
++
++
++struct ieee80211_probe_response {
++ struct ieee80211_header_data header;
++ u32 time_stamp[2];
++ u16 beacon_interval;
++ u16 capability;
++ struct ieee80211_info_element info_element;
++} __attribute__ ((packed));
++
++struct ieee80211_probe_request {
++ struct ieee80211_header_data header;
++ /*struct ieee80211_info_element info_element;*/
++} __attribute__ ((packed));
++
++struct ieee80211_assoc_request_frame {
++ struct rtw_ieee80211_hdr_3addr header;
++ u16 capability;
++ u16 listen_interval;
++ //u8 current_ap[ETH_ALEN];
++ struct ieee80211_info_element_hdr info_element;
++} __attribute__ ((packed));
++
++struct ieee80211_assoc_response_frame {
++ struct rtw_ieee80211_hdr_3addr header;
++ u16 capability;
++ u16 status;
++ u16 aid;
++// struct ieee80211_info_element info_element; /* supported rates */
++} __attribute__ ((packed));
++#endif
++
++
++
++#ifdef PLATFORM_WINDOWS
++
++#pragma pack(1)
++
++struct ieee80211_authentication {
++ struct ieee80211_header_data header;
++ u16 algorithm;
++ u16 transaction;
++ u16 status;
++ //struct ieee80211_info_element_hdr info_element;
++} ;
++
++
++struct ieee80211_probe_response {
++ struct ieee80211_header_data header;
++ u32 time_stamp[2];
++ u16 beacon_interval;
++ u16 capability;
++ struct ieee80211_info_element info_element;
++} ;
++
++struct ieee80211_probe_request {
++ struct ieee80211_header_data header;
++ /*struct ieee80211_info_element info_element;*/
++} ;
++
++struct ieee80211_assoc_request_frame {
++ struct rtw_ieee80211_hdr_3addr header;
++ u16 capability;
++ u16 listen_interval;
++ //u8 current_ap[ETH_ALEN];
++ struct ieee80211_info_element_hdr info_element;
++} ;
++
++struct ieee80211_assoc_response_frame {
++ struct rtw_ieee80211_hdr_3addr header;
++ u16 capability;
++ u16 status;
++ u16 aid;
++// struct ieee80211_info_element info_element; /* supported rates */
++};
++
++#pragma pack()
++
++#endif
++
++
++
++
++struct ieee80211_txb {
++ u8 nr_frags;
++ u8 encrypted;
++ u16 reserved;
++ u16 frag_size;
++ u16 payload_size;
++ struct sk_buff *fragments[0];
++};
++
++
++/* SWEEP TABLE ENTRIES NUMBER*/
++#define MAX_SWEEP_TAB_ENTRIES 42
++#define MAX_SWEEP_TAB_ENTRIES_PER_PACKET 7
++/* MAX_RATES_LENGTH needs to be 12. The spec says 8, and many APs
++ * only use 8, and then use extended rates for the remaining supported
++ * rates. Other APs, however, stick all of their supported rates on the
++ * main rates information element... */
++#define MAX_RATES_LENGTH ((u8)12)
++#define MAX_RATES_EX_LENGTH ((u8)16)
++#define MAX_NETWORK_COUNT 128
++#define MAX_CHANNEL_NUMBER 161
++#define IEEE80211_SOFTMAC_SCAN_TIME 400
++//(HZ / 2)
++#define IEEE80211_SOFTMAC_ASSOC_RETRY_TIME (HZ * 2)
++
++#define CRC_LENGTH 4U
++
++#define MAX_WPA_IE_LEN (256)
++#define MAX_WPS_IE_LEN (512)
++#define MAX_P2P_IE_LEN (256)
++#define MAX_WFD_IE_LEN (128)
++
++#define NETWORK_EMPTY_ESSID (1<<0)
++#define NETWORK_HAS_OFDM (1<<1)
++#define NETWORK_HAS_CCK (1<<2)
++
++#define IEEE80211_DTIM_MBCAST 4
++#define IEEE80211_DTIM_UCAST 2
++#define IEEE80211_DTIM_VALID 1
++#define IEEE80211_DTIM_INVALID 0
++
++#define IEEE80211_PS_DISABLED 0
++#define IEEE80211_PS_UNICAST IEEE80211_DTIM_UCAST
++#define IEEE80211_PS_MBCAST IEEE80211_DTIM_MBCAST
++#define IW_ESSID_MAX_SIZE 32
++#if 0
++struct ieee80211_network {
++ /* These entries are used to identify a unique network */
++ u8 bssid[ETH_ALEN];
++ u8 channel;
++ /* Ensure null-terminated for any debug msgs */
++ u8 ssid[IW_ESSID_MAX_SIZE + 1];
++ u8 ssid_len;
++ u8 rssi; //relative signal strength
++ u8 sq; //signal quality
++
++ /* These are network statistics */
++ //struct ieee80211_rx_stats stats;
++ u16 capability;
++ u16 aid;
++ u8 rates[MAX_RATES_LENGTH];
++ u8 rates_len;
++ u8 rates_ex[MAX_RATES_EX_LENGTH];
++ u8 rates_ex_len;
++
++ u8 edca_parmsets[18];
++
++ u8 mode;
++ u8 flags;
++ u8 time_stamp[8];
++ u16 beacon_interval;
++ u16 listen_interval;
++ u16 atim_window;
++ u8 wpa_ie[MAX_WPA_IE_LEN];
++ size_t wpa_ie_len;
++ u8 rsn_ie[MAX_WPA_IE_LEN];
++ size_t rsn_ie_len;
++ u8 country[6];
++ u8 dtim_period;
++ u8 dtim_data;
++ u8 power_constraint;
++ u8 qosinfo;
++ u8 qbssload[5];
++ u8 network_type;
++ int join_res;
++ unsigned long last_scanned;
++};
++#endif
++/*
++join_res:
++-1: authentication fail
++-2: association fail
++> 0: TID
++*/
++
++#ifndef PLATFORM_FREEBSD //Baron BSD has already defined
++
++enum ieee80211_state {
++
++ /* the card is not linked at all */
++ IEEE80211_NOLINK = 0,
++
++ /* IEEE80211_ASSOCIATING* are for BSS client mode
++ * the driver shall not perform RX filtering unless
++ * the state is LINKED.
++ * The driver shall just check for the state LINKED and
++ * defaults to NOLINK for ALL the other states (including
++ * LINKED_SCANNING)
++ */
++
++ /* the association procedure will start (wq scheduling)*/
++ IEEE80211_ASSOCIATING,
++ IEEE80211_ASSOCIATING_RETRY,
++
++ /* the association procedure is sending AUTH request*/
++ IEEE80211_ASSOCIATING_AUTHENTICATING,
++
++ /* the association procedure has successfully authentcated
++ * and is sending association request
++ */
++ IEEE80211_ASSOCIATING_AUTHENTICATED,
++
++ /* the link is ok. the card associated to a BSS or linked
++ * to a ibss cell or acting as an AP and creating the bss
++ */
++ IEEE80211_LINKED,
++
++ /* same as LINKED, but the driver shall apply RX filter
++ * rules as we are in NO_LINK mode. As the card is still
++ * logically linked, but it is doing a syncro site survey
++ * then it will be back to LINKED state.
++ */
++ IEEE80211_LINKED_SCANNING,
++
++};
++#endif //PLATFORM_FREEBSD
++
++#define DEFAULT_MAX_SCAN_AGE (15 * HZ)
++#define DEFAULT_FTS 2346
++#define MAC_FMT "%02x:%02x:%02x:%02x:%02x:%02x"
++#define MAC_ARG(x) ((u8*)(x))[0],((u8*)(x))[1],((u8*)(x))[2],((u8*)(x))[3],((u8*)(x))[4],((u8*)(x))[5]
++
++#ifdef PLATFORM_FREEBSD //Baron change func to macro
++#define is_multicast_mac_addr(Addr) ((((Addr[0]) & 0x01) == 0x01) && ((Addr[0]) != 0xff))
++#define is_broadcast_mac_addr(Addr) ((((Addr[0]) & 0xff) == 0xff) && (((Addr[1]) & 0xff) == 0xff) && \
++(((Addr[2]) & 0xff) == 0xff) && (((Addr[3]) & 0xff) == 0xff) && (((Addr[4]) & 0xff) == 0xff) && \
++(((Addr[5]) & 0xff) == 0xff))
++#else
++extern __inline int is_multicast_mac_addr(const u8 *addr)
++{
++ return ((addr[0] != 0xff) && (0x01 & addr[0]));
++}
++
++extern __inline int is_broadcast_mac_addr(const u8 *addr)
++{
++ return ((addr[0] == 0xff) && (addr[1] == 0xff) && (addr[2] == 0xff) && \
++ (addr[3] == 0xff) && (addr[4] == 0xff) && (addr[5] == 0xff));
++}
++
++extern __inline int is_zero_mac_addr(const u8 *addr)
++{
++ return ((addr[0] == 0x00) && (addr[1] == 0x00) && (addr[2] == 0x00) && \
++ (addr[3] == 0x00) && (addr[4] == 0x00) && (addr[5] == 0x00));
++}
++#endif //PLATFORM_FREEBSD
++
++#define CFG_IEEE80211_RESERVE_FCS (1<<0)
++#define CFG_IEEE80211_COMPUTE_FCS (1<<1)
++
++typedef struct tx_pending_t{
++ int frag;
++ struct ieee80211_txb *txb;
++}tx_pending_t;
++
++
++
++#define MAXTID 16
++
++#define IEEE_A (1<<0)
++#define IEEE_B (1<<1)
++#define IEEE_G (1<<2)
++#define IEEE_MODE_MASK (IEEE_A|IEEE_B|IEEE_G)
++
++//Baron move to ieee80211.c
++int ieee80211_is_empty_essid(const char *essid, int essid_len);
++int ieee80211_get_hdrlen(u16 fc);
++
++#if 0
++/* Action frame categories (IEEE 802.11-2007, 7.3.1.11, Table 7-24) */
++#define WLAN_ACTION_SPECTRUM_MGMT 0
++#define WLAN_ACTION_QOS 1
++#define WLAN_ACTION_DLS 2
++#define WLAN_ACTION_BLOCK_ACK 3
++#define WLAN_ACTION_RADIO_MEASUREMENT 5
++#define WLAN_ACTION_FT 6
++#define WLAN_ACTION_SA_QUERY 8
++#define WLAN_ACTION_WMM 17
++#endif
++
++
++/* Action category code */
++enum rtw_ieee80211_category {
++ RTW_WLAN_CATEGORY_SPECTRUM_MGMT = 0,
++ RTW_WLAN_CATEGORY_QOS = 1,
++ RTW_WLAN_CATEGORY_DLS = 2,
++ RTW_WLAN_CATEGORY_BACK = 3,
++ RTW_WLAN_CATEGORY_PUBLIC = 4, //IEEE 802.11 public action frames
++ RTW_WLAN_CATEGORY_RADIO_MEASUREMENT = 5,
++ RTW_WLAN_CATEGORY_FT = 6,
++ RTW_WLAN_CATEGORY_HT = 7,
++ RTW_WLAN_CATEGORY_SA_QUERY = 8,
++ RTW_WLAN_CATEGORY_UNPROTECTED_WNM = 11, // add for CONFIG_IEEE80211W, none 11w also can use
++ RTW_WLAN_CATEGORY_TDLS = 12,
++ RTW_WLAN_CATEGORY_SELF_PROTECTED = 15, // add for CONFIG_IEEE80211W, none 11w also can use
++ RTW_WLAN_CATEGORY_WMM = 17,
++ RTW_WLAN_CATEGORY_P2P = 0x7f,//P2P action frames
++};
++
++/* SPECTRUM_MGMT action code */
++enum rtw_ieee80211_spectrum_mgmt_actioncode {
++ RTW_WLAN_ACTION_SPCT_MSR_REQ = 0,
++ RTW_WLAN_ACTION_SPCT_MSR_RPRT = 1,
++ RTW_WLAN_ACTION_SPCT_TPC_REQ = 2,
++ RTW_WLAN_ACTION_SPCT_TPC_RPRT = 3,
++ RTW_WLAN_ACTION_SPCT_CHL_SWITCH = 4,
++ RTW_WLAN_ACTION_SPCT_EXT_CHL_SWITCH = 5,
++};
++
++enum _PUBLIC_ACTION{
++ ACT_PUBLIC_BSSCOEXIST = 0, // 20/40 BSS Coexistence
++ ACT_PUBLIC_DSE_ENABLE = 1,
++ ACT_PUBLIC_DSE_DEENABLE = 2,
++ ACT_PUBLIC_DSE_REG_LOCATION = 3,
++ ACT_PUBLIC_EXT_CHL_SWITCH = 4,
++ ACT_PUBLIC_DSE_MSR_REQ = 5,
++ ACT_PUBLIC_DSE_MSR_RPRT = 6,
++ ACT_PUBLIC_MP = 7, // Measurement Pilot
++ ACT_PUBLIC_DSE_PWR_CONSTRAINT = 8,
++ ACT_PUBLIC_VENDOR = 9, // for WIFI_DIRECT
++ ACT_PUBLIC_GAS_INITIAL_REQ = 10,
++ ACT_PUBLIC_GAS_INITIAL_RSP = 11,
++ ACT_PUBLIC_GAS_COMEBACK_REQ = 12,
++ ACT_PUBLIC_GAS_COMEBACK_RSP = 13,
++ ACT_PUBLIC_TDLS_DISCOVERY_RSP = 14,
++ ACT_PUBLIC_LOCATION_TRACK = 15,
++ ACT_PUBLIC_MAX
++};
++
++#ifdef CONFIG_TDLS
++enum TDLS_ACTION_FIELD{
++ TDLS_SETUP_REQUEST = 0,
++ TDLS_SETUP_RESPONSE = 1,
++ TDLS_SETUP_CONFIRM = 2,
++ TDLS_TEARDOWN = 3,
++ TDLS_PEER_TRAFFIC_INDICATION = 4,
++ TDLS_CHANNEL_SWITCH_REQUEST = 5,
++ TDLS_CHANNEL_SWITCH_RESPONSE = 6,
++ TDLS_PEER_PSM_REQUEST = 7,
++ TDLS_PEER_PSM_RESPONSE = 8,
++ TDLS_PEER_TRAFFIC_RESPONSE = 9,
++ TDLS_DISCOVERY_REQUEST = 10,
++ TDLS_DISCOVERY_RESPONSE = 14, //it's used in public action frame
++};
++
++#define TUNNELED_PROBE_REQ 15
++#define TUNNELED_PROBE_RSP 16
++#endif //CONFIG_TDLS
++
++/* BACK action code */
++enum rtw_ieee80211_back_actioncode {
++ RTW_WLAN_ACTION_ADDBA_REQ = 0,
++ RTW_WLAN_ACTION_ADDBA_RESP = 1,
++ RTW_WLAN_ACTION_DELBA = 2,
++};
++
++/* HT features action code */
++enum rtw_ieee80211_ht_actioncode {
++ RTW_WLAN_ACTION_NOTIFY_CH_WIDTH = 0,
++ RTW_WLAN_ACTION_SM_PS = 1,
++ RTW_WLAN_ACTION_PSPM = 2,
++ RTW_WLAN_ACTION_PCO_PHASE = 3,
++ RTW_WLAN_ACTION_MIMO_CSI_MX = 4,
++ RTW_WLAN_ACTION_MIMO_NONCP_BF = 5,
++ RTW_WLAN_ACTION_MIMP_CP_BF = 6,
++ RTW_WLAN_ACTION_ASEL_INDICATES_FB = 7,
++ RTW_WLAN_ACTION_HI_INFO_EXCHG = 8,
++};
++
++/* BACK (block-ack) parties */
++enum rtw_ieee80211_back_parties {
++ RTW_WLAN_BACK_RECIPIENT = 0,
++ RTW_WLAN_BACK_INITIATOR = 1,
++ RTW_WLAN_BACK_TIMER = 2,
++};
++
++
++#define OUI_MICROSOFT 0x0050f2 /* Microsoft (also used in Wi-Fi specs)
++ * 00:50:F2 */
++#ifndef PLATFORM_FREEBSD //Baron BSD has defined
++#define WME_OUI_TYPE 2
++#endif //PLATFORM_FREEBSD
++#define WME_OUI_SUBTYPE_INFORMATION_ELEMENT 0
++#define WME_OUI_SUBTYPE_PARAMETER_ELEMENT 1
++#define WME_OUI_SUBTYPE_TSPEC_ELEMENT 2
++#define WME_VERSION 1
++
++#define WME_ACTION_CODE_SETUP_REQUEST 0
++#define WME_ACTION_CODE_SETUP_RESPONSE 1
++#define WME_ACTION_CODE_TEARDOWN 2
++
++#define WME_SETUP_RESPONSE_STATUS_ADMISSION_ACCEPTED 0
++#define WME_SETUP_RESPONSE_STATUS_INVALID_PARAMETERS 1
++#define WME_SETUP_RESPONSE_STATUS_REFUSED 3
++
++#define WME_TSPEC_DIRECTION_UPLINK 0
++#define WME_TSPEC_DIRECTION_DOWNLINK 1
++#define WME_TSPEC_DIRECTION_BI_DIRECTIONAL 3
++
++
++#define OUI_BROADCOM 0x00904c /* Broadcom (Epigram) */
++
++#define VENDOR_HT_CAPAB_OUI_TYPE 0x33 /* 00-90-4c:0x33 */
++
++/**
++ * enum rtw_ieee80211_channel_flags - channel flags
++ *
++ * Channel flags set by the regulatory control code.
++ *
++ * @RTW_IEEE80211_CHAN_DISABLED: This channel is disabled.
++ * @RTW_IEEE80211_CHAN_PASSIVE_SCAN: Only passive scanning is permitted
++ * on this channel.
++ * @RTW_IEEE80211_CHAN_NO_IBSS: IBSS is not allowed on this channel.
++ * @RTW_IEEE80211_CHAN_RADAR: Radar detection is required on this channel.
++ * @RTW_IEEE80211_CHAN_NO_HT40PLUS: extension channel above this channel
++ * is not permitted.
++ * @RTW_IEEE80211_CHAN_NO_HT40MINUS: extension channel below this channel
++ * is not permitted.
++ */
++ enum rtw_ieee80211_channel_flags {
++ RTW_IEEE80211_CHAN_DISABLED = 1<<0,
++ RTW_IEEE80211_CHAN_PASSIVE_SCAN = 1<<1,
++ RTW_IEEE80211_CHAN_NO_IBSS = 1<<2,
++ RTW_IEEE80211_CHAN_RADAR = 1<<3,
++ RTW_IEEE80211_CHAN_NO_HT40PLUS = 1<<4,
++ RTW_IEEE80211_CHAN_NO_HT40MINUS = 1<<5,
++ };
++
++ #define RTW_IEEE80211_CHAN_NO_HT40 \
++ (RTW_IEEE80211_CHAN_NO_HT40PLUS | RTW_IEEE80211_CHAN_NO_HT40MINUS)
++
++/* Represent channel details, subset of ieee80211_channel */
++struct rtw_ieee80211_channel {
++ //enum ieee80211_band band;
++ //u16 center_freq;
++ u16 hw_value;
++ u32 flags;
++ //int max_antenna_gain;
++ //int max_power;
++ //int max_reg_power;
++ //bool beacon_found;
++ //u32 orig_flags;
++ //int orig_mag;
++ //int orig_mpwr;
++};
++
++#define CHAN_FMT \
++ /*"band:%d, "*/ \
++ /*"center_freq:%u, "*/ \
++ "hw_value:%u, " \
++ "flags:0x%08x" \
++ /*"max_antenna_gain:%d\n"*/ \
++ /*"max_power:%d\n"*/ \
++ /*"max_reg_power:%d\n"*/ \
++ /*"beacon_found:%u\n"*/ \
++ /*"orig_flags:0x%08x\n"*/ \
++ /*"orig_mag:%d\n"*/ \
++ /*"orig_mpwr:%d\n"*/
++
++#define CHAN_ARG(channel) \
++ /*(channel)->band*/ \
++ /*, (channel)->center_freq*/ \
++ (channel)->hw_value \
++ , (channel)->flags \
++ /*, (channel)->max_antenna_gain*/ \
++ /*, (channel)->max_power*/ \
++ /*, (channel)->max_reg_power*/ \
++ /*, (channel)->beacon_found*/ \
++ /*, (channel)->orig_flags*/ \
++ /*, (channel)->orig_mag*/ \
++ /*, (channel)->orig_mpwr*/ \
++
++/* Parsed Information Elements */
++struct rtw_ieee802_11_elems {
++ u8 *ssid;
++ u8 ssid_len;
++ u8 *supp_rates;
++ u8 supp_rates_len;
++ u8 *fh_params;
++ u8 fh_params_len;
++ u8 *ds_params;
++ u8 ds_params_len;
++ u8 *cf_params;
++ u8 cf_params_len;
++ u8 *tim;
++ u8 tim_len;
++ u8 *ibss_params;
++ u8 ibss_params_len;
++ u8 *challenge;
++ u8 challenge_len;
++ u8 *erp_info;
++ u8 erp_info_len;
++ u8 *ext_supp_rates;
++ u8 ext_supp_rates_len;
++ u8 *wpa_ie;
++ u8 wpa_ie_len;
++ u8 *rsn_ie;
++ u8 rsn_ie_len;
++ u8 *wme;
++ u8 wme_len;
++ u8 *wme_tspec;
++ u8 wme_tspec_len;
++ u8 *wps_ie;
++ u8 wps_ie_len;
++ u8 *power_cap;
++ u8 power_cap_len;
++ u8 *supp_channels;
++ u8 supp_channels_len;
++ u8 *mdie;
++ u8 mdie_len;
++ u8 *ftie;
++ u8 ftie_len;
++ u8 *timeout_int;
++ u8 timeout_int_len;
++ u8 *ht_capabilities;
++ u8 ht_capabilities_len;
++ u8 *ht_operation;
++ u8 ht_operation_len;
++ u8 *vendor_ht_cap;
++ u8 vendor_ht_cap_len;
++};
++
++typedef enum { ParseOK = 0, ParseUnknown = 1, ParseFailed = -1 } ParseRes;
++
++ParseRes rtw_ieee802_11_parse_elems(u8 *start, uint len,
++ struct rtw_ieee802_11_elems *elems,
++ int show_errors);
++
++u8 *rtw_set_fixed_ie(unsigned char *pbuf, unsigned int len, unsigned char *source, unsigned int *frlen);
++u8 *rtw_set_ie(u8 *pbuf, sint index, uint len, u8 *source, uint *frlen);
++
++enum secondary_ch_offset {
++ SCN = 0, /* no secondary channel */
++ SCA = 1, /* secondary channel above */
++ SCB = 3, /* secondary channel below */
++};
++u8 secondary_ch_offset_to_hal_ch_offset(u8 ch_offset);
++u8 hal_ch_offset_to_secondary_ch_offset(u8 ch_offset);
++u8 *rtw_set_ie_ch_switch(u8 *buf, u32 *buf_len, u8 ch_switch_mode, u8 new_ch, u8 ch_switch_cnt);
++u8 *rtw_set_ie_secondary_ch_offset(u8 *buf, u32 *buf_len, u8 secondary_ch_offset);
++u8 *rtw_set_ie_mesh_ch_switch_parm(u8 *buf, u32 *buf_len, u8 ttl, u8 flags, u16 reason, u16 precedence);
++
++u8 *rtw_get_ie(u8*pbuf, sint index, sint *len, sint limit);
++u8 *rtw_get_ie_ex(u8 *in_ie, uint in_len, u8 eid, u8 *oui, u8 oui_len, u8 *ie, uint *ielen);
++int rtw_ies_remove_ie(u8 *ies, uint *ies_len, uint offset, u8 eid, u8 *oui, u8 oui_len);
++
++void rtw_set_supported_rate(u8* SupportedRates, uint mode) ;
++
++unsigned char *rtw_get_wpa_ie(unsigned char *pie, int *wpa_ie_len, int limit);
++unsigned char *rtw_get_wpa2_ie(unsigned char *pie, int *rsn_ie_len, int limit);
++int rtw_get_wpa_cipher_suite(u8 *s);
++int rtw_get_wpa2_cipher_suite(u8 *s);
++int rtw_parse_wpa_ie(u8* wpa_ie, int wpa_ie_len, int *group_cipher, int *pairwise_cipher);
++int rtw_parse_wpa2_ie(u8* wpa_ie, int wpa_ie_len, int *group_cipher, int *pairwise_cipher);
++
++int rtw_get_sec_ie(u8 *in_ie,uint in_len,u8 *rsn_ie,u16 *rsn_len,u8 *wpa_ie,u16 *wpa_len);
++
++u8 rtw_is_wps_ie(u8 *ie_ptr, uint *wps_ielen);
++u8 *rtw_get_wps_ie(u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen);
++u8 *rtw_get_wps_attr(u8 *wps_ie, uint wps_ielen, u16 target_attr_id ,u8 *buf_attr, u32 *len_attr);
++u8 *rtw_get_wps_attr_content(u8 *wps_ie, uint wps_ielen, u16 target_attr_id ,u8 *buf_content, uint *len_content);
++
++/**
++ * for_each_ie - iterate over continuous IEs
++ * @ie:
++ * @buf:
++ * @buf_len:
++ */
++#define for_each_ie(ie, buf, buf_len) \
++ for (ie = (void*)buf; (((u8*)ie) - ((u8*)buf) + 1) < buf_len; ie = (void*)(((u8*)ie) + *(((u8*)ie)+1) + 2))
++
++void dump_ies(u8 *buf, u32 buf_len);
++void dump_wps_ie(u8 *ie, u32 ie_len);
++
++#ifdef CONFIG_P2P
++u32 rtw_get_p2p_merged_ies_len(u8 *in_ie, u32 in_len);
++int rtw_p2p_merge_ies(u8 *in_ie, u32 in_len, u8 *merge_ie);
++void dump_p2p_ie(u8 *ie, u32 ie_len);
++u8 *rtw_get_p2p_ie(u8 *in_ie, int in_len, u8 *p2p_ie, uint *p2p_ielen);
++u8 *rtw_get_p2p_attr(u8 *p2p_ie, uint p2p_ielen, u8 target_attr_id ,u8 *buf_attr, u32 *len_attr);
++u8 *rtw_get_p2p_attr_content(u8 *p2p_ie, uint p2p_ielen, u8 target_attr_id ,u8 *buf_content, uint *len_content);
++u32 rtw_set_p2p_attr_content(u8 *pbuf, u8 attr_id, u16 attr_len, u8 *pdata_attr);
++void rtw_WLAN_BSSID_EX_remove_p2p_attr(WLAN_BSSID_EX *bss_ex, u8 attr_id);
++#endif
++
++#ifdef CONFIG_WFD
++int rtw_get_wfd_ie(u8 *in_ie, int in_len, u8 *wfd_ie, uint *wfd_ielen);
++int rtw_get_wfd_attr_content(u8 *wfd_ie, uint wfd_ielen, u8 target_attr_id ,u8 *attr_content, uint *attr_contentlen);
++#endif // CONFIG_WFD
++
++uint rtw_get_rateset_len(u8 *rateset);
++
++struct registry_priv;
++int rtw_generate_ie(struct registry_priv *pregistrypriv);
++
++
++int rtw_get_bit_value_from_ieee_value(u8 val);
++
++uint rtw_is_cckrates_included(u8 *rate);
++
++uint rtw_is_cckratesonly_included(u8 *rate);
++
++int rtw_check_network_type(unsigned char *rate, int ratelen, int channel);
++
++void rtw_macaddr_cfg(u8 *mac_addr);
++
++u16 rtw_mcs_rate(u8 rf_type, u8 bw_40MHz, u8 short_GI_20, u8 short_GI_40, unsigned char * MCS_rate);
++
++int rtw_action_frame_parse(const u8 *frame, u32 frame_len, u8* category, u8 *action);
++const char *action_public_str(u8 action);
++
++#endif /* IEEE80211_H */
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/if_ether.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/if_ether.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/if_ether.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/if_ether.h 2015-07-28 01:20:58.317611539 +0200
+@@ -0,0 +1,112 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++
++#ifndef _LINUX_IF_ETHER_H
++#define _LINUX_IF_ETHER_H
++
++/*
++ * IEEE 802.3 Ethernet magic constants. The frame sizes omit the preamble
++ * and FCS/CRC (frame check sequence).
++ */
++
++#define ETH_ALEN 6 /* Octets in one ethernet addr */
++#define ETH_HLEN 14 /* Total octets in header. */
++#define ETH_ZLEN 60 /* Min. octets in frame sans FCS */
++#define ETH_DATA_LEN 1500 /* Max. octets in payload */
++#define ETH_FRAME_LEN 1514 /* Max. octets in frame sans FCS */
++
++/*
++ * These are the defined Ethernet Protocol ID's.
++ */
++
++#define ETH_P_LOOP 0x0060 /* Ethernet Loopback packet */
++#define ETH_P_PUP 0x0200 /* Xerox PUP packet */
++#define ETH_P_PUPAT 0x0201 /* Xerox PUP Addr Trans packet */
++#define ETH_P_IP 0x0800 /* Internet Protocol packet */
++#define ETH_P_X25 0x0805 /* CCITT X.25 */
++#define ETH_P_ARP 0x0806 /* Address Resolution packet */
++#define ETH_P_BPQ 0x08FF /* G8BPQ AX.25 Ethernet Packet [ NOT AN OFFICIALLY REGISTERED ID ] */
++#define ETH_P_IEEEPUP 0x0a00 /* Xerox IEEE802.3 PUP packet */
++#define ETH_P_IEEEPUPAT 0x0a01 /* Xerox IEEE802.3 PUP Addr Trans packet */
++#define ETH_P_DEC 0x6000 /* DEC Assigned proto */
++#define ETH_P_DNA_DL 0x6001 /* DEC DNA Dump/Load */
++#define ETH_P_DNA_RC 0x6002 /* DEC DNA Remote Console */
++#define ETH_P_DNA_RT 0x6003 /* DEC DNA Routing */
++#define ETH_P_LAT 0x6004 /* DEC LAT */
++#define ETH_P_DIAG 0x6005 /* DEC Diagnostics */
++#define ETH_P_CUST 0x6006 /* DEC Customer use */
++#define ETH_P_SCA 0x6007 /* DEC Systems Comms Arch */
++#define ETH_P_RARP 0x8035 /* Reverse Addr Res packet */
++#define ETH_P_ATALK 0x809B /* Appletalk DDP */
++#define ETH_P_AARP 0x80F3 /* Appletalk AARP */
++#define ETH_P_8021Q 0x8100 /* 802.1Q VLAN Extended Header */
++#define ETH_P_IPX 0x8137 /* IPX over DIX */
++#define ETH_P_IPV6 0x86DD /* IPv6 over bluebook */
++#define ETH_P_PPP_DISC 0x8863 /* PPPoE discovery messages */
++#define ETH_P_PPP_SES 0x8864 /* PPPoE session messages */
++#define ETH_P_ATMMPOA 0x884c /* MultiProtocol Over ATM */
++#define ETH_P_ATMFATE 0x8884 /* Frame-based ATM Transport
++ * over Ethernet
++ */
++
++/*
++ * Non DIX types. Won't clash for 1500 types.
++ */
++
++#define ETH_P_802_3 0x0001 /* Dummy type for 802.3 frames */
++#define ETH_P_AX25 0x0002 /* Dummy protocol id for AX.25 */
++#define ETH_P_ALL 0x0003 /* Every packet (be careful!!!) */
++#define ETH_P_802_2 0x0004 /* 802.2 frames */
++#define ETH_P_SNAP 0x0005 /* Internal only */
++#define ETH_P_DDCMP 0x0006 /* DEC DDCMP: Internal only */
++#define ETH_P_WAN_PPP 0x0007 /* Dummy type for WAN PPP frames*/
++#define ETH_P_PPP_MP 0x0008 /* Dummy type for PPP MP frames */
++#define ETH_P_LOCALTALK 0x0009 /* Localtalk pseudo type */
++#define ETH_P_PPPTALK 0x0010 /* Dummy type for Atalk over PPP*/
++#define ETH_P_TR_802_2 0x0011 /* 802.2 frames */
++#define ETH_P_MOBITEX 0x0015 /* Mobitex (kaz@cafe.net) */
++#define ETH_P_CONTROL 0x0016 /* Card specific control frames */
++#define ETH_P_IRDA 0x0017 /* Linux-IrDA */
++#define ETH_P_ECONET 0x0018 /* Acorn Econet */
++
++/*
++ * This is an Ethernet frame header.
++ */
++
++struct ethhdr
++{
++ unsigned char h_dest[ETH_ALEN]; /* destination eth addr */
++ unsigned char h_source[ETH_ALEN]; /* source ether addr */
++ unsigned short h_proto; /* packet type ID field */
++};
++
++struct _vlan {
++ unsigned short h_vlan_TCI; // Encapsulates priority and VLAN ID
++ unsigned short h_vlan_encapsulated_proto;
++};
++
++
++
++#define get_vlan_id(pvlan) ((ntohs((unsigned short )pvlan->h_vlan_TCI)) & 0xfff)
++#define get_vlan_priority(pvlan) ((ntohs((unsigned short )pvlan->h_vlan_TCI))>>13)
++#define get_vlan_encap_proto(pvlan) (ntohs((unsigned short )pvlan->h_vlan_encapsulated_proto))
++
++
++#endif /* _LINUX_IF_ETHER_H */
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/ioctl_cfg80211.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/ioctl_cfg80211.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/ioctl_cfg80211.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/ioctl_cfg80211.h 2015-07-28 01:20:58.317611539 +0200
+@@ -0,0 +1,179 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef __IOCTL_CFG80211_H__
++#define __IOCTL_CFG80211_H__
++
++#if defined(CONFIG_IOCTL_CFG80211) && !defined(CONFIG_CFG80211) && !defined(CONFIG_CFG80211_MODULE)
++ #error "Can't define CONFIG_IOCTL_CFG80211 because neither CONFIG_CFG80211 nor CONFIG_CFG80211_MODULE is defined in kernel"
++#endif
++#if defined(CONFIG_IOCTL_CFG80211) && LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35)
++ #error "We haven't verify our cfg80211 solution below kernel version 2.6.35"
++#endif
++
++#if defined(RTW_USE_CFG80211_STA_EVENT)
++ #undef CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER
++#endif
++
++struct rtw_wdev_invit_info {
++ u8 state; /* 0: req, 1:rep */
++ u8 peer_mac[ETH_ALEN];
++ u8 active;
++ u8 token;
++ u8 flags;
++ u8 status;
++ u8 req_op_ch;
++ u8 rsp_op_ch;
++};
++
++#define rtw_wdev_invit_info_init(invit_info) \
++ do { \
++ (invit_info)->state = 0xff; \
++ _rtw_memset((invit_info)->peer_mac, 0, ETH_ALEN); \
++ (invit_info)->active = 0xff; \
++ (invit_info)->token = 0; \
++ (invit_info)->flags = 0x00; \
++ (invit_info)->status = 0xff; \
++ (invit_info)->req_op_ch = 0; \
++ (invit_info)->rsp_op_ch = 0; \
++ } while (0)
++
++struct rtw_wdev_nego_info {
++ u8 state; /* 0: req, 1:rep, 3:conf */
++ u8 peer_mac[ETH_ALEN];
++ u8 active;
++ u8 token;
++ u8 status;
++ u8 req_intent;
++ u8 req_op_ch;
++ u8 req_listen_ch;
++ u8 rsp_intent;
++ u8 rsp_op_ch;
++ u8 conf_op_ch;
++};
++
++#define rtw_wdev_nego_info_init(nego_info) \
++ do { \
++ (nego_info)->state = 0xff; \
++ _rtw_memset((nego_info)->peer_mac, 0, ETH_ALEN); \
++ (nego_info)->active = 0xff; \
++ (nego_info)->token = 0; \
++ (nego_info)->status = 0xff; \
++ (nego_info)->req_intent = 0xff; \
++ (nego_info)->req_op_ch = 0; \
++ (nego_info)->req_listen_ch = 0; \
++ (nego_info)->rsp_intent = 0xff; \
++ (nego_info)->rsp_op_ch = 0; \
++ (nego_info)->conf_op_ch = 0; \
++ } while (0)
++
++struct rtw_wdev_priv
++{
++ struct wireless_dev *rtw_wdev;
++
++ _adapter *padapter;
++
++ struct cfg80211_scan_request *scan_request;
++ _lock scan_req_lock;
++
++ struct net_device *pmon_ndev;//for monitor interface
++ char ifname_mon[IFNAMSIZ + 1]; //interface name for monitor interface
++
++ u8 p2p_enabled;
++
++ u8 provdisc_req_issued;
++
++ struct rtw_wdev_invit_info invit_info;
++ struct rtw_wdev_nego_info nego_info;
++
++ u8 bandroid_scan;
++ bool block;
++ bool power_mgmt;
++
++#ifdef CONFIG_CONCURRENT_MODE
++ ATOMIC_T ro_ch_to;
++ ATOMIC_T switch_ch_to;
++#endif
++
++};
++
++#define wdev_to_priv(w) ((struct rtw_wdev_priv *)(wdev_priv(w)))
++
++#define wiphy_to_adapter(x) (_adapter *)(((struct rtw_wdev_priv*)wiphy_priv(x))->padapter)
++
++#define wiphy_to_wdev(x) (struct wireless_dev *)(((struct rtw_wdev_priv*)wiphy_priv(x))->rtw_wdev)
++
++int rtw_wdev_alloc(_adapter *padapter, struct device *dev);
++void rtw_wdev_free(struct wireless_dev *wdev);
++void rtw_wdev_unregister(struct wireless_dev *wdev);
++
++void rtw_cfg80211_init_wiphy(_adapter *padapter);
++
++void rtw_cfg80211_surveydone_event_callback(_adapter *padapter);
++int rtw_cfg80211_check_bss(_adapter *padapter);
++void rtw_cfg80211_indicate_connect(_adapter *padapter);
++void rtw_cfg80211_indicate_disconnect(_adapter *padapter);
++void rtw_cfg80211_indicate_scan_done(struct rtw_wdev_priv *pwdev_priv, bool aborted);
++
++#ifdef CONFIG_AP_MODE
++void rtw_cfg80211_indicate_sta_assoc(_adapter *padapter, u8 *pmgmt_frame, uint frame_len);
++void rtw_cfg80211_indicate_sta_disassoc(_adapter *padapter, unsigned char *da, unsigned short reason);
++#endif //CONFIG_AP_MODE
++
++void rtw_cfg80211_issue_p2p_provision_request(_adapter *padapter, const u8 *buf, size_t len);
++void rtw_cfg80211_rx_p2p_action_public(_adapter *padapter, u8 *pmgmt_frame, uint frame_len);
++void rtw_cfg80211_rx_action_p2p(_adapter *padapter, u8 *pmgmt_frame, uint frame_len);
++void rtw_cfg80211_rx_action(_adapter *adapter, u8 *frame, uint frame_len, const char*msg);
++
++int rtw_cfg80211_set_mgnt_wpsp2pie(struct net_device *net, char *buf, int len, int type);
++
++bool rtw_cfg80211_pwr_mgmt(_adapter *adapter);
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,4,0)) && !defined(COMPAT_KERNEL_RELEASE)
++#define rtw_cfg80211_rx_mgmt(adapter, freq, sig_dbm, buf, len, gfp) cfg80211_rx_mgmt((adapter)->pnetdev, freq, buf, len, gfp)
++#elif (LINUX_VERSION_CODE < KERNEL_VERSION(3,6,0))
++#define rtw_cfg80211_rx_mgmt(adapter, freq, sig_dbm, buf, len, gfp) cfg80211_rx_mgmt((adapter)->pnetdev, freq, sig_dbm, buf, len, gfp)
++#else
++#define rtw_cfg80211_rx_mgmt(adapter, freq, sig_dbm, buf, len, gfp) cfg80211_rx_mgmt((adapter)->rtw_wdev, freq, sig_dbm, buf, len, gfp)
++#endif
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,4,0)) && !defined(COMPAT_KERNEL_RELEASE)
++#define rtw_cfg80211_send_rx_assoc(adapter, bss, buf, len) cfg80211_send_rx_assoc((adapter)->pnetdev, buf, len)
++#else
++#define rtw_cfg80211_send_rx_assoc(adapter, bss, buf, len) cfg80211_send_rx_assoc((adapter)->pnetdev, bss, buf, len)
++#endif
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,6,0))
++#define rtw_cfg80211_mgmt_tx_status(adapter, cookie, buf, len, ack, gfp) cfg80211_mgmt_tx_status((adapter)->pnetdev, cookie, buf, len, ack, gfp)
++#else
++#define rtw_cfg80211_mgmt_tx_status(adapter, cookie, buf, len, ack, gfp) cfg80211_mgmt_tx_status((adapter)->rtw_wdev, cookie, buf, len, ack, gfp)
++#endif
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,6,0))
++#define rtw_cfg80211_ready_on_channel(adapter, cookie, chan, channel_type, duration, gfp) cfg80211_ready_on_channel((adapter)->pnetdev, cookie, chan, channel_type, duration, gfp)
++#define rtw_cfg80211_remain_on_channel_expired(adapter, cookie, chan, chan_type, gfp) cfg80211_remain_on_channel_expired((adapter)->pnetdev, cookie, chan, chan_type, gfp)
++#elif (LINUX_VERSION_CODE < KERNEL_VERSION(3,8,0))
++#define rtw_cfg80211_ready_on_channel(adapter, cookie, chan, channel_type, duration, gfp) cfg80211_ready_on_channel((adapter)->rtw_wdev, cookie, chan, channel_type, duration, gfp)
++#define rtw_cfg80211_remain_on_channel_expired(adapter, cookie, chan, chan_type, gfp) cfg80211_remain_on_channel_expired((adapter)->rtw_wdev, cookie, chan, chan_type, gfp)
++#else
++#define rtw_cfg80211_ready_on_channel(adapter, cookie, chan, channel_type, duration, gfp) cfg80211_ready_on_channel((adapter)->rtw_wdev, cookie, chan, duration, gfp)
++#define rtw_cfg80211_remain_on_channel_expired(adapter, cookie, chan, chan_type, gfp) cfg80211_remain_on_channel_expired((adapter)->rtw_wdev, cookie, chan, gfp)
++#endif
++
++#endif //__IOCTL_CFG80211_H__
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/ip.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/ip.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/ip.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/ip.h 2015-07-28 01:20:58.317611539 +0200
+@@ -0,0 +1,141 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef _LINUX_IP_H
++#define _LINUX_IP_H
++#include <rtw_byteorder.h>
++
++/* SOL_IP socket options */
++
++#define IPTOS_TOS_MASK 0x1E
++#define IPTOS_TOS(tos) ((tos)&IPTOS_TOS_MASK)
++#define IPTOS_LOWDELAY 0x10
++#define IPTOS_THROUGHPUT 0x08
++#define IPTOS_RELIABILITY 0x04
++#define IPTOS_MINCOST 0x02
++
++#define IPTOS_PREC_MASK 0xE0
++#define IPTOS_PREC(tos) ((tos)&IPTOS_PREC_MASK)
++#define IPTOS_PREC_NETCONTROL 0xe0
++#define IPTOS_PREC_INTERNETCONTROL 0xc0
++#define IPTOS_PREC_CRITIC_ECP 0xa0
++#define IPTOS_PREC_FLASHOVERRIDE 0x80
++#define IPTOS_PREC_FLASH 0x60
++#define IPTOS_PREC_IMMEDIATE 0x40
++#define IPTOS_PREC_PRIORITY 0x20
++#define IPTOS_PREC_ROUTINE 0x00
++
++
++/* IP options */
++#define IPOPT_COPY 0x80
++#define IPOPT_CLASS_MASK 0x60
++#define IPOPT_NUMBER_MASK 0x1f
++
++#define IPOPT_COPIED(o) ((o)&IPOPT_COPY)
++#define IPOPT_CLASS(o) ((o)&IPOPT_CLASS_MASK)
++#define IPOPT_NUMBER(o) ((o)&IPOPT_NUMBER_MASK)
++
++#define IPOPT_CONTROL 0x00
++#define IPOPT_RESERVED1 0x20
++#define IPOPT_MEASUREMENT 0x40
++#define IPOPT_RESERVED2 0x60
++
++#define IPOPT_END (0 |IPOPT_CONTROL)
++#define IPOPT_NOOP (1 |IPOPT_CONTROL)
++#define IPOPT_SEC (2 |IPOPT_CONTROL|IPOPT_COPY)
++#define IPOPT_LSRR (3 |IPOPT_CONTROL|IPOPT_COPY)
++#define IPOPT_TIMESTAMP (4 |IPOPT_MEASUREMENT)
++#define IPOPT_RR (7 |IPOPT_CONTROL)
++#define IPOPT_SID (8 |IPOPT_CONTROL|IPOPT_COPY)
++#define IPOPT_SSRR (9 |IPOPT_CONTROL|IPOPT_COPY)
++#define IPOPT_RA (20|IPOPT_CONTROL|IPOPT_COPY)
++
++#define IPVERSION 4
++#define MAXTTL 255
++#define IPDEFTTL 64
++
++/* struct timestamp, struct route and MAX_ROUTES are removed.
++
++ REASONS: it is clear that nobody used them because:
++ - MAX_ROUTES value was wrong.
++ - "struct route" was wrong.
++ - "struct timestamp" had fatally misaligned bitfields and was completely unusable.
++ */
++
++#define IPOPT_OPTVAL 0
++#define IPOPT_OLEN 1
++#define IPOPT_OFFSET 2
++#define IPOPT_MINOFF 4
++#define MAX_IPOPTLEN 40
++#define IPOPT_NOP IPOPT_NOOP
++#define IPOPT_EOL IPOPT_END
++#define IPOPT_TS IPOPT_TIMESTAMP
++
++#define IPOPT_TS_TSONLY 0 /* timestamps only */
++#define IPOPT_TS_TSANDADDR 1 /* timestamps and addresses */
++#define IPOPT_TS_PRESPEC 3 /* specified modules only */
++
++#ifdef PLATFORM_LINUX
++
++struct ip_options {
++ __u32 faddr; /* Saved first hop address */
++ unsigned char optlen;
++ unsigned char srr;
++ unsigned char rr;
++ unsigned char ts;
++ unsigned char is_setbyuser:1, /* Set by setsockopt? */
++ is_data:1, /* Options in __data, rather than skb */
++ is_strictroute:1, /* Strict source route */
++ srr_is_hit:1, /* Packet destination addr was our one */
++ is_changed:1, /* IP checksum more not valid */
++ rr_needaddr:1, /* Need to record addr of outgoing dev */
++ ts_needtime:1, /* Need to record timestamp */
++ ts_needaddr:1; /* Need to record addr of outgoing dev */
++ unsigned char router_alert;
++ unsigned char __pad1;
++ unsigned char __pad2;
++ unsigned char __data[0];
++};
++
++#define optlength(opt) (sizeof(struct ip_options) + opt->optlen)
++#endif
++
++struct iphdr {
++#if defined(__LITTLE_ENDIAN_BITFIELD)
++ __u8 ihl:4,
++ version:4;
++#elif defined (__BIG_ENDIAN_BITFIELD)
++ __u8 version:4,
++ ihl:4;
++#else
++#error "Please fix <asm/byteorder.h>"
++#endif
++ __u8 tos;
++ __u16 tot_len;
++ __u16 id;
++ __u16 frag_off;
++ __u8 ttl;
++ __u8 protocol;
++ __u16 check;
++ __u32 saddr;
++ __u32 daddr;
++ /*The options start here. */
++};
++
++#endif /* _LINUX_IP_H */
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/linux/wireless.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/linux/wireless.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/linux/wireless.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/linux/wireless.h 2015-07-28 01:20:58.317611539 +0200
+@@ -0,0 +1,90 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++
++#ifndef _LINUX_WIRELESS_H
++#define _LINUX_WIRELESS_H
++
++/***************************** INCLUDES *****************************/
++
++#if 0
++#include <linux/types.h> /* for __u* and __s* typedefs */
++#include <linux/socket.h> /* for "struct sockaddr" et al */
++#include <linux/if.h> /* for IFNAMSIZ and co... */
++#else
++#define __user
++//typedef uint16_t __u16;
++#include <sys/socket.h> /* for "struct sockaddr" et al */
++#include <net/if.h> /* for IFNAMSIZ and co... */
++#endif
++
++/****************************** TYPES ******************************/
++
++/* --------------------------- SUBTYPES --------------------------- */
++/*
++ * For all data larger than 16 octets, we need to use a
++ * pointer to memory allocated in user space.
++ */
++struct iw_point
++{
++ void __user *pointer; /* Pointer to the data (in user space) */
++ __u16 length; /* number of fields or size in bytes */
++ __u16 flags; /* Optional params */
++};
++
++
++/* ------------------------ IOCTL REQUEST ------------------------ */
++/*
++ * This structure defines the payload of an ioctl, and is used
++ * below.
++ *
++ * Note that this structure should fit on the memory footprint
++ * of iwreq (which is the same as ifreq), which mean a max size of
++ * 16 octets = 128 bits. Warning, pointers might be 64 bits wide...
++ * You should check this when increasing the structures defined
++ * above in this file...
++ */
++union iwreq_data
++{
++ /* Config - generic */
++ char name[IFNAMSIZ];
++ /* Name : used to verify the presence of wireless extensions.
++ * Name of the protocol/provider... */
++
++ struct iw_point data; /* Other large parameters */
++};
++
++/*
++ * The structure to exchange data for ioctl.
++ * This structure is the same as 'struct ifreq', but (re)defined for
++ * convenience...
++ * Do I need to remind you about structure size (32 octets) ?
++ */
++struct iwreq
++{
++ union
++ {
++ char ifrn_name[IFNAMSIZ]; /* if name, e.g. "eth0" */
++ } ifr_ifrn;
++
++ /* Data part (defined just above) */
++ union iwreq_data u;
++};
++
++#endif /* _LINUX_WIRELESS_H */
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/mlme_osdep.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/mlme_osdep.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/mlme_osdep.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/mlme_osdep.h 2015-07-28 01:20:58.317611539 +0200
+@@ -0,0 +1,39 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef __MLME_OSDEP_H_
++#define __MLME_OSDEP_H_
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++
++#if defined(PLATFORM_WINDOWS) || defined(PLATFORM_MPIXEL)
++extern int time_after(u32 now, u32 old);
++#endif
++
++extern void rtw_init_mlme_timer(_adapter *padapter);
++extern void rtw_os_indicate_disconnect( _adapter *adapter );
++extern void rtw_os_indicate_connect( _adapter *adapter );
++void rtw_os_indicate_scan_done( _adapter *padapter, bool aborted);
++extern void rtw_report_sec_ie(_adapter *adapter,u8 authmode,u8 *sec_ie);
++
++void rtw_reset_securitypriv( _adapter *adapter );
++
++#endif //_MLME_OSDEP_H_
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/mp_custom_oid.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/mp_custom_oid.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/mp_custom_oid.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/mp_custom_oid.h 2015-07-28 01:20:58.317611539 +0200
+@@ -0,0 +1,353 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef __CUSTOM_OID_H
++#define __CUSTOM_OID_H
++
++// by Owen
++// 0xFF818000 - 0xFF81802F RTL8180 Mass Production Kit
++// 0xFF818500 - 0xFF81850F RTL8185 Setup Utility
++// 0xFF818580 - 0xFF81858F RTL8185 Phy Status Utility
++
++//
++
++// by Owen for Production Kit
++// For Production Kit with Agilent Equipments
++// in order to make our custom oids hopefully somewhat unique
++// we will use 0xFF (indicating implementation specific OID)
++// 81(first byte of non zero Realtek unique identifier)
++// 80 (second byte of non zero Realtek unique identifier)
++// XX (the custom OID number - providing 255 possible custom oids)
++
++#define OID_RT_PRO_RESET_DUT 0xFF818000
++#define OID_RT_PRO_SET_DATA_RATE 0xFF818001
++#define OID_RT_PRO_START_TEST 0xFF818002
++#define OID_RT_PRO_STOP_TEST 0xFF818003
++#define OID_RT_PRO_SET_PREAMBLE 0xFF818004
++#define OID_RT_PRO_SET_SCRAMBLER 0xFF818005
++#define OID_RT_PRO_SET_FILTER_BB 0xFF818006
++#define OID_RT_PRO_SET_MANUAL_DIVERSITY_BB 0xFF818007
++#define OID_RT_PRO_SET_CHANNEL_DIRECT_CALL 0xFF818008
++#define OID_RT_PRO_SET_SLEEP_MODE_DIRECT_CALL 0xFF818009
++#define OID_RT_PRO_SET_WAKE_MODE_DIRECT_CALL 0xFF81800A
++
++#define OID_RT_PRO_SET_TX_ANTENNA_BB 0xFF81800D
++#define OID_RT_PRO_SET_ANTENNA_BB 0xFF81800E
++#define OID_RT_PRO_SET_CR_SCRAMBLER 0xFF81800F
++#define OID_RT_PRO_SET_CR_NEW_FILTER 0xFF818010
++#define OID_RT_PRO_SET_TX_POWER_CONTROL 0xFF818011
++#define OID_RT_PRO_SET_CR_TX_CONFIG 0xFF818012
++#define OID_RT_PRO_GET_TX_POWER_CONTROL 0xFF818013
++#define OID_RT_PRO_GET_CR_SIGNAL_QUALITY 0xFF818014
++#define OID_RT_PRO_SET_CR_SETPOINT 0xFF818015
++#define OID_RT_PRO_SET_INTEGRATOR 0xFF818016
++#define OID_RT_PRO_SET_SIGNAL_QUALITY 0xFF818017
++#define OID_RT_PRO_GET_INTEGRATOR 0xFF818018
++#define OID_RT_PRO_GET_SIGNAL_QUALITY 0xFF818019
++#define OID_RT_PRO_QUERY_EEPROM_TYPE 0xFF81801A
++#define OID_RT_PRO_WRITE_MAC_ADDRESS 0xFF81801B
++#define OID_RT_PRO_READ_MAC_ADDRESS 0xFF81801C
++#define OID_RT_PRO_WRITE_CIS_DATA 0xFF81801D
++#define OID_RT_PRO_READ_CIS_DATA 0xFF81801E
++#define OID_RT_PRO_WRITE_POWER_CONTROL 0xFF81801F
++#define OID_RT_PRO_READ_POWER_CONTROL 0xFF818020
++#define OID_RT_PRO_WRITE_EEPROM 0xFF818021
++#define OID_RT_PRO_READ_EEPROM 0xFF818022
++#define OID_RT_PRO_RESET_TX_PACKET_SENT 0xFF818023
++#define OID_RT_PRO_QUERY_TX_PACKET_SENT 0xFF818024
++#define OID_RT_PRO_RESET_RX_PACKET_RECEIVED 0xFF818025
++#define OID_RT_PRO_QUERY_RX_PACKET_RECEIVED 0xFF818026
++#define OID_RT_PRO_QUERY_RX_PACKET_CRC32_ERROR 0xFF818027
++#define OID_RT_PRO_QUERY_CURRENT_ADDRESS 0xFF818028
++#define OID_RT_PRO_QUERY_PERMANENT_ADDRESS 0xFF818029
++#define OID_RT_PRO_SET_PHILIPS_RF_PARAMETERS 0xFF81802A
++#define OID_RT_PRO_RECEIVE_PACKET 0xFF81802C
++// added by Owen on 04/08/03 for Cameo's request
++#define OID_RT_PRO_WRITE_EEPROM_BYTE 0xFF81802D
++#define OID_RT_PRO_READ_EEPROM_BYTE 0xFF81802E
++#define OID_RT_PRO_SET_MODULATION 0xFF81802F
++//
++
++//Sean
++#define OID_RT_DRIVER_OPTION 0xFF818080
++#define OID_RT_RF_OFF 0xFF818081
++#define OID_RT_AUTH_STATUS 0xFF818082
++
++//========================================================================
++#define OID_RT_PRO_SET_CONTINUOUS_TX 0xFF81800B
++#define OID_RT_PRO_SET_SINGLE_CARRIER_TX 0xFF81800C
++#define OID_RT_PRO_SET_CARRIER_SUPPRESSION_TX 0xFF81802B
++#define OID_RT_PRO_SET_SINGLE_TONE_TX 0xFF818043
++//========================================================================
++
++
++// by Owen for RTL8185 Phy Status Report Utility
++#define OID_RT_UTILITY_FALSE_ALARM_COUNTERS 0xFF818580
++#define OID_RT_UTILITY_SELECT_DEBUG_MODE 0xFF818581
++#define OID_RT_UTILITY_SELECT_SUBCARRIER_NUMBER 0xFF818582
++#define OID_RT_UTILITY_GET_RSSI_STATUS 0xFF818583
++#define OID_RT_UTILITY_GET_FRAME_DETECTION_STATUS 0xFF818584
++#define OID_RT_UTILITY_GET_AGC_AND_FREQUENCY_OFFSET_ESTIMATION_STATUS 0xFF818585
++#define OID_RT_UTILITY_GET_CHANNEL_ESTIMATION_STATUS 0xFF818586
++//
++
++// by Owen on 03/09/19-03/09/22 for RTL8185
++#define OID_RT_WIRELESS_MODE 0xFF818500
++#define OID_RT_SUPPORTED_RATES 0xFF818501
++#define OID_RT_DESIRED_RATES 0xFF818502
++#define OID_RT_WIRELESS_MODE_STARTING_ADHOC 0xFF818503
++//
++
++#define OID_RT_GET_CONNECT_STATE 0xFF030001
++#define OID_RT_RESCAN 0xFF030002
++#define OID_RT_SET_KEY_LENGTH 0xFF030003
++#define OID_RT_SET_DEFAULT_KEY_ID 0xFF030004
++
++#define OID_RT_SET_CHANNEL 0xFF010182
++#define OID_RT_SET_SNIFFER_MODE 0xFF010183
++#define OID_RT_GET_SIGNAL_QUALITY 0xFF010184
++#define OID_RT_GET_SMALL_PACKET_CRC 0xFF010185
++#define OID_RT_GET_MIDDLE_PACKET_CRC 0xFF010186
++#define OID_RT_GET_LARGE_PACKET_CRC 0xFF010187
++#define OID_RT_GET_TX_RETRY 0xFF010188
++#define OID_RT_GET_RX_RETRY 0xFF010189
++#define OID_RT_PRO_SET_FW_DIG_STATE 0xFF01018A//S
++#define OID_RT_PRO_SET_FW_RA_STATE 0xFF01018B//S
++
++#define OID_RT_GET_RX_TOTAL_PACKET 0xFF010190
++#define OID_RT_GET_TX_BEACON_OK 0xFF010191
++#define OID_RT_GET_TX_BEACON_ERR 0xFF010192
++#define OID_RT_GET_RX_ICV_ERR 0xFF010193
++#define OID_RT_SET_ENCRYPTION_ALGORITHM 0xFF010194
++#define OID_RT_SET_NO_AUTO_RESCAN 0xFF010195
++#define OID_RT_GET_PREAMBLE_MODE 0xFF010196
++#define OID_RT_GET_DRIVER_UP_DELTA_TIME 0xFF010197
++#define OID_RT_GET_AP_IP 0xFF010198
++#define OID_RT_GET_CHANNELPLAN 0xFF010199
++#define OID_RT_SET_PREAMBLE_MODE 0xFF01019A
++#define OID_RT_SET_BCN_INTVL 0xFF01019B
++#define OID_RT_GET_RF_VENDER 0xFF01019C
++#define OID_RT_DEDICATE_PROBE 0xFF01019D
++#define OID_RT_PRO_RX_FILTER_PATTERN 0xFF01019E
++
++#define OID_RT_GET_DCST_CURRENT_THRESHOLD 0xFF01019F
++
++#define OID_RT_GET_CCA_ERR 0xFF0101A0
++#define OID_RT_GET_CCA_UPGRADE_THRESHOLD 0xFF0101A1
++#define OID_RT_GET_CCA_FALLBACK_THRESHOLD 0xFF0101A2
++
++#define OID_RT_GET_CCA_UPGRADE_EVALUATE_TIMES 0xFF0101A3
++#define OID_RT_GET_CCA_FALLBACK_EVALUATE_TIMES 0xFF0101A4
++
++// by Owen on 03/31/03 for Cameo's request
++#define OID_RT_SET_RATE_ADAPTIVE 0xFF0101A5
++//
++#define OID_RT_GET_DCST_EVALUATE_PERIOD 0xFF0101A5
++#define OID_RT_GET_DCST_TIME_UNIT_INDEX 0xFF0101A6
++#define OID_RT_GET_TOTAL_TX_BYTES 0xFF0101A7
++#define OID_RT_GET_TOTAL_RX_BYTES 0xFF0101A8
++#define OID_RT_CURRENT_TX_POWER_LEVEL 0xFF0101A9
++#define OID_RT_GET_ENC_KEY_MISMATCH_COUNT 0xFF0101AA
++#define OID_RT_GET_ENC_KEY_MATCH_COUNT 0xFF0101AB
++#define OID_RT_GET_CHANNEL 0xFF0101AC
++
++#define OID_RT_SET_CHANNELPLAN 0xFF0101AD
++#define OID_RT_GET_HARDWARE_RADIO_OFF 0xFF0101AE
++#define OID_RT_CHANNELPLAN_BY_COUNTRY 0xFF0101AF
++#define OID_RT_SCAN_AVAILABLE_BSSID 0xFF0101B0
++#define OID_RT_GET_HARDWARE_VERSION 0xFF0101B1
++#define OID_RT_GET_IS_ROAMING 0xFF0101B2
++#define OID_RT_GET_IS_PRIVACY 0xFF0101B3
++#define OID_RT_GET_KEY_MISMATCH 0xFF0101B4
++#define OID_RT_SET_RSSI_ROAM_TRAFFIC_TH 0xFF0101B5
++#define OID_RT_SET_RSSI_ROAM_SIGNAL_TH 0xFF0101B6
++#define OID_RT_RESET_LOG 0xFF0101B7
++#define OID_RT_GET_LOG 0xFF0101B8
++#define OID_RT_SET_INDICATE_HIDDEN_AP 0xFF0101B9
++#define OID_RT_GET_HEADER_FAIL 0xFF0101BA
++#define OID_RT_SUPPORTED_WIRELESS_MODE 0xFF0101BB
++#define OID_RT_GET_CHANNEL_LIST 0xFF0101BC
++#define OID_RT_GET_SCAN_IN_PROGRESS 0xFF0101BD
++#define OID_RT_GET_TX_INFO 0xFF0101BE
++#define OID_RT_RF_READ_WRITE_OFFSET 0xFF0101BF
++#define OID_RT_RF_READ_WRITE 0xFF0101C0
++
++// For Netgear request. 2005.01.13, by rcnjko.
++#define OID_RT_FORCED_DATA_RATE 0xFF0101C1
++#define OID_RT_WIRELESS_MODE_FOR_SCAN_LIST 0xFF0101C2
++// For Netgear request. 2005.02.17, by rcnjko.
++#define OID_RT_GET_BSS_WIRELESS_MODE 0xFF0101C3
++// For AZ project. 2005.06.27, by rcnjko.
++#define OID_RT_SCAN_WITH_MAGIC_PACKET 0xFF0101C4
++
++// Vincent 8185MP
++#define OID_RT_PRO_RX_FILTER 0xFF0111C0
++
++//Andy TEST
++//#define OID_RT_PRO_WRITE_REGISTRY 0xFF0111C1
++//#define OID_RT_PRO_READ_REGISTRY 0xFF0111C2
++#define OID_CE_USB_WRITE_REGISTRY 0xFF0111C1
++#define OID_CE_USB_READ_REGISTRY 0xFF0111C2
++
++
++#define OID_RT_PRO_SET_INITIAL_GAIN 0xFF0111C3
++#define OID_RT_PRO_SET_BB_RF_STANDBY_MODE 0xFF0111C4
++#define OID_RT_PRO_SET_BB_RF_SHUTDOWN_MODE 0xFF0111C5
++#define OID_RT_PRO_SET_TX_CHARGE_PUMP 0xFF0111C6
++#define OID_RT_PRO_SET_RX_CHARGE_PUMP 0xFF0111C7
++#define OID_RT_PRO_RF_WRITE_REGISTRY 0xFF0111C8
++#define OID_RT_PRO_RF_READ_REGISTRY 0xFF0111C9
++#define OID_RT_PRO_QUERY_RF_TYPE 0xFF0111CA
++
++// AP OID
++#define OID_RT_AP_GET_ASSOCIATED_STATION_LIST 0xFF010300
++#define OID_RT_AP_GET_CURRENT_TIME_STAMP 0xFF010301
++#define OID_RT_AP_SWITCH_INTO_AP_MODE 0xFF010302
++#define OID_RT_AP_SET_DTIM_PERIOD 0xFF010303
++#define OID_RT_AP_SUPPORTED 0xFF010304 // Determine if driver supports AP mode. 2004.08.27, by rcnjko.
++#define OID_RT_AP_SET_PASSPHRASE 0xFF010305 // Set WPA-PSK passphrase into authenticator. 2005.07.08, byrcnjko.
++
++// 8187MP. 2004.09.06, by rcnjko.
++#define OID_RT_PRO8187_WI_POLL 0xFF818780
++#define OID_RT_PRO_WRITE_BB_REG 0xFF818781
++#define OID_RT_PRO_READ_BB_REG 0xFF818782
++#define OID_RT_PRO_WRITE_RF_REG 0xFF818783
++#define OID_RT_PRO_READ_RF_REG 0xFF818784
++
++// Meeting House. added by Annie, 2005-07-20.
++#define OID_RT_MH_VENDER_ID 0xFFEDC100
++
++//8711 MP OID added 20051230.
++#define OID_RT_PRO8711_JOIN_BSS 0xFF871100//S
++
++#define OID_RT_PRO_READ_REGISTER 0xFF871101 //Q
++#define OID_RT_PRO_WRITE_REGISTER 0xFF871102 //S
++
++#define OID_RT_PRO_BURST_READ_REGISTER 0xFF871103 //Q
++#define OID_RT_PRO_BURST_WRITE_REGISTER 0xFF871104 //S
++
++#define OID_RT_PRO_WRITE_TXCMD 0xFF871105 //S
++
++#define OID_RT_PRO_READ16_EEPROM 0xFF871106 //Q
++#define OID_RT_PRO_WRITE16_EEPROM 0xFF871107 //S
++
++#define OID_RT_PRO_H2C_SET_COMMAND 0xFF871108 //S
++#define OID_RT_PRO_H2C_QUERY_RESULT 0xFF871109 //Q
++
++#define OID_RT_PRO8711_WI_POLL 0xFF87110A //Q
++#define OID_RT_PRO8711_PKT_LOSS 0xFF87110B //Q
++#define OID_RT_RD_ATTRIB_MEM 0xFF87110C//Q
++#define OID_RT_WR_ATTRIB_MEM 0xFF87110D//S
++
++
++//Method 2 for H2C/C2H
++#define OID_RT_PRO_H2C_CMD_MODE 0xFF871110 //S
++#define OID_RT_PRO_H2C_CMD_RSP_MODE 0xFF871111 //Q
++#define OID_RT_PRO_H2C_CMD_EVENT_MODE 0xFF871112 //S
++#define OID_RT_PRO_WAIT_C2H_EVENT 0xFF871113 //Q
++#define OID_RT_PRO_RW_ACCESS_PROTOCOL_TEST 0xFF871114//Q
++
++#define OID_RT_PRO_SCSI_ACCESS_TEST 0xFF871115 //Q, S
++
++#define OID_RT_PRO_SCSI_TCPIPOFFLOAD_OUT 0xFF871116 //S
++#define OID_RT_PRO_SCSI_TCPIPOFFLOAD_IN 0xFF871117 //Q,S
++#define OID_RT_RRO_RX_PKT_VIA_IOCTRL 0xFF871118 //Q
++#define OID_RT_RRO_RX_PKTARRAY_VIA_IOCTRL 0xFF871119 //Q
++
++#define OID_RT_RPO_SET_PWRMGT_TEST 0xFF87111A //S
++#define OID_RT_PRO_QRY_PWRMGT_TEST 0XFF87111B //Q
++#define OID_RT_RPO_ASYNC_RWIO_TEST 0xFF87111C //S
++#define OID_RT_RPO_ASYNC_RWIO_POLL 0xFF87111D //Q
++#define OID_RT_PRO_SET_RF_INTFS 0xFF87111E //S
++#define OID_RT_POLL_RX_STATUS 0xFF87111F //Q
++
++#define OID_RT_PRO_CFG_DEBUG_MESSAGE 0xFF871120 //Q,S
++#define OID_RT_PRO_SET_DATA_RATE_EX 0xFF871121//S
++#define OID_RT_PRO_SET_BASIC_RATE 0xFF871122//S
++#define OID_RT_PRO_READ_TSSI 0xFF871123//S
++#define OID_RT_PRO_SET_POWER_TRACKING 0xFF871124//S
++
++
++#define OID_RT_PRO_QRY_PWRSTATE 0xFF871150 //Q
++#define OID_RT_PRO_SET_PWRSTATE 0xFF871151 //S
++
++//Method 2 , using workitem
++#define OID_RT_SET_READ_REG 0xFF871181 //S
++#define OID_RT_SET_WRITE_REG 0xFF871182 //S
++#define OID_RT_SET_BURST_READ_REG 0xFF871183 //S
++#define OID_RT_SET_BURST_WRITE_REG 0xFF871184 //S
++#define OID_RT_SET_WRITE_TXCMD 0xFF871185 //S
++#define OID_RT_SET_READ16_EEPROM 0xFF871186 //S
++#define OID_RT_SET_WRITE16_EEPROM 0xFF871187 //S
++#define OID_RT_QRY_POLL_WKITEM 0xFF871188 //Q
++
++//For SDIO INTERFACE only
++#define OID_RT_PRO_SYNCPAGERW_SRAM 0xFF8711A0 //Q, S
++#define OID_RT_PRO_871X_DRV_EXT 0xFF8711A1
++
++//For USB INTERFACE only
++#define OID_RT_PRO_USB_VENDOR_REQ 0xFF8711B0 //Q, S
++#define OID_RT_PRO_SCSI_AUTO_TEST 0xFF8711B1 //S
++#define OID_RT_PRO_USB_MAC_AC_FIFO_WRITE 0xFF8711B2 //S
++#define OID_RT_PRO_USB_MAC_RX_FIFO_READ 0xFF8711B3 //Q
++#define OID_RT_PRO_USB_MAC_RX_FIFO_POLLING 0xFF8711B4 //Q
++
++#define OID_RT_PRO_H2C_SET_RATE_TABLE 0xFF8711FB //S
++#define OID_RT_PRO_H2C_GET_RATE_TABLE 0xFF8711FC //S
++#define OID_RT_PRO_H2C_C2H_LBK_TEST 0xFF8711FE
++
++#define OID_RT_PRO_ENCRYPTION_CTRL 0xFF871200 //Q, S
++#define OID_RT_PRO_ADD_STA_INFO 0xFF871201 //S
++#define OID_RT_PRO_DELE_STA_INFO 0xFF871202 //S
++#define OID_RT_PRO_QUERY_DR_VARIABLE 0xFF871203 //Q
++
++#define OID_RT_PRO_RX_PACKET_TYPE 0xFF871204 //Q, S
++
++#define OID_RT_PRO_READ_EFUSE 0xFF871205 //Q
++#define OID_RT_PRO_WRITE_EFUSE 0xFF871206 //S
++#define OID_RT_PRO_RW_EFUSE_PGPKT 0xFF871207 //Q, S
++#define OID_RT_GET_EFUSE_CURRENT_SIZE 0xFF871208 //Q
++
++#define OID_RT_SET_BANDWIDTH 0xFF871209 //S
++#define OID_RT_SET_CRYSTAL_CAP 0xFF87120A //S
++
++#define OID_RT_SET_RX_PACKET_TYPE 0xFF87120B //S
++
++#define OID_RT_GET_EFUSE_MAX_SIZE 0xFF87120C //Q
++
++#define OID_RT_PRO_SET_TX_AGC_OFFSET 0xFF87120D //S
++
++#define OID_RT_PRO_SET_PKT_TEST_MODE 0xFF87120E //S
++
++#define OID_RT_PRO_FOR_EVM_TEST_SETTING 0xFF87120F //S
++
++#define OID_RT_PRO_GET_THERMAL_METER 0xFF871210 //Q
++
++#define OID_RT_RESET_PHY_RX_PACKET_COUNT 0xFF871211 //S
++#define OID_RT_GET_PHY_RX_PACKET_RECEIVED 0xFF871212 //Q
++#define OID_RT_GET_PHY_RX_PACKET_CRC32_ERROR 0xFF871213 //Q
++
++#define OID_RT_SET_POWER_DOWN 0xFF871214 //S
++
++#define OID_RT_GET_POWER_MODE 0xFF871215 //Q
++
++#define OID_RT_PRO_EFUSE 0xFF871216 //Q, S
++#define OID_RT_PRO_EFUSE_MAP 0xFF871217 //Q, S
++
++#endif //#ifndef __CUSTOM_OID_H
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/nic_spec.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/nic_spec.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/nic_spec.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/nic_spec.h 2015-07-28 01:20:58.317611539 +0200
+@@ -0,0 +1,46 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++
++
++#ifndef __NIC_SPEC_H__
++#define __NIC_SPEC_H__
++
++#include <drv_conf.h>
++
++#define RTL8711_MCTRL_ (0x20000)
++#define RTL8711_UART_ (0x30000)
++#define RTL8711_TIMER_ (0x40000)
++#define RTL8711_FINT_ (0x50000)
++#define RTL8711_HINT_ (0x50000)
++#define RTL8711_GPIO_ (0x60000)
++#define RTL8711_WLANCTRL_ (0x200000)
++#define RTL8711_WLANFF_ (0xe00000)
++#define RTL8711_HCICTRL_ (0x600000)
++#define RTL8711_SYSCFG_ (0x620000)
++#define RTL8711_SYSCTRL_ (0x620000)
++#define RTL8711_MCCTRL_ (0x020000)
++
++
++#include <rtl8711_regdef.h>
++
++#include <rtl8711_bitdef.h>
++
++
++#endif // __RTL8711_SPEC_H__
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/osdep_ce_service.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/osdep_ce_service.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/osdep_ce_service.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/osdep_ce_service.h 2015-07-28 01:20:58.317611539 +0200
+@@ -0,0 +1,170 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++
++#ifndef __OSDEP_CE_SERVICE_H_
++#define __OSDEP_CE_SERVICE_H_
++
++
++#include <ndis.h>
++#include <ntddndis.h>
++
++#ifdef CONFIG_SDIO_HCI
++#include "SDCardDDK.h"
++#endif
++
++#ifdef CONFIG_USB_HCI
++#include <usbdi.h>
++#endif
++
++typedef HANDLE _sema;
++typedef LIST_ENTRY _list;
++typedef NDIS_STATUS _OS_STATUS;
++
++typedef NDIS_SPIN_LOCK _lock;
++
++typedef HANDLE _rwlock; //Mutex
++
++typedef u32 _irqL;
++
++typedef NDIS_HANDLE _nic_hdl;
++
++
++typedef NDIS_MINIPORT_TIMER _timer;
++
++struct __queue {
++ LIST_ENTRY queue;
++ _lock lock;
++};
++
++typedef NDIS_PACKET _pkt;
++typedef NDIS_BUFFER _buffer;
++typedef struct __queue _queue;
++
++typedef HANDLE _thread_hdl_;
++typedef DWORD thread_return;
++typedef void* thread_context;
++typedef NDIS_WORK_ITEM _workitem;
++
++#define thread_exit() ExitThread(STATUS_SUCCESS); return 0;
++
++
++#define SEMA_UPBND (0x7FFFFFFF) //8192
++
++__inline static _list *get_prev(_list *list)
++{
++ return list->Blink;
++}
++
++__inline static _list *get_next(_list *list)
++{
++ return list->Flink;
++}
++
++__inline static _list *get_list_head(_queue *queue)
++{
++ return (&(queue->queue));
++}
++
++#define LIST_CONTAINOR(ptr, type, member) CONTAINING_RECORD(ptr, type, member)
++
++__inline static void _enter_critical(_lock *plock, _irqL *pirqL)
++{
++ NdisAcquireSpinLock(plock);
++}
++
++__inline static void _exit_critical(_lock *plock, _irqL *pirqL)
++{
++ NdisReleaseSpinLock(plock);
++}
++
++__inline static _enter_critical_ex(_lock *plock, _irqL *pirqL)
++{
++ NdisDprAcquireSpinLock(plock);
++}
++
++__inline static _exit_critical_ex(_lock *plock, _irqL *pirqL)
++{
++ NdisDprReleaseSpinLock(plock);
++}
++
++
++__inline static void _enter_hwio_critical(_rwlock *prwlock, _irqL *pirqL)
++{
++ WaitForSingleObject(*prwlock, INFINITE );
++
++}
++
++__inline static void _exit_hwio_critical(_rwlock *prwlock, _irqL *pirqL)
++{
++ ReleaseMutex(*prwlock);
++}
++
++__inline static void rtw_list_delete(_list *plist)
++{
++ RemoveEntryList(plist);
++ InitializeListHead(plist);
++}
++
++__inline static void _init_timer(_timer *ptimer,_nic_hdl nic_hdl,void *pfunc,PVOID cntx)
++{
++ NdisMInitializeTimer(ptimer, nic_hdl, pfunc, cntx);
++}
++
++__inline static void _set_timer(_timer *ptimer,u32 delay_time)
++{
++ NdisMSetTimer(ptimer,delay_time);
++}
++
++__inline static void _cancel_timer(_timer *ptimer,u8 *bcancelled)
++{
++ NdisMCancelTimer(ptimer,bcancelled);
++}
++
++__inline static void _init_workitem(_workitem *pwork, void *pfunc, PVOID cntx)
++{
++
++ NdisInitializeWorkItem(pwork, pfunc, cntx);
++}
++
++__inline static void _set_workitem(_workitem *pwork)
++{
++ NdisScheduleWorkItem(pwork);
++}
++
++#define ATOMIC_INIT(i) { (i) }
++
++//
++// Global Mutex: can only be used at PASSIVE level.
++//
++
++#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter) \
++{ \
++ while (NdisInterlockedIncrement((PULONG)&(_MutexCounter)) != 1)\
++ { \
++ NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \
++ NdisMSleep(10000); \
++ } \
++}
++
++#define RELEASE_GLOBAL_MUTEX(_MutexCounter) \
++{ \
++ NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \
++}
++#endif
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/osdep_intf.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/osdep_intf.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/osdep_intf.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/osdep_intf.h 2015-07-28 01:20:58.317611539 +0200
+@@ -0,0 +1,154 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++
++#ifndef __OSDEP_INTF_H_
++#define __OSDEP_INTF_H_
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++
++struct intf_priv {
++
++ u8 *intf_dev;
++ u32 max_iosz; //USB2.0: 128, USB1.1: 64, SDIO:64
++ u32 max_xmitsz; //USB2.0: unlimited, SDIO:512
++ u32 max_recvsz; //USB2.0: unlimited, SDIO:512
++
++ volatile u8 *io_rwmem;
++ volatile u8 *allocated_io_rwmem;
++ u32 io_wsz; //unit: 4bytes
++ u32 io_rsz;//unit: 4bytes
++ u8 intf_status;
++
++ void (*_bus_io)(u8 *priv);
++
++/*
++Under Sync. IRP (SDIO/USB)
++A protection mechanism is necessary for the io_rwmem(read/write protocol)
++
++Under Async. IRP (SDIO/USB)
++The protection mechanism is through the pending queue.
++*/
++
++ _mutex ioctl_mutex;
++
++
++#ifdef PLATFORM_LINUX
++ #ifdef CONFIG_USB_HCI
++ // when in USB, IO is through interrupt in/out endpoints
++ struct usb_device *udev;
++ PURB piorw_urb;
++ u8 io_irp_cnt;
++ u8 bio_irp_pending;
++ _sema io_retevt;
++ _timer io_timer;
++ u8 bio_irp_timeout;
++ u8 bio_timer_cancel;
++ #endif
++#endif
++
++#ifdef PLATFORM_OS_XP
++ #ifdef CONFIG_SDIO_HCI
++ // below is for io_rwmem...
++ PMDL pmdl;
++ PSDBUS_REQUEST_PACKET sdrp;
++ PSDBUS_REQUEST_PACKET recv_sdrp;
++ PSDBUS_REQUEST_PACKET xmit_sdrp;
++
++ PIRP piorw_irp;
++
++ #endif
++ #ifdef CONFIG_USB_HCI
++ PURB piorw_urb;
++ PIRP piorw_irp;
++ u8 io_irp_cnt;
++ u8 bio_irp_pending;
++ _sema io_retevt;
++ #endif
++#endif
++
++};
++
++
++#ifdef CONFIG_R871X_TEST
++int rtw_start_pseudo_adhoc(_adapter *padapter);
++int rtw_stop_pseudo_adhoc(_adapter *padapter);
++#endif
++
++struct dvobj_priv *devobj_init(void);
++void devobj_deinit(struct dvobj_priv *pdvobj);
++
++u8 rtw_init_drv_sw(_adapter *padapter);
++u8 rtw_free_drv_sw(_adapter *padapter);
++u8 rtw_reset_drv_sw(_adapter *padapter);
++
++u32 rtw_start_drv_threads(_adapter *padapter);
++void rtw_stop_drv_threads (_adapter *padapter);
++void rtw_cancel_all_timer(_adapter *padapter);
++
++#ifdef PLATFORM_LINUX
++int rtw_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
++
++int rtw_init_netdev_name(struct net_device *pnetdev, const char *ifname);
++struct net_device *rtw_init_netdev(_adapter *padapter);
++void rtw_unregister_netdevs(struct dvobj_priv *dvobj);
++
++#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,35))
++u16 rtw_recv_select_queue(struct sk_buff *skb);
++#endif //LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,35)
++
++#ifdef CONFIG_PROC_DEBUG
++void rtw_proc_init_one(struct net_device *dev);
++void rtw_proc_remove_one(struct net_device *dev);
++#else //!CONFIG_PROC_DEBUG
++static void rtw_proc_init_one(struct net_device *dev){}
++static void rtw_proc_remove_one(struct net_device *dev){}
++#endif //!CONFIG_PROC_DEBUG
++#endif //PLATFORM_LINUX
++
++
++#ifdef PLATFORM_FREEBSD
++extern int rtw_ioctl(struct ifnet * ifp, u_long cmd, caddr_t data);
++#endif
++
++void rtw_ips_dev_unload(_adapter *padapter);
++#ifdef CONFIG_IPS
++int rtw_ips_pwr_up(_adapter *padapter);
++void rtw_ips_pwr_down(_adapter *padapter);
++#endif
++
++#ifdef CONFIG_CONCURRENT_MODE
++struct _io_ops;
++_adapter *rtw_drv_if2_init(_adapter *primary_padapter, void (*set_intf_ops)(struct _io_ops *pops));
++void rtw_drv_if2_free(_adapter *if2);
++void rtw_drv_if2_stop(_adapter *if2);
++#ifdef CONFIG_MULTI_VIR_IFACES
++struct dvobj_priv;
++_adapter *rtw_drv_add_vir_if(_adapter *primary_padapter, void (*set_intf_ops)(struct _io_ops *pops));
++void rtw_drv_stop_vir_ifaces(struct dvobj_priv *dvobj);
++void rtw_drv_free_vir_ifaces(struct dvobj_priv *dvobj);
++#endif //CONFIG_MULTI_VIR_IFACES
++#endif
++
++int rtw_drv_register_netdev(_adapter *padapter);
++void rtw_ndev_destructor(_nic_hdl ndev);
++
++#endif //_OSDEP_INTF_H_
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/osdep_service.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/osdep_service.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/osdep_service.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/osdep_service.h 2015-07-28 01:20:58.317611539 +0200
+@@ -0,0 +1,1813 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef __OSDEP_SERVICE_H_
++#define __OSDEP_SERVICE_H_
++
++#include <drv_conf.h>
++#include <basic_types.h>
++//#include <rtl871x_byteorder.h>
++
++#define _FAIL 0
++#define _SUCCESS 1
++#define RTW_RX_HANDLED 2
++//#define RTW_STATUS_TIMEDOUT -110
++
++#undef _TRUE
++#define _TRUE 1
++
++#undef _FALSE
++#define _FALSE 0
++
++
++#ifdef PLATFORM_FREEBSD
++#include <sys/cdefs.h>
++#include <sys/types.h>
++#include <sys/systm.h>
++#include <sys/param.h>
++#include <sys/sockio.h>
++#include <sys/sysctl.h>
++#include <sys/lock.h>
++#include <sys/mutex.h>
++#include <sys/mbuf.h>
++#include <sys/kernel.h>
++#include <sys/socket.h>
++#include <sys/systm.h>
++#include <sys/malloc.h>
++#include <sys/module.h>
++#include <sys/bus.h>
++#include <sys/endian.h>
++#include <sys/kdb.h>
++#include <sys/kthread.h>
++#include <machine/atomic.h>
++
++#include <machine/bus.h>
++#include <machine/resource.h>
++#include <sys/rman.h>
++
++#include <net/bpf.h>
++#include <net/if.h>
++#include <net/if_arp.h>
++#include <net/ethernet.h>
++#include <net/if_dl.h>
++#include <net/if_media.h>
++#include <net/if_types.h>
++#include <net/route.h>
++
++
++#include <netinet/in.h>
++#include <netinet/in_systm.h>
++#include <netinet/in_var.h>
++#include <netinet/if_ether.h>
++
++#include <net80211/ieee80211_var.h>
++#include <net80211/ieee80211_regdomain.h>
++#include <net80211/ieee80211_radiotap.h>
++#include <net80211/ieee80211_ratectl.h>
++
++#include <dev/usb/usb.h>
++#include <dev/usb/usbdi.h>
++#include "usbdevs.h"
++
++#define USB_DEBUG_VAR rum_debug
++#include <dev/usb/usb_debug.h>
++
++#if 1 //Baron porting from linux, it's all temp solution, needs to check again
++#include <sys/sema.h>
++#include <sys/pcpu.h> /* XXX for PCPU_GET */
++// typedef struct semaphore _sema;
++ typedef struct sema _sema;
++// typedef spinlock_t _lock;
++ typedef struct mtx _lock;
++ typedef struct mtx _mutex;
++ typedef struct timer_list _timer;
++ struct list_head {
++ struct list_head *next, *prev;
++ };
++ struct __queue {
++ struct list_head queue;
++ _lock lock;
++ };
++
++ //typedef struct sk_buff _pkt;
++ typedef struct mbuf _pkt;
++ typedef struct mbuf _buffer;
++
++ typedef struct __queue _queue;
++ typedef struct list_head _list;
++ typedef int _OS_STATUS;
++ //typedef u32 _irqL;
++ typedef unsigned long _irqL;
++ typedef struct ifnet * _nic_hdl;
++
++ typedef pid_t _thread_hdl_;
++// typedef struct thread _thread_hdl_;
++ typedef void thread_return;
++ typedef void* thread_context;
++
++ //#define thread_exit() complete_and_exit(NULL, 0)
++
++ typedef void timer_hdl_return;
++ typedef void* timer_hdl_context;
++ typedef struct work_struct _workitem;
++
++#define KERNEL_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c))
++/* emulate a modern version */
++#define LINUX_VERSION_CODE KERNEL_VERSION(2, 6, 35)
++
++#define WIRELESS_EXT -1
++#define HZ hz
++#define spin_lock_irqsave mtx_lock_irqsave
++#define spin_lock_bh mtx_lock_irqsave
++#define mtx_lock_irqsave(lock, x) mtx_lock(lock)//{local_irq_save((x)); mtx_lock_spin((lock));}
++//#define IFT_RTW 0xf9 //ifnet allocate type for RTW
++#define free_netdev if_free
++#define LIST_CONTAINOR(ptr, type, member) \
++ ((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member)))
++#define container_of(p,t,n) (t*)((p)-&(((t*)0)->n))
++/*
++ * Linux timers are emulated using FreeBSD callout functions
++ * (and taskqueue functionality).
++ *
++ * Currently no timer stats functionality.
++ *
++ * See (linux_compat) processes.c
++ *
++ */
++struct timer_list {
++
++ /* FreeBSD callout related fields */
++ struct callout callout;
++
++ //timeout function
++ void (*function)(void*);
++ //argument
++ void *arg;
++
++};
++struct workqueue_struct;
++struct work_struct;
++typedef void (*work_func_t)(struct work_struct *work);
++/* Values for the state of an item of work (work_struct) */
++typedef enum work_state {
++ WORK_STATE_UNSET = 0,
++ WORK_STATE_CALLOUT_PENDING = 1,
++ WORK_STATE_TASK_PENDING = 2,
++ WORK_STATE_WORK_CANCELLED = 3
++} work_state_t;
++
++struct work_struct {
++ struct task task; /* FreeBSD task */
++ work_state_t state; /* the pending or otherwise state of work. */
++ work_func_t func;
++};
++#define spin_unlock_irqrestore mtx_unlock_irqrestore
++#define spin_unlock_bh mtx_unlock_irqrestore
++#define mtx_unlock_irqrestore(lock,x) mtx_unlock(lock);
++extern void _rtw_spinlock_init(_lock *plock);
++
++//modify private structure to match freebsd
++#define BITS_PER_LONG 32
++union ktime {
++ s64 tv64;
++#if BITS_PER_LONG != 64 && !defined(CONFIG_KTIME_SCALAR)
++ struct {
++#ifdef __BIG_ENDIAN
++ s32 sec, nsec;
++#else
++ s32 nsec, sec;
++#endif
++ } tv;
++#endif
++};
++#define kmemcheck_bitfield_begin(name)
++#define kmemcheck_bitfield_end(name)
++#define CHECKSUM_NONE 0
++typedef unsigned char *sk_buff_data_t;
++typedef union ktime ktime_t; /* Kill this */
++
++void rtw_mtx_lock(_lock *plock);
++
++void rtw_mtx_unlock(_lock *plock);
++
++/**
++ * struct sk_buff - socket buffer
++ * @next: Next buffer in list
++ * @prev: Previous buffer in list
++ * @sk: Socket we are owned by
++ * @tstamp: Time we arrived
++ * @dev: Device we arrived on/are leaving by
++ * @transport_header: Transport layer header
++ * @network_header: Network layer header
++ * @mac_header: Link layer header
++ * @_skb_refdst: destination entry (with norefcount bit)
++ * @sp: the security path, used for xfrm
++ * @cb: Control buffer. Free for use by every layer. Put private vars here
++ * @len: Length of actual data
++ * @data_len: Data length
++ * @mac_len: Length of link layer header
++ * @hdr_len: writable header length of cloned skb
++ * @csum: Checksum (must include start/offset pair)
++ * @csum_start: Offset from skb->head where checksumming should start
++ * @csum_offset: Offset from csum_start where checksum should be stored
++ * @local_df: allow local fragmentation
++ * @cloned: Head may be cloned (check refcnt to be sure)
++ * @nohdr: Payload reference only, must not modify header
++ * @pkt_type: Packet class
++ * @fclone: skbuff clone status
++ * @ip_summed: Driver fed us an IP checksum
++ * @priority: Packet queueing priority
++ * @users: User count - see {datagram,tcp}.c
++ * @protocol: Packet protocol from driver
++ * @truesize: Buffer size
++ * @head: Head of buffer
++ * @data: Data head pointer
++ * @tail: Tail pointer
++ * @end: End pointer
++ * @destructor: Destruct function
++ * @mark: Generic packet mark
++ * @nfct: Associated connection, if any
++ * @ipvs_property: skbuff is owned by ipvs
++ * @peeked: this packet has been seen already, so stats have been
++ * done for it, don't do them again
++ * @nf_trace: netfilter packet trace flag
++ * @nfctinfo: Relationship of this skb to the connection
++ * @nfct_reasm: netfilter conntrack re-assembly pointer
++ * @nf_bridge: Saved data about a bridged frame - see br_netfilter.c
++ * @skb_iif: ifindex of device we arrived on
++ * @rxhash: the packet hash computed on receive
++ * @queue_mapping: Queue mapping for multiqueue devices
++ * @tc_index: Traffic control index
++ * @tc_verd: traffic control verdict
++ * @ndisc_nodetype: router type (from link layer)
++ * @dma_cookie: a cookie to one of several possible DMA operations
++ * done by skb DMA functions
++ * @secmark: security marking
++ * @vlan_tci: vlan tag control information
++ */
++
++struct sk_buff {
++ /* These two members must be first. */
++ struct sk_buff *next;
++ struct sk_buff *prev;
++
++ ktime_t tstamp;
++
++ struct sock *sk;
++ //struct net_device *dev;
++ struct ifnet *dev;
++
++ /*
++ * This is the control buffer. It is free to use for every
++ * layer. Please put your private variables there. If you
++ * want to keep them across layers you have to do a skb_clone()
++ * first. This is owned by whoever has the skb queued ATM.
++ */
++ char cb[48] __aligned(8);
++
++ unsigned long _skb_refdst;
++#ifdef CONFIG_XFRM
++ struct sec_path *sp;
++#endif
++ unsigned int len,
++ data_len;
++ u16 mac_len,
++ hdr_len;
++ union {
++ u32 csum;
++ struct {
++ u16 csum_start;
++ u16 csum_offset;
++ }smbol2;
++ }smbol1;
++ u32 priority;
++ kmemcheck_bitfield_begin(flags1);
++ u8 local_df:1,
++ cloned:1,
++ ip_summed:2,
++ nohdr:1,
++ nfctinfo:3;
++ u8 pkt_type:3,
++ fclone:2,
++ ipvs_property:1,
++ peeked:1,
++ nf_trace:1;
++ kmemcheck_bitfield_end(flags1);
++ u16 protocol;
++
++ void (*destructor)(struct sk_buff *skb);
++#if defined(CONFIG_NF_CONNTRACK) || defined(CONFIG_NF_CONNTRACK_MODULE)
++ struct nf_conntrack *nfct;
++ struct sk_buff *nfct_reasm;
++#endif
++#ifdef CONFIG_BRIDGE_NETFILTER
++ struct nf_bridge_info *nf_bridge;
++#endif
++
++ int skb_iif;
++#ifdef CONFIG_NET_SCHED
++ u16 tc_index; /* traffic control index */
++#ifdef CONFIG_NET_CLS_ACT
++ u16 tc_verd; /* traffic control verdict */
++#endif
++#endif
++
++ u32 rxhash;
++
++ kmemcheck_bitfield_begin(flags2);
++ u16 queue_mapping:16;
++#ifdef CONFIG_IPV6_NDISC_NODETYPE
++ u8 ndisc_nodetype:2,
++ deliver_no_wcard:1;
++#else
++ u8 deliver_no_wcard:1;
++#endif
++ kmemcheck_bitfield_end(flags2);
++
++ /* 0/14 bit hole */
++
++#ifdef CONFIG_NET_DMA
++ dma_cookie_t dma_cookie;
++#endif
++#ifdef CONFIG_NETWORK_SECMARK
++ u32 secmark;
++#endif
++ union {
++ u32 mark;
++ u32 dropcount;
++ }symbol3;
++
++ u16 vlan_tci;
++
++ sk_buff_data_t transport_header;
++ sk_buff_data_t network_header;
++ sk_buff_data_t mac_header;
++ /* These elements must be at the end, see alloc_skb() for details. */
++ sk_buff_data_t tail;
++ sk_buff_data_t end;
++ unsigned char *head,
++ *data;
++ unsigned int truesize;
++ atomic_t users;
++};
++struct sk_buff_head {
++ /* These two members must be first. */
++ struct sk_buff *next;
++ struct sk_buff *prev;
++
++ u32 qlen;
++ _lock lock;
++};
++#define skb_tail_pointer(skb) skb->tail
++static inline unsigned char *skb_put(struct sk_buff *skb, unsigned int len)
++{
++ unsigned char *tmp = skb_tail_pointer(skb);
++ //SKB_LINEAR_ASSERT(skb);
++ skb->tail += len;
++ skb->len += len;
++ return tmp;
++}
++
++static inline unsigned char *__skb_pull(struct sk_buff *skb, unsigned int len)
++{
++ skb->len -= len;
++ if(skb->len < skb->data_len)
++ printf("%s(),%d,error!\n",__FUNCTION__,__LINE__);
++ return skb->data += len;
++}
++static inline unsigned char *skb_pull(struct sk_buff *skb, unsigned int len)
++{
++ #ifdef PLATFORM_FREEBSD
++ return __skb_pull(skb, len);
++ #else
++ return unlikely(len > skb->len) ? NULL : __skb_pull(skb, len);
++ #endif //PLATFORM_FREEBSD
++}
++static inline u32 skb_queue_len(const struct sk_buff_head *list_)
++{
++ return list_->qlen;
++}
++static inline void __skb_insert(struct sk_buff *newsk,
++ struct sk_buff *prev, struct sk_buff *next,
++ struct sk_buff_head *list)
++{
++ newsk->next = next;
++ newsk->prev = prev;
++ next->prev = prev->next = newsk;
++ list->qlen++;
++}
++static inline void __skb_queue_before(struct sk_buff_head *list,
++ struct sk_buff *next,
++ struct sk_buff *newsk)
++{
++ __skb_insert(newsk, next->prev, next, list);
++}
++static inline void skb_queue_tail(struct sk_buff_head *list,
++ struct sk_buff *newsk)
++{
++ mtx_lock(&list->lock);
++ __skb_queue_before(list, (struct sk_buff *)list, newsk);
++ mtx_unlock(&list->lock);
++}
++static inline struct sk_buff *skb_peek(struct sk_buff_head *list_)
++{
++ struct sk_buff *list = ((struct sk_buff *)list_)->next;
++ if (list == (struct sk_buff *)list_)
++ list = NULL;
++ return list;
++}
++static inline void __skb_unlink(struct sk_buff *skb, struct sk_buff_head *list)
++{
++ struct sk_buff *next, *prev;
++
++ list->qlen--;
++ next = skb->next;
++ prev = skb->prev;
++ skb->next = skb->prev = NULL;
++ next->prev = prev;
++ prev->next = next;
++}
++
++static inline struct sk_buff *skb_dequeue(struct sk_buff_head *list)
++{
++ mtx_lock(&list->lock);
++
++ struct sk_buff *skb = skb_peek(list);
++ if (skb)
++ __skb_unlink(skb, list);
++
++ mtx_unlock(&list->lock);
++
++ return skb;
++}
++static inline void skb_reserve(struct sk_buff *skb, int len)
++{
++ skb->data += len;
++ skb->tail += len;
++}
++static inline void __skb_queue_head_init(struct sk_buff_head *list)
++{
++ list->prev = list->next = (struct sk_buff *)list;
++ list->qlen = 0;
++}
++/*
++ * This function creates a split out lock class for each invocation;
++ * this is needed for now since a whole lot of users of the skb-queue
++ * infrastructure in drivers have different locking usage (in hardirq)
++ * than the networking core (in softirq only). In the long run either the
++ * network layer or drivers should need annotation to consolidate the
++ * main types of usage into 3 classes.
++ */
++static inline void skb_queue_head_init(struct sk_buff_head *list)
++{
++ _rtw_spinlock_init(&list->lock);
++ __skb_queue_head_init(list);
++}
++unsigned long copy_from_user(void *to, const void *from, unsigned long n);
++unsigned long copy_to_user(void *to, const void *from, unsigned long n);
++struct sk_buff * dev_alloc_skb(unsigned int size);
++struct sk_buff *skb_clone(const struct sk_buff *skb);
++void dev_kfree_skb_any(struct sk_buff *skb);
++#endif //Baron porting from linux, it's all temp solution, needs to check again
++
++
++#if 1 // kenny add Linux compatibility code for Linux USB driver
++#include <dev/usb/usb_compat_linux.h>
++
++#define __init // __attribute ((constructor))
++#define __exit // __attribute ((destructor))
++
++/*
++ * Definitions for module_init and module_exit macros.
++ *
++ * These macros will use the SYSINIT framework to call a specified
++ * function (with no arguments) on module loading or unloading.
++ *
++ */
++
++void module_init_exit_wrapper(void *arg);
++
++#define module_init(initfn) \
++ SYSINIT(mod_init_ ## initfn, \
++ SI_SUB_KLD, SI_ORDER_FIRST, \
++ module_init_exit_wrapper, initfn)
++
++#define module_exit(exitfn) \
++ SYSUNINIT(mod_exit_ ## exitfn, \
++ SI_SUB_KLD, SI_ORDER_ANY, \
++ module_init_exit_wrapper, exitfn)
++
++/*
++ * The usb_register and usb_deregister functions are used to register
++ * usb drivers with the usb subsystem.
++ */
++int usb_register(struct usb_driver *driver);
++int usb_deregister(struct usb_driver *driver);
++
++/*
++ * usb_get_dev and usb_put_dev - increment/decrement the reference count
++ * of the usb device structure.
++ *
++ * Original body of usb_get_dev:
++ *
++ * if (dev)
++ * get_device(&dev->dev);
++ * return dev;
++ *
++ * Reference counts are not currently used in this compatibility
++ * layer. So these functions will do nothing.
++ */
++static inline struct usb_device *
++usb_get_dev(struct usb_device *dev)
++{
++ return dev;
++}
++
++static inline void
++usb_put_dev(struct usb_device *dev)
++{
++ return;
++}
++
++
++// rtw_usb_compat_linux
++int rtw_usb_submit_urb(struct urb *urb, uint16_t mem_flags);
++int rtw_usb_unlink_urb(struct urb *urb);
++int rtw_usb_clear_halt(struct usb_device *dev, struct usb_host_endpoint *uhe);
++int rtw_usb_control_msg(struct usb_device *dev, struct usb_host_endpoint *uhe,
++ uint8_t request, uint8_t requesttype,
++ uint16_t value, uint16_t index, void *data,
++ uint16_t size, usb_timeout_t timeout);
++int rtw_usb_set_interface(struct usb_device *dev, uint8_t iface_no, uint8_t alt_index);
++int rtw_usb_setup_endpoint(struct usb_device *dev,
++ struct usb_host_endpoint *uhe, usb_size_t bufsize);
++struct urb *rtw_usb_alloc_urb(uint16_t iso_packets, uint16_t mem_flags);
++struct usb_host_endpoint *rtw_usb_find_host_endpoint(struct usb_device *dev, uint8_t type, uint8_t ep);
++struct usb_host_interface *rtw_usb_altnum_to_altsetting(const struct usb_interface *intf, uint8_t alt_index);
++struct usb_interface *rtw_usb_ifnum_to_if(struct usb_device *dev, uint8_t iface_no);
++void *rtw_usb_buffer_alloc(struct usb_device *dev, usb_size_t size, uint8_t *dma_addr);
++void *rtw_usbd_get_intfdata(struct usb_interface *intf);
++void rtw_usb_linux_register(void *arg);
++void rtw_usb_linux_deregister(void *arg);
++void rtw_usb_linux_free_device(struct usb_device *dev);
++void rtw_usb_buffer_free(struct usb_device *dev, usb_size_t size,
++ void *addr, uint8_t dma_addr);
++void rtw_usb_free_urb(struct urb *urb);
++void rtw_usb_init_urb(struct urb *urb);
++void rtw_usb_kill_urb(struct urb *urb);
++void rtw_usb_set_intfdata(struct usb_interface *intf, void *data);
++void rtw_usb_fill_bulk_urb(struct urb *urb, struct usb_device *udev,
++ struct usb_host_endpoint *uhe, void *buf,
++ int length, usb_complete_t callback, void *arg);
++int rtw_usb_bulk_msg(struct usb_device *udev, struct usb_host_endpoint *uhe,
++ void *data, int len, uint16_t *pactlen, usb_timeout_t timeout);
++void *usb_get_intfdata(struct usb_interface *intf);
++int usb_linux_init_endpoints(struct usb_device *udev);
++
++
++
++typedef struct urb * PURB;
++
++typedef unsigned gfp_t;
++#define __GFP_WAIT ((gfp_t)0x10u) /* Can wait and reschedule? */
++#define __GFP_HIGH ((gfp_t)0x20u) /* Should access emergency pools? */
++#define __GFP_IO ((gfp_t)0x40u) /* Can start physical IO? */
++#define __GFP_FS ((gfp_t)0x80u) /* Can call down to low-level FS? */
++#define __GFP_COLD ((gfp_t)0x100u) /* Cache-cold page required */
++#define __GFP_NOWARN ((gfp_t)0x200u) /* Suppress page allocation failure warning */
++#define __GFP_REPEAT ((gfp_t)0x400u) /* Retry the allocation. Might fail */
++#define __GFP_NOFAIL ((gfp_t)0x800u) /* Retry for ever. Cannot fail */
++#define __GFP_NORETRY ((gfp_t)0x1000u)/* Do not retry. Might fail */
++#define __GFP_NO_GROW ((gfp_t)0x2000u)/* Slab internal usage */
++#define __GFP_COMP ((gfp_t)0x4000u)/* Add compound page metadata */
++#define __GFP_ZERO ((gfp_t)0x8000u)/* Return zeroed page on success */
++#define __GFP_NOMEMALLOC ((gfp_t)0x10000u) /* Don't use emergency reserves */
++#define __GFP_HARDWALL ((gfp_t)0x20000u) /* Enforce hardwall cpuset memory allocs */
++
++/* This equals 0, but use constants in case they ever change */
++#define GFP_NOWAIT (GFP_ATOMIC & ~__GFP_HIGH)
++/* GFP_ATOMIC means both !wait (__GFP_WAIT not set) and use emergency pool */
++#define GFP_ATOMIC (__GFP_HIGH)
++#define GFP_NOIO (__GFP_WAIT)
++#define GFP_NOFS (__GFP_WAIT | __GFP_IO)
++#define GFP_KERNEL (__GFP_WAIT | __GFP_IO | __GFP_FS)
++#define GFP_USER (__GFP_WAIT | __GFP_IO | __GFP_FS | __GFP_HARDWALL)
++#define GFP_HIGHUSER (__GFP_WAIT | __GFP_IO | __GFP_FS | __GFP_HARDWALL | \
++ __GFP_HIGHMEM)
++
++
++#endif // kenny add Linux compatibility code for Linux USB
++
++
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24))
++ #define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1))
++#endif
++
++__inline static _list *get_next(_list *list)
++{
++ return list->next;
++}
++
++__inline static _list *get_list_head(_queue *queue)
++{
++ return (&(queue->queue));
++}
++
++
++#define LIST_CONTAINOR(ptr, type, member) \
++ ((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member)))
++
++
++__inline static void _enter_critical(_lock *plock, _irqL *pirqL)
++{
++ spin_lock_irqsave(plock, *pirqL);
++}
++
++__inline static void _exit_critical(_lock *plock, _irqL *pirqL)
++{
++ spin_unlock_irqrestore(plock, *pirqL);
++}
++
++__inline static void _enter_critical_ex(_lock *plock, _irqL *pirqL)
++{
++ spin_lock_irqsave(plock, *pirqL);
++}
++
++__inline static void _exit_critical_ex(_lock *plock, _irqL *pirqL)
++{
++ spin_unlock_irqrestore(plock, *pirqL);
++}
++
++__inline static void _enter_critical_bh(_lock *plock, _irqL *pirqL)
++{
++ spin_lock_bh(plock, *pirqL);
++}
++
++__inline static void _exit_critical_bh(_lock *plock, _irqL *pirqL)
++{
++ spin_unlock_bh(plock, *pirqL);
++}
++
++__inline static void _enter_critical_mutex(_mutex *pmutex, _irqL *pirqL)
++{
++
++ mtx_lock(pmutex);
++
++}
++
++
++__inline static void _exit_critical_mutex(_mutex *pmutex, _irqL *pirqL)
++{
++
++ mtx_unlock(pmutex);
++
++}
++static inline void __list_del(struct list_head * prev, struct list_head * next)
++{
++ next->prev = prev;
++ prev->next = next;
++}
++static inline void INIT_LIST_HEAD(struct list_head *list)
++{
++ list->next = list;
++ list->prev = list;
++}
++__inline static void rtw_list_delete(_list *plist)
++{
++ __list_del(plist->prev, plist->next);
++ INIT_LIST_HEAD(plist);
++}
++
++__inline static void _init_timer(_timer *ptimer,_nic_hdl padapter,void *pfunc,void* cntx)
++{
++ ptimer->function = pfunc;
++ ptimer->arg = cntx;
++ callout_init(&ptimer->callout, CALLOUT_MPSAFE);
++}
++
++__inline static void _set_timer(_timer *ptimer,u32 delay_time)
++{
++ // mod_timer(ptimer , (jiffies+(delay_time*HZ/1000)));
++ if(ptimer->function && ptimer->arg){
++ rtw_mtx_lock(NULL);
++ callout_reset(&ptimer->callout, delay_time,ptimer->function, ptimer->arg);
++ rtw_mtx_unlock(NULL);
++ }
++}
++
++__inline static void _cancel_timer(_timer *ptimer,u8 *bcancelled)
++{
++ // del_timer_sync(ptimer);
++ // *bcancelled= _TRUE;//TRUE ==1; FALSE==0
++ rtw_mtx_lock(NULL);
++ callout_drain(&ptimer->callout);
++ rtw_mtx_unlock(NULL);
++}
++
++__inline static void _init_workitem(_workitem *pwork, void *pfunc, PVOID cntx)
++{
++ printf("%s Not implement yet! \n",__FUNCTION__);
++}
++
++__inline static void _set_workitem(_workitem *pwork)
++{
++ printf("%s Not implement yet! \n",__FUNCTION__);
++// schedule_work(pwork);
++}
++
++//
++// Global Mutex: can only be used at PASSIVE level.
++//
++
++#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter) \
++{ \
++}
++
++#define RELEASE_GLOBAL_MUTEX(_MutexCounter) \
++{ \
++}
++
++#define ATOMIC_INIT(i) { (i) }
++
++#endif //PLATFORM_FREEBSD
++
++
++#ifdef PLATFORM_LINUX
++ #include <linux/version.h>
++ #include <linux/spinlock.h>
++ #include <linux/compiler.h>
++ #include <linux/kernel.h>
++ #include <linux/errno.h>
++ #include <linux/init.h>
++ #include <linux/slab.h>
++ #include <linux/module.h>
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,5))
++ #include <linux/kref.h>
++#endif
++ //#include <linux/smp_lock.h>
++ #include <linux/netdevice.h>
++ #include <linux/skbuff.h>
++ #include <linux/circ_buf.h>
++ #include <asm/uaccess.h>
++ #include <asm/byteorder.h>
++ #include <asm/atomic.h>
++ #include <asm/io.h>
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26))
++ #include <asm/semaphore.h>
++#else
++ #include <linux/semaphore.h>
++#endif
++ #include <linux/sem.h>
++ #include <linux/sched.h>
++ #include <linux/etherdevice.h>
++ #include <linux/wireless.h>
++ #include <net/iw_handler.h>
++ #include <linux/if_arp.h>
++ #include <linux/rtnetlink.h>
++ #include <linux/delay.h>
++ #include <linux/proc_fs.h> // Necessary because we use the proc fs
++ #include <linux/interrupt.h> // for struct tasklet_struct
++ #include <linux/ip.h>
++ #include <linux/kthread.h>
++
++#ifdef CONFIG_IOCTL_CFG80211
++// #include <linux/ieee80211.h>
++ #include <net/ieee80211_radiotap.h>
++ #include <net/cfg80211.h>
++#endif //CONFIG_IOCTL_CFG80211
++
++#ifdef CONFIG_TCP_CSUM_OFFLOAD_TX
++ #include <linux/in.h>
++ #include <linux/udp.h>
++#endif
++
++#ifdef CONFIG_USB_HCI
++ #include <linux/usb.h>
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21))
++ #include <linux/usb_ch9.h>
++#else
++ #include <linux/usb/ch9.h>
++#endif
++#endif
++
++#ifdef CONFIG_PCI_HCI
++ #include <linux/pci.h>
++#endif
++
++
++#ifdef CONFIG_USB_HCI
++ typedef struct urb * PURB;
++#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,22))
++#ifdef CONFIG_USB_SUSPEND
++#define CONFIG_AUTOSUSPEND 1
++#endif
++#endif
++#endif
++
++ typedef struct semaphore _sema;
++ typedef spinlock_t _lock;
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37))
++ typedef struct mutex _mutex;
++#else
++ typedef struct semaphore _mutex;
++#endif
++ typedef struct timer_list _timer;
++
++ struct __queue {
++ struct list_head queue;
++ _lock lock;
++ };
++
++ typedef struct sk_buff _pkt;
++ typedef unsigned char _buffer;
++
++ typedef struct __queue _queue;
++ typedef struct list_head _list;
++ typedef int _OS_STATUS;
++ //typedef u32 _irqL;
++ typedef unsigned long _irqL;
++ typedef struct net_device * _nic_hdl;
++
++ typedef void* _thread_hdl_;
++ typedef int thread_return;
++ typedef void* thread_context;
++
++ #define thread_exit() complete_and_exit(NULL, 0)
++
++ typedef void timer_hdl_return;
++ typedef void* timer_hdl_context;
++ typedef struct work_struct _workitem;
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24))
++ #define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1))
++#endif
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,22))
++// Porting from linux kernel, for compatible with old kernel.
++static inline unsigned char *skb_tail_pointer(const struct sk_buff *skb)
++{
++ return skb->tail;
++}
++
++static inline void skb_reset_tail_pointer(struct sk_buff *skb)
++{
++ skb->tail = skb->data;
++}
++
++static inline void skb_set_tail_pointer(struct sk_buff *skb, const int offset)
++{
++ skb->tail = skb->data + offset;
++}
++
++static inline unsigned char *skb_end_pointer(const struct sk_buff *skb)
++{
++ return skb->end;
++}
++#endif
++
++__inline static _list *get_next(_list *list)
++{
++ return list->next;
++}
++
++__inline static _list *get_list_head(_queue *queue)
++{
++ return (&(queue->queue));
++}
++
++
++#define LIST_CONTAINOR(ptr, type, member) \
++ ((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member)))
++
++
++__inline static void _enter_critical(_lock *plock, _irqL *pirqL)
++{
++ spin_lock_irqsave(plock, *pirqL);
++}
++
++__inline static void _exit_critical(_lock *plock, _irqL *pirqL)
++{
++ spin_unlock_irqrestore(plock, *pirqL);
++}
++
++__inline static void _enter_critical_ex(_lock *plock, _irqL *pirqL)
++{
++ spin_lock_irqsave(plock, *pirqL);
++}
++
++__inline static void _exit_critical_ex(_lock *plock, _irqL *pirqL)
++{
++ spin_unlock_irqrestore(plock, *pirqL);
++}
++
++__inline static void _enter_critical_bh(_lock *plock, _irqL *pirqL)
++{
++ spin_lock_bh(plock);
++}
++
++__inline static void _exit_critical_bh(_lock *plock, _irqL *pirqL)
++{
++ spin_unlock_bh(plock);
++}
++
++__inline static void _enter_critical_mutex(_mutex *pmutex, _irqL *pirqL)
++{
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37))
++ mutex_lock(pmutex);
++#else
++ down(pmutex);
++#endif
++}
++
++
++__inline static void _exit_critical_mutex(_mutex *pmutex, _irqL *pirqL)
++{
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37))
++ mutex_unlock(pmutex);
++#else
++ up(pmutex);
++#endif
++}
++
++__inline static void rtw_list_delete(_list *plist)
++{
++ list_del_init(plist);
++}
++
++__inline static void _init_timer(_timer *ptimer,_nic_hdl nic_hdl,void *pfunc,void* cntx)
++{
++ //setup_timer(ptimer, pfunc,(u32)cntx);
++ ptimer->function = pfunc;
++ ptimer->data = (unsigned long)cntx;
++ init_timer(ptimer);
++}
++
++__inline static void _set_timer(_timer *ptimer,u32 delay_time)
++{
++ mod_timer(ptimer , (jiffies+(delay_time*HZ/1000)));
++}
++
++__inline static void _cancel_timer(_timer *ptimer,u8 *bcancelled)
++{
++ del_timer_sync(ptimer);
++ *bcancelled= _TRUE;//TRUE ==1; FALSE==0
++}
++
++#ifdef PLATFORM_LINUX
++#define RTW_TIMER_HDL_ARGS void *FunctionContext
++#elif defined(PLATFORM_OS_CE) || defined(PLATFORM_WINDOWS)
++#define RTW_TIMER_HDL_ARGS IN PVOID SystemSpecific1, IN PVOID FunctionContext, IN PVOID SystemSpecific2, IN PVOID SystemSpecific3
++#endif
++
++#define RTW_TIMER_HDL_NAME(name) rtw_##name##_timer_hdl
++#define RTW_DECLARE_TIMER_HDL(name) void RTW_TIMER_HDL_NAME(name)(RTW_TIMER_HDL_ARGS)
++
++
++__inline static void _init_workitem(_workitem *pwork, void *pfunc, PVOID cntx)
++{
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20))
++ INIT_WORK(pwork, pfunc);
++#else
++ INIT_WORK(pwork, pfunc,pwork);
++#endif
++}
++
++__inline static void _set_workitem(_workitem *pwork)
++{
++ schedule_work(pwork);
++}
++
++__inline static void _cancel_workitem_sync(_workitem *pwork)
++{
++#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,22))
++ cancel_work_sync(pwork);
++#else
++ flush_scheduled_work();
++#endif
++}
++
++//
++// Global Mutex: can only be used at PASSIVE level.
++//
++
++#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter) \
++{ \
++ while (atomic_inc_return((atomic_t *)&(_MutexCounter)) != 1)\
++ { \
++ atomic_dec((atomic_t *)&(_MutexCounter)); \
++ msleep(10); \
++ } \
++}
++
++#define RELEASE_GLOBAL_MUTEX(_MutexCounter) \
++{ \
++ atomic_dec((atomic_t *)&(_MutexCounter)); \
++}
++
++static inline int rtw_netif_queue_stopped(struct net_device *pnetdev)
++{
++#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,35))
++ return (netif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 0)) &&
++ netif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 1)) &&
++ netif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 2)) &&
++ netif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 3)) );
++#else
++ return netif_queue_stopped(pnetdev);
++#endif
++}
++
++static inline void rtw_netif_wake_queue(struct net_device *pnetdev)
++{
++#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,35))
++ netif_tx_wake_all_queues(pnetdev);
++#else
++ netif_wake_queue(pnetdev);
++#endif
++}
++
++static inline void rtw_netif_start_queue(struct net_device *pnetdev)
++{
++#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,35))
++ netif_tx_start_all_queues(pnetdev);
++#else
++ netif_start_queue(pnetdev);
++#endif
++}
++
++static inline void rtw_netif_stop_queue(struct net_device *pnetdev)
++{
++#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,35))
++ netif_tx_stop_all_queues(pnetdev);
++#else
++ netif_stop_queue(pnetdev);
++#endif
++}
++
++#endif // PLATFORM_LINUX
++
++
++#ifdef PLATFORM_OS_XP
++
++ #include <ndis.h>
++ #include <ntddk.h>
++ #include <ntddndis.h>
++ #include <ntdef.h>
++
++#ifdef CONFIG_USB_HCI
++ #include <usb.h>
++ #include <usbioctl.h>
++ #include <usbdlib.h>
++#endif
++
++ typedef KSEMAPHORE _sema;
++ typedef LIST_ENTRY _list;
++ typedef NDIS_STATUS _OS_STATUS;
++
++
++ typedef NDIS_SPIN_LOCK _lock;
++
++ typedef KMUTEX _mutex;
++
++ typedef KIRQL _irqL;
++
++ // USB_PIPE for WINCE , but handle can be use just integer under windows
++ typedef NDIS_HANDLE _nic_hdl;
++
++
++ typedef NDIS_MINIPORT_TIMER _timer;
++
++ struct __queue {
++ LIST_ENTRY queue;
++ _lock lock;
++ };
++
++ typedef NDIS_PACKET _pkt;
++ typedef NDIS_BUFFER _buffer;
++ typedef struct __queue _queue;
++
++ typedef PKTHREAD _thread_hdl_;
++ typedef void thread_return;
++ typedef void* thread_context;
++
++ typedef NDIS_WORK_ITEM _workitem;
++
++ #define thread_exit() PsTerminateSystemThread(STATUS_SUCCESS);
++
++ #define HZ 10000000
++ #define SEMA_UPBND (0x7FFFFFFF) //8192
++
++__inline static _list *get_next(_list *list)
++{
++ return list->Flink;
++}
++
++__inline static _list *get_list_head(_queue *queue)
++{
++ return (&(queue->queue));
++}
++
++
++#define LIST_CONTAINOR(ptr, type, member) CONTAINING_RECORD(ptr, type, member)
++
++
++__inline static _enter_critical(_lock *plock, _irqL *pirqL)
++{
++ NdisAcquireSpinLock(plock);
++}
++
++__inline static _exit_critical(_lock *plock, _irqL *pirqL)
++{
++ NdisReleaseSpinLock(plock);
++}
++
++
++__inline static _enter_critical_ex(_lock *plock, _irqL *pirqL)
++{
++ NdisDprAcquireSpinLock(plock);
++}
++
++__inline static _exit_critical_ex(_lock *plock, _irqL *pirqL)
++{
++ NdisDprReleaseSpinLock(plock);
++}
++
++__inline static void _enter_critical_bh(_lock *plock, _irqL *pirqL)
++{
++ NdisDprAcquireSpinLock(plock);
++}
++
++__inline static void _exit_critical_bh(_lock *plock, _irqL *pirqL)
++{
++ NdisDprReleaseSpinLock(plock);
++}
++
++__inline static _enter_critical_mutex(_mutex *pmutex, _irqL *pirqL)
++{
++ KeWaitForSingleObject(pmutex, Executive, KernelMode, FALSE, NULL);
++}
++
++
++__inline static _exit_critical_mutex(_mutex *pmutex, _irqL *pirqL)
++{
++ KeReleaseMutex(pmutex, FALSE);
++}
++
++
++__inline static void rtw_list_delete(_list *plist)
++{
++ RemoveEntryList(plist);
++ InitializeListHead(plist);
++}
++
++__inline static void _init_timer(_timer *ptimer,_nic_hdl nic_hdl,void *pfunc,PVOID cntx)
++{
++ NdisMInitializeTimer(ptimer, nic_hdl, pfunc, cntx);
++}
++
++__inline static void _set_timer(_timer *ptimer,u32 delay_time)
++{
++ NdisMSetTimer(ptimer,delay_time);
++}
++
++__inline static void _cancel_timer(_timer *ptimer,u8 *bcancelled)
++{
++ NdisMCancelTimer(ptimer,bcancelled);
++}
++
++__inline static void _init_workitem(_workitem *pwork, void *pfunc, PVOID cntx)
++{
++
++ NdisInitializeWorkItem(pwork, pfunc, cntx);
++}
++
++__inline static void _set_workitem(_workitem *pwork)
++{
++ NdisScheduleWorkItem(pwork);
++}
++
++
++#define ATOMIC_INIT(i) { (i) }
++
++//
++// Global Mutex: can only be used at PASSIVE level.
++//
++
++#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter) \
++{ \
++ while (NdisInterlockedIncrement((PULONG)&(_MutexCounter)) != 1)\
++ { \
++ NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \
++ NdisMSleep(10000); \
++ } \
++}
++
++#define RELEASE_GLOBAL_MUTEX(_MutexCounter) \
++{ \
++ NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \
++}
++
++#endif // PLATFORM_OS_XP
++
++
++#ifdef PLATFORM_OS_CE
++#include <osdep_ce_service.h>
++#endif
++
++#include <rtw_byteorder.h>
++
++#ifndef BIT
++ #define BIT(x) ( 1 << (x))
++#endif
++
++extern int RTW_STATUS_CODE(int error_code);
++
++#define CONFIG_USE_VMALLOC
++
++/* flags used for rtw_mstat_update() */
++enum mstat_f {
++ /* type: 0x00ff */
++ MSTAT_TYPE_VIR = 0x00,
++ MSTAT_TYPE_PHY= 0x01,
++ MSTAT_TYPE_SKB = 0x02,
++ MSTAT_TYPE_USB = 0x03,
++ MSTAT_TYPE_MAX = 0x04,
++
++ /* func: 0xff00 */
++ MSTAT_FUNC_UNSPECIFIED = 0x00<<8,
++ MSTAT_FUNC_IO = 0x01<<8,
++ MSTAT_FUNC_TX_IO = 0x02<<8,
++ MSTAT_FUNC_RX_IO = 0x03<<8,
++ MSTAT_FUNC_TX = 0x04<<8,
++ MSTAT_FUNC_RX = 0x05<<8,
++ MSTAT_FUNC_MAX = 0x06<<8,
++};
++
++#define mstat_tf_idx(flags) ((flags)&0xff)
++#define mstat_ff_idx(flags) (((flags)&0xff00) >> 8)
++
++typedef enum mstat_status{
++ MSTAT_ALLOC_SUCCESS = 0,
++ MSTAT_ALLOC_FAIL,
++ MSTAT_FREE
++} MSTAT_STATUS;
++
++#ifdef DBG_MEM_ALLOC
++void rtw_mstat_update(const enum mstat_f flags, const MSTAT_STATUS status, u32 sz);
++int _rtw_mstat_dump(char *buf, int len);
++void rtw_mstat_dump (void);
++u8* dbg_rtw_vmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line);
++u8* dbg_rtw_zvmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line);
++void dbg_rtw_vmfree(u8 *pbuf, const enum mstat_f flags, u32 sz, const char *func, const int line);
++u8* dbg_rtw_malloc(u32 sz, const enum mstat_f flags, const char *func, const int line);
++u8* dbg_rtw_zmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line);
++void dbg_rtw_mfree(u8 *pbuf, const enum mstat_f flags, u32 sz, const char *func, const int line);
++
++struct sk_buff * dbg_rtw_skb_alloc(unsigned int size, const enum mstat_f flags, const char *func, const int line);
++void dbg_rtw_skb_free(struct sk_buff *skb, const enum mstat_f flags, const char *func, const int line);
++struct sk_buff *dbg_rtw_skb_copy(const struct sk_buff *skb, const enum mstat_f flags, const char *func, const int line);
++struct sk_buff *dbg_rtw_skb_clone(struct sk_buff *skb, const enum mstat_f flags, const char *func, const int line);
++int dbg_rtw_netif_rx(_nic_hdl ndev, struct sk_buff *skb, const enum mstat_f flags, const char *func, int line);
++void dbg_rtw_skb_queue_purge(struct sk_buff_head *list, enum mstat_f flags, const char *func, int line);
++
++#ifdef CONFIG_USB_HCI
++void *dbg_rtw_usb_buffer_alloc(struct usb_device *dev, size_t size, dma_addr_t *dma, const enum mstat_f flags, const char *func, const int line);
++void dbg_rtw_usb_buffer_free(struct usb_device *dev, size_t size, void *addr, dma_addr_t dma, const enum mstat_f flags, const char *func, const int line);
++#endif /* CONFIG_USB_HCI */
++
++#ifdef CONFIG_USE_VMALLOC
++#define rtw_vmalloc(sz) dbg_rtw_vmalloc((sz), MSTAT_TYPE_VIR, __FUNCTION__, __LINE__)
++#define rtw_zvmalloc(sz) dbg_rtw_zvmalloc((sz), MSTAT_TYPE_VIR, __FUNCTION__, __LINE__)
++#define rtw_vmfree(pbuf, sz) dbg_rtw_vmfree((pbuf), (sz), MSTAT_TYPE_VIR, __FUNCTION__, __LINE__)
++#define rtw_vmalloc_f(sz, mstat_f) dbg_rtw_vmalloc((sz), ((mstat_f)&0xff00)|MSTAT_TYPE_VIR, __FUNCTION__, __LINE__)
++#define rtw_zvmalloc_f(sz, mstat_f) dbg_rtw_zvmalloc((sz), ((mstat_f)&0xff00)|MSTAT_TYPE_VIR, __FUNCTION__, __LINE__)
++#define rtw_vmfree_f(pbuf, sz, mstat_f) dbg_rtw_vmfree((pbuf), (sz), ((mstat_f)&0xff00)|MSTAT_TYPE_VIR, __FUNCTION__, __LINE__)
++#else /* CONFIG_USE_VMALLOC */
++#define rtw_vmalloc(sz) dbg_rtw_malloc((sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
++#define rtw_zvmalloc(sz) dbg_rtw_zmalloc((sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
++#define rtw_vmfree(pbuf, sz) dbg_rtw_mfree((pbuf), (sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
++#define rtw_vmalloc_f(sz, mstat_f) dbg_rtw_malloc((sz), ((mstat_f)&0xff00)|MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
++#define rtw_zvmalloc_f(sz, mstat_f) dbg_rtw_zmalloc((sz), ((mstat_f)&0xff00)|MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
++#define rtw_vmfree_f(pbuf, sz, mstat_f) dbg_rtw_mfree((pbuf), (sz), ((mstat_f)&0xff00)|MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
++#endif /* CONFIG_USE_VMALLOC */
++#define rtw_malloc(sz) dbg_rtw_malloc((sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
++#define rtw_zmalloc(sz) dbg_rtw_zmalloc((sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
++#define rtw_mfree(pbuf, sz) dbg_rtw_mfree((pbuf), (sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
++#define rtw_malloc_f(sz, mstat_f) dbg_rtw_malloc((sz), ((mstat_f)&0xff00)|MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
++#define rtw_zmalloc_f(sz, mstat_f) dbg_rtw_zmalloc((sz), ((mstat_f)&0xff00)|MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
++#define rtw_mfree_f(pbuf, sz, mstat_f) dbg_rtw_mfree((pbuf), (sz), ((mstat_f)&0xff00)|MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
++
++#define rtw_skb_alloc(size) dbg_rtw_skb_alloc((size), MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
++#define rtw_skb_free(skb) dbg_rtw_skb_free((skb), MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
++#define rtw_skb_alloc_f(size, mstat_f) dbg_rtw_skb_alloc((size), ((mstat_f)&0xff00)|MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
++#define rtw_skb_free_f(skb, mstat_f) dbg_rtw_skb_free((skb), ((mstat_f)&0xff00)|MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
++#define rtw_skb_copy(skb) dbg_rtw_skb_copy((skb), MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
++#define rtw_skb_clone(skb) dbg_rtw_skb_clone((skb), MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
++#define rtw_skb_copy_f(skb, mstat_f) dbg_rtw_skb_copy((skb), ((mstat_f)&0xff00)|MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
++#define rtw_skb_clone_f(skb, mstat_f) dbg_rtw_skb_clone((skb), ((mstat_f)&0xff00)|MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
++#define rtw_netif_rx(ndev, skb) dbg_rtw_netif_rx(ndev, skb, MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
++#define rtw_skb_queue_purge(sk_buff_head) dbg_rtw_skb_queue_purge(sk_buff_head, MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
++#ifdef CONFIG_USB_HCI
++#define rtw_usb_buffer_alloc(dev, size, dma) dbg_rtw_usb_buffer_alloc((dev), (size), (dma), MSTAT_TYPE_USB, __FUNCTION__, __LINE__)
++#define rtw_usb_buffer_free(dev, size, addr, dma) dbg_rtw_usb_buffer_free((dev), (size), (addr), (dma), MSTAT_TYPE_USB, __FUNCTION__, __LINE__)
++#define rtw_usb_buffer_alloc_f(dev, size, dma, mstat_f) dbg_rtw_usb_buffer_alloc((dev), (size), (dma), ((mstat_f)&0xff00)|MSTAT_TYPE_USB, __FUNCTION__, __LINE__)
++#define rtw_usb_buffer_free_f(dev, size, addr, dma, mstat_f) dbg_rtw_usb_buffer_free((dev), (size), (addr), (dma), ((mstat_f)&0xff00)|MSTAT_TYPE_USB, __FUNCTION__, __LINE__)
++#endif /* CONFIG_USB_HCI */
++
++#else /* DBG_MEM_ALLOC */
++#define rtw_mstat_update(flag, status, sz) do {} while(0)
++#define rtw_mstat_dump() do {} while(0)
++u8* _rtw_vmalloc(u32 sz);
++u8* _rtw_zvmalloc(u32 sz);
++void _rtw_vmfree(u8 *pbuf, u32 sz);
++u8* _rtw_zmalloc(u32 sz);
++u8* _rtw_malloc(u32 sz);
++void _rtw_mfree(u8 *pbuf, u32 sz);
++
++struct sk_buff *_rtw_skb_alloc(u32 sz);
++void _rtw_skb_free(struct sk_buff *skb);
++struct sk_buff *_rtw_skb_copy(const struct sk_buff *skb);
++struct sk_buff *_rtw_skb_clone(struct sk_buff *skb);
++int _rtw_netif_rx(_nic_hdl ndev, struct sk_buff *skb);
++void _rtw_skb_queue_purge(struct sk_buff_head *list);
++
++#ifdef CONFIG_USB_HCI
++void *_rtw_usb_buffer_alloc(struct usb_device *dev, size_t size, dma_addr_t *dma);
++void _rtw_usb_buffer_free(struct usb_device *dev, size_t size, void *addr, dma_addr_t dma);
++#endif /* CONFIG_USB_HCI */
++
++#ifdef CONFIG_USE_VMALLOC
++#define rtw_vmalloc(sz) _rtw_vmalloc((sz))
++#define rtw_zvmalloc(sz) _rtw_zvmalloc((sz))
++#define rtw_vmfree(pbuf, sz) _rtw_vmfree((pbuf), (sz))
++#define rtw_vmalloc_f(sz, mstat_f) _rtw_vmalloc((sz))
++#define rtw_zvmalloc_f(sz, mstat_f) _rtw_zvmalloc((sz))
++#define rtw_vmfree_f(pbuf, sz, mstat_f) _rtw_vmfree((pbuf), (sz))
++#else /* CONFIG_USE_VMALLOC */
++#define rtw_vmalloc(sz) _rtw_malloc((sz))
++#define rtw_zvmalloc(sz) _rtw_zmalloc((sz))
++#define rtw_vmfree(pbuf, sz) _rtw_mfree((pbuf), (sz))
++#define rtw_vmalloc_f(sz, mstat_f) _rtw_malloc((sz))
++#define rtw_zvmalloc_f(sz, mstat_f) _rtw_zmalloc((sz))
++#define rtw_vmfree_f(pbuf, sz, mstat_f) _rtw_mfree((pbuf), (sz))
++#endif /* CONFIG_USE_VMALLOC */
++#define rtw_malloc(sz) _rtw_malloc((sz))
++#define rtw_zmalloc(sz) _rtw_zmalloc((sz))
++#define rtw_mfree(pbuf, sz) _rtw_mfree((pbuf), (sz))
++#define rtw_malloc_f(sz, mstat_f) _rtw_malloc((sz))
++#define rtw_zmalloc_f(sz, mstat_f) _rtw_zmalloc((sz))
++#define rtw_mfree_f(pbuf, sz, mstat_f) _rtw_mfree((pbuf), (sz))
++
++#define rtw_skb_alloc(size) _rtw_skb_alloc((size))
++#define rtw_skb_free(skb) _rtw_skb_free((skb))
++#define rtw_skb_alloc_f(size, mstat_f) _rtw_skb_alloc((size))
++#define rtw_skb_free_f(skb, mstat_f) _rtw_skb_free((skb))
++#define rtw_skb_copy(skb) _rtw_skb_copy((skb))
++#define rtw_skb_clone(skb) _rtw_skb_clone((skb))
++#define rtw_skb_copy_f(skb, mstat_f) _rtw_skb_copy((skb))
++#define rtw_skb_clone_f(skb, mstat_f) _rtw_skb_clone((skb))
++#define rtw_netif_rx(ndev, skb) _rtw_netif_rx(ndev, skb)
++#define rtw_skb_queue_purge(sk_buff_head) _rtw_skb_queue_purge(sk_buff_head)
++#ifdef CONFIG_USB_HCI
++#define rtw_usb_buffer_alloc(dev, size, dma) _rtw_usb_buffer_alloc((dev), (size), (dma))
++#define rtw_usb_buffer_free(dev, size, addr, dma) _rtw_usb_buffer_free((dev), (size), (addr), (dma))
++#define rtw_usb_buffer_alloc_f(dev, size, dma, mstat_f) _rtw_usb_buffer_alloc((dev), (size), (dma))
++#define rtw_usb_buffer_free_f(dev, size, addr, dma, mstat_f) _rtw_usb_buffer_free((dev), (size), (addr), (dma))
++#endif /* CONFIG_USB_HCI */
++#endif /* DBG_MEM_ALLOC */
++
++extern void* rtw_malloc2d(int h, int w, int size);
++extern void rtw_mfree2d(void *pbuf, int h, int w, int size);
++
++extern void _rtw_memcpy(void* dec, void* sour, u32 sz);
++extern int _rtw_memcmp(void *dst, void *src, u32 sz);
++extern void _rtw_memset(void *pbuf, int c, u32 sz);
++
++extern void _rtw_init_listhead(_list *list);
++extern u32 rtw_is_list_empty(_list *phead);
++extern void rtw_list_insert_head(_list *plist, _list *phead);
++extern void rtw_list_insert_tail(_list *plist, _list *phead);
++#ifndef PLATFORM_FREEBSD
++extern void rtw_list_delete(_list *plist);
++#endif //PLATFORM_FREEBSD
++
++extern void _rtw_init_sema(_sema *sema, int init_val);
++extern void _rtw_free_sema(_sema *sema);
++extern void _rtw_up_sema(_sema *sema);
++extern u32 _rtw_down_sema(_sema *sema);
++extern void _rtw_mutex_init(_mutex *pmutex);
++extern void _rtw_mutex_free(_mutex *pmutex);
++#ifndef PLATFORM_FREEBSD
++extern void _rtw_spinlock_init(_lock *plock);
++#endif //PLATFORM_FREEBSD
++extern void _rtw_spinlock_free(_lock *plock);
++extern void _rtw_spinlock(_lock *plock);
++extern void _rtw_spinunlock(_lock *plock);
++extern void _rtw_spinlock_ex(_lock *plock);
++extern void _rtw_spinunlock_ex(_lock *plock);
++
++extern void _rtw_init_queue(_queue *pqueue);
++extern u32 _rtw_queue_empty(_queue *pqueue);
++extern u32 rtw_end_of_queue_search(_list *queue, _list *pelement);
++
++extern u32 rtw_get_current_time(void);
++extern u32 rtw_systime_to_ms(u32 systime);
++extern u32 rtw_ms_to_systime(u32 ms);
++extern s32 rtw_get_passing_time_ms(u32 start);
++extern s32 rtw_get_time_interval_ms(u32 start, u32 end);
++
++extern void rtw_sleep_schedulable(int ms);
++
++extern void rtw_msleep_os(int ms);
++extern void rtw_usleep_os(int us);
++
++extern u32 rtw_atoi(u8* s);
++
++#ifdef DBG_DELAY_OS
++#define rtw_mdelay_os(ms) _rtw_mdelay_os((ms), __FUNCTION__, __LINE__)
++#define rtw_udelay_os(ms) _rtw_udelay_os((ms), __FUNCTION__, __LINE__)
++extern void _rtw_mdelay_os(int ms, const char *func, const int line);
++extern void _rtw_udelay_os(int us, const char *func, const int line);
++#else
++extern void rtw_mdelay_os(int ms);
++extern void rtw_udelay_os(int us);
++#endif
++
++extern void rtw_yield_os(void);
++
++
++__inline static unsigned char _cancel_timer_ex(_timer *ptimer)
++{
++#ifdef PLATFORM_LINUX
++ return del_timer_sync(ptimer);
++#endif
++#ifdef PLATFORM_FREEBSD
++ _cancel_timer(ptimer,0);
++ return 0;
++#endif
++#ifdef PLATFORM_WINDOWS
++ u8 bcancelled;
++
++ _cancel_timer(ptimer, &bcancelled);
++
++ return bcancelled;
++#endif
++}
++
++#ifdef PLATFORM_FREEBSD
++static __inline void thread_enter(void *context);
++#endif //PLATFORM_FREEBSD
++static __inline void thread_enter(char *name)
++{
++#ifdef PLATFORM_LINUX
++ #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0))
++ daemonize("%s", name);
++ #endif
++ allow_signal(SIGTERM);
++#endif
++#ifdef PLATFORM_FREEBSD
++ printf("%s", "RTKTHREAD_enter");
++#endif
++}
++
++#ifdef PLATFORM_FREEBSD
++#define thread_exit() do{printf("%s", "RTKTHREAD_exit");}while(0)
++#endif //PLATFORM_FREEBSD
++__inline static void flush_signals_thread(void)
++{
++#ifdef PLATFORM_LINUX
++ if (signal_pending (current))
++ {
++ flush_signals(current);
++ }
++#endif
++}
++
++__inline static _OS_STATUS res_to_status(sint res)
++{
++
++
++#if defined (PLATFORM_LINUX) || defined (PLATFORM_MPIXEL) || defined (PLATFORM_FREEBSD)
++ return res;
++#endif
++
++#ifdef PLATFORM_WINDOWS
++
++ if (res == _SUCCESS)
++ return NDIS_STATUS_SUCCESS;
++ else
++ return NDIS_STATUS_FAILURE;
++
++#endif
++
++}
++
++__inline static void rtw_dump_stack(void)
++{
++#ifdef PLATFORM_LINUX
++ dump_stack();
++#endif
++}
++
++#ifdef PLATFORM_LINUX
++#define rtw_warn_on(condition) WARN_ON(condition)
++#else
++#define rtw_warn_on(condition) do {} while (0)
++#endif
++
++#define _RND(sz, r) ((((sz)+((r)-1))/(r))*(r))
++#define RND4(x) (((x >> 2) + (((x & 3) == 0) ? 0: 1)) << 2)
++
++__inline static u32 _RND4(u32 sz)
++{
++
++ u32 val;
++
++ val = ((sz >> 2) + ((sz & 3) ? 1: 0)) << 2;
++
++ return val;
++
++}
++
++__inline static u32 _RND8(u32 sz)
++{
++
++ u32 val;
++
++ val = ((sz >> 3) + ((sz & 7) ? 1: 0)) << 3;
++
++ return val;
++
++}
++
++__inline static u32 _RND128(u32 sz)
++{
++
++ u32 val;
++
++ val = ((sz >> 7) + ((sz & 127) ? 1: 0)) << 7;
++
++ return val;
++
++}
++
++__inline static u32 _RND256(u32 sz)
++{
++
++ u32 val;
++
++ val = ((sz >> 8) + ((sz & 255) ? 1: 0)) << 8;
++
++ return val;
++
++}
++
++__inline static u32 _RND512(u32 sz)
++{
++
++ u32 val;
++
++ val = ((sz >> 9) + ((sz & 511) ? 1: 0)) << 9;
++
++ return val;
++
++}
++
++__inline static u32 bitshift(u32 bitmask)
++{
++ u32 i;
++
++ for (i = 0; i <= 31; i++)
++ if (((bitmask>>i) & 0x1) == 1) break;
++
++ return i;
++}
++
++#ifndef MAC_FMT
++#define MAC_FMT "%02x:%02x:%02x:%02x:%02x:%02x"
++#endif
++#ifndef MAC_ARG
++#define MAC_ARG(x) ((u8*)(x))[0],((u8*)(x))[1],((u8*)(x))[2],((u8*)(x))[3],((u8*)(x))[4],((u8*)(x))[5]
++#endif
++
++//#ifdef __GNUC__
++#ifdef PLATFORM_LINUX
++#define STRUCT_PACKED __attribute__ ((packed))
++#else
++#define STRUCT_PACKED
++#endif
++
++
++// limitation of path length
++#ifdef PLATFORM_LINUX
++ #define PATH_LENGTH_MAX PATH_MAX
++#elif defined(PLATFORM_WINDOWS)
++ #define PATH_LENGTH_MAX MAX_PATH
++#endif
++
++
++// Suspend lock prevent system from going suspend
++#ifdef CONFIG_WAKELOCK
++#include <linux/wakelock.h>
++#elif defined(CONFIG_ANDROID_POWER)
++#include <linux/android_power.h>
++#endif
++
++extern void rtw_suspend_lock_init(void);
++extern void rtw_suspend_lock_uninit(void);
++extern void rtw_lock_suspend(void);
++extern void rtw_unlock_suspend(void);
++extern void rtw_lock_suspend_timeout(u32 timeout_ms);
++
++
++//Atomic integer operations
++#ifdef PLATFORM_LINUX
++ #define ATOMIC_T atomic_t
++#elif defined(PLATFORM_WINDOWS)
++ #define ATOMIC_T LONG
++#elif defined(PLATFORM_FREEBSD)
++ typedef uint32_t ATOMIC_T ;
++#endif
++
++extern void ATOMIC_SET(ATOMIC_T *v, int i);
++extern int ATOMIC_READ(ATOMIC_T *v);
++extern void ATOMIC_ADD(ATOMIC_T *v, int i);
++extern void ATOMIC_SUB(ATOMIC_T *v, int i);
++extern void ATOMIC_INC(ATOMIC_T *v);
++extern void ATOMIC_DEC(ATOMIC_T *v);
++extern int ATOMIC_ADD_RETURN(ATOMIC_T *v, int i);
++extern int ATOMIC_SUB_RETURN(ATOMIC_T *v, int i);
++extern int ATOMIC_INC_RETURN(ATOMIC_T *v);
++extern int ATOMIC_DEC_RETURN(ATOMIC_T *v);
++
++//File operation APIs, just for linux now
++extern int rtw_is_file_readable(char *path);
++extern int rtw_retrive_from_file(char *path, u8* buf, u32 sz);
++extern int rtw_store_to_file(char *path, u8* buf, u32 sz);
++
++
++#if 1 //#ifdef MEM_ALLOC_REFINE_ADAPTOR
++struct rtw_netdev_priv_indicator {
++ void *priv;
++ u32 sizeof_priv;
++};
++struct net_device *rtw_alloc_etherdev_with_old_priv(int sizeof_priv, void *old_priv);
++extern struct net_device * rtw_alloc_etherdev(int sizeof_priv);
++
++#ifndef PLATFORM_FREEBSD
++#define rtw_netdev_priv(netdev) ( ((struct rtw_netdev_priv_indicator *)netdev_priv(netdev))->priv )
++#else //PLATFORM_FREEBSD
++#define rtw_netdev_priv(netdev) (((struct ifnet *)netdev)->if_softc)
++#endif //PLATFORM_FREEBSD
++
++#ifndef PLATFORM_FREEBSD
++extern void rtw_free_netdev(struct net_device * netdev);
++#else //PLATFORM_FREEBSD
++#define rtw_free_netdev(netdev) if_free((netdev))
++#endif //PLATFORM_FREEBSD
++
++#else //MEM_ALLOC_REFINE_ADAPTOR
++
++#define rtw_alloc_etherdev(sizeof_priv) alloc_etherdev((sizeof_priv))
++
++#ifndef PLATFORM_FREEBSD
++#define rtw_netdev_priv(netdev) netdev_priv((netdev))
++#define rtw_free_netdev(netdev) free_netdev((netdev))
++#else //PLATFORM_FREEBSD
++#define rtw_netdev_priv(netdev) (((struct ifnet *)netdev)->if_softc)
++#define rtw_free_netdev(netdev) if_free((netdev))
++#endif //PLATFORM_FREEBSD
++#endif
++
++#ifdef PLATFORM_LINUX
++#define NDEV_FMT "%s"
++#define NDEV_ARG(ndev) ndev->name
++#define ADPT_FMT "%s"
++#define ADPT_ARG(adapter) adapter->pnetdev->name
++#define FUNC_NDEV_FMT "%s(%s)"
++#define FUNC_NDEV_ARG(ndev) __func__, ndev->name
++#define FUNC_ADPT_FMT "%s(%s)"
++#define FUNC_ADPT_ARG(adapter) __func__, adapter->pnetdev->name
++#else
++#define NDEV_FMT "%s"
++#define NDEV_ARG(ndev) ""
++#define ADPT_FMT "%s"
++#define ADPT_ARG(adapter) ""
++#define FUNC_NDEV_FMT "%s"
++#define FUNC_NDEV_ARG(ndev) __func__
++#define FUNC_ADPT_FMT "%s"
++#define FUNC_ADPT_ARG(adapter) __func__
++#endif
++
++#ifdef PLATFORM_LINUX
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27))
++#define rtw_signal_process(pid, sig) kill_pid(find_vpid((pid)),(sig), 1)
++#else //(LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27))
++#define rtw_signal_process(pid, sig) kill_proc((pid), (sig), 1)
++#endif //(LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27))
++#endif //PLATFORM_LINUX
++
++extern u64 rtw_modular64(u64 x, u64 y);
++extern u64 rtw_division64(u64 x, u64 y);
++
++
++/* Macros for handling unaligned memory accesses */
++
++#define RTW_GET_BE16(a) ((u16) (((a)[0] << 8) | (a)[1]))
++#define RTW_PUT_BE16(a, val) \
++ do { \
++ (a)[0] = ((u16) (val)) >> 8; \
++ (a)[1] = ((u16) (val)) & 0xff; \
++ } while (0)
++
++#define RTW_GET_LE16(a) ((u16) (((a)[1] << 8) | (a)[0]))
++#define RTW_PUT_LE16(a, val) \
++ do { \
++ (a)[1] = ((u16) (val)) >> 8; \
++ (a)[0] = ((u16) (val)) & 0xff; \
++ } while (0)
++
++#define RTW_GET_BE24(a) ((((u32) (a)[0]) << 16) | (((u32) (a)[1]) << 8) | \
++ ((u32) (a)[2]))
++#define RTW_PUT_BE24(a, val) \
++ do { \
++ (a)[0] = (u8) ((((u32) (val)) >> 16) & 0xff); \
++ (a)[1] = (u8) ((((u32) (val)) >> 8) & 0xff); \
++ (a)[2] = (u8) (((u32) (val)) & 0xff); \
++ } while (0)
++
++#define RTW_GET_BE32(a) ((((u32) (a)[0]) << 24) | (((u32) (a)[1]) << 16) | \
++ (((u32) (a)[2]) << 8) | ((u32) (a)[3]))
++#define RTW_PUT_BE32(a, val) \
++ do { \
++ (a)[0] = (u8) ((((u32) (val)) >> 24) & 0xff); \
++ (a)[1] = (u8) ((((u32) (val)) >> 16) & 0xff); \
++ (a)[2] = (u8) ((((u32) (val)) >> 8) & 0xff); \
++ (a)[3] = (u8) (((u32) (val)) & 0xff); \
++ } while (0)
++
++#define RTW_GET_LE32(a) ((((u32) (a)[3]) << 24) | (((u32) (a)[2]) << 16) | \
++ (((u32) (a)[1]) << 8) | ((u32) (a)[0]))
++#define RTW_PUT_LE32(a, val) \
++ do { \
++ (a)[3] = (u8) ((((u32) (val)) >> 24) & 0xff); \
++ (a)[2] = (u8) ((((u32) (val)) >> 16) & 0xff); \
++ (a)[1] = (u8) ((((u32) (val)) >> 8) & 0xff); \
++ (a)[0] = (u8) (((u32) (val)) & 0xff); \
++ } while (0)
++
++#define RTW_GET_BE64(a) ((((u64) (a)[0]) << 56) | (((u64) (a)[1]) << 48) | \
++ (((u64) (a)[2]) << 40) | (((u64) (a)[3]) << 32) | \
++ (((u64) (a)[4]) << 24) | (((u64) (a)[5]) << 16) | \
++ (((u64) (a)[6]) << 8) | ((u64) (a)[7]))
++#define RTW_PUT_BE64(a, val) \
++ do { \
++ (a)[0] = (u8) (((u64) (val)) >> 56); \
++ (a)[1] = (u8) (((u64) (val)) >> 48); \
++ (a)[2] = (u8) (((u64) (val)) >> 40); \
++ (a)[3] = (u8) (((u64) (val)) >> 32); \
++ (a)[4] = (u8) (((u64) (val)) >> 24); \
++ (a)[5] = (u8) (((u64) (val)) >> 16); \
++ (a)[6] = (u8) (((u64) (val)) >> 8); \
++ (a)[7] = (u8) (((u64) (val)) & 0xff); \
++ } while (0)
++
++#define RTW_GET_LE64(a) ((((u64) (a)[7]) << 56) | (((u64) (a)[6]) << 48) | \
++ (((u64) (a)[5]) << 40) | (((u64) (a)[4]) << 32) | \
++ (((u64) (a)[3]) << 24) | (((u64) (a)[2]) << 16) | \
++ (((u64) (a)[1]) << 8) | ((u64) (a)[0]))
++
++void rtw_buf_free(u8 **buf, u32 *buf_len);
++void rtw_buf_update(u8 **buf, u32 *buf_len, u8 *src, u32 src_len);
++
++struct rtw_cbuf {
++ u32 write;
++ u32 read;
++ u32 size;
++ void *bufs[0];
++};
++
++bool rtw_cbuf_full(struct rtw_cbuf *cbuf);
++bool rtw_cbuf_empty(struct rtw_cbuf *cbuf);
++bool rtw_cbuf_push(struct rtw_cbuf *cbuf, void *buf);
++void *rtw_cbuf_pop(struct rtw_cbuf *cbuf);
++struct rtw_cbuf *rtw_cbuf_alloc(u32 size);
++void rtw_cbuf_free(struct rtw_cbuf *cbuf);
++
++#endif
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/pci_hal.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/pci_hal.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/pci_hal.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/pci_hal.h 2015-07-28 01:20:58.317611539 +0200
+@@ -0,0 +1,167 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef __PCI_HAL_H__
++#define __PCI_HAL_H__
++
++
++#define INTEL_VENDOR_ID 0x8086
++#define SIS_VENDOR_ID 0x1039
++#define ATI_VENDOR_ID 0x1002
++#define ATI_DEVICE_ID 0x7914
++#define AMD_VENDOR_ID 0x1022
++
++#define PCI_MAX_BRIDGE_NUMBER 255
++#define PCI_MAX_DEVICES 32
++#define PCI_MAX_FUNCTION 8
++
++#define PCI_CONF_ADDRESS 0x0CF8 // PCI Configuration Space Address
++#define PCI_CONF_DATA 0x0CFC // PCI Configuration Space Data
++
++#define PCI_CLASS_BRIDGE_DEV 0x06
++#define PCI_SUBCLASS_BR_PCI_TO_PCI 0x04
++
++#define PCI_CAPABILITY_ID_PCI_EXPRESS 0x10
++
++#define U1DONTCARE 0xFF
++#define U2DONTCARE 0xFFFF
++#define U4DONTCARE 0xFFFFFFFF
++
++#define PCI_VENDER_ID_REALTEK 0x10ec
++
++#define HAL_HW_PCI_8180_DEVICE_ID 0x8180
++#define HAL_HW_PCI_8185_DEVICE_ID 0x8185 //8185 or 8185b
++#define HAL_HW_PCI_8188_DEVICE_ID 0x8188 //8185b
++#define HAL_HW_PCI_8198_DEVICE_ID 0x8198 //8185b
++#define HAL_HW_PCI_8190_DEVICE_ID 0x8190 //8190
++#define HAL_HW_PCI_8723E_DEVICE_ID 0x8723 //8723E
++#define HAL_HW_PCI_8192_DEVICE_ID 0x8192 //8192 PCI-E
++#define HAL_HW_PCI_8192SE_DEVICE_ID 0x8192 //8192 SE
++#define HAL_HW_PCI_8174_DEVICE_ID 0x8174 //8192 SE
++#define HAL_HW_PCI_8173_DEVICE_ID 0x8173 //8191 SE Crab
++#define HAL_HW_PCI_8172_DEVICE_ID 0x8172 //8191 SE RE
++#define HAL_HW_PCI_8171_DEVICE_ID 0x8171 //8191 SE Unicron
++#define HAL_HW_PCI_0045_DEVICE_ID 0x0045 //8190 PCI for Ceraga
++#define HAL_HW_PCI_0046_DEVICE_ID 0x0046 //8190 Cardbus for Ceraga
++#define HAL_HW_PCI_0044_DEVICE_ID 0x0044 //8192e PCIE for Ceraga
++#define HAL_HW_PCI_0047_DEVICE_ID 0x0047 //8192e Express Card for Ceraga
++#define HAL_HW_PCI_700F_DEVICE_ID 0x700F
++#define HAL_HW_PCI_701F_DEVICE_ID 0x701F
++#define HAL_HW_PCI_DLINK_DEVICE_ID 0x3304
++#define HAL_HW_PCI_8192CET_DEVICE_ID 0x8191 //8192ce
++#define HAL_HW_PCI_8192CE_DEVICE_ID 0x8178 //8192ce
++#define HAL_HW_PCI_8191CE_DEVICE_ID 0x8177 //8192ce
++#define HAL_HW_PCI_8188CE_DEVICE_ID 0x8176 //8192ce
++#define HAL_HW_PCI_8192CU_DEVICE_ID 0x8191 //8192ce
++#define HAL_HW_PCI_8192DE_DEVICE_ID 0x8193 //8192de
++#define HAL_HW_PCI_002B_DEVICE_ID 0x002B //8192de, provided by HW SD
++
++#define HAL_MEMORY_MAPPED_IO_RANGE_8190PCI 0x1000 //8190 support 16 pages of IO registers
++#define HAL_HW_PCI_REVISION_ID_8190PCI 0x00
++#define HAL_MEMORY_MAPPED_IO_RANGE_8192PCIE 0x4000 //8192 support 16 pages of IO registers
++#define HAL_HW_PCI_REVISION_ID_8192PCIE 0x01
++#define HAL_MEMORY_MAPPED_IO_RANGE_8192SE 0x4000 //8192 support 16 pages of IO registers
++#define HAL_HW_PCI_REVISION_ID_8192SE 0x10
++#define HAL_HW_PCI_REVISION_ID_8192CE 0x1
++#define HAL_MEMORY_MAPPED_IO_RANGE_8192CE 0x4000 //8192 support 16 pages of IO registers
++#define HAL_HW_PCI_REVISION_ID_8192DE 0x0
++#define HAL_MEMORY_MAPPED_IO_RANGE_8192DE 0x4000 //8192 support 16 pages of IO registers
++
++enum pci_bridge_vendor {
++ PCI_BRIDGE_VENDOR_INTEL = 0x0,//0b'0000,0001
++ PCI_BRIDGE_VENDOR_ATI, //= 0x02,//0b'0000,0010
++ PCI_BRIDGE_VENDOR_AMD, //= 0x04,//0b'0000,0100
++ PCI_BRIDGE_VENDOR_SIS ,//= 0x08,//0b'0000,1000
++ PCI_BRIDGE_VENDOR_UNKNOWN, //= 0x40,//0b'0100,0000
++ PCI_BRIDGE_VENDOR_MAX ,//= 0x80
++} ;
++
++struct rt_pci_capabilities_header {
++ u8 capability_id;
++ u8 next;
++};
++
++struct pci_priv{
++ u8 linkctrl_reg;
++
++ u8 busnumber;
++ u8 devnumber;
++ u8 funcnumber;
++
++ u8 pcibridge_busnum;
++ u8 pcibridge_devnum;
++ u8 pcibridge_funcnum;
++ u8 pcibridge_vendor;
++ u16 pcibridge_vendorid;
++ u16 pcibridge_deviceid;
++ u8 pcibridge_pciehdr_offset;
++ u8 pcibridge_linkctrlreg;
++
++ u8 amd_l1_patch;
++};
++
++typedef struct _RT_ISR_CONTENT
++{
++ union{
++ u32 IntArray[2];
++ u32 IntReg4Byte;
++ u16 IntReg2Byte;
++ };
++}RT_ISR_CONTENT, *PRT_ISR_CONTENT;
++
++//#define RegAddr(addr) (addr + 0xB2000000UL)
++//some platform macros will def here
++static inline void NdisRawWritePortUlong(u32 port, u32 val)
++{
++ outl(val, port);
++ //writel(val, (u8 *)RegAddr(port));
++}
++
++static inline void NdisRawWritePortUchar(u32 port, u8 val)
++{
++ outb(val, port);
++ //writeb(val, (u8 *)RegAddr(port));
++}
++
++static inline void NdisRawReadPortUchar(u32 port, u8 *pval)
++{
++ *pval = inb(port);
++ //*pval = readb((u8 *)RegAddr(port));
++}
++
++static inline void NdisRawReadPortUshort(u32 port, u16 *pval)
++{
++ *pval = inw(port);
++ //*pval = readw((u8 *)RegAddr(port));
++}
++
++static inline void NdisRawReadPortUlong(u32 port, u32 *pval)
++{
++ *pval = inl(port);
++ //*pval = readl((u8 *)RegAddr(port));
++}
++
++#ifdef CONFIG_RTL8192C
++void rtl8192ce_set_hal_ops(_adapter * padapter);
++#endif
++#ifdef CONFIG_RTL8192D
++void rtl8192de_set_hal_ops(_adapter * padapter);
++#endif
++
++#endif //__PCIE_HAL_H__
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/pci_ops.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/pci_ops.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/pci_ops.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/pci_ops.h 2015-07-28 01:20:58.317611539 +0200
+@@ -0,0 +1,60 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef __PCI_OPS_H_
++#define __PCI_OPS_H_
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++#include <osdep_intf.h>
++
++#ifdef CONFIG_RTL8192C
++u32 rtl8192ce_init_desc_ring(_adapter * padapter);
++u32 rtl8192ce_free_desc_ring(_adapter * padapter);
++void rtl8192ce_reset_desc_ring(_adapter * padapter);
++#ifdef CONFIG_64BIT_DMA
++u8 PlatformEnable92CEDMA64(PADAPTER Adapter);
++#endif
++int rtl8192ce_interrupt(PADAPTER Adapter);
++void rtl8192ce_xmit_tasklet(void *priv);
++void rtl8192ce_recv_tasklet(void *priv);
++void rtl8192ce_prepare_bcn_tasklet(void *priv);
++void rtl8192ce_set_intf_ops(struct _io_ops *pops);
++#define pci_set_intf_ops rtl8192ce_set_intf_ops
++#endif
++
++#ifdef CONFIG_RTL8192D
++u32 rtl8192de_init_desc_ring(_adapter * padapter);
++u32 rtl8192de_free_desc_ring(_adapter * padapter);
++void rtl8192de_reset_desc_ring(_adapter * padapter);
++#ifdef CONFIG_64BIT_DMA
++u8 PlatformEnable92DEDMA64(PADAPTER Adapter);
++#endif
++int rtl8192de_interrupt(PADAPTER Adapter);
++void rtl8192de_xmit_tasklet(void *priv);
++void rtl8192de_recv_tasklet(void *priv);
++void rtl8192de_prepare_bcn_tasklet(void *priv);
++void rtl8192de_set_intf_ops(struct _io_ops *pops);
++#define pci_set_intf_ops rtl8192de_set_intf_ops
++u32 MpReadPCIDwordDBI8192D(IN PADAPTER Adapter, IN u16 Offset, IN u8 Direct);
++void MpWritePCIDwordDBI8192D(IN PADAPTER Adapter, IN u16 Offset, IN u32 Value, IN u8 Direct);
++#endif
++
++#endif
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/pci_osintf.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/pci_osintf.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/pci_osintf.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/pci_osintf.h 2015-07-28 01:20:58.317611539 +0200
+@@ -0,0 +1,32 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef __PCI_OSINTF_H
++#define __PCI_OSINTF_H
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++
++
++void rtw_pci_disable_aspm(_adapter *padapter);
++void rtw_pci_enable_aspm(_adapter *padapter);
++
++
++#endif
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/recv_osdep.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/recv_osdep.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/recv_osdep.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/recv_osdep.h 2015-07-28 01:20:58.317611539 +0200
+@@ -0,0 +1,57 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef __RECV_OSDEP_H_
++#define __RECV_OSDEP_H_
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++
++
++extern sint _rtw_init_recv_priv(struct recv_priv *precvpriv, _adapter *padapter);
++extern void _rtw_free_recv_priv (struct recv_priv *precvpriv);
++
++
++extern s32 rtw_recv_entry(union recv_frame *precv_frame);
++extern int rtw_recv_indicatepkt(_adapter *adapter, union recv_frame *precv_frame);
++extern void rtw_recv_returnpacket(IN _nic_hdl cnxt, IN _pkt *preturnedpkt);
++
++extern void rtw_hostapd_mlme_rx(_adapter *padapter, union recv_frame *precv_frame);
++extern void rtw_handle_tkip_mic_err(_adapter *padapter,u8 bgroup);
++
++
++int rtw_init_recv_priv(struct recv_priv *precvpriv, _adapter *padapter);
++void rtw_free_recv_priv (struct recv_priv *precvpriv);
++
++
++int rtw_os_recv_resource_init(struct recv_priv *precvpriv, _adapter *padapter);
++int rtw_os_recv_resource_alloc(_adapter *padapter, union recv_frame *precvframe);
++void rtw_os_recv_resource_free(struct recv_priv *precvpriv);
++
++
++int rtw_os_recvbuf_resource_alloc(_adapter *padapter, struct recv_buf *precvbuf);
++int rtw_os_recvbuf_resource_free(_adapter *padapter, struct recv_buf *precvbuf);
++
++void rtw_os_read_port(_adapter *padapter, struct recv_buf *precvbuf);
++
++void rtw_init_recv_timer(struct recv_reorder_ctrl *preorder_ctrl);
++
++
++#endif //
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtl8192c_cmd.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtl8192c_cmd.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtl8192c_cmd.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtl8192c_cmd.h 2015-07-28 01:20:58.317611539 +0200
+@@ -0,0 +1,152 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef __RTL8192C_CMD_H_
++#define __RTL8192C_CMD_H_
++
++
++enum cmd_msg_element_id
++{
++ NONE_CMDMSG_EID,
++ AP_OFFLOAD_EID=0,
++ SET_PWRMODE_EID=1,
++ JOINBSS_RPT_EID=2,
++ RSVD_PAGE_EID=3,
++ RSSI_4_EID = 4,
++ RSSI_SETTING_EID=5,
++ MACID_CONFIG_EID=6,
++ MACID_PS_MODE_EID=7,
++ P2P_PS_OFFLOAD_EID=8,
++ SELECTIVE_SUSPEND_ROF_CMD=9,
++#ifdef CONFIG_WOWLAN
++ H2C_WO_WLAN_CMD = 26, // Wake on Wlan.
++ EXT_MACID_PERIOD_EID = 27, // support macid to 64
++ MACID64_CONFIG_EID = 28, // support macid to 64
++#endif // CONFIG_WOWLAN
++ P2P_PS_CTW_CMD_EID=32,
++ H2C_92C_IO_OFFLOAD=44,
++#ifdef CONFIG_WOWLAN
++ KEEP_ALIVE_CONTROL_CMD=48,
++ DISCONNECT_DECISION_CTRL_CMD=49,
++ REMOTE_WAKE_CTRL_CMD=60,
++#endif // CONFIG_WOWLAN
++ H2C_92C_TSF_SYNC=67,
++ H2C_92C_DISABLE_BCN_FUNC=68,
++ H2C_92C_RESET_TSF = 75,
++ H2C_92C_CMD_MAX
++};
++
++struct cmd_msg_parm {
++ u8 eid; //element id
++ u8 sz; // sz
++ u8 buf[6];
++};
++
++typedef struct _SETPWRMODE_PARM{
++ u8 Mode;
++ u8 SmartPS;
++ u8 BcnPassTime; // unit: 100ms
++}SETPWRMODE_PARM, *PSETPWRMODE_PARM;
++
++#ifdef CONFIG_WOWLAN
++typedef struct _SETWOWLAN_PARM{
++ u8 mode;
++ u8 gpio_index;
++ u8 gpio_duration;
++ u8 second_mode;
++ u8 reserve;
++}SETWOWLAN_PARM, *PSETWOWLAN_PARM;
++
++#define FW_WOWLAN_FUN_EN BIT(0)
++#define FW_WOWLAN_PATTERN_MATCH BIT(1)
++#define FW_WOWLAN_MAGIC_PKT BIT(2)
++#define FW_WOWLAN_UNICAST BIT(3)
++#define FW_WOWLAN_ALL_PKT_DROP BIT(4)
++#define FW_WOWLAN_GPIO_ACTIVE BIT(5)
++#define FW_WOWLAN_REKEY_WAKEUP BIT(6)
++#define FW_WOWLAN_DEAUTH_WAKEUP BIT(7)
++
++#define FW_WOWLAN_GPIO_WAKEUP_EN BIT(0)
++#define FW_FW_PARSE_MAGIC_PKT BIT(1)
++#endif // CONFIG_WOWLAN
++
++struct H2C_SS_RFOFF_PARAM{
++ u8 ROFOn; // 1: on, 0:off
++ u16 gpio_period; // unit: 1024 us
++}__attribute__ ((packed));
++
++
++typedef struct JOINBSSRPT_PARM{
++ u8 OpMode; // RT_MEDIA_STATUS
++}JOINBSSRPT_PARM, *PJOINBSSRPT_PARM;
++
++typedef struct _RSVDPAGE_LOC{
++ u8 LocProbeRsp;
++ u8 LocPsPoll;
++ u8 LocNullData;
++}RSVDPAGE_LOC, *PRSVDPAGE_LOC;
++
++struct P2P_PS_Offload_t {
++ unsigned char Offload_En:1;
++ unsigned char role:1; // 1: Owner, 0: Client
++ unsigned char CTWindow_En:1;
++ unsigned char NoA0_En:1;
++ unsigned char NoA1_En:1;
++ unsigned char AllStaSleep:1; // Only valid in Owner
++ unsigned char discovery:1;
++ unsigned char rsvd:1;
++};
++
++struct P2P_PS_CTWPeriod_t {
++ unsigned char CTWPeriod; //TU
++};
++
++// host message to firmware cmd
++void rtl8192c_set_FwPwrMode_cmd(_adapter*padapter, u8 Mode);
++void rtl8192c_set_FwJoinBssReport_cmd(_adapter* padapter, u8 mstatus);
++u8 rtl8192c_set_rssi_cmd(_adapter*padapter, u8 *param);
++u8 rtl8192c_set_raid_cmd(_adapter*padapter, u32 mask, u8 arg);
++void rtl8192c_Add_RateATid(PADAPTER pAdapter, u32 bitmap, u8 arg);
++u8 rtl8192c_set_FwSelectSuspend_cmd(_adapter*padapter,u8 bfwpoll, u16 period);
++#ifdef CONFIG_P2P
++void rtl8192c_set_p2p_ps_offload_cmd(_adapter* padapter, u8 p2p_ps_state);
++#endif //CONFIG_P2P
++
++#ifdef CONFIG_IOL
++typedef struct _IO_OFFLOAD_LOC{
++ u8 LocCmd;
++}IO_OFFLOAD_LOC, *PIO_OFFLOAD_LOC;
++int rtl8192c_IOL_exec_cmds_sync(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms);
++#endif //CONFIG_IOL
++
++#ifdef CONFIG_BEACON_DISABLE_OFFLOAD
++u8 rtl8192c_dis_beacon_fun_cmd(_adapter* padapter);
++#endif // CONFIG_BEACON_DISABLE_OFFLOAD
++
++
++#ifdef CONFIG_TSF_RESET_OFFLOAD
++int reset_tsf(PADAPTER Adapter, u8 reset_port );
++#endif // CONFIG_TSF_RESET_OFFLOAD
++
++#ifdef CONFIG_WOWLAN
++void rtl8192c_set_wowlan_cmd(_adapter* padapter);
++void SetFwRelatedForWoWLAN8192CU(_adapter* padapter,u8 bHostIsGoingtoSleep);
++#endif // CONFIG_WOWLAN
++
++#endif // __RTL8192C_CMD_H_
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtl8192c_dm.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtl8192c_dm.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtl8192c_dm.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtl8192c_dm.h 2015-07-28 01:20:58.317611539 +0200
+@@ -0,0 +1,515 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef __RTL8192C_DM_H__
++#define __RTL8192C_DM_H__
++//============================================================
++// Description:
++//
++// This file is for 92CE/92CU dynamic mechanism only
++//
++//
++//============================================================
++
++#define RSSI_CCK 0
++#define RSSI_OFDM 1
++#define RSSI_DEFAULT 2
++
++//============================================================
++// structure and define
++//============================================================
++
++typedef struct _FALSE_ALARM_STATISTICS{
++ u32 Cnt_Parity_Fail;
++ u32 Cnt_Rate_Illegal;
++ u32 Cnt_Crc8_fail;
++ u32 Cnt_Mcs_fail;
++ u32 Cnt_Ofdm_fail;
++ u32 Cnt_Cck_fail;
++ u32 Cnt_all;
++ u32 Cnt_Fast_Fsync;
++ u32 Cnt_SB_Search_fail;
++}FALSE_ALARM_STATISTICS, *PFALSE_ALARM_STATISTICS;
++
++typedef struct _Dynamic_Power_Saving_
++{
++ u8 PreCCAState;
++ u8 CurCCAState;
++
++ u8 PreRFState;
++ u8 CurRFState;
++
++ s32 Rssi_val_min;
++
++}PS_T;
++
++typedef struct _Dynamic_Initial_Gain_Threshold_
++{
++ u8 Dig_Enable_Flag;
++ u8 Dig_Ext_Port_Stage;
++
++ int RssiLowThresh;
++ int RssiHighThresh;
++
++ u32 FALowThresh;
++ u32 FAHighThresh;
++
++ u8 CurSTAConnectState;
++ u8 PreSTAConnectState;
++ u8 CurMultiSTAConnectState;
++
++ u8 PreIGValue;
++ u8 CurIGValue;
++ u8 BackupIGValue;
++
++ char BackoffVal;
++ char BackoffVal_range_max;
++ char BackoffVal_range_min;
++ u8 rx_gain_range_max;
++ u8 rx_gain_range_min;
++ u8 Rssi_val_min;
++
++ u8 PreCCKPDState;
++ u8 CurCCKPDState;
++ u8 PreCCKFAState;
++ u8 CurCCKFAState;
++ u8 PreCCAState;
++ u8 CurCCAState;
++
++ u8 LargeFAHit;
++ u8 ForbiddenIGI;
++ u32 Recover_cnt;
++ u8 rx_gain_range_min_nolink;
++
++}DIG_T;
++
++typedef enum tag_Dynamic_Init_Gain_Operation_Type_Definition
++{
++ DIG_TYPE_THRESH_HIGH = 0,
++ DIG_TYPE_THRESH_LOW = 1,
++ DIG_TYPE_BACKOFF = 2,
++ DIG_TYPE_RX_GAIN_MIN = 3,
++ DIG_TYPE_RX_GAIN_MAX = 4,
++ DIG_TYPE_ENABLE = 5,
++ DIG_TYPE_DISABLE = 6,
++ DIG_OP_TYPE_MAX
++}DM_DIG_OP_E;
++
++typedef enum tag_CCK_Packet_Detection_Threshold_Type_Definition
++{
++ CCK_PD_STAGE_LowRssi = 0,
++ CCK_PD_STAGE_HighRssi = 1,
++ CCK_PD_STAGE_MAX = 3,
++}DM_CCK_PDTH_E;
++
++typedef enum tag_1R_CCA_Type_Definition
++{
++ CCA_1R =0,
++ CCA_2R = 1,
++ CCA_MAX = 2,
++}DM_1R_CCA_E;
++
++typedef enum tag_RF_Type_Definition
++{
++ RF_Save =0,
++ RF_Normal = 1,
++ RF_MAX = 2,
++}DM_RF_E;
++
++typedef enum tag_DIG_EXT_PORT_ALGO_Definition
++{
++ DIG_EXT_PORT_STAGE_0 = 0,
++ DIG_EXT_PORT_STAGE_1 = 1,
++ DIG_EXT_PORT_STAGE_2 = 2,
++ DIG_EXT_PORT_STAGE_3 = 3,
++ DIG_EXT_PORT_STAGE_MAX = 4,
++}DM_DIG_EXT_PORT_ALG_E;
++
++
++typedef enum tag_DIG_Connect_Definition
++{
++ DIG_STA_DISCONNECT = 0,
++ DIG_STA_CONNECT = 1,
++ DIG_STA_BEFORE_CONNECT = 2,
++ DIG_MultiSTA_DISCONNECT = 3,
++ DIG_MultiSTA_CONNECT = 4,
++ DIG_CONNECT_MAX
++}DM_DIG_CONNECT_E;
++
++
++
++typedef enum _BT_Ant_NUM{
++ Ant_x2 = 0,
++ Ant_x1 = 1
++} BT_Ant_NUM, *PBT_Ant_NUM;
++
++typedef enum _BT_CoType{
++ BT_2Wire = 0,
++ BT_ISSC_3Wire = 1,
++ BT_Accel = 2,
++ BT_CSR_BC4 = 3,
++ BT_CSR_BC8 = 4,
++ BT_RTL8756 = 5,
++} BT_CoType, *PBT_CoType;
++
++typedef enum _BT_CurState{
++ BT_OFF = 0,
++ BT_ON = 1,
++} BT_CurState, *PBT_CurState;
++
++typedef enum _BT_ServiceType{
++ BT_SCO = 0,
++ BT_A2DP = 1,
++ BT_HID = 2,
++ BT_HID_Idle = 3,
++ BT_Scan = 4,
++ BT_Idle = 5,
++ BT_OtherAction = 6,
++ BT_Busy = 7,
++ BT_OtherBusy = 8,
++ BT_PAN = 9,
++} BT_ServiceType, *PBT_ServiceType;
++
++typedef enum _BT_RadioShared{
++ BT_Radio_Shared = 0,
++ BT_Radio_Individual = 1,
++} BT_RadioShared, *PBT_RadioShared;
++
++struct btcoexist_priv {
++ u8 BT_Coexist;
++ u8 BT_Ant_Num;
++ u8 BT_CoexistType;
++ u8 BT_State;
++ u8 BT_CUR_State; //0:on, 1:off
++ u8 BT_Ant_isolation; //0:good, 1:bad
++ u8 BT_PapeCtrl; //0:SW, 1:SW/HW dynamic
++ u8 BT_Service;
++ u8 BT_Ampdu; // 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU.
++ u8 BT_RadioSharedType;
++ u32 Ratio_Tx;
++ u32 Ratio_PRI;
++ u8 BtRfRegOrigin1E;
++ u8 BtRfRegOrigin1F;
++ u8 BtRssiState;
++ u32 BtEdcaUL;
++ u32 BtEdcaDL;
++ u32 BT_EDCA[2];
++ u8 bCOBT;
++
++ u8 bInitSet;
++ u8 bBTBusyTraffic;
++ u8 bBTTrafficModeSet;
++ u8 bBTNonTrafficModeSet;
++ //BTTraffic BT21TrafficStatistics;
++ u32 CurrentState;
++ u32 PreviousState;
++ u8 BtPreRssiState;
++ u8 bFWCoexistAllOff;
++ u8 bSWCoexistAllOff;
++};
++
++#define BW_AUTO_SWITCH_HIGH_LOW 25
++#define BW_AUTO_SWITCH_LOW_HIGH 30
++
++#define DM_DIG_THRESH_HIGH 40
++#define DM_DIG_THRESH_LOW 35
++
++#define DM_FALSEALARM_THRESH_LOW 400
++#define DM_FALSEALARM_THRESH_HIGH 1000
++
++#define DM_DIG_MAX 0x3e
++#define DM_DIG_MIN 0x1e //0x22//0x1c
++
++#define DM_DIG_FA_UPPER 0x3e
++#define DM_DIG_FA_LOWER 0x20
++#define DM_DIG_FA_TH0 0x20
++#define DM_DIG_FA_TH1 0x100
++#define DM_DIG_FA_TH2 0x200
++
++#define DM_DIG_BACKOFF_MAX 12
++#define DM_DIG_BACKOFF_MIN (-4)
++#define DM_DIG_BACKOFF_DEFAULT 10
++
++#define RxPathSelection_SS_TH_low 30
++#define RxPathSelection_diff_TH 18
++
++#define DM_RATR_STA_INIT 0
++#define DM_RATR_STA_HIGH 1
++#define DM_RATR_STA_MIDDLE 2
++#define DM_RATR_STA_LOW 3
++
++#define CTSToSelfTHVal 30
++#define RegC38_TH 20
++
++#define WAIotTHVal 25
++
++//Dynamic Tx Power Control Threshold
++#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
++#define TX_POWER_NEAR_FIELD_THRESH_LVL1 67
++
++#define TxHighPwrLevel_Normal 0
++#define TxHighPwrLevel_Level1 1
++#define TxHighPwrLevel_Level2 2
++#define TxHighPwrLevel_BT1 3
++#define TxHighPwrLevel_BT2 4
++#define TxHighPwrLevel_15 5
++#define TxHighPwrLevel_35 6
++#define TxHighPwrLevel_50 7
++#define TxHighPwrLevel_70 8
++#define TxHighPwrLevel_100 9
++
++#define DM_Type_ByFW 0
++#define DM_Type_ByDriver 1
++
++
++typedef struct _RATE_ADAPTIVE
++{
++ u8 RateAdaptiveDisabled;
++ u8 RATRState;
++ u16 reserve;
++
++ u32 HighRSSIThreshForRA;
++ u32 High2LowRSSIThreshForRA;
++ u8 Low2HighRSSIThreshForRA40M;
++ u32 LowRSSIThreshForRA40M;
++ u8 Low2HighRSSIThreshForRA20M;
++ u32 LowRSSIThreshForRA20M;
++ u32 UpperRSSIThresholdRATR;
++ u32 MiddleRSSIThresholdRATR;
++ u32 LowRSSIThresholdRATR;
++ u32 LowRSSIThresholdRATR40M;
++ u32 LowRSSIThresholdRATR20M;
++ u8 PingRSSIEnable; //cosa add for Netcore long range ping issue
++ u32 PingRSSIRATR; //cosa add for Netcore long range ping issue
++ u32 PingRSSIThreshForRA;//cosa add for Netcore long range ping issue
++ u32 LastRATR;
++ u8 PreRATRState;
++
++} RATE_ADAPTIVE, *PRATE_ADAPTIVE;
++
++typedef enum tag_SW_Antenna_Switch_Definition
++{
++ Antenna_B = 1,
++ Antenna_A = 2,
++ Antenna_MAX = 3,
++}DM_SWAS_E;
++
++#ifdef CONFIG_ANTENNA_DIVERSITY
++// This indicates two different the steps.
++// In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air.
++// In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK
++// with original RSSI to determine if it is necessary to switch antenna.
++#define SWAW_STEP_PEAK 0
++#define SWAW_STEP_DETERMINE 1
++
++#define TP_MODE 0
++#define RSSI_MODE 1
++#define TRAFFIC_LOW 0
++#define TRAFFIC_HIGH 1
++
++typedef struct _SW_Antenna_Switch_
++{
++ u8 try_flag;
++ s32 PreRSSI;
++ u8 CurAntenna;
++ u8 PreAntenna;
++ u8 RSSI_Trying;
++ u8 TestMode;
++ u8 bTriggerAntennaSwitch;
++ u8 SelectAntennaMap;
++ // Before link Antenna Switch check
++ u8 SWAS_NoLink_State;
++
++}SWAT_T;
++
++
++#endif
++
++
++struct dm_priv
++{
++ u8 DM_Type;
++ u8 DMFlag, DMFlag_tmp;
++
++
++ //for DIG
++ u8 bDMInitialGainEnable;
++ u8 binitialized; // for dm_initial_gain_Multi_STA use.
++ DIG_T DM_DigTable;
++
++ PS_T DM_PSTable;
++
++ FALSE_ALARM_STATISTICS FalseAlmCnt;
++
++ //for rate adaptive, in fact, 88c/92c fw will handle this
++ u8 bUseRAMask;
++ RATE_ADAPTIVE RateAdaptive;
++
++ //* Upper and Lower Signal threshold for Rate Adaptive*/
++ int UndecoratedSmoothedPWDB;
++ int UndecoratedSmoothedCCK;
++ int EntryMinUndecoratedSmoothedPWDB;
++ int EntryMaxUndecoratedSmoothedPWDB;
++
++
++ //for High Power
++ u8 bDynamicTxPowerEnable;
++ u8 LastDTPLvl;
++ u8 DynamicTxHighPowerLvl;//Add by Jacken Tx Power Control for Near/Far Range 2008/03/06
++
++ //for tx power tracking
++ //u8 bTXPowerTracking;
++ u8 TXPowercount;
++ u8 bTXPowerTrackingInit;
++ u8 TxPowerTrackControl; //for mp mode, turn off txpwrtracking as default
++ u8 TM_Trigger;
++
++ u8 ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1
++ u8 ThermalValue;
++ u8 ThermalValue_LCK;
++ u8 ThermalValue_IQK;
++ u8 ThermalValue_DPK;
++
++ u8 bRfPiEnable;
++
++ //for APK
++ u32 APKoutput[2][2]; //path A/B; output1_1a/output1_2a
++ u8 bAPKdone;
++ u8 bAPKThermalMeterIgnore;
++ u8 bDPdone;
++ u8 bDPPathAOK;
++ u8 bDPPathBOK;
++
++ //for IQK
++ u32 RegC04;
++ u32 Reg874;
++ u32 RegC08;
++ u32 RegB68;
++ u32 RegB6C;
++ u32 Reg870;
++ u32 Reg860;
++ u32 Reg864;
++ u32 ADDA_backup[IQK_ADDA_REG_NUM];
++ u32 IQK_MAC_backup[IQK_MAC_REG_NUM];
++ u32 IQK_BB_backup_recover[9];
++ u32 IQK_BB_backup[IQK_BB_REG_NUM];
++ u8 PowerIndex_backup[6];
++
++ u8 bCCKinCH14;
++
++ char CCK_index;
++ char OFDM_index[2];
++
++ BOOLEAN bDoneTxpower;
++ char CCK_index_HP;
++ char OFDM_index_HP[2];
++ u8 ThermalValue_HP[HP_THERMAL_NUM];
++ u8 ThermalValue_HP_index;
++
++ //for TxPwrTracking
++ int RegE94;
++ int RegE9C;
++ int RegEB4;
++ int RegEBC;
++
++ u32 TXPowerTrackingCallbackCnt; //cosa add for debug
++
++ u32 prv_traffic_idx; // edca turbo
++
++ // for dm_RF_Saving
++ u8 initialize;
++ u32 rf_saving_Reg874;
++ u32 rf_saving_RegC70;
++ u32 rf_saving_Reg85C;
++ u32 rf_saving_RegA74;
++
++ //for Antenna diversity
++#ifdef CONFIG_ANTENNA_DIVERSITY
++ SWAT_T DM_SWAT_Table;
++#endif
++#ifdef CONFIG_SW_ANTENNA_DIVERSITY
++ _timer SwAntennaSwitchTimer;
++
++ u64 lastTxOkCnt;
++ u64 lastRxOkCnt;
++ u64 TXByteCnt_A;
++ u64 TXByteCnt_B;
++ u64 RXByteCnt_A;
++ u64 RXByteCnt_B;
++ u8 DoubleComfirm;
++ u8 TrafficLoad;
++#endif
++
++ s32 OFDM_Pkt_Cnt;
++ u8 RSSI_Select;
++ u8 DIG_Dynamic_MIN ;
++
++ // Add for Reading Initial Data Rate SEL Register 0x484 during watchdog. Using for fill tx desc. 2011.3.21 by Thomas
++ u8 INIDATA_RATE[32];
++
++#ifdef CONFIG_DM_ADAPTIVITY
++ /* Ported from ODM, for ESTI Adaptivity test */
++ s8 TH_L2H_ini;
++ s8 TH_EDCCA_HL_diff;
++ s8 IGI_Base;
++ u8 IGI_target;
++ bool ForceEDCCA;
++ u8 AdapEn_RSSI;
++ s8 Force_TH_H;
++ s8 Force_TH_L;
++ u8 IGI_LowerBound;
++
++ bool bPreEdccaEnable;
++#endif
++};
++
++
++/*------------------------Export global variable----------------------------*/
++/*------------------------Export global variable----------------------------*/
++/*------------------------Export Marco Definition---------------------------*/
++//#define DM_MultiSTA_InitGainChangeNotify(Event) {DM_DigTable.CurMultiSTAConnectState = Event;}
++
++
++//============================================================
++// function prototype
++//============================================================
++void rtl8192c_init_dm_priv(IN PADAPTER Adapter);
++void rtl8192c_deinit_dm_priv(IN PADAPTER Adapter);
++void rtl8192c_InitHalDm(IN PADAPTER Adapter);
++void rtl8192c_HalDmWatchDog(IN PADAPTER Adapter);
++
++VOID rtl8192c_dm_CheckTXPowerTracking(IN PADAPTER Adapter);
++
++void rtl8192c_dm_RF_Saving(IN PADAPTER pAdapter, IN u8 bForceInNormal);
++
++#ifdef CONFIG_BT_COEXIST
++void rtl8192c_set_dm_bt_coexist(_adapter *padapter, u8 bStart);
++void rtl8192c_issue_delete_ba(_adapter *padapter, u8 dir);
++#endif
++
++#ifdef CONFIG_SW_ANTENNA_DIVERSITY
++void SwAntDivRSSICheck8192C(_adapter *padapter ,u32 RxPWDBAll);
++void SwAntDivRestAfterLink8192C(IN PADAPTER Adapter);
++#endif
++#ifdef CONFIG_ANTENNA_DIVERSITY
++void SwAntDivCompare8192C(PADAPTER Adapter, WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src);
++u8 SwAntDivBeforeLink8192C(IN PADAPTER Adapter);
++#endif
++
++#endif //__HAL8190PCIDM_H__
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtl8192c_event.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtl8192c_event.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtl8192c_event.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtl8192c_event.h 2015-07-28 01:20:58.317611539 +0200
+@@ -0,0 +1,26 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef _RTL8192C_EVENT_H_
++#define _RTL8192C_EVENT_H_
++
++
++
++
++#endif
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtl8192c_hal.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtl8192c_hal.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtl8192c_hal.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtl8192c_hal.h 2015-07-28 01:20:58.321597318 +0200
+@@ -0,0 +1,934 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef __RTL8192C_HAL_H__
++#define __RTL8192C_HAL_H__
++
++#include "hal_com.h"
++#include "rtl8192c_spec.h"
++#include "Hal8192CPhyReg.h"
++#include "Hal8192CPhyCfg.h"
++#include "rtl8192c_rf.h"
++#include "rtl8192c_dm.h"
++#include "rtl8192c_recv.h"
++#include "rtl8192c_xmit.h"
++#include "rtl8192c_cmd.h"
++#ifdef DBG_CONFIG_ERROR_DETECT
++#include "rtl8192c_sreset.h"
++#endif
++
++#ifdef CONFIG_PCI_HCI
++
++ #include "Hal8192CEHWImg.h"
++
++ #define RTL819X_DEFAULT_RF_TYPE RF_2T2R
++ //#define RTL819X_DEFAULT_RF_TYPE RF_1T2R
++ #define RTL819X_TOTAL_RF_PATH 2
++
++ //2TODO: The following need to check!!
++ #define RTL8192C_FW_TSMC_IMG "rtl8192CE\\rtl8192cfwT.bin"
++ #define RTL8192C_FW_UMC_IMG "rtl8192CE\\rtl8192cfwU.bin"
++ #define RTL8192C_FW_UMC_B_IMG "rtl8192CE\\rtl8192cfwU_B.bin"
++
++ #define RTL8188C_PHY_REG "rtl8192CE\\PHY_REG_1T.txt"
++ #define RTL8188C_PHY_RADIO_A "rtl8192CE\\radio_a_1T.txt"
++ #define RTL8188C_PHY_RADIO_B "rtl8192CE\\radio_b_1T.txt"
++ #define RTL8188C_AGC_TAB "rtl8192CE\\AGC_TAB_1T.txt"
++ #define RTL8188C_PHY_MACREG "rtl8192CE\\MACREG_1T.txt"
++
++ #define RTL8192C_PHY_REG "rtl8192CE\\PHY_REG_2T.txt"
++ #define RTL8192C_PHY_RADIO_A "rtl8192CE\\radio_a_2T.txt"
++ #define RTL8192C_PHY_RADIO_B "rtl8192CE\\radio_b_2T.txt"
++ #define RTL8192C_AGC_TAB "rtl8192CE\\AGC_TAB_2T.txt"
++ #define RTL8192C_PHY_MACREG "rtl8192CE\\MACREG_2T.txt"
++
++ #define RTL819X_PHY_MACPHY_REG "rtl8192CE\\MACPHY_reg.txt"
++ #define RTL819X_PHY_MACPHY_REG_PG "rtl8192CE\\MACPHY_reg_PG.txt"
++ #define RTL819X_PHY_MACREG "rtl8192CE\\MAC_REG.txt"
++ #define RTL819X_PHY_REG "rtl8192CE\\PHY_REG.txt"
++ #define RTL819X_PHY_REG_1T2R "rtl8192CE\\PHY_REG_1T2R.txt"
++ #define RTL819X_PHY_REG_to1T1R "rtl8192CE\\phy_to1T1R_a.txt"
++ #define RTL819X_PHY_REG_to1T2R "rtl8192CE\\phy_to1T2R.txt"
++ #define RTL819X_PHY_REG_to2T2R "rtl8192CE\\phy_to2T2R.txt"
++ #define RTL819X_PHY_REG_PG "rtl8192CE\\PHY_REG_PG.txt"
++ #define RTL819X_AGC_TAB "rtl8192CE\\AGC_TAB.txt"
++ #define RTL819X_PHY_RADIO_A "rtl8192CE\\radio_a.txt"
++ #define RTL819X_PHY_RADIO_A_1T "rtl8192CE\\radio_a_1t.txt"
++ #define RTL819X_PHY_RADIO_A_2T "rtl8192CE\\radio_a_2t.txt"
++ #define RTL819X_PHY_RADIO_B "rtl8192CE\\radio_b.txt"
++ #define RTL819X_PHY_RADIO_B_GM "rtl8192CE\\radio_b_gm.txt"
++ #define RTL819X_PHY_RADIO_C "rtl8192CE\\radio_c.txt"
++ #define RTL819X_PHY_RADIO_D "rtl8192CE\\radio_d.txt"
++ #define RTL819X_EEPROM_MAP "rtl8192CE\\8192ce.map"
++ #define RTL819X_EFUSE_MAP "rtl8192CE\\8192ce.map"
++
++//---------------------------------------------------------------------
++// RTL8723E From file
++//---------------------------------------------------------------------
++ #define RTL8723_FW_UMC_IMG "rtl8723E\\rtl8723fw.bin"
++ #define RTL8723_PHY_REG "rtl8723E\\PHY_REG_1T.txt"
++ #define RTL8723_PHY_RADIO_A "rtl8723E\\radio_a_1T.txt"
++ #define RTL8723_PHY_RADIO_B "rtl8723E\\radio_b_1T.txt"
++ #define RTL8723_AGC_TAB "rtl8723E\\AGC_TAB_1T.txt"
++ #define RTL8723_PHY_MACREG "rtl8723E\\MAC_REG.txt"
++ #define RTL8723_PHY_MACREG "rtl8723E\\MAC_REG.txt"
++ #define RTL8723_PHY_REG_PG "rtl8723E\\PHY_REG_PG.txt"
++ #define RTL8723_PHY_REG_MP "rtl8723E\\PHY_REG_MP.txt"
++
++ // The file name "_2T" is for 92CE, "_1T" is for 88CE. Modified by tynli. 2009.11.24.
++ #define Rtl819XFwTSMCImageArray Rtl8192CEFwTSMCImgArray
++ #define Rtl819XFwUMCACutImageArray Rtl8192CEFwUMCACutImgArray
++ #define Rtl819XFwUMCBCutImageArray Rtl8192CEFwUMCBCutImgArray
++
++ #define Rtl8723FwUMCImageArray Rtl8192CEFwUMC8723ImgArray
++ #define Rtl819XMAC_Array Rtl8192CEMAC_2T_Array
++ #define Rtl819XAGCTAB_2TArray Rtl8192CEAGCTAB_2TArray
++ #define Rtl819XAGCTAB_1TArray Rtl8192CEAGCTAB_1TArray
++ #define Rtl819XPHY_REG_2TArray Rtl8192CEPHY_REG_2TArray
++ #define Rtl819XPHY_REG_1TArray Rtl8192CEPHY_REG_1TArray
++ #define Rtl819XRadioA_2TArray Rtl8192CERadioA_2TArray
++ #define Rtl819XRadioA_1TArray Rtl8192CERadioA_1TArray
++ #define Rtl819XRadioB_2TArray Rtl8192CERadioB_2TArray
++ #define Rtl819XRadioB_1TArray Rtl8192CERadioB_1TArray
++ #define Rtl819XPHY_REG_Array_PG Rtl8192CEPHY_REG_Array_PG
++ #define Rtl819XPHY_REG_Array_MP Rtl8192CEPHY_REG_Array_MP
++
++#elif defined(CONFIG_USB_HCI)
++
++ #include "Hal8192CUHWImg.h"
++#ifdef CONFIG_WOWLAN
++ #include "Hal8192CUHWImg_wowlan.h"
++#endif //CONFIG_WOWLAN
++ //2TODO: We should define 8192S firmware related macro settings here!!
++ #define RTL819X_DEFAULT_RF_TYPE RF_1T2R
++ #define RTL819X_TOTAL_RF_PATH 2
++
++ //TODO: The following need to check!!
++ #define RTL8192C_FW_TSMC_IMG "rtl8192CU\\rtl8192cfwT.bin"
++ #define RTL8192C_FW_UMC_IMG "rtl8192CU\\rtl8192cfwU.bin"
++ #define RTL8192C_FW_UMC_B_IMG "rtl8192CU\\rtl8192cfwU_B.bin"
++#ifdef CONFIG_WOWLAN
++ #define RTL8192C_FW_TSMC_WW_IMG "rtl8192CU\\rtl8192cfwTww.bin"
++ #define RTL8192C_FW_UMC_WW_IMG "rtl8192CU\\rtl8192cfwUww.bin"
++ #define RTL8192C_FW_UMC_B_WW_IMG "rtl8192CU\\rtl8192cfwU_Bww.bin"
++#endif // CONFIG_WOWLAN
++ //#define RTL819X_FW_BOOT_IMG "rtl8192CU\\boot.img"
++ //#define RTL819X_FW_MAIN_IMG "rtl8192CU\\main.img"
++ //#define RTL819X_FW_DATA_IMG "rtl8192CU\\data.img"
++
++ #define RTL8188C_PHY_REG "rtl8188CU\\PHY_REG.txt"
++ #define RTL8188C_PHY_RADIO_A "rtl8188CU\\radio_a.txt"
++ #define RTL8188C_PHY_RADIO_B "rtl8188CU\\radio_b.txt"
++ #define RTL8188C_PHY_RADIO_A_mCard "rtl8192CU\\radio_a_1T_mCard.txt"
++ #define RTL8188C_PHY_RADIO_B_mCard "rtl8192CU\\radio_b_1T_mCard.txt"
++ #define RTL8188C_PHY_RADIO_A_HP "rtl8192CU\\radio_a_1T_HP.txt"
++ #define RTL8188C_AGC_TAB "rtl8188CU\\AGC_TAB.txt"
++ #define RTL8188C_PHY_MACREG "rtl8188CU\\MACREG.txt"
++
++ #define RTL8192C_PHY_REG "rtl8192CU\\PHY_REG.txt"
++ #define RTL8192C_PHY_RADIO_A "rtl8192CU\\radio_a.txt"
++ #define RTL8192C_PHY_RADIO_B "rtl8192CU\\radio_b.txt"
++ #define RTL8192C_AGC_TAB "rtl8192CU\\AGC_TAB.txt"
++ #define RTL8192C_PHY_MACREG "rtl8192CU\\MACREG.txt"
++
++ #define RTL819X_PHY_REG_PG "rtl8192CU\\PHY_REG_PG.txt"
++
++//---------------------------------------------------------------------
++// RTL8723U From file
++//---------------------------------------------------------------------
++ #define RTL8723_FW_UMC_IMG "rtl8723U\\rtl8723fw.bin"
++ #define RTL8723_PHY_REG "rtl8723U\\PHY_REG_1T.txt"
++ #define RTL8723_PHY_RADIO_A "rtl8723U\\radio_a_1T.txt"
++ #define RTL8723_PHY_RADIO_B "rtl8723U\\radio_b_1T.txt"
++ #define RTL8723_AGC_TAB "rtl8723U\\AGC_TAB_1T.txt"
++ #define RTL8723_PHY_MACREG "rtl8723U\\MAC_REG.txt"
++ #define RTL8723_PHY_MACREG "rtl8723U\\MAC_REG.txt"
++ #define RTL8723_PHY_REG_PG "rtl8723U\\PHY_REG_PG.txt"
++ #define RTL8723_PHY_REG_MP "rtl8723U\\PHY_REG_MP.txt"
++
++ // The file name "_2T" is for 92CU, "_1T" is for 88CU. Modified by tynli. 2009.11.24.
++ #define Rtl819XFwImageArray Rtl8192CUFwTSMCImgArray
++ #define Rtl819XFwTSMCImageArray Rtl8192CUFwTSMCImgArray
++ #define Rtl819XFwUMCACutImageArray Rtl8192CUFwUMCACutImgArray
++ #define Rtl819XFwUMCBCutImageArray Rtl8192CUFwUMCBCutImgArray
++#ifdef CONFIG_WOWLAN
++ #define Rtl8192C_FwTSMCWWImageArray Rtl8192CUFwTSMCWWImgArray
++ #define Rtl8192C_FwUMCWWImageArray Rtl8192CUFwUMCACutWWImgArray
++ #define Rtl8192C_FwUMCBCutWWImageArray Rtl8192CUFwUMCBCutWWImgArray
++#endif //CONFIG_WOWLAN
++ #define Rtl819XMAC_Array Rtl8192CUMAC_2T_Array
++ #define Rtl819XAGCTAB_2TArray Rtl8192CUAGCTAB_2TArray
++ #define Rtl819XAGCTAB_1TArray Rtl8192CUAGCTAB_1TArray
++ #define Rtl819XAGCTAB_1T_HPArray Rtl8192CUAGCTAB_1T_HPArray
++ #define Rtl819XPHY_REG_2TArray Rtl8192CUPHY_REG_2TArray
++ #define Rtl819XPHY_REG_1TArray Rtl8192CUPHY_REG_1TArray
++ #define Rtl819XPHY_REG_1T_mCardArray Rtl8192CUPHY_REG_1T_mCardArray
++ #define Rtl819XPHY_REG_2T_mCardArray Rtl8192CUPHY_REG_2T_mCardArray
++ #define Rtl819XPHY_REG_1T_HPArray Rtl8192CUPHY_REG_1T_HPArray
++ #define Rtl819XRadioA_2TArray Rtl8192CURadioA_2TArray
++ #define Rtl819XRadioA_1TArray Rtl8192CURadioA_1TArray
++ #define Rtl819XRadioA_1T_mCardArray Rtl8192CURadioA_1T_mCardArray
++ #define Rtl819XRadioB_2TArray Rtl8192CURadioB_2TArray
++ #define Rtl819XRadioB_1TArray Rtl8192CURadioB_1TArray
++ #define Rtl819XRadioB_1T_mCardArray Rtl8192CURadioB_1T_mCardArray
++ #define Rtl819XRadioA_1T_HPArray Rtl8192CURadioA_1T_HPArray
++ #define Rtl819XPHY_REG_Array_PG Rtl8192CUPHY_REG_Array_PG
++ #define Rtl819XPHY_REG_Array_PG_mCard Rtl8192CUPHY_REG_Array_PG_mCard
++ #define Rtl819XPHY_REG_Array_PG_HP Rtl8192CUPHY_REG_Array_PG_HP
++ #define Rtl819XPHY_REG_Array_MP Rtl8192CUPHY_REG_Array_MP
++#endif
++
++#define DRVINFO_SZ 4 // unit is 8bytes
++#define PageNum_128(_Len) (u32)(((_Len)>>7) + ((_Len)&0x7F ? 1:0))
++
++#define FW_8192C_SIZE 16384+32//16k
++#define FW_8192C_START_ADDRESS 0x1000
++//#define FW_8192C_END_ADDRESS 0x3FFF //Filen said this is for test chip
++#define FW_8192C_END_ADDRESS 0x1FFF
++
++#define MAX_PAGE_SIZE 4096 // @ page : 4k bytes
++
++#define IS_FW_HEADER_EXIST(_pFwHdr) ((le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x92C0 ||\
++ (le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x88C0 ||\
++ (le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x2300)
++
++typedef enum _FIRMWARE_SOURCE{
++ FW_SOURCE_IMG_FILE = 0,
++ FW_SOURCE_HEADER_FILE = 1, //from header file
++}FIRMWARE_SOURCE, *PFIRMWARE_SOURCE;
++
++typedef struct _RT_FIRMWARE{
++ FIRMWARE_SOURCE eFWSource;
++ u8* szFwBuffer;
++ u32 ulFwLength;
++#ifdef CONFIG_WOWLAN
++ u8* szWoWLANFwBuffer;
++ u32 ulWoWLANFwLength;
++#endif //CONFIG_WOWLAN
++}RT_FIRMWARE, *PRT_FIRMWARE, RT_FIRMWARE_92C, *PRT_FIRMWARE_92C;
++
++//
++// This structure must be cared byte-ordering
++//
++// Added by tynli. 2009.12.04.
++typedef struct _RT_8192C_FIRMWARE_HDR {//8-byte alinment required
++
++ //--- LONG WORD 0 ----
++ u16 Signature; // 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut
++ u8 Category; // AP/NIC and USB/PCI
++ u8 Function; // Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions
++ u16 Version; // FW Version
++ u8 Subversion; // FW Subversion, default 0x00
++ u16 Rsvd1;
++
++
++ //--- LONG WORD 1 ----
++ u8 Month; // Release time Month field
++ u8 Date; // Release time Date field
++ u8 Hour; // Release time Hour field
++ u8 Minute; // Release time Minute field
++ u16 RamCodeSize; // The size of RAM code
++ u16 Rsvd2;
++
++ //--- LONG WORD 2 ----
++ u32 SvnIdx; // The SVN entry index
++ u32 Rsvd3;
++
++ //--- LONG WORD 3 ----
++ u32 Rsvd4;
++ u32 Rsvd5;
++
++}RT_8192C_FIRMWARE_HDR, *PRT_8192C_FIRMWARE_HDR;
++
++#define DRIVER_EARLY_INT_TIME 0x05
++#define BCN_DMA_ATIME_INT_TIME 0x02
++
++#ifdef CONFIG_USB_RX_AGGREGATION
++
++typedef enum _USB_RX_AGG_MODE{
++ USB_RX_AGG_DISABLE,
++ USB_RX_AGG_DMA,
++ USB_RX_AGG_USB,
++ USB_RX_AGG_MIX
++}USB_RX_AGG_MODE;
++
++#define MAX_RX_DMA_BUFFER_SIZE 10240 // 10K for 8192C RX DMA buffer
++
++#endif
++
++
++#define TX_SELE_HQ BIT(0) // High Queue
++#define TX_SELE_LQ BIT(1) // Low Queue
++#define TX_SELE_NQ BIT(2) // Normal Queue
++
++
++// Note: We will divide number of page equally for each queue other than public queue!
++
++#define TX_TOTAL_PAGE_NUMBER 0xF8
++#define TX_PAGE_BOUNDARY (TX_TOTAL_PAGE_NUMBER + 1)
++
++// For Normal Chip Setting
++// (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER
++#define NORMAL_PAGE_NUM_PUBQ 0xE7
++#define NORMAL_PAGE_NUM_HPQ 0x0C
++#define NORMAL_PAGE_NUM_LPQ 0x02
++#define NORMAL_PAGE_NUM_NPQ 0x02
++
++
++// For Test Chip Setting
++// (HPQ + LPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER
++#define TEST_PAGE_NUM_PUBQ 0x7E
++
++
++// For Test Chip Setting
++#define WMM_TEST_TX_TOTAL_PAGE_NUMBER 0xF5
++#define WMM_TEST_TX_PAGE_BOUNDARY (WMM_TEST_TX_TOTAL_PAGE_NUMBER + 1) //F6
++
++#define WMM_TEST_PAGE_NUM_PUBQ 0xA3
++#define WMM_TEST_PAGE_NUM_HPQ 0x29
++#define WMM_TEST_PAGE_NUM_LPQ 0x29
++
++
++//Note: For Normal Chip Setting ,modify later
++#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER 0xF5
++#define WMM_NORMAL_TX_PAGE_BOUNDARY (WMM_TEST_TX_TOTAL_PAGE_NUMBER + 1) //F6
++
++#define WMM_NORMAL_PAGE_NUM_PUBQ 0x65
++#define WMM_NORMAL_PAGE_NUM_HPQ 0x30
++#define WMM_NORMAL_PAGE_NUM_LPQ 0x30
++#define WMM_NORMAL_PAGE_NUM_NPQ 0x30
++
++//-------------------------------------------------------------------------
++// Chip specific
++//-------------------------------------------------------------------------
++#define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3)
++#define CHIP_BONDING_92C_1T2R 0x1
++#define CHIP_BONDING_88C_USB_MCARD 0x2
++#define CHIP_BONDING_88C_USB_HP 0x1
++
++//
++// 2011.01.06. Define new structure of chip version for RTL8723 and so on. Added by tynli.
++//
++/*
++ | BIT15:12 | BIT11:8 | BIT 7 | BIT6:4 | BIT3 | BIT2:0 |
++ |-------------+-----------+-----------+-------+-----------+-------|
++ | IC version(CUT) | ROM version | Manufacturer | RF type | Chip type | IC Type |
++ | | | TSMC/UMC | | TEST/NORMAL| |
++*/
++// [15:12] IC version(CUT): A-cut=0, B-cut=1, C-cut=2, D-cut=3
++// [7] Manufacturer: TSMC=0, UMC=1
++// [6:4] RF type: 1T1R=0, 1T2R=1, 2T2R=2
++// [3] Chip type: TEST=0, NORMAL=1
++// [2:0] IC type: 81xxC=0, 8723=1, 92D=2
++
++#define CHIP_8723 BIT(0)
++#define CHIP_92D BIT(1)
++#define NORMAL_CHIP BIT(3)
++#define RF_TYPE_1T1R (~(BIT(4)|BIT(5)|BIT(6)))
++#define RF_TYPE_1T2R BIT(4)
++#define RF_TYPE_2T2R BIT(5)
++#define CHIP_VENDOR_UMC BIT(7)
++#define B_CUT_VERSION BIT(12)
++#define C_CUT_VERSION BIT(13)
++#define D_CUT_VERSION ((BIT(13)|BIT(14)))
++
++
++// MASK
++#define IC_TYPE_MASK (BIT(0)|BIT(1)|BIT(2))
++#define CHIP_TYPE_MASK BIT(3)
++#define RF_TYPE_MASK (BIT(4)|BIT(5)|BIT(6))
++#define MANUFACTUER_MASK BIT(7)
++#define ROM_VERSION_MASK (BIT(11)|BIT(10)|BIT(9)|BIT(8))
++#define CUT_VERSION_MASK (BIT(15)|BIT(14)|BIT(13)|BIT(12))
++
++// Get element
++#define GET_CVID_IC_TYPE(version) ((version) & IC_TYPE_MASK)
++#define GET_CVID_CHIP_TYPE(version) ((version) & CHIP_TYPE_MASK)
++#define GET_CVID_RF_TYPE(version) ((version) & RF_TYPE_MASK)
++#define GET_CVID_MANUFACTUER(version) ((version) & MANUFACTUER_MASK)
++#define GET_CVID_ROM_VERSION(version) ((version) & ROM_VERSION_MASK)
++#define GET_CVID_CUT_VERSION(version) ((version) & CUT_VERSION_MASK)
++
++#define IS_81XXC(version) ((GET_CVID_IC_TYPE(version) == 0)? _TRUE : _FALSE)
++#define IS_8723_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8723)? _TRUE : _FALSE)
++#define IS_92D(version) ((GET_CVID_IC_TYPE(version) == CHIP_92D)? _TRUE : _FALSE)
++#define IS_1T1R(version) ((GET_CVID_RF_TYPE(version))? _FALSE : _TRUE)
++#define IS_1T2R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_1T2R)? _TRUE : _FALSE)
++#define IS_2T2R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_2T2R)? _TRUE : _FALSE)
++#define IS_NORMAL_CHIP(version) ((GET_CVID_CHIP_TYPE(version))? _TRUE: _FALSE)
++#define IS_CHIP_VENDOR_UMC(version) ((GET_CVID_MANUFACTUER(version))? _TRUE: _FALSE)
++
++#define IS_81XXC_TEST_CHIP(version) ((IS_81XXC(version) && (!IS_NORMAL_CHIP(version)))? _TRUE: _FALSE)
++#define IS_92D_TEST_CHIP(version) ((IS_92D(version) && (!IS_NORMAL_CHIP(version)))? _TRUE: _FALSE)
++#define IS_92C_SERIAL(version) ((IS_81XXC(version) && IS_2T2R(version)) ? _TRUE : _FALSE)
++#define IS_VENDOR_UMC_A_CUT(version) ((IS_CHIP_VENDOR_UMC(version)) ? ((GET_CVID_CUT_VERSION(version)) ? _FALSE : _TRUE) : _FALSE)
++#define IS_VENDOR_8723_A_CUT(version) ((IS_8723_SERIES(version)) ? ((GET_CVID_CUT_VERSION(version)) ? _FALSE : _TRUE) : _FALSE)
++// <tynli_Note> 88/92C UMC B-cut vendor is set to TSMC so we need to check CHIP_VENDOR_UMC bit is not 1.
++#define IS_81xxC_VENDOR_UMC_B_CUT(version) ((IS_CHIP_VENDOR_UMC(version)) ? ((GET_CVID_CUT_VERSION(version) == B_CUT_VERSION) ? _TRUE : _FALSE):_FALSE)
++#define IS_92D_SINGLEPHY(version) ((IS_92D(version)) ? (IS_2T2R(version) ? _TRUE: _FALSE) : _FALSE)
++#define IS_92D_C_CUT(version) ((IS_92D(version)) ? ((GET_CVID_CUT_VERSION(version) == 0x2) ? _TRUE : _FALSE) : _FALSE)
++#define IS_92D_D_CUT(version) ((IS_92D(version)) ? ((GET_CVID_CUT_VERSION(version) == 0x3) ? _TRUE : _FALSE) : _FALSE)
++
++typedef enum _VERSION_8192C{
++ VERSION_TEST_CHIP_88C = 0x0000,
++ VERSION_TEST_CHIP_92C = 0x0020,
++ VERSION_TEST_UMC_CHIP_8723 = 0x0081,
++ VERSION_NORMAL_TSMC_CHIP_88C = 0x0008,
++ VERSION_NORMAL_TSMC_CHIP_92C = 0x0028,
++ VERSION_NORMAL_TSMC_CHIP_92C_1T2R = 0x0018,
++ VERSION_NORMAL_UMC_CHIP_88C_A_CUT = 0x0088,
++ VERSION_NORMAL_UMC_CHIP_92C_A_CUT = 0x00a8,
++ VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT = 0x0098,
++ VERSION_NORMAL_UMC_CHIP_8723_1T1R_A_CUT = 0x0089,
++ VERSION_NORMAL_UMC_CHIP_8723_1T1R_B_CUT = 0x1089,
++ VERSION_NORMAL_UMC_CHIP_88C_B_CUT = 0x1088,
++ VERSION_NORMAL_UMC_CHIP_92C_B_CUT = 0x10a8,
++ VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT = 0x1090,
++ VERSION_TEST_CHIP_92D_SINGLEPHY= 0x0022,
++ VERSION_TEST_CHIP_92D_DUALPHY = 0x0002,
++ VERSION_NORMAL_CHIP_92D_SINGLEPHY= 0x002a,
++ VERSION_NORMAL_CHIP_92D_DUALPHY = 0x000a,
++ VERSION_NORMAL_CHIP_92D_C_CUT_SINGLEPHY = 0x202a,
++ VERSION_NORMAL_CHIP_92D_C_CUT_DUALPHY = 0x200a,
++ VERSION_NORMAL_CHIP_92D_D_CUT_SINGLEPHY = 0x302a,
++ VERSION_NORMAL_CHIP_92D_D_CUT_DUALPHY = 0x300a,
++}VERSION_8192C,*PVERSION_8192C;
++
++
++
++//-------------------------------------------------------------------------
++// Channel Plan
++//-------------------------------------------------------------------------
++enum ChannelPlan{
++ CHPL_FCC = 0,
++ CHPL_IC = 1,
++ CHPL_ETSI = 2,
++ CHPL_SPAIN = 3,
++ CHPL_FRANCE = 4,
++ CHPL_MKK = 5,
++ CHPL_MKK1 = 6,
++ CHPL_ISRAEL = 7,
++ CHPL_TELEC = 8,
++ CHPL_GLOBAL = 9,
++ CHPL_WORLD = 10,
++};
++
++typedef struct _TxPowerInfo{
++ u8 CCKIndex[RF_PATH_MAX][CHANNEL_GROUP_MAX];
++ u8 HT40_1SIndex[RF_PATH_MAX][CHANNEL_GROUP_MAX];
++ u8 HT40_2SIndexDiff[RF_PATH_MAX][CHANNEL_GROUP_MAX];
++ s8 HT20IndexDiff[RF_PATH_MAX][CHANNEL_GROUP_MAX];
++ u8 OFDMIndexDiff[RF_PATH_MAX][CHANNEL_GROUP_MAX];
++ u8 HT40MaxOffset[RF_PATH_MAX][CHANNEL_GROUP_MAX];
++ u8 HT20MaxOffset[RF_PATH_MAX][CHANNEL_GROUP_MAX];
++ u8 TSSI_A;
++ u8 TSSI_B;
++}TxPowerInfo, *PTxPowerInfo;
++
++#define EFUSE_REAL_CONTENT_LEN 512
++#define EFUSE_MAP_LEN 128
++#define EFUSE_MAX_SECTION 16
++#define EFUSE_IC_ID_OFFSET 506 //For some inferiority IC purpose. added by Roger, 2009.09.02.
++#define AVAILABLE_EFUSE_ADDR(addr) (addr < EFUSE_REAL_CONTENT_LEN)
++//
++// <Roger_Notes> To prevent out of boundary programming case, leave 1byte and program full section
++// 9bytes + 1byt + 5bytes and pre 1byte.
++// For worst case:
++// | 1byte|----8bytes----|1byte|--5bytes--|
++// | | Reserved(14bytes) |
++//
++#define EFUSE_OOB_PROTECT_BYTES 15 // PG data exclude header, dummy 6 bytes frome CP test and reserved 1byte.
++
++
++#define EFUSE_MAP_LEN_8723 256
++#define EFUSE_MAX_SECTION_8723 32
++
++//========================================================
++// EFUSE for BT definition
++//========================================================
++#define EFUSE_BT_REAL_CONTENT_LEN 1536 // 512*3
++#define EFUSE_BT_MAP_LEN 1024 // 1k bytes
++#define EFUSE_BT_MAX_SECTION 128 // 1024/8
++
++#define EFUSE_PROTECT_BYTES_BANK 16
++
++//
++// <Roger_Notes> For RTL8723 WiFi/BT/GPS multi-function configuration. 2010.10.06.
++//
++typedef enum _RT_MULTI_FUNC{
++ RT_MULTI_FUNC_NONE = 0x00,
++ RT_MULTI_FUNC_WIFI = 0x01,
++ RT_MULTI_FUNC_BT = 0x02,
++ RT_MULTI_FUNC_GPS = 0x04,
++}RT_MULTI_FUNC,*PRT_MULTI_FUNC;
++
++//
++// <Roger_Notes> For RTL8723 WiFi PDn/GPIO polarity control configuration. 2010.10.08.
++//
++typedef enum _RT_POLARITY_CTL{
++ RT_POLARITY_LOW_ACT = 0,
++ RT_POLARITY_HIGH_ACT = 1,
++}RT_POLARITY_CTL,*PRT_POLARITY_CTL;
++
++// For RTL8723 regulator mode. by tynli. 2011.01.14.
++typedef enum _RT_REGULATOR_MODE{
++ RT_SWITCHING_REGULATOR = 0,
++ RT_LDO_REGULATOR = 1,
++}RT_REGULATOR_MODE,*PRT_REGULATOR_MODE;
++
++enum c2h_id_8192c {
++ C2H_DBG = 0,
++ C2H_TSF = 1,
++ C2H_AP_RPT_RSP = 2,
++ C2H_CCX_TX_RPT = 3,
++ C2H_BT_RSSI = 4,
++ C2H_BT_OP_MODE = 5,
++ C2H_EXT_RA_RPT = 6,
++ C2H_HW_INFO_EXCH = 10,
++ C2H_C2H_H2C_TEST = 11,
++ C2H_BT_INFO = 12,
++ C2H_BT_MP_INFO = 15,
++ MAX_C2HEVENT
++};
++
++#ifdef CONFIG_PCI_HCI
++struct hal_data_8192ce
++{
++ VERSION_8192C VersionID;
++ RT_MULTI_FUNC MultiFunc; // For multi-function consideration.
++ RT_POLARITY_CTL PolarityCtl; // For Wifi PDn Polarity control.
++ RT_REGULATOR_MODE RegulatorMode; // switching regulator or LDO
++ u16 CustomerID;
++
++ u16 FirmwareVersion;
++ u16 FirmwareVersionRev;
++ u16 FirmwareSubVersion;
++
++ u32 IntrMask[2];
++ u32 IntrMaskToSet[2];
++
++ u32 DisabledFunctions;
++
++ //current WIFI_PHY values
++ u32 ReceiveConfig;
++ u32 TransmitConfig;
++ WIRELESS_MODE CurrentWirelessMode;
++ HT_CHANNEL_WIDTH CurrentChannelBW;
++ u8 CurrentChannel;
++ u8 nCur40MhzPrimeSC;// Control channel sub-carrier
++
++ u16 BasicRateSet;
++
++ //rf_ctrl
++ _lock rf_lock;
++ u8 rf_chip;
++ u8 rf_type;
++ u8 NumTotalRFPath;
++
++ INTERFACE_SELECT_8192CPCIe InterfaceSel;
++
++ //
++ // EEPROM setting.
++ //
++ u16 EEPROMVID;
++ u16 EEPROMDID;
++ u16 EEPROMSVID;
++ u16 EEPROMSMID;
++ u16 EEPROMChannelPlan;
++ u16 EEPROMVersion;
++
++ u8 EEPROMChnlAreaTxPwrCCK[2][3];
++ u8 EEPROMChnlAreaTxPwrHT40_1S[2][3];
++ u8 EEPROMChnlAreaTxPwrHT40_2SDiff[2][3];
++ u8 EEPROMPwrLimitHT20[3];
++ u8 EEPROMPwrLimitHT40[3];
++
++ u8 bTXPowerDataReadFromEEPORM;
++ u8 EEPROMThermalMeter;
++ u8 EEPROMTSSI[2];
++
++ u8 EEPROMCustomerID;
++ u8 EEPROMBoardType;
++ u8 EEPROMRegulatory;
++
++ u8 bDefaultAntenna;
++ u8 bIQKInitialized;
++
++ u8 TxPwrLevelCck[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
++ u8 TxPwrLevelHT40_1S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr
++ u8 TxPwrLevelHT40_2S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr
++ s8 TxPwrHt20Diff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// HT 20<->40 Pwr diff
++ u8 TxPwrLegacyHtDiff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// For HT<->legacy pwr diff
++ // For power group
++ u8 PwrGroupHT20[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
++ u8 PwrGroupHT40[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
++
++ u8 LegacyHTTxPowerDiff;// Legacy to HT rate power diff
++
++#ifdef CONFIG_BT_COEXIST
++ struct btcoexist_priv bt_coexist;
++#endif
++
++ // Read/write are allow for following hardware information variables
++ u8 framesync;
++ u32 framesyncC34;
++ u8 framesyncMonitor;
++ u8 DefaultInitialGain[4];
++ u8 pwrGroupCnt;
++ u32 MCSTxPowerLevelOriginalOffset[7][16];
++ u32 CCKTxPowerLevelOriginalOffset;
++
++ u32 AntennaTxPath; // Antenna path Tx
++ u32 AntennaRxPath; // Antenna path Rx
++ u8 BluetoothCoexist;
++ u8 ExternalPA;
++
++ //u32 LedControlNum;
++ //u32 LedControlMode;
++ u8 bLedOpenDrain; // Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16.
++ //u32 TxPowerTrackControl;
++ u8 b1x1RecvCombine; // for 1T1R receive combining
++
++ u8 bCurrentTurboEDCA;
++ u32 AcParam_BE; //Original parameter for BE, use for EDCA turbo.
++
++ //vivi, for tx power tracking, 20080407
++ //u16 TSSI_13dBm;
++ //u32 Pwr_Track;
++ // The current Tx Power Level
++ u8 CurrentCckTxPwrIdx;
++ u8 CurrentOfdm24GTxPwrIdx;
++
++ BB_REGISTER_DEFINITION_T PHYRegDef[4]; //Radio A/B/C/D
++
++ BOOLEAN bRFPathRxEnable[4]; // We support 4 RF path now.
++
++ u32 RfRegChnlVal[2];
++
++ u8 bCckHighPower;
++
++ //RDG enable
++ BOOLEAN bRDGEnable;
++
++ //for host message to fw
++ u8 LastHMEBoxNum;
++
++ u8 fw_ractrl;
++ u8 RegTxPause;
++ // Beacon function related global variable.
++ u32 RegBcnCtrlVal;
++ u8 RegFwHwTxQCtrl;
++ u8 RegReg542;
++ u8 CurAntenna;
++ u8 AntDivCfg;
++
++#ifdef CONFIG_SW_ANTENNA_DIVERSITY
++ //SW Antenna Switch
++ s32 RSSI_sum_A;
++ s32 RSSI_sum_B;
++ s32 RSSI_cnt_A;
++ s32 RSSI_cnt_B;
++ BOOLEAN RSSI_test;
++#endif
++#ifdef CONFIG_HW_ANTENNA_DIVERSITY
++ //Hybrid Antenna Diversity
++ u32 CCK_Ant1_Cnt;
++ u32 CCK_Ant2_Cnt;
++ u32 OFDM_Ant1_Cnt;
++ u32 OFDM_Ant2_Cnt;
++#endif
++
++ struct dm_priv dmpriv;
++ u8 bDumpRxPkt;//for debug
++#ifdef DBG_CONFIG_ERROR_DETECT
++ struct sreset_priv srestpriv;
++#endif
++ u8 bInterruptMigration;
++ u8 bDisableTxInt;
++ u8 bGpioHwWpsPbc;
++
++ u8 FwRsvdPageStartOffset; //2010.06.23. Added by tynli. Reserve page start offset except beacon in TxQ.
++
++ u16 EfuseUsedBytes;
++
++#ifdef CONFIG_P2P
++ struct P2P_PS_Offload_t p2p_ps_offload;
++#endif //CONFIG_P2P
++};
++
++typedef struct hal_data_8192ce HAL_DATA_TYPE, *PHAL_DATA_TYPE;
++
++//
++// Function disabled.
++//
++#define DF_TX_BIT BIT0
++#define DF_RX_BIT BIT1
++#define DF_IO_BIT BIT2
++#define DF_IO_D3_BIT BIT3
++
++#define RT_DF_TYPE u32
++#define RT_DISABLE_FUNC(__pAdapter, __FuncBits) ((__pAdapter)->DisabledFunctions |= ((RT_DF_TYPE)(__FuncBits)))
++#define RT_ENABLE_FUNC(__pAdapter, __FuncBits) ((__pAdapter)->DisabledFunctions &= (~((RT_DF_TYPE)(__FuncBits))))
++#define RT_IS_FUNC_DISABLED(__pAdapter, __FuncBits) ( (__pAdapter)->DisabledFunctions & (__FuncBits) )
++#define IS_MULTI_FUNC_CHIP(_Adapter) (((((PHAL_DATA_TYPE)(_Adapter->HalData))->MultiFunc) & (RT_MULTI_FUNC_BT|RT_MULTI_FUNC_GPS)) ? _TRUE : _FALSE)
++
++void InterruptRecognized8192CE(PADAPTER Adapter, PRT_ISR_CONTENT pIsrContent);
++VOID UpdateInterruptMask8192CE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);
++#endif
++
++#ifdef CONFIG_USB_HCI
++struct hal_data_8192cu
++{
++ VERSION_8192C VersionID;
++ RT_MULTI_FUNC MultiFunc; // For multi-function consideration.
++ RT_POLARITY_CTL PolarityCtl; // For Wifi PDn Polarity control.
++ RT_REGULATOR_MODE RegulatorMode; // switching regulator or LDO
++ u16 CustomerID;
++
++ u16 FirmwareVersion;
++ u16 FirmwareVersionRev;
++ u16 FirmwareSubVersion;
++
++ //current WIFI_PHY values
++ u32 ReceiveConfig;
++ WIRELESS_MODE CurrentWirelessMode;
++ HT_CHANNEL_WIDTH CurrentChannelBW;
++ u8 CurrentChannel;
++ u8 nCur40MhzPrimeSC;// Control channel sub-carrier
++
++ u16 BasicRateSet;
++
++ //rf_ctrl
++ u8 rf_chip;
++ u8 rf_type;
++ u8 NumTotalRFPath;
++
++ u8 BoardType;
++ //INTERFACE_SELECT_8192CUSB InterfaceSel;
++
++ //
++ // EEPROM setting.
++ //
++ u16 EEPROMVID;
++ u16 EEPROMPID;
++ u16 EEPROMSVID;
++ u16 EEPROMSDID;
++ u8 EEPROMCustomerID;
++ u8 EEPROMSubCustomerID;
++ u8 EEPROMVersion;
++ u8 EEPROMRegulatory;
++
++ u8 bTXPowerDataReadFromEEPORM;
++ u8 EEPROMThermalMeter;
++
++ u8 bIQKInitialized;
++
++ u8 TxPwrLevelCck[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
++ u8 TxPwrLevelHT40_1S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr
++ u8 TxPwrLevelHT40_2S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr
++ s8 TxPwrHt20Diff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// HT 20<->40 Pwr diff
++ u8 TxPwrLegacyHtDiff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// For HT<->legacy pwr diff
++ // For power group
++ u8 PwrGroupHT20[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
++ u8 PwrGroupHT40[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
++
++ u8 LegacyHTTxPowerDiff;// Legacy to HT rate power diff
++
++ // Read/write are allow for following hardware information variables
++ u8 framesync;
++ u32 framesyncC34;
++ u8 framesyncMonitor;
++ u8 DefaultInitialGain[4];
++ u8 pwrGroupCnt;
++ u32 MCSTxPowerLevelOriginalOffset[7][16];
++ u32 CCKTxPowerLevelOriginalOffset;
++
++ u32 AntennaTxPath; // Antenna path Tx
++ u32 AntennaRxPath; // Antenna path Rx
++ u8 BluetoothCoexist;
++ u8 ExternalPA;
++
++ u8 bLedOpenDrain; // Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16.
++
++ //u32 LedControlNum;
++ //u32 LedControlMode;
++ //u32 TxPowerTrackControl;
++ u8 b1x1RecvCombine; // for 1T1R receive combining
++
++ u8 bCurrentTurboEDCA;
++ u32 AcParam_BE; //Original parameter for BE, use for EDCA turbo.
++
++ //vivi, for tx power tracking, 20080407
++ //u16 TSSI_13dBm;
++ //u32 Pwr_Track;
++ // The current Tx Power Level
++ u8 CurrentCckTxPwrIdx;
++ u8 CurrentOfdm24GTxPwrIdx;
++
++ BB_REGISTER_DEFINITION_T PHYRegDef[4]; //Radio A/B/C/D
++
++ BOOLEAN bRFPathRxEnable[4]; // We support 4 RF path now.
++
++ u32 RfRegChnlVal[2];
++
++ u8 bCckHighPower;
++
++ //RDG enable
++ BOOLEAN bRDGEnable;
++
++ //for host message to fw
++ u8 LastHMEBoxNum;
++
++ u8 fw_ractrl;
++ u8 RegTxPause;
++ // Beacon function related global variable.
++ u32 RegBcnCtrlVal;
++ u8 RegFwHwTxQCtrl;
++ u8 RegReg542;
++
++ struct dm_priv dmpriv;
++#ifdef DBG_CONFIG_ERROR_DETECT
++ struct sreset_priv srestpriv;
++#endif
++
++#ifdef CONFIG_BT_COEXIST
++ struct btcoexist_priv bt_coexist;
++#endif
++ u8 CurAntenna;
++ u8 AntDivCfg;
++
++#ifdef CONFIG_SW_ANTENNA_DIVERSITY
++ //SW Antenna Switch
++ s32 RSSI_sum_A;
++ s32 RSSI_sum_B;
++ s32 RSSI_cnt_A;
++ s32 RSSI_cnt_B;
++ BOOLEAN RSSI_test;
++#endif
++#ifdef CONFIG_HW_ANTENNA_DIVERSITY
++ //Hybrid Antenna Diversity
++ u32 CCK_Ant1_Cnt;
++ u32 CCK_Ant2_Cnt;
++ u32 OFDM_Ant1_Cnt;
++ u32 OFDM_Ant2_Cnt;
++#endif
++
++ u8 bDumpRxPkt;//for debug
++ u8 FwRsvdPageStartOffset; //2010.06.23. Added by tynli. Reserve page start offset except beacon in TxQ.
++
++ // 2010/08/09 MH Add CU power down mode.
++ BOOLEAN pwrdown;
++
++ // For 92C USB endpoint setting
++ //
++
++ u32 UsbBulkOutSize;
++
++ int RtBulkOutPipe[3];
++ int RtBulkInPipe;
++ int RtIntInPipe;
++ // Add for dual MAC 0--Mac0 1--Mac1
++ u32 interfaceIndex;
++
++ u8 OutEpQueueSel;
++ u8 OutEpNumber;
++
++ u8 Queue2EPNum[8];//for out endpoint number mapping
++
++#ifdef CONFIG_USB_TX_AGGREGATION
++ u8 UsbTxAggMode;
++ u8 UsbTxAggDescNum;
++#endif
++#ifdef CONFIG_USB_RX_AGGREGATION
++ u16 HwRxPageSize; // Hardware setting
++ u32 MaxUsbRxAggBlock;
++
++ USB_RX_AGG_MODE UsbRxAggMode;
++ u8 UsbRxAggBlockCount; // USB Block count. Block size is 512-byte in hight speed and 64-byte in full speed
++ u8 UsbRxAggBlockTimeout;
++ u8 UsbRxAggPageCount; // 8192C DMA page count
++ u8 UsbRxAggPageTimeout;
++#endif
++
++ // 2010/12/10 MH Add for USB aggreation mode dynamic shceme.
++ BOOLEAN UsbRxHighSpeedMode;
++
++ // 2010/11/22 MH Add for slim combo debug mode selective.
++ // This is used for fix the drawback of CU TSMC-A/UMC-A cut. HW auto suspend ability. Close BT clock.
++ BOOLEAN SlimComboDbg;
++
++ u16 EfuseUsedBytes;
++
++#ifdef CONFIG_P2P
++ struct P2P_PS_Offload_t p2p_ps_offload;
++#endif //CONFIG_P2P
++};
++
++typedef struct hal_data_8192cu HAL_DATA_TYPE, *PHAL_DATA_TYPE;
++#endif
++
++#define GET_HAL_DATA(__pAdapter) ((HAL_DATA_TYPE *)((__pAdapter)->HalData))
++#define GET_RF_TYPE(priv) (GET_HAL_DATA(priv)->rf_type)
++
++#define INCLUDE_MULTI_FUNC_BT(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT)
++#define INCLUDE_MULTI_FUNC_GPS(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)
++
++VOID rtl8192c_FirmwareSelfReset(IN PADAPTER Adapter);
++int FirmwareDownload92C(IN PADAPTER Adapter,IN BOOLEAN bUsedWoWLANFw);
++VOID InitializeFirmwareVars92C(PADAPTER Adapter);
++u8 GetEEPROMSize8192C(PADAPTER Adapter);
++void rtl8192c_EfuseParseChnlPlan(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
++VERSION_8192C rtl8192c_ReadChipVersion(IN PADAPTER Adapter);
++void rtl8192c_ReadBluetoothCoexistInfo(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
++//void rtl8192c_free_hal_data(_adapter * padapter);
++VOID rtl8192c_EfuseParseIDCode(PADAPTER pAdapter, u8 *hwinfo);
++void rtl8192c_set_hal_ops(struct hal_ops *pHalFunc);
++
++s32 c2h_id_filter_ccx_8192c(u8 id);
++#endif
++
++#ifdef CONFIG_MP_INCLUDED
++
++extern void Hal_SetAntenna(PADAPTER pAdapter);
++extern void Hal_SetBandwidth(PADAPTER pAdapter);
++
++extern void Hal_SetTxPower(PADAPTER pAdapter);
++extern void Hal_SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart);
++extern void Hal_SetSingleToneTx ( PADAPTER pAdapter , u8 bStart );
++extern void Hal_SetSingleCarrierTx (PADAPTER pAdapter, u8 bStart);
++extern void Hal_SetContinuousTx (PADAPTER pAdapter, u8 bStart);
++
++extern void Hal_SetDataRate(PADAPTER pAdapter);
++extern void Hal_SetChannel(PADAPTER pAdapter);
++extern void Hal_SetAntennaPathPower(PADAPTER pAdapter);
++extern s32 Hal_SetThermalMeter(PADAPTER pAdapter, u8 target_ther);
++extern s32 Hal_SetPowerTracking(PADAPTER padapter, u8 enable);
++extern void Hal_GetPowerTracking(PADAPTER padapter, u8 * enable);
++extern void Hal_GetThermalMeter(PADAPTER pAdapter, u8 *value);
++extern void Hal_mpt_SwitchRfSetting(PADAPTER pAdapter);
++extern void Hal_MPT_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14);
++extern void Hal_MPT_CCKTxPowerAdjustbyIndex(PADAPTER pAdapter, BOOLEAN beven);
++extern void Hal_SetCCKTxPower(PADAPTER pAdapter, u8 * TxPower);
++extern void Hal_SetOFDMTxPower(PADAPTER pAdapter, u8 * TxPower);
++extern void Hal_TriggerRFThermalMeter(PADAPTER pAdapter);
++extern u8 Hal_ReadRFThermalMeter(PADAPTER pAdapter);
++extern void Hal_SetCCKContinuousTx(PADAPTER pAdapter, u8 bStart);
++extern void Hal_SetOFDMContinuousTx(PADAPTER pAdapter, u8 bStart);
++
++#endif
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtl8192c_led.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtl8192c_led.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtl8192c_led.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtl8192c_led.h 2015-07-28 01:20:58.321597318 +0200
+@@ -0,0 +1,41 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef __RTL8192C_LED_H_
++#define __RTL8192C_LED_H_
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++
++
++//================================================================================
++// Interface to manipulate LED objects.
++//================================================================================
++#ifdef CONFIG_USB_HCI
++void rtl8192cu_InitSwLeds(_adapter *padapter);
++void rtl8192cu_DeInitSwLeds(_adapter *padapter);
++#endif
++#ifdef CONFIG_PCI_HCI
++void rtl8192ce_gen_RefreshLedState(PADAPTER Adapter);
++void rtl8192ce_InitSwLeds(_adapter *padapter);
++void rtl8192ce_DeInitSwLeds(_adapter *padapter);
++#endif
++
++#endif
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtl8192c_recv.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtl8192c_recv.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtl8192c_recv.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtl8192c_recv.h 2015-07-28 01:20:58.321597318 +0200
+@@ -0,0 +1,183 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef _RTL8192C_RECV_H_
++#define _RTL8192C_RECV_H_
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++
++
++#ifdef PLATFORM_OS_XP
++ #define NR_RECVBUFF (16)
++#elif defined(PLATFORM_OS_CE)
++ #define NR_RECVBUFF (4)
++#else
++#ifdef CONFIG_SINGLE_RECV_BUF
++ #define NR_RECVBUFF (1)
++#else
++ #define NR_RECVBUFF (4)
++#endif //CONFIG_SINGLE_RECV_BUF
++
++ #define NR_PREALLOC_RECV_SKB (8)
++#endif
++
++
++#define RECV_BLK_SZ 512
++#define RECV_BLK_CNT 16
++#define RECV_BLK_TH RECV_BLK_CNT
++
++#if defined(CONFIG_USB_HCI)
++
++#ifdef PLATFORM_OS_CE
++#define MAX_RECVBUF_SZ (8192+1024) // 8K+1k
++#else
++ #ifndef CONFIG_MINIMAL_MEMORY_USAGE
++ //#define MAX_RECVBUF_SZ (32768) // 32k
++ //#define MAX_RECVBUF_SZ (16384) //16K
++ //#define MAX_RECVBUF_SZ (10240) //10K
++ #ifdef CONFIG_PLATFORM_MSTAR
++ #define MAX_RECVBUF_SZ (8192) // 8K
++ #else
++ #define MAX_RECVBUF_SZ (15360) // 15k < 16k
++ #endif
++ //#define MAX_RECVBUF_SZ (8192+1024) // 8K+1k
++ #else
++ #define MAX_RECVBUF_SZ (4000) // about 4K
++ #endif
++#endif
++
++#elif defined(CONFIG_PCI_HCI)
++//#ifndef CONFIG_MINIMAL_MEMORY_USAGE
++// #define MAX_RECVBUF_SZ (9100)
++//#else
++ #define MAX_RECVBUF_SZ (4000) // about 4K
++//#endif
++
++#define RX_MPDU_QUEUE 0
++#define RX_CMD_QUEUE 1
++#define RX_MAX_QUEUE 2
++#endif
++
++
++#define RECV_BULK_IN_ADDR 0x80
++#define RECV_INT_IN_ADDR 0x81
++
++#define PHY_RSSI_SLID_WIN_MAX 100
++#define PHY_LINKQUALITY_SLID_WIN_MAX 20
++
++
++struct phy_stat
++{
++ unsigned int phydw0;
++
++ unsigned int phydw1;
++
++ unsigned int phydw2;
++
++ unsigned int phydw3;
++
++ unsigned int phydw4;
++
++ unsigned int phydw5;
++
++ unsigned int phydw6;
++
++ unsigned int phydw7;
++};
++
++typedef struct _Phy_OFDM_Rx_Status_Report_8192cd
++{
++ unsigned char trsw_gain_X[4];
++ unsigned char pwdb_all;
++ unsigned char cfosho_X[4];
++ unsigned char cfotail_X[4];
++ unsigned char rxevm_X[2];
++ unsigned char rxsnr_X[4];
++ unsigned char pdsnr_X[2];
++ unsigned char csi_current_X[2];
++ unsigned char csi_target_X[2];
++ unsigned char sigevm;
++ unsigned char max_ex_pwr;
++//#ifdef RTL8192SE
++#ifdef CONFIG_LITTLE_ENDIAN
++ unsigned char ex_intf_flg:1;
++ unsigned char sgi_en:1;
++ unsigned char rxsc:2;
++ //unsigned char rsvd:4;
++ unsigned char idle_long:1;
++ unsigned char r_ant_train_en:1;
++ unsigned char ANTSELB:1;
++ unsigned char ANTSEL:1;
++#else // _BIG_ENDIAN_
++ //unsigned char rsvd:4;
++ unsigned char ANTSEL:1;
++ unsigned char ANTSELB:1;
++ unsigned char r_ant_train_en:1;
++ unsigned char idle_long:1;
++ unsigned char rxsc:2;
++ unsigned char sgi_en:1;
++ unsigned char ex_intf_flg:1;
++#endif
++//#else // RTL8190, RTL8192E
++// unsigned char sgi_en;
++// unsigned char rxsc_sgien_exflg;
++//#endif
++} __attribute__ ((packed))PHY_STS_OFDM_8192CD_T,PHY_RX_DRIVER_INFO_8192CD;
++
++typedef struct _Phy_CCK_Rx_Status_Report_8192cd
++{
++ /* For CCK rate descriptor. This is a signed 8:1 variable. LSB bit presend
++ 0.5. And MSB 7 bts presend a signed value. Range from -64~+63.5. */
++ u8 adc_pwdb_X[4];
++ u8 SQ_rpt;
++ u8 cck_agc_rpt;
++} PHY_STS_CCK_8192CD_T;
++
++
++// Rx smooth factor
++#define Rx_Smooth_Factor (20)
++
++
++#ifdef CONFIG_USB_HCI
++typedef struct _INTERRUPT_MSG_FORMAT_EX{
++ unsigned int C2H_MSG0;
++ unsigned int C2H_MSG1;
++ unsigned int C2H_MSG2;
++ unsigned int C2H_MSG3;
++ unsigned int HISR; // from HISR Reg0x124, read to clear
++ unsigned int HISRE;// from HISRE Reg0x12c, read to clear
++ unsigned int MSG_EX;
++}INTERRUPT_MSG_FORMAT_EX,*PINTERRUPT_MSG_FORMAT_EX;
++
++void rtl8192cu_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf);
++int rtl8192cu_init_recv_priv(_adapter * padapter);
++void rtl8192cu_free_recv_priv(_adapter * padapter);
++#endif
++
++#ifdef CONFIG_PCI_HCI
++int rtl8192ce_init_recv_priv(_adapter * padapter);
++void rtl8192ce_free_recv_priv(_adapter * padapter);
++#endif
++
++void rtl8192c_translate_rx_signal_stuff(union recv_frame *precvframe, struct phy_stat *pphy_info);
++void rtl8192c_query_rx_desc_status(union recv_frame *precvframe, struct recv_stat *pdesc);
++
++#endif
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtl8192c_rf.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtl8192c_rf.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtl8192c_rf.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtl8192c_rf.h 2015-07-28 01:20:58.321597318 +0200
+@@ -0,0 +1,91 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++/******************************************************************************
++ *
++ *
++ * Module: rtl8192c_rf.h ( Header File)
++ *
++ * Note: Collect every HAL RF type exter API or constant.
++ *
++ * Function:
++ *
++ * Export:
++ *
++ * Abbrev:
++ *
++ * History:
++ * Data Who Remark
++ *
++ * 09/25/2008 MHC Create initial version.
++ *
++ *
++******************************************************************************/
++#ifndef _RTL8192C_RF_H_
++#define _RTL8192C_RF_H_
++/* Check to see if the file has been included already. */
++
++
++/*--------------------------Define Parameters-------------------------------*/
++
++//
++// For RF 6052 Series
++//
++#define RF6052_MAX_TX_PWR 0x3F
++#define RF6052_MAX_REG 0x3F
++#define RF6052_MAX_PATH 2
++/*--------------------------Define Parameters-------------------------------*/
++
++
++/*------------------------------Define structure----------------------------*/
++
++/*------------------------------Define structure----------------------------*/
++
++
++/*------------------------Export global variable----------------------------*/
++/*------------------------Export global variable----------------------------*/
++
++/*------------------------Export Marco Definition---------------------------*/
++
++/*------------------------Export Marco Definition---------------------------*/
++
++
++/*--------------------------Exported Function prototype---------------------*/
++
++//
++// RF RL6052 Series API
++//
++void rtl8192c_RF_ChangeTxPath( IN PADAPTER Adapter,
++ IN u16 DataRate);
++void rtl8192c_PHY_RF6052SetBandwidth(
++ IN PADAPTER Adapter,
++ IN HT_CHANNEL_WIDTH Bandwidth);
++VOID rtl8192c_PHY_RF6052SetCckTxPower(
++ IN PADAPTER Adapter,
++ IN u8* pPowerlevel);
++VOID rtl8192c_PHY_RF6052SetOFDMTxPower(
++ IN PADAPTER Adapter,
++ IN u8* pPowerLevel,
++ IN u8 Channel);
++int PHY_RF6052_Config8192C( IN PADAPTER Adapter );
++
++/*--------------------------Exported Function prototype---------------------*/
++
++
++#endif/* End of HalRf.h */
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtl8192c_spec.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtl8192c_spec.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtl8192c_spec.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtl8192c_spec.h 2015-07-28 01:20:58.321597318 +0200
+@@ -0,0 +1,1864 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef __RTL8192C_SPEC_H__
++#define __RTL8192C_SPEC_H__
++
++#include <drv_conf.h>
++
++#ifndef BIT
++#define BIT(x) (1 << (x))
++#endif
++
++#define BIT0 0x00000001
++#define BIT1 0x00000002
++#define BIT2 0x00000004
++#define BIT3 0x00000008
++#define BIT4 0x00000010
++#define BIT5 0x00000020
++#define BIT6 0x00000040
++#define BIT7 0x00000080
++#define BIT8 0x00000100
++#define BIT9 0x00000200
++#define BIT10 0x00000400
++#define BIT11 0x00000800
++#define BIT12 0x00001000
++#define BIT13 0x00002000
++#define BIT14 0x00004000
++#define BIT15 0x00008000
++#define BIT16 0x00010000
++#define BIT17 0x00020000
++#define BIT18 0x00040000
++#define BIT19 0x00080000
++#define BIT20 0x00100000
++#define BIT21 0x00200000
++#define BIT22 0x00400000
++#define BIT23 0x00800000
++#define BIT24 0x01000000
++#define BIT25 0x02000000
++#define BIT26 0x04000000
++#define BIT27 0x08000000
++#define BIT28 0x10000000
++#define BIT29 0x20000000
++#define BIT30 0x40000000
++#define BIT31 0x80000000
++
++
++//============================================================
++// 8192C Regsiter offset definition
++//============================================================
++
++
++//============================================================
++//
++//============================================================
++
++//-----------------------------------------------------
++//
++// 0x0000h ~ 0x00FFh System Configuration
++//
++//-----------------------------------------------------
++#define REG_SYS_ISO_CTRL 0x0000
++#define REG_SYS_FUNC_EN 0x0002
++#define REG_APS_FSMCO 0x0004
++#define REG_SYS_CLKR 0x0008
++#define REG_9346CR 0x000A
++#define REG_EE_VPD 0x000C
++#define REG_AFE_MISC 0x0010
++#define REG_SPS0_CTRL 0x0011
++#define REG_SPS_OCP_CFG 0x0018
++#define REG_RSV_CTRL 0x001C
++#define REG_RF_CTRL 0x001F
++#define REG_LDOA15_CTRL 0x0020
++#define REG_LDOV12D_CTRL 0x0021
++#define REG_LDOHCI12_CTRL 0x0022
++#define REG_LPLDO_CTRL 0x0023
++#define REG_AFE_XTAL_CTRL 0x0024
++#define REG_AFE_PLL_CTRL 0x0028
++#define REG_EFUSE_CTRL 0x0030
++#define REG_EFUSE_TEST 0x0034
++#define REG_PWR_DATA 0x0038
++#define REG_CAL_TIMER 0x003C
++#define REG_ACLK_MON 0x003E
++#define REG_GPIO_MUXCFG 0x0040
++#define REG_GPIO_IO_SEL 0x0042
++#define REG_MAC_PINMUX_CFG 0x0043
++#define REG_GPIO_PIN_CTRL 0x0044
++#define REG_GPIO_INTM 0x0048
++#define REG_LEDCFG0 0x004C
++#define REG_LEDCFG1 0x004D
++#define REG_LEDCFG2 0x004E
++#define REG_LEDCFG3 0x004F
++#define REG_LEDCFG REG_LEDCFG2
++#define REG_FSIMR 0x0050
++#define REG_FSISR 0x0054
++#define REG_HSIMR 0x0058
++#define REG_HSISR 0x005c
++#define REG_GPIO_PIN_CTRL_2 0x0060 // RTL8723 WIFI/BT/GPS Multi-Function GPIO Pin Control.
++#define REG_GPIO_IO_SEL_2 0x0062 // RTL8723 WIFI/BT/GPS Multi-Function GPIO Select.
++#define REG_MULTI_FUNC_CTRL 0x0068 // RTL8723 WIFI/BT/GPS Multi-Function control source.
++#define REG_MCUFWDL 0x0080
++#ifdef CONFIG_WOWLAN
++#define REG_WOWLAN_REASON 0x0081
++#endif //CONFIG_WOWLAN
++#define REG_HMEBOX_EXT_0 0x0088
++#define REG_HMEBOX_EXT_1 0x008A
++#define REG_HMEBOX_EXT_2 0x008C
++#define REG_HMEBOX_EXT_3 0x008E
++#define REG_HOST_SUSP_CNT 0x00BC // Host suspend counter on FPGA platform
++#define REG_EFUSE_ACCESS 0x00CF // Efuse access protection for RTL8723
++#define REG_BIST_SCAN 0x00D0
++#define REG_BIST_RPT 0x00D4
++#define REG_BIST_ROM_RPT 0x00D8
++#define REG_USB_SIE_INTF 0x00E0
++#define REG_PCIE_MIO_INTF 0x00E4
++#define REG_PCIE_MIO_INTD 0x00E8
++#define REG_HPON_FSM 0x00EC
++#define REG_SYS_CFG 0x00F0
++#define REG_GPIO_OUTSTS 0x00F4 // For RTL8723 only.
++
++//-----------------------------------------------------
++//
++// 0x0100h ~ 0x01FFh MACTOP General Configuration
++//
++//-----------------------------------------------------
++#define REG_CR 0x0100
++#define REG_PBP 0x0104
++#define REG_TRXDMA_CTRL 0x010C
++#define REG_TRXFF_BNDY 0x0114
++#define REG_TRXFF_STATUS 0x0118
++#define REG_RXFF_PTR 0x011C
++#define REG_HIMR 0x0120
++#define REG_HISR 0x0124
++#define REG_HIMRE 0x0128
++#define REG_HISRE 0x012C
++#define REG_CPWM 0x012F
++#define REG_FWIMR 0x0130
++#define REG_FWISR 0x0134
++#define REG_PKTBUF_DBG_CTRL 0x0140
++#define REG_PKTBUF_DBG_DATA_L 0x0144
++#define REG_PKTBUF_DBG_DATA_H 0x0148
++
++#define REG_TC0_CTRL 0x0150
++#define REG_TC1_CTRL 0x0154
++#define REG_TC2_CTRL 0x0158
++#define REG_TC3_CTRL 0x015C
++#define REG_TC4_CTRL 0x0160
++#define REG_TCUNIT_BASE 0x0164
++#define REG_MBIST_START 0x0174
++#define REG_MBIST_DONE 0x0178
++#define REG_MBIST_FAIL 0x017C
++#define REG_C2HEVT_MSG_NORMAL 0x01A0
++#define REG_C2HEVT_CLEAR 0x01AF
++#define REG_C2HEVT_MSG_TEST 0x01B8
++#define REG_MCUTST_1 0x01c0
++#define REG_FMETHR 0x01C8
++#define REG_HMETFR 0x01CC
++#define REG_HMEBOX_0 0x01D0
++#define REG_HMEBOX_1 0x01D4
++#define REG_HMEBOX_2 0x01D8
++#define REG_HMEBOX_3 0x01DC
++
++#define REG_LLT_INIT 0x01E0
++#define REG_BB_ACCEESS_CTRL 0x01E8
++#define REG_BB_ACCESS_DATA 0x01EC
++
++
++//-----------------------------------------------------
++//
++// 0x0200h ~ 0x027Fh TXDMA Configuration
++//
++//-----------------------------------------------------
++#define REG_RQPN 0x0200
++#define REG_FIFOPAGE 0x0204
++#define REG_TDECTRL 0x0208
++#define REG_TXDMA_OFFSET_CHK 0x020C
++#define REG_TXDMA_STATUS 0x0210
++#define REG_RQPN_NPQ 0x0214
++
++//-----------------------------------------------------
++//
++// 0x0280h ~ 0x02FFh RXDMA Configuration
++//
++//-----------------------------------------------------
++#define REG_RXDMA_AGG_PG_TH 0x0280
++#define REG_RXPKT_NUM 0x0284
++#define REG_RXDMA_STATUS 0x0288
++
++
++//-----------------------------------------------------
++//
++// 0x0300h ~ 0x03FFh PCIe
++//
++//-----------------------------------------------------
++#define REG_PCIE_CTRL_REG 0x0300
++#define REG_INT_MIG 0x0304 // Interrupt Migration
++#define REG_BCNQ_DESA 0x0308 // TX Beacon Descriptor Address
++#define REG_HQ_DESA 0x0310 // TX High Queue Descriptor Address
++#define REG_MGQ_DESA 0x0318 // TX Manage Queue Descriptor Address
++#define REG_VOQ_DESA 0x0320 // TX VO Queue Descriptor Address
++#define REG_VIQ_DESA 0x0328 // TX VI Queue Descriptor Address
++#define REG_BEQ_DESA 0x0330 // TX BE Queue Descriptor Address
++#define REG_BKQ_DESA 0x0338 // TX BK Queue Descriptor Address
++#define REG_RX_DESA 0x0340 // RX Queue Descriptor Address
++#define REG_DBI 0x0348 // Backdoor REG for Access Configuration
++#define REG_MDIO 0x0354 // MDIO for Access PCIE PHY
++#define REG_DBG_SEL 0x0360 // Debug Selection Register
++#define REG_PCIE_HRPWM 0x0361 //PCIe RPWM
++#define REG_PCIE_HCPWM 0x0363 //PCIe CPWM
++#define REG_UART_CTRL 0x0364 // UART Control
++#define REG_UART_TX_DESA 0x0370 // UART TX Descriptor Address
++#define REG_UART_RX_DESA 0x0378 // UART Rx Descriptor Address
++
++
++// spec version 11
++//-----------------------------------------------------
++//
++// 0x0400h ~ 0x047Fh Protocol Configuration
++//
++//-----------------------------------------------------
++#define REG_VOQ_INFORMATION 0x0400
++#define REG_VIQ_INFORMATION 0x0404
++#define REG_BEQ_INFORMATION 0x0408
++#define REG_BKQ_INFORMATION 0x040C
++#define REG_MGQ_INFORMATION 0x0410
++#define REG_HGQ_INFORMATION 0x0414
++#define REG_BCNQ_INFORMATION 0x0418
++
++
++#define REG_CPU_MGQ_INFORMATION 0x041C
++#define REG_FWHW_TXQ_CTRL 0x0420
++#define REG_HWSEQ_CTRL 0x0423
++#define REG_TXPKTBUF_BCNQ_BDNY 0x0424
++#define REG_TXPKTBUF_MGQ_BDNY 0x0425
++#define REG_LIFETIME_EN 0x0426
++#define REG_MULTI_BCNQ_OFFSET 0x0427
++#define REG_SPEC_SIFS 0x0428
++#define REG_RL 0x042A
++#define REG_DARFRC 0x0430
++#define REG_RARFRC 0x0438
++#define REG_RRSR 0x0440
++#define REG_ARFR0 0x0444
++#define REG_ARFR1 0x0448
++#define REG_ARFR2 0x044C
++#define REG_ARFR3 0x0450
++#define REG_AGGLEN_LMT 0x0458
++#define REG_AMPDU_MIN_SPACE 0x045C
++#define REG_TXPKTBUF_WMAC_LBK_BF_HD 0x045D
++#define REG_FAST_EDCA_CTRL 0x0460
++#define REG_RD_RESP_PKT_TH 0x0463
++#define REG_INIRTS_RATE_SEL 0x0480
++#define REG_INIDATA_RATE_SEL 0x0484
++
++//#define REG_FW_TSF_SYNC_CNT 0x04A0
++#define REG_FW_RESET_TSF_CNT_1 0x05FC
++#define REG_FW_RESET_TSF_CNT_0 0x05FD
++#define REG_FW_BCN_DIS_CNT 0x05FE
++
++#define REG_POWER_STATUS 0x04A4
++#define REG_POWER_STAGE1 0x04B4
++#define REG_POWER_STAGE2 0x04B8
++#define REG_PKT_VO_VI_LIFE_TIME 0x04C0
++#define REG_PKT_BE_BK_LIFE_TIME 0x04C2
++#define REG_STBC_SETTING 0x04C4
++#define REG_PROT_MODE_CTRL 0x04C8
++#define REG_MAX_AGGR_NUM 0x04CA
++#define REG_RTS_MAX_AGGR_NUM 0x04CB
++#define REG_BAR_MODE_CTRL 0x04CC
++#define REG_RA_TRY_RATE_AGG_LMT 0x04CF
++#define REG_NQOS_SEQ 0x04DC
++#define REG_QOS_SEQ 0x04DE
++#define REG_NEED_CPU_HANDLE 0x04E0
++#define REG_PKT_LOSE_RPT 0x04E1
++#define REG_PTCL_ERR_STATUS 0x04E2
++#define REG_DUMMY 0x04FC
++
++
++
++//-----------------------------------------------------
++//
++// 0x0500h ~ 0x05FFh EDCA Configuration
++//
++//-----------------------------------------------------
++#define REG_EDCA_VO_PARAM 0x0500
++#define REG_EDCA_VI_PARAM 0x0504
++#define REG_EDCA_BE_PARAM 0x0508
++#define REG_EDCA_BK_PARAM 0x050C
++#define REG_BCNTCFG 0x0510
++#define REG_PIFS 0x0512
++#define REG_RDG_PIFS 0x0513
++#define REG_SIFS_CCK 0x0514
++#define REG_SIFS_OFDM 0x0516
++#define REG_SIFS_CTX 0x0514
++#define REG_SIFS_TRX 0x0516
++#define REG_TSFTR_SYN_OFFSET 0x0518
++#define REG_AGGR_BREAK_TIME 0x051A
++#define REG_SLOT 0x051B
++#define REG_TX_PTCL_CTRL 0x0520
++#define REG_TXPAUSE 0x0522
++#define REG_DIS_TXREQ_CLR 0x0523
++#define REG_RD_CTRL 0x0524
++#define REG_TBTT_PROHIBIT 0x0540
++#define REG_RD_NAV_NXT 0x0544
++#define REG_NAV_PROT_LEN 0x0546
++#define REG_BCN_CTRL 0x0550
++#define REG_BCN_CTRL_1 0x0551
++#define REG_MBID_NUM 0x0552
++#define REG_DUAL_TSF_RST 0x0553
++#define REG_BCN_INTERVAL 0x0554 // The same as REG_MBSSID_BCN_SPACE
++#define REG_MBSSID_BCN_SPACE 0x0554
++#define REG_DRVERLYINT 0x0558
++#define REG_BCNDMATIM 0x0559
++#define REG_ATIMWND 0x055A
++#define REG_BCN_MAX_ERR 0x055D
++#define REG_RXTSF_OFFSET_CCK 0x055E
++#define REG_RXTSF_OFFSET_OFDM 0x055F
++#define REG_TSFTR 0x0560
++#define REG_TSFTR1 0x0568
++#define REG_INIT_TSFTR 0x0564
++#define REG_ATIMWND_1 0x0570
++#define REG_PSTIMER 0x0580
++#define REG_TIMER0 0x0584
++#define REG_TIMER1 0x0588
++#define REG_ACMHWCTRL 0x05C0
++#define REG_ACMRSTCTRL 0x05C1
++#define REG_ACMAVG 0x05C2
++#define REG_VO_ADMTIME 0x05C4
++#define REG_VI_ADMTIME 0x05C6
++#define REG_BE_ADMTIME 0x05C8
++#define REG_EDCA_RANDOM_GEN 0x05CC
++#define REG_SCH_TXCMD 0x05D0
++
++
++//-----------------------------------------------------
++//
++// 0x0600h ~ 0x07FFh WMAC Configuration
++//
++//-----------------------------------------------------
++#define REG_APSD_CTRL 0x0600
++#define REG_BWOPMODE 0x0603
++#define REG_TCR 0x0604
++#define REG_RCR 0x0608
++#define REG_RX_PKT_LIMIT 0x060C
++#define REG_RX_DLK_TIME 0x060D
++#define REG_RX_DRVINFO_SZ 0x060F
++
++#define REG_MACID 0x0610
++#define REG_BSSID 0x0618
++#define REG_MAR 0x0620
++#define REG_MBIDCAMCFG 0x0628
++
++#define REG_USTIME_EDCA 0x0638
++#define REG_MAC_SPEC_SIFS 0x063A
++
++// 20100719 Joseph: Hardware register definition change. (HW datasheet v54)
++#define REG_R2T_SIFS 0x063C // [15:8]SIFS_R2T_OFDM, [7:0]SIFS_R2T_CCK
++#define REG_T2T_SIFS 0x063E // [15:8]SIFS_T2T_OFDM, [7:0]SIFS_T2T_CCK
++#define REG_ACKTO 0x0640
++#define REG_CTS2TO 0x0641
++#define REG_EIFS 0x0642
++
++//WMA, BA, CCX
++#define REG_NAV_CTRL 0x0650
++#define REG_BACAMCMD 0x0654
++#define REG_BACAMCONTENT 0x0658
++#define REG_LBDLY 0x0660
++#define REG_FWDLY 0x0661
++#define REG_RXERR_RPT 0x0664
++#define REG_WMAC_TRXPTCL_CTL 0x0668
++
++
++// Security
++#define REG_CAMCMD 0x0670
++#define REG_CAMWRITE 0x0674
++#define REG_CAMREAD 0x0678
++#define REG_CAMDBG 0x067C
++#define REG_SECCFG 0x0680
++
++// Power
++#define REG_WOW_CTRL 0x0690
++#define REG_PSSTATUS 0x0691
++#define REG_PS_RX_INFO 0x0692
++#define REG_LPNAV_CTRL 0x0694
++#define REG_WKFMCAM_CMD 0x0698
++#define REG_WKFMCAM_RWD 0x069C
++#define REG_RXFLTMAP0 0x06A0
++#define REG_RXFLTMAP1 0x06A2
++#define REG_RXFLTMAP2 0x06A4
++#define REG_BCN_PSR_RPT 0x06A8
++#define REG_CALB32K_CTRL 0x06AC
++#define REG_PKT_MON_CTRL 0x06B4
++#define REG_BT_COEX_TABLE 0x06C0
++#define REG_WMAC_RESP_TXINFO 0x06D8
++
++#define REG_MACID1 0x0700
++#define REG_BSSID1 0x0708
++
++
++//-----------------------------------------------------
++//
++// 0xFE00h ~ 0xFE55h USB Configuration
++//
++//-----------------------------------------------------
++#define REG_USB_INFO 0xFE17
++#define REG_USB_SPECIAL_OPTION 0xFE55
++#define REG_USB_DMA_AGG_TO 0xFE5B
++#define REG_USB_AGG_TO 0xFE5C
++#define REG_USB_AGG_TH 0xFE5D
++
++// For test chip
++#define REG_TEST_USB_TXQS 0xFE48
++#define REG_TEST_SIE_VID 0xFE60 // 0xFE60~0xFE61
++#define REG_TEST_SIE_PID 0xFE62 // 0xFE62~0xFE63
++#define REG_TEST_SIE_OPTIONAL 0xFE64
++#define REG_TEST_SIE_CHIRP_K 0xFE65
++#define REG_TEST_SIE_PHY 0xFE66 // 0xFE66~0xFE6B
++#define REG_TEST_SIE_MAC_ADDR 0xFE70 // 0xFE70~0xFE75
++#define REG_TEST_SIE_STRING 0xFE80 // 0xFE80~0xFEB9
++
++
++// For normal chip
++#define REG_NORMAL_SIE_VID 0xFE60 // 0xFE60~0xFE61
++#define REG_NORMAL_SIE_PID 0xFE62 // 0xFE62~0xFE63
++#define REG_NORMAL_SIE_OPTIONAL 0xFE64
++#define REG_NORMAL_SIE_EP 0xFE65 // 0xFE65~0xFE67
++#define REG_NORMAL_SIE_PHY 0xFE68 // 0xFE68~0xFE6B
++#define REG_NORMAL_SIE_OPTIONAL2 0xFE6C
++#define REG_NORMAL_SIE_GPS_EP 0xFE6D // 0xFE6D, for RTL8723 only.
++#define REG_NORMAL_SIE_MAC_ADDR 0xFE70 // 0xFE70~0xFE75
++#define REG_NORMAL_SIE_STRING 0xFE80 // 0xFE80~0xFEDF
++
++
++//-----------------------------------------------------
++//
++// Redifine 8192C register definition for compatibility
++//
++//-----------------------------------------------------
++
++// TODO: use these definition when using REG_xxx naming rule.
++// NOTE: DO NOT Remove these definition. Use later.
++
++#define SYS_ISO_CTRL REG_SYS_ISO_CTRL // System Isolation Interface Control.
++#define SYS_FUNC_EN REG_SYS_FUNC_EN // System Function Enable.
++#define SYS_CLK REG_SYS_CLKR
++#define CR9346 REG_9346CR // 93C46/93C56 Command Register.
++#define EFUSE_CTRL REG_EFUSE_CTRL // E-Fuse Control.
++#define EFUSE_TEST REG_EFUSE_TEST // E-Fuse Test.
++#define MSR (REG_CR + 2) // Media Status register
++#define ISR REG_HISR
++#define TSFR REG_TSFTR // Timing Sync Function Timer Register.
++
++#define MACIDR0 REG_MACID // MAC ID Register, Offset 0x0050-0x0053
++#define MACIDR4 (REG_MACID + 4) // MAC ID Register, Offset 0x0054-0x0055
++
++#define PBP REG_PBP
++
++// Redifine MACID register, to compatible prior ICs.
++#define IDR0 MACIDR0
++#define IDR4 MACIDR4
++
++
++//
++// 9. Security Control Registers (Offset: )
++//
++#define RWCAM REG_CAMCMD //IN 8190 Data Sheet is called CAMcmd
++#define WCAMI REG_CAMWRITE // Software write CAM input content
++#define RCAMO REG_CAMREAD // Software read/write CAM config
++#define CAMDBG REG_CAMDBG
++#define SECR REG_SECCFG //Security Configuration Register
++
++// Unused register
++#define UnusedRegister 0x1BF
++#define DCAM UnusedRegister
++#define PSR UnusedRegister
++#define BBAddr UnusedRegister
++#define PhyDataR UnusedRegister
++
++#define InvalidBBRFValue 0x12345678
++
++// Min Spacing related settings.
++#define MAX_MSS_DENSITY_2T 0x13
++#define MAX_MSS_DENSITY_1T 0x0A
++
++//----------------------------------------------------------------------------
++// 8192C Cmd9346CR bits (Offset 0xA, 16bit)
++//----------------------------------------------------------------------------
++#define CmdEEPROM_En BIT5 // EEPROM enable when set 1
++#define CmdEERPOMSEL BIT4 // System EEPROM select, 0: boot from E-FUSE, 1: The EEPROM used is 9346
++#define Cmd9346CR_9356SEL BIT4
++#define AutoLoadEEPROM (CmdEEPROM_En|CmdEERPOMSEL)
++#define AutoLoadEFUSE CmdEEPROM_En
++
++//----------------------------------------------------------------------------
++// 8192C GPIO MUX Configuration Register (offset 0x40, 4 byte)
++//----------------------------------------------------------------------------
++#define GPIOSEL_GPIO 0
++#define GPIOSEL_ENBT BIT5
++
++//----------------------------------------------------------------------------
++// 8192C GPIO PIN Control Register (offset 0x44, 4 byte)
++//----------------------------------------------------------------------------
++#define GPIO_IN REG_GPIO_PIN_CTRL // GPIO pins input value
++#define GPIO_OUT (REG_GPIO_PIN_CTRL+1) // GPIO pins output value
++#define GPIO_IO_SEL (REG_GPIO_PIN_CTRL+2) // GPIO pins output enable when a bit is set to "1"; otherwise, input is configured.
++#define GPIO_MOD (REG_GPIO_PIN_CTRL+3)
++
++//----------------------------------------------------------------------------
++// 8192C (MSR) Media Status Register (Offset 0x4C, 8 bits)
++//----------------------------------------------------------------------------
++/*
++Network Type
++00: No link
++01: Link in ad hoc network
++10: Link in infrastructure network
++11: AP mode
++Default: 00b.
++*/
++#define MSR_NOLINK 0x00
++#define MSR_ADHOC 0x01
++#define MSR_INFRA 0x02
++#define MSR_AP 0x03
++
++//
++// 6. Adaptive Control Registers (Offset: 0x0160 - 0x01CF)
++//
++//----------------------------------------------------------------------------
++// 8192C Response Rate Set Register (offset 0x181, 24bits)
++//----------------------------------------------------------------------------
++#define RRSR_RSC_OFFSET 21
++#define RRSR_SHORT_OFFSET 23
++#define RRSR_RSC_BW_40M 0x600000
++#define RRSR_RSC_UPSUBCHNL 0x400000
++#define RRSR_RSC_LOWSUBCHNL 0x200000
++#define RRSR_SHORT 0x800000
++#define RRSR_1M BIT0
++#define RRSR_2M BIT1
++#define RRSR_5_5M BIT2
++#define RRSR_11M BIT3
++#define RRSR_6M BIT4
++#define RRSR_9M BIT5
++#define RRSR_12M BIT6
++#define RRSR_18M BIT7
++#define RRSR_24M BIT8
++#define RRSR_36M BIT9
++#define RRSR_48M BIT10
++#define RRSR_54M BIT11
++#define RRSR_MCS0 BIT12
++#define RRSR_MCS1 BIT13
++#define RRSR_MCS2 BIT14
++#define RRSR_MCS3 BIT15
++#define RRSR_MCS4 BIT16
++#define RRSR_MCS5 BIT17
++#define RRSR_MCS6 BIT18
++#define RRSR_MCS7 BIT19
++#define BRSR_AckShortPmb BIT23
++// CCK ACK: use Short Preamble or not
++
++
++//----------------------------------------------------------------------------
++// 8192C Rate Definition
++//----------------------------------------------------------------------------
++//CCK
++#define RATR_1M 0x00000001
++#define RATR_2M 0x00000002
++#define RATR_55M 0x00000004
++#define RATR_11M 0x00000008
++//OFDM
++#define RATR_6M 0x00000010
++#define RATR_9M 0x00000020
++#define RATR_12M 0x00000040
++#define RATR_18M 0x00000080
++#define RATR_24M 0x00000100
++#define RATR_36M 0x00000200
++#define RATR_48M 0x00000400
++#define RATR_54M 0x00000800
++//MCS 1 Spatial Stream
++#define RATR_MCS0 0x00001000
++#define RATR_MCS1 0x00002000
++#define RATR_MCS2 0x00004000
++#define RATR_MCS3 0x00008000
++#define RATR_MCS4 0x00010000
++#define RATR_MCS5 0x00020000
++#define RATR_MCS6 0x00040000
++#define RATR_MCS7 0x00080000
++//MCS 2 Spatial Stream
++#define RATR_MCS8 0x00100000
++#define RATR_MCS9 0x00200000
++#define RATR_MCS10 0x00400000
++#define RATR_MCS11 0x00800000
++#define RATR_MCS12 0x01000000
++#define RATR_MCS13 0x02000000
++#define RATR_MCS14 0x04000000
++#define RATR_MCS15 0x08000000
++
++//----------------------------------------------------------------------------
++// 8192C BW_OPMODE bits (Offset 0x203, 8bit)
++//----------------------------------------------------------------------------
++#define BW_OPMODE_20MHZ BIT2
++#define BW_OPMODE_5G BIT1
++#define BW_OPMODE_11J BIT0
++
++
++//----------------------------------------------------------------------------
++// 8192C CAM Config Setting (offset 0x250, 1 byte)
++//----------------------------------------------------------------------------
++#define CAM_VALID BIT15
++#define CAM_NOTVALID 0x0000
++#define CAM_USEDK BIT5
++
++#define CAM_CONTENT_COUNT 8
++
++#define CAM_NONE 0x0
++#define CAM_WEP40 0x01
++#define CAM_TKIP 0x02
++#define CAM_AES 0x04
++#define CAM_WEP104 0x05
++
++#define TOTAL_CAM_ENTRY 32
++#define HALF_CAM_ENTRY 16
++
++#define CAM_CONFIG_USEDK _TRUE
++#define CAM_CONFIG_NO_USEDK _FALSE
++
++#define CAM_WRITE BIT16
++#define CAM_READ 0x00000000
++#define CAM_POLLINIG BIT31
++
++#define SCR_UseDK 0x01
++#define SCR_TxSecEnable 0x02
++#define SCR_RxSecEnable 0x04
++
++
++//
++// 12. Host Interrupt Status Registers (Offset: 0x0300 - 0x030F)
++//
++//----------------------------------------------------------------------------
++// 8190 IMR/ISR bits (offset 0xfd, 8bits)
++//----------------------------------------------------------------------------
++#define IMR8190_DISABLED 0x0
++// IMR DW0 Bit 0-31
++#define IMR_BCNDMAINT6 BIT31 // Beacon DMA Interrupt 6
++#define IMR_BCNDMAINT5 BIT30 // Beacon DMA Interrupt 5
++#define IMR_BCNDMAINT4 BIT29 // Beacon DMA Interrupt 4
++#define IMR_BCNDMAINT3 BIT28 // Beacon DMA Interrupt 3
++#define IMR_BCNDMAINT2 BIT27 // Beacon DMA Interrupt 2
++#define IMR_BCNDMAINT1 BIT26 // Beacon DMA Interrupt 1
++#define IMR_BCNDOK8 BIT25 // Beacon Queue DMA OK Interrup 8
++#define IMR_BCNDOK7 BIT24 // Beacon Queue DMA OK Interrup 7
++#define IMR_BCNDOK6 BIT23 // Beacon Queue DMA OK Interrup 6
++#define IMR_BCNDOK5 BIT22 // Beacon Queue DMA OK Interrup 5
++#define IMR_BCNDOK4 BIT21 // Beacon Queue DMA OK Interrup 4
++#define IMR_BCNDOK3 BIT20 // Beacon Queue DMA OK Interrup 3
++#define IMR_BCNDOK2 BIT19 // Beacon Queue DMA OK Interrup 2
++#define IMR_BCNDOK1 BIT18 // Beacon Queue DMA OK Interrup 1
++#define IMR_TIMEOUT2 BIT17 // Timeout interrupt 2
++#define IMR_TIMEOUT1 BIT16 // Timeout interrupt 1
++#define IMR_TXFOVW BIT15 // Transmit FIFO Overflow
++#define IMR_PSTIMEOUT BIT14 // Power save time out interrupt
++#define IMR_BcnInt BIT13 // Beacon DMA Interrupt 0
++#define IMR_RXFOVW BIT12 // Receive FIFO Overflow
++#define IMR_RDU BIT11 // Receive Descriptor Unavailable
++#define IMR_ATIMEND BIT10 // For 92C,ATIM Window End Interrupt
++#define IMR_BDOK BIT9 // Beacon Queue DMA OK Interrup
++#define IMR_HIGHDOK BIT8 // High Queue DMA OK Interrupt
++#define IMR_TBDOK BIT7 // Transmit Beacon OK interrup
++#define IMR_MGNTDOK BIT6 // Management Queue DMA OK Interrupt
++#define IMR_TBDER BIT5 // For 92C,Transmit Beacon Error Interrupt
++#define IMR_BKDOK BIT4 // AC_BK DMA OK Interrupt
++#define IMR_BEDOK BIT3 // AC_BE DMA OK Interrupt
++#define IMR_VIDOK BIT2 // AC_VI DMA OK Interrupt
++#define IMR_VODOK BIT1 // AC_VO DMA Interrupt
++#define IMR_ROK BIT0 // Receive DMA OK Interrupt
++
++#define IMR_RX_MASK (IMR_ROK|IMR_RDU|IMR_RXFOVW)
++#define IMR_TX_MASK (IMR_VODOK|IMR_VIDOK|IMR_BEDOK|IMR_BKDOK|IMR_MGNTDOK|IMR_HIGHDOK|IMR_BDOK)
++
++// 13. Host Interrupt Status Extension Register (Offset: 0x012C-012Eh)
++#define IMR_BcnInt_E BIT12
++#define IMR_TXERR BIT11
++#define IMR_RXERR BIT10
++#define IMR_C2HCMD BIT9
++#define IMR_CPWM BIT8
++//RSVD [2-7]
++#define IMR_OCPINT BIT1
++#define IMR_WLANOFF BIT0
++
++
++
++//----------------------------------------------------------------------------
++// 8192C EFUSE
++//----------------------------------------------------------------------------
++#define HWSET_MAX_SIZE 128
++
++
++//----------------------------------------------------------------------------
++// 8192C EEPROM/EFUSE share register definition.
++//----------------------------------------------------------------------------
++
++//
++// Default Value for EEPROM or EFUSE!!!
++//
++#define EEPROM_Default_TSSI 0x0
++#define EEPROM_Default_TxPowerDiff 0x0
++#define EEPROM_Default_CrystalCap 0x5
++#define EEPROM_Default_BoardType 0x02 // Default: 2X2, RTL8192CE(QFPN68)
++#define EEPROM_Default_TxPower 0x1010
++#define EEPROM_Default_HT2T_TxPwr 0x10
++
++#define EEPROM_Default_LegacyHTTxPowerDiff 0x3
++#define EEPROM_Default_ThermalMeter 0x12
++
++#define EEPROM_Default_AntTxPowerDiff 0x0
++#define EEPROM_Default_TxPwDiff_CrystalCap 0x5
++#define EEPROM_Default_TxPowerLevel 0x22
++#define EEPROM_Default_HT40_2SDiff 0x0
++#define EEPROM_Default_HT20_Diff 2 // HT20<->40 default Tx Power Index Difference
++#define EEPROM_Default_LegacyHTTxPowerDiff 0x3
++#define EEPROM_Default_HT40_PwrMaxOffset 0
++#define EEPROM_Default_HT20_PwrMaxOffset 0
++
++// For debug
++#define EEPROM_Default_PID 0x1234
++#define EEPROM_Default_VID 0x5678
++#define EEPROM_Default_CustomerID 0xAB
++#define EEPROM_Default_SubCustomerID 0xCD
++#define EEPROM_Default_Version 0
++
++#define EEPROM_CHANNEL_PLAN_FCC 0x0
++#define EEPROM_CHANNEL_PLAN_IC 0x1
++#define EEPROM_CHANNEL_PLAN_ETSI 0x2
++#define EEPROM_CHANNEL_PLAN_SPAIN 0x3
++#define EEPROM_CHANNEL_PLAN_FRANCE 0x4
++#define EEPROM_CHANNEL_PLAN_MKK 0x5
++#define EEPROM_CHANNEL_PLAN_MKK1 0x6
++#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7
++#define EEPROM_CHANNEL_PLAN_TELEC 0x8
++#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9
++#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA
++#define EEPROM_CHANNEL_PLAN_NCC 0xB
++#define EEPROM_USB_OPTIONAL1 0xE
++#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80
++
++
++#define EEPROM_CID_DEFAULT 0x0
++#define EEPROM_CID_TOSHIBA 0x4
++#define EEPROM_CID_CCX 0x10 // CCX test. By Bruce, 2009-02-25.
++#define EEPROM_CID_QMI 0x0D
++#define EEPROM_CID_WHQL 0xFE // added by chiyoko for dtm, 20090108
++
++
++#define RTL_EEPROM_ID 0x8129
++
++
++#ifdef CONFIG_PCI_HCI
++#define RT_IBSS_INT_MASKS (IMR_BcnInt | IMR_TBDOK | IMR_TBDER)
++#define RT_AC_INT_MASKS (IMR_VIDOK | IMR_VODOK | IMR_BEDOK|IMR_BKDOK)
++#define RT_BSS_INT_MASKS (RT_IBSS_INT_MASKS)
++
++//
++// Interface type.
++//
++typedef enum _INTERFACE_SELECT_8192CPCIe{
++ INTF_SEL0_SOLO_MINICARD = 0, // WiFi solo-mCard
++ INTF_SEL1_BT_COMBO_MINICARD = 1, // WiFi+BT combo-mCard
++ INTF_SEL2_PCIe = 2, // PCIe Card
++} INTERFACE_SELECT_8192CPCIe, *PINTERFACE_SELECT_8192CPCIe;
++
++#define RTL8190_EEPROM_ID 0x8129 // 0-1
++#define EEPROM_HPON 0x02 // LDO settings.2-5
++#define EEPROM_CLK 0x06 // Clock settings.6-7
++#define EEPROM_TESTR 0x08 // SE Test mode.8
++
++#define EEPROM_VID 0x0A // SE Vendor ID.A-B
++#define EEPROM_DID 0x0C // SE Device ID. C-D
++#define EEPROM_SVID 0x0E // SE Vendor ID.E-F
++#define EEPROM_SMID 0x10 // SE PCI Subsystem ID. 10-11
++
++#define EEPROM_MAC_ADDR 0x16 // SEMAC Address. 12-17
++
++//----------------------------------------------------------------
++// Ziv - Let PCIe and USB use the same define. Modify address mapping later.
++#define EEPROM_CCK_TX_PWR_INX 0x5A
++#define EEPROM_HT40_1S_TX_PWR_INX 0x60
++#define EEPROM_HT40_2S_TX_PWR_INX_DIFF 0x66
++#define EEPROM_HT20_TX_PWR_INX_DIFF 0x69
++#define EEPROM_OFDM_TX_PWR_INX_DIFF 0x6C
++#define EEPROM_HT40_MAX_PWR_OFFSET 0x6F
++#define EEPROM_HT20_MAX_PWR_OFFSET 0x72
++
++#define EEPROM_CHANNEL_PLAN 0x75
++#define EEPROM_TSSI_A 0x76
++#define EEPROM_TSSI_B 0x77
++#define EEPROM_THERMAL_METER 0x78
++#define EEPROM_RF_OPT1 0x79
++#define EEPROM_RF_OPT2 0x7A
++#define EEPROM_RF_OPT3 0x7B
++#define EEPROM_RF_OPT4 0x7C
++#define EEPROM_VERSION 0x7E
++#define EEPROM_CUSTOMER_ID 0x7F
++
++#define EEPROM_NORMAL_BoardType EEPROM_RF_OPT1 //[7:5]
++
++#endif
++
++#ifdef CONFIG_USB_HCI
++
++//should be renamed and moved to another file
++typedef enum _BOARD_TYPE_8192CUSB{
++ BOARD_USB_DONGLE = 0, // USB dongle
++ BOARD_USB_High_PA = 1, // USB dongle with high power PA
++ BOARD_MINICARD = 2, // Minicard
++ BOARD_USB_SOLO = 3, // USB solo-Slim module
++ BOARD_USB_COMBO = 4, // USB Combo-Slim module
++} BOARD_TYPE_8192CUSB, *PBOARD_TYPE_8192CUSB;
++
++#define SUPPORT_HW_RADIO_DETECT(pHalData) (pHalData->BoardType == BOARD_MINICARD||\
++ pHalData->BoardType == BOARD_USB_SOLO||\
++ pHalData->BoardType == BOARD_USB_COMBO)
++
++//---------------------------------------------------------------
++// EEPROM address for Test chip
++//---------------------------------------------------------------
++#define EEPROM_TEST_USB_OPT 0x0E
++#define EEPROM_TEST_CHIRP_K 0x0F
++#define EEPROM_TEST_EP_SETTING 0x0E
++#define EEPROM_TEST_USB_PHY 0x10
++
++
++//---------------------------------------------------------------
++// EEPROM address for Normal chip
++//---------------------------------------------------------------
++#define EEPROM_NORMAL_USB_OPT 0x0E
++#define EEPROM_NORMAL_CHIRP_K 0x0E // Changed
++#define EEPROM_NORMAL_EP_SETTING 0x0F // Changed
++#define EEPROM_NORMAL_USB_PHY 0x12 // Changed
++
++
++// Test chip and normal chip common define
++//---------------------------------------------------------------
++// EEPROM address for both
++//---------------------------------------------------------------
++#define EEPROM_ID0 0x00
++#define EEPROM_ID1 0x01
++#define EEPROM_RTK_RSV1 0x02
++#define EEPROM_RTK_RSV2 0x03
++#define EEPROM_RTK_RSV3 0x04
++#define EEPROM_RTK_RSV4 0x05
++#define EEPROM_RTK_RSV5 0x06
++#define EEPROM_DBG_SEL 0x07
++#define EEPROM_RTK_RSV6 0x08
++#define EEPROM_VID 0x0A
++#define EEPROM_PID 0x0C
++
++#define EEPROM_MAC_ADDR 0x16
++#define EEPROM_STRING 0x1C
++#define EEPROM_SUBCUSTOMER_ID 0x59
++#define EEPROM_CCK_TX_PWR_INX 0x5A
++#define EEPROM_HT40_1S_TX_PWR_INX 0x60
++#define EEPROM_HT40_2S_TX_PWR_INX_DIFF 0x66
++#define EEPROM_HT20_TX_PWR_INX_DIFF 0x69
++#define EEPROM_OFDM_TX_PWR_INX_DIFF 0x6C
++#define EEPROM_HT40_MAX_PWR_OFFSET 0x6F
++#define EEPROM_HT20_MAX_PWR_OFFSET 0x72
++
++#define EEPROM_CHANNEL_PLAN 0x75
++#define EEPROM_TSSI_A 0x76
++#define EEPROM_TSSI_B 0x77
++#define EEPROM_THERMAL_METER 0x78
++#define EEPROM_RF_OPT1 0x79
++#define EEPROM_RF_OPT2 0x7A
++#define EEPROM_RF_OPT3 0x7B
++#define EEPROM_RF_OPT4 0x7C
++#define EEPROM_VERSION 0x7E
++#define EEPROM_CUSTOMER_ID 0x7F
++
++#define EEPROM_BoardType 0x54 //0x0: RTL8188SU, 0x1: RTL8191SU, 0x2: RTL8192SU, 0x3: RTL8191GU
++#define EEPROM_TxPwIndex 0x5C //0x5C-0x76, Tx Power index.
++#define EEPROM_PwDiff 0x67 // Difference of gain index between legacy and high throughput OFDM.
++
++#define EEPROM_TxPowerCCK 0x5A // CCK Tx Power
++
++// 2009/02/09 Cosa Add for SD3 requirement
++#define EEPROM_TX_PWR_HT20_DIFF 0x6e// HT20 Tx Power Index Difference
++#define DEFAULT_HT20_TXPWR_DIFF 2 // HT20<->40 default Tx Power Index Difference
++#define EEPROM_TX_PWR_OFDM_DIFF 0x71// OFDM Tx Power Index Difference
++
++#define EEPROM_TxPWRGroup 0x73// Power diff for channel group
++#define EEPROM_Regulatory 0x79// Check if power safety is need
++
++#define EEPROM_BLUETOOTH_COEXIST 0x7E // 92cu, 0x7E[4]
++#define EEPROM_NORMAL_BoardType EEPROM_RF_OPT1 //[7:5]
++#define BOARD_TYPE_NORMAL_MASK 0xE0
++#define BOARD_TYPE_TEST_MASK 0x0F
++#define EEPROM_EASY_REPLACEMENT 0x50//BIT0 1 for build-in module, 0 for external dongle
++//-------------------------------------------------------------
++// EEPROM content definitions
++//-------------------------------------------------------------
++#define OS_LINK_SPEED BIT(5)
++
++#define BOARD_TYPE_MASK 0xF
++
++#define BT_COEXISTENCE BIT(4)
++#define BT_CO_SHIFT 4
++
++#define EP_NUMBER_MASK 0x30 //bit 4:5 0Eh
++#define EP_NUMBER_SHIFT 4
++
++
++#define USB_PHY_PARA_SIZE 5
++
++
++//-------------------------------------------------------------
++// EEPROM default value definitions
++//-------------------------------------------------------------
++// Use 0xABCD instead of 0x8192 for debug
++#define EEPROM_DEF_ID_0 0xCD // Byte 0x00
++#define EEPROM_DEF_ID_1 0xAB // Byte 0x01
++
++#define EEPROM_DEF_RTK_RSV_A3 0x74 // Byte 0x03
++#define EEPROM_DEF_RTK_RSV_A4 0x6D // Byte 0x04
++#define EEPROM_DEF_RTK_RSV_A8 0xFF // Byte 0x08
++
++#define EEPROM_DEF_VID_0 0x0A // Byte 0x0A
++#define EEPROM_DEF_VID_1 0x0B
++
++#define EEPROM_DEF_PID_0 0x92 // Byte 0x0C
++#define EEPROM_DEF_PID_1 0x81
++
++
++#define EEPROM_TEST_DEF_USB_OPT 0x80 // Byte 0x0E
++#define EEPROM_NORMAL_DEF_USB_OPT 0x00 // Byte 0x0E
++
++#define EEPROM_DEF_CHIRPK 0x15 // Byte 0x0F
++
++#define EEPROM_DEF_USB_PHY_0 0x85 // Byte 0x10
++#define EEPROM_DEF_USB_PHY_1 0x62 // Byte 0x11
++#define EEPROM_DEF_USB_PHY_2 0x9E // Byte 0x12
++#define EEPROM_DEF_USB_PHY_3 0x06 // Byte 0x13
++
++#define EEPROM_DEF_TSSI_A 0x09 // Byte 0x78
++#define EEPROM_DEF_TSSI_B 0x09 // Byte 0x79
++
++
++#define EEPROM_DEF_THERMAL_METER 0x12 // Byte 0x7A
++
++#define RF_OPTION1 0x79// Check if power safety spec is need
++#define RF_OPTION2 0x7A
++#define RF_OPTION3 0x7B
++#define RF_OPTION4 0x7C
++
++
++#define EEPROM_USB_SN BIT(0)
++#define EEPROM_USB_REMOTE_WAKEUP BIT(1)
++#define EEPROM_USB_DEVICE_PWR BIT(2)
++#define EEPROM_EP_NUMBER (BIT(3)|BIT(4))
++
++#if 0
++#define EEPROM_CHANNEL_PLAN_FCC 0x0
++#define EEPROM_CHANNEL_PLAN_IC 0x1
++#define EEPROM_CHANNEL_PLAN_ETSI 0x2
++#define EEPROM_CHANNEL_PLAN_SPAIN 0x3
++#define EEPROM_CHANNEL_PLAN_FRANCE 0x4
++#define EEPROM_CHANNEL_PLAN_MKK 0x5
++#define EEPROM_CHANNEL_PLAN_MKK1 0x6
++#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7
++#define EEPROM_CHANNEL_PLAN_TELEC 0x8
++#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9
++#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA
++#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80
++
++#define EEPROM_CID_DEFAULT 0x0
++
++#define EEPROM_CID_WHQL 0xFE // added by chiyoko for dtm, 20090108
++
++
++#define EEPROM_CID_CCX 0x10 // CCX test. By Bruce, 2009-02-25.
++#endif
++
++#endif
++
++
++/*===================================================================
++=====================================================================
++Here the register defines are for 92C. When the define is as same with 92C,
++we will use the 92C's define for the consistency
++So the following defines for 92C is not entire!!!!!!
++=====================================================================
++=====================================================================*/
++/*
++Based on Datasheet V33---090401
++Register Summary
++Current IOREG MAP
++0x0000h ~ 0x00FFh System Configuration (256 Bytes)
++0x0100h ~ 0x01FFh MACTOP General Configuration (256 Bytes)
++0x0200h ~ 0x027Fh TXDMA Configuration (128 Bytes)
++0x0280h ~ 0x02FFh RXDMA Configuration (128 Bytes)
++0x0300h ~ 0x03FFh PCIE EMAC Reserved Region (256 Bytes)
++0x0400h ~ 0x04FFh Protocol Configuration (256 Bytes)
++0x0500h ~ 0x05FFh EDCA Configuration (256 Bytes)
++0x0600h ~ 0x07FFh WMAC Configuration (512 Bytes)
++0x2000h ~ 0x3FFFh 8051 FW Download Region (8196 Bytes)
++*/
++
++//----------------------------------------------------------------------------
++// 8192C (RCR) Receive Configuration Register (Offset 0x608, 32 bits)
++//----------------------------------------------------------------------------
++#define RCR_APPFCS BIT31 //WMAC append FCS after pauload
++#define RCR_APP_MIC BIT30 //
++#define RCR_APP_PHYSTS BIT28//
++#define RCR_APP_ICV BIT29 //
++#define RCR_APP_PHYST_RXFF BIT28 //
++#define RCR_APP_BA_SSN BIT27 //Accept BA SSN
++#define RCR_ENMBID BIT24 //Enable Multiple BssId.
++#define RCR_LSIGEN BIT23
++#define RCR_MFBEN BIT22
++#define RCR_HTC_LOC_CTRL BIT14 //MFC<--HTC=1 MFC-->HTC=0
++#define RCR_AMF BIT13 //Accept management type frame
++#define RCR_ACF BIT12 //Accept control type frame
++#define RCR_ADF BIT11 //Accept data type frame
++#define RCR_AICV BIT9 //Accept ICV error packet
++#define RCR_ACRC32 BIT8 //Accept CRC32 error packet
++#define RCR_CBSSID_BCN BIT7 //Accept BSSID match packet (Rx beacon, probe rsp)
++#define RCR_CBSSID_DATA BIT6 //Accept BSSID match packet (Data)
++#define RCR_CBSSID RCR_CBSSID_DATA //Accept BSSID match packet
++#define RCR_APWRMGT BIT5 //Accept power management packet
++#define RCR_ADD3 BIT4 //Accept address 3 match packet
++#define RCR_AB BIT3 //Accept broadcast packet
++#define RCR_AM BIT2 //Accept multicast packet
++#define RCR_APM BIT1 //Accept physical match packet
++#define RCR_AAP BIT0 //Accept all unicast packet
++#define RCR_MXDMA_OFFSET 8
++#define RCR_FIFO_OFFSET 13
++
++
++
++//============================================================================
++// 8192c USB specific Regsiter Offset and Content definition,
++// 2009.08.18, added by vivi. for merge 92c and 92C into one driver
++//============================================================================
++//#define APS_FSMCO 0x0004 same with 92Ce
++#define RSV_CTRL 0x001C
++#define RD_CTRL 0x0524
++
++//-----------------------------------------------------
++//
++// 0xFE00h ~ 0xFE55h USB Configuration
++//
++//-----------------------------------------------------
++#define REG_USB_INFO 0xFE17
++#define REG_USB_SPECIAL_OPTION 0xFE55
++#define REG_USB_DMA_AGG_TO 0xFE5B
++#define REG_USB_AGG_TO 0xFE5C
++#define REG_USB_AGG_TH 0xFE5D
++
++#define REG_USB_VID 0xFE60
++#define REG_USB_PID 0xFE62
++#define REG_USB_OPTIONAL 0xFE64
++#define REG_USB_CHIRP_K 0xFE65
++#define REG_USB_PHY 0xFE66
++#define REG_USB_MAC_ADDR 0xFE70
++
++#define REG_USB_HRPWM 0xFE58
++#define REG_USB_HCPWM 0xFE57
++
++#define InvalidBBRFValue 0x12345678
++
++//============================================================================
++// 8192C Regsiter Bit and Content definition
++//============================================================================
++//-----------------------------------------------------
++//
++// 0x0000h ~ 0x00FFh System Configuration
++//
++//-----------------------------------------------------
++
++//2 SPS0_CTRL
++#define SW18_FPWM BIT(3)
++
++
++//2 SYS_ISO_CTRL
++#define ISO_MD2PP BIT(0)
++#define ISO_UA2USB BIT(1)
++#define ISO_UD2CORE BIT(2)
++#define ISO_PA2PCIE BIT(3)
++#define ISO_PD2CORE BIT(4)
++#define ISO_IP2MAC BIT(5)
++#define ISO_DIOP BIT(6)
++#define ISO_DIOE BIT(7)
++#define ISO_EB2CORE BIT(8)
++#define ISO_DIOR BIT(9)
++
++#define PWC_EV25V BIT(14)
++#define PWC_EV12V BIT(15)
++
++
++//2 SYS_FUNC_EN
++#define FEN_BBRSTB BIT(0)
++#define FEN_BB_GLB_RSTn BIT(1)
++#define FEN_USBA BIT(2)
++#define FEN_UPLL BIT(3)
++#define FEN_USBD BIT(4)
++#define FEN_DIO_PCIE BIT(5)
++#define FEN_PCIEA BIT(6)
++#define FEN_PPLL BIT(7)
++#define FEN_PCIED BIT(8)
++#define FEN_DIOE BIT(9)
++#define FEN_CPUEN BIT(10)
++#define FEN_DCORE BIT(11)
++#define FEN_ELDR BIT(12)
++#define FEN_DIO_RF BIT(13)
++#define FEN_HWPDN BIT(14)
++#define FEN_MREGEN BIT(15)
++
++//2 APS_FSMCO
++#define PFM_LDALL BIT(0)
++#define PFM_ALDN BIT(1)
++#define PFM_LDKP BIT(2)
++#define PFM_WOWL BIT(3)
++#define EnPDN BIT(4)
++#define PDN_PL BIT(5)
++#define APFM_ONMAC BIT(8)
++#define APFM_OFF BIT(9)
++#define APFM_RSM BIT(10)
++#define AFSM_HSUS BIT(11)
++#define AFSM_PCIE BIT(12)
++#define APDM_MAC BIT(13)
++#define APDM_HOST BIT(14)
++#define APDM_HPDN BIT(15)
++#define RDY_MACON BIT(16)
++#define SUS_HOST BIT(17)
++#define ROP_ALD BIT(20)
++#define ROP_PWR BIT(21)
++#define ROP_SPS BIT(22)
++#define SOP_MRST BIT(25)
++#define SOP_FUSE BIT(26)
++#define SOP_ABG BIT(27)
++#define SOP_AMB BIT(28)
++#define SOP_RCK BIT(29)
++#define SOP_A8M BIT(30)
++#define XOP_BTCK BIT(31)
++
++//2 SYS_CLKR
++#define ANAD16V_EN BIT(0)
++#define ANA8M BIT(1)
++#define MACSLP BIT(4)
++#define LOADER_CLK_EN BIT(5)
++#define _80M_SSC_DIS BIT(7)
++#define _80M_SSC_EN_HO BIT(8)
++#define PHY_SSC_RSTB BIT(9)
++#define SEC_CLK_EN BIT(10)
++#define MAC_CLK_EN BIT(11)
++#define SYS_CLK_EN BIT(12)
++#define RING_CLK_EN BIT(13)
++
++
++//2 9346CR
++
++
++#define EEDO BIT(0)
++#define EEDI BIT(1)
++#define EESK BIT(2)
++#define EECS BIT(3)
++//#define EERPROMSEL BIT(4)
++//#define EEPROM_EN BIT(5)
++#define BOOT_FROM_EEPROM BIT(4)
++#define EEPROM_EN BIT(5)
++#define EEM0 BIT(6)
++#define EEM1 BIT(7)
++
++
++//2 AFE_MISC
++#define AFE_BGEN BIT(0)
++#define AFE_MBEN BIT(1)
++#define MAC_ID_EN BIT(7)
++
++
++//2 SPS0_CTRL
++
++
++//2 SPS_OCP_CFG
++
++
++//2 RSV_CTRL
++#define WLOCK_ALL BIT(0)
++#define WLOCK_00 BIT(1)
++#define WLOCK_04 BIT(2)
++#define WLOCK_08 BIT(3)
++#define WLOCK_40 BIT(4)
++#define R_DIS_PRST_0 BIT(5)
++#define R_DIS_PRST_1 BIT(6)
++#define LOCK_ALL_EN BIT(7)
++
++//2 RF_CTRL
++#define RF_EN BIT(0)
++#define RF_RSTB BIT(1)
++#define RF_SDMRSTB BIT(2)
++
++
++
++//2 LDOA15_CTRL
++#define LDA15_EN BIT(0)
++#define LDA15_STBY BIT(1)
++#define LDA15_OBUF BIT(2)
++#define LDA15_REG_VOS BIT(3)
++#define _LDA15_VOADJ(x) (((x) & 0x7) << 4)
++
++
++
++//2 LDOV12D_CTRL
++#define LDV12_EN BIT(0)
++#define LDV12_SDBY BIT(1)
++#define LPLDO_HSM BIT(2)
++#define LPLDO_LSM_DIS BIT(3)
++#define _LDV12_VADJ(x) (((x) & 0xF) << 4)
++
++
++//2 AFE_XTAL_CTRL
++#define XTAL_EN BIT(0)
++#define XTAL_BSEL BIT(1)
++#define _XTAL_BOSC(x) (((x) & 0x3) << 2)
++#define _XTAL_CADJ(x) (((x) & 0xF) << 4)
++#define XTAL_GATE_USB BIT(8)
++#define _XTAL_USB_DRV(x) (((x) & 0x3) << 9)
++#define XTAL_GATE_AFE BIT(11)
++#define _XTAL_AFE_DRV(x) (((x) & 0x3) << 12)
++#define XTAL_RF_GATE BIT(14)
++#define _XTAL_RF_DRV(x) (((x) & 0x3) << 15)
++#define XTAL_GATE_DIG BIT(17)
++#define _XTAL_DIG_DRV(x) (((x) & 0x3) << 18)
++#define XTAL_BT_GATE BIT(20)
++#define _XTAL_BT_DRV(x) (((x) & 0x3) << 21)
++#define _XTAL_GPIO(x) (((x) & 0x7) << 23)
++
++
++#define CKDLY_AFE BIT(26)
++#define CKDLY_USB BIT(27)
++#define CKDLY_DIG BIT(28)
++#define CKDLY_BT BIT(29)
++
++
++//2 AFE_PLL_CTRL
++#define APLL_EN BIT(0)
++#define APLL_320_EN BIT(1)
++#define APLL_FREF_SEL BIT(2)
++#define APLL_EDGE_SEL BIT(3)
++#define APLL_WDOGB BIT(4)
++#define APLL_LPFEN BIT(5)
++
++#define APLL_REF_CLK_13MHZ 0x1
++#define APLL_REF_CLK_19_2MHZ 0x2
++#define APLL_REF_CLK_20MHZ 0x3
++#define APLL_REF_CLK_25MHZ 0x4
++#define APLL_REF_CLK_26MHZ 0x5
++#define APLL_REF_CLK_38_4MHZ 0x6
++#define APLL_REF_CLK_40MHZ 0x7
++
++#define APLL_320EN BIT(14)
++#define APLL_80EN BIT(15)
++#define APLL_1MEN BIT(24)
++
++
++//2 EFUSE_CTRL
++#define ALD_EN BIT(18)
++#define EF_PD BIT(19)
++#define EF_FLAG BIT(31)
++
++//2 EFUSE_TEST (For RTL8723 partially)
++#define EF_TRPT BIT(7)
++#define EF_CELL_SEL (BIT(8)|BIT(9)) // 00: Wifi Efuse, 01: BT Efuse0, 10: BT Efuse1, 11: BT Efuse2
++#define LDOE25_EN BIT(31)
++#define EFUSE_SEL(x) (((x) & 0x3) << 8)
++#define EFUSE_SEL_MASK 0x300
++#define EFUSE_WIFI_SEL_0 0x0
++#define EFUSE_BT_SEL_0 0x1
++#define EFUSE_BT_SEL_1 0x2
++#define EFUSE_BT_SEL_2 0x3
++
++#define EFUSE_ACCESS_ON 0x69 // For RTL8723 only.
++#define EFUSE_ACCESS_OFF 0x00 // For RTL8723 only.
++
++//2 PWR_DATA
++
++//2 CAL_TIMER
++
++//2 ACLK_MON
++#define RSM_EN BIT(0)
++#define Timer_EN BIT(4)
++
++
++//2 GPIO_MUXCFG
++#define TRSW0EN BIT(2)
++#define TRSW1EN BIT(3)
++#define EROM_EN BIT(4)
++#define EnBT BIT(5)
++#define EnUart BIT(8)
++#define Uart_910 BIT(9)
++#define EnPMAC BIT(10)
++#define SIC_SWRST BIT(11)
++#define EnSIC BIT(12)
++#define SIC_23 BIT(13)
++#define EnHDP BIT(14)
++#define SIC_LBK BIT(15)
++
++//2 GPIO_PIN_CTRL
++
++// GPIO BIT
++#define HAL_8192C_HW_GPIO_WPS_BIT BIT(2)
++
++//2 GPIO_INTM
++
++//2 LEDCFG
++#define LED0PL BIT(4)
++#define LED0DIS BIT(7)
++#define LED1DIS BIT(15)
++#define LED1PL BIT(12)
++
++#define SECCAM_CLR BIT(30)
++
++
++//2 FSIMR
++
++//2 FSISR
++
++
++//2 8051FWDL
++//2 MCUFWDL
++#define MCUFWDL_EN BIT(0)
++#define MCUFWDL_RDY BIT(1)
++#define FWDL_ChkSum_rpt BIT(2)
++#define MACINI_RDY BIT(3)
++#define BBINI_RDY BIT(4)
++#define RFINI_RDY BIT(5)
++#define WINTINI_RDY BIT(6)
++#define CPRST BIT(23)
++
++//2REG_HPON_FSM
++#define BOND92CE_1T2R_CFG BIT(22)
++
++
++//2 REG_SYS_CFG
++#define XCLK_VLD BIT(0)
++#define ACLK_VLD BIT(1)
++#define UCLK_VLD BIT(2)
++#define PCLK_VLD BIT(3)
++#define PCIRSTB BIT(4)
++#define V15_VLD BIT(5)
++#define TRP_B15V_EN BIT(7)
++#define SIC_IDLE BIT(8)
++#define BD_MAC2 BIT(9)
++#define BD_MAC1 BIT(10)
++#define IC_MACPHY_MODE BIT(11)
++#define CHIP_VER (BIT(12)|BIT(13)|BIT(14)|BIT(15))
++#define BT_FUNC BIT(16)
++#define VENDOR_ID BIT(19)
++#define PAD_HWPD_IDN BIT(22)
++#define TRP_VAUX_EN BIT(23)
++#define TRP_BT_EN BIT(24)
++#define BD_PKG_SEL BIT(25)
++#define BD_HCI_SEL BIT(26)
++#define TYPE_ID BIT(27)
++
++#define CHIP_VER_RTL_MASK 0xF000 //Bit 12 ~ 15
++#define CHIP_VER_RTL_SHIFT 12
++
++//2REG_GPIO_OUTSTS (For RTL8723 only)
++#define EFS_HCI_SEL (BIT(0)|BIT(1))
++#define PAD_HCI_SEL (BIT(2)|BIT(3))
++#define HCI_SEL (BIT(4)|BIT(5))
++#define PKG_SEL_HCI BIT(6)
++#define FEN_GPS BIT(7)
++#define FEN_BT BIT(8)
++#define FEN_WL BIT(9)
++#define FEN_PCI BIT(10)
++#define FEN_USB BIT(11)
++#define BTRF_HWPDN_N BIT(12)
++#define WLRF_HWPDN_N BIT(13)
++#define PDN_BT_N BIT(14)
++#define PDN_GPS_N BIT(15)
++#define BT_CTL_HWPDN BIT(16)
++#define GPS_CTL_HWPDN BIT(17)
++#define PPHY_SUSB BIT(20)
++#define UPHY_SUSB BIT(21)
++#define PCI_SUSEN BIT(22)
++#define USB_SUSEN BIT(23)
++#define RF_RL_ID (BIT(31)|BIT(30)|BIT(29)|BIT(28))
++
++//-----------------------------------------------------
++//
++// 0x0100h ~ 0x01FFh MACTOP General Configuration
++//
++//-----------------------------------------------------
++
++
++//2 Function Enable Registers
++//2 CR
++
++#define REG_LBMODE (REG_CR + 3)
++
++
++#define HCI_TXDMA_EN BIT(0)
++#define HCI_RXDMA_EN BIT(1)
++#define TXDMA_EN BIT(2)
++#define RXDMA_EN BIT(3)
++#define PROTOCOL_EN BIT(4)
++#define SCHEDULE_EN BIT(5)
++#define MACTXEN BIT(6)
++#define MACRXEN BIT(7)
++#define ENSWBCN BIT(8)
++#define ENSEC BIT(9)
++
++// Network type
++#define _NETTYPE(x) (((x) & 0x3) << 16)
++#define MASK_NETTYPE 0x30000
++#define NT_NO_LINK 0x0
++#define NT_LINK_AD_HOC 0x1
++#define NT_LINK_AP 0x2
++#define NT_AS_AP 0x3
++
++#define _LBMODE(x) (((x) & 0xF) << 24)
++#define MASK_LBMODE 0xF000000
++#define LOOPBACK_NORMAL 0x0
++#define LOOPBACK_IMMEDIATELY 0xB
++#define LOOPBACK_MAC_DELAY 0x3
++#define LOOPBACK_PHY 0x1
++#define LOOPBACK_DMA 0x7
++
++
++//2 PBP - Page Size Register
++#define GET_RX_PAGE_SIZE(value) ((value) & 0xF)
++#define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4)
++#define _PSRX_MASK 0xF
++#define _PSTX_MASK 0xF0
++#define _PSRX(x) (x)
++#define _PSTX(x) ((x) << 4)
++
++#define PBP_64 0x0
++#define PBP_128 0x1
++#define PBP_256 0x2
++#define PBP_512 0x3
++#define PBP_1024 0x4
++
++
++//2 TX/RXDMA
++#define RXDMA_ARBBW_EN BIT(0)
++#define RXSHFT_EN BIT(1)
++#define RXDMA_AGG_EN BIT(2)
++#define QS_VO_QUEUE BIT(8)
++#define QS_VI_QUEUE BIT(9)
++#define QS_BE_QUEUE BIT(10)
++#define QS_BK_QUEUE BIT(11)
++#define QS_MANAGER_QUEUE BIT(12)
++#define QS_HIGH_QUEUE BIT(13)
++
++#define HQSEL_VOQ BIT(0)
++#define HQSEL_VIQ BIT(1)
++#define HQSEL_BEQ BIT(2)
++#define HQSEL_BKQ BIT(3)
++#define HQSEL_MGTQ BIT(4)
++#define HQSEL_HIQ BIT(5)
++
++// For normal driver, 0x10C
++#define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14)
++#define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12)
++#define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10)
++#define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8 )
++#define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6 )
++#define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4 )
++
++#define QUEUE_LOW 1
++#define QUEUE_NORMAL 2
++#define QUEUE_HIGH 3
++
++
++
++//2 TRXFF_BNDY
++
++
++//2 LLT_INIT
++#define _LLT_NO_ACTIVE 0x0
++#define _LLT_WRITE_ACCESS 0x1
++#define _LLT_READ_ACCESS 0x2
++
++#define _LLT_INIT_DATA(x) ((x) & 0xFF)
++#define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8)
++#define _LLT_OP(x) (((x) & 0x3) << 30)
++#define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3)
++
++
++//2 BB_ACCESS_CTRL
++#define BB_WRITE_READ_MASK (BIT(31) | BIT(30))
++#define BB_WRITE_EN BIT(30)
++#define BB_READ_EN BIT(31)
++//#define BB_ADDR_MASK 0xFFF
++//#define _BB_ADDR(x) ((x) & BB_ADDR_MASK)
++
++//-----------------------------------------------------
++//
++// 0x0200h ~ 0x027Fh TXDMA Configuration
++//
++//-----------------------------------------------------
++//2 RQPN
++#define _HPQ(x) ((x) & 0xFF)
++#define _LPQ(x) (((x) & 0xFF) << 8)
++#define _PUBQ(x) (((x) & 0xFF) << 16)
++#define _NPQ(x) ((x) & 0xFF) // NOTE: in RQPN_NPQ register
++
++
++#define HPQ_PUBLIC_DIS BIT(24)
++#define LPQ_PUBLIC_DIS BIT(25)
++#define LD_RQPN BIT(31)
++
++
++//2 TDECTRL
++#define BCN_VALID BIT(16)
++#define BCN_HEAD(x) (((x) & 0xFF) << 8)
++#define BCN_HEAD_MASK 0xFF00
++
++//2 TDECTL
++#define BLK_DESC_NUM_SHIFT 4
++#define BLK_DESC_NUM_MASK 0xF
++
++
++//2 TXDMA_OFFSET_CHK
++#define DROP_DATA_EN BIT(9)
++
++//-----------------------------------------------------
++//
++// 0x0400h ~ 0x047Fh Protocol Configuration
++//
++//-----------------------------------------------------
++//2 FWHW_TXQ_CTRL
++#define EN_AMPDU_RTY_NEW BIT(7)
++
++//2 INIRTSMCS_SEL
++#define _INIRTSMCS_SEL(x) ((x) & 0x3F)
++
++
++//2 SPEC SIFS
++#define _SPEC_SIFS_CCK(x) ((x) & 0xFF)
++#define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8)
++
++
++//2 RRSR
++
++#define RATE_REG_BITMAP_ALL 0xFFFFF
++
++#define _RRSC_BITMAP(x) ((x) & 0xFFFFF)
++
++#define _RRSR_RSC(x) (((x) & 0x3) << 21)
++#define RRSR_RSC_RESERVED 0x0
++#define RRSR_RSC_UPPER_SUBCHANNEL 0x1
++#define RRSR_RSC_LOWER_SUBCHANNEL 0x2
++#define RRSR_RSC_DUPLICATE_MODE 0x3
++
++
++//2 ARFR
++#define USE_SHORT_G1 BIT(20)
++
++//2 AGGLEN_LMT_L
++#define _AGGLMT_MCS0(x) ((x) & 0xF)
++#define _AGGLMT_MCS1(x) (((x) & 0xF) << 4)
++#define _AGGLMT_MCS2(x) (((x) & 0xF) << 8)
++#define _AGGLMT_MCS3(x) (((x) & 0xF) << 12)
++#define _AGGLMT_MCS4(x) (((x) & 0xF) << 16)
++#define _AGGLMT_MCS5(x) (((x) & 0xF) << 20)
++#define _AGGLMT_MCS6(x) (((x) & 0xF) << 24)
++#define _AGGLMT_MCS7(x) (((x) & 0xF) << 28)
++
++
++//2 RL
++#define RETRY_LIMIT_SHORT_SHIFT 8
++#define RETRY_LIMIT_LONG_SHIFT 0
++
++
++//2 DARFRC
++#define _DARF_RC1(x) ((x) & 0x1F)
++#define _DARF_RC2(x) (((x) & 0x1F) << 8)
++#define _DARF_RC3(x) (((x) & 0x1F) << 16)
++#define _DARF_RC4(x) (((x) & 0x1F) << 24)
++// NOTE: shift starting from address (DARFRC + 4)
++#define _DARF_RC5(x) ((x) & 0x1F)
++#define _DARF_RC6(x) (((x) & 0x1F) << 8)
++#define _DARF_RC7(x) (((x) & 0x1F) << 16)
++#define _DARF_RC8(x) (((x) & 0x1F) << 24)
++
++
++//2 RARFRC
++#define _RARF_RC1(x) ((x) & 0x1F)
++#define _RARF_RC2(x) (((x) & 0x1F) << 8)
++#define _RARF_RC3(x) (((x) & 0x1F) << 16)
++#define _RARF_RC4(x) (((x) & 0x1F) << 24)
++// NOTE: shift starting from address (RARFRC + 4)
++#define _RARF_RC5(x) ((x) & 0x1F)
++#define _RARF_RC6(x) (((x) & 0x1F) << 8)
++#define _RARF_RC7(x) (((x) & 0x1F) << 16)
++#define _RARF_RC8(x) (((x) & 0x1F) << 24)
++
++
++
++
++//-----------------------------------------------------
++//
++// 0x0500h ~ 0x05FFh EDCA Configuration
++//
++//-----------------------------------------------------
++
++
++
++//2 EDCA setting
++#define AC_PARAM_TXOP_LIMIT_OFFSET 16
++#define AC_PARAM_ECW_MAX_OFFSET 12
++#define AC_PARAM_ECW_MIN_OFFSET 8
++#define AC_PARAM_AIFS_OFFSET 0
++
++
++//2 EDCA_VO_PARAM
++#define _AIFS(x) (x)
++#define _ECW_MAX_MIN(x) ((x) << 8)
++#define _TXOP_LIMIT(x) ((x) << 16)
++
++
++#define _BCNIFS(x) ((x) & 0xFF)
++#define _BCNECW(x) (((x) & 0xF))<< 8)
++
++
++#define _LRL(x) ((x) & 0x3F)
++#define _SRL(x) (((x) & 0x3F) << 8)
++
++
++//2 SIFS_CCK
++#define _SIFS_CCK_CTX(x) ((x) & 0xFF)
++#define _SIFS_CCK_TRX(x) (((x) & 0xFF) << 8);
++
++
++//2 SIFS_OFDM
++#define _SIFS_OFDM_CTX(x) ((x) & 0xFF)
++#define _SIFS_OFDM_TRX(x) (((x) & 0xFF) << 8);
++
++
++//2 TBTT PROHIBIT
++#define _TBTT_PROHIBIT_HOLD(x) (((x) & 0xFF) << 8)
++
++
++//2 REG_RD_CTRL
++#define DIS_EDCA_CNT_DWN BIT(11)
++
++
++//2 BCN_CTRL
++#define EN_MBSSID BIT(1)
++#define EN_TXBCN_RPT BIT(2)
++#define EN_BCN_FUNCTION BIT(3)
++// The same function but different bit field.
++#define DIS_TSF_UDT0_NORMAL_CHIP BIT(4)
++#define DIS_TSF_UDT0_TEST_CHIP BIT(5)
++
++//2 ACMHWCTRL
++#define AcmHw_HwEn BIT(0)
++#define AcmHw_BeqEn BIT(1)
++#define AcmHw_ViqEn BIT(2)
++#define AcmHw_VoqEn BIT(3)
++#define AcmHw_BeqStatus BIT(4)
++#define AcmHw_ViqStatus BIT(5)
++#define AcmHw_VoqStatus BIT(6)
++
++
++
++//-----------------------------------------------------
++//
++// 0x0600h ~ 0x07FFh WMAC Configuration
++//
++//-----------------------------------------------------
++
++//2 APSD_CTRL
++#define APSDOFF BIT(6)
++#define APSDOFF_STATUS BIT(7)
++
++
++//2 BWOPMODE
++#define BW_20MHZ BIT(2)
++//#define BW_OPMODE_20MHZ BIT(2) // For compability
++
++
++#define RATE_BITMAP_ALL 0xFFFFF
++
++// Only use CCK 1M rate for ACK
++#define RATE_RRSR_CCK_ONLY_1M 0xFFFF1
++
++//2 TCR
++#define TSFRST BIT(0)
++#define DIS_GCLK BIT(1)
++#define PAD_SEL BIT(2)
++#define PWR_ST BIT(6)
++#define PWRBIT_OW_EN BIT(7)
++#define ACRC BIT(8)
++#define CFENDFORM BIT(9)
++#define ICV BIT(10)
++
++
++
++//2 RCR
++#define AAP BIT(0)
++#define APM BIT(1)
++#define AM BIT(2)
++#define AB BIT(3)
++#define ADD3 BIT(4)
++#define APWRMGT BIT(5)
++#define CBSSID BIT(6)
++#define CBSSID_BCN BIT(7)
++#define ACRC32 BIT(8)
++#define AICV BIT(9)
++#define ADF BIT(11)
++#define ACF BIT(12)
++#define AMF BIT(13)
++#define HTC_LOC_CTRL BIT(14)
++#define UC_DATA_EN BIT(16)
++#define BM_DATA_EN BIT(17)
++#define MFBEN BIT(22)
++#define LSIGEN BIT(23)
++#define EnMBID BIT(24)
++#define APP_BASSN BIT(27)
++#define APP_PHYSTS BIT(28)
++#define APP_ICV BIT(29)
++#define APP_MIC BIT(30)
++#define APP_FCS BIT(31)
++
++//2 RX_PKT_LIMIT
++
++//2 RX_DLK_TIME
++
++//2 MBIDCAMCFG
++
++
++
++//2 AMPDU_MIN_SPACE
++#define _MIN_SPACE(x) ((x) & 0x7)
++#define _SHORT_GI_PADDING(x) (((x) & 0x1F) << 3)
++
++
++//2 RXERR_RPT
++#define RXERR_TYPE_OFDM_PPDU 0
++#define RXERR_TYPE_OFDM_FALSE_ALARM 1
++#define RXERR_TYPE_OFDM_MPDU_OK 2
++#define RXERR_TYPE_OFDM_MPDU_FAIL 3
++#define RXERR_TYPE_CCK_PPDU 4
++#define RXERR_TYPE_CCK_FALSE_ALARM 5
++#define RXERR_TYPE_CCK_MPDU_OK 6
++#define RXERR_TYPE_CCK_MPDU_FAIL 7
++#define RXERR_TYPE_HT_PPDU 8
++#define RXERR_TYPE_HT_FALSE_ALARM 9
++#define RXERR_TYPE_HT_MPDU_TOTAL 10
++#define RXERR_TYPE_HT_MPDU_OK 11
++#define RXERR_TYPE_HT_MPDU_FAIL 12
++#define RXERR_TYPE_RX_FULL_DROP 15
++
++#define RXERR_COUNTER_MASK 0xFFFFF
++#define RXERR_RPT_RST BIT(27)
++#define _RXERR_RPT_SEL(type) ((type) << 28)
++
++
++//2 SECCFG
++#define SCR_TxUseDK BIT(0) //Force Tx Use Default Key
++#define SCR_RxUseDK BIT(1) //Force Rx Use Default Key
++#define SCR_TxEncEnable BIT(2) //Enable Tx Encryption
++#define SCR_RxDecEnable BIT(3) //Enable Rx Decryption
++#define SCR_SKByA2 BIT(4) //Search kEY BY A2
++#define SCR_NoSKMC BIT(5) //No Key Search Multicast
++
++
++
++//-----------------------------------------------------
++//
++// 0xFE00h ~ 0xFE55h USB Configuration
++//
++//-----------------------------------------------------
++
++//2 USB Information (0xFE17)
++#define USB_IS_HIGH_SPEED 0
++#define USB_IS_FULL_SPEED 1
++#define USB_SPEED_MASK BIT(5)
++
++#define USB_NORMAL_SIE_EP_MASK 0xF
++#define USB_NORMAL_SIE_EP_SHIFT 4
++
++#define USB_TEST_EP_MASK 0x30
++#define USB_TEST_EP_SHIFT 4
++
++//2 Special Option
++#define USB_AGG_EN BIT(3)
++
++
++//2REG_C2HEVT_CLEAR
++#define C2H_EVT_HOST_CLOSE 0x00 // Set by driver and notify FW that the driver has read the C2H command message
++#define C2H_EVT_FW_CLOSE 0xFF // Set by FW indicating that FW had set the C2H command message and it's not yet read by driver.
++
++
++//2REG_MULTI_FUNC_CTRL(For RTL8723 Only)
++#define WL_HWPDN_EN BIT0 // Enable GPIO[9] as WiFi HW PDn source
++#define WL_HWPDN_SL BIT1 // WiFi HW PDn polarity control
++#define WL_FUNC_EN BIT2 // WiFi function enable
++#define WL_HWROF_EN BIT3 // Enable GPIO[9] as WiFi RF HW PDn source
++#define BT_HWPDN_EN BIT16 // Enable GPIO[11] as BT HW PDn source
++#define BT_HWPDN_SL BIT17 // BT HW PDn polarity control
++#define BT_FUNC_EN BIT18 // BT function enable
++#define BT_HWROF_EN BIT19 // Enable GPIO[11] as BT/GPS RF HW PDn source
++#define GPS_HWPDN_EN BIT20 // Enable GPIO[10] as GPS HW PDn source
++#define GPS_HWPDN_SL BIT21 // GPS HW PDn polarity control
++#define GPS_FUNC_EN BIT22 // GPS function enable
++
++//3 REG_LIFECTRL_CTRL
++#define HAL92C_EN_PKT_LIFE_TIME_BK BIT3
++#define HAL92C_EN_PKT_LIFE_TIME_BE BIT2
++#define HAL92C_EN_PKT_LIFE_TIME_VI BIT1
++#define HAL92C_EN_PKT_LIFE_TIME_VO BIT0
++
++#define HAL92C_MSDU_LIFE_TIME_UNIT 128 // in us, said by Tim.
++
++//========================================================
++// General definitions
++//========================================================
++
++#define MAC_ADDR_LEN 6
++#define LAST_ENTRY_OF_TX_PKT_BUFFER 255
++
++#define POLLING_LLT_THRESHOLD 20
++#define POLLING_READY_TIMEOUT_COUNT 1000
++
++// Min Spacing related settings.
++#define MAX_MSS_DENSITY_2T 0x13
++#define MAX_MSS_DENSITY_1T 0x0A
++
++//----------------------------------------------------------------------------
++// 8192C GPIO MUX Configuration Register (offset 0x40, 4 byte)
++//----------------------------------------------------------------------------
++#define GPIOSEL_GPIO 0
++#define GPIOSEL_ENBT BIT5
++
++//----------------------------------------------------------------------------
++// 8192C GPIO PIN Control Register (offset 0x44, 4 byte)
++//----------------------------------------------------------------------------
++#define GPIO_IN REG_GPIO_PIN_CTRL // GPIO pins input value
++#define GPIO_OUT (REG_GPIO_PIN_CTRL+1) // GPIO pins output value
++#define GPIO_IO_SEL (REG_GPIO_PIN_CTRL+2) // GPIO pins output enable when a bit is set to "1"; otherwise, input is configured.
++#define GPIO_MOD (REG_GPIO_PIN_CTRL+3)
++
++
++
++#include "basic_types.h"
++
++#endif
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtl8192c_sreset.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtl8192c_sreset.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtl8192c_sreset.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtl8192c_sreset.h 2015-07-28 01:20:58.321597318 +0200
+@@ -0,0 +1,32 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef _RTL8192C_SRESET_C_
++#define _RTL8192C_SRESET_C_
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++#include <rtw_sreset.h>
++
++#ifdef DBG_CONFIG_ERROR_DETECT
++extern void rtl8192c_sreset_xmit_status_check(_adapter *padapter);
++extern void rtl8192c_sreset_linked_status_check(_adapter *padapter);
++#endif
++#endif
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtl8192c_xmit.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtl8192c_xmit.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtl8192c_xmit.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtl8192c_xmit.h 2015-07-28 01:20:58.321597318 +0200
+@@ -0,0 +1,128 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef _RTL8192C_XMIT_H_
++#define _RTL8192C_XMIT_H_
++
++//
++// Queue Select Value in TxDesc
++//
++#define QSLT_BK 0x2//0x01
++#define QSLT_BE 0x0
++#define QSLT_VI 0x5//0x4
++#define QSLT_VO 0x7//0x6
++#define QSLT_BEACON 0x10
++#define QSLT_HIGH 0x11
++#define QSLT_MGNT 0x12
++#define QSLT_CMD 0x13
++
++struct txrpt_ccx_8192c {
++ /* offset 0 */
++ u8 retry_cnt:6;
++ u8 rsvd_0:2;
++
++ /* offset 1 */
++ u8 rts_retry_cnt:6;
++ u8 rsvd_1:2;
++
++ /* offset 2 */
++ u8 ccx_qtime0;
++ u8 ccx_qtime1;
++
++ /* offset 4 */
++ u8 missed_pkt_num:5;
++ u8 rsvd_4:3;
++
++ /* offset 5 */
++ u8 mac_id:5;
++ u8 des1_fragssn:3;
++
++ /* offset 6 */
++ u8 rpt_pkt_num:5;
++ u8 pkt_drop:1;
++ u8 lifetime_over:1;
++ u8 retry_over:1;
++
++ /* offset 7*/
++ u8 edca_tx_queue:4;
++ u8 rsvd_7:1;
++ u8 bmc:1;
++ u8 pkt_ok:1;
++ u8 int_ccx:1;
++};
++
++#define txrpt_ccx_qtime_8192c(txrpt_ccx) ((txrpt_ccx)->ccx_qtime0+((txrpt_ccx)->ccx_qtime1<<8))
++
++#ifdef CONFIG_XMIT_ACK
++void dump_txrpt_ccx_8192c(void *buf);
++void handle_txrpt_ccx_8192c(_adapter *adapter, void *buf);
++#else
++#define dump_txrpt_ccx_8192c(buf) do {} while(0)
++#define handle_txrpt_ccx_8192c(adapter, buf) do {} while(0)
++#endif
++
++#ifdef CONFIG_USB_HCI
++
++#ifdef CONFIG_USB_TX_AGGREGATION
++#define MAX_TX_AGG_PACKET_NUMBER 0xFF
++#endif
++
++s32 rtl8192cu_init_xmit_priv(_adapter * padapter);
++
++void rtl8192cu_free_xmit_priv(_adapter * padapter);
++
++void rtl8192cu_cal_txdesc_chksum(struct tx_desc *ptxdesc);
++
++s32 rtl8192cu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
++
++s32 rtl8192cu_mgnt_xmit(_adapter *padapter, struct xmit_frame *pmgntframe);
++
++s32 rtl8192cu_hal_xmit(_adapter *padapter, struct xmit_frame *pxmitframe);
++
++s32 rtl8192cu_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
++
++#ifdef CONFIG_HOSTAPD_MLME
++s32 rtl8192cu_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt);
++#endif
++
++#endif
++
++#ifdef CONFIG_PCI_HCI
++s32 rtl8192ce_init_xmit_priv(_adapter * padapter);
++void rtl8192ce_free_xmit_priv(_adapter * padapter);
++
++s32 rtl8192ce_enqueue_xmitbuf(struct rtw_tx_ring *ring, struct xmit_buf *pxmitbuf);
++struct xmit_buf *rtl8192ce_dequeue_xmitbuf(struct rtw_tx_ring *ring);
++
++void rtl8192ce_xmitframe_resume(_adapter *padapter);
++
++s32 rtl8192ce_mgnt_xmit(_adapter *padapter, struct xmit_frame *pmgntframe);
++
++s32 rtl8192ce_hal_xmit(_adapter *padapter, struct xmit_frame *pxmitframe);
++
++s32 rtl8192ce_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
++
++
++#ifdef CONFIG_HOSTAPD_MLME
++s32 rtl8192ce_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt);
++#endif
++
++#endif
++
++#endif
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtl8192d_cmd.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtl8192d_cmd.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtl8192d_cmd.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtl8192d_cmd.h 2015-07-28 01:20:58.321597318 +0200
+@@ -0,0 +1,140 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef __RTL8192D_CMD_H_
++#define __RTL8192D_CMD_H_
++
++
++//--------------------------------------------
++//3 Host Message Box
++//--------------------------------------------
++
++// User Define Message [31:8]
++
++//_SETPWRMODE_PARM
++#define SET_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
++#define SET_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
++#define SET_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
++
++//JOINBSSRPT_PARM
++#define SET_H2CCMD_JOINBSSRPT_PARM_OPMODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
++
++//_RSVDPAGE_LOC
++#define SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
++#define SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
++#define SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
++
++//P2P_PS_OFFLOAD
++
++struct P2P_PS_Offload_t {
++ unsigned char Offload_En:1;
++ unsigned char role:1; // 1: Owner, 0: Client
++ unsigned char CTWindow_En:1;
++ unsigned char NoA0_En:1;
++ unsigned char NoA1_En:1;
++ unsigned char AllStaSleep:1; // Only valid in Owner
++ unsigned char discovery:1;
++ unsigned char rsvd:1;
++};
++
++#define SET_H2CCMD_P2P_PS_OFFLOAD_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
++#define SET_H2CCMD_P2P_PS_OFFLOAD_ROLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
++#define SET_H2CCMD_P2P_PS_OFFLOAD_CTW(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
++#define SET_H2CCMD_P2P_PS_OFFLOAD_NOA0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)
++#define SET_H2CCMD_P2P_PS_OFFLOAD_NOA1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value)
++#define SET_H2CCMD_P2P_PS_OFFLOAD_ALLSTASLEEP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 1, __Value)
++#define SET_H2CCMD_P2P_PS_OFFLOAD_DISCOVERY(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 6, 1, __Value)
++
++// Description: Determine the types of H2C commands that are the same in driver and Fw.
++// Fisrt constructed by tynli. 2009.10.09.
++typedef enum _RTL8192D_H2C_CMD
++{
++ H2C_AP_OFFLOAD = 0, /*0*/
++ H2C_SETPWRMODE = 1, /*1*/
++ H2C_JOINBSSRPT = 2, /*2*/
++ H2C_RSVDPAGE = 3,
++ H2C_RSSI_REPORT = 5,
++ H2C_RA_MASK = 6,
++ H2C_P2P_PS_OFFLOAD = 8,
++ H2C_MAC_MODE_SEL = 9,
++ H2C_PWRM=15,
++#ifdef CONFIG_WOWLAN
++ H2C_WO_WLAN_CMD = 20, // Wake on Wlan.
++#endif // CONFIG_WOWLAN
++ H2C_P2P_PS_CTW_CMD = 24,
++ H2C_PathDiv = 26, //PathDiv--NeilChen--2011.07.15
++#ifdef CONFIG_WOWLAN
++ KEEP_ALIVE_CONTROL_CMD=31, //keep alive for wake on wlan
++ DISCONNECT_DECISION_CTRL_CMD=32,
++ REMOTE_WAKE_CTRL_CMD=34,
++#endif // CONFIG_WOWLAN
++ H2C_92D_TSF_SYNC=36,
++ H2C_92D_RESET_TSF = 43,
++ H2C_CMD_MAX
++}RTL8192D_H2C_CMD;
++
++struct cmd_msg_parm {
++ u8 eid; //element id
++ u8 sz; // sz
++ u8 buf[6];
++};
++
++
++void FillH2CCmd92D(_adapter* padapter, u8 ElementID, u32 CmdLen, u8* pCmdBuffer);
++
++// host message to firmware cmd
++void rtl8192d_set_FwPwrMode_cmd(_adapter*padapter, u8 Mode);
++void rtl8192d_set_FwJoinBssReport_cmd(_adapter* padapter, u8 mstatus);
++u8 rtl8192d_set_rssi_cmd(_adapter*padapter, u8 *param);
++u8 rtl8192d_set_raid_cmd(_adapter*padapter, u32 mask, u8 arg);
++void rtl8192d_Add_RateATid(PADAPTER pAdapter, u32 bitmap, u8 arg);
++#ifdef CONFIG_P2P
++void rtl8192d_set_p2p_ps_offload_cmd(_adapter* padapter, u8 p2p_ps_state);
++#endif //CONFIG_P2P
++
++#ifdef CONFIG_TSF_RESET_OFFLOAD
++int reset_tsf(PADAPTER Adapter, u8 reset_port );
++#endif // CONFIG_TSF_RESET_OFFLOAD
++
++#ifdef CONFIG_WOWLAN
++typedef struct _SETWOWLAN_PARM{
++ u8 mode;
++ u8 gpio_index;
++ u8 gpio_duration;
++ u8 second_mode;
++ u8 reserve;
++}SETWOWLAN_PARM, *PSETWOWLAN_PARM;
++
++#define FW_WOWLAN_FUN_EN BIT(0)
++#define FW_WOWLAN_PATTERN_MATCH BIT(1)
++#define FW_WOWLAN_MAGIC_PKT BIT(2)
++#define FW_WOWLAN_UNICAST BIT(3)
++#define FW_WOWLAN_ALL_PKT_DROP BIT(4)
++#define FW_WOWLAN_GPIO_ACTIVE BIT(5)
++#define FW_WOWLAN_REKEY_WAKEUP BIT(6)
++#define FW_WOWLAN_DEAUTH_WAKEUP BIT(7)
++
++#define FW_WOWLAN_GPIO_WAKEUP_EN BIT(0)
++#define FW_FW_PARSE_MAGIC_PKT BIT(1)
++
++void rtl8192d_set_wowlan_cmd(_adapter* padapter);
++void SetFwRelatedForWoWLAN8192DU(_adapter* padapter,u8 bHostIsGoingtoSleep);
++#endif // CONFIG_WOWLAN
++
++#endif // __RTL8192D_CMD_H_
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtl8192d_dm.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtl8192d_dm.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtl8192d_dm.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtl8192d_dm.h 2015-07-28 01:20:58.321597318 +0200
+@@ -0,0 +1,420 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef __RTL8192D_DM_H__
++#define __RTL8192D_DM_H__
++//============================================================
++// Description:
++//
++// This file is for 92CE/92CU dynamic mechanism only
++//
++//
++//============================================================
++//============================================================
++// Global var
++//============================================================
++
++extern u32 EDCAParam[maxAP][3] ;
++
++//============================================================
++// structure and define
++//============================================================
++
++typedef struct _FALSE_ALARM_STATISTICS{
++ u32 Cnt_Parity_Fail;
++ u32 Cnt_Rate_Illegal;
++ u32 Cnt_Crc8_fail;
++ u32 Cnt_Mcs_fail;
++ u32 Cnt_Ofdm_fail;
++ u32 Cnt_Cck_fail;
++ u32 Cnt_all;
++ u32 Cnt_Fast_Fsync;
++ u32 Cnt_SB_Search_fail;
++}FALSE_ALARM_STATISTICS, *PFALSE_ALARM_STATISTICS;
++
++typedef struct _Dynamic_Power_Saving_
++{
++ u8 PreCCAState;
++ u8 CurCCAState;
++
++ u8 PreRFState;
++ u8 CurRFState;
++
++ //int Rssi_val_min;
++
++}PS_T,*pPS_T;
++
++typedef struct _Dynamic_Initial_Gain_Threshold_
++{
++ u8 Dig_Enable_Flag;
++ u8 Dig_Ext_Port_Stage;
++
++ int RssiLowThresh;
++ int RssiHighThresh;
++
++ u32 FALowThresh;
++ u32 FAHighThresh;
++
++ u8 CurSTAConnectState;
++ u8 PreSTAConnectState;
++ u8 CurMultiSTAConnectState;
++
++ u8 PreIGValue;
++ u8 CurIGValue;
++ u8 BackupIGValue;
++
++ char BackoffVal;
++ char BackoffVal_range_max;
++ char BackoffVal_range_min;
++ u8 rx_gain_range_max;
++ u8 rx_gain_range_min;
++ u8 Rssi_val_min;
++
++ u8 PreCCKPDState;
++ u8 CurCCKPDState;
++
++ u8 LargeFAHit;
++ u8 ForbiddenIGI;
++ u32 Recover_cnt;
++ u8 rx_gain_range_min_nolink;
++}DIG_T,*pDIG_T;
++
++typedef enum tag_Dynamic_Init_Gain_Operation_Type_Definition
++{
++ DIG_TYPE_THRESH_HIGH = 0,
++ DIG_TYPE_THRESH_LOW = 1,
++ DIG_TYPE_BACKOFF = 2,
++ DIG_TYPE_RX_GAIN_MIN = 3,
++ DIG_TYPE_RX_GAIN_MAX = 4,
++ DIG_TYPE_ENABLE = 5,
++ DIG_TYPE_DISABLE = 6,
++ DIG_OP_TYPE_MAX
++}DM_DIG_OP_E;
++
++typedef enum tag_CCK_Packet_Detection_Threshold_Type_Definition
++{
++ CCK_PD_STAGE_LowRssi = 0,
++ CCK_PD_STAGE_HighRssi = 1,
++ CCK_PD_STAGE_MAX = 3,
++}DM_CCK_PDTH_E;
++
++typedef enum tag_1R_CCA_Type_Definition
++{
++ CCA_MIN = 0,
++ CCA_1R =1,
++ CCA_2R = 2,
++ CCA_MAX = 3,
++}DM_1R_CCA_E;
++
++typedef enum tag_RF_Type_Definition
++{
++ RF_Save =0,
++ RF_Normal = 1,
++ RF_MAX = 2,
++}DM_RF_E;
++
++typedef enum tag_DIG_EXT_PORT_ALGO_Definition
++{
++ DIG_EXT_PORT_STAGE_0 = 0,
++ DIG_EXT_PORT_STAGE_1 = 1,
++ DIG_EXT_PORT_STAGE_2 = 2,
++ DIG_EXT_PORT_STAGE_3 = 3,
++ DIG_EXT_PORT_STAGE_MAX = 4,
++}DM_DIG_EXT_PORT_ALG_E;
++
++
++typedef enum tag_DIG_Connect_Definition
++{
++ DIG_STA_DISCONNECT = 0,
++ DIG_STA_CONNECT = 1,
++ DIG_STA_BEFORE_CONNECT = 2,
++ DIG_MultiSTA_DISCONNECT = 3,
++ DIG_MultiSTA_CONNECT = 4,
++ DIG_CONNECT_MAX
++}DM_DIG_CONNECT_E;
++
++
++#define DM_DIG_THRESH_HIGH 40
++#define DM_DIG_THRESH_LOW 35
++
++#define DM_FALSEALARM_THRESH_LOW 400
++#define DM_FALSEALARM_THRESH_HIGH 1000
++
++#define DM_DIG_MAX 0x3e
++#define DM_DIG_MIN 0x1e //0x22//0x1c
++
++#define DM_DIG_FA_UPPER 0x32
++#define DM_DIG_FA_LOWER 0x20
++
++//vivi 92c&92d has different definition, 20110504
++//this is for 92c
++#define DM_DIG_FA_TH0 0x200//0x20
++#define DM_DIG_FA_TH1 0x300//0x100
++#define DM_DIG_FA_TH2 0x400//0x200
++//this is for 92d
++#define DM_DIG_FA_TH0_92D 0x100
++#define DM_DIG_FA_TH1_92D 0x150
++#define DM_DIG_FA_TH2_92D 0x250
++
++#define DM_DIG_BACKOFF_MAX 12
++#define DM_DIG_BACKOFF_MIN (-4)
++#define DM_DIG_BACKOFF_DEFAULT 10
++
++#define RxPathSelection_SS_TH_low 30
++#define RxPathSelection_diff_TH 18
++
++#define DM_RATR_STA_INIT 0
++#define DM_RATR_STA_HIGH 1
++#define DM_RATR_STA_MIDDLE 2
++#define DM_RATR_STA_LOW 3
++
++#define CTSToSelfTHVal 30
++#define RegC38_TH 20
++
++#define WAIotTHVal 25
++
++//Dynamic Tx Power Control Threshold
++#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
++#define TX_POWER_NEAR_FIELD_THRESH_LVL1 67
++
++#define TxHighPwrLevel_Normal 0
++#define TxHighPwrLevel_Level1 1
++#define TxHighPwrLevel_Level2 2
++#define TxHighPwrLevel_BT1 3
++#define TxHighPwrLevel_BT2 4
++#define TxHighPwrLevel_15 5
++#define TxHighPwrLevel_35 6
++#define TxHighPwrLevel_50 7
++#define TxHighPwrLevel_70 8
++#define TxHighPwrLevel_100 9
++
++#define DM_Type_ByFW 0
++#define DM_Type_ByDriver 1
++
++typedef struct _RATE_ADAPTIVE
++{
++ u8 RateAdaptiveDisabled;
++ u8 RATRState;
++ u16 reserve;
++
++ u32 HighRSSIThreshForRA;
++ u32 High2LowRSSIThreshForRA;
++ u8 Low2HighRSSIThreshForRA40M;
++ u32 LowRSSIThreshForRA40M;
++ u8 Low2HighRSSIThreshForRA20M;
++ u32 LowRSSIThreshForRA20M;
++ u32 UpperRSSIThresholdRATR;
++ u32 MiddleRSSIThresholdRATR;
++ u32 LowRSSIThresholdRATR;
++ u32 LowRSSIThresholdRATR40M;
++ u32 LowRSSIThresholdRATR20M;
++ u8 PingRSSIEnable; //cosa add for Netcore long range ping issue
++ u32 PingRSSIRATR; //cosa add for Netcore long range ping issue
++ u32 PingRSSIThreshForRA;//cosa add for Netcore long range ping issue
++ u32 LastRATR;
++ u8 PreRATRState;
++
++} RATE_ADAPTIVE, *PRATE_ADAPTIVE;
++
++typedef enum tag_SW_Antenna_Switch_Definition
++{
++ Antenna_B = 1,
++ Antenna_A = 2,
++ Antenna_MAX = 3,
++}DM_SWAS_E;
++
++// 20100514 Joseph: Add definition for antenna switching test after link.
++// This indicates two different the steps.
++// In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air.
++// In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK
++// with original RSSI to determine if it is necessary to switch antenna.
++#define SWAW_STEP_PEAK 0
++#define SWAW_STEP_DETERMINE 1
++
++#define TP_MODE 0
++#define RSSI_MODE 1
++#define TRAFFIC_LOW 0
++#define TRAFFIC_HIGH 1
++
++//=============================
++//Neil Chen---2011--06--15--
++//==============================
++//3 PathDiv
++typedef struct _SW_Antenna_Switch_
++{
++ u8 try_flag;
++ s32 PreRSSI;
++ u8 CurAntenna;
++ u8 PreAntenna;
++ u8 RSSI_Trying;
++ u8 TestMode;
++ u8 bTriggerAntennaSwitch;
++ u8 SelectAntennaMap;
++
++ // Before link Antenna Switch check
++ u8 SWAS_NoLink_State;
++ u32 SWAS_NoLink_BK_Reg860;
++}SWAT_T, *pSWAT_T;
++//========================================
++
++struct dm_priv
++{
++ u8 DM_Type;
++ u8 DMFlag, DMFlag_tmp;
++
++ //for DIG
++ u8 bDMInitialGainEnable;
++ //u8 binitialized; // for dm_initial_gain_Multi_STA use.
++ DIG_T DM_DigTable;
++
++ PS_T DM_PSTable;
++
++ FALSE_ALARM_STATISTICS FalseAlmCnt;
++
++ //for rate adaptive, in fact, 88c/92c fw will handle this
++ u8 bUseRAMask;
++ RATE_ADAPTIVE RateAdaptive;
++
++ //* Upper and Lower Signal threshold for Rate Adaptive*/
++ int UndecoratedSmoothedPWDB;
++ int EntryMinUndecoratedSmoothedPWDB;
++ int EntryMaxUndecoratedSmoothedPWDB;
++ int MinUndecoratedPWDBForDM;
++ int LastMinUndecoratedPWDBForDM;
++#ifdef CONFIG_DUALMAC_CONCURRENT
++ int RssiValMinForAnotherMacOfDMSP;
++ u32 CurDigValueForAnotherMacOfDMSP;
++ BOOLEAN bWriteDigForAnotherMacOfDMSP;
++ BOOLEAN bChangeCCKPDStateForAnotherMacOfDMSP;
++ u8 CurCCKPDStateForAnotherMacOfDMSP;
++ BOOLEAN bChangeTxHighPowerLvlForAnotherMacOfDMSP;
++ u8 CurTxHighLvlForAnotherMacOfDMSP;
++#endif
++
++ //for High Power
++ u8 bDynamicTxPowerEnable;
++ u8 LastDTPLvl;
++ u8 DynamicTxHighPowerLvl;//Add by Jacken Tx Power Control for Near/Far Range 2008/03/06
++
++ //for tx power tracking
++ u8 bTXPowerTracking;
++ u8 TXPowercount;
++ u8 bTXPowerTrackingInit;
++ u8 TxPowerTrackControl; //for mp mode, turn off txpwrtracking as default
++ u8 TM_Trigger;
++
++ u8 ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1
++ u8 ThermalValue;
++ u8 ThermalValue_LCK;
++ u8 ThermalValue_IQK;
++ u8 ThermalValue_AVG[AVG_THERMAL_NUM];
++ u8 ThermalValue_AVG_index;
++ u8 ThermalValue_RxGain;
++ u8 ThermalValue_Crystal;
++ u8 Delta_IQK;
++ u8 Delta_LCK;
++ u8 bRfPiEnable;
++ u8 bReloadtxpowerindex;
++ u8 bDoneTxpower;
++
++ //for APK
++ u32 APKoutput[2][2]; //path A/B; output1_1a/output1_2a
++ u8 bAPKdone;
++ u8 bAPKThermalMeterIgnore;
++ BOOLEAN bDPKdone[2];
++ BOOLEAN bDPKstore;
++ BOOLEAN bDPKworking;
++ u8 OFDM_min_index_internalPA_DPK[2];
++ u8 TxPowerLevelDPK[2];
++
++ u32 RegA24;
++
++ //for IQK
++ u32 Reg874;
++ u32 RegC08;
++ u32 Reg88C;
++ u8 Reg522;
++ u8 Reg550;
++ u8 Reg551;
++ u32 Reg870;
++ u32 ADDA_backup[IQK_ADDA_REG_NUM];
++ u32 IQK_MAC_backup[IQK_MAC_REG_NUM];
++ u32 IQK_BB_backup[IQK_BB_REG_NUM];
++
++ u8 bCCKinCH14;
++
++ char CCK_index;
++ //u8 Record_CCK_20Mindex;
++ //u8 Record_CCK_40Mindex;
++ char OFDM_index[2];
++
++ SWAT_T DM_SWAT_Table;
++
++ //for TxPwrTracking
++ int RegE94;
++ int RegE9C;
++ int RegEB4;
++ int RegEBC;
++#if MP_DRIVER == 1
++ u8 RegC04_MP;
++ u32 RegD04_MP;
++#endif
++ u32 TXPowerTrackingCallbackCnt; //cosa add for debug
++
++ u32 prv_traffic_idx; // edca turbo
++
++ u32 RegRF3C[2]; //pathA / pathB
++
++ // Add for Reading Initial Data Rate SEL Register 0x484 during watchdog. Using for fill tx desc. 2011.3.21 by Thomas
++ u8 INIDATA_RATE[32];
++
++#ifdef CONFIG_DM_ADAPTIVITY
++ /* Ported from ODM, for ESTI Adaptivity test */
++ s8 TH_L2H_ini;
++ s8 TH_EDCCA_HL_diff;
++ s8 IGI_Base;
++ u8 IGI_target;
++ bool ForceEDCCA;
++ u8 AdapEn_RSSI;
++ s8 Force_TH_H;
++ s8 Force_TH_L;
++ u8 IGI_LowerBound;
++
++ bool bPreEdccaEnable;
++#endif
++};
++
++
++/*------------------------Export global variable----------------------------*/
++/*------------------------Export global variable----------------------------*/
++/*------------------------Export Marco Definition---------------------------*/
++//#define DM_MultiSTA_InitGainChangeNotify(Event) {DM_DigTable.CurMultiSTAConnectState = Event;}
++
++
++//============================================================
++// function prototype
++//============================================================
++void rtl8192d_init_dm_priv(IN PADAPTER Adapter);
++void rtl8192d_deinit_dm_priv(IN PADAPTER Adapter);
++void rtl8192d_InitHalDm(IN PADAPTER Adapter);
++void rtl8192d_HalDmWatchDog(IN PADAPTER Adapter);
++
++VOID rtl8192d_dm_CheckTXPowerTracking(IN PADAPTER Adapter);
++
++#endif //__HAL8190PCIDM_H__
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtl8192d_hal.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtl8192d_hal.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtl8192d_hal.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtl8192d_hal.h 2015-07-28 01:20:58.321597318 +0200
+@@ -0,0 +1,1125 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef __RTL8192D_HAL_H__
++#define __RTL8192D_HAL_H__
++
++#include "hal_com.h"
++#include "rtl8192d_spec.h"
++#include "Hal8192DPhyReg.h"
++#include "Hal8192DPhyCfg.h"
++#include "rtl8192d_rf.h"
++#include "rtl8192d_dm.h"
++#include "rtl8192d_recv.h"
++#include "rtl8192d_xmit.h"
++#include "rtl8192d_cmd.h"
++
++/*---------------------------Define Local Constant---------------------------*/
++/* Channel switch:The size of command tables for switch channel*/
++#define MAX_PRECMD_CNT 16
++#define MAX_RFDEPENDCMD_CNT 16
++#define MAX_POSTCMD_CNT 16
++
++#define MAX_DOZE_WAITING_TIMES_9x 64
++
++#define MAX_RF_IMR_INDEX 12
++#define MAX_RF_IMR_INDEX_NORMAL 13
++#define RF_REG_NUM_for_C_CUT_5G 6
++#define RF_REG_NUM_for_C_CUT_5G_internalPA 7
++#define RF_REG_NUM_for_C_CUT_2G 5
++#define RF_CHNL_NUM_5G 19
++#define RF_CHNL_NUM_5G_40M 17
++#define TARGET_CHNL_NUM_5G 221
++#define TARGET_CHNL_NUM_2G 14
++#define TARGET_CHNL_NUM_2G_5G 59
++#define CV_CURVE_CNT 64
++
++//static u32 RF_REG_FOR_5G_SWCHNL[MAX_RF_IMR_INDEX]={0,0x2f,0x30,0x31,0x32,0x33,0x34,0x35,0x36,0x38,0x39,0x0};
++static u32 RF_REG_FOR_5G_SWCHNL_NORMAL[MAX_RF_IMR_INDEX_NORMAL]={0,0x2f,0x30,0x31,0x32,0x33,0x34,0x35,0x36,0x37,0x38,0x39,0x0};
++
++static u8 RF_REG_for_C_CUT_5G[RF_REG_NUM_for_C_CUT_5G] =
++ {RF_SYN_G1, RF_SYN_G2, RF_SYN_G3, RF_SYN_G4, RF_SYN_G5, RF_SYN_G6};
++
++static u8 RF_REG_for_C_CUT_5G_internalPA[RF_REG_NUM_for_C_CUT_5G_internalPA] =
++ {0x0B, 0x48, 0x49, 0x4B, 0x03, 0x04, 0x0E};
++static u8 RF_REG_for_C_CUT_2G[RF_REG_NUM_for_C_CUT_2G] =
++ {RF_SYN_G1, RF_SYN_G2, RF_SYN_G3, RF_SYN_G7, RF_SYN_G8};
++
++#if DBG
++static u32 RF_REG_MASK_for_C_CUT_2G[RF_REG_NUM_for_C_CUT_2G] =
++ {BIT19|BIT18|BIT17|BIT14|BIT1, BIT10|BIT9,
++ BIT18|BIT17|BIT16|BIT1, BIT2|BIT1,
++ BIT15|BIT14|BIT13|BIT12|BIT11};
++#endif //amy, temp remove
++static u8 RF_CHNL_5G[RF_CHNL_NUM_5G] =
++ {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140};
++static u8 RF_CHNL_5G_40M[RF_CHNL_NUM_5G_40M] =
++ {38,42,46,50,54,58,62,102,106,110,114,118,122,126,130,134,138};
++
++static u32 RF_REG_Param_for_C_CUT_5G[5][RF_REG_NUM_for_C_CUT_5G] = {
++ {0xE43BE, 0xFC638, 0x77C0A, 0xDE471, 0xd7110, 0x8EB04},
++ {0xE43BE, 0xFC078, 0xF7C1A, 0xE0C71, 0xD7550, 0xAEB04},
++ {0xE43BF, 0xFF038, 0xF7C0A, 0xDE471, 0xE5550, 0xAEB04},
++ {0xE43BF, 0xFF079, 0xF7C1A, 0xDE471, 0xE5550, 0xAEB04},
++ {0xE43BF, 0xFF038, 0xF7C1A, 0xDE471, 0xd7550, 0xAEB04}};
++
++static u32 RF_REG_Param_for_C_CUT_2G[3][RF_REG_NUM_for_C_CUT_2G] = {
++ {0x643BC, 0xFC038, 0x77C1A, 0x41289, 0x01840},
++ {0x643BC, 0xFC038, 0x07C1A, 0x41289, 0x01840},
++ {0x243BC, 0xFC438, 0x07C1A, 0x4128B, 0x0FC41}};
++
++#if SWLCK == 1
++static u32 RF_REG_SYN_G4_for_C_CUT_2G = 0xD1C31&0x7FF;
++#endif
++
++static u32 RF_REG_Param_for_C_CUT_5G_internalPA[3][RF_REG_NUM_for_C_CUT_5G_internalPA] = {
++ {0x01a00, 0x40443, 0x00eb5, 0x89bec, 0x94a12, 0x94a12, 0x94a12},
++ {0x01800, 0xc0443, 0x00730, 0x896ee, 0x94a52, 0x94a52, 0x94a52},
++ {0x01800, 0xc0443, 0x00730, 0x896ee, 0x94a12, 0x94a12, 0x94a12}};
++
++
++
++//[mode][patha+b][reg]
++static u32 RF_IMR_Param_Normal[1][3][MAX_RF_IMR_INDEX_NORMAL]={{
++ {0x70000,0x00ff0,0x4400f,0x00ff0,0x0,0x0,0x0,0x0,0x0,0x64888,0xe266c,0x00090,0x22fff},// channel 1-14.
++ {0x70000,0x22880,0x4470f,0x55880,0x00070, 0x88000, 0x0,0x88080,0x70000,0x64a82,0xe466c,0x00090,0x32c9a}, //path 36-64
++ {0x70000,0x44880,0x4477f,0x77880,0x00070, 0x88000, 0x0,0x880b0,0x0,0x64b82,0xe466c,0x00090,0x32c9a} //100 -165
++}
++};
++
++//static u32 CurveIndex_5G[TARGET_CHNL_NUM_5G]={0};
++//static u32 CurveIndex_2G[TARGET_CHNL_NUM_2G]={0};
++static u32 CurveIndex[TARGET_CHNL_NUM_2G_5G]={0};
++
++static u32 TargetChnl_5G[TARGET_CHNL_NUM_5G] = {
++25141, 25116, 25091, 25066, 25041,
++25016, 24991, 24966, 24941, 24917,
++24892, 24867, 24843, 24818, 24794,
++24770, 24765, 24721, 24697, 24672,
++24648, 24624, 24600, 24576, 24552,
++24528, 24504, 24480, 24457, 24433,
++24409, 24385, 24362, 24338, 24315,
++24291, 24268, 24245, 24221, 24198,
++24175, 24151, 24128, 24105, 24082,
++24059, 24036, 24013, 23990, 23967,
++23945, 23922, 23899, 23876, 23854,
++23831, 23809, 23786, 23764, 23741,
++23719, 23697, 23674, 23652, 23630,
++23608, 23586, 23564, 23541, 23519,
++23498, 23476, 23454, 23432, 23410,
++23388, 23367, 23345, 23323, 23302,
++23280, 23259, 23237, 23216, 23194,
++23173, 23152, 23130, 23109, 23088,
++23067, 23046, 23025, 23003, 22982,
++22962, 22941, 22920, 22899, 22878,
++22857, 22837, 22816, 22795, 22775,
++22754, 22733, 22713, 22692, 22672,
++22652, 22631, 22611, 22591, 22570,
++22550, 22530, 22510, 22490, 22469,
++22449, 22429, 22409, 22390, 22370,
++22350, 22336, 22310, 22290, 22271,
++22251, 22231, 22212, 22192, 22173,
++22153, 22134, 22114, 22095, 22075,
++22056, 22037, 22017, 21998, 21979,
++21960, 21941, 21921, 21902, 21883,
++21864, 21845, 21826, 21807, 21789,
++21770, 21751, 21732, 21713, 21695,
++21676, 21657, 21639, 21620, 21602,
++21583, 21565, 21546, 21528, 21509,
++21491, 21473, 21454, 21436, 21418,
++21400, 21381, 21363, 21345, 21327,
++21309, 21291, 21273, 21255, 21237,
++21219, 21201, 21183, 21166, 21148,
++21130, 21112, 21095, 21077, 21059,
++21042, 21024, 21007, 20989, 20972,
++25679, 25653, 25627, 25601, 25575,
++25549, 25523, 25497, 25471, 25446,
++25420, 25394, 25369, 25343, 25318,
++25292, 25267, 25242, 25216, 25191,
++25166 };
++
++static u32 TargetChnl_2G[TARGET_CHNL_NUM_2G] = { // channel 1~14
++26084, 26030, 25976, 25923, 25869, 25816, 25764,
++25711, 25658, 25606, 25554, 25502, 25451, 25328
++};
++
++
++#ifdef CONFIG_PCI_HCI
++ #include <pci_ops.h>
++ #include "Hal8192DEHWImg.h"
++
++ #define RTL819X_DEFAULT_RF_TYPE RF_2T2R
++
++//---------------------------------------------------------------------
++// RTL8192DE From file
++//---------------------------------------------------------------------
++ #define RTL8192D_FW_IMG "rtl8192DE\\rtl8192dfw.bin"
++
++ #define RTL8192D_PHY_REG "rtl8192DE\\PHY_REG.txt"
++ #define RTL8192D_PHY_REG_PG "rtl8192DE\\PHY_REG_PG.txt"
++ #define RTL8192D_PHY_REG_MP "rtl8192DE\\PHY_REG_MP.txt"
++
++ #define RTL8192D_AGC_TAB "rtl8192DE\\AGC_TAB.txt"
++ #define RTL8192D_AGC_TAB_2G "rtl8192DE\\AGC_TAB_2G.txt"
++ #define RTL8192D_AGC_TAB_5G "rtl8192DE\\AGC_TAB_5G.txt"
++ #define RTL8192D_PHY_RADIO_A "rtl8192DE\\radio_a.txt"
++ #define RTL8192D_PHY_RADIO_B "rtl8192DE\\radio_b.txt"
++ #define RTL8192D_PHY_RADIO_A_intPA "rtl8192DE\\radio_a_intPA.txt"
++ #define RTL8192D_PHY_RADIO_B_intPA "rtl8192DE\\radio_b_intPA.txt"
++ #define RTL8192D_PHY_MACREG "rtl8192DE\\MAC_REG.txt"
++
++//---------------------------------------------------------------------
++// RTL8192DE From header
++//---------------------------------------------------------------------
++
++ // Fw Array
++ #define Rtl8192D_FwImageArray Rtl8192DEFwImgArray
++
++ // MAC/BB/PHY Array
++ #define Rtl8192D_MAC_Array Rtl8192DEMAC_2T_Array
++ #define Rtl8192D_AGCTAB_Array Rtl8192DEAGCTAB_Array
++ #define Rtl8192D_AGCTAB_5GArray Rtl8192DEAGCTAB_5GArray
++ #define Rtl8192D_AGCTAB_2GArray Rtl8192DEAGCTAB_2GArray
++ #define Rtl8192D_AGCTAB_2TArray Rtl8192DEAGCTAB_2TArray
++ #define Rtl8192D_AGCTAB_1TArray Rtl8192DEAGCTAB_1TArray
++ #define Rtl8192D_PHY_REG_2TArray Rtl8192DEPHY_REG_2TArray
++ #define Rtl8192D_PHY_REG_1TArray Rtl8192DEPHY_REG_1TArray
++ #define Rtl8192D_PHY_REG_Array_PG Rtl8192DEPHY_REG_Array_PG
++ #define Rtl8192D_PHY_REG_Array_MP Rtl8192DEPHY_REG_Array_MP
++ #define Rtl8192D_RadioA_2TArray Rtl8192DERadioA_2TArray
++ #define Rtl8192D_RadioA_1TArray Rtl8192DERadioA_1TArray
++ #define Rtl8192D_RadioB_2TArray Rtl8192DERadioB_2TArray
++ #define Rtl8192D_RadioB_1TArray Rtl8192DERadioB_1TArray
++ #define Rtl8192D_RadioA_2T_intPAArray Rtl8192DERadioA_2T_intPAArray
++ #define Rtl8192D_RadioB_2T_intPAArray Rtl8192DERadioB_2T_intPAArray
++
++ // Array length
++ #define Rtl8192D_FwImageArrayLength Rtl8192DEImgArrayLength
++ #define Rtl8192D_MAC_ArrayLength Rtl8192DEMAC_2T_ArrayLength
++ #define Rtl8192D_AGCTAB_5GArrayLength Rtl8192DEAGCTAB_5GArrayLength
++ #define Rtl8192D_AGCTAB_2GArrayLength Rtl8192DEAGCTAB_2GArrayLength
++ #define Rtl8192D_AGCTAB_2TArrayLength Rtl8192DEAGCTAB_2TArrayLength
++ #define Rtl8192D_AGCTAB_1TArrayLength Rtl8192DEAGCTAB_1TArrayLength
++ #define Rtl8192D_AGCTAB_ArrayLength Rtl8192DEAGCTAB_ArrayLength
++ #define Rtl8192D_PHY_REG_2TArrayLength Rtl8192DEPHY_REG_2TArrayLength
++ #define Rtl8192D_PHY_REG_1TArrayLength Rtl8192DEPHY_REG_1TArrayLength
++ #define Rtl8192D_PHY_REG_Array_PGLength Rtl8192DEPHY_REG_Array_PGLength
++ #define Rtl8192D_PHY_REG_Array_MPLength Rtl8192DEPHY_REG_Array_MPLength
++ #define Rtl8192D_RadioA_2TArrayLength Rtl8192DERadioA_2TArrayLength
++ #define Rtl8192D_RadioB_2TArrayLength Rtl8192DERadioB_2TArrayLength
++ #define Rtl8192D_RadioA_2T_intPAArrayLength Rtl8192DERadioA_2T_intPAArrayLength
++ #define Rtl8192D_RadioB_2T_intPAArrayLength Rtl8192DERadioB_2T_intPAArrayLength
++
++#elif defined(CONFIG_USB_HCI)
++
++ #include "Hal8192DUHWImg.h"
++#ifdef CONFIG_WOWLAN
++ #include "Hal8192DUHWImg_wowlan.h"
++#endif //CONFIG_WOWLAN
++ #define RTL819X_DEFAULT_RF_TYPE RF_1T2R
++
++//---------------------------------------------------------------------
++// RTL8192DU From file
++//---------------------------------------------------------------------
++ #define RTL8192D_FW_IMG "rtl8192DU\\rtl8192dfw.bin"
++
++ #define RTL8192D_PHY_REG "rtl8192DU\\PHY_REG.txt"
++ #define RTL8192D_PHY_REG_PG "rtl8192DU\\PHY_REG_PG.txt"
++ #define RTL8192D_PHY_REG_MP "rtl8192DU\\PHY_REG_MP.txt"
++
++ #define RTL8192D_AGC_TAB "rtl8192DU\\AGC_TAB.txt"
++ #define RTL8192D_AGC_TAB_2G "rtl8192DU\\AGC_TAB_2G.txt"
++ #define RTL8192D_AGC_TAB_5G "rtl8192DU\\AGC_TAB_5G.txt"
++ #define RTL8192D_PHY_RADIO_A "rtl8192DU\\radio_a.txt"
++ #define RTL8192D_PHY_RADIO_B "rtl8192DU\\radio_b.txt"
++ #define RTL8192D_PHY_RADIO_A_intPA "rtl8192DU\\radio_a_intPA.txt"
++ #define RTL8192D_PHY_RADIO_B_intPA "rtl8192DU\\radio_b_intPA.txt"
++ #define RTL8192D_PHY_MACREG "rtl8192DU\\MAC_REG.txt"
++
++//---------------------------------------------------------------------
++// RTL8192DU From header
++//---------------------------------------------------------------------
++
++ // Fw Array
++ #define Rtl8192D_FwImageArray Rtl8192DUFwImgArray
++#ifdef CONFIG_WOWLAN
++ #define Rtl8192D_FwWWImageArray Rtl8192DUFwWWImgArray
++#endif //CONFIG_WOWLAN
++ // MAC/BB/PHY Array
++ #define Rtl8192D_MAC_Array Rtl8192DUMAC_2T_Array
++ #define Rtl8192D_AGCTAB_Array Rtl8192DUAGCTAB_Array
++ #define Rtl8192D_AGCTAB_5GArray Rtl8192DUAGCTAB_5GArray
++ #define Rtl8192D_AGCTAB_2GArray Rtl8192DUAGCTAB_2GArray
++ #define Rtl8192D_AGCTAB_2TArray Rtl8192DUAGCTAB_2TArray
++ #define Rtl8192D_AGCTAB_1TArray Rtl8192DUAGCTAB_1TArray
++ #define Rtl8192D_PHY_REG_2TArray Rtl8192DUPHY_REG_2TArray
++ #define Rtl8192D_PHY_REG_1TArray Rtl8192DUPHY_REG_1TArray
++ #define Rtl8192D_PHY_REG_Array_PG Rtl8192DUPHY_REG_Array_PG
++ #define Rtl8192D_PHY_REG_Array_MP Rtl8192DUPHY_REG_Array_MP
++ #define Rtl8192D_RadioA_2TArray Rtl8192DURadioA_2TArray
++ #define Rtl8192D_RadioA_1TArray Rtl8192DURadioA_1TArray
++ #define Rtl8192D_RadioB_2TArray Rtl8192DURadioB_2TArray
++ #define Rtl8192D_RadioB_1TArray Rtl8192DURadioB_1TArray
++ #define Rtl8192D_RadioA_2T_intPAArray Rtl8192DURadioA_2T_intPAArray
++ #define Rtl8192D_RadioB_2T_intPAArray Rtl8192DURadioB_2T_intPAArray
++
++ // Array length
++ #define Rtl8192D_FwImageArrayLength Rtl8192DUImgArrayLength
++ #define Rtl8192D_MAC_ArrayLength Rtl8192DUMAC_2T_ArrayLength
++ #define Rtl8192D_AGCTAB_5GArrayLength Rtl8192DUAGCTAB_5GArrayLength
++ #define Rtl8192D_AGCTAB_2GArrayLength Rtl8192DUAGCTAB_2GArrayLength
++ #define Rtl8192D_AGCTAB_2TArrayLength Rtl8192DUAGCTAB_2TArrayLength
++ #define Rtl8192D_AGCTAB_1TArrayLength Rtl8192DUAGCTAB_1TArrayLength
++ #define Rtl8192D_AGCTAB_ArrayLength Rtl8192DUAGCTAB_ArrayLength
++ #define Rtl8192D_PHY_REG_2TArrayLength Rtl8192DUPHY_REG_2TArrayLength
++ #define Rtl8192D_PHY_REG_1TArrayLength Rtl8192DUPHY_REG_1TArrayLength
++ #define Rtl8192D_PHY_REG_Array_PGLength Rtl8192DUPHY_REG_Array_PGLength
++ #define Rtl8192D_PHY_REG_Array_MPLength Rtl8192DUPHY_REG_Array_MPLength
++ #define Rtl8192D_RadioA_2TArrayLength Rtl8192DURadioA_2TArrayLength
++ #define Rtl8192D_RadioB_2TArrayLength Rtl8192DURadioB_2TArrayLength
++ #define Rtl8192D_RadioA_2T_intPAArrayLength Rtl8192DURadioA_2T_intPAArrayLength
++ #define Rtl8192D_RadioB_2T_intPAArrayLength Rtl8192DURadioB_2T_intPAArrayLength
++
++ // The file name "_2T" is for 92CU, "_1T" is for 88CU. Modified by tynli. 2009.11.24.
++/* #define Rtl819XFwImageArray Rtl8192DUFwImgArray
++ #define Rtl819XMAC_Array Rtl8192DUMAC_2TArray
++ #define Rtl819XAGCTAB_Array Rtl8192DUAGCTAB_Array
++ #define Rtl819XAGCTAB_5GArray Rtl8192DUAGCTAB_5GArray
++ #define Rtl819XAGCTAB_2GArray Rtl8192DUAGCTAB_2GArray
++ #define Rtl819XPHY_REG_2TArray Rtl8192DUPHY_REG_2TArray
++ #define Rtl819XPHY_REG_1TArray Rtl8192DUPHY_REG_1TArray
++ #define Rtl819XRadioA_2TArray Rtl8192DURadioA_2TArray
++ #define Rtl819XRadioA_1TArray Rtl8192DURadioA_1TArray
++ #define Rtl819XRadioA_2T_intPAArray Rtl8192DURadioA_2T_intPAArray
++ #define Rtl819XRadioB_2TArray Rtl8192DURadioB_2TArray
++ #define Rtl819XRadioB_1TArray Rtl8192DURadioB_1TArray
++ #define Rtl819XRadioB_2T_intPAArray Rtl8192DURadioB_2T_intPAArray
++ #define Rtl819XPHY_REG_Array_PG Rtl8192DUPHY_REG_Array_PG
++ #define Rtl819XPHY_REG_Array_MP Rtl8192DUPHY_REG_Array_MP
++
++ #define Rtl819XAGCTAB_2TArray Rtl8192DUAGCTAB_2TArray
++ #define Rtl819XAGCTAB_1TArray Rtl8192DUAGCTAB_1TArray*/
++
++#endif
++
++#define DRVINFO_SZ 4 // unit is 8bytes
++#define PageNum_128(_Len) (u32)(((_Len)>>7) + ((_Len)&0x7F ? 1:0))
++
++//
++// Check if FW header exists. We do not consider the lower 4 bits in this case.
++// By tynli. 2009.12.04.
++//
++#define IS_FW_HEADER_EXIST(_pFwHdr) ((le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x92C0 ||\
++ (le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x88C0 ||\
++ (le16_to_cpu(_pFwHdr->Signature)&0xFFFF) == 0x92D0 ||\
++ (le16_to_cpu(_pFwHdr->Signature)&0xFFFF) == 0x92D1 ||\
++ (le16_to_cpu(_pFwHdr->Signature)&0xFFFF) == 0x92D2 ||\
++ (le16_to_cpu(_pFwHdr->Signature)&0xFFFF) == 0x92D3 )
++
++#define FW_8192D_SIZE 0x8020 // Max FW len = 32k + 32(FW header length).
++#define FW_8192D_START_ADDRESS 0x1000
++#define FW_8192D_END_ADDRESS 0x1FFF
++
++#define MAX_PAGE_SIZE 4096 // @ page : 4k bytes
++
++typedef enum _FIRMWARE_SOURCE{
++ FW_SOURCE_IMG_FILE = 0,
++ FW_SOURCE_HEADER_FILE = 1, //from header file
++}FIRMWARE_SOURCE, *PFIRMWARE_SOURCE;
++
++typedef struct _RT_FIRMWARE{
++ FIRMWARE_SOURCE eFWSource;
++ u8* szFwBuffer;
++ u32 ulFwLength;
++#ifdef CONFIG_WOWLAN
++ u8* szWoWLANFwBuffer;
++ u32 ulWoWLANFwLength;
++#endif //CONFIG_WOWLAN
++}RT_FIRMWARE, *PRT_FIRMWARE, RT_FIRMWARE_92D, *PRT_FIRMWARE_92D;
++
++//
++// This structure must be cared byte-ordering
++//
++// Added by tynli. 2009.12.04.
++typedef struct _RT_8192D_FIRMWARE_HDR {//8-byte alinment required
++
++ //--- LONG WORD 0 ----
++ u16 Signature; // 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut
++ u8 Category; // AP/NIC and USB/PCI
++ u8 Function; // Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions
++ u16 Version; // FW Version
++ u8 Subversion; // FW Subversion, default 0x00
++ u8 Rsvd1;
++
++
++ //--- LONG WORD 1 ----
++ u8 Month; // Release time Month field
++ u8 Date; // Release time Date field
++ u8 Hour; // Release time Hour field
++ u8 Minute; // Release time Minute field
++ u16 RamCodeSize; // The size of RAM code
++ u16 Rsvd2;
++
++ //--- LONG WORD 2 ----
++ u32 SvnIdx; // The SVN entry index
++ u32 Rsvd3;
++
++ //--- LONG WORD 3 ----
++ u32 Rsvd4;
++ u32 Rsvd5;
++
++}RT_8192D_FIRMWARE_HDR, *PRT_8192D_FIRMWARE_HDR;
++
++#define DRIVER_EARLY_INT_TIME 0x05
++#define BCN_DMA_ATIME_INT_TIME 0x02
++
++typedef enum _BT_CoType{
++ BT_2Wire = 0,
++ BT_ISSC_3Wire = 1,
++ BT_Accel = 2,
++ BT_CSR = 3,
++ BT_CSR_ENHAN = 4,
++ BT_RTL8756 = 5,
++} BT_CoType, *PBT_CoType;
++
++typedef enum _BT_CurState{
++ BT_OFF = 0,
++ BT_ON = 1,
++} BT_CurState, *PBT_CurState;
++
++typedef enum _BT_ServiceType{
++ BT_SCO = 0,
++ BT_A2DP = 1,
++ BT_HID = 2,
++ BT_HID_Idle = 3,
++ BT_Scan = 4,
++ BT_Idle = 5,
++ BT_OtherAction = 6,
++ BT_Busy = 7,
++ BT_OtherBusy = 8,
++} BT_ServiceType, *PBT_ServiceType;
++
++typedef enum _BT_RadioShared{
++ BT_Radio_Shared = 0,
++ BT_Radio_Individual = 1,
++} BT_RadioShared, *PBT_RadioShared;
++
++typedef struct _BT_COEXIST_STR{
++ u8 BluetoothCoexist;
++ u8 BT_Ant_Num;
++ u8 BT_CoexistType;
++ u8 BT_State;
++ u8 BT_CUR_State; //0:on, 1:off
++ u8 BT_Ant_isolation; //0:good, 1:bad
++ u8 BT_PapeCtrl; //0:SW, 1:SW/HW dynamic
++ u8 BT_Service;
++ u8 BT_RadioSharedType;
++ u8 Ratio_Tx;
++ u8 Ratio_PRI;
++}BT_COEXIST_STR, *PBT_COEXIST_STR;
++
++//Added for 92D IQK setting.
++typedef struct _IQK_MATRIX_REGS_SETTING{
++ BOOLEAN bIQKDone;
++#if 1
++ int Value[1][IQK_Matrix_REG_NUM];
++#else
++ u32 Mark[IQK_Matrix_REG_NUM];
++ u32 Value[IQK_Matrix_REG_NUM];
++#endif
++}IQK_MATRIX_REGS_SETTING,*PIQK_MATRIX_REGS_SETTING;
++
++#ifdef CONFIG_USB_RX_AGGREGATION
++
++typedef enum _USB_RX_AGG_MODE{
++ USB_RX_AGG_DISABLE,
++ USB_RX_AGG_DMA,
++ USB_RX_AGG_USB,
++ USB_RX_AGG_DMA_USB
++}USB_RX_AGG_MODE;
++
++#define MAX_RX_DMA_BUFFER_SIZE 10240 // 10K for 8192C RX DMA buffer
++
++#endif
++
++
++#define TX_SELE_HQ BIT(0) // High Queue
++#define TX_SELE_LQ BIT(1) // Low Queue
++#define TX_SELE_NQ BIT(2) // Normal Queue
++
++
++// Note: We will divide number of page equally for each queue other than public queue!
++
++#define TX_TOTAL_PAGE_NUMBER 0xF8
++#define TX_PAGE_BOUNDARY (TX_TOTAL_PAGE_NUMBER + 1)
++
++// For Normal Chip Setting
++// (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER
++#define NORMAL_PAGE_NUM_PUBQ 0x56
++
++
++// For Test Chip Setting
++// (HPQ + LPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER
++#define TEST_PAGE_NUM_PUBQ_92DU 0x89
++#define TX_TOTAL_PAGE_NUMBER_92D_DUAL_MAC 0x7A
++#define NORMAL_PAGE_NUM_PUBQ_92D_DUAL_MAC 0x5A
++#define NORMAL_PAGE_NUM_HPQ_92D_DUAL_MAC 0x10
++#define NORMAL_PAGE_NUM_LPQ_92D_DUAL_MAC 0x10
++#define NORMAL_PAGE_NUM_NORMALQ_92D_DUAL_MAC 0
++
++#define TX_PAGE_BOUNDARY_DUAL_MAC (TX_TOTAL_PAGE_NUMBER_92D_DUAL_MAC + 1)
++
++// For Test Chip Setting
++#define WMM_TEST_TX_TOTAL_PAGE_NUMBER 0xF5
++#define WMM_TEST_TX_PAGE_BOUNDARY (WMM_TEST_TX_TOTAL_PAGE_NUMBER + 1) //F6
++
++#define WMM_TEST_PAGE_NUM_PUBQ 0xA3
++#define WMM_TEST_PAGE_NUM_HPQ 0x29
++#define WMM_TEST_PAGE_NUM_LPQ 0x29
++
++
++//Note: For Normal Chip Setting ,modify later
++#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER 0xF5
++#define WMM_NORMAL_TX_PAGE_BOUNDARY (WMM_TEST_TX_TOTAL_PAGE_NUMBER + 1) //F6
++
++#define WMM_NORMAL_PAGE_NUM_PUBQ_92D 0X65//0x82
++#define WMM_NORMAL_PAGE_NUM_HPQ_92D 0X30//0x29
++#define WMM_NORMAL_PAGE_NUM_LPQ_92D 0X30
++#define WMM_NORMAL_PAGE_NUM_NPQ_92D 0X30
++
++#define WMM_NORMAL_PAGE_NUM_PUBQ_92D_DUAL_MAC 0X32
++#define WMM_NORMAL_PAGE_NUM_HPQ_92D_DUAL_MAC 0X18
++#define WMM_NORMAL_PAGE_NUM_LPQ_92D_DUAL_MAC 0X18
++#define WMM_NORMAL_PAGE_NUM_NPQ_92D_DUAL_MAC 0X18
++
++//-------------------------------------------------------------------------
++// Chip specific
++//-------------------------------------------------------------------------
++
++#define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3)
++#define CHIP_BONDING_92C_1T2R 0x1
++#define CHIP_BONDING_88C_USB_MCARD 0x2
++#define CHIP_BONDING_88C_USB_HP 0x1
++
++//
++// 2011.01.06. Define new structure of chip version for RTL8723 and so on. Added by tynli.
++//
++/*
++ | BIT15:12 | BIT11:8 | BIT 7 | BIT6:4 | BIT3 | BIT2:0 |
++ |-------------+-----------+-----------+-------+-----------+-------|
++ | IC version(CUT) | ROM version | Manufacturer | RF type | Chip type | IC Type |
++ | | | TSMC/UMC | | TEST/NORMAL| |
++*/
++// [15:12] IC version(CUT): A-cut=0, B-cut=1, C-cut=2, D-cut=3
++// [7] Manufacturer: TSMC=0, UMC=1
++// [6:4] RF type: 1T1R=0, 1T2R=1, 2T2R=2
++// [3] Chip type: TEST=0, NORMAL=1
++// [2:0] IC type: 81xxC=0, 8723=1, 92D=2
++
++#define CHIP_8723 BIT(0)
++#define CHIP_92D BIT(1)
++#define NORMAL_CHIP BIT(3)
++#define RF_TYPE_1T1R (~(BIT(4)|BIT(5)|BIT(6)))
++#define RF_TYPE_1T2R BIT(4)
++#define RF_TYPE_2T2R BIT(5)
++#define CHIP_VENDOR_UMC BIT(7)
++#define B_CUT_VERSION BIT(12)
++#define C_CUT_VERSION BIT(13)
++#define D_CUT_VERSION ((BIT(12)|BIT(13)))
++#define E_CUT_VERSION BIT(14)
++
++
++// MASK
++#define IC_TYPE_MASK (BIT(0)|BIT(1)|BIT(2))
++#define CHIP_TYPE_MASK BIT(3)
++#define RF_TYPE_MASK (BIT(4)|BIT(5)|BIT(6))
++#define MANUFACTUER_MASK BIT(7)
++#define ROM_VERSION_MASK (BIT(11)|BIT(10)|BIT(9)|BIT(8))
++#define CUT_VERSION_MASK (BIT(15)|BIT(14)|BIT(13)|BIT(12))
++
++// Get element
++#define GET_CVID_IC_TYPE(version) ((version) & IC_TYPE_MASK)
++#define GET_CVID_CHIP_TYPE(version) ((version) & CHIP_TYPE_MASK)
++#define GET_CVID_RF_TYPE(version) ((version) & RF_TYPE_MASK)
++#define GET_CVID_MANUFACTUER(version) ((version) & MANUFACTUER_MASK)
++#define GET_CVID_ROM_VERSION(version) ((version) & ROM_VERSION_MASK)
++#define GET_CVID_CUT_VERSION(version) ((version) & CUT_VERSION_MASK)
++
++#define IS_81XXC(version) ((GET_CVID_IC_TYPE(version) == 0)? _TRUE : _FALSE)
++#define IS_8723_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8723)? _TRUE : _FALSE)
++#define IS_92D(version) ((GET_CVID_IC_TYPE(version) == CHIP_92D)? _TRUE : _FALSE)
++#define IS_1T1R(version) ((GET_CVID_RF_TYPE(version))? _FALSE : _TRUE)
++#define IS_1T2R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_1T2R)? _TRUE : _FALSE)
++#define IS_2T2R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_2T2R)? _TRUE : _FALSE)
++#define IS_CHIP_VENDOR_UMC(version) ((GET_CVID_MANUFACTUER(version))? _TRUE: _FALSE)
++
++#define IS_92C_SERIAL(version) ((IS_81XXC(version) && IS_2T2R(version)) ? _TRUE : _FALSE)
++#define IS_VENDOR_UMC_A_CUT(version) ((IS_CHIP_VENDOR_UMC(version)) ? ((GET_CVID_CUT_VERSION(version)) ? _FALSE : _TRUE) : _FALSE)
++#define IS_VENDOR_8723_A_CUT(version) ((IS_8723_SERIES(version)) ? ((GET_CVID_CUT_VERSION(version)) ? _FALSE : _TRUE) : _FALSE)
++// <tynli_Note> 88/92C UMC B-cut vendor is set to TSMC so we need to check CHIP_VENDOR_UMC bit is not 1.
++#define IS_81xxC_VENDOR_UMC_B_CUT(version) ((IS_CHIP_VENDOR_UMC(version)) ? ((GET_CVID_CUT_VERSION(version) == B_CUT_VERSION) ? _TRUE : _FALSE):_FALSE)
++#define IS_92D_SINGLEPHY(version) ((IS_92D(version)) ? (IS_2T2R(version) ? _TRUE: _FALSE) : _FALSE)
++
++#define IS_92D_C_CUT(version) ((IS_92D(version)) ? ((GET_CVID_CUT_VERSION(version) == C_CUT_VERSION) ? _TRUE : _FALSE) : _FALSE)
++#define IS_92D_D_CUT(version) ((IS_92D(version)) ? ((GET_CVID_CUT_VERSION(version) == D_CUT_VERSION) ? _TRUE : _FALSE) : _FALSE)
++#define IS_92D_E_CUT(version) ((IS_92D(version)) ? ((GET_CVID_CUT_VERSION(version) == E_CUT_VERSION) ? _TRUE : _FALSE) : _FALSE)
++#define IS_NORMAL_CHIP92D(version) ((GET_CVID_CHIP_TYPE(version))? _TRUE: _FALSE)
++
++typedef enum _VERSION_8192D{
++ VERSION_TEST_CHIP_88C = 0x0000,
++ VERSION_TEST_CHIP_92C = 0x0020,
++ VERSION_TEST_UMC_CHIP_8723 = 0x0081,
++ VERSION_NORMAL_TSMC_CHIP_88C = 0x0008,
++ VERSION_NORMAL_TSMC_CHIP_92C = 0x0028,
++ VERSION_NORMAL_TSMC_CHIP_92C_1T2R = 0x0018,
++ VERSION_NORMAL_UMC_CHIP_88C_A_CUT = 0x0088,
++ VERSION_NORMAL_UMC_CHIP_92C_A_CUT = 0x00a8,
++ VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT = 0x0098,
++ VERSION_NORMAL_UMC_CHIP_8723_1T1R_A_CUT = 0x0089,
++ VERSION_NORMAL_UMC_CHIP_8723_1T1R_B_CUT = 0x1089,
++ VERSION_NORMAL_UMC_CHIP_88C_B_CUT = 0x1088,
++ VERSION_NORMAL_UMC_CHIP_92C_B_CUT = 0x10a8,
++ VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT = 0x1090,
++ VERSION_TEST_CHIP_92D_SINGLEPHY= 0x0022,
++ VERSION_TEST_CHIP_92D_DUALPHY = 0x0002,
++ VERSION_NORMAL_CHIP_92D_SINGLEPHY= 0x002a,
++ VERSION_NORMAL_CHIP_92D_DUALPHY = 0x000a,
++ VERSION_NORMAL_CHIP_92D_C_CUT_SINGLEPHY = 0x202a,
++ VERSION_NORMAL_CHIP_92D_C_CUT_DUALPHY = 0x200a,
++ VERSION_NORMAL_CHIP_92D_D_CUT_SINGLEPHY = 0x302a,
++ VERSION_NORMAL_CHIP_92D_D_CUT_DUALPHY = 0x300a,
++ VERSION_NORMAL_CHIP_92D_E_CUT_SINGLEPHY = 0x402a,
++ VERSION_NORMAL_CHIP_92D_E_CUT_DUALPHY = 0x400a,
++}VERSION_8192D,*PVERSION_8192D;
++
++
++//-------------------------------------------------------------------------
++// Channel Plan
++//-------------------------------------------------------------------------
++enum ChannelPlan{
++ CHPL_FCC = 0,
++ CHPL_IC = 1,
++ CHPL_ETSI = 2,
++ CHPL_SPAIN = 3,
++ CHPL_FRANCE = 4,
++ CHPL_MKK = 5,
++ CHPL_MKK1 = 6,
++ CHPL_ISRAEL = 7,
++ CHPL_TELEC = 8,
++ CHPL_GLOBAL = 9,
++ CHPL_WORLD = 10,
++};
++
++typedef struct _TxPowerInfo{
++ u8 CCKIndex[RF_PATH_MAX][CHANNEL_GROUP_MAX];
++ u8 HT40_1SIndex[RF_PATH_MAX][CHANNEL_GROUP_MAX];
++ u8 HT40_2SIndexDiff[RF_PATH_MAX][CHANNEL_GROUP_MAX];
++ s8 HT20IndexDiff[RF_PATH_MAX][CHANNEL_GROUP_MAX];
++ u8 OFDMIndexDiff[RF_PATH_MAX][CHANNEL_GROUP_MAX];
++ u8 HT40MaxOffset[RF_PATH_MAX][CHANNEL_GROUP_MAX];
++ u8 HT20MaxOffset[RF_PATH_MAX][CHANNEL_GROUP_MAX];
++ u8 TSSI_A[3];
++ u8 TSSI_B[3];
++ u8 TSSI_A_5G[3]; //5GL/5GM/5GH
++ u8 TSSI_B_5G[3];
++}TxPowerInfo, *PTxPowerInfo;
++
++#define EFUSE_REAL_CONTENT_LEN 1024
++#define EFUSE_MAP_LEN 256
++#define EFUSE_MAX_SECTION 32
++#define EFUSE_MAX_SECTION_BASE 16
++// <Roger_Notes> To prevent out of boundary programming case, leave 1byte and program full section
++// 9bytes + 1byt + 5bytes and pre 1byte.
++// For worst case:
++// | 2byte|----8bytes----|1byte|--7bytes--| //92D
++#define EFUSE_OOB_PROTECT_BYTES 18 // PG data exclude header, dummy 7 bytes frome CP test and reserved 1byte.
++
++typedef enum _PA_MODE {
++ PA_MODE_EXTERNAL = 0x00,
++ PA_MODE_INTERNAL_SP3T = 0x01,
++ PA_MODE_INTERNAL_SPDT = 0x02
++} PA_MODE;
++
++/* Copy from rtl8192c */
++enum c2h_id_8192d {
++ C2H_DBG = 0,
++ C2H_TSF = 1,
++ C2H_AP_RPT_RSP = 2,
++ C2H_CCX_TX_RPT = 3,
++ C2H_BT_RSSI = 4,
++ C2H_BT_OP_MODE = 5,
++ C2H_EXT_RA_RPT = 6,
++ C2H_HW_INFO_EXCH = 10,
++ C2H_C2H_H2C_TEST = 11,
++ C2H_BT_INFO = 12,
++ C2H_BT_MP_INFO = 15,
++ MAX_C2HEVENT
++};
++
++#ifdef CONFIG_PCI_HCI
++struct hal_data_8192de
++{
++ VERSION_8192D VersionID;
++
++ // add for 92D Phy mode/mac/Band mode
++ MACPHY_MODE_8192D MacPhyMode92D;
++ BAND_TYPE CurrentBandType92D; //0:2.4G, 1:5G
++ BAND_TYPE BandSet92D;
++ BOOLEAN bIsVS;
++ BOOLEAN bSupportRemoteWakeUp;
++ u8 AutoLoadStatusFor8192D;
++
++ BOOLEAN bNOPG;
++
++ BOOLEAN bMasterOfDMSP;
++ BOOLEAN bSlaveOfDMSP;
++
++ u16 CustomerID;
++
++ u16 FirmwareVersion;
++ u16 FirmwareVersionRev;
++ u16 FirmwareSubVersion;
++
++ u32 IntrMask[2];
++ u32 IntrMaskToSet[2];
++
++ u32 DisabledFunctions;
++
++ //current WIFI_PHY values
++ u32 ReceiveConfig;
++ u32 TransmitConfig;
++ WIRELESS_MODE CurrentWirelessMode;
++ HT_CHANNEL_WIDTH CurrentChannelBW;
++ u8 CurrentChannel;
++ u8 nCur40MhzPrimeSC;// Control channel sub-carrier
++ u16 BasicRateSet;
++
++ //rf_ctrl
++ u8 rf_chip;
++ u8 rf_type;
++ u8 NumTotalRFPath;
++
++ //
++ // EEPROM setting.
++ //
++ u16 EEPROMVID;
++ u16 EEPROMDID;
++ u16 EEPROMSVID;
++ u16 EEPROMSMID;
++ u16 EEPROMChannelPlan;
++ u16 EEPROMVersion;
++
++ u8 EEPROMCustomerID;
++ u8 EEPROMBoardType;
++ u8 EEPROMRegulatory;
++
++ u8 EEPROMThermalMeter;
++
++ u8 EEPROMC9;
++ u8 EEPROMCC;
++ u8 PAMode;
++
++ u8 TxPwrLevelCck[RF_PATH_MAX][CHANNEL_MAX_NUMBER_2G];
++ u8 TxPwrLevelHT40_1S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr
++ u8 TxPwrLevelHT40_2S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr
++ s8 TxPwrHt20Diff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// HT 20<->40 Pwr diff
++ u8 TxPwrLegacyHtDiff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// For HT<->legacy pwr diff
++ // For power group
++ u8 PwrGroupHT20[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
++ u8 PwrGroupHT40[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
++
++ u8 LegacyHTTxPowerDiff;// Legacy to HT rate power diff
++
++ u8 CrystalCap; // CrystalCap.
++
++#ifdef CONFIG_BT_COEXIST
++ struct btcoexist_priv bt_coexist;
++#endif
++
++ // Read/write are allow for following hardware information variables
++ u8 framesync;
++ u32 framesyncC34;
++ u8 framesyncMonitor;
++ u8 DefaultInitialGain[4];
++ u8 pwrGroupCnt;
++ u32 MCSTxPowerLevelOriginalOffset[MAX_PG_GROUP][16];
++ u32 CCKTxPowerLevelOriginalOffset;
++
++ u32 AntennaTxPath; // Antenna path Tx
++ u32 AntennaRxPath; // Antenna path Rx
++ u8 BluetoothCoexist;
++ u8 ExternalPA;
++ u8 InternalPA5G[2]; //pathA / pathB
++
++ //u32 LedControlNum;
++ //u32 LedControlMode;
++ //u32 TxPowerTrackControl;
++ u8 b1x1RecvCombine; // for 1T1R receive combining
++
++ u8 bCurrentTurboEDCA;
++ u32 AcParam_BE; //Original parameter for BE, use for EDCA turbo.
++
++ //vivi, for tx power tracking, 20080407
++ //u16 TSSI_13dBm;
++ //u32 Pwr_Track;
++ // The current Tx Power Level
++ u8 CurrentCckTxPwrIdx;
++ u8 CurrentOfdm24GTxPwrIdx;
++
++ BB_REGISTER_DEFINITION_T PHYRegDef[4]; //Radio A/B/C/D
++
++ BOOLEAN bRFPathRxEnable[4]; // We support 4 RF path now.
++
++ u32 RfRegChnlVal[2];
++
++ u8 bCckHighPower;
++
++ BOOLEAN bPhyValueInitReady;
++
++ BOOLEAN bTXPowerDataReadFromEEPORM;
++
++ BOOLEAN bInSetPower;
++
++ //RDG enable
++ BOOLEAN bRDGEnable;
++
++ BOOLEAN bLoadIMRandIQKSettingFor2G;// True if IMR or IQK have done for 2.4G in scan progress
++ BOOLEAN bNeedIQK;
++
++ BOOLEAN bLCKInProgress;
++
++ BOOLEAN bEarlyModeEnable;
++
++#if 1
++ IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM];
++#else
++ //regc80¡¢regc94¡¢regc4c¡¢regc88¡¢regc9c¡¢regc14¡¢regca0¡¢regc1c¡¢regc78
++ u4Byte IQKMatrixReg[IQK_Matrix_REG_NUM];
++ IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM]; // 1->2G,24->5G 20M channel,21->5G 40M channel.
++#endif
++
++ //for host message to fw
++ u8 LastHMEBoxNum;
++
++ u8 fw_ractrl;
++ // Beacon function related global variable.
++ u32 RegBcnCtrlVal;
++ u8 RegTxPause;
++ u8 RegFwHwTxQCtrl;
++ u8 RegReg542;
++ u8 RegCR_1;
++
++ struct dm_priv dmpriv;
++
++ u8 bInterruptMigration;
++
++ u8 FwRsvdPageStartOffset; //2010.06.23. Added by tynli. Reserve page start offset except beacon in TxQ.
++
++ // Add for dual MAC 0--Mac0 1--Mac1
++ u32 interfaceIndex;
++
++ u16 RegRRSR;
++
++ u16 EfuseUsedBytes;
++ u8 RTSInitRate; // 2010.11.24.by tynli.
++#ifdef CONFIG_P2P
++ struct P2P_PS_Offload_t p2p_ps_offload;
++#endif //CONFIG_P2P
++};
++
++typedef struct hal_data_8192de HAL_DATA_TYPE, *PHAL_DATA_TYPE;
++
++//
++// Function disabled.
++//
++#define DF_TX_BIT BIT0
++#define DF_RX_BIT BIT1
++#define DF_IO_BIT BIT2
++#define DF_IO_D3_BIT BIT3
++
++#define RT_DF_TYPE u32
++#define RT_DISABLE_FUNC(__pAdapter, __FuncBits) ((__pAdapter)->DisabledFunctions |= ((RT_DF_TYPE)(__FuncBits)))
++#define RT_ENABLE_FUNC(__pAdapter, __FuncBits) ((__pAdapter)->DisabledFunctions &= (~((RT_DF_TYPE)(__FuncBits))))
++#define RT_IS_FUNC_DISABLED(__pAdapter, __FuncBits) ( (__pAdapter)->DisabledFunctions & (__FuncBits) )
++
++void InterruptRecognized8192DE(PADAPTER Adapter, PRT_ISR_CONTENT pIsrContent);
++VOID UpdateInterruptMask8192DE(PADAPTER Adapter, u32 AddMSR, u32 RemoveMSR);
++#endif
++
++#ifdef CONFIG_USB_HCI
++
++//should be renamed and moved to another file
++typedef enum _INTERFACE_SELECT_8192DUSB{
++ INTF_SEL0_USB = 0, // USB
++ INTF_SEL1_MINICARD = 1, // Minicard
++ INTF_SEL2_EKB_PRO = 2, // Eee keyboard proprietary
++ INTF_SEL3_PRO = 3, // Customized proprietary
++} INTERFACE_SELECT_8192DUSB, *PINTERFACE_SELECT_8192DUSB;
++
++typedef INTERFACE_SELECT_8192DUSB INTERFACE_SELECT_USB;
++
++struct hal_data_8192du
++{
++ VERSION_8192D VersionID;
++
++ // add for 92D Phy mode/mac/Band mode
++ MACPHY_MODE_8192D MacPhyMode92D;
++ BAND_TYPE CurrentBandType92D; //0:2.4G, 1:5G
++ BAND_TYPE BandSet92D;
++ BOOLEAN bIsVS;
++
++ BOOLEAN bNOPG;
++
++ BOOLEAN bSupportRemoteWakeUp;
++ BOOLEAN bMasterOfDMSP;
++ BOOLEAN bSlaveOfDMSP;
++#ifdef CONFIG_DUALMAC_CONCURRENT
++ BOOLEAN bInModeSwitchProcess;
++#endif
++
++ u16 CustomerID;
++
++ u16 FirmwareVersion;
++ u16 FirmwareVersionRev;
++ u16 FirmwareSubVersion;
++
++ //current WIFI_PHY values
++ u32 ReceiveConfig;
++ WIRELESS_MODE CurrentWirelessMode;
++ HT_CHANNEL_WIDTH CurrentChannelBW;
++ u8 CurrentChannel;
++ u8 nCur40MhzPrimeSC;// Control channel sub-carrier
++ u16 BasicRateSet;
++
++ INTERFACE_SELECT_8192DUSB InterfaceSel;
++
++ //rf_ctrl
++ u8 rf_chip;
++ u8 rf_type;
++ u8 NumTotalRFPath;
++
++ //
++ // EEPROM setting.
++ //
++ u8 EEPROMVersion;
++ u16 EEPROMVID;
++ u16 EEPROMPID;
++ u16 EEPROMSVID;
++ u16 EEPROMSDID;
++ u8 EEPROMCustomerID;
++ u8 EEPROMSubCustomerID;
++ u8 EEPROMRegulatory;
++
++ u8 EEPROMThermalMeter;
++
++ u8 EEPROMC9;
++ u8 EEPROMCC;
++ u8 PAMode;
++
++ u8 TxPwrLevelCck[RF_PATH_MAX][CHANNEL_MAX_NUMBER_2G];
++ u8 TxPwrLevelHT40_1S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr
++ u8 TxPwrLevelHT40_2S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr
++ s8 TxPwrHt20Diff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// HT 20<->40 Pwr diff
++ u8 TxPwrLegacyHtDiff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// For HT<->legacy pwr diff
++ // For power group
++ u8 PwrGroupHT20[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
++ u8 PwrGroupHT40[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
++
++ u8 LegacyHTTxPowerDiff;// Legacy to HT rate power diff
++
++ u8 CrystalCap; // CrystalCap.
++
++#ifdef CONFIG_BT_COEXIST
++ struct btcoexist_priv bt_coexist;
++#endif
++
++ // Read/write are allow for following hardware information variables
++ u8 framesync;
++ u32 framesyncC34;
++ u8 framesyncMonitor;
++ u8 DefaultInitialGain[4];
++ u8 pwrGroupCnt;
++ u32 MCSTxPowerLevelOriginalOffset[MAX_PG_GROUP][16];
++ u32 CCKTxPowerLevelOriginalOffset;
++
++ u32 AntennaTxPath; // Antenna path Tx
++ u32 AntennaRxPath; // Antenna path Rx
++ u8 BluetoothCoexist;
++ u8 ExternalPA;
++ u8 InternalPA5G[2]; //pathA / pathB
++
++ //u32 LedControlNum;
++ //u32 LedControlMode;
++ //u32 TxPowerTrackControl;
++ u8 b1x1RecvCombine; // for 1T1R receive combining
++
++ u8 bCurrentTurboEDCA;
++ u32 AcParam_BE; //Original parameter for BE, use for EDCA turbo.
++
++ //vivi, for tx power tracking, 20080407
++ //u16 TSSI_13dBm;
++ //u32 Pwr_Track;
++ // The current Tx Power Level
++ u8 CurrentCckTxPwrIdx;
++ u8 CurrentOfdm24GTxPwrIdx;
++
++ BB_REGISTER_DEFINITION_T PHYRegDef[4]; //Radio A/B/C/D
++
++ BOOLEAN bRFPathRxEnable[4]; // We support 4 RF path now.
++
++ u32 RfRegChnlVal[2];
++
++ u8 bCckHighPower;
++
++ BOOLEAN bPhyValueInitReady;
++
++ BOOLEAN bTXPowerDataReadFromEEPORM;
++
++ BOOLEAN bInSetPower;
++
++ //RDG enable
++ BOOLEAN bRDGEnable;
++
++ BOOLEAN bLoadIMRandIQKSettingFor2G;// True if IMR or IQK have done for 2.4G in scan progress
++ BOOLEAN bNeedIQK;
++
++ BOOLEAN bLCKInProgress;
++
++ BOOLEAN bEarlyModeEnable;
++
++#if 1
++ IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM];
++#else
++ //regc80¡¢regc94¡¢regc4c¡¢regc88¡¢regc9c¡¢regc14¡¢regca0¡¢regc1c¡¢regc78
++ u4Byte IQKMatrixReg[IQK_Matrix_REG_NUM];
++ IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM]; // 1->2G,24->5G 20M channel,21->5G 40M channel.
++#endif
++
++ //for host message to fw
++ u8 LastHMEBoxNum;
++
++ u8 fw_ractrl;
++ // Beacon function related global variable.
++ u32 RegBcnCtrlVal;
++ u8 RegTxPause;
++ u8 RegFwHwTxQCtrl;
++ u8 RegReg542;
++ u8 RegCR_1;
++
++ struct dm_priv dmpriv;
++
++ u8 FwRsvdPageStartOffset; //2010.06.23. Added by tynli. Reserve page start offset except beacon in TxQ.
++
++ //Query RF by FW
++ BOOLEAN bReadRFbyFW;
++
++ // For 92C USB endpoint setting
++ //
++
++ u32 UsbBulkOutSize;
++
++ int RtBulkOutPipe[3];
++ int RtBulkInPipe;
++ int RtIntInPipe;
++
++ // Add for dual MAC 0--Mac0 1--Mac1
++ u32 interfaceIndex;
++
++ u8 OutEpQueueSel;
++ u8 OutEpNumber;
++
++ u8 Queue2EPNum[8];//for out endpoint number mapping
++
++#ifdef CONFIG_USB_TX_AGGREGATION
++ u8 UsbTxAggMode;
++ u8 UsbTxAggDescNum;
++#endif
++#ifdef CONFIG_USB_RX_AGGREGATION
++ u16 HwRxPageSize; // Hardware setting
++ u32 MaxUsbRxAggBlock;
++
++ USB_RX_AGG_MODE UsbRxAggMode;
++ u8 UsbRxAggBlockCount; // USB Block count. Block size is 512-byte in hight speed and 64-byte in full speed
++ u8 UsbRxAggBlockTimeout;
++ u8 UsbRxAggPageCount; // 8192C DMA page count
++ u8 UsbRxAggPageTimeout;
++#endif
++
++ u16 RegRRSR;
++
++ u16 EfuseUsedBytes;
++ u8 RTSInitRate; // 2010.11.24.by tynli.
++#ifdef CONFIG_P2P
++ struct P2P_PS_Offload_t p2p_ps_offload;
++#endif //CONFIG_P2P
++};
++
++typedef struct hal_data_8192du HAL_DATA_TYPE, *PHAL_DATA_TYPE;
++#endif
++
++#define GET_HAL_DATA(__pAdapter) ((HAL_DATA_TYPE *)((__pAdapter)->HalData))
++#define GET_RF_TYPE(priv) (GET_HAL_DATA(priv)->rf_type)
++
++int FirmwareDownload92D(IN PADAPTER Adapter,IN BOOLEAN bUsedWoWLANFw);
++VOID rtl8192d_FirmwareSelfReset(IN PADAPTER Adapter);
++void rtl8192d_ReadChipVersion(IN PADAPTER Adapter);
++VOID rtl8192d_EfuseParseChnlPlan(PADAPTER Adapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
++VOID rtl8192d_ReadTxPowerInfo(PADAPTER Adapter, u8* PROMContent, BOOLEAN AutoLoadFail);
++VOID rtl8192d_ResetDualMacSwitchVariables(IN PADAPTER Adapter);
++u8 GetEEPROMSize8192D(PADAPTER Adapter);
++BOOLEAN PHY_CheckPowerOffFor8192D(PADAPTER Adapter);
++VOID PHY_SetPowerOnFor8192D(PADAPTER Adapter);
++//void PHY_ConfigMacPhyMode92D(PADAPTER Adapter);
++void rtl8192d_free_hal_data(_adapter * padapter);
++void rtl8192d_set_hal_ops(struct hal_ops *pHalFunc);
++
++#endif
++
++#ifdef CONFIG_MP_INCLUDED
++
++
++extern void Hal_SetAntenna(PADAPTER pAdapter);
++extern void Hal_SetBandwidth(PADAPTER pAdapter);
++
++extern void Hal_SetTxPower(PADAPTER pAdapter);
++extern void Hal_SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart);
++extern void Hal_SetSingleToneTx ( PADAPTER pAdapter , u8 bStart );
++extern void Hal_SetSingleCarrierTx (PADAPTER pAdapter, u8 bStart);
++extern void Hal_SetContinuousTx (PADAPTER pAdapter, u8 bStart);
++extern void Hal_SetBandwidth(PADAPTER pAdapter);
++
++extern void Hal_SetDataRate(PADAPTER pAdapter);
++extern void Hal_SetChannel(PADAPTER pAdapter);
++extern void Hal_SetAntennaPathPower(PADAPTER pAdapter);
++extern s32 Hal_SetThermalMeter(PADAPTER pAdapter, u8 target_ther);
++extern s32 Hal_SetPowerTracking(PADAPTER padapter, u8 enable);
++extern void Hal_GetPowerTracking(PADAPTER padapter, u8 * enable);
++extern void Hal_GetThermalMeter(PADAPTER pAdapter, u8 *value);
++extern void Hal_mpt_SwitchRfSetting(PADAPTER pAdapter);
++extern void Hal_MPT_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14);
++extern void Hal_MPT_CCKTxPowerAdjustbyIndex(PADAPTER pAdapter, BOOLEAN beven);
++extern void Hal_SetCCKTxPower(PADAPTER pAdapter, u8 * TxPower);
++extern void Hal_SetOFDMTxPower(PADAPTER pAdapter, u8 * TxPower);
++extern void Hal_TriggerRFThermalMeter(PADAPTER pAdapter);
++extern u8 Hal_ReadRFThermalMeter(PADAPTER pAdapter);
++extern void Hal_SetCCKContinuousTx(PADAPTER pAdapter, u8 bStart);
++extern void Hal_SetOFDMContinuousTx(PADAPTER pAdapter, u8 bStart);
++
++
++#endif //end CONFIG_MP_INCLUDED
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtl8192d_led.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtl8192d_led.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtl8192d_led.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtl8192d_led.h 2015-07-28 01:20:58.321597318 +0200
+@@ -0,0 +1,42 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef __RTL8192D_LED_H_
++#define __RTL8192D_LED_H_
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++
++
++//================================================================================
++// Interface to manipulate LED objects.
++//================================================================================
++#ifdef CONFIG_USB_HCI
++void rtl8192du_InitSwLeds(_adapter *padapter);
++void rtl8192du_DeInitSwLeds(_adapter *padapter);
++#endif
++
++#ifdef CONFIG_PCI_HCI
++void rtl8192de_gen_RefreshLedState(PADAPTER Adapter);
++void rtl8192de_InitSwLeds(_adapter *padapter);
++void rtl8192de_DeInitSwLeds(_adapter *padapter);
++#endif
++
++#endif
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtl8192d_recv.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtl8192d_recv.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtl8192d_recv.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtl8192d_recv.h 2015-07-28 01:20:58.321597318 +0200
+@@ -0,0 +1,186 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef _RTL8192D_RECV_H_
++#define _RTL8192D_RECV_H_
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++
++
++#ifdef PLATFORM_OS_XP
++ #ifdef CONFIG_SDIO_HCI
++ #define NR_RECVBUFF 1024//512//128
++ #else
++ #define NR_RECVBUFF (16)
++ #endif
++#elif defined(PLATFORM_OS_CE)
++ #ifdef CONFIG_SDIO_HCI
++ #define NR_RECVBUFF (128)
++ #else
++ #define NR_RECVBUFF (4)
++ #endif
++#else
++#ifdef CONFIG_SINGLE_RECV_BUF
++ #define NR_RECVBUFF (1)
++#else
++ #define NR_RECVBUFF (4)
++#endif //CONFIG_SINGLE_RECV_BUF
++ #define NR_PREALLOC_RECV_SKB (8)
++#endif
++
++
++
++#define RECV_BLK_SZ 512
++#define RECV_BLK_CNT 16
++#define RECV_BLK_TH RECV_BLK_CNT
++
++#if defined(CONFIG_USB_HCI)
++
++#ifdef PLATFORM_OS_CE
++#define MAX_RECVBUF_SZ (8192+1024) // 8K+1k
++#else
++ #ifndef CONFIG_MINIMAL_MEMORY_USAGE
++ //#define MAX_RECVBUF_SZ (32768) // 32k
++ //#define MAX_RECVBUF_SZ (16384) //16K
++ //#define MAX_RECVBUF_SZ (10240) //10K
++ #ifdef CONFIG_PLATFORM_MSTAR
++ #define MAX_RECVBUF_SZ (8192) // 8K
++ #else
++ #define MAX_RECVBUF_SZ (15360) // 15k < 16k
++ #endif
++ #else
++ #define MAX_RECVBUF_SZ (4000) // about 4K
++ #endif
++#endif
++
++#elif defined(CONFIG_PCI_HCI)
++//#ifndef CONFIG_MINIMAL_MEMORY_USAGE
++// #define MAX_RECVBUF_SZ (9100)
++//#else
++ #define MAX_RECVBUF_SZ (4000) // about 4K
++//#endif
++
++#define RX_MPDU_QUEUE 0
++#define RX_CMD_QUEUE 1
++#define RX_MAX_QUEUE 2
++#endif
++
++#define RECV_BULK_IN_ADDR 0x80
++#define RECV_INT_IN_ADDR 0x81
++
++#define PHY_RSSI_SLID_WIN_MAX 100
++#define PHY_LINKQUALITY_SLID_WIN_MAX 20
++
++struct phy_stat
++{
++ unsigned int phydw0;
++
++ unsigned int phydw1;
++
++ unsigned int phydw2;
++
++ unsigned int phydw3;
++
++ unsigned int phydw4;
++
++ unsigned int phydw5;
++
++ unsigned int phydw6;
++
++ unsigned int phydw7;
++};
++
++typedef struct _Phy_OFDM_Rx_Status_Report_8192cd
++{
++ unsigned char trsw_gain_X[4];
++ unsigned char pwdb_all;
++ unsigned char cfosho_X[4];
++ unsigned char cfotail_X[4];
++ unsigned char rxevm_X[2];
++ unsigned char rxsnr_X[4];
++ unsigned char pdsnr_X[2];
++ unsigned char csi_current_X[2];
++ unsigned char csi_target_X[2];
++ unsigned char sigevm;
++ unsigned char max_ex_pwr;
++//#ifdef RTL8192SE
++#ifdef CONFIG_LITTLE_ENDIAN
++ unsigned char ex_intf_flg:1;
++ unsigned char sgi_en:1;
++ unsigned char rxsc:2;
++ //unsigned char rsvd:4;
++ unsigned char idle_long:1;
++ unsigned char r_ant_train_en:1;
++ unsigned char ANTSELB:1;
++ unsigned char ANTSEL:1;
++#else // _BIG_ENDIAN_
++ //unsigned char rsvd:4;
++ unsigned char ANTSEL:1;
++ unsigned char ANTSELB:1;
++ unsigned char r_ant_train_en:1;
++ unsigned char idle_long:1;
++ unsigned char rxsc:2;
++ unsigned char sgi_en:1;
++ unsigned char ex_intf_flg:1;
++#endif
++//#else // RTL8190, RTL8192E
++// unsigned char sgi_en;
++// unsigned char rxsc_sgien_exflg;
++//#endif
++}__attribute__ ((packed)) PHY_STS_OFDM_8192CD_T,PHY_RX_DRIVER_INFO_8192CD;
++
++typedef struct _Phy_CCK_Rx_Status_Report_8192cd
++{
++ /* For CCK rate descriptor. This is a signed 8:1 variable. LSB bit presend
++ 0.5. And MSB 7 bts presend a signed value. Range from -64~+63.5. */
++ u8 adc_pwdb_X[4];
++ u8 SQ_rpt;
++ u8 cck_agc_rpt;
++} PHY_STS_CCK_8192CD_T;
++
++// Rx smooth factor
++#define Rx_Smooth_Factor (20)
++
++#ifdef CONFIG_USB_HCI
++typedef struct _INTERRUPT_MSG_FORMAT_EX{
++ unsigned int C2H_MSG0;
++ unsigned int C2H_MSG1;
++ unsigned int C2H_MSG2;
++ unsigned int C2H_MSG3;
++ unsigned int HISR; // from HISR Reg0x124, read to clear
++ unsigned int HISRE;// from HISRE Reg0x12c, read to clear
++ unsigned int MSG_EX;
++}INTERRUPT_MSG_FORMAT_EX,*PINTERRUPT_MSG_FORMAT_EX;
++
++void rtl8192du_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf);
++int rtl8192du_init_recv_priv(_adapter * padapter);
++void rtl8192du_free_recv_priv(_adapter * padapter);
++#endif
++
++#ifdef CONFIG_PCI_HCI
++int rtl8192de_init_recv_priv(_adapter * padapter);
++void rtl8192de_free_recv_priv(_adapter * padapter);
++#endif
++
++void rtl8192d_translate_rx_signal_stuff(union recv_frame *precvframe, struct phy_stat *pphy_info);
++void rtl8192d_query_rx_desc_status(union recv_frame *precvframe, struct recv_stat *pdesc);
++
++#endif
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtl8192d_rf.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtl8192d_rf.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtl8192d_rf.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtl8192d_rf.h 2015-07-28 01:20:58.321597318 +0200
+@@ -0,0 +1,96 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++/******************************************************************************
++ *
++ *
++ * Module: rtl8192d_rf.h ( Header File)
++ *
++ * Note: Collect every HAL RF type exter API or constant.
++ *
++ * Function:
++ *
++ * Export:
++ *
++ * Abbrev:
++ *
++ * History:
++ * Data Who Remark
++ *
++ * 09/25/2008 MHC Create initial version.
++ *
++ *
++******************************************************************************/
++#ifndef _RTL8192D_RF_H_
++#define _RTL8192D_RF_H_
++/* Check to see if the file has been included already. */
++
++
++/*--------------------------Define Parameters-------------------------------*/
++
++//
++// For RF 6052 Series
++//
++#define RF6052_MAX_TX_PWR 0x3F
++#define RF6052_MAX_REG 0x3F
++#define RF6052_MAX_PATH 2
++/*--------------------------Define Parameters-------------------------------*/
++
++
++/*------------------------------Define structure----------------------------*/
++
++/*------------------------------Define structure----------------------------*/
++
++
++/*------------------------Export global variable----------------------------*/
++/*------------------------Export global variable----------------------------*/
++
++/*------------------------Export Marco Definition---------------------------*/
++
++/*------------------------Export Marco Definition---------------------------*/
++
++
++/*--------------------------Exported Function prototype---------------------*/
++
++//
++// RF RL6052 Series API
++//
++void rtl8192d_RF_ChangeTxPath( IN PADAPTER Adapter,
++ IN u16 DataRate);
++void rtl8192d_PHY_RF6052SetBandwidth(
++ IN PADAPTER Adapter,
++ IN HT_CHANNEL_WIDTH Bandwidth);
++VOID rtl8192d_PHY_RF6052SetCckTxPower(
++ IN PADAPTER Adapter,
++ IN u8* pPowerlevel);
++VOID rtl8192d_PHY_RF6052SetOFDMTxPower(
++ IN PADAPTER Adapter,
++ IN u8* pPowerLevel,
++ IN u8 Channel);
++int PHY_RF6052_Config8192D( IN PADAPTER Adapter );
++
++BOOLEAN rtl8192d_PHY_EnableAnotherPHY(IN PADAPTER Adapter, IN BOOLEAN bMac0);
++
++void rtl8192d_PHY_PowerDownAnotherPHY(IN PADAPTER Adapter, IN BOOLEAN bMac0);
++
++
++/*--------------------------Exported Function prototype---------------------*/
++
++
++#endif/* End of HalRf.h */
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtl8192d_spec.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtl8192d_spec.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtl8192d_spec.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtl8192d_spec.h 2015-07-28 01:20:58.321597318 +0200
+@@ -0,0 +1,1840 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++
++#ifndef __RTL8192D_SPEC_H__
++#define __RTL8192D_SPEC_H__
++
++#include <drv_conf.h>
++
++#ifndef BIT
++#define BIT(x) (1 << (x))
++#endif
++
++#define BIT0 0x00000001
++#define BIT1 0x00000002
++#define BIT2 0x00000004
++#define BIT3 0x00000008
++#define BIT4 0x00000010
++#define BIT5 0x00000020
++#define BIT6 0x00000040
++#define BIT7 0x00000080
++#define BIT8 0x00000100
++#define BIT9 0x00000200
++#define BIT10 0x00000400
++#define BIT11 0x00000800
++#define BIT12 0x00001000
++#define BIT13 0x00002000
++#define BIT14 0x00004000
++#define BIT15 0x00008000
++#define BIT16 0x00010000
++#define BIT17 0x00020000
++#define BIT18 0x00040000
++#define BIT19 0x00080000
++#define BIT20 0x00100000
++#define BIT21 0x00200000
++#define BIT22 0x00400000
++#define BIT23 0x00800000
++#define BIT24 0x01000000
++#define BIT25 0x02000000
++#define BIT26 0x04000000
++#define BIT27 0x08000000
++#define BIT28 0x10000000
++#define BIT29 0x20000000
++#define BIT30 0x40000000
++#define BIT31 0x80000000
++
++
++//============================================================
++// 8192D Regsiter offset definition
++//============================================================
++
++
++//============================================================
++//
++//============================================================
++
++//-----------------------------------------------------
++//
++// 0x0000h ~ 0x00FFh System Configuration
++//
++//-----------------------------------------------------
++#define REG_SYS_ISO_CTRL 0x0000
++#define REG_SYS_FUNC_EN 0x0002
++#define REG_APS_FSMCO 0x0004
++#define REG_SYS_CLKR 0x0008
++#define REG_9346CR 0x000A
++#define REG_EE_VPD 0x000C
++#define REG_AFE_MISC 0x0010
++#define REG_SPS0_CTRL 0x0011
++#define REG_POWER_OFF_IN_PROCESS 0x0017
++#define REG_SPS_OCP_CFG 0x0018
++#define REG_RSV_CTRL 0x001C
++#define REG_RF_CTRL 0x001F
++#define REG_LDOA15_CTRL 0x0020
++#define REG_LDOV12D_CTRL 0x0021
++#define REG_LDOHCI12_CTRL 0x0022
++#define REG_LPLDO_CTRL 0x0023
++#define REG_AFE_XTAL_CTRL 0x0024
++#define REG_AFE_PLL_CTRL 0x0028
++#define REG_MAC_PHY_CTRL 0x002c //for 92d, DMDP,SMSP,DMSP contrl
++#define REG_EFUSE_CTRL 0x0030
++#define REG_EFUSE_TEST 0x0034
++#define REG_PWR_DATA 0x0038
++#define REG_CAL_TIMER 0x003C
++#define REG_ACLK_MON 0x003E
++#define REG_GPIO_MUXCFG 0x0040
++//#define REG_GPIO_MUXCFG 0x0041
++#define REG_GPIO_IO_SEL 0x0042
++#define REG_MAC_PINMUX_CFG 0x0043
++#define REG_GPIO_PIN_CTRL 0x0044
++#define REG_GPIO_INTM 0x0048
++#define REG_LEDCFG0 0x004C
++#define REG_LEDCFG1 0x004D
++#define REG_LEDCFG2 0x004E
++#define REG_LEDCFG3 0x004F
++#define REG_FSIMR 0x0050
++#define REG_FSISR 0x0054
++
++#define REG_MCUFWDL 0x0080
++#ifdef CONFIG_WOWLAN
++#define REG_WOWLAN_REASON 0x00FC
++#endif // CONFIG_WOWLAN
++#define REG_HMEBOX_EXT_0 0x0088
++#define REG_HMEBOX_EXT_1 0x008A
++#define REG_HMEBOX_EXT_2 0x008C
++#define REG_HMEBOX_EXT_3 0x008E
++
++#define REG_BIST_SCAN 0x00D0
++#define REG_BIST_RPT 0x00D4
++#define REG_BIST_ROM_RPT 0x00D8
++#define REG_USB_SIE_INTF 0x00E0
++#define REG_PCIE_MIO_INTF 0x00E4
++#define REG_PCIE_MIO_INTD 0x00E8
++#define REG_HPON_FSM 0x00EC
++#define REG_SYS_CFG 0x00F0
++#define REG_MAC_PHY_CTRL_NORMAL 0x00f8
++
++#define REG_MAC0 0x0081
++#define REG_MAC1 0x0053
++#define FW_MAC0_ready 0x18
++#define FW_MAC1_ready 0x1A
++#define MAC0_ON BIT7
++#define MAC1_ON BIT0
++#define mac0_ready BIT0
++#define mac1_ready BIT0
++
++
++//-----------------------------------------------------
++//
++// 0x0100h ~ 0x01FFh MACTOP General Configuration
++//
++//-----------------------------------------------------
++#define REG_CR 0x0100
++#define REG_PBP 0x0104
++#define REG_TRXDMA_CTRL 0x010C
++#define REG_TRXFF_BNDY 0x0114
++#define REG_TRXFF_STATUS 0x0118
++#define REG_RXFF_PTR 0x011C
++#define REG_HIMR 0x0120
++#define REG_HISR 0x0124
++#define REG_HIMRE 0x0128
++#define REG_HISRE 0x012C
++#define REG_CPWM 0x012F
++#define REG_FWIMR 0x0130
++#define REG_FWISR 0x0134
++#define REG_FTIMR 0x0138
++#define REG_PKTBUF_DBG_CTRL 0x0140
++#define REG_PKTBUF_DBG_DATA_L 0x0144
++#define REG_PKTBUF_DBG_DATA_H 0x0148
++
++#define REG_TC0_CTRL 0x0150
++#define REG_TC1_CTRL 0x0154
++#define REG_TC2_CTRL 0x0158
++#define REG_TC3_CTRL 0x015C
++#define REG_TC4_CTRL 0x0160
++#define REG_TCUNIT_BASE 0x0164
++#define REG_MBIST_START 0x0174
++#define REG_MBIST_DONE 0x0178
++#define REG_MBIST_FAIL 0x017C
++#define REG_C2HEVT_MSG_NORMAL 0x01A0
++#define REG_C2HEVT_CLEAR 0x01AF
++#define REG_C2HEVT_MSG_TEST 0x01B8
++#define REG_MCUTST_1 0x01c0
++#define REG_FMETHR 0x01C8
++#define REG_HMETFR 0x01CC
++#define REG_HMEBOX_0 0x01D0
++#define REG_HMEBOX_1 0x01D4
++#define REG_HMEBOX_2 0x01D8
++#define REG_HMEBOX_3 0x01DC
++
++#define REG_LLT_INIT 0x01E0
++#define REG_BB_ACCEESS_CTRL 0x01E8
++#define REG_BB_ACCESS_DATA 0x01EC
++
++
++//-----------------------------------------------------
++//
++// 0x0200h ~ 0x027Fh TXDMA Configuration
++//
++//-----------------------------------------------------
++#define REG_RQPN 0x0200
++#define REG_FIFOPAGE 0x0204
++#define REG_TDECTRL 0x0208
++#define REG_TXDMA_OFFSET_CHK 0x020C
++#define REG_TXDMA_STATUS 0x0210
++#define REG_RQPN_NPQ 0x0214
++
++//-----------------------------------------------------
++//
++// 0x0280h ~ 0x02FFh RXDMA Configuration
++//
++//-----------------------------------------------------
++#define REG_RXDMA_AGG_PG_TH 0x0280
++#define REG_RXPKT_NUM 0x0284
++#define REG_RXDMA_STATUS 0x0288
++
++
++//-----------------------------------------------------
++//
++// 0x0300h ~ 0x03FFh PCIe
++//
++//-----------------------------------------------------
++#define REG_PCIE_CTRL_REG 0x0300
++#define REG_INT_MIG 0x0304 // Interrupt Migration
++#define REG_BCNQ_DESA 0x0308 // TX Beacon Descriptor Address
++#define REG_HQ_DESA 0x0310 // TX High Queue Descriptor Address
++#define REG_MGQ_DESA 0x0318 // TX Manage Queue Descriptor Address
++#define REG_VOQ_DESA 0x0320 // TX VO Queue Descriptor Address
++#define REG_VIQ_DESA 0x0328 // TX VI Queue Descriptor Address
++#define REG_BEQ_DESA 0x0330 // TX BE Queue Descriptor Address
++#define REG_BKQ_DESA 0x0338 // TX BK Queue Descriptor Address
++#define REG_RX_DESA 0x0340 // RX Queue Descriptor Address
++#define REG_DBI 0x0348 // Backdoor REG for Access Configuration
++//sherry added for DBI Read/Write 20091126
++#define REG_DBI_WDATA 0x0348 // Backdoor REG for Access Configuration
++#define REG_DBI_RDATA 0x034C //Backdoor REG for Access Configuration
++#define REG_DBI_CTRL 0x0350 //Backdoor REG for Access Configuration
++#define REG_DBI_FLAG 0x0352 //Backdoor REG for Access Configuration#define REG_MDIO 0x0354 // MDIO for Access PCIE PHY
++#define REG_MDIO 0x0354 // MDIO for Access PCIE PHY
++#define REG_DBG_SEL 0x0360 // Debug Selection Register
++#define REG_PCIE_HRPWM 0x0361 //PCIe RPWM
++#define REG_PCIE_HCPWM 0x0363 //PCIe CPWM
++#define REG_UART_CTRL 0x0364 // UART Control
++#define REG_UART_TX_DESA 0x0370 // UART TX Descriptor Address
++#define REG_UART_RX_DESA 0x0378 // UART Rx Descriptor Address
++
++
++// spec version 11
++//-----------------------------------------------------
++//
++// 0x0400h ~ 0x047Fh Protocol Configuration
++//
++//-----------------------------------------------------
++#define REG_VOQ_INFORMATION 0x0400
++#define REG_VIQ_INFORMATION 0x0404
++#define REG_BEQ_INFORMATION 0x0408
++#define REG_BKQ_INFORMATION 0x040C
++#define REG_MGQ_INFORMATION 0x0410
++#define REG_HGQ_INFORMATION 0x0414
++#define REG_BCNQ_INFORMATION 0x0418
++
++
++#define REG_CPU_MGQ_INFORMATION 0x041C
++#define REG_FWHW_TXQ_CTRL 0x0420
++#define REG_HWSEQ_CTRL 0x0423
++#define REG_TXPKTBUF_BCNQ_BDNY 0x0424
++#define REG_TXPKTBUF_MGQ_BDNY 0x0425
++#define REG_LIFETIME_EN 0x0426
++#define REG_MULTI_BCNQ_OFFSET 0x0427
++#define REG_SPEC_SIFS 0x0428
++#define REG_RL 0x042A
++#define REG_DARFRC 0x0430
++#define REG_RARFRC 0x0438
++#define REG_RRSR 0x0440
++#define REG_ARFR0 0x0444
++#define REG_ARFR1 0x0448
++#define REG_ARFR2 0x044C
++#define REG_ARFR3 0x0450
++#define REG_AGGLEN_LMT 0x0458
++#define REG_AMPDU_MIN_SPACE 0x045C
++#define REG_TXPKTBUF_WMAC_LBK_BF_HD 0x045D
++#define REG_FAST_EDCA_CTRL 0x0460
++#define REG_RD_RESP_PKT_TH 0x0463
++#define REG_INIRTS_RATE_SEL 0x0480
++#define REG_INIDATA_RATE_SEL 0x0484
++
++//#define REG_FW_TSF_SYNC_CNT 0x04A0
++#define REG_FW_RESET_TSF_CNT_1 0x05FC
++#define REG_FW_RESET_TSF_CNT_0 0x05FD
++#define REG_FW_BCN_DIS_CNT 0x05FE
++
++#define REG_POWER_STATUS 0x04A4
++#define REG_POWER_STAGE1 0x04B4
++#define REG_POWER_STAGE2 0x04B8
++#define REG_PKT_VO_VI_LIFE_TIME 0x04C0
++#define REG_PKT_BE_BK_LIFE_TIME 0x04C2
++#define REG_STBC_SETTING 0x04C4
++#define REG_PROT_MODE_CTRL 0x04C8
++#define REG_MAX_AGGR_NUM 0x04CA
++#define REG_RTS_MAX_AGGR_NUM 0x04CB
++#define REG_BAR_MODE_CTRL 0x04CC
++#define REG_RA_TRY_RATE_AGG_LMT 0x04CF
++#define REG_EARLY_MODE_CONTROL 0x04D0
++#define REG_NQOS_SEQ 0x04DC
++#define REG_QOS_SEQ 0x04DE
++#define REG_NEED_CPU_HANDLE 0x04E0
++#define REG_PKT_LOSE_RPT 0x04E1
++#define REG_PTCL_ERR_STATUS 0x04E2
++#define REG_DUMMY 0x04FC
++
++
++
++//-----------------------------------------------------
++//
++// 0x0500h ~ 0x05FFh EDCA Configuration
++//
++//-----------------------------------------------------
++#define REG_EDCA_VO_PARAM 0x0500
++#define REG_EDCA_VI_PARAM 0x0504
++#define REG_EDCA_BE_PARAM 0x0508
++#define REG_EDCA_BK_PARAM 0x050C
++#define REG_BCNTCFG 0x0510
++#define REG_PIFS 0x0512
++#define REG_RDG_PIFS 0x0513
++#define REG_SIFS_CTX 0x0514
++#define REG_SIFS_TRX 0x0516
++#define REG_TSFTR_SYN_OFFSET 0x0518
++#define REG_AGGR_BREAK_TIME 0x051A
++#define REG_SLOT 0x051B
++#define REG_TX_PTCL_CTRL 0x0520
++#define REG_TXPAUSE 0x0522
++#define REG_DIS_TXREQ_CLR 0x0523
++#define REG_RD_CTRL 0x0524
++#define REG_TBTT_PROHIBIT 0x0540
++#define REG_RD_NAV_NXT 0x0544
++#define REG_NAV_PROT_LEN 0x0546
++#define REG_BCN_CTRL 0x0550
++#define REG_BCN_CTRL_1 0x0551
++#define REG_MBID_NUM 0x0552
++#define REG_DUAL_TSF_RST 0x0553
++#define REG_BCN_INTERVAL 0x0554 // The same as REG_MBSSID_BCN_SPACE
++#define REG_MBSSID_BCN_SPACE 0x0554
++#define REG_DRVERLYINT 0x0558
++#define REG_BCNDMATIM 0x0559
++#define REG_ATIMWND 0x055A
++#define REG_USTIME_TSF 0x055C
++#define REG_BCN_MAX_ERR 0x055D
++#define REG_RXTSF_OFFSET_CCK 0x055E
++#define REG_RXTSF_OFFSET_OFDM 0x055F
++#define REG_TSFTR 0x0560
++#define REG_TSFTR1 0x0568
++#define REG_INIT_TSFTR 0x0564
++#define REG_ATIMWND_1 0x0570
++#define REG_PSTIMER 0x0580
++#define REG_TIMER0 0x0584
++#define REG_TIMER1 0x0588
++#define REG_ACMHWCTRL 0x05C0
++#define REG_ACMRSTCTRL 0x05C1
++#define REG_ACMAVG 0x05C2
++#define REG_VO_ADMTIME 0x05C4
++#define REG_VI_ADMTIME 0x05C6
++#define REG_BE_ADMTIME 0x05C8
++#define REG_EDCA_RANDOM_GEN 0x05CC
++#define REG_SCH_TXCMD 0x05D0
++
++#define REG_DMC 0x05F0 //Dual MAC Co-Existence Register
++
++
++//-----------------------------------------------------
++//
++// 0x0600h ~ 0x07FFh WMAC Configuration
++//
++//-----------------------------------------------------
++#define REG_APSD_CTRL 0x0600
++#define REG_BWOPMODE 0x0603
++#define REG_TCR 0x0604
++#define REG_RCR 0x0608
++#define REG_RX_PKT_LIMIT 0x060C
++#define REG_RX_DLK_TIME 0x060D
++#define REG_RX_DRVINFO_SZ 0x060F
++
++#define REG_MACID 0x0610
++#define REG_BSSID 0x0618
++#define REG_MAR 0x0620
++#define REG_MBIDCAMCFG 0x0628
++
++#define REG_USTIME_EDCA 0x0638
++#define REG_MAC_SPEC_SIFS 0x063A
++#define REG_RESP_SIFS_CCK 0x063C
++#define REG_RESP_SIFS_OFDM 0x063E
++#define REG_ACKTO 0x0640
++#define REG_CTS2TO 0x0641
++#define REG_EIFS 0x0642
++
++
++//WMA, BA, CCX
++#define REG_NAV_CTRL 0x0650
++#define REG_BACAMCMD 0x0654
++#define REG_BACAMCONTENT 0x0658
++#define REG_LBDLY 0x0660
++#define REG_FWDLY 0x0661
++#define REG_RXERR_RPT 0x0664
++#define REG_WMAC_TRXPTCL_CTL 0x0668
++
++
++// Security
++#define REG_CAMCMD 0x0670
++#define REG_CAMWRITE 0x0674
++#define REG_CAMREAD 0x0678
++#define REG_CAMDBG 0x067C
++#define REG_SECCFG 0x0680
++
++// Power
++#define REG_WOW_CTRL 0x0690
++#define REG_PSSTATUS 0x0691
++#define REG_PS_RX_INFO 0x0692
++#define REG_LPNAV_CTRL 0x0694
++#define REG_WKFMCAM_CMD 0x0698
++#define REG_WKFMCAM_RWD 0x069C
++#define REG_RXFLTMAP0 0x06A0
++#define REG_RXFLTMAP1 0x06A2
++#define REG_RXFLTMAP2 0x06A4
++#define REG_BCN_PSR_RPT 0x06A8
++#define REG_CALB32K_CTRL 0x06AC
++#define REG_PKT_MON_CTRL 0x06B4
++#define REG_BT_COEX_TABLE 0x06C0
++#define REG_WMAC_RESP_TXINFO 0x06D8
++
++#define REG_MACID1 0x0700
++#define REG_BSSID1 0x0708
++
++//-----------------------------------------------------
++//
++// 0xFE00h ~ 0xFE55h USB Configuration
++//
++//-----------------------------------------------------
++#define REG_USB_INFO 0xFE17
++#define REG_USB_SPECIAL_OPTION 0xFE55
++#define REG_USB_DMA_AGG_TO 0xFE5B
++#define REG_USB_AGG_TO 0xFE5C
++#define REG_USB_AGG_TH 0xFE5D
++
++// for 92DU high_Queue low_Queue Normal_Queue select
++#define REG_USB_High_NORMAL_Queue_Select_MAC0 0xFE44
++//#define REG_USB_LOW_Queue_Select_MAC0 0xFE45
++#define REG_USB_High_NORMAL_Queue_Select_MAC1 0xFE47
++//#define REG_USB_LOW_Queue_Select_MAC1 0xFE48
++
++// For test chip
++#define REG_TEST_USB_TXQS 0xFE48
++#define REG_TEST_SIE_VID 0xFE60 // 0xFE60~0xFE61
++#define REG_TEST_SIE_PID 0xFE62 // 0xFE62~0xFE63
++#define REG_TEST_SIE_OPTIONAL 0xFE64
++#define REG_TEST_SIE_CHIRP_K 0xFE65
++#define REG_TEST_SIE_PHY 0xFE66 // 0xFE66~0xFE6B
++#define REG_TEST_SIE_MAC_ADDR 0xFE70 // 0xFE70~0xFE75
++#define REG_TEST_SIE_STRING 0xFE80 // 0xFE80~0xFEB9
++
++
++// For normal chip
++#define REG_NORMAL_SIE_VID 0xFE60 // 0xFE60~0xFE61
++#define REG_NORMAL_SIE_PID 0xFE62 // 0xFE62~0xFE63
++#define REG_NORMAL_SIE_OPTIONAL 0xFE64
++#define REG_NORMAL_SIE_EP 0xFE65 // 0xFE65~0xFE67
++#define REG_NORMAL_SIE_PHY 0xFE68 // 0xFE68~0xFE6B
++#define REG_NORMAL_SIE_MAC_ADDR 0xFE70 // 0xFE70~0xFE75
++#define REG_NORMAL_SIE_STRING 0xFE80 // 0xFE80~0xFEDF
++
++
++//-----------------------------------------------------
++//
++// Redifine 8192C register definition for compatibility
++//
++//-----------------------------------------------------
++
++// TODO: use these definition when using REG_xxx naming rule.
++// NOTE: DO NOT Remove these definition. Use later.
++
++#define SYS_ISO_CTRL REG_SYS_ISO_CTRL // System Isolation Interface Control.
++#define SYS_FUNC_EN REG_SYS_FUNC_EN // System Function Enable.
++#define SYS_CLK REG_SYS_CLKR
++#define CR9346 REG_9346CR // 93C46/93C56 Command Register.
++#define EFUSE_CTRL REG_EFUSE_CTRL // E-Fuse Control.
++#define EFUSE_TEST REG_EFUSE_TEST // E-Fuse Test.
++#define MSR (REG_CR + 2) // Media Status register
++#define ISR REG_HISR
++#define TSFR REG_TSFTR // Timing Sync Function Timer Register.
++
++#define MACIDR0 REG_MACID // MAC ID Register, Offset 0x0050-0x0053
++#define MACIDR4 (REG_MACID + 4) // MAC ID Register, Offset 0x0054-0x0055
++
++#define PBP REG_PBP
++
++// Redifine MACID register, to compatible prior ICs.
++#define IDR0 MACIDR0
++#define IDR4 MACIDR4
++
++
++//
++// 9. Security Control Registers (Offset: )
++//
++#define RWCAM REG_CAMCMD //IN 8190 Data Sheet is called CAMcmd
++#define WCAMI REG_CAMWRITE // Software write CAM input content
++#define RCAMO REG_CAMREAD // Software read/write CAM config
++#define CAMDBG REG_CAMDBG
++#define SECR REG_SECCFG //Security Configuration Register
++
++// Unused register
++#define UnusedRegister 0x1BF
++#define DCAM UnusedRegister
++#define PSR UnusedRegister
++#define BBAddr UnusedRegister
++#define PhyDataR UnusedRegister
++
++#define InvalidBBRFValue 0x12345678
++
++// Min Spacing related settings.
++#define MAX_MSS_DENSITY_2T 0x13
++#define MAX_MSS_DENSITY_1T 0x0A
++
++//----------------------------------------------------------------------------
++// 8192C Cmd9346CR bits (Offset 0xA, 16bit)
++//----------------------------------------------------------------------------
++#define CmdEEPROM_En BIT5 // EEPROM enable when set 1
++#define CmdEERPOMSEL BIT4 // System EEPROM select, 0: boot from E-FUSE, 1: The EEPROM used is 9346
++#define Cmd9346CR_9356SEL BIT4
++#define AutoLoadEEPROM (CmdEEPROM_En|CmdEERPOMSEL)
++#define AutoLoadEFUSE CmdEEPROM_En
++
++// 8192C GPIO MUX Configuration Register (offset 0x40, 4 byte)
++//----------------------------------------------------------------------------
++#define GPIOSEL_GPIO 0
++#define GPIOSEL_ENBT BIT5
++
++//----------------------------------------------------------------------------
++// 8192C GPIO PIN Control Register (offset 0x44, 4 byte)
++//----------------------------------------------------------------------------
++#define GPIO_IN REG_GPIO_PIN_CTRL // GPIO pins input value
++#define GPIO_OUT (REG_GPIO_PIN_CTRL+1) // GPIO pins output value
++#define GPIO_IO_SEL (REG_GPIO_PIN_CTRL+2) // GPIO pins output enable when a bit is set to "1"; otherwise, input is configured.
++#define GPIO_MOD (REG_GPIO_PIN_CTRL+3)
++
++
++//----------------------------------------------------------------------------
++// 8192C (MSR) Media Status Register (Offset 0x4C, 8 bits)
++//----------------------------------------------------------------------------
++/*
++Network Type
++00: No link
++01: Link in ad hoc network
++10: Link in infrastructure network
++11: AP mode
++Default: 00b.
++*/
++#define MSR_NOLINK 0x00
++#define MSR_ADHOC 0x01
++#define MSR_INFRA 0x02
++#define MSR_AP 0x03
++
++//
++// 6. Adaptive Control Registers (Offset: 0x0160 - 0x01CF)
++//
++//----------------------------------------------------------------------------
++// 8192C Response Rate Set Register (offset 0x181, 24bits)
++//----------------------------------------------------------------------------
++#define RRSR_RSC_OFFSET 21
++#define RRSR_SHORT_OFFSET 23
++#define RRSR_RSC_BW_40M 0x600000
++#define RRSR_RSC_UPSUBCHNL 0x400000
++#define RRSR_RSC_LOWSUBCHNL 0x200000
++#define RRSR_SHORT 0x800000
++#define RRSR_1M BIT0
++#define RRSR_2M BIT1
++#define RRSR_5_5M BIT2
++#define RRSR_11M BIT3
++#define RRSR_6M BIT4
++#define RRSR_9M BIT5
++#define RRSR_12M BIT6
++#define RRSR_18M BIT7
++#define RRSR_24M BIT8
++#define RRSR_36M BIT9
++#define RRSR_48M BIT10
++#define RRSR_54M BIT11
++#define RRSR_MCS0 BIT12
++#define RRSR_MCS1 BIT13
++#define RRSR_MCS2 BIT14
++#define RRSR_MCS3 BIT15
++#define RRSR_MCS4 BIT16
++#define RRSR_MCS5 BIT17
++#define RRSR_MCS6 BIT18
++#define RRSR_MCS7 BIT19
++#define BRSR_AckShortPmb BIT23
++// CCK ACK: use Short Preamble or not
++
++
++//----------------------------------------------------------------------------
++// 8192C Rate Definition
++//----------------------------------------------------------------------------
++//CCK
++#define RATR_1M 0x00000001
++#define RATR_2M 0x00000002
++#define RATR_55M 0x00000004
++#define RATR_11M 0x00000008
++//OFDM
++#define RATR_6M 0x00000010
++#define RATR_9M 0x00000020
++#define RATR_12M 0x00000040
++#define RATR_18M 0x00000080
++#define RATR_24M 0x00000100
++#define RATR_36M 0x00000200
++#define RATR_48M 0x00000400
++#define RATR_54M 0x00000800
++//MCS 1 Spatial Stream
++#define RATR_MCS0 0x00001000
++#define RATR_MCS1 0x00002000
++#define RATR_MCS2 0x00004000
++#define RATR_MCS3 0x00008000
++#define RATR_MCS4 0x00010000
++#define RATR_MCS5 0x00020000
++#define RATR_MCS6 0x00040000
++#define RATR_MCS7 0x00080000
++//MCS 2 Spatial Stream
++#define RATR_MCS8 0x00100000
++#define RATR_MCS9 0x00200000
++#define RATR_MCS10 0x00400000
++#define RATR_MCS11 0x00800000
++#define RATR_MCS12 0x01000000
++#define RATR_MCS13 0x02000000
++#define RATR_MCS14 0x04000000
++#define RATR_MCS15 0x08000000
++
++//----------------------------------------------------------------------------
++// 8192C BW_OPMODE bits (Offset 0x203, 8bit)
++//----------------------------------------------------------------------------
++#define BW_OPMODE_20MHZ BIT2
++#define BW_OPMODE_5G BIT1
++#define BW_OPMODE_11J BIT0
++
++
++//----------------------------------------------------------------------------
++// 8192C CAM Config Setting (offset 0x250, 1 byte)
++//----------------------------------------------------------------------------
++#define CAM_VALID BIT15
++#define CAM_NOTVALID 0x0000
++#define CAM_USEDK BIT5
++
++#define CAM_CONTENT_COUNT 8
++
++#define CAM_NONE 0x0
++#define CAM_WEP40 0x01
++#define CAM_TKIP 0x02
++#define CAM_AES 0x04
++#define CAM_WEP104 0x05
++#define CAM_SMS4 0x6
++
++
++#define TOTAL_CAM_ENTRY 32
++#define HALF_CAM_ENTRY 16
++
++#define CAM_CONFIG_USEDK _TRUE
++#define CAM_CONFIG_NO_USEDK _FALSE
++
++#define CAM_WRITE BIT16
++#define CAM_READ 0x00000000
++#define CAM_POLLINIG BIT31
++
++#define SCR_UseDK 0x01
++#define SCR_TxSecEnable 0x02
++#define SCR_RxSecEnable 0x04
++
++
++//
++// 12. Host Interrupt Status Registers (Offset: 0x0300 - 0x030F)
++//
++//----------------------------------------------------------------------------
++// 8190 IMR/ISR bits (offset 0xfd, 8bits)
++//----------------------------------------------------------------------------
++#define IMR8190_DISABLED 0x0
++// IMR DW0 Bit 0-31
++#define IMR_BCNDMAINT6 BIT31 // Beacon DMA Interrupt 6
++#define IMR_BCNDMAINT5 BIT30 // Beacon DMA Interrupt 5
++#define IMR_BCNDMAINT4 BIT29 // Beacon DMA Interrupt 4
++#define IMR_BCNDMAINT3 BIT28 // Beacon DMA Interrupt 3
++#define IMR_BCNDMAINT2 BIT27 // Beacon DMA Interrupt 2
++#define IMR_BCNDMAINT1 BIT26 // Beacon DMA Interrupt 1
++#define IMR_BCNDOK8 BIT25 // Beacon Queue DMA OK Interrup 8
++#define IMR_BCNDOK7 BIT24 // Beacon Queue DMA OK Interrup 7
++#define IMR_BCNDOK6 BIT23 // Beacon Queue DMA OK Interrup 6
++#define IMR_BCNDOK5 BIT22 // Beacon Queue DMA OK Interrup 5
++#define IMR_BCNDOK4 BIT21 // Beacon Queue DMA OK Interrup 4
++#define IMR_BCNDOK3 BIT20 // Beacon Queue DMA OK Interrup 3
++#define IMR_BCNDOK2 BIT19 // Beacon Queue DMA OK Interrup 2
++#define IMR_BCNDOK1 BIT18 // Beacon Queue DMA OK Interrup 1
++#define IMR_TIMEOUT2 BIT17 // Timeout interrupt 2
++#define IMR_TIMEOUT1 BIT16 // Timeout interrupt 1
++#define IMR_TXFOVW BIT15 // Transmit FIFO Overflow
++#define IMR_PSTIMEOUT BIT14 // Power save time out interrupt
++#define IMR_BcnInt BIT13 // Beacon DMA Interrupt 0
++#define IMR_RXFOVW BIT12 // Receive FIFO Overflow
++#define IMR_RDU BIT11 // Receive Descriptor Unavailable
++#define IMR_ATIMEND BIT10 // For 92C,ATIM Window End Interrupt
++#define IMR_BDOK BIT9 // Beacon Queue DMA OK Interrup
++#define IMR_HIGHDOK BIT8 // High Queue DMA OK Interrupt
++#define IMR_TBDOK BIT7 // Transmit Beacon OK interrup
++#define IMR_MGNTDOK BIT6 // Management Queue DMA OK Interrupt
++#define IMR_TBDER BIT5 // For 92C,Transmit Beacon Error Interrupt
++#define IMR_BKDOK BIT4 // AC_BK DMA OK Interrupt
++#define IMR_BEDOK BIT3 // AC_BE DMA OK Interrupt
++#define IMR_VIDOK BIT2 // AC_VI DMA OK Interrupt
++#define IMR_VODOK BIT1 // AC_VO DMA Interrupt
++#define IMR_ROK BIT0 // Receive DMA OK Interrupt
++
++// 13. Host Interrupt Status Extension Register (Offset: 0x012C-012Eh)
++#define IMR_TXERR BIT11
++#define IMR_RXERR BIT10
++#define IMR_C2HCMD BIT9
++#define IMR_CPWM BIT8
++//RSVD [2-7]
++#define IMR_OCPINT BIT1
++#define IMR_WLANOFF BIT0
++
++
++
++//----------------------------------------------------------------------------
++// 8192D EFUSE
++//----------------------------------------------------------------------------
++#define HWSET_MAX_SIZE 256
++
++//----------------------------------------------------------------------------
++// 8192C EEPROM/EFUSE share register definition.
++//----------------------------------------------------------------------------
++
++//
++// Default Value for EEPROM or EFUSE!!!
++//
++#define EEPROM_Default_TSSI 0x0
++#define EEPROM_Default_TxPowerDiff 0x0
++#define EEPROM_Default_CrystalCap 0x0 //92D default 0x0
++#define EEPROM_Default_BoardType 0x02 // Default: 2X2, RTL8192CE(QFPN68)
++#define EEPROM_Default_TxPower 0x1010
++#define EEPROM_Default_HT2T_TxPwr 0x10
++
++#define EEPROM_Default_LegacyHTTxPowerDiff 0x4
++#define EEPROM_Default_ThermalMeter 0x12
++
++#define EEPROM_Default_AntTxPowerDiff 0x0
++//#define EEPROM_Default_TxPwDiff_CrystalCap 0x5
++#define EEPROM_Default_TxPowerLevel_2G 0x2C
++#define EEPROM_Default_TxPowerLevel_5G 0x22
++
++#define EEPROM_Default_HT40_2SDiff 0x0
++#define EEPROM_Default_HT20_Diff 2 // HT20<->40 default Tx Power Index Difference
++#define EEPROM_Default_LegacyHTTxPowerDiff 0x4 //OFDM Tx Power index diff
++#define EEPROM_Default_HT40_PwrMaxOffset 0
++#define EEPROM_Default_HT20_PwrMaxOffset 0
++
++// For debug
++#define EEPROM_Default_PID 0x1234
++#define EEPROM_Default_VID 0x5678
++#define EEPROM_Default_CustomerID 0xAB
++#define EEPROM_Default_SubCustomerID 0xCD
++#define EEPROM_Default_Version 0
++
++#define EEPROM_Default_externalPA_C9 0x00
++#define EEPROM_Default_externalPA_CC 0xFF
++#define EEPROM_Default_internalPA_SP3T_C9 0xAA
++#define EEPROM_Default_internalPA_SP3T_CC 0xAF
++#define EEPROM_Default_internalPA_SPDT_C9 0xAA
++#ifdef CONFIG_PCI_HCI
++#define EEPROM_Default_internalPA_SPDT_CC 0xA0
++#else
++#define EEPROM_Default_internalPA_SPDT_CC 0xFA
++#endif
++
++#define EEPROM_CHANNEL_PLAN_FCC 0x0
++#define EEPROM_CHANNEL_PLAN_IC 0x1
++#define EEPROM_CHANNEL_PLAN_ETSI 0x2
++#define EEPROM_CHANNEL_PLAN_SPAIN 0x3
++#define EEPROM_CHANNEL_PLAN_FRANCE 0x4
++#define EEPROM_CHANNEL_PLAN_MKK 0x5
++#define EEPROM_CHANNEL_PLAN_MKK1 0x6
++#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7
++#define EEPROM_CHANNEL_PLAN_TELEC 0x8
++#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9
++#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA
++#define EEPROM_CHANNEL_PLAN_NCC 0xB
++#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80
++
++
++#define EEPROM_CID_DEFAULT 0x0
++#define EEPROM_CID_TOSHIBA 0x4
++#define EEPROM_CID_CCX 0x10 // CCX test. By Bruce, 2009-02-25.
++#define EEPROM_CID_QMI 0x0D
++#define EEPROM_CID_WHQL 0xFE // added by chiyoko for dtm, 20090108
++
++
++#define RTL8192_EEPROM_ID 0x8129
++#define EEPROM_WAPI_SUPPORT 0x78
++
++
++#ifdef CONFIG_PCI_HCI
++#define RT_IBSS_INT_MASKS (IMR_BcnInt | IMR_TBDOK | IMR_TBDER)
++#define RT_AC_INT_MASKS (IMR_VIDOK | IMR_VODOK | IMR_BEDOK|IMR_BKDOK)
++#define RT_BSS_INT_MASKS (RT_IBSS_INT_MASKS)
++
++#define RTL8190_EEPROM_ID 0x8129 // 0-1
++#define EEPROM_HPON 0x02 // LDO settings.2-5
++#define EEPROM_CLK 0x06 // Clock settings.6-7
++#define EEPROM_MAC_FUNCTION 0x08 // SE Test mode.8
++
++#define EEPROM_VID 0x28 // SE Vendor ID.A-B
++#define EEPROM_DID 0x2A // SE Device ID. C-D
++#define EEPROM_SVID 0x2C // SE Vendor ID.E-F
++#define EEPROM_SMID 0x2E // SE PCI Subsystem ID. 10-11
++
++#define EEPROM_MAC_ADDR 0x16 // SEMAC Address. 12-17
++#define EEPROM_MAC_ADDR_MAC0_92D 0x55
++#define EEPROM_MAC_ADDR_MAC1_92D 0x5B
++//----------------------------------------------------------------
++// 2.4G band Tx power index setting
++#define EEPROM_CCK_TX_PWR_INX_2G 0x61
++#define EEPROM_HT40_1S_TX_PWR_INX_2G 0x67
++#define EEPROM_HT40_2S_TX_PWR_INX_DIFF_2G 0x6D
++#define EEPROM_HT20_TX_PWR_INX_DIFF_2G 0x70
++#define EEPROM_OFDM_TX_PWR_INX_DIFF_2G 0x73
++#define EEPROM_HT40_MAX_PWR_OFFSET_2G 0x76
++#define EEPROM_HT20_MAX_PWR_OFFSET_2G 0x79
++
++//5GL channel 32-64
++#define EEPROM_HT40_1S_TX_PWR_INX_5GL 0x7C
++#define EEPROM_HT40_2S_TX_PWR_INX_DIFF_5GL 0x82
++#define EEPROM_HT20_TX_PWR_INX_DIFF_5GL 0x85
++#define EEPROM_OFDM_TX_PWR_INX_DIFF_5GL 0x88
++#define EEPROM_HT40_MAX_PWR_OFFSET_5GL 0x8B
++#define EEPROM_HT20_MAX_PWR_OFFSET_5GL 0x8E
++
++//5GM channel 100-140
++#define EEPROM_HT40_1S_TX_PWR_INX_5GM 0x91
++#define EEPROM_HT40_2S_TX_PWR_INX_DIFF_5GM 0x97
++#define EEPROM_HT20_TX_PWR_INX_DIFF_5GM 0x9A
++#define EEPROM_OFDM_TX_PWR_INX_DIFF_5GM 0x9D
++#define EEPROM_HT40_MAX_PWR_OFFSET_5GM 0xA0
++#define EEPROM_HT20_MAX_PWR_OFFSET_5GM 0xA3
++
++//5GH channel 149-165
++#define EEPROM_HT40_1S_TX_PWR_INX_5GH 0xA6
++#define EEPROM_HT40_2S_TX_PWR_INX_DIFF_5GH 0xAC
++#define EEPROM_HT20_TX_PWR_INX_DIFF_5GH 0xAF
++#define EEPROM_OFDM_TX_PWR_INX_DIFF_5GH 0xB2
++#define EEPROM_HT40_MAX_PWR_OFFSET_5GH 0xB5
++#define EEPROM_HT20_MAX_PWR_OFFSET_5GH 0xB8
++
++#define EEPROM_CHANNEL_PLAN 0xBB // Map of supported channels.
++#define EEPROM_IQK_DELTA 0xBC
++#define EEPROM_LCK_DELTA 0xBC
++#define EEPROM_XTAL_K 0xBD //[7:5]
++#define EEPROM_TSSI_A_5G 0xBE
++#define EEPROM_TSSI_B_5G 0xBF
++#define EEPROM_TSSI_AB_5G 0xC0
++#define EEPROM_THERMAL_METER 0xC3 //[4:0]
++#define EEPROM_PATHDIV 0xC4
++#define EEPROM_RF_OPT1 0xC4
++#define EEPROM_RF_OPT2 0xC5
++#define EEPROM_RF_OPT3 0xC6
++#define EEPROM_RF_OPT4 0xC7
++#define EEPROM_RF_OPT5 0xC8
++#define EEPROM_RF_OPT6 0xC9
++#define EEPROM_VERSION 0xCA
++#define EEPROM_CUSTOMER_ID 0xCB
++#define EEPROM_RF_OPT7 0xCC
++
++#define EEPROM_WIDIPAIRING_ADDR 0xF0
++#define EEPROM_WIDIPAIRING_KEY 0xF6
++
++#define EEPROM_DEF_PART_NO 0x3FD //Byte
++#define EEPROME_CHIP_VERSION_L 0x3FF
++#define EEPROME_CHIP_VERSION_H 0x3FE
++#endif
++
++#ifdef CONFIG_USB_HCI
++#define RTL8190_EEPROM_ID 0x8129 // 0-1
++#define EEPROM_HPON 0x02 // LDO settings.2-5
++#define EEPROM_CLK 0x06 // Clock settings.6-7
++#define EEPROM_MAC_FUNCTION 0x08 // SE Test mode.8
++
++#define EEPROM_VID 0xC // SE Vendor ID.A-B
++#define EEPROM_PID 0xE // SE Device ID. C-D
++#define EEPROM_ENDPOINT_SETTING 0x10
++#ifdef CONFIG_WOWLAN
++#define EEPROM_Option_Setting 0x11
++#endif // CONFIG_WOWLAN
++#define EEPROM_CHIRP_K 0x12 // Changed
++#define EEPROM_USB_PHY 0x13 // Changed
++#define EEPROM_NORMAL_BoardType EEPROM_RF_OPT1 //[7:5]
++#define EEPROM_MAC_ADDR 0x16 // SEMAC Address. 12-17
++#define EEPROM_STRING 0x1F
++#define EEPROM_SUBCUSTOMER_ID 0x59
++
++#define EEPROM_MAC_ADDR_MAC0_92D 0x19
++#define EEPROM_MAC_ADDR_MAC1_92D 0x5B
++//----------------------------------------------------------------
++// 2.4G band Tx power index setting
++#define EEPROM_CCK_TX_PWR_INX_2G 0x61
++#define EEPROM_HT40_1S_TX_PWR_INX_2G 0x67
++#define EEPROM_HT40_2S_TX_PWR_INX_DIFF_2G 0x6D
++#define EEPROM_HT20_TX_PWR_INX_DIFF_2G 0x70
++#define EEPROM_OFDM_TX_PWR_INX_DIFF_2G 0x73
++#define EEPROM_HT40_MAX_PWR_OFFSET_2G 0x76
++#define EEPROM_HT20_MAX_PWR_OFFSET_2G 0x79
++
++//5GL channel 32-64
++#define EEPROM_HT40_1S_TX_PWR_INX_5GL 0x7C
++#define EEPROM_HT40_2S_TX_PWR_INX_DIFF_5GL 0x82
++#define EEPROM_HT20_TX_PWR_INX_DIFF_5GL 0x85
++#define EEPROM_OFDM_TX_PWR_INX_DIFF_5GL 0x88
++#define EEPROM_HT40_MAX_PWR_OFFSET_5GL 0x8B
++#define EEPROM_HT20_MAX_PWR_OFFSET_5GL 0x8E
++
++//5GM channel 100-140
++#define EEPROM_HT40_1S_TX_PWR_INX_5GM 0x91
++#define EEPROM_HT40_2S_TX_PWR_INX_DIFF_5GM 0x97
++#define EEPROM_HT20_TX_PWR_INX_DIFF_5GM 0x9A
++#define EEPROM_OFDM_TX_PWR_INX_DIFF_5GM 0x9D
++#define EEPROM_HT40_MAX_PWR_OFFSET_5GM 0xA0
++#define EEPROM_HT20_MAX_PWR_OFFSET_5GM 0xA3
++
++//5GH channel 149-165
++#define EEPROM_HT40_1S_TX_PWR_INX_5GH 0xA6
++#define EEPROM_HT40_2S_TX_PWR_INX_DIFF_5GH 0xAC
++#define EEPROM_HT20_TX_PWR_INX_DIFF_5GH 0xAF
++#define EEPROM_OFDM_TX_PWR_INX_DIFF_5GH 0xB2
++#define EEPROM_HT40_MAX_PWR_OFFSET_5GH 0xB5
++#define EEPROM_HT20_MAX_PWR_OFFSET_5GH 0xB8
++
++#define EEPROM_CHANNEL_PLAN 0xBB // Map of supported channels.
++#define EEPROM_TEST_CHANNEL_PLAN 0xBB
++#define EEPROM_IQK_DELTA 0xBC
++#define EEPROM_LCK_DELTA 0xBC
++#define EEPROM_XTAL_K 0xBD //[7:5]
++#define EEPROM_TSSI_A_5G 0xBE
++#define EEPROM_TSSI_B_5G 0xBF
++#define EEPROM_TSSI_AB_5G 0xC0
++#define EEPROM_THERMAL_METER 0xC3 //[4:0]
++#define EEPROM_RF_OPT1 0xC4
++#define EEPROM_RF_OPT2 0xC5
++#define EEPROM_RF_OPT3 0xC6
++#define EEPROM_RF_OPT4 0xC7
++#define EEPROM_RF_OPT5 0xC8
++#define EEPROM_RF_OPT6 0xC9
++#define EEPROM_VERSION 0xCA
++#define EEPROM_CUSTOMER_ID 0xCB
++#define EEPROM_RF_OPT7 0xCC
++
++#define EEPROM_DEF_PART_NO 0x3FD //Byte
++#define EEPROME_CHIP_VERSION_L 0x3FF
++#define EEPROME_CHIP_VERSION_H 0x3FE
++
++//-------------------------------------------------------------
++// EEPROM content definitions
++//-------------------------------------------------------------
++#define OS_LINK_SPEED_NORMAL_MASK BIT3 | BIT2
++#define OS_LINK_SPEED_TEST_MASK BIT3 | BIT4
++
++#define BOARD_TYPE_NORMAL_MASK 0xE0
++#define BOARD_TYPE_TEST_MASK 0xF
++
++#define BT_COEXISTENCE_TEST BIT4
++#define BT_COEXISTENCE_NORMAL BIT5
++
++#define BT_CO_SHIFT_TEST 4
++#define BT_CO_SHIFT_NORMAL 5
++
++#define EP_NUMBER_MASK_TEST 0x30 //bit 4:5 0Eh
++#define EP_NUMBER_SHIFT_TEST 4
++
++#define USB_PHY_PARA_SIZE_TEST 6
++#define USB_PHY_PARA_SIZE_NORMAL 4
++
++//-------------------------------------------------------------
++// EEPROM default value definitions
++//-------------------------------------------------------------
++// Use 0xABCD instead of 0x8192 for debug
++#define EEPROM_DEF_ID_0 0xCD // Byte 0x00
++#define EEPROM_DEF_ID_1 0xAB // Byte 0x01
++
++#define EEPROM_DEF_RTK_RSV_A3 0x74 // Byte 0x03
++#define EEPROM_DEF_RTK_RSV_A4 0x6D // Byte 0x04
++#define EEPROM_DEF_RTK_RSV_A8 0xFF // Byte 0x08
++
++#define EEPROM_DEF_VID_0 0x0A // Byte 0x0A
++#define EEPROM_DEF_VID_1 0x0B
++
++#define EEPROM_DEF_PID_0 0x92 // Byte 0x0C
++#define EEPROM_DEF_PID_1 0x81
++
++
++#define EEPROM_TEST_DEF_USB_OPT 0x80 // Byte 0x0E
++#define EEPROM_NORMAL_DEF_USB_OPT 0x00 // Byte 0x0E
++
++#define EEPROM_DEF_CHIRPK 0x15 // Byte 0x0F
++
++#define EEPROM_DEF_USB_PHY_0 0x85 // Byte 0x10
++#define EEPROM_DEF_USB_PHY_1 0x62 // Byte 0x11
++#define EEPROM_DEF_USB_PHY_2 0x9E // Byte 0x12
++#define EEPROM_DEF_USB_PHY_3 0x06 // Byte 0x13
++
++#define EEPROM_DEF_TSSI_A 0x09 // Byte 0x78
++#define EEPROM_DEF_TSSI_B 0x09 // Byte 0x79
++
++
++#define EEPROM_DEF_THERMAL_METER 0x12 // Byte 0x7A
++
++
++#define EEPROM_USB_SN BIT(0)
++#define EEPROM_USB_REMOTE_WAKEUP BIT(1)
++#define EEPROM_USB_DEVICE_PWR BIT(2)
++#define EEPROM_EP_NUMBER (BIT(3)|BIT(4))
++
++#if 0
++#define EEPROM_CHANNEL_PLAN_FCC 0x0
++#define EEPROM_CHANNEL_PLAN_IC 0x1
++#define EEPROM_CHANNEL_PLAN_ETSI 0x2
++#define EEPROM_CHANNEL_PLAN_SPAIN 0x3
++#define EEPROM_CHANNEL_PLAN_FRANCE 0x4
++#define EEPROM_CHANNEL_PLAN_MKK 0x5
++#define EEPROM_CHANNEL_PLAN_MKK1 0x6
++#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7
++#define EEPROM_CHANNEL_PLAN_TELEC 0x8
++#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9
++#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA
++#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80
++
++#define EEPROM_CID_DEFAULT 0x0
++
++#define EEPROM_CID_WHQL 0xFE // added by chiyoko for dtm, 20090108
++
++
++#define EEPROM_CID_CCX 0x10 // CCX test. By Bruce, 2009-02-25.
++
++#endif
++#endif
++
++
++/*===================================================================
++=====================================================================
++Here the register defines are for 92C. When the define is as same with 92C,
++we will use the 92C's define for the consistency
++So the following defines for 92C is not entire!!!!!!
++=====================================================================
++=====================================================================*/
++/*
++Based on Datasheet V33---090401
++Register Summary
++Current IOREG MAP
++0x0000h ~ 0x00FFh System Configuration (256 Bytes)
++0x0100h ~ 0x01FFh MACTOP General Configuration (256 Bytes)
++0x0200h ~ 0x027Fh TXDMA Configuration (128 Bytes)
++0x0280h ~ 0x02FFh RXDMA Configuration (128 Bytes)
++0x0300h ~ 0x03FFh PCIE EMAC Reserved Region (256 Bytes)
++0x0400h ~ 0x04FFh Protocol Configuration (256 Bytes)
++0x0500h ~ 0x05FFh EDCA Configuration (256 Bytes)
++0x0600h ~ 0x07FFh WMAC Configuration (512 Bytes)
++0x2000h ~ 0x3FFFh 8051 FW Download Region (8196 Bytes)
++*/
++
++//----------------------------------------------------------------------------
++// 8192C (RCR) Receive Configuration Register (Offset 0x608, 32 bits)
++//----------------------------------------------------------------------------
++#define RCR_APPFCS BIT31 //WMAC append FCS after pauload
++#define RCR_APP_MIC BIT30 //
++#define RCR_APP_ICV BIT29 //
++#define RCR_APP_PHYST_RXFF BIT28 //
++#define RCR_APP_BA_SSN BIT27 //Accept BA SSN
++#define RCR_ENMBID BIT24 //Enable Multiple BssId.
++#define RCR_LSIGEN BIT23
++#define RCR_MFBEN BIT22
++#define RCR_HTC_LOC_CTRL BIT14 //MFC<--HTC=1 MFC-->HTC=0
++#define RCR_AMF BIT13 //Accept management type frame
++#define RCR_ACF BIT12 //Accept control type frame
++#define RCR_ADF BIT11 //Accept data type frame
++#define RCR_AICV BIT9 //Accept ICV error packet
++#define RCR_ACRC32 BIT8 //Accept CRC32 error packet
++#define RCR_CBSSID_BCN BIT7 //Accept BSSID match packet (Rx beacon, probe rsp)
++#define RCR_CBSSID_DATA BIT6 //Accept BSSID match packet (Data)
++#define RCR_CBSSID RCR_CBSSID_DATA //Accept BSSID match packet
++#define RCR_APWRMGT BIT5 //Accept power management packet
++#define RCR_ADD3 BIT4 //Accept address 3 match packet
++#define RCR_AB BIT3 //Accept broadcast packet
++#define RCR_AM BIT2 //Accept multicast packet
++#define RCR_APM BIT1 //Accept physical match packet
++#define RCR_AAP BIT0 //Accept all unicast packet
++#define RCR_MXDMA_OFFSET 8
++#define RCR_FIFO_OFFSET 13
++
++
++
++//============================================================================
++// 8192c USB specific Regsiter Offset and Content definition,
++// 2009.08.18, added by vivi. for merge 92c and 92C into one driver
++//============================================================================
++//#define APS_FSMCO 0x0004 same with 92Ce
++#define RSV_CTRL 0x001C
++#define RD_CTRL 0x0524
++
++//-----------------------------------------------------
++//
++// 0xFE00h ~ 0xFE55h USB Configuration
++//
++//-----------------------------------------------------
++#define REG_USB_INFO 0xFE17
++#define REG_USB_SPECIAL_OPTION 0xFE55
++#define REG_USB_DMA_AGG_TO 0xFE5B
++#define REG_USB_AGG_TO 0xFE5C
++#define REG_USB_AGG_TH 0xFE5D
++
++#define REG_USB_VID 0xFE60
++#define REG_USB_PID 0xFE62
++#define REG_USB_OPTIONAL 0xFE64
++#define REG_USB_CHIRP_K 0xFE65
++#define REG_USB_PHY 0xFE66
++#define REG_USB_MAC_ADDR 0xFE70
++
++#define REG_USB_HRPWM 0xFE58
++#define REG_USB_HCPWM 0xFE57
++
++#define InvalidBBRFValue 0x12345678
++
++//============================================================================
++// 8192C Regsiter Bit and Content definition
++//============================================================================
++//-----------------------------------------------------
++//
++// 0x0000h ~ 0x00FFh System Configuration
++//
++//-----------------------------------------------------
++
++//2 SPS0_CTRL
++#define SW18_FPWM BIT(3)
++
++
++//2 SYS_ISO_CTRL
++#define ISO_MD2PP BIT(0)
++#define ISO_UA2USB BIT(1)
++#define ISO_UD2CORE BIT(2)
++#define ISO_PA2PCIE BIT(3)
++#define ISO_PD2CORE BIT(4)
++#define ISO_IP2MAC BIT(5)
++#define ISO_DIOP BIT(6)
++#define ISO_DIOE BIT(7)
++#define ISO_EB2CORE BIT(8)
++#define ISO_DIOR BIT(9)
++
++#define PWC_EV25V BIT(14)
++#define PWC_EV12V BIT(15)
++
++
++//2 SYS_FUNC_EN
++#define FEN_BBRSTB BIT(0)
++#define FEN_BB_GLB_RSTn BIT(1)
++#define FEN_USBA BIT(2)
++#define FEN_UPLL BIT(3)
++#define FEN_USBD BIT(4)
++#define FEN_DIO_PCIE BIT(5)
++#define FEN_PCIEA BIT(6)
++#define FEN_PPLL BIT(7)
++#define FEN_PCIED BIT(8)
++#define FEN_DIOE BIT(9)
++#define FEN_CPUEN BIT(10)
++#define FEN_DCORE BIT(11)
++#define FEN_ELDR BIT(12)
++#define FEN_DIO_RF BIT(13)
++#define FEN_HWPDN BIT(14)
++#define FEN_MREGEN BIT(15)
++
++//2 APS_FSMCO
++#define PFM_LDALL BIT(0)
++#define PFM_ALDN BIT(1)
++#define PFM_LDKP BIT(2)
++#define PFM_WOWL BIT(3)
++#define EnPDN BIT(4)
++#define PDN_PL BIT(5)
++#define APFM_ONMAC BIT(8)
++#define APFM_OFF BIT(9)
++#define APFM_RSM BIT(10)
++#define AFSM_HSUS BIT(11)
++#define AFSM_PCIE BIT(12)
++#define APDM_MAC BIT(13)
++#define APDM_HOST BIT(14)
++#define APDM_HPDN BIT(15)
++#define RDY_MACON BIT(16)
++#define SUS_HOST BIT(17)
++#define ROP_ALD BIT(20)
++#define ROP_PWR BIT(21)
++#define ROP_SPS BIT(22)
++#define SOP_MRST BIT(25)
++#define SOP_FUSE BIT(26)
++#define SOP_ABG BIT(27)
++#define SOP_AMB BIT(28)
++#define SOP_RCK BIT(29)
++#define SOP_A8M BIT(30)
++#define XOP_BTCK BIT(31)
++
++//2 SYS_CLKR
++#define ANAD16V_EN BIT(0)
++#define ANA8M BIT(1)
++#define MACSLP BIT(4)
++#define LOADER_CLK_EN BIT(5)
++#define _80M_SSC_DIS BIT(7)
++#define _80M_SSC_EN_HO BIT(8)
++#define PHY_SSC_RSTB BIT(9)
++#define SEC_CLK_EN BIT(10)
++#define MAC_CLK_EN BIT(11)
++#define SYS_CLK_EN BIT(12)
++#define RING_CLK_EN BIT(13)
++
++
++//2 9346CR
++
++#define BOOT_FROM_EEPROM BIT(4)
++#define EEPROM_EN BIT(5)
++
++
++//2 AFE_MISC
++#define AFE_BGEN BIT(0)
++#define AFE_MBEN BIT(1)
++#define MAC_ID_EN BIT(7)
++
++
++//2 SPS0_CTRL
++
++
++//2 SPS_OCP_CFG
++
++
++//2 RSV_CTRL
++#define WLOCK_ALL BIT(0)
++#define WLOCK_00 BIT(1)
++#define WLOCK_04 BIT(2)
++#define WLOCK_08 BIT(3)
++#define WLOCK_40 BIT(4)
++#define R_DIS_PRST_0 BIT(5)
++#define R_DIS_PRST_1 BIT(6)
++#define LOCK_ALL_EN BIT(7)
++
++//2 RF_CTRL
++#define RF_EN BIT(0)
++#define RF_RSTB BIT(1)
++#define RF_SDMRSTB BIT(2)
++
++
++
++//2 LDOA15_CTRL
++#define LDA15_EN BIT(0)
++#define LDA15_STBY BIT(1)
++#define LDA15_OBUF BIT(2)
++#define LDA15_REG_VOS BIT(3)
++#define _LDA15_VOADJ(x) (((x) & 0x7) << 4)
++
++
++
++//2 LDOV12D_CTRL
++#define LDV12_EN BIT(0)
++#define LDV12_SDBY BIT(1)
++#define LPLDO_HSM BIT(2)
++#define LPLDO_LSM_DIS BIT(3)
++#define _LDV12_VADJ(x) (((x) & 0xF) << 4)
++
++
++//2 AFE_XTAL_CTRL
++#define XTAL_EN BIT(0)
++#define XTAL_BSEL BIT(1)
++#define _XTAL_BOSC(x) (((x) & 0x3) << 2)
++#define _XTAL_CADJ(x) (((x) & 0xF) << 4)
++#define XTAL_GATE_USB BIT(8)
++#define _XTAL_USB_DRV(x) (((x) & 0x3) << 9)
++#define XTAL_GATE_AFE BIT(11)
++#define _XTAL_AFE_DRV(x) (((x) & 0x3) << 12)
++#define XTAL_RF_GATE BIT(14)
++#define _XTAL_RF_DRV(x) (((x) & 0x3) << 15)
++#define XTAL_GATE_DIG BIT(17)
++#define _XTAL_DIG_DRV(x) (((x) & 0x3) << 18)
++#define XTAL_BT_GATE BIT(20)
++#define _XTAL_BT_DRV(x) (((x) & 0x3) << 21)
++#define _XTAL_GPIO(x) (((x) & 0x7) << 23)
++
++
++#define CKDLY_AFE BIT(26)
++#define CKDLY_USB BIT(27)
++#define CKDLY_DIG BIT(28)
++#define CKDLY_BT BIT(29)
++
++
++//2 AFE_PLL_CTRL
++#define APLL_EN BIT(0)
++#define APLL_320_EN BIT(1)
++#define APLL_FREF_SEL BIT(2)
++#define APLL_EDGE_SEL BIT(3)
++#define APLL_WDOGB BIT(4)
++#define APLL_LPFEN BIT(5)
++
++#define APLL_REF_CLK_13MHZ 0x1
++#define APLL_REF_CLK_19_2MHZ 0x2
++#define APLL_REF_CLK_20MHZ 0x3
++#define APLL_REF_CLK_25MHZ 0x4
++#define APLL_REF_CLK_26MHZ 0x5
++#define APLL_REF_CLK_38_4MHZ 0x6
++#define APLL_REF_CLK_40MHZ 0x7
++
++#define APLL_320EN BIT(14)
++#define APLL_80EN BIT(15)
++#define APLL_1MEN BIT(24)
++
++
++//2 EFUSE_CTRL
++#define ALD_EN BIT(18)
++#define EF_PD BIT(19)
++#define EF_FLAG BIT(31)
++
++//2 EFUSE_TEST
++#define EF_TRPT BIT(7)
++#define LDOE25_EN BIT(31)
++
++//2 PWR_DATA
++
++//2 CAL_TIMER
++
++//2 ACLK_MON
++#define RSM_EN BIT(0)
++#define Timer_EN BIT(4)
++
++
++//2 GPIO_MUXCFG
++#define TRSW0EN BIT(2)
++#define TRSW1EN BIT(3)
++#define EROM_EN BIT(4)
++#define EnBT BIT(5)
++#define EnUart BIT(8)
++#define Uart_910 BIT(9)
++#define EnPMAC BIT(10)
++#define SIC_SWRST BIT(11)
++#define EnSIC BIT(12)
++#define SIC_23 BIT(13)
++#define EnHDP BIT(14)
++#define SIC_LBK BIT(15)
++
++//2 GPIO_PIN_CTRL
++
++
++
++//2 GPIO_INTM
++
++//2 LEDCFG
++#define LED0PL BIT(4)
++#define LED1PL BIT(12)
++#define LED0DIS BIT(7)
++
++#define SECCAM_CLR BIT(30)
++
++//2 FSIMR
++
++//2 FSISR
++
++
++//2 8051FWDL
++//2 MCUFWDL
++#define MCUFWDL_EN BIT(0)
++#define MCUFWDL_RDY BIT(1)
++#define FWDL_ChkSum_rpt BIT(2)
++#define MACINI_RDY BIT(3)
++#define BBINI_RDY BIT(4)
++#define RFINI_RDY BIT(5)
++#define WINTINI_RDY BIT(6)
++#define MAC1_WINTINI_RDY BIT(11)// 0X81 BIT3
++#define CPRST BIT(23)
++
++
++
++
++//2 REG_SYS_CFG
++#define XCLK_VLD BIT(0)
++#define ACLK_VLD BIT(1)
++#define UCLK_VLD BIT(2)
++#define PCLK_VLD BIT(3)
++#define PCIRSTB BIT(4)
++#define V15_VLD BIT(5)
++#define TRP_B15V_EN BIT(7)
++#define SIC_IDLE BIT(8)
++#define BD_MAC2 BIT(9)
++#define BD_MAC1 BIT(10)
++#define IC_MACPHY_MODE BIT(11)
++#define PAD_HWPD_IDN BIT(22)
++#define TRP_VAUX_EN BIT(23)
++#define TRP_BT_EN BIT(24)
++#define BD_PKG_SEL BIT(25)
++#define BD_HCI_SEL BIT(26)
++#define TYPE_ID BIT(27)
++
++#define CHIP_VER_RTL_MASK 0xF000 //Bit 12 ~ 15
++#define CHIP_VER_RTL_SHIFT 12
++
++//-----------------------------------------------------
++//
++// 0x0100h ~ 0x01FFh MACTOP General Configuration
++//
++//-----------------------------------------------------
++
++
++//2 Function Enable Registers
++//2 CR
++
++#define REG_LBMODE (REG_CR + 3)
++
++
++#define HCI_TXDMA_EN BIT(0)
++#define HCI_RXDMA_EN BIT(1)
++#define TXDMA_EN BIT(2)
++#define RXDMA_EN BIT(3)
++#define PROTOCOL_EN BIT(4)
++#define SCHEDULE_EN BIT(5)
++#define MACTXEN BIT(6)
++#define MACRXEN BIT(7)
++#define ENSWBCN BIT(8)
++#define ENSEC BIT(9)
++
++// Network type
++#define _NETTYPE(x) (((x) & 0x3) << 16)
++#define MASK_NETTYPE 0x30000
++#define NT_NO_LINK 0x0
++#define NT_LINK_AD_HOC 0x1
++#define NT_LINK_AP 0x2
++#define NT_AS_AP 0x3
++
++#define _LBMODE(x) (((x) & 0xF) << 24)
++#define MASK_LBMODE 0xF000000
++#define LOOPBACK_NORMAL 0x0
++#define LOOPBACK_IMMEDIATELY 0xB
++#define LOOPBACK_MAC_DELAY 0x3
++#define LOOPBACK_PHY 0x1
++#define LOOPBACK_DMA 0x7
++
++
++//2 PBP - Page Size Register
++#define GET_RX_PAGE_SIZE(value) ((value) & 0xF)
++#define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4)
++#define _PSRX_MASK 0xF
++#define _PSTX_MASK 0xF0
++#define _PSRX(x) (x)
++#define _PSTX(x) ((x) << 4)
++
++#define PBP_64 0x0
++#define PBP_128 0x1
++#define PBP_256 0x2
++#define PBP_512 0x3
++#define PBP_1024 0x4
++
++
++//2 TX/RXDMA
++#define RXDMA_ARBBW_EN BIT(0)
++#define RXSHFT_EN BIT(1)
++#define RXDMA_AGG_EN BIT(2)
++#define QS_VO_QUEUE BIT(8)
++#define QS_VI_QUEUE BIT(9)
++#define QS_BE_QUEUE BIT(10)
++#define QS_BK_QUEUE BIT(11)
++#define QS_MANAGER_QUEUE BIT(12)
++#define QS_HIGH_QUEUE BIT(13)
++
++#define HQSEL_VOQ BIT(0)
++#define HQSEL_VIQ BIT(1)
++#define HQSEL_BEQ BIT(2)
++#define HQSEL_BKQ BIT(3)
++#define HQSEL_MGTQ BIT(4)
++#define HQSEL_HIQ BIT(5)
++
++// For normal driver, 0x10C
++#define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14)
++#define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12)
++#define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10)
++#define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8 )
++#define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6 )
++#define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4 )
++
++#define QUEUE_LOW 1
++#define QUEUE_NORMAL 2
++#define QUEUE_HIGH 3
++
++
++
++//2 TRXFF_BNDY
++
++
++//2 LLT_INIT
++#define _LLT_NO_ACTIVE 0x0
++#define _LLT_WRITE_ACCESS 0x1
++#define _LLT_READ_ACCESS 0x2
++
++#define _LLT_INIT_DATA(x) ((x) & 0xFF)
++#define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8)
++#define _LLT_OP(x) (((x) & 0x3) << 30)
++#define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3)
++
++
++//2 BB_ACCESS_CTRL
++#define BB_WRITE_READ_MASK (BIT(31) | BIT(30))
++#define BB_WRITE_EN BIT(30)
++#define BB_READ_EN BIT(31)
++//#define BB_ADDR_MASK 0xFFF
++//#define _BB_ADDR(x) ((x) & BB_ADDR_MASK)
++
++//-----------------------------------------------------
++//
++// 0x0200h ~ 0x027Fh TXDMA Configuration
++//
++//-----------------------------------------------------
++//2 RQPN
++#define _HPQ(x) ((x) & 0xFF)
++#define _LPQ(x) (((x) & 0xFF) << 8)
++#define _PUBQ(x) (((x) & 0xFF) << 16)
++#define _NPQ(x) ((x) & 0xFF) // NOTE: in RQPN_NPQ register
++
++
++#define HPQ_PUBLIC_DIS BIT(24)
++#define LPQ_PUBLIC_DIS BIT(25)
++#define LD_RQPN BIT(31)
++
++
++//2 TDECTRL
++#define BCN_VALID BIT(16)
++#define BCN_HEAD(x) (((x) & 0xFF) << 8)
++#define BCN_HEAD_MASK 0xFF00
++
++//2 TDECTL
++#define BLK_DESC_NUM_SHIFT 4
++#define BLK_DESC_NUM_MASK 0xF
++
++
++//2 TXDMA_OFFSET_CHK
++#define DROP_DATA_EN BIT(9)
++
++//-----------------------------------------------------
++//
++// 0x0400h ~ 0x047Fh Protocol Configuration
++//
++//-----------------------------------------------------
++//2 FWHW_TXQ_CTRL
++#define EN_AMPDU_RTY_NEW BIT(7)
++
++//2 INIRTSMCS_SEL
++#define _INIRTSMCS_SEL(x) ((x) & 0x3F)
++
++
++//2 SPEC SIFS
++#define _SPEC_SIFS_CCK(x) ((x) & 0xFF)
++#define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8)
++
++
++//2 RRSR
++
++#define RATE_REG_BITMAP_ALL 0xFFFFF
++
++#define _RRSC_BITMAP(x) ((x) & 0xFFFFF)
++
++#define _RRSR_RSC(x) (((x) & 0x3) << 21)
++#define RRSR_RSC_RESERVED 0x0
++#define RRSR_RSC_UPPER_SUBCHANNEL 0x1
++#define RRSR_RSC_LOWER_SUBCHANNEL 0x2
++#define RRSR_RSC_DUPLICATE_MODE 0x3
++
++
++//2 ARFR
++#define USE_SHORT_G1 BIT(20)
++
++//2 AGGLEN_LMT_L
++#define _AGGLMT_MCS0(x) ((x) & 0xF)
++#define _AGGLMT_MCS1(x) (((x) & 0xF) << 4)
++#define _AGGLMT_MCS2(x) (((x) & 0xF) << 8)
++#define _AGGLMT_MCS3(x) (((x) & 0xF) << 12)
++#define _AGGLMT_MCS4(x) (((x) & 0xF) << 16)
++#define _AGGLMT_MCS5(x) (((x) & 0xF) << 20)
++#define _AGGLMT_MCS6(x) (((x) & 0xF) << 24)
++#define _AGGLMT_MCS7(x) (((x) & 0xF) << 28)
++
++
++//2 RL
++#define RETRY_LIMIT_SHORT_SHIFT 8
++#define RETRY_LIMIT_LONG_SHIFT 0
++
++
++//2 DARFRC
++#define _DARF_RC1(x) ((x) & 0x1F)
++#define _DARF_RC2(x) (((x) & 0x1F) << 8)
++#define _DARF_RC3(x) (((x) & 0x1F) << 16)
++#define _DARF_RC4(x) (((x) & 0x1F) << 24)
++// NOTE: shift starting from address (DARFRC + 4)
++#define _DARF_RC5(x) ((x) & 0x1F)
++#define _DARF_RC6(x) (((x) & 0x1F) << 8)
++#define _DARF_RC7(x) (((x) & 0x1F) << 16)
++#define _DARF_RC8(x) (((x) & 0x1F) << 24)
++
++
++//2 RARFRC
++#define _RARF_RC1(x) ((x) & 0x1F)
++#define _RARF_RC2(x) (((x) & 0x1F) << 8)
++#define _RARF_RC3(x) (((x) & 0x1F) << 16)
++#define _RARF_RC4(x) (((x) & 0x1F) << 24)
++// NOTE: shift starting from address (RARFRC + 4)
++#define _RARF_RC5(x) ((x) & 0x1F)
++#define _RARF_RC6(x) (((x) & 0x1F) << 8)
++#define _RARF_RC7(x) (((x) & 0x1F) << 16)
++#define _RARF_RC8(x) (((x) & 0x1F) << 24)
++
++
++
++
++//-----------------------------------------------------
++//
++// 0x0500h ~ 0x05FFh EDCA Configuration
++//
++//-----------------------------------------------------
++
++
++
++//2 EDCA setting
++#define AC_PARAM_TXOP_LIMIT_OFFSET 16
++#define AC_PARAM_ECW_MAX_OFFSET 12
++#define AC_PARAM_ECW_MIN_OFFSET 8
++#define AC_PARAM_AIFS_OFFSET 0
++
++
++//2 EDCA_VO_PARAM
++#define _AIFS(x) (x)
++#define _ECW_MAX_MIN(x) ((x) << 8)
++#define _TXOP_LIMIT(x) ((x) << 16)
++
++
++#define _BCNIFS(x) ((x) & 0xFF)
++#define _BCNECW(x) (((x) & 0xF))<< 8)
++
++
++#define _LRL(x) ((x) & 0x3F)
++#define _SRL(x) (((x) & 0x3F) << 8)
++
++
++//2 SIFS_CCK
++#define _SIFS_CCK_CTX(x) ((x) & 0xFF)
++#define _SIFS_CCK_TRX(x) (((x) & 0xFF) << 8);
++
++
++//2 SIFS_OFDM
++#define _SIFS_OFDM_CTX(x) ((x) & 0xFF)
++#define _SIFS_OFDM_TRX(x) (((x) & 0xFF) << 8);
++
++
++//2 TBTT PROHIBIT
++#define _TBTT_PROHIBIT_HOLD(x) (((x) & 0xFF) << 8)
++
++
++//2 REG_RD_CTRL
++#define DIS_EDCA_CNT_DWN BIT(11)
++
++
++//2 BCN_CTRL
++#define EN_MBSSID BIT(1)
++#define EN_TXBCN_RPT BIT(2)
++#define EN_BCN_FUNCTION BIT(3)
++// The same function but different bit field.
++#define DIS_TSF_UDT0_NORMAL_CHIP BIT(4)
++#define DIS_TSF_UDT0_TEST_CHIP BIT(5)
++
++//2 ACMHWCTRL
++#define AcmHw_HwEn BIT(0)
++#define AcmHw_BeqEn BIT(1)
++#define AcmHw_ViqEn BIT(2)
++#define AcmHw_VoqEn BIT(3)
++#define AcmHw_BeqStatus BIT(4)
++#define AcmHw_ViqStatus BIT(5)
++#define AcmHw_VoqStatus BIT(6)
++
++
++
++//-----------------------------------------------------
++//
++// 0x0600h ~ 0x07FFh WMAC Configuration
++//
++//-----------------------------------------------------
++
++//2 APSD_CTRL
++#define APSDOFF BIT(6)
++#define APSDOFF_STATUS BIT(7)
++
++
++//2 BWOPMODE
++#define BW_20MHZ BIT(2)
++//#define BW_OPMODE_20MHZ BIT(2) // For compability
++
++
++#define RATE_BITMAP_ALL 0xFFFFF
++
++// Only use CCK 1M rate for ACK
++#define RATE_RRSR_CCK_ONLY_1M 0xFFFF1
++#define RATE_RRSR_WITHOUT_CCK 0xFFFF0
++
++//2 TCR
++#define TSFRST BIT(0)
++#define DIS_GCLK BIT(1)
++#define PAD_SEL BIT(2)
++#define PWR_ST BIT(6)
++#define PWRBIT_OW_EN BIT(7)
++#define ACRC BIT(8)
++#define CFENDFORM BIT(9)
++#define ICV BIT(10)
++
++
++
++//2 RCR
++#define AAP BIT(0)
++#define APM BIT(1)
++#define AM BIT(2)
++#define AB BIT(3)
++#define ADD3 BIT(4)
++#define APWRMGT BIT(5)
++#define CBSSID BIT(6)
++#define CBSSID_BCN BIT(7)
++#define ACRC32 BIT(8)
++#define AICV BIT(9)
++#define ADF BIT(11)
++#define ACF BIT(12)
++#define AMF BIT(13)
++#define HTC_LOC_CTRL BIT(14)
++#define UC_DATA_EN BIT(16)
++#define BM_DATA_EN BIT(17)
++#define MFBEN BIT(22)
++#define LSIGEN BIT(23)
++#define EnMBID BIT(24)
++#define APP_BASSN BIT(27)
++#define APP_PHYSTS BIT(28)
++#define APP_ICV BIT(29)
++#define APP_MIC BIT(30)
++#define APP_FCS BIT(31)
++
++//2 RX_PKT_LIMIT
++
++//2 RX_DLK_TIME
++
++//2 MBIDCAMCFG
++
++
++
++//2 AMPDU_MIN_SPACE
++#define _MIN_SPACE(x) ((x) & 0x7)
++#define _SHORT_GI_PADDING(x) (((x) & 0x1F) << 3)
++
++
++//2 RXERR_RPT
++#define RXERR_TYPE_OFDM_PPDU 0
++#define RXERR_TYPE_OFDM_FALSE_ALARM 1
++#define RXERR_TYPE_OFDM_MPDU_OK 2
++#define RXERR_TYPE_OFDM_MPDU_FAIL 3
++#define RXERR_TYPE_CCK_PPDU 4
++#define RXERR_TYPE_CCK_FALSE_ALARM 5
++#define RXERR_TYPE_CCK_MPDU_OK 6
++#define RXERR_TYPE_CCK_MPDU_FAIL 7
++#define RXERR_TYPE_HT_PPDU 8
++#define RXERR_TYPE_HT_FALSE_ALARM 9
++#define RXERR_TYPE_HT_MPDU_TOTAL 10
++#define RXERR_TYPE_HT_MPDU_OK 11
++#define RXERR_TYPE_HT_MPDU_FAIL 12
++#define RXERR_TYPE_RX_FULL_DROP 15
++
++#define RXERR_COUNTER_MASK 0xFFFFF
++#define RXERR_RPT_RST BIT(27)
++#define _RXERR_RPT_SEL(type) ((type) << 28)
++
++
++//2 SECCFG
++#define SCR_TxUseDK BIT(0) //Force Tx Use Default Key
++#define SCR_RxUseDK BIT(1) //Force Rx Use Default Key
++#define SCR_TxEncEnable BIT(2) //Enable Tx Encryption
++#define SCR_RxDecEnable BIT(3) //Enable Rx Decryption
++#define SCR_SKByA2 BIT(4) //Search kEY BY A2
++#define SCR_NoSKMC BIT(5) //No Key Search Multicast
++#define SCR_TXBCUSEDK BIT(6) // Force Tx Broadcast packets Use Default Key
++#define SCR_RXBCUSEDK BIT(7) // Force Rx Broadcast packets Use Default Key
++
++//vivi added for new cam search flow, 20091028
++#ifdef HW_EN_DE_CRYPTION_FOR_NEW_CAM_SEARCH_FLOW
++#define SCR_TxUseBroadcastDK BIT6 //Force Tx Use Broadcast Default Key
++#define SCR_RxUseBroadcastDK BIT7 //Force Rx Use Broadcast Default Key
++#endif
++
++
++//-----------------------------------------------------
++//
++// 0xFE00h ~ 0xFE55h USB Configuration
++//
++//-----------------------------------------------------
++
++//2 USB Information (0xFE17)
++#define USB_IS_HIGH_SPEED 0
++#define USB_IS_FULL_SPEED 1
++#define USB_SPEED_MASK BIT(5)
++
++#define USB_NORMAL_SIE_EP_MASK 0xF
++#define USB_NORMAL_SIE_EP_SHIFT 4
++
++#define USB_TEST_EP_MASK 0x30
++#define USB_TEST_EP_SHIFT 4
++
++//2 Special Option
++#define USB_AGG_EN BIT(3)
++
++
++//2REG_C2HEVT_CLEAR
++#define C2H_EVT_HOST_CLOSE 0x00 // Set by driver and notify FW that the driver has read the C2H command message
++#define C2H_EVT_FW_CLOSE 0xFF // Set by FW indicating that FW had set the C2H command message and it's not yet read by driver.
++
++//2 8192D PartNo.
++#define PARTNO_92D_NIC (BIT7|BIT6)
++#define PARTNO_92D_NIC_REMARK (BIT5|BIT4)
++#define PARTNO_SINGLE_BAND_VS BIT3
++#define PARTNO_SINGLE_BAND_VS_REMARK BIT1
++#define PARTNO_CONCURRENT_BAND_VC (BIT3|BIT2)
++#define PARTNO_CONCURRENT_BAND_VC_REMARK (BIT1|BIT0)
++//========================================================
++// General definitions
++//========================================================
++
++#define MAC_ADDR_LEN 6
++#define LAST_ENTRY_OF_TX_PKT_BUFFER 255
++#define LAST_ENTRY_OF_TX_PKT_BUFFER_DUAL_MAC 127
++
++#define POLLING_LLT_THRESHOLD 20
++#define POLLING_READY_TIMEOUT_COUNT 1000
++
++// Min Spacing related settings.
++#define MAX_MSS_DENSITY_2T 0x13
++#define MAX_MSS_DENSITY_1T 0x0A
++// GPIO BIT
++#define HAL_8192C_HW_GPIO_WPS_BIT BIT2
++
++
++#include "basic_types.h"
++
++#endif
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtl8192d_xmit.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtl8192d_xmit.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtl8192d_xmit.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtl8192d_xmit.h 2015-07-28 01:20:58.321597318 +0200
+@@ -0,0 +1,144 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef _RTL8192D_XMIT_H_
++#define _RTL8192D_XMIT_H_
++
++//
++// Queue Select Value in TxDesc
++//
++#define QSLT_BK 0x2//0x01
++#define QSLT_BE 0x0
++#define QSLT_VI 0x5//0x4
++#define QSLT_VO 0x7//0x6
++#define QSLT_BEACON 0x10
++#define QSLT_HIGH 0x11
++#define QSLT_MGNT 0x12
++#define QSLT_CMD 0x13
++
++//Because we open EM for normal case, we just always insert 2*8 bytes.by wl
++#define USB_92D_DUMMY_OFFSET 2
++#define USB_92D_DUMMY_LENGTH (USB_92D_DUMMY_OFFSET * PACKET_OFFSET_SZ)
++#define USB_HWDESC_HEADER_LEN (TXDESC_SIZE + USB_92D_DUMMY_LENGTH)
++
++//For 92D early mode
++#define SET_EARLYMODE_PKTNUM(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 0, 3, __Value)
++#define SET_EARLYMODE_LEN0(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 12, __Value)
++#define SET_EARLYMODE_LEN1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 16, 12, __Value)
++#define SET_EARLYMODE_LEN2_1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 28, 4, __Value)
++#define SET_EARLYMODE_LEN2_2(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 8, __Value)
++#define SET_EARLYMODE_LEN3(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 8, 12, __Value)
++#define SET_EARLYMODE_LEN4(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 20, 12, __Value)
++
++/* Copy from rtl8192c */
++struct txrpt_ccx_8192d {
++ /* offset 0 */
++ u8 retry_cnt:6;
++ u8 rsvd_0:2;
++
++ /* offset 1 */
++ u8 rts_retry_cnt:6;
++ u8 rsvd_1:2;
++
++ /* offset 2 */
++ u8 ccx_qtime0;
++ u8 ccx_qtime1;
++
++ /* offset 4 */
++ u8 missed_pkt_num:5;
++ u8 rsvd_4:3;
++
++ /* offset 5 */
++ u8 mac_id:5;
++ u8 des1_fragssn:3;
++
++ /* offset 6 */
++ u8 rpt_pkt_num:5;
++ u8 pkt_drop:1;
++ u8 lifetime_over:1;
++ u8 retry_over:1;
++
++ /* offset 7*/
++ u8 edca_tx_queue:4;
++ u8 rsvd_7:1;
++ u8 bmc:1;
++ u8 pkt_ok:1;
++ u8 int_ccx:1;
++};
++
++#define txrpt_ccx_qtime_8192d(txrpt_ccx) ((txrpt_ccx)->ccx_qtime0+((txrpt_ccx)->ccx_qtime1<<8))
++
++#ifdef CONFIG_XMIT_ACK
++void dump_txrpt_ccx_8192d(void *buf);
++void handle_txrpt_ccx_8192d(_adapter *adapter, void *buf);
++#else
++#define dump_txrpt_ccx_8192d(buf) do {} while(0)
++#define handle_txrpt_ccx_8192d(adapter, buf) do {} while(0)
++#endif
++
++#ifdef CONFIG_USB_HCI
++
++#ifdef CONFIG_USB_TX_AGGREGATION
++#define MAX_TX_AGG_PACKET_NUMBER 0xFF
++#endif
++
++s32 rtl8192du_init_xmit_priv(_adapter * padapter);
++
++void rtl8192du_free_xmit_priv(_adapter * padapter);
++
++void rtl8192du_cal_txdesc_chksum(struct tx_desc *ptxdesc);
++
++s32 rtl8192du_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
++
++s32 rtl8192du_mgnt_xmit(_adapter *padapter, struct xmit_frame *pmgntframe);
++
++s32 rtl8192du_hal_xmit(_adapter *padapter, struct xmit_frame *pxmitframe);
++
++s32 rtl8192du_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
++
++
++#ifdef CONFIG_HOSTAPD_MLME
++s32 rtl8192du_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt);
++#endif
++
++#endif
++
++#ifdef CONFIG_PCI_HCI
++s32 rtl8192de_init_xmit_priv(_adapter * padapter);
++void rtl8192de_free_xmit_priv(_adapter * padapter);
++
++s32 rtl8192de_enqueue_xmitbuf(struct rtw_tx_ring *ring, struct xmit_buf *pxmitbuf);
++struct xmit_buf *rtl8192de_dequeue_xmitbuf(struct rtw_tx_ring *ring);
++
++void rtl8192de_xmitframe_resume(_adapter *padapter);
++
++s32 rtl8192de_mgnt_xmit(_adapter *padapter, struct xmit_frame *pmgntframe);
++
++s32 rtl8192de_hal_xmit(_adapter *padapter, struct xmit_frame *pxmitframe);
++
++s32 rtl8192de_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
++
++#ifdef CONFIG_HOSTAPD_MLME
++s32 rtl8192de_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt);
++#endif
++
++#endif
++
++
++#endif
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtw_android.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtw_android.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtw_android.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtw_android.h 2015-07-28 01:20:58.321597318 +0200
+@@ -0,0 +1,89 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++
++#ifndef __RTW_ANDROID_H__
++#define __RTW_ANDROID_H__
++
++#include <linux/module.h>
++#include <linux/netdevice.h>
++
++enum ANDROID_WIFI_CMD {
++ ANDROID_WIFI_CMD_START,
++ ANDROID_WIFI_CMD_STOP,
++ ANDROID_WIFI_CMD_SCAN_ACTIVE,
++ ANDROID_WIFI_CMD_SCAN_PASSIVE,
++ ANDROID_WIFI_CMD_RSSI,
++ ANDROID_WIFI_CMD_LINKSPEED,
++ ANDROID_WIFI_CMD_RXFILTER_START,
++ ANDROID_WIFI_CMD_RXFILTER_STOP,
++ ANDROID_WIFI_CMD_RXFILTER_ADD,
++ ANDROID_WIFI_CMD_RXFILTER_REMOVE,
++ ANDROID_WIFI_CMD_BTCOEXSCAN_START,
++ ANDROID_WIFI_CMD_BTCOEXSCAN_STOP,
++ ANDROID_WIFI_CMD_BTCOEXMODE,
++ ANDROID_WIFI_CMD_SETSUSPENDOPT,
++ ANDROID_WIFI_CMD_P2P_DEV_ADDR,
++ ANDROID_WIFI_CMD_SETFWPATH,
++ ANDROID_WIFI_CMD_SETBAND,
++ ANDROID_WIFI_CMD_GETBAND,
++ ANDROID_WIFI_CMD_COUNTRY,
++ ANDROID_WIFI_CMD_P2P_SET_NOA,
++ ANDROID_WIFI_CMD_P2P_GET_NOA,
++ ANDROID_WIFI_CMD_P2P_SET_PS,
++ ANDROID_WIFI_CMD_SET_AP_WPS_P2P_IE,
++#ifdef PNO_SUPPORT
++ ANDROID_WIFI_CMD_PNOSSIDCLR_SET,
++ ANDROID_WIFI_CMD_PNOSETUP_SET,
++ ANDROID_WIFI_CMD_PNOENABLE_SET,
++ ANDROID_WIFI_CMD_PNODEBUG_SET,
++#endif
++
++ ANDROID_WIFI_CMD_MACADDR,
++
++ ANDROID_WIFI_CMD_BLOCK,
++
++ ANDROID_WIFI_CMD_WFD_ENABLE,
++ ANDROID_WIFI_CMD_WFD_DISABLE,
++
++ ANDROID_WIFI_CMD_WFD_SET_TCPPORT,
++ ANDROID_WIFI_CMD_WFD_SET_MAX_TPUT,
++ ANDROID_WIFI_CMD_WFD_SET_DEVTYPE,
++
++ ANDROID_WIFI_CMD_MAX
++};
++
++int rtw_android_cmdstr_to_num(char *cmdstr);
++int rtw_android_priv_cmd(struct net_device *net, struct ifreq *ifr, int cmd);
++
++#if defined(RTW_ENABLE_WIFI_CONTROL_FUNC)
++int rtw_android_wifictrl_func_add(void);
++void rtw_android_wifictrl_func_del(void);
++void* wl_android_prealloc(int section, unsigned long size);
++
++int wifi_get_irq_number(unsigned long *irq_flags_ptr);
++int wifi_set_power(int on, unsigned long msec);
++int wifi_get_mac_addr(unsigned char *buf);
++void *wifi_get_country_code(char *ccode);
++#else
++static int rtw_android_wifictrl_func_add(void) { return 0; }
++static void rtw_android_wifictrl_func_del(void) {}
++#endif /* defined(RTW_ENABLE_WIFI_CONTROL_FUNC) */
++
++#endif //__RTW_ANDROID_H__
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtw_ap.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtw_ap.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtw_ap.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtw_ap.h 2015-07-28 01:20:58.321597318 +0200
+@@ -0,0 +1,63 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef __RTW_AP_H_
++#define __RTW_AP_H_
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++
++
++#ifdef CONFIG_AP_MODE
++
++//external function
++extern void rtw_indicate_sta_assoc_event(_adapter *padapter, struct sta_info *psta);
++extern void rtw_indicate_sta_disassoc_event(_adapter *padapter, struct sta_info *psta);
++
++
++void init_mlme_ap_info(_adapter *padapter);
++void free_mlme_ap_info(_adapter *padapter);
++//void update_BCNTIM(_adapter *padapter);
++void rtw_add_bcn_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 index, u8 *data, u8 len);
++void rtw_remove_bcn_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 index);
++void update_beacon(_adapter *padapter, u8 ie_id, u8 *oui, u8 tx);
++void expire_timeout_chk(_adapter *padapter);
++void update_sta_info_apmode(_adapter *padapter, struct sta_info *psta);
++int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len);
++void rtw_ap_restore_network(_adapter *padapter);
++void rtw_set_macaddr_acl(_adapter *padapter, int mode);
++int rtw_acl_add_sta(_adapter *padapter, u8 *addr);
++int rtw_acl_remove_sta(_adapter *padapter, u8 *addr);
++
++#ifdef CONFIG_NATIVEAP_MLME
++void associated_clients_update(_adapter *padapter, u8 updated);
++void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta);
++u8 bss_cap_update_on_sta_leave(_adapter *padapter, struct sta_info *psta);
++void sta_info_update(_adapter *padapter, struct sta_info *psta);
++void ap_sta_info_defer_update(_adapter *padapter, struct sta_info *psta);
++u8 ap_free_sta(_adapter *padapter, struct sta_info *psta, bool active, u16 reason);
++int rtw_sta_flush(_adapter *padapter);
++int rtw_ap_inform_ch_switch(_adapter *padapter, u8 new_ch, u8 ch_offset);
++void start_ap_mode(_adapter *padapter);
++void stop_ap_mode(_adapter *padapter);
++#endif
++#endif //end of CONFIG_AP_MODE
++
++#endif
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtw_br_ext.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtw_br_ext.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtw_br_ext.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtw_br_ext.h 2015-07-28 01:20:58.321597318 +0200
+@@ -0,0 +1,75 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef _RTW_BR_EXT_H_
++#define _RTW_BR_EXT_H_
++
++#if 1 // rtw_wifi_driver
++#define CL_IPV6_PASS 1
++#define MACADDRLEN 6
++#define _DEBUG_ERR printk
++#define _DEBUG_INFO //printk
++#define DEBUG_WARN printk
++#define DEBUG_INFO //printk
++#define DEBUG_ERR printk
++//#define GET_MY_HWADDR ((GET_MIB(priv))->dot11OperationEntry.hwaddr)
++#define GET_MY_HWADDR(padapter) ((padapter)->eeprompriv.mac_addr)
++#endif // rtw_wifi_driver
++
++#define NAT25_HASH_BITS 4
++#define NAT25_HASH_SIZE (1 << NAT25_HASH_BITS)
++#define NAT25_AGEING_TIME 300
++
++#ifdef CL_IPV6_PASS
++#define MAX_NETWORK_ADDR_LEN 17
++#else
++#define MAX_NETWORK_ADDR_LEN 11
++#endif
++
++struct nat25_network_db_entry
++{
++ struct nat25_network_db_entry *next_hash;
++ struct nat25_network_db_entry **pprev_hash;
++ atomic_t use_count;
++ unsigned char macAddr[6];
++ unsigned long ageing_timer;
++ unsigned char networkAddr[MAX_NETWORK_ADDR_LEN];
++};
++
++enum NAT25_METHOD {
++ NAT25_MIN,
++ NAT25_CHECK,
++ NAT25_INSERT,
++ NAT25_LOOKUP,
++ NAT25_PARSE,
++ NAT25_MAX
++};
++
++struct br_ext_info {
++ unsigned int nat25_disable;
++ unsigned int macclone_enable;
++ unsigned int dhcp_bcst_disable;
++ int addPPPoETag; // 1: Add PPPoE relay-SID, 0: disable
++ unsigned char nat25_dmzMac[MACADDRLEN];
++ unsigned int nat25sc_disable;
++};
++
++void nat25_db_cleanup(_adapter *priv);
++
++#endif // _RTW_BR_EXT_H_
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtw_byteorder.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtw_byteorder.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtw_byteorder.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtw_byteorder.h 2015-07-28 01:20:58.321597318 +0200
+@@ -0,0 +1,39 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef _RTL871X_BYTEORDER_H_
++#define _RTL871X_BYTEORDER_H_
++
++#include <drv_conf.h>
++
++#if defined (CONFIG_LITTLE_ENDIAN) && defined (CONFIG_BIG_ENDIAN)
++#error "Shall be CONFIG_LITTLE_ENDIAN or CONFIG_BIG_ENDIAN, but not both!\n"
++#endif
++
++#if defined (CONFIG_LITTLE_ENDIAN)
++#ifndef CONFIG_PLATFORM_MSTAR389
++# include <byteorder/little_endian.h>
++#endif
++#elif defined (CONFIG_BIG_ENDIAN)
++# include <byteorder/big_endian.h>
++#else
++# error "Must be LITTLE/BIG Endian Host"
++#endif
++
++#endif /* _RTL871X_BYTEORDER_H_ */
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtw_cmd.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtw_cmd.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtw_cmd.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtw_cmd.h 2015-07-28 01:20:58.321597318 +0200
+@@ -0,0 +1,1166 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef __RTW_CMD_H_
++#define __RTW_CMD_H_
++
++#include <drv_conf.h>
++#include <wlan_bssdef.h>
++#include <rtw_rf.h>
++#include <rtw_led.h>
++
++#define C2H_MEM_SZ (16*1024)
++
++#ifndef CONFIG_RTL8711FW
++
++ #include <osdep_service.h>
++ #include <ieee80211.h> // <ieee80211/ieee80211.h>
++
++
++ #define FREE_CMDOBJ_SZ 128
++
++ #define MAX_CMDSZ 1024
++ #define MAX_RSPSZ 512
++ #define MAX_EVTSZ 1024
++
++#ifdef PLATFORM_OS_CE
++ #define CMDBUFF_ALIGN_SZ 4
++#else
++ #define CMDBUFF_ALIGN_SZ 512
++#endif
++
++ struct cmd_obj {
++ _adapter *padapter;
++ u16 cmdcode;
++ u8 res;
++ u8 *parmbuf;
++ u32 cmdsz;
++ u8 *rsp;
++ u32 rspsz;
++ //_sema cmd_sem;
++ _list list;
++ };
++
++ struct cmd_priv {
++ _sema cmd_queue_sema;
++ //_sema cmd_done_sema;
++ _sema terminate_cmdthread_sema;
++ _queue cmd_queue;
++ u8 cmd_seq;
++ u8 *cmd_buf; //shall be non-paged, and 4 bytes aligned
++ u8 *cmd_allocated_buf;
++ u8 *rsp_buf; //shall be non-paged, and 4 bytes aligned
++ u8 *rsp_allocated_buf;
++ u32 cmd_issued_cnt;
++ u32 cmd_done_cnt;
++ u32 rsp_cnt;
++ u8 cmdthd_running;
++ u8 stop_req;
++ _adapter *padapter;
++ };
++
++#ifdef CONFIG_EVENT_THREAD_MODE
++ struct evt_obj {
++ u16 evtcode;
++ u8 res;
++ u8 *parmbuf;
++ u32 evtsz;
++ _list list;
++ };
++#endif
++
++ struct evt_priv {
++#ifdef CONFIG_EVENT_THREAD_MODE
++ _sema evt_notify;
++ _sema terminate_evtthread_sema;
++ _queue evt_queue;
++#endif
++
++//#define CONFIG_C2H_WK
++#ifdef CONFIG_C2H_WK
++ _workitem c2h_wk;
++ bool c2h_wk_alive;
++ struct rtw_cbuf *c2h_queue;
++ #define C2H_QUEUE_MAX_LEN 10
++#endif
++
++#ifdef CONFIG_H2CLBK
++ _sema lbkevt_done;
++ u8 lbkevt_limit;
++ u8 lbkevt_num;
++ u8 *cmdevt_parm;
++#endif
++ ATOMIC_T event_seq;
++ u8 *evt_buf; //shall be non-paged, and 4 bytes aligned
++ u8 *evt_allocated_buf;
++ u32 evt_done_cnt;
++#ifdef CONFIG_SDIO_HCI
++ u8 *c2h_mem;
++ u8 *allocated_c2h_mem;
++#ifdef PLATFORM_OS_XP
++ PMDL pc2h_mdl;
++#endif
++#endif
++
++ };
++
++#define init_h2fwcmd_w_parm_no_rsp(pcmd, pparm, code) \
++do {\
++ _rtw_init_listhead(&pcmd->list);\
++ pcmd->cmdcode = code;\
++ pcmd->parmbuf = (u8 *)(pparm);\
++ pcmd->cmdsz = sizeof (*pparm);\
++ pcmd->rsp = NULL;\
++ pcmd->rspsz = 0;\
++} while(0)
++
++struct c2h_evt_hdr {
++ u8 id:4;
++ u8 plen:4;
++ u8 seq;
++ u8 payload[0];
++};
++
++#define c2h_evt_exist(c2h_evt) ((c2h_evt)->id || (c2h_evt)->plen)
++
++extern u32 rtw_enqueue_cmd(struct cmd_priv *pcmdpriv, struct cmd_obj *obj);
++extern struct cmd_obj *rtw_dequeue_cmd(struct cmd_priv *pcmdpriv);
++extern void rtw_free_cmd_obj(struct cmd_obj *pcmd);
++
++#ifdef CONFIG_EVENT_THREAD_MODE
++extern u32 rtw_enqueue_evt(struct evt_priv *pevtpriv, struct evt_obj *obj);
++extern struct evt_obj *rtw_dequeue_evt(_queue *queue);
++extern void rtw_free_evt_obj(struct evt_obj *pcmd);
++#endif
++
++void rtw_stop_cmd_thread(_adapter *adapter);
++thread_return rtw_cmd_thread(thread_context context);
++
++extern u32 rtw_init_cmd_priv (struct cmd_priv *pcmdpriv);
++extern void rtw_free_cmd_priv (struct cmd_priv *pcmdpriv);
++
++extern u32 rtw_init_evt_priv (struct evt_priv *pevtpriv);
++extern void rtw_free_evt_priv (struct evt_priv *pevtpriv);
++extern void rtw_cmd_clr_isr(struct cmd_priv *pcmdpriv);
++extern void rtw_evt_notify_isr(struct evt_priv *pevtpriv);
++#ifdef CONFIG_P2P
++u8 p2p_protocol_wk_cmd(_adapter*padapter, int intCmdType );
++#endif //CONFIG_P2P
++
++#else
++ #include <ieee80211.h>
++#endif /* CONFIG_RTL8711FW */
++
++enum rtw_drvextra_cmd_id
++{
++ NONE_WK_CID,
++ DYNAMIC_CHK_WK_CID,
++ DM_CTRL_WK_CID,
++ PBC_POLLING_WK_CID,
++ POWER_SAVING_CTRL_WK_CID,//IPS,AUTOSuspend
++ LPS_CTRL_WK_CID,
++ ANT_SELECT_WK_CID,
++ P2P_PS_WK_CID,
++ P2P_PROTO_WK_CID,
++ CHECK_HIQ_WK_CID,//for softap mode, check hi queue if empty
++ INTEl_WIDI_WK_CID,
++ C2H_WK_CID,
++ RESET_SECURITYPRIV, // add for CONFIG_IEEE80211W, none 11w also can use
++ FREE_ASSOC_RESOURCES, // add for CONFIG_IEEE80211W, none 11w also can use
++ MAX_WK_CID
++};
++
++enum LPS_CTRL_TYPE
++{
++ LPS_CTRL_SCAN=0,
++ LPS_CTRL_JOINBSS=1,
++ LPS_CTRL_CONNECT=2,
++ LPS_CTRL_DISCONNECT=3,
++ LPS_CTRL_SPECIAL_PACKET=4,
++};
++
++enum RFINTFS {
++ SWSI,
++ HWSI,
++ HWPI,
++};
++
++/*
++Caller Mode: Infra, Ad-HoC(C)
++
++Notes: To enter USB suspend mode
++
++Command Mode
++
++*/
++struct usb_suspend_parm {
++ u32 action;// 1: sleep, 0:resume
++};
++
++/*
++Caller Mode: Infra, Ad-HoC
++
++Notes: To join a known BSS.
++
++Command-Event Mode
++
++*/
++
++/*
++Caller Mode: Infra, Ad-Hoc
++
++Notes: To join the specified bss
++
++Command Event Mode
++
++*/
++struct joinbss_parm {
++ WLAN_BSSID_EX network;
++};
++
++/*
++Caller Mode: Infra, Ad-HoC(C)
++
++Notes: To disconnect the current associated BSS
++
++Command Mode
++
++*/
++struct disconnect_parm {
++ u32 deauth_timeout_ms;
++};
++
++/*
++Caller Mode: AP, Ad-HoC(M)
++
++Notes: To create a BSS
++
++Command Mode
++*/
++struct createbss_parm {
++ WLAN_BSSID_EX network;
++};
++
++/*
++Caller Mode: AP, Ad-HoC, Infra
++
++Notes: To set the NIC mode of RTL8711
++
++Command Mode
++
++The definition of mode:
++
++#define IW_MODE_AUTO 0 // Let the driver decides which AP to join
++#define IW_MODE_ADHOC 1 // Single cell network (Ad-Hoc Clients)
++#define IW_MODE_INFRA 2 // Multi cell network, roaming, ..
++#define IW_MODE_MASTER 3 // Synchronisation master or Access Point
++#define IW_MODE_REPEAT 4 // Wireless Repeater (forwarder)
++#define IW_MODE_SECOND 5 // Secondary master/repeater (backup)
++#define IW_MODE_MONITOR 6 // Passive monitor (listen only)
++
++*/
++struct setopmode_parm {
++ u8 mode;
++ u8 rsvd[3];
++};
++
++/*
++Caller Mode: AP, Ad-HoC, Infra
++
++Notes: To ask RTL8711 performing site-survey
++
++Command-Event Mode
++
++*/
++
++#define RTW_SSID_SCAN_AMOUNT 9 // for WEXT_CSCAN_AMOUNT 9
++#define RTW_CHANNEL_SCAN_AMOUNT (14+37)
++struct sitesurvey_parm {
++ sint scan_mode; //active: 1, passive: 0
++ /* sint bsslimit; // 1 ~ 48 */
++ u8 ssid_num;
++ u8 ch_num;
++ NDIS_802_11_SSID ssid[RTW_SSID_SCAN_AMOUNT];
++ struct rtw_ieee80211_channel ch[RTW_CHANNEL_SCAN_AMOUNT];
++};
++
++/*
++Caller Mode: Any
++
++Notes: To set the auth type of RTL8711. open/shared/802.1x
++
++Command Mode
++
++*/
++struct setauth_parm {
++ u8 mode; //0: legacy open, 1: legacy shared 2: 802.1x
++ u8 _1x; //0: PSK, 1: TLS
++ u8 rsvd[2];
++};
++
++/*
++Caller Mode: Infra
++
++a. algorithm: wep40, wep104, tkip & aes
++b. keytype: grp key/unicast key
++c. key contents
++
++when shared key ==> keyid is the camid
++when 802.1x ==> keyid [0:1] ==> grp key
++when 802.1x ==> keyid > 2 ==> unicast key
++
++*/
++struct setkey_parm {
++ u8 algorithm; // encryption algorithm, could be none, wep40, TKIP, CCMP, wep104
++ u8 keyid;
++ u8 grpkey; // 1: this is the grpkey for 802.1x. 0: this is the unicast key for 802.1x
++ u8 set_tx; // 1: main tx key for wep. 0: other key.
++ u8 key[16]; // this could be 40 or 104
++};
++
++/*
++When in AP or Ad-Hoc mode, this is used to
++allocate an sw/hw entry for a newly associated sta.
++
++Command
++
++when shared key ==> algorithm/keyid
++
++*/
++struct set_stakey_parm {
++ u8 addr[ETH_ALEN];
++ u8 algorithm;
++ u8 id;// currently for erasing cam entry if algorithm == _NO_PRIVACY_
++ u8 key[16];
++};
++
++struct set_stakey_rsp {
++ u8 addr[ETH_ALEN];
++ u8 keyid;
++ u8 rsvd;
++};
++
++/*
++Caller Ad-Hoc/AP
++
++Command -Rsp(AID == CAMID) mode
++
++This is to force fw to add an sta_data entry per driver's request.
++
++FW will write an cam entry associated with it.
++
++*/
++struct set_assocsta_parm {
++ u8 addr[ETH_ALEN];
++};
++
++struct set_assocsta_rsp {
++ u8 cam_id;
++ u8 rsvd[3];
++};
++
++/*
++ Caller Ad-Hoc/AP
++
++ Command mode
++
++ This is to force fw to del an sta_data entry per driver's request
++
++ FW will invalidate the cam entry associated with it.
++
++*/
++struct del_assocsta_parm {
++ u8 addr[ETH_ALEN];
++};
++
++/*
++Caller Mode: AP/Ad-HoC(M)
++
++Notes: To notify fw that given staid has changed its power state
++
++Command Mode
++
++*/
++struct setstapwrstate_parm {
++ u8 staid;
++ u8 status;
++ u8 hwaddr[6];
++};
++
++/*
++Caller Mode: Any
++
++Notes: To setup the basic rate of RTL8711
++
++Command Mode
++
++*/
++struct setbasicrate_parm {
++ u8 basicrates[NumRates];
++};
++
++/*
++Caller Mode: Any
++
++Notes: To read the current basic rate
++
++Command-Rsp Mode
++
++*/
++struct getbasicrate_parm {
++ u32 rsvd;
++};
++
++struct getbasicrate_rsp {
++ u8 basicrates[NumRates];
++};
++
++/*
++Caller Mode: Any
++
++Notes: To setup the data rate of RTL8711
++
++Command Mode
++
++*/
++struct setdatarate_parm {
++#ifdef MP_FIRMWARE_OFFLOAD
++ u32 curr_rateidx;
++#else
++ u8 mac_id;
++ u8 datarates[NumRates];
++#endif
++};
++
++/*
++Caller Mode: Any
++
++Notes: To read the current data rate
++
++Command-Rsp Mode
++
++*/
++struct getdatarate_parm {
++ u32 rsvd;
++
++};
++struct getdatarate_rsp {
++ u8 datarates[NumRates];
++};
++
++
++/*
++Caller Mode: Any
++AP: AP can use the info for the contents of beacon frame
++Infra: STA can use the info when sitesurveying
++Ad-HoC(M): Like AP
++Ad-HoC(C): Like STA
++
++
++Notes: To set the phy capability of the NIC
++
++Command Mode
++
++*/
++
++struct setphyinfo_parm {
++ struct regulatory_class class_sets[NUM_REGULATORYS];
++ u8 status;
++};
++
++struct getphyinfo_parm {
++ u32 rsvd;
++};
++
++struct getphyinfo_rsp {
++ struct regulatory_class class_sets[NUM_REGULATORYS];
++ u8 status;
++};
++
++/*
++Caller Mode: Any
++
++Notes: To set the channel/modem/band
++This command will be used when channel/modem/band is changed.
++
++Command Mode
++
++*/
++struct setphy_parm {
++ u8 rfchannel;
++ u8 modem;
++};
++
++/*
++Caller Mode: Any
++
++Notes: To get the current setting of channel/modem/band
++
++Command-Rsp Mode
++
++*/
++struct getphy_parm {
++ u32 rsvd;
++
++};
++struct getphy_rsp {
++ u8 rfchannel;
++ u8 modem;
++};
++
++struct readBB_parm {
++ u8 offset;
++};
++struct readBB_rsp {
++ u8 value;
++};
++
++struct readTSSI_parm {
++ u8 offset;
++};
++struct readTSSI_rsp {
++ u8 value;
++};
++
++struct writeBB_parm {
++ u8 offset;
++ u8 value;
++};
++
++struct readRF_parm {
++ u8 offset;
++};
++struct readRF_rsp {
++ u32 value;
++};
++
++struct writeRF_parm {
++ u32 offset;
++ u32 value;
++};
++
++struct getrfintfs_parm {
++ u8 rfintfs;
++};
++
++
++struct Tx_Beacon_param
++{
++ WLAN_BSSID_EX network;
++};
++
++/*
++ Notes: This command is used for H2C/C2H loopback testing
++
++ mac[0] == 0
++ ==> CMD mode, return H2C_SUCCESS.
++ The following condition must be ture under CMD mode
++ mac[1] == mac[4], mac[2] == mac[3], mac[0]=mac[5]= 0;
++ s0 == 0x1234, s1 == 0xabcd, w0 == 0x78563412, w1 == 0x5aa5def7;
++ s2 == (b1 << 8 | b0);
++
++ mac[0] == 1
++ ==> CMD_RSP mode, return H2C_SUCCESS_RSP
++
++ The rsp layout shall be:
++ rsp: parm:
++ mac[0] = mac[5];
++ mac[1] = mac[4];
++ mac[2] = mac[3];
++ mac[3] = mac[2];
++ mac[4] = mac[1];
++ mac[5] = mac[0];
++ s0 = s1;
++ s1 = swap16(s0);
++ w0 = swap32(w1);
++ b0 = b1
++ s2 = s0 + s1
++ b1 = b0
++ w1 = w0
++
++ mac[0] == 2
++ ==> CMD_EVENT mode, return H2C_SUCCESS
++ The event layout shall be:
++ event: parm:
++ mac[0] = mac[5];
++ mac[1] = mac[4];
++ mac[2] = event's sequence number, starting from 1 to parm's marc[3]
++ mac[3] = mac[2];
++ mac[4] = mac[1];
++ mac[5] = mac[0];
++ s0 = swap16(s0) - event.mac[2];
++ s1 = s1 + event.mac[2];
++ w0 = swap32(w0);
++ b0 = b1
++ s2 = s0 + event.mac[2]
++ b1 = b0
++ w1 = swap32(w1) - event.mac[2];
++
++ parm->mac[3] is the total event counts that host requested.
++
++
++ event will be the same with the cmd's param.
++
++*/
++
++#ifdef CONFIG_H2CLBK
++
++struct seth2clbk_parm {
++ u8 mac[6];
++ u16 s0;
++ u16 s1;
++ u32 w0;
++ u8 b0;
++ u16 s2;
++ u8 b1;
++ u32 w1;
++};
++
++struct geth2clbk_parm {
++ u32 rsv;
++};
++
++struct geth2clbk_rsp {
++ u8 mac[6];
++ u16 s0;
++ u16 s1;
++ u32 w0;
++ u8 b0;
++ u16 s2;
++ u8 b1;
++ u32 w1;
++};
++
++#endif /* CONFIG_H2CLBK */
++
++// CMD param Formart for driver extra cmd handler
++struct drvextra_cmd_parm {
++ int ec_id; //extra cmd id
++ int type_size; // Can use this field as the type id or command size
++ unsigned char *pbuf;
++};
++
++/*------------------- Below are used for RF/BB tunning ---------------------*/
++
++struct setantenna_parm {
++ u8 tx_antset;
++ u8 rx_antset;
++ u8 tx_antenna;
++ u8 rx_antenna;
++};
++
++struct enrateadaptive_parm {
++ u32 en;
++};
++
++struct settxagctbl_parm {
++ u32 txagc[MAX_RATES_LENGTH];
++};
++
++struct gettxagctbl_parm {
++ u32 rsvd;
++};
++struct gettxagctbl_rsp {
++ u32 txagc[MAX_RATES_LENGTH];
++};
++
++struct setagcctrl_parm {
++ u32 agcctrl; // 0: pure hw, 1: fw
++};
++
++
++struct setssup_parm {
++ u32 ss_ForceUp[MAX_RATES_LENGTH];
++};
++
++struct getssup_parm {
++ u32 rsvd;
++};
++struct getssup_rsp {
++ u8 ss_ForceUp[MAX_RATES_LENGTH];
++};
++
++
++struct setssdlevel_parm {
++ u8 ss_DLevel[MAX_RATES_LENGTH];
++};
++
++struct getssdlevel_parm {
++ u32 rsvd;
++};
++struct getssdlevel_rsp {
++ u8 ss_DLevel[MAX_RATES_LENGTH];
++};
++
++struct setssulevel_parm {
++ u8 ss_ULevel[MAX_RATES_LENGTH];
++};
++
++struct getssulevel_parm {
++ u32 rsvd;
++};
++struct getssulevel_rsp {
++ u8 ss_ULevel[MAX_RATES_LENGTH];
++};
++
++
++struct setcountjudge_parm {
++ u8 count_judge[MAX_RATES_LENGTH];
++};
++
++struct getcountjudge_parm {
++ u32 rsvd;
++};
++struct getcountjudge_rsp {
++ u8 count_judge[MAX_RATES_LENGTH];
++};
++
++
++struct setratable_parm {
++ u8 ss_ForceUp[NumRates];
++ u8 ss_ULevel[NumRates];
++ u8 ss_DLevel[NumRates];
++ u8 count_judge[NumRates];
++};
++
++struct getratable_parm {
++ uint rsvd;
++};
++struct getratable_rsp {
++ u8 ss_ForceUp[NumRates];
++ u8 ss_ULevel[NumRates];
++ u8 ss_DLevel[NumRates];
++ u8 count_judge[NumRates];
++};
++
++
++//to get TX,RX retry count
++struct gettxretrycnt_parm{
++ unsigned int rsvd;
++};
++struct gettxretrycnt_rsp{
++ unsigned long tx_retrycnt;
++};
++
++struct getrxretrycnt_parm{
++ unsigned int rsvd;
++};
++struct getrxretrycnt_rsp{
++ unsigned long rx_retrycnt;
++};
++
++//to get BCNOK,BCNERR count
++struct getbcnokcnt_parm{
++ unsigned int rsvd;
++};
++struct getbcnokcnt_rsp{
++ unsigned long bcnokcnt;
++};
++
++struct getbcnerrcnt_parm{
++ unsigned int rsvd;
++};
++struct getbcnerrcnt_rsp{
++ unsigned long bcnerrcnt;
++};
++
++// to get current TX power level
++struct getcurtxpwrlevel_parm{
++ unsigned int rsvd;
++};
++struct getcurtxpwrlevel_rsp{
++ unsigned short tx_power;
++};
++
++struct setprobereqextraie_parm {
++ unsigned char e_id;
++ unsigned char ie_len;
++ unsigned char ie[0];
++};
++
++struct setassocreqextraie_parm {
++ unsigned char e_id;
++ unsigned char ie_len;
++ unsigned char ie[0];
++};
++
++struct setproberspextraie_parm {
++ unsigned char e_id;
++ unsigned char ie_len;
++ unsigned char ie[0];
++};
++
++struct setassocrspextraie_parm {
++ unsigned char e_id;
++ unsigned char ie_len;
++ unsigned char ie[0];
++};
++
++
++struct addBaReq_parm
++{
++ unsigned int tid;
++ u8 addr[ETH_ALEN];
++};
++
++/*H2C Handler index: 46 */
++struct set_ch_parm {
++ u8 ch;
++ u8 bw;
++ u8 ch_offset;
++};
++
++#ifdef MP_FIRMWARE_OFFLOAD
++/*H2C Handler index: 47 */
++struct SetTxPower_parm
++{
++ u8 TxPower;
++};
++
++/*H2C Handler index: 48 */
++struct SwitchAntenna_parm
++{
++ u16 antenna_tx;
++ u16 antenna_rx;
++// R_ANTENNA_SELECT_CCK cck_txrx;
++ u8 cck_txrx;
++};
++
++/*H2C Handler index: 49 */
++struct SetCrystalCap_parm
++{
++ u32 curr_crystalcap;
++};
++
++/*H2C Handler index: 50 */
++struct SetSingleCarrierTx_parm
++{
++ u8 bStart;
++};
++
++/*H2C Handler index: 51 */
++struct SetSingleToneTx_parm
++{
++ u8 bStart;
++ u8 curr_rfpath;
++};
++
++/*H2C Handler index: 52 */
++struct SetCarrierSuppressionTx_parm
++{
++ u8 bStart;
++ u32 curr_rateidx;
++};
++
++/*H2C Handler index: 53 */
++struct SetContinuousTx_parm
++{
++ u8 bStart;
++ u8 CCK_flag; /*1:CCK 2:OFDM*/
++ u32 curr_rateidx;
++};
++
++/*H2C Handler index: 54 */
++struct SwitchBandwidth_parm
++{
++ u8 curr_bandwidth;
++};
++
++#endif /* MP_FIRMWARE_OFFLOAD */
++
++/*H2C Handler index: 59 */
++struct SetChannelPlan_param
++{
++ u8 channel_plan;
++};
++
++/*H2C Handler index: 60 */
++struct LedBlink_param
++{
++ PLED_871x pLed;
++};
++
++/*H2C Handler index: 61 */
++struct SetChannelSwitch_param
++{
++ u8 new_ch_no;
++};
++
++/*H2C Handler index: 62 */
++struct TDLSoption_param
++{
++ u8 addr[ETH_ALEN];
++ u8 option;
++};
++
++#define GEN_CMD_CODE(cmd) cmd ## _CMD_
++
++
++/*
++
++Result:
++0x00: success
++0x01: sucess, and check Response.
++0x02: cmd ignored due to duplicated sequcne number
++0x03: cmd dropped due to invalid cmd code
++0x04: reserved.
++
++*/
++
++#define H2C_RSP_OFFSET 512
++
++#define H2C_SUCCESS 0x00
++#define H2C_SUCCESS_RSP 0x01
++#define H2C_DUPLICATED 0x02
++#define H2C_DROPPED 0x03
++#define H2C_PARAMETERS_ERROR 0x04
++#define H2C_REJECTED 0x05
++#define H2C_CMD_OVERFLOW 0x06
++#define H2C_RESERVED 0x07
++
++extern u8 rtw_setassocsta_cmd(_adapter *padapter, u8 *mac_addr);
++extern u8 rtw_setstandby_cmd(_adapter *padapter, uint action);
++u8 rtw_sitesurvey_cmd(_adapter *padapter, NDIS_802_11_SSID *ssid, int ssid_num, struct rtw_ieee80211_channel *ch, int ch_num);
++extern u8 rtw_createbss_cmd(_adapter *padapter);
++extern u8 rtw_createbss_cmd_ex(_adapter *padapter, unsigned char *pbss, unsigned int sz);
++extern u8 rtw_setphy_cmd(_adapter *padapter, u8 modem, u8 ch);
++extern u8 rtw_setstakey_cmd(_adapter *padapter, u8 *psta, u8 unicast_key);
++extern u8 rtw_clearstakey_cmd(_adapter *padapter, u8 *psta, u8 entry, u8 enqueue);
++extern u8 rtw_joinbss_cmd(_adapter *padapter, struct wlan_network* pnetwork);
++u8 rtw_disassoc_cmd(_adapter *padapter, u32 deauth_timeout_ms, bool enqueue);
++extern u8 rtw_setopmode_cmd(_adapter *padapter, NDIS_802_11_NETWORK_INFRASTRUCTURE networktype);
++extern u8 rtw_setdatarate_cmd(_adapter *padapter, u8 *rateset);
++extern u8 rtw_setbasicrate_cmd(_adapter *padapter, u8 *rateset);
++extern u8 rtw_setbbreg_cmd(_adapter * padapter, u8 offset, u8 val);
++extern u8 rtw_setrfreg_cmd(_adapter * padapter, u8 offset, u32 val);
++extern u8 rtw_getbbreg_cmd(_adapter * padapter, u8 offset, u8 * pval);
++extern u8 rtw_getrfreg_cmd(_adapter * padapter, u8 offset, u8 * pval);
++extern u8 rtw_setrfintfs_cmd(_adapter *padapter, u8 mode);
++extern u8 rtw_setrttbl_cmd(_adapter *padapter, struct setratable_parm *prate_table);
++extern u8 rtw_getrttbl_cmd(_adapter *padapter, struct getratable_rsp *pval);
++
++extern u8 rtw_gettssi_cmd(_adapter *padapter, u8 offset,u8 *pval);
++extern u8 rtw_setfwdig_cmd(_adapter*padapter, u8 type);
++extern u8 rtw_setfwra_cmd(_adapter*padapter, u8 type);
++
++extern u8 rtw_addbareq_cmd(_adapter*padapter, u8 tid, u8 *addr);
++// add for CONFIG_IEEE80211W, none 11w also can use
++extern u8 rtw_reset_securitypriv_cmd(_adapter*padapter);
++extern u8 rtw_free_assoc_resources_cmd(_adapter *padapter);
++extern u8 rtw_dynamic_chk_wk_cmd(_adapter *adapter);
++
++u8 rtw_lps_ctrl_wk_cmd(_adapter*padapter, u8 lps_ctrl_type, u8 enqueue);
++
++#ifdef CONFIG_ANTENNA_DIVERSITY
++extern u8 rtw_antenna_select_cmd(_adapter*padapter, u8 antenna,u8 enqueue);
++#endif
++
++extern u8 rtw_ps_cmd(_adapter*padapter);
++
++
++#ifdef CONFIG_AP_MODE
++u8 rtw_chk_hi_queue_cmd(_adapter*padapter);
++#endif
++
++u8 rtw_set_ch_cmd(_adapter*padapter, u8 ch, u8 bw, u8 ch_offset, u8 enqueue);
++extern u8 rtw_set_chplan_cmd(_adapter*padapter, u8 chplan, u8 enqueue);
++extern u8 rtw_led_blink_cmd(_adapter*padapter, PLED_871x pLed);
++extern u8 rtw_set_csa_cmd(_adapter*padapter, u8 new_ch_no);
++extern u8 rtw_tdls_cmd(_adapter*padapter, u8 *addr, u8 option);
++
++extern u8 rtw_c2h_wk_cmd(PADAPTER padapter, u8 *c2h_evt);
++
++u8 rtw_drvextra_cmd_hdl(_adapter *padapter, unsigned char *pbuf);
++
++extern void rtw_survey_cmd_callback(_adapter *padapter, struct cmd_obj *pcmd);
++extern void rtw_disassoc_cmd_callback(_adapter *padapter, struct cmd_obj *pcmd);
++extern void rtw_joinbss_cmd_callback(_adapter *padapter, struct cmd_obj *pcmd);
++extern void rtw_createbss_cmd_callback(_adapter *padapter, struct cmd_obj *pcmd);
++extern void rtw_getbbrfreg_cmdrsp_callback(_adapter *padapter, struct cmd_obj *pcmd);
++extern void rtw_readtssi_cmdrsp_callback(_adapter* padapter, struct cmd_obj *pcmd);
++
++extern void rtw_setstaKey_cmdrsp_callback(_adapter *padapter, struct cmd_obj *pcmd);
++extern void rtw_setassocsta_cmdrsp_callback(_adapter *padapter, struct cmd_obj *pcmd);
++extern void rtw_getrttbl_cmdrsp_callback(_adapter *padapter, struct cmd_obj *pcmd);
++
++
++struct _cmd_callback {
++ u32 cmd_code;
++ void (*callback)(_adapter *padapter, struct cmd_obj *cmd);
++};
++
++enum rtw_h2c_cmd
++{
++ GEN_CMD_CODE(_Read_MACREG) , /*0*/
++ GEN_CMD_CODE(_Write_MACREG) ,
++ GEN_CMD_CODE(_Read_BBREG) ,
++ GEN_CMD_CODE(_Write_BBREG) ,
++ GEN_CMD_CODE(_Read_RFREG) ,
++ GEN_CMD_CODE(_Write_RFREG) , /*5*/
++ GEN_CMD_CODE(_Read_EEPROM) ,
++ GEN_CMD_CODE(_Write_EEPROM) ,
++ GEN_CMD_CODE(_Read_EFUSE) ,
++ GEN_CMD_CODE(_Write_EFUSE) ,
++
++ GEN_CMD_CODE(_Read_CAM) , /*10*/
++ GEN_CMD_CODE(_Write_CAM) ,
++ GEN_CMD_CODE(_setBCNITV),
++ GEN_CMD_CODE(_setMBIDCFG),
++ GEN_CMD_CODE(_JoinBss), /*14*/
++ GEN_CMD_CODE(_DisConnect) , /*15*/
++ GEN_CMD_CODE(_CreateBss) ,
++ GEN_CMD_CODE(_SetOpMode) ,
++ GEN_CMD_CODE(_SiteSurvey), /*18*/
++ GEN_CMD_CODE(_SetAuth) ,
++
++ GEN_CMD_CODE(_SetKey) , /*20*/
++ GEN_CMD_CODE(_SetStaKey) ,
++ GEN_CMD_CODE(_SetAssocSta) ,
++ GEN_CMD_CODE(_DelAssocSta) ,
++ GEN_CMD_CODE(_SetStaPwrState) ,
++ GEN_CMD_CODE(_SetBasicRate) , /*25*/
++ GEN_CMD_CODE(_GetBasicRate) ,
++ GEN_CMD_CODE(_SetDataRate) ,
++ GEN_CMD_CODE(_GetDataRate) ,
++ GEN_CMD_CODE(_SetPhyInfo) ,
++
++ GEN_CMD_CODE(_GetPhyInfo) , /*30*/
++ GEN_CMD_CODE(_SetPhy) ,
++ GEN_CMD_CODE(_GetPhy) ,
++ GEN_CMD_CODE(_readRssi) ,
++ GEN_CMD_CODE(_readGain) ,
++ GEN_CMD_CODE(_SetAtim) , /*35*/
++ GEN_CMD_CODE(_SetPwrMode) ,
++ GEN_CMD_CODE(_JoinbssRpt),
++ GEN_CMD_CODE(_SetRaTable) ,
++ GEN_CMD_CODE(_GetRaTable) ,
++
++ GEN_CMD_CODE(_GetCCXReport), /*40*/
++ GEN_CMD_CODE(_GetDTMReport),
++ GEN_CMD_CODE(_GetTXRateStatistics),
++ GEN_CMD_CODE(_SetUsbSuspend),
++ GEN_CMD_CODE(_SetH2cLbk),
++ GEN_CMD_CODE(_AddBAReq) , /*45*/
++ GEN_CMD_CODE(_SetChannel), /*46*/
++ GEN_CMD_CODE(_SetTxPower),
++ GEN_CMD_CODE(_SwitchAntenna),
++ GEN_CMD_CODE(_SetCrystalCap),
++ GEN_CMD_CODE(_SetSingleCarrierTx), /*50*/
++
++ GEN_CMD_CODE(_SetSingleToneTx),/*51*/
++ GEN_CMD_CODE(_SetCarrierSuppressionTx),
++ GEN_CMD_CODE(_SetContinuousTx),
++ GEN_CMD_CODE(_SwitchBandwidth), /*54*/
++ GEN_CMD_CODE(_TX_Beacon), /*55*/
++
++ GEN_CMD_CODE(_Set_MLME_EVT), /*56*/
++ GEN_CMD_CODE(_Set_Drv_Extra), /*57*/
++ GEN_CMD_CODE(_Set_H2C_MSG), /*58*/
++
++ GEN_CMD_CODE(_SetChannelPlan), /*59*/
++ GEN_CMD_CODE(_LedBlink), /*60*/
++
++ GEN_CMD_CODE(_SetChannelSwitch), /*61*/
++ GEN_CMD_CODE(_TDLS), /*62*/
++
++ MAX_H2CCMD
++};
++
++#define _GetBBReg_CMD_ _Read_BBREG_CMD_
++#define _SetBBReg_CMD_ _Write_BBREG_CMD_
++#define _GetRFReg_CMD_ _Read_RFREG_CMD_
++#define _SetRFReg_CMD_ _Write_RFREG_CMD_
++
++#ifdef _RTW_CMD_C_
++struct _cmd_callback rtw_cmd_callback[] =
++{
++ {GEN_CMD_CODE(_Read_MACREG), NULL}, /*0*/
++ {GEN_CMD_CODE(_Write_MACREG), NULL},
++ {GEN_CMD_CODE(_Read_BBREG), &rtw_getbbrfreg_cmdrsp_callback},
++ {GEN_CMD_CODE(_Write_BBREG), NULL},
++ {GEN_CMD_CODE(_Read_RFREG), &rtw_getbbrfreg_cmdrsp_callback},
++ {GEN_CMD_CODE(_Write_RFREG), NULL}, /*5*/
++ {GEN_CMD_CODE(_Read_EEPROM), NULL},
++ {GEN_CMD_CODE(_Write_EEPROM), NULL},
++ {GEN_CMD_CODE(_Read_EFUSE), NULL},
++ {GEN_CMD_CODE(_Write_EFUSE), NULL},
++
++ {GEN_CMD_CODE(_Read_CAM), NULL}, /*10*/
++ {GEN_CMD_CODE(_Write_CAM), NULL},
++ {GEN_CMD_CODE(_setBCNITV), NULL},
++ {GEN_CMD_CODE(_setMBIDCFG), NULL},
++ {GEN_CMD_CODE(_JoinBss), &rtw_joinbss_cmd_callback}, /*14*/
++ {GEN_CMD_CODE(_DisConnect), &rtw_disassoc_cmd_callback}, /*15*/
++ {GEN_CMD_CODE(_CreateBss), &rtw_createbss_cmd_callback},
++ {GEN_CMD_CODE(_SetOpMode), NULL},
++ {GEN_CMD_CODE(_SiteSurvey), &rtw_survey_cmd_callback}, /*18*/
++ {GEN_CMD_CODE(_SetAuth), NULL},
++
++ {GEN_CMD_CODE(_SetKey), NULL}, /*20*/
++ {GEN_CMD_CODE(_SetStaKey), &rtw_setstaKey_cmdrsp_callback},
++ {GEN_CMD_CODE(_SetAssocSta), &rtw_setassocsta_cmdrsp_callback},
++ {GEN_CMD_CODE(_DelAssocSta), NULL},
++ {GEN_CMD_CODE(_SetStaPwrState), NULL},
++ {GEN_CMD_CODE(_SetBasicRate), NULL}, /*25*/
++ {GEN_CMD_CODE(_GetBasicRate), NULL},
++ {GEN_CMD_CODE(_SetDataRate), NULL},
++ {GEN_CMD_CODE(_GetDataRate), NULL},
++ {GEN_CMD_CODE(_SetPhyInfo), NULL},
++
++ {GEN_CMD_CODE(_GetPhyInfo), NULL}, /*30*/
++ {GEN_CMD_CODE(_SetPhy), NULL},
++ {GEN_CMD_CODE(_GetPhy), NULL},
++ {GEN_CMD_CODE(_readRssi), NULL},
++ {GEN_CMD_CODE(_readGain), NULL},
++ {GEN_CMD_CODE(_SetAtim), NULL}, /*35*/
++ {GEN_CMD_CODE(_SetPwrMode), NULL},
++ {GEN_CMD_CODE(_JoinbssRpt), NULL},
++ {GEN_CMD_CODE(_SetRaTable), NULL},
++ {GEN_CMD_CODE(_GetRaTable) , NULL},
++
++ {GEN_CMD_CODE(_GetCCXReport), NULL}, /*40*/
++ {GEN_CMD_CODE(_GetDTMReport), NULL},
++ {GEN_CMD_CODE(_GetTXRateStatistics), NULL},
++ {GEN_CMD_CODE(_SetUsbSuspend), NULL},
++ {GEN_CMD_CODE(_SetH2cLbk), NULL},
++ {GEN_CMD_CODE(_AddBAReq), NULL}, /*45*/
++ {GEN_CMD_CODE(_SetChannel), NULL}, /*46*/
++ {GEN_CMD_CODE(_SetTxPower), NULL},
++ {GEN_CMD_CODE(_SwitchAntenna), NULL},
++ {GEN_CMD_CODE(_SetCrystalCap), NULL},
++ {GEN_CMD_CODE(_SetSingleCarrierTx), NULL}, /*50*/
++
++ {GEN_CMD_CODE(_SetSingleToneTx), NULL}, /*51*/
++ {GEN_CMD_CODE(_SetCarrierSuppressionTx), NULL},
++ {GEN_CMD_CODE(_SetContinuousTx), NULL},
++ {GEN_CMD_CODE(_SwitchBandwidth), NULL}, /*54*/
++ {GEN_CMD_CODE(_TX_Beacon), NULL},/*55*/
++
++ {GEN_CMD_CODE(_Set_MLME_EVT), NULL},/*56*/
++ {GEN_CMD_CODE(_Set_Drv_Extra), NULL},/*57*/
++ {GEN_CMD_CODE(_Set_H2C_MSG), NULL},/*58*/
++ {GEN_CMD_CODE(_SetChannelPlan), NULL},/*59*/
++ {GEN_CMD_CODE(_LedBlink), NULL},/*60*/
++
++ {GEN_CMD_CODE(_SetChannelSwitch), NULL},/*61*/
++ {GEN_CMD_CODE(_TDLS), NULL},/*62*/
++};
++#endif
++
++#endif // _CMD_H_
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtw_debug.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtw_debug.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtw_debug.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtw_debug.h 2015-07-28 01:20:58.321597318 +0200
+@@ -0,0 +1,537 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef __RTW_DEBUG_H__
++#define __RTW_DEBUG_H__
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++
++
++#define _no_debug_ 0
++#define _drv_emerg_ 1
++#define _drv_alert_ 2
++#define _drv_crit_ 3
++#define _drv_err_ 4
++#define _drv_warning_ 5
++#define _drv_notice_ 6
++#define _drv_info_ 7
++#define _drv_dump_ 8
++#define _drv_debug_ 9
++#define _drv_always_ _drv_emerg_
++
++#define _module_rtl871x_xmit_c_ BIT(0)
++#define _module_xmit_osdep_c_ BIT(1)
++#define _module_rtl871x_recv_c_ BIT(2)
++#define _module_recv_osdep_c_ BIT(3)
++#define _module_rtl871x_mlme_c_ BIT(4)
++#define _module_mlme_osdep_c_ BIT(5)
++#define _module_rtl871x_sta_mgt_c_ BIT(6)
++#define _module_rtl871x_cmd_c_ BIT(7)
++#define _module_cmd_osdep_c_ BIT(8)
++#define _module_rtl871x_io_c_ BIT(9)
++#define _module_io_osdep_c_ BIT(10)
++#define _module_os_intfs_c_ BIT(11)
++#define _module_rtl871x_security_c_ BIT(12)
++#define _module_rtl871x_eeprom_c_ BIT(13)
++#define _module_hal_init_c_ BIT(14)
++#define _module_hci_hal_init_c_ BIT(15)
++#define _module_rtl871x_ioctl_c_ BIT(16)
++#define _module_rtl871x_ioctl_set_c_ BIT(17)
++#define _module_rtl871x_ioctl_query_c_ BIT(18)
++#define _module_rtl871x_pwrctrl_c_ BIT(19)
++#define _module_hci_intfs_c_ BIT(20)
++#define _module_hci_ops_c_ BIT(21)
++#define _module_osdep_service_c_ BIT(22)
++#define _module_mp_ BIT(23)
++#define _module_hci_ops_os_c_ BIT(24)
++#define _module_rtl871x_ioctl_os_c BIT(25)
++#define _module_rtl8712_cmd_c_ BIT(26)
++//#define _module_efuse_ BIT(27)
++#define _module_rtl8192c_xmit_c_ BIT(28)
++#define _module_hal_xmit_c_ BIT(28)
++#define _module_efuse_ BIT(29)
++#define _module_rtl8712_recv_c_ BIT(30)
++#define _module_rtl8712_led_c_ BIT(31)
++
++#undef _MODULE_DEFINE_
++
++#if defined _RTW_XMIT_C_
++ #define _MODULE_DEFINE_ _module_rtl871x_xmit_c_
++#elif defined _XMIT_OSDEP_C_
++ #define _MODULE_DEFINE_ _module_xmit_osdep_c_
++#elif defined _RTW_RECV_C_
++ #define _MODULE_DEFINE_ _module_rtl871x_recv_c_
++#elif defined _RECV_OSDEP_C_
++ #define _MODULE_DEFINE_ _module_recv_osdep_c_
++#elif defined _RTW_MLME_C_
++ #define _MODULE_DEFINE_ _module_rtl871x_mlme_c_
++#elif defined _MLME_OSDEP_C_
++ #define _MODULE_DEFINE_ _module_mlme_osdep_c_
++#elif defined _RTW_MLME_EXT_C_
++ #define _MODULE_DEFINE_ 1
++#elif defined _RTW_STA_MGT_C_
++ #define _MODULE_DEFINE_ _module_rtl871x_sta_mgt_c_
++#elif defined _RTW_CMD_C_
++ #define _MODULE_DEFINE_ _module_rtl871x_cmd_c_
++#elif defined _CMD_OSDEP_C_
++ #define _MODULE_DEFINE_ _module_cmd_osdep_c_
++#elif defined _RTW_IO_C_
++ #define _MODULE_DEFINE_ _module_rtl871x_io_c_
++#elif defined _IO_OSDEP_C_
++ #define _MODULE_DEFINE_ _module_io_osdep_c_
++#elif defined _OS_INTFS_C_
++ #define _MODULE_DEFINE_ _module_os_intfs_c_
++#elif defined _RTW_SECURITY_C_
++ #define _MODULE_DEFINE_ _module_rtl871x_security_c_
++#elif defined _RTW_EEPROM_C_
++ #define _MODULE_DEFINE_ _module_rtl871x_eeprom_c_
++#elif defined _HAL_INTF_C_
++ #define _MODULE_DEFINE_ _module_hal_init_c_
++#elif defined _HCI_HAL_INIT_C_
++ #define _MODULE_DEFINE_ _module_hci_hal_init_c_
++#elif defined _RTL871X_IOCTL_C_
++ #define _MODULE_DEFINE_ _module_rtl871x_ioctl_c_
++#elif defined _RTL871X_IOCTL_SET_C_
++ #define _MODULE_DEFINE_ _module_rtl871x_ioctl_set_c_
++#elif defined _RTL871X_IOCTL_QUERY_C_
++ #define _MODULE_DEFINE_ _module_rtl871x_ioctl_query_c_
++#elif defined _RTL871X_PWRCTRL_C_
++ #define _MODULE_DEFINE_ _module_rtl871x_pwrctrl_c_
++#elif defined _RTW_PWRCTRL_C_
++ #define _MODULE_DEFINE_ 1
++#elif defined _HCI_INTF_C_
++ #define _MODULE_DEFINE_ _module_hci_intfs_c_
++#elif defined _HCI_OPS_C_
++ #define _MODULE_DEFINE_ _module_hci_ops_c_
++#elif defined _SDIO_OPS_C_
++ #define _MODULE_DEFINE_ 1
++#elif defined _OSDEP_HCI_INTF_C_
++ #define _MODULE_DEFINE_ _module_hci_intfs_c_
++#elif defined _OSDEP_SERVICE_C_
++ #define _MODULE_DEFINE_ _module_osdep_service_c_
++#elif defined _HCI_OPS_OS_C_
++ #define _MODULE_DEFINE_ _module_hci_ops_os_c_
++#elif defined _RTL871X_IOCTL_LINUX_C_
++ #define _MODULE_DEFINE_ _module_rtl871x_ioctl_os_c
++#elif defined _RTL8712_CMD_C_
++ #define _MODULE_DEFINE_ _module_rtl8712_cmd_c_
++#elif defined _RTL8192C_XMIT_C_
++ #define _MODULE_DEFINE_ 1
++#elif defined _RTL8723AS_XMIT_C_
++ #define _MODULE_DEFINE_ 1
++#elif defined _RTL8712_RECV_C_
++ #define _MODULE_DEFINE_ _module_rtl8712_recv_c_
++#elif defined _RTL8192CU_RECV_C_
++ #define _MODULE_DEFINE_ _module_rtl8712_recv_c_
++#elif defined _RTL871X_MLME_EXT_C_
++ #define _MODULE_DEFINE_ _module_mlme_osdep_c_
++#elif defined _RTW_MP_C_
++ #define _MODULE_DEFINE_ _module_mp_
++#elif defined _RTW_MP_IOCTL_C_
++ #define _MODULE_DEFINE_ _module_mp_
++#elif defined _RTW_EFUSE_C_
++ #define _MODULE_DEFINE_ _module_efuse_
++#endif
++
++#ifdef PLATFORM_OS_CE
++extern void rtl871x_cedbg(const char *fmt, ...);
++#endif
++
++#define RT_TRACE(_Comp, _Level, Fmt) do{}while(0)
++#define _func_enter_ do{}while(0)
++#define _func_exit_ do{}while(0)
++#define RT_PRINT_DATA(_Comp, _Level, _TitleString, _HexData, _HexDataLen) do{}while(0)
++
++#undef _dbgdump
++
++#ifdef CONFIG_DEBUG_RTL871X
++
++#ifndef _RTL871X_DEBUG_C_
++ extern u32 GlobalDebugLevel;
++ extern u64 GlobalDebugComponents;
++#endif
++
++#ifdef PLATFORM_WINDOWS
++
++ #ifdef PLATFORM_OS_XP
++
++ #define _dbgdump DbgPrint
++
++ #elif defined PLATFORM_OS_CE
++
++ #define _dbgdump rtl871x_cedbg
++
++ #endif
++
++#elif defined PLATFORM_LINUX
++
++ #define _dbgdump printk
++
++#elif defined PLATFORM_FREEBSD
++
++ #define _dbgdump printf
++
++#endif
++
++#endif /* CONFIG_DEBUG_RTL871X */
++
++
++#if defined (_dbgdump) && defined (_MODULE_DEFINE_)
++
++ #undef RT_TRACE
++ #define RT_TRACE(_Comp, _Level, Fmt)\
++ do {\
++ if((_Comp & GlobalDebugComponents) && (_Level <= GlobalDebugLevel)) {\
++ _dbgdump("%s [0x%08x,%d]", RTL871X_MODULE_NAME, (unsigned int)_Comp, _Level);\
++ _dbgdump Fmt;\
++ }\
++ }while(0)
++
++#endif
++
++
++#if defined (_dbgdump)
++
++ #undef _func_enter_
++ #define _func_enter_ \
++ do { \
++ if (GlobalDebugLevel >= _drv_debug_) \
++ { \
++ _dbgdump("\n %s : %s enters at %d\n", RTL871X_MODULE_NAME, __FUNCTION__, __LINE__);\
++ } \
++ } while(0)
++
++ #undef _func_exit_
++ #define _func_exit_ \
++ do { \
++ if (GlobalDebugLevel >= _drv_debug_) \
++ { \
++ _dbgdump("\n %s : %s exits at %d\n", RTL871X_MODULE_NAME, __FUNCTION__, __LINE__); \
++ } \
++ } while(0)
++
++ #undef RT_PRINT_DATA
++ #define RT_PRINT_DATA(_Comp, _Level, _TitleString, _HexData, _HexDataLen) \
++ if(((_Comp) & GlobalDebugComponents) && (_Level <= GlobalDebugLevel)) \
++ { \
++ int __i; \
++ u8 *ptr = (u8 *)_HexData; \
++ _dbgdump("Rtl871x: "); \
++ _dbgdump(_TitleString); \
++ for( __i=0; __i<(int)_HexDataLen; __i++ ) \
++ { \
++ _dbgdump("%02X%s", ptr[__i], (((__i + 1) % 4) == 0)?" ":" "); \
++ if (((__i + 1) % 16) == 0) _dbgdump("\n"); \
++ } \
++ _dbgdump("\n"); \
++ }
++#endif
++
++
++#ifdef CONFIG_DEBUG_RTL819X
++
++#undef _dbgdump
++
++#ifdef PLATFORM_WINDOWS
++
++ #ifdef PLATFORM_OS_XP
++
++ #define _dbgdump DbgPrint
++
++ #elif defined PLATFORM_OS_CE
++
++ #define _dbgdump rtl871x_cedbg
++
++ #endif
++
++#elif defined PLATFORM_LINUX
++
++ #define _dbgdump printk
++
++#elif defined PLATFORM_FREEBSD
++
++ #define _dbgdump printf
++
++#endif
++
++#endif /* CONFIG_DEBUG_RTL819X */
++
++
++#ifdef PLATFORM_WINDOWS
++ #define DBG_871X do {} while(0)
++ #define MSG_8192C do {} while(0)
++ #define DBG_8192C do {} while(0)
++ #define WRN_8192C do {} while(0)
++ #define ERR_8192C do {} while(0)
++#endif
++
++#ifdef PLATFORM_LINUX
++ #define DBG_871X(x, ...) do {} while(0)
++ #define MSG_8192C(x, ...) do {} while(0)
++ #define DBG_8192C(x,...) do {} while(0)
++ #define WRN_8192C(x,...) do {} while(0)
++ #define ERR_8192C(x,...) do {} while(0)
++#endif
++
++#ifdef PLATFORM_FREEBSD
++ #define _dbgdump printf
++ #define DBG_871X(x, ...) do {} while(0)
++ #define MSG_8192C(x, ...) do {} while(0)
++ #define DBG_8192C(x,...) do {} while(0)
++ #define WRN_8192C(x,...) do {} while(0)
++ #define ERR_8192C(x,...) do {} while(0)
++#endif
++
++extern u32 GlobalDebugLevel;
++#define LOG_LEVEL(level, ...)\
++ do {\
++ if(level <= GlobalDebugLevel) {\
++ printk(__VA_ARGS__);\
++ }\
++ }while(0)
++
++#define DBG_871X_LEVEL LOG_LEVEL
++
++#if defined (_dbgdump)
++ #undef DBG_871X
++// #define DBG_871X _dbgdump
++ #define DBG_871X(...) LOG_LEVEL(_drv_emerg_ , __VA_ARGS__)
++
++ #undef MSG_8192C
++// #define MSG_8192C _dbgdump
++ #define MSG_8192C(...) LOG_LEVEL(_drv_emerg_ , __VA_ARGS__)
++
++ #undef DBG_8192C
++// #define DBG_8192C _dbgdump
++ #define DBG_8192C(...) LOG_LEVEL(_drv_emerg_ , __VA_ARGS__)
++
++
++ #undef WRN_8192C
++ #define WRN_8192C _dbgdump
++
++ #undef ERR_8192C
++ #define ERR_8192C _dbgdump
++#endif
++
++
++#ifdef CONFIG_PROC_DEBUG
++
++ int proc_get_drv_version(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data);
++
++ int proc_get_log_level(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data);
++
++ int proc_set_log_level(struct file *file, const char *buffer,
++ unsigned long count, void *data);
++
++#ifdef DBG_MEM_ALLOC
++ int proc_get_mstat(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data);
++#endif /* DBG_MEM_ALLOC */
++
++ int proc_get_write_reg(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data);
++
++ int proc_set_write_reg(struct file *file, const char *buffer,
++ unsigned long count, void *data);
++
++ int proc_get_read_reg(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data);
++
++ int proc_set_read_reg(struct file *file, const char *buffer,
++ unsigned long count, void *data);
++
++
++ int proc_get_fwstate(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data);
++
++ int proc_get_sec_info(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data);
++
++ int proc_get_mlmext_state(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data);
++
++ int proc_get_qos_option(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data);
++
++ int proc_get_ht_option(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data);
++
++ int proc_get_rf_info(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data);
++
++ int proc_get_ap_info(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data);
++
++ int proc_get_adapter_state(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data);
++
++ int proc_get_trx_info(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data);
++
++ int proc_get_mac_reg_dump1(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data);
++
++ int proc_get_mac_reg_dump2(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data);
++
++ int proc_get_mac_reg_dump3(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data);
++
++ int proc_get_bb_reg_dump1(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data);
++
++ int proc_get_bb_reg_dump2(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data);
++
++ int proc_get_bb_reg_dump3(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data);
++
++ int proc_get_rf_reg_dump1(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data);
++
++ int proc_get_rf_reg_dump2(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data);
++
++ int proc_get_rf_reg_dump3(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data);
++
++ int proc_get_rf_reg_dump4(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data);
++
++#ifdef CONFIG_AP_MODE
++
++ int proc_get_all_sta_info(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data);
++
++#endif
++
++#ifdef DBG_MEMORY_LEAK
++ int proc_get_malloc_cnt(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data);
++#endif
++
++#ifdef CONFIG_FIND_BEST_CHANNEL
++ int proc_get_best_channel(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data);
++ int proc_set_best_channel(struct file *file, const char *buffer,
++ unsigned long count, void *data);
++#endif
++
++ int proc_get_rx_signal(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data);
++
++ int proc_set_rx_signal(struct file *file, const char *buffer,
++ unsigned long count, void *data);
++
++ int proc_get_ht_enable(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data);
++
++ int proc_set_ht_enable(struct file *file, const char *buffer,
++ unsigned long count, void *data);
++
++ int proc_get_cbw40_enable(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data);
++
++ int proc_set_cbw40_enable(struct file *file, const char *buffer,
++ unsigned long count, void *data);
++
++ int proc_get_ampdu_enable(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data);
++
++ int proc_set_ampdu_enable(struct file *file, const char *buffer,
++ unsigned long count, void *data);
++
++ int proc_get_two_path_rssi(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data);
++
++ int proc_get_rx_stbc(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data);
++
++ int proc_set_rx_stbc(struct file *file, const char *buffer,
++ unsigned long count, void *data);
++
++
++ int proc_get_vid(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data);
++
++ int proc_get_pid(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data);
++
++ int proc_get_rssi_disp(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data);
++
++ int proc_set_rssi_disp(struct file *file, const char *buffer,
++ unsigned long count, void *data);
++
++#if defined(DBG_CONFIG_ERROR_DETECT)
++int proc_get_sreset(char *page, char **start, off_t offset, int count, int *eof, void *data);
++int proc_set_sreset(struct file *file, const char *buffer, unsigned long count, void *data);
++#endif /* DBG_CONFIG_ERROR_DETECT */
++
++#ifdef CONFIG_DM_ADAPTIVITY
++int proc_get_dm_adaptivity(char *page, char **start,
++ off_t offset, int count,
++ int *eof, void *data);
++int proc_set_dm_adaptivity(struct file *file, const char *buffer,
++ unsigned long count, void *data);
++#endif /* CONFIG_DM_ADAPTIVITY */
++
++#endif //CONFIG_PROC_DEBUG
++
++#endif //__RTW_DEBUG_H__
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtw_eeprom.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtw_eeprom.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtw_eeprom.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtw_eeprom.h 2015-07-28 01:20:58.321597318 +0200
+@@ -0,0 +1,152 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef __RTW_EEPROM_H__
++#define __RTW_EEPROM_H__
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++
++#define RTL8712_EEPROM_ID 0x8712
++#define EEPROM_MAX_SIZE 256
++#define CLOCK_RATE 50 //100us
++
++//- EEPROM opcodes
++#define EEPROM_READ_OPCODE 06
++#define EEPROM_WRITE_OPCODE 05
++#define EEPROM_ERASE_OPCODE 07
++#define EEPROM_EWEN_OPCODE 19 // Erase/write enable
++#define EEPROM_EWDS_OPCODE 16 // Erase/write disable
++
++//Country codes
++#define USA 0x555320
++#define EUROPE 0x1 //temp, should be provided later
++#define JAPAN 0x2 //temp, should be provided later
++
++#ifdef CONFIG_SDIO_HCI
++#define eeprom_cis0_sz 17
++#define eeprom_cis1_sz 50
++#endif
++
++#define EEPROM_CID_DEFAULT 0x0
++#define EEPROM_CID_ALPHA 0x1
++#define EEPROM_CID_Senao 0x3
++#define EEPROM_CID_NetCore 0x5
++#define EEPROM_CID_CAMEO 0X8
++#define EEPROM_CID_SITECOM 0x9
++#define EEPROM_CID_COREGA 0xB
++#define EEPROM_CID_EDIMAX_BELKIN 0xC
++#define EEPROM_CID_SERCOMM_BELKIN 0xE
++#define EEPROM_CID_CAMEO1 0xF
++#define EEPROM_CID_WNC_COREGA 0x12
++#define EEPROM_CID_CLEVO 0x13
++#define EEPROM_CID_WHQL 0xFE // added by chiyoko for dtm, 20090108
++
++//
++// Customer ID, note that:
++// This variable is initiailzed through EEPROM or registry,
++// however, its definition may be different with that in EEPROM for
++// EEPROM size consideration. So, we have to perform proper translation between them.
++// Besides, CustomerID of registry has precedence of that of EEPROM.
++// defined below. 060703, by rcnjko.
++//
++typedef enum _RT_CUSTOMER_ID
++{
++ RT_CID_DEFAULT = 0,
++ RT_CID_8187_ALPHA0 = 1,
++ RT_CID_8187_SERCOMM_PS = 2,
++ RT_CID_8187_HW_LED = 3,
++ RT_CID_8187_NETGEAR = 4,
++ RT_CID_WHQL = 5,
++ RT_CID_819x_CAMEO = 6,
++ RT_CID_819x_RUNTOP = 7,
++ RT_CID_819x_Senao = 8,
++ RT_CID_TOSHIBA = 9, // Merge by Jacken, 2008/01/31.
++ RT_CID_819x_Netcore = 10,
++ RT_CID_Nettronix = 11,
++ RT_CID_DLINK = 12,
++ RT_CID_PRONET = 13,
++ RT_CID_COREGA = 14,
++ RT_CID_CHINA_MOBILE = 15,
++ RT_CID_819x_ALPHA = 16,
++ RT_CID_819x_Sitecom = 17,
++ RT_CID_CCX = 18, // It's set under CCX logo test and isn't demanded for CCX functions, but for test behavior like retry limit and tx report. By Bruce, 2009-02-17.
++ RT_CID_819x_Lenovo = 19,
++ RT_CID_819x_QMI = 20,
++ RT_CID_819x_Edimax_Belkin = 21,
++ RT_CID_819x_Sercomm_Belkin = 22,
++ RT_CID_819x_CAMEO1 = 23,
++ RT_CID_819x_MSI = 24,
++ RT_CID_819x_Acer = 25,
++ RT_CID_819x_AzWave_ASUS = 26,
++ RT_CID_819x_AzWave = 27, // For AzWave in PCIe, The ID is AzWave use and not only Asus
++ RT_CID_819x_HP = 28,
++ RT_CID_819x_WNC_COREGA = 29,
++ RT_CID_819x_Arcadyan_Belkin = 30,
++ RT_CID_819x_SAMSUNG = 31,
++ RT_CID_819x_CLEVO = 32,
++ RT_CID_819x_DELL = 33,
++ RT_CID_819x_PRONETS = 34,
++ RT_CID_819x_Edimax_ASUS = 35,
++ RT_CID_819x_CAMEO_NETGEAR = 36,
++}RT_CUSTOMER_ID, *PRT_CUSTOMER_ID;
++
++struct eeprom_priv
++{
++ u8 bautoload_fail_flag;
++ //u8 bempty;
++ //u8 sys_config;
++ u8 mac_addr[6]; //PermanentAddress
++ //u8 config0;
++ u16 channel_plan;
++ //u8 country_string[3];
++ //u8 tx_power_b[15];
++ //u8 tx_power_g[15];
++ //u8 tx_power_a[201];
++
++ u8 EepromOrEfuse;
++
++ u8 efuse_eeprom_data[EEPROM_MAX_SIZE];
++
++#ifdef CONFIG_SDIO_HCI
++ u8 sdio_setting;
++ u32 ocr;
++ u8 cis0[eeprom_cis0_sz];
++ u8 cis1[eeprom_cis1_sz];
++#endif
++};
++
++
++extern void eeprom_write16(_adapter *padapter, u16 reg, u16 data);
++extern u16 eeprom_read16(_adapter *padapter, u16 reg);
++extern void read_eeprom_content(_adapter *padapter);
++extern void eeprom_read_sz(_adapter * padapter, u16 reg,u8* data, u32 sz);
++
++extern void read_eeprom_content_by_attrib(_adapter * padapter );
++
++#ifdef PLATFORM_LINUX
++#ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE
++extern int isAdaptorInfoFileValid(void);
++extern int storeAdaptorInfoFile(char *path, struct eeprom_priv * eeprom_priv);
++extern int retriveAdaptorInfoFile(char *path, struct eeprom_priv * eeprom_priv);
++#endif //CONFIG_ADAPTOR_INFO_CACHING_FILE
++#endif //PLATFORM_LINUX
++
++#endif //__RTL871X_EEPROM_H__
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtw_efuse.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtw_efuse.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtw_efuse.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtw_efuse.h 2015-07-28 01:20:58.321597318 +0200
+@@ -0,0 +1,123 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef __RTW_EFUSE_H__
++#define __RTW_EFUSE_H__
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++
++#define EFUSE_ERROE_HANDLE 1
++
++#define PG_STATE_HEADER 0x01
++#define PG_STATE_WORD_0 0x02
++#define PG_STATE_WORD_1 0x04
++#define PG_STATE_WORD_2 0x08
++#define PG_STATE_WORD_3 0x10
++#define PG_STATE_DATA 0x20
++
++#define PG_SWBYTE_H 0x01
++#define PG_SWBYTE_L 0x02
++
++#define PGPKT_DATA_SIZE 8
++
++#define EFUSE_WIFI 0
++#define EFUSE_BT 1
++
++enum _EFUSE_DEF_TYPE {
++ TYPE_EFUSE_MAX_SECTION = 0,
++ TYPE_EFUSE_REAL_CONTENT_LEN = 1,
++ TYPE_AVAILABLE_EFUSE_BYTES_BANK = 2,
++ TYPE_AVAILABLE_EFUSE_BYTES_TOTAL = 3,
++ TYPE_EFUSE_MAP_LEN = 4,
++ TYPE_EFUSE_PROTECT_BYTES_BANK = 5,
++};
++
++#define EFUSE_MAX_MAP_LEN 256
++#define EFUSE_MAX_HW_SIZE 512
++#define EFUSE_MAX_SECTION_BASE 16
++
++#define EXT_HEADER(header) ((header & 0x1F ) == 0x0F)
++#define ALL_WORDS_DISABLED(wde) ((wde & 0x0F) == 0x0F)
++#define GET_HDR_OFFSET_2_0(header) ( (header & 0xE0) >> 5)
++
++#define EFUSE_REPEAT_THRESHOLD_ 3
++
++//=============================================
++// The following is for BT Efuse definition
++//=============================================
++#define EFUSE_BT_MAX_MAP_LEN 1024
++#define EFUSE_MAX_BANK 4
++#define EFUSE_MAX_BT_BANK (EFUSE_MAX_BANK-1)
++//=============================================
++/*--------------------------Define Parameters-------------------------------*/
++#define EFUSE_MAX_WORD_UNIT 4
++
++/*------------------------------Define structure----------------------------*/
++typedef struct PG_PKT_STRUCT_A{
++ u8 offset;
++ u8 word_en;
++ u8 data[8];
++ u8 word_cnts;
++}PGPKT_STRUCT,*PPGPKT_STRUCT;
++/*------------------------------Define structure----------------------------*/
++
++
++/*------------------------Export global variable----------------------------*/
++extern u8 fakeEfuseBank;
++extern u32 fakeEfuseUsedBytes;
++extern u8 fakeEfuseContent[];
++extern u8 fakeEfuseInitMap[];
++extern u8 fakeEfuseModifiedMap[];
++
++extern u32 BTEfuseUsedBytes;
++extern u8 BTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE];
++extern u8 BTEfuseInitMap[];
++extern u8 BTEfuseModifiedMap[];
++
++extern u32 fakeBTEfuseUsedBytes;
++extern u8 fakeBTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE];
++extern u8 fakeBTEfuseInitMap[];
++extern u8 fakeBTEfuseModifiedMap[];
++/*------------------------Export global variable----------------------------*/
++
++u8 efuse_GetCurrentSize(PADAPTER padapter, u16 *size);
++u16 efuse_GetMaxSize(PADAPTER padapter);
++u8 rtw_efuse_access(PADAPTER padapter, u8 bRead, u16 start_addr, u16 cnts, u8 *data);
++u8 rtw_efuse_map_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data);
++u8 rtw_efuse_map_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data);
++
++u16 Efuse_GetCurrentSize(PADAPTER pAdapter, u8 efuseType, BOOLEAN bPseudoTest);
++u8 Efuse_CalculateWordCnts(u8 word_en);
++void ReadEFuseByte(PADAPTER Adapter, u16 _offset, u8 *pbuf, BOOLEAN bPseudoTest) ;
++void EFUSE_GetEfuseDefinition(PADAPTER pAdapter, u8 efuseType, u8 type, void *pOut, BOOLEAN bPseudoTest);
++u8 efuse_OneByteRead(PADAPTER pAdapter, u16 addr, u8 *data, BOOLEAN bPseudoTest);
++u8 efuse_OneByteWrite(PADAPTER pAdapter, u16 addr, u8 data, BOOLEAN bPseudoTest);
++
++void Efuse_PowerSwitch(PADAPTER pAdapter,u8 bWrite,u8 PwrState);
++int Efuse_PgPacketRead(PADAPTER pAdapter, u8 offset, u8 *data, BOOLEAN bPseudoTest);
++int Efuse_PgPacketWrite(PADAPTER pAdapter, u8 offset, u8 word_en, u8 *data, BOOLEAN bPseudoTest);
++void efuse_WordEnableDataRead(u8 word_en, u8 *sourdata, u8 *targetdata);
++u8 Efuse_WordEnableDataWrite(PADAPTER pAdapter, u16 efuse_addr, u8 word_en, u8 *data, BOOLEAN bPseudoTest);
++
++u8 EFUSE_Read1Byte(PADAPTER pAdapter, u16 Address);
++void EFUSE_ShadowMapUpdate(PADAPTER pAdapter, u8 efuseType, BOOLEAN bPseudoTest);
++void EFUSE_ShadowRead(PADAPTER pAdapter, u8 Type, u16 Offset, u32 *Value);
++
++#endif
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtw_event.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtw_event.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtw_event.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtw_event.h 2015-07-28 01:20:58.321597318 +0200
+@@ -0,0 +1,153 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef _RTW_EVENT_H_
++#define _RTW_EVENT_H_
++#include <drv_conf.h>
++#include <osdep_service.h>
++
++#ifndef CONFIG_RTL8711FW
++#ifdef PLATFORM_LINUX
++#include <wlan_bssdef.h>
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26))
++#include <asm/semaphore.h>
++#else
++#include <linux/semaphore.h>
++#endif
++#include <linux/sem.h>
++#endif
++#else
++#include <wlan_bssdef.h>
++#endif//CONFIG_RTL8711FW
++
++
++
++#ifdef CONFIG_H2CLBK
++#include <h2clbk.h>
++#endif
++
++/*
++Used to report a bss has been scanned
++
++*/
++struct survey_event {
++ WLAN_BSSID_EX bss;
++};
++
++/*
++Used to report that the requested site survey has been done.
++
++bss_cnt indicates the number of bss that has been reported.
++
++
++*/
++struct surveydone_event {
++ unsigned int bss_cnt;
++
++};
++
++/*
++Used to report the link result of joinning the given bss
++
++
++join_res:
++-1: authentication fail
++-2: association fail
++> 0: TID
++
++*/
++struct joinbss_event {
++ struct wlan_network network;
++};
++
++/*
++Used to report a given STA has joinned the created BSS.
++It is used in AP/Ad-HoC(M) mode.
++
++
++*/
++struct stassoc_event {
++ unsigned char macaddr[6];
++ unsigned char rsvd[2];
++ int cam_id;
++
++};
++
++struct stadel_event {
++ unsigned char macaddr[6];
++ unsigned char rsvd[2]; //for reason
++ int mac_id;
++};
++
++struct addba_event
++{
++ unsigned int tid;
++};
++
++
++#ifdef CONFIG_H2CLBK
++struct c2hlbk_event{
++ unsigned char mac[6];
++ unsigned short s0;
++ unsigned short s1;
++ unsigned int w0;
++ unsigned char b0;
++ unsigned short s2;
++ unsigned char b1;
++ unsigned int w1;
++};
++#endif//CONFIG_H2CLBK
++
++#define GEN_EVT_CODE(event) event ## _EVT_
++
++
++
++struct fwevent {
++ u32 parmsize;
++ void (*event_callback)(_adapter *dev, u8 *pbuf);
++};
++
++
++#define C2HEVENT_SZ 32
++
++struct event_node{
++ unsigned char *node;
++ unsigned char evt_code;
++ unsigned short evt_sz;
++ volatile int *caller_ff_tail;
++ int caller_ff_sz;
++};
++
++struct c2hevent_queue {
++ volatile int head;
++ volatile int tail;
++ struct event_node nodes[C2HEVENT_SZ];
++ unsigned char seq;
++};
++
++#define NETWORK_QUEUE_SZ 4
++
++struct network_queue {
++ volatile int head;
++ volatile int tail;
++ WLAN_BSSID_EX networks[NETWORK_QUEUE_SZ];
++};
++
++
++#endif // _WLANEVENT_H_
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtw_ht.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtw_ht.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtw_ht.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtw_ht.h 2015-07-28 01:20:58.321597318 +0200
+@@ -0,0 +1,49 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef _RTW_HT_H_
++#define _RTW_HT_H_
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include "wifi.h"
++
++struct ht_priv
++{
++ u32 ht_option;
++ u32 ampdu_enable;//for enable Tx A-MPDU
++ //u8 baddbareq_issued[16];
++ u32 tx_amsdu_enable;//for enable Tx A-MSDU
++ u32 tx_amdsu_maxlen; // 1: 8k, 0:4k ; default:8k, for tx
++ u32 rx_ampdu_maxlen; //for rx reordering ctrl win_sz, updated when join_callback.
++
++ u8 bwmode;//
++ u8 ch_offset;//PRIME_CHNL_OFFSET
++ u8 sgi;//short GI
++
++ //for processing Tx A-MPDU
++ u8 agg_enable_bitmap;
++ //u8 ADDBA_retry_count;
++ u8 candidate_tid_bitmap;
++
++ struct rtw_ieee80211_ht_cap ht_cap;
++
++};
++
++#endif //_RTL871X_HT_H_
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtw_ioctl.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtw_ioctl.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtw_ioctl.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtw_ioctl.h 2015-07-28 01:20:58.321597318 +0200
+@@ -0,0 +1,268 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef _RTW_IOCTL_H_
++#define _RTW_IOCTL_H_
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++
++#ifndef OID_802_11_CAPABILITY
++ #define OID_802_11_CAPABILITY 0x0d010122
++#endif
++
++#ifndef OID_802_11_PMKID
++ #define OID_802_11_PMKID 0x0d010123
++#endif
++
++
++// For DDK-defined OIDs
++#define OID_NDIS_SEG1 0x00010100
++#define OID_NDIS_SEG2 0x00010200
++#define OID_NDIS_SEG3 0x00020100
++#define OID_NDIS_SEG4 0x01010100
++#define OID_NDIS_SEG5 0x01020100
++#define OID_NDIS_SEG6 0x01020200
++#define OID_NDIS_SEG7 0xFD010100
++#define OID_NDIS_SEG8 0x0D010100
++#define OID_NDIS_SEG9 0x0D010200
++#define OID_NDIS_SEG10 0x0D020200
++
++#define SZ_OID_NDIS_SEG1 23
++#define SZ_OID_NDIS_SEG2 3
++#define SZ_OID_NDIS_SEG3 6
++#define SZ_OID_NDIS_SEG4 6
++#define SZ_OID_NDIS_SEG5 4
++#define SZ_OID_NDIS_SEG6 8
++#define SZ_OID_NDIS_SEG7 7
++#define SZ_OID_NDIS_SEG8 36
++#define SZ_OID_NDIS_SEG9 24
++#define SZ_OID_NDIS_SEG10 19
++
++// For Realtek-defined OIDs
++#define OID_MP_SEG1 0xFF871100
++#define OID_MP_SEG2 0xFF818000
++
++#define OID_MP_SEG3 0xFF818700
++#define OID_MP_SEG4 0xFF011100
++
++#define DEBUG_OID(dbg, str) \
++ if((!dbg)) \
++ { \
++ RT_TRACE(_module_rtl871x_ioctl_c_,_drv_info_,("%s(%d): %s", __FUNCTION__, __LINE__, str)); \
++ }
++
++
++enum oid_type
++{
++ QUERY_OID,
++ SET_OID
++};
++
++struct oid_funs_node {
++ unsigned int oid_start; //the starting number for OID
++ unsigned int oid_end; //the ending number for OID
++ struct oid_obj_priv *node_array;
++ unsigned int array_sz; //the size of node_array
++ int query_counter; //count the number of query hits for this segment
++ int set_counter; //count the number of set hits for this segment
++};
++
++struct oid_par_priv
++{
++ void *adapter_context;
++ NDIS_OID oid;
++ void *information_buf;
++ u32 information_buf_len;
++ u32 *bytes_rw;
++ u32 *bytes_needed;
++ enum oid_type type_of_oid;
++ u32 dbg;
++};
++
++struct oid_obj_priv {
++ unsigned char dbg; // 0: without OID debug message 1: with OID debug message
++ NDIS_STATUS (*oidfuns)(struct oid_par_priv *poid_par_priv);
++};
++
++#if (defined(CONFIG_MP_INCLUDED) && defined(_RTW_MP_IOCTL_C_)) || \
++ (defined(PLATFORM_WINDOWS) && defined(_RTW_IOCTL_RTL_C_))
++static NDIS_STATUS oid_null_function(struct oid_par_priv* poid_par_priv)
++{
++ _func_enter_;
++ _func_exit_;
++ return NDIS_STATUS_SUCCESS;
++}
++#endif
++
++#ifdef PLATFORM_WINDOWS
++
++int TranslateNdisPsToRtPs(IN NDIS_802_11_POWER_MODE ndisPsMode);
++
++//OID Handler for Segment 1
++NDIS_STATUS oid_gen_supported_list_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_gen_hardware_status_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_gen_media_supported_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_gen_media_in_use_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_gen_maximum_lookahead_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_gen_maximum_frame_size_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_gen_link_speed_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_gen_transmit_buffer_space_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_gen_receive_buffer_space_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_gen_transmit_block_size_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_gen_receive_block_size_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_gen_vendor_id_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_gen_vendor_description_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_gen_current_packet_filter_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_gen_current_lookahead_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_gen_driver_version_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_gen_maximum_total_size_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_gen_protocol_options_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_gen_mac_options_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_gen_media_connect_status_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_gen_maximum_send_packets_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_gen_vendor_driver_version_hdl(struct oid_par_priv* poid_par_priv);
++
++
++//OID Handler for Segment 2
++NDIS_STATUS oid_gen_physical_medium_hdl(struct oid_par_priv* poid_par_priv);
++
++//OID Handler for Segment 3
++NDIS_STATUS oid_gen_xmit_ok_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_gen_rcv_ok_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_gen_xmit_error_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_gen_rcv_error_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_gen_rcv_no_buffer_hdl(struct oid_par_priv* poid_par_priv);
++
++
++//OID Handler for Segment 4
++NDIS_STATUS oid_802_3_permanent_address_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_802_3_current_address_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_802_3_multicast_list_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_802_3_maximum_list_size_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_802_3_mac_options_hdl(struct oid_par_priv* poid_par_priv);
++
++
++
++//OID Handler for Segment 5
++NDIS_STATUS oid_802_3_rcv_error_alignment_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_802_3_xmit_one_collision_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_802_3_xmit_more_collisions_hdl(struct oid_par_priv* poid_par_priv);
++
++
++//OID Handler for Segment 6
++NDIS_STATUS oid_802_3_xmit_deferred_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_802_3_xmit_max_collisions_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_802_3_rcv_overrun_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_802_3_xmit_underrun_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_802_3_xmit_heartbeat_failure_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_802_3_xmit_times_crs_lost_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_802_3_xmit_late_collisions_hdl(struct oid_par_priv* poid_par_priv);
++
++
++
++//OID Handler for Segment 7
++NDIS_STATUS oid_pnp_capabilities_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_pnp_set_power_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_pnp_query_power_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_pnp_add_wake_up_pattern_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_pnp_remove_wake_up_pattern_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_pnp_wake_up_pattern_list_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_pnp_enable_wake_up_hdl(struct oid_par_priv* poid_par_priv);
++
++
++
++//OID Handler for Segment 8
++NDIS_STATUS oid_802_11_bssid_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_802_11_ssid_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_802_11_infrastructure_mode_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_802_11_add_wep_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_802_11_remove_wep_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_802_11_disassociate_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_802_11_authentication_mode_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_802_11_privacy_filter_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_802_11_bssid_list_scan_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_802_11_encryption_status_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_802_11_reload_defaults_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_802_11_add_key_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_802_11_remove_key_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_802_11_association_information_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_802_11_test_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_802_11_media_stream_mode_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_802_11_capability_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_802_11_pmkid_hdl(struct oid_par_priv* poid_par_priv);
++
++
++
++
++
++//OID Handler for Segment 9
++NDIS_STATUS oid_802_11_network_types_supported_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_802_11_network_type_in_use_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_802_11_tx_power_level_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_802_11_rssi_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_802_11_rssi_trigger_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_802_11_fragmentation_threshold_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_802_11_rts_threshold_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_802_11_number_of_antennas_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_802_11_rx_antenna_selected_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_802_11_tx_antenna_selected_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_802_11_supported_rates_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_802_11_desired_rates_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_802_11_configuration_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_802_11_power_mode_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_802_11_bssid_list_hdl(struct oid_par_priv* poid_par_priv);
++
++
++//OID Handler for Segment 10
++NDIS_STATUS oid_802_11_statistics_hdl(struct oid_par_priv* poid_par_priv);
++
++
++//OID Handler for Segment ED
++NDIS_STATUS oid_rt_mh_vender_id_hdl(struct oid_par_priv* poid_par_priv);
++
++void Set_802_3_MULTICAST_LIST(ADAPTER *pAdapter, UCHAR *MCListbuf, ULONG MCListlen, BOOLEAN bAcceptAllMulticast);
++
++#endif// end of PLATFORM_WINDOWS
++
++
++#if defined(PLATFORM_LINUX) && defined(CONFIG_WIRELESS_EXT)
++extern struct iw_handler_def rtw_handlers_def;
++#endif
++
++extern NDIS_STATUS drv_query_info(
++ IN _nic_hdl MiniportAdapterContext,
++ IN NDIS_OID Oid,
++ IN void * InformationBuffer,
++ IN u32 InformationBufferLength,
++ OUT u32* BytesWritten,
++ OUT u32* BytesNeeded
++ );
++
++extern NDIS_STATUS drv_set_info(
++ IN _nic_hdl MiniportAdapterContext,
++ IN NDIS_OID Oid,
++ IN void * InformationBuffer,
++ IN u32 InformationBufferLength,
++ OUT u32* BytesRead,
++ OUT u32* BytesNeeded
++ );
++
++#endif // #ifndef __INC_CEINFO_
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtw_ioctl_query.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtw_ioctl_query.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtw_ioctl_query.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtw_ioctl_query.h 2015-07-28 01:20:58.321597318 +0200
+@@ -0,0 +1,35 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef _RTW_IOCTL_QUERY_H_
++#define _RTW_IOCTL_QUERY_H_
++
++#include <drv_conf.h>
++#include <drv_types.h>
++
++
++#ifdef PLATFORM_WINDOWS
++
++u8 query_802_11_capability(_adapter* padapter,u8* pucBuf,u32 * pulOutLen);
++u8 query_802_11_association_information (_adapter * padapter, PNDIS_802_11_ASSOCIATION_INFORMATION pAssocInfo);
++
++#endif
++
++
++#endif
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtw_ioctl_rtl.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtw_ioctl_rtl.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtw_ioctl_rtl.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtw_ioctl_rtl.h 2015-07-28 01:20:58.321597318 +0200
+@@ -0,0 +1,83 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef _RTW_IOCTL_RTL_H_
++#define _RTW_IOCTL_RTL_H_
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++
++//************** oid_rtl_seg_01_01 **************
++NDIS_STATUS oid_rt_get_signal_quality_hdl(struct oid_par_priv* poid_par_priv);//84
++NDIS_STATUS oid_rt_get_small_packet_crc_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_get_middle_packet_crc_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_get_large_packet_crc_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_get_tx_retry_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_get_rx_retry_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_get_rx_total_packet_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_get_tx_beacon_ok_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_get_tx_beacon_err_hdl(struct oid_par_priv* poid_par_priv);
++
++NDIS_STATUS oid_rt_pro_set_fw_dig_state_hdl(struct oid_par_priv* poid_par_priv); //8a
++NDIS_STATUS oid_rt_pro_set_fw_ra_state_hdl(struct oid_par_priv* poid_par_priv); //8b
++
++NDIS_STATUS oid_rt_get_rx_icv_err_hdl(struct oid_par_priv* poid_par_priv);//93
++NDIS_STATUS oid_rt_set_encryption_algorithm_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_get_preamble_mode_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_get_ap_ip_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_get_channelplan_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_set_channelplan_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_set_preamble_mode_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_set_bcn_intvl_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_dedicate_probe_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_get_total_tx_bytes_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_get_total_rx_bytes_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_current_tx_power_level_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_get_enc_key_mismatch_count_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_get_enc_key_match_count_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_get_channel_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_get_hardware_radio_off_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_get_key_mismatch_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_supported_wireless_mode_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_get_channel_list_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_get_scan_in_progress_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_forced_data_rate_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_wireless_mode_for_scan_list_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_get_bss_wireless_mode_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_scan_with_magic_packet_hdl(struct oid_par_priv* poid_par_priv);
++
++//************** oid_rtl_seg_01_03 section start **************
++NDIS_STATUS oid_rt_ap_get_associated_station_list_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_ap_switch_into_ap_mode_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_ap_supported_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_ap_set_passphrase_hdl(struct oid_par_priv* poid_par_priv);
++
++// oid_rtl_seg_01_11
++NDIS_STATUS oid_rt_pro_rf_write_registry_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_pro_rf_read_registry_hdl(struct oid_par_priv* poid_par_priv);
++
++//************** oid_rtl_seg_03_00 section start **************
++NDIS_STATUS oid_rt_get_connect_state_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_set_default_key_id_hdl(struct oid_par_priv* poid_par_priv);
++
++
++
++
++#endif
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtw_ioctl_set.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtw_ioctl_set.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtw_ioctl_set.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtw_ioctl_set.h 2015-07-28 01:20:58.321597318 +0200
+@@ -0,0 +1,78 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef __RTW_IOCTL_SET_H_
++#define __RTW_IOCTL_SET_H_
++
++#include <drv_conf.h>
++#include <drv_types.h>
++
++
++typedef u8 NDIS_802_11_PMKID_VALUE[16];
++
++typedef struct _BSSIDInfo {
++ NDIS_802_11_MAC_ADDRESS BSSID;
++ NDIS_802_11_PMKID_VALUE PMKID;
++} BSSIDInfo, *PBSSIDInfo;
++
++
++#ifdef PLATFORM_OS_XP
++typedef struct _NDIS_802_11_PMKID {
++ u32 Length;
++ u32 BSSIDInfoCount;
++ BSSIDInfo BSSIDInfo[1];
++} NDIS_802_11_PMKID, *PNDIS_802_11_PMKID;
++#endif
++
++
++#ifdef PLATFORM_WINDOWS
++u8 rtw_set_802_11_reload_defaults(_adapter * padapter, NDIS_802_11_RELOAD_DEFAULTS reloadDefaults);
++u8 rtw_set_802_11_test(_adapter * padapter, NDIS_802_11_TEST * test);
++u8 rtw_set_802_11_pmkid(_adapter *pdapter, NDIS_802_11_PMKID *pmkid);
++
++u8 rtw_pnp_set_power_sleep(_adapter* padapter);
++u8 rtw_pnp_set_power_wakeup(_adapter* padapter);
++
++void rtw_pnp_resume_wk(void *context);
++void rtw_pnp_sleep_wk(void * context);
++
++#endif
++
++u8 rtw_set_802_11_add_key(_adapter * padapter, NDIS_802_11_KEY * key);
++u8 rtw_set_802_11_authentication_mode(_adapter *pdapter, NDIS_802_11_AUTHENTICATION_MODE authmode);
++u8 rtw_set_802_11_bssid(_adapter* padapter, u8 *bssid);
++u8 rtw_set_802_11_add_wep(_adapter * padapter, NDIS_802_11_WEP * wep);
++u8 rtw_set_802_11_disassociate(_adapter * padapter);
++u8 rtw_set_802_11_bssid_list_scan(_adapter* padapter, NDIS_802_11_SSID *pssid, int ssid_max_num);
++u8 rtw_set_802_11_infrastructure_mode(_adapter * padapter, NDIS_802_11_NETWORK_INFRASTRUCTURE networktype);
++u8 rtw_set_802_11_remove_wep(_adapter * padapter, u32 keyindex);
++u8 rtw_set_802_11_ssid(_adapter * padapter, NDIS_802_11_SSID * ssid);
++u8 rtw_set_802_11_connect(_adapter* padapter, u8 *bssid, NDIS_802_11_SSID *ssid);
++u8 rtw_set_802_11_remove_key(_adapter * padapter, NDIS_802_11_REMOVE_KEY * key);
++
++u8 rtw_validate_bssid(u8 *bssid);
++u8 rtw_validate_ssid(NDIS_802_11_SSID *ssid);
++
++u16 rtw_get_cur_max_rate(_adapter *adapter);
++int rtw_set_scan_mode(_adapter *adapter, RT_SCAN_TYPE scan_mode);
++int rtw_set_channel_plan(_adapter *adapter, u8 channel_plan);
++int rtw_set_country(_adapter *adapter, const char *country_code);
++int rtw_set_band(_adapter *adapter, enum _BAND band);
++
++#endif
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtw_io.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtw_io.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtw_io.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtw_io.h 2015-07-28 01:20:58.321597318 +0200
+@@ -0,0 +1,504 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++
++#ifndef _RTW_IO_H_
++#define _RTW_IO_H_
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <osdep_intf.h>
++
++#ifdef PLATFORM_LINUX
++#include <asm/byteorder.h>
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26))
++#include <asm/semaphore.h>
++#else
++#include <linux/semaphore.h>
++#endif
++#include <linux/list.h>
++//#include <linux/smp_lock.h>
++#include <linux/spinlock.h>
++#include <asm/atomic.h>
++
++#ifdef CONFIG_USB_HCI
++#include <linux/usb.h>
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21))
++#include <linux/usb_ch9.h>
++#else
++#include <linux/usb/ch9.h>
++#endif
++#endif //CONFIG_USB_HCI
++
++#endif //PLATFORM_LINUX
++
++
++#define NUM_IOREQ 8
++
++#ifdef PLATFORM_WINDOWS
++#define MAX_PROT_SZ 64
++#endif
++#ifdef PLATFORM_LINUX
++#define MAX_PROT_SZ (64-16)
++#endif
++
++#define _IOREADY 0
++#define _IO_WAIT_COMPLETE 1
++#define _IO_WAIT_RSP 2
++
++// IO COMMAND TYPE
++#define _IOSZ_MASK_ (0x7F)
++#define _IO_WRITE_ BIT(7)
++#define _IO_FIXED_ BIT(8)
++#define _IO_BURST_ BIT(9)
++#define _IO_BYTE_ BIT(10)
++#define _IO_HW_ BIT(11)
++#define _IO_WORD_ BIT(12)
++#define _IO_SYNC_ BIT(13)
++#define _IO_CMDMASK_ (0x1F80)
++
++
++/*
++ For prompt mode accessing, caller shall free io_req
++ Otherwise, io_handler will free io_req
++*/
++
++
++
++// IO STATUS TYPE
++#define _IO_ERR_ BIT(2)
++#define _IO_SUCCESS_ BIT(1)
++#define _IO_DONE_ BIT(0)
++
++
++#define IO_RD32 (_IO_SYNC_ | _IO_WORD_)
++#define IO_RD16 (_IO_SYNC_ | _IO_HW_)
++#define IO_RD8 (_IO_SYNC_ | _IO_BYTE_)
++
++#define IO_RD32_ASYNC (_IO_WORD_)
++#define IO_RD16_ASYNC (_IO_HW_)
++#define IO_RD8_ASYNC (_IO_BYTE_)
++
++#define IO_WR32 (_IO_WRITE_ | _IO_SYNC_ | _IO_WORD_)
++#define IO_WR16 (_IO_WRITE_ | _IO_SYNC_ | _IO_HW_)
++#define IO_WR8 (_IO_WRITE_ | _IO_SYNC_ | _IO_BYTE_)
++
++#define IO_WR32_ASYNC (_IO_WRITE_ | _IO_WORD_)
++#define IO_WR16_ASYNC (_IO_WRITE_ | _IO_HW_)
++#define IO_WR8_ASYNC (_IO_WRITE_ | _IO_BYTE_)
++
++/*
++
++ Only Sync. burst accessing is provided.
++
++*/
++
++#define IO_WR_BURST(x) (_IO_WRITE_ | _IO_SYNC_ | _IO_BURST_ | ( (x) & _IOSZ_MASK_))
++#define IO_RD_BURST(x) (_IO_SYNC_ | _IO_BURST_ | ( (x) & _IOSZ_MASK_))
++
++
++
++//below is for the intf_option bit defition...
++
++#define _INTF_ASYNC_ BIT(0) //support async io
++
++struct intf_priv;
++struct intf_hdl;
++struct io_queue;
++
++struct _io_ops
++{
++ u8 (*_read8)(struct intf_hdl *pintfhdl, u32 addr);
++ u16 (*_read16)(struct intf_hdl *pintfhdl, u32 addr);
++ u32 (*_read32)(struct intf_hdl *pintfhdl, u32 addr);
++
++ int (*_write8)(struct intf_hdl *pintfhdl, u32 addr, u8 val);
++ int (*_write16)(struct intf_hdl *pintfhdl, u32 addr, u16 val);
++ int (*_write32)(struct intf_hdl *pintfhdl, u32 addr, u32 val);
++ int (*_writeN)(struct intf_hdl *pintfhdl, u32 addr, u32 length, u8 *pdata);
++
++ int (*_write8_async)(struct intf_hdl *pintfhdl, u32 addr, u8 val);
++ int (*_write16_async)(struct intf_hdl *pintfhdl, u32 addr, u16 val);
++ int (*_write32_async)(struct intf_hdl *pintfhdl, u32 addr, u32 val);
++
++ void (*_read_mem)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
++ void (*_write_mem)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
++
++ void (*_sync_irp_protocol_rw)(struct io_queue *pio_q);
++
++ u32 (*_read_interrupt)(struct intf_hdl *pintfhdl, u32 addr);
++
++ u32 (*_read_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
++ u32 (*_write_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
++
++ u32 (*_write_scsi)(struct intf_hdl *pintfhdl,u32 cnt, u8 *pmem);
++
++ void (*_read_port_cancel)(struct intf_hdl *pintfhdl);
++ void (*_write_port_cancel)(struct intf_hdl *pintfhdl);
++
++};
++
++struct io_req {
++ _list list;
++ u32 addr;
++ volatile u32 val;
++ u32 command;
++ u32 status;
++ u8 *pbuf;
++ _sema sema;
++
++#ifdef PLATFORM_OS_CE
++#ifdef CONFIG_USB_HCI
++ // URB handler for rtw_write_mem
++ USB_TRANSFER usb_transfer_write_mem;
++#endif
++#endif
++
++ void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt);
++ u8 *cnxt;
++
++#ifdef PLATFORM_OS_XP
++ PMDL pmdl;
++ PIRP pirp;
++
++#ifdef CONFIG_SDIO_HCI
++ PSDBUS_REQUEST_PACKET sdrp;
++#endif
++
++#endif
++
++
++};
++
++struct intf_hdl {
++
++/*
++ u32 intf_option;
++ u32 bus_status;
++ u32 do_flush;
++ u8 *adapter;
++ u8 *intf_dev;
++ struct intf_priv *pintfpriv;
++ u8 cnt;
++ void (*intf_hdl_init)(u8 *priv);
++ void (*intf_hdl_unload)(u8 *priv);
++ void (*intf_hdl_open)(u8 *priv);
++ void (*intf_hdl_close)(u8 *priv);
++ struct _io_ops io_ops;
++ //u8 intf_status;//moved to struct intf_priv
++ u16 len;
++ u16 done_len;
++*/
++ _adapter *padapter;
++ struct dvobj_priv *pintf_dev;// pointer to &(padapter->dvobjpriv);
++
++ struct _io_ops io_ops;
++
++};
++
++struct reg_protocol_rd {
++
++#ifdef CONFIG_LITTLE_ENDIAN
++
++ //DW1
++ u32 NumOfTrans:4;
++ u32 Reserved1:4;
++ u32 Reserved2:24;
++ //DW2
++ u32 ByteCount:7;
++ u32 WriteEnable:1; //0:read, 1:write
++ u32 FixOrContinuous:1; //0:continuous, 1: Fix
++ u32 BurstMode:1;
++ u32 Byte1Access:1;
++ u32 Byte2Access:1;
++ u32 Byte4Access:1;
++ u32 Reserved3:3;
++ u32 Reserved4:16;
++ //DW3
++ u32 BusAddress;
++ //DW4
++ //u32 Value;
++#else
++
++
++//DW1
++ u32 Reserved1 :4;
++ u32 NumOfTrans :4;
++
++ u32 Reserved2 :24;
++
++ //DW2
++ u32 WriteEnable : 1;
++ u32 ByteCount :7;
++
++
++ u32 Reserved3 : 3;
++ u32 Byte4Access : 1;
++
++ u32 Byte2Access : 1;
++ u32 Byte1Access : 1;
++ u32 BurstMode :1 ;
++ u32 FixOrContinuous : 1;
++
++ u32 Reserved4 : 16;
++
++ //DW3
++ u32 BusAddress;
++
++ //DW4
++ //u32 Value;
++
++#endif
++
++};
++
++
++struct reg_protocol_wt {
++
++
++#ifdef CONFIG_LITTLE_ENDIAN
++
++ //DW1
++ u32 NumOfTrans:4;
++ u32 Reserved1:4;
++ u32 Reserved2:24;
++ //DW2
++ u32 ByteCount:7;
++ u32 WriteEnable:1; //0:read, 1:write
++ u32 FixOrContinuous:1; //0:continuous, 1: Fix
++ u32 BurstMode:1;
++ u32 Byte1Access:1;
++ u32 Byte2Access:1;
++ u32 Byte4Access:1;
++ u32 Reserved3:3;
++ u32 Reserved4:16;
++ //DW3
++ u32 BusAddress;
++ //DW4
++ u32 Value;
++
++#else
++ //DW1
++ u32 Reserved1 :4;
++ u32 NumOfTrans :4;
++
++ u32 Reserved2 :24;
++
++ //DW2
++ u32 WriteEnable : 1;
++ u32 ByteCount :7;
++
++ u32 Reserved3 : 3;
++ u32 Byte4Access : 1;
++
++ u32 Byte2Access : 1;
++ u32 Byte1Access : 1;
++ u32 BurstMode :1 ;
++ u32 FixOrContinuous : 1;
++
++ u32 Reserved4 : 16;
++
++ //DW3
++ u32 BusAddress;
++
++ //DW4
++ u32 Value;
++
++#endif
++
++};
++
++
++
++/*
++Below is the data structure used by _io_handler
++
++*/
++
++struct io_queue {
++ _lock lock;
++ _list free_ioreqs;
++ _list pending; //The io_req list that will be served in the single protocol read/write.
++ _list processing;
++ u8 *free_ioreqs_buf; // 4-byte aligned
++ u8 *pallocated_free_ioreqs_buf;
++ struct intf_hdl intf;
++};
++
++struct io_priv{
++
++ _adapter *padapter;
++
++ struct intf_hdl intf;
++
++};
++
++extern uint ioreq_flush(_adapter *adapter, struct io_queue *ioqueue);
++extern void sync_ioreq_enqueue(struct io_req *preq,struct io_queue *ioqueue);
++extern uint sync_ioreq_flush(_adapter *adapter, struct io_queue *ioqueue);
++
++
++extern uint free_ioreq(struct io_req *preq, struct io_queue *pio_queue);
++extern struct io_req *alloc_ioreq(struct io_queue *pio_q);
++
++extern uint register_intf_hdl(u8 *dev, struct intf_hdl *pintfhdl);
++extern void unregister_intf_hdl(struct intf_hdl *pintfhdl);
++
++extern void _rtw_attrib_read(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
++extern void _rtw_attrib_write(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
++
++extern u8 _rtw_read8(_adapter *adapter, u32 addr);
++extern u16 _rtw_read16(_adapter *adapter, u32 addr);
++extern u32 _rtw_read32(_adapter *adapter, u32 addr);
++extern void _rtw_read_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
++extern void _rtw_read_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
++extern void _rtw_read_port_cancel(_adapter *adapter);
++
++
++extern int _rtw_write8(_adapter *adapter, u32 addr, u8 val);
++extern int _rtw_write16(_adapter *adapter, u32 addr, u16 val);
++extern int _rtw_write32(_adapter *adapter, u32 addr, u32 val);
++extern int _rtw_writeN(_adapter *adapter, u32 addr, u32 length, u8 *pdata);
++
++extern int _rtw_write8_async(_adapter *adapter, u32 addr, u8 val);
++extern int _rtw_write16_async(_adapter *adapter, u32 addr, u16 val);
++extern int _rtw_write32_async(_adapter *adapter, u32 addr, u32 val);
++
++extern void _rtw_write_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
++extern u32 _rtw_write_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
++u32 _rtw_write_port_and_wait(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem, int timeout_ms);
++extern void _rtw_write_port_cancel(_adapter *adapter);
++
++#ifdef DBG_IO
++bool match_read_sniff_ranges(u16 addr, u16 len);
++bool match_write_sniff_ranges(u16 addr, u16 len);
++
++extern u8 dbg_rtw_read8(_adapter *adapter, u32 addr, const char *caller, const int line);
++extern u16 dbg_rtw_read16(_adapter *adapter, u32 addr, const char *caller, const int line);
++extern u32 dbg_rtw_read32(_adapter *adapter, u32 addr, const char *caller, const int line);
++
++extern int dbg_rtw_write8(_adapter *adapter, u32 addr, u8 val, const char *caller, const int line);
++extern int dbg_rtw_write16(_adapter *adapter, u32 addr, u16 val, const char *caller, const int line);
++extern int dbg_rtw_write32(_adapter *adapter, u32 addr, u32 val, const char *caller, const int line);
++extern int dbg_rtw_writeN(_adapter *adapter, u32 addr ,u32 length , u8 *data, const char *caller, const int line);
++
++#define rtw_read8(adapter, addr) dbg_rtw_read8((adapter), (addr), __FUNCTION__, __LINE__)
++#define rtw_read16(adapter, addr) dbg_rtw_read16((adapter), (addr), __FUNCTION__, __LINE__)
++#define rtw_read32(adapter, addr) dbg_rtw_read32((adapter), (addr), __FUNCTION__, __LINE__)
++#define rtw_read_mem(adapter, addr, cnt, mem) _rtw_read_mem((adapter), (addr), (cnt), (mem))
++#define rtw_read_port(adapter, addr, cnt, mem) _rtw_read_port((adapter), (addr), (cnt), (mem))
++#define rtw_read_port_cancel(adapter) _rtw_read_port_cancel((adapter))
++
++#define rtw_write8(adapter, addr, val) dbg_rtw_write8((adapter), (addr), (val), __FUNCTION__, __LINE__)
++#define rtw_write16(adapter, addr, val) dbg_rtw_write16((adapter), (addr), (val), __FUNCTION__, __LINE__)
++#define rtw_write32(adapter, addr, val) dbg_rtw_write32((adapter), (addr), (val), __FUNCTION__, __LINE__)
++#define rtw_writeN(adapter, addr, length, data) dbg_rtw_writeN((adapter), (addr), (length), (data), __FUNCTION__, __LINE__)
++
++#define rtw_write8_async(adapter, addr, val) _rtw_write8_async((adapter), (addr), (val))
++#define rtw_write16_async(adapter, addr, val) _rtw_write16_async((adapter), (addr), (val))
++#define rtw_write32_async(adapter, addr, val) _rtw_write32_async((adapter), (addr), (val))
++
++#define rtw_write_mem(adapter, addr, cnt, mem) _rtw_write_mem((adapter), addr, cnt, mem)
++#define rtw_write_port(adapter, addr, cnt, mem) _rtw_write_port(adapter, addr, cnt, mem)
++#define rtw_write_port_and_wait(adapter, addr, cnt, mem, timeout_ms) _rtw_write_port_and_wait((adapter), (addr), (cnt), (mem), (timeout_ms))
++#define rtw_write_port_cancel(adapter) _rtw_write_port_cancel(adapter)
++#else //DBG_IO
++#define rtw_read8(adapter, addr) _rtw_read8((adapter), (addr))
++#define rtw_read16(adapter, addr) _rtw_read16((adapter), (addr))
++#define rtw_read32(adapter, addr) _rtw_read32((adapter), (addr))
++#define rtw_read_mem(adapter, addr, cnt, mem) _rtw_read_mem((adapter), (addr), (cnt), (mem))
++#define rtw_read_port(adapter, addr, cnt, mem) _rtw_read_port((adapter), (addr), (cnt), (mem))
++#define rtw_read_port_cancel(adapter) _rtw_read_port_cancel((adapter))
++
++#define rtw_write8(adapter, addr, val) _rtw_write8((adapter), (addr), (val))
++#define rtw_write16(adapter, addr, val) _rtw_write16((adapter), (addr), (val))
++#define rtw_write32(adapter, addr, val) _rtw_write32((adapter), (addr), (val))
++#define rtw_writeN(adapter, addr, length, data) _rtw_writeN((adapter), (addr), (length), (data))
++
++#define rtw_write8_async(adapter, addr, val) _rtw_write8_async((adapter), (addr), (val))
++#define rtw_write16_async(adapter, addr, val) _rtw_write16_async((adapter), (addr), (val))
++#define rtw_write32_async(adapter, addr, val) _rtw_write32_async((adapter), (addr), (val))
++
++#define rtw_write_mem(adapter, addr, cnt, mem) _rtw_write_mem((adapter), (addr), (cnt), (mem))
++#define rtw_write_port(adapter, addr, cnt, mem) _rtw_write_port((adapter), (addr), (cnt), (mem))
++#define rtw_write_port_and_wait(adapter, addr, cnt, mem, timeout_ms) _rtw_write_port_and_wait((adapter), (addr), (cnt), (mem), (timeout_ms))
++#define rtw_write_port_cancel(adapter) _rtw_write_port_cancel((adapter))
++#endif //DBG_IO
++
++extern void rtw_write_scsi(_adapter *adapter, u32 cnt, u8 *pmem);
++
++//ioreq
++extern void ioreq_read8(_adapter *adapter, u32 addr, u8 *pval);
++extern void ioreq_read16(_adapter *adapter, u32 addr, u16 *pval);
++extern void ioreq_read32(_adapter *adapter, u32 addr, u32 *pval);
++extern void ioreq_write8(_adapter *adapter, u32 addr, u8 val);
++extern void ioreq_write16(_adapter *adapter, u32 addr, u16 val);
++extern void ioreq_write32(_adapter *adapter, u32 addr, u32 val);
++
++
++extern uint async_read8(_adapter *adapter, u32 addr, u8 *pbuff,
++ void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt);
++extern uint async_read16(_adapter *adapter, u32 addr, u8 *pbuff,
++ void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt);
++extern uint async_read32(_adapter *adapter, u32 addr, u8 *pbuff,
++ void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt);
++
++extern void async_read_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
++extern void async_read_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
++
++extern void async_write8(_adapter *adapter, u32 addr, u8 val,
++ void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt);
++extern void async_write16(_adapter *adapter, u32 addr, u16 val,
++ void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt);
++extern void async_write32(_adapter *adapter, u32 addr, u32 val,
++ void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt);
++
++extern void async_write_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
++extern void async_write_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
++
++
++int rtw_init_io_priv(_adapter *padapter, void (*set_intf_ops)(struct _io_ops *pops));
++
++
++extern uint alloc_io_queue(_adapter *adapter);
++extern void free_io_queue(_adapter *adapter);
++extern void async_bus_io(struct io_queue *pio_q);
++extern void bus_sync_io(struct io_queue *pio_q);
++extern u32 _ioreq2rwmem(struct io_queue *pio_q);
++extern void dev_power_down(_adapter * Adapter, u8 bpwrup);
++
++/*
++#define RTL_R8(reg) rtw_read8(padapter, reg)
++#define RTL_R16(reg) rtw_read16(padapter, reg)
++#define RTL_R32(reg) rtw_read32(padapter, reg)
++#define RTL_W8(reg, val8) rtw_write8(padapter, reg, val8)
++#define RTL_W16(reg, val16) rtw_write16(padapter, reg, val16)
++#define RTL_W32(reg, val32) rtw_write32(padapter, reg, val32)
++*/
++
++/*
++#define RTL_W8_ASYNC(reg, val8) rtw_write32_async(padapter, reg, val8)
++#define RTL_W16_ASYNC(reg, val16) rtw_write32_async(padapter, reg, val16)
++#define RTL_W32_ASYNC(reg, val32) rtw_write32_async(padapter, reg, val32)
++
++#define RTL_WRITE_BB(reg, val32) phy_SetUsbBBReg(padapter, reg, val32)
++#define RTL_READ_BB(reg) phy_QueryUsbBBReg(padapter, reg)
++*/
++
++#endif //_RTL8711_IO_H_
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtw_iol.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtw_iol.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtw_iol.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtw_iol.h 2015-07-28 01:20:58.321597318 +0200
+@@ -0,0 +1,89 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef __RTW_IOL_H_
++#define __RTW_IOL_H_
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++
++typedef struct _io_offload_cmd {
++ u8 rsvd0;
++ u8 cmd;
++ u16 address;
++ u32 value;
++} IO_OFFLOAD_CMD, IOL_CMD;
++
++#define IOL_CMD_LLT 0x00
++//#define IOL_CMD_R_EFUSE 0x01
++#define IOL_CMD_WB_REG 0x02
++#define IOL_CMD_WW_REG 0x03
++#define IOL_CMD_WD_REG 0x04
++//#define IOL_CMD_W_RF 0x05
++#define IOL_CMD_DELAY_US 0x80
++#define IOL_CMD_DELAY_MS 0x81
++//#define IOL_CMD_DELAY_S 0x82
++#define IOL_CMD_END 0x83
++
++/*****************************************************
++CMD Address Value
++(B1) (B2/B3:H/L addr) (B4:B7 : MSB:LSB)
++******************************************************
++IOL_CMD_LLT - B7: PGBNDY
++//IOL_CMD_R_EFUSE - -
++IOL_CMD_WB_REG 0x0~0xFFFF B7
++IOL_CMD_WW_REG 0x0~0xFFFF B6~B7
++IOL_CMD_WD_REG 0x0~0xFFFF B4~B7
++//IOL_CMD_W_RF RF Reg B5~B7
++IOL_CMD_DELAY_US - B6~B7
++IOL_CMD_DELAY_MS - B6~B7
++//IOL_CMD_DELAY_S - B6~B7
++IOL_CMD_END - -
++******************************************************/
++
++struct xmit_frame *rtw_IOL_accquire_xmit_frame(ADAPTER *adapter);
++int rtw_IOL_append_cmds(struct xmit_frame *xmit_frame, u8 *IOL_cmds, u32 cmd_len);
++int rtw_IOL_append_LLT_cmd(struct xmit_frame *xmit_frame, u8 page_boundary);
++int _rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value);
++int _rtw_IOL_append_WW_cmd(struct xmit_frame *xmit_frame, u16 addr, u16 value);
++int _rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value);
++int rtw_IOL_append_DELAY_US_cmd(struct xmit_frame *xmit_frame, u16 us);
++int rtw_IOL_append_DELAY_MS_cmd(struct xmit_frame *xmit_frame, u16 ms);
++int rtw_IOL_append_END_cmd(struct xmit_frame *xmit_frame);
++int rtw_IOL_exec_cmds_sync(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms);
++int rtw_IOL_exec_cmd_array_sync(PADAPTER adapter, u8 *IOL_cmds, u32 cmd_num, u32 max_wating_ms);
++int rtw_IOL_exec_empty_cmds_sync(ADAPTER *adapter, u32 max_wating_ms);
++
++#ifdef DBG_IO
++int dbg_rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value, const char *caller, const int line);
++int dbg_rtw_IOL_append_WW_cmd(struct xmit_frame *xmit_frame, u16 addr, u16 value, const char *caller, const int line);
++int dbg_rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value, const char *caller, const int line);
++#define rtw_IOL_append_WB_cmd(xmit_frame, addr, value) dbg_rtw_IOL_append_WB_cmd((xmit_frame), (addr), (value), __FUNCTION__, __LINE__)
++#define rtw_IOL_append_WW_cmd(xmit_frame, addr, value) dbg_rtw_IOL_append_WW_cmd((xmit_frame), (addr), (value), __FUNCTION__, __LINE__)
++#define rtw_IOL_append_WD_cmd(xmit_frame, addr, value) dbg_rtw_IOL_append_WD_cmd((xmit_frame), (addr), (value), __FUNCTION__, __LINE__)
++#else
++#define rtw_IOL_append_WB_cmd(xmit_frame, addr, value) _rtw_IOL_append_WB_cmd((xmit_frame), (addr), (value))
++#define rtw_IOL_append_WW_cmd(xmit_frame, addr, value) _rtw_IOL_append_WW_cmd((xmit_frame), (addr), (value))
++#define rtw_IOL_append_WD_cmd(xmit_frame, addr, value) _rtw_IOL_append_WD_cmd((xmit_frame), (addr), (value))
++#endif
++
++bool rtw_IOL_applied(ADAPTER *adapter);
++
++#endif //__RTW_IOL_H_
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtw_led.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtw_led.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtw_led.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtw_led.h 2015-07-28 01:20:58.321597318 +0200
+@@ -0,0 +1,216 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef __RTW_LED_H_
++#define __RTW_LED_H_
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++
++#define MSECS(t) (HZ * ((t) / 1000) + (HZ * ((t) % 1000)) / 1000)
++
++typedef enum _LED_CTL_MODE{
++ LED_CTL_POWER_ON = 1,
++ LED_CTL_LINK = 2,
++ LED_CTL_NO_LINK = 3,
++ LED_CTL_TX = 4,
++ LED_CTL_RX = 5,
++ LED_CTL_SITE_SURVEY = 6,
++ LED_CTL_POWER_OFF = 7,
++ LED_CTL_START_TO_LINK = 8,
++ LED_CTL_START_WPS = 9,
++ LED_CTL_STOP_WPS = 10,
++ LED_CTL_START_WPS_BOTTON = 11, //added for runtop
++ LED_CTL_STOP_WPS_FAIL = 12, //added for ALPHA
++ LED_CTL_STOP_WPS_FAIL_OVERLAP = 13, //added for BELKIN
++}LED_CTL_MODE;
++
++
++#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI)
++//================================================================================
++// LED object.
++//================================================================================
++
++typedef enum _LED_STATE_871x{
++ LED_UNKNOWN = 0,
++ RTW_LED_ON = 1,
++ RTW_LED_OFF = 2,
++ LED_BLINK_NORMAL = 3,
++ LED_BLINK_SLOWLY = 4,
++ LED_POWER_ON_BLINK = 5,
++ LED_SCAN_BLINK = 6, // LED is blinking during scanning period, the # of times to blink is depend on time for scanning.
++ LED_NO_LINK_BLINK = 7, // LED is blinking during no link state.
++ LED_BLINK_StartToBlink = 8,// Customzied for Sercomm Printer Server case
++ LED_BLINK_WPS = 9, // LED is blinkg during WPS communication
++ LED_TXRX_BLINK = 10,
++ LED_BLINK_WPS_STOP = 11, //for ALPHA
++ LED_BLINK_WPS_STOP_OVERLAP = 12, //for BELKIN
++}LED_STATE_871x;
++
++#define IS_LED_WPS_BLINKING(_LED_871x) (((PLED_871x)_LED_871x)->CurrLedState==LED_BLINK_WPS \
++ || ((PLED_871x)_LED_871x)->CurrLedState==LED_BLINK_WPS_STOP \
++ || ((PLED_871x)_LED_871x)->bLedWPSBlinkInProgress)
++
++#define IS_LED_BLINKING(_LED_871x) (((PLED_871x)_LED_871x)->bLedWPSBlinkInProgress \
++ ||((PLED_871x)_LED_871x)->bLedScanBlinkInProgress)
++
++typedef enum _LED_PIN_871x{
++ LED_PIN_GPIO0,
++ LED_PIN_LED0,
++ LED_PIN_LED1
++}LED_PIN_871x;
++
++typedef struct _LED_871x{
++ _adapter *padapter;
++ LED_PIN_871x LedPin; // Identify how to implement this SW led.
++ LED_STATE_871x CurrLedState; // Current LED state.
++ u8 bLedOn; // true if LED is ON, false if LED is OFF.
++
++ u8 bSWLedCtrl;
++
++ u8 bLedBlinkInProgress; // true if it is blinking, false o.w..
++ // ALPHA, added by chiyoko, 20090106
++ u8 bLedNoLinkBlinkInProgress;
++ u8 bLedLinkBlinkInProgress;
++ u8 bLedStartToLinkBlinkInProgress;
++ u8 bLedScanBlinkInProgress;
++ u8 bLedWPSBlinkInProgress;
++
++ u32 BlinkTimes; // Number of times to toggle led state for blinking.
++ LED_STATE_871x BlinkingLedState; // Next state for blinking, either RTW_LED_ON or RTW_LED_OFF are.
++
++ _timer BlinkTimer; // Timer object for led blinking.
++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)|| defined PLATFORM_FREEBSD
++ _workitem BlinkWorkItem; // Workitem used by BlinkTimer to manipulate H/W to blink LED.
++#endif
++} LED_871x, *PLED_871x;
++
++
++//================================================================================
++// LED customization.
++//================================================================================
++
++typedef enum _LED_STRATEGY_871x{
++ SW_LED_MODE0, // SW control 1 LED via GPIO0. It is default option.
++ SW_LED_MODE1, // 2 LEDs, through LED0 and LED1. For ALPHA.
++ SW_LED_MODE2, // SW control 1 LED via GPIO0, customized for AzWave 8187 minicard.
++ SW_LED_MODE3, // SW control 1 LED via GPIO0, customized for Sercomm Printer Server case.
++ SW_LED_MODE4, //for Edimax / Belkin
++ SW_LED_MODE5, //for Sercomm / Belkin
++ SW_LED_MODE6, //for 88CU minicard, porting from ce SW_LED_MODE7
++ HW_LED, // HW control 2 LEDs, LED0 and LED1 (there are 4 different control modes, see MAC.CONFIG1 for details.)
++}LED_STRATEGY_871x, *PLED_STRATEGY_871x;
++#endif //CONFIG_USB_HCI
++
++#ifdef CONFIG_PCI_HCI
++//================================================================================
++// LED object.
++//================================================================================
++
++typedef enum _LED_STATE_871x{
++ LED_UNKNOWN = 0,
++ RTW_LED_ON = 1,
++ RTW_LED_OFF = 2,
++ LED_BLINK_NORMAL = 3,
++ LED_BLINK_SLOWLY = 4,
++ LED_POWER_ON_BLINK = 5,
++ LED_SCAN_BLINK = 6, // LED is blinking during scanning period, the # of times to blink is depend on time for scanning.
++ LED_NO_LINK_BLINK = 7, // LED is blinking during no link state.
++ LED_BLINK_StartToBlink = 8,
++ LED_BLINK_TXRX = 9,
++ LED_BLINK_RUNTOP = 10, // Customized for RunTop
++ LED_BLINK_CAMEO = 11,
++}LED_STATE_871x;
++
++typedef enum _LED_PIN_871x{
++ LED_PIN_GPIO0,
++ LED_PIN_LED0,
++ LED_PIN_LED1,
++ LED_PIN_LED2
++}LED_PIN_871x;
++
++typedef struct _LED_871x{
++ _adapter *padapter;
++
++ LED_PIN_871x LedPin; // Identify how to implement this SW led.
++
++ LED_STATE_871x CurrLedState; // Current LED state.
++ u8 bLedOn; // TRUE if LED is ON, FALSE if LED is OFF.
++
++ u8 bLedBlinkInProgress; // TRUE if it is blinking, FALSE o.w..
++ u8 bLedWPSBlinkInProgress; // TRUE if it is blinking, FALSE o.w..
++
++ u8 bLedSlowBlinkInProgress;//added by vivi, for led new mode
++ u32 BlinkTimes; // Number of times to toggle led state for blinking.
++ LED_STATE_871x BlinkingLedState; // Next state for blinking, either RTW_LED_ON or RTW_LED_OFF are.
++
++ _timer BlinkTimer; // Timer object for led blinking.
++
++ u8 bLedLinkBlinkInProgress;
++ u8 bLedNoLinkBlinkInProgress;
++ u8 bLedScanBlinkInProgress;
++} LED_871x, *PLED_871x;
++
++
++//================================================================================
++// LED customization.
++//================================================================================
++
++typedef enum _LED_STRATEGY_871x{
++ SW_LED_MODE0, // SW control 1 LED via GPIO0. It is default option.
++ SW_LED_MODE1, // SW control for PCI Express
++ SW_LED_MODE2, // SW control for Cameo.
++ SW_LED_MODE3, // SW contorl for RunTop.
++ SW_LED_MODE4, // SW control for Netcore
++ SW_LED_MODE5, //added by vivi, for led new mode, DLINK
++ SW_LED_MODE6, //added by vivi, for led new mode, PRONET
++ SW_LED_MODE7, //added by chiyokolin, for Lenovo, PCI Express Minicard Spec Rev.1.2 spec
++ SW_LED_MODE8, //added by chiyokolin, for QMI
++ SW_LED_MODE9, //added by chiyokolin, for BITLAND, PCI Express Minicard Spec Rev.1.1
++ SW_LED_MODE10, //added by chiyokolin, for Edimax-ASUS
++ HW_LED, // HW control 2 LEDs, LED0 and LED1 (there are 4 different control modes)
++}LED_STRATEGY_871x, *PLED_STRATEGY_871x;
++
++#define LED_CM8_BLINK_INTERVAL 500 //for QMI
++#endif //CONFIG_PCI_HCI
++
++struct led_priv{
++ /* add for led controll */
++ LED_871x SwLed0;
++ LED_871x SwLed1;
++ LED_STRATEGY_871x LedStrategy;
++ u8 bRegUseLed;
++ void (*LedControlHandler)(_adapter *padapter, LED_CTL_MODE LedAction);
++ /* add for led controll */
++};
++
++#ifdef CONFIG_SW_LED
++#define rtw_led_control(adapter, LedAction) \
++ do { \
++ if((adapter)->ledpriv.LedControlHandler) \
++ (adapter)->ledpriv.LedControlHandler((adapter), (LedAction)); \
++ } while(0)
++#else //CONFIG_SW_LED
++#define rtw_led_control(adapter, LedAction)
++#endif //CONFIG_SW_LED
++
++extern void BlinkHandler(PLED_871x pLed);
++
++#endif //__RTW_LED_H_
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtw_mlme_ext.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtw_mlme_ext.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtw_mlme_ext.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtw_mlme_ext.h 2015-07-28 01:20:58.321597318 +0200
+@@ -0,0 +1,962 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef __RTW_MLME_EXT_H_
++#define __RTW_MLME_EXT_H_
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++#include <wlan_bssdef.h>
++
++
++// Commented by Albert 20101105
++// Increase the SURVEY_TO value from 100 to 150 ( 100ms to 150ms )
++// The Realtek 8188CE SoftAP will spend around 100ms to send the probe response after receiving the probe request.
++// So, this driver tried to extend the dwell time for each scanning channel.
++// This will increase the chance to receive the probe response from SoftAP.
++
++#define SURVEY_TO (100)
++#define REAUTH_TO (300) //(50)
++#define REASSOC_TO (300) //(50)
++//#define DISCONNECT_TO (3000)
++#define ADDBA_TO (2000)
++
++#define LINKED_TO (1) //unit:2 sec, 1x2=2 sec
++
++#define REAUTH_LIMIT (4)
++#define REASSOC_LIMIT (4)
++#define READDBA_LIMIT (2)
++
++//#define IOCMD_REG0 0x10250370
++//#define IOCMD_REG1 0x10250374
++//#define IOCMD_REG2 0x10250378
++
++//#define FW_DYNAMIC_FUN_SWITCH 0x10250364
++
++//#define WRITE_BB_CMD 0xF0000001
++//#define SET_CHANNEL_CMD 0xF3000000
++//#define UPDATE_RA_CMD 0xFD0000A2
++
++#define DYNAMIC_FUNC_DISABLE (0x0)
++#define DYNAMIC_FUNC_DIG BIT(0)
++#define DYNAMIC_FUNC_HP BIT(1)
++#define DYNAMIC_FUNC_SS BIT(2) //Tx Power Tracking
++#define DYNAMIC_FUNC_BT BIT(3)
++#define DYNAMIC_FUNC_ANT_DIV BIT(4)
++#define DYNAMIC_FUNC_ADAPTIVITY BIT(5)
++
++#define _HW_STATE_NOLINK_ 0x00
++#define _HW_STATE_ADHOC_ 0x01
++#define _HW_STATE_STATION_ 0x02
++#define _HW_STATE_AP_ 0x03
++
++
++#define _1M_RATE_ 0
++#define _2M_RATE_ 1
++#define _5M_RATE_ 2
++#define _11M_RATE_ 3
++#define _6M_RATE_ 4
++#define _9M_RATE_ 5
++#define _12M_RATE_ 6
++#define _18M_RATE_ 7
++#define _24M_RATE_ 8
++#define _36M_RATE_ 9
++#define _48M_RATE_ 10
++#define _54M_RATE_ 11
++
++
++extern unsigned char RTW_WPA_OUI[];
++extern unsigned char WMM_OUI[];
++extern unsigned char WPS_OUI[];
++extern unsigned char WFD_OUI[];
++extern unsigned char P2P_OUI[];
++
++extern unsigned char WMM_INFO_OUI[];
++extern unsigned char WMM_PARA_OUI[];
++
++
++//
++// Channel Plan Type.
++// Note:
++// We just add new channel plan when the new channel plan is different from any of the following
++// channel plan.
++// If you just wnat to customize the acitions(scan period or join actions) about one of the channel plan,
++// customize them in RT_CHANNEL_INFO in the RT_CHANNEL_LIST.
++//
++typedef enum _RT_CHANNEL_DOMAIN
++{
++ //===== old channel plan mapping =====//
++ RT_CHANNEL_DOMAIN_FCC = 0x00,
++ RT_CHANNEL_DOMAIN_IC = 0x01,
++ RT_CHANNEL_DOMAIN_ETSI = 0x02,
++ RT_CHANNEL_DOMAIN_SPAIN = 0x03,
++ RT_CHANNEL_DOMAIN_FRANCE = 0x04,
++ RT_CHANNEL_DOMAIN_MKK = 0x05,
++ RT_CHANNEL_DOMAIN_MKK1 = 0x06,
++ RT_CHANNEL_DOMAIN_ISRAEL = 0x07,
++ RT_CHANNEL_DOMAIN_TELEC = 0x08,
++ RT_CHANNEL_DOMAIN_GLOBAL_DOAMIN = 0x09,
++ RT_CHANNEL_DOMAIN_WORLD_WIDE_13 = 0x0A,
++ RT_CHANNEL_DOMAIN_TAIWAN = 0x0B,
++ RT_CHANNEL_DOMAIN_CHINA = 0x0C,
++ RT_CHANNEL_DOMAIN_SINGAPORE_INDIA_MEXICO = 0x0D,
++ RT_CHANNEL_DOMAIN_KOREA = 0x0E,
++ RT_CHANNEL_DOMAIN_TURKEY = 0x0F,
++ RT_CHANNEL_DOMAIN_JAPAN = 0x10,
++ RT_CHANNEL_DOMAIN_FCC_NO_DFS = 0x11,
++ RT_CHANNEL_DOMAIN_JAPAN_NO_DFS = 0x12,
++ RT_CHANNEL_DOMAIN_WORLD_WIDE_5G = 0x13,
++ RT_CHANNEL_DOMAIN_TAIWAN_NO_DFS = 0x14,
++
++ //===== new channel plan mapping, (2GDOMAIN_5GDOMAIN) =====//
++ RT_CHANNEL_DOMAIN_WORLD_NULL = 0x20,
++ RT_CHANNEL_DOMAIN_ETSI1_NULL = 0x21,
++ RT_CHANNEL_DOMAIN_FCC1_NULL = 0x22,
++ RT_CHANNEL_DOMAIN_MKK1_NULL = 0x23,
++ RT_CHANNEL_DOMAIN_ETSI2_NULL = 0x24,
++ RT_CHANNEL_DOMAIN_FCC1_FCC1 = 0x25,
++ RT_CHANNEL_DOMAIN_WORLD_ETSI1 = 0x26,
++ RT_CHANNEL_DOMAIN_MKK1_MKK1 = 0x27,
++ RT_CHANNEL_DOMAIN_WORLD_KCC1 = 0x28,
++ RT_CHANNEL_DOMAIN_WORLD_FCC2 = 0x29,
++ RT_CHANNEL_DOMAIN_WORLD_FCC3 = 0x30,
++ RT_CHANNEL_DOMAIN_WORLD_FCC4 = 0x31,
++ RT_CHANNEL_DOMAIN_WORLD_FCC5 = 0x32,
++ RT_CHANNEL_DOMAIN_WORLD_FCC6 = 0x33,
++ RT_CHANNEL_DOMAIN_FCC1_FCC7 = 0x34,
++ RT_CHANNEL_DOMAIN_WORLD_ETSI2 = 0x35,
++ RT_CHANNEL_DOMAIN_WORLD_ETSI3 = 0x36,
++ RT_CHANNEL_DOMAIN_MKK1_MKK2 = 0x37,
++ RT_CHANNEL_DOMAIN_MKK1_MKK3 = 0x38,
++ RT_CHANNEL_DOMAIN_FCC1_NCC1 = 0x39,
++ RT_CHANNEL_DOMAIN_FCC1_NCC2 = 0x40,
++
++ //===== Add new channel plan above this line===============//
++ RT_CHANNEL_DOMAIN_MAX,
++ RT_CHANNEL_DOMAIN_REALTEK_DEFINE = 0x7F,
++}RT_CHANNEL_DOMAIN, *PRT_CHANNEL_DOMAIN;
++
++typedef enum _RT_CHANNEL_DOMAIN_2G
++{
++ RT_CHANNEL_DOMAIN_2G_WORLD = 0x00, //Worldwird 13
++ RT_CHANNEL_DOMAIN_2G_ETSI1 = 0x01, //Europe
++ RT_CHANNEL_DOMAIN_2G_FCC1 = 0x02, //US
++ RT_CHANNEL_DOMAIN_2G_MKK1 = 0x03, //Japan
++ RT_CHANNEL_DOMAIN_2G_ETSI2 = 0x04, //France
++ RT_CHANNEL_DOMAIN_2G_NULL = 0x05,
++ //===== Add new channel plan above this line===============//
++ RT_CHANNEL_DOMAIN_2G_MAX,
++}RT_CHANNEL_DOMAIN_2G, *PRT_CHANNEL_DOMAIN_2G;
++
++typedef enum _RT_CHANNEL_DOMAIN_5G
++{
++ RT_CHANNEL_DOMAIN_5G_NULL = 0x00,
++ RT_CHANNEL_DOMAIN_5G_ETSI1 = 0x01, //Europe
++ RT_CHANNEL_DOMAIN_5G_ETSI2 = 0x02, //Australia, New Zealand
++ RT_CHANNEL_DOMAIN_5G_ETSI3 = 0x03, //Russia
++ RT_CHANNEL_DOMAIN_5G_FCC1 = 0x04, //US
++ RT_CHANNEL_DOMAIN_5G_FCC2 = 0x05, //FCC o/w DFS Channels
++ RT_CHANNEL_DOMAIN_5G_FCC3 = 0x06, //India, Mexico
++ RT_CHANNEL_DOMAIN_5G_FCC4 = 0x07, //Venezuela
++ RT_CHANNEL_DOMAIN_5G_FCC5 = 0x08, //China
++ RT_CHANNEL_DOMAIN_5G_FCC6 = 0x09, //Israel
++ RT_CHANNEL_DOMAIN_5G_FCC7_IC1 = 0x0A, //US, Canada
++ RT_CHANNEL_DOMAIN_5G_KCC1 = 0x0B, //Korea
++ RT_CHANNEL_DOMAIN_5G_MKK1 = 0x0C, //Japan
++ RT_CHANNEL_DOMAIN_5G_MKK2 = 0x0D, //Japan (W52, W53)
++ RT_CHANNEL_DOMAIN_5G_MKK3 = 0x0E, //Japan (W56)
++ RT_CHANNEL_DOMAIN_5G_NCC1 = 0x0F, //Taiwan
++ RT_CHANNEL_DOMAIN_5G_NCC2 = 0x10, //Taiwan o/w DFS
++ //===== Add new channel plan above this line===============//
++ //===== Driver Self Defined =====//
++ RT_CHANNEL_DOMAIN_5G_FCC = 0x11,
++ RT_CHANNEL_DOMAIN_5G_JAPAN_NO_DFS = 0x12,
++ RT_CHANNEL_DOMAIN_5G_FCC4_NO_DFS = 0x13,
++ RT_CHANNEL_DOMAIN_5G_MAX,
++}RT_CHANNEL_DOMAIN_5G, *PRT_CHANNEL_DOMAIN_5G;
++
++#define rtw_is_channel_plan_valid(chplan) (chplan<RT_CHANNEL_DOMAIN_MAX || chplan == RT_CHANNEL_DOMAIN_REALTEK_DEFINE)
++
++typedef struct _RT_CHANNEL_PLAN
++{
++ unsigned char Channel[MAX_CHANNEL_NUM];
++ unsigned char Len;
++}RT_CHANNEL_PLAN, *PRT_CHANNEL_PLAN;
++
++typedef struct _RT_CHANNEL_PLAN_2G
++{
++ unsigned char Channel[MAX_CHANNEL_NUM_2G];
++ unsigned char Len;
++}RT_CHANNEL_PLAN_2G, *PRT_CHANNEL_PLAN_2G;
++
++typedef struct _RT_CHANNEL_PLAN_5G
++{
++ unsigned char Channel[MAX_CHANNEL_NUM_5G];
++ unsigned char Len;
++}RT_CHANNEL_PLAN_5G, *PRT_CHANNEL_PLAN_5G;
++
++typedef struct _RT_CHANNEL_PLAN_MAP
++{
++ unsigned char Index2G;
++ unsigned char Index5G;
++}RT_CHANNEL_PLAN_MAP, *PRT_CHANNEL_PLAN_MAP;
++
++enum Associated_AP
++{
++ atherosAP = 0,
++ broadcomAP = 1,
++ ciscoAP = 2,
++ marvellAP = 3,
++ ralinkAP = 4,
++ realtekAP = 5,
++ airgocapAP = 6,
++ unknownAP = 7,
++ maxAP,
++};
++
++enum SCAN_STATE
++{
++ SCAN_DISABLE = 0,
++ SCAN_START = 1,
++ SCAN_TXNULL = 2,
++ SCAN_PROCESS = 3,
++ SCAN_COMPLETE = 4,
++ SCAN_STATE_MAX,
++};
++
++struct mlme_handler {
++ unsigned int num;
++ char* str;
++ unsigned int (*func)(_adapter *padapter, union recv_frame *precv_frame);
++};
++
++struct action_handler {
++ unsigned int num;
++ char* str;
++ unsigned int (*func)(_adapter *padapter, union recv_frame *precv_frame);
++};
++
++struct ss_res
++{
++ int state;
++ int bss_cnt;
++ int channel_idx;
++ int scan_mode;
++ u8 ssid_num;
++ u8 ch_num;
++ NDIS_802_11_SSID ssid[RTW_SSID_SCAN_AMOUNT];
++ struct rtw_ieee80211_channel ch[RTW_CHANNEL_SCAN_AMOUNT];
++};
++
++//#define AP_MODE 0x0C
++//#define STATION_MODE 0x08
++//#define AD_HOC_MODE 0x04
++//#define NO_LINK_MODE 0x00
++
++#define WIFI_FW_NULL_STATE _HW_STATE_NOLINK_
++#define WIFI_FW_STATION_STATE _HW_STATE_STATION_
++#define WIFI_FW_AP_STATE _HW_STATE_AP_
++#define WIFI_FW_ADHOC_STATE _HW_STATE_ADHOC_
++
++#define WIFI_FW_AUTH_NULL 0x00000100
++#define WIFI_FW_AUTH_STATE 0x00000200
++#define WIFI_FW_AUTH_SUCCESS 0x00000400
++
++#define WIFI_FW_ASSOC_STATE 0x00002000
++#define WIFI_FW_ASSOC_SUCCESS 0x00004000
++
++#define WIFI_FW_LINKING_STATE (WIFI_FW_AUTH_NULL | WIFI_FW_AUTH_STATE | WIFI_FW_AUTH_SUCCESS |WIFI_FW_ASSOC_STATE)
++
++#ifdef CONFIG_TDLS
++// 1: Write RCR DATA BIT
++// 2: Issue peer traffic indication
++// 3: Go back to the channel linked with AP, terminating channel switch procedure
++// 4: Init channel sensing, receive all data and mgnt frame
++// 5: Channel sensing and report candidate channel
++// 6: First time set channel to off channel
++// 7: Go back tp the channel linked with AP when set base channel as target channel
++// 8: Set channel back to base channel
++// 9: Set channel back to off channel
++// 10: Restore RCR DATA BIT
++// 11: Check alive
++// 12: Check alive
++// 13: Free TDLS sta
++enum TDLS_option
++{
++ TDLS_WRCR = 1,
++ TDLS_SD_PTI = 2,
++ TDLS_CS_OFF = 3,
++ TDLS_INIT_CH_SEN = 4,
++ TDLS_DONE_CH_SEN = 5,
++ TDLS_OFF_CH = 6,
++ TDLS_BASE_CH = 7,
++ TDLS_P_OFF_CH = 8,
++ TDLS_P_BASE_CH = 9,
++ TDLS_RS_RCR = 10,
++ TDLS_CKALV_PH1 = 11,
++ TDLS_CKALV_PH2 = 12,
++ TDLS_FREE_STA = 13,
++ maxTDLS,
++};
++
++#endif //CONFIG_TDLS
++
++struct FW_Sta_Info
++{
++ struct sta_info *psta;
++ u32 status;
++ u32 rx_pkt;
++ u32 retry;
++ NDIS_802_11_RATES_EX SupportedRates;
++};
++
++/*
++ * Usage:
++ * When one iface acted as AP mode and the other iface is STA mode and scanning,
++ * it should switch back to AP's operating channel periodically.
++ * Parameters info:
++ * When the driver scanned RTW_SCAN_NUM_OF_CH channels, it would switch back to AP's operating channel for
++ * RTW_STAY_AP_CH_MILLISECOND * SURVEY_TO milliseconds.
++ * Example:
++ * For chip supports 2.4G + 5GHz and AP mode is operating in channel 1,
++ * RTW_SCAN_NUM_OF_CH is 8, RTW_STAY_AP_CH_MILLISECOND is 3 and SURVEY_TO is 100.
++ * When it's STA mode gets set_scan command,
++ * it would
++ * 1. Doing the scan on channel 1.2.3.4.5.6.7.8
++ * 2. Back to channel 1 for 300 milliseconds
++ * 3. Go through doing site survey on channel 9.10.11.36.40.44.48.52
++ * 4. Back to channel 1 for 300 milliseconds
++ * 5. ... and so on, till survey done.
++ */
++#if defined CONFIG_STA_MODE_SCAN_UNDER_AP_MODE && defined CONFIG_CONCURRENT_MODE
++#define RTW_SCAN_NUM_OF_CH 8
++#define RTW_STAY_AP_CH_MILLISECOND 3 // this value is a multiplier,for example, when this value is 3, it would stay AP's op ch for
++ // 3 * SURVEY_TO millisecond.
++#endif //defined CONFIG_STA_MODE_SCAN_UNDER_AP_MODE && defined CONFIG_CONCURRENT_MODE
++
++struct mlme_ext_info
++{
++ u32 state;
++ u32 reauth_count;
++ u32 reassoc_count;
++ u32 link_count;
++ u32 auth_seq;
++ u32 auth_algo; // 802.11 auth, could be open, shared, auto
++ u32 authModeToggle;
++ u32 enc_algo;//encrypt algorithm;
++ u32 key_index; // this is only valid for legendary wep, 0~3 for key id.
++ u32 iv;
++ u8 chg_txt[128];
++ u16 aid;
++ u16 bcn_interval;
++ u16 capability;
++ u8 assoc_AP_vendor;
++ u8 slotTime;
++ u8 preamble_mode;
++ u8 WMM_enable;
++ u8 ERP_enable;
++ u8 ERP_IE;
++ u8 HT_enable;
++ u8 HT_caps_enable;
++ u8 HT_info_enable;
++ u8 HT_protection;
++ u8 turboMode_cts2self;
++ u8 turboMode_rtsen;
++ u8 SM_PS;
++ u8 agg_enable_bitmap;
++ u8 ADDBA_retry_count;
++ u8 candidate_tid_bitmap;
++ u8 dialogToken;
++ // Accept ADDBA Request
++ BOOLEAN bAcceptAddbaReq;
++ u8 bwmode_updated;
++ u8 hidden_ssid_mode;
++
++ struct ADDBA_request ADDBA_req;
++ struct WMM_para_element WMM_param;
++ struct HT_caps_element HT_caps;
++ struct HT_info_element HT_info;
++ WLAN_BSSID_EX network;//join network or bss_network, if in ap mode, it is the same to cur_network.network
++ struct FW_Sta_Info FW_sta_info[NUM_STA];
++
++#ifdef CONFIG_STA_MODE_SCAN_UNDER_AP_MODE
++ u8 scan_cnt;
++#endif //CONFIG_STA_MODE_SCAN_UNDER_AP_MODE
++};
++
++// The channel information about this channel including joining, scanning, and power constraints.
++typedef struct _RT_CHANNEL_INFO
++{
++ u8 ChannelNum; // The channel number.
++ RT_SCAN_TYPE ScanType; // Scan type such as passive or active scan.
++ //u16 ScanPeriod; // Listen time in millisecond in this channel.
++ //s32 MaxTxPwrDbm; // Max allowed tx power.
++ //u32 ExInfo; // Extended Information for this channel.
++#ifdef CONFIG_FIND_BEST_CHANNEL
++ u32 rx_count;
++#endif
++}RT_CHANNEL_INFO, *PRT_CHANNEL_INFO;
++
++int rtw_ch_set_search_ch(RT_CHANNEL_INFO *ch_set, const u32 ch);
++bool rtw_mlme_band_check(_adapter *adapter, const u32 ch);
++
++// P2P_MAX_REG_CLASSES - Maximum number of regulatory classes
++#define P2P_MAX_REG_CLASSES 10
++
++// P2P_MAX_REG_CLASS_CHANNELS - Maximum number of channels per regulatory class
++#define P2P_MAX_REG_CLASS_CHANNELS 20
++
++// struct p2p_channels - List of supported channels
++struct p2p_channels {
++ // struct p2p_reg_class - Supported regulatory class
++ struct p2p_reg_class {
++ // reg_class - Regulatory class (IEEE 802.11-2007, Annex J)
++ u8 reg_class;
++
++ // channel - Supported channels
++ u8 channel[P2P_MAX_REG_CLASS_CHANNELS];
++
++ // channels - Number of channel entries in use
++ size_t channels;
++ } reg_class[P2P_MAX_REG_CLASSES];
++
++ // reg_classes - Number of reg_class entries in use
++ size_t reg_classes;
++};
++
++struct p2p_oper_class_map {
++ enum hw_mode {IEEE80211G,IEEE80211A} mode;
++ u8 op_class;
++ u8 min_chan;
++ u8 max_chan;
++ u8 inc;
++ enum { BW20, BW40PLUS, BW40MINUS } bw;
++};
++
++struct mlme_ext_priv
++{
++ _adapter *padapter;
++ u8 mlmeext_init;
++ ATOMIC_T event_seq;
++ u16 mgnt_seq;
++#ifdef CONFIG_IEEE80211W
++ u16 sa_query_seq;
++ u64 mgnt_80211w_IPN;
++ u64 mgnt_80211w_IPN_rx;
++#endif //CONFIG_IEEE80211W
++ //struct fw_priv fwpriv;
++
++ unsigned char cur_channel;
++ unsigned char cur_bwmode;
++ unsigned char cur_ch_offset;//PRIME_CHNL_OFFSET
++ unsigned char cur_wireless_mode;
++
++ unsigned char max_chan_nums;
++ RT_CHANNEL_INFO channel_set[MAX_CHANNEL_NUM];
++ struct p2p_channels channel_list;
++ unsigned char basicrate[NumRates];
++ unsigned char datarate[NumRates];
++
++ struct ss_res sitesurvey_res;
++ struct mlme_ext_info mlmext_info;//for sta/adhoc mode, including current scanning/connecting/connected related info.
++ //for ap mode, network includes ap's cap_info
++ _timer survey_timer;
++ _timer link_timer;
++#ifdef CONFIG_IEEE80211W
++ _timer sa_query_timer;
++#endif //CONFIG_IEEE80211W
++ //_timer ADDBA_timer;
++ u16 chan_scan_time;
++
++ u8 scan_abort;
++ u8 tx_rate; // TXRATE when USERATE is set.
++
++ u32 retry; //retry for issue probereq
++
++ u64 TSFValue;
++
++#ifdef CONFIG_AP_MODE
++ unsigned char bstart_bss;
++#endif
++
++ //recv_decache check for Action_public frame
++ u8 action_public_dialog_token;
++ u16 action_public_rxseq;
++
++#ifdef CONFIG_80211D
++ u8 update_channel_plan_by_ap_done;
++#endif
++
++#ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK
++ u8 active_keep_alive_check;
++#endif
++
++};
++
++int init_mlme_ext_priv(_adapter* padapter);
++int init_hw_mlme_ext(_adapter *padapter);
++void free_mlme_ext_priv (struct mlme_ext_priv *pmlmeext);
++extern void init_mlme_ext_timer(_adapter *padapter);
++extern void init_addba_retry_timer(_adapter *padapter, struct sta_info *psta);
++extern struct xmit_frame *alloc_mgtxmitframe(struct xmit_priv *pxmitpriv);
++struct xmit_frame *alloc_mgtxmitframe_once(struct xmit_priv *pxmitpriv);
++
++//void fill_fwpriv(_adapter * padapter, struct fw_priv *pfwpriv);
++
++unsigned char networktype_to_raid(unsigned char network_type);
++int judge_network_type(_adapter *padapter, unsigned char *rate, int ratelen);
++void get_rate_set(_adapter *padapter, unsigned char *pbssrate, int *bssrate_len);
++void UpdateBrateTbl(_adapter *padapter,u8 *mBratesOS);
++void UpdateBrateTblForSoftAP(u8 *bssrateset, u32 bssratelen);
++void change_band_update_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork);
++
++void Save_DM_Func_Flag(_adapter *padapter);
++void Restore_DM_Func_Flag(_adapter *padapter);
++void Switch_DM_Func(_adapter *padapter, u8 mode, u8 enable);
++
++//void Set_NETYPE1_MSR(_adapter *padapter, u8 type);
++//void Set_NETYPE0_MSR(_adapter *padapter, u8 type);
++void Set_MSR(_adapter *padapter, u8 type);
++
++u8 rtw_get_oper_ch(_adapter *adapter);
++void rtw_set_oper_ch(_adapter *adapter, u8 ch);
++u8 rtw_get_oper_bw(_adapter *adapter);
++void rtw_set_oper_bw(_adapter *adapter, u8 bw);
++u8 rtw_get_oper_choffset(_adapter *adapter);
++void rtw_set_oper_choffset(_adapter *adapter, u8 offset);
++u32 rtw_get_on_oper_ch_time(_adapter *adapter);
++u32 rtw_get_on_cur_ch_time(_adapter *adapter);
++
++void set_channel_bwmode(_adapter *padapter, unsigned char channel, unsigned char channel_offset, unsigned short bwmode);
++void SelectChannel(_adapter *padapter, unsigned char channel);
++void SetBWMode(_adapter *padapter, unsigned short bwmode, unsigned char channel_offset);
++
++unsigned int decide_wait_for_beacon_timeout(unsigned int bcn_interval);
++
++void write_cam(_adapter *padapter, u8 entry, u16 ctrl, u8 *mac, u8 *key);
++void clear_cam_entry(_adapter *padapter, u8 entry);
++
++void invalidate_cam_all(_adapter *padapter);
++void CAM_empty_entry(PADAPTER Adapter, u8 ucIndex);
++
++
++int allocate_fw_sta_entry(_adapter *padapter);
++void flush_all_cam_entry(_adapter *padapter);
++
++BOOLEAN IsLegal5GChannel(PADAPTER Adapter, u8 channel);
++
++void site_survey(_adapter *padapter);
++u8 collect_bss_info(_adapter *padapter, union recv_frame *precv_frame, WLAN_BSSID_EX *bssid);
++
++int get_bsstype(unsigned short capability);
++u8* get_my_bssid(WLAN_BSSID_EX *pnetwork);
++u16 get_beacon_interval(WLAN_BSSID_EX *bss);
++
++int is_client_associated_to_ap(_adapter *padapter);
++int is_client_associated_to_ibss(_adapter *padapter);
++int is_IBSS_empty(_adapter *padapter);
++
++unsigned char check_assoc_AP(u8 *pframe, uint len);
++
++int WMM_param_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE);
++#ifdef CONFIG_WFD
++int WFD_info_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE);
++#endif
++void WMMOnAssocRsp(_adapter *padapter);
++
++void HT_caps_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE);
++void HT_info_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE);
++void HTOnAssocRsp(_adapter *padapter);
++
++void ERP_IE_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE);
++void VCS_update(_adapter *padapter, struct sta_info *psta);
++
++void update_beacon_info(_adapter *padapter, u8 *pframe, uint len, struct sta_info *psta);
++#ifdef CONFIG_DFS
++void process_csa_ie(_adapter *padapter, u8 *pframe, uint len);
++#endif //CONFIG_DFS
++void update_IOT_info(_adapter *padapter);
++void update_capinfo(PADAPTER Adapter, u16 updateCap);
++void update_wireless_mode(_adapter * padapter);
++void update_tx_basic_rate(_adapter *padapter, u8 modulation);
++void update_bmc_sta_support_rate(_adapter *padapter, u32 mac_id);
++int update_sta_support_rate(_adapter *padapter, u8* pvar_ie, uint var_ie_len, int cam_idx);
++
++//for sta/adhoc mode
++void update_sta_info(_adapter *padapter, struct sta_info *psta);
++unsigned int update_basic_rate(unsigned char *ptn, unsigned int ptn_sz);
++unsigned int update_supported_rate(unsigned char *ptn, unsigned int ptn_sz);
++unsigned int update_MSC_rate(struct HT_caps_element *pHT_caps);
++void Update_RA_Entry(_adapter *padapter, u32 mac_id);
++void set_sta_rate(_adapter *padapter, struct sta_info *psta);
++
++unsigned int receive_disconnect(_adapter *padapter, unsigned char *MacAddr, unsigned short reason);
++
++unsigned char get_highest_rate_idx(u32 mask);
++int support_short_GI(_adapter *padapter, struct HT_caps_element *pHT_caps);
++unsigned int is_ap_in_tkip(_adapter *padapter);
++
++
++void report_join_res(_adapter *padapter, int res);
++void report_survey_event(_adapter *padapter, union recv_frame *precv_frame);
++void report_surveydone_event(_adapter *padapter);
++void report_del_sta_event(_adapter *padapter, unsigned char* MacAddr, unsigned short reason);
++void report_add_sta_event(_adapter *padapter, unsigned char* MacAddr, int cam_idx);
++
++void beacon_timing_control(_adapter *padapter);
++extern u8 set_tx_beacon_cmd(_adapter*padapter);
++unsigned int setup_beacon_frame(_adapter *padapter, unsigned char *beacon_frame);
++void update_mgnt_tx_rate(_adapter *padapter, u8 rate);
++void update_mgntframe_attrib(_adapter *padapter, struct pkt_attrib *pattrib);
++void dump_mgntframe(_adapter *padapter, struct xmit_frame *pmgntframe);
++s32 dump_mgntframe_and_wait(_adapter *padapter, struct xmit_frame *pmgntframe, int timeout_ms);
++s32 dump_mgntframe_and_wait_ack(_adapter *padapter, struct xmit_frame *pmgntframe);
++
++#ifdef CONFIG_P2P
++void issue_probersp_p2p(_adapter *padapter, unsigned char *da);
++void issue_p2p_provision_request( _adapter *padapter, u8* pssid, u8 ussidlen, u8* pdev_raddr);
++void issue_p2p_GO_request(_adapter *padapter, u8* raddr);
++void issue_probereq_p2p(_adapter *padapter, u8 *da);
++int issue_probereq_p2p_ex(_adapter *adapter, u8 *da, int try_cnt, int wait_ms);
++void issue_p2p_invitation_response(_adapter *padapter, u8* raddr, u8 dialogToken, u8 success);
++void issue_p2p_invitation_request(_adapter *padapter, u8* raddr );
++#endif //CONFIG_P2P
++void issue_beacon(_adapter *padapter);
++void issue_probersp(_adapter *padapter, unsigned char *da, u8 is_valid_p2p_probereq);
++void issue_assocreq(_adapter *padapter);
++void issue_asocrsp(_adapter *padapter, unsigned short status, struct sta_info *pstat, int pkt_type);
++void issue_auth(_adapter *padapter, struct sta_info *psta, unsigned short status);
++void issue_probereq(_adapter *padapter, NDIS_802_11_SSID *pssid, u8 *da);
++s32 issue_probereq_ex(_adapter *padapter, NDIS_802_11_SSID *pssid, u8* da, int try_cnt, int wait_ms);
++int issue_nulldata(_adapter *padapter, unsigned char *da, unsigned int power_mode, int try_cnt, int wait_ms);
++int issue_qos_nulldata(_adapter *padapter, unsigned char *da, u16 tid, int try_cnt, int wait_ms);
++int issue_deauth(_adapter *padapter, unsigned char *da, unsigned short reason);
++int issue_deauth_ex(_adapter *padapter, u8 *da, unsigned short reason, int try_cnt, int wait_ms);
++void issue_action_spct_ch_switch(_adapter *padapter, u8 *ra, u8 new_ch, u8 ch_offset);
++void issue_action_BA(_adapter *padapter, unsigned char *raddr, unsigned char action, unsigned short status);
++#ifdef CONFIG_IEEE80211W
++void issue_action_SA_Query(_adapter *padapter, unsigned char *raddr, unsigned char action, unsigned short tid);
++#endif //CONFIG_IEEE80211W
++unsigned int send_delba(_adapter *padapter, u8 initiator, u8 *addr);
++unsigned int send_beacon(_adapter *padapter);
++
++void start_clnt_assoc(_adapter *padapter);
++void start_clnt_auth(_adapter* padapter);
++void start_clnt_join(_adapter* padapter);
++void start_create_ibss(_adapter* padapter);
++
++unsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame);
++unsigned int OnAssocRsp(_adapter *padapter, union recv_frame *precv_frame);
++unsigned int OnProbeReq(_adapter *padapter, union recv_frame *precv_frame);
++unsigned int OnProbeRsp(_adapter *padapter, union recv_frame *precv_frame);
++unsigned int DoReserved(_adapter *padapter, union recv_frame *precv_frame);
++unsigned int OnBeacon(_adapter *padapter, union recv_frame *precv_frame);
++unsigned int OnAtim(_adapter *padapter, union recv_frame *precv_frame);
++unsigned int OnDisassoc(_adapter *padapter, union recv_frame *precv_frame);
++unsigned int OnAuth(_adapter *padapter, union recv_frame *precv_frame);
++unsigned int OnAuthClient(_adapter *padapter, union recv_frame *precv_frame);
++unsigned int OnDeAuth(_adapter *padapter, union recv_frame *precv_frame);
++unsigned int OnAction(_adapter *padapter, union recv_frame *precv_frame);
++
++unsigned int on_action_spct(_adapter *padapter, union recv_frame *precv_frame);
++unsigned int OnAction_qos(_adapter *padapter, union recv_frame *precv_frame);
++unsigned int OnAction_dls(_adapter *padapter, union recv_frame *precv_frame);
++unsigned int OnAction_back(_adapter *padapter, union recv_frame *precv_frame);
++unsigned int on_action_public(_adapter *padapter, union recv_frame *precv_frame);
++unsigned int OnAction_ht(_adapter *padapter, union recv_frame *precv_frame);
++#ifdef CONFIG_IEEE80211W
++unsigned int OnAction_sa_query(_adapter *padapter, union recv_frame *precv_frame);
++#endif //CONFIG_IEEE80211W
++unsigned int OnAction_wmm(_adapter *padapter, union recv_frame *precv_frame);
++unsigned int OnAction_p2p(_adapter *padapter, union recv_frame *precv_frame);
++
++
++void mlmeext_joinbss_event_callback(_adapter *padapter, int join_res);
++void mlmeext_sta_del_event_callback(_adapter *padapter);
++void mlmeext_sta_add_event_callback(_adapter *padapter, struct sta_info *psta);
++
++void linked_status_chk(_adapter *padapter);
++
++void survey_timer_hdl (_adapter *padapter);
++void link_timer_hdl (_adapter *padapter);
++void addba_timer_hdl(struct sta_info *psta);
++#ifdef CONFIG_IEEE80211W
++void sa_query_timer_hdl(_adapter *padapter);
++#endif //CONFIG_IEEE80211W
++//void reauth_timer_hdl(_adapter *padapter);
++//void reassoc_timer_hdl(_adapter *padapter);
++
++#define set_survey_timer(mlmeext, ms) \
++ do { \
++ /*DBG_871X("%s set_survey_timer(%p, %d)\n", __FUNCTION__, (mlmeext), (ms));*/ \
++ _set_timer(&(mlmeext)->survey_timer, (ms)); \
++ } while(0)
++
++#define set_link_timer(mlmeext, ms) \
++ do { \
++ /*DBG_871X("%s set_link_timer(%p, %d)\n", __FUNCTION__, (mlmeext), (ms));*/ \
++ _set_timer(&(mlmeext)->link_timer, (ms)); \
++ } while(0)
++#ifdef CONFIG_IEEE80211W
++#define set_sa_query_timer(mlmeext, ms) \
++ do { \
++ DBG_871X("%s set_sa_query_timer(%p, %d)\n", __FUNCTION__, (mlmeext), (ms)); \
++ _set_timer(&(mlmeext)->sa_query_timer, (ms)); \
++ } while(0)
++#endif //CONFIG_IEEE80211W
++extern int cckrates_included(unsigned char *rate, int ratelen);
++extern int cckratesonly_included(unsigned char *rate, int ratelen);
++
++extern void process_addba_req(_adapter *padapter, u8 *paddba_req, u8 *addr);
++
++extern void update_TSF(struct mlme_ext_priv *pmlmeext, u8 *pframe, uint len);
++extern void correct_TSF(_adapter *padapter, struct mlme_ext_priv *pmlmeext);
++
++
++#ifdef CONFIG_CONCURRENT_MODE
++ sint check_buddy_mlmeinfo_state(_adapter *padapter, u32 state);
++void concurrent_chk_joinbss_done(_adapter *padapter, int join_res);
++#endif //CONFIG_CONCURRENT_MODE
++
++#ifdef CONFIG_DUALMAC_CONCURRENT
++void dc_SelectChannel(_adapter *padapter, unsigned char channel);
++void dc_SetBWMode(_adapter *padapter, unsigned short bwmode, unsigned char channel_offset);
++void dc_set_channel_bwmode_disconnect(_adapter *padapter);
++u8 dc_handle_join_request(_adapter *padapter);
++void dc_handle_join_done(_adapter *padapter, u8 join_res);
++sint dc_check_fwstate(_adapter *padapter, sint fw_state);
++u8 dc_handle_site_survey(_adapter *padapter);
++void dc_report_survey_event(_adapter *padapter, union recv_frame *precv_frame);
++void dc_set_channel_bwmode_survey_done(_adapter *padapter);
++void dc_set_ap_channel_bandwidth(_adapter *padapter, u8 channel, u8 channel_offset, u8 bwmode);
++void dc_resume_xmit(_adapter *padapter);
++u8 dc_check_xmit(_adapter *padapter);
++#endif
++
++int rtw_chk_start_clnt_join(_adapter *padapter);
++int rtw_get_ch_setting_union(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset);
++
++struct cmd_hdl {
++ uint parmsize;
++ u8 (*h2cfuns)(struct _ADAPTER *padapter, u8 *pbuf);
++};
++
++
++u8 read_macreg_hdl(_adapter *padapter, u8 *pbuf);
++u8 write_macreg_hdl(_adapter *padapter, u8 *pbuf);
++u8 read_bbreg_hdl(_adapter *padapter, u8 *pbuf);
++u8 write_bbreg_hdl(_adapter *padapter, u8 *pbuf);
++u8 read_rfreg_hdl(_adapter *padapter, u8 *pbuf);
++u8 write_rfreg_hdl(_adapter *padapter, u8 *pbuf);
++
++
++u8 NULL_hdl(_adapter *padapter, u8 *pbuf);
++u8 join_cmd_hdl(_adapter *padapter, u8 *pbuf);
++u8 disconnect_hdl(_adapter *padapter, u8 *pbuf);
++u8 createbss_hdl(_adapter *padapter, u8 *pbuf);
++u8 setopmode_hdl(_adapter *padapter, u8 *pbuf);
++u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf);
++u8 setauth_hdl(_adapter *padapter, u8 *pbuf);
++u8 setkey_hdl(_adapter *padapter, u8 *pbuf);
++u8 set_stakey_hdl(_adapter *padapter, u8 *pbuf);
++u8 set_assocsta_hdl(_adapter *padapter, u8 *pbuf);
++u8 del_assocsta_hdl(_adapter *padapter, u8 *pbuf);
++u8 add_ba_hdl(_adapter *padapter, unsigned char *pbuf);
++
++u8 mlme_evt_hdl(_adapter *padapter, unsigned char *pbuf);
++u8 h2c_msg_hdl(_adapter *padapter, unsigned char *pbuf);
++u8 tx_beacon_hdl(_adapter *padapter, unsigned char *pbuf);
++u8 set_ch_hdl(_adapter *padapter, u8 *pbuf);
++u8 set_chplan_hdl(_adapter *padapter, unsigned char *pbuf);
++u8 led_blink_hdl(_adapter *padapter, unsigned char *pbuf);
++u8 set_csa_hdl(_adapter *padapter, unsigned char *pbuf); //Kurt: Handling DFS channel switch announcement ie.
++u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf);
++
++
++#define GEN_DRV_CMD_HANDLER(size, cmd) {size, &cmd ## _hdl},
++#define GEN_MLME_EXT_HANDLER(size, cmd) {size, cmd},
++
++#ifdef _RTW_CMD_C_
++
++struct cmd_hdl wlancmds[] =
++{
++ GEN_DRV_CMD_HANDLER(0, NULL) /*0*/
++ GEN_DRV_CMD_HANDLER(0, NULL)
++ GEN_DRV_CMD_HANDLER(0, NULL)
++ GEN_DRV_CMD_HANDLER(0, NULL)
++ GEN_DRV_CMD_HANDLER(0, NULL)
++ GEN_DRV_CMD_HANDLER(0, NULL)
++ GEN_MLME_EXT_HANDLER(0, NULL)
++ GEN_MLME_EXT_HANDLER(0, NULL)
++ GEN_MLME_EXT_HANDLER(0, NULL)
++ GEN_MLME_EXT_HANDLER(0, NULL)
++ GEN_MLME_EXT_HANDLER(0, NULL) /*10*/
++ GEN_MLME_EXT_HANDLER(0, NULL)
++ GEN_MLME_EXT_HANDLER(0, NULL)
++ GEN_MLME_EXT_HANDLER(0, NULL)
++ GEN_MLME_EXT_HANDLER(sizeof (struct joinbss_parm), join_cmd_hdl) /*14*/
++ GEN_MLME_EXT_HANDLER(sizeof (struct disconnect_parm), disconnect_hdl)
++ GEN_MLME_EXT_HANDLER(sizeof (struct createbss_parm), createbss_hdl)
++ GEN_MLME_EXT_HANDLER(sizeof (struct setopmode_parm), setopmode_hdl)
++ GEN_MLME_EXT_HANDLER(sizeof (struct sitesurvey_parm), sitesurvey_cmd_hdl) /*18*/
++ GEN_MLME_EXT_HANDLER(sizeof (struct setauth_parm), setauth_hdl)
++ GEN_MLME_EXT_HANDLER(sizeof (struct setkey_parm), setkey_hdl) /*20*/
++ GEN_MLME_EXT_HANDLER(sizeof (struct set_stakey_parm), set_stakey_hdl)
++ GEN_MLME_EXT_HANDLER(sizeof (struct set_assocsta_parm), NULL)
++ GEN_MLME_EXT_HANDLER(sizeof (struct del_assocsta_parm), NULL)
++ GEN_MLME_EXT_HANDLER(sizeof (struct setstapwrstate_parm), NULL)
++ GEN_MLME_EXT_HANDLER(sizeof (struct setbasicrate_parm), NULL)
++ GEN_MLME_EXT_HANDLER(sizeof (struct getbasicrate_parm), NULL)
++ GEN_MLME_EXT_HANDLER(sizeof (struct setdatarate_parm), NULL)
++ GEN_MLME_EXT_HANDLER(sizeof (struct getdatarate_parm), NULL)
++ GEN_MLME_EXT_HANDLER(sizeof (struct setphyinfo_parm), NULL)
++ GEN_MLME_EXT_HANDLER(sizeof (struct getphyinfo_parm), NULL) /*30*/
++ GEN_MLME_EXT_HANDLER(sizeof (struct setphy_parm), NULL)
++ GEN_MLME_EXT_HANDLER(sizeof (struct getphy_parm), NULL)
++ GEN_MLME_EXT_HANDLER(0, NULL)
++ GEN_MLME_EXT_HANDLER(0, NULL)
++ GEN_MLME_EXT_HANDLER(0, NULL)
++ GEN_MLME_EXT_HANDLER(0, NULL)
++ GEN_MLME_EXT_HANDLER(0, NULL)
++ GEN_MLME_EXT_HANDLER(0, NULL)
++ GEN_MLME_EXT_HANDLER(0, NULL)
++ GEN_MLME_EXT_HANDLER(0, NULL) /*40*/
++ GEN_MLME_EXT_HANDLER(0, NULL)
++ GEN_MLME_EXT_HANDLER(0, NULL)
++ GEN_MLME_EXT_HANDLER(0, NULL)
++ GEN_MLME_EXT_HANDLER(0, NULL)
++ GEN_MLME_EXT_HANDLER(sizeof(struct addBaReq_parm), add_ba_hdl)
++ GEN_MLME_EXT_HANDLER(sizeof(struct set_ch_parm), set_ch_hdl) /* 46 */
++ GEN_MLME_EXT_HANDLER(0, NULL)
++ GEN_MLME_EXT_HANDLER(0, NULL)
++ GEN_MLME_EXT_HANDLER(0, NULL)
++ GEN_MLME_EXT_HANDLER(0, NULL) /*50*/
++ GEN_MLME_EXT_HANDLER(0, NULL)
++ GEN_MLME_EXT_HANDLER(0, NULL)
++ GEN_MLME_EXT_HANDLER(0, NULL)
++ GEN_MLME_EXT_HANDLER(0, NULL)
++ GEN_MLME_EXT_HANDLER(sizeof(struct Tx_Beacon_param), tx_beacon_hdl) /*55*/
++
++ GEN_MLME_EXT_HANDLER(0, mlme_evt_hdl) /*56*/
++ GEN_MLME_EXT_HANDLER(0, rtw_drvextra_cmd_hdl) /*57*/
++
++ GEN_MLME_EXT_HANDLER(0, h2c_msg_hdl) /*58*/
++ GEN_MLME_EXT_HANDLER(sizeof(struct SetChannelPlan_param), set_chplan_hdl) /*59*/
++ GEN_MLME_EXT_HANDLER(sizeof(struct LedBlink_param), led_blink_hdl) /*60*/
++ GEN_MLME_EXT_HANDLER(sizeof(struct SetChannelSwitch_param), set_csa_hdl) /*61*/
++ GEN_MLME_EXT_HANDLER(sizeof(struct TDLSoption_param), tdls_hdl) /*62*/
++};
++
++#endif
++
++struct C2HEvent_Header
++{
++
++#ifdef CONFIG_LITTLE_ENDIAN
++
++ unsigned int len:16;
++ unsigned int ID:8;
++ unsigned int seq:8;
++
++#elif defined(CONFIG_BIG_ENDIAN)
++
++ unsigned int seq:8;
++ unsigned int ID:8;
++ unsigned int len:16;
++
++#else
++
++# error "Must be LITTLE or BIG Endian"
++
++#endif
++
++ unsigned int rsvd;
++
++};
++
++void rtw_dummy_event_callback(_adapter *adapter , u8 *pbuf);
++void rtw_fwdbg_event_callback(_adapter *adapter , u8 *pbuf);
++
++enum rtw_c2h_event
++{
++ GEN_EVT_CODE(_Read_MACREG)=0, /*0*/
++ GEN_EVT_CODE(_Read_BBREG),
++ GEN_EVT_CODE(_Read_RFREG),
++ GEN_EVT_CODE(_Read_EEPROM),
++ GEN_EVT_CODE(_Read_EFUSE),
++ GEN_EVT_CODE(_Read_CAM), /*5*/
++ GEN_EVT_CODE(_Get_BasicRate),
++ GEN_EVT_CODE(_Get_DataRate),
++ GEN_EVT_CODE(_Survey), /*8*/
++ GEN_EVT_CODE(_SurveyDone), /*9*/
++
++ GEN_EVT_CODE(_JoinBss) , /*10*/
++ GEN_EVT_CODE(_AddSTA),
++ GEN_EVT_CODE(_DelSTA),
++ GEN_EVT_CODE(_AtimDone) ,
++ GEN_EVT_CODE(_TX_Report),
++ GEN_EVT_CODE(_CCX_Report), /*15*/
++ GEN_EVT_CODE(_DTM_Report),
++ GEN_EVT_CODE(_TX_Rate_Statistics),
++ GEN_EVT_CODE(_C2HLBK),
++ GEN_EVT_CODE(_FWDBG),
++ GEN_EVT_CODE(_C2HFEEDBACK), /*20*/
++ GEN_EVT_CODE(_ADDBA),
++ GEN_EVT_CODE(_C2HBCN),
++ GEN_EVT_CODE(_ReportPwrState), //filen: only for PCIE, USB
++ GEN_EVT_CODE(_CloseRF), //filen: only for PCIE, work around ASPM
++ MAX_C2HEVT
++};
++
++
++#ifdef _RTW_MLME_EXT_C_
++
++static struct fwevent wlanevents[] =
++{
++ {0, rtw_dummy_event_callback}, /*0*/
++ {0, NULL},
++ {0, NULL},
++ {0, NULL},
++ {0, NULL},
++ {0, NULL},
++ {0, NULL},
++ {0, NULL},
++ {0, &rtw_survey_event_callback}, /*8*/
++ {sizeof (struct surveydone_event), &rtw_surveydone_event_callback}, /*9*/
++
++ {0, &rtw_joinbss_event_callback}, /*10*/
++ {sizeof(struct stassoc_event), &rtw_stassoc_event_callback},
++ {sizeof(struct stadel_event), &rtw_stadel_event_callback},
++ {0, &rtw_atimdone_event_callback},
++ {0, rtw_dummy_event_callback},
++ {0, NULL}, /*15*/
++ {0, NULL},
++ {0, NULL},
++ {0, NULL},
++ {0, rtw_fwdbg_event_callback},
++ {0, NULL}, /*20*/
++ {0, NULL},
++ {0, NULL},
++ {0, &rtw_cpwm_event_callback},
++};
++
++#endif//_RTL8192C_CMD_C_
++
++#endif
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtw_mlme.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtw_mlme.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtw_mlme.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtw_mlme.h 2015-07-28 01:20:58.321597318 +0200
+@@ -0,0 +1,843 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef __RTW_MLME_H_
++#define __RTW_MLME_H_
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <mlme_osdep.h>
++#include <drv_types.h>
++#include <wlan_bssdef.h>
++
++#ifdef CONFIG_INTEL_WIDI
++#include <rtw_intel_widi.h>
++#endif
++
++#define MAX_BSS_CNT 128
++//#define MAX_JOIN_TIMEOUT 2000
++//#define MAX_JOIN_TIMEOUT 2500
++#define MAX_JOIN_TIMEOUT 6500
++
++// Commented by Albert 20101105
++// Increase the scanning timeout because of increasing the SURVEY_TO value.
++
++#define SCANNING_TIMEOUT 8000
++
++#define SCAN_INTERVAL (30) // unit:2sec, 30*2=60sec
++
++#ifdef PALTFORM_OS_WINCE
++#define SCANQUEUE_LIFETIME 12000000 // unit:us
++#else
++#define SCANQUEUE_LIFETIME 20 // unit:sec
++#endif
++
++#define WIFI_NULL_STATE 0x00000000
++
++#define WIFI_ASOC_STATE 0x00000001 // Under Linked state...
++#define WIFI_REASOC_STATE 0x00000002
++#define WIFI_SLEEP_STATE 0x00000004
++#define WIFI_STATION_STATE 0x00000008
++
++#define WIFI_AP_STATE 0x00000010
++#define WIFI_ADHOC_STATE 0x00000020
++#define WIFI_ADHOC_MASTER_STATE 0x00000040
++#define WIFI_UNDER_LINKING 0x00000080
++
++#define WIFI_UNDER_WPS 0x00000100
++//#define WIFI_UNDER_CMD 0x00000200
++//#define WIFI_UNDER_P2P 0x00000400
++#define WIFI_STA_ALIVE_CHK_STATE 0x00000400
++#define WIFI_SITE_MONITOR 0x00000800 //to indicate the station is under site surveying
++
++#ifdef WDS
++#define WIFI_WDS 0x00001000
++#define WIFI_WDS_RX_BEACON 0x00002000 // already rx WDS AP beacon
++#endif
++#ifdef AUTO_CONFIG
++#define WIFI_AUTOCONF 0x00004000
++#define WIFI_AUTOCONF_IND 0x00008000
++#endif
++
++/*
++// ========== P2P Section Start ===============
++#define WIFI_P2P_LISTEN_STATE 0x00010000
++#define WIFI_P2P_GROUP_FORMATION_STATE 0x00020000
++// ========== P2P Section End ===============
++*/
++
++//#ifdef UNDER_MPTEST
++#define WIFI_MP_STATE 0x00010000
++#define WIFI_MP_CTX_BACKGROUND 0x00020000 // in continous tx background
++#define WIFI_MP_CTX_ST 0x00040000 // in continous tx with single-tone
++#define WIFI_MP_CTX_BACKGROUND_PENDING 0x00080000 // pending in continous tx background due to out of skb
++#define WIFI_MP_CTX_CCK_HW 0x00100000 // in continous tx
++#define WIFI_MP_CTX_CCK_CS 0x00200000 // in continous tx with carrier suppression
++#define WIFI_MP_LPBK_STATE 0x00400000
++//#endif
++
++//#define _FW_UNDER_CMD WIFI_UNDER_CMD
++#define _FW_UNDER_LINKING WIFI_UNDER_LINKING
++#define _FW_LINKED WIFI_ASOC_STATE
++#define _FW_UNDER_SURVEY WIFI_SITE_MONITOR
++
++
++enum dot11AuthAlgrthmNum {
++ dot11AuthAlgrthm_Open = 0,
++ dot11AuthAlgrthm_Shared,
++ dot11AuthAlgrthm_8021X,
++ dot11AuthAlgrthm_Auto,
++ dot11AuthAlgrthm_MaxNum
++};
++
++// Scan type including active and passive scan.
++typedef enum _RT_SCAN_TYPE
++{
++ SCAN_PASSIVE,
++ SCAN_ACTIVE,
++ SCAN_MIX,
++}RT_SCAN_TYPE, *PRT_SCAN_TYPE;
++
++enum DriverInterface {
++ DRIVER_WEXT = 1,
++ DRIVER_CFG80211 = 2
++};
++
++enum _BAND
++{
++ GHZ24_50 = 0,
++ GHZ_50,
++ GHZ_24,
++ GHZ_MAX,
++};
++
++#define rtw_band_valid(band) ((band) >= GHZ24_50 && (band) < GHZ_MAX)
++
++enum SCAN_RESULT_TYPE
++{
++ SCAN_RESULT_P2P_ONLY = 0, // Will return all the P2P devices.
++ SCAN_RESULT_ALL = 1, // Will return all the scanned device, include AP.
++ SCAN_RESULT_WFD_TYPE = 2 // Will just return the correct WFD device.
++ // If this device is Miracast sink device, it will just return all the Miracast source devices.
++};
++
++/*
++
++there are several "locks" in mlme_priv,
++since mlme_priv is a shared resource between many threads,
++like ISR/Call-Back functions, the OID handlers, and even timer functions.
++
++
++Each _queue has its own locks, already.
++Other items are protected by mlme_priv.lock.
++
++To avoid possible dead lock, any thread trying to modifiying mlme_priv
++SHALL not lock up more than one locks at a time!
++
++*/
++
++
++#define traffic_threshold 10
++#define traffic_scan_period 500
++
++struct sitesurvey_ctrl {
++ u64 last_tx_pkts;
++ uint last_rx_pkts;
++ sint traffic_busy;
++ _timer sitesurvey_ctrl_timer;
++};
++
++typedef struct _RT_LINK_DETECT_T{
++ u32 NumTxOkInPeriod;
++ u32 NumRxOkInPeriod;
++ u32 NumRxUnicastOkInPeriod;
++ BOOLEAN bBusyTraffic;
++ BOOLEAN bTxBusyTraffic;
++ BOOLEAN bRxBusyTraffic;
++ BOOLEAN bHigherBusyTraffic; // For interrupt migration purpose.
++ BOOLEAN bHigherBusyRxTraffic; // We may disable Tx interrupt according as Rx traffic.
++ BOOLEAN bHigherBusyTxTraffic; // We may disable Tx interrupt according as Tx traffic.
++}RT_LINK_DETECT_T, *PRT_LINK_DETECT_T;
++
++struct profile_info {
++ u8 ssidlen;
++ u8 ssid[ WLAN_SSID_MAXLEN ];
++ u8 peermac[ ETH_ALEN ];
++};
++
++struct tx_invite_req_info{
++ u8 token;
++ u8 benable;
++ u8 go_ssid[ WLAN_SSID_MAXLEN ];
++ u8 ssidlen;
++ u8 go_bssid[ ETH_ALEN ];
++ u8 peer_macaddr[ ETH_ALEN ];
++ u8 operating_ch; // This information will be set by using the p2p_set op_ch=x
++ u8 peer_ch; // The listen channel for peer P2P device
++
++};
++
++struct tx_invite_resp_info{
++ u8 token; // Used to record the dialog token of p2p invitation request frame.
++};
++
++#ifdef CONFIG_WFD
++
++struct wifi_display_info{
++ u16 wfd_enable; // Eanble/Disable the WFD function.
++ u16 rtsp_ctrlport; // TCP port number at which the this WFD device listens for RTSP messages
++ u16 peer_rtsp_ctrlport; // TCP port number at which the peer WFD device listens for RTSP messages
++ // This filed should be filled when receiving the gropu negotiation request
++
++ u8 peer_session_avail; // WFD session is available or not for the peer wfd device.
++ // This variable will be set when sending the provisioning discovery request to peer WFD device.
++ // And this variable will be reset when it is read by using the iwpriv p2p_get wfd_sa command.
++
++ u8 ip_address[4];
++ u8 peer_ip_address[4];
++ u8 wfd_pc; // WFD preferred connection
++ // 0 -> Prefer to use the P2P for WFD connection on peer side.
++ // 1 -> Prefer to use the TDLS for WFD connection on peer side.
++
++ u8 wfd_device_type; // WFD Device Type
++ // 0 -> WFD Source Device
++ // 1 -> WFD Primary Sink Device
++ enum SCAN_RESULT_TYPE scan_result_type; // Used when P2P is enable. This parameter will impact the scan result.
++};
++#endif //CONFIG_WFD
++
++struct tx_provdisc_req_info{
++ u16 wps_config_method_request; // Used when sending the provisioning request frame
++ u16 peer_channel_num[2]; // The channel number which the receiver stands.
++ NDIS_802_11_SSID ssid;
++ u8 peerDevAddr[ ETH_ALEN ]; // Peer device address
++ u8 peerIFAddr[ ETH_ALEN ]; // Peer interface address
++ u8 benable; // This provision discovery request frame is trigger to send or not
++};
++
++struct rx_provdisc_req_info{ //When peer device issue prov_disc_req first, we should store the following informations
++ u8 peerDevAddr[ ETH_ALEN ]; // Peer device address
++ u8 strconfig_method_desc_of_prov_disc_req[4]; // description for the config method located in the provisioning discovery request frame.
++ // The UI must know this information to know which config method the remote p2p device is requiring.
++};
++
++struct tx_nego_req_info{
++ u16 peer_channel_num[2]; // The channel number which the receiver stands.
++ u8 peerDevAddr[ ETH_ALEN ]; // Peer device address
++ u8 benable; // This negoitation request frame is trigger to send or not
++};
++
++struct group_id_info{
++ u8 go_device_addr[ ETH_ALEN ]; // The GO's device address of this P2P group
++ u8 ssid[ WLAN_SSID_MAXLEN ]; // The SSID of this P2P group
++};
++
++struct scan_limit_info{
++ u8 scan_op_ch_only; // When this flag is set, the driver should just scan the operation channel
++#ifndef P2P_OP_CHECK_SOCIAL_CH
++ u8 operation_ch[2]; // Store the operation channel of invitation request frame
++#else
++ u8 operation_ch[5]; // Store additional channel 1,6,11 for Android 4.2 IOT & Nexus 4
++#endif //P2P_OP_CHECK_SOCIAL_CH
++};
++
++#ifdef CONFIG_IOCTL_CFG80211
++struct cfg80211_wifidirect_info{
++ _timer remain_on_ch_timer;
++ u8 restore_channel;
++ struct ieee80211_channel remain_on_ch_channel;
++ enum nl80211_channel_type remain_on_ch_type;
++ u64 remain_on_ch_cookie;
++ bool is_ro_ch;
++};
++#endif //CONFIG_IOCTL_CFG80211
++
++struct wifidirect_info{
++ _adapter* padapter;
++ _timer find_phase_timer;
++ _timer restore_p2p_state_timer;
++
++ // Used to do the scanning. After confirming the peer is availalble, the driver transmits the P2P frame to peer.
++ _timer pre_tx_scan_timer;
++ _timer reset_ch_sitesurvey;
++ _timer reset_ch_sitesurvey2; // Just for resetting the scan limit function by using p2p nego
++#ifdef CONFIG_CONCURRENT_MODE
++ // Used to switch the channel between legacy AP and listen state.
++ _timer ap_p2p_switch_timer;
++#endif
++ struct tx_provdisc_req_info tx_prov_disc_info;
++ struct rx_provdisc_req_info rx_prov_disc_info;
++ struct tx_invite_req_info invitereq_info;
++ struct profile_info profileinfo[ P2P_MAX_PERSISTENT_GROUP_NUM ]; // Store the profile information of persistent group
++ struct tx_invite_resp_info inviteresp_info;
++ struct tx_nego_req_info nego_req_info;
++ struct group_id_info groupid_info; // Store the group id information when doing the group negotiation handshake.
++ struct scan_limit_info rx_invitereq_info; // Used for get the limit scan channel from the Invitation procedure
++ struct scan_limit_info p2p_info; // Used for get the limit scan channel from the P2P negotiation handshake
++#ifdef CONFIG_WFD
++ struct wifi_display_info *wfd_info;
++#endif
++ enum P2P_ROLE role;
++ enum P2P_STATE pre_p2p_state;
++ enum P2P_STATE p2p_state;
++ u8 device_addr[ETH_ALEN]; // The device address should be the mac address of this device.
++ u8 interface_addr[ETH_ALEN];
++ u8 social_chan[4];
++ u8 listen_channel;
++ u8 operating_channel;
++ u8 listen_dwell; // This value should be between 1 and 3
++ u8 support_rate[8];
++ u8 p2p_wildcard_ssid[P2P_WILDCARD_SSID_LEN];
++ u8 intent; // should only include the intent value.
++ u8 p2p_peer_interface_addr[ ETH_ALEN ];
++ u8 p2p_peer_device_addr[ ETH_ALEN ];
++ u8 peer_intent; // Included the intent value and tie breaker value.
++ u8 device_name[ WPS_MAX_DEVICE_NAME_LEN ]; // Device name for displaying on searching device screen
++ u8 device_name_len;
++ u8 profileindex; // Used to point to the index of profileinfo array
++ u8 peer_operating_ch;
++ u8 find_phase_state_exchange_cnt;
++ u16 device_password_id_for_nego; // The device password ID for group negotation
++ u8 negotiation_dialog_token;
++ u8 nego_ssid[ WLAN_SSID_MAXLEN ]; // SSID information for group negotitation
++ u8 nego_ssidlen;
++ u8 p2p_group_ssid[WLAN_SSID_MAXLEN];
++ u8 p2p_group_ssid_len;
++ u8 persistent_supported; // Flag to know the persistent function should be supported or not.
++ // In the Sigma test, the Sigma will provide this enable from the sta_set_p2p CAPI.
++ // 0: disable
++ // 1: enable
++ u8 session_available; // Flag to set the WFD session available to enable or disable "by Sigma"
++ // In the Sigma test, the Sigma will disable the session available by using the sta_preset CAPI.
++ // 0: disable
++ // 1: enable
++ u8 wfd_tdls_enable; // Flag to enable or disable the TDLS by WFD Sigma
++ // 0: disable
++ // 1: enable
++ u8 wfd_tdls_weaksec; // Flag to enable or disable the weak security function for TDLS by WFD Sigma
++ // 0: disable
++ // In this case, the driver can't issue the tdsl setup request frame.
++ // 1: enable
++ // In this case, the driver can issue the tdls setup request frame
++ // even the current security is weak security.
++
++ enum P2P_WPSINFO ui_got_wps_info; // This field will store the WPS value (PIN value or PBC) that UI had got from the user.
++ u16 supported_wps_cm; // This field describes the WPS config method which this driver supported.
++ // The value should be the combination of config method defined in page104 of WPS v2.0 spec.
++ u8 external_uuid; // UUID flag
++ u8 uuid[16]; // UUID
++ uint channel_list_attr_len; // This field will contain the length of body of P2P Channel List attribute of group negotitation response frame.
++ u8 channel_list_attr[100]; // This field will contain the body of P2P Channel List attribute of group negotitation response frame.
++ // We will use the channel_cnt and channel_list fields when constructing the group negotitation confirm frame.
++ u8 driver_interface; // Indicate DRIVER_WEXT or DRIVER_CFG80211
++
++#ifdef CONFIG_CONCURRENT_MODE
++ u16 ext_listen_interval; // The interval to be available with legacy AP (ms)
++ u16 ext_listen_period; // The time period to be available for P2P listen state (ms)
++#endif
++#ifdef CONFIG_P2P_PS
++ enum P2P_PS_MODE p2p_ps_mode; // indicate p2p ps mode
++ enum P2P_PS_STATE p2p_ps_state; // indicate p2p ps state
++ u8 noa_index; // Identifies and instance of Notice of Absence timing.
++ u8 ctwindow; // Client traffic window. A period of time in TU after TBTT.
++ u8 opp_ps; // opportunistic power save.
++ u8 noa_num; // number of NoA descriptor in P2P IE.
++ u8 noa_count[P2P_MAX_NOA_NUM]; // Count for owner, Type of client.
++ u32 noa_duration[P2P_MAX_NOA_NUM]; // Max duration for owner, preferred or min acceptable duration for client.
++ u32 noa_interval[P2P_MAX_NOA_NUM]; // Length of interval for owner, preferred or max acceptable interval of client.
++ u32 noa_start_time[P2P_MAX_NOA_NUM]; // schedule expressed in terms of the lower 4 bytes of the TSF timer.
++#endif // CONFIG_P2P_PS
++};
++
++struct tdls_ss_record{ //signal strength record; recording the tdls sta with lowerest ss
++ u8 macaddr[ETH_ALEN];
++ u8 RxPWDBAll;
++ u8 is_tdls_sta; // _TRUE: direct link sta, _FALSE: else
++};
++
++struct tdls_info{
++ u8 ap_prohibited;
++ uint setup_state;
++ u8 sta_cnt;
++ u8 sta_maximum; // 1:tdls sta is equal (NUM_STA-1), reach max direct link number; 0: else;
++ struct tdls_ss_record ss_record;
++ u8 macid_index; //macid entry that is ready to write
++ u8 clear_cam; //cam entry that is trying to clear, using it in direct link teardown
++ u8 ch_sensing;
++ u8 cur_channel;
++ u8 candidate_ch;
++ u8 collect_pkt_num[MAX_CHANNEL_NUM];
++ _lock cmd_lock;
++ _lock hdl_lock;
++ u8 watchdog_count;
++ u8 dev_discovered; //WFD_TDLS: for sigma test
++ u8 enable;
++#ifdef CONFIG_WFD
++ struct wifi_display_info *wfd_info;
++#endif
++};
++
++struct mlme_priv {
++
++ _lock lock;
++ sint fw_state; //shall we protect this variable? maybe not necessarily...
++
++ u8 to_join; //flag
++ #ifdef CONFIG_LAYER2_ROAMING
++ u8 to_roaming; // roaming trying times
++ #endif
++
++ u8 *nic_hdl;
++
++ u8 not_indic_disco;
++ _list *pscanned;
++ _queue free_bss_pool;
++ _queue scanned_queue;
++ u8 *free_bss_buf;
++ u32 num_of_scanned;
++
++ NDIS_802_11_SSID assoc_ssid;
++ u8 assoc_bssid[6];
++
++ struct wlan_network cur_network;
++
++ //uint wireless_mode; no used, remove it
++
++ u32 scan_interval;
++
++ _timer assoc_timer;
++
++ uint assoc_by_bssid;
++ uint assoc_by_rssi;
++
++ _timer scan_to_timer; // driver itself handles scan_timeout status.
++ u32 scan_start_time; // used to evaluate the time spent in scanning
++
++ #ifdef CONFIG_SET_SCAN_DENY_TIMER
++ _timer set_scan_deny_timer;
++ ATOMIC_T set_scan_deny; //0: allowed, 1: deny
++ #endif
++
++ struct qos_priv qospriv;
++
++#ifdef CONFIG_80211N_HT
++
++ /* Number of non-HT AP/stations */
++ int num_sta_no_ht;
++
++ /* Number of HT AP/stations 20 MHz */
++ //int num_sta_ht_20mhz;
++
++
++ int num_FortyMHzIntolerant;
++
++ struct ht_priv htpriv;
++
++#endif
++
++ RT_LINK_DETECT_T LinkDetectInfo;
++ _timer dynamic_chk_timer; //dynamic/periodic check timer
++
++ u8 acm_mask; // for wmm acm mask
++ u8 ChannelPlan;
++ RT_SCAN_TYPE scan_mode; // active: 1, passive: 0
++
++ //u8 probereq_wpsie[MAX_WPS_IE_LEN];//added in probe req
++ //int probereq_wpsie_len;
++ u8 *wps_probe_req_ie;
++ u32 wps_probe_req_ie_len;
++
++#if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME)
++ /* Number of associated Non-ERP stations (i.e., stations using 802.11b
++ * in 802.11g BSS) */
++ int num_sta_non_erp;
++
++ /* Number of associated stations that do not support Short Slot Time */
++ int num_sta_no_short_slot_time;
++
++ /* Number of associated stations that do not support Short Preamble */
++ int num_sta_no_short_preamble;
++
++ int olbc; /* Overlapping Legacy BSS Condition */
++
++ /* Number of HT associated stations that do not support greenfield */
++ int num_sta_ht_no_gf;
++
++ /* Number of associated non-HT stations */
++ //int num_sta_no_ht;
++
++ /* Number of HT associated stations 20 MHz */
++ int num_sta_ht_20mhz;
++
++ /* Overlapping BSS information */
++ int olbc_ht;
++
++#ifdef CONFIG_80211N_HT
++ u16 ht_op_mode;
++#endif /* CONFIG_80211N_HT */
++
++ u8 *assoc_req;
++ u32 assoc_req_len;
++ u8 *assoc_rsp;
++ u32 assoc_rsp_len;
++
++ u8 *wps_beacon_ie;
++ //u8 *wps_probe_req_ie;
++ u8 *wps_probe_resp_ie;
++ u8 *wps_assoc_resp_ie; // for CONFIG_IOCTL_CFG80211, this IE could include p2p ie / wfd ie
++
++ u32 wps_beacon_ie_len;
++ //u32 wps_probe_req_ie_len;
++ u32 wps_probe_resp_ie_len;
++ u32 wps_assoc_resp_ie_len; // for CONFIG_IOCTL_CFG80211, this IE len could include p2p ie / wfd ie
++
++ u8 *p2p_beacon_ie;
++ u8 *p2p_probe_req_ie;
++ u8 *p2p_probe_resp_ie;
++ u8 *p2p_go_probe_resp_ie; //for GO
++ u8 *p2p_assoc_req_ie;
++
++ u32 p2p_beacon_ie_len;
++ u32 p2p_probe_req_ie_len;
++ u32 p2p_probe_resp_ie_len;
++ u32 p2p_go_probe_resp_ie_len; //for GO
++ u32 p2p_assoc_req_ie_len;
++/*
++#if defined(CONFIG_P2P) && defined(CONFIG_IOCTL_CFG80211)
++ //u8 *wps_p2p_beacon_ie;
++ u8 *p2p_beacon_ie;
++ u8 *wps_p2p_probe_resp_ie;
++ u8 *wps_p2p_assoc_resp_ie;
++ //u32 wps_p2p_beacon_ie_len;
++ u32 p2p_beacon_ie_len;
++ u32 wps_p2p_probe_resp_ie_len;
++ u32 wps_p2p_assoc_resp_ie_len;
++#endif
++*/
++
++ _lock bcn_update_lock;
++ u8 update_bcn;
++
++
++#endif //#if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME)
++
++#if defined(CONFIG_WFD) && defined(CONFIG_IOCTL_CFG80211)
++
++ u8 *wfd_beacon_ie;
++ u8 *wfd_probe_req_ie;
++ u8 *wfd_probe_resp_ie;
++ u8 *wfd_go_probe_resp_ie; //for GO
++ u8 *wfd_assoc_req_ie;
++
++ u32 wfd_beacon_ie_len;
++ u32 wfd_probe_req_ie_len;
++ u32 wfd_probe_resp_ie_len;
++ u32 wfd_go_probe_resp_ie_len; //for GO
++ u32 wfd_assoc_req_ie_len;
++
++#endif
++
++#ifdef RTK_DMP_PLATFORM
++ // DMP kobject_hotplug function signal need in passive level
++ _workitem Linkup_workitem;
++ _workitem Linkdown_workitem;
++#endif
++
++#ifdef CONFIG_INTEL_WIDI
++ int widi_state;
++ int listen_state;
++ _timer listen_timer;
++ ATOMIC_T rx_probe_rsp; // 1:receive probe respone from RDS source.
++ u8 *l2sdTaBuffer;
++ u8 channel_idx;
++ s8 group_cnt; //For WiDi 3.5, they specified another scan algo. for WFD/RDS co-existed
++ u8 sa_ext[L2SDTA_SERVICE_VE_LEN];
++
++ u8 widi_enable;
++ /**
++ * For WiDi 4; upper layer would set
++ * p2p_primary_device_type_category_id
++ * p2p_primary_device_type_sub_category_id
++ * p2p_secondary_device_type_category_id
++ * p2p_secondary_device_type_sub_category_id
++ */
++ u16 p2p_pdt_cid;
++ u16 p2p_pdt_scid;
++ u8 num_p2p_sdt;
++ u16 p2p_sdt_cid[MAX_NUM_P2P_SDT];
++ u16 p2p_sdt_scid[MAX_NUM_P2P_SDT];
++ u8 p2p_reject_disable; //When starting NL80211 wpa_supplicant/hostapd, it will call netdev_close
++ //such that it will cause p2p disabled. Use this flag to reject.
++#endif // CONFIG_INTEL_WIDI
++
++#ifdef CONFIG_CONCURRENT_MODE
++ u8 scanning_via_buddy_intf;
++#endif
++};
++
++#ifdef CONFIG_AP_MODE
++
++struct hostapd_priv
++{
++ _adapter *padapter;
++
++#ifdef CONFIG_HOSTAPD_MLME
++ struct net_device *pmgnt_netdev;
++ struct usb_anchor anchored;
++#endif
++
++};
++
++extern int hostapd_mode_init(_adapter *padapter);
++extern void hostapd_mode_unload(_adapter *padapter);
++#endif
++
++
++extern void rtw_joinbss_event_prehandle(_adapter *adapter, u8 *pbuf);
++extern void rtw_survey_event_callback(_adapter *adapter, u8 *pbuf);
++extern void rtw_surveydone_event_callback(_adapter *adapter, u8 *pbuf);
++extern void rtw_joinbss_event_callback(_adapter *adapter, u8 *pbuf);
++extern void rtw_stassoc_event_callback(_adapter *adapter, u8 *pbuf);
++extern void rtw_stadel_event_callback(_adapter *adapter, u8 *pbuf);
++extern void rtw_atimdone_event_callback(_adapter *adapter, u8 *pbuf);
++extern void rtw_cpwm_event_callback(_adapter *adapter, u8 *pbuf);
++
++#ifdef PLATFORM_WINDOWS
++extern thread_return event_thread(void *context);
++
++extern void rtw_join_timeout_handler (
++ IN PVOID SystemSpecific1,
++ IN PVOID FunctionContext,
++ IN PVOID SystemSpecific2,
++ IN PVOID SystemSpecific3
++ );
++
++extern void _rtw_scan_timeout_handler (
++ IN PVOID SystemSpecific1,
++ IN PVOID FunctionContext,
++ IN PVOID SystemSpecific2,
++ IN PVOID SystemSpecific3
++ );
++
++#endif
++
++#if defined (PLATFORM_LINUX)|| defined (PLATFORM_FREEBSD)
++extern int event_thread(void *context);
++extern void rtw_join_timeout_handler(void* FunctionContext);
++extern void _rtw_scan_timeout_handler(void* FunctionContext);
++#endif
++
++extern void rtw_free_network_queue(_adapter *adapter,u8 isfreeall);
++extern int rtw_init_mlme_priv(_adapter *adapter);// (struct mlme_priv *pmlmepriv);
++
++extern void rtw_free_mlme_priv (struct mlme_priv *pmlmepriv);
++
++
++extern sint rtw_select_and_join_from_scanned_queue(struct mlme_priv *pmlmepriv);
++extern sint rtw_set_key(_adapter *adapter,struct security_priv *psecuritypriv,sint keyid, u8 set_tx);
++extern sint rtw_set_auth(_adapter *adapter,struct security_priv *psecuritypriv);
++
++__inline static u8 *get_bssid(struct mlme_priv *pmlmepriv)
++{ //if sta_mode:pmlmepriv->cur_network.network.MacAddress=> bssid
++ // if adhoc_mode:pmlmepriv->cur_network.network.MacAddress=> ibss mac address
++ return pmlmepriv->cur_network.network.MacAddress;
++}
++
++__inline static sint check_fwstate(struct mlme_priv *pmlmepriv, sint state)
++{
++ if (pmlmepriv->fw_state & state)
++ return _TRUE;
++
++ return _FALSE;
++}
++
++__inline static sint get_fwstate(struct mlme_priv *pmlmepriv)
++{
++ return pmlmepriv->fw_state;
++}
++
++/*
++ * No Limit on the calling context,
++ * therefore set it to be the critical section...
++ *
++ * ### NOTE:#### (!!!!)
++ * MUST TAKE CARE THAT BEFORE CALLING THIS FUNC, YOU SHOULD HAVE LOCKED pmlmepriv->lock
++ */
++__inline static void set_fwstate(struct mlme_priv *pmlmepriv, sint state)
++{
++ pmlmepriv->fw_state |= state;
++}
++
++__inline static void _clr_fwstate_(struct mlme_priv *pmlmepriv, sint state)
++{
++ pmlmepriv->fw_state &= ~state;
++}
++
++/*
++ * No Limit on the calling context,
++ * therefore set it to be the critical section...
++ */
++__inline static void clr_fwstate(struct mlme_priv *pmlmepriv, sint state)
++{
++ _irqL irqL;
++
++ _enter_critical_bh(&pmlmepriv->lock, &irqL);
++ if (check_fwstate(pmlmepriv, state) == _TRUE)
++ pmlmepriv->fw_state ^= state;
++ _exit_critical_bh(&pmlmepriv->lock, &irqL);
++}
++
++__inline static void clr_fwstate_ex(struct mlme_priv *pmlmepriv, sint state)
++{
++ _irqL irqL;
++
++ _enter_critical_bh(&pmlmepriv->lock, &irqL);
++ _clr_fwstate_(pmlmepriv, state);
++ _exit_critical_bh(&pmlmepriv->lock, &irqL);
++}
++
++__inline static void up_scanned_network(struct mlme_priv *pmlmepriv)
++{
++ _irqL irqL;
++
++ _enter_critical_bh(&pmlmepriv->lock, &irqL);
++ pmlmepriv->num_of_scanned++;
++ _exit_critical_bh(&pmlmepriv->lock, &irqL);
++}
++
++#ifdef CONFIG_CONCURRENT_MODE
++sint rtw_buddy_adapter_up(_adapter *padapter);
++sint check_buddy_fwstate(_adapter *padapter, sint state);
++#endif //CONFIG_CONCURRENT_MODE
++
++__inline static void down_scanned_network(struct mlme_priv *pmlmepriv)
++{
++ _irqL irqL;
++
++ _enter_critical_bh(&pmlmepriv->lock, &irqL);
++ pmlmepriv->num_of_scanned--;
++ _exit_critical_bh(&pmlmepriv->lock, &irqL);
++}
++
++__inline static void set_scanned_network_val(struct mlme_priv *pmlmepriv, sint val)
++{
++ _irqL irqL;
++
++ _enter_critical_bh(&pmlmepriv->lock, &irqL);
++ pmlmepriv->num_of_scanned = val;
++ _exit_critical_bh(&pmlmepriv->lock, &irqL);
++}
++
++extern u16 rtw_get_capability(WLAN_BSSID_EX *bss);
++extern void rtw_update_scanned_network(_adapter *adapter, WLAN_BSSID_EX *target);
++extern void rtw_disconnect_hdl_under_linked(_adapter* adapter, struct sta_info *psta, u8 free_assoc);
++extern void rtw_generate_random_ibss(u8 *pibss);
++extern struct wlan_network* rtw_find_network(_queue *scanned_queue, u8 *addr);
++extern struct wlan_network* rtw_get_oldest_wlan_network(_queue *scanned_queue);
++
++extern void rtw_free_assoc_resources(_adapter* adapter, int lock_scanned_queue);
++extern void rtw_indicate_disconnect(_adapter* adapter);
++extern void rtw_indicate_connect(_adapter* adapter);
++void rtw_indicate_scan_done( _adapter *padapter, bool aborted);
++void rtw_scan_abort(_adapter *adapter);
++
++extern int rtw_restruct_sec_ie(_adapter *adapter,u8 *in_ie,u8 *out_ie,uint in_len);
++extern int rtw_restruct_wmm_ie(_adapter *adapter, u8 *in_ie, u8 *out_ie, uint in_len, uint initial_out_len);
++extern void rtw_init_registrypriv_dev_network(_adapter *adapter);
++
++extern void rtw_update_registrypriv_dev_network(_adapter *adapter);
++
++extern void rtw_get_encrypt_decrypt_from_registrypriv(_adapter *adapter);
++
++extern void _rtw_join_timeout_handler(_adapter *adapter);
++extern void rtw_scan_timeout_handler(_adapter *adapter);
++
++extern void rtw_dynamic_check_timer_handlder(_adapter *adapter);
++#ifdef CONFIG_SET_SCAN_DENY_TIMER
++bool rtw_is_scan_deny(_adapter *adapter);
++void rtw_clear_scan_deny(_adapter *adapter);
++void rtw_set_scan_deny_timer_hdl(_adapter *adapter);
++void rtw_set_scan_deny(_adapter *adapter, u32 ms);
++#else
++#define rtw_is_scan_deny(adapter) _FALSE
++#define rtw_clear_scan_deny(adapter) do {} while (0)
++#define rtw_set_scan_deny_timer_hdl(adapter) do {} while (0)
++#define rtw_set_scan_deny(adapter, ms) do {} while (0)
++#endif
++
++
++extern int _rtw_init_mlme_priv(_adapter *padapter);
++
++void rtw_free_mlme_priv_ie_data(struct mlme_priv *pmlmepriv);
++
++extern void _rtw_free_mlme_priv(struct mlme_priv *pmlmepriv);
++
++extern int _rtw_enqueue_network(_queue *queue, struct wlan_network *pnetwork);
++
++extern struct wlan_network* _rtw_dequeue_network(_queue *queue);
++
++extern struct wlan_network* _rtw_alloc_network(struct mlme_priv *pmlmepriv);
++
++
++extern void _rtw_free_network(struct mlme_priv *pmlmepriv, struct wlan_network *pnetwork, u8 isfreeall);
++extern void _rtw_free_network_nolock(struct mlme_priv *pmlmepriv, struct wlan_network *pnetwork);
++
++
++extern struct wlan_network* _rtw_find_network(_queue *scanned_queue, u8 *addr);
++
++extern void _rtw_free_network_queue(_adapter* padapter, u8 isfreeall);
++
++extern sint rtw_if_up(_adapter *padapter);
++
++
++u8 *rtw_get_capability_from_ie(u8 *ie);
++u8 *rtw_get_timestampe_from_ie(u8 *ie);
++u8 *rtw_get_beacon_interval_from_ie(u8 *ie);
++
++
++void rtw_joinbss_reset(_adapter *padapter);
++
++#ifdef CONFIG_80211N_HT
++unsigned int rtw_restructure_ht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, uint in_len, uint *pout_len, u8 channel);
++void rtw_update_ht_cap(_adapter *padapter, u8 *pie, uint ie_len, u8 channel);
++void rtw_issue_addbareq_cmd(_adapter *padapter, struct xmit_frame *pxmitframe);
++#endif
++
++int rtw_is_same_ibss(_adapter *adapter, struct wlan_network *pnetwork);
++int is_same_network(WLAN_BSSID_EX *src, WLAN_BSSID_EX *dst);
++
++#ifdef CONFIG_LAYER2_ROAMING
++void _rtw_roaming(_adapter *adapter, struct wlan_network *tgt_network);
++void rtw_roaming(_adapter *adapter, struct wlan_network *tgt_network);
++void rtw_set_roaming(_adapter *adapter, u8 to_roaming);
++u8 rtw_to_roaming(_adapter *adapter);
++#else
++#define _rtw_roaming(adapter, tgt_network) do {} while(0)
++#define rtw_roaming(adapter, tgt_network) do {} while(0)
++#define rtw_set_roaming(adapter, to_roaming) do {} while(0)
++#define rtw_to_roaming(adapter) 0
++#endif
++
++
++#ifdef CONFIG_INTEL_PROXIM
++void rtw_proxim_enable(_adapter *padapter);
++void rtw_proxim_disable(_adapter *padapter);
++void rtw_proxim_send_packet(_adapter *padapter,u8 *pbuf,u16 len,u8 hw_rate);
++#endif //CONFIG_INTEL_PROXIM
++#endif //__RTL871X_MLME_H_
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtw_mp.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtw_mp.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtw_mp.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtw_mp.h 2015-07-28 01:20:58.321597318 +0200
+@@ -0,0 +1,711 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef _RTW_MP_H_
++#define _RTW_MP_H_
++
++#ifndef PLATFORM_WINDOWS
++// 00 - Success
++// 11 - Error
++#define STATUS_SUCCESS (0x00000000L)
++#define STATUS_PENDING (0x00000103L)
++
++#define STATUS_UNSUCCESSFUL (0xC0000001L)
++#define STATUS_INSUFFICIENT_RESOURCES (0xC000009AL)
++#define STATUS_NOT_SUPPORTED (0xC00000BBL)
++
++#define NDIS_STATUS_SUCCESS ((NDIS_STATUS)STATUS_SUCCESS)
++#define NDIS_STATUS_PENDING ((NDIS_STATUS)STATUS_PENDING)
++#define NDIS_STATUS_NOT_RECOGNIZED ((NDIS_STATUS)0x00010001L)
++#define NDIS_STATUS_NOT_COPIED ((NDIS_STATUS)0x00010002L)
++#define NDIS_STATUS_NOT_ACCEPTED ((NDIS_STATUS)0x00010003L)
++#define NDIS_STATUS_CALL_ACTIVE ((NDIS_STATUS)0x00010007L)
++
++#define NDIS_STATUS_FAILURE ((NDIS_STATUS)STATUS_UNSUCCESSFUL)
++#define NDIS_STATUS_RESOURCES ((NDIS_STATUS)STATUS_INSUFFICIENT_RESOURCES)
++#define NDIS_STATUS_CLOSING ((NDIS_STATUS)0xC0010002L)
++#define NDIS_STATUS_BAD_VERSION ((NDIS_STATUS)0xC0010004L)
++#define NDIS_STATUS_BAD_CHARACTERISTICS ((NDIS_STATUS)0xC0010005L)
++#define NDIS_STATUS_ADAPTER_NOT_FOUND ((NDIS_STATUS)0xC0010006L)
++#define NDIS_STATUS_OPEN_FAILED ((NDIS_STATUS)0xC0010007L)
++#define NDIS_STATUS_DEVICE_FAILED ((NDIS_STATUS)0xC0010008L)
++#define NDIS_STATUS_MULTICAST_FULL ((NDIS_STATUS)0xC0010009L)
++#define NDIS_STATUS_MULTICAST_EXISTS ((NDIS_STATUS)0xC001000AL)
++#define NDIS_STATUS_MULTICAST_NOT_FOUND ((NDIS_STATUS)0xC001000BL)
++#define NDIS_STATUS_REQUEST_ABORTED ((NDIS_STATUS)0xC001000CL)
++#define NDIS_STATUS_RESET_IN_PROGRESS ((NDIS_STATUS)0xC001000DL)
++#define NDIS_STATUS_CLOSING_INDICATING ((NDIS_STATUS)0xC001000EL)
++#define NDIS_STATUS_NOT_SUPPORTED ((NDIS_STATUS)STATUS_NOT_SUPPORTED)
++#define NDIS_STATUS_INVALID_PACKET ((NDIS_STATUS)0xC001000FL)
++#define NDIS_STATUS_OPEN_LIST_FULL ((NDIS_STATUS)0xC0010010L)
++#define NDIS_STATUS_ADAPTER_NOT_READY ((NDIS_STATUS)0xC0010011L)
++#define NDIS_STATUS_ADAPTER_NOT_OPEN ((NDIS_STATUS)0xC0010012L)
++#define NDIS_STATUS_NOT_INDICATING ((NDIS_STATUS)0xC0010013L)
++#define NDIS_STATUS_INVALID_LENGTH ((NDIS_STATUS)0xC0010014L)
++#define NDIS_STATUS_INVALID_DATA ((NDIS_STATUS)0xC0010015L)
++#define NDIS_STATUS_BUFFER_TOO_SHORT ((NDIS_STATUS)0xC0010016L)
++#define NDIS_STATUS_INVALID_OID ((NDIS_STATUS)0xC0010017L)
++#define NDIS_STATUS_ADAPTER_REMOVED ((NDIS_STATUS)0xC0010018L)
++#define NDIS_STATUS_UNSUPPORTED_MEDIA ((NDIS_STATUS)0xC0010019L)
++#define NDIS_STATUS_GROUP_ADDRESS_IN_USE ((NDIS_STATUS)0xC001001AL)
++#define NDIS_STATUS_FILE_NOT_FOUND ((NDIS_STATUS)0xC001001BL)
++#define NDIS_STATUS_ERROR_READING_FILE ((NDIS_STATUS)0xC001001CL)
++#define NDIS_STATUS_ALREADY_MAPPED ((NDIS_STATUS)0xC001001DL)
++#define NDIS_STATUS_RESOURCE_CONFLICT ((NDIS_STATUS)0xC001001EL)
++#define NDIS_STATUS_NO_CABLE ((NDIS_STATUS)0xC001001FL)
++
++#define NDIS_STATUS_INVALID_SAP ((NDIS_STATUS)0xC0010020L)
++#define NDIS_STATUS_SAP_IN_USE ((NDIS_STATUS)0xC0010021L)
++#define NDIS_STATUS_INVALID_ADDRESS ((NDIS_STATUS)0xC0010022L)
++#define NDIS_STATUS_VC_NOT_ACTIVATED ((NDIS_STATUS)0xC0010023L)
++#define NDIS_STATUS_DEST_OUT_OF_ORDER ((NDIS_STATUS)0xC0010024L) // cause 27
++#define NDIS_STATUS_VC_NOT_AVAILABLE ((NDIS_STATUS)0xC0010025L) // cause 35,45
++#define NDIS_STATUS_CELLRATE_NOT_AVAILABLE ((NDIS_STATUS)0xC0010026L) // cause 37
++#define NDIS_STATUS_INCOMPATABLE_QOS ((NDIS_STATUS)0xC0010027L) // cause 49
++#define NDIS_STATUS_AAL_PARAMS_UNSUPPORTED ((NDIS_STATUS)0xC0010028L) // cause 93
++#define NDIS_STATUS_NO_ROUTE_TO_DESTINATION ((NDIS_STATUS)0xC0010029L) // cause 3
++#endif /* #ifndef PLATFORM_WINDOWS */
++
++#if 0
++#define MPT_NOOP 0
++#define MPT_READ_MAC_1BYTE 1
++#define MPT_READ_MAC_2BYTE 2
++#define MPT_READ_MAC_4BYTE 3
++#define MPT_WRITE_MAC_1BYTE 4
++#define MPT_WRITE_MAC_2BYTE 5
++#define MPT_WRITE_MAC_4BYTE 6
++#define MPT_READ_BB_CCK 7
++#define MPT_WRITE_BB_CCK 8
++#define MPT_READ_BB_OFDM 9
++#define MPT_WRITE_BB_OFDM 10
++#define MPT_READ_RF 11
++#define MPT_WRITE_RF 12
++#define MPT_READ_EEPROM_1BYTE 13
++#define MPT_WRITE_EEPROM_1BYTE 14
++#define MPT_READ_EEPROM_2BYTE 15
++#define MPT_WRITE_EEPROM_2BYTE 16
++#define MPT_SET_CSTHRESHOLD 21
++#define MPT_SET_INITGAIN 22
++#define MPT_SWITCH_BAND 23
++#define MPT_SWITCH_CHANNEL 24
++#define MPT_SET_DATARATE 25
++#define MPT_SWITCH_ANTENNA 26
++#define MPT_SET_TX_POWER 27
++#define MPT_SET_CONT_TX 28
++#define MPT_SET_SINGLE_CARRIER 29
++#define MPT_SET_CARRIER_SUPPRESSION 30
++#define MPT_GET_RATE_TABLE 31
++#define MPT_READ_TSSI 32
++#define MPT_GET_THERMAL_METER 33
++#endif
++
++#define MAX_MP_XMITBUF_SZ 2048
++#define NR_MP_XMITFRAME 8
++
++struct mp_xmit_frame
++{
++ _list list;
++
++ struct pkt_attrib attrib;
++
++ _pkt *pkt;
++
++ int frame_tag;
++
++ _adapter *padapter;
++
++#ifdef CONFIG_USB_HCI
++
++ //insert urb, irp, and irpcnt info below...
++ //max frag_cnt = 8
++
++ u8 *mem_addr;
++ u32 sz[8];
++
++#if defined(PLATFORM_OS_XP) || defined(PLATFORM_LINUX)
++ PURB pxmit_urb[8];
++#endif
++
++#ifdef PLATFORM_OS_XP
++ PIRP pxmit_irp[8];
++#endif
++
++ u8 bpending[8];
++ sint ac_tag[8];
++ sint last[8];
++ uint irpcnt;
++ uint fragcnt;
++#endif /* CONFIG_USB_HCI */
++
++ uint mem[(MAX_MP_XMITBUF_SZ >> 2)];
++};
++
++struct mp_wiparam
++{
++ u32 bcompleted;
++ u32 act_type;
++ u32 io_offset;
++ u32 io_value;
++};
++
++typedef void(*wi_act_func)(void* padapter);
++
++#ifdef PLATFORM_WINDOWS
++struct mp_wi_cntx
++{
++ u8 bmpdrv_unload;
++
++ // Work Item
++ NDIS_WORK_ITEM mp_wi;
++ NDIS_EVENT mp_wi_evt;
++ _lock mp_wi_lock;
++ u8 bmp_wi_progress;
++ wi_act_func curractfunc;
++ // Variable needed in each implementation of CurrActFunc.
++ struct mp_wiparam param;
++};
++#endif
++
++struct mp_tx
++{
++ u8 stop;
++ u32 count, sended;
++ u8 payload;
++ struct pkt_attrib attrib;
++ struct tx_desc desc;
++ u8 *pallocated_buf;
++ u8 *buf;
++ u32 buf_size, write_size;
++ _thread_hdl_ PktTxThread;
++};
++
++//#if (MP_DRIVER == 1)
++#if defined(CONFIG_RTL8192C) || defined(CONFIG_RTL8192D) || defined(CONFIG_RTL8723A) || defined(CONFIG_RTL8188E)
++#ifdef CONFIG_RTL8192C
++#include <Hal8192CPhyCfg.h>
++#endif
++#ifdef CONFIG_RTL8192D
++#include <Hal8192DPhyCfg.h>
++#endif
++#ifdef CONFIG_RTL8723A
++#include <Hal8723APhyCfg.h>
++#endif
++#ifdef CONFIG_RTL8188E
++#include <rtl8188e_hal.h>
++#endif
++#define MP_MAX_LINES 1000
++#define MP_MAX_LINES_BYTES 256
++#define u1Byte u8
++#define s1Byte s8
++#define u4Byte u32
++#define s4Byte s32
++typedef VOID (*MPT_WORK_ITEM_HANDLER)(IN PVOID Adapter);
++typedef struct _MPT_CONTEXT
++{
++ // Indicate if we have started Mass Production Test.
++ BOOLEAN bMassProdTest;
++
++ // Indicate if the driver is unloading or unloaded.
++ BOOLEAN bMptDrvUnload;
++
++ /* 8190 PCI does not support NDIS_WORK_ITEM. */
++ // Work Item for Mass Production Test.
++ //NDIS_WORK_ITEM MptWorkItem;
++// RT_WORK_ITEM MptWorkItem;
++ // Event used to sync the case unloading driver and MptWorkItem is still in progress.
++// NDIS_EVENT MptWorkItemEvent;
++ // To protect the following variables.
++// NDIS_SPIN_LOCK MptWorkItemSpinLock;
++ // Indicate a MptWorkItem is scheduled and not yet finished.
++ BOOLEAN bMptWorkItemInProgress;
++ // An instance which implements function and context of MptWorkItem.
++ MPT_WORK_ITEM_HANDLER CurrMptAct;
++
++ // 1=Start, 0=Stop from UI.
++ ULONG MptTestStart;
++ // _TEST_MODE, defined in MPT_Req2.h
++ ULONG MptTestItem;
++ // Variable needed in each implementation of CurrMptAct.
++ ULONG MptActType; // Type of action performed in CurrMptAct.
++ // The Offset of IO operation is depend of MptActType.
++ ULONG MptIoOffset;
++ // The Value of IO operation is depend of MptActType.
++ ULONG MptIoValue;
++ // The RfPath of IO operation is depend of MptActType.
++ ULONG MptRfPath;
++
++ WIRELESS_MODE MptWirelessModeToSw; // Wireless mode to switch.
++ u8 MptChannelToSw; // Channel to switch.
++ u8 MptInitGainToSet; // Initial gain to set.
++ //ULONG bMptAntennaA; // TRUE if we want to use antenna A.
++ ULONG MptBandWidth; // bandwidth to switch.
++ ULONG MptRateIndex; // rate index.
++ // Register value kept for Single Carrier Tx test.
++ u8 btMpCckTxPower;
++ // Register value kept for Single Carrier Tx test.
++ u8 btMpOfdmTxPower;
++ // For MP Tx Power index
++ u8 TxPwrLevel[2]; // rf-A, rf-B
++
++ // Content of RCR Regsiter for Mass Production Test.
++ ULONG MptRCR;
++ // TRUE if we only receive packets with specific pattern.
++ BOOLEAN bMptFilterPattern;
++ // Rx OK count, statistics used in Mass Production Test.
++ ULONG MptRxOkCnt;
++ // Rx CRC32 error count, statistics used in Mass Production Test.
++ ULONG MptRxCrcErrCnt;
++
++ BOOLEAN bCckContTx; // TRUE if we are in CCK Continuous Tx test.
++ BOOLEAN bOfdmContTx; // TRUE if we are in OFDM Continuous Tx test.
++ BOOLEAN bStartContTx; // TRUE if we have start Continuous Tx test.
++ // TRUE if we are in Single Carrier Tx test.
++ BOOLEAN bSingleCarrier;
++ // TRUE if we are in Carrier Suppression Tx Test.
++ BOOLEAN bCarrierSuppression;
++ //TRUE if we are in Single Tone Tx test.
++ BOOLEAN bSingleTone;
++
++ // ACK counter asked by K.Y..
++ BOOLEAN bMptEnableAckCounter;
++ ULONG MptAckCounter;
++
++ // SD3 Willis For 8192S to save 1T/2T RF table for ACUT Only fro ACUT delete later ~~~!
++ //s1Byte BufOfLines[2][MAX_LINES_HWCONFIG_TXT][MAX_BYTES_LINE_HWCONFIG_TXT];
++ //s1Byte BufOfLines[2][MP_MAX_LINES][MP_MAX_LINES_BYTES];
++ //s4Byte RfReadLine[2];
++
++ u8 APK_bound[2]; //for APK path A/path B
++ BOOLEAN bMptIndexEven;
++
++ u8 backup0xc50;
++ u8 backup0xc58;
++ u8 backup0xc30;
++}MPT_CONTEXT, *PMPT_CONTEXT;
++#endif
++//#endif
++
++/* E-Fuse */
++#ifdef CONFIG_RTL8192D
++#define EFUSE_MAP_SIZE 255
++#endif
++#ifdef CONFIG_RTL8192C
++#define EFUSE_MAP_SIZE 128
++#endif
++#ifdef CONFIG_RTL8723A
++#define EFUSE_MAP_SIZE 256
++#endif
++#ifdef CONFIG_RTL8188E
++#define EFUSE_MAP_SIZE 256
++#endif
++#define EFUSE_MAX_SIZE 512
++
++/* end of E-Fuse */
++
++//#define RTPRIV_IOCTL_MP ( SIOCIWFIRSTPRIV + 0x17)
++enum {
++ WRITE_REG = 1,
++ READ_REG,
++ WRITE_RF,
++ READ_RF,
++ MP_START,
++ MP_STOP,
++ MP_RATE,
++ MP_CHANNEL,
++ MP_BANDWIDTH,
++ MP_TXPOWER,
++ MP_ANT_TX,
++ MP_ANT_RX,
++ MP_CTX,
++ MP_QUERY,
++ MP_ARX,
++ MP_PSD,
++ MP_PWRTRK,
++ MP_THER,
++ MP_IOCTL,
++ EFUSE_GET,
++ EFUSE_SET,
++ MP_RESET_STATS,
++ MP_DUMP,
++ MP_PHYPARA,
++ MP_NULL,
++};
++
++struct mp_priv
++{
++ _adapter *papdater;
++
++ //Testing Flag
++ u32 mode;//0 for normal type packet, 1 for loopback packet (16bytes TXCMD)
++
++ u32 prev_fw_state;
++
++ //OID cmd handler
++ struct mp_wiparam workparam;
++// u8 act_in_progress;
++
++ //Tx Section
++ u8 TID;
++ u32 tx_pktcount;
++ struct mp_tx tx;
++
++ //Rx Section
++ u32 rx_pktcount;
++ u32 rx_crcerrpktcount;
++ u32 rx_pktloss;
++
++ struct recv_stat rxstat;
++
++ //RF/BB relative
++ u8 channel;
++ u8 bandwidth;
++ u8 prime_channel_offset;
++ u8 txpoweridx;
++ u8 txpoweridx_b;
++ u8 rateidx;
++ u32 preamble;
++// u8 modem;
++ u32 CrystalCap;
++// u32 curr_crystalcap;
++
++ u16 antenna_tx;
++ u16 antenna_rx;
++// u8 curr_rfpath;
++
++ u8 check_mp_pkt;
++
++// uint ForcedDataRate;
++
++ struct wlan_network mp_network;
++ NDIS_802_11_MAC_ADDRESS network_macaddr;
++
++#ifdef PLATFORM_WINDOWS
++ u32 rx_testcnt;
++ u32 rx_testcnt1;
++ u32 rx_testcnt2;
++ u32 tx_testcnt;
++ u32 tx_testcnt1;
++
++ struct mp_wi_cntx wi_cntx;
++
++ u8 h2c_result;
++ u8 h2c_seqnum;
++ u16 h2c_cmdcode;
++ u8 h2c_resp_parambuf[512];
++ _lock h2c_lock;
++ _lock wkitm_lock;
++ u32 h2c_cmdcnt;
++ NDIS_EVENT h2c_cmd_evt;
++ NDIS_EVENT c2h_set;
++ NDIS_EVENT h2c_clr;
++ NDIS_EVENT cpwm_int;
++
++ NDIS_EVENT scsir_full_evt;
++ NDIS_EVENT scsiw_empty_evt;
++#endif
++
++ u8 *pallocated_mp_xmitframe_buf;
++ u8 *pmp_xmtframe_buf;
++ _queue free_mp_xmitqueue;
++ u32 free_mp_xmitframe_cnt;
++
++ MPT_CONTEXT MptCtx;
++};
++
++typedef struct _IOCMD_STRUCT_ {
++ u8 cmdclass;
++ u16 value;
++ u8 index;
++}IOCMD_STRUCT;
++
++struct rf_reg_param {
++ u32 path;
++ u32 offset;
++ u32 value;
++};
++
++struct bb_reg_param {
++ u32 offset;
++ u32 value;
++};
++//=======================================================================
++
++#define LOWER _TRUE
++#define RAISE _FALSE
++
++/* Hardware Registers */
++#if 0
++#if 0
++#define IOCMD_CTRL_REG 0x102502C0
++#define IOCMD_DATA_REG 0x102502C4
++#else
++#define IOCMD_CTRL_REG 0x10250370
++#define IOCMD_DATA_REG 0x10250374
++#endif
++
++#define IOCMD_GET_THERMAL_METER 0xFD000028
++
++#define IOCMD_CLASS_BB_RF 0xF0
++#define IOCMD_BB_READ_IDX 0x00
++#define IOCMD_BB_WRITE_IDX 0x01
++#define IOCMD_RF_READ_IDX 0x02
++#define IOCMD_RF_WRIT_IDX 0x03
++#endif
++#define BB_REG_BASE_ADDR 0x800
++
++/* MP variables */
++#if 0
++#define _2MAC_MODE_ 0
++#define _LOOPBOOK_MODE_ 1
++#endif
++typedef enum _MP_MODE_ {
++ MP_OFF,
++ MP_ON,
++ MP_ERR,
++ MP_CONTINUOUS_TX,
++ MP_SINGLE_CARRIER_TX,
++ MP_CARRIER_SUPPRISSION_TX,
++ MP_SINGLE_TONE_TX,
++ MP_PACKET_TX,
++ MP_PACKET_RX
++} MP_MODE;
++
++#ifdef CONFIG_RTL8192C
++#define RF_PATH_A RF_PATH_A
++#define RF_PATH_B RF_PATH_B
++#define RF_PATH_C RF_PATH_C
++#define RF_PATH_D RF_PATH_D
++
++#define MAX_RF_PATH_NUMS RF_PATH_MAX
++#else
++#define RF_PATH_A 0
++#define RF_PATH_B 1
++#define RF_PATH_C 2
++#define RF_PATH_D 3
++
++#define MAX_RF_PATH_NUMS 2
++#endif
++
++extern u8 mpdatarate[NumRates];
++
++/* MP set force data rate base on the definition. */
++typedef enum _MPT_RATE_INDEX
++{
++ /* CCK rate. */
++ MPT_RATE_1M, /* 0 */
++ MPT_RATE_2M,
++ MPT_RATE_55M,
++ MPT_RATE_11M, /* 3 */
++
++ /* OFDM rate. */
++ MPT_RATE_6M, /* 4 */
++ MPT_RATE_9M,
++ MPT_RATE_12M,
++ MPT_RATE_18M,
++ MPT_RATE_24M,
++ MPT_RATE_36M,
++ MPT_RATE_48M,
++ MPT_RATE_54M, /* 11 */
++
++ /* HT rate. */
++ MPT_RATE_MCS0, /* 12 */
++ MPT_RATE_MCS1,
++ MPT_RATE_MCS2,
++ MPT_RATE_MCS3,
++ MPT_RATE_MCS4,
++ MPT_RATE_MCS5,
++ MPT_RATE_MCS6,
++ MPT_RATE_MCS7, /* 19 */
++ MPT_RATE_MCS8,
++ MPT_RATE_MCS9,
++ MPT_RATE_MCS10,
++ MPT_RATE_MCS11,
++ MPT_RATE_MCS12,
++ MPT_RATE_MCS13,
++ MPT_RATE_MCS14,
++ MPT_RATE_MCS15, /* 27 */
++ MPT_RATE_LAST
++}MPT_RATE_E, *PMPT_RATE_E;
++
++#if 0
++// Represent Channel Width in HT Capabilities
++typedef enum _HT_CHANNEL_WIDTH {
++ HT_CHANNEL_WIDTH_20 = 0,
++ HT_CHANNEL_WIDTH_40 = 1,
++}HT_CHANNEL_WIDTH, *PHT_CHANNEL_WIDTH;
++#endif
++
++#define MAX_TX_PWR_INDEX_N_MODE 64 // 0x3F
++
++typedef enum _POWER_MODE_ {
++ POWER_LOW = 0,
++ POWER_NORMAL
++}POWER_MODE;
++
++
++#define RX_PKT_BROADCAST 1
++#define RX_PKT_DEST_ADDR 2
++#define RX_PKT_PHY_MATCH 3
++
++#if 0
++#define RPTMaxCount 0x000FFFFF;
++
++// parameter 1 : BitMask
++// bit 0 : OFDM PPDU
++// bit 1 : OFDM False Alarm
++// bit 2 : OFDM MPDU OK
++// bit 3 : OFDM MPDU Fail
++// bit 4 : CCK PPDU
++// bit 5 : CCK False Alarm
++// bit 6 : CCK MPDU ok
++// bit 7 : CCK MPDU fail
++// bit 8 : HT PPDU counter
++// bit 9 : HT false alarm
++// bit 10 : HT MPDU total
++// bit 11 : HT MPDU OK
++// bit 12 : HT MPDU fail
++// bit 15 : RX full drop
++typedef enum _RXPHY_BITMASK_
++{
++ OFDM_PPDU_BIT = 0,
++ OFDM_FALSE_BIT,
++ OFDM_MPDU_OK_BIT,
++ OFDM_MPDU_FAIL_BIT,
++ CCK_PPDU_BIT,
++ CCK_FALSE_BIT,
++ CCK_MPDU_OK_BIT,
++ CCK_MPDU_FAIL_BIT,
++ HT_PPDU_BIT,
++ HT_FALSE_BIT,
++ HT_MPDU_BIT,
++ HT_MPDU_OK_BIT,
++ HT_MPDU_FAIL_BIT,
++} RXPHY_BITMASK;
++#endif
++
++typedef enum _ENCRY_CTRL_STATE_ {
++ HW_CONTROL, //hw encryption& decryption
++ SW_CONTROL, //sw encryption& decryption
++ HW_ENCRY_SW_DECRY, //hw encryption & sw decryption
++ SW_ENCRY_HW_DECRY //sw encryption & hw decryption
++}ENCRY_CTRL_STATE;
++
++typedef enum _OFDM_TX_MODE {
++ OFDM_ALL_OFF = 0,
++ OFDM_ContinuousTx = 1,
++ OFDM_SingleCarrier = 2,
++ OFDM_SingleTone = 4,
++} OFDM_TX_MODE;
++
++//=======================================================================
++//extern struct mp_xmit_frame *alloc_mp_xmitframe(struct mp_priv *pmp_priv);
++//extern int free_mp_xmitframe(struct xmit_priv *pxmitpriv, struct mp_xmit_frame *pmp_xmitframe);
++
++extern s32 init_mp_priv(PADAPTER padapter);
++extern void free_mp_priv(struct mp_priv *pmp_priv);
++extern s32 MPT_InitializeAdapter(PADAPTER padapter, u8 Channel);
++extern void MPT_DeInitAdapter(PADAPTER padapter);
++extern s32 mp_start_test(PADAPTER padapter);
++extern void mp_stop_test(PADAPTER padapter);
++
++//=======================================================================
++//extern void IQCalibrateBcut(PADAPTER pAdapter);
++
++//extern u32 bb_reg_read(PADAPTER Adapter, u16 offset);
++//extern u8 bb_reg_write(PADAPTER Adapter, u16 offset, u32 value);
++//extern u32 rf_reg_read(PADAPTER Adapter, u8 path, u8 offset);
++//extern u8 rf_reg_write(PADAPTER Adapter, u8 path, u8 offset, u32 value);
++
++//extern u32 get_bb_reg(PADAPTER Adapter, u16 offset, u32 bitmask);
++//extern u8 set_bb_reg(PADAPTER Adapter, u16 offset, u32 bitmask, u32 value);
++//extern u32 get_rf_reg(PADAPTER Adapter, u8 path, u8 offset, u32 bitmask);
++//extern u8 set_rf_reg(PADAPTER Adapter, u8 path, u8 offset, u32 bitmask, u32 value);
++
++extern u32 _read_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 bitmask);
++extern void _write_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 bitmask, u32 val);
++
++extern u32 read_macreg(_adapter *padapter, u32 addr, u32 sz);
++extern void write_macreg(_adapter *padapter, u32 addr, u32 val, u32 sz);
++extern u32 read_bbreg(_adapter *padapter, u32 addr, u32 bitmask);
++extern void write_bbreg(_adapter *padapter, u32 addr, u32 bitmask, u32 val);
++extern u32 read_rfreg(PADAPTER padapter, u8 rfpath, u32 addr);
++extern void write_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 val);
++
++extern void SetChannel(PADAPTER pAdapter);
++extern void SetBandwidth(PADAPTER pAdapter);
++extern void SetTxPower(PADAPTER pAdapter);
++extern void SetAntennaPathPower(PADAPTER pAdapter);
++//extern void SetTxAGCOffset(PADAPTER pAdapter, u32 ulTxAGCOffset);
++extern void SetDataRate(PADAPTER pAdapter);
++
++extern void SetAntenna(PADAPTER pAdapter);
++
++//extern void SetCrystalCap(PADAPTER pAdapter);
++
++extern s32 SetThermalMeter(PADAPTER pAdapter, u8 target_ther);
++extern void GetThermalMeter(PADAPTER pAdapter, u8 *value);
++
++extern void SetContinuousTx(PADAPTER pAdapter, u8 bStart);
++extern void SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart);
++extern void SetSingleToneTx(PADAPTER pAdapter, u8 bStart);
++extern void SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart);
++
++extern void fill_txdesc_for_mp(PADAPTER padapter, struct tx_desc *ptxdesc);
++extern void SetPacketTx(PADAPTER padapter);
++extern void SetPacketRx(PADAPTER pAdapter, u8 bStartRx);
++
++extern void ResetPhyRxPktCount(PADAPTER pAdapter);
++extern u32 GetPhyRxPktReceived(PADAPTER pAdapter);
++extern u32 GetPhyRxPktCRC32Error(PADAPTER pAdapter);
++
++extern s32 SetPowerTracking(PADAPTER padapter, u8 enable);
++extern void GetPowerTracking(PADAPTER padapter, u8 *enable);
++
++extern u32 mp_query_psd(PADAPTER pAdapter, u8 *data);
++
++
++extern void Hal_SetAntenna(PADAPTER pAdapter);
++extern void Hal_SetBandwidth(PADAPTER pAdapter);
++
++extern void Hal_SetTxPower(PADAPTER pAdapter);
++extern void Hal_SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart);
++extern void Hal_SetSingleToneTx ( PADAPTER pAdapter , u8 bStart );
++extern void Hal_SetSingleCarrierTx (PADAPTER pAdapter, u8 bStart);
++extern void Hal_SetContinuousTx (PADAPTER pAdapter, u8 bStart);
++extern void Hal_SetBandwidth(PADAPTER pAdapter);
++
++extern void Hal_SetDataRate(PADAPTER pAdapter);
++extern void Hal_SetChannel(PADAPTER pAdapter);
++extern void Hal_SetAntennaPathPower(PADAPTER pAdapter);
++extern s32 Hal_SetThermalMeter(PADAPTER pAdapter, u8 target_ther);
++extern s32 Hal_SetPowerTracking(PADAPTER padapter, u8 enable);
++extern void Hal_GetPowerTracking(PADAPTER padapter, u8 * enable);
++extern void Hal_GetThermalMeter(PADAPTER pAdapter, u8 *value);
++extern void Hal_mpt_SwitchRfSetting(PADAPTER pAdapter);
++extern void Hal_MPT_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14);
++extern void Hal_MPT_CCKTxPowerAdjustbyIndex(PADAPTER pAdapter, BOOLEAN beven);
++extern void Hal_SetCCKTxPower(PADAPTER pAdapter, u8 * TxPower);
++extern void Hal_SetOFDMTxPower(PADAPTER pAdapter, u8 * TxPower);
++extern void Hal_TriggerRFThermalMeter(PADAPTER pAdapter);
++extern u8 Hal_ReadRFThermalMeter(PADAPTER pAdapter);
++extern void Hal_SetCCKContinuousTx(PADAPTER pAdapter, u8 bStart);
++extern void Hal_SetOFDMContinuousTx(PADAPTER pAdapter, u8 bStart);
++extern void Hal_ProSetCrystalCap (PADAPTER pAdapter , u32 CrystalCapVal);
++
++#endif //_RTW_MP_H_
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtw_mp_ioctl.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtw_mp_ioctl.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtw_mp_ioctl.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtw_mp_ioctl.h 2015-07-28 01:20:58.321597318 +0200
+@@ -0,0 +1,595 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef _RTW_MP_IOCTL_H_
++#define _RTW_MP_IOCTL_H_
++
++//#include <drv_conf.h>
++//#include <osdep_service.h>
++#include <drv_types.h>
++#include <mp_custom_oid.h>
++#include <rtw_ioctl.h>
++#include <rtw_ioctl_rtl.h>
++#include <rtw_efuse.h>
++#include <rtw_mp.h>
++
++#if 0
++#define TESTFWCMDNUMBER 1000000
++#define TEST_H2CINT_WAIT_TIME 500
++#define TEST_C2HINT_WAIT_TIME 500
++#define HCI_TEST_SYSCFG_HWMASK 1
++#define _BUSCLK_40M (4 << 2)
++#endif
++//------------------------------------------------------------------------------
++typedef struct CFG_DBG_MSG_STRUCT {
++ u32 DebugLevel;
++ u32 DebugComponent_H32;
++ u32 DebugComponent_L32;
++}CFG_DBG_MSG_STRUCT,*PCFG_DBG_MSG_STRUCT;
++
++typedef struct _RW_REG {
++ u32 offset;
++ u32 width;
++ u32 value;
++}mp_rw_reg,RW_Reg, *pRW_Reg;
++
++//for OID_RT_PRO_READ16_EEPROM & OID_RT_PRO_WRITE16_EEPROM
++typedef struct _EEPROM_RW_PARAM {
++ u32 offset;
++ u16 value;
++}eeprom_rw_param,EEPROM_RWParam, *pEEPROM_RWParam;
++
++typedef struct _EFUSE_ACCESS_STRUCT_ {
++ u16 start_addr;
++ u16 cnts;
++ u8 data[0];
++}EFUSE_ACCESS_STRUCT, *PEFUSE_ACCESS_STRUCT;
++
++typedef struct _BURST_RW_REG {
++ u32 offset;
++ u32 len;
++ u8 Data[256];
++}burst_rw_reg,Burst_RW_Reg, *pBurst_RW_Reg;
++
++typedef struct _USB_VendorReq{
++ u8 bRequest;
++ u16 wValue;
++ u16 wIndex;
++ u16 wLength;
++ u8 u8Dir;//0:OUT, 1:IN
++ u8 u8InData;
++}usb_vendor_req, USB_VendorReq, *pUSB_VendorReq;
++
++typedef struct _DR_VARIABLE_STRUCT_ {
++ u8 offset;
++ u32 variable;
++}DR_VARIABLE_STRUCT;
++
++//int mp_start_joinbss(_adapter *padapter, NDIS_802_11_SSID *pssid);
++
++//void _irqlevel_changed_(_irqL *irqlevel, /*BOOLEAN*/unsigned char bLower);
++#ifdef PLATFORM_OS_XP
++static void _irqlevel_changed_(_irqL *irqlevel, u8 bLower)
++{
++
++ if (bLower == LOWER) {
++ *irqlevel = KeGetCurrentIrql();
++
++ if (*irqlevel > PASSIVE_LEVEL) {
++ KeLowerIrql(PASSIVE_LEVEL);
++ }
++ } else {
++ if (KeGetCurrentIrql() == PASSIVE_LEVEL) {
++ KeRaiseIrql(DISPATCH_LEVEL, irqlevel);
++ }
++ }
++
++}
++#else
++#define _irqlevel_changed_(a,b)
++#endif
++
++//oid_rtl_seg_81_80_00
++NDIS_STATUS oid_rt_pro_set_data_rate_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_pro_start_test_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_pro_stop_test_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_pro_set_channel_direct_call_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_pro_set_antenna_bb_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_pro_set_tx_power_control_hdl(struct oid_par_priv* poid_par_priv);
++//oid_rtl_seg_81_80_20
++NDIS_STATUS oid_rt_pro_query_tx_packet_sent_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_pro_query_rx_packet_received_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_pro_query_rx_packet_crc32_error_hdl(struct oid_par_priv* poid_par_priv);
++
++NDIS_STATUS oid_rt_pro_reset_tx_packet_sent_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_pro_reset_rx_packet_received_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_pro_set_modulation_hdl(struct oid_par_priv* poid_par_priv);
++
++NDIS_STATUS oid_rt_pro_set_continuous_tx_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_pro_set_single_carrier_tx_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_pro_set_carrier_suppression_tx_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_pro_set_single_tone_tx_hdl(struct oid_par_priv* poid_par_priv);
++
++
++//oid_rtl_seg_81_87
++NDIS_STATUS oid_rt_pro_write_bb_reg_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_pro_read_bb_reg_hdl(struct oid_par_priv* poid_par_priv);
++
++NDIS_STATUS oid_rt_pro_write_rf_reg_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_pro_read_rf_reg_hdl(struct oid_par_priv* poid_par_priv);
++
++
++//oid_rtl_seg_81_85
++NDIS_STATUS oid_rt_wireless_mode_hdl(struct oid_par_priv* poid_par_priv);
++
++
++// oid_rtl_seg_87_11_00
++NDIS_STATUS oid_rt_pro8711_join_bss_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_pro_read_register_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_pro_write_register_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_pro_burst_read_register_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_pro_burst_write_register_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_pro_write_txcmd_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_pro_read16_eeprom_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_pro_write16_eeprom_hdl (struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_pro8711_wi_poll_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_pro8711_pkt_loss_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_rd_attrib_mem_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_wr_attrib_mem_hdl (struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_pro_set_rf_intfs_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_poll_rx_status_hdl(struct oid_par_priv* poid_par_priv);
++// oid_rtl_seg_87_11_20
++NDIS_STATUS oid_rt_pro_cfg_debug_message_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_pro_set_data_rate_ex_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_pro_set_basic_rate_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_pro_read_tssi_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_pro_set_power_tracking_hdl(struct oid_par_priv* poid_par_priv);
++//oid_rtl_seg_87_11_50
++NDIS_STATUS oid_rt_pro_qry_pwrstate_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_pro_set_pwrstate_hdl(struct oid_par_priv* poid_par_priv);
++//oid_rtl_seg_87_11_F0
++NDIS_STATUS oid_rt_pro_h2c_set_rate_table_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_pro_h2c_get_rate_table_hdl(struct oid_par_priv* poid_par_priv);
++
++
++//oid_rtl_seg_87_12_00
++NDIS_STATUS oid_rt_pro_encryption_ctrl_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_pro_add_sta_info_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_pro_dele_sta_info_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_pro_query_dr_variable_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_pro_rx_packet_type_hdl(struct oid_par_priv* poid_par_priv);
++
++NDIS_STATUS oid_rt_pro_read_efuse_hdl(struct oid_par_priv *poid_par_priv);
++NDIS_STATUS oid_rt_pro_write_efuse_hdl(struct oid_par_priv *poid_par_priv);
++NDIS_STATUS oid_rt_pro_rw_efuse_pgpkt_hdl(struct oid_par_priv *poid_par_priv);
++NDIS_STATUS oid_rt_get_efuse_current_size_hdl(struct oid_par_priv *poid_par_priv);
++NDIS_STATUS oid_rt_pro_efuse_hdl(struct oid_par_priv *poid_par_priv);
++NDIS_STATUS oid_rt_pro_efuse_map_hdl(struct oid_par_priv *poid_par_priv);
++
++NDIS_STATUS oid_rt_set_bandwidth_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_set_crystal_cap_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_set_rx_packet_type_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_get_efuse_max_size_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_pro_set_tx_agc_offset_hdl(struct oid_par_priv* poid_par_priv);
++
++NDIS_STATUS oid_rt_pro_set_pkt_test_mode_hdl(struct oid_par_priv* poid_par_priv);
++
++NDIS_STATUS oid_rt_get_thermal_meter_hdl(struct oid_par_priv* poid_par_priv);
++
++NDIS_STATUS oid_rt_reset_phy_rx_packet_count_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_get_phy_rx_packet_received_hdl(struct oid_par_priv* poid_par_priv);
++NDIS_STATUS oid_rt_get_phy_rx_packet_crc32_error_hdl(struct oid_par_priv* poid_par_priv);
++
++NDIS_STATUS oid_rt_set_power_down_hdl(struct oid_par_priv* poid_par_priv);
++
++NDIS_STATUS oid_rt_get_power_mode_hdl(struct oid_par_priv* poid_par_priv);
++
++NDIS_STATUS oid_rt_pro_trigger_gpio_hdl(struct oid_par_priv *poid_par_priv);
++
++#ifdef _RTW_MP_IOCTL_C_
++
++const struct oid_obj_priv oid_rtl_seg_81_80_00[] =
++{
++ {1, &oid_null_function}, //0x00 OID_RT_PRO_RESET_DUT
++ {1, &oid_rt_pro_set_data_rate_hdl}, //0x01
++ {1, &oid_rt_pro_start_test_hdl}, //0x02
++ {1, &oid_rt_pro_stop_test_hdl}, //0x03
++ {1, &oid_null_function}, //0x04 OID_RT_PRO_SET_PREAMBLE
++ {1, &oid_null_function}, //0x05 OID_RT_PRO_SET_SCRAMBLER
++ {1, &oid_null_function}, //0x06 OID_RT_PRO_SET_FILTER_BB
++ {1, &oid_null_function}, //0x07 OID_RT_PRO_SET_MANUAL_DIVERSITY_BB
++ {1, &oid_rt_pro_set_channel_direct_call_hdl}, //0x08
++ {1, &oid_null_function}, //0x09 OID_RT_PRO_SET_SLEEP_MODE_DIRECT_CALL
++ {1, &oid_null_function}, //0x0A OID_RT_PRO_SET_WAKE_MODE_DIRECT_CALL
++ {1, &oid_rt_pro_set_continuous_tx_hdl}, //0x0B OID_RT_PRO_SET_TX_CONTINUOUS_DIRECT_CALL
++ {1, &oid_rt_pro_set_single_carrier_tx_hdl}, //0x0C OID_RT_PRO_SET_SINGLE_CARRIER_TX_CONTINUOUS
++ {1, &oid_null_function}, //0x0D OID_RT_PRO_SET_TX_ANTENNA_BB
++ {1, &oid_rt_pro_set_antenna_bb_hdl}, //0x0E
++ {1, &oid_null_function}, //0x0F OID_RT_PRO_SET_CR_SCRAMBLER
++ {1, &oid_null_function}, //0x10 OID_RT_PRO_SET_CR_NEW_FILTER
++ {1, &oid_rt_pro_set_tx_power_control_hdl}, //0x11 OID_RT_PRO_SET_TX_POWER_CONTROL
++ {1, &oid_null_function}, //0x12 OID_RT_PRO_SET_CR_TX_CONFIG
++ {1, &oid_null_function}, //0x13 OID_RT_PRO_GET_TX_POWER_CONTROL
++ {1, &oid_null_function}, //0x14 OID_RT_PRO_GET_CR_SIGNAL_QUALITY
++ {1, &oid_null_function}, //0x15 OID_RT_PRO_SET_CR_SETPOINT
++ {1, &oid_null_function}, //0x16 OID_RT_PRO_SET_INTEGRATOR
++ {1, &oid_null_function}, //0x17 OID_RT_PRO_SET_SIGNAL_QUALITY
++ {1, &oid_null_function}, //0x18 OID_RT_PRO_GET_INTEGRATOR
++ {1, &oid_null_function}, //0x19 OID_RT_PRO_GET_SIGNAL_QUALITY
++ {1, &oid_null_function}, //0x1A OID_RT_PRO_QUERY_EEPROM_TYPE
++ {1, &oid_null_function}, //0x1B OID_RT_PRO_WRITE_MAC_ADDRESS
++ {1, &oid_null_function}, //0x1C OID_RT_PRO_READ_MAC_ADDRESS
++ {1, &oid_null_function}, //0x1D OID_RT_PRO_WRITE_CIS_DATA
++ {1, &oid_null_function}, //0x1E OID_RT_PRO_READ_CIS_DATA
++ {1, &oid_null_function} //0x1F OID_RT_PRO_WRITE_POWER_CONTROL
++
++};
++
++const struct oid_obj_priv oid_rtl_seg_81_80_20[] =
++{
++ {1, &oid_null_function}, //0x20 OID_RT_PRO_READ_POWER_CONTROL
++ {1, &oid_null_function}, //0x21 OID_RT_PRO_WRITE_EEPROM
++ {1, &oid_null_function}, //0x22 OID_RT_PRO_READ_EEPROM
++ {1, &oid_rt_pro_reset_tx_packet_sent_hdl}, //0x23
++ {1, &oid_rt_pro_query_tx_packet_sent_hdl}, //0x24
++ {1, &oid_rt_pro_reset_rx_packet_received_hdl}, //0x25
++ {1, &oid_rt_pro_query_rx_packet_received_hdl}, //0x26
++ {1, &oid_rt_pro_query_rx_packet_crc32_error_hdl}, //0x27
++ {1, &oid_null_function}, //0x28 OID_RT_PRO_QUERY_CURRENT_ADDRESS
++ {1, &oid_null_function}, //0x29 OID_RT_PRO_QUERY_PERMANENT_ADDRESS
++ {1, &oid_null_function}, //0x2A OID_RT_PRO_SET_PHILIPS_RF_PARAMETERS
++ {1, &oid_rt_pro_set_carrier_suppression_tx_hdl},//0x2B OID_RT_PRO_SET_CARRIER_SUPPRESSION_TX
++ {1, &oid_null_function}, //0x2C OID_RT_PRO_RECEIVE_PACKET
++ {1, &oid_null_function}, //0x2D OID_RT_PRO_WRITE_EEPROM_BYTE
++ {1, &oid_null_function}, //0x2E OID_RT_PRO_READ_EEPROM_BYTE
++ {1, &oid_rt_pro_set_modulation_hdl} //0x2F
++
++};
++
++const struct oid_obj_priv oid_rtl_seg_81_80_40[] =
++{
++ {1, &oid_null_function}, //0x40
++ {1, &oid_null_function}, //0x41
++ {1, &oid_null_function}, //0x42
++ {1, &oid_rt_pro_set_single_tone_tx_hdl}, //0x43
++ {1, &oid_null_function}, //0x44
++ {1, &oid_null_function} //0x45
++};
++
++const struct oid_obj_priv oid_rtl_seg_81_80_80[] =
++{
++ {1, &oid_null_function}, //0x80 OID_RT_DRIVER_OPTION
++ {1, &oid_null_function}, //0x81 OID_RT_RF_OFF
++ {1, &oid_null_function} //0x82 OID_RT_AUTH_STATUS
++
++};
++
++const struct oid_obj_priv oid_rtl_seg_81_85[] =
++{
++ {1, &oid_rt_wireless_mode_hdl} //0x00 OID_RT_WIRELESS_MODE
++};
++
++struct oid_obj_priv oid_rtl_seg_81_87[] =
++{
++ {1, &oid_null_function}, //0x80 OID_RT_PRO8187_WI_POLL
++ {1, &oid_rt_pro_write_bb_reg_hdl}, //0x81
++ {1, &oid_rt_pro_read_bb_reg_hdl}, //0x82
++ {1, &oid_rt_pro_write_rf_reg_hdl}, //0x82
++ {1, &oid_rt_pro_read_rf_reg_hdl} //0x83
++};
++
++struct oid_obj_priv oid_rtl_seg_87_11_00[] =
++{
++ {1, &oid_rt_pro8711_join_bss_hdl}, //0x00 //S
++ {1, &oid_rt_pro_read_register_hdl}, //0x01
++ {1, &oid_rt_pro_write_register_hdl}, //0x02
++ {1, &oid_rt_pro_burst_read_register_hdl}, //0x03
++ {1, &oid_rt_pro_burst_write_register_hdl}, //0x04
++ {1, &oid_rt_pro_write_txcmd_hdl}, //0x05
++ {1, &oid_rt_pro_read16_eeprom_hdl}, //0x06
++ {1, &oid_rt_pro_write16_eeprom_hdl}, //0x07
++ {1, &oid_null_function}, //0x08 OID_RT_PRO_H2C_SET_COMMAND
++ {1, &oid_null_function}, //0x09 OID_RT_PRO_H2C_QUERY_RESULT
++ {1, &oid_rt_pro8711_wi_poll_hdl}, //0x0A
++ {1, &oid_rt_pro8711_pkt_loss_hdl}, //0x0B
++ {1, &oid_rt_rd_attrib_mem_hdl}, //0x0C
++ {1, &oid_rt_wr_attrib_mem_hdl}, //0x0D
++ {1, &oid_null_function}, //0x0E
++ {1, &oid_null_function}, //0x0F
++ {1, &oid_null_function}, //0x10 OID_RT_PRO_H2C_CMD_MODE
++ {1, &oid_null_function}, //0x11 OID_RT_PRO_H2C_CMD_RSP_MODE
++ {1, &oid_null_function}, //0X12 OID_RT_PRO_WAIT_C2H_EVENT
++ {1, &oid_null_function}, //0X13 OID_RT_PRO_RW_ACCESS_PROTOCOL_TEST
++ {1, &oid_null_function}, //0X14 OID_RT_PRO_SCSI_ACCESS_TEST
++ {1, &oid_null_function}, //0X15 OID_RT_PRO_SCSI_TCPIPOFFLOAD_OUT
++ {1, &oid_null_function}, //0X16 OID_RT_PRO_SCSI_TCPIPOFFLOAD_IN
++ {1, &oid_null_function}, //0X17 OID_RT_RRO_RX_PKT_VIA_IOCTRL
++ {1, &oid_null_function}, //0X18 OID_RT_RRO_RX_PKTARRAY_VIA_IOCTRL
++ {1, &oid_null_function}, //0X19 OID_RT_RPO_SET_PWRMGT_TEST
++ {1, &oid_null_function}, //0X1A
++ {1, &oid_null_function}, //0X1B OID_RT_PRO_QRY_PWRMGT_TEST
++ {1, &oid_null_function}, //0X1C OID_RT_RPO_ASYNC_RWIO_TEST
++ {1, &oid_null_function}, //0X1D OID_RT_RPO_ASYNC_RWIO_POLL
++ {1, &oid_rt_pro_set_rf_intfs_hdl}, //0X1E
++ {1, &oid_rt_poll_rx_status_hdl} //0X1F
++};
++
++struct oid_obj_priv oid_rtl_seg_87_11_20[] =
++{
++ {1, &oid_rt_pro_cfg_debug_message_hdl}, //0x20
++ {1, &oid_rt_pro_set_data_rate_ex_hdl}, //0x21
++ {1, &oid_rt_pro_set_basic_rate_hdl}, //0x22
++ {1, &oid_rt_pro_read_tssi_hdl}, //0x23
++ {1, &oid_rt_pro_set_power_tracking_hdl} //0x24
++};
++
++
++struct oid_obj_priv oid_rtl_seg_87_11_50[] =
++{
++ {1, &oid_rt_pro_qry_pwrstate_hdl}, //0x50
++ {1, &oid_rt_pro_set_pwrstate_hdl} //0x51
++};
++
++struct oid_obj_priv oid_rtl_seg_87_11_80[] =
++{
++ {1, &oid_null_function} //0x80
++};
++
++struct oid_obj_priv oid_rtl_seg_87_11_B0[] =
++{
++ {1, &oid_null_function} //0xB0
++};
++
++struct oid_obj_priv oid_rtl_seg_87_11_F0[] =
++{
++ {1, &oid_null_function}, //0xF0
++ {1, &oid_null_function}, //0xF1
++ {1, &oid_null_function}, //0xF2
++ {1, &oid_null_function}, //0xF3
++ {1, &oid_null_function}, //0xF4
++ {1, &oid_null_function}, //0xF5
++ {1, &oid_null_function}, //0xF6
++ {1, &oid_null_function}, //0xF7
++ {1, &oid_null_function}, //0xF8
++ {1, &oid_null_function}, //0xF9
++ {1, &oid_null_function}, //0xFA
++ {1, &oid_rt_pro_h2c_set_rate_table_hdl}, //0xFB
++ {1, &oid_rt_pro_h2c_get_rate_table_hdl}, //0xFC
++ {1, &oid_null_function}, //0xFD
++ {1, &oid_null_function}, //0xFE OID_RT_PRO_H2C_C2H_LBK_TEST
++ {1, &oid_null_function} //0xFF
++
++};
++
++struct oid_obj_priv oid_rtl_seg_87_12_00[]=
++{
++ {1, &oid_rt_pro_encryption_ctrl_hdl}, //0x00 Q&S
++ {1, &oid_rt_pro_add_sta_info_hdl}, //0x01 S
++ {1, &oid_rt_pro_dele_sta_info_hdl}, //0x02 S
++ {1, &oid_rt_pro_query_dr_variable_hdl}, //0x03 Q
++ {1, &oid_rt_pro_rx_packet_type_hdl}, //0x04 Q,S
++ {1, &oid_rt_pro_read_efuse_hdl}, //0x05 Q OID_RT_PRO_READ_EFUSE
++ {1, &oid_rt_pro_write_efuse_hdl}, //0x06 S OID_RT_PRO_WRITE_EFUSE
++ {1, &oid_rt_pro_rw_efuse_pgpkt_hdl}, //0x07 Q,S
++ {1, &oid_rt_get_efuse_current_size_hdl}, //0x08 Q
++ {1, &oid_rt_set_bandwidth_hdl}, //0x09
++ {1, &oid_rt_set_crystal_cap_hdl}, //0x0a
++ {1, &oid_rt_set_rx_packet_type_hdl}, //0x0b S
++ {1, &oid_rt_get_efuse_max_size_hdl}, //0x0c
++ {1, &oid_rt_pro_set_tx_agc_offset_hdl}, //0x0d
++ {1, &oid_rt_pro_set_pkt_test_mode_hdl}, //0x0e
++ {1, &oid_null_function}, //0x0f OID_RT_PRO_FOR_EVM_TEST_SETTING
++ {1, &oid_rt_get_thermal_meter_hdl}, //0x10 Q OID_RT_PRO_GET_THERMAL_METER
++ {1, &oid_rt_reset_phy_rx_packet_count_hdl}, //0x11 S OID_RT_RESET_PHY_RX_PACKET_COUNT
++ {1, &oid_rt_get_phy_rx_packet_received_hdl}, //0x12 Q OID_RT_GET_PHY_RX_PACKET_RECEIVED
++ {1, &oid_rt_get_phy_rx_packet_crc32_error_hdl}, //0x13 Q OID_RT_GET_PHY_RX_PACKET_CRC32_ERROR
++ {1, &oid_rt_set_power_down_hdl}, //0x14 Q OID_RT_SET_POWER_DOWN
++ {1, &oid_rt_get_power_mode_hdl} //0x15 Q OID_RT_GET_POWER_MODE
++};
++
++#else /* _RTL871X_MP_IOCTL_C_ */
++
++extern struct oid_obj_priv oid_rtl_seg_81_80_00[32];
++extern struct oid_obj_priv oid_rtl_seg_81_80_20[16];
++extern struct oid_obj_priv oid_rtl_seg_81_80_40[6];
++extern struct oid_obj_priv oid_rtl_seg_81_80_80[3];
++
++extern struct oid_obj_priv oid_rtl_seg_81_85[1];
++extern struct oid_obj_priv oid_rtl_seg_81_87[5];
++
++extern struct oid_obj_priv oid_rtl_seg_87_11_00[32];
++extern struct oid_obj_priv oid_rtl_seg_87_11_20[5];
++extern struct oid_obj_priv oid_rtl_seg_87_11_50[2];
++extern struct oid_obj_priv oid_rtl_seg_87_11_80[1];
++extern struct oid_obj_priv oid_rtl_seg_87_11_B0[1];
++extern struct oid_obj_priv oid_rtl_seg_87_11_F0[16];
++
++extern struct oid_obj_priv oid_rtl_seg_87_12_00[32];
++
++#endif /* _RTL871X_MP_IOCTL_C_ */
++
++struct rwreg_param{
++ u32 offset;
++ u32 width;
++ u32 value;
++};
++
++struct bbreg_param{
++ u32 offset;
++ u32 phymask;
++ u32 value;
++};
++/*
++struct rfchannel_param{
++ u32 ch;
++ u32 modem;
++};
++*/
++struct txpower_param{
++ u32 pwr_index;
++};
++
++
++struct datarate_param{
++ u32 rate_index;
++};
++
++
++struct rfintfs_parm {
++ u32 rfintfs;
++};
++
++typedef struct _mp_xmit_parm_ {
++ u8 enable;
++ u32 count;
++ u16 length;
++ u8 payload_type;
++ u8 da[ETH_ALEN];
++}MP_XMIT_PARM, *PMP_XMIT_PARM;
++
++struct mp_xmit_packet {
++ u32 len;
++ u32 mem[MAX_MP_XMITBUF_SZ >> 2];
++};
++
++struct psmode_param {
++ u32 ps_mode;
++ u32 smart_ps;
++};
++
++//for OID_RT_PRO_READ16_EEPROM & OID_RT_PRO_WRITE16_EEPROM
++struct eeprom_rw_param {
++ u32 offset;
++ u16 value;
++};
++
++struct mp_ioctl_handler {
++ u32 paramsize;
++ u32 (*handler)(struct oid_par_priv* poid_par_priv);
++ u32 oid;
++};
++
++struct mp_ioctl_param{
++ u32 subcode;
++ u32 len;
++ u8 data[0];
++};
++
++#define GEN_MP_IOCTL_SUBCODE(code) _MP_IOCTL_ ## code ## _CMD_
++
++enum RTL871X_MP_IOCTL_SUBCODE {
++ GEN_MP_IOCTL_SUBCODE(MP_START), /*0*/
++ GEN_MP_IOCTL_SUBCODE(MP_STOP),
++ GEN_MP_IOCTL_SUBCODE(READ_REG),
++ GEN_MP_IOCTL_SUBCODE(WRITE_REG),
++ GEN_MP_IOCTL_SUBCODE(READ_BB_REG),
++ GEN_MP_IOCTL_SUBCODE(WRITE_BB_REG), /*5*/
++ GEN_MP_IOCTL_SUBCODE(READ_RF_REG),
++ GEN_MP_IOCTL_SUBCODE(WRITE_RF_REG),
++ GEN_MP_IOCTL_SUBCODE(SET_CHANNEL),
++ GEN_MP_IOCTL_SUBCODE(SET_TXPOWER),
++ GEN_MP_IOCTL_SUBCODE(SET_DATARATE), /*10*/
++ GEN_MP_IOCTL_SUBCODE(SET_BANDWIDTH),
++ GEN_MP_IOCTL_SUBCODE(SET_ANTENNA),
++ GEN_MP_IOCTL_SUBCODE(CNTU_TX),
++ GEN_MP_IOCTL_SUBCODE(SC_TX),
++ GEN_MP_IOCTL_SUBCODE(CS_TX), /*15*/
++ GEN_MP_IOCTL_SUBCODE(ST_TX),
++ GEN_MP_IOCTL_SUBCODE(IOCTL_XMIT_PACKET),
++ GEN_MP_IOCTL_SUBCODE(SET_RX_PKT_TYPE),
++ GEN_MP_IOCTL_SUBCODE(RESET_PHY_RX_PKT_CNT),
++ GEN_MP_IOCTL_SUBCODE(GET_PHY_RX_PKT_RECV), /*20*/
++ GEN_MP_IOCTL_SUBCODE(GET_PHY_RX_PKT_ERROR),
++ GEN_MP_IOCTL_SUBCODE(READ16_EEPROM),
++ GEN_MP_IOCTL_SUBCODE(WRITE16_EEPROM),
++ GEN_MP_IOCTL_SUBCODE(EFUSE),
++ GEN_MP_IOCTL_SUBCODE(EFUSE_MAP), /*25*/
++ GEN_MP_IOCTL_SUBCODE(GET_EFUSE_MAX_SIZE),
++ GEN_MP_IOCTL_SUBCODE(GET_EFUSE_CURRENT_SIZE),
++ GEN_MP_IOCTL_SUBCODE(GET_THERMAL_METER),
++ GEN_MP_IOCTL_SUBCODE(SET_PTM),
++ GEN_MP_IOCTL_SUBCODE(SET_POWER_DOWN), /*30*/
++ GEN_MP_IOCTL_SUBCODE(TRIGGER_GPIO),
++ GEN_MP_IOCTL_SUBCODE(SET_DM_BT), /*35*/
++ GEN_MP_IOCTL_SUBCODE(DEL_BA), /*36*/
++ GEN_MP_IOCTL_SUBCODE(GET_WIFI_STATUS), /*37*/
++ MAX_MP_IOCTL_SUBCODE,
++};
++
++u32 mp_ioctl_xmit_packet_hdl(struct oid_par_priv* poid_par_priv);
++
++#ifdef _RTW_MP_IOCTL_C_
++
++#define GEN_MP_IOCTL_HANDLER(sz, hdl, oid) {sz, hdl, oid},
++
++#define EXT_MP_IOCTL_HANDLER(sz, subcode, oid) {sz, mp_ioctl_ ## subcode ## _hdl, oid},
++
++
++struct mp_ioctl_handler mp_ioctl_hdl[] = {
++
++/*0*/ GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_pro_start_test_hdl, OID_RT_PRO_START_TEST)
++ GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_pro_stop_test_hdl, OID_RT_PRO_STOP_TEST)
++
++ GEN_MP_IOCTL_HANDLER(sizeof(struct rwreg_param), oid_rt_pro_read_register_hdl, OID_RT_PRO_READ_REGISTER)
++ GEN_MP_IOCTL_HANDLER(sizeof(struct rwreg_param), oid_rt_pro_write_register_hdl, OID_RT_PRO_WRITE_REGISTER)
++ GEN_MP_IOCTL_HANDLER(sizeof(struct bb_reg_param), oid_rt_pro_read_bb_reg_hdl, OID_RT_PRO_READ_BB_REG)
++/*5*/ GEN_MP_IOCTL_HANDLER(sizeof(struct bb_reg_param), oid_rt_pro_write_bb_reg_hdl, OID_RT_PRO_WRITE_BB_REG)
++ GEN_MP_IOCTL_HANDLER(sizeof(struct rf_reg_param), oid_rt_pro_read_rf_reg_hdl, OID_RT_PRO_RF_READ_REGISTRY)
++ GEN_MP_IOCTL_HANDLER(sizeof(struct rf_reg_param), oid_rt_pro_write_rf_reg_hdl, OID_RT_PRO_RF_WRITE_REGISTRY)
++
++ GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_pro_set_channel_direct_call_hdl, OID_RT_PRO_SET_CHANNEL_DIRECT_CALL)
++ GEN_MP_IOCTL_HANDLER(sizeof(struct txpower_param), oid_rt_pro_set_tx_power_control_hdl, OID_RT_PRO_SET_TX_POWER_CONTROL)
++/*10*/ GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_pro_set_data_rate_hdl, OID_RT_PRO_SET_DATA_RATE)
++ GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_set_bandwidth_hdl, OID_RT_SET_BANDWIDTH)
++ GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_pro_set_antenna_bb_hdl, OID_RT_PRO_SET_ANTENNA_BB)
++
++ GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_pro_set_continuous_tx_hdl, OID_RT_PRO_SET_CONTINUOUS_TX)
++ GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_pro_set_single_carrier_tx_hdl, OID_RT_PRO_SET_SINGLE_CARRIER_TX)
++/*15*/ GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_pro_set_carrier_suppression_tx_hdl, OID_RT_PRO_SET_CARRIER_SUPPRESSION_TX)
++ GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_pro_set_single_tone_tx_hdl, OID_RT_PRO_SET_SINGLE_TONE_TX)
++
++ EXT_MP_IOCTL_HANDLER(0, xmit_packet, 0)
++
++ GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_set_rx_packet_type_hdl, OID_RT_SET_RX_PACKET_TYPE)
++ GEN_MP_IOCTL_HANDLER(0, oid_rt_reset_phy_rx_packet_count_hdl, OID_RT_RESET_PHY_RX_PACKET_COUNT)
++/*20*/ GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_get_phy_rx_packet_received_hdl, OID_RT_GET_PHY_RX_PACKET_RECEIVED)
++ GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_get_phy_rx_packet_crc32_error_hdl, OID_RT_GET_PHY_RX_PACKET_CRC32_ERROR)
++
++ GEN_MP_IOCTL_HANDLER(sizeof(struct eeprom_rw_param), NULL, 0)
++ GEN_MP_IOCTL_HANDLER(sizeof(struct eeprom_rw_param), NULL, 0)
++ GEN_MP_IOCTL_HANDLER(sizeof(EFUSE_ACCESS_STRUCT), oid_rt_pro_efuse_hdl, OID_RT_PRO_EFUSE)
++/*25*/ GEN_MP_IOCTL_HANDLER(0, oid_rt_pro_efuse_map_hdl, OID_RT_PRO_EFUSE_MAP)
++ GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_get_efuse_max_size_hdl, OID_RT_GET_EFUSE_MAX_SIZE)
++ GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_get_efuse_current_size_hdl, OID_RT_GET_EFUSE_CURRENT_SIZE)
++
++ GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_get_thermal_meter_hdl, OID_RT_PRO_GET_THERMAL_METER)
++ GEN_MP_IOCTL_HANDLER(sizeof(u8), oid_rt_pro_set_power_tracking_hdl, OID_RT_PRO_SET_POWER_TRACKING)
++/*30*/ GEN_MP_IOCTL_HANDLER(sizeof(u8), oid_rt_set_power_down_hdl, OID_RT_SET_POWER_DOWN)
++/*31*/ GEN_MP_IOCTL_HANDLER(0, oid_rt_pro_trigger_gpio_hdl, 0)
++
++
++};
++
++#else /* _RTW_MP_IOCTL_C_ */
++
++extern struct mp_ioctl_handler mp_ioctl_hdl[];
++
++#endif /* _RTW_MP_IOCTL_C_ */
++
++#endif
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtw_mp_phy_regdef.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtw_mp_phy_regdef.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtw_mp_phy_regdef.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtw_mp_phy_regdef.h 2015-07-28 01:20:58.321597318 +0200
+@@ -0,0 +1,1096 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++/*****************************************************************************
++ *
++ * Module: __RTW_MP_PHY_REGDEF_H_
++ *
++ *
++ * Note: 1. Define PMAC/BB register map
++ * 2. Define RF register map
++ * 3. PMAC/BB register bit mask.
++ * 4. RF reg bit mask.
++ * 5. Other BB/RF relative definition.
++ *
++ *
++ * Export: Constants, macro, functions(API), global variables(None).
++ *
++ * Abbrev:
++ *
++ * History:
++ * Data Who Remark
++ * 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h.
++ * 2. Reorganize code architecture.
++ * 09/25/2008 MH 1. Add RL6052 register definition
++ *
++ *****************************************************************************/
++#ifndef __RTW_MP_PHY_REGDEF_H_
++#define __RTW_MP_PHY_REGDEF_H_
++
++
++/*--------------------------Define Parameters-------------------------------*/
++
++//============================================================
++// 8192S Regsiter offset definition
++//============================================================
++
++//
++// BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
++// 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
++// 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
++// 3. RF register 0x00-2E
++// 4. Bit Mask for BB/RF register
++// 5. Other defintion for BB/RF R/W
++//
++
++
++//
++// 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
++// 1. Page1(0x100)
++//
++#define rPMAC_Reset 0x100
++#define rPMAC_TxStart 0x104
++#define rPMAC_TxLegacySIG 0x108
++#define rPMAC_TxHTSIG1 0x10c
++#define rPMAC_TxHTSIG2 0x110
++#define rPMAC_PHYDebug 0x114
++#define rPMAC_TxPacketNum 0x118
++#define rPMAC_TxIdle 0x11c
++#define rPMAC_TxMACHeader0 0x120
++#define rPMAC_TxMACHeader1 0x124
++#define rPMAC_TxMACHeader2 0x128
++#define rPMAC_TxMACHeader3 0x12c
++#define rPMAC_TxMACHeader4 0x130
++#define rPMAC_TxMACHeader5 0x134
++#define rPMAC_TxDataType 0x138
++#define rPMAC_TxRandomSeed 0x13c
++#define rPMAC_CCKPLCPPreamble 0x140
++#define rPMAC_CCKPLCPHeader 0x144
++#define rPMAC_CCKCRC16 0x148
++#define rPMAC_OFDMRxCRC32OK 0x170
++#define rPMAC_OFDMRxCRC32Er 0x174
++#define rPMAC_OFDMRxParityEr 0x178
++#define rPMAC_OFDMRxCRC8Er 0x17c
++#define rPMAC_CCKCRxRC16Er 0x180
++#define rPMAC_CCKCRxRC32Er 0x184
++#define rPMAC_CCKCRxRC32OK 0x188
++#define rPMAC_TxStatus 0x18c
++
++//
++// 2. Page2(0x200)
++//
++// The following two definition are only used for USB interface.
++//#define RF_BB_CMD_ADDR 0x02c0 // RF/BB read/write command address.
++//#define RF_BB_CMD_DATA 0x02c4 // RF/BB read/write command data.
++
++//
++// 3. Page8(0x800)
++//
++#define rFPGA0_RFMOD 0x800 //RF mode & CCK TxSC // RF BW Setting??
++
++#define rFPGA0_TxInfo 0x804 // Status report??
++#define rFPGA0_PSDFunction 0x808
++
++#define rFPGA0_TxGainStage 0x80c // Set TX PWR init gain?
++
++#define rFPGA0_RFTiming1 0x810 // Useless now
++#define rFPGA0_RFTiming2 0x814
++//#define rFPGA0_XC_RFTiming 0x818
++//#define rFPGA0_XD_RFTiming 0x81c
++
++#define rFPGA0_XA_HSSIParameter1 0x820 // RF 3 wire register
++#define rFPGA0_XA_HSSIParameter2 0x824
++#define rFPGA0_XB_HSSIParameter1 0x828
++#define rFPGA0_XB_HSSIParameter2 0x82c
++#define rFPGA0_XC_HSSIParameter1 0x830
++#define rFPGA0_XC_HSSIParameter2 0x834
++#define rFPGA0_XD_HSSIParameter1 0x838
++#define rFPGA0_XD_HSSIParameter2 0x83c
++#define rFPGA0_XA_LSSIParameter 0x840
++#define rFPGA0_XB_LSSIParameter 0x844
++#define rFPGA0_XC_LSSIParameter 0x848
++#define rFPGA0_XD_LSSIParameter 0x84c
++
++#define rFPGA0_RFWakeUpParameter 0x850 // Useless now
++#define rFPGA0_RFSleepUpParameter 0x854
++
++#define rFPGA0_XAB_SwitchControl 0x858 // RF Channel switch
++#define rFPGA0_XCD_SwitchControl 0x85c
++
++#define rFPGA0_XA_RFInterfaceOE 0x860 // RF Channel switch
++#define rFPGA0_XB_RFInterfaceOE 0x864
++#define rFPGA0_XC_RFInterfaceOE 0x868
++#define rFPGA0_XD_RFInterfaceOE 0x86c
++
++#define rFPGA0_XAB_RFInterfaceSW 0x870 // RF Interface Software Control
++#define rFPGA0_XCD_RFInterfaceSW 0x874
++
++#define rFPGA0_XAB_RFParameter 0x878 // RF Parameter
++#define rFPGA0_XCD_RFParameter 0x87c
++
++#define rFPGA0_AnalogParameter1 0x880 // Crystal cap setting RF-R/W protection for parameter4??
++#define rFPGA0_AnalogParameter2 0x884
++#define rFPGA0_AnalogParameter3 0x888 // Useless now
++#define rFPGA0_AnalogParameter4 0x88c
++
++#define rFPGA0_XA_LSSIReadBack 0x8a0 // Tranceiver LSSI Readback
++#define rFPGA0_XB_LSSIReadBack 0x8a4
++#define rFPGA0_XC_LSSIReadBack 0x8a8
++#define rFPGA0_XD_LSSIReadBack 0x8ac
++
++#define rFPGA0_PSDReport 0x8b4 // Useless now
++#define rFPGA0_XAB_RFInterfaceRB 0x8e0 // Useless now // RF Interface Readback Value
++#define rFPGA0_XCD_RFInterfaceRB 0x8e4 // Useless now
++
++//
++// 4. Page9(0x900)
++//
++#define rFPGA1_RFMOD 0x900 //RF mode & OFDM TxSC // RF BW Setting??
++
++#define rFPGA1_TxBlock 0x904 // Useless now
++#define rFPGA1_DebugSelect 0x908 // Useless now
++#define rFPGA1_TxInfo 0x90c // Useless now // Status report??
++
++//
++// 5. PageA(0xA00)
++//
++// Set Control channel to upper or lower. These settings are required only for 40MHz
++#define rCCK0_System 0xa00
++
++#define rCCK0_AFESetting 0xa04 // Disable init gain now // Select RX path by RSSI
++#define rCCK0_CCA 0xa08 // Disable init gain now // Init gain
++
++#define rCCK0_RxAGC1 0xa0c //AGC default value, saturation level // Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series
++#define rCCK0_RxAGC2 0xa10 //AGC & DAGC
++
++#define rCCK0_RxHP 0xa14
++
++#define rCCK0_DSPParameter1 0xa18 //Timing recovery & Channel estimation threshold
++#define rCCK0_DSPParameter2 0xa1c //SQ threshold
++
++#define rCCK0_TxFilter1 0xa20
++#define rCCK0_TxFilter2 0xa24
++#define rCCK0_DebugPort 0xa28 //debug port and Tx filter3
++#define rCCK0_FalseAlarmReport 0xa2c //0xa2d useless now 0xa30-a4f channel report
++#define rCCK0_TRSSIReport 0xa50
++#define rCCK0_RxReport 0xa54 //0xa57
++#define rCCK0_FACounterLower 0xa5c //0xa5b
++#define rCCK0_FACounterUpper 0xa58 //0xa5c
++
++//
++// 6. PageC(0xC00)
++//
++#define rOFDM0_LSTF 0xc00
++
++#define rOFDM0_TRxPathEnable 0xc04
++#define rOFDM0_TRMuxPar 0xc08
++#define rOFDM0_TRSWIsolation 0xc0c
++
++#define rOFDM0_XARxAFE 0xc10 //RxIQ DC offset, Rx digital filter, DC notch filter
++#define rOFDM0_XARxIQImbalance 0xc14 //RxIQ imblance matrix
++#define rOFDM0_XBRxAFE 0xc18
++#define rOFDM0_XBRxIQImbalance 0xc1c
++#define rOFDM0_XCRxAFE 0xc20
++#define rOFDM0_XCRxIQImbalance 0xc24
++#define rOFDM0_XDRxAFE 0xc28
++#define rOFDM0_XDRxIQImbalance 0xc2c
++
++#define rOFDM0_RxDetector1 0xc30 //PD,BW & SBD // DM tune init gain
++#define rOFDM0_RxDetector2 0xc34 //SBD & Fame Sync.
++#define rOFDM0_RxDetector3 0xc38 //Frame Sync.
++#define rOFDM0_RxDetector4 0xc3c //PD, SBD, Frame Sync & Short-GI
++
++#define rOFDM0_RxDSP 0xc40 //Rx Sync Path
++#define rOFDM0_CFOandDAGC 0xc44 //CFO & DAGC
++#define rOFDM0_CCADropThreshold 0xc48 //CCA Drop threshold
++#define rOFDM0_ECCAThreshold 0xc4c // energy CCA
++
++#define rOFDM0_XAAGCCore1 0xc50 // DIG
++#define rOFDM0_XAAGCCore2 0xc54
++#define rOFDM0_XBAGCCore1 0xc58
++#define rOFDM0_XBAGCCore2 0xc5c
++#define rOFDM0_XCAGCCore1 0xc60
++#define rOFDM0_XCAGCCore2 0xc64
++#define rOFDM0_XDAGCCore1 0xc68
++#define rOFDM0_XDAGCCore2 0xc6c
++
++#define rOFDM0_AGCParameter1 0xc70
++#define rOFDM0_AGCParameter2 0xc74
++#define rOFDM0_AGCRSSITable 0xc78
++#define rOFDM0_HTSTFAGC 0xc7c
++
++#define rOFDM0_XATxIQImbalance 0xc80 // TX PWR TRACK and DIG
++#define rOFDM0_XATxAFE 0xc84
++#define rOFDM0_XBTxIQImbalance 0xc88
++#define rOFDM0_XBTxAFE 0xc8c
++#define rOFDM0_XCTxIQImbalance 0xc90
++#define rOFDM0_XCTxAFE 0xc94
++#define rOFDM0_XDTxIQImbalance 0xc98
++#define rOFDM0_XDTxAFE 0xc9c
++#define rOFDM0_RxIQExtAnta 0xca0
++
++#define rOFDM0_RxHPParameter 0xce0
++#define rOFDM0_TxPseudoNoiseWgt 0xce4
++#define rOFDM0_FrameSync 0xcf0
++#define rOFDM0_DFSReport 0xcf4
++#define rOFDM0_TxCoeff1 0xca4
++#define rOFDM0_TxCoeff2 0xca8
++#define rOFDM0_TxCoeff3 0xcac
++#define rOFDM0_TxCoeff4 0xcb0
++#define rOFDM0_TxCoeff5 0xcb4
++#define rOFDM0_TxCoeff6 0xcb8
++
++
++//
++// 7. PageD(0xD00)
++//
++#define rOFDM1_LSTF 0xd00
++#define rOFDM1_TRxPathEnable 0xd04
++
++#define rOFDM1_CFO 0xd08 // No setting now
++#define rOFDM1_CSI1 0xd10
++#define rOFDM1_SBD 0xd14
++#define rOFDM1_CSI2 0xd18
++#define rOFDM1_CFOTracking 0xd2c
++#define rOFDM1_TRxMesaure1 0xd34
++#define rOFDM1_IntfDet 0xd3c
++#define rOFDM1_PseudoNoiseStateAB 0xd50
++#define rOFDM1_PseudoNoiseStateCD 0xd54
++#define rOFDM1_RxPseudoNoiseWgt 0xd58
++
++#define rOFDM_PHYCounter1 0xda0 //cca, parity fail
++#define rOFDM_PHYCounter2 0xda4 //rate illegal, crc8 fail
++#define rOFDM_PHYCounter3 0xda8 //MCS not support
++
++#define rOFDM_ShortCFOAB 0xdac // No setting now
++#define rOFDM_ShortCFOCD 0xdb0
++#define rOFDM_LongCFOAB 0xdb4
++#define rOFDM_LongCFOCD 0xdb8
++#define rOFDM_TailCFOAB 0xdbc
++#define rOFDM_TailCFOCD 0xdc0
++#define rOFDM_PWMeasure1 0xdc4
++#define rOFDM_PWMeasure2 0xdc8
++#define rOFDM_BWReport 0xdcc
++#define rOFDM_AGCReport 0xdd0
++#define rOFDM_RxSNR 0xdd4
++#define rOFDM_RxEVMCSI 0xdd8
++#define rOFDM_SIGReport 0xddc
++
++
++//
++// 8. PageE(0xE00)
++//
++#define rTxAGC_Rate18_06 0xe00
++#define rTxAGC_Rate54_24 0xe04
++#define rTxAGC_CCK_Mcs32 0xe08
++#define rTxAGC_Mcs03_Mcs00 0xe10
++#define rTxAGC_Mcs07_Mcs04 0xe14
++#define rTxAGC_Mcs11_Mcs08 0xe18
++#define rTxAGC_Mcs15_Mcs12 0xe1c
++
++// Analog- control in RX_WAIT_CCA : REG: EE0 [Analog- Power & Control Register]
++#define rRx_Wait_CCCA 0xe70
++#define rAnapar_Ctrl_BB 0xee0
++
++//
++// 7. RF Register 0x00-0x2E (RF 8256)
++// RF-0222D 0x00-3F
++//
++//Zebra1
++#define RTL92SE_FPGA_VERIFY 0
++#define rZebra1_HSSIEnable 0x0 // Useless now
++#define rZebra1_TRxEnable1 0x1
++#define rZebra1_TRxEnable2 0x2
++#define rZebra1_AGC 0x4
++#define rZebra1_ChargePump 0x5
++//#if (RTL92SE_FPGA_VERIFY == 1)
++#define rZebra1_Channel 0x7 // RF channel switch
++//#else
++
++//#endif
++#define rZebra1_TxGain 0x8 // Useless now
++#define rZebra1_TxLPF 0x9
++#define rZebra1_RxLPF 0xb
++#define rZebra1_RxHPFCorner 0xc
++
++//Zebra4
++#define rGlobalCtrl 0 // Useless now
++#define rRTL8256_TxLPF 19
++#define rRTL8256_RxLPF 11
++
++//RTL8258
++#define rRTL8258_TxLPF 0x11 // Useless now
++#define rRTL8258_RxLPF 0x13
++#define rRTL8258_RSSILPF 0xa
++
++//
++// RL6052 Register definition
++//
++#define RF_AC 0x00 //
++
++#define RF_IQADJ_G1 0x01 //
++#define RF_IQADJ_G2 0x02 //
++#define RF_POW_TRSW 0x05 //
++
++#define RF_GAIN_RX 0x06 //
++#define RF_GAIN_TX 0x07 //
++
++#define RF_TXM_IDAC 0x08 //
++#define RF_BS_IQGEN 0x0F //
++
++#define RF_MODE1 0x10 //
++#define RF_MODE2 0x11 //
++
++#define RF_RX_AGC_HP 0x12 //
++#define RF_TX_AGC 0x13 //
++#define RF_BIAS 0x14 //
++#define RF_IPA 0x15 //
++#define RF_POW_ABILITY 0x17 //
++#define RF_MODE_AG 0x18 //
++#define rRfChannel 0x18 // RF channel and BW switch
++#define RF_CHNLBW 0x18 // RF channel and BW switch
++#define RF_TOP 0x19 //
++
++#define RF_RX_G1 0x1A //
++#define RF_RX_G2 0x1B //
++
++#define RF_RX_BB2 0x1C //
++#define RF_RX_BB1 0x1D //
++
++#define RF_RCK1 0x1E //
++#define RF_RCK2 0x1F //
++
++#define RF_TX_G1 0x20 //
++#define RF_TX_G2 0x21 //
++#define RF_TX_G3 0x22 //
++
++#define RF_TX_BB1 0x23 //
++
++#define RF_T_METER 0x24 //
++
++#define RF_SYN_G1 0x25 // RF TX Power control
++#define RF_SYN_G2 0x26 // RF TX Power control
++#define RF_SYN_G3 0x27 // RF TX Power control
++#define RF_SYN_G4 0x28 // RF TX Power control
++#define RF_SYN_G5 0x29 // RF TX Power control
++#define RF_SYN_G6 0x2A // RF TX Power control
++#define RF_SYN_G7 0x2B // RF TX Power control
++#define RF_SYN_G8 0x2C // RF TX Power control
++
++#define RF_RCK_OS 0x30 // RF TX PA control
++
++#define RF_TXPA_G1 0x31 // RF TX PA control
++#define RF_TXPA_G2 0x32 // RF TX PA control
++#define RF_TXPA_G3 0x33 // RF TX PA control
++
++//
++//Bit Mask
++//
++// 1. Page1(0x100)
++#define bBBResetB 0x100 // Useless now?
++#define bGlobalResetB 0x200
++#define bOFDMTxStart 0x4
++#define bCCKTxStart 0x8
++#define bCRC32Debug 0x100
++#define bPMACLoopback 0x10
++#define bTxLSIG 0xffffff
++#define bOFDMTxRate 0xf
++#define bOFDMTxReserved 0x10
++#define bOFDMTxLength 0x1ffe0
++#define bOFDMTxParity 0x20000
++#define bTxHTSIG1 0xffffff
++#define bTxHTMCSRate 0x7f
++#define bTxHTBW 0x80
++#define bTxHTLength 0xffff00
++#define bTxHTSIG2 0xffffff
++#define bTxHTSmoothing 0x1
++#define bTxHTSounding 0x2
++#define bTxHTReserved 0x4
++#define bTxHTAggreation 0x8
++#define bTxHTSTBC 0x30
++#define bTxHTAdvanceCoding 0x40
++#define bTxHTShortGI 0x80
++#define bTxHTNumberHT_LTF 0x300
++#define bTxHTCRC8 0x3fc00
++#define bCounterReset 0x10000
++#define bNumOfOFDMTx 0xffff
++#define bNumOfCCKTx 0xffff0000
++#define bTxIdleInterval 0xffff
++#define bOFDMService 0xffff0000
++#define bTxMACHeader 0xffffffff
++#define bTxDataInit 0xff
++#define bTxHTMode 0x100
++#define bTxDataType 0x30000
++#define bTxRandomSeed 0xffffffff
++#define bCCKTxPreamble 0x1
++#define bCCKTxSFD 0xffff0000
++#define bCCKTxSIG 0xff
++#define bCCKTxService 0xff00
++#define bCCKLengthExt 0x8000
++#define bCCKTxLength 0xffff0000
++#define bCCKTxCRC16 0xffff
++#define bCCKTxStatus 0x1
++#define bOFDMTxStatus 0x2
++
++#define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff))
++
++// 2. Page8(0x800)
++#define bRFMOD 0x1 // Reg 0x800 rFPGA0_RFMOD
++#define bJapanMode 0x2
++#define bCCKTxSC 0x30
++#define bCCKEn 0x1000000
++#define bOFDMEn 0x2000000
++
++#define bOFDMRxADCPhase 0x10000 // Useless now
++#define bOFDMTxDACPhase 0x40000
++#define bXATxAGC 0x3f
++
++#define bXBTxAGC 0xf00 // Reg 80c rFPGA0_TxGainStage
++#define bXCTxAGC 0xf000
++#define bXDTxAGC 0xf0000
++
++#define bPAStart 0xf0000000 // Useless now
++#define bTRStart 0x00f00000
++#define bRFStart 0x0000f000
++#define bBBStart 0x000000f0
++#define bBBCCKStart 0x0000000f
++#define bPAEnd 0xf //Reg0x814
++#define bTREnd 0x0f000000
++#define bRFEnd 0x000f0000
++#define bCCAMask 0x000000f0 //T2R
++#define bR2RCCAMask 0x00000f00
++#define bHSSI_R2TDelay 0xf8000000
++#define bHSSI_T2RDelay 0xf80000
++#define bContTxHSSI 0x400 //chane gain at continue Tx
++#define bIGFromCCK 0x200
++#define bAGCAddress 0x3f
++#define bRxHPTx 0x7000
++#define bRxHPT2R 0x38000
++#define bRxHPCCKIni 0xc0000
++#define bAGCTxCode 0xc00000
++#define bAGCRxCode 0x300000
++
++#define b3WireDataLength 0x800 // Reg 0x820~84f rFPGA0_XA_HSSIParameter1
++#define b3WireAddressLength 0x400
++
++#define b3WireRFPowerDown 0x1 // Useless now
++//#define bHWSISelect 0x8
++#define b5GPAPEPolarity 0x40000000
++#define b2GPAPEPolarity 0x80000000
++#define bRFSW_TxDefaultAnt 0x3
++#define bRFSW_TxOptionAnt 0x30
++#define bRFSW_RxDefaultAnt 0x300
++#define bRFSW_RxOptionAnt 0x3000
++#define bRFSI_3WireData 0x1
++#define bRFSI_3WireClock 0x2
++#define bRFSI_3WireLoad 0x4
++#define bRFSI_3WireRW 0x8
++#define bRFSI_3Wire 0xf
++
++#define bRFSI_RFENV 0x10 // Reg 0x870 rFPGA0_XAB_RFInterfaceSW
++
++#define bRFSI_TRSW 0x20 // Useless now
++#define bRFSI_TRSWB 0x40
++#define bRFSI_ANTSW 0x100
++#define bRFSI_ANTSWB 0x200
++#define bRFSI_PAPE 0x400
++#define bRFSI_PAPE5G 0x800
++#define bBandSelect 0x1
++#define bHTSIG2_GI 0x80
++#define bHTSIG2_Smoothing 0x01
++#define bHTSIG2_Sounding 0x02
++#define bHTSIG2_Aggreaton 0x08
++#define bHTSIG2_STBC 0x30
++#define bHTSIG2_AdvCoding 0x40
++#define bHTSIG2_NumOfHTLTF 0x300
++#define bHTSIG2_CRC8 0x3fc
++#define bHTSIG1_MCS 0x7f
++#define bHTSIG1_BandWidth 0x80
++#define bHTSIG1_HTLength 0xffff
++#define bLSIG_Rate 0xf
++#define bLSIG_Reserved 0x10
++#define bLSIG_Length 0x1fffe
++#define bLSIG_Parity 0x20
++#define bCCKRxPhase 0x4
++#if (RTL92SE_FPGA_VERIFY == 1)
++#define bLSSIReadAddress 0x3f000000 //LSSI "Read" Address // Reg 0x824 rFPGA0_XA_HSSIParameter2
++#else
++#define bLSSIReadAddress 0x7f800000 // T65 RF
++#endif
++#define bLSSIReadEdge 0x80000000 //LSSI "Read" edge signal
++#if (RTL92SE_FPGA_VERIFY == 1)
++#define bLSSIReadBackData 0xfff // Reg 0x8a0 rFPGA0_XA_LSSIReadBack
++#else
++#define bLSSIReadBackData 0xfffff // T65 RF
++#endif
++#define bLSSIReadOKFlag 0x1000 // Useless now
++#define bCCKSampleRate 0x8 //0: 44MHz, 1:88MHz
++#define bRegulator0Standby 0x1
++#define bRegulatorPLLStandby 0x2
++#define bRegulator1Standby 0x4
++#define bPLLPowerUp 0x8
++#define bDPLLPowerUp 0x10
++#define bDA10PowerUp 0x20
++#define bAD7PowerUp 0x200
++#define bDA6PowerUp 0x2000
++#define bXtalPowerUp 0x4000
++#define b40MDClkPowerUP 0x8000
++#define bDA6DebugMode 0x20000
++#define bDA6Swing 0x380000
++
++#define bADClkPhase 0x4000000 // Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ
++
++#define b80MClkDelay 0x18000000 // Useless
++#define bAFEWatchDogEnable 0x20000000
++
++#define bXtalCap01 0xc0000000 // Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap
++#define bXtalCap23 0x3
++#define bXtalCap92x 0x0f000000
++#define bXtalCap 0x0f000000
++
++#define bIntDifClkEnable 0x400 // Useless
++#define bExtSigClkEnable 0x800
++#define bBandgapMbiasPowerUp 0x10000
++#define bAD11SHGain 0xc0000
++#define bAD11InputRange 0x700000
++#define bAD11OPCurrent 0x3800000
++#define bIPathLoopback 0x4000000
++#define bQPathLoopback 0x8000000
++#define bAFELoopback 0x10000000
++#define bDA10Swing 0x7e0
++#define bDA10Reverse 0x800
++#define bDAClkSource 0x1000
++#define bAD7InputRange 0x6000
++#define bAD7Gain 0x38000
++#define bAD7OutputCMMode 0x40000
++#define bAD7InputCMMode 0x380000
++#define bAD7Current 0xc00000
++#define bRegulatorAdjust 0x7000000
++#define bAD11PowerUpAtTx 0x1
++#define bDA10PSAtTx 0x10
++#define bAD11PowerUpAtRx 0x100
++#define bDA10PSAtRx 0x1000
++#define bCCKRxAGCFormat 0x200
++#define bPSDFFTSamplepPoint 0xc000
++#define bPSDAverageNum 0x3000
++#define bIQPathControl 0xc00
++#define bPSDFreq 0x3ff
++#define bPSDAntennaPath 0x30
++#define bPSDIQSwitch 0x40
++#define bPSDRxTrigger 0x400000
++#define bPSDTxTrigger 0x80000000
++#define bPSDSineToneScale 0x7f000000
++#define bPSDReport 0xffff
++
++// 3. Page9(0x900)
++#define bOFDMTxSC 0x30000000 // Useless
++#define bCCKTxOn 0x1
++#define bOFDMTxOn 0x2
++#define bDebugPage 0xfff //reset debug page and also HWord, LWord
++#define bDebugItem 0xff //reset debug page and LWord
++#define bAntL 0x10
++#define bAntNonHT 0x100
++#define bAntHT1 0x1000
++#define bAntHT2 0x10000
++#define bAntHT1S1 0x100000
++#define bAntNonHTS1 0x1000000
++
++// 4. PageA(0xA00)
++#define bCCKBBMode 0x3 // Useless
++#define bCCKTxPowerSaving 0x80
++#define bCCKRxPowerSaving 0x40
++
++#define bCCKSideBand 0x10 // Reg 0xa00 rCCK0_System 20/40 switch
++
++#define bCCKScramble 0x8 // Useless
++#define bCCKAntDiversity 0x8000
++#define bCCKCarrierRecovery 0x4000
++#define bCCKTxRate 0x3000
++#define bCCKDCCancel 0x0800
++#define bCCKISICancel 0x0400
++#define bCCKMatchFilter 0x0200
++#define bCCKEqualizer 0x0100
++#define bCCKPreambleDetect 0x800000
++#define bCCKFastFalseCCA 0x400000
++#define bCCKChEstStart 0x300000
++#define bCCKCCACount 0x080000
++#define bCCKcs_lim 0x070000
++#define bCCKBistMode 0x80000000
++#define bCCKCCAMask 0x40000000
++#define bCCKTxDACPhase 0x4
++#define bCCKRxADCPhase 0x20000000 //r_rx_clk
++#define bCCKr_cp_mode0 0x0100
++#define bCCKTxDCOffset 0xf0
++#define bCCKRxDCOffset 0xf
++#define bCCKCCAMode 0xc000
++#define bCCKFalseCS_lim 0x3f00
++#define bCCKCS_ratio 0xc00000
++#define bCCKCorgBit_sel 0x300000
++#define bCCKPD_lim 0x0f0000
++#define bCCKNewCCA 0x80000000
++#define bCCKRxHPofIG 0x8000
++#define bCCKRxIG 0x7f00
++#define bCCKLNAPolarity 0x800000
++#define bCCKRx1stGain 0x7f0000
++#define bCCKRFExtend 0x20000000 //CCK Rx Iinital gain polarity
++#define bCCKRxAGCSatLevel 0x1f000000
++#define bCCKRxAGCSatCount 0xe0
++#define bCCKRxRFSettle 0x1f //AGCsamp_dly
++#define bCCKFixedRxAGC 0x8000
++//#define bCCKRxAGCFormat 0x4000 //remove to HSSI register 0x824
++#define bCCKAntennaPolarity 0x2000
++#define bCCKTxFilterType 0x0c00
++#define bCCKRxAGCReportType 0x0300
++#define bCCKRxDAGCEn 0x80000000
++#define bCCKRxDAGCPeriod 0x20000000
++#define bCCKRxDAGCSatLevel 0x1f000000
++#define bCCKTimingRecovery 0x800000
++#define bCCKTxC0 0x3f0000
++#define bCCKTxC1 0x3f000000
++#define bCCKTxC2 0x3f
++#define bCCKTxC3 0x3f00
++#define bCCKTxC4 0x3f0000
++#define bCCKTxC5 0x3f000000
++#define bCCKTxC6 0x3f
++#define bCCKTxC7 0x3f00
++#define bCCKDebugPort 0xff0000
++#define bCCKDACDebug 0x0f000000
++#define bCCKFalseAlarmEnable 0x8000
++#define bCCKFalseAlarmRead 0x4000
++#define bCCKTRSSI 0x7f
++#define bCCKRxAGCReport 0xfe
++#define bCCKRxReport_AntSel 0x80000000
++#define bCCKRxReport_MFOff 0x40000000
++#define bCCKRxRxReport_SQLoss 0x20000000
++#define bCCKRxReport_Pktloss 0x10000000
++#define bCCKRxReport_Lockedbit 0x08000000
++#define bCCKRxReport_RateError 0x04000000
++#define bCCKRxReport_RxRate 0x03000000
++#define bCCKRxFACounterLower 0xff
++#define bCCKRxFACounterUpper 0xff000000
++#define bCCKRxHPAGCStart 0xe000
++#define bCCKRxHPAGCFinal 0x1c00
++#define bCCKRxFalseAlarmEnable 0x8000
++#define bCCKFACounterFreeze 0x4000
++#define bCCKTxPathSel 0x10000000
++#define bCCKDefaultRxPath 0xc000000
++#define bCCKOptionRxPath 0x3000000
++
++// 5. PageC(0xC00)
++#define bNumOfSTF 0x3 // Useless
++#define bShift_L 0xc0
++#define bGI_TH 0xc
++#define bRxPathA 0x1
++#define bRxPathB 0x2
++#define bRxPathC 0x4
++#define bRxPathD 0x8
++#define bTxPathA 0x1
++#define bTxPathB 0x2
++#define bTxPathC 0x4
++#define bTxPathD 0x8
++#define bTRSSIFreq 0x200
++#define bADCBackoff 0x3000
++#define bDFIRBackoff 0xc000
++#define bTRSSILatchPhase 0x10000
++#define bRxIDCOffset 0xff
++#define bRxQDCOffset 0xff00
++#define bRxDFIRMode 0x1800000
++#define bRxDCNFType 0xe000000
++#define bRXIQImb_A 0x3ff
++#define bRXIQImb_B 0xfc00
++#define bRXIQImb_C 0x3f0000
++#define bRXIQImb_D 0xffc00000
++#define bDC_dc_Notch 0x60000
++#define bRxNBINotch 0x1f000000
++#define bPD_TH 0xf
++#define bPD_TH_Opt2 0xc000
++#define bPWED_TH 0x700
++#define bIfMF_Win_L 0x800
++#define bPD_Option 0x1000
++#define bMF_Win_L 0xe000
++#define bBW_Search_L 0x30000
++#define bwin_enh_L 0xc0000
++#define bBW_TH 0x700000
++#define bED_TH2 0x3800000
++#define bBW_option 0x4000000
++#define bRatio_TH 0x18000000
++#define bWindow_L 0xe0000000
++#define bSBD_Option 0x1
++#define bFrame_TH 0x1c
++#define bFS_Option 0x60
++#define bDC_Slope_check 0x80
++#define bFGuard_Counter_DC_L 0xe00
++#define bFrame_Weight_Short 0x7000
++#define bSub_Tune 0xe00000
++#define bFrame_DC_Length 0xe000000
++#define bSBD_start_offset 0x30000000
++#define bFrame_TH_2 0x7
++#define bFrame_GI2_TH 0x38
++#define bGI2_Sync_en 0x40
++#define bSarch_Short_Early 0x300
++#define bSarch_Short_Late 0xc00
++#define bSarch_GI2_Late 0x70000
++#define bCFOAntSum 0x1
++#define bCFOAcc 0x2
++#define bCFOStartOffset 0xc
++#define bCFOLookBack 0x70
++#define bCFOSumWeight 0x80
++#define bDAGCEnable 0x10000
++#define bTXIQImb_A 0x3ff
++#define bTXIQImb_B 0xfc00
++#define bTXIQImb_C 0x3f0000
++#define bTXIQImb_D 0xffc00000
++#define bTxIDCOffset 0xff
++#define bTxQDCOffset 0xff00
++#define bTxDFIRMode 0x10000
++#define bTxPesudoNoiseOn 0x4000000
++#define bTxPesudoNoise_A 0xff
++#define bTxPesudoNoise_B 0xff00
++#define bTxPesudoNoise_C 0xff0000
++#define bTxPesudoNoise_D 0xff000000
++#define bCCADropOption 0x20000
++#define bCCADropThres 0xfff00000
++#define bEDCCA_H 0xf
++#define bEDCCA_L 0xf0
++#define bLambda_ED 0x300
++#define bRxInitialGain 0x7f
++#define bRxAntDivEn 0x80
++#define bRxAGCAddressForLNA 0x7f00
++#define bRxHighPowerFlow 0x8000
++#define bRxAGCFreezeThres 0xc0000
++#define bRxFreezeStep_AGC1 0x300000
++#define bRxFreezeStep_AGC2 0xc00000
++#define bRxFreezeStep_AGC3 0x3000000
++#define bRxFreezeStep_AGC0 0xc000000
++#define bRxRssi_Cmp_En 0x10000000
++#define bRxQuickAGCEn 0x20000000
++#define bRxAGCFreezeThresMode 0x40000000
++#define bRxOverFlowCheckType 0x80000000
++#define bRxAGCShift 0x7f
++#define bTRSW_Tri_Only 0x80
++#define bPowerThres 0x300
++#define bRxAGCEn 0x1
++#define bRxAGCTogetherEn 0x2
++#define bRxAGCMin 0x4
++#define bRxHP_Ini 0x7
++#define bRxHP_TRLNA 0x70
++#define bRxHP_RSSI 0x700
++#define bRxHP_BBP1 0x7000
++#define bRxHP_BBP2 0x70000
++#define bRxHP_BBP3 0x700000
++#define bRSSI_H 0x7f0000 //the threshold for high power
++#define bRSSI_Gen 0x7f000000 //the threshold for ant diversity
++#define bRxSettle_TRSW 0x7
++#define bRxSettle_LNA 0x38
++#define bRxSettle_RSSI 0x1c0
++#define bRxSettle_BBP 0xe00
++#define bRxSettle_RxHP 0x7000
++#define bRxSettle_AntSW_RSSI 0x38000
++#define bRxSettle_AntSW 0xc0000
++#define bRxProcessTime_DAGC 0x300000
++#define bRxSettle_HSSI 0x400000
++#define bRxProcessTime_BBPPW 0x800000
++#define bRxAntennaPowerShift 0x3000000
++#define bRSSITableSelect 0xc000000
++#define bRxHP_Final 0x7000000
++#define bRxHTSettle_BBP 0x7
++#define bRxHTSettle_HSSI 0x8
++#define bRxHTSettle_RxHP 0x70
++#define bRxHTSettle_BBPPW 0x80
++#define bRxHTSettle_Idle 0x300
++#define bRxHTSettle_Reserved 0x1c00
++#define bRxHTRxHPEn 0x8000
++#define bRxHTAGCFreezeThres 0x30000
++#define bRxHTAGCTogetherEn 0x40000
++#define bRxHTAGCMin 0x80000
++#define bRxHTAGCEn 0x100000
++#define bRxHTDAGCEn 0x200000
++#define bRxHTRxHP_BBP 0x1c00000
++#define bRxHTRxHP_Final 0xe0000000
++#define bRxPWRatioTH 0x3
++#define bRxPWRatioEn 0x4
++#define bRxMFHold 0x3800
++#define bRxPD_Delay_TH1 0x38
++#define bRxPD_Delay_TH2 0x1c0
++#define bRxPD_DC_COUNT_MAX 0x600
++//#define bRxMF_Hold 0x3800
++#define bRxPD_Delay_TH 0x8000
++#define bRxProcess_Delay 0xf0000
++#define bRxSearchrange_GI2_Early 0x700000
++#define bRxFrame_Guard_Counter_L 0x3800000
++#define bRxSGI_Guard_L 0xc000000
++#define bRxSGI_Search_L 0x30000000
++#define bRxSGI_TH 0xc0000000
++#define bDFSCnt0 0xff
++#define bDFSCnt1 0xff00
++#define bDFSFlag 0xf0000
++#define bMFWeightSum 0x300000
++#define bMinIdxTH 0x7f000000
++#define bDAFormat 0x40000
++#define bTxChEmuEnable 0x01000000
++#define bTRSWIsolation_A 0x7f
++#define bTRSWIsolation_B 0x7f00
++#define bTRSWIsolation_C 0x7f0000
++#define bTRSWIsolation_D 0x7f000000
++#define bExtLNAGain 0x7c00
++
++// 6. PageE(0xE00)
++#define bSTBCEn 0x4 // Useless
++#define bAntennaMapping 0x10
++#define bNss 0x20
++#define bCFOAntSumD 0x200
++#define bPHYCounterReset 0x8000000
++#define bCFOReportGet 0x4000000
++#define bOFDMContinueTx 0x10000000
++#define bOFDMSingleCarrier 0x20000000
++#define bOFDMSingleTone 0x40000000
++//#define bRxPath1 0x01
++//#define bRxPath2 0x02
++//#define bRxPath3 0x04
++//#define bRxPath4 0x08
++//#define bTxPath1 0x10
++//#define bTxPath2 0x20
++#define bHTDetect 0x100
++#define bCFOEn 0x10000
++#define bCFOValue 0xfff00000
++#define bSigTone_Re 0x3f
++#define bSigTone_Im 0x7f00
++#define bCounter_CCA 0xffff
++#define bCounter_ParityFail 0xffff0000
++#define bCounter_RateIllegal 0xffff
++#define bCounter_CRC8Fail 0xffff0000
++#define bCounter_MCSNoSupport 0xffff
++#define bCounter_FastSync 0xffff
++#define bShortCFO 0xfff
++#define bShortCFOTLength 12 //total
++#define bShortCFOFLength 11 //fraction
++#define bLongCFO 0x7ff
++#define bLongCFOTLength 11
++#define bLongCFOFLength 11
++#define bTailCFO 0x1fff
++#define bTailCFOTLength 13
++#define bTailCFOFLength 12
++#define bmax_en_pwdB 0xffff
++#define bCC_power_dB 0xffff0000
++#define bnoise_pwdB 0xffff
++#define bPowerMeasTLength 10
++#define bPowerMeasFLength 3
++#define bRx_HT_BW 0x1
++#define bRxSC 0x6
++#define bRx_HT 0x8
++#define bNB_intf_det_on 0x1
++#define bIntf_win_len_cfg 0x30
++#define bNB_Intf_TH_cfg 0x1c0
++#define bRFGain 0x3f
++#define bTableSel 0x40
++#define bTRSW 0x80
++#define bRxSNR_A 0xff
++#define bRxSNR_B 0xff00
++#define bRxSNR_C 0xff0000
++#define bRxSNR_D 0xff000000
++#define bSNREVMTLength 8
++#define bSNREVMFLength 1
++#define bCSI1st 0xff
++#define bCSI2nd 0xff00
++#define bRxEVM1st 0xff0000
++#define bRxEVM2nd 0xff000000
++#define bSIGEVM 0xff
++#define bPWDB 0xff00
++#define bSGIEN 0x10000
++
++#define bSFactorQAM1 0xf // Useless
++#define bSFactorQAM2 0xf0
++#define bSFactorQAM3 0xf00
++#define bSFactorQAM4 0xf000
++#define bSFactorQAM5 0xf0000
++#define bSFactorQAM6 0xf0000
++#define bSFactorQAM7 0xf00000
++#define bSFactorQAM8 0xf000000
++#define bSFactorQAM9 0xf0000000
++#define bCSIScheme 0x100000
++
++#define bNoiseLvlTopSet 0x3 // Useless
++#define bChSmooth 0x4
++#define bChSmoothCfg1 0x38
++#define bChSmoothCfg2 0x1c0
++#define bChSmoothCfg3 0xe00
++#define bChSmoothCfg4 0x7000
++#define bMRCMode 0x800000
++#define bTHEVMCfg 0x7000000
++
++#define bLoopFitType 0x1 // Useless
++#define bUpdCFO 0x40
++#define bUpdCFOOffData 0x80
++#define bAdvUpdCFO 0x100
++#define bAdvTimeCtrl 0x800
++#define bUpdClko 0x1000
++#define bFC 0x6000
++#define bTrackingMode 0x8000
++#define bPhCmpEnable 0x10000
++#define bUpdClkoLTF 0x20000
++#define bComChCFO 0x40000
++#define bCSIEstiMode 0x80000
++#define bAdvUpdEqz 0x100000
++#define bUChCfg 0x7000000
++#define bUpdEqz 0x8000000
++
++#define bTxAGCRate18_06 0x7f7f7f7f // Useless
++#define bTxAGCRate54_24 0x7f7f7f7f
++#define bTxAGCRateMCS32 0x7f
++#define bTxAGCRateCCK 0x7f00
++#define bTxAGCRateMCS3_MCS0 0x7f7f7f7f
++#define bTxAGCRateMCS7_MCS4 0x7f7f7f7f
++#define bTxAGCRateMCS11_MCS8 0x7f7f7f7f
++#define bTxAGCRateMCS15_MCS12 0x7f7f7f7f
++
++//Rx Pseduo noise
++#define bRxPesudoNoiseOn 0x20000000 // Useless
++#define bRxPesudoNoise_A 0xff
++#define bRxPesudoNoise_B 0xff00
++#define bRxPesudoNoise_C 0xff0000
++#define bRxPesudoNoise_D 0xff000000
++#define bPesudoNoiseState_A 0xffff
++#define bPesudoNoiseState_B 0xffff0000
++#define bPesudoNoiseState_C 0xffff
++#define bPesudoNoiseState_D 0xffff0000
++
++//7. RF Register
++//Zebra1
++#define bZebra1_HSSIEnable 0x8 // Useless
++#define bZebra1_TRxControl 0xc00
++#define bZebra1_TRxGainSetting 0x07f
++#define bZebra1_RxCorner 0xc00
++#define bZebra1_TxChargePump 0x38
++#define bZebra1_RxChargePump 0x7
++#define bZebra1_ChannelNum 0xf80
++#define bZebra1_TxLPFBW 0x400
++#define bZebra1_RxLPFBW 0x600
++
++//Zebra4
++#define bRTL8256RegModeCtrl1 0x100 // Useless
++#define bRTL8256RegModeCtrl0 0x40
++#define bRTL8256_TxLPFBW 0x18
++#define bRTL8256_RxLPFBW 0x600
++
++//RTL8258
++#define bRTL8258_TxLPFBW 0xc // Useless
++#define bRTL8258_RxLPFBW 0xc00
++#define bRTL8258_RSSILPFBW 0xc0
++
++
++//
++// Other Definition
++//
++
++//byte endable for sb_write
++#define bByte0 0x1 // Useless
++#define bByte1 0x2
++#define bByte2 0x4
++#define bByte3 0x8
++#define bWord0 0x3
++#define bWord1 0xc
++#define bDWord 0xf
++
++//for PutRegsetting & GetRegSetting BitMask
++#define bMaskByte0 0xff // Reg 0xc50 rOFDM0_XAAGCCore~0xC6f
++#define bMaskByte1 0xff00
++#define bMaskByte2 0xff0000
++#define bMaskByte3 0xff000000
++#define bMaskHWord 0xffff0000
++#define bMaskLWord 0x0000ffff
++#define bMaskDWord 0xffffffff
++#define bMaskH4Bits 0xf0000000
++#define bMaskOFDM_D 0xffc00000
++#define bMaskCCK 0x3f3f3f3f
++#define bMask12Bits 0xfff
++
++//for PutRFRegsetting & GetRFRegSetting BitMask
++#if (RTL92SE_FPGA_VERIFY == 1)
++//#define bMask12Bits 0xfff // RF Reg mask bits
++//#define bMask20Bits 0xfff // RF Reg mask bits T65 RF
++#define bRFRegOffsetMask 0xfff
++#else
++//#define bMask12Bits 0xfffff // RF Reg mask bits
++//#define bMask20Bits 0xfffff // RF Reg mask bits T65 RF
++#define bRFRegOffsetMask 0xfffff
++#endif
++#define bEnable 0x1 // Useless
++#define bDisable 0x0
++
++#define LeftAntenna 0x0 // Useless
++#define RightAntenna 0x1
++
++#define tCheckTxStatus 500 //500ms // Useless
++#define tUpdateRxCounter 100 //100ms
++
++#define rateCCK 0 // Useless
++#define rateOFDM 1
++#define rateHT 2
++
++//define Register-End
++#define bPMAC_End 0x1ff // Useless
++#define bFPGAPHY0_End 0x8ff
++#define bFPGAPHY1_End 0x9ff
++#define bCCKPHY0_End 0xaff
++#define bOFDMPHY0_End 0xcff
++#define bOFDMPHY1_End 0xdff
++
++//define max debug item in each debug page
++//#define bMaxItem_FPGA_PHY0 0x9
++//#define bMaxItem_FPGA_PHY1 0x3
++//#define bMaxItem_PHY_11B 0x16
++//#define bMaxItem_OFDM_PHY0 0x29
++//#define bMaxItem_OFDM_PHY1 0x0
++
++#define bPMACControl 0x0 // Useless
++#define bWMACControl 0x1
++#define bWNICControl 0x2
++
++#if 0
++#define ANTENNA_A 0x1 // Useless
++#define ANTENNA_B 0x2
++#define ANTENNA_AB 0x3 // ANTENNA_A|ANTENNA_B
++
++#define ANTENNA_C 0x4
++#define ANTENNA_D 0x8
++#endif
++
++#define RCR_AAP BIT(0) // accept all physical address
++#define RCR_APM BIT(1) // accept physical match
++#define RCR_AM BIT(2) // accept multicast
++#define RCR_AB BIT(3) // accept broadcast
++#define RCR_ACRC32 BIT(5) // accept error packet
++#define RCR_9356SEL BIT(6)
++#define RCR_AICV BIT(12) // Accept ICV error packet
++#define RCR_RXFTH0 (BIT(13)|BIT(14)|BIT(15)) // Rx FIFO threshold
++#define RCR_ADF BIT(18) // Accept Data(frame type) frame
++#define RCR_ACF BIT(19) // Accept control frame
++#define RCR_AMF BIT(20) // Accept management frame
++#define RCR_ADD3 BIT(21)
++#define RCR_APWRMGT BIT(22) // Accept power management packet
++#define RCR_CBSSID BIT(23) // Accept BSSID match packet
++#define RCR_ENMARP BIT(28) // enable mac auto reset phy
++#define RCR_EnCS1 BIT(29) // enable carrier sense method 1
++#define RCR_EnCS2 BIT(30) // enable carrier sense method 2
++#define RCR_OnlyErlPkt BIT(31) // Rx Early mode is performed for packet size greater than 1536
++
++/*--------------------------Define Parameters-------------------------------*/
++
++
++#endif //__INC_HAL8192SPHYREG_H
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtw_p2p.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtw_p2p.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtw_p2p.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtw_p2p.h 2015-07-28 01:20:58.321597318 +0200
+@@ -0,0 +1,160 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef __RTW_P2P_H_
++#define __RTW_P2P_H_
++
++#include <drv_types.h>
++
++u32 build_beacon_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);
++u32 build_probe_resp_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);
++u32 build_prov_disc_request_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, u8* pssid, u8 ussidlen, u8* pdev_raddr );
++u32 build_assoc_resp_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, u8 status_code);
++u32 build_deauth_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);
++#ifdef CONFIG_WFD
++u32 build_probe_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);
++u32 build_probe_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, u8 tunneled);
++u32 build_beacon_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);
++u32 build_nego_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);
++u32 build_nego_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);
++u32 build_nego_confirm_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);
++u32 build_invitation_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);
++u32 build_invitation_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);
++u32 build_assoc_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);
++u32 build_assoc_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);
++u32 build_provdisc_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);
++u32 build_provdisc_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);
++#endif //CONFIG_WFD
++
++u32 process_probe_req_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pframe, uint len);
++u32 process_assoc_req_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pframe, uint len, struct sta_info *psta);
++u32 process_p2p_devdisc_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint len);
++u32 process_p2p_devdisc_resp(struct wifidirect_info *pwdinfo, u8 *pframe, uint len);
++u8 process_p2p_provdisc_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint len);
++u8 process_p2p_provdisc_resp(struct wifidirect_info *pwdinfo, u8 *pframe);
++u8 process_p2p_group_negotation_req( struct wifidirect_info *pwdinfo, u8 *pframe, uint len );
++u8 process_p2p_group_negotation_resp( struct wifidirect_info *pwdinfo, u8 *pframe, uint len );
++u8 process_p2p_group_negotation_confirm( struct wifidirect_info *pwdinfo, u8 *pframe, uint len );
++u8 process_p2p_presence_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint len);
++
++void p2p_protocol_wk_hdl(_adapter *padapter, int intCmdType);
++
++#ifdef CONFIG_P2P_PS
++void process_p2p_ps_ie(PADAPTER padapter, u8 *IEs, u32 IELength);
++void p2p_ps_wk_hdl(_adapter *padapter, u8 p2p_ps_state);
++u8 p2p_ps_wk_cmd(_adapter*padapter, u8 p2p_ps_state, u8 enqueue);
++#endif // CONFIG_P2P_PS
++
++#ifdef CONFIG_IOCTL_CFG80211
++void rtw_init_cfg80211_wifidirect_info( _adapter* padapter);
++int rtw_p2p_check_frames(_adapter *padapter, const u8 *buf, u32 len, u8 tx);
++void rtw_append_wfd_ie(_adapter *padapter, u8 *buf, u32 *len);
++#endif //CONFIG_IOCTL_CFG80211
++
++void reset_global_wifidirect_info( _adapter* padapter );
++int rtw_init_wifi_display_info(_adapter* padapter);
++void rtw_init_wifidirect_timers(_adapter* padapter);
++void rtw_init_wifidirect_addrs(_adapter* padapter, u8 *dev_addr, u8 *iface_addr);
++void init_wifidirect_info( _adapter* padapter, enum P2P_ROLE role);
++int rtw_p2p_enable(_adapter *padapter, enum P2P_ROLE role);
++
++static inline void _rtw_p2p_set_state(struct wifidirect_info *wdinfo, enum P2P_STATE state)
++{
++ if(wdinfo->p2p_state != state) {
++ //wdinfo->pre_p2p_state = wdinfo->p2p_state;
++ wdinfo->p2p_state = state;
++ }
++}
++static inline void _rtw_p2p_set_pre_state(struct wifidirect_info *wdinfo, enum P2P_STATE state)
++{
++ if(wdinfo->pre_p2p_state != state) {
++ wdinfo->pre_p2p_state = state;
++ }
++}
++#if 0
++static inline void _rtw_p2p_restore_state(struct wifidirect_info *wdinfo)
++{
++ if(wdinfo->pre_p2p_state != -1) {
++ wdinfo->p2p_state = wdinfo->pre_p2p_state;
++ wdinfo->pre_p2p_state = -1;
++ }
++}
++#endif
++static inline void _rtw_p2p_set_role(struct wifidirect_info *wdinfo, enum P2P_ROLE role)
++{
++ if(wdinfo->role != role) {
++ wdinfo->role = role;
++ }
++}
++static inline int _rtw_p2p_state(struct wifidirect_info *wdinfo)
++{
++ return wdinfo->p2p_state;
++}
++static inline int _rtw_p2p_pre_state(struct wifidirect_info *wdinfo)
++{
++ return wdinfo->pre_p2p_state;
++}
++static inline int _rtw_p2p_role(struct wifidirect_info *wdinfo)
++{
++ return wdinfo->role;
++}
++static inline bool _rtw_p2p_chk_state(struct wifidirect_info *wdinfo, enum P2P_STATE state)
++{
++ return wdinfo->p2p_state == state;
++}
++static inline bool _rtw_p2p_chk_role(struct wifidirect_info *wdinfo, enum P2P_ROLE role)
++{
++ return wdinfo->role == role;
++}
++
++#ifdef CONFIG_DBG_P2P
++void dbg_rtw_p2p_set_state(struct wifidirect_info *wdinfo, enum P2P_STATE state, const char *caller, int line);
++void dbg_rtw_p2p_set_pre_state(struct wifidirect_info *wdinfo, enum P2P_STATE state, const char *caller, int line);
++//void dbg_rtw_p2p_restore_state(struct wifidirect_info *wdinfo, const char *caller, int line);
++void dbg_rtw_p2p_set_role(struct wifidirect_info *wdinfo, enum P2P_ROLE role, const char *caller, int line);
++#define rtw_p2p_set_state(wdinfo, state) dbg_rtw_p2p_set_state(wdinfo, state, __FUNCTION__, __LINE__)
++#define rtw_p2p_set_pre_state(wdinfo, state) dbg_rtw_p2p_set_pre_state(wdinfo, state, __FUNCTION__, __LINE__)
++#define rtw_p2p_set_role(wdinfo, role) dbg_rtw_p2p_set_role(wdinfo, role, __FUNCTION__, __LINE__)
++//#define rtw_p2p_restore_state(wdinfo) dbg_rtw_p2p_restore_state(wdinfo, __FUNCTION__, __LINE__)
++#else //CONFIG_DBG_P2P
++#define rtw_p2p_set_state(wdinfo, state) _rtw_p2p_set_state(wdinfo, state)
++#define rtw_p2p_set_pre_state(wdinfo, state) _rtw_p2p_set_pre_state(wdinfo, state)
++#define rtw_p2p_set_role(wdinfo, role) _rtw_p2p_set_role(wdinfo, role)
++//#define rtw_p2p_restore_state(wdinfo) _rtw_p2p_restore_state(wdinfo)
++#endif //CONFIG_DBG_P2P
++
++#define rtw_p2p_state(wdinfo) _rtw_p2p_state(wdinfo)
++#define rtw_p2p_pre_state(wdinfo) _rtw_p2p_pre_state(wdinfo)
++#define rtw_p2p_role(wdinfo) _rtw_p2p_role(wdinfo)
++#define rtw_p2p_chk_state(wdinfo, state) _rtw_p2p_chk_state(wdinfo, state)
++#define rtw_p2p_chk_role(wdinfo, role) _rtw_p2p_chk_role(wdinfo, role)
++
++#define rtw_p2p_findphase_ex_set(wdinfo, value) \
++ (wdinfo)->find_phase_state_exchange_cnt = (value)
++
++//is this find phase exchange for social channel scan?
++#define rtw_p2p_findphase_ex_is_social(wdinfo) \
++ (wdinfo)->find_phase_state_exchange_cnt >= P2P_FINDPHASE_EX_SOCIAL_FIRST
++
++//should we need find phase exchange anymore?
++#define rtw_p2p_findphase_ex_is_needed(wdinfo) \
++ ((wdinfo)->find_phase_state_exchange_cnt < P2P_FINDPHASE_EX_MAX && \
++ (wdinfo)->find_phase_state_exchange_cnt != P2P_FINDPHASE_EX_NONE)
++
++#endif
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtw_pwrctrl.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtw_pwrctrl.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtw_pwrctrl.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtw_pwrctrl.h 2015-07-28 01:20:58.321597318 +0200
+@@ -0,0 +1,362 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef __RTW_PWRCTRL_H_
++#define __RTW_PWRCTRL_H_
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++
++#ifdef CONFIG_HAS_EARLYSUSPEND
++#include <linux/earlysuspend.h>
++#endif //CONFIG_HAS_EARLYSUSPEND
++
++
++#define FW_PWR0 0
++#define FW_PWR1 1
++#define FW_PWR2 2
++#define FW_PWR3 3
++
++
++#define HW_PWR0 7
++#define HW_PWR1 6
++#define HW_PWR2 2
++#define HW_PWR3 0
++#define HW_PWR4 8
++
++#define FW_PWRMSK 0x7
++
++
++#define XMIT_ALIVE BIT(0)
++#define RECV_ALIVE BIT(1)
++#define CMD_ALIVE BIT(2)
++#define EVT_ALIVE BIT(3)
++
++
++enum Power_Mgnt
++{
++ PS_MODE_ACTIVE = 0 ,
++ PS_MODE_MIN ,
++ PS_MODE_MAX ,
++ PS_MODE_DTIM ,
++ PS_MODE_VOIP ,
++ PS_MODE_UAPSD_WMM ,
++ PS_MODE_UAPSD ,
++ PS_MODE_IBSS ,
++ PS_MODE_WWLAN ,
++ PM_Radio_Off ,
++ PM_Card_Disable ,
++ PS_MODE_NUM
++};
++
++
++/*
++ BIT[2:0] = HW state
++ BIT[3] = Protocol PS state, 0: register active state , 1: register sleep state
++ BIT[4] = sub-state
++*/
++
++#define PS_DPS BIT(0)
++#define PS_LCLK (PS_DPS)
++#define PS_RF_OFF BIT(1)
++#define PS_ALL_ON BIT(2)
++#define PS_ST_ACTIVE BIT(3)
++
++#define PS_ISR_ENABLE BIT(4)
++#define PS_IMR_ENABLE BIT(5)
++#define PS_ACK BIT(6)
++#define PS_TOGGLE BIT(7)
++
++#define PS_STATE_MASK (0x0F)
++#define PS_STATE_HW_MASK (0x07)
++#define PS_SEQ_MASK (0xc0)
++
++#define PS_STATE(x) (PS_STATE_MASK & (x))
++#define PS_STATE_HW(x) (PS_STATE_HW_MASK & (x))
++#define PS_SEQ(x) (PS_SEQ_MASK & (x))
++
++#define PS_STATE_S0 (PS_DPS)
++#define PS_STATE_S1 (PS_LCLK)
++#define PS_STATE_S2 (PS_RF_OFF)
++#define PS_STATE_S3 (PS_ALL_ON)
++#define PS_STATE_S4 ((PS_ST_ACTIVE) | (PS_ALL_ON))
++
++
++#define PS_IS_RF_ON(x) ((x) & (PS_ALL_ON))
++#define PS_IS_ACTIVE(x) ((x) & (PS_ST_ACTIVE))
++#define CLR_PS_STATE(x) ((x) = ((x) & (0xF0)))
++
++
++struct reportpwrstate_parm {
++ unsigned char mode;
++ unsigned char state; //the CPWM value
++ unsigned short rsvd;
++};
++
++
++typedef _sema _pwrlock;
++
++
++__inline static void _init_pwrlock(_pwrlock *plock)
++{
++ _rtw_init_sema(plock, 1);
++}
++
++__inline static void _free_pwrlock(_pwrlock *plock)
++{
++ _rtw_free_sema(plock);
++}
++
++
++__inline static void _enter_pwrlock(_pwrlock *plock)
++{
++ _rtw_down_sema(plock);
++}
++
++
++__inline static void _exit_pwrlock(_pwrlock *plock)
++{
++ _rtw_up_sema(plock);
++}
++
++#define LPS_DELAY_TIME 1*HZ // 1 sec
++
++#define EXE_PWR_NONE 0x01
++#define EXE_PWR_IPS 0x02
++#define EXE_PWR_LPS 0x04
++
++// RF state.
++typedef enum _rt_rf_power_state
++{
++ rf_on, // RF is on after RFSleep or RFOff
++ rf_sleep, // 802.11 Power Save mode
++ rf_off, // HW/SW Radio OFF or Inactive Power Save
++ //=====Add the new RF state above this line=====//
++ rf_max
++}rt_rf_power_state;
++
++// RF Off Level for IPS or HW/SW radio off
++#define RT_RF_OFF_LEVL_ASPM BIT(0) // PCI ASPM
++#define RT_RF_OFF_LEVL_CLK_REQ BIT(1) // PCI clock request
++#define RT_RF_OFF_LEVL_PCI_D3 BIT(2) // PCI D3 mode
++#define RT_RF_OFF_LEVL_HALT_NIC BIT(3) // NIC halt, re-initialize hw parameters
++#define RT_RF_OFF_LEVL_FREE_FW BIT(4) // FW free, re-download the FW
++#define RT_RF_OFF_LEVL_FW_32K BIT(5) // FW in 32k
++#define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6) // Always enable ASPM and Clock Req in initialization.
++#define RT_RF_LPS_DISALBE_2R BIT(30) // When LPS is on, disable 2R if no packet is received or transmittd.
++#define RT_RF_LPS_LEVEL_ASPM BIT(31) // LPS with ASPM
++
++#define RT_IN_PS_LEVEL(ppsc, _PS_FLAG) ((ppsc->cur_ps_level & _PS_FLAG) ? _TRUE : _FALSE)
++#define RT_CLEAR_PS_LEVEL(ppsc, _PS_FLAG) (ppsc->cur_ps_level &= (~(_PS_FLAG)))
++#define RT_SET_PS_LEVEL(ppsc, _PS_FLAG) (ppsc->cur_ps_level |= _PS_FLAG)
++
++
++enum _PS_BBRegBackup_ {
++ PSBBREG_RF0 = 0,
++ PSBBREG_RF1,
++ PSBBREG_RF2,
++ PSBBREG_AFE0,
++ PSBBREG_TOTALCNT
++};
++
++enum { // for ips_mode
++ IPS_NONE=0,
++ IPS_NORMAL,
++ IPS_LEVEL_2,
++};
++
++struct pwrctrl_priv
++{
++ _pwrlock lock;
++ volatile u8 rpwm; // requested power state for fw
++ volatile u8 cpwm; // fw current power state. updated when 1. read from HCPWM 2. driver lowers power level
++ volatile u8 tog; // toggling
++ volatile u8 cpwm_tog; // toggling
++ u8 pwr_mode;
++ u8 smart_ps;
++ u32 alives;
++
++ u8 b_hw_radio_off;
++ u8 reg_rfoff;
++ u8 reg_pdnmode; //powerdown mode
++ u32 rfoff_reason;
++
++ //RF OFF Level
++ u32 cur_ps_level;
++ u32 reg_rfps_level;
++
++
++
++#ifdef CONFIG_PCI_HCI
++ //just for PCIE ASPM
++ u8 b_support_aspm; // If it supports ASPM, Offset[560h] = 0x40, otherwise Offset[560h] = 0x00.
++ u8 b_support_backdoor;
++
++ //just for PCIE ASPM
++ u8 const_amdpci_aspm;
++#endif
++
++ uint ips_enter_cnts;
++ uint ips_leave_cnts;
++
++ u8 ips_mode;
++ u8 ips_mode_req; // used to accept the mode setting request, will update to ipsmode later
++ uint bips_processing;
++ u32 ips_deny_time; /* will deny IPS when system time is smaller than this */
++ u8 ps_processing; /* temporarily used to mark whether in rtw_ps_processor */
++
++ u8 bLeisurePs;
++ u8 LpsIdleCount;
++ u8 power_mgnt;
++ u8 bFwCurrentInPSMode;
++ u32 DelayLPSLastTimeStamp;
++
++ s32 pnp_current_pwr_state;
++ u8 pnp_bstop_trx;
++
++
++ u8 bInternalAutoSuspend;
++ u8 bInSuspend;
++ u8 bSupportRemoteWakeup;
++#ifdef CONFIG_WOWLAN
++ u8 wowlan_mode;
++ u8 wowlan_pattern;
++ u8 wowlan_magic;
++ u8 wowlan_unicast;
++ u8 wowlan_pattern_idx;
++ u32 wowlan_pattern_context[8][5];
++#endif // CONFIG_WOWLAN
++ _timer pwr_state_check_timer;
++ int pwr_state_check_interval;
++ u8 pwr_state_check_cnts;
++
++ int ps_flag;
++
++ rt_rf_power_state rf_pwrstate;//cur power state
++ //rt_rf_power_state current_rfpwrstate;
++ rt_rf_power_state change_rfpwrstate;
++
++ u8 bHWPowerdown;//if support hw power down
++ u8 bHWPwrPindetect;
++ u8 bkeepfwalive;
++ u8 brfoffbyhw;
++ unsigned long PS_BBRegBackup[PSBBREG_TOTALCNT];
++
++ #ifdef CONFIG_RESUME_IN_WORKQUEUE
++ struct workqueue_struct *rtw_workqueue;
++ _workitem resume_work;
++ #endif
++
++ #ifdef CONFIG_HAS_EARLYSUSPEND
++ struct early_suspend early_suspend;
++ u8 do_late_resume;
++ #endif //CONFIG_HAS_EARLYSUSPEND
++
++ #ifdef CONFIG_ANDROID_POWER
++ android_early_suspend_t early_suspend;
++ u8 do_late_resume;
++ #endif
++
++};
++
++#define rtw_get_ips_mode_req(pwrctrlpriv) \
++ (pwrctrlpriv)->ips_mode_req
++
++#define rtw_ips_mode_req(pwrctrlpriv, ips_mode) \
++ (pwrctrlpriv)->ips_mode_req = (ips_mode)
++
++#define RTW_PWR_STATE_CHK_INTERVAL 2000
++
++#define _rtw_set_pwr_state_check_timer(pwrctrlpriv, ms) \
++ do { \
++ /*DBG_871X("%s _rtw_set_pwr_state_check_timer(%p, %d)\n", __FUNCTION__, (pwrctrlpriv), (ms));*/ \
++ _set_timer(&(pwrctrlpriv)->pwr_state_check_timer, (ms)); \
++ } while(0)
++
++#define rtw_set_pwr_state_check_timer(pwrctrlpriv) \
++ _rtw_set_pwr_state_check_timer((pwrctrlpriv), (pwrctrlpriv)->pwr_state_check_interval)
++
++extern void rtw_init_pwrctrl_priv(_adapter *adapter);
++extern void rtw_free_pwrctrl_priv(_adapter * adapter);
++
++#ifdef CONFIG_LPS_LCLK
++extern s32 rtw_register_tx_alive(PADAPTER padapter);
++extern void rtw_unregister_tx_alive(PADAPTER padapter);
++extern s32 rtw_register_rx_alive(PADAPTER padapter);
++extern void rtw_unregister_rx_alive(PADAPTER padapter);
++extern s32 rtw_register_cmd_alive(PADAPTER padapter);
++extern void rtw_unregister_cmd_alive(PADAPTER padapter);
++extern s32 rtw_register_evt_alive(PADAPTER padapter);
++extern void rtw_unregister_evt_alive(PADAPTER padapter);
++extern void cpwm_int_hdl(PADAPTER padapter, struct reportpwrstate_parm *preportpwrstate);
++#endif
++
++extern void rtw_set_ps_mode(_adapter * padapter, u8 ps_mode, u8 smart_ps);
++extern void rtw_set_rpwm(_adapter * padapter, u8 val8);
++extern void LeaveAllPowerSaveMode(PADAPTER Adapter);
++#ifdef CONFIG_IPS
++void _ips_enter(_adapter * padapter);
++void ips_enter(_adapter * padapter);
++int _ips_leave(_adapter * padapter);
++int ips_leave(_adapter * padapter);
++#endif
++
++void rtw_ps_processor(_adapter*padapter);
++
++#ifdef CONFIG_AUTOSUSPEND
++int autoresume_enter(_adapter* padapter);
++#endif
++#ifdef SUPPORT_HW_RFOFF_DETECTED
++rt_rf_power_state RfOnOffDetect(IN PADAPTER pAdapter );
++#endif
++
++
++#ifdef CONFIG_LPS
++void LPS_Enter(PADAPTER padapter);
++void LPS_Leave(PADAPTER padapter);
++#endif
++
++#ifdef CONFIG_RESUME_IN_WORKQUEUE
++void rtw_resume_in_workqueue(struct pwrctrl_priv *pwrpriv);
++#endif //CONFIG_RESUME_IN_WORKQUEUE
++
++#if defined(CONFIG_HAS_EARLYSUSPEND ) || defined(CONFIG_ANDROID_POWER)
++bool rtw_is_earlysuspend_registered(struct pwrctrl_priv *pwrpriv);
++bool rtw_is_do_late_resume(struct pwrctrl_priv *pwrpriv);
++void rtw_set_do_late_resume(struct pwrctrl_priv *pwrpriv, bool enable);
++void rtw_register_early_suspend(struct pwrctrl_priv *pwrpriv);
++void rtw_unregister_early_suspend(struct pwrctrl_priv *pwrpriv);
++#else
++#define rtw_is_earlysuspend_registered(pwrpriv) _FALSE
++#define rtw_is_do_late_resume(pwrpriv) _FALSE
++#define rtw_set_do_late_resume(pwrpriv, enable) do {} while (0)
++#define rtw_register_early_suspend(pwrpriv) do {} while (0)
++#define rtw_unregister_early_suspend(pwrpriv) do {} while (0)
++#endif /* CONFIG_HAS_EARLYSUSPEND || CONFIG_ANDROID_POWER */
++
++u8 rtw_interface_ps_func(_adapter *padapter,HAL_INTF_PS_FUNC efunc_id,u8* val);
++void rtw_set_ips_deny(_adapter *padapter, u32 ms);
++int _rtw_pwr_wakeup(_adapter *padapter, u32 ips_deffer_ms, const char *caller);
++#define rtw_pwr_wakeup(adapter) _rtw_pwr_wakeup(adapter, RTW_PWR_STATE_CHK_INTERVAL, __FUNCTION__)
++#define rtw_pwr_wakeup_ex(adapter, ips_deffer_ms) _rtw_pwr_wakeup(adapter, ips_deffer_ms, __FUNCTION__)
++int rtw_pm_set_ips(_adapter *padapter, u8 mode);
++int rtw_pm_set_lps(_adapter *padapter, u8 mode);
++
++#endif //__RTL871X_PWRCTRL_H_
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtw_qos.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtw_qos.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtw_qos.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtw_qos.h 2015-07-28 01:20:58.321597318 +0200
+@@ -0,0 +1,39 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++
++
++#ifndef _RTW_QOS_H_
++#define _RTW_QOS_H_
++#include <drv_conf.h>
++#include <osdep_service.h>
++
++
++
++
++
++
++struct qos_priv {
++
++ unsigned int qos_option; //bit mask option: u-apsd, s-apsd, ts, block ack...
++
++};
++
++
++#endif //_RTL871X_QOS_H_
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtw_recv.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtw_recv.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtw_recv.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtw_recv.h 2015-07-28 01:20:58.321597318 +0200
+@@ -0,0 +1,730 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef _RTW_RECV_H_
++#define _RTW_RECV_H_
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++
++
++#define NR_RECVFRAME 256
++
++#define RXFRAME_ALIGN 8
++#define RXFRAME_ALIGN_SZ (1<<RXFRAME_ALIGN)
++
++#define MAX_RXFRAME_CNT 512
++#define MAX_RX_NUMBLKS (32)
++#define RECVFRAME_HDR_ALIGN 128
++
++#define SNAP_SIZE sizeof(struct ieee80211_snap_hdr)
++
++static u8 SNAP_ETH_TYPE_IPX[2] = {0x81, 0x37};
++
++static u8 SNAP_ETH_TYPE_APPLETALK_AARP[2] = {0x80, 0xf3};
++static u8 SNAP_ETH_TYPE_APPLETALK_DDP[2] = {0x80, 0x9b};
++static u8 SNAP_ETH_TYPE_TDLS[2] = {0x89, 0x0d};
++static u8 SNAP_HDR_APPLETALK_DDP[3] = {0x08, 0x00, 0x07}; // Datagram Delivery Protocol
++
++static u8 oui_8021h[] = {0x00, 0x00, 0xf8};
++static u8 oui_rfc1042[]= {0x00,0x00,0x00};
++
++#define MAX_SUBFRAME_COUNT 64
++static u8 rtw_rfc1042_header[] =
++{ 0xaa, 0xaa, 0x03, 0x00, 0x00, 0x00 };
++/* Bridge-Tunnel header (for EtherTypes ETH_P_AARP and ETH_P_IPX) */
++static u8 rtw_bridge_tunnel_header[] =
++{ 0xaa, 0xaa, 0x03, 0x00, 0x00, 0xf8 };
++
++//for Rx reordering buffer control
++struct recv_reorder_ctrl
++{
++ _adapter *padapter;
++ u8 enable;
++ u16 indicate_seq;//=wstart_b, init_value=0xffff
++ u16 wend_b;
++ u8 wsize_b;
++ _queue pending_recvframe_queue;
++ _timer reordering_ctrl_timer;
++};
++
++struct stainfo_rxcache {
++ u16 tid_rxseq[16];
++/*
++ unsigned short tid0_rxseq;
++ unsigned short tid1_rxseq;
++ unsigned short tid2_rxseq;
++ unsigned short tid3_rxseq;
++ unsigned short tid4_rxseq;
++ unsigned short tid5_rxseq;
++ unsigned short tid6_rxseq;
++ unsigned short tid7_rxseq;
++ unsigned short tid8_rxseq;
++ unsigned short tid9_rxseq;
++ unsigned short tid10_rxseq;
++ unsigned short tid11_rxseq;
++ unsigned short tid12_rxseq;
++ unsigned short tid13_rxseq;
++ unsigned short tid14_rxseq;
++ unsigned short tid15_rxseq;
++*/
++};
++
++
++struct smooth_rssi_data {
++ u32 elements[100]; //array to store values
++ u32 index; //index to current array to store
++ u32 total_num; //num of valid elements
++ u32 total_val; //sum of valid elements
++};
++
++struct signal_stat {
++ u8 update_req; //used to indicate
++ u8 avg_val; //avg of valid elements
++ u32 total_num; //num of valid elements
++ u32 total_val; //sum of valid elements
++};
++
++struct rx_pkt_attrib
++{
++ u16 pkt_len;
++ u8 physt;
++ u8 drvinfo_sz;
++ u8 shift_sz;
++ u8 hdrlen; //the WLAN Header Len
++ u8 to_fr_ds;
++ u8 amsdu;
++ u8 qos;
++ u8 priority;
++ u8 pw_save;
++ u8 mdata;
++ u16 seq_num;
++ u8 frag_num;
++ u8 mfrag;
++ u8 order;
++ u8 privacy; //in frame_ctrl field
++ u8 bdecrypted;
++ u8 encrypt; //when 0 indicate no encrypt. when non-zero, indicate the encrypt algorith
++ u8 iv_len;
++ u8 icv_len;
++ u8 crc_err;
++ u8 icv_err;
++
++ u16 eth_type;
++
++ u8 dst[ETH_ALEN];
++ u8 src[ETH_ALEN];
++ u8 ta[ETH_ALEN];
++ u8 ra[ETH_ALEN];
++ u8 bssid[ETH_ALEN];
++
++ u8 ack_policy;
++
++//#ifdef CONFIG_TCP_CSUM_OFFLOAD_RX
++ u8 tcpchk_valid; // 0: invalid, 1: valid
++ u8 ip_chkrpt; //0: incorrect, 1: correct
++ u8 tcp_chkrpt; //0: incorrect, 1: correct
++//#endif
++ u8 key_index;
++
++ u8 mcs_rate;
++ u8 rxht;
++ u8 sgi;
++ u8 signal_qual;
++ s8 rx_mimo_signal_qual[2];
++ u8 signal_strength;
++ u8 rx_rssi[2]; //This value is percentage
++ u8 rx_snr[2];
++ u32 RxPWDBAll;
++ s32 RecvSignalPower;
++};
++
++
++//These definition is used for Rx packet reordering.
++#define SN_LESS(a, b) (((a-b)&0x800)!=0)
++#define SN_EQUAL(a, b) (a == b)
++//#define REORDER_WIN_SIZE 128
++//#define REORDER_ENTRY_NUM 128
++#define REORDER_WAIT_TIME (50) // (ms)
++
++#define RECVBUFF_ALIGN_SZ 8
++
++#define RXDESC_SIZE 24
++#define RXDESC_OFFSET RXDESC_SIZE
++
++struct recv_stat
++{
++ unsigned int rxdw0;
++
++ unsigned int rxdw1;
++
++ unsigned int rxdw2;
++
++ unsigned int rxdw3;
++
++ unsigned int rxdw4;
++
++ unsigned int rxdw5;
++
++#ifdef CONFIG_PCI_HCI
++ unsigned int rxdw6;
++
++ unsigned int rxdw7;
++#endif
++};
++
++#define EOR BIT(30)
++
++#ifdef CONFIG_PCI_HCI
++#define PCI_MAX_RX_QUEUE 1// MSDU packet queue, Rx Command Queue
++#define PCI_MAX_RX_COUNT 128
++
++struct rtw_rx_ring {
++ struct recv_stat *desc;
++ dma_addr_t dma;
++ unsigned int idx;
++ struct sk_buff *rx_buf[PCI_MAX_RX_COUNT];
++};
++#endif
++
++/*
++accesser of recv_priv: rtw_recv_entry(dispatch / passive level); recv_thread(passive) ; returnpkt(dispatch)
++; halt(passive) ;
++
++using enter_critical section to protect
++*/
++struct recv_priv
++{
++ _lock lock;
++
++#ifdef CONFIG_RECV_THREAD_MODE
++ _sema recv_sema;
++ _sema terminate_recvthread_sema;
++#endif
++
++ //_queue blk_strms[MAX_RX_NUMBLKS]; // keeping the block ack frame until return ack
++ _queue free_recv_queue;
++ _queue recv_pending_queue;
++ _queue uc_swdec_pending_queue;
++
++
++ u8 *pallocated_frame_buf;
++ u8 *precv_frame_buf;
++
++ uint free_recvframe_cnt;
++
++ _adapter *adapter;
++
++#ifdef PLATFORM_WINDOWS
++ _nic_hdl RxPktPoolHdl;
++ _nic_hdl RxBufPoolHdl;
++
++#ifdef PLATFORM_OS_XP
++ PMDL pbytecnt_mdl;
++#endif
++ uint counter; //record the number that up-layer will return to drv; only when counter==0 can we release recv_priv
++ NDIS_EVENT recv_resource_evt ;
++#endif
++
++ u32 bIsAnyNonBEPkts;
++ u64 rx_bytes;
++ u64 rx_pkts;
++ u64 rx_drop;
++ u64 last_rx_bytes;
++
++ uint rx_icv_err;
++ uint rx_largepacket_crcerr;
++ uint rx_smallpacket_crcerr;
++ uint rx_middlepacket_crcerr;
++
++#ifdef CONFIG_USB_HCI
++ //u8 *pallocated_urb_buf;
++ _sema allrxreturnevt;
++ uint ff_hwaddr;
++ u8 rx_pending_cnt;
++
++#ifdef CONFIG_USB_INTERRUPT_IN_PIPE
++#ifdef PLATFORM_LINUX
++ PURB int_in_urb;
++#endif
++
++ u8 *int_in_buf;
++#endif
++
++#endif
++#if defined(PLATFORM_LINUX) || defined(PLATFORM_FREEBSD)
++#ifdef PLATFORM_FREEBSD
++ struct task irq_prepare_beacon_tasklet;
++ struct task recv_tasklet;
++#else //PLATFORM_FREEBSD
++ struct tasklet_struct irq_prepare_beacon_tasklet;
++ struct tasklet_struct recv_tasklet;
++#endif //PLATFORM_FREEBSD
++ struct sk_buff_head free_recv_skb_queue;
++ struct sk_buff_head rx_skb_queue;
++#ifdef CONFIG_RX_INDICATE_QUEUE
++ struct task rx_indicate_tasklet;
++ struct ifqueue rx_indicate_queue;
++#endif // CONFIG_RX_INDICATE_QUEUE
++
++#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX
++ _queue recv_buf_pending_queue;
++#endif // CONFIG_USE_USB_BUFFER_ALLOC_RX
++#endif //defined(PLATFORM_LINUX) || defined(PLATFORM_FREEBSD)
++
++ u8 *pallocated_recv_buf;
++ u8 *precv_buf; // 4 alignment
++ _queue free_recv_buf_queue;
++ u32 free_recv_buf_queue_cnt;
++
++#ifdef CONFIG_SDIO_HCI
++ _queue recv_buf_pending_queue;
++#endif
++
++#ifdef CONFIG_PCI_HCI
++ // Rx
++ struct rtw_rx_ring rx_ring[PCI_MAX_RX_QUEUE];
++ int rxringcount;
++ u16 rxbuffersize;
++#endif
++
++ //For display the phy informatiom
++ u8 is_signal_dbg; // for debug
++ u8 signal_strength_dbg; // for debug
++ s8 rssi;
++ s8 rxpwdb;
++ u8 signal_strength;
++ u8 signal_qual;
++ u8 noise;
++ int RxSNRdB[2];
++ s8 RxRssi[2];
++ int FalseAlmCnt_all;
++
++#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
++ _timer signal_stat_timer;
++ u32 signal_stat_sampling_interval;
++ //u32 signal_stat_converging_constant;
++ struct signal_stat signal_qual_data;
++ struct signal_stat signal_strength_data;
++#else //CONFIG_NEW_SIGNAL_STAT_PROCESS
++ struct smooth_rssi_data signal_qual_data;
++ struct smooth_rssi_data signal_strength_data;
++#endif //CONFIG_NEW_SIGNAL_STAT_PROCESS
++
++ u32 recvbuf_skb_alloc_fail_cnt;
++ u32 recvbuf_null_cnt;
++ u32 read_port_complete_EINPROGRESS_cnt;
++ u32 read_port_complete_other_urb_err_cnt;
++
++
++};
++
++#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
++#define rtw_set_signal_stat_timer(recvpriv) _set_timer(&(recvpriv)->signal_stat_timer, (recvpriv)->signal_stat_sampling_interval)
++#endif //CONFIG_NEW_SIGNAL_STAT_PROCESS
++
++struct sta_recv_priv {
++
++ _lock lock;
++ sint option;
++
++ //_queue blk_strms[MAX_RX_NUMBLKS];
++ _queue defrag_q; //keeping the fragment frame until defrag
++
++ struct stainfo_rxcache rxcache;
++
++ //uint sta_rx_bytes;
++ //uint sta_rx_pkts;
++ //uint sta_rx_fail;
++
++};
++
++
++struct recv_buf
++{
++ _list list;
++
++ _lock recvbuf_lock;
++
++ u32 ref_cnt;
++
++ PADAPTER adapter;
++
++ u8 *pbuf;
++ u8 *pallocated_buf;
++
++ u32 len;
++ u8 *phead;
++ u8 *pdata;
++ u8 *ptail;
++ u8 *pend;
++
++#ifdef CONFIG_USB_HCI
++
++ #if defined(PLATFORM_OS_XP)||defined(PLATFORM_LINUX)||defined(PLATFORM_FREEBSD)
++ PURB purb;
++ dma_addr_t dma_transfer_addr; /* (in) dma addr for transfer_buffer */
++ u32 alloc_sz;
++ #endif
++
++ #ifdef PLATFORM_OS_XP
++ PIRP pirp;
++ #endif
++
++ #ifdef PLATFORM_OS_CE
++ USB_TRANSFER usb_transfer_read_port;
++ #endif
++
++ u8 irp_pending;
++ int transfer_len;
++
++#endif
++
++#ifdef PLATFORM_LINUX
++ _pkt *pskb;
++ u8 reuse;
++#endif
++#ifdef PLATFORM_FREEBSD //skb solution
++ struct sk_buff *pskb;
++ u8 reuse;
++#endif //PLATFORM_FREEBSD //skb solution
++};
++
++
++/*
++ head ----->
++
++ data ----->
++
++ payload
++
++ tail ----->
++
++
++ end ----->
++
++ len = (unsigned int )(tail - data);
++
++*/
++struct recv_frame_hdr
++{
++ _list list;
++#ifndef CONFIG_BSD_RX_USE_MBUF
++ struct sk_buff *pkt;
++ struct sk_buff *pkt_newalloc;
++#else // CONFIG_BSD_RX_USE_MBUF
++ _pkt *pkt;
++ _pkt *pkt_newalloc;
++#endif // CONFIG_BSD_RX_USE_MBUF
++
++ _adapter *adapter;
++
++ u8 fragcnt;
++
++ int frame_tag;
++
++ struct rx_pkt_attrib attrib;
++
++ uint len;
++ u8 *rx_head;
++ u8 *rx_data;
++ u8 *rx_tail;
++ u8 *rx_end;
++
++ void *precvbuf;
++
++
++ //
++ struct sta_info *psta;
++
++ //for A-MPDU Rx reordering buffer control
++ struct recv_reorder_ctrl *preorder_ctrl;
++
++};
++
++
++union recv_frame{
++
++ union{
++ _list list;
++ struct recv_frame_hdr hdr;
++ uint mem[RECVFRAME_HDR_ALIGN>>2];
++ }u;
++
++ //uint mem[MAX_RXSZ>>2];
++
++};
++
++
++extern union recv_frame *_rtw_alloc_recvframe (_queue *pfree_recv_queue); //get a free recv_frame from pfree_recv_queue
++extern union recv_frame *rtw_alloc_recvframe (_queue *pfree_recv_queue); //get a free recv_frame from pfree_recv_queue
++extern void rtw_init_recvframe(union recv_frame *precvframe ,struct recv_priv *precvpriv);
++extern int rtw_free_recvframe(union recv_frame *precvframe, _queue *pfree_recv_queue);
++
++#define rtw_dequeue_recvframe(queue) rtw_alloc_recvframe(queue)
++extern int _rtw_enqueue_recvframe(union recv_frame *precvframe, _queue *queue);
++extern int rtw_enqueue_recvframe(union recv_frame *precvframe, _queue *queue);
++
++extern void rtw_free_recvframe_queue(_queue *pframequeue, _queue *pfree_recv_queue);
++u32 rtw_free_uc_swdec_pending_queue(_adapter *adapter);
++
++sint rtw_enqueue_recvbuf_to_head(struct recv_buf *precvbuf, _queue *queue);
++sint rtw_enqueue_recvbuf(struct recv_buf *precvbuf, _queue *queue);
++struct recv_buf *rtw_dequeue_recvbuf (_queue *queue);
++
++void rtw_reordering_ctrl_timeout_handler(void *pcontext);
++
++__inline static u8 *get_rxmem(union recv_frame *precvframe)
++{
++ //always return rx_head...
++ if(precvframe==NULL)
++ return NULL;
++
++ return precvframe->u.hdr.rx_head;
++}
++
++__inline static u8 *get_rx_status(union recv_frame *precvframe)
++{
++
++ return get_rxmem(precvframe);
++
++}
++
++__inline static u8 *get_recvframe_data(union recv_frame *precvframe)
++{
++
++ //alwasy return rx_data
++ if(precvframe==NULL)
++ return NULL;
++
++ return precvframe->u.hdr.rx_data;
++
++}
++
++__inline static u8 *recvframe_push(union recv_frame *precvframe, sint sz)
++{
++ // append data before rx_data
++
++ /* add data to the start of recv_frame
++ *
++ * This function extends the used data area of the recv_frame at the buffer
++ * start. rx_data must be still larger than rx_head, after pushing.
++ */
++
++ if(precvframe==NULL)
++ return NULL;
++
++
++ precvframe->u.hdr.rx_data -= sz ;
++ if( precvframe->u.hdr.rx_data < precvframe->u.hdr.rx_head )
++ {
++ precvframe->u.hdr.rx_data += sz ;
++ return NULL;
++ }
++
++ precvframe->u.hdr.len +=sz;
++
++ return precvframe->u.hdr.rx_data;
++
++}
++
++
++__inline static u8 *recvframe_pull(union recv_frame *precvframe, sint sz)
++{
++ // rx_data += sz; move rx_data sz bytes hereafter
++
++ //used for extract sz bytes from rx_data, update rx_data and return the updated rx_data to the caller
++
++
++ if(precvframe==NULL)
++ return NULL;
++
++
++ precvframe->u.hdr.rx_data += sz;
++
++ if(precvframe->u.hdr.rx_data > precvframe->u.hdr.rx_tail)
++ {
++ precvframe->u.hdr.rx_data -= sz;
++ return NULL;
++ }
++
++ precvframe->u.hdr.len -=sz;
++
++ return precvframe->u.hdr.rx_data;
++
++}
++
++__inline static u8 *recvframe_put(union recv_frame *precvframe, sint sz)
++{
++ // rx_tai += sz; move rx_tail sz bytes hereafter
++
++ //used for append sz bytes from ptr to rx_tail, update rx_tail and return the updated rx_tail to the caller
++ //after putting, rx_tail must be still larger than rx_end.
++ unsigned char * prev_rx_tail;
++
++ if(precvframe==NULL)
++ return NULL;
++
++ prev_rx_tail = precvframe->u.hdr.rx_tail;
++
++ precvframe->u.hdr.rx_tail += sz;
++
++ if(precvframe->u.hdr.rx_tail > precvframe->u.hdr.rx_end)
++ {
++ precvframe->u.hdr.rx_tail -= sz;
++ return NULL;
++ }
++
++ precvframe->u.hdr.len +=sz;
++
++ return precvframe->u.hdr.rx_tail;
++
++}
++
++
++
++__inline static u8 *recvframe_pull_tail(union recv_frame *precvframe, sint sz)
++{
++ // rmv data from rx_tail (by yitsen)
++
++ //used for extract sz bytes from rx_end, update rx_end and return the updated rx_end to the caller
++ //after pulling, rx_end must be still larger than rx_data.
++
++ if(precvframe==NULL)
++ return NULL;
++
++ precvframe->u.hdr.rx_tail -= sz;
++
++ if(precvframe->u.hdr.rx_tail < precvframe->u.hdr.rx_data)
++ {
++ precvframe->u.hdr.rx_tail += sz;
++ return NULL;
++ }
++
++ precvframe->u.hdr.len -=sz;
++
++ return precvframe->u.hdr.rx_tail;
++
++}
++
++
++
++__inline static _buffer * get_rxbuf_desc(union recv_frame *precvframe)
++{
++ _buffer * buf_desc;
++
++ if(precvframe==NULL)
++ return NULL;
++#ifdef PLATFORM_WINDOWS
++ NdisQueryPacket(precvframe->u.hdr.pkt, NULL, NULL, &buf_desc, NULL);
++#endif
++
++ return buf_desc;
++}
++
++
++__inline static union recv_frame *rxmem_to_recvframe(u8 *rxmem)
++{
++ //due to the design of 2048 bytes alignment of recv_frame, we can reference the union recv_frame
++ //from any given member of recv_frame.
++ // rxmem indicates the any member/address in recv_frame
++
++ return (union recv_frame*)(((SIZE_PTR)rxmem >> RXFRAME_ALIGN) << RXFRAME_ALIGN);
++
++}
++
++__inline static union recv_frame *pkt_to_recvframe(_pkt *pkt)
++{
++
++ u8 * buf_star;
++ union recv_frame * precv_frame;
++#ifdef PLATFORM_WINDOWS
++ _buffer * buf_desc;
++ uint len;
++
++ NdisQueryPacket(pkt, NULL, NULL, &buf_desc, &len);
++ NdisQueryBufferSafe(buf_desc, &buf_star, &len, HighPagePriority);
++#endif
++ precv_frame = rxmem_to_recvframe((unsigned char*)buf_star);
++
++ return precv_frame;
++}
++
++__inline static u8 *pkt_to_recvmem(_pkt *pkt)
++{
++ // return the rx_head
++
++ union recv_frame * precv_frame = pkt_to_recvframe(pkt);
++
++ return precv_frame->u.hdr.rx_head;
++
++}
++
++__inline static u8 *pkt_to_recvdata(_pkt *pkt)
++{
++ // return the rx_data
++
++ union recv_frame * precv_frame =pkt_to_recvframe(pkt);
++
++ return precv_frame->u.hdr.rx_data;
++
++}
++
++
++__inline static sint get_recvframe_len(union recv_frame *precvframe)
++{
++ return precvframe->u.hdr.len;
++}
++
++__inline static u8 query_rx_pwr_percentage(s8 antpower )
++{
++ if ((antpower <= -100) || (antpower >= 20))
++ {
++ return 0;
++ }
++ else if (antpower >= 0)
++ {
++ return 100;
++ }
++ else
++ {
++ return (100+antpower);
++ }
++}
++
++__inline static s32 translate_percentage_to_dbm(u32 SignalStrengthIndex)
++{
++ s32 SignalPower; // in dBm.
++
++ // Translate to dBm (x=0.5y-95).
++ SignalPower = (s32)((SignalStrengthIndex + 1) >> 1);
++ SignalPower -= 95;
++
++ return SignalPower;
++}
++
++
++struct sta_info;
++
++extern void _rtw_init_sta_recv_priv(struct sta_recv_priv *psta_recvpriv);
++
++extern void mgt_dispatcher(_adapter *padapter, union recv_frame *precv_frame);
++
++#endif
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtw_rf.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtw_rf.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtw_rf.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtw_rf.h 2015-07-28 01:20:58.321597318 +0200
+@@ -0,0 +1,151 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef __RTW_RF_H_
++#define __RTW_RF_H_
++
++#include <drv_conf.h>
++#include <rtw_cmd.h>
++
++#define OFDM_PHY 1
++#define MIXED_PHY 2
++#define CCK_PHY 3
++
++#define NumRates (13)
++
++// slot time for 11g
++#define SHORT_SLOT_TIME 9
++#define NON_SHORT_SLOT_TIME 20
++
++#define RTL8711_RF_MAX_SENS 6
++#define RTL8711_RF_DEF_SENS 4
++
++//
++// We now define the following channels as the max channels in each channel plan.
++// 2G, total 14 chnls
++// {1,2,3,4,5,6,7,8,9,10,11,12,13,14}
++// 5G, total 24 chnls
++// {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140,149,153,157,161,165}
++#define MAX_CHANNEL_NUM_2G 14
++#define MAX_CHANNEL_NUM_5G 24
++#define MAX_CHANNEL_NUM 38//14+24
++
++//#define NUM_REGULATORYS 21
++#define NUM_REGULATORYS 1
++
++//Country codes
++#define USA 0x555320
++#define EUROPE 0x1 //temp, should be provided later
++#define JAPAN 0x2 //temp, should be provided later
++
++struct regulatory_class {
++ u32 starting_freq; //MHz,
++ u8 channel_set[MAX_CHANNEL_NUM];
++ u8 channel_cck_power[MAX_CHANNEL_NUM];//dbm
++ u8 channel_ofdm_power[MAX_CHANNEL_NUM];//dbm
++ u8 txpower_limit; //dbm
++ u8 channel_spacing; //MHz
++ u8 modem;
++};
++
++typedef enum _CAPABILITY{
++ cESS = 0x0001,
++ cIBSS = 0x0002,
++ cPollable = 0x0004,
++ cPollReq = 0x0008,
++ cPrivacy = 0x0010,
++ cShortPreamble = 0x0020,
++ cPBCC = 0x0040,
++ cChannelAgility = 0x0080,
++ cSpectrumMgnt = 0x0100,
++ cQos = 0x0200, // For HCCA, use with CF-Pollable and CF-PollReq
++ cShortSlotTime = 0x0400,
++ cAPSD = 0x0800,
++ cRM = 0x1000, // RRM (Radio Request Measurement)
++ cDSSS_OFDM = 0x2000,
++ cDelayedBA = 0x4000,
++ cImmediateBA = 0x8000,
++}CAPABILITY, *PCAPABILITY;
++
++enum _REG_PREAMBLE_MODE{
++ PREAMBLE_LONG = 1,
++ PREAMBLE_AUTO = 2,
++ PREAMBLE_SHORT = 3,
++};
++
++
++enum _RTL8712_RF_MIMO_CONFIG_{
++ RTL8712_RFCONFIG_1T=0x10,
++ RTL8712_RFCONFIG_2T=0x20,
++ RTL8712_RFCONFIG_1R=0x01,
++ RTL8712_RFCONFIG_2R=0x02,
++ RTL8712_RFCONFIG_1T1R=0x11,
++ RTL8712_RFCONFIG_1T2R=0x12,
++ RTL8712_RFCONFIG_TURBO=0x92,
++ RTL8712_RFCONFIG_2T2R=0x22
++};
++
++
++// Bandwidth Offset
++#define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0
++#define HAL_PRIME_CHNL_OFFSET_LOWER 1
++#define HAL_PRIME_CHNL_OFFSET_UPPER 2
++
++// Represent Channel Width in HT Capabilities
++//
++typedef enum _HT_CHANNEL_WIDTH {
++ HT_CHANNEL_WIDTH_20 = 0,
++ HT_CHANNEL_WIDTH_40 = 1,
++}HT_CHANNEL_WIDTH, *PHT_CHANNEL_WIDTH;
++
++//
++// Represent Extention Channel Offset in HT Capabilities
++// This is available only in 40Mhz mode.
++//
++typedef enum _HT_EXTCHNL_OFFSET{
++ HT_EXTCHNL_OFFSET_NO_EXT = 0,
++ HT_EXTCHNL_OFFSET_UPPER = 1,
++ HT_EXTCHNL_OFFSET_NO_DEF = 2,
++ HT_EXTCHNL_OFFSET_LOWER = 3,
++}HT_EXTCHNL_OFFSET, *PHT_EXTCHNL_OFFSET;
++
++/* 2007/11/15 MH Define different RF type. */
++typedef enum _RT_RF_TYPE_DEFINITION
++{
++ RF_1T2R = 0,
++ RF_2T4R = 1,
++ RF_2T2R = 2,
++ RF_1T1R = 3,
++ RF_2T2R_GREEN = 4,
++ RF_819X_MAX_TYPE = 5,
++}RT_RF_TYPE_DEF_E;
++
++typedef enum _RF_RADIO_PATH{
++ RF_PATH_A = 0, //Radio Path A
++ RF_PATH_B = 1, //Radio Path B
++ RF_PATH_C = 2, //Radio Path C
++ RF_PATH_D = 3, //Radio Path D
++ //RF_PATH_MAX //Max RF number 90 support
++}RF_RADIO_PATH_E, *PRF_RADIO_PATH_E;
++
++u32 rtw_ch2freq(u32 ch);
++u32 rtw_freq2ch(u32 freq);
++
++
++#endif //_RTL8711_RF_H_
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtw_security.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtw_security.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtw_security.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtw_security.h 2015-07-28 01:20:58.321597318 +0200
+@@ -0,0 +1,446 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef __RTW_SECURITY_H_
++#define __RTW_SECURITY_H_
++
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++
++
++#define _NO_PRIVACY_ 0x0
++#define _WEP40_ 0x1
++#define _TKIP_ 0x2
++#define _TKIP_WTMIC_ 0x3
++#define _AES_ 0x4
++#define _WEP104_ 0x5
++#ifdef CONFIG_IEEE80211W
++#define _BIP_ 0x8
++#endif //CONFIG_IEEE80211W
++#define is_wep_enc(alg) (((alg) == _WEP40_) || ((alg) == _WEP104_))
++
++#define _WPA_IE_ID_ 0xdd
++#define _WPA2_IE_ID_ 0x30
++
++#define SHA256_MAC_LEN 32
++#define AES_BLOCK_SIZE 16
++#define AES_PRIV_SIZE (4 * 44)
++
++#ifndef Ndis802_11AuthModeWPA2
++#define Ndis802_11AuthModeWPA2 (Ndis802_11AuthModeWPANone + 1)
++#endif
++
++#ifndef Ndis802_11AuthModeWPA2PSK
++#define Ndis802_11AuthModeWPA2PSK (Ndis802_11AuthModeWPANone + 2)
++#endif
++
++union pn48 {
++
++ u64 val;
++
++#ifdef CONFIG_LITTLE_ENDIAN
++
++struct {
++ u8 TSC0;
++ u8 TSC1;
++ u8 TSC2;
++ u8 TSC3;
++ u8 TSC4;
++ u8 TSC5;
++ u8 TSC6;
++ u8 TSC7;
++} _byte_;
++
++#elif defined(CONFIG_BIG_ENDIAN)
++
++struct {
++ u8 TSC7;
++ u8 TSC6;
++ u8 TSC5;
++ u8 TSC4;
++ u8 TSC3;
++ u8 TSC2;
++ u8 TSC1;
++ u8 TSC0;
++} _byte_;
++
++#endif
++
++};
++
++union Keytype {
++ u8 skey[16];
++ u32 lkey[4];
++};
++
++
++typedef struct _RT_PMKID_LIST
++{
++ u8 bUsed;
++ u8 Bssid[6];
++ u8 PMKID[16];
++ u8 SsidBuf[33];
++ u8* ssid_octet;
++ u16 ssid_length;
++} RT_PMKID_LIST, *PRT_PMKID_LIST;
++
++
++struct security_priv
++{
++ u32 dot11AuthAlgrthm; // 802.11 auth, could be open, shared, 8021x and authswitch
++ u32 dot11PrivacyAlgrthm; // This specify the privacy for shared auth. algorithm.
++
++ /* WEP */
++ u32 dot11PrivacyKeyIndex; // this is only valid for legendary wep, 0~3 for key id. (tx key index)
++ union Keytype dot11DefKey[4]; // this is only valid for def. key
++ u32 dot11DefKeylen[4];
++ u8 key_mask; /* use to restore wep key after hal_init */
++
++ u32 dot118021XGrpPrivacy; // This specify the privacy algthm. used for Grp key
++ u32 dot118021XGrpKeyid; // key id used for Grp Key ( tx key index)
++ union Keytype dot118021XGrpKey[4]; // 802.1x Group Key, for inx0 and inx1
++ union Keytype dot118021XGrptxmickey[4];
++ union Keytype dot118021XGrprxmickey[4];
++ union pn48 dot11Grptxpn; // PN48 used for Grp Key xmit.
++ union pn48 dot11Grprxpn; // PN48 used for Grp Key recv.
++#ifdef CONFIG_IEEE80211W
++ u32 dot11wBIPKeyid; // key id used for BIP Key ( tx key index)
++ union Keytype dot11wBIPKey[6]; // BIP Key, for index4 and index5
++ union pn48 dot11wBIPtxpn; // PN48 used for Grp Key xmit.
++ union pn48 dot11wBIPrxpn; // PN48 used for Grp Key recv.
++#endif //CONFIG_IEEE80211W
++#ifdef CONFIG_AP_MODE
++ //extend security capabilities for AP_MODE
++ unsigned int dot8021xalg;//0:disable, 1:psk, 2:802.1x
++ unsigned int wpa_psk;//0:disable, bit(0): WPA, bit(1):WPA2
++ unsigned int wpa_group_cipher;
++ unsigned int wpa2_group_cipher;
++ unsigned int wpa_pairwise_cipher;
++ unsigned int wpa2_pairwise_cipher;
++#endif
++
++ u8 wps_ie[MAX_WPS_IE_LEN];//added in assoc req
++ int wps_ie_len;
++
++
++ u8 binstallGrpkey;
++#ifdef CONFIG_IEEE80211W
++ u8 binstallBIPkey;
++#endif //CONFIG_IEEE80211W
++ u8 busetkipkey;
++ //_timer tkip_timer;
++ u8 bcheck_grpkey;
++ u8 bgrpkey_handshake;
++
++ //u8 packet_cnt;//unused, removed
++
++ s32 sw_encrypt;//from registry_priv
++ s32 sw_decrypt;//from registry_priv
++
++ s32 hw_decrypted;//if the rx packets is hw_decrypted==_FALSE, it means the hw has not been ready.
++
++
++ //keeps the auth_type & enc_status from upper layer ioctl(wpa_supplicant or wzc)
++ u32 ndisauthtype; // NDIS_802_11_AUTHENTICATION_MODE
++ u32 ndisencryptstatus; // NDIS_802_11_ENCRYPTION_STATUS
++
++ WLAN_BSSID_EX sec_bss; //for joinbss (h2c buffer) usage
++
++ NDIS_802_11_WEP ndiswep;
++#ifdef PLATFORM_WINDOWS
++ u8 KeyMaterial[16];// variable length depending on above field.
++#endif
++
++ u8 assoc_info[600];
++ u8 szofcapability[256]; //for wpa2 usage
++ u8 oidassociation[512]; //for wpa/wpa2 usage
++ u8 authenticator_ie[256]; //store ap security information element
++ u8 supplicant_ie[256]; //store sta security information element
++
++
++ //for tkip countermeasure
++ u32 last_mic_err_time;
++ u8 btkip_countermeasure;
++ u8 btkip_wait_report;
++ u32 btkip_countermeasure_time;
++
++ //---------------------------------------------------------------------------
++ // For WPA2 Pre-Authentication.
++ //---------------------------------------------------------------------------
++ //u8 RegEnablePreAuth; // Default value: Pre-Authentication enabled or not, from registry "EnablePreAuth". Added by Annie, 2005-11-01.
++ //u8 EnablePreAuthentication; // Current Value: Pre-Authentication enabled or not.
++ RT_PMKID_LIST PMKIDList[NUM_PMKID_CACHE]; // Renamed from PreAuthKey[NUM_PRE_AUTH_KEY]. Annie, 2006-10-13.
++ u8 PMKIDIndex;
++ //u32 PMKIDCount; // Added by Annie, 2006-10-13.
++ //u8 szCapability[256]; // For WPA2-PSK using zero-config, by Annie, 2005-09-20.
++
++ u8 bWepDefaultKeyIdxSet;
++};
++
++struct sha256_state {
++ u64 length;
++ u32 state[8], curlen;
++ u8 buf[64];
++};
++
++#define GET_ENCRY_ALGO(psecuritypriv, psta, encry_algo, bmcst)\
++do{\
++ switch(psecuritypriv->dot11AuthAlgrthm)\
++ {\
++ case dot11AuthAlgrthm_Open:\
++ case dot11AuthAlgrthm_Shared:\
++ case dot11AuthAlgrthm_Auto:\
++ encry_algo = (u8)psecuritypriv->dot11PrivacyAlgrthm;\
++ break;\
++ case dot11AuthAlgrthm_8021X:\
++ if(bmcst)\
++ encry_algo = (u8)psecuritypriv->dot118021XGrpPrivacy;\
++ else\
++ encry_algo =(u8) psta->dot118021XPrivacy;\
++ break;\
++ }\
++}while(0)
++
++
++#define SET_ICE_IV_LEN( iv_len, icv_len, encrypt)\
++do{\
++ switch(encrypt)\
++ {\
++ case _WEP40_:\
++ case _WEP104_:\
++ iv_len = 4;\
++ icv_len = 4;\
++ break;\
++ case _TKIP_:\
++ iv_len = 8;\
++ icv_len = 4;\
++ break;\
++ case _AES_:\
++ iv_len = 8;\
++ icv_len = 8;\
++ break;\
++ default:\
++ iv_len = 0;\
++ icv_len = 0;\
++ break;\
++ }\
++}while(0)
++
++
++#define GET_TKIP_PN(iv,dot11txpn)\
++do{\
++ dot11txpn._byte_.TSC0=iv[2];\
++ dot11txpn._byte_.TSC1=iv[0];\
++ dot11txpn._byte_.TSC2=iv[4];\
++ dot11txpn._byte_.TSC3=iv[5];\
++ dot11txpn._byte_.TSC4=iv[6];\
++ dot11txpn._byte_.TSC5=iv[7];\
++}while(0)
++
++
++#define ROL32( A, n ) ( ((A) << (n)) | ( ((A)>>(32-(n))) & ( (1UL << (n)) - 1 ) ) )
++#define ROR32( A, n ) ROL32( (A), 32-(n) )
++
++struct mic_data
++{
++ u32 K0, K1; // Key
++ u32 L, R; // Current state
++ u32 M; // Message accumulator (single word)
++ u32 nBytesInM; // # bytes in M
++};
++
++extern const u32 Te0[256];
++extern const u32 Te1[256];
++extern const u32 Te2[256];
++extern const u32 Te3[256];
++extern const u32 Te4[256];
++extern const u32 Td0[256];
++extern const u32 Td1[256];
++extern const u32 Td2[256];
++extern const u32 Td3[256];
++extern const u32 Td4[256];
++extern const u32 rcon[10];
++extern const u8 Td4s[256];
++extern const u8 rcons[10];
++
++#define RCON(i) (rcons[(i)] << 24)
++
++static inline u32 rotr(u32 val, int bits)
++{
++ return (val >> bits) | (val << (32 - bits));
++}
++
++#define TE0(i) Te0[((i) >> 24) & 0xff]
++#define TE1(i) rotr(Te0[((i) >> 16) & 0xff], 8)
++#define TE2(i) rotr(Te0[((i) >> 8) & 0xff], 16)
++#define TE3(i) rotr(Te0[(i) & 0xff], 24)
++#define TE41(i) ((Te0[((i) >> 24) & 0xff] << 8) & 0xff000000)
++#define TE42(i) (Te0[((i) >> 16) & 0xff] & 0x00ff0000)
++#define TE43(i) (Te0[((i) >> 8) & 0xff] & 0x0000ff00)
++#define TE44(i) ((Te0[(i) & 0xff] >> 8) & 0x000000ff)
++#define TE421(i) ((Te0[((i) >> 16) & 0xff] << 8) & 0xff000000)
++#define TE432(i) (Te0[((i) >> 8) & 0xff] & 0x00ff0000)
++#define TE443(i) (Te0[(i) & 0xff] & 0x0000ff00)
++#define TE414(i) ((Te0[((i) >> 24) & 0xff] >> 8) & 0x000000ff)
++#define TE4(i) ((Te0[(i)] >> 8) & 0x000000ff)
++
++#define TD0(i) Td0[((i) >> 24) & 0xff]
++#define TD1(i) rotr(Td0[((i) >> 16) & 0xff], 8)
++#define TD2(i) rotr(Td0[((i) >> 8) & 0xff], 16)
++#define TD3(i) rotr(Td0[(i) & 0xff], 24)
++#define TD41(i) (Td4s[((i) >> 24) & 0xff] << 24)
++#define TD42(i) (Td4s[((i) >> 16) & 0xff] << 16)
++#define TD43(i) (Td4s[((i) >> 8) & 0xff] << 8)
++#define TD44(i) (Td4s[(i) & 0xff])
++#define TD0_(i) Td0[(i) & 0xff]
++#define TD1_(i) rotr(Td0[(i) & 0xff], 8)
++#define TD2_(i) rotr(Td0[(i) & 0xff], 16)
++#define TD3_(i) rotr(Td0[(i) & 0xff], 24)
++
++#define GETU32(pt) (((u32)(pt)[0] << 24) ^ ((u32)(pt)[1] << 16) ^ \
++ ((u32)(pt)[2] << 8) ^ ((u32)(pt)[3]))
++
++#define PUTU32(ct, st) { \
++(ct)[0] = (u8)((st) >> 24); (ct)[1] = (u8)((st) >> 16); \
++(ct)[2] = (u8)((st) >> 8); (ct)[3] = (u8)(st); }
++
++#define WPA_GET_BE32(a) ((((u32) (a)[0]) << 24) | (((u32) (a)[1]) << 16) | \
++ (((u32) (a)[2]) << 8) | ((u32) (a)[3]))
++
++#define WPA_PUT_LE16(a, val) \
++ do { \
++ (a)[1] = ((u16) (val)) >> 8; \
++ (a)[0] = ((u16) (val)) & 0xff; \
++ } while (0)
++
++#define WPA_PUT_BE32(a, val) \
++ do { \
++ (a)[0] = (u8) ((((u32) (val)) >> 24) & 0xff); \
++ (a)[1] = (u8) ((((u32) (val)) >> 16) & 0xff); \
++ (a)[2] = (u8) ((((u32) (val)) >> 8) & 0xff); \
++ (a)[3] = (u8) (((u32) (val)) & 0xff); \
++ } while (0)
++
++#define WPA_PUT_BE64(a, val) \
++ do { \
++ (a)[0] = (u8) (((u64) (val)) >> 56); \
++ (a)[1] = (u8) (((u64) (val)) >> 48); \
++ (a)[2] = (u8) (((u64) (val)) >> 40); \
++ (a)[3] = (u8) (((u64) (val)) >> 32); \
++ (a)[4] = (u8) (((u64) (val)) >> 24); \
++ (a)[5] = (u8) (((u64) (val)) >> 16); \
++ (a)[6] = (u8) (((u64) (val)) >> 8); \
++ (a)[7] = (u8) (((u64) (val)) & 0xff); \
++ } while (0)
++
++/* ===== start - public domain SHA256 implementation ===== */
++
++/* This is based on SHA256 implementation in LibTomCrypt that was released into
++ * public domain by Tom St Denis. */
++
++/* the K array */
++static const unsigned long K[64] = {
++ 0x428a2f98UL, 0x71374491UL, 0xb5c0fbcfUL, 0xe9b5dba5UL, 0x3956c25bUL,
++ 0x59f111f1UL, 0x923f82a4UL, 0xab1c5ed5UL, 0xd807aa98UL, 0x12835b01UL,
++ 0x243185beUL, 0x550c7dc3UL, 0x72be5d74UL, 0x80deb1feUL, 0x9bdc06a7UL,
++ 0xc19bf174UL, 0xe49b69c1UL, 0xefbe4786UL, 0x0fc19dc6UL, 0x240ca1ccUL,
++ 0x2de92c6fUL, 0x4a7484aaUL, 0x5cb0a9dcUL, 0x76f988daUL, 0x983e5152UL,
++ 0xa831c66dUL, 0xb00327c8UL, 0xbf597fc7UL, 0xc6e00bf3UL, 0xd5a79147UL,
++ 0x06ca6351UL, 0x14292967UL, 0x27b70a85UL, 0x2e1b2138UL, 0x4d2c6dfcUL,
++ 0x53380d13UL, 0x650a7354UL, 0x766a0abbUL, 0x81c2c92eUL, 0x92722c85UL,
++ 0xa2bfe8a1UL, 0xa81a664bUL, 0xc24b8b70UL, 0xc76c51a3UL, 0xd192e819UL,
++ 0xd6990624UL, 0xf40e3585UL, 0x106aa070UL, 0x19a4c116UL, 0x1e376c08UL,
++ 0x2748774cUL, 0x34b0bcb5UL, 0x391c0cb3UL, 0x4ed8aa4aUL, 0x5b9cca4fUL,
++ 0x682e6ff3UL, 0x748f82eeUL, 0x78a5636fUL, 0x84c87814UL, 0x8cc70208UL,
++ 0x90befffaUL, 0xa4506cebUL, 0xbef9a3f7UL, 0xc67178f2UL
++};
++
++
++/* Various logical functions */
++#define RORc(x, y) \
++( ((((unsigned long) (x) & 0xFFFFFFFFUL) >> (unsigned long) ((y) & 31)) | \
++ ((unsigned long) (x) << (unsigned long) (32 - ((y) & 31)))) & 0xFFFFFFFFUL)
++#define Ch(x,y,z) (z ^ (x & (y ^ z)))
++#define Maj(x,y,z) (((x | y) & z) | (x & y))
++#define S(x, n) RORc((x), (n))
++#define R(x, n) (((x)&0xFFFFFFFFUL)>>(n))
++#define Sigma0(x) (S(x, 2) ^ S(x, 13) ^ S(x, 22))
++#define Sigma1(x) (S(x, 6) ^ S(x, 11) ^ S(x, 25))
++#define Gamma0(x) (S(x, 7) ^ S(x, 18) ^ R(x, 3))
++#define Gamma1(x) (S(x, 17) ^ S(x, 19) ^ R(x, 10))
++#ifndef MIN
++#define MIN(x, y) (((x) < (y)) ? (x) : (y))
++#endif
++#ifdef CONFIG_IEEE80211W
++int omac1_aes_128(u8 *key, u8 *data, size_t data_len, u8 *mac);
++#endif //CONFIG_IEEE80211W
++void rtw_secmicsetkey(struct mic_data *pmicdata, u8 * key );
++void rtw_secmicappendbyte(struct mic_data *pmicdata, u8 b );
++void rtw_secmicappend(struct mic_data *pmicdata, u8 * src, u32 nBytes );
++void rtw_secgetmic(struct mic_data *pmicdata, u8 * dst );
++
++void rtw_seccalctkipmic(
++ u8 * key,
++ u8 *header,
++ u8 *data,
++ u32 data_len,
++ u8 *Miccode,
++ u8 priority);
++
++u32 rtw_aes_encrypt(_adapter *padapter, u8 *pxmitframe);
++u32 rtw_tkip_encrypt(_adapter *padapter, u8 *pxmitframe);
++void rtw_wep_encrypt(_adapter *padapter, u8 *pxmitframe);
++
++u32 rtw_aes_decrypt(_adapter *padapter, u8 *precvframe);
++u32 rtw_tkip_decrypt(_adapter *padapter, u8 *precvframe);
++void rtw_wep_decrypt(_adapter *padapter, u8 *precvframe);
++#ifdef CONFIG_IEEE80211W
++u32 rtw_BIP_verify(_adapter *padapter, u8 *precvframe);
++#endif //CONFIG_IEEE80211W
++#ifdef CONFIG_TDLS
++void wpa_tdls_generate_tpk(_adapter *padapter, struct sta_info *psta);
++int wpa_tdls_ftie_mic(u8 *kck, u8 trans_seq,
++ u8 *lnkid, u8 *rsnie, u8 *timeoutie, u8 *ftie,
++ u8 *mic);
++int tdls_verify_mic(u8 *kck, u8 trans_seq,
++ u8 *lnkid, u8 *rsnie, u8 *timeoutie, u8 *ftie);
++#endif //CONFIG_TDLS
++
++#ifdef PLATFORM_WINDOWS
++void rtw_use_tkipkey_handler (
++ IN PVOID SystemSpecific1,
++ IN PVOID FunctionContext,
++ IN PVOID SystemSpecific2,
++ IN PVOID SystemSpecific3
++ );
++#endif
++#ifdef PLATFORM_LINUX
++void rtw_use_tkipkey_handler(void* FunctionContext);
++#endif
++
++#ifdef PLATFORM_FREEBSD
++void rtw_use_tkipkey_handler(void* FunctionContext);
++#endif //PLATFORM_FREEBSD
++
++void rtw_sec_restore_wep_key(_adapter *adapter);
++u8 rtw_handle_tkip_countermeasure(_adapter* adapter, const char *caller);
++
++#endif //__RTL871X_SECURITY_H_
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtw_sreset.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtw_sreset.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtw_sreset.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtw_sreset.h 2015-07-28 01:20:58.321597318 +0200
+@@ -0,0 +1,73 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef _RTW_SRESET_C_
++#define _RTW_SRESET_C_
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++
++enum {
++ SRESET_TGP_NULL = 0,
++ SRESET_TGP_XMIT_STATUS = 1,
++ SRESET_TGP_LINK_STATUS = 2,
++};
++
++struct sreset_priv {
++ _mutex silentreset_mutex;
++ u8 silent_reset_inprogress;
++ u8 Wifi_Error_Status;
++ unsigned long last_tx_time;
++ unsigned long last_tx_complete_time;
++
++ s32 dbg_trigger_point;
++};
++
++#ifdef CONFIG_RTL8192C
++#include <rtl8192c_hal.h>
++#endif
++#ifdef CONFIG_RTL8192D
++#include <rtl8192d_hal.h>
++#endif
++#ifdef CONFIG_RTL8723A
++#include <rtl8723a_hal.h>
++#endif
++#ifdef CONFIG_RTL8188E
++#include <rtl8188e_hal.h>
++#endif
++
++#define WIFI_STATUS_SUCCESS 0
++#define USB_VEN_REQ_CMD_FAIL BIT0
++#define USB_READ_PORT_FAIL BIT1
++#define USB_WRITE_PORT_FAIL BIT2
++#define WIFI_MAC_TXDMA_ERROR BIT3
++#define WIFI_TX_HANG BIT4
++#define WIFI_RX_HANG BIT5
++#define WIFI_IF_NOT_EXIST BIT6
++
++void sreset_init_value(_adapter *padapter);
++void sreset_reset_value(_adapter *padapter);
++u8 sreset_get_wifi_status(_adapter *padapter);
++void sreset_set_wifi_error_status(_adapter *padapter, u32 status);
++void sreset_set_trigger_point(_adapter *padapter, s32 tgp);
++bool sreset_inprogress(_adapter *padapter);
++void sreset_reset(_adapter *padapter);
++
++#endif
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtw_tdls.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtw_tdls.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtw_tdls.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtw_tdls.h 2015-07-28 01:20:58.321597318 +0200
+@@ -0,0 +1,142 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef __RTW_TDLS_H_
++#define __RTW_TDLS_H_
++
++#include <drv_types.h>
++
++#ifdef CONFIG_TDLS
++/* TDLS STA state */
++#define TDLS_STATE_NONE 0x00000000 //default state
++#define TDLS_INITIATOR_STATE 0x10000000
++#define TDLS_RESPONDER_STATE 0x20000000
++#define TDLS_LINKED_STATE 0x40000000
++#define TDLS_CH_SWITCH_ON_STATE 0x01000000
++#define TDLS_PEER_AT_OFF_STATE 0x02000000 //could send pkt on target ch
++#define TDLS_AT_OFF_CH_STATE 0x04000000
++#define TDLS_CH_SW_INITIATOR_STATE 0x08000000 //avoiding duplicated or unconditional ch. switch rsp.
++#define TDLS_APSD_CHSW_STATE 0x00100000 //in APSD and want to setup channel switch
++#define TDLS_PEER_SLEEP_STATE 0x00200000 //peer sta is sleeping
++#define TDLS_SW_OFF_STATE 0x00400000 //terminate channel swithcing
++#define TDLS_ALIVE_STATE 0x00010000 //Check if peer sta is alived.
++
++#define TPK_RESEND_COUNT 301
++#define CH_SWITCH_TIME 10
++#define CH_SWITCH_TIMEOUT 30
++#define TDLS_STAY_TIME 500
++#define TDLS_SIGNAL_THRESH 0x20
++#define TDLS_WATCHDOG_PERIOD 10 //Periodically sending tdls discovery request in TDLS_WATCHDOG_PERIOD * 2 sec
++#define TDLS_ALIVE_TIMER_PH1 5000
++#define TDLS_ALIVE_TIMER_PH2 2000
++#define TDLS_STAY_TIME 500
++#define TDLS_HANDSHAKE_TIME 2000
++#define TDLS_ALIVE_COUNT 3
++#define TDLS_INI_MACID_ENTRY 6
++
++/* TDLS */
++#define TDLS_MIC_LEN 16
++#define WPA_NONCE_LEN 32
++#define TDLS_TIMEOUT_LEN 4
++
++struct wpa_tdls_ftie {
++ u8 ie_type; /* FTIE */
++ u8 ie_len;
++ u8 mic_ctrl[2];
++ u8 mic[TDLS_MIC_LEN];
++ u8 Anonce[WPA_NONCE_LEN]; /* Responder Nonce in TDLS */
++ u8 Snonce[WPA_NONCE_LEN]; /* Initiator Nonce in TDLS */
++ /* followed by optional elements */
++} ;
++
++struct wpa_tdls_lnkid {
++ u8 ie_type; /* Link Identifier IE */
++ u8 ie_len;
++ u8 bssid[ETH_ALEN];
++ u8 init_sta[ETH_ALEN];
++ u8 resp_sta[ETH_ALEN];
++} ;
++
++static u8 TDLS_RSNIE[]={ 0x01, 0x00, //version shall be set to 1
++ 0x00, 0x0f, 0xac, 0x07, //group sipher suite
++ 0x01, 0x00, //pairwise cipher suite count
++ 0x00, 0x0f, 0xac, 0x04, //pairwise cipher suite list; CCMP only
++ 0x01, 0x00, //AKM suite count
++ 0x00, 0x0f, 0xac, 0x07, //TPK Handshake
++ 0x00, 0x02,
++ //PMKID shall not be present
++ };
++
++static u8 TDLS_WMMIE[]={0x00, 0x50, 0xf2, 0x02, 0x00, 0x01, 0x00}; //Qos info all set zero
++
++static u8 TDLS_EXT_CAPIE[] = {0x00, 0x00, 0x00, 0x50, 0x20}; //bit(28), bit(30), bit(37)
++
++// SRC: Supported Regulatory Classes
++static u8 TDLS_SRC[] = { 0x01, 0x01, 0x02, 0x03, 0x04, 0x0c, 0x16, 0x17, 0x18, 0x19, 0x1b, 0x1c, 0x1d, 0x1e, 0x20, 0x21 };
++
++void rtw_reset_tdls_info(_adapter* padapter);
++int rtw_init_tdls_info(_adapter* padapter);
++void rtw_free_tdls_info(struct tdls_info *ptdlsinfo);
++void issue_nulldata_to_TDLS_peer_STA(_adapter *padapter, struct sta_info *ptdls_sta, unsigned int power_mode);
++void init_TPK_timer(_adapter *padapter, struct sta_info *psta);
++void init_ch_switch_timer(_adapter *padapter, struct sta_info *psta);
++void init_base_ch_timer(_adapter *padapter, struct sta_info *psta);
++void init_off_ch_timer(_adapter *padapter, struct sta_info *psta);
++void init_tdls_alive_timer(_adapter *padapter, struct sta_info *psta);
++void init_handshake_timer(_adapter *padapter, struct sta_info *psta);
++void free_tdls_sta(_adapter *padapter, struct sta_info *ptdls_sta);
++#ifdef CONFIG_WFD
++void issue_tunneled_probe_req(_adapter *padapter);
++void issue_tunneled_probe_rsp(_adapter *padapter, union recv_frame *precv_frame);
++#endif //CONFIG_WFD
++void issue_tdls_dis_req(_adapter *padapter, u8 *mac_addr);
++void issue_tdls_setup_req(_adapter *padapter, u8 *mac_addr);
++void issue_tdls_setup_rsp(_adapter *padapter, union recv_frame *precv_frame);
++void issue_tdls_setup_cfm(_adapter *padapter, union recv_frame *precv_frame);
++void issue_tdls_dis_rsp(_adapter * padapter, union recv_frame * precv_frame, u8 dialog);
++void issue_tdls_teardown(_adapter *padapter, u8 *mac_addr);
++void issue_tdls_peer_traffic_indication(_adapter *padapter, struct sta_info *psta);
++void issue_tdls_ch_switch_req(_adapter *padapter, u8 *mac_addr);
++void issue_tdls_ch_switch_rsp(_adapter *padapter, u8 *mac_addr);
++sint On_TDLS_Dis_Rsp(_adapter *adapter, union recv_frame *precv_frame);
++sint On_TDLS_Setup_Req(_adapter *adapter, union recv_frame *precv_frame);
++sint On_TDLS_Setup_Rsp(_adapter *adapter, union recv_frame *precv_frame);
++sint On_TDLS_Setup_Cfm(_adapter *adapter, union recv_frame *precv_frame);
++sint On_TDLS_Dis_Req(_adapter *adapter, union recv_frame *precv_frame);
++sint On_TDLS_Teardown(_adapter *adapter, union recv_frame *precv_frame);
++sint On_TDLS_Peer_Traffic_Rsp(_adapter *adapter, union recv_frame *precv_frame);
++sint On_TDLS_Ch_Switch_Req(_adapter *adapter, union recv_frame *precv_frame);
++sint On_TDLS_Ch_Switch_Rsp(_adapter *adapter, union recv_frame *precv_frame);
++void rtw_build_tdls_setup_req_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe);
++void rtw_build_tdls_setup_rsp_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe);
++void rtw_build_tdls_setup_cfm_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe);
++void rtw_build_tdls_teardown_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe);
++void rtw_build_tdls_dis_req_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe);
++void rtw_build_tdls_dis_rsp_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe, u8 dialog);
++void rtw_build_tdls_peer_traffic_indication_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe);
++void rtw_build_tdls_ch_switch_req_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe);
++void rtw_build_tdls_ch_switch_rsp_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe);
++void rtw_build_tunneled_probe_req_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe);
++void rtw_build_tunneled_probe_rsp_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe);
++
++int update_sgi_tdls(_adapter *padapter, struct sta_info *psta);
++u32 update_mask_tdls(_adapter *padapter, struct sta_info *psta);
++#endif //CONFIG_TDLS
++
++#endif
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtw_version.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtw_version.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtw_version.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtw_version.h 2015-07-28 01:20:58.321597318 +0200
+@@ -0,0 +1 @@
++#define DRIVERVERSION "v4.0.2_9000.20130911"
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtw_xmit.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtw_xmit.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/rtw_xmit.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/rtw_xmit.h 2015-07-28 01:20:58.321597318 +0200
+@@ -0,0 +1,753 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef _RTW_XMIT_H_
++#define _RTW_XMIT_H_
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++#ifdef PLATFORM_FREEBSD
++#include <if_ether.h>
++#endif //PLATFORM_FREEBSD
++
++#ifdef CONFIG_SDIO_HCI
++//#define MAX_XMITBUF_SZ (30720)// (2048)
++#define MAX_XMITBUF_SZ (12288)
++#define NR_XMITBUFF (16)
++
++#elif defined (CONFIG_USB_HCI)
++#ifdef CONFIG_USB_TX_AGGREGATION
++ #if defined(CONFIG_PLATFORM_ARM_SUNxI) || defined(CONFIG_PLATFORM_ARM_SUN6I)
++ #define MAX_XMITBUF_SZ (12288) //12k 1536*8
++ #elif defined (CONFIG_PLATFORM_MSTAR)
++ #define MAX_XMITBUF_SZ 7680 // 7.5k
++ #else
++ #define MAX_XMITBUF_SZ (20480) // 20k
++ #endif
++#else
++#define MAX_XMITBUF_SZ (2048)
++#endif //CONFIG_USB_TX_AGGREGATION
++#ifdef CONFIG_SINGLE_XMIT_BUF
++#define NR_XMITBUFF (1)
++#else
++#define NR_XMITBUFF (4)
++#endif //CONFIG_SINGLE_XMIT_BUF
++
++#elif defined (CONFIG_PCI_HCI)
++#define MAX_XMITBUF_SZ (1664)
++#define NR_XMITBUFF (128)
++#endif
++
++#ifdef PLATFORM_OS_CE
++#define XMITBUF_ALIGN_SZ 4
++#else
++#ifdef CONFIG_PCI_HCI
++#define XMITBUF_ALIGN_SZ 4
++#else
++#define XMITBUF_ALIGN_SZ 512
++#endif
++#endif
++
++// xmit extension buff defination
++#define MAX_XMIT_EXTBUF_SZ (1536)
++#ifdef CONFIG_SINGLE_XMIT_BUF
++#define NR_XMIT_EXTBUFF (1)
++#else
++#define NR_XMIT_EXTBUFF (32)
++#endif //CONFIG_SINGLE_XMIT_BUF
++
++#define MAX_NUMBLKS (1)
++
++#define XMIT_VO_QUEUE (0)
++#define XMIT_VI_QUEUE (1)
++#define XMIT_BE_QUEUE (2)
++#define XMIT_BK_QUEUE (3)
++
++#define VO_QUEUE_INX 0
++#define VI_QUEUE_INX 1
++#define BE_QUEUE_INX 2
++#define BK_QUEUE_INX 3
++#define BCN_QUEUE_INX 4
++#define MGT_QUEUE_INX 5
++#define HIGH_QUEUE_INX 6
++#define TXCMD_QUEUE_INX 7
++
++#define HW_QUEUE_ENTRY 8
++
++#ifdef CONFIG_PCI_HCI
++//#define TXDESC_NUM 64
++#define TXDESC_NUM 128
++#define TXDESC_NUM_BE_QUEUE 128
++#endif
++
++#define WEP_IV(pattrib_iv, dot11txpn, keyidx)\
++do{\
++ pattrib_iv[0] = dot11txpn._byte_.TSC0;\
++ pattrib_iv[1] = dot11txpn._byte_.TSC1;\
++ pattrib_iv[2] = dot11txpn._byte_.TSC2;\
++ pattrib_iv[3] = ((keyidx & 0x3)<<6);\
++ dot11txpn.val = (dot11txpn.val == 0xffffff) ? 0: (dot11txpn.val+1);\
++}while(0)
++
++
++#define TKIP_IV(pattrib_iv, dot11txpn, keyidx)\
++do{\
++ pattrib_iv[0] = dot11txpn._byte_.TSC1;\
++ pattrib_iv[1] = (dot11txpn._byte_.TSC1 | 0x20) & 0x7f;\
++ pattrib_iv[2] = dot11txpn._byte_.TSC0;\
++ pattrib_iv[3] = BIT(5) | ((keyidx & 0x3)<<6);\
++ pattrib_iv[4] = dot11txpn._byte_.TSC2;\
++ pattrib_iv[5] = dot11txpn._byte_.TSC3;\
++ pattrib_iv[6] = dot11txpn._byte_.TSC4;\
++ pattrib_iv[7] = dot11txpn._byte_.TSC5;\
++ dot11txpn.val = dot11txpn.val == 0xffffffffffffULL ? 0: (dot11txpn.val+1);\
++}while(0)
++
++#define AES_IV(pattrib_iv, dot11txpn, keyidx)\
++do{\
++ pattrib_iv[0] = dot11txpn._byte_.TSC0;\
++ pattrib_iv[1] = dot11txpn._byte_.TSC1;\
++ pattrib_iv[2] = 0;\
++ pattrib_iv[3] = BIT(5) | ((keyidx & 0x3)<<6);\
++ pattrib_iv[4] = dot11txpn._byte_.TSC2;\
++ pattrib_iv[5] = dot11txpn._byte_.TSC3;\
++ pattrib_iv[6] = dot11txpn._byte_.TSC4;\
++ pattrib_iv[7] = dot11txpn._byte_.TSC5;\
++ dot11txpn.val = dot11txpn.val == 0xffffffffffffULL ? 0: (dot11txpn.val+1);\
++}while(0)
++
++
++#define HWXMIT_ENTRY 4
++
++#define TXDESC_SIZE 32
++
++#ifdef CONFIG_SDIO_HCI
++#define TXDESC_OFFSET TXDESC_SIZE
++#endif
++
++#ifdef CONFIG_USB_HCI
++#define PACKET_OFFSET_SZ (8)
++#define TXDESC_OFFSET (TXDESC_SIZE + PACKET_OFFSET_SZ)
++#endif
++
++#ifdef CONFIG_PCI_HCI
++#define TXDESC_OFFSET 0
++#define TX_DESC_NEXT_DESC_OFFSET 40
++#endif
++
++//
++//defined for TX DESC Operation
++//
++
++#define MAX_TID (15)
++
++//OFFSET 0
++#define OFFSET_SZ 0
++#define OFFSET_SHT 16
++#define BMC BIT(24)
++#define LSG BIT(26)
++#define FSG BIT(27)
++#define OWN BIT(31)
++
++//OFFSET 4
++#define PKT_OFFSET_SZ 0
++#define BK BIT(6)
++#define QSEL_SHT 8
++#define Rate_ID_SHT 16
++#define NAVUSEHDR BIT(20)
++#define PKT_OFFSET_SHT 26
++#define HWPC BIT(31)
++
++//OFFSET 8
++#define AGG_EN BIT(29)
++
++//OFFSET 12
++#define SEQ_SHT 16
++
++//OFFSET 16
++#define QoS BIT(6)
++#define HW_SEQ_EN BIT(7)
++#define USERATE BIT(8)
++#define DISDATAFB BIT(10)
++#define DATA_SHORT BIT(24)
++#define DATA_BW BIT(25)
++
++//OFFSET 20
++#define SGI BIT(6)
++
++struct tx_desc{
++
++ //DWORD 0
++ unsigned int txdw0;
++
++ unsigned int txdw1;
++
++ unsigned int txdw2;
++
++ unsigned int txdw3;
++
++ unsigned int txdw4;
++
++ unsigned int txdw5;
++
++ unsigned int txdw6;
++
++ unsigned int txdw7;
++#ifdef CONFIG_PCI_HCI
++ unsigned int txdw8;
++
++ unsigned int txdw9;
++
++ unsigned int txdw10;
++
++ unsigned int txdw11;
++
++ // 2008/05/15 MH Because PCIE HW memory R/W 4K limit. And now, our descriptor
++ // size is 40 bytes. If you use more than 102 descriptor( 103*40>4096), HW will execute
++ // memoryR/W CRC error. And then all DMA fetch will fail. We must decrease descriptor
++ // number or enlarge descriptor size as 64 bytes.
++ unsigned int txdw12;
++
++ unsigned int txdw13;
++
++ unsigned int txdw14;
++
++ unsigned int txdw15;
++#endif
++};
++
++
++union txdesc {
++ struct tx_desc txdesc;
++ unsigned int value[TXDESC_SIZE>>2];
++};
++
++#ifdef CONFIG_PCI_HCI
++#define PCI_MAX_TX_QUEUE_COUNT 8
++
++struct rtw_tx_ring {
++ struct tx_desc *desc;
++ dma_addr_t dma;
++ unsigned int idx;
++ unsigned int entries;
++ _queue queue;
++ u32 qlen;
++};
++#endif
++
++struct hw_xmit {
++ //_lock xmit_lock;
++ //_list pending;
++ _queue *sta_queue;
++ //struct hw_txqueue *phwtxqueue;
++ //sint txcmdcnt;
++ int accnt;
++};
++
++#if 0
++struct pkt_attrib
++{
++ u8 type;
++ u8 subtype;
++ u8 bswenc;
++ u8 dhcp_pkt;
++ u16 ether_type;
++ int pktlen; //the original 802.3 pkt raw_data len (not include ether_hdr data)
++ int pkt_hdrlen; //the original 802.3 pkt header len
++ int hdrlen; //the WLAN Header Len
++ int nr_frags;
++ int last_txcmdsz;
++ int encrypt; //when 0 indicate no encrypt. when non-zero, indicate the encrypt algorith
++ u8 iv[8];
++ int iv_len;
++ u8 icv[8];
++ int icv_len;
++ int priority;
++ int ack_policy;
++ int mac_id;
++ int vcs_mode; //virtual carrier sense method
++
++ u8 dst[ETH_ALEN];
++ u8 src[ETH_ALEN];
++ u8 ta[ETH_ALEN];
++ u8 ra[ETH_ALEN];
++
++ u8 key_idx;
++
++ u8 qos_en;
++ u8 ht_en;
++ u8 raid;//rate adpative id
++ u8 bwmode;
++ u8 ch_offset;//PRIME_CHNL_OFFSET
++ u8 sgi;//short GI
++ u8 ampdu_en;//tx ampdu enable
++ u8 mdata;//more data bit
++ u8 eosp;
++
++ u8 pctrl;//per packet txdesc control enable
++ u8 triggered;//for ap mode handling Power Saving sta
++
++ u32 qsel;
++ u16 seqnum;
++
++ struct sta_info * psta;
++#ifdef CONFIG_TCP_CSUM_OFFLOAD_TX
++ u8 hw_tcp_csum;
++#endif
++};
++#else
++//reduce size
++struct pkt_attrib
++{
++ u8 type;
++ u8 subtype;
++ u8 bswenc;
++ u8 dhcp_pkt;
++ u16 ether_type;
++ u16 seqnum;
++ u16 pkt_hdrlen; //the original 802.3 pkt header len
++ u16 hdrlen; //the WLAN Header Len
++ u32 pktlen; //the original 802.3 pkt raw_data len (not include ether_hdr data)
++ u32 last_txcmdsz;
++ u8 nr_frags;
++ u8 encrypt; //when 0 indicate no encrypt. when non-zero, indicate the encrypt algorith
++ u8 iv_len;
++ u8 icv_len;
++ u8 iv[8];
++ u8 icv[8];
++ u8 priority;
++ u8 ack_policy;
++ u8 mac_id;
++ u8 vcs_mode; //virtual carrier sense method
++ u8 dst[ETH_ALEN];
++ u8 src[ETH_ALEN];
++ u8 ta[ETH_ALEN];
++ u8 ra[ETH_ALEN];
++ u8 key_idx;
++ u8 qos_en;
++ u8 ht_en;
++ u8 raid;//rate adpative id
++ u8 bwmode;
++ u8 ch_offset;//PRIME_CHNL_OFFSET
++ u8 sgi;//short GI
++ u8 ampdu_en;//tx ampdu enable
++ u8 mdata;//more data bit
++ u8 pctrl;//per packet txdesc control enable
++ u8 triggered;//for ap mode handling Power Saving sta
++ u8 qsel;
++ u8 eosp;
++ u8 rate;
++ u8 intel_proxim;
++ u8 retry_ctrl;
++ struct sta_info * psta;
++#ifdef CONFIG_TCP_CSUM_OFFLOAD_TX
++ u8 hw_tcp_csum;
++#endif
++ union Keytype dot11tkiptxmickey;
++ //union Keytype dot11tkiprxmickey;
++ union Keytype dot118021x_UncstKey;
++};
++#endif
++
++#ifdef PLATFORM_FREEBSD
++#define ETH_ALEN 6 /* Octets in one ethernet addr */
++#define ETH_HLEN 14 /* Total octets in header. */
++#define ETH_P_IP 0x0800 /* Internet Protocol packet */
++
++/*struct rtw_ieee80211_hdr {
++ uint16_t frame_control;
++ uint16_t duration_id;
++ u8 addr1[6];
++ u8 addr2[6];
++ u8 addr3[6];
++ uint16_t seq_ctrl;
++ u8 addr4[6];
++} ;*/
++#endif //PLATFORM_FREEBSD
++
++#define WLANHDR_OFFSET 64
++
++#define NULL_FRAMETAG (0x0)
++#define DATA_FRAMETAG 0x01
++#define L2_FRAMETAG 0x02
++#define MGNT_FRAMETAG 0x03
++#define AMSDU_FRAMETAG 0x04
++
++#define EII_FRAMETAG 0x05
++#define IEEE8023_FRAMETAG 0x06
++
++#define MP_FRAMETAG 0x07
++
++#define TXAGG_FRAMETAG 0x08
++
++struct submit_ctx{
++ u32 submit_time; /* */
++ u32 timeout_ms; /* <0: not synchronous, 0: wait forever, >0: up to ms waiting */
++ int status; /* status for operation */
++#ifdef PLATFORM_LINUX
++ struct completion done;
++#endif
++};
++
++enum {
++ RTW_SCTX_SUBMITTED = -1,
++ RTW_SCTX_DONE_SUCCESS = 0,
++ RTW_SCTX_DONE_UNKNOWN,
++ RTW_SCTX_DONE_TIMEOUT,
++ RTW_SCTX_DONE_BUF_ALLOC,
++ RTW_SCTX_DONE_BUF_FREE,
++ RTW_SCTX_DONE_WRITE_PORT_ERR,
++ RTW_SCTX_DONE_TX_DESC_NA,
++ RTW_SCTX_DONE_TX_DENY,
++ RTW_SCTX_DONE_CCX_PKT_FAIL,
++ RTW_SCTX_DONE_DRV_STOP,
++ RTW_SCTX_DONE_DEV_REMOVE,
++};
++
++
++void rtw_sctx_init(struct submit_ctx *sctx, int timeout_ms);
++int rtw_sctx_wait(struct submit_ctx *sctx);
++void rtw_sctx_done_err(struct submit_ctx **sctx, int status);
++void rtw_sctx_done(struct submit_ctx **sctx);
++
++struct xmit_buf
++{
++ _list list;
++
++ _adapter *padapter;
++
++ u8 *pallocated_buf;
++
++ u8 *pbuf;
++
++ void *priv_data;
++
++ u16 ext_tag; // 0: Normal xmitbuf, 1: extension xmitbuf.
++ u16 flags;
++ u32 alloc_sz;
++
++ struct submit_ctx *sctx;
++
++#ifdef CONFIG_USB_HCI
++
++ u32 sz[8];
++
++#if defined(PLATFORM_OS_XP)||defined(PLATFORM_LINUX) || defined(PLATFORM_FREEBSD)
++ PURB pxmit_urb[8];
++ dma_addr_t dma_transfer_addr; /* (in) dma addr for transfer_buffer */
++#endif
++
++#ifdef PLATFORM_OS_XP
++ PIRP pxmit_irp[8];
++#endif
++
++#ifdef PLATFORM_OS_CE
++ USB_TRANSFER usb_transfer_write_port;
++#endif
++
++ u8 bpending[8];
++
++ sint last[8];
++
++#endif
++
++#ifdef CONFIG_SDIO_HCI
++ u32 len;
++ u8 *phead;
++ u8 *pdata;
++ u8 *ptail;
++ u8 *pend;
++ u32 ff_hwaddr;
++#ifdef PLATFORM_OS_XP
++ PMDL pxmitbuf_mdl;
++ PIRP pxmitbuf_irp;
++ PSDBUS_REQUEST_PACKET pxmitbuf_sdrp;
++#endif
++#endif
++
++#ifdef CONFIG_PCI_HCI
++ u32 len;
++#endif
++
++#ifdef DBG_XMIT_BUF
++ u8 no;
++#endif
++
++};
++
++struct xmit_frame
++{
++ _list list;
++
++ struct pkt_attrib attrib;
++
++ _pkt *pkt;
++
++ int frame_tag;
++
++ _adapter *padapter;
++
++ u8 *buf_addr;
++
++ struct xmit_buf *pxmitbuf;
++
++#ifdef CONFIG_SDIO_HCI
++ u8 pg_num;
++ u8 agg_num;
++#endif
++
++#ifdef CONFIG_USB_HCI
++#ifdef CONFIG_USB_TX_AGGREGATION
++ u8 agg_num;
++#endif
++ u8 pkt_offset;
++#ifdef CONFIG_RTL8192D
++ u8 EMPktNum;
++ u16 EMPktLen[5];//The max value by HW
++#endif
++#endif
++#ifdef CONFIG_XMIT_ACK
++ u8 ack_report;
++#endif
++
++ u8 *alloc_addr; /* the actual address this xmitframe allocated */
++ u8 ext_tag; /* 0:data, 1:mgmt */
++
++};
++
++struct tx_servq {
++ _list tx_pending;
++ _queue sta_pending;
++ int qcnt;
++};
++
++
++
++struct sta_xmit_priv
++{
++ _lock lock;
++ sint option;
++ sint apsd_setting; //When bit mask is on, the associated edca queue supports APSD.
++
++
++ //struct tx_servq blk_q[MAX_NUMBLKS];
++ struct tx_servq be_q; //priority == 0,3
++ struct tx_servq bk_q; //priority == 1,2
++ struct tx_servq vi_q; //priority == 4,5
++ struct tx_servq vo_q; //priority == 6,7
++ _list legacy_dz;
++ _list apsd;
++
++ u16 txseq_tid[16];
++
++ //uint sta_tx_bytes;
++ //u64 sta_tx_pkts;
++ //uint sta_tx_fail;
++
++};
++
++
++struct hw_txqueue {
++ volatile sint head;
++ volatile sint tail;
++ volatile sint free_sz; //in units of 64 bytes
++ volatile sint free_cmdsz;
++ volatile sint txsz[8];
++ uint ff_hwaddr;
++ uint cmd_hwaddr;
++ sint ac_tag;
++};
++
++
++struct xmit_priv {
++
++ _lock lock;
++
++ _sema xmit_sema;
++ _sema terminate_xmitthread_sema;
++
++ //_queue blk_strms[MAX_NUMBLKS];
++ _queue be_pending;
++ _queue bk_pending;
++ _queue vi_pending;
++ _queue vo_pending;
++ _queue bm_pending;
++
++ //_queue legacy_dz_queue;
++ //_queue apsd_queue;
++
++ u8 *pallocated_frame_buf;
++ u8 *pxmit_frame_buf;
++ uint free_xmitframe_cnt;
++ _queue free_xmit_queue;
++
++ //uint mapping_addr;
++ //uint pkt_sz;
++
++ u8 *xframe_ext_alloc_addr;
++ u8 *xframe_ext;
++ uint free_xframe_ext_cnt;
++ _queue free_xframe_ext_queue;
++
++ //struct hw_txqueue be_txqueue;
++ //struct hw_txqueue bk_txqueue;
++ //struct hw_txqueue vi_txqueue;
++ //struct hw_txqueue vo_txqueue;
++ //struct hw_txqueue bmc_txqueue;
++
++ uint frag_len;
++
++ _adapter *adapter;
++
++ u8 vcs_setting;
++ u8 vcs;
++ u8 vcs_type;
++ //u16 rts_thresh;
++
++ u64 tx_bytes;
++ u64 tx_pkts;
++ u64 tx_drop;
++ u64 last_tx_bytes;
++ u64 last_tx_pkts;
++
++ struct hw_xmit *hwxmits;
++ u8 hwxmit_entry;
++
++#ifdef CONFIG_USB_HCI
++ _sema tx_retevt;//all tx return event;
++ u8 txirp_cnt;//
++
++#ifdef PLATFORM_OS_CE
++ USB_TRANSFER usb_transfer_write_port;
++// USB_TRANSFER usb_transfer_write_mem;
++#endif
++#ifdef PLATFORM_LINUX
++ struct tasklet_struct xmit_tasklet;
++#endif
++#ifdef PLATFORM_FREEBSD
++ struct task xmit_tasklet;
++#endif
++ //per AC pending irp
++ int beq_cnt;
++ int bkq_cnt;
++ int viq_cnt;
++ int voq_cnt;
++
++#endif
++
++#ifdef CONFIG_PCI_HCI
++ // Tx
++ struct rtw_tx_ring tx_ring[PCI_MAX_TX_QUEUE_COUNT];
++ int txringcount[PCI_MAX_TX_QUEUE_COUNT];
++#ifdef PLATFORM_LINUX
++ struct tasklet_struct xmit_tasklet;
++#endif
++#endif
++
++ _queue free_xmitbuf_queue;
++ _queue pending_xmitbuf_queue;
++ u8 *pallocated_xmitbuf;
++ u8 *pxmitbuf;
++ uint free_xmitbuf_cnt;
++
++ _queue free_xmit_extbuf_queue;
++ u8 *pallocated_xmit_extbuf;
++ u8 *pxmit_extbuf;
++ uint free_xmit_extbuf_cnt;
++
++ u16 nqos_ssn;
++
++#ifdef CONFIG_XMIT_ACK
++ int ack_tx;
++ _mutex ack_tx_mutex;
++ struct submit_ctx ack_tx_ops;
++#endif
++ _lock lock_sctx;
++};
++
++extern struct xmit_buf *rtw_alloc_xmitbuf_ext(struct xmit_priv *pxmitpriv);
++extern s32 rtw_free_xmitbuf_ext(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
++
++extern struct xmit_buf *rtw_alloc_xmitbuf(struct xmit_priv *pxmitpriv);
++extern s32 rtw_free_xmitbuf(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
++
++void rtw_count_tx_stats(_adapter *padapter, struct xmit_frame *pxmitframe, int sz);
++extern void rtw_update_protection(_adapter *padapter, u8 *ie, uint ie_len);
++extern s32 rtw_make_wlanhdr(_adapter *padapter, u8 *hdr, struct pkt_attrib *pattrib);
++extern s32 rtw_put_snap(u8 *data, u16 h_proto);
++
++extern struct xmit_frame *rtw_alloc_xmitframe(struct xmit_priv *pxmitpriv);
++struct xmit_frame *rtw_alloc_xmitframe_ext(struct xmit_priv *pxmitpriv);
++struct xmit_frame *rtw_alloc_xmitframe_once(struct xmit_priv *pxmitpriv);
++extern s32 rtw_free_xmitframe(struct xmit_priv *pxmitpriv, struct xmit_frame *pxmitframe);
++extern void rtw_free_xmitframe_queue(struct xmit_priv *pxmitpriv, _queue *pframequeue);
++struct tx_servq *rtw_get_sta_pending(_adapter *padapter, struct sta_info *psta, sint up, u8 *ac);
++extern s32 rtw_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
++extern struct xmit_frame* rtw_dequeue_xframe(struct xmit_priv *pxmitpriv, struct hw_xmit *phwxmit_i, sint entry);
++
++extern s32 rtw_xmit_classifier(_adapter *padapter, struct xmit_frame *pxmitframe);
++extern thread_return rtw_xmit_thread(thread_context context);
++extern u32 rtw_calculate_wlan_pkt_size_by_attribue(struct pkt_attrib *pattrib);
++#define rtw_wlan_pkt_size(f) rtw_calculate_wlan_pkt_size_by_attribue(&f->attrib)
++extern s32 rtw_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxmitframe);
++#ifdef CONFIG_IEEE80211W
++extern s32 rtw_mgmt_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxmitframe);
++#endif //CONFIG_IEEE80211W
++#ifdef CONFIG_TDLS
++s32 rtw_xmit_tdls_coalesce(_adapter *padapter, struct xmit_frame *pxmitframe, u8 action);
++#endif //CONFIG_TDLS
++s32 _rtw_init_hw_txqueue(struct hw_txqueue* phw_txqueue, u8 ac_tag);
++void _rtw_init_sta_xmit_priv(struct sta_xmit_priv *psta_xmitpriv);
++
++
++s32 rtw_txframes_pending(_adapter *padapter);
++s32 rtw_txframes_sta_ac_pending(_adapter *padapter, struct pkt_attrib *pattrib);
++void rtw_init_hwxmits(struct hw_xmit *phwxmit, sint entry);
++
++
++s32 _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, _adapter *padapter);
++void _rtw_free_xmit_priv (struct xmit_priv *pxmitpriv);
++
++
++void rtw_alloc_hwxmits(_adapter *padapter);
++void rtw_free_hwxmits(_adapter *padapter);
++
++
++s32 rtw_xmit(_adapter *padapter, _pkt **pkt);
++
++#if defined(CONFIG_AP_MODE) || defined(CONFIG_TDLS)
++sint xmitframe_enqueue_for_sleeping_sta(_adapter *padapter, struct xmit_frame *pxmitframe);
++void stop_sta_xmit(_adapter *padapter, struct sta_info *psta);
++void wakeup_sta_to_xmit(_adapter *padapter, struct sta_info *psta);
++void xmit_delivery_enabled_frames(_adapter *padapter, struct sta_info *psta);
++#endif
++
++u8 qos_acm(u8 acm_mask, u8 priority);
++
++#ifdef CONFIG_XMIT_ACK
++int rtw_ack_tx_wait(struct xmit_priv *pxmitpriv, u32 timeout_ms);
++void rtw_ack_tx_done(struct xmit_priv *pxmitpriv, int status);
++#endif //CONFIG_XMIT_ACK
++
++
++//include after declaring struct xmit_buf, in order to avoid warning
++#include <xmit_osdep.h>
++
++#endif //_RTL871X_XMIT_H_
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/sta_info.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/sta_info.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/sta_info.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/sta_info.h 2015-07-28 01:20:58.321597318 +0200
+@@ -0,0 +1,431 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef __STA_INFO_H_
++#define __STA_INFO_H_
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++#include <wifi.h>
++
++#define IBSS_START_MAC_ID 2
++#define NUM_STA 32
++#define NUM_ACL 16
++
++
++//if mode ==0, then the sta is allowed once the addr is hit.
++//if mode ==1, then the sta is rejected once the addr is non-hit.
++struct rtw_wlan_acl_node {
++ _list list;
++ u8 addr[ETH_ALEN];
++ u8 valid;
++};
++
++//mode=0, disable
++//mode=1, accept unless in deny list
++//mode=2, deny unless in accept list
++struct wlan_acl_pool {
++ int mode;
++ int num;
++ struct rtw_wlan_acl_node aclnode[NUM_ACL];
++ _queue acl_node_q;
++};
++
++typedef struct _RSSI_STA{
++ s32 UndecoratedSmoothedPWDB;
++ s32 UndecoratedSmoothedCCK;
++ s32 UndecoratedSmoothedOFDM;
++ u64 PacketMap;
++ u8 ValidBit;
++}RSSI_STA, *PRSSI_STA;
++
++struct stainfo_stats {
++
++ u64 rx_mgnt_pkts;
++ u64 rx_beacon_pkts;
++ u64 rx_probereq_pkts;
++ u64 rx_probersp_pkts;
++ u64 rx_probersp_bm_pkts;
++ u64 rx_probersp_uo_pkts;
++ u64 rx_ctrl_pkts;
++ u64 rx_data_pkts;
++
++ u64 last_rx_mgnt_pkts;
++ u64 last_rx_beacon_pkts;
++ u64 last_rx_probereq_pkts;
++ u64 last_rx_probersp_pkts;
++ u64 last_rx_probersp_bm_pkts;
++ u64 last_rx_probersp_uo_pkts;
++ u64 last_rx_ctrl_pkts;
++ u64 last_rx_data_pkts;
++
++ u64 rx_bytes;
++ u64 rx_drops;
++
++ u64 tx_pkts;
++ u64 tx_bytes;
++ u64 tx_drops;
++
++};
++
++#ifdef CONFIG_TDLS
++struct TDLS_PeerKey {
++ u8 kck[16]; /* TPK-KCK */
++ u8 tk[16]; /* TPK-TK; only CCMP will be used */
++} ;
++#endif //CONFIG_TDLS
++
++struct sta_info {
++
++ _lock lock;
++ _list list; //free_sta_queue
++ _list hash_list; //sta_hash
++ //_list asoc_list; //20061114
++ //_list sleep_list;//sleep_q
++ //_list wakeup_list;//wakeup_q
++
++ struct sta_xmit_priv sta_xmitpriv;
++ struct sta_recv_priv sta_recvpriv;
++
++ _queue sleep_q;
++ unsigned int sleepq_len;
++
++ uint state;
++ uint aid;
++ uint mac_id;
++ uint qos_option;
++ u8 hwaddr[ETH_ALEN];
++
++ uint ieee8021x_blocked; //0: allowed, 1:blocked
++ uint dot118021XPrivacy; //aes, tkip...
++ union Keytype dot11tkiptxmickey;
++ union Keytype dot11tkiprxmickey;
++ union Keytype dot118021x_UncstKey;
++ union pn48 dot11txpn; // PN48 used for Unicast xmit.
++#ifdef CONFIG_IEEE80211W
++ union pn48 dot11wtxpn; // PN48 used for Unicast mgmt xmit.
++#endif //CONFIG_IEEE80211W
++ union pn48 dot11rxpn; // PN48 used for Unicast recv.
++
++
++ u8 bssrateset[16];
++ u32 bssratelen;
++ s32 rssi;
++ s32 signal_quality;
++
++ u8 cts2self;
++ u8 rtsen;
++
++ u8 raid;
++ u8 init_rate;
++ u32 ra_mask;
++ struct stainfo_stats sta_stats;
++
++#ifdef CONFIG_TDLS
++ u32 tdls_sta_state;
++ u8 dialog;
++ u8 SNonce[32];
++ u8 ANonce[32];
++ u32 TDLS_PeerKey_Lifetime;
++ u16 TPK_count;
++ _timer TPK_timer;
++ struct TDLS_PeerKey tpk;
++ _adapter *padapter;
++ u16 stat_code;
++ u8 off_ch;
++ u16 ch_switch_time;
++ u16 ch_switch_timeout;
++ u8 option;
++ _timer option_timer;
++ _timer base_ch_timer;
++ _timer off_ch_timer;
++
++ _timer handshake_timer;
++ _timer alive_timer1;
++ _timer alive_timer2;
++ u8 timer_flag;
++ u8 alive_count;
++#endif //CONFIG_TDLS
++
++ //for A-MPDU TX, ADDBA timeout check
++ _timer addba_retry_timer;
++
++ //for A-MPDU Rx reordering buffer control
++ struct recv_reorder_ctrl recvreorder_ctrl[16];
++
++ //for A-MPDU Tx
++ //unsigned char ampdu_txen_bitmap;
++ u16 BA_starting_seqctrl[16];
++
++
++#ifdef CONFIG_80211N_HT
++ struct ht_priv htpriv;
++#endif
++
++ //Notes:
++ //STA_Mode:
++ //curr_network(mlme_priv/security_priv/qos/ht) + sta_info: (STA & AP) CAP/INFO
++ //scan_q: AP CAP/INFO
++
++ //AP_Mode:
++ //curr_network(mlme_priv/security_priv/qos/ht) : AP CAP/INFO
++ //sta_info: (AP & STA) CAP/INFO
++
++#ifdef CONFIG_AP_MODE
++
++ _list asoc_list;
++ _list auth_list;
++
++ unsigned int expire_to;
++ unsigned int auth_seq;
++ unsigned int authalg;
++ unsigned char chg_txt[128];
++
++ u16 capability;
++ int flags;
++
++ int dot8021xalg;//0:disable, 1:psk, 2:802.1x
++ int wpa_psk;//0:disable, bit(0): WPA, bit(1):WPA2
++ int wpa_group_cipher;
++ int wpa2_group_cipher;
++ int wpa_pairwise_cipher;
++ int wpa2_pairwise_cipher;
++
++ u8 bpairwise_key_installed;
++
++#ifdef CONFIG_NATIVEAP_MLME
++ u8 wpa_ie[32];
++
++ u8 nonerp_set;
++ u8 no_short_slot_time_set;
++ u8 no_short_preamble_set;
++ u8 no_ht_gf_set;
++ u8 no_ht_set;
++ u8 ht_20mhz_set;
++#endif // CONFIG_NATIVEAP_MLME
++
++ unsigned int tx_ra_bitmap;
++ u8 qos_info;
++
++ u8 max_sp_len;
++ u8 uapsd_bk;//BIT(0): Delivery enabled, BIT(1): Trigger enabled
++ u8 uapsd_be;
++ u8 uapsd_vi;
++ u8 uapsd_vo;
++
++ u8 has_legacy_ac;
++ unsigned int sleepq_ac_len;
++
++#ifdef CONFIG_P2P
++ //p2p priv data
++ u8 is_p2p_device;
++ u8 p2p_status_code;
++
++ //p2p client info
++ u8 dev_addr[ETH_ALEN];
++ //u8 iface_addr[ETH_ALEN];//= hwaddr[ETH_ALEN]
++ u8 dev_cap;
++ u16 config_methods;
++ u8 primary_dev_type[8];
++ u8 num_of_secdev_type;
++ u8 secdev_types_list[32];// 32/8 == 4;
++ u16 dev_name_len;
++ u8 dev_name[32];
++#endif //CONFIG_P2P
++
++#ifdef CONFIG_TX_MCAST2UNI
++ u8 under_exist_checking;
++#endif // CONFIG_TX_MCAST2UNI
++
++ u8 keep_alive_trycnt;
++
++#endif // CONFIG_AP_MODE
++
++#ifdef CONFIG_IOCTL_CFG80211
++ u8 *passoc_req;
++ u32 assoc_req_len;
++#endif
++
++ //for DM
++ RSSI_STA rssi_stat;
++
++ /* To store the sequence number of received management frame */
++ u16 RxMgmtFrameSeqNum;
++};
++
++#define sta_rx_pkts(sta) \
++ (sta->sta_stats.rx_mgnt_pkts \
++ + sta->sta_stats.rx_ctrl_pkts \
++ + sta->sta_stats.rx_data_pkts)
++
++#define sta_last_rx_pkts(sta) \
++ (sta->sta_stats.last_rx_mgnt_pkts \
++ + sta->sta_stats.last_rx_ctrl_pkts \
++ + sta->sta_stats.last_rx_data_pkts)
++
++#define sta_rx_data_pkts(sta) \
++ (sta->sta_stats.rx_data_pkts)
++
++#define sta_last_rx_data_pkts(sta) \
++ (sta->sta_stats.last_rx_data_pkts)
++
++#define sta_rx_mgnt_pkts(sta) \
++ (sta->sta_stats.rx_mgnt_pkts)
++
++#define sta_last_rx_mgnt_pkts(sta) \
++ (sta->sta_stats.last_rx_mgnt_pkts)
++
++#define sta_rx_beacon_pkts(sta) \
++ (sta->sta_stats.rx_beacon_pkts)
++
++#define sta_last_rx_beacon_pkts(sta) \
++ (sta->sta_stats.last_rx_beacon_pkts)
++
++#define sta_rx_probereq_pkts(sta) \
++ (sta->sta_stats.rx_probereq_pkts)
++
++#define sta_last_rx_probereq_pkts(sta) \
++ (sta->sta_stats.last_rx_probereq_pkts)
++
++#define sta_rx_probersp_pkts(sta) \
++ (sta->sta_stats.rx_probersp_pkts)
++
++#define sta_last_rx_probersp_pkts(sta) \
++ (sta->sta_stats.last_rx_probersp_pkts)
++
++#define sta_rx_probersp_bm_pkts(sta) \
++ (sta->sta_stats.rx_probersp_bm_pkts)
++
++#define sta_last_rx_probersp_bm_pkts(sta) \
++ (sta->sta_stats.last_rx_probersp_bm_pkts)
++
++#define sta_rx_probersp_uo_pkts(sta) \
++ (sta->sta_stats.rx_probersp_uo_pkts)
++
++#define sta_last_rx_probersp_uo_pkts(sta) \
++ (sta->sta_stats.last_rx_probersp_uo_pkts)
++
++#define sta_update_last_rx_pkts(sta) \
++ do { \
++ sta->sta_stats.last_rx_mgnt_pkts = sta->sta_stats.rx_mgnt_pkts; \
++ sta->sta_stats.last_rx_beacon_pkts = sta->sta_stats.rx_beacon_pkts; \
++ sta->sta_stats.last_rx_probereq_pkts = sta->sta_stats.rx_probereq_pkts; \
++ sta->sta_stats.last_rx_probersp_pkts = sta->sta_stats.rx_probersp_pkts; \
++ sta->sta_stats.last_rx_probersp_bm_pkts = sta->sta_stats.rx_probersp_bm_pkts; \
++ sta->sta_stats.last_rx_probersp_uo_pkts = sta->sta_stats.rx_probersp_uo_pkts; \
++ sta->sta_stats.last_rx_ctrl_pkts = sta->sta_stats.rx_ctrl_pkts; \
++ sta->sta_stats.last_rx_data_pkts = sta->sta_stats.rx_data_pkts; \
++ } while(0)
++
++#define STA_RX_PKTS_ARG(sta) \
++ sta->sta_stats.rx_mgnt_pkts \
++ , sta->sta_stats.rx_ctrl_pkts \
++ , sta->sta_stats.rx_data_pkts
++
++#define STA_LAST_RX_PKTS_ARG(sta) \
++ sta->sta_stats.last_rx_mgnt_pkts \
++ , sta->sta_stats.last_rx_ctrl_pkts \
++ , sta->sta_stats.last_rx_data_pkts
++
++#define STA_RX_PKTS_DIFF_ARG(sta) \
++ sta->sta_stats.rx_mgnt_pkts - sta->sta_stats.last_rx_mgnt_pkts \
++ , sta->sta_stats.rx_ctrl_pkts - sta->sta_stats.last_rx_ctrl_pkts \
++ , sta->sta_stats.rx_data_pkts -sta->sta_stats.last_rx_data_pkts
++
++#define STA_PKTS_FMT "(m:%llu, c:%llu, d:%llu)"
++
++struct sta_priv {
++
++ u8 *pallocated_stainfo_buf;
++ u8 *pstainfo_buf;
++ _queue free_sta_queue;
++
++ _lock sta_hash_lock;
++ _list sta_hash[NUM_STA];
++ int asoc_sta_count;
++ _queue sleep_q;
++ _queue wakeup_q;
++
++ _adapter *padapter;
++
++
++#ifdef CONFIG_AP_MODE
++ _list asoc_list;
++ _list auth_list;
++ _lock asoc_list_lock;
++ _lock auth_list_lock;
++ u8 asoc_list_cnt;
++ u8 auth_list_cnt;
++
++ unsigned int auth_to; //sec, time to expire in authenticating.
++ unsigned int assoc_to; //sec, time to expire before associating.
++ unsigned int expire_to; //sec , time to expire after associated.
++
++ /* pointers to STA info; based on allocated AID or NULL if AID free
++ * AID is in the range 1-2007, so sta_aid[0] corresponders to AID 1
++ * and so on
++ */
++ struct sta_info *sta_aid[NUM_STA];
++
++ u16 sta_dz_bitmap;//only support 15 stations, staion aid bitmap for sleeping sta.
++ u16 tim_bitmap;//only support 15 stations, aid=0~15 mapping bit0~bit15
++
++ u16 max_num_sta;
++
++ struct wlan_acl_pool acl_list;
++#endif
++
++};
++
++
++__inline static u32 wifi_mac_hash(u8 *mac)
++{
++ u32 x;
++
++ x = mac[0];
++ x = (x << 2) ^ mac[1];
++ x = (x << 2) ^ mac[2];
++ x = (x << 2) ^ mac[3];
++ x = (x << 2) ^ mac[4];
++ x = (x << 2) ^ mac[5];
++
++ x ^= x >> 8;
++ x = x & (NUM_STA - 1);
++
++ return x;
++}
++
++
++extern u32 _rtw_init_sta_priv(struct sta_priv *pstapriv);
++extern u32 _rtw_free_sta_priv(struct sta_priv *pstapriv);
++
++#define stainfo_offset_valid(offset) (offset < NUM_STA && offset >= 0)
++int rtw_stainfo_offset(struct sta_priv *stapriv, struct sta_info *sta);
++struct sta_info *rtw_get_stainfo_by_offset(struct sta_priv *stapriv, int offset);
++
++extern struct sta_info *rtw_alloc_stainfo(struct sta_priv *pstapriv, u8 *hwaddr);
++extern u32 rtw_free_stainfo(_adapter *padapter , struct sta_info *psta);
++extern void rtw_free_all_stainfo(_adapter *padapter);
++extern struct sta_info *rtw_get_stainfo(struct sta_priv *pstapriv, u8 *hwaddr);
++extern u32 rtw_init_bcmc_stainfo(_adapter* padapter);
++extern struct sta_info* rtw_get_bcmc_stainfo(_adapter* padapter);
++extern u8 rtw_access_ctrl(_adapter *padapter, u8 *mac_addr);
++
++#endif //_STA_INFO_H_
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/usb_hal.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/usb_hal.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/usb_hal.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/usb_hal.h 2015-07-28 01:20:58.321597318 +0200
+@@ -0,0 +1,36 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef __USB_HAL_H__
++#define __USB_HAL_H__
++
++
++void rtl8192cu_set_hal_ops(_adapter * padapter);
++
++void rtl8192du_set_hal_ops(_adapter * padapter);
++#ifdef CONFIG_INTEL_PROXIM
++extern _adapter *rtw_usb_get_sw_pointer(void);
++#endif //CONFIG_INTEL_PROXIM
++#ifdef CONFIG_WOWLAN
++#ifdef CONFIG_WOWLAN_MANUAL
++extern int rtw_suspend_toshiba(PADAPTER Adapter);
++extern int rtw_resume_toshiba(PADAPTER Adapter);
++#endif // CONFIG_WOWLAN_MANUAL
++#endif //CONFIG_WOWLAN
++#endif //__USB_HAL_H__
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/usb_ops.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/usb_ops.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/usb_ops.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/usb_ops.h 2015-07-28 01:20:58.321597318 +0200
+@@ -0,0 +1,109 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef __USB_OPS_H_
++#define __USB_OPS_H_
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++#include <osdep_intf.h>
++
++#define REALTEK_USB_VENQT_READ 0xC0
++#define REALTEK_USB_VENQT_WRITE 0x40
++#define REALTEK_USB_VENQT_CMD_REQ 0x05
++#define REALTEK_USB_VENQT_CMD_IDX 0x00
++
++enum{
++ VENDOR_WRITE = 0x00,
++ VENDOR_READ = 0x01,
++};
++#define ALIGNMENT_UNIT 16
++#define MAX_VENDOR_REQ_CMD_SIZE 254 //8188cu SIE Support
++#define MAX_USB_IO_CTL_SIZE (MAX_VENDOR_REQ_CMD_SIZE +ALIGNMENT_UNIT)
++
++#ifdef PLATFORM_LINUX
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,12))
++#define rtw_usb_control_msg(dev, pipe, request, requesttype, value, index, data, size, timeout_ms) \
++ usb_control_msg((dev), (pipe), (request), (requesttype), (value), (index), (data), (size), (timeout_ms))
++#define rtw_usb_bulk_msg(usb_dev, pipe, data, len, actual_length, timeout_ms) \
++ usb_bulk_msg((usb_dev), (pipe), (data), (len), (actual_length), (timeout_ms))
++#else
++#define rtw_usb_control_msg(dev, pipe, request, requesttype, value, index, data, size,timeout_ms) \
++ usb_control_msg((dev), (pipe), (request), (requesttype), (value), (index), (data), (size), \
++ ((timeout_ms) == 0) ||((timeout_ms)*HZ/1000>0)?((timeout_ms)*HZ/1000):1)
++#define rtw_usb_bulk_msg(usb_dev, pipe, data, len, actual_length, timeout_ms) \
++ usb_bulk_msg((usb_dev), (pipe), (data), (len), (actual_length), \
++ ((timeout_ms) == 0) ||((timeout_ms)*HZ/1000>0)?((timeout_ms)*HZ/1000):1)
++#endif
++#include <usb_ops_linux.h>
++#endif //PLATFORM_LINUX
++
++#ifdef CONFIG_RTL8192C
++void rtl8192cu_set_intf_ops(struct _io_ops *pops);
++#define usb_set_intf_ops rtl8192cu_set_intf_ops
++
++void rtl8192cu_recv_tasklet(void *priv);
++
++void rtl8192cu_xmit_tasklet(void *priv);
++#endif
++
++#ifdef CONFIG_RTL8192D
++void rtl8192du_set_intf_ops(struct _io_ops *pops);
++#define usb_set_intf_ops rtl8192du_set_intf_ops
++
++#ifndef PLATFORM_FREEBSD
++void rtl8192du_recv_tasklet(void *priv);
++#else // PLATFORM_FREEBSD
++void rtl8192du_recv_tasklet(void *priv, int npending);
++#ifdef CONFIG_RX_INDICATE_QUEUE
++void rtw_rx_indicate_tasklet(void *priv, int npending);
++#endif // CONFIG_RX_INDICATE_QUEUE
++#endif // PLATFORM_FREEBSD
++
++void rtl8192du_xmit_tasklet(void *priv);
++#endif
++
++/*
++* Increase and check if the continual_urb_error of this @param dvobjprive is larger than MAX_CONTINUAL_URB_ERR
++* @return _TRUE:
++* @return _FALSE:
++*/
++static inline int rtw_inc_and_chk_continual_urb_error(struct dvobj_priv *dvobj)
++{
++ int ret = _FALSE;
++ int value;
++ if( (value=ATOMIC_INC_RETURN(&dvobj->continual_urb_error)) > MAX_CONTINUAL_URB_ERR) {
++ DBG_871X("[dvobj:%p][ERROR] continual_urb_error:%d > %d\n", dvobj, value, MAX_CONTINUAL_URB_ERR);
++ ret = _TRUE;
++ } else {
++ //DBG_871X("[dvobj:%p] continual_urb_error:%d\n", dvobj, value);
++ }
++ return ret;
++}
++
++/*
++* Set the continual_urb_error of this @param dvobjprive to 0
++*/
++static inline void rtw_reset_continual_urb_error(struct dvobj_priv *dvobj)
++{
++ ATOMIC_SET(&dvobj->continual_urb_error, 0);
++}
++
++#endif //__USB_OPS_H_
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/usb_ops_linux.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/usb_ops_linux.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/usb_ops_linux.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/usb_ops_linux.h 2015-07-28 01:20:58.321597318 +0200
+@@ -0,0 +1,62 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef __USB_OPS_LINUX_H__
++#define __USB_OPS_LINUX_H__
++
++#define VENDOR_CMD_MAX_DATA_LEN 254
++
++#define RTW_USB_CONTROL_MSG_TIMEOUT_TEST 10//ms
++#define RTW_USB_CONTROL_MSG_TIMEOUT 500//ms
++
++#if defined(CONFIG_VENDOR_REQ_RETRY) && defined(CONFIG_USB_VENDOR_REQ_MUTEX)
++/* vendor req retry should be in the situation when each vendor req is atomically submitted from others */
++#define MAX_USBCTRL_VENDORREQ_TIMES 10
++#else
++#define MAX_USBCTRL_VENDORREQ_TIMES 1
++#endif
++
++#define RTW_USB_BULKOUT_TIMEOUT 5000//ms
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)) || (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,18))
++#define _usbctrl_vendorreq_async_callback(urb, regs) _usbctrl_vendorreq_async_callback(urb)
++#define usb_bulkout_zero_complete(purb, regs) usb_bulkout_zero_complete(purb)
++#define usb_write_mem_complete(purb, regs) usb_write_mem_complete(purb)
++#define usb_write_port_complete(purb, regs) usb_write_port_complete(purb)
++#define usb_read_port_complete(purb, regs) usb_read_port_complete(purb)
++#define usb_read_interrupt_complete(purb, regs) usb_read_interrupt_complete(purb)
++#endif
++
++#ifdef CONFIG_USB_SUPPORT_ASYNC_VDN_REQ
++int usb_async_write8(struct intf_hdl *pintfhdl, u32 addr, u8 val);
++int usb_async_write16(struct intf_hdl *pintfhdl, u32 addr, u16 val);
++int usb_async_write32(struct intf_hdl *pintfhdl, u32 addr, u32 val);
++#endif /* CONFIG_USB_SUPPORT_ASYNC_VDN_REQ */
++
++unsigned int ffaddr2pipehdl(struct dvobj_priv *pdvobj, u32 addr);
++
++void usb_read_mem(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem);
++void usb_write_mem(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *wmem);
++
++void usb_read_port_cancel(struct intf_hdl *pintfhdl);
++
++u32 usb_write_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *wmem);
++void usb_write_port_cancel(struct intf_hdl *pintfhdl);
++
++#endif
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/usb_osintf.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/usb_osintf.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/usb_osintf.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/usb_osintf.h 2015-07-28 01:20:58.321597318 +0200
+@@ -0,0 +1,37 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef __USB_OSINTF_H
++#define __USB_OSINTF_H
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++#include <usb_vendor_req.h>
++
++#define USBD_HALTED(Status) ((ULONG)(Status) >> 30 == 3)
++
++
++//uint usb_dvobj_init(_adapter * adapter);
++//void usb_dvobj_deinit(_adapter * adapter);
++
++u8 usbvendorrequest(struct dvobj_priv *pdvobjpriv, RT_USB_BREQUEST brequest, RT_USB_WVALUE wvalue, u8 windex, void* data, u8 datalen, u8 isdirectionin);
++
++
++#endif
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/usb_vendor_req.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/usb_vendor_req.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/usb_vendor_req.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/usb_vendor_req.h 2015-07-28 01:20:58.321597318 +0200
+@@ -0,0 +1,59 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef _USB_VENDOR_REQUEST_H_
++#define _USB_VENDOR_REQUEST_H_
++
++//4 Set/Get Register related wIndex/Data
++#define RT_USB_RESET_MASK_OFF 0
++#define RT_USB_RESET_MASK_ON 1
++#define RT_USB_SLEEP_MASK_OFF 0
++#define RT_USB_SLEEP_MASK_ON 1
++#define RT_USB_LDO_ON 1
++#define RT_USB_LDO_OFF 0
++
++//4 Set/Get SYSCLK related wValue or Data
++#define RT_USB_SYSCLK_32KHZ 0
++#define RT_USB_SYSCLK_40MHZ 1
++#define RT_USB_SYSCLK_60MHZ 2
++
++
++typedef enum _RT_USB_BREQUEST {
++ RT_USB_SET_REGISTER = 1,
++ RT_USB_SET_SYSCLK = 2,
++ RT_USB_GET_SYSCLK = 3,
++ RT_USB_GET_REGISTER = 4
++} RT_USB_BREQUEST;
++
++
++typedef enum _RT_USB_WVALUE {
++ RT_USB_RESET_MASK = 1,
++ RT_USB_SLEEP_MASK = 2,
++ RT_USB_USB_HRCPWM = 3,
++ RT_USB_LDO = 4,
++ RT_USB_BOOT_TYPE = 5
++} RT_USB_WVALUE;
++
++
++//BOOLEAN usbvendorrequest(PCE_USB_DEVICE CEdevice, RT_USB_BREQUEST bRequest, RT_USB_WVALUE wValue, UCHAR wIndex, PVOID Data, UCHAR DataLength, BOOLEAN isDirectionIn);
++//BOOLEAN CEusbGetStatusRequest(PCE_USB_DEVICE CEdevice, IN USHORT Op, IN USHORT Index, PVOID Data);
++//BOOLEAN CEusbFeatureRequest(PCE_USB_DEVICE CEdevice, IN USHORT Op, IN USHORT FeatureSelector, IN USHORT Index);
++//BOOLEAN CEusbGetDescriptorRequest(PCE_USB_DEVICE CEdevice, IN short urbLength, IN UCHAR DescriptorType, IN UCHAR Index, IN USHORT LanguageId, IN PVOID TransferBuffer, IN ULONG TransferBufferLength);
++
++#endif
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/wifi.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/wifi.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/wifi.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/wifi.h 2015-07-28 01:20:58.325583098 +0200
+@@ -0,0 +1,1245 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef _WIFI_H_
++#define _WIFI_H_
++
++#include <rtw_byteorder.h>
++
++#ifdef BIT
++//#error "BIT define occurred earlier elsewhere!\n"
++#undef BIT
++#endif
++#define BIT(x) (1 << (x))
++
++
++#define WLAN_ETHHDR_LEN 14
++#define WLAN_ETHADDR_LEN 6
++#define WLAN_IEEE_OUI_LEN 3
++#define WLAN_ADDR_LEN 6
++#define WLAN_CRC_LEN 4
++#define WLAN_BSSID_LEN 6
++#define WLAN_BSS_TS_LEN 8
++#define WLAN_HDR_A3_LEN 24
++#define WLAN_HDR_A4_LEN 30
++#define WLAN_HDR_A3_QOS_LEN 26
++#define WLAN_HDR_A4_QOS_LEN 32
++#define WLAN_SSID_MAXLEN 32
++#define WLAN_DATA_MAXLEN 2312
++
++#define WLAN_A3_PN_OFFSET 24
++#define WLAN_A4_PN_OFFSET 30
++
++#define WLAN_MIN_ETHFRM_LEN 60
++#define WLAN_MAX_ETHFRM_LEN 1514
++#define WLAN_ETHHDR_LEN 14
++
++#define P80211CAPTURE_VERSION 0x80211001
++
++#ifdef GREEN_HILL
++#pragma pack(1)
++#endif
++
++enum WIFI_FRAME_TYPE {
++ WIFI_MGT_TYPE = (0),
++ WIFI_CTRL_TYPE = (BIT(2)),
++ WIFI_DATA_TYPE = (BIT(3)),
++ WIFI_QOS_DATA_TYPE = (BIT(7)|BIT(3)), //!< QoS Data
++};
++
++enum WIFI_FRAME_SUBTYPE {
++
++ // below is for mgt frame
++ WIFI_ASSOCREQ = (0 | WIFI_MGT_TYPE),
++ WIFI_ASSOCRSP = (BIT(4) | WIFI_MGT_TYPE),
++ WIFI_REASSOCREQ = (BIT(5) | WIFI_MGT_TYPE),
++ WIFI_REASSOCRSP = (BIT(5) | BIT(4) | WIFI_MGT_TYPE),
++ WIFI_PROBEREQ = (BIT(6) | WIFI_MGT_TYPE),
++ WIFI_PROBERSP = (BIT(6) | BIT(4) | WIFI_MGT_TYPE),
++ WIFI_BEACON = (BIT(7) | WIFI_MGT_TYPE),
++ WIFI_ATIM = (BIT(7) | BIT(4) | WIFI_MGT_TYPE),
++ WIFI_DISASSOC = (BIT(7) | BIT(5) | WIFI_MGT_TYPE),
++ WIFI_AUTH = (BIT(7) | BIT(5) | BIT(4) | WIFI_MGT_TYPE),
++ WIFI_DEAUTH = (BIT(7) | BIT(6) | WIFI_MGT_TYPE),
++ WIFI_ACTION = (BIT(7) | BIT(6) | BIT(4) | WIFI_MGT_TYPE),
++
++ // below is for control frame
++ WIFI_PSPOLL = (BIT(7) | BIT(5) | WIFI_CTRL_TYPE),
++ WIFI_RTS = (BIT(7) | BIT(5) | BIT(4) | WIFI_CTRL_TYPE),
++ WIFI_CTS = (BIT(7) | BIT(6) | WIFI_CTRL_TYPE),
++ WIFI_ACK = (BIT(7) | BIT(6) | BIT(4) | WIFI_CTRL_TYPE),
++ WIFI_CFEND = (BIT(7) | BIT(6) | BIT(5) | WIFI_CTRL_TYPE),
++ WIFI_CFEND_CFACK = (BIT(7) | BIT(6) | BIT(5) | BIT(4) | WIFI_CTRL_TYPE),
++
++ // below is for data frame
++ WIFI_DATA = (0 | WIFI_DATA_TYPE),
++ WIFI_DATA_CFACK = (BIT(4) | WIFI_DATA_TYPE),
++ WIFI_DATA_CFPOLL = (BIT(5) | WIFI_DATA_TYPE),
++ WIFI_DATA_CFACKPOLL = (BIT(5) | BIT(4) | WIFI_DATA_TYPE),
++ WIFI_DATA_NULL = (BIT(6) | WIFI_DATA_TYPE),
++ WIFI_CF_ACK = (BIT(6) | BIT(4) | WIFI_DATA_TYPE),
++ WIFI_CF_POLL = (BIT(6) | BIT(5) | WIFI_DATA_TYPE),
++ WIFI_CF_ACKPOLL = (BIT(6) | BIT(5) | BIT(4) | WIFI_DATA_TYPE),
++ WIFI_QOS_DATA_NULL = (BIT(6) | WIFI_QOS_DATA_TYPE),
++};
++
++enum WIFI_REASON_CODE {
++ _RSON_RESERVED_ = 0,
++ _RSON_UNSPECIFIED_ = 1,
++ _RSON_AUTH_NO_LONGER_VALID_ = 2,
++ _RSON_DEAUTH_STA_LEAVING_ = 3,
++ _RSON_INACTIVITY_ = 4,
++ _RSON_UNABLE_HANDLE_ = 5,
++ _RSON_CLS2_ = 6,
++ _RSON_CLS3_ = 7,
++ _RSON_DISAOC_STA_LEAVING_ = 8,
++ _RSON_ASOC_NOT_AUTH_ = 9,
++
++ // WPA reason
++ _RSON_INVALID_IE_ = 13,
++ _RSON_MIC_FAILURE_ = 14,
++ _RSON_4WAY_HNDSHK_TIMEOUT_ = 15,
++ _RSON_GROUP_KEY_UPDATE_TIMEOUT_ = 16,
++ _RSON_DIFF_IE_ = 17,
++ _RSON_MLTCST_CIPHER_NOT_VALID_ = 18,
++ _RSON_UNICST_CIPHER_NOT_VALID_ = 19,
++ _RSON_AKMP_NOT_VALID_ = 20,
++ _RSON_UNSUPPORT_RSNE_VER_ = 21,
++ _RSON_INVALID_RSNE_CAP_ = 22,
++ _RSON_IEEE_802DOT1X_AUTH_FAIL_ = 23,
++
++ //belowing are Realtek definition
++ _RSON_PMK_NOT_AVAILABLE_ = 24,
++ _RSON_TDLS_TEAR_TOOFAR_ = 25,
++ _RSON_TDLS_TEAR_UN_RSN_ = 26,
++};
++
++/* Reason codes (IEEE 802.11-2007, 7.3.1.7, Table 7-22) */
++#if 0
++#define WLAN_REASON_UNSPECIFIED 1
++#define WLAN_REASON_PREV_AUTH_NOT_VALID 2
++#define WLAN_REASON_DEAUTH_LEAVING 3
++#define WLAN_REASON_DISASSOC_DUE_TO_INACTIVITY 4
++#define WLAN_REASON_DISASSOC_AP_BUSY 5
++#define WLAN_REASON_CLASS2_FRAME_FROM_NONAUTH_STA 6
++#define WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA 7
++#define WLAN_REASON_DISASSOC_STA_HAS_LEFT 8
++#define WLAN_REASON_STA_REQ_ASSOC_WITHOUT_AUTH 9
++#endif
++/* IEEE 802.11h */
++#define WLAN_REASON_PWR_CAPABILITY_NOT_VALID 10
++#define WLAN_REASON_SUPPORTED_CHANNEL_NOT_VALID 11
++#if 0
++/* IEEE 802.11i */
++#define WLAN_REASON_INVALID_IE 13
++#define WLAN_REASON_MICHAEL_MIC_FAILURE 14
++#define WLAN_REASON_4WAY_HANDSHAKE_TIMEOUT 15
++#define WLAN_REASON_GROUP_KEY_UPDATE_TIMEOUT 16
++#define WLAN_REASON_IE_IN_4WAY_DIFFERS 17
++#define WLAN_REASON_GROUP_CIPHER_NOT_VALID 18
++#define WLAN_REASON_PAIRWISE_CIPHER_NOT_VALID 19
++#define WLAN_REASON_AKMP_NOT_VALID 20
++#define WLAN_REASON_UNSUPPORTED_RSN_IE_VERSION 21
++#define WLAN_REASON_INVALID_RSN_IE_CAPAB 22
++#define WLAN_REASON_IEEE_802_1X_AUTH_FAILED 23
++#define WLAN_REASON_CIPHER_SUITE_REJECTED 24
++#endif
++
++enum WIFI_STATUS_CODE {
++ _STATS_SUCCESSFUL_ = 0,
++ _STATS_FAILURE_ = 1,
++ _STATS_CAP_FAIL_ = 10,
++ _STATS_NO_ASOC_ = 11,
++ _STATS_OTHER_ = 12,
++ _STATS_NO_SUPP_ALG_ = 13,
++ _STATS_OUT_OF_AUTH_SEQ_ = 14,
++ _STATS_CHALLENGE_FAIL_ = 15,
++ _STATS_AUTH_TIMEOUT_ = 16,
++ _STATS_UNABLE_HANDLE_STA_ = 17,
++ _STATS_RATE_FAIL_ = 18,
++};
++
++/* Status codes (IEEE 802.11-2007, 7.3.1.9, Table 7-23) */
++#if 0
++#define WLAN_STATUS_SUCCESS 0
++#define WLAN_STATUS_UNSPECIFIED_FAILURE 1
++#define WLAN_STATUS_CAPS_UNSUPPORTED 10
++#define WLAN_STATUS_REASSOC_NO_ASSOC 11
++#define WLAN_STATUS_ASSOC_DENIED_UNSPEC 12
++#define WLAN_STATUS_NOT_SUPPORTED_AUTH_ALG 13
++#define WLAN_STATUS_UNKNOWN_AUTH_TRANSACTION 14
++#define WLAN_STATUS_CHALLENGE_FAIL 15
++#define WLAN_STATUS_AUTH_TIMEOUT 16
++#define WLAN_STATUS_AP_UNABLE_TO_HANDLE_NEW_STA 17
++#define WLAN_STATUS_ASSOC_DENIED_RATES 18
++#endif
++//entended
++/* IEEE 802.11b */
++#define WLAN_STATUS_ASSOC_DENIED_NOSHORT 19
++#define WLAN_STATUS_ASSOC_DENIED_NOPBCC 20
++#define WLAN_STATUS_ASSOC_DENIED_NOAGILITY 21
++/* IEEE 802.11h */
++#define WLAN_STATUS_SPEC_MGMT_REQUIRED 22
++#define WLAN_STATUS_PWR_CAPABILITY_NOT_VALID 23
++#define WLAN_STATUS_SUPPORTED_CHANNEL_NOT_VALID 24
++/* IEEE 802.11g */
++#define WLAN_STATUS_ASSOC_DENIED_NO_SHORT_SLOT_TIME 25
++#define WLAN_STATUS_ASSOC_DENIED_NO_ER_PBCC 26
++#define WLAN_STATUS_ASSOC_DENIED_NO_DSSS_OFDM 27
++/* IEEE 802.11w */
++#define WLAN_STATUS_ASSOC_REJECTED_TEMPORARILY 30
++#define WLAN_STATUS_ROBUST_MGMT_FRAME_POLICY_VIOLATION 31
++/* IEEE 802.11i */
++#define WLAN_STATUS_INVALID_IE 40
++#define WLAN_STATUS_GROUP_CIPHER_NOT_VALID 41
++#define WLAN_STATUS_PAIRWISE_CIPHER_NOT_VALID 42
++#define WLAN_STATUS_AKMP_NOT_VALID 43
++#define WLAN_STATUS_UNSUPPORTED_RSN_IE_VERSION 44
++#define WLAN_STATUS_INVALID_RSN_IE_CAPAB 45
++#define WLAN_STATUS_CIPHER_REJECTED_PER_POLICY 46
++#define WLAN_STATUS_TS_NOT_CREATED 47
++#define WLAN_STATUS_DIRECT_LINK_NOT_ALLOWED 48
++#define WLAN_STATUS_DEST_STA_NOT_PRESENT 49
++#define WLAN_STATUS_DEST_STA_NOT_QOS_STA 50
++#define WLAN_STATUS_ASSOC_DENIED_LISTEN_INT_TOO_LARGE 51
++/* IEEE 802.11r */
++#define WLAN_STATUS_INVALID_FT_ACTION_FRAME_COUNT 52
++#define WLAN_STATUS_INVALID_PMKID 53
++#define WLAN_STATUS_INVALID_MDIE 54
++#define WLAN_STATUS_INVALID_FTIE 55
++
++
++enum WIFI_REG_DOMAIN {
++ DOMAIN_FCC = 1,
++ DOMAIN_IC = 2,
++ DOMAIN_ETSI = 3,
++ DOMAIN_SPAIN = 4,
++ DOMAIN_FRANCE = 5,
++ DOMAIN_MKK = 6,
++ DOMAIN_ISRAEL = 7,
++ DOMAIN_MKK1 = 8,
++ DOMAIN_MKK2 = 9,
++ DOMAIN_MKK3 = 10,
++ DOMAIN_MAX
++};
++
++#define _TO_DS_ BIT(8)
++#define _FROM_DS_ BIT(9)
++#define _MORE_FRAG_ BIT(10)
++#define _RETRY_ BIT(11)
++#define _PWRMGT_ BIT(12)
++#define _MORE_DATA_ BIT(13)
++#define _PRIVACY_ BIT(14)
++#define _ORDER_ BIT(15)
++
++#define SetToDs(pbuf) \
++ do { \
++ *(unsigned short *)(pbuf) |= cpu_to_le16(_TO_DS_); \
++ } while(0)
++
++#define GetToDs(pbuf) (((*(unsigned short *)(pbuf)) & le16_to_cpu(_TO_DS_)) != 0)
++
++#define ClearToDs(pbuf) \
++ do { \
++ *(unsigned short *)(pbuf) &= (~cpu_to_le16(_TO_DS_)); \
++ } while(0)
++
++#define SetFrDs(pbuf) \
++ do { \
++ *(unsigned short *)(pbuf) |= cpu_to_le16(_FROM_DS_); \
++ } while(0)
++
++#define GetFrDs(pbuf) (((*(unsigned short *)(pbuf)) & le16_to_cpu(_FROM_DS_)) != 0)
++
++#define ClearFrDs(pbuf) \
++ do { \
++ *(unsigned short *)(pbuf) &= (~cpu_to_le16(_FROM_DS_)); \
++ } while(0)
++
++#define get_tofr_ds(pframe) ((GetToDs(pframe) << 1) | GetFrDs(pframe))
++
++
++#define SetMFrag(pbuf) \
++ do { \
++ *(unsigned short *)(pbuf) |= cpu_to_le16(_MORE_FRAG_); \
++ } while(0)
++
++#define GetMFrag(pbuf) (((*(unsigned short *)(pbuf)) & le16_to_cpu(_MORE_FRAG_)) != 0)
++
++#define ClearMFrag(pbuf) \
++ do { \
++ *(unsigned short *)(pbuf) &= (~cpu_to_le16(_MORE_FRAG_)); \
++ } while(0)
++
++#define SetRetry(pbuf) \
++ do { \
++ *(unsigned short *)(pbuf) |= cpu_to_le16(_RETRY_); \
++ } while(0)
++
++#define GetRetry(pbuf) (((*(unsigned short *)(pbuf)) & le16_to_cpu(_RETRY_)) != 0)
++
++#define ClearRetry(pbuf) \
++ do { \
++ *(unsigned short *)(pbuf) &= (~cpu_to_le16(_RETRY_)); \
++ } while(0)
++
++#define SetPwrMgt(pbuf) \
++ do { \
++ *(unsigned short *)(pbuf) |= cpu_to_le16(_PWRMGT_); \
++ } while(0)
++
++#define GetPwrMgt(pbuf) (((*(unsigned short *)(pbuf)) & le16_to_cpu(_PWRMGT_)) != 0)
++
++#define ClearPwrMgt(pbuf) \
++ do { \
++ *(unsigned short *)(pbuf) &= (~cpu_to_le16(_PWRMGT_)); \
++ } while(0)
++
++#define SetMData(pbuf) \
++ do { \
++ *(unsigned short *)(pbuf) |= cpu_to_le16(_MORE_DATA_); \
++ } while(0)
++
++#define GetMData(pbuf) (((*(unsigned short *)(pbuf)) & le16_to_cpu(_MORE_DATA_)) != 0)
++
++#define ClearMData(pbuf) \
++ do { \
++ *(unsigned short *)(pbuf) &= (~cpu_to_le16(_MORE_DATA_)); \
++ } while(0)
++
++#define SetPrivacy(pbuf) \
++ do { \
++ *(unsigned short *)(pbuf) |= cpu_to_le16(_PRIVACY_); \
++ } while(0)
++
++#define GetPrivacy(pbuf) (((*(unsigned short *)(pbuf)) & le16_to_cpu(_PRIVACY_)) != 0)
++
++#define ClearPrivacy(pbuf) \
++ do { \
++ *(unsigned short *)(pbuf) &= (~cpu_to_le16(_PRIVACY_)); \
++ } while(0)
++
++
++#define GetOrder(pbuf) (((*(unsigned short *)(pbuf)) & le16_to_cpu(_ORDER_)) != 0)
++
++#define GetFrameType(pbuf) (le16_to_cpu(*(unsigned short *)(pbuf)) & (BIT(3) | BIT(2)))
++
++#define SetFrameType(pbuf,type) \
++ do { \
++ *(unsigned short *)(pbuf) &= __constant_cpu_to_le16(~(BIT(3) | BIT(2))); \
++ *(unsigned short *)(pbuf) |= __constant_cpu_to_le16(type); \
++ } while(0)
++
++#define GetFrameSubType(pbuf) (cpu_to_le16(*(unsigned short *)(pbuf)) & (BIT(7) | BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2)))
++
++#define SetFrameSubType(pbuf,type) \
++ do { \
++ *(unsigned short *)(pbuf) &= cpu_to_le16(~(BIT(7) | BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2))); \
++ *(unsigned short *)(pbuf) |= cpu_to_le16(type); \
++ } while(0)
++
++#define GetSequence(pbuf) (cpu_to_le16(*(unsigned short *)((SIZE_PTR)(pbuf) + 22)) >> 4)
++
++#define GetFragNum(pbuf) (cpu_to_le16(*(unsigned short *)((SIZE_PTR)(pbuf) + 22)) & 0x0f)
++
++#define GetTupleCache(pbuf) (cpu_to_le16(*(unsigned short *)((SIZE_PTR)(pbuf) + 22)))
++
++#define SetFragNum(pbuf, num) \
++ do { \
++ *(unsigned short *)((SIZE_PTR)(pbuf) + 22) = \
++ ((*(unsigned short *)((SIZE_PTR)(pbuf) + 22)) & le16_to_cpu(~(0x000f))) | \
++ cpu_to_le16(0x0f & (num)); \
++ } while(0)
++
++#define SetSeqNum(pbuf, num) \
++ do { \
++ *(unsigned short *)((SIZE_PTR)(pbuf) + 22) = \
++ ((*(unsigned short *)((SIZE_PTR)(pbuf) + 22)) & le16_to_cpu((unsigned short)~0xfff0)) | \
++ le16_to_cpu((unsigned short)(0xfff0 & (num << 4))); \
++ } while(0)
++
++#define SetDuration(pbuf, dur) \
++ do { \
++ *(unsigned short *)((SIZE_PTR)(pbuf) + 2) = cpu_to_le16(0xffff & (dur)); \
++ } while(0)
++
++
++#define SetPriority(pbuf, tid) \
++ do { \
++ *(unsigned short *)(pbuf) |= cpu_to_le16(tid & 0xf); \
++ } while(0)
++
++#define GetPriority(pbuf) ((le16_to_cpu(*(unsigned short *)(pbuf))) & 0xf)
++
++#define SetEOSP(pbuf, eosp) \
++ do { \
++ *(unsigned short *)(pbuf) |= cpu_to_le16( (eosp & 1) << 4); \
++ } while(0)
++
++#define SetAckpolicy(pbuf, ack) \
++ do { \
++ *(unsigned short *)(pbuf) |= cpu_to_le16( (ack & 3) << 5); \
++ } while(0)
++
++#define GetAckpolicy(pbuf) (((le16_to_cpu(*(unsigned short *)pbuf)) >> 5) & 0x3)
++
++#define GetAMsdu(pbuf) (((le16_to_cpu(*(unsigned short *)pbuf)) >> 7) & 0x1)
++
++#define SetAMsdu(pbuf, amsdu) \
++ do { \
++ *(unsigned short *)(pbuf) |= cpu_to_le16( (amsdu & 1) << 7); \
++ } while(0)
++
++#define GetAid(pbuf) (cpu_to_le16(*(unsigned short *)((SIZE_PTR)(pbuf) + 2)) & 0x3fff)
++
++#define GetTid(pbuf) (cpu_to_le16(*(unsigned short *)((SIZE_PTR)(pbuf) + (((GetToDs(pbuf)<<1)|GetFrDs(pbuf))==3?30:24))) & 0x000f)
++
++#define GetAddr1Ptr(pbuf) ((unsigned char *)((SIZE_PTR)(pbuf) + 4))
++
++#define GetAddr2Ptr(pbuf) ((unsigned char *)((SIZE_PTR)(pbuf) + 10))
++
++#define GetAddr3Ptr(pbuf) ((unsigned char *)((SIZE_PTR)(pbuf) + 16))
++
++#define GetAddr4Ptr(pbuf) ((unsigned char *)((SIZE_PTR)(pbuf) + 24))
++
++#define MacAddr_isBcst(addr) \
++( \
++ ( (addr[0] == 0xff) && (addr[1] == 0xff) && \
++ (addr[2] == 0xff) && (addr[3] == 0xff) && \
++ (addr[4] == 0xff) && (addr[5] == 0xff) ) ? _TRUE : _FALSE \
++)
++
++__inline static int IS_MCAST(unsigned char *da)
++{
++ if ((*da) & 0x01)
++ return _TRUE;
++ else
++ return _FALSE;
++}
++
++
++__inline static unsigned char * get_da(unsigned char *pframe)
++{
++ unsigned char *da;
++ unsigned int to_fr_ds = (GetToDs(pframe) << 1) | GetFrDs(pframe);
++
++ switch (to_fr_ds) {
++ case 0x00: // ToDs=0, FromDs=0
++ da = GetAddr1Ptr(pframe);
++ break;
++ case 0x01: // ToDs=0, FromDs=1
++ da = GetAddr1Ptr(pframe);
++ break;
++ case 0x02: // ToDs=1, FromDs=0
++ da = GetAddr3Ptr(pframe);
++ break;
++ default: // ToDs=1, FromDs=1
++ da = GetAddr3Ptr(pframe);
++ break;
++ }
++
++ return da;
++}
++
++
++__inline static unsigned char * get_sa(unsigned char *pframe)
++{
++ unsigned char *sa;
++ unsigned int to_fr_ds = (GetToDs(pframe) << 1) | GetFrDs(pframe);
++
++ switch (to_fr_ds) {
++ case 0x00: // ToDs=0, FromDs=0
++ sa = GetAddr2Ptr(pframe);
++ break;
++ case 0x01: // ToDs=0, FromDs=1
++ sa = GetAddr3Ptr(pframe);
++ break;
++ case 0x02: // ToDs=1, FromDs=0
++ sa = GetAddr2Ptr(pframe);
++ break;
++ default: // ToDs=1, FromDs=1
++ sa = GetAddr4Ptr(pframe);
++ break;
++ }
++
++ return sa;
++}
++
++__inline static unsigned char * get_hdr_bssid(unsigned char *pframe)
++{
++ unsigned char *sa;
++ unsigned int to_fr_ds = (GetToDs(pframe) << 1) | GetFrDs(pframe);
++
++ switch (to_fr_ds) {
++ case 0x00: // ToDs=0, FromDs=0
++ sa = GetAddr3Ptr(pframe);
++ break;
++ case 0x01: // ToDs=0, FromDs=1
++ sa = GetAddr2Ptr(pframe);
++ break;
++ case 0x02: // ToDs=1, FromDs=0
++ sa = GetAddr1Ptr(pframe);
++ break;
++ case 0x03: // ToDs=1, FromDs=1
++ sa = GetAddr1Ptr(pframe);
++ break;
++ default:
++ sa =NULL; //???????
++ break;
++ }
++
++ return sa;
++}
++
++
++__inline static int IsFrameTypeCtrl(unsigned char *pframe)
++{
++ if(WIFI_CTRL_TYPE == GetFrameType(pframe))
++ return _TRUE;
++ else
++ return _FALSE;
++}
++/*-----------------------------------------------------------------------------
++ Below is for the security related definition
++------------------------------------------------------------------------------*/
++#define _RESERVED_FRAME_TYPE_ 0
++#define _SKB_FRAME_TYPE_ 2
++#define _PRE_ALLOCMEM_ 1
++#define _PRE_ALLOCHDR_ 3
++#define _PRE_ALLOCLLCHDR_ 4
++#define _PRE_ALLOCICVHDR_ 5
++#define _PRE_ALLOCMICHDR_ 6
++
++#define _SIFSTIME_ ((priv->pmib->dot11BssType.net_work_type&WIRELESS_11A)?16:10)
++#define _ACKCTSLNG_ 14 //14 bytes long, including crclng
++#define _CRCLNG_ 4
++
++#define _ASOCREQ_IE_OFFSET_ 4 // excluding wlan_hdr
++#define _ASOCRSP_IE_OFFSET_ 6
++#define _REASOCREQ_IE_OFFSET_ 10
++#define _REASOCRSP_IE_OFFSET_ 6
++#define _PROBEREQ_IE_OFFSET_ 0
++#define _PROBERSP_IE_OFFSET_ 12
++#define _AUTH_IE_OFFSET_ 6
++#define _DEAUTH_IE_OFFSET_ 0
++#define _BEACON_IE_OFFSET_ 12
++#define _PUBLIC_ACTION_IE_OFFSET_ 8
++
++#define _FIXED_IE_LENGTH_ _BEACON_IE_OFFSET_
++
++#define _SSID_IE_ 0
++#define _SUPPORTEDRATES_IE_ 1
++#define _DSSET_IE_ 3
++#define _TIM_IE_ 5
++#define _IBSS_PARA_IE_ 6
++#define _COUNTRY_IE_ 7
++#define _CHLGETXT_IE_ 16
++#define _POW_CAP_IE_ 33
++#define _SUPPORTED_CH_IE_ 36
++#define _CH_SWTICH_ANNOUNCE_ 37 //Secondary Channel Offset
++#define _RSN_IE_2_ 48
++#define _SSN_IE_1_ 221
++#define _ERPINFO_IE_ 42
++#define _EXT_SUPPORTEDRATES_IE_ 50
++
++#define _HT_CAPABILITY_IE_ 45
++#define _FTIE_ 55
++#define _TIMEOUT_ITVL_IE_ 56
++#define _SRC_IE_ 59
++#define _HT_EXTRA_INFO_IE_ 61
++#define _HT_ADD_INFO_IE_ 61 //_HT_EXTRA_INFO_IE_
++
++#define EID_BSSCoexistence 72 // 20/40 BSS Coexistence
++#define EID_BSSIntolerantChlReport 73
++#define _RIC_Descriptor_IE_ 75
++
++#ifdef CONFIG_IEEE80211W
++#define _MME_IE_ 76 //802.11w Management MIC element
++#endif //CONFIG_IEEE80211W
++#define _LINK_ID_IE_ 101
++#define _CH_SWITCH_TIMING_ 104
++#define _PTI_BUFFER_STATUS_ 106
++#define _EXT_CAP_IE_ 127
++#define _VENDOR_SPECIFIC_IE_ 221
++
++#define _RESERVED47_ 47
++
++/* ---------------------------------------------------------------------------
++ Below is the fixed elements...
++-----------------------------------------------------------------------------*/
++#define _AUTH_ALGM_NUM_ 2
++#define _AUTH_SEQ_NUM_ 2
++#define _BEACON_ITERVAL_ 2
++#define _CAPABILITY_ 2
++#define _CURRENT_APADDR_ 6
++#define _LISTEN_INTERVAL_ 2
++#define _RSON_CODE_ 2
++#define _ASOC_ID_ 2
++#define _STATUS_CODE_ 2
++#define _TIMESTAMP_ 8
++
++#define AUTH_ODD_TO 0
++#define AUTH_EVEN_TO 1
++
++#define WLAN_ETHCONV_ENCAP 1
++#define WLAN_ETHCONV_RFC1042 2
++#define WLAN_ETHCONV_8021h 3
++
++#define cap_ESS BIT(0)
++#define cap_IBSS BIT(1)
++#define cap_CFPollable BIT(2)
++#define cap_CFRequest BIT(3)
++#define cap_Privacy BIT(4)
++#define cap_ShortPremble BIT(5)
++#define cap_PBCC BIT(6)
++#define cap_ChAgility BIT(7)
++#define cap_SpecMgmt BIT(8)
++#define cap_QoS BIT(9)
++#define cap_ShortSlot BIT(10)
++
++/*-----------------------------------------------------------------------------
++ Below is the definition for 802.11i / 802.1x
++------------------------------------------------------------------------------*/
++#define _IEEE8021X_MGT_ 1 // WPA
++#define _IEEE8021X_PSK_ 2 // WPA with pre-shared key
++
++/*
++#define _NO_PRIVACY_ 0
++#define _WEP_40_PRIVACY_ 1
++#define _TKIP_PRIVACY_ 2
++#define _WRAP_PRIVACY_ 3
++#define _CCMP_PRIVACY_ 4
++#define _WEP_104_PRIVACY_ 5
++#define _WEP_WPA_MIXED_PRIVACY_ 6 // WEP + WPA
++*/
++
++#ifdef CONFIG_IEEE80211W
++#define _MME_IE_LENGTH_ 18
++#endif //CONFIG_IEEE80211W
++/*-----------------------------------------------------------------------------
++ Below is the definition for WMM
++------------------------------------------------------------------------------*/
++#define _WMM_IE_Length_ 7 // for WMM STA
++#define _WMM_Para_Element_Length_ 24
++
++
++/*-----------------------------------------------------------------------------
++ Below is the definition for 802.11n
++------------------------------------------------------------------------------*/
++
++/* block-ack parameters */
++#define IEEE80211_ADDBA_PARAM_POLICY_MASK 0x0002
++#define IEEE80211_ADDBA_PARAM_TID_MASK 0x003C
++#define RTW_IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK 0xFFA0
++#define IEEE80211_DELBA_PARAM_TID_MASK 0xF000
++#define IEEE80211_DELBA_PARAM_INITIATOR_MASK 0x0800
++
++//#ifdef CONFIG_80211N_HT
++
++#define SetOrderBit(pbuf) \
++ do { \
++ *(unsigned short *)(pbuf) |= cpu_to_le16(_ORDER_); \
++ } while(0)
++
++#define GetOrderBit(pbuf) (((*(unsigned short *)(pbuf)) & le16_to_cpu(_ORDER_)) != 0)
++
++
++/**
++ * struct rtw_ieee80211_bar - HT Block Ack Request
++ *
++ * This structure refers to "HT BlockAckReq" as
++ * described in 802.11n draft section 7.2.1.7.1
++ */
++ #if defined(PLATFORM_LINUX) || defined(CONFIG_RTL8712FW)
++struct rtw_ieee80211_bar {
++ unsigned short frame_control;
++ unsigned short duration;
++ unsigned char ra[6];
++ unsigned char ta[6];
++ unsigned short control;
++ unsigned short start_seq_num;
++} __attribute__((packed));
++ #endif
++
++/* 802.11 BAR control masks */
++#define IEEE80211_BAR_CTRL_ACK_POLICY_NORMAL 0x0000
++#define IEEE80211_BAR_CTRL_CBMTID_COMPRESSED_BA 0x0004
++
++
++ #if defined(PLATFORM_LINUX) || defined(CONFIG_RTL8712FW) || defined(PLATFORM_FREEBSD)
++
++
++
++ /**
++ * struct rtw_ieee80211_ht_cap - HT capabilities
++ *
++ * This structure refers to "HT capabilities element" as
++ * described in 802.11n draft section 7.3.2.52
++ */
++
++struct rtw_ieee80211_ht_cap {
++ unsigned short cap_info;
++ unsigned char ampdu_params_info;
++ unsigned char supp_mcs_set[16];
++ unsigned short extended_ht_cap_info;
++ unsigned int tx_BF_cap_info;
++ unsigned char antenna_selection_info;
++} __attribute__ ((packed));
++
++/**
++ * struct rtw_ieee80211_ht_cap - HT additional information
++ *
++ * This structure refers to "HT information element" as
++ * described in 802.11n draft section 7.3.2.53
++ */
++struct ieee80211_ht_addt_info {
++ unsigned char control_chan;
++ unsigned char ht_param;
++ unsigned short operation_mode;
++ unsigned short stbc_param;
++ unsigned char basic_set[16];
++} __attribute__ ((packed));
++
++
++struct HT_caps_element
++{
++ union
++ {
++ struct
++ {
++ unsigned short HT_caps_info;
++ unsigned char AMPDU_para;
++ unsigned char MCS_rate[16];
++ unsigned short HT_ext_caps;
++ unsigned int Beamforming_caps;
++ unsigned char ASEL_caps;
++ } HT_cap_element;
++ unsigned char HT_cap[26];
++ }u;
++} __attribute__ ((packed));
++
++struct HT_info_element
++{
++ unsigned char primary_channel;
++ unsigned char infos[5];
++ unsigned char MCS_rate[16];
++} __attribute__ ((packed));
++
++struct AC_param
++{
++ unsigned char ACI_AIFSN;
++ unsigned char CW;
++ unsigned short TXOP_limit;
++} __attribute__ ((packed));
++
++struct WMM_para_element
++{
++ unsigned char QoS_info;
++ unsigned char reserved;
++ struct AC_param ac_param[4];
++} __attribute__ ((packed));
++
++struct ADDBA_request
++{
++ unsigned char dialog_token;
++ unsigned short BA_para_set;
++ unsigned short BA_timeout_value;
++ unsigned short BA_starting_seqctrl;
++} __attribute__ ((packed));
++
++
++
++#endif
++
++
++#ifdef PLATFORM_WINDOWS
++
++#pragma pack(1)
++
++struct rtw_ieee80211_ht_cap {
++ unsigned short cap_info;
++ unsigned char ampdu_params_info;
++ unsigned char supp_mcs_set[16];
++ unsigned short extended_ht_cap_info;
++ unsigned int tx_BF_cap_info;
++ unsigned char antenna_selection_info;
++};
++
++
++struct ieee80211_ht_addt_info {
++ unsigned char control_chan;
++ unsigned char ht_param;
++ unsigned short operation_mode;
++ unsigned short stbc_param;
++ unsigned char basic_set[16];
++};
++
++struct HT_caps_element
++{
++ union
++ {
++ struct
++ {
++ unsigned short HT_caps_info;
++ unsigned char AMPDU_para;
++ unsigned char MCS_rate[16];
++ unsigned short HT_ext_caps;
++ unsigned int Beamforming_caps;
++ unsigned char ASEL_caps;
++ } HT_cap_element;
++ unsigned char HT_cap[26];
++ };
++};
++
++struct HT_info_element
++{
++ unsigned char primary_channel;
++ unsigned char infos[5];
++ unsigned char MCS_rate[16];
++};
++
++struct AC_param
++{
++ unsigned char ACI_AIFSN;
++ unsigned char CW;
++ unsigned short TXOP_limit;
++};
++
++struct WMM_para_element
++{
++ unsigned char QoS_info;
++ unsigned char reserved;
++ struct AC_param ac_param[4];
++};
++
++struct ADDBA_request
++{
++ unsigned char dialog_token;
++ unsigned short BA_para_set;
++ unsigned short BA_timeout_value;
++ unsigned short BA_starting_seqctrl;
++};
++
++
++#pragma pack()
++
++#endif
++
++
++/* 802.11n HT capabilities masks */
++#define IEEE80211_HT_CAP_SUP_WIDTH 0x0002
++#define IEEE80211_HT_CAP_SM_PS 0x000C
++#define IEEE80211_HT_CAP_GRN_FLD 0x0010
++#define IEEE80211_HT_CAP_SGI_20 0x0020
++#define IEEE80211_HT_CAP_SGI_40 0x0040
++#define IEEE80211_HT_CAP_TX_STBC 0x0080
++#define IEEE80211_HT_CAP_RX_STBC 0x0300
++#define IEEE80211_HT_CAP_DELAY_BA 0x0400
++#define IEEE80211_HT_CAP_MAX_AMSDU 0x0800
++#define IEEE80211_HT_CAP_DSSSCCK40 0x1000
++/* 802.11n HT capability AMPDU settings */
++#define IEEE80211_HT_CAP_AMPDU_FACTOR 0x03
++#define IEEE80211_HT_CAP_AMPDU_DENSITY 0x1C
++/* 802.11n HT capability MSC set */
++#define IEEE80211_SUPP_MCS_SET_UEQM 4
++#define IEEE80211_HT_CAP_MAX_STREAMS 4
++#define IEEE80211_SUPP_MCS_SET_LEN 10
++/* maximum streams the spec allows */
++#define IEEE80211_HT_CAP_MCS_TX_DEFINED 0x01
++#define IEEE80211_HT_CAP_MCS_TX_RX_DIFF 0x02
++#define IEEE80211_HT_CAP_MCS_TX_STREAMS 0x0C
++#define IEEE80211_HT_CAP_MCS_TX_UEQM 0x10
++/* 802.11n HT IE masks */
++#define IEEE80211_HT_IE_CHA_SEC_OFFSET 0x03
++#define IEEE80211_HT_IE_CHA_SEC_NONE 0x00
++#define IEEE80211_HT_IE_CHA_SEC_ABOVE 0x01
++#define IEEE80211_HT_IE_CHA_SEC_BELOW 0x03
++#define IEEE80211_HT_IE_CHA_WIDTH 0x04
++#define IEEE80211_HT_IE_HT_PROTECTION 0x0003
++#define IEEE80211_HT_IE_NON_GF_STA_PRSNT 0x0004
++#define IEEE80211_HT_IE_NON_HT_STA_PRSNT 0x0010
++
++/* block-ack parameters */
++#define IEEE80211_ADDBA_PARAM_POLICY_MASK 0x0002
++#define IEEE80211_ADDBA_PARAM_TID_MASK 0x003C
++#define RTW_IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK 0xFFA0
++#define IEEE80211_DELBA_PARAM_TID_MASK 0xF000
++#define IEEE80211_DELBA_PARAM_INITIATOR_MASK 0x0800
++
++/*
++ * A-PMDU buffer sizes
++ * According to IEEE802.11n spec size varies from 8K to 64K (in powers of 2)
++ */
++#define IEEE80211_MIN_AMPDU_BUF 0x8
++#define IEEE80211_MAX_AMPDU_BUF 0x40
++
++
++/* Spatial Multiplexing Power Save Modes */
++#define WLAN_HT_CAP_SM_PS_STATIC 0
++#define WLAN_HT_CAP_SM_PS_DYNAMIC 1
++#define WLAN_HT_CAP_SM_PS_INVALID 2
++#define WLAN_HT_CAP_SM_PS_DISABLED 3
++
++
++#define OP_MODE_PURE 0
++#define OP_MODE_MAY_BE_LEGACY_STAS 1
++#define OP_MODE_20MHZ_HT_STA_ASSOCED 2
++#define OP_MODE_MIXED 3
++
++#define HT_INFO_HT_PARAM_SECONDARY_CHNL_OFF_MASK ((u8) BIT(0) | BIT(1))
++#define HT_INFO_HT_PARAM_SECONDARY_CHNL_ABOVE ((u8) BIT(0))
++#define HT_INFO_HT_PARAM_SECONDARY_CHNL_BELOW ((u8) BIT(0) | BIT(1))
++#define HT_INFO_HT_PARAM_REC_TRANS_CHNL_WIDTH ((u8) BIT(2))
++#define HT_INFO_HT_PARAM_RIFS_MODE ((u8) BIT(3))
++#define HT_INFO_HT_PARAM_CTRL_ACCESS_ONLY ((u8) BIT(4))
++#define HT_INFO_HT_PARAM_SRV_INTERVAL_GRANULARITY ((u8) BIT(5))
++
++#define HT_INFO_OPERATION_MODE_OP_MODE_MASK \
++ ((u16) (0x0001 | 0x0002))
++#define HT_INFO_OPERATION_MODE_OP_MODE_OFFSET 0
++#define HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT ((u8) BIT(2))
++#define HT_INFO_OPERATION_MODE_TRANSMIT_BURST_LIMIT ((u8) BIT(3))
++#define HT_INFO_OPERATION_MODE_NON_HT_STA_PRESENT ((u8) BIT(4))
++
++#define HT_INFO_STBC_PARAM_DUAL_BEACON ((u16) BIT(6))
++#define HT_INFO_STBC_PARAM_DUAL_STBC_PROTECT ((u16) BIT(7))
++#define HT_INFO_STBC_PARAM_SECONDARY_BCN ((u16) BIT(8))
++#define HT_INFO_STBC_PARAM_LSIG_TXOP_PROTECT_ALLOWED ((u16) BIT(9))
++#define HT_INFO_STBC_PARAM_PCO_ACTIVE ((u16) BIT(10))
++#define HT_INFO_STBC_PARAM_PCO_PHASE ((u16) BIT(11))
++
++
++
++//#endif
++
++// ===============WPS Section===============
++// For WPSv1.0
++#define WPSOUI 0x0050f204
++// WPS attribute ID
++#define WPS_ATTR_VER1 0x104A
++#define WPS_ATTR_SIMPLE_CONF_STATE 0x1044
++#define WPS_ATTR_RESP_TYPE 0x103B
++#define WPS_ATTR_UUID_E 0x1047
++#define WPS_ATTR_MANUFACTURER 0x1021
++#define WPS_ATTR_MODEL_NAME 0x1023
++#define WPS_ATTR_MODEL_NUMBER 0x1024
++#define WPS_ATTR_SERIAL_NUMBER 0x1042
++#define WPS_ATTR_PRIMARY_DEV_TYPE 0x1054
++#define WPS_ATTR_SEC_DEV_TYPE_LIST 0x1055
++#define WPS_ATTR_DEVICE_NAME 0x1011
++#define WPS_ATTR_CONF_METHOD 0x1008
++#define WPS_ATTR_RF_BANDS 0x103C
++#define WPS_ATTR_DEVICE_PWID 0x1012
++#define WPS_ATTR_REQUEST_TYPE 0x103A
++#define WPS_ATTR_ASSOCIATION_STATE 0x1002
++#define WPS_ATTR_CONFIG_ERROR 0x1009
++#define WPS_ATTR_VENDOR_EXT 0x1049
++#define WPS_ATTR_SELECTED_REGISTRAR 0x1041
++
++// Value of WPS attribute "WPS_ATTR_DEVICE_NAME
++#define WPS_MAX_DEVICE_NAME_LEN 32
++
++// Value of WPS Request Type Attribute
++#define WPS_REQ_TYPE_ENROLLEE_INFO_ONLY 0x00
++#define WPS_REQ_TYPE_ENROLLEE_OPEN_8021X 0x01
++#define WPS_REQ_TYPE_REGISTRAR 0x02
++#define WPS_REQ_TYPE_WLAN_MANAGER_REGISTRAR 0x03
++
++// Value of WPS Response Type Attribute
++#define WPS_RESPONSE_TYPE_INFO_ONLY 0x00
++#define WPS_RESPONSE_TYPE_8021X 0x01
++#define WPS_RESPONSE_TYPE_REGISTRAR 0x02
++#define WPS_RESPONSE_TYPE_AP 0x03
++
++// Value of WPS WiFi Simple Configuration State Attribute
++#define WPS_WSC_STATE_NOT_CONFIG 0x01
++#define WPS_WSC_STATE_CONFIG 0x02
++
++// Value of WPS Version Attribute
++#define WPS_VERSION_1 0x10
++
++// Value of WPS Configuration Method Attribute
++#define WPS_CONFIG_METHOD_FLASH 0x0001
++#define WPS_CONFIG_METHOD_ETHERNET 0x0002
++#define WPS_CONFIG_METHOD_LABEL 0x0004
++#define WPS_CONFIG_METHOD_DISPLAY 0x0008
++#define WPS_CONFIG_METHOD_E_NFC 0x0010
++#define WPS_CONFIG_METHOD_I_NFC 0x0020
++#define WPS_CONFIG_METHOD_NFC 0x0040
++#define WPS_CONFIG_METHOD_PBC 0x0080
++#define WPS_CONFIG_METHOD_KEYPAD 0x0100
++#define WPS_CONFIG_METHOD_VPBC 0x0280
++#define WPS_CONFIG_METHOD_PPBC 0x0480
++#define WPS_CONFIG_METHOD_VDISPLAY 0x2008
++#define WPS_CONFIG_METHOD_PDISPLAY 0x4008
++
++// Value of Category ID of WPS Primary Device Type Attribute
++#define WPS_PDT_CID_DISPLAYS 0x0007
++#define WPS_PDT_CID_MULIT_MEDIA 0x0008
++#define WPS_PDT_CID_RTK_WIDI WPS_PDT_CID_MULIT_MEDIA
++
++// Value of Sub Category ID of WPS Primary Device Type Attribute
++#define WPS_PDT_SCID_MEDIA_SERVER 0x0005
++#define WPS_PDT_SCID_RTK_DMP WPS_PDT_SCID_MEDIA_SERVER
++
++// Value of Device Password ID
++#define WPS_DPID_PIN 0x0000
++#define WPS_DPID_USER_SPEC 0x0001
++#define WPS_DPID_MACHINE_SPEC 0x0002
++#define WPS_DPID_REKEY 0x0003
++#define WPS_DPID_PBC 0x0004
++#define WPS_DPID_REGISTRAR_SPEC 0x0005
++
++// Value of WPS RF Bands Attribute
++#define WPS_RF_BANDS_2_4_GHZ 0x01
++#define WPS_RF_BANDS_5_GHZ 0x02
++
++// Value of WPS Association State Attribute
++#define WPS_ASSOC_STATE_NOT_ASSOCIATED 0x00
++#define WPS_ASSOC_STATE_CONNECTION_SUCCESS 0x01
++#define WPS_ASSOC_STATE_CONFIGURATION_FAILURE 0x02
++#define WPS_ASSOC_STATE_ASSOCIATION_FAILURE 0x03
++#define WPS_ASSOC_STATE_IP_FAILURE 0x04
++
++// =====================P2P Section=====================
++// For P2P
++#define P2POUI 0x506F9A09
++
++// P2P Attribute ID
++#define P2P_ATTR_STATUS 0x00
++#define P2P_ATTR_MINOR_REASON_CODE 0x01
++#define P2P_ATTR_CAPABILITY 0x02
++#define P2P_ATTR_DEVICE_ID 0x03
++#define P2P_ATTR_GO_INTENT 0x04
++#define P2P_ATTR_CONF_TIMEOUT 0x05
++#define P2P_ATTR_LISTEN_CH 0x06
++#define P2P_ATTR_GROUP_BSSID 0x07
++#define P2P_ATTR_EX_LISTEN_TIMING 0x08
++#define P2P_ATTR_INTENTED_IF_ADDR 0x09
++#define P2P_ATTR_MANAGEABILITY 0x0A
++#define P2P_ATTR_CH_LIST 0x0B
++#define P2P_ATTR_NOA 0x0C
++#define P2P_ATTR_DEVICE_INFO 0x0D
++#define P2P_ATTR_GROUP_INFO 0x0E
++#define P2P_ATTR_GROUP_ID 0x0F
++#define P2P_ATTR_INTERFACE 0x10
++#define P2P_ATTR_OPERATING_CH 0x11
++#define P2P_ATTR_INVITATION_FLAGS 0x12
++
++// Value of Status Attribute
++#define P2P_STATUS_SUCCESS 0x00
++#define P2P_STATUS_FAIL_INFO_UNAVAILABLE 0x01
++#define P2P_STATUS_FAIL_INCOMPATIBLE_PARAM 0x02
++#define P2P_STATUS_FAIL_LIMIT_REACHED 0x03
++#define P2P_STATUS_FAIL_INVALID_PARAM 0x04
++#define P2P_STATUS_FAIL_REQUEST_UNABLE 0x05
++#define P2P_STATUS_FAIL_PREVOUS_PROTO_ERR 0x06
++#define P2P_STATUS_FAIL_NO_COMMON_CH 0x07
++#define P2P_STATUS_FAIL_UNKNOWN_P2PGROUP 0x08
++#define P2P_STATUS_FAIL_BOTH_GOINTENT_15 0x09
++#define P2P_STATUS_FAIL_INCOMPATIBLE_PROVSION 0x0A
++#define P2P_STATUS_FAIL_USER_REJECT 0x0B
++
++// Value of Inviation Flags Attribute
++#define P2P_INVITATION_FLAGS_PERSISTENT BIT(0)
++
++#define DMP_P2P_DEVCAP_SUPPORT (P2P_DEVCAP_SERVICE_DISCOVERY | \
++ P2P_DEVCAP_CLIENT_DISCOVERABILITY | \
++ P2P_DEVCAP_CONCURRENT_OPERATION | \
++ P2P_DEVCAP_INVITATION_PROC)
++
++#define DMP_P2P_GRPCAP_SUPPORT (P2P_GRPCAP_INTRABSS)
++
++// Value of Device Capability Bitmap
++#define P2P_DEVCAP_SERVICE_DISCOVERY BIT(0)
++#define P2P_DEVCAP_CLIENT_DISCOVERABILITY BIT(1)
++#define P2P_DEVCAP_CONCURRENT_OPERATION BIT(2)
++#define P2P_DEVCAP_INFRA_MANAGED BIT(3)
++#define P2P_DEVCAP_DEVICE_LIMIT BIT(4)
++#define P2P_DEVCAP_INVITATION_PROC BIT(5)
++
++// Value of Group Capability Bitmap
++#define P2P_GRPCAP_GO BIT(0)
++#define P2P_GRPCAP_PERSISTENT_GROUP BIT(1)
++#define P2P_GRPCAP_GROUP_LIMIT BIT(2)
++#define P2P_GRPCAP_INTRABSS BIT(3)
++#define P2P_GRPCAP_CROSS_CONN BIT(4)
++#define P2P_GRPCAP_PERSISTENT_RECONN BIT(5)
++#define P2P_GRPCAP_GROUP_FORMATION BIT(6)
++
++// P2P Public Action Frame ( Management Frame )
++#define P2P_PUB_ACTION_ACTION 0x09
++
++// P2P Public Action Frame Type
++#define P2P_GO_NEGO_REQ 0
++#define P2P_GO_NEGO_RESP 1
++#define P2P_GO_NEGO_CONF 2
++#define P2P_INVIT_REQ 3
++#define P2P_INVIT_RESP 4
++#define P2P_DEVDISC_REQ 5
++#define P2P_DEVDISC_RESP 6
++#define P2P_PROVISION_DISC_REQ 7
++#define P2P_PROVISION_DISC_RESP 8
++
++// P2P Action Frame Type
++#define P2P_NOTICE_OF_ABSENCE 0
++#define P2P_PRESENCE_REQUEST 1
++#define P2P_PRESENCE_RESPONSE 2
++#define P2P_GO_DISC_REQUEST 3
++
++
++#define P2P_MAX_PERSISTENT_GROUP_NUM 10
++
++#define P2P_PROVISIONING_SCAN_CNT 3
++
++#define P2P_WILDCARD_SSID_LEN 7
++
++#define P2P_FINDPHASE_EX_NONE 0 // default value, used when: (1)p2p disabed or (2)p2p enabled but only do 1 scan phase
++#define P2P_FINDPHASE_EX_FULL 1 // used when p2p enabled and want to do 1 scan phase and P2P_FINDPHASE_EX_MAX-1 find phase
++#define P2P_FINDPHASE_EX_SOCIAL_FIRST (P2P_FINDPHASE_EX_FULL+1)
++#define P2P_FINDPHASE_EX_MAX 4
++#define P2P_FINDPHASE_EX_SOCIAL_LAST P2P_FINDPHASE_EX_MAX
++
++#define P2P_PROVISION_TIMEOUT 5000 // 5 seconds timeout for sending the provision discovery request
++#define P2P_CONCURRENT_PROVISION_TIMEOUT 3000 // 3 seconds timeout for sending the provision discovery request under concurrent mode
++#define P2P_GO_NEGO_TIMEOUT 5000 // 5 seconds timeout for receiving the group negotation response
++#define P2P_CONCURRENT_GO_NEGO_TIMEOUT 3000 // 3 seconds timeout for sending the negotiation request under concurrent mode
++#define P2P_TX_PRESCAN_TIMEOUT 100 // 100ms
++#define P2P_INVITE_TIMEOUT 5000 // 5 seconds timeout for sending the invitation request
++#define P2P_CONCURRENT_INVITE_TIMEOUT 3000 // 3 seconds timeout for sending the invitation request under concurrent mode
++#define P2P_RESET_SCAN_CH 15000 // 15 seconds timeout to reset the scan channel ( based on channel plan )
++#define P2P_MAX_INTENT 15
++
++#define P2P_MAX_NOA_NUM 2
++
++// WPS Configuration Method
++#define WPS_CM_NONE 0x0000
++#define WPS_CM_LABEL 0x0004
++#define WPS_CM_DISPLYA 0x0008
++#define WPS_CM_EXTERNAL_NFC_TOKEN 0x0010
++#define WPS_CM_INTEGRATED_NFC_TOKEN 0x0020
++#define WPS_CM_NFC_INTERFACE 0x0040
++#define WPS_CM_PUSH_BUTTON 0x0080
++#define WPS_CM_KEYPAD 0x0100
++#define WPS_CM_SW_PUHS_BUTTON 0x0280
++#define WPS_CM_HW_PUHS_BUTTON 0x0480
++#define WPS_CM_SW_DISPLAY_PIN 0x2008
++#define WPS_CM_LCD_DISPLAY_PIN 0x4008
++
++enum P2P_ROLE {
++ P2P_ROLE_DISABLE = 0,
++ P2P_ROLE_DEVICE = 1,
++ P2P_ROLE_CLIENT = 2,
++ P2P_ROLE_GO = 3
++};
++
++enum P2P_STATE {
++ P2P_STATE_NONE = 0, // P2P disable
++ P2P_STATE_IDLE = 1, // P2P had enabled and do nothing
++ P2P_STATE_LISTEN = 2, // In pure listen state
++ P2P_STATE_SCAN = 3, // In scan phase
++ P2P_STATE_FIND_PHASE_LISTEN = 4, // In the listen state of find phase
++ P2P_STATE_FIND_PHASE_SEARCH = 5, // In the search state of find phase
++ P2P_STATE_TX_PROVISION_DIS_REQ = 6, // In P2P provisioning discovery
++ P2P_STATE_RX_PROVISION_DIS_RSP = 7,
++ P2P_STATE_RX_PROVISION_DIS_REQ = 8,
++ P2P_STATE_GONEGO_ING = 9, // Doing the group owner negoitation handshake
++ P2P_STATE_GONEGO_OK = 10, // finish the group negoitation handshake with success
++ P2P_STATE_GONEGO_FAIL = 11, // finish the group negoitation handshake with failure
++ P2P_STATE_RECV_INVITE_REQ_MATCH = 12, // receiving the P2P Inviation request and match with the profile.
++ P2P_STATE_PROVISIONING_ING = 13, // Doing the P2P WPS
++ P2P_STATE_PROVISIONING_DONE = 14, // Finish the P2P WPS
++ P2P_STATE_TX_INVITE_REQ = 15, // Transmit the P2P Invitation request
++ P2P_STATE_RX_INVITE_RESP_OK = 16, // Receiving the P2P Invitation response with sucess
++ P2P_STATE_RECV_INVITE_REQ_DISMATCH = 17, // receiving the P2P Inviation request and dismatch with the profile.
++ P2P_STATE_RECV_INVITE_REQ_GO = 18, // receiving the P2P Inviation request and this wifi is GO.
++ P2P_STATE_RECV_INVITE_REQ_JOIN = 19, // receiving the P2P Inviation request to join an existing P2P Group.
++ P2P_STATE_RX_INVITE_RESP_FAIL = 20, // recveing the P2P Inviation response with failure
++ P2P_STATE_RX_INFOR_NOREADY = 21, // receiving p2p negoitation response with information is not available
++ P2P_STATE_TX_INFOR_NOREADY = 22, // sending p2p negoitation response with information is not available
++};
++
++enum P2P_WPSINFO {
++ P2P_NO_WPSINFO = 0,
++ P2P_GOT_WPSINFO_PEER_DISPLAY_PIN = 1,
++ P2P_GOT_WPSINFO_SELF_DISPLAY_PIN = 2,
++ P2P_GOT_WPSINFO_PBC = 3,
++};
++
++#define P2P_PRIVATE_IOCTL_SET_LEN 64
++
++enum P2P_PROTO_WK_ID
++{
++ P2P_FIND_PHASE_WK = 0,
++ P2P_RESTORE_STATE_WK = 1,
++ P2P_PRE_TX_PROVDISC_PROCESS_WK = 2,
++ P2P_PRE_TX_NEGOREQ_PROCESS_WK = 3,
++ P2P_PRE_TX_INVITEREQ_PROCESS_WK = 4,
++ P2P_AP_P2P_CH_SWITCH_PROCESS_WK =5,
++ P2P_RO_CH_WK = 6,
++};
++
++#ifdef CONFIG_P2P_PS
++enum P2P_PS_STATE
++{
++ P2P_PS_DISABLE = 0,
++ P2P_PS_ENABLE = 1,
++ P2P_PS_SCAN = 2,
++ P2P_PS_SCAN_DONE = 3,
++ P2P_PS_ALLSTASLEEP = 4, // for P2P GO
++};
++
++enum P2P_PS_MODE
++{
++ P2P_PS_NONE = 0,
++ P2P_PS_CTWINDOW = 1,
++ P2P_PS_NOA = 2,
++ P2P_PS_MIX = 3, // CTWindow and NoA
++};
++#endif // CONFIG_P2P_PS
++
++// =====================WFD Section=====================
++// For Wi-Fi Display
++#define WFD_ATTR_DEVICE_INFO 0x00
++#define WFD_ATTR_ASSOC_BSSID 0x01
++#define WFD_ATTR_COUPLED_SINK_INFO 0x06
++#define WFD_ATTR_LOCAL_IP_ADDR 0x08
++#define WFD_ATTR_SESSION_INFO 0x09
++#define WFD_ATTR_ALTER_MAC 0x0a
++
++// For WFD Device Information Attribute
++#define WFD_DEVINFO_SOURCE 0x0000
++#define WFD_DEVINFO_PSINK 0x0001
++#define WFD_DEVINFO_SSINK 0x0002
++#define WFD_DEVINFO_DUAL 0x0003
++
++#define WFD_DEVINFO_SESSION_AVAIL 0x0010
++#define WFD_DEVINFO_WSD 0x0040
++#define WFD_DEVINFO_PC_TDLS 0x0080
++#define WFD_DEVINFO_HDCP_SUPPORT 0x0100
++
++
++#ifdef CONFIG_TX_MCAST2UNI
++#define IP_MCAST_MAC(mac) ((mac[0]==0x01)&&(mac[1]==0x00)&&(mac[2]==0x5e))
++#define ICMPV6_MCAST_MAC(mac) ((mac[0]==0x33)&&(mac[1]==0x33)&&(mac[2]!=0xff))
++#endif // CONFIG_TX_MCAST2UNI
++
++
++
++#endif // _WIFI_H_
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/wlan_bssdef.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/wlan_bssdef.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/wlan_bssdef.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/wlan_bssdef.h 2015-07-28 01:20:58.325583098 +0200
+@@ -0,0 +1,702 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef __WLAN_BSSDEF_H__
++#define __WLAN_BSSDEF_H__
++
++
++#define MAX_IE_SZ 768
++
++
++#ifdef PLATFORM_LINUX
++
++#define NDIS_802_11_LENGTH_SSID 32
++#define NDIS_802_11_LENGTH_RATES 8
++#define NDIS_802_11_LENGTH_RATES_EX 16
++
++typedef unsigned char NDIS_802_11_MAC_ADDRESS[6];
++typedef long NDIS_802_11_RSSI; // in dBm
++typedef unsigned char NDIS_802_11_RATES[NDIS_802_11_LENGTH_RATES]; // Set of 8 data rates
++typedef unsigned char NDIS_802_11_RATES_EX[NDIS_802_11_LENGTH_RATES_EX]; // Set of 16 data rates
++
++
++typedef ULONG NDIS_802_11_KEY_INDEX;
++typedef unsigned long long NDIS_802_11_KEY_RSC;
++
++
++typedef struct _NDIS_802_11_SSID
++{
++ ULONG SsidLength;
++ UCHAR Ssid[32];
++} NDIS_802_11_SSID, *PNDIS_802_11_SSID;
++
++typedef enum _NDIS_802_11_NETWORK_TYPE
++{
++ Ndis802_11FH,
++ Ndis802_11DS,
++ Ndis802_11OFDM5,
++ Ndis802_11OFDM24,
++ Ndis802_11NetworkTypeMax // not a real type, defined as an upper bound
++} NDIS_802_11_NETWORK_TYPE, *PNDIS_802_11_NETWORK_TYPE;
++
++typedef struct _NDIS_802_11_CONFIGURATION_FH
++{
++ ULONG Length; // Length of structure
++ ULONG HopPattern; // As defined by 802.11, MSB set
++ ULONG HopSet; // to one if non-802.11
++ ULONG DwellTime; // units are Kusec
++} NDIS_802_11_CONFIGURATION_FH, *PNDIS_802_11_CONFIGURATION_FH;
++
++
++/*
++ FW will only save the channel number in DSConfig.
++ ODI Handler will convert the channel number to freq. number.
++*/
++typedef struct _NDIS_802_11_CONFIGURATION
++{
++ ULONG Length; // Length of structure
++ ULONG BeaconPeriod; // units are Kusec
++ ULONG ATIMWindow; // units are Kusec
++ ULONG DSConfig; // Frequency, units are kHz
++ NDIS_802_11_CONFIGURATION_FH FHConfig;
++} NDIS_802_11_CONFIGURATION, *PNDIS_802_11_CONFIGURATION;
++
++
++
++typedef enum _NDIS_802_11_NETWORK_INFRASTRUCTURE
++{
++ Ndis802_11IBSS,
++ Ndis802_11Infrastructure,
++ Ndis802_11AutoUnknown,
++ Ndis802_11InfrastructureMax, // Not a real value, defined as upper bound
++ Ndis802_11APMode
++} NDIS_802_11_NETWORK_INFRASTRUCTURE, *PNDIS_802_11_NETWORK_INFRASTRUCTURE;
++
++
++
++
++
++typedef struct _NDIS_802_11_FIXED_IEs
++{
++ UCHAR Timestamp[8];
++ USHORT BeaconInterval;
++ USHORT Capabilities;
++} NDIS_802_11_FIXED_IEs, *PNDIS_802_11_FIXED_IEs;
++
++
++
++typedef struct _NDIS_802_11_VARIABLE_IEs
++{
++ UCHAR ElementID;
++ UCHAR Length;
++ UCHAR data[1];
++} NDIS_802_11_VARIABLE_IEs, *PNDIS_802_11_VARIABLE_IEs;
++
++
++
++/*
++
++
++
++Length is the 4 bytes multiples of the sume of
++ sizeof (NDIS_802_11_MAC_ADDRESS) + 2 + sizeof (NDIS_802_11_SSID) + sizeof (ULONG)
+++ sizeof (NDIS_802_11_RSSI) + sizeof (NDIS_802_11_NETWORK_TYPE) + sizeof (NDIS_802_11_CONFIGURATION)
+++ sizeof (NDIS_802_11_RATES_EX) + IELength
++
++Except the IELength, all other fields are fixed length. Therefore, we can define a marco to present the
++partial sum.
++
++*/
++#if 0
++typedef struct _NDIS_WLAN_BSSID_EX
++{
++ ULONG Length;
++ NDIS_802_11_MAC_ADDRESS MacAddress;
++ UCHAR Reserved[2];//[0]: IS beacon frame, [1]:optimum_antenna=>For antenna diversity;
++ NDIS_802_11_SSID Ssid;
++ ULONG Privacy;
++ NDIS_802_11_RSSI Rssi;
++ NDIS_802_11_NETWORK_TYPE NetworkTypeInUse;
++ NDIS_802_11_CONFIGURATION Configuration;
++ NDIS_802_11_NETWORK_INFRASTRUCTURE InfrastructureMode;
++ NDIS_802_11_RATES_EX SupportedRates;
++ ULONG IELength;
++ UCHAR IEs[MAX_IE_SZ]; //(timestamp, beacon interval, and capability information)
++} NDIS_WLAN_BSSID_EX, *PNDIS_WLAN_BSSID_EX;
++
++
++typedef struct _NDIS_802_11_BSSID_LIST_EX
++{
++ ULONG NumberOfItems;
++ NDIS_WLAN_BSSID_EX Bssid[1];
++} NDIS_802_11_BSSID_LIST_EX, *PNDIS_802_11_BSSID_LIST_EX;
++#endif
++
++typedef enum _NDIS_802_11_AUTHENTICATION_MODE
++{
++ Ndis802_11AuthModeOpen,
++ Ndis802_11AuthModeShared,
++ Ndis802_11AuthModeAutoSwitch,
++ Ndis802_11AuthModeWPA,
++ Ndis802_11AuthModeWPAPSK,
++ Ndis802_11AuthModeWPANone,
++ Ndis802_11AuthModeMax // Not a real mode, defined as upper bound
++} NDIS_802_11_AUTHENTICATION_MODE, *PNDIS_802_11_AUTHENTICATION_MODE;
++
++typedef enum _NDIS_802_11_WEP_STATUS
++{
++ Ndis802_11WEPEnabled,
++ Ndis802_11Encryption1Enabled = Ndis802_11WEPEnabled,
++ Ndis802_11WEPDisabled,
++ Ndis802_11EncryptionDisabled = Ndis802_11WEPDisabled,
++ Ndis802_11WEPKeyAbsent,
++ Ndis802_11Encryption1KeyAbsent = Ndis802_11WEPKeyAbsent,
++ Ndis802_11WEPNotSupported,
++ Ndis802_11EncryptionNotSupported = Ndis802_11WEPNotSupported,
++ Ndis802_11Encryption2Enabled,
++ Ndis802_11Encryption2KeyAbsent,
++ Ndis802_11Encryption3Enabled,
++ Ndis802_11Encryption3KeyAbsent
++} NDIS_802_11_WEP_STATUS, *PNDIS_802_11_WEP_STATUS,
++ NDIS_802_11_ENCRYPTION_STATUS, *PNDIS_802_11_ENCRYPTION_STATUS;
++
++
++#define NDIS_802_11_AI_REQFI_CAPABILITIES 1
++#define NDIS_802_11_AI_REQFI_LISTENINTERVAL 2
++#define NDIS_802_11_AI_REQFI_CURRENTAPADDRESS 4
++
++#define NDIS_802_11_AI_RESFI_CAPABILITIES 1
++#define NDIS_802_11_AI_RESFI_STATUSCODE 2
++#define NDIS_802_11_AI_RESFI_ASSOCIATIONID 4
++
++typedef struct _NDIS_802_11_AI_REQFI
++{
++ USHORT Capabilities;
++ USHORT ListenInterval;
++ NDIS_802_11_MAC_ADDRESS CurrentAPAddress;
++} NDIS_802_11_AI_REQFI, *PNDIS_802_11_AI_REQFI;
++
++typedef struct _NDIS_802_11_AI_RESFI
++{
++ USHORT Capabilities;
++ USHORT StatusCode;
++ USHORT AssociationId;
++} NDIS_802_11_AI_RESFI, *PNDIS_802_11_AI_RESFI;
++
++typedef struct _NDIS_802_11_ASSOCIATION_INFORMATION
++{
++ ULONG Length;
++ USHORT AvailableRequestFixedIEs;
++ NDIS_802_11_AI_REQFI RequestFixedIEs;
++ ULONG RequestIELength;
++ ULONG OffsetRequestIEs;
++ USHORT AvailableResponseFixedIEs;
++ NDIS_802_11_AI_RESFI ResponseFixedIEs;
++ ULONG ResponseIELength;
++ ULONG OffsetResponseIEs;
++} NDIS_802_11_ASSOCIATION_INFORMATION, *PNDIS_802_11_ASSOCIATION_INFORMATION;
++
++typedef enum _NDIS_802_11_RELOAD_DEFAULTS
++{
++ Ndis802_11ReloadWEPKeys
++} NDIS_802_11_RELOAD_DEFAULTS, *PNDIS_802_11_RELOAD_DEFAULTS;
++
++
++// Key mapping keys require a BSSID
++typedef struct _NDIS_802_11_KEY
++{
++ ULONG Length; // Length of this structure
++ ULONG KeyIndex;
++ ULONG KeyLength; // length of key in bytes
++ NDIS_802_11_MAC_ADDRESS BSSID;
++ NDIS_802_11_KEY_RSC KeyRSC;
++ UCHAR KeyMaterial[32]; // variable length depending on above field
++} NDIS_802_11_KEY, *PNDIS_802_11_KEY;
++
++typedef struct _NDIS_802_11_REMOVE_KEY
++{
++ ULONG Length; // Length of this structure
++ ULONG KeyIndex;
++ NDIS_802_11_MAC_ADDRESS BSSID;
++} NDIS_802_11_REMOVE_KEY, *PNDIS_802_11_REMOVE_KEY;
++
++typedef struct _NDIS_802_11_WEP
++{
++ ULONG Length; // Length of this structure
++ ULONG KeyIndex; // 0 is the per-client key, 1-N are the global keys
++ ULONG KeyLength; // length of key in bytes
++ UCHAR KeyMaterial[16];// variable length depending on above field
++} NDIS_802_11_WEP, *PNDIS_802_11_WEP;
++
++typedef struct _NDIS_802_11_AUTHENTICATION_REQUEST
++{
++ ULONG Length; // Length of structure
++ NDIS_802_11_MAC_ADDRESS Bssid;
++ ULONG Flags;
++} NDIS_802_11_AUTHENTICATION_REQUEST, *PNDIS_802_11_AUTHENTICATION_REQUEST;
++
++typedef enum _NDIS_802_11_STATUS_TYPE
++{
++ Ndis802_11StatusType_Authentication,
++ Ndis802_11StatusType_MediaStreamMode,
++ Ndis802_11StatusType_PMKID_CandidateList,
++ Ndis802_11StatusTypeMax // not a real type, defined as an upper bound
++} NDIS_802_11_STATUS_TYPE, *PNDIS_802_11_STATUS_TYPE;
++
++typedef struct _NDIS_802_11_STATUS_INDICATION
++{
++ NDIS_802_11_STATUS_TYPE StatusType;
++} NDIS_802_11_STATUS_INDICATION, *PNDIS_802_11_STATUS_INDICATION;
++
++// mask for authentication/integrity fields
++#define NDIS_802_11_AUTH_REQUEST_AUTH_FIELDS 0x0f
++#define NDIS_802_11_AUTH_REQUEST_REAUTH 0x01
++#define NDIS_802_11_AUTH_REQUEST_KEYUPDATE 0x02
++#define NDIS_802_11_AUTH_REQUEST_PAIRWISE_ERROR 0x06
++#define NDIS_802_11_AUTH_REQUEST_GROUP_ERROR 0x0E
++
++// MIC check time, 60 seconds.
++#define MIC_CHECK_TIME 60000000
++
++typedef struct _NDIS_802_11_AUTHENTICATION_EVENT
++{
++ NDIS_802_11_STATUS_INDICATION Status;
++ NDIS_802_11_AUTHENTICATION_REQUEST Request[1];
++} NDIS_802_11_AUTHENTICATION_EVENT, *PNDIS_802_11_AUTHENTICATION_EVENT;
++
++typedef struct _NDIS_802_11_TEST
++{
++ ULONG Length;
++ ULONG Type;
++ union
++ {
++ NDIS_802_11_AUTHENTICATION_EVENT AuthenticationEvent;
++ NDIS_802_11_RSSI RssiTrigger;
++ }tt;
++} NDIS_802_11_TEST, *PNDIS_802_11_TEST;
++
++
++#endif //end of #ifdef PLATFORM_LINUX
++
++#ifdef PLATFORM_FREEBSD
++
++#define NDIS_802_11_LENGTH_SSID 32
++#define NDIS_802_11_LENGTH_RATES 8
++#define NDIS_802_11_LENGTH_RATES_EX 16
++
++typedef unsigned char NDIS_802_11_MAC_ADDRESS[6];
++typedef long NDIS_802_11_RSSI; // in dBm
++typedef unsigned char NDIS_802_11_RATES[NDIS_802_11_LENGTH_RATES]; // Set of 8 data rates
++typedef unsigned char NDIS_802_11_RATES_EX[NDIS_802_11_LENGTH_RATES_EX]; // Set of 16 data rates
++
++
++typedef ULONG NDIS_802_11_KEY_INDEX;
++typedef unsigned long long NDIS_802_11_KEY_RSC;
++
++
++typedef struct _NDIS_802_11_SSID
++{
++ ULONG SsidLength;
++ UCHAR Ssid[32];
++} NDIS_802_11_SSID, *PNDIS_802_11_SSID;
++
++typedef enum _NDIS_802_11_NETWORK_TYPE
++{
++ Ndis802_11FH,
++ Ndis802_11DS,
++ Ndis802_11OFDM5,
++ Ndis802_11OFDM24,
++ Ndis802_11NetworkTypeMax // not a real type, defined as an upper bound
++} NDIS_802_11_NETWORK_TYPE, *PNDIS_802_11_NETWORK_TYPE;
++
++typedef struct _NDIS_802_11_CONFIGURATION_FH
++{
++ ULONG Length; // Length of structure
++ ULONG HopPattern; // As defined by 802.11, MSB set
++ ULONG HopSet; // to one if non-802.11
++ ULONG DwellTime; // units are Kusec
++} NDIS_802_11_CONFIGURATION_FH, *PNDIS_802_11_CONFIGURATION_FH;
++
++
++/*
++ FW will only save the channel number in DSConfig.
++ ODI Handler will convert the channel number to freq. number.
++*/
++typedef struct _NDIS_802_11_CONFIGURATION
++{
++ ULONG Length; // Length of structure
++ ULONG BeaconPeriod; // units are Kusec
++ ULONG ATIMWindow; // units are Kusec
++ ULONG DSConfig; // Frequency, units are kHz
++ NDIS_802_11_CONFIGURATION_FH FHConfig;
++} NDIS_802_11_CONFIGURATION, *PNDIS_802_11_CONFIGURATION;
++
++
++
++typedef enum _NDIS_802_11_NETWORK_INFRASTRUCTURE
++{
++ Ndis802_11IBSS,
++ Ndis802_11Infrastructure,
++ Ndis802_11AutoUnknown,
++ Ndis802_11InfrastructureMax, // Not a real value, defined as upper bound
++ Ndis802_11APMode
++} NDIS_802_11_NETWORK_INFRASTRUCTURE, *PNDIS_802_11_NETWORK_INFRASTRUCTURE;
++
++
++
++
++
++typedef struct _NDIS_802_11_FIXED_IEs
++{
++ UCHAR Timestamp[8];
++ USHORT BeaconInterval;
++ USHORT Capabilities;
++} NDIS_802_11_FIXED_IEs, *PNDIS_802_11_FIXED_IEs;
++
++
++
++typedef struct _NDIS_802_11_VARIABLE_IEs
++{
++ UCHAR ElementID;
++ UCHAR Length;
++ UCHAR data[1];
++} NDIS_802_11_VARIABLE_IEs, *PNDIS_802_11_VARIABLE_IEs;
++
++
++
++/*
++
++
++
++Length is the 4 bytes multiples of the sume of
++ sizeof (NDIS_802_11_MAC_ADDRESS) + 2 + sizeof (NDIS_802_11_SSID) + sizeof (ULONG)
+++ sizeof (NDIS_802_11_RSSI) + sizeof (NDIS_802_11_NETWORK_TYPE) + sizeof (NDIS_802_11_CONFIGURATION)
+++ sizeof (NDIS_802_11_RATES_EX) + IELength
++
++Except the IELength, all other fields are fixed length. Therefore, we can define a marco to present the
++partial sum.
++
++*/
++#if 0
++typedef struct _NDIS_WLAN_BSSID_EX
++{
++ ULONG Length;
++ NDIS_802_11_MAC_ADDRESS MacAddress;
++ UCHAR Reserved[2];//[0]: IS beacon frame, [1]:optimum_antenna=>For antenna diversity;
++ NDIS_802_11_SSID Ssid;
++ ULONG Privacy;
++ NDIS_802_11_RSSI Rssi;
++ NDIS_802_11_NETWORK_TYPE NetworkTypeInUse;
++ NDIS_802_11_CONFIGURATION Configuration;
++ NDIS_802_11_NETWORK_INFRASTRUCTURE InfrastructureMode;
++ NDIS_802_11_RATES_EX SupportedRates;
++ ULONG IELength;
++ UCHAR IEs[MAX_IE_SZ]; //(timestamp, beacon interval, and capability information)
++} NDIS_WLAN_BSSID_EX, *PNDIS_WLAN_BSSID_EX;
++
++
++typedef struct _NDIS_802_11_BSSID_LIST_EX
++{
++ ULONG NumberOfItems;
++ NDIS_WLAN_BSSID_EX Bssid[1];
++} NDIS_802_11_BSSID_LIST_EX, *PNDIS_802_11_BSSID_LIST_EX;
++#endif
++
++typedef enum _NDIS_802_11_AUTHENTICATION_MODE
++{
++ Ndis802_11AuthModeOpen,
++ Ndis802_11AuthModeShared,
++ Ndis802_11AuthModeAutoSwitch,
++ Ndis802_11AuthModeWPA,
++ Ndis802_11AuthModeWPAPSK,
++ Ndis802_11AuthModeWPANone,
++ Ndis802_11AuthModeMax // Not a real mode, defined as upper bound
++} NDIS_802_11_AUTHENTICATION_MODE, *PNDIS_802_11_AUTHENTICATION_MODE;
++
++typedef enum _NDIS_802_11_WEP_STATUS
++{
++ Ndis802_11WEPEnabled,
++ Ndis802_11Encryption1Enabled = Ndis802_11WEPEnabled,
++ Ndis802_11WEPDisabled,
++ Ndis802_11EncryptionDisabled = Ndis802_11WEPDisabled,
++ Ndis802_11WEPKeyAbsent,
++ Ndis802_11Encryption1KeyAbsent = Ndis802_11WEPKeyAbsent,
++ Ndis802_11WEPNotSupported,
++ Ndis802_11EncryptionNotSupported = Ndis802_11WEPNotSupported,
++ Ndis802_11Encryption2Enabled,
++ Ndis802_11Encryption2KeyAbsent,
++ Ndis802_11Encryption3Enabled,
++ Ndis802_11Encryption3KeyAbsent
++} NDIS_802_11_WEP_STATUS, *PNDIS_802_11_WEP_STATUS,
++ NDIS_802_11_ENCRYPTION_STATUS, *PNDIS_802_11_ENCRYPTION_STATUS;
++
++
++#define NDIS_802_11_AI_REQFI_CAPABILITIES 1
++#define NDIS_802_11_AI_REQFI_LISTENINTERVAL 2
++#define NDIS_802_11_AI_REQFI_CURRENTAPADDRESS 4
++
++#define NDIS_802_11_AI_RESFI_CAPABILITIES 1
++#define NDIS_802_11_AI_RESFI_STATUSCODE 2
++#define NDIS_802_11_AI_RESFI_ASSOCIATIONID 4
++
++typedef struct _NDIS_802_11_AI_REQFI
++{
++ USHORT Capabilities;
++ USHORT ListenInterval;
++ NDIS_802_11_MAC_ADDRESS CurrentAPAddress;
++} NDIS_802_11_AI_REQFI, *PNDIS_802_11_AI_REQFI;
++
++typedef struct _NDIS_802_11_AI_RESFI
++{
++ USHORT Capabilities;
++ USHORT StatusCode;
++ USHORT AssociationId;
++} NDIS_802_11_AI_RESFI, *PNDIS_802_11_AI_RESFI;
++
++typedef struct _NDIS_802_11_ASSOCIATION_INFORMATION
++{
++ ULONG Length;
++ USHORT AvailableRequestFixedIEs;
++ NDIS_802_11_AI_REQFI RequestFixedIEs;
++ ULONG RequestIELength;
++ ULONG OffsetRequestIEs;
++ USHORT AvailableResponseFixedIEs;
++ NDIS_802_11_AI_RESFI ResponseFixedIEs;
++ ULONG ResponseIELength;
++ ULONG OffsetResponseIEs;
++} NDIS_802_11_ASSOCIATION_INFORMATION, *PNDIS_802_11_ASSOCIATION_INFORMATION;
++
++typedef enum _NDIS_802_11_RELOAD_DEFAULTS
++{
++ Ndis802_11ReloadWEPKeys
++} NDIS_802_11_RELOAD_DEFAULTS, *PNDIS_802_11_RELOAD_DEFAULTS;
++
++
++// Key mapping keys require a BSSID
++typedef struct _NDIS_802_11_KEY
++{
++ ULONG Length; // Length of this structure
++ ULONG KeyIndex;
++ ULONG KeyLength; // length of key in bytes
++ NDIS_802_11_MAC_ADDRESS BSSID;
++ NDIS_802_11_KEY_RSC KeyRSC;
++ UCHAR KeyMaterial[32]; // variable length depending on above field
++} NDIS_802_11_KEY, *PNDIS_802_11_KEY;
++
++typedef struct _NDIS_802_11_REMOVE_KEY
++{
++ ULONG Length; // Length of this structure
++ ULONG KeyIndex;
++ NDIS_802_11_MAC_ADDRESS BSSID;
++} NDIS_802_11_REMOVE_KEY, *PNDIS_802_11_REMOVE_KEY;
++
++typedef struct _NDIS_802_11_WEP
++{
++ ULONG Length; // Length of this structure
++ ULONG KeyIndex; // 0 is the per-client key, 1-N are the global keys
++ ULONG KeyLength; // length of key in bytes
++ UCHAR KeyMaterial[16];// variable length depending on above field
++} NDIS_802_11_WEP, *PNDIS_802_11_WEP;
++
++typedef struct _NDIS_802_11_AUTHENTICATION_REQUEST
++{
++ ULONG Length; // Length of structure
++ NDIS_802_11_MAC_ADDRESS Bssid;
++ ULONG Flags;
++} NDIS_802_11_AUTHENTICATION_REQUEST, *PNDIS_802_11_AUTHENTICATION_REQUEST;
++
++typedef enum _NDIS_802_11_STATUS_TYPE
++{
++ Ndis802_11StatusType_Authentication,
++ Ndis802_11StatusType_MediaStreamMode,
++ Ndis802_11StatusType_PMKID_CandidateList,
++ Ndis802_11StatusTypeMax // not a real type, defined as an upper bound
++} NDIS_802_11_STATUS_TYPE, *PNDIS_802_11_STATUS_TYPE;
++
++typedef struct _NDIS_802_11_STATUS_INDICATION
++{
++ NDIS_802_11_STATUS_TYPE StatusType;
++} NDIS_802_11_STATUS_INDICATION, *PNDIS_802_11_STATUS_INDICATION;
++
++// mask for authentication/integrity fields
++#define NDIS_802_11_AUTH_REQUEST_AUTH_FIELDS 0x0f
++#define NDIS_802_11_AUTH_REQUEST_REAUTH 0x01
++#define NDIS_802_11_AUTH_REQUEST_KEYUPDATE 0x02
++#define NDIS_802_11_AUTH_REQUEST_PAIRWISE_ERROR 0x06
++#define NDIS_802_11_AUTH_REQUEST_GROUP_ERROR 0x0E
++
++// MIC check time, 60 seconds.
++#define MIC_CHECK_TIME 60000000
++
++typedef struct _NDIS_802_11_AUTHENTICATION_EVENT
++{
++ NDIS_802_11_STATUS_INDICATION Status;
++ NDIS_802_11_AUTHENTICATION_REQUEST Request[1];
++} NDIS_802_11_AUTHENTICATION_EVENT, *PNDIS_802_11_AUTHENTICATION_EVENT;
++
++typedef struct _NDIS_802_11_TEST
++{
++ ULONG Length;
++ ULONG Type;
++ union
++ {
++ NDIS_802_11_AUTHENTICATION_EVENT AuthenticationEvent;
++ NDIS_802_11_RSSI RssiTrigger;
++ }tt;
++} NDIS_802_11_TEST, *PNDIS_802_11_TEST;
++
++
++#endif //PLATFORM_FREEBSD
++#ifndef Ndis802_11APMode
++#define Ndis802_11APMode (Ndis802_11InfrastructureMax+1)
++#endif
++
++typedef struct _WLAN_PHY_INFO
++{
++ u8 SignalStrength;//(in percentage)
++ u8 SignalQuality;//(in percentage)
++ u8 Optimum_antenna; //for Antenna diversity
++ u8 Reserved_0;
++}WLAN_PHY_INFO,*PWLAN_PHY_INFO;
++
++/* temporally add #pragma pack for structure alignment issue of
++* WLAN_BSSID_EX and get_WLAN_BSSID_EX_sz()
++*/
++#ifdef PLATFORM_WINDOWS
++#pragma pack(push)
++#pragma pack(1)
++#endif
++typedef struct _WLAN_BSSID_EX
++{
++ ULONG Length;
++ NDIS_802_11_MAC_ADDRESS MacAddress;
++ UCHAR Reserved[2];//[0]: IS beacon frame
++ NDIS_802_11_SSID Ssid;
++ ULONG Privacy;
++ NDIS_802_11_RSSI Rssi;//(in dBM,raw data ,get from PHY)
++ NDIS_802_11_NETWORK_TYPE NetworkTypeInUse;
++ NDIS_802_11_CONFIGURATION Configuration;
++ NDIS_802_11_NETWORK_INFRASTRUCTURE InfrastructureMode;
++ NDIS_802_11_RATES_EX SupportedRates;
++ WLAN_PHY_INFO PhyInfo;
++ ULONG IELength;
++ UCHAR IEs[MAX_IE_SZ]; //(timestamp, beacon interval, and capability information)
++}
++#ifndef PLATFORM_WINDOWS
++__attribute__((packed))
++#endif
++WLAN_BSSID_EX, *PWLAN_BSSID_EX;
++#ifdef PLATFORM_WINDOWS
++#pragma pack(pop)
++#endif
++
++__inline static uint get_WLAN_BSSID_EX_sz(WLAN_BSSID_EX *bss)
++{
++ return (sizeof(WLAN_BSSID_EX) - MAX_IE_SZ + bss->IELength);
++}
++
++struct wlan_network {
++ _list list;
++ int network_type; //refer to ieee80211.h for WIRELESS_11A/B/G
++ int fixed; // set to fixed when not to be removed as site-surveying
++ unsigned long last_scanned; //timestamp for the network
++ int aid; //will only be valid when a BSS is joinned.
++ int join_res;
++ WLAN_BSSID_EX network; //must be the last item
++#ifdef PLATFORM_WINDOWS
++ unsigned char iebuf[MAX_IE_SZ];
++#endif
++
++};
++
++enum VRTL_CARRIER_SENSE
++{
++ DISABLE_VCS,
++ ENABLE_VCS,
++ AUTO_VCS
++};
++
++enum VCS_TYPE
++{
++ NONE_VCS,
++ RTS_CTS,
++ CTS_TO_SELF
++};
++
++
++
++
++#define PWR_CAM 0
++#define PWR_MINPS 1
++#define PWR_MAXPS 2
++#define PWR_UAPSD 3
++#define PWR_VOIP 4
++
++
++enum UAPSD_MAX_SP
++{
++ NO_LIMIT,
++ TWO_MSDU,
++ FOUR_MSDU,
++ SIX_MSDU
++};
++
++
++//john
++#define NUM_PRE_AUTH_KEY 16
++#define NUM_PMKID_CACHE NUM_PRE_AUTH_KEY
++
++/*
++* WPA2
++*/
++
++#ifndef PLATFORM_OS_CE
++typedef struct _PMKID_CANDIDATE {
++ NDIS_802_11_MAC_ADDRESS BSSID;
++ ULONG Flags;
++} PMKID_CANDIDATE, *PPMKID_CANDIDATE;
++
++typedef struct _NDIS_802_11_PMKID_CANDIDATE_LIST
++{
++ ULONG Version; // Version of the structure
++ ULONG NumCandidates; // No. of pmkid candidates
++ PMKID_CANDIDATE CandidateList[1];
++} NDIS_802_11_PMKID_CANDIDATE_LIST, *PNDIS_802_11_PMKID_CANDIDATE_LIST;
++
++
++typedef struct _NDIS_802_11_AUTHENTICATION_ENCRYPTION
++{
++ NDIS_802_11_AUTHENTICATION_MODE AuthModeSupported;
++ NDIS_802_11_ENCRYPTION_STATUS EncryptStatusSupported;
++
++} NDIS_802_11_AUTHENTICATION_ENCRYPTION, *PNDIS_802_11_AUTHENTICATION_ENCRYPTION;
++
++typedef struct _NDIS_802_11_CAPABILITY
++{
++ ULONG Length;
++ ULONG Version;
++ ULONG NoOfPMKIDs;
++ ULONG NoOfAuthEncryptPairsSupported;
++ NDIS_802_11_AUTHENTICATION_ENCRYPTION AuthenticationEncryptionSupported[1];
++
++} NDIS_802_11_CAPABILITY, *PNDIS_802_11_CAPABILITY;
++#endif
++
++
++#endif //#ifndef WLAN_BSSDEF_H_
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/include/xmit_osdep.h linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/xmit_osdep.h
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/include/xmit_osdep.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/include/xmit_osdep.h 2015-07-28 01:20:58.325583098 +0200
+@@ -0,0 +1,94 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef __XMIT_OSDEP_H_
++#define __XMIT_OSDEP_H_
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++
++struct pkt_file {
++ _pkt *pkt;
++ SIZE_T pkt_len; //the remainder length of the open_file
++ _buffer *cur_buffer;
++ u8 *buf_start;
++ u8 *cur_addr;
++ SIZE_T buf_len;
++};
++
++#ifdef PLATFORM_WINDOWS
++
++#ifdef PLATFORM_OS_XP
++#ifdef CONFIG_USB_HCI
++#include <usb.h>
++#include <usbdlib.h>
++#include <usbioctl.h>
++#endif
++#endif
++
++#define NR_XMITFRAME 128
++
++#define ETH_ALEN 6
++
++extern NDIS_STATUS rtw_xmit_entry(
++IN _nic_hdl cnxt,
++IN NDIS_PACKET *pkt,
++IN UINT flags
++);
++
++#endif
++
++#ifdef PLATFORM_FREEBSD
++#define NR_XMITFRAME 256
++extern int rtw_xmit_entry(_pkt *pkt, _nic_hdl pnetdev);
++extern void rtw_xmit_entry_wrap (struct ifnet * pifp);
++#endif //PLATFORM_FREEBSD
++
++#ifdef PLATFORM_LINUX
++
++#define NR_XMITFRAME 256
++
++struct xmit_priv;
++struct pkt_attrib;
++struct sta_xmit_priv;
++struct xmit_frame;
++struct xmit_buf;
++
++extern int _rtw_xmit_entry(_pkt *pkt, _nic_hdl pnetdev);
++extern int rtw_xmit_entry(_pkt *pkt, _nic_hdl pnetdev);
++
++#endif
++
++void rtw_os_xmit_schedule(_adapter *padapter);
++
++int rtw_os_xmit_resource_alloc(_adapter *padapter, struct xmit_buf *pxmitbuf,u32 alloc_sz);
++void rtw_os_xmit_resource_free(_adapter *padapter, struct xmit_buf *pxmitbuf,u32 free_sz);
++
++extern void rtw_set_tx_chksum_offload(_pkt *pkt, struct pkt_attrib *pattrib);
++
++extern uint rtw_remainder_len(struct pkt_file *pfile);
++extern void _rtw_open_pktfile(_pkt *pkt, struct pkt_file *pfile);
++extern uint _rtw_pktfile_read (struct pkt_file *pfile, u8 *rmem, uint rlen);
++extern sint rtw_endofpktfile (struct pkt_file *pfile);
++
++extern void rtw_os_pkt_complete(_adapter *padapter, _pkt *pkt);
++extern void rtw_os_xmit_complete(_adapter *padapter, struct xmit_frame *pxframe);
++
++#endif //__XMIT_OSDEP_H_
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/Kconfig linux-xbian-rpi/drivers/net/wireless/rtl8192cu/Kconfig
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/Kconfig 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/Kconfig 2015-07-28 01:20:58.297682643 +0200
+@@ -0,0 +1,9 @@
++config RTL8192CU
++ tristate "Realtek 8192C USB WiFi"
++ depends on MAC80211 && USB
++ select CFG80211_WEXT
++ select WIRELESS_EXT
++ select WEXT_PRIV
++ ---help---
++ This option adds the Realtek RTL8192CU USB device such as Edimax EW-7811Un.
++
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/Makefile linux-xbian-rpi/drivers/net/wireless/rtl8192cu/Makefile
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/Makefile 2015-07-28 01:20:58.297682643 +0200
+@@ -0,0 +1,615 @@
++EXTRA_CFLAGS += $(USER_EXTRA_CFLAGS)
++EXTRA_CFLAGS += -O1
++#EXTRA_CFLAGS += -O3
++#EXTRA_CFLAGS += -Wall
++#EXTRA_CFLAGS += -Wextra
++#EXTRA_CFLAGS += -Werror
++#EXTRA_CFLAGS += -pedantic
++#EXTRA_CFLAGS += -Wshadow -Wpointer-arith -Wcast-qual -Wstrict-prototypes -Wmissing-prototypes
++
++EXTRA_CFLAGS += -Wno-unused-variable
++EXTRA_CFLAGS += -Wno-unused-value
++EXTRA_CFLAGS += -Wno-unused-label
++EXTRA_CFLAGS += -Wno-unused-parameter
++EXTRA_CFLAGS += -Wno-unused-function
++EXTRA_CFLAGS += -Wno-unused
++
++EXTRA_CFLAGS += -Wno-uninitialized
++
++EXTRA_CFLAGS += -I$(src)/include
++
++CONFIG_AUTOCFG_CP = n
++
++CONFIG_RTL8192C = y
++CONFIG_RTL8192D = n
++CONFIG_RTL8723A = n
++
++CONFIG_USB_HCI = y
++CONFIG_PCI_HCI = n
++CONFIG_SDIO_HCI = n
++
++CONFIG_MP_INCLUDED = n
++CONFIG_POWER_SAVING = y
++CONFIG_USB_AUTOSUSPEND = n
++CONFIG_HW_PWRP_DETECTION = n
++CONFIG_WIFI_TEST = n
++CONFIG_BT_COEXISTENCE = n
++CONFIG_RTL8192CU_REDEFINE_1X1 = n
++CONFIG_INTEL_WIDI = n
++CONFIG_WAKE_ON_WLAN = n
++
++CONFIG_PLATFORM_I386_PC = y
++CONFIG_PLATFORM_TI_AM3517 = n
++CONFIG_PLATFORM_ANDROID_X86 = n
++CONFIG_PLATFORM_JB_X86 = n
++CONFIG_PLATFORM_ARM_S3C2K4 = n
++CONFIG_PLATFORM_ARM_PXA2XX = n
++CONFIG_PLATFORM_ARM_S3C6K4 = n
++CONFIG_PLATFORM_MIPS_RMI = n
++CONFIG_PLATFORM_RTD2880B = n
++CONFIG_PLATFORM_MIPS_AR9132 = n
++CONFIG_PLATFORM_RTK_DMP = n
++CONFIG_PLATFORM_MIPS_PLM = n
++CONFIG_PLATFORM_MSTAR389 = n
++CONFIG_PLATFORM_MT53XX = n
++CONFIG_PLATFORM_ARM_MX51_241H = n
++CONFIG_PLATFORM_FS_MX61 = n
++CONFIG_PLATFORM_ACTIONS_ATJ227X = n
++CONFIG_PLATFORM_TEGRA3_CARDHU = n
++CONFIG_PLATFORM_TEGRA4_DALMORE = n
++CONFIG_PLATFORM_ARM_TCC8900 = n
++CONFIG_PLATFORM_ARM_TCC8920 = n
++CONFIG_PLATFORM_ARM_TCC8920_JB42 = n
++CONFIG_PLATFORM_ARM_RK2818 = n
++CONFIG_PLATFORM_ARM_TI_PANDA = n
++CONFIG_PLATFORM_MIPS_JZ4760 = n
++CONFIG_PLATFORM_DMP_PHILIPS = n
++CONFIG_PLATFORM_TI_DM365 = n
++CONFIG_PLATFORM_MN10300 = n
++CONFIG_PLATFORM_MSTAR_TITANIA12 = n
++CONFIG_PLATFORM_MSTAR_A3 = n
++CONFIG_PLATFORM_ARM_SUNxI = n
++CONFIG_PLATFORM_ARM_SUN6I = n
++
++CONFIG_DRVEXT_MODULE = n
++
++export TopDIR ?= $(shell pwd)
++
++
++ifeq ($(CONFIG_RTL8192C), y)
++
++RTL871X = rtl8192c
++
++ifeq ($(CONFIG_USB_HCI), y)
++MODULE_NAME = 8192cu
++FW_FILES := hal/$(RTL871X)/usb/Hal8192CUHWImg.o
++ifneq ($(CONFIG_WAKE_ON_WLAN), n)
++FW_FILES += hal/$(RTL871X)/usb/Hal8192CUHWImg_wowlan.o
++endif
++endif
++ifeq ($(CONFIG_PCI_HCI), y)
++MODULE_NAME = 8192ce
++FW_FILES := hal/$(RTL871X)/pci/Hal8192CEHWImg.o
++endif
++
++CHIP_FILES := \
++ hal/$(RTL871X)/$(RTL871X)_sreset.o \
++ hal/$(RTL871X)/$(RTL871X)_xmit.o
++CHIP_FILES += $(FW_FILES)
++endif
++
++ifeq ($(CONFIG_RTL8192D), y)
++
++RTL871X = rtl8192d
++
++ifeq ($(CONFIG_USB_HCI), y)
++MODULE_NAME = 8192du
++FW_FILES := hal/$(RTL871X)/usb/Hal8192DUHWImg.o
++ifneq ($(CONFIG_WAKE_ON_WLAN), n)
++FW_FILES += hal/$(RTL871X)/usb/Hal8192DUHWImg_wowlan.o
++endif
++endif
++ifeq ($(CONFIG_PCI_HCI), y)
++MODULE_NAME = 8192de
++FW_FILES := hal/$(RTL871X)/pci/Hal8192DEHWImg.o
++endif
++
++CHIP_FILES := \
++ hal/$(RTL871X)/$(RTL871X)_xmit.o
++CHIP_FILES += $(FW_FILES)
++endif
++
++ifeq ($(CONFIG_RTL8723A), y)
++
++RTL871X = rtl8723a
++
++ifeq ($(CONFIG_SDIO_HCI), y)
++MODULE_NAME = 8723as
++FW_FILES := hal/$(RTL871X)/sdio/Hal8723SHWImg.o
++endif
++
++ifeq ($(CONFIG_USB_HCI), y)
++MODULE_NAME = 8723au
++FW_FILES := hal/$(RTL871X)/usb/Hal8723UHWImg.o
++endif
++
++ifeq ($(CONFIG_PCI_HCI), y)
++MODULE_NAME = 8723ae
++FW_FILES := hal/$(RTL871X)/pci/Hal8723EHWImg.o
++endif
++
++PWRSEQ_FILES := hal/HalPwrSeqCmd.o \
++ hal/$(RTL871X)/Hal8723PwrSeq.o
++
++CHIP_FILES += $(FW_FILES) $(PWRSEQ_FILES)
++
++endif
++
++ifeq ($(CONFIG_SDIO_HCI), y)
++HCI_NAME = sdio
++endif
++
++ifeq ($(CONFIG_USB_HCI), y)
++HCI_NAME = usb
++endif
++
++ifeq ($(CONFIG_PCI_HCI), y)
++HCI_NAME = pci
++endif
++
++
++_OS_INTFS_FILES := os_dep/osdep_service.o \
++ os_dep/linux/os_intfs.o \
++ os_dep/linux/$(HCI_NAME)_intf.o \
++ os_dep/linux/$(HCI_NAME)_ops_linux.o \
++ os_dep/linux/ioctl_linux.o \
++ os_dep/linux/xmit_linux.o \
++ os_dep/linux/mlme_linux.o \
++ os_dep/linux/recv_linux.o \
++ os_dep/linux/ioctl_cfg80211.o \
++ os_dep/linux/rtw_android.o
++
++
++_HAL_INTFS_FILES := hal/hal_intf.o \
++ hal/hal_com.o \
++ hal/dm.o \
++ hal/$(RTL871X)/$(RTL871X)_hal_init.o \
++ hal/$(RTL871X)/$(RTL871X)_phycfg.o \
++ hal/$(RTL871X)/$(RTL871X)_rf6052.o \
++ hal/$(RTL871X)/$(RTL871X)_dm.o \
++ hal/$(RTL871X)/$(RTL871X)_rxdesc.o \
++ hal/$(RTL871X)/$(RTL871X)_cmd.o \
++ hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \
++ hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_led.o \
++ hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_xmit.o \
++ hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_recv.o
++
++ifeq ($(CONFIG_SDIO_HCI), y)
++_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o
++else
++_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops_linux.o
++endif
++
++ifeq ($(CONFIG_MP_INCLUDED), y)
++_HAL_INTFS_FILES += hal/$(RTL871X)/$(RTL871X)_mp.o
++endif
++
++_HAL_INTFS_FILES += $(CHIP_FILES)
++
++
++ifeq ($(CONFIG_AUTOCFG_CP), y)
++$(shell cp $(TopDIR)/autoconf_$(RTL871X)_$(HCI_NAME)_linux.h $(TopDIR)/include/autoconf.h)
++endif
++
++
++ifeq ($(CONFIG_USB_HCI), y)
++ifeq ($(CONFIG_USB_AUTOSUSPEND), y)
++EXTRA_CFLAGS += -DCONFIG_USB_AUTOSUSPEND
++endif
++endif
++
++ifeq ($(CONFIG_POWER_SAVING), y)
++EXTRA_CFLAGS += -DCONFIG_POWER_SAVING
++endif
++
++ifeq ($(CONFIG_HW_PWRP_DETECTION), y)
++EXTRA_CFLAGS += -DCONFIG_HW_PWRP_DETECTION
++endif
++
++ifeq ($(CONFIG_WIFI_TEST), y)
++EXTRA_CFLAGS += -DCONFIG_WIFI_TEST
++endif
++
++ifeq ($(CONFIG_BT_COEXISTENCE), y)
++EXTRA_CFLAGS += -DCONFIG_BT_COEXISTENCE
++endif
++
++ifeq ($(CONFIG_RTL8192CU_REDEFINE_1X1), y)
++EXTRA_CFLAGS += -DRTL8192C_RECONFIG_TO_1T1R
++endif
++
++ifeq ($(CONFIG_WAKE_ON_WLAN), y)
++EXTRA_CFLAGS += -DCONFIG_WAKE_ON_WLAN
++endif
++
++ifeq ($(CONFIG_INTEL_WIDI), y)
++EXTRA_CFLAGS += -DCONFIG_INTEL_WIDI
++endif
++
++ifeq ($(CONFIG_PLATFORM_I386_PC), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
++SUBARCH := $(shell uname -m | sed -e s/i.86/i386/)
++ARCH ?= $(SUBARCH)
++CROSS_COMPILE ?=
++KVER := $(shell uname -r)
++KSRC := /lib/modules/$(KVER)/build
++MODDESTDIR := /lib/modules/$(KVER)/kernel/drivers/net/wireless/
++INSTALL_PREFIX :=
++endif
++
++ifeq ($(CONFIG_PLATFORM_TI_AM3517), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ANDROID -DCONFIG_PLATFORM_SHUTTLE
++CROSS_COMPILE := arm-eabi-
++KSRC := $(shell pwd)/../../../Android/kernel
++ARCH := arm
++endif
++
++ifeq ($(CONFIG_PLATFORM_MSTAR_TITANIA12), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_MSTAR -DCONFIG_PLATFORM_MSTAR_TITANIA12
++ARCH:=mips
++CROSS_COMPILE:= /usr/src/Mstar_kernel/mips-4.3/bin/mips-linux-gnu-
++KVER:= 2.6.28.9
++KSRC:= /usr/src/Mstar_kernel/2.6.28.9/
++endif
++
++ifeq ($(CONFIG_PLATFORM_MSTAR_A3), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_MSTAR -DCONFIG_PLATFORM_MSTAR_A3
++ARCH:=arm
++CROSS_COMPILE:= arm-none-linux-gnueabi-
++KVER:= 2.6.35.11
++KSRC:= /home/gary/PERFORCE/THEALE/RedLion/2.6.35.11/
++MODULE_NAME = wlan
++endif
++
++ifeq ($(CONFIG_PLATFORM_ANDROID_X86), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
++SUBARCH := $(shell uname -m | sed -e s/i.86/i386/)
++ARCH := $(SUBARCH)
++CROSS_COMPILE := /media/DATA-2/android-x86/ics-x86_20120130/prebuilt/linux-x86/toolchain/i686-unknown-linux-gnu-4.2.1/bin/i686-unknown-linux-gnu-
++KSRC := /media/DATA-2/android-x86/ics-x86_20120130/out/target/product/generic_x86/obj/kernel
++MODULE_NAME :=wlan
++endif
++
++ifeq ($(CONFIG_PLATFORM_JB_X86), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
++EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
++EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
++EXTRA_CFLAGS += -DCONFIG_P2P_IPS
++SUBARCH := $(shell uname -m | sed -e s/i.86/i386/)
++ARCH := $(SUBARCH)
++CROSS_COMPILE := /home/android_sdk/android-x86_JB/prebuilts/gcc/linux-x86/x86/i686-linux-android-4.7/bin/i686-linux-android-
++KSRC := /home/android_sdk/android-x86_JB/out/target/product/x86/obj/kernel/
++MODULE_NAME :=wlan
++endif
++
++ifeq ($(CONFIG_PLATFORM_ARM_PXA2XX), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
++ARCH := arm
++CROSS_COMPILE := arm-none-linux-gnueabi-
++KVER := 2.6.34.1
++KSRC ?= /usr/src/linux-2.6.34.1
++endif
++
++ifeq ($(CONFIG_PLATFORM_ARM_S3C2K4), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
++ARCH := arm
++CROSS_COMPILE := arm-linux-
++KVER := 2.6.24.7_$(ARCH)
++KSRC := /usr/src/kernels/linux-$(KVER)
++endif
++
++ifeq ($(CONFIG_PLATFORM_ARM_S3C6K4), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
++ARCH := arm
++CROSS_COMPILE := arm-none-linux-gnueabi-
++KVER := 2.6.34.1
++KSRC ?= /usr/src/linux-2.6.34.1
++endif
++
++ifeq ($(CONFIG_PLATFORM_RTD2880B), y)
++EXTRA_CFLAGS += -DCONFIG_BIG_ENDIAN -DCONFIG_PLATFORM_RTD2880B
++ARCH:=
++CROSS_COMPILE:=
++KVER:=
++KSRC:=
++endif
++
++ifeq ($(CONFIG_PLATFORM_MIPS_RMI), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
++ARCH:=mips
++CROSS_COMPILE:=mipsisa32r2-uclibc-
++KVER:=
++KSRC:= /root/work/kernel_realtek
++endif
++
++ifeq ($(CONFIG_PLATFORM_MIPS_PLM), y)
++EXTRA_CFLAGS += -DCONFIG_BIG_ENDIAN
++ARCH:=mips
++CROSS_COMPILE:=mipsisa32r2-uclibc-
++KVER:=
++KSRC:= /root/work/kernel_realtek
++endif
++
++ifeq ($(CONFIG_PLATFORM_MSTAR389), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_MSTAR389
++ARCH:=mips
++CROSS_COMPILE:= mips-linux-gnu-
++KVER:= 2.6.28.10
++KSRC:= /home/mstar/mstar_linux/2.6.28.9/
++endif
++
++ifeq ($(CONFIG_PLATFORM_MIPS_AR9132), y)
++EXTRA_CFLAGS += -DCONFIG_BIG_ENDIAN
++ARCH := mips
++CROSS_COMPILE := mips-openwrt-linux-
++KSRC := /home/alex/test_openwrt/tmp/linux-2.6.30.9
++endif
++
++ifeq ($(CONFIG_PLATFORM_DMP_PHILIPS), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DRTK_DMP_PLATFORM
++ARCH := mips
++#CROSS_COMPILE:=/usr/local/msdk-4.3.6-mips-EL-2.6.12.6-0.9.30.3/bin/mipsel-linux-
++CROSS_COMPILE:=/usr/local/toolchain_mipsel/bin/mipsel-linux-
++KSRC ?=/usr/local/Jupiter/linux-2.6.12
++endif
++
++ifeq ($(CONFIG_PLATFORM_RTK_DMP), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DRTK_DMP_PLATFORM
++ARCH:=mips
++CROSS_COMPILE:=mipsel-linux-
++KVER:=
++KSRC ?= /usr/src/DMP_Kernel/jupiter/linux-2.6.12
++endif
++
++ifeq ($(CONFIG_PLATFORM_MT53XX), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_MT53XX
++ARCH:= arm
++CROSS_COMPILE:= arm11_mtk_le-
++KVER:= 2.6.27
++KSRC?= /proj/mtk00802/BD_Compare/BDP/Dev/BDP_V301/BDP_Linux/linux-2.6.27
++endif
++
++ifeq ($(CONFIG_PLATFORM_ARM_MX51_241H), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_WISTRON_PLATFORM
++ARCH := arm
++CROSS_COMPILE := /opt/freescale/usr/local/gcc-4.1.2-glibc-2.5-nptl-3/arm-none-linux-gnueabi/bin/arm-none-linux-gnueabi-
++KVER := 2.6.31
++KSRC ?= /lib/modules/2.6.31-770-g0e46b52/source
++endif
++
++ifeq ($(CONFIG_PLATFORM_FS_MX61), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
++ARCH := arm
++CROSS_COMPILE := /home/share/CusEnv/FreeScale/arm-eabi-4.4.3/bin/arm-eabi-
++KSRC ?= /home/share/CusEnv/FreeScale/FS_kernel_env
++endif
++
++
++
++ifeq ($(CONFIG_PLATFORM_ACTIONS_ATJ227X), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ACTIONS_ATJ227X
++ARCH := mips
++CROSS_COMPILE := /home/cnsd4/project/actions/tools-2.6.27/bin/mipsel-linux-gnu-
++KVER := 2.6.27
++KSRC := /home/cnsd4/project/actions/linux-2.6.27.28
++endif
++
++ifeq ($(CONFIG_PLATFORM_TI_DM365), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_TI_DM365
++ARCH := arm
++CROSS_COMPILE := /home/cnsd4/Appro/mv_pro_5.0/montavista/pro/devkit/arm/v5t_le/bin/arm_v5t_le-
++KVER := 2.6.18
++KSRC := /home/cnsd4/Appro/mv_pro_5.0/montavista/pro/devkit/lsp/ti-davinci/linux-dm365
++endif
++
++ifeq ($(CONFIG_PLATFORM_TEGRA3_CARDHU), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
++# default setting for Android 4.1, 4.2
++EXTRA_CFLAGS += -DRTW_ENABLE_WIFI_CONTROL_FUNC
++EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
++EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
++EXTRA_CFLAGS += -DCONFIG_P2P_IPS
++ARCH := arm
++CROSS_COMPILE := /home/android_sdk/nvidia/tegra-16r3-partner-android-4.1_20120723/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/bin/arm-eabi-
++KSRC := /home/android_sdk/nvidia/tegra-16r3-partner-android-4.1_20120723/out/target/product/cardhu/obj/KERNEL
++MODULE_NAME := wlan
++endif
++
++ifeq ($(CONFIG_PLATFORM_TEGRA4_DALMORE), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
++# default setting for Android 4.1, 4.2
++EXTRA_CFLAGS += -DRTW_ENABLE_WIFI_CONTROL_FUNC
++EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
++EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
++EXTRA_CFLAGS += -DCONFIG_P2P_IPS
++ARCH := arm
++CROSS_COMPILE := /home/android_sdk/nvidia/tegra-17r9-partner-android-4.2-dalmore_20130131/prebuilts/gcc/linux-x86/arm/arm-eabi-4.6/bin/arm-eabi-
++KSRC := /home/android_sdk/nvidia/tegra-17r9-partner-android-4.2-dalmore_20130131/out/target/product/dalmore/obj/KERNEL
++MODULE_NAME := wlan
++endif
++
++ifeq ($(CONFIG_PLATFORM_ARM_TCC8900), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
++ARCH := arm
++CROSS_COMPILE := /home/android_sdk/Telechips/SDK_2304_20110613/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/bin/arm-eabi-
++KSRC := /home/android_sdk/Telechips/SDK_2304_20110613/kernel
++MODULE_NAME := wlan
++endif
++
++ifeq ($(CONFIG_PLATFORM_ARM_TCC8920), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
++ARCH := arm
++CROSS_COMPILE := /home/android_sdk/Telechips/v12.06_r1-tcc-android-4.0.4/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/bin/arm-eabi-
++KSRC := /home/android_sdk/Telechips/v12.06_r1-tcc-android-4.0.4/kernel
++MODULE_NAME := wlan
++endif
++
++ifeq ($(CONFIG_PLATFORM_ARM_TCC8920_JB42), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
++# default setting for Android 4.1, 4.2
++EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
++EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
++EXTRA_CFLAGS += -DCONFIG_P2P_IPS
++ARCH := arm
++CROSS_COMPILE := /home/android_sdk/Telechips/v13.03_r1-tcc-android-4.2.2_ds_patched/prebuilts/gcc/linux-x86/arm/arm-eabi-4.6/bin/arm-eabi-
++KSRC := /home/android_sdk/Telechips/v13.03_r1-tcc-android-4.2.2_ds_patched/kernel
++MODULE_NAME := wlan
++endif
++
++ifeq ($(CONFIG_PLATFORM_ARM_RK2818), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ANDROID -DCONFIG_PLATFORM_ROCKCHIPS -DCONFIG_MINIMAL_MEMORY_USAGE
++ARCH := arm
++CROSS_COMPILE := /usr/src/release_fae_version/toolchain/arm-eabi-4.4.0/bin/arm-eabi-
++KSRC := /usr/src/release_fae_version/kernel25_A7_281x
++MODULE_NAME := wlan
++endif
++
++ifeq ($(CONFIG_PLATFORM_ARM_TI_PANDA), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN #-DCONFIG_MINIMAL_MEMORY_USAGE
++ARCH := arm
++#CROSS_COMPILE := /media/DATA-1/aosp/ics-aosp_20111227/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/bin/arm-eabi-
++#KSRC := /media/DATA-1/aosp/android-omap-panda-3.0_20120104
++CROSS_COMPILE := /media/DATA-1/android-4.0/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/bin/arm-eabi-
++KSRC := /media/DATA-1/android-4.0/panda_kernel/omap
++MODULE_NAME := wlan
++endif
++
++ifeq ($(CONFIG_PLATFORM_MIPS_JZ4760), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_MINIMAL_MEMORY_USAGE
++ARCH ?= mips
++CROSS_COMPILE ?= /mnt/sdb5/Ingenic/Umido/mips-4.3/bin/mips-linux-gnu-
++KSRC ?= /mnt/sdb5/Ingenic/Umido/kernel
++endif
++
++#Add setting for MN10300
++ifeq ($(CONFIG_PLATFORM_MN10300), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_MN10300
++ARCH := mn10300
++CROSS_COMPILE := mn10300-linux-
++KVER := 2.6.32.2
++KSRC := /home/winuser/work/Plat_sLD2T_V3010/usr/src/linux-2.6.32.2
++INSTALL_PREFIX :=
++endif
++
++ifeq ($(CONFIG_PLATFORM_ARM_SUNxI), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ARM_SUNxI
++ARCH := arm
++CROSS_COMPILE := arm-none-linux-gnueabi-
++KVER := 3.0.8
++#KSRC:= ../lichee/linux-3.0/
++endif
++
++ifeq ($(CONFIG_PLATFORM_ARM_SUN6I), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
++EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUN6I
++EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX
++EXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT
++# default setting for Android 4.1, 4.2
++EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
++EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
++EXTRA_CFLAGS += -DCONFIG_P2P_IPS
++ARCH := arm
++CROSS_COMPILE := arm-none-linux-gnueabi-
++KVER := 3.3.0
++#KSRC:= ../lichee/linux-3.3/
++endif
++
++ifneq ($(USER_MODULE_NAME),)
++MODULE_NAME := $(USER_MODULE_NAME)
++endif
++
++ifeq ($(CONFIG_MP_INCLUDED), y)
++MODULE_NAME := $(MODULE_NAME)_mp
++EXTRA_CFLAGS += -DCONFIG_MP_INCLUDED
++endif
++
++
++ifneq ($(KERNELRELEASE),)
++
++
++rtk_core := core/rtw_cmd.o \
++ core/rtw_security.o \
++ core/rtw_debug.o \
++ core/rtw_io.o \
++ core/rtw_ioctl_query.o \
++ core/rtw_ioctl_set.o \
++ core/rtw_ieee80211.o \
++ core/rtw_mlme.o \
++ core/rtw_mlme_ext.o \
++ core/rtw_wlan_util.o \
++ core/rtw_pwrctrl.o \
++ core/rtw_rf.o \
++ core/rtw_recv.o \
++ core/rtw_sta_mgt.o \
++ core/rtw_ap.o \
++ core/rtw_xmit.o \
++ core/rtw_p2p.o \
++ core/rtw_tdls.o \
++ core/rtw_br_ext.o \
++ core/rtw_iol.o \
++ core/rtw_sreset.o
++
++$(MODULE_NAME)-y += $(rtk_core)
++
++$(MODULE_NAME)-$(CONFIG_INTEL_WIDI) += core/rtw_intel_widi.o
++
++$(MODULE_NAME)-y += core/efuse/rtw_efuse.o
++
++$(MODULE_NAME)-y += $(_HAL_INTFS_FILES)
++
++$(MODULE_NAME)-y += $(_OS_INTFS_FILES)
++
++$(MODULE_NAME)-$(CONFIG_MP_INCLUDED) += core/rtw_mp.o \
++ core/rtw_mp_ioctl.o
++
++obj-$(CONFIG_RTL8192CU) := $(MODULE_NAME).o
++
++else
++
++export CONFIG_RTL8192CU = m
++
++all: modules
++
++modules:
++ $(MAKE) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) -C $(KSRC) M=$(shell pwd) modules
++
++strip:
++ $(CROSS_COMPILE)strip $(MODULE_NAME).ko --strip-unneeded
++
++install:
++ install -p -m 644 $(MODULE_NAME).ko $(MODDESTDIR)
++ /sbin/depmod -a ${KVER}
++
++uninstall:
++ rm -f $(MODDESTDIR)/$(MODULE_NAME).ko
++ /sbin/depmod -a ${KVER}
++
++
++config_r:
++ @echo "make config"
++ /bin/bash script/Configure script/config.in
++
++.PHONY: modules clean
++
++clean:
++ rm -fr *.mod.c *.mod *.o .*.cmd *.ko *~
++ rm .tmp_versions -fr ; rm Module.symvers -fr
++ rm -fr Module.markers ; rm -fr modules.order
++ cd core/efuse ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko
++ cd core ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko
++ cd hal/$(RTL871X)/$(HCI_NAME) ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko
++ cd hal/$(RTL871X) ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko
++ cd hal ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko
++ cd os_dep/linux ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko
++ cd os_dep ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko
++endif
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/os_dep/linux/ioctl_cfg80211.c linux-xbian-rpi/drivers/net/wireless/rtl8192cu/os_dep/linux/ioctl_cfg80211.c
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/os_dep/linux/ioctl_cfg80211.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/os_dep/linux/ioctl_cfg80211.c 2015-07-28 01:20:58.429213356 +0200
+@@ -0,0 +1,5488 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#define _IOCTL_CFG80211_C_
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++#include <rtw_ioctl.h>
++#include <rtw_ioctl_set.h>
++#include <rtw_ioctl_query.h>
++#include <xmit_osdep.h>
++
++#ifdef CONFIG_IOCTL_CFG80211
++
++#include "ioctl_cfg80211.h"
++
++#define RTW_MAX_MGMT_TX_CNT (8)
++
++#define RTW_SCAN_IE_LEN_MAX 2304
++#define RTW_MAX_REMAIN_ON_CHANNEL_DURATION 65535 //ms
++#define RTW_MAX_NUM_PMKIDS 4
++
++#define RTW_CH_MAX_2G_CHANNEL 14 /* Max channel in 2G band */
++
++static const u32 rtw_cipher_suites[] = {
++ WLAN_CIPHER_SUITE_WEP40,
++ WLAN_CIPHER_SUITE_WEP104,
++ WLAN_CIPHER_SUITE_TKIP,
++ WLAN_CIPHER_SUITE_CCMP,
++#ifdef CONFIG_IEEE80211W
++ WLAN_CIPHER_SUITE_AES_CMAC,
++#endif //CONFIG_IEEE80211W
++};
++
++#define RATETAB_ENT(_rate, _rateid, _flags) \
++ { \
++ .bitrate = (_rate), \
++ .hw_value = (_rateid), \
++ .flags = (_flags), \
++ }
++
++#define CHAN2G(_channel, _freq, _flags) { \
++ .band = IEEE80211_BAND_2GHZ, \
++ .center_freq = (_freq), \
++ .hw_value = (_channel), \
++ .flags = (_flags), \
++ .max_antenna_gain = 0, \
++ .max_power = 30, \
++}
++
++#define CHAN5G(_channel, _flags) { \
++ .band = IEEE80211_BAND_5GHZ, \
++ .center_freq = 5000 + (5 * (_channel)), \
++ .hw_value = (_channel), \
++ .flags = (_flags), \
++ .max_antenna_gain = 0, \
++ .max_power = 30, \
++}
++
++static struct ieee80211_rate rtw_rates[] = {
++ RATETAB_ENT(10, 0x1, 0),
++ RATETAB_ENT(20, 0x2, 0),
++ RATETAB_ENT(55, 0x4, 0),
++ RATETAB_ENT(110, 0x8, 0),
++ RATETAB_ENT(60, 0x10, 0),
++ RATETAB_ENT(90, 0x20, 0),
++ RATETAB_ENT(120, 0x40, 0),
++ RATETAB_ENT(180, 0x80, 0),
++ RATETAB_ENT(240, 0x100, 0),
++ RATETAB_ENT(360, 0x200, 0),
++ RATETAB_ENT(480, 0x400, 0),
++ RATETAB_ENT(540, 0x800, 0),
++};
++
++#define rtw_a_rates (rtw_rates + 4)
++#define RTW_A_RATES_NUM 8
++#define rtw_g_rates (rtw_rates + 0)
++#define RTW_G_RATES_NUM 12
++
++#define RTW_2G_CHANNELS_NUM 14
++#define RTW_5G_CHANNELS_NUM 37
++
++static struct ieee80211_channel rtw_2ghz_channels[] = {
++ CHAN2G(1, 2412, 0),
++ CHAN2G(2, 2417, 0),
++ CHAN2G(3, 2422, 0),
++ CHAN2G(4, 2427, 0),
++ CHAN2G(5, 2432, 0),
++ CHAN2G(6, 2437, 0),
++ CHAN2G(7, 2442, 0),
++ CHAN2G(8, 2447, 0),
++ CHAN2G(9, 2452, 0),
++ CHAN2G(10, 2457, 0),
++ CHAN2G(11, 2462, 0),
++ CHAN2G(12, 2467, 0),
++ CHAN2G(13, 2472, 0),
++ CHAN2G(14, 2484, 0),
++};
++
++static struct ieee80211_channel rtw_5ghz_a_channels[] = {
++ CHAN5G(34, 0), CHAN5G(36, 0),
++ CHAN5G(38, 0), CHAN5G(40, 0),
++ CHAN5G(42, 0), CHAN5G(44, 0),
++ CHAN5G(46, 0), CHAN5G(48, 0),
++ CHAN5G(52, 0), CHAN5G(56, 0),
++ CHAN5G(60, 0), CHAN5G(64, 0),
++ CHAN5G(100, 0), CHAN5G(104, 0),
++ CHAN5G(108, 0), CHAN5G(112, 0),
++ CHAN5G(116, 0), CHAN5G(120, 0),
++ CHAN5G(124, 0), CHAN5G(128, 0),
++ CHAN5G(132, 0), CHAN5G(136, 0),
++ CHAN5G(140, 0), CHAN5G(149, 0),
++ CHAN5G(153, 0), CHAN5G(157, 0),
++ CHAN5G(161, 0), CHAN5G(165, 0),
++ CHAN5G(184, 0), CHAN5G(188, 0),
++ CHAN5G(192, 0), CHAN5G(196, 0),
++ CHAN5G(200, 0), CHAN5G(204, 0),
++ CHAN5G(208, 0), CHAN5G(212, 0),
++ CHAN5G(216, 0),
++};
++
++
++void rtw_2g_channels_init(struct ieee80211_channel *channels)
++{
++ _rtw_memcpy((void*)channels, (void*)rtw_2ghz_channels,
++ sizeof(struct ieee80211_channel)*RTW_2G_CHANNELS_NUM
++ );
++}
++
++void rtw_5g_channels_init(struct ieee80211_channel *channels)
++{
++ _rtw_memcpy((void*)channels, (void*)rtw_5ghz_a_channels,
++ sizeof(struct ieee80211_channel)*RTW_5G_CHANNELS_NUM
++ );
++}
++
++void rtw_2g_rates_init(struct ieee80211_rate *rates)
++{
++ _rtw_memcpy(rates, rtw_g_rates,
++ sizeof(struct ieee80211_rate)*RTW_G_RATES_NUM
++ );
++}
++
++void rtw_5g_rates_init(struct ieee80211_rate *rates)
++{
++ _rtw_memcpy(rates, rtw_a_rates,
++ sizeof(struct ieee80211_rate)*RTW_A_RATES_NUM
++ );
++}
++
++struct ieee80211_supported_band *rtw_spt_band_alloc(
++ enum ieee80211_band band
++ )
++{
++ struct ieee80211_supported_band *spt_band = NULL;
++ int n_channels, n_bitrates;
++
++ if(band == IEEE80211_BAND_2GHZ)
++ {
++ n_channels = RTW_2G_CHANNELS_NUM;
++ n_bitrates = RTW_G_RATES_NUM;
++ }
++ else if(band == IEEE80211_BAND_5GHZ)
++ {
++ n_channels = RTW_5G_CHANNELS_NUM;
++ n_bitrates = RTW_A_RATES_NUM;
++ }
++ else
++ {
++ goto exit;
++ }
++
++ spt_band = (struct ieee80211_supported_band *)rtw_zmalloc(
++ sizeof(struct ieee80211_supported_band)
++ + sizeof(struct ieee80211_channel)*n_channels
++ + sizeof(struct ieee80211_rate)*n_bitrates
++ );
++ if(!spt_band)
++ goto exit;
++
++ spt_band->channels = (struct ieee80211_channel*)(((u8*)spt_band)+sizeof(struct ieee80211_supported_band));
++ spt_band->bitrates= (struct ieee80211_rate*)(((u8*)spt_band->channels)+sizeof(struct ieee80211_channel)*n_channels);
++ spt_band->band = band;
++ spt_band->n_channels = n_channels;
++ spt_band->n_bitrates = n_bitrates;
++
++ if(band == IEEE80211_BAND_2GHZ)
++ {
++ rtw_2g_channels_init(spt_band->channels);
++ rtw_2g_rates_init(spt_band->bitrates);
++ }
++ else if(band == IEEE80211_BAND_5GHZ)
++ {
++ rtw_5g_channels_init(spt_band->channels);
++ rtw_5g_rates_init(spt_band->bitrates);
++ }
++
++ //spt_band.ht_cap
++
++exit:
++
++ return spt_band;
++}
++
++void rtw_spt_band_free(struct ieee80211_supported_band *spt_band)
++{
++ u32 size;
++
++ if(!spt_band)
++ return;
++
++ if(spt_band->band == IEEE80211_BAND_2GHZ)
++ {
++ size = sizeof(struct ieee80211_supported_band)
++ + sizeof(struct ieee80211_channel)*RTW_2G_CHANNELS_NUM
++ + sizeof(struct ieee80211_rate)*RTW_G_RATES_NUM;
++ }
++ else if(spt_band->band == IEEE80211_BAND_5GHZ)
++ {
++ size = sizeof(struct ieee80211_supported_band)
++ + sizeof(struct ieee80211_channel)*RTW_5G_CHANNELS_NUM
++ + sizeof(struct ieee80211_rate)*RTW_A_RATES_NUM;
++ }
++ else
++ {
++
++ }
++ rtw_mfree((u8*)spt_band, size);
++}
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE)
++static const struct ieee80211_txrx_stypes
++rtw_cfg80211_default_mgmt_stypes[NUM_NL80211_IFTYPES] = {
++ [NL80211_IFTYPE_ADHOC] = {
++ .tx = 0xffff,
++ .rx = BIT(IEEE80211_STYPE_ACTION >> 4)
++ },
++ [NL80211_IFTYPE_STATION] = {
++ .tx = 0xffff,
++ .rx = BIT(IEEE80211_STYPE_ACTION >> 4) |
++ BIT(IEEE80211_STYPE_PROBE_REQ >> 4)
++ },
++ [NL80211_IFTYPE_AP] = {
++ .tx = 0xffff,
++ .rx = BIT(IEEE80211_STYPE_ASSOC_REQ >> 4) |
++ BIT(IEEE80211_STYPE_REASSOC_REQ >> 4) |
++ BIT(IEEE80211_STYPE_PROBE_REQ >> 4) |
++ BIT(IEEE80211_STYPE_DISASSOC >> 4) |
++ BIT(IEEE80211_STYPE_AUTH >> 4) |
++ BIT(IEEE80211_STYPE_DEAUTH >> 4) |
++ BIT(IEEE80211_STYPE_ACTION >> 4)
++ },
++ [NL80211_IFTYPE_AP_VLAN] = {
++ /* copy AP */
++ .tx = 0xffff,
++ .rx = BIT(IEEE80211_STYPE_ASSOC_REQ >> 4) |
++ BIT(IEEE80211_STYPE_REASSOC_REQ >> 4) |
++ BIT(IEEE80211_STYPE_PROBE_REQ >> 4) |
++ BIT(IEEE80211_STYPE_DISASSOC >> 4) |
++ BIT(IEEE80211_STYPE_AUTH >> 4) |
++ BIT(IEEE80211_STYPE_DEAUTH >> 4) |
++ BIT(IEEE80211_STYPE_ACTION >> 4)
++ },
++ [NL80211_IFTYPE_P2P_CLIENT] = {
++ .tx = 0xffff,
++ .rx = BIT(IEEE80211_STYPE_ACTION >> 4) |
++ BIT(IEEE80211_STYPE_PROBE_REQ >> 4)
++ },
++ [NL80211_IFTYPE_P2P_GO] = {
++ .tx = 0xffff,
++ .rx = BIT(IEEE80211_STYPE_ASSOC_REQ >> 4) |
++ BIT(IEEE80211_STYPE_REASSOC_REQ >> 4) |
++ BIT(IEEE80211_STYPE_PROBE_REQ >> 4) |
++ BIT(IEEE80211_STYPE_DISASSOC >> 4) |
++ BIT(IEEE80211_STYPE_AUTH >> 4) |
++ BIT(IEEE80211_STYPE_DEAUTH >> 4) |
++ BIT(IEEE80211_STYPE_ACTION >> 4)
++ },
++};
++#endif
++
++static int rtw_ieee80211_channel_to_frequency(int chan, int band)
++{
++ /* see 802.11 17.3.8.3.2 and Annex J
++ * there are overlapping channel numbers in 5GHz and 2GHz bands */
++
++ if (band == IEEE80211_BAND_5GHZ) {
++ if (chan >= 182 && chan <= 196)
++ return 4000 + chan * 5;
++ else
++ return 5000 + chan * 5;
++ } else { /* IEEE80211_BAND_2GHZ */
++ if (chan == 14)
++ return 2484;
++ else if (chan < 14)
++ return 2407 + chan * 5;
++ else
++ return 0; /* not supported */
++ }
++}
++
++#define MAX_BSSINFO_LEN 1000
++static int rtw_cfg80211_inform_bss(_adapter *padapter, struct wlan_network *pnetwork)
++{
++ int ret=0;
++ struct ieee80211_channel *notify_channel;
++ struct cfg80211_bss *bss;
++ //struct ieee80211_supported_band *band;
++ u16 channel;
++ u32 freq;
++ u64 notify_timestamp;
++ u16 notify_capability;
++ u16 notify_interval;
++ u8 *notify_ie;
++ size_t notify_ielen;
++ s32 notify_signal;
++ u8 buf[MAX_BSSINFO_LEN], *pbuf;
++ size_t len,bssinf_len=0;
++ struct rtw_ieee80211_hdr *pwlanhdr;
++ unsigned short *fctrl;
++ u8 bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
++
++ struct wireless_dev *wdev = padapter->rtw_wdev;
++ struct wiphy *wiphy = wdev->wiphy;
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++
++
++ //DBG_8192C("%s\n", __func__);
++
++ bssinf_len = pnetwork->network.IELength+sizeof (struct rtw_ieee80211_hdr_3addr);
++ if(bssinf_len > MAX_BSSINFO_LEN){
++ DBG_871X("%s IE Length too long > %d byte \n",__FUNCTION__,MAX_BSSINFO_LEN);
++ goto exit;
++ }
++
++ //To reduce PBC Overlap rate
++ //_enter_critical_bh(&pwdev_priv->scan_req_lock, &irqL);
++ if(wdev_to_priv(wdev)->scan_request != NULL)
++ {
++ u8 *psr=NULL, sr = 0;
++ NDIS_802_11_SSID *pssid = &pnetwork->network.Ssid;
++ struct cfg80211_scan_request *request = wdev_to_priv(wdev)->scan_request;
++ struct cfg80211_ssid *ssids = request->ssids;
++ u32 wpsielen=0;
++ u8 *wpsie=NULL;
++
++ wpsie = rtw_get_wps_ie(pnetwork->network.IEs+_FIXED_IE_LENGTH_, pnetwork->network.IELength-_FIXED_IE_LENGTH_, NULL, &wpsielen);
++
++ if(wpsie && wpsielen>0)
++ psr = rtw_get_wps_attr_content(wpsie, wpsielen, WPS_ATTR_SELECTED_REGISTRAR, (u8*)(&sr), NULL);
++
++ if (sr != 0)
++ {
++ if(request->n_ssids == 1 && request->n_channels == 1) // it means under processing WPS
++ {
++ DBG_8192C("ssid=%s, len=%d\n", pssid->Ssid, pssid->SsidLength);
++
++ if(pssid->SsidLength == ssids[0].ssid_len &&
++ _rtw_memcmp(pssid->Ssid, ssids[0].ssid, ssids[0].ssid_len))
++ {
++ DBG_871X("%s, got sr and ssid match!\n", __func__);
++ }
++ else
++ {
++ if(psr !=NULL)
++ *psr = 0; //clear sr
++
++#if 0
++ WLAN_BSSID_EX *pselect_network = &pnetwork->network;
++ struct cfg80211_bss *pselect_bss = NULL;
++ struct ieee80211_channel *notify_channel = NULL;
++ u32 freq;
++
++ DBG_871X("%s, got sr, but ssid mismatch, to remove this bss\n", __func__);
++
++ if (pselect_network->Configuration.DSConfig <= RTW_CH_MAX_2G_CHANNEL)
++ freq = rtw_ieee80211_channel_to_frequency(pselect_network->Configuration.DSConfig, IEEE80211_BAND_2GHZ);
++ else
++ freq = rtw_ieee80211_channel_to_frequency(pselect_network->Configuration.DSConfig, IEEE80211_BAND_5GHZ);
++
++ notify_channel = ieee80211_get_channel(wiphy, freq);
++ pselect_bss = cfg80211_get_bss(wiphy, NULL/*notify_channel*/,
++ pselect_network->MacAddress, pselect_network->Ssid.Ssid,
++ pselect_network->Ssid.SsidLength, 0/*WLAN_CAPABILITY_ESS*/,
++ 0/*WLAN_CAPABILITY_ESS*/);
++
++ if(pselect_bss)
++ {
++ DBG_871X("%s, got bss for cfg80211 for unlinking bss\n", __func__);
++
++ cfg80211_unlink_bss(wiphy, pselect_bss);
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0)
++ cfg80211_put_bss(wiphy, pselect_bss);
++#else
++ cfg80211_put_bss(pselect_bss);
++#endif
++
++ }
++
++ goto exit;
++#endif
++ }
++ }
++ }
++ }
++ //_exit_critical_bh(&pwdev_priv->scan_req_lock, &irqL);
++
++ channel = pnetwork->network.Configuration.DSConfig;
++ if (channel <= RTW_CH_MAX_2G_CHANNEL)
++ freq = rtw_ieee80211_channel_to_frequency(channel, IEEE80211_BAND_2GHZ);
++ else
++ freq = rtw_ieee80211_channel_to_frequency(channel, IEEE80211_BAND_5GHZ);
++
++ notify_channel = ieee80211_get_channel(wiphy, freq);
++
++ //rtw_get_timestampe_from_ie()
++ notify_timestamp = jiffies_to_msecs(jiffies)*1000; /* uSec */
++
++ notify_interval = le16_to_cpu(*(u16*)rtw_get_beacon_interval_from_ie(pnetwork->network.IEs));
++ notify_capability = le16_to_cpu(*(u16*)rtw_get_capability_from_ie(pnetwork->network.IEs));
++
++
++ notify_ie = pnetwork->network.IEs+_FIXED_IE_LENGTH_;
++ notify_ielen = pnetwork->network.IELength-_FIXED_IE_LENGTH_;
++
++ //We've set wiphy's signal_type as CFG80211_SIGNAL_TYPE_MBM: signal strength in mBm (100*dBm)
++ if ( check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE &&
++ is_same_network(&pmlmepriv->cur_network.network, &pnetwork->network)) {
++ notify_signal = 100*translate_percentage_to_dbm(padapter->recvpriv.signal_strength);//dbm
++ } else {
++ notify_signal = 100*translate_percentage_to_dbm(pnetwork->network.PhyInfo.SignalStrength);//dbm
++ }
++
++/*
++ DBG_8192C("bssid: %2.2X:%2.2X:%2.2X:%2.2X:%2.2X:%2.2X\n",
++ pnetwork->network.MacAddress[0], pnetwork->network.MacAddress[1], pnetwork->network.MacAddress[2],
++ pnetwork->network.MacAddress[3], pnetwork->network.MacAddress[4], pnetwork->network.MacAddress[5]);
++ DBG_8192C("Channel: %d(%d)\n", channel, freq);
++ DBG_8192C("Capability: %X\n", notify_capability);
++ DBG_8192C("Beacon interval: %d\n", notify_interval);
++ DBG_8192C("Signal: %d\n", notify_signal);
++ DBG_8192C("notify_timestamp: %#018llx\n", notify_timestamp);
++*/
++
++ pbuf = buf;
++
++ pwlanhdr = (struct rtw_ieee80211_hdr *)pbuf;
++ fctrl = &(pwlanhdr->frame_ctl);
++ *(fctrl) = 0;
++
++ SetSeqNum(pwlanhdr, 0/*pmlmeext->mgnt_seq*/);
++ //pmlmeext->mgnt_seq++;
++
++ if (pnetwork->network.Reserved[0] == 1) { // WIFI_BEACON
++ _rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN);
++ SetFrameSubType(pbuf, WIFI_BEACON);
++ } else {
++ _rtw_memcpy(pwlanhdr->addr1, myid(&(padapter->eeprompriv)), ETH_ALEN);
++ SetFrameSubType(pbuf, WIFI_PROBERSP);
++ }
++
++ _rtw_memcpy(pwlanhdr->addr2, pnetwork->network.MacAddress, ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr3, pnetwork->network.MacAddress, ETH_ALEN);
++
++
++ pbuf += sizeof(struct rtw_ieee80211_hdr_3addr);
++ len = sizeof (struct rtw_ieee80211_hdr_3addr);
++
++ _rtw_memcpy(pbuf, pnetwork->network.IEs, pnetwork->network.IELength);
++ len += pnetwork->network.IELength;
++
++ //#ifdef CONFIG_P2P
++ //if(rtw_get_p2p_ie(pnetwork->network.IEs+12, pnetwork->network.IELength-12, NULL, NULL))
++ //{
++ // DBG_8192C("%s, got p2p_ie\n", __func__);
++ //}
++ //#endif
++
++
++#if 1
++ bss = cfg80211_inform_bss_frame(wiphy, notify_channel, (struct ieee80211_mgmt *)buf,
++ len, notify_signal, GFP_ATOMIC);
++#else
++
++ bss = cfg80211_inform_bss(wiphy, notify_channel, (const u8 *)pnetwork->network.MacAddress,
++ notify_timestamp, notify_capability, notify_interval, notify_ie,
++ notify_ielen, notify_signal, GFP_ATOMIC/*GFP_KERNEL*/);
++#endif
++
++ if (unlikely(!bss)) {
++ DBG_8192C("rtw_cfg80211_inform_bss error\n");
++ return -EINVAL;
++ }
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38))
++#ifndef COMPAT_KERNEL_RELEASE
++ //patch for cfg80211, update beacon ies to information_elements
++ if (pnetwork->network.Reserved[0] == 1) { // WIFI_BEACON
++
++ if(bss->len_information_elements != bss->len_beacon_ies)
++ {
++ bss->information_elements = bss->beacon_ies;
++ bss->len_information_elements = bss->len_beacon_ies;
++ }
++ }
++#endif //COMPAT_KERNEL_RELEASE
++#endif //LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38)
++
++/*
++ {
++ if( bss->information_elements == bss->proberesp_ies)
++ {
++ if( bss->len_information_elements != bss->len_proberesp_ies)
++ {
++ DBG_8192C("error!, len_information_elements != bss->len_proberesp_ies\n");
++ }
++
++ }
++ else if(bss->len_information_elements < bss->len_beacon_ies)
++ {
++ bss->information_elements = bss->beacon_ies;
++ bss->len_information_elements = bss->len_beacon_ies;
++ }
++ }
++*/
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0)
++ cfg80211_put_bss(wiphy, bss);
++#else
++ cfg80211_put_bss(bss);
++#endif
++
++exit:
++ return ret;
++
++}
++
++/*
++ Check the given bss is valid by kernel API cfg80211_get_bss()
++ @padapter : the given adapter
++
++ return _TRUE if bss is valid, _FALSE for not found.
++*/
++int rtw_cfg80211_check_bss(_adapter *padapter)
++{
++ WLAN_BSSID_EX *pnetwork = &(padapter->mlmeextpriv.mlmext_info.network);
++ struct cfg80211_bss *bss = NULL;
++ struct ieee80211_channel *notify_channel = NULL;
++ u32 freq;
++
++ if (!(pnetwork) || !(padapter->rtw_wdev))
++ return _FALSE;
++
++ if (pnetwork->Configuration.DSConfig <= RTW_CH_MAX_2G_CHANNEL)
++ freq = rtw_ieee80211_channel_to_frequency(pnetwork->Configuration.DSConfig, IEEE80211_BAND_2GHZ);
++ else
++ freq = rtw_ieee80211_channel_to_frequency(pnetwork->Configuration.DSConfig, IEEE80211_BAND_5GHZ);
++
++ notify_channel = ieee80211_get_channel(padapter->rtw_wdev->wiphy, freq);
++ bss = cfg80211_get_bss(padapter->rtw_wdev->wiphy, notify_channel,
++ pnetwork->MacAddress, pnetwork->Ssid.Ssid,
++ pnetwork->Ssid.SsidLength,
++ WLAN_CAPABILITY_ESS, WLAN_CAPABILITY_ESS);
++
++ return (bss!=NULL);
++}
++
++void rtw_cfg80211_indicate_connect(_adapter *padapter)
++{
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct wlan_network *cur_network = &(pmlmepriv->cur_network);
++ struct wireless_dev *pwdev = padapter->rtw_wdev;
++#ifdef CONFIG_P2P
++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo);
++#endif
++ struct cfg80211_bss *bss = NULL;
++
++ DBG_871X(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
++ if (pwdev->iftype != NL80211_IFTYPE_STATION
++ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE)
++ && pwdev->iftype != NL80211_IFTYPE_P2P_CLIENT
++ #endif
++ ) {
++ return;
++ }
++
++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE)
++ return;
++
++#ifdef CONFIG_P2P
++ if(pwdinfo->driver_interface == DRIVER_CFG80211 )
++ {
++ if(!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
++ {
++ rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo));
++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT);
++ rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK);
++ DBG_8192C("%s, role=%d, p2p_state=%d, pre_p2p_state=%d\n", __func__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo), rtw_p2p_pre_state(pwdinfo));
++ }
++ }
++#endif //CONFIG_P2P
++
++ #ifdef CONFIG_LAYER2_ROAMING
++ if (rtw_to_roaming(padapter) > 0) {
++ #if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 39) || defined(COMPAT_KERNEL_RELEASE)
++ struct wiphy *wiphy = pwdev->wiphy;
++ struct ieee80211_channel *notify_channel;
++ u32 freq;
++ u16 channel = cur_network->network.Configuration.DSConfig;
++
++ if (channel <= RTW_CH_MAX_2G_CHANNEL)
++ freq = rtw_ieee80211_channel_to_frequency(channel, IEEE80211_BAND_2GHZ);
++ else
++ freq = rtw_ieee80211_channel_to_frequency(channel, IEEE80211_BAND_5GHZ);
++
++ notify_channel = ieee80211_get_channel(wiphy, freq);
++ #endif
++
++ DBG_871X("%s call cfg80211_roamed\n", __FUNCTION__);
++ cfg80211_roamed(padapter->pnetdev
++ #if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 39) || defined(COMPAT_KERNEL_RELEASE)
++ , notify_channel
++ #endif
++ , cur_network->network.MacAddress
++ , pmlmepriv->assoc_req+sizeof(struct rtw_ieee80211_hdr_3addr)+2
++ , pmlmepriv->assoc_req_len-sizeof(struct rtw_ieee80211_hdr_3addr)-2
++ , pmlmepriv->assoc_rsp+sizeof(struct rtw_ieee80211_hdr_3addr)+6
++ , pmlmepriv->assoc_rsp_len-sizeof(struct rtw_ieee80211_hdr_3addr)-6
++ , GFP_ATOMIC);
++ }
++ else
++ #endif
++ {
++ DBG_8192C("pwdev->sme_state(b)=%d\n", pwdev->sme_state);
++ cfg80211_connect_result(padapter->pnetdev, cur_network->network.MacAddress
++ , pmlmepriv->assoc_req+sizeof(struct rtw_ieee80211_hdr_3addr)+2
++ , pmlmepriv->assoc_req_len-sizeof(struct rtw_ieee80211_hdr_3addr)-2
++ , pmlmepriv->assoc_rsp+sizeof(struct rtw_ieee80211_hdr_3addr)+6
++ , pmlmepriv->assoc_rsp_len-sizeof(struct rtw_ieee80211_hdr_3addr)-6
++ , WLAN_STATUS_SUCCESS, GFP_ATOMIC);
++ DBG_8192C("pwdev->sme_state(a)=%d\n", pwdev->sme_state);
++ }
++}
++
++void rtw_cfg80211_indicate_disconnect(_adapter *padapter)
++{
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct wireless_dev *pwdev = padapter->rtw_wdev;
++#ifdef CONFIG_P2P
++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo);
++#endif
++
++ DBG_871X(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
++
++ if (pwdev->iftype != NL80211_IFTYPE_STATION
++ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE)
++ && pwdev->iftype != NL80211_IFTYPE_P2P_CLIENT
++ #endif
++ ) {
++ return;
++ }
++
++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE)
++ return;
++
++#ifdef CONFIG_P2P
++ if( pwdinfo->driver_interface == DRIVER_CFG80211 )
++ {
++ if(!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
++ {
++ _cancel_timer_ex( &pwdinfo->find_phase_timer );
++ _cancel_timer_ex( &pwdinfo->restore_p2p_state_timer );
++ _cancel_timer_ex( &pwdinfo->pre_tx_scan_timer);
++
++ rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo));
++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE);
++
++ DBG_8192C("%s, role=%d, p2p_state=%d, pre_p2p_state=%d\n", __func__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo), rtw_p2p_pre_state(pwdinfo));
++ }
++ }
++#endif //CONFIG_P2P
++
++ if (!padapter->mlmepriv.not_indic_disco) {
++ DBG_8192C("pwdev->sme_state(b)=%d\n", pwdev->sme_state);
++
++ if(pwdev->sme_state==CFG80211_SME_CONNECTING)
++ cfg80211_connect_result(padapter->pnetdev, NULL, NULL, 0, NULL, 0,
++ WLAN_STATUS_UNSPECIFIED_FAILURE, GFP_ATOMIC/*GFP_KERNEL*/);
++ else if(pwdev->sme_state==CFG80211_SME_CONNECTED)
++ cfg80211_disconnected(padapter->pnetdev, 0, NULL, 0, GFP_ATOMIC);
++ //else
++ //DBG_8192C("pwdev->sme_state=%d\n", pwdev->sme_state);
++
++ DBG_8192C("pwdev->sme_state(a)=%d\n", pwdev->sme_state);
++ }
++}
++
++
++#ifdef CONFIG_AP_MODE
++static u8 set_pairwise_key(_adapter *padapter, struct sta_info *psta)
++{
++ struct cmd_obj* ph2c;
++ struct set_stakey_parm *psetstakey_para;
++ struct cmd_priv *pcmdpriv=&padapter->cmdpriv;
++ u8 res=_SUCCESS;
++
++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj));
++ if ( ph2c == NULL){
++ res= _FAIL;
++ goto exit;
++ }
++
++ psetstakey_para = (struct set_stakey_parm*)rtw_zmalloc(sizeof(struct set_stakey_parm));
++ if(psetstakey_para==NULL){
++ rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj));
++ res=_FAIL;
++ goto exit;
++ }
++
++ init_h2fwcmd_w_parm_no_rsp(ph2c, psetstakey_para, _SetStaKey_CMD_);
++
++
++ psetstakey_para->algorithm = (u8)psta->dot118021XPrivacy;
++
++ _rtw_memcpy(psetstakey_para->addr, psta->hwaddr, ETH_ALEN);
++
++ _rtw_memcpy(psetstakey_para->key, &psta->dot118021x_UncstKey, 16);
++
++
++ res = rtw_enqueue_cmd(pcmdpriv, ph2c);
++
++exit:
++
++ return res;
++
++}
++
++static int set_group_key(_adapter *padapter, u8 *key, u8 alg, int keyid)
++{
++ u8 keylen;
++ struct cmd_obj* pcmd;
++ struct setkey_parm *psetkeyparm;
++ struct cmd_priv *pcmdpriv=&(padapter->cmdpriv);
++ int res=_SUCCESS;
++
++ DBG_8192C("%s\n", __FUNCTION__);
++
++ pcmd = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj));
++ if(pcmd==NULL){
++ res= _FAIL;
++ goto exit;
++ }
++ psetkeyparm=(struct setkey_parm*)rtw_zmalloc(sizeof(struct setkey_parm));
++ if(psetkeyparm==NULL){
++ rtw_mfree((unsigned char *)pcmd, sizeof(struct cmd_obj));
++ res= _FAIL;
++ goto exit;
++ }
++
++ _rtw_memset(psetkeyparm, 0, sizeof(struct setkey_parm));
++
++ psetkeyparm->keyid=(u8)keyid;
++ if (is_wep_enc(alg))
++ padapter->securitypriv.key_mask |= BIT(psetkeyparm->keyid);
++
++ psetkeyparm->algorithm = alg;
++
++ psetkeyparm->set_tx = 1;
++
++ switch(alg)
++ {
++ case _WEP40_:
++ keylen = 5;
++ break;
++ case _WEP104_:
++ keylen = 13;
++ break;
++ case _TKIP_:
++ case _TKIP_WTMIC_:
++ case _AES_:
++ keylen = 16;
++ default:
++ keylen = 16;
++ }
++
++ _rtw_memcpy(&(psetkeyparm->key[0]), key, keylen);
++
++ pcmd->cmdcode = _SetKey_CMD_;
++ pcmd->parmbuf = (u8 *)psetkeyparm;
++ pcmd->cmdsz = (sizeof(struct setkey_parm));
++ pcmd->rsp = NULL;
++ pcmd->rspsz = 0;
++
++
++ _rtw_init_listhead(&pcmd->list);
++
++ res = rtw_enqueue_cmd(pcmdpriv, pcmd);
++
++exit:
++
++ return res;
++
++
++}
++
++static int set_wep_key(_adapter *padapter, u8 *key, u8 keylen, int keyid)
++{
++ u8 alg;
++
++ switch(keylen)
++ {
++ case 5:
++ alg =_WEP40_;
++ break;
++ case 13:
++ alg =_WEP104_;
++ break;
++ default:
++ alg =_NO_PRIVACY_;
++ }
++
++ return set_group_key(padapter, key, alg, keyid);
++
++}
++
++static int rtw_cfg80211_ap_set_encryption(struct net_device *dev, struct ieee_param *param, u32 param_len)
++{
++ int ret = 0;
++ u32 wep_key_idx, wep_key_len,wep_total_len;
++ struct sta_info *psta = NULL, *pbcmc_sta = NULL;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct security_priv* psecuritypriv=&(padapter->securitypriv);
++ struct sta_priv *pstapriv = &padapter->stapriv;
++
++ DBG_8192C("%s\n", __FUNCTION__);
++
++ param->u.crypt.err = 0;
++ param->u.crypt.alg[IEEE_CRYPT_ALG_NAME_LEN - 1] = '\0';
++
++ //sizeof(struct ieee_param) = 64 bytes;
++ //if (param_len != (u32) ((u8 *) param->u.crypt.key - (u8 *) param) + param->u.crypt.key_len)
++ if (param_len != sizeof(struct ieee_param) + param->u.crypt.key_len)
++ {
++ ret = -EINVAL;
++ goto exit;
++ }
++
++ if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff &&
++ param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff &&
++ param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff)
++ {
++ if (param->u.crypt.idx >= WEP_KEYS)
++ {
++ ret = -EINVAL;
++ goto exit;
++ }
++ }
++ else
++ {
++ psta = rtw_get_stainfo(pstapriv, param->sta_addr);
++ if(!psta)
++ {
++ //ret = -EINVAL;
++ DBG_8192C("rtw_set_encryption(), sta has already been removed or never been added\n");
++ goto exit;
++ }
++ }
++
++ if (strcmp(param->u.crypt.alg, "none") == 0 && (psta==NULL))
++ {
++ //todo:clear default encryption keys
++
++ DBG_8192C("clear default encryption keys, keyid=%d\n", param->u.crypt.idx);
++
++ goto exit;
++ }
++
++
++ if (strcmp(param->u.crypt.alg, "WEP") == 0 && (psta==NULL))
++ {
++ DBG_8192C("r871x_set_encryption, crypt.alg = WEP\n");
++
++ wep_key_idx = param->u.crypt.idx;
++ wep_key_len = param->u.crypt.key_len;
++
++ DBG_8192C("r871x_set_encryption, wep_key_idx=%d, len=%d\n", wep_key_idx, wep_key_len);
++
++ if((wep_key_idx >= WEP_KEYS) || (wep_key_len<=0))
++ {
++ ret = -EINVAL;
++ goto exit;
++ }
++
++ if (wep_key_len > 0)
++ {
++ wep_key_len = wep_key_len <= 5 ? 5 : 13;
++ }
++
++ if (psecuritypriv->bWepDefaultKeyIdxSet == 0)
++ {
++ //wep default key has not been set, so use this key index as default key.
++
++ psecuritypriv->ndisencryptstatus = Ndis802_11Encryption1Enabled;
++ psecuritypriv->dot11PrivacyAlgrthm=_WEP40_;
++ psecuritypriv->dot118021XGrpPrivacy=_WEP40_;
++
++ if(wep_key_len == 13)
++ {
++ psecuritypriv->dot11PrivacyAlgrthm=_WEP104_;
++ psecuritypriv->dot118021XGrpPrivacy=_WEP104_;
++ }
++
++ psecuritypriv->dot11PrivacyKeyIndex = wep_key_idx;
++ }
++
++ _rtw_memcpy(&(psecuritypriv->dot11DefKey[wep_key_idx].skey[0]), param->u.crypt.key, wep_key_len);
++
++ psecuritypriv->dot11DefKeylen[wep_key_idx] = wep_key_len;
++
++ set_wep_key(padapter, param->u.crypt.key, wep_key_len, wep_key_idx);
++
++ goto exit;
++
++ }
++
++
++ if(!psta && check_fwstate(pmlmepriv, WIFI_AP_STATE)) // //group key
++ {
++ if(param->u.crypt.set_tx == 0) //group key
++ {
++ if(strcmp(param->u.crypt.alg, "WEP") == 0)
++ {
++ DBG_8192C("%s, set group_key, WEP\n", __FUNCTION__);
++
++ _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len>16 ?16:param->u.crypt.key_len));
++
++ psecuritypriv->dot118021XGrpPrivacy = _WEP40_;
++ if(param->u.crypt.key_len==13)
++ {
++ psecuritypriv->dot118021XGrpPrivacy = _WEP104_;
++ }
++
++ }
++ else if(strcmp(param->u.crypt.alg, "TKIP") == 0)
++ {
++ DBG_8192C("%s, set group_key, TKIP\n", __FUNCTION__);
++
++ psecuritypriv->dot118021XGrpPrivacy = _TKIP_;
++
++ _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len>16 ?16:param->u.crypt.key_len));
++
++ //DEBUG_ERR("set key length :param->u.crypt.key_len=%d\n", param->u.crypt.key_len);
++ //set mic key
++ _rtw_memcpy(psecuritypriv->dot118021XGrptxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[16]), 8);
++ _rtw_memcpy(psecuritypriv->dot118021XGrprxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[24]), 8);
++
++ psecuritypriv->busetkipkey = _TRUE;
++
++ }
++ else if(strcmp(param->u.crypt.alg, "CCMP") == 0)
++ {
++ DBG_8192C("%s, set group_key, CCMP\n", __FUNCTION__);
++
++ psecuritypriv->dot118021XGrpPrivacy = _AES_;
++
++ _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len>16 ?16:param->u.crypt.key_len));
++ }
++ else
++ {
++ DBG_8192C("%s, set group_key, none\n", __FUNCTION__);
++
++ psecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_;
++ }
++
++ psecuritypriv->dot118021XGrpKeyid = param->u.crypt.idx;
++
++ psecuritypriv->binstallGrpkey = _TRUE;
++
++ psecuritypriv->dot11PrivacyAlgrthm = psecuritypriv->dot118021XGrpPrivacy;//!!!
++
++ set_group_key(padapter, param->u.crypt.key, psecuritypriv->dot118021XGrpPrivacy, param->u.crypt.idx);
++
++ pbcmc_sta=rtw_get_bcmc_stainfo(padapter);
++ if(pbcmc_sta)
++ {
++ pbcmc_sta->ieee8021x_blocked = _FALSE;
++ pbcmc_sta->dot118021XPrivacy= psecuritypriv->dot118021XGrpPrivacy;//rx will use bmc_sta's dot118021XPrivacy
++ }
++
++ }
++
++ goto exit;
++
++ }
++
++ if(psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X && psta) // psk/802_1x
++ {
++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE))
++ {
++ if(param->u.crypt.set_tx ==1) //pairwise key
++ {
++ _rtw_memcpy(psta->dot118021x_UncstKey.skey, param->u.crypt.key, (param->u.crypt.key_len>16 ?16:param->u.crypt.key_len));
++
++ if(strcmp(param->u.crypt.alg, "WEP") == 0)
++ {
++ DBG_8192C("%s, set pairwise key, WEP\n", __FUNCTION__);
++
++ psta->dot118021XPrivacy = _WEP40_;
++ if(param->u.crypt.key_len==13)
++ {
++ psta->dot118021XPrivacy = _WEP104_;
++ }
++ }
++ else if(strcmp(param->u.crypt.alg, "TKIP") == 0)
++ {
++ DBG_8192C("%s, set pairwise key, TKIP\n", __FUNCTION__);
++
++ psta->dot118021XPrivacy = _TKIP_;
++
++ //DEBUG_ERR("set key length :param->u.crypt.key_len=%d\n", param->u.crypt.key_len);
++ //set mic key
++ _rtw_memcpy(psta->dot11tkiptxmickey.skey, &(param->u.crypt.key[16]), 8);
++ _rtw_memcpy(psta->dot11tkiprxmickey.skey, &(param->u.crypt.key[24]), 8);
++
++ psecuritypriv->busetkipkey = _TRUE;
++
++ }
++ else if(strcmp(param->u.crypt.alg, "CCMP") == 0)
++ {
++
++ DBG_8192C("%s, set pairwise key, CCMP\n", __FUNCTION__);
++
++ psta->dot118021XPrivacy = _AES_;
++ }
++ else
++ {
++ DBG_8192C("%s, set pairwise key, none\n", __FUNCTION__);
++
++ psta->dot118021XPrivacy = _NO_PRIVACY_;
++ }
++
++ set_pairwise_key(padapter, psta);
++
++ psta->ieee8021x_blocked = _FALSE;
++
++ psta->bpairwise_key_installed = _TRUE;
++
++ }
++ else//group key???
++ {
++ if(strcmp(param->u.crypt.alg, "WEP") == 0)
++ {
++ _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len>16 ?16:param->u.crypt.key_len));
++
++ psecuritypriv->dot118021XGrpPrivacy = _WEP40_;
++ if(param->u.crypt.key_len==13)
++ {
++ psecuritypriv->dot118021XGrpPrivacy = _WEP104_;
++ }
++ }
++ else if(strcmp(param->u.crypt.alg, "TKIP") == 0)
++ {
++ psecuritypriv->dot118021XGrpPrivacy = _TKIP_;
++
++ _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len>16 ?16:param->u.crypt.key_len));
++
++ //DEBUG_ERR("set key length :param->u.crypt.key_len=%d\n", param->u.crypt.key_len);
++ //set mic key
++ _rtw_memcpy(psecuritypriv->dot118021XGrptxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[16]), 8);
++ _rtw_memcpy(psecuritypriv->dot118021XGrprxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[24]), 8);
++
++ psecuritypriv->busetkipkey = _TRUE;
++
++ }
++ else if(strcmp(param->u.crypt.alg, "CCMP") == 0)
++ {
++ psecuritypriv->dot118021XGrpPrivacy = _AES_;
++
++ _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len>16 ?16:param->u.crypt.key_len));
++ }
++ else
++ {
++ psecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_;
++ }
++
++ psecuritypriv->dot118021XGrpKeyid = param->u.crypt.idx;
++
++ psecuritypriv->binstallGrpkey = _TRUE;
++
++ psecuritypriv->dot11PrivacyAlgrthm = psecuritypriv->dot118021XGrpPrivacy;//!!!
++
++ set_group_key(padapter, param->u.crypt.key, psecuritypriv->dot118021XGrpPrivacy, param->u.crypt.idx);
++
++ pbcmc_sta=rtw_get_bcmc_stainfo(padapter);
++ if(pbcmc_sta)
++ {
++ pbcmc_sta->ieee8021x_blocked = _FALSE;
++ pbcmc_sta->dot118021XPrivacy= psecuritypriv->dot118021XGrpPrivacy;//rx will use bmc_sta's dot118021XPrivacy
++ }
++
++ }
++
++ }
++
++ }
++
++exit:
++
++ return ret;
++
++}
++#endif
++
++static int rtw_cfg80211_set_encryption(struct net_device *dev, struct ieee_param *param, u32 param_len)
++{
++ int ret = 0;
++ u32 wep_key_idx, wep_key_len,wep_total_len;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct security_priv *psecuritypriv = &padapter->securitypriv;
++#ifdef CONFIG_P2P
++ struct wifidirect_info* pwdinfo = &padapter->wdinfo;
++#endif //CONFIG_P2P
++
++_func_enter_;
++
++ DBG_8192C("%s\n", __func__);
++
++ param->u.crypt.err = 0;
++ param->u.crypt.alg[IEEE_CRYPT_ALG_NAME_LEN - 1] = '\0';
++
++ if (param_len < (u32) ((u8 *) param->u.crypt.key - (u8 *) param) + param->u.crypt.key_len)
++ {
++ ret = -EINVAL;
++ goto exit;
++ }
++
++ if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff &&
++ param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff &&
++ param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff)
++ {
++ if (param->u.crypt.idx >= WEP_KEYS
++#ifdef CONFIG_IEEE80211W
++ && param->u.crypt.idx > BIP_MAX_KEYID
++#endif //CONFIG_IEEE80211W
++ )
++ {
++ ret = -EINVAL;
++ goto exit;
++ }
++ } else {
++ ret = -EINVAL;
++ goto exit;
++ }
++
++ if (strcmp(param->u.crypt.alg, "WEP") == 0)
++ {
++ RT_TRACE(_module_rtl871x_ioctl_os_c,_drv_err_,("wpa_set_encryption, crypt.alg = WEP\n"));
++ DBG_8192C("wpa_set_encryption, crypt.alg = WEP\n");
++
++ wep_key_idx = param->u.crypt.idx;
++ wep_key_len = param->u.crypt.key_len;
++
++ if ((wep_key_idx > WEP_KEYS) || (wep_key_len <= 0))
++ {
++ ret = -EINVAL;
++ goto exit;
++ }
++
++ if (psecuritypriv->bWepDefaultKeyIdxSet == 0)
++ {
++ //wep default key has not been set, so use this key index as default key.
++
++ wep_key_len = wep_key_len <= 5 ? 5 : 13;
++
++ psecuritypriv->ndisencryptstatus = Ndis802_11Encryption1Enabled;
++ psecuritypriv->dot11PrivacyAlgrthm = _WEP40_;
++ psecuritypriv->dot118021XGrpPrivacy = _WEP40_;
++
++ if(wep_key_len==13)
++ {
++ psecuritypriv->dot11PrivacyAlgrthm = _WEP104_;
++ psecuritypriv->dot118021XGrpPrivacy = _WEP104_;
++ }
++
++ psecuritypriv->dot11PrivacyKeyIndex = wep_key_idx;
++ }
++
++ _rtw_memcpy(&(psecuritypriv->dot11DefKey[wep_key_idx].skey[0]), param->u.crypt.key, wep_key_len);
++
++ psecuritypriv->dot11DefKeylen[wep_key_idx] = wep_key_len;
++
++ rtw_set_key(padapter, psecuritypriv, wep_key_idx, 0);
++
++ goto exit;
++ }
++
++ if(padapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) // 802_1x
++ {
++ struct sta_info * psta,*pbcmc_sta;
++ struct sta_priv * pstapriv = &padapter->stapriv;
++
++ //DBG_8192C("%s, : dot11AuthAlgrthm == dot11AuthAlgrthm_8021X \n", __func__);
++
++ if (check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_MP_STATE) == _TRUE) //sta mode
++ {
++ psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));
++ if (psta == NULL) {
++ //DEBUG_ERR( ("Set wpa_set_encryption: Obtain Sta_info fail \n"));
++ DBG_8192C("%s, : Obtain Sta_info fail \n", __func__);
++ }
++ else
++ {
++ //Jeff: don't disable ieee8021x_blocked while clearing key
++ if (strcmp(param->u.crypt.alg, "none") != 0)
++ psta->ieee8021x_blocked = _FALSE;
++
++
++ if((padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption2Enabled)||
++ (padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption3Enabled))
++ {
++ psta->dot118021XPrivacy = padapter->securitypriv.dot11PrivacyAlgrthm;
++ }
++
++ if(param->u.crypt.set_tx ==1)//pairwise key
++ {
++
++ DBG_8192C("%s, : param->u.crypt.set_tx ==1 \n", __func__);
++
++ _rtw_memcpy(psta->dot118021x_UncstKey.skey, param->u.crypt.key, (param->u.crypt.key_len>16 ?16:param->u.crypt.key_len));
++
++ if(strcmp(param->u.crypt.alg, "TKIP") == 0)//set mic key
++ {
++ //DEBUG_ERR(("\nset key length :param->u.crypt.key_len=%d\n", param->u.crypt.key_len));
++ _rtw_memcpy(psta->dot11tkiptxmickey.skey, &(param->u.crypt.key[16]), 8);
++ _rtw_memcpy(psta->dot11tkiprxmickey.skey, &(param->u.crypt.key[24]), 8);
++
++ padapter->securitypriv.busetkipkey=_FALSE;
++ //_set_timer(&padapter->securitypriv.tkip_timer, 50);
++ }
++
++ //DEBUG_ERR((" param->u.crypt.key_len=%d\n",param->u.crypt.key_len));
++ DBG_871X(" ~~~~set sta key:unicastkey\n");
++
++ rtw_setstakey_cmd(padapter, (unsigned char *)psta, _TRUE);
++ }
++ else//group key
++ {
++ if(strcmp(param->u.crypt.alg, "TKIP") == 0 || strcmp(param->u.crypt.alg, "CCMP") == 0)
++ {
++ _rtw_memcpy(padapter->securitypriv.dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key,(param->u.crypt.key_len>16 ?16:param->u.crypt.key_len));
++ _rtw_memcpy(padapter->securitypriv.dot118021XGrptxmickey[param->u.crypt.idx].skey,&(param->u.crypt.key[16]),8);
++ _rtw_memcpy(padapter->securitypriv.dot118021XGrprxmickey[param->u.crypt.idx].skey,&(param->u.crypt.key[24]),8);
++ padapter->securitypriv.binstallGrpkey = _TRUE;
++ //DEBUG_ERR((" param->u.crypt.key_len=%d\n", param->u.crypt.key_len));
++ DBG_871X(" ~~~~set sta key:groupkey\n");
++
++ padapter->securitypriv.dot118021XGrpKeyid = param->u.crypt.idx;
++
++ rtw_set_key(padapter,&padapter->securitypriv,param->u.crypt.idx, 1);
++ }
++#ifdef CONFIG_IEEE80211W
++ else if(strcmp(param->u.crypt.alg, "BIP") == 0)
++ {
++ int no;
++ //DBG_871X("BIP key_len=%d , index=%d @@@@@@@@@@@@@@@@@@\n", param->u.crypt.key_len, param->u.crypt.idx);
++ //save the IGTK key, length 16 bytes
++ _rtw_memcpy(padapter->securitypriv.dot11wBIPKey[param->u.crypt.idx].skey, param->u.crypt.key,(param->u.crypt.key_len>16 ?16:param->u.crypt.key_len));
++ /*DBG_871X("IGTK key below:\n");
++ for(no=0;no<16;no++)
++ printk(" %02x ", padapter->securitypriv.dot11wBIPKey[param->u.crypt.idx].skey[no]);
++ DBG_871X("\n");*/
++ padapter->securitypriv.dot11wBIPKeyid = param->u.crypt.idx;
++ padapter->securitypriv.binstallBIPkey = _TRUE;
++ DBG_871X(" ~~~~set sta key:IGKT\n");
++ }
++#endif //CONFIG_IEEE80211W
++
++#ifdef CONFIG_P2P
++ if(pwdinfo->driver_interface == DRIVER_CFG80211 )
++ {
++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_PROVISIONING_ING))
++ {
++ rtw_p2p_set_state(pwdinfo, P2P_STATE_PROVISIONING_DONE);
++ }
++ }
++#endif //CONFIG_P2P
++
++ }
++ }
++
++ pbcmc_sta=rtw_get_bcmc_stainfo(padapter);
++ if(pbcmc_sta==NULL)
++ {
++ //DEBUG_ERR( ("Set OID_802_11_ADD_KEY: bcmc stainfo is null \n"));
++ }
++ else
++ {
++ //Jeff: don't disable ieee8021x_blocked while clearing key
++ if (strcmp(param->u.crypt.alg, "none") != 0)
++ pbcmc_sta->ieee8021x_blocked = _FALSE;
++
++ if((padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption2Enabled)||
++ (padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption3Enabled))
++ {
++ pbcmc_sta->dot118021XPrivacy = padapter->securitypriv.dot11PrivacyAlgrthm;
++ }
++ }
++ }
++ else if(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE)) //adhoc mode
++ {
++ }
++ }
++
++exit:
++
++ DBG_8192C("%s, ret=%d\n", __func__, ret);
++
++ _func_exit_;
++
++ return ret;
++}
++
++static int cfg80211_rtw_add_key(struct wiphy *wiphy, struct net_device *ndev,
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE)
++ u8 key_index, bool pairwise, const u8 *mac_addr,
++#else // (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37))
++ u8 key_index, const u8 *mac_addr,
++#endif // (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37))
++ struct key_params *params)
++{
++ char *alg_name;
++ u32 param_len;
++ struct ieee_param *param = NULL;
++ int ret=0;
++ struct wireless_dev *rtw_wdev = wiphy_to_wdev(wiphy);
++ _adapter *padapter = wiphy_to_adapter(wiphy);
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++
++ DBG_871X(FUNC_NDEV_FMT" adding key for %pM\n", FUNC_NDEV_ARG(ndev), mac_addr);
++ DBG_871X("cipher=0x%x\n", params->cipher);
++ DBG_871X("key_len=0x%x\n", params->key_len);
++ DBG_871X("seq_len=0x%x\n", params->seq_len);
++ DBG_871X("key_index=%d\n", key_index);
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE)
++ DBG_871X("pairwise=%d\n", pairwise);
++#endif // (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37))
++
++ param_len = sizeof(struct ieee_param) + params->key_len;
++ param = (struct ieee_param *)rtw_malloc(param_len);
++ if (param == NULL)
++ return -1;
++
++ _rtw_memset(param, 0, param_len);
++
++ param->cmd = IEEE_CMD_SET_ENCRYPTION;
++ _rtw_memset(param->sta_addr, 0xff, ETH_ALEN);
++
++ switch (params->cipher) {
++ case IW_AUTH_CIPHER_NONE:
++ //todo: remove key
++ //remove = 1;
++ alg_name = "none";
++ break;
++ case WLAN_CIPHER_SUITE_WEP40:
++ case WLAN_CIPHER_SUITE_WEP104:
++ alg_name = "WEP";
++ break;
++ case WLAN_CIPHER_SUITE_TKIP:
++ alg_name = "TKIP";
++ break;
++ case WLAN_CIPHER_SUITE_CCMP:
++ alg_name = "CCMP";
++ break;
++#ifdef CONFIG_IEEE80211W
++ case WLAN_CIPHER_SUITE_AES_CMAC:
++ alg_name = "BIP";
++ break;
++#endif //CONFIG_IEEE80211W
++ default:
++ return -ENOTSUPP;
++ }
++
++ strncpy((char *)param->u.crypt.alg, alg_name, IEEE_CRYPT_ALG_NAME_LEN);
++
++
++ if (!mac_addr || is_broadcast_ether_addr(mac_addr))
++ {
++ param->u.crypt.set_tx = 0; //for wpa/wpa2 group key
++ } else {
++ param->u.crypt.set_tx = 1; //for wpa/wpa2 pairwise key
++ }
++
++
++ //param->u.crypt.idx = key_index - 1;
++ param->u.crypt.idx = key_index;
++
++ if (params->seq_len && params->seq)
++ {
++ _rtw_memcpy(param->u.crypt.seq, params->seq, params->seq_len);
++ }
++
++ if(params->key_len && params->key)
++ {
++ param->u.crypt.key_len = params->key_len;
++ _rtw_memcpy(param->u.crypt.key, params->key, params->key_len);
++ }
++
++ if(check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)
++ {
++ ret = rtw_cfg80211_set_encryption(ndev, param, param_len);
++ }
++ else if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE)
++ {
++#ifdef CONFIG_AP_MODE
++ if(mac_addr)
++ _rtw_memcpy(param->sta_addr, (void*)mac_addr, ETH_ALEN);
++
++ ret = rtw_cfg80211_ap_set_encryption(ndev, param, param_len);
++#endif
++ }
++ else
++ {
++ DBG_8192C("error! fw_state=0x%x, iftype=%d\n", pmlmepriv->fw_state, rtw_wdev->iftype);
++
++ }
++
++ if(param)
++ {
++ rtw_mfree((u8*)param, param_len);
++ }
++
++ return ret;
++
++}
++
++static int cfg80211_rtw_get_key(struct wiphy *wiphy, struct net_device *ndev,
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE)
++ u8 key_index, bool pairwise, const u8 *mac_addr,
++#else // (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37))
++ u8 key_index, const u8 *mac_addr,
++#endif // (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37))
++ void *cookie,
++ void (*callback)(void *cookie,
++ struct key_params*))
++{
++#if 0
++ struct iwm_priv *iwm = ndev_to_iwm(ndev);
++ struct iwm_key *key = &iwm->keys[key_index];
++ struct key_params params;
++
++ IWM_DBG_WEXT(iwm, DBG, "Getting key %d\n", key_index);
++
++ memset(&params, 0, sizeof(params));
++
++ params.cipher = key->cipher;
++ params.key_len = key->key_len;
++ params.seq_len = key->seq_len;
++ params.seq = key->seq;
++ params.key = key->key;
++
++ callback(cookie, &params);
++
++ return key->key_len ? 0 : -ENOENT;
++#endif
++ DBG_871X(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev));
++ return 0;
++}
++
++static int cfg80211_rtw_del_key(struct wiphy *wiphy, struct net_device *ndev,
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE)
++ u8 key_index, bool pairwise, const u8 *mac_addr)
++#else // (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37))
++ u8 key_index, const u8 *mac_addr)
++#endif // (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37))
++{
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
++ struct security_priv *psecuritypriv = &padapter->securitypriv;
++
++ DBG_871X(FUNC_NDEV_FMT" key_index=%d\n", FUNC_NDEV_ARG(ndev), key_index);
++
++ if (key_index == psecuritypriv->dot11PrivacyKeyIndex)
++ {
++ //clear the flag of wep default key set.
++ psecuritypriv->bWepDefaultKeyIdxSet = 0;
++ }
++
++ return 0;
++}
++
++static int cfg80211_rtw_set_default_key(struct wiphy *wiphy,
++ struct net_device *ndev, u8 key_index
++ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38)) || defined(COMPAT_KERNEL_RELEASE)
++ , bool unicast, bool multicast
++ #endif
++ )
++{
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
++ struct security_priv *psecuritypriv = &padapter->securitypriv;
++
++ DBG_871X(FUNC_NDEV_FMT" key_index=%d"
++ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38)) || defined(COMPAT_KERNEL_RELEASE)
++ ", unicast=%d, multicast=%d"
++ #endif
++ ".\n", FUNC_NDEV_ARG(ndev), key_index
++ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38)) || defined(COMPAT_KERNEL_RELEASE)
++ , unicast, multicast
++ #endif
++ );
++
++ if ((key_index < WEP_KEYS) && ((psecuritypriv->dot11PrivacyAlgrthm == _WEP40_) || (psecuritypriv->dot11PrivacyAlgrthm == _WEP104_))) //set wep default key
++ {
++ psecuritypriv->ndisencryptstatus = Ndis802_11Encryption1Enabled;
++
++ psecuritypriv->dot11PrivacyKeyIndex = key_index;
++
++ psecuritypriv->dot11PrivacyAlgrthm = _WEP40_;
++ psecuritypriv->dot118021XGrpPrivacy = _WEP40_;
++ if (psecuritypriv->dot11DefKeylen[key_index] == 13)
++ {
++ psecuritypriv->dot11PrivacyAlgrthm = _WEP104_;
++ psecuritypriv->dot118021XGrpPrivacy = _WEP104_;
++ }
++
++ psecuritypriv->bWepDefaultKeyIdxSet = 1; //set the flag to represent that wep default key has been set
++ }
++
++ return 0;
++
++}
++
++static int cfg80211_rtw_get_station(struct wiphy *wiphy,
++ struct net_device *ndev,
++ u8 *mac, struct station_info *sinfo)
++{
++ int ret = 0;
++ _adapter *padapter = wiphy_to_adapter(wiphy);
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct sta_info *psta = NULL;
++ struct sta_priv *pstapriv = &padapter->stapriv;
++
++ sinfo->filled = 0;
++
++ if (!mac) {
++ DBG_871X(FUNC_NDEV_FMT" mac==%p\n", FUNC_NDEV_ARG(ndev), mac);
++ ret = -ENOENT;
++ goto exit;
++ }
++
++ psta = rtw_get_stainfo(pstapriv, mac);
++ if (psta == NULL) {
++ DBG_8192C("%s, sta_info is null\n", __func__);
++ ret = -ENOENT;
++ goto exit;
++ }
++
++#ifdef CONFIG_DEBUG_CFG80211
++ DBG_871X(FUNC_NDEV_FMT" mac="MAC_FMT"\n", FUNC_NDEV_ARG(ndev), MAC_ARG(mac));
++#endif
++
++ //for infra./P2PClient mode
++ if( check_fwstate(pmlmepriv, WIFI_STATION_STATE)
++ && check_fwstate(pmlmepriv, _FW_LINKED)
++ )
++ {
++ struct wlan_network *cur_network = &(pmlmepriv->cur_network);
++
++ if (_rtw_memcmp(mac, cur_network->network.MacAddress, ETH_ALEN) == _FALSE) {
++ DBG_871X("%s, mismatch bssid="MAC_FMT"\n", __func__, MAC_ARG(cur_network->network.MacAddress));
++ ret = -ENOENT;
++ goto exit;
++ }
++
++ sinfo->filled |= STATION_INFO_SIGNAL;
++ sinfo->signal = translate_percentage_to_dbm(padapter->recvpriv.signal_strength);
++
++ sinfo->filled |= STATION_INFO_TX_BITRATE;
++ sinfo->txrate.legacy = rtw_get_cur_max_rate(padapter);
++
++ sinfo->filled |= STATION_INFO_RX_PACKETS;
++ sinfo->rx_packets = sta_rx_data_pkts(psta);
++
++ sinfo->filled |= STATION_INFO_TX_PACKETS;
++ sinfo->tx_packets = psta->sta_stats.tx_pkts;
++
++ }
++
++ //for Ad-Hoc/AP mode
++ if ((check_fwstate(pmlmepriv, WIFI_ADHOC_STATE)
++ ||check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)
++ ||check_fwstate(pmlmepriv, WIFI_AP_STATE))
++ && check_fwstate(pmlmepriv, _FW_LINKED)
++ )
++ {
++ //TODO: should acquire station info...
++ }
++
++exit:
++ return ret;
++}
++
++extern int netdev_open(struct net_device *pnetdev);
++#ifdef CONFIG_CONCURRENT_MODE
++extern int netdev_if2_open(struct net_device *pnetdev);
++#endif
++
++/*
++enum nl80211_iftype {
++ NL80211_IFTYPE_UNSPECIFIED,
++ NL80211_IFTYPE_ADHOC, //1
++ NL80211_IFTYPE_STATION, //2
++ NL80211_IFTYPE_AP, //3
++ NL80211_IFTYPE_AP_VLAN,
++ NL80211_IFTYPE_WDS,
++ NL80211_IFTYPE_MONITOR, //6
++ NL80211_IFTYPE_MESH_POINT,
++ NL80211_IFTYPE_P2P_CLIENT, //8
++ NL80211_IFTYPE_P2P_GO, //9
++ //keep last
++ NUM_NL80211_IFTYPES,
++ NL80211_IFTYPE_MAX = NUM_NL80211_IFTYPES - 1
++};
++*/
++static int cfg80211_rtw_change_iface(struct wiphy *wiphy,
++ struct net_device *ndev,
++ enum nl80211_iftype type, u32 *flags,
++ struct vif_params *params)
++{
++ enum nl80211_iftype old_type;
++ NDIS_802_11_NETWORK_INFRASTRUCTURE networkType ;
++ _adapter *padapter = wiphy_to_adapter(wiphy);
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++ struct wireless_dev *rtw_wdev = wiphy_to_wdev(wiphy);
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ _irqL irqL;
++ _queue *queue = &pmlmepriv->scanned_queue;
++#ifdef CONFIG_P2P
++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo);
++#endif
++ int ret = 0;
++ u8 change = _FALSE;
++
++ if (adapter_to_dvobj(padapter)->processing_dev_remove == _TRUE) {
++ ret= -EPERM;
++ goto exit;
++ }
++
++#ifdef CONFIG_CONCURRENT_MODE
++ if(padapter->adapter_type == SECONDARY_ADAPTER)
++ {
++ DBG_871X(FUNC_NDEV_FMT" call netdev_if2_open\n", FUNC_NDEV_ARG(ndev));
++ if(netdev_if2_open(ndev) != 0) {
++ ret= -EPERM;
++ goto exit;
++ }
++ }
++ else if(padapter->adapter_type == PRIMARY_ADAPTER)
++#endif //CONFIG_CONCURRENT_MODE
++ {
++ DBG_871X(FUNC_NDEV_FMT" call netdev_open\n", FUNC_NDEV_ARG(ndev));
++ if(netdev_open(ndev) != 0) {
++ ret= -EPERM;
++ goto exit;
++ }
++ }
++
++ if(_FAIL == rtw_pwr_wakeup(padapter)) {
++ ret= -EPERM;
++ goto exit;
++ }
++
++ old_type = rtw_wdev->iftype;
++ DBG_871X(FUNC_NDEV_FMT" old_iftype=%d, new_iftype=%d\n",
++ FUNC_NDEV_ARG(ndev), old_type, type);
++
++ if(old_type != type)
++ {
++ change = _TRUE;
++ pmlmeext->action_public_rxseq = 0xffff;
++ pmlmeext->action_public_dialog_token = 0xff;
++ }
++
++ switch (type) {
++ case NL80211_IFTYPE_ADHOC:
++ networkType = Ndis802_11IBSS;
++ break;
++#if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE))
++ case NL80211_IFTYPE_P2P_CLIENT:
++#endif
++ case NL80211_IFTYPE_STATION:
++ networkType = Ndis802_11Infrastructure;
++ #ifdef CONFIG_P2P
++ if(pwdinfo->driver_interface == DRIVER_CFG80211 )
++ {
++ if(change && rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO))
++ {
++ _cancel_timer_ex( &pwdinfo->find_phase_timer );
++ _cancel_timer_ex( &pwdinfo->restore_p2p_state_timer );
++ _cancel_timer_ex( &pwdinfo->pre_tx_scan_timer);
++
++ //it means remove GO and change mode from AP(GO) to station(P2P DEVICE)
++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE);
++ rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo));
++
++ DBG_8192C("%s, role=%d, p2p_state=%d, pre_p2p_state=%d\n", __func__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo), rtw_p2p_pre_state(pwdinfo));
++ }
++ }
++ #endif //CONFIG_P2P
++ break;
++#if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE))
++ case NL80211_IFTYPE_P2P_GO:
++#endif
++ case NL80211_IFTYPE_AP:
++ networkType = Ndis802_11APMode;
++ #ifdef CONFIG_P2P
++ if(pwdinfo->driver_interface == DRIVER_CFG80211 )
++ {
++ if(change && !rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
++ {
++ //it means P2P Group created, we will be GO and change mode from P2P DEVICE to AP(GO)
++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO);
++ }
++ }
++ #endif //CONFIG_P2P
++ break;
++ default:
++ return -EOPNOTSUPP;
++ }
++
++ rtw_wdev->iftype = type;
++
++ _enter_critical_bh(&pmlmepriv->lock, &irqL);
++ _enter_critical_bh(&queue->lock, &irqL);
++
++ if (rtw_set_802_11_infrastructure_mode(padapter, networkType) ==_FALSE)
++ {
++ rtw_wdev->iftype = old_type;
++ ret = -EPERM;
++ _exit_critical_bh(&queue->lock, &irqL);
++ _exit_critical_bh(&pmlmepriv->lock, &irqL);
++ goto exit;
++ }
++ _exit_critical_bh(&queue->lock, &irqL);
++ _exit_critical_bh(&pmlmepriv->lock, &irqL);
++
++ rtw_setopmode_cmd(padapter, networkType);
++
++exit:
++
++ return ret;
++}
++
++void rtw_cfg80211_indicate_scan_done(struct rtw_wdev_priv *pwdev_priv, bool aborted)
++{
++ _irqL irqL;
++
++ _enter_critical_bh(&pwdev_priv->scan_req_lock, &irqL);
++ if(pwdev_priv->scan_request != NULL)
++ {
++ //struct cfg80211_scan_request *scan_request = pwdev_priv->scan_request;
++
++ #ifdef CONFIG_DEBUG_CFG80211
++ DBG_871X("%s with scan req\n", __FUNCTION__);
++ #endif
++
++ //avoid WARN_ON(request != wiphy_to_dev(request->wiphy)->scan_req);
++ //if(scan_request == wiphy_to_dev(scan_request->wiphy)->scan_req)
++ if(pwdev_priv->scan_request->wiphy != pwdev_priv->rtw_wdev->wiphy)
++ {
++ DBG_8192C("error wiphy compare\n");
++ }
++ else
++ {
++ cfg80211_scan_done(pwdev_priv->scan_request, aborted);
++ }
++
++ pwdev_priv->scan_request = NULL;
++
++ } else {
++ #ifdef CONFIG_DEBUG_CFG80211
++ DBG_871X("%s without scan req\n", __FUNCTION__);
++ #endif
++ }
++ _exit_critical_bh(&pwdev_priv->scan_req_lock, &irqL);
++}
++
++void rtw_cfg80211_surveydone_event_callback(_adapter *padapter)
++{
++ _irqL irqL;
++ _list *plist, *phead;
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ _queue *queue = &(pmlmepriv->scanned_queue);
++ struct wlan_network *pnetwork = NULL;
++ u32 cnt=0;
++ u32 wait_for_surveydone;
++ sint wait_status;
++#ifdef CONFIG_P2P
++ struct wifidirect_info* pwdinfo = &padapter->wdinfo;
++#endif //CONFIG_P2P
++ struct rtw_wdev_priv *pwdev_priv = wdev_to_priv(padapter->rtw_wdev);
++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
++
++#ifdef CONFIG_DEBUG_CFG80211
++ DBG_8192C("%s\n", __func__);
++#endif
++
++ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++
++ phead = get_list_head(queue);
++ plist = get_next(phead);
++
++ while(1)
++ {
++ if (rtw_end_of_queue_search(phead,plist)== _TRUE)
++ break;
++
++ pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
++
++ //report network only if the current channel set contains the channel to which this network belongs
++ if(rtw_ch_set_search_ch(padapter->mlmeextpriv.channel_set, pnetwork->network.Configuration.DSConfig) >= 0
++ && rtw_mlme_band_check(padapter, pnetwork->network.Configuration.DSConfig) == _TRUE
++ && _TRUE == rtw_validate_ssid(&(pnetwork->network.Ssid))
++ )
++ {
++ //ev=translate_scan(padapter, a, pnetwork, ev, stop);
++ rtw_cfg80211_inform_bss(padapter, pnetwork);
++ }
++
++ plist = get_next(plist);
++
++ }
++
++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++
++ //call this after other things have been done
++ rtw_cfg80211_indicate_scan_done(wdev_to_priv(padapter->rtw_wdev), _FALSE);
++}
++
++static int rtw_cfg80211_set_probe_req_wpsp2pie(_adapter *padapter, char *buf, int len)
++{
++ int ret = 0;
++ uint wps_ielen = 0;
++ u8 *wps_ie;
++ u32 p2p_ielen = 0;
++ u8 *p2p_ie;
++ u32 wfd_ielen = 0;
++ u8 *wfd_ie;
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++
++#ifdef CONFIG_DEBUG_CFG80211
++ DBG_8192C("%s, ielen=%d\n", __func__, len);
++#endif
++
++ if(len>0)
++ {
++ if((wps_ie = rtw_get_wps_ie(buf, len, NULL, &wps_ielen)))
++ {
++ #ifdef CONFIG_DEBUG_CFG80211
++ DBG_8192C("probe_req_wps_ielen=%d\n", wps_ielen);
++ #endif
++
++ if(pmlmepriv->wps_probe_req_ie)
++ {
++ u32 free_len = pmlmepriv->wps_probe_req_ie_len;
++ pmlmepriv->wps_probe_req_ie_len = 0;
++ rtw_mfree(pmlmepriv->wps_probe_req_ie, free_len);
++ pmlmepriv->wps_probe_req_ie = NULL;
++ }
++
++ pmlmepriv->wps_probe_req_ie = rtw_malloc(wps_ielen);
++ if ( pmlmepriv->wps_probe_req_ie == NULL) {
++ DBG_8192C("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__);
++ return -EINVAL;
++
++ }
++ _rtw_memcpy(pmlmepriv->wps_probe_req_ie, wps_ie, wps_ielen);
++ pmlmepriv->wps_probe_req_ie_len = wps_ielen;
++ }
++
++ //buf += wps_ielen;
++ //len -= wps_ielen;
++
++ #ifdef CONFIG_P2P
++ if((p2p_ie=rtw_get_p2p_ie(buf, len, NULL, &p2p_ielen)))
++ {
++ struct wifidirect_info *wdinfo = &padapter->wdinfo;
++ u32 attr_contentlen = 0;
++ u8 listen_ch_attr[5];
++
++ #ifdef CONFIG_DEBUG_CFG80211
++ DBG_8192C("probe_req_p2p_ielen=%d\n", p2p_ielen);
++ #endif
++
++ if(pmlmepriv->p2p_probe_req_ie)
++ {
++ u32 free_len = pmlmepriv->p2p_probe_req_ie_len;
++ pmlmepriv->p2p_probe_req_ie_len = 0;
++ rtw_mfree(pmlmepriv->p2p_probe_req_ie, free_len);
++ pmlmepriv->p2p_probe_req_ie = NULL;
++ }
++
++ pmlmepriv->p2p_probe_req_ie = rtw_malloc(p2p_ielen);
++ if ( pmlmepriv->p2p_probe_req_ie == NULL) {
++ DBG_8192C("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__);
++ return -EINVAL;
++
++ }
++ _rtw_memcpy(pmlmepriv->p2p_probe_req_ie, p2p_ie, p2p_ielen);
++ pmlmepriv->p2p_probe_req_ie_len = p2p_ielen;
++
++ if(rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_LISTEN_CH, (u8*)listen_ch_attr, (uint*) &attr_contentlen)
++ && attr_contentlen == 5)
++ {
++ if (wdinfo->listen_channel != listen_ch_attr[4]) {
++ DBG_871X(FUNC_ADPT_FMT" listen channel - country:%c%c%c, class:%u, ch:%u\n",
++ FUNC_ADPT_ARG(padapter), listen_ch_attr[0], listen_ch_attr[1], listen_ch_attr[2],
++ listen_ch_attr[3], listen_ch_attr[4]);
++ wdinfo->listen_channel = listen_ch_attr[4];
++ }
++ }
++ }
++ #endif //CONFIG_P2P
++
++ //buf += p2p_ielen;
++ //len -= p2p_ielen;
++
++ #ifdef CONFIG_WFD
++ if(rtw_get_wfd_ie(buf, len, NULL, &wfd_ielen))
++ {
++ #ifdef CONFIG_DEBUG_CFG80211
++ DBG_8192C("probe_req_wfd_ielen=%d\n", wfd_ielen);
++ #endif
++
++ if(pmlmepriv->wfd_probe_req_ie)
++ {
++ u32 free_len = pmlmepriv->wfd_probe_req_ie_len;
++ pmlmepriv->wfd_probe_req_ie_len = 0;
++ rtw_mfree(pmlmepriv->wfd_probe_req_ie, free_len);
++ pmlmepriv->wfd_probe_req_ie = NULL;
++ }
++
++ pmlmepriv->wfd_probe_req_ie = rtw_malloc(wfd_ielen);
++ if ( pmlmepriv->wfd_probe_req_ie == NULL) {
++ DBG_8192C("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__);
++ return -EINVAL;
++
++ }
++ rtw_get_wfd_ie(buf, len, pmlmepriv->wfd_probe_req_ie, &pmlmepriv->wfd_probe_req_ie_len);
++ }
++ #endif //CONFIG_WFD
++
++ }
++
++ return ret;
++
++}
++
++static int cfg80211_rtw_scan(struct wiphy *wiphy
++ #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 6, 0))
++ , struct net_device *ndev
++ #endif
++ , struct cfg80211_scan_request *request)
++{
++ int i;
++ u8 _status = _FALSE;
++ int ret = 0;
++ _adapter *padapter = wiphy_to_adapter(wiphy);
++ struct mlme_priv *pmlmepriv= &padapter->mlmepriv;
++ NDIS_802_11_SSID ssid[RTW_SSID_SCAN_AMOUNT];
++ struct rtw_ieee80211_channel ch[RTW_CHANNEL_SCAN_AMOUNT];
++ _irqL irqL;
++ u8 *wps_ie=NULL;
++ uint wps_ielen=0;
++ u8 *p2p_ie=NULL;
++ uint p2p_ielen=0;
++ u8 survey_times=3;
++ u8 survey_times_for_one_ch=6;
++#ifdef CONFIG_P2P
++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo);
++#endif //CONFIG_P2P
++ struct rtw_wdev_priv *pwdev_priv = wdev_to_priv(padapter->rtw_wdev);
++ struct cfg80211_ssid *ssids = request->ssids;
++ int social_channel = 0, j = 0;
++ bool need_indicate_scan_done = _FALSE;
++#ifdef CONFIG_CONCURRENT_MODE
++ PADAPTER pbuddy_adapter = NULL;
++ struct mlme_priv *pbuddy_mlmepriv = NULL;
++#endif //CONFIG_CONCURRENT_MODE
++
++//#ifdef CONFIG_DEBUG_CFG80211
++ DBG_871X(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
++//#endif
++
++#ifdef CONFIG_CONCURRENT_MODE
++ if (padapter->pbuddy_adapter) {
++ pbuddy_adapter = padapter->pbuddy_adapter;
++ pbuddy_mlmepriv = &(pbuddy_adapter->mlmepriv);
++ }
++#endif //CONFIG_CONCURRENT_MODE
++
++#ifdef CONFIG_MP_INCLUDED
++ if (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE)
++ {
++ ret = -EPERM;
++ goto exit;
++ }
++#endif
++
++ _enter_critical_bh(&pwdev_priv->scan_req_lock, &irqL);
++ pwdev_priv->scan_request = request;
++ _exit_critical_bh(&pwdev_priv->scan_req_lock, &irqL);
++
++ if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE)
++ {
++#ifdef CONFIG_DEBUG_CFG80211
++ DBG_871X("%s under WIFI_AP_STATE\n", __FUNCTION__);
++#endif
++
++ if (check_fwstate(pmlmepriv, WIFI_UNDER_WPS|_FW_UNDER_SURVEY|_FW_UNDER_LINKING) == _TRUE)
++ {
++ DBG_8192C("%s, fwstate=0x%x\n", __func__, pmlmepriv->fw_state);
++
++ if(check_fwstate(pmlmepriv, WIFI_UNDER_WPS))
++ {
++ DBG_8192C("AP mode process WPS \n");
++ }
++
++ need_indicate_scan_done = _TRUE;
++ goto check_need_indicate_scan_done;
++ }
++ }
++
++ if(_FAIL == rtw_pwr_wakeup(padapter)) {
++ need_indicate_scan_done = _TRUE;
++ goto check_need_indicate_scan_done;
++ }
++
++ #ifdef CONFIG_P2P
++ if( pwdinfo->driver_interface == DRIVER_CFG80211 )
++ {
++ if(ssids->ssid != NULL
++ && _rtw_memcmp(ssids->ssid, "DIRECT-", 7)
++ && rtw_get_p2p_ie((u8 *)request->ie, request->ie_len, NULL, NULL)
++ )
++ {
++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
++ {
++ u32 initialgain = 0x30;
++ rtw_p2p_enable(padapter, P2P_ROLE_DEVICE);
++ wdev_to_priv(padapter->rtw_wdev)->p2p_enabled = _TRUE;
++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_INITIAL_GAIN, (u8 *)&(initialgain));
++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_INITIAL_GAIN, (u8 *)&(initialgain));
++ }
++ else
++ {
++ rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo));
++ #ifdef CONFIG_DEBUG_CFG80211
++ DBG_8192C("%s, role=%d, p2p_state=%d\n", __func__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo));
++ #endif
++ }
++ rtw_p2p_set_state(pwdinfo, P2P_STATE_LISTEN);
++
++ if(request->n_channels == 3 &&
++ request->channels[0]->hw_value == 1 &&
++ request->channels[1]->hw_value == 6 &&
++ request->channels[2]->hw_value == 11
++ )
++ {
++ social_channel = 1;
++ }
++ }
++ }
++ #endif //CONFIG_P2P
++
++ if(request->ie && request->ie_len>0)
++ {
++ rtw_cfg80211_set_probe_req_wpsp2pie(padapter, (u8 *)request->ie, request->ie_len );
++ }
++
++ if (pmlmepriv->LinkDetectInfo.bBusyTraffic == _TRUE)
++ {
++ DBG_8192C("%s, bBusyTraffic == _TRUE\n", __func__);
++ need_indicate_scan_done = _TRUE;
++ goto check_need_indicate_scan_done;
++ }
++ if (rtw_is_scan_deny(padapter)){
++ DBG_871X(FUNC_ADPT_FMT ": scan deny\n", FUNC_ADPT_ARG(padapter));
++ need_indicate_scan_done = _TRUE;
++ goto check_need_indicate_scan_done;
++ }
++
++#ifdef CONFIG_CONCURRENT_MODE
++ if(pbuddy_mlmepriv && (pbuddy_mlmepriv->LinkDetectInfo.bBusyTraffic == _TRUE))
++ {
++ DBG_8192C("%s, bBusyTraffic == _TRUE at buddy_intf\n", __func__);
++ need_indicate_scan_done = _TRUE;
++ goto check_need_indicate_scan_done;
++ }
++#endif //CONFIG_CONCURRENT_MODE
++
++ if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY|_FW_UNDER_LINKING) == _TRUE)
++ {
++ DBG_8192C("%s, fwstate=0x%x\n", __func__, pmlmepriv->fw_state);
++ need_indicate_scan_done = _TRUE;
++ goto check_need_indicate_scan_done;
++ }
++
++#ifdef CONFIG_CONCURRENT_MODE
++ if (check_buddy_fwstate(padapter,
++ _FW_UNDER_SURVEY|_FW_UNDER_LINKING|WIFI_UNDER_WPS) == _TRUE)
++ {
++ if(check_buddy_fwstate(padapter, _FW_UNDER_SURVEY))
++ {
++ DBG_8192C("scanning_via_buddy_intf\n");
++ pmlmepriv->scanning_via_buddy_intf = _TRUE;
++ }
++
++ DBG_8192C("buddy_intf's mlme state:0x%x\n", pbuddy_mlmepriv->fw_state);
++
++ need_indicate_scan_done = _TRUE;
++ goto check_need_indicate_scan_done;
++ }
++#endif
++
++
++#ifdef CONFIG_P2P
++ if( pwdinfo->driver_interface == DRIVER_CFG80211 )
++ {
++ if(!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) && !rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE))
++ {
++ rtw_p2p_set_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH);
++ rtw_free_network_queue(padapter, _TRUE);
++
++ if(social_channel == 0)
++ rtw_p2p_findphase_ex_set(pwdinfo, P2P_FINDPHASE_EX_NONE);
++ else
++ rtw_p2p_findphase_ex_set(pwdinfo, P2P_FINDPHASE_EX_SOCIAL_LAST);
++ }
++ }
++#endif //CONFIG_P2P
++
++
++ _rtw_memset(ssid, 0, sizeof(NDIS_802_11_SSID)*RTW_SSID_SCAN_AMOUNT);
++ //parsing request ssids, n_ssids
++ for (i = 0; i < request->n_ssids && i < RTW_SSID_SCAN_AMOUNT; i++) {
++ #ifdef CONFIG_DEBUG_CFG80211
++ DBG_8192C("ssid=%s, len=%d\n", ssids[i].ssid, ssids[i].ssid_len);
++ #endif
++ _rtw_memcpy(ssid[i].Ssid, ssids[i].ssid, ssids[i].ssid_len);
++ ssid[i].SsidLength = ssids[i].ssid_len;
++ }
++
++
++ /* parsing channels, n_channels */
++ _rtw_memset(ch, 0, sizeof(struct rtw_ieee80211_channel)*RTW_CHANNEL_SCAN_AMOUNT);
++ for (i=0;i<request->n_channels && i<RTW_CHANNEL_SCAN_AMOUNT;i++) {
++ #ifdef CONFIG_DEBUG_CFG80211
++ DBG_871X(FUNC_ADPT_FMT CHAN_FMT"\n", FUNC_ADPT_ARG(padapter), CHAN_ARG(request->channels[i]));
++ #endif
++ ch[i].hw_value = request->channels[i]->hw_value;
++ ch[i].flags = request->channels[i]->flags;
++ }
++
++ _enter_critical_bh(&pmlmepriv->lock, &irqL);
++ if (request->n_channels == 1) {
++ for(i=1;i<survey_times_for_one_ch;i++)
++ _rtw_memcpy(&ch[i], &ch[0], sizeof(struct rtw_ieee80211_channel));
++ _status = rtw_sitesurvey_cmd(padapter, ssid, RTW_SSID_SCAN_AMOUNT, ch, survey_times_for_one_ch);
++ } else if (request->n_channels == 2) {
++ _rtw_memcpy(&ch[3], &ch[1], sizeof(struct rtw_ieee80211_channel));
++ for(i=1;i<survey_times;i++) {
++ _rtw_memcpy(&ch[i], &ch[0], sizeof(struct rtw_ieee80211_channel));
++ _rtw_memcpy(&ch[i+3], &ch[3], sizeof(struct rtw_ieee80211_channel));
++ }
++ _status = rtw_sitesurvey_cmd(padapter, ssid, RTW_SSID_SCAN_AMOUNT, ch, survey_times * 2);
++ } else {
++ _status = rtw_sitesurvey_cmd(padapter, ssid, RTW_SSID_SCAN_AMOUNT, NULL, 0);
++ }
++ _exit_critical_bh(&pmlmepriv->lock, &irqL);
++
++
++ if(_status == _FALSE)
++ {
++ ret = -1;
++ }
++
++check_need_indicate_scan_done:
++ if(need_indicate_scan_done)
++ rtw_cfg80211_surveydone_event_callback(padapter);
++
++exit:
++
++ return ret;
++
++}
++
++static int cfg80211_rtw_set_wiphy_params(struct wiphy *wiphy, u32 changed)
++{
++#if 0
++ struct iwm_priv *iwm = wiphy_to_iwm(wiphy);
++
++ if (changed & WIPHY_PARAM_RTS_THRESHOLD &&
++ (iwm->conf.rts_threshold != wiphy->rts_threshold)) {
++ int ret;
++
++ iwm->conf.rts_threshold = wiphy->rts_threshold;
++
++ ret = iwm_umac_set_config_fix(iwm, UMAC_PARAM_TBL_CFG_FIX,
++ CFG_RTS_THRESHOLD,
++ iwm->conf.rts_threshold);
++ if (ret < 0)
++ return ret;
++ }
++
++ if (changed & WIPHY_PARAM_FRAG_THRESHOLD &&
++ (iwm->conf.frag_threshold != wiphy->frag_threshold)) {
++ int ret;
++
++ iwm->conf.frag_threshold = wiphy->frag_threshold;
++
++ ret = iwm_umac_set_config_fix(iwm, UMAC_PARAM_TBL_FA_CFG_FIX,
++ CFG_FRAG_THRESHOLD,
++ iwm->conf.frag_threshold);
++ if (ret < 0)
++ return ret;
++ }
++#endif
++ DBG_8192C("%s\n", __func__);
++ return 0;
++}
++
++static int cfg80211_rtw_join_ibss(struct wiphy *wiphy, struct net_device *ndev,
++ struct cfg80211_ibss_params *params)
++{
++#if 0
++ struct iwm_priv *iwm = wiphy_to_iwm(wiphy);
++ struct ieee80211_channel *chan = params->channel;
++
++ if (!test_bit(IWM_STATUS_READY, &iwm->status))
++ return -EIO;
++
++ /* UMAC doesn't support creating or joining an IBSS network
++ * with specified bssid. */
++ if (params->bssid)
++ return -EOPNOTSUPP;
++
++ iwm->channel = ieee80211_frequency_to_channel(chan->center_freq);
++ iwm->umac_profile->ibss.band = chan->band;
++ iwm->umac_profile->ibss.channel = iwm->channel;
++ iwm->umac_profile->ssid.ssid_len = params->ssid_len;
++ memcpy(iwm->umac_profile->ssid.ssid, params->ssid, params->ssid_len);
++
++ return iwm_send_mlme_profile(iwm);
++#endif
++ DBG_871X(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev));
++ return 0;
++}
++
++static int cfg80211_rtw_leave_ibss(struct wiphy *wiphy, struct net_device *ndev)
++{
++#if 0
++ struct iwm_priv *iwm = wiphy_to_iwm(wiphy);
++
++ if (iwm->umac_profile_active)
++ return iwm_invalidate_mlme_profile(iwm);
++#endif
++ DBG_871X(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev));
++ return 0;
++}
++
++static int rtw_cfg80211_set_wpa_version(struct security_priv *psecuritypriv, u32 wpa_version)
++{
++ DBG_8192C("%s, wpa_version=%d\n", __func__, wpa_version);
++
++ if (!wpa_version) {
++ psecuritypriv->ndisauthtype = Ndis802_11AuthModeOpen;
++ return 0;
++ }
++
++
++ if (wpa_version & (NL80211_WPA_VERSION_1 | NL80211_WPA_VERSION_2))
++ {
++ psecuritypriv->ndisauthtype = Ndis802_11AuthModeWPAPSK;
++ }
++
++/*
++ if (wpa_version & NL80211_WPA_VERSION_2)
++ {
++ psecuritypriv->ndisauthtype = Ndis802_11AuthModeWPA2PSK;
++ }
++*/
++
++ return 0;
++
++}
++
++static int rtw_cfg80211_set_auth_type(struct security_priv *psecuritypriv,
++ enum nl80211_auth_type sme_auth_type)
++{
++ DBG_8192C("%s, nl80211_auth_type=%d\n", __func__, sme_auth_type);
++
++
++ switch (sme_auth_type) {
++ case NL80211_AUTHTYPE_AUTOMATIC:
++
++ psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Auto;
++
++ break;
++ case NL80211_AUTHTYPE_OPEN_SYSTEM:
++
++ psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Open;
++
++ if(psecuritypriv->ndisauthtype>Ndis802_11AuthModeWPA)
++ psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_8021X;
++
++ break;
++ case NL80211_AUTHTYPE_SHARED_KEY:
++
++ psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Shared;
++
++ psecuritypriv->ndisencryptstatus = Ndis802_11Encryption1Enabled;
++
++
++ break;
++ default:
++ psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Open;
++ //return -ENOTSUPP;
++ }
++
++ return 0;
++
++}
++
++static int rtw_cfg80211_set_cipher(struct security_priv *psecuritypriv, u32 cipher, bool ucast)
++{
++ u32 ndisencryptstatus = Ndis802_11EncryptionDisabled;
++
++ u32 *profile_cipher = ucast ? &psecuritypriv->dot11PrivacyAlgrthm :
++ &psecuritypriv->dot118021XGrpPrivacy;
++
++ DBG_8192C("%s, ucast=%d, cipher=0x%x\n", __func__, ucast, cipher);
++
++
++ if (!cipher) {
++ *profile_cipher = _NO_PRIVACY_;
++ psecuritypriv->ndisencryptstatus = ndisencryptstatus;
++ return 0;
++ }
++
++ switch (cipher) {
++ case IW_AUTH_CIPHER_NONE:
++ *profile_cipher = _NO_PRIVACY_;
++ ndisencryptstatus = Ndis802_11EncryptionDisabled;
++ break;
++ case WLAN_CIPHER_SUITE_WEP40:
++ *profile_cipher = _WEP40_;
++ ndisencryptstatus = Ndis802_11Encryption1Enabled;
++ break;
++ case WLAN_CIPHER_SUITE_WEP104:
++ *profile_cipher = _WEP104_;
++ ndisencryptstatus = Ndis802_11Encryption1Enabled;
++ break;
++ case WLAN_CIPHER_SUITE_TKIP:
++ *profile_cipher = _TKIP_;
++ ndisencryptstatus = Ndis802_11Encryption2Enabled;
++ break;
++ case WLAN_CIPHER_SUITE_CCMP:
++ *profile_cipher = _AES_;
++ ndisencryptstatus = Ndis802_11Encryption3Enabled;
++ break;
++ default:
++ DBG_8192C("Unsupported cipher: 0x%x\n", cipher);
++ return -ENOTSUPP;
++ }
++
++ if(ucast)
++ {
++ psecuritypriv->ndisencryptstatus = ndisencryptstatus;
++
++ //if(psecuritypriv->dot11PrivacyAlgrthm >= _AES_)
++ // psecuritypriv->ndisauthtype = Ndis802_11AuthModeWPA2PSK;
++ }
++
++ return 0;
++}
++
++static int rtw_cfg80211_set_key_mgt(struct security_priv *psecuritypriv, u32 key_mgt)
++{
++ DBG_8192C("%s, key_mgt=0x%x\n", __func__, key_mgt);
++
++ if (key_mgt == WLAN_AKM_SUITE_8021X)
++ //*auth_type = UMAC_AUTH_TYPE_8021X;
++ psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_8021X;
++ else if (key_mgt == WLAN_AKM_SUITE_PSK) {
++ psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_8021X;
++ } else {
++ DBG_8192C("Invalid key mgt: 0x%x\n", key_mgt);
++ //return -EINVAL;
++ }
++
++ return 0;
++}
++
++static int rtw_cfg80211_set_wpa_ie(_adapter *padapter, u8 *pie, size_t ielen)
++{
++ u8 *buf=NULL, *pos=NULL;
++ u32 left;
++ int group_cipher = 0, pairwise_cipher = 0;
++ int ret = 0;
++ int wpa_ielen=0;
++ int wpa2_ielen=0;
++ u8 *pwpa, *pwpa2;
++ u8 null_addr[]= {0,0,0,0,0,0};
++
++ if (pie == NULL || !ielen) {
++ /* Treat this as normal case, but need to clear WIFI_UNDER_WPS */
++ _clr_fwstate_(&padapter->mlmepriv, WIFI_UNDER_WPS);
++ goto exit;
++ }
++
++ if (ielen > MAX_WPA_IE_LEN+MAX_WPS_IE_LEN+MAX_P2P_IE_LEN) {
++ ret = -EINVAL;
++ goto exit;
++ }
++
++ buf = rtw_zmalloc(ielen);
++ if (buf == NULL){
++ ret = -ENOMEM;
++ goto exit;
++ }
++
++ _rtw_memcpy(buf, pie , ielen);
++
++ //dump
++ {
++ int i;
++ DBG_8192C("set wpa_ie(length:%zu):\n", ielen);
++ for(i=0;i<ielen;i=i+8)
++ DBG_8192C("0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x \n",buf[i],buf[i+1],buf[i+2],buf[i+3],buf[i+4],buf[i+5],buf[i+6],buf[i+7]);
++ }
++
++ pos = buf;
++ if(ielen < RSN_HEADER_LEN){
++ RT_TRACE(_module_rtl871x_ioctl_os_c,_drv_err_,("Ie len too short %d\n", ielen));
++ ret = -1;
++ goto exit;
++ }
++
++ pwpa = rtw_get_wpa_ie(buf, &wpa_ielen, ielen);
++ if(pwpa && wpa_ielen>0)
++ {
++ if(rtw_parse_wpa_ie(pwpa, wpa_ielen+2, &group_cipher, &pairwise_cipher) == _SUCCESS)
++ {
++ padapter->securitypriv.dot11AuthAlgrthm= dot11AuthAlgrthm_8021X;
++ padapter->securitypriv.ndisauthtype=Ndis802_11AuthModeWPAPSK;
++ _rtw_memcpy(padapter->securitypriv.supplicant_ie, &pwpa[0], wpa_ielen+2);
++
++ DBG_8192C("got wpa_ie, wpa_ielen:%u\n", wpa_ielen);
++ }
++ }
++
++ pwpa2 = rtw_get_wpa2_ie(buf, &wpa2_ielen, ielen);
++ if(pwpa2 && wpa2_ielen>0)
++ {
++ if(rtw_parse_wpa2_ie(pwpa2, wpa2_ielen+2, &group_cipher, &pairwise_cipher) == _SUCCESS)
++ {
++ padapter->securitypriv.dot11AuthAlgrthm= dot11AuthAlgrthm_8021X;
++ padapter->securitypriv.ndisauthtype=Ndis802_11AuthModeWPA2PSK;
++ _rtw_memcpy(padapter->securitypriv.supplicant_ie, &pwpa2[0], wpa2_ielen+2);
++
++ DBG_8192C("got wpa2_ie, wpa2_ielen:%u\n", wpa2_ielen);
++ }
++ }
++
++ if (group_cipher == 0)
++ {
++ group_cipher = WPA_CIPHER_NONE;
++ }
++ if (pairwise_cipher == 0)
++ {
++ pairwise_cipher = WPA_CIPHER_NONE;
++ }
++
++ switch(group_cipher)
++ {
++ case WPA_CIPHER_NONE:
++ padapter->securitypriv.dot118021XGrpPrivacy=_NO_PRIVACY_;
++ padapter->securitypriv.ndisencryptstatus=Ndis802_11EncryptionDisabled;
++ break;
++ case WPA_CIPHER_WEP40:
++ padapter->securitypriv.dot118021XGrpPrivacy=_WEP40_;
++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;
++ break;
++ case WPA_CIPHER_TKIP:
++ padapter->securitypriv.dot118021XGrpPrivacy=_TKIP_;
++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption2Enabled;
++ break;
++ case WPA_CIPHER_CCMP:
++ padapter->securitypriv.dot118021XGrpPrivacy=_AES_;
++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption3Enabled;
++ break;
++ case WPA_CIPHER_WEP104:
++ padapter->securitypriv.dot118021XGrpPrivacy=_WEP104_;
++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;
++ break;
++ }
++
++ switch(pairwise_cipher)
++ {
++ case WPA_CIPHER_NONE:
++ padapter->securitypriv.dot11PrivacyAlgrthm=_NO_PRIVACY_;
++ padapter->securitypriv.ndisencryptstatus=Ndis802_11EncryptionDisabled;
++ break;
++ case WPA_CIPHER_WEP40:
++ padapter->securitypriv.dot11PrivacyAlgrthm=_WEP40_;
++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;
++ break;
++ case WPA_CIPHER_TKIP:
++ padapter->securitypriv.dot11PrivacyAlgrthm=_TKIP_;
++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption2Enabled;
++ break;
++ case WPA_CIPHER_CCMP:
++ padapter->securitypriv.dot11PrivacyAlgrthm=_AES_;
++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption3Enabled;
++ break;
++ case WPA_CIPHER_WEP104:
++ padapter->securitypriv.dot11PrivacyAlgrthm=_WEP104_;
++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;
++ break;
++ }
++
++ {/* handle wps_ie */
++ uint wps_ielen;
++ u8 *wps_ie;
++
++ wps_ie = rtw_get_wps_ie(buf, ielen, NULL, &wps_ielen);
++ if (wps_ie && wps_ielen > 0) {
++ DBG_8192C("got wps_ie, wps_ielen:%u\n", wps_ielen);
++ padapter->securitypriv.wps_ie_len = wps_ielen<MAX_WPS_IE_LEN?wps_ielen:MAX_WPS_IE_LEN;
++ _rtw_memcpy(padapter->securitypriv.wps_ie, wps_ie, padapter->securitypriv.wps_ie_len);
++ set_fwstate(&padapter->mlmepriv, WIFI_UNDER_WPS);
++ } else {
++ _clr_fwstate_(&padapter->mlmepriv, WIFI_UNDER_WPS);
++ }
++ }
++
++ #ifdef CONFIG_P2P
++ {//check p2p_ie for assoc req;
++ uint p2p_ielen=0;
++ u8 *p2p_ie;
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++
++ if((p2p_ie=rtw_get_p2p_ie(buf, ielen, NULL, &p2p_ielen)))
++ {
++ #ifdef CONFIG_DEBUG_CFG80211
++ DBG_8192C("%s p2p_assoc_req_ielen=%d\n", __FUNCTION__, p2p_ielen);
++ #endif
++
++ if(pmlmepriv->p2p_assoc_req_ie)
++ {
++ u32 free_len = pmlmepriv->p2p_assoc_req_ie_len;
++ pmlmepriv->p2p_assoc_req_ie_len = 0;
++ rtw_mfree(pmlmepriv->p2p_assoc_req_ie, free_len);
++ pmlmepriv->p2p_assoc_req_ie = NULL;
++ }
++
++ pmlmepriv->p2p_assoc_req_ie = rtw_malloc(p2p_ielen);
++ if ( pmlmepriv->p2p_assoc_req_ie == NULL) {
++ DBG_8192C("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__);
++ goto exit;
++ }
++ _rtw_memcpy(pmlmepriv->p2p_assoc_req_ie, p2p_ie, p2p_ielen);
++ pmlmepriv->p2p_assoc_req_ie_len = p2p_ielen;
++ }
++ }
++ #endif //CONFIG_P2P
++
++ #ifdef CONFIG_WFD
++ {//check wfd_ie for assoc req;
++ uint wfd_ielen=0;
++ u8 *wfd_ie;
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++
++ if(rtw_get_wfd_ie(buf, ielen, NULL, &wfd_ielen))
++ {
++ #ifdef CONFIG_DEBUG_CFG80211
++ DBG_8192C("%s wfd_assoc_req_ielen=%d\n", __FUNCTION__, wfd_ielen);
++ #endif
++
++ if(pmlmepriv->wfd_assoc_req_ie)
++ {
++ u32 free_len = pmlmepriv->wfd_assoc_req_ie_len;
++ pmlmepriv->wfd_assoc_req_ie_len = 0;
++ rtw_mfree(pmlmepriv->wfd_assoc_req_ie, free_len);
++ pmlmepriv->wfd_assoc_req_ie = NULL;
++ }
++
++ pmlmepriv->wfd_assoc_req_ie = rtw_malloc(wfd_ielen);
++ if ( pmlmepriv->wfd_assoc_req_ie == NULL) {
++ DBG_8192C("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__);
++ goto exit;
++ }
++ rtw_get_wfd_ie(buf, ielen, pmlmepriv->wfd_assoc_req_ie, &pmlmepriv->wfd_assoc_req_ie_len);
++ }
++ }
++ #endif //CONFIG_WFD
++
++ //TKIP and AES disallow multicast packets until installing group key
++ if(padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_
++ || padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_WTMIC_
++ || padapter->securitypriv.dot11PrivacyAlgrthm == _AES_)
++ //WPS open need to enable multicast
++ //|| check_fwstate(&padapter->mlmepriv, WIFI_UNDER_WPS) == _TRUE)
++ rtw_hal_set_hwreg(padapter, HW_VAR_OFF_RCR_AM, null_addr);
++
++ RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_info_,
++ ("rtw_set_wpa_ie: pairwise_cipher=0x%08x padapter->securitypriv.ndisencryptstatus=%d padapter->securitypriv.ndisauthtype=%d\n",
++ pairwise_cipher, padapter->securitypriv.ndisencryptstatus, padapter->securitypriv.ndisauthtype));
++
++exit:
++ if (buf)
++ rtw_mfree(buf, ielen);
++ if (ret)
++ _clr_fwstate_(&padapter->mlmepriv, WIFI_UNDER_WPS);
++ return ret;
++}
++
++static int cfg80211_rtw_connect(struct wiphy *wiphy, struct net_device *ndev,
++ struct cfg80211_connect_params *sme)
++{
++ int ret=0;
++ _irqL irqL;
++ _list *phead;
++ struct wlan_network *pnetwork = NULL;
++ NDIS_802_11_AUTHENTICATION_MODE authmode;
++ NDIS_802_11_SSID ndis_ssid;
++ u8 *dst_ssid, *src_ssid;
++ u8 *dst_bssid, *src_bssid;
++ //u8 matched_by_bssid=_FALSE;
++ //u8 matched_by_ssid=_FALSE;
++ u8 matched=_FALSE;
++ _adapter *padapter = wiphy_to_adapter(wiphy);
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct security_priv *psecuritypriv = &padapter->securitypriv;
++ _queue *queue = &pmlmepriv->scanned_queue;
++
++ DBG_871X("=>"FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev));
++ DBG_871X("privacy=%d, key=%p, key_len=%d, key_idx=%d\n",
++ sme->privacy, sme->key, sme->key_len, sme->key_idx);
++
++
++ if(wdev_to_priv(padapter->rtw_wdev)->block == _TRUE)
++ {
++ ret = -EBUSY;
++ DBG_871X("%s wdev_priv.block is set\n", __FUNCTION__);
++ goto exit;
++ }
++
++#ifdef CONFIG_PLATFORM_MSTAR
++ printk("MStar Android!\n");
++ if((wdev_to_priv(padapter->rtw_wdev))->bandroid_scan == _FALSE)
++ {
++#ifdef CONFIG_P2P
++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo);
++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
++#endif //CONFIG_P2P
++ {
++ ret = -EBUSY;
++ printk("Android hasn't attached yet!\n");
++ goto exit;
++ }
++ }
++#endif
++
++ if(_FAIL == rtw_pwr_wakeup(padapter)) {
++ ret= -EPERM;
++ goto exit;
++ }
++
++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE)) {
++ ret = -EPERM;
++ goto exit;
++ }
++
++#ifdef CONFIG_CONCURRENT_MODE
++ if (check_buddy_fwstate(padapter, _FW_UNDER_LINKING) == _TRUE) {
++ DBG_8192C("%s, but buddy_intf is under linking\n", __FUNCTION__);
++ ret = -EINVAL;
++ goto exit;
++ }
++ if (check_buddy_fwstate(padapter, _FW_UNDER_SURVEY) == _TRUE) {
++ rtw_scan_abort(padapter->pbuddy_adapter);
++ }
++#endif
++
++ if (!sme->ssid || !sme->ssid_len)
++ {
++ ret = -EINVAL;
++ goto exit;
++ }
++
++ if (sme->ssid_len > IW_ESSID_MAX_SIZE){
++
++ ret= -E2BIG;
++ goto exit;
++ }
++
++ _rtw_memset(&ndis_ssid, 0, sizeof(NDIS_802_11_SSID));
++ ndis_ssid.SsidLength = sme->ssid_len;
++ _rtw_memcpy(ndis_ssid.Ssid, sme->ssid, sme->ssid_len);
++
++ DBG_8192C("ssid=%s, len=%zu\n", ndis_ssid.Ssid, sme->ssid_len);
++
++
++ if (sme->bssid)
++ DBG_8192C("bssid="MAC_FMT"\n", MAC_ARG(sme->bssid));
++
++
++ if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == _TRUE) {
++ ret = -EBUSY;
++ DBG_8192C("%s, fw_state=0x%x, goto exit\n", __FUNCTION__, pmlmepriv->fw_state);
++ goto exit;
++ }
++ if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE) {
++ rtw_scan_abort(padapter);
++ }
++
++ psecuritypriv->ndisencryptstatus = Ndis802_11EncryptionDisabled;
++ psecuritypriv->dot11PrivacyAlgrthm = _NO_PRIVACY_;
++ psecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_;
++ psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Open; //open system
++ psecuritypriv->ndisauthtype = Ndis802_11AuthModeOpen;
++
++
++ ret = rtw_cfg80211_set_wpa_version(psecuritypriv, sme->crypto.wpa_versions);
++ if (ret < 0)
++ goto exit;
++
++ ret = rtw_cfg80211_set_auth_type(psecuritypriv, sme->auth_type);
++ if (ret < 0)
++ goto exit;
++
++ DBG_8192C("%s, ie_len=%zu\n", __func__, sme->ie_len);
++
++ ret = rtw_cfg80211_set_wpa_ie(padapter, sme->ie, sme->ie_len);
++ if (ret < 0)
++ goto exit;
++
++ if (sme->crypto.n_ciphers_pairwise) {
++ ret = rtw_cfg80211_set_cipher(psecuritypriv, sme->crypto.ciphers_pairwise[0], _TRUE);
++ if (ret < 0)
++ goto exit;
++ }
++
++ //For WEP Shared auth
++ if((psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_Shared
++ || psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_Auto) && sme->key
++ )
++ {
++ u32 wep_key_idx, wep_key_len,wep_total_len;
++ NDIS_802_11_WEP *pwep = NULL;
++ DBG_871X("%s(): Shared/Auto WEP\n",__FUNCTION__);
++
++ wep_key_idx = sme->key_idx;
++ wep_key_len = sme->key_len;
++
++ if (sme->key_idx > WEP_KEYS) {
++ ret = -EINVAL;
++ goto exit;
++ }
++
++ if (wep_key_len > 0)
++ {
++ wep_key_len = wep_key_len <= 5 ? 5 : 13;
++ wep_total_len = wep_key_len + FIELD_OFFSET(NDIS_802_11_WEP, KeyMaterial);
++ pwep =(NDIS_802_11_WEP *) rtw_malloc(wep_total_len);
++ if(pwep == NULL){
++ DBG_871X(" wpa_set_encryption: pwep allocate fail !!!\n");
++ ret = -ENOMEM;
++ goto exit;
++ }
++
++ _rtw_memset(pwep, 0, wep_total_len);
++
++ pwep->KeyLength = wep_key_len;
++ pwep->Length = wep_total_len;
++
++ if(wep_key_len==13)
++ {
++ padapter->securitypriv.dot11PrivacyAlgrthm=_WEP104_;
++ padapter->securitypriv.dot118021XGrpPrivacy=_WEP104_;
++ }
++ }
++ else {
++ ret = -EINVAL;
++ goto exit;
++ }
++
++ pwep->KeyIndex = wep_key_idx;
++ pwep->KeyIndex |= 0x80000000;
++
++ _rtw_memcpy(pwep->KeyMaterial, (void *)sme->key, pwep->KeyLength);
++
++ if(rtw_set_802_11_add_wep(padapter, pwep) == (u8)_FAIL)
++ {
++ ret = -EOPNOTSUPP ;
++ }
++
++ if (pwep) {
++ rtw_mfree((u8 *)pwep,wep_total_len);
++ }
++
++ if(ret < 0)
++ goto exit;
++ }
++
++ ret = rtw_cfg80211_set_cipher(psecuritypriv, sme->crypto.cipher_group, _FALSE);
++ if (ret < 0)
++ return ret;
++
++ if (sme->crypto.n_akm_suites) {
++ ret = rtw_cfg80211_set_key_mgt(psecuritypriv, sme->crypto.akm_suites[0]);
++ if (ret < 0)
++ goto exit;
++ }
++
++ authmode = psecuritypriv->ndisauthtype;
++ rtw_set_802_11_authentication_mode(padapter, authmode);
++
++ //rtw_set_802_11_encryption_mode(padapter, padapter->securitypriv.ndisencryptstatus);
++
++ if (rtw_set_802_11_connect(padapter, sme->bssid, &ndis_ssid) == _FALSE) {
++ ret = -1;
++ goto exit;
++ }
++
++ DBG_8192C("set ssid:dot11AuthAlgrthm=%d, dot11PrivacyAlgrthm=%d, dot118021XGrpPrivacy=%d\n", psecuritypriv->dot11AuthAlgrthm, psecuritypriv->dot11PrivacyAlgrthm, psecuritypriv->dot118021XGrpPrivacy);
++
++exit:
++
++ DBG_8192C("<=%s, ret %d\n",__FUNCTION__, ret);
++
++ return ret;
++}
++
++static int cfg80211_rtw_disconnect(struct wiphy *wiphy, struct net_device *ndev,
++ u16 reason_code)
++{
++ _adapter *padapter = wiphy_to_adapter(wiphy);
++
++ DBG_871X(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev));
++
++ rtw_set_roaming(padapter, 0);
++
++ if(check_fwstate(&padapter->mlmepriv, _FW_LINKED))
++ {
++ rtw_scan_abort(padapter);
++ LeaveAllPowerSaveMode(padapter);
++ rtw_disassoc_cmd(padapter, 500, _FALSE);
++
++ DBG_871X("%s...call rtw_indicate_disconnect\n", __FUNCTION__);
++
++ padapter->mlmepriv.not_indic_disco = _TRUE;
++ rtw_indicate_disconnect(padapter);
++ padapter->mlmepriv.not_indic_disco = _FALSE;
++
++ rtw_free_assoc_resources(padapter, 1);
++ }
++
++ return 0;
++}
++
++static int cfg80211_rtw_set_txpower(struct wiphy *wiphy,
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,8,0))
++ struct wireless_dev *wdev,
++#endif
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,36)) || defined(COMPAT_KERNEL_RELEASE)
++ enum nl80211_tx_power_setting type, int mbm)
++#else
++ enum tx_power_setting type, int dbm)
++#endif
++{
++#if 0
++ struct iwm_priv *iwm = wiphy_to_iwm(wiphy);
++ int ret;
++
++ switch (type) {
++ case NL80211_TX_POWER_AUTOMATIC:
++ return 0;
++ case NL80211_TX_POWER_FIXED:
++ if (mbm < 0 || (mbm % 100))
++ return -EOPNOTSUPP;
++
++ if (!test_bit(IWM_STATUS_READY, &iwm->status))
++ return 0;
++
++ ret = iwm_umac_set_config_fix(iwm, UMAC_PARAM_TBL_CFG_FIX,
++ CFG_TX_PWR_LIMIT_USR,
++ MBM_TO_DBM(mbm) * 2);
++ if (ret < 0)
++ return ret;
++
++ return iwm_tx_power_trigger(iwm);
++ default:
++ IWM_ERR(iwm, "Unsupported power type: %d\n", type);
++ return -EOPNOTSUPP;
++ }
++#endif
++ DBG_8192C("%s\n", __func__);
++ return 0;
++}
++
++static int cfg80211_rtw_get_txpower(struct wiphy *wiphy,
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,8,0))
++ struct wireless_dev *wdev,
++#endif
++ int *dbm)
++{
++ //_adapter *padapter = wiphy_to_adapter(wiphy);
++
++ DBG_8192C("%s\n", __func__);
++
++ *dbm = (12);
++
++ return 0;
++}
++
++inline bool rtw_cfg80211_pwr_mgmt(_adapter *adapter)
++{
++ struct rtw_wdev_priv *rtw_wdev_priv = wdev_to_priv(adapter->rtw_wdev);
++ return rtw_wdev_priv->power_mgmt;
++}
++
++static int cfg80211_rtw_set_power_mgmt(struct wiphy *wiphy,
++ struct net_device *ndev,
++ bool enabled, int timeout)
++{
++ _adapter *padapter = wiphy_to_adapter(wiphy);
++ struct rtw_wdev_priv *rtw_wdev_priv = wdev_to_priv(padapter->rtw_wdev);
++
++ DBG_871X(FUNC_NDEV_FMT" enabled:%u, timeout:%d\n", FUNC_NDEV_ARG(ndev),
++ enabled, timeout);
++
++ rtw_wdev_priv->power_mgmt = enabled;
++
++ #ifdef CONFIG_LPS
++ if (!enabled)
++ LPS_Leave(padapter);
++ #endif
++
++ return 0;
++}
++
++static int cfg80211_rtw_set_pmksa(struct wiphy *wiphy,
++ struct net_device *netdev,
++ struct cfg80211_pmksa *pmksa)
++{
++ u8 index,blInserted = _FALSE;
++ _adapter *padapter = wiphy_to_adapter(wiphy);
++ struct security_priv *psecuritypriv = &padapter->securitypriv;
++ u8 strZeroMacAddress[ ETH_ALEN ] = { 0x00 };
++
++ DBG_871X(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(netdev));
++
++ if ( _rtw_memcmp( pmksa->bssid, strZeroMacAddress, ETH_ALEN ) == _TRUE )
++ {
++ return -EINVAL;
++ }
++
++ blInserted = _FALSE;
++
++ //overwrite PMKID
++ for(index=0 ; index<NUM_PMKID_CACHE; index++)
++ {
++ if( _rtw_memcmp( psecuritypriv->PMKIDList[index].Bssid, pmksa->bssid, ETH_ALEN) ==_TRUE )
++ { // BSSID is matched, the same AP => rewrite with new PMKID.
++ DBG_871X(FUNC_NDEV_FMT" BSSID exists in the PMKList.\n", FUNC_NDEV_ARG(netdev));
++
++ _rtw_memcpy( psecuritypriv->PMKIDList[index].PMKID, pmksa->pmkid, WLAN_PMKID_LEN);
++ psecuritypriv->PMKIDList[index].bUsed = _TRUE;
++ psecuritypriv->PMKIDIndex = index+1;
++ blInserted = _TRUE;
++ break;
++ }
++ }
++
++ if(!blInserted)
++ {
++ // Find a new entry
++ DBG_871X(FUNC_NDEV_FMT" Use the new entry index = %d for this PMKID.\n",
++ FUNC_NDEV_ARG(netdev), psecuritypriv->PMKIDIndex );
++
++ _rtw_memcpy(psecuritypriv->PMKIDList[psecuritypriv->PMKIDIndex].Bssid, pmksa->bssid, ETH_ALEN);
++ _rtw_memcpy(psecuritypriv->PMKIDList[psecuritypriv->PMKIDIndex].PMKID, pmksa->pmkid, WLAN_PMKID_LEN);
++
++ psecuritypriv->PMKIDList[psecuritypriv->PMKIDIndex].bUsed = _TRUE;
++ psecuritypriv->PMKIDIndex++ ;
++ if(psecuritypriv->PMKIDIndex==16)
++ {
++ psecuritypriv->PMKIDIndex =0;
++ }
++ }
++
++ return 0;
++}
++
++static int cfg80211_rtw_del_pmksa(struct wiphy *wiphy,
++ struct net_device *netdev,
++ struct cfg80211_pmksa *pmksa)
++{
++ u8 index, bMatched = _FALSE;
++ _adapter *padapter = wiphy_to_adapter(wiphy);
++ struct security_priv *psecuritypriv = &padapter->securitypriv;
++
++ DBG_871X(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(netdev));
++
++ for(index=0 ; index<NUM_PMKID_CACHE; index++)
++ {
++ if( _rtw_memcmp( psecuritypriv->PMKIDList[index].Bssid, pmksa->bssid, ETH_ALEN) ==_TRUE )
++ { // BSSID is matched, the same AP => Remove this PMKID information and reset it.
++ _rtw_memset( psecuritypriv->PMKIDList[index].Bssid, 0x00, ETH_ALEN );
++ _rtw_memset( psecuritypriv->PMKIDList[index].PMKID, 0x00, WLAN_PMKID_LEN );
++ psecuritypriv->PMKIDList[index].bUsed = _FALSE;
++ bMatched = _TRUE;
++ break;
++ }
++ }
++
++ if(_FALSE == bMatched)
++ {
++ DBG_871X(FUNC_NDEV_FMT" do not have matched BSSID\n"
++ , FUNC_NDEV_ARG(netdev));
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++static int cfg80211_rtw_flush_pmksa(struct wiphy *wiphy,
++ struct net_device *netdev)
++{
++ _adapter *padapter = wiphy_to_adapter(wiphy);
++ struct security_priv *psecuritypriv = &padapter->securitypriv;
++
++ DBG_871X(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(netdev));
++
++ _rtw_memset( &psecuritypriv->PMKIDList[ 0 ], 0x00, sizeof( RT_PMKID_LIST ) * NUM_PMKID_CACHE );
++ psecuritypriv->PMKIDIndex = 0;
++
++ return 0;
++}
++
++#ifdef CONFIG_AP_MODE
++void rtw_cfg80211_indicate_sta_assoc(_adapter *padapter, u8 *pmgmt_frame, uint frame_len)
++{
++ s32 freq;
++ int channel;
++ struct wireless_dev *pwdev = padapter->rtw_wdev;
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++ struct net_device *ndev = padapter->pnetdev;
++
++ DBG_871X(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
++
++#if defined(RTW_USE_CFG80211_STA_EVENT) || defined(COMPAT_KERNEL_RELEASE)
++ {
++ struct station_info sinfo;
++ u8 ie_offset;
++ if (GetFrameSubType(pmgmt_frame) == WIFI_ASSOCREQ)
++ ie_offset = _ASOCREQ_IE_OFFSET_;
++ else // WIFI_REASSOCREQ
++ ie_offset = _REASOCREQ_IE_OFFSET_;
++
++ sinfo.filled = 0;
++ sinfo.filled = STATION_INFO_ASSOC_REQ_IES;
++ sinfo.assoc_req_ies = pmgmt_frame + WLAN_HDR_A3_LEN + ie_offset;
++ sinfo.assoc_req_ies_len = frame_len - WLAN_HDR_A3_LEN - ie_offset;
++ cfg80211_new_sta(ndev, GetAddr2Ptr(pmgmt_frame), &sinfo, GFP_ATOMIC);
++ }
++#else /* defined(RTW_USE_CFG80211_STA_EVENT) */
++ channel = pmlmeext->cur_channel;
++ if (channel <= RTW_CH_MAX_2G_CHANNEL)
++ freq = rtw_ieee80211_channel_to_frequency(channel, IEEE80211_BAND_2GHZ);
++ else
++ freq = rtw_ieee80211_channel_to_frequency(channel, IEEE80211_BAND_5GHZ);
++
++ #ifdef COMPAT_KERNEL_RELEASE
++ rtw_cfg80211_rx_mgmt(padapter, freq, 0, pmgmt_frame, frame_len, GFP_ATOMIC);
++ #elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER)
++ rtw_cfg80211_rx_mgmt(padapter, freq, 0, pmgmt_frame, frame_len, GFP_ATOMIC);
++ #else //COMPAT_KERNEL_RELEASE
++ {
++ //to avoid WARN_ON(wdev->iftype != NL80211_IFTYPE_STATION) when calling cfg80211_send_rx_assoc()
++ #ifndef CONFIG_PLATFORM_MSTAR
++ pwdev->iftype = NL80211_IFTYPE_STATION;
++ #endif //CONFIG_PLATFORM_MSTAR
++ DBG_8192C("iftype=%d before call cfg80211_send_rx_assoc()\n", pwdev->iftype);
++ rtw_cfg80211_send_rx_assoc(padapter, NULL, pmgmt_frame, frame_len);
++ DBG_8192C("iftype=%d after call cfg80211_send_rx_assoc()\n", pwdev->iftype);
++ pwdev->iftype = NL80211_IFTYPE_AP;
++ //cfg80211_rx_action(padapter->pnetdev, freq, pmgmt_frame, frame_len, GFP_ATOMIC);
++ }
++ #endif //COMPAT_KERNEL_RELEASE
++#endif /* defined(RTW_USE_CFG80211_STA_EVENT) */
++
++}
++
++void rtw_cfg80211_indicate_sta_disassoc(_adapter *padapter, unsigned char *da, unsigned short reason)
++{
++ s32 freq;
++ int channel;
++ u8 *pmgmt_frame;
++ uint frame_len;
++ struct rtw_ieee80211_hdr *pwlanhdr;
++ unsigned short *fctrl;
++ u8 mgmt_buf[128] = {0};
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ struct net_device *ndev = padapter->pnetdev;
++
++ DBG_871X(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
++
++#if defined(RTW_USE_CFG80211_STA_EVENT) || defined(COMPAT_KERNEL_RELEASE)
++ cfg80211_del_sta(ndev, da, GFP_ATOMIC);
++#else /* defined(RTW_USE_CFG80211_STA_EVENT) */
++ channel = pmlmeext->cur_channel;
++ if (channel <= RTW_CH_MAX_2G_CHANNEL)
++ freq = rtw_ieee80211_channel_to_frequency(channel, IEEE80211_BAND_2GHZ);
++ else
++ freq = rtw_ieee80211_channel_to_frequency(channel, IEEE80211_BAND_5GHZ);
++
++ pmgmt_frame = mgmt_buf;
++ pwlanhdr = (struct rtw_ieee80211_hdr *)pmgmt_frame;
++
++ fctrl = &(pwlanhdr->frame_ctl);
++ *(fctrl) = 0;
++
++ //_rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);
++ //_rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr1, myid(&(padapter->eeprompriv)), ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr2, da, ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
++
++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
++ pmlmeext->mgnt_seq++;
++ SetFrameSubType(pmgmt_frame, WIFI_DEAUTH);
++
++ pmgmt_frame += sizeof(struct rtw_ieee80211_hdr_3addr);
++ frame_len = sizeof(struct rtw_ieee80211_hdr_3addr);
++
++ reason = cpu_to_le16(reason);
++ pmgmt_frame = rtw_set_fixed_ie(pmgmt_frame, _RSON_CODE_ , (unsigned char *)&reason, &frame_len);
++
++ #ifdef COMPAT_KERNEL_RELEASE
++ rtw_cfg80211_rx_mgmt(padapter, freq, 0, mgmt_buf, frame_len, GFP_ATOMIC);
++ #elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER)
++ rtw_cfg80211_rx_mgmt(padapter, freq, 0, mgmt_buf, frame_len, GFP_ATOMIC);
++ #else //COMPAT_KERNEL_RELEASE
++ cfg80211_send_disassoc(padapter->pnetdev, mgmt_buf, frame_len);
++ //cfg80211_rx_action(padapter->pnetdev, freq, mgmt_buf, frame_len, GFP_ATOMIC);
++ #endif //COMPAT_KERNEL_RELEASE
++#endif /* defined(RTW_USE_CFG80211_STA_EVENT) */
++}
++
++static int rtw_cfg80211_monitor_if_open(struct net_device *ndev)
++{
++ int ret = 0;
++
++ DBG_8192C("%s\n", __func__);
++
++ return ret;
++}
++
++static int rtw_cfg80211_monitor_if_close(struct net_device *ndev)
++{
++ int ret = 0;
++
++ DBG_8192C("%s\n", __func__);
++
++ return ret;
++}
++
++static int rtw_cfg80211_monitor_if_xmit_entry(struct sk_buff *skb, struct net_device *ndev)
++{
++ int ret = 0;
++ int rtap_len;
++ int qos_len = 0;
++ int dot11_hdr_len = 24;
++ int snap_len = 6;
++ unsigned char *pdata;
++ u16 frame_ctl;
++ unsigned char src_mac_addr[6];
++ unsigned char dst_mac_addr[6];
++ struct ieee80211_hdr *dot11_hdr;
++ struct ieee80211_radiotap_header *rtap_hdr;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
++
++ DBG_871X(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev));
++
++ if (skb)
++ rtw_mstat_update(MSTAT_TYPE_SKB, MSTAT_ALLOC_SUCCESS, skb->truesize);
++
++ if (unlikely(skb->len < sizeof(struct ieee80211_radiotap_header)))
++ goto fail;
++
++ rtap_hdr = (struct ieee80211_radiotap_header *)skb->data;
++ if (unlikely(rtap_hdr->it_version))
++ goto fail;
++
++ rtap_len = ieee80211_get_radiotap_len(skb->data);
++ if (unlikely(skb->len < rtap_len))
++ goto fail;
++
++ if(rtap_len != 14)
++ {
++ DBG_8192C("radiotap len (should be 14): %d\n", rtap_len);
++ goto fail;
++ }
++
++ /* Skip the ratio tap header */
++ skb_pull(skb, rtap_len);
++
++ dot11_hdr = (struct ieee80211_hdr *)skb->data;
++ frame_ctl = le16_to_cpu(dot11_hdr->frame_control);
++ /* Check if the QoS bit is set */
++ if ((frame_ctl & RTW_IEEE80211_FCTL_FTYPE) == RTW_IEEE80211_FTYPE_DATA) {
++ /* Check if this ia a Wireless Distribution System (WDS) frame
++ * which has 4 MAC addresses
++ */
++ if (dot11_hdr->frame_control & 0x0080)
++ qos_len = 2;
++ if ((dot11_hdr->frame_control & 0x0300) == 0x0300)
++ dot11_hdr_len += 6;
++
++ memcpy(dst_mac_addr, dot11_hdr->addr1, sizeof(dst_mac_addr));
++ memcpy(src_mac_addr, dot11_hdr->addr2, sizeof(src_mac_addr));
++
++ /* Skip the 802.11 header, QoS (if any) and SNAP, but leave spaces for
++ * for two MAC addresses
++ */
++ skb_pull(skb, dot11_hdr_len + qos_len + snap_len - sizeof(src_mac_addr) * 2);
++ pdata = (unsigned char*)skb->data;
++ memcpy(pdata, dst_mac_addr, sizeof(dst_mac_addr));
++ memcpy(pdata + sizeof(dst_mac_addr), src_mac_addr, sizeof(src_mac_addr));
++
++ DBG_8192C("should be eapol packet\n");
++
++ /* Use the real net device to transmit the packet */
++ ret = _rtw_xmit_entry(skb, padapter->pnetdev);
++
++ return ret;
++
++ }
++ else if ((frame_ctl & (RTW_IEEE80211_FCTL_FTYPE|RTW_IEEE80211_FCTL_STYPE))
++ == (RTW_IEEE80211_FTYPE_MGMT|RTW_IEEE80211_STYPE_ACTION)
++ )
++ {
++ //only for action frames
++ struct xmit_frame *pmgntframe;
++ struct pkt_attrib *pattrib;
++ unsigned char *pframe;
++ //u8 category, action, OUI_Subtype, dialogToken=0;
++ //unsigned char *frame_body;
++ struct rtw_ieee80211_hdr *pwlanhdr;
++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++ u8 *buf = skb->data;
++ u32 len = skb->len;
++ u8 category, action;
++ int type = -1;
++
++ if (rtw_action_frame_parse(buf, len, &category, &action) == _FALSE) {
++ DBG_8192C(FUNC_NDEV_FMT" frame_control:0x%x\n", FUNC_NDEV_ARG(ndev),
++ le16_to_cpu(((struct rtw_ieee80211_hdr_3addr *)buf)->frame_ctl));
++ goto fail;
++ }
++
++ DBG_8192C("RTW_Tx:da="MAC_FMT" via "FUNC_NDEV_FMT"\n",
++ MAC_ARG(GetAddr1Ptr(buf)), FUNC_NDEV_ARG(ndev));
++ #ifdef CONFIG_P2P
++ if((type = rtw_p2p_check_frames(padapter, buf, len, _TRUE)) >= 0)
++ goto dump;
++ #endif
++ if (category == RTW_WLAN_CATEGORY_PUBLIC)
++ DBG_871X("RTW_Tx:%s\n", action_public_str(action));
++ else
++ DBG_871X("RTW_Tx:category(%u), action(%u)\n", category, action);
++
++dump:
++ //starting alloc mgmt frame to dump it
++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL)
++ {
++ goto fail;
++ }
++
++ //update attribute
++ pattrib = &pmgntframe->attrib;
++ update_mgntframe_attrib(padapter, pattrib);
++ pattrib->retry_ctrl = _FALSE;
++
++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++
++ _rtw_memcpy(pframe, (void*)buf, len);
++ #ifdef CONFIG_WFD
++ if (type >= 0)
++ {
++ struct wifi_display_info *pwfd_info;
++
++ pwfd_info = padapter->wdinfo.wfd_info;
++
++ if ( _TRUE == pwfd_info->wfd_enable )
++ {
++ rtw_append_wfd_ie( padapter, pframe, &len );
++ }
++ }
++ #endif // CONFIG_WFD
++ pattrib->pktlen = len;
++
++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++ //update seq number
++ pmlmeext->mgnt_seq = GetSequence(pwlanhdr);
++ pattrib->seqnum = pmlmeext->mgnt_seq;
++ pmlmeext->mgnt_seq++;
++
++
++ pattrib->last_txcmdsz = pattrib->pktlen;
++
++ dump_mgntframe(padapter, pmgntframe);
++
++ }
++ else
++ {
++ DBG_8192C("frame_ctl=0x%x\n", frame_ctl & (RTW_IEEE80211_FCTL_FTYPE|RTW_IEEE80211_FCTL_STYPE));
++ }
++
++
++fail:
++
++ dev_kfree_skb(skb);
++
++ return 0;
++
++}
++
++static void rtw_cfg80211_monitor_if_set_multicast_list(struct net_device *ndev)
++{
++ DBG_8192C("%s\n", __func__);
++}
++
++static int rtw_cfg80211_monitor_if_set_mac_address(struct net_device *ndev, void *addr)
++{
++ int ret = 0;
++
++ DBG_8192C("%s\n", __func__);
++
++ return ret;
++}
++
++#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,29))
++static const struct net_device_ops rtw_cfg80211_monitor_if_ops = {
++ .ndo_open = rtw_cfg80211_monitor_if_open,
++ .ndo_stop = rtw_cfg80211_monitor_if_close,
++ .ndo_start_xmit = rtw_cfg80211_monitor_if_xmit_entry,
++ #if (LINUX_VERSION_CODE < KERNEL_VERSION(3,2,0))
++ .ndo_set_multicast_list = rtw_cfg80211_monitor_if_set_multicast_list,
++ #endif
++ .ndo_set_mac_address = rtw_cfg80211_monitor_if_set_mac_address,
++};
++#endif
++
++static int rtw_cfg80211_add_monitor_if(_adapter *padapter, char *name, struct net_device **ndev)
++{
++ int ret = 0;
++ struct net_device* mon_ndev = NULL;
++ struct wireless_dev* mon_wdev = NULL;
++ struct rtw_netdev_priv_indicator *pnpi;
++ struct rtw_wdev_priv *pwdev_priv = wdev_to_priv(padapter->rtw_wdev);
++
++ if (!name ) {
++ DBG_871X(FUNC_ADPT_FMT" without specific name\n", FUNC_ADPT_ARG(padapter));
++ ret = -EINVAL;
++ goto out;
++ }
++
++ if (pwdev_priv->pmon_ndev) {
++ DBG_871X(FUNC_ADPT_FMT" monitor interface exist: "NDEV_FMT"\n",
++ FUNC_ADPT_ARG(padapter), NDEV_ARG(pwdev_priv->pmon_ndev));
++ ret = -EBUSY;
++ goto out;
++ }
++
++ mon_ndev = alloc_etherdev(sizeof(struct rtw_netdev_priv_indicator));
++ if (!mon_ndev) {
++ DBG_871X(FUNC_ADPT_FMT" allocate ndev fail\n", FUNC_ADPT_ARG(padapter));
++ ret = -ENOMEM;
++ goto out;
++ }
++
++ mon_ndev->type = ARPHRD_IEEE80211_RADIOTAP;
++ strncpy(mon_ndev->name, name, IFNAMSIZ);
++ mon_ndev->name[IFNAMSIZ - 1] = 0;
++ mon_ndev->destructor = rtw_ndev_destructor;
++
++#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,29))
++ mon_ndev->netdev_ops = &rtw_cfg80211_monitor_if_ops;
++#else
++ mon_ndev->open = rtw_cfg80211_monitor_if_open;
++ mon_ndev->stop = rtw_cfg80211_monitor_if_close;
++ mon_ndev->hard_start_xmit = rtw_cfg80211_monitor_if_xmit_entry;
++ mon_ndev->set_mac_address = rtw_cfg80211_monitor_if_set_mac_address;
++#endif
++
++ pnpi = netdev_priv(mon_ndev);
++ pnpi->priv = padapter;
++ pnpi->sizeof_priv = sizeof(_adapter);
++
++ /* wdev */
++ mon_wdev = (struct wireless_dev *)rtw_zmalloc(sizeof(struct wireless_dev));
++ if (!mon_wdev) {
++ DBG_871X(FUNC_ADPT_FMT" allocate mon_wdev fail\n", FUNC_ADPT_ARG(padapter));
++ ret = -ENOMEM;
++ goto out;
++ }
++
++ mon_wdev->wiphy = padapter->rtw_wdev->wiphy;
++ mon_wdev->netdev = mon_ndev;
++ mon_wdev->iftype = NL80211_IFTYPE_MONITOR;
++ mon_ndev->ieee80211_ptr = mon_wdev;
++
++ ret = register_netdevice(mon_ndev);
++ if (ret) {
++ goto out;
++ }
++
++ *ndev = pwdev_priv->pmon_ndev = mon_ndev;
++ _rtw_memcpy(pwdev_priv->ifname_mon, name, IFNAMSIZ+1);
++
++out:
++ if (ret && mon_wdev) {
++ rtw_mfree((u8*)mon_wdev, sizeof(struct wireless_dev));
++ mon_wdev = NULL;
++ }
++
++ if (ret && mon_ndev) {
++ free_netdev(mon_ndev);
++ *ndev = mon_ndev = NULL;
++ }
++
++ return ret;
++}
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,6,0))
++static struct wireless_dev *
++#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38)) || defined(COMPAT_KERNEL_RELEASE)
++static struct net_device *
++#else
++static int
++#endif
++ cfg80211_rtw_add_virtual_intf(
++ struct wiphy *wiphy,
++ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,7,0))
++ const char *name,
++ #else
++ char *name,
++ #endif
++ enum nl80211_iftype type, u32 *flags, struct vif_params *params)
++{
++ int ret = 0;
++ struct net_device* ndev = NULL;
++ _adapter *padapter = wiphy_to_adapter(wiphy);
++
++ DBG_871X(FUNC_ADPT_FMT " wiphy:%s, name:%s, type:%d\n",
++ FUNC_ADPT_ARG(padapter), wiphy_name(wiphy), name, type);
++
++ switch (type) {
++ case NL80211_IFTYPE_ADHOC:
++ case NL80211_IFTYPE_AP_VLAN:
++ case NL80211_IFTYPE_WDS:
++ case NL80211_IFTYPE_MESH_POINT:
++ ret = -ENODEV;
++ break;
++ case NL80211_IFTYPE_MONITOR:
++ ret = rtw_cfg80211_add_monitor_if(padapter, (char *)name, &ndev);
++ break;
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE)
++ case NL80211_IFTYPE_P2P_CLIENT:
++#endif
++ case NL80211_IFTYPE_STATION:
++ ret = -ENODEV;
++ break;
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE)
++ case NL80211_IFTYPE_P2P_GO:
++#endif
++ case NL80211_IFTYPE_AP:
++ ret = -ENODEV;
++ break;
++ default:
++ ret = -ENODEV;
++ DBG_871X("Unsupported interface type\n");
++ break;
++ }
++
++ DBG_871X(FUNC_ADPT_FMT" ndev:%p, ret:%d\n", FUNC_ADPT_ARG(padapter), ndev, ret);
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,6,0))
++ return ndev ? ndev->ieee80211_ptr : ERR_PTR(ret);
++#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38)) || defined(COMPAT_KERNEL_RELEASE)
++ return ndev ? ndev : ERR_PTR(ret);
++#else
++ return ret;
++#endif
++}
++
++static int cfg80211_rtw_del_virtual_intf(struct wiphy *wiphy,
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,6,0))
++ struct wireless_dev *wdev
++#else
++ struct net_device *ndev
++#endif
++)
++{
++ struct rtw_wdev_priv *pwdev_priv = (struct rtw_wdev_priv *)wiphy_priv(wiphy);
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,6,0))
++ struct net_device *ndev;
++ ndev = wdev ? wdev->netdev : NULL;
++#endif
++
++ if (!ndev)
++ goto exit;
++
++ unregister_netdevice(ndev);
++
++ if (ndev == pwdev_priv->pmon_ndev) {
++ pwdev_priv->pmon_ndev = NULL;
++ pwdev_priv->ifname_mon[0] = '\0';
++ DBG_871X(FUNC_NDEV_FMT" remove monitor interface\n", FUNC_NDEV_ARG(ndev));
++ }
++
++exit:
++ return 0;
++}
++
++static int rtw_add_beacon(_adapter *adapter, const u8 *head, size_t head_len, const u8 *tail, size_t tail_len)
++{
++ int ret=0;
++ u8 *pbuf = NULL;
++ uint len, wps_ielen=0;
++ uint p2p_ielen=0;
++ u8 *p2p_ie;
++ u8 got_p2p_ie = _FALSE;
++ struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
++ //struct sta_priv *pstapriv = &padapter->stapriv;
++
++
++ DBG_8192C("%s beacon_head_len=%zu, beacon_tail_len=%zu\n", __FUNCTION__, head_len, tail_len);
++
++
++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE)
++ return -EINVAL;
++
++ if(head_len<24)
++ return -EINVAL;
++
++
++ pbuf = rtw_zmalloc(head_len+tail_len);
++ if(!pbuf)
++ return -ENOMEM;
++
++
++ //_rtw_memcpy(&pstapriv->max_num_sta, param->u.bcn_ie.reserved, 2);
++
++ //if((pstapriv->max_num_sta>NUM_STA) || (pstapriv->max_num_sta<=0))
++ // pstapriv->max_num_sta = NUM_STA;
++
++
++ _rtw_memcpy(pbuf, (void *)head+24, head_len-24);// 24=beacon header len.
++ _rtw_memcpy(pbuf+head_len-24, (void *)tail, tail_len);
++
++ len = head_len+tail_len-24;
++
++ //check wps ie if inclued
++ if(rtw_get_wps_ie(pbuf+_FIXED_IE_LENGTH_, len-_FIXED_IE_LENGTH_, NULL, &wps_ielen))
++ DBG_8192C("add bcn, wps_ielen=%d\n", wps_ielen);
++
++#ifdef CONFIG_P2P
++ //check p2p ie if inclued
++ if( adapter->wdinfo.driver_interface == DRIVER_CFG80211 )
++ {
++ //check p2p if enable
++ if(rtw_get_p2p_ie(pbuf+_FIXED_IE_LENGTH_, len-_FIXED_IE_LENGTH_, NULL, &p2p_ielen))
++ {
++ struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
++ struct wifidirect_info *pwdinfo= &(adapter->wdinfo);
++
++ DBG_8192C("got p2p_ie, len=%d\n", p2p_ielen);
++ got_p2p_ie = _TRUE;
++
++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
++ {
++ DBG_8192C("Enable P2P function for the first time\n");
++ rtw_p2p_enable(adapter, P2P_ROLE_GO);
++ wdev_to_priv(adapter->rtw_wdev)->p2p_enabled = _TRUE;
++ }
++ else
++ {
++ _cancel_timer_ex( &pwdinfo->find_phase_timer );
++ _cancel_timer_ex( &pwdinfo->restore_p2p_state_timer );
++ _cancel_timer_ex( &pwdinfo->pre_tx_scan_timer);
++
++ DBG_8192C("enter GO Mode, p2p_ielen=%d\n", p2p_ielen);
++
++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO);
++ rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK);
++ pwdinfo->intent = 15;
++ }
++ }
++ }
++#endif // CONFIG_P2P
++
++ /* pbss_network->IEs will not include p2p_ie, wfd ie */
++ rtw_ies_remove_ie(pbuf, &len, _BEACON_IE_OFFSET_, _VENDOR_SPECIFIC_IE_, P2P_OUI, 4);
++ rtw_ies_remove_ie(pbuf, &len, _BEACON_IE_OFFSET_, _VENDOR_SPECIFIC_IE_, WFD_OUI, 4);
++
++ if (rtw_check_beacon_data(adapter, pbuf, len) == _SUCCESS)
++ {
++#ifdef CONFIG_P2P
++ //check p2p if enable
++ if(got_p2p_ie == _TRUE)
++ {
++ struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
++ struct wifidirect_info *pwdinfo= &(adapter->wdinfo);
++ pwdinfo->operating_channel = pmlmeext->cur_channel;
++ }
++#endif //CONFIG_P2P
++ ret = 0;
++ }
++ else
++ {
++ ret = -EINVAL;
++ }
++
++
++ rtw_mfree(pbuf, head_len+tail_len);
++
++ return ret;
++}
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,4,0)) && !defined(COMPAT_KERNEL_RELEASE)
++static int cfg80211_rtw_add_beacon(struct wiphy *wiphy, struct net_device *ndev,
++ struct beacon_parameters *info)
++{
++ int ret=0;
++ _adapter *adapter = wiphy_to_adapter(wiphy);
++
++ DBG_871X(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev));
++ ret = rtw_add_beacon(adapter, info->head, info->head_len, info->tail, info->tail_len);
++
++ return ret;
++}
++
++static int cfg80211_rtw_set_beacon(struct wiphy *wiphy, struct net_device *ndev,
++ struct beacon_parameters *info)
++{
++ _adapter *padapter = wiphy_to_adapter(wiphy);
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++
++ DBG_871X(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev));
++
++ pmlmeext->bstart_bss = _TRUE;
++
++ cfg80211_rtw_add_beacon(wiphy, ndev, info);
++
++ return 0;
++}
++
++static int cfg80211_rtw_del_beacon(struct wiphy *wiphy, struct net_device *ndev)
++{
++ DBG_871X(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev));
++
++ return 0;
++}
++#else
++static int cfg80211_rtw_start_ap(struct wiphy *wiphy, struct net_device *ndev,
++ struct cfg80211_ap_settings *settings)
++{
++ int ret = 0;
++ _adapter *adapter = wiphy_to_adapter(wiphy);
++
++ DBG_871X(FUNC_NDEV_FMT" hidden_ssid:%d, auth_type:%d\n", FUNC_NDEV_ARG(ndev),
++ settings->hidden_ssid, settings->auth_type);
++
++ ret = rtw_add_beacon(adapter, settings->beacon.head, settings->beacon.head_len,
++ settings->beacon.tail, settings->beacon.tail_len);
++
++ adapter->mlmeextpriv.mlmext_info.hidden_ssid_mode = settings->hidden_ssid;
++
++ if (settings->ssid && settings->ssid_len) {
++ WLAN_BSSID_EX *pbss_network = &adapter->mlmepriv.cur_network.network;
++ WLAN_BSSID_EX *pbss_network_ext = &adapter->mlmeextpriv.mlmext_info.network;
++
++ if(0)
++ DBG_871X(FUNC_ADPT_FMT" ssid:(%s,%d), from ie:(%s,%d)\n", FUNC_ADPT_ARG(adapter),
++ settings->ssid, settings->ssid_len,
++ pbss_network->Ssid.Ssid, pbss_network->Ssid.SsidLength);
++
++ _rtw_memcpy(pbss_network->Ssid.Ssid, (void *)settings->ssid, settings->ssid_len);
++ pbss_network->Ssid.SsidLength = settings->ssid_len;
++ _rtw_memcpy(pbss_network_ext->Ssid.Ssid, (void *)settings->ssid, settings->ssid_len);
++ pbss_network_ext->Ssid.SsidLength = settings->ssid_len;
++
++ if(0)
++ DBG_871X(FUNC_ADPT_FMT" after ssid:(%s,%d), (%s,%d)\n", FUNC_ADPT_ARG(adapter),
++ pbss_network->Ssid.Ssid, pbss_network->Ssid.SsidLength,
++ pbss_network_ext->Ssid.Ssid, pbss_network_ext->Ssid.SsidLength);
++ }
++
++ return ret;
++}
++
++static int cfg80211_rtw_change_beacon(struct wiphy *wiphy, struct net_device *ndev,
++ struct cfg80211_beacon_data *info)
++{
++ int ret = 0;
++ _adapter *adapter = wiphy_to_adapter(wiphy);
++
++ DBG_871X(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev));
++
++ ret = rtw_add_beacon(adapter, info->head, info->head_len, info->tail, info->tail_len);
++
++ return ret;
++}
++
++static int cfg80211_rtw_stop_ap(struct wiphy *wiphy, struct net_device *ndev)
++{
++ DBG_871X(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev));
++ return 0;
++}
++
++#endif //(LINUX_VERSION_CODE < KERNEL_VERSION(3,4,0))
++
++static int cfg80211_rtw_add_station(struct wiphy *wiphy, struct net_device *ndev,
++ u8 *mac, struct station_parameters *params)
++{
++ DBG_871X(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev));
++
++ return 0;
++}
++
++static int cfg80211_rtw_del_station(struct wiphy *wiphy, struct net_device *ndev,
++ u8 *mac)
++{
++ int ret=0;
++ _irqL irqL;
++ _list *phead, *plist;
++ u8 updated;
++ struct sta_info *psta = NULL;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ struct sta_priv *pstapriv = &padapter->stapriv;
++
++ DBG_871X("+"FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev));
++
++ if(check_fwstate(pmlmepriv, (_FW_LINKED|WIFI_AP_STATE)) != _TRUE)
++ {
++ DBG_8192C("%s, fw_state != FW_LINKED|WIFI_AP_STATE\n", __func__);
++ return -EINVAL;
++ }
++
++
++ if(!mac)
++ {
++ DBG_8192C("flush all sta, and cam_entry\n");
++
++ flush_all_cam_entry(padapter); //clear CAM
++
++ ret = rtw_sta_flush(padapter);
++
++ return ret;
++ }
++
++
++ DBG_8192C("free sta macaddr =" MAC_FMT "\n", MAC_ARG(mac));
++
++ if (mac[0] == 0xff && mac[1] == 0xff &&
++ mac[2] == 0xff && mac[3] == 0xff &&
++ mac[4] == 0xff && mac[5] == 0xff)
++ {
++ return -EINVAL;
++ }
++
++
++ _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++
++ phead = &pstapriv->asoc_list;
++ plist = get_next(phead);
++
++ //check asoc_queue
++ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE)
++ {
++ psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);
++
++ plist = get_next(plist);
++
++ if(_rtw_memcmp(mac, psta->hwaddr, ETH_ALEN))
++ {
++ if(psta->dot8021xalg == 1 && psta->bpairwise_key_installed == _FALSE)
++ {
++ DBG_8192C("%s, sta's dot8021xalg = 1 and key_installed = _FALSE\n", __func__);
++ }
++ else
++ {
++ DBG_8192C("free psta=%p, aid=%d\n", psta, psta->aid);
++
++ rtw_list_delete(&psta->asoc_list);
++ pstapriv->asoc_list_cnt--;
++
++ //_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++ updated = ap_free_sta(padapter, psta, _TRUE, WLAN_REASON_DEAUTH_LEAVING);
++ //_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++
++ psta = NULL;
++
++ break;
++ }
++
++ }
++
++ }
++
++ _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++
++ associated_clients_update(padapter, updated);
++
++ DBG_871X("-"FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev));
++
++ return ret;
++
++}
++
++static int cfg80211_rtw_change_station(struct wiphy *wiphy, struct net_device *ndev,
++ u8 *mac, struct station_parameters *params)
++{
++ DBG_871X(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev));
++
++ return 0;
++}
++
++static int cfg80211_rtw_dump_station(struct wiphy *wiphy, struct net_device *ndev,
++ int idx, u8 *mac, struct station_info *sinfo)
++{
++ DBG_871X(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev));
++
++ //TODO: dump scanned queue
++
++ return -ENOENT;
++}
++
++static int cfg80211_rtw_change_bss(struct wiphy *wiphy, struct net_device *ndev,
++ struct bss_parameters *params)
++{
++ u8 i;
++
++ DBG_871X(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev));
++/*
++ DBG_8192C("use_cts_prot=%d\n", params->use_cts_prot);
++ DBG_8192C("use_short_preamble=%d\n", params->use_short_preamble);
++ DBG_8192C("use_short_slot_time=%d\n", params->use_short_slot_time);
++ DBG_8192C("ap_isolate=%d\n", params->ap_isolate);
++
++ DBG_8192C("basic_rates_len=%d\n", params->basic_rates_len);
++ for(i=0; i<params->basic_rates_len; i++)
++ {
++ DBG_8192C("basic_rates=%d\n", params->basic_rates[i]);
++
++ }
++*/
++ return 0;
++
++}
++
++static int cfg80211_rtw_set_channel(struct wiphy *wiphy
++ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35))
++ , struct net_device *ndev
++ #endif
++ , struct ieee80211_channel *chan, enum nl80211_channel_type channel_type)
++{
++ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35))
++ DBG_871X(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev));
++ #endif
++
++ return 0;
++}
++
++static int cfg80211_rtw_auth(struct wiphy *wiphy, struct net_device *ndev,
++ struct cfg80211_auth_request *req)
++{
++ DBG_871X(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev));
++
++ return 0;
++}
++
++static int cfg80211_rtw_assoc(struct wiphy *wiphy, struct net_device *ndev,
++ struct cfg80211_assoc_request *req)
++{
++ DBG_871X(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev));
++
++ return 0;
++}
++#endif //CONFIG_AP_MODE
++
++void rtw_cfg80211_rx_action_p2p(_adapter *padapter, u8 *pmgmt_frame, uint frame_len)
++{
++ int type;
++ s32 freq;
++ int channel;
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++ u8 category, action;
++
++ channel = rtw_get_oper_ch(padapter);
++
++ DBG_8192C("RTW_Rx:cur_ch=%d\n", channel);
++ #ifdef CONFIG_P2P
++ type = rtw_p2p_check_frames(padapter, pmgmt_frame, frame_len, _FALSE);
++ if (type >= 0)
++ goto indicate;
++ #endif
++ rtw_action_frame_parse(pmgmt_frame, frame_len, &category, &action);
++ DBG_871X("RTW_Rx:category(%u), action(%u)\n", category, action);
++
++indicate:
++ if (channel <= RTW_CH_MAX_2G_CHANNEL)
++ freq = rtw_ieee80211_channel_to_frequency(channel, IEEE80211_BAND_2GHZ);
++ else
++ freq = rtw_ieee80211_channel_to_frequency(channel, IEEE80211_BAND_5GHZ);
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE)
++ rtw_cfg80211_rx_mgmt(padapter, freq, 0, pmgmt_frame, frame_len, GFP_ATOMIC);
++#else
++ cfg80211_rx_action(padapter->pnetdev, freq, pmgmt_frame, frame_len, GFP_ATOMIC);
++#endif
++}
++
++void rtw_cfg80211_rx_p2p_action_public(_adapter *padapter, u8 *pmgmt_frame, uint frame_len)
++{
++ int type;
++ s32 freq;
++ int channel;
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++ u8 category, action;
++
++ channel = rtw_get_oper_ch(padapter);
++
++ DBG_8192C("RTW_Rx:cur_ch=%d\n", channel);
++ #ifdef CONFIG_P2P
++ type = rtw_p2p_check_frames(padapter, pmgmt_frame, frame_len, _FALSE);
++ if (type >= 0) {
++ switch (type) {
++ case P2P_GO_NEGO_CONF:
++ case P2P_PROVISION_DISC_RESP:
++ case P2P_INVIT_RESP:
++ rtw_set_scan_deny(padapter, 2000);
++ rtw_clear_scan_deny(padapter);
++ }
++ goto indicate;
++ }
++ #endif
++ rtw_action_frame_parse(pmgmt_frame, frame_len, &category, &action);
++ DBG_871X("RTW_Rx:category(%u), action(%u)\n", category, action);
++
++indicate:
++ if (channel <= RTW_CH_MAX_2G_CHANNEL)
++ freq = rtw_ieee80211_channel_to_frequency(channel, IEEE80211_BAND_2GHZ);
++ else
++ freq = rtw_ieee80211_channel_to_frequency(channel, IEEE80211_BAND_5GHZ);
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE)
++ rtw_cfg80211_rx_mgmt(padapter, freq, 0, pmgmt_frame, frame_len, GFP_ATOMIC);
++#else
++ cfg80211_rx_action(padapter->pnetdev, freq, pmgmt_frame, frame_len, GFP_ATOMIC);
++#endif
++}
++
++void rtw_cfg80211_rx_action(_adapter *adapter, u8 *frame, uint frame_len, const char*msg)
++{
++ s32 freq;
++ int channel;
++ struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);
++ struct rtw_wdev_priv *pwdev_priv = wdev_to_priv(adapter->rtw_wdev);
++ u8 category, action;
++
++ channel = rtw_get_oper_ch(adapter);
++
++ rtw_action_frame_parse(frame, frame_len, &category, &action);
++
++ DBG_8192C("RTW_Rx:cur_ch=%d\n", channel);
++ if (msg)
++ DBG_871X("RTW_Rx:%s\n", msg);
++ else
++ DBG_871X("RTW_Rx:category(%u), action(%u)\n", category, action);
++
++ if (channel <= RTW_CH_MAX_2G_CHANNEL)
++ freq = rtw_ieee80211_channel_to_frequency(channel, IEEE80211_BAND_2GHZ);
++ else
++ freq = rtw_ieee80211_channel_to_frequency(channel, IEEE80211_BAND_5GHZ);
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE)
++ rtw_cfg80211_rx_mgmt(adapter, freq, 0, frame, frame_len, GFP_ATOMIC);
++#else
++ cfg80211_rx_action(adapter->pnetdev, freq, frame, frame_len, GFP_ATOMIC);
++#endif
++
++}
++
++#ifdef CONFIG_P2P
++void rtw_cfg80211_issue_p2p_provision_request(_adapter *padapter, const u8 *buf, size_t len)
++{
++ u16 wps_devicepassword_id = 0x0000;
++ uint wps_devicepassword_id_len = 0;
++ u8 wpsie[ 255 ] = { 0x00 }, p2p_ie[ 255 ] = { 0x00 };
++ uint p2p_ielen = 0;
++ uint wpsielen = 0;
++ u32 devinfo_contentlen = 0;
++ u8 devinfo_content[64] = { 0x00 };
++ u16 capability = 0;
++ uint capability_len = 0;
++
++ unsigned char category = RTW_WLAN_CATEGORY_PUBLIC;
++ u8 action = P2P_PUB_ACTION_ACTION;
++ u8 dialogToken = 1;
++ u32 p2poui = cpu_to_be32(P2POUI);
++ u8 oui_subtype = P2P_PROVISION_DISC_REQ;
++ u32 p2pielen = 0;
++#ifdef CONFIG_WFD
++ u32 wfdielen = 0;
++#endif //CONFIG_WFD
++
++ struct xmit_frame *pmgntframe;
++ struct pkt_attrib *pattrib;
++ unsigned char *pframe;
++ struct rtw_ieee80211_hdr *pwlanhdr;
++ unsigned short *fctrl;
++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++
++ struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
++ u8 *frame_body = (unsigned char *)(buf + sizeof(struct rtw_ieee80211_hdr_3addr));
++ size_t frame_body_len = len - sizeof(struct rtw_ieee80211_hdr_3addr);
++
++
++ DBG_871X( "[%s] In\n", __FUNCTION__ );
++
++ //prepare for building provision_request frame
++ _rtw_memcpy(pwdinfo->tx_prov_disc_info.peerIFAddr, GetAddr1Ptr(buf), ETH_ALEN);
++ _rtw_memcpy(pwdinfo->tx_prov_disc_info.peerDevAddr, GetAddr1Ptr(buf), ETH_ALEN);
++
++ pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_PUSH_BUTTON;
++
++ rtw_get_wps_ie( frame_body + _PUBLIC_ACTION_IE_OFFSET_, frame_body_len - _PUBLIC_ACTION_IE_OFFSET_, wpsie, &wpsielen);
++ rtw_get_wps_attr_content( wpsie, wpsielen, WPS_ATTR_DEVICE_PWID, (u8*) &wps_devicepassword_id, &wps_devicepassword_id_len);
++ wps_devicepassword_id = be16_to_cpu( wps_devicepassword_id );
++
++ switch(wps_devicepassword_id)
++ {
++ case WPS_DPID_PIN:
++ pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_LABEL;
++ break;
++ case WPS_DPID_USER_SPEC:
++ pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_DISPLYA;
++ break;
++ case WPS_DPID_MACHINE_SPEC:
++ break;
++ case WPS_DPID_REKEY:
++ break;
++ case WPS_DPID_PBC:
++ pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_PUSH_BUTTON;
++ break;
++ case WPS_DPID_REGISTRAR_SPEC:
++ pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_KEYPAD;
++ break;
++ default:
++ break;
++ }
++
++
++ if ( rtw_get_p2p_ie( frame_body + _PUBLIC_ACTION_IE_OFFSET_, frame_body_len - _PUBLIC_ACTION_IE_OFFSET_, p2p_ie, &p2p_ielen ) )
++ {
++
++ rtw_get_p2p_attr_content( p2p_ie, p2p_ielen, P2P_ATTR_DEVICE_INFO, devinfo_content, &devinfo_contentlen);
++ rtw_get_p2p_attr_content( p2p_ie, p2p_ielen, P2P_ATTR_CAPABILITY, (u8*)&capability, &capability_len);
++
++ }
++
++
++ //start to build provision_request frame
++ _rtw_memset(wpsie, 0, sizeof(wpsie));
++ _rtw_memset(p2p_ie, 0, sizeof(p2p_ie));
++ p2p_ielen = 0;
++
++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL)
++ {
++ return;
++ }
++
++
++ //update attribute
++ pattrib = &pmgntframe->attrib;
++ update_mgntframe_attrib(padapter, pattrib);
++
++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++ fctrl = &(pwlanhdr->frame_ctl);
++ *(fctrl) = 0;
++
++ _rtw_memcpy(pwlanhdr->addr1, pwdinfo->tx_prov_disc_info.peerDevAddr, ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN);
++ _rtw_memcpy(pwlanhdr->addr3, pwdinfo->tx_prov_disc_info.peerDevAddr, ETH_ALEN);
++
++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
++ pmlmeext->mgnt_seq++;
++ SetFrameSubType(pframe, WIFI_ACTION);
++
++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
++ pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++
++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
++ pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));
++ pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen));
++ pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen));
++ pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen));
++
++
++ //build_prov_disc_request_p2p_ie
++ // P2P OUI
++ p2pielen = 0;
++ p2p_ie[ p2pielen++ ] = 0x50;
++ p2p_ie[ p2pielen++ ] = 0x6F;
++ p2p_ie[ p2pielen++ ] = 0x9A;
++ p2p_ie[ p2pielen++ ] = 0x09; // WFA P2P v1.0
++
++ // Commented by Albert 20110301
++ // According to the P2P Specification, the provision discovery request frame should contain 3 P2P attributes
++ // 1. P2P Capability
++ // 2. Device Info
++ // 3. Group ID ( When joining an operating P2P Group )
++
++ // P2P Capability ATTR
++ // Type:
++ p2p_ie[ p2pielen++ ] = P2P_ATTR_CAPABILITY;
++
++ // Length:
++ //*(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0002 );
++ RTW_PUT_LE16(p2p_ie + p2pielen, 0x0002);
++ p2pielen += 2;
++
++ // Value:
++ // Device Capability Bitmap, 1 byte
++ // Group Capability Bitmap, 1 byte
++ _rtw_memcpy(p2p_ie + p2pielen, &capability, 2);
++ p2pielen += 2;
++
++
++ // Device Info ATTR
++ // Type:
++ p2p_ie[ p2pielen++ ] = P2P_ATTR_DEVICE_INFO;
++
++ // Length:
++ // 21 -> P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes)
++ // + NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes)
++ //*(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 21 + pwdinfo->device_name_len );
++ RTW_PUT_LE16(p2p_ie + p2pielen, devinfo_contentlen);
++ p2pielen += 2;
++
++ // Value:
++ _rtw_memcpy(p2p_ie + p2pielen, devinfo_content, devinfo_contentlen);
++ p2pielen += devinfo_contentlen;
++
++
++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2p_ie, &p2p_ielen);
++ //p2pielen = build_prov_disc_request_p2p_ie( pwdinfo, pframe, NULL, 0, pwdinfo->tx_prov_disc_info.peerDevAddr);
++ //pframe += p2pielen;
++ pattrib->pktlen += p2p_ielen;
++
++ wpsielen = 0;
++ // WPS OUI
++ *(u32*) ( wpsie ) = cpu_to_be32( WPSOUI );
++ wpsielen += 4;
++
++ // WPS version
++ // Type:
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_VER1 );
++ wpsielen += 2;
++
++ // Length:
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0001 );
++ wpsielen += 2;
++
++ // Value:
++ wpsie[wpsielen++] = WPS_VERSION_1; // Version 1.0
++
++ // Config Method
++ // Type:
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_CONF_METHOD );
++ wpsielen += 2;
++
++ // Length:
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0002 );
++ wpsielen += 2;
++
++ // Value:
++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( pwdinfo->tx_prov_disc_info.wps_config_method_request );
++ wpsielen += 2;
++
++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen );
++
++
++#ifdef CONFIG_WFD
++ wfdielen = build_provdisc_req_wfd_ie(pwdinfo, pframe);
++ pframe += wfdielen;
++ pattrib->pktlen += wfdielen;
++#endif //CONFIG_WFD
++
++ pattrib->last_txcmdsz = pattrib->pktlen;
++
++ //dump_mgntframe(padapter, pmgntframe);
++ if (dump_mgntframe_and_wait_ack(padapter, pmgntframe) != _SUCCESS)
++ DBG_8192C("%s, ack to\n", __func__);
++
++ //if(wps_devicepassword_id == WPS_DPID_REGISTRAR_SPEC)
++ //{
++ // DBG_8192C("waiting for p2p peer key-in PIN CODE\n");
++ // rtw_msleep_os(15000); // 15 sec for key in PIN CODE, workaround for GS2 before issuing Nego Req.
++ //}
++
++}
++
++static s32 cfg80211_rtw_remain_on_channel(struct wiphy *wiphy,
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,6,0))
++ struct wireless_dev *wdev,
++#else
++ struct net_device *ndev,
++#endif
++ struct ieee80211_channel * channel,
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,8,0))
++ enum nl80211_channel_type channel_type,
++#endif
++ unsigned int duration, u64 *cookie)
++{
++ s32 err = 0;
++ _adapter *padapter = wiphy_to_adapter(wiphy);
++ struct rtw_wdev_priv *pwdev_priv = wdev_to_priv(padapter->rtw_wdev);
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct wifidirect_info *pwdinfo = &padapter->wdinfo;
++ struct cfg80211_wifidirect_info *pcfg80211_wdinfo = &padapter->cfg80211_wdinfo;
++ u8 remain_ch = (u8) ieee80211_frequency_to_channel(channel->center_freq);
++ u8 ready_on_channel = _FALSE;
++
++ DBG_871X(FUNC_ADPT_FMT" ch:%u duration:%d\n", FUNC_ADPT_ARG(padapter), remain_ch, duration);
++
++ if(pcfg80211_wdinfo->is_ro_ch == _TRUE)
++ {
++ DBG_8192C("%s, cancel ro ch timer\n", __func__);
++
++ _cancel_timer_ex(&padapter->cfg80211_wdinfo.remain_on_ch_timer);
++
++#ifdef CONFIG_CONCURRENT_MODE
++ ATOMIC_SET(&pwdev_priv->ro_ch_to, 1);
++#endif //CONFIG_CONCURRENT_MODE
++
++ p2p_protocol_wk_hdl(padapter, P2P_RO_CH_WK);
++ }
++
++ pcfg80211_wdinfo->is_ro_ch = _TRUE;
++
++ if(_FAIL == rtw_pwr_wakeup(padapter)) {
++ err = -EFAULT;
++ goto exit;
++ }
++
++ _rtw_memcpy(&pcfg80211_wdinfo->remain_on_ch_channel, channel, sizeof(struct ieee80211_channel));
++ #if (LINUX_VERSION_CODE < KERNEL_VERSION(3,8,0))
++ pcfg80211_wdinfo->remain_on_ch_type= channel_type;
++ #endif
++ pcfg80211_wdinfo->remain_on_ch_cookie= *cookie;
++
++ rtw_scan_abort(padapter);
++#ifdef CONFIG_CONCURRENT_MODE
++ if(rtw_buddy_adapter_up(padapter))
++ rtw_scan_abort(padapter->pbuddy_adapter);
++#endif //CONFIG_CONCURRENT_MODE
++
++ //if(!rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT) && !rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO))
++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
++ {
++ rtw_p2p_enable(padapter, P2P_ROLE_DEVICE);
++ wdev_to_priv(padapter->rtw_wdev)->p2p_enabled = _TRUE;
++ }
++ else
++ {
++ rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo));
++#ifdef CONFIG_DEBUG_CFG80211
++ DBG_8192C("%s, role=%d, p2p_state=%d\n", __func__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo));
++#endif
++ }
++
++
++ rtw_p2p_set_state(pwdinfo, P2P_STATE_LISTEN);
++
++
++ if(duration < 400)
++ duration = duration*3;//extend from exper.
++
++
++#ifdef CONFIG_CONCURRENT_MODE
++ if(check_buddy_fwstate(padapter, _FW_LINKED) &&
++ (duration<pwdinfo->ext_listen_interval))
++ {
++ duration = duration + pwdinfo->ext_listen_interval;
++ }
++#endif
++
++ pcfg80211_wdinfo->restore_channel = rtw_get_oper_ch(padapter);
++
++ if(rtw_ch_set_search_ch(pmlmeext->channel_set, remain_ch) >= 0) {
++#ifdef CONFIG_CONCURRENT_MODE
++ if ( check_buddy_fwstate(padapter, _FW_LINKED ) )
++ {
++ PADAPTER pbuddy_adapter = padapter->pbuddy_adapter;
++ struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv;
++
++ if(remain_ch != pbuddy_mlmeext->cur_channel)
++ {
++ if(ATOMIC_READ(&pwdev_priv->switch_ch_to)==1 ||
++ (remain_ch != pmlmeext->cur_channel))
++ {
++ DBG_8192C("%s, issue nulldata pwrbit=1\n", __func__);
++ issue_nulldata(padapter->pbuddy_adapter, NULL, 1, 3, 500);
++
++ ATOMIC_SET(&pwdev_priv->switch_ch_to, 0);
++
++ DBG_8192C("%s, set switch ch timer, duration=%d\n", __func__, duration-pwdinfo->ext_listen_interval);
++ _set_timer(&pwdinfo->ap_p2p_switch_timer, duration-pwdinfo->ext_listen_interval);
++ }
++ }
++
++ ready_on_channel = _TRUE;
++ //pmlmeext->cur_channel = remain_ch;
++ //set_channel_bwmode(padapter, remain_ch, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HT_CHANNEL_WIDTH_20);
++ }else
++#endif //CONFIG_CONCURRENT_MODE
++ if(remain_ch != pmlmeext->cur_channel )
++ {
++ ready_on_channel = _TRUE;
++ //pmlmeext->cur_channel = remain_ch;
++ //set_channel_bwmode(padapter, remain_ch, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HT_CHANNEL_WIDTH_20);
++ }
++ } else {
++ DBG_871X("%s remain_ch:%u not in channel plan!!!!\n", __FUNCTION__, remain_ch);
++ }
++
++
++ //call this after other things have been done
++#ifdef CONFIG_CONCURRENT_MODE
++ if(ATOMIC_READ(&pwdev_priv->ro_ch_to)==1 ||
++ (remain_ch != pmlmeext->cur_channel))
++ {
++ u8 co_channel = 0xff;
++ ATOMIC_SET(&pwdev_priv->ro_ch_to, 0);
++#endif
++
++ if(ready_on_channel == _TRUE)
++ {
++ if ( !check_fwstate(&padapter->mlmepriv, _FW_LINKED ) )
++ pmlmeext->cur_channel = remain_ch;
++
++#ifdef CONFIG_CONCURRENT_MODE
++ co_channel = rtw_get_oper_ch(padapter);
++
++ if(co_channel !=remain_ch)
++#endif
++ {
++ if (!padapter->mlmepriv.LinkDetectInfo.bBusyTraffic)
++ set_channel_bwmode(padapter, remain_ch, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HT_CHANNEL_WIDTH_20);
++ }
++ }
++ DBG_8192C("%s, set ro ch timer, duration=%d\n", __func__, duration);
++ _set_timer( &pcfg80211_wdinfo->remain_on_ch_timer, duration);
++
++#ifdef CONFIG_CONCURRENT_MODE
++ }
++#endif
++
++ rtw_cfg80211_ready_on_channel(padapter, *cookie, channel, channel_type, duration, GFP_KERNEL);
++
++exit:
++ if (err)
++ pcfg80211_wdinfo->is_ro_ch = _FALSE;
++
++ return err;
++}
++
++static s32 cfg80211_rtw_cancel_remain_on_channel(struct wiphy *wiphy,
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,6,0))
++ struct wireless_dev *wdev,
++#else
++ struct net_device *ndev,
++#endif
++ u64 cookie)
++{
++ s32 err = 0;
++ _adapter *padapter = wiphy_to_adapter(wiphy);
++ struct rtw_wdev_priv *pwdev_priv = wdev_to_priv(padapter->rtw_wdev);
++ struct wifidirect_info *pwdinfo = &padapter->wdinfo;
++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
++ struct cfg80211_wifidirect_info *pcfg80211_wdinfo = &padapter->cfg80211_wdinfo;
++
++ DBG_871X(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
++
++ if (pcfg80211_wdinfo->is_ro_ch == _TRUE) {
++ DBG_8192C("%s, cancel ro ch timer\n", __func__);
++ _cancel_timer_ex(&padapter->cfg80211_wdinfo.remain_on_ch_timer);
++ #ifdef CONFIG_CONCURRENT_MODE
++ ATOMIC_SET(&pwdev_priv->ro_ch_to, 1);
++ #endif
++ p2p_protocol_wk_hdl(padapter, P2P_RO_CH_WK);
++ }
++
++ #if 0
++ // Disable P2P Listen State
++ if(!rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT) && !rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO))
++ {
++ if(!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
++ {
++ _cancel_timer_ex( &pwdinfo->find_phase_timer );
++ _cancel_timer_ex( &pwdinfo->restore_p2p_state_timer );
++ _cancel_timer_ex( &pwdinfo->pre_tx_scan_timer);
++
++ rtw_p2p_set_state(pwdinfo, P2P_STATE_NONE);
++ _rtw_memset(pwdinfo, 0x00, sizeof(struct wifidirect_info));
++ }
++ }
++ else
++ #endif
++ {
++ rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo));
++#ifdef CONFIG_DEBUG_CFG80211
++ DBG_8192C("%s, role=%d, p2p_state=%d\n", __func__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo));
++#endif
++ }
++ pcfg80211_wdinfo->is_ro_ch = _FALSE;
++
++ return err;
++}
++
++#endif //CONFIG_P2P
++
++static int _cfg80211_rtw_mgmt_tx(_adapter *padapter, u8 tx_ch, const u8 *buf, size_t len)
++{
++ struct xmit_frame *pmgntframe;
++ struct pkt_attrib *pattrib;
++ unsigned char *pframe;
++ int ret = _FAIL;
++ bool ack = _TRUE;
++ struct rtw_ieee80211_hdr *pwlanhdr;
++ struct rtw_wdev_priv *pwdev_priv = wdev_to_priv(padapter->rtw_wdev);
++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++ struct wifidirect_info *pwdinfo = &padapter->wdinfo;
++ //struct cfg80211_wifidirect_info *pcfg80211_wdinfo = &padapter->cfg80211_wdinfo;
++
++ if(_FAIL == rtw_pwr_wakeup(padapter)) {
++ ret = -EFAULT;
++ goto exit;
++ }
++
++ rtw_set_scan_deny(padapter, 1000);
++
++ rtw_scan_abort(padapter);
++ #ifdef CONFIG_CONCURRENT_MODE
++ if(rtw_buddy_adapter_up(padapter))
++ rtw_scan_abort(padapter->pbuddy_adapter);
++ #endif /* CONFIG_CONCURRENT_MODE */
++
++ if (padapter->cfg80211_wdinfo.is_ro_ch == _TRUE) {
++ //DBG_8192C("%s, cancel ro ch timer\n", __func__);
++ //_cancel_timer_ex(&padapter->cfg80211_wdinfo.remain_on_ch_timer);
++ //padapter->cfg80211_wdinfo.is_ro_ch = _FALSE;
++ #ifdef CONFIG_CONCURRENT_MODE
++ if (!check_fwstate(&padapter->mlmepriv, _FW_LINKED ))
++ {
++ DBG_8192C("%s, extend ro ch time\n", __func__);
++ _set_timer( &padapter->cfg80211_wdinfo.remain_on_ch_timer, pwdinfo->ext_listen_period);
++ }
++ #endif //CONFIG_CONCURRENT_MODE
++ }
++
++#ifdef CONFIG_CONCURRENT_MODE
++ if (check_buddy_fwstate(padapter, _FW_LINKED )) {
++ u8 co_channel=0xff;
++ PADAPTER pbuddy_adapter = padapter->pbuddy_adapter;
++ struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv;
++
++ co_channel = rtw_get_oper_ch(padapter);
++
++ if (tx_ch != pbuddy_mlmeext->cur_channel) {
++
++ u16 ext_listen_period;
++
++ if (ATOMIC_READ(&pwdev_priv->switch_ch_to)==1) {
++ DBG_8192C("%s, issue nulldata pwrbit=1\n", __func__);
++ issue_nulldata(padapter->pbuddy_adapter, NULL, 1, 3, 500);
++
++ ATOMIC_SET(&pwdev_priv->switch_ch_to, 0);
++
++ //DBG_8192C("%s, set switch ch timer, period=%d\n", __func__, pwdinfo->ext_listen_period);
++ //_set_timer(&pwdinfo->ap_p2p_switch_timer, pwdinfo->ext_listen_period);
++ }
++
++ if (check_fwstate(&padapter->mlmepriv, _FW_LINKED ))
++ {
++ ext_listen_period = 500;// 500ms
++ }
++ else
++ {
++ ext_listen_period = pwdinfo->ext_listen_period;
++ }
++
++ DBG_8192C("%s, set switch ch timer, period=%d\n", __func__, ext_listen_period);
++ _set_timer(&pwdinfo->ap_p2p_switch_timer, ext_listen_period);
++
++ }
++
++ if (!check_fwstate(&padapter->mlmepriv, _FW_LINKED ))
++ pmlmeext->cur_channel = tx_ch;
++
++ if (tx_ch != co_channel)
++ set_channel_bwmode(padapter, tx_ch, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HT_CHANNEL_WIDTH_20);
++ }else
++#endif //CONFIG_CONCURRENT_MODE
++ //if (tx_ch != pmlmeext->cur_channel) {
++ if(tx_ch != rtw_get_oper_ch(padapter)) {
++ if (!check_fwstate(&padapter->mlmepriv, _FW_LINKED ))
++ pmlmeext->cur_channel = tx_ch;
++ set_channel_bwmode(padapter, tx_ch, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HT_CHANNEL_WIDTH_20);
++ }
++
++ //starting alloc mgmt frame to dump it
++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL)
++ {
++ //ret = -ENOMEM;
++ ret = _FAIL;
++ goto exit;
++ }
++
++ //update attribute
++ pattrib = &pmgntframe->attrib;
++ update_mgntframe_attrib(padapter, pattrib);
++ pattrib->retry_ctrl = _FALSE;
++
++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++
++ _rtw_memcpy(pframe, (void*)buf, len);
++ pattrib->pktlen = len;
++
++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++ //update seq number
++ pmlmeext->mgnt_seq = GetSequence(pwlanhdr);
++ pattrib->seqnum = pmlmeext->mgnt_seq;
++ pmlmeext->mgnt_seq++;
++
++#ifdef CONFIG_WFD
++ {
++ struct wifi_display_info *pwfd_info;
++
++ pwfd_info = padapter->wdinfo.wfd_info;
++
++ if ( _TRUE == pwfd_info->wfd_enable )
++ {
++ rtw_append_wfd_ie( padapter, pframe, &pattrib->pktlen );
++ }
++ }
++#endif // CONFIG_WFD
++
++ pattrib->last_txcmdsz = pattrib->pktlen;
++
++ if (dump_mgntframe_and_wait_ack(padapter, pmgntframe) != _SUCCESS)
++ {
++ ack = _FALSE;
++ ret = _FAIL;
++
++ #ifdef CONFIG_DEBUG_CFG80211
++ DBG_8192C("%s, ack == _FAIL\n", __func__);
++ #endif
++ }
++ else
++ {
++ #ifdef CONFIG_DEBUG_CFG80211
++ DBG_8192C("%s, ack=%d, ok!\n", __func__, ack);
++ #endif
++ ret = _SUCCESS;
++ }
++
++exit:
++
++ #ifdef CONFIG_DEBUG_CFG80211
++ DBG_8192C("%s, ret=%d\n", __func__, ret);
++ #endif
++
++ return ret;
++
++}
++
++static int cfg80211_rtw_mgmt_tx(struct wiphy *wiphy,
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,6,0))
++ struct wireless_dev *wdev,
++#else
++ struct net_device *ndev,
++#endif
++ struct ieee80211_channel *chan,
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38)) || defined(COMPAT_KERNEL_RELEASE)
++ bool offchan,
++#endif
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,8,0))
++ enum nl80211_channel_type channel_type,
++ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE)
++ bool channel_type_valid,
++ #endif
++#endif
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38)) || defined(COMPAT_KERNEL_RELEASE)
++ unsigned int wait,
++#endif
++ const u8 *buf, size_t len,
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,0))
++ bool no_cck,
++#endif
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,3,0))
++ bool dont_wait_for_ack,
++#endif
++ u64 *cookie)
++{
++ _adapter *padapter = (_adapter *)wiphy_to_adapter(wiphy);
++ struct rtw_wdev_priv *pwdev_priv = wdev_to_priv(padapter->rtw_wdev);
++ int ret = 0;
++ int tx_ret;
++ u32 dump_limit = RTW_MAX_MGMT_TX_CNT;
++ u32 dump_cnt = 0;
++ bool ack = _TRUE;
++ u8 tx_ch = (u8)ieee80211_frequency_to_channel(chan->center_freq);
++ u8 category, action;
++ int type = (-1);
++ u32 start = rtw_get_current_time();
++
++ /* cookie generation */
++ *cookie = (unsigned long) buf;
++
++#ifdef CONFIG_DEBUG_CFG80211
++ DBG_871X(FUNC_ADPT_FMT" len=%zu, ch=%d"
++ #if (LINUX_VERSION_CODE < KERNEL_VERSION(3,8,0))
++ ", ch_type=%d"
++ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE)
++ ", channel_type_valid=%d"
++ #endif
++ #endif
++ "\n", FUNC_ADPT_ARG(padapter),
++ len, tx_ch
++ #if (LINUX_VERSION_CODE < KERNEL_VERSION(3,8,0))
++ , channel_type
++ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE)
++ , channel_type_valid
++ #endif
++ #endif
++ );
++#endif /* CONFIG_DEBUG_CFG80211 */
++
++ /* indicate ack before issue frame to avoid racing with rsp frame */
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE)
++ rtw_cfg80211_mgmt_tx_status(padapter, *cookie, buf, len, ack, GFP_KERNEL);
++#elif (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,34) && LINUX_VERSION_CODE<=KERNEL_VERSION(2,6,35))
++ cfg80211_action_tx_status(ndev, *cookie, buf, len, ack, GFP_KERNEL);
++#endif
++
++ if (rtw_action_frame_parse(buf, len, &category, &action) == _FALSE) {
++ DBG_8192C(FUNC_ADPT_FMT" frame_control:0x%x\n", FUNC_ADPT_ARG(padapter),
++ le16_to_cpu(((struct rtw_ieee80211_hdr_3addr *)buf)->frame_ctl));
++ goto exit;
++ }
++
++ DBG_8192C("RTW_Tx:tx_ch=%d, da="MAC_FMT"\n", tx_ch, MAC_ARG(GetAddr1Ptr(buf)));
++ #ifdef CONFIG_P2P
++ if((type = rtw_p2p_check_frames(padapter, buf, len, _TRUE)) >= 0) {
++ goto dump;
++ }
++ #endif
++ if (category == RTW_WLAN_CATEGORY_PUBLIC)
++ DBG_871X("RTW_Tx:%s\n", action_public_str(action));
++ else
++ DBG_871X("RTW_Tx:category(%u), action(%u)\n", category, action);
++
++dump:
++ do {
++ dump_cnt++;
++ tx_ret = _cfg80211_rtw_mgmt_tx(padapter, tx_ch, buf, len);
++ } while (dump_cnt < dump_limit && tx_ret != _SUCCESS);
++
++ if (tx_ret != _SUCCESS || dump_cnt > 1) {
++ DBG_871X(FUNC_ADPT_FMT" %s (%d/%d) in %d ms\n", FUNC_ADPT_ARG(padapter),
++ tx_ret==_SUCCESS?"OK":"FAIL", dump_cnt, dump_limit, rtw_get_passing_time_ms(start));
++ }
++
++ switch (type) {
++ case P2P_GO_NEGO_CONF:
++ rtw_clear_scan_deny(padapter);
++ break;
++ case P2P_INVIT_RESP:
++ if (pwdev_priv->invit_info.flags & BIT(0)
++ && pwdev_priv->invit_info.status == 0)
++ {
++ DBG_871X(FUNC_ADPT_FMT" agree with invitation of persistent group\n",
++ FUNC_ADPT_ARG(padapter));
++ rtw_set_scan_deny(padapter, 5000);
++ rtw_pwr_wakeup_ex(padapter, 5000);
++ rtw_clear_scan_deny(padapter);
++ }
++ break;
++ }
++
++exit:
++ return ret;
++}
++
++static void cfg80211_rtw_mgmt_frame_register(struct wiphy *wiphy,
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
++ struct wireless_dev *wdev,
++#else
++ struct net_device *ndev,
++#endif
++ u16 frame_type, bool reg)
++{
++ _adapter *adapter = wiphy_to_adapter(wiphy);
++
++#ifdef CONFIG_DEBUG_CFG80211
++ DBG_871X(FUNC_ADPT_FMT" frame_type:%x, reg:%d\n", FUNC_ADPT_ARG(adapter),
++ frame_type, reg);
++#endif
++
++ if (frame_type != (IEEE80211_FTYPE_MGMT | IEEE80211_STYPE_PROBE_REQ))
++ return;
++
++ return;
++}
++
++static int rtw_cfg80211_set_beacon_wpsp2pie(struct net_device *ndev, char *buf, int len)
++{
++ int ret = 0;
++ uint wps_ielen = 0;
++ u8 *wps_ie;
++ u32 p2p_ielen = 0;
++ u8 wps_oui[8]={0x0,0x50,0xf2,0x04};
++ u8 *p2p_ie;
++ u32 wfd_ielen = 0;
++ u8 *wfd_ie;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++
++ DBG_871X(FUNC_NDEV_FMT" ielen=%d\n", FUNC_NDEV_ARG(ndev), len);
++
++ if(len>0)
++ {
++ if((wps_ie = rtw_get_wps_ie(buf, len, NULL, &wps_ielen)))
++ {
++ #ifdef CONFIG_DEBUG_CFG80211
++ DBG_8192C("bcn_wps_ielen=%d\n", wps_ielen);
++ #endif
++
++ if(pmlmepriv->wps_beacon_ie)
++ {
++ u32 free_len = pmlmepriv->wps_beacon_ie_len;
++ pmlmepriv->wps_beacon_ie_len = 0;
++ rtw_mfree(pmlmepriv->wps_beacon_ie, free_len);
++ pmlmepriv->wps_beacon_ie = NULL;
++ }
++
++ pmlmepriv->wps_beacon_ie = rtw_malloc(wps_ielen);
++ if ( pmlmepriv->wps_beacon_ie == NULL) {
++ DBG_8192C("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__);
++ return -EINVAL;
++
++ }
++
++ _rtw_memcpy(pmlmepriv->wps_beacon_ie, wps_ie, wps_ielen);
++ pmlmepriv->wps_beacon_ie_len = wps_ielen;
++
++ update_beacon(padapter, _VENDOR_SPECIFIC_IE_, wps_oui, _TRUE);
++
++ }
++
++ //buf += wps_ielen;
++ //len -= wps_ielen;
++
++ #ifdef CONFIG_P2P
++ if((p2p_ie=rtw_get_p2p_ie(buf, len, NULL, &p2p_ielen)))
++ {
++ #ifdef CONFIG_DEBUG_CFG80211
++ DBG_8192C("bcn_p2p_ielen=%d\n", p2p_ielen);
++ #endif
++
++ if(pmlmepriv->p2p_beacon_ie)
++ {
++ u32 free_len = pmlmepriv->p2p_beacon_ie_len;
++ pmlmepriv->p2p_beacon_ie_len = 0;
++ rtw_mfree(pmlmepriv->p2p_beacon_ie, free_len);
++ pmlmepriv->p2p_beacon_ie = NULL;
++ }
++
++ pmlmepriv->p2p_beacon_ie = rtw_malloc(p2p_ielen);
++ if ( pmlmepriv->p2p_beacon_ie == NULL) {
++ DBG_8192C("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__);
++ return -EINVAL;
++
++ }
++
++ _rtw_memcpy(pmlmepriv->p2p_beacon_ie, p2p_ie, p2p_ielen);
++ pmlmepriv->p2p_beacon_ie_len = p2p_ielen;
++
++ }
++ #endif //CONFIG_P2P
++
++ //buf += p2p_ielen;
++ //len -= p2p_ielen;
++
++ #ifdef CONFIG_WFD
++ if(rtw_get_wfd_ie(buf, len, NULL, &wfd_ielen))
++ {
++ #ifdef CONFIG_DEBUG_CFG80211
++ DBG_8192C("bcn_wfd_ielen=%d\n", wfd_ielen);
++ #endif
++
++ if(pmlmepriv->wfd_beacon_ie)
++ {
++ u32 free_len = pmlmepriv->wfd_beacon_ie_len;
++ pmlmepriv->wfd_beacon_ie_len = 0;
++ rtw_mfree(pmlmepriv->wfd_beacon_ie, free_len);
++ pmlmepriv->wfd_beacon_ie = NULL;
++ }
++
++ pmlmepriv->wfd_beacon_ie = rtw_malloc(wfd_ielen);
++ if ( pmlmepriv->wfd_beacon_ie == NULL) {
++ DBG_8192C("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__);
++ return -EINVAL;
++
++ }
++ rtw_get_wfd_ie(buf, len, pmlmepriv->wfd_beacon_ie, &pmlmepriv->wfd_beacon_ie_len);
++ }
++ #endif //CONFIG_WFD
++
++ pmlmeext->bstart_bss = _TRUE;
++
++ }
++
++ return ret;
++
++}
++
++static int rtw_cfg80211_set_probe_resp_wpsp2pie(struct net_device *net, char *buf, int len)
++{
++ int ret = 0;
++ uint wps_ielen = 0;
++ u8 *wps_ie;
++ u32 p2p_ielen = 0;
++ u8 *p2p_ie;
++ u32 wfd_ielen = 0;
++ u8 *wfd_ie;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(net);
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++
++#ifdef CONFIG_DEBUG_CFG80211
++ DBG_8192C("%s, ielen=%d\n", __func__, len);
++#endif
++
++ if(len>0)
++ {
++ if((wps_ie = rtw_get_wps_ie(buf, len, NULL, &wps_ielen)))
++ {
++ uint attr_contentlen = 0;
++ u16 uconfig_method, *puconfig_method = NULL;
++
++ #ifdef CONFIG_DEBUG_CFG80211
++ DBG_8192C("probe_resp_wps_ielen=%d\n", wps_ielen);
++ #endif
++
++ if(check_fwstate(pmlmepriv, WIFI_UNDER_WPS))
++ {
++ u8 sr = 0;
++ rtw_get_wps_attr_content(wps_ie, wps_ielen, WPS_ATTR_SELECTED_REGISTRAR, (u8*)(&sr), NULL);
++
++ if (sr != 0)
++ {
++ DBG_871X("%s, got sr\n", __func__);
++ }
++ else
++ {
++ DBG_8192C("GO mode process WPS under site-survey, sr no set\n");
++ return ret;
++ }
++ }
++
++ if(pmlmepriv->wps_probe_resp_ie)
++ {
++ u32 free_len = pmlmepriv->wps_probe_resp_ie_len;
++ pmlmepriv->wps_probe_resp_ie_len = 0;
++ rtw_mfree(pmlmepriv->wps_probe_resp_ie, free_len);
++ pmlmepriv->wps_probe_resp_ie = NULL;
++ }
++
++ pmlmepriv->wps_probe_resp_ie = rtw_malloc(wps_ielen);
++ if ( pmlmepriv->wps_probe_resp_ie == NULL) {
++ DBG_8192C("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__);
++ return -EINVAL;
++
++ }
++
++ //add PUSH_BUTTON config_method by driver self in wpsie of probe_resp at GO Mode
++ if ( (puconfig_method = (u16*)rtw_get_wps_attr_content( wps_ie, wps_ielen, WPS_ATTR_CONF_METHOD , NULL, &attr_contentlen)) != NULL )
++ {
++ #ifdef CONFIG_DEBUG_CFG80211
++ //printk("config_method in wpsie of probe_resp = 0x%x\n", be16_to_cpu(*puconfig_method));
++ #endif
++
++ uconfig_method = WPS_CM_PUSH_BUTTON;
++ uconfig_method = cpu_to_be16( uconfig_method );
++
++ *puconfig_method |= uconfig_method;
++ }
++
++ _rtw_memcpy(pmlmepriv->wps_probe_resp_ie, wps_ie, wps_ielen);
++ pmlmepriv->wps_probe_resp_ie_len = wps_ielen;
++
++ }
++
++ //buf += wps_ielen;
++ //len -= wps_ielen;
++
++ #ifdef CONFIG_P2P
++ if((p2p_ie=rtw_get_p2p_ie(buf, len, NULL, &p2p_ielen)))
++ {
++ u8 is_GO = _FALSE;
++ u32 attr_contentlen = 0;
++ u16 cap_attr=0;
++
++ #ifdef CONFIG_DEBUG_CFG80211
++ DBG_8192C("probe_resp_p2p_ielen=%d\n", p2p_ielen);
++ #endif
++
++ //Check P2P Capability ATTR
++ if( rtw_get_p2p_attr_content( p2p_ie, p2p_ielen, P2P_ATTR_CAPABILITY, (u8*)&cap_attr, (uint*) &attr_contentlen) )
++ {
++ u8 grp_cap=0;
++ //DBG_8192C( "[%s] Got P2P Capability Attr!!\n", __FUNCTION__ );
++ cap_attr = le16_to_cpu(cap_attr);
++ grp_cap = (u8)((cap_attr >> 8)&0xff);
++
++ is_GO = (grp_cap&BIT(0)) ? _TRUE:_FALSE;
++
++ if(is_GO)
++ DBG_8192C("Got P2P Capability Attr, grp_cap=0x%x, is_GO\n", grp_cap);
++ }
++
++
++ if(is_GO == _FALSE)
++ {
++ if(pmlmepriv->p2p_probe_resp_ie)
++ {
++ u32 free_len = pmlmepriv->p2p_probe_resp_ie_len;
++ pmlmepriv->p2p_probe_resp_ie_len = 0;
++ rtw_mfree(pmlmepriv->p2p_probe_resp_ie, free_len);
++ pmlmepriv->p2p_probe_resp_ie = NULL;
++ }
++
++ pmlmepriv->p2p_probe_resp_ie = rtw_malloc(p2p_ielen);
++ if ( pmlmepriv->p2p_probe_resp_ie == NULL) {
++ DBG_8192C("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__);
++ return -EINVAL;
++
++ }
++ _rtw_memcpy(pmlmepriv->p2p_probe_resp_ie, p2p_ie, p2p_ielen);
++ pmlmepriv->p2p_probe_resp_ie_len = p2p_ielen;
++ }
++ else
++ {
++ if(pmlmepriv->p2p_go_probe_resp_ie)
++ {
++ u32 free_len = pmlmepriv->p2p_go_probe_resp_ie_len;
++ pmlmepriv->p2p_go_probe_resp_ie_len = 0;
++ rtw_mfree(pmlmepriv->p2p_go_probe_resp_ie, free_len);
++ pmlmepriv->p2p_go_probe_resp_ie = NULL;
++ }
++
++ pmlmepriv->p2p_go_probe_resp_ie = rtw_malloc(p2p_ielen);
++ if ( pmlmepriv->p2p_go_probe_resp_ie == NULL) {
++ DBG_8192C("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__);
++ return -EINVAL;
++
++ }
++ _rtw_memcpy(pmlmepriv->p2p_go_probe_resp_ie, p2p_ie, p2p_ielen);
++ pmlmepriv->p2p_go_probe_resp_ie_len = p2p_ielen;
++ }
++
++ }
++ #endif //CONFIG_P2P
++
++ //buf += p2p_ielen;
++ //len -= p2p_ielen;
++
++ #ifdef CONFIG_WFD
++ if(rtw_get_wfd_ie(buf, len, NULL, &wfd_ielen))
++ {
++ #ifdef CONFIG_DEBUG_CFG80211
++ DBG_8192C("probe_resp_wfd_ielen=%d\n", wfd_ielen);
++ #endif
++
++ if(pmlmepriv->wfd_probe_resp_ie)
++ {
++ u32 free_len = pmlmepriv->wfd_probe_resp_ie_len;
++ pmlmepriv->wfd_probe_resp_ie_len = 0;
++ rtw_mfree(pmlmepriv->wfd_probe_resp_ie, free_len);
++ pmlmepriv->wfd_probe_resp_ie = NULL;
++ }
++
++ pmlmepriv->wfd_probe_resp_ie = rtw_malloc(wfd_ielen);
++ if ( pmlmepriv->wfd_probe_resp_ie == NULL) {
++ DBG_8192C("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__);
++ return -EINVAL;
++
++ }
++ rtw_get_wfd_ie(buf, len, pmlmepriv->wfd_probe_resp_ie, &pmlmepriv->wfd_probe_resp_ie_len);
++ }
++ #endif //CONFIG_WFD
++
++ }
++
++ return ret;
++
++}
++
++static int rtw_cfg80211_set_assoc_resp_wpsp2pie(struct net_device *net, char *buf, int len)
++{
++ int ret = 0;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(net);
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++
++ DBG_8192C("%s, ielen=%d\n", __func__, len);
++
++ if(len>0)
++ {
++ if(pmlmepriv->wps_assoc_resp_ie)
++ {
++ u32 free_len = pmlmepriv->wps_assoc_resp_ie_len;
++ pmlmepriv->wps_assoc_resp_ie_len = 0;
++ rtw_mfree(pmlmepriv->wps_assoc_resp_ie, free_len);
++ pmlmepriv->wps_assoc_resp_ie = NULL;
++ }
++
++ pmlmepriv->wps_assoc_resp_ie = rtw_malloc(len);
++ if ( pmlmepriv->wps_assoc_resp_ie == NULL) {
++ DBG_8192C("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__);
++ return -EINVAL;
++
++ }
++ _rtw_memcpy(pmlmepriv->wps_assoc_resp_ie, buf, len);
++ pmlmepriv->wps_assoc_resp_ie_len = len;
++ }
++
++ return ret;
++
++}
++
++int rtw_cfg80211_set_mgnt_wpsp2pie(struct net_device *net, char *buf, int len,
++ int type)
++{
++ int ret = 0;
++ uint wps_ielen = 0;
++ u32 p2p_ielen = 0;
++
++#ifdef CONFIG_DEBUG_CFG80211
++ DBG_8192C("%s, ielen=%d\n", __func__, len);
++#endif
++
++ if( (rtw_get_wps_ie(buf, len, NULL, &wps_ielen) && (wps_ielen>0))
++ #ifdef CONFIG_P2P
++ || (rtw_get_p2p_ie(buf, len, NULL, &p2p_ielen) && (p2p_ielen>0))
++ #endif
++ )
++ {
++ if (net != NULL)
++ {
++ switch (type)
++ {
++ case 0x1: //BEACON
++ ret = rtw_cfg80211_set_beacon_wpsp2pie(net, buf, len);
++ break;
++ case 0x2: //PROBE_RESP
++ ret = rtw_cfg80211_set_probe_resp_wpsp2pie(net, buf, len);
++ break;
++ case 0x4: //ASSOC_RESP
++ ret = rtw_cfg80211_set_assoc_resp_wpsp2pie(net, buf, len);
++ break;
++ }
++ }
++ }
++
++ return ret;
++
++}
++
++static struct cfg80211_ops rtw_cfg80211_ops = {
++ .change_virtual_intf = cfg80211_rtw_change_iface,
++ .add_key = cfg80211_rtw_add_key,
++ .get_key = cfg80211_rtw_get_key,
++ .del_key = cfg80211_rtw_del_key,
++ .set_default_key = cfg80211_rtw_set_default_key,
++ .get_station = cfg80211_rtw_get_station,
++ .scan = cfg80211_rtw_scan,
++ .set_wiphy_params = cfg80211_rtw_set_wiphy_params,
++ .connect = cfg80211_rtw_connect,
++ .disconnect = cfg80211_rtw_disconnect,
++ .join_ibss = cfg80211_rtw_join_ibss,
++ .leave_ibss = cfg80211_rtw_leave_ibss,
++ .set_tx_power = cfg80211_rtw_set_txpower,
++ .get_tx_power = cfg80211_rtw_get_txpower,
++ .set_power_mgmt = cfg80211_rtw_set_power_mgmt,
++ .set_pmksa = cfg80211_rtw_set_pmksa,
++ .del_pmksa = cfg80211_rtw_del_pmksa,
++ .flush_pmksa = cfg80211_rtw_flush_pmksa,
++
++#ifdef CONFIG_AP_MODE
++ .add_virtual_intf = cfg80211_rtw_add_virtual_intf,
++ .del_virtual_intf = cfg80211_rtw_del_virtual_intf,
++
++ #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 4, 0)) && !defined(COMPAT_KERNEL_RELEASE)
++ .add_beacon = cfg80211_rtw_add_beacon,
++ .set_beacon = cfg80211_rtw_set_beacon,
++ .del_beacon = cfg80211_rtw_del_beacon,
++ #else
++ .start_ap = cfg80211_rtw_start_ap,
++ .change_beacon = cfg80211_rtw_change_beacon,
++ .stop_ap = cfg80211_rtw_stop_ap,
++ #endif
++
++ .add_station = cfg80211_rtw_add_station,
++ .del_station = cfg80211_rtw_del_station,
++ .change_station = cfg80211_rtw_change_station,
++ .dump_station = cfg80211_rtw_dump_station,
++ .change_bss = cfg80211_rtw_change_bss,
++ #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 6, 0))
++ .set_channel = cfg80211_rtw_set_channel,
++ #endif
++ //.auth = cfg80211_rtw_auth,
++ //.assoc = cfg80211_rtw_assoc,
++#endif //CONFIG_AP_MODE
++
++#ifdef CONFIG_P2P
++ .remain_on_channel = cfg80211_rtw_remain_on_channel,
++ .cancel_remain_on_channel = cfg80211_rtw_cancel_remain_on_channel,
++#endif
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE)
++ .mgmt_tx = cfg80211_rtw_mgmt_tx,
++ .mgmt_frame_register = cfg80211_rtw_mgmt_frame_register,
++#elif (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,34) && LINUX_VERSION_CODE<=KERNEL_VERSION(2,6,35))
++ .action = cfg80211_rtw_mgmt_tx,
++#endif
++};
++
++static void rtw_cfg80211_init_ht_capab(struct ieee80211_sta_ht_cap *ht_cap, enum ieee80211_band band, u8 rf_type)
++{
++
++#define MAX_BIT_RATE_40MHZ_MCS15 300 /* Mbps */
++#define MAX_BIT_RATE_40MHZ_MCS7 150 /* Mbps */
++
++ ht_cap->ht_supported = _TRUE;
++
++ ht_cap->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
++ IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20 |
++ IEEE80211_HT_CAP_DSSSCCK40 | IEEE80211_HT_CAP_MAX_AMSDU;
++
++ /*
++ *Maximum length of AMPDU that the STA can receive.
++ *Length = 2 ^ (13 + max_ampdu_length_exp) - 1 (octets)
++ */
++ ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
++
++ /*Minimum MPDU start spacing , */
++ ht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_16;
++
++ ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
++
++ /*
++ *hw->wiphy->bands[IEEE80211_BAND_2GHZ]
++ *base on ant_num
++ *rx_mask: RX mask
++ *if rx_ant =1 rx_mask[0]=0xff;==>MCS0-MCS7
++ *if rx_ant =2 rx_mask[1]=0xff;==>MCS8-MCS15
++ *if rx_ant >=3 rx_mask[2]=0xff;
++ *if BW_40 rx_mask[4]=0x01;
++ *highest supported RX rate
++ */
++ if(rf_type == RF_1T1R)
++ {
++ ht_cap->mcs.rx_mask[0] = 0xFF;
++ ht_cap->mcs.rx_mask[1] = 0x00;
++ ht_cap->mcs.rx_mask[4] = 0x01;
++
++ ht_cap->mcs.rx_highest = MAX_BIT_RATE_40MHZ_MCS7;
++ }
++ else if((rf_type == RF_1T2R) || (rf_type==RF_2T2R))
++ {
++ ht_cap->mcs.rx_mask[0] = 0xFF;
++ ht_cap->mcs.rx_mask[1] = 0xFF;
++ ht_cap->mcs.rx_mask[4] = 0x01;
++
++ ht_cap->mcs.rx_highest = MAX_BIT_RATE_40MHZ_MCS15;
++ }
++ else
++ {
++ DBG_8192C("%s, error rf_type=%d\n", __func__, rf_type);
++ }
++
++}
++
++void rtw_cfg80211_init_wiphy(_adapter *padapter)
++{
++ u8 rf_type;
++ struct ieee80211_supported_band *bands;
++ struct wireless_dev *pwdev = padapter->rtw_wdev;
++ struct wiphy *wiphy = pwdev->wiphy;
++
++ rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));
++
++ DBG_8192C("%s:rf_type=%d\n", __func__, rf_type);
++
++ /* if (padapter->registrypriv.wireless_mode & WIRELESS_11G) */
++ {
++ bands = wiphy->bands[IEEE80211_BAND_2GHZ];
++ if(bands)
++ rtw_cfg80211_init_ht_capab(&bands->ht_cap, IEEE80211_BAND_2GHZ, rf_type);
++ }
++
++ /* if (padapter->registrypriv.wireless_mode & WIRELESS_11A) */
++ {
++ bands = wiphy->bands[IEEE80211_BAND_5GHZ];
++ if(bands)
++ rtw_cfg80211_init_ht_capab(&bands->ht_cap, IEEE80211_BAND_5GHZ, rf_type);
++ }
++}
++
++/*
++struct ieee80211_iface_limit rtw_limits[] = {
++ { .max = 1, .types = BIT(NL80211_IFTYPE_STATION)
++ | BIT(NL80211_IFTYPE_ADHOC)
++#ifdef CONFIG_AP_MODE
++ | BIT(NL80211_IFTYPE_AP)
++#endif
++#if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE))
++ | BIT(NL80211_IFTYPE_P2P_CLIENT)
++ | BIT(NL80211_IFTYPE_P2P_GO)
++#endif
++ },
++ {.max = 1, .types = BIT(NL80211_IFTYPE_MONITOR)},
++};
++
++struct ieee80211_iface_combination rtw_combinations = {
++ .limits = rtw_limits,
++ .n_limits = ARRAY_SIZE(rtw_limits),
++ .max_interfaces = 2,
++ .num_different_channels = 1,
++};
++*/
++
++static void rtw_cfg80211_preinit_wiphy(_adapter *padapter, struct wiphy *wiphy)
++{
++
++ wiphy->signal_type = CFG80211_SIGNAL_TYPE_MBM;
++
++ wiphy->max_scan_ssids = RTW_SSID_SCAN_AMOUNT;
++ wiphy->max_scan_ie_len = RTW_SCAN_IE_LEN_MAX;
++ wiphy->max_num_pmkids = RTW_MAX_NUM_PMKIDS;
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38)) || defined(COMPAT_KERNEL_RELEASE)
++ wiphy->max_remain_on_channel_duration = RTW_MAX_REMAIN_ON_CHANNEL_DURATION;
++#endif
++
++ wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION)
++ | BIT(NL80211_IFTYPE_ADHOC)
++#ifdef CONFIG_AP_MODE
++ | BIT(NL80211_IFTYPE_AP)
++ | BIT(NL80211_IFTYPE_MONITOR)
++#endif
++#if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE))
++ | BIT(NL80211_IFTYPE_P2P_CLIENT)
++ | BIT(NL80211_IFTYPE_P2P_GO)
++#endif
++ ;
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE)
++#ifdef CONFIG_AP_MODE
++ wiphy->mgmt_stypes = rtw_cfg80211_default_mgmt_stypes;
++#endif //CONFIG_AP_MODE
++#endif
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,0))
++ wiphy->software_iftypes |= BIT(NL80211_IFTYPE_MONITOR);
++#endif
++
++ /*
++ wiphy->iface_combinations = &rtw_combinations;
++ wiphy->n_iface_combinations = 1;
++ */
++
++ wiphy->cipher_suites = rtw_cipher_suites;
++ wiphy->n_cipher_suites = ARRAY_SIZE(rtw_cipher_suites);
++
++ /* if (padapter->registrypriv.wireless_mode & WIRELESS_11G) */
++ wiphy->bands[IEEE80211_BAND_2GHZ] = rtw_spt_band_alloc(IEEE80211_BAND_2GHZ);
++ /* if (padapter->registrypriv.wireless_mode & WIRELESS_11A) */
++ wiphy->bands[IEEE80211_BAND_5GHZ] = rtw_spt_band_alloc(IEEE80211_BAND_5GHZ);
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38) && LINUX_VERSION_CODE < KERNEL_VERSION(3,0,0))
++ wiphy->flags |= WIPHY_FLAG_SUPPORTS_SEPARATE_DEFAULT_KEYS;
++#endif
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,3,0))
++ wiphy->flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL;
++ wiphy->flags |= WIPHY_FLAG_OFFCHAN_TX | WIPHY_FLAG_HAVE_AP_SME;
++#endif
++
++ if(padapter->registrypriv.power_mgnt != PS_MODE_ACTIVE)
++ wiphy->flags |= WIPHY_FLAG_PS_ON_BY_DEFAULT;
++ else
++ wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
++}
++
++int rtw_wdev_alloc(_adapter *padapter, struct device *dev)
++{
++ int ret = 0;
++ struct wiphy *wiphy;
++ struct wireless_dev *wdev;
++ struct rtw_wdev_priv *pwdev_priv;
++ struct net_device *pnetdev = padapter->pnetdev;
++
++ DBG_8192C("%s(padapter=%p)\n", __func__, padapter);
++
++ /* wiphy */
++ wiphy = wiphy_new(&rtw_cfg80211_ops, sizeof(struct rtw_wdev_priv));
++ if (!wiphy) {
++ DBG_8192C("Couldn't allocate wiphy device\n");
++ ret = -ENOMEM;
++ goto exit;
++ }
++ set_wiphy_dev(wiphy, dev);
++ rtw_cfg80211_preinit_wiphy(padapter, wiphy);
++
++ ret = wiphy_register(wiphy);
++ if (ret < 0) {
++ DBG_8192C("Couldn't register wiphy device\n");
++ goto free_wiphy;
++ }
++
++ /* wdev */
++ wdev = (struct wireless_dev *)rtw_zmalloc(sizeof(struct wireless_dev));
++ if (!wdev) {
++ DBG_8192C("Couldn't allocate wireless device\n");
++ ret = -ENOMEM;
++ goto unregister_wiphy;
++ }
++ wdev->wiphy = wiphy;
++ wdev->netdev = pnetdev;
++ //wdev->iftype = NL80211_IFTYPE_STATION;
++ wdev->iftype = NL80211_IFTYPE_MONITOR; // for rtw_setopmode_cmd() in cfg80211_rtw_change_iface()
++ padapter->rtw_wdev = wdev;
++ pnetdev->ieee80211_ptr = wdev;
++
++ //init pwdev_priv
++ pwdev_priv = wdev_to_priv(wdev);
++ pwdev_priv->rtw_wdev = wdev;
++ pwdev_priv->pmon_ndev = NULL;
++ pwdev_priv->ifname_mon[0] = '\0';
++ pwdev_priv->padapter = padapter;
++ pwdev_priv->scan_request = NULL;
++ _rtw_spinlock_init(&pwdev_priv->scan_req_lock);
++
++ pwdev_priv->p2p_enabled = _FALSE;
++ pwdev_priv->provdisc_req_issued = _FALSE;
++ rtw_wdev_invit_info_init(&pwdev_priv->invit_info);
++ rtw_wdev_nego_info_init(&pwdev_priv->nego_info);
++
++ pwdev_priv->bandroid_scan = _FALSE;
++
++ if(padapter->registrypriv.power_mgnt != PS_MODE_ACTIVE)
++ pwdev_priv->power_mgmt = _TRUE;
++ else
++ pwdev_priv->power_mgmt = _FALSE;
++
++#ifdef CONFIG_CONCURRENT_MODE
++ ATOMIC_SET(&pwdev_priv->switch_ch_to, 1);
++ ATOMIC_SET(&pwdev_priv->ro_ch_to, 1);
++#endif
++
++ return ret;
++
++ rtw_mfree((u8*)wdev, sizeof(struct wireless_dev));
++unregister_wiphy:
++ wiphy_unregister(wiphy);
++ free_wiphy:
++ wiphy_free(wiphy);
++exit:
++ return ret;
++
++}
++
++void rtw_wdev_free(struct wireless_dev *wdev)
++{
++ struct rtw_wdev_priv *pwdev_priv;
++
++ DBG_8192C("%s(wdev=%p)\n", __func__, wdev);
++
++ if (!wdev)
++ return;
++
++ pwdev_priv = wdev_to_priv(wdev);
++
++ rtw_spt_band_free(wdev->wiphy->bands[IEEE80211_BAND_2GHZ]);
++ rtw_spt_band_free(wdev->wiphy->bands[IEEE80211_BAND_5GHZ]);
++
++ wiphy_free(wdev->wiphy);
++
++ rtw_mfree((u8*)wdev, sizeof(struct wireless_dev));
++}
++
++void rtw_wdev_unregister(struct wireless_dev *wdev)
++{
++ struct rtw_wdev_priv *pwdev_priv;
++
++ DBG_8192C("%s(wdev=%p)\n", __func__, wdev);
++
++ if (!wdev)
++ return;
++
++ pwdev_priv = wdev_to_priv(wdev);
++
++ rtw_cfg80211_indicate_scan_done(pwdev_priv, _TRUE);
++
++ if (pwdev_priv->pmon_ndev) {
++ DBG_8192C("%s, unregister monitor interface\n", __func__);
++ unregister_netdev(pwdev_priv->pmon_ndev);
++ }
++
++ wiphy_unregister(wdev->wiphy);
++}
++
++#endif //CONFIG_IOCTL_CFG80211
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/os_dep/linux/ioctl_linux.c linux-xbian-rpi/drivers/net/wireless/rtl8192cu/os_dep/linux/ioctl_linux.c
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/os_dep/linux/ioctl_linux.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/os_dep/linux/ioctl_linux.c 2015-07-28 01:20:58.429213356 +0200
+@@ -0,0 +1,11908 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#define _IOCTL_LINUX_C_
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++#include <wlan_bssdef.h>
++#include <rtw_debug.h>
++#include <wifi.h>
++#include <rtw_mlme.h>
++#include <rtw_mlme_ext.h>
++#include <rtw_ioctl.h>
++#include <rtw_ioctl_set.h>
++#include <rtw_ioctl_query.h>
++
++//#ifdef CONFIG_MP_INCLUDED
++#include <rtw_mp_ioctl.h>
++//#endif
++
++#ifdef CONFIG_USB_HCI
++#include <usb_ops.h>
++#endif //CONFIG_USB_HCI
++#include <rtw_version.h>
++
++#ifdef CONFIG_MP_INCLUDED
++#include <rtw_mp.h>
++#endif
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,27))
++#define iwe_stream_add_event(a, b, c, d, e) iwe_stream_add_event(b, c, d, e)
++#define iwe_stream_add_point(a, b, c, d, e) iwe_stream_add_point(b, c, d, e)
++#endif
++
++
++#define RTL_IOCTL_WPA_SUPPLICANT SIOCIWFIRSTPRIV+30
++
++#define SCAN_ITEM_SIZE 768
++#define MAX_CUSTOM_LEN 64
++#define RATE_COUNT 4
++
++#ifdef CONFIG_GLOBAL_UI_PID
++extern int ui_pid[3];
++#endif
++
++// combo scan
++#define WEXT_CSCAN_AMOUNT 9
++#define WEXT_CSCAN_BUF_LEN 360
++#define WEXT_CSCAN_HEADER "CSCAN S\x01\x00\x00S\x00"
++#define WEXT_CSCAN_HEADER_SIZE 12
++#define WEXT_CSCAN_SSID_SECTION 'S'
++#define WEXT_CSCAN_CHANNEL_SECTION 'C'
++#define WEXT_CSCAN_NPROBE_SECTION 'N'
++#define WEXT_CSCAN_ACTV_DWELL_SECTION 'A'
++#define WEXT_CSCAN_PASV_DWELL_SECTION 'P'
++#define WEXT_CSCAN_HOME_DWELL_SECTION 'H'
++#define WEXT_CSCAN_TYPE_SECTION 'T'
++
++
++extern u8 key_2char2num(u8 hch, u8 lch);
++extern u8 str_2char2num(u8 hch, u8 lch);
++extern u8 convert_ip_addr(u8 hch, u8 mch, u8 lch);
++
++u32 rtw_rates[] = {1000000,2000000,5500000,11000000,
++ 6000000,9000000,12000000,18000000,24000000,36000000,48000000,54000000};
++
++static const char * const iw_operation_mode[] =
++{
++ "Auto", "Ad-Hoc", "Managed", "Master", "Repeater", "Secondary", "Monitor"
++};
++
++static int hex2num_i(char c)
++{
++ if (c >= '0' && c <= '9')
++ return c - '0';
++ if (c >= 'a' && c <= 'f')
++ return c - 'a' + 10;
++ if (c >= 'A' && c <= 'F')
++ return c - 'A' + 10;
++ return -1;
++}
++
++static int hex2byte_i(const char *hex)
++{
++ int a, b;
++ a = hex2num_i(*hex++);
++ if (a < 0)
++ return -1;
++ b = hex2num_i(*hex++);
++ if (b < 0)
++ return -1;
++ return (a << 4) | b;
++}
++
++/**
++ * hwaddr_aton - Convert ASCII string to MAC address
++ * @txt: MAC address as a string (e.g., "00:11:22:33:44:55")
++ * @addr: Buffer for the MAC address (ETH_ALEN = 6 bytes)
++ * Returns: 0 on success, -1 on failure (e.g., string not a MAC address)
++ */
++static int hwaddr_aton_i(const char *txt, u8 *addr)
++{
++ int i;
++
++ for (i = 0; i < 6; i++) {
++ int a, b;
++
++ a = hex2num_i(*txt++);
++ if (a < 0)
++ return -1;
++ b = hex2num_i(*txt++);
++ if (b < 0)
++ return -1;
++ *addr++ = (a << 4) | b;
++ if (i < 5 && *txt++ != ':')
++ return -1;
++ }
++
++ return 0;
++}
++
++static void indicate_wx_custom_event(_adapter *padapter, char *msg)
++{
++#ifndef CONFIG_IOCTL_CFG80211
++ u8 *buff, *p;
++ union iwreq_data wrqu;
++
++ if ((u32)strlen(msg) > IW_CUSTOM_MAX) {
++ DBG_871X("%s strlen(msg):%u > IW_CUSTOM_MAX:%u\n", __FUNCTION__ ,(u32)strlen(msg), IW_CUSTOM_MAX);
++ return;
++ }
++
++ buff = rtw_zmalloc(IW_CUSTOM_MAX+1);
++ if(!buff)
++ return;
++
++ _rtw_memcpy(buff, msg, strlen(msg));
++
++ _rtw_memset(&wrqu,0,sizeof(wrqu));
++ wrqu.data.length = strlen(msg);
++
++ DBG_871X("%s %s\n", __FUNCTION__, buff);
++ wireless_send_event(padapter->pnetdev, IWEVCUSTOM, &wrqu, buff);
++
++ rtw_mfree(buff, IW_CUSTOM_MAX+1);
++#endif
++}
++
++
++static void request_wps_pbc_event(_adapter *padapter)
++{
++#ifndef CONFIG_IOCTL_CFG80211
++ u8 *buff, *p;
++ union iwreq_data wrqu;
++
++ buff = rtw_malloc(IW_CUSTOM_MAX);
++ if(!buff)
++ return;
++
++ _rtw_memset(buff, 0, IW_CUSTOM_MAX);
++
++ p=buff;
++
++ p+=sprintf(p, "WPS_PBC_START.request=TRUE");
++
++ _rtw_memset(&wrqu,0,sizeof(wrqu));
++
++ wrqu.data.length = p-buff;
++
++ wrqu.data.length = (wrqu.data.length<IW_CUSTOM_MAX) ? wrqu.data.length:IW_CUSTOM_MAX;
++
++ DBG_871X("%s\n", __FUNCTION__);
++
++ wireless_send_event(padapter->pnetdev, IWEVCUSTOM, &wrqu, buff);
++
++ if(buff)
++ {
++ rtw_mfree(buff, IW_CUSTOM_MAX);
++ }
++#endif
++}
++
++
++void indicate_wx_scan_complete_event(_adapter *padapter)
++{
++#ifndef CONFIG_IOCTL_CFG80211
++ union iwreq_data wrqu;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++
++ _rtw_memset(&wrqu, 0, sizeof(union iwreq_data));
++
++ //DBG_871X("+rtw_indicate_wx_scan_complete_event\n");
++ wireless_send_event(padapter->pnetdev, SIOCGIWSCAN, &wrqu, NULL);
++#endif
++}
++
++
++void rtw_indicate_wx_assoc_event(_adapter *padapter)
++{
++#ifndef CONFIG_IOCTL_CFG80211
++ union iwreq_data wrqu;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++
++ _rtw_memset(&wrqu, 0, sizeof(union iwreq_data));
++
++ wrqu.ap_addr.sa_family = ARPHRD_ETHER;
++
++ _rtw_memcpy(wrqu.ap_addr.sa_data, pmlmepriv->cur_network.network.MacAddress, ETH_ALEN);
++
++ //DBG_871X("+rtw_indicate_wx_assoc_event\n");
++ wireless_send_event(padapter->pnetdev, SIOCGIWAP, &wrqu, NULL);
++#endif
++}
++
++void rtw_indicate_wx_disassoc_event(_adapter *padapter)
++{
++#ifndef CONFIG_IOCTL_CFG80211
++ union iwreq_data wrqu;
++
++ _rtw_memset(&wrqu, 0, sizeof(union iwreq_data));
++
++ wrqu.ap_addr.sa_family = ARPHRD_ETHER;
++ _rtw_memset(wrqu.ap_addr.sa_data, 0, ETH_ALEN);
++
++ //DBG_871X("+rtw_indicate_wx_disassoc_event\n");
++ wireless_send_event(padapter->pnetdev, SIOCGIWAP, &wrqu, NULL);
++#endif
++}
++
++/*
++uint rtw_is_cckrates_included(u8 *rate)
++{
++ u32 i = 0;
++
++ while(rate[i]!=0)
++ {
++ if ( (((rate[i]) & 0x7f) == 2) || (((rate[i]) & 0x7f) == 4) ||
++ (((rate[i]) & 0x7f) == 11) || (((rate[i]) & 0x7f) == 22) )
++ return _TRUE;
++ i++;
++ }
++
++ return _FALSE;
++}
++
++uint rtw_is_cckratesonly_included(u8 *rate)
++{
++ u32 i = 0;
++
++ while(rate[i]!=0)
++ {
++ if ( (((rate[i]) & 0x7f) != 2) && (((rate[i]) & 0x7f) != 4) &&
++ (((rate[i]) & 0x7f) != 11) && (((rate[i]) & 0x7f) != 22) )
++ return _FALSE;
++ i++;
++ }
++
++ return _TRUE;
++}
++*/
++
++static char *translate_scan(_adapter *padapter,
++ struct iw_request_info* info, struct wlan_network *pnetwork,
++ char *start, char *stop)
++{
++ struct iw_event iwe;
++ u16 cap;
++ u32 ht_ielen = 0;
++ char custom[MAX_CUSTOM_LEN];
++ char *p;
++ u16 max_rate=0, rate, ht_cap=_FALSE;
++ u32 i = 0;
++ char *current_val;
++ long rssi;
++ u8 bw_40MHz=0, short_GI=0;
++ u16 mcs_rate=0;
++ struct registry_priv *pregpriv = &padapter->registrypriv;
++#ifdef CONFIG_P2P
++ struct wifidirect_info *pwdinfo = &padapter->wdinfo;
++#endif //CONFIG_P2P
++
++#ifdef CONFIG_P2P
++#ifdef CONFIG_WFD
++ if ( SCAN_RESULT_ALL == pwdinfo->wfd_info->scan_result_type )
++ {
++
++ }
++ else if ( ( SCAN_RESULT_P2P_ONLY == pwdinfo->wfd_info->scan_result_type ) ||
++ ( SCAN_RESULT_WFD_TYPE == pwdinfo->wfd_info->scan_result_type ) )
++#endif // CONFIG_WFD
++ {
++ if(!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
++ {
++ u32 blnGotP2PIE = _FALSE;
++
++ // User is doing the P2P device discovery
++ // The prefix of SSID should be "DIRECT-" and the IE should contains the P2P IE.
++ // If not, the driver should ignore this AP and go to the next AP.
++
++ // Verifying the SSID
++ if ( _rtw_memcmp( pnetwork->network.Ssid.Ssid, pwdinfo->p2p_wildcard_ssid, P2P_WILDCARD_SSID_LEN ) )
++ {
++ u32 p2pielen = 0;
++
++ // Verifying the P2P IE
++ if ( rtw_get_p2p_ie( &pnetwork->network.IEs[12], pnetwork->network.IELength - 12, NULL, &p2pielen) )
++ {
++ blnGotP2PIE = _TRUE;
++ }
++ }
++
++ if ( blnGotP2PIE == _FALSE )
++ {
++ return start;
++ }
++
++ }
++ }
++
++#ifdef CONFIG_WFD
++ if ( SCAN_RESULT_WFD_TYPE == pwdinfo->wfd_info->scan_result_type )
++ {
++ u32 blnGotWFD = _FALSE;
++ u8 wfd_ie[ 128 ] = { 0x00 };
++ uint wfd_ielen = 0;
++
++ if ( rtw_get_wfd_ie( &pnetwork->network.IEs[12], pnetwork->network.IELength - 12, wfd_ie, &wfd_ielen ) )
++ {
++ u8 wfd_devinfo[ 6 ] = { 0x00 };
++ uint wfd_devlen = 6;
++
++ if ( rtw_get_wfd_attr_content( wfd_ie, wfd_ielen, WFD_ATTR_DEVICE_INFO, wfd_devinfo, &wfd_devlen) )
++ {
++ if ( pwdinfo->wfd_info->wfd_device_type == WFD_DEVINFO_PSINK )
++ {
++ // the first two bits will indicate the WFD device type
++ if ( ( wfd_devinfo[ 1 ] & 0x03 ) == WFD_DEVINFO_SOURCE )
++ {
++ // If this device is Miracast PSink device, the scan reuslt should just provide the Miracast source.
++ blnGotWFD = _TRUE;
++ }
++ }
++ else if ( pwdinfo->wfd_info->wfd_device_type == WFD_DEVINFO_SOURCE )
++ {
++ // the first two bits will indicate the WFD device type
++ if ( ( wfd_devinfo[ 1 ] & 0x03 ) == WFD_DEVINFO_PSINK )
++ {
++ // If this device is Miracast source device, the scan reuslt should just provide the Miracast PSink.
++ // Todo: How about the SSink?!
++ blnGotWFD = _TRUE;
++ }
++ }
++ }
++ }
++
++ if ( blnGotWFD == _FALSE )
++ {
++ return start;
++ }
++ }
++#endif // CONFIG_WFD
++
++#endif //CONFIG_P2P
++ /* AP MAC address */
++ iwe.cmd = SIOCGIWAP;
++ iwe.u.ap_addr.sa_family = ARPHRD_ETHER;
++
++ _rtw_memcpy(iwe.u.ap_addr.sa_data, pnetwork->network.MacAddress, ETH_ALEN);
++ start = iwe_stream_add_event(info, start, stop, &iwe, IW_EV_ADDR_LEN);
++
++ /* Add the ESSID */
++ iwe.cmd = SIOCGIWESSID;
++ iwe.u.data.flags = 1;
++ iwe.u.data.length = min((u16)pnetwork->network.Ssid.SsidLength, (u16)32);
++ start = iwe_stream_add_point(info, start, stop, &iwe, pnetwork->network.Ssid.Ssid);
++
++ //parsing HT_CAP_IE
++ p = rtw_get_ie(&pnetwork->network.IEs[12], _HT_CAPABILITY_IE_, &ht_ielen, pnetwork->network.IELength-12);
++
++ if(p && ht_ielen>0)
++ {
++ struct rtw_ieee80211_ht_cap *pht_capie;
++ ht_cap = _TRUE;
++ pht_capie = (struct rtw_ieee80211_ht_cap *)(p+2);
++ _rtw_memcpy(&mcs_rate , pht_capie->supp_mcs_set, 2);
++ bw_40MHz = (pht_capie->cap_info&IEEE80211_HT_CAP_SUP_WIDTH) ? 1:0;
++ short_GI = (pht_capie->cap_info&(IEEE80211_HT_CAP_SGI_20|IEEE80211_HT_CAP_SGI_40)) ? 1:0;
++ }
++
++ /* Add the protocol name */
++ iwe.cmd = SIOCGIWNAME;
++ if ((rtw_is_cckratesonly_included((u8*)&pnetwork->network.SupportedRates)) == _TRUE)
++ {
++ if(ht_cap == _TRUE)
++ snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11bn");
++ else
++ snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11b");
++ }
++ else if ((rtw_is_cckrates_included((u8*)&pnetwork->network.SupportedRates)) == _TRUE)
++ {
++ if(ht_cap == _TRUE)
++ snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11bgn");
++ else
++ snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11bg");
++ }
++ else
++ {
++ if(pnetwork->network.Configuration.DSConfig > 14)
++ {
++ if(ht_cap == _TRUE)
++ snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11an");
++ else
++ snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11a");
++ }
++ else
++ {
++ if(ht_cap == _TRUE)
++ snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11gn");
++ else
++ snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11g");
++ }
++ }
++
++ start = iwe_stream_add_event(info, start, stop, &iwe, IW_EV_CHAR_LEN);
++
++ /* Add mode */
++ iwe.cmd = SIOCGIWMODE;
++ _rtw_memcpy((u8 *)&cap, rtw_get_capability_from_ie(pnetwork->network.IEs), 2);
++
++
++ cap = le16_to_cpu(cap);
++
++ if(cap & (WLAN_CAPABILITY_IBSS |WLAN_CAPABILITY_BSS)){
++ if (cap & WLAN_CAPABILITY_BSS)
++ iwe.u.mode = IW_MODE_MASTER;
++ else
++ iwe.u.mode = IW_MODE_ADHOC;
++
++ start = iwe_stream_add_event(info, start, stop, &iwe, IW_EV_UINT_LEN);
++ }
++
++ if(pnetwork->network.Configuration.DSConfig<1 /*|| pnetwork->network.Configuration.DSConfig>14*/)
++ pnetwork->network.Configuration.DSConfig = 1;
++
++ /* Add frequency/channel */
++ iwe.cmd = SIOCGIWFREQ;
++ iwe.u.freq.m = rtw_ch2freq(pnetwork->network.Configuration.DSConfig) * 100000;
++ iwe.u.freq.e = 1;
++ iwe.u.freq.i = pnetwork->network.Configuration.DSConfig;
++ start = iwe_stream_add_event(info, start, stop, &iwe, IW_EV_FREQ_LEN);
++
++ /* Add encryption capability */
++ iwe.cmd = SIOCGIWENCODE;
++ if (cap & WLAN_CAPABILITY_PRIVACY)
++ iwe.u.data.flags = IW_ENCODE_ENABLED | IW_ENCODE_NOKEY;
++ else
++ iwe.u.data.flags = IW_ENCODE_DISABLED;
++ iwe.u.data.length = 0;
++ start = iwe_stream_add_point(info, start, stop, &iwe, pnetwork->network.Ssid.Ssid);
++
++ /*Add basic and extended rates */
++ max_rate = 0;
++ p = custom;
++ p += snprintf(p, MAX_CUSTOM_LEN - (p - custom), " Rates (Mb/s): ");
++ while(pnetwork->network.SupportedRates[i]!=0)
++ {
++ rate = pnetwork->network.SupportedRates[i]&0x7F;
++ if (rate > max_rate)
++ max_rate = rate;
++ p += snprintf(p, MAX_CUSTOM_LEN - (p - custom),
++ "%d%s ", rate >> 1, (rate & 1) ? ".5" : "");
++ i++;
++ }
++
++ if(ht_cap == _TRUE)
++ {
++ if(mcs_rate&0x8000)//MCS15
++ {
++ max_rate = (bw_40MHz) ? ((short_GI)?300:270):((short_GI)?144:130);
++
++ }
++ else if(mcs_rate&0x0080)//MCS7
++ {
++ max_rate = (bw_40MHz) ? ((short_GI)?150:135):((short_GI)?72:65);
++ }
++ else//default MCS7
++ {
++ DBG_871X("wx_get_scan, mcs_rate_bitmap=0x%x\n", mcs_rate);
++ max_rate = (bw_40MHz) ? ((short_GI)?150:135):((short_GI)?72:65);
++ }
++
++ max_rate = max_rate*2;//Mbps/2;
++ }
++
++ iwe.cmd = SIOCGIWRATE;
++ iwe.u.bitrate.fixed = iwe.u.bitrate.disabled = 0;
++ iwe.u.bitrate.value = max_rate * 500000;
++ start = iwe_stream_add_event(info, start, stop, &iwe, IW_EV_PARAM_LEN);
++
++ //parsing WPA/WPA2 IE
++ {
++ u8 buf[MAX_WPA_IE_LEN];
++ u8 wpa_ie[255],rsn_ie[255];
++ u16 wpa_len=0,rsn_len=0;
++ u8 *p;
++ sint out_len=0;
++ out_len=rtw_get_sec_ie(pnetwork->network.IEs ,pnetwork->network.IELength,rsn_ie,&rsn_len,wpa_ie,&wpa_len);
++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("rtw_wx_get_scan: ssid=%s\n",pnetwork->network.Ssid.Ssid));
++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("rtw_wx_get_scan: wpa_len=%d rsn_len=%d\n",wpa_len,rsn_len));
++
++ if (wpa_len > 0)
++ {
++ p=buf;
++ _rtw_memset(buf, 0, MAX_WPA_IE_LEN);
++ p += sprintf(p, "wpa_ie=");
++ for (i = 0; i < wpa_len; i++) {
++ p += sprintf(p, "%02x", wpa_ie[i]);
++ }
++
++ _rtw_memset(&iwe, 0, sizeof(iwe));
++ iwe.cmd = IWEVCUSTOM;
++ iwe.u.data.length = strlen(buf);
++ start = iwe_stream_add_point(info, start, stop, &iwe,buf);
++
++ _rtw_memset(&iwe, 0, sizeof(iwe));
++ iwe.cmd =IWEVGENIE;
++ iwe.u.data.length = wpa_len;
++ start = iwe_stream_add_point(info, start, stop, &iwe, wpa_ie);
++ }
++ if (rsn_len > 0)
++ {
++ p = buf;
++ _rtw_memset(buf, 0, MAX_WPA_IE_LEN);
++ p += sprintf(p, "rsn_ie=");
++ for (i = 0; i < rsn_len; i++) {
++ p += sprintf(p, "%02x", rsn_ie[i]);
++ }
++ _rtw_memset(&iwe, 0, sizeof(iwe));
++ iwe.cmd = IWEVCUSTOM;
++ iwe.u.data.length = strlen(buf);
++ start = iwe_stream_add_point(info, start, stop, &iwe,buf);
++
++ _rtw_memset(&iwe, 0, sizeof(iwe));
++ iwe.cmd =IWEVGENIE;
++ iwe.u.data.length = rsn_len;
++ start = iwe_stream_add_point(info, start, stop, &iwe, rsn_ie);
++ }
++ }
++
++ { //parsing WPS IE
++ uint cnt = 0,total_ielen;
++ u8 *wpsie_ptr=NULL;
++ uint wps_ielen = 0;
++
++ u8 *ie_ptr = pnetwork->network.IEs +_FIXED_IE_LENGTH_;
++ total_ielen= pnetwork->network.IELength - _FIXED_IE_LENGTH_;
++
++ while(cnt < total_ielen)
++ {
++ if(rtw_is_wps_ie(&ie_ptr[cnt], &wps_ielen) && (wps_ielen>2))
++ {
++ wpsie_ptr = &ie_ptr[cnt];
++ iwe.cmd =IWEVGENIE;
++ iwe.u.data.length = (u16)wps_ielen;
++ start = iwe_stream_add_point(info, start, stop, &iwe, wpsie_ptr);
++ }
++ cnt+=ie_ptr[cnt+1]+2; //goto next
++ }
++ }
++
++
++{
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ u8 ss, sq;
++
++ /* Add quality statistics */
++ iwe.cmd = IWEVQUAL;
++ iwe.u.qual.updated = IW_QUAL_QUAL_UPDATED | IW_QUAL_LEVEL_UPDATED | IW_QUAL_NOISE_INVALID
++ #ifdef CONFIG_SIGNAL_DISPLAY_DBM
++ | IW_QUAL_DBM
++ #endif
++ ;
++
++ if ( check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE &&
++ is_same_network(&pmlmepriv->cur_network.network, &pnetwork->network)) {
++ ss = padapter->recvpriv.signal_strength;
++ sq = padapter->recvpriv.signal_qual;
++ } else {
++ ss = pnetwork->network.PhyInfo.SignalStrength;
++ sq = pnetwork->network.PhyInfo.SignalQuality;
++ }
++
++
++ #ifdef CONFIG_SIGNAL_DISPLAY_DBM
++ iwe.u.qual.level = (u8) translate_percentage_to_dbm(ss);//dbm
++ #else
++ iwe.u.qual.level = (u8)ss;//%
++ #endif
++
++ iwe.u.qual.qual = (u8)sq; // signal quality
++
++ #ifdef CONFIG_PLATFORM_ROCKCHIPS
++ iwe.u.qual.noise = -100; // noise level suggest by zhf@rockchips
++ #else
++ iwe.u.qual.noise = 0; // noise level
++ #endif //CONFIG_PLATFORM_ROCKCHIPS
++
++ //DBG_871X("iqual=%d, ilevel=%d, inoise=%d, iupdated=%d\n", iwe.u.qual.qual, iwe.u.qual.level , iwe.u.qual.noise, iwe.u.qual.updated);
++
++ start = iwe_stream_add_event(info, start, stop, &iwe, IW_EV_QUAL_LEN);
++}
++
++ return start;
++}
++
++static int wpa_set_auth_algs(struct net_device *dev, u32 value)
++{
++ _adapter *padapter = (_adapter *) rtw_netdev_priv(dev);
++ int ret = 0;
++
++ if ((value & AUTH_ALG_SHARED_KEY)&&(value & AUTH_ALG_OPEN_SYSTEM))
++ {
++ DBG_871X("wpa_set_auth_algs, AUTH_ALG_SHARED_KEY and AUTH_ALG_OPEN_SYSTEM [value:0x%x]\n",value);
++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;
++ padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeAutoSwitch;
++ padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Auto;
++ }
++ else if (value & AUTH_ALG_SHARED_KEY)
++ {
++ DBG_871X("wpa_set_auth_algs, AUTH_ALG_SHARED_KEY [value:0x%x]\n",value);
++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;
++
++#ifdef CONFIG_PLATFORM_MT53XX
++ padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeAutoSwitch;
++ padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Auto;
++#else
++ padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeShared;
++ padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Shared;
++#endif
++ }
++ else if(value & AUTH_ALG_OPEN_SYSTEM)
++ {
++ DBG_871X("wpa_set_auth_algs, AUTH_ALG_OPEN_SYSTEM\n");
++ //padapter->securitypriv.ndisencryptstatus = Ndis802_11EncryptionDisabled;
++ if(padapter->securitypriv.ndisauthtype < Ndis802_11AuthModeWPAPSK)
++ {
++#ifdef CONFIG_PLATFORM_MT53XX
++ padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeAutoSwitch;
++ padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Auto;
++#else
++ padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeOpen;
++ padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Open;
++#endif
++ }
++
++ }
++ else if(value & AUTH_ALG_LEAP)
++ {
++ DBG_871X("wpa_set_auth_algs, AUTH_ALG_LEAP\n");
++ }
++ else
++ {
++ DBG_871X("wpa_set_auth_algs, error!\n");
++ ret = -EINVAL;
++ }
++
++ return ret;
++
++}
++
++static int wpa_set_encryption(struct net_device *dev, struct ieee_param *param, u32 param_len)
++{
++ int ret = 0;
++ u32 wep_key_idx, wep_key_len,wep_total_len;
++ NDIS_802_11_WEP *pwep = NULL;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct security_priv *psecuritypriv = &padapter->securitypriv;
++#ifdef CONFIG_P2P
++ struct wifidirect_info* pwdinfo = &padapter->wdinfo;
++#endif //CONFIG_P2P
++
++_func_enter_;
++
++ param->u.crypt.err = 0;
++ param->u.crypt.alg[IEEE_CRYPT_ALG_NAME_LEN - 1] = '\0';
++
++ if (param_len < (u32) ((u8 *) param->u.crypt.key - (u8 *) param) + param->u.crypt.key_len)
++ {
++ ret = -EINVAL;
++ goto exit;
++ }
++
++ if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff &&
++ param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff &&
++ param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff)
++ {
++
++ if (param->u.crypt.idx >= WEP_KEYS
++#ifdef CONFIG_IEEE80211W
++ && param->u.crypt.idx > BIP_MAX_KEYID
++#endif //CONFIG_IEEE80211W
++ )
++ {
++ ret = -EINVAL;
++ goto exit;
++ }
++ }
++ else
++ {
++
++ {
++ ret = -EINVAL;
++ goto exit;
++ }
++ }
++
++ if (strcmp(param->u.crypt.alg, "WEP") == 0)
++ {
++ RT_TRACE(_module_rtl871x_ioctl_os_c,_drv_err_,("wpa_set_encryption, crypt.alg = WEP\n"));
++ DBG_871X("wpa_set_encryption, crypt.alg = WEP\n");
++
++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;
++ padapter->securitypriv.dot11PrivacyAlgrthm=_WEP40_;
++ padapter->securitypriv.dot118021XGrpPrivacy=_WEP40_;
++
++ wep_key_idx = param->u.crypt.idx;
++ wep_key_len = param->u.crypt.key_len;
++
++ RT_TRACE(_module_rtl871x_ioctl_os_c,_drv_info_,("(1)wep_key_idx=%d\n", wep_key_idx));
++ DBG_871X("(1)wep_key_idx=%d\n", wep_key_idx);
++
++ if (wep_key_idx > WEP_KEYS)
++ return -EINVAL;
++
++ RT_TRACE(_module_rtl871x_ioctl_os_c,_drv_info_,("(2)wep_key_idx=%d\n", wep_key_idx));
++
++ if (wep_key_len > 0)
++ {
++ wep_key_len = wep_key_len <= 5 ? 5 : 13;
++ wep_total_len = wep_key_len + FIELD_OFFSET(NDIS_802_11_WEP, KeyMaterial);
++ pwep =(NDIS_802_11_WEP *) rtw_malloc(wep_total_len);
++ if(pwep == NULL){
++ RT_TRACE(_module_rtl871x_ioctl_os_c,_drv_err_,(" wpa_set_encryption: pwep allocate fail !!!\n"));
++ goto exit;
++ }
++
++ _rtw_memset(pwep, 0, wep_total_len);
++
++ pwep->KeyLength = wep_key_len;
++ pwep->Length = wep_total_len;
++
++ if(wep_key_len==13)
++ {
++ padapter->securitypriv.dot11PrivacyAlgrthm=_WEP104_;
++ padapter->securitypriv.dot118021XGrpPrivacy=_WEP104_;
++ }
++ }
++ else {
++ ret = -EINVAL;
++ goto exit;
++ }
++
++ pwep->KeyIndex = wep_key_idx;
++ pwep->KeyIndex |= 0x80000000;
++
++ _rtw_memcpy(pwep->KeyMaterial, param->u.crypt.key, pwep->KeyLength);
++
++ if(param->u.crypt.set_tx)
++ {
++ DBG_871X("wep, set_tx=1\n");
++
++ if(rtw_set_802_11_add_wep(padapter, pwep) == (u8)_FAIL)
++ {
++ ret = -EOPNOTSUPP ;
++ }
++ }
++ else
++ {
++ DBG_871X("wep, set_tx=0\n");
++
++ //don't update "psecuritypriv->dot11PrivacyAlgrthm" and
++ //"psecuritypriv->dot11PrivacyKeyIndex=keyid", but can rtw_set_key to fw/cam
++
++ if (wep_key_idx >= WEP_KEYS) {
++ ret = -EOPNOTSUPP ;
++ goto exit;
++ }
++
++ _rtw_memcpy(&(psecuritypriv->dot11DefKey[wep_key_idx].skey[0]), pwep->KeyMaterial, pwep->KeyLength);
++ psecuritypriv->dot11DefKeylen[wep_key_idx]=pwep->KeyLength;
++ rtw_set_key(padapter, psecuritypriv, wep_key_idx, 0);
++ }
++
++ goto exit;
++ }
++
++ if(padapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) // 802_1x
++ {
++ struct sta_info * psta,*pbcmc_sta;
++ struct sta_priv * pstapriv = &padapter->stapriv;
++
++ if (check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_MP_STATE) == _TRUE) //sta mode
++ {
++ psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));
++ if (psta == NULL) {
++ //DEBUG_ERR( ("Set wpa_set_encryption: Obtain Sta_info fail \n"));
++ }
++ else
++ {
++ //Jeff: don't disable ieee8021x_blocked while clearing key
++ if (strcmp(param->u.crypt.alg, "none") != 0)
++ psta->ieee8021x_blocked = _FALSE;
++
++ if((padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption2Enabled)||
++ (padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption3Enabled))
++ {
++ psta->dot118021XPrivacy = padapter->securitypriv.dot11PrivacyAlgrthm;
++ }
++
++ if(param->u.crypt.set_tx ==1)//pairwise key
++ {
++ _rtw_memcpy(psta->dot118021x_UncstKey.skey, param->u.crypt.key, (param->u.crypt.key_len>16 ?16:param->u.crypt.key_len));
++
++ if(strcmp(param->u.crypt.alg, "TKIP") == 0)//set mic key
++ {
++ //DEBUG_ERR(("\nset key length :param->u.crypt.key_len=%d\n", param->u.crypt.key_len));
++ _rtw_memcpy(psta->dot11tkiptxmickey.skey, &(param->u.crypt.key[16]), 8);
++ _rtw_memcpy(psta->dot11tkiprxmickey.skey, &(param->u.crypt.key[24]), 8);
++
++ padapter->securitypriv.busetkipkey=_FALSE;
++ //_set_timer(&padapter->securitypriv.tkip_timer, 50);
++ }
++
++ //DEBUG_ERR(("\n param->u.crypt.key_len=%d\n",param->u.crypt.key_len));
++ //DEBUG_ERR(("\n ~~~~stastakey:unicastkey\n"));
++ DBG_871X("\n ~~~~stastakey:unicastkey\n");
++
++ rtw_setstakey_cmd(padapter, (unsigned char *)psta, _TRUE);
++ }
++ else//group key
++ {
++ if(strcmp(param->u.crypt.alg, "TKIP") == 0 || strcmp(param->u.crypt.alg, "CCMP") == 0)
++ {
++ _rtw_memcpy(padapter->securitypriv.dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key,(param->u.crypt.key_len>16 ?16:param->u.crypt.key_len));
++ //only TKIP group key need to install this
++ if(param->u.crypt.key_len > 16)
++ {
++ _rtw_memcpy(padapter->securitypriv.dot118021XGrptxmickey[param->u.crypt.idx].skey,&(param->u.crypt.key[16]),8);
++ _rtw_memcpy(padapter->securitypriv.dot118021XGrprxmickey[param->u.crypt.idx].skey,&(param->u.crypt.key[24]),8);
++ }
++ padapter->securitypriv.binstallGrpkey = _TRUE;
++ //DEBUG_ERR((" param->u.crypt.key_len=%d\n", param->u.crypt.key_len));
++ DBG_871X(" ~~~~set sta key:groupkey\n");
++
++ padapter->securitypriv.dot118021XGrpKeyid = param->u.crypt.idx;
++
++ rtw_set_key(padapter,&padapter->securitypriv,param->u.crypt.idx, 1);
++ }
++#ifdef CONFIG_IEEE80211W
++ else if(strcmp(param->u.crypt.alg, "BIP") == 0)
++ {
++ int no;
++ //printk("BIP key_len=%d , index=%d @@@@@@@@@@@@@@@@@@\n", param->u.crypt.key_len, param->u.crypt.idx);
++ //save the IGTK key, length 16 bytes
++ _rtw_memcpy(padapter->securitypriv.dot11wBIPKey[param->u.crypt.idx].skey, param->u.crypt.key,(param->u.crypt.key_len>16 ?16:param->u.crypt.key_len));
++ /*printk("IGTK key below:\n");
++ for(no=0;no<16;no++)
++ printk(" %02x ", padapter->securitypriv.dot11wBIPKey[param->u.crypt.idx].skey[no]);
++ printk("\n");*/
++ padapter->securitypriv.dot11wBIPKeyid = param->u.crypt.idx;
++ padapter->securitypriv.binstallBIPkey = _TRUE;
++ DBG_871X(" ~~~~set sta key:IGKT\n");
++ }
++#endif //CONFIG_IEEE80211W
++
++#ifdef CONFIG_P2P
++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_PROVISIONING_ING))
++ {
++ rtw_p2p_set_state(pwdinfo, P2P_STATE_PROVISIONING_DONE);
++ }
++#endif //CONFIG_P2P
++
++ }
++ }
++
++ pbcmc_sta=rtw_get_bcmc_stainfo(padapter);
++ if(pbcmc_sta==NULL)
++ {
++ //DEBUG_ERR( ("Set OID_802_11_ADD_KEY: bcmc stainfo is null \n"));
++ }
++ else
++ {
++ //Jeff: don't disable ieee8021x_blocked while clearing key
++ if (strcmp(param->u.crypt.alg, "none") != 0)
++ pbcmc_sta->ieee8021x_blocked = _FALSE;
++
++ if((padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption2Enabled)||
++ (padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption3Enabled))
++ {
++ pbcmc_sta->dot118021XPrivacy = padapter->securitypriv.dot11PrivacyAlgrthm;
++ }
++ }
++ }
++ else if(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE)) //adhoc mode
++ {
++ }
++ }
++
++exit:
++
++ if (pwep) {
++ rtw_mfree((u8 *)pwep, wep_total_len);
++ }
++
++ _func_exit_;
++
++ return ret;
++}
++
++static int rtw_set_wpa_ie(_adapter *padapter, char *pie, unsigned short ielen)
++{
++ u8 *buf=NULL, *pos=NULL;
++ u32 left;
++ int group_cipher = 0, pairwise_cipher = 0;
++ int ret = 0;
++ u8 null_addr[]= {0,0,0,0,0,0};
++#ifdef CONFIG_P2P
++ struct wifidirect_info* pwdinfo = &padapter->wdinfo;
++#endif //CONFIG_P2P
++
++ if((ielen > MAX_WPA_IE_LEN) || (pie == NULL)){
++ _clr_fwstate_(&padapter->mlmepriv, WIFI_UNDER_WPS);
++ if(pie == NULL)
++ return ret;
++ else
++ return -EINVAL;
++ }
++
++ if(ielen)
++ {
++ buf = rtw_zmalloc(ielen);
++ if (buf == NULL){
++ ret = -ENOMEM;
++ goto exit;
++ }
++
++ _rtw_memcpy(buf, pie , ielen);
++
++ //dump
++ {
++ int i;
++ DBG_871X("\n wpa_ie(length:%d):\n", ielen);
++ for(i=0;i<ielen;i=i+8)
++ DBG_871X("0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x \n",buf[i],buf[i+1],buf[i+2],buf[i+3],buf[i+4],buf[i+5],buf[i+6],buf[i+7]);
++ }
++
++ pos = buf;
++ if(ielen < RSN_HEADER_LEN){
++ RT_TRACE(_module_rtl871x_ioctl_os_c,_drv_err_,("Ie len too short %d\n", ielen));
++ ret = -1;
++ goto exit;
++ }
++
++#if 0
++ pos += RSN_HEADER_LEN;
++ left = ielen - RSN_HEADER_LEN;
++
++ if (left >= RSN_SELECTOR_LEN){
++ pos += RSN_SELECTOR_LEN;
++ left -= RSN_SELECTOR_LEN;
++ }
++ else if (left > 0){
++ RT_TRACE(_module_rtl871x_ioctl_os_c,_drv_err_,("Ie length mismatch, %u too much \n", left));
++ ret =-1;
++ goto exit;
++ }
++#endif
++
++ if(rtw_parse_wpa_ie(buf, ielen, &group_cipher, &pairwise_cipher) == _SUCCESS)
++ {
++ padapter->securitypriv.dot11AuthAlgrthm= dot11AuthAlgrthm_8021X;
++ padapter->securitypriv.ndisauthtype=Ndis802_11AuthModeWPAPSK;
++ _rtw_memcpy(padapter->securitypriv.supplicant_ie, &buf[0], ielen);
++ }
++
++ if(rtw_parse_wpa2_ie(buf, ielen, &group_cipher, &pairwise_cipher) == _SUCCESS)
++ {
++ padapter->securitypriv.dot11AuthAlgrthm= dot11AuthAlgrthm_8021X;
++ padapter->securitypriv.ndisauthtype=Ndis802_11AuthModeWPA2PSK;
++ _rtw_memcpy(padapter->securitypriv.supplicant_ie, &buf[0], ielen);
++ }
++
++ if (group_cipher == 0)
++ {
++ group_cipher = WPA_CIPHER_NONE;
++ }
++ if (pairwise_cipher == 0)
++ {
++ pairwise_cipher = WPA_CIPHER_NONE;
++ }
++
++ switch(group_cipher)
++ {
++ case WPA_CIPHER_NONE:
++ padapter->securitypriv.dot118021XGrpPrivacy=_NO_PRIVACY_;
++ padapter->securitypriv.ndisencryptstatus=Ndis802_11EncryptionDisabled;
++ break;
++ case WPA_CIPHER_WEP40:
++ padapter->securitypriv.dot118021XGrpPrivacy=_WEP40_;
++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;
++ break;
++ case WPA_CIPHER_TKIP:
++ padapter->securitypriv.dot118021XGrpPrivacy=_TKIP_;
++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption2Enabled;
++ break;
++ case WPA_CIPHER_CCMP:
++ padapter->securitypriv.dot118021XGrpPrivacy=_AES_;
++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption3Enabled;
++ break;
++ case WPA_CIPHER_WEP104:
++ padapter->securitypriv.dot118021XGrpPrivacy=_WEP104_;
++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;
++ break;
++ }
++
++ switch(pairwise_cipher)
++ {
++ case WPA_CIPHER_NONE:
++ padapter->securitypriv.dot11PrivacyAlgrthm=_NO_PRIVACY_;
++ padapter->securitypriv.ndisencryptstatus=Ndis802_11EncryptionDisabled;
++ break;
++ case WPA_CIPHER_WEP40:
++ padapter->securitypriv.dot11PrivacyAlgrthm=_WEP40_;
++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;
++ break;
++ case WPA_CIPHER_TKIP:
++ padapter->securitypriv.dot11PrivacyAlgrthm=_TKIP_;
++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption2Enabled;
++ break;
++ case WPA_CIPHER_CCMP:
++ padapter->securitypriv.dot11PrivacyAlgrthm=_AES_;
++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption3Enabled;
++ break;
++ case WPA_CIPHER_WEP104:
++ padapter->securitypriv.dot11PrivacyAlgrthm=_WEP104_;
++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;
++ break;
++ }
++
++ _clr_fwstate_(&padapter->mlmepriv, WIFI_UNDER_WPS);
++ {//set wps_ie
++ u16 cnt = 0;
++ u8 eid, wps_oui[4]={0x0,0x50,0xf2,0x04};
++
++ while( cnt < ielen )
++ {
++ eid = buf[cnt];
++
++ if((eid==_VENDOR_SPECIFIC_IE_)&&(_rtw_memcmp(&buf[cnt+2], wps_oui, 4)==_TRUE))
++ {
++ DBG_871X("SET WPS_IE\n");
++
++ padapter->securitypriv.wps_ie_len = ( (buf[cnt+1]+2) < (MAX_WPA_IE_LEN<<2)) ? (buf[cnt+1]+2):(MAX_WPA_IE_LEN<<2);
++
++ _rtw_memcpy(padapter->securitypriv.wps_ie, &buf[cnt], padapter->securitypriv.wps_ie_len);
++
++ set_fwstate(&padapter->mlmepriv, WIFI_UNDER_WPS);
++
++#ifdef CONFIG_P2P
++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_OK))
++ {
++ rtw_p2p_set_state(pwdinfo, P2P_STATE_PROVISIONING_ING);
++ }
++#endif //CONFIG_P2P
++ cnt += buf[cnt+1]+2;
++
++ break;
++ } else {
++ cnt += buf[cnt+1]+2; //goto next
++ }
++ }
++ }
++ }
++
++ //TKIP and AES disallow multicast packets until installing group key
++ if(padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_
++ || padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_WTMIC_
++ || padapter->securitypriv.dot11PrivacyAlgrthm == _AES_)
++ //WPS open need to enable multicast
++ //|| check_fwstate(&padapter->mlmepriv, WIFI_UNDER_WPS) == _TRUE)
++ rtw_hal_set_hwreg(padapter, HW_VAR_OFF_RCR_AM, null_addr);
++
++ RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_info_,
++ ("rtw_set_wpa_ie: pairwise_cipher=0x%08x padapter->securitypriv.ndisencryptstatus=%d padapter->securitypriv.ndisauthtype=%d\n",
++ pairwise_cipher, padapter->securitypriv.ndisencryptstatus, padapter->securitypriv.ndisauthtype));
++
++exit:
++
++ if (buf) rtw_mfree(buf, ielen);
++
++ return ret;
++}
++
++static int rtw_wx_get_name(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ u16 cap;
++ u32 ht_ielen = 0;
++ char *p;
++ u8 ht_cap=_FALSE;
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ WLAN_BSSID_EX *pcur_bss = &pmlmepriv->cur_network.network;
++ NDIS_802_11_RATES_EX* prates = NULL;
++
++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("cmd_code=%x\n", info->cmd));
++
++ _func_enter_;
++
++ if (check_fwstate(pmlmepriv, _FW_LINKED|WIFI_ADHOC_MASTER_STATE) == _TRUE)
++ {
++ //parsing HT_CAP_IE
++ p = rtw_get_ie(&pcur_bss->IEs[12], _HT_CAPABILITY_IE_, &ht_ielen, pcur_bss->IELength-12);
++ if(p && ht_ielen>0)
++ {
++ ht_cap = _TRUE;
++ }
++
++ prates = &pcur_bss->SupportedRates;
++
++ if (rtw_is_cckratesonly_included((u8*)prates) == _TRUE)
++ {
++ if(ht_cap == _TRUE)
++ snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11bn");
++ else
++ snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11b");
++ }
++ else if ((rtw_is_cckrates_included((u8*)prates)) == _TRUE)
++ {
++ if(ht_cap == _TRUE)
++ snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11bgn");
++ else
++ snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11bg");
++ }
++ else
++ {
++ if(pcur_bss->Configuration.DSConfig > 14)
++ {
++ if(ht_cap == _TRUE)
++ snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11an");
++ else
++ snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11a");
++ }
++ else
++ {
++ if(ht_cap == _TRUE)
++ snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11gn");
++ else
++ snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11g");
++ }
++ }
++ }
++ else
++ {
++ //prates = &padapter->registrypriv.dev_network.SupportedRates;
++ //snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11g");
++ snprintf(wrqu->name, IFNAMSIZ, "unassociated");
++ }
++
++ _func_exit_;
++
++ return 0;
++}
++
++static int rtw_wx_set_freq(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++ _func_enter_;
++
++ RT_TRACE(_module_rtl871x_mlme_c_, _drv_notice_, ("+rtw_wx_set_freq\n"));
++
++ _func_exit_;
++
++ return 0;
++}
++
++static int rtw_wx_get_freq(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ WLAN_BSSID_EX *pcur_bss = &pmlmepriv->cur_network.network;
++
++ if(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)
++ {
++ //wrqu->freq.m = ieee80211_wlan_frequencies[pcur_bss->Configuration.DSConfig-1] * 100000;
++ wrqu->freq.m = rtw_ch2freq(pcur_bss->Configuration.DSConfig) * 100000;
++ wrqu->freq.e = 1;
++ wrqu->freq.i = pcur_bss->Configuration.DSConfig;
++
++ }
++ else{
++ wrqu->freq.m = rtw_ch2freq(padapter->mlmeextpriv.cur_channel) * 100000;
++ wrqu->freq.e = 1;
++ wrqu->freq.i = padapter->mlmeextpriv.cur_channel;
++ }
++
++ return 0;
++}
++
++static int rtw_wx_set_mode(struct net_device *dev, struct iw_request_info *a,
++ union iwreq_data *wrqu, char *b)
++{
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ NDIS_802_11_NETWORK_INFRASTRUCTURE networkType ;
++ int ret = 0;
++ _irqL irqL;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ _queue *queue = &pmlmepriv->scanned_queue;
++ _func_enter_;
++
++ if(_FAIL == rtw_pwr_wakeup(padapter)) {
++ ret= -EPERM;
++ goto exit;
++ }
++
++ if (padapter->hw_init_completed==_FALSE){
++ ret = -EPERM;
++ goto exit;
++ }
++
++ switch(wrqu->mode)
++ {
++ case IW_MODE_AUTO:
++ networkType = Ndis802_11AutoUnknown;
++ DBG_871X("set_mode = IW_MODE_AUTO\n");
++ break;
++ case IW_MODE_ADHOC:
++ networkType = Ndis802_11IBSS;
++ DBG_871X("set_mode = IW_MODE_ADHOC\n");
++ break;
++ case IW_MODE_MASTER:
++ networkType = Ndis802_11APMode;
++ DBG_871X("set_mode = IW_MODE_MASTER\n");
++ //rtw_setopmode_cmd(padapter, networkType);
++ break;
++ case IW_MODE_INFRA:
++ networkType = Ndis802_11Infrastructure;
++ DBG_871X("set_mode = IW_MODE_INFRA\n");
++ break;
++
++ default :
++ ret = -EINVAL;;
++ RT_TRACE(_module_rtl871x_ioctl_os_c,_drv_err_,("\n Mode: %s is not supported \n", iw_operation_mode[wrqu->mode]));
++ goto exit;
++ }
++
++/*
++ if(Ndis802_11APMode == networkType)
++ {
++ rtw_setopmode_cmd(padapter, networkType);
++ }
++ else
++ {
++ rtw_setopmode_cmd(padapter, Ndis802_11AutoUnknown);
++ }
++*/
++ _enter_critical_bh(&pmlmepriv->lock, &irqL);
++ _enter_critical_bh(&queue->lock, &irqL);
++ if (rtw_set_802_11_infrastructure_mode(padapter, networkType) ==_FALSE){
++
++ ret = -EPERM;
++ _exit_critical_bh(&queue->lock, &irqL);
++ _exit_critical_bh(&pmlmepriv->lock, &irqL);
++ goto exit;
++
++ }
++ _exit_critical_bh(&queue->lock, &irqL);
++ _exit_critical_bh(&pmlmepriv->lock, &irqL);
++ rtw_setopmode_cmd(padapter, networkType);
++
++exit:
++
++ _func_exit_;
++
++ return ret;
++
++}
++
++static int rtw_wx_get_mode(struct net_device *dev, struct iw_request_info *a,
++ union iwreq_data *wrqu, char *b)
++{
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++
++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,(" rtw_wx_get_mode \n"));
++
++ _func_enter_;
++
++ if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)
++ {
++ wrqu->mode = IW_MODE_INFRA;
++ }
++ else if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) ||
++ (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE))
++
++ {
++ wrqu->mode = IW_MODE_ADHOC;
++ }
++ else if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE)
++ {
++ wrqu->mode = IW_MODE_MASTER;
++ }
++ else
++ {
++ wrqu->mode = IW_MODE_AUTO;
++ }
++
++ _func_exit_;
++
++ return 0;
++
++}
++
++
++static int rtw_wx_set_pmkid(struct net_device *dev,
++ struct iw_request_info *a,
++ union iwreq_data *wrqu, char *extra)
++{
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ u8 j,blInserted = _FALSE;
++ int intReturn = _FALSE;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct security_priv *psecuritypriv = &padapter->securitypriv;
++ struct iw_pmksa* pPMK = ( struct iw_pmksa* ) extra;
++ u8 strZeroMacAddress[ ETH_ALEN ] = { 0x00 };
++ u8 strIssueBssid[ ETH_ALEN ] = { 0x00 };
++
++/*
++ struct iw_pmksa
++ {
++ __u32 cmd;
++ struct sockaddr bssid;
++ __u8 pmkid[IW_PMKID_LEN]; //IW_PMKID_LEN=16
++ }
++ There are the BSSID information in the bssid.sa_data array.
++ If cmd is IW_PMKSA_FLUSH, it means the wpa_suppplicant wants to clear all the PMKID information.
++ If cmd is IW_PMKSA_ADD, it means the wpa_supplicant wants to add a PMKID/BSSID to driver.
++ If cmd is IW_PMKSA_REMOVE, it means the wpa_supplicant wants to remove a PMKID/BSSID from driver.
++ */
++
++ _rtw_memcpy( strIssueBssid, pPMK->bssid.sa_data, ETH_ALEN);
++ if ( pPMK->cmd == IW_PMKSA_ADD )
++ {
++ DBG_871X( "[rtw_wx_set_pmkid] IW_PMKSA_ADD!\n" );
++ if ( _rtw_memcmp( strIssueBssid, strZeroMacAddress, ETH_ALEN ) == _TRUE )
++ {
++ return( intReturn );
++ }
++ else
++ {
++ intReturn = _TRUE;
++ }
++ blInserted = _FALSE;
++
++ //overwrite PMKID
++ for(j=0 ; j<NUM_PMKID_CACHE; j++)
++ {
++ if( _rtw_memcmp( psecuritypriv->PMKIDList[j].Bssid, strIssueBssid, ETH_ALEN) ==_TRUE )
++ { // BSSID is matched, the same AP => rewrite with new PMKID.
++
++ DBG_871X( "[rtw_wx_set_pmkid] BSSID exists in the PMKList.\n" );
++
++ _rtw_memcpy( psecuritypriv->PMKIDList[j].PMKID, pPMK->pmkid, IW_PMKID_LEN);
++ psecuritypriv->PMKIDList[ j ].bUsed = _TRUE;
++ psecuritypriv->PMKIDIndex = j+1;
++ blInserted = _TRUE;
++ break;
++ }
++ }
++
++ if(!blInserted)
++ {
++ // Find a new entry
++ DBG_871X( "[rtw_wx_set_pmkid] Use the new entry index = %d for this PMKID.\n",
++ psecuritypriv->PMKIDIndex );
++
++ _rtw_memcpy(psecuritypriv->PMKIDList[psecuritypriv->PMKIDIndex].Bssid, strIssueBssid, ETH_ALEN);
++ _rtw_memcpy(psecuritypriv->PMKIDList[psecuritypriv->PMKIDIndex].PMKID, pPMK->pmkid, IW_PMKID_LEN);
++
++ psecuritypriv->PMKIDList[ psecuritypriv->PMKIDIndex ].bUsed = _TRUE;
++ psecuritypriv->PMKIDIndex++ ;
++ if(psecuritypriv->PMKIDIndex==16)
++ {
++ psecuritypriv->PMKIDIndex =0;
++ }
++ }
++ }
++ else if ( pPMK->cmd == IW_PMKSA_REMOVE )
++ {
++ DBG_871X( "[rtw_wx_set_pmkid] IW_PMKSA_REMOVE!\n" );
++ intReturn = _TRUE;
++ for(j=0 ; j<NUM_PMKID_CACHE; j++)
++ {
++ if( _rtw_memcmp( psecuritypriv->PMKIDList[j].Bssid, strIssueBssid, ETH_ALEN) ==_TRUE )
++ { // BSSID is matched, the same AP => Remove this PMKID information and reset it.
++ _rtw_memset( psecuritypriv->PMKIDList[ j ].Bssid, 0x00, ETH_ALEN );
++ psecuritypriv->PMKIDList[ j ].bUsed = _FALSE;
++ break;
++ }
++ }
++ }
++ else if ( pPMK->cmd == IW_PMKSA_FLUSH )
++ {
++ DBG_871X( "[rtw_wx_set_pmkid] IW_PMKSA_FLUSH!\n" );
++ _rtw_memset( &psecuritypriv->PMKIDList[ 0 ], 0x00, sizeof( RT_PMKID_LIST ) * NUM_PMKID_CACHE );
++ psecuritypriv->PMKIDIndex = 0;
++ intReturn = _TRUE;
++ }
++ return( intReturn );
++}
++
++static int rtw_wx_get_sens(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++ #ifdef CONFIG_PLATFORM_ROCKCHIPS
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++
++ /*
++ * 20110311 Commented by Jeff
++ * For rockchip platform's wpa_driver_wext_get_rssi
++ */
++ if(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) {
++ //wrqu->sens.value=-padapter->recvpriv.signal_strength;
++ wrqu->sens.value=-padapter->recvpriv.rssi;
++ //DBG_871X("%s: %d\n", __FUNCTION__, wrqu->sens.value);
++ wrqu->sens.fixed = 0; /* no auto select */
++ } else
++ #endif
++ {
++ wrqu->sens.value = 0;
++ wrqu->sens.fixed = 0; /* no auto select */
++ wrqu->sens.disabled = 1;
++ }
++ return 0;
++}
++
++static int rtw_wx_get_range(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++ struct iw_range *range = (struct iw_range *)extra;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++
++ u16 val;
++ int i;
++
++ _func_enter_;
++
++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("rtw_wx_get_range. cmd_code=%x\n", info->cmd));
++
++ wrqu->data.length = sizeof(*range);
++ _rtw_memset(range, 0, sizeof(*range));
++
++ /* Let's try to keep this struct in the same order as in
++ * linux/include/wireless.h
++ */
++
++ /* TODO: See what values we can set, and remove the ones we can't
++ * set, or fill them with some default data.
++ */
++
++ /* ~5 Mb/s real (802.11b) */
++ range->throughput = 5 * 1000 * 1000;
++
++ // TODO: Not used in 802.11b?
++// range->min_nwid; /* Minimal NWID we are able to set */
++ // TODO: Not used in 802.11b?
++// range->max_nwid; /* Maximal NWID we are able to set */
++
++ /* Old Frequency (backward compat - moved lower ) */
++// range->old_num_channels;
++// range->old_num_frequency;
++// range->old_freq[6]; /* Filler to keep "version" at the same offset */
++
++ /* signal level threshold range */
++
++ //percent values between 0 and 100.
++ range->max_qual.qual = 100;
++ range->max_qual.level = 100;
++ range->max_qual.noise = 100;
++ range->max_qual.updated = 7; /* Updated all three */
++
++
++ range->avg_qual.qual = 92; /* > 8% missed beacons is 'bad' */
++ /* TODO: Find real 'good' to 'bad' threshol value for RSSI */
++ range->avg_qual.level = 20 + -98;
++ range->avg_qual.noise = 0;
++ range->avg_qual.updated = 7; /* Updated all three */
++
++ range->num_bitrates = RATE_COUNT;
++
++ for (i = 0; i < RATE_COUNT && i < IW_MAX_BITRATES; i++) {
++ range->bitrate[i] = rtw_rates[i];
++ }
++
++ range->min_frag = MIN_FRAG_THRESHOLD;
++ range->max_frag = MAX_FRAG_THRESHOLD;
++
++ range->pm_capa = 0;
++
++ range->we_version_compiled = WIRELESS_EXT;
++ range->we_version_source = 16;
++
++// range->retry_capa; /* What retry options are supported */
++// range->retry_flags; /* How to decode max/min retry limit */
++// range->r_time_flags; /* How to decode max/min retry life */
++// range->min_retry; /* Minimal number of retries */
++// range->max_retry; /* Maximal number of retries */
++// range->min_r_time; /* Minimal retry lifetime */
++// range->max_r_time; /* Maximal retry lifetime */
++
++ for (i = 0, val = 0; i < MAX_CHANNEL_NUM; i++) {
++
++ // Include only legal frequencies for some countries
++ if(pmlmeext->channel_set[i].ChannelNum != 0)
++ {
++ range->freq[val].i = pmlmeext->channel_set[i].ChannelNum;
++ range->freq[val].m = rtw_ch2freq(pmlmeext->channel_set[i].ChannelNum) * 100000;
++ range->freq[val].e = 1;
++ val++;
++ }
++
++ if (val == IW_MAX_FREQUENCIES)
++ break;
++ }
++
++ range->num_channels = val;
++ range->num_frequency = val;
++
++// Commented by Albert 2009/10/13
++// The following code will proivde the security capability to network manager.
++// If the driver doesn't provide this capability to network manager,
++// the WPA/WPA2 routers can't be choosen in the network manager.
++
++/*
++#define IW_SCAN_CAPA_NONE 0x00
++#define IW_SCAN_CAPA_ESSID 0x01
++#define IW_SCAN_CAPA_BSSID 0x02
++#define IW_SCAN_CAPA_CHANNEL 0x04
++#define IW_SCAN_CAPA_MODE 0x08
++#define IW_SCAN_CAPA_RATE 0x10
++#define IW_SCAN_CAPA_TYPE 0x20
++#define IW_SCAN_CAPA_TIME 0x40
++*/
++
++#if WIRELESS_EXT > 17
++ range->enc_capa = IW_ENC_CAPA_WPA|IW_ENC_CAPA_WPA2|
++ IW_ENC_CAPA_CIPHER_TKIP|IW_ENC_CAPA_CIPHER_CCMP;
++#endif
++
++#ifdef IW_SCAN_CAPA_ESSID //WIRELESS_EXT > 21
++ range->scan_capa = IW_SCAN_CAPA_ESSID | IW_SCAN_CAPA_TYPE |IW_SCAN_CAPA_BSSID|
++ IW_SCAN_CAPA_CHANNEL|IW_SCAN_CAPA_MODE|IW_SCAN_CAPA_RATE;
++#endif
++
++
++ _func_exit_;
++
++ return 0;
++
++}
++
++//set bssid flow
++//s1. rtw_set_802_11_infrastructure_mode()
++//s2. rtw_set_802_11_authentication_mode()
++//s3. set_802_11_encryption_mode()
++//s4. rtw_set_802_11_bssid()
++static int rtw_wx_set_wap(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *awrq,
++ char *extra)
++{
++ _irqL irqL;
++ uint ret = 0;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct sockaddr *temp = (struct sockaddr *)awrq;
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ _list *phead;
++ u8 *dst_bssid, *src_bssid;
++ _queue *queue = &(pmlmepriv->scanned_queue);
++ struct wlan_network *pnetwork = NULL;
++ NDIS_802_11_AUTHENTICATION_MODE authmode;
++
++ _func_enter_;
++/*
++#ifdef CONFIG_CONCURRENT_MODE
++ if(padapter->iface_type > PRIMARY_IFACE)
++ {
++ ret = -EINVAL;
++ goto exit;
++ }
++#endif
++*/
++
++#ifdef CONFIG_CONCURRENT_MODE
++ if (check_buddy_fwstate(padapter, _FW_UNDER_SURVEY|_FW_UNDER_LINKING) == _TRUE)
++ {
++ printk("set bssid, but buddy_intf is under scanning or linking\n");
++
++ ret = -EINVAL;
++
++ goto exit;
++ }
++#endif
++
++#ifdef CONFIG_DUALMAC_CONCURRENT
++ if (dc_check_fwstate(padapter, _FW_UNDER_SURVEY|_FW_UNDER_LINKING)== _TRUE)
++ {
++ printk("set bssid, but buddy_intf is under scanning or linking\n");
++ ret = -EINVAL;
++ goto exit;
++ }
++#endif
++
++ if(_FAIL == rtw_pwr_wakeup(padapter))
++ {
++ ret= -1;
++ goto exit;
++ }
++
++ if(!padapter->bup){
++ ret = -1;
++ goto exit;
++ }
++
++
++ if (temp->sa_family != ARPHRD_ETHER){
++ ret = -EINVAL;
++ goto exit;
++ }
++
++ authmode = padapter->securitypriv.ndisauthtype;
++ _enter_critical_bh(&pmlmepriv->lock, &irqL);
++ _enter_critical_bh(&queue->lock, &irqL);
++ phead = get_list_head(queue);
++ pmlmepriv->pscanned = get_next(phead);
++
++ while (1)
++ {
++
++ if ((rtw_end_of_queue_search(phead, pmlmepriv->pscanned)) == _TRUE)
++ {
++#if 0
++ ret = -EINVAL;
++ goto exit;
++
++ if(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE)
++ {
++ rtw_set_802_11_bssid(padapter, temp->sa_data);
++ goto exit;
++ }
++ else
++ {
++ ret = -EINVAL;
++ goto exit;
++ }
++#endif
++
++ break;
++ }
++
++ pnetwork = LIST_CONTAINOR(pmlmepriv->pscanned, struct wlan_network, list);
++
++ pmlmepriv->pscanned = get_next(pmlmepriv->pscanned);
++
++ dst_bssid = pnetwork->network.MacAddress;
++
++ src_bssid = temp->sa_data;
++
++ if ((_rtw_memcmp(dst_bssid, src_bssid, ETH_ALEN)) == _TRUE)
++ {
++ if(!rtw_set_802_11_infrastructure_mode(padapter, pnetwork->network.InfrastructureMode))
++ {
++ ret = -1;
++ _exit_critical_bh(&queue->lock, &irqL);
++ _exit_critical_bh(&pmlmepriv->lock, &irqL);
++ goto exit;
++ }
++
++ break;
++ }
++
++ }
++ _exit_critical_bh(&queue->lock, &irqL);
++ _exit_critical_bh(&pmlmepriv->lock, &irqL);
++ rtw_set_802_11_authentication_mode(padapter, authmode);
++ //set_802_11_encryption_mode(padapter, padapter->securitypriv.ndisencryptstatus);
++ if (rtw_set_802_11_bssid(padapter, temp->sa_data) == _FALSE) {
++ ret = -1;
++ goto exit;
++ }
++
++exit:
++
++ _func_exit_;
++
++ return ret;
++}
++
++static int rtw_wx_get_wap(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ WLAN_BSSID_EX *pcur_bss = &pmlmepriv->cur_network.network;
++
++ wrqu->ap_addr.sa_family = ARPHRD_ETHER;
++
++ _rtw_memset(wrqu->ap_addr.sa_data, 0, ETH_ALEN);
++
++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("rtw_wx_get_wap\n"));
++
++ _func_enter_;
++
++ if ( ((check_fwstate(pmlmepriv, _FW_LINKED)) == _TRUE) ||
++ ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)) == _TRUE) ||
++ ((check_fwstate(pmlmepriv, WIFI_AP_STATE)) == _TRUE) )
++ {
++
++ _rtw_memcpy(wrqu->ap_addr.sa_data, pcur_bss->MacAddress, ETH_ALEN);
++ }
++ else
++ {
++ _rtw_memset(wrqu->ap_addr.sa_data, 0, ETH_ALEN);
++ }
++
++ _func_exit_;
++
++ return 0;
++
++}
++
++static int rtw_wx_set_mlme(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++#if 0
++/* SIOCSIWMLME data */
++struct iw_mlme
++{
++ __u16 cmd; /* IW_MLME_* */
++ __u16 reason_code;
++ struct sockaddr addr;
++};
++#endif
++
++ int ret=0;
++ u16 reason;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct iw_mlme *mlme = (struct iw_mlme *) extra;
++
++
++ if(mlme==NULL)
++ return -1;
++
++ printk("%s\n", __FUNCTION__);
++
++ reason = cpu_to_le16(mlme->reason_code);
++
++
++ printk("%s, cmd=%d, reason=%d\n", __FUNCTION__, mlme->cmd, reason);
++
++ switch (mlme->cmd)
++ {
++ case IW_MLME_DEAUTH:
++ if(!rtw_set_802_11_disassociate(padapter))
++ ret = -1;
++ break;
++
++ case IW_MLME_DISASSOC:
++ if(!rtw_set_802_11_disassociate(padapter))
++ ret = -1;
++
++ break;
++
++ default:
++ return -EOPNOTSUPP;
++ }
++
++ return ret;
++
++}
++
++static int rtw_wx_set_scan(struct net_device *dev, struct iw_request_info *a,
++ union iwreq_data *wrqu, char *extra)
++{
++ u8 _status = _FALSE;
++ int ret = 0;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct mlme_priv *pmlmepriv= &padapter->mlmepriv;
++ NDIS_802_11_SSID ssid[RTW_SSID_SCAN_AMOUNT];
++ _irqL irqL;
++#ifdef CONFIG_P2P
++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo);
++#endif //CONFIG_P2P
++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("rtw_wx_set_scan\n"));
++
++_func_enter_;
++
++ #ifdef DBG_IOCTL
++ DBG_871X("DBG_IOCTL %s:%d\n",__FUNCTION__, __LINE__);
++ #endif
++/*
++#ifdef CONFIG_CONCURRENT_MODE
++ if(padapter->iface_type > PRIMARY_IFACE)
++ {
++ ret = -1;
++ goto exit;
++ }
++#endif
++*/
++
++#ifdef CONFIG_MP_INCLUDED
++ if (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE)
++ {
++ ret = -1;
++ goto exit;
++ }
++#endif
++
++ if(_FAIL == rtw_pwr_wakeup(padapter))
++ {
++ ret= -1;
++ goto exit;
++ }
++
++ if(padapter->bDriverStopped){
++ DBG_871X("bDriverStopped=%d\n", padapter->bDriverStopped);
++ ret= -1;
++ goto exit;
++ }
++
++ if(!padapter->bup){
++ ret = -1;
++ goto exit;
++ }
++
++ if (padapter->hw_init_completed==_FALSE){
++ ret = -1;
++ goto exit;
++ }
++
++ // When Busy Traffic, driver do not site survey. So driver return success.
++ // wpa_supplicant will not issue SIOCSIWSCAN cmd again after scan timeout.
++ // modify by thomas 2011-02-22.
++ if (pmlmepriv->LinkDetectInfo.bBusyTraffic == _TRUE)
++ {
++ indicate_wx_scan_complete_event(padapter);
++ goto exit;
++ }
++
++ if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY|_FW_UNDER_LINKING) == _TRUE)
++ {
++ indicate_wx_scan_complete_event(padapter);
++ goto exit;
++ }
++
++#ifdef CONFIG_CONCURRENT_MODE
++ if (check_buddy_fwstate(padapter,
++ _FW_UNDER_SURVEY|_FW_UNDER_LINKING|WIFI_UNDER_WPS) == _TRUE)
++ {
++ if(check_buddy_fwstate(padapter, _FW_UNDER_SURVEY))
++ {
++ printk("scanning_via_buddy_intf\n");
++ pmlmepriv->scanning_via_buddy_intf = _TRUE;
++ }
++
++ indicate_wx_scan_complete_event(padapter);
++
++ goto exit;
++ }
++#endif
++
++#ifdef CONFIG_DUALMAC_CONCURRENT
++ if (dc_check_fwstate(padapter, _FW_UNDER_SURVEY|_FW_UNDER_LINKING)== _TRUE)
++ {
++ indicate_wx_scan_complete_event(padapter);
++ goto exit;
++ }
++#endif
++
++// Mareded by Albert 20101103
++// For the DMP WiFi Display project, the driver won't to scan because
++// the pmlmepriv->scan_interval is always equal to 3.
++// So, the wpa_supplicant won't find out the WPS SoftAP.
++
++/*
++ if(pmlmepriv->scan_interval>10)
++ pmlmepriv->scan_interval = 0;
++
++ if(pmlmepriv->scan_interval > 0)
++ {
++ DBG_871X("scan done\n");
++ ret = 0;
++ goto exit;
++ }
++
++*/
++#ifdef CONFIG_P2P
++ if(!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
++ {
++ rtw_p2p_set_pre_state( pwdinfo, rtw_p2p_state( pwdinfo ) );
++ rtw_p2p_set_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH);
++ rtw_p2p_findphase_ex_set(pwdinfo, P2P_FINDPHASE_EX_FULL);
++ rtw_free_network_queue(padapter, _TRUE);
++ }
++#endif //CONFIG_P2P
++
++ _rtw_memset(ssid, 0, sizeof(NDIS_802_11_SSID)*RTW_SSID_SCAN_AMOUNT);
++
++#if WIRELESS_EXT >= 17
++ if (wrqu->data.length == sizeof(struct iw_scan_req))
++ {
++ struct iw_scan_req *req = (struct iw_scan_req *)extra;
++
++ if (wrqu->data.flags & IW_SCAN_THIS_ESSID)
++ {
++ int len = min((int)req->essid_len, IW_ESSID_MAX_SIZE);
++
++ _rtw_memcpy(ssid[0].Ssid, req->essid, len);
++ ssid[0].SsidLength = len;
++
++ DBG_871X("IW_SCAN_THIS_ESSID, ssid=%s, len=%d\n", req->essid, req->essid_len);
++
++ _enter_critical_bh(&pmlmepriv->lock, &irqL);
++
++ _status = rtw_sitesurvey_cmd(padapter, ssid, 1, NULL, 0);
++
++ _exit_critical_bh(&pmlmepriv->lock, &irqL);
++
++ }
++ else if (req->scan_type == IW_SCAN_TYPE_PASSIVE)
++ {
++ DBG_871X("rtw_wx_set_scan, req->scan_type == IW_SCAN_TYPE_PASSIVE\n");
++ }
++
++ }
++ else
++#endif
++
++ if( wrqu->data.length >= WEXT_CSCAN_HEADER_SIZE
++ && _rtw_memcmp(extra, WEXT_CSCAN_HEADER, WEXT_CSCAN_HEADER_SIZE) == _TRUE
++ )
++ {
++ int len = wrqu->data.length -WEXT_CSCAN_HEADER_SIZE;
++ char *pos = extra+WEXT_CSCAN_HEADER_SIZE;
++ char section;
++ char sec_len;
++ int ssid_index = 0;
++
++ //DBG_871X("%s COMBO_SCAN header is recognized\n", __FUNCTION__);
++
++ while(len >= 1) {
++ section = *(pos++); len-=1;
++
++ switch(section) {
++ case WEXT_CSCAN_SSID_SECTION:
++ //DBG_871X("WEXT_CSCAN_SSID_SECTION\n");
++ if(len < 1) {
++ len = 0;
++ break;
++ }
++
++ sec_len = *(pos++); len-=1;
++
++ if(sec_len>0 && sec_len<=len) {
++ ssid[ssid_index].SsidLength = sec_len;
++ _rtw_memcpy(ssid[ssid_index].Ssid, pos, ssid[ssid_index].SsidLength);
++ //DBG_871X("%s COMBO_SCAN with specific ssid:%s, %d\n", __FUNCTION__
++ // , ssid[ssid_index].Ssid, ssid[ssid_index].SsidLength);
++ ssid_index++;
++ }
++
++ pos+=sec_len; len-=sec_len;
++ break;
++
++
++ case WEXT_CSCAN_CHANNEL_SECTION:
++ //DBG_871X("WEXT_CSCAN_CHANNEL_SECTION\n");
++ pos+=1; len-=1;
++ break;
++ case WEXT_CSCAN_ACTV_DWELL_SECTION:
++ //DBG_871X("WEXT_CSCAN_ACTV_DWELL_SECTION\n");
++ pos+=2; len-=2;
++ break;
++ case WEXT_CSCAN_PASV_DWELL_SECTION:
++ //DBG_871X("WEXT_CSCAN_PASV_DWELL_SECTION\n");
++ pos+=2; len-=2;
++ break;
++ case WEXT_CSCAN_HOME_DWELL_SECTION:
++ //DBG_871X("WEXT_CSCAN_HOME_DWELL_SECTION\n");
++ pos+=2; len-=2;
++ break;
++ case WEXT_CSCAN_TYPE_SECTION:
++ //DBG_871X("WEXT_CSCAN_TYPE_SECTION\n");
++ pos+=1; len-=1;
++ break;
++ #if 0
++ case WEXT_CSCAN_NPROBE_SECTION:
++ DBG_871X("WEXT_CSCAN_NPROBE_SECTION\n");
++ break;
++ #endif
++
++ default:
++ //DBG_871X("Unknown CSCAN section %c\n", section);
++ len = 0; // stop parsing
++ }
++ //DBG_871X("len:%d\n", len);
++
++ }
++
++ //jeff: it has still some scan paramater to parse, we only do this now...
++ _status = rtw_set_802_11_bssid_list_scan(padapter, ssid, RTW_SSID_SCAN_AMOUNT);
++
++ } else
++
++ {
++ _status = rtw_set_802_11_bssid_list_scan(padapter, NULL, 0);
++ }
++
++ if(_status == _FALSE)
++ ret = -1;
++
++exit:
++ #ifdef DBG_IOCTL
++ DBG_871X("DBG_IOCTL %s:%d return %d\n",__FUNCTION__, __LINE__, ret);
++ #endif
++
++_func_exit_;
++
++ return ret;
++}
++
++static int rtw_wx_get_scan(struct net_device *dev, struct iw_request_info *a,
++ union iwreq_data *wrqu, char *extra)
++{
++ _irqL irqL;
++ _list *plist, *phead;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ _queue *queue = &(pmlmepriv->scanned_queue);
++ struct wlan_network *pnetwork = NULL;
++ char *ev = extra;
++ char *stop = ev + wrqu->data.length;
++ u32 ret = 0;
++ u32 cnt=0;
++ u32 wait_for_surveydone;
++ sint wait_status;
++#ifdef CONFIG_CONCURRENT_MODE
++ //PADAPTER pbuddy_adapter = padapter->pbuddy_adapter;
++ //struct mlme_priv *pbuddy_mlmepriv = &(pbuddy_adapter->mlmepriv);
++#endif
++#ifdef CONFIG_P2P
++ struct wifidirect_info* pwdinfo = &padapter->wdinfo;
++#endif //CONFIG_P2P
++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("rtw_wx_get_scan\n"));
++ RT_TRACE(_module_rtl871x_ioctl_os_c,_drv_info_, (" Start of Query SIOCGIWSCAN .\n"));
++
++ _func_enter_;
++
++ #ifdef DBG_IOCTL
++ DBG_871X("DBG_IOCTL %s:%d\n",__FUNCTION__, __LINE__);
++ #endif
++
++/*
++#ifdef CONFIG_CONCURRENT_MODE
++ if(padapter->iface_type > PRIMARY_IFACE)
++ {
++ ret = -EINVAL;
++ goto exit;
++ }
++#endif
++*/
++ if(padapter->pwrctrlpriv.brfoffbyhw && padapter->bDriverStopped)
++ {
++ ret = -EINVAL;
++ goto exit;
++ }
++
++#ifdef CONFIG_P2P
++ if(!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
++ {
++ // P2P is enabled
++ if ( padapter->chip_type == RTL8192D )
++ wait_for_surveydone = 300; // Because the 8192du supports more channels.
++ else
++ wait_for_surveydone = 200;
++ }
++ else
++ {
++ // P2P is disabled
++ wait_for_surveydone = 100;
++ }
++#else
++ {
++ wait_for_surveydone = 100;
++ }
++#endif //CONFIG_P2P
++
++/*
++#ifdef CONFIG_CONCURRENT_MODE
++ if(pmlmepriv->scanning_via_buddy_intf == _TRUE)
++ {
++ pmlmepriv->scanning_via_buddy_intf = _FALSE;//reset
++
++ // change pointers to buddy interface
++ padapter = pbuddy_adapter;
++ pmlmepriv = pbuddy_mlmepriv;
++ queue = &(pbuddy_mlmepriv->scanned_queue);
++
++ }
++#endif // CONFIG_CONCURRENT_MODE
++*/
++
++ wait_status = _FW_UNDER_SURVEY
++ #ifndef CONFIG_ANDROID
++ |_FW_UNDER_LINKING
++ #endif
++ ;
++
++#ifdef CONFIG_DUALMAC_CONCURRENT
++ while(dc_check_fwstate(padapter, wait_status)== _TRUE)
++ {
++ rtw_msleep_os(30);
++ cnt++;
++ if(cnt > wait_for_surveydone )
++ break;
++ }
++#endif // CONFIG_DUALMAC_CONCURRENT
++
++ while(check_fwstate(pmlmepriv, wait_status) == _TRUE)
++ {
++ rtw_msleep_os(30);
++ cnt++;
++ if(cnt > wait_for_surveydone )
++ break;
++ }
++
++ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++
++ phead = get_list_head(queue);
++ plist = get_next(phead);
++
++ while(1)
++ {
++ if (rtw_end_of_queue_search(phead,plist)== _TRUE)
++ break;
++
++ if((stop - ev) < SCAN_ITEM_SIZE) {
++ ret = -E2BIG;
++ break;
++ }
++
++ pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
++
++ //report network only if the current channel set contains the channel to which this network belongs
++ if(rtw_ch_set_search_ch(padapter->mlmeextpriv.channel_set, pnetwork->network.Configuration.DSConfig) >= 0
++ && rtw_mlme_band_check(padapter, pnetwork->network.Configuration.DSConfig) == _TRUE
++ && _TRUE == rtw_validate_ssid(&(pnetwork->network.Ssid))
++ )
++ {
++ ev=translate_scan(padapter, a, pnetwork, ev, stop);
++ }
++
++ plist = get_next(plist);
++
++ }
++
++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++
++ wrqu->data.length = ev-extra;
++ wrqu->data.flags = 0;
++
++exit:
++
++ _func_exit_;
++
++ #ifdef DBG_IOCTL
++ DBG_871X("DBG_IOCTL %s:%d return %d\n",__FUNCTION__, __LINE__, ret);
++ #endif
++
++ return ret ;
++
++}
++
++//set ssid flow
++//s1. rtw_set_802_11_infrastructure_mode()
++//s2. set_802_11_authenticaion_mode()
++//s3. set_802_11_encryption_mode()
++//s4. rtw_set_802_11_ssid()
++static int rtw_wx_set_essid(struct net_device *dev,
++ struct iw_request_info *a,
++ union iwreq_data *wrqu, char *extra)
++{
++ _irqL irqL;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ _queue *queue = &pmlmepriv->scanned_queue;
++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
++ _list *phead;
++ s8 status = _TRUE;
++ struct wlan_network *pnetwork = NULL;
++ NDIS_802_11_AUTHENTICATION_MODE authmode;
++ NDIS_802_11_SSID ndis_ssid;
++ u8 *dst_ssid, *src_ssid;
++
++ uint ret = 0, len;
++
++ _func_enter_;
++
++ #ifdef DBG_IOCTL
++ DBG_871X("DBG_IOCTL %s:%d\n",__FUNCTION__, __LINE__);
++ #endif
++
++/*
++#ifdef CONFIG_CONCURRENT_MODE
++ if(padapter->iface_type > PRIMARY_IFACE)
++ {
++ ret = -EINVAL;
++ goto exit;
++ }
++#endif
++*/
++
++#ifdef CONFIG_CONCURRENT_MODE
++ if (check_buddy_fwstate(padapter, _FW_UNDER_SURVEY|_FW_UNDER_LINKING) == _TRUE)
++ {
++ printk("set ssid, but buddy_intf is under scanning or linking\n");
++
++ ret = -EINVAL;
++
++ goto exit;
++ }
++#endif
++
++#ifdef CONFIG_DUALMAC_CONCURRENT
++ if (dc_check_fwstate(padapter, _FW_UNDER_SURVEY|_FW_UNDER_LINKING)== _TRUE)
++ {
++ printk("set bssid, but buddy_intf is under scanning or linking\n");
++ ret = -EINVAL;
++ goto exit;
++ }
++#endif
++
++ RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_info_,
++ ("+rtw_wx_set_essid: fw_state=0x%08x\n", get_fwstate(pmlmepriv)));
++ if(_FAIL == rtw_pwr_wakeup(padapter))
++ {
++ ret = -1;
++ goto exit;
++ }
++
++ if(!padapter->bup){
++ ret = -1;
++ goto exit;
++ }
++
++#if WIRELESS_EXT <= 20
++ if ((wrqu->essid.length-1) > IW_ESSID_MAX_SIZE){
++#else
++ if (wrqu->essid.length > IW_ESSID_MAX_SIZE){
++#endif
++ ret= -E2BIG;
++ goto exit;
++ }
++
++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE)) {
++ ret = -1;
++ goto exit;
++ }
++
++ authmode = padapter->securitypriv.ndisauthtype;
++ DBG_871X("=>%s\n",__FUNCTION__);
++ if (wrqu->essid.flags && wrqu->essid.length)
++ {
++ // Commented by Albert 20100519
++ // We got the codes in "set_info" function of iwconfig source code.
++ // =========================================
++ // wrq.u.essid.length = strlen(essid) + 1;
++ // if(we_kernel_version > 20)
++ // wrq.u.essid.length--;
++ // =========================================
++ // That means, if the WIRELESS_EXT less than or equal to 20, the correct ssid len should subtract 1.
++#if WIRELESS_EXT <= 20
++ len = ((wrqu->essid.length-1) < IW_ESSID_MAX_SIZE) ? (wrqu->essid.length-1) : IW_ESSID_MAX_SIZE;
++#else
++ len = (wrqu->essid.length < IW_ESSID_MAX_SIZE) ? wrqu->essid.length : IW_ESSID_MAX_SIZE;
++#endif
++
++ if( wrqu->essid.length != 33 )
++ DBG_871X("ssid=%s, len=%d\n", extra, wrqu->essid.length);
++
++ _rtw_memset(&ndis_ssid, 0, sizeof(NDIS_802_11_SSID));
++ ndis_ssid.SsidLength = len;
++ _rtw_memcpy(ndis_ssid.Ssid, extra, len);
++ src_ssid = ndis_ssid.Ssid;
++
++ RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_info_, ("rtw_wx_set_essid: ssid=[%s]\n", src_ssid));
++ _enter_critical_bh(&pmlmepriv->lock, &irqL);
++ _enter_critical_bh(&queue->lock, &irqL);
++ phead = get_list_head(queue);
++ pmlmepriv->pscanned = get_next(phead);
++
++ while (1)
++ {
++ if (rtw_end_of_queue_search(phead, pmlmepriv->pscanned) == _TRUE)
++ {
++#if 0
++ if(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE)
++ {
++ rtw_set_802_11_ssid(padapter, &ndis_ssid);
++
++ goto exit;
++ }
++ else
++ {
++ RT_TRACE(_module_rtl871x_ioctl_os_c,_drv_info_,("rtw_wx_set_ssid(): scanned_queue is empty\n"));
++ ret = -EINVAL;
++ goto exit;
++ }
++#endif
++ RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_warning_,
++ ("rtw_wx_set_essid: scan_q is empty, set ssid to check if scanning again!\n"));
++
++ break;
++ }
++
++ pnetwork = LIST_CONTAINOR(pmlmepriv->pscanned, struct wlan_network, list);
++
++ pmlmepriv->pscanned = get_next(pmlmepriv->pscanned);
++
++ dst_ssid = pnetwork->network.Ssid.Ssid;
++
++ RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_info_,
++ ("rtw_wx_set_essid: dst_ssid=%s\n",
++ pnetwork->network.Ssid.Ssid));
++
++ if ((_rtw_memcmp(dst_ssid, src_ssid, ndis_ssid.SsidLength) == _TRUE) &&
++ (pnetwork->network.Ssid.SsidLength==ndis_ssid.SsidLength))
++ {
++ RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_info_,
++ ("rtw_wx_set_essid: find match, set infra mode\n"));
++
++ if(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE)
++ {
++ if(pnetwork->network.InfrastructureMode != pmlmepriv->cur_network.network.InfrastructureMode)
++ continue;
++ }
++
++ if (rtw_set_802_11_infrastructure_mode(padapter, pnetwork->network.InfrastructureMode) == _FALSE)
++ {
++ ret = -1;
++ _exit_critical_bh(&queue->lock, &irqL);
++ _exit_critical_bh(&pmlmepriv->lock, &irqL);
++ goto exit;
++ }
++
++ break;
++ }
++ }
++ _exit_critical_bh(&queue->lock, &irqL);
++ _exit_critical_bh(&pmlmepriv->lock, &irqL);
++ RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_info_,
++ ("set ssid: set_802_11_auth. mode=%d\n", authmode));
++ rtw_set_802_11_authentication_mode(padapter, authmode);
++ //set_802_11_encryption_mode(padapter, padapter->securitypriv.ndisencryptstatus);
++ if (rtw_set_802_11_ssid(padapter, &ndis_ssid) == _FALSE) {
++ ret = -1;
++ goto exit;
++ }
++ }
++
++exit:
++
++ DBG_871X("<=%s, ret %d\n",__FUNCTION__, ret);
++
++ #ifdef DBG_IOCTL
++ DBG_871X("DBG_IOCTL %s:%d return %d\n",__FUNCTION__, __LINE__, ret);
++ #endif
++
++ _func_exit_;
++
++ return ret;
++}
++
++static int rtw_wx_get_essid(struct net_device *dev,
++ struct iw_request_info *a,
++ union iwreq_data *wrqu, char *extra)
++{
++ u32 len,ret = 0;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ WLAN_BSSID_EX *pcur_bss = &pmlmepriv->cur_network.network;
++
++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("rtw_wx_get_essid\n"));
++
++ _func_enter_;
++
++ if ( (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) ||
++ (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE))
++ {
++ len = pcur_bss->Ssid.SsidLength;
++
++ wrqu->essid.length = len;
++
++ _rtw_memcpy(extra, pcur_bss->Ssid.Ssid, len);
++
++ wrqu->essid.flags = 1;
++ }
++ else
++ {
++ ret = -1;
++ goto exit;
++ }
++
++exit:
++
++ _func_exit_;
++
++ return ret;
++
++}
++
++static int rtw_wx_set_rate(struct net_device *dev,
++ struct iw_request_info *a,
++ union iwreq_data *wrqu, char *extra)
++{
++ int i, ret = 0;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ u8 datarates[NumRates];
++ u32 target_rate = wrqu->bitrate.value;
++ u32 fixed = wrqu->bitrate.fixed;
++ u32 ratevalue = 0;
++ u8 mpdatarate[NumRates]={11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, 0xff};
++
++_func_enter_;
++
++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,(" rtw_wx_set_rate \n"));
++ RT_TRACE(_module_rtl871x_ioctl_os_c,_drv_info_,("target_rate = %d, fixed = %d\n",target_rate,fixed));
++
++ if(target_rate == -1){
++ ratevalue = 11;
++ goto set_rate;
++ }
++ target_rate = target_rate/100000;
++
++ switch(target_rate){
++ case 10:
++ ratevalue = 0;
++ break;
++ case 20:
++ ratevalue = 1;
++ break;
++ case 55:
++ ratevalue = 2;
++ break;
++ case 60:
++ ratevalue = 3;
++ break;
++ case 90:
++ ratevalue = 4;
++ break;
++ case 110:
++ ratevalue = 5;
++ break;
++ case 120:
++ ratevalue = 6;
++ break;
++ case 180:
++ ratevalue = 7;
++ break;
++ case 240:
++ ratevalue = 8;
++ break;
++ case 360:
++ ratevalue = 9;
++ break;
++ case 480:
++ ratevalue = 10;
++ break;
++ case 540:
++ ratevalue = 11;
++ break;
++ default:
++ ratevalue = 11;
++ break;
++ }
++
++set_rate:
++
++ for(i=0; i<NumRates; i++)
++ {
++ if(ratevalue==mpdatarate[i])
++ {
++ datarates[i] = mpdatarate[i];
++ if(fixed == 0)
++ break;
++ }
++ else{
++ datarates[i] = 0xff;
++ }
++
++ RT_TRACE(_module_rtl871x_ioctl_os_c,_drv_info_,("datarate_inx=%d\n",datarates[i]));
++ }
++
++ if( rtw_setdatarate_cmd(padapter, datarates) !=_SUCCESS){
++ RT_TRACE(_module_rtl871x_ioctl_os_c,_drv_err_,("rtw_wx_set_rate Fail!!!\n"));
++ ret = -1;
++ }
++
++_func_exit_;
++
++ return ret;
++}
++
++static int rtw_wx_get_rate(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++ u16 max_rate = 0;
++
++ max_rate = rtw_get_cur_max_rate((_adapter *)rtw_netdev_priv(dev));
++
++ if(max_rate == 0)
++ return -EPERM;
++
++ wrqu->bitrate.fixed = 0; /* no auto select */
++ wrqu->bitrate.value = max_rate * 100000;
++
++ return 0;
++}
++
++static int rtw_wx_set_rts(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++
++ _func_enter_;
++
++ if (wrqu->rts.disabled)
++ padapter->registrypriv.rts_thresh = 2347;
++ else {
++ if (wrqu->rts.value < 0 ||
++ wrqu->rts.value > 2347)
++ return -EINVAL;
++
++ padapter->registrypriv.rts_thresh = wrqu->rts.value;
++ }
++
++ DBG_871X("%s, rts_thresh=%d\n", __func__, padapter->registrypriv.rts_thresh);
++
++ _func_exit_;
++
++ return 0;
++
++}
++
++static int rtw_wx_get_rts(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++
++ _func_enter_;
++
++ DBG_871X("%s, rts_thresh=%d\n", __func__, padapter->registrypriv.rts_thresh);
++
++ wrqu->rts.value = padapter->registrypriv.rts_thresh;
++ wrqu->rts.fixed = 0; /* no auto select */
++ //wrqu->rts.disabled = (wrqu->rts.value == DEFAULT_RTS_THRESHOLD);
++
++ _func_exit_;
++
++ return 0;
++}
++
++static int rtw_wx_set_frag(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++
++ _func_enter_;
++
++ if (wrqu->frag.disabled)
++ padapter->xmitpriv.frag_len = MAX_FRAG_THRESHOLD;
++ else {
++ if (wrqu->frag.value < MIN_FRAG_THRESHOLD ||
++ wrqu->frag.value > MAX_FRAG_THRESHOLD)
++ return -EINVAL;
++
++ padapter->xmitpriv.frag_len = wrqu->frag.value & ~0x1;
++ }
++
++ DBG_871X("%s, frag_len=%d\n", __func__, padapter->xmitpriv.frag_len);
++
++ _func_exit_;
++
++ return 0;
++
++}
++
++static int rtw_wx_get_frag(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++
++ _func_enter_;
++
++ DBG_871X("%s, frag_len=%d\n", __func__, padapter->xmitpriv.frag_len);
++
++ wrqu->frag.value = padapter->xmitpriv.frag_len;
++ wrqu->frag.fixed = 0; /* no auto select */
++ //wrqu->frag.disabled = (wrqu->frag.value == DEFAULT_FRAG_THRESHOLD);
++
++ _func_exit_;
++
++ return 0;
++}
++
++static int rtw_wx_get_retry(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++ //_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++
++
++ wrqu->retry.value = 7;
++ wrqu->retry.fixed = 0; /* no auto select */
++ wrqu->retry.disabled = 1;
++
++ return 0;
++
++}
++
++#if 0
++#define IW_ENCODE_INDEX 0x00FF /* Token index (if needed) */
++#define IW_ENCODE_FLAGS 0xFF00 /* Flags defined below */
++#define IW_ENCODE_MODE 0xF000 /* Modes defined below */
++#define IW_ENCODE_DISABLED 0x8000 /* Encoding disabled */
++#define IW_ENCODE_ENABLED 0x0000 /* Encoding enabled */
++#define IW_ENCODE_RESTRICTED 0x4000 /* Refuse non-encoded packets */
++#define IW_ENCODE_OPEN 0x2000 /* Accept non-encoded packets */
++#define IW_ENCODE_NOKEY 0x0800 /* Key is write only, so not present */
++#define IW_ENCODE_TEMP 0x0400 /* Temporary key */
++/*
++iwconfig wlan0 key on -> flags = 0x6001 -> maybe it means auto
++iwconfig wlan0 key off -> flags = 0x8800
++iwconfig wlan0 key open -> flags = 0x2800
++iwconfig wlan0 key open 1234567890 -> flags = 0x2000
++iwconfig wlan0 key restricted -> flags = 0x4800
++iwconfig wlan0 key open [3] 1234567890 -> flags = 0x2003
++iwconfig wlan0 key restricted [2] 1234567890 -> flags = 0x4002
++iwconfig wlan0 key open [3] -> flags = 0x2803
++iwconfig wlan0 key restricted [2] -> flags = 0x4802
++*/
++#endif
++
++static int rtw_wx_set_enc(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *keybuf)
++{
++ u32 key, ret = 0;
++ u32 keyindex_provided;
++ NDIS_802_11_WEP wep;
++ NDIS_802_11_AUTHENTICATION_MODE authmode;
++
++ struct iw_point *erq = &(wrqu->encoding);
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
++ DBG_871X("+rtw_wx_set_enc, flags=0x%x\n", erq->flags);
++
++ _rtw_memset(&wep, 0, sizeof(NDIS_802_11_WEP));
++
++ key = erq->flags & IW_ENCODE_INDEX;
++
++ _func_enter_;
++
++ if (erq->flags & IW_ENCODE_DISABLED)
++ {
++ DBG_871X("EncryptionDisabled\n");
++ padapter->securitypriv.ndisencryptstatus = Ndis802_11EncryptionDisabled;
++ padapter->securitypriv.dot11PrivacyAlgrthm=_NO_PRIVACY_;
++ padapter->securitypriv.dot118021XGrpPrivacy=_NO_PRIVACY_;
++ padapter->securitypriv.dot11AuthAlgrthm= dot11AuthAlgrthm_Open; //open system
++ authmode = Ndis802_11AuthModeOpen;
++ padapter->securitypriv.ndisauthtype=authmode;
++
++ goto exit;
++ }
++
++ if (key) {
++ if (key > WEP_KEYS)
++ return -EINVAL;
++ key--;
++ keyindex_provided = 1;
++ }
++ else
++ {
++ keyindex_provided = 0;
++ key = padapter->securitypriv.dot11PrivacyKeyIndex;
++ DBG_871X("rtw_wx_set_enc, key=%d\n", key);
++ }
++
++ //set authentication mode
++ if(erq->flags & IW_ENCODE_OPEN)
++ {
++ DBG_871X("rtw_wx_set_enc():IW_ENCODE_OPEN\n");
++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;//Ndis802_11EncryptionDisabled;
++
++#ifdef CONFIG_PLATFORM_MT53XX
++ padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Auto;
++#else
++ padapter->securitypriv.dot11AuthAlgrthm= dot11AuthAlgrthm_Open;
++#endif
++
++ padapter->securitypriv.dot11PrivacyAlgrthm=_NO_PRIVACY_;
++ padapter->securitypriv.dot118021XGrpPrivacy=_NO_PRIVACY_;
++ authmode = Ndis802_11AuthModeOpen;
++ padapter->securitypriv.ndisauthtype=authmode;
++ }
++ else if(erq->flags & IW_ENCODE_RESTRICTED)
++ {
++ DBG_871X("rtw_wx_set_enc():IW_ENCODE_RESTRICTED\n");
++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;
++
++#ifdef CONFIG_PLATFORM_MT53XX
++ padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Auto;
++#else
++ padapter->securitypriv.dot11AuthAlgrthm= dot11AuthAlgrthm_Shared;
++#endif
++
++ padapter->securitypriv.dot11PrivacyAlgrthm=_WEP40_;
++ padapter->securitypriv.dot118021XGrpPrivacy=_WEP40_;
++ authmode = Ndis802_11AuthModeShared;
++ padapter->securitypriv.ndisauthtype=authmode;
++ }
++ else
++ {
++ DBG_871X("rtw_wx_set_enc():erq->flags=0x%x\n", erq->flags);
++
++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;//Ndis802_11EncryptionDisabled;
++ padapter->securitypriv.dot11AuthAlgrthm= dot11AuthAlgrthm_Open; //open system
++ padapter->securitypriv.dot11PrivacyAlgrthm=_NO_PRIVACY_;
++ padapter->securitypriv.dot118021XGrpPrivacy=_NO_PRIVACY_;
++ authmode = Ndis802_11AuthModeOpen;
++ padapter->securitypriv.ndisauthtype=authmode;
++ }
++
++ wep.KeyIndex = key;
++ if (erq->length > 0)
++ {
++ wep.KeyLength = erq->length <= 5 ? 5 : 13;
++
++ wep.Length = wep.KeyLength + FIELD_OFFSET(NDIS_802_11_WEP, KeyMaterial);
++ }
++ else
++ {
++ wep.KeyLength = 0 ;
++
++ if(keyindex_provided == 1)// set key_id only, no given KeyMaterial(erq->length==0).
++ {
++ padapter->securitypriv.dot11PrivacyKeyIndex = key;
++
++ DBG_871X("(keyindex_provided == 1), keyid=%d, key_len=%d\n", key, padapter->securitypriv.dot11DefKeylen[key]);
++
++ switch(padapter->securitypriv.dot11DefKeylen[key])
++ {
++ case 5:
++ padapter->securitypriv.dot11PrivacyAlgrthm=_WEP40_;
++ break;
++ case 13:
++ padapter->securitypriv.dot11PrivacyAlgrthm=_WEP104_;
++ break;
++ default:
++ padapter->securitypriv.dot11PrivacyAlgrthm=_NO_PRIVACY_;
++ break;
++ }
++
++ goto exit;
++
++ }
++
++ }
++
++ wep.KeyIndex |= 0x80000000;
++
++ _rtw_memcpy(wep.KeyMaterial, keybuf, wep.KeyLength);
++
++ if (rtw_set_802_11_add_wep(padapter, &wep) == _FALSE) {
++ if(rf_on == pwrpriv->rf_pwrstate )
++ ret = -EOPNOTSUPP;
++ goto exit;
++ }
++
++exit:
++
++ _func_exit_;
++
++ return ret;
++
++}
++
++static int rtw_wx_get_enc(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *keybuf)
++{
++ uint key, ret =0;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct iw_point *erq = &(wrqu->encoding);
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++
++ _func_enter_;
++
++ if(check_fwstate(pmlmepriv, _FW_LINKED) != _TRUE)
++ {
++ if(check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) != _TRUE)
++ {
++ erq->length = 0;
++ erq->flags |= IW_ENCODE_DISABLED;
++ return 0;
++ }
++ }
++
++
++ key = erq->flags & IW_ENCODE_INDEX;
++
++ if (key) {
++ if (key > WEP_KEYS)
++ return -EINVAL;
++ key--;
++ } else
++ {
++ key = padapter->securitypriv.dot11PrivacyKeyIndex;
++ }
++
++ erq->flags = key + 1;
++
++ //if(padapter->securitypriv.ndisauthtype == Ndis802_11AuthModeOpen)
++ //{
++ // erq->flags |= IW_ENCODE_OPEN;
++ //}
++
++ switch(padapter->securitypriv.ndisencryptstatus)
++ {
++ case Ndis802_11EncryptionNotSupported:
++ case Ndis802_11EncryptionDisabled:
++
++ erq->length = 0;
++ erq->flags |= IW_ENCODE_DISABLED;
++
++ break;
++
++ case Ndis802_11Encryption1Enabled:
++
++ erq->length = padapter->securitypriv.dot11DefKeylen[key];
++
++ if(erq->length)
++ {
++ _rtw_memcpy(keybuf, padapter->securitypriv.dot11DefKey[key].skey, padapter->securitypriv.dot11DefKeylen[key]);
++
++ erq->flags |= IW_ENCODE_ENABLED;
++
++ if(padapter->securitypriv.ndisauthtype == Ndis802_11AuthModeOpen)
++ {
++ erq->flags |= IW_ENCODE_OPEN;
++ }
++ else if(padapter->securitypriv.ndisauthtype == Ndis802_11AuthModeShared)
++ {
++ erq->flags |= IW_ENCODE_RESTRICTED;
++ }
++ }
++ else
++ {
++ erq->length = 0;
++ erq->flags |= IW_ENCODE_DISABLED;
++ }
++
++ break;
++
++ case Ndis802_11Encryption2Enabled:
++ case Ndis802_11Encryption3Enabled:
++
++ erq->length = 16;
++ erq->flags |= (IW_ENCODE_ENABLED | IW_ENCODE_OPEN | IW_ENCODE_NOKEY);
++
++ break;
++
++ default:
++ erq->length = 0;
++ erq->flags |= IW_ENCODE_DISABLED;
++
++ break;
++
++ }
++
++ _func_exit_;
++
++ return ret;
++
++}
++
++static int rtw_wx_get_power(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++ //_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++
++ wrqu->power.value = 0;
++ wrqu->power.fixed = 0; /* no auto select */
++ wrqu->power.disabled = 1;
++
++ return 0;
++
++}
++
++static int rtw_wx_set_gen_ie(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++ int ret;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++
++ ret = rtw_set_wpa_ie(padapter, extra, wrqu->data.length);
++
++ return ret;
++}
++
++static int rtw_wx_set_auth(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct iw_param *param = (struct iw_param*)&(wrqu->param);
++ int ret = 0;
++
++ switch (param->flags & IW_AUTH_INDEX) {
++ case IW_AUTH_WPA_VERSION:
++ break;
++ case IW_AUTH_CIPHER_PAIRWISE:
++
++ break;
++ case IW_AUTH_CIPHER_GROUP:
++
++ break;
++ case IW_AUTH_KEY_MGMT:
++ /*
++ * ??? does not use these parameters
++ */
++ break;
++
++ case IW_AUTH_TKIP_COUNTERMEASURES:
++ {
++ if ( param->value )
++ { // wpa_supplicant is enabling the tkip countermeasure.
++ padapter->securitypriv.btkip_countermeasure = _TRUE;
++ }
++ else
++ { // wpa_supplicant is disabling the tkip countermeasure.
++ padapter->securitypriv.btkip_countermeasure = _FALSE;
++ }
++ break;
++ }
++ case IW_AUTH_DROP_UNENCRYPTED:
++ {
++ /* HACK:
++ *
++ * wpa_supplicant calls set_wpa_enabled when the driver
++ * is loaded and unloaded, regardless of if WPA is being
++ * used. No other calls are made which can be used to
++ * determine if encryption will be used or not prior to
++ * association being expected. If encryption is not being
++ * used, drop_unencrypted is set to false, else true -- we
++ * can use this to determine if the CAP_PRIVACY_ON bit should
++ * be set.
++ */
++
++ if(padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption1Enabled)
++ {
++ break;//it means init value, or using wep, ndisencryptstatus = Ndis802_11Encryption1Enabled,
++ // then it needn't reset it;
++ }
++
++ if(param->value){
++ padapter->securitypriv.ndisencryptstatus = Ndis802_11EncryptionDisabled;
++ padapter->securitypriv.dot11PrivacyAlgrthm=_NO_PRIVACY_;
++ padapter->securitypriv.dot118021XGrpPrivacy=_NO_PRIVACY_;
++ padapter->securitypriv.dot11AuthAlgrthm= dot11AuthAlgrthm_Open; //open system
++ padapter->securitypriv.ndisauthtype=Ndis802_11AuthModeOpen;
++ }
++
++ break;
++ }
++
++ case IW_AUTH_80211_AUTH_ALG:
++
++ #if defined(CONFIG_ANDROID) || 1
++ /*
++ * It's the starting point of a link layer connection using wpa_supplicant
++ */
++ if(check_fwstate(&padapter->mlmepriv, _FW_LINKED)) {
++ LeaveAllPowerSaveMode(padapter);
++ rtw_disassoc_cmd(padapter, 500, _FALSE);
++ DBG_871X("%s...call rtw_indicate_disconnect\n ",__FUNCTION__);
++ rtw_indicate_disconnect(padapter);
++ rtw_free_assoc_resources(padapter, 1);
++ }
++ #endif
++
++
++ ret = wpa_set_auth_algs(dev, (u32)param->value);
++
++ break;
++
++ case IW_AUTH_WPA_ENABLED:
++
++ //if(param->value)
++ // padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_8021X; //802.1x
++ //else
++ // padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Open;//open system
++
++ //_disassociate(priv);
++
++ break;
++
++ case IW_AUTH_RX_UNENCRYPTED_EAPOL:
++ //ieee->ieee802_1x = param->value;
++ break;
++
++ case IW_AUTH_PRIVACY_INVOKED:
++ //ieee->privacy_invoked = param->value;
++ break;
++
++ default:
++ return -EOPNOTSUPP;
++
++ }
++
++ return ret;
++
++}
++
++static int rtw_wx_set_enc_ext(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++ char *alg_name;
++ u32 param_len;
++ struct ieee_param *param = NULL;
++ struct iw_point *pencoding = &wrqu->encoding;
++ struct iw_encode_ext *pext = (struct iw_encode_ext *)extra;
++ int ret=0;
++
++ param_len = sizeof(struct ieee_param) + pext->key_len;
++ param = (struct ieee_param *)rtw_malloc(param_len);
++ if (param == NULL)
++ return -1;
++
++ _rtw_memset(param, 0, param_len);
++
++ param->cmd = IEEE_CMD_SET_ENCRYPTION;
++ _rtw_memset(param->sta_addr, 0xff, ETH_ALEN);
++
++
++ switch (pext->alg) {
++ case IW_ENCODE_ALG_NONE:
++ //todo: remove key
++ //remove = 1;
++ alg_name = "none";
++ break;
++ case IW_ENCODE_ALG_WEP:
++ alg_name = "WEP";
++ break;
++ case IW_ENCODE_ALG_TKIP:
++ alg_name = "TKIP";
++ break;
++ case IW_ENCODE_ALG_CCMP:
++ alg_name = "CCMP";
++ break;
++#ifdef CONFIG_IEEE80211W
++ case IW_ENCODE_ALG_AES_CMAC:
++ alg_name = "BIP";
++ break;
++#endif //CONFIG_IEEE80211W
++ default:
++ return -1;
++ }
++
++ strncpy((char *)param->u.crypt.alg, alg_name, IEEE_CRYPT_ALG_NAME_LEN);
++
++
++ if((pext->ext_flags & IW_ENCODE_EXT_GROUP_KEY)//?
++#ifdef CONFIG_IEEE80211W
++ || (pext->ext_flags & IW_ENCODE_ALG_AES_CMAC)
++#endif //CONFIG_IEEE80211W
++ )
++ {
++ param->u.crypt.set_tx = 0;
++ }
++
++ if (pext->ext_flags & IW_ENCODE_EXT_SET_TX_KEY)//?
++ {
++ param->u.crypt.set_tx = 1;
++ }
++
++ param->u.crypt.idx = (pencoding->flags&0x00FF) -1 ;
++
++ if (pext->ext_flags & IW_ENCODE_EXT_RX_SEQ_VALID)
++ {
++ _rtw_memcpy(param->u.crypt.seq, pext->rx_seq, 8);
++ }
++
++ if(pext->key_len)
++ {
++ param->u.crypt.key_len = pext->key_len;
++ //_rtw_memcpy(param + 1, pext + 1, pext->key_len);
++ _rtw_memcpy(param->u.crypt.key, pext + 1, pext->key_len);
++ }
++
++
++ if (pencoding->flags & IW_ENCODE_DISABLED)
++ {
++ //todo: remove key
++ //remove = 1;
++ }
++
++ ret = wpa_set_encryption(dev, param, param_len);
++
++
++ if(param)
++ {
++ rtw_mfree((u8*)param, param_len);
++ }
++
++
++ return ret;
++
++}
++
++
++static int rtw_wx_get_nick(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++ //_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ //struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ //struct security_priv *psecuritypriv = &padapter->securitypriv;
++
++ if(extra)
++ {
++ wrqu->data.length = 14;
++ wrqu->data.flags = 1;
++ _rtw_memcpy(extra, "<WIFI@REALTEK>", 14);
++ }
++
++ //rtw_signal_process(pid, SIGUSR1); //for test
++
++ //dump debug info here
++/*
++ u32 dot11AuthAlgrthm; // 802.11 auth, could be open, shared, and 8021x
++ u32 dot11PrivacyAlgrthm; // This specify the privacy for shared auth. algorithm.
++ u32 dot118021XGrpPrivacy; // This specify the privacy algthm. used for Grp key
++ u32 ndisauthtype;
++ u32 ndisencryptstatus;
++*/
++
++ //DBG_871X("auth_alg=0x%x, enc_alg=0x%x, auth_type=0x%x, enc_type=0x%x\n",
++ // psecuritypriv->dot11AuthAlgrthm, psecuritypriv->dot11PrivacyAlgrthm,
++ // psecuritypriv->ndisauthtype, psecuritypriv->ndisencryptstatus);
++
++ //DBG_871X("enc_alg=0x%x\n", psecuritypriv->dot11PrivacyAlgrthm);
++ //DBG_871X("auth_type=0x%x\n", psecuritypriv->ndisauthtype);
++ //DBG_871X("enc_type=0x%x\n", psecuritypriv->ndisencryptstatus);
++
++#if 0
++ DBG_871X("dbg(0x210)=0x%x\n", rtw_read32(padapter, 0x210));
++ DBG_871X("dbg(0x608)=0x%x\n", rtw_read32(padapter, 0x608));
++ DBG_871X("dbg(0x280)=0x%x\n", rtw_read32(padapter, 0x280));
++ DBG_871X("dbg(0x284)=0x%x\n", rtw_read32(padapter, 0x284));
++ DBG_871X("dbg(0x288)=0x%x\n", rtw_read32(padapter, 0x288));
++
++ DBG_871X("dbg(0x664)=0x%x\n", rtw_read32(padapter, 0x664));
++
++
++ DBG_871X("\n");
++
++ DBG_871X("dbg(0x430)=0x%x\n", rtw_read32(padapter, 0x430));
++ DBG_871X("dbg(0x438)=0x%x\n", rtw_read32(padapter, 0x438));
++
++ DBG_871X("dbg(0x440)=0x%x\n", rtw_read32(padapter, 0x440));
++
++ DBG_871X("dbg(0x458)=0x%x\n", rtw_read32(padapter, 0x458));
++
++ DBG_871X("dbg(0x484)=0x%x\n", rtw_read32(padapter, 0x484));
++ DBG_871X("dbg(0x488)=0x%x\n", rtw_read32(padapter, 0x488));
++
++ DBG_871X("dbg(0x444)=0x%x\n", rtw_read32(padapter, 0x444));
++ DBG_871X("dbg(0x448)=0x%x\n", rtw_read32(padapter, 0x448));
++ DBG_871X("dbg(0x44c)=0x%x\n", rtw_read32(padapter, 0x44c));
++ DBG_871X("dbg(0x450)=0x%x\n", rtw_read32(padapter, 0x450));
++#endif
++
++ return 0;
++
++}
++
++static int rtw_wx_read32(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++ PADAPTER padapter;
++ struct iw_point *p;
++ u16 len;
++ u32 addr;
++ u32 data32;
++ u32 bytes;
++ u8 *ptmp;
++
++
++ padapter = (PADAPTER)rtw_netdev_priv(dev);
++ p = &wrqu->data;
++ len = p->length;
++ ptmp = (u8*)rtw_malloc(len);
++ if (NULL == ptmp)
++ return -ENOMEM;
++
++ if (copy_from_user(ptmp, p->pointer, len)) {
++ rtw_mfree(ptmp, len);
++ return -EFAULT;
++ }
++
++ bytes = 0;
++ addr = 0;
++ sscanf(ptmp, "%d,%x", &bytes, &addr);
++
++ switch (bytes) {
++ case 1:
++ data32 = rtw_read8(padapter, addr);
++ sprintf(extra, "0x%02X", data32);
++ break;
++ case 2:
++ data32 = rtw_read16(padapter, addr);
++ sprintf(extra, "0x%04X", data32);
++ break;
++ case 4:
++ data32 = rtw_read32(padapter, addr);
++ sprintf(extra, "0x%08X", data32);
++ break;
++ default:
++ printk(KERN_INFO "%s: usage> read [bytes],[address(hex)]\n", __func__);
++ return -EINVAL;
++ }
++ printk(KERN_INFO "%s: addr=0x%08X data=%s\n", __func__, addr, extra);
++
++ rtw_mfree(ptmp, len);
++
++ return 0;
++}
++
++static int rtw_wx_write32(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++ PADAPTER padapter = (PADAPTER)rtw_netdev_priv(dev);
++
++ u32 addr;
++ u32 data32;
++ u32 bytes;
++
++
++ bytes = 0;
++ addr = 0;
++ data32 = 0;
++ sscanf(extra, "%d,%x,%x", &bytes, &addr, &data32);
++
++ switch (bytes) {
++ case 1:
++ rtw_write8(padapter, addr, (u8)data32);
++ printk(KERN_INFO "%s: addr=0x%08X data=0x%02X\n", __func__, addr, (u8)data32);
++ break;
++ case 2:
++ rtw_write16(padapter, addr, (u16)data32);
++ printk(KERN_INFO "%s: addr=0x%08X data=0x%04X\n", __func__, addr, (u16)data32);
++ break;
++ case 4:
++ rtw_write32(padapter, addr, data32);
++ printk(KERN_INFO "%s: addr=0x%08X data=0x%08X\n", __func__, addr, data32);
++ break;
++ default:
++ printk(KERN_INFO "%s: usage> write [bytes],[address(hex)],[data(hex)]\n", __func__);
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++static int rtw_wx_read_rf(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ u32 path, addr, data32;
++
++
++ path = *(u32*)extra;
++ addr = *((u32*)extra + 1);
++ data32 = rtw_hal_read_rfreg(padapter, path, addr, 0xFFFFF);
++// DBG_871X("%s: path=%d addr=0x%02x data=0x%05x\n", __func__, path, addr, data32);
++ /*
++ * IMPORTANT!!
++ * Only when wireless private ioctl is at odd order,
++ * "extra" would be copied to user space.
++ */
++ sprintf(extra, "0x%05x", data32);
++
++ return 0;
++}
++
++static int rtw_wx_write_rf(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ u32 path, addr, data32;
++
++
++ path = *(u32*)extra;
++ addr = *((u32*)extra + 1);
++ data32 = *((u32*)extra + 2);
++// DBG_871X("%s: path=%d addr=0x%02x data=0x%05x\n", __func__, path, addr, data32);
++ rtw_hal_write_rfreg(padapter, path, addr, 0xFFFFF, data32);
++
++ return 0;
++}
++
++static int rtw_wx_priv_null(struct net_device *dev, struct iw_request_info *a,
++ union iwreq_data *wrqu, char *b)
++{
++ return -1;
++}
++
++static int dummy(struct net_device *dev, struct iw_request_info *a,
++ union iwreq_data *wrqu, char *b)
++{
++ //_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ //struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++
++ //DBG_871X("cmd_code=%x, fwstate=0x%x\n", a->cmd, get_fwstate(pmlmepriv));
++
++ return -1;
++
++}
++
++static int rtw_wx_set_channel_plan(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct registry_priv *pregistrypriv = &padapter->registrypriv;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ extern int rtw_channel_plan;
++ u8 channel_plan_req = (u8) (*((int *)wrqu));
++
++ #if 0
++ rtw_channel_plan = (int)wrqu->data.pointer;
++ pregistrypriv->channel_plan = rtw_channel_plan;
++ pmlmepriv->ChannelPlan = pregistrypriv->channel_plan;
++ #endif
++
++ if( _SUCCESS == rtw_set_chplan_cmd(padapter, channel_plan_req, 1) ) {
++ DBG_871X("%s set channel_plan = 0x%02X\n", __func__, pmlmepriv->ChannelPlan);
++ } else
++ return -EPERM;
++
++ return 0;
++}
++
++static int rtw_wx_set_mtk_wps_probe_ie(struct net_device *dev,
++ struct iw_request_info *a,
++ union iwreq_data *wrqu, char *b)
++{
++#ifdef CONFIG_PLATFORM_MT53XX
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++
++ RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_notice_,
++ ("WLAN IOCTL: cmd_code=%x, fwstate=0x%x\n",
++ a->cmd, get_fwstate(pmlmepriv)));
++#endif
++ return 0;
++}
++
++static int rtw_wx_get_sensitivity(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *buf)
++{
++#ifdef CONFIG_PLATFORM_MT53XX
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++
++ // Modified by Albert 20110914
++ // This is in dbm format for MTK platform.
++ wrqu->qual.level = padapter->recvpriv.rssi;
++ DBG_871X(" level = %u\n", wrqu->qual.level );
++#endif
++ return 0;
++}
++
++static int rtw_wx_set_mtk_wps_ie(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++#ifdef CONFIG_PLATFORM_MT53XX
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++
++ return rtw_set_wpa_ie(padapter, wrqu->data.pointer, wrqu->data.length);
++#else
++ return 0;
++#endif
++}
++
++/*
++typedef int (*iw_handler)(struct net_device *dev, struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra);
++*/
++/*
++ * For all data larger than 16 octets, we need to use a
++ * pointer to memory allocated in user space.
++ */
++static int rtw_drvext_hdl(struct net_device *dev, struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++
++ #if 0
++struct iw_point
++{
++ void __user *pointer; /* Pointer to the data (in user space) */
++ __u16 length; /* number of fields or size in bytes */
++ __u16 flags; /* Optional params */
++};
++ #endif
++
++#ifdef CONFIG_DRVEXT_MODULE
++ u8 res;
++ struct drvext_handler *phandler;
++ struct drvext_oidparam *poidparam;
++ int ret;
++ u16 len;
++ u8 *pparmbuf, bset;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct iw_point *p = &wrqu->data;
++
++ if( (!p->length) || (!p->pointer)){
++ ret = -EINVAL;
++ goto _rtw_drvext_hdl_exit;
++ }
++
++
++ bset = (u8)(p->flags&0xFFFF);
++ len = p->length;
++ pparmbuf = (u8*)rtw_malloc(len);
++ if (pparmbuf == NULL){
++ ret = -ENOMEM;
++ goto _rtw_drvext_hdl_exit;
++ }
++
++ if(bset)//set info
++ {
++ if (copy_from_user(pparmbuf, p->pointer,len)) {
++ rtw_mfree(pparmbuf, len);
++ ret = -EFAULT;
++ goto _rtw_drvext_hdl_exit;
++ }
++ }
++ else//query info
++ {
++
++ }
++
++
++ //
++ poidparam = (struct drvext_oidparam *)pparmbuf;
++
++ RT_TRACE(_module_rtl871x_ioctl_os_c,_drv_info_,("drvext set oid subcode [%d], len[%d], InformationBufferLength[%d]\r\n",
++ poidparam->subcode, poidparam->len, len));
++
++
++ //check subcode
++ if ( poidparam->subcode >= MAX_DRVEXT_HANDLERS)
++ {
++ RT_TRACE(_module_rtl871x_ioctl_os_c,_drv_err_,("no matching drvext handlers\r\n"));
++ ret = -EINVAL;
++ goto _rtw_drvext_hdl_exit;
++ }
++
++
++ if ( poidparam->subcode >= MAX_DRVEXT_OID_SUBCODES)
++ {
++ RT_TRACE(_module_rtl871x_ioctl_os_c,_drv_err_,("no matching drvext subcodes\r\n"));
++ ret = -EINVAL;
++ goto _rtw_drvext_hdl_exit;
++ }
++
++
++ phandler = drvextoidhandlers + poidparam->subcode;
++
++ if (poidparam->len != phandler->parmsize)
++ {
++ RT_TRACE(_module_rtl871x_ioctl_os_c,_drv_err_,("no matching drvext param size %d vs %d\r\n",
++ poidparam->len , phandler->parmsize));
++ ret = -EINVAL;
++ goto _rtw_drvext_hdl_exit;
++ }
++
++
++ res = phandler->handler(&padapter->drvextpriv, bset, poidparam->data);
++
++ if(res==0)
++ {
++ ret = 0;
++
++ if (bset == 0x00) {//query info
++ //_rtw_memcpy(p->pointer, pparmbuf, len);
++ if (copy_to_user(p->pointer, pparmbuf, len))
++ ret = -EFAULT;
++ }
++ }
++ else
++ ret = -EFAULT;
++
++
++_rtw_drvext_hdl_exit:
++
++ return ret;
++
++#endif
++
++ return 0;
++
++}
++
++static void rtw_dbg_mode_hdl(_adapter *padapter, u32 id, u8 *pdata, u32 len)
++{
++ pRW_Reg RegRWStruct;
++ struct rf_reg_param *prfreg;
++ u8 path;
++ u8 offset;
++ u32 value;
++
++ DBG_871X("%s\n", __FUNCTION__);
++
++ switch(id)
++ {
++ case GEN_MP_IOCTL_SUBCODE(MP_START):
++ DBG_871X("871x_driver is only for normal mode, can't enter mp mode\n");
++ break;
++ case GEN_MP_IOCTL_SUBCODE(READ_REG):
++ RegRWStruct = (pRW_Reg)pdata;
++ switch (RegRWStruct->width)
++ {
++ case 1:
++ RegRWStruct->value = rtw_read8(padapter, RegRWStruct->offset);
++ break;
++ case 2:
++ RegRWStruct->value = rtw_read16(padapter, RegRWStruct->offset);
++ break;
++ case 4:
++ RegRWStruct->value = rtw_read32(padapter, RegRWStruct->offset);
++ break;
++ default:
++ break;
++ }
++
++ break;
++ case GEN_MP_IOCTL_SUBCODE(WRITE_REG):
++ RegRWStruct = (pRW_Reg)pdata;
++ switch (RegRWStruct->width)
++ {
++ case 1:
++ rtw_write8(padapter, RegRWStruct->offset, (u8)RegRWStruct->value);
++ break;
++ case 2:
++ rtw_write16(padapter, RegRWStruct->offset, (u16)RegRWStruct->value);
++ break;
++ case 4:
++ rtw_write32(padapter, RegRWStruct->offset, (u32)RegRWStruct->value);
++ break;
++ default:
++ break;
++ }
++
++ break;
++ case GEN_MP_IOCTL_SUBCODE(READ_RF_REG):
++
++ prfreg = (struct rf_reg_param *)pdata;
++
++ path = (u8)prfreg->path;
++ offset = (u8)prfreg->offset;
++
++ value = rtw_hal_read_rfreg(padapter, path, offset, 0xffffffff);
++
++ prfreg->value = value;
++
++ break;
++ case GEN_MP_IOCTL_SUBCODE(WRITE_RF_REG):
++
++ prfreg = (struct rf_reg_param *)pdata;
++
++ path = (u8)prfreg->path;
++ offset = (u8)prfreg->offset;
++ value = prfreg->value;
++
++ rtw_hal_write_rfreg(padapter, path, offset, 0xffffffff, value);
++
++ break;
++ case GEN_MP_IOCTL_SUBCODE(TRIGGER_GPIO):
++ DBG_871X("==> trigger gpio 0\n");
++ rtw_hal_set_hwreg(padapter, HW_VAR_TRIGGER_GPIO_0, 0);
++ break;
++#ifdef CONFIG_BT_COEXIST
++ case GEN_MP_IOCTL_SUBCODE(SET_DM_BT):
++ DBG_871X("==> set dm_bt_coexist:%x\n",*(u8 *)pdata);
++ rtw_hal_set_hwreg(padapter, HW_VAR_BT_SET_COEXIST, pdata);
++ break;
++ case GEN_MP_IOCTL_SUBCODE(DEL_BA):
++ DBG_871X("==> delete ba:%x\n",*(u8 *)pdata);
++ rtw_hal_set_hwreg(padapter, HW_VAR_BT_ISSUE_DELBA, pdata);
++ break;
++#endif
++#ifdef DBG_CONFIG_ERROR_DETECT
++ case GEN_MP_IOCTL_SUBCODE(GET_WIFI_STATUS):
++ *pdata = rtw_hal_sreset_get_wifi_status(padapter);
++ break;
++#endif
++
++ default:
++ break;
++ }
++
++}
++
++static int rtw_mp_ioctl_hdl(struct net_device *dev, struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++ int ret = 0;
++ u32 BytesRead, BytesWritten, BytesNeeded;
++ struct oid_par_priv oid_par;
++ struct mp_ioctl_handler *phandler;
++ struct mp_ioctl_param *poidparam;
++ uint status=0;
++ u16 len;
++ u8 *pparmbuf = NULL, bset;
++ PADAPTER padapter = (PADAPTER)rtw_netdev_priv(dev);
++ struct iw_point *p = &wrqu->data;
++
++ //DBG_871X("+rtw_mp_ioctl_hdl\n");
++
++ //mutex_lock(&ioctl_mutex);
++
++ if ((!p->length) || (!p->pointer)) {
++ ret = -EINVAL;
++ goto _rtw_mp_ioctl_hdl_exit;
++ }
++
++ pparmbuf = NULL;
++ bset = (u8)(p->flags & 0xFFFF);
++ len = p->length;
++ pparmbuf = (u8*)rtw_malloc(len);
++ if (pparmbuf == NULL){
++ ret = -ENOMEM;
++ goto _rtw_mp_ioctl_hdl_exit;
++ }
++
++ if (copy_from_user(pparmbuf, p->pointer, len)) {
++ ret = -EFAULT;
++ goto _rtw_mp_ioctl_hdl_exit;
++ }
++
++ poidparam = (struct mp_ioctl_param *)pparmbuf;
++ RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_info_,
++ ("rtw_mp_ioctl_hdl: subcode [%d], len[%d], buffer_len[%d]\r\n",
++ poidparam->subcode, poidparam->len, len));
++
++ if (poidparam->subcode >= MAX_MP_IOCTL_SUBCODE) {
++ RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_err_, ("no matching drvext subcodes\r\n"));
++ ret = -EINVAL;
++ goto _rtw_mp_ioctl_hdl_exit;
++ }
++
++ //DBG_871X("%s: %d\n", __func__, poidparam->subcode);
++
++#ifdef CONFIG_MP_INCLUDED
++ phandler = mp_ioctl_hdl + poidparam->subcode;
++
++ if ((phandler->paramsize != 0) && (poidparam->len < phandler->paramsize))
++ {
++ RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_err_,
++ ("no matching drvext param size %d vs %d\r\n",
++ poidparam->len, phandler->paramsize));
++ ret = -EINVAL;
++ goto _rtw_mp_ioctl_hdl_exit;
++ }
++
++ if (phandler->handler)
++ {
++ oid_par.adapter_context = padapter;
++ oid_par.oid = phandler->oid;
++ oid_par.information_buf = poidparam->data;
++ oid_par.information_buf_len = poidparam->len;
++ oid_par.dbg = 0;
++
++ BytesWritten = 0;
++ BytesNeeded = 0;
++
++ if (bset) {
++ oid_par.bytes_rw = &BytesRead;
++ oid_par.bytes_needed = &BytesNeeded;
++ oid_par.type_of_oid = SET_OID;
++ } else {
++ oid_par.bytes_rw = &BytesWritten;
++ oid_par.bytes_needed = &BytesNeeded;
++ oid_par.type_of_oid = QUERY_OID;
++ }
++
++ status = phandler->handler(&oid_par);
++
++ //todo:check status, BytesNeeded, etc.
++ }
++ else {
++ DBG_871X("rtw_mp_ioctl_hdl(): err!, subcode=%d, oid=%d, handler=%p\n",
++ poidparam->subcode, phandler->oid, phandler->handler);
++ ret = -EFAULT;
++ goto _rtw_mp_ioctl_hdl_exit;
++ }
++#else
++
++ rtw_dbg_mode_hdl(padapter, poidparam->subcode, poidparam->data, poidparam->len);
++
++#endif
++
++ if (bset == 0x00) {//query info
++ if (copy_to_user(p->pointer, pparmbuf, len))
++ ret = -EFAULT;
++ }
++
++ if (status) {
++ ret = -EFAULT;
++ goto _rtw_mp_ioctl_hdl_exit;
++ }
++
++_rtw_mp_ioctl_hdl_exit:
++
++ if (pparmbuf)
++ rtw_mfree(pparmbuf, len);
++
++ //mutex_unlock(&ioctl_mutex);
++
++ return ret;
++}
++
++static int rtw_get_ap_info(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++ int bssid_match, ret = 0;
++ u32 cnt=0, wpa_ielen;
++ _irqL irqL;
++ _list *plist, *phead;
++ unsigned char *pbuf;
++ u8 bssid[ETH_ALEN];
++ char data[32];
++ struct wlan_network *pnetwork = NULL;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ _queue *queue = &(pmlmepriv->scanned_queue);
++ struct iw_point *pdata = &wrqu->data;
++
++ DBG_871X("+rtw_get_aplist_info\n");
++
++ if((padapter->bDriverStopped) || (pdata==NULL))
++ {
++ ret= -EINVAL;
++ goto exit;
++ }
++
++ while((check_fwstate(pmlmepriv, (_FW_UNDER_SURVEY|_FW_UNDER_LINKING))) == _TRUE)
++ {
++ rtw_msleep_os(30);
++ cnt++;
++ if(cnt > 100)
++ break;
++ }
++
++
++ //pdata->length = 0;//?
++ pdata->flags = 0;
++ if(pdata->length>=32)
++ {
++ if(copy_from_user(data, pdata->pointer, 32))
++ {
++ ret= -EINVAL;
++ goto exit;
++ }
++ }
++ else
++ {
++ ret= -EINVAL;
++ goto exit;
++ }
++
++ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++
++ phead = get_list_head(queue);
++ plist = get_next(phead);
++
++ while(1)
++ {
++ if (rtw_end_of_queue_search(phead,plist)== _TRUE)
++ break;
++
++
++ pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
++
++ //if(hwaddr_aton_i(pdata->pointer, bssid))
++ if(hwaddr_aton_i(data, bssid))
++ {
++ DBG_871X("Invalid BSSID '%s'.\n", (u8*)data);
++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++ return -EINVAL;
++ }
++
++
++ if(_rtw_memcmp(bssid, pnetwork->network.MacAddress, ETH_ALEN) == _TRUE)//BSSID match, then check if supporting wpa/wpa2
++ {
++ DBG_871X("BSSID:" MAC_FMT "\n", MAC_ARG(bssid));
++
++ pbuf = rtw_get_wpa_ie(&pnetwork->network.IEs[12], &wpa_ielen, pnetwork->network.IELength-12);
++ if(pbuf && (wpa_ielen>0))
++ {
++ pdata->flags = 1;
++ break;
++ }
++
++ pbuf = rtw_get_wpa2_ie(&pnetwork->network.IEs[12], &wpa_ielen, pnetwork->network.IELength-12);
++ if(pbuf && (wpa_ielen>0))
++ {
++ pdata->flags = 2;
++ break;
++ }
++
++ }
++
++ plist = get_next(plist);
++
++ }
++
++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++
++ if(pdata->length>=34)
++ {
++ if(copy_to_user((u8*)pdata->pointer+32, (u8*)&pdata->flags, 1))
++ {
++ ret= -EINVAL;
++ goto exit;
++ }
++ }
++
++exit:
++
++ return ret;
++
++}
++
++static int rtw_set_pid(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++
++ int ret = 0;
++ _adapter *padapter = rtw_netdev_priv(dev);
++ int *pdata = (int *)wrqu;
++ int selector;
++
++ if((padapter->bDriverStopped) || (pdata==NULL))
++ {
++ ret= -EINVAL;
++ goto exit;
++ }
++
++ selector = *pdata;
++ if(selector < 3 && selector >=0) {
++ padapter->pid[selector] = *(pdata+1);
++ #ifdef CONFIG_GLOBAL_UI_PID
++ ui_pid[selector] = *(pdata+1);
++ #endif
++ DBG_871X("%s set pid[%d]=%d\n", __FUNCTION__, selector ,padapter->pid[selector]);
++ }
++ else
++ DBG_871X("%s selector %d error\n", __FUNCTION__, selector);
++
++exit:
++
++ return ret;
++
++}
++
++static int rtw_wps_start(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++
++ int ret = 0;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct iw_point *pdata = &wrqu->data;
++ u32 u32wps_start = 0;
++ unsigned int uintRet = 0;
++
++ uintRet = copy_from_user( ( void* ) &u32wps_start, pdata->pointer, 4 );
++
++ if((padapter->bDriverStopped) || (pdata==NULL))
++ {
++ ret= -EINVAL;
++ goto exit;
++ }
++
++ if ( u32wps_start == 0 )
++ {
++ u32wps_start = *extra;
++ }
++
++ DBG_871X( "[%s] wps_start = %d\n", __FUNCTION__, u32wps_start );
++
++ if ( u32wps_start == 1 ) // WPS Start
++ {
++ rtw_led_control(padapter, LED_CTL_START_WPS);
++ }
++ else if ( u32wps_start == 2 ) // WPS Stop because of wps success
++ {
++ rtw_led_control(padapter, LED_CTL_STOP_WPS);
++ }
++ else if ( u32wps_start == 3 ) // WPS Stop because of wps fail
++ {
++ rtw_led_control(padapter, LED_CTL_STOP_WPS_FAIL);
++ }
++
++#ifdef CONFIG_INTEL_WIDI
++ process_intel_widi_wps_status(padapter, u32wps_start);
++#endif //CONFIG_INTEL_WIDI
++
++exit:
++
++ return ret;
++
++}
++
++#ifdef CONFIG_P2P
++static int rtw_wext_p2p_enable(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++
++ int ret = 0;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ struct iw_point *pdata = &wrqu->data;
++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo);
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
++ enum P2P_ROLE init_role = P2P_ROLE_DISABLE;
++
++ if(*extra == '0' )
++ init_role = P2P_ROLE_DISABLE;
++ else if(*extra == '1')
++ init_role = P2P_ROLE_DEVICE;
++ else if(*extra == '2')
++ init_role = P2P_ROLE_CLIENT;
++ else if(*extra == '3')
++ init_role = P2P_ROLE_GO;
++
++ if(_FAIL == rtw_p2p_enable(padapter, init_role))
++ {
++ ret = -EFAULT;
++ goto exit;
++ }
++
++ //set channel/bandwidth
++ if(init_role != P2P_ROLE_DISABLE)
++ {
++ u8 channel, ch_offset;
++ u16 bwmode;
++
++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_LISTEN))
++ {
++ // Stay at the listen state and wait for discovery.
++ channel = pwdinfo->listen_channel;
++ pwdinfo->operating_channel = pwdinfo->listen_channel;
++ ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++ bwmode = HT_CHANNEL_WIDTH_20;
++ }
++#ifdef CONFIG_CONCURRENT_MODE
++ else if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE))
++ {
++ _adapter *pbuddy_adapter = padapter->pbuddy_adapter;
++ //struct wifidirect_info *pbuddy_wdinfo = &pbuddy_adapter->wdinfo;
++ struct mlme_priv *pbuddy_mlmepriv = &pbuddy_adapter->mlmepriv;
++ struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv;
++
++ _set_timer( &pwdinfo->ap_p2p_switch_timer, pwdinfo->ext_listen_interval );
++ if ( check_fwstate( pbuddy_mlmepriv, _FW_LINKED ) )
++ {
++ pwdinfo->operating_channel = pbuddy_mlmeext->cur_channel;
++ // How about the ch_offset and bwmode ??
++ }
++ else
++ {
++ pwdinfo->operating_channel = pwdinfo->listen_channel;
++ }
++
++ channel = pbuddy_mlmeext->cur_channel;
++ ch_offset = pbuddy_mlmeext->cur_ch_offset;
++ bwmode = pbuddy_mlmeext->cur_bwmode;
++ }
++#endif
++ else
++ {
++ pwdinfo->operating_channel = pmlmeext->cur_channel;
++
++ channel = pwdinfo->operating_channel;
++ ch_offset = pmlmeext->cur_ch_offset;
++ bwmode = pmlmeext->cur_bwmode;
++ }
++
++ set_channel_bwmode(padapter, channel, ch_offset, bwmode);
++ }
++
++exit:
++ return ret;
++
++}
++
++static int rtw_p2p_set_go_nego_ssid(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++
++ int ret = 0;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ struct iw_point *pdata = &wrqu->data;
++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo);
++
++ DBG_871X( "[%s] ssid = %s, len = %d\n", __FUNCTION__, extra, (u32)strlen( extra ) );
++ _rtw_memcpy( pwdinfo->nego_ssid, extra, strlen( extra ) );
++ pwdinfo->nego_ssidlen = strlen( extra );
++
++ return ret;
++
++}
++
++
++static int rtw_p2p_set_intent(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++ int ret = 0;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo);
++ u8 intent = pwdinfo->intent;
++
++ extra[ wrqu->data.length ] = 0x00;
++
++ intent = rtw_atoi( extra );
++
++ if ( intent <= 15 )
++ {
++ pwdinfo->intent= intent;
++ }
++ else
++ {
++ ret = -1;
++ }
++
++ DBG_871X( "[%s] intent = %d\n", __FUNCTION__, intent);
++
++ return ret;
++
++}
++
++static int rtw_p2p_set_listen_ch(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++
++ int ret = 0;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo);
++ u8 listen_ch = pwdinfo->listen_channel; // Listen channel number
++
++ extra[ wrqu->data.length ] = 0x00;
++ listen_ch = rtw_atoi( extra );
++
++ if ( ( listen_ch == 1 ) || ( listen_ch == 6 ) || ( listen_ch == 11 ) )
++ {
++ pwdinfo->listen_channel = listen_ch;
++ set_channel_bwmode(padapter, pwdinfo->listen_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HT_CHANNEL_WIDTH_20);
++ }
++ else
++ {
++ ret = -1;
++ }
++
++ DBG_871X( "[%s] listen_ch = %d\n", __FUNCTION__, pwdinfo->listen_channel );
++
++ return ret;
++
++}
++
++static int rtw_p2p_set_op_ch(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++// Commented by Albert 20110524
++// This function is used to set the operating channel if the driver will become the group owner
++
++ int ret = 0;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo);
++ u8 op_ch = pwdinfo->operating_channel; // Operating channel number
++
++ extra[ wrqu->data.length ] = 0x00;
++
++ op_ch = ( u8 ) rtw_atoi( extra );
++ if ( op_ch > 0 )
++ {
++ pwdinfo->operating_channel = op_ch;
++ }
++ else
++ {
++ ret = -1;
++ }
++
++ DBG_871X( "[%s] op_ch = %d\n", __FUNCTION__, pwdinfo->operating_channel );
++
++ return ret;
++
++}
++
++
++static int rtw_p2p_profilefound(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++
++ int ret = 0;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo);
++
++ // Comment by Albert 2010/10/13
++ // Input data format:
++ // Ex: 0
++ // Ex: 1XX:XX:XX:XX:XX:XXYYSSID
++ // 0 => Reflush the profile record list.
++ // 1 => Add the profile list
++ // XX:XX:XX:XX:XX:XX => peer's MAC Address ( ex: 00:E0:4C:00:00:01 )
++ // YY => SSID Length
++ // SSID => SSID for persistence group
++
++ DBG_871X( "[%s] In value = %s, len = %d \n", __FUNCTION__, extra, wrqu->data.length -1);
++
++
++ // The upper application should pass the SSID to driver by using this rtw_p2p_profilefound function.
++ if(!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
++ {
++ if ( extra[ 0 ] == '0' )
++ {
++ // Remove all the profile information of wifidirect_info structure.
++ _rtw_memset( &pwdinfo->profileinfo[ 0 ], 0x00, sizeof( struct profile_info ) * P2P_MAX_PERSISTENT_GROUP_NUM );
++ pwdinfo->profileindex = 0;
++ }
++ else
++ {
++ if ( pwdinfo->profileindex >= P2P_MAX_PERSISTENT_GROUP_NUM )
++ {
++ ret = -1;
++ }
++ else
++ {
++ int jj, kk;
++
++ // Add this profile information into pwdinfo->profileinfo
++ // Ex: 1XX:XX:XX:XX:XX:XXYYSSID
++ for( jj = 0, kk = 1; jj < ETH_ALEN; jj++, kk += 3 )
++ {
++ pwdinfo->profileinfo[ pwdinfo->profileindex ].peermac[ jj ] = key_2char2num(extra[ kk ], extra[ kk+ 1 ]);
++ }
++
++ //pwdinfo->profileinfo[ pwdinfo->profileindex ].ssidlen = ( extra[18] - '0' ) * 10 + ( extra[ 19 ] - '0' );
++ //_rtw_memcpy( pwdinfo->profileinfo[ pwdinfo->profileindex ].ssid, &extra[ 20 ], pwdinfo->profileinfo[ pwdinfo->profileindex ].ssidlen );
++ pwdinfo->profileindex++;
++ }
++ }
++ }
++
++ return ret;
++
++}
++
++static int rtw_p2p_setDN(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++
++ int ret = 0;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo);
++
++
++ DBG_871X( "[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length -1 );
++
++ _rtw_memset( pwdinfo->device_name, 0x00, WPS_MAX_DEVICE_NAME_LEN );
++ _rtw_memcpy( pwdinfo->device_name, extra, wrqu->data.length - 1 );
++ pwdinfo->device_name_len = wrqu->data.length - 1;
++ return ret;
++
++}
++
++
++static int rtw_p2p_get_status(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++
++ int ret = 0;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct iw_point *pdata = &wrqu->data;
++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo );
++
++
++ if ( padapter->bShowGetP2PState )
++ {
++ DBG_871X( "[%s] Role = %d, Status = %d, peer addr = %.2X:%.2X:%.2X:%.2X:%.2X:%.2X\n", __FUNCTION__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo),
++ pwdinfo->p2p_peer_interface_addr[ 0 ], pwdinfo->p2p_peer_interface_addr[ 1 ], pwdinfo->p2p_peer_interface_addr[ 2 ],
++ pwdinfo->p2p_peer_interface_addr[ 3 ], pwdinfo->p2p_peer_interface_addr[ 4 ], pwdinfo->p2p_peer_interface_addr[ 5 ]);
++ }
++
++ // Commented by Albert 2010/10/12
++ // Because of the output size limitation, I had removed the "Role" information.
++ // About the "Role" information, we will use the new private IOCTL to get the "Role" information.
++ sprintf( extra, "\n\nStatus=%.2d\n", rtw_p2p_state(pwdinfo) );
++ wrqu->data.length = strlen( extra );
++
++ return ret;
++
++}
++
++// Commented by Albert 20110520
++// This function will return the config method description
++// This config method description will show us which config method the remote P2P device is intented to use
++// by sending the provisioning discovery request frame.
++
++static int rtw_p2p_get_req_cm(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++
++ int ret = 0;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct iw_point *pdata = &wrqu->data;
++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo );
++
++ sprintf( extra, "\n\nCM=%s\n", pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req );
++ wrqu->data.length = strlen( extra );
++ return ret;
++
++}
++
++
++static int rtw_p2p_get_role(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++
++ int ret = 0;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct iw_point *pdata = &wrqu->data;
++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo );
++
++
++ DBG_871X( "[%s] Role = %d, Status = %d, peer addr = %.2X:%.2X:%.2X:%.2X:%.2X:%.2X\n", __FUNCTION__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo),
++ pwdinfo->p2p_peer_interface_addr[ 0 ], pwdinfo->p2p_peer_interface_addr[ 1 ], pwdinfo->p2p_peer_interface_addr[ 2 ],
++ pwdinfo->p2p_peer_interface_addr[ 3 ], pwdinfo->p2p_peer_interface_addr[ 4 ], pwdinfo->p2p_peer_interface_addr[ 5 ]);
++
++ sprintf( extra, "\n\nRole=%.2d\n", rtw_p2p_role(pwdinfo) );
++ wrqu->data.length = strlen( extra );
++ return ret;
++
++}
++
++
++static int rtw_p2p_get_peer_ifaddr(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++
++ int ret = 0;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct iw_point *pdata = &wrqu->data;
++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo );
++
++
++ DBG_871X( "[%s] Role = %d, Status = %d, peer addr = %.2X:%.2X:%.2X:%.2X:%.2X:%.2X\n", __FUNCTION__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo),
++ pwdinfo->p2p_peer_interface_addr[ 0 ], pwdinfo->p2p_peer_interface_addr[ 1 ], pwdinfo->p2p_peer_interface_addr[ 2 ],
++ pwdinfo->p2p_peer_interface_addr[ 3 ], pwdinfo->p2p_peer_interface_addr[ 4 ], pwdinfo->p2p_peer_interface_addr[ 5 ]);
++
++ sprintf( extra, "\nMAC %.2X:%.2X:%.2X:%.2X:%.2X:%.2X",
++ pwdinfo->p2p_peer_interface_addr[ 0 ], pwdinfo->p2p_peer_interface_addr[ 1 ], pwdinfo->p2p_peer_interface_addr[ 2 ],
++ pwdinfo->p2p_peer_interface_addr[ 3 ], pwdinfo->p2p_peer_interface_addr[ 4 ], pwdinfo->p2p_peer_interface_addr[ 5 ]);
++ wrqu->data.length = strlen( extra );
++ return ret;
++
++}
++
++static int rtw_p2p_get_peer_devaddr(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++
++{
++
++ int ret = 0;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct iw_point *pdata = &wrqu->data;
++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo );
++
++ DBG_871X( "[%s] Role = %d, Status = %d, peer addr = %.2X:%.2X:%.2X:%.2X:%.2X:%.2X\n", __FUNCTION__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo),
++ pwdinfo->rx_prov_disc_info.peerDevAddr[ 0 ], pwdinfo->rx_prov_disc_info.peerDevAddr[ 1 ],
++ pwdinfo->rx_prov_disc_info.peerDevAddr[ 2 ], pwdinfo->rx_prov_disc_info.peerDevAddr[ 3 ],
++ pwdinfo->rx_prov_disc_info.peerDevAddr[ 4 ], pwdinfo->rx_prov_disc_info.peerDevAddr[ 5 ]);
++ sprintf( extra, "\n%.2X%.2X%.2X%.2X%.2X%.2X",
++ pwdinfo->rx_prov_disc_info.peerDevAddr[ 0 ], pwdinfo->rx_prov_disc_info.peerDevAddr[ 1 ],
++ pwdinfo->rx_prov_disc_info.peerDevAddr[ 2 ], pwdinfo->rx_prov_disc_info.peerDevAddr[ 3 ],
++ pwdinfo->rx_prov_disc_info.peerDevAddr[ 4 ], pwdinfo->rx_prov_disc_info.peerDevAddr[ 5 ]);
++ wrqu->data.length = strlen( extra );
++ return ret;
++
++}
++
++static int rtw_p2p_get_peer_devaddr_by_invitation(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++
++{
++
++ int ret = 0;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct iw_point *pdata = &wrqu->data;
++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo );
++
++ DBG_871X( "[%s] Role = %d, Status = %d, peer addr = %.2X:%.2X:%.2X:%.2X:%.2X:%.2X\n", __FUNCTION__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo),
++ pwdinfo->p2p_peer_device_addr[ 0 ], pwdinfo->p2p_peer_device_addr[ 1 ],
++ pwdinfo->p2p_peer_device_addr[ 2 ], pwdinfo->p2p_peer_device_addr[ 3 ],
++ pwdinfo->p2p_peer_device_addr[ 4 ], pwdinfo->p2p_peer_device_addr[ 5 ]);
++ sprintf( extra, "\nMAC %.2X:%.2X:%.2X:%.2X:%.2X:%.2X",
++ pwdinfo->p2p_peer_device_addr[ 0 ], pwdinfo->p2p_peer_device_addr[ 1 ],
++ pwdinfo->p2p_peer_device_addr[ 2 ], pwdinfo->p2p_peer_device_addr[ 3 ],
++ pwdinfo->p2p_peer_device_addr[ 4 ], pwdinfo->p2p_peer_device_addr[ 5 ]);
++ wrqu->data.length = strlen( extra );
++ return ret;
++
++}
++
++static int rtw_p2p_get_groupid(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++
++{
++
++ int ret = 0;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct iw_point *pdata = &wrqu->data;
++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo );
++
++ sprintf( extra, "\n%.2X:%.2X:%.2X:%.2X:%.2X:%.2X %s",
++ pwdinfo->groupid_info.go_device_addr[ 0 ], pwdinfo->groupid_info.go_device_addr[ 1 ],
++ pwdinfo->groupid_info.go_device_addr[ 2 ], pwdinfo->groupid_info.go_device_addr[ 3 ],
++ pwdinfo->groupid_info.go_device_addr[ 4 ], pwdinfo->groupid_info.go_device_addr[ 5 ],
++ pwdinfo->groupid_info.ssid);
++ wrqu->data.length = strlen( extra );
++ return ret;
++
++}
++
++static int rtw_p2p_get_op_ch(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++
++{
++
++ int ret = 0;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct iw_point *pdata = &wrqu->data;
++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo );
++
++
++ DBG_871X( "[%s] Op_ch = %02x\n", __FUNCTION__, pwdinfo->operating_channel);
++
++ sprintf( extra, "\n\nOp_ch=%.2d\n", pwdinfo->operating_channel );
++ wrqu->data.length = strlen( extra );
++ return ret;
++
++}
++
++inline static void macstr2num(u8 *dst, u8 *src)
++{
++ int jj, kk;
++ for (jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3)
++ {
++ dst[jj] = key_2char2num(src[kk], src[kk + 1]);
++ }
++}
++
++static int rtw_p2p_get_wps_configmethod(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra, char *subcmd)
++{
++
++ int ret = 0;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ u8 peerMAC[ETH_ALEN] = { 0x00 };
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ _irqL irqL;
++ _list * plist,*phead;
++ _queue *queue = &(pmlmepriv->scanned_queue);
++ struct wlan_network *pnetwork = NULL;
++ u8 blnMatch = 0;
++ u16 attr_content = 0;
++ uint attr_contentlen = 0;
++ u8 attr_content_str[P2P_PRIVATE_IOCTL_SET_LEN] = { 0x00 };
++
++ // Commented by Albert 20110727
++ // The input data is the MAC address which the application wants to know its WPS config method.
++ // After knowing its WPS config method, the application can decide the config method for provisioning discovery.
++ // Format: iwpriv wlanx p2p_get_wpsCM 00:E0:4C:00:00:05
++
++ DBG_871X("[%s] data = %s\n", __FUNCTION__, subcmd);
++
++ macstr2num(peerMAC, subcmd);
++
++ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++
++ phead = get_list_head(queue);
++ plist = get_next(phead);
++
++ while (1)
++ {
++ if (rtw_end_of_queue_search(phead, plist) == _TRUE) break;
++
++ pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
++ if (_rtw_memcmp(pnetwork->network.MacAddress, peerMAC, ETH_ALEN))
++ {
++ u8 *wpsie;
++ uint wpsie_len = 0;
++
++ // The mac address is matched.
++
++ if ((wpsie = rtw_get_wps_ie(&pnetwork->network.IEs[12], pnetwork->network.IELength - 12, NULL, &wpsie_len)))
++ {
++ rtw_get_wps_attr_content(wpsie, wpsie_len, WPS_ATTR_CONF_METHOD, (u8 *)&attr_content, &attr_contentlen);
++ if (attr_contentlen)
++ {
++ attr_content = be16_to_cpu(attr_content);
++ sprintf(attr_content_str, "\n\nM=%.4d", attr_content);
++ blnMatch = 1;
++ }
++ }
++
++ break;
++ }
++
++ plist = get_next(plist);
++
++ }
++
++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++
++ if (!blnMatch)
++ {
++ sprintf(attr_content_str, "\n\nM=0000");
++ }
++
++ wrqu->data.length = strlen(attr_content_str);
++ _rtw_memcpy(extra, attr_content_str, wrqu->data.length);
++
++ return ret;
++
++}
++
++#ifdef CONFIG_WFD
++static int rtw_p2p_get_peer_wfd_port(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++
++ int ret = 0;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct iw_point *pdata = &wrqu->data;
++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo );
++
++ DBG_871X( "[%s] p2p_state = %d\n", __FUNCTION__, rtw_p2p_state(pwdinfo) );
++
++ sprintf( extra, "\n\nPort=%d\n", pwdinfo->wfd_info->peer_rtsp_ctrlport );
++ DBG_871X( "[%s] remote port = %d\n", __FUNCTION__, pwdinfo->wfd_info->peer_rtsp_ctrlport );
++
++ wrqu->data.length = strlen( extra );
++ return ret;
++
++}
++
++static int rtw_p2p_get_peer_wfd_preferred_connection(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++
++ int ret = 0;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct iw_point *pdata = &wrqu->data;
++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo );
++
++ sprintf( extra, "\n\nwfd_pc=%d\n", pwdinfo->wfd_info->wfd_pc );
++ DBG_871X( "[%s] wfd_pc = %d\n", __FUNCTION__, pwdinfo->wfd_info->wfd_pc );
++
++ wrqu->data.length = strlen( extra );
++ pwdinfo->wfd_info->wfd_pc = _FALSE; // Reset the WFD preferred connection to P2P
++ return ret;
++
++}
++
++static int rtw_p2p_get_peer_wfd_session_available(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++
++ int ret = 0;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct iw_point *pdata = &wrqu->data;
++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo );
++
++ sprintf( extra, "\n\nwfd_sa=%d\n", pwdinfo->wfd_info->peer_session_avail );
++ DBG_871X( "[%s] wfd_sa = %d\n", __FUNCTION__, pwdinfo->wfd_info->peer_session_avail );
++
++ wrqu->data.length = strlen( extra );
++ pwdinfo->wfd_info->peer_session_avail = _TRUE; // Reset the WFD session available
++ return ret;
++
++}
++
++#endif // CONFIG_WFD
++
++static int rtw_p2p_get_go_device_address(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra, char *subcmd)
++{
++
++ int ret = 0;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ u8 peerMAC[ETH_ALEN] = { 0x00 };
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ _irqL irqL;
++ _list *plist, *phead;
++ _queue *queue = &(pmlmepriv->scanned_queue);
++ struct wlan_network *pnetwork = NULL;
++ u8 blnMatch = 0;
++ u8 *p2pie;
++ uint p2pielen = 0, attr_contentlen = 0;
++ u8 attr_content[100] = { 0x00 };
++ u8 go_devadd_str[P2P_PRIVATE_IOCTL_SET_LEN] = { 0x00 };
++
++ // Commented by Albert 20121209
++ // The input data is the GO's interface address which the application wants to know its device address.
++ // Format: iwpriv wlanx p2p_get2 go_devadd=00:E0:4C:00:00:05
++
++ DBG_871X("[%s] data = %s\n", __FUNCTION__, subcmd);
++
++ macstr2num(peerMAC, subcmd);
++
++ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++
++ phead = get_list_head(queue);
++ plist = get_next(phead);
++
++ while (1)
++ {
++ if (rtw_end_of_queue_search(phead, plist) == _TRUE) break;
++
++ pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
++ if (_rtw_memcmp(pnetwork->network.MacAddress, peerMAC, ETH_ALEN))
++ {
++ // Commented by Albert 2011/05/18
++ // Match the device address located in the P2P IE
++ // This is for the case that the P2P device address is not the same as the P2P interface address.
++
++ if ((p2pie = rtw_get_p2p_ie(&pnetwork->network.IEs[12], pnetwork->network.IELength - 12, NULL, &p2pielen)))
++ {
++ while (p2pie)
++ {
++ // The P2P Device ID attribute is included in the Beacon frame.
++ // The P2P Device Info attribute is included in the probe response frame.
++
++ _rtw_memset(attr_content, 0x00, 100);
++ if (rtw_get_p2p_attr_content(p2pie, p2pielen, P2P_ATTR_DEVICE_ID, attr_content, &attr_contentlen))
++ {
++ // Handle the P2P Device ID attribute of Beacon first
++ blnMatch = 1;
++ break;
++
++ } else if (rtw_get_p2p_attr_content(p2pie, p2pielen, P2P_ATTR_DEVICE_INFO, attr_content, &attr_contentlen))
++ {
++ // Handle the P2P Device Info attribute of probe response
++ blnMatch = 1;
++ break;
++ }
++
++ //Get the next P2P IE
++ p2pie = rtw_get_p2p_ie(p2pie + p2pielen, pnetwork->network.IELength - 12 - (p2pie - &pnetwork->network.IEs[12] + p2pielen), NULL, &p2pielen);
++ }
++ }
++ }
++
++ plist = get_next(plist);
++
++ }
++
++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++
++ if (!blnMatch)
++ {
++ sprintf(go_devadd_str, "\n\ndev_add=NULL");
++ } else
++ {
++ sprintf(go_devadd_str, "\n\ndev_add=%.2X:%.2X:%.2X:%.2X:%.2X:%.2X",
++ attr_content[0], attr_content[1], attr_content[2], attr_content[3], attr_content[4], attr_content[5]);
++ }
++
++ wrqu->data.length = strlen(go_devadd_str);
++ _rtw_memcpy(extra, go_devadd_str, wrqu->data.length);
++
++ return ret;
++
++}
++
++static int rtw_p2p_get_device_type(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra, char *subcmd)
++{
++
++ int ret = 0;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ u8 peerMAC[ETH_ALEN] = { 0x00 };
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ _irqL irqL;
++ _list *plist, *phead;
++ _queue *queue = &(pmlmepriv->scanned_queue);
++ struct wlan_network *pnetwork = NULL;
++ u8 blnMatch = 0;
++ u8 dev_type[8] = { 0x00 };
++ uint dev_type_len = 0;
++ u8 dev_type_str[P2P_PRIVATE_IOCTL_SET_LEN] = { 0x00 }; // +9 is for the str "dev_type=", we have to clear it at wrqu->data.pointer
++
++ // Commented by Albert 20121209
++ // The input data is the MAC address which the application wants to know its device type.
++ // Such user interface could know the device type.
++ // Format: iwpriv wlanx p2p_get2 dev_type=00:E0:4C:00:00:05
++
++ DBG_871X("[%s] data = %s\n", __FUNCTION__, subcmd);
++
++ macstr2num(peerMAC, subcmd);
++
++ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++
++ phead = get_list_head(queue);
++ plist = get_next(phead);
++
++ while (1)
++ {
++ if (rtw_end_of_queue_search(phead, plist) == _TRUE) break;
++
++ pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
++ if (_rtw_memcmp(pnetwork->network.MacAddress, peerMAC, ETH_ALEN))
++ {
++ u8 *wpsie;
++ uint wpsie_len = 0;
++
++ // The mac address is matched.
++
++ if ((wpsie = rtw_get_wps_ie(&pnetwork->network.IEs[12], pnetwork->network.IELength - 12, NULL, &wpsie_len)))
++ {
++ rtw_get_wps_attr_content(wpsie, wpsie_len, WPS_ATTR_PRIMARY_DEV_TYPE, dev_type, &dev_type_len);
++ if (dev_type_len)
++ {
++ u16 type = 0;
++
++ _rtw_memcpy(&type, dev_type, 2);
++ type = be16_to_cpu(type);
++ sprintf(dev_type_str, "\n\nN=%.2d", type);
++ blnMatch = 1;
++ }
++ }
++ break;
++ }
++
++ plist = get_next(plist);
++
++ }
++
++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++
++ if (!blnMatch)
++ {
++ sprintf(dev_type_str, "\n\nN=00");
++ }
++
++ wrqu->data.length = strlen(dev_type_str);
++ _rtw_memcpy(extra, dev_type_str, wrqu->data.length);
++
++ return ret;
++
++}
++
++static int rtw_p2p_get_device_name(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra, char *subcmd)
++{
++
++ int ret = 0;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ u8 peerMAC[ETH_ALEN] = { 0x00 };
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ _irqL irqL;
++ _list *plist, *phead;
++ _queue *queue = &(pmlmepriv->scanned_queue);
++ struct wlan_network *pnetwork = NULL;
++ u8 blnMatch = 0;
++ u8 dev_name[WPS_MAX_DEVICE_NAME_LEN] = { 0x00 };
++ uint dev_len = 0;
++ u8 dev_name_str[P2P_PRIVATE_IOCTL_SET_LEN] = { 0x00 };
++
++ // Commented by Albert 20121225
++ // The input data is the MAC address which the application wants to know its device name.
++ // Such user interface could show peer device's device name instead of ssid.
++ // Format: iwpriv wlanx p2p_get2 devN=00:E0:4C:00:00:05
++
++ DBG_871X("[%s] data = %s\n", __FUNCTION__, subcmd);
++
++ macstr2num(peerMAC, subcmd);
++
++ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++
++ phead = get_list_head(queue);
++ plist = get_next(phead);
++
++ while (1)
++ {
++ if (rtw_end_of_queue_search(phead, plist) == _TRUE) break;
++
++ pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
++ if (_rtw_memcmp(pnetwork->network.MacAddress, peerMAC, ETH_ALEN))
++ {
++ u8 *wpsie;
++ uint wpsie_len = 0;
++
++ // The mac address is matched.
++
++ if ((wpsie = rtw_get_wps_ie(&pnetwork->network.IEs[12], pnetwork->network.IELength - 12, NULL, &wpsie_len)))
++ {
++ rtw_get_wps_attr_content(wpsie, wpsie_len, WPS_ATTR_DEVICE_NAME, dev_name, &dev_len);
++ if (dev_len)
++ {
++ sprintf(dev_name_str, "\n\nN=%s", dev_name);
++ blnMatch = 1;
++ }
++ }
++ break;
++ }
++
++ plist = get_next(plist);
++
++ }
++
++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++
++ if (!blnMatch)
++ {
++ sprintf(dev_name_str, "\n\nN=0000");
++ }
++
++ wrqu->data.length = strlen(dev_name_str);
++ _rtw_memcpy(extra, dev_name_str, wrqu->data.length);
++
++ return ret;
++
++}
++
++static int rtw_p2p_get_invitation_procedure(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra, char *subcmd)
++{
++
++ int ret = 0;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ u8 peerMAC[ETH_ALEN] = { 0x00 };
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ _irqL irqL;
++ _list *plist, *phead;
++ _queue *queue = &(pmlmepriv->scanned_queue);
++ struct wlan_network *pnetwork = NULL;
++ u8 blnMatch = 0;
++ u8 *p2pie;
++ uint p2pielen = 0, attr_contentlen = 0;
++ u8 attr_content[2] = { 0x00 };
++ u8 inv_proc_str[P2P_PRIVATE_IOCTL_SET_LEN] = { 0x00 };
++
++ // Commented by Ouden 20121226
++ // The application wants to know P2P initation procedure is support or not.
++ // Format: iwpriv wlanx p2p_get2 InvProc=00:E0:4C:00:00:05
++
++ DBG_871X("[%s] data = %s\n", __FUNCTION__, subcmd);
++
++ macstr2num(peerMAC, subcmd);
++
++ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++
++ phead = get_list_head(queue);
++ plist = get_next(phead);
++
++ while (1)
++ {
++ if (rtw_end_of_queue_search(phead, plist) == _TRUE) break;
++
++ pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
++ if (_rtw_memcmp(pnetwork->network.MacAddress, peerMAC, ETH_ALEN))
++ {
++ // Commented by Albert 20121226
++ // Match the device address located in the P2P IE
++ // This is for the case that the P2P device address is not the same as the P2P interface address.
++
++ if ((p2pie = rtw_get_p2p_ie(&pnetwork->network.IEs[12], pnetwork->network.IELength - 12, NULL, &p2pielen)))
++ {
++ while (p2pie)
++ {
++ //_rtw_memset( attr_content, 0x00, 2);
++ if (rtw_get_p2p_attr_content(p2pie, p2pielen, P2P_ATTR_CAPABILITY, attr_content, &attr_contentlen))
++ {
++ // Handle the P2P capability attribute
++ blnMatch = 1;
++ break;
++
++ }
++
++ //Get the next P2P IE
++ p2pie = rtw_get_p2p_ie(p2pie + p2pielen, pnetwork->network.IELength - 12 - (p2pie - &pnetwork->network.IEs[12] + p2pielen), NULL, &p2pielen);
++ }
++ }
++ }
++
++ plist = get_next(plist);
++
++ }
++
++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++
++ if (!blnMatch)
++ {
++ sprintf(inv_proc_str, "\nIP=-1");
++ } else
++ {
++ if (attr_content[0] && 0x20)
++ {
++ sprintf(inv_proc_str, "\nIP=1");
++ } else
++ {
++ sprintf(inv_proc_str, "\nIP=0");
++ }
++ }
++
++ wrqu->data.length = strlen(inv_proc_str);
++ _rtw_memcpy(extra, inv_proc_str, wrqu->data.length);
++
++ return ret;
++
++}
++
++static int rtw_p2p_connect(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++
++ int ret = 0;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo );
++ u8 peerMAC[ ETH_ALEN ] = { 0x00 };
++ int jj,kk;
++ u8 peerMACStr[ ETH_ALEN * 2 ] = { 0x00 };
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ _irqL irqL;
++ _list *plist, *phead;
++ _queue *queue = &(pmlmepriv->scanned_queue);
++ struct wlan_network *pnetwork = NULL;
++ uint uintPeerChannel = 0;
++#ifdef CONFIG_CONCURRENT_MODE
++ _adapter *pbuddy_adapter = padapter->pbuddy_adapter;
++ struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv;
++#endif // CONFIG_CONCURRENT_MODE
++
++
++ // Commented by Albert 20110304
++ // The input data contains two informations.
++ // 1. First information is the MAC address which wants to formate with
++ // 2. Second information is the WPS PINCode or "pbc" string for push button method
++ // Format: 00:E0:4C:00:00:05
++ // Format: 00:E0:4C:00:00:05
++
++ DBG_871X( "[%s] data = %s\n", __FUNCTION__, extra );
++
++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
++ {
++ DBG_871X( "[%s] WiFi Direct is disable!\n", __FUNCTION__ );
++ return ret;
++ }
++
++ if ( pwdinfo->ui_got_wps_info == P2P_NO_WPSINFO )
++ {
++ return -1;
++ }
++
++ for( jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3 )
++ {
++ peerMAC[ jj ] = key_2char2num( extra[kk], extra[kk+ 1] );
++ }
++
++ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++
++ phead = get_list_head(queue);
++ plist = get_next(phead);
++
++ while(1)
++ {
++ if (rtw_end_of_queue_search(phead,plist)== _TRUE)
++ break;
++
++ pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
++ if ( _rtw_memcmp( pnetwork->network.MacAddress, peerMAC, ETH_ALEN ) )
++ {
++ uintPeerChannel = pnetwork->network.Configuration.DSConfig;
++ break;
++ }
++
++ plist = get_next(plist);
++
++ }
++
++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++
++ if ( uintPeerChannel )
++ {
++#ifdef CONFIG_CONCURRENT_MODE
++ if ( check_buddy_fwstate(padapter, _FW_LINKED ) )
++ {
++ _cancel_timer_ex( &pwdinfo->ap_p2p_switch_timer );
++ }
++#endif // CONFIG_CONCURRENT_MODE
++
++ _rtw_memset( &pwdinfo->nego_req_info, 0x00, sizeof( struct tx_nego_req_info ) );
++ _rtw_memset( &pwdinfo->groupid_info, 0x00, sizeof( struct group_id_info ) );
++
++ pwdinfo->nego_req_info.peer_channel_num[ 0 ] = uintPeerChannel;
++ _rtw_memcpy( pwdinfo->nego_req_info.peerDevAddr, pnetwork->network.MacAddress, ETH_ALEN );
++ pwdinfo->nego_req_info.benable = _TRUE;
++
++ _cancel_timer_ex( &pwdinfo->restore_p2p_state_timer );
++ if ( rtw_p2p_state(pwdinfo) != P2P_STATE_GONEGO_OK )
++ {
++ // Restore to the listen state if the current p2p state is not nego OK
++ rtw_p2p_set_state(pwdinfo, P2P_STATE_LISTEN );
++ }
++
++ rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo));
++ rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_ING);
++
++#ifdef CONFIG_CONCURRENT_MODE
++ if ( check_buddy_fwstate(padapter, _FW_LINKED ) )
++ {
++ // Have to enter the power saving with the AP
++ set_channel_bwmode(padapter, pbuddy_mlmeext->cur_channel, pbuddy_mlmeext->cur_ch_offset, pbuddy_mlmeext->cur_bwmode);
++
++ issue_nulldata(pbuddy_adapter, NULL, 1, 3, 500);
++ }
++#endif // CONFIG_CONCURRENT_MODE
++
++ DBG_871X( "[%s] Start PreTx Procedure!\n", __FUNCTION__ );
++ _set_timer( &pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT );
++
++#ifdef CONFIG_CONCURRENT_MODE
++ if ( check_buddy_fwstate(padapter, _FW_LINKED ) )
++ {
++ _set_timer( &pwdinfo->restore_p2p_state_timer, P2P_CONCURRENT_GO_NEGO_TIMEOUT );
++ }
++ else
++ {
++ _set_timer( &pwdinfo->restore_p2p_state_timer, P2P_GO_NEGO_TIMEOUT );
++ }
++#else
++ _set_timer( &pwdinfo->restore_p2p_state_timer, P2P_GO_NEGO_TIMEOUT );
++#endif // CONFIG_CONCURRENT_MODE
++
++ }
++ else
++ {
++ DBG_871X( "[%s] Not Found in Scanning Queue~\n", __FUNCTION__ );
++ ret = -1;
++ }
++exit:
++ return ret;
++}
++
++static int rtw_p2p_invite_req(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++
++ int ret = 0;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct iw_point *pdata = &wrqu->data;
++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo );
++ int jj,kk;
++ u8 peerMACStr[ ETH_ALEN * 2 ] = { 0x00 };
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ _list *plist, *phead;
++ _queue *queue = &(pmlmepriv->scanned_queue);
++ struct wlan_network *pnetwork = NULL;
++ uint uintPeerChannel = 0;
++ u8 attr_content[50] = { 0x00 }, _status = 0;
++ u8 *p2pie;
++ uint p2pielen = 0, attr_contentlen = 0;
++ _irqL irqL;
++ struct tx_invite_req_info* pinvite_req_info = &pwdinfo->invitereq_info;
++#ifdef CONFIG_CONCURRENT_MODE
++ _adapter *pbuddy_adapter = padapter->pbuddy_adapter;
++ struct mlme_priv *pbuddy_mlmepriv = &pbuddy_adapter->mlmepriv;
++ struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv;
++#endif // CONFIG_CONCURRENT_MODE
++
++#ifdef CONFIG_WFD
++ struct wifi_display_info* pwfd_info = pwdinfo->wfd_info;
++#endif // CONFIG_WFD
++
++ // Commented by Albert 20120321
++ // The input data contains two informations.
++ // 1. First information is the P2P device address which you want to send to.
++ // 2. Second information is the group id which combines with GO's mac address, space and GO's ssid.
++ // Command line sample: iwpriv wlan0 p2p_set invite="00:11:22:33:44:55 00:E0:4C:00:00:05 DIRECT-xy"
++ // Format: 00:11:22:33:44:55 00:E0:4C:00:00:05 DIRECT-xy
++
++ DBG_871X( "[%s] data = %s\n", __FUNCTION__, extra );
++
++ if ( wrqu->data.length <= 37 )
++ {
++ DBG_871X( "[%s] Wrong format!\n", __FUNCTION__ );
++ return ret;
++ }
++
++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
++ {
++ DBG_871X( "[%s] WiFi Direct is disable!\n", __FUNCTION__ );
++ return ret;
++ }
++ else
++ {
++ // Reset the content of struct tx_invite_req_info
++ pinvite_req_info->benable = _FALSE;
++ _rtw_memset( pinvite_req_info->go_bssid, 0x00, ETH_ALEN );
++ _rtw_memset( pinvite_req_info->go_ssid, 0x00, WLAN_SSID_MAXLEN );
++ pinvite_req_info->ssidlen = 0x00;
++ pinvite_req_info->operating_ch = pwdinfo->operating_channel;
++ _rtw_memset( pinvite_req_info->peer_macaddr, 0x00, ETH_ALEN );
++ pinvite_req_info->token = 3;
++ }
++
++ for( jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3 )
++ {
++ pinvite_req_info->peer_macaddr[ jj ] = key_2char2num( extra[kk], extra[kk+ 1] );
++ }
++
++ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++
++ phead = get_list_head(queue);
++ plist = get_next(phead);
++
++ while(1)
++ {
++ if (rtw_end_of_queue_search(phead,plist)== _TRUE)
++ break;
++
++ pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
++
++ // Commented by Albert 2011/05/18
++ // Match the device address located in the P2P IE
++ // This is for the case that the P2P device address is not the same as the P2P interface address.
++
++ if ( (p2pie=rtw_get_p2p_ie( &pnetwork->network.IEs[12], pnetwork->network.IELength - 12, NULL, &p2pielen)) )
++ {
++ // The P2P Device ID attribute is included in the Beacon frame.
++ // The P2P Device Info attribute is included in the probe response frame.
++
++ if ( rtw_get_p2p_attr_content( p2pie, p2pielen, P2P_ATTR_DEVICE_ID, attr_content, &attr_contentlen) )
++ {
++ // Handle the P2P Device ID attribute of Beacon first
++ if ( _rtw_memcmp( attr_content, pinvite_req_info->peer_macaddr, ETH_ALEN ) )
++ {
++ uintPeerChannel = pnetwork->network.Configuration.DSConfig;
++ break;
++ }
++ }
++ else if ( rtw_get_p2p_attr_content( p2pie, p2pielen, P2P_ATTR_DEVICE_INFO, attr_content, &attr_contentlen) )
++ {
++ // Handle the P2P Device Info attribute of probe response
++ if ( _rtw_memcmp( attr_content, pinvite_req_info->peer_macaddr, ETH_ALEN ) )
++ {
++ uintPeerChannel = pnetwork->network.Configuration.DSConfig;
++ break;
++ }
++ }
++
++ }
++
++ plist = get_next(plist);
++
++ }
++
++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++
++#ifdef CONFIG_WFD
++ if ( uintPeerChannel )
++ {
++ u8 wfd_ie[ 128 ] = { 0x00 };
++ uint wfd_ielen = 0;
++
++ if ( rtw_get_wfd_ie( &pnetwork->network.IEs[12], pnetwork->network.IELength - 12, wfd_ie, &wfd_ielen ) )
++ {
++ u8 wfd_devinfo[ 6 ] = { 0x00 };
++ uint wfd_devlen = 6;
++
++ DBG_871X( "[%s] Found WFD IE!\n", __FUNCTION__ );
++ if ( rtw_get_wfd_attr_content( wfd_ie, wfd_ielen, WFD_ATTR_DEVICE_INFO, wfd_devinfo, &wfd_devlen ) )
++ {
++ u16 wfd_devinfo_field = 0;
++
++ // Commented by Albert 20120319
++ // The first two bytes are the WFD device information field of WFD device information subelement.
++ // In big endian format.
++ wfd_devinfo_field = RTW_GET_BE16(wfd_devinfo);
++ if ( wfd_devinfo_field & WFD_DEVINFO_SESSION_AVAIL )
++ {
++ pwfd_info->peer_session_avail = _TRUE;
++ }
++ else
++ {
++ pwfd_info->peer_session_avail = _FALSE;
++ }
++ }
++ }
++
++ if ( _FALSE == pwfd_info->peer_session_avail )
++ {
++ DBG_871X( "[%s] WFD Session not avaiable!\n", __FUNCTION__ );
++ goto exit;
++ }
++ }
++#endif // CONFIG_WFD
++
++ if ( uintPeerChannel )
++ {
++#ifdef CONFIG_CONCURRENT_MODE
++ if ( check_fwstate( pbuddy_mlmepriv, _FW_LINKED ) )
++ {
++ _cancel_timer_ex( &pwdinfo->ap_p2p_switch_timer );
++ }
++#endif // CONFIG_CONCURRENT_MODE
++
++ // Store the GO's bssid
++ for( jj = 0, kk = 18; jj < ETH_ALEN; jj++, kk += 3 )
++ {
++ pinvite_req_info->go_bssid[ jj ] = key_2char2num( extra[kk], extra[kk+ 1] );
++ }
++
++ // Store the GO's ssid
++ pinvite_req_info->ssidlen = wrqu->data.length - 36;
++ _rtw_memcpy( pinvite_req_info->go_ssid, &extra[ 36 ], (u32) pinvite_req_info->ssidlen );
++ pinvite_req_info->benable = _TRUE;
++ pinvite_req_info->peer_ch = uintPeerChannel;
++
++ rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo));
++ rtw_p2p_set_state(pwdinfo, P2P_STATE_TX_INVITE_REQ);
++
++#ifdef CONFIG_CONCURRENT_MODE
++ if ( check_fwstate( pbuddy_mlmepriv, _FW_LINKED ) )
++ {
++ // Have to enter the power saving with the AP
++ set_channel_bwmode(padapter, pbuddy_mlmeext->cur_channel, pbuddy_mlmeext->cur_ch_offset, pbuddy_mlmeext->cur_bwmode);
++
++ issue_nulldata(pbuddy_adapter, NULL, 1, 3, 500);
++ }
++ else
++ {
++ set_channel_bwmode(padapter, uintPeerChannel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HT_CHANNEL_WIDTH_20);
++ }
++#else
++ set_channel_bwmode(padapter, uintPeerChannel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HT_CHANNEL_WIDTH_20);
++#endif
++
++ _set_timer( &pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT );
++
++#ifdef CONFIG_CONCURRENT_MODE
++ if ( check_fwstate( pbuddy_mlmepriv, _FW_LINKED ) )
++ {
++ _set_timer( &pwdinfo->restore_p2p_state_timer, P2P_CONCURRENT_INVITE_TIMEOUT );
++ }
++ else
++ {
++ _set_timer( &pwdinfo->restore_p2p_state_timer, P2P_INVITE_TIMEOUT );
++ }
++#else
++ _set_timer( &pwdinfo->restore_p2p_state_timer, P2P_INVITE_TIMEOUT );
++#endif // CONFIG_CONCURRENT_MODE
++
++
++ }
++ else
++ {
++ DBG_871X( "[%s] NOT Found in the Scanning Queue!\n", __FUNCTION__ );
++ }
++exit:
++
++ return ret;
++
++}
++
++static int rtw_p2p_set_persistent(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++
++ int ret = 0;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct iw_point *pdata = &wrqu->data;
++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo );
++ int jj,kk;
++ u8 peerMACStr[ ETH_ALEN * 2 ] = { 0x00 };
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ _list *plist, *phead;
++ _queue *queue = &(pmlmepriv->scanned_queue);
++ struct wlan_network *pnetwork = NULL;
++ uint uintPeerChannel = 0;
++ u8 attr_content[50] = { 0x00 }, _status = 0;
++ u8 *p2pie;
++ uint p2pielen = 0, attr_contentlen = 0;
++ _irqL irqL;
++ struct tx_invite_req_info* pinvite_req_info = &pwdinfo->invitereq_info;
++#ifdef CONFIG_CONCURRENT_MODE
++ _adapter *pbuddy_adapter = padapter->pbuddy_adapter;
++ struct mlme_priv *pbuddy_mlmepriv = &pbuddy_adapter->mlmepriv;
++ struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv;
++#endif // CONFIG_CONCURRENT_MODE
++
++#ifdef CONFIG_WFD
++ struct wifi_display_info* pwfd_info = pwdinfo->wfd_info;
++#endif // CONFIG_WFD
++
++ // Commented by Albert 20120328
++ // The input data is 0 or 1
++ // 0: disable persistent group functionality
++ // 1: enable persistent group founctionality
++
++ DBG_871X( "[%s] data = %s\n", __FUNCTION__, extra );
++
++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
++ {
++ DBG_871X( "[%s] WiFi Direct is disable!\n", __FUNCTION__ );
++ return ret;
++ }
++ else
++ {
++ if ( extra[ 0 ] == '0' ) // Disable the persistent group function.
++ {
++ pwdinfo->persistent_supported = _FALSE;
++ }
++ else if ( extra[ 0 ] == '1' ) // Enable the persistent group function.
++ {
++ pwdinfo->persistent_supported = _TRUE;
++ }
++ else
++ {
++ pwdinfo->persistent_supported = _FALSE;
++ }
++ }
++ printk( "[%s] persistent_supported = %d\n", __FUNCTION__, pwdinfo->persistent_supported );
++
++exit:
++
++ return ret;
++
++}
++
++static int hexstr2bin(const char *hex, u8 *buf, size_t len)
++{
++ size_t i;
++ int a;
++ const char *ipos = hex;
++ u8 *opos = buf;
++
++ for (i = 0; i < len; i++) {
++ a = hex2byte_i(ipos);
++ if (a < 0)
++ return -1;
++ *opos++ = a;
++ ipos += 2;
++ }
++ return 0;
++}
++
++static int uuid_str2bin(const char *str, u8 *bin)
++{
++ const char *pos;
++ u8 *opos;
++
++ pos = str;
++ opos = bin;
++
++ if (hexstr2bin(pos, opos, 4))
++ return -1;
++ pos += 8;
++ opos += 4;
++
++ if (*pos++ != '-' || hexstr2bin(pos, opos, 2))
++ return -1;
++ pos += 4;
++ opos += 2;
++
++ if (*pos++ != '-' || hexstr2bin(pos, opos, 2))
++ return -1;
++ pos += 4;
++ opos += 2;
++
++ if (*pos++ != '-' || hexstr2bin(pos, opos, 2))
++ return -1;
++ pos += 4;
++ opos += 2;
++
++ if (*pos++ != '-' || hexstr2bin(pos, opos, 6))
++ return -1;
++
++ return 0;
++}
++
++static int rtw_p2p_set_wps_uuid(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++
++ int ret = 0;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
++
++ DBG_871X("[%s] data = %s\n", __FUNCTION__, extra);
++
++ if ((36 == strlen(extra)) && (uuid_str2bin(extra, pwdinfo->uuid) == 0))
++ {
++ pwdinfo->external_uuid = 1;
++ } else {
++ pwdinfo->external_uuid = 0;
++ ret = -EINVAL;
++ }
++
++ return ret;
++
++}
++#ifdef CONFIG_WFD
++static int rtw_p2p_set_pc(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++
++ int ret = 0;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct iw_point *pdata = &wrqu->data;
++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo );
++ u8 peerMAC[ ETH_ALEN ] = { 0x00 };
++ int jj,kk;
++ u8 peerMACStr[ ETH_ALEN * 2 ] = { 0x00 };
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ _list *plist, *phead;
++ _queue *queue = &(pmlmepriv->scanned_queue);
++ struct wlan_network *pnetwork = NULL;
++ u8 attr_content[50] = { 0x00 }, _status = 0;
++ u8 *p2pie;
++ uint p2pielen = 0, attr_contentlen = 0;
++ _irqL irqL;
++ uint uintPeerChannel = 0;
++#ifdef CONFIG_CONCURRENT_MODE
++ _adapter *pbuddy_adapter = padapter->pbuddy_adapter;
++ struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv;
++#endif // CONFIG_CONCURRENT_MODE
++ struct wifi_display_info* pwfd_info = pwdinfo->wfd_info;
++
++ // Commented by Albert 20120512
++ // 1. Input information is the MAC address which wants to know the Preferred Connection bit (PC bit)
++ // Format: 00:E0:4C:00:00:05
++
++ DBG_871X( "[%s] data = %s\n", __FUNCTION__, extra );
++
++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
++ {
++ DBG_871X( "[%s] WiFi Direct is disable!\n", __FUNCTION__ );
++ return ret;
++ }
++
++ for( jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3 )
++ {
++ peerMAC[ jj ] = key_2char2num( extra[kk], extra[kk+ 1] );
++ }
++
++ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++
++ phead = get_list_head(queue);
++ plist = get_next(phead);
++
++ while(1)
++ {
++ if (rtw_end_of_queue_search(phead,plist)== _TRUE)
++ break;
++
++ pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
++
++ // Commented by Albert 2011/05/18
++ // Match the device address located in the P2P IE
++ // This is for the case that the P2P device address is not the same as the P2P interface address.
++
++ if ( (p2pie=rtw_get_p2p_ie( &pnetwork->network.IEs[12], pnetwork->network.IELength - 12, NULL, &p2pielen)) )
++ {
++ // The P2P Device ID attribute is included in the Beacon frame.
++ // The P2P Device Info attribute is included in the probe response frame.
++ printk( "[%s] Got P2P IE\n", __FUNCTION__ );
++ if ( rtw_get_p2p_attr_content( p2pie, p2pielen, P2P_ATTR_DEVICE_ID, attr_content, &attr_contentlen) )
++ {
++ // Handle the P2P Device ID attribute of Beacon first
++ printk( "[%s] P2P_ATTR_DEVICE_ID \n", __FUNCTION__ );
++ if ( _rtw_memcmp( attr_content, peerMAC, ETH_ALEN ) )
++ {
++ uintPeerChannel = pnetwork->network.Configuration.DSConfig;
++ break;
++ }
++ }
++ else if ( rtw_get_p2p_attr_content( p2pie, p2pielen, P2P_ATTR_DEVICE_INFO, attr_content, &attr_contentlen) )
++ {
++ // Handle the P2P Device Info attribute of probe response
++ printk( "[%s] P2P_ATTR_DEVICE_INFO \n", __FUNCTION__ );
++ if ( _rtw_memcmp( attr_content, peerMAC, ETH_ALEN ) )
++ {
++ uintPeerChannel = pnetwork->network.Configuration.DSConfig;
++ break;
++ }
++ }
++
++ }
++
++ plist = get_next(plist);
++
++ }
++
++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++ printk( "[%s] channel = %d\n", __FUNCTION__, uintPeerChannel );
++
++ if ( uintPeerChannel )
++ {
++ u8 wfd_ie[ 128 ] = { 0x00 };
++ uint wfd_ielen = 0;
++
++ if ( rtw_get_wfd_ie( &pnetwork->network.IEs[12], pnetwork->network.IELength - 12, wfd_ie, &wfd_ielen ) )
++ {
++ u8 wfd_devinfo[ 6 ] = { 0x00 };
++ uint wfd_devlen = 6;
++
++ DBG_871X( "[%s] Found WFD IE!\n", __FUNCTION__ );
++ if ( rtw_get_wfd_attr_content( wfd_ie, wfd_ielen, WFD_ATTR_DEVICE_INFO, wfd_devinfo, &wfd_devlen ) )
++ {
++ u16 wfd_devinfo_field = 0;
++
++ // Commented by Albert 20120319
++ // The first two bytes are the WFD device information field of WFD device information subelement.
++ // In big endian format.
++ wfd_devinfo_field = RTW_GET_BE16(wfd_devinfo);
++ if ( wfd_devinfo_field & WFD_DEVINFO_PC_TDLS )
++ {
++ pwfd_info->wfd_pc = _TRUE;
++ }
++ else
++ {
++ pwfd_info->wfd_pc = _FALSE;
++ }
++ }
++ }
++ }
++ else
++ {
++ DBG_871X( "[%s] NOT Found in the Scanning Queue!\n", __FUNCTION__ );
++ }
++
++exit:
++
++ return ret;
++
++}
++
++static int rtw_p2p_set_wfd_device_type(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++
++ int ret = 0;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct iw_point *pdata = &wrqu->data;
++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo );
++ struct wifi_display_info *pwfd_info = pwdinfo->wfd_info;
++
++ // Commented by Albert 20120328
++ // The input data is 0 or 1
++ // 0: specify to Miracast source device
++ // 1 or others: specify to Miracast sink device (display device)
++
++ DBG_871X( "[%s] data = %s\n", __FUNCTION__, extra );
++
++ if ( extra[ 0 ] == '0' ) // Set to Miracast source device.
++ {
++ pwfd_info->wfd_device_type = WFD_DEVINFO_SOURCE;
++ }
++ else // Set to Miracast sink device.
++ {
++ pwfd_info->wfd_device_type = WFD_DEVINFO_PSINK;
++ }
++
++exit:
++
++ return ret;
++
++}
++
++static int rtw_p2p_set_scan_result_type(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++
++ int ret = 0;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct iw_point *pdata = &wrqu->data;
++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo );
++ struct wifi_display_info *pwfd_info = pwdinfo->wfd_info;
++
++ // Commented by Albert 20120328
++ // The input data is 0 , 1 , 2
++ // 0: when the P2P is enabled, the scan result will return all the found P2P device.
++ // 1: when the P2P is enabled, the scan result will return all the found P2P device and AP.
++ // 2: when the P2P is enabled, the scan result will show up the found Miracast devices base on...
++ // It will show up all the Miracast source device if this device is sink.
++ // It will show up all the Miracast sink device if this device is source.
++
++ DBG_871X( "[%s] data = %s\n", __FUNCTION__, extra );
++
++ if ( extra[ 0 ] == '0' )
++ {
++ pwfd_info->scan_result_type = SCAN_RESULT_P2P_ONLY;
++ }
++ else if ( extra[ 0 ] == '1' )
++ {
++ pwfd_info->scan_result_type = SCAN_RESULT_ALL;
++ }
++ else if ( extra[ 0 ] == '2' )
++ {
++ pwfd_info->scan_result_type = SCAN_RESULT_WFD_TYPE;
++ }
++ else
++ {
++ pwfd_info->scan_result_type = SCAN_RESULT_P2P_ONLY;
++ }
++
++exit:
++
++ return ret;
++
++}
++
++static int rtw_p2p_set_wfd_enable(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++// Commented by Kurt 20121206
++// This function is used to set wfd enabled
++
++ int ret = 0;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo);
++
++ if(*extra == '0' )
++ pwdinfo->wfd_info->wfd_enable = _FALSE;
++ else if(*extra == '1')
++ pwdinfo->wfd_info->wfd_enable = _TRUE;
++
++ DBG_871X( "[%s] wfd_enable = %d\n", __FUNCTION__, pwdinfo->wfd_info->wfd_enable );
++
++ return ret;
++
++}
++
++static int rtw_p2p_set_driver_iface(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++// Commented by Kurt 20121206
++// This function is used to set driver iface is WEXT or CFG80211
++ int ret = 0;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo);
++
++ if(*extra == '1' )
++ {
++ pwdinfo->driver_interface = DRIVER_WEXT;
++ DBG_871X( "[%s] driver_interface = WEXT\n", __FUNCTION__);
++ }
++ else if(*extra == '2')
++ {
++ pwdinfo->driver_interface = DRIVER_CFG80211;
++ DBG_871X( "[%s] driver_interface = CFG80211\n", __FUNCTION__);
++ }
++
++ return ret;
++
++}
++
++// To set the WFD session available to enable or disable
++static int rtw_p2p_set_sa(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++
++ int ret = 0;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct iw_point *pdata = &wrqu->data;
++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo );
++ struct wifi_display_info *pwfd_info = pwdinfo->wfd_info;
++
++ DBG_871X( "[%s] data = %s\n", __FUNCTION__, extra );
++
++ if( 0 )
++ {
++ DBG_871X( "[%s] WiFi Direct is disable!\n", __FUNCTION__ );
++ return ret;
++ }
++ else
++ {
++ if ( extra[ 0 ] == '0' ) // Disable the session available.
++ {
++ pwdinfo->session_available = _FALSE;
++ }
++ else if ( extra[ 0 ] == '1' ) // Enable the session available.
++ {
++ pwdinfo->session_available = _TRUE;
++ }
++ else
++ {
++ pwdinfo->session_available = _FALSE;
++ }
++ }
++ printk( "[%s] session available = %d\n", __FUNCTION__, pwdinfo->session_available );
++
++exit:
++
++ return ret;
++
++}
++#endif //CONFIG_WFD
++
++static int rtw_p2p_prov_disc(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++ int ret = 0;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo );
++ u8 peerMAC[ ETH_ALEN ] = { 0x00 };
++ int jj,kk;
++ u8 peerMACStr[ ETH_ALEN * 2 ] = { 0x00 };
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ _list *plist, *phead;
++ _queue *queue = &(pmlmepriv->scanned_queue);
++ struct wlan_network *pnetwork = NULL;
++ uint uintPeerChannel = 0;
++ u8 attr_content[100] = { 0x00 }, _status = 0;
++ u8 *p2pie;
++ uint p2pielen = 0, attr_contentlen = 0;
++ _irqL irqL;
++ u8 ie_offset;
++#ifdef CONFIG_CONCURRENT_MODE
++ _adapter *pbuddy_adapter = padapter->pbuddy_adapter;
++ struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv;
++#endif // CONFIG_CONCURRENT_MODE
++
++#ifdef CONFIG_WFD
++ struct wifi_display_info* pwfd_info = pwdinfo->wfd_info;
++#endif // CONFIG_WFD
++
++ // Commented by Albert 20110301
++ // The input data contains two informations.
++ // 1. First information is the MAC address which wants to issue the provisioning discovery request frame.
++ // 2. Second information is the WPS configuration method which wants to discovery
++ // Format: 00:E0:4C:00:00:05_display
++ // Format: 00:E0:4C:00:00:05_keypad
++ // Format: 00:E0:4C:00:00:05_pbc
++ // Format: 00:E0:4C:00:00:05_label
++
++ DBG_871X( "[%s] data = %s\n", __FUNCTION__, extra );
++
++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
++ {
++ DBG_871X( "[%s] WiFi Direct is disable!\n", __FUNCTION__ );
++ return ret;
++ }
++ else
++ {
++#ifdef CONFIG_INTEL_WIDI
++ if(check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE){
++ DBG_871X( "[%s] WiFi is under survey!\n", __FUNCTION__ );
++ return ret;
++ }
++#endif //CONFIG_INTEL_WIDI
++
++ // Reset the content of struct tx_provdisc_req_info excluded the wps_config_method_request.
++ _rtw_memset( pwdinfo->tx_prov_disc_info.peerDevAddr, 0x00, ETH_ALEN );
++ _rtw_memset( pwdinfo->tx_prov_disc_info.peerIFAddr, 0x00, ETH_ALEN );
++ _rtw_memset( &pwdinfo->tx_prov_disc_info.ssid, 0x00, sizeof( NDIS_802_11_SSID ) );
++ pwdinfo->tx_prov_disc_info.peer_channel_num[ 0 ] = 0;
++ pwdinfo->tx_prov_disc_info.peer_channel_num[ 1 ] = 0;
++ pwdinfo->tx_prov_disc_info.benable = _FALSE;
++ }
++
++ for( jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3 )
++ {
++ peerMAC[ jj ] = key_2char2num( extra[kk], extra[kk+ 1] );
++ }
++
++ if ( _rtw_memcmp( &extra[ 18 ], "display", 7 ) )
++ {
++ pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_DISPLYA;
++ }
++ else if ( _rtw_memcmp( &extra[ 18 ], "keypad", 7 ) )
++ {
++ pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_KEYPAD;
++ }
++ else if ( _rtw_memcmp( &extra[ 18 ], "pbc", 3 ) )
++ {
++ pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_PUSH_BUTTON;
++ }
++ else if ( _rtw_memcmp( &extra[ 18 ], "label", 5 ) )
++ {
++ pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_LABEL;
++ }
++ else
++ {
++ DBG_871X( "[%s] Unknown WPS config methodn", __FUNCTION__ );
++ return( ret );
++ }
++
++
++ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++
++ phead = get_list_head(queue);
++ plist = get_next(phead);
++
++ while(1)
++ {
++ if (rtw_end_of_queue_search(phead,plist)== _TRUE)
++ break;
++
++ if( uintPeerChannel != 0 )
++ break;
++
++ pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
++
++ // Commented by Albert 2011/05/18
++ // Match the device address located in the P2P IE
++ // This is for the case that the P2P device address is not the same as the P2P interface address.
++
++ if (pnetwork->network.Reserved[0] == 2) { // Probe Request
++ ie_offset = 0;
++ } else { // Beacon or Probe Respones
++ ie_offset = 12;
++ }
++ if ( (p2pie=rtw_get_p2p_ie( &pnetwork->network.IEs[ie_offset], pnetwork->network.IELength - ie_offset, NULL, &p2pielen)) )
++ {
++ while ( p2pie )
++ {
++ // The P2P Device ID attribute is included in the Beacon frame.
++ // The P2P Device Info attribute is included in the probe response frame.
++
++ if ( rtw_get_p2p_attr_content( p2pie, p2pielen, P2P_ATTR_DEVICE_ID, attr_content, &attr_contentlen) )
++ {
++ // Handle the P2P Device ID attribute of Beacon first
++ if ( _rtw_memcmp( attr_content, peerMAC, ETH_ALEN ) )
++ {
++ uintPeerChannel = pnetwork->network.Configuration.DSConfig;
++ break;
++ }
++ }
++ else if ( rtw_get_p2p_attr_content( p2pie, p2pielen, P2P_ATTR_DEVICE_INFO, attr_content, &attr_contentlen) )
++ {
++ // Handle the P2P Device Info attribute of probe response
++ if ( _rtw_memcmp( attr_content, peerMAC, ETH_ALEN ) )
++ {
++ uintPeerChannel = pnetwork->network.Configuration.DSConfig;
++ break;
++ }
++ }
++
++ //Get the next P2P IE
++ p2pie = rtw_get_p2p_ie(p2pie+p2pielen, pnetwork->network.IELength - ie_offset -(p2pie -&pnetwork->network.IEs[ie_offset] + p2pielen), NULL, &p2pielen);
++ }
++ }
++
++#ifdef CONFIG_INTEL_WIDI
++ // Some Intel WiDi source may not provide P2P IE,
++ // so we could only compare mac addr by 802.11 Source Address
++ if( pmlmepriv->widi_state == INTEL_WIDI_STATE_WFD_CONNECTION
++ && uintPeerChannel == 0 )
++ {
++ if ( _rtw_memcmp( pnetwork->network.MacAddress, peerMAC, ETH_ALEN ) )
++ {
++ uintPeerChannel = pnetwork->network.Configuration.DSConfig;
++ break;
++ }
++ }
++#endif //CONFIG_INTEL_WIDI
++
++ plist = get_next(plist);
++
++ }
++
++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++
++ if ( uintPeerChannel )
++ {
++#ifdef CONFIG_WFD
++ {
++ u8 wfd_ie[ 128 ] = { 0x00 };
++ uint wfd_ielen = 0;
++
++ if ( rtw_get_wfd_ie( &pnetwork->network.IEs[12], pnetwork->network.IELength - 12, wfd_ie, &wfd_ielen ) )
++ {
++ u8 wfd_devinfo[ 6 ] = { 0x00 };
++ uint wfd_devlen = 6;
++
++ DBG_871X( "[%s] Found WFD IE!\n", __FUNCTION__ );
++ if ( rtw_get_wfd_attr_content( wfd_ie, wfd_ielen, WFD_ATTR_DEVICE_INFO, wfd_devinfo, &wfd_devlen ) )
++ {
++ u16 wfd_devinfo_field = 0;
++
++ // Commented by Albert 20120319
++ // The first two bytes are the WFD device information field of WFD device information subelement.
++ // In big endian format.
++ wfd_devinfo_field = RTW_GET_BE16(wfd_devinfo);
++ if ( wfd_devinfo_field & WFD_DEVINFO_SESSION_AVAIL )
++ {
++ pwfd_info->peer_session_avail = _TRUE;
++ }
++ else
++ {
++ pwfd_info->peer_session_avail = _FALSE;
++ }
++ }
++ }
++
++ if ( _FALSE == pwfd_info->peer_session_avail )
++ {
++ DBG_871X( "[%s] WFD Session not avaiable!\n", __FUNCTION__ );
++ goto exit;
++ }
++ }
++#endif // CONFIG_WFD
++
++ DBG_871X( "[%s] peer channel: %d!\n", __FUNCTION__, uintPeerChannel );
++#ifdef CONFIG_CONCURRENT_MODE
++ if ( check_buddy_fwstate(padapter, _FW_LINKED ) )
++ {
++ _cancel_timer_ex( &pwdinfo->ap_p2p_switch_timer );
++ }
++#endif // CONFIG_CONCURRENT_MODE
++ _rtw_memcpy( pwdinfo->tx_prov_disc_info.peerIFAddr, pnetwork->network.MacAddress, ETH_ALEN );
++ _rtw_memcpy( pwdinfo->tx_prov_disc_info.peerDevAddr, peerMAC, ETH_ALEN );
++ pwdinfo->tx_prov_disc_info.peer_channel_num[0] = ( u16 ) uintPeerChannel;
++ pwdinfo->tx_prov_disc_info.benable = _TRUE;
++ rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo));
++ rtw_p2p_set_state(pwdinfo, P2P_STATE_TX_PROVISION_DIS_REQ);
++
++ if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT))
++ {
++ _rtw_memcpy( &pwdinfo->tx_prov_disc_info.ssid, &pnetwork->network.Ssid, sizeof( NDIS_802_11_SSID ) );
++ }
++ else if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE) || rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO))
++ {
++ _rtw_memcpy( pwdinfo->tx_prov_disc_info.ssid.Ssid, pwdinfo->p2p_wildcard_ssid, P2P_WILDCARD_SSID_LEN );
++ pwdinfo->tx_prov_disc_info.ssid.SsidLength= P2P_WILDCARD_SSID_LEN;
++ }
++
++#ifdef CONFIG_CONCURRENT_MODE
++ if ( check_buddy_fwstate(padapter, _FW_LINKED ) )
++ {
++ // Have to enter the power saving with the AP
++ set_channel_bwmode(padapter, pbuddy_mlmeext->cur_channel, pbuddy_mlmeext->cur_ch_offset, pbuddy_mlmeext->cur_bwmode);
++
++ issue_nulldata(pbuddy_adapter, NULL, 1, 3, 500);
++ }
++ else
++ {
++ set_channel_bwmode(padapter, uintPeerChannel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HT_CHANNEL_WIDTH_20);
++ }
++#else
++ set_channel_bwmode(padapter, uintPeerChannel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HT_CHANNEL_WIDTH_20);
++#endif
++
++ _set_timer( &pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT );
++
++#ifdef CONFIG_CONCURRENT_MODE
++ if ( check_buddy_fwstate(padapter, _FW_LINKED ) )
++ {
++ _set_timer( &pwdinfo->restore_p2p_state_timer, P2P_CONCURRENT_PROVISION_TIMEOUT );
++ }
++ else
++ {
++ _set_timer( &pwdinfo->restore_p2p_state_timer, P2P_PROVISION_TIMEOUT );
++ }
++#else
++ _set_timer( &pwdinfo->restore_p2p_state_timer, P2P_PROVISION_TIMEOUT );
++#endif // CONFIG_CONCURRENT_MODE
++
++
++ }
++ else
++ {
++ DBG_871X( "[%s] NOT Found in the Scanning Queue!\n", __FUNCTION__ );
++#ifdef CONFIG_INTEL_WIDI
++ rtw_p2p_set_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH);
++ rtw_p2p_findphase_ex_set(pwdinfo, P2P_FINDPHASE_EX_NONE);
++ rtw_free_network_queue(padapter, _TRUE);
++ _enter_critical_bh(&pmlmepriv->lock, &irqL);
++ rtw_sitesurvey_cmd(padapter, NULL, 0, NULL, 0);
++ _exit_critical_bh(&pmlmepriv->lock, &irqL);
++#endif //CONFIG_INTEL_WIDI
++ }
++exit:
++
++ return ret;
++
++}
++
++// Added by Albert 20110328
++// This function is used to inform the driver the user had specified the pin code value or pbc
++// to application.
++
++static int rtw_p2p_got_wpsinfo(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++
++ int ret = 0;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo );
++
++
++ DBG_871X( "[%s] data = %s\n", __FUNCTION__, extra );
++ // Added by Albert 20110328
++ // if the input data is P2P_NO_WPSINFO -> reset the wpsinfo
++ // if the input data is P2P_GOT_WPSINFO_PEER_DISPLAY_PIN -> the utility just input the PIN code got from the peer P2P device.
++ // if the input data is P2P_GOT_WPSINFO_SELF_DISPLAY_PIN -> the utility just got the PIN code from itself.
++ // if the input data is P2P_GOT_WPSINFO_PBC -> the utility just determine to use the PBC
++
++ if ( *extra == '0' )
++ {
++ pwdinfo->ui_got_wps_info = P2P_NO_WPSINFO;
++ }
++ else if ( *extra == '1' )
++ {
++ pwdinfo->ui_got_wps_info = P2P_GOT_WPSINFO_PEER_DISPLAY_PIN;
++ }
++ else if ( *extra == '2' )
++ {
++ pwdinfo->ui_got_wps_info = P2P_GOT_WPSINFO_SELF_DISPLAY_PIN;
++ }
++ else if ( *extra == '3' )
++ {
++ pwdinfo->ui_got_wps_info = P2P_GOT_WPSINFO_PBC;
++ }
++ else
++ {
++ pwdinfo->ui_got_wps_info = P2P_NO_WPSINFO;
++ }
++
++ return ret;
++
++}
++
++#endif //CONFIG_P2P
++
++static int rtw_p2p_set(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++
++ int ret = 0;
++#ifdef CONFIG_P2P
++
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ struct iw_point *pdata = &wrqu->data;
++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo);
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++
++ DBG_871X( "[%s] extra = %s\n", __FUNCTION__, extra );
++
++ if ( _rtw_memcmp( extra, "enable=", 7 ) )
++ {
++ rtw_wext_p2p_enable( dev, info, wrqu, &extra[7] );
++ }
++ else if ( _rtw_memcmp( extra, "setDN=", 6 ) )
++ {
++ wrqu->data.length -= 6;
++ rtw_p2p_setDN( dev, info, wrqu, &extra[6] );
++ }
++ else if ( _rtw_memcmp( extra, "profilefound=", 13 ) )
++ {
++ wrqu->data.length -= 13;
++ rtw_p2p_profilefound( dev, info, wrqu, &extra[13] );
++ }
++ else if ( _rtw_memcmp( extra, "prov_disc=", 10 ) )
++ {
++ wrqu->data.length -= 10;
++ rtw_p2p_prov_disc( dev, info, wrqu, &extra[10] );
++ }
++ else if ( _rtw_memcmp( extra, "nego=", 5 ) )
++ {
++ wrqu->data.length -= 5;
++ rtw_p2p_connect( dev, info, wrqu, &extra[5] );
++ }
++ else if ( _rtw_memcmp( extra, "intent=", 7 ) )
++ {
++ // Commented by Albert 2011/03/23
++ // The wrqu->data.length will include the null character
++ // So, we will decrease 7 + 1
++ wrqu->data.length -= 8;
++ rtw_p2p_set_intent( dev, info, wrqu, &extra[7] );
++ }
++ else if ( _rtw_memcmp( extra, "ssid=", 5 ) )
++ {
++ wrqu->data.length -= 5;
++ rtw_p2p_set_go_nego_ssid( dev, info, wrqu, &extra[5] );
++ }
++ else if ( _rtw_memcmp( extra, "got_wpsinfo=", 12 ) )
++ {
++ wrqu->data.length -= 12;
++ rtw_p2p_got_wpsinfo( dev, info, wrqu, &extra[12] );
++ }
++ else if ( _rtw_memcmp( extra, "listen_ch=", 10 ) )
++ {
++ // Commented by Albert 2011/05/24
++ // The wrqu->data.length will include the null character
++ // So, we will decrease (10 + 1)
++ wrqu->data.length -= 11;
++ rtw_p2p_set_listen_ch( dev, info, wrqu, &extra[10] );
++ }
++ else if ( _rtw_memcmp( extra, "op_ch=", 6 ) )
++ {
++ // Commented by Albert 2011/05/24
++ // The wrqu->data.length will include the null character
++ // So, we will decrease (6 + 1)
++ wrqu->data.length -= 7;
++ rtw_p2p_set_op_ch( dev, info, wrqu, &extra[6] );
++ }
++ else if ( _rtw_memcmp( extra, "invite=", 7 ) )
++ {
++ wrqu->data.length -= 8;
++ rtw_p2p_invite_req( dev, info, wrqu, &extra[7] );
++ }
++ else if ( _rtw_memcmp( extra, "persistent=", 11 ) )
++ {
++ wrqu->data.length -= 11;
++ rtw_p2p_set_persistent( dev, info, wrqu, &extra[11] );
++ }
++ else if ( _rtw_memcmp ( extra, "uuid=", 5) )
++ {
++ wrqu->data.length -= 5;
++ ret = rtw_p2p_set_wps_uuid( dev, info, wrqu, &extra[5] );
++ }
++#ifdef CONFIG_WFD
++ else if ( _rtw_memcmp( extra, "sa=", 3 ) )
++ {
++ // sa: WFD Session Available information
++ wrqu->data.length -= 3;
++ rtw_p2p_set_sa( dev, info, wrqu, &extra[3] );
++ }
++ else if ( _rtw_memcmp( extra, "pc=", 3 ) )
++ {
++ // pc: WFD Preferred Connection
++ wrqu->data.length -= 3;
++ rtw_p2p_set_pc( dev, info, wrqu, &extra[3] );
++ }
++ else if ( _rtw_memcmp( extra, "wfd_type=", 9 ) )
++ {
++ // Specify this device is Mircast source or sink
++ wrqu->data.length -= 9;
++ rtw_p2p_set_wfd_device_type( dev, info, wrqu, &extra[9] );
++ }
++ else if ( _rtw_memcmp( extra, "scan_type=", 10 ) )
++ {
++ wrqu->data.length -= 10;
++ rtw_p2p_set_scan_result_type( dev, info, wrqu, &extra[10] );
++ }
++ else if ( _rtw_memcmp( extra, "wfd_enable=", 11 ) )
++ {
++ wrqu->data.length -= 11;
++ rtw_p2p_set_wfd_enable( dev, info, wrqu, &extra[11] );
++ }
++ else if ( _rtw_memcmp( extra, "driver_iface=", 13 ) )
++ {
++ wrqu->data.length -= 13;
++ rtw_p2p_set_driver_iface( dev, info, wrqu, &extra[13] );
++ }
++#endif //CONFIG_WFD
++#endif //CONFIG_P2P
++
++ return ret;
++
++}
++
++static int rtw_p2p_get(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++
++ int ret = 0;
++
++#ifdef CONFIG_P2P
++
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ struct iw_point *pdata = &wrqu->data;
++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo);
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++
++ if ( padapter->bShowGetP2PState )
++ {
++ DBG_871X( "[%s] extra = %s\n", __FUNCTION__, (char*) wrqu->data.pointer );
++ }
++
++ if ( _rtw_memcmp( wrqu->data.pointer, "status", 6 ) )
++ {
++ rtw_p2p_get_status( dev, info, wrqu, extra );
++ }
++ else if ( _rtw_memcmp( wrqu->data.pointer, "role", 4 ) )
++ {
++ rtw_p2p_get_role( dev, info, wrqu, extra);
++ }
++ else if ( _rtw_memcmp( wrqu->data.pointer, "peer_ifa", 8 ) )
++ {
++ rtw_p2p_get_peer_ifaddr( dev, info, wrqu, extra);
++ }
++ else if ( _rtw_memcmp( wrqu->data.pointer, "req_cm", 6 ) )
++ {
++ rtw_p2p_get_req_cm( dev, info, wrqu, extra);
++ }
++ else if ( _rtw_memcmp( wrqu->data.pointer, "peer_deva", 9 ) )
++ {
++ // Get the P2P device address when receiving the provision discovery request frame.
++ rtw_p2p_get_peer_devaddr( dev, info, wrqu, extra);
++ }
++ else if ( _rtw_memcmp( wrqu->data.pointer, "group_id", 8 ) )
++ {
++ rtw_p2p_get_groupid( dev, info, wrqu, extra);
++ }
++ else if ( _rtw_memcmp( wrqu->data.pointer, "inv_peer_deva", 13 ) )
++ {
++ // Get the P2P device address when receiving the P2P Invitation request frame.
++ rtw_p2p_get_peer_devaddr_by_invitation( dev, info, wrqu, extra);
++ }
++ else if ( _rtw_memcmp( wrqu->data.pointer, "op_ch", 5 ) )
++ {
++ rtw_p2p_get_op_ch( dev, info, wrqu, extra);
++ }
++#ifdef CONFIG_WFD
++ else if ( _rtw_memcmp( wrqu->data.pointer, "peer_port", 9 ) )
++ {
++ rtw_p2p_get_peer_wfd_port( dev, info, wrqu, extra );
++ }
++ else if ( _rtw_memcmp( wrqu->data.pointer, "wfd_sa", 6 ) )
++ {
++ rtw_p2p_get_peer_wfd_session_available( dev, info, wrqu, extra );
++ }
++ else if ( _rtw_memcmp( wrqu->data.pointer, "wfd_pc", 6 ) )
++ {
++ rtw_p2p_get_peer_wfd_preferred_connection( dev, info, wrqu, extra );
++ }
++#endif // CONFIG_WFD
++
++#endif //CONFIG_P2P
++
++ return ret;
++
++}
++
++static int rtw_p2p_get2(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++
++ int ret = 0;
++
++#ifdef CONFIG_P2P
++
++ int length = wrqu->data.length;
++ char *buffer = (u8 *)rtw_malloc(length);
++
++ if (buffer == NULL)
++ {
++ ret = -ENOMEM;
++ goto bad;
++ }
++
++ if (copy_from_user(buffer, wrqu->data.pointer, wrqu->data.length))
++ {
++ ret - EFAULT;
++ goto bad;
++ }
++
++ DBG_871X("[%s] buffer = %s\n", __FUNCTION__, buffer);
++
++ if (_rtw_memcmp(buffer, "wpsCM=", 6))
++ {
++ ret = rtw_p2p_get_wps_configmethod(dev, info, wrqu, extra, &buffer[6]);
++ } else if (_rtw_memcmp(buffer, "devN=", 5))
++ {
++ ret = rtw_p2p_get_device_name(dev, info, wrqu, extra, &buffer[5]);
++ } else if (_rtw_memcmp(buffer, "dev_type=", 9))
++ {
++ ret = rtw_p2p_get_device_type(dev, info, wrqu, extra, &buffer[9]);
++ } else if (_rtw_memcmp(buffer, "go_devadd=", 10))
++ {
++ ret = rtw_p2p_get_go_device_address(dev, info, wrqu, extra, &buffer[10]);
++ } else if (_rtw_memcmp(buffer, "InvProc=", 8))
++ {
++ ret = rtw_p2p_get_invitation_procedure(dev, info, wrqu, extra, &buffer[8]);
++ } else
++ {
++ snprintf(extra, sizeof("Command not found."), "Command not found.");
++ wrqu->data.length = strlen(extra);
++ }
++
++bad:
++ if (buffer)
++ {
++ rtw_mfree(buffer, length);
++ }
++
++#endif //CONFIG_P2P
++
++ return ret;
++
++}
++
++extern int rtw_change_ifname(_adapter *padapter, const char *ifname);
++static int rtw_rereg_nd_name(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++ int ret = 0;
++ _adapter *padapter = rtw_netdev_priv(dev);
++ struct rereg_nd_name_data *rereg_priv = &padapter->rereg_nd_name_priv;
++ char new_ifname[IFNAMSIZ];
++
++ if(rereg_priv->old_ifname[0] == 0) {
++ char *reg_ifname;
++#ifdef CONFIG_CONCURRENT_MODE
++ if (padapter->isprimary)
++ reg_ifname = padapter->registrypriv.ifname;
++ else
++#endif
++ reg_ifname = padapter->registrypriv.if2name;
++
++ strncpy(rereg_priv->old_ifname, reg_ifname, IFNAMSIZ);
++ rereg_priv->old_ifname[IFNAMSIZ-1] = 0;
++ }
++
++ //DBG_871X("%s wrqu->data.length:%d\n", __FUNCTION__, wrqu->data.length);
++ if(wrqu->data.length > IFNAMSIZ)
++ return -EFAULT;
++
++ if ( copy_from_user(new_ifname, wrqu->data.pointer, IFNAMSIZ) ) {
++ return -EFAULT;
++ }
++
++ if( 0 == strcmp(rereg_priv->old_ifname, new_ifname) ) {
++ return ret;
++ }
++
++ DBG_871X("%s new_ifname:%s\n", __FUNCTION__, new_ifname);
++ if( 0 != (ret = rtw_change_ifname(padapter, new_ifname)) ) {
++ goto exit;
++ }
++
++ if(_rtw_memcmp(rereg_priv->old_ifname, "disable%d", 9) == _TRUE) {
++ padapter->ledpriv.bRegUseLed= rereg_priv->old_bRegUseLed;
++ rtw_hal_sw_led_init(padapter);
++ rtw_ips_mode_req(&padapter->pwrctrlpriv, rereg_priv->old_ips_mode);
++ }
++
++ strncpy(rereg_priv->old_ifname, new_ifname, IFNAMSIZ);
++ rereg_priv->old_ifname[IFNAMSIZ-1] = 0;
++
++ if(_rtw_memcmp(new_ifname, "disable%d", 9) == _TRUE) {
++
++ DBG_871X("%s disable\n", __FUNCTION__);
++ // free network queue for Android's timming issue
++ rtw_free_network_queue(padapter, _TRUE);
++
++ // close led
++ rtw_led_control(padapter, LED_CTL_POWER_OFF);
++ rereg_priv->old_bRegUseLed = padapter->ledpriv.bRegUseLed;
++ padapter->ledpriv.bRegUseLed= _FALSE;
++ rtw_hal_sw_led_deinit(padapter);
++
++ // the interface is being "disabled", we can do deeper IPS
++ rereg_priv->old_ips_mode = rtw_get_ips_mode_req(&padapter->pwrctrlpriv);
++ rtw_ips_mode_req(&padapter->pwrctrlpriv, IPS_NORMAL);
++ }
++exit:
++ return ret;
++
++}
++
++#if 0
++void mac_reg_dump(_adapter *padapter)
++{
++ int i,j=1;
++ DBG_871X("\n======= MAC REG =======\n");
++ for(i=0x0;i<0x300;i+=4)
++ {
++ if(j%4==1) DBG_871X("0x%02x",i);
++ DBG_871X(" 0x%08x ",rtw_read32(padapter,i));
++ if((j++)%4 == 0) DBG_871X("\n");
++ }
++ for(i=0x400;i<0x800;i+=4)
++ {
++ if(j%4==1) DBG_871X("0x%02x",i);
++ DBG_871X(" 0x%08x ",rtw_read32(padapter,i));
++ if((j++)%4 == 0) DBG_871X("\n");
++ }
++}
++void bb_reg_dump(_adapter *padapter)
++{
++ int i,j=1;
++ DBG_871X("\n======= BB REG =======\n");
++ for(i=0x800;i<0x1000;i+=4)
++ {
++ if(j%4==1) DBG_871X("0x%02x",i);
++
++ DBG_871X(" 0x%08x ",rtw_read32(padapter,i));
++ if((j++)%4 == 0) DBG_871X("\n");
++ }
++}
++void rf_reg_dump(_adapter *padapter)
++{
++ int i,j=1,path;
++ u32 value;
++ DBG_871X("\n======= RF REG =======\n");
++ for(path=0;path<2;path++)
++ {
++ DBG_871X("\nRF_Path(%x)\n",path);
++ for(i=0;i<0x100;i++)
++ {
++ value = PHY_QueryRFReg(padapter, (RF90_RADIO_PATH_E)path,i, bMaskDWord);
++ if(j%4==1) DBG_871X("0x%02x ",i);
++ DBG_871X(" 0x%08x ",value);
++ if((j++)%4==0) DBG_871X("\n");
++ }
++ }
++}
++
++#endif
++
++void mac_reg_dump(_adapter *padapter)
++{
++ int i,j=1;
++ DBG_871X("\n======= MAC REG =======\n");
++ for(i=0x0;i<0x300;i+=4)
++ {
++ if(j%4==1) DBG_871X("0x%02x",i);
++ DBG_871X(" 0x%08x ",rtw_read32(padapter,i));
++ if((j++)%4 == 0) DBG_871X("\n");
++ }
++ for(i=0x400;i<0x800;i+=4)
++ {
++ if(j%4==1) DBG_871X("0x%02x",i);
++ DBG_871X(" 0x%08x ",rtw_read32(padapter,i));
++ if((j++)%4 == 0) DBG_871X("\n");
++ }
++}
++void bb_reg_dump(_adapter *padapter)
++{
++ int i,j=1;
++ DBG_871X("\n======= BB REG =======\n");
++ for(i=0x800;i<0x1000;i+=4)
++ {
++ if(j%4==1) DBG_871X("0x%02x",i);
++
++ DBG_871X(" 0x%08x ",rtw_read32(padapter,i));
++ if((j++)%4 == 0) DBG_871X("\n");
++ }
++}
++void rf_reg_dump(_adapter *padapter)
++{
++ int i,j=1,path;
++ u32 value;
++ u8 rf_type,path_nums = 0;
++ rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));
++
++ DBG_871X("\n======= RF REG =======\n");
++ if((RF_1T2R == rf_type) ||(RF_1T1R ==rf_type ))
++ path_nums = 1;
++ else
++ path_nums = 2;
++
++ for(path=0;path<path_nums;path++)
++ {
++ DBG_871X("\nRF_Path(%x)\n",path);
++ for(i=0;i<0x100;i++)
++ {
++ //value = PHY_QueryRFReg(padapter, (RF90_RADIO_PATH_E)path,i, bMaskDWord);
++ value =rtw_hal_read_rfreg(padapter, path, i, 0xffffffff);
++ if(j%4==1) DBG_871X("0x%02x ",i);
++ DBG_871X(" 0x%08x ",value);
++ if((j++)%4==0) DBG_871X("\n");
++ }
++ }
++}
++
++#ifdef CONFIG_IOL
++#include <rtw_iol.h>
++#endif
++#ifdef DBG_CONFIG_ERROR_DETECT
++#include <rtw_sreset.h>
++#endif
++static int rtw_dbg_port(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++ _irqL irqL;
++ int ret = 0;
++ u8 major_cmd, minor_cmd;
++ u16 arg;
++ u32 extra_arg, *pdata, val32;
++ struct sta_info *psta;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ struct security_priv *psecuritypriv = &padapter->securitypriv;
++ struct wlan_network *cur_network = &(pmlmepriv->cur_network);
++ struct sta_priv *pstapriv = &padapter->stapriv;
++
++
++ pdata = (u32*)&wrqu->data;
++
++ val32 = *pdata;
++ arg = (u16)(val32&0x0000ffff);
++ major_cmd = (u8)(val32>>24);
++ minor_cmd = (u8)((val32>>16)&0x00ff);
++
++ extra_arg = *(pdata+1);
++
++ switch(major_cmd)
++ {
++ case 0x70://read_reg
++ switch(minor_cmd)
++ {
++ case 1:
++ DBG_871X("rtw_read8(0x%x)=0x%02x\n", arg, rtw_read8(padapter, arg));
++ break;
++ case 2:
++ DBG_871X("rtw_read16(0x%x)=0x%04x\n", arg, rtw_read16(padapter, arg));
++ break;
++ case 4:
++ DBG_871X("rtw_read32(0x%x)=0x%08x\n", arg, rtw_read32(padapter, arg));
++ break;
++ }
++ break;
++ case 0x71://write_reg
++ switch(minor_cmd)
++ {
++ case 1:
++ rtw_write8(padapter, arg, extra_arg);
++ DBG_871X("rtw_write8(0x%x)=0x%02x\n", arg, rtw_read8(padapter, arg));
++ break;
++ case 2:
++ rtw_write16(padapter, arg, extra_arg);
++ DBG_871X("rtw_write16(0x%x)=0x%04x\n", arg, rtw_read16(padapter, arg));
++ break;
++ case 4:
++ rtw_write32(padapter, arg, extra_arg);
++ DBG_871X("rtw_write32(0x%x)=0x%08x\n", arg, rtw_read32(padapter, arg));
++ break;
++ }
++ break;
++ case 0x72://read_bb
++ DBG_871X("read_bbreg(0x%x)=0x%x\n", arg, rtw_hal_read_bbreg(padapter, arg, 0xffffffff));
++ break;
++ case 0x73://write_bb
++ rtw_hal_write_bbreg(padapter, arg, 0xffffffff, extra_arg);
++ DBG_871X("write_bbreg(0x%x)=0x%x\n", arg, rtw_hal_read_bbreg(padapter, arg, 0xffffffff));
++ break;
++ case 0x74://read_rf
++ DBG_871X("read RF_reg path(0x%02x),offset(0x%x),value(0x%08x)\n",minor_cmd,arg,rtw_hal_read_rfreg(padapter, minor_cmd, arg, 0xffffffff));
++ break;
++ case 0x75://write_rf
++ rtw_hal_write_rfreg(padapter, minor_cmd, arg, 0xffffffff, extra_arg);
++ DBG_871X("write RF_reg path(0x%02x),offset(0x%x),value(0x%08x)\n",minor_cmd,arg, rtw_hal_read_rfreg(padapter, minor_cmd, arg, 0xffffffff));
++ break;
++
++ case 0x76:
++ switch(minor_cmd)
++ {
++ case 0x00: //normal mode,
++ padapter->recvpriv.is_signal_dbg = 0;
++ break;
++ case 0x01: //dbg mode
++ padapter->recvpriv.is_signal_dbg = 1;
++ extra_arg = extra_arg>100?100:extra_arg;
++ extra_arg = extra_arg<0?0:extra_arg;
++ padapter->recvpriv.signal_strength_dbg=extra_arg;
++ break;
++ }
++ break;
++ case 0x78: //IOL test
++ switch(minor_cmd)
++ {
++ #ifdef CONFIG_IOL
++ case 0x04: //LLT table initialization test
++ {
++ u8 page_boundary = 0xf9;
++ {
++ struct xmit_frame *xmit_frame;
++
++ if((xmit_frame=rtw_IOL_accquire_xmit_frame(padapter)) == NULL) {
++ ret = -ENOMEM;
++ break;
++ }
++
++ rtw_IOL_append_LLT_cmd(xmit_frame, page_boundary);
++
++
++ if(_SUCCESS != rtw_IOL_exec_cmds_sync(padapter, xmit_frame, 500) )
++ ret = -EPERM;
++ }
++ }
++ break;
++ case 0x05: //blink LED test
++ {
++ u16 reg = 0x4c;
++ u32 blink_num = 50;
++ u32 blink_delay_ms = 200;
++ int i;
++
++ {
++ struct xmit_frame *xmit_frame;
++
++ if((xmit_frame=rtw_IOL_accquire_xmit_frame(padapter)) == NULL) {
++ ret = -ENOMEM;
++ break;
++ }
++
++ for(i=0;i<blink_num;i++){
++ rtw_IOL_append_WB_cmd(xmit_frame, reg, 0x00);
++ rtw_IOL_append_DELAY_MS_cmd(xmit_frame, blink_delay_ms);
++ rtw_IOL_append_WB_cmd(xmit_frame, reg, 0x08);
++ rtw_IOL_append_DELAY_MS_cmd(xmit_frame, blink_delay_ms);
++ }
++ if(_SUCCESS != rtw_IOL_exec_cmds_sync(padapter, xmit_frame, (blink_delay_ms*blink_num*2)+200) )
++ ret = -EPERM;
++ }
++ }
++ break;
++
++ case 0x06: //continuous wirte byte test
++ {
++ u16 reg = arg;
++ u16 start_value = 0;
++ u32 write_num = extra_arg;
++ int i;
++ u8 final;
++
++ {
++ struct xmit_frame *xmit_frame;
++
++ if((xmit_frame=rtw_IOL_accquire_xmit_frame(padapter)) == NULL) {
++ ret = -ENOMEM;
++ break;
++ }
++
++ for(i=0;i<write_num;i++){
++ rtw_IOL_append_WB_cmd(xmit_frame, reg, i+start_value);
++ }
++ if(_SUCCESS != rtw_IOL_exec_cmds_sync(padapter, xmit_frame, 5000))
++ ret = -EPERM;
++ }
++
++ if(start_value+write_num-1 == (final=rtw_read8(padapter, reg)) ) {
++ DBG_871X("continuous IOL_CMD_WB_REG to 0x%x %u times Success, start:%u, final:%u\n", reg, write_num, start_value, final);
++ } else {
++ DBG_871X("continuous IOL_CMD_WB_REG to 0x%x %u times Fail, start:%u, final:%u\n", reg, write_num, start_value, final);
++ }
++ }
++ break;
++
++ case 0x07: //continuous wirte word test
++ {
++ u16 reg = arg;
++ u16 start_value = 200;
++ u32 write_num = extra_arg;
++
++ int i;
++ u16 final;
++
++ {
++ struct xmit_frame *xmit_frame;
++
++ if((xmit_frame=rtw_IOL_accquire_xmit_frame(padapter)) == NULL) {
++ ret = -ENOMEM;
++ break;
++ }
++
++ for(i=0;i<write_num;i++){
++ rtw_IOL_append_WW_cmd(xmit_frame, reg, i+start_value);
++ }
++ if(_SUCCESS !=rtw_IOL_exec_cmds_sync(padapter, xmit_frame, 5000))
++ ret = -EPERM;
++ }
++
++ if(start_value+write_num-1 == (final=rtw_read16(padapter, reg)) ) {
++ DBG_871X("continuous IOL_CMD_WW_REG to 0x%x %u times Success, start:%u, final:%u\n", reg, write_num, start_value, final);
++ } else {
++ DBG_871X("continuous IOL_CMD_WW_REG to 0x%x %u times Fail, start:%u, final:%u\n", reg, write_num, start_value, final);
++ }
++ }
++ break;
++
++ case 0x08: //continuous wirte dword test
++ {
++ u16 reg = arg;
++ u32 start_value = 0x110000c7;
++ u32 write_num = extra_arg;
++
++ int i;
++ u32 final;
++
++ {
++ struct xmit_frame *xmit_frame;
++
++ if((xmit_frame=rtw_IOL_accquire_xmit_frame(padapter)) == NULL) {
++ ret = -ENOMEM;
++ break;
++ }
++
++ for(i=0;i<write_num;i++){
++ rtw_IOL_append_WD_cmd(xmit_frame, reg, i+start_value);
++ }
++ if(_SUCCESS !=rtw_IOL_exec_cmds_sync(padapter, xmit_frame, 5000))
++ ret = -EPERM;
++
++ }
++
++ if(start_value+write_num-1 == (final=rtw_read32(padapter, reg)) ) {
++ DBG_871X("continuous IOL_CMD_WD_REG to 0x%x %u times Success, start:%u, final:%u\n", reg, write_num, start_value, final);
++ } else {
++ DBG_871X("continuous IOL_CMD_WD_REG to 0x%x %u times Fail, start:%u, final:%u\n", reg, write_num, start_value, final);
++ }
++ }
++ break;
++ #endif //CONFIG_IOL
++ }
++ break;
++ case 0x7a:
++ receive_disconnect(padapter, pmlmeinfo->network.MacAddress
++ , WLAN_REASON_EXPIRATION_CHK);
++ break;
++
++ case 0x7F:
++ switch(minor_cmd)
++ {
++ case 0x0:
++ DBG_871X("fwstate=0x%x\n", get_fwstate(pmlmepriv));
++ break;
++ case 0x01:
++ DBG_871X("auth_alg=0x%x, enc_alg=0x%x, auth_type=0x%x, enc_type=0x%x\n",
++ psecuritypriv->dot11AuthAlgrthm, psecuritypriv->dot11PrivacyAlgrthm,
++ psecuritypriv->ndisauthtype, psecuritypriv->ndisencryptstatus);
++ break;
++ case 0x02:
++ DBG_871X("pmlmeinfo->state=0x%x\n", pmlmeinfo->state);
++ break;
++ case 0x03:
++ DBG_871X("qos_option=%d\n", pmlmepriv->qospriv.qos_option);
++ DBG_871X("ht_option=%d\n", pmlmepriv->htpriv.ht_option);
++ break;
++ case 0x04:
++ DBG_871X("cur_ch=%d\n", pmlmeext->cur_channel);
++ DBG_871X("cur_bw=%d\n", pmlmeext->cur_bwmode);
++ DBG_871X("cur_ch_off=%d\n", pmlmeext->cur_ch_offset);
++ break;
++ case 0x05:
++ psta = rtw_get_stainfo(pstapriv, cur_network->network.MacAddress);
++ if(psta)
++ {
++ int i;
++ struct recv_reorder_ctrl *preorder_ctrl;
++
++ DBG_871X("SSID=%s\n", cur_network->network.Ssid.Ssid);
++ DBG_871X("sta's macaddr:" MAC_FMT "\n", MAC_ARG(psta->hwaddr));
++ DBG_871X("cur_channel=%d, cur_bwmode=%d, cur_ch_offset=%d\n", pmlmeext->cur_channel, pmlmeext->cur_bwmode, pmlmeext->cur_ch_offset);
++ DBG_871X("rtsen=%d, cts2slef=%d\n", psta->rtsen, psta->cts2self);
++ DBG_871X("qos_en=%d, ht_en=%d, init_rate=%d\n", psta->qos_option, psta->htpriv.ht_option, psta->init_rate);
++ DBG_871X("state=0x%x, aid=%d, macid=%d, raid=%d\n", psta->state, psta->aid, psta->mac_id, psta->raid);
++ DBG_871X("bwmode=%d, ch_offset=%d, sgi=%d\n", psta->htpriv.bwmode, psta->htpriv.ch_offset, psta->htpriv.sgi);
++ DBG_871X("ampdu_enable = %d\n", psta->htpriv.ampdu_enable);
++ DBG_871X("agg_enable_bitmap=%x, candidate_tid_bitmap=%x\n", psta->htpriv.agg_enable_bitmap, psta->htpriv.candidate_tid_bitmap);
++
++ for(i=0;i<16;i++)
++ {
++ preorder_ctrl = &psta->recvreorder_ctrl[i];
++ if(preorder_ctrl->enable)
++ {
++ DBG_871X("tid=%d, indicate_seq=%d\n", i, preorder_ctrl->indicate_seq);
++ }
++ }
++
++ }
++ else
++ {
++ DBG_871X("can't get sta's macaddr, cur_network's macaddr:" MAC_FMT "\n", MAC_ARG(cur_network->network.MacAddress));
++ }
++ break;
++ case 0x06:
++ {
++ u8 DMFlag;
++ rtw_hal_get_hwreg(padapter, HW_VAR_DM_FLAG, (u8 *)(&DMFlag));
++ DBG_871X("(B)DMFlag=0x%x, arg=0x%x\n", DMFlag, arg);
++ DMFlag = (u8)(0x0f&arg);
++ DBG_871X("(A)DMFlag=0x%x\n", DMFlag);
++ rtw_hal_set_hwreg(padapter, HW_VAR_DM_FLAG, (u8 *)(&DMFlag));
++ }
++ break;
++ case 0x07:
++ DBG_871X("bSurpriseRemoved=%d, bDriverStopped=%d\n",
++ padapter->bSurpriseRemoved, padapter->bDriverStopped);
++ break;
++ case 0x08:
++ {
++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++ struct recv_priv *precvpriv = &padapter->recvpriv;
++
++ DBG_871X("free_xmitbuf_cnt=%d, free_xmitframe_cnt=%d"
++ ", free_xmit_extbuf_cnt=%d, free_xframe_ext_cnt=%d"
++ ", free_recvframe_cnt=%d\n",
++ pxmitpriv->free_xmitbuf_cnt, pxmitpriv->free_xmitframe_cnt,
++ pxmitpriv->free_xmit_extbuf_cnt, pxmitpriv->free_xframe_ext_cnt,
++ precvpriv->free_recvframe_cnt);
++ #ifdef CONFIG_USB_HCI
++ DBG_871X("rx_urb_pending_cn=%d\n", precvpriv->rx_pending_cnt);
++ #endif
++ }
++ break;
++ case 0x09:
++ {
++ int i, j;
++ _list *plist, *phead;
++ struct recv_reorder_ctrl *preorder_ctrl;
++
++#ifdef CONFIG_AP_MODE
++ DBG_871X("sta_dz_bitmap=0x%x, tim_bitmap=0x%x\n", pstapriv->sta_dz_bitmap, pstapriv->tim_bitmap);
++#endif
++ _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
++
++ for(i=0; i< NUM_STA; i++)
++ {
++ phead = &(pstapriv->sta_hash[i]);
++ plist = get_next(phead);
++
++ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE)
++ {
++ psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
++
++ plist = get_next(plist);
++
++ if(extra_arg == psta->aid)
++ {
++ DBG_871X("sta's macaddr:" MAC_FMT "\n", MAC_ARG(psta->hwaddr));
++ DBG_871X("rtsen=%d, cts2slef=%d\n", psta->rtsen, psta->cts2self);
++ DBG_871X("qos_en=%d, ht_en=%d, init_rate=%d\n", psta->qos_option, psta->htpriv.ht_option, psta->init_rate);
++ DBG_871X("state=0x%x, aid=%d, macid=%d, raid=%d\n", psta->state, psta->aid, psta->mac_id, psta->raid);
++ DBG_871X("bwmode=%d, ch_offset=%d, sgi=%d\n", psta->htpriv.bwmode, psta->htpriv.ch_offset, psta->htpriv.sgi);
++ DBG_871X("ampdu_enable = %d\n", psta->htpriv.ampdu_enable);
++ DBG_871X("agg_enable_bitmap=%x, candidate_tid_bitmap=%x\n", psta->htpriv.agg_enable_bitmap, psta->htpriv.candidate_tid_bitmap);
++#ifdef CONFIG_AP_MODE
++ DBG_871X("capability=0x%x\n", psta->capability);
++ DBG_871X("flags=0x%x\n", psta->flags);
++ DBG_871X("wpa_psk=0x%x\n", psta->wpa_psk);
++ DBG_871X("wpa2_group_cipher=0x%x\n", psta->wpa2_group_cipher);
++ DBG_871X("wpa2_pairwise_cipher=0x%x\n", psta->wpa2_pairwise_cipher);
++ DBG_871X("qos_info=0x%x\n", psta->qos_info);
++#endif
++ DBG_871X("dot118021XPrivacy=0x%x\n", psta->dot118021XPrivacy);
++
++
++
++ for(j=0;j<16;j++)
++ {
++ preorder_ctrl = &psta->recvreorder_ctrl[j];
++ if(preorder_ctrl->enable)
++ {
++ DBG_871X("tid=%d, indicate_seq=%d\n", j, preorder_ctrl->indicate_seq);
++ }
++ }
++
++ }
++
++ }
++ }
++
++ _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
++
++ }
++ break;
++
++ case 0x0c://dump rx packet
++ {
++ DBG_871X("dump rx packet (%d)\n",extra_arg);
++ //pHalData->bDumpRxPkt =extra_arg;
++ rtw_hal_set_def_var(padapter, HAL_DEF_DBG_DUMP_RXPKT, &(extra_arg));
++ }
++ break;
++#if 0
++ case 0x0d://dump cam
++ {
++ //u8 entry = (u8) extra_arg;
++ u8 entry=0;
++ //dump cam
++ for(entry=0;entry<32;entry++)
++ read_cam(padapter,entry);
++ }
++ break;
++#endif
++ #ifdef DBG_CONFIG_ERROR_DETECT
++ case 0x0f:
++ {
++ if(extra_arg == 0){
++ DBG_871X("###### silent reset test.......#####\n");
++ rtw_hal_sreset_reset(padapter);
++ } else {
++ sreset_set_trigger_point(padapter, extra_arg);
++ }
++
++ }
++ break;
++ case 0x15:
++ {
++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
++ DBG_871X("==>silent resete cnts:%d\n",pwrpriv->ips_enter_cnts);
++ }
++ break;
++
++ #endif
++
++ case 0x10:// driver version display
++ DBG_871X("rtw driver version=%s\n", DRIVERVERSION);
++ break;
++ case 0x11:
++ {
++ DBG_871X("turn %s Rx RSSI display function\n",(extra_arg==1)?"on":"off");
++ padapter->bRxRSSIDisplay = extra_arg ;
++ }
++ break;
++ case 0x12: //set rx_stbc
++ {
++ struct registry_priv *pregpriv = &padapter->registrypriv;
++ // 0: disable, bit(0):enable 2.4g, bit(1):enable 5g, 0x3: enable both 2.4g and 5g
++ //default is set to enable 2.4GHZ for IOT issue with bufflao's AP at 5GHZ
++ if( pregpriv && (extra_arg == 0 || extra_arg == 1|| extra_arg == 2 || extra_arg == 3))
++ {
++ pregpriv->rx_stbc= extra_arg;
++ DBG_871X("set rx_stbc=%d\n",pregpriv->rx_stbc);
++ }
++ else
++ DBG_871X("get rx_stbc=%d\n",pregpriv->rx_stbc);
++
++ }
++ break;
++ case 0x13: //set ampdu_enable
++ {
++ struct registry_priv *pregpriv = &padapter->registrypriv;
++ // 0: disable, 0x1:enable (but wifi_spec should be 0), 0x2: force enable (don't care wifi_spec)
++ if( pregpriv && extra_arg >= 0 && extra_arg < 3 )
++ {
++ pregpriv->ampdu_enable= extra_arg;
++ DBG_871X("set ampdu_enable=%d\n",pregpriv->ampdu_enable);
++ }
++ else
++ DBG_871X("get ampdu_enable=%d\n",pregpriv->ampdu_enable);
++
++ }
++ break;
++ case 0x14: //get wifi_spec
++ {
++ struct registry_priv *pregpriv = &padapter->registrypriv;
++ DBG_871X("get wifi_spec=%d\n",pregpriv->wifi_spec);
++
++ }
++ break;
++ case 0x22:
++ {
++ DBG_871X("turn %s the ForceWriteInitGain Variable\n",(extra_arg==1)?"on":"off");
++ padapter->bForceWriteInitGain = extra_arg;
++ break;
++ }
++ case 0x23:
++ {
++ DBG_871X("turn %s the bNotifyChannelChange Variable\n",(extra_arg==1)?"on":"off");
++ padapter->bNotifyChannelChange = extra_arg;
++ break;
++ }
++ case 0x24:
++ {
++#ifdef CONFIG_P2P
++ DBG_871X("turn %s the bShowGetP2PState Variable\n",(extra_arg==1)?"on":"off");
++ padapter->bShowGetP2PState = extra_arg;
++#endif // CONFIG_P2P
++ break;
++ }
++#if 1
++ case 0xdd://registers dump , 0 for mac reg,1 for bb reg, 2 for rf reg
++ {
++ if(extra_arg==0){
++ mac_reg_dump(padapter);
++ }
++ else if(extra_arg==1){
++ bb_reg_dump(padapter);
++ }
++ else if(extra_arg==2){
++ rf_reg_dump(padapter);
++ }
++
++ }
++ break;
++#endif
++ case 0xee://turn on/off dynamic funcs
++ {
++ u8 dm_flag;
++
++ if(0xf==extra_arg){
++ rtw_hal_get_def_var(padapter, HAL_DEF_DBG_DM_FUNC,&dm_flag);
++ DBG_871X(" === DMFlag(0x%02x) === \n",dm_flag);
++ DBG_871X("extra_arg = 0 - disable all dynamic func \n");
++ DBG_871X("extra_arg = 1 - disable DIG- BIT(0)\n");
++ DBG_871X("extra_arg = 2 - disable High power - BIT(1)\n");
++ DBG_871X("extra_arg = 3 - disable tx power tracking - BIT(2)\n");
++ DBG_871X("extra_arg = 4 - disable BT coexistence - BIT(3)\n");
++ DBG_871X("extra_arg = 5 - disable antenna diversity - BIT(4)\n");
++ DBG_871X("extra_arg = 6 - enable all dynamic func \n");
++ }
++ else{
++ /* extra_arg = 0 - disable all dynamic func
++ extra_arg = 1 - disable DIG
++ extra_arg = 2 - disable tx power tracking
++ extra_arg = 3 - turn on all dynamic func
++ */
++ rtw_hal_set_def_var(padapter, HAL_DEF_DBG_DM_FUNC, &(extra_arg));
++ rtw_hal_get_def_var(padapter, HAL_DEF_DBG_DM_FUNC,&dm_flag);
++ DBG_871X(" === DMFlag(0x%02x) === \n",dm_flag);
++ }
++ }
++ break;
++
++ case 0xfd:
++ rtw_write8(padapter, 0xc50, arg);
++ DBG_871X("wr(0xc50)=0x%x\n", rtw_read8(padapter, 0xc50));
++ rtw_write8(padapter, 0xc58, arg);
++ DBG_871X("wr(0xc58)=0x%x\n", rtw_read8(padapter, 0xc58));
++ break;
++ case 0xfe:
++ DBG_871X("rd(0xc50)=0x%x\n", rtw_read8(padapter, 0xc50));
++ DBG_871X("rd(0xc58)=0x%x\n", rtw_read8(padapter, 0xc58));
++ break;
++ case 0xff:
++ {
++ DBG_871X("dbg(0x210)=0x%x\n", rtw_read32(padapter, 0x210));
++ DBG_871X("dbg(0x608)=0x%x\n", rtw_read32(padapter, 0x608));
++ DBG_871X("dbg(0x280)=0x%x\n", rtw_read32(padapter, 0x280));
++ DBG_871X("dbg(0x284)=0x%x\n", rtw_read32(padapter, 0x284));
++ DBG_871X("dbg(0x288)=0x%x\n", rtw_read32(padapter, 0x288));
++
++ DBG_871X("dbg(0x664)=0x%x\n", rtw_read32(padapter, 0x664));
++
++
++ DBG_871X("\n");
++
++ DBG_871X("dbg(0x430)=0x%x\n", rtw_read32(padapter, 0x430));
++ DBG_871X("dbg(0x438)=0x%x\n", rtw_read32(padapter, 0x438));
++
++ DBG_871X("dbg(0x440)=0x%x\n", rtw_read32(padapter, 0x440));
++
++ DBG_871X("dbg(0x458)=0x%x\n", rtw_read32(padapter, 0x458));
++
++ DBG_871X("dbg(0x484)=0x%x\n", rtw_read32(padapter, 0x484));
++ DBG_871X("dbg(0x488)=0x%x\n", rtw_read32(padapter, 0x488));
++
++ DBG_871X("dbg(0x444)=0x%x\n", rtw_read32(padapter, 0x444));
++ DBG_871X("dbg(0x448)=0x%x\n", rtw_read32(padapter, 0x448));
++ DBG_871X("dbg(0x44c)=0x%x\n", rtw_read32(padapter, 0x44c));
++ DBG_871X("dbg(0x450)=0x%x\n", rtw_read32(padapter, 0x450));
++ }
++ break;
++ }
++ break;
++ default:
++ DBG_871X("error dbg cmd!\n");
++ break;
++ }
++
++
++ return ret;
++
++}
++
++static int wpa_set_param(struct net_device *dev, u8 name, u32 value)
++{
++ uint ret=0;
++ u32 flags;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++
++ switch (name){
++ case IEEE_PARAM_WPA_ENABLED:
++
++ padapter->securitypriv.dot11AuthAlgrthm= dot11AuthAlgrthm_8021X; //802.1x
++
++ //ret = ieee80211_wpa_enable(ieee, value);
++
++ switch((value)&0xff)
++ {
++ case 1 : //WPA
++ padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeWPAPSK; //WPA_PSK
++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption2Enabled;
++ break;
++ case 2: //WPA2
++ padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeWPA2PSK; //WPA2_PSK
++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption3Enabled;
++ break;
++ }
++
++ RT_TRACE(_module_rtl871x_ioctl_os_c,_drv_info_,("wpa_set_param:padapter->securitypriv.ndisauthtype=%d\n", padapter->securitypriv.ndisauthtype));
++
++ break;
++
++ case IEEE_PARAM_TKIP_COUNTERMEASURES:
++ //ieee->tkip_countermeasures=value;
++ break;
++
++ case IEEE_PARAM_DROP_UNENCRYPTED:
++ {
++ /* HACK:
++ *
++ * wpa_supplicant calls set_wpa_enabled when the driver
++ * is loaded and unloaded, regardless of if WPA is being
++ * used. No other calls are made which can be used to
++ * determine if encryption will be used or not prior to
++ * association being expected. If encryption is not being
++ * used, drop_unencrypted is set to false, else true -- we
++ * can use this to determine if the CAP_PRIVACY_ON bit should
++ * be set.
++ */
++
++#if 0
++ struct ieee80211_security sec = {
++ .flags = SEC_ENABLED,
++ .enabled = value,
++ };
++ ieee->drop_unencrypted = value;
++ /* We only change SEC_LEVEL for open mode. Others
++ * are set by ipw_wpa_set_encryption.
++ */
++ if (!value) {
++ sec.flags |= SEC_LEVEL;
++ sec.level = SEC_LEVEL_0;
++ }
++ else {
++ sec.flags |= SEC_LEVEL;
++ sec.level = SEC_LEVEL_1;
++ }
++ if (ieee->set_security)
++ ieee->set_security(ieee->dev, &sec);
++#endif
++ break;
++
++ }
++ case IEEE_PARAM_PRIVACY_INVOKED:
++
++ //ieee->privacy_invoked=value;
++
++ break;
++
++ case IEEE_PARAM_AUTH_ALGS:
++
++ ret = wpa_set_auth_algs(dev, value);
++
++ break;
++
++ case IEEE_PARAM_IEEE_802_1X:
++
++ //ieee->ieee802_1x=value;
++
++ break;
++
++ case IEEE_PARAM_WPAX_SELECT:
++
++ // added for WPA2 mixed mode
++ //DBG_871X(KERN_WARNING "------------------------>wpax value = %x\n", value);
++ /*
++ spin_lock_irqsave(&ieee->wpax_suitlist_lock,flags);
++ ieee->wpax_type_set = 1;
++ ieee->wpax_type_notify = value;
++ spin_unlock_irqrestore(&ieee->wpax_suitlist_lock,flags);
++ */
++
++ break;
++
++ default:
++
++
++
++ ret = -EOPNOTSUPP;
++
++
++ break;
++
++ }
++
++ return ret;
++
++}
++
++static int wpa_mlme(struct net_device *dev, u32 command, u32 reason)
++{
++ int ret = 0;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++
++ switch (command)
++ {
++ case IEEE_MLME_STA_DEAUTH:
++
++ if(!rtw_set_802_11_disassociate(padapter))
++ ret = -1;
++
++ break;
++
++ case IEEE_MLME_STA_DISASSOC:
++
++ if(!rtw_set_802_11_disassociate(padapter))
++ ret = -1;
++
++ break;
++
++ default:
++ ret = -EOPNOTSUPP;
++ break;
++ }
++
++ return ret;
++
++}
++
++static int wpa_supplicant_ioctl(struct net_device *dev, struct iw_point *p)
++{
++ struct ieee_param *param;
++ uint ret=0;
++
++ //down(&ieee->wx_sem);
++
++ if (p->length < sizeof(struct ieee_param) || !p->pointer){
++ ret = -EINVAL;
++ goto out;
++ }
++
++ param = (struct ieee_param *)rtw_malloc(p->length);
++ if (param == NULL)
++ {
++ ret = -ENOMEM;
++ goto out;
++ }
++
++ if (copy_from_user(param, p->pointer, p->length))
++ {
++ rtw_mfree((u8*)param, p->length);
++ ret = -EFAULT;
++ goto out;
++ }
++
++ switch (param->cmd) {
++
++ case IEEE_CMD_SET_WPA_PARAM:
++ ret = wpa_set_param(dev, param->u.wpa_param.name, param->u.wpa_param.value);
++ break;
++
++ case IEEE_CMD_SET_WPA_IE:
++ //ret = wpa_set_wpa_ie(dev, param, p->length);
++ ret = rtw_set_wpa_ie((_adapter *)rtw_netdev_priv(dev), (char*)param->u.wpa_ie.data, (u16)param->u.wpa_ie.len);
++ break;
++
++ case IEEE_CMD_SET_ENCRYPTION:
++ ret = wpa_set_encryption(dev, param, p->length);
++ break;
++
++ case IEEE_CMD_MLME:
++ ret = wpa_mlme(dev, param->u.mlme.command, param->u.mlme.reason_code);
++ break;
++
++ default:
++ DBG_871X("Unknown WPA supplicant request: %d\n", param->cmd);
++ ret = -EOPNOTSUPP;
++ break;
++
++ }
++
++ if (ret == 0 && copy_to_user(p->pointer, param, p->length))
++ ret = -EFAULT;
++
++ rtw_mfree((u8 *)param, p->length);
++
++out:
++
++ //up(&ieee->wx_sem);
++
++ return ret;
++
++}
++
++#ifdef CONFIG_AP_MODE
++static u8 set_pairwise_key(_adapter *padapter, struct sta_info *psta)
++{
++ struct cmd_obj* ph2c;
++ struct set_stakey_parm *psetstakey_para;
++ struct cmd_priv *pcmdpriv=&padapter->cmdpriv;
++ u8 res=_SUCCESS;
++
++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj));
++ if ( ph2c == NULL){
++ res= _FAIL;
++ goto exit;
++ }
++
++ psetstakey_para = (struct set_stakey_parm*)rtw_zmalloc(sizeof(struct set_stakey_parm));
++ if(psetstakey_para==NULL){
++ rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj));
++ res=_FAIL;
++ goto exit;
++ }
++
++ init_h2fwcmd_w_parm_no_rsp(ph2c, psetstakey_para, _SetStaKey_CMD_);
++
++
++ psetstakey_para->algorithm = (u8)psta->dot118021XPrivacy;
++
++ _rtw_memcpy(psetstakey_para->addr, psta->hwaddr, ETH_ALEN);
++
++ _rtw_memcpy(psetstakey_para->key, &psta->dot118021x_UncstKey, 16);
++
++
++ res = rtw_enqueue_cmd(pcmdpriv, ph2c);
++
++exit:
++
++ return res;
++
++}
++
++static int set_group_key(_adapter *padapter, u8 *key, u8 alg, int keyid)
++{
++ u8 keylen;
++ struct cmd_obj* pcmd;
++ struct setkey_parm *psetkeyparm;
++ struct cmd_priv *pcmdpriv=&(padapter->cmdpriv);
++ int res=_SUCCESS;
++
++ DBG_871X("%s\n", __FUNCTION__);
++
++ pcmd = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj));
++ if(pcmd==NULL){
++ res= _FAIL;
++ goto exit;
++ }
++ psetkeyparm=(struct setkey_parm*)rtw_zmalloc(sizeof(struct setkey_parm));
++ if(psetkeyparm==NULL){
++ rtw_mfree((unsigned char *)pcmd, sizeof(struct cmd_obj));
++ res= _FAIL;
++ goto exit;
++ }
++
++ _rtw_memset(psetkeyparm, 0, sizeof(struct setkey_parm));
++
++ psetkeyparm->keyid=(u8)keyid;
++ if (is_wep_enc(alg))
++ padapter->securitypriv.key_mask |= BIT(psetkeyparm->keyid);
++
++ psetkeyparm->algorithm = alg;
++
++ psetkeyparm->set_tx = 1;
++
++ switch(alg)
++ {
++ case _WEP40_:
++ keylen = 5;
++ break;
++ case _WEP104_:
++ keylen = 13;
++ break;
++ case _TKIP_:
++ case _TKIP_WTMIC_:
++ case _AES_:
++ keylen = 16;
++ default:
++ keylen = 16;
++ }
++
++ _rtw_memcpy(&(psetkeyparm->key[0]), key, keylen);
++
++ pcmd->cmdcode = _SetKey_CMD_;
++ pcmd->parmbuf = (u8 *)psetkeyparm;
++ pcmd->cmdsz = (sizeof(struct setkey_parm));
++ pcmd->rsp = NULL;
++ pcmd->rspsz = 0;
++
++
++ _rtw_init_listhead(&pcmd->list);
++
++ res = rtw_enqueue_cmd(pcmdpriv, pcmd);
++
++exit:
++
++ return res;
++
++
++}
++
++static int set_wep_key(_adapter *padapter, u8 *key, u8 keylen, int keyid)
++{
++ u8 alg;
++
++ switch(keylen)
++ {
++ case 5:
++ alg =_WEP40_;
++ break;
++ case 13:
++ alg =_WEP104_;
++ break;
++ default:
++ alg =_NO_PRIVACY_;
++ }
++
++ return set_group_key(padapter, key, alg, keyid);
++
++}
++
++
++static int rtw_set_encryption(struct net_device *dev, struct ieee_param *param, u32 param_len)
++{
++ int ret = 0;
++ u32 wep_key_idx, wep_key_len,wep_total_len;
++ NDIS_802_11_WEP *pwep = NULL;
++ struct sta_info *psta = NULL, *pbcmc_sta = NULL;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct security_priv* psecuritypriv=&(padapter->securitypriv);
++ struct sta_priv *pstapriv = &padapter->stapriv;
++
++ DBG_871X("%s\n", __FUNCTION__);
++
++ param->u.crypt.err = 0;
++ param->u.crypt.alg[IEEE_CRYPT_ALG_NAME_LEN - 1] = '\0';
++
++ //sizeof(struct ieee_param) = 64 bytes;
++ //if (param_len != (u32) ((u8 *) param->u.crypt.key - (u8 *) param) + param->u.crypt.key_len)
++ if (param_len != sizeof(struct ieee_param) + param->u.crypt.key_len)
++ {
++ ret = -EINVAL;
++ goto exit;
++ }
++
++ if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff &&
++ param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff &&
++ param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff)
++ {
++ if (param->u.crypt.idx >= WEP_KEYS)
++ {
++ ret = -EINVAL;
++ goto exit;
++ }
++ }
++ else
++ {
++ psta = rtw_get_stainfo(pstapriv, param->sta_addr);
++ if(!psta)
++ {
++ //ret = -EINVAL;
++ DBG_871X("rtw_set_encryption(), sta has already been removed or never been added\n");
++ goto exit;
++ }
++ }
++
++ if (strcmp(param->u.crypt.alg, "none") == 0 && (psta==NULL))
++ {
++ //todo:clear default encryption keys
++
++ DBG_871X("clear default encryption keys, keyid=%d\n", param->u.crypt.idx);
++
++ goto exit;
++ }
++
++
++ if (strcmp(param->u.crypt.alg, "WEP") == 0 && (psta==NULL))
++ {
++ DBG_871X("r871x_set_encryption, crypt.alg = WEP\n");
++
++ wep_key_idx = param->u.crypt.idx;
++ wep_key_len = param->u.crypt.key_len;
++
++ DBG_871X("r871x_set_encryption, wep_key_idx=%d, len=%d\n", wep_key_idx, wep_key_len);
++
++ if((wep_key_idx >= WEP_KEYS) || (wep_key_len<=0))
++ {
++ ret = -EINVAL;
++ goto exit;
++ }
++
++
++ if (wep_key_len > 0)
++ {
++ wep_key_len = wep_key_len <= 5 ? 5 : 13;
++ wep_total_len = wep_key_len + FIELD_OFFSET(NDIS_802_11_WEP, KeyMaterial);
++ pwep =(NDIS_802_11_WEP *)rtw_malloc(wep_total_len);
++ if(pwep == NULL){
++ DBG_871X(" r871x_set_encryption: pwep allocate fail !!!\n");
++ goto exit;
++ }
++
++ _rtw_memset(pwep, 0, wep_total_len);
++
++ pwep->KeyLength = wep_key_len;
++ pwep->Length = wep_total_len;
++
++ }
++
++ pwep->KeyIndex = wep_key_idx;
++
++ _rtw_memcpy(pwep->KeyMaterial, param->u.crypt.key, pwep->KeyLength);
++
++ if(param->u.crypt.set_tx)
++ {
++ DBG_871X("wep, set_tx=1\n");
++
++ psecuritypriv->ndisencryptstatus = Ndis802_11Encryption1Enabled;
++ psecuritypriv->dot11PrivacyAlgrthm=_WEP40_;
++ psecuritypriv->dot118021XGrpPrivacy=_WEP40_;
++
++ if(pwep->KeyLength==13)
++ {
++ psecuritypriv->dot11PrivacyAlgrthm=_WEP104_;
++ psecuritypriv->dot118021XGrpPrivacy=_WEP104_;
++ }
++
++
++ psecuritypriv->dot11PrivacyKeyIndex = wep_key_idx;
++
++ _rtw_memcpy(&(psecuritypriv->dot11DefKey[wep_key_idx].skey[0]), pwep->KeyMaterial, pwep->KeyLength);
++
++ psecuritypriv->dot11DefKeylen[wep_key_idx]=pwep->KeyLength;
++
++ set_wep_key(padapter, pwep->KeyMaterial, pwep->KeyLength, wep_key_idx);
++
++
++ }
++ else
++ {
++ DBG_871X("wep, set_tx=0\n");
++
++ //don't update "psecuritypriv->dot11PrivacyAlgrthm" and
++ //"psecuritypriv->dot11PrivacyKeyIndex=keyid", but can rtw_set_key to cam
++
++ _rtw_memcpy(&(psecuritypriv->dot11DefKey[wep_key_idx].skey[0]), pwep->KeyMaterial, pwep->KeyLength);
++
++ psecuritypriv->dot11DefKeylen[wep_key_idx] = pwep->KeyLength;
++
++ set_wep_key(padapter, pwep->KeyMaterial, pwep->KeyLength, wep_key_idx);
++
++ }
++
++ goto exit;
++
++ }
++
++
++ if(!psta && check_fwstate(pmlmepriv, WIFI_AP_STATE)) // //group key
++ {
++ if(param->u.crypt.set_tx ==1)
++ {
++ if(strcmp(param->u.crypt.alg, "WEP") == 0)
++ {
++ DBG_871X("%s, set group_key, WEP\n", __FUNCTION__);
++
++ _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len>16 ?16:param->u.crypt.key_len));
++
++ psecuritypriv->dot118021XGrpPrivacy = _WEP40_;
++ if(param->u.crypt.key_len==13)
++ {
++ psecuritypriv->dot118021XGrpPrivacy = _WEP104_;
++ }
++
++ }
++ else if(strcmp(param->u.crypt.alg, "TKIP") == 0)
++ {
++ DBG_871X("%s, set group_key, TKIP\n", __FUNCTION__);
++
++ psecuritypriv->dot118021XGrpPrivacy = _TKIP_;
++
++ _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len>16 ?16:param->u.crypt.key_len));
++
++ //DEBUG_ERR("set key length :param->u.crypt.key_len=%d\n", param->u.crypt.key_len);
++ //set mic key
++ _rtw_memcpy(psecuritypriv->dot118021XGrptxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[16]), 8);
++ _rtw_memcpy(psecuritypriv->dot118021XGrprxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[24]), 8);
++
++ psecuritypriv->busetkipkey = _TRUE;
++
++ }
++ else if(strcmp(param->u.crypt.alg, "CCMP") == 0)
++ {
++ DBG_871X("%s, set group_key, CCMP\n", __FUNCTION__);
++
++ psecuritypriv->dot118021XGrpPrivacy = _AES_;
++
++ _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len>16 ?16:param->u.crypt.key_len));
++ }
++ else
++ {
++ DBG_871X("%s, set group_key, none\n", __FUNCTION__);
++
++ psecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_;
++ }
++
++ psecuritypriv->dot118021XGrpKeyid = param->u.crypt.idx;
++
++ psecuritypriv->binstallGrpkey = _TRUE;
++
++ psecuritypriv->dot11PrivacyAlgrthm = psecuritypriv->dot118021XGrpPrivacy;//!!!
++
++ set_group_key(padapter, param->u.crypt.key, psecuritypriv->dot118021XGrpPrivacy, param->u.crypt.idx);
++
++ pbcmc_sta=rtw_get_bcmc_stainfo(padapter);
++ if(pbcmc_sta)
++ {
++ pbcmc_sta->ieee8021x_blocked = _FALSE;
++ pbcmc_sta->dot118021XPrivacy= psecuritypriv->dot118021XGrpPrivacy;//rx will use bmc_sta's dot118021XPrivacy
++ }
++
++ }
++
++ goto exit;
++
++ }
++
++ if(psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X && psta) // psk/802_1x
++ {
++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE))
++ {
++ if(param->u.crypt.set_tx ==1)
++ {
++ _rtw_memcpy(psta->dot118021x_UncstKey.skey, param->u.crypt.key, (param->u.crypt.key_len>16 ?16:param->u.crypt.key_len));
++
++ if(strcmp(param->u.crypt.alg, "WEP") == 0)
++ {
++ DBG_871X("%s, set pairwise key, WEP\n", __FUNCTION__);
++
++ psta->dot118021XPrivacy = _WEP40_;
++ if(param->u.crypt.key_len==13)
++ {
++ psta->dot118021XPrivacy = _WEP104_;
++ }
++ }
++ else if(strcmp(param->u.crypt.alg, "TKIP") == 0)
++ {
++ DBG_871X("%s, set pairwise key, TKIP\n", __FUNCTION__);
++
++ psta->dot118021XPrivacy = _TKIP_;
++
++ //DEBUG_ERR("set key length :param->u.crypt.key_len=%d\n", param->u.crypt.key_len);
++ //set mic key
++ _rtw_memcpy(psta->dot11tkiptxmickey.skey, &(param->u.crypt.key[16]), 8);
++ _rtw_memcpy(psta->dot11tkiprxmickey.skey, &(param->u.crypt.key[24]), 8);
++
++ psecuritypriv->busetkipkey = _TRUE;
++
++ }
++ else if(strcmp(param->u.crypt.alg, "CCMP") == 0)
++ {
++
++ DBG_871X("%s, set pairwise key, CCMP\n", __FUNCTION__);
++
++ psta->dot118021XPrivacy = _AES_;
++ }
++ else
++ {
++ DBG_871X("%s, set pairwise key, none\n", __FUNCTION__);
++
++ psta->dot118021XPrivacy = _NO_PRIVACY_;
++ }
++
++ set_pairwise_key(padapter, psta);
++
++ psta->ieee8021x_blocked = _FALSE;
++
++ }
++ else//group key???
++ {
++ if(strcmp(param->u.crypt.alg, "WEP") == 0)
++ {
++ _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len>16 ?16:param->u.crypt.key_len));
++
++ psecuritypriv->dot118021XGrpPrivacy = _WEP40_;
++ if(param->u.crypt.key_len==13)
++ {
++ psecuritypriv->dot118021XGrpPrivacy = _WEP104_;
++ }
++ }
++ else if(strcmp(param->u.crypt.alg, "TKIP") == 0)
++ {
++ psecuritypriv->dot118021XGrpPrivacy = _TKIP_;
++
++ _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len>16 ?16:param->u.crypt.key_len));
++
++ //DEBUG_ERR("set key length :param->u.crypt.key_len=%d\n", param->u.crypt.key_len);
++ //set mic key
++ _rtw_memcpy(psecuritypriv->dot118021XGrptxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[16]), 8);
++ _rtw_memcpy(psecuritypriv->dot118021XGrprxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[24]), 8);
++
++ psecuritypriv->busetkipkey = _TRUE;
++
++ }
++ else if(strcmp(param->u.crypt.alg, "CCMP") == 0)
++ {
++ psecuritypriv->dot118021XGrpPrivacy = _AES_;
++
++ _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len>16 ?16:param->u.crypt.key_len));
++ }
++ else
++ {
++ psecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_;
++ }
++
++ psecuritypriv->dot118021XGrpKeyid = param->u.crypt.idx;
++
++ psecuritypriv->binstallGrpkey = _TRUE;
++
++ psecuritypriv->dot11PrivacyAlgrthm = psecuritypriv->dot118021XGrpPrivacy;//!!!
++
++ set_group_key(padapter, param->u.crypt.key, psecuritypriv->dot118021XGrpPrivacy, param->u.crypt.idx);
++
++ pbcmc_sta=rtw_get_bcmc_stainfo(padapter);
++ if(pbcmc_sta)
++ {
++ pbcmc_sta->ieee8021x_blocked = _FALSE;
++ pbcmc_sta->dot118021XPrivacy= psecuritypriv->dot118021XGrpPrivacy;//rx will use bmc_sta's dot118021XPrivacy
++ }
++
++ }
++
++ }
++
++ }
++
++exit:
++
++ if(pwep)
++ {
++ rtw_mfree((u8 *)pwep,wep_total_len);
++ }
++
++ return ret;
++
++}
++
++static int rtw_set_beacon(struct net_device *dev, struct ieee_param *param, int len)
++{
++ int ret=0;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ struct sta_priv *pstapriv = &padapter->stapriv;
++ unsigned char *pbuf = param->u.bcn_ie.buf;
++
++
++ DBG_871X("%s, len=%d\n", __FUNCTION__, len);
++
++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE)
++ return -EINVAL;
++
++ _rtw_memcpy(&pstapriv->max_num_sta, param->u.bcn_ie.reserved, 2);
++
++ if((pstapriv->max_num_sta>NUM_STA) || (pstapriv->max_num_sta<=0))
++ pstapriv->max_num_sta = NUM_STA;
++
++
++ if(rtw_check_beacon_data(padapter, pbuf, (len-12-2)) == _SUCCESS)// 12 = param header, 2:no packed
++ ret = 0;
++ else
++ ret = -EINVAL;
++
++
++ return ret;
++
++}
++
++static int rtw_hostapd_sta_flush(struct net_device *dev)
++{
++ //_irqL irqL;
++ //_list *phead, *plist;
++ int ret=0;
++ //struct sta_info *psta = NULL;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ //struct sta_priv *pstapriv = &padapter->stapriv;
++
++ DBG_871X("%s\n", __FUNCTION__);
++
++ flush_all_cam_entry(padapter); //clear CAM
++
++ ret = rtw_sta_flush(padapter);
++
++ return ret;
++
++}
++
++static int rtw_add_sta(struct net_device *dev, struct ieee_param *param)
++{
++ _irqL irqL;
++ int ret=0;
++ struct sta_info *psta = NULL;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ struct sta_priv *pstapriv = &padapter->stapriv;
++
++ DBG_871X("rtw_add_sta(aid=%d)=" MAC_FMT "\n", param->u.add_sta.aid, MAC_ARG(param->sta_addr));
++
++ if(check_fwstate(pmlmepriv, (_FW_LINKED|WIFI_AP_STATE)) != _TRUE)
++ {
++ return -EINVAL;
++ }
++
++ if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff &&
++ param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff &&
++ param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff)
++ {
++ return -EINVAL;
++ }
++
++/*
++ psta = rtw_get_stainfo(pstapriv, param->sta_addr);
++ if(psta)
++ {
++ DBG_871X("rtw_add_sta(), free has been added psta=%p\n", psta);
++ _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL);
++ rtw_free_stainfo(padapter, psta);
++ _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);
++
++ psta = NULL;
++ }
++*/
++ //psta = rtw_alloc_stainfo(pstapriv, param->sta_addr);
++ psta = rtw_get_stainfo(pstapriv, param->sta_addr);
++ if(psta)
++ {
++ int flags = param->u.add_sta.flags;
++
++ //DBG_871X("rtw_add_sta(), init sta's variables, psta=%p\n", psta);
++
++ psta->aid = param->u.add_sta.aid;//aid=1~2007
++
++ _rtw_memcpy(psta->bssrateset, param->u.add_sta.tx_supp_rates, 16);
++
++
++ //check wmm cap.
++ if(WLAN_STA_WME&flags)
++ psta->qos_option = 1;
++ else
++ psta->qos_option = 0;
++
++ if(pmlmepriv->qospriv.qos_option == 0)
++ psta->qos_option = 0;
++
++
++#ifdef CONFIG_80211N_HT
++ //chec 802.11n ht cap.
++ if(WLAN_STA_HT&flags)
++ {
++ psta->htpriv.ht_option = _TRUE;
++ psta->qos_option = 1;
++ _rtw_memcpy((void*)&psta->htpriv.ht_cap, (void*)&param->u.add_sta.ht_cap, sizeof(struct rtw_ieee80211_ht_cap));
++ }
++ else
++ {
++ psta->htpriv.ht_option = _FALSE;
++ }
++
++ if(pmlmepriv->htpriv.ht_option == _FALSE)
++ psta->htpriv.ht_option = _FALSE;
++#endif
++
++
++ update_sta_info_apmode(padapter, psta);
++
++
++ }
++ else
++ {
++ ret = -ENOMEM;
++ }
++
++ return ret;
++
++}
++
++static int rtw_del_sta(struct net_device *dev, struct ieee_param *param)
++{
++ _irqL irqL;
++ int ret=0;
++ struct sta_info *psta = NULL;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ struct sta_priv *pstapriv = &padapter->stapriv;
++
++ DBG_871X("rtw_del_sta=" MAC_FMT "\n", MAC_ARG(param->sta_addr));
++
++ if(check_fwstate(pmlmepriv, (_FW_LINKED|WIFI_AP_STATE)) != _TRUE)
++ {
++ return -EINVAL;
++ }
++
++ if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff &&
++ param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff &&
++ param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff)
++ {
++ return -EINVAL;
++ }
++
++ psta = rtw_get_stainfo(pstapriv, param->sta_addr);
++ if(psta)
++ {
++ u8 updated=_FALSE;
++
++ //DBG_871X("free psta=%p, aid=%d\n", psta, psta->aid);
++
++ _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++ if(rtw_is_list_empty(&psta->asoc_list)==_FALSE)
++ {
++ rtw_list_delete(&psta->asoc_list);
++ pstapriv->asoc_list_cnt--;
++ updated = ap_free_sta(padapter, psta, _TRUE, WLAN_REASON_DEAUTH_LEAVING);
++
++ }
++ _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++
++ associated_clients_update(padapter, updated);
++
++ psta = NULL;
++
++ }
++ else
++ {
++ DBG_871X("rtw_del_sta(), sta has already been removed or never been added\n");
++
++ //ret = -1;
++ }
++
++
++ return ret;
++
++}
++
++static int rtw_ioctl_get_sta_data(struct net_device *dev, struct ieee_param *param, int len)
++{
++ int ret=0;
++ struct sta_info *psta = NULL;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ struct sta_priv *pstapriv = &padapter->stapriv;
++ struct ieee_param_ex *param_ex = (struct ieee_param_ex *)param;
++ struct sta_data *psta_data = (struct sta_data *)param_ex->data;
++
++ DBG_871X("rtw_ioctl_get_sta_info, sta_addr: " MAC_FMT "\n", MAC_ARG(param_ex->sta_addr));
++
++ if(check_fwstate(pmlmepriv, (_FW_LINKED|WIFI_AP_STATE)) != _TRUE)
++ {
++ return -EINVAL;
++ }
++
++ if (param_ex->sta_addr[0] == 0xff && param_ex->sta_addr[1] == 0xff &&
++ param_ex->sta_addr[2] == 0xff && param_ex->sta_addr[3] == 0xff &&
++ param_ex->sta_addr[4] == 0xff && param_ex->sta_addr[5] == 0xff)
++ {
++ return -EINVAL;
++ }
++
++ psta = rtw_get_stainfo(pstapriv, param_ex->sta_addr);
++ if(psta)
++ {
++#if 0
++ struct {
++ u16 aid;
++ u16 capability;
++ int flags;
++ u32 sta_set;
++ u8 tx_supp_rates[16];
++ u32 tx_supp_rates_len;
++ struct rtw_ieee80211_ht_cap ht_cap;
++ u64 rx_pkts;
++ u64 rx_bytes;
++ u64 rx_drops;
++ u64 tx_pkts;
++ u64 tx_bytes;
++ u64 tx_drops;
++ } get_sta;
++#endif
++ psta_data->aid = (u16)psta->aid;
++ psta_data->capability = psta->capability;
++ psta_data->flags = psta->flags;
++
++/*
++ nonerp_set : BIT(0)
++ no_short_slot_time_set : BIT(1)
++ no_short_preamble_set : BIT(2)
++ no_ht_gf_set : BIT(3)
++ no_ht_set : BIT(4)
++ ht_20mhz_set : BIT(5)
++*/
++
++ psta_data->sta_set =((psta->nonerp_set) |
++ (psta->no_short_slot_time_set <<1) |
++ (psta->no_short_preamble_set <<2) |
++ (psta->no_ht_gf_set <<3) |
++ (psta->no_ht_set <<4) |
++ (psta->ht_20mhz_set <<5));
++
++ psta_data->tx_supp_rates_len = psta->bssratelen;
++ _rtw_memcpy(psta_data->tx_supp_rates, psta->bssrateset, psta->bssratelen);
++
++ _rtw_memcpy(&psta_data->ht_cap, &psta->htpriv.ht_cap, sizeof(struct rtw_ieee80211_ht_cap));
++
++ psta_data->rx_pkts = psta->sta_stats.rx_data_pkts;
++ psta_data->rx_bytes = psta->sta_stats.rx_bytes;
++ psta_data->rx_drops = psta->sta_stats.rx_drops;
++
++ psta_data->tx_pkts = psta->sta_stats.tx_pkts;
++ psta_data->tx_bytes = psta->sta_stats.tx_bytes;
++ psta_data->tx_drops = psta->sta_stats.tx_drops;
++
++
++ }
++ else
++ {
++ ret = -1;
++ }
++
++ return ret;
++
++}
++
++static int rtw_get_sta_wpaie(struct net_device *dev, struct ieee_param *param)
++{
++ int ret=0;
++ struct sta_info *psta = NULL;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ struct sta_priv *pstapriv = &padapter->stapriv;
++
++ DBG_871X("rtw_get_sta_wpaie, sta_addr: " MAC_FMT "\n", MAC_ARG(param->sta_addr));
++
++ if(check_fwstate(pmlmepriv, (_FW_LINKED|WIFI_AP_STATE)) != _TRUE)
++ {
++ return -EINVAL;
++ }
++
++ if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff &&
++ param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff &&
++ param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff)
++ {
++ return -EINVAL;
++ }
++
++ psta = rtw_get_stainfo(pstapriv, param->sta_addr);
++ if(psta)
++ {
++ if((psta->wpa_ie[0] == WLAN_EID_RSN) || (psta->wpa_ie[0] == WLAN_EID_GENERIC))
++ {
++ int wpa_ie_len;
++ int copy_len;
++
++ wpa_ie_len = psta->wpa_ie[1];
++
++ copy_len = ((wpa_ie_len+2) > sizeof(psta->wpa_ie)) ? (sizeof(psta->wpa_ie)):(wpa_ie_len+2);
++
++ param->u.wpa_ie.len = copy_len;
++
++ _rtw_memcpy(param->u.wpa_ie.reserved, psta->wpa_ie, copy_len);
++ }
++ else
++ {
++ //ret = -1;
++ DBG_871X("sta's wpa_ie is NONE\n");
++ }
++ }
++ else
++ {
++ ret = -1;
++ }
++
++ return ret;
++
++}
++
++static int rtw_set_wps_beacon(struct net_device *dev, struct ieee_param *param, int len)
++{
++ int ret=0;
++ unsigned char wps_oui[4]={0x0,0x50,0xf2,0x04};
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ int ie_len;
++
++ DBG_871X("%s, len=%d\n", __FUNCTION__, len);
++
++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE)
++ return -EINVAL;
++
++ ie_len = len-12-2;// 12 = param header, 2:no packed
++
++
++ if(pmlmepriv->wps_beacon_ie)
++ {
++ rtw_mfree(pmlmepriv->wps_beacon_ie, pmlmepriv->wps_beacon_ie_len);
++ pmlmepriv->wps_beacon_ie = NULL;
++ }
++
++ if(ie_len>0)
++ {
++ pmlmepriv->wps_beacon_ie = rtw_malloc(ie_len);
++ pmlmepriv->wps_beacon_ie_len = ie_len;
++ if ( pmlmepriv->wps_beacon_ie == NULL) {
++ DBG_871X("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__);
++ return -EINVAL;
++ }
++
++ _rtw_memcpy(pmlmepriv->wps_beacon_ie, param->u.bcn_ie.buf, ie_len);
++
++ update_beacon(padapter, _VENDOR_SPECIFIC_IE_, wps_oui, _TRUE);
++
++ pmlmeext->bstart_bss = _TRUE;
++
++ }
++
++
++ return ret;
++
++}
++
++static int rtw_set_wps_probe_resp(struct net_device *dev, struct ieee_param *param, int len)
++{
++ int ret=0;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ int ie_len;
++
++ DBG_871X("%s, len=%d\n", __FUNCTION__, len);
++
++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE)
++ return -EINVAL;
++
++ ie_len = len-12-2;// 12 = param header, 2:no packed
++
++
++ if(pmlmepriv->wps_probe_resp_ie)
++ {
++ rtw_mfree(pmlmepriv->wps_probe_resp_ie, pmlmepriv->wps_probe_resp_ie_len);
++ pmlmepriv->wps_probe_resp_ie = NULL;
++ }
++
++ if(ie_len>0)
++ {
++ pmlmepriv->wps_probe_resp_ie = rtw_malloc(ie_len);
++ pmlmepriv->wps_probe_resp_ie_len = ie_len;
++ if ( pmlmepriv->wps_probe_resp_ie == NULL) {
++ DBG_871X("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__);
++ return -EINVAL;
++ }
++ _rtw_memcpy(pmlmepriv->wps_probe_resp_ie, param->u.bcn_ie.buf, ie_len);
++ }
++
++
++ return ret;
++
++}
++
++static int rtw_set_wps_assoc_resp(struct net_device *dev, struct ieee_param *param, int len)
++{
++ int ret=0;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ int ie_len;
++
++ DBG_871X("%s, len=%d\n", __FUNCTION__, len);
++
++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE)
++ return -EINVAL;
++
++ ie_len = len-12-2;// 12 = param header, 2:no packed
++
++
++ if(pmlmepriv->wps_assoc_resp_ie)
++ {
++ rtw_mfree(pmlmepriv->wps_assoc_resp_ie, pmlmepriv->wps_assoc_resp_ie_len);
++ pmlmepriv->wps_assoc_resp_ie = NULL;
++ }
++
++ if(ie_len>0)
++ {
++ pmlmepriv->wps_assoc_resp_ie = rtw_malloc(ie_len);
++ pmlmepriv->wps_assoc_resp_ie_len = ie_len;
++ if ( pmlmepriv->wps_assoc_resp_ie == NULL) {
++ DBG_871X("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__);
++ return -EINVAL;
++ }
++
++ _rtw_memcpy(pmlmepriv->wps_assoc_resp_ie, param->u.bcn_ie.buf, ie_len);
++ }
++
++
++ return ret;
++
++}
++
++static int rtw_set_hidden_ssid(struct net_device *dev, struct ieee_param *param, int len)
++{
++ int ret=0;
++ _adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++ struct mlme_priv *mlmepriv = &(adapter->mlmepriv);
++ struct mlme_ext_priv *mlmeext = &(adapter->mlmeextpriv);
++ struct mlme_ext_info *mlmeinfo = &(mlmeext->mlmext_info);
++ int ie_len;
++ u8 *ssid_ie;
++ char ssid[NDIS_802_11_LENGTH_SSID + 1];
++ sint ssid_len;
++ u8 ignore_broadcast_ssid;
++
++ if(check_fwstate(mlmepriv, WIFI_AP_STATE) != _TRUE)
++ return -EPERM;
++
++ if (param->u.bcn_ie.reserved[0] != 0xea)
++ return -EINVAL;
++
++ mlmeinfo->hidden_ssid_mode = ignore_broadcast_ssid = param->u.bcn_ie.reserved[1];
++
++ ie_len = len-12-2;// 12 = param header, 2:no packed
++ ssid_ie = rtw_get_ie(param->u.bcn_ie.buf, WLAN_EID_SSID, &ssid_len, ie_len);
++
++ if (ssid_ie && ssid_len) {
++ WLAN_BSSID_EX *pbss_network = &mlmepriv->cur_network.network;
++ WLAN_BSSID_EX *pbss_network_ext = &mlmeinfo->network;
++
++ _rtw_memcpy(ssid, ssid_ie+2, ssid_len);
++ ssid[ssid_len>NDIS_802_11_LENGTH_SSID?NDIS_802_11_LENGTH_SSID:ssid_len] = 0x0;
++
++ if(0)
++ DBG_871X(FUNC_ADPT_FMT" ssid:(%s,%d), from ie:(%s,%d), (%s,%d)\n", FUNC_ADPT_ARG(adapter),
++ ssid, ssid_len,
++ pbss_network->Ssid.Ssid, pbss_network->Ssid.SsidLength,
++ pbss_network_ext->Ssid.Ssid, pbss_network_ext->Ssid.SsidLength);
++
++ _rtw_memcpy(pbss_network->Ssid.Ssid, (void *)ssid, ssid_len);
++ pbss_network->Ssid.SsidLength = ssid_len;
++ _rtw_memcpy(pbss_network_ext->Ssid.Ssid, (void *)ssid, ssid_len);
++ pbss_network_ext->Ssid.SsidLength = ssid_len;
++
++ if(0)
++ DBG_871X(FUNC_ADPT_FMT" after ssid:(%s,%d), (%s,%d)\n", FUNC_ADPT_ARG(adapter),
++ pbss_network->Ssid.Ssid, pbss_network->Ssid.SsidLength,
++ pbss_network_ext->Ssid.Ssid, pbss_network_ext->Ssid.SsidLength);
++ }
++
++ DBG_871X(FUNC_ADPT_FMT" ignore_broadcast_ssid:%d, %s,%d\n", FUNC_ADPT_ARG(adapter),
++ ignore_broadcast_ssid, ssid, ssid_len);
++
++ return ret;
++}
++
++static int rtw_ioctl_acl_remove_sta(struct net_device *dev, struct ieee_param *param, int len)
++{
++ int ret=0;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++
++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE)
++ return -EINVAL;
++
++ if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff &&
++ param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff &&
++ param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff)
++ {
++ return -EINVAL;
++ }
++
++ ret = rtw_acl_remove_sta(padapter, param->sta_addr);
++
++ return ret;
++
++}
++
++static int rtw_ioctl_acl_add_sta(struct net_device *dev, struct ieee_param *param, int len)
++{
++ int ret=0;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++
++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE)
++ return -EINVAL;
++
++ if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff &&
++ param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff &&
++ param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff)
++ {
++ return -EINVAL;
++ }
++
++ ret = rtw_acl_add_sta(padapter, param->sta_addr);
++
++ return ret;
++
++}
++
++static int rtw_ioctl_set_macaddr_acl(struct net_device *dev, struct ieee_param *param, int len)
++{
++ int ret=0;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++
++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE)
++ return -EINVAL;
++
++ rtw_set_macaddr_acl(padapter, param->u.mlme.command);
++
++ return ret;
++}
++
++static int rtw_hostapd_ioctl(struct net_device *dev, struct iw_point *p)
++{
++ struct ieee_param *param;
++ int ret=0;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++
++ //DBG_871X("%s\n", __FUNCTION__);
++
++ /*
++ * this function is expect to call in master mode, which allows no power saving
++ * so, we just check hw_init_completed instead of call rfpwrstate_check()
++ */
++
++ if (padapter->hw_init_completed==_FALSE){
++ ret = -EPERM;
++ goto out;
++ }
++
++
++ //if (p->length < sizeof(struct ieee_param) || !p->pointer){
++ if(!p->pointer){
++ ret = -EINVAL;
++ goto out;
++ }
++
++ param = (struct ieee_param *)rtw_malloc(p->length);
++ if (param == NULL)
++ {
++ ret = -ENOMEM;
++ goto out;
++ }
++
++ if (copy_from_user(param, p->pointer, p->length))
++ {
++ rtw_mfree((u8*)param, p->length);
++ ret = -EFAULT;
++ goto out;
++ }
++
++ //DBG_871X("%s, cmd=%d\n", __FUNCTION__, param->cmd);
++
++ switch (param->cmd)
++ {
++ case RTL871X_HOSTAPD_FLUSH:
++
++ ret = rtw_hostapd_sta_flush(dev);
++
++ break;
++
++ case RTL871X_HOSTAPD_ADD_STA:
++
++ ret = rtw_add_sta(dev, param);
++
++ break;
++
++ case RTL871X_HOSTAPD_REMOVE_STA:
++
++ ret = rtw_del_sta(dev, param);
++
++ break;
++
++ case RTL871X_HOSTAPD_SET_BEACON:
++
++ ret = rtw_set_beacon(dev, param, p->length);
++
++ break;
++
++ case RTL871X_SET_ENCRYPTION:
++
++ ret = rtw_set_encryption(dev, param, p->length);
++
++ break;
++
++ case RTL871X_HOSTAPD_GET_WPAIE_STA:
++
++ ret = rtw_get_sta_wpaie(dev, param);
++
++ break;
++
++ case RTL871X_HOSTAPD_SET_WPS_BEACON:
++
++ ret = rtw_set_wps_beacon(dev, param, p->length);
++
++ break;
++
++ case RTL871X_HOSTAPD_SET_WPS_PROBE_RESP:
++
++ ret = rtw_set_wps_probe_resp(dev, param, p->length);
++
++ break;
++
++ case RTL871X_HOSTAPD_SET_WPS_ASSOC_RESP:
++
++ ret = rtw_set_wps_assoc_resp(dev, param, p->length);
++
++ break;
++
++ case RTL871X_HOSTAPD_SET_HIDDEN_SSID:
++
++ ret = rtw_set_hidden_ssid(dev, param, p->length);
++
++ break;
++
++ case RTL871X_HOSTAPD_GET_INFO_STA:
++
++ ret = rtw_ioctl_get_sta_data(dev, param, p->length);
++
++ break;
++
++ case RTL871X_HOSTAPD_SET_MACADDR_ACL:
++
++ ret = rtw_ioctl_set_macaddr_acl(dev, param, p->length);
++
++ break;
++
++ case RTL871X_HOSTAPD_ACL_ADD_STA:
++
++ ret = rtw_ioctl_acl_add_sta(dev, param, p->length);
++
++ break;
++
++ case RTL871X_HOSTAPD_ACL_REMOVE_STA:
++
++ ret = rtw_ioctl_acl_remove_sta(dev, param, p->length);
++
++ break;
++
++ default:
++ DBG_871X("Unknown hostapd request: %d\n", param->cmd);
++ ret = -EOPNOTSUPP;
++ break;
++
++ }
++
++ if (ret == 0 && copy_to_user(p->pointer, param, p->length))
++ ret = -EFAULT;
++
++
++ rtw_mfree((u8 *)param, p->length);
++
++out:
++
++ return ret;
++
++}
++#endif
++
++#include <rtw_android.h>
++static int rtw_wx_set_priv(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *awrq,
++ char *extra)
++{
++
++#ifdef CONFIG_DEBUG_RTW_WX_SET_PRIV
++ char *ext_dbg;
++#endif
++
++ int ret = 0;
++ int len = 0;
++ char *ext;
++ int i;
++
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct iw_point *dwrq = (struct iw_point*)awrq;
++
++ //RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_notice_, ("+rtw_wx_set_priv\n"));
++ if(dwrq->length == 0)
++ return -EFAULT;
++ len = dwrq->length;
++ if (!(ext = rtw_vmalloc(len)))
++ return -ENOMEM;
++
++ if (copy_from_user(ext, dwrq->pointer, len)) {
++ rtw_vmfree(ext, len);
++ return -EFAULT;
++ }
++
++
++ //RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_notice_,
++ // ("rtw_wx_set_priv: %s req=%s\n",
++ // dev->name, ext));
++
++ #ifdef CONFIG_DEBUG_RTW_WX_SET_PRIV
++ if (!(ext_dbg = rtw_vmalloc(len)))
++ {
++ rtw_vmfree(ext, len);
++ return -ENOMEM;
++ }
++
++ _rtw_memcpy(ext_dbg, ext, len);
++ #endif
++
++ //added for wps2.0 @20110524
++ if(dwrq->flags == 0x8766 && len > 8)
++ {
++ u32 cp_sz;
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ u8 *probereq_wpsie = ext;
++ int probereq_wpsie_len = len;
++ u8 wps_oui[4]={0x0,0x50,0xf2,0x04};
++
++ if((_VENDOR_SPECIFIC_IE_ == probereq_wpsie[0]) &&
++ (_rtw_memcmp(&probereq_wpsie[2], wps_oui, 4) ==_TRUE))
++ {
++ cp_sz = probereq_wpsie_len>MAX_WPS_IE_LEN ? MAX_WPS_IE_LEN:probereq_wpsie_len;
++
++ //_rtw_memcpy(pmlmepriv->probereq_wpsie, probereq_wpsie, cp_sz);
++ //pmlmepriv->probereq_wpsie_len = cp_sz;
++
++ printk("probe_req_wps_ielen=%d\n", cp_sz);
++
++ if(pmlmepriv->wps_probe_req_ie)
++ {
++ u32 free_len = pmlmepriv->wps_probe_req_ie_len;
++ pmlmepriv->wps_probe_req_ie_len = 0;
++ rtw_mfree(pmlmepriv->wps_probe_req_ie, free_len);
++ pmlmepriv->wps_probe_req_ie = NULL;
++ }
++
++ pmlmepriv->wps_probe_req_ie = rtw_malloc(cp_sz);
++ if ( pmlmepriv->wps_probe_req_ie == NULL) {
++ printk("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__);
++ ret = -EINVAL;
++ goto FREE_EXT;
++
++ }
++
++ _rtw_memcpy(pmlmepriv->wps_probe_req_ie, probereq_wpsie, cp_sz);
++ pmlmepriv->wps_probe_req_ie_len = cp_sz;
++
++ }
++
++ goto FREE_EXT;
++
++ }
++
++ if( len >= WEXT_CSCAN_HEADER_SIZE
++ && _rtw_memcmp(ext, WEXT_CSCAN_HEADER, WEXT_CSCAN_HEADER_SIZE) == _TRUE
++ ){
++ ret = rtw_wx_set_scan(dev, info, awrq, ext);
++ goto FREE_EXT;
++ }
++
++#ifdef CONFIG_ANDROID
++ //DBG_871X("rtw_wx_set_priv: %s req=%s\n", dev->name, ext);
++
++ i = rtw_android_cmdstr_to_num(ext);
++
++ switch(i) {
++ case ANDROID_WIFI_CMD_START :
++ indicate_wx_custom_event(padapter, "START");
++ break;
++ case ANDROID_WIFI_CMD_STOP :
++ indicate_wx_custom_event(padapter, "STOP");
++ break;
++ case ANDROID_WIFI_CMD_RSSI :
++ {
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ struct wlan_network *pcur_network = &pmlmepriv->cur_network;
++
++ if(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) {
++ sprintf(ext, "%s rssi %d", pcur_network->network.Ssid.Ssid, padapter->recvpriv.rssi);
++ } else {
++ sprintf(ext, "OK");
++ }
++ }
++ break;
++ case ANDROID_WIFI_CMD_LINKSPEED :
++ {
++ u16 mbps = rtw_get_cur_max_rate(padapter)/10;
++ sprintf(ext, "LINKSPEED %d", mbps);
++ }
++ break;
++ case ANDROID_WIFI_CMD_MACADDR :
++ sprintf(ext, "MACADDR = " MAC_FMT, MAC_ARG(dev->dev_addr));
++ break;
++ case ANDROID_WIFI_CMD_SCAN_ACTIVE :
++ {
++ //rtw_set_scan_mode(padapter, SCAN_ACTIVE);
++ sprintf(ext, "OK");
++ }
++ break;
++ case ANDROID_WIFI_CMD_SCAN_PASSIVE :
++ {
++ //rtw_set_scan_mode(padapter, SCAN_PASSIVE);
++ sprintf(ext, "OK");
++ }
++ break;
++
++ case ANDROID_WIFI_CMD_COUNTRY :
++ {
++ char country_code[10];
++ sscanf(ext, "%*s %s", country_code);
++ rtw_set_country(padapter, country_code);
++ sprintf(ext, "OK");
++ }
++ break;
++ default :
++ #ifdef CONFIG_DEBUG_RTW_WX_SET_PRIV
++ DBG_871X("%s: %s unknowned req=%s\n", __FUNCTION__,
++ dev->name, ext_dbg);
++ #endif
++
++ sprintf(ext, "OK");
++
++ }
++
++ if (copy_to_user(dwrq->pointer, ext, min(dwrq->length, (u16)(strlen(ext)+1)) ) )
++ ret = -EFAULT;
++
++ #ifdef CONFIG_DEBUG_RTW_WX_SET_PRIV
++ DBG_871X("%s: %s req=%s rep=%s dwrq->length=%d, strlen(ext)+1=%d\n", __FUNCTION__,
++ dev->name, ext_dbg ,ext, dwrq->length, (u16)(strlen(ext)+1));
++ #endif
++#endif //end of CONFIG_ANDROID
++
++
++FREE_EXT:
++
++ rtw_vmfree(ext, len);
++ #ifdef CONFIG_DEBUG_RTW_WX_SET_PRIV
++ rtw_vmfree(ext_dbg, len);
++ #endif
++
++ //DBG_871X("rtw_wx_set_priv: (SIOCSIWPRIV) %s ret=%d\n",
++ // dev->name, ret);
++
++ return ret;
++
++}
++
++static int rtw_mp_efuse_get(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wdata, char *extra)
++{
++ struct iw_point *wrqu = (struct iw_point *)wdata;
++ PADAPTER padapter = rtw_netdev_priv(dev);
++ struct mp_priv *pmp_priv;
++
++ int i,j =0;
++ u8 data[EFUSE_MAP_SIZE];
++ u8 rawdata[EFUSE_MAX_SIZE];
++ u16 mapLen=0;
++ char *pch, *ptmp, *token, *tmp[3]={0x00,0x00,0x00};
++ u16 addr = 0, cnts = 0, max_available_size = 0,raw_cursize = 0 ,raw_maxsize = 0;
++
++ _rtw_memset(data, '\0', sizeof(data));
++ _rtw_memset(rawdata, '\0', sizeof(rawdata));
++
++ if (copy_from_user(extra, wrqu->pointer, wrqu->length))
++ return -EFAULT;
++
++ pch = extra;
++ DBG_871X("%s: in=%s\n", __func__, extra);
++
++ i=0;
++ //mac 16 "00e04c871200" rmap,00,2
++ while ( (token = strsep (&pch,",") )!=NULL )
++ {
++ if(i>2) break;
++ tmp[i] = token;
++ i++;
++ }
++
++ if ( strcmp(tmp[0],"realmap") == 0 ) {
++
++ DBG_871X("strcmp OK = %s \n" ,tmp[0]);
++
++ mapLen = EFUSE_MAP_SIZE;
++
++ if (rtw_efuse_map_read(padapter, 0, mapLen, data) == _SUCCESS){
++ DBG_871X("\t rtw_efuse_map_read \n");
++ }else {
++ DBG_871X("\t rtw_efuse_map_read : Fail \n");
++ return -EFAULT;
++ }
++ _rtw_memset(extra, '\0', sizeof(extra));
++ DBG_871X("\tOFFSET\tVALUE(hex)\n");
++ sprintf(extra, "%s \n", extra);
++ for ( i = 0; i < EFUSE_MAP_SIZE; i += 16 )
++ {
++ DBG_871X("\t0x%02x\t", i);
++ sprintf(extra, "%s \t0x%02x\t", extra,i);
++ for (j = 0; j < 8; j++)
++ {
++ DBG_871X("%02X ", data[i+j]);
++ sprintf(extra, "%s %02X", extra, data[i+j]);
++ }
++ DBG_871X("\t");
++ sprintf(extra,"%s\t",extra);
++ for (; j < 16; j++){
++ DBG_871X("%02X ", data[i+j]);
++ sprintf(extra, "%s %02X", extra, data[i+j]);
++ }
++ DBG_871X("\n");
++ sprintf(extra,"%s\n",extra);
++ }
++ DBG_871X("\n");
++ wrqu->length = strlen(extra);
++
++ return 0;
++ }
++ else if ( strcmp(tmp[0],"rmap") == 0 ) {
++ if ( tmp[1]==NULL || tmp[2]==NULL ) return -EINVAL;
++ // rmap addr cnts
++ addr = simple_strtoul(tmp[1], &ptmp, 16);
++
++ DBG_871X("addr = %x \n" ,addr);
++
++ cnts=simple_strtoul(tmp[2], &ptmp,10);
++ if(cnts==0) return -EINVAL;
++
++ DBG_871X("cnts = %d \n" ,cnts);
++ //_rtw_memset(extra, '\0', wrqu->data.length);
++
++ EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, (PVOID)&max_available_size, _FALSE);
++ if ((addr + cnts) > max_available_size) {
++ DBG_871X("(addr + cnts parameter error \n");
++ return -EFAULT;
++ }
++
++ if (rtw_efuse_map_read(padapter, addr, cnts, data) == _FAIL)
++ {
++ DBG_871X("rtw_efuse_access error \n");
++ }
++ else{
++ DBG_871X("rtw_efuse_access ok \n");
++ }
++
++ _rtw_memset(extra, '\0', sizeof(extra));
++ for ( i = 0; i < cnts; i ++) {
++ DBG_871X("0x%02x", data[i]);
++ sprintf(extra, "%s 0x%02X", extra, data[i]);
++ DBG_871X(" ");
++ sprintf(extra,"%s ",extra);
++ }
++
++ wrqu->length = strlen(extra)+1;
++
++ DBG_871X("extra = %s ", extra);
++
++ return 0;
++ }
++ else if ( strcmp(tmp[0],"realraw") == 0 ) {
++ addr=0;
++ mapLen = EFUSE_MAX_SIZE;
++
++ if (rtw_efuse_access(padapter, _FALSE, addr, mapLen, rawdata) == _FAIL)
++ {
++ DBG_871X("\t rtw_efuse_map_read : Fail \n");
++ return -EFAULT;
++ } else
++ {
++ DBG_871X("\t rtw_efuse_access raw ok \n");
++ }
++
++ _rtw_memset(extra, '\0', sizeof(extra));
++ for ( i=0; i<mapLen; i++ ) {
++ DBG_871X(" %02x", rawdata[i]);
++ sprintf(extra, "%s %02x", extra, rawdata[i] );
++
++ if ((i & 0xF) == 0xF){
++ DBG_871X("\n\t");
++ sprintf(extra, "%s\n\t", extra);
++ }
++ else if ((i & 0x7) == 0x7){
++ DBG_871X("\t");
++ sprintf(extra, "%s\t", extra);
++ }
++ }
++ wrqu->length = strlen(extra);
++ return 0;
++ }
++ else if ( strcmp(tmp[0],"mac") == 0 ) {
++ if ( tmp[1]==NULL || tmp[2]==NULL ) return -EINVAL;
++ #ifdef CONFIG_RTL8192C
++ addr = 0x16;
++ cnts = 6;
++ #endif
++ #ifdef CONFIG_RTL8192D
++ addr = 0x19;
++ cnts = 6;
++ #endif
++ EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, (PVOID)&max_available_size, _FALSE);
++ if ((addr + mapLen) > max_available_size) {
++ DBG_871X("(addr + cnts parameter error \n");
++ return -EFAULT;
++ }
++ if (rtw_efuse_map_read(padapter, addr, cnts, data) == _FAIL)
++ {
++ DBG_871X("rtw_efuse_access error \n");
++ }
++ else{
++ DBG_871X("rtw_efuse_access ok \n");
++ }
++ _rtw_memset(extra, '\0', sizeof(extra));
++ for ( i = 0; i < cnts; i ++) {
++ DBG_871X("0x%02x", data[i]);
++ sprintf(extra, "%s 0x%02X", extra, data[i+j]);
++ DBG_871X(" ");
++ sprintf(extra,"%s ",extra);
++ }
++ wrqu->length = strlen(extra);
++ return 0;
++ }
++ else if ( strcmp(tmp[0],"vidpid") == 0 ) {
++ if ( tmp[1]==NULL || tmp[2]==NULL ) return -EINVAL;
++ #ifdef CONFIG_RTL8192C
++ addr=0x0a;
++ #endif
++ #ifdef CONFIG_RTL8192D
++ addr = 0x0c;
++ #endif
++ cnts = 4;
++ EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, (PVOID)&max_available_size, _FALSE);
++ if ((addr + mapLen) > max_available_size) {
++ DBG_871X("(addr + cnts parameter error \n");
++ return -EFAULT;
++ }
++ if (rtw_efuse_map_read(padapter, addr, cnts, data) == _FAIL)
++ {
++ DBG_871X("rtw_efuse_access error \n");
++ }
++ else{
++ DBG_871X("rtw_efuse_access ok \n");
++ }
++ _rtw_memset(extra, '\0', sizeof(extra));
++ for ( i = 0; i < cnts; i ++) {
++ DBG_871X("0x%02x", data[i]);
++ sprintf(extra, "%s 0x%02X", extra, data[i+j]);
++ DBG_871X(" ");
++ sprintf(extra,"%s ",extra);
++ }
++ wrqu->length = strlen(extra);
++ return 0;
++ }
++ else if ( strcmp(tmp[0],"ableraw") == 0 ) {
++ efuse_GetCurrentSize(padapter,&raw_cursize);
++ raw_maxsize = efuse_GetMaxSize(padapter);
++ sprintf(extra, "%s : [ available raw size] = %d",extra,raw_maxsize-raw_cursize);
++ wrqu->length = strlen(extra);
++
++ return 0;
++ }else
++ {
++ sprintf(extra, "%s : Command not found\n",extra);
++ wrqu->length = strlen(extra);
++ return 0;
++ }
++
++ return 0;
++}
++
++static int rtw_mp_efuse_set(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wdata, char *extra)
++{
++ struct iw_point *wrqu = (struct iw_point *)wdata;
++ PADAPTER padapter = rtw_netdev_priv(dev);
++
++ u8 buffer[40];
++ u32 i,jj,kk;
++ u8 setdata[EFUSE_MAP_SIZE];
++ u8 setrawdata[EFUSE_MAX_SIZE];
++ char *pch, *ptmp, *token, *edata,*tmp[3]={0x00,0x00,0x00};
++
++ u16 addr = 0, max_available_size = 0;
++ u32 cnts = 0;
++
++ pch = extra;
++ DBG_871X("%s: in=%s\n", __func__, extra);
++
++ i=0;
++ while ( (token = strsep (&pch,",") )!=NULL )
++ {
++ if(i>2) break;
++ tmp[i] = token;
++ i++;
++ }
++
++ // tmp[0],[1],[2]
++ // wmap,addr,00e04c871200
++ if ( strcmp(tmp[0],"wmap") == 0 ) {
++ if ( tmp[1]==NULL || tmp[2]==NULL ) return -EINVAL;
++ if ( ! strlen( tmp[2] )/2 > 1 ) return -EFAULT;
++
++ addr = simple_strtoul( tmp[1], &ptmp, 16 );
++ addr = addr & 0xFF;
++ DBG_871X("addr = %x \n" ,addr);
++
++ cnts = strlen( tmp[2] )/2;
++ if ( cnts == 0) return -EFAULT;
++
++ DBG_871X("cnts = %d \n" ,cnts);
++ DBG_871X("target data = %s \n" ,tmp[2]);
++
++ for( jj = 0, kk = 0; jj < cnts; jj++, kk += 2 )
++ {
++ setdata[jj] = key_2char2num( tmp[2][kk], tmp[2][kk+ 1] );
++ }
++
++ EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, (PVOID)&max_available_size, _FALSE);
++
++ if ((addr + cnts) > max_available_size) {
++ DBG_871X("parameter error \n");
++ return -EFAULT;
++ }
++ if (rtw_efuse_map_write(padapter, addr, cnts, setdata) == _FAIL) {
++ DBG_871X("rtw_efuse_map_write error \n");
++ return -EFAULT;
++ } else
++ DBG_871X("rtw_efuse_map_write ok \n");
++
++ return 0;
++ }
++ else if ( strcmp(tmp[0],"wraw") == 0 ) {
++ if ( tmp[1]==NULL || tmp[2]==NULL ) return -EINVAL;
++ if ( ! strlen( tmp[2] )/2 > 1 ) return -EFAULT;
++ addr = simple_strtoul( tmp[1], &ptmp, 16 );
++ addr = addr & 0xFF;
++ DBG_871X("addr = %x \n" ,addr);
++
++ cnts=strlen( tmp[2] )/2;
++ if ( cnts == 0) return -EFAULT;
++
++ DBG_871X(" cnts = %d \n" ,cnts );
++ DBG_871X("target data = %s \n" ,tmp[2] );
++
++ for( jj = 0, kk = 0; jj < cnts; jj++, kk += 2 )
++ {
++ setrawdata[jj] = key_2char2num( tmp[2][kk], tmp[2][kk+ 1] );
++ }
++
++ if ( rtw_efuse_access( padapter, _TRUE, addr, cnts, setrawdata ) == _FAIL ){
++ DBG_871X("\t rtw_efuse_map_read : Fail \n");
++ return -EFAULT;
++ } else
++ DBG_871X("\t rtw_efuse_access raw ok \n");
++
++ return 0;
++ }
++ else if ( strcmp(tmp[0],"mac") == 0 ) {
++ if ( tmp[1]==NULL || tmp[2]==NULL ) return -EINVAL;
++ //mac,00e04c871200
++ #ifdef CONFIG_RTL8192C
++ addr = 0x16;
++ #endif
++ #ifdef CONFIG_RTL8192D
++ addr = 0x19;
++ #endif
++ cnts = strlen( tmp[1] )/2;
++ if ( cnts == 0) return -EFAULT;
++ if ( cnts > 6 ){
++ DBG_871X("error data for mac addr = %s \n" ,tmp[1]);
++ return -EFAULT;
++ }
++
++ DBG_871X("target data = %s \n" ,tmp[1]);
++
++ for( jj = 0, kk = 0; jj < cnts; jj++, kk += 2 )
++ {
++ setdata[jj] = key_2char2num(tmp[1][kk], tmp[1][kk+ 1]);
++ }
++
++ EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, (PVOID)&max_available_size, _FALSE);
++
++ if ((addr + cnts) > max_available_size) {
++ DBG_871X("parameter error \n");
++ return -EFAULT;
++ }
++ if ( rtw_efuse_map_write(padapter, addr, cnts, setdata) == _FAIL ) {
++ DBG_871X("rtw_efuse_map_write error \n");
++ return -EFAULT;
++ } else
++ DBG_871X("rtw_efuse_map_write ok \n");
++
++ return 0;
++ }
++ else if ( strcmp(tmp[0],"vidpid") == 0 ) {
++ if ( tmp[1]==NULL || tmp[2]==NULL ) return -EINVAL;
++ // pidvid,da0b7881
++ #ifdef CONFIG_RTL8192C
++ addr=0x0a;
++ #endif
++ #ifdef CONFIG_RTL8192D
++ addr = 0x0c;
++ #endif
++
++ cnts=strlen( tmp[1] )/2;
++ if ( cnts == 0) return -EFAULT;
++ DBG_871X("target data = %s \n" ,tmp[1]);
++
++ for( jj = 0, kk = 0; jj < cnts; jj++, kk += 2 )
++ {
++ setdata[jj] = key_2char2num(tmp[1][kk], tmp[1][kk+ 1]);
++ }
++
++ EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, (PVOID)&max_available_size, _FALSE);
++
++ if ((addr + cnts) > max_available_size) {
++ DBG_871X("parameter error \n");
++ return -EFAULT;
++ }
++
++ if ( rtw_efuse_map_write(padapter, addr, cnts, setdata) == _FAIL ) {
++ DBG_871X("rtw_efuse_map_write error \n");
++ return -EFAULT;
++ } else
++ DBG_871X("rtw_efuse_map_write ok \n");
++
++ return 0;
++ }
++ else{
++ DBG_871X("Command not found\n");
++ return 0;
++ }
++
++ return 0;
++}
++
++
++
++#if defined(CONFIG_MP_INCLUDED) && defined(CONFIG_MP_IWPRIV_SUPPORT)
++
++/*
++ * Input Format: %s,%d,%d
++ * %s is width, could be
++ * "b" for 1 byte
++ * "w" for WORD (2 bytes)
++ * "dw" for DWORD (4 bytes)
++ * 1st %d is address(offset)
++ * 2st %d is data to write
++ */
++static int rtw_mp_write_reg(struct net_device *dev,
++ struct iw_request_info *info,
++ struct iw_point *wrqu, char *extra)
++{
++ char *pch, *pnext, *ptmp;
++ char *width_str;
++ char width;
++ u32 addr, data;
++ int ret;
++ PADAPTER padapter = rtw_netdev_priv(dev);
++
++
++ pch = extra;
++ pnext = strpbrk(pch, " ,.-");
++ if (pnext == NULL) return -EINVAL;
++ *pnext = 0;
++ width_str = pch;
++
++ pch = pnext + 1;
++ pnext = strpbrk(pch, " ,.-");
++ if (pnext == NULL) return -EINVAL;
++ *pnext = 0;
++ addr = simple_strtoul(pch, &ptmp, 16);
++ if (addr > 0x3FFF) return -EINVAL;
++
++ pch = pnext + 1;
++ if ((pch - extra) >= wrqu->length) return -EINVAL;
++ data = simple_strtoul(pch, &ptmp, 16);
++
++ ret = 0;
++ width = width_str[0];
++ switch (width) {
++ case 'b':
++ // 1 byte
++ if (data > 0xFF) {
++ ret = -EINVAL;
++ break;
++ }
++ rtw_write8(padapter, addr, data);
++ break;
++ case 'w':
++ // 2 bytes
++ if (data > 0xFFFF) {
++ ret = -EINVAL;
++ break;
++ }
++ rtw_write16(padapter, addr, data);
++ break;
++ case 'd':
++ // 4 bytes
++ rtw_write32(padapter, addr, data);
++ break;
++ default:
++ ret = -EINVAL;
++ break;
++ }
++
++ return ret;
++}
++
++/*
++ * Input Format: %s,%d
++ * %s is width, could be
++ * "b" for 1 byte
++ * "w" for WORD (2 bytes)
++ * "dw" for DWORD (4 bytes)
++ * %d is address(offset)
++ *
++ * Return:
++ * %d for data readed
++ */
++static int rtw_mp_read_reg(struct net_device *dev,
++ struct iw_request_info *info,
++ struct iw_point *wrqu, char *extra)
++{
++ char input[wrqu->length];
++ char *pch, *pnext, *ptmp;
++ char *width_str;
++ char width;
++ char data[20],tmp[20];
++ u32 addr;
++ //u32 *data = (u32*)extra;
++ u32 ret, i=0, j=0, strtout=0;
++ PADAPTER padapter = rtw_netdev_priv(dev);
++
++ if (wrqu->length > 128) return -EFAULT;
++
++ if (copy_from_user(input, wrqu->pointer, wrqu->length))
++ return -EFAULT;
++
++ _rtw_memset(data, 0, 20);
++ _rtw_memset(tmp, 0, 20);
++ _rtw_memset(extra, 0, wrqu->length);
++
++ pch = input;
++ pnext = strpbrk(pch, " ,.-");
++ if (pnext == NULL) return -EINVAL;
++ *pnext = 0;
++ width_str = pch;
++
++ pch = pnext + 1;
++ if ((pch - input) >= wrqu->length) return -EINVAL;
++
++ addr = simple_strtoul(pch, &ptmp, 16);
++ if (addr > 0x3FFF) return -EINVAL;
++
++ ret = 0;
++ width = width_str[0];
++ switch (width) {
++ case 'b':
++ // 1 byte
++ // *(u8*)data = rtw_read8(padapter, addr);
++ sprintf(extra, "%d\n", rtw_read8(padapter, addr));
++ wrqu->length = strlen(extra);
++ break;
++ case 'w':
++ // 2 bytes
++ //*(u16*)data = rtw_read16(padapter, addr);
++ sprintf(data, "%04d\n", rtw_read16(padapter, addr));
++ for( i=0 ; i <= strlen(data) ; i++)
++ {
++ if( i%2==0 )
++ {
++ tmp[j]=' ';
++ j++;
++ }
++ if ( data[i] != '\0' )
++ tmp[j] = data[i];
++
++ j++;
++ }
++ pch = tmp;
++ DBG_871X("pch=%s",pch);
++
++ while( *pch != '\0' )
++ {
++ pnext = strpbrk(pch, " ");
++ pnext++;
++ if ( *pnext != '\0' )
++ {
++ strtout = simple_strtoul (pnext , &ptmp, 16);
++ sprintf( extra, "%s %d" ,extra ,strtout );
++ }
++ else{
++ break;
++ }
++ pch = pnext;
++ }
++ wrqu->length = 6;
++ break;
++ case 'd':
++ // 4 bytes
++ //*data = rtw_read32(padapter, addr);
++ sprintf(data, "%08x", rtw_read32(padapter, addr));
++ //add read data format blank
++ for( i=0 ; i <= strlen(data) ; i++)
++ {
++ if( i%2==0 )
++ {
++ tmp[j]=' ';
++ j++;
++ }
++ tmp[j] = data[i];
++ j++;
++ }
++ pch = tmp;
++ DBG_871X("pch=%s",pch);
++
++ while( *pch != '\0' )
++ {
++ pnext = strpbrk(pch, " ");
++ pnext++;
++ if ( *pnext != '\0' )
++ {
++ strtout = simple_strtoul (pnext , &ptmp, 16);
++ sprintf( extra, "%s %d" ,extra ,strtout );
++ }
++ else{
++ break;
++ }
++ pch = pnext;
++ }
++ wrqu->length = strlen(extra);
++ break;
++
++ default:
++ wrqu->length = 0;
++ ret = -EINVAL;
++ break;
++
++ }
++
++ return ret;
++}
++
++/*
++ * Input Format: %d,%x,%x
++ * %d is RF path, should be smaller than MAX_RF_PATH_NUMS
++ * 1st %x is address(offset)
++ * 2st %x is data to write
++ */
++ static int rtw_mp_write_rf(struct net_device *dev,
++ struct iw_request_info *info,
++ struct iw_point *wrqu, char *extra)
++{
++/*static int rtw_mp_write_rf(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++*/
++ u32 path, addr, data;
++ int ret;
++ PADAPTER padapter = rtw_netdev_priv(dev);
++
++
++ ret = sscanf(extra, "%d,%x,%x", &path, &addr, &data);
++ if (ret < 3) return -EINVAL;
++
++ if (path >= MAX_RF_PATH_NUMS) return -EINVAL;
++ if (addr > 0xFF) return -EINVAL;
++ if (data > 0xFFFFF) return -EINVAL;
++ _rtw_memset(extra, 0, wrqu->length);
++
++ write_rfreg(padapter, path, addr, data);
++
++ sprintf(extra, "write_rf completed \n");
++
++ return 0;
++}
++
++/*
++ * Input Format: %d,%x
++ * %d is RF path, should be smaller than MAX_RF_PATH_NUMS
++ * %x is address(offset)
++ *
++ * Return:
++ * %d for data readed
++ */
++static int rtw_mp_read_rf(struct net_device *dev,
++ struct iw_request_info *info,
++ struct iw_point *wrqu, char *extra)
++{
++ char input[wrqu->length];
++ char *pch, *pnext, *ptmp;
++ char data[20],tmp[20];
++ //u32 *data = (u32*)extra;
++ u32 path, addr;
++ u32 ret,i=0 ,j=0,strtou=0;
++ PADAPTER padapter = rtw_netdev_priv(dev);
++
++
++ if (wrqu->length > 128) return -EFAULT;
++ if (copy_from_user(input, wrqu->pointer, wrqu->length))
++ return -EFAULT;
++
++ ret = sscanf(input, "%d,%x", &path, &addr);
++ if (ret < 2) return -EINVAL;
++
++ if (path >= MAX_RF_PATH_NUMS) return -EINVAL;
++ if (addr > 0xFF) return -EINVAL;
++
++ _rtw_memset(extra, 0, wrqu->length);
++
++ //*data = read_rfreg(padapter, path, addr);
++ sprintf(data, "%08x", read_rfreg(padapter, path, addr));
++ //add read data format blank
++ for( i=0 ; i <= strlen(data) ; i++)
++ {
++ if( i%2==0 )
++ {
++ tmp[j]=' ';
++ j++;
++ }
++ tmp[j] = data[i];
++ j++;
++ }
++ pch = tmp;
++ DBG_871X("pch=%s",pch);
++
++ while( *pch != '\0' )
++ {
++ pnext = strpbrk(pch, " ");
++ pnext++;
++ if ( *pnext != '\0' )
++ {
++ strtou = simple_strtoul (pnext , &ptmp, 16);
++ sprintf( extra, "%s %d" ,extra ,strtou );
++ }
++ else{
++ break;
++ }
++ pch = pnext;
++ }
++ wrqu->length = strlen(extra);
++
++ return 0;
++}
++
++static int rtw_mp_start(struct net_device *dev,
++ struct iw_request_info *info,
++ struct iw_point *wrqu, char *extra)
++{
++ u8 val8;
++ PADAPTER padapter = rtw_netdev_priv(dev);
++
++
++ if (padapter->registrypriv.mp_mode == 0)
++ return -EPERM;
++
++ if (padapter->mppriv.mode == MP_OFF) {
++ if (mp_start_test(padapter) == _FAIL)
++ return -EPERM;
++ padapter->mppriv.mode = MP_ON;
++ }
++
++ return 0;
++}
++
++static int rtw_mp_stop(struct net_device *dev,
++ struct iw_request_info *info,
++ struct iw_point *wrqu, char *extra)
++{
++ PADAPTER padapter = rtw_netdev_priv(dev);
++
++
++ if (padapter->mppriv.mode != MP_OFF) {
++ mp_stop_test(padapter);
++ padapter->mppriv.mode = MP_OFF;
++ }
++
++ return 0;
++}
++
++extern int wifirate2_ratetbl_inx(unsigned char rate);
++
++static int rtw_mp_rate(struct net_device *dev,
++ struct iw_request_info *info,
++ struct iw_point *wrqu, char *extra)
++{
++ u32 rate = MPT_RATE_1M;
++ u8 input[wrqu->length];
++ PADAPTER padapter = rtw_netdev_priv(dev);
++
++ if (copy_from_user(input, wrqu->pointer, wrqu->length))
++ return -EFAULT;
++
++ rate = rtw_atoi(input);
++ sprintf( extra, "Set data rate to %d" , rate );
++
++ if(rate <= 0x7f)
++ rate = wifirate2_ratetbl_inx( (u8)rate);
++ else
++ rate =(rate-0x80+MPT_RATE_MCS0);
++
++ //DBG_871X("%s: rate=%d\n", __func__, rate);
++
++ if (rate >= MPT_RATE_LAST )
++ return -EINVAL;
++
++ padapter->mppriv.rateidx = rate;
++ Hal_SetDataRate(padapter);
++
++ wrqu->length = strlen(extra) + 1;
++ return 0;
++}
++
++static int rtw_mp_channel(struct net_device *dev,
++ struct iw_request_info *info,
++ struct iw_point *wrqu, char *extra)
++{
++
++ PADAPTER padapter = rtw_netdev_priv(dev);
++ u8 input[wrqu->length];
++ u32 channel = 1;
++
++ if (copy_from_user(input, wrqu->pointer, wrqu->length))
++ return -EFAULT;
++
++ channel = rtw_atoi(input);
++ //DBG_871X("%s: channel=%d\n", __func__, channel);
++ sprintf( extra, "Change channel %d to channel %d", padapter->mppriv.channel , channel );
++
++ padapter->mppriv.channel = channel;
++ Hal_SetChannel(padapter);
++
++ wrqu->length = strlen(extra) + 1;
++ return 0;
++}
++
++static int rtw_mp_bandwidth(struct net_device *dev,
++ struct iw_request_info *info,
++ struct iw_point *wrqu, char *extra)
++{
++ u32 bandwidth=0, sg=0;
++ //u8 buffer[40];
++ PADAPTER padapter = rtw_netdev_priv(dev);
++ //if (copy_from_user(buffer, (void*)wrqu->data.pointer, wrqu->data.length))
++ // return -EFAULT;
++
++ //DBG_871X("%s:iwpriv in=%s\n", __func__, extra);
++
++ sscanf(extra, "40M=%d,shortGI=%d", &bandwidth, &sg);
++
++ if (bandwidth != HT_CHANNEL_WIDTH_40)
++ bandwidth = HT_CHANNEL_WIDTH_20;
++
++ //DBG_871X("%s: bw=%d sg=%d \n", __func__, bandwidth , sg);
++
++ padapter->mppriv.bandwidth = (u8)bandwidth;
++ padapter->mppriv.preamble = sg;
++
++ SetBandwidth(padapter);
++
++ return 0;
++}
++
++static int rtw_mp_txpower(struct net_device *dev,
++ struct iw_request_info *info,
++ struct iw_point *wrqu, char *extra)
++{
++ u32 idx_a=0,idx_b=0;
++ u8 input[wrqu->length];
++
++ PADAPTER padapter = rtw_netdev_priv(dev);
++
++ if (copy_from_user(input, wrqu->pointer, wrqu->length))
++ return -EFAULT;
++
++ sscanf(input,"patha=%d,pathb=%d",&idx_a,&idx_b);
++ //DBG_871X("%s: tx_pwr_idx_a=%x b=%x\n", __func__, idx_a, idx_b);
++
++ sprintf( extra, "Set power level path_A:%d path_B:%d", idx_a , idx_b );
++ padapter->mppriv.txpoweridx = (u8)idx_a;
++ padapter->mppriv.txpoweridx_b = (u8)idx_b;
++
++ Hal_SetAntennaPathPower(padapter);
++
++ wrqu->length = strlen(extra) + 1;
++ return 0;
++}
++
++static int rtw_mp_ant_tx(struct net_device *dev,
++ struct iw_request_info *info,
++ struct iw_point *wrqu, char *extra)
++{
++ u8 i;
++ u8 input[wrqu->length];
++ u16 antenna = 0;
++ PADAPTER padapter = rtw_netdev_priv(dev);
++
++ if (copy_from_user(input, wrqu->pointer, wrqu->length))
++ return -EFAULT;
++
++ //DBG_871X("%s: input=%s\n", __func__, input);
++
++ sprintf( extra, "switch Tx antenna to %s", input );
++
++ for (i=0; i < strlen(input); i++)
++ {
++ switch(input[i])
++ {
++ case 'a' :
++ antenna|=ANTENNA_A;
++ break;
++ case 'b':
++ antenna|=ANTENNA_B;
++ break;
++ }
++ }
++ //antenna |= BIT(extra[i]-'a');
++ //DBG_871X("%s: antenna=0x%x\n", __func__, antenna);
++ padapter->mppriv.antenna_tx = antenna;
++ //DBG_871X("%s:mppriv.antenna_rx=%d\n", __func__, padapter->mppriv.antenna_tx);
++
++ Hal_SetAntenna(padapter);
++
++ wrqu->length = strlen(extra) + 1;
++ return 0;
++}
++
++static int rtw_mp_ant_rx(struct net_device *dev,
++ struct iw_request_info *info,
++ struct iw_point *wrqu, char *extra)
++{
++ u8 i;
++ u16 antenna = 0;
++ u8 input[wrqu->length];
++ PADAPTER padapter = rtw_netdev_priv(dev);
++
++ if (copy_from_user(input, wrqu->pointer, wrqu->length))
++ return -EFAULT;
++ //DBG_871X("%s: input=%s\n", __func__, input);
++ _rtw_memset(extra, 0, wrqu->length);
++
++ sprintf( extra, "switch Rx antenna to %s", input );
++
++ for (i=0; i < strlen(input); i++) {
++
++ switch( input[i] )
++ {
++ case 'a' :
++ antenna|=ANTENNA_A;
++ break;
++ case 'b':
++ antenna|=ANTENNA_B;
++ break;
++ }
++ }
++
++ //DBG_871X("%s: antenna=0x%x\n", __func__, antenna);
++ padapter->mppriv.antenna_rx = antenna;
++ //DBG_871X("%s:mppriv.antenna_rx=%d\n", __func__, padapter->mppriv.antenna_rx);
++ Hal_SetAntenna(padapter);
++ wrqu->length = strlen(extra);
++
++ return 0;
++}
++
++static int rtw_mp_ctx(struct net_device *dev,
++ struct iw_request_info *info,
++ struct iw_point *wrqu, char *extra)
++{
++ u32 pkTx = 1, countPkTx = 1, cotuTx = 1, CarrSprTx = 1, scTx = 1, sgleTx = 1, stop = 1;
++ u32 bStartTest = 1;
++ u32 count = 0;
++ struct mp_priv *pmp_priv;
++ struct pkt_attrib *pattrib;
++
++ PADAPTER padapter = rtw_netdev_priv(dev);
++
++
++ pmp_priv = &padapter->mppriv;
++
++ if (copy_from_user(extra, wrqu->pointer, wrqu->length))
++ return -EFAULT;
++
++ DBG_871X("%s: in=%s\n", __func__, extra);
++
++ countPkTx = strncmp(extra, "count=", 5); // strncmp TRUE is 0
++ cotuTx = strncmp(extra, "background", 20);
++ CarrSprTx = strncmp(extra, "background,cs", 20);
++ scTx = strncmp(extra, "background,sc", 20);
++ sgleTx = strncmp(extra, "background,stone", 20);
++ pkTx = strncmp(extra, "background,pkt", 20);
++ stop = strncmp(extra, "stop", 5);
++ sscanf(extra, "count=%d,pkt", &count);
++
++ //DBG_871X("%s: count=%d countPkTx=%d cotuTx=%d CarrSprTx=%d scTx=%d sgleTx=%d pkTx=%d stop=%d\n", __func__, count, countPkTx, cotuTx, CarrSprTx, pkTx, sgleTx, scTx, stop);
++ _rtw_memset(extra, '\0', sizeof(extra));
++
++ if (stop == 0) {
++ bStartTest = 0; // To set Stop
++ pmp_priv->tx.stop = 1;
++ sprintf( extra, "Stop continuous Tx");
++ } else {
++ bStartTest = 1;
++ if (pmp_priv->mode != MP_ON) {
++ if (pmp_priv->tx.stop != 1) {
++ DBG_871X("%s: MP_MODE != ON %d\n", __func__, pmp_priv->mode);
++ return -EFAULT;
++ }
++ }
++ }
++
++ if (pkTx == 0 || countPkTx == 0)
++ pmp_priv->mode = MP_PACKET_TX;
++ if (sgleTx == 0)
++ pmp_priv->mode = MP_SINGLE_TONE_TX;
++ if (cotuTx == 0)
++ pmp_priv->mode = MP_CONTINUOUS_TX;
++ if (CarrSprTx == 0)
++ pmp_priv->mode = MP_CARRIER_SUPPRISSION_TX;
++ if (scTx == 0)
++ pmp_priv->mode = MP_SINGLE_CARRIER_TX;
++
++ switch (pmp_priv->mode)
++ {
++ case MP_PACKET_TX:
++
++ //DBG_871X("%s:pkTx %d\n", __func__,bStartTest);
++ if (bStartTest == 0)
++ {
++ pmp_priv->tx.stop = 1;
++ pmp_priv->mode = MP_ON;
++ sprintf( extra, "Stop continuous Tx");
++ }
++ else if (pmp_priv->tx.stop == 1)
++ {
++ sprintf( extra, "Start continuous DA=ffffffffffff len=1500 count=%u,\n",count);
++ //DBG_871X("%s:countPkTx %d\n", __func__,count);
++ pmp_priv->tx.stop = 0;
++ pmp_priv->tx.count = count;
++ pmp_priv->tx.payload = 2;
++ pattrib = &pmp_priv->tx.attrib;
++ pattrib->pktlen = 1460;
++ _rtw_memset(pattrib->dst, 0xFF, ETH_ALEN);
++ SetPacketTx(padapter);
++ }
++ else {
++ //DBG_871X("%s: pkTx not stop\n", __func__);
++ return -EFAULT;
++ }
++ wrqu->length = strlen(extra);
++ return 0;
++
++ case MP_SINGLE_TONE_TX:
++ //DBG_871X("%s: sgleTx %d \n", __func__, bStartTest);
++ if (bStartTest != 0){
++ sprintf( extra, "Start continuous DA=ffffffffffff len=1500 \n infinite=yes.");
++
++ }
++ Hal_SetSingleToneTx(padapter, (u8)bStartTest);
++ break;
++
++ case MP_CONTINUOUS_TX:
++ DBG_871X("%s: cotuTx %d\n", __func__, bStartTest);
++ if (bStartTest != 0){
++ sprintf( extra, "Start continuous DA=ffffffffffff len=1500 \n infinite=yes.");
++ }
++ Hal_SetContinuousTx(padapter, (u8)bStartTest);
++ break;
++
++ case MP_CARRIER_SUPPRISSION_TX:
++ //DBG_871X("%s: CarrSprTx %d\n", __func__, bStartTest);
++ if (bStartTest != 0){
++ if( pmp_priv->rateidx <= MPT_RATE_11M )
++ {
++ sprintf( extra, "Start continuous DA=ffffffffffff len=1500 \n infinite=yes.");
++ }else
++ sprintf( extra, "Specify carrier suppression but not CCK rate");
++ }
++ Hal_SetCarrierSuppressionTx(padapter, (u8)bStartTest);
++ break;
++
++ case MP_SINGLE_CARRIER_TX:
++ //DBG_871X("%s: scTx %d\n", __func__, bStartTest);
++ if (bStartTest != 0){
++ sprintf( extra, "Start continuous DA=ffffffffffff len=1500 \n infinite=yes.");
++ }
++ Hal_SetSingleCarrierTx(padapter, (u8)bStartTest);
++ break;
++
++ default:
++ //DBG_871X("%s:No Match MP_MODE\n", __func__);
++ sprintf( extra, "Error! Continuous-Tx is not on-going.");
++ return -EFAULT;
++ }
++
++ if (bStartTest) {
++ struct mp_priv *pmp_priv = &padapter->mppriv;
++ if (pmp_priv->tx.stop == 0) {
++ pmp_priv->tx.stop = 1;
++ //DBG_871X("%s: pkt tx is running...\n", __func__);
++ rtw_msleep_os(5);
++ }
++ pmp_priv->tx.stop = 0;
++ pmp_priv->tx.count = 1;
++ SetPacketTx(padapter);
++ } else {
++ pmp_priv->mode = MP_ON;
++ }
++
++ wrqu->length = strlen(extra);
++ return 0;
++}
++
++static int rtw_mp_arx(struct net_device *dev,
++ struct iw_request_info *info,
++ struct iw_point *wrqu, char *extra)
++{
++ u8 bStartRx=0,bStopRx=0;
++ PADAPTER padapter = rtw_netdev_priv(dev);
++ u8 input[wrqu->length];
++
++ if (copy_from_user(input, wrqu->pointer, wrqu->length))
++ return -EFAULT;
++
++ DBG_871X("%s: %s\n", __func__, input);
++
++ bStartRx = (strncmp(input, "start", 5)==0)?1:0; // strncmp TRUE is 0
++ bStopRx = (strncmp(input, "stop", 5)==0)?1:0; // strncmp TRUE is 0
++ SetPacketRx(padapter, bStartRx);
++
++ if(bStartRx)
++ {
++ sprintf( extra, "start");
++ wrqu->length = strlen(extra) + 1;
++ }
++ else if(bStopRx)
++ {
++ sprintf( extra, "Received packet OK:%d CRC error:%d",padapter->mppriv.rx_pktcount,
++ padapter->mppriv.rx_crcerrpktcount);
++ wrqu->length = strlen(extra) + 1;
++ }
++
++
++ return 0;
++}
++
++static int rtw_mp_trx_query(struct net_device *dev,
++ struct iw_request_info *info,
++ struct iw_point *wrqu, char *extra)
++{
++ u32 txok,txfail,rxok,rxfail;
++ PADAPTER padapter = rtw_netdev_priv(dev);
++ //if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length))
++ // return -EFAULT;
++
++ txok=padapter->mppriv.tx.sended;
++ txfail=0;
++ rxok = padapter->mppriv.rx_pktcount;
++ rxfail = padapter->mppriv.rx_crcerrpktcount;
++
++ _rtw_memset(extra, '\0', 128);
++
++ sprintf(extra, "Tx OK:%d, Tx Fail:%d, Rx OK:%d, CRC error:%d ", txok, txfail,rxok,rxfail);
++
++ wrqu->length=strlen(extra)+1;
++
++ return 0;
++}
++
++static int rtw_mp_pwrtrk(struct net_device *dev,
++ struct iw_request_info *info,
++ struct iw_point *wrqu, char *extra)
++{
++ u8 enable;
++ u32 thermal;
++ s32 ret;
++ PADAPTER padapter = rtw_netdev_priv(dev);
++ u8 input[wrqu->length];
++
++ if (copy_from_user(input, wrqu->pointer, wrqu->length))
++ return -EFAULT;
++
++ _rtw_memset(extra, 0, wrqu->length);
++
++ enable = 1;
++ if (wrqu->length > 1) { // not empty string
++ if (strncmp(input, "stop", 4) == 0)
++ {
++ enable = 0;
++ sprintf(extra, "mp tx power tracking stop");
++ }
++ else if (sscanf(input, "ther=%d", &thermal)) {
++ ret = Hal_SetThermalMeter(padapter, (u8)thermal);
++ if (ret == _FAIL) return -EPERM;
++ sprintf(extra, "mp tx power tracking start,target value=%d ok ",thermal);
++ }else {
++ return -EINVAL;
++ }
++ }
++
++ ret = Hal_SetPowerTracking(padapter, enable);
++ if (ret == _FAIL) return -EPERM;
++
++ wrqu->length = strlen(extra);
++
++ return 0;
++}
++
++static int rtw_mp_psd(struct net_device *dev,
++ struct iw_request_info *info,
++ struct iw_point *wrqu, char *extra)
++{
++ PADAPTER padapter = rtw_netdev_priv(dev);
++ u8 input[wrqu->length];
++
++ if (copy_from_user(input, wrqu->pointer, wrqu->length))
++ return -EFAULT;
++
++ strcpy(extra,input);
++
++ wrqu->length = mp_query_psd(padapter, extra);
++
++ return 0;
++}
++
++static int rtw_mp_thermal(struct net_device *dev,
++ struct iw_request_info *info,
++ struct iw_point *wrqu, char *extra)
++{
++ u8 val;
++ u16 bwrite=1;
++ #ifdef CONFIG_RTL8192C
++ u16 addr=0x78;
++ #endif
++ #ifdef CONFIG_RTL8192D
++ u16 addr=0xc3;
++ #endif
++ u16 cnt=1;
++ u16 max_available_size=0;
++ PADAPTER padapter = rtw_netdev_priv(dev);
++
++ if (copy_from_user(extra, wrqu->pointer, wrqu->length))
++ return -EFAULT;
++
++ //DBG_871X("print extra %s \n",extra);
++
++ bwrite = strncmp(extra, "write", 6); // strncmp TRUE is 0
++
++ Hal_GetThermalMeter(padapter, &val);
++
++ if( bwrite == 0 )
++ {
++ //DBG_871X("to write val:%d",val);
++ EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, (PVOID)&max_available_size, _FALSE);
++ if( 2 > max_available_size )
++ {
++ DBG_871X("no available efuse!\n");
++ return -EFAULT;
++ }
++ if ( rtw_efuse_map_write(padapter, addr, cnt, &val) == _FAIL )
++ {
++ DBG_871X("rtw_efuse_map_write error \n");
++ return -EFAULT;
++ }
++ else
++ {
++ sprintf(extra, " efuse write ok :%d", val);
++ }
++ }
++ else
++ {
++ sprintf(extra, "%d", val);
++ }
++ wrqu->length = strlen(extra);
++
++ return 0;
++}
++
++static int rtw_mp_reset_stats(struct net_device *dev,
++ struct iw_request_info *info,
++ struct iw_point *wrqu, char *extra)
++{
++ struct mp_priv *pmp_priv;
++ struct pkt_attrib *pattrib;
++ PADAPTER padapter = rtw_netdev_priv(dev);
++
++ pmp_priv = &padapter->mppriv;
++
++ pmp_priv->tx.sended = 0;
++ padapter->mppriv.rx_pktcount = 0;
++ padapter->mppriv.rx_crcerrpktcount = 0;
++
++ return 0;
++}
++
++static int rtw_mp_dump(struct net_device *dev,
++ struct iw_request_info *info,
++ struct iw_point *wrqu, char *extra)
++{
++ struct mp_priv *pmp_priv;
++ struct pkt_attrib *pattrib;
++ u32 value;
++ u8 rf_type,path_nums = 0;
++ u32 i,j=1,path;
++ PADAPTER padapter = rtw_netdev_priv(dev);
++
++ pmp_priv = &padapter->mppriv;
++
++
++ //if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length))
++ // return -EFAULT;
++
++ if ( strncmp(extra, "all", 4)==0 )
++ {
++ DBG_871X("\n======= MAC REG =======\n");
++ for ( i=0x0;i<0x300;i+=4 )
++ {
++ if(j%4==1) DBG_871X("0x%02x",i);
++ DBG_871X(" 0x%08x ",rtw_read32(padapter,i));
++ if((j++)%4 == 0) DBG_871X("\n");
++ }
++ for( i=0x400;i<0x800;i+=4 )
++ {
++ if(j%4==1) DBG_871X("0x%02x",i);
++ DBG_871X(" 0x%08x ",rtw_read32(padapter,i));
++ if((j++)%4 == 0) DBG_871X("\n");
++ }
++
++ i,j=1;
++ rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));
++
++ DBG_871X("\n======= RF REG =======\n");
++ if(( RF_1T2R == rf_type ) ||( RF_1T1R ==rf_type ))
++ path_nums = 1;
++ else
++ path_nums = 2;
++
++ for(path=0;path<path_nums;path++)
++ {
++#ifdef CONFIG_RTL8192D
++ for (i = 0; i < 0x50; i++)
++#else
++ for (i = 0; i < 0x34; i++)
++#endif
++ {
++ //value = PHY_QueryRFReg(padapter, (RF90_RADIO_PATH_E)path,i, bMaskDWord);
++ value =rtw_hal_read_rfreg(padapter, path, i, 0xffffffff);
++ if(j%4==1) DBG_871X("0x%02x ",i);
++ DBG_871X(" 0x%08x ",value);
++ if((j++)%4==0) DBG_871X("\n");
++ }
++ }
++ }
++ return 0;
++}
++
++static int rtw_mp_phypara(struct net_device *dev,
++ struct iw_request_info *info,
++ struct iw_point *wrqu, char *extra)
++{
++
++ PADAPTER padapter = rtw_netdev_priv(dev);
++ char input[wrqu->length];
++ u32 valxcap;
++
++ if (copy_from_user(input, wrqu->pointer, wrqu->length))
++ return -EFAULT;
++
++ DBG_871X("%s:iwpriv in=%s\n", __func__, input);
++
++ sscanf(input, "xcap=%d", &valxcap);
++
++ if (!IS_HARDWARE_TYPE_8192D(padapter))
++ return 0;
++#ifdef CONFIG_RTL8192D
++ Hal_ProSetCrystalCap( padapter , valxcap );
++#endif
++
++ sprintf( extra, "Set xcap=%d",valxcap );
++ wrqu->length = strlen(extra) + 1;
++
++return 0;
++
++}
++
++
++/* update Tx AGC offset */
++static int rtw_mp_antBdiff(struct net_device *dev,
++ struct iw_request_info *info,
++ struct iw_point *wrqu, char *extra)
++{
++
++
++ // MPT_ProSetTxAGCOffset
++ return 0;
++}
++
++
++static int rtw_mp_set(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wdata, char *extra)
++{
++ struct iw_point *wrqu = (struct iw_point *)wdata;
++ u32 subcmd = wrqu->flags;
++ PADAPTER padapter = rtw_netdev_priv(dev);
++
++ if (padapter == NULL)
++ {
++ return -ENETDOWN;
++ }
++
++ //_rtw_memset(extra, 0x00, IW_PRIV_SIZE_MASK);
++
++ if (extra == NULL)
++ {
++ wrqu->length = 0;
++ return -EIO;
++ }
++
++ switch(subcmd)
++ {
++ case WRITE_REG :
++ rtw_mp_write_reg (dev,info,wrqu,extra);
++ break;
++
++ case WRITE_RF:
++ rtw_mp_write_rf (dev,info,wrqu,extra);
++ break;
++
++ case MP_START:
++ DBG_871X("set case mp_start \n");
++ rtw_mp_start (dev,info,wrqu,extra);
++ break;
++
++ case MP_STOP:
++ DBG_871X("set case mp_stop \n");
++ rtw_mp_stop (dev,info,wrqu,extra);
++ break;
++
++ case MP_BANDWIDTH:
++ DBG_871X("set case mp_bandwidth \n");
++ rtw_mp_bandwidth (dev,info,wrqu,extra);
++ break;
++
++ case MP_RESET_STATS:
++ DBG_871X("set case MP_RESET_STATS \n");
++ rtw_mp_reset_stats (dev,info,wrqu,extra);
++ break;
++
++ case EFUSE_SET:
++ DBG_871X("efuse set \n");
++ rtw_mp_efuse_set (dev,info,wdata,extra);
++ break;
++
++ }
++
++
++ return 0;
++}
++
++
++static int rtw_mp_get(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wdata, char *extra)
++{
++ struct iw_point *wrqu = (struct iw_point *)wdata;
++ u32 subcmd = wrqu->flags;
++ PADAPTER padapter = rtw_netdev_priv(dev);
++
++ //DBG_871X("in mp_get extra= %s \n",extra);
++
++ if (padapter == NULL)
++ {
++ return -ENETDOWN;
++ }
++ if (extra == NULL)
++ {
++ wrqu->length = 0;
++ return -EIO;
++ }
++
++ switch(subcmd)
++ {
++ case MP_PHYPARA:
++ DBG_871X("mp_get MP_PHYPARA \n");
++ rtw_mp_phypara(dev,info,wrqu,extra);
++ break;
++
++ case MP_CHANNEL:
++ DBG_871X("set case mp_channel \n");
++ rtw_mp_channel (dev,info,wrqu,extra);
++ break;
++
++ case READ_REG:
++ DBG_871X("mp_get READ_REG \n");
++ rtw_mp_read_reg (dev,info,wrqu,extra);
++ break;
++ case READ_RF:
++ DBG_871X("mp_get READ_RF \n");
++ rtw_mp_read_rf (dev,info,wrqu,extra);
++ break;
++
++ case MP_RATE:
++ DBG_871X("set case mp_rate \n");
++ rtw_mp_rate (dev,info,wrqu,extra);
++ break;
++
++ case MP_TXPOWER:
++ DBG_871X("set case MP_TXPOWER \n");
++ rtw_mp_txpower (dev,info,wrqu,extra);
++ break;
++
++ case MP_ANT_TX:
++ DBG_871X("set case MP_ANT_TX \n");
++ rtw_mp_ant_tx (dev,info,wrqu,extra);
++ break;
++
++ case MP_ANT_RX:
++ DBG_871X("set case MP_ANT_RX \n");
++ rtw_mp_ant_rx (dev,info,wrqu,extra);
++ break;
++
++ case MP_QUERY:
++ DBG_871X("mp_get mp_query MP_QUERY \n");
++ rtw_mp_trx_query(dev,info,wrqu,extra);
++ break;
++
++ case MP_CTX:
++ DBG_871X("set case MP_CTX \n");
++ rtw_mp_ctx (dev,info,wrqu,extra);
++ break;
++
++ case MP_ARX:
++ DBG_871X("set case MP_ARX \n");
++ rtw_mp_arx (dev,info,wrqu,extra);
++ break;
++
++ case EFUSE_GET:
++ DBG_871X("efuse get EFUSE_GET \n");
++ rtw_mp_efuse_get(dev,info,wdata,extra);
++ break;
++
++ case MP_DUMP:
++ DBG_871X("set case MP_DUMP \n");
++ rtw_mp_dump (dev,info,wrqu,extra);
++ break;
++ case MP_PSD:
++ DBG_871X("set case MP_PSD \n");
++ rtw_mp_psd (dev,info,wrqu,extra);
++ break;
++
++ case MP_THER:
++ DBG_871X("set case MP_THER \n");
++ rtw_mp_thermal (dev,info,wrqu,extra);
++ break;
++
++ case MP_PWRTRK:
++ DBG_871X("set case MP_PWRTRK \n");
++ rtw_mp_pwrtrk (dev,info,wrqu,extra);
++ break;
++ }
++
++return 0;
++}
++
++#endif //#if defined(CONFIG_MP_INCLUDED) && defined(CONFIG_MP_IWPRIV_SUPPORT)
++
++static int rtw_wfd_tdls_enable(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++ int ret = 0;
++
++#ifdef CONFIG_TDLS
++#ifdef CONFIG_WFD
++
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++
++ printk( "[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length -1 );
++
++ if ( extra[ 0 ] == '0' )
++ {
++ padapter->wdinfo.wfd_tdls_enable = 0;
++ }
++ else
++ {
++ padapter->wdinfo.wfd_tdls_enable = 1;
++ }
++
++#endif //CONFIG_WFD
++#endif //CONFIG_TDLS
++
++ return ret;
++}
++
++static int rtw_tdls_weaksec(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++ int ret = 0;
++
++#ifdef CONFIG_TDLS
++
++ u8 i, j;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++
++ DBG_871X( "[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length -1 );
++
++ if ( extra[ 0 ] == '0' )
++ {
++ padapter->wdinfo.wfd_tdls_weaksec = 0;
++ }
++ else
++ {
++ padapter->wdinfo.wfd_tdls_weaksec = 1;
++ }
++#endif
++
++ return ret;
++}
++
++
++static int rtw_tdls_enable(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++ int ret = 0;
++
++#ifdef CONFIG_TDLS
++
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
++ _irqL irqL;
++ _list *plist, *phead;
++ s32 index;
++ struct sta_info *psta = NULL;
++ struct sta_priv *pstapriv = &padapter->stapriv;
++ u8 tdls_sta[NUM_STA][ETH_ALEN];
++ u8 empty_hwaddr[ETH_ALEN] = { 0x00 };
++
++ printk( "[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length -1 );
++
++ _rtw_memset(tdls_sta, 0x00, sizeof(tdls_sta));
++
++ if ( extra[ 0 ] == '0' )
++ {
++ ptdlsinfo->enable = 0;
++
++ if(pstapriv->asoc_sta_count==1)
++ return ret;
++
++ _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
++ for(index=0; index< NUM_STA; index++)
++ {
++ phead = &(pstapriv->sta_hash[index]);
++ plist = get_next(phead);
++
++ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE)
++ {
++ psta = LIST_CONTAINOR(plist, struct sta_info ,hash_list);
++
++ plist = get_next(plist);
++
++ if(psta->tdls_sta_state != TDLS_STATE_NONE)
++ {
++ _rtw_memcpy(tdls_sta[index], psta->hwaddr, ETH_ALEN);
++ }
++ }
++ }
++ _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
++
++ for(index=0; index< NUM_STA; index++)
++ {
++ if( !_rtw_memcmp(tdls_sta[index], empty_hwaddr, ETH_ALEN) )
++ {
++ printk("issue tear down to "MAC_FMT"\n", MAC_ARG(tdls_sta[index]));
++ issue_tdls_teardown(padapter, tdls_sta[index]);
++ }
++ }
++ rtw_tdls_cmd(padapter, myid(&(padapter->eeprompriv)), TDLS_RS_RCR);
++ rtw_reset_tdls_info(padapter);
++ }
++ else if ( extra[ 0 ] == '1' )
++ {
++ ptdlsinfo->enable = 1;
++ }
++#endif //CONFIG_TDLS
++
++ return ret;
++}
++
++static int rtw_tdls_setup(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++ int ret = 0;
++
++#ifdef CONFIG_TDLS
++
++ u8 i, j;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ u8 mac_addr[ETH_ALEN];
++
++#ifdef CONFIG_WFD
++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo);
++#endif // CONFIG_WFD
++
++ printk( "[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length -1 );
++
++ for( i=0, j=0 ; i < ETH_ALEN; i++, j+=3 ){
++ mac_addr[i]=key_2char2num(*(extra+j), *(extra+j+1));
++ }
++
++#ifdef CONFIG_WFD
++ if ( _AES_ != padapter->securitypriv.dot11PrivacyAlgrthm )
++ {
++ // Weak Security situation with AP.
++ if ( 0 == pwdinfo->wfd_tdls_weaksec )
++ {
++ // Can't send the tdls setup request out!!
++ DBG_871X( "[%s] Current link is not AES, SKIP sending the tdls setup request!!\n", __FUNCTION__ );
++ }
++ else
++ {
++ issue_tdls_setup_req(padapter, mac_addr);
++ }
++ }
++ else
++#endif // CONFIG_WFD
++ {
++ issue_tdls_setup_req(padapter, mac_addr);
++ }
++#endif
++
++ return ret;
++}
++
++static int rtw_tdls_teardown(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++ int ret = 0;
++
++#ifdef CONFIG_TDLS
++
++ u8 i,j;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct sta_info *ptdls_sta = NULL;
++ u8 mac_addr[ETH_ALEN];
++
++ printk( "[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length -1 );
++
++ for( i=0, j=0 ; i < ETH_ALEN; i++, j+=3 ){
++ mac_addr[i]=key_2char2num(*(extra+j), *(extra+j+1));
++ }
++
++ ptdls_sta = rtw_get_stainfo( &(padapter->stapriv), mac_addr);
++
++ if(ptdls_sta != NULL)
++ {
++ ptdls_sta->stat_code = _RSON_TDLS_TEAR_UN_RSN_;
++ issue_tdls_teardown(padapter, mac_addr);
++ }
++
++#endif //CONFIG_TDLS
++
++ return ret;
++}
++
++static int rtw_tdls_discovery(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++ int ret = 0;
++
++#ifdef CONFIG_TDLS
++
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++
++ printk( "[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length -1 );
++
++ issue_tdls_dis_req(padapter, NULL);
++
++#endif //CONFIG_TDLS
++
++ return ret;
++}
++
++static int rtw_tdls_ch_switch(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++ int ret = 0;
++
++#ifdef CONFIG_TDLS
++
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
++ u8 i, j, mac_addr[ETH_ALEN];
++ struct sta_info *ptdls_sta = NULL;
++
++ printk( "[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length -1 );
++
++ for( i=0, j=0 ; i < ETH_ALEN; i++, j+=3 ){
++ mac_addr[i]=key_2char2num(*(extra+j), *(extra+j+1));
++ }
++
++ ptdls_sta = rtw_get_stainfo(&padapter->stapriv, mac_addr);
++ if( ptdls_sta == NULL )
++ return ret;
++ ptdlsinfo->ch_sensing=1;
++
++ rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_INIT_CH_SEN);
++
++#endif //CONFIG_TDLS
++
++ return ret;
++}
++
++static int rtw_tdls_pson(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++ int ret = 0;
++
++#ifdef CONFIG_TDLS
++
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ u8 i, j, mac_addr[ETH_ALEN];
++ struct sta_info *ptdls_sta = NULL;
++
++ printk( "[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length -1 );
++
++ for( i=0, j=0 ; i < ETH_ALEN; i++, j+=3 ){
++ mac_addr[i]=key_2char2num(*(extra+j), *(extra+j+1));
++ }
++
++ ptdls_sta = rtw_get_stainfo(&padapter->stapriv, mac_addr);
++
++ issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta, 1);
++
++#endif //CONFIG_TDLS
++
++ return ret;
++}
++
++static int rtw_tdls_psoff(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++ int ret = 0;
++
++#ifdef CONFIG_TDLS
++
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ u8 i, j, mac_addr[ETH_ALEN];
++ struct sta_info *ptdls_sta = NULL;
++
++ printk( "[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length -1 );
++
++ for( i=0, j=0 ; i < ETH_ALEN; i++, j+=3 ){
++ mac_addr[i]=key_2char2num(*(extra+j), *(extra+j+1));
++ }
++
++ ptdls_sta = rtw_get_stainfo(&padapter->stapriv, mac_addr);
++
++ issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta, 0);
++
++#endif //CONFIG_TDLS
++
++ return ret;
++}
++
++static int rtw_tdls_setip(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++ int ret = 0;
++
++#ifdef CONFIG_TDLS
++#ifdef CONFIG_WFD
++
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
++ struct wifi_display_info *pwfd_info = ptdlsinfo->wfd_info;
++ u8 i=0, j=0, k=0, tag=0, ip[3] = { 0xff }, *ptr = extra;
++
++ printk( "[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length - 1 );
++
++
++ while( i < 4 )
++ {
++ for( j=0; j < 4; j++)
++ {
++ if( *( extra + j + tag ) == '.' || *( extra + j + tag ) == '\0' )
++ {
++ if( j == 1 )
++ pwfd_info->ip_address[i]=convert_ip_addr( '0', '0', *(extra+(j-1)+tag));
++ if( j == 2 )
++ pwfd_info->ip_address[i]=convert_ip_addr( '0', *(extra+(j-2)+tag), *(extra+(j-1)+tag));
++ if( j == 3 )
++ pwfd_info->ip_address[i]=convert_ip_addr( *(extra+(j-3)+tag), *(extra+(j-2)+tag), *(extra+(j-1)+tag));
++
++ tag += j + 1;
++ break;
++ }
++ }
++ i++;
++ }
++
++ printk( "[%s] Set IP = %u.%u.%u.%u \n", __FUNCTION__,
++ ptdlsinfo->wfd_info->ip_address[0], ptdlsinfo->wfd_info->ip_address[1],
++ ptdlsinfo->wfd_info->ip_address[2], ptdlsinfo->wfd_info->ip_address[3]
++ );
++
++#endif //CONFIG_WFD
++#endif //CONFIG_TDLS
++
++ return ret;
++}
++
++static int rtw_tdls_getip(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++ int ret = 0;
++
++#ifdef CONFIG_TDLS
++#ifdef CONFIG_WFD
++
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
++ struct wifi_display_info *pwfd_info = ptdlsinfo->wfd_info;
++
++ printk( "[%s]\n", __FUNCTION__);
++
++ sprintf( extra, "\n\n%u.%u.%u.%u\n",
++ pwfd_info->peer_ip_address[0], pwfd_info->peer_ip_address[1],
++ pwfd_info->peer_ip_address[2], pwfd_info->peer_ip_address[3]
++ );
++
++ printk( "[%s] IP=%u.%u.%u.%u\n", __FUNCTION__,
++ pwfd_info->peer_ip_address[0], pwfd_info->peer_ip_address[1],
++ pwfd_info->peer_ip_address[2], pwfd_info->peer_ip_address[3]
++ );
++
++ wrqu->data.length = strlen( extra );
++
++#endif //CONFIG_WFD
++#endif //CONFIG_TDLS
++
++ return ret;
++}
++
++static int rtw_tdls_getport(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++
++ int ret = 0;
++
++#ifdef CONFIG_TDLS
++#ifdef CONFIG_WFD
++
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
++ struct wifi_display_info *pwfd_info = ptdlsinfo->wfd_info;
++
++ printk( "[%s]\n", __FUNCTION__);
++
++ sprintf( extra, "\n\n%d\n", pwfd_info->peer_rtsp_ctrlport );
++ printk( "[%s] remote port = %d\n", __FUNCTION__, pwfd_info->peer_rtsp_ctrlport );
++
++ wrqu->data.length = strlen( extra );
++
++#endif //CONFIG_WFD
++#endif //CONFIG_TDLS
++
++ return ret;
++
++}
++
++//WFDTDLS, for sigma test
++static int rtw_tdls_dis_result(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++
++ int ret = 0;
++
++#ifdef CONFIG_TDLS
++#ifdef CONFIG_WFD
++
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
++ struct wifi_display_info *pwfd_info = ptdlsinfo->wfd_info;
++
++ printk( "[%s]\n", __FUNCTION__);
++
++ if(ptdlsinfo->dev_discovered == 1 )
++ {
++ sprintf( extra, "\n\nDis=1\n" );
++ ptdlsinfo->dev_discovered = 0;
++ }
++
++ wrqu->data.length = strlen( extra );
++
++#endif //CONFIG_WFD
++#endif //CONFIG_TDLS
++
++ return ret;
++
++}
++
++//WFDTDLS, for sigma test
++static int rtw_wfd_tdls_status(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++
++ int ret = 0;
++
++#ifdef CONFIG_TDLS
++#ifdef CONFIG_WFD
++
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
++ struct wifi_display_info *pwfd_info = ptdlsinfo->wfd_info;
++
++ printk( "[%s]\n", __FUNCTION__);
++
++ if(ptdlsinfo->setup_state == TDLS_LINKED_STATE )
++ {
++ sprintf( extra, "\n\nStatus=1\n" );
++ }
++ else
++ {
++ sprintf( extra, "\n\nStatus=0\n" );
++ }
++
++ wrqu->data.length = strlen( extra );
++
++#endif //CONFIG_WFD
++#endif //CONFIG_TDLS
++
++ return ret;
++
++}
++
++static int rtw_tdls_ch_switch_off(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++ int ret = 0;
++
++#ifdef CONFIG_TDLS
++
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ u8 i, j, mac_addr[ETH_ALEN];
++ struct sta_info *ptdls_sta = NULL;
++
++ printk( "[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length -1 );
++
++ for( i=0, j=0 ; i < ETH_ALEN; i++, j+=3 ){
++ mac_addr[i]=key_2char2num(*(extra+j), *(extra+j+1));
++ }
++
++ ptdls_sta = rtw_get_stainfo(&padapter->stapriv, mac_addr);
++
++ ptdls_sta->tdls_sta_state |= TDLS_SW_OFF_STATE;
++/*
++ if((ptdls_sta->tdls_sta_state & TDLS_AT_OFF_CH_STATE) && (ptdls_sta->tdls_sta_state & TDLS_PEER_AT_OFF_STATE)){
++ pmlmeinfo->tdls_candidate_ch= pmlmeext->cur_channel;
++ issue_tdls_ch_switch_req(padapter, mac_addr);
++ DBG_871X("issue tdls ch switch req back to base channel\n");
++ }
++*/
++
++#endif //CONFIG_TDLS
++
++ return ret;
++}
++
++static int rtw_tdls(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++ int ret = 0;
++
++#ifdef CONFIG_TDLS
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++
++ printk( "[%s] extra = %s\n", __FUNCTION__, extra );
++ // WFD Sigma will use the tdls enable command to let the driver know we want to test the tdls now!
++ if ( _rtw_memcmp( extra, "wfdenable=", 10 ) )
++ {
++ wrqu->data.length -=10;
++ rtw_wfd_tdls_enable( dev, info, wrqu, &extra[10] );
++ return ret;
++ }
++ else if ( _rtw_memcmp( extra, "weaksec=", 8 ) )
++ {
++ wrqu->data.length -=8;
++ rtw_tdls_weaksec( dev, info, wrqu, &extra[8] );
++ return ret;
++ }
++ else if ( _rtw_memcmp( extra, "tdlsenable=", 11 ) )
++ {
++ wrqu->data.length -=11;
++ rtw_tdls_enable( dev, info, wrqu, &extra[11] );
++ return ret;
++ }
++
++ if( padapter->tdlsinfo.enable == 0 )
++ {
++ printk("tdls haven't enabled\n");
++ return 0;
++ }
++
++ if ( _rtw_memcmp( extra, "setup=", 6 ) )
++ {
++ wrqu->data.length -=6;
++ rtw_tdls_setup( dev, info, wrqu, &extra[6] );
++ }
++ else if (_rtw_memcmp( extra, "tear=", 5 ) )
++ {
++ wrqu->data.length -= 5;
++ rtw_tdls_teardown( dev, info, wrqu, &extra[5] );
++ }
++ else if (_rtw_memcmp( extra, "dis=", 4 ) )
++ {
++ wrqu->data.length -= 4;
++ rtw_tdls_discovery( dev, info, wrqu, &extra[4] );
++ }
++ else if (_rtw_memcmp( extra, "sw=", 3 ) )
++ {
++ wrqu->data.length -= 3;
++ rtw_tdls_ch_switch( dev, info, wrqu, &extra[3] );
++ }
++ else if (_rtw_memcmp( extra, "swoff=", 6 ) )
++ {
++ wrqu->data.length -= 6;
++ rtw_tdls_ch_switch_off( dev, info, wrqu, &extra[6] );
++ }
++ else if (_rtw_memcmp( extra, "pson=", 5 ) )
++ {
++ wrqu->data.length -= 5;
++ rtw_tdls_pson( dev, info, wrqu, &extra[5] );
++ }
++ else if (_rtw_memcmp( extra, "psoff=", 6 ) )
++ {
++ wrqu->data.length -= 6;
++ rtw_tdls_psoff( dev, info, wrqu, &extra[6] );
++ }
++#ifdef CONFIG_WFD
++ else if (_rtw_memcmp( extra, "setip=", 6 ) )
++ {
++ wrqu->data.length -= 6;
++ rtw_tdls_setip( dev, info, wrqu, &extra[6] );
++ }
++ else if (_rtw_memcmp( extra, "tprobe=", 6 ) )
++ {
++ issue_tunneled_probe_req((_adapter *)rtw_netdev_priv(dev));
++ }
++#endif //CONFIG_WFD
++
++#endif //CONFIG_TDLS
++
++ return ret;
++}
++
++
++static int rtw_tdls_get(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++ int ret = 0;
++
++#ifdef CONFIG_WFD
++
++ DBG_871X( "[%s] extra = %s\n", __FUNCTION__, (char*) wrqu->data.pointer );
++
++ if ( _rtw_memcmp( wrqu->data.pointer, "ip", 2 ) )
++ {
++ rtw_tdls_getip( dev, info, wrqu, extra );
++ }
++ if ( _rtw_memcmp( wrqu->data.pointer, "port", 4 ) )
++ {
++ rtw_tdls_getport( dev, info, wrqu, extra );
++ }
++
++ //WFDTDLS, for sigma test
++ if ( _rtw_memcmp( wrqu->data.pointer, "dis", 3 ) )
++ {
++ rtw_tdls_dis_result( dev, info, wrqu, extra );
++ }
++ if ( _rtw_memcmp( wrqu->data.pointer, "status", 6 ) )
++ {
++ rtw_wfd_tdls_status( dev, info, wrqu, extra );
++ }
++
++#endif //CONFIG_WFD
++
++ return ret;
++}
++
++static int rtw_pm_set(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++ int ret = 0;
++ unsigned mode = 0;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++
++ DBG_871X( "[%s] extra = %s\n", __FUNCTION__, extra );
++
++ if ( _rtw_memcmp( extra, "lps=", 4 ) )
++ {
++ sscanf(extra+4, "%u", &mode);
++ ret = rtw_pm_set_lps(padapter,mode);
++ }
++ else if ( _rtw_memcmp( extra, "ips=", 4 ) )
++ {
++ sscanf(extra+4, "%u", &mode);
++ ret = rtw_pm_set_ips(padapter,mode);
++ }
++ else{
++ ret = -EINVAL;
++ }
++
++ return ret;
++}
++
++#ifdef CONFIG_WOWLAN
++static int rtw_wowlan_ctrl(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++ int ret = 0;
++ struct oid_par_priv oid_par;
++ struct wowlan_ioctl_param *poidparam;
++ uint status=0;
++ u16 len;
++ u8 *pparmbuf = NULL, bset;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++
++ struct iw_point *p = &wrqu->data;
++
++ //DBG_871X("+rtw_wowlan_ctrl\n");
++
++ //mutex_lock(&ioctl_mutex);
++
++ if ((!p->length) || (!p->pointer)) {
++ ret = -EINVAL;
++ goto _rtw_wowlan_ctrl_exit;
++ }
++
++ pparmbuf = NULL;
++ bset = (u8)(p->flags & 0xFFFF);
++ len = p->length;
++ pparmbuf = (u8*)rtw_malloc(len);
++ if (pparmbuf == NULL){
++ ret = -ENOMEM;
++ goto _rtw_wowlan_ctrl_exit;
++ }
++
++ if (copy_from_user(pparmbuf, p->pointer, len)) {
++ ret = -EFAULT;
++ goto _rtw_wowlan_ctrl_exit_free;
++ }
++ poidparam = (struct wowlan_ioctl_param *)pparmbuf;
++
++ if(padapter->pwrctrlpriv.bSupportRemoteWakeup==_FALSE){
++ ret = -EPERM;
++ DBG_871X("+rtw_wowlan_ctrl: Device didn't support the remote wakeup!!\n");
++ goto _rtw_wowlan_ctrl_exit_free;
++ }
++ rtw_hal_set_hwreg(padapter,HW_VAR_WOWLAN,(u8 *)poidparam);
++
++ DBG_871X("rtw_wowlan_ctrl: subcode [%d], len[%d], buffer_len[%d]\r\n",
++ poidparam->subcode, poidparam->len, len);
++
++ if (copy_to_user(p->pointer, pparmbuf, len)) {
++ ret = -EFAULT;
++ }
++
++
++_rtw_wowlan_ctrl_exit_free:
++ //DBG_871X("-rtw_wowlan_ctrl( subcode = %d)\n", poidparam->subcode);
++ rtw_mfree(pparmbuf, len);
++_rtw_wowlan_ctrl_exit:
++
++
++ return ret;
++}
++#endif //CONFIG_WOWLAN
++
++#ifdef CONFIG_INTEL_WIDI
++static int rtw_widi_set(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++ int ret = 0;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++
++ process_intel_widi_cmd(padapter, extra);
++
++ return ret;
++}
++
++static int rtw_widi_set_probe_request(struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++ int ret = 0;
++ u8 *pbuf = NULL;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++
++ pbuf = rtw_malloc(sizeof(l2_msg_t));
++ if(pbuf)
++ {
++ copy_from_user(pbuf, wrqu->data.pointer, wrqu->data.length);
++ //_rtw_memcpy(pbuf, wrqu->data.pointer, wrqu->data.length);
++
++ if( wrqu->data.flags == 0 )
++ intel_widi_wk_cmd(padapter, INTEL_WIDI_ISSUE_PROB_WK, pbuf);
++ else if( wrqu->data.flags == 1 )
++ rtw_set_wfd_rds_sink_info( padapter, (l2_msg_t *)pbuf );
++ }
++ return ret;
++}
++
++#endif // CONFIG_INTEL_WIDI
++
++#ifdef RTL8723A_SDIO_LOOPBACK
++#include <rtl8723a_hal.h>
++
++static s32 initLoopback(PADAPTER padapter)
++{
++ PLOOPBACKDATA ploopback;
++
++
++ if (padapter->ploopback == NULL) {
++ ploopback = (PLOOPBACKDATA)rtw_zmalloc(sizeof(LOOPBACKDATA));
++ if (ploopback == NULL) return -ENOMEM;
++
++ _rtw_init_sema(&ploopback->sema, 0);
++
++ ploopback->bstop = _TRUE;
++ ploopback->cnt = 0;
++ ploopback->size = 300;
++ _rtw_memset(ploopback->msg, 0, sizeof(ploopback->msg));
++
++ padapter->ploopback = ploopback;
++ }
++
++ return 0;
++}
++
++static void freeLoopback(PADAPTER padapter)
++{
++ PLOOPBACKDATA ploopback;
++
++
++ ploopback = padapter->ploopback;
++ if (ploopback) {
++ rtw_mfree((u8*)ploopback, sizeof(LOOPBACKDATA));
++ padapter->ploopback = NULL;
++ }
++}
++
++static s32 initpseudoadhoc(PADAPTER padapter)
++{
++ NDIS_802_11_NETWORK_INFRASTRUCTURE networkType;
++ s32 err;
++ _irqL irqL;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ _queue *queue = &pmlmepriv->scanned_queue;
++
++ networkType = Ndis802_11IBSS;
++ _enter_critical_bh(&pmlmepriv->lock, &irqL);
++ _enter_critical_bh(&queue->lock, &irqL);
++ err = rtw_set_802_11_infrastructure_mode(padapter, networkType);
++ _exit_critical_bh(&queue->lock, &irqL);
++ _exit_critical_bh(&pmlmepriv->lock, &irqL);
++ if (err == _FALSE) return _FAIL;
++
++ err = rtw_setopmode_cmd(padapter, networkType);
++ if (err == _FAIL) return _FAIL;
++
++ return _SUCCESS;
++}
++
++static s32 createpseudoadhoc(PADAPTER padapter)
++{
++ NDIS_802_11_AUTHENTICATION_MODE authmode;
++ struct mlme_priv *pmlmepriv;
++ NDIS_802_11_SSID *passoc_ssid;
++ WLAN_BSSID_EX *pdev_network;
++ u8 *pibss;
++ u8 ssid[] = "pseduo_ad-hoc";
++ s32 err;
++ _irqL irqL;
++
++
++ pmlmepriv = &padapter->mlmepriv;
++
++ authmode = Ndis802_11AuthModeOpen;
++ err = rtw_set_802_11_authentication_mode(padapter, authmode);
++ if (err == _FALSE) return _FAIL;
++
++ passoc_ssid = &pmlmepriv->assoc_ssid;
++ _rtw_memset(passoc_ssid, 0, sizeof(NDIS_802_11_SSID));
++ passoc_ssid->SsidLength = sizeof(ssid) - 1;
++ _rtw_memcpy(passoc_ssid->Ssid, ssid, passoc_ssid->SsidLength);
++
++ pdev_network = &padapter->registrypriv.dev_network;
++ pibss = padapter->registrypriv.dev_network.MacAddress;
++ _rtw_memcpy(&pdev_network->Ssid, passoc_ssid, sizeof(NDIS_802_11_SSID));
++
++ rtw_update_registrypriv_dev_network(padapter);
++ rtw_generate_random_ibss(pibss);
++
++ _enter_critical_bh(&pmlmepriv->lock, &irqL);
++ pmlmepriv->fw_state = WIFI_ADHOC_MASTER_STATE;
++ _exit_critical_bh(&pmlmepriv->lock, &irqL);
++
++#if 0
++ err = rtw_createbss_cmd(padapter);
++ if (err == _FAIL) return _FAIL;
++#else
++{
++ struct wlan_network *pcur_network;
++ struct sta_info *psta;
++
++ //3 create a new psta
++ pcur_network = &pmlmepriv->cur_network;
++
++ //clear psta in the cur_network, if any
++ psta = rtw_get_stainfo(&padapter->stapriv, pcur_network->network.MacAddress);
++ if (psta) rtw_free_stainfo(padapter, psta);
++
++ psta = rtw_alloc_stainfo(&padapter->stapriv, pibss);
++ if (psta == NULL) return _FAIL;
++
++ //3 join psudo AdHoc
++ pcur_network->join_res = 1;
++ pcur_network->aid = psta->aid = 1;
++ _rtw_memcpy(&pcur_network->network, pdev_network, get_WLAN_BSSID_EX_sz(pdev_network));
++
++ // set msr to WIFI_FW_ADHOC_STATE
++#if 0
++ Set_NETYPE0_MSR(padapter, WIFI_FW_ADHOC_STATE);
++#else
++ {
++ u8 val8;
++
++ val8 = rtw_read8(padapter, MSR);
++ val8 &= 0xFC; // clear NETYPE0
++ val8 |= WIFI_FW_ADHOC_STATE & 0x3;
++ rtw_write8(padapter, MSR, val8);
++ }
++#endif
++}
++#endif
++
++ return _SUCCESS;
++}
++
++extern void rtl8723a_cal_txdesc_chksum(struct tx_desc *ptxdesc);
++extern void rtl8723a_fill_default_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf);
++
++static struct xmit_frame* createloopbackpkt(PADAPTER padapter, u32 size)
++{
++ struct xmit_priv *pxmitpriv;
++ struct xmit_frame *pframe;
++ struct xmit_buf *pxmitbuf;
++ struct pkt_attrib *pattrib;
++ struct tx_desc *desc;
++ u8 *pkt_start, *pkt_end, *ptr;
++ struct rtw_ieee80211_hdr *hdr;
++ s32 bmcast;
++ _irqL irqL;
++
++
++ if ((TXDESC_SIZE + WLANHDR_OFFSET + size) > MAX_XMITBUF_SZ) return NULL;
++
++ pxmitpriv = &padapter->xmitpriv;
++ pframe = NULL;
++
++ //2 1. allocate xmit frame
++ pframe = rtw_alloc_xmitframe(pxmitpriv);
++ if (pframe == NULL) return NULL;
++ pframe->padapter = padapter;
++
++ //2 2. allocate xmit buffer
++ _enter_critical_bh(&pxmitpriv->lock, &irqL);
++ pxmitbuf = rtw_alloc_xmitbuf(pxmitpriv);
++ _exit_critical_bh(&pxmitpriv->lock, &irqL);
++ if (pxmitbuf == NULL) {
++ rtw_free_xmitframe(pxmitpriv, pframe);
++ return NULL;
++ }
++
++ pframe->pxmitbuf = pxmitbuf;
++ pframe->buf_addr = pxmitbuf->pbuf;
++ pxmitbuf->priv_data = pframe;
++
++ //2 3. update_attrib()
++ pattrib = &pframe->attrib;
++
++ // init xmitframe attribute
++ _rtw_memset(pattrib, 0, sizeof(struct pkt_attrib));
++
++ pattrib->ether_type = 0x8723;
++ _rtw_memcpy(pattrib->src, padapter->eeprompriv.mac_addr, ETH_ALEN);
++ _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
++ _rtw_memset(pattrib->dst, 0xFF, ETH_ALEN);
++ _rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN);
++// pattrib->pctrl = 0;
++// pattrib->dhcp_pkt = 0;
++// pattrib->pktlen = 0;
++ pattrib->ack_policy = 0;
++// pattrib->pkt_hdrlen = ETH_HLEN;
++ pattrib->hdrlen = WLAN_HDR_A3_LEN;
++ pattrib->subtype = WIFI_DATA;
++ pattrib->priority = 0;
++ pattrib->qsel = pattrib->priority;
++// do_queue_select(padapter, pattrib);
++ pattrib->nr_frags = 1;
++ pattrib->encrypt = 0;
++ pattrib->bswenc = _FALSE;
++ pattrib->qos_en = _FALSE;
++
++ bmcast = IS_MCAST(pattrib->ra);
++ if (bmcast) {
++ pattrib->mac_id = 1;
++ pattrib->psta = rtw_get_bcmc_stainfo(padapter);
++ } else {
++ pattrib->mac_id = 0;
++ pattrib->psta = rtw_get_stainfo(&padapter->stapriv, get_bssid(&padapter->mlmepriv));
++ }
++
++ pattrib->pktlen = size;
++ pattrib->last_txcmdsz = pattrib->hdrlen + pattrib->pktlen;
++
++ //2 4. fill TX descriptor
++ desc = (struct tx_desc*)pframe->buf_addr;
++ _rtw_memset(desc, 0, TXDESC_SIZE);
++
++ rtl8723a_fill_default_txdesc(pframe, (u8*)desc);
++
++ // Hw set sequence number
++ ((PTXDESC)desc)->hwseq_en = 0; // HWSEQ_EN, 0:disable, 1:enable
++// ((PTXDESC)desc)->hwseq_sel = 0; // HWSEQ_SEL
++
++ ((PTXDESC)desc)->disdatafb = 1;
++
++ // convert to little endian
++ desc->txdw0 = cpu_to_le32(desc->txdw0);
++ desc->txdw1 = cpu_to_le32(desc->txdw1);
++ desc->txdw2 = cpu_to_le32(desc->txdw2);
++ desc->txdw3 = cpu_to_le32(desc->txdw3);
++ desc->txdw4 = cpu_to_le32(desc->txdw4);
++ desc->txdw5 = cpu_to_le32(desc->txdw5);
++ desc->txdw6 = cpu_to_le32(desc->txdw6);
++ desc->txdw7 = cpu_to_le32(desc->txdw7);
++#ifdef CONFIG_PCI_HCI
++ desc->txdw8 = cpu_to_le32(desc->txdw8);
++ desc->txdw9 = cpu_to_le32(desc->txdw9);
++ desc->txdw10 = cpu_to_le32(desc->txdw10);
++ desc->txdw11 = cpu_to_le32(desc->txdw11);
++ desc->txdw12 = cpu_to_le32(desc->txdw12);
++ desc->txdw13 = cpu_to_le32(desc->txdw13);
++ desc->txdw14 = cpu_to_le32(desc->txdw14);
++ desc->txdw15 = cpu_to_le32(desc->txdw15);
++#endif
++
++ rtl8723a_cal_txdesc_chksum(desc);
++
++ //2 5. coalesce
++ pkt_start = pframe->buf_addr + TXDESC_SIZE;
++ pkt_end = pkt_start + pattrib->last_txcmdsz;
++
++ //3 5.1. make wlan header, make_wlanhdr()
++ hdr = (struct rtw_ieee80211_hdr *)pkt_start;
++ SetFrameSubType(&hdr->frame_ctl, pattrib->subtype);
++ _rtw_memcpy(hdr->addr1, pattrib->dst, ETH_ALEN); // DA
++ _rtw_memcpy(hdr->addr2, pattrib->src, ETH_ALEN); // SA
++ _rtw_memcpy(hdr->addr3, get_bssid(&padapter->mlmepriv), ETH_ALEN); // RA, BSSID
++
++ //3 5.2. make payload
++ ptr = pkt_start + pattrib->hdrlen;
++ get_random_bytes(ptr, pkt_end - ptr);
++
++ pxmitbuf->len = TXDESC_SIZE + pattrib->last_txcmdsz;
++ pxmitbuf->ptail += pxmitbuf->len;
++
++ return pframe;
++}
++
++static void freeloopbackpkt(PADAPTER padapter, struct xmit_frame *pframe)
++{
++ struct xmit_priv *pxmitpriv;
++ struct xmit_buf *pxmitbuf;
++
++
++ pxmitpriv = &padapter->xmitpriv;
++ pxmitbuf = pframe->pxmitbuf;
++
++ rtw_free_xmitframe(pxmitpriv, pframe);
++ rtw_free_xmitbuf(pxmitpriv, pxmitbuf);
++}
++
++extern u32 get_txfifo_hwaddr(struct xmit_frame *pxmitframe);
++
++thread_return lbk_thread(thread_context context)
++{
++ s32 err;
++ PADAPTER padapter;
++ PLOOPBACKDATA ploopback;
++ struct xmit_frame *pxmitframe;
++ u32 cnt, ok, fail, i, headerlen;
++ u32 pktsize;
++ u32 ff_hwaddr;
++
++
++ padapter = (PADAPTER)context;
++ ploopback = padapter->ploopback;
++ if (ploopback == NULL) return -1;
++ cnt = 0;
++ ok = 0;
++ fail = 0;
++
++ daemonize("%s", "RTW_LBK_THREAD");
++ allow_signal(SIGTERM);
++
++ do {
++ if (ploopback->size == 0) {
++ get_random_bytes(&pktsize, 4);
++ pktsize = (pktsize % 1535) + 1; // 1~1535
++ } else
++ pktsize = ploopback->size;
++
++ pxmitframe = createloopbackpkt(padapter, pktsize);
++ if (pxmitframe == NULL) {
++ sprintf(ploopback->msg, "loopback FAIL! 3. create Packet FAIL!");
++ break;
++ }
++
++ ploopback->txsize = TXDESC_SIZE + pxmitframe->attrib.last_txcmdsz;
++ _rtw_memcpy(ploopback->txbuf, pxmitframe->buf_addr, ploopback->txsize);
++
++ ff_hwaddr = get_txfifo_hwaddr(pxmitframe);
++ rtw_write_port(padapter, ff_hwaddr, ploopback->txsize, ploopback->txbuf);
++ cnt++;
++
++ _rtw_down_sema(&ploopback->sema);
++
++{
++ PHAL_DATA_TYPE phal;
++ struct recv_stat *prxstat;
++ struct recv_stat report;
++ PRXREPORT prxreport;
++ u32 drvinfosize;
++ u32 rxpktsize;
++ u8 fcssize;
++
++ prxstat = (struct recv_stat*)ploopback->rxbuf;
++ report.rxdw0 = le32_to_cpu(prxstat->rxdw0);
++ report.rxdw1 = le32_to_cpu(prxstat->rxdw1);
++ report.rxdw2 = le32_to_cpu(prxstat->rxdw2);
++ report.rxdw3 = le32_to_cpu(prxstat->rxdw3);
++ report.rxdw4 = le32_to_cpu(prxstat->rxdw4);
++ report.rxdw5 = le32_to_cpu(prxstat->rxdw5);
++
++ prxreport = (PRXREPORT)&report;
++ drvinfosize = prxreport->drvinfosize << 3;
++ rxpktsize = prxreport->pktlen;
++
++ phal = GET_HAL_DATA(padapter);
++ if (phal->ReceiveConfig & RCR_APPFCS) fcssize = IEEE80211_FCS_LEN;
++ else fcssize = 0;
++
++ if ((ploopback->txsize - TXDESC_SIZE) != (rxpktsize - fcssize)) {
++ printk("%s: cnt=%d, size not match! tx=%d rx=%d\n",
++ __func__, i, ploopback->txsize - TXDESC_SIZE,
++ rxpktsize - fcssize);
++ err = _FALSE;
++ } else {
++ err = _rtw_memcmp(ploopback->txbuf + TXDESC_SIZE,\
++ ploopback->rxbuf + RXDESC_SIZE + drvinfosize,\
++ ploopback->txsize - TXDESC_SIZE);
++ }
++}
++
++ if (err == _TRUE)
++ ok++;
++ else
++ fail++;
++
++ ploopback->txsize = 0;
++ _rtw_memset(ploopback->txbuf, 0, 0x8000);
++ ploopback->rxsize = 0;
++ _rtw_memset(ploopback->rxbuf, 0, 0x8000);
++
++ freeloopbackpkt(padapter, pxmitframe);
++ pxmitframe = NULL;
++
++ if (signal_pending(current)) {
++ flush_signals(current);
++ }
++
++ if ((ploopback->bstop == _TRUE) ||
++ ((ploopback->cnt != 0) && (ploopback->cnt == cnt)))
++ {
++ u32 ok_rate, fail_rate;
++ ok_rate = (ok*100)/cnt;
++ fail_rate = (fail*100)/cnt;
++ sprintf(ploopback->msg, "loopback result: ok=%d%%(%d/%d),error=%d%%(%d/%d)", ok_rate, ok, cnt, fail_rate, fail, cnt);
++ break;
++ }
++ } while (1);
++
++ ploopback->bstop = _TRUE;
++
++ thread_exit();
++}
++
++static void loopbackTest(PADAPTER padapter, u32 cnt, u32 size, u8* pmsg)
++{
++ PLOOPBACKDATA ploopback;
++ u32 len;
++ s32 err;
++
++
++ ploopback = padapter->ploopback;
++
++ if (ploopback)
++ {
++ ploopback->bstop = _TRUE;
++ len = 0;
++ do {
++ len = strlen(ploopback->msg);
++ if (len) break;
++ rtw_msleep_os(1);
++ } while (1);
++ _rtw_memcpy(pmsg, ploopback->msg, len+1);
++ freeLoopback(padapter);
++ return;
++ }
++
++ // create pseudo ad-hoc connection
++ err = initpseudoadhoc(padapter);
++ if (err == _FAIL) {
++ sprintf(pmsg, "loopback FAIL! 1.1 init ad-hoc FAIL!");
++ return;
++ }
++
++ err = createpseudoadhoc(padapter);
++ if (err == _FAIL) {
++ sprintf(pmsg, "loopback FAIL! 1.2 create ad-hoc master FAIL!");
++ return;
++ }
++
++ err = initLoopback(padapter);
++ if (err) {
++ sprintf(pmsg, "loopback FAIL! 2. init FAIL! error code=%d", err);
++ return;
++ }
++
++ ploopback = padapter->ploopback;
++
++ ploopback->bstop = _FALSE;
++ ploopback->cnt = cnt;
++ ploopback->size = size;
++ ploopback->lbkthread = kthread_run(lbk_thread, padapter, "RTW_LBK_THREAD");
++ if (IS_ERR(padapter->lbkthread))
++ {
++ freeLoopback(padapter);
++ sprintf(pmsg, "loopback start FAIL! cnt=%d", cnt);
++ return;
++ }
++
++ sprintf(pmsg, "loopback start! cnt=%d", cnt);
++}
++
++extern u8 _InitPowerOn(PADAPTER padapter);
++extern s32 rtl8723a_FirmwareDownload(PADAPTER padapter);
++
++static int rtw_test(
++ struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++ u32 len;
++ u8 *pbuf, *pch;
++ char *ptmp;
++ u8 *delim = ",";
++ PADAPTER padapter = rtw_netdev_priv(dev);
++
++
++ printk("+%s\n", __func__);
++ len = wrqu->data.length;
++
++ pbuf = (u8*)rtw_zmalloc(len);
++ if (pbuf == NULL) {
++ printk("%s: no memory!\n", __func__);
++ return -ENOMEM;
++ }
++
++ if (copy_from_user(pbuf, wrqu->data.pointer, len)) {
++ rtw_mfree(pbuf, len);
++ printk("%s: copy from user fail!\n", __func__);
++ return -EFAULT;
++ }
++ printk("%s: string=\"%s\"\n", __func__, pbuf);
++
++ ptmp = (char*)pbuf;
++ pch = strsep(&ptmp, delim);
++ if ((pch == NULL) || (strlen(pch) == 0)) {
++ rtw_mfree(pbuf, len);
++ printk("%s: parameter error(level 1)!\n", __func__);
++ return -EFAULT;
++ }
++
++#ifdef RTL8723A_SDIO_LOOPBACK
++ if (strcmp(pch, "loopback") == 0)
++ {
++ s32 cnt = 0;
++ u32 size = 64;
++
++ pch = strsep(&ptmp, delim);
++ if ((pch == NULL) || (strlen(pch) == 0)) {
++ rtw_mfree(pbuf, len);
++ printk("%s: parameter error(level 2)!\n", __func__);
++ return -EFAULT;
++ }
++
++ sscanf(pch, "%d", &cnt);
++ printk("%s: loopback cnt=%d\n", __func__, cnt);
++
++ pch = strsep(&ptmp, delim);
++ if ((pch == NULL) || (strlen(pch) == 0)) {
++ rtw_mfree(pbuf, len);
++ printk("%s: parameter error(level 2)!\n", __func__);
++ return -EFAULT;
++ }
++
++ sscanf(pch, "%d", &size);
++ printk("%s: loopback size=%d\n", __func__, size);
++
++ loopbackTest(padapter, cnt, size, extra);
++ wrqu->data.length = strlen(extra) + 1;
++
++ rtw_mfree(pbuf, len);
++ return 0;
++ }
++#endif
++
++ if (strcmp(pch, "poweron") == 0)
++ {
++ s32 ret;
++
++ ret = _InitPowerOn(padapter);
++ if (_FAIL == ret)
++ printk("%s: power on FAIL!\n", __func__);
++ else
++ printk("%s: power on OK.\n", __func__);
++
++ rtw_mfree(pbuf, len);
++ return 0;
++ }
++
++ if (strcmp(pch, "dlfw") == 0)
++ {
++ s32 ret;
++
++ ret = rtl8723a_FirmwareDownload(padapter);
++ if (_FAIL == ret)
++ printk("%s: download FW FAIL!\n", __func__);
++ else
++ printk("%s: download FW OK.\n", __func__);
++
++ rtw_mfree(pbuf, len);
++ return 0;
++ }
++
++ rtw_mfree(pbuf, len);
++ return 0;
++}
++#else
++static int rtw_test(
++ struct net_device *dev,
++ struct iw_request_info *info,
++ union iwreq_data *wrqu, char *extra)
++{
++ printk("%s\n", __func__);
++ return 0;
++}
++#endif //RTL8723A_SDIO_LOOPBACK
++
++#include <rtw_android.h>
++int rtw_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
++{
++ struct iwreq *wrq = (struct iwreq *)rq;
++ int ret=0;
++
++ switch (cmd)
++ {
++ case RTL_IOCTL_WPA_SUPPLICANT:
++ ret = wpa_supplicant_ioctl(dev, &wrq->u.data);
++ break;
++#ifdef CONFIG_AP_MODE
++ case RTL_IOCTL_HOSTAPD:
++ ret = rtw_hostapd_ioctl(dev, &wrq->u.data);
++ break;
++#ifdef CONFIG_NO_WIRELESS_HANDLERS
++ case SIOCSIWMODE:
++ ret = rtw_wx_set_mode(dev, NULL, &wrq->u, NULL);
++ break;
++#endif
++#endif
++ case (SIOCDEVPRIVATE+1):
++ ret = rtw_android_priv_cmd(dev, rq, cmd);
++ break;
++ default:
++ ret = -EOPNOTSUPP;
++ break;
++ }
++
++ return ret;
++}
++
++static iw_handler rtw_handlers[] =
++{
++ NULL, /* SIOCSIWCOMMIT */
++ rtw_wx_get_name, /* SIOCGIWNAME */
++ dummy, /* SIOCSIWNWID */
++ dummy, /* SIOCGIWNWID */
++ rtw_wx_set_freq, /* SIOCSIWFREQ */
++ rtw_wx_get_freq, /* SIOCGIWFREQ */
++ rtw_wx_set_mode, /* SIOCSIWMODE */
++ rtw_wx_get_mode, /* SIOCGIWMODE */
++ dummy, /* SIOCSIWSENS */
++ rtw_wx_get_sens, /* SIOCGIWSENS */
++ NULL, /* SIOCSIWRANGE */
++ rtw_wx_get_range, /* SIOCGIWRANGE */
++ rtw_wx_set_priv, /* SIOCSIWPRIV */
++ NULL, /* SIOCGIWPRIV */
++ NULL, /* SIOCSIWSTATS */
++ NULL, /* SIOCGIWSTATS */
++ dummy, /* SIOCSIWSPY */
++ dummy, /* SIOCGIWSPY */
++ NULL, /* SIOCGIWTHRSPY */
++ NULL, /* SIOCWIWTHRSPY */
++ rtw_wx_set_wap, /* SIOCSIWAP */
++ rtw_wx_get_wap, /* SIOCGIWAP */
++ rtw_wx_set_mlme, /* request MLME operation; uses struct iw_mlme */
++ dummy, /* SIOCGIWAPLIST -- depricated */
++ rtw_wx_set_scan, /* SIOCSIWSCAN */
++ rtw_wx_get_scan, /* SIOCGIWSCAN */
++ rtw_wx_set_essid, /* SIOCSIWESSID */
++ rtw_wx_get_essid, /* SIOCGIWESSID */
++ dummy, /* SIOCSIWNICKN */
++ rtw_wx_get_nick, /* SIOCGIWNICKN */
++ NULL, /* -- hole -- */
++ NULL, /* -- hole -- */
++ rtw_wx_set_rate, /* SIOCSIWRATE */
++ rtw_wx_get_rate, /* SIOCGIWRATE */
++ rtw_wx_set_rts, /* SIOCSIWRTS */
++ rtw_wx_get_rts, /* SIOCGIWRTS */
++ rtw_wx_set_frag, /* SIOCSIWFRAG */
++ rtw_wx_get_frag, /* SIOCGIWFRAG */
++ dummy, /* SIOCSIWTXPOW */
++ dummy, /* SIOCGIWTXPOW */
++ dummy, /* SIOCSIWRETRY */
++ rtw_wx_get_retry, /* SIOCGIWRETRY */
++ rtw_wx_set_enc, /* SIOCSIWENCODE */
++ rtw_wx_get_enc, /* SIOCGIWENCODE */
++ dummy, /* SIOCSIWPOWER */
++ rtw_wx_get_power, /* SIOCGIWPOWER */
++ NULL, /*---hole---*/
++ NULL, /*---hole---*/
++ rtw_wx_set_gen_ie, /* SIOCSIWGENIE */
++ NULL, /* SIOCGWGENIE */
++ rtw_wx_set_auth, /* SIOCSIWAUTH */
++ NULL, /* SIOCGIWAUTH */
++ rtw_wx_set_enc_ext, /* SIOCSIWENCODEEXT */
++ NULL, /* SIOCGIWENCODEEXT */
++ rtw_wx_set_pmkid, /* SIOCSIWPMKSA */
++ NULL, /*---hole---*/
++};
++
++#if defined(CONFIG_MP_INCLUDED) && defined(CONFIG_MP_IWPRIV_SUPPORT)
++
++static const struct iw_priv_args rtw_private_args[] =
++{
++ { SIOCIWFIRSTPRIV + 0x00, IW_PRIV_TYPE_CHAR | 1024, 0 , ""}, //set
++ { SIOCIWFIRSTPRIV + 0x01, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK , ""},//get
++/* --- sub-ioctls definitions --- */
++ { MP_START , IW_PRIV_TYPE_CHAR | 1024, 0, "mp_start" }, //set
++ { MP_PHYPARA, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_phypara" },//get
++ { MP_STOP , IW_PRIV_TYPE_CHAR | 1024, 0, "mp_stop" }, //set
++ { MP_CHANNEL , IW_PRIV_TYPE_CHAR | 1024 , IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_channel" },//get
++ { MP_BANDWIDTH , IW_PRIV_TYPE_CHAR | 1024, 0, "mp_bandwidth"}, //set
++ { MP_RATE , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_rate" },//get
++ { MP_RESET_STATS , IW_PRIV_TYPE_CHAR | 1024, 0, "mp_reset_stats"},
++ { MP_QUERY , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK , "mp_query"}, //get
++ { MP_NULL, IW_PRIV_TYPE_CHAR | 128, 0,"NULL"},//set
++ { READ_REG , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "read_reg" },
++ { MP_NULL, IW_PRIV_TYPE_CHAR | 128, 0,"NULL"},//set
++ { MP_RATE , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_rate" },
++ { MP_NULL, IW_PRIV_TYPE_CHAR | 128, 0,"NULL"},//set
++ { READ_RF , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "read_rf" },
++ { MP_NULL, IW_PRIV_TYPE_CHAR | 128, 0,"NULL"},//set
++ { MP_PSD , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_psd"},
++ { MP_NULL, IW_PRIV_TYPE_CHAR | 128, 0,"NULL"},//set
++ { MP_DUMP, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_dump" },
++ { MP_NULL, IW_PRIV_TYPE_CHAR | 128, 0,"NULL"},//set
++ { MP_TXPOWER , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_txpower"},
++ { MP_NULL, IW_PRIV_TYPE_CHAR | 128, 0,"NULL"},//set
++ { MP_ANT_TX , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_ant_tx"},
++ { MP_NULL, IW_PRIV_TYPE_CHAR | 128, 0,"NULL"},//set
++ { MP_ANT_RX , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_ant_rx"},
++ { MP_NULL, IW_PRIV_TYPE_CHAR | 128, 0,"NULL"},//set
++ { WRITE_REG , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "write_reg" },
++ { MP_NULL, IW_PRIV_TYPE_CHAR | 128, 0,"NULL"},//set
++ { WRITE_RF , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "write_rf" },
++ { MP_NULL, IW_PRIV_TYPE_CHAR | 128, 0,"NULL"},//set
++ { MP_CTX , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_ctx"},
++ { MP_NULL, IW_PRIV_TYPE_CHAR | 128, 0,"NULL"},//set
++ { MP_ARX , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_arx"},
++ { MP_ANT_RX , IW_PRIV_TYPE_CHAR | 1024, 0, "mp_ant_rx"},
++ { MP_THER , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_ther"},
++ { EFUSE_SET, IW_PRIV_TYPE_CHAR | 1024, 0, "efuse_set" },
++ { EFUSE_GET, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "efuse_get" },
++ { MP_NULL , IW_PRIV_TYPE_CHAR | 1024, 0, "NULL"},
++ { MP_PWRTRK, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_pwrtrk" },
++ { MP_IOCTL, IW_PRIV_TYPE_CHAR | 1024, 0, "mp_ioctl"}, // mp_ioctl
++
++
++ { SIOCIWFIRSTPRIV + 0x02, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK , "test"},//set
++};
++
++
++static iw_handler rtw_private_handler[] =
++{
++ rtw_mp_set,
++ rtw_mp_get,
++};
++
++#else // not inlucde MP
++
++static const struct iw_priv_args rtw_private_args[] = {
++ {
++ SIOCIWFIRSTPRIV + 0x0,
++ IW_PRIV_TYPE_CHAR | 0x7FF, 0, "write"
++ },
++ {
++ SIOCIWFIRSTPRIV + 0x1,
++ IW_PRIV_TYPE_CHAR | 0x7FF,
++ IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_FIXED | IFNAMSIZ, "read"
++ },
++ {
++ SIOCIWFIRSTPRIV + 0x2, 0, 0, "driver_ext"
++ },
++ {
++ SIOCIWFIRSTPRIV + 0x3, 0, 0, "mp_ioctl"
++ },
++ {
++ SIOCIWFIRSTPRIV + 0x4,
++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "apinfo"
++ },
++ {
++ SIOCIWFIRSTPRIV + 0x5,
++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 2, 0, "setpid"
++ },
++ {
++ SIOCIWFIRSTPRIV + 0x6,
++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "wps_start"
++ },
++//for PLATFORM_MT53XX
++ {
++ SIOCIWFIRSTPRIV + 0x7,
++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "get_sensitivity"
++ },
++ {
++ SIOCIWFIRSTPRIV + 0x8,
++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "wps_prob_req_ie"
++ },
++ {
++ SIOCIWFIRSTPRIV + 0x9,
++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "wps_assoc_req_ie"
++ },
++
++//for RTK_DMP_PLATFORM
++ {
++ SIOCIWFIRSTPRIV + 0xA,
++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "channel_plan"
++ },
++
++ {
++ SIOCIWFIRSTPRIV + 0xB,
++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 2, 0, "dbg"
++ },
++ {
++ SIOCIWFIRSTPRIV + 0xC,
++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 3, 0, "rfw"
++ },
++ {
++ SIOCIWFIRSTPRIV + 0xD,
++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 2, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_FIXED | IFNAMSIZ, "rfr"
++ },
++#ifdef CONFIG_WOWLAN
++ {
++ SIOCIWFIRSTPRIV + 0xE,0,0, "wowlan_ctrl"
++ },
++#endif // CONFIG_WOWLAN
++ {
++ SIOCIWFIRSTPRIV + 0x10,
++ IW_PRIV_TYPE_CHAR | 1024, 0, "p2p_set"
++ },
++ {
++ SIOCIWFIRSTPRIV + 0x11,
++ IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK , "p2p_get"
++ },
++ {
++ SIOCIWFIRSTPRIV + 0x12, 0, 0, "NULL"
++ },
++ {
++ SIOCIWFIRSTPRIV + 0x13,
++ IW_PRIV_TYPE_CHAR | 64, IW_PRIV_TYPE_CHAR | 64 , "p2p_get2"
++ },
++ {
++ SIOCIWFIRSTPRIV + 0x14,
++ IW_PRIV_TYPE_CHAR | 64, 0, "tdls"
++ },
++ {
++ SIOCIWFIRSTPRIV + 0x15,
++ IW_PRIV_TYPE_CHAR | P2P_PRIVATE_IOCTL_SET_LEN, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_FIXED | P2P_PRIVATE_IOCTL_SET_LEN , "tdls_get"
++ },
++ {
++ SIOCIWFIRSTPRIV + 0x16,
++ IW_PRIV_TYPE_CHAR | 64, 0, "pm_set"
++ },
++
++ {SIOCIWFIRSTPRIV + 0x18, IW_PRIV_TYPE_CHAR | IFNAMSIZ , 0 , "rereg_nd_name"},
++
++ {SIOCIWFIRSTPRIV + 0x1A, IW_PRIV_TYPE_CHAR | 128, 0, "efuse_set"},
++ {SIOCIWFIRSTPRIV + 0x1B, IW_PRIV_TYPE_CHAR | 128, IW_PRIV_TYPE_CHAR |IW_PRIV_SIZE_FIXED |0x700 ,"efuse_get"},
++ {
++ SIOCIWFIRSTPRIV + 0x1D,
++ IW_PRIV_TYPE_CHAR | 40, IW_PRIV_TYPE_CHAR | 0x7FF, "test"
++ },
++#ifdef CONFIG_INTEL_WIDI
++ {
++ SIOCIWFIRSTPRIV + 0x1E,
++ IW_PRIV_TYPE_CHAR | 1024, 0, "widi_set"
++ },
++ {
++ SIOCIWFIRSTPRIV + 0x1F,
++ IW_PRIV_TYPE_CHAR | 128, 0, "widi_prob_req"
++ },
++#endif // CONFIG_INTEL_WIDI
++};
++
++static iw_handler rtw_private_handler[] =
++{
++ rtw_wx_write32, //0x00
++ rtw_wx_read32, //0x01
++ rtw_drvext_hdl, //0x02
++ rtw_mp_ioctl_hdl, //0x03
++
++// for MM DTV platform
++ rtw_get_ap_info, //0x04
++
++ rtw_set_pid, //0x05
++ rtw_wps_start, //0x06
++
++// for PLATFORM_MT53XX
++ rtw_wx_get_sensitivity, //0x07
++ rtw_wx_set_mtk_wps_probe_ie, //0x08
++ rtw_wx_set_mtk_wps_ie, //0x09
++
++// for RTK_DMP_PLATFORM
++// Set Channel depend on the country code
++ rtw_wx_set_channel_plan, //0x0A
++
++ rtw_dbg_port, //0x0B
++ rtw_wx_write_rf, //0x0C
++ rtw_wx_read_rf, //0x0D
++
++#ifdef CONFIG_WOWLAN
++ rtw_wowlan_ctrl, //0x0E
++#else
++ rtw_wx_priv_null, //0x0E
++#endif //CONFIG_WOWLAN
++ rtw_wx_priv_null, //0x0F
++
++ rtw_p2p_set, //0x10
++ rtw_p2p_get, //0x11
++ NULL, //0x12
++ rtw_p2p_get2, //0x13
++
++ rtw_tdls, //0x14
++ rtw_tdls_get, //0x15
++
++ rtw_pm_set, //0x16
++ rtw_wx_priv_null, //0x17
++ rtw_rereg_nd_name, //0x18
++ rtw_wx_priv_null, //0x19
++
++ rtw_mp_efuse_set, //0x1A
++ rtw_mp_efuse_get, //0x1B
++ NULL, // 0x1C is reserved for hostapd
++ rtw_test , // 0x1D
++#ifdef CONFIG_INTEL_WIDI
++ rtw_widi_set, //0x1E
++ rtw_widi_set_probe_request, //0x1F
++#endif // CONFIG_INTEL_WIDI
++};
++
++#endif // #if defined(CONFIG_MP_INCLUDED) && defined(CONFIG_MP_IWPRIV_SUPPORT)
++
++#if WIRELESS_EXT >= 17
++static struct iw_statistics *rtw_get_wireless_stats(struct net_device *dev)
++{
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++ struct iw_statistics *piwstats=&padapter->iwstats;
++ int tmp_level = 0;
++ int tmp_qual = 0;
++ int tmp_noise = 0;
++
++ if (check_fwstate(&padapter->mlmepriv, _FW_LINKED) != _TRUE)
++ {
++ piwstats->qual.qual = 0;
++ piwstats->qual.level = 0;
++ piwstats->qual.noise = 0;
++ //DBG_871X("No link level:%d, qual:%d, noise:%d\n", tmp_level, tmp_qual, tmp_noise);
++ }
++ else{
++ #ifdef CONFIG_SIGNAL_DISPLAY_DBM
++ tmp_level = translate_percentage_to_dbm(padapter->recvpriv.signal_strength);
++ #else
++ tmp_level = padapter->recvpriv.signal_strength;
++ #endif
++
++ tmp_qual = padapter->recvpriv.signal_qual;
++ tmp_noise =padapter->recvpriv.noise;
++ //DBG_871X("level:%d, qual:%d, noise:%d, rssi (%d)\n", tmp_level, tmp_qual, tmp_noise,padapter->recvpriv.rssi);
++
++ piwstats->qual.level = tmp_level;
++ piwstats->qual.qual = tmp_qual;
++ piwstats->qual.noise = tmp_noise;
++ }
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,14))
++ piwstats->qual.updated = IW_QUAL_ALL_UPDATED ;//|IW_QUAL_DBM;
++#else
++#ifdef RTK_DMP_PLATFORM
++ //IW_QUAL_DBM= 0x8, if driver use this flag, wireless extension will show value of dbm.
++ //remove this flag for show percentage 0~100
++ piwstats->qual.updated = 0x07;
++#else
++ piwstats->qual.updated = 0x0f;
++#endif
++#endif
++
++ #ifdef CONFIG_SIGNAL_DISPLAY_DBM
++ piwstats->qual.updated = piwstats->qual.updated | IW_QUAL_DBM;
++ #endif
++
++ return &padapter->iwstats;
++}
++#endif
++
++#ifdef CONFIG_WIRELESS_EXT
++struct iw_handler_def rtw_handlers_def =
++{
++ .standard = rtw_handlers,
++ .num_standard = sizeof(rtw_handlers) / sizeof(iw_handler),
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,33)) || defined(CONFIG_WEXT_PRIV)
++ .private = rtw_private_handler,
++ .private_args = (struct iw_priv_args *)rtw_private_args,
++ .num_private = sizeof(rtw_private_handler) / sizeof(iw_handler),
++ .num_private_args = sizeof(rtw_private_args) / sizeof(struct iw_priv_args),
++#endif
++#if WIRELESS_EXT >= 17
++ .get_wireless_stats = rtw_get_wireless_stats,
++#endif
++};
++#endif
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/os_dep/linux/mlme_linux.c linux-xbian-rpi/drivers/net/wireless/rtl8192cu/os_dep/linux/mlme_linux.c
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/os_dep/linux/mlme_linux.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/os_dep/linux/mlme_linux.c 2015-07-28 01:20:58.429213356 +0200
+@@ -0,0 +1,585 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++
++
++#define _MLME_OSDEP_C_
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++#include <mlme_osdep.h>
++
++
++#ifdef RTK_DMP_PLATFORM
++void Linkup_workitem_callback(struct work_struct *work)
++{
++ struct mlme_priv *pmlmepriv = container_of(work, struct mlme_priv, Linkup_workitem);
++ _adapter *padapter = container_of(pmlmepriv, _adapter, mlmepriv);
++
++_func_enter_;
++
++ RT_TRACE(_module_mlme_osdep_c_,_drv_info_,("+ Linkup_workitem_callback\n"));
++
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,12))
++ kobject_uevent(&padapter->pnetdev->dev.kobj, KOBJ_LINKUP);
++#else
++ kobject_hotplug(&padapter->pnetdev->class_dev.kobj, KOBJ_LINKUP);
++#endif
++
++_func_exit_;
++}
++
++void Linkdown_workitem_callback(struct work_struct *work)
++{
++ struct mlme_priv *pmlmepriv = container_of(work, struct mlme_priv, Linkdown_workitem);
++ _adapter *padapter = container_of(pmlmepriv, _adapter, mlmepriv);
++
++_func_enter_;
++
++ RT_TRACE(_module_mlme_osdep_c_,_drv_info_,("+ Linkdown_workitem_callback\n"));
++
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,12))
++ kobject_uevent(&padapter->pnetdev->dev.kobj, KOBJ_LINKDOWN);
++#else
++ kobject_hotplug(&padapter->pnetdev->class_dev.kobj, KOBJ_LINKDOWN);
++#endif
++
++_func_exit_;
++}
++#endif
++
++
++/*
++void sitesurvey_ctrl_handler(void *FunctionContext)
++{
++ _adapter *adapter = (_adapter *)FunctionContext;
++
++ _sitesurvey_ctrl_handler(adapter);
++
++ _set_timer(&adapter->mlmepriv.sitesurveyctrl.sitesurvey_ctrl_timer, 3000);
++}
++*/
++
++void rtw_join_timeout_handler (void *FunctionContext)
++{
++ _adapter *adapter = (_adapter *)FunctionContext;
++ _rtw_join_timeout_handler(adapter);
++}
++
++
++void _rtw_scan_timeout_handler (void *FunctionContext)
++{
++ _adapter *adapter = (_adapter *)FunctionContext;
++ rtw_scan_timeout_handler(adapter);
++}
++
++
++void _dynamic_check_timer_handlder (void *FunctionContext)
++{
++ _adapter *adapter = (_adapter *)FunctionContext;
++
++ rtw_dynamic_check_timer_handlder(adapter);
++
++ _set_timer(&adapter->mlmepriv.dynamic_chk_timer, 2000);
++}
++
++#ifdef CONFIG_SET_SCAN_DENY_TIMER
++void _rtw_set_scan_deny_timer_hdl(void *FunctionContext)
++{
++ _adapter *adapter = (_adapter *)FunctionContext;
++ rtw_set_scan_deny_timer_hdl(adapter);
++}
++#endif
++
++
++void rtw_init_mlme_timer(_adapter *padapter)
++{
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++
++ _init_timer(&(pmlmepriv->assoc_timer), padapter->pnetdev, rtw_join_timeout_handler, padapter);
++ //_init_timer(&(pmlmepriv->sitesurveyctrl.sitesurvey_ctrl_timer), padapter->pnetdev, sitesurvey_ctrl_handler, padapter);
++ _init_timer(&(pmlmepriv->scan_to_timer), padapter->pnetdev, _rtw_scan_timeout_handler, padapter);
++
++ _init_timer(&(pmlmepriv->dynamic_chk_timer), padapter->pnetdev, _dynamic_check_timer_handlder, padapter);
++
++ #ifdef CONFIG_SET_SCAN_DENY_TIMER
++ _init_timer(&(pmlmepriv->set_scan_deny_timer), padapter->pnetdev, _rtw_set_scan_deny_timer_hdl, padapter);
++ #endif
++
++#ifdef RTK_DMP_PLATFORM
++ _init_workitem(&(pmlmepriv->Linkup_workitem), Linkup_workitem_callback, padapter);
++ _init_workitem(&(pmlmepriv->Linkdown_workitem), Linkdown_workitem_callback, padapter);
++#endif
++
++}
++
++extern void rtw_indicate_wx_assoc_event(_adapter *padapter);
++extern void rtw_indicate_wx_disassoc_event(_adapter *padapter);
++
++void rtw_os_indicate_connect(_adapter *adapter)
++{
++
++_func_enter_;
++
++#ifdef CONFIG_IOCTL_CFG80211
++ rtw_cfg80211_indicate_connect(adapter);
++#endif //CONFIG_IOCTL_CFG80211
++
++ rtw_indicate_wx_assoc_event(adapter);
++ netif_carrier_on(adapter->pnetdev);
++
++ if(adapter->pid[2] !=0)
++ rtw_signal_process(adapter->pid[2], SIGALRM);
++
++#ifdef RTK_DMP_PLATFORM
++ _set_workitem(&adapter->mlmepriv.Linkup_workitem);
++#endif
++
++_func_exit_;
++
++}
++
++extern void indicate_wx_scan_complete_event(_adapter *padapter);
++void rtw_os_indicate_scan_done( _adapter *padapter, bool aborted)
++{
++#ifdef CONFIG_IOCTL_CFG80211
++ rtw_cfg80211_indicate_scan_done(wdev_to_priv(padapter->rtw_wdev), aborted);
++#endif
++ indicate_wx_scan_complete_event(padapter);
++}
++
++static RT_PMKID_LIST backupPMKIDList[ NUM_PMKID_CACHE ];
++void rtw_reset_securitypriv( _adapter *adapter )
++{
++ u8 backupPMKIDIndex = 0;
++ u8 backupTKIPCountermeasure = 0x00;
++ u32 backupTKIPcountermeasure_time = 0;
++ // add for CONFIG_IEEE80211W, none 11w also can use
++ _irqL irqL;
++ struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
++
++ _enter_critical_bh(&adapter->security_key_mutex, &irqL);
++
++ if(adapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X)//802.1x
++ {
++ // Added by Albert 2009/02/18
++ // We have to backup the PMK information for WiFi PMK Caching test item.
++ //
++ // Backup the btkip_countermeasure information.
++ // When the countermeasure is trigger, the driver have to disconnect with AP for 60 seconds.
++
++ _rtw_memset( &backupPMKIDList[ 0 ], 0x00, sizeof( RT_PMKID_LIST ) * NUM_PMKID_CACHE );
++
++ _rtw_memcpy( &backupPMKIDList[ 0 ], &adapter->securitypriv.PMKIDList[ 0 ], sizeof( RT_PMKID_LIST ) * NUM_PMKID_CACHE );
++ backupPMKIDIndex = adapter->securitypriv.PMKIDIndex;
++ backupTKIPCountermeasure = adapter->securitypriv.btkip_countermeasure;
++ backupTKIPcountermeasure_time = adapter->securitypriv.btkip_countermeasure_time;
++#ifdef CONFIG_IEEE80211W
++ //reset RX BIP packet number
++ pmlmeext->mgnt_80211w_IPN_rx = 0;
++#endif //CONFIG_IEEE80211W
++ _rtw_memset((unsigned char *)&adapter->securitypriv, 0, sizeof (struct security_priv));
++ //_init_timer(&(adapter->securitypriv.tkip_timer),adapter->pnetdev, rtw_use_tkipkey_handler, adapter);
++
++ // Added by Albert 2009/02/18
++ // Restore the PMK information to securitypriv structure for the following connection.
++ _rtw_memcpy( &adapter->securitypriv.PMKIDList[ 0 ], &backupPMKIDList[ 0 ], sizeof( RT_PMKID_LIST ) * NUM_PMKID_CACHE );
++ adapter->securitypriv.PMKIDIndex = backupPMKIDIndex;
++ adapter->securitypriv.btkip_countermeasure = backupTKIPCountermeasure;
++ adapter->securitypriv.btkip_countermeasure_time = backupTKIPcountermeasure_time;
++
++ adapter->securitypriv.ndisauthtype = Ndis802_11AuthModeOpen;
++ adapter->securitypriv.ndisencryptstatus = Ndis802_11WEPDisabled;
++
++ }
++ else //reset values in securitypriv
++ {
++ //if(adapter->mlmepriv.fw_state & WIFI_STATION_STATE)
++ //{
++ struct security_priv *psec_priv=&adapter->securitypriv;
++
++ psec_priv->dot11AuthAlgrthm =dot11AuthAlgrthm_Open; //open system
++ psec_priv->dot11PrivacyAlgrthm = _NO_PRIVACY_;
++ psec_priv->dot11PrivacyKeyIndex = 0;
++
++ psec_priv->dot118021XGrpPrivacy = _NO_PRIVACY_;
++ psec_priv->dot118021XGrpKeyid = 1;
++
++ psec_priv->ndisauthtype = Ndis802_11AuthModeOpen;
++ psec_priv->ndisencryptstatus = Ndis802_11WEPDisabled;
++ //}
++ }
++ // add for CONFIG_IEEE80211W, none 11w also can use
++ _exit_critical_bh(&adapter->security_key_mutex, &irqL);
++}
++
++void rtw_os_indicate_disconnect( _adapter *adapter )
++{
++ //RT_PMKID_LIST backupPMKIDList[ NUM_PMKID_CACHE ];
++
++_func_enter_;
++
++ netif_carrier_off(adapter->pnetdev); // Do it first for tx broadcast pkt after disconnection issue!
++
++#ifdef CONFIG_IOCTL_CFG80211
++ rtw_cfg80211_indicate_disconnect(adapter);
++#endif //CONFIG_IOCTL_CFG80211
++
++ rtw_indicate_wx_disassoc_event(adapter);
++
++#ifdef RTK_DMP_PLATFORM
++ _set_workitem(&adapter->mlmepriv.Linkdown_workitem);
++#endif
++ //modify for CONFIG_IEEE80211W, none 11w also can use the same command
++ rtw_reset_securitypriv_cmd(adapter);
++
++_func_exit_;
++
++}
++
++void rtw_report_sec_ie(_adapter *adapter,u8 authmode,u8 *sec_ie)
++{
++ uint len;
++ u8 *buff,*p,i;
++ union iwreq_data wrqu;
++
++_func_enter_;
++
++ RT_TRACE(_module_mlme_osdep_c_,_drv_info_,("+rtw_report_sec_ie, authmode=%d\n", authmode));
++
++ buff = NULL;
++ if(authmode==_WPA_IE_ID_)
++ {
++ RT_TRACE(_module_mlme_osdep_c_,_drv_info_,("rtw_report_sec_ie, authmode=%d\n", authmode));
++
++ buff = rtw_malloc(IW_CUSTOM_MAX);
++
++ _rtw_memset(buff,0,IW_CUSTOM_MAX);
++
++ p=buff;
++
++ p+=sprintf(p,"ASSOCINFO(ReqIEs=");
++
++ len = sec_ie[1]+2;
++ len = (len < IW_CUSTOM_MAX) ? len:IW_CUSTOM_MAX;
++
++ for(i=0;i<len;i++){
++ p+=sprintf(p,"%02x",sec_ie[i]);
++ }
++
++ p+=sprintf(p,")");
++
++ _rtw_memset(&wrqu,0,sizeof(wrqu));
++
++ wrqu.data.length=p-buff;
++
++ wrqu.data.length = (wrqu.data.length<IW_CUSTOM_MAX) ? wrqu.data.length:IW_CUSTOM_MAX;
++
++ wireless_send_event(adapter->pnetdev,IWEVCUSTOM,&wrqu,buff);
++
++ if(buff)
++ rtw_mfree(buff, IW_CUSTOM_MAX);
++
++ }
++
++_func_exit_;
++
++}
++
++void _survey_timer_hdl (void *FunctionContext)
++{
++ _adapter *padapter = (_adapter *)FunctionContext;
++
++ survey_timer_hdl(padapter);
++}
++
++void _link_timer_hdl (void *FunctionContext)
++{
++ _adapter *padapter = (_adapter *)FunctionContext;
++ link_timer_hdl(padapter);
++}
++
++void _addba_timer_hdl(void *FunctionContext)
++{
++ struct sta_info *psta = (struct sta_info *)FunctionContext;
++ addba_timer_hdl(psta);
++}
++
++#ifdef CONFIG_IEEE80211W
++void _sa_query_timer_hdl (void *FunctionContext)
++{
++ _adapter *padapter = (_adapter *)FunctionContext;
++ sa_query_timer_hdl(padapter);
++}
++#endif //CONFIG_IEEE80211W
++
++void init_addba_retry_timer(_adapter *padapter, struct sta_info *psta)
++{
++
++ _init_timer(&psta->addba_retry_timer, padapter->pnetdev, _addba_timer_hdl, psta);
++}
++
++/*
++void _reauth_timer_hdl(void *FunctionContext)
++{
++ _adapter *padapter = (_adapter *)FunctionContext;
++ reauth_timer_hdl(padapter);
++}
++
++void _reassoc_timer_hdl(void *FunctionContext)
++{
++ _adapter *padapter = (_adapter *)FunctionContext;
++ reassoc_timer_hdl(padapter);
++}
++*/
++
++void init_mlme_ext_timer(_adapter *padapter)
++{
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++
++ _init_timer(&pmlmeext->survey_timer, padapter->pnetdev, _survey_timer_hdl, padapter);
++ _init_timer(&pmlmeext->link_timer, padapter->pnetdev, _link_timer_hdl, padapter);
++#ifdef CONFIG_IEEE80211W
++ _init_timer(&pmlmeext->sa_query_timer, padapter->pnetdev, _sa_query_timer_hdl, padapter);
++#endif //CONFIG_IEEE80211W
++ //_init_timer(&pmlmeext->ADDBA_timer, padapter->pnetdev, _addba_timer_hdl, padapter);
++
++ //_init_timer(&pmlmeext->reauth_timer, padapter->pnetdev, _reauth_timer_hdl, padapter);
++ //_init_timer(&pmlmeext->reassoc_timer, padapter->pnetdev, _reassoc_timer_hdl, padapter);
++}
++
++#ifdef CONFIG_AP_MODE
++
++void rtw_indicate_sta_assoc_event(_adapter *padapter, struct sta_info *psta)
++{
++ union iwreq_data wrqu;
++ struct sta_priv *pstapriv = &padapter->stapriv;
++
++ if(psta==NULL)
++ return;
++
++ if(psta->aid > NUM_STA)
++ return;
++
++ if(pstapriv->sta_aid[psta->aid - 1] != psta)
++ return;
++
++
++ wrqu.addr.sa_family = ARPHRD_ETHER;
++
++ _rtw_memcpy(wrqu.addr.sa_data, psta->hwaddr, ETH_ALEN);
++
++ DBG_871X("+rtw_indicate_sta_assoc_event\n");
++
++ wireless_send_event(padapter->pnetdev, IWEVREGISTERED, &wrqu, NULL);
++
++}
++
++void rtw_indicate_sta_disassoc_event(_adapter *padapter, struct sta_info *psta)
++{
++ union iwreq_data wrqu;
++ struct sta_priv *pstapriv = &padapter->stapriv;
++
++ if(psta==NULL)
++ return;
++
++ if(psta->aid > NUM_STA)
++ return;
++
++ if(pstapriv->sta_aid[psta->aid - 1] != psta)
++ return;
++
++
++ wrqu.addr.sa_family = ARPHRD_ETHER;
++
++ _rtw_memcpy(wrqu.addr.sa_data, psta->hwaddr, ETH_ALEN);
++
++ DBG_871X("+rtw_indicate_sta_disassoc_event\n");
++
++ wireless_send_event(padapter->pnetdev, IWEVEXPIRED, &wrqu, NULL);
++
++}
++
++
++#ifdef CONFIG_HOSTAPD_MLME
++
++static int mgnt_xmit_entry(struct sk_buff *skb, struct net_device *pnetdev)
++{
++ struct hostapd_priv *phostapdpriv = rtw_netdev_priv(pnetdev);
++ _adapter *padapter = (_adapter *)phostapdpriv->padapter;
++
++ //DBG_871X("%s\n", __FUNCTION__);
++
++ return rtw_hal_hostap_mgnt_xmit_entry(padapter, skb);
++}
++
++static int mgnt_netdev_open(struct net_device *pnetdev)
++{
++ struct hostapd_priv *phostapdpriv = rtw_netdev_priv(pnetdev);
++
++ DBG_871X("mgnt_netdev_open: MAC Address:" MAC_FMT "\n", MAC_ARG(pnetdev->dev_addr));
++
++
++ init_usb_anchor(&phostapdpriv->anchored);
++
++ if(!rtw_netif_queue_stopped(pnetdev))
++ rtw_netif_start_queue(pnetdev);
++ else
++ rtw_netif_wake_queue(pnetdev);
++
++
++ netif_carrier_on(pnetdev);
++
++ //rtw_write16(phostapdpriv->padapter, 0x0116, 0x0100);//only excluding beacon
++
++ return 0;
++}
++static int mgnt_netdev_close(struct net_device *pnetdev)
++{
++ struct hostapd_priv *phostapdpriv = rtw_netdev_priv(pnetdev);
++
++ DBG_871X("%s\n", __FUNCTION__);
++
++ usb_kill_anchored_urbs(&phostapdpriv->anchored);
++
++ netif_carrier_off(pnetdev);
++
++ if (!rtw_netif_queue_stopped(pnetdev))
++ rtw_netif_stop_queue(pnetdev);
++
++ //rtw_write16(phostapdpriv->padapter, 0x0116, 0x3f3f);
++
++ return 0;
++}
++
++#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,29))
++static const struct net_device_ops rtl871x_mgnt_netdev_ops = {
++ .ndo_open = mgnt_netdev_open,
++ .ndo_stop = mgnt_netdev_close,
++ .ndo_start_xmit = mgnt_xmit_entry,
++ //.ndo_set_mac_address = r871x_net_set_mac_address,
++ //.ndo_get_stats = r871x_net_get_stats,
++ //.ndo_do_ioctl = r871x_mp_ioctl,
++};
++#endif
++
++int hostapd_mode_init(_adapter *padapter)
++{
++ unsigned char mac[ETH_ALEN];
++ struct hostapd_priv *phostapdpriv;
++ struct net_device *pnetdev;
++
++ pnetdev = rtw_alloc_etherdev(sizeof(struct hostapd_priv));
++ if (!pnetdev)
++ return -ENOMEM;
++
++ //SET_MODULE_OWNER(pnetdev);
++ ether_setup(pnetdev);
++
++ //pnetdev->type = ARPHRD_IEEE80211;
++
++ phostapdpriv = rtw_netdev_priv(pnetdev);
++ phostapdpriv->pmgnt_netdev = pnetdev;
++ phostapdpriv->padapter= padapter;
++ padapter->phostapdpriv = phostapdpriv;
++
++ //pnetdev->init = NULL;
++
++#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,29))
++
++ DBG_871X("register rtl871x_mgnt_netdev_ops to netdev_ops\n");
++
++ pnetdev->netdev_ops = &rtl871x_mgnt_netdev_ops;
++
++#else
++
++ pnetdev->open = mgnt_netdev_open;
++
++ pnetdev->stop = mgnt_netdev_close;
++
++ pnetdev->hard_start_xmit = mgnt_xmit_entry;
++
++ //pnetdev->set_mac_address = r871x_net_set_mac_address;
++
++ //pnetdev->get_stats = r871x_net_get_stats;
++
++ //pnetdev->do_ioctl = r871x_mp_ioctl;
++
++#endif
++
++ pnetdev->watchdog_timeo = HZ; /* 1 second timeout */
++
++ //pnetdev->wireless_handlers = NULL;
++
++#ifdef CONFIG_TCP_CSUM_OFFLOAD_TX
++ pnetdev->features |= NETIF_F_IP_CSUM;
++#endif
++
++
++
++ if(dev_alloc_name(pnetdev,"mgnt.wlan%d") < 0)
++ {
++ DBG_871X("hostapd_mode_init(): dev_alloc_name, fail! \n");
++ }
++
++
++ //SET_NETDEV_DEV(pnetdev, pintfpriv->udev);
++
++
++ mac[0]=0x00;
++ mac[1]=0xe0;
++ mac[2]=0x4c;
++ mac[3]=0x87;
++ mac[4]=0x11;
++ mac[5]=0x12;
++
++ _rtw_memcpy(pnetdev->dev_addr, mac, ETH_ALEN);
++
++
++ netif_carrier_off(pnetdev);
++
++
++ /* Tell the network stack we exist */
++ if (register_netdev(pnetdev) != 0)
++ {
++ DBG_871X("hostapd_mode_init(): register_netdev fail!\n");
++
++ if(pnetdev)
++ {
++ rtw_free_netdev(pnetdev);
++ }
++ }
++
++ return 0;
++
++}
++
++void hostapd_mode_unload(_adapter *padapter)
++{
++ struct hostapd_priv *phostapdpriv = padapter->phostapdpriv;
++ struct net_device *pnetdev = phostapdpriv->pmgnt_netdev;
++
++ unregister_netdev(pnetdev);
++ rtw_free_netdev(pnetdev);
++
++}
++
++#endif
++#endif
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/os_dep/linux/os_intfs.c linux-xbian-rpi/drivers/net/wireless/rtl8192cu/os_dep/linux/os_intfs.c
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/os_dep/linux/os_intfs.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/os_dep/linux/os_intfs.c 2015-07-28 01:20:58.429213356 +0200
+@@ -0,0 +1,2748 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#define _OS_INTFS_C_
++
++#include <drv_conf.h>
++
++#if defined (PLATFORM_LINUX) && defined (PLATFORM_WINDOWS)
++
++#error "Shall be Linux or Windows, but not both!\n"
++
++#endif
++
++#include <osdep_service.h>
++#include <drv_types.h>
++#include <xmit_osdep.h>
++#include <recv_osdep.h>
++#include <hal_intf.h>
++#include <rtw_ioctl.h>
++#include <rtw_version.h>
++
++#ifdef CONFIG_USB_HCI
++#include <usb_osintf.h>
++#endif
++
++#ifdef CONFIG_PCI_HCI
++#include <pci_osintf.h>
++#endif
++
++#ifdef CONFIG_BR_EXT
++#include <rtw_br_ext.h>
++#endif //CONFIG_BR_EXT
++
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION("Realtek Wireless Lan Driver");
++MODULE_AUTHOR("Realtek Semiconductor Corp.");
++MODULE_VERSION(DRIVERVERSION);
++
++/* module param defaults */
++int rtw_chip_version = 0x00;
++int rtw_rfintfs = HWPI;
++int rtw_lbkmode = 0;//RTL8712_AIR_TRX;
++
++
++int rtw_network_mode = Ndis802_11IBSS;//Ndis802_11Infrastructure;//infra, ad-hoc, auto
++//NDIS_802_11_SSID ssid;
++int rtw_channel = 1;//ad-hoc support requirement
++int rtw_wireless_mode = WIRELESS_11BG_24N;
++int rtw_vrtl_carrier_sense = AUTO_VCS;
++int rtw_vcs_type = RTS_CTS;//*
++int rtw_rts_thresh = 2347;//*
++int rtw_frag_thresh = 2346;//*
++int rtw_preamble = PREAMBLE_LONG;//long, short, auto
++int rtw_scan_mode = 1;//active, passive
++int rtw_adhoc_tx_pwr = 1;
++int rtw_soft_ap = 0;
++//int smart_ps = 1;
++#ifdef CONFIG_POWER_SAVING
++int rtw_power_mgnt = 1;
++#ifdef CONFIG_IPS_LEVEL_2
++int rtw_ips_mode = IPS_LEVEL_2;
++#else
++int rtw_ips_mode = IPS_NORMAL;
++#endif
++#else
++int rtw_power_mgnt = PS_MODE_ACTIVE;
++int rtw_ips_mode = IPS_NONE;
++#endif
++module_param(rtw_ips_mode, int, 0644);
++MODULE_PARM_DESC(rtw_ips_mode,"The default IPS mode");
++
++int rtw_radio_enable = 1;
++int rtw_long_retry_lmt = 7;
++int rtw_short_retry_lmt = 7;
++int rtw_busy_thresh = 40;
++//int qos_enable = 0; //*
++int rtw_ack_policy = NORMAL_ACK;
++#ifdef CONFIG_MP_INCLUDED
++int rtw_mp_mode = 1;
++#else
++int rtw_mp_mode = 0;
++#endif
++int rtw_software_encrypt = 0;
++int rtw_software_decrypt = 0;
++
++int rtw_acm_method = 0;// 0:By SW 1:By HW.
++
++int rtw_wmm_enable = 1;// default is set to enable the wmm.
++int rtw_uapsd_enable = 0;
++int rtw_uapsd_max_sp = NO_LIMIT;
++int rtw_uapsd_acbk_en = 0;
++int rtw_uapsd_acbe_en = 0;
++int rtw_uapsd_acvi_en = 0;
++int rtw_uapsd_acvo_en = 0;
++
++#ifdef CONFIG_80211N_HT
++int rtw_ht_enable = 1;
++int rtw_cbw40_enable = 3; // 0 :diable, bit(0): enable 2.4g, bit(1): enable 5g
++int rtw_ampdu_enable = 1;//for enable tx_ampdu
++int rtw_rx_stbc = 1;// 0: disable, bit(0):enable 2.4g, bit(1):enable 5g, default is set to enable 2.4GHZ for IOT issue with bufflao's AP at 5GHZ
++int rtw_ampdu_amsdu = 0;// 0: disabled, 1:enabled, 2:auto
++#endif
++
++int rtw_lowrate_two_xmit = 1;//Use 2 path Tx to transmit MCS0~7 and legacy mode
++
++//int rf_config = RF_1T2R; // 1T2R
++int rtw_rf_config = RF_819X_MAX_TYPE; //auto
++int rtw_low_power = 0;
++#ifdef CONFIG_WIFI_TEST
++int rtw_wifi_spec = 1;//for wifi test
++#else
++int rtw_wifi_spec = 0;
++#endif
++
++int rtw_special_rf_path = 0; //0: 2T2R ,1: only turn on path A 1T1R, 2: only turn on path B 1T1R
++
++int rtw_channel_plan = RT_CHANNEL_DOMAIN_MAX;
++
++#ifdef CONFIG_BT_COEXIST
++int rtw_bt_iso = 2;// 0:Low, 1:High, 2:From Efuse
++int rtw_bt_sco = 3;// 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter, 4.Busy, 5.OtherBusy
++int rtw_bt_ampdu =1 ;// 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU.
++#endif
++int rtw_AcceptAddbaReq = _TRUE;// 0:Reject AP's Add BA req, 1:Accept AP's Add BA req.
++
++int rtw_antdiv_cfg = 2; // 0:OFF , 1:ON, 2:decide by Efuse config
++
++#ifdef CONFIG_USB_AUTOSUSPEND
++int rtw_enusbss = 1;//0:disable,1:enable
++#else
++int rtw_enusbss = 0;//0:disable,1:enable
++#endif
++
++int rtw_hwpdn_mode=2;//0:disable,1:enable,2: by EFUSE config
++
++#ifdef CONFIG_HW_PWRP_DETECTION
++int rtw_hwpwrp_detect = 1;
++#else
++int rtw_hwpwrp_detect = 0; //HW power ping detect 0:disable , 1:enable
++#endif
++
++#ifdef CONFIG_USB_HCI
++int rtw_hw_wps_pbc = 1;
++#else
++int rtw_hw_wps_pbc = 0;
++#endif
++
++#ifdef CONFIG_TX_MCAST2UNI
++int rtw_mc2u_disable = 0;
++#endif // CONFIG_TX_MCAST2UNI
++
++int rtw_mac_phy_mode = 0; //0:by efuse, 1:smsp, 2:dmdp, 3:dmsp.
++
++#ifdef CONFIG_80211D
++int rtw_80211d = 0;
++#endif
++
++char* ifname = "wlan%d";
++module_param(ifname, charp, 0644);
++MODULE_PARM_DESC(ifname, "The default name to allocate for first interface");
++
++char* if2name = "wlan%d";
++module_param(if2name, charp, 0644);
++MODULE_PARM_DESC(if2name, "The default name to allocate for second interface");
++
++char* rtw_initmac = 0; // temp mac address if users want to use instead of the mac address in Efuse
++
++#ifdef CONFIG_MULTI_VIR_IFACES
++int rtw_ext_iface_num = 1;//primary/secondary iface is excluded
++module_param(rtw_ext_iface_num, int, 0644);
++#endif //CONFIG_MULTI_VIR_IFACES
++
++module_param(rtw_initmac, charp, 0644);
++module_param(rtw_channel_plan, int, 0644);
++module_param(rtw_chip_version, int, 0644);
++module_param(rtw_rfintfs, int, 0644);
++module_param(rtw_lbkmode, int, 0644);
++module_param(rtw_network_mode, int, 0644);
++module_param(rtw_channel, int, 0644);
++module_param(rtw_mp_mode, int, 0644);
++module_param(rtw_wmm_enable, int, 0644);
++module_param(rtw_vrtl_carrier_sense, int, 0644);
++module_param(rtw_vcs_type, int, 0644);
++module_param(rtw_busy_thresh, int, 0644);
++#ifdef CONFIG_80211N_HT
++module_param(rtw_ht_enable, int, 0644);
++module_param(rtw_cbw40_enable, int, 0644);
++module_param(rtw_ampdu_enable, int, 0644);
++module_param(rtw_rx_stbc, int, 0644);
++module_param(rtw_ampdu_amsdu, int, 0644);
++#endif
++
++module_param(rtw_lowrate_two_xmit, int, 0644);
++
++module_param(rtw_rf_config, int, 0644);
++module_param(rtw_power_mgnt, int, 0644);
++module_param(rtw_low_power, int, 0644);
++module_param(rtw_wifi_spec, int, 0644);
++
++module_param(rtw_special_rf_path, int, 0644);
++
++module_param(rtw_antdiv_cfg, int, 0644);
++
++
++module_param(rtw_enusbss, int, 0644);
++module_param(rtw_hwpdn_mode, int, 0644);
++module_param(rtw_hwpwrp_detect, int, 0644);
++
++module_param(rtw_hw_wps_pbc, int, 0644);
++
++#ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE
++char *rtw_adaptor_info_caching_file_path= "/data/misc/wifi/rtw_cache";
++module_param(rtw_adaptor_info_caching_file_path, charp, 0644);
++MODULE_PARM_DESC(rtw_adaptor_info_caching_file_path, "The path of adapter info cache file");
++#endif //CONFIG_ADAPTOR_INFO_CACHING_FILE
++
++#ifdef CONFIG_LAYER2_ROAMING
++uint rtw_max_roaming_times=2;
++module_param(rtw_max_roaming_times, uint, 0644);
++MODULE_PARM_DESC(rtw_max_roaming_times,"The max roaming times to try");
++#endif //CONFIG_LAYER2_ROAMING
++
++#ifdef CONFIG_IOL
++bool rtw_force_iol=_FALSE;
++module_param(rtw_force_iol, bool, 0644);
++MODULE_PARM_DESC(rtw_force_iol,"Force to enable IOL");
++#endif //CONFIG_IOL
++
++#ifdef CONFIG_FILE_FWIMG
++char *rtw_fw_file_path= "";
++module_param(rtw_fw_file_path, charp, 0644);
++MODULE_PARM_DESC(rtw_fw_file_path, "The path of fw image");
++#endif //CONFIG_FILE_FWIMG
++
++#ifdef CONFIG_TX_MCAST2UNI
++module_param(rtw_mc2u_disable, int, 0644);
++#endif // CONFIG_TX_MCAST2UNI
++
++module_param(rtw_mac_phy_mode, int, 0644);
++
++#ifdef CONFIG_80211D
++module_param(rtw_80211d, int, 0644);
++#endif
++
++uint rtw_notch_filter = RTW_NOTCH_FILTER;
++module_param(rtw_notch_filter, uint, 0644);
++MODULE_PARM_DESC(rtw_notch_filter, "0:Disable, 1:Enable, 2:Enable only for P2P");
++
++static uint loadparam( _adapter *padapter, _nic_hdl pnetdev);
++int _netdev_open(struct net_device *pnetdev);
++int netdev_open (struct net_device *pnetdev);
++static int netdev_close (struct net_device *pnetdev);
++
++//#ifdef RTK_DMP_PLATFORM
++#ifdef CONFIG_PROC_DEBUG
++#define RTL8192C_PROC_NAME "rtl819xC"
++#define RTL8192D_PROC_NAME "rtl819xD"
++static char rtw_proc_name[IFNAMSIZ];
++static struct proc_dir_entry *rtw_proc = NULL;
++static int rtw_proc_cnt = 0;
++
++#define RTW_PROC_NAME DRV_NAME
++
++void rtw_proc_init_one(struct net_device *dev)
++{
++ struct proc_dir_entry *dir_dev = NULL;
++ struct proc_dir_entry *entry=NULL;
++ _adapter *padapter = rtw_netdev_priv(dev);
++ u8 rf_type;
++
++ if(rtw_proc == NULL)
++ {
++ if(padapter->chip_type == RTL8188C_8192C)
++ {
++ _rtw_memcpy(rtw_proc_name, RTL8192C_PROC_NAME, sizeof(RTL8192C_PROC_NAME));
++ }
++ else if(padapter->chip_type == RTL8192D)
++ {
++ _rtw_memcpy(rtw_proc_name, RTL8192D_PROC_NAME, sizeof(RTL8192D_PROC_NAME));
++ }
++ else if(padapter->chip_type == RTL8723A)
++ {
++ _rtw_memcpy(rtw_proc_name, RTW_PROC_NAME, sizeof(RTW_PROC_NAME));
++ }
++ else if(padapter->chip_type == RTL8188E)
++ {
++ _rtw_memcpy(rtw_proc_name, RTW_PROC_NAME, sizeof(RTW_PROC_NAME));
++ }
++ else
++ {
++ _rtw_memcpy(rtw_proc_name, RTW_PROC_NAME, sizeof(RTW_PROC_NAME));
++ }
++
++#if(LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24))
++ rtw_proc=create_proc_entry(rtw_proc_name, S_IFDIR, proc_net);
++#else
++ rtw_proc=create_proc_entry(rtw_proc_name, S_IFDIR, init_net.proc_net);
++#endif
++ if (rtw_proc == NULL) {
++ DBG_871X(KERN_ERR "Unable to create rtw_proc directory\n");
++ return;
++ }
++
++ entry = create_proc_read_entry("ver_info", S_IFREG | S_IRUGO, rtw_proc, proc_get_drv_version, dev);
++ if (!entry) {
++ DBG_871X("Unable to create_proc_read_entry!\n");
++ return;
++ }
++
++ entry = create_proc_read_entry("log_level", S_IFREG | S_IRUGO,
++ rtw_proc, proc_get_log_level, dev);
++ if (!entry) {
++ DBG_871X("Unable to create_proc_read_entry!\n");
++ return;
++ }
++ entry->write_proc = proc_set_log_level;
++
++#ifdef DBG_MEM_ALLOC
++ entry = create_proc_read_entry("mstat", S_IFREG | S_IRUGO,
++ rtw_proc, proc_get_mstat, dev);
++ if (!entry) {
++ DBG_871X("Unable to create_proc_read_entry!\n");
++ return;
++ }
++#endif /* DBG_MEM_ALLOC */
++ }
++
++
++
++ if(padapter->dir_dev == NULL)
++ {
++ padapter->dir_dev = create_proc_entry(dev->name,
++ S_IFDIR | S_IRUGO | S_IXUGO,
++ rtw_proc);
++
++ dir_dev = padapter->dir_dev;
++
++ if(dir_dev==NULL)
++ {
++ if(rtw_proc_cnt == 0)
++ {
++ if(rtw_proc){
++#if(LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24))
++ remove_proc_entry(rtw_proc_name, proc_net);
++#else
++ remove_proc_entry(rtw_proc_name, init_net.proc_net);
++#endif
++ rtw_proc = NULL;
++ }
++ }
++
++ DBG_871X("Unable to create dir_dev directory\n");
++ return;
++ }
++ }
++ else
++ {
++ return;
++ }
++
++ rtw_proc_cnt++;
++
++ entry = create_proc_read_entry("write_reg", S_IFREG | S_IRUGO,
++ dir_dev, proc_get_write_reg, dev);
++ if (!entry) {
++ DBG_871X("Unable to create_proc_read_entry!\n");
++ return;
++ }
++ entry->write_proc = proc_set_write_reg;
++
++ entry = create_proc_read_entry("read_reg", S_IFREG | S_IRUGO,
++ dir_dev, proc_get_read_reg, dev);
++ if (!entry) {
++ DBG_871X("Unable to create_proc_read_entry!\n");
++ return;
++ }
++ entry->write_proc = proc_set_read_reg;
++
++
++ entry = create_proc_read_entry("fwstate", S_IFREG | S_IRUGO,
++ dir_dev, proc_get_fwstate, dev);
++ if (!entry) {
++ DBG_871X("Unable to create_proc_read_entry!\n");
++ return;
++ }
++
++
++ entry = create_proc_read_entry("sec_info", S_IFREG | S_IRUGO,
++ dir_dev, proc_get_sec_info, dev);
++ if (!entry) {
++ DBG_871X("Unable to create_proc_read_entry!\n");
++ return;
++ }
++
++
++ entry = create_proc_read_entry("mlmext_state", S_IFREG | S_IRUGO,
++ dir_dev, proc_get_mlmext_state, dev);
++ if (!entry) {
++ DBG_871X("Unable to create_proc_read_entry!\n");
++ return;
++ }
++
++
++ entry = create_proc_read_entry("qos_option", S_IFREG | S_IRUGO,
++ dir_dev, proc_get_qos_option, dev);
++ if (!entry) {
++ DBG_871X("Unable to create_proc_read_entry!\n");
++ return;
++ }
++
++ entry = create_proc_read_entry("ht_option", S_IFREG | S_IRUGO,
++ dir_dev, proc_get_ht_option, dev);
++ if (!entry) {
++ DBG_871X("Unable to create_proc_read_entry!\n");
++ return;
++ }
++
++ entry = create_proc_read_entry("rf_info", S_IFREG | S_IRUGO,
++ dir_dev, proc_get_rf_info, dev);
++ if (!entry) {
++ DBG_871X("Unable to create_proc_read_entry!\n");
++ return;
++ }
++
++ entry = create_proc_read_entry("ap_info", S_IFREG | S_IRUGO,
++ dir_dev, proc_get_ap_info, dev);
++ if (!entry) {
++ DBG_871X("Unable to create_proc_read_entry!\n");
++ return;
++ }
++
++ entry = create_proc_read_entry("adapter_state", S_IFREG | S_IRUGO,
++ dir_dev, proc_get_adapter_state, dev);
++ if (!entry) {
++ DBG_871X("Unable to create_proc_read_entry!\n");
++ return;
++ }
++
++ entry = create_proc_read_entry("trx_info", S_IFREG | S_IRUGO,
++ dir_dev, proc_get_trx_info, dev);
++ if (!entry) {
++ DBG_871X("Unable to create_proc_read_entry!\n");
++ return;
++ }
++
++ entry = create_proc_read_entry("mac_reg_dump1", S_IFREG | S_IRUGO,
++ dir_dev, proc_get_mac_reg_dump1, dev);
++ if (!entry) {
++ DBG_871X("Unable to create_proc_read_entry!\n");
++ return;
++ }
++
++ entry = create_proc_read_entry("mac_reg_dump2", S_IFREG | S_IRUGO,
++ dir_dev, proc_get_mac_reg_dump2, dev);
++ if (!entry) {
++ DBG_871X("Unable to create_proc_read_entry!\n");
++ return;
++ }
++
++ entry = create_proc_read_entry("mac_reg_dump3", S_IFREG | S_IRUGO,
++ dir_dev, proc_get_mac_reg_dump3, dev);
++ if (!entry) {
++ DBG_871X("Unable to create_proc_read_entry!\n");
++ return;
++ }
++
++ entry = create_proc_read_entry("bb_reg_dump1", S_IFREG | S_IRUGO,
++ dir_dev, proc_get_bb_reg_dump1, dev);
++ if (!entry) {
++ DBG_871X("Unable to create_proc_read_entry!\n");
++ return;
++ }
++
++ entry = create_proc_read_entry("bb_reg_dump2", S_IFREG | S_IRUGO,
++ dir_dev, proc_get_bb_reg_dump2, dev);
++ if (!entry) {
++ DBG_871X("Unable to create_proc_read_entry!\n");
++ return;
++ }
++
++ entry = create_proc_read_entry("bb_reg_dump3", S_IFREG | S_IRUGO,
++ dir_dev, proc_get_bb_reg_dump3, dev);
++ if (!entry) {
++ DBG_871X("Unable to create_proc_read_entry!\n");
++ return;
++ }
++
++ entry = create_proc_read_entry("rf_reg_dump1", S_IFREG | S_IRUGO,
++ dir_dev, proc_get_rf_reg_dump1, dev);
++ if (!entry) {
++ DBG_871X("Unable to create_proc_read_entry!\n");
++ return;
++ }
++
++ entry = create_proc_read_entry("rf_reg_dump2", S_IFREG | S_IRUGO,
++ dir_dev, proc_get_rf_reg_dump2, dev);
++ if (!entry) {
++ DBG_871X("Unable to create_proc_read_entry!\n");
++ return;
++ }
++
++ rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));
++ if((RF_1T2R == rf_type) ||(RF_1T1R ==rf_type )) {
++ entry = create_proc_read_entry("rf_reg_dump3", S_IFREG | S_IRUGO,
++ dir_dev, proc_get_rf_reg_dump3, dev);
++ if (!entry) {
++ DBG_871X("Unable to create_proc_read_entry!\n");
++ return;
++ }
++
++ entry = create_proc_read_entry("rf_reg_dump4", S_IFREG | S_IRUGO,
++ dir_dev, proc_get_rf_reg_dump4, dev);
++ if (!entry) {
++ DBG_871X("Unable to create_proc_read_entry!\n");
++ return;
++ }
++ }
++
++#ifdef CONFIG_AP_MODE
++
++ entry = create_proc_read_entry("all_sta_info", S_IFREG | S_IRUGO,
++ dir_dev, proc_get_all_sta_info, dev);
++ if (!entry) {
++ DBG_871X("Unable to create_proc_read_entry!\n");
++ return;
++ }
++#endif
++
++#ifdef DBG_MEMORY_LEAK
++ entry = create_proc_read_entry("_malloc_cnt", S_IFREG | S_IRUGO,
++ dir_dev, proc_get_malloc_cnt, dev);
++ if (!entry) {
++ DBG_871X("Unable to create_proc_read_entry!\n");
++ return;
++ }
++#endif
++
++#ifdef CONFIG_FIND_BEST_CHANNEL
++ entry = create_proc_read_entry("best_channel", S_IFREG | S_IRUGO,
++ dir_dev, proc_get_best_channel, dev);
++ if (!entry) {
++ DBG_871X("Unable to create_proc_read_entry!\n");
++ return;
++ }
++ entry->write_proc = proc_set_best_channel;
++#endif
++
++ entry = create_proc_read_entry("rx_signal", S_IFREG | S_IRUGO,
++ dir_dev, proc_get_rx_signal, dev);
++ if (!entry) {
++ DBG_871X("Unable to create_proc_read_entry!\n");
++ return;
++ }
++ entry->write_proc = proc_set_rx_signal;
++
++ entry = create_proc_read_entry("ht_enable", S_IFREG | S_IRUGO,
++ dir_dev, proc_get_ht_enable, dev);
++ if (!entry) {
++ DBG_871X("Unable to create_proc_read_entry!\n");
++ return;
++ }
++ entry->write_proc = proc_set_ht_enable;
++
++ entry = create_proc_read_entry("cbw40_enable", S_IFREG | S_IRUGO,
++ dir_dev, proc_get_cbw40_enable, dev);
++ if (!entry) {
++ DBG_871X("Unable to create_proc_read_entry!\n");
++ return;
++ }
++ entry->write_proc = proc_set_cbw40_enable;
++
++ entry = create_proc_read_entry("ampdu_enable", S_IFREG | S_IRUGO,
++ dir_dev, proc_get_ampdu_enable, dev);
++ if (!entry) {
++ DBG_871X("Unable to create_proc_read_entry!\n");
++ return;
++ }
++ entry->write_proc = proc_set_ampdu_enable;
++
++ entry = create_proc_read_entry("rx_stbc", S_IFREG | S_IRUGO,
++ dir_dev, proc_get_rx_stbc, dev);
++ if (!entry) {
++ DBG_871X("Unable to create_proc_read_entry!\n");
++ return;
++ }
++ entry->write_proc = proc_set_rx_stbc;
++
++
++ entry = create_proc_read_entry("path_rssi", S_IFREG | S_IRUGO,
++ dir_dev, proc_get_two_path_rssi, dev);
++
++ entry = create_proc_read_entry("vid", S_IFREG | S_IRUGO,
++ dir_dev, proc_get_vid, dev);
++ if (!entry) {
++ DBG_871X("Unable to create_proc_read_entry!\n");
++ return;
++ }
++
++ entry = create_proc_read_entry("pid", S_IFREG | S_IRUGO,
++ dir_dev, proc_get_pid, dev);
++ if (!entry) {
++ DBG_871X("Unable to create_proc_read_entry!\n");
++ return;
++ }
++
++ entry = create_proc_read_entry("rssi_disp", S_IFREG | S_IRUGO,
++ dir_dev, proc_get_rssi_disp, dev);
++ if (!entry) {
++ DBG_871X("Unable to create_proc_read_entry!\n");
++ return;
++ }
++ entry->write_proc = proc_set_rssi_disp;
++
++#if defined(DBG_CONFIG_ERROR_DETECT)
++ entry = create_proc_read_entry("sreset", S_IFREG | S_IRUGO,
++ dir_dev, proc_get_sreset, dev);
++ if (!entry) {
++ DBG_871X("Unable to create_proc_read_entry!\n");
++ return;
++ }
++ entry->write_proc = proc_set_sreset;
++#endif /* DBG_CONFIG_ERROR_DETECT */
++
++#ifdef CONFIG_DM_ADAPTIVITY
++ entry = create_proc_read_entry("dm_adaptivity", S_IFREG | S_IRUGO,
++ dir_dev, proc_get_dm_adaptivity, dev);
++ if (!entry) {
++ DBG_871X("Unable to create_proc_read_entry!\n");
++ return;
++ }
++ entry->write_proc = proc_set_dm_adaptivity;
++#endif /* CONFIG_DM_ADAPTIVITY */
++
++}
++
++void rtw_proc_remove_one(struct net_device *dev)
++{
++ struct proc_dir_entry *dir_dev = NULL;
++ _adapter *padapter = rtw_netdev_priv(dev);
++ u8 rf_type;
++
++ dir_dev = padapter->dir_dev;
++ padapter->dir_dev = NULL;
++
++ if (dir_dev) {
++
++ remove_proc_entry("write_reg", dir_dev);
++ remove_proc_entry("read_reg", dir_dev);
++ remove_proc_entry("fwstate", dir_dev);
++ remove_proc_entry("sec_info", dir_dev);
++ remove_proc_entry("mlmext_state", dir_dev);
++ remove_proc_entry("qos_option", dir_dev);
++ remove_proc_entry("ht_option", dir_dev);
++ remove_proc_entry("rf_info", dir_dev);
++ remove_proc_entry("ap_info", dir_dev);
++ remove_proc_entry("adapter_state", dir_dev);
++ remove_proc_entry("trx_info", dir_dev);
++
++ remove_proc_entry("mac_reg_dump1", dir_dev);
++ remove_proc_entry("mac_reg_dump2", dir_dev);
++ remove_proc_entry("mac_reg_dump3", dir_dev);
++ remove_proc_entry("bb_reg_dump1", dir_dev);
++ remove_proc_entry("bb_reg_dump2", dir_dev);
++ remove_proc_entry("bb_reg_dump3", dir_dev);
++ remove_proc_entry("rf_reg_dump1", dir_dev);
++ remove_proc_entry("rf_reg_dump2", dir_dev);
++ rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));
++ if((RF_1T2R == rf_type) ||(RF_1T1R ==rf_type )) {
++ remove_proc_entry("rf_reg_dump3", dir_dev);
++ remove_proc_entry("rf_reg_dump4", dir_dev);
++ }
++#ifdef CONFIG_AP_MODE
++ remove_proc_entry("all_sta_info", dir_dev);
++#endif
++
++#ifdef DBG_MEMORY_LEAK
++ remove_proc_entry("_malloc_cnt", dir_dev);
++#endif
++
++#ifdef CONFIG_FIND_BEST_CHANNEL
++ remove_proc_entry("best_channel", dir_dev);
++#endif
++ remove_proc_entry("rx_signal", dir_dev);
++
++ remove_proc_entry("cbw40_enable", dir_dev);
++
++ remove_proc_entry("ht_enable", dir_dev);
++
++ remove_proc_entry("ampdu_enable", dir_dev);
++
++ remove_proc_entry("rx_stbc", dir_dev);
++
++ remove_proc_entry("path_rssi", dir_dev);
++
++ remove_proc_entry("vid", dir_dev);
++
++ remove_proc_entry("pid", dir_dev);
++
++ remove_proc_entry("rssi_disp", dir_dev);
++
++#if defined(DBG_CONFIG_ERROR_DETECT)
++ remove_proc_entry("sreset", dir_dev);
++#endif /* DBG_CONFIG_ERROR_DETECT */
++
++#ifdef CONFIG_DM_ADAPTIVITY
++ remove_proc_entry("dm_adaptivity", dir_dev);
++#endif
++
++ remove_proc_entry(dev->name, rtw_proc);
++ dir_dev = NULL;
++
++ }
++ else
++ {
++ return;
++ }
++
++ rtw_proc_cnt--;
++
++ if(rtw_proc_cnt == 0)
++ {
++ if(rtw_proc){
++ remove_proc_entry("ver_info", rtw_proc);
++
++ remove_proc_entry("log_level", rtw_proc);
++ #ifdef DBG_MEM_ALLOC
++ remove_proc_entry("mstat", rtw_proc);
++ #endif /* DBG_MEM_ALLOC */
++#if(LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24))
++ remove_proc_entry(rtw_proc_name, proc_net);
++#else
++ remove_proc_entry(rtw_proc_name, init_net.proc_net);
++#endif
++ rtw_proc = NULL;
++ }
++ }
++}
++#endif
++
++uint loadparam( _adapter *padapter, _nic_hdl pnetdev);
++uint loadparam( _adapter *padapter, _nic_hdl pnetdev)
++{
++
++ uint status = _SUCCESS;
++ struct registry_priv *registry_par = &padapter->registrypriv;
++
++_func_enter_;
++
++ registry_par->chip_version = (u8)rtw_chip_version;
++ registry_par->rfintfs = (u8)rtw_rfintfs;
++ registry_par->lbkmode = (u8)rtw_lbkmode;
++ //registry_par->hci = (u8)hci;
++ registry_par->network_mode = (u8)rtw_network_mode;
++
++ _rtw_memcpy(registry_par->ssid.Ssid, "ANY", 3);
++ registry_par->ssid.SsidLength = 3;
++
++ registry_par->channel = (u8)rtw_channel;
++ registry_par->wireless_mode = (u8)rtw_wireless_mode;
++ registry_par->vrtl_carrier_sense = (u8)rtw_vrtl_carrier_sense ;
++ registry_par->vcs_type = (u8)rtw_vcs_type;
++ registry_par->rts_thresh=(u16)rtw_rts_thresh;
++ registry_par->frag_thresh=(u16)rtw_frag_thresh;
++ registry_par->preamble = (u8)rtw_preamble;
++ registry_par->scan_mode = (u8)rtw_scan_mode;
++ registry_par->adhoc_tx_pwr = (u8)rtw_adhoc_tx_pwr;
++ registry_par->soft_ap= (u8)rtw_soft_ap;
++ //registry_par->smart_ps = (u8)rtw_smart_ps;
++ registry_par->power_mgnt = (u8)rtw_power_mgnt;
++ registry_par->ips_mode = (u8)rtw_ips_mode;
++ registry_par->radio_enable = (u8)rtw_radio_enable;
++ registry_par->long_retry_lmt = (u8)rtw_long_retry_lmt;
++ registry_par->short_retry_lmt = (u8)rtw_short_retry_lmt;
++ registry_par->busy_thresh = (u16)rtw_busy_thresh;
++ //registry_par->qos_enable = (u8)rtw_qos_enable;
++ registry_par->ack_policy = (u8)rtw_ack_policy;
++ registry_par->mp_mode = (u8)rtw_mp_mode;
++ registry_par->software_encrypt = (u8)rtw_software_encrypt;
++ registry_par->software_decrypt = (u8)rtw_software_decrypt;
++
++ registry_par->acm_method = (u8)rtw_acm_method;
++
++ //UAPSD
++ registry_par->wmm_enable = (u8)rtw_wmm_enable;
++ registry_par->uapsd_enable = (u8)rtw_uapsd_enable;
++ registry_par->uapsd_max_sp = (u8)rtw_uapsd_max_sp;
++ registry_par->uapsd_acbk_en = (u8)rtw_uapsd_acbk_en;
++ registry_par->uapsd_acbe_en = (u8)rtw_uapsd_acbe_en;
++ registry_par->uapsd_acvi_en = (u8)rtw_uapsd_acvi_en;
++ registry_par->uapsd_acvo_en = (u8)rtw_uapsd_acvo_en;
++
++#ifdef CONFIG_80211N_HT
++ registry_par->ht_enable = (u8)rtw_ht_enable;
++ registry_par->cbw40_enable = (u8)rtw_cbw40_enable;
++ registry_par->ampdu_enable = (u8)rtw_ampdu_enable;
++ registry_par->rx_stbc = (u8)rtw_rx_stbc;
++ registry_par->ampdu_amsdu = (u8)rtw_ampdu_amsdu;
++#endif
++
++ registry_par->lowrate_two_xmit = (u8)rtw_lowrate_two_xmit;
++ registry_par->rf_config = (u8)rtw_rf_config;
++ registry_par->low_power = (u8)rtw_low_power;
++
++
++ registry_par->wifi_spec = (u8)rtw_wifi_spec;
++ registry_par->special_rf_path = (u8)rtw_special_rf_path;
++ registry_par->channel_plan = (u8)rtw_channel_plan;
++
++#ifdef CONFIG_BT_COEXIST
++ registry_par->bt_iso = (u8)rtw_bt_iso;
++ registry_par->bt_sco = (u8)rtw_bt_sco;
++ registry_par->bt_ampdu = (u8)rtw_bt_ampdu;
++#endif
++ registry_par->bAcceptAddbaReq = (u8)rtw_AcceptAddbaReq;
++
++ registry_par->antdiv_cfg = (u8)rtw_antdiv_cfg;
++
++#ifdef CONFIG_AUTOSUSPEND
++ registry_par->usbss_enable = (u8)rtw_enusbss;//0:disable,1:enable
++#endif
++#ifdef SUPPORT_HW_RFOFF_DETECTED
++ registry_par->hwpdn_mode = (u8)rtw_hwpdn_mode;//0:disable,1:enable,2:by EFUSE config
++ registry_par->hwpwrp_detect = (u8)rtw_hwpwrp_detect;//0:disable,1:enable
++#endif
++
++ registry_par->hw_wps_pbc = (u8)rtw_hw_wps_pbc;
++
++#ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE
++ snprintf(registry_par->adaptor_info_caching_file_path, PATH_LENGTH_MAX, "%s", rtw_adaptor_info_caching_file_path);
++ registry_par->adaptor_info_caching_file_path[PATH_LENGTH_MAX-1]=0;
++#endif
++
++#ifdef CONFIG_LAYER2_ROAMING
++ registry_par->max_roaming_times = (u8)rtw_max_roaming_times;
++#ifdef CONFIG_INTEL_WIDI
++ registry_par->max_roaming_times = (u8)rtw_max_roaming_times + 2;
++#endif // CONFIG_INTEL_WIDI
++#endif
++
++#ifdef CONFIG_IOL
++ registry_par->force_iol = rtw_force_iol;
++#endif
++
++ registry_par->mac_phy_mode = rtw_mac_phy_mode;
++
++#ifdef CONFIG_80211D
++ registry_par->enable80211d = (u8)rtw_80211d;
++#endif
++
++ snprintf(registry_par->ifname, 16, "%s", ifname);
++ snprintf(registry_par->if2name, 16, "%s", if2name);
++
++ registry_par->notch_filter = (u8)rtw_notch_filter;
++
++#ifdef CONFIG_MULTI_VIR_IFACES
++ registry_par->ext_iface_num = (u8)rtw_ext_iface_num;
++#endif //CONFIG_MULTI_VIR_IFACES
++
++_func_exit_;
++
++ return status;
++}
++
++static int rtw_net_set_mac_address(struct net_device *pnetdev, void *p)
++{
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev);
++ struct sockaddr *addr = p;
++
++ if(padapter->bup == _FALSE)
++ {
++ //DBG_871X("r8711_net_set_mac_address(), MAC=%x:%x:%x:%x:%x:%x\n", addr->sa_data[0], addr->sa_data[1], addr->sa_data[2], addr->sa_data[3],
++ //addr->sa_data[4], addr->sa_data[5]);
++ _rtw_memcpy(padapter->eeprompriv.mac_addr, addr->sa_data, ETH_ALEN);
++ //_rtw_memcpy(pnetdev->dev_addr, addr->sa_data, ETH_ALEN);
++ //padapter->bset_hwaddr = _TRUE;
++ }
++
++ return 0;
++}
++
++static struct net_device_stats *rtw_net_get_stats(struct net_device *pnetdev)
++{
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev);
++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
++ struct recv_priv *precvpriv = &(padapter->recvpriv);
++
++ padapter->stats.tx_packets = pxmitpriv->tx_pkts;//pxmitpriv->tx_pkts++;
++ padapter->stats.rx_packets = precvpriv->rx_pkts;//precvpriv->rx_pkts++;
++ padapter->stats.tx_dropped = pxmitpriv->tx_drop;
++ padapter->stats.rx_dropped = precvpriv->rx_drop;
++ padapter->stats.tx_bytes = pxmitpriv->tx_bytes;
++ padapter->stats.rx_bytes = precvpriv->rx_bytes;
++
++ return &padapter->stats;
++}
++
++#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,35))
++/*
++ * AC to queue mapping
++ *
++ * AC_VO -> queue 0
++ * AC_VI -> queue 1
++ * AC_BE -> queue 2
++ * AC_BK -> queue 3
++ */
++static const u16 rtw_1d_to_queue[8] = { 2, 3, 3, 2, 1, 1, 0, 0 };
++
++/* Given a data frame determine the 802.1p/1d tag to use. */
++unsigned int rtw_classify8021d(struct sk_buff *skb)
++{
++ unsigned int dscp;
++
++ /* skb->priority values from 256->263 are magic values to
++ * directly indicate a specific 802.1d priority. This is used
++ * to allow 802.1d priority to be passed directly in from VLAN
++ * tags, etc.
++ */
++ if (skb->priority >= 256 && skb->priority <= 263)
++ return skb->priority - 256;
++
++ switch (skb->protocol) {
++ case htons(ETH_P_IP):
++ dscp = ip_hdr(skb)->tos & 0xfc;
++ break;
++ default:
++ return 0;
++ }
++
++ return dscp >> 5;
++}
++
++static u16 rtw_select_queue(struct net_device *dev, struct sk_buff *skb)
++{
++ _adapter *padapter = rtw_netdev_priv(dev);
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++
++ skb->priority = rtw_classify8021d(skb);
++
++ if(pmlmepriv->acm_mask != 0)
++ {
++ skb->priority = qos_acm(pmlmepriv->acm_mask, skb->priority);
++ }
++
++ return rtw_1d_to_queue[skb->priority];
++}
++
++u16 rtw_recv_select_queue(struct sk_buff *skb)
++{
++ struct iphdr *piphdr;
++ unsigned int dscp;
++ u16 eth_type;
++ u32 priority;
++ u8 *pdata = skb->data;
++
++ _rtw_memcpy(&eth_type, pdata+(ETH_ALEN<<1), 2);
++
++ switch (eth_type) {
++ case htons(ETH_P_IP):
++
++ piphdr = (struct iphdr *)(pdata+ETH_HLEN);
++
++ dscp = piphdr->tos & 0xfc;
++
++ priority = dscp >> 5;
++
++ break;
++ default:
++ priority = 0;
++ }
++
++ return rtw_1d_to_queue[priority];
++
++}
++
++#endif
++
++#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,29))
++static const struct net_device_ops rtw_netdev_ops = {
++ .ndo_open = netdev_open,
++ .ndo_stop = netdev_close,
++ .ndo_start_xmit = rtw_xmit_entry,
++#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,35))
++ .ndo_select_queue = rtw_select_queue,
++#endif
++ .ndo_set_mac_address = rtw_net_set_mac_address,
++ .ndo_get_stats = rtw_net_get_stats,
++ .ndo_do_ioctl = rtw_ioctl,
++};
++#endif
++
++int rtw_init_netdev_name(struct net_device *pnetdev, const char *ifname)
++{
++ _adapter *padapter = rtw_netdev_priv(pnetdev);
++
++#ifdef CONFIG_EASY_REPLACEMENT
++ struct net_device *TargetNetdev = NULL;
++ _adapter *TargetAdapter = NULL;
++ struct net *devnet = NULL;
++
++ if(padapter->bDongle == 1)
++ {
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24))
++ TargetNetdev = dev_get_by_name("wlan0");
++#else
++ #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26))
++ devnet = pnetdev->nd_net;
++ #else
++ devnet = dev_net(pnetdev);
++ #endif
++ TargetNetdev = dev_get_by_name(devnet, "wlan0");
++#endif
++ if(TargetNetdev) {
++ DBG_871X("Force onboard module driver disappear !!!\n");
++ TargetAdapter = rtw_netdev_priv(TargetNetdev);
++ TargetAdapter->DriverState = DRIVER_DISAPPEAR;
++
++ padapter->pid[0] = TargetAdapter->pid[0];
++ padapter->pid[1] = TargetAdapter->pid[1];
++ padapter->pid[2] = TargetAdapter->pid[2];
++
++ dev_put(TargetNetdev);
++ unregister_netdev(TargetNetdev);
++
++ if(TargetAdapter->chip_type == padapter->chip_type)
++ rtw_proc_remove_one(TargetNetdev);
++
++ padapter->DriverState = DRIVER_REPLACE_DONGLE;
++ }
++ }
++#endif //CONFIG_EASY_REPLACEMENT
++
++ if(dev_alloc_name(pnetdev, ifname) < 0)
++ {
++ RT_TRACE(_module_os_intfs_c_,_drv_err_,("dev_alloc_name, fail! \n"));
++ }
++
++ netif_carrier_off(pnetdev);
++ //rtw_netif_stop_queue(pnetdev);
++
++ return 0;
++}
++
++struct net_device *rtw_init_netdev(_adapter *old_padapter)
++{
++ _adapter *padapter;
++ struct net_device *pnetdev;
++
++ RT_TRACE(_module_os_intfs_c_,_drv_info_,("+init_net_dev\n"));
++
++ if(old_padapter != NULL)
++ pnetdev = rtw_alloc_etherdev_with_old_priv(sizeof(_adapter), (void *)old_padapter);
++ else
++ pnetdev = rtw_alloc_etherdev(sizeof(_adapter));
++
++ if (!pnetdev)
++ return NULL;
++
++ padapter = rtw_netdev_priv(pnetdev);
++ padapter->pnetdev = pnetdev;
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)
++ SET_MODULE_OWNER(pnetdev);
++#endif
++
++ //pnetdev->init = NULL;
++
++#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,29))
++ DBG_871X("register rtw_netdev_ops to netdev_ops\n");
++ pnetdev->netdev_ops = &rtw_netdev_ops;
++#else
++ pnetdev->open = netdev_open;
++ pnetdev->stop = netdev_close;
++ pnetdev->hard_start_xmit = rtw_xmit_entry;
++ pnetdev->set_mac_address = rtw_net_set_mac_address;
++ pnetdev->get_stats = rtw_net_get_stats;
++ pnetdev->do_ioctl = rtw_ioctl;
++#endif
++
++
++#ifdef CONFIG_TCP_CSUM_OFFLOAD_TX
++ pnetdev->features |= NETIF_F_IP_CSUM;
++#endif
++ //pnetdev->tx_timeout = NULL;
++ pnetdev->watchdog_timeo = HZ*3; /* 3 second timeout */
++#ifdef CONFIG_WIRELESS_EXT
++ pnetdev->wireless_handlers = (struct iw_handler_def *)&rtw_handlers_def;
++#endif
++
++#ifdef WIRELESS_SPY
++ //priv->wireless_data.spy_data = &priv->spy_data;
++ //pnetdev->wireless_data = &priv->wireless_data;
++#endif
++
++ //step 2.
++ loadparam(padapter, pnetdev);
++
++ return pnetdev;
++
++}
++
++void rtw_unregister_netdevs(struct dvobj_priv *dvobj)
++{
++ int i;
++ _adapter *padapter = NULL;
++
++ for (i=0;i<dvobj->iface_nums;i++) {
++ struct net_device *pnetdev = NULL;
++
++ padapter = dvobj->padapters[i];
++
++ if (padapter == NULL)
++ continue;
++
++ pnetdev = padapter->pnetdev;
++
++ if((padapter->DriverState != DRIVER_DISAPPEAR) && pnetdev) {
++ unregister_netdev(pnetdev); //will call netdev_close()
++ rtw_proc_remove_one(pnetdev);
++ }
++
++ #ifdef CONFIG_IOCTL_CFG80211
++ rtw_wdev_unregister(padapter->rtw_wdev);
++ #endif
++ }
++
++}
++
++u32 rtw_start_drv_threads(_adapter *padapter)
++{
++
++ u32 _status = _SUCCESS;
++
++ RT_TRACE(_module_os_intfs_c_,_drv_info_,("+rtw_start_drv_threads\n"));
++#ifdef CONFIG_XMIT_THREAD_MODE
++ padapter->xmitThread = kthread_run(rtw_xmit_thread, padapter, "RTW_XMIT_THREAD");
++ if(IS_ERR(padapter->xmitThread))
++ _status = _FAIL;
++#endif
++
++#ifdef CONFIG_RECV_THREAD_MODE
++ padapter->recvThread = kthread_run(rtw_recv_thread, padapter, "RTW_RECV_THREAD");
++ if(IS_ERR(padapter->recvThread))
++ _status = _FAIL;
++#endif
++
++#ifdef CONFIG_CONCURRENT_MODE
++ if(padapter->isprimary == _TRUE)
++#endif //CONFIG_CONCURRENT_MODE
++ {
++ padapter->cmdThread = kthread_run(rtw_cmd_thread, padapter, "RTW_CMD_THREAD");
++ if(IS_ERR(padapter->cmdThread))
++ _status = _FAIL;
++ else
++ _rtw_down_sema(&padapter->cmdpriv.terminate_cmdthread_sema); //wait for cmd_thread to run
++ }
++
++
++#ifdef CONFIG_EVENT_THREAD_MODE
++ padapter->evtThread = kthread_run(event_thread, padapter, "RTW_EVENT_THREAD");
++ if(IS_ERR(padapter->evtThread))
++ _status = _FAIL;
++#endif
++
++ return _status;
++
++}
++
++void rtw_stop_drv_threads (_adapter *padapter)
++{
++ RT_TRACE(_module_os_intfs_c_,_drv_info_,("+rtw_stop_drv_threads\n"));
++
++#ifdef CONFIG_CONCURRENT_MODE
++ if(padapter->isprimary == _TRUE)
++#endif //CONFIG_CONCURRENT_MODE
++ {
++ rtw_stop_cmd_thread(padapter);
++ }
++
++#ifdef CONFIG_EVENT_THREAD_MODE
++ _rtw_up_sema(&padapter->evtpriv.evt_notify);
++ if(padapter->evtThread){
++ _rtw_down_sema(&padapter->evtpriv.terminate_evtthread_sema);
++ }
++#endif
++
++#ifdef CONFIG_XMIT_THREAD_MODE
++ // Below is to termindate tx_thread...
++ _rtw_up_sema(&padapter->xmitpriv.xmit_sema);
++ _rtw_down_sema(&padapter->xmitpriv.terminate_xmitthread_sema);
++ RT_TRACE(_module_os_intfs_c_,_drv_info_,("\n drv_halt: rtw_xmit_thread can be terminated ! \n"));
++#endif
++
++#ifdef CONFIG_RECV_THREAD_MODE
++ // Below is to termindate rx_thread...
++ _rtw_up_sema(&padapter->recvpriv.recv_sema);
++ _rtw_down_sema(&padapter->recvpriv.terminate_recvthread_sema);
++ RT_TRACE(_module_os_intfs_c_,_drv_info_,("\n drv_halt:recv_thread can be terminated! \n"));
++#endif
++
++
++}
++
++u8 rtw_init_default_value(_adapter *padapter);
++u8 rtw_init_default_value(_adapter *padapter)
++{
++ u8 ret = _SUCCESS;
++ struct registry_priv* pregistrypriv = &padapter->registrypriv;
++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++ struct mlme_priv *pmlmepriv= &padapter->mlmepriv;
++ struct security_priv *psecuritypriv = &padapter->securitypriv;
++
++ //xmit_priv
++ pxmitpriv->vcs_setting = pregistrypriv->vrtl_carrier_sense;
++ pxmitpriv->vcs = pregistrypriv->vcs_type;
++ pxmitpriv->vcs_type = pregistrypriv->vcs_type;
++ //pxmitpriv->rts_thresh = pregistrypriv->rts_thresh;
++ pxmitpriv->frag_len = pregistrypriv->frag_thresh;
++
++
++
++ //recv_priv
++
++
++ //mlme_priv
++ pmlmepriv->scan_interval = SCAN_INTERVAL;// 30*2 sec = 60sec
++ pmlmepriv->scan_mode = SCAN_ACTIVE;
++
++ //qos_priv
++ //pmlmepriv->qospriv.qos_option = pregistrypriv->wmm_enable;
++
++ //ht_priv
++#ifdef CONFIG_80211N_HT
++ pmlmepriv->htpriv.ampdu_enable = _FALSE;//set to disabled
++#endif
++
++ //security_priv
++ //rtw_get_encrypt_decrypt_from_registrypriv(padapter);
++ psecuritypriv->binstallGrpkey = _FAIL;
++ psecuritypriv->sw_encrypt=pregistrypriv->software_encrypt;
++ psecuritypriv->sw_decrypt=pregistrypriv->software_decrypt;
++
++ psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Open; //open system
++ psecuritypriv->dot11PrivacyAlgrthm = _NO_PRIVACY_;
++
++ psecuritypriv->dot11PrivacyKeyIndex = 0;
++
++ psecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_;
++ psecuritypriv->dot118021XGrpKeyid = 1;
++
++ psecuritypriv->ndisauthtype = Ndis802_11AuthModeOpen;
++ psecuritypriv->ndisencryptstatus = Ndis802_11WEPDisabled;
++
++
++ //pwrctrl_priv
++
++
++ //registry_priv
++ rtw_init_registrypriv_dev_network(padapter);
++ rtw_update_registrypriv_dev_network(padapter);
++
++
++ //hal_priv
++ rtw_hal_def_value_init(padapter);
++
++ //misc.
++ padapter->bReadPortCancel = _FALSE;
++ padapter->bWritePortCancel = _FALSE;
++ padapter->bRxRSSIDisplay = 0;
++ padapter->bForceWriteInitGain = 1;
++ padapter->bNotifyChannelChange = 0;
++#ifdef CONFIG_P2P
++ padapter->bShowGetP2PState = 1;
++#endif
++ return ret;
++}
++
++struct dvobj_priv *devobj_init(void)
++{
++ struct dvobj_priv *pdvobj = NULL;
++
++ if ((pdvobj = (struct dvobj_priv*)rtw_zmalloc(sizeof(*pdvobj))) == NULL)
++ return NULL;
++
++ _rtw_mutex_init(&pdvobj->hw_init_mutex);
++ _rtw_mutex_init(&pdvobj->h2c_fwcmd_mutex);
++ _rtw_mutex_init(&pdvobj->setch_mutex);
++ _rtw_mutex_init(&pdvobj->setbw_mutex);
++
++ pdvobj->processing_dev_remove = _FALSE;
++
++ return pdvobj;
++}
++
++void devobj_deinit(struct dvobj_priv *pdvobj)
++{
++ if(!pdvobj)
++ return;
++
++ _rtw_mutex_free(&pdvobj->hw_init_mutex);
++ _rtw_mutex_free(&pdvobj->h2c_fwcmd_mutex);
++ _rtw_mutex_free(&pdvobj->setch_mutex);
++ _rtw_mutex_free(&pdvobj->setbw_mutex);
++
++ rtw_mfree((u8*)pdvobj, sizeof(*pdvobj));
++}
++
++u8 rtw_reset_drv_sw(_adapter *padapter)
++{
++ u8 ret8=_SUCCESS;
++ struct mlme_priv *pmlmepriv= &padapter->mlmepriv;
++ struct pwrctrl_priv *pwrctrlpriv = &padapter->pwrctrlpriv;
++
++ //hal_priv
++ rtw_hal_def_value_init(padapter);
++ padapter->bReadPortCancel = _FALSE;
++ padapter->bWritePortCancel = _FALSE;
++ padapter->bRxRSSIDisplay = 0;
++ pmlmepriv->scan_interval = SCAN_INTERVAL;// 30*2 sec = 60sec
++
++ pwrctrlpriv->bips_processing = _FALSE;
++ pwrctrlpriv->rf_pwrstate = rf_on;
++
++ padapter->xmitpriv.tx_pkts = 0;
++ padapter->recvpriv.rx_pkts = 0;
++
++ pmlmepriv->LinkDetectInfo.bBusyTraffic = _FALSE;
++
++ _clr_fwstate_(pmlmepriv, _FW_UNDER_SURVEY |_FW_UNDER_LINKING);
++
++#ifdef CONFIG_AUTOSUSPEND
++ #if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,22) && LINUX_VERSION_CODE<=KERNEL_VERSION(2,6,34))
++ adapter_to_dvobj(padapter)->pusbdev->autosuspend_disabled = 1;//autosuspend disabled by the user
++ #endif
++#endif
++
++#ifdef DBG_CONFIG_ERROR_DETECT
++ rtw_hal_sreset_reset_value(padapter);
++#endif
++ pwrctrlpriv->pwr_state_check_cnts = 0;
++
++ //mlmeextpriv
++ padapter->mlmeextpriv.sitesurvey_res.state= SCAN_DISABLE;
++
++#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
++ rtw_set_signal_stat_timer(&padapter->recvpriv);
++#endif
++
++ return ret8;
++}
++
++
++u8 rtw_init_drv_sw(_adapter *padapter)
++{
++
++ u8 ret8=_SUCCESS;
++
++_func_enter_;
++
++ RT_TRACE(_module_os_intfs_c_,_drv_info_,("+rtw_init_drv_sw\n"));
++
++ if ((rtw_init_cmd_priv(&padapter->cmdpriv)) == _FAIL)
++ {
++ RT_TRACE(_module_os_intfs_c_,_drv_err_,("\n Can't init cmd_priv\n"));
++ ret8=_FAIL;
++ goto exit;
++ }
++
++ padapter->cmdpriv.padapter=padapter;
++
++ if ((rtw_init_evt_priv(&padapter->evtpriv)) == _FAIL)
++ {
++ RT_TRACE(_module_os_intfs_c_,_drv_err_,("\n Can't init evt_priv\n"));
++ ret8=_FAIL;
++ goto exit;
++ }
++
++
++ if (rtw_init_mlme_priv(padapter) == _FAIL)
++ {
++ RT_TRACE(_module_os_intfs_c_,_drv_err_,("\n Can't init mlme_priv\n"));
++ ret8=_FAIL;
++ goto exit;
++ }
++
++#ifdef CONFIG_P2P
++ rtw_init_wifidirect_timers(padapter);
++ init_wifidirect_info(padapter, P2P_ROLE_DISABLE);
++ reset_global_wifidirect_info(padapter);
++ #ifdef CONFIG_IOCTL_CFG80211
++ rtw_init_cfg80211_wifidirect_info(padapter);
++ #endif
++#ifdef CONFIG_WFD
++ if(rtw_init_wifi_display_info(padapter) == _FAIL)
++ RT_TRACE(_module_os_intfs_c_,_drv_err_,("\n Can't init init_wifi_display_info\n"));
++#endif
++#endif /* CONFIG_P2P */
++
++ if(init_mlme_ext_priv(padapter) == _FAIL)
++ {
++ RT_TRACE(_module_os_intfs_c_,_drv_err_,("\n Can't init mlme_ext_priv\n"));
++ ret8=_FAIL;
++ goto exit;
++ }
++
++#ifdef CONFIG_TDLS
++ if(rtw_init_tdls_info(padapter) == _FAIL)
++ {
++ DBG_871X("Can't rtw_init_tdls_info\n");
++ ret8=_FAIL;
++ goto exit;
++ }
++#endif //CONFIG_TDLS
++
++ if(_rtw_init_xmit_priv(&padapter->xmitpriv, padapter) == _FAIL)
++ {
++ DBG_871X("Can't _rtw_init_xmit_priv\n");
++ ret8=_FAIL;
++ goto exit;
++ }
++
++ if(_rtw_init_recv_priv(&padapter->recvpriv, padapter) == _FAIL)
++ {
++ DBG_871X("Can't _rtw_init_recv_priv\n");
++ ret8=_FAIL;
++ goto exit;
++ }
++ // add for CONFIG_IEEE80211W, none 11w also can use
++ _rtw_spinlock_init(&padapter->security_key_mutex);
++
++ // We don't need to memset padapter->XXX to zero, because adapter is allocated by rtw_zvmalloc().
++ //_rtw_memset((unsigned char *)&padapter->securitypriv, 0, sizeof (struct security_priv));
++
++ //_init_timer(&(padapter->securitypriv.tkip_timer), padapter->pifp, rtw_use_tkipkey_handler, padapter);
++
++ if(_rtw_init_sta_priv(&padapter->stapriv) == _FAIL)
++ {
++ DBG_871X("Can't _rtw_init_sta_priv\n");
++ ret8=_FAIL;
++ goto exit;
++ }
++
++ padapter->stapriv.padapter = padapter;
++ padapter->setband = GHZ24_50;
++ rtw_init_bcmc_stainfo(padapter);
++
++ rtw_init_pwrctrl_priv(padapter);
++
++ //_rtw_memset((u8 *)&padapter->qospriv, 0, sizeof (struct qos_priv));//move to mlme_priv
++
++#ifdef CONFIG_MP_INCLUDED
++ if (init_mp_priv(padapter) == _FAIL) {
++ DBG_871X("%s: initialize MP private data Fail!\n", __func__);
++ }
++#endif
++
++ ret8 = rtw_init_default_value(padapter);
++
++ rtw_hal_dm_init(padapter);
++ rtw_hal_sw_led_init(padapter);
++
++#ifdef DBG_CONFIG_ERROR_DETECT
++ rtw_hal_sreset_init(padapter);
++#endif
++
++#ifdef CONFIG_INTEL_WIDI
++ if(rtw_init_intel_widi(padapter) == _FAIL)
++ {
++ DBG_871X("Can't rtw_init_intel_widi\n");
++ ret8=_FAIL;
++ goto exit;
++ }
++#endif //CONFIG_INTEL_WIDI
++
++#ifdef CONFIG_BR_EXT
++ _rtw_spinlock_init(&padapter->br_ext_lock);
++#endif // CONFIG_BR_EXT
++
++exit:
++
++ RT_TRACE(_module_os_intfs_c_,_drv_info_,("-rtw_init_drv_sw\n"));
++
++ _func_exit_;
++
++ return ret8;
++
++}
++
++void rtw_cancel_all_timer(_adapter *padapter)
++{
++ RT_TRACE(_module_os_intfs_c_,_drv_info_,("+rtw_cancel_all_timer\n"));
++
++ _cancel_timer_ex(&padapter->mlmepriv.assoc_timer);
++ RT_TRACE(_module_os_intfs_c_,_drv_info_,("rtw_cancel_all_timer:cancel association timer complete! \n"));
++
++ //_cancel_timer_ex(&padapter->securitypriv.tkip_timer);
++ //RT_TRACE(_module_os_intfs_c_,_drv_info_,("rtw_cancel_all_timer:cancel tkip_timer! \n"));
++
++ _cancel_timer_ex(&padapter->mlmepriv.scan_to_timer);
++ RT_TRACE(_module_os_intfs_c_,_drv_info_,("rtw_cancel_all_timer:cancel scan_to_timer! \n"));
++
++ _cancel_timer_ex(&padapter->mlmepriv.dynamic_chk_timer);
++ RT_TRACE(_module_os_intfs_c_,_drv_info_,("rtw_cancel_all_timer:cancel dynamic_chk_timer! \n"));
++
++ // cancel sw led timer
++ rtw_hal_sw_led_deinit(padapter);
++ RT_TRACE(_module_os_intfs_c_,_drv_info_,("rtw_cancel_all_timer:cancel DeInitSwLeds! \n"));
++
++ _cancel_timer_ex(&padapter->pwrctrlpriv.pwr_state_check_timer);
++
++#ifdef CONFIG_IOCTL_CFG80211
++#ifdef CONFIG_P2P
++ _cancel_timer_ex(&padapter->cfg80211_wdinfo.remain_on_ch_timer);
++#endif //CONFIG_P2P
++#endif //CONFIG_IOCTL_CFG80211
++
++#ifdef CONFIG_SET_SCAN_DENY_TIMER
++ _cancel_timer_ex(&padapter->mlmepriv.set_scan_deny_timer);
++ rtw_clear_scan_deny(padapter);
++ RT_TRACE(_module_os_intfs_c_,_drv_info_,("rtw_cancel_all_timer:cancel set_scan_deny_timer! \n"));
++#endif
++
++#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
++ _cancel_timer_ex(&padapter->recvpriv.signal_stat_timer);
++#endif
++
++ // cancel dm timer
++ rtw_hal_dm_deinit(padapter);
++
++#ifdef CONFIG_PLATFORM_FS_MX61
++ msleep(50);
++#endif
++}
++
++u8 rtw_free_drv_sw(_adapter *padapter)
++{
++ RT_TRACE(_module_os_intfs_c_,_drv_info_,("==>rtw_free_drv_sw"));
++
++
++ //we can call rtw_p2p_enable here, but:
++ // 1. rtw_p2p_enable may have IO operation
++ // 2. rtw_p2p_enable is bundled with wext interface
++ #ifdef CONFIG_P2P
++ {
++ struct wifidirect_info *pwdinfo = &padapter->wdinfo;
++ if(!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
++ {
++ _cancel_timer_ex( &pwdinfo->find_phase_timer );
++ _cancel_timer_ex( &pwdinfo->restore_p2p_state_timer );
++ _cancel_timer_ex( &pwdinfo->pre_tx_scan_timer);
++#ifdef CONFIG_CONCURRENT_MODE
++ _cancel_timer_ex( &pwdinfo->ap_p2p_switch_timer );
++#endif // CONFIG_CONCURRENT_MODE
++ rtw_p2p_set_state(pwdinfo, P2P_STATE_NONE);
++ }
++ }
++ #endif
++ // add for CONFIG_IEEE80211W, none 11w also can use
++ _rtw_spinlock_free(&padapter->security_key_mutex);
++
++#ifdef CONFIG_BR_EXT
++ _rtw_spinlock_free(&padapter->br_ext_lock);
++#endif // CONFIG_BR_EXT
++
++#ifdef CONFIG_INTEL_WIDI
++ rtw_free_intel_widi(padapter);
++#endif //CONFIG_INTEL_WIDI
++
++ free_mlme_ext_priv(&padapter->mlmeextpriv);
++
++#ifdef CONFIG_TDLS
++ //rtw_free_tdls_info(&padapter->tdlsinfo);
++#endif //CONFIG_TDLS
++
++ rtw_free_cmd_priv(&padapter->cmdpriv);
++
++ rtw_free_evt_priv(&padapter->evtpriv);
++
++ rtw_free_mlme_priv(&padapter->mlmepriv);
++
++ //free_io_queue(padapter);
++
++ _rtw_free_xmit_priv(&padapter->xmitpriv);
++
++ _rtw_free_sta_priv(&padapter->stapriv); //will free bcmc_stainfo here
++
++ _rtw_free_recv_priv(&padapter->recvpriv);
++
++ rtw_free_pwrctrl_priv(padapter);
++
++ //rtw_mfree((void *)padapter, sizeof (padapter));
++
++#ifdef CONFIG_DRVEXT_MODULE
++ free_drvext(&padapter->drvextpriv);
++#endif
++
++ rtw_hal_free_data(padapter);
++
++ RT_TRACE(_module_os_intfs_c_,_drv_info_,("<==rtw_free_drv_sw\n"));
++
++ //free the old_pnetdev
++ if(padapter->rereg_nd_name_priv.old_pnetdev) {
++ free_netdev(padapter->rereg_nd_name_priv.old_pnetdev);
++ padapter->rereg_nd_name_priv.old_pnetdev = NULL;
++ }
++
++ // clear pbuddy_adapter to avoid access wrong pointer.
++ if(padapter->pbuddy_adapter != NULL)
++ {
++ padapter->pbuddy_adapter->pbuddy_adapter = NULL;
++ }
++
++ RT_TRACE(_module_os_intfs_c_,_drv_info_,("-rtw_free_drv_sw\n"));
++
++ return _SUCCESS;
++
++}
++
++#ifdef CONFIG_CONCURRENT_MODE
++
++#ifdef CONFIG_USB_HCI
++ #include <usb_hal.h>
++#endif
++
++#ifdef CONFIG_MULTI_VIR_IFACES
++int _netdev_vir_if_open(struct net_device *pnetdev)
++{
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev);
++ _adapter *primary_padapter = GET_PRIMARY_ADAPTER(padapter);
++
++ DBG_871X(FUNC_NDEV_FMT" enter\n", FUNC_NDEV_ARG(pnetdev));
++
++ if(!primary_padapter)
++ goto _netdev_virtual_iface_open_error;
++
++ if(primary_padapter->bup == _FALSE || primary_padapter->hw_init_completed == _FALSE)
++ {
++ _netdev_open(primary_padapter->pnetdev);
++ }
++
++ if(padapter->bup == _FALSE && primary_padapter->bup == _TRUE &&
++ primary_padapter->hw_init_completed == _TRUE)
++ {
++ int i;
++
++ padapter->bDriverStopped = _FALSE;
++ padapter->bSurpriseRemoved = _FALSE;
++ padapter->bCardDisableWOHSM = _FALSE;
++
++ _rtw_memcpy(padapter->HalData, primary_padapter->HalData, padapter->hal_data_sz);
++
++ padapter->bFWReady = primary_padapter->bFWReady;
++
++ if(rtw_start_drv_threads(padapter) == _FAIL)
++ {
++ goto _netdev_virtual_iface_open_error;
++ }
++
++ padapter->dir_dev = NULL;
++ rtw_proc_init_one(pnetdev);
++
++#ifdef CONFIG_IOCTL_CFG80211
++ rtw_cfg80211_init_wiphy(padapter);
++#endif
++
++ padapter->bup = _TRUE;
++ padapter->hw_init_completed = _TRUE;
++
++ rtw_start_mbssid_cam(padapter);//start mbssid_cam after bup = _TRUE & hw_init_completed = _TRUE
++
++ }
++
++ padapter->net_closed = _FALSE;
++
++ _set_timer(&padapter->mlmepriv.dynamic_chk_timer, 2000);
++
++ if(!rtw_netif_queue_stopped(pnetdev))
++ rtw_netif_start_queue(pnetdev);
++ else
++ rtw_netif_wake_queue(pnetdev);
++
++
++ DBG_871X(FUNC_NDEV_FMT" exit\n", FUNC_NDEV_ARG(pnetdev));
++ return 0;
++
++_netdev_virtual_iface_open_error:
++
++ padapter->bup = _FALSE;
++
++ netif_carrier_off(pnetdev);
++ rtw_netif_stop_queue(pnetdev);
++
++ return (-1);
++
++}
++
++int netdev_vir_if_open(struct net_device *pnetdev)
++{
++ int ret;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev);
++
++ _enter_critical_mutex(&(adapter_to_dvobj(padapter)->hw_init_mutex), NULL);
++ ret = _netdev_vir_if_open(pnetdev);
++ _exit_critical_mutex(&(adapter_to_dvobj(padapter)->hw_init_mutex), NULL);
++ return ret;
++}
++
++static int netdev_vir_if_close(struct net_device *pnetdev)
++{
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev);
++
++ padapter->net_closed = _TRUE;
++
++ if(pnetdev)
++ {
++ if (!rtw_netif_queue_stopped(pnetdev))
++ rtw_netif_stop_queue(pnetdev);
++ }
++
++#ifdef CONFIG_IOCTL_CFG80211
++ rtw_scan_abort(padapter);
++ wdev_to_priv(padapter->rtw_wdev)->bandroid_scan = _FALSE;
++#endif
++
++ return 0;
++}
++
++#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,29))
++static const struct net_device_ops rtw_netdev_vir_if_ops = {
++ .ndo_open = netdev_vir_if_open,
++ .ndo_stop = netdev_vir_if_close,
++ .ndo_start_xmit = rtw_xmit_entry,
++ .ndo_set_mac_address = rtw_net_set_mac_address,
++ .ndo_get_stats = rtw_net_get_stats,
++ .ndo_do_ioctl = rtw_ioctl,
++#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,35))
++ .ndo_select_queue = rtw_select_queue,
++#endif
++};
++#endif
++
++_adapter *rtw_drv_add_vir_if(_adapter *primary_padapter, void (*set_intf_ops)(struct _io_ops *pops))
++{
++
++ int res = _FAIL;
++ struct net_device *pnetdev=NULL;
++ _adapter *padapter = NULL;
++ struct dvobj_priv *pdvobjpriv;
++ u8 mac[ETH_ALEN];
++
++/*
++ if((primary_padapter->bup == _FALSE) ||
++ (rtw_buddy_adapter_up(primary_padapter) == _FALSE))
++ {
++ goto error_rtw_drv_add_iface;
++ }
++
++*/
++ /****** init netdev ******/
++ pnetdev = rtw_init_netdev(NULL);
++ if (!pnetdev)
++ goto error_rtw_drv_add_iface;
++
++#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,29))
++ DBG_871X("register rtw_netdev_virtual_iface_ops to netdev_ops\n");
++ pnetdev->netdev_ops = &rtw_netdev_vir_if_ops;
++#else
++ pnetdev->open = netdev_vir_if_open;
++ pnetdev->stop = netdev_vir_if_close;
++#endif
++
++#ifdef CONFIG_NO_WIRELESS_HANDLERS
++ pnetdev->wireless_handlers = NULL;
++#endif
++
++ /****** init adapter ******/
++ padapter = rtw_netdev_priv(pnetdev);
++ _rtw_memcpy(padapter, primary_padapter, sizeof(_adapter));
++
++ //
++ padapter->bup = _FALSE;
++ padapter->net_closed = _TRUE;
++ padapter->hw_init_completed = _FALSE;
++
++
++ //set adapter_type/iface type
++ padapter->isprimary = _FALSE;
++ padapter->adapter_type = MAX_ADAPTER;
++ padapter->pbuddy_adapter = primary_padapter;
++#if 0
++#ifndef CONFIG_HWPORT_SWAP //Port0 -> Pri , Port1 -> Sec
++ padapter->iface_type = IFACE_PORT1;
++#else
++ padapter->iface_type = IFACE_PORT0;
++#endif //CONFIG_HWPORT_SWAP
++#else
++ //extended virtual interfaces always are set to port0
++ padapter->iface_type = IFACE_PORT0;
++#endif
++ //
++ padapter->pnetdev = pnetdev;
++
++ /****** setup dvobj ******/
++ pdvobjpriv = adapter_to_dvobj(padapter);
++ padapter->iface_id = pdvobjpriv->iface_nums;
++ pdvobjpriv->padapters[pdvobjpriv->iface_nums++] = padapter;
++
++ SET_NETDEV_DEV(pnetdev, dvobj_to_dev(pdvobjpriv));
++#ifdef CONFIG_IOCTL_CFG80211
++ rtw_wdev_alloc(padapter, dvobj_to_dev(pdvobjpriv));
++#endif //CONFIG_IOCTL_CFG80211
++
++ //set interface_type/chip_type/HardwareType
++ padapter->interface_type = primary_padapter->interface_type;
++ padapter->chip_type = primary_padapter->chip_type;
++ padapter->HardwareType = primary_padapter->HardwareType;
++
++ //set hal data & hal ops
++#if defined(CONFIG_RTL8192C)
++ #if defined(CONFIG_PCI_HCI)
++ rtl8192ce_set_hal_ops(padapter);
++ #elif defined(CONFIG_USB_HCI)
++ rtl8192cu_set_hal_ops(padapter);
++ #endif
++#elif defined(CONFIG_RTL8192D)
++ #if defined(CONFIG_PCI_HCI)
++ rtl8192de_set_hal_ops(padapter);
++ #elif defined(CONFIG_USB_HCI)
++ rtl8192du_set_hal_ops(padapter);
++ #endif
++#endif
++
++ padapter->HalFunc.inirp_init = NULL;
++ padapter->HalFunc.inirp_deinit = NULL;
++ padapter->intf_start = NULL;
++ padapter->intf_stop = NULL;
++
++ //step init_io_priv
++ if ((rtw_init_io_priv(padapter, set_intf_ops)) == _FAIL) {
++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,(" \n Can't init io_reqs\n"));
++ }
++
++ //step read_chip_version
++ rtw_hal_read_chip_version(padapter);
++
++ //step usb endpoint mapping
++ rtw_hal_chip_configure(padapter);
++
++
++ //init drv data
++ if(rtw_init_drv_sw(padapter)!= _SUCCESS)
++ goto error_rtw_drv_add_iface;
++
++
++ //get mac address from primary_padapter
++ _rtw_memcpy(mac, primary_padapter->eeprompriv.mac_addr, ETH_ALEN);
++
++ if (((mac[0]==0xff) &&(mac[1]==0xff) && (mac[2]==0xff) &&
++ (mac[3]==0xff) && (mac[4]==0xff) &&(mac[5]==0xff)) ||
++ ((mac[0]==0x0) && (mac[1]==0x0) && (mac[2]==0x0) &&
++ (mac[3]==0x0) && (mac[4]==0x0) &&(mac[5]==0x0)))
++ {
++ mac[0] = 0x00;
++ mac[1] = 0xe0;
++ mac[2] = 0x4c;
++ mac[3] = 0x87;
++ mac[4] = 0x11;
++ mac[5] = 0x22;
++ }
++ else
++ {
++ //If the BIT1 is 0, the address is universally administered.
++ //If it is 1, the address is locally administered
++#if 1 //needs enable MBSSID CAM
++ mac[0] |= BIT(1); // locally administered
++ mac[0] |= (padapter->iface_id-1)<<4;
++#endif
++ }
++
++ _rtw_memcpy(padapter->eeprompriv.mac_addr, mac, ETH_ALEN);
++
++ padapter->dir_dev = NULL;
++
++ res = _SUCCESS;
++
++ return padapter;
++
++
++error_rtw_drv_add_iface:
++
++ if(padapter)
++ rtw_free_drv_sw(padapter);
++
++ if (pnetdev)
++ rtw_free_netdev(pnetdev);
++
++ return NULL;
++
++}
++
++void rtw_drv_stop_vir_if(_adapter *padapter)
++{
++ struct net_device *pnetdev=NULL;
++
++ if (padapter == NULL)
++ return;
++
++ pnetdev = padapter->pnetdev;
++
++ rtw_cancel_all_timer(padapter);
++
++ if(padapter->bup == _TRUE)
++ {
++ padapter->bDriverStopped = _TRUE;
++
++ #ifdef CONFIG_XMIT_ACK
++ if (padapter->xmitpriv.ack_tx)
++ rtw_ack_tx_done(&padapter->xmitpriv, RTW_SCTX_DONE_DRV_STOP);
++ #endif
++
++ if(padapter->intf_stop)
++ {
++ padapter->intf_stop(padapter);
++ }
++
++ rtw_stop_drv_threads(padapter);
++
++ padapter->bup = _FALSE;
++ }
++}
++
++void rtw_drv_free_vir_if(_adapter *padapter)
++{
++ struct net_device *pnetdev=NULL;
++
++ if (padapter == NULL)
++ return;
++
++ padapter->pbuddy_adapter = NULL;
++
++ pnetdev = padapter->pnetdev;
++
++#ifdef CONFIG_IOCTL_CFG80211
++ rtw_wdev_free(padapter->rtw_wdev);
++#endif //CONFIG_IOCTL_CFG80211
++
++ rtw_free_drv_sw(padapter);
++
++ rtw_free_netdev(pnetdev);
++}
++
++void rtw_drv_stop_vir_ifaces(struct dvobj_priv *dvobj)
++{
++ int i;
++ //struct dvobj_priv *dvobj = primary_padapter->dvobj;
++
++ for(i=2;i<dvobj->iface_nums;i++)
++ {
++ rtw_drv_stop_vir_if(dvobj->padapters[i]);
++ }
++}
++
++void rtw_drv_free_vir_ifaces(struct dvobj_priv *dvobj)
++{
++ int i;
++ //struct dvobj_priv *dvobj = primary_padapter->dvobj;
++
++ for(i=2;i<dvobj->iface_nums;i++)
++ {
++ rtw_drv_free_vir_if(dvobj->padapters[i]);
++ }
++}
++
++void rtw_drv_del_vir_if(_adapter *padapter)
++{
++ rtw_drv_stop_vir_if(padapter);
++ rtw_drv_free_vir_if(padapter);
++}
++
++void rtw_drv_del_vir_ifaces(_adapter *primary_padapter)
++{
++ int i;
++ struct dvobj_priv *dvobj = primary_padapter->dvobj;
++
++ for(i=2;i<dvobj->iface_nums;i++)
++ {
++ rtw_drv_del_vir_if(dvobj->padapters[i]);
++ }
++}
++#endif //CONFIG_MULTI_VIR_IFACES
++
++int _netdev_if2_open(struct net_device *pnetdev)
++{
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev);
++ _adapter *primary_padapter = padapter->pbuddy_adapter;
++
++ DBG_871X("+871x_drv - if2_open, bup=%d\n", padapter->bup);
++
++ if(primary_padapter->bup == _FALSE || primary_padapter->hw_init_completed == _FALSE)
++ {
++ _netdev_open(primary_padapter->pnetdev);
++ }
++
++ if(padapter->bup == _FALSE && primary_padapter->bup == _TRUE &&
++ primary_padapter->hw_init_completed == _TRUE)
++ {
++ int i;
++
++ padapter->bDriverStopped = _FALSE;
++ padapter->bSurpriseRemoved = _FALSE;
++ padapter->bCardDisableWOHSM = _FALSE;
++
++ _rtw_memcpy(padapter->HalData, primary_padapter->HalData, padapter->hal_data_sz);
++
++ padapter->bFWReady = primary_padapter->bFWReady;
++
++ rtw_hal_set_hwreg(padapter, HW_VAR_DM_INIT_PWDB, NULL);
++
++ //if (init_mlme_ext_priv(padapter) == _FAIL)
++ // goto netdev_if2_open_error;
++
++
++ if(rtw_start_drv_threads(padapter) == _FAIL)
++ {
++ goto netdev_if2_open_error;
++ }
++
++
++ if(padapter->intf_start)
++ {
++ padapter->intf_start(padapter);
++ }
++
++
++ padapter->hw_init_completed = _TRUE;
++
++ padapter->dir_dev = NULL;
++ rtw_proc_init_one(pnetdev);
++
++
++#ifdef CONFIG_IOCTL_CFG80211
++ rtw_cfg80211_init_wiphy(padapter);
++#endif
++
++ padapter->bup = _TRUE;
++
++ }
++
++ padapter->net_closed = _FALSE;
++
++ _set_timer(&padapter->mlmepriv.dynamic_chk_timer, 2000);
++
++ if(!rtw_netif_queue_stopped(pnetdev))
++ rtw_netif_start_queue(pnetdev);
++ else
++ rtw_netif_wake_queue(pnetdev);
++
++ DBG_871X("-871x_drv - if2_open, bup=%d\n", padapter->bup);
++ return 0;
++
++netdev_if2_open_error:
++
++ padapter->bup = _FALSE;
++
++ netif_carrier_off(pnetdev);
++ rtw_netif_stop_queue(pnetdev);
++
++ return (-1);
++
++}
++
++int netdev_if2_open(struct net_device *pnetdev)
++{
++ int ret;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev);
++
++ _enter_critical_mutex(&(adapter_to_dvobj(padapter)->hw_init_mutex), NULL);
++ ret = _netdev_if2_open(pnetdev);
++ _exit_critical_mutex(&(adapter_to_dvobj(padapter)->hw_init_mutex), NULL);
++ return ret;
++}
++
++static int netdev_if2_close(struct net_device *pnetdev)
++{
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev);
++
++ padapter->net_closed = _TRUE;
++
++ if(pnetdev)
++ {
++ if (!rtw_netif_queue_stopped(pnetdev))
++ rtw_netif_stop_queue(pnetdev);
++ }
++
++#ifdef CONFIG_IOCTL_CFG80211
++ rtw_scan_abort(padapter);
++ wdev_to_priv(padapter->rtw_wdev)->bandroid_scan = _FALSE;
++#endif
++
++ return 0;
++}
++
++#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,29))
++static const struct net_device_ops rtw_netdev_if2_ops = {
++ .ndo_open = netdev_if2_open,
++ .ndo_stop = netdev_if2_close,
++ .ndo_start_xmit = rtw_xmit_entry,
++ .ndo_set_mac_address = rtw_net_set_mac_address,
++ .ndo_get_stats = rtw_net_get_stats,
++ .ndo_do_ioctl = rtw_ioctl,
++#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,35))
++ .ndo_select_queue = rtw_select_queue,
++#endif
++};
++#endif
++
++_adapter *rtw_drv_if2_init(_adapter *primary_padapter, void (*set_intf_ops)(struct _io_ops *pops))
++{
++ int res = _FAIL;
++ struct net_device *pnetdev = NULL;
++ _adapter *padapter = NULL;
++ struct dvobj_priv *pdvobjpriv;
++ u8 mac[ETH_ALEN];
++
++ /****** init netdev ******/
++ pnetdev = rtw_init_netdev(NULL);
++ if (!pnetdev)
++ goto error_rtw_drv_if2_init;
++
++#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,29))
++ DBG_871X("register rtw_netdev_if2_ops to netdev_ops\n");
++ pnetdev->netdev_ops = &rtw_netdev_if2_ops;
++#else
++ pnetdev->open = netdev_if2_open;
++ pnetdev->stop = netdev_if2_close;
++#endif
++
++#ifdef CONFIG_NO_WIRELESS_HANDLERS
++ pnetdev->wireless_handlers = NULL;
++#endif
++
++ /****** init adapter ******/
++ padapter = rtw_netdev_priv(pnetdev);
++ _rtw_memcpy(padapter, primary_padapter, sizeof(_adapter));
++
++ //
++ padapter->bup = _FALSE;
++ padapter->net_closed = _TRUE;
++ padapter->hw_init_completed = _FALSE;
++
++ //set adapter_type/iface type
++ padapter->isprimary = _FALSE;
++ padapter->adapter_type = SECONDARY_ADAPTER;
++ padapter->pbuddy_adapter = primary_padapter;
++ padapter->iface_id = IFACE_ID1;
++#ifndef CONFIG_HWPORT_SWAP //Port0 -> Pri , Port1 -> Sec
++ padapter->iface_type = IFACE_PORT1;
++#else
++ padapter->iface_type = IFACE_PORT0;
++#endif //CONFIG_HWPORT_SWAP
++ //
++ padapter->pnetdev = pnetdev;
++
++ /****** setup dvobj ******/
++ pdvobjpriv = adapter_to_dvobj(padapter);
++ pdvobjpriv->if2 = padapter;
++ pdvobjpriv->padapters[pdvobjpriv->iface_nums++] = padapter;
++
++ SET_NETDEV_DEV(pnetdev, dvobj_to_dev(pdvobjpriv));
++ #ifdef CONFIG_IOCTL_CFG80211
++ rtw_wdev_alloc(padapter, dvobj_to_dev(pdvobjpriv));
++ #endif //CONFIG_IOCTL_CFG80211
++
++ //set interface_type/chip_type/HardwareType
++ padapter->interface_type = primary_padapter->interface_type;
++ padapter->chip_type = primary_padapter->chip_type;
++ padapter->HardwareType = primary_padapter->HardwareType;
++
++ //set hal data & hal ops
++#if defined(CONFIG_RTL8192C)
++ #if defined(CONFIG_PCI_HCI)
++ rtl8192ce_set_hal_ops(padapter);
++ #elif defined(CONFIG_USB_HCI)
++ rtl8192cu_set_hal_ops(padapter);
++ #endif
++#elif defined(CONFIG_RTL8192D)
++ #if defined(CONFIG_PCI_HCI)
++ rtl8192de_set_hal_ops(padapter);
++ #elif defined(CONFIG_USB_HCI)
++ rtl8192du_set_hal_ops(padapter);
++ #endif
++#endif
++
++ padapter->HalFunc.inirp_init = NULL;
++ padapter->HalFunc.inirp_deinit = NULL;
++
++ //
++ padapter->intf_start = primary_padapter->intf_start;
++ padapter->intf_stop = primary_padapter->intf_stop;
++
++ //step init_io_priv
++ if ((rtw_init_io_priv(padapter, set_intf_ops)) == _FAIL) {
++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,(" \n Can't init io_reqs\n"));
++ }
++
++ //step read_chip_version
++ rtw_hal_read_chip_version(padapter);
++
++ //step usb endpoint mapping
++ rtw_hal_chip_configure(padapter);
++
++
++ //init drv data
++ if(rtw_init_drv_sw(padapter)!= _SUCCESS)
++ goto error_rtw_drv_if2_init;
++
++ //get mac address from primary_padapter
++ _rtw_memcpy(mac, primary_padapter->eeprompriv.mac_addr, ETH_ALEN);
++
++ if (((mac[0]==0xff) &&(mac[1]==0xff) && (mac[2]==0xff) &&
++ (mac[3]==0xff) && (mac[4]==0xff) &&(mac[5]==0xff)) ||
++ ((mac[0]==0x0) && (mac[1]==0x0) && (mac[2]==0x0) &&
++ (mac[3]==0x0) && (mac[4]==0x0) &&(mac[5]==0x0)))
++ {
++ mac[0] = 0x00;
++ mac[1] = 0xe0;
++ mac[2] = 0x4c;
++ mac[3] = 0x87;
++ mac[4] = 0x11;
++ mac[5] = 0x22;
++ }
++ else
++ {
++ //If the BIT1 is 0, the address is universally administered.
++ //If it is 1, the address is locally administered
++ mac[0] |= BIT(1); // locally administered
++
++ }
++
++ _rtw_memcpy(padapter->eeprompriv.mac_addr, mac, ETH_ALEN);
++ rtw_init_wifidirect_addrs(padapter, padapter->eeprompriv.mac_addr, padapter->eeprompriv.mac_addr);
++
++ primary_padapter->pbuddy_adapter = padapter;
++
++ padapter->dir_dev = NULL;
++
++ res = _SUCCESS;
++
++ return padapter;
++
++
++error_rtw_drv_if2_init:
++
++ if(padapter)
++ rtw_free_drv_sw(padapter);
++
++ if (pnetdev)
++ rtw_free_netdev(pnetdev);
++
++ return NULL;
++
++}
++
++void rtw_drv_if2_free(_adapter *if2)
++{
++ _adapter *padapter = if2;
++ struct net_device *pnetdev = NULL;
++
++ if (padapter == NULL)
++ return;
++
++ pnetdev = padapter->pnetdev;
++
++#ifdef CONFIG_IOCTL_CFG80211
++ rtw_wdev_free(padapter->rtw_wdev);
++#endif /* CONFIG_IOCTL_CFG80211 */
++
++
++ rtw_free_drv_sw(padapter);
++
++ rtw_free_netdev(pnetdev);
++
++}
++
++void rtw_drv_if2_stop(_adapter *if2)
++{
++ _adapter *padapter = if2;
++
++ if (padapter == NULL)
++ return;
++
++ rtw_cancel_all_timer(padapter);
++
++ if (padapter->bup == _TRUE) {
++ padapter->bDriverStopped = _TRUE;
++ #ifdef CONFIG_XMIT_ACK
++ if (padapter->xmitpriv.ack_tx)
++ rtw_ack_tx_done(&padapter->xmitpriv, RTW_SCTX_DONE_DRV_STOP);
++ #endif
++
++ if(padapter->intf_stop)
++ {
++ padapter->intf_stop(padapter);
++ }
++
++ rtw_stop_drv_threads(padapter);
++
++ padapter->bup = _FALSE;
++ }
++}
++#endif //end of CONFIG_CONCURRENT_MODE
++
++#ifdef CONFIG_BR_EXT
++void netdev_br_init(struct net_device *netdev)
++{
++ _adapter *adapter = (_adapter *)rtw_netdev_priv(netdev);
++
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35))
++ rcu_read_lock();
++#endif // (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35))
++
++ //if(check_fwstate(pmlmepriv, WIFI_STATION_STATE|WIFI_ADHOC_STATE) == _TRUE)
++ {
++ //struct net_bridge *br = netdev->br_port->br;//->dev->dev_addr;
++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35))
++ if (netdev->br_port)
++#else // (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35))
++ if (rcu_dereference(adapter->pnetdev->rx_handler_data))
++#endif // (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35))
++ {
++ struct net_device *br_netdev;
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24))
++ br_netdev = dev_get_by_name(CONFIG_BR_EXT_BRNAME);
++#else // (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24))
++ struct net *devnet = NULL;
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26))
++ devnet = netdev->nd_net;
++#else // (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26))
++ devnet = dev_net(netdev);
++#endif // (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26))
++
++ br_netdev = dev_get_by_name(devnet, CONFIG_BR_EXT_BRNAME);
++#endif // (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24))
++
++ if (br_netdev) {
++ memcpy(adapter->br_mac, br_netdev->dev_addr, ETH_ALEN);
++ dev_put(br_netdev);
++ } else
++ printk("%s()-%d: dev_get_by_name(%s) failed!", __FUNCTION__, __LINE__, CONFIG_BR_EXT_BRNAME);
++ }
++
++ adapter->ethBrExtInfo.addPPPoETag = 1;
++ }
++
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35))
++ rcu_read_unlock();
++#endif // (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35))
++}
++#endif //CONFIG_BR_EXT
++
++static int _rtw_drv_register_netdev(_adapter *padapter, char *name)
++{
++ int ret = _SUCCESS;
++ struct net_device *pnetdev = padapter->pnetdev;
++
++ /* alloc netdev name */
++ rtw_init_netdev_name(pnetdev, name);
++
++ _rtw_memcpy(pnetdev->dev_addr, padapter->eeprompriv.mac_addr, ETH_ALEN);
++
++ /* Tell the network stack we exist */
++ if (register_netdev(pnetdev) != 0) {
++ DBG_871X(FUNC_NDEV_FMT "Failed!\n", FUNC_NDEV_ARG(pnetdev));
++ ret = _FAIL;
++ goto error_register_netdev;
++ }
++
++ DBG_871X("%s, MAC Address (if%d) = " MAC_FMT "\n", __FUNCTION__, (padapter->iface_id+1), MAC_ARG(pnetdev->dev_addr));
++
++ return ret;
++
++error_register_netdev:
++
++ if(padapter->iface_id > IFACE_ID0)
++ {
++ rtw_free_drv_sw(padapter);
++
++ rtw_free_netdev(pnetdev);
++ }
++
++ return ret;
++}
++
++int rtw_drv_register_netdev(_adapter *if1)
++{
++ int i, status = _SUCCESS;
++ struct dvobj_priv *dvobj = if1->dvobj;
++
++ if(dvobj->iface_nums < IFACE_ID_MAX)
++ {
++ for(i=0; i<dvobj->iface_nums; i++)
++ {
++ _adapter *padapter = dvobj->padapters[i];
++
++ if(padapter)
++ {
++ char *name;
++
++ if(padapter->iface_id == IFACE_ID0)
++ name = if1->registrypriv.ifname;
++ else if(padapter->iface_id == IFACE_ID1)
++ name = if1->registrypriv.if2name;
++ else
++ name = "wlan%d";
++
++ if((status = _rtw_drv_register_netdev(padapter, name)) != _SUCCESS) {
++ break;
++ }
++ }
++ }
++ }
++
++ return status;
++}
++
++int _netdev_open(struct net_device *pnetdev)
++{
++ uint status;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev);
++ struct pwrctrl_priv *pwrctrlpriv = &padapter->pwrctrlpriv;
++
++ RT_TRACE(_module_os_intfs_c_,_drv_info_,("+871x_drv - dev_open\n"));
++ DBG_871X("+871x_drv - drv_open, bup=%d\n", padapter->bup);
++
++ if(pwrctrlpriv->ps_flag == _TRUE){
++ padapter->net_closed = _FALSE;
++ goto netdev_open_normal_process;
++ }
++
++ if(padapter->bup == _FALSE)
++ {
++ padapter->bDriverStopped = _FALSE;
++ padapter->bSurpriseRemoved = _FALSE;
++ padapter->bCardDisableWOHSM = _FALSE;
++
++ status = rtw_hal_init(padapter);
++ if (status ==_FAIL)
++ {
++ RT_TRACE(_module_os_intfs_c_,_drv_err_,("rtl871x_hal_init(): Can't init h/w!\n"));
++ goto netdev_open_error;
++ }
++
++ DBG_871X("MAC Address = "MAC_FMT"\n", MAC_ARG(pnetdev->dev_addr));
++
++
++ status=rtw_start_drv_threads(padapter);
++ if(status ==_FAIL)
++ {
++ RT_TRACE(_module_os_intfs_c_,_drv_err_,("Initialize driver software resource Failed!\n"));
++ goto netdev_open_error;
++ }
++
++#ifdef CONFIG_DRVEXT_MODULE
++ init_drvext(padapter);
++#endif
++
++ if(padapter->intf_start)
++ {
++ padapter->intf_start(padapter);
++ }
++
++#ifndef RTK_DMP_PLATFORM
++ rtw_proc_init_one(pnetdev);
++#endif
++
++#ifdef CONFIG_IOCTL_CFG80211
++ rtw_cfg80211_init_wiphy(padapter);
++#endif
++
++ rtw_led_control(padapter, LED_CTL_NO_LINK);
++
++ padapter->bup = _TRUE;
++ }
++ padapter->net_closed = _FALSE;
++
++ _set_timer(&padapter->mlmepriv.dynamic_chk_timer, 2000);
++
++ padapter->pwrctrlpriv.bips_processing = _FALSE;
++ rtw_set_pwr_state_check_timer(&padapter->pwrctrlpriv);
++
++ //netif_carrier_on(pnetdev);//call this func when rtw_joinbss_event_callback return success
++ if(!rtw_netif_queue_stopped(pnetdev))
++ rtw_netif_start_queue(pnetdev);
++ else
++ rtw_netif_wake_queue(pnetdev);
++
++#ifdef CONFIG_BR_EXT
++ netdev_br_init(pnetdev);
++#endif // CONFIG_BR_EXT
++
++netdev_open_normal_process:
++
++ #ifdef CONFIG_CONCURRENT_MODE
++ {
++ _adapter *sec_adapter = padapter->pbuddy_adapter;
++ if(sec_adapter && (sec_adapter->bup == _FALSE || sec_adapter->hw_init_completed == _FALSE))
++ _netdev_if2_open(sec_adapter->pnetdev);
++ }
++ #endif
++
++ RT_TRACE(_module_os_intfs_c_,_drv_info_,("-871x_drv - dev_open\n"));
++ DBG_871X("-871x_drv - drv_open, bup=%d\n", padapter->bup);
++
++ return 0;
++
++netdev_open_error:
++
++ padapter->bup = _FALSE;
++
++ netif_carrier_off(pnetdev);
++ rtw_netif_stop_queue(pnetdev);
++
++ RT_TRACE(_module_os_intfs_c_,_drv_err_,("-871x_drv - dev_open, fail!\n"));
++ DBG_871X("-871x_drv - drv_open fail, bup=%d\n", padapter->bup);
++
++ return (-1);
++
++}
++
++int netdev_open(struct net_device *pnetdev)
++{
++ int ret;
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev);
++
++ _enter_critical_mutex(&(adapter_to_dvobj(padapter)->hw_init_mutex), NULL);
++ ret = _netdev_open(pnetdev);
++ _exit_critical_mutex(&(adapter_to_dvobj(padapter)->hw_init_mutex), NULL);
++
++ return ret;
++}
++
++#ifdef CONFIG_IPS
++int ips_netdrv_open(_adapter *padapter)
++{
++ int status = _SUCCESS;
++ padapter->net_closed = _FALSE;
++ DBG_871X("===> %s.........\n",__FUNCTION__);
++
++
++ padapter->bDriverStopped = _FALSE;
++ padapter->bCardDisableWOHSM = _FALSE;
++ //padapter->bup = _TRUE;
++
++ status = rtw_hal_init(padapter);
++ if (status ==_FAIL)
++ {
++ RT_TRACE(_module_os_intfs_c_,_drv_err_,("ips_netdrv_open(): Can't init h/w!\n"));
++ goto netdev_open_error;
++ }
++
++ if(padapter->intf_start)
++ {
++ padapter->intf_start(padapter);
++ }
++
++ rtw_set_pwr_state_check_timer(&padapter->pwrctrlpriv);
++ _set_timer(&padapter->mlmepriv.dynamic_chk_timer,5000);
++
++ return _SUCCESS;
++
++netdev_open_error:
++ //padapter->bup = _FALSE;
++ DBG_871X("-ips_netdrv_open - drv_open failure, bup=%d\n", padapter->bup);
++
++ return _FAIL;
++}
++
++
++int rtw_ips_pwr_up(_adapter *padapter)
++{
++ int result;
++ u32 start_time = rtw_get_current_time();
++ DBG_871X("===> rtw_ips_pwr_up..............\n");
++ rtw_reset_drv_sw(padapter);
++
++ result = ips_netdrv_open(padapter);
++
++ rtw_led_control(padapter, LED_CTL_NO_LINK);
++
++ DBG_871X("<=== rtw_ips_pwr_up.............. in %dms\n", rtw_get_passing_time_ms(start_time));
++ return result;
++
++}
++
++void rtw_ips_pwr_down(_adapter *padapter)
++{
++ u32 start_time = rtw_get_current_time();
++ DBG_871X("===> rtw_ips_pwr_down...................\n");
++
++ padapter->bCardDisableWOHSM = _TRUE;
++ padapter->net_closed = _TRUE;
++
++ rtw_led_control(padapter, LED_CTL_POWER_OFF);
++
++ rtw_ips_dev_unload(padapter);
++ padapter->bCardDisableWOHSM = _FALSE;
++ DBG_871X("<=== rtw_ips_pwr_down..................... in %dms\n", rtw_get_passing_time_ms(start_time));
++}
++#endif
++void rtw_ips_dev_unload(_adapter *padapter)
++{
++ struct net_device *pnetdev= (struct net_device*)padapter->pnetdev;
++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
++ DBG_871X("====> %s...\n",__FUNCTION__);
++
++ rtw_hal_set_hwreg(padapter, HW_VAR_FIFO_CLEARN_UP, 0);
++
++ if(padapter->intf_stop)
++ {
++ padapter->intf_stop(padapter);
++ }
++
++ //s5.
++ if(padapter->bSurpriseRemoved == _FALSE)
++ {
++ rtw_hal_deinit(padapter);
++ }
++
++}
++
++int pm_netdev_open(struct net_device *pnetdev,u8 bnormal)
++{
++ int status;
++ if(bnormal)
++ status = netdev_open(pnetdev);
++#ifdef CONFIG_IPS
++ else
++ status = (_SUCCESS == ips_netdrv_open((_adapter *)rtw_netdev_priv(pnetdev)))?(0):(-1);
++#endif
++
++ return status;
++}
++
++static int netdev_close(struct net_device *pnetdev)
++{
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev);
++
++ RT_TRACE(_module_os_intfs_c_,_drv_info_,("+871x_drv - drv_close\n"));
++
++ if(padapter->pwrctrlpriv.bInternalAutoSuspend == _TRUE)
++ {
++ //rtw_pwr_wakeup(padapter);
++ if(padapter->pwrctrlpriv.rf_pwrstate == rf_off)
++ padapter->pwrctrlpriv.ps_flag = _TRUE;
++ }
++ padapter->net_closed = _TRUE;
++
++/* if(!padapter->hw_init_completed)
++ {
++ DBG_871X("(1)871x_drv - drv_close, bup=%d, hw_init_completed=%d\n", padapter->bup, padapter->hw_init_completed);
++
++ padapter->bDriverStopped = _TRUE;
++
++ rtw_dev_unload(padapter);
++ }
++ else*/
++ if(padapter->pwrctrlpriv.rf_pwrstate == rf_on){
++ DBG_871X("(2)871x_drv - drv_close, bup=%d, hw_init_completed=%d\n", padapter->bup, padapter->hw_init_completed);
++
++ //s1.
++ if(pnetdev)
++ {
++ if (!rtw_netif_queue_stopped(pnetdev))
++ rtw_netif_stop_queue(pnetdev);
++ }
++
++#ifndef CONFIG_ANDROID
++ //s2.
++ LeaveAllPowerSaveMode(padapter);
++ rtw_disassoc_cmd(padapter, 500, _FALSE);
++ //s2-2. indicate disconnect to os
++ rtw_indicate_disconnect(padapter);
++ //s2-3.
++ rtw_free_assoc_resources(padapter, 1);
++ //s2-4.
++ rtw_free_network_queue(padapter,_TRUE);
++#endif
++ // Close LED
++ rtw_led_control(padapter, LED_CTL_POWER_OFF);
++ }
++
++#ifdef CONFIG_BR_EXT
++ //if (OPMODE & (WIFI_STATION_STATE | WIFI_ADHOC_STATE))
++ {
++ //void nat25_db_cleanup(_adapter *priv);
++ nat25_db_cleanup(padapter);
++ }
++#endif // CONFIG_BR_EXT
++
++#ifdef CONFIG_P2P
++#ifdef CONFIG_IOCTL_CFG80211
++ if( padapter->wdinfo.driver_interface == DRIVER_CFG80211 )
++ {
++ if(wdev_to_priv(padapter->rtw_wdev)->p2p_enabled == _TRUE)
++ wdev_to_priv(padapter->rtw_wdev)->p2p_enabled = _FALSE;
++ }
++#endif //CONFIG_IOCTL_CFG80211
++ rtw_p2p_enable(padapter, P2P_ROLE_DISABLE);
++#endif //CONFIG_P2P
++
++#ifdef CONFIG_IOCTL_CFG80211
++ rtw_scan_abort(padapter);
++ wdev_to_priv(padapter->rtw_wdev)->bandroid_scan = _FALSE;
++ padapter->rtw_wdev->iftype = NL80211_IFTYPE_MONITOR; //set this at the end
++#endif //CONFIG_IOCTL_CFG80211
++
++ RT_TRACE(_module_os_intfs_c_,_drv_info_,("-871x_drv - drv_close\n"));
++ DBG_871X("-871x_drv - drv_close, bup=%d\n", padapter->bup);
++
++ return 0;
++}
++
++void rtw_ndev_destructor(struct net_device *ndev)
++{
++ DBG_871X(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev));
++
++#ifdef CONFIG_IOCTL_CFG80211
++ if (ndev->ieee80211_ptr)
++ rtw_mfree((u8 *)ndev->ieee80211_ptr, sizeof(struct wireless_dev));
++#endif
++ free_netdev(ndev);
++}
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/os_dep/linux/pci_intf.c linux-xbian-rpi/drivers/net/wireless/rtl8192cu/os_dep/linux/pci_intf.c
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/os_dep/linux/pci_intf.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/os_dep/linux/pci_intf.c 2015-07-28 01:20:58.433199136 +0200
+@@ -0,0 +1,1996 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#define _HCI_INTF_C_
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++#include <recv_osdep.h>
++#include <xmit_osdep.h>
++#include <hal_intf.h>
++#include <rtw_version.h>
++
++#ifndef CONFIG_PCI_HCI
++
++#error "CONFIG_PCI_HCI shall be on!\n"
++
++#endif
++
++#include <pci_ops.h>
++#include <pci_osintf.h>
++#include <pci_hal.h>
++
++#if defined (PLATFORM_LINUX) && defined (PLATFORM_WINDOWS)
++
++#error "Shall be Linux or Windows, but not both!\n"
++
++#endif
++
++#ifdef CONFIG_80211N_HT
++extern int rtw_ht_enable;
++extern int rtw_cbw40_enable;
++extern int rtw_ampdu_enable;//for enable tx_ampdu
++#endif
++
++#ifdef CONFIG_PM
++extern int pm_netdev_open(struct net_device *pnetdev);
++static int rtw_suspend(struct pci_dev *pdev, pm_message_t state);
++static int rtw_resume(struct pci_dev *pdev);
++#endif
++
++
++static int rtw_drv_init(struct pci_dev *pdev, const struct pci_device_id *pdid);
++static void rtw_dev_remove(struct pci_dev *pdev);
++
++static struct specific_device_id specific_device_id_tbl[] = {
++ {.idVendor=0x0b05, .idProduct=0x1791, .flags=SPEC_DEV_ID_DISABLE_HT},
++ {.idVendor=0x13D3, .idProduct=0x3311, .flags=SPEC_DEV_ID_DISABLE_HT},
++ {}
++};
++
++struct pci_device_id rtw_pci_id_tbl[] = {
++#ifdef CONFIG_RTL8192C
++ {PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0x8191)},
++ {PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0x8178)},
++ {PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0x8177)},
++ {PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0x8176)},
++#endif
++#ifdef CONFIG_RTL8192D
++ {PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0x8193)},
++ {PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0x002B)},
++#endif
++ {},
++};
++
++struct pci_drv_priv {
++ struct pci_driver rtw_pci_drv;
++ int drv_registered;
++};
++
++
++static struct pci_drv_priv pci_drvpriv = {
++ .rtw_pci_drv.name = (char*)DRV_NAME,
++ .rtw_pci_drv.probe = rtw_drv_init,
++ .rtw_pci_drv.remove = rtw_dev_remove,
++ .rtw_pci_drv.id_table = rtw_pci_id_tbl,
++#ifdef CONFIG_PM
++ .rtw_pci_drv.suspend = rtw_suspend,
++ .rtw_pci_drv.resume = rtw_resume,
++#else
++ .rtw_pci_drv.suspend = NULL,
++ .rtw_pci_drv.resume = NULL,
++#endif
++};
++
++
++MODULE_DEVICE_TABLE(pci, rtw_pci_id_tbl);
++
++
++static u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = {
++ INTEL_VENDOR_ID,
++ ATI_VENDOR_ID,
++ AMD_VENDOR_ID,
++ SIS_VENDOR_ID
++};
++
++static u8 rtw_pci_platform_switch_device_pci_aspm(_adapter *padapter, u8 value)
++{
++ struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
++ u8 bresult = _SUCCESS;
++ int error;
++
++ value |= 0x40;
++
++ error = pci_write_config_byte(pdvobjpriv->ppcidev, 0x80, value);
++
++ if(error != 0)
++ {
++ bresult = _FALSE;
++ DBG_871X("rtw_pci_platform_switch_device_pci_aspm error (%d)\n",error);
++ }
++
++ return bresult;
++}
++
++//
++// When we set 0x01 to enable clk request. Set 0x0 to disable clk req.
++//
++static u8 rtw_pci_switch_clk_req(_adapter *padapter, u8 value)
++{
++ struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
++ u8 buffer, bresult = _SUCCESS;
++ int error;
++
++ buffer = value;
++
++ if(!padapter->hw_init_completed)
++ return bresult;
++
++ error = pci_write_config_byte(pdvobjpriv->ppcidev, 0x81, value);
++
++ if(error != 0)
++ {
++ bresult = _FALSE;
++ DBG_871X("rtw_pci_switch_clk_req error (%d)\n",error);
++ }
++
++ return bresult;
++}
++
++#if 0
++//Description:
++//Disable RTL8192SE ASPM & Disable Pci Bridge ASPM
++void rtw_pci_disable_aspm(_adapter *padapter)
++{
++ struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
++ struct pci_priv *pcipriv = &(pdvobjpriv->pcipriv);
++ u32 pcicfg_addrport = 0;
++ u8 num4bytes;
++ u8 linkctrl_reg;
++ u16 pcibridge_linkctrlreg, aspmlevel = 0;
++
++ // When there exists anyone's busnum, devnum, and funcnum that are set to 0xff,
++ // we do not execute any action and return.
++ // if it is not intel bus then don't enable ASPM.
++ if ((pcipriv->busnumber == 0xff
++ && pcipriv->devnumber == 0xff
++ && pcipriv->funcnumber == 0xff)
++ || (pcipriv->pcibridge_busnum == 0xff
++ && pcipriv->pcibridge_devnum == 0xff
++ && pcipriv->pcibridge_funcnum == 0xff))
++ {
++ DBG_871X("PlatformEnableASPM(): Fail to enable ASPM. Cannot find the Bus of PCI(Bridge).\n");
++ return;
++ }
++
++ if (pcipriv->pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
++ DBG_871X("%s(): Disable ASPM. Recognize the Bus of PCI(Bridge) as UNKNOWN.\n", __func__);
++ }
++
++ if (pwrpriv->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
++ RT_CLEAR_PS_LEVEL(pwrpriv, RT_RF_OFF_LEVL_CLK_REQ);
++ rtw_pci_switch_clk_req(padapter, 0x0);
++ }
++
++ {
++ // Suggested by SD1 for promising device will in L0 state after an I/O.
++ u8 tmp_u1b;
++
++ pci_read_config_byte(pdvobjpriv->ppcidev, 0x80, &tmp_u1b);
++ }
++
++ // Retrieve original configuration settings.
++ linkctrl_reg = pcipriv->linkctrl_reg;
++ pcibridge_linkctrlreg = pcipriv->pcibridge_linkctrlreg;
++
++ // Set corresponding value.
++ aspmlevel |= BIT(0) | BIT(1);
++ linkctrl_reg &= ~aspmlevel;
++ pcibridge_linkctrlreg &= ~(BIT(0) | BIT(1));
++
++ rtw_pci_platform_switch_device_pci_aspm(padapter, linkctrl_reg);
++ rtw_udelay_os(50);
++
++ //When there exists anyone's busnum, devnum, and funcnum that are set to 0xff,
++ // we do not execute any action and return.
++ if ((pcipriv->busnumber == 0xff &&
++ pcipriv->devnumber == 0xff &&
++ pcipriv->funcnumber == 0xff) ||
++ (pcipriv->pcibridge_busnum == 0xff &&
++ pcipriv->pcibridge_devnum == 0xff
++ && pcipriv->pcibridge_funcnum == 0xff))
++ {
++ //Do Nothing!!
++ }
++ else
++ {
++ //4 //Disable Pci Bridge ASPM
++ pcicfg_addrport = (pcipriv->pcibridge_busnum << 16) |
++ (pcipriv->pcibridge_devnum << 11) |
++ (pcipriv->pcibridge_funcnum << 8) | (1 << 31);
++ num4bytes = (pcipriv->pcibridge_pciehdr_offset + 0x10) / 4;
++
++ // set up address port at 0xCF8 offset field= 0 (dev|vend)
++ NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport + (num4bytes << 2));
++
++ // now grab data port with device|vendor 4 byte dword
++ NdisRawWritePortUchar(PCI_CONF_DATA, pcibridge_linkctrlreg);
++
++ DBG_871X("rtw_pci_disable_aspm():PciBridge busnumber[%x], DevNumbe[%x], funcnumber[%x], Write reg[%x] = %x\n",
++ pcipriv->pcibridge_busnum, pcipriv->pcibridge_devnum,
++ pcipriv->pcibridge_funcnum,
++ (pcipriv->pcibridge_pciehdr_offset+0x10), pcibridge_linkctrlreg);
++
++ rtw_udelay_os(50);
++ }
++}
++
++//[ASPM]
++//Description:
++// Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for power saving
++// We should follow the sequence to enable RTL8192SE first then enable Pci Bridge ASPM
++// or the system will show bluescreen.
++void rtw_pci_enable_aspm(_adapter *padapter)
++{
++ struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
++ struct pci_priv *pcipriv = &(pdvobjpriv->pcipriv);
++ u16 aspmlevel = 0;
++ u32 pcicfg_addrport = 0;
++ u8 num4bytes;
++ u8 u_pcibridge_aspmsetting = 0;
++ u8 u_device_aspmsetting = 0;
++
++ // When there exists anyone's busnum, devnum, and funcnum that are set to 0xff,
++ // we do not execute any action and return.
++ // if it is not intel bus then don't enable ASPM.
++
++ if ((pcipriv->busnumber == 0xff
++ && pcipriv->devnumber == 0xff
++ && pcipriv->funcnumber == 0xff)
++ || (pcipriv->pcibridge_busnum == 0xff
++ && pcipriv->pcibridge_devnum == 0xff
++ && pcipriv->pcibridge_funcnum == 0xff))
++ {
++ DBG_871X("PlatformEnableASPM(): Fail to enable ASPM. Cannot find the Bus of PCI(Bridge).\n");
++ return;
++ }
++
++ //4 Enable Pci Bridge ASPM
++ pcicfg_addrport = (pcipriv->pcibridge_busnum << 16)
++ | (pcipriv->pcibridge_devnum << 11)
++ | (pcipriv->pcibridge_funcnum << 8) | (1 << 31);
++ num4bytes = (pcipriv->pcibridge_pciehdr_offset + 0x10) / 4;
++ // set up address port at 0xCF8 offset field= 0 (dev|vend)
++ NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport + (num4bytes << 2));
++ // now grab data port with device|vendor 4 byte dword
++
++ u_pcibridge_aspmsetting = pcipriv->pcibridge_linkctrlreg | pdvobjpriv->const_hostpci_aspm_setting;
++
++ if (pcipriv->pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL ||
++ pcipriv->pcibridge_vendor == PCI_BRIDGE_VENDOR_SIS)
++ u_pcibridge_aspmsetting &= ~BIT(0);
++
++ NdisRawWritePortUchar(PCI_CONF_DATA, u_pcibridge_aspmsetting);
++
++ DBG_871X("PlatformEnableASPM():PciBridge busnumber[%x], DevNumbe[%x], funcnumber[%x], Write reg[%x] = %x\n",
++ pcipriv->pcibridge_busnum,
++ pcipriv->pcibridge_devnum,
++ pcipriv->pcibridge_funcnum,
++ (pcipriv->pcibridge_pciehdr_offset+0x10),
++ u_pcibridge_aspmsetting);
++
++ rtw_udelay_os(50);
++
++ // Get ASPM level (with/without Clock Req)
++ aspmlevel |= pdvobjpriv->const_devicepci_aspm_setting;
++ u_device_aspmsetting = pcipriv->linkctrl_reg;
++ u_device_aspmsetting |= aspmlevel;
++
++ rtw_pci_platform_switch_device_pci_aspm(padapter, u_device_aspmsetting); //(priv->linkctrl_reg | ASPMLevel));
++
++ if (pwrpriv->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
++ rtw_pci_switch_clk_req(padapter, (pwrpriv->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0);
++ RT_SET_PS_LEVEL(pwrpriv, RT_RF_OFF_LEVL_CLK_REQ);
++ }
++
++ rtw_udelay_os(50);
++}
++
++//
++//Description:
++//To get link control field by searching from PCIe capability lists.
++//
++static u8
++rtw_get_link_control_field(_adapter *padapter, u8 busnum, u8 devnum,
++ u8 funcnum)
++{
++ struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
++ struct pci_priv *pcipriv = &(pdvobjpriv->pcipriv);
++ struct rt_pci_capabilities_header capability_hdr;
++ u8 capability_offset, num4bytes;
++ u32 pcicfg_addrport = 0;
++ u8 linkctrl_reg;
++ u8 status = _FALSE;
++
++ //If busnum, devnum, funcnum are set to 0xff.
++ if (busnum == 0xff && devnum == 0xff && funcnum == 0xff) {
++ DBG_871X("GetLinkControlField(): Fail to find PCIe Capability\n");
++ return _FALSE;
++ }
++
++ pcicfg_addrport = (busnum << 16) | (devnum << 11) | (funcnum << 8) | (1 << 31);
++
++ //2PCIeCap
++
++ // The device supports capability lists. Find the capabilities.
++ num4bytes = 0x34 / 4;
++ //get capability_offset
++ // set up address port at 0xCF8 offset field= 0 (dev|vend)
++ NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport + (num4bytes << 2));
++ // now grab data port with device|vendor 4 byte dword
++ NdisRawReadPortUchar(PCI_CONF_DATA, &capability_offset);
++
++ // Loop through the capabilities in search of the power management capability.
++ // The list is NULL-terminated, so the last offset will always be zero.
++
++ while (capability_offset != 0) {
++ // First find the number of 4 Byte.
++ num4bytes = capability_offset / 4;
++
++ // Read the header of the capability at this offset. If the retrieved capability is not
++ // the power management capability that we are looking for, follow the link to the
++ // next capability and continue looping.
++
++ //4 get capability_hdr
++ // set up address port at 0xCF8 offset field= 0 (dev|vend)
++ NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport + (num4bytes << 2));
++ // now grab data port with device|vendor 4 byte dword
++ NdisRawReadPortUshort(PCI_CONF_DATA, (u16 *) & capability_hdr);
++
++ // Found the PCI express capability
++ if (capability_hdr.capability_id == PCI_CAPABILITY_ID_PCI_EXPRESS)
++ {
++ break;
++ }
++ else
++ {
++ // This is some other capability. Keep looking for the PCI express capability.
++ capability_offset = capability_hdr.next;
++ }
++ }
++
++ if (capability_hdr.capability_id == PCI_CAPABILITY_ID_PCI_EXPRESS) //
++ {
++ num4bytes = (capability_offset + 0x10) / 4;
++
++ //4 Read Link Control Register
++ // set up address port at 0xCF8 offset field= 0 (dev|vend)
++ NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport + (num4bytes << 2));
++ // now grab data port with device|vendor 4 byte dword
++ NdisRawReadPortUchar(PCI_CONF_DATA, &linkctrl_reg);
++
++ pcipriv->pcibridge_pciehdr_offset = capability_offset;
++ pcipriv->pcibridge_linkctrlreg = linkctrl_reg;
++
++ status = _TRUE;
++ }
++ else
++ {
++ // We didn't find a PCIe capability.
++ DBG_871X("GetLinkControlField(): Cannot Find PCIe Capability\n");
++ }
++
++ return status;
++}
++
++//
++//Description:
++//To get PCI bus infomation and return busnum, devnum, and funcnum about
++//the bus(bridge) which the device binds.
++//
++static u8
++rtw_get_pci_bus_info(_adapter *padapter,
++ u16 vendorid,
++ u16 deviceid,
++ u8 irql, u8 basecode, u8 subclass, u8 filed19val,
++ u8 * busnum, u8 * devnum, u8 * funcnum)
++{
++ struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
++ struct pci_dev *pdev = pdvobjpriv->ppcidev;
++ u8 busnum_idx, devicenum_idx, functionnum_idx;
++ u32 pcicfg_addrport = 0;
++ u32 dev_venid = 0, classcode, field19, headertype;
++ u16 venId, devId;
++ u8 basec, subc, irqline;
++ u16 regoffset;
++ u8 b_singlefunc = _FALSE;
++ u8 b_bridgechk = _FALSE;
++
++ *busnum = 0xFF;
++ *devnum = 0xFF;
++ *funcnum = 0xFF;
++
++ //DBG_871X("==============>vendorid:%x,deviceid:%x,irql:%x\n", vendorid,deviceid,irql);
++ if ((basecode == PCI_CLASS_BRIDGE_DEV) &&
++ (subclass == PCI_SUBCLASS_BR_PCI_TO_PCI)
++ && (filed19val == U1DONTCARE))
++ b_bridgechk = _TRUE;
++
++ // perform a complete pci bus scan operation
++ for (busnum_idx = 0; busnum_idx < PCI_MAX_BRIDGE_NUMBER; busnum_idx++) //255
++ {
++ for (devicenum_idx = 0; devicenum_idx < PCI_MAX_DEVICES; devicenum_idx++) //32
++ {
++ b_singlefunc = _FALSE;
++ for (functionnum_idx = 0; functionnum_idx < PCI_MAX_FUNCTION; functionnum_idx++) //8
++ {
++ //
++ // <Roger_Notes> We have to skip redundant Bus scan to prevent unexpected system hang
++ // if single function is present in this device.
++ // 2009.02.26.
++ //
++ if (functionnum_idx == 0) {
++ //4 get header type (DWORD #3)
++ pcicfg_addrport = (busnum_idx << 16) | (devicenum_idx << 11) | (functionnum_idx << 8) | (1 << 31);
++ NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport + (3 << 2));
++ NdisRawReadPortUlong(PCI_CONF_DATA, &headertype);
++ headertype = ((headertype >> 16) & 0x0080) >> 7; // address 0x0e[7].
++ if (headertype == 0) //Single function
++ b_singlefunc = _TRUE;
++ }
++ else
++ {//By pass the following scan process.
++ if (b_singlefunc == _TRUE)
++ break;
++ }
++
++ // Set access enable control.
++ pcicfg_addrport = (busnum_idx << 16) | (devicenum_idx << 11) | (functionnum_idx << 8) | (1 << 31);
++
++ //4 // Get vendorid/ deviceid
++ // set up address port at 0xCF8 offset field= 0 (dev|vend)
++ NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport);
++ // now grab data port with device|vendor 4 byte dword
++ NdisRawReadPortUlong(PCI_CONF_DATA, &dev_venid);
++
++ // if data port is full of 1s, no device is present
++ // some broken boards return 0 if a slot is empty:
++ if (dev_venid == 0xFFFFFFFF || dev_venid == 0)
++ continue; //PCI_INVALID_VENDORID
++
++ // 4 // Get irql
++ regoffset = 0x3C;
++ pcicfg_addrport = (busnum_idx << 16) | (devicenum_idx << 11) | (functionnum_idx << 8) | (1 << 31) | (regoffset & 0xFFFFFFFC);
++ NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport);
++ NdisRawReadPortUchar((PCI_CONF_DATA +(regoffset & 0x3)), &irqline);
++
++ venId = (u16) (dev_venid >> 0) & 0xFFFF;
++ devId = (u16) (dev_venid >> 16) & 0xFFFF;
++
++ // Check Vendor ID
++ if (!b_bridgechk && (venId != vendorid) && (vendorid != U2DONTCARE))
++ continue;
++
++ // Check Device ID
++ if (!b_bridgechk && (devId != deviceid) && (deviceid != U2DONTCARE))
++ continue;
++
++ // Check irql
++ if (!b_bridgechk && (irqline != irql) && (irql != U1DONTCARE))
++ continue;
++
++ //4 get Class Code
++ pcicfg_addrport = (busnum_idx << 16) | (devicenum_idx << 11) | (functionnum_idx << 8) | (1 << 31);
++ NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport + (2 << 2));
++ NdisRawReadPortUlong(PCI_CONF_DATA, &classcode);
++ classcode = classcode >> 8;
++
++ basec = (u8) (classcode >> 16) & 0xFF;
++ subc = (u8) (classcode >> 8) & 0xFF;
++ if (b_bridgechk && (venId != vendorid) && (basec == basecode) && (subc == subclass))
++ return _TRUE;
++
++ // Check Vendor ID
++ if (b_bridgechk && (venId != vendorid) && (vendorid != U2DONTCARE))
++ continue;
++
++ // Check Device ID
++ if (b_bridgechk && (devId != deviceid) && (deviceid != U2DONTCARE))
++ continue;
++
++ // Check irql
++ if (b_bridgechk && (irqline != irql) && (irql != U1DONTCARE))
++ continue;
++
++ //4 get field 0x19 value (DWORD #6)
++ NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport + (6 << 2));
++ NdisRawReadPortUlong(PCI_CONF_DATA, &field19);
++ field19 = (field19 >> 8) & 0xFF;
++
++ //4 Matching Class Code and filed19.
++ if ((basec == basecode) && (subc == subclass) && ((field19 == filed19val) || (filed19val == U1DONTCARE))) {
++ *busnum = busnum_idx;
++ *devnum = devicenum_idx;
++ *funcnum = functionnum_idx;
++
++ DBG_871X("GetPciBusInfo(): Find Device(%X:%X) bus=%d dev=%d, func=%d\n",
++ vendorid, deviceid, busnum_idx, devicenum_idx, functionnum_idx);
++ return _TRUE;
++ }
++ }
++ }
++ }
++
++ DBG_871X("GetPciBusInfo(): Cannot Find Device(%X:%X:%X)\n", vendorid, deviceid, dev_venid);
++
++ return _FALSE;
++}
++
++static u8
++rtw_get_pci_brideg_info(_adapter *padapter,
++ u8 basecode,
++ u8 subclass,
++ u8 filed19val, u8 * busnum, u8 * devnum,
++ u8 * funcnum, u16 * vendorid, u16 * deviceid)
++{
++ u8 busnum_idx, devicenum_idx, functionnum_idx;
++ u32 pcicfg_addrport = 0;
++ u32 dev_venid, classcode, field19, headertype;
++ u16 venId, devId;
++ u8 basec, subc, irqline;
++ u16 regoffset;
++ u8 b_singlefunc = _FALSE;
++
++ *busnum = 0xFF;
++ *devnum = 0xFF;
++ *funcnum = 0xFF;
++
++ // perform a complete pci bus scan operation
++ for (busnum_idx = 0; busnum_idx < PCI_MAX_BRIDGE_NUMBER; busnum_idx++) //255
++ {
++ for (devicenum_idx = 0; devicenum_idx < PCI_MAX_DEVICES; devicenum_idx++) //32
++ {
++ b_singlefunc = _FALSE;
++ for (functionnum_idx = 0; functionnum_idx < PCI_MAX_FUNCTION; functionnum_idx++) //8
++ {
++ //
++ // <Roger_Notes> We have to skip redundant Bus scan to prevent unexpected system hang
++ // if single function is present in this device.
++ // 2009.02.26.
++ //
++ if (functionnum_idx == 0)
++ {
++ //4 get header type (DWORD #3)
++ pcicfg_addrport = (busnum_idx << 16) | (devicenum_idx << 11) | (functionnum_idx << 8) | (1 << 31);
++ //NdisRawWritePortUlong((ULONG_PTR)PCI_CONF_ADDRESS , pcicfg_addrport + (3 << 2));
++ //NdisRawReadPortUlong((ULONG_PTR)PCI_CONF_DATA, &headertype);
++ NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport + (3 << 2));
++ NdisRawReadPortUlong(PCI_CONF_DATA, &headertype);
++ headertype = ((headertype >> 16) & 0x0080) >> 7; // address 0x0e[7].
++ if (headertype == 0) //Single function
++ b_singlefunc = _TRUE;
++ }
++ else
++ {//By pass the following scan process.
++ if (b_singlefunc == _TRUE)
++ break;
++ }
++
++ pcicfg_addrport = (busnum_idx << 16) | (devicenum_idx << 11) | (functionnum_idx << 8) | (1 << 31);
++
++ //4 // Get vendorid/ deviceid
++ // set up address port at 0xCF8 offset field= 0 (dev|vend)
++ NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport);
++ // now grab data port with device|vendor 4 byte dword
++ NdisRawReadPortUlong(PCI_CONF_DATA, &dev_venid);
++
++ //4 Get irql
++ regoffset = 0x3C;
++ pcicfg_addrport = (busnum_idx << 16) | (devicenum_idx << 11) | (functionnum_idx << 8) | (1 << 31) | (regoffset & 0xFFFFFFFC);
++ NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport);
++ NdisRawReadPortUchar((PCI_CONF_DATA + (regoffset & 0x3)), &irqline);
++
++ venId = (u16) (dev_venid >> 0) & 0xFFFF;
++ devId = (u16) (dev_venid >> 16) & 0xFFFF;
++
++ //4 get Class Code
++ pcicfg_addrport = (busnum_idx << 16) | (devicenum_idx << 11) | (functionnum_idx << 8) | (1 << 31);
++ NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport + (2 << 2));
++ NdisRawReadPortUlong(PCI_CONF_DATA, &classcode);
++ classcode = classcode >> 8;
++
++ basec = (u8) (classcode >> 16) & 0xFF;
++ subc = (u8) (classcode >> 8) & 0xFF;
++
++ //4 get field 0x19 value (DWORD #6)
++ NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport + (6 << 2));
++ NdisRawReadPortUlong(PCI_CONF_DATA, &field19);
++ field19 = (field19 >> 8) & 0xFF;
++
++ //4 Matching Class Code and filed19.
++ if ((basec == basecode) && (subc == subclass) && ((field19 == filed19val) || (filed19val == U1DONTCARE))) {
++ *busnum = busnum_idx;
++ *devnum = devicenum_idx;
++ *funcnum = functionnum_idx;
++ *vendorid = venId;
++ *deviceid = devId;
++
++ DBG_871X("GetPciBridegInfo : Find Device(%X:%X) bus=%d dev=%d, func=%d\n",
++ venId, devId, busnum_idx, devicenum_idx, functionnum_idx);
++
++ return _TRUE;
++ }
++ }
++ }
++ }
++
++ DBG_871X("GetPciBridegInfo(): Cannot Find PciBridge for Device\n");
++
++ return _FALSE;
++} // end of GetPciBridegInfo
++
++//
++//Description:
++//To find specific bridge information.
++//
++static void rtw_find_bridge_info(_adapter *padapter)
++{
++ struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
++ struct pci_priv *pcipriv = &(pdvobjpriv->pcipriv);
++ u8 pcibridge_busnum = 0xff;
++ u8 pcibridge_devnum = 0xff;
++ u8 pcibridge_funcnum = 0xff;
++ u16 pcibridge_vendorid = 0xff;
++ u16 pcibridge_deviceid = 0xff;
++ u8 tmp = 0;
++
++ rtw_get_pci_brideg_info(padapter,
++ PCI_CLASS_BRIDGE_DEV,
++ PCI_SUBCLASS_BR_PCI_TO_PCI,
++ pcipriv->busnumber,
++ &pcibridge_busnum,
++ &pcibridge_devnum, &pcibridge_funcnum,
++ &pcibridge_vendorid, &pcibridge_deviceid);
++
++ // match the array of vendor id and regonize which chipset is used.
++ pcipriv->pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
++
++ for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) {
++ if (pcibridge_vendorid == pcibridge_vendors[tmp]) {
++ pcipriv->pcibridge_vendor = tmp;
++ DBG_871X("Pci Bridge Vendor is found index: %d\n", tmp);
++ break;
++ }
++ }
++ DBG_871X("Pci Bridge Vendor is %x\n", pcibridge_vendors[tmp]);
++
++ // Update corresponding PCI bus info.
++ pcipriv->pcibridge_busnum = pcibridge_busnum;
++ pcipriv->pcibridge_devnum = pcibridge_devnum;
++ pcipriv->pcibridge_funcnum = pcibridge_funcnum;
++ pcipriv->pcibridge_vendorid = pcibridge_vendorid;
++ pcipriv->pcibridge_deviceid = pcibridge_deviceid;
++
++}
++
++static u8
++rtw_get_amd_l1_patch(_adapter *padapter, u8 busnum, u8 devnum,
++ u8 funcnum)
++{
++ u8 status = _FALSE;
++ u8 offset_e0;
++ unsigned offset_e4;
++ u32 pcicfg_addrport = 0;
++
++ pcicfg_addrport = (busnum << 16) | (devnum << 11) | (funcnum << 8) | (1 << 31);
++
++ NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport + 0xE0);
++ NdisRawWritePortUchar(PCI_CONF_DATA, 0xA0);
++
++ NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport + 0xE0);
++ NdisRawReadPortUchar(PCI_CONF_DATA, &offset_e0);
++
++ if (offset_e0 == 0xA0)
++ {
++ NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport + 0xE4);
++ NdisRawReadPortUlong(PCI_CONF_DATA, &offset_e4);
++ //DbgPrint("Offset E4 %x\n", offset_e4);
++ if (offset_e4 & BIT(23))
++ status = _TRUE;
++ }
++
++ return status;
++}
++#else
++/*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/
++void rtw_pci_disable_aspm(_adapter *padapter)
++{
++ struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
++ struct pci_dev *pdev = pdvobjpriv->ppcidev;
++ struct pci_dev *bridge_pdev = pdev->bus->self;
++ struct pci_priv *pcipriv = &(pdvobjpriv->pcipriv);
++ u8 linkctrl_reg;
++ u16 pcibridge_linkctrlreg;
++ u16 aspmlevel = 0;
++
++ // We do not diable/enable ASPM by driver, in the future, the BIOS will enable host and NIC ASPM.
++ // Advertised by SD1 victorh. Added by tynli. 2009.11.23.
++ if(pdvobjpriv->const_pci_aspm == 0)
++ return;
++
++ if(!padapter->hw_init_completed)
++ return;
++
++ if (pcipriv->pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
++ RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("%s(): PCI(Bridge) UNKNOWN.\n", __FUNCTION__));
++ return;
++ }
++
++ linkctrl_reg = pcipriv->linkctrl_reg;
++ pcibridge_linkctrlreg = pcipriv->pcibridge_linkctrlreg;
++
++ // Set corresponding value.
++ aspmlevel |= BIT(0) | BIT(1);
++ linkctrl_reg &=~aspmlevel;
++ pcibridge_linkctrlreg &=~aspmlevel;
++
++ if (pwrpriv->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
++ RT_CLEAR_PS_LEVEL(pwrpriv, RT_RF_OFF_LEVL_CLK_REQ);
++ rtw_pci_switch_clk_req(padapter, 0x0);
++ }
++
++ {
++ /*for promising device will in L0 state after an I/O.*/
++ u8 tmp_u1b;
++ pci_read_config_byte(pdev, 0x80, &tmp_u1b);
++ }
++
++ rtw_pci_platform_switch_device_pci_aspm(padapter, linkctrl_reg);
++ rtw_udelay_os(50);
++
++ //When there exists anyone's BusNum, DevNum, and FuncNum that are set to 0xff,
++ // we do not execute any action and return. Added by tynli.
++ if( (pcipriv->busnumber == 0xff && pcipriv->devnumber == 0xff && pcipriv->funcnumber == 0xff) ||
++ (pcipriv->pcibridge_busnum == 0xff && pcipriv->pcibridge_devnum == 0xff && pcipriv->pcibridge_funcnum == 0xff) )
++ {
++ // Do Nothing!!
++ }
++ else
++ {
++ /*Disable Pci Bridge ASPM*/
++ //NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport + (num4bytes << 2));
++ //NdisRawWritePortUchar(PCI_CONF_DATA, pcibridge_linkctrlreg);
++ pci_write_config_byte(bridge_pdev, pcipriv->pcibridge_pciehdr_offset + 0x10, pcibridge_linkctrlreg);
++
++ DBG_871X("rtw_pci_disable_aspm():PciBridge busnumber[%x], DevNumbe[%x], funcnumber[%x], Write reg[%x] = %x\n",
++ pcipriv->pcibridge_busnum, pcipriv->pcibridge_devnum,
++ pcipriv->pcibridge_funcnum,
++ (pcipriv->pcibridge_pciehdr_offset+0x10), pcibridge_linkctrlreg);
++
++ rtw_udelay_os(50);
++ }
++
++}
++
++/*Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for
++power saving We should follow the sequence to enable
++RTL8192SE first then enable Pci Bridge ASPM
++or the system will show bluescreen.*/
++void rtw_pci_enable_aspm(_adapter *padapter)
++{
++ struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
++ struct pci_dev *pdev = pdvobjpriv->ppcidev;
++ struct pci_dev *bridge_pdev = pdev->bus->self;
++ struct pci_priv *pcipriv = &(pdvobjpriv->pcipriv);
++ u16 aspmlevel = 0;
++ u8 u_pcibridge_aspmsetting = 0;
++ u8 u_device_aspmsetting = 0;
++ u32 u_device_aspmsupportsetting = 0;
++
++ // We do not diable/enable ASPM by driver, in the future, the BIOS will enable host and NIC ASPM.
++ // Advertised by SD1 victorh. Added by tynli. 2009.11.23.
++ if(pdvobjpriv->const_pci_aspm == 0)
++ return;
++
++ //When there exists anyone's BusNum, DevNum, and FuncNum that are set to 0xff,
++ // we do not execute any action and return. Added by tynli.
++ if( (pcipriv->busnumber == 0xff && pcipriv->devnumber == 0xff && pcipriv->funcnumber == 0xff) ||
++ (pcipriv->pcibridge_busnum == 0xff && pcipriv->pcibridge_devnum == 0xff && pcipriv->pcibridge_funcnum == 0xff) )
++ {
++ DBG_871X("rtw_pci_enable_aspm(): Fail to enable ASPM. Cannot find the Bus of PCI(Bridge).\n");
++ return;
++ }
++
++//Get Bridge ASPM Support
++//not to enable bridge aspm if bridge does not support
++//Added by sherry 20100803
++ if (IS_HARDWARE_TYPE_8192DE(padapter))
++ {
++ //PciCfgAddrPort = (pcipriv->pcibridge_busnum << 16)|(pcipriv->pcibridge_devnum<< 11)|(pcipriv->pcibridge_funcnum << 8)|(1 << 31);
++ //Num4Bytes = (pcipriv->pcibridge_pciehdr_offset+0x0C)/4;
++ //NdisRawWritePortUlong((ULONG_PTR)PCI_CONF_ADDRESS , PciCfgAddrPort+(Num4Bytes << 2));
++ //NdisRawReadPortUlong((ULONG_PTR)PCI_CONF_DATA,&uDeviceASPMSupportSetting);
++ pci_read_config_dword(bridge_pdev, (pcipriv->pcibridge_pciehdr_offset+0x0C), &u_device_aspmsupportsetting);
++ DBG_871X("rtw_pci_enable_aspm(): Bridge ASPM support %x \n",u_device_aspmsupportsetting);
++ if(((u_device_aspmsupportsetting & BIT(11)) != BIT(11)) || ((u_device_aspmsupportsetting & BIT(10)) != BIT(10)))
++ {
++ if(pdvobjpriv->const_devicepci_aspm_setting == 3)
++ {
++ DBG_871X("rtw_pci_enable_aspm(): Bridge not support L0S or L1\n");
++ return;
++ }
++ else if(pdvobjpriv->const_devicepci_aspm_setting == 2)
++ {
++ if((u_device_aspmsupportsetting & BIT(11)) != BIT(11))
++ {
++ DBG_871X("rtw_pci_enable_aspm(): Bridge not support L1 \n");
++ return;
++ }
++ }
++ else if(pdvobjpriv->const_devicepci_aspm_setting == 1)
++ {
++ if((u_device_aspmsupportsetting & BIT(10)) != BIT(10))
++ {
++ DBG_871X("rtw_pci_enable_aspm(): Bridge not support L0s \n");
++ return;
++ }
++
++ }
++ }
++ else
++ {
++ DBG_871X("rtw_pci_enable_aspm(): Bridge support L0s and L1 \n");
++ }
++ }
++
++
++ /*Enable Pci Bridge ASPM*/
++ //PciCfgAddrPort = (pcipriv->pcibridge_busnum << 16)|(pcipriv->pcibridge_devnum<< 11) |(pcipriv->pcibridge_funcnum << 8)|(1 << 31);
++ //Num4Bytes = (pcipriv->pcibridge_pciehdr_offset+0x10)/4;
++ // set up address port at 0xCF8 offset field= 0 (dev|vend)
++ //NdisRawWritePortUlong(PCI_CONF_ADDRESS, PciCfgAddrPort + (Num4Bytes << 2));
++ // now grab data port with device|vendor 4 byte dword
++
++ u_pcibridge_aspmsetting = pcipriv->pcibridge_linkctrlreg;
++ u_pcibridge_aspmsetting |= pdvobjpriv->const_hostpci_aspm_setting;
++
++ if (pcipriv->pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL ||
++ pcipriv->pcibridge_vendor == PCI_BRIDGE_VENDOR_SIS )
++ u_pcibridge_aspmsetting &= ~BIT(0); // for intel host 42 device 43
++
++ //NdisRawWritePortUchar(PCI_CONF_DATA, u_pcibridge_aspmsetting);
++ pci_write_config_byte(bridge_pdev, (pcipriv->pcibridge_pciehdr_offset+0x10), u_pcibridge_aspmsetting);
++
++ DBG_871X("PlatformEnableASPM():PciBridge busnumber[%x], DevNumbe[%x], funcnumber[%x], Write reg[%x] = %x\n",
++ pcipriv->pcibridge_busnum, pcipriv->pcibridge_devnum, pcipriv->pcibridge_funcnum,
++ (pcipriv->pcibridge_pciehdr_offset+0x10),
++ u_pcibridge_aspmsetting);
++
++ rtw_udelay_os(50);
++
++ /*Get ASPM level (with/without Clock Req)*/
++ aspmlevel |= pdvobjpriv->const_devicepci_aspm_setting;
++ u_device_aspmsetting = pcipriv->linkctrl_reg;
++ u_device_aspmsetting |= aspmlevel; // device 43
++
++ rtw_pci_platform_switch_device_pci_aspm(padapter, u_device_aspmsetting);
++
++ if (pwrpriv->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
++ rtw_pci_switch_clk_req(padapter, (pwrpriv->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0);
++ RT_SET_PS_LEVEL(pwrpriv, RT_RF_OFF_LEVL_CLK_REQ);
++ }
++
++ rtw_udelay_os(50);
++}
++
++static u8 rtw_pci_get_amd_l1_patch(struct dvobj_priv *dvobj)
++{
++ struct pci_dev *pdev = dvobj->ppcidev;
++ struct pci_dev *bridge_pdev = pdev->bus->self;
++ u8 status = _FALSE;
++ u8 offset_e0;
++ u32 offset_e4;
++
++ //NdisRawWritePortUlong(PCI_CONF_ADDRESS,pcicfg_addrport + 0xE0);
++ //NdisRawWritePortUchar(PCI_CONF_DATA, 0xA0);
++ pci_write_config_byte(bridge_pdev, 0xE0, 0xA0);
++
++ //NdisRawWritePortUlong(PCI_CONF_ADDRESS,pcicfg_addrport + 0xE0);
++ //NdisRawReadPortUchar(PCI_CONF_DATA, &offset_e0);
++ pci_read_config_byte(bridge_pdev, 0xE0, &offset_e0);
++
++ if (offset_e0 == 0xA0) {
++ //NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport + 0xE4);
++ //NdisRawReadPortUlong(PCI_CONF_DATA, &offset_e4);
++ pci_read_config_dword(bridge_pdev, 0xE4, &offset_e4);
++ if (offset_e4 & BIT(23))
++ status = _TRUE;
++ }
++
++ return status;
++}
++
++static void rtw_pci_get_linkcontrol_field(struct dvobj_priv *dvobj)
++{
++ struct pci_priv *pcipriv = &(dvobj->pcipriv);
++ struct pci_dev *pdev = dvobj->ppcidev;
++ struct pci_dev *bridge_pdev = pdev->bus->self;
++ u8 capabilityoffset = pcipriv->pcibridge_pciehdr_offset;
++ u8 linkctrl_reg;
++
++ /*Read Link Control Register*/
++ pci_read_config_byte(bridge_pdev, capabilityoffset + PCI_EXP_LNKCTL, &linkctrl_reg);
++
++ pcipriv->pcibridge_linkctrlreg = linkctrl_reg;
++}
++#endif
++
++static void rtw_pci_parse_configuration(struct dvobj_priv *dvobj)
++{
++ struct pci_dev *pdev = dvobj->ppcidev;
++ struct pci_priv *pcipriv = &(dvobj->pcipriv);
++ u8 tmp;
++ int pos;
++ u8 linkctrl_reg;
++
++ //Link Control Register
++ pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
++ pci_read_config_byte(pdev, pos + PCI_EXP_LNKCTL, &linkctrl_reg);
++ pcipriv->linkctrl_reg = linkctrl_reg;
++
++ //DBG_871X("Link Control Register = %x\n", pcipriv->linkctrl_reg);
++
++ pci_read_config_byte(pdev, 0x98, &tmp);
++ tmp |= BIT(4);
++ pci_write_config_byte(pdev, 0x98, tmp);
++
++ //tmp = 0x17;
++ //pci_write_config_byte(pdev, 0x70f, tmp);
++}
++
++//
++// Update PCI dependent default settings.
++//
++static void rtw_pci_update_default_setting(_adapter *padapter)
++{
++ struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
++ struct pci_priv *pcipriv = &(pdvobjpriv->pcipriv);
++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
++
++ //reset pPSC->reg_rfps_level & priv->b_support_aspm
++ pwrpriv->reg_rfps_level = 0;
++ pwrpriv->b_support_aspm = 0;
++
++ // Dynamic Mechanism,
++ //rtw_hal_set_def_var(pAdapter, HAL_DEF_INIT_GAIN, &(pDevice->InitGainState));
++
++ // Update PCI ASPM setting
++ pwrpriv->const_amdpci_aspm = pdvobjpriv->const_amdpci_aspm;
++ switch (pdvobjpriv->const_pci_aspm) {
++ case 0: // No ASPM
++ break;
++
++ case 1: // ASPM dynamically enabled/disable.
++ pwrpriv->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM;
++ break;
++
++ case 2: // ASPM with Clock Req dynamically enabled/disable.
++ pwrpriv->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM | RT_RF_OFF_LEVL_CLK_REQ);
++ break;
++
++ case 3: // Always enable ASPM and Clock Req from initialization to halt.
++ pwrpriv->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM);
++ pwrpriv->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM | RT_RF_OFF_LEVL_CLK_REQ);
++ break;
++
++ case 4: // Always enable ASPM without Clock Req from initialization to halt.
++ pwrpriv->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM | RT_RF_OFF_LEVL_CLK_REQ);
++ pwrpriv->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM;
++ break;
++ }
++
++ pwrpriv->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
++
++ // Update Radio OFF setting
++ switch (pdvobjpriv->const_hwsw_rfoff_d3) {
++ case 1:
++ if (pwrpriv->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
++ pwrpriv->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
++ break;
++
++ case 2:
++ if (pwrpriv->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
++ pwrpriv->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
++ pwrpriv->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
++ break;
++
++ case 3:
++ pwrpriv->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3;
++ break;
++ }
++
++ // Update Rx 2R setting
++ //pPSC->reg_rfps_level |= ((pDevice->RegLPS2RDisable) ? RT_RF_LPS_DISALBE_2R : 0);
++
++ //
++ // Set HW definition to determine if it supports ASPM.
++ //
++ switch (pdvobjpriv->const_support_pciaspm) {
++ case 0: // Not support ASPM.
++ {
++ u8 b_support_aspm = _FALSE;
++ pwrpriv->b_support_aspm = b_support_aspm;
++ }
++ break;
++
++ case 1: // Support ASPM.
++ {
++ u8 b_support_aspm = _TRUE;
++ u8 b_support_backdoor = _TRUE;
++
++ pwrpriv->b_support_aspm = b_support_aspm;
++
++ /*if(pAdapter->MgntInfo.CustomerID == RT_CID_TOSHIBA &&
++ pcipriv->pcibridge_vendor == PCI_BRIDGE_VENDOR_AMD &&
++ !pcipriv->amd_l1_patch)
++ b_support_backdoor = _FALSE;*/
++
++ pwrpriv->b_support_backdoor = b_support_backdoor;
++ }
++ break;
++
++ case 2: // Set by Chipset.
++ // ASPM value set by chipset.
++ if (pcipriv->pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) {
++ u8 b_support_aspm = _TRUE;
++ pwrpriv->b_support_aspm = b_support_aspm;
++ }
++ break;
++
++ default:
++ // Do nothing. Set when finding the chipset.
++ break;
++ }
++}
++
++static void rtw_pci_initialize_adapter_common(_adapter *padapter)
++{
++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
++
++ rtw_pci_update_default_setting(padapter);
++
++ if (pwrpriv->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) {
++ // Always enable ASPM & Clock Req.
++ rtw_pci_enable_aspm(padapter);
++ RT_SET_PS_LEVEL(pwrpriv, RT_RF_PS_LEVEL_ALWAYS_ASPM);
++ }
++
++}
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)) || (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,18))
++#define rtw_pci_interrupt(x,y,z) rtw_pci_interrupt(x,y)
++#endif
++
++static irqreturn_t rtw_pci_interrupt(int irq, void *priv, struct pt_regs *regs)
++{
++ struct dvobj_priv *dvobj = (struct dvobj_priv *)priv;
++ _adapter *adapter = dvobj->if1;
++
++ if (dvobj->irq_enabled == 0) {
++ return IRQ_HANDLED;
++ }
++
++ if(rtw_hal_interrupt_handler(adapter) == _FAIL)
++ return IRQ_HANDLED;
++ //return IRQ_NONE;
++
++ return IRQ_HANDLED;
++}
++
++#ifdef RTK_DMP_PLATFORM
++#define pci_iounmap(x,y) iounmap(y)
++#endif
++
++int pci_alloc_irq(struct dvobj_priv *dvobj)
++{
++ int err;
++ struct pci_dev *pdev = dvobj->ppcidev;
++
++#if defined(IRQF_SHARED)
++ err = request_irq(pdev->irq, &rtw_pci_interrupt, IRQF_SHARED, DRV_NAME, dvobj);
++#else
++ err = request_irq(pdev->irq, &rtw_pci_interrupt, SA_SHIRQ, DRV_NAME, dvobj);
++#endif
++ if (err) {
++ DBG_871X("Error allocating IRQ %d",pdev->irq);
++ } else {
++ dvobj->irq_alloc = 1;
++ DBG_871X("Request_irq OK, IRQ %d\n",pdev->irq);
++ }
++
++ return err?_FAIL:_SUCCESS;
++}
++
++static struct dvobj_priv *pci_dvobj_init(struct pci_dev *pdev)
++{
++ int err;
++ u32 status = _FAIL;
++ struct dvobj_priv *dvobj = NULL;
++ struct pci_priv *pcipriv = NULL;
++ struct pci_dev *bridge_pdev = pdev->bus->self;
++ unsigned long pmem_start, pmem_len, pmem_flags;
++ u8 tmp;
++
++_func_enter_;
++
++ if ((dvobj = devobj_init()) == NULL) {
++ goto exit;
++ }
++ dvobj->ppcidev = pdev;
++ pcipriv = &(dvobj->pcipriv);
++ pci_set_drvdata(pdev, dvobj);
++
++ if ( (err = pci_enable_device(pdev)) != 0) {
++ DBG_871X(KERN_ERR "%s : Cannot enable new PCI device\n", pci_name(pdev));
++ goto free_dvobj;
++ }
++
++#ifdef CONFIG_64BIT_DMA
++ if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
++ DBG_871X("RTL819xCE: Using 64bit DMA\n");
++ if ((err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) != 0) {
++ DBG_871X(KERN_ERR "Unable to obtain 64bit DMA for consistent allocations\n");
++ goto disable_picdev;
++ }
++ dvobj->bdma64 = _TRUE;
++ } else
++#endif
++ {
++ if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
++ if ((err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) != 0) {
++ DBG_871X(KERN_ERR "Unable to obtain 32bit DMA for consistent allocations\n");
++ goto disable_picdev;
++ }
++ }
++ }
++
++ pci_set_master(pdev);
++
++ if ((err = pci_request_regions(pdev, DRV_NAME)) != 0) {
++ DBG_871X(KERN_ERR "Can't obtain PCI resources\n");
++ goto disable_picdev;
++ }
++ //MEM map
++ pmem_start = pci_resource_start(pdev, 2);
++ pmem_len = pci_resource_len(pdev, 2);
++ pmem_flags = pci_resource_flags(pdev, 2);
++
++#ifdef RTK_DMP_PLATFORM
++ dvobj->pci_mem_start = (unsigned long)ioremap_nocache(pmem_start, pmem_len);
++#else
++ dvobj->pci_mem_start = (unsigned long)pci_iomap(pdev, 2, pmem_len); /* shared mem start */
++#endif
++ if (dvobj->pci_mem_start == 0) {
++ DBG_871X(KERN_ERR "Can't map PCI mem\n");
++ goto release_regions;
++ }
++
++ DBG_871X("Memory mapped space start: 0x%08lx len:%08lx flags:%08lx, after map:0x%08lx\n",
++ pmem_start, pmem_len, pmem_flags, dvobj->pci_mem_start);
++
++ // Disable Clk Request */
++ pci_write_config_byte(pdev, 0x81, 0);
++ // leave D3 mode */
++ pci_write_config_byte(pdev, 0x44, 0);
++ pci_write_config_byte(pdev, 0x04, 0x06);
++ pci_write_config_byte(pdev, 0x04, 0x07);
++
++
++#if 1
++ /*find bus info*/
++ pcipriv->busnumber = pdev->bus->number;
++ pcipriv->devnumber = PCI_SLOT(pdev->devfn);
++ pcipriv->funcnumber = PCI_FUNC(pdev->devfn);
++
++ /*find bridge info*/
++ pcipriv->pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
++ if(bridge_pdev){
++ pcipriv->pcibridge_vendorid = bridge_pdev->vendor;
++ for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) {
++ if (bridge_pdev->vendor == pcibridge_vendors[tmp]) {
++ pcipriv->pcibridge_vendor = tmp;
++ DBG_871X("Pci Bridge Vendor is found index: %d, %x\n", tmp, pcibridge_vendors[tmp]);
++ break;
++ }
++ }
++ }
++
++ //if (pcipriv->pcibridge_vendor != PCI_BRIDGE_VENDOR_UNKNOWN) {
++ if(bridge_pdev){
++ pcipriv->pcibridge_busnum = bridge_pdev->bus->number;
++ pcipriv->pcibridge_devnum = PCI_SLOT(bridge_pdev->devfn);
++ pcipriv->pcibridge_funcnum = PCI_FUNC(bridge_pdev->devfn);
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,34))
++ pcipriv->pcibridge_pciehdr_offset = pci_find_capability(bridge_pdev, PCI_CAP_ID_EXP);
++#else
++ pcipriv->pcibridge_pciehdr_offset = bridge_pdev->pcie_cap;
++#endif
++
++ rtw_pci_get_linkcontrol_field(dvobj);
++
++ if (pcipriv->pcibridge_vendor == PCI_BRIDGE_VENDOR_AMD) {
++ pcipriv->amd_l1_patch = rtw_pci_get_amd_l1_patch(dvobj);
++ }
++ }
++#else
++ //
++ // Find bridge related info.
++ //
++ rtw_get_pci_bus_info(padapter,
++ pdev->vendor,
++ pdev->device,
++ (u8) pdvobjpriv->irqline,
++ 0x02, 0x80, U1DONTCARE,
++ &pcipriv->busnumber,
++ &pcipriv->devnumber,
++ &pcipriv->funcnumber);
++
++ rtw_find_bridge_info(padapter);
++
++ if (pcipriv->pcibridge_vendor != PCI_BRIDGE_VENDOR_UNKNOWN) {
++ rtw_get_link_control_field(padapter,
++ pcipriv->pcibridge_busnum,
++ pcipriv->pcibridge_devnum,
++ pcipriv->pcibridge_funcnum);
++
++ if (pcipriv->pcibridge_vendor == PCI_BRIDGE_VENDOR_AMD) {
++ pcipriv->amd_l1_patch =
++ rtw_get_amd_l1_patch(padapter,
++ pcipriv->pcibridge_busnum,
++ pcipriv->pcibridge_devnum,
++ pcipriv->pcibridge_funcnum);
++ }
++ }
++#endif
++
++ //
++ // Allow the hardware to look at PCI config information.
++ //
++ rtw_pci_parse_configuration(dvobj);
++
++ DBG_871X("pcidev busnumber:devnumber:funcnumber:"
++ "vendor:link_ctl %d:%d:%d:%x:%x\n",
++ pcipriv->busnumber,
++ pcipriv->devnumber,
++ pcipriv->funcnumber,
++ pdev->vendor,
++ pcipriv->linkctrl_reg);
++
++ DBG_871X("pci_bridge busnumber:devnumber:funcnumber:vendor:"
++ "pcie_cap:link_ctl_reg: %d:%d:%d:%x:%x:%x:%x\n",
++ pcipriv->pcibridge_busnum,
++ pcipriv->pcibridge_devnum,
++ pcipriv->pcibridge_funcnum,
++ pcibridge_vendors[pcipriv->pcibridge_vendor],
++ pcipriv->pcibridge_pciehdr_offset,
++ pcipriv->pcibridge_linkctrlreg,
++ pcipriv->amd_l1_patch);
++
++ status = _SUCCESS;
++
++iounmap:
++ if (status != _SUCCESS && dvobj->pci_mem_start != 0) {
++ pci_iounmap(pdev, (void *)dvobj->pci_mem_start);
++ dvobj->pci_mem_start = 0;
++ }
++release_regions:
++ if (status != _SUCCESS)
++ pci_release_regions(pdev);
++disable_picdev:
++ if (status != _SUCCESS)
++ pci_disable_device(pdev);
++free_dvobj:
++ if (status != _SUCCESS && dvobj) {
++ pci_set_drvdata(pdev, NULL);
++ devobj_deinit(dvobj);
++ dvobj = NULL;
++ }
++exit:
++_func_exit_;
++ return dvobj;
++}
++
++static void pci_dvobj_deinit(struct pci_dev *pdev)
++{
++ struct dvobj_priv *dvobj = pci_get_drvdata(pdev);
++_func_enter_;
++
++ pci_set_drvdata(pdev, NULL);
++ if (dvobj) {
++ if (dvobj->irq_alloc) {
++ free_irq(pdev->irq, dvobj);
++ dvobj->irq_alloc = 0;
++ }
++
++ if (dvobj->pci_mem_start != 0) {
++ pci_iounmap(pdev, (void *)dvobj->pci_mem_start);
++ dvobj->pci_mem_start = 0;
++ }
++
++ devobj_deinit(dvobj);
++ }
++
++ pci_release_regions(pdev);
++ pci_disable_device(pdev);
++
++_func_exit_;
++}
++
++static void decide_chip_type_by_pci_device_id(_adapter *padapter, struct pci_dev *pdev)
++{
++ u16 venderid, deviceid, irqline;
++ u8 revisionid;
++ struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
++
++
++ venderid = pdev->vendor;
++ deviceid = pdev->device;
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23))
++ pci_read_config_byte(pdev, PCI_REVISION_ID, &revisionid); // PCI_REVISION_ID 0x08
++#else
++ revisionid = pdev->revision;
++#endif
++ pci_read_config_word(pdev, PCI_INTERRUPT_LINE, &irqline); // PCI_INTERRUPT_LINE 0x3c
++ pdvobjpriv->irqline = irqline;
++
++
++ //
++ // Decide hardware type here.
++ //
++ if( deviceid == HAL_HW_PCI_8185_DEVICE_ID ||
++ deviceid == HAL_HW_PCI_8188_DEVICE_ID ||
++ deviceid == HAL_HW_PCI_8198_DEVICE_ID)
++ {
++ DBG_871X("Adapter (8185/8185B) is found- VendorID/DeviceID=%x/%x\n", venderid, deviceid);
++ padapter->HardwareType=HARDWARE_TYPE_RTL8185;
++ }
++ else if (deviceid == HAL_HW_PCI_8190_DEVICE_ID ||
++ deviceid == HAL_HW_PCI_0045_DEVICE_ID ||
++ deviceid == HAL_HW_PCI_0046_DEVICE_ID ||
++ deviceid == HAL_HW_PCI_DLINK_DEVICE_ID)
++ {
++ DBG_871X("Adapter(8190 PCI) is found - vendorid/deviceid=%x/%x\n", venderid, deviceid);
++ padapter->HardwareType = HARDWARE_TYPE_RTL8190P;
++ }
++ else if (deviceid == HAL_HW_PCI_8192_DEVICE_ID ||
++ deviceid == HAL_HW_PCI_0044_DEVICE_ID ||
++ deviceid == HAL_HW_PCI_0047_DEVICE_ID ||
++ deviceid == HAL_HW_PCI_8192SE_DEVICE_ID ||
++ deviceid == HAL_HW_PCI_8174_DEVICE_ID ||
++ deviceid == HAL_HW_PCI_8173_DEVICE_ID ||
++ deviceid == HAL_HW_PCI_8172_DEVICE_ID ||
++ deviceid == HAL_HW_PCI_8171_DEVICE_ID)
++ {
++ // 8192e and and 8192se may have the same device ID 8192. However, their Revision
++ // ID is different
++ // Added for 92DE. We deferentiate it from SVID,SDID.
++ if( pdev->subsystem_vendor == 0x10EC && pdev->subsystem_device == 0xE020){
++ padapter->HardwareType = HARDWARE_TYPE_RTL8192DE;
++ DBG_871X("Adapter(8192DE) is found - VendorID/DeviceID/RID=%X/%X/%X\n", venderid, deviceid, revisionid);
++ }else{
++ switch (revisionid) {
++ case HAL_HW_PCI_REVISION_ID_8192PCIE:
++ DBG_871X("Adapter(8192 PCI-E) is found - vendorid/deviceid=%x/%x\n", venderid, deviceid);
++ padapter->HardwareType = HARDWARE_TYPE_RTL8192E;
++ break;
++ case HAL_HW_PCI_REVISION_ID_8192SE:
++ DBG_871X("Adapter(8192SE) is found - vendorid/deviceid=%x/%x\n", venderid, deviceid);
++ padapter->HardwareType = HARDWARE_TYPE_RTL8192SE;
++ break;
++ default:
++ DBG_871X("Err: Unknown device - vendorid/deviceid=%x/%x\n", venderid, deviceid);
++ padapter->HardwareType = HARDWARE_TYPE_RTL8192SE;
++ break;
++ }
++ }
++ }
++ else if(deviceid==HAL_HW_PCI_8723E_DEVICE_ID )
++ {//RTL8723E may have the same device ID with RTL8192CET
++ padapter->HardwareType = HARDWARE_TYPE_RTL8723AE;
++ DBG_871X("Adapter(8723 PCI-E) is found - VendorID/DeviceID=%x/%x\n", venderid, deviceid);
++ }
++ else if (deviceid == HAL_HW_PCI_8192CET_DEVICE_ID ||
++ deviceid == HAL_HW_PCI_8192CE_DEVICE_ID ||
++ deviceid == HAL_HW_PCI_8191CE_DEVICE_ID ||
++ deviceid == HAL_HW_PCI_8188CE_DEVICE_ID)
++ {
++ DBG_871X("Adapter(8192C PCI-E) is found - vendorid/deviceid=%x/%x\n", venderid, deviceid);
++ padapter->HardwareType = HARDWARE_TYPE_RTL8192CE;
++ }
++ else if (deviceid == HAL_HW_PCI_8192DE_DEVICE_ID ||
++ deviceid == HAL_HW_PCI_002B_DEVICE_ID ){
++ padapter->HardwareType = HARDWARE_TYPE_RTL8192DE;
++ DBG_871X("Adapter(8192DE) is found - VendorID/DeviceID/RID=%X/%X/%X\n", venderid, deviceid, revisionid);
++ }
++ else
++ {
++ DBG_871X("Err: Unknown device - vendorid/deviceid=%x/%x\n", venderid, deviceid);
++ //padapter->HardwareType = HAL_DEFAULT_HARDWARE_TYPE;
++ }
++
++
++ padapter->chip_type = NULL_CHIP_TYPE;
++
++ //TODO:
++#ifdef CONFIG_RTL8192C
++ padapter->chip_type = RTL8188C_8192C;
++ padapter->HardwareType = HARDWARE_TYPE_RTL8192CE;
++#endif
++#ifdef CONFIG_RTL8192D
++ pdvobjpriv->InterfaceNumber = revisionid;
++
++ padapter->chip_type = RTL8192D;
++ padapter->HardwareType = HARDWARE_TYPE_RTL8192DE;
++#endif
++
++}
++
++static void pci_intf_start(_adapter *padapter)
++{
++
++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("+pci_intf_start\n"));
++ DBG_871X("+pci_intf_start\n");
++
++#ifdef CONFIG_PCILED_BLINK
++ rtw_led_control(padapter, LED_CTL_NO_LINK);
++#endif
++ //Enable hw interrupt
++ rtw_hal_enable_interrupt(padapter);
++
++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("-pci_intf_start\n"));
++ DBG_871X("-pci_intf_start\n");
++}
++
++static void pci_intf_stop(_adapter *padapter)
++{
++
++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("+pci_intf_stop\n"));
++
++ //Disable hw interrupt
++ if(padapter->bSurpriseRemoved == _FALSE)
++ {
++ //device still exists, so driver can do i/o operation
++ rtw_hal_disable_interrupt(padapter);
++ tasklet_disable(&(padapter->recvpriv.recv_tasklet));
++ tasklet_disable(&(padapter->recvpriv.irq_prepare_beacon_tasklet));
++ tasklet_disable(&(padapter->xmitpriv.xmit_tasklet));
++
++#ifdef CONFIG_CONCURRENT_MODE
++ /* This function only be called at driver removing. disable buddy_adapter too
++ don't disable interrupt of buddy_adapter because it is same as primary.
++ */
++ if (padapter->pbuddy_adapter){
++ tasklet_disable(&(padapter->pbuddy_adapter->recvpriv.recv_tasklet));
++ tasklet_disable(&(padapter->pbuddy_adapter->recvpriv.irq_prepare_beacon_tasklet));
++ tasklet_disable(&(padapter->pbuddy_adapter->xmitpriv.xmit_tasklet));
++ }
++#endif
++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("pci_intf_stop: SurpriseRemoved==_FALSE\n"));
++ }
++ else
++ {
++ // Clear irq_enabled to prevent handle interrupt function.
++ adapter_to_dvobj(padapter)->irq_enabled = 0;
++ }
++
++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("-pci_intf_stop\n"));
++
++}
++
++
++static void rtw_dev_unload(_adapter *padapter)
++{
++ struct net_device *pnetdev= (struct net_device*)padapter->pnetdev;
++
++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("+rtw_dev_unload\n"));
++
++ if(padapter->bup == _TRUE)
++ {
++ DBG_871X("+rtw_dev_unload\n");
++
++ padapter->bDriverStopped = _TRUE;
++ #ifdef CONFIG_XMIT_ACK
++ if (padapter->xmitpriv.ack_tx)
++ rtw_ack_tx_done(&padapter->xmitpriv, RTW_SCTX_DONE_DRV_STOP);
++ #endif
++
++ //s3.
++ if(padapter->intf_stop)
++ {
++ padapter->intf_stop(padapter);
++ }
++
++ //s4.
++ rtw_stop_drv_threads(padapter);
++
++
++ //s5.
++ if(padapter->bSurpriseRemoved == _FALSE)
++ {
++ DBG_871X("r871x_dev_unload()->rtl871x_hal_deinit()\n");
++ rtw_hal_deinit(padapter);
++
++ padapter->bSurpriseRemoved = _TRUE;
++ }
++
++ padapter->bup = _FALSE;
++
++ }
++ else
++ {
++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("r871x_dev_unload():padapter->bup == _FALSE\n" ));
++ }
++
++ DBG_871X("-rtw_dev_unload\n");
++
++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("-rtw_dev_unload\n"));
++
++}
++
++static void disable_ht_for_spec_devid(const struct pci_device_id *pdid)
++{
++#ifdef CONFIG_80211N_HT
++ u16 vid, pid;
++ u32 flags;
++ int i;
++ int num = sizeof(specific_device_id_tbl)/sizeof(struct specific_device_id);
++
++ for(i=0; i<num; i++)
++ {
++ vid = specific_device_id_tbl[i].idVendor;
++ pid = specific_device_id_tbl[i].idProduct;
++ flags = specific_device_id_tbl[i].flags;
++
++ if((pdid->vendor==vid) && (pdid->device==pid) && (flags&SPEC_DEV_ID_DISABLE_HT))
++ {
++ rtw_ht_enable = 0;
++ rtw_cbw40_enable = 0;
++ rtw_ampdu_enable = 0;
++ }
++
++ }
++#endif
++}
++
++#ifdef CONFIG_PM
++static int rtw_suspend(struct pci_dev *pdev, pm_message_t state)
++{
++ _func_enter_;
++
++
++ _func_exit_;
++ return 0;
++}
++
++static int rtw_resume(struct pci_dev *pdev)
++{
++ _func_enter_;
++
++
++ _func_exit_;
++
++ return 0;
++}
++#endif
++
++_adapter *rtw_pci_if1_init(struct dvobj_priv * dvobj, struct pci_dev *pdev,
++ const struct pci_device_id *pdid)
++{
++ _adapter *padapter = NULL;
++ struct net_device *pnetdev = NULL;
++ int status = _FAIL;
++
++ if ((padapter = (_adapter *)rtw_zvmalloc(sizeof(*padapter))) == NULL) {
++ goto exit;
++ }
++ padapter->dvobj = dvobj;
++ dvobj->if1 = padapter;
++
++ padapter->bDriverStopped=_TRUE;
++
++ dvobj->padapters[dvobj->iface_nums++] = padapter;
++ padapter->iface_id = IFACE_ID0;
++
++#if defined(CONFIG_CONCURRENT_MODE) || defined(CONFIG_DUALMAC_CONCURRENT)
++ //set adapter_type/iface type for primary padapter
++ padapter->isprimary = _TRUE;
++ padapter->adapter_type = PRIMARY_ADAPTER;
++ #ifndef CONFIG_HWPORT_SWAP
++ padapter->iface_type = IFACE_PORT0;
++ #else
++ padapter->iface_type = IFACE_PORT1;
++ #endif
++#endif
++
++ //step 1-1., decide the chip_type via vid/pid
++ padapter->interface_type = RTW_PCIE;
++ decide_chip_type_by_pci_device_id(padapter, pdev);
++
++ if((pnetdev = rtw_init_netdev(padapter)) == NULL) {
++ goto free_adapter;
++ }
++ if (dvobj->bdma64)
++ pnetdev->features |= NETIF_F_HIGHDMA;
++ pnetdev->irq = pdev->irq;
++ SET_NETDEV_DEV(pnetdev, dvobj_to_dev(dvobj));
++ padapter = rtw_netdev_priv(pnetdev);
++
++ //step 2. hook HalFunc, allocate HalData
++ if (padapter->chip_type == RTL8188C_8192C) {
++ #ifdef CONFIG_RTL8192C
++ rtl8192ce_set_hal_ops(padapter);
++ #endif
++ } else if (padapter->chip_type == RTL8192D) {
++ #ifdef CONFIG_RTL8192D
++ rtl8192de_set_hal_ops(padapter);
++ #endif
++ } else {
++ DBG_871X("Detect NULL_CHIP_TYPE\n");
++ goto free_hal_data;
++ }
++
++ //step 3. initialize the dvobj_priv
++ padapter->intf_start=&pci_intf_start;
++ padapter->intf_stop=&pci_intf_stop;
++
++
++ //.2
++ if ((rtw_init_io_priv(padapter, pci_set_intf_ops)) == _FAIL) {
++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,(" \n Can't init io_reqs\n"));
++ goto free_hal_data;
++ }
++
++ //.3
++ rtw_hal_read_chip_version(padapter);
++
++ //.4
++ rtw_hal_chip_configure(padapter);
++
++ //step 4. read efuse/eeprom data and get mac_addr
++ rtw_hal_read_chip_info(padapter);
++
++ if (rtw_handle_dualmac(padapter, 1) != _SUCCESS)
++ goto free_hal_data;
++
++#ifdef CONFIG_IOCTL_CFG80211
++ if(rtw_wdev_alloc(padapter, dvobj_to_dev(dvobj)) != 0) {
++ goto handle_dualmac;
++ }
++#endif
++
++ //step 5.
++ if (rtw_init_drv_sw(padapter) == _FAIL) {
++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("Initialize driver software resource Failed!\n"));
++ goto free_wdev;
++ }
++
++ status = rtw_hal_inirp_init(padapter);
++ if(status ==_FAIL){
++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("Initialize PCI desc ring Failed!\n"));
++ goto free_drv_sw;
++ }
++
++ rtw_macaddr_cfg(padapter->eeprompriv.mac_addr);
++ rtw_init_wifidirect_addrs(padapter, padapter->eeprompriv.mac_addr, padapter->eeprompriv.mac_addr);
++
++
++ rtw_hal_disable_interrupt(padapter);
++
++ //step 6. Init pci related configuration
++ rtw_pci_initialize_adapter_common(padapter);
++
++ DBG_871X("bDriverStopped:%d, bSurpriseRemoved:%d, bup:%d, hw_init_completed:%d\n"
++ ,padapter->bDriverStopped
++ ,padapter->bSurpriseRemoved
++ ,padapter->bup
++ ,padapter->hw_init_completed
++ );
++
++ status = _SUCCESS;
++
++inirp_deinit:
++ if (status != _SUCCESS)
++ rtw_hal_inirp_deinit(padapter);
++free_drv_sw:
++ if (status != _SUCCESS)
++ rtw_free_drv_sw(padapter);
++free_wdev:
++ if (status != _SUCCESS) {
++ #ifdef CONFIG_IOCTL_CFG80211
++ rtw_wdev_unregister(padapter->rtw_wdev);
++ rtw_wdev_free(padapter->rtw_wdev);
++ #endif
++ }
++handle_dualmac:
++ if (status != _SUCCESS)
++ rtw_handle_dualmac(padapter, 0);
++free_hal_data:
++ if (status != _SUCCESS && padapter->HalData)
++ rtw_mfree(padapter->HalData, sizeof(*(padapter->HalData)));
++free_adapter:
++ if (status != _SUCCESS) {
++ if (pnetdev)
++ rtw_free_netdev(pnetdev);
++ else if (padapter)
++ rtw_vmfree((u8*)padapter, sizeof(*padapter));
++ padapter = NULL;
++ }
++exit:
++ return padapter;
++}
++
++static void rtw_pci_if1_deinit(_adapter *if1)
++{
++ struct net_device *pnetdev = if1->pnetdev;
++ struct mlme_priv *pmlmepriv= &if1->mlmepriv;
++
++ // padapter->intf_stop(padapter);
++
++ if(check_fwstate(pmlmepriv, _FW_LINKED))
++ rtw_disassoc_cmd(if1, 0, _FALSE);
++
++#ifdef CONFIG_AP_MODE
++ free_mlme_ap_info(if1);
++ #ifdef CONFIG_HOSTAPD_MLME
++ hostapd_mode_unload(if1);
++ #endif
++#endif
++
++ rtw_cancel_all_timer(if1);
++#ifdef CONFIG_WOWLAN
++ if1->pwrctrlpriv.wowlan_mode=_FALSE;
++#endif //CONFIG_WOWLAN
++ rtw_dev_unload(if1);
++
++ DBG_871X("%s, hw_init_completed=%d\n", __func__, if1->hw_init_completed);
++
++ //s6.
++ rtw_handle_dualmac(if1, 0);
++
++#ifdef CONFIG_IOCTL_CFG80211
++ if (if1->rtw_wdev)
++ rtw_wdev_free(if1->rtw_wdev);
++#endif //CONFIG_IOCTL_CFG80211
++
++ rtw_hal_inirp_deinit(if1);
++ rtw_free_drv_sw(if1);
++
++ if(pnetdev)
++ rtw_free_netdev(pnetdev);
++
++#ifdef CONFIG_PLATFORM_RTD2880B
++ DBG_871X("wlan link down\n");
++ rtd2885_wlan_netlink_sendMsg("linkdown", "8712");
++#endif
++}
++
++/*
++ * drv_init() - a device potentially for us
++ *
++ * notes: drv_init() is called when the bus driver has located a card for us to support.
++ * We accept the new device by returning 0.
++*/
++static int rtw_drv_init(struct pci_dev *pdev, const struct pci_device_id *did)
++{
++ int i, err = -ENODEV;
++
++ int status;
++ _adapter *if1 = NULL, *if2 = NULL;
++ struct dvobj_priv *dvobj;
++
++ RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("+rtw_drv_init\n"));
++
++ //step 0.
++ disable_ht_for_spec_devid(did);
++
++ /* Initialize dvobj_priv */
++ if ((dvobj = pci_dvobj_init(pdev)) == NULL) {
++ RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("initialize device object priv Failed!\n"));
++ goto exit;
++ }
++
++ /* Initialize if1 */
++ if ((if1 = rtw_pci_if1_init(dvobj, pdev, did)) == NULL) {
++ DBG_871X("rtw_pci_if1_init Failed!\n");
++ goto free_dvobj;
++ }
++
++ /* Initialize if2 */
++#ifdef CONFIG_CONCURRENT_MODE
++ if((if2 = rtw_drv_if2_init(if1, pci_set_intf_ops)) == NULL) {
++ goto free_if1;
++ }
++#endif
++
++#ifdef CONFIG_GLOBAL_UI_PID
++ if (ui_pid[1]!=0) {
++ DBG_871X("ui_pid[1]:%d\n",ui_pid[1]);
++ rtw_signal_process(ui_pid[1], SIGUSR2);
++ }
++#endif
++
++ //dev_alloc_name && register_netdev
++ if((status = rtw_drv_register_netdev(if1)) != _SUCCESS) {
++ goto free_if1;
++ }
++
++#ifdef CONFIG_HOSTAPD_MLME
++ hostapd_mode_init(if1);
++#endif
++
++#ifdef CONFIG_PLATFORM_RTD2880B
++ DBG_871X("wlan link up\n");
++ rtd2885_wlan_netlink_sendMsg("linkup", "8712");
++#endif
++
++#ifdef RTK_DMP_PLATFORM
++ rtw_proc_init_one(if1->pnetdev);
++#endif
++
++
++ /* alloc irq */
++ if (pci_alloc_irq(dvobj) != _SUCCESS)
++ goto free_if2;
++
++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("-871x_drv - drv_init, success!\n"));
++ //DBG_871X("-871x_drv - drv_init, success!\n");
++
++ status = _SUCCESS;
++
++free_if2:
++ if(status != _SUCCESS && if2) {
++ #ifdef CONFIG_CONCURRENT_MODE
++ rtw_drv_if2_stop(if2);
++ rtw_drv_if2_free(if2);
++ #endif
++ }
++free_if1:
++ if (status != _SUCCESS && if1) {
++ rtw_pci_if1_deinit(if1);
++ }
++free_dvobj:
++ if (status != _SUCCESS)
++ pci_dvobj_deinit(pdev);
++exit:
++ return status == _SUCCESS?0:-ENODEV;
++}
++
++/*
++ * dev_remove() - our device is being removed
++*/
++//rmmod module & unplug(SurpriseRemoved) will call r871xu_dev_remove() => how to recognize both
++static void rtw_dev_remove(struct pci_dev *pdev)
++{
++ struct dvobj_priv *pdvobjpriv = pci_get_drvdata(pdev);
++ _adapter *padapter = pdvobjpriv->if1;
++ struct net_device *pnetdev = padapter->pnetdev;
++
++_func_exit_;
++
++ DBG_871X("+rtw_dev_remove\n");
++
++ pdvobjpriv->processing_dev_remove = _TRUE;
++
++ if (unlikely(!padapter)) {
++ return;
++ }
++
++ rtw_unregister_netdevs(pdvobjpriv);
++
++ #if 0
++#ifdef RTK_DMP_PLATFORM
++ padapter->bSurpriseRemoved = _FALSE; // always trate as device exists
++ // this will let the driver to disable it's interrupt
++#else
++ if(pci_drvpriv.drv_registered == _TRUE)
++ {
++ //DBG_871X("r871xu_dev_remove():padapter->bSurpriseRemoved == _TRUE\n");
++ padapter->bSurpriseRemoved = _TRUE;
++ }
++ /*else
++ {
++ //DBG_871X("r871xu_dev_remove():module removed\n");
++ padapter->hw_init_completed = _FALSE;
++ }*/
++#endif
++ #endif
++
++#if defined(CONFIG_HAS_EARLYSUSPEND) || defined(CONFIG_ANDROID_POWER)
++ rtw_unregister_early_suspend(&padapter->pwrctrlpriv);
++#endif
++
++ rtw_pm_set_ips(padapter, IPS_NONE);
++ rtw_pm_set_lps(padapter, PS_MODE_ACTIVE);
++
++ LeaveAllPowerSaveMode(padapter);
++
++ rtw_hal_disable_interrupt(padapter);
++
++#ifdef CONFIG_CONCURRENT_MODE
++ rtw_drv_if2_stop(pdvobjpriv->if2);
++#endif //CONFIG_CONCURRENT_MODE
++
++ rtw_pci_if1_deinit(padapter);
++
++#ifdef CONFIG_CONCURRENT_MODE
++ rtw_drv_if2_free(pdvobjpriv->if2);
++#endif
++
++ pci_dvobj_deinit(pdev);
++
++ DBG_871X("-r871xu_dev_remove, done\n");
++
++_func_exit_;
++ return;
++}
++
++
++static int __init rtw_drv_entry(void)
++{
++ int ret = 0;
++
++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("+rtw_drv_entry\n"));
++ DBG_871X("rtw driver version=%s\n", DRIVERVERSION);
++ DBG_871X("Build at: %s %s\n", __DATE__, __TIME__);
++ pci_drvpriv.drv_registered = _TRUE;
++
++ rtw_suspend_lock_init();
++
++ ret = pci_register_driver(&pci_drvpriv.rtw_pci_drv);
++ if (ret) {
++ RT_TRACE(_module_hci_intfs_c_, _drv_err_, (": No device found\n"));
++ }
++
++ return ret;
++}
++
++static void __exit rtw_drv_halt(void)
++{
++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("+rtw_drv_halt\n"));
++ DBG_871X("+rtw_drv_halt\n");
++
++ pci_drvpriv.drv_registered = _FALSE;
++
++ pci_unregister_driver(&pci_drvpriv.rtw_pci_drv);
++
++ rtw_suspend_lock_uninit();
++ DBG_871X("-rtw_drv_halt\n");
++
++ rtw_mstat_dump();
++}
++
++
++module_init(rtw_drv_entry);
++module_exit(rtw_drv_halt);
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/os_dep/linux/pci_ops_linux.c linux-xbian-rpi/drivers/net/wireless/rtl8192cu/os_dep/linux/pci_ops_linux.c
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/os_dep/linux/pci_ops_linux.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/os_dep/linux/pci_ops_linux.c 2015-07-28 01:20:58.433199136 +0200
+@@ -0,0 +1,21 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *******************************************************************************/
++#define _PCI_OPS_LINUX_C_
++
++#include <drv_types.h>
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/os_dep/linux/recv_linux.c linux-xbian-rpi/drivers/net/wireless/rtl8192cu/os_dep/linux/recv_linux.c
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/os_dep/linux/recv_linux.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/os_dep/linux/recv_linux.c 2015-07-28 01:20:58.433199136 +0200
+@@ -0,0 +1,447 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#define _RECV_OSDEP_C_
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++
++#include <wifi.h>
++#include <recv_osdep.h>
++
++#include <osdep_intf.h>
++#include <ethernet.h>
++
++#ifdef CONFIG_USB_HCI
++#include <usb_ops.h>
++#endif
++
++//init os related resource in struct recv_priv
++int rtw_os_recv_resource_init(struct recv_priv *precvpriv, _adapter *padapter)
++{
++ int res=_SUCCESS;
++
++ return res;
++}
++
++//alloc os related resource in union recv_frame
++int rtw_os_recv_resource_alloc(_adapter *padapter, union recv_frame *precvframe)
++{
++ int res=_SUCCESS;
++
++ precvframe->u.hdr.pkt_newalloc = precvframe->u.hdr.pkt = NULL;
++
++ return res;
++
++}
++
++//free os related resource in union recv_frame
++void rtw_os_recv_resource_free(struct recv_priv *precvpriv)
++{
++
++}
++
++
++//alloc os related resource in struct recv_buf
++int rtw_os_recvbuf_resource_alloc(_adapter *padapter, struct recv_buf *precvbuf)
++{
++ int res=_SUCCESS;
++
++#ifdef CONFIG_USB_HCI
++ struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
++ struct usb_device *pusbd = pdvobjpriv->pusbdev;
++
++ precvbuf->irp_pending = _FALSE;
++ precvbuf->purb = usb_alloc_urb(0, GFP_KERNEL);
++ if(precvbuf->purb == NULL){
++ res = _FAIL;
++ }
++
++ precvbuf->pskb = NULL;
++
++ precvbuf->reuse = _FALSE;
++
++ precvbuf->pallocated_buf = precvbuf->pbuf = NULL;
++
++ precvbuf->pdata = precvbuf->phead = precvbuf->ptail = precvbuf->pend = NULL;
++
++ precvbuf->transfer_len = 0;
++
++ precvbuf->len = 0;
++
++ #ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX
++ precvbuf->pallocated_buf = rtw_usb_buffer_alloc(pusbd, (size_t)precvbuf->alloc_sz, &precvbuf->dma_transfer_addr);
++ precvbuf->pbuf = precvbuf->pallocated_buf;
++ if(precvbuf->pallocated_buf == NULL)
++ return _FAIL;
++ #endif //CONFIG_USE_USB_BUFFER_ALLOC_RX
++
++#endif //CONFIG_USB_HCI
++
++ return res;
++}
++
++//free os related resource in struct recv_buf
++int rtw_os_recvbuf_resource_free(_adapter *padapter, struct recv_buf *precvbuf)
++{
++ int ret = _SUCCESS;
++
++#ifdef CONFIG_USB_HCI
++
++#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX
++
++ struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
++ struct usb_device *pusbd = pdvobjpriv->pusbdev;
++
++ rtw_usb_buffer_free(pusbd, (size_t)precvbuf->alloc_sz, precvbuf->pallocated_buf, precvbuf->dma_transfer_addr);
++ precvbuf->pallocated_buf = NULL;
++ precvbuf->dma_transfer_addr = 0;
++
++#endif //CONFIG_USE_USB_BUFFER_ALLOC_RX
++
++ if(precvbuf->purb)
++ {
++ //usb_kill_urb(precvbuf->purb);
++ usb_free_urb(precvbuf->purb);
++ }
++
++#endif //CONFIG_USB_HCI
++
++
++ if(precvbuf->pskb)
++ rtw_skb_free(precvbuf->pskb);
++
++
++ return ret;
++
++}
++
++void rtw_handle_tkip_mic_err(_adapter *padapter,u8 bgroup)
++{
++#ifdef CONFIG_IOCTL_CFG80211
++ enum nl80211_key_type key_type;
++#endif
++ union iwreq_data wrqu;
++ struct iw_michaelmicfailure ev;
++ struct mlme_priv* pmlmepriv = &padapter->mlmepriv;
++ struct security_priv *psecuritypriv = &padapter->securitypriv;
++ u32 cur_time = 0;
++
++ if( psecuritypriv->last_mic_err_time == 0 )
++ {
++ psecuritypriv->last_mic_err_time = rtw_get_current_time();
++ }
++ else
++ {
++ cur_time = rtw_get_current_time();
++
++ if( cur_time - psecuritypriv->last_mic_err_time < 60*HZ )
++ {
++ psecuritypriv->btkip_countermeasure = _TRUE;
++ psecuritypriv->last_mic_err_time = 0;
++ psecuritypriv->btkip_countermeasure_time = cur_time;
++ }
++ else
++ {
++ psecuritypriv->last_mic_err_time = rtw_get_current_time();
++ }
++ }
++
++#ifdef CONFIG_IOCTL_CFG80211
++ if ( bgroup )
++ {
++ key_type |= NL80211_KEYTYPE_GROUP;
++ }
++ else
++ {
++ key_type |= NL80211_KEYTYPE_PAIRWISE;
++ }
++
++ cfg80211_michael_mic_failure(padapter->pnetdev, (u8 *)&pmlmepriv->assoc_bssid[ 0 ], key_type, -1,
++ NULL, GFP_ATOMIC);
++#endif
++
++ _rtw_memset( &ev, 0x00, sizeof( ev ) );
++ if ( bgroup )
++ {
++ ev.flags |= IW_MICFAILURE_GROUP;
++ }
++ else
++ {
++ ev.flags |= IW_MICFAILURE_PAIRWISE;
++ }
++
++ ev.src_addr.sa_family = ARPHRD_ETHER;
++ _rtw_memcpy( ev.src_addr.sa_data, &pmlmepriv->assoc_bssid[ 0 ], ETH_ALEN );
++
++ _rtw_memset( &wrqu, 0x00, sizeof( wrqu ) );
++ wrqu.data.length = sizeof( ev );
++
++ wireless_send_event( padapter->pnetdev, IWEVMICHAELMICFAILURE, &wrqu, (char*) &ev );
++}
++
++void rtw_hostapd_mlme_rx(_adapter *padapter, union recv_frame *precv_frame)
++{
++#ifdef CONFIG_HOSTAPD_MLME
++ _pkt *skb;
++ struct hostapd_priv *phostapdpriv = padapter->phostapdpriv;
++ struct net_device *pmgnt_netdev = phostapdpriv->pmgnt_netdev;
++
++ RT_TRACE(_module_recv_osdep_c_, _drv_info_, ("+rtw_hostapd_mlme_rx\n"));
++
++ skb = precv_frame->u.hdr.pkt;
++
++ if (skb == NULL)
++ return;
++
++ skb->data = precv_frame->u.hdr.rx_data;
++ skb->tail = precv_frame->u.hdr.rx_tail;
++ skb->len = precv_frame->u.hdr.len;
++
++ //pskb_copy = rtw_skb_copy(skb);
++// if(skb == NULL) goto _exit;
++
++ skb->dev = pmgnt_netdev;
++ skb->ip_summed = CHECKSUM_NONE;
++ skb->pkt_type = PACKET_OTHERHOST;
++ //skb->protocol = __constant_htons(0x0019); /*ETH_P_80211_RAW*/
++ skb->protocol = __constant_htons(0x0003); /*ETH_P_80211_RAW*/
++
++ //DBG_871X("(1)data=0x%x, head=0x%x, tail=0x%x, mac_header=0x%x, len=%d\n", skb->data, skb->head, skb->tail, skb->mac_header, skb->len);
++
++ //skb->mac.raw = skb->data;
++ skb_reset_mac_header(skb);
++
++ //skb_pull(skb, 24);
++ _rtw_memset(skb->cb, 0, sizeof(skb->cb));
++
++ rtw_netif_rx(pmgnt_netdev, skb);
++
++ precv_frame->u.hdr.pkt = NULL; // set pointer to NULL before rtw_free_recvframe() if call rtw_netif_rx()
++#endif
++}
++
++int rtw_recv_indicatepkt(_adapter *padapter, union recv_frame *precv_frame)
++{
++ struct recv_priv *precvpriv;
++ _queue *pfree_recv_queue;
++ _pkt *skb;
++ struct mlme_priv*pmlmepriv = &padapter->mlmepriv;
++#ifdef CONFIG_TCP_CSUM_OFFLOAD_RX
++ struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;
++#endif
++
++#ifdef CONFIG_BR_EXT
++ void *br_port = NULL;
++#endif
++
++_func_enter_;
++
++ precvpriv = &(padapter->recvpriv);
++ pfree_recv_queue = &(precvpriv->free_recv_queue);
++
++#ifdef CONFIG_DRVEXT_MODULE
++ if (drvext_rx_handler(padapter, precv_frame->u.hdr.rx_data, precv_frame->u.hdr.len) == _SUCCESS)
++ {
++ goto _recv_indicatepkt_drop;
++ }
++#endif
++
++ skb = precv_frame->u.hdr.pkt;
++ if(skb == NULL)
++ {
++ RT_TRACE(_module_recv_osdep_c_,_drv_err_,("rtw_recv_indicatepkt():skb==NULL something wrong!!!!\n"));
++ goto _recv_indicatepkt_drop;
++ }
++
++ RT_TRACE(_module_recv_osdep_c_,_drv_info_,("rtw_recv_indicatepkt():skb != NULL !!!\n"));
++ RT_TRACE(_module_recv_osdep_c_,_drv_info_,("rtw_recv_indicatepkt():precv_frame->u.hdr.rx_head=%p precv_frame->hdr.rx_data=%p\n", precv_frame->u.hdr.rx_head, precv_frame->u.hdr.rx_data));
++ RT_TRACE(_module_recv_osdep_c_,_drv_info_,("precv_frame->hdr.rx_tail=%p precv_frame->u.hdr.rx_end=%p precv_frame->hdr.len=%d \n", precv_frame->u.hdr.rx_tail, precv_frame->u.hdr.rx_end, precv_frame->u.hdr.len));
++
++ skb->data = precv_frame->u.hdr.rx_data;
++
++ skb_set_tail_pointer(skb, precv_frame->u.hdr.len);
++
++ skb->len = precv_frame->u.hdr.len;
++
++ RT_TRACE(_module_recv_osdep_c_,_drv_info_,("\n skb->head=%p skb->data=%p skb->tail=%p skb->end=%p skb->len=%d\n", skb->head, skb->data, skb->tail, skb->end, skb->len));
++
++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE)
++ {
++ _pkt *pskb2=NULL;
++ struct sta_info *psta = NULL;
++ struct sta_priv *pstapriv = &padapter->stapriv;
++ struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;
++ int bmcast = IS_MCAST(pattrib->dst);
++
++ //DBG_871X("bmcast=%d\n", bmcast);
++
++ if(_rtw_memcmp(pattrib->dst, myid(&padapter->eeprompriv), ETH_ALEN)==_FALSE)
++ {
++ //DBG_871X("not ap psta=%p, addr=%pM\n", psta, pattrib->dst);
++
++ if(bmcast)
++ {
++ psta = rtw_get_bcmc_stainfo(padapter);
++ pskb2 = rtw_skb_clone(skb);
++ } else {
++ psta = rtw_get_stainfo(pstapriv, pattrib->dst);
++ }
++
++ if(psta)
++ {
++ struct net_device *pnetdev= (struct net_device*)padapter->pnetdev;
++
++ //DBG_871X("directly forwarding to the rtw_xmit_entry\n");
++
++ //skb->ip_summed = CHECKSUM_NONE;
++ skb->dev = pnetdev;
++#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,35))
++ skb_set_queue_mapping(skb, rtw_recv_select_queue(skb));
++#endif //LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,35)
++
++ _rtw_xmit_entry(skb, pnetdev);
++
++ if(bmcast)
++ skb = pskb2;
++ else
++ goto _recv_indicatepkt_end;
++ }
++
++
++ }
++ else// to APself
++ {
++ //DBG_871X("to APSelf\n");
++ }
++ }
++
++
++#ifdef CONFIG_BR_EXT
++
++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35))
++ br_port = padapter->pnetdev->br_port;
++#else // (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35))
++ rcu_read_lock();
++ br_port = rcu_dereference(padapter->pnetdev->rx_handler_data);
++ rcu_read_unlock();
++#endif // (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35))
++
++ if( br_port && (check_fwstate(pmlmepriv, WIFI_STATION_STATE|WIFI_ADHOC_STATE) == _TRUE) )
++ {
++ int nat25_handle_frame(_adapter *priv, struct sk_buff *skb);
++ if (nat25_handle_frame(padapter, skb) == -1) {
++ //priv->ext_stats.rx_data_drops++;
++ //DEBUG_ERR("RX DROP: nat25_handle_frame fail!\n");
++ //return FAIL;
++#if 1
++ // bypass this frame to upper layer!!
++#else
++ goto _recv_indicatepkt_drop;
++#endif
++ }
++ }
++
++#endif // CONFIG_BR_EXT
++
++
++#ifdef CONFIG_TCP_CSUM_OFFLOAD_RX
++ if ( (pattrib->tcpchk_valid == 1) && (pattrib->tcp_chkrpt == 1) ) {
++ skb->ip_summed = CHECKSUM_UNNECESSARY;
++ //DBG_871X("CHECKSUM_UNNECESSARY \n");
++ } else {
++ skb->ip_summed = CHECKSUM_NONE;
++ //DBG_871X("CHECKSUM_NONE(%d, %d) \n", pattrib->tcpchk_valid, pattrib->tcp_chkrpt);
++ }
++#else /* !CONFIG_TCP_CSUM_OFFLOAD_RX */
++
++ skb->ip_summed = CHECKSUM_NONE;
++
++#endif
++
++ skb->dev = padapter->pnetdev;
++ skb->protocol = eth_type_trans(skb, padapter->pnetdev);
++
++ rtw_netif_rx(padapter->pnetdev, skb);
++
++_recv_indicatepkt_end:
++
++ precv_frame->u.hdr.pkt = NULL; // pointers to NULL before rtw_free_recvframe()
++
++ rtw_free_recvframe(precv_frame, pfree_recv_queue);
++
++ RT_TRACE(_module_recv_osdep_c_,_drv_info_,("\n rtw_recv_indicatepkt :after rtw_netif_rx!!!!\n"));
++
++_func_exit_;
++
++ return _SUCCESS;
++
++_recv_indicatepkt_drop:
++
++ //enqueue back to free_recv_queue
++ if(precv_frame)
++ rtw_free_recvframe(precv_frame, pfree_recv_queue);
++
++ return _FAIL;
++
++_func_exit_;
++
++}
++
++void rtw_os_read_port(_adapter *padapter, struct recv_buf *precvbuf)
++{
++ struct recv_priv *precvpriv = &padapter->recvpriv;
++
++#ifdef CONFIG_USB_HCI
++
++ precvbuf->ref_cnt--;
++
++ //free skb in recv_buf
++ rtw_skb_free(precvbuf->pskb);
++
++ precvbuf->pskb = NULL;
++ precvbuf->reuse = _FALSE;
++
++ if(precvbuf->irp_pending == _FALSE)
++ {
++ rtw_read_port(padapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf);
++ }
++
++
++#endif
++#ifdef CONFIG_SDIO_HCI
++ precvbuf->pskb = NULL;
++#endif
++
++}
++void _rtw_reordering_ctrl_timeout_handler (void *FunctionContext);
++void _rtw_reordering_ctrl_timeout_handler (void *FunctionContext)
++{
++ struct recv_reorder_ctrl *preorder_ctrl = (struct recv_reorder_ctrl *)FunctionContext;
++ rtw_reordering_ctrl_timeout_handler(preorder_ctrl);
++}
++
++void rtw_init_recv_timer(struct recv_reorder_ctrl *preorder_ctrl)
++{
++ _adapter *padapter = preorder_ctrl->padapter;
++
++ _init_timer(&(preorder_ctrl->reordering_ctrl_timer), padapter->pnetdev, _rtw_reordering_ctrl_timeout_handler, preorder_ctrl);
++
++}
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/os_dep/linux/rtw_android.c linux-xbian-rpi/drivers/net/wireless/rtl8192cu/os_dep/linux/rtw_android.c
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/os_dep/linux/rtw_android.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/os_dep/linux/rtw_android.c 2015-07-28 01:20:58.433199136 +0200
+@@ -0,0 +1,838 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++
++#include <linux/module.h>
++#include <linux/netdevice.h>
++
++#include <rtw_android.h>
++#include <osdep_service.h>
++#include <rtw_debug.h>
++#include <ioctl_cfg80211.h>
++#include <rtw_ioctl_set.h>
++
++#if defined(RTW_ENABLE_WIFI_CONTROL_FUNC)
++#include <linux/platform_device.h>
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
++#include <linux/wlan_plat.h>
++#else
++#include <linux/wifi_tiwlan.h>
++#endif
++#endif /* defined(RTW_ENABLE_WIFI_CONTROL_FUNC) */
++
++const char *android_wifi_cmd_str[ANDROID_WIFI_CMD_MAX] = {
++ "START",
++ "STOP",
++ "SCAN-ACTIVE",
++ "SCAN-PASSIVE",
++ "RSSI",
++ "LINKSPEED",
++ "RXFILTER-START",
++ "RXFILTER-STOP",
++ "RXFILTER-ADD",
++ "RXFILTER-REMOVE",
++ "BTCOEXSCAN-START",
++ "BTCOEXSCAN-STOP",
++ "BTCOEXMODE",
++ "SETSUSPENDOPT",
++ "P2P_DEV_ADDR",
++ "SETFWPATH",
++ "SETBAND",
++ "GETBAND",
++ "COUNTRY",
++ "P2P_SET_NOA",
++ "P2P_GET_NOA",
++ "P2P_SET_PS",
++ "SET_AP_WPS_P2P_IE",
++#ifdef PNO_SUPPORT
++ "PNOSSIDCLR",
++ "PNOSETUP ",
++ "PNOFORCE",
++ "PNODEBUG",
++#endif
++
++ "MACADDR",
++
++ "BLOCK",
++ "WFD-ENABLE",
++ "WFD-DISABLE",
++ "WFD-SET-TCPPORT",
++ "WFD-SET-MAXTPUT",
++ "WFD-SET-DEVTYPE",
++};
++
++#ifdef PNO_SUPPORT
++#define PNO_TLV_PREFIX 'S'
++#define PNO_TLV_VERSION '1'
++#define PNO_TLV_SUBVERSION '2'
++#define PNO_TLV_RESERVED '0'
++#define PNO_TLV_TYPE_SSID_IE 'S'
++#define PNO_TLV_TYPE_TIME 'T'
++#define PNO_TLV_FREQ_REPEAT 'R'
++#define PNO_TLV_FREQ_EXPO_MAX 'M'
++
++typedef struct cmd_tlv {
++ char prefix;
++ char version;
++ char subver;
++ char reserved;
++} cmd_tlv_t;
++#endif /* PNO_SUPPORT */
++
++typedef struct android_wifi_priv_cmd {
++
++#ifdef CONFIG_COMPAT
++ compat_uptr_t buf;
++#else
++ char *buf;
++#endif
++
++ int used_len;
++ int total_len;
++} android_wifi_priv_cmd;
++
++/**
++ * Local (static) functions and variables
++ */
++
++/* Initialize g_wifi_on to 1 so dhd_bus_start will be called for the first
++ * time (only) in dhd_open, subsequential wifi on will be handled by
++ * wl_android_wifi_on
++ */
++static int g_wifi_on = _TRUE;
++
++
++#ifdef PNO_SUPPORT
++static int wl_android_set_pno_setup(struct net_device *dev, char *command, int total_len)
++{
++ wlc_ssid_t ssids_local[MAX_PFN_LIST_COUNT];
++ int res = -1;
++ int nssid = 0;
++ cmd_tlv_t *cmd_tlv_temp;
++ char *str_ptr;
++ int tlv_size_left;
++ int pno_time = 0;
++ int pno_repeat = 0;
++ int pno_freq_expo_max = 0;
++
++#ifdef PNO_SET_DEBUG
++ int i;
++ char pno_in_example[] = {
++ 'P', 'N', 'O', 'S', 'E', 'T', 'U', 'P', ' ',
++ 'S', '1', '2', '0',
++ 'S',
++ 0x05,
++ 'd', 'l', 'i', 'n', 'k',
++ 'S',
++ 0x04,
++ 'G', 'O', 'O', 'G',
++ 'T',
++ '0', 'B',
++ 'R',
++ '2',
++ 'M',
++ '2',
++ 0x00
++ };
++#endif /* PNO_SET_DEBUG */
++
++ DHD_INFO(("%s: command=%s, len=%d\n", __FUNCTION__, command, total_len));
++
++ if (total_len < (strlen(CMD_PNOSETUP_SET) + sizeof(cmd_tlv_t))) {
++ DBG_871X("%s argument=%d less min size\n", __FUNCTION__, total_len);
++ goto exit_proc;
++ }
++
++#ifdef PNO_SET_DEBUG
++ memcpy(command, pno_in_example, sizeof(pno_in_example));
++ for (i = 0; i < sizeof(pno_in_example); i++)
++ printf("%02X ", command[i]);
++ printf("\n");
++ total_len = sizeof(pno_in_example);
++#endif
++
++ str_ptr = command + strlen(CMD_PNOSETUP_SET);
++ tlv_size_left = total_len - strlen(CMD_PNOSETUP_SET);
++
++ cmd_tlv_temp = (cmd_tlv_t *)str_ptr;
++ memset(ssids_local, 0, sizeof(ssids_local));
++
++ if ((cmd_tlv_temp->prefix == PNO_TLV_PREFIX) &&
++ (cmd_tlv_temp->version == PNO_TLV_VERSION) &&
++ (cmd_tlv_temp->subver == PNO_TLV_SUBVERSION)) {
++
++ str_ptr += sizeof(cmd_tlv_t);
++ tlv_size_left -= sizeof(cmd_tlv_t);
++
++ if ((nssid = wl_iw_parse_ssid_list_tlv(&str_ptr, ssids_local,
++ MAX_PFN_LIST_COUNT, &tlv_size_left)) <= 0) {
++ DBG_871X("SSID is not presented or corrupted ret=%d\n", nssid);
++ goto exit_proc;
++ } else {
++ if ((str_ptr[0] != PNO_TLV_TYPE_TIME) || (tlv_size_left <= 1)) {
++ DBG_871X("%s scan duration corrupted field size %d\n",
++ __FUNCTION__, tlv_size_left);
++ goto exit_proc;
++ }
++ str_ptr++;
++ pno_time = simple_strtoul(str_ptr, &str_ptr, 16);
++ DHD_INFO(("%s: pno_time=%d\n", __FUNCTION__, pno_time));
++
++ if (str_ptr[0] != 0) {
++ if ((str_ptr[0] != PNO_TLV_FREQ_REPEAT)) {
++ DBG_871X("%s pno repeat : corrupted field\n",
++ __FUNCTION__);
++ goto exit_proc;
++ }
++ str_ptr++;
++ pno_repeat = simple_strtoul(str_ptr, &str_ptr, 16);
++ DHD_INFO(("%s :got pno_repeat=%d\n", __FUNCTION__, pno_repeat));
++ if (str_ptr[0] != PNO_TLV_FREQ_EXPO_MAX) {
++ DBG_871X("%s FREQ_EXPO_MAX corrupted field size\n",
++ __FUNCTION__);
++ goto exit_proc;
++ }
++ str_ptr++;
++ pno_freq_expo_max = simple_strtoul(str_ptr, &str_ptr, 16);
++ DHD_INFO(("%s: pno_freq_expo_max=%d\n",
++ __FUNCTION__, pno_freq_expo_max));
++ }
++ }
++ } else {
++ DBG_871X("%s get wrong TLV command\n", __FUNCTION__);
++ goto exit_proc;
++ }
++
++ res = dhd_dev_pno_set(dev, ssids_local, nssid, pno_time, pno_repeat, pno_freq_expo_max);
++
++exit_proc:
++ return res;
++}
++#endif /* PNO_SUPPORT */
++
++int rtw_android_cmdstr_to_num(char *cmdstr)
++{
++ int cmd_num;
++ for(cmd_num=0 ; cmd_num<ANDROID_WIFI_CMD_MAX; cmd_num++)
++ if(0 == strncasecmp(cmdstr , android_wifi_cmd_str[cmd_num], strlen(android_wifi_cmd_str[cmd_num])) )
++ break;
++
++ return cmd_num;
++}
++
++int rtw_android_get_rssi(struct net_device *net, char *command, int total_len)
++{
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(net);
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ struct wlan_network *pcur_network = &pmlmepriv->cur_network;
++ int bytes_written = 0;
++
++ if(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) {
++ bytes_written += snprintf(&command[bytes_written], total_len, "%s rssi %d",
++ pcur_network->network.Ssid.Ssid, padapter->recvpriv.rssi);
++ }
++
++ return bytes_written;
++}
++
++int rtw_android_get_link_speed(struct net_device *net, char *command, int total_len)
++{
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(net);
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ struct wlan_network *pcur_network = &pmlmepriv->cur_network;
++ int bytes_written = 0;
++ u16 link_speed = 0;
++
++ link_speed = rtw_get_cur_max_rate(padapter)/10;
++ bytes_written = snprintf(command, total_len, "LinkSpeed %d", link_speed);
++
++ return bytes_written;
++}
++
++int rtw_android_get_macaddr(struct net_device *net, char *command, int total_len)
++{
++ _adapter *adapter = (_adapter *)rtw_netdev_priv(net);
++ int bytes_written = 0;
++
++ bytes_written = snprintf(command, total_len, "Macaddr = "MAC_FMT, MAC_ARG(net->dev_addr));
++ return bytes_written;
++}
++
++int rtw_android_set_country(struct net_device *net, char *command, int total_len)
++{
++ _adapter *adapter = (_adapter *)rtw_netdev_priv(net);
++ char *country_code = command + strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_COUNTRY]) + 1;
++ int ret = _FAIL;
++
++ ret = rtw_set_country(adapter, country_code);
++
++ return (ret==_SUCCESS)?0:-1;
++}
++
++int rtw_android_get_p2p_dev_addr(struct net_device *net, char *command, int total_len)
++{
++ int bytes_written = 0;
++
++ //We use the same address as our HW MAC address
++ _rtw_memcpy(command, net->dev_addr, ETH_ALEN);
++
++ bytes_written = ETH_ALEN;
++ return bytes_written;
++}
++
++int rtw_android_set_block(struct net_device *net, char *command, int total_len)
++{
++ _adapter *adapter = (_adapter *)rtw_netdev_priv(net);
++ char *block_value = command + strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_BLOCK]) + 1;
++
++ #ifdef CONFIG_IOCTL_CFG80211
++ wdev_to_priv(adapter->rtw_wdev)->block = (*block_value=='0')?_FALSE:_TRUE;
++ #endif
++
++ return 0;
++}
++
++int rtw_android_setband(struct net_device *net, char *command, int total_len)
++{
++ _adapter *adapter = (_adapter *)rtw_netdev_priv(net);
++ char *arg = command + strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_SETBAND]) + 1;
++ u32 band = GHZ_MAX;
++ int ret = _FAIL;
++
++ sscanf(arg, "%u", &band);
++ ret = rtw_set_band(adapter, band);
++
++ return (ret==_SUCCESS)?0:-1;
++}
++
++int rtw_android_getband(struct net_device *net, char *command, int total_len)
++{
++ _adapter *adapter = (_adapter *)rtw_netdev_priv(net);
++ int bytes_written = 0;
++
++ bytes_written = snprintf(command, total_len, "%u", adapter->setband);
++
++ return bytes_written;
++}
++
++int get_int_from_command( char* pcmd )
++{
++ int i = 0;
++
++ for( i = 0; i < strlen( pcmd ); i++ )
++ {
++ if ( pcmd[ i ] == '=' )
++ {
++ // Skip the '=' and space characters.
++ i += 2;
++ break;
++ }
++ }
++ return ( rtw_atoi( pcmd + i ) );
++}
++
++int rtw_android_priv_cmd(struct net_device *net, struct ifreq *ifr, int cmd)
++{
++ int ret = 0;
++ char *command = NULL;
++ int cmd_num;
++ int bytes_written = 0;
++ android_wifi_priv_cmd priv_cmd;
++
++ rtw_lock_suspend();
++
++ if (!ifr->ifr_data) {
++ ret = -EINVAL;
++ goto exit;
++ }
++ if (copy_from_user(&priv_cmd, ifr->ifr_data, sizeof(android_wifi_priv_cmd))) {
++ ret = -EFAULT;
++ goto exit;
++ }
++
++ command = rtw_zmalloc(priv_cmd.total_len);
++ if (!command)
++ {
++ DBG_871X("%s: failed to allocate memory\n", __FUNCTION__);
++ ret = -ENOMEM;
++ goto exit;
++ }
++
++ if (!access_ok(VERIFY_READ, priv_cmd.buf, priv_cmd.total_len)){
++ DBG_871X("%s: failed to access memory\n", __FUNCTION__);
++ ret = -EFAULT;
++ goto exit;
++ }
++ if (copy_from_user(command, (void *)priv_cmd.buf, priv_cmd.total_len)) {
++ ret = -EFAULT;
++ goto exit;
++ }
++
++ DBG_871X("%s: Android private cmd \"%s\" on %s\n"
++ , __FUNCTION__, command, ifr->ifr_name);
++
++ cmd_num = rtw_android_cmdstr_to_num(command);
++
++ switch(cmd_num) {
++ case ANDROID_WIFI_CMD_START:
++ //bytes_written = wl_android_wifi_on(net);
++ goto response;
++ case ANDROID_WIFI_CMD_SETFWPATH:
++ goto response;
++ }
++
++ if (!g_wifi_on) {
++ DBG_871X("%s: Ignore private cmd \"%s\" - iface %s is down\n"
++ ,__FUNCTION__, command, ifr->ifr_name);
++ ret = 0;
++ goto exit;
++ }
++
++ switch(cmd_num) {
++
++ case ANDROID_WIFI_CMD_STOP:
++ //bytes_written = wl_android_wifi_off(net);
++ break;
++
++ case ANDROID_WIFI_CMD_SCAN_ACTIVE:
++ //rtw_set_scan_mode((_adapter *)rtw_netdev_priv(net), SCAN_ACTIVE);
++#ifdef CONFIG_PLATFORM_MSTAR
++#ifdef CONFIG_IOCTL_CFG80211
++ (wdev_to_priv(net->ieee80211_ptr))->bandroid_scan = _TRUE;
++#endif //CONFIG_IOCTL_CFG80211
++#endif //CONFIG_PLATFORM_MSTAR
++ break;
++ case ANDROID_WIFI_CMD_SCAN_PASSIVE:
++ //rtw_set_scan_mode((_adapter *)rtw_netdev_priv(net), SCAN_PASSIVE);
++ break;
++
++ case ANDROID_WIFI_CMD_RSSI:
++ bytes_written = rtw_android_get_rssi(net, command, priv_cmd.total_len);
++ break;
++ case ANDROID_WIFI_CMD_LINKSPEED:
++ bytes_written = rtw_android_get_link_speed(net, command, priv_cmd.total_len);
++ break;
++
++ case ANDROID_WIFI_CMD_MACADDR:
++ bytes_written = rtw_android_get_macaddr(net, command, priv_cmd.total_len);
++ break;
++
++ case ANDROID_WIFI_CMD_BLOCK:
++ bytes_written = rtw_android_set_block(net, command, priv_cmd.total_len);
++ break;
++
++ case ANDROID_WIFI_CMD_RXFILTER_START:
++ //bytes_written = net_os_set_packet_filter(net, 1);
++ break;
++ case ANDROID_WIFI_CMD_RXFILTER_STOP:
++ //bytes_written = net_os_set_packet_filter(net, 0);
++ break;
++ case ANDROID_WIFI_CMD_RXFILTER_ADD:
++ //int filter_num = *(command + strlen(CMD_RXFILTER_ADD) + 1) - '0';
++ //bytes_written = net_os_rxfilter_add_remove(net, TRUE, filter_num);
++ break;
++ case ANDROID_WIFI_CMD_RXFILTER_REMOVE:
++ //int filter_num = *(command + strlen(CMD_RXFILTER_REMOVE) + 1) - '0';
++ //bytes_written = net_os_rxfilter_add_remove(net, FALSE, filter_num);
++ break;
++
++ case ANDROID_WIFI_CMD_BTCOEXSCAN_START:
++ /* TBD: BTCOEXSCAN-START */
++ break;
++ case ANDROID_WIFI_CMD_BTCOEXSCAN_STOP:
++ /* TBD: BTCOEXSCAN-STOP */
++ break;
++ case ANDROID_WIFI_CMD_BTCOEXMODE:
++ #if 0
++ uint mode = *(command + strlen(CMD_BTCOEXMODE) + 1) - '0';
++ if (mode == 1)
++ net_os_set_packet_filter(net, 0); /* DHCP starts */
++ else
++ net_os_set_packet_filter(net, 1); /* DHCP ends */
++#ifdef WL_CFG80211
++ bytes_written = wl_cfg80211_set_btcoex_dhcp(net, command);
++#endif
++ #endif
++ break;
++
++ case ANDROID_WIFI_CMD_SETSUSPENDOPT:
++ //bytes_written = wl_android_set_suspendopt(net, command, priv_cmd.total_len);
++ break;
++
++ case ANDROID_WIFI_CMD_SETBAND:
++ bytes_written = rtw_android_setband(net, command, priv_cmd.total_len);
++ break;
++
++ case ANDROID_WIFI_CMD_GETBAND:
++ bytes_written = rtw_android_getband(net, command, priv_cmd.total_len);
++ break;
++
++ case ANDROID_WIFI_CMD_COUNTRY:
++ bytes_written = rtw_android_set_country(net, command, priv_cmd.total_len);
++ break;
++
++#ifdef PNO_SUPPORT
++ case ANDROID_WIFI_CMD_PNOSSIDCLR_SET:
++ //bytes_written = dhd_dev_pno_reset(net);
++ break;
++ case ANDROID_WIFI_CMD_PNOSETUP_SET:
++ //bytes_written = wl_android_set_pno_setup(net, command, priv_cmd.total_len);
++ break;
++ case ANDROID_WIFI_CMD_PNOENABLE_SET:
++ //uint pfn_enabled = *(command + strlen(CMD_PNOENABLE_SET) + 1) - '0';
++ //bytes_written = dhd_dev_pno_enable(net, pfn_enabled);
++ break;
++#endif
++
++ case ANDROID_WIFI_CMD_P2P_DEV_ADDR:
++ bytes_written = rtw_android_get_p2p_dev_addr(net, command, priv_cmd.total_len);
++ break;
++ case ANDROID_WIFI_CMD_P2P_SET_NOA:
++ //int skip = strlen(CMD_P2P_SET_NOA) + 1;
++ //bytes_written = wl_cfg80211_set_p2p_noa(net, command + skip, priv_cmd.total_len - skip);
++ break;
++ case ANDROID_WIFI_CMD_P2P_GET_NOA:
++ //bytes_written = wl_cfg80211_get_p2p_noa(net, command, priv_cmd.total_len);
++ break;
++ case ANDROID_WIFI_CMD_P2P_SET_PS:
++ //int skip = strlen(CMD_P2P_SET_PS) + 1;
++ //bytes_written = wl_cfg80211_set_p2p_ps(net, command + skip, priv_cmd.total_len - skip);
++ break;
++
++#ifdef CONFIG_IOCTL_CFG80211
++ case ANDROID_WIFI_CMD_SET_AP_WPS_P2P_IE:
++ {
++ int skip = strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_SET_AP_WPS_P2P_IE]) + 3;
++ bytes_written = rtw_cfg80211_set_mgnt_wpsp2pie(net, command + skip, priv_cmd.total_len - skip, *(command + skip - 2) - '0');
++ break;
++ }
++#endif //CONFIG_IOCTL_CFG80211
++
++#ifdef CONFIG_WFD
++ case ANDROID_WIFI_CMD_WFD_ENABLE:
++ {
++ // Commented by Albert 2012/07/24
++ // We can enable the WFD function by using the following command:
++ // wpa_cli driver wfd-enable
++
++ struct wifi_display_info *pwfd_info;
++ _adapter* padapter = ( _adapter * ) rtw_netdev_priv(net);
++
++ pwfd_info = &padapter->wfd_info;
++ if( padapter->wdinfo.driver_interface == DRIVER_CFG80211 )
++ pwfd_info->wfd_enable = _TRUE;
++ break;
++ }
++
++ case ANDROID_WIFI_CMD_WFD_DISABLE:
++ {
++ // Commented by Albert 2012/07/24
++ // We can disable the WFD function by using the following command:
++ // wpa_cli driver wfd-disable
++
++ struct wifi_display_info *pwfd_info;
++ _adapter* padapter = ( _adapter * ) rtw_netdev_priv(net);
++
++ pwfd_info = &padapter->wfd_info;
++ if( padapter->wdinfo.driver_interface == DRIVER_CFG80211 )
++ pwfd_info->wfd_enable = _FALSE;
++ break;
++ }
++ case ANDROID_WIFI_CMD_WFD_SET_TCPPORT:
++ {
++ // Commented by Albert 2012/07/24
++ // We can set the tcp port number by using the following command:
++ // wpa_cli driver wfd-set-tcpport = 554
++
++ struct wifi_display_info *pwfd_info;
++ _adapter* padapter = ( _adapter * ) rtw_netdev_priv(net);
++
++ pwfd_info = &padapter->wfd_info;
++ if( padapter->wdinfo.driver_interface == DRIVER_CFG80211 )
++ pwfd_info->rtsp_ctrlport = ( u16 ) get_int_from_command( priv_cmd.buf );
++ break;
++ }
++ case ANDROID_WIFI_CMD_WFD_SET_MAX_TPUT:
++ {
++
++
++ break;
++ }
++ case ANDROID_WIFI_CMD_WFD_SET_DEVTYPE:
++ {
++ // Commented by Albert 2012/08/28
++ // Specify the WFD device type ( WFD source/primary sink )
++
++ struct wifi_display_info *pwfd_info;
++ _adapter* padapter = ( _adapter * ) rtw_netdev_priv(net);
++
++ pwfd_info = &padapter->wfd_info;
++ if( padapter->wdinfo.driver_interface == DRIVER_CFG80211 )
++ {
++ pwfd_info->wfd_device_type = ( u8 ) get_int_from_command( priv_cmd.buf );
++
++ pwfd_info->wfd_device_type &= WFD_DEVINFO_DUAL;
++ }
++ break;
++ }
++#endif
++ default:
++ DBG_871X("Unknown PRIVATE command %s - ignored\n", command);
++ snprintf(command, 3, "OK");
++ bytes_written = strlen("OK");
++ }
++
++response:
++ if (bytes_written >= 0) {
++ if ((bytes_written == 0) && (priv_cmd.total_len > 0))
++ command[0] = '\0';
++ if (bytes_written >= priv_cmd.total_len) {
++ DBG_871X("%s: bytes_written = %d\n", __FUNCTION__, bytes_written);
++ bytes_written = priv_cmd.total_len;
++ } else {
++ bytes_written++;
++ }
++ priv_cmd.used_len = bytes_written;
++ if (copy_to_user((void *)priv_cmd.buf, command, bytes_written)) {
++ DBG_871X("%s: failed to copy data to user buffer\n", __FUNCTION__);
++ ret = -EFAULT;
++ }
++ }
++ else {
++ ret = bytes_written;
++ }
++
++exit:
++ rtw_unlock_suspend();
++ if (command) {
++ rtw_mfree(command, priv_cmd.total_len);
++ }
++
++ return ret;
++}
++
++
++/**
++ * Functions for Android WiFi card detection
++ */
++#if defined(RTW_ENABLE_WIFI_CONTROL_FUNC)
++
++static int g_wifidev_registered = 0;
++static struct semaphore wifi_control_sem;
++static struct wifi_platform_data *wifi_control_data = NULL;
++static struct resource *wifi_irqres = NULL;
++
++static int wifi_add_dev(void);
++static void wifi_del_dev(void);
++
++int rtw_android_wifictrl_func_add(void)
++{
++ int ret = 0;
++ sema_init(&wifi_control_sem, 0);
++
++ ret = wifi_add_dev();
++ if (ret) {
++ DBG_871X("%s: platform_driver_register failed\n", __FUNCTION__);
++ return ret;
++ }
++ g_wifidev_registered = 1;
++
++ /* Waiting callback after platform_driver_register is done or exit with error */
++ if (down_timeout(&wifi_control_sem, msecs_to_jiffies(1000)) != 0) {
++ ret = -EINVAL;
++ DBG_871X("%s: platform_driver_register timeout\n", __FUNCTION__);
++ }
++
++ return ret;
++}
++
++void rtw_android_wifictrl_func_del(void)
++{
++ if (g_wifidev_registered)
++ {
++ wifi_del_dev();
++ g_wifidev_registered = 0;
++ }
++}
++
++void *wl_android_prealloc(int section, unsigned long size)
++{
++ void *alloc_ptr = NULL;
++ if (wifi_control_data && wifi_control_data->mem_prealloc) {
++ alloc_ptr = wifi_control_data->mem_prealloc(section, size);
++ if (alloc_ptr) {
++ DBG_871X("success alloc section %d\n", section);
++ if (size != 0L)
++ memset(alloc_ptr, 0, size);
++ return alloc_ptr;
++ }
++ }
++
++ DBG_871X("can't alloc section %d\n", section);
++ return NULL;
++}
++
++int wifi_get_irq_number(unsigned long *irq_flags_ptr)
++{
++ if (wifi_irqres) {
++ *irq_flags_ptr = wifi_irqres->flags & IRQF_TRIGGER_MASK;
++ return (int)wifi_irqres->start;
++ }
++#ifdef CUSTOM_OOB_GPIO_NUM
++ return CUSTOM_OOB_GPIO_NUM;
++#else
++ return -1;
++#endif
++}
++
++int wifi_set_power(int on, unsigned long msec)
++{
++ DBG_871X("%s = %d\n", __FUNCTION__, on);
++ if (wifi_control_data && wifi_control_data->set_power) {
++ wifi_control_data->set_power(on);
++ }
++ if (msec)
++ msleep(msec);
++ return 0;
++}
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
++int wifi_get_mac_addr(unsigned char *buf)
++{
++ DBG_871X("%s\n", __FUNCTION__);
++ if (!buf)
++ return -EINVAL;
++ if (wifi_control_data && wifi_control_data->get_mac_addr) {
++ return wifi_control_data->get_mac_addr(buf);
++ }
++ return -EOPNOTSUPP;
++}
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35)) */
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39)) || defined(COMPAT_KERNEL_RELEASE)
++void *wifi_get_country_code(char *ccode)
++{
++ DBG_871X("%s\n", __FUNCTION__);
++ if (!ccode)
++ return NULL;
++ if (wifi_control_data && wifi_control_data->get_country_code) {
++ return wifi_control_data->get_country_code(ccode);
++ }
++ return NULL;
++}
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39)) */
++
++static int wifi_set_carddetect(int on)
++{
++ DBG_871X("%s = %d\n", __FUNCTION__, on);
++ if (wifi_control_data && wifi_control_data->set_carddetect) {
++ wifi_control_data->set_carddetect(on);
++ }
++ return 0;
++}
++
++static int wifi_probe(struct platform_device *pdev)
++{
++ struct wifi_platform_data *wifi_ctrl =
++ (struct wifi_platform_data *)(pdev->dev.platform_data);
++
++ DBG_871X("## %s\n", __FUNCTION__);
++ wifi_irqres = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "bcmdhd_wlan_irq");
++ if (wifi_irqres == NULL)
++ wifi_irqres = platform_get_resource_byname(pdev,
++ IORESOURCE_IRQ, "bcm4329_wlan_irq");
++ wifi_control_data = wifi_ctrl;
++
++ wifi_set_power(1, 0); /* Power On */
++ wifi_set_carddetect(1); /* CardDetect (0->1) */
++
++ up(&wifi_control_sem);
++ return 0;
++}
++
++static int wifi_remove(struct platform_device *pdev)
++{
++ struct wifi_platform_data *wifi_ctrl =
++ (struct wifi_platform_data *)(pdev->dev.platform_data);
++
++ DBG_871X("## %s\n", __FUNCTION__);
++ wifi_control_data = wifi_ctrl;
++
++ wifi_set_power(0, 0); /* Power Off */
++ wifi_set_carddetect(0); /* CardDetect (1->0) */
++
++ up(&wifi_control_sem);
++ return 0;
++}
++
++static int wifi_suspend(struct platform_device *pdev, pm_message_t state)
++{
++ DBG_871X("##> %s\n", __FUNCTION__);
++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 39)) && defined(OOB_INTR_ONLY)
++ bcmsdh_oob_intr_set(0);
++#endif
++ return 0;
++}
++
++static int wifi_resume(struct platform_device *pdev)
++{
++ DBG_871X("##> %s\n", __FUNCTION__);
++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 39)) && defined(OOB_INTR_ONLY)
++ if (dhd_os_check_if_up(bcmsdh_get_drvdata()))
++ bcmsdh_oob_intr_set(1);
++#endif
++ return 0;
++}
++
++/* temporarily use these two */
++static struct platform_driver wifi_device = {
++ .probe = wifi_probe,
++ .remove = wifi_remove,
++ .suspend = wifi_suspend,
++ .resume = wifi_resume,
++ .driver = {
++ .name = "bcmdhd_wlan",
++ }
++};
++
++static struct platform_driver wifi_device_legacy = {
++ .probe = wifi_probe,
++ .remove = wifi_remove,
++ .suspend = wifi_suspend,
++ .resume = wifi_resume,
++ .driver = {
++ .name = "bcm4329_wlan",
++ }
++};
++
++static int wifi_add_dev(void)
++{
++ DBG_871X("## Calling platform_driver_register\n");
++ platform_driver_register(&wifi_device);
++ platform_driver_register(&wifi_device_legacy);
++ return 0;
++}
++
++static void wifi_del_dev(void)
++{
++ DBG_871X("## Unregister platform_driver_register\n");
++ platform_driver_unregister(&wifi_device);
++ platform_driver_unregister(&wifi_device_legacy);
++}
++#endif /* defined(RTW_ENABLE_WIFI_CONTROL_FUNC) */
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/os_dep/linux/usb_intf.c linux-xbian-rpi/drivers/net/wireless/rtl8192cu/os_dep/linux/usb_intf.c
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/os_dep/linux/usb_intf.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/os_dep/linux/usb_intf.c 2015-07-28 01:20:58.433199136 +0200
+@@ -0,0 +1,1655 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#define _HCI_INTF_C_
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++#include <recv_osdep.h>
++#include <xmit_osdep.h>
++#include <hal_intf.h>
++#include <rtw_version.h>
++
++#ifndef CONFIG_USB_HCI
++
++#error "CONFIG_USB_HCI shall be on!\n"
++
++#endif
++
++#include <usb_vendor_req.h>
++#include <usb_ops.h>
++#include <usb_osintf.h>
++#include <usb_hal.h>
++#ifdef CONFIG_PLATFORM_RTK_DMP
++#include <asm/io.h>
++#endif
++
++#if defined (PLATFORM_LINUX) && defined (PLATFORM_WINDOWS)
++
++#error "Shall be Linux or Windows, but not both!\n"
++
++#endif
++
++#ifdef CONFIG_80211N_HT
++extern int rtw_ht_enable;
++extern int rtw_cbw40_enable;
++extern int rtw_ampdu_enable;//for enable tx_ampdu
++#endif
++
++#ifdef CONFIG_GLOBAL_UI_PID
++int ui_pid[3] = {0, 0, 0};
++#endif
++
++
++extern int pm_netdev_open(struct net_device *pnetdev,u8 bnormal);
++static int rtw_suspend(struct usb_interface *intf, pm_message_t message);
++static int rtw_resume(struct usb_interface *intf);
++int rtw_resume_process(_adapter *padapter);
++
++
++static int rtw_drv_init(struct usb_interface *pusb_intf,const struct usb_device_id *pdid);
++static void rtw_dev_remove(struct usb_interface *pusb_intf);
++
++#define USB_VENDER_ID_REALTEK 0x0BDA
++
++/* DID_USB_v915_20121224 */
++#define RTL8192C_USB_IDS \
++ /*=== Realtek demoboard ===*/ \
++ {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x8191)},/* Default ID */ \
++ /****** 8188CUS ********/ \
++ {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x8176)},/* 8188cu 1*1 dongole */ \
++ {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x8170)},/* 8188CE-VAU USB minCard */ \
++ {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x817E)},/* 8188CE-VAU USB minCard */ \
++ {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x817A)},/* 8188cu Slim Solo */ \
++ {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x817B)},/* 8188cu Slim Combo */ \
++ {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x817D)},/* 8188RU High-power USB Dongle */ \
++ {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x8754)},/* 8188 Combo for BC4 */ \
++ {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x817F)},/* 8188RU */ \
++ {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x818A)},/* RTL8188CUS-VL */ \
++ {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x018A)},/* RTL8188CTV */ \
++ {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x17C0)}, /* RTK demoboard - USB-N10E */ \
++ /****** 8192CUS ********/ \
++ {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x8177)},/* 8191cu 1*2 */ \
++ {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x8178)},/* 8192cu 2*2 */ \
++ {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x817C)},/* 8192CE-VAU USB minCard */ \
++ {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x8191)},/* 8192CU 2*2 */ \
++ {USB_DEVICE(0x1058, 0x0631)},/* Alpha, 8192CU */ \
++ /*=== Customer ID ===*/ \
++ /****** 8188CUS Dongle ********/ \
++ {USB_DEVICE(0x2019, 0xED17)},/* PCI - Edimax */ \
++ {USB_DEVICE(0x0DF6, 0x0052)},/* Sitecom - Edimax */ \
++ {USB_DEVICE(0x7392, 0x7811)},/* Edimax - Edimax */ \
++ {USB_DEVICE(0x07B8, 0x8189)},/* Abocom - Abocom */ \
++ {USB_DEVICE(0x0EB0, 0x9071)},/* NO Brand - Etop */ \
++ {USB_DEVICE(0x06F8, 0xE033)},/* Hercules - Edimax */ \
++ {USB_DEVICE(0x103C, 0x1629)},/* HP - Lite-On ,8188CUS Slim Combo */ \
++ {USB_DEVICE(0x2001, 0x3308)},/* D-Link - Alpha */ \
++ {USB_DEVICE(0x050D, 0x1102)},/* Belkin - Edimax */ \
++ {USB_DEVICE(0x2019, 0xAB2A)},/* Planex - Abocom */ \
++ {USB_DEVICE(0x20F4, 0x648B)},/* TRENDnet - Cameo */ \
++ {USB_DEVICE(0x4855, 0x0090)},/* - Feixun */ \
++ {USB_DEVICE(0x13D3, 0x3357)},/* - AzureWave */ \
++ {USB_DEVICE(0x0DF6, 0x005C)},/* Sitecom - Edimax */ \
++ {USB_DEVICE(0x0BDA, 0x5088)},/* Thinkware - CC&C */ \
++ {USB_DEVICE(0x4856, 0x0091)},/* NetweeN - Feixun */ \
++ {USB_DEVICE(0x0846, 0x9041)}, /* Netgear - Cameo */ \
++ {USB_DEVICE(0x2019, 0x4902)},/* Planex - Etop */ \
++ {USB_DEVICE(0x2019, 0xAB2E)},/* SW-WF02-AD15 -Abocom */ \
++ {USB_DEVICE(0x2001, 0x330B)}, /* D-LINK - T&W */ \
++ {USB_DEVICE(0xCDAB, 0x8010)}, /* - - compare */ \
++ {USB_DEVICE(0x0B05, 0x17BA)}, /* ASUS - Edimax */ \
++ {USB_DEVICE(0x0BDA, 0x1E1E)}, /* Intel - - */ \
++ {USB_DEVICE(0x04BB, 0x094c)}, /* I-O DATA - Edimax */ \
++ /****** 8188CTV ********/ \
++ {USB_DEVICE(0xCDAB, 0x8011)}, /* - - compare */ \
++ {USB_DEVICE(0x0BDA, 0x0A8A)}, /* Sony - Foxconn */ \
++ /****** 8188 RU ********/ \
++ {USB_DEVICE(0x0BDA, 0x317F)},/* Netcore,Netcore */ \
++ /****** 8188CE-VAU ********/ \
++ {USB_DEVICE(0x13D3, 0x3359)},/* - Azwave */ \
++ {USB_DEVICE(0x13D3, 0x3358)},/* - Azwave */ \
++ /****** 8188CUS Slim Solo********/ \
++ {USB_DEVICE(0x04F2, 0xAFF7)},/* XAVI - XAVI */ \
++ {USB_DEVICE(0x04F2, 0xAFF9)},/* XAVI - XAVI */ \
++ {USB_DEVICE(0x04F2, 0xAFFA)},/* XAVI - XAVI */ \
++ /****** 8188CUS Slim Combo ********/ \
++ {USB_DEVICE(0x04F2, 0xAFF8)},/* XAVI - XAVI */ \
++ {USB_DEVICE(0x04F2, 0xAFFB)},/* XAVI - XAVI */ \
++ {USB_DEVICE(0x04F2, 0xAFFC)},/* XAVI - XAVI */ \
++ {USB_DEVICE(0x2019, 0x1201)},/* Planex - Vencer */ \
++ /****** 8192CUS Dongle ********/ \
++ {USB_DEVICE(0x2001, 0x3307)},/* D-Link - Cameo */ \
++ {USB_DEVICE(0x2001, 0x330A)},/* D-Link - Alpha */ \
++ {USB_DEVICE(0x2001, 0x3309)},/* D-Link - Alpha */ \
++ {USB_DEVICE(0x2001, 0x330D)},/* D-Link - DWA 131 */ \
++ {USB_DEVICE(0x0586, 0x341F)},/* Zyxel - Abocom */ \
++ {USB_DEVICE(0x7392, 0x7822)},/* Edimax - Edimax */ \
++ {USB_DEVICE(0x2019, 0xAB2B)},/* Planex - Abocom */ \
++ {USB_DEVICE(0x07B8, 0x8178)},/* Abocom - Abocom */ \
++ {USB_DEVICE(0x07AA, 0x0056)},/* ATKK - Gemtek */ \
++ {USB_DEVICE(0x4855, 0x0091)},/* - Feixun */ \
++ {USB_DEVICE(0x050D, 0x2102)},/* Belkin - Sercomm */ \
++ {USB_DEVICE(0x050D, 0x2103)},/* Belkin - Edimax */ \
++ {USB_DEVICE(0x20F4, 0x624D)},/* TRENDnet */ \
++ {USB_DEVICE(0x0DF6, 0x0061)},/* Sitecom - Edimax */ \
++ {USB_DEVICE(0x0B05, 0x17AB)},/* ASUS - Edimax */ \
++ {USB_DEVICE(0x0846, 0x9021)},/* Netgear - Sercomm */ \
++ {USB_DEVICE(0x0846, 0xF001)}, /* Netgear - Sercomm */ \
++ {USB_DEVICE(0x0E66, 0x0019)},/* Hawking,Edimax */ \
++ {USB_DEVICE(0x0E66, 0x0020)}, /* Hawking - Edimax */ \
++ {USB_DEVICE(0x050D, 0x1004)}, /* Belkin - Edimax */ \
++ {USB_DEVICE(0x0BDA, 0x2E2E)}, /* Intel - - */ \
++ {USB_DEVICE(0x2357, 0x0100)}, /* TP-Link - TP-Link */ \
++ {USB_DEVICE(0x06F8, 0xE035)}, /* Hercules - Edimax */ \
++ {USB_DEVICE(0x04BB, 0x0950)}, /* IO-DATA - Edimax */ \
++ {USB_DEVICE(0x0DF6, 0x0070)}, /* Sitecom - Edimax */ \
++ {USB_DEVICE(0x0789, 0x016D)}, /* LOGITEC - Edimax */ \
++ /****** 8192CE-VAU ********/ \
++ {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x8186)},/* Intel-Xavi( Azwave) */
++
++#define RTL8192D_USB_IDS \
++ /*=== Realtek demoboard ===*/ \
++ /****** 8192DU ********/ \
++ {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x8193)},/* 8192DU-VC */ \
++ {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x8194)},/* 8192DU-VS */ \
++ {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x8111)},/* Realtek 5G dongle for WiFi Display */ \
++ {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x0193)},/* 8192DE-VAU */ \
++ {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x8171)},/* 8192DU-VC */ \
++ /*=== Customer ID ===*/ \
++ /****** 8192DU-VC ********/ \
++ {USB_DEVICE(0x2019, 0xAB2C)},/* PCI - Abocm */ \
++ {USB_DEVICE(0x2019, 0x4903)},/* PCI - ETOP */ \
++ {USB_DEVICE(0x2019, 0x4904)},/* PCI - ETOP */ \
++ {USB_DEVICE(0x07B8, 0x8193)},/* Abocom - Abocom */ \
++ /****** 8192DU-VS ********/ \
++ {USB_DEVICE(0x20F4, 0x664B)}, /* TRENDnet - Cameo */ \
++ {USB_DEVICE(0x04DD, 0x954F)}, /* Sharp */ \
++ {USB_DEVICE(0x04DD, 0x96A6)}, /* Sharp */ \
++ {USB_DEVICE(0x050D, 0x110A)}, /* Belkin - Edimax */ \
++ {USB_DEVICE(0x050D, 0x1105)}, /* Belkin - Edimax */ \
++ {USB_DEVICE(0x050D, 0x120A)}, /* Belkin - Edimax */ \
++ {USB_DEVICE(0x1668, 0x8102)}, /* - */ \
++ {USB_DEVICE(0x0BDA, 0xE194)}, /* - Edimax */ \
++ /****** 8192DU-WiFi Display Dongle ********/ \
++ {USB_DEVICE(0x2019, 0xAB2D)},/* Planex - Abocom ,5G dongle for WiFi Display */
++
++#ifndef CONFIG_RTL8192C
++ #undef RTL8192C_USB_IDS
++ #define RTL8192C_USB_IDS
++#endif
++#ifndef CONFIG_RTL8192D
++ #undef RTL8192D_USB_IDS
++ #define RTL8192D_USB_IDS
++#endif
++
++
++static struct usb_device_id rtw_usb_id_tbl[] ={
++ RTL8192C_USB_IDS
++ RTL8192D_USB_IDS
++ {} /* Terminating entry */
++};
++MODULE_DEVICE_TABLE(usb, rtw_usb_id_tbl);
++
++int const rtw_usb_id_len = sizeof(rtw_usb_id_tbl) / sizeof(struct usb_device_id);
++
++static struct specific_device_id specific_device_id_tbl[] = {
++ {.idVendor=USB_VENDER_ID_REALTEK, .idProduct=0x8177, .flags=SPEC_DEV_ID_DISABLE_HT},//8188cu 1*1 dongole, (b/g mode only)
++ {.idVendor=USB_VENDER_ID_REALTEK, .idProduct=0x817E, .flags=SPEC_DEV_ID_DISABLE_HT},//8188CE-VAU USB minCard (b/g mode only)
++ {.idVendor=0x0b05, .idProduct=0x1791, .flags=SPEC_DEV_ID_DISABLE_HT},
++ {.idVendor=0x13D3, .idProduct=0x3311, .flags=SPEC_DEV_ID_DISABLE_HT},
++ {.idVendor=0x13D3, .idProduct=0x3359, .flags=SPEC_DEV_ID_DISABLE_HT},//Russian customer -Azwave (8188CE-VAU g mode)
++#ifdef RTK_DMP_PLATFORM
++ {.idVendor=USB_VENDER_ID_REALTEK, .idProduct=0x8111, .flags=SPEC_DEV_ID_ASSIGN_IFNAME}, // Realtek 5G dongle for WiFi Display
++ {.idVendor=0x2019, .idProduct=0xAB2D, .flags=SPEC_DEV_ID_ASSIGN_IFNAME}, // PCI-Abocom 5G dongle for WiFi Display
++#endif /* RTK_DMP_PLATFORM */
++ {}
++};
++
++struct rtw_usb_drv {
++ struct usb_driver usbdrv;
++ int drv_registered;
++};
++
++static void rtw_dev_shutdown(struct device *dev)
++{
++ struct usb_interface *usb_intf = container_of(dev, struct usb_interface, dev);
++ struct dvobj_priv *dvobj = usb_get_intfdata(usb_intf);
++ _adapter *adapter = dvobj->if1;
++ int i;
++
++ DBG_871X("%s\n", __func__);
++
++ for (i = 0; i<dvobj->iface_nums; i++) {
++ adapter = dvobj->padapters[i];
++ adapter->bSurpriseRemoved = _TRUE;
++ }
++
++ ATOMIC_SET(&dvobj->continual_urb_error, MAX_CONTINUAL_URB_ERR+1);
++}
++
++#ifdef CONFIG_RTL8192C
++static struct usb_device_id rtl8192c_usb_id_tbl[] ={
++ RTL8192C_USB_IDS
++ {} /* Terminating entry */
++};
++
++struct rtw_usb_drv rtl8192c_usb_drv = {
++ .usbdrv.name = (char*)"rtl8192cu",
++ .usbdrv.probe = rtw_drv_init,
++ .usbdrv.disconnect = rtw_dev_remove,
++ .usbdrv.id_table = rtl8192c_usb_id_tbl,
++ .usbdrv.suspend = rtw_suspend,
++ .usbdrv.resume = rtw_resume,
++ #if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 22))
++ .usbdrv.reset_resume = rtw_resume,
++ #endif
++ #ifdef CONFIG_AUTOSUSPEND
++ .usbdrv.supports_autosuspend = 1,
++ #endif
++
++ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 19))
++ .usbdrv.drvwrap.driver.shutdown = rtw_dev_shutdown,
++ #else
++ .usbdrv.driver.shutdown = rtw_dev_shutdown,
++ #endif
++};
++
++static struct rtw_usb_drv *usb_drv = &rtl8192c_usb_drv;
++#endif /* CONFIG_RTL8192C */
++
++#ifdef CONFIG_RTL8192D
++static struct usb_device_id rtl8192d_usb_id_tbl[] ={
++ RTL8192D_USB_IDS
++ {} /* Terminating entry */
++};
++
++struct rtw_usb_drv rtl8192d_usb_drv = {
++ .usbdrv.name = (char*)"rtl8192du",
++ .usbdrv.probe = rtw_drv_init,
++ .usbdrv.disconnect = rtw_dev_remove,
++ .usbdrv.id_table = rtl8192d_usb_id_tbl,
++ .usbdrv.suspend = rtw_suspend,
++ .usbdrv.resume = rtw_resume,
++ #if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 22))
++ .usbdrv.reset_resume = rtw_resume,
++ #endif
++ #ifdef CONFIG_AUTOSUSPEND
++ .usbdrv.supports_autosuspend = 1,
++ #endif
++
++ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 19))
++ .usbdrv.drvwrap.driver.shutdown = rtw_dev_shutdown,
++ #else
++ .usbdrv.driver.shutdown = rtw_dev_shutdown,
++ #endif
++};
++static struct rtw_usb_drv *usb_drv = &rtl8192d_usb_drv;
++#endif /* CONFIG_RTL8192D */
++
++static inline int RT_usb_endpoint_dir_in(const struct usb_endpoint_descriptor *epd)
++{
++ return ((epd->bEndpointAddress & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN);
++}
++
++static inline int RT_usb_endpoint_dir_out(const struct usb_endpoint_descriptor *epd)
++{
++ return ((epd->bEndpointAddress & USB_ENDPOINT_DIR_MASK) == USB_DIR_OUT);
++}
++
++static inline int RT_usb_endpoint_xfer_int(const struct usb_endpoint_descriptor *epd)
++{
++ return ((epd->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT);
++}
++
++static inline int RT_usb_endpoint_xfer_bulk(const struct usb_endpoint_descriptor *epd)
++{
++ return ((epd->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK);
++}
++
++static inline int RT_usb_endpoint_is_bulk_in(const struct usb_endpoint_descriptor *epd)
++{
++ return (RT_usb_endpoint_xfer_bulk(epd) && RT_usb_endpoint_dir_in(epd));
++}
++
++static inline int RT_usb_endpoint_is_bulk_out(const struct usb_endpoint_descriptor *epd)
++{
++ return (RT_usb_endpoint_xfer_bulk(epd) && RT_usb_endpoint_dir_out(epd));
++}
++
++static inline int RT_usb_endpoint_is_int_in(const struct usb_endpoint_descriptor *epd)
++{
++ return (RT_usb_endpoint_xfer_int(epd) && RT_usb_endpoint_dir_in(epd));
++}
++
++static inline int RT_usb_endpoint_num(const struct usb_endpoint_descriptor *epd)
++{
++ return epd->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
++}
++
++static u8 rtw_init_intf_priv(struct dvobj_priv *dvobj)
++{
++ u8 rst = _SUCCESS;
++
++ #ifdef CONFIG_USB_VENDOR_REQ_MUTEX
++ _rtw_mutex_init(&dvobj->usb_vendor_req_mutex);
++ #endif
++
++
++ #ifdef CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC
++ dvobj->usb_alloc_vendor_req_buf = rtw_zmalloc(MAX_USB_IO_CTL_SIZE);
++ if (dvobj->usb_alloc_vendor_req_buf == NULL) {
++ DBG_871X("alloc usb_vendor_req_buf failed... /n");
++ rst = _FAIL;
++ goto exit;
++ }
++ dvobj->usb_vendor_req_buf =
++ (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(dvobj->usb_alloc_vendor_req_buf ), ALIGNMENT_UNIT);
++exit:
++ #endif
++
++ return rst;
++
++}
++
++static u8 rtw_deinit_intf_priv(struct dvobj_priv *dvobj)
++{
++ u8 rst = _SUCCESS;
++
++ #ifdef CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC
++ if(dvobj->usb_vendor_req_buf)
++ rtw_mfree(dvobj->usb_alloc_vendor_req_buf, MAX_USB_IO_CTL_SIZE);
++ #endif
++
++ #ifdef CONFIG_USB_VENDOR_REQ_MUTEX
++ _rtw_mutex_free(&dvobj->usb_vendor_req_mutex);
++ #endif
++
++ return rst;
++}
++
++static struct dvobj_priv *usb_dvobj_init(struct usb_interface *usb_intf)
++{
++ int i;
++ u8 val8;
++ int status = _FAIL;
++ struct dvobj_priv *pdvobjpriv = NULL;
++ struct usb_device *pusbd;
++ struct usb_device_descriptor *pdev_desc;
++ struct usb_host_config *phost_conf;
++ struct usb_config_descriptor *pconf_desc;
++ struct usb_host_interface *phost_iface;
++ struct usb_interface_descriptor *piface_desc;
++ struct usb_host_endpoint *phost_endp;
++ struct usb_endpoint_descriptor *pendp_desc;
++
++_func_enter_;
++
++ if((pdvobjpriv = devobj_init()) == NULL) {
++ goto exit;
++ }
++
++ pdvobjpriv->pusbintf = usb_intf ;
++ pusbd = pdvobjpriv->pusbdev = interface_to_usbdev(usb_intf);
++ usb_set_intfdata(usb_intf, pdvobjpriv);
++
++ pdvobjpriv->RtNumInPipes = 0;
++ pdvobjpriv->RtNumOutPipes = 0;
++
++
++ pdev_desc = &pusbd->descriptor;
++#if 0
++ DBG_871X("\n8712_usb_device_descriptor:\n");
++ DBG_871X("bLength=%x\n", pdev_desc->bLength);
++ DBG_871X("bDescriptorType=%x\n", pdev_desc->bDescriptorType);
++ DBG_871X("bcdUSB=%x\n", pdev_desc->bcdUSB);
++ DBG_871X("bDeviceClass=%x\n", pdev_desc->bDeviceClass);
++ DBG_871X("bDeviceSubClass=%x\n", pdev_desc->bDeviceSubClass);
++ DBG_871X("bDeviceProtocol=%x\n", pdev_desc->bDeviceProtocol);
++ DBG_871X("bMaxPacketSize0=%x\n", pdev_desc->bMaxPacketSize0);
++ DBG_871X("idVendor=%x\n", pdev_desc->idVendor);
++ DBG_871X("idProduct=%x\n", pdev_desc->idProduct);
++ DBG_871X("bcdDevice=%x\n", pdev_desc->bcdDevice);
++ DBG_871X("iManufacturer=%x\n", pdev_desc->iManufacturer);
++ DBG_871X("iProduct=%x\n", pdev_desc->iProduct);
++ DBG_871X("iSerialNumber=%x\n", pdev_desc->iSerialNumber);
++ DBG_871X("bNumConfigurations=%x\n", pdev_desc->bNumConfigurations);
++#endif
++
++ phost_conf = pusbd->actconfig;
++ pconf_desc = &phost_conf->desc;
++
++#if 0
++ DBG_871X("\n8712_usb_configuration_descriptor:\n");
++ DBG_871X("bLength=%x\n", pconf_desc->bLength);
++ DBG_871X("bDescriptorType=%x\n", pconf_desc->bDescriptorType);
++ DBG_871X("wTotalLength=%x\n", pconf_desc->wTotalLength);
++ DBG_871X("bNumInterfaces=%x\n", pconf_desc->bNumInterfaces);
++ DBG_871X("bConfigurationValue=%x\n", pconf_desc->bConfigurationValue);
++ DBG_871X("iConfiguration=%x\n", pconf_desc->iConfiguration);
++ DBG_871X("bmAttributes=%x\n", pconf_desc->bmAttributes);
++ DBG_871X("bMaxPower=%x\n", pconf_desc->bMaxPower);
++#endif
++
++ //DBG_871X("\n/****** num of altsetting = (%d) ******/\n", usb_intf->num_altsetting);
++
++ phost_iface = &usb_intf->altsetting[0];
++ piface_desc = &phost_iface->desc;
++
++#if 0
++ DBG_871X("\n8712_usb_interface_descriptor:\n");
++ DBG_871X("bLength=%x\n", piface_desc->bLength);
++ DBG_871X("bDescriptorType=%x\n", piface_desc->bDescriptorType);
++ DBG_871X("bInterfaceNumber=%x\n", piface_desc->bInterfaceNumber);
++ DBG_871X("bAlternateSetting=%x\n", piface_desc->bAlternateSetting);
++ DBG_871X("bNumEndpoints=%x\n", piface_desc->bNumEndpoints);
++ DBG_871X("bInterfaceClass=%x\n", piface_desc->bInterfaceClass);
++ DBG_871X("bInterfaceSubClass=%x\n", piface_desc->bInterfaceSubClass);
++ DBG_871X("bInterfaceProtocol=%x\n", piface_desc->bInterfaceProtocol);
++ DBG_871X("iInterface=%x\n", piface_desc->iInterface);
++#endif
++
++ pdvobjpriv->NumInterfaces = pconf_desc->bNumInterfaces;
++ pdvobjpriv->InterfaceNumber = piface_desc->bInterfaceNumber;
++ pdvobjpriv->nr_endpoint = piface_desc->bNumEndpoints;
++
++ //DBG_871X("\ndump usb_endpoint_descriptor:\n");
++
++ for (i = 0; i < pdvobjpriv->nr_endpoint; i++)
++ {
++ phost_endp = phost_iface->endpoint + i;
++ if (phost_endp)
++ {
++ pendp_desc = &phost_endp->desc;
++
++ DBG_871X("\nusb_endpoint_descriptor(%d):\n", i);
++ DBG_871X("bLength=%x\n",pendp_desc->bLength);
++ DBG_871X("bDescriptorType=%x\n",pendp_desc->bDescriptorType);
++ DBG_871X("bEndpointAddress=%x\n",pendp_desc->bEndpointAddress);
++ //DBG_871X("bmAttributes=%x\n",pendp_desc->bmAttributes);
++ //DBG_871X("wMaxPacketSize=%x\n",pendp_desc->wMaxPacketSize);
++ DBG_871X("wMaxPacketSize=%x\n",le16_to_cpu(pendp_desc->wMaxPacketSize));
++ DBG_871X("bInterval=%x\n",pendp_desc->bInterval);
++ //DBG_871X("bRefresh=%x\n",pendp_desc->bRefresh);
++ //DBG_871X("bSynchAddress=%x\n",pendp_desc->bSynchAddress);
++
++ if (RT_usb_endpoint_is_bulk_in(pendp_desc))
++ {
++ DBG_871X("RT_usb_endpoint_is_bulk_in = %x\n", RT_usb_endpoint_num(pendp_desc));
++ pdvobjpriv->RtNumInPipes++;
++ }
++ else if (RT_usb_endpoint_is_int_in(pendp_desc))
++ {
++ DBG_871X("RT_usb_endpoint_is_int_in = %x, Interval = %x\n", RT_usb_endpoint_num(pendp_desc),pendp_desc->bInterval);
++ pdvobjpriv->RtNumInPipes++;
++ }
++ else if (RT_usb_endpoint_is_bulk_out(pendp_desc))
++ {
++ DBG_871X("RT_usb_endpoint_is_bulk_out = %x\n", RT_usb_endpoint_num(pendp_desc));
++ pdvobjpriv->RtNumOutPipes++;
++ }
++ pdvobjpriv->ep_num[i] = RT_usb_endpoint_num(pendp_desc);
++ }
++ }
++
++ DBG_871X("nr_endpoint=%d, in_num=%d, out_num=%d\n\n", pdvobjpriv->nr_endpoint, pdvobjpriv->RtNumInPipes, pdvobjpriv->RtNumOutPipes);
++
++ if (pusbd->speed == USB_SPEED_HIGH) {
++ pdvobjpriv->ishighspeed = _TRUE;
++ DBG_871X("USB_SPEED_HIGH\n");
++ } else {
++ pdvobjpriv->ishighspeed = _FALSE;
++ DBG_871X("NON USB_SPEED_HIGH\n");
++ }
++
++ if (rtw_init_intf_priv(pdvobjpriv) == _FAIL) {
++ RT_TRACE(_module_os_intfs_c_,_drv_err_,("\n Can't INIT rtw_init_intf_priv\n"));
++ goto free_dvobj;
++ }
++
++ //.3 misc
++ _rtw_init_sema(&(pdvobjpriv->usb_suspend_sema), 0);
++
++ rtw_reset_continual_urb_error(pdvobjpriv);
++
++ usb_get_dev(pusbd);
++
++ //DBG_871X("%s %d\n", __func__, ATOMIC_READ(&usb_intf->dev.kobj.kref.refcount));
++
++ status = _SUCCESS;
++
++free_dvobj:
++ if (status != _SUCCESS && pdvobjpriv) {
++ usb_set_intfdata(usb_intf, NULL);
++ devobj_deinit(pdvobjpriv);
++ pdvobjpriv = NULL;
++ }
++exit:
++_func_exit_;
++ return pdvobjpriv;
++}
++
++static void usb_dvobj_deinit(struct usb_interface *usb_intf)
++{
++ struct dvobj_priv *dvobj = usb_get_intfdata(usb_intf);
++
++_func_enter_;
++
++ usb_set_intfdata(usb_intf, NULL);
++ if (dvobj) {
++ //Modify condition for 92DU DMDP 2010.11.18, by Thomas
++ /*if ((dvobj->NumInterfaces == 1)
++ || ((dvobj->InterfaceNumber == 1) && (dvobj->DualMacMode == _TRUE))) {
++ if (interface_to_usbdev(usb_intf)->state != USB_STATE_NOTATTACHED) {
++ //If we didn't unplug usb dongle and remove/insert modlue, driver fails on sitesurvey for the first time when device is up .
++ //Reset usb port for sitesurvey fail issue. 2009.8.13, by Thomas
++ DBG_871X("usb attached..., try to reset usb device\n");
++ usb_reset_device(interface_to_usbdev(usb_intf));
++ }
++ }*/
++ rtw_deinit_intf_priv(dvobj);
++ devobj_deinit(dvobj);
++ }
++
++ //DBG_871X("%s %d\n", __func__, ATOMIC_READ(&usb_intf->dev.kobj.kref.refcount));
++ usb_put_dev(interface_to_usbdev(usb_intf));
++
++_func_exit_;
++}
++
++static void decide_chip_type_by_usb_device_id(_adapter *padapter, const struct usb_device_id *pdid)
++{
++ padapter->chip_type = NULL_CHIP_TYPE;
++#ifdef CONFIG_RTL8192C
++ padapter->chip_type = RTL8188C_8192C;
++ padapter->HardwareType = HARDWARE_TYPE_RTL8192CU;
++ DBG_871X("CHIP TYPE: RTL8188C_8192C\n");
++#endif
++
++#ifdef CONFIG_RTL8192D
++ padapter->chip_type = RTL8192D;
++ padapter->HardwareType = HARDWARE_TYPE_RTL8192DU;
++ DBG_871X("CHIP TYPE: RTL8192D\n");
++#endif
++}
++
++static void usb_intf_start(_adapter *padapter)
++{
++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("+usb_intf_start\n"));
++ rtw_hal_inirp_init(padapter);
++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("-usb_intf_start\n"));
++}
++
++static void usb_intf_stop(_adapter *padapter)
++{
++
++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("+usb_intf_stop\n"));
++
++ //disabel_hw_interrupt
++ if(padapter->bSurpriseRemoved == _FALSE)
++ {
++ //device still exists, so driver can do i/o operation
++ //TODO:
++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("SurpriseRemoved==_FALSE\n"));
++ }
++
++ //cancel in irp
++ rtw_hal_inirp_deinit(padapter);
++
++ //cancel out irp
++ rtw_write_port_cancel(padapter);
++
++ //todo:cancel other irps
++
++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("-usb_intf_stop\n"));
++
++}
++
++static void rtw_dev_unload(_adapter *padapter)
++{
++ struct net_device *pnetdev= (struct net_device*)padapter->pnetdev;
++ u8 val8;
++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("+rtw_dev_unload\n"));
++
++ if(padapter->bup == _TRUE)
++ {
++ DBG_871X("===> rtw_dev_unload\n");
++
++ padapter->bDriverStopped = _TRUE;
++ #ifdef CONFIG_XMIT_ACK
++ if (padapter->xmitpriv.ack_tx)
++ rtw_ack_tx_done(&padapter->xmitpriv, RTW_SCTX_DONE_DRV_STOP);
++ #endif
++
++ //s3.
++ if(padapter->intf_stop)
++ {
++ padapter->intf_stop(padapter);
++ }
++
++ //s4.
++ if(!padapter->pwrctrlpriv.bInternalAutoSuspend )
++ rtw_stop_drv_threads(padapter);
++
++
++ //s5.
++ if(padapter->bSurpriseRemoved == _FALSE)
++ {
++ //DBG_871X("r871x_dev_unload()->rtl871x_hal_deinit()\n");
++#ifdef CONFIG_WOWLAN
++ if((padapter->pwrctrlpriv.bSupportRemoteWakeup==_TRUE)&&(padapter->pwrctrlpriv.wowlan_mode==_TRUE)){
++ DBG_871X("%s bSupportWakeOnWlan==_TRUE do not run rtw_hal_deinit()\n",__FUNCTION__);
++ }
++ else
++#endif //CONFIG_WOWLAN
++ {
++ rtw_hal_deinit(padapter);
++ }
++ padapter->bSurpriseRemoved = _TRUE;
++ }
++
++ padapter->bup = _FALSE;
++#ifdef CONFIG_WOWLAN
++ padapter->hw_init_completed=_FALSE;
++#endif //CONFIG_WOWLAN
++ }
++ else
++ {
++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("r871x_dev_unload():padapter->bup == _FALSE\n" ));
++ }
++
++ DBG_871X("<=== rtw_dev_unload\n");
++
++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("-rtw_dev_unload\n"));
++
++}
++
++static void process_spec_devid(const struct usb_device_id *pdid)
++{
++ u16 vid, pid;
++ u32 flags;
++ int i;
++ int num = sizeof(specific_device_id_tbl)/sizeof(struct specific_device_id);
++
++ for(i=0; i<num; i++)
++ {
++ vid = specific_device_id_tbl[i].idVendor;
++ pid = specific_device_id_tbl[i].idProduct;
++ flags = specific_device_id_tbl[i].flags;
++
++#ifdef CONFIG_80211N_HT
++ if((pdid->idVendor==vid) && (pdid->idProduct==pid) && (flags&SPEC_DEV_ID_DISABLE_HT))
++ {
++ rtw_ht_enable = 0;
++ rtw_cbw40_enable = 0;
++ rtw_ampdu_enable = 0;
++ }
++#endif
++
++#ifdef RTK_DMP_PLATFORM
++ // Change the ifname to wlan10 when PC side WFD dongle plugin on DMP platform.
++ // It is used to distinguish between normal and PC-side wifi dongle/module.
++ if((pdid->idVendor==vid) && (pdid->idProduct==pid) && (flags&SPEC_DEV_ID_ASSIGN_IFNAME))
++ {
++ extern char* ifname;
++ strncpy(ifname, "wlan10", 6);
++ //DBG_871X("%s()-%d: ifname=%s, vid=%04X, pid=%04X\n", __FUNCTION__, __LINE__, ifname, vid, pid);
++ }
++#endif /* RTK_DMP_PLATFORM */
++
++ }
++}
++
++#ifdef SUPPORT_HW_RFOFF_DETECTED
++int rtw_hw_suspend(_adapter *padapter )
++{
++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
++ struct usb_interface *pusb_intf = adapter_to_dvobj(padapter)->pusbintf;
++ struct net_device *pnetdev = padapter->pnetdev;
++
++ _func_enter_;
++
++ if((!padapter->bup) || (padapter->bDriverStopped)||(padapter->bSurpriseRemoved))
++ {
++ DBG_871X("padapter->bup=%d bDriverStopped=%d bSurpriseRemoved = %d\n",
++ padapter->bup, padapter->bDriverStopped,padapter->bSurpriseRemoved);
++ goto error_exit;
++ }
++
++ if(padapter)//system suspend
++ {
++ LeaveAllPowerSaveMode(padapter);
++
++ DBG_871X("==> rtw_hw_suspend\n");
++ _enter_pwrlock(&pwrpriv->lock);
++ pwrpriv->bips_processing = _TRUE;
++ //padapter->net_closed = _TRUE;
++ //s1.
++ if(pnetdev)
++ {
++ netif_carrier_off(pnetdev);
++ rtw_netif_stop_queue(pnetdev);
++ }
++
++ //s2.
++ rtw_disassoc_cmd(padapter, 500, _FALSE);
++
++ //s2-2. indicate disconnect to os
++ //rtw_indicate_disconnect(padapter);
++ {
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++
++ if(check_fwstate(pmlmepriv, _FW_LINKED))
++ {
++ _clr_fwstate_(pmlmepriv, _FW_LINKED);
++
++ rtw_led_control(padapter, LED_CTL_NO_LINK);
++
++ rtw_os_indicate_disconnect(padapter);
++
++ #ifdef CONFIG_LPS
++ //donnot enqueue cmd
++ rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_DISCONNECT, 0);
++ #endif
++ }
++
++ }
++ //s2-3.
++ rtw_free_assoc_resources(padapter, 1);
++
++ //s2-4.
++ rtw_free_network_queue(padapter,_TRUE);
++ #ifdef CONFIG_IPS
++ rtw_ips_dev_unload(padapter);
++ #endif
++ pwrpriv->rf_pwrstate = rf_off;
++ pwrpriv->bips_processing = _FALSE;
++
++ _exit_pwrlock(&pwrpriv->lock);
++ }
++ else
++ goto error_exit;
++
++ _func_exit_;
++ return 0;
++
++error_exit:
++ DBG_871X("%s, failed \n",__FUNCTION__);
++ return (-1);
++
++}
++
++int rtw_hw_resume(_adapter *padapter)
++{
++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
++ struct usb_interface *pusb_intf = adapter_to_dvobj(padapter)->pusbintf;
++ struct net_device *pnetdev = padapter->pnetdev;
++
++ _func_enter_;
++
++ if(padapter)//system resume
++ {
++ DBG_871X("==> rtw_hw_resume\n");
++ _enter_pwrlock(&pwrpriv->lock);
++ pwrpriv->bips_processing = _TRUE;
++ rtw_reset_drv_sw(padapter);
++
++ if(pm_netdev_open(pnetdev,_FALSE) != 0)
++ {
++ _exit_pwrlock(&pwrpriv->lock);
++ goto error_exit;
++ }
++
++ netif_device_attach(pnetdev);
++ netif_carrier_on(pnetdev);
++
++ if(!rtw_netif_queue_stopped(pnetdev))
++ rtw_netif_start_queue(pnetdev);
++ else
++ rtw_netif_wake_queue(pnetdev);
++
++ pwrpriv->bkeepfwalive = _FALSE;
++ pwrpriv->brfoffbyhw = _FALSE;
++
++ pwrpriv->rf_pwrstate = rf_on;
++ pwrpriv->bips_processing = _FALSE;
++
++ _exit_pwrlock(&pwrpriv->lock);
++ }
++ else
++ {
++ goto error_exit;
++ }
++
++ _func_exit_;
++
++ return 0;
++error_exit:
++ DBG_871X("%s, Open net dev failed \n",__FUNCTION__);
++ return (-1);
++}
++#endif
++
++static int rtw_suspend(struct usb_interface *pusb_intf, pm_message_t message)
++{
++ struct dvobj_priv *dvobj = usb_get_intfdata(pusb_intf);
++ _adapter *padapter = dvobj->if1;
++ struct net_device *pnetdev = padapter->pnetdev;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
++ struct usb_device *usb_dev = interface_to_usbdev(pusb_intf);
++#ifdef CONFIG_WOWLAN
++ struct wowlan_ioctl_param poidparam;
++#endif // CONFIG_WOWLAN
++ int ret = 0;
++ u32 start_time = rtw_get_current_time();
++ _func_enter_;
++
++ DBG_871X("==> %s (%s:%d)\n",__FUNCTION__, current->comm, current->pid);
++
++ if((!padapter->bup) || (padapter->bDriverStopped)||(padapter->bSurpriseRemoved))
++ {
++ DBG_871X("padapter->bup=%d bDriverStopped=%d bSurpriseRemoved = %d\n",
++ padapter->bup, padapter->bDriverStopped,padapter->bSurpriseRemoved);
++ goto exit;
++ }
++
++ if(pwrpriv->bInternalAutoSuspend )
++ {
++ #ifdef CONFIG_AUTOSUSPEND
++ #ifdef SUPPORT_HW_RFOFF_DETECTED
++ // The FW command register update must after MAC and FW init ready.
++ if((padapter->bFWReady) && ( padapter->pwrctrlpriv.bHWPwrPindetect ) && (padapter->registrypriv.usbss_enable ))
++ {
++ u8 bOpen = _TRUE;
++ rtw_interface_ps_func(padapter,HAL_USB_SELECT_SUSPEND,&bOpen);
++ //rtl8192c_set_FwSelectSuspend_cmd(padapter,_TRUE ,500);//note fw to support hw power down ping detect
++ }
++ #endif
++ #endif
++ }
++ pwrpriv->bInSuspend = _TRUE;
++ rtw_cancel_all_timer(padapter);
++ LeaveAllPowerSaveMode(padapter);
++
++ rtw_stop_cmd_thread(padapter);
++
++ _enter_pwrlock(&pwrpriv->lock);
++ //padapter->net_closed = _TRUE;
++ //s1.
++ if(pnetdev)
++ {
++ netif_carrier_off(pnetdev);
++ rtw_netif_stop_queue(pnetdev);
++ }
++#ifdef CONFIG_WOWLAN
++ if(padapter->pwrctrlpriv.bSupportRemoteWakeup==_TRUE&&padapter->pwrctrlpriv.wowlan_mode==_TRUE){
++ u8 ps_mode=PS_MODE_MIN;
++ //set H2C command
++ poidparam.subcode=WOWLAN_ENABLE;
++ rtw_hal_set_hwreg(padapter,HW_VAR_WOWLAN,(u8 *)&poidparam);
++ //rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_PWRMODE, &ps_mode);
++ //rtw_set_rpwm(padapter, PS_STATE_S2);
++ }
++ else
++#endif //CONFIG_WOWLAN
++ {
++ //s2.
++ rtw_disassoc_cmd(padapter, 0, _FALSE);
++ }
++
++#ifdef CONFIG_LAYER2_ROAMING_RESUME
++ if(check_fwstate(pmlmepriv, WIFI_STATION_STATE) && check_fwstate(pmlmepriv, _FW_LINKED) )
++ {
++ //printk("%s:%d assoc_ssid:%s\n", __FUNCTION__, __LINE__, pmlmepriv->assoc_ssid.Ssid);
++ DBG_871X("%s:%d %s(" MAC_FMT "), length:%d assoc_ssid.length:%d\n",__FUNCTION__, __LINE__,
++ pmlmepriv->cur_network.network.Ssid.Ssid,
++ MAC_ARG(pmlmepriv->cur_network.network.MacAddress),
++ pmlmepriv->cur_network.network.Ssid.SsidLength,
++ pmlmepriv->assoc_ssid.SsidLength);
++ rtw_set_roaming(padapter, 1);
++ }
++#endif
++ //s2-2. indicate disconnect to os
++ rtw_indicate_disconnect(padapter);
++ //s2-3.
++ rtw_free_assoc_resources(padapter, 1);
++#ifdef CONFIG_AUTOSUSPEND
++ if(!pwrpriv->bInternalAutoSuspend )
++#endif
++ //s2-4.
++ rtw_free_network_queue(padapter, _TRUE);
++
++ rtw_dev_unload(padapter);
++#ifdef CONFIG_AUTOSUSPEND
++ pwrpriv->rf_pwrstate = rf_off;
++ pwrpriv->bips_processing = _FALSE;
++#endif
++ _exit_pwrlock(&pwrpriv->lock);
++
++ if(check_fwstate(pmlmepriv, _FW_UNDER_SURVEY))
++ rtw_indicate_scan_done(padapter, 1);
++
++ if(check_fwstate(pmlmepriv, _FW_UNDER_LINKING))
++ rtw_indicate_disconnect(padapter);
++
++exit:
++ DBG_871X("<=== %s return %d.............. in %dms\n", __FUNCTION__
++ , ret, rtw_get_passing_time_ms(start_time));
++
++ _func_exit_;
++ return ret;
++}
++
++static int rtw_resume(struct usb_interface *pusb_intf)
++{
++ struct dvobj_priv *dvobj = usb_get_intfdata(pusb_intf);
++ _adapter *padapter = dvobj->if1;
++ struct net_device *pnetdev = padapter->pnetdev;
++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
++ int ret = 0;
++
++ if(pwrpriv->bInternalAutoSuspend ){
++ ret = rtw_resume_process(padapter);
++ } else {
++#ifdef CONFIG_RESUME_IN_WORKQUEUE
++ rtw_resume_in_workqueue(pwrpriv);
++#else
++ if (rtw_is_earlysuspend_registered(pwrpriv)
++ #ifdef CONFIG_WOWLAN
++ && !padapter->pwrctrlpriv.wowlan_mode
++ #endif /* CONFIG_WOWLAN */
++ ) {
++ /* jeff: bypass resume here, do in late_resume */
++ rtw_set_do_late_resume(pwrpriv, _TRUE);
++ } else {
++ ret = rtw_resume_process(padapter);
++ }
++#endif /* CONFIG_RESUME_IN_WORKQUEUE */
++ }
++
++ return ret;
++
++}
++
++int rtw_resume_process(_adapter *padapter)
++{
++ struct net_device *pnetdev;
++ struct pwrctrl_priv *pwrpriv;
++ int ret = -1;
++ u32 start_time = rtw_get_current_time();
++ _func_enter_;
++
++ DBG_871X("==> %s (%s:%d)\n",__FUNCTION__, current->comm, current->pid);
++
++ if(padapter) {
++ pnetdev= padapter->pnetdev;
++ pwrpriv = &padapter->pwrctrlpriv;
++ } else {
++ goto exit;
++ }
++
++ _enter_pwrlock(&pwrpriv->lock);
++ rtw_reset_drv_sw(padapter);
++ pwrpriv->bkeepfwalive = _FALSE;
++
++ DBG_871X("bkeepfwalive(%x)\n",pwrpriv->bkeepfwalive);
++ if(pm_netdev_open(pnetdev,_TRUE) != 0) {
++ _exit_pwrlock(&pwrpriv->lock);
++ goto exit;
++ }
++
++ netif_device_attach(pnetdev);
++ netif_carrier_on(pnetdev);
++
++#ifdef CONFIG_AUTOSUSPEND
++ if(pwrpriv->bInternalAutoSuspend )
++ {
++ #ifdef CONFIG_AUTOSUSPEND
++ #ifdef SUPPORT_HW_RFOFF_DETECTED
++ // The FW command register update must after MAC and FW init ready.
++ if((padapter->bFWReady) && ( padapter->pwrctrlpriv.bHWPwrPindetect ) && (padapter->registrypriv.usbss_enable ))
++ {
++ //rtl8192c_set_FwSelectSuspend_cmd(padapter,_FALSE ,500);//note fw to support hw power down ping detect
++ u8 bOpen = _FALSE;
++ rtw_interface_ps_func(padapter,HAL_USB_SELECT_SUSPEND,&bOpen);
++ }
++ #endif
++ #endif
++
++ pwrpriv->bInternalAutoSuspend = _FALSE;
++ pwrpriv->brfoffbyhw = _FALSE;
++ }
++#endif
++ _exit_pwrlock(&pwrpriv->lock);
++
++ if( padapter->pid[1]!=0) {
++ DBG_871X("pid[1]:%d\n",padapter->pid[1]);
++ rtw_signal_process(padapter->pid[1], SIGUSR2);
++ }
++
++ #ifdef CONFIG_LAYER2_ROAMING_RESUME
++ rtw_roaming(padapter, NULL);
++ #endif
++
++ ret = 0;
++exit:
++ #ifdef CONFIG_RESUME_IN_WORKQUEUE
++ rtw_unlock_suspend();
++ #endif //CONFIG_RESUME_IN_WORKQUEUE
++
++ pwrpriv->bInSuspend = _FALSE;
++ DBG_871X("<=== %s return %d.............. in %dms\n", __FUNCTION__
++ , ret, rtw_get_passing_time_ms(start_time));
++
++ _func_exit_;
++
++ return ret;
++}
++
++#ifdef CONFIG_AUTOSUSPEND
++void autosuspend_enter(_adapter* padapter)
++{
++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
++ struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++
++ pwrpriv->bInternalAutoSuspend = _TRUE;
++ pwrpriv->bips_processing = _TRUE;
++
++ DBG_871X("==>autosuspend_enter...........\n");
++
++ if(rf_off == pwrpriv->change_rfpwrstate )
++ {
++ #if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,35))
++ usb_enable_autosuspend(dvobj->pusbdev);
++ #else
++ dvobj->pusbdev->autosuspend_disabled = 0;//autosuspend disabled by the user
++ #endif
++
++ #if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,33))
++ usb_autopm_put_interface(dvobj->pusbintf);
++ #elif (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,20))
++ usb_autopm_enable(dvobj->pusbintf);
++ #else
++ usb_autosuspend_device(dvobj->pusbdev, 1);
++ #endif
++ }
++ #if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,32))
++ DBG_871X("...pm_usage_cnt(%d).....\n", atomic_read(&(dvobj->pusbintf->pm_usage_cnt)));
++ #else
++ DBG_871X("...pm_usage_cnt(%d).....\n", dvobj->pusbintf->pm_usage_cnt);
++ #endif
++
++}
++int autoresume_enter(_adapter* padapter)
++{
++ int result = _SUCCESS;
++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
++ struct security_priv* psecuritypriv=&(padapter->securitypriv);
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++
++
++ DBG_871X("====> autoresume_enter \n");
++
++ if(rf_off == pwrpriv->rf_pwrstate )
++ {
++ pwrpriv->ps_flag = _FALSE;
++ #if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,33))
++ if (usb_autopm_get_interface(dvobj->pusbintf) < 0)
++ {
++ DBG_871X( "can't get autopm: %d\n", result);
++ result = _FAIL;
++ goto error_exit;
++ }
++ #elif (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,20))
++ usb_autopm_disable(dvobj->pusbintf);
++ #else
++ usb_autoresume_device(dvobj->pusbdev, 1);
++ #endif
++
++ #if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,32))
++ DBG_871X("...pm_usage_cnt(%d).....\n", atomic_read(&(dvobj->pusbintf->pm_usage_cnt)));
++ #else
++ DBG_871X("...pm_usage_cnt(%d).....\n", dvobj->pusbintf->pm_usage_cnt);
++ #endif
++ }
++ DBG_871X("<==== autoresume_enter \n");
++error_exit:
++
++ return result;
++}
++#endif
++
++#ifdef CONFIG_PLATFORM_RTD2880B
++extern void rtd2885_wlan_netlink_sendMsg(char *action_string, char *name);
++#endif
++
++#ifdef CONFIG_PLATFORM_ARM_SUNxI
++#include <mach/sys_config.h>
++extern int sw_usb_disable_hcd(__u32 usbc_no);
++extern int sw_usb_enable_hcd(__u32 usbc_no);
++static int usb_wifi_host = 2;
++#endif
++
++#ifdef CONFIG_PLATFORM_ARM_SUN6I
++#include <mach/sys_config.h>
++extern int sw_usb_disable_hcd(__u32 usbc_no);
++extern int sw_usb_enable_hcd(__u32 usbc_no);
++extern void wifi_pm_power(int on);
++static script_item_u item;
++#endif
++
++_adapter *rtw_usb_if1_init(struct dvobj_priv *dvobj,
++ struct usb_interface *pusb_intf, const struct usb_device_id *pdid)
++{
++ _adapter *padapter = NULL;
++ struct net_device *pnetdev = NULL;
++ int status = _FAIL;
++
++ if ((padapter = (_adapter *)rtw_zvmalloc(sizeof(*padapter))) == NULL) {
++ goto exit;
++ }
++ padapter->dvobj = dvobj;
++ dvobj->if1 = padapter;
++
++ padapter->bDriverStopped=_TRUE;
++
++ dvobj->padapters[dvobj->iface_nums++] = padapter;
++ padapter->iface_id = IFACE_ID0;
++
++#if defined(CONFIG_CONCURRENT_MODE) || defined(CONFIG_DUALMAC_CONCURRENT)
++ //set adapter_type/iface type for primary padapter
++ padapter->isprimary = _TRUE;
++ padapter->adapter_type = PRIMARY_ADAPTER;
++ #ifndef CONFIG_HWPORT_SWAP
++ padapter->iface_type = IFACE_PORT0;
++ #else
++ padapter->iface_type = IFACE_PORT1;
++ #endif
++#endif
++
++ #ifndef RTW_DVOBJ_CHIP_HW_TYPE
++ //step 1-1., decide the chip_type via vid/pid
++ padapter->interface_type = RTW_USB;
++ decide_chip_type_by_usb_device_id(padapter, pdid);
++ #endif
++
++ if((pnetdev = rtw_init_netdev(padapter)) == NULL) {
++ goto free_adapter;
++ }
++ SET_NETDEV_DEV(pnetdev, dvobj_to_dev(dvobj));
++ padapter = rtw_netdev_priv(pnetdev);
++
++ //step 2. hook HalFunc, allocate HalData
++ if(padapter->chip_type == RTL8188C_8192C) {
++ #ifdef CONFIG_RTL8192C
++ rtl8192cu_set_hal_ops(padapter);
++ #endif
++ } else if(padapter->chip_type == RTL8192D) {
++ #ifdef CONFIG_RTL8192D
++ rtl8192du_set_hal_ops(padapter);
++ #endif
++ } else {
++ DBG_871X("Detect NULL_CHIP_TYPE\n");
++ goto free_hal_data;
++ }
++
++ //step 3.
++ padapter->intf_start=&usb_intf_start;
++ padapter->intf_stop=&usb_intf_stop;
++
++ //.2
++ if ((rtw_init_io_priv(padapter, usb_set_intf_ops)) == _FAIL) {
++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,(" \n Can't init io_reqs\n"));
++ goto free_hal_data;
++ }
++
++ rtw_hal_read_chip_version(padapter);
++
++ //.4 usb endpoint mapping
++ rtw_hal_chip_configure(padapter);
++
++ //step 4. read efuse/eeprom data and get mac_addr
++ rtw_hal_read_chip_info(padapter);
++
++ if (rtw_handle_dualmac(padapter, 1) != _SUCCESS)
++ goto free_hal_data;
++
++#ifdef CONFIG_IOCTL_CFG80211
++ if(rtw_wdev_alloc(padapter, dvobj_to_dev(dvobj)) != 0) {
++ goto handle_dualmac;
++ }
++#endif
++
++ //step 5.
++ if (rtw_init_drv_sw(padapter) == _FAIL) {
++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("Initialize driver software resource Failed!\n"));
++ goto free_wdev;
++ }
++
++#ifdef CONFIG_PM
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,18))
++ if(padapter->pwrctrlpriv.bSupportRemoteWakeup)
++ {
++ dvobj->pusbdev->do_remote_wakeup=1;
++ pusb_intf->needs_remote_wakeup = 1;
++ device_init_wakeup(&pusb_intf->dev, 1);
++ DBG_871X("\n padapter->pwrctrlpriv.bSupportRemoteWakeup~~~~~~\n");
++ DBG_871X("\n padapter->pwrctrlpriv.bSupportRemoteWakeup~~~[%d]~~~\n",device_may_wakeup(&pusb_intf->dev));
++ }
++#endif
++#endif
++
++#ifdef CONFIG_AUTOSUSPEND
++ if( padapter->registrypriv.power_mgnt != PS_MODE_ACTIVE )
++ {
++ if(padapter->registrypriv.usbss_enable ){ /* autosuspend (2s delay) */
++ #if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,38))
++ dvobj->pusbdev->dev.power.autosuspend_delay = 0 * HZ;//15 * HZ; idle-delay time
++ #else
++ dvobj->pusbdev->autosuspend_delay = 0 * HZ;//15 * HZ; idle-delay time
++ #endif
++
++ #if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,35))
++ usb_enable_autosuspend(dvobj->pusbdev);
++ #elif (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,22) && LINUX_VERSION_CODE<=KERNEL_VERSION(2,6,34))
++ padapter->bDisableAutosuspend = dvobj->pusbdev->autosuspend_disabled ;
++ dvobj->pusbdev->autosuspend_disabled = 0;//autosuspend disabled by the user
++ #endif
++
++ usb_autopm_get_interface(dvobj->pusbintf );//init pm_usage_cnt ,let it start from 1
++
++ #if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,32))
++ DBG_871X("%s...pm_usage_cnt(%d).....\n",__FUNCTION__, atomic_read(&(dvobj->pusbintf ->pm_usage_cnt)));
++ #else
++ DBG_871X("%s...pm_usage_cnt(%d).....\n",__FUNCTION__, dvobj->pusbintf ->pm_usage_cnt);
++ #endif
++ }
++ }
++#endif
++
++ // set mac addr
++ rtw_macaddr_cfg(padapter->eeprompriv.mac_addr);
++ rtw_init_wifidirect_addrs(padapter, padapter->eeprompriv.mac_addr, padapter->eeprompriv.mac_addr);
++
++ DBG_871X("bDriverStopped:%d, bSurpriseRemoved:%d, bup:%d, hw_init_completed:%d\n"
++ ,padapter->bDriverStopped
++ ,padapter->bSurpriseRemoved
++ ,padapter->bup
++ ,padapter->hw_init_completed
++ );
++
++ status = _SUCCESS;
++
++free_wdev:
++ if(status != _SUCCESS) {
++ #ifdef CONFIG_IOCTL_CFG80211
++ rtw_wdev_unregister(padapter->rtw_wdev);
++ rtw_wdev_free(padapter->rtw_wdev);
++ #endif
++ }
++handle_dualmac:
++ if (status != _SUCCESS)
++ rtw_handle_dualmac(padapter, 0);
++free_hal_data:
++ if(status != _SUCCESS && padapter->HalData)
++ rtw_mfree(padapter->HalData, sizeof(*(padapter->HalData)));
++free_adapter:
++ if (status != _SUCCESS) {
++ if (pnetdev)
++ rtw_free_netdev(pnetdev);
++ else if (padapter)
++ rtw_vmfree((u8*)padapter, sizeof(*padapter));
++ padapter = NULL;
++ }
++exit:
++ return padapter;
++}
++
++static void rtw_usb_if1_deinit(_adapter *if1)
++{
++ struct net_device *pnetdev = if1->pnetdev;
++ struct mlme_priv *pmlmepriv= &if1->mlmepriv;
++
++ if(check_fwstate(pmlmepriv, _FW_LINKED))
++ rtw_disassoc_cmd(if1, 0, _FALSE);
++
++#ifdef CONFIG_AP_MODE
++ free_mlme_ap_info(if1);
++ #ifdef CONFIG_HOSTAPD_MLME
++ hostapd_mode_unload(if1);
++ #endif
++#endif
++
++ rtw_cancel_all_timer(if1);
++#ifdef CONFIG_WOWLAN
++ if1->pwrctrlpriv.wowlan_mode=_FALSE;
++#endif //CONFIG_WOWLAN
++ rtw_dev_unload(if1);
++
++ DBG_871X("%s, hw_init_completed=%d\n", __func__, if1->hw_init_completed);
++
++ //s6.
++ rtw_handle_dualmac(if1, 0);
++
++#ifdef CONFIG_IOCTL_CFG80211
++ if (if1->rtw_wdev)
++ rtw_wdev_free(if1->rtw_wdev);
++#endif //CONFIG_IOCTL_CFG80211
++
++ rtw_free_drv_sw(if1);
++
++ if(pnetdev)
++ rtw_free_netdev(pnetdev);
++
++#ifdef CONFIG_PLATFORM_RTD2880B
++ DBG_871X("wlan link down\n");
++ rtd2885_wlan_netlink_sendMsg("linkdown", "8712");
++#endif
++
++}
++
++/*
++ * drv_init() - a device potentially for us
++ *
++ * notes: drv_init() is called when the bus driver has located a card for us to support.
++ * We accept the new device by returning 0.
++*/
++
++_adapter *rtw_sw_export = NULL;
++
++static int rtw_drv_init(struct usb_interface *pusb_intf, const struct usb_device_id *did)
++{
++ int i;
++ uint status = _FAIL;
++ _adapter *if1 = NULL, *if2 = NULL;
++ struct dvobj_priv *dvobj = NULL;
++
++
++ RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("+rtw_drv_init\n"));
++
++
++ //step 0.
++ process_spec_devid(did);
++
++ /* Initialize dvobj_priv */
++ if ((dvobj = usb_dvobj_init(pusb_intf)) == NULL) {
++ RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("initialize device object priv Failed!\n"));
++ goto exit;
++ }
++
++ /* Initialize if1 */
++ if ((if1 = rtw_usb_if1_init(dvobj, pusb_intf, did)) == NULL) {
++ DBG_871X("rtw_usb_if1_init Failed!\n");
++ goto free_dvobj;
++ }
++
++ /* Initialize if2 */
++#ifdef CONFIG_CONCURRENT_MODE
++ if((if2 = rtw_drv_if2_init(if1, usb_set_intf_ops)) == NULL) {
++ goto free_if1;
++ }
++#ifdef CONFIG_MULTI_VIR_IFACES
++ for(i=0; i<if1->registrypriv.ext_iface_num;i++)
++ {
++ if(rtw_drv_add_vir_if(if1, usb_set_intf_ops) == NULL)
++ {
++ DBG_871X("rtw_drv_add_iface failed! (%d)\n", i);
++ goto free_if1;
++ }
++ }
++#endif //CONFIG_MULTI_VIR_IFACES
++#endif
++
++#ifdef CONFIG_INTEL_PROXIM
++ rtw_sw_export=if1;
++#endif
++
++#ifdef CONFIG_GLOBAL_UI_PID
++ if (ui_pid[1]!=0) {
++ DBG_871X("ui_pid[1]:%d\n",ui_pid[1]);
++ rtw_signal_process(ui_pid[1], SIGUSR2);
++ }
++#endif
++
++ //dev_alloc_name && register_netdev
++ if((status = rtw_drv_register_netdev(if1)) != _SUCCESS) {
++ goto free_if1;
++ }
++
++#ifdef CONFIG_HOSTAPD_MLME
++ hostapd_mode_init(if1);
++#endif
++
++#ifdef CONFIG_PLATFORM_RTD2880B
++ DBG_871X("wlan link up\n");
++ rtd2885_wlan_netlink_sendMsg("linkup", "8712");
++#endif
++
++#ifdef RTK_DMP_PLATFORM
++ rtw_proc_init_one(if1->pnetdev);
++#endif
++
++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("-871x_drv - drv_init, success!\n"));
++
++ status = _SUCCESS;
++
++free_if1:
++ if (status != _SUCCESS && if1) {
++ rtw_usb_if1_deinit(if1);
++ }
++free_dvobj:
++ if (status != _SUCCESS)
++ usb_dvobj_deinit(pusb_intf);
++exit:
++ return status == _SUCCESS?0:-ENODEV;
++}
++
++/*
++ * dev_remove() - our device is being removed
++*/
++//rmmod module & unplug(SurpriseRemoved) will call r871xu_dev_remove() => how to recognize both
++static void rtw_dev_remove(struct usb_interface *pusb_intf)
++{
++ struct dvobj_priv *dvobj = usb_get_intfdata(pusb_intf);
++ _adapter *padapter = dvobj->if1;
++
++_func_exit_;
++
++ DBG_871X("+rtw_dev_remove\n");
++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("+dev_remove()\n"));
++
++ dvobj->processing_dev_remove = _TRUE;
++
++ rtw_unregister_netdevs(dvobj);
++
++ if(usb_drv->drv_registered == _TRUE)
++ {
++ //DBG_871X("r871xu_dev_remove():padapter->bSurpriseRemoved == _TRUE\n");
++ padapter->bSurpriseRemoved = _TRUE;
++ }
++ /*else
++ {
++ //DBG_871X("r871xu_dev_remove():module removed\n");
++ padapter->hw_init_completed = _FALSE;
++ }*/
++
++#if defined(CONFIG_HAS_EARLYSUSPEND) || defined(CONFIG_ANDROID_POWER)
++ rtw_unregister_early_suspend(&padapter->pwrctrlpriv);
++#endif
++
++ rtw_pm_set_ips(padapter, IPS_NONE);
++ rtw_pm_set_lps(padapter, PS_MODE_ACTIVE);
++
++ LeaveAllPowerSaveMode(padapter);
++
++#ifdef CONFIG_CONCURRENT_MODE
++#ifdef CONFIG_MULTI_VIR_IFACES
++ rtw_drv_stop_vir_ifaces(dvobj);
++#endif //CONFIG_MULTI_VIR_IFACES
++ rtw_drv_if2_stop(dvobj->if2);
++#endif //CONFIG_CONCURRENT_MODE
++
++ rtw_usb_if1_deinit(padapter);
++
++#ifdef CONFIG_CONCURRENT_MODE
++#ifdef CONFIG_MULTI_VIR_IFACES
++ rtw_drv_free_vir_ifaces(dvobj);
++#endif //CONFIG_MULTI_VIR_IFACES
++ rtw_drv_if2_free(dvobj->if2);
++#endif //CONFIG_CONCURRENT_MODE
++
++ usb_dvobj_deinit(pusb_intf);
++
++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("-dev_remove()\n"));
++ DBG_871X("-r871xu_dev_remove, done\n");
++
++
++#ifdef CONFIG_INTEL_PROXIM
++ rtw_sw_export=NULL;
++#endif
++
++_func_exit_;
++
++ return;
++
++}
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24))
++extern int console_suspend_enabled;
++#endif
++
++static int __init rtw_drv_entry(void)
++{
++#ifdef CONFIG_PLATFORM_RTK_DMP
++ u32 tmp;
++ tmp=readl((volatile unsigned int*)0xb801a608);
++ tmp &= 0xffffff00;
++ tmp |= 0x55;
++ writel(tmp,(volatile unsigned int*)0xb801a608);//write dummy register for 1055
++#endif
++#ifdef CONFIG_PLATFORM_ARM_SUNxI
++#ifndef CONFIG_RTL8723A
++ int ret = 0;
++ /* ----------get usb_wifi_usbc_num------------- */
++ ret = script_parser_fetch("usb_wifi_para", "usb_wifi_usbc_num", (int *)&usb_wifi_host, 64);
++ if(ret != 0){
++ printk("ERR: script_parser_fetch usb_wifi_usbc_num failed\n");
++ ret = -ENOMEM;
++ return ret;
++ }
++ printk("sw_usb_enable_hcd: usbc_num = %d\n", usb_wifi_host);
++ sw_usb_enable_hcd(usb_wifi_host);
++#endif //CONFIG_RTL8723A
++#endif //CONFIG_PLATFORM_ARM_SUNxI
++
++#ifdef CONFIG_PLATFORM_ARM_SUN6I
++ script_item_value_type_e type;
++
++ type = script_get_item("wifi_para", "wifi_usbc_id", &item);
++ if(SCIRPT_ITEM_VALUE_TYPE_INT != type){
++ printk("ERR: script_get_item wifi_usbc_id failed\n");
++ return -ENOMEM;
++ }
++
++ printk("sw_usb_enable_hcd: usbc_num = %d\n", item.val);
++ wifi_pm_power(1);
++ mdelay(10);
++ sw_usb_enable_hcd(item.val);
++#endif //CONFIG_PLATFORM_ARM_SUN6I
++
++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("+rtw_drv_entry\n"));
++
++ DBG_871X(DRV_NAME " driver version=%s\n", DRIVERVERSION);
++ DBG_871X("build time: %s %s\n", __DATE__, __TIME__);
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24))
++ //console_suspend_enabled=0;
++#endif
++
++ rtw_suspend_lock_init();
++
++ usb_drv->drv_registered = _TRUE;
++ return usb_register(&usb_drv->usbdrv);
++}
++
++static void __exit rtw_drv_halt(void)
++{
++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("+rtw_drv_halt\n"));
++ DBG_871X("+rtw_drv_halt\n");
++
++ usb_drv->drv_registered = _FALSE;
++ usb_deregister(&usb_drv->usbdrv);
++
++#ifdef CONFIG_PLATFORM_ARM_SUNxI
++#ifndef CONFIG_RTL8723A
++ printk("sw_usb_disable_hcd: usbc_num = %d\n", usb_wifi_host);
++ sw_usb_disable_hcd(usb_wifi_host);
++#endif //ifndef CONFIG_RTL8723A
++#endif //CONFIG_PLATFORM_ARM_SUNxI
++#ifdef CONFIG_PLATFORM_ARM_SUN6I
++ sw_usb_disable_hcd(item.val);
++ wifi_pm_power(0);
++#endif
++
++ rtw_suspend_lock_uninit();
++ DBG_871X("-rtw_drv_halt\n");
++
++ rtw_mstat_dump();
++}
++
++
++module_init(rtw_drv_entry);
++module_exit(rtw_drv_halt);
++
++#ifdef CONFIG_WOWLAN
++#ifdef CONFIG_WOWLAN_MANUAL
++
++int rtw_resume_toshiba(PADAPTER Adapter)
++{
++ struct dvobj_priv *pdvobjpriv;
++ pdvobjpriv = adapter_to_dvobj(Adapter);
++
++ rtw_resume(pdvobjpriv->pusbintf);
++ return 0;
++}
++
++int rtw_suspend_toshiba(PADAPTER Adapter)
++{
++ pm_message_t msg;
++ struct dvobj_priv *pdvobjpriv;
++ pdvobjpriv = adapter_to_dvobj(Adapter);
++ msg.event=0;
++ //for Toshiba only, they should call rtw_suspend before suspend
++ rtw_suspend(pdvobjpriv->pusbintf, msg);
++ return 0;
++}
++EXPORT_SYMBOL(rtw_suspend_toshiba);
++EXPORT_SYMBOL(rtw_resume_toshiba);
++#endif //CONFIG_WOWLAN_MANUAL
++#endif //CONFIG_WOWLAN
++
++#ifdef CONFIG_INTEL_PROXIM
++_adapter *rtw_usb_get_sw_pointer(void)
++{
++ return rtw_sw_export;
++}
++EXPORT_SYMBOL(rtw_usb_get_sw_pointer);
++#endif //CONFIG_INTEL_PROXIM
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/os_dep/linux/usb_ops_linux.c linux-xbian-rpi/drivers/net/wireless/rtl8192cu/os_dep/linux/usb_ops_linux.c
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/os_dep/linux/usb_ops_linux.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/os_dep/linux/usb_ops_linux.c 2015-07-28 01:20:58.433199136 +0200
+@@ -0,0 +1,648 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *******************************************************************************/
++#define _USB_OPS_LINUX_C_
++
++#include <drv_types.h>
++#include <usb_ops_linux.h>
++#include <rtw_sreset.h>
++
++#ifdef CONFIG_USB_SUPPORT_ASYNC_VDN_REQ
++static void _usbctrl_vendorreq_async_callback(struct urb *urb, struct pt_regs *regs)
++{
++ if (urb) {
++ if (urb->context) {
++ rtw_mfree(urb->context);
++ }
++ usb_free_urb(urb);
++ }
++}
++
++static int _usbctrl_vendorreq_async_write(struct usb_device *udev, u8 request,
++ u16 value, u16 index, void *pdata, u16 len, u8 requesttype)
++{
++ int rc;
++ unsigned int pipe;
++ u8 reqtype;
++ struct usb_ctrlrequest *dr;
++ struct urb *urb;
++ struct rtl819x_async_write_data {
++ u8 data[VENDOR_CMD_MAX_DATA_LEN];
++ struct usb_ctrlrequest dr;
++ } *buf;
++
++
++ if (requesttype == VENDOR_READ) {
++ pipe = usb_rcvctrlpipe(udev, 0);//read_in
++ reqtype = REALTEK_USB_VENQT_READ;
++ }
++ else {
++ pipe = usb_sndctrlpipe(udev, 0);//write_out
++ reqtype = REALTEK_USB_VENQT_WRITE;
++ }
++
++ buf = (struct rtl819x_async_write_data *)rtw_zmalloc(sizeof(*buf));
++ if (!buf) {
++ rc = -ENOMEM;
++ goto exit;
++ }
++
++ urb = usb_alloc_urb(0, GFP_ATOMIC);
++ if (!urb) {
++ rtw_mfree((u8*)buf, sizeof(*buf));
++ rc = -ENOMEM;
++ goto exit;
++ }
++
++ dr = &buf->dr;
++
++ dr->bRequestType = reqtype;
++ dr->bRequest = request;
++ dr->wValue = cpu_to_le16(value);
++ dr->wIndex = cpu_to_le16(index);
++ dr->wLength = cpu_to_le16(len);
++
++ _rtw_memcpy(buf, pdata, len);
++
++ usb_fill_control_urb(urb, udev, pipe, (unsigned char *)dr, buf, len,
++ _usbctrl_vendorreq_async_callback, buf);
++
++ rc = usb_submit_urb(urb, GFP_ATOMIC);
++ if (rc < 0) {
++ rtw_mfree((u8*)buf, sizeof(*buf));
++ usb_free_urb(urb);
++ }
++
++exit:
++ return rc;
++}
++
++int usb_write_async(struct usb_device *udev, u32 addr, void *pdata, u16 len)
++{
++ u8 request;
++ u8 requesttype;
++ u16 wvalue;
++ u16 index;
++
++ int ret;
++
++ requesttype = VENDOR_WRITE;//write_out
++ request = REALTEK_USB_VENQT_CMD_REQ;
++ index = REALTEK_USB_VENQT_CMD_IDX;//n/a
++
++ wvalue = (u16)(addr&0x0000ffff);
++
++ ret = _usbctrl_vendorreq_async_write(udev, request, wvalue, index, pdata, len, requesttype);
++
++ return ret;
++}
++
++int usb_async_write8(struct intf_hdl *pintfhdl, u32 addr, u8 val)
++{
++ u8 data;
++ int ret;
++ struct dvobj_priv *pdvobjpriv = (struct dvobj_priv *)pintfhdl->pintf_dev;
++ struct usb_device *udev=pdvobjpriv->pusbdev;
++
++ _func_enter_;
++ data = val;
++ ret = usb_write_async(udev, addr, &data, 1);
++ _func_exit_;
++
++ return ret;
++}
++
++int usb_async_write16(struct intf_hdl *pintfhdl, u32 addr, u16 val)
++{
++ u16 data;
++ int ret;
++ struct dvobj_priv *pdvobjpriv = (struct dvobj_priv *)pintfhdl->pintf_dev;
++ struct usb_device *udev=pdvobjpriv->pusbdev;
++
++ _func_enter_;
++ data = val;
++ ret = usb_write_async(udev, addr, &data, 2);
++ _func_exit_;
++
++ return ret;
++}
++
++int usb_async_write32(struct intf_hdl *pintfhdl, u32 addr, u32 val)
++{
++ u32 data;
++ int ret;
++ struct dvobj_priv *pdvobjpriv = (struct dvobj_priv *)pintfhdl->pintf_dev;
++ struct usb_device *udev=pdvobjpriv->pusbdev;
++
++ _func_enter_;
++ data = val;
++ ret = usb_write_async(udev, addr, &data, 4);
++ _func_exit_;
++
++ return ret;
++}
++#endif /* CONFIG_USB_SUPPORT_ASYNC_VDN_REQ */
++
++unsigned int ffaddr2pipehdl(struct dvobj_priv *pdvobj, u32 addr)
++{
++ unsigned int pipe=0;
++ int ep_num=0;
++ _adapter *padapter = pdvobj->if1;
++ struct usb_device *pusbd = pdvobj->pusbdev;
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++
++ if (addr == RECV_BULK_IN_ADDR) {
++ pipe=usb_rcvbulkpipe(pusbd, pHalData->RtBulkInPipe);
++
++ } else if (addr == RECV_INT_IN_ADDR) {
++ pipe=usb_rcvbulkpipe(pusbd, pHalData->RtIntInPipe);
++
++ } else if (addr < HW_QUEUE_ENTRY) {
++ ep_num = pHalData->Queue2EPNum[addr];
++ pipe = usb_sndbulkpipe(pusbd, ep_num);
++ }
++
++ return pipe;
++}
++
++struct zero_bulkout_context{
++ void *pbuf;
++ void *purb;
++ void *pirp;
++ void *padapter;
++};
++
++static void usb_bulkout_zero_complete(struct urb *purb, struct pt_regs *regs)
++{
++ struct zero_bulkout_context *pcontext = (struct zero_bulkout_context *)purb->context;
++
++ //DBG_8192C("+usb_bulkout_zero_complete\n");
++
++ if(pcontext)
++ {
++ if(pcontext->pbuf)
++ {
++ rtw_mfree(pcontext->pbuf, sizeof(int));
++ }
++
++ if(pcontext->purb && (pcontext->purb==purb))
++ {
++ usb_free_urb(pcontext->purb);
++ }
++
++
++ rtw_mfree((u8*)pcontext, sizeof(struct zero_bulkout_context));
++ }
++
++
++}
++
++static u32 usb_bulkout_zero(struct intf_hdl *pintfhdl, u32 addr)
++{
++ int pipe, status, len;
++ u32 ret;
++ unsigned char *pbuf;
++ struct zero_bulkout_context *pcontext;
++ PURB purb = NULL;
++ _adapter *padapter = (_adapter *)pintfhdl->padapter;
++ struct dvobj_priv *pdvobj = adapter_to_dvobj(padapter);
++ struct usb_device *pusbd = pdvobj->pusbdev;
++
++ //DBG_871X("%s\n", __func__);
++
++
++ if((padapter->bDriverStopped) || (padapter->bSurpriseRemoved) ||(padapter->pwrctrlpriv.pnp_bstop_trx))
++ {
++ return _FAIL;
++ }
++
++
++ pcontext = (struct zero_bulkout_context *)rtw_zmalloc(sizeof(struct zero_bulkout_context));
++
++ pbuf = (unsigned char *)rtw_zmalloc(sizeof(int));
++ purb = usb_alloc_urb(0, GFP_ATOMIC);
++
++ len = 0;
++ pcontext->pbuf = pbuf;
++ pcontext->purb = purb;
++ pcontext->pirp = NULL;
++ pcontext->padapter = padapter;
++
++
++ //translate DMA FIFO addr to pipehandle
++ //pipe = ffaddr2pipehdl(pdvobj, addr);
++
++ usb_fill_bulk_urb(purb, pusbd, pipe,
++ pbuf,
++ len,
++ usb_bulkout_zero_complete,
++ pcontext);//context is pcontext
++
++ status = usb_submit_urb(purb, GFP_ATOMIC);
++
++ if (!status)
++ {
++ ret= _SUCCESS;
++ }
++ else
++ {
++ ret= _FAIL;
++ }
++
++
++ return _SUCCESS;
++
++}
++
++void usb_read_mem(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem)
++{
++
++}
++
++void usb_write_mem(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *wmem)
++{
++
++}
++
++
++void usb_read_port_cancel(struct intf_hdl *pintfhdl)
++{
++ int i;
++ struct recv_buf *precvbuf;
++ _adapter *padapter = pintfhdl->padapter;
++ precvbuf = (struct recv_buf *)padapter->recvpriv.precv_buf;
++
++ DBG_871X("%s\n", __func__);
++
++ padapter->bReadPortCancel = _TRUE;
++
++ for (i=0; i < NR_RECVBUFF ; i++) {
++
++ precvbuf->reuse = _TRUE;
++ if (precvbuf->purb) {
++ //DBG_8192C("usb_read_port_cancel : usb_kill_urb \n");
++ usb_kill_urb(precvbuf->purb);
++ }
++ precvbuf++;
++ }
++
++#ifdef CONFIG_USB_INTERRUPT_IN_PIPE
++ usb_kill_urb(padapter->recvpriv.int_in_urb);
++#endif
++}
++
++static void usb_write_port_complete(struct urb *purb, struct pt_regs *regs)
++{
++ _irqL irqL;
++ int i;
++ struct xmit_buf *pxmitbuf = (struct xmit_buf *)purb->context;
++ //struct xmit_frame *pxmitframe = (struct xmit_frame *)pxmitbuf->priv_data;
++ //_adapter *padapter = pxmitframe->padapter;
++ _adapter *padapter = pxmitbuf->padapter;
++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++ //struct pkt_attrib *pattrib = &pxmitframe->attrib;
++
++_func_enter_;
++
++ switch(pxmitbuf->flags)
++ {
++ case VO_QUEUE_INX:
++ pxmitpriv->voq_cnt--;
++ break;
++ case VI_QUEUE_INX:
++ pxmitpriv->viq_cnt--;
++ break;
++ case BE_QUEUE_INX:
++ pxmitpriv->beq_cnt--;
++ break;
++ case BK_QUEUE_INX:
++ pxmitpriv->bkq_cnt--;
++ break;
++ case HIGH_QUEUE_INX:
++#ifdef CONFIG_AP_MODE
++ rtw_chk_hi_queue_cmd(padapter);
++#endif
++ break;
++ default:
++ break;
++ }
++
++
++/*
++ _enter_critical(&pxmitpriv->lock, &irqL);
++
++ pxmitpriv->txirp_cnt--;
++
++ switch(pattrib->priority)
++ {
++ case 1:
++ case 2:
++ pxmitpriv->bkq_cnt--;
++ //DBG_8192C("pxmitpriv->bkq_cnt=%d\n", pxmitpriv->bkq_cnt);
++ break;
++ case 4:
++ case 5:
++ pxmitpriv->viq_cnt--;
++ //DBG_8192C("pxmitpriv->viq_cnt=%d\n", pxmitpriv->viq_cnt);
++ break;
++ case 6:
++ case 7:
++ pxmitpriv->voq_cnt--;
++ //DBG_8192C("pxmitpriv->voq_cnt=%d\n", pxmitpriv->voq_cnt);
++ break;
++ case 0:
++ case 3:
++ default:
++ pxmitpriv->beq_cnt--;
++ //DBG_8192C("pxmitpriv->beq_cnt=%d\n", pxmitpriv->beq_cnt);
++ break;
++
++ }
++
++ _exit_critical(&pxmitpriv->lock, &irqL);
++
++
++ if(pxmitpriv->txirp_cnt==0)
++ {
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_write_port_complete: txirp_cnt== 0, set allrxreturnevt!\n"));
++ _rtw_up_sema(&(pxmitpriv->tx_retevt));
++ }
++*/
++ //rtw_free_xmitframe(pxmitpriv, pxmitframe);
++
++ if(padapter->bSurpriseRemoved || padapter->bDriverStopped ||padapter->bWritePortCancel)
++ {
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_write_port_complete:bDriverStopped(%d) OR bSurpriseRemoved(%d)", padapter->bDriverStopped, padapter->bSurpriseRemoved));
++ DBG_8192C("%s(): TX Warning! bDriverStopped(%d) OR bSurpriseRemoved(%d) bWritePortCancel(%d) pxmitbuf->ext_tag(%x) \n",
++ __FUNCTION__,padapter->bDriverStopped, padapter->bSurpriseRemoved,padapter->bReadPortCancel,pxmitbuf->ext_tag);
++
++ goto check_completion;
++ }
++
++
++ if (purb->status==0) {
++
++ } else {
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_write_port_complete : purb->status(%d) != 0 \n", purb->status));
++ DBG_871X("###=> urb_write_port_complete status(%d)\n",purb->status);
++ if((purb->status==-EPIPE)||(purb->status==-EPROTO))
++ {
++ //usb_clear_halt(pusbdev, purb->pipe);
++ //msleep(10);
++ sreset_set_wifi_error_status(padapter, USB_WRITE_PORT_FAIL);
++ } else if (purb->status == -EINPROGRESS) {
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_write_port_complete: EINPROGESS\n"));
++ goto check_completion;
++
++ } else if (purb->status == -ENOENT) {
++ DBG_871X("%s: -ENOENT\n", __func__);
++ goto check_completion;
++
++ } else if (purb->status == -ECONNRESET) {
++ DBG_871X("%s: -ECONNRESET\n", __func__);
++ goto check_completion;
++
++ } else if (purb->status == -ESHUTDOWN) {
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_write_port_complete: ESHUTDOWN\n"));
++ padapter->bDriverStopped=_TRUE;
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_write_port_complete:bDriverStopped=TRUE\n"));
++
++ goto check_completion;
++ }
++ else
++ {
++ padapter->bSurpriseRemoved=_TRUE;
++ DBG_8192C("bSurpriseRemoved=TRUE\n");
++ //rtl8192cu_trigger_gpio_0(padapter);
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_write_port_complete:bSurpriseRemoved=TRUE\n"));
++
++ goto check_completion;
++ }
++ }
++
++ #ifdef DBG_CONFIG_ERROR_DETECT
++ {
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++ pHalData->srestpriv.last_tx_complete_time = rtw_get_current_time();
++ }
++ #endif
++
++check_completion:
++ _enter_critical(&pxmitpriv->lock_sctx, &irqL);
++ rtw_sctx_done_err(&pxmitbuf->sctx,
++ purb->status ? RTW_SCTX_DONE_WRITE_PORT_ERR : RTW_SCTX_DONE_SUCCESS);
++ _exit_critical(&pxmitpriv->lock_sctx, &irqL);
++
++ rtw_free_xmitbuf(pxmitpriv, pxmitbuf);
++
++ //if(rtw_txframes_pending(padapter))
++ {
++ tasklet_hi_schedule(&pxmitpriv->xmit_tasklet);
++ }
++
++_func_exit_;
++
++}
++
++u32 usb_write_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *wmem)
++{
++ _irqL irqL;
++ unsigned int pipe;
++ int status;
++ u32 ret = _FAIL, bwritezero = _FALSE;
++ PURB purb = NULL;
++ _adapter *padapter = (_adapter *)pintfhdl->padapter;
++ struct dvobj_priv *pdvobj = adapter_to_dvobj(padapter);
++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++ struct xmit_buf *pxmitbuf = (struct xmit_buf *)wmem;
++ struct xmit_frame *pxmitframe = (struct xmit_frame *)pxmitbuf->priv_data;
++ struct usb_device *pusbd = pdvobj->pusbdev;
++ struct pkt_attrib *pattrib = &pxmitframe->attrib;
++
++_func_enter_;
++
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("+usb_write_port\n"));
++
++ if ((padapter->bDriverStopped) || (padapter->bSurpriseRemoved) ||(padapter->pwrctrlpriv.pnp_bstop_trx)) {
++ #ifdef DBG_TX
++ DBG_871X(" DBG_TX %s:%d bDriverStopped%d, bSurpriseRemoved:%d, pnp_bstop_trx:%d\n",__FUNCTION__, __LINE__
++ ,padapter->bDriverStopped, padapter->bSurpriseRemoved, padapter->pwrctrlpriv.pnp_bstop_trx );
++ #endif
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_write_port:( padapter->bDriverStopped ||padapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx)!!!\n"));
++ rtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_TX_DENY);
++ goto exit;
++ }
++
++ _enter_critical(&pxmitpriv->lock, &irqL);
++
++ switch(addr)
++ {
++ case VO_QUEUE_INX:
++ pxmitpriv->voq_cnt++;
++ pxmitbuf->flags = VO_QUEUE_INX;
++ break;
++ case VI_QUEUE_INX:
++ pxmitpriv->viq_cnt++;
++ pxmitbuf->flags = VI_QUEUE_INX;
++ break;
++ case BE_QUEUE_INX:
++ pxmitpriv->beq_cnt++;
++ pxmitbuf->flags = BE_QUEUE_INX;
++ break;
++ case BK_QUEUE_INX:
++ pxmitpriv->bkq_cnt++;
++ pxmitbuf->flags = BK_QUEUE_INX;
++ break;
++ case HIGH_QUEUE_INX:
++ pxmitbuf->flags = HIGH_QUEUE_INX;
++ break;
++ default:
++ pxmitbuf->flags = MGT_QUEUE_INX;
++ break;
++ }
++
++ _exit_critical(&pxmitpriv->lock, &irqL);
++
++ purb = pxmitbuf->pxmit_urb[0];
++
++#if 0
++ if(pdvobj->ishighspeed)
++ {
++ if(cnt> 0 && cnt%512 == 0)
++ {
++ //DBG_8192C("ishighspeed, cnt=%d\n", cnt);
++ bwritezero = _TRUE;
++ }
++ }
++ else
++ {
++ if(cnt > 0 && cnt%64 == 0)
++ {
++ //DBG_8192C("cnt=%d\n", cnt);
++ bwritezero = _TRUE;
++ }
++ }
++#endif
++
++ //translate DMA FIFO addr to pipehandle
++ pipe = ffaddr2pipehdl(pdvobj, addr);
++
++#ifdef CONFIG_REDUCE_USB_TX_INT
++ if ( (pxmitpriv->free_xmitbuf_cnt%NR_XMITBUFF == 0)
++ || (pxmitbuf->ext_tag == _TRUE) )
++ {
++ purb->transfer_flags &= (~URB_NO_INTERRUPT);
++ } else {
++ purb->transfer_flags |= URB_NO_INTERRUPT;
++ //DBG_8192C("URB_NO_INTERRUPT ");
++ }
++#endif
++
++
++ usb_fill_bulk_urb(purb, pusbd, pipe,
++ pxmitframe->buf_addr, //= pxmitbuf->pbuf
++ cnt,
++ usb_write_port_complete,
++ pxmitbuf);//context is pxmitbuf
++
++#ifdef CONFIG_USE_USB_BUFFER_ALLOC_TX
++ purb->transfer_dma = pxmitbuf->dma_transfer_addr;
++ purb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP;
++ purb->transfer_flags |= URB_ZERO_PACKET;
++#endif // CONFIG_USE_USB_BUFFER_ALLOC_TX
++
++#if 0
++ if (bwritezero)
++ {
++ purb->transfer_flags |= URB_ZERO_PACKET;
++ }
++#endif
++
++ status = usb_submit_urb(purb, GFP_ATOMIC);
++ if (!status) {
++ #ifdef DBG_CONFIG_ERROR_DETECT
++ {
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++ pHalData->srestpriv.last_tx_time = rtw_get_current_time();
++ }
++ #endif
++ } else {
++ rtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_WRITE_PORT_ERR);
++ DBG_871X("usb_write_port, status=%d\n", status);
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_write_port(): usb_submit_urb, status=%x\n", status));
++
++ switch (status) {
++ case -ENODEV:
++ padapter->bDriverStopped=_TRUE;
++ break;
++ default:
++ break;
++ }
++ goto exit;
++ }
++
++ ret= _SUCCESS;
++
++// Commented by Albert 2009/10/13
++// We add the URB_ZERO_PACKET flag to urb so that the host will send the zero packet automatically.
++/*
++ if(bwritezero == _TRUE)
++ {
++ usb_bulkout_zero(pintfhdl, addr);
++ }
++*/
++
++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("-usb_write_port\n"));
++
++exit:
++ if (ret != _SUCCESS)
++ rtw_free_xmitbuf(pxmitpriv, pxmitbuf);
++_func_exit_;
++ return ret;
++
++}
++
++void usb_write_port_cancel(struct intf_hdl *pintfhdl)
++{
++ int i, j;
++ _adapter *padapter = pintfhdl->padapter;
++ struct xmit_buf *pxmitbuf = (struct xmit_buf *)padapter->xmitpriv.pxmitbuf;
++
++ DBG_871X("%s \n", __func__);
++
++ padapter->bWritePortCancel = _TRUE;
++
++ for (i=0; i<NR_XMITBUFF; i++) {
++ for (j=0; j<8; j++) {
++ if (pxmitbuf->pxmit_urb[j]) {
++ usb_kill_urb(pxmitbuf->pxmit_urb[j]);
++ }
++ }
++ pxmitbuf++;
++ }
++
++ pxmitbuf = (struct xmit_buf*)padapter->xmitpriv.pxmit_extbuf;
++ for (i = 0; i < NR_XMIT_EXTBUFF; i++) {
++ for (j=0; j<8; j++) {
++ if(pxmitbuf->pxmit_urb[j]) {
++ usb_kill_urb(pxmitbuf->pxmit_urb[j]);
++ }
++ }
++ pxmitbuf++;
++ }
++}
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/os_dep/linux/xmit_linux.c linux-xbian-rpi/drivers/net/wireless/rtl8192cu/os_dep/linux/xmit_linux.c
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/os_dep/linux/xmit_linux.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/os_dep/linux/xmit_linux.c 2015-07-28 01:20:58.433199136 +0200
+@@ -0,0 +1,420 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#define _XMIT_OSDEP_C_
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++
++#include <if_ether.h>
++#include <ip.h>
++#include <rtw_byteorder.h>
++#include <wifi.h>
++#include <mlme_osdep.h>
++#include <xmit_osdep.h>
++#include <osdep_intf.h>
++#include <circ_buf.h>
++
++
++uint rtw_remainder_len(struct pkt_file *pfile)
++{
++ return (pfile->buf_len - ((SIZE_PTR)(pfile->cur_addr) - (SIZE_PTR)(pfile->buf_start)));
++}
++
++void _rtw_open_pktfile (_pkt *pktptr, struct pkt_file *pfile)
++{
++_func_enter_;
++
++ pfile->pkt = pktptr;
++ pfile->cur_addr = pfile->buf_start = pktptr->data;
++ pfile->pkt_len = pfile->buf_len = pktptr->len;
++
++ pfile->cur_buffer = pfile->buf_start ;
++
++_func_exit_;
++}
++
++uint _rtw_pktfile_read (struct pkt_file *pfile, u8 *rmem, uint rlen)
++{
++ uint len = 0;
++
++_func_enter_;
++
++ len = rtw_remainder_len(pfile);
++ len = (rlen > len)? len: rlen;
++
++ if(rmem)
++ skb_copy_bits(pfile->pkt, pfile->buf_len-pfile->pkt_len, rmem, len);
++
++ pfile->cur_addr += len;
++ pfile->pkt_len -= len;
++
++_func_exit_;
++
++ return len;
++}
++
++sint rtw_endofpktfile(struct pkt_file *pfile)
++{
++_func_enter_;
++
++ if (pfile->pkt_len == 0) {
++_func_exit_;
++ return _TRUE;
++ }
++
++_func_exit_;
++
++ return _FALSE;
++}
++
++void rtw_set_tx_chksum_offload(_pkt *pkt, struct pkt_attrib *pattrib)
++{
++
++#ifdef CONFIG_TCP_CSUM_OFFLOAD_TX
++ struct sk_buff *skb = (struct sk_buff *)pkt;
++ pattrib->hw_tcp_csum = 0;
++
++ if (skb->ip_summed == CHECKSUM_PARTIAL) {
++ if (skb_shinfo(skb)->nr_frags == 0)
++ {
++ const struct iphdr *ip = ip_hdr(skb);
++ if (ip->protocol == IPPROTO_TCP) {
++ // TCP checksum offload by HW
++ DBG_871X("CHECKSUM_PARTIAL TCP\n");
++ pattrib->hw_tcp_csum = 1;
++ //skb_checksum_help(skb);
++ } else if (ip->protocol == IPPROTO_UDP) {
++ //DBG_871X("CHECKSUM_PARTIAL UDP\n");
++#if 1
++ skb_checksum_help(skb);
++#else
++ // Set UDP checksum = 0 to skip checksum check
++ struct udphdr *udp = skb_transport_header(skb);
++ udp->check = 0;
++#endif
++ } else {
++ DBG_871X("%s-%d TCP CSUM offload Error!!\n", __FUNCTION__, __LINE__);
++ WARN_ON(1); /* we need a WARN() */
++ }
++ }
++ else { // IP fragmentation case
++ DBG_871X("%s-%d nr_frags != 0, using skb_checksum_help(skb);!!\n", __FUNCTION__, __LINE__);
++ skb_checksum_help(skb);
++ }
++ }
++#endif
++
++}
++
++int rtw_os_xmit_resource_alloc(_adapter *padapter, struct xmit_buf *pxmitbuf,u32 alloc_sz)
++{
++#ifdef CONFIG_USB_HCI
++ int i;
++ struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
++ struct usb_device *pusbd = pdvobjpriv->pusbdev;
++
++#ifdef CONFIG_USE_USB_BUFFER_ALLOC_TX
++ pxmitbuf->pallocated_buf = rtw_usb_buffer_alloc(pusbd, (size_t)alloc_sz, &pxmitbuf->dma_transfer_addr);
++ pxmitbuf->pbuf = pxmitbuf->pallocated_buf;
++ if(pxmitbuf->pallocated_buf == NULL)
++ return _FAIL;
++#else // CONFIG_USE_USB_BUFFER_ALLOC_TX
++
++ pxmitbuf->pallocated_buf = rtw_zmalloc(alloc_sz);
++ if (pxmitbuf->pallocated_buf == NULL)
++ {
++ return _FAIL;
++ }
++
++ pxmitbuf->pbuf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitbuf->pallocated_buf), XMITBUF_ALIGN_SZ);
++ pxmitbuf->dma_transfer_addr = 0;
++
++#endif // CONFIG_USE_USB_BUFFER_ALLOC_TX
++
++ for(i=0; i<8; i++)
++ {
++ pxmitbuf->pxmit_urb[i] = usb_alloc_urb(0, GFP_KERNEL);
++ if(pxmitbuf->pxmit_urb[i] == NULL)
++ {
++ DBG_871X("pxmitbuf->pxmit_urb[i]==NULL");
++ return _FAIL;
++ }
++
++ }
++#endif
++#if defined(CONFIG_PCI_HCI) || defined(CONFIG_SDIO_HCI)
++ pxmitbuf->pallocated_buf = rtw_zmalloc(alloc_sz);
++ if (pxmitbuf->pallocated_buf == NULL)
++ {
++ return _FAIL;
++ }
++
++ pxmitbuf->pbuf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitbuf->pallocated_buf), XMITBUF_ALIGN_SZ);
++#endif
++
++ return _SUCCESS;
++}
++
++void rtw_os_xmit_resource_free(_adapter *padapter, struct xmit_buf *pxmitbuf,u32 free_sz)
++{
++#ifdef CONFIG_USB_HCI
++ int i;
++ struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
++ struct usb_device *pusbd = pdvobjpriv->pusbdev;
++
++
++ for(i=0; i<8; i++)
++ {
++ if(pxmitbuf->pxmit_urb[i])
++ {
++ //usb_kill_urb(pxmitbuf->pxmit_urb[i]);
++ usb_free_urb(pxmitbuf->pxmit_urb[i]);
++ }
++ }
++
++#ifdef CONFIG_USE_USB_BUFFER_ALLOC_TX
++ rtw_usb_buffer_free(pusbd, (size_t)free_sz, pxmitbuf->pallocated_buf, pxmitbuf->dma_transfer_addr);
++ pxmitbuf->pallocated_buf = NULL;
++ pxmitbuf->dma_transfer_addr = 0;
++#else // CONFIG_USE_USB_BUFFER_ALLOC_TX
++ if(pxmitbuf->pallocated_buf)
++ rtw_mfree(pxmitbuf->pallocated_buf, free_sz);
++#endif // CONFIG_USE_USB_BUFFER_ALLOC_TX
++
++#endif
++#if defined(CONFIG_PCI_HCI) || defined(CONFIG_SDIO_HCI)
++ if(pxmitbuf->pallocated_buf)
++ rtw_mfree(pxmitbuf->pallocated_buf, free_sz);
++#endif
++}
++
++void rtw_os_pkt_complete(_adapter *padapter, _pkt *pkt)
++{
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35))
++ u16 queue;
++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++
++ queue = skb_get_queue_mapping(pkt);
++ if(__netif_subqueue_stopped(padapter->pnetdev, queue) &&
++ (pxmitpriv->hwxmits[queue].accnt < NR_XMITFRAME/2))
++ {
++ netif_wake_subqueue(padapter->pnetdev, queue);
++ }
++#else
++ if (netif_queue_stopped(padapter->pnetdev))
++ netif_wake_queue(padapter->pnetdev);
++#endif
++
++ rtw_skb_free(pkt);
++}
++
++void rtw_os_xmit_complete(_adapter *padapter, struct xmit_frame *pxframe)
++{
++ if(pxframe->pkt)
++ rtw_os_pkt_complete(padapter, pxframe->pkt);
++
++ pxframe->pkt = NULL;
++}
++
++void rtw_os_xmit_schedule(_adapter *padapter)
++{
++#ifdef CONFIG_SDIO_HCI
++ if(!padapter)
++ return;
++
++ if (rtw_txframes_pending(padapter))
++ _rtw_up_sema(&padapter->xmitpriv.xmit_sema);
++#else
++ _irqL irqL;
++ struct xmit_priv *pxmitpriv;
++
++ if(!padapter)
++ return;
++
++ pxmitpriv = &padapter->xmitpriv;
++
++ _enter_critical_bh(&pxmitpriv->lock, &irqL);
++
++ if(rtw_txframes_pending(padapter))
++ {
++ tasklet_hi_schedule(&pxmitpriv->xmit_tasklet);
++ }
++
++ _exit_critical_bh(&pxmitpriv->lock, &irqL);
++#endif
++}
++
++
++
++#ifdef CONFIG_TX_MCAST2UNI
++int rtw_mlcst2unicst(_adapter *padapter, struct sk_buff *skb)
++{
++ struct sta_priv *pstapriv = &padapter->stapriv;
++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++ _irqL irqL;
++ _list *phead, *plist;
++ struct sk_buff *newskb;
++ struct sta_info *psta = NULL;
++ u8 chk_alive_num = 0;
++ char chk_alive_list[NUM_STA];
++ u8 bc_addr[6]={0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
++ u8 null_addr[6]={0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
++
++ int i;
++ s32 res;
++
++ _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++ phead = &pstapriv->asoc_list;
++ plist = get_next(phead);
++
++ //free sta asoc_queue
++ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
++ int stainfo_offset;
++ psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);
++ plist = get_next(plist);
++
++ stainfo_offset = rtw_stainfo_offset(pstapriv, psta);
++ if (stainfo_offset_valid(stainfo_offset)) {
++ chk_alive_list[chk_alive_num++] = stainfo_offset;
++ }
++ }
++ _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++
++ for (i = 0; i < chk_alive_num; i++) {
++ psta = rtw_get_stainfo_by_offset(pstapriv, chk_alive_list[i]);
++
++ /* avoid come from STA1 and send back STA1 */
++ if (_rtw_memcmp(psta->hwaddr, &skb->data[6], 6) == _TRUE
++ || _rtw_memcmp(psta->hwaddr, null_addr, 6) == _TRUE
++ || _rtw_memcmp(psta->hwaddr, bc_addr, 6) == _TRUE
++ )
++ continue;
++
++ newskb = rtw_skb_copy(skb);
++
++ if (newskb) {
++ _rtw_memcpy(newskb->data, psta->hwaddr, 6);
++ res = rtw_xmit(padapter, &newskb);
++ if (res < 0) {
++ DBG_871X("%s()-%d: rtw_xmit() return error!\n", __FUNCTION__, __LINE__);
++ pxmitpriv->tx_drop++;
++ rtw_skb_free(newskb);
++ } else
++ pxmitpriv->tx_pkts++;
++ } else {
++ DBG_871X("%s-%d: rtw_skb_copy() failed!\n", __FUNCTION__, __LINE__);
++ pxmitpriv->tx_drop++;
++ //rtw_skb_free(skb);
++ return _FALSE; // Caller shall tx this multicast frame via normal way.
++ }
++ }
++
++ rtw_skb_free(skb);
++ return _TRUE;
++}
++#endif // CONFIG_TX_MCAST2UNI
++
++
++int _rtw_xmit_entry(_pkt *pkt, _nic_hdl pnetdev)
++{
++ _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev);
++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++#ifdef CONFIG_TX_MCAST2UNI
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ extern int rtw_mc2u_disable;
++#endif // CONFIG_TX_MCAST2UNI
++ s32 res = 0;
++#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,35))
++ u16 queue;
++#endif
++
++_func_enter_;
++
++ RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("+xmit_enry\n"));
++
++ if (rtw_if_up(padapter) == _FALSE) {
++ RT_TRACE(_module_xmit_osdep_c_, _drv_err_, ("rtw_xmit_entry: rtw_if_up fail\n"));
++ #ifdef DBG_TX_DROP_FRAME
++ DBG_871X("DBG_TX_DROP_FRAME %s if_up fail\n", __FUNCTION__);
++ #endif
++ goto drop_packet;
++ }
++
++#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,35))
++ queue = skb_get_queue_mapping(pkt);
++ /* No free space for Tx, tx_worker is too slow */
++ if (pxmitpriv->hwxmits[queue].accnt > NR_XMITFRAME/2) {
++ //DBG_871X("%s(): stop netif_subqueue[%d]\n", __FUNCTION__, queue);
++ netif_stop_subqueue(padapter->pnetdev, queue);
++ return NETDEV_TX_BUSY;
++ }
++#endif
++
++#ifdef CONFIG_TX_MCAST2UNI
++ if ( !rtw_mc2u_disable
++ && check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE
++ && ( IP_MCAST_MAC(pkt->data)
++ || ICMPV6_MCAST_MAC(pkt->data) )
++ && (padapter->registrypriv.wifi_spec == 0)
++ )
++ {
++ if ( pxmitpriv->free_xmitframe_cnt > (NR_XMITFRAME/4) ) {
++ res = rtw_mlcst2unicst(padapter, pkt);
++ if (res == _TRUE) {
++ goto exit;
++ }
++ } else {
++ //DBG_871X("Stop M2U(%d, %d)! ", pxmitpriv->free_xmitframe_cnt, pxmitpriv->free_xmitbuf_cnt);
++ //DBG_871X("!m2u );
++ }
++ }
++#endif // CONFIG_TX_MCAST2UNI
++
++ res = rtw_xmit(padapter, &pkt);
++ if (res < 0) {
++ #ifdef DBG_TX_DROP_FRAME
++ DBG_871X("DBG_TX_DROP_FRAME %s rtw_xmit fail\n", __FUNCTION__);
++ #endif
++ goto drop_packet;
++ }
++
++ pxmitpriv->tx_pkts++;
++ RT_TRACE(_module_xmit_osdep_c_, _drv_info_, ("rtw_xmit_entry: tx_pkts=%d\n", (u32)pxmitpriv->tx_pkts));
++ goto exit;
++
++drop_packet:
++ pxmitpriv->tx_drop++;
++ rtw_skb_free(pkt);
++ RT_TRACE(_module_xmit_osdep_c_, _drv_notice_, ("rtw_xmit_entry: drop, tx_drop=%d\n", (u32)pxmitpriv->tx_drop));
++
++exit:
++
++_func_exit_;
++
++ return 0;
++}
++
++int rtw_xmit_entry(_pkt *pkt, _nic_hdl pnetdev)
++{
++ if (pkt)
++ rtw_mstat_update(MSTAT_TYPE_SKB, MSTAT_ALLOC_SUCCESS, pkt->truesize);
++ return _rtw_xmit_entry(pkt, pnetdev);
++}
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/os_dep/osdep_service.c linux-xbian-rpi/drivers/net/wireless/rtl8192cu/os_dep/osdep_service.c
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/os_dep/osdep_service.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/os_dep/osdep_service.c 2015-07-28 01:20:58.433199136 +0200
+@@ -0,0 +1,2299 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++
++
++#define _OSDEP_SERVICE_C_
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++#include <recv_osdep.h>
++#ifdef PLATFORM_LINUX
++#include <linux/vmalloc.h>
++#endif
++#ifdef PLATFORM_FREEBSD
++#include <sys/malloc.h>
++#include <sys/time.h>
++#endif /* PLATFORM_FREEBSD */
++#ifdef RTK_DMP_PLATFORM
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,12))
++#include <linux/pageremap.h>
++#endif
++#endif
++
++#define RT_TAG '1178'
++
++#ifdef DBG_MEMORY_LEAK
++#ifdef PLATFORM_LINUX
++#include <asm/atomic.h>
++atomic_t _malloc_cnt = ATOMIC_INIT(0);
++atomic_t _malloc_size = ATOMIC_INIT(0);
++#endif
++#endif /* DBG_MEMORY_LEAK */
++
++
++#if defined(PLATFORM_LINUX)
++/*
++* Translate the OS dependent @param error_code to OS independent RTW_STATUS_CODE
++* @return: one of RTW_STATUS_CODE
++*/
++inline int RTW_STATUS_CODE(int error_code){
++ if(error_code >=0)
++ return _SUCCESS;
++
++ switch(error_code) {
++ //case -ETIMEDOUT:
++ // return RTW_STATUS_TIMEDOUT;
++ default:
++ return _FAIL;
++ }
++}
++#else
++inline int RTW_STATUS_CODE(int error_code){
++ return error_code;
++}
++#endif
++
++u32 rtw_atoi(u8* s)
++{
++
++ int num=0,flag=0;
++ int i;
++ for(i=0;i<=strlen(s);i++)
++ {
++ if(s[i] >= '0' && s[i] <= '9')
++ num = num * 10 + s[i] -'0';
++ else if(s[0] == '-' && i==0)
++ flag =1;
++ else
++ break;
++ }
++
++ if(flag == 1)
++ num = num * -1;
++
++ return(num);
++
++}
++
++inline u8* _rtw_vmalloc(u32 sz)
++{
++ u8 *pbuf;
++#ifdef PLATFORM_LINUX
++ pbuf = vmalloc(sz);
++#endif
++#ifdef PLATFORM_FREEBSD
++ pbuf = malloc(sz,M_DEVBUF,M_NOWAIT);
++#endif
++
++#ifdef PLATFORM_WINDOWS
++ NdisAllocateMemoryWithTag(&pbuf,sz, RT_TAG);
++#endif
++
++#ifdef DBG_MEMORY_LEAK
++#ifdef PLATFORM_LINUX
++ if ( pbuf != NULL) {
++ atomic_inc(&_malloc_cnt);
++ atomic_add(sz, &_malloc_size);
++ }
++#endif
++#endif /* DBG_MEMORY_LEAK */
++
++ return pbuf;
++}
++
++inline u8* _rtw_zvmalloc(u32 sz)
++{
++ u8 *pbuf;
++#ifdef PLATFORM_LINUX
++ pbuf = _rtw_vmalloc(sz);
++ if (pbuf != NULL)
++ memset(pbuf, 0, sz);
++#endif
++#ifdef PLATFORM_FREEBSD
++ pbuf = malloc(sz,M_DEVBUF,M_ZERO|M_NOWAIT);
++#endif
++#ifdef PLATFORM_WINDOWS
++ NdisAllocateMemoryWithTag(&pbuf,sz, RT_TAG);
++ if (pbuf != NULL)
++ NdisFillMemory(pbuf, sz, 0);
++#endif
++
++ return pbuf;
++}
++
++inline void _rtw_vmfree(u8 *pbuf, u32 sz)
++{
++#ifdef PLATFORM_LINUX
++ vfree(pbuf);
++#endif
++#ifdef PLATFORM_FREEBSD
++ free(pbuf,M_DEVBUF);
++#endif
++#ifdef PLATFORM_WINDOWS
++ NdisFreeMemory(pbuf,sz, 0);
++#endif
++
++#ifdef DBG_MEMORY_LEAK
++#ifdef PLATFORM_LINUX
++ atomic_dec(&_malloc_cnt);
++ atomic_sub(sz, &_malloc_size);
++#endif
++#endif /* DBG_MEMORY_LEAK */
++}
++
++u8* _rtw_malloc(u32 sz)
++{
++
++ u8 *pbuf=NULL;
++
++#ifdef PLATFORM_LINUX
++#ifdef RTK_DMP_PLATFORM
++ if(sz > 0x4000)
++ pbuf = (u8 *)dvr_malloc(sz);
++ else
++#endif
++ pbuf = kmalloc(sz,in_interrupt() ? GFP_ATOMIC : GFP_KERNEL);
++
++#endif
++#ifdef PLATFORM_FREEBSD
++ pbuf = malloc(sz,M_DEVBUF,M_NOWAIT);
++#endif
++#ifdef PLATFORM_WINDOWS
++
++ NdisAllocateMemoryWithTag(&pbuf,sz, RT_TAG);
++
++#endif
++
++#ifdef DBG_MEMORY_LEAK
++#ifdef PLATFORM_LINUX
++ if ( pbuf != NULL) {
++ atomic_inc(&_malloc_cnt);
++ atomic_add(sz, &_malloc_size);
++ }
++#endif
++#endif /* DBG_MEMORY_LEAK */
++
++ return pbuf;
++
++}
++
++
++u8* _rtw_zmalloc(u32 sz)
++{
++#ifdef PLATFORM_FREEBSD
++ return malloc(sz,M_DEVBUF,M_ZERO|M_NOWAIT);
++#else // PLATFORM_FREEBSD
++ u8 *pbuf = _rtw_malloc(sz);
++
++ if (pbuf != NULL) {
++
++#ifdef PLATFORM_LINUX
++ memset(pbuf, 0, sz);
++#endif
++
++#ifdef PLATFORM_WINDOWS
++ NdisFillMemory(pbuf, sz, 0);
++#endif
++
++ }
++
++ return pbuf;
++#endif // PLATFORM_FREEBSD
++}
++
++void _rtw_mfree(u8 *pbuf, u32 sz)
++{
++
++#ifdef PLATFORM_LINUX
++#ifdef RTK_DMP_PLATFORM
++ if(sz > 0x4000)
++ dvr_free(pbuf);
++ else
++#endif
++ kfree(pbuf);
++
++#endif
++#ifdef PLATFORM_FREEBSD
++ free(pbuf,M_DEVBUF);
++#endif
++#ifdef PLATFORM_WINDOWS
++
++ NdisFreeMemory(pbuf,sz, 0);
++
++#endif
++
++#ifdef DBG_MEMORY_LEAK
++#ifdef PLATFORM_LINUX
++ atomic_dec(&_malloc_cnt);
++ atomic_sub(sz, &_malloc_size);
++#endif
++#endif /* DBG_MEMORY_LEAK */
++
++}
++
++#ifdef PLATFORM_FREEBSD
++//review again
++struct sk_buff * dev_alloc_skb(unsigned int size)
++{
++ struct sk_buff *skb=NULL;
++ u8 *data=NULL;
++
++ //skb = (struct sk_buff *)_rtw_zmalloc(sizeof(struct sk_buff)); // for skb->len, etc.
++ skb = (struct sk_buff *)_rtw_malloc(sizeof(struct sk_buff));
++ if(!skb)
++ goto out;
++ data = _rtw_malloc(size);
++ if(!data)
++ goto nodata;
++
++ skb->head = (unsigned char*)data;
++ skb->data = (unsigned char*)data;
++ skb->tail = (unsigned char*)data;
++ skb->end = (unsigned char*)data + size;
++ skb->len = 0;
++ //printf("%s()-%d: skb=%p, skb->head = %p\n", __FUNCTION__, __LINE__, skb, skb->head);
++
++out:
++ return skb;
++nodata:
++ _rtw_mfree((u8 *)skb, sizeof(struct sk_buff));
++ skb = NULL;
++goto out;
++
++}
++
++void dev_kfree_skb_any(struct sk_buff *skb)
++{
++ //printf("%s()-%d: skb->head = %p\n", __FUNCTION__, __LINE__, skb->head);
++ if(skb->head)
++ _rtw_mfree(skb->head, 0);
++ //printf("%s()-%d: skb = %p\n", __FUNCTION__, __LINE__, skb);
++ if(skb)
++ _rtw_mfree((u8 *)skb, 0);
++}
++struct sk_buff *skb_clone(const struct sk_buff *skb)
++{
++ return NULL;
++}
++
++#endif /* PLATFORM_FREEBSD */
++
++inline struct sk_buff *_rtw_skb_alloc(u32 sz)
++{
++#ifdef PLATFORM_LINUX
++ return __dev_alloc_skb(sz, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL);
++#endif /* PLATFORM_LINUX */
++
++#ifdef PLATFORM_FREEBSD
++ return dev_alloc_skb(sz);
++#endif /* PLATFORM_FREEBSD */
++}
++
++inline void _rtw_skb_free(struct sk_buff *skb)
++{
++ dev_kfree_skb_any(skb);
++}
++
++inline struct sk_buff *_rtw_skb_copy(const struct sk_buff *skb)
++{
++#ifdef PLATFORM_LINUX
++ return skb_copy(skb, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL);
++#endif /* PLATFORM_LINUX */
++
++#ifdef PLATFORM_FREEBSD
++ return NULL;
++#endif /* PLATFORM_FREEBSD */
++}
++
++inline struct sk_buff *_rtw_skb_clone(struct sk_buff *skb)
++{
++#ifdef PLATFORM_LINUX
++ return skb_clone(skb, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL);
++#endif /* PLATFORM_LINUX */
++
++#ifdef PLATFORM_FREEBSD
++ return skb_clone(skb);
++#endif /* PLATFORM_FREEBSD */
++}
++
++inline int _rtw_netif_rx(_nic_hdl ndev, struct sk_buff *skb)
++{
++#ifdef PLATFORM_LINUX
++ skb->dev = ndev;
++ return netif_rx(skb);
++#endif /* PLATFORM_LINUX */
++
++#ifdef PLATFORM_FREEBSD
++ return (*ndev->if_input)(ndev, skb);
++#endif /* PLATFORM_FREEBSD */
++}
++
++void _rtw_skb_queue_purge(struct sk_buff_head *list)
++{
++ struct sk_buff *skb;
++
++ while ((skb = skb_dequeue(list)) != NULL)
++ _rtw_skb_free(skb);
++}
++
++#ifdef CONFIG_USB_HCI
++inline void *_rtw_usb_buffer_alloc(struct usb_device *dev, size_t size, dma_addr_t *dma)
++{
++#ifdef PLATFORM_LINUX
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35))
++ return usb_alloc_coherent(dev, size, (in_interrupt() ? GFP_ATOMIC : GFP_KERNEL), dma);
++#else
++ return usb_buffer_alloc(dev, size, (in_interrupt() ? GFP_ATOMIC : GFP_KERNEL), dma);
++#endif
++#endif /* PLATFORM_LINUX */
++
++#ifdef PLATFORM_FREEBSD
++ return (malloc(size, M_USBDEV, M_NOWAIT | M_ZERO));
++#endif /* PLATFORM_FREEBSD */
++}
++inline void _rtw_usb_buffer_free(struct usb_device *dev, size_t size, void *addr, dma_addr_t dma)
++{
++#ifdef PLATFORM_LINUX
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35))
++ usb_free_coherent(dev, size, addr, dma);
++#else
++ usb_buffer_free(dev, size, addr, dma);
++#endif
++#endif /* PLATFORM_LINUX */
++
++#ifdef PLATFORM_FREEBSD
++ free(addr, M_USBDEV);
++#endif /* PLATFORM_FREEBSD */
++}
++#endif /* CONFIG_USB_HCI */
++
++#ifdef DBG_MEM_ALLOC
++
++struct rtw_mem_stat {
++ ATOMIC_T alloc; // the memory bytes we allocate currently
++ ATOMIC_T peak; // the peak memory bytes we allocate
++ ATOMIC_T alloc_cnt; // the alloc count for alloc currently
++ ATOMIC_T alloc_err_cnt; // the error times we fail to allocate memory
++};
++
++struct rtw_mem_stat rtw_mem_type_stat[mstat_tf_idx(MSTAT_TYPE_MAX)];
++struct rtw_mem_stat rtw_mem_func_stat[mstat_ff_idx(MSTAT_FUNC_MAX)];
++
++char *MSTAT_TYPE_str[] = {
++ "VIR",
++ "PHY",
++ "SKB",
++ "USB",
++};
++
++char *MSTAT_FUNC_str[] = {
++ "UNSP",
++ "IO",
++ "TXIO",
++ "RXIO",
++ "TX",
++ "RX",
++};
++
++int _rtw_mstat_dump(char *buf, int len)
++{
++ int cnt = 0;
++ int i;
++ int value_t[4][mstat_tf_idx(MSTAT_TYPE_MAX)];
++ int value_f[4][mstat_ff_idx(MSTAT_FUNC_MAX)];
++
++ int vir_alloc, vir_peak, vir_alloc_err, phy_alloc, phy_peak, phy_alloc_err;
++ int tx_alloc, tx_peak, tx_alloc_err, rx_alloc, rx_peak, rx_alloc_err;
++
++ for(i=0;i<mstat_tf_idx(MSTAT_TYPE_MAX);i++) {
++ value_t[0][i] = ATOMIC_READ(&(rtw_mem_type_stat[i].alloc));
++ value_t[1][i] = ATOMIC_READ(&(rtw_mem_type_stat[i].peak));
++ value_t[2][i] = ATOMIC_READ(&(rtw_mem_type_stat[i].alloc_cnt));
++ value_t[3][i] = ATOMIC_READ(&(rtw_mem_type_stat[i].alloc_err_cnt));
++ }
++
++ #if 0
++ for(i=0;i<mstat_ff_idx(MSTAT_FUNC_MAX);i++) {
++ value_f[0][i] = ATOMIC_READ(&(rtw_mem_func_stat[i].alloc));
++ value_f[1][i] = ATOMIC_READ(&(rtw_mem_func_stat[i].peak));
++ value_f[2][i] = ATOMIC_READ(&(rtw_mem_func_stat[i].alloc_cnt));
++ value_f[3][i] = ATOMIC_READ(&(rtw_mem_func_stat[i].alloc_err_cnt));
++ }
++ #endif
++
++ cnt += snprintf(buf+cnt, len-cnt, "===================== MSTAT =====================\n");
++ cnt += snprintf(buf+cnt, len-cnt, "%4s %10s %10s %10s %10s\n", "TAG", "alloc", "peak", "aloc_cnt", "err_cnt");
++ cnt += snprintf(buf+cnt, len-cnt, "-------------------------------------------------\n");
++ for(i=0;i<mstat_tf_idx(MSTAT_TYPE_MAX);i++) {
++ cnt += snprintf(buf+cnt, len-cnt, "%4s %10d %10d %10d %10d\n", MSTAT_TYPE_str[i], value_t[0][i], value_t[1][i], value_t[2][i], value_t[3][i]);
++ }
++ #if 0
++ cnt += snprintf(buf+cnt, len-cnt, "-------------------------------------------------\n");
++ for(i=0;i<mstat_ff_idx(MSTAT_FUNC_MAX);i++) {
++ cnt += snprintf(buf+cnt, len-cnt, "%4s %10d %10d %10d %10d\n", MSTAT_FUNC_str[i], value_f[0][i], value_f[1][i], value_f[2][i], value_f[3][i]);
++ }
++ #endif
++
++ return cnt;
++}
++
++void rtw_mstat_dump(void)
++{
++ char buf[768] = {0};
++
++ _rtw_mstat_dump(buf, 768);
++ DBG_871X("\n%s", buf);
++}
++
++void rtw_mstat_update(const enum mstat_f flags, const MSTAT_STATUS status, u32 sz)
++{
++ static u32 update_time = 0;
++ int peak, alloc;
++ int i;
++
++ /* initialization */
++ if(!update_time) {
++ for(i=0;i<mstat_tf_idx(MSTAT_TYPE_MAX);i++) {
++ ATOMIC_SET(&(rtw_mem_type_stat[i].alloc), 0);
++ ATOMIC_SET(&(rtw_mem_type_stat[i].peak), 0);
++ ATOMIC_SET(&(rtw_mem_type_stat[i].alloc_cnt), 0);
++ ATOMIC_SET(&(rtw_mem_type_stat[i].alloc_err_cnt), 0);
++ }
++ for(i=0;i<mstat_ff_idx(MSTAT_FUNC_MAX);i++) {
++ ATOMIC_SET(&(rtw_mem_func_stat[i].alloc), 0);
++ ATOMIC_SET(&(rtw_mem_func_stat[i].peak), 0);
++ ATOMIC_SET(&(rtw_mem_func_stat[i].alloc_cnt), 0);
++ ATOMIC_SET(&(rtw_mem_func_stat[i].alloc_err_cnt), 0);
++ }
++ }
++
++ switch(status) {
++ case MSTAT_ALLOC_SUCCESS:
++ ATOMIC_INC(&(rtw_mem_type_stat[mstat_tf_idx(flags)].alloc_cnt));
++ alloc = ATOMIC_ADD_RETURN(&(rtw_mem_type_stat[mstat_tf_idx(flags)].alloc), sz);
++ peak=ATOMIC_READ(&(rtw_mem_type_stat[mstat_tf_idx(flags)].peak));
++ if (peak<alloc)
++ ATOMIC_SET(&(rtw_mem_type_stat[mstat_tf_idx(flags)].peak), alloc);
++
++ ATOMIC_INC(&(rtw_mem_func_stat[mstat_ff_idx(flags)].alloc_cnt));
++ alloc = ATOMIC_ADD_RETURN(&(rtw_mem_func_stat[mstat_ff_idx(flags)].alloc), sz);
++ peak=ATOMIC_READ(&(rtw_mem_func_stat[mstat_ff_idx(flags)].peak));
++ if (peak<alloc)
++ ATOMIC_SET(&(rtw_mem_func_stat[mstat_ff_idx(flags)].peak), alloc);
++ break;
++
++ case MSTAT_ALLOC_FAIL:
++ ATOMIC_INC(&(rtw_mem_type_stat[mstat_tf_idx(flags)].alloc_err_cnt));
++
++ ATOMIC_INC(&(rtw_mem_func_stat[mstat_ff_idx(flags)].alloc_err_cnt));
++ break;
++
++ case MSTAT_FREE:
++ ATOMIC_DEC(&(rtw_mem_type_stat[mstat_tf_idx(flags)].alloc_cnt));
++ ATOMIC_SUB(&(rtw_mem_type_stat[mstat_tf_idx(flags)].alloc), sz);
++
++ ATOMIC_DEC(&(rtw_mem_func_stat[mstat_ff_idx(flags)].alloc_cnt));
++ ATOMIC_SUB(&(rtw_mem_func_stat[mstat_ff_idx(flags)].alloc), sz);
++ break;
++ };
++
++ //if (rtw_get_passing_time_ms(update_time) > 5000) {
++ // rtw_mstat_dump();
++ update_time=rtw_get_current_time();
++ //}
++}
++
++
++
++inline u8* dbg_rtw_vmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line)
++{
++ u8 *p;
++ //DBG_871X("DBG_MEM_ALLOC %s:%d %s(%d)\n", func, line, __FUNCTION__, (sz));
++
++ p=_rtw_vmalloc((sz));
++
++ rtw_mstat_update(
++ flags
++ , p ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL
++ , sz
++ );
++
++ return p;
++}
++
++inline u8* dbg_rtw_zvmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line)
++{
++ u8 *p;
++ //DBG_871X("DBG_MEM_ALLOC %s:%d %s(%d)\n", func, line, __FUNCTION__, (sz));
++
++ p=_rtw_zvmalloc((sz));
++
++ rtw_mstat_update(
++ flags
++ , p ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL
++ , sz
++ );
++
++ return p;
++}
++
++inline void dbg_rtw_vmfree(u8 *pbuf, u32 sz, const enum mstat_f flags, const char *func, const int line)
++{
++ //DBG_871X("DBG_MEM_ALLOC %s:%d %s(%p,%d)\n", func, line, __FUNCTION__, (pbuf), (sz));
++
++ _rtw_vmfree((pbuf), (sz));
++
++ rtw_mstat_update(
++ flags
++ , MSTAT_FREE
++ , sz
++ );
++}
++
++inline u8* dbg_rtw_malloc(u32 sz, const enum mstat_f flags, const char *func, const int line)
++{
++ u8 *p;
++
++ //if(sz>=153 && sz<=306)
++ // DBG_871X("DBG_MEM_ALLOC %s:%d %s(%d)\n", func, line, __FUNCTION__, (sz));
++
++ //if((sz)>4096)
++ // DBG_871X("DBG_MEM_ALLOC %s:%d %s(%d)\n", func, line, __FUNCTION__, (sz));
++
++ p=_rtw_malloc((sz));
++
++ rtw_mstat_update(
++ flags
++ , p ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL
++ , sz
++ );
++
++ return p;
++}
++
++inline u8* dbg_rtw_zmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line)
++{
++ u8 *p;
++
++ //if(sz>=153 && sz<=306)
++ // DBG_871X("DBG_MEM_ALLOC %s:%d %s(%d)\n", func, line, __FUNCTION__, (sz));
++
++ //if((sz)>4096)
++ // DBG_871X("DBG_MEM_ALLOC %s:%d %s(%d)\n", func, line, __FUNCTION__, (sz));
++
++ p = _rtw_zmalloc((sz));
++
++ rtw_mstat_update(
++ flags
++ , p ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL
++ , sz
++ );
++
++ return p;
++}
++
++inline void dbg_rtw_mfree(u8 *pbuf, u32 sz, const enum mstat_f flags, const char *func, const int line)
++{
++ //if(sz>=153 && sz<=306)
++ // DBG_871X("DBG_MEM_ALLOC %s:%d %s(%d)\n", func, line, __FUNCTION__, (sz));
++
++ //if((sz)>4096)
++ // DBG_871X("DBG_MEM_ALLOC %s:%d %s(%p,%d)\n", func, line, __FUNCTION__, (pbuf), (sz));
++
++ _rtw_mfree((pbuf), (sz));
++
++ rtw_mstat_update(
++ flags
++ , MSTAT_FREE
++ , sz
++ );
++}
++
++inline struct sk_buff * dbg_rtw_skb_alloc(unsigned int size, const enum mstat_f flags, const char *func, int line)
++{
++ struct sk_buff *skb;
++ unsigned int truesize = 0;
++
++ skb = _rtw_skb_alloc(size);
++
++ if(skb)
++ truesize = skb->truesize;
++
++ if(!skb || truesize < size /*|| size > 4096*/)
++ DBG_871X("DBG_MEM_ALLOC %s:%d %s(%d), skb:%p, truesize=%u\n", func, line, __FUNCTION__, size, skb, truesize);
++
++ rtw_mstat_update(
++ flags
++ , skb ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL
++ , truesize
++ );
++
++ return skb;
++}
++
++inline void dbg_rtw_skb_free(struct sk_buff *skb, const enum mstat_f flags, const char *func, int line)
++{
++ unsigned int truesize = skb->truesize;
++
++ //if(truesize > 4096)
++ // DBG_871X("DBG_MEM_ALLOC %s:%d %s, truesize=%u\n", func, line, __FUNCTION__, truesize);
++
++ _rtw_skb_free(skb);
++
++ rtw_mstat_update(
++ flags
++ , MSTAT_FREE
++ , truesize
++ );
++}
++
++inline struct sk_buff *dbg_rtw_skb_copy(const struct sk_buff *skb, const enum mstat_f flags, const char *func, const int line)
++{
++ struct sk_buff *skb_cp;
++ unsigned int truesize = skb->truesize;
++ unsigned int cp_truesize = 0;
++
++ skb_cp = _rtw_skb_copy(skb);
++ if(skb_cp)
++ cp_truesize = skb_cp->truesize;
++
++ if(!skb_cp || cp_truesize != truesize /*||cp_truesize > 4096*/)
++ DBG_871X("DBG_MEM_ALLOC %s:%d %s(%u), skb_cp:%p, cp_truesize=%u\n", func, line, __FUNCTION__, truesize, skb_cp, cp_truesize);
++
++ rtw_mstat_update(
++ flags
++ , skb_cp ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL
++ , truesize
++ );
++
++ return skb_cp;
++}
++
++inline struct sk_buff *dbg_rtw_skb_clone(struct sk_buff *skb, const enum mstat_f flags, const char *func, const int line)
++{
++ struct sk_buff *skb_cl;
++ unsigned int truesize = skb->truesize;
++ unsigned int cl_truesize = 0;
++
++ skb_cl = _rtw_skb_clone(skb);
++ if(skb_cl)
++ cl_truesize = skb_cl->truesize;
++
++ if(!skb_cl || cl_truesize != truesize /*|| cl_truesize > 4096*/)
++ DBG_871X("DBG_MEM_ALLOC %s:%d %s(%u), skb_cl:%p, cl_truesize=%u\n", func, line, __FUNCTION__, truesize, skb_cl, cl_truesize);
++
++ rtw_mstat_update(
++ flags
++ , skb_cl ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL
++ , truesize
++ );
++
++ return skb_cl;
++}
++
++inline int dbg_rtw_netif_rx(_nic_hdl ndev, struct sk_buff *skb, const enum mstat_f flags, const char *func, int line)
++{
++ int ret;
++ unsigned int truesize = skb->truesize;
++
++ //if(truesize > 4096)
++ // DBG_871X("DBG_MEM_ALLOC %s:%d %s, truesize=%u\n", func, line, __FUNCTION__, truesize);
++
++ ret = _rtw_netif_rx(ndev, skb);
++
++ rtw_mstat_update(
++ flags
++ , MSTAT_FREE
++ , truesize
++ );
++
++ return ret;
++}
++
++inline void dbg_rtw_skb_queue_purge(struct sk_buff_head *list, enum mstat_f flags, const char *func, int line)
++{
++ struct sk_buff *skb;
++
++ while ((skb = skb_dequeue(list)) != NULL)
++ dbg_rtw_skb_free(skb, flags, func, line);
++}
++
++#ifdef CONFIG_USB_HCI
++inline void *dbg_rtw_usb_buffer_alloc(struct usb_device *dev, size_t size, dma_addr_t *dma, const enum mstat_f flags, const char *func, int line)
++{
++ void *p;
++ //DBG_871X("DBG_MEM_ALLOC %s:%d %s(%d)\n", func, line, __FUNCTION__, size);
++
++ p = _rtw_usb_buffer_alloc(dev, size, dma);
++
++ rtw_mstat_update(
++ flags
++ , p ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL
++ , size
++ );
++
++ return p;
++}
++
++inline void dbg_rtw_usb_buffer_free(struct usb_device *dev, size_t size, void *addr, dma_addr_t dma, const enum mstat_f flags, const char *func, int line)
++{
++ //DBG_871X("DBG_MEM_ALLOC %s:%d %s(%d)\n", func, line, __FUNCTION__, size);
++
++ _rtw_usb_buffer_free(dev, size, addr, dma);
++
++ rtw_mstat_update(
++ flags
++ , MSTAT_FREE
++ , size
++ );
++}
++#endif /* CONFIG_USB_HCI */
++#endif /* DBG_MEM_ALLOC */
++
++void* rtw_malloc2d(int h, int w, int size)
++{
++ int j;
++
++ void **a = (void **) rtw_zmalloc( h*sizeof(void *) + h*w*size );
++ if(a == NULL)
++ {
++ DBG_871X("%s: alloc memory fail!\n", __FUNCTION__);
++ return NULL;
++ }
++
++ for( j=0; j<h; j++ )
++ a[j] = ((char *)(a+h)) + j*w*size;
++
++ return a;
++}
++
++void rtw_mfree2d(void *pbuf, int h, int w, int size)
++{
++ rtw_mfree((u8 *)pbuf, h*sizeof(void*) + w*h*size);
++}
++
++void _rtw_memcpy(void* dst, void* src, u32 sz)
++{
++
++#if defined (PLATFORM_LINUX)|| defined (PLATFORM_FREEBSD)
++
++ memcpy(dst, src, sz);
++
++#endif
++
++#ifdef PLATFORM_WINDOWS
++
++ NdisMoveMemory(dst, src, sz);
++
++#endif
++
++}
++
++int _rtw_memcmp(void *dst, void *src, u32 sz)
++{
++
++#if defined (PLATFORM_LINUX)|| defined (PLATFORM_FREEBSD)
++//under Linux/GNU/GLibc, the return value of memcmp for two same mem. chunk is 0
++
++ if (!(memcmp(dst, src, sz)))
++ return _TRUE;
++ else
++ return _FALSE;
++#endif
++
++
++#ifdef PLATFORM_WINDOWS
++//under Windows, the return value of NdisEqualMemory for two same mem. chunk is 1
++
++ if (NdisEqualMemory (dst, src, sz))
++ return _TRUE;
++ else
++ return _FALSE;
++
++#endif
++
++
++
++}
++
++void _rtw_memset(void *pbuf, int c, u32 sz)
++{
++
++#if defined (PLATFORM_LINUX)|| defined (PLATFORM_FREEBSD)
++
++ memset(pbuf, c, sz);
++
++#endif
++
++#ifdef PLATFORM_WINDOWS
++#if 0
++ NdisZeroMemory(pbuf, sz);
++ if (c != 0) memset(pbuf, c, sz);
++#else
++ NdisFillMemory(pbuf, sz, c);
++#endif
++#endif
++
++}
++
++#ifdef PLATFORM_FREEBSD
++static inline void __list_add(_list *pnew, _list *pprev, _list *pnext)
++ {
++ pnext->prev = pnew;
++ pnew->next = pnext;
++ pnew->prev = pprev;
++ pprev->next = pnew;
++}
++#endif /* PLATFORM_FREEBSD */
++
++void _rtw_init_listhead(_list *list)
++{
++
++#ifdef PLATFORM_LINUX
++
++ INIT_LIST_HEAD(list);
++
++#endif
++
++#ifdef PLATFORM_FREEBSD
++ list->next = list;
++ list->prev = list;
++#endif
++#ifdef PLATFORM_WINDOWS
++
++ NdisInitializeListHead(list);
++
++#endif
++
++}
++
++
++/*
++For the following list_xxx operations,
++caller must guarantee the atomic context.
++Otherwise, there will be racing condition.
++*/
++u32 rtw_is_list_empty(_list *phead)
++{
++
++#ifdef PLATFORM_LINUX
++
++ if (list_empty(phead))
++ return _TRUE;
++ else
++ return _FALSE;
++
++#endif
++#ifdef PLATFORM_FREEBSD
++
++ if (phead->next == phead)
++ return _TRUE;
++ else
++ return _FALSE;
++
++#endif
++
++
++#ifdef PLATFORM_WINDOWS
++
++ if (IsListEmpty(phead))
++ return _TRUE;
++ else
++ return _FALSE;
++
++#endif
++
++
++}
++
++void rtw_list_insert_head(_list *plist, _list *phead)
++{
++
++#ifdef PLATFORM_LINUX
++ list_add(plist, phead);
++#endif
++
++#ifdef PLATFORM_FREEBSD
++ __list_add(plist, phead, phead->next);
++#endif
++
++#ifdef PLATFORM_WINDOWS
++ InsertHeadList(phead, plist);
++#endif
++}
++
++void rtw_list_insert_tail(_list *plist, _list *phead)
++{
++
++#ifdef PLATFORM_LINUX
++
++ list_add_tail(plist, phead);
++
++#endif
++#ifdef PLATFORM_FREEBSD
++
++ __list_add(plist, phead->prev, phead);
++
++#endif
++#ifdef PLATFORM_WINDOWS
++
++ InsertTailList(phead, plist);
++
++#endif
++
++}
++
++
++/*
++
++Caller must check if the list is empty before calling rtw_list_delete
++
++*/
++
++
++void _rtw_init_sema(_sema *sema, int init_val)
++{
++
++#ifdef PLATFORM_LINUX
++
++ sema_init(sema, init_val);
++
++#endif
++#ifdef PLATFORM_FREEBSD
++ sema_init(sema, init_val, "rtw_drv");
++#endif
++#ifdef PLATFORM_OS_XP
++
++ KeInitializeSemaphore(sema, init_val, SEMA_UPBND); // count=0;
++
++#endif
++
++#ifdef PLATFORM_OS_CE
++ if(*sema == NULL)
++ *sema = CreateSemaphore(NULL, init_val, SEMA_UPBND, NULL);
++#endif
++
++}
++
++void _rtw_free_sema(_sema *sema)
++{
++#ifdef PLATFORM_FREEBSD
++ sema_destroy(sema);
++#endif
++#ifdef PLATFORM_OS_CE
++ CloseHandle(*sema);
++#endif
++
++}
++
++void _rtw_up_sema(_sema *sema)
++{
++
++#ifdef PLATFORM_LINUX
++
++ up(sema);
++
++#endif
++#ifdef PLATFORM_FREEBSD
++ sema_post(sema);
++#endif
++#ifdef PLATFORM_OS_XP
++
++ KeReleaseSemaphore(sema, IO_NETWORK_INCREMENT, 1, FALSE );
++
++#endif
++
++#ifdef PLATFORM_OS_CE
++ ReleaseSemaphore(*sema, 1, NULL );
++#endif
++}
++
++u32 _rtw_down_sema(_sema *sema)
++{
++
++#ifdef PLATFORM_LINUX
++
++ if (down_interruptible(sema))
++ return _FAIL;
++ else
++ return _SUCCESS;
++
++#endif
++#ifdef PLATFORM_FREEBSD
++ sema_wait(sema);
++ return _SUCCESS;
++#endif
++#ifdef PLATFORM_OS_XP
++
++ if(STATUS_SUCCESS == KeWaitForSingleObject(sema, Executive, KernelMode, TRUE, NULL))
++ return _SUCCESS;
++ else
++ return _FAIL;
++#endif
++
++#ifdef PLATFORM_OS_CE
++ if(WAIT_OBJECT_0 == WaitForSingleObject(*sema, INFINITE ))
++ return _SUCCESS;
++ else
++ return _FAIL;
++#endif
++}
++
++
++
++void _rtw_mutex_init(_mutex *pmutex)
++{
++#ifdef PLATFORM_LINUX
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37))
++ mutex_init(pmutex);
++#else
++ init_MUTEX(pmutex);
++#endif
++
++#endif
++#ifdef PLATFORM_FREEBSD
++ mtx_init(pmutex, "", NULL, MTX_DEF|MTX_RECURSE);
++#endif
++#ifdef PLATFORM_OS_XP
++
++ KeInitializeMutex(pmutex, 0);
++
++#endif
++
++#ifdef PLATFORM_OS_CE
++ *pmutex = CreateMutex( NULL, _FALSE, NULL);
++#endif
++}
++
++void _rtw_mutex_free(_mutex *pmutex);
++void _rtw_mutex_free(_mutex *pmutex)
++{
++#ifdef PLATFORM_LINUX
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37))
++ mutex_destroy(pmutex);
++#else
++#endif
++
++#ifdef PLATFORM_FREEBSD
++ sema_destroy(pmutex);
++#endif
++
++#endif
++
++#ifdef PLATFORM_OS_XP
++
++#endif
++
++#ifdef PLATFORM_OS_CE
++
++#endif
++}
++
++void _rtw_spinlock_init(_lock *plock)
++{
++
++#ifdef PLATFORM_LINUX
++
++ spin_lock_init(plock);
++
++#endif
++#ifdef PLATFORM_FREEBSD
++ mtx_init(plock, "", NULL, MTX_DEF|MTX_RECURSE);
++#endif
++#ifdef PLATFORM_WINDOWS
++
++ NdisAllocateSpinLock(plock);
++
++#endif
++
++}
++
++void _rtw_spinlock_free(_lock *plock)
++{
++#ifdef PLATFORM_FREEBSD
++ mtx_destroy(plock);
++#endif
++
++#ifdef PLATFORM_WINDOWS
++
++ NdisFreeSpinLock(plock);
++
++#endif
++
++}
++#ifdef PLATFORM_FREEBSD
++extern PADAPTER prtw_lock;
++
++void rtw_mtx_lock(_lock *plock){
++ if(prtw_lock){
++ mtx_lock(&prtw_lock->glock);
++ }
++ else{
++ printf("%s prtw_lock==NULL",__FUNCTION__);
++ }
++}
++void rtw_mtx_unlock(_lock *plock){
++ if(prtw_lock){
++ mtx_unlock(&prtw_lock->glock);
++ }
++ else{
++ printf("%s prtw_lock==NULL",__FUNCTION__);
++ }
++
++}
++#endif //PLATFORM_FREEBSD
++
++
++void _rtw_spinlock(_lock *plock)
++{
++
++#ifdef PLATFORM_LINUX
++
++ spin_lock(plock);
++
++#endif
++#ifdef PLATFORM_FREEBSD
++ mtx_lock(plock);
++#endif
++#ifdef PLATFORM_WINDOWS
++
++ NdisAcquireSpinLock(plock);
++
++#endif
++
++}
++
++void _rtw_spinunlock(_lock *plock)
++{
++
++#ifdef PLATFORM_LINUX
++
++ spin_unlock(plock);
++
++#endif
++#ifdef PLATFORM_FREEBSD
++ mtx_unlock(plock);
++#endif
++#ifdef PLATFORM_WINDOWS
++
++ NdisReleaseSpinLock(plock);
++
++#endif
++}
++
++
++void _rtw_spinlock_ex(_lock *plock)
++{
++
++#ifdef PLATFORM_LINUX
++
++ spin_lock(plock);
++
++#endif
++#ifdef PLATFORM_FREEBSD
++ mtx_lock(plock);
++#endif
++#ifdef PLATFORM_WINDOWS
++
++ NdisDprAcquireSpinLock(plock);
++
++#endif
++
++}
++
++void _rtw_spinunlock_ex(_lock *plock)
++{
++
++#ifdef PLATFORM_LINUX
++
++ spin_unlock(plock);
++
++#endif
++#ifdef PLATFORM_FREEBSD
++ mtx_unlock(plock);
++#endif
++#ifdef PLATFORM_WINDOWS
++
++ NdisDprReleaseSpinLock(plock);
++
++#endif
++}
++
++
++
++void _rtw_init_queue(_queue *pqueue)
++{
++
++ _rtw_init_listhead(&(pqueue->queue));
++
++ _rtw_spinlock_init(&(pqueue->lock));
++
++}
++
++u32 _rtw_queue_empty(_queue *pqueue)
++{
++ return (rtw_is_list_empty(&(pqueue->queue)));
++}
++
++
++u32 rtw_end_of_queue_search(_list *head, _list *plist)
++{
++ if (head == plist)
++ return _TRUE;
++ else
++ return _FALSE;
++}
++
++
++u32 rtw_get_current_time(void)
++{
++
++#ifdef PLATFORM_LINUX
++ return jiffies;
++#endif
++#ifdef PLATFORM_FREEBSD
++ struct timeval tvp;
++ getmicrotime(&tvp);
++ return tvp.tv_sec;
++#endif
++#ifdef PLATFORM_WINDOWS
++ LARGE_INTEGER SystemTime;
++ NdisGetCurrentSystemTime(&SystemTime);
++ return (u32)(SystemTime.LowPart);// count of 100-nanosecond intervals
++#endif
++}
++
++inline u32 rtw_systime_to_ms(u32 systime)
++{
++#ifdef PLATFORM_LINUX
++ return systime * 1000 / HZ;
++#endif
++#ifdef PLATFORM_FREEBSD
++ return systime * 1000;
++#endif
++#ifdef PLATFORM_WINDOWS
++ return systime / 10000 ;
++#endif
++}
++
++inline u32 rtw_ms_to_systime(u32 ms)
++{
++#ifdef PLATFORM_LINUX
++ return ms * HZ / 1000;
++#endif
++#ifdef PLATFORM_FREEBSD
++ return ms /1000;
++#endif
++#ifdef PLATFORM_WINDOWS
++ return ms * 10000 ;
++#endif
++}
++
++// the input parameter start use the same unit as returned by rtw_get_current_time
++inline s32 rtw_get_passing_time_ms(u32 start)
++{
++#ifdef PLATFORM_LINUX
++ return rtw_systime_to_ms(jiffies-start);
++#endif
++#ifdef PLATFORM_FREEBSD
++ return rtw_systime_to_ms(rtw_get_current_time());
++#endif
++#ifdef PLATFORM_WINDOWS
++ LARGE_INTEGER SystemTime;
++ NdisGetCurrentSystemTime(&SystemTime);
++ return rtw_systime_to_ms((u32)(SystemTime.LowPart) - start) ;
++#endif
++}
++
++inline s32 rtw_get_time_interval_ms(u32 start, u32 end)
++{
++#ifdef PLATFORM_LINUX
++ return rtw_systime_to_ms(end-start);
++#endif
++#ifdef PLATFORM_FREEBSD
++ return rtw_systime_to_ms(rtw_get_current_time());
++#endif
++#ifdef PLATFORM_WINDOWS
++ return rtw_systime_to_ms(end-start);
++#endif
++}
++
++
++void rtw_sleep_schedulable(int ms)
++{
++
++#ifdef PLATFORM_LINUX
++
++ u32 delta;
++
++ delta = (ms * HZ)/1000;//(ms)
++ if (delta == 0) {
++ delta = 1;// 1 ms
++ }
++ set_current_state(TASK_INTERRUPTIBLE);
++ if (schedule_timeout(delta) != 0) {
++ return ;
++ }
++ return;
++
++#endif
++#ifdef PLATFORM_FREEBSD
++ DELAY(ms*1000);
++ return ;
++#endif
++
++#ifdef PLATFORM_WINDOWS
++
++ NdisMSleep(ms*1000); //(us)*1000=(ms)
++
++#endif
++
++}
++
++
++void rtw_msleep_os(int ms)
++{
++
++#ifdef PLATFORM_LINUX
++
++ msleep((unsigned int)ms);
++
++#endif
++#ifdef PLATFORM_FREEBSD
++ //Delay for delay microseconds
++ DELAY(ms*1000);
++ return ;
++#endif
++#ifdef PLATFORM_WINDOWS
++
++ NdisMSleep(ms*1000); //(us)*1000=(ms)
++
++#endif
++
++
++}
++void rtw_usleep_os(int us)
++{
++
++#ifdef PLATFORM_LINUX
++
++ // msleep((unsigned int)us);
++ if ( 1 < (us/1000) )
++ msleep(1);
++ else
++ msleep( (us/1000) + 1);
++
++#endif
++#ifdef PLATFORM_FREEBSD
++ //Delay for delay microseconds
++ DELAY(us);
++
++ return ;
++#endif
++#ifdef PLATFORM_WINDOWS
++
++ NdisMSleep(us); //(us)
++
++#endif
++
++
++}
++
++
++#ifdef DBG_DELAY_OS
++void _rtw_mdelay_os(int ms, const char *func, const int line)
++{
++ #if 0
++ if(ms>10)
++ DBG_871X("%s:%d %s(%d)\n", func, line, __FUNCTION__, ms);
++ rtw_msleep_os(ms);
++ return;
++ #endif
++
++
++ DBG_871X("%s:%d %s(%d)\n", func, line, __FUNCTION__, ms);
++
++#if defined(PLATFORM_LINUX)
++
++ mdelay((unsigned long)ms);
++
++#elif defined(PLATFORM_WINDOWS)
++
++ NdisStallExecution(ms*1000); //(us)*1000=(ms)
++
++#endif
++
++
++}
++void _rtw_udelay_os(int us, const char *func, const int line)
++{
++
++ #if 0
++ if(us > 1000) {
++ DBG_871X("%s:%d %s(%d)\n", func, line, __FUNCTION__, us);
++ rtw_usleep_os(us);
++ return;
++ }
++ #endif
++
++
++ DBG_871X("%s:%d %s(%d)\n", func, line, __FUNCTION__, us);
++
++
++#if defined(PLATFORM_LINUX)
++
++ udelay((unsigned long)us);
++
++#elif defined(PLATFORM_WINDOWS)
++
++ NdisStallExecution(us); //(us)
++
++#endif
++
++}
++#else
++void rtw_mdelay_os(int ms)
++{
++
++#ifdef PLATFORM_LINUX
++
++ mdelay((unsigned long)ms);
++
++#endif
++#ifdef PLATFORM_FREEBSD
++ DELAY(ms*1000);
++ return ;
++#endif
++#ifdef PLATFORM_WINDOWS
++
++ NdisStallExecution(ms*1000); //(us)*1000=(ms)
++
++#endif
++
++
++}
++void rtw_udelay_os(int us)
++{
++
++#ifdef PLATFORM_LINUX
++
++ udelay((unsigned long)us);
++
++#endif
++#ifdef PLATFORM_FREEBSD
++ //Delay for delay microseconds
++ DELAY(us);
++ return ;
++#endif
++#ifdef PLATFORM_WINDOWS
++
++ NdisStallExecution(us); //(us)
++
++#endif
++
++}
++#endif
++
++void rtw_yield_os()
++{
++#ifdef PLATFORM_LINUX
++ yield();
++#endif
++#ifdef PLATFORM_FREEBSD
++ yield();
++#endif
++#ifdef PLATFORM_WINDOWS
++ SwitchToThread();
++#endif
++}
++
++#define RTW_SUSPEND_LOCK_NAME "rtw_wifi"
++
++#ifdef CONFIG_WAKELOCK
++static struct wake_lock rtw_suspend_lock;
++#elif defined(CONFIG_ANDROID_POWER)
++static android_suspend_lock_t rtw_suspend_lock ={
++ .name = RTW_SUSPEND_LOCK_NAME
++};
++#endif
++
++inline void rtw_suspend_lock_init()
++{
++ #ifdef CONFIG_WAKELOCK
++ wake_lock_init(&rtw_suspend_lock, WAKE_LOCK_SUSPEND, RTW_SUSPEND_LOCK_NAME);
++ #elif defined(CONFIG_ANDROID_POWER)
++ android_init_suspend_lock(&rtw_suspend_lock);
++ #endif
++}
++
++inline void rtw_suspend_lock_uninit()
++{
++ #ifdef CONFIG_WAKELOCK
++ wake_lock_destroy(&rtw_suspend_lock);
++ #elif defined(CONFIG_ANDROID_POWER)
++ android_uninit_suspend_lock(&rtw_suspend_lock);
++ #endif
++}
++
++inline void rtw_lock_suspend()
++{
++ #ifdef CONFIG_WAKELOCK
++ wake_lock(&rtw_suspend_lock);
++ #elif defined(CONFIG_ANDROID_POWER)
++ android_lock_suspend(&rtw_suspend_lock);
++ #endif
++}
++
++inline void rtw_unlock_suspend()
++{
++ #ifdef CONFIG_WAKELOCK
++ wake_unlock(&rtw_suspend_lock);
++ #elif defined(CONFIG_ANDROID_POWER)
++ android_unlock_suspend(&rtw_suspend_lock);
++ #endif
++}
++
++inline void rtw_lock_suspend_timeout(u32 timeout_ms)
++{
++ #ifdef CONFIG_WAKELOCK
++ wake_lock_timeout(&rtw_suspend_lock, rtw_ms_to_systime(timeout_ms));
++ #elif defined(CONFIG_ANDROID_POWER)
++ android_lock_suspend_auto_expire(&rtw_suspend_lock, rtw_ms_to_systime(timeout_ms));
++ #endif
++}
++
++inline void ATOMIC_SET(ATOMIC_T *v, int i)
++{
++ #ifdef PLATFORM_LINUX
++ atomic_set(v,i);
++ #elif defined(PLATFORM_WINDOWS)
++ *v=i;// other choice????
++ #elif defined(PLATFORM_FREEBSD)
++ atomic_set_int(v,i);
++ #endif
++}
++
++inline int ATOMIC_READ(ATOMIC_T *v)
++{
++ #ifdef PLATFORM_LINUX
++ return atomic_read(v);
++ #elif defined(PLATFORM_WINDOWS)
++ return *v; // other choice????
++ #elif defined(PLATFORM_FREEBSD)
++ return atomic_load_acq_32(v);
++ #endif
++}
++
++inline void ATOMIC_ADD(ATOMIC_T *v, int i)
++{
++ #ifdef PLATFORM_LINUX
++ atomic_add(i,v);
++ #elif defined(PLATFORM_WINDOWS)
++ InterlockedAdd(v,i);
++ #elif defined(PLATFORM_FREEBSD)
++ atomic_add_int(v,i);
++ #endif
++}
++inline void ATOMIC_SUB(ATOMIC_T *v, int i)
++{
++ #ifdef PLATFORM_LINUX
++ atomic_sub(i,v);
++ #elif defined(PLATFORM_WINDOWS)
++ InterlockedAdd(v,-i);
++ #elif defined(PLATFORM_FREEBSD)
++ atomic_subtract_int(v,i);
++ #endif
++}
++
++inline void ATOMIC_INC(ATOMIC_T *v)
++{
++ #ifdef PLATFORM_LINUX
++ atomic_inc(v);
++ #elif defined(PLATFORM_WINDOWS)
++ InterlockedIncrement(v);
++ #elif defined(PLATFORM_FREEBSD)
++ atomic_add_int(v,1);
++ #endif
++}
++
++inline void ATOMIC_DEC(ATOMIC_T *v)
++{
++ #ifdef PLATFORM_LINUX
++ atomic_dec(v);
++ #elif defined(PLATFORM_WINDOWS)
++ InterlockedDecrement(v);
++ #elif defined(PLATFORM_FREEBSD)
++ atomic_subtract_int(v,1);
++ #endif
++}
++
++inline int ATOMIC_ADD_RETURN(ATOMIC_T *v, int i)
++{
++ #ifdef PLATFORM_LINUX
++ return atomic_add_return(i,v);
++ #elif defined(PLATFORM_WINDOWS)
++ return InterlockedAdd(v,i);
++ #elif defined(PLATFORM_FREEBSD)
++ atomic_add_int(v,i);
++ return atomic_load_acq_32(v);
++ #endif
++}
++
++inline int ATOMIC_SUB_RETURN(ATOMIC_T *v, int i)
++{
++ #ifdef PLATFORM_LINUX
++ return atomic_sub_return(i,v);
++ #elif defined(PLATFORM_WINDOWS)
++ return InterlockedAdd(v,-i);
++ #elif defined(PLATFORM_FREEBSD)
++ atomic_subtract_int(v,i);
++ return atomic_load_acq_32(v);
++ #endif
++}
++
++inline int ATOMIC_INC_RETURN(ATOMIC_T *v)
++{
++ #ifdef PLATFORM_LINUX
++ return atomic_inc_return(v);
++ #elif defined(PLATFORM_WINDOWS)
++ return InterlockedIncrement(v);
++ #elif defined(PLATFORM_FREEBSD)
++ atomic_add_int(v,1);
++ return atomic_load_acq_32(v);
++ #endif
++}
++
++inline int ATOMIC_DEC_RETURN(ATOMIC_T *v)
++{
++ #ifdef PLATFORM_LINUX
++ return atomic_dec_return(v);
++ #elif defined(PLATFORM_WINDOWS)
++ return InterlockedDecrement(v);
++ #elif defined(PLATFORM_FREEBSD)
++ atomic_subtract_int(v,1);
++ return atomic_load_acq_32(v);
++ #endif
++}
++
++
++#ifdef PLATFORM_LINUX
++/*
++* Open a file with the specific @param path, @param flag, @param mode
++* @param fpp the pointer of struct file pointer to get struct file pointer while file opening is success
++* @param path the path of the file to open
++* @param flag file operation flags, please refer to linux document
++* @param mode please refer to linux document
++* @return Linux specific error code
++*/
++static int openFile(struct file **fpp, char *path, int flag, int mode)
++{
++ struct file *fp;
++
++ fp=filp_open(path, flag, mode);
++ if(IS_ERR(fp)) {
++ *fpp=NULL;
++ return PTR_ERR(fp);
++ }
++ else {
++ *fpp=fp;
++ return 0;
++ }
++}
++
++/*
++* Close the file with the specific @param fp
++* @param fp the pointer of struct file to close
++* @return always 0
++*/
++static int closeFile(struct file *fp)
++{
++ filp_close(fp,NULL);
++ return 0;
++}
++
++static int readFile(struct file *fp,char *buf,int len)
++{
++ int rlen=0, sum=0;
++
++ if (!fp->f_op || !fp->f_op->read)
++ return -EPERM;
++
++ while(sum<len) {
++ rlen=fp->f_op->read(fp,buf+sum,len-sum, &fp->f_pos);
++ if(rlen>0)
++ sum+=rlen;
++ else if(0 != rlen)
++ return rlen;
++ else
++ break;
++ }
++
++ return sum;
++
++}
++
++static int writeFile(struct file *fp,char *buf,int len)
++{
++ int wlen=0, sum=0;
++
++ if (!fp->f_op || !fp->f_op->write)
++ return -EPERM;
++
++ while(sum<len) {
++ wlen=fp->f_op->write(fp,buf+sum,len-sum, &fp->f_pos);
++ if(wlen>0)
++ sum+=wlen;
++ else if(0 != wlen)
++ return wlen;
++ else
++ break;
++ }
++
++ return sum;
++
++}
++
++/*
++* Test if the specifi @param path is a file and readable
++* @param path the path of the file to test
++* @return Linux specific error code
++*/
++static int isFileReadable(char *path)
++{
++ struct file *fp;
++ int ret = 0;
++ mm_segment_t oldfs;
++ char buf;
++
++ fp=filp_open(path, O_RDONLY, 0);
++ if(IS_ERR(fp)) {
++ ret = PTR_ERR(fp);
++ }
++ else {
++ oldfs = get_fs(); set_fs(get_ds());
++
++ if(1!=readFile(fp, &buf, 1))
++ ret = PTR_ERR(fp);
++
++ set_fs(oldfs);
++ filp_close(fp,NULL);
++ }
++ return ret;
++}
++
++/*
++* Open the file with @param path and retrive the file content into memory starting from @param buf for @param sz at most
++* @param path the path of the file to open and read
++* @param buf the starting address of the buffer to store file content
++* @param sz how many bytes to read at most
++* @return the byte we've read, or Linux specific error code
++*/
++static int retriveFromFile(char *path, u8* buf, u32 sz)
++{
++ int ret =-1;
++ mm_segment_t oldfs;
++ struct file *fp;
++
++ if(path && buf) {
++ if( 0 == (ret=openFile(&fp,path, O_RDONLY, 0)) ){
++ DBG_871X("%s openFile path:%s fp=%p\n",__FUNCTION__, path ,fp);
++
++ oldfs = get_fs(); set_fs(get_ds());
++ ret=readFile(fp, buf, sz);
++ set_fs(oldfs);
++ closeFile(fp);
++
++ DBG_871X("%s readFile, ret:%d\n",__FUNCTION__, ret);
++
++ } else {
++ DBG_871X("%s openFile path:%s Fail, ret:%d\n",__FUNCTION__, path, ret);
++ }
++ } else {
++ DBG_871X("%s NULL pointer\n",__FUNCTION__);
++ ret = -EINVAL;
++ }
++ return ret;
++}
++
++/*
++* Open the file with @param path and wirte @param sz byte of data starting from @param buf into the file
++* @param path the path of the file to open and write
++* @param buf the starting address of the data to write into file
++* @param sz how many bytes to write at most
++* @return the byte we've written, or Linux specific error code
++*/
++static int storeToFile(char *path, u8* buf, u32 sz)
++{
++ int ret =0;
++ mm_segment_t oldfs;
++ struct file *fp;
++
++ if(path && buf) {
++ if( 0 == (ret=openFile(&fp, path, O_CREAT|O_WRONLY, 0666)) ) {
++ DBG_871X("%s openFile path:%s fp=%p\n",__FUNCTION__, path ,fp);
++
++ oldfs = get_fs(); set_fs(get_ds());
++ ret=writeFile(fp, buf, sz);
++ set_fs(oldfs);
++ closeFile(fp);
++
++ DBG_871X("%s writeFile, ret:%d\n",__FUNCTION__, ret);
++
++ } else {
++ DBG_871X("%s openFile path:%s Fail, ret:%d\n",__FUNCTION__, path, ret);
++ }
++ } else {
++ DBG_871X("%s NULL pointer\n",__FUNCTION__);
++ ret = -EINVAL;
++ }
++ return ret;
++}
++#endif //PLATFORM_LINUX
++
++/*
++* Test if the specifi @param path is a file and readable
++* @param path the path of the file to test
++* @return _TRUE or _FALSE
++*/
++int rtw_is_file_readable(char *path)
++{
++#ifdef PLATFORM_LINUX
++ if(isFileReadable(path) == 0)
++ return _TRUE;
++ else
++ return _FALSE;
++#else
++ //Todo...
++ return _FALSE;
++#endif
++}
++
++/*
++* Open the file with @param path and retrive the file content into memory starting from @param buf for @param sz at most
++* @param path the path of the file to open and read
++* @param buf the starting address of the buffer to store file content
++* @param sz how many bytes to read at most
++* @return the byte we've read
++*/
++int rtw_retrive_from_file(char *path, u8* buf, u32 sz)
++{
++#ifdef PLATFORM_LINUX
++ int ret =retriveFromFile(path, buf, sz);
++ return ret>=0?ret:0;
++#else
++ //Todo...
++ return 0;
++#endif
++}
++
++/*
++* Open the file with @param path and wirte @param sz byte of data starting from @param buf into the file
++* @param path the path of the file to open and write
++* @param buf the starting address of the data to write into file
++* @param sz how many bytes to write at most
++* @return the byte we've written
++*/
++int rtw_store_to_file(char *path, u8* buf, u32 sz)
++{
++#ifdef PLATFORM_LINUX
++ int ret =storeToFile(path, buf, sz);
++ return ret>=0?ret:0;
++#else
++ //Todo...
++ return 0;
++#endif
++}
++
++#if 1 //#ifdef MEM_ALLOC_REFINE_ADAPTOR
++#ifdef PLATFORM_LINUX
++struct net_device *rtw_alloc_etherdev_with_old_priv(int sizeof_priv, void *old_priv)
++{
++ struct net_device *pnetdev;
++ struct rtw_netdev_priv_indicator *pnpi;
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35))
++ pnetdev = alloc_etherdev_mq(sizeof(struct rtw_netdev_priv_indicator), 4);
++#else
++ pnetdev = alloc_etherdev(sizeof(struct rtw_netdev_priv_indicator));
++#endif
++ if (!pnetdev)
++ goto RETURN;
++
++ pnpi = netdev_priv(pnetdev);
++ pnpi->priv=old_priv;
++ pnpi->sizeof_priv=sizeof_priv;
++
++RETURN:
++ return pnetdev;
++}
++
++struct net_device *rtw_alloc_etherdev(int sizeof_priv)
++{
++ struct net_device *pnetdev;
++ struct rtw_netdev_priv_indicator *pnpi;
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35))
++ pnetdev = alloc_etherdev_mq(sizeof(struct rtw_netdev_priv_indicator), 4);
++#else
++ pnetdev = alloc_etherdev(sizeof(struct rtw_netdev_priv_indicator));
++#endif
++ if (!pnetdev)
++ goto RETURN;
++
++ pnpi = netdev_priv(pnetdev);
++
++ pnpi->priv = rtw_zvmalloc(sizeof_priv);
++ if (!pnpi->priv) {
++ free_netdev(pnetdev);
++ pnetdev = NULL;
++ goto RETURN;
++ }
++
++ pnpi->sizeof_priv=sizeof_priv;
++RETURN:
++ return pnetdev;
++}
++
++void rtw_free_netdev(struct net_device * netdev)
++{
++ struct rtw_netdev_priv_indicator *pnpi;
++
++ if(!netdev)
++ goto RETURN;
++
++ pnpi = netdev_priv(netdev);
++
++ if(!pnpi->priv)
++ goto RETURN;
++
++ rtw_vmfree(pnpi->priv, pnpi->sizeof_priv);
++ free_netdev(netdev);
++
++RETURN:
++ return;
++}
++
++/*
++* Jeff: this function should be called under ioctl (rtnl_lock is accquired) while
++* LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26)
++*/
++int rtw_change_ifname(_adapter *padapter, const char *ifname)
++{
++ struct net_device *pnetdev;
++ struct net_device *cur_pnetdev = padapter->pnetdev;
++ struct rereg_nd_name_data *rereg_priv;
++ int ret;
++
++ if(!padapter)
++ goto error;
++
++ rereg_priv = &padapter->rereg_nd_name_priv;
++
++ //free the old_pnetdev
++ if(rereg_priv->old_pnetdev) {
++ free_netdev(rereg_priv->old_pnetdev);
++ rereg_priv->old_pnetdev = NULL;
++ }
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26))
++ if(!rtnl_is_locked())
++ unregister_netdev(cur_pnetdev);
++ else
++#endif
++ unregister_netdevice(cur_pnetdev);
++
++ rtw_proc_remove_one(cur_pnetdev);
++
++ rereg_priv->old_pnetdev=cur_pnetdev;
++
++ pnetdev = rtw_init_netdev(padapter);
++ if (!pnetdev) {
++ ret = -1;
++ goto error;
++ }
++
++ SET_NETDEV_DEV(pnetdev, dvobj_to_dev(adapter_to_dvobj(padapter)));
++
++ rtw_init_netdev_name(pnetdev, ifname);
++
++ _rtw_memcpy(pnetdev->dev_addr, padapter->eeprompriv.mac_addr, ETH_ALEN);
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26))
++ if(!rtnl_is_locked())
++ ret = register_netdev(pnetdev);
++ else
++#endif
++ ret = register_netdevice(pnetdev);
++
++ if ( ret != 0) {
++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("register_netdev() failed\n"));
++ goto error;
++ }
++
++ rtw_proc_init_one(pnetdev);
++
++ return 0;
++
++error:
++
++ return -1;
++
++}
++#endif
++#endif //MEM_ALLOC_REFINE_ADAPTOR
++
++#ifdef PLATFORM_FREEBSD
++/*
++ * Copy a buffer from userspace and write into kernel address
++ * space.
++ *
++ * This emulation just calls the FreeBSD copyin function (to
++ * copy data from user space buffer into a kernel space buffer)
++ * and is designed to be used with the above io_write_wrapper.
++ *
++ * This function should return the number of bytes not copied.
++ * I.e. success results in a zero value.
++ * Negative error values are not returned.
++ */
++unsigned long
++copy_from_user(void *to, const void *from, unsigned long n)
++{
++ if ( copyin(from, to, n) != 0 ) {
++ /* Any errors will be treated as a failure
++ to copy any of the requested bytes */
++ return n;
++ }
++
++ return 0;
++}
++
++unsigned long
++copy_to_user(void *to, const void *from, unsigned long n)
++{
++ if ( copyout(from, to, n) != 0 ) {
++ /* Any errors will be treated as a failure
++ to copy any of the requested bytes */
++ return n;
++ }
++
++ return 0;
++}
++
++
++/*
++ * The usb_register and usb_deregister functions are used to register
++ * usb drivers with the usb subsystem. In this compatibility layer
++ * emulation a list of drivers (struct usb_driver) is maintained
++ * and is used for probing/attaching etc.
++ *
++ * usb_register and usb_deregister simply call these functions.
++ */
++int
++usb_register(struct usb_driver *driver)
++{
++ rtw_usb_linux_register(driver);
++ return 0;
++}
++
++
++int
++usb_deregister(struct usb_driver *driver)
++{
++ rtw_usb_linux_deregister(driver);
++ return 0;
++}
++
++void module_init_exit_wrapper(void *arg)
++{
++ int (*func)(void) = arg;
++ func();
++ return;
++}
++
++#endif //PLATFORM_FREEBSD
++u64 rtw_modular64(u64 x, u64 y)
++{
++#ifdef PLATFORM_LINUX
++ return do_div(x, y);
++#elif defined(PLATFORM_WINDOWS)
++ return (x % y);
++#elif defined(PLATFORM_FREEBSD)
++ return (x %y);
++#endif
++}
++
++u64 rtw_division64(u64 x, u64 y)
++{
++#ifdef PLATFORM_LINUX
++ do_div(x, y);
++ return x;
++#elif defined(PLATFORM_WINDOWS)
++ return (x / y);
++#elif defined(PLATFORM_FREEBSD)
++ return (x / y);
++#endif
++}
++
++void rtw_buf_free(u8 **buf, u32 *buf_len)
++{
++ u32 ori_len;
++
++ if (!buf || !buf_len)
++ return;
++
++ ori_len = *buf_len;
++
++ if (*buf) {
++ u32 tmp_buf_len = *buf_len;
++ *buf_len = 0;
++ rtw_mfree(*buf, tmp_buf_len);
++ *buf = NULL;
++ }
++}
++
++void rtw_buf_update(u8 **buf, u32 *buf_len, u8 *src, u32 src_len)
++{
++ u32 ori_len = 0, dup_len = 0;
++ u8 *ori = NULL;
++ u8 *dup = NULL;
++
++ if (!buf || !buf_len)
++ return;
++
++ if (!src || !src_len)
++ goto keep_ori;
++
++ /* duplicate src */
++ dup = rtw_malloc(src_len);
++ if (dup) {
++ dup_len = src_len;
++ _rtw_memcpy(dup, src, dup_len);
++ }
++
++keep_ori:
++ ori = *buf;
++ ori_len = *buf_len;
++
++ /* replace buf with dup */
++ *buf_len = 0;
++ *buf = dup;
++ *buf_len = dup_len;
++
++ /* free ori */
++ if (ori && ori_len > 0)
++ rtw_mfree(ori, ori_len);
++}
++
++
++/**
++ * rtw_cbuf_full - test if cbuf is full
++ * @cbuf: pointer of struct rtw_cbuf
++ *
++ * Returns: _TRUE if cbuf is full
++ */
++inline bool rtw_cbuf_full(struct rtw_cbuf *cbuf)
++{
++ return (cbuf->write == cbuf->read-1)? _TRUE : _FALSE;
++}
++
++/**
++ * rtw_cbuf_empty - test if cbuf is empty
++ * @cbuf: pointer of struct rtw_cbuf
++ *
++ * Returns: _TRUE if cbuf is empty
++ */
++inline bool rtw_cbuf_empty(struct rtw_cbuf *cbuf)
++{
++ return (cbuf->write == cbuf->read)? _TRUE : _FALSE;
++}
++
++/**
++ * rtw_cbuf_push - push a pointer into cbuf
++ * @cbuf: pointer of struct rtw_cbuf
++ * @buf: pointer to push in
++ *
++ * Lock free operation, be careful of the use scheme
++ * Returns: _TRUE push success
++ */
++bool rtw_cbuf_push(struct rtw_cbuf *cbuf, void *buf)
++{
++ if (rtw_cbuf_full(cbuf))
++ return _FAIL;
++
++ if (0)
++ DBG_871X("%s on %u\n", __func__, cbuf->write);
++ cbuf->bufs[cbuf->write] = buf;
++ cbuf->write = (cbuf->write+1)%cbuf->size;
++
++ return _SUCCESS;
++}
++
++/**
++ * rtw_cbuf_pop - pop a pointer from cbuf
++ * @cbuf: pointer of struct rtw_cbuf
++ *
++ * Lock free operation, be careful of the use scheme
++ * Returns: pointer popped out
++ */
++void *rtw_cbuf_pop(struct rtw_cbuf *cbuf)
++{
++ void *buf;
++ if (rtw_cbuf_empty(cbuf))
++ return NULL;
++
++ if (0)
++ DBG_871X("%s on %u\n", __func__, cbuf->read);
++ buf = cbuf->bufs[cbuf->read];
++ cbuf->read = (cbuf->read+1)%cbuf->size;
++
++ return buf;
++}
++
++/**
++ * rtw_cbuf_alloc - allocte a rtw_cbuf with given size and do initialization
++ * @size: size of pointer
++ *
++ * Returns: pointer of srtuct rtw_cbuf, NULL for allocation failure
++ */
++struct rtw_cbuf *rtw_cbuf_alloc(u32 size)
++{
++ struct rtw_cbuf *cbuf;
++
++ cbuf = (struct rtw_cbuf *)rtw_malloc(sizeof(*cbuf) + sizeof(void*)*size);
++
++ if (cbuf) {
++ cbuf->write = cbuf->read = 0;
++ cbuf->size = size;
++ }
++
++ return cbuf;
++}
++
++/**
++ * rtw_cbuf_free - free the given rtw_cbuf
++ * @cbuf: pointer of struct rtw_cbuf to free
++ */
++void rtw_cbuf_free(struct rtw_cbuf *cbuf)
++{
++ rtw_mfree((u8*)cbuf, sizeof(*cbuf) + sizeof(void*)*cbuf->size);
++}
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/runwpa linux-xbian-rpi/drivers/net/wireless/rtl8192cu/runwpa
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/runwpa 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/runwpa 2015-07-28 01:20:58.433199136 +0200
+@@ -0,0 +1,18 @@
++#!/bin/bash
++
++if [ "`which iwconfig`" = "" ] ; then
++ echo "WARNING:Wireless tool not exist!"
++ echo " Please install it!"
++ exit
++else
++ if [ `uname -r | cut -d. -f2` -eq 4 ]; then
++ wpa_supplicant -D ipw -c wpa1.conf -i wlan0
++ else
++ if [ `iwconfig -v |awk '{print $4}' | head -n 1` -lt 18 ] ; then
++ wpa_supplicant -D ipw -c wpa1.conf -i wlan0
++ else
++ wpa_supplicant -D wext -c wpa1.conf -i wlan0
++ fi
++
++ fi
++fi
+diff -Nur linux-4.1.3/drivers/net/wireless/rtl8192cu/wlan0dhcp linux-xbian-rpi/drivers/net/wireless/rtl8192cu/wlan0dhcp
+--- linux-4.1.3/drivers/net/wireless/rtl8192cu/wlan0dhcp 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/net/wireless/rtl8192cu/wlan0dhcp 2015-07-28 01:20:58.433199136 +0200
+@@ -0,0 +1,15 @@
++#!/bin/bash
++
++var0=`ps aux|awk '/dhclient wlan0/'|awk '$11!="awk"{print $2}'`
++
++kill $var0
++cp ifcfg-wlan0 /etc/sysconfig/network-scripts/
++
++dhclient wlan0
++
++var1=`ifconfig wlan0 |awk '/inet/{print $2}'|awk -F: '{print $2}'`
++
++
++rm -f /etc/sysconfig/network-scripts/ifcfg-wlan0
++
++echo "get ip: $var1"
+diff -Nur linux-4.1.3/drivers/of/fdt.c linux-xbian-rpi/drivers/of/fdt.c
+--- linux-4.1.3/drivers/of/fdt.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/of/fdt.c 2015-07-28 01:20:58.433199136 +0200
+@@ -933,19 +933,38 @@
+
+ /* Retrieve command line */
+ p = of_get_flat_dt_prop(node, "bootargs", &l);
+- if (p != NULL && l > 0)
+- strlcpy(data, p, min((int)l, COMMAND_LINE_SIZE));
+
+ /*
+ * CONFIG_CMDLINE is meant to be a default in case nothing else
+ * managed to set the command line, unless CONFIG_CMDLINE_FORCE
+ * is set in which case we override whatever was found earlier.
++ *
++ * However, it can be useful to be able to treat the default as
++ * a starting point to be extended using CONFIG_CMDLINE_EXTEND.
+ */
++ ((char *)data)[0] = '\0';
++
+ #ifdef CONFIG_CMDLINE
+-#ifndef CONFIG_CMDLINE_FORCE
+- if (!((char *)data)[0])
++ strlcpy(data, CONFIG_CMDLINE, COMMAND_LINE_SIZE);
++
++ if (p != NULL && l > 0) {
++#if defined(CONFIG_CMDLINE_EXTEND)
++ int len = strlen(data);
++ if (len > 0) {
++ strlcat(data, " ", COMMAND_LINE_SIZE);
++ len++;
++ }
++ strlcpy((char *)data + len, p, min((int)l, COMMAND_LINE_SIZE - len));
++#elif defined(CONFIG_CMDLINE_FORCE)
++ pr_warning("Ignoring bootargs property (using the default kernel command line)\n");
++#else
++ /* Neither extend nor force - just override */
++ strlcpy(data, p, min((int)l, COMMAND_LINE_SIZE));
+ #endif
+- strlcpy(data, CONFIG_CMDLINE, COMMAND_LINE_SIZE);
++ }
++#else /* CONFIG_CMDLINE */
++ if (p != NULL && l > 0) {
++ strlcpy(data, p, min((int)l, COMMAND_LINE_SIZE));
+ #endif /* CONFIG_CMDLINE */
+
+ pr_debug("Command line is: %s\n", (char*)data);
+diff -Nur linux-4.1.3/drivers/pinctrl/bcm/pinctrl-bcm2835.c linux-xbian-rpi/drivers/pinctrl/bcm/pinctrl-bcm2835.c
+--- linux-4.1.3/drivers/pinctrl/bcm/pinctrl-bcm2835.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/pinctrl/bcm/pinctrl-bcm2835.c 2015-07-28 01:20:58.433199136 +0200
+@@ -47,6 +47,7 @@
+ #define MODULE_NAME "pinctrl-bcm2835"
+ #define BCM2835_NUM_GPIOS 54
+ #define BCM2835_NUM_BANKS 2
++#define BCM2835_NUM_IRQS 3
+
+ #define BCM2835_PIN_BITMAP_SZ \
+ DIV_ROUND_UP(BCM2835_NUM_GPIOS, sizeof(unsigned long) * 8)
+@@ -88,13 +89,13 @@
+
+ struct bcm2835_gpio_irqdata {
+ struct bcm2835_pinctrl *pc;
+- int bank;
++ int irqgroup;
+ };
+
+ struct bcm2835_pinctrl {
+ struct device *dev;
+ void __iomem *base;
+- int irq[BCM2835_NUM_BANKS];
++ int irq[BCM2835_NUM_IRQS];
+
+ /* note: locking assumes each bank will have its own unsigned long */
+ unsigned long enabled_irq_map[BCM2835_NUM_BANKS];
+@@ -105,7 +106,7 @@
+ struct gpio_chip gpio_chip;
+ struct pinctrl_gpio_range gpio_range;
+
+- struct bcm2835_gpio_irqdata irq_data[BCM2835_NUM_BANKS];
++ struct bcm2835_gpio_irqdata irq_data[BCM2835_NUM_IRQS];
+ spinlock_t irq_lock[BCM2835_NUM_BANKS];
+ };
+
+@@ -355,7 +356,14 @@
+ static int bcm2835_gpio_direction_output(struct gpio_chip *chip,
+ unsigned offset, int value)
+ {
+- return pinctrl_gpio_direction_output(chip->base + offset);
++ struct bcm2835_pinctrl *pc = dev_get_drvdata(chip->dev);
++ int ret;
++
++ ret = pinctrl_gpio_direction_output(chip->base + offset);
++ if (ret >= 0)
++ bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset);
++
++ return ret;
+ }
+
+ static void bcm2835_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
+@@ -382,22 +390,21 @@
+ .get = bcm2835_gpio_get,
+ .set = bcm2835_gpio_set,
+ .to_irq = bcm2835_gpio_to_irq,
+- .base = -1,
++ .base = 0,
+ .ngpio = BCM2835_NUM_GPIOS,
+ .can_sleep = false,
+ };
+
+-static irqreturn_t bcm2835_gpio_irq_handler(int irq, void *dev_id)
++static int bcm2835_gpio_irq_handle_bank(struct bcm2835_pinctrl *pc,
++ unsigned int bank, u32 mask)
+ {
+- struct bcm2835_gpio_irqdata *irqdata = dev_id;
+- struct bcm2835_pinctrl *pc = irqdata->pc;
+- int bank = irqdata->bank;
+ unsigned long events;
+ unsigned offset;
+ unsigned gpio;
+ unsigned int type;
+
+ events = bcm2835_gpio_rd(pc, GPEDS0 + bank * 4);
++ events &= mask;
+ events &= pc->enabled_irq_map[bank];
+ for_each_set_bit(offset, &events, 32) {
+ gpio = (32 * bank) + offset;
+@@ -405,7 +412,30 @@
+
+ generic_handle_irq(irq_linear_revmap(pc->irq_domain, gpio));
+ }
+- return events ? IRQ_HANDLED : IRQ_NONE;
++
++ return (events != 0);
++}
++
++static irqreturn_t bcm2835_gpio_irq_handler(int irq, void *dev_id)
++{
++ struct bcm2835_gpio_irqdata *irqdata = dev_id;
++ struct bcm2835_pinctrl *pc = irqdata->pc;
++ int handled = 0;
++
++ switch (irqdata->irqgroup) {
++ case 0: /* IRQ0 covers GPIOs 0-27 */
++ handled = bcm2835_gpio_irq_handle_bank(pc, 0, 0x0fffffff);
++ break;
++ case 1: /* IRQ1 covers GPIOs 28-45 */
++ handled = bcm2835_gpio_irq_handle_bank(pc, 0, 0xf0000000) |
++ bcm2835_gpio_irq_handle_bank(pc, 1, 0x00003fff);
++ break;
++ case 2: /* IRQ2 covers GPIOs 46-53 */
++ handled = bcm2835_gpio_irq_handle_bank(pc, 1, 0x003fc000);
++ break;
++ }
++
++ return handled ? IRQ_HANDLED : IRQ_NONE;
+ }
+
+ static inline void __bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
+@@ -993,8 +1023,6 @@
+ for (i = 0; i < BCM2835_NUM_BANKS; i++) {
+ unsigned long events;
+ unsigned offset;
+- int len;
+- char *name;
+
+ /* clear event detection flags */
+ bcm2835_gpio_wr(pc, GPREN0 + i * 4, 0);
+@@ -1009,10 +1037,17 @@
+ for_each_set_bit(offset, &events, 32)
+ bcm2835_gpio_wr(pc, GPEDS0 + i * 4, BIT(offset));
+
++ spin_lock_init(&pc->irq_lock[i]);
++ }
++
++ for (i = 0; i < BCM2835_NUM_IRQS; i++) {
++ int len;
++ char *name;
+ pc->irq[i] = irq_of_parse_and_map(np, i);
++ if (pc->irq[i] == 0)
++ break;
+ pc->irq_data[i].pc = pc;
+- pc->irq_data[i].bank = i;
+- spin_lock_init(&pc->irq_lock[i]);
++ pc->irq_data[i].irqgroup = i;
+
+ len = strlen(dev_name(pc->dev)) + 16;
+ name = devm_kzalloc(pc->dev, len, GFP_KERNEL);
+@@ -1070,6 +1105,7 @@
+ .remove = bcm2835_pinctrl_remove,
+ .driver = {
+ .name = MODULE_NAME,
++ .owner = THIS_MODULE,
+ .of_match_table = bcm2835_pinctrl_match,
+ },
+ };
+diff -Nur linux-4.1.3/drivers/pinctrl/Makefile linux-xbian-rpi/drivers/pinctrl/Makefile
+--- linux-4.1.3/drivers/pinctrl/Makefile 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/pinctrl/Makefile 2015-07-28 01:20:58.433199136 +0200
+@@ -38,6 +38,7 @@
+ obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o
+ obj-$(CONFIG_PINCTRL_ZYNQ) += pinctrl-zynq.o
+
++obj-$(CONFIG_ARCH_BCM2708)$(CONFIG_ARCH_BCM2709) += bcm/
+ obj-$(CONFIG_ARCH_BCM) += bcm/
+ obj-$(CONFIG_ARCH_BERLIN) += berlin/
+ obj-y += freescale/
+diff -Nur linux-4.1.3/drivers/power/reset/gpio-poweroff.c linux-xbian-rpi/drivers/power/reset/gpio-poweroff.c
+--- linux-4.1.3/drivers/power/reset/gpio-poweroff.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/power/reset/gpio-poweroff.c 2015-07-28 01:20:58.433199136 +0200
+@@ -48,9 +48,11 @@
+ static int gpio_poweroff_probe(struct platform_device *pdev)
+ {
+ bool input = false;
++ bool force = false;
+
+ /* If a pm_power_off function has already been added, leave it alone */
+- if (pm_power_off != NULL) {
++ force = of_property_read_bool(pdev->dev.of_node, "force");
++ if (!force && (pm_power_off != NULL)) {
+ dev_err(&pdev->dev,
+ "%s: pm_power_off function already registered",
+ __func__);
+diff -Nur linux-4.1.3/drivers/rtc/rtc-ds1307.c linux-xbian-rpi/drivers/rtc/rtc-ds1307.c
+--- linux-4.1.3/drivers/rtc/rtc-ds1307.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/rtc/rtc-ds1307.c 2015-07-28 01:20:58.433199136 +0200
+@@ -1242,6 +1242,14 @@
+ return 0;
+ }
+
++#ifdef CONFIG_OF
++static const struct of_device_id ds1307_of_match[] = {
++ { .compatible = "maxim,ds1307" },
++ { }
++};
++MODULE_DEVICE_TABLE(of, ds1307_of_match);
++#endif
++
+ static struct i2c_driver ds1307_driver = {
+ .driver = {
+ .name = "rtc-ds1307",
+diff -Nur linux-4.1.3/drivers/spi/Kconfig linux-xbian-rpi/drivers/spi/Kconfig
+--- linux-4.1.3/drivers/spi/Kconfig 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/spi/Kconfig 2015-07-28 01:20:58.433199136 +0200
+@@ -77,7 +77,7 @@
+
+ config SPI_BCM2835
+ tristate "BCM2835 SPI controller"
+- depends on ARCH_BCM2835 || COMPILE_TEST
++ depends on ARCH_BCM2835 || ARCH_BCM2708 || ARCH_BCM2709 || COMPILE_TEST
+ depends on GPIOLIB
+ help
+ This selects a driver for the Broadcom BCM2835 SPI master.
+@@ -87,6 +87,14 @@
+ is for the regular SPI controller. Slave mode operation is not also
+ not supported.
+
++config SPI_BCM2708
++ tristate "BCM2708 SPI controller driver (SPI0)"
++ depends on MACH_BCM2708 || MACH_BCM2709
++ help
++ This selects a driver for the Broadcom BCM2708 SPI master (SPI0). This
++ driver is not compatible with the "Universal SPI Master" or the SPI slave
++ device.
++
+ config SPI_BFIN5XX
+ tristate "SPI controller driver for ADI Blackfin5xx"
+ depends on BLACKFIN && !BF60x
+diff -Nur linux-4.1.3/drivers/spi/Makefile linux-xbian-rpi/drivers/spi/Makefile
+--- linux-4.1.3/drivers/spi/Makefile 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/spi/Makefile 2015-07-28 01:20:58.433199136 +0200
+@@ -20,6 +20,7 @@
+ obj-$(CONFIG_SPI_BCM63XX_HSSPI) += spi-bcm63xx-hsspi.o
+ obj-$(CONFIG_SPI_BFIN5XX) += spi-bfin5xx.o
+ obj-$(CONFIG_SPI_ADI_V3) += spi-adi-v3.o
++obj-$(CONFIG_SPI_BCM2708) += spi-bcm2708.o
+ obj-$(CONFIG_SPI_BFIN_SPORT) += spi-bfin-sport.o
+ obj-$(CONFIG_SPI_BITBANG) += spi-bitbang.o
+ obj-$(CONFIG_SPI_BUTTERFLY) += spi-butterfly.o
+diff -Nur linux-4.1.3/drivers/spi/spi-bcm2708.c linux-xbian-rpi/drivers/spi/spi-bcm2708.c
+--- linux-4.1.3/drivers/spi/spi-bcm2708.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/spi/spi-bcm2708.c 2015-07-28 01:20:58.433199136 +0200
+@@ -0,0 +1,628 @@
++/*
++ * Driver for Broadcom BCM2708 SPI Controllers
++ *
++ * Copyright (C) 2012 Chris Boot
++ *
++ * This driver is inspired by:
++ * spi-ath79.c, Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
++ * spi-atmel.c, Copyright (C) 2006 Atmel Corporation
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/spinlock.h>
++#include <linux/clk.h>
++#include <linux/err.h>
++#include <linux/platform_device.h>
++#include <linux/io.h>
++#include <linux/spi/spi.h>
++#include <linux/interrupt.h>
++#include <linux/delay.h>
++#include <linux/log2.h>
++#include <linux/sched.h>
++#include <linux/wait.h>
++
++/* SPI register offsets */
++#define SPI_CS 0x00
++#define SPI_FIFO 0x04
++#define SPI_CLK 0x08
++#define SPI_DLEN 0x0c
++#define SPI_LTOH 0x10
++#define SPI_DC 0x14
++
++/* Bitfields in CS */
++#define SPI_CS_LEN_LONG 0x02000000
++#define SPI_CS_DMA_LEN 0x01000000
++#define SPI_CS_CSPOL2 0x00800000
++#define SPI_CS_CSPOL1 0x00400000
++#define SPI_CS_CSPOL0 0x00200000
++#define SPI_CS_RXF 0x00100000
++#define SPI_CS_RXR 0x00080000
++#define SPI_CS_TXD 0x00040000
++#define SPI_CS_RXD 0x00020000
++#define SPI_CS_DONE 0x00010000
++#define SPI_CS_LEN 0x00002000
++#define SPI_CS_REN 0x00001000
++#define SPI_CS_ADCS 0x00000800
++#define SPI_CS_INTR 0x00000400
++#define SPI_CS_INTD 0x00000200
++#define SPI_CS_DMAEN 0x00000100
++#define SPI_CS_TA 0x00000080
++#define SPI_CS_CSPOL 0x00000040
++#define SPI_CS_CLEAR_RX 0x00000020
++#define SPI_CS_CLEAR_TX 0x00000010
++#define SPI_CS_CPOL 0x00000008
++#define SPI_CS_CPHA 0x00000004
++#define SPI_CS_CS_10 0x00000002
++#define SPI_CS_CS_01 0x00000001
++
++#define SPI_TIMEOUT_MS 1000
++
++#define DRV_NAME "bcm2708_spi"
++
++struct bcm2708_spi {
++ spinlock_t lock;
++ void __iomem *base;
++ int irq;
++ struct clk *clk;
++ bool stopping;
++
++ struct list_head queue;
++ struct workqueue_struct *workq;
++ struct work_struct work;
++ struct completion done;
++
++ const u8 *tx_buf;
++ u8 *rx_buf;
++ int len;
++};
++
++struct bcm2708_spi_state {
++ u32 cs;
++ u16 cdiv;
++};
++
++/*
++ * This function sets the ALT mode on the SPI pins so that we can use them with
++ * the SPI hardware.
++ *
++ * FIXME: This is a hack. Use pinmux / pinctrl.
++ */
++static void bcm2708_init_pinmode(void)
++{
++#define INP_GPIO(g) *(gpio+((g)/10)) &= ~(7<<(((g)%10)*3))
++#define SET_GPIO_ALT(g,a) *(gpio+(((g)/10))) |= (((a)<=3?(a)+4:(a)==4?3:2)<<(((g)%10)*3))
++
++ int pin;
++ u32 *gpio = ioremap(GPIO_BASE, SZ_16K);
++
++ /* SPI is on GPIO 7..11 */
++ for (pin = 7; pin <= 11; pin++) {
++ INP_GPIO(pin); /* set mode to GPIO input first */
++ SET_GPIO_ALT(pin, 0); /* set mode to ALT 0 */
++ }
++
++ iounmap(gpio);
++
++#undef INP_GPIO
++#undef SET_GPIO_ALT
++}
++
++static inline u32 bcm2708_rd(struct bcm2708_spi *bs, unsigned reg)
++{
++ return readl(bs->base + reg);
++}
++
++static inline void bcm2708_wr(struct bcm2708_spi *bs, unsigned reg, u32 val)
++{
++ writel(val, bs->base + reg);
++}
++
++static inline void bcm2708_rd_fifo(struct bcm2708_spi *bs, int len)
++{
++ u8 byte;
++
++ while (len--) {
++ byte = bcm2708_rd(bs, SPI_FIFO);
++ if (bs->rx_buf)
++ *bs->rx_buf++ = byte;
++ }
++}
++
++static inline void bcm2708_wr_fifo(struct bcm2708_spi *bs, int len)
++{
++ u8 byte;
++ u16 val;
++
++ if (len > bs->len)
++ len = bs->len;
++
++ if (unlikely(bcm2708_rd(bs, SPI_CS) & SPI_CS_LEN)) {
++ /* LoSSI mode */
++ if (unlikely(len % 2)) {
++ printk(KERN_ERR"bcm2708_wr_fifo: length must be even, skipping.\n");
++ bs->len = 0;
++ return;
++ }
++ while (len) {
++ if (bs->tx_buf) {
++ val = *(const u16 *)bs->tx_buf;
++ bs->tx_buf += 2;
++ } else
++ val = 0;
++ bcm2708_wr(bs, SPI_FIFO, val);
++ bs->len -= 2;
++ len -= 2;
++ }
++ return;
++ }
++
++ while (len--) {
++ byte = bs->tx_buf ? *bs->tx_buf++ : 0;
++ bcm2708_wr(bs, SPI_FIFO, byte);
++ bs->len--;
++ }
++}
++
++static irqreturn_t bcm2708_spi_interrupt(int irq, void *dev_id)
++{
++ struct spi_master *master = dev_id;
++ struct bcm2708_spi *bs = spi_master_get_devdata(master);
++ u32 cs;
++
++ spin_lock(&bs->lock);
++
++ cs = bcm2708_rd(bs, SPI_CS);
++
++ if (cs & SPI_CS_DONE) {
++ if (bs->len) { /* first interrupt in a transfer */
++ /* fill the TX fifo with up to 16 bytes */
++ bcm2708_wr_fifo(bs, 16);
++ } else { /* transfer complete */
++ /* disable interrupts */
++ cs &= ~(SPI_CS_INTR | SPI_CS_INTD);
++ bcm2708_wr(bs, SPI_CS, cs);
++
++ /* drain RX FIFO */
++ while (cs & SPI_CS_RXD) {
++ bcm2708_rd_fifo(bs, 1);
++ cs = bcm2708_rd(bs, SPI_CS);
++ }
++
++ /* wake up our bh */
++ complete(&bs->done);
++ }
++ } else if (cs & SPI_CS_RXR) {
++ /* read 12 bytes of data */
++ bcm2708_rd_fifo(bs, 12);
++
++ /* write up to 12 bytes */
++ bcm2708_wr_fifo(bs, 12);
++ }
++
++ spin_unlock(&bs->lock);
++
++ return IRQ_HANDLED;
++}
++
++static int bcm2708_setup_state(struct spi_master *master,
++ struct device *dev, struct bcm2708_spi_state *state,
++ u32 hz, u8 csel, u8 mode, u8 bpw)
++{
++ struct bcm2708_spi *bs = spi_master_get_devdata(master);
++ int cdiv;
++ unsigned long bus_hz;
++ u32 cs = 0;
++
++ bus_hz = clk_get_rate(bs->clk);
++
++ if (hz >= bus_hz) {
++ cdiv = 2; /* bus_hz / 2 is as fast as we can go */
++ } else if (hz) {
++ cdiv = DIV_ROUND_UP(bus_hz, hz);
++
++ /* CDIV must be a power of 2, so round up */
++ cdiv = roundup_pow_of_two(cdiv);
++
++ if (cdiv > 65536) {
++ dev_dbg(dev,
++ "setup: %d Hz too slow, cdiv %u; min %ld Hz\n",
++ hz, cdiv, bus_hz / 65536);
++ return -EINVAL;
++ } else if (cdiv == 65536) {
++ cdiv = 0;
++ } else if (cdiv == 1) {
++ cdiv = 2; /* 1 gets rounded down to 0; == 65536 */
++ }
++ } else {
++ cdiv = 0;
++ }
++
++ switch (bpw) {
++ case 8:
++ break;
++ case 9:
++ /* Reading in LoSSI mode is a special case. See 'BCM2835 ARM Peripherals' datasheet */
++ cs |= SPI_CS_LEN;
++ break;
++ default:
++ dev_dbg(dev, "setup: invalid bits_per_word %u (must be 8 or 9)\n",
++ bpw);
++ return -EINVAL;
++ }
++
++ if (mode & SPI_CPOL)
++ cs |= SPI_CS_CPOL;
++ if (mode & SPI_CPHA)
++ cs |= SPI_CS_CPHA;
++
++ if (!(mode & SPI_NO_CS)) {
++ if (mode & SPI_CS_HIGH) {
++ cs |= SPI_CS_CSPOL;
++ cs |= SPI_CS_CSPOL0 << csel;
++ }
++
++ cs |= csel;
++ } else {
++ cs |= SPI_CS_CS_10 | SPI_CS_CS_01;
++ }
++
++ if (state) {
++ state->cs = cs;
++ state->cdiv = cdiv;
++ dev_dbg(dev, "setup: want %d Hz; "
++ "bus_hz=%lu / cdiv=%u == %lu Hz; "
++ "mode %u: cs 0x%08X\n",
++ hz, bus_hz, cdiv, bus_hz/cdiv, mode, cs);
++ }
++
++ return 0;
++}
++
++static int bcm2708_process_transfer(struct bcm2708_spi *bs,
++ struct spi_message *msg, struct spi_transfer *xfer)
++{
++ struct spi_device *spi = msg->spi;
++ struct bcm2708_spi_state state, *stp;
++ int ret;
++ u32 cs;
++
++ if (bs->stopping)
++ return -ESHUTDOWN;
++
++ if (xfer->bits_per_word || xfer->speed_hz) {
++ ret = bcm2708_setup_state(spi->master, &spi->dev, &state,
++ xfer->speed_hz ? xfer->speed_hz : spi->max_speed_hz,
++ spi->chip_select, spi->mode,
++ xfer->bits_per_word ? xfer->bits_per_word :
++ spi->bits_per_word);
++ if (ret)
++ return ret;
++
++ stp = &state;
++ } else {
++ stp = spi->controller_state;
++ }
++
++ reinit_completion(&bs->done);
++ bs->tx_buf = xfer->tx_buf;
++ bs->rx_buf = xfer->rx_buf;
++ bs->len = xfer->len;
++
++ cs = stp->cs | SPI_CS_INTR | SPI_CS_INTD | SPI_CS_TA;
++
++ bcm2708_wr(bs, SPI_CLK, stp->cdiv);
++ bcm2708_wr(bs, SPI_CS, cs);
++
++ ret = wait_for_completion_timeout(&bs->done,
++ msecs_to_jiffies(SPI_TIMEOUT_MS));
++ if (ret == 0) {
++ dev_err(&spi->dev, "transfer timed out\n");
++ return -ETIMEDOUT;
++ }
++
++ if (xfer->delay_usecs)
++ udelay(xfer->delay_usecs);
++
++ if (list_is_last(&xfer->transfer_list, &msg->transfers) ||
++ xfer->cs_change) {
++ /* clear TA and interrupt flags */
++ bcm2708_wr(bs, SPI_CS, stp->cs);
++ }
++
++ msg->actual_length += (xfer->len - bs->len);
++
++ return 0;
++}
++
++static void bcm2708_work(struct work_struct *work)
++{
++ struct bcm2708_spi *bs = container_of(work, struct bcm2708_spi, work);
++ unsigned long flags;
++ struct spi_message *msg;
++ struct spi_transfer *xfer;
++ int status = 0;
++
++ spin_lock_irqsave(&bs->lock, flags);
++ while (!list_empty(&bs->queue)) {
++ msg = list_first_entry(&bs->queue, struct spi_message, queue);
++ list_del_init(&msg->queue);
++ spin_unlock_irqrestore(&bs->lock, flags);
++
++ list_for_each_entry(xfer, &msg->transfers, transfer_list) {
++ status = bcm2708_process_transfer(bs, msg, xfer);
++ if (status)
++ break;
++ }
++
++ msg->status = status;
++ msg->complete(msg->context);
++
++ spin_lock_irqsave(&bs->lock, flags);
++ }
++ spin_unlock_irqrestore(&bs->lock, flags);
++}
++
++static int bcm2708_spi_setup(struct spi_device *spi)
++{
++ struct bcm2708_spi *bs = spi_master_get_devdata(spi->master);
++ struct bcm2708_spi_state *state;
++ int ret;
++
++ if (bs->stopping)
++ return -ESHUTDOWN;
++
++ state = spi->controller_state;
++ if (!state) {
++ state = kzalloc(sizeof(*state), GFP_KERNEL);
++ if (!state)
++ return -ENOMEM;
++
++ spi->controller_state = state;
++ }
++
++ ret = bcm2708_setup_state(spi->master, &spi->dev, state,
++ spi->max_speed_hz, spi->chip_select, spi->mode,
++ spi->bits_per_word);
++ if (ret < 0) {
++ kfree(state);
++ spi->controller_state = NULL;
++ return ret;
++ }
++
++ dev_dbg(&spi->dev,
++ "setup: cd %d: %d Hz, bpw %u, mode 0x%x -> CS=%08x CDIV=%04x\n",
++ spi->chip_select, spi->max_speed_hz, spi->bits_per_word,
++ spi->mode, state->cs, state->cdiv);
++
++ return 0;
++}
++
++static int bcm2708_spi_transfer(struct spi_device *spi, struct spi_message *msg)
++{
++ struct bcm2708_spi *bs = spi_master_get_devdata(spi->master);
++ struct spi_transfer *xfer;
++ int ret;
++ unsigned long flags;
++
++ if (unlikely(list_empty(&msg->transfers)))
++ return -EINVAL;
++
++ if (bs->stopping)
++ return -ESHUTDOWN;
++
++ list_for_each_entry(xfer, &msg->transfers, transfer_list) {
++ if (!(xfer->tx_buf || xfer->rx_buf) && xfer->len) {
++ dev_dbg(&spi->dev, "missing rx or tx buf\n");
++ return -EINVAL;
++ }
++
++ if (!xfer->bits_per_word || xfer->speed_hz)
++ continue;
++
++ ret = bcm2708_setup_state(spi->master, &spi->dev, NULL,
++ xfer->speed_hz ? xfer->speed_hz : spi->max_speed_hz,
++ spi->chip_select, spi->mode,
++ xfer->bits_per_word ? xfer->bits_per_word :
++ spi->bits_per_word);
++ if (ret)
++ return ret;
++ }
++
++ msg->status = -EINPROGRESS;
++ msg->actual_length = 0;
++
++ spin_lock_irqsave(&bs->lock, flags);
++ list_add_tail(&msg->queue, &bs->queue);
++ queue_work(bs->workq, &bs->work);
++ spin_unlock_irqrestore(&bs->lock, flags);
++
++ return 0;
++}
++
++static void bcm2708_spi_cleanup(struct spi_device *spi)
++{
++ if (spi->controller_state) {
++ kfree(spi->controller_state);
++ spi->controller_state = NULL;
++ }
++}
++
++static int bcm2708_spi_probe(struct platform_device *pdev)
++{
++ struct resource *regs;
++ int irq, err = -ENOMEM;
++ struct clk *clk;
++ struct spi_master *master;
++ struct bcm2708_spi *bs;
++
++ regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (!regs) {
++ dev_err(&pdev->dev, "could not get IO memory\n");
++ return -ENXIO;
++ }
++
++ irq = platform_get_irq(pdev, 0);
++ if (irq < 0) {
++ dev_err(&pdev->dev, "could not get IRQ\n");
++ return irq;
++ }
++
++ clk = clk_get(&pdev->dev, NULL);
++ if (IS_ERR(clk)) {
++ dev_err(&pdev->dev, "could not find clk: %ld\n", PTR_ERR(clk));
++ return PTR_ERR(clk);
++ }
++
++ if (!pdev->dev.of_node)
++ bcm2708_init_pinmode();
++
++ master = spi_alloc_master(&pdev->dev, sizeof(*bs));
++ if (!master) {
++ dev_err(&pdev->dev, "spi_alloc_master() failed\n");
++ goto out_clk_put;
++ }
++
++ /* the spi->mode bits understood by this driver: */
++ master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_NO_CS;
++
++ master->bus_num = pdev->id;
++ master->num_chipselect = 3;
++ master->setup = bcm2708_spi_setup;
++ master->transfer = bcm2708_spi_transfer;
++ master->cleanup = bcm2708_spi_cleanup;
++ master->dev.of_node = pdev->dev.of_node;
++ platform_set_drvdata(pdev, master);
++
++ bs = spi_master_get_devdata(master);
++
++ spin_lock_init(&bs->lock);
++ INIT_LIST_HEAD(&bs->queue);
++ init_completion(&bs->done);
++ INIT_WORK(&bs->work, bcm2708_work);
++
++ bs->base = ioremap(regs->start, resource_size(regs));
++ if (!bs->base) {
++ dev_err(&pdev->dev, "could not remap memory\n");
++ goto out_master_put;
++ }
++
++ bs->workq = create_singlethread_workqueue(dev_name(&pdev->dev));
++ if (!bs->workq) {
++ dev_err(&pdev->dev, "could not create workqueue\n");
++ goto out_iounmap;
++ }
++
++ bs->irq = irq;
++ bs->clk = clk;
++ bs->stopping = false;
++
++ err = request_irq(irq, bcm2708_spi_interrupt, 0, dev_name(&pdev->dev),
++ master);
++ if (err) {
++ dev_err(&pdev->dev, "could not request IRQ: %d\n", err);
++ goto out_workqueue;
++ }
++
++ /* initialise the hardware */
++ clk_prepare_enable(clk);
++ bcm2708_wr(bs, SPI_CS, SPI_CS_REN | SPI_CS_CLEAR_RX | SPI_CS_CLEAR_TX);
++
++ err = spi_register_master(master);
++ if (err) {
++ dev_err(&pdev->dev, "could not register SPI master: %d\n", err);
++ goto out_free_irq;
++ }
++
++ dev_info(&pdev->dev, "SPI Controller at 0x%08lx (irq %d)\n",
++ (unsigned long)regs->start, irq);
++
++ return 0;
++
++out_free_irq:
++ free_irq(bs->irq, master);
++ clk_disable_unprepare(bs->clk);
++out_workqueue:
++ destroy_workqueue(bs->workq);
++out_iounmap:
++ iounmap(bs->base);
++out_master_put:
++ spi_master_put(master);
++out_clk_put:
++ clk_put(clk);
++ return err;
++}
++
++static int bcm2708_spi_remove(struct platform_device *pdev)
++{
++ struct spi_master *master = platform_get_drvdata(pdev);
++ struct bcm2708_spi *bs = spi_master_get_devdata(master);
++
++ /* reset the hardware and block queue progress */
++ spin_lock_irq(&bs->lock);
++ bs->stopping = true;
++ bcm2708_wr(bs, SPI_CS, SPI_CS_CLEAR_RX | SPI_CS_CLEAR_TX);
++ spin_unlock_irq(&bs->lock);
++
++ flush_work(&bs->work);
++
++ clk_disable_unprepare(bs->clk);
++ clk_put(bs->clk);
++ free_irq(bs->irq, master);
++ iounmap(bs->base);
++
++ spi_unregister_master(master);
++
++ return 0;
++}
++
++static const struct of_device_id bcm2708_spi_match[] = {
++ { .compatible = "brcm,bcm2708-spi", },
++ {}
++};
++MODULE_DEVICE_TABLE(of, bcm2708_spi_match);
++
++static struct platform_driver bcm2708_spi_driver = {
++ .driver = {
++ .name = DRV_NAME,
++ .owner = THIS_MODULE,
++ .of_match_table = bcm2708_spi_match,
++ },
++ .probe = bcm2708_spi_probe,
++ .remove = bcm2708_spi_remove,
++};
++
++
++static int __init bcm2708_spi_init(void)
++{
++ return platform_driver_probe(&bcm2708_spi_driver, bcm2708_spi_probe);
++}
++module_init(bcm2708_spi_init);
++
++static void __exit bcm2708_spi_exit(void)
++{
++ platform_driver_unregister(&bcm2708_spi_driver);
++}
++module_exit(bcm2708_spi_exit);
++
++
++//module_platform_driver(bcm2708_spi_driver);
++
++MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2708");
++MODULE_AUTHOR("Chris Boot <bootc@bootc.net>");
++MODULE_LICENSE("GPL v2");
++MODULE_ALIAS("platform:" DRV_NAME);
+diff -Nur linux-4.1.3/drivers/spi/spi-bcm2835.c linux-xbian-rpi/drivers/spi/spi-bcm2835.c
+--- linux-4.1.3/drivers/spi/spi-bcm2835.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/spi/spi-bcm2835.c 2015-07-28 01:20:58.433199136 +0200
+@@ -359,6 +359,8 @@
+ {
+ int err;
+ struct gpio_chip *chip;
++ struct device_node *pins;
++ u32 pingroup_index;
+ /*
+ * sanity checking the native-chipselects
+ */
+@@ -375,15 +377,42 @@
+ "setup: only two native chip-selects are supported\n");
+ return -EINVAL;
+ }
+- /* now translate native cs to GPIO */
+
+- /* get the gpio chip for the base */
+- chip = gpiochip_find("pinctrl-bcm2835", chip_match_name);
+- if (!chip)
+- return 0;
++ /* now translate native cs to GPIO */
++ /* first look for chip select pins in the devices pin groups */
++ for (pingroup_index = 0;
++ (pins = of_parse_phandle(spi->master->dev.of_node,
++ "pinctrl-0",
++ pingroup_index)) != 0;
++ pingroup_index++) {
++ u32 pin;
++ u32 pin_index;
++ for (pin_index = 0;
++ of_property_read_u32_index(pins,
++ "brcm,pins",
++ pin_index,
++ &pin) == 0;
++ pin_index++) {
++ if (((spi->chip_select == 0) &&
++ ((pin == 8) || (pin == 36) || (pin == 46))) ||
++ ((spi->chip_select == 1) &&
++ ((pin == 7) || (pin == 35)))) {
++ spi->cs_gpio = pin;
++ break;
++ }
++ }
++ of_node_put(pins);
++ }
++ /* if that fails, assume GPIOs 7-11 are used */
++ if (!gpio_is_valid(spi->cs_gpio) ) {
++ /* get the gpio chip for the base */
++ chip = gpiochip_find("pinctrl-bcm2835", chip_match_name);
++ if (!chip)
++ return 0;
+
+- /* and calculate the real CS */
+- spi->cs_gpio = chip->base + 8 - spi->chip_select;
++ /* and calculate the real CS */
++ spi->cs_gpio = chip->base + 8 - spi->chip_select;
++ }
+
+ /* and set up the "mode" and level */
+ dev_info(&spi->dev, "setting up native-CS%i as GPIO %i\n",
+diff -Nur linux-4.1.3/drivers/spi/spidev.c linux-xbian-rpi/drivers/spi/spidev.c
+--- linux-4.1.3/drivers/spi/spidev.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/spi/spidev.c 2015-07-28 01:20:58.437184915 +0200
+@@ -706,6 +706,7 @@
+ #ifdef CONFIG_OF
+ static const struct of_device_id spidev_dt_ids[] = {
+ { .compatible = "rohm,dh2228fv" },
++ { .compatible = "spidev" },
+ {},
+ };
+ MODULE_DEVICE_TABLE(of, spidev_dt_ids);
+diff -Nur linux-4.1.3/drivers/staging/media/lirc/kcompat.h linux-xbian-rpi/drivers/staging/media/lirc/kcompat.h
+--- linux-4.1.3/drivers/staging/media/lirc/kcompat.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/staging/media/lirc/kcompat.h 2015-07-28 01:20:58.437184915 +0200
+@@ -0,0 +1,139 @@
++/*
++ * Support header for building lirc drivers on kernels older than the
++ * latest upstream kernel. As of this update, 2.6.18 is the oldest
++ * kernel officially supported any longer. For older kernels, just
++ * rewind the scm history a ways. We can't hope to significantly improve
++ * things if we have to support crusty old kernels only a tiny minority
++ * of people still run, some of these source files are/were really nasty
++ * and hard to follow due to the proliferation of #if LINUX_VERSION_CODE
++ * bits...
++ */
++
++#ifndef _KCOMPAT_H
++#define _KCOMPAT_H
++
++#include <linux/version.h>
++
++#ifndef __func__
++#define __func__ __FUNCTION__
++#endif
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 34)
++#define usb_alloc_coherent usb_buffer_alloc
++#define usb_free_coherent usb_buffer_free
++#endif
++
++#define LIRC_THIS_MODULE(x)
++
++#include <linux/device.h>
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 26)
++
++#define lirc_device_create(cs, parent, dev, drvdata, fmt, args...) \
++ class_device_create(cs, NULL, dev, parent, fmt, ## args)
++
++#else /* >= 2.6.26 */
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 27)
++
++#define lirc_device_create(cs, parent, dev, drvdata, fmt, args...) \
++ device_create(cs, parent, dev, fmt, ## args)
++
++#else /* >= 2.6.27 */
++
++#define lirc_device_create device_create
++
++#endif /* >= 2.6.27 */
++
++#endif /* >= 2.6.26 */
++
++#define LIRC_DEVFS_PREFIX
++
++typedef struct class lirc_class_t;
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 26)
++
++#define lirc_device_destroy class_device_destroy
++
++#else
++
++#define lirc_device_destroy device_destroy
++
++#endif
++
++#ifndef LIRC_DEVFS_PREFIX
++#define LIRC_DEVFS_PREFIX "usb/"
++#endif
++
++#include <linux/moduleparam.h>
++
++#include <linux/interrupt.h>
++#ifndef IRQ_RETVAL
++typedef void irqreturn_t;
++#define IRQ_NONE
++#define IRQ_HANDLED
++#define IRQ_RETVAL(x)
++#endif
++
++#ifndef MOD_IN_USE
++#ifdef CONFIG_MODULE_UNLOAD
++#define MOD_IN_USE module_refcount(THIS_MODULE)
++#else
++#error "LIRC modules currently require"
++#error " 'Loadable module support ---> Module unloading'"
++#error "to be enabled in the kernel"
++#endif
++#endif
++
++/*************************** I2C specific *****************************/
++#include <linux/i2c.h>
++
++/* removed in 2.6.14 */
++#ifndef I2C_ALGO_BIT
++# define I2C_ALGO_BIT 0
++#endif
++
++/* removed in 2.6.16 */
++#ifndef I2C_DRIVERID_EXP3
++# define I2C_DRIVERID_EXP3 0xf003
++#endif
++
++/*************************** USB specific *****************************/
++#include <linux/usb.h>
++
++/* removed in 2.6.14 */
++#ifndef URB_ASYNC_UNLINK
++#define URB_ASYNC_UNLINK 0
++#endif
++
++/*************************** pm_wakeup.h ******************************/
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 27)
++static inline void device_set_wakeup_capable(struct device *dev, int val) {}
++#endif /* kernel < 2.6.27 */
++
++/*************************** interrupt.h ******************************/
++/* added in 2.6.18, old defines removed in 2.6.24 */
++#ifndef IRQF_DISABLED
++#define IRQF_DISABLED SA_INTERRUPT
++#endif
++#ifndef IRQF_SHARED
++#define IRQF_SHARED SA_SHIRQ
++#endif
++
++/****************************** bitops.h **********************************/
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24)
++#define BIT_MASK(nr) (1UL << ((nr) % BITS_PER_LONG))
++#define BIT_WORD(nr) ((nr) / BITS_PER_LONG)
++#endif
++
++/****************************** kernel.h **********************************/
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 29)
++#define DIV_ROUND_CLOSEST(x, divisor)( \
++{ \
++ typeof(divisor) __divisor = divisor; \
++ (((x) + ((__divisor) / 2)) / (__divisor)); \
++} \
++)
++#endif
++
++#endif /* _KCOMPAT_H */
+diff -Nur linux-4.1.3/drivers/staging/media/lirc/Kconfig linux-xbian-rpi/drivers/staging/media/lirc/Kconfig
+--- linux-4.1.3/drivers/staging/media/lirc/Kconfig 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/staging/media/lirc/Kconfig 2015-07-28 01:20:58.437184915 +0200
+@@ -32,6 +32,18 @@
+ help
+ Driver for Homebrew Parallel Port Receivers
+
++config LIRC_RPI
++ tristate "Homebrew GPIO Port Receiver/Transmitter for the RaspberryPi"
++ depends on LIRC
++ help
++ Driver for Homebrew GPIO Port Receiver/Transmitter for the RaspberryPi
++
++config LIRC_XBOX
++ tristate "Homebrew XBOX Receiver for the RaspberryPi"
++ depends on LIRC
++ help
++ Homebrew XBOX Receiver for the RaspberryPi
++
+ config LIRC_SASEM
+ tristate "Sasem USB IR Remote"
+ depends on LIRC && USB
+diff -Nur linux-4.1.3/drivers/staging/media/lirc/lirc_rpi.c linux-xbian-rpi/drivers/staging/media/lirc/lirc_rpi.c
+--- linux-4.1.3/drivers/staging/media/lirc/lirc_rpi.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/staging/media/lirc/lirc_rpi.c 2015-07-28 01:20:58.437184915 +0200
+@@ -0,0 +1,765 @@
++/*
++ * lirc_rpi.c
++ *
++ * lirc_rpi - Device driver that records pulse- and pause-lengths
++ * (space-lengths) (just like the lirc_serial driver does)
++ * between GPIO interrupt events on the Raspberry Pi.
++ * Lots of code has been taken from the lirc_serial module,
++ * so I would like say thanks to the authors.
++ *
++ * Copyright (C) 2012 Aron Robert Szabo <aron@reon.hu>,
++ * Michael Bishop <cleverca22@gmail.com>
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++
++#include <linux/module.h>
++#include <linux/errno.h>
++#include <linux/interrupt.h>
++#include <linux/sched.h>
++#include <linux/kernel.h>
++#include <linux/time.h>
++#include <linux/timex.h>
++#include <linux/timekeeping.h>
++#include <linux/string.h>
++#include <linux/delay.h>
++#include <linux/platform_device.h>
++#include <linux/irq.h>
++#include <linux/spinlock.h>
++#include <media/lirc.h>
++#include <media/lirc_dev.h>
++#include <mach/gpio.h>
++#include <linux/gpio.h>
++#include <linux/of_platform.h>
++
++#include <linux/platform_data/bcm2708.h>
++
++#define LIRC_DRIVER_NAME "lirc_rpi"
++#define RBUF_LEN 256
++#define LIRC_TRANSMITTER_LATENCY 50
++
++#ifndef MAX_UDELAY_MS
++#define MAX_UDELAY_US 5000
++#else
++#define MAX_UDELAY_US (MAX_UDELAY_MS*1000)
++#endif
++
++#define dprintk(fmt, args...) \
++ do { \
++ if (debug) \
++ printk(KERN_DEBUG LIRC_DRIVER_NAME ": " \
++ fmt, ## args); \
++ } while (0)
++
++/* module parameters */
++
++/* set the default GPIO input pin */
++static int gpio_in_pin = 18;
++/* set the default pull behaviour for input pin */
++static int gpio_in_pull = BCM2708_PULL_DOWN;
++/* set the default GPIO output pin */
++static int gpio_out_pin = 17;
++/* enable debugging messages */
++static bool debug;
++/* -1 = auto, 0 = active high, 1 = active low */
++static int sense = -1;
++/* use softcarrier by default */
++static bool softcarrier = 1;
++/* 0 = do not invert output, 1 = invert output */
++static bool invert = 0;
++
++struct gpio_chip *gpiochip;
++static int irq_num;
++
++/* forward declarations */
++static long send_pulse(unsigned long length);
++static void send_space(long length);
++static void lirc_rpi_exit(void);
++
++static struct platform_device *lirc_rpi_dev;
++static struct timeval lasttv = { 0, 0 };
++static struct lirc_buffer rbuf;
++static spinlock_t lock;
++
++/* initialized/set in init_timing_params() */
++static unsigned int freq = 38000;
++static unsigned int duty_cycle = 50;
++static unsigned long period;
++static unsigned long pulse_width;
++static unsigned long space_width;
++
++static void safe_udelay(unsigned long usecs)
++{
++ while (usecs > MAX_UDELAY_US) {
++ udelay(MAX_UDELAY_US);
++ usecs -= MAX_UDELAY_US;
++ }
++ udelay(usecs);
++}
++
++static unsigned long read_current_us(void)
++{
++ struct timespec now;
++ getnstimeofday(&now);
++ return (now.tv_sec * 1000000) + (now.tv_nsec/1000);
++}
++
++static int init_timing_params(unsigned int new_duty_cycle,
++ unsigned int new_freq)
++{
++ if (1000 * 1000000L / new_freq * new_duty_cycle / 100 <=
++ LIRC_TRANSMITTER_LATENCY)
++ return -EINVAL;
++ if (1000 * 1000000L / new_freq * (100 - new_duty_cycle) / 100 <=
++ LIRC_TRANSMITTER_LATENCY)
++ return -EINVAL;
++ duty_cycle = new_duty_cycle;
++ freq = new_freq;
++ period = 1000 * 1000000L / freq;
++ pulse_width = period * duty_cycle / 100;
++ space_width = period - pulse_width;
++ dprintk("in init_timing_params, freq=%d pulse=%ld, "
++ "space=%ld\n", freq, pulse_width, space_width);
++ return 0;
++}
++
++static long send_pulse_softcarrier(unsigned long length)
++{
++ int flag;
++ unsigned long actual, target;
++ unsigned long actual_us, initial_us, target_us;
++
++ length *= 1000;
++
++ actual = 0; target = 0; flag = 0;
++ actual_us = read_current_us();
++
++ while (actual < length) {
++ if (flag) {
++ gpiochip->set(gpiochip, gpio_out_pin, invert);
++ target += space_width;
++ } else {
++ gpiochip->set(gpiochip, gpio_out_pin, !invert);
++ target += pulse_width;
++ }
++ initial_us = actual_us;
++ target_us = actual_us + (target - actual) / 1000;
++ /*
++ * Note - we've checked in ioctl that the pulse/space
++ * widths are big enough so that d is > 0
++ */
++ if ((int)(target_us - actual_us) > 0)
++ udelay(target_us - actual_us);
++ actual_us = read_current_us();
++ actual += (actual_us - initial_us) * 1000;
++ flag = !flag;
++ }
++ return (actual-length) / 1000;
++}
++
++static long send_pulse(unsigned long length)
++{
++ if (length <= 0)
++ return 0;
++
++ if (softcarrier) {
++ return send_pulse_softcarrier(length);
++ } else {
++ gpiochip->set(gpiochip, gpio_out_pin, !invert);
++ safe_udelay(length);
++ return 0;
++ }
++}
++
++static void send_space(long length)
++{
++ gpiochip->set(gpiochip, gpio_out_pin, invert);
++ if (length <= 0)
++ return;
++ safe_udelay(length);
++}
++
++static void rbwrite(int l)
++{
++ if (lirc_buffer_full(&rbuf)) {
++ /* no new signals will be accepted */
++ dprintk("Buffer overrun\n");
++ return;
++ }
++ lirc_buffer_write(&rbuf, (void *)&l);
++}
++
++static void frbwrite(int l)
++{
++ /* simple noise filter */
++ static int pulse, space;
++ static unsigned int ptr;
++
++ if (ptr > 0 && (l & PULSE_BIT)) {
++ pulse += l & PULSE_MASK;
++ if (pulse > 250) {
++ rbwrite(space);
++ rbwrite(pulse | PULSE_BIT);
++ ptr = 0;
++ pulse = 0;
++ }
++ return;
++ }
++ if (!(l & PULSE_BIT)) {
++ if (ptr == 0) {
++ if (l > 20000) {
++ space = l;
++ ptr++;
++ return;
++ }
++ } else {
++ if (l > 20000) {
++ space += pulse;
++ if (space > PULSE_MASK)
++ space = PULSE_MASK;
++ space += l;
++ if (space > PULSE_MASK)
++ space = PULSE_MASK;
++ pulse = 0;
++ return;
++ }
++ rbwrite(space);
++ rbwrite(pulse | PULSE_BIT);
++ ptr = 0;
++ pulse = 0;
++ }
++ }
++ rbwrite(l);
++}
++
++static irqreturn_t irq_handler(int i, void *blah, struct pt_regs *regs)
++{
++ struct timeval tv;
++ long deltv;
++ int data;
++ int signal;
++
++ /* use the GPIO signal level */
++ signal = gpiochip->get(gpiochip, gpio_in_pin);
++
++ if (sense != -1) {
++ /* get current time */
++ do_gettimeofday(&tv);
++
++ /* calc time since last interrupt in microseconds */
++ deltv = tv.tv_sec-lasttv.tv_sec;
++ if (tv.tv_sec < lasttv.tv_sec ||
++ (tv.tv_sec == lasttv.tv_sec &&
++ tv.tv_usec < lasttv.tv_usec)) {
++ printk(KERN_WARNING LIRC_DRIVER_NAME
++ ": AIEEEE: your clock just jumped backwards\n");
++ printk(KERN_WARNING LIRC_DRIVER_NAME
++ ": %d %d %lx %lx %lx %lx\n", signal, sense,
++ tv.tv_sec, lasttv.tv_sec,
++ tv.tv_usec, lasttv.tv_usec);
++ data = PULSE_MASK;
++ } else if (deltv > 15) {
++ data = PULSE_MASK; /* really long time */
++ if (!(signal^sense)) {
++ /* sanity check */
++ printk(KERN_WARNING LIRC_DRIVER_NAME
++ ": AIEEEE: %d %d %lx %lx %lx %lx\n",
++ signal, sense, tv.tv_sec, lasttv.tv_sec,
++ tv.tv_usec, lasttv.tv_usec);
++ /*
++ * detecting pulse while this
++ * MUST be a space!
++ */
++ sense = sense ? 0 : 1;
++ }
++ } else {
++ data = (int) (deltv*1000000 +
++ (tv.tv_usec - lasttv.tv_usec));
++ }
++ frbwrite(signal^sense ? data : (data|PULSE_BIT));
++ lasttv = tv;
++ wake_up_interruptible(&rbuf.wait_poll);
++ }
++
++ return IRQ_HANDLED;
++}
++
++static int is_right_chip(struct gpio_chip *chip, void *data)
++{
++ dprintk("is_right_chip %s %d\n", chip->label, strcmp(data, chip->label));
++
++ if (strcmp(data, chip->label) == 0)
++ return 1;
++ return 0;
++}
++
++static inline int read_bool_property(const struct device_node *np,
++ const char *propname,
++ bool *out_value)
++{
++ u32 value = 0;
++ int err = of_property_read_u32(np, propname, &value);
++ if (err == 0)
++ *out_value = (value != 0);
++ return err;
++}
++
++static void read_pin_settings(struct device_node *node)
++{
++ u32 pin;
++ int index;
++
++ for (index = 0;
++ of_property_read_u32_index(
++ node,
++ "brcm,pins",
++ index,
++ &pin) == 0;
++ index++) {
++ u32 function;
++ int err;
++ err = of_property_read_u32_index(
++ node,
++ "brcm,function",
++ index,
++ &function);
++ if (err == 0) {
++ if (function == 1) /* Output */
++ gpio_out_pin = pin;
++ else if (function == 0) /* Input */
++ gpio_in_pin = pin;
++ }
++ }
++}
++
++static int init_port(void)
++{
++ int i, nlow, nhigh, ret;
++ struct device_node *node;
++
++ node = lirc_rpi_dev->dev.of_node;
++
++ gpiochip = gpiochip_find("bcm2708_gpio", is_right_chip);
++
++ /*
++ * Because of the lack of a setpull function, only support
++ * pinctrl-bcm2835 if using device tree.
++ */
++ if (!gpiochip && node)
++ gpiochip = gpiochip_find("pinctrl-bcm2835", is_right_chip);
++
++ if (!gpiochip) {
++ pr_err(LIRC_DRIVER_NAME ": gpio chip not found!\n");
++ return -ENODEV;
++ }
++
++ if (node) {
++ struct device_node *pins_node;
++
++ pins_node = of_parse_phandle(node, "pinctrl-0", 0);
++ if (!pins_node) {
++ printk(KERN_ERR LIRC_DRIVER_NAME
++ ": pinctrl settings not found!\n");
++ ret = -EINVAL;
++ goto exit_init_port;
++ }
++
++ read_pin_settings(pins_node);
++
++ of_property_read_u32(node, "rpi,sense", &sense);
++
++ read_bool_property(node, "rpi,softcarrier", &softcarrier);
++
++ read_bool_property(node, "rpi,invert", &invert);
++
++ read_bool_property(node, "rpi,debug", &debug);
++
++ }
++ else
++ {
++ if (gpio_in_pin >= BCM2708_NR_GPIOS ||
++ gpio_out_pin >= BCM2708_NR_GPIOS) {
++ ret = -EINVAL;
++ printk(KERN_ERR LIRC_DRIVER_NAME
++ ": invalid GPIO pin(s) specified!\n");
++ goto exit_init_port;
++ }
++
++ if (gpio_request(gpio_out_pin, LIRC_DRIVER_NAME " ir/out")) {
++ printk(KERN_ALERT LIRC_DRIVER_NAME
++ ": cant claim gpio pin %d\n", gpio_out_pin);
++ ret = -ENODEV;
++ goto exit_init_port;
++ }
++
++ if (gpio_request(gpio_in_pin, LIRC_DRIVER_NAME " ir/in")) {
++ printk(KERN_ALERT LIRC_DRIVER_NAME
++ ": cant claim gpio pin %d\n", gpio_in_pin);
++ ret = -ENODEV;
++ goto exit_gpio_free_out_pin;
++ }
++
++ bcm2708_gpio_setpull(gpiochip, gpio_in_pin, gpio_in_pull);
++ gpiochip->direction_input(gpiochip, gpio_in_pin);
++ gpiochip->direction_output(gpiochip, gpio_out_pin, 1);
++ }
++
++ gpiochip->set(gpiochip, gpio_out_pin, invert);
++
++ irq_num = gpiochip->to_irq(gpiochip, gpio_in_pin);
++ dprintk("to_irq %d\n", irq_num);
++
++ /* if pin is high, then this must be an active low receiver. */
++ if (sense == -1) {
++ /* wait 1/2 sec for the power supply */
++ msleep(500);
++
++ /*
++ * probe 9 times every 0.04s, collect "votes" for
++ * active high/low
++ */
++ nlow = 0;
++ nhigh = 0;
++ for (i = 0; i < 9; i++) {
++ if (gpiochip->get(gpiochip, gpio_in_pin))
++ nlow++;
++ else
++ nhigh++;
++ msleep(40);
++ }
++ sense = (nlow >= nhigh ? 1 : 0);
++ printk(KERN_INFO LIRC_DRIVER_NAME
++ ": auto-detected active %s receiver on GPIO pin %d\n",
++ sense ? "low" : "high", gpio_in_pin);
++ } else {
++ printk(KERN_INFO LIRC_DRIVER_NAME
++ ": manually using active %s receiver on GPIO pin %d\n",
++ sense ? "low" : "high", gpio_in_pin);
++ }
++
++ return 0;
++
++ exit_gpio_free_out_pin:
++ gpio_free(gpio_out_pin);
++
++ exit_init_port:
++ return ret;
++}
++
++// called when the character device is opened
++static int set_use_inc(void *data)
++{
++ int result;
++
++ /* initialize timestamp */
++ do_gettimeofday(&lasttv);
++
++ result = request_irq(irq_num,
++ (irq_handler_t) irq_handler,
++ IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING,
++ LIRC_DRIVER_NAME, (void*) 0);
++
++ switch (result) {
++ case -EBUSY:
++ printk(KERN_ERR LIRC_DRIVER_NAME
++ ": IRQ %d is busy\n",
++ irq_num);
++ return -EBUSY;
++ case -EINVAL:
++ printk(KERN_ERR LIRC_DRIVER_NAME
++ ": Bad irq number or handler\n");
++ return -EINVAL;
++ default:
++ dprintk("Interrupt %d obtained\n",
++ irq_num);
++ break;
++ };
++
++ /* initialize pulse/space widths */
++ init_timing_params(duty_cycle, freq);
++
++ return 0;
++}
++
++static void set_use_dec(void *data)
++{
++ /* GPIO Pin Falling/Rising Edge Detect Disable */
++ irq_set_irq_type(irq_num, 0);
++ disable_irq(irq_num);
++
++ free_irq(irq_num, (void *) 0);
++
++ dprintk(KERN_INFO LIRC_DRIVER_NAME
++ ": freed IRQ %d\n", irq_num);
++}
++
++static ssize_t lirc_write(struct file *file, const char *buf,
++ size_t n, loff_t *ppos)
++{
++ int i, count;
++ unsigned long flags;
++ long delta = 0;
++ int *wbuf;
++
++ count = n / sizeof(int);
++ if (n % sizeof(int) || count % 2 == 0)
++ return -EINVAL;
++ wbuf = memdup_user(buf, n);
++ if (IS_ERR(wbuf))
++ return PTR_ERR(wbuf);
++ spin_lock_irqsave(&lock, flags);
++
++ for (i = 0; i < count; i++) {
++ if (i%2)
++ send_space(wbuf[i] - delta);
++ else
++ delta = send_pulse(wbuf[i]);
++ }
++ gpiochip->set(gpiochip, gpio_out_pin, invert);
++
++ spin_unlock_irqrestore(&lock, flags);
++ kfree(wbuf);
++ return n;
++}
++
++static long lirc_ioctl(struct file *filep, unsigned int cmd, unsigned long arg)
++{
++ int result;
++ __u32 value;
++
++ switch (cmd) {
++ case LIRC_GET_SEND_MODE:
++ return -ENOIOCTLCMD;
++ break;
++
++ case LIRC_SET_SEND_MODE:
++ result = get_user(value, (__u32 *) arg);
++ if (result)
++ return result;
++ /* only LIRC_MODE_PULSE supported */
++ if (value != LIRC_MODE_PULSE)
++ return -ENOSYS;
++ break;
++
++ case LIRC_GET_LENGTH:
++ return -ENOSYS;
++ break;
++
++ case LIRC_SET_SEND_DUTY_CYCLE:
++ dprintk("SET_SEND_DUTY_CYCLE\n");
++ result = get_user(value, (__u32 *) arg);
++ if (result)
++ return result;
++ if (value <= 0 || value > 100)
++ return -EINVAL;
++ return init_timing_params(value, freq);
++ break;
++
++ case LIRC_SET_SEND_CARRIER:
++ dprintk("SET_SEND_CARRIER\n");
++ result = get_user(value, (__u32 *) arg);
++ if (result)
++ return result;
++ if (value > 500000 || value < 20000)
++ return -EINVAL;
++ return init_timing_params(duty_cycle, value);
++ break;
++
++ default:
++ return lirc_dev_fop_ioctl(filep, cmd, arg);
++ }
++ return 0;
++}
++
++static const struct file_operations lirc_fops = {
++ .owner = THIS_MODULE,
++ .write = lirc_write,
++ .unlocked_ioctl = lirc_ioctl,
++ .read = lirc_dev_fop_read,
++ .poll = lirc_dev_fop_poll,
++ .open = lirc_dev_fop_open,
++ .release = lirc_dev_fop_close,
++ .llseek = no_llseek,
++};
++
++static struct lirc_driver driver = {
++ .name = LIRC_DRIVER_NAME,
++ .minor = -1,
++ .code_length = 1,
++ .sample_rate = 0,
++ .data = NULL,
++ .add_to_buf = NULL,
++ .rbuf = &rbuf,
++ .set_use_inc = set_use_inc,
++ .set_use_dec = set_use_dec,
++ .fops = &lirc_fops,
++ .dev = NULL,
++ .owner = THIS_MODULE,
++};
++
++static const struct of_device_id lirc_rpi_of_match[] = {
++ { .compatible = "rpi,lirc-rpi", },
++ {},
++};
++MODULE_DEVICE_TABLE(of, lirc_rpi_of_match);
++
++static struct platform_driver lirc_rpi_driver = {
++ .driver = {
++ .name = LIRC_DRIVER_NAME,
++ .owner = THIS_MODULE,
++ .of_match_table = of_match_ptr(lirc_rpi_of_match),
++ },
++};
++
++static int __init lirc_rpi_init(void)
++{
++ struct device_node *node;
++ int result;
++
++ /* Init read buffer. */
++ result = lirc_buffer_init(&rbuf, sizeof(int), RBUF_LEN);
++ if (result < 0)
++ return -ENOMEM;
++
++ result = platform_driver_register(&lirc_rpi_driver);
++ if (result) {
++ printk(KERN_ERR LIRC_DRIVER_NAME
++ ": lirc register returned %d\n", result);
++ goto exit_buffer_free;
++ }
++
++ node = of_find_compatible_node(NULL, NULL,
++ lirc_rpi_of_match[0].compatible);
++
++ if (node) {
++ /* DT-enabled */
++ lirc_rpi_dev = of_find_device_by_node(node);
++ WARN_ON(lirc_rpi_dev->dev.of_node != node);
++ of_node_put(node);
++ }
++ else {
++ lirc_rpi_dev = platform_device_alloc(LIRC_DRIVER_NAME, 0);
++ if (!lirc_rpi_dev) {
++ result = -ENOMEM;
++ goto exit_driver_unregister;
++ }
++
++ result = platform_device_add(lirc_rpi_dev);
++ if (result)
++ goto exit_device_put;
++ }
++
++ return 0;
++
++ exit_device_put:
++ platform_device_put(lirc_rpi_dev);
++
++ exit_driver_unregister:
++ platform_driver_unregister(&lirc_rpi_driver);
++
++ exit_buffer_free:
++ lirc_buffer_free(&rbuf);
++
++ return result;
++}
++
++static void lirc_rpi_exit(void)
++{
++ if (!lirc_rpi_dev->dev.of_node)
++ platform_device_unregister(lirc_rpi_dev);
++ platform_driver_unregister(&lirc_rpi_driver);
++ lirc_buffer_free(&rbuf);
++}
++
++static int __init lirc_rpi_init_module(void)
++{
++ int result;
++
++ result = lirc_rpi_init();
++ if (result)
++ return result;
++
++ result = init_port();
++ if (result < 0)
++ goto exit_rpi;
++
++ driver.features = LIRC_CAN_SET_SEND_DUTY_CYCLE |
++ LIRC_CAN_SET_SEND_CARRIER |
++ LIRC_CAN_SEND_PULSE |
++ LIRC_CAN_REC_MODE2;
++
++ driver.dev = &lirc_rpi_dev->dev;
++ driver.minor = lirc_register_driver(&driver);
++
++ if (driver.minor < 0) {
++ printk(KERN_ERR LIRC_DRIVER_NAME
++ ": device registration failed with %d\n", result);
++ result = -EIO;
++ goto exit_rpi;
++ }
++
++ printk(KERN_INFO LIRC_DRIVER_NAME ": driver registered!\n");
++
++ return 0;
++
++ exit_rpi:
++ lirc_rpi_exit();
++
++ return result;
++}
++
++static void __exit lirc_rpi_exit_module(void)
++{
++ lirc_unregister_driver(driver.minor);
++
++ gpio_free(gpio_out_pin);
++ gpio_free(gpio_in_pin);
++
++ lirc_rpi_exit();
++
++ printk(KERN_INFO LIRC_DRIVER_NAME ": cleaned up module\n");
++}
++
++module_init(lirc_rpi_init_module);
++module_exit(lirc_rpi_exit_module);
++
++MODULE_DESCRIPTION("Infra-red receiver and blaster driver for Raspberry Pi GPIO.");
++MODULE_AUTHOR("Aron Robert Szabo <aron@reon.hu>");
++MODULE_AUTHOR("Michael Bishop <cleverca22@gmail.com>");
++MODULE_LICENSE("GPL");
++
++module_param(gpio_out_pin, int, S_IRUGO);
++MODULE_PARM_DESC(gpio_out_pin, "GPIO output/transmitter pin number of the BCM"
++ " processor. (default 17");
++
++module_param(gpio_in_pin, int, S_IRUGO);
++MODULE_PARM_DESC(gpio_in_pin, "GPIO input pin number of the BCM processor."
++ " (default 18");
++
++module_param(gpio_in_pull, int, S_IRUGO);
++MODULE_PARM_DESC(gpio_in_pull, "GPIO input pin pull configuration."
++ " (0 = off, 1 = up, 2 = down, default down)");
++
++module_param(sense, int, S_IRUGO);
++MODULE_PARM_DESC(sense, "Override autodetection of IR receiver circuit"
++ " (0 = active high, 1 = active low )");
++
++module_param(softcarrier, bool, S_IRUGO);
++MODULE_PARM_DESC(softcarrier, "Software carrier (0 = off, 1 = on, default on)");
++
++module_param(invert, bool, S_IRUGO);
++MODULE_PARM_DESC(invert, "Invert output (0 = off, 1 = on, default off");
++
++module_param(debug, bool, S_IRUGO | S_IWUSR);
++MODULE_PARM_DESC(debug, "Enable debugging messages");
+diff -Nur linux-4.1.3/drivers/staging/media/lirc/lirc_xbox.c linux-xbian-rpi/drivers/staging/media/lirc/lirc_xbox.c
+--- linux-4.1.3/drivers/staging/media/lirc/lirc_xbox.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/staging/media/lirc/lirc_xbox.c 2015-07-28 01:20:58.437184915 +0200
+@@ -0,0 +1,993 @@
++/*
++ * lirc_xbox - USB remote support for LIRC
++ * (supports Microsoft XBOX DVD Dongle)
++ *
++ * Copyright (C) 2003-2004 Paul Miller <pmiller9@users.sourceforge.net>
++ *
++ * This driver was derived from:
++ * Vladimir Dergachev <volodya@minspring.com>'s 2002
++ * "USB ATI Remote support" (input device)
++ * Adrian Dewhurst <sailor-lk@sailorfrag.net>'s 2002
++ * "USB StreamZap remote driver" (LIRC)
++ * Artur Lipowski <alipowski@kki.net.pl>'s 2002
++ * "lirc_dev" and "lirc_gpio" LIRC modules
++ * Michael Wojciechowski
++ * initial xbox support
++ * Vassilis Virvilis <vasvir@iit.demokritos.gr> 2006
++ * reworked the patch for lirc submission
++ * Paul Miller's <pmiller9@users.sourceforge.net> 2004
++ * lirc_atiusb - removed all ati remote support
++ * $Id: lirc_xbox.c,v 1.88 2011/06/03 11:11:11 jmartin Exp $
++ */
++
++/*
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++
++#include <linux/version.h>
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 33)
++#include <linux/autoconf.h>
++#endif
++
++#include <linux/kernel.h>
++#include <linux/errno.h>
++#include <linux/init.h>
++#include <linux/slab.h>
++#include <linux/module.h>
++#include <linux/kmod.h>
++//#include <linux/smp_lock.h>
++#include <linux/completion.h>
++#include <linux/uaccess.h>
++#include <linux/usb.h>
++#include <linux/poll.h>
++#include <linux/wait.h>
++#include <linux/list.h>
++
++#include "kcompat.h"
++#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35)
++#include <media/lirc.h>
++#include <media/lirc_dev.h>
++#else
++#include "drivers/lirc.h"
++#include "drivers/lirc_dev/lirc_dev.h"
++#endif
++
++#define DRIVER_VERSION "$Revision: 0.01 $"
++#define DRIVER_AUTHOR "Jason Martin <austinspartan@users.sourceforge.net>"
++#define DRIVER_DESC "XBOX DVD Dongle USB remote driver for LIRC"
++#define DRIVER_NAME "lirc_xbox"
++
++#define CODE_LENGTH 6
++#define CODE_MIN_LENGTH 6
++#define DECODE_LENGTH 1
++
++/* module parameters */
++#ifdef CONFIG_USB_DEBUG
++static int debug = 1;
++#else
++static int debug;
++#endif
++
++#define dprintk(fmt, args...) \
++ do { \
++ if (debug) \
++ printk(KERN_DEBUG fmt, ## args); \
++ } while (0)
++
++/*
++ * USB_BUFF_LEN must be the maximum value of the code_length array.
++ * It is used for static arrays.
++ */
++#define USB_BUFF_LEN 6
++
++static int mask = 0xFFFF; /* channel acceptance bit mask */
++static int unique; /* enable channel-specific codes */
++static int repeat = 10; /* repeat time in 1/100 sec */
++static unsigned long repeat_jiffies; /* repeat timeout */
++
++/* get hi and low bytes of a 16-bits int */
++#define HI(a) ((unsigned char)((a) >> 8))
++#define LO(a) ((unsigned char)((a) & 0xff))
++
++/* general constants */
++#define SEND_FLAG_IN_PROGRESS 1
++#define SEND_FLAG_COMPLETE 2
++#define FREE_ALL 0xFF
++
++/* endpoints */
++#define EP_KEYS 0
++#define EP_MOUSE 1
++#define EP_MOUSE_ADDR 0x81
++#define EP_KEYS_ADDR 0x82
++
++/* USB vendor ids for XBOX DVD Dongles */
++#define VENDOR_MS1 0x040b
++#define VENDOR_MS2 0x045e
++#define VENDOR_MS3 0xFFFF
++
++static struct usb_device_id usb_remote_table[] = {
++ /* Gamester Xbox DVD Movie Playback Kit IR */
++ { USB_DEVICE(VENDOR_MS1, 0x6521) },
++
++ /* Microsoft Xbox DVD Movie Playback Kit IR */
++ { USB_DEVICE(VENDOR_MS2, 0x0284) },
++
++ /*
++ * Some Chinese manufacturer -- conflicts with the joystick from the
++ * same manufacturer
++ */
++ { USB_DEVICE(VENDOR_MS3, 0xFFFF) },
++
++ /* Terminating entry */
++ { }
++};
++
++/* init strings */
++#define USB_OUTLEN 7
++
++static char init1[] = {0x01, 0x00, 0x20, 0x14};
++static char init2[] = {0x01, 0x00, 0x20, 0x14, 0x20, 0x20, 0x20};
++
++struct in_endpt {
++ /* inner link in list of endpoints for the remote specified by ir */
++ struct list_head iep_list_link;
++ struct xbox_dev *ir;
++ struct urb *urb;
++ struct usb_endpoint_descriptor *ep;
++
++ /* buffers and dma */
++ unsigned char *buf;
++ unsigned int len;
++ dma_addr_t dma;
++
++ /* handle repeats */
++ unsigned char old[USB_BUFF_LEN];
++ unsigned long old_jiffies;
++};
++
++struct out_endpt {
++ struct xbox_dev *ir;
++ struct urb *urb;
++ struct usb_endpoint_descriptor *ep;
++
++ /* buffers and dma */
++ unsigned char *buf;
++ dma_addr_t dma;
++
++ /* handle sending (init strings) */
++ int send_flags;
++ wait_queue_head_t wait;
++};
++
++
++/* data structure for each usb remote */
++struct xbox_dev {
++ /* inner link in list of all remotes managed by this module */
++ struct list_head remote_list_link;
++ /* Number of usb interfaces associated with this device */
++ int dev_refcount;
++
++ /* usb */
++ struct usb_device *usbdev;
++ /* Head link to list of all inbound endpoints in this remote */
++ struct list_head iep_listhead;
++ struct out_endpt *out_init;
++ int devnum;
++
++ /* lirc */
++ struct lirc_driver *d;
++ int connected;
++
++ /* locking */
++ struct mutex lock;
++};
++
++/* list of all registered devices via the remote_list_link in xbox_dev */
++static struct list_head remote_list;
++
++/*
++ * Convenience macros to retrieve a pointer to the surrounding struct from
++ * the given list_head reference within, pointed at by link.
++ */
++#define get_iep_from_link(link) \
++ list_entry((link), struct in_endpt, iep_list_link);
++#define get_irctl_from_link(link) \
++ list_entry((link), struct xbox_dev, remote_list_link);
++
++/* send packet - used to initialize remote */
++static void send_packet(struct out_endpt *oep, u16 cmd, unsigned char *data)
++{
++ struct xbox_dev *ir = oep->ir;
++ DECLARE_WAITQUEUE(wait, current);
++ int timeout = HZ; /* 1 second */
++ unsigned char buf[USB_OUTLEN];
++
++ dprintk(DRIVER_NAME "[%d]: send called (%#x)\n", ir->devnum, cmd);
++
++ mutex_lock(&ir->lock);
++ oep->urb->transfer_buffer_length = LO(cmd) + 1;
++ oep->urb->dev = oep->ir->usbdev;
++ oep->send_flags = SEND_FLAG_IN_PROGRESS;
++
++ memcpy(buf+1, data, LO(cmd));
++ buf[0] = HI(cmd);
++ memcpy(oep->buf, buf, LO(cmd)+1);
++
++ set_current_state(TASK_INTERRUPTIBLE);
++ add_wait_queue(&oep->wait, &wait);
++
++ if (usb_submit_urb(oep->urb, GFP_ATOMIC)) {
++ set_current_state(TASK_RUNNING);
++ remove_wait_queue(&oep->wait, &wait);
++ mutex_unlock(&ir->lock);
++ return;
++ }
++ mutex_unlock(&ir->lock);
++
++ while (timeout && (oep->urb->status == -EINPROGRESS)
++ && !(oep->send_flags & SEND_FLAG_COMPLETE)) {
++ timeout = schedule_timeout(timeout);
++ rmb();
++ }
++
++ dprintk(DRIVER_NAME "[%d]: send complete (%#x)\n", ir->devnum, cmd);
++
++ set_current_state(TASK_RUNNING);
++ remove_wait_queue(&oep->wait, &wait);
++ oep->urb->transfer_flags |= URB_ASYNC_UNLINK;
++ usb_unlink_urb(oep->urb);
++}
++
++static int unregister_from_lirc(struct xbox_dev *ir)
++{
++ struct lirc_driver *d = ir->d;
++ int devnum;
++
++ devnum = ir->devnum;
++ dprintk(DRIVER_NAME "[%d]: unregister from lirc called\n", devnum);
++
++ lirc_unregister_driver(d->minor);
++
++ printk(DRIVER_NAME "[%d]: usb remote disconnected\n", devnum);
++ return 0;
++}
++
++static int set_use_inc(void *data)
++{
++ struct xbox_dev *ir = data;
++ struct list_head *pos, *n;
++ struct in_endpt *iep;
++ int rtn;
++
++ if (!ir) {
++ printk(DRIVER_NAME "[?]: set_use_inc called with no context\n");
++ return -EIO;
++ }
++ dprintk(DRIVER_NAME "[%d]: set use inc\n", ir->devnum);
++
++ mutex_lock(&ir->lock);
++ if (!ir->connected) {
++ if (!ir->usbdev) {
++ mutex_unlock(&ir->lock);
++ dprintk(DRIVER_NAME "[%d]: !ir->usbdev\n", ir->devnum);
++ return -ENOENT;
++ }
++
++ /* Iterate through the inbound endpoints */
++ list_for_each_safe(pos, n, &ir->iep_listhead) {
++ /* extract the current in_endpt */
++ iep = get_iep_from_link(pos);
++ iep->urb->dev = ir->usbdev;
++ dprintk(DRIVER_NAME "[%d]: linking iep 0x%02x (%p)\n",
++ ir->devnum, iep->ep->bEndpointAddress, iep);
++ rtn = usb_submit_urb(iep->urb, GFP_ATOMIC);
++ if (rtn) {
++ printk(DRIVER_NAME "[%d]: open result = %d "
++ "error submitting urb\n",
++ ir->devnum, rtn);
++ mutex_unlock(&ir->lock);
++ return -EIO;
++ }
++ }
++ ir->connected = 1;
++ }
++ mutex_unlock(&ir->lock);
++
++ return 0;
++}
++
++static void set_use_dec(void *data)
++{
++ struct xbox_dev *ir = data;
++ struct list_head *pos, *n;
++ struct in_endpt *iep;
++
++ if (!ir) {
++ printk(DRIVER_NAME "[?]: set_use_dec called with no context\n");
++ return;
++ }
++ dprintk(DRIVER_NAME "[%d]: set use dec\n", ir->devnum);
++
++ mutex_lock(&ir->lock);
++ if (ir->connected) {
++ /* Free inbound usb urbs */
++ list_for_each_safe(pos, n, &ir->iep_listhead) {
++ iep = get_iep_from_link(pos);
++ dprintk(DRIVER_NAME "[%d]: unlinking iep 0x%02x (%p)\n",
++ ir->devnum, iep->ep->bEndpointAddress, iep);
++ usb_kill_urb(iep->urb);
++ }
++ ir->connected = 0;
++ }
++ mutex_unlock(&ir->lock);
++}
++
++static void print_data(struct in_endpt *iep, char *buf, int len)
++{
++ const int clen = CODE_LENGTH;
++ char codes[clen * 3 + 1];
++ int i;
++
++ if (len <= 0)
++ return;
++
++ for (i = 0; i < len && i < clen; i++)
++ snprintf(codes+i*3, 4, "%02x ", buf[i] & 0xFF);
++ printk(DRIVER_NAME "[%d]: data received %s (ep=0x%x length=%d)\n",
++ iep->ir->devnum, codes, iep->ep->bEndpointAddress, len);
++}
++
++static int code_check_xbox(struct in_endpt *iep, int len)
++{
++ // struct xbox_dev *ir = iep->ir;
++ const int clen = CODE_LENGTH;
++
++ if (len != clen) {
++ dprintk(DRIVER_NAME ": We got %d instead of %d bytes from xbox "
++ "ir.. ?\n", len, clen);
++ return -1;
++ }
++
++ /* check for repeats */
++ if (memcmp(iep->old, iep->buf, len) == 0) {
++ if (iep->old_jiffies + repeat_jiffies > jiffies)
++ return -1;
++ } else {
++ /*
++ * the third byte of xbox ir packet seems to contain key info
++ * the last two bytes are.. some kind of clock?
++ */
++ iep->buf[0] = iep->buf[2];
++ memset(iep->buf + 1, 0, len - 1);
++ memcpy(iep->old, iep->buf, len);
++ }
++ iep->old_jiffies = jiffies;
++
++ return 0;
++}
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 19)
++static void usb_remote_recv(struct urb *urb, struct pt_regs *regs)
++#else
++static void usb_remote_recv(struct urb *urb)
++#endif
++{
++ struct in_endpt *iep;
++ int len, result = -1;
++
++ if (!urb)
++ return;
++ iep = urb->context;
++ if (!iep) {
++ urb->transfer_flags |= URB_ASYNC_UNLINK;
++ usb_unlink_urb(urb);
++ return;
++ }
++ if (!iep->ir->usbdev)
++ return;
++
++ len = urb->actual_length;
++ if (debug)
++ print_data(iep, urb->transfer_buffer, len);
++
++ switch (urb->status) {
++
++ case 0:
++ result = code_check_xbox(iep, len);
++
++ if (result < 0)
++ break;
++
++ lirc_buffer_write(iep->ir->d->rbuf, iep->buf);
++ wake_up(&iep->ir->d->rbuf->wait_poll);
++ break;
++
++ case -ECONNRESET:
++ case -ENOENT:
++ case -ESHUTDOWN:
++ urb->transfer_flags |= URB_ASYNC_UNLINK;
++ usb_unlink_urb(urb);
++ return;
++
++ case -EPIPE:
++ default:
++ break;
++ }
++
++ usb_submit_urb(urb, GFP_ATOMIC);
++}
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 19)
++static void usb_remote_send(struct urb *urb, struct pt_regs *regs)
++#else
++static void usb_remote_send(struct urb *urb)
++#endif
++{
++ struct out_endpt *oep;
++
++ if (!urb)
++ return;
++ oep = urb->context;
++ if (!oep) {
++ urb->transfer_flags |= URB_ASYNC_UNLINK;
++ usb_unlink_urb(urb);
++ return;
++ }
++ if (!oep->ir->usbdev)
++ return;
++
++ dprintk(DRIVER_NAME "[%d]: usb out called\n", oep->ir->devnum);
++
++ if (urb->status)
++ return;
++
++ oep->send_flags |= SEND_FLAG_COMPLETE;
++ wmb();
++ if (waitqueue_active(&oep->wait))
++ wake_up(&oep->wait);
++}
++
++
++/*
++ * Initialization and removal
++ */
++
++/*
++ * Free iep according to mem_failure which specifies a checkpoint into the
++ * initialization sequence for rollback recovery.
++ */
++static void free_in_endpt(struct in_endpt *iep, int mem_failure)
++{
++ struct xbox_dev *ir;
++ dprintk(DRIVER_NAME ": free_in_endpt(%p, %d)\n", iep, mem_failure);
++ if (!iep)
++ return;
++
++ ir = iep->ir;
++ if (!ir) {
++ dprintk(DRIVER_NAME ": free_in_endpt: WARNING! null ir\n");
++ return;
++ }
++ mutex_lock(&ir->lock);
++ switch (mem_failure) {
++ case FREE_ALL:
++ case 5:
++ list_del(&iep->iep_list_link);
++ dprintk(DRIVER_NAME "[%d]: free_in_endpt removing ep=0x%0x "
++ "from list\n", ir->devnum, iep->ep->bEndpointAddress);
++ case 4:
++ if (iep->urb) {
++ iep->urb->transfer_flags |= URB_ASYNC_UNLINK;
++ usb_unlink_urb(iep->urb);
++ usb_free_urb(iep->urb);
++ iep->urb = 0;
++ } else
++ dprintk(DRIVER_NAME "[%d]: free_in_endpt null urb!\n",
++ ir->devnum);
++ case 3:
++ usb_free_coherent(iep->ir->usbdev, iep->len, iep->buf, iep->dma);
++ iep->buf = 0;
++ case 2:
++ kfree(iep);
++ }
++ mutex_unlock(&ir->lock);
++}
++
++/*
++ * Construct a new inbound endpoint for this remote, and add it to the list of
++ * in_epts in ir.
++ */
++static struct in_endpt *new_in_endpt(struct xbox_dev *ir,
++ struct usb_endpoint_descriptor *ep)
++{
++ struct usb_device *dev = ir->usbdev;
++ struct in_endpt *iep;
++ int pipe, maxp, len, addr;
++ int mem_failure;
++
++ addr = ep->bEndpointAddress;
++ pipe = usb_rcvintpipe(dev, addr);
++ maxp = usb_maxpacket(dev, pipe, usb_pipeout(pipe));
++
++/* len = (maxp > USB_BUFLEN) ? USB_BUFLEN : maxp;
++ * len -= (len % CODE_LENGTH); */
++ len = CODE_LENGTH;
++
++ dprintk(DRIVER_NAME "[%d]: acceptable inbound endpoint (0x%x) found "
++ "(maxp=%d len=%d)\n", ir->devnum, addr, maxp, len);
++
++ mem_failure = 0;
++ iep = kzalloc(sizeof(*iep), GFP_KERNEL);
++ if (!iep) {
++ mem_failure = 1;
++ goto new_in_endpt_failure_check;
++ }
++ iep->ir = ir;
++ iep->ep = ep;
++ iep->len = len;
++
++ iep->buf = usb_alloc_coherent(dev, len, GFP_ATOMIC, &iep->dma);
++ if (!iep->buf) {
++ mem_failure = 2;
++ goto new_in_endpt_failure_check;
++ }
++
++ iep->urb = usb_alloc_urb(0, GFP_KERNEL);
++ if (!iep->urb)
++ mem_failure = 3;
++
++new_in_endpt_failure_check:
++
++ if (mem_failure) {
++ free_in_endpt(iep, mem_failure);
++ printk(DRIVER_NAME "[%d]: ep=0x%x out of memory (code=%d)\n",
++ ir->devnum, addr, mem_failure);
++ return NULL;
++ }
++ list_add_tail(&iep->iep_list_link, &ir->iep_listhead);
++ dprintk(DRIVER_NAME "[%d]: adding ep=0x%0x to list\n",
++ ir->devnum, iep->ep->bEndpointAddress);
++ return iep;
++}
++
++static void free_out_endpt(struct out_endpt *oep, int mem_failure)
++{
++ struct xbox_dev *ir;
++ dprintk(DRIVER_NAME ": free_out_endpt(%p, %d)\n", oep, mem_failure);
++ if (!oep)
++ return;
++
++ wake_up_all(&oep->wait);
++
++ ir = oep->ir;
++ if (!ir) {
++ dprintk(DRIVER_NAME ": free_out_endpt: WARNING! null ir\n");
++ return;
++ }
++ mutex_lock(&ir->lock);
++ switch (mem_failure) {
++ case FREE_ALL:
++ case 4:
++ if (oep->urb) {
++ oep->urb->transfer_flags |= URB_ASYNC_UNLINK;
++ usb_unlink_urb(oep->urb);
++ usb_free_urb(oep->urb);
++ oep->urb = 0;
++ } else {
++ dprintk(DRIVER_NAME "[%d]: free_out_endpt: null urb!\n",
++ ir->devnum);
++ }
++ case 3:
++ usb_free_coherent(oep->ir->usbdev, USB_OUTLEN,
++ oep->buf, oep->dma);
++ oep->buf = 0;
++ case 2:
++ kfree(oep);
++ }
++ mutex_unlock(&ir->lock);
++}
++
++static struct out_endpt *new_out_endpt(struct xbox_dev *ir,
++ struct usb_endpoint_descriptor *ep)
++{
++ struct usb_device *dev = ir->usbdev;
++ struct out_endpt *oep;
++ int mem_failure;
++
++ dprintk(DRIVER_NAME "[%d]: acceptable outbound endpoint (0x%x) found\n",
++ ir->devnum, ep->bEndpointAddress);
++
++ mem_failure = 0;
++ oep = kzalloc(sizeof(*oep), GFP_KERNEL);
++ if (!oep)
++ mem_failure = 1;
++ else {
++ oep->ir = ir;
++ oep->ep = ep;
++ init_waitqueue_head(&oep->wait);
++
++ oep->buf = usb_alloc_coherent(dev, USB_OUTLEN,
++ GFP_ATOMIC, &oep->dma);
++ if (!oep->buf)
++ mem_failure = 2;
++ else {
++ oep->urb = usb_alloc_urb(0, GFP_KERNEL);
++ if (!oep->urb)
++ mem_failure = 3;
++ }
++ }
++ if (mem_failure) {
++ free_out_endpt(oep, mem_failure);
++ printk(DRIVER_NAME "[%d]: ep=0x%x out of memory (code=%d)\n",
++ ir->devnum, ep->bEndpointAddress, mem_failure);
++ return NULL;
++ }
++ return oep;
++}
++
++static void free_irctl(struct xbox_dev *ir, int mem_failure)
++{
++ struct list_head *pos, *n;
++ struct in_endpt *in;
++ dprintk(DRIVER_NAME ": free_irctl(%p, %d)\n", ir, mem_failure);
++
++ if (!ir)
++ return;
++
++ list_for_each_safe(pos, n, &ir->iep_listhead) {
++ in = get_iep_from_link(pos);
++ free_in_endpt(in, FREE_ALL);
++ }
++ if (ir->out_init) {
++ free_out_endpt(ir->out_init, FREE_ALL);
++ ir->out_init = NULL;
++ }
++
++ mutex_lock(&ir->lock);
++ switch (mem_failure) {
++ case FREE_ALL:
++ case 6:
++ if (!--ir->dev_refcount) {
++ list_del(&ir->remote_list_link);
++ dprintk(DRIVER_NAME "[%d]: free_irctl: removing "
++ "remote from list\n", ir->devnum);
++ } else {
++ dprintk(DRIVER_NAME "[%d]: free_irctl: refcount at %d,"
++ "aborting free_irctl\n",
++ ir->devnum, ir->dev_refcount);
++ mutex_unlock(&ir->lock);
++ return;
++ }
++ case 5:
++ case 4:
++ case 3:
++ if (ir->d) {
++ switch (mem_failure) {
++ case 5:
++ lirc_buffer_free(ir->d->rbuf);
++ case 4:
++ kfree(ir->d->rbuf);
++ case 3:
++ kfree(ir->d);
++ }
++ } else
++ printk(DRIVER_NAME "[%d]: ir->d is a null pointer!\n",
++ ir->devnum);
++ case 2:
++ mutex_unlock(&ir->lock);
++ kfree(ir);
++ return;
++ }
++ mutex_unlock(&ir->lock);
++}
++
++static struct xbox_dev *new_irctl(struct usb_interface *intf)
++{
++ struct usb_device *dev = interface_to_usbdev(intf);
++ struct xbox_dev *ir;
++ struct lirc_driver *driver;
++ int devnum, dclen;
++ int mem_failure;
++
++ devnum = dev->devnum;
++
++ dprintk(DRIVER_NAME "[%d]: remote type = XBOX DVD Dongle\n", devnum);
++
++ mem_failure = 0;
++ ir = kzalloc(sizeof(*ir), GFP_KERNEL);
++ if (!ir) {
++ mem_failure = 1;
++ goto new_irctl_failure_check;
++ }
++
++ dclen = DECODE_LENGTH;
++
++ /*
++ * add this infrared remote struct to remote_list, keeping track
++ * of the number of drivers registered.
++ */
++ dprintk(DRIVER_NAME "[%d]: adding remote to list\n", devnum);
++ list_add_tail(&ir->remote_list_link, &remote_list);
++ ir->dev_refcount = 1;
++
++ driver = kzalloc(sizeof(*driver), GFP_KERNEL);
++ if (!driver) {
++ mem_failure = 2;
++ goto new_irctl_failure_check;
++ }
++
++ ir->d = driver;
++ driver->rbuf = kmalloc(sizeof(*(driver->rbuf)), GFP_KERNEL);
++ if (!driver->rbuf) {
++ mem_failure = 3;
++ goto new_irctl_failure_check;
++ }
++
++ if (lirc_buffer_init(driver->rbuf, dclen, 2)) {
++ mem_failure = 4;
++ goto new_irctl_failure_check;
++ }
++
++ strcpy(driver->name, DRIVER_NAME " ");
++ driver->minor = -1;
++ driver->code_length = dclen * 8;
++ driver->features = LIRC_CAN_REC_LIRCCODE;
++ driver->data = ir;
++ driver->set_use_inc = &set_use_inc;
++ driver->set_use_dec = &set_use_dec;
++ driver->dev = &intf->dev;
++ driver->owner = THIS_MODULE;
++ ir->usbdev = dev;
++ ir->devnum = devnum;
++
++ mutex_init(&ir->lock);
++ INIT_LIST_HEAD(&ir->iep_listhead);
++
++new_irctl_failure_check:
++
++ if (mem_failure) {
++ free_irctl(ir, mem_failure);
++ printk(DRIVER_NAME "[%d]: out of memory (code=%d)\n",
++ devnum, mem_failure);
++ return NULL;
++ }
++ return ir;
++}
++
++/*
++ * Scan the global list of remotes to see if the device listed is one of them.
++ * If it is, the corresponding xbox_dev is returned, with its dev_refcount
++ * incremented. Otherwise, returns null.
++ */
++static struct xbox_dev *get_prior_reg_ir(struct usb_device *dev)
++{
++ struct list_head *pos;
++ struct xbox_dev *ir = NULL;
++
++ dprintk(DRIVER_NAME "[%d]: scanning remote_list...\n", dev->devnum);
++ list_for_each(pos, &remote_list) {
++ ir = get_irctl_from_link(pos);
++ if (ir->usbdev != dev) {
++ dprintk(DRIVER_NAME "[%d]: device %d isn't it...",
++ dev->devnum, ir->devnum);
++ ir = NULL;
++ } else {
++ dprintk(DRIVER_NAME "[%d]: prior instance found.\n",
++ dev->devnum);
++ ir->dev_refcount++;
++ break;
++ }
++ }
++ return ir;
++}
++
++/*
++ * If the USB interface has an out endpoint for control.
++ */
++static void send_outbound_init(struct xbox_dev *ir)
++{
++ if (ir->out_init) {
++ struct out_endpt *oep = ir->out_init;
++ dprintk(DRIVER_NAME "[%d]: usb_remote_probe: initializing "
++ "outbound ep\n", ir->devnum);
++ usb_fill_int_urb(oep->urb, ir->usbdev,
++ usb_sndintpipe(ir->usbdev, oep->ep->bEndpointAddress),
++ oep->buf, USB_OUTLEN, usb_remote_send,
++ oep, oep->ep->bInterval);
++ oep->urb->transfer_dma = oep->dma;
++ oep->urb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP;
++
++ send_packet(oep, 0x8004, init1);
++ send_packet(oep, 0x8007, init2);
++ }
++}
++
++/* Log driver and usb info */
++static void log_usb_dev_info(struct usb_device *dev)
++{
++ char buf[63], name[128] = "";
++
++ if (dev->descriptor.iManufacturer
++ && usb_string(dev, dev->descriptor.iManufacturer,
++ buf, sizeof(buf)) > 0)
++ strlcpy(name, buf, sizeof(name));
++ if (dev->descriptor.iProduct
++ && usb_string(dev, dev->descriptor.iProduct, buf, sizeof(buf)) > 0)
++ snprintf(name + strlen(name), sizeof(name) - strlen(name),
++ " %s", buf);
++ printk(DRIVER_NAME "[%d]: %s on usb%d:%d\n", dev->devnum, name,
++ dev->bus->busnum, dev->devnum);
++}
++
++
++static int usb_remote_probe(struct usb_interface *intf,
++ const struct usb_device_id *id)
++{
++ struct usb_device *dev = interface_to_usbdev(intf);
++ struct usb_host_interface *idesc;
++ struct usb_endpoint_descriptor *ep;
++ struct in_endpt *iep;
++ struct xbox_dev *ir;
++ int i;
++
++ dprintk(DRIVER_NAME "[%d]: usb_remote_probe: dev:%p, intf:%p, id:%p)\n",
++ dev->devnum, dev, intf, id);
++
++ idesc = intf->cur_altsetting;
++
++ /* Check if a usb remote has already been registered for this device */
++ ir = get_prior_reg_ir(dev);
++
++ if (!ir) {
++ ir = new_irctl(intf);
++ if (!ir)
++ return -ENOMEM;
++ }
++
++ /*
++ * step through the endpoints to find first in and first out endpoint
++ * of type interrupt transfer
++ */
++ for (i = 0; i < idesc->desc.bNumEndpoints; ++i) {
++ ep = &idesc->endpoint[i].desc;
++ dprintk(DRIVER_NAME "[%d]: processing endpoint %d\n",
++ dev->devnum, i);
++ if (((ep->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ==
++ USB_DIR_IN) &&
++ ((ep->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) ==
++ USB_ENDPOINT_XFER_INT)) {
++
++ iep = new_in_endpt(ir, ep);
++ if (iep)
++ {
++ usb_fill_int_urb(iep->urb, dev,
++ usb_rcvintpipe(dev,
++ iep->ep->bEndpointAddress),
++ iep->buf, iep->len, usb_remote_recv,
++ iep, iep->ep->bInterval);
++ iep->urb->transfer_dma = iep->dma;
++ iep->urb->transfer_flags |=
++ URB_NO_TRANSFER_DMA_MAP;
++ }
++ }
++
++ if (((ep->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ==
++ USB_DIR_OUT) &&
++ ((ep->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) ==
++ USB_ENDPOINT_XFER_INT) &&
++ (ir->out_init == NULL))
++ ir->out_init = new_out_endpt(ir, ep);
++ }
++ if (list_empty(&ir->iep_listhead)) {
++ printk(DRIVER_NAME "[%d]: inbound endpoint not found\n",
++ ir->devnum);
++ free_irctl(ir, FREE_ALL);
++ return -ENODEV;
++ }
++ if (ir->dev_refcount == 1) {
++ ir->d->minor = lirc_register_driver(ir->d);
++ if (ir->d->minor < 0) {
++ free_irctl(ir, FREE_ALL);
++ return -ENODEV;
++ }
++
++ /* Note new driver registration in kernel logs */
++ log_usb_dev_info(dev);
++
++ /* outbound data (initialization) */
++ send_outbound_init(ir);
++ }
++
++ usb_set_intfdata(intf, ir);
++ return 0;
++}
++
++static void usb_remote_disconnect(struct usb_interface *intf)
++{
++ /* struct usb_device *dev = interface_to_usbdev(intf); */
++ struct xbox_dev *ir = usb_get_intfdata(intf);
++ usb_set_intfdata(intf, NULL);
++
++ dprintk(DRIVER_NAME ": disconnecting remote %d:\n",
++ (ir ? ir->devnum : -1));
++ if (!ir || !ir->d)
++ return;
++
++ if (ir->usbdev) {
++ /* Only unregister once */
++ ir->usbdev = NULL;
++ unregister_from_lirc(ir);
++ }
++
++ /* This also removes the current remote from remote_list */
++ free_irctl(ir, FREE_ALL);
++}
++
++static struct usb_driver usb_remote_driver = {
++ LIRC_THIS_MODULE(.owner = THIS_MODULE)
++ .name = DRIVER_NAME,
++ .probe = usb_remote_probe,
++ .disconnect = usb_remote_disconnect,
++ .id_table = usb_remote_table
++};
++
++static int __init usb_remote_init(void)
++{
++ int i;
++
++ INIT_LIST_HEAD(&remote_list);
++
++ printk(KERN_INFO "\n" DRIVER_NAME ": " DRIVER_DESC " "
++ DRIVER_VERSION "\n");
++ printk(DRIVER_NAME ": " DRIVER_AUTHOR "\n");
++ dprintk(DRIVER_NAME ": debug mode enabled: "
++ "$Id: lirc_xbox.c,v 1.88 2011/06/05 11:11:11 jmartin Exp $\n");
++
++ repeat_jiffies = repeat*HZ/100;
++
++ i = usb_register(&usb_remote_driver);
++ if (i) {
++ printk(DRIVER_NAME ": usb register failed, result = %d\n", i);
++ return -ENODEV;
++ }
++
++ return 0;
++}
++
++static void __exit usb_remote_exit(void)
++{
++ usb_deregister(&usb_remote_driver);
++}
++
++module_init(usb_remote_init);
++module_exit(usb_remote_exit);
++
++MODULE_DESCRIPTION(DRIVER_DESC);
++MODULE_AUTHOR(DRIVER_AUTHOR);
++MODULE_LICENSE("GPL");
++MODULE_DEVICE_TABLE(usb, usb_remote_table);
++
++module_param(debug, bool, S_IRUGO | S_IWUSR);
++MODULE_PARM_DESC(debug, "Debug enabled or not (default: 0)");
++
++module_param(mask, int, S_IRUGO | S_IWUSR);
++MODULE_PARM_DESC(mask, "Set channel acceptance bit mask (default: 0xFFFF)");
++
++module_param(unique, bool, S_IRUGO | S_IWUSR);
++MODULE_PARM_DESC(unique, "Enable channel-specific codes (default: 0)");
++
++module_param(repeat, int, S_IRUGO | S_IWUSR);
++MODULE_PARM_DESC(repeat, "Repeat timeout (1/100 sec) (default: 10)");
+diff -Nur linux-4.1.3/drivers/staging/media/lirc/Makefile linux-xbian-rpi/drivers/staging/media/lirc/Makefile
+--- linux-4.1.3/drivers/staging/media/lirc/Makefile 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/staging/media/lirc/Makefile 2015-07-28 01:20:58.437184915 +0200
+@@ -6,6 +6,8 @@
+ obj-$(CONFIG_LIRC_BT829) += lirc_bt829.o
+ obj-$(CONFIG_LIRC_IMON) += lirc_imon.o
+ obj-$(CONFIG_LIRC_PARALLEL) += lirc_parallel.o
++obj-$(CONFIG_LIRC_RPI) += lirc_rpi.o
++obj-$(CONFIG_LIRC_XBOX) += lirc_xbox.o
+ obj-$(CONFIG_LIRC_SASEM) += lirc_sasem.o
+ obj-$(CONFIG_LIRC_SERIAL) += lirc_serial.o
+ obj-$(CONFIG_LIRC_SIR) += lirc_sir.o
+diff -Nur linux-4.1.3/drivers/thermal/bcm2835-thermal.c linux-xbian-rpi/drivers/thermal/bcm2835-thermal.c
+--- linux-4.1.3/drivers/thermal/bcm2835-thermal.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/thermal/bcm2835-thermal.c 2015-07-28 01:20:58.437184915 +0200
+@@ -0,0 +1,141 @@
++/*****************************************************************************
++* Copyright 2011 Broadcom Corporation. All rights reserved.
++*
++* Unless you and Broadcom execute a separate written software license
++* agreement governing use of this software, this software is licensed to you
++* under the terms of the GNU General Public License version 2, available at
++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
++*
++* Notwithstanding the above, under no circumstances may you combine this
++* software in any way with any other Broadcom software provided under a
++* license other than the GPL, without Broadcom's express prior written
++* consent.
++*****************************************************************************/
++
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/thermal.h>
++#include <soc/bcm2835/raspberrypi-firmware.h>
++
++static int bcm2835_thermal_get_property(struct thermal_zone_device *tz,
++ unsigned long *temp, u32 tag)
++{
++ struct rpi_firmware *fw = tz->devdata;
++ struct {
++ u32 id;
++ u32 val;
++ } packet;
++ int ret;
++
++ *temp = 0;
++ packet.id = 0;
++ ret = rpi_firmware_property(fw, tag, &packet, sizeof(packet));
++ if (ret) {
++ dev_err(&tz->device, "Failed to get temperature\n");
++ return ret;
++ }
++
++ *temp = packet.val;
++ dev_dbg(&tz->device, "%stemp=%lu\n",
++ tag == RPI_FIRMWARE_GET_MAX_TEMPERATURE ? "max" : "", *temp);
++
++ return 0;
++}
++
++static int bcm2835_thermal_get_temp(struct thermal_zone_device *tz,
++ unsigned long *temp)
++{
++ return bcm2835_thermal_get_property(tz, temp,
++ RPI_FIRMWARE_GET_TEMPERATURE);
++}
++
++static int bcm2835_thermal_get_max_temp(struct thermal_zone_device *tz,
++ int trip, unsigned long *temp)
++{
++ /*
++ * The maximum safe temperature of the SoC.
++ * Overclock may be disabled above this temperature.
++ */
++ return bcm2835_thermal_get_property(tz, temp,
++ RPI_FIRMWARE_GET_MAX_TEMPERATURE);
++}
++
++static int bcm2835_thermal_get_trip_type(struct thermal_zone_device *tz,
++ int trip, enum thermal_trip_type *type)
++{
++ *type = THERMAL_TRIP_HOT;
++
++ return 0;
++}
++
++static int bcm2835_thermal_get_mode(struct thermal_zone_device *tz,
++ enum thermal_device_mode *mode)
++{
++ *mode = THERMAL_DEVICE_ENABLED;
++
++ return 0;
++}
++
++static struct thermal_zone_device_ops ops = {
++ .get_temp = bcm2835_thermal_get_temp,
++ .get_trip_temp = bcm2835_thermal_get_max_temp,
++ .get_trip_type = bcm2835_thermal_get_trip_type,
++ .get_mode = bcm2835_thermal_get_mode,
++};
++
++static int bcm2835_thermal_probe(struct platform_device *pdev)
++{
++ struct device_node *fw_np;
++ struct rpi_firmware *fw;
++ struct thermal_zone_device *tz;
++
++ fw_np = of_parse_phandle(pdev->dev.of_node, "firmware", 0);
++/* Remove comment when booting without Device Tree is no longer supported
++ if (!fw_np) {
++ dev_err(&pdev->dev, "Missing firmware node\n");
++ return -ENOENT;
++ }
++*/
++ fw = rpi_firmware_get(fw_np);
++ if (!fw)
++ return -EPROBE_DEFER;
++
++ tz = thermal_zone_device_register("bcm2835_thermal", 1, 0, fw, &ops,
++ NULL, 0, 0);
++ if (IS_ERR(tz)) {
++ dev_err(&pdev->dev, "Failed to register the thermal device\n");
++ return PTR_ERR(tz);
++ }
++
++ platform_set_drvdata(pdev, tz);
++
++ return 0;
++}
++
++static int bcm2835_thermal_remove(struct platform_device *pdev)
++{
++ thermal_zone_device_unregister(platform_get_drvdata(pdev));
++
++ return 0;
++}
++
++static const struct of_device_id bcm2835_thermal_of_match_table[] = {
++ { .compatible = "brcm,bcm2835-thermal", },
++ {},
++};
++MODULE_DEVICE_TABLE(of, bcm2835_thermal_of_match_table);
++
++static struct platform_driver bcm2835_thermal_driver = {
++ .probe = bcm2835_thermal_probe,
++ .remove = bcm2835_thermal_remove,
++ .driver = {
++ .name = "bcm2835_thermal",
++ .of_match_table = bcm2835_thermal_of_match_table,
++ },
++};
++module_platform_driver(bcm2835_thermal_driver);
++
++MODULE_AUTHOR("Dorian Peake");
++MODULE_AUTHOR("Noralf Trønnes");
++MODULE_DESCRIPTION("Thermal driver for bcm2835 chip");
++MODULE_LICENSE("GPL");
+diff -Nur linux-4.1.3/drivers/thermal/Kconfig linux-xbian-rpi/drivers/thermal/Kconfig
+--- linux-4.1.3/drivers/thermal/Kconfig 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/thermal/Kconfig 2015-07-28 01:20:58.437184915 +0200
+@@ -238,6 +238,13 @@
+ enforce idle time which results in more package C-state residency. The
+ user interface is exposed via generic thermal framework.
+
++config THERMAL_BCM2835
++ depends on BCM2708_MBOX
++ tristate "BCM2835 Thermal Driver"
++ help
++ This will enable temperature monitoring for the Broadcom BCM2835
++ chip. If built as a module, it will be called 'bcm2835-thermal'.
++
+ config X86_PKG_TEMP_THERMAL
+ tristate "X86 package temperature thermal driver"
+ depends on X86_THERMAL_VECTOR
+diff -Nur linux-4.1.3/drivers/thermal/Makefile linux-xbian-rpi/drivers/thermal/Makefile
+--- linux-4.1.3/drivers/thermal/Makefile 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/thermal/Makefile 2015-07-28 01:20:58.437184915 +0200
+@@ -33,6 +33,7 @@
+ obj-$(CONFIG_IMX_THERMAL) += imx_thermal.o
+ obj-$(CONFIG_DB8500_CPUFREQ_COOLING) += db8500_cpufreq_cooling.o
+ obj-$(CONFIG_INTEL_POWERCLAMP) += intel_powerclamp.o
++obj-$(CONFIG_THERMAL_BCM2835) += bcm2835-thermal.o
+ obj-$(CONFIG_X86_PKG_TEMP_THERMAL) += x86_pkg_temp_thermal.o
+ obj-$(CONFIG_INTEL_SOC_DTS_THERMAL) += intel_soc_dts_thermal.o
+ obj-$(CONFIG_TI_SOC_THERMAL) += ti-soc-thermal/
+diff -Nur linux-4.1.3/drivers/tty/serial/8250/8250_core.c linux-xbian-rpi/drivers/tty/serial/8250/8250_core.c
+--- linux-4.1.3/drivers/tty/serial/8250/8250_core.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/tty/serial/8250/8250_core.c 2015-07-28 01:20:58.437184915 +0200
+@@ -3262,6 +3262,8 @@
+
+ if (nr_uarts > UART_NR)
+ nr_uarts = UART_NR;
++ if (!nr_uarts)
++ return;
+
+ for (i = 0; i < nr_uarts; i++) {
+ struct uart_8250_port *up = &serial8250_ports[i];
+diff -Nur linux-4.1.3/drivers/usb/core/generic.c linux-xbian-rpi/drivers/usb/core/generic.c
+--- linux-4.1.3/drivers/usb/core/generic.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/usb/core/generic.c 2015-07-28 01:20:58.437184915 +0200
+@@ -152,6 +152,7 @@
+ dev_warn(&udev->dev,
+ "no configuration chosen from %d choice%s\n",
+ num_configs, plural(num_configs));
++ dev_warn(&udev->dev, "No support over %dmA\n", udev->bus_mA);
+ }
+ return i;
+ }
+diff -Nur linux-4.1.3/drivers/usb/core/hub.c linux-xbian-rpi/drivers/usb/core/hub.c
+--- linux-4.1.3/drivers/usb/core/hub.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/usb/core/hub.c 2015-07-28 01:20:58.441170694 +0200
+@@ -4922,7 +4922,7 @@
+ if (portchange & USB_PORT_STAT_C_OVERCURRENT) {
+ u16 status = 0, unused;
+
+- dev_dbg(&port_dev->dev, "over-current change\n");
++ dev_notice(&port_dev->dev, "over-current change\n");
+ usb_clear_port_feature(hdev, port1,
+ USB_PORT_FEAT_C_OVER_CURRENT);
+ msleep(100); /* Cool down */
+diff -Nur linux-4.1.3/drivers/usb/core/message.c linux-xbian-rpi/drivers/usb/core/message.c
+--- linux-4.1.3/drivers/usb/core/message.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/usb/core/message.c 2015-07-28 01:20:58.441170694 +0200
+@@ -1872,6 +1872,85 @@
+ if (cp->string == NULL &&
+ !(dev->quirks & USB_QUIRK_CONFIG_INTF_STRINGS))
+ cp->string = usb_cache_string(dev, cp->desc.iConfiguration);
++/* Uncomment this define to enable the HS Electrical Test support */
++#define DWC_HS_ELECT_TST 1
++#ifdef DWC_HS_ELECT_TST
++ /* Here we implement the HS Electrical Test support. The
++ * tester uses a vendor ID of 0x1A0A to indicate we should
++ * run a special test sequence. The product ID tells us
++ * which sequence to run. We invoke the test sequence by
++ * sending a non-standard SetFeature command to our root
++ * hub port. Our dwc_otg_hcd_hub_control() routine will
++ * recognize the command and perform the desired test
++ * sequence.
++ */
++ if (dev->descriptor.idVendor == 0x1A0A) {
++ /* HSOTG Electrical Test */
++ dev_warn(&dev->dev, "VID from HSOTG Electrical Test Fixture\n");
++
++ if (dev->bus && dev->bus->root_hub) {
++ struct usb_device *hdev = dev->bus->root_hub;
++ dev_warn(&dev->dev, "Got PID 0x%x\n", dev->descriptor.idProduct);
++
++ switch (dev->descriptor.idProduct) {
++ case 0x0101: /* TEST_SE0_NAK */
++ dev_warn(&dev->dev, "TEST_SE0_NAK\n");
++ usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
++ USB_REQ_SET_FEATURE, USB_RT_PORT,
++ USB_PORT_FEAT_TEST, 0x300, NULL, 0, HZ);
++ break;
++
++ case 0x0102: /* TEST_J */
++ dev_warn(&dev->dev, "TEST_J\n");
++ usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
++ USB_REQ_SET_FEATURE, USB_RT_PORT,
++ USB_PORT_FEAT_TEST, 0x100, NULL, 0, HZ);
++ break;
++
++ case 0x0103: /* TEST_K */
++ dev_warn(&dev->dev, "TEST_K\n");
++ usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
++ USB_REQ_SET_FEATURE, USB_RT_PORT,
++ USB_PORT_FEAT_TEST, 0x200, NULL, 0, HZ);
++ break;
++
++ case 0x0104: /* TEST_PACKET */
++ dev_warn(&dev->dev, "TEST_PACKET\n");
++ usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
++ USB_REQ_SET_FEATURE, USB_RT_PORT,
++ USB_PORT_FEAT_TEST, 0x400, NULL, 0, HZ);
++ break;
++
++ case 0x0105: /* TEST_FORCE_ENABLE */
++ dev_warn(&dev->dev, "TEST_FORCE_ENABLE\n");
++ usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
++ USB_REQ_SET_FEATURE, USB_RT_PORT,
++ USB_PORT_FEAT_TEST, 0x500, NULL, 0, HZ);
++ break;
++
++ case 0x0106: /* HS_HOST_PORT_SUSPEND_RESUME */
++ dev_warn(&dev->dev, "HS_HOST_PORT_SUSPEND_RESUME\n");
++ usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
++ USB_REQ_SET_FEATURE, USB_RT_PORT,
++ USB_PORT_FEAT_TEST, 0x600, NULL, 0, 40 * HZ);
++ break;
++
++ case 0x0107: /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */
++ dev_warn(&dev->dev, "SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup\n");
++ usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
++ USB_REQ_SET_FEATURE, USB_RT_PORT,
++ USB_PORT_FEAT_TEST, 0x700, NULL, 0, 40 * HZ);
++ break;
++
++ case 0x0108: /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */
++ dev_warn(&dev->dev, "SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute\n");
++ usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
++ USB_REQ_SET_FEATURE, USB_RT_PORT,
++ USB_PORT_FEAT_TEST, 0x800, NULL, 0, 40 * HZ);
++ }
++ }
++ }
++#endif /* DWC_HS_ELECT_TST */
+
+ /* Now that the interfaces are installed, re-enable LPM. */
+ usb_unlocked_enable_lpm(dev);
+diff -Nur linux-4.1.3/drivers/usb/core/otg_whitelist.h linux-xbian-rpi/drivers/usb/core/otg_whitelist.h
+--- linux-4.1.3/drivers/usb/core/otg_whitelist.h 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/usb/core/otg_whitelist.h 2015-07-28 01:20:58.441170694 +0200
+@@ -19,33 +19,82 @@
+ static struct usb_device_id whitelist_table [] = {
+
+ /* hubs are optional in OTG, but very handy ... */
++#define CERT_WITHOUT_HUBS
++#if defined(CERT_WITHOUT_HUBS)
++{ USB_DEVICE( 0x0000, 0x0000 ), }, /* Root HUB Only*/
++#else
+ { USB_DEVICE_INFO(USB_CLASS_HUB, 0, 0), },
+ { USB_DEVICE_INFO(USB_CLASS_HUB, 0, 1), },
++{ USB_DEVICE_INFO(USB_CLASS_HUB, 0, 2), },
++#endif
+
+ #ifdef CONFIG_USB_PRINTER /* ignoring nonstatic linkage! */
+ /* FIXME actually, printers are NOT supposed to use device classes;
+ * they're supposed to use interface classes...
+ */
+-{ USB_DEVICE_INFO(7, 1, 1) },
+-{ USB_DEVICE_INFO(7, 1, 2) },
+-{ USB_DEVICE_INFO(7, 1, 3) },
++//{ USB_DEVICE_INFO(7, 1, 1) },
++//{ USB_DEVICE_INFO(7, 1, 2) },
++//{ USB_DEVICE_INFO(7, 1, 3) },
+ #endif
+
+ #ifdef CONFIG_USB_NET_CDCETHER
+ /* Linux-USB CDC Ethernet gadget */
+-{ USB_DEVICE(0x0525, 0xa4a1), },
++//{ USB_DEVICE(0x0525, 0xa4a1), },
+ /* Linux-USB CDC Ethernet + RNDIS gadget */
+-{ USB_DEVICE(0x0525, 0xa4a2), },
++//{ USB_DEVICE(0x0525, 0xa4a2), },
+ #endif
+
+ #if defined(CONFIG_USB_TEST) || defined(CONFIG_USB_TEST_MODULE)
+ /* gadget zero, for testing */
+-{ USB_DEVICE(0x0525, 0xa4a0), },
++//{ USB_DEVICE(0x0525, 0xa4a0), },
+ #endif
+
++/* OPT Tester */
++{ USB_DEVICE( 0x1a0a, 0x0101 ), }, /* TEST_SE0_NAK */
++{ USB_DEVICE( 0x1a0a, 0x0102 ), }, /* Test_J */
++{ USB_DEVICE( 0x1a0a, 0x0103 ), }, /* Test_K */
++{ USB_DEVICE( 0x1a0a, 0x0104 ), }, /* Test_PACKET */
++{ USB_DEVICE( 0x1a0a, 0x0105 ), }, /* Test_FORCE_ENABLE */
++{ USB_DEVICE( 0x1a0a, 0x0106 ), }, /* HS_PORT_SUSPEND_RESUME */
++{ USB_DEVICE( 0x1a0a, 0x0107 ), }, /* SINGLE_STEP_GET_DESCRIPTOR setup */
++{ USB_DEVICE( 0x1a0a, 0x0108 ), }, /* SINGLE_STEP_GET_DESCRIPTOR execute */
++
++/* Sony cameras */
++{ USB_DEVICE_VER(0x054c,0x0010,0x0410, 0x0500), },
++
++/* Memory Devices */
++//{ USB_DEVICE( 0x0781, 0x5150 ), }, /* SanDisk */
++//{ USB_DEVICE( 0x05DC, 0x0080 ), }, /* Lexar */
++//{ USB_DEVICE( 0x4146, 0x9281 ), }, /* IOMEGA */
++//{ USB_DEVICE( 0x067b, 0x2507 ), }, /* Hammer 20GB External HD */
++{ USB_DEVICE( 0x0EA0, 0x2168 ), }, /* Ours Technology Inc. (BUFFALO ClipDrive)*/
++//{ USB_DEVICE( 0x0457, 0x0150 ), }, /* Silicon Integrated Systems Corp. */
++
++/* HP Printers */
++//{ USB_DEVICE( 0x03F0, 0x1102 ), }, /* HP Photosmart 245 */
++//{ USB_DEVICE( 0x03F0, 0x1302 ), }, /* HP Photosmart 370 Series */
++
++/* Speakers */
++//{ USB_DEVICE( 0x0499, 0x3002 ), }, /* YAMAHA YST-MS35D USB Speakers */
++//{ USB_DEVICE( 0x0672, 0x1041 ), }, /* Labtec USB Headset */
++
+ { } /* Terminating entry */
+ };
+
++static inline void report_errors(struct usb_device *dev)
++{
++ /* OTG MESSAGE: report errors here, customize to match your product */
++ dev_info(&dev->dev, "device Vendor:%04x Product:%04x is not supported\n",
++ le16_to_cpu(dev->descriptor.idVendor),
++ le16_to_cpu(dev->descriptor.idProduct));
++ if (USB_CLASS_HUB == dev->descriptor.bDeviceClass){
++ dev_printk(KERN_CRIT, &dev->dev, "Unsupported Hub Topology\n");
++ } else {
++ dev_printk(KERN_CRIT, &dev->dev, "Attached Device is not Supported\n");
++ }
++}
++
++
+ static int is_targeted(struct usb_device *dev)
+ {
+ struct usb_device_id *id = whitelist_table;
+@@ -95,16 +144,57 @@
+ continue;
+
+ return 1;
+- }
++ /* NOTE: can't use usb_match_id() since interface caches
++ * aren't set up yet. this is cut/paste from that code.
++ */
++ for (id = whitelist_table; id->match_flags; id++) {
++#ifdef DEBUG
++ dev_dbg(&dev->dev,
++ "ID: V:%04x P:%04x DC:%04x SC:%04x PR:%04x \n",
++ id->idVendor,
++ id->idProduct,
++ id->bDeviceClass,
++ id->bDeviceSubClass,
++ id->bDeviceProtocol);
++#endif
+
+- /* add other match criteria here ... */
++ if ((id->match_flags & USB_DEVICE_ID_MATCH_VENDOR) &&
++ id->idVendor != le16_to_cpu(dev->descriptor.idVendor))
++ continue;
++
++ if ((id->match_flags & USB_DEVICE_ID_MATCH_PRODUCT) &&
++ id->idProduct != le16_to_cpu(dev->descriptor.idProduct))
++ continue;
++
++ /* No need to test id->bcdDevice_lo != 0, since 0 is never
++ greater than any unsigned number. */
++ if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_LO) &&
++ (id->bcdDevice_lo > le16_to_cpu(dev->descriptor.bcdDevice)))
++ continue;
++
++ if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_HI) &&
++ (id->bcdDevice_hi < le16_to_cpu(dev->descriptor.bcdDevice)))
++ continue;
++
++ if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_CLASS) &&
++ (id->bDeviceClass != dev->descriptor.bDeviceClass))
++ continue;
++
++ if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_SUBCLASS) &&
++ (id->bDeviceSubClass != dev->descriptor.bDeviceSubClass))
++ continue;
++
++ if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_PROTOCOL) &&
++ (id->bDeviceProtocol != dev->descriptor.bDeviceProtocol))
++ continue;
+
++ return 1;
++ }
++ }
+
+- /* OTG MESSAGE: report errors here, customize to match your product */
+- dev_err(&dev->dev, "device v%04x p%04x is not supported\n",
+- le16_to_cpu(dev->descriptor.idVendor),
+- le16_to_cpu(dev->descriptor.idProduct));
++ /* add other match criteria here ... */
+
++ report_errors(dev);
+ return 0;
+ }
+
+diff -Nur linux-4.1.3/drivers/usb/gadget/file_storage.c linux-xbian-rpi/drivers/usb/gadget/file_storage.c
+--- linux-4.1.3/drivers/usb/gadget/file_storage.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/usb/gadget/file_storage.c 2015-07-28 01:20:58.441170694 +0200
+@@ -0,0 +1,3676 @@
++/*
++ * file_storage.c -- File-backed USB Storage Gadget, for USB development
++ *
++ * Copyright (C) 2003-2008 Alan Stern
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ * 1. Redistributions of source code must retain the above copyright
++ * notice, this list of conditions, and the following disclaimer,
++ * without modification.
++ * 2. Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * 3. The names of the above-listed copyright holders may not be used
++ * to endorse or promote products derived from this software without
++ * specific prior written permission.
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++
++/*
++ * The File-backed Storage Gadget acts as a USB Mass Storage device,
++ * appearing to the host as a disk drive or as a CD-ROM drive. In addition
++ * to providing an example of a genuinely useful gadget driver for a USB
++ * device, it also illustrates a technique of double-buffering for increased
++ * throughput. Last but not least, it gives an easy way to probe the
++ * behavior of the Mass Storage drivers in a USB host.
++ *
++ * Backing storage is provided by a regular file or a block device, specified
++ * by the "file" module parameter. Access can be limited to read-only by
++ * setting the optional "ro" module parameter. (For CD-ROM emulation,
++ * access is always read-only.) The gadget will indicate that it has
++ * removable media if the optional "removable" module parameter is set.
++ *
++ * The gadget supports the Control-Bulk (CB), Control-Bulk-Interrupt (CBI),
++ * and Bulk-Only (also known as Bulk-Bulk-Bulk or BBB) transports, selected
++ * by the optional "transport" module parameter. It also supports the
++ * following protocols: RBC (0x01), ATAPI or SFF-8020i (0x02), QIC-157 (0c03),
++ * UFI (0x04), SFF-8070i (0x05), and transparent SCSI (0x06), selected by
++ * the optional "protocol" module parameter. In addition, the default
++ * Vendor ID, Product ID, release number and serial number can be overridden.
++ *
++ * There is support for multiple logical units (LUNs), each of which has
++ * its own backing file. The number of LUNs can be set using the optional
++ * "luns" module parameter (anywhere from 1 to 8), and the corresponding
++ * files are specified using comma-separated lists for "file" and "ro".
++ * The default number of LUNs is taken from the number of "file" elements;
++ * it is 1 if "file" is not given. If "removable" is not set then a backing
++ * file must be specified for each LUN. If it is set, then an unspecified
++ * or empty backing filename means the LUN's medium is not loaded. Ideally
++ * each LUN would be settable independently as a disk drive or a CD-ROM
++ * drive, but currently all LUNs have to be the same type. The CD-ROM
++ * emulation includes a single data track and no audio tracks; hence there
++ * need be only one backing file per LUN.
++ *
++ * Requirements are modest; only a bulk-in and a bulk-out endpoint are
++ * needed (an interrupt-out endpoint is also needed for CBI). The memory
++ * requirement amounts to two 16K buffers, size configurable by a parameter.
++ * Support is included for both full-speed and high-speed operation.
++ *
++ * Note that the driver is slightly non-portable in that it assumes a
++ * single memory/DMA buffer will be useable for bulk-in, bulk-out, and
++ * interrupt-in endpoints. With most device controllers this isn't an
++ * issue, but there may be some with hardware restrictions that prevent
++ * a buffer from being used by more than one endpoint.
++ *
++ * Module options:
++ *
++ * file=filename[,filename...]
++ * Required if "removable" is not set, names of
++ * the files or block devices used for
++ * backing storage
++ * serial=HHHH... Required serial number (string of hex chars)
++ * ro=b[,b...] Default false, booleans for read-only access
++ * removable Default false, boolean for removable media
++ * luns=N Default N = number of filenames, number of
++ * LUNs to support
++ * nofua=b[,b...] Default false, booleans for ignore FUA flag
++ * in SCSI WRITE(10,12) commands
++ * stall Default determined according to the type of
++ * USB device controller (usually true),
++ * boolean to permit the driver to halt
++ * bulk endpoints
++ * cdrom Default false, boolean for whether to emulate
++ * a CD-ROM drive
++ * transport=XXX Default BBB, transport name (CB, CBI, or BBB)
++ * protocol=YYY Default SCSI, protocol name (RBC, 8020 or
++ * ATAPI, QIC, UFI, 8070, or SCSI;
++ * also 1 - 6)
++ * vendor=0xVVVV Default 0x0525 (NetChip), USB Vendor ID
++ * product=0xPPPP Default 0xa4a5 (FSG), USB Product ID
++ * release=0xRRRR Override the USB release number (bcdDevice)
++ * buflen=N Default N=16384, buffer size used (will be
++ * rounded down to a multiple of
++ * PAGE_CACHE_SIZE)
++ *
++ * If CONFIG_USB_FILE_STORAGE_TEST is not set, only the "file", "serial", "ro",
++ * "removable", "luns", "nofua", "stall", and "cdrom" options are available;
++ * default values are used for everything else.
++ *
++ * The pathnames of the backing files and the ro settings are available in
++ * the attribute files "file", "nofua", and "ro" in the lun<n> subdirectory of
++ * the gadget's sysfs directory. If the "removable" option is set, writing to
++ * these files will simulate ejecting/loading the medium (writing an empty
++ * line means eject) and adjusting a write-enable tab. Changes to the ro
++ * setting are not allowed when the medium is loaded or if CD-ROM emulation
++ * is being used.
++ *
++ * This gadget driver is heavily based on "Gadget Zero" by David Brownell.
++ * The driver's SCSI command interface was based on the "Information
++ * technology - Small Computer System Interface - 2" document from
++ * X3T9.2 Project 375D, Revision 10L, 7-SEP-93, available at
++ * <http://www.t10.org/ftp/t10/drafts/s2/s2-r10l.pdf>. The single exception
++ * is opcode 0x23 (READ FORMAT CAPACITIES), which was based on the
++ * "Universal Serial Bus Mass Storage Class UFI Command Specification"
++ * document, Revision 1.0, December 14, 1998, available at
++ * <http://www.usb.org/developers/devclass_docs/usbmass-ufi10.pdf>.
++ */
++
++
++/*
++ * Driver Design
++ *
++ * The FSG driver is fairly straightforward. There is a main kernel
++ * thread that handles most of the work. Interrupt routines field
++ * callbacks from the controller driver: bulk- and interrupt-request
++ * completion notifications, endpoint-0 events, and disconnect events.
++ * Completion events are passed to the main thread by wakeup calls. Many
++ * ep0 requests are handled at interrupt time, but SetInterface,
++ * SetConfiguration, and device reset requests are forwarded to the
++ * thread in the form of "exceptions" using SIGUSR1 signals (since they
++ * should interrupt any ongoing file I/O operations).
++ *
++ * The thread's main routine implements the standard command/data/status
++ * parts of a SCSI interaction. It and its subroutines are full of tests
++ * for pending signals/exceptions -- all this polling is necessary since
++ * the kernel has no setjmp/longjmp equivalents. (Maybe this is an
++ * indication that the driver really wants to be running in userspace.)
++ * An important point is that so long as the thread is alive it keeps an
++ * open reference to the backing file. This will prevent unmounting
++ * the backing file's underlying filesystem and could cause problems
++ * during system shutdown, for example. To prevent such problems, the
++ * thread catches INT, TERM, and KILL signals and converts them into
++ * an EXIT exception.
++ *
++ * In normal operation the main thread is started during the gadget's
++ * fsg_bind() callback and stopped during fsg_unbind(). But it can also
++ * exit when it receives a signal, and there's no point leaving the
++ * gadget running when the thread is dead. So just before the thread
++ * exits, it deregisters the gadget driver. This makes things a little
++ * tricky: The driver is deregistered at two places, and the exiting
++ * thread can indirectly call fsg_unbind() which in turn can tell the
++ * thread to exit. The first problem is resolved through the use of the
++ * REGISTERED atomic bitflag; the driver will only be deregistered once.
++ * The second problem is resolved by having fsg_unbind() check
++ * fsg->state; it won't try to stop the thread if the state is already
++ * FSG_STATE_TERMINATED.
++ *
++ * To provide maximum throughput, the driver uses a circular pipeline of
++ * buffer heads (struct fsg_buffhd). In principle the pipeline can be
++ * arbitrarily long; in practice the benefits don't justify having more
++ * than 2 stages (i.e., double buffering). But it helps to think of the
++ * pipeline as being a long one. Each buffer head contains a bulk-in and
++ * a bulk-out request pointer (since the buffer can be used for both
++ * output and input -- directions always are given from the host's
++ * point of view) as well as a pointer to the buffer and various state
++ * variables.
++ *
++ * Use of the pipeline follows a simple protocol. There is a variable
++ * (fsg->next_buffhd_to_fill) that points to the next buffer head to use.
++ * At any time that buffer head may still be in use from an earlier
++ * request, so each buffer head has a state variable indicating whether
++ * it is EMPTY, FULL, or BUSY. Typical use involves waiting for the
++ * buffer head to be EMPTY, filling the buffer either by file I/O or by
++ * USB I/O (during which the buffer head is BUSY), and marking the buffer
++ * head FULL when the I/O is complete. Then the buffer will be emptied
++ * (again possibly by USB I/O, during which it is marked BUSY) and
++ * finally marked EMPTY again (possibly by a completion routine).
++ *
++ * A module parameter tells the driver to avoid stalling the bulk
++ * endpoints wherever the transport specification allows. This is
++ * necessary for some UDCs like the SuperH, which cannot reliably clear a
++ * halt on a bulk endpoint. However, under certain circumstances the
++ * Bulk-only specification requires a stall. In such cases the driver
++ * will halt the endpoint and set a flag indicating that it should clear
++ * the halt in software during the next device reset. Hopefully this
++ * will permit everything to work correctly. Furthermore, although the
++ * specification allows the bulk-out endpoint to halt when the host sends
++ * too much data, implementing this would cause an unavoidable race.
++ * The driver will always use the "no-stall" approach for OUT transfers.
++ *
++ * One subtle point concerns sending status-stage responses for ep0
++ * requests. Some of these requests, such as device reset, can involve
++ * interrupting an ongoing file I/O operation, which might take an
++ * arbitrarily long time. During that delay the host might give up on
++ * the original ep0 request and issue a new one. When that happens the
++ * driver should not notify the host about completion of the original
++ * request, as the host will no longer be waiting for it. So the driver
++ * assigns to each ep0 request a unique tag, and it keeps track of the
++ * tag value of the request associated with a long-running exception
++ * (device-reset, interface-change, or configuration-change). When the
++ * exception handler is finished, the status-stage response is submitted
++ * only if the current ep0 request tag is equal to the exception request
++ * tag. Thus only the most recently received ep0 request will get a
++ * status-stage response.
++ *
++ * Warning: This driver source file is too long. It ought to be split up
++ * into a header file plus about 3 separate .c files, to handle the details
++ * of the Gadget, USB Mass Storage, and SCSI protocols.
++ */
++
++
++/* #define VERBOSE_DEBUG */
++/* #define DUMP_MSGS */
++
++
++#include <linux/blkdev.h>
++#include <linux/completion.h>
++#include <linux/dcache.h>
++#include <linux/delay.h>
++#include <linux/device.h>
++#include <linux/fcntl.h>
++#include <linux/file.h>
++#include <linux/fs.h>
++#include <linux/kref.h>
++#include <linux/kthread.h>
++#include <linux/limits.h>
++#include <linux/module.h>
++#include <linux/rwsem.h>
++#include <linux/slab.h>
++#include <linux/spinlock.h>
++#include <linux/string.h>
++#include <linux/freezer.h>
++#include <linux/utsname.h>
++
++#include <linux/usb/ch9.h>
++#include <linux/usb/gadget.h>
++
++#include "gadget_chips.h"
++
++
++
++/*
++ * Kbuild is not very cooperative with respect to linking separately
++ * compiled library objects into one module. So for now we won't use
++ * separate compilation ... ensuring init/exit sections work to shrink
++ * the runtime footprint, and giving us at least some parts of what
++ * a "gcc --combine ... part1.c part2.c part3.c ... " build would.
++ */
++#include "usbstring.c"
++#include "config.c"
++#include "epautoconf.c"
++
++/*-------------------------------------------------------------------------*/
++
++#define DRIVER_DESC "File-backed Storage Gadget"
++#define DRIVER_NAME "g_file_storage"
++#define DRIVER_VERSION "1 September 2010"
++
++static char fsg_string_manufacturer[64];
++static const char fsg_string_product[] = DRIVER_DESC;
++static const char fsg_string_config[] = "Self-powered";
++static const char fsg_string_interface[] = "Mass Storage";
++
++
++#include "storage_common.c"
++
++
++MODULE_DESCRIPTION(DRIVER_DESC);
++MODULE_AUTHOR("Alan Stern");
++MODULE_LICENSE("Dual BSD/GPL");
++
++/*
++ * This driver assumes self-powered hardware and has no way for users to
++ * trigger remote wakeup. It uses autoconfiguration to select endpoints
++ * and endpoint addresses.
++ */
++
++
++/*-------------------------------------------------------------------------*/
++
++
++/* Encapsulate the module parameter settings */
++
++static struct {
++ char *file[FSG_MAX_LUNS];
++ char *serial;
++ bool ro[FSG_MAX_LUNS];
++ bool nofua[FSG_MAX_LUNS];
++ unsigned int num_filenames;
++ unsigned int num_ros;
++ unsigned int num_nofuas;
++ unsigned int nluns;
++
++ bool removable;
++ bool can_stall;
++ bool cdrom;
++
++ char *transport_parm;
++ char *protocol_parm;
++ unsigned short vendor;
++ unsigned short product;
++ unsigned short release;
++ unsigned int buflen;
++
++ int transport_type;
++ char *transport_name;
++ int protocol_type;
++ char *protocol_name;
++
++} mod_data = { // Default values
++ .transport_parm = "BBB",
++ .protocol_parm = "SCSI",
++ .removable = 0,
++ .can_stall = 1,
++ .cdrom = 0,
++ .vendor = FSG_VENDOR_ID,
++ .product = FSG_PRODUCT_ID,
++ .release = 0xffff, // Use controller chip type
++ .buflen = 16384,
++ };
++
++
++module_param_array_named(file, mod_data.file, charp, &mod_data.num_filenames,
++ S_IRUGO);
++MODULE_PARM_DESC(file, "names of backing files or devices");
++
++module_param_named(serial, mod_data.serial, charp, S_IRUGO);
++MODULE_PARM_DESC(serial, "USB serial number");
++
++module_param_array_named(ro, mod_data.ro, bool, &mod_data.num_ros, S_IRUGO);
++MODULE_PARM_DESC(ro, "true to force read-only");
++
++module_param_array_named(nofua, mod_data.nofua, bool, &mod_data.num_nofuas,
++ S_IRUGO);
++MODULE_PARM_DESC(nofua, "true to ignore SCSI WRITE(10,12) FUA bit");
++
++module_param_named(luns, mod_data.nluns, uint, S_IRUGO);
++MODULE_PARM_DESC(luns, "number of LUNs");
++
++module_param_named(removable, mod_data.removable, bool, S_IRUGO);
++MODULE_PARM_DESC(removable, "true to simulate removable media");
++
++module_param_named(stall, mod_data.can_stall, bool, S_IRUGO);
++MODULE_PARM_DESC(stall, "false to prevent bulk stalls");
++
++module_param_named(cdrom, mod_data.cdrom, bool, S_IRUGO);
++MODULE_PARM_DESC(cdrom, "true to emulate cdrom instead of disk");
++
++/* In the non-TEST version, only the module parameters listed above
++ * are available. */
++#ifdef CONFIG_USB_FILE_STORAGE_TEST
++
++module_param_named(transport, mod_data.transport_parm, charp, S_IRUGO);
++MODULE_PARM_DESC(transport, "type of transport (BBB, CBI, or CB)");
++
++module_param_named(protocol, mod_data.protocol_parm, charp, S_IRUGO);
++MODULE_PARM_DESC(protocol, "type of protocol (RBC, 8020, QIC, UFI, "
++ "8070, or SCSI)");
++
++module_param_named(vendor, mod_data.vendor, ushort, S_IRUGO);
++MODULE_PARM_DESC(vendor, "USB Vendor ID");
++
++module_param_named(product, mod_data.product, ushort, S_IRUGO);
++MODULE_PARM_DESC(product, "USB Product ID");
++
++module_param_named(release, mod_data.release, ushort, S_IRUGO);
++MODULE_PARM_DESC(release, "USB release number");
++
++module_param_named(buflen, mod_data.buflen, uint, S_IRUGO);
++MODULE_PARM_DESC(buflen, "I/O buffer size");
++
++#endif /* CONFIG_USB_FILE_STORAGE_TEST */
++
++
++/*
++ * These definitions will permit the compiler to avoid generating code for
++ * parts of the driver that aren't used in the non-TEST version. Even gcc
++ * can recognize when a test of a constant expression yields a dead code
++ * path.
++ */
++
++#ifdef CONFIG_USB_FILE_STORAGE_TEST
++
++#define transport_is_bbb() (mod_data.transport_type == USB_PR_BULK)
++#define transport_is_cbi() (mod_data.transport_type == USB_PR_CBI)
++#define protocol_is_scsi() (mod_data.protocol_type == USB_SC_SCSI)
++
++#else
++
++#define transport_is_bbb() 1
++#define transport_is_cbi() 0
++#define protocol_is_scsi() 1
++
++#endif /* CONFIG_USB_FILE_STORAGE_TEST */
++
++
++/*-------------------------------------------------------------------------*/
++
++
++struct fsg_dev {
++ /* lock protects: state, all the req_busy's, and cbbuf_cmnd */
++ spinlock_t lock;
++ struct usb_gadget *gadget;
++
++ /* filesem protects: backing files in use */
++ struct rw_semaphore filesem;
++
++ /* reference counting: wait until all LUNs are released */
++ struct kref ref;
++
++ struct usb_ep *ep0; // Handy copy of gadget->ep0
++ struct usb_request *ep0req; // For control responses
++ unsigned int ep0_req_tag;
++ const char *ep0req_name;
++
++ struct usb_request *intreq; // For interrupt responses
++ int intreq_busy;
++ struct fsg_buffhd *intr_buffhd;
++
++ unsigned int bulk_out_maxpacket;
++ enum fsg_state state; // For exception handling
++ unsigned int exception_req_tag;
++
++ u8 config, new_config;
++
++ unsigned int running : 1;
++ unsigned int bulk_in_enabled : 1;
++ unsigned int bulk_out_enabled : 1;
++ unsigned int intr_in_enabled : 1;
++ unsigned int phase_error : 1;
++ unsigned int short_packet_received : 1;
++ unsigned int bad_lun_okay : 1;
++
++ unsigned long atomic_bitflags;
++#define REGISTERED 0
++#define IGNORE_BULK_OUT 1
++#define SUSPENDED 2
++
++ struct usb_ep *bulk_in;
++ struct usb_ep *bulk_out;
++ struct usb_ep *intr_in;
++
++ struct fsg_buffhd *next_buffhd_to_fill;
++ struct fsg_buffhd *next_buffhd_to_drain;
++
++ int thread_wakeup_needed;
++ struct completion thread_notifier;
++ struct task_struct *thread_task;
++
++ int cmnd_size;
++ u8 cmnd[MAX_COMMAND_SIZE];
++ enum data_direction data_dir;
++ u32 data_size;
++ u32 data_size_from_cmnd;
++ u32 tag;
++ unsigned int lun;
++ u32 residue;
++ u32 usb_amount_left;
++
++ /* The CB protocol offers no way for a host to know when a command
++ * has completed. As a result the next command may arrive early,
++ * and we will still have to handle it. For that reason we need
++ * a buffer to store new commands when using CB (or CBI, which
++ * does not oblige a host to wait for command completion either). */
++ int cbbuf_cmnd_size;
++ u8 cbbuf_cmnd[MAX_COMMAND_SIZE];
++
++ unsigned int nluns;
++ struct fsg_lun *luns;
++ struct fsg_lun *curlun;
++ /* Must be the last entry */
++ struct fsg_buffhd buffhds[];
++};
++
++typedef void (*fsg_routine_t)(struct fsg_dev *);
++
++static int exception_in_progress(struct fsg_dev *fsg)
++{
++ return (fsg->state > FSG_STATE_IDLE);
++}
++
++/* Make bulk-out requests be divisible by the maxpacket size */
++static void set_bulk_out_req_length(struct fsg_dev *fsg,
++ struct fsg_buffhd *bh, unsigned int length)
++{
++ unsigned int rem;
++
++ bh->bulk_out_intended_length = length;
++ rem = length % fsg->bulk_out_maxpacket;
++ if (rem > 0)
++ length += fsg->bulk_out_maxpacket - rem;
++ bh->outreq->length = length;
++}
++
++static struct fsg_dev *the_fsg;
++static struct usb_gadget_driver fsg_driver;
++
++
++/*-------------------------------------------------------------------------*/
++
++static int fsg_set_halt(struct fsg_dev *fsg, struct usb_ep *ep)
++{
++ const char *name;
++
++ if (ep == fsg->bulk_in)
++ name = "bulk-in";
++ else if (ep == fsg->bulk_out)
++ name = "bulk-out";
++ else
++ name = ep->name;
++ DBG(fsg, "%s set halt\n", name);
++ return usb_ep_set_halt(ep);
++}
++
++
++/*-------------------------------------------------------------------------*/
++
++/*
++ * DESCRIPTORS ... most are static, but strings and (full) configuration
++ * descriptors are built on demand. Also the (static) config and interface
++ * descriptors are adjusted during fsg_bind().
++ */
++
++/* There is only one configuration. */
++#define CONFIG_VALUE 1
++
++static struct usb_device_descriptor
++device_desc = {
++ .bLength = sizeof device_desc,
++ .bDescriptorType = USB_DT_DEVICE,
++
++ .bcdUSB = cpu_to_le16(0x0200),
++ .bDeviceClass = USB_CLASS_PER_INTERFACE,
++
++ /* The next three values can be overridden by module parameters */
++ .idVendor = cpu_to_le16(FSG_VENDOR_ID),
++ .idProduct = cpu_to_le16(FSG_PRODUCT_ID),
++ .bcdDevice = cpu_to_le16(0xffff),
++
++ .iManufacturer = FSG_STRING_MANUFACTURER,
++ .iProduct = FSG_STRING_PRODUCT,
++ .iSerialNumber = FSG_STRING_SERIAL,
++ .bNumConfigurations = 1,
++};
++
++static struct usb_config_descriptor
++config_desc = {
++ .bLength = sizeof config_desc,
++ .bDescriptorType = USB_DT_CONFIG,
++
++ /* wTotalLength computed by usb_gadget_config_buf() */
++ .bNumInterfaces = 1,
++ .bConfigurationValue = CONFIG_VALUE,
++ .iConfiguration = FSG_STRING_CONFIG,
++ .bmAttributes = USB_CONFIG_ATT_ONE | USB_CONFIG_ATT_SELFPOWER,
++ .bMaxPower = CONFIG_USB_GADGET_VBUS_DRAW / 2,
++};
++
++
++static struct usb_qualifier_descriptor
++dev_qualifier = {
++ .bLength = sizeof dev_qualifier,
++ .bDescriptorType = USB_DT_DEVICE_QUALIFIER,
++
++ .bcdUSB = cpu_to_le16(0x0200),
++ .bDeviceClass = USB_CLASS_PER_INTERFACE,
++
++ .bNumConfigurations = 1,
++};
++
++static int populate_bos(struct fsg_dev *fsg, u8 *buf)
++{
++ memcpy(buf, &fsg_bos_desc, USB_DT_BOS_SIZE);
++ buf += USB_DT_BOS_SIZE;
++
++ memcpy(buf, &fsg_ext_cap_desc, USB_DT_USB_EXT_CAP_SIZE);
++ buf += USB_DT_USB_EXT_CAP_SIZE;
++
++ memcpy(buf, &fsg_ss_cap_desc, USB_DT_USB_SS_CAP_SIZE);
++
++ return USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE
++ + USB_DT_USB_EXT_CAP_SIZE;
++}
++
++/*
++ * Config descriptors must agree with the code that sets configurations
++ * and with code managing interfaces and their altsettings. They must
++ * also handle different speeds and other-speed requests.
++ */
++static int populate_config_buf(struct usb_gadget *gadget,
++ u8 *buf, u8 type, unsigned index)
++{
++ enum usb_device_speed speed = gadget->speed;
++ int len;
++ const struct usb_descriptor_header **function;
++
++ if (index > 0)
++ return -EINVAL;
++
++ if (gadget_is_dualspeed(gadget) && type == USB_DT_OTHER_SPEED_CONFIG)
++ speed = (USB_SPEED_FULL + USB_SPEED_HIGH) - speed;
++ function = gadget_is_dualspeed(gadget) && speed == USB_SPEED_HIGH
++ ? (const struct usb_descriptor_header **)fsg_hs_function
++ : (const struct usb_descriptor_header **)fsg_fs_function;
++
++ /* for now, don't advertise srp-only devices */
++ if (!gadget_is_otg(gadget))
++ function++;
++
++ len = usb_gadget_config_buf(&config_desc, buf, EP0_BUFSIZE, function);
++ ((struct usb_config_descriptor *) buf)->bDescriptorType = type;
++ return len;
++}
++
++
++/*-------------------------------------------------------------------------*/
++
++/* These routines may be called in process context or in_irq */
++
++/* Caller must hold fsg->lock */
++static void wakeup_thread(struct fsg_dev *fsg)
++{
++ /* Tell the main thread that something has happened */
++ fsg->thread_wakeup_needed = 1;
++ if (fsg->thread_task)
++ wake_up_process(fsg->thread_task);
++}
++
++
++static void raise_exception(struct fsg_dev *fsg, enum fsg_state new_state)
++{
++ unsigned long flags;
++
++ /* Do nothing if a higher-priority exception is already in progress.
++ * If a lower-or-equal priority exception is in progress, preempt it
++ * and notify the main thread by sending it a signal. */
++ spin_lock_irqsave(&fsg->lock, flags);
++ if (fsg->state <= new_state) {
++ fsg->exception_req_tag = fsg->ep0_req_tag;
++ fsg->state = new_state;
++ if (fsg->thread_task)
++ send_sig_info(SIGUSR1, SEND_SIG_FORCED,
++ fsg->thread_task);
++ }
++ spin_unlock_irqrestore(&fsg->lock, flags);
++}
++
++
++/*-------------------------------------------------------------------------*/
++
++/* The disconnect callback and ep0 routines. These always run in_irq,
++ * except that ep0_queue() is called in the main thread to acknowledge
++ * completion of various requests: set config, set interface, and
++ * Bulk-only device reset. */
++
++static void fsg_disconnect(struct usb_gadget *gadget)
++{
++ struct fsg_dev *fsg = get_gadget_data(gadget);
++
++ DBG(fsg, "disconnect or port reset\n");
++ raise_exception(fsg, FSG_STATE_DISCONNECT);
++}
++
++
++static int ep0_queue(struct fsg_dev *fsg)
++{
++ int rc;
++
++ rc = usb_ep_queue(fsg->ep0, fsg->ep0req, GFP_ATOMIC);
++ if (rc != 0 && rc != -ESHUTDOWN) {
++
++ /* We can't do much more than wait for a reset */
++ WARNING(fsg, "error in submission: %s --> %d\n",
++ fsg->ep0->name, rc);
++ }
++ return rc;
++}
++
++static void ep0_complete(struct usb_ep *ep, struct usb_request *req)
++{
++ struct fsg_dev *fsg = ep->driver_data;
++
++ if (req->actual > 0)
++ dump_msg(fsg, fsg->ep0req_name, req->buf, req->actual);
++ if (req->status || req->actual != req->length)
++ DBG(fsg, "%s --> %d, %u/%u\n", __func__,
++ req->status, req->actual, req->length);
++ if (req->status == -ECONNRESET) // Request was cancelled
++ usb_ep_fifo_flush(ep);
++
++ if (req->status == 0 && req->context)
++ ((fsg_routine_t) (req->context))(fsg);
++}
++
++
++/*-------------------------------------------------------------------------*/
++
++/* Bulk and interrupt endpoint completion handlers.
++ * These always run in_irq. */
++
++static void bulk_in_complete(struct usb_ep *ep, struct usb_request *req)
++{
++ struct fsg_dev *fsg = ep->driver_data;
++ struct fsg_buffhd *bh = req->context;
++
++ if (req->status || req->actual != req->length)
++ DBG(fsg, "%s --> %d, %u/%u\n", __func__,
++ req->status, req->actual, req->length);
++ if (req->status == -ECONNRESET) // Request was cancelled
++ usb_ep_fifo_flush(ep);
++
++ /* Hold the lock while we update the request and buffer states */
++ smp_wmb();
++ spin_lock(&fsg->lock);
++ bh->inreq_busy = 0;
++ bh->state = BUF_STATE_EMPTY;
++ wakeup_thread(fsg);
++ spin_unlock(&fsg->lock);
++}
++
++static void bulk_out_complete(struct usb_ep *ep, struct usb_request *req)
++{
++ struct fsg_dev *fsg = ep->driver_data;
++ struct fsg_buffhd *bh = req->context;
++
++ dump_msg(fsg, "bulk-out", req->buf, req->actual);
++ if (req->status || req->actual != bh->bulk_out_intended_length)
++ DBG(fsg, "%s --> %d, %u/%u\n", __func__,
++ req->status, req->actual,
++ bh->bulk_out_intended_length);
++ if (req->status == -ECONNRESET) // Request was cancelled
++ usb_ep_fifo_flush(ep);
++
++ /* Hold the lock while we update the request and buffer states */
++ smp_wmb();
++ spin_lock(&fsg->lock);
++ bh->outreq_busy = 0;
++ bh->state = BUF_STATE_FULL;
++ wakeup_thread(fsg);
++ spin_unlock(&fsg->lock);
++}
++
++
++#ifdef CONFIG_USB_FILE_STORAGE_TEST
++static void intr_in_complete(struct usb_ep *ep, struct usb_request *req)
++{
++ struct fsg_dev *fsg = ep->driver_data;
++ struct fsg_buffhd *bh = req->context;
++
++ if (req->status || req->actual != req->length)
++ DBG(fsg, "%s --> %d, %u/%u\n", __func__,
++ req->status, req->actual, req->length);
++ if (req->status == -ECONNRESET) // Request was cancelled
++ usb_ep_fifo_flush(ep);
++
++ /* Hold the lock while we update the request and buffer states */
++ smp_wmb();
++ spin_lock(&fsg->lock);
++ fsg->intreq_busy = 0;
++ bh->state = BUF_STATE_EMPTY;
++ wakeup_thread(fsg);
++ spin_unlock(&fsg->lock);
++}
++
++#else
++static void intr_in_complete(struct usb_ep *ep, struct usb_request *req)
++{}
++#endif /* CONFIG_USB_FILE_STORAGE_TEST */
++
++
++/*-------------------------------------------------------------------------*/
++
++/* Ep0 class-specific handlers. These always run in_irq. */
++
++#ifdef CONFIG_USB_FILE_STORAGE_TEST
++static void received_cbi_adsc(struct fsg_dev *fsg, struct fsg_buffhd *bh)
++{
++ struct usb_request *req = fsg->ep0req;
++ static u8 cbi_reset_cmnd[6] = {
++ SEND_DIAGNOSTIC, 4, 0xff, 0xff, 0xff, 0xff};
++
++ /* Error in command transfer? */
++ if (req->status || req->length != req->actual ||
++ req->actual < 6 || req->actual > MAX_COMMAND_SIZE) {
++
++ /* Not all controllers allow a protocol stall after
++ * receiving control-out data, but we'll try anyway. */
++ fsg_set_halt(fsg, fsg->ep0);
++ return; // Wait for reset
++ }
++
++ /* Is it the special reset command? */
++ if (req->actual >= sizeof cbi_reset_cmnd &&
++ memcmp(req->buf, cbi_reset_cmnd,
++ sizeof cbi_reset_cmnd) == 0) {
++
++ /* Raise an exception to stop the current operation
++ * and reinitialize our state. */
++ DBG(fsg, "cbi reset request\n");
++ raise_exception(fsg, FSG_STATE_RESET);
++ return;
++ }
++
++ VDBG(fsg, "CB[I] accept device-specific command\n");
++ spin_lock(&fsg->lock);
++
++ /* Save the command for later */
++ if (fsg->cbbuf_cmnd_size)
++ WARNING(fsg, "CB[I] overwriting previous command\n");
++ fsg->cbbuf_cmnd_size = req->actual;
++ memcpy(fsg->cbbuf_cmnd, req->buf, fsg->cbbuf_cmnd_size);
++
++ wakeup_thread(fsg);
++ spin_unlock(&fsg->lock);
++}
++
++#else
++static void received_cbi_adsc(struct fsg_dev *fsg, struct fsg_buffhd *bh)
++{}
++#endif /* CONFIG_USB_FILE_STORAGE_TEST */
++
++
++static int class_setup_req(struct fsg_dev *fsg,
++ const struct usb_ctrlrequest *ctrl)
++{
++ struct usb_request *req = fsg->ep0req;
++ int value = -EOPNOTSUPP;
++ u16 w_index = le16_to_cpu(ctrl->wIndex);
++ u16 w_value = le16_to_cpu(ctrl->wValue);
++ u16 w_length = le16_to_cpu(ctrl->wLength);
++
++ if (!fsg->config)
++ return value;
++
++ /* Handle Bulk-only class-specific requests */
++ if (transport_is_bbb()) {
++ switch (ctrl->bRequest) {
++
++ case US_BULK_RESET_REQUEST:
++ if (ctrl->bRequestType != (USB_DIR_OUT |
++ USB_TYPE_CLASS | USB_RECIP_INTERFACE))
++ break;
++ if (w_index != 0 || w_value != 0 || w_length != 0) {
++ value = -EDOM;
++ break;
++ }
++
++ /* Raise an exception to stop the current operation
++ * and reinitialize our state. */
++ DBG(fsg, "bulk reset request\n");
++ raise_exception(fsg, FSG_STATE_RESET);
++ value = DELAYED_STATUS;
++ break;
++
++ case US_BULK_GET_MAX_LUN:
++ if (ctrl->bRequestType != (USB_DIR_IN |
++ USB_TYPE_CLASS | USB_RECIP_INTERFACE))
++ break;
++ if (w_index != 0 || w_value != 0 || w_length != 1) {
++ value = -EDOM;
++ break;
++ }
++ VDBG(fsg, "get max LUN\n");
++ *(u8 *) req->buf = fsg->nluns - 1;
++ value = 1;
++ break;
++ }
++ }
++
++ /* Handle CBI class-specific requests */
++ else {
++ switch (ctrl->bRequest) {
++
++ case USB_CBI_ADSC_REQUEST:
++ if (ctrl->bRequestType != (USB_DIR_OUT |
++ USB_TYPE_CLASS | USB_RECIP_INTERFACE))
++ break;
++ if (w_index != 0 || w_value != 0) {
++ value = -EDOM;
++ break;
++ }
++ if (w_length > MAX_COMMAND_SIZE) {
++ value = -EOVERFLOW;
++ break;
++ }
++ value = w_length;
++ fsg->ep0req->context = received_cbi_adsc;
++ break;
++ }
++ }
++
++ if (value == -EOPNOTSUPP)
++ VDBG(fsg,
++ "unknown class-specific control req "
++ "%02x.%02x v%04x i%04x l%u\n",
++ ctrl->bRequestType, ctrl->bRequest,
++ le16_to_cpu(ctrl->wValue), w_index, w_length);
++ return value;
++}
++
++
++/*-------------------------------------------------------------------------*/
++
++/* Ep0 standard request handlers. These always run in_irq. */
++
++static int standard_setup_req(struct fsg_dev *fsg,
++ const struct usb_ctrlrequest *ctrl)
++{
++ struct usb_request *req = fsg->ep0req;
++ int value = -EOPNOTSUPP;
++ u16 w_index = le16_to_cpu(ctrl->wIndex);
++ u16 w_value = le16_to_cpu(ctrl->wValue);
++
++ /* Usually this just stores reply data in the pre-allocated ep0 buffer,
++ * but config change events will also reconfigure hardware. */
++ switch (ctrl->bRequest) {
++
++ case USB_REQ_GET_DESCRIPTOR:
++ if (ctrl->bRequestType != (USB_DIR_IN | USB_TYPE_STANDARD |
++ USB_RECIP_DEVICE))
++ break;
++ switch (w_value >> 8) {
++
++ case USB_DT_DEVICE:
++ VDBG(fsg, "get device descriptor\n");
++ device_desc.bMaxPacketSize0 = fsg->ep0->maxpacket;
++ value = sizeof device_desc;
++ memcpy(req->buf, &device_desc, value);
++ break;
++ case USB_DT_DEVICE_QUALIFIER:
++ VDBG(fsg, "get device qualifier\n");
++ if (!gadget_is_dualspeed(fsg->gadget) ||
++ fsg->gadget->speed == USB_SPEED_SUPER)
++ break;
++ /*
++ * Assume ep0 uses the same maxpacket value for both
++ * speeds
++ */
++ dev_qualifier.bMaxPacketSize0 = fsg->ep0->maxpacket;
++ value = sizeof dev_qualifier;
++ memcpy(req->buf, &dev_qualifier, value);
++ break;
++
++ case USB_DT_OTHER_SPEED_CONFIG:
++ VDBG(fsg, "get other-speed config descriptor\n");
++ if (!gadget_is_dualspeed(fsg->gadget) ||
++ fsg->gadget->speed == USB_SPEED_SUPER)
++ break;
++ goto get_config;
++ case USB_DT_CONFIG:
++ VDBG(fsg, "get configuration descriptor\n");
++get_config:
++ value = populate_config_buf(fsg->gadget,
++ req->buf,
++ w_value >> 8,
++ w_value & 0xff);
++ break;
++
++ case USB_DT_STRING:
++ VDBG(fsg, "get string descriptor\n");
++
++ /* wIndex == language code */
++ value = usb_gadget_get_string(&fsg_stringtab,
++ w_value & 0xff, req->buf);
++ break;
++
++ case USB_DT_BOS:
++ VDBG(fsg, "get bos descriptor\n");
++
++ if (gadget_is_superspeed(fsg->gadget))
++ value = populate_bos(fsg, req->buf);
++ break;
++ }
++
++ break;
++
++ /* One config, two speeds */
++ case USB_REQ_SET_CONFIGURATION:
++ if (ctrl->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD |
++ USB_RECIP_DEVICE))
++ break;
++ VDBG(fsg, "set configuration\n");
++ if (w_value == CONFIG_VALUE || w_value == 0) {
++ fsg->new_config = w_value;
++
++ /* Raise an exception to wipe out previous transaction
++ * state (queued bufs, etc) and set the new config. */
++ raise_exception(fsg, FSG_STATE_CONFIG_CHANGE);
++ value = DELAYED_STATUS;
++ }
++ break;
++ case USB_REQ_GET_CONFIGURATION:
++ if (ctrl->bRequestType != (USB_DIR_IN | USB_TYPE_STANDARD |
++ USB_RECIP_DEVICE))
++ break;
++ VDBG(fsg, "get configuration\n");
++ *(u8 *) req->buf = fsg->config;
++ value = 1;
++ break;
++
++ case USB_REQ_SET_INTERFACE:
++ if (ctrl->bRequestType != (USB_DIR_OUT| USB_TYPE_STANDARD |
++ USB_RECIP_INTERFACE))
++ break;
++ if (fsg->config && w_index == 0) {
++
++ /* Raise an exception to wipe out previous transaction
++ * state (queued bufs, etc) and install the new
++ * interface altsetting. */
++ raise_exception(fsg, FSG_STATE_INTERFACE_CHANGE);
++ value = DELAYED_STATUS;
++ }
++ break;
++ case USB_REQ_GET_INTERFACE:
++ if (ctrl->bRequestType != (USB_DIR_IN | USB_TYPE_STANDARD |
++ USB_RECIP_INTERFACE))
++ break;
++ if (!fsg->config)
++ break;
++ if (w_index != 0) {
++ value = -EDOM;
++ break;
++ }
++ VDBG(fsg, "get interface\n");
++ *(u8 *) req->buf = 0;
++ value = 1;
++ break;
++
++ default:
++ VDBG(fsg,
++ "unknown control req %02x.%02x v%04x i%04x l%u\n",
++ ctrl->bRequestType, ctrl->bRequest,
++ w_value, w_index, le16_to_cpu(ctrl->wLength));
++ }
++
++ return value;
++}
++
++
++static int fsg_setup(struct usb_gadget *gadget,
++ const struct usb_ctrlrequest *ctrl)
++{
++ struct fsg_dev *fsg = get_gadget_data(gadget);
++ int rc;
++ int w_length = le16_to_cpu(ctrl->wLength);
++
++ ++fsg->ep0_req_tag; // Record arrival of a new request
++ fsg->ep0req->context = NULL;
++ fsg->ep0req->length = 0;
++ dump_msg(fsg, "ep0-setup", (u8 *) ctrl, sizeof(*ctrl));
++
++ if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_CLASS)
++ rc = class_setup_req(fsg, ctrl);
++ else
++ rc = standard_setup_req(fsg, ctrl);
++
++ /* Respond with data/status or defer until later? */
++ if (rc >= 0 && rc != DELAYED_STATUS) {
++ rc = min(rc, w_length);
++ fsg->ep0req->length = rc;
++ fsg->ep0req->zero = rc < w_length;
++ fsg->ep0req_name = (ctrl->bRequestType & USB_DIR_IN ?
++ "ep0-in" : "ep0-out");
++ rc = ep0_queue(fsg);
++ }
++
++ /* Device either stalls (rc < 0) or reports success */
++ return rc;
++}
++
++
++/*-------------------------------------------------------------------------*/
++
++/* All the following routines run in process context */
++
++
++/* Use this for bulk or interrupt transfers, not ep0 */
++static void start_transfer(struct fsg_dev *fsg, struct usb_ep *ep,
++ struct usb_request *req, int *pbusy,
++ enum fsg_buffer_state *state)
++{
++ int rc;
++
++ if (ep == fsg->bulk_in)
++ dump_msg(fsg, "bulk-in", req->buf, req->length);
++ else if (ep == fsg->intr_in)
++ dump_msg(fsg, "intr-in", req->buf, req->length);
++
++ spin_lock_irq(&fsg->lock);
++ *pbusy = 1;
++ *state = BUF_STATE_BUSY;
++ spin_unlock_irq(&fsg->lock);
++ rc = usb_ep_queue(ep, req, GFP_KERNEL);
++ if (rc != 0) {
++ *pbusy = 0;
++ *state = BUF_STATE_EMPTY;
++
++ /* We can't do much more than wait for a reset */
++
++ /* Note: currently the net2280 driver fails zero-length
++ * submissions if DMA is enabled. */
++ if (rc != -ESHUTDOWN && !(rc == -EOPNOTSUPP &&
++ req->length == 0))
++ WARNING(fsg, "error in submission: %s --> %d\n",
++ ep->name, rc);
++ }
++}
++
++
++static int sleep_thread(struct fsg_dev *fsg)
++{
++ int rc = 0;
++
++ /* Wait until a signal arrives or we are woken up */
++ for (;;) {
++ try_to_freeze();
++ set_current_state(TASK_INTERRUPTIBLE);
++ if (signal_pending(current)) {
++ rc = -EINTR;
++ break;
++ }
++ if (fsg->thread_wakeup_needed)
++ break;
++ schedule();
++ }
++ __set_current_state(TASK_RUNNING);
++ fsg->thread_wakeup_needed = 0;
++ return rc;
++}
++
++
++/*-------------------------------------------------------------------------*/
++
++static int do_read(struct fsg_dev *fsg)
++{
++ struct fsg_lun *curlun = fsg->curlun;
++ u32 lba;
++ struct fsg_buffhd *bh;
++ int rc;
++ u32 amount_left;
++ loff_t file_offset, file_offset_tmp;
++ unsigned int amount;
++ ssize_t nread;
++
++ /* Get the starting Logical Block Address and check that it's
++ * not too big */
++ if (fsg->cmnd[0] == READ_6)
++ lba = get_unaligned_be24(&fsg->cmnd[1]);
++ else {
++ lba = get_unaligned_be32(&fsg->cmnd[2]);
++
++ /* We allow DPO (Disable Page Out = don't save data in the
++ * cache) and FUA (Force Unit Access = don't read from the
++ * cache), but we don't implement them. */
++ if ((fsg->cmnd[1] & ~0x18) != 0) {
++ curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
++ return -EINVAL;
++ }
++ }
++ if (lba >= curlun->num_sectors) {
++ curlun->sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
++ return -EINVAL;
++ }
++ file_offset = ((loff_t) lba) << curlun->blkbits;
++
++ /* Carry out the file reads */
++ amount_left = fsg->data_size_from_cmnd;
++ if (unlikely(amount_left == 0))
++ return -EIO; // No default reply
++
++ for (;;) {
++
++ /* Figure out how much we need to read:
++ * Try to read the remaining amount.
++ * But don't read more than the buffer size.
++ * And don't try to read past the end of the file.
++ */
++ amount = min((unsigned int) amount_left, mod_data.buflen);
++ amount = min((loff_t) amount,
++ curlun->file_length - file_offset);
++
++ /* Wait for the next buffer to become available */
++ bh = fsg->next_buffhd_to_fill;
++ while (bh->state != BUF_STATE_EMPTY) {
++ rc = sleep_thread(fsg);
++ if (rc)
++ return rc;
++ }
++
++ /* If we were asked to read past the end of file,
++ * end with an empty buffer. */
++ if (amount == 0) {
++ curlun->sense_data =
++ SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
++ curlun->sense_data_info = file_offset >> curlun->blkbits;
++ curlun->info_valid = 1;
++ bh->inreq->length = 0;
++ bh->state = BUF_STATE_FULL;
++ break;
++ }
++
++ /* Perform the read */
++ file_offset_tmp = file_offset;
++ nread = vfs_read(curlun->filp,
++ (char __user *) bh->buf,
++ amount, &file_offset_tmp);
++ VLDBG(curlun, "file read %u @ %llu -> %d\n", amount,
++ (unsigned long long) file_offset,
++ (int) nread);
++ if (signal_pending(current))
++ return -EINTR;
++
++ if (nread < 0) {
++ LDBG(curlun, "error in file read: %d\n",
++ (int) nread);
++ nread = 0;
++ } else if (nread < amount) {
++ LDBG(curlun, "partial file read: %d/%u\n",
++ (int) nread, amount);
++ nread = round_down(nread, curlun->blksize);
++ }
++ file_offset += nread;
++ amount_left -= nread;
++ fsg->residue -= nread;
++
++ /* Except at the end of the transfer, nread will be
++ * equal to the buffer size, which is divisible by the
++ * bulk-in maxpacket size.
++ */
++ bh->inreq->length = nread;
++ bh->state = BUF_STATE_FULL;
++
++ /* If an error occurred, report it and its position */
++ if (nread < amount) {
++ curlun->sense_data = SS_UNRECOVERED_READ_ERROR;
++ curlun->sense_data_info = file_offset >> curlun->blkbits;
++ curlun->info_valid = 1;
++ break;
++ }
++
++ if (amount_left == 0)
++ break; // No more left to read
++
++ /* Send this buffer and go read some more */
++ bh->inreq->zero = 0;
++ start_transfer(fsg, fsg->bulk_in, bh->inreq,
++ &bh->inreq_busy, &bh->state);
++ fsg->next_buffhd_to_fill = bh->next;
++ }
++
++ return -EIO; // No default reply
++}
++
++
++/*-------------------------------------------------------------------------*/
++
++static int do_write(struct fsg_dev *fsg)
++{
++ struct fsg_lun *curlun = fsg->curlun;
++ u32 lba;
++ struct fsg_buffhd *bh;
++ int get_some_more;
++ u32 amount_left_to_req, amount_left_to_write;
++ loff_t usb_offset, file_offset, file_offset_tmp;
++ unsigned int amount;
++ ssize_t nwritten;
++ int rc;
++
++ if (curlun->ro) {
++ curlun->sense_data = SS_WRITE_PROTECTED;
++ return -EINVAL;
++ }
++ spin_lock(&curlun->filp->f_lock);
++ curlun->filp->f_flags &= ~O_SYNC; // Default is not to wait
++ spin_unlock(&curlun->filp->f_lock);
++
++ /* Get the starting Logical Block Address and check that it's
++ * not too big */
++ if (fsg->cmnd[0] == WRITE_6)
++ lba = get_unaligned_be24(&fsg->cmnd[1]);
++ else {
++ lba = get_unaligned_be32(&fsg->cmnd[2]);
++
++ /* We allow DPO (Disable Page Out = don't save data in the
++ * cache) and FUA (Force Unit Access = write directly to the
++ * medium). We don't implement DPO; we implement FUA by
++ * performing synchronous output. */
++ if ((fsg->cmnd[1] & ~0x18) != 0) {
++ curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
++ return -EINVAL;
++ }
++ /* FUA */
++ if (!curlun->nofua && (fsg->cmnd[1] & 0x08)) {
++ spin_lock(&curlun->filp->f_lock);
++ curlun->filp->f_flags |= O_DSYNC;
++ spin_unlock(&curlun->filp->f_lock);
++ }
++ }
++ if (lba >= curlun->num_sectors) {
++ curlun->sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
++ return -EINVAL;
++ }
++
++ /* Carry out the file writes */
++ get_some_more = 1;
++ file_offset = usb_offset = ((loff_t) lba) << curlun->blkbits;
++ amount_left_to_req = amount_left_to_write = fsg->data_size_from_cmnd;
++
++ while (amount_left_to_write > 0) {
++
++ /* Queue a request for more data from the host */
++ bh = fsg->next_buffhd_to_fill;
++ if (bh->state == BUF_STATE_EMPTY && get_some_more) {
++
++ /* Figure out how much we want to get:
++ * Try to get the remaining amount,
++ * but not more than the buffer size.
++ */
++ amount = min(amount_left_to_req, mod_data.buflen);
++
++ /* Beyond the end of the backing file? */
++ if (usb_offset >= curlun->file_length) {
++ get_some_more = 0;
++ curlun->sense_data =
++ SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
++ curlun->sense_data_info = usb_offset >> curlun->blkbits;
++ curlun->info_valid = 1;
++ continue;
++ }
++
++ /* Get the next buffer */
++ usb_offset += amount;
++ fsg->usb_amount_left -= amount;
++ amount_left_to_req -= amount;
++ if (amount_left_to_req == 0)
++ get_some_more = 0;
++
++ /* Except at the end of the transfer, amount will be
++ * equal to the buffer size, which is divisible by
++ * the bulk-out maxpacket size.
++ */
++ set_bulk_out_req_length(fsg, bh, amount);
++ start_transfer(fsg, fsg->bulk_out, bh->outreq,
++ &bh->outreq_busy, &bh->state);
++ fsg->next_buffhd_to_fill = bh->next;
++ continue;
++ }
++
++ /* Write the received data to the backing file */
++ bh = fsg->next_buffhd_to_drain;
++ if (bh->state == BUF_STATE_EMPTY && !get_some_more)
++ break; // We stopped early
++ if (bh->state == BUF_STATE_FULL) {
++ smp_rmb();
++ fsg->next_buffhd_to_drain = bh->next;
++ bh->state = BUF_STATE_EMPTY;
++
++ /* Did something go wrong with the transfer? */
++ if (bh->outreq->status != 0) {
++ curlun->sense_data = SS_COMMUNICATION_FAILURE;
++ curlun->sense_data_info = file_offset >> curlun->blkbits;
++ curlun->info_valid = 1;
++ break;
++ }
++
++ amount = bh->outreq->actual;
++ if (curlun->file_length - file_offset < amount) {
++ LERROR(curlun,
++ "write %u @ %llu beyond end %llu\n",
++ amount, (unsigned long long) file_offset,
++ (unsigned long long) curlun->file_length);
++ amount = curlun->file_length - file_offset;
++ }
++
++ /* Don't accept excess data. The spec doesn't say
++ * what to do in this case. We'll ignore the error.
++ */
++ amount = min(amount, bh->bulk_out_intended_length);
++
++ /* Don't write a partial block */
++ amount = round_down(amount, curlun->blksize);
++ if (amount == 0)
++ goto empty_write;
++
++ /* Perform the write */
++ file_offset_tmp = file_offset;
++ nwritten = vfs_write(curlun->filp,
++ (char __user *) bh->buf,
++ amount, &file_offset_tmp);
++ VLDBG(curlun, "file write %u @ %llu -> %d\n", amount,
++ (unsigned long long) file_offset,
++ (int) nwritten);
++ if (signal_pending(current))
++ return -EINTR; // Interrupted!
++
++ if (nwritten < 0) {
++ LDBG(curlun, "error in file write: %d\n",
++ (int) nwritten);
++ nwritten = 0;
++ } else if (nwritten < amount) {
++ LDBG(curlun, "partial file write: %d/%u\n",
++ (int) nwritten, amount);
++ nwritten = round_down(nwritten, curlun->blksize);
++ }
++ file_offset += nwritten;
++ amount_left_to_write -= nwritten;
++ fsg->residue -= nwritten;
++
++ /* If an error occurred, report it and its position */
++ if (nwritten < amount) {
++ curlun->sense_data = SS_WRITE_ERROR;
++ curlun->sense_data_info = file_offset >> curlun->blkbits;
++ curlun->info_valid = 1;
++ break;
++ }
++
++ empty_write:
++ /* Did the host decide to stop early? */
++ if (bh->outreq->actual < bh->bulk_out_intended_length) {
++ fsg->short_packet_received = 1;
++ break;
++ }
++ continue;
++ }
++
++ /* Wait for something to happen */
++ rc = sleep_thread(fsg);
++ if (rc)
++ return rc;
++ }
++
++ return -EIO; // No default reply
++}
++
++
++/*-------------------------------------------------------------------------*/
++
++static int do_synchronize_cache(struct fsg_dev *fsg)
++{
++ struct fsg_lun *curlun = fsg->curlun;
++ int rc;
++
++ /* We ignore the requested LBA and write out all file's
++ * dirty data buffers. */
++ rc = fsg_lun_fsync_sub(curlun);
++ if (rc)
++ curlun->sense_data = SS_WRITE_ERROR;
++ return 0;
++}
++
++
++/*-------------------------------------------------------------------------*/
++
++static void invalidate_sub(struct fsg_lun *curlun)
++{
++ struct file *filp = curlun->filp;
++ struct inode *inode = filp->f_path.dentry->d_inode;
++ unsigned long rc;
++
++ rc = invalidate_mapping_pages(inode->i_mapping, 0, -1);
++ VLDBG(curlun, "invalidate_mapping_pages -> %ld\n", rc);
++}
++
++static int do_verify(struct fsg_dev *fsg)
++{
++ struct fsg_lun *curlun = fsg->curlun;
++ u32 lba;
++ u32 verification_length;
++ struct fsg_buffhd *bh = fsg->next_buffhd_to_fill;
++ loff_t file_offset, file_offset_tmp;
++ u32 amount_left;
++ unsigned int amount;
++ ssize_t nread;
++
++ /* Get the starting Logical Block Address and check that it's
++ * not too big */
++ lba = get_unaligned_be32(&fsg->cmnd[2]);
++ if (lba >= curlun->num_sectors) {
++ curlun->sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
++ return -EINVAL;
++ }
++
++ /* We allow DPO (Disable Page Out = don't save data in the
++ * cache) but we don't implement it. */
++ if ((fsg->cmnd[1] & ~0x10) != 0) {
++ curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
++ return -EINVAL;
++ }
++
++ verification_length = get_unaligned_be16(&fsg->cmnd[7]);
++ if (unlikely(verification_length == 0))
++ return -EIO; // No default reply
++
++ /* Prepare to carry out the file verify */
++ amount_left = verification_length << curlun->blkbits;
++ file_offset = ((loff_t) lba) << curlun->blkbits;
++
++ /* Write out all the dirty buffers before invalidating them */
++ fsg_lun_fsync_sub(curlun);
++ if (signal_pending(current))
++ return -EINTR;
++
++ invalidate_sub(curlun);
++ if (signal_pending(current))
++ return -EINTR;
++
++ /* Just try to read the requested blocks */
++ while (amount_left > 0) {
++
++ /* Figure out how much we need to read:
++ * Try to read the remaining amount, but not more than
++ * the buffer size.
++ * And don't try to read past the end of the file.
++ */
++ amount = min((unsigned int) amount_left, mod_data.buflen);
++ amount = min((loff_t) amount,
++ curlun->file_length - file_offset);
++ if (amount == 0) {
++ curlun->sense_data =
++ SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
++ curlun->sense_data_info = file_offset >> curlun->blkbits;
++ curlun->info_valid = 1;
++ break;
++ }
++
++ /* Perform the read */
++ file_offset_tmp = file_offset;
++ nread = vfs_read(curlun->filp,
++ (char __user *) bh->buf,
++ amount, &file_offset_tmp);
++ VLDBG(curlun, "file read %u @ %llu -> %d\n", amount,
++ (unsigned long long) file_offset,
++ (int) nread);
++ if (signal_pending(current))
++ return -EINTR;
++
++ if (nread < 0) {
++ LDBG(curlun, "error in file verify: %d\n",
++ (int) nread);
++ nread = 0;
++ } else if (nread < amount) {
++ LDBG(curlun, "partial file verify: %d/%u\n",
++ (int) nread, amount);
++ nread = round_down(nread, curlun->blksize);
++ }
++ if (nread == 0) {
++ curlun->sense_data = SS_UNRECOVERED_READ_ERROR;
++ curlun->sense_data_info = file_offset >> curlun->blkbits;
++ curlun->info_valid = 1;
++ break;
++ }
++ file_offset += nread;
++ amount_left -= nread;
++ }
++ return 0;
++}
++
++
++/*-------------------------------------------------------------------------*/
++
++static int do_inquiry(struct fsg_dev *fsg, struct fsg_buffhd *bh)
++{
++ u8 *buf = (u8 *) bh->buf;
++
++ static char vendor_id[] = "Linux ";
++ static char product_disk_id[] = "File-Stor Gadget";
++ static char product_cdrom_id[] = "File-CD Gadget ";
++
++ if (!fsg->curlun) { // Unsupported LUNs are okay
++ fsg->bad_lun_okay = 1;
++ memset(buf, 0, 36);
++ buf[0] = 0x7f; // Unsupported, no device-type
++ buf[4] = 31; // Additional length
++ return 36;
++ }
++
++ memset(buf, 0, 8);
++ buf[0] = (mod_data.cdrom ? TYPE_ROM : TYPE_DISK);
++ if (mod_data.removable)
++ buf[1] = 0x80;
++ buf[2] = 2; // ANSI SCSI level 2
++ buf[3] = 2; // SCSI-2 INQUIRY data format
++ buf[4] = 31; // Additional length
++ // No special options
++ sprintf(buf + 8, "%-8s%-16s%04x", vendor_id,
++ (mod_data.cdrom ? product_cdrom_id :
++ product_disk_id),
++ mod_data.release);
++ return 36;
++}
++
++
++static int do_request_sense(struct fsg_dev *fsg, struct fsg_buffhd *bh)
++{
++ struct fsg_lun *curlun = fsg->curlun;
++ u8 *buf = (u8 *) bh->buf;
++ u32 sd, sdinfo;
++ int valid;
++
++ /*
++ * From the SCSI-2 spec., section 7.9 (Unit attention condition):
++ *
++ * If a REQUEST SENSE command is received from an initiator
++ * with a pending unit attention condition (before the target
++ * generates the contingent allegiance condition), then the
++ * target shall either:
++ * a) report any pending sense data and preserve the unit
++ * attention condition on the logical unit, or,
++ * b) report the unit attention condition, may discard any
++ * pending sense data, and clear the unit attention
++ * condition on the logical unit for that initiator.
++ *
++ * FSG normally uses option a); enable this code to use option b).
++ */
++#if 0
++ if (curlun && curlun->unit_attention_data != SS_NO_SENSE) {
++ curlun->sense_data = curlun->unit_attention_data;
++ curlun->unit_attention_data = SS_NO_SENSE;
++ }
++#endif
++
++ if (!curlun) { // Unsupported LUNs are okay
++ fsg->bad_lun_okay = 1;
++ sd = SS_LOGICAL_UNIT_NOT_SUPPORTED;
++ sdinfo = 0;
++ valid = 0;
++ } else {
++ sd = curlun->sense_data;
++ sdinfo = curlun->sense_data_info;
++ valid = curlun->info_valid << 7;
++ curlun->sense_data = SS_NO_SENSE;
++ curlun->sense_data_info = 0;
++ curlun->info_valid = 0;
++ }
++
++ memset(buf, 0, 18);
++ buf[0] = valid | 0x70; // Valid, current error
++ buf[2] = SK(sd);
++ put_unaligned_be32(sdinfo, &buf[3]); /* Sense information */
++ buf[7] = 18 - 8; // Additional sense length
++ buf[12] = ASC(sd);
++ buf[13] = ASCQ(sd);
++ return 18;
++}
++
++
++static int do_read_capacity(struct fsg_dev *fsg, struct fsg_buffhd *bh)
++{
++ struct fsg_lun *curlun = fsg->curlun;
++ u32 lba = get_unaligned_be32(&fsg->cmnd[2]);
++ int pmi = fsg->cmnd[8];
++ u8 *buf = (u8 *) bh->buf;
++
++ /* Check the PMI and LBA fields */
++ if (pmi > 1 || (pmi == 0 && lba != 0)) {
++ curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
++ return -EINVAL;
++ }
++
++ put_unaligned_be32(curlun->num_sectors - 1, &buf[0]);
++ /* Max logical block */
++ put_unaligned_be32(curlun->blksize, &buf[4]); /* Block length */
++ return 8;
++}
++
++
++static int do_read_header(struct fsg_dev *fsg, struct fsg_buffhd *bh)
++{
++ struct fsg_lun *curlun = fsg->curlun;
++ int msf = fsg->cmnd[1] & 0x02;
++ u32 lba = get_unaligned_be32(&fsg->cmnd[2]);
++ u8 *buf = (u8 *) bh->buf;
++
++ if ((fsg->cmnd[1] & ~0x02) != 0) { /* Mask away MSF */
++ curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
++ return -EINVAL;
++ }
++ if (lba >= curlun->num_sectors) {
++ curlun->sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
++ return -EINVAL;
++ }
++
++ memset(buf, 0, 8);
++ buf[0] = 0x01; /* 2048 bytes of user data, rest is EC */
++ store_cdrom_address(&buf[4], msf, lba);
++ return 8;
++}
++
++
++static int do_read_toc(struct fsg_dev *fsg, struct fsg_buffhd *bh)
++{
++ struct fsg_lun *curlun = fsg->curlun;
++ int msf = fsg->cmnd[1] & 0x02;
++ int start_track = fsg->cmnd[6];
++ u8 *buf = (u8 *) bh->buf;
++
++ if ((fsg->cmnd[1] & ~0x02) != 0 || /* Mask away MSF */
++ start_track > 1) {
++ curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
++ return -EINVAL;
++ }
++
++ memset(buf, 0, 20);
++ buf[1] = (20-2); /* TOC data length */
++ buf[2] = 1; /* First track number */
++ buf[3] = 1; /* Last track number */
++ buf[5] = 0x16; /* Data track, copying allowed */
++ buf[6] = 0x01; /* Only track is number 1 */
++ store_cdrom_address(&buf[8], msf, 0);
++
++ buf[13] = 0x16; /* Lead-out track is data */
++ buf[14] = 0xAA; /* Lead-out track number */
++ store_cdrom_address(&buf[16], msf, curlun->num_sectors);
++ return 20;
++}
++
++
++static int do_mode_sense(struct fsg_dev *fsg, struct fsg_buffhd *bh)
++{
++ struct fsg_lun *curlun = fsg->curlun;
++ int mscmnd = fsg->cmnd[0];
++ u8 *buf = (u8 *) bh->buf;
++ u8 *buf0 = buf;
++ int pc, page_code;
++ int changeable_values, all_pages;
++ int valid_page = 0;
++ int len, limit;
++
++ if ((fsg->cmnd[1] & ~0x08) != 0) { // Mask away DBD
++ curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
++ return -EINVAL;
++ }
++ pc = fsg->cmnd[2] >> 6;
++ page_code = fsg->cmnd[2] & 0x3f;
++ if (pc == 3) {
++ curlun->sense_data = SS_SAVING_PARAMETERS_NOT_SUPPORTED;
++ return -EINVAL;
++ }
++ changeable_values = (pc == 1);
++ all_pages = (page_code == 0x3f);
++
++ /* Write the mode parameter header. Fixed values are: default
++ * medium type, no cache control (DPOFUA), and no block descriptors.
++ * The only variable value is the WriteProtect bit. We will fill in
++ * the mode data length later. */
++ memset(buf, 0, 8);
++ if (mscmnd == MODE_SENSE) {
++ buf[2] = (curlun->ro ? 0x80 : 0x00); // WP, DPOFUA
++ buf += 4;
++ limit = 255;
++ } else { // MODE_SENSE_10
++ buf[3] = (curlun->ro ? 0x80 : 0x00); // WP, DPOFUA
++ buf += 8;
++ limit = 65535; // Should really be mod_data.buflen
++ }
++
++ /* No block descriptors */
++
++ /* The mode pages, in numerical order. The only page we support
++ * is the Caching page. */
++ if (page_code == 0x08 || all_pages) {
++ valid_page = 1;
++ buf[0] = 0x08; // Page code
++ buf[1] = 10; // Page length
++ memset(buf+2, 0, 10); // None of the fields are changeable
++
++ if (!changeable_values) {
++ buf[2] = 0x04; // Write cache enable,
++ // Read cache not disabled
++ // No cache retention priorities
++ put_unaligned_be16(0xffff, &buf[4]);
++ /* Don't disable prefetch */
++ /* Minimum prefetch = 0 */
++ put_unaligned_be16(0xffff, &buf[8]);
++ /* Maximum prefetch */
++ put_unaligned_be16(0xffff, &buf[10]);
++ /* Maximum prefetch ceiling */
++ }
++ buf += 12;
++ }
++
++ /* Check that a valid page was requested and the mode data length
++ * isn't too long. */
++ len = buf - buf0;
++ if (!valid_page || len > limit) {
++ curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
++ return -EINVAL;
++ }
++
++ /* Store the mode data length */
++ if (mscmnd == MODE_SENSE)
++ buf0[0] = len - 1;
++ else
++ put_unaligned_be16(len - 2, buf0);
++ return len;
++}
++
++
++static int do_start_stop(struct fsg_dev *fsg)
++{
++ struct fsg_lun *curlun = fsg->curlun;
++ int loej, start;
++
++ if (!mod_data.removable) {
++ curlun->sense_data = SS_INVALID_COMMAND;
++ return -EINVAL;
++ }
++
++ // int immed = fsg->cmnd[1] & 0x01;
++ loej = fsg->cmnd[4] & 0x02;
++ start = fsg->cmnd[4] & 0x01;
++
++#ifdef CONFIG_USB_FILE_STORAGE_TEST
++ if ((fsg->cmnd[1] & ~0x01) != 0 || // Mask away Immed
++ (fsg->cmnd[4] & ~0x03) != 0) { // Mask LoEj, Start
++ curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
++ return -EINVAL;
++ }
++
++ if (!start) {
++
++ /* Are we allowed to unload the media? */
++ if (curlun->prevent_medium_removal) {
++ LDBG(curlun, "unload attempt prevented\n");
++ curlun->sense_data = SS_MEDIUM_REMOVAL_PREVENTED;
++ return -EINVAL;
++ }
++ if (loej) { // Simulate an unload/eject
++ up_read(&fsg->filesem);
++ down_write(&fsg->filesem);
++ fsg_lun_close(curlun);
++ up_write(&fsg->filesem);
++ down_read(&fsg->filesem);
++ }
++ } else {
++
++ /* Our emulation doesn't support mounting; the medium is
++ * available for use as soon as it is loaded. */
++ if (!fsg_lun_is_open(curlun)) {
++ curlun->sense_data = SS_MEDIUM_NOT_PRESENT;
++ return -EINVAL;
++ }
++ }
++#endif
++ return 0;
++}
++
++
++static int do_prevent_allow(struct fsg_dev *fsg)
++{
++ struct fsg_lun *curlun = fsg->curlun;
++ int prevent;
++
++ if (!mod_data.removable) {
++ curlun->sense_data = SS_INVALID_COMMAND;
++ return -EINVAL;
++ }
++
++ prevent = fsg->cmnd[4] & 0x01;
++ if ((fsg->cmnd[4] & ~0x01) != 0) { // Mask away Prevent
++ curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
++ return -EINVAL;
++ }
++
++ if (curlun->prevent_medium_removal && !prevent)
++ fsg_lun_fsync_sub(curlun);
++ curlun->prevent_medium_removal = prevent;
++ return 0;
++}
++
++
++static int do_read_format_capacities(struct fsg_dev *fsg,
++ struct fsg_buffhd *bh)
++{
++ struct fsg_lun *curlun = fsg->curlun;
++ u8 *buf = (u8 *) bh->buf;
++
++ buf[0] = buf[1] = buf[2] = 0;
++ buf[3] = 8; // Only the Current/Maximum Capacity Descriptor
++ buf += 4;
++
++ put_unaligned_be32(curlun->num_sectors, &buf[0]);
++ /* Number of blocks */
++ put_unaligned_be32(curlun->blksize, &buf[4]); /* Block length */
++ buf[4] = 0x02; /* Current capacity */
++ return 12;
++}
++
++
++static int do_mode_select(struct fsg_dev *fsg, struct fsg_buffhd *bh)
++{
++ struct fsg_lun *curlun = fsg->curlun;
++
++ /* We don't support MODE SELECT */
++ curlun->sense_data = SS_INVALID_COMMAND;
++ return -EINVAL;
++}
++
++
++/*-------------------------------------------------------------------------*/
++
++static int halt_bulk_in_endpoint(struct fsg_dev *fsg)
++{
++ int rc;
++
++ rc = fsg_set_halt(fsg, fsg->bulk_in);
++ if (rc == -EAGAIN)
++ VDBG(fsg, "delayed bulk-in endpoint halt\n");
++ while (rc != 0) {
++ if (rc != -EAGAIN) {
++ WARNING(fsg, "usb_ep_set_halt -> %d\n", rc);
++ rc = 0;
++ break;
++ }
++
++ /* Wait for a short time and then try again */
++ if (msleep_interruptible(100) != 0)
++ return -EINTR;
++ rc = usb_ep_set_halt(fsg->bulk_in);
++ }
++ return rc;
++}
++
++static int wedge_bulk_in_endpoint(struct fsg_dev *fsg)
++{
++ int rc;
++
++ DBG(fsg, "bulk-in set wedge\n");
++ rc = usb_ep_set_wedge(fsg->bulk_in);
++ if (rc == -EAGAIN)
++ VDBG(fsg, "delayed bulk-in endpoint wedge\n");
++ while (rc != 0) {
++ if (rc != -EAGAIN) {
++ WARNING(fsg, "usb_ep_set_wedge -> %d\n", rc);
++ rc = 0;
++ break;
++ }
++
++ /* Wait for a short time and then try again */
++ if (msleep_interruptible(100) != 0)
++ return -EINTR;
++ rc = usb_ep_set_wedge(fsg->bulk_in);
++ }
++ return rc;
++}
++
++static int throw_away_data(struct fsg_dev *fsg)
++{
++ struct fsg_buffhd *bh;
++ u32 amount;
++ int rc;
++
++ while ((bh = fsg->next_buffhd_to_drain)->state != BUF_STATE_EMPTY ||
++ fsg->usb_amount_left > 0) {
++
++ /* Throw away the data in a filled buffer */
++ if (bh->state == BUF_STATE_FULL) {
++ smp_rmb();
++ bh->state = BUF_STATE_EMPTY;
++ fsg->next_buffhd_to_drain = bh->next;
++
++ /* A short packet or an error ends everything */
++ if (bh->outreq->actual < bh->bulk_out_intended_length ||
++ bh->outreq->status != 0) {
++ raise_exception(fsg, FSG_STATE_ABORT_BULK_OUT);
++ return -EINTR;
++ }
++ continue;
++ }
++
++ /* Try to submit another request if we need one */
++ bh = fsg->next_buffhd_to_fill;
++ if (bh->state == BUF_STATE_EMPTY && fsg->usb_amount_left > 0) {
++ amount = min(fsg->usb_amount_left,
++ (u32) mod_data.buflen);
++
++ /* Except at the end of the transfer, amount will be
++ * equal to the buffer size, which is divisible by
++ * the bulk-out maxpacket size.
++ */
++ set_bulk_out_req_length(fsg, bh, amount);
++ start_transfer(fsg, fsg->bulk_out, bh->outreq,
++ &bh->outreq_busy, &bh->state);
++ fsg->next_buffhd_to_fill = bh->next;
++ fsg->usb_amount_left -= amount;
++ continue;
++ }
++
++ /* Otherwise wait for something to happen */
++ rc = sleep_thread(fsg);
++ if (rc)
++ return rc;
++ }
++ return 0;
++}
++
++
++static int finish_reply(struct fsg_dev *fsg)
++{
++ struct fsg_buffhd *bh = fsg->next_buffhd_to_fill;
++ int rc = 0;
++
++ switch (fsg->data_dir) {
++ case DATA_DIR_NONE:
++ break; // Nothing to send
++
++ /* If we don't know whether the host wants to read or write,
++ * this must be CB or CBI with an unknown command. We mustn't
++ * try to send or receive any data. So stall both bulk pipes
++ * if we can and wait for a reset. */
++ case DATA_DIR_UNKNOWN:
++ if (mod_data.can_stall) {
++ fsg_set_halt(fsg, fsg->bulk_out);
++ rc = halt_bulk_in_endpoint(fsg);
++ }
++ break;
++
++ /* All but the last buffer of data must have already been sent */
++ case DATA_DIR_TO_HOST:
++ if (fsg->data_size == 0)
++ ; // Nothing to send
++
++ /* If there's no residue, simply send the last buffer */
++ else if (fsg->residue == 0) {
++ bh->inreq->zero = 0;
++ start_transfer(fsg, fsg->bulk_in, bh->inreq,
++ &bh->inreq_busy, &bh->state);
++ fsg->next_buffhd_to_fill = bh->next;
++ }
++
++ /* There is a residue. For CB and CBI, simply mark the end
++ * of the data with a short packet. However, if we are
++ * allowed to stall, there was no data at all (residue ==
++ * data_size), and the command failed (invalid LUN or
++ * sense data is set), then halt the bulk-in endpoint
++ * instead. */
++ else if (!transport_is_bbb()) {
++ if (mod_data.can_stall &&
++ fsg->residue == fsg->data_size &&
++ (!fsg->curlun || fsg->curlun->sense_data != SS_NO_SENSE)) {
++ bh->state = BUF_STATE_EMPTY;
++ rc = halt_bulk_in_endpoint(fsg);
++ } else {
++ bh->inreq->zero = 1;
++ start_transfer(fsg, fsg->bulk_in, bh->inreq,
++ &bh->inreq_busy, &bh->state);
++ fsg->next_buffhd_to_fill = bh->next;
++ }
++ }
++
++ /*
++ * For Bulk-only, mark the end of the data with a short
++ * packet. If we are allowed to stall, halt the bulk-in
++ * endpoint. (Note: This violates the Bulk-Only Transport
++ * specification, which requires us to pad the data if we
++ * don't halt the endpoint. Presumably nobody will mind.)
++ */
++ else {
++ bh->inreq->zero = 1;
++ start_transfer(fsg, fsg->bulk_in, bh->inreq,
++ &bh->inreq_busy, &bh->state);
++ fsg->next_buffhd_to_fill = bh->next;
++ if (mod_data.can_stall)
++ rc = halt_bulk_in_endpoint(fsg);
++ }
++ break;
++
++ /* We have processed all we want from the data the host has sent.
++ * There may still be outstanding bulk-out requests. */
++ case DATA_DIR_FROM_HOST:
++ if (fsg->residue == 0)
++ ; // Nothing to receive
++
++ /* Did the host stop sending unexpectedly early? */
++ else if (fsg->short_packet_received) {
++ raise_exception(fsg, FSG_STATE_ABORT_BULK_OUT);
++ rc = -EINTR;
++ }
++
++ /* We haven't processed all the incoming data. Even though
++ * we may be allowed to stall, doing so would cause a race.
++ * The controller may already have ACK'ed all the remaining
++ * bulk-out packets, in which case the host wouldn't see a
++ * STALL. Not realizing the endpoint was halted, it wouldn't
++ * clear the halt -- leading to problems later on. */
++#if 0
++ else if (mod_data.can_stall) {
++ fsg_set_halt(fsg, fsg->bulk_out);
++ raise_exception(fsg, FSG_STATE_ABORT_BULK_OUT);
++ rc = -EINTR;
++ }
++#endif
++
++ /* We can't stall. Read in the excess data and throw it
++ * all away. */
++ else
++ rc = throw_away_data(fsg);
++ break;
++ }
++ return rc;
++}
++
++
++static int send_status(struct fsg_dev *fsg)
++{
++ struct fsg_lun *curlun = fsg->curlun;
++ struct fsg_buffhd *bh;
++ int rc;
++ u8 status = US_BULK_STAT_OK;
++ u32 sd, sdinfo = 0;
++
++ /* Wait for the next buffer to become available */
++ bh = fsg->next_buffhd_to_fill;
++ while (bh->state != BUF_STATE_EMPTY) {
++ rc = sleep_thread(fsg);
++ if (rc)
++ return rc;
++ }
++
++ if (curlun) {
++ sd = curlun->sense_data;
++ sdinfo = curlun->sense_data_info;
++ } else if (fsg->bad_lun_okay)
++ sd = SS_NO_SENSE;
++ else
++ sd = SS_LOGICAL_UNIT_NOT_SUPPORTED;
++
++ if (fsg->phase_error) {
++ DBG(fsg, "sending phase-error status\n");
++ status = US_BULK_STAT_PHASE;
++ sd = SS_INVALID_COMMAND;
++ } else if (sd != SS_NO_SENSE) {
++ DBG(fsg, "sending command-failure status\n");
++ status = US_BULK_STAT_FAIL;
++ VDBG(fsg, " sense data: SK x%02x, ASC x%02x, ASCQ x%02x;"
++ " info x%x\n",
++ SK(sd), ASC(sd), ASCQ(sd), sdinfo);
++ }
++
++ if (transport_is_bbb()) {
++ struct bulk_cs_wrap *csw = bh->buf;
++
++ /* Store and send the Bulk-only CSW */
++ csw->Signature = cpu_to_le32(US_BULK_CS_SIGN);
++ csw->Tag = fsg->tag;
++ csw->Residue = cpu_to_le32(fsg->residue);
++ csw->Status = status;
++
++ bh->inreq->length = US_BULK_CS_WRAP_LEN;
++ bh->inreq->zero = 0;
++ start_transfer(fsg, fsg->bulk_in, bh->inreq,
++ &bh->inreq_busy, &bh->state);
++
++ } else if (mod_data.transport_type == USB_PR_CB) {
++
++ /* Control-Bulk transport has no status phase! */
++ return 0;
++
++ } else { // USB_PR_CBI
++ struct interrupt_data *buf = bh->buf;
++
++ /* Store and send the Interrupt data. UFI sends the ASC
++ * and ASCQ bytes. Everything else sends a Type (which
++ * is always 0) and the status Value. */
++ if (mod_data.protocol_type == USB_SC_UFI) {
++ buf->bType = ASC(sd);
++ buf->bValue = ASCQ(sd);
++ } else {
++ buf->bType = 0;
++ buf->bValue = status;
++ }
++ fsg->intreq->length = CBI_INTERRUPT_DATA_LEN;
++
++ fsg->intr_buffhd = bh; // Point to the right buffhd
++ fsg->intreq->buf = bh->inreq->buf;
++ fsg->intreq->context = bh;
++ start_transfer(fsg, fsg->intr_in, fsg->intreq,
++ &fsg->intreq_busy, &bh->state);
++ }
++
++ fsg->next_buffhd_to_fill = bh->next;
++ return 0;
++}
++
++
++/*-------------------------------------------------------------------------*/
++
++/* Check whether the command is properly formed and whether its data size
++ * and direction agree with the values we already have. */
++static int check_command(struct fsg_dev *fsg, int cmnd_size,
++ enum data_direction data_dir, unsigned int mask,
++ int needs_medium, const char *name)
++{
++ int i;
++ int lun = fsg->cmnd[1] >> 5;
++ static const char dirletter[4] = {'u', 'o', 'i', 'n'};
++ char hdlen[20];
++ struct fsg_lun *curlun;
++
++ /* Adjust the expected cmnd_size for protocol encapsulation padding.
++ * Transparent SCSI doesn't pad. */
++ if (protocol_is_scsi())
++ ;
++
++ /* There's some disagreement as to whether RBC pads commands or not.
++ * We'll play it safe and accept either form. */
++ else if (mod_data.protocol_type == USB_SC_RBC) {
++ if (fsg->cmnd_size == 12)
++ cmnd_size = 12;
++
++ /* All the other protocols pad to 12 bytes */
++ } else
++ cmnd_size = 12;
++
++ hdlen[0] = 0;
++ if (fsg->data_dir != DATA_DIR_UNKNOWN)
++ sprintf(hdlen, ", H%c=%u", dirletter[(int) fsg->data_dir],
++ fsg->data_size);
++ VDBG(fsg, "SCSI command: %s; Dc=%d, D%c=%u; Hc=%d%s\n",
++ name, cmnd_size, dirletter[(int) data_dir],
++ fsg->data_size_from_cmnd, fsg->cmnd_size, hdlen);
++
++ /* We can't reply at all until we know the correct data direction
++ * and size. */
++ if (fsg->data_size_from_cmnd == 0)
++ data_dir = DATA_DIR_NONE;
++ if (fsg->data_dir == DATA_DIR_UNKNOWN) { // CB or CBI
++ fsg->data_dir = data_dir;
++ fsg->data_size = fsg->data_size_from_cmnd;
++
++ } else { // Bulk-only
++ if (fsg->data_size < fsg->data_size_from_cmnd) {
++
++ /* Host data size < Device data size is a phase error.
++ * Carry out the command, but only transfer as much
++ * as we are allowed. */
++ fsg->data_size_from_cmnd = fsg->data_size;
++ fsg->phase_error = 1;
++ }
++ }
++ fsg->residue = fsg->usb_amount_left = fsg->data_size;
++
++ /* Conflicting data directions is a phase error */
++ if (fsg->data_dir != data_dir && fsg->data_size_from_cmnd > 0) {
++ fsg->phase_error = 1;
++ return -EINVAL;
++ }
++
++ /* Verify the length of the command itself */
++ if (cmnd_size != fsg->cmnd_size) {
++
++ /* Special case workaround: There are plenty of buggy SCSI
++ * implementations. Many have issues with cbw->Length
++ * field passing a wrong command size. For those cases we
++ * always try to work around the problem by using the length
++ * sent by the host side provided it is at least as large
++ * as the correct command length.
++ * Examples of such cases would be MS-Windows, which issues
++ * REQUEST SENSE with cbw->Length == 12 where it should
++ * be 6, and xbox360 issuing INQUIRY, TEST UNIT READY and
++ * REQUEST SENSE with cbw->Length == 10 where it should
++ * be 6 as well.
++ */
++ if (cmnd_size <= fsg->cmnd_size) {
++ DBG(fsg, "%s is buggy! Expected length %d "
++ "but we got %d\n", name,
++ cmnd_size, fsg->cmnd_size);
++ cmnd_size = fsg->cmnd_size;
++ } else {
++ fsg->phase_error = 1;
++ return -EINVAL;
++ }
++ }
++
++ /* Check that the LUN values are consistent */
++ if (transport_is_bbb()) {
++ if (fsg->lun != lun)
++ DBG(fsg, "using LUN %d from CBW, "
++ "not LUN %d from CDB\n",
++ fsg->lun, lun);
++ }
++
++ /* Check the LUN */
++ curlun = fsg->curlun;
++ if (curlun) {
++ if (fsg->cmnd[0] != REQUEST_SENSE) {
++ curlun->sense_data = SS_NO_SENSE;
++ curlun->sense_data_info = 0;
++ curlun->info_valid = 0;
++ }
++ } else {
++ fsg->bad_lun_okay = 0;
++
++ /* INQUIRY and REQUEST SENSE commands are explicitly allowed
++ * to use unsupported LUNs; all others may not. */
++ if (fsg->cmnd[0] != INQUIRY &&
++ fsg->cmnd[0] != REQUEST_SENSE) {
++ DBG(fsg, "unsupported LUN %d\n", fsg->lun);
++ return -EINVAL;
++ }
++ }
++
++ /* If a unit attention condition exists, only INQUIRY and
++ * REQUEST SENSE commands are allowed; anything else must fail. */
++ if (curlun && curlun->unit_attention_data != SS_NO_SENSE &&
++ fsg->cmnd[0] != INQUIRY &&
++ fsg->cmnd[0] != REQUEST_SENSE) {
++ curlun->sense_data = curlun->unit_attention_data;
++ curlun->unit_attention_data = SS_NO_SENSE;
++ return -EINVAL;
++ }
++
++ /* Check that only command bytes listed in the mask are non-zero */
++ fsg->cmnd[1] &= 0x1f; // Mask away the LUN
++ for (i = 1; i < cmnd_size; ++i) {
++ if (fsg->cmnd[i] && !(mask & (1 << i))) {
++ if (curlun)
++ curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
++ return -EINVAL;
++ }
++ }
++
++ /* If the medium isn't mounted and the command needs to access
++ * it, return an error. */
++ if (curlun && !fsg_lun_is_open(curlun) && needs_medium) {
++ curlun->sense_data = SS_MEDIUM_NOT_PRESENT;
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++/* wrapper of check_command for data size in blocks handling */
++static int check_command_size_in_blocks(struct fsg_dev *fsg, int cmnd_size,
++ enum data_direction data_dir, unsigned int mask,
++ int needs_medium, const char *name)
++{
++ if (fsg->curlun)
++ fsg->data_size_from_cmnd <<= fsg->curlun->blkbits;
++ return check_command(fsg, cmnd_size, data_dir,
++ mask, needs_medium, name);
++}
++
++static int do_scsi_command(struct fsg_dev *fsg)
++{
++ struct fsg_buffhd *bh;
++ int rc;
++ int reply = -EINVAL;
++ int i;
++ static char unknown[16];
++
++ dump_cdb(fsg);
++
++ /* Wait for the next buffer to become available for data or status */
++ bh = fsg->next_buffhd_to_drain = fsg->next_buffhd_to_fill;
++ while (bh->state != BUF_STATE_EMPTY) {
++ rc = sleep_thread(fsg);
++ if (rc)
++ return rc;
++ }
++ fsg->phase_error = 0;
++ fsg->short_packet_received = 0;
++
++ down_read(&fsg->filesem); // We're using the backing file
++ switch (fsg->cmnd[0]) {
++
++ case INQUIRY:
++ fsg->data_size_from_cmnd = fsg->cmnd[4];
++ if ((reply = check_command(fsg, 6, DATA_DIR_TO_HOST,
++ (1<<4), 0,
++ "INQUIRY")) == 0)
++ reply = do_inquiry(fsg, bh);
++ break;
++
++ case MODE_SELECT:
++ fsg->data_size_from_cmnd = fsg->cmnd[4];
++ if ((reply = check_command(fsg, 6, DATA_DIR_FROM_HOST,
++ (1<<1) | (1<<4), 0,
++ "MODE SELECT(6)")) == 0)
++ reply = do_mode_select(fsg, bh);
++ break;
++
++ case MODE_SELECT_10:
++ fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
++ if ((reply = check_command(fsg, 10, DATA_DIR_FROM_HOST,
++ (1<<1) | (3<<7), 0,
++ "MODE SELECT(10)")) == 0)
++ reply = do_mode_select(fsg, bh);
++ break;
++
++ case MODE_SENSE:
++ fsg->data_size_from_cmnd = fsg->cmnd[4];
++ if ((reply = check_command(fsg, 6, DATA_DIR_TO_HOST,
++ (1<<1) | (1<<2) | (1<<4), 0,
++ "MODE SENSE(6)")) == 0)
++ reply = do_mode_sense(fsg, bh);
++ break;
++
++ case MODE_SENSE_10:
++ fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
++ if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST,
++ (1<<1) | (1<<2) | (3<<7), 0,
++ "MODE SENSE(10)")) == 0)
++ reply = do_mode_sense(fsg, bh);
++ break;
++
++ case ALLOW_MEDIUM_REMOVAL:
++ fsg->data_size_from_cmnd = 0;
++ if ((reply = check_command(fsg, 6, DATA_DIR_NONE,
++ (1<<4), 0,
++ "PREVENT-ALLOW MEDIUM REMOVAL")) == 0)
++ reply = do_prevent_allow(fsg);
++ break;
++
++ case READ_6:
++ i = fsg->cmnd[4];
++ fsg->data_size_from_cmnd = (i == 0) ? 256 : i;
++ if ((reply = check_command_size_in_blocks(fsg, 6,
++ DATA_DIR_TO_HOST,
++ (7<<1) | (1<<4), 1,
++ "READ(6)")) == 0)
++ reply = do_read(fsg);
++ break;
++
++ case READ_10:
++ fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
++ if ((reply = check_command_size_in_blocks(fsg, 10,
++ DATA_DIR_TO_HOST,
++ (1<<1) | (0xf<<2) | (3<<7), 1,
++ "READ(10)")) == 0)
++ reply = do_read(fsg);
++ break;
++
++ case READ_12:
++ fsg->data_size_from_cmnd = get_unaligned_be32(&fsg->cmnd[6]);
++ if ((reply = check_command_size_in_blocks(fsg, 12,
++ DATA_DIR_TO_HOST,
++ (1<<1) | (0xf<<2) | (0xf<<6), 1,
++ "READ(12)")) == 0)
++ reply = do_read(fsg);
++ break;
++
++ case READ_CAPACITY:
++ fsg->data_size_from_cmnd = 8;
++ if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST,
++ (0xf<<2) | (1<<8), 1,
++ "READ CAPACITY")) == 0)
++ reply = do_read_capacity(fsg, bh);
++ break;
++
++ case READ_HEADER:
++ if (!mod_data.cdrom)
++ goto unknown_cmnd;
++ fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
++ if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST,
++ (3<<7) | (0x1f<<1), 1,
++ "READ HEADER")) == 0)
++ reply = do_read_header(fsg, bh);
++ break;
++
++ case READ_TOC:
++ if (!mod_data.cdrom)
++ goto unknown_cmnd;
++ fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
++ if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST,
++ (7<<6) | (1<<1), 1,
++ "READ TOC")) == 0)
++ reply = do_read_toc(fsg, bh);
++ break;
++
++ case READ_FORMAT_CAPACITIES:
++ fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
++ if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST,
++ (3<<7), 1,
++ "READ FORMAT CAPACITIES")) == 0)
++ reply = do_read_format_capacities(fsg, bh);
++ break;
++
++ case REQUEST_SENSE:
++ fsg->data_size_from_cmnd = fsg->cmnd[4];
++ if ((reply = check_command(fsg, 6, DATA_DIR_TO_HOST,
++ (1<<4), 0,
++ "REQUEST SENSE")) == 0)
++ reply = do_request_sense(fsg, bh);
++ break;
++
++ case START_STOP:
++ fsg->data_size_from_cmnd = 0;
++ if ((reply = check_command(fsg, 6, DATA_DIR_NONE,
++ (1<<1) | (1<<4), 0,
++ "START-STOP UNIT")) == 0)
++ reply = do_start_stop(fsg);
++ break;
++
++ case SYNCHRONIZE_CACHE:
++ fsg->data_size_from_cmnd = 0;
++ if ((reply = check_command(fsg, 10, DATA_DIR_NONE,
++ (0xf<<2) | (3<<7), 1,
++ "SYNCHRONIZE CACHE")) == 0)
++ reply = do_synchronize_cache(fsg);
++ break;
++
++ case TEST_UNIT_READY:
++ fsg->data_size_from_cmnd = 0;
++ reply = check_command(fsg, 6, DATA_DIR_NONE,
++ 0, 1,
++ "TEST UNIT READY");
++ break;
++
++ /* Although optional, this command is used by MS-Windows. We
++ * support a minimal version: BytChk must be 0. */
++ case VERIFY:
++ fsg->data_size_from_cmnd = 0;
++ if ((reply = check_command(fsg, 10, DATA_DIR_NONE,
++ (1<<1) | (0xf<<2) | (3<<7), 1,
++ "VERIFY")) == 0)
++ reply = do_verify(fsg);
++ break;
++
++ case WRITE_6:
++ i = fsg->cmnd[4];
++ fsg->data_size_from_cmnd = (i == 0) ? 256 : i;
++ if ((reply = check_command_size_in_blocks(fsg, 6,
++ DATA_DIR_FROM_HOST,
++ (7<<1) | (1<<4), 1,
++ "WRITE(6)")) == 0)
++ reply = do_write(fsg);
++ break;
++
++ case WRITE_10:
++ fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
++ if ((reply = check_command_size_in_blocks(fsg, 10,
++ DATA_DIR_FROM_HOST,
++ (1<<1) | (0xf<<2) | (3<<7), 1,
++ "WRITE(10)")) == 0)
++ reply = do_write(fsg);
++ break;
++
++ case WRITE_12:
++ fsg->data_size_from_cmnd = get_unaligned_be32(&fsg->cmnd[6]);
++ if ((reply = check_command_size_in_blocks(fsg, 12,
++ DATA_DIR_FROM_HOST,
++ (1<<1) | (0xf<<2) | (0xf<<6), 1,
++ "WRITE(12)")) == 0)
++ reply = do_write(fsg);
++ break;
++
++ /* Some mandatory commands that we recognize but don't implement.
++ * They don't mean much in this setting. It's left as an exercise
++ * for anyone interested to implement RESERVE and RELEASE in terms
++ * of Posix locks. */
++ case FORMAT_UNIT:
++ case RELEASE:
++ case RESERVE:
++ case SEND_DIAGNOSTIC:
++ // Fall through
++
++ default:
++ unknown_cmnd:
++ fsg->data_size_from_cmnd = 0;
++ sprintf(unknown, "Unknown x%02x", fsg->cmnd[0]);
++ if ((reply = check_command(fsg, fsg->cmnd_size,
++ DATA_DIR_UNKNOWN, ~0, 0, unknown)) == 0) {
++ fsg->curlun->sense_data = SS_INVALID_COMMAND;
++ reply = -EINVAL;
++ }
++ break;
++ }
++ up_read(&fsg->filesem);
++
++ if (reply == -EINTR || signal_pending(current))
++ return -EINTR;
++
++ /* Set up the single reply buffer for finish_reply() */
++ if (reply == -EINVAL)
++ reply = 0; // Error reply length
++ if (reply >= 0 && fsg->data_dir == DATA_DIR_TO_HOST) {
++ reply = min((u32) reply, fsg->data_size_from_cmnd);
++ bh->inreq->length = reply;
++ bh->state = BUF_STATE_FULL;
++ fsg->residue -= reply;
++ } // Otherwise it's already set
++
++ return 0;
++}
++
++
++/*-------------------------------------------------------------------------*/
++
++static int received_cbw(struct fsg_dev *fsg, struct fsg_buffhd *bh)
++{
++ struct usb_request *req = bh->outreq;
++ struct bulk_cb_wrap *cbw = req->buf;
++
++ /* Was this a real packet? Should it be ignored? */
++ if (req->status || test_bit(IGNORE_BULK_OUT, &fsg->atomic_bitflags))
++ return -EINVAL;
++
++ /* Is the CBW valid? */
++ if (req->actual != US_BULK_CB_WRAP_LEN ||
++ cbw->Signature != cpu_to_le32(
++ US_BULK_CB_SIGN)) {
++ DBG(fsg, "invalid CBW: len %u sig 0x%x\n",
++ req->actual,
++ le32_to_cpu(cbw->Signature));
++
++ /* The Bulk-only spec says we MUST stall the IN endpoint
++ * (6.6.1), so it's unavoidable. It also says we must
++ * retain this state until the next reset, but there's
++ * no way to tell the controller driver it should ignore
++ * Clear-Feature(HALT) requests.
++ *
++ * We aren't required to halt the OUT endpoint; instead
++ * we can simply accept and discard any data received
++ * until the next reset. */
++ wedge_bulk_in_endpoint(fsg);
++ set_bit(IGNORE_BULK_OUT, &fsg->atomic_bitflags);
++ return -EINVAL;
++ }
++
++ /* Is the CBW meaningful? */
++ if (cbw->Lun >= FSG_MAX_LUNS || cbw->Flags & ~US_BULK_FLAG_IN ||
++ cbw->Length <= 0 || cbw->Length > MAX_COMMAND_SIZE) {
++ DBG(fsg, "non-meaningful CBW: lun = %u, flags = 0x%x, "
++ "cmdlen %u\n",
++ cbw->Lun, cbw->Flags, cbw->Length);
++
++ /* We can do anything we want here, so let's stall the
++ * bulk pipes if we are allowed to. */
++ if (mod_data.can_stall) {
++ fsg_set_halt(fsg, fsg->bulk_out);
++ halt_bulk_in_endpoint(fsg);
++ }
++ return -EINVAL;
++ }
++
++ /* Save the command for later */
++ fsg->cmnd_size = cbw->Length;
++ memcpy(fsg->cmnd, cbw->CDB, fsg->cmnd_size);
++ if (cbw->Flags & US_BULK_FLAG_IN)
++ fsg->data_dir = DATA_DIR_TO_HOST;
++ else
++ fsg->data_dir = DATA_DIR_FROM_HOST;
++ fsg->data_size = le32_to_cpu(cbw->DataTransferLength);
++ if (fsg->data_size == 0)
++ fsg->data_dir = DATA_DIR_NONE;
++ fsg->lun = cbw->Lun;
++ fsg->tag = cbw->Tag;
++ return 0;
++}
++
++
++static int get_next_command(struct fsg_dev *fsg)
++{
++ struct fsg_buffhd *bh;
++ int rc = 0;
++
++ if (transport_is_bbb()) {
++
++ /* Wait for the next buffer to become available */
++ bh = fsg->next_buffhd_to_fill;
++ while (bh->state != BUF_STATE_EMPTY) {
++ rc = sleep_thread(fsg);
++ if (rc)
++ return rc;
++ }
++
++ /* Queue a request to read a Bulk-only CBW */
++ set_bulk_out_req_length(fsg, bh, US_BULK_CB_WRAP_LEN);
++ start_transfer(fsg, fsg->bulk_out, bh->outreq,
++ &bh->outreq_busy, &bh->state);
++
++ /* We will drain the buffer in software, which means we
++ * can reuse it for the next filling. No need to advance
++ * next_buffhd_to_fill. */
++
++ /* Wait for the CBW to arrive */
++ while (bh->state != BUF_STATE_FULL) {
++ rc = sleep_thread(fsg);
++ if (rc)
++ return rc;
++ }
++ smp_rmb();
++ rc = received_cbw(fsg, bh);
++ bh->state = BUF_STATE_EMPTY;
++
++ } else { // USB_PR_CB or USB_PR_CBI
++
++ /* Wait for the next command to arrive */
++ while (fsg->cbbuf_cmnd_size == 0) {
++ rc = sleep_thread(fsg);
++ if (rc)
++ return rc;
++ }
++
++ /* Is the previous status interrupt request still busy?
++ * The host is allowed to skip reading the status,
++ * so we must cancel it. */
++ if (fsg->intreq_busy)
++ usb_ep_dequeue(fsg->intr_in, fsg->intreq);
++
++ /* Copy the command and mark the buffer empty */
++ fsg->data_dir = DATA_DIR_UNKNOWN;
++ spin_lock_irq(&fsg->lock);
++ fsg->cmnd_size = fsg->cbbuf_cmnd_size;
++ memcpy(fsg->cmnd, fsg->cbbuf_cmnd, fsg->cmnd_size);
++ fsg->cbbuf_cmnd_size = 0;
++ spin_unlock_irq(&fsg->lock);
++
++ /* Use LUN from the command */
++ fsg->lun = fsg->cmnd[1] >> 5;
++ }
++
++ /* Update current lun */
++ if (fsg->lun >= 0 && fsg->lun < fsg->nluns)
++ fsg->curlun = &fsg->luns[fsg->lun];
++ else
++ fsg->curlun = NULL;
++
++ return rc;
++}
++
++
++/*-------------------------------------------------------------------------*/
++
++static int enable_endpoint(struct fsg_dev *fsg, struct usb_ep *ep,
++ const struct usb_endpoint_descriptor *d)
++{
++ int rc;
++
++ ep->driver_data = fsg;
++ ep->desc = d;
++ rc = usb_ep_enable(ep);
++ if (rc)
++ ERROR(fsg, "can't enable %s, result %d\n", ep->name, rc);
++ return rc;
++}
++
++static int alloc_request(struct fsg_dev *fsg, struct usb_ep *ep,
++ struct usb_request **preq)
++{
++ *preq = usb_ep_alloc_request(ep, GFP_ATOMIC);
++ if (*preq)
++ return 0;
++ ERROR(fsg, "can't allocate request for %s\n", ep->name);
++ return -ENOMEM;
++}
++
++/*
++ * Reset interface setting and re-init endpoint state (toggle etc).
++ * Call with altsetting < 0 to disable the interface. The only other
++ * available altsetting is 0, which enables the interface.
++ */
++static int do_set_interface(struct fsg_dev *fsg, int altsetting)
++{
++ int rc = 0;
++ int i;
++ const struct usb_endpoint_descriptor *d;
++
++ if (fsg->running)
++ DBG(fsg, "reset interface\n");
++
++reset:
++ /* Deallocate the requests */
++ for (i = 0; i < fsg_num_buffers; ++i) {
++ struct fsg_buffhd *bh = &fsg->buffhds[i];
++
++ if (bh->inreq) {
++ usb_ep_free_request(fsg->bulk_in, bh->inreq);
++ bh->inreq = NULL;
++ }
++ if (bh->outreq) {
++ usb_ep_free_request(fsg->bulk_out, bh->outreq);
++ bh->outreq = NULL;
++ }
++ }
++ if (fsg->intreq) {
++ usb_ep_free_request(fsg->intr_in, fsg->intreq);
++ fsg->intreq = NULL;
++ }
++
++ /* Disable the endpoints */
++ if (fsg->bulk_in_enabled) {
++ usb_ep_disable(fsg->bulk_in);
++ fsg->bulk_in_enabled = 0;
++ }
++ if (fsg->bulk_out_enabled) {
++ usb_ep_disable(fsg->bulk_out);
++ fsg->bulk_out_enabled = 0;
++ }
++ if (fsg->intr_in_enabled) {
++ usb_ep_disable(fsg->intr_in);
++ fsg->intr_in_enabled = 0;
++ }
++
++ fsg->running = 0;
++ if (altsetting < 0 || rc != 0)
++ return rc;
++
++ DBG(fsg, "set interface %d\n", altsetting);
++
++ /* Enable the endpoints */
++ d = fsg_ep_desc(fsg->gadget,
++ &fsg_fs_bulk_in_desc, &fsg_hs_bulk_in_desc,
++ &fsg_ss_bulk_in_desc);
++ if ((rc = enable_endpoint(fsg, fsg->bulk_in, d)) != 0)
++ goto reset;
++ fsg->bulk_in_enabled = 1;
++
++ d = fsg_ep_desc(fsg->gadget,
++ &fsg_fs_bulk_out_desc, &fsg_hs_bulk_out_desc,
++ &fsg_ss_bulk_out_desc);
++ if ((rc = enable_endpoint(fsg, fsg->bulk_out, d)) != 0)
++ goto reset;
++ fsg->bulk_out_enabled = 1;
++ fsg->bulk_out_maxpacket = usb_endpoint_maxp(d);
++ clear_bit(IGNORE_BULK_OUT, &fsg->atomic_bitflags);
++
++ if (transport_is_cbi()) {
++ d = fsg_ep_desc(fsg->gadget,
++ &fsg_fs_intr_in_desc, &fsg_hs_intr_in_desc,
++ &fsg_ss_intr_in_desc);
++ if ((rc = enable_endpoint(fsg, fsg->intr_in, d)) != 0)
++ goto reset;
++ fsg->intr_in_enabled = 1;
++ }
++
++ /* Allocate the requests */
++ for (i = 0; i < fsg_num_buffers; ++i) {
++ struct fsg_buffhd *bh = &fsg->buffhds[i];
++
++ if ((rc = alloc_request(fsg, fsg->bulk_in, &bh->inreq)) != 0)
++ goto reset;
++ if ((rc = alloc_request(fsg, fsg->bulk_out, &bh->outreq)) != 0)
++ goto reset;
++ bh->inreq->buf = bh->outreq->buf = bh->buf;
++ bh->inreq->context = bh->outreq->context = bh;
++ bh->inreq->complete = bulk_in_complete;
++ bh->outreq->complete = bulk_out_complete;
++ }
++ if (transport_is_cbi()) {
++ if ((rc = alloc_request(fsg, fsg->intr_in, &fsg->intreq)) != 0)
++ goto reset;
++ fsg->intreq->complete = intr_in_complete;
++ }
++
++ fsg->running = 1;
++ for (i = 0; i < fsg->nluns; ++i)
++ fsg->luns[i].unit_attention_data = SS_RESET_OCCURRED;
++ return rc;
++}
++
++
++/*
++ * Change our operational configuration. This code must agree with the code
++ * that returns config descriptors, and with interface altsetting code.
++ *
++ * It's also responsible for power management interactions. Some
++ * configurations might not work with our current power sources.
++ * For now we just assume the gadget is always self-powered.
++ */
++static int do_set_config(struct fsg_dev *fsg, u8 new_config)
++{
++ int rc = 0;
++
++ /* Disable the single interface */
++ if (fsg->config != 0) {
++ DBG(fsg, "reset config\n");
++ fsg->config = 0;
++ rc = do_set_interface(fsg, -1);
++ }
++
++ /* Enable the interface */
++ if (new_config != 0) {
++ fsg->config = new_config;
++ if ((rc = do_set_interface(fsg, 0)) != 0)
++ fsg->config = 0; // Reset on errors
++ else
++ INFO(fsg, "%s config #%d\n",
++ usb_speed_string(fsg->gadget->speed),
++ fsg->config);
++ }
++ return rc;
++}
++
++
++/*-------------------------------------------------------------------------*/
++
++static void handle_exception(struct fsg_dev *fsg)
++{
++ siginfo_t info;
++ int sig;
++ int i;
++ int num_active;
++ struct fsg_buffhd *bh;
++ enum fsg_state old_state;
++ u8 new_config;
++ struct fsg_lun *curlun;
++ unsigned int exception_req_tag;
++ int rc;
++
++ /* Clear the existing signals. Anything but SIGUSR1 is converted
++ * into a high-priority EXIT exception. */
++ for (;;) {
++ sig = dequeue_signal_lock(current, &current->blocked, &info);
++ if (!sig)
++ break;
++ if (sig != SIGUSR1) {
++ if (fsg->state < FSG_STATE_EXIT)
++ DBG(fsg, "Main thread exiting on signal\n");
++ raise_exception(fsg, FSG_STATE_EXIT);
++ }
++ }
++
++ /* Cancel all the pending transfers */
++ if (fsg->intreq_busy)
++ usb_ep_dequeue(fsg->intr_in, fsg->intreq);
++ for (i = 0; i < fsg_num_buffers; ++i) {
++ bh = &fsg->buffhds[i];
++ if (bh->inreq_busy)
++ usb_ep_dequeue(fsg->bulk_in, bh->inreq);
++ if (bh->outreq_busy)
++ usb_ep_dequeue(fsg->bulk_out, bh->outreq);
++ }
++
++ /* Wait until everything is idle */
++ for (;;) {
++ num_active = fsg->intreq_busy;
++ for (i = 0; i < fsg_num_buffers; ++i) {
++ bh = &fsg->buffhds[i];
++ num_active += bh->inreq_busy + bh->outreq_busy;
++ }
++ if (num_active == 0)
++ break;
++ if (sleep_thread(fsg))
++ return;
++ }
++
++ /* Clear out the controller's fifos */
++ if (fsg->bulk_in_enabled)
++ usb_ep_fifo_flush(fsg->bulk_in);
++ if (fsg->bulk_out_enabled)
++ usb_ep_fifo_flush(fsg->bulk_out);
++ if (fsg->intr_in_enabled)
++ usb_ep_fifo_flush(fsg->intr_in);
++
++ /* Reset the I/O buffer states and pointers, the SCSI
++ * state, and the exception. Then invoke the handler. */
++ spin_lock_irq(&fsg->lock);
++
++ for (i = 0; i < fsg_num_buffers; ++i) {
++ bh = &fsg->buffhds[i];
++ bh->state = BUF_STATE_EMPTY;
++ }
++ fsg->next_buffhd_to_fill = fsg->next_buffhd_to_drain =
++ &fsg->buffhds[0];
++
++ exception_req_tag = fsg->exception_req_tag;
++ new_config = fsg->new_config;
++ old_state = fsg->state;
++
++ if (old_state == FSG_STATE_ABORT_BULK_OUT)
++ fsg->state = FSG_STATE_STATUS_PHASE;
++ else {
++ for (i = 0; i < fsg->nluns; ++i) {
++ curlun = &fsg->luns[i];
++ curlun->prevent_medium_removal = 0;
++ curlun->sense_data = curlun->unit_attention_data =
++ SS_NO_SENSE;
++ curlun->sense_data_info = 0;
++ curlun->info_valid = 0;
++ }
++ fsg->state = FSG_STATE_IDLE;
++ }
++ spin_unlock_irq(&fsg->lock);
++
++ /* Carry out any extra actions required for the exception */
++ switch (old_state) {
++ default:
++ break;
++
++ case FSG_STATE_ABORT_BULK_OUT:
++ send_status(fsg);
++ spin_lock_irq(&fsg->lock);
++ if (fsg->state == FSG_STATE_STATUS_PHASE)
++ fsg->state = FSG_STATE_IDLE;
++ spin_unlock_irq(&fsg->lock);
++ break;
++
++ case FSG_STATE_RESET:
++ /* In case we were forced against our will to halt a
++ * bulk endpoint, clear the halt now. (The SuperH UDC
++ * requires this.) */
++ if (test_and_clear_bit(IGNORE_BULK_OUT, &fsg->atomic_bitflags))
++ usb_ep_clear_halt(fsg->bulk_in);
++
++ if (transport_is_bbb()) {
++ if (fsg->ep0_req_tag == exception_req_tag)
++ ep0_queue(fsg); // Complete the status stage
++
++ } else if (transport_is_cbi())
++ send_status(fsg); // Status by interrupt pipe
++
++ /* Technically this should go here, but it would only be
++ * a waste of time. Ditto for the INTERFACE_CHANGE and
++ * CONFIG_CHANGE cases. */
++ // for (i = 0; i < fsg->nluns; ++i)
++ // fsg->luns[i].unit_attention_data = SS_RESET_OCCURRED;
++ break;
++
++ case FSG_STATE_INTERFACE_CHANGE:
++ rc = do_set_interface(fsg, 0);
++ if (fsg->ep0_req_tag != exception_req_tag)
++ break;
++ if (rc != 0) // STALL on errors
++ fsg_set_halt(fsg, fsg->ep0);
++ else // Complete the status stage
++ ep0_queue(fsg);
++ break;
++
++ case FSG_STATE_CONFIG_CHANGE:
++ rc = do_set_config(fsg, new_config);
++ if (fsg->ep0_req_tag != exception_req_tag)
++ break;
++ if (rc != 0) // STALL on errors
++ fsg_set_halt(fsg, fsg->ep0);
++ else // Complete the status stage
++ ep0_queue(fsg);
++ break;
++
++ case FSG_STATE_DISCONNECT:
++ for (i = 0; i < fsg->nluns; ++i)
++ fsg_lun_fsync_sub(fsg->luns + i);
++ do_set_config(fsg, 0); // Unconfigured state
++ break;
++
++ case FSG_STATE_EXIT:
++ case FSG_STATE_TERMINATED:
++ do_set_config(fsg, 0); // Free resources
++ spin_lock_irq(&fsg->lock);
++ fsg->state = FSG_STATE_TERMINATED; // Stop the thread
++ spin_unlock_irq(&fsg->lock);
++ break;
++ }
++}
++
++
++/*-------------------------------------------------------------------------*/
++
++static int fsg_main_thread(void *fsg_)
++{
++ struct fsg_dev *fsg = fsg_;
++
++ /* Allow the thread to be killed by a signal, but set the signal mask
++ * to block everything but INT, TERM, KILL, and USR1. */
++ allow_signal(SIGINT);
++ allow_signal(SIGTERM);
++ allow_signal(SIGKILL);
++ allow_signal(SIGUSR1);
++
++ /* Allow the thread to be frozen */
++ set_freezable();
++
++ /* Arrange for userspace references to be interpreted as kernel
++ * pointers. That way we can pass a kernel pointer to a routine
++ * that expects a __user pointer and it will work okay. */
++ set_fs(get_ds());
++
++ /* The main loop */
++ while (fsg->state != FSG_STATE_TERMINATED) {
++ if (exception_in_progress(fsg) || signal_pending(current)) {
++ handle_exception(fsg);
++ continue;
++ }
++
++ if (!fsg->running) {
++ sleep_thread(fsg);
++ continue;
++ }
++
++ if (get_next_command(fsg))
++ continue;
++
++ spin_lock_irq(&fsg->lock);
++ if (!exception_in_progress(fsg))
++ fsg->state = FSG_STATE_DATA_PHASE;
++ spin_unlock_irq(&fsg->lock);
++
++ if (do_scsi_command(fsg) || finish_reply(fsg))
++ continue;
++
++ spin_lock_irq(&fsg->lock);
++ if (!exception_in_progress(fsg))
++ fsg->state = FSG_STATE_STATUS_PHASE;
++ spin_unlock_irq(&fsg->lock);
++
++ if (send_status(fsg))
++ continue;
++
++ spin_lock_irq(&fsg->lock);
++ if (!exception_in_progress(fsg))
++ fsg->state = FSG_STATE_IDLE;
++ spin_unlock_irq(&fsg->lock);
++ }
++
++ spin_lock_irq(&fsg->lock);
++ fsg->thread_task = NULL;
++ spin_unlock_irq(&fsg->lock);
++
++ /* If we are exiting because of a signal, unregister the
++ * gadget driver. */
++ if (test_and_clear_bit(REGISTERED, &fsg->atomic_bitflags))
++ usb_gadget_unregister_driver(&fsg_driver);
++
++ /* Let the unbind and cleanup routines know the thread has exited */
++ complete_and_exit(&fsg->thread_notifier, 0);
++}
++
++
++/*-------------------------------------------------------------------------*/
++
++
++/* The write permissions and store_xxx pointers are set in fsg_bind() */
++static DEVICE_ATTR(ro, 0444, fsg_show_ro, NULL);
++static DEVICE_ATTR(nofua, 0644, fsg_show_nofua, NULL);
++static DEVICE_ATTR(file, 0444, fsg_show_file, NULL);
++
++
++/*-------------------------------------------------------------------------*/
++
++static void fsg_release(struct kref *ref)
++{
++ struct fsg_dev *fsg = container_of(ref, struct fsg_dev, ref);
++
++ kfree(fsg->luns);
++ kfree(fsg);
++}
++
++static void lun_release(struct device *dev)
++{
++ struct rw_semaphore *filesem = dev_get_drvdata(dev);
++ struct fsg_dev *fsg =
++ container_of(filesem, struct fsg_dev, filesem);
++
++ kref_put(&fsg->ref, fsg_release);
++}
++
++static void /* __init_or_exit */ fsg_unbind(struct usb_gadget *gadget)
++{
++ struct fsg_dev *fsg = get_gadget_data(gadget);
++ int i;
++ struct fsg_lun *curlun;
++ struct usb_request *req = fsg->ep0req;
++
++ DBG(fsg, "unbind\n");
++ clear_bit(REGISTERED, &fsg->atomic_bitflags);
++
++ /* If the thread isn't already dead, tell it to exit now */
++ if (fsg->state != FSG_STATE_TERMINATED) {
++ raise_exception(fsg, FSG_STATE_EXIT);
++ wait_for_completion(&fsg->thread_notifier);
++
++ /* The cleanup routine waits for this completion also */
++ complete(&fsg->thread_notifier);
++ }
++
++ /* Unregister the sysfs attribute files and the LUNs */
++ for (i = 0; i < fsg->nluns; ++i) {
++ curlun = &fsg->luns[i];
++ if (curlun->registered) {
++ device_remove_file(&curlun->dev, &dev_attr_nofua);
++ device_remove_file(&curlun->dev, &dev_attr_ro);
++ device_remove_file(&curlun->dev, &dev_attr_file);
++ fsg_lun_close(curlun);
++ device_unregister(&curlun->dev);
++ curlun->registered = 0;
++ }
++ }
++
++ /* Free the data buffers */
++ for (i = 0; i < fsg_num_buffers; ++i)
++ kfree(fsg->buffhds[i].buf);
++
++ /* Free the request and buffer for endpoint 0 */
++ if (req) {
++ kfree(req->buf);
++ usb_ep_free_request(fsg->ep0, req);
++ }
++
++ set_gadget_data(gadget, NULL);
++}
++
++
++static int __init check_parameters(struct fsg_dev *fsg)
++{
++ int prot;
++ int gcnum;
++
++ /* Store the default values */
++ mod_data.transport_type = USB_PR_BULK;
++ mod_data.transport_name = "Bulk-only";
++ mod_data.protocol_type = USB_SC_SCSI;
++ mod_data.protocol_name = "Transparent SCSI";
++
++ /* Some peripheral controllers are known not to be able to
++ * halt bulk endpoints correctly. If one of them is present,
++ * disable stalls.
++ */
++ if (gadget_is_at91(fsg->gadget))
++ mod_data.can_stall = 0;
++
++ if (mod_data.release == 0xffff) { // Parameter wasn't set
++ gcnum = usb_gadget_controller_number(fsg->gadget);
++ if (gcnum >= 0)
++ mod_data.release = 0x0300 + gcnum;
++ else {
++ WARNING(fsg, "controller '%s' not recognized\n",
++ fsg->gadget->name);
++ mod_data.release = 0x0399;
++ }
++ }
++
++ prot = simple_strtol(mod_data.protocol_parm, NULL, 0);
++
++#ifdef CONFIG_USB_FILE_STORAGE_TEST
++ if (strnicmp(mod_data.transport_parm, "BBB", 10) == 0) {
++ ; // Use default setting
++ } else if (strnicmp(mod_data.transport_parm, "CB", 10) == 0) {
++ mod_data.transport_type = USB_PR_CB;
++ mod_data.transport_name = "Control-Bulk";
++ } else if (strnicmp(mod_data.transport_parm, "CBI", 10) == 0) {
++ mod_data.transport_type = USB_PR_CBI;
++ mod_data.transport_name = "Control-Bulk-Interrupt";
++ } else {
++ ERROR(fsg, "invalid transport: %s\n", mod_data.transport_parm);
++ return -EINVAL;
++ }
++
++ if (strnicmp(mod_data.protocol_parm, "SCSI", 10) == 0 ||
++ prot == USB_SC_SCSI) {
++ ; // Use default setting
++ } else if (strnicmp(mod_data.protocol_parm, "RBC", 10) == 0 ||
++ prot == USB_SC_RBC) {
++ mod_data.protocol_type = USB_SC_RBC;
++ mod_data.protocol_name = "RBC";
++ } else if (strnicmp(mod_data.protocol_parm, "8020", 4) == 0 ||
++ strnicmp(mod_data.protocol_parm, "ATAPI", 10) == 0 ||
++ prot == USB_SC_8020) {
++ mod_data.protocol_type = USB_SC_8020;
++ mod_data.protocol_name = "8020i (ATAPI)";
++ } else if (strnicmp(mod_data.protocol_parm, "QIC", 3) == 0 ||
++ prot == USB_SC_QIC) {
++ mod_data.protocol_type = USB_SC_QIC;
++ mod_data.protocol_name = "QIC-157";
++ } else if (strnicmp(mod_data.protocol_parm, "UFI", 10) == 0 ||
++ prot == USB_SC_UFI) {
++ mod_data.protocol_type = USB_SC_UFI;
++ mod_data.protocol_name = "UFI";
++ } else if (strnicmp(mod_data.protocol_parm, "8070", 4) == 0 ||
++ prot == USB_SC_8070) {
++ mod_data.protocol_type = USB_SC_8070;
++ mod_data.protocol_name = "8070i";
++ } else {
++ ERROR(fsg, "invalid protocol: %s\n", mod_data.protocol_parm);
++ return -EINVAL;
++ }
++
++ mod_data.buflen &= PAGE_CACHE_MASK;
++ if (mod_data.buflen <= 0) {
++ ERROR(fsg, "invalid buflen\n");
++ return -ETOOSMALL;
++ }
++
++#endif /* CONFIG_USB_FILE_STORAGE_TEST */
++
++ /* Serial string handling.
++ * On a real device, the serial string would be loaded
++ * from permanent storage. */
++ if (mod_data.serial) {
++ const char *ch;
++ unsigned len = 0;
++
++ /* Sanity check :
++ * The CB[I] specification limits the serial string to
++ * 12 uppercase hexadecimal characters.
++ * BBB need at least 12 uppercase hexadecimal characters,
++ * with a maximum of 126. */
++ for (ch = mod_data.serial; *ch; ++ch) {
++ ++len;
++ if ((*ch < '0' || *ch > '9') &&
++ (*ch < 'A' || *ch > 'F')) { /* not uppercase hex */
++ WARNING(fsg,
++ "Invalid serial string character: %c\n",
++ *ch);
++ goto no_serial;
++ }
++ }
++ if (len > 126 ||
++ (mod_data.transport_type == USB_PR_BULK && len < 12) ||
++ (mod_data.transport_type != USB_PR_BULK && len > 12)) {
++ WARNING(fsg, "Invalid serial string length!\n");
++ goto no_serial;
++ }
++ fsg_strings[FSG_STRING_SERIAL - 1].s = mod_data.serial;
++ } else {
++ WARNING(fsg, "No serial-number string provided!\n");
++ no_serial:
++ device_desc.iSerialNumber = 0;
++ }
++
++ return 0;
++}
++
++
++static int __init fsg_bind(struct usb_gadget *gadget)
++{
++ struct fsg_dev *fsg = the_fsg;
++ int rc;
++ int i;
++ struct fsg_lun *curlun;
++ struct usb_ep *ep;
++ struct usb_request *req;
++ char *pathbuf, *p;
++
++ fsg->gadget = gadget;
++ set_gadget_data(gadget, fsg);
++ fsg->ep0 = gadget->ep0;
++ fsg->ep0->driver_data = fsg;
++
++ if ((rc = check_parameters(fsg)) != 0)
++ goto out;
++
++ if (mod_data.removable) { // Enable the store_xxx attributes
++ dev_attr_file.attr.mode = 0644;
++ dev_attr_file.store = fsg_store_file;
++ if (!mod_data.cdrom) {
++ dev_attr_ro.attr.mode = 0644;
++ dev_attr_ro.store = fsg_store_ro;
++ }
++ }
++
++ /* Only for removable media? */
++ dev_attr_nofua.attr.mode = 0644;
++ dev_attr_nofua.store = fsg_store_nofua;
++
++ /* Find out how many LUNs there should be */
++ i = mod_data.nluns;
++ if (i == 0)
++ i = max(mod_data.num_filenames, 1u);
++ if (i > FSG_MAX_LUNS) {
++ ERROR(fsg, "invalid number of LUNs: %d\n", i);
++ rc = -EINVAL;
++ goto out;
++ }
++
++ /* Create the LUNs, open their backing files, and register the
++ * LUN devices in sysfs. */
++ fsg->luns = kzalloc(i * sizeof(struct fsg_lun), GFP_KERNEL);
++ if (!fsg->luns) {
++ rc = -ENOMEM;
++ goto out;
++ }
++ fsg->nluns = i;
++
++ for (i = 0; i < fsg->nluns; ++i) {
++ curlun = &fsg->luns[i];
++ curlun->cdrom = !!mod_data.cdrom;
++ curlun->ro = mod_data.cdrom || mod_data.ro[i];
++ curlun->initially_ro = curlun->ro;
++ curlun->removable = mod_data.removable;
++ curlun->nofua = mod_data.nofua[i];
++ curlun->dev.release = lun_release;
++ curlun->dev.parent = &gadget->dev;
++ curlun->dev.driver = &fsg_driver.driver;
++ dev_set_drvdata(&curlun->dev, &fsg->filesem);
++ dev_set_name(&curlun->dev,"%s-lun%d",
++ dev_name(&gadget->dev), i);
++
++ kref_get(&fsg->ref);
++ rc = device_register(&curlun->dev);
++ if (rc) {
++ INFO(fsg, "failed to register LUN%d: %d\n", i, rc);
++ put_device(&curlun->dev);
++ goto out;
++ }
++ curlun->registered = 1;
++
++ rc = device_create_file(&curlun->dev, &dev_attr_ro);
++ if (rc)
++ goto out;
++ rc = device_create_file(&curlun->dev, &dev_attr_nofua);
++ if (rc)
++ goto out;
++ rc = device_create_file(&curlun->dev, &dev_attr_file);
++ if (rc)
++ goto out;
++
++ if (mod_data.file[i] && *mod_data.file[i]) {
++ rc = fsg_lun_open(curlun, mod_data.file[i]);
++ if (rc)
++ goto out;
++ } else if (!mod_data.removable) {
++ ERROR(fsg, "no file given for LUN%d\n", i);
++ rc = -EINVAL;
++ goto out;
++ }
++ }
++
++ /* Find all the endpoints we will use */
++ usb_ep_autoconfig_reset(gadget);
++ ep = usb_ep_autoconfig(gadget, &fsg_fs_bulk_in_desc);
++ if (!ep)
++ goto autoconf_fail;
++ ep->driver_data = fsg; // claim the endpoint
++ fsg->bulk_in = ep;
++
++ ep = usb_ep_autoconfig(gadget, &fsg_fs_bulk_out_desc);
++ if (!ep)
++ goto autoconf_fail;
++ ep->driver_data = fsg; // claim the endpoint
++ fsg->bulk_out = ep;
++
++ if (transport_is_cbi()) {
++ ep = usb_ep_autoconfig(gadget, &fsg_fs_intr_in_desc);
++ if (!ep)
++ goto autoconf_fail;
++ ep->driver_data = fsg; // claim the endpoint
++ fsg->intr_in = ep;
++ }
++
++ /* Fix up the descriptors */
++ device_desc.idVendor = cpu_to_le16(mod_data.vendor);
++ device_desc.idProduct = cpu_to_le16(mod_data.product);
++ device_desc.bcdDevice = cpu_to_le16(mod_data.release);
++
++ i = (transport_is_cbi() ? 3 : 2); // Number of endpoints
++ fsg_intf_desc.bNumEndpoints = i;
++ fsg_intf_desc.bInterfaceSubClass = mod_data.protocol_type;
++ fsg_intf_desc.bInterfaceProtocol = mod_data.transport_type;
++ fsg_fs_function[i + FSG_FS_FUNCTION_PRE_EP_ENTRIES] = NULL;
++
++ if (gadget_is_dualspeed(gadget)) {
++ fsg_hs_function[i + FSG_HS_FUNCTION_PRE_EP_ENTRIES] = NULL;
++
++ /* Assume endpoint addresses are the same for both speeds */
++ fsg_hs_bulk_in_desc.bEndpointAddress =
++ fsg_fs_bulk_in_desc.bEndpointAddress;
++ fsg_hs_bulk_out_desc.bEndpointAddress =
++ fsg_fs_bulk_out_desc.bEndpointAddress;
++ fsg_hs_intr_in_desc.bEndpointAddress =
++ fsg_fs_intr_in_desc.bEndpointAddress;
++ }
++
++ if (gadget_is_superspeed(gadget)) {
++ unsigned max_burst;
++
++ fsg_ss_function[i + FSG_SS_FUNCTION_PRE_EP_ENTRIES] = NULL;
++
++ /* Calculate bMaxBurst, we know packet size is 1024 */
++ max_burst = min_t(unsigned, mod_data.buflen / 1024, 15);
++
++ /* Assume endpoint addresses are the same for both speeds */
++ fsg_ss_bulk_in_desc.bEndpointAddress =
++ fsg_fs_bulk_in_desc.bEndpointAddress;
++ fsg_ss_bulk_in_comp_desc.bMaxBurst = max_burst;
++
++ fsg_ss_bulk_out_desc.bEndpointAddress =
++ fsg_fs_bulk_out_desc.bEndpointAddress;
++ fsg_ss_bulk_out_comp_desc.bMaxBurst = max_burst;
++ }
++
++ if (gadget_is_otg(gadget))
++ fsg_otg_desc.bmAttributes |= USB_OTG_HNP;
++
++ rc = -ENOMEM;
++
++ /* Allocate the request and buffer for endpoint 0 */
++ fsg->ep0req = req = usb_ep_alloc_request(fsg->ep0, GFP_KERNEL);
++ if (!req)
++ goto out;
++ req->buf = kmalloc(EP0_BUFSIZE, GFP_KERNEL);
++ if (!req->buf)
++ goto out;
++ req->complete = ep0_complete;
++
++ /* Allocate the data buffers */
++ for (i = 0; i < fsg_num_buffers; ++i) {
++ struct fsg_buffhd *bh = &fsg->buffhds[i];
++
++ /* Allocate for the bulk-in endpoint. We assume that
++ * the buffer will also work with the bulk-out (and
++ * interrupt-in) endpoint. */
++ bh->buf = kmalloc(mod_data.buflen, GFP_KERNEL);
++ if (!bh->buf)
++ goto out;
++ bh->next = bh + 1;
++ }
++ fsg->buffhds[fsg_num_buffers - 1].next = &fsg->buffhds[0];
++
++ /* This should reflect the actual gadget power source */
++ usb_gadget_set_selfpowered(gadget);
++
++ snprintf(fsg_string_manufacturer, sizeof fsg_string_manufacturer,
++ "%s %s with %s",
++ init_utsname()->sysname, init_utsname()->release,
++ gadget->name);
++
++ fsg->thread_task = kthread_create(fsg_main_thread, fsg,
++ "file-storage-gadget");
++ if (IS_ERR(fsg->thread_task)) {
++ rc = PTR_ERR(fsg->thread_task);
++ goto out;
++ }
++
++ INFO(fsg, DRIVER_DESC ", version: " DRIVER_VERSION "\n");
++ INFO(fsg, "NOTE: This driver is deprecated. "
++ "Consider using g_mass_storage instead.\n");
++ INFO(fsg, "Number of LUNs=%d\n", fsg->nluns);
++
++ pathbuf = kmalloc(PATH_MAX, GFP_KERNEL);
++ for (i = 0; i < fsg->nluns; ++i) {
++ curlun = &fsg->luns[i];
++ if (fsg_lun_is_open(curlun)) {
++ p = NULL;
++ if (pathbuf) {
++ p = d_path(&curlun->filp->f_path,
++ pathbuf, PATH_MAX);
++ if (IS_ERR(p))
++ p = NULL;
++ }
++ LINFO(curlun, "ro=%d, nofua=%d, file: %s\n",
++ curlun->ro, curlun->nofua, (p ? p : "(error)"));
++ }
++ }
++ kfree(pathbuf);
++
++ DBG(fsg, "transport=%s (x%02x)\n",
++ mod_data.transport_name, mod_data.transport_type);
++ DBG(fsg, "protocol=%s (x%02x)\n",
++ mod_data.protocol_name, mod_data.protocol_type);
++ DBG(fsg, "VendorID=x%04x, ProductID=x%04x, Release=x%04x\n",
++ mod_data.vendor, mod_data.product, mod_data.release);
++ DBG(fsg, "removable=%d, stall=%d, cdrom=%d, buflen=%u\n",
++ mod_data.removable, mod_data.can_stall,
++ mod_data.cdrom, mod_data.buflen);
++ DBG(fsg, "I/O thread pid: %d\n", task_pid_nr(fsg->thread_task));
++
++ set_bit(REGISTERED, &fsg->atomic_bitflags);
++
++ /* Tell the thread to start working */
++ wake_up_process(fsg->thread_task);
++ return 0;
++
++autoconf_fail:
++ ERROR(fsg, "unable to autoconfigure all endpoints\n");
++ rc = -ENOTSUPP;
++
++out:
++ fsg->state = FSG_STATE_TERMINATED; // The thread is dead
++ fsg_unbind(gadget);
++ complete(&fsg->thread_notifier);
++ return rc;
++}
++
++
++/*-------------------------------------------------------------------------*/
++
++static void fsg_suspend(struct usb_gadget *gadget)
++{
++ struct fsg_dev *fsg = get_gadget_data(gadget);
++
++ DBG(fsg, "suspend\n");
++ set_bit(SUSPENDED, &fsg->atomic_bitflags);
++}
++
++static void fsg_resume(struct usb_gadget *gadget)
++{
++ struct fsg_dev *fsg = get_gadget_data(gadget);
++
++ DBG(fsg, "resume\n");
++ clear_bit(SUSPENDED, &fsg->atomic_bitflags);
++}
++
++
++/*-------------------------------------------------------------------------*/
++
++static struct usb_gadget_driver fsg_driver = {
++ .max_speed = USB_SPEED_SUPER,
++ .function = (char *) fsg_string_product,
++ .unbind = fsg_unbind,
++ .disconnect = fsg_disconnect,
++ .setup = fsg_setup,
++ .suspend = fsg_suspend,
++ .resume = fsg_resume,
++
++ .driver = {
++ .name = DRIVER_NAME,
++ .owner = THIS_MODULE,
++ // .release = ...
++ // .suspend = ...
++ // .resume = ...
++ },
++};
++
++
++static int __init fsg_alloc(void)
++{
++ struct fsg_dev *fsg;
++
++ fsg = kzalloc(sizeof *fsg +
++ fsg_num_buffers * sizeof *(fsg->buffhds), GFP_KERNEL);
++
++ if (!fsg)
++ return -ENOMEM;
++ spin_lock_init(&fsg->lock);
++ init_rwsem(&fsg->filesem);
++ kref_init(&fsg->ref);
++ init_completion(&fsg->thread_notifier);
++
++ the_fsg = fsg;
++ return 0;
++}
++
++
++static int __init fsg_init(void)
++{
++ int rc;
++ struct fsg_dev *fsg;
++
++ rc = fsg_num_buffers_validate();
++ if (rc != 0)
++ return rc;
++
++ if ((rc = fsg_alloc()) != 0)
++ return rc;
++ fsg = the_fsg;
++ if ((rc = usb_gadget_probe_driver(&fsg_driver, fsg_bind)) != 0)
++ kref_put(&fsg->ref, fsg_release);
++ return rc;
++}
++module_init(fsg_init);
++
++
++static void __exit fsg_cleanup(void)
++{
++ struct fsg_dev *fsg = the_fsg;
++
++ /* Unregister the driver iff the thread hasn't already done so */
++ if (test_and_clear_bit(REGISTERED, &fsg->atomic_bitflags))
++ usb_gadget_unregister_driver(&fsg_driver);
++
++ /* Wait for the thread to finish up */
++ wait_for_completion(&fsg->thread_notifier);
++
++ kref_put(&fsg->ref, fsg_release);
++}
++module_exit(fsg_cleanup);
+diff -Nur linux-4.1.3/drivers/usb/host/dwc_common_port/changes.txt linux-xbian-rpi/drivers/usb/host/dwc_common_port/changes.txt
+--- linux-4.1.3/drivers/usb/host/dwc_common_port/changes.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/usb/host/dwc_common_port/changes.txt 2015-07-28 01:20:58.441170694 +0200
+@@ -0,0 +1,174 @@
++
++dwc_read_reg32() and friends now take an additional parameter, a pointer to an
++IO context struct. The IO context struct should live in an os-dependent struct
++in your driver. As an example, the dwc_usb3 driver has an os-dependent struct
++named 'os_dep' embedded in the main device struct. So there these calls look
++like this:
++
++ dwc_read_reg32(&usb3_dev->os_dep.ioctx, &pcd->dev_global_regs->dcfg);
++
++ dwc_write_reg32(&usb3_dev->os_dep.ioctx,
++ &pcd->dev_global_regs->dcfg, 0);
++
++Note that for the existing Linux driver ports, it is not necessary to actually
++define the 'ioctx' member in the os-dependent struct. Since Linux does not
++require an IO context, its macros for dwc_read_reg32() and friends do not
++use the context pointer, so it is optimized away by the compiler. But it is
++necessary to add the pointer parameter to all of the call sites, to be ready
++for any future ports (such as FreeBSD) which do require an IO context.
++
++
++Similarly, dwc_alloc(), dwc_alloc_atomic(), dwc_strdup(), and dwc_free() now
++take an additional parameter, a pointer to a memory context. Examples:
++
++ addr = dwc_alloc(&usb3_dev->os_dep.memctx, size);
++
++ dwc_free(&usb3_dev->os_dep.memctx, addr);
++
++Again, for the Linux ports, it is not necessary to actually define the memctx
++member, but it is necessary to add the pointer parameter to all of the call
++sites.
++
++
++Same for dwc_dma_alloc() and dwc_dma_free(). Examples:
++
++ virt_addr = dwc_dma_alloc(&usb3_dev->os_dep.dmactx, size, &phys_addr);
++
++ dwc_dma_free(&usb3_dev->os_dep.dmactx, size, virt_addr, phys_addr);
++
++
++Same for dwc_mutex_alloc() and dwc_mutex_free(). Examples:
++
++ mutex = dwc_mutex_alloc(&usb3_dev->os_dep.mtxctx);
++
++ dwc_mutex_free(&usb3_dev->os_dep.mtxctx, mutex);
++
++
++Same for dwc_spinlock_alloc() and dwc_spinlock_free(). Examples:
++
++ lock = dwc_spinlock_alloc(&usb3_dev->osdep.splctx);
++
++ dwc_spinlock_free(&usb3_dev->osdep.splctx, lock);
++
++
++Same for dwc_timer_alloc(). Example:
++
++ timer = dwc_timer_alloc(&usb3_dev->os_dep.tmrctx, "dwc_usb3_tmr1",
++ cb_func, cb_data);
++
++
++Same for dwc_waitq_alloc(). Example:
++
++ waitq = dwc_waitq_alloc(&usb3_dev->os_dep.wtqctx);
++
++
++Same for dwc_thread_run(). Example:
++
++ thread = dwc_thread_run(&usb3_dev->os_dep.thdctx, func,
++ "dwc_usb3_thd1", data);
++
++
++Same for dwc_workq_alloc(). Example:
++
++ workq = dwc_workq_alloc(&usb3_dev->osdep.wkqctx, "dwc_usb3_wkq1");
++
++
++Same for dwc_task_alloc(). Example:
++
++ task = dwc_task_alloc(&usb3_dev->os_dep.tskctx, "dwc_usb3_tsk1",
++ cb_func, cb_data);
++
++
++In addition to the context pointer additions, a few core functions have had
++other changes made to their parameters:
++
++The 'flags' parameter to dwc_spinlock_irqsave() and dwc_spinunlock_irqrestore()
++has been changed from a uint64_t to a dwc_irqflags_t.
++
++dwc_thread_should_stop() now takes a 'dwc_thread_t *' parameter, because the
++FreeBSD equivalent of that function requires it.
++
++And, in addition to the context pointer, dwc_task_alloc() also adds a
++'char *name' parameter, to be consistent with dwc_thread_run() and
++dwc_workq_alloc(), and because the FreeBSD equivalent of that function
++requires a unique name.
++
++
++Here is a complete list of the core functions that now take a pointer to a
++context as their first parameter:
++
++ dwc_read_reg32
++ dwc_read_reg64
++ dwc_write_reg32
++ dwc_write_reg64
++ dwc_modify_reg32
++ dwc_modify_reg64
++ dwc_alloc
++ dwc_alloc_atomic
++ dwc_strdup
++ dwc_free
++ dwc_dma_alloc
++ dwc_dma_free
++ dwc_mutex_alloc
++ dwc_mutex_free
++ dwc_spinlock_alloc
++ dwc_spinlock_free
++ dwc_timer_alloc
++ dwc_waitq_alloc
++ dwc_thread_run
++ dwc_workq_alloc
++ dwc_task_alloc Also adds a 'char *name' as its 2nd parameter
++
++And here are the core functions that have other changes to their parameters:
++
++ dwc_spinlock_irqsave 'flags' param is now a 'dwc_irqflags_t *'
++ dwc_spinunlock_irqrestore 'flags' param is now a 'dwc_irqflags_t'
++ dwc_thread_should_stop Adds a 'dwc_thread_t *' parameter
++
++
++
++The changes to the core functions also require some of the other library
++functions to change:
++
++ dwc_cc_if_alloc() and dwc_cc_if_free() now take a 'void *memctx'
++ (for memory allocation) as the 1st param and a 'void *mtxctx'
++ (for mutex allocation) as the 2nd param.
++
++ dwc_cc_clear(), dwc_cc_add(), dwc_cc_change(), dwc_cc_remove(),
++ dwc_cc_data_for_save(), and dwc_cc_restore_from_data() now take a
++ 'void *memctx' as the 1st param.
++
++ dwc_dh_modpow(), dwc_dh_pk(), and dwc_dh_derive_keys() now take a
++ 'void *memctx' as the 1st param.
++
++ dwc_modpow() now takes a 'void *memctx' as the 1st param.
++
++ dwc_alloc_notification_manager() now takes a 'void *memctx' as the
++ 1st param and a 'void *wkqctx' (for work queue allocation) as the 2nd
++ param, and also now returns an integer value that is non-zero if
++ allocation of its data structures or work queue fails.
++
++ dwc_register_notifier() now takes a 'void *memctx' as the 1st param.
++
++ dwc_memory_debug_start() now takes a 'void *mem_ctx' as the first
++ param, and also now returns an integer value that is non-zero if
++ allocation of its data structures fails.
++
++
++
++Other miscellaneous changes:
++
++The DEBUG_MEMORY and DEBUG_REGS #define's have been renamed to
++DWC_DEBUG_MEMORY and DWC_DEBUG_REGS.
++
++The following #define's have been added to allow selectively compiling library
++features:
++
++ DWC_CCLIB
++ DWC_CRYPTOLIB
++ DWC_NOTIFYLIB
++ DWC_UTFLIB
++
++A DWC_LIBMODULE #define has also been added. If this is not defined, then the
++module code in dwc_common_linux.c is not compiled in. This allows linking the
++library code directly into a driver module, instead of as a standalone module.
+diff -Nur linux-4.1.3/drivers/usb/host/dwc_common_port/doc/doxygen.cfg linux-xbian-rpi/drivers/usb/host/dwc_common_port/doc/doxygen.cfg
+--- linux-4.1.3/drivers/usb/host/dwc_common_port/doc/doxygen.cfg 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/usb/host/dwc_common_port/doc/doxygen.cfg 2015-07-28 01:20:58.441170694 +0200
+@@ -0,0 +1,270 @@
++# Doxyfile 1.4.5
++
++#---------------------------------------------------------------------------
++# Project related configuration options
++#---------------------------------------------------------------------------
++PROJECT_NAME = "Synopsys DWC Portability and Common Library for UWB"
++PROJECT_NUMBER =
++OUTPUT_DIRECTORY = doc
++CREATE_SUBDIRS = NO
++OUTPUT_LANGUAGE = English
++BRIEF_MEMBER_DESC = YES
++REPEAT_BRIEF = YES
++ABBREVIATE_BRIEF = "The $name class" \
++ "The $name widget" \
++ "The $name file" \
++ is \
++ provides \
++ specifies \
++ contains \
++ represents \
++ a \
++ an \
++ the
++ALWAYS_DETAILED_SEC = YES
++INLINE_INHERITED_MEMB = NO
++FULL_PATH_NAMES = NO
++STRIP_FROM_PATH = ..
++STRIP_FROM_INC_PATH =
++SHORT_NAMES = NO
++JAVADOC_AUTOBRIEF = YES
++MULTILINE_CPP_IS_BRIEF = NO
++DETAILS_AT_TOP = YES
++INHERIT_DOCS = YES
++SEPARATE_MEMBER_PAGES = NO
++TAB_SIZE = 8
++ALIASES =
++OPTIMIZE_OUTPUT_FOR_C = YES
++OPTIMIZE_OUTPUT_JAVA = NO
++BUILTIN_STL_SUPPORT = NO
++DISTRIBUTE_GROUP_DOC = NO
++SUBGROUPING = NO
++#---------------------------------------------------------------------------
++# Build related configuration options
++#---------------------------------------------------------------------------
++EXTRACT_ALL = NO
++EXTRACT_PRIVATE = NO
++EXTRACT_STATIC = YES
++EXTRACT_LOCAL_CLASSES = NO
++EXTRACT_LOCAL_METHODS = NO
++HIDE_UNDOC_MEMBERS = NO
++HIDE_UNDOC_CLASSES = NO
++HIDE_FRIEND_COMPOUNDS = NO
++HIDE_IN_BODY_DOCS = NO
++INTERNAL_DOCS = NO
++CASE_SENSE_NAMES = YES
++HIDE_SCOPE_NAMES = NO
++SHOW_INCLUDE_FILES = NO
++INLINE_INFO = YES
++SORT_MEMBER_DOCS = NO
++SORT_BRIEF_DOCS = NO
++SORT_BY_SCOPE_NAME = NO
++GENERATE_TODOLIST = YES
++GENERATE_TESTLIST = YES
++GENERATE_BUGLIST = YES
++GENERATE_DEPRECATEDLIST= YES
++ENABLED_SECTIONS =
++MAX_INITIALIZER_LINES = 30
++SHOW_USED_FILES = YES
++SHOW_DIRECTORIES = YES
++FILE_VERSION_FILTER =
++#---------------------------------------------------------------------------
++# configuration options related to warning and progress messages
++#---------------------------------------------------------------------------
++QUIET = YES
++WARNINGS = YES
++WARN_IF_UNDOCUMENTED = NO
++WARN_IF_DOC_ERROR = YES
++WARN_NO_PARAMDOC = YES
++WARN_FORMAT = "$file:$line: $text"
++WARN_LOGFILE =
++#---------------------------------------------------------------------------
++# configuration options related to the input files
++#---------------------------------------------------------------------------
++INPUT = .
++FILE_PATTERNS = *.c \
++ *.cc \
++ *.cxx \
++ *.cpp \
++ *.c++ \
++ *.d \
++ *.java \
++ *.ii \
++ *.ixx \
++ *.ipp \
++ *.i++ \
++ *.inl \
++ *.h \
++ *.hh \
++ *.hxx \
++ *.hpp \
++ *.h++ \
++ *.idl \
++ *.odl \
++ *.cs \
++ *.php \
++ *.php3 \
++ *.inc \
++ *.m \
++ *.mm \
++ *.dox \
++ *.py \
++ *.C \
++ *.CC \
++ *.C++ \
++ *.II \
++ *.I++ \
++ *.H \
++ *.HH \
++ *.H++ \
++ *.CS \
++ *.PHP \
++ *.PHP3 \
++ *.M \
++ *.MM \
++ *.PY
++RECURSIVE = NO
++EXCLUDE =
++EXCLUDE_SYMLINKS = NO
++EXCLUDE_PATTERNS =
++EXAMPLE_PATH =
++EXAMPLE_PATTERNS = *
++EXAMPLE_RECURSIVE = NO
++IMAGE_PATH =
++INPUT_FILTER =
++FILTER_PATTERNS =
++FILTER_SOURCE_FILES = NO
++#---------------------------------------------------------------------------
++# configuration options related to source browsing
++#---------------------------------------------------------------------------
++SOURCE_BROWSER = NO
++INLINE_SOURCES = NO
++STRIP_CODE_COMMENTS = YES
++REFERENCED_BY_RELATION = YES
++REFERENCES_RELATION = YES
++USE_HTAGS = NO
++VERBATIM_HEADERS = NO
++#---------------------------------------------------------------------------
++# configuration options related to the alphabetical class index
++#---------------------------------------------------------------------------
++ALPHABETICAL_INDEX = NO
++COLS_IN_ALPHA_INDEX = 5
++IGNORE_PREFIX =
++#---------------------------------------------------------------------------
++# configuration options related to the HTML output
++#---------------------------------------------------------------------------
++GENERATE_HTML = YES
++HTML_OUTPUT = html
++HTML_FILE_EXTENSION = .html
++HTML_HEADER =
++HTML_FOOTER =
++HTML_STYLESHEET =
++HTML_ALIGN_MEMBERS = YES
++GENERATE_HTMLHELP = NO
++CHM_FILE =
++HHC_LOCATION =
++GENERATE_CHI = NO
++BINARY_TOC = NO
++TOC_EXPAND = NO
++DISABLE_INDEX = NO
++ENUM_VALUES_PER_LINE = 4
++GENERATE_TREEVIEW = YES
++TREEVIEW_WIDTH = 250
++#---------------------------------------------------------------------------
++# configuration options related to the LaTeX output
++#---------------------------------------------------------------------------
++GENERATE_LATEX = NO
++LATEX_OUTPUT = latex
++LATEX_CMD_NAME = latex
++MAKEINDEX_CMD_NAME = makeindex
++COMPACT_LATEX = NO
++PAPER_TYPE = a4wide
++EXTRA_PACKAGES =
++LATEX_HEADER =
++PDF_HYPERLINKS = NO
++USE_PDFLATEX = NO
++LATEX_BATCHMODE = NO
++LATEX_HIDE_INDICES = NO
++#---------------------------------------------------------------------------
++# configuration options related to the RTF output
++#---------------------------------------------------------------------------
++GENERATE_RTF = NO
++RTF_OUTPUT = rtf
++COMPACT_RTF = NO
++RTF_HYPERLINKS = NO
++RTF_STYLESHEET_FILE =
++RTF_EXTENSIONS_FILE =
++#---------------------------------------------------------------------------
++# configuration options related to the man page output
++#---------------------------------------------------------------------------
++GENERATE_MAN = NO
++MAN_OUTPUT = man
++MAN_EXTENSION = .3
++MAN_LINKS = NO
++#---------------------------------------------------------------------------
++# configuration options related to the XML output
++#---------------------------------------------------------------------------
++GENERATE_XML = NO
++XML_OUTPUT = xml
++XML_SCHEMA =
++XML_DTD =
++XML_PROGRAMLISTING = YES
++#---------------------------------------------------------------------------
++# configuration options for the AutoGen Definitions output
++#---------------------------------------------------------------------------
++GENERATE_AUTOGEN_DEF = NO
++#---------------------------------------------------------------------------
++# configuration options related to the Perl module output
++#---------------------------------------------------------------------------
++GENERATE_PERLMOD = NO
++PERLMOD_LATEX = NO
++PERLMOD_PRETTY = YES
++PERLMOD_MAKEVAR_PREFIX =
++#---------------------------------------------------------------------------
++# Configuration options related to the preprocessor
++#---------------------------------------------------------------------------
++ENABLE_PREPROCESSING = YES
++MACRO_EXPANSION = NO
++EXPAND_ONLY_PREDEF = NO
++SEARCH_INCLUDES = YES
++INCLUDE_PATH =
++INCLUDE_FILE_PATTERNS =
++PREDEFINED = DEBUG DEBUG_MEMORY
++EXPAND_AS_DEFINED =
++SKIP_FUNCTION_MACROS = YES
++#---------------------------------------------------------------------------
++# Configuration::additions related to external references
++#---------------------------------------------------------------------------
++TAGFILES =
++GENERATE_TAGFILE =
++ALLEXTERNALS = NO
++EXTERNAL_GROUPS = YES
++PERL_PATH = /usr/bin/perl
++#---------------------------------------------------------------------------
++# Configuration options related to the dot tool
++#---------------------------------------------------------------------------
++CLASS_DIAGRAMS = YES
++HIDE_UNDOC_RELATIONS = YES
++HAVE_DOT = NO
++CLASS_GRAPH = YES
++COLLABORATION_GRAPH = YES
++GROUP_GRAPHS = YES
++UML_LOOK = NO
++TEMPLATE_RELATIONS = NO
++INCLUDE_GRAPH = NO
++INCLUDED_BY_GRAPH = YES
++CALL_GRAPH = NO
++GRAPHICAL_HIERARCHY = YES
++DIRECTORY_GRAPH = YES
++DOT_IMAGE_FORMAT = png
++DOT_PATH =
++DOTFILE_DIRS =
++MAX_DOT_GRAPH_DEPTH = 1000
++DOT_TRANSPARENT = NO
++DOT_MULTI_TARGETS = NO
++GENERATE_LEGEND = YES
++DOT_CLEANUP = YES
++#---------------------------------------------------------------------------
++# Configuration::additions related to the search engine
++#---------------------------------------------------------------------------
++SEARCHENGINE = NO
+diff -Nur linux-4.1.3/drivers/usb/host/dwc_common_port/dwc_cc.c linux-xbian-rpi/drivers/usb/host/dwc_common_port/dwc_cc.c
+--- linux-4.1.3/drivers/usb/host/dwc_common_port/dwc_cc.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/usb/host/dwc_common_port/dwc_cc.c 2015-07-28 01:20:58.441170694 +0200
+@@ -0,0 +1,532 @@
++/* =========================================================================
++ * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_cc.c $
++ * $Revision: #4 $
++ * $Date: 2010/11/04 $
++ * $Change: 1621692 $
++ *
++ * Synopsys Portability Library Software and documentation
++ * (hereinafter, "Software") is an Unsupported proprietary work of
++ * Synopsys, Inc. unless otherwise expressly agreed to in writing
++ * between Synopsys and you.
++ *
++ * The Software IS NOT an item of Licensed Software or Licensed Product
++ * under any End User Software License Agreement or Agreement for
++ * Licensed Product with Synopsys or any supplement thereto. You are
++ * permitted to use and redistribute this Software in source and binary
++ * forms, with or without modification, provided that redistributions
++ * of source code must retain this notice. You may not view, use,
++ * disclose, copy or distribute this file or any information contained
++ * herein except pursuant to this license grant from Synopsys. If you
++ * do not agree with this notice, including the disclaimer below, then
++ * you are not authorized to use the Software.
++ *
++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
++ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL
++ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
++ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
++ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++ * DAMAGE.
++ * ========================================================================= */
++#ifdef DWC_CCLIB
++
++#include "dwc_cc.h"
++
++typedef struct dwc_cc
++{
++ uint32_t uid;
++ uint8_t chid[16];
++ uint8_t cdid[16];
++ uint8_t ck[16];
++ uint8_t *name;
++ uint8_t length;
++ DWC_CIRCLEQ_ENTRY(dwc_cc) list_entry;
++} dwc_cc_t;
++
++DWC_CIRCLEQ_HEAD(context_list, dwc_cc);
++
++/** The main structure for CC management. */
++struct dwc_cc_if
++{
++ dwc_mutex_t *mutex;
++ char *filename;
++
++ unsigned is_host:1;
++
++ dwc_notifier_t *notifier;
++
++ struct context_list list;
++};
++
++#ifdef DEBUG
++static inline void dump_bytes(char *name, uint8_t *bytes, int len)
++{
++ int i;
++ DWC_PRINTF("%s: ", name);
++ for (i=0; i<len; i++) {
++ DWC_PRINTF("%02x ", bytes[i]);
++ }
++ DWC_PRINTF("\n");
++}
++#else
++#define dump_bytes(x...)
++#endif
++
++static dwc_cc_t *alloc_cc(void *mem_ctx, uint8_t *name, uint32_t length)
++{
++ dwc_cc_t *cc = dwc_alloc(mem_ctx, sizeof(dwc_cc_t));
++ if (!cc) {
++ return NULL;
++ }
++ DWC_MEMSET(cc, 0, sizeof(dwc_cc_t));
++
++ if (name) {
++ cc->length = length;
++ cc->name = dwc_alloc(mem_ctx, length);
++ if (!cc->name) {
++ dwc_free(mem_ctx, cc);
++ return NULL;
++ }
++
++ DWC_MEMCPY(cc->name, name, length);
++ }
++
++ return cc;
++}
++
++static void free_cc(void *mem_ctx, dwc_cc_t *cc)
++{
++ if (cc->name) {
++ dwc_free(mem_ctx, cc->name);
++ }
++ dwc_free(mem_ctx, cc);
++}
++
++static uint32_t next_uid(dwc_cc_if_t *cc_if)
++{
++ uint32_t uid = 0;
++ dwc_cc_t *cc;
++ DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) {
++ if (cc->uid > uid) {
++ uid = cc->uid;
++ }
++ }
++
++ if (uid == 0) {
++ uid = 255;
++ }
++
++ return uid + 1;
++}
++
++static dwc_cc_t *cc_find(dwc_cc_if_t *cc_if, uint32_t uid)
++{
++ dwc_cc_t *cc;
++ DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) {
++ if (cc->uid == uid) {
++ return cc;
++ }
++ }
++ return NULL;
++}
++
++static unsigned int cc_data_size(dwc_cc_if_t *cc_if)
++{
++ unsigned int size = 0;
++ dwc_cc_t *cc;
++ DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) {
++ size += (48 + 1);
++ if (cc->name) {
++ size += cc->length;
++ }
++ }
++ return size;
++}
++
++static uint32_t cc_match_chid(dwc_cc_if_t *cc_if, uint8_t *chid)
++{
++ uint32_t uid = 0;
++ dwc_cc_t *cc;
++
++ DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) {
++ if (DWC_MEMCMP(cc->chid, chid, 16) == 0) {
++ uid = cc->uid;
++ break;
++ }
++ }
++ return uid;
++}
++static uint32_t cc_match_cdid(dwc_cc_if_t *cc_if, uint8_t *cdid)
++{
++ uint32_t uid = 0;
++ dwc_cc_t *cc;
++
++ DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) {
++ if (DWC_MEMCMP(cc->cdid, cdid, 16) == 0) {
++ uid = cc->uid;
++ break;
++ }
++ }
++ return uid;
++}
++
++/* Internal cc_add */
++static int32_t cc_add(void *mem_ctx, dwc_cc_if_t *cc_if, uint8_t *chid,
++ uint8_t *cdid, uint8_t *ck, uint8_t *name, uint8_t length)
++{
++ dwc_cc_t *cc;
++ uint32_t uid;
++
++ if (cc_if->is_host) {
++ uid = cc_match_cdid(cc_if, cdid);
++ }
++ else {
++ uid = cc_match_chid(cc_if, chid);
++ }
++
++ if (uid) {
++ DWC_DEBUGC("Replacing previous connection context id=%d name=%p name_len=%d", uid, name, length);
++ cc = cc_find(cc_if, uid);
++ }
++ else {
++ cc = alloc_cc(mem_ctx, name, length);
++ cc->uid = next_uid(cc_if);
++ DWC_CIRCLEQ_INSERT_TAIL(&cc_if->list, cc, list_entry);
++ }
++
++ DWC_MEMCPY(&(cc->chid[0]), chid, 16);
++ DWC_MEMCPY(&(cc->cdid[0]), cdid, 16);
++ DWC_MEMCPY(&(cc->ck[0]), ck, 16);
++
++ DWC_DEBUGC("Added connection context id=%d name=%p name_len=%d", cc->uid, name, length);
++ dump_bytes("CHID", cc->chid, 16);
++ dump_bytes("CDID", cc->cdid, 16);
++ dump_bytes("CK", cc->ck, 16);
++ return cc->uid;
++}
++
++/* Internal cc_clear */
++static void cc_clear(void *mem_ctx, dwc_cc_if_t *cc_if)
++{
++ while (!DWC_CIRCLEQ_EMPTY(&cc_if->list)) {
++ dwc_cc_t *cc = DWC_CIRCLEQ_FIRST(&cc_if->list);
++ DWC_CIRCLEQ_REMOVE_INIT(&cc_if->list, cc, list_entry);
++ free_cc(mem_ctx, cc);
++ }
++}
++
++dwc_cc_if_t *dwc_cc_if_alloc(void *mem_ctx, void *mtx_ctx,
++ dwc_notifier_t *notifier, unsigned is_host)
++{
++ dwc_cc_if_t *cc_if = NULL;
++
++ /* Allocate a common_cc_if structure */
++ cc_if = dwc_alloc(mem_ctx, sizeof(dwc_cc_if_t));
++
++ if (!cc_if)
++ return NULL;
++
++#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES))
++ DWC_MUTEX_ALLOC_LINUX_DEBUG(cc_if->mutex);
++#else
++ cc_if->mutex = dwc_mutex_alloc(mtx_ctx);
++#endif
++ if (!cc_if->mutex) {
++ dwc_free(mem_ctx, cc_if);
++ return NULL;
++ }
++
++ DWC_CIRCLEQ_INIT(&cc_if->list);
++ cc_if->is_host = is_host;
++ cc_if->notifier = notifier;
++ return cc_if;
++}
++
++void dwc_cc_if_free(void *mem_ctx, void *mtx_ctx, dwc_cc_if_t *cc_if)
++{
++#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES))
++ DWC_MUTEX_FREE(cc_if->mutex);
++#else
++ dwc_mutex_free(mtx_ctx, cc_if->mutex);
++#endif
++ cc_clear(mem_ctx, cc_if);
++ dwc_free(mem_ctx, cc_if);
++}
++
++static void cc_changed(dwc_cc_if_t *cc_if)
++{
++ if (cc_if->notifier) {
++ dwc_notify(cc_if->notifier, DWC_CC_LIST_CHANGED_NOTIFICATION, cc_if);
++ }
++}
++
++void dwc_cc_clear(void *mem_ctx, dwc_cc_if_t *cc_if)
++{
++ DWC_MUTEX_LOCK(cc_if->mutex);
++ cc_clear(mem_ctx, cc_if);
++ DWC_MUTEX_UNLOCK(cc_if->mutex);
++ cc_changed(cc_if);
++}
++
++int32_t dwc_cc_add(void *mem_ctx, dwc_cc_if_t *cc_if, uint8_t *chid,
++ uint8_t *cdid, uint8_t *ck, uint8_t *name, uint8_t length)
++{
++ uint32_t uid;
++
++ DWC_MUTEX_LOCK(cc_if->mutex);
++ uid = cc_add(mem_ctx, cc_if, chid, cdid, ck, name, length);
++ DWC_MUTEX_UNLOCK(cc_if->mutex);
++ cc_changed(cc_if);
++
++ return uid;
++}
++
++void dwc_cc_change(void *mem_ctx, dwc_cc_if_t *cc_if, int32_t id, uint8_t *chid,
++ uint8_t *cdid, uint8_t *ck, uint8_t *name, uint8_t length)
++{
++ dwc_cc_t* cc;
++
++ DWC_DEBUGC("Change connection context %d", id);
++
++ DWC_MUTEX_LOCK(cc_if->mutex);
++ cc = cc_find(cc_if, id);
++ if (!cc) {
++ DWC_ERROR("Uid %d not found in cc list\n", id);
++ DWC_MUTEX_UNLOCK(cc_if->mutex);
++ return;
++ }
++
++ if (chid) {
++ DWC_MEMCPY(&(cc->chid[0]), chid, 16);
++ }
++ if (cdid) {
++ DWC_MEMCPY(&(cc->cdid[0]), cdid, 16);
++ }
++ if (ck) {
++ DWC_MEMCPY(&(cc->ck[0]), ck, 16);
++ }
++
++ if (name) {
++ if (cc->name) {
++ dwc_free(mem_ctx, cc->name);
++ }
++ cc->name = dwc_alloc(mem_ctx, length);
++ if (!cc->name) {
++ DWC_ERROR("Out of memory in dwc_cc_change()\n");
++ DWC_MUTEX_UNLOCK(cc_if->mutex);
++ return;
++ }
++ cc->length = length;
++ DWC_MEMCPY(cc->name, name, length);
++ }
++
++ DWC_MUTEX_UNLOCK(cc_if->mutex);
++
++ cc_changed(cc_if);
++
++ DWC_DEBUGC("Changed connection context id=%d\n", id);
++ dump_bytes("New CHID", cc->chid, 16);
++ dump_bytes("New CDID", cc->cdid, 16);
++ dump_bytes("New CK", cc->ck, 16);
++}
++
++void dwc_cc_remove(void *mem_ctx, dwc_cc_if_t *cc_if, int32_t id)
++{
++ dwc_cc_t *cc;
++
++ DWC_DEBUGC("Removing connection context %d", id);
++
++ DWC_MUTEX_LOCK(cc_if->mutex);
++ cc = cc_find(cc_if, id);
++ if (!cc) {
++ DWC_ERROR("Uid %d not found in cc list\n", id);
++ DWC_MUTEX_UNLOCK(cc_if->mutex);
++ return;
++ }
++
++ DWC_CIRCLEQ_REMOVE_INIT(&cc_if->list, cc, list_entry);
++ DWC_MUTEX_UNLOCK(cc_if->mutex);
++ free_cc(mem_ctx, cc);
++
++ cc_changed(cc_if);
++}
++
++uint8_t *dwc_cc_data_for_save(void *mem_ctx, dwc_cc_if_t *cc_if, unsigned int *length)
++{
++ uint8_t *buf, *x;
++ uint8_t zero = 0;
++ dwc_cc_t *cc;
++
++ DWC_MUTEX_LOCK(cc_if->mutex);
++ *length = cc_data_size(cc_if);
++ if (!(*length)) {
++ DWC_MUTEX_UNLOCK(cc_if->mutex);
++ return NULL;
++ }
++
++ DWC_DEBUGC("Creating data for saving (length=%d)", *length);
++
++ buf = dwc_alloc(mem_ctx, *length);
++ if (!buf) {
++ *length = 0;
++ DWC_MUTEX_UNLOCK(cc_if->mutex);
++ return NULL;
++ }
++
++ x = buf;
++ DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) {
++ DWC_MEMCPY(x, cc->chid, 16);
++ x += 16;
++ DWC_MEMCPY(x, cc->cdid, 16);
++ x += 16;
++ DWC_MEMCPY(x, cc->ck, 16);
++ x += 16;
++ if (cc->name) {
++ DWC_MEMCPY(x, &cc->length, 1);
++ x += 1;
++ DWC_MEMCPY(x, cc->name, cc->length);
++ x += cc->length;
++ }
++ else {
++ DWC_MEMCPY(x, &zero, 1);
++ x += 1;
++ }
++ }
++ DWC_MUTEX_UNLOCK(cc_if->mutex);
++
++ return buf;
++}
++
++void dwc_cc_restore_from_data(void *mem_ctx, dwc_cc_if_t *cc_if, uint8_t *data, uint32_t length)
++{
++ uint8_t name_length;
++ uint8_t *name;
++ uint8_t *chid;
++ uint8_t *cdid;
++ uint8_t *ck;
++ uint32_t i = 0;
++
++ DWC_MUTEX_LOCK(cc_if->mutex);
++ cc_clear(mem_ctx, cc_if);
++
++ while (i < length) {
++ chid = &data[i];
++ i += 16;
++ cdid = &data[i];
++ i += 16;
++ ck = &data[i];
++ i += 16;
++
++ name_length = data[i];
++ i ++;
++
++ if (name_length) {
++ name = &data[i];
++ i += name_length;
++ }
++ else {
++ name = NULL;
++ }
++
++ /* check to see if we haven't overflown the buffer */
++ if (i > length) {
++ DWC_ERROR("Data format error while attempting to load CCs "
++ "(nlen=%d, iter=%d, buflen=%d).\n", name_length, i, length);
++ break;
++ }
++
++ cc_add(mem_ctx, cc_if, chid, cdid, ck, name, name_length);
++ }
++ DWC_MUTEX_UNLOCK(cc_if->mutex);
++
++ cc_changed(cc_if);
++}
++
++uint32_t dwc_cc_match_chid(dwc_cc_if_t *cc_if, uint8_t *chid)
++{
++ uint32_t uid = 0;
++
++ DWC_MUTEX_LOCK(cc_if->mutex);
++ uid = cc_match_chid(cc_if, chid);
++ DWC_MUTEX_UNLOCK(cc_if->mutex);
++ return uid;
++}
++uint32_t dwc_cc_match_cdid(dwc_cc_if_t *cc_if, uint8_t *cdid)
++{
++ uint32_t uid = 0;
++
++ DWC_MUTEX_LOCK(cc_if->mutex);
++ uid = cc_match_cdid(cc_if, cdid);
++ DWC_MUTEX_UNLOCK(cc_if->mutex);
++ return uid;
++}
++
++uint8_t *dwc_cc_ck(dwc_cc_if_t *cc_if, int32_t id)
++{
++ uint8_t *ck = NULL;
++ dwc_cc_t *cc;
++
++ DWC_MUTEX_LOCK(cc_if->mutex);
++ cc = cc_find(cc_if, id);
++ if (cc) {
++ ck = cc->ck;
++ }
++ DWC_MUTEX_UNLOCK(cc_if->mutex);
++
++ return ck;
++
++}
++
++uint8_t *dwc_cc_chid(dwc_cc_if_t *cc_if, int32_t id)
++{
++ uint8_t *retval = NULL;
++ dwc_cc_t *cc;
++
++ DWC_MUTEX_LOCK(cc_if->mutex);
++ cc = cc_find(cc_if, id);
++ if (cc) {
++ retval = cc->chid;
++ }
++ DWC_MUTEX_UNLOCK(cc_if->mutex);
++
++ return retval;
++}
++
++uint8_t *dwc_cc_cdid(dwc_cc_if_t *cc_if, int32_t id)
++{
++ uint8_t *retval = NULL;
++ dwc_cc_t *cc;
++
++ DWC_MUTEX_LOCK(cc_if->mutex);
++ cc = cc_find(cc_if, id);
++ if (cc) {
++ retval = cc->cdid;
++ }
++ DWC_MUTEX_UNLOCK(cc_if->mutex);
++
++ return retval;
++}
++
++uint8_t *dwc_cc_name(dwc_cc_if_t *cc_if, int32_t id, uint8_t *length)
++{
++ uint8_t *retval = NULL;
++ dwc_cc_t *cc;
++
++ DWC_MUTEX_LOCK(cc_if->mutex);
++ *length = 0;
++ cc = cc_find(cc_if, id);
++ if (cc) {
++ *length = cc->length;
++ retval = cc->name;
++ }
++ DWC_MUTEX_UNLOCK(cc_if->mutex);
++
++ return retval;
++}
++
++#endif /* DWC_CCLIB */
+diff -Nur linux-4.1.3/drivers/usb/host/dwc_common_port/dwc_cc.h linux-xbian-rpi/drivers/usb/host/dwc_common_port/dwc_cc.h
+--- linux-4.1.3/drivers/usb/host/dwc_common_port/dwc_cc.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/usb/host/dwc_common_port/dwc_cc.h 2015-07-28 01:20:58.441170694 +0200
+@@ -0,0 +1,224 @@
++/* =========================================================================
++ * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_cc.h $
++ * $Revision: #4 $
++ * $Date: 2010/09/28 $
++ * $Change: 1596182 $
++ *
++ * Synopsys Portability Library Software and documentation
++ * (hereinafter, "Software") is an Unsupported proprietary work of
++ * Synopsys, Inc. unless otherwise expressly agreed to in writing
++ * between Synopsys and you.
++ *
++ * The Software IS NOT an item of Licensed Software or Licensed Product
++ * under any End User Software License Agreement or Agreement for
++ * Licensed Product with Synopsys or any supplement thereto. You are
++ * permitted to use and redistribute this Software in source and binary
++ * forms, with or without modification, provided that redistributions
++ * of source code must retain this notice. You may not view, use,
++ * disclose, copy or distribute this file or any information contained
++ * herein except pursuant to this license grant from Synopsys. If you
++ * do not agree with this notice, including the disclaimer below, then
++ * you are not authorized to use the Software.
++ *
++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
++ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL
++ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
++ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
++ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++ * DAMAGE.
++ * ========================================================================= */
++#ifndef _DWC_CC_H_
++#define _DWC_CC_H_
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/** @file
++ *
++ * This file defines the Context Context library.
++ *
++ * The main data structure is dwc_cc_if_t which is returned by either the
++ * dwc_cc_if_alloc function or returned by the module to the user via a provided
++ * function. The data structure is opaque and should only be manipulated via the
++ * functions provied in this API.
++ *
++ * It manages a list of connection contexts and operations can be performed to
++ * add, remove, query, search, and change, those contexts. Additionally,
++ * a dwc_notifier_t object can be requested from the manager so that
++ * the user can be notified whenever the context list has changed.
++ */
++
++#include "dwc_os.h"
++#include "dwc_list.h"
++#include "dwc_notifier.h"
++
++
++/* Notifications */
++#define DWC_CC_LIST_CHANGED_NOTIFICATION "DWC_CC_LIST_CHANGED_NOTIFICATION"
++
++struct dwc_cc_if;
++typedef struct dwc_cc_if dwc_cc_if_t;
++
++
++/** @name Connection Context Operations */
++/** @{ */
++
++/** This function allocates memory for a dwc_cc_if_t structure, initializes
++ * fields to default values, and returns a pointer to the structure or NULL on
++ * error. */
++extern dwc_cc_if_t *dwc_cc_if_alloc(void *mem_ctx, void *mtx_ctx,
++ dwc_notifier_t *notifier, unsigned is_host);
++
++/** Frees the memory for the specified CC structure allocated from
++ * dwc_cc_if_alloc(). */
++extern void dwc_cc_if_free(void *mem_ctx, void *mtx_ctx, dwc_cc_if_t *cc_if);
++
++/** Removes all contexts from the connection context list */
++extern void dwc_cc_clear(void *mem_ctx, dwc_cc_if_t *cc_if);
++
++/** Adds a connection context (CHID, CK, CDID, Name) to the connection context list.
++ * If a CHID already exists, the CK and name are overwritten. Statistics are
++ * not overwritten.
++ *
++ * @param cc_if The cc_if structure.
++ * @param chid A pointer to the 16-byte CHID. This value will be copied.
++ * @param ck A pointer to the 16-byte CK. This value will be copied.
++ * @param cdid A pointer to the 16-byte CDID. This value will be copied.
++ * @param name An optional host friendly name as defined in the association model
++ * spec. Must be a UTF16-LE unicode string. Can be NULL to indicated no name.
++ * @param length The length othe unicode string.
++ * @return A unique identifier used to refer to this context that is valid for
++ * as long as this context is still in the list. */
++extern int32_t dwc_cc_add(void *mem_ctx, dwc_cc_if_t *cc_if, uint8_t *chid,
++ uint8_t *cdid, uint8_t *ck, uint8_t *name,
++ uint8_t length);
++
++/** Changes the CHID, CK, CDID, or Name values of a connection context in the
++ * list, preserving any accumulated statistics. This would typically be called
++ * if the host decideds to change the context with a SET_CONNECTION request.
++ *
++ * @param cc_if The cc_if structure.
++ * @param id The identifier of the connection context.
++ * @param chid A pointer to the 16-byte CHID. This value will be copied. NULL
++ * indicates no change.
++ * @param cdid A pointer to the 16-byte CDID. This value will be copied. NULL
++ * indicates no change.
++ * @param ck A pointer to the 16-byte CK. This value will be copied. NULL
++ * indicates no change.
++ * @param name Host friendly name UTF16-LE. NULL indicates no change.
++ * @param length Length of name. */
++extern void dwc_cc_change(void *mem_ctx, dwc_cc_if_t *cc_if, int32_t id,
++ uint8_t *chid, uint8_t *cdid, uint8_t *ck,
++ uint8_t *name, uint8_t length);
++
++/** Remove the specified connection context.
++ * @param cc_if The cc_if structure.
++ * @param id The identifier of the connection context to remove. */
++extern void dwc_cc_remove(void *mem_ctx, dwc_cc_if_t *cc_if, int32_t id);
++
++/** Get a binary block of data for the connection context list and attributes.
++ * This data can be used by the OS specific driver to save the connection
++ * context list into non-volatile memory.
++ *
++ * @param cc_if The cc_if structure.
++ * @param length Return the length of the data buffer.
++ * @return A pointer to the data buffer. The memory for this buffer should be
++ * freed with DWC_FREE() after use. */
++extern uint8_t *dwc_cc_data_for_save(void *mem_ctx, dwc_cc_if_t *cc_if,
++ unsigned int *length);
++
++/** Restore the connection context list from the binary data that was previously
++ * returned from a call to dwc_cc_data_for_save. This can be used by the OS specific
++ * driver to load a connection context list from non-volatile memory.
++ *
++ * @param cc_if The cc_if structure.
++ * @param data The data bytes as returned from dwc_cc_data_for_save.
++ * @param length The length of the data. */
++extern void dwc_cc_restore_from_data(void *mem_ctx, dwc_cc_if_t *cc_if,
++ uint8_t *data, unsigned int length);
++
++/** Find the connection context from the specified CHID.
++ *
++ * @param cc_if The cc_if structure.
++ * @param chid A pointer to the CHID data.
++ * @return A non-zero identifier of the connection context if the CHID matches.
++ * Otherwise returns 0. */
++extern uint32_t dwc_cc_match_chid(dwc_cc_if_t *cc_if, uint8_t *chid);
++
++/** Find the connection context from the specified CDID.
++ *
++ * @param cc_if The cc_if structure.
++ * @param cdid A pointer to the CDID data.
++ * @return A non-zero identifier of the connection context if the CHID matches.
++ * Otherwise returns 0. */
++extern uint32_t dwc_cc_match_cdid(dwc_cc_if_t *cc_if, uint8_t *cdid);
++
++/** Retrieve the CK from the specified connection context.
++ *
++ * @param cc_if The cc_if structure.
++ * @param id The identifier of the connection context.
++ * @return A pointer to the CK data. The memory does not need to be freed. */
++extern uint8_t *dwc_cc_ck(dwc_cc_if_t *cc_if, int32_t id);
++
++/** Retrieve the CHID from the specified connection context.
++ *
++ * @param cc_if The cc_if structure.
++ * @param id The identifier of the connection context.
++ * @return A pointer to the CHID data. The memory does not need to be freed. */
++extern uint8_t *dwc_cc_chid(dwc_cc_if_t *cc_if, int32_t id);
++
++/** Retrieve the CDID from the specified connection context.
++ *
++ * @param cc_if The cc_if structure.
++ * @param id The identifier of the connection context.
++ * @return A pointer to the CDID data. The memory does not need to be freed. */
++extern uint8_t *dwc_cc_cdid(dwc_cc_if_t *cc_if, int32_t id);
++
++extern uint8_t *dwc_cc_name(dwc_cc_if_t *cc_if, int32_t id, uint8_t *length);
++
++/** Checks a buffer for non-zero.
++ * @param id A pointer to a 16 byte buffer.
++ * @return true if the 16 byte value is non-zero. */
++static inline unsigned dwc_assoc_is_not_zero_id(uint8_t *id) {
++ int i;
++ for (i=0; i<16; i++) {
++ if (id[i]) return 1;
++ }
++ return 0;
++}
++
++/** Checks a buffer for zero.
++ * @param id A pointer to a 16 byte buffer.
++ * @return true if the 16 byte value is zero. */
++static inline unsigned dwc_assoc_is_zero_id(uint8_t *id) {
++ return !dwc_assoc_is_not_zero_id(id);
++}
++
++/** Prints an ASCII representation for the 16-byte chid, cdid, or ck, into
++ * buffer. */
++static inline int dwc_print_id_string(char *buffer, uint8_t *id) {
++ char *ptr = buffer;
++ int i;
++ for (i=0; i<16; i++) {
++ ptr += DWC_SPRINTF(ptr, "%02x", id[i]);
++ if (i < 15) {
++ ptr += DWC_SPRINTF(ptr, " ");
++ }
++ }
++ return ptr - buffer;
++}
++
++/** @} */
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* _DWC_CC_H_ */
+diff -Nur linux-4.1.3/drivers/usb/host/dwc_common_port/dwc_common_fbsd.c linux-xbian-rpi/drivers/usb/host/dwc_common_port/dwc_common_fbsd.c
+--- linux-4.1.3/drivers/usb/host/dwc_common_port/dwc_common_fbsd.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/usb/host/dwc_common_port/dwc_common_fbsd.c 2015-07-28 01:20:58.441170694 +0200
+@@ -0,0 +1,1308 @@
++#include "dwc_os.h"
++#include "dwc_list.h"
++
++#ifdef DWC_CCLIB
++# include "dwc_cc.h"
++#endif
++
++#ifdef DWC_CRYPTOLIB
++# include "dwc_modpow.h"
++# include "dwc_dh.h"
++# include "dwc_crypto.h"
++#endif
++
++#ifdef DWC_NOTIFYLIB
++# include "dwc_notifier.h"
++#endif
++
++/* OS-Level Implementations */
++
++/* This is the FreeBSD 7.0 kernel implementation of the DWC platform library. */
++
++
++/* MISC */
++
++void *DWC_MEMSET(void *dest, uint8_t byte, uint32_t size)
++{
++ return memset(dest, byte, size);
++}
++
++void *DWC_MEMCPY(void *dest, void const *src, uint32_t size)
++{
++ return memcpy(dest, src, size);
++}
++
++void *DWC_MEMMOVE(void *dest, void *src, uint32_t size)
++{
++ bcopy(src, dest, size);
++ return dest;
++}
++
++int DWC_MEMCMP(void *m1, void *m2, uint32_t size)
++{
++ return memcmp(m1, m2, size);
++}
++
++int DWC_STRNCMP(void *s1, void *s2, uint32_t size)
++{
++ return strncmp(s1, s2, size);
++}
++
++int DWC_STRCMP(void *s1, void *s2)
++{
++ return strcmp(s1, s2);
++}
++
++int DWC_STRLEN(char const *str)
++{
++ return strlen(str);
++}
++
++char *DWC_STRCPY(char *to, char const *from)
++{
++ return strcpy(to, from);
++}
++
++char *DWC_STRDUP(char const *str)
++{
++ int len = DWC_STRLEN(str) + 1;
++ char *new = DWC_ALLOC_ATOMIC(len);
++
++ if (!new) {
++ return NULL;
++ }
++
++ DWC_MEMCPY(new, str, len);
++ return new;
++}
++
++int DWC_ATOI(char *str, int32_t *value)
++{
++ char *end = NULL;
++
++ *value = strtol(str, &end, 0);
++ if (*end == '\0') {
++ return 0;
++ }
++
++ return -1;
++}
++
++int DWC_ATOUI(char *str, uint32_t *value)
++{
++ char *end = NULL;
++
++ *value = strtoul(str, &end, 0);
++ if (*end == '\0') {
++ return 0;
++ }
++
++ return -1;
++}
++
++
++#ifdef DWC_UTFLIB
++/* From usbstring.c */
++
++int DWC_UTF8_TO_UTF16LE(uint8_t const *s, uint16_t *cp, unsigned len)
++{
++ int count = 0;
++ u8 c;
++ u16 uchar;
++
++ /* this insists on correct encodings, though not minimal ones.
++ * BUT it currently rejects legit 4-byte UTF-8 code points,
++ * which need surrogate pairs. (Unicode 3.1 can use them.)
++ */
++ while (len != 0 && (c = (u8) *s++) != 0) {
++ if (unlikely(c & 0x80)) {
++ // 2-byte sequence:
++ // 00000yyyyyxxxxxx = 110yyyyy 10xxxxxx
++ if ((c & 0xe0) == 0xc0) {
++ uchar = (c & 0x1f) << 6;
++
++ c = (u8) *s++;
++ if ((c & 0xc0) != 0xc0)
++ goto fail;
++ c &= 0x3f;
++ uchar |= c;
++
++ // 3-byte sequence (most CJKV characters):
++ // zzzzyyyyyyxxxxxx = 1110zzzz 10yyyyyy 10xxxxxx
++ } else if ((c & 0xf0) == 0xe0) {
++ uchar = (c & 0x0f) << 12;
++
++ c = (u8) *s++;
++ if ((c & 0xc0) != 0xc0)
++ goto fail;
++ c &= 0x3f;
++ uchar |= c << 6;
++
++ c = (u8) *s++;
++ if ((c & 0xc0) != 0xc0)
++ goto fail;
++ c &= 0x3f;
++ uchar |= c;
++
++ /* no bogus surrogates */
++ if (0xd800 <= uchar && uchar <= 0xdfff)
++ goto fail;
++
++ // 4-byte sequence (surrogate pairs, currently rare):
++ // 11101110wwwwzzzzyy + 110111yyyyxxxxxx
++ // = 11110uuu 10uuzzzz 10yyyyyy 10xxxxxx
++ // (uuuuu = wwww + 1)
++ // FIXME accept the surrogate code points (only)
++ } else
++ goto fail;
++ } else
++ uchar = c;
++ put_unaligned (cpu_to_le16 (uchar), cp++);
++ count++;
++ len--;
++ }
++ return count;
++fail:
++ return -1;
++}
++
++#endif /* DWC_UTFLIB */
++
++
++/* dwc_debug.h */
++
++dwc_bool_t DWC_IN_IRQ(void)
++{
++// return in_irq();
++ return 0;
++}
++
++dwc_bool_t DWC_IN_BH(void)
++{
++// return in_softirq();
++ return 0;
++}
++
++void DWC_VPRINTF(char *format, va_list args)
++{
++ vprintf(format, args);
++}
++
++int DWC_VSNPRINTF(char *str, int size, char *format, va_list args)
++{
++ return vsnprintf(str, size, format, args);
++}
++
++void DWC_PRINTF(char *format, ...)
++{
++ va_list args;
++
++ va_start(args, format);
++ DWC_VPRINTF(format, args);
++ va_end(args);
++}
++
++int DWC_SPRINTF(char *buffer, char *format, ...)
++{
++ int retval;
++ va_list args;
++
++ va_start(args, format);
++ retval = vsprintf(buffer, format, args);
++ va_end(args);
++ return retval;
++}
++
++int DWC_SNPRINTF(char *buffer, int size, char *format, ...)
++{
++ int retval;
++ va_list args;
++
++ va_start(args, format);
++ retval = vsnprintf(buffer, size, format, args);
++ va_end(args);
++ return retval;
++}
++
++void __DWC_WARN(char *format, ...)
++{
++ va_list args;
++
++ va_start(args, format);
++ DWC_VPRINTF(format, args);
++ va_end(args);
++}
++
++void __DWC_ERROR(char *format, ...)
++{
++ va_list args;
++
++ va_start(args, format);
++ DWC_VPRINTF(format, args);
++ va_end(args);
++}
++
++void DWC_EXCEPTION(char *format, ...)
++{
++ va_list args;
++
++ va_start(args, format);
++ DWC_VPRINTF(format, args);
++ va_end(args);
++// BUG_ON(1); ???
++}
++
++#ifdef DEBUG
++void __DWC_DEBUG(char *format, ...)
++{
++ va_list args;
++
++ va_start(args, format);
++ DWC_VPRINTF(format, args);
++ va_end(args);
++}
++#endif
++
++
++/* dwc_mem.h */
++
++#if 0
++dwc_pool_t *DWC_DMA_POOL_CREATE(uint32_t size,
++ uint32_t align,
++ uint32_t alloc)
++{
++ struct dma_pool *pool = dma_pool_create("Pool", NULL,
++ size, align, alloc);
++ return (dwc_pool_t *)pool;
++}
++
++void DWC_DMA_POOL_DESTROY(dwc_pool_t *pool)
++{
++ dma_pool_destroy((struct dma_pool *)pool);
++}
++
++void *DWC_DMA_POOL_ALLOC(dwc_pool_t *pool, uint64_t *dma_addr)
++{
++// return dma_pool_alloc((struct dma_pool *)pool, GFP_KERNEL, dma_addr);
++ return dma_pool_alloc((struct dma_pool *)pool, M_WAITOK, dma_addr);
++}
++
++void *DWC_DMA_POOL_ZALLOC(dwc_pool_t *pool, uint64_t *dma_addr)
++{
++ void *vaddr = DWC_DMA_POOL_ALLOC(pool, dma_addr);
++ memset(..);
++}
++
++void DWC_DMA_POOL_FREE(dwc_pool_t *pool, void *vaddr, void *daddr)
++{
++ dma_pool_free(pool, vaddr, daddr);
++}
++#endif
++
++static void dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
++{
++ if (error)
++ return;
++ *(bus_addr_t *)arg = segs[0].ds_addr;
++}
++
++void *__DWC_DMA_ALLOC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr)
++{
++ dwc_dmactx_t *dma = (dwc_dmactx_t *)dma_ctx;
++ int error;
++
++ error = bus_dma_tag_create(
++#if __FreeBSD_version >= 700000
++ bus_get_dma_tag(dma->dev), /* parent */
++#else
++ NULL, /* parent */
++#endif
++ 4, 0, /* alignment, bounds */
++ BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
++ BUS_SPACE_MAXADDR, /* highaddr */
++ NULL, NULL, /* filter, filterarg */
++ size, /* maxsize */
++ 1, /* nsegments */
++ size, /* maxsegsize */
++ 0, /* flags */
++ NULL, /* lockfunc */
++ NULL, /* lockarg */
++ &dma->dma_tag);
++ if (error) {
++ device_printf(dma->dev, "%s: bus_dma_tag_create failed: %d\n",
++ __func__, error);
++ goto fail_0;
++ }
++
++ error = bus_dmamem_alloc(dma->dma_tag, &dma->dma_vaddr,
++ BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &dma->dma_map);
++ if (error) {
++ device_printf(dma->dev, "%s: bus_dmamem_alloc(%ju) failed: %d\n",
++ __func__, (uintmax_t)size, error);
++ goto fail_1;
++ }
++
++ dma->dma_paddr = 0;
++ error = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr, size,
++ dmamap_cb, &dma->dma_paddr, BUS_DMA_NOWAIT);
++ if (error || dma->dma_paddr == 0) {
++ device_printf(dma->dev, "%s: bus_dmamap_load failed: %d\n",
++ __func__, error);
++ goto fail_2;
++ }
++
++ *dma_addr = dma->dma_paddr;
++ return dma->dma_vaddr;
++
++fail_2:
++ bus_dmamap_unload(dma->dma_tag, dma->dma_map);
++fail_1:
++ bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
++ bus_dma_tag_destroy(dma->dma_tag);
++fail_0:
++ dma->dma_map = NULL;
++ dma->dma_tag = NULL;
++
++ return NULL;
++}
++
++void __DWC_DMA_FREE(void *dma_ctx, uint32_t size, void *virt_addr, dwc_dma_t dma_addr)
++{
++ dwc_dmactx_t *dma = (dwc_dmactx_t *)dma_ctx;
++
++ if (dma->dma_tag == NULL)
++ return;
++ if (dma->dma_map != NULL) {
++ bus_dmamap_sync(dma->dma_tag, dma->dma_map,
++ BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
++ bus_dmamap_unload(dma->dma_tag, dma->dma_map);
++ bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
++ dma->dma_map = NULL;
++ }
++
++ bus_dma_tag_destroy(dma->dma_tag);
++ dma->dma_tag = NULL;
++}
++
++void *__DWC_ALLOC(void *mem_ctx, uint32_t size)
++{
++ return malloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
++}
++
++void *__DWC_ALLOC_ATOMIC(void *mem_ctx, uint32_t size)
++{
++ return malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO);
++}
++
++void __DWC_FREE(void *mem_ctx, void *addr)
++{
++ free(addr, M_DEVBUF);
++}
++
++
++#ifdef DWC_CRYPTOLIB
++/* dwc_crypto.h */
++
++void DWC_RANDOM_BYTES(uint8_t *buffer, uint32_t length)
++{
++ get_random_bytes(buffer, length);
++}
++
++int DWC_AES_CBC(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t iv[16], uint8_t *out)
++{
++ struct crypto_blkcipher *tfm;
++ struct blkcipher_desc desc;
++ struct scatterlist sgd;
++ struct scatterlist sgs;
++
++ tfm = crypto_alloc_blkcipher("cbc(aes)", 0, CRYPTO_ALG_ASYNC);
++ if (tfm == NULL) {
++ printk("failed to load transform for aes CBC\n");
++ return -1;
++ }
++
++ crypto_blkcipher_setkey(tfm, key, keylen);
++ crypto_blkcipher_set_iv(tfm, iv, 16);
++
++ sg_init_one(&sgd, out, messagelen);
++ sg_init_one(&sgs, message, messagelen);
++
++ desc.tfm = tfm;
++ desc.flags = 0;
++
++ if (crypto_blkcipher_encrypt(&desc, &sgd, &sgs, messagelen)) {
++ crypto_free_blkcipher(tfm);
++ DWC_ERROR("AES CBC encryption failed");
++ return -1;
++ }
++
++ crypto_free_blkcipher(tfm);
++ return 0;
++}
++
++int DWC_SHA256(uint8_t *message, uint32_t len, uint8_t *out)
++{
++ struct crypto_hash *tfm;
++ struct hash_desc desc;
++ struct scatterlist sg;
++
++ tfm = crypto_alloc_hash("sha256", 0, CRYPTO_ALG_ASYNC);
++ if (IS_ERR(tfm)) {
++ DWC_ERROR("Failed to load transform for sha256: %ld", PTR_ERR(tfm));
++ return 0;
++ }
++ desc.tfm = tfm;
++ desc.flags = 0;
++
++ sg_init_one(&sg, message, len);
++ crypto_hash_digest(&desc, &sg, len, out);
++ crypto_free_hash(tfm);
++
++ return 1;
++}
++
++int DWC_HMAC_SHA256(uint8_t *message, uint32_t messagelen,
++ uint8_t *key, uint32_t keylen, uint8_t *out)
++{
++ struct crypto_hash *tfm;
++ struct hash_desc desc;
++ struct scatterlist sg;
++
++ tfm = crypto_alloc_hash("hmac(sha256)", 0, CRYPTO_ALG_ASYNC);
++ if (IS_ERR(tfm)) {
++ DWC_ERROR("Failed to load transform for hmac(sha256): %ld", PTR_ERR(tfm));
++ return 0;
++ }
++ desc.tfm = tfm;
++ desc.flags = 0;
++
++ sg_init_one(&sg, message, messagelen);
++ crypto_hash_setkey(tfm, key, keylen);
++ crypto_hash_digest(&desc, &sg, messagelen, out);
++ crypto_free_hash(tfm);
++
++ return 1;
++}
++
++#endif /* DWC_CRYPTOLIB */
++
++
++/* Byte Ordering Conversions */
++
++uint32_t DWC_CPU_TO_LE32(uint32_t *p)
++{
++#ifdef __LITTLE_ENDIAN
++ return *p;
++#else
++ uint8_t *u_p = (uint8_t *)p;
++
++ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
++#endif
++}
++
++uint32_t DWC_CPU_TO_BE32(uint32_t *p)
++{
++#ifdef __BIG_ENDIAN
++ return *p;
++#else
++ uint8_t *u_p = (uint8_t *)p;
++
++ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
++#endif
++}
++
++uint32_t DWC_LE32_TO_CPU(uint32_t *p)
++{
++#ifdef __LITTLE_ENDIAN
++ return *p;
++#else
++ uint8_t *u_p = (uint8_t *)p;
++
++ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
++#endif
++}
++
++uint32_t DWC_BE32_TO_CPU(uint32_t *p)
++{
++#ifdef __BIG_ENDIAN
++ return *p;
++#else
++ uint8_t *u_p = (uint8_t *)p;
++
++ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
++#endif
++}
++
++uint16_t DWC_CPU_TO_LE16(uint16_t *p)
++{
++#ifdef __LITTLE_ENDIAN
++ return *p;
++#else
++ uint8_t *u_p = (uint8_t *)p;
++ return (u_p[1] | (u_p[0] << 8));
++#endif
++}
++
++uint16_t DWC_CPU_TO_BE16(uint16_t *p)
++{
++#ifdef __BIG_ENDIAN
++ return *p;
++#else
++ uint8_t *u_p = (uint8_t *)p;
++ return (u_p[1] | (u_p[0] << 8));
++#endif
++}
++
++uint16_t DWC_LE16_TO_CPU(uint16_t *p)
++{
++#ifdef __LITTLE_ENDIAN
++ return *p;
++#else
++ uint8_t *u_p = (uint8_t *)p;
++ return (u_p[1] | (u_p[0] << 8));
++#endif
++}
++
++uint16_t DWC_BE16_TO_CPU(uint16_t *p)
++{
++#ifdef __BIG_ENDIAN
++ return *p;
++#else
++ uint8_t *u_p = (uint8_t *)p;
++ return (u_p[1] | (u_p[0] << 8));
++#endif
++}
++
++
++/* Registers */
++
++uint32_t DWC_READ_REG32(void *io_ctx, uint32_t volatile *reg)
++{
++ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
++ bus_size_t ior = (bus_size_t)reg;
++
++ return bus_space_read_4(io->iot, io->ioh, ior);
++}
++
++#if 0
++uint64_t DWC_READ_REG64(void *io_ctx, uint64_t volatile *reg)
++{
++ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
++ bus_size_t ior = (bus_size_t)reg;
++
++ return bus_space_read_8(io->iot, io->ioh, ior);
++}
++#endif
++
++void DWC_WRITE_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t value)
++{
++ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
++ bus_size_t ior = (bus_size_t)reg;
++
++ bus_space_write_4(io->iot, io->ioh, ior, value);
++}
++
++#if 0
++void DWC_WRITE_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t value)
++{
++ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
++ bus_size_t ior = (bus_size_t)reg;
++
++ bus_space_write_8(io->iot, io->ioh, ior, value);
++}
++#endif
++
++void DWC_MODIFY_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t clear_mask,
++ uint32_t set_mask)
++{
++ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
++ bus_size_t ior = (bus_size_t)reg;
++
++ bus_space_write_4(io->iot, io->ioh, ior,
++ (bus_space_read_4(io->iot, io->ioh, ior) &
++ ~clear_mask) | set_mask);
++}
++
++#if 0
++void DWC_MODIFY_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t clear_mask,
++ uint64_t set_mask)
++{
++ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
++ bus_size_t ior = (bus_size_t)reg;
++
++ bus_space_write_8(io->iot, io->ioh, ior,
++ (bus_space_read_8(io->iot, io->ioh, ior) &
++ ~clear_mask) | set_mask);
++}
++#endif
++
++
++/* Locking */
++
++dwc_spinlock_t *DWC_SPINLOCK_ALLOC(void)
++{
++ struct mtx *sl = DWC_ALLOC(sizeof(*sl));
++
++ if (!sl) {
++ DWC_ERROR("Cannot allocate memory for spinlock");
++ return NULL;
++ }
++
++ mtx_init(sl, "dw3spn", NULL, MTX_SPIN);
++ return (dwc_spinlock_t *)sl;
++}
++
++void DWC_SPINLOCK_FREE(dwc_spinlock_t *lock)
++{
++ struct mtx *sl = (struct mtx *)lock;
++
++ mtx_destroy(sl);
++ DWC_FREE(sl);
++}
++
++void DWC_SPINLOCK(dwc_spinlock_t *lock)
++{
++ mtx_lock_spin((struct mtx *)lock); // ???
++}
++
++void DWC_SPINUNLOCK(dwc_spinlock_t *lock)
++{
++ mtx_unlock_spin((struct mtx *)lock); // ???
++}
++
++void DWC_SPINLOCK_IRQSAVE(dwc_spinlock_t *lock, dwc_irqflags_t *flags)
++{
++ mtx_lock_spin((struct mtx *)lock);
++}
++
++void DWC_SPINUNLOCK_IRQRESTORE(dwc_spinlock_t *lock, dwc_irqflags_t flags)
++{
++ mtx_unlock_spin((struct mtx *)lock);
++}
++
++dwc_mutex_t *DWC_MUTEX_ALLOC(void)
++{
++ struct mtx *m;
++ dwc_mutex_t *mutex = (dwc_mutex_t *)DWC_ALLOC(sizeof(struct mtx));
++
++ if (!mutex) {
++ DWC_ERROR("Cannot allocate memory for mutex");
++ return NULL;
++ }
++
++ m = (struct mtx *)mutex;
++ mtx_init(m, "dw3mtx", NULL, MTX_DEF);
++ return mutex;
++}
++
++#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES))
++#else
++void DWC_MUTEX_FREE(dwc_mutex_t *mutex)
++{
++ mtx_destroy((struct mtx *)mutex);
++ DWC_FREE(mutex);
++}
++#endif
++
++void DWC_MUTEX_LOCK(dwc_mutex_t *mutex)
++{
++ struct mtx *m = (struct mtx *)mutex;
++
++ mtx_lock(m);
++}
++
++int DWC_MUTEX_TRYLOCK(dwc_mutex_t *mutex)
++{
++ struct mtx *m = (struct mtx *)mutex;
++
++ return mtx_trylock(m);
++}
++
++void DWC_MUTEX_UNLOCK(dwc_mutex_t *mutex)
++{
++ struct mtx *m = (struct mtx *)mutex;
++
++ mtx_unlock(m);
++}
++
++
++/* Timing */
++
++void DWC_UDELAY(uint32_t usecs)
++{
++ DELAY(usecs);
++}
++
++void DWC_MDELAY(uint32_t msecs)
++{
++ do {
++ DELAY(1000);
++ } while (--msecs);
++}
++
++void DWC_MSLEEP(uint32_t msecs)
++{
++ struct timeval tv;
++
++ tv.tv_sec = msecs / 1000;
++ tv.tv_usec = (msecs - tv.tv_sec * 1000) * 1000;
++ pause("dw3slp", tvtohz(&tv));
++}
++
++uint32_t DWC_TIME(void)
++{
++ struct timeval tv;
++
++ microuptime(&tv); // or getmicrouptime? (less precise, but faster)
++ return tv.tv_sec * 1000 + tv.tv_usec / 1000;
++}
++
++
++/* Timers */
++
++struct dwc_timer {
++ struct callout t;
++ char *name;
++ dwc_spinlock_t *lock;
++ dwc_timer_callback_t cb;
++ void *data;
++};
++
++dwc_timer_t *DWC_TIMER_ALLOC(char *name, dwc_timer_callback_t cb, void *data)
++{
++ dwc_timer_t *t = DWC_ALLOC(sizeof(*t));
++
++ if (!t) {
++ DWC_ERROR("Cannot allocate memory for timer");
++ return NULL;
++ }
++
++ callout_init(&t->t, 1);
++
++ t->name = DWC_STRDUP(name);
++ if (!t->name) {
++ DWC_ERROR("Cannot allocate memory for timer->name");
++ goto no_name;
++ }
++
++ t->lock = DWC_SPINLOCK_ALLOC();
++ if (!t->lock) {
++ DWC_ERROR("Cannot allocate memory for lock");
++ goto no_lock;
++ }
++
++ t->cb = cb;
++ t->data = data;
++
++ return t;
++
++ no_lock:
++ DWC_FREE(t->name);
++ no_name:
++ DWC_FREE(t);
++
++ return NULL;
++}
++
++void DWC_TIMER_FREE(dwc_timer_t *timer)
++{
++ callout_stop(&timer->t);
++ DWC_SPINLOCK_FREE(timer->lock);
++ DWC_FREE(timer->name);
++ DWC_FREE(timer);
++}
++
++void DWC_TIMER_SCHEDULE(dwc_timer_t *timer, uint32_t time)
++{
++ struct timeval tv;
++
++ tv.tv_sec = time / 1000;
++ tv.tv_usec = (time - tv.tv_sec * 1000) * 1000;
++ callout_reset(&timer->t, tvtohz(&tv), timer->cb, timer->data);
++}
++
++void DWC_TIMER_CANCEL(dwc_timer_t *timer)
++{
++ callout_stop(&timer->t);
++}
++
++
++/* Wait Queues */
++
++struct dwc_waitq {
++ struct mtx lock;
++ int abort;
++};
++
++dwc_waitq_t *DWC_WAITQ_ALLOC(void)
++{
++ dwc_waitq_t *wq = DWC_ALLOC(sizeof(*wq));
++
++ if (!wq) {
++ DWC_ERROR("Cannot allocate memory for waitqueue");
++ return NULL;
++ }
++
++ mtx_init(&wq->lock, "dw3wtq", NULL, MTX_DEF);
++ wq->abort = 0;
++
++ return wq;
++}
++
++void DWC_WAITQ_FREE(dwc_waitq_t *wq)
++{
++ mtx_destroy(&wq->lock);
++ DWC_FREE(wq);
++}
++
++int32_t DWC_WAITQ_WAIT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, void *data)
++{
++// intrmask_t ipl;
++ int result = 0;
++
++ mtx_lock(&wq->lock);
++// ipl = splbio();
++
++ /* Skip the sleep if already aborted or triggered */
++ if (!wq->abort && !cond(data)) {
++// splx(ipl);
++ result = msleep(wq, &wq->lock, PCATCH, "dw3wat", 0); // infinite timeout
++// ipl = splbio();
++ }
++
++ if (result == ERESTART) { // signaled - restart
++ result = -DWC_E_RESTART;
++
++ } else if (result == EINTR) { // signaled - interrupt
++ result = -DWC_E_ABORT;
++
++ } else if (wq->abort) {
++ result = -DWC_E_ABORT;
++
++ } else {
++ result = 0;
++ }
++
++ wq->abort = 0;
++// splx(ipl);
++ mtx_unlock(&wq->lock);
++ return result;
++}
++
++int32_t DWC_WAITQ_WAIT_TIMEOUT(dwc_waitq_t *wq, dwc_waitq_condition_t cond,
++ void *data, int32_t msecs)
++{
++ struct timeval tv, tv1, tv2;
++// intrmask_t ipl;
++ int result = 0;
++
++ tv.tv_sec = msecs / 1000;
++ tv.tv_usec = (msecs - tv.tv_sec * 1000) * 1000;
++
++ mtx_lock(&wq->lock);
++// ipl = splbio();
++
++ /* Skip the sleep if already aborted or triggered */
++ if (!wq->abort && !cond(data)) {
++// splx(ipl);
++ getmicrouptime(&tv1);
++ result = msleep(wq, &wq->lock, PCATCH, "dw3wto", tvtohz(&tv));
++ getmicrouptime(&tv2);
++// ipl = splbio();
++ }
++
++ if (result == 0) { // awoken
++ if (wq->abort) {
++ result = -DWC_E_ABORT;
++ } else {
++ tv2.tv_usec -= tv1.tv_usec;
++ if (tv2.tv_usec < 0) {
++ tv2.tv_usec += 1000000;
++ tv2.tv_sec--;
++ }
++
++ tv2.tv_sec -= tv1.tv_sec;
++ result = tv2.tv_sec * 1000 + tv2.tv_usec / 1000;
++ result = msecs - result;
++ if (result <= 0)
++ result = 1;
++ }
++ } else if (result == ERESTART) { // signaled - restart
++ result = -DWC_E_RESTART;
++
++ } else if (result == EINTR) { // signaled - interrupt
++ result = -DWC_E_ABORT;
++
++ } else { // timed out
++ result = -DWC_E_TIMEOUT;
++ }
++
++ wq->abort = 0;
++// splx(ipl);
++ mtx_unlock(&wq->lock);
++ return result;
++}
++
++void DWC_WAITQ_TRIGGER(dwc_waitq_t *wq)
++{
++ wakeup(wq);
++}
++
++void DWC_WAITQ_ABORT(dwc_waitq_t *wq)
++{
++// intrmask_t ipl;
++
++ mtx_lock(&wq->lock);
++// ipl = splbio();
++ wq->abort = 1;
++ wakeup(wq);
++// splx(ipl);
++ mtx_unlock(&wq->lock);
++}
++
++
++/* Threading */
++
++struct dwc_thread {
++ struct proc *proc;
++ int abort;
++};
++
++dwc_thread_t *DWC_THREAD_RUN(dwc_thread_function_t func, char *name, void *data)
++{
++ int retval;
++ dwc_thread_t *thread = DWC_ALLOC(sizeof(*thread));
++
++ if (!thread) {
++ return NULL;
++ }
++
++ thread->abort = 0;
++ retval = kthread_create((void (*)(void *))func, data, &thread->proc,
++ RFPROC | RFNOWAIT, 0, "%s", name);
++ if (retval) {
++ DWC_FREE(thread);
++ return NULL;
++ }
++
++ return thread;
++}
++
++int DWC_THREAD_STOP(dwc_thread_t *thread)
++{
++ int retval;
++
++ thread->abort = 1;
++ retval = tsleep(&thread->abort, 0, "dw3stp", 60 * hz);
++
++ if (retval == 0) {
++ /* DWC_THREAD_EXIT() will free the thread struct */
++ return 0;
++ }
++
++ /* NOTE: We leak the thread struct if thread doesn't die */
++
++ if (retval == EWOULDBLOCK) {
++ return -DWC_E_TIMEOUT;
++ }
++
++ return -DWC_E_UNKNOWN;
++}
++
++dwc_bool_t DWC_THREAD_SHOULD_STOP(dwc_thread_t *thread)
++{
++ return thread->abort;
++}
++
++void DWC_THREAD_EXIT(dwc_thread_t *thread)
++{
++ wakeup(&thread->abort);
++ DWC_FREE(thread);
++ kthread_exit(0);
++}
++
++
++/* tasklets
++ - Runs in interrupt context (cannot sleep)
++ - Each tasklet runs on a single CPU [ How can we ensure this on FreeBSD? Does it matter? ]
++ - Different tasklets can be running simultaneously on different CPUs [ shouldn't matter ]
++ */
++struct dwc_tasklet {
++ struct task t;
++ dwc_tasklet_callback_t cb;
++ void *data;
++};
++
++static void tasklet_callback(void *data, int pending) // what to do with pending ???
++{
++ dwc_tasklet_t *task = (dwc_tasklet_t *)data;
++
++ task->cb(task->data);
++}
++
++dwc_tasklet_t *DWC_TASK_ALLOC(char *name, dwc_tasklet_callback_t cb, void *data)
++{
++ dwc_tasklet_t *task = DWC_ALLOC(sizeof(*task));
++
++ if (task) {
++ task->cb = cb;
++ task->data = data;
++ TASK_INIT(&task->t, 0, tasklet_callback, task);
++ } else {
++ DWC_ERROR("Cannot allocate memory for tasklet");
++ }
++
++ return task;
++}
++
++void DWC_TASK_FREE(dwc_tasklet_t *task)
++{
++ taskqueue_drain(taskqueue_fast, &task->t); // ???
++ DWC_FREE(task);
++}
++
++void DWC_TASK_SCHEDULE(dwc_tasklet_t *task)
++{
++ /* Uses predefined system queue */
++ taskqueue_enqueue_fast(taskqueue_fast, &task->t);
++}
++
++
++/* workqueues
++ - Runs in process context (can sleep)
++ */
++typedef struct work_container {
++ dwc_work_callback_t cb;
++ void *data;
++ dwc_workq_t *wq;
++ char *name;
++ int hz;
++
++#ifdef DEBUG
++ DWC_CIRCLEQ_ENTRY(work_container) entry;
++#endif
++ struct task task;
++} work_container_t;
++
++#ifdef DEBUG
++DWC_CIRCLEQ_HEAD(work_container_queue, work_container);
++#endif
++
++struct dwc_workq {
++ struct taskqueue *taskq;
++ dwc_spinlock_t *lock;
++ dwc_waitq_t *waitq;
++ int pending;
++
++#ifdef DEBUG
++ struct work_container_queue entries;
++#endif
++};
++
++static void do_work(void *data, int pending) // what to do with pending ???
++{
++ work_container_t *container = (work_container_t *)data;
++ dwc_workq_t *wq = container->wq;
++ dwc_irqflags_t flags;
++
++ if (container->hz) {
++ pause("dw3wrk", container->hz);
++ }
++
++ container->cb(container->data);
++ DWC_DEBUG("Work done: %s, container=%p", container->name, container);
++
++ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
++
++#ifdef DEBUG
++ DWC_CIRCLEQ_REMOVE(&wq->entries, container, entry);
++#endif
++ if (container->name)
++ DWC_FREE(container->name);
++ DWC_FREE(container);
++ wq->pending--;
++ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
++ DWC_WAITQ_TRIGGER(wq->waitq);
++}
++
++static int work_done(void *data)
++{
++ dwc_workq_t *workq = (dwc_workq_t *)data;
++
++ return workq->pending == 0;
++}
++
++int DWC_WORKQ_WAIT_WORK_DONE(dwc_workq_t *workq, int timeout)
++{
++ return DWC_WAITQ_WAIT_TIMEOUT(workq->waitq, work_done, workq, timeout);
++}
++
++dwc_workq_t *DWC_WORKQ_ALLOC(char *name)
++{
++ dwc_workq_t *wq = DWC_ALLOC(sizeof(*wq));
++
++ if (!wq) {
++ DWC_ERROR("Cannot allocate memory for workqueue");
++ return NULL;
++ }
++
++ wq->taskq = taskqueue_create(name, M_NOWAIT, taskqueue_thread_enqueue, &wq->taskq);
++ if (!wq->taskq) {
++ DWC_ERROR("Cannot allocate memory for taskqueue");
++ goto no_taskq;
++ }
++
++ wq->pending = 0;
++
++ wq->lock = DWC_SPINLOCK_ALLOC();
++ if (!wq->lock) {
++ DWC_ERROR("Cannot allocate memory for spinlock");
++ goto no_lock;
++ }
++
++ wq->waitq = DWC_WAITQ_ALLOC();
++ if (!wq->waitq) {
++ DWC_ERROR("Cannot allocate memory for waitqueue");
++ goto no_waitq;
++ }
++
++ taskqueue_start_threads(&wq->taskq, 1, PWAIT, "%s taskq", "dw3tsk");
++
++#ifdef DEBUG
++ DWC_CIRCLEQ_INIT(&wq->entries);
++#endif
++ return wq;
++
++ no_waitq:
++ DWC_SPINLOCK_FREE(wq->lock);
++ no_lock:
++ taskqueue_free(wq->taskq);
++ no_taskq:
++ DWC_FREE(wq);
++
++ return NULL;
++}
++
++void DWC_WORKQ_FREE(dwc_workq_t *wq)
++{
++#ifdef DEBUG
++ dwc_irqflags_t flags;
++
++ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
++
++ if (wq->pending != 0) {
++ struct work_container *container;
++
++ DWC_ERROR("Destroying work queue with pending work");
++
++ DWC_CIRCLEQ_FOREACH(container, &wq->entries, entry) {
++ DWC_ERROR("Work %s still pending", container->name);
++ }
++ }
++
++ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
++#endif
++ DWC_WAITQ_FREE(wq->waitq);
++ DWC_SPINLOCK_FREE(wq->lock);
++ taskqueue_free(wq->taskq);
++ DWC_FREE(wq);
++}
++
++void DWC_WORKQ_SCHEDULE(dwc_workq_t *wq, dwc_work_callback_t cb, void *data,
++ char *format, ...)
++{
++ dwc_irqflags_t flags;
++ work_container_t *container;
++ static char name[128];
++ va_list args;
++
++ va_start(args, format);
++ DWC_VSNPRINTF(name, 128, format, args);
++ va_end(args);
++
++ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
++ wq->pending++;
++ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
++ DWC_WAITQ_TRIGGER(wq->waitq);
++
++ container = DWC_ALLOC_ATOMIC(sizeof(*container));
++ if (!container) {
++ DWC_ERROR("Cannot allocate memory for container");
++ return;
++ }
++
++ container->name = DWC_STRDUP(name);
++ if (!container->name) {
++ DWC_ERROR("Cannot allocate memory for container->name");
++ DWC_FREE(container);
++ return;
++ }
++
++ container->cb = cb;
++ container->data = data;
++ container->wq = wq;
++ container->hz = 0;
++
++ DWC_DEBUG("Queueing work: %s, container=%p", container->name, container);
++
++ TASK_INIT(&container->task, 0, do_work, container);
++
++#ifdef DEBUG
++ DWC_CIRCLEQ_INSERT_TAIL(&wq->entries, container, entry);
++#endif
++ taskqueue_enqueue_fast(wq->taskq, &container->task);
++}
++
++void DWC_WORKQ_SCHEDULE_DELAYED(dwc_workq_t *wq, dwc_work_callback_t cb,
++ void *data, uint32_t time, char *format, ...)
++{
++ dwc_irqflags_t flags;
++ work_container_t *container;
++ static char name[128];
++ struct timeval tv;
++ va_list args;
++
++ va_start(args, format);
++ DWC_VSNPRINTF(name, 128, format, args);
++ va_end(args);
++
++ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
++ wq->pending++;
++ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
++ DWC_WAITQ_TRIGGER(wq->waitq);
++
++ container = DWC_ALLOC_ATOMIC(sizeof(*container));
++ if (!container) {
++ DWC_ERROR("Cannot allocate memory for container");
++ return;
++ }
++
++ container->name = DWC_STRDUP(name);
++ if (!container->name) {
++ DWC_ERROR("Cannot allocate memory for container->name");
++ DWC_FREE(container);
++ return;
++ }
++
++ container->cb = cb;
++ container->data = data;
++ container->wq = wq;
++
++ tv.tv_sec = time / 1000;
++ tv.tv_usec = (time - tv.tv_sec * 1000) * 1000;
++ container->hz = tvtohz(&tv);
++
++ DWC_DEBUG("Queueing work: %s, container=%p", container->name, container);
++
++ TASK_INIT(&container->task, 0, do_work, container);
++
++#ifdef DEBUG
++ DWC_CIRCLEQ_INSERT_TAIL(&wq->entries, container, entry);
++#endif
++ taskqueue_enqueue_fast(wq->taskq, &container->task);
++}
++
++int DWC_WORKQ_PENDING(dwc_workq_t *wq)
++{
++ return wq->pending;
++}
+diff -Nur linux-4.1.3/drivers/usb/host/dwc_common_port/dwc_common_linux.c linux-xbian-rpi/drivers/usb/host/dwc_common_port/dwc_common_linux.c
+--- linux-4.1.3/drivers/usb/host/dwc_common_port/dwc_common_linux.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/usb/host/dwc_common_port/dwc_common_linux.c 2015-07-28 01:20:58.441170694 +0200
+@@ -0,0 +1,1434 @@
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/kthread.h>
++
++#ifdef DWC_CCLIB
++# include "dwc_cc.h"
++#endif
++
++#ifdef DWC_CRYPTOLIB
++# include "dwc_modpow.h"
++# include "dwc_dh.h"
++# include "dwc_crypto.h"
++#endif
++
++#ifdef DWC_NOTIFYLIB
++# include "dwc_notifier.h"
++#endif
++
++/* OS-Level Implementations */
++
++/* This is the Linux kernel implementation of the DWC platform library. */
++#include <linux/moduleparam.h>
++#include <linux/ctype.h>
++#include <linux/crypto.h>
++#include <linux/delay.h>
++#include <linux/device.h>
++#include <linux/dma-mapping.h>
++#include <linux/cdev.h>
++#include <linux/errno.h>
++#include <linux/interrupt.h>
++#include <linux/jiffies.h>
++#include <linux/list.h>
++#include <linux/pci.h>
++#include <linux/random.h>
++#include <linux/scatterlist.h>
++#include <linux/slab.h>
++#include <linux/stat.h>
++#include <linux/string.h>
++#include <linux/timer.h>
++#include <linux/usb.h>
++
++#include <linux/version.h>
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)
++# include <linux/usb/gadget.h>
++#else
++# include <linux/usb_gadget.h>
++#endif
++
++#include <asm/io.h>
++#include <asm/page.h>
++#include <asm/uaccess.h>
++#include <asm/unaligned.h>
++
++#include "dwc_os.h"
++#include "dwc_list.h"
++
++
++/* MISC */
++
++void *DWC_MEMSET(void *dest, uint8_t byte, uint32_t size)
++{
++ return memset(dest, byte, size);
++}
++
++void *DWC_MEMCPY(void *dest, void const *src, uint32_t size)
++{
++ return memcpy(dest, src, size);
++}
++
++void *DWC_MEMMOVE(void *dest, void *src, uint32_t size)
++{
++ return memmove(dest, src, size);
++}
++
++int DWC_MEMCMP(void *m1, void *m2, uint32_t size)
++{
++ return memcmp(m1, m2, size);
++}
++
++int DWC_STRNCMP(void *s1, void *s2, uint32_t size)
++{
++ return strncmp(s1, s2, size);
++}
++
++int DWC_STRCMP(void *s1, void *s2)
++{
++ return strcmp(s1, s2);
++}
++
++int DWC_STRLEN(char const *str)
++{
++ return strlen(str);
++}
++
++char *DWC_STRCPY(char *to, char const *from)
++{
++ return strcpy(to, from);
++}
++
++char *DWC_STRDUP(char const *str)
++{
++ int len = DWC_STRLEN(str) + 1;
++ char *new = DWC_ALLOC_ATOMIC(len);
++
++ if (!new) {
++ return NULL;
++ }
++
++ DWC_MEMCPY(new, str, len);
++ return new;
++}
++
++int DWC_ATOI(const char *str, int32_t *value)
++{
++ char *end = NULL;
++
++ *value = simple_strtol(str, &end, 0);
++ if (*end == '\0') {
++ return 0;
++ }
++
++ return -1;
++}
++
++int DWC_ATOUI(const char *str, uint32_t *value)
++{
++ char *end = NULL;
++
++ *value = simple_strtoul(str, &end, 0);
++ if (*end == '\0') {
++ return 0;
++ }
++
++ return -1;
++}
++
++
++#ifdef DWC_UTFLIB
++/* From usbstring.c */
++
++int DWC_UTF8_TO_UTF16LE(uint8_t const *s, uint16_t *cp, unsigned len)
++{
++ int count = 0;
++ u8 c;
++ u16 uchar;
++
++ /* this insists on correct encodings, though not minimal ones.
++ * BUT it currently rejects legit 4-byte UTF-8 code points,
++ * which need surrogate pairs. (Unicode 3.1 can use them.)
++ */
++ while (len != 0 && (c = (u8) *s++) != 0) {
++ if (unlikely(c & 0x80)) {
++ // 2-byte sequence:
++ // 00000yyyyyxxxxxx = 110yyyyy 10xxxxxx
++ if ((c & 0xe0) == 0xc0) {
++ uchar = (c & 0x1f) << 6;
++
++ c = (u8) *s++;
++ if ((c & 0xc0) != 0xc0)
++ goto fail;
++ c &= 0x3f;
++ uchar |= c;
++
++ // 3-byte sequence (most CJKV characters):
++ // zzzzyyyyyyxxxxxx = 1110zzzz 10yyyyyy 10xxxxxx
++ } else if ((c & 0xf0) == 0xe0) {
++ uchar = (c & 0x0f) << 12;
++
++ c = (u8) *s++;
++ if ((c & 0xc0) != 0xc0)
++ goto fail;
++ c &= 0x3f;
++ uchar |= c << 6;
++
++ c = (u8) *s++;
++ if ((c & 0xc0) != 0xc0)
++ goto fail;
++ c &= 0x3f;
++ uchar |= c;
++
++ /* no bogus surrogates */
++ if (0xd800 <= uchar && uchar <= 0xdfff)
++ goto fail;
++
++ // 4-byte sequence (surrogate pairs, currently rare):
++ // 11101110wwwwzzzzyy + 110111yyyyxxxxxx
++ // = 11110uuu 10uuzzzz 10yyyyyy 10xxxxxx
++ // (uuuuu = wwww + 1)
++ // FIXME accept the surrogate code points (only)
++ } else
++ goto fail;
++ } else
++ uchar = c;
++ put_unaligned (cpu_to_le16 (uchar), cp++);
++ count++;
++ len--;
++ }
++ return count;
++fail:
++ return -1;
++}
++#endif /* DWC_UTFLIB */
++
++
++/* dwc_debug.h */
++
++dwc_bool_t DWC_IN_IRQ(void)
++{
++ return in_irq();
++}
++
++dwc_bool_t DWC_IN_BH(void)
++{
++ return in_softirq();
++}
++
++void DWC_VPRINTF(char *format, va_list args)
++{
++ vprintk(format, args);
++}
++
++int DWC_VSNPRINTF(char *str, int size, char *format, va_list args)
++{
++ return vsnprintf(str, size, format, args);
++}
++
++void DWC_PRINTF(char *format, ...)
++{
++ va_list args;
++
++ va_start(args, format);
++ DWC_VPRINTF(format, args);
++ va_end(args);
++}
++
++int DWC_SPRINTF(char *buffer, char *format, ...)
++{
++ int retval;
++ va_list args;
++
++ va_start(args, format);
++ retval = vsprintf(buffer, format, args);
++ va_end(args);
++ return retval;
++}
++
++int DWC_SNPRINTF(char *buffer, int size, char *format, ...)
++{
++ int retval;
++ va_list args;
++
++ va_start(args, format);
++ retval = vsnprintf(buffer, size, format, args);
++ va_end(args);
++ return retval;
++}
++
++void __DWC_WARN(char *format, ...)
++{
++ va_list args;
++
++ va_start(args, format);
++ DWC_PRINTF(KERN_WARNING);
++ DWC_VPRINTF(format, args);
++ va_end(args);
++}
++
++void __DWC_ERROR(char *format, ...)
++{
++ va_list args;
++
++ va_start(args, format);
++ DWC_PRINTF(KERN_ERR);
++ DWC_VPRINTF(format, args);
++ va_end(args);
++}
++
++void DWC_EXCEPTION(char *format, ...)
++{
++ va_list args;
++
++ va_start(args, format);
++ DWC_PRINTF(KERN_ERR);
++ DWC_VPRINTF(format, args);
++ va_end(args);
++ BUG_ON(1);
++}
++
++#ifdef DEBUG
++void __DWC_DEBUG(char *format, ...)
++{
++ va_list args;
++
++ va_start(args, format);
++ DWC_PRINTF(KERN_DEBUG);
++ DWC_VPRINTF(format, args);
++ va_end(args);
++}
++#endif
++
++
++/* dwc_mem.h */
++
++#if 0
++dwc_pool_t *DWC_DMA_POOL_CREATE(uint32_t size,
++ uint32_t align,
++ uint32_t alloc)
++{
++ struct dma_pool *pool = dma_pool_create("Pool", NULL,
++ size, align, alloc);
++ return (dwc_pool_t *)pool;
++}
++
++void DWC_DMA_POOL_DESTROY(dwc_pool_t *pool)
++{
++ dma_pool_destroy((struct dma_pool *)pool);
++}
++
++void *DWC_DMA_POOL_ALLOC(dwc_pool_t *pool, uint64_t *dma_addr)
++{
++ return dma_pool_alloc((struct dma_pool *)pool, GFP_KERNEL, dma_addr);
++}
++
++void *DWC_DMA_POOL_ZALLOC(dwc_pool_t *pool, uint64_t *dma_addr)
++{
++ void *vaddr = DWC_DMA_POOL_ALLOC(pool, dma_addr);
++ memset(..);
++}
++
++void DWC_DMA_POOL_FREE(dwc_pool_t *pool, void *vaddr, void *daddr)
++{
++ dma_pool_free(pool, vaddr, daddr);
++}
++#endif
++
++void *__DWC_DMA_ALLOC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr)
++{
++#ifdef xxCOSIM /* Only works for 32-bit cosim */
++ void *buf = dma_alloc_coherent(dma_ctx, (size_t)size, dma_addr, GFP_KERNEL);
++#else
++ void *buf = dma_alloc_coherent(dma_ctx, (size_t)size, dma_addr, GFP_KERNEL | GFP_DMA32);
++#endif
++ if (!buf) {
++ return NULL;
++ }
++
++ memset(buf, 0, (size_t)size);
++ return buf;
++}
++
++void *__DWC_DMA_ALLOC_ATOMIC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr)
++{
++ void *buf = dma_alloc_coherent(NULL, (size_t)size, dma_addr, GFP_ATOMIC);
++ if (!buf) {
++ return NULL;
++ }
++ memset(buf, 0, (size_t)size);
++ return buf;
++}
++
++void __DWC_DMA_FREE(void *dma_ctx, uint32_t size, void *virt_addr, dwc_dma_t dma_addr)
++{
++ dma_free_coherent(dma_ctx, size, virt_addr, dma_addr);
++}
++
++void *__DWC_ALLOC(void *mem_ctx, uint32_t size)
++{
++ return kzalloc(size, GFP_KERNEL);
++}
++
++void *__DWC_ALLOC_ATOMIC(void *mem_ctx, uint32_t size)
++{
++ return kzalloc(size, GFP_ATOMIC);
++}
++
++void __DWC_FREE(void *mem_ctx, void *addr)
++{
++ kfree(addr);
++}
++
++
++#ifdef DWC_CRYPTOLIB
++/* dwc_crypto.h */
++
++void DWC_RANDOM_BYTES(uint8_t *buffer, uint32_t length)
++{
++ get_random_bytes(buffer, length);
++}
++
++int DWC_AES_CBC(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t iv[16], uint8_t *out)
++{
++ struct crypto_blkcipher *tfm;
++ struct blkcipher_desc desc;
++ struct scatterlist sgd;
++ struct scatterlist sgs;
++
++ tfm = crypto_alloc_blkcipher("cbc(aes)", 0, CRYPTO_ALG_ASYNC);
++ if (tfm == NULL) {
++ printk("failed to load transform for aes CBC\n");
++ return -1;
++ }
++
++ crypto_blkcipher_setkey(tfm, key, keylen);
++ crypto_blkcipher_set_iv(tfm, iv, 16);
++
++ sg_init_one(&sgd, out, messagelen);
++ sg_init_one(&sgs, message, messagelen);
++
++ desc.tfm = tfm;
++ desc.flags = 0;
++
++ if (crypto_blkcipher_encrypt(&desc, &sgd, &sgs, messagelen)) {
++ crypto_free_blkcipher(tfm);
++ DWC_ERROR("AES CBC encryption failed");
++ return -1;
++ }
++
++ crypto_free_blkcipher(tfm);
++ return 0;
++}
++
++int DWC_SHA256(uint8_t *message, uint32_t len, uint8_t *out)
++{
++ struct crypto_hash *tfm;
++ struct hash_desc desc;
++ struct scatterlist sg;
++
++ tfm = crypto_alloc_hash("sha256", 0, CRYPTO_ALG_ASYNC);
++ if (IS_ERR(tfm)) {
++ DWC_ERROR("Failed to load transform for sha256: %ld\n", PTR_ERR(tfm));
++ return 0;
++ }
++ desc.tfm = tfm;
++ desc.flags = 0;
++
++ sg_init_one(&sg, message, len);
++ crypto_hash_digest(&desc, &sg, len, out);
++ crypto_free_hash(tfm);
++
++ return 1;
++}
++
++int DWC_HMAC_SHA256(uint8_t *message, uint32_t messagelen,
++ uint8_t *key, uint32_t keylen, uint8_t *out)
++{
++ struct crypto_hash *tfm;
++ struct hash_desc desc;
++ struct scatterlist sg;
++
++ tfm = crypto_alloc_hash("hmac(sha256)", 0, CRYPTO_ALG_ASYNC);
++ if (IS_ERR(tfm)) {
++ DWC_ERROR("Failed to load transform for hmac(sha256): %ld\n", PTR_ERR(tfm));
++ return 0;
++ }
++ desc.tfm = tfm;
++ desc.flags = 0;
++
++ sg_init_one(&sg, message, messagelen);
++ crypto_hash_setkey(tfm, key, keylen);
++ crypto_hash_digest(&desc, &sg, messagelen, out);
++ crypto_free_hash(tfm);
++
++ return 1;
++}
++#endif /* DWC_CRYPTOLIB */
++
++
++/* Byte Ordering Conversions */
++
++uint32_t DWC_CPU_TO_LE32(uint32_t *p)
++{
++#ifdef __LITTLE_ENDIAN
++ return *p;
++#else
++ uint8_t *u_p = (uint8_t *)p;
++
++ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
++#endif
++}
++
++uint32_t DWC_CPU_TO_BE32(uint32_t *p)
++{
++#ifdef __BIG_ENDIAN
++ return *p;
++#else
++ uint8_t *u_p = (uint8_t *)p;
++
++ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
++#endif
++}
++
++uint32_t DWC_LE32_TO_CPU(uint32_t *p)
++{
++#ifdef __LITTLE_ENDIAN
++ return *p;
++#else
++ uint8_t *u_p = (uint8_t *)p;
++
++ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
++#endif
++}
++
++uint32_t DWC_BE32_TO_CPU(uint32_t *p)
++{
++#ifdef __BIG_ENDIAN
++ return *p;
++#else
++ uint8_t *u_p = (uint8_t *)p;
++
++ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
++#endif
++}
++
++uint16_t DWC_CPU_TO_LE16(uint16_t *p)
++{
++#ifdef __LITTLE_ENDIAN
++ return *p;
++#else
++ uint8_t *u_p = (uint8_t *)p;
++ return (u_p[1] | (u_p[0] << 8));
++#endif
++}
++
++uint16_t DWC_CPU_TO_BE16(uint16_t *p)
++{
++#ifdef __BIG_ENDIAN
++ return *p;
++#else
++ uint8_t *u_p = (uint8_t *)p;
++ return (u_p[1] | (u_p[0] << 8));
++#endif
++}
++
++uint16_t DWC_LE16_TO_CPU(uint16_t *p)
++{
++#ifdef __LITTLE_ENDIAN
++ return *p;
++#else
++ uint8_t *u_p = (uint8_t *)p;
++ return (u_p[1] | (u_p[0] << 8));
++#endif
++}
++
++uint16_t DWC_BE16_TO_CPU(uint16_t *p)
++{
++#ifdef __BIG_ENDIAN
++ return *p;
++#else
++ uint8_t *u_p = (uint8_t *)p;
++ return (u_p[1] | (u_p[0] << 8));
++#endif
++}
++
++
++/* Registers */
++
++uint32_t DWC_READ_REG32(uint32_t volatile *reg)
++{
++ return readl(reg);
++}
++
++#if 0
++uint64_t DWC_READ_REG64(uint64_t volatile *reg)
++{
++}
++#endif
++
++void DWC_WRITE_REG32(uint32_t volatile *reg, uint32_t value)
++{
++ writel(value, reg);
++}
++
++#if 0
++void DWC_WRITE_REG64(uint64_t volatile *reg, uint64_t value)
++{
++}
++#endif
++
++void DWC_MODIFY_REG32(uint32_t volatile *reg, uint32_t clear_mask, uint32_t set_mask)
++{
++ writel((readl(reg) & ~clear_mask) | set_mask, reg);
++}
++
++#if 0
++void DWC_MODIFY_REG64(uint64_t volatile *reg, uint64_t clear_mask, uint64_t set_mask)
++{
++}
++#endif
++
++
++/* Locking */
++
++dwc_spinlock_t *DWC_SPINLOCK_ALLOC(void)
++{
++ spinlock_t *sl = (spinlock_t *)1;
++
++#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP)
++ sl = DWC_ALLOC(sizeof(*sl));
++ if (!sl) {
++ DWC_ERROR("Cannot allocate memory for spinlock\n");
++ return NULL;
++ }
++
++ spin_lock_init(sl);
++#endif
++ return (dwc_spinlock_t *)sl;
++}
++
++void DWC_SPINLOCK_FREE(dwc_spinlock_t *lock)
++{
++#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP)
++ DWC_FREE(lock);
++#endif
++}
++
++void DWC_SPINLOCK(dwc_spinlock_t *lock)
++{
++#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP)
++ spin_lock((spinlock_t *)lock);
++#endif
++}
++
++void DWC_SPINUNLOCK(dwc_spinlock_t *lock)
++{
++#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP)
++ spin_unlock((spinlock_t *)lock);
++#endif
++}
++
++void DWC_SPINLOCK_IRQSAVE(dwc_spinlock_t *lock, dwc_irqflags_t *flags)
++{
++ dwc_irqflags_t f;
++
++#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP)
++ spin_lock_irqsave((spinlock_t *)lock, f);
++#else
++ local_irq_save(f);
++#endif
++ *flags = f;
++}
++
++void DWC_SPINUNLOCK_IRQRESTORE(dwc_spinlock_t *lock, dwc_irqflags_t flags)
++{
++#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP)
++ spin_unlock_irqrestore((spinlock_t *)lock, flags);
++#else
++ local_irq_restore(flags);
++#endif
++}
++
++dwc_mutex_t *DWC_MUTEX_ALLOC(void)
++{
++ struct mutex *m;
++ dwc_mutex_t *mutex = (dwc_mutex_t *)DWC_ALLOC(sizeof(struct mutex));
++
++ if (!mutex) {
++ DWC_ERROR("Cannot allocate memory for mutex\n");
++ return NULL;
++ }
++
++ m = (struct mutex *)mutex;
++ mutex_init(m);
++ return mutex;
++}
++
++#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES))
++#else
++void DWC_MUTEX_FREE(dwc_mutex_t *mutex)
++{
++ mutex_destroy((struct mutex *)mutex);
++ DWC_FREE(mutex);
++}
++#endif
++
++void DWC_MUTEX_LOCK(dwc_mutex_t *mutex)
++{
++ struct mutex *m = (struct mutex *)mutex;
++ mutex_lock(m);
++}
++
++int DWC_MUTEX_TRYLOCK(dwc_mutex_t *mutex)
++{
++ struct mutex *m = (struct mutex *)mutex;
++ return mutex_trylock(m);
++}
++
++void DWC_MUTEX_UNLOCK(dwc_mutex_t *mutex)
++{
++ struct mutex *m = (struct mutex *)mutex;
++ mutex_unlock(m);
++}
++
++
++/* Timing */
++
++void DWC_UDELAY(uint32_t usecs)
++{
++ udelay(usecs);
++}
++
++void DWC_MDELAY(uint32_t msecs)
++{
++ mdelay(msecs);
++}
++
++void DWC_MSLEEP(uint32_t msecs)
++{
++ msleep(msecs);
++}
++
++uint32_t DWC_TIME(void)
++{
++ return jiffies_to_msecs(jiffies);
++}
++
++
++/* Timers */
++
++struct dwc_timer {
++ struct timer_list *t;
++ char *name;
++ dwc_timer_callback_t cb;
++ void *data;
++ uint8_t scheduled;
++ dwc_spinlock_t *lock;
++};
++
++static void timer_callback(unsigned long data)
++{
++ dwc_timer_t *timer = (dwc_timer_t *)data;
++ dwc_irqflags_t flags;
++
++ DWC_SPINLOCK_IRQSAVE(timer->lock, &flags);
++ timer->scheduled = 0;
++ DWC_SPINUNLOCK_IRQRESTORE(timer->lock, flags);
++ DWC_DEBUGC("Timer %s callback", timer->name);
++ timer->cb(timer->data);
++}
++
++dwc_timer_t *DWC_TIMER_ALLOC(char *name, dwc_timer_callback_t cb, void *data)
++{
++ dwc_timer_t *t = DWC_ALLOC(sizeof(*t));
++
++ if (!t) {
++ DWC_ERROR("Cannot allocate memory for timer");
++ return NULL;
++ }
++
++ t->t = DWC_ALLOC(sizeof(*t->t));
++ if (!t->t) {
++ DWC_ERROR("Cannot allocate memory for timer->t");
++ goto no_timer;
++ }
++
++ t->name = DWC_STRDUP(name);
++ if (!t->name) {
++ DWC_ERROR("Cannot allocate memory for timer->name");
++ goto no_name;
++ }
++
++#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_SPINLOCK))
++ DWC_SPINLOCK_ALLOC_LINUX_DEBUG(t->lock);
++#else
++ t->lock = DWC_SPINLOCK_ALLOC();
++#endif
++ if (!t->lock) {
++ DWC_ERROR("Cannot allocate memory for lock");
++ goto no_lock;
++ }
++
++ t->scheduled = 0;
++ t->t->base = &boot_tvec_bases;
++ t->t->expires = jiffies;
++ setup_timer(t->t, timer_callback, (unsigned long)t);
++
++ t->cb = cb;
++ t->data = data;
++
++ return t;
++
++ no_lock:
++ DWC_FREE(t->name);
++ no_name:
++ DWC_FREE(t->t);
++ no_timer:
++ DWC_FREE(t);
++ return NULL;
++}
++
++void DWC_TIMER_FREE(dwc_timer_t *timer)
++{
++ dwc_irqflags_t flags;
++
++ DWC_SPINLOCK_IRQSAVE(timer->lock, &flags);
++
++ if (timer->scheduled) {
++ del_timer(timer->t);
++ timer->scheduled = 0;
++ }
++
++ DWC_SPINUNLOCK_IRQRESTORE(timer->lock, flags);
++ DWC_SPINLOCK_FREE(timer->lock);
++ DWC_FREE(timer->t);
++ DWC_FREE(timer->name);
++ DWC_FREE(timer);
++}
++
++void DWC_TIMER_SCHEDULE(dwc_timer_t *timer, uint32_t time)
++{
++ dwc_irqflags_t flags;
++
++ DWC_SPINLOCK_IRQSAVE(timer->lock, &flags);
++
++ if (!timer->scheduled) {
++ timer->scheduled = 1;
++ DWC_DEBUGC("Scheduling timer %s to expire in +%d msec", timer->name, time);
++ timer->t->expires = jiffies + msecs_to_jiffies(time);
++ add_timer(timer->t);
++ } else {
++ DWC_DEBUGC("Modifying timer %s to expire in +%d msec", timer->name, time);
++ mod_timer(timer->t, jiffies + msecs_to_jiffies(time));
++ }
++
++ DWC_SPINUNLOCK_IRQRESTORE(timer->lock, flags);
++}
++
++void DWC_TIMER_CANCEL(dwc_timer_t *timer)
++{
++ del_timer(timer->t);
++}
++
++
++/* Wait Queues */
++
++struct dwc_waitq {
++ wait_queue_head_t queue;
++ int abort;
++};
++
++dwc_waitq_t *DWC_WAITQ_ALLOC(void)
++{
++ dwc_waitq_t *wq = DWC_ALLOC(sizeof(*wq));
++
++ if (!wq) {
++ DWC_ERROR("Cannot allocate memory for waitqueue\n");
++ return NULL;
++ }
++
++ init_waitqueue_head(&wq->queue);
++ wq->abort = 0;
++ return wq;
++}
++
++void DWC_WAITQ_FREE(dwc_waitq_t *wq)
++{
++ DWC_FREE(wq);
++}
++
++int32_t DWC_WAITQ_WAIT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, void *data)
++{
++ int result = wait_event_interruptible(wq->queue,
++ cond(data) || wq->abort);
++ if (result == -ERESTARTSYS) {
++ wq->abort = 0;
++ return -DWC_E_RESTART;
++ }
++
++ if (wq->abort == 1) {
++ wq->abort = 0;
++ return -DWC_E_ABORT;
++ }
++
++ wq->abort = 0;
++
++ if (result == 0) {
++ return 0;
++ }
++
++ return -DWC_E_UNKNOWN;
++}
++
++int32_t DWC_WAITQ_WAIT_TIMEOUT(dwc_waitq_t *wq, dwc_waitq_condition_t cond,
++ void *data, int32_t msecs)
++{
++ int32_t tmsecs;
++ int result = wait_event_interruptible_timeout(wq->queue,
++ cond(data) || wq->abort,
++ msecs_to_jiffies(msecs));
++ if (result == -ERESTARTSYS) {
++ wq->abort = 0;
++ return -DWC_E_RESTART;
++ }
++
++ if (wq->abort == 1) {
++ wq->abort = 0;
++ return -DWC_E_ABORT;
++ }
++
++ wq->abort = 0;
++
++ if (result > 0) {
++ tmsecs = jiffies_to_msecs(result);
++ if (!tmsecs) {
++ return 1;
++ }
++
++ return tmsecs;
++ }
++
++ if (result == 0) {
++ return -DWC_E_TIMEOUT;
++ }
++
++ return -DWC_E_UNKNOWN;
++}
++
++void DWC_WAITQ_TRIGGER(dwc_waitq_t *wq)
++{
++ wq->abort = 0;
++ wake_up_interruptible(&wq->queue);
++}
++
++void DWC_WAITQ_ABORT(dwc_waitq_t *wq)
++{
++ wq->abort = 1;
++ wake_up_interruptible(&wq->queue);
++}
++
++
++/* Threading */
++
++dwc_thread_t *DWC_THREAD_RUN(dwc_thread_function_t func, char *name, void *data)
++{
++ struct task_struct *thread = kthread_run(func, data, name);
++
++ if (thread == ERR_PTR(-ENOMEM)) {
++ return NULL;
++ }
++
++ return (dwc_thread_t *)thread;
++}
++
++int DWC_THREAD_STOP(dwc_thread_t *thread)
++{
++ return kthread_stop((struct task_struct *)thread);
++}
++
++dwc_bool_t DWC_THREAD_SHOULD_STOP(void)
++{
++ return kthread_should_stop();
++}
++
++
++/* tasklets
++ - run in interrupt context (cannot sleep)
++ - each tasklet runs on a single CPU
++ - different tasklets can be running simultaneously on different CPUs
++ */
++struct dwc_tasklet {
++ struct tasklet_struct t;
++ dwc_tasklet_callback_t cb;
++ void *data;
++};
++
++static void tasklet_callback(unsigned long data)
++{
++ dwc_tasklet_t *t = (dwc_tasklet_t *)data;
++ t->cb(t->data);
++}
++
++dwc_tasklet_t *DWC_TASK_ALLOC(char *name, dwc_tasklet_callback_t cb, void *data)
++{
++ dwc_tasklet_t *t = DWC_ALLOC(sizeof(*t));
++
++ if (t) {
++ t->cb = cb;
++ t->data = data;
++ tasklet_init(&t->t, tasklet_callback, (unsigned long)t);
++ } else {
++ DWC_ERROR("Cannot allocate memory for tasklet\n");
++ }
++
++ return t;
++}
++
++void DWC_TASK_FREE(dwc_tasklet_t *task)
++{
++ DWC_FREE(task);
++}
++
++void DWC_TASK_SCHEDULE(dwc_tasklet_t *task)
++{
++ tasklet_schedule(&task->t);
++}
++
++void DWC_TASK_HI_SCHEDULE(dwc_tasklet_t *task)
++{
++ tasklet_hi_schedule(&task->t);
++}
++
++
++/* workqueues
++ - run in process context (can sleep)
++ */
++typedef struct work_container {
++ dwc_work_callback_t cb;
++ void *data;
++ dwc_workq_t *wq;
++ char *name;
++
++#ifdef DEBUG
++ DWC_CIRCLEQ_ENTRY(work_container) entry;
++#endif
++ struct delayed_work work;
++} work_container_t;
++
++#ifdef DEBUG
++DWC_CIRCLEQ_HEAD(work_container_queue, work_container);
++#endif
++
++struct dwc_workq {
++ struct workqueue_struct *wq;
++ dwc_spinlock_t *lock;
++ dwc_waitq_t *waitq;
++ int pending;
++
++#ifdef DEBUG
++ struct work_container_queue entries;
++#endif
++};
++
++static void do_work(struct work_struct *work)
++{
++ dwc_irqflags_t flags;
++ struct delayed_work *dw = container_of(work, struct delayed_work, work);
++ work_container_t *container = container_of(dw, struct work_container, work);
++ dwc_workq_t *wq = container->wq;
++
++ container->cb(container->data);
++
++#ifdef DEBUG
++ DWC_CIRCLEQ_REMOVE(&wq->entries, container, entry);
++#endif
++ DWC_DEBUGC("Work done: %s, container=%p", container->name, container);
++ if (container->name) {
++ DWC_FREE(container->name);
++ }
++ DWC_FREE(container);
++
++ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
++ wq->pending--;
++ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
++ DWC_WAITQ_TRIGGER(wq->waitq);
++}
++
++static int work_done(void *data)
++{
++ dwc_workq_t *workq = (dwc_workq_t *)data;
++ return workq->pending == 0;
++}
++
++int DWC_WORKQ_WAIT_WORK_DONE(dwc_workq_t *workq, int timeout)
++{
++ return DWC_WAITQ_WAIT_TIMEOUT(workq->waitq, work_done, workq, timeout);
++}
++
++dwc_workq_t *DWC_WORKQ_ALLOC(char *name)
++{
++ dwc_workq_t *wq = DWC_ALLOC(sizeof(*wq));
++
++ if (!wq) {
++ return NULL;
++ }
++
++ wq->wq = create_singlethread_workqueue(name);
++ if (!wq->wq) {
++ goto no_wq;
++ }
++
++ wq->pending = 0;
++
++#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_SPINLOCK))
++ DWC_SPINLOCK_ALLOC_LINUX_DEBUG(wq->lock);
++#else
++ wq->lock = DWC_SPINLOCK_ALLOC();
++#endif
++ if (!wq->lock) {
++ goto no_lock;
++ }
++
++ wq->waitq = DWC_WAITQ_ALLOC();
++ if (!wq->waitq) {
++ goto no_waitq;
++ }
++
++#ifdef DEBUG
++ DWC_CIRCLEQ_INIT(&wq->entries);
++#endif
++ return wq;
++
++ no_waitq:
++ DWC_SPINLOCK_FREE(wq->lock);
++ no_lock:
++ destroy_workqueue(wq->wq);
++ no_wq:
++ DWC_FREE(wq);
++
++ return NULL;
++}
++
++void DWC_WORKQ_FREE(dwc_workq_t *wq)
++{
++#ifdef DEBUG
++ if (wq->pending != 0) {
++ struct work_container *wc;
++ DWC_ERROR("Destroying work queue with pending work");
++ DWC_CIRCLEQ_FOREACH(wc, &wq->entries, entry) {
++ DWC_ERROR("Work %s still pending", wc->name);
++ }
++ }
++#endif
++ destroy_workqueue(wq->wq);
++ DWC_SPINLOCK_FREE(wq->lock);
++ DWC_WAITQ_FREE(wq->waitq);
++ DWC_FREE(wq);
++}
++
++void DWC_WORKQ_SCHEDULE(dwc_workq_t *wq, dwc_work_callback_t cb, void *data,
++ char *format, ...)
++{
++ dwc_irqflags_t flags;
++ work_container_t *container;
++ static char name[128];
++ va_list args;
++
++ va_start(args, format);
++ DWC_VSNPRINTF(name, 128, format, args);
++ va_end(args);
++
++ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
++ wq->pending++;
++ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
++ DWC_WAITQ_TRIGGER(wq->waitq);
++
++ container = DWC_ALLOC_ATOMIC(sizeof(*container));
++ if (!container) {
++ DWC_ERROR("Cannot allocate memory for container\n");
++ return;
++ }
++
++ container->name = DWC_STRDUP(name);
++ if (!container->name) {
++ DWC_ERROR("Cannot allocate memory for container->name\n");
++ DWC_FREE(container);
++ return;
++ }
++
++ container->cb = cb;
++ container->data = data;
++ container->wq = wq;
++ DWC_DEBUGC("Queueing work: %s, container=%p", container->name, container);
++ INIT_WORK(&container->work.work, do_work);
++
++#ifdef DEBUG
++ DWC_CIRCLEQ_INSERT_TAIL(&wq->entries, container, entry);
++#endif
++ queue_work(wq->wq, &container->work.work);
++}
++
++void DWC_WORKQ_SCHEDULE_DELAYED(dwc_workq_t *wq, dwc_work_callback_t cb,
++ void *data, uint32_t time, char *format, ...)
++{
++ dwc_irqflags_t flags;
++ work_container_t *container;
++ static char name[128];
++ va_list args;
++
++ va_start(args, format);
++ DWC_VSNPRINTF(name, 128, format, args);
++ va_end(args);
++
++ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
++ wq->pending++;
++ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
++ DWC_WAITQ_TRIGGER(wq->waitq);
++
++ container = DWC_ALLOC_ATOMIC(sizeof(*container));
++ if (!container) {
++ DWC_ERROR("Cannot allocate memory for container\n");
++ return;
++ }
++
++ container->name = DWC_STRDUP(name);
++ if (!container->name) {
++ DWC_ERROR("Cannot allocate memory for container->name\n");
++ DWC_FREE(container);
++ return;
++ }
++
++ container->cb = cb;
++ container->data = data;
++ container->wq = wq;
++ DWC_DEBUGC("Queueing work: %s, container=%p", container->name, container);
++ INIT_DELAYED_WORK(&container->work, do_work);
++
++#ifdef DEBUG
++ DWC_CIRCLEQ_INSERT_TAIL(&wq->entries, container, entry);
++#endif
++ queue_delayed_work(wq->wq, &container->work, msecs_to_jiffies(time));
++}
++
++int DWC_WORKQ_PENDING(dwc_workq_t *wq)
++{
++ return wq->pending;
++}
++
++
++#ifdef DWC_LIBMODULE
++
++#ifdef DWC_CCLIB
++/* CC */
++EXPORT_SYMBOL(dwc_cc_if_alloc);
++EXPORT_SYMBOL(dwc_cc_if_free);
++EXPORT_SYMBOL(dwc_cc_clear);
++EXPORT_SYMBOL(dwc_cc_add);
++EXPORT_SYMBOL(dwc_cc_remove);
++EXPORT_SYMBOL(dwc_cc_change);
++EXPORT_SYMBOL(dwc_cc_data_for_save);
++EXPORT_SYMBOL(dwc_cc_restore_from_data);
++EXPORT_SYMBOL(dwc_cc_match_chid);
++EXPORT_SYMBOL(dwc_cc_match_cdid);
++EXPORT_SYMBOL(dwc_cc_ck);
++EXPORT_SYMBOL(dwc_cc_chid);
++EXPORT_SYMBOL(dwc_cc_cdid);
++EXPORT_SYMBOL(dwc_cc_name);
++#endif /* DWC_CCLIB */
++
++#ifdef DWC_CRYPTOLIB
++# ifndef CONFIG_MACH_IPMATE
++/* Modpow */
++EXPORT_SYMBOL(dwc_modpow);
++
++/* DH */
++EXPORT_SYMBOL(dwc_dh_modpow);
++EXPORT_SYMBOL(dwc_dh_derive_keys);
++EXPORT_SYMBOL(dwc_dh_pk);
++# endif /* CONFIG_MACH_IPMATE */
++
++/* Crypto */
++EXPORT_SYMBOL(dwc_wusb_aes_encrypt);
++EXPORT_SYMBOL(dwc_wusb_cmf);
++EXPORT_SYMBOL(dwc_wusb_prf);
++EXPORT_SYMBOL(dwc_wusb_fill_ccm_nonce);
++EXPORT_SYMBOL(dwc_wusb_gen_nonce);
++EXPORT_SYMBOL(dwc_wusb_gen_key);
++EXPORT_SYMBOL(dwc_wusb_gen_mic);
++#endif /* DWC_CRYPTOLIB */
++
++/* Notification */
++#ifdef DWC_NOTIFYLIB
++EXPORT_SYMBOL(dwc_alloc_notification_manager);
++EXPORT_SYMBOL(dwc_free_notification_manager);
++EXPORT_SYMBOL(dwc_register_notifier);
++EXPORT_SYMBOL(dwc_unregister_notifier);
++EXPORT_SYMBOL(dwc_add_observer);
++EXPORT_SYMBOL(dwc_remove_observer);
++EXPORT_SYMBOL(dwc_notify);
++#endif
++
++/* Memory Debugging Routines */
++#ifdef DWC_DEBUG_MEMORY
++EXPORT_SYMBOL(dwc_alloc_debug);
++EXPORT_SYMBOL(dwc_alloc_atomic_debug);
++EXPORT_SYMBOL(dwc_free_debug);
++EXPORT_SYMBOL(dwc_dma_alloc_debug);
++EXPORT_SYMBOL(dwc_dma_free_debug);
++#endif
++
++EXPORT_SYMBOL(DWC_MEMSET);
++EXPORT_SYMBOL(DWC_MEMCPY);
++EXPORT_SYMBOL(DWC_MEMMOVE);
++EXPORT_SYMBOL(DWC_MEMCMP);
++EXPORT_SYMBOL(DWC_STRNCMP);
++EXPORT_SYMBOL(DWC_STRCMP);
++EXPORT_SYMBOL(DWC_STRLEN);
++EXPORT_SYMBOL(DWC_STRCPY);
++EXPORT_SYMBOL(DWC_STRDUP);
++EXPORT_SYMBOL(DWC_ATOI);
++EXPORT_SYMBOL(DWC_ATOUI);
++
++#ifdef DWC_UTFLIB
++EXPORT_SYMBOL(DWC_UTF8_TO_UTF16LE);
++#endif /* DWC_UTFLIB */
++
++EXPORT_SYMBOL(DWC_IN_IRQ);
++EXPORT_SYMBOL(DWC_IN_BH);
++EXPORT_SYMBOL(DWC_VPRINTF);
++EXPORT_SYMBOL(DWC_VSNPRINTF);
++EXPORT_SYMBOL(DWC_PRINTF);
++EXPORT_SYMBOL(DWC_SPRINTF);
++EXPORT_SYMBOL(DWC_SNPRINTF);
++EXPORT_SYMBOL(__DWC_WARN);
++EXPORT_SYMBOL(__DWC_ERROR);
++EXPORT_SYMBOL(DWC_EXCEPTION);
++
++#ifdef DEBUG
++EXPORT_SYMBOL(__DWC_DEBUG);
++#endif
++
++EXPORT_SYMBOL(__DWC_DMA_ALLOC);
++EXPORT_SYMBOL(__DWC_DMA_ALLOC_ATOMIC);
++EXPORT_SYMBOL(__DWC_DMA_FREE);
++EXPORT_SYMBOL(__DWC_ALLOC);
++EXPORT_SYMBOL(__DWC_ALLOC_ATOMIC);
++EXPORT_SYMBOL(__DWC_FREE);
++
++#ifdef DWC_CRYPTOLIB
++EXPORT_SYMBOL(DWC_RANDOM_BYTES);
++EXPORT_SYMBOL(DWC_AES_CBC);
++EXPORT_SYMBOL(DWC_SHA256);
++EXPORT_SYMBOL(DWC_HMAC_SHA256);
++#endif
++
++EXPORT_SYMBOL(DWC_CPU_TO_LE32);
++EXPORT_SYMBOL(DWC_CPU_TO_BE32);
++EXPORT_SYMBOL(DWC_LE32_TO_CPU);
++EXPORT_SYMBOL(DWC_BE32_TO_CPU);
++EXPORT_SYMBOL(DWC_CPU_TO_LE16);
++EXPORT_SYMBOL(DWC_CPU_TO_BE16);
++EXPORT_SYMBOL(DWC_LE16_TO_CPU);
++EXPORT_SYMBOL(DWC_BE16_TO_CPU);
++EXPORT_SYMBOL(DWC_READ_REG32);
++EXPORT_SYMBOL(DWC_WRITE_REG32);
++EXPORT_SYMBOL(DWC_MODIFY_REG32);
++
++#if 0
++EXPORT_SYMBOL(DWC_READ_REG64);
++EXPORT_SYMBOL(DWC_WRITE_REG64);
++EXPORT_SYMBOL(DWC_MODIFY_REG64);
++#endif
++
++EXPORT_SYMBOL(DWC_SPINLOCK_ALLOC);
++EXPORT_SYMBOL(DWC_SPINLOCK_FREE);
++EXPORT_SYMBOL(DWC_SPINLOCK);
++EXPORT_SYMBOL(DWC_SPINUNLOCK);
++EXPORT_SYMBOL(DWC_SPINLOCK_IRQSAVE);
++EXPORT_SYMBOL(DWC_SPINUNLOCK_IRQRESTORE);
++EXPORT_SYMBOL(DWC_MUTEX_ALLOC);
++
++#if (!defined(DWC_LINUX) || !defined(CONFIG_DEBUG_MUTEXES))
++EXPORT_SYMBOL(DWC_MUTEX_FREE);
++#endif
++
++EXPORT_SYMBOL(DWC_MUTEX_LOCK);
++EXPORT_SYMBOL(DWC_MUTEX_TRYLOCK);
++EXPORT_SYMBOL(DWC_MUTEX_UNLOCK);
++EXPORT_SYMBOL(DWC_UDELAY);
++EXPORT_SYMBOL(DWC_MDELAY);
++EXPORT_SYMBOL(DWC_MSLEEP);
++EXPORT_SYMBOL(DWC_TIME);
++EXPORT_SYMBOL(DWC_TIMER_ALLOC);
++EXPORT_SYMBOL(DWC_TIMER_FREE);
++EXPORT_SYMBOL(DWC_TIMER_SCHEDULE);
++EXPORT_SYMBOL(DWC_TIMER_CANCEL);
++EXPORT_SYMBOL(DWC_WAITQ_ALLOC);
++EXPORT_SYMBOL(DWC_WAITQ_FREE);
++EXPORT_SYMBOL(DWC_WAITQ_WAIT);
++EXPORT_SYMBOL(DWC_WAITQ_WAIT_TIMEOUT);
++EXPORT_SYMBOL(DWC_WAITQ_TRIGGER);
++EXPORT_SYMBOL(DWC_WAITQ_ABORT);
++EXPORT_SYMBOL(DWC_THREAD_RUN);
++EXPORT_SYMBOL(DWC_THREAD_STOP);
++EXPORT_SYMBOL(DWC_THREAD_SHOULD_STOP);
++EXPORT_SYMBOL(DWC_TASK_ALLOC);
++EXPORT_SYMBOL(DWC_TASK_FREE);
++EXPORT_SYMBOL(DWC_TASK_SCHEDULE);
++EXPORT_SYMBOL(DWC_WORKQ_WAIT_WORK_DONE);
++EXPORT_SYMBOL(DWC_WORKQ_ALLOC);
++EXPORT_SYMBOL(DWC_WORKQ_FREE);
++EXPORT_SYMBOL(DWC_WORKQ_SCHEDULE);
++EXPORT_SYMBOL(DWC_WORKQ_SCHEDULE_DELAYED);
++EXPORT_SYMBOL(DWC_WORKQ_PENDING);
++
++static int dwc_common_port_init_module(void)
++{
++ int result = 0;
++
++ printk(KERN_DEBUG "Module dwc_common_port init\n" );
++
++#ifdef DWC_DEBUG_MEMORY
++ result = dwc_memory_debug_start(NULL);
++ if (result) {
++ printk(KERN_ERR
++ "dwc_memory_debug_start() failed with error %d\n",
++ result);
++ return result;
++ }
++#endif
++
++#ifdef DWC_NOTIFYLIB
++ result = dwc_alloc_notification_manager(NULL, NULL);
++ if (result) {
++ printk(KERN_ERR
++ "dwc_alloc_notification_manager() failed with error %d\n",
++ result);
++ return result;
++ }
++#endif
++ return result;
++}
++
++static void dwc_common_port_exit_module(void)
++{
++ printk(KERN_DEBUG "Module dwc_common_port exit\n" );
++
++#ifdef DWC_NOTIFYLIB
++ dwc_free_notification_manager();
++#endif
++
++#ifdef DWC_DEBUG_MEMORY
++ dwc_memory_debug_stop();
++#endif
++}
++
++module_init(dwc_common_port_init_module);
++module_exit(dwc_common_port_exit_module);
++
++MODULE_DESCRIPTION("DWC Common Library - Portable version");
++MODULE_AUTHOR("Synopsys Inc.");
++MODULE_LICENSE ("GPL");
++
++#endif /* DWC_LIBMODULE */
+diff -Nur linux-4.1.3/drivers/usb/host/dwc_common_port/dwc_common_nbsd.c linux-xbian-rpi/drivers/usb/host/dwc_common_port/dwc_common_nbsd.c
+--- linux-4.1.3/drivers/usb/host/dwc_common_port/dwc_common_nbsd.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/usb/host/dwc_common_port/dwc_common_nbsd.c 2015-07-28 01:20:58.441170694 +0200
+@@ -0,0 +1,1275 @@
++#include "dwc_os.h"
++#include "dwc_list.h"
++
++#ifdef DWC_CCLIB
++# include "dwc_cc.h"
++#endif
++
++#ifdef DWC_CRYPTOLIB
++# include "dwc_modpow.h"
++# include "dwc_dh.h"
++# include "dwc_crypto.h"
++#endif
++
++#ifdef DWC_NOTIFYLIB
++# include "dwc_notifier.h"
++#endif
++
++/* OS-Level Implementations */
++
++/* This is the NetBSD 4.0.1 kernel implementation of the DWC platform library. */
++
++
++/* MISC */
++
++void *DWC_MEMSET(void *dest, uint8_t byte, uint32_t size)
++{
++ return memset(dest, byte, size);
++}
++
++void *DWC_MEMCPY(void *dest, void const *src, uint32_t size)
++{
++ return memcpy(dest, src, size);
++}
++
++void *DWC_MEMMOVE(void *dest, void *src, uint32_t size)
++{
++ bcopy(src, dest, size);
++ return dest;
++}
++
++int DWC_MEMCMP(void *m1, void *m2, uint32_t size)
++{
++ return memcmp(m1, m2, size);
++}
++
++int DWC_STRNCMP(void *s1, void *s2, uint32_t size)
++{
++ return strncmp(s1, s2, size);
++}
++
++int DWC_STRCMP(void *s1, void *s2)
++{
++ return strcmp(s1, s2);
++}
++
++int DWC_STRLEN(char const *str)
++{
++ return strlen(str);
++}
++
++char *DWC_STRCPY(char *to, char const *from)
++{
++ return strcpy(to, from);
++}
++
++char *DWC_STRDUP(char const *str)
++{
++ int len = DWC_STRLEN(str) + 1;
++ char *new = DWC_ALLOC_ATOMIC(len);
++
++ if (!new) {
++ return NULL;
++ }
++
++ DWC_MEMCPY(new, str, len);
++ return new;
++}
++
++int DWC_ATOI(char *str, int32_t *value)
++{
++ char *end = NULL;
++
++ /* NetBSD doesn't have 'strtol' in the kernel, but 'strtoul'
++ * should be equivalent on 2's complement machines
++ */
++ *value = strtoul(str, &end, 0);
++ if (*end == '\0') {
++ return 0;
++ }
++
++ return -1;
++}
++
++int DWC_ATOUI(char *str, uint32_t *value)
++{
++ char *end = NULL;
++
++ *value = strtoul(str, &end, 0);
++ if (*end == '\0') {
++ return 0;
++ }
++
++ return -1;
++}
++
++
++#ifdef DWC_UTFLIB
++/* From usbstring.c */
++
++int DWC_UTF8_TO_UTF16LE(uint8_t const *s, uint16_t *cp, unsigned len)
++{
++ int count = 0;
++ u8 c;
++ u16 uchar;
++
++ /* this insists on correct encodings, though not minimal ones.
++ * BUT it currently rejects legit 4-byte UTF-8 code points,
++ * which need surrogate pairs. (Unicode 3.1 can use them.)
++ */
++ while (len != 0 && (c = (u8) *s++) != 0) {
++ if (unlikely(c & 0x80)) {
++ // 2-byte sequence:
++ // 00000yyyyyxxxxxx = 110yyyyy 10xxxxxx
++ if ((c & 0xe0) == 0xc0) {
++ uchar = (c & 0x1f) << 6;
++
++ c = (u8) *s++;
++ if ((c & 0xc0) != 0xc0)
++ goto fail;
++ c &= 0x3f;
++ uchar |= c;
++
++ // 3-byte sequence (most CJKV characters):
++ // zzzzyyyyyyxxxxxx = 1110zzzz 10yyyyyy 10xxxxxx
++ } else if ((c & 0xf0) == 0xe0) {
++ uchar = (c & 0x0f) << 12;
++
++ c = (u8) *s++;
++ if ((c & 0xc0) != 0xc0)
++ goto fail;
++ c &= 0x3f;
++ uchar |= c << 6;
++
++ c = (u8) *s++;
++ if ((c & 0xc0) != 0xc0)
++ goto fail;
++ c &= 0x3f;
++ uchar |= c;
++
++ /* no bogus surrogates */
++ if (0xd800 <= uchar && uchar <= 0xdfff)
++ goto fail;
++
++ // 4-byte sequence (surrogate pairs, currently rare):
++ // 11101110wwwwzzzzyy + 110111yyyyxxxxxx
++ // = 11110uuu 10uuzzzz 10yyyyyy 10xxxxxx
++ // (uuuuu = wwww + 1)
++ // FIXME accept the surrogate code points (only)
++ } else
++ goto fail;
++ } else
++ uchar = c;
++ put_unaligned (cpu_to_le16 (uchar), cp++);
++ count++;
++ len--;
++ }
++ return count;
++fail:
++ return -1;
++}
++
++#endif /* DWC_UTFLIB */
++
++
++/* dwc_debug.h */
++
++dwc_bool_t DWC_IN_IRQ(void)
++{
++// return in_irq();
++ return 0;
++}
++
++dwc_bool_t DWC_IN_BH(void)
++{
++// return in_softirq();
++ return 0;
++}
++
++void DWC_VPRINTF(char *format, va_list args)
++{
++ vprintf(format, args);
++}
++
++int DWC_VSNPRINTF(char *str, int size, char *format, va_list args)
++{
++ return vsnprintf(str, size, format, args);
++}
++
++void DWC_PRINTF(char *format, ...)
++{
++ va_list args;
++
++ va_start(args, format);
++ DWC_VPRINTF(format, args);
++ va_end(args);
++}
++
++int DWC_SPRINTF(char *buffer, char *format, ...)
++{
++ int retval;
++ va_list args;
++
++ va_start(args, format);
++ retval = vsprintf(buffer, format, args);
++ va_end(args);
++ return retval;
++}
++
++int DWC_SNPRINTF(char *buffer, int size, char *format, ...)
++{
++ int retval;
++ va_list args;
++
++ va_start(args, format);
++ retval = vsnprintf(buffer, size, format, args);
++ va_end(args);
++ return retval;
++}
++
++void __DWC_WARN(char *format, ...)
++{
++ va_list args;
++
++ va_start(args, format);
++ DWC_VPRINTF(format, args);
++ va_end(args);
++}
++
++void __DWC_ERROR(char *format, ...)
++{
++ va_list args;
++
++ va_start(args, format);
++ DWC_VPRINTF(format, args);
++ va_end(args);
++}
++
++void DWC_EXCEPTION(char *format, ...)
++{
++ va_list args;
++
++ va_start(args, format);
++ DWC_VPRINTF(format, args);
++ va_end(args);
++// BUG_ON(1); ???
++}
++
++#ifdef DEBUG
++void __DWC_DEBUG(char *format, ...)
++{
++ va_list args;
++
++ va_start(args, format);
++ DWC_VPRINTF(format, args);
++ va_end(args);
++}
++#endif
++
++
++/* dwc_mem.h */
++
++#if 0
++dwc_pool_t *DWC_DMA_POOL_CREATE(uint32_t size,
++ uint32_t align,
++ uint32_t alloc)
++{
++ struct dma_pool *pool = dma_pool_create("Pool", NULL,
++ size, align, alloc);
++ return (dwc_pool_t *)pool;
++}
++
++void DWC_DMA_POOL_DESTROY(dwc_pool_t *pool)
++{
++ dma_pool_destroy((struct dma_pool *)pool);
++}
++
++void *DWC_DMA_POOL_ALLOC(dwc_pool_t *pool, uint64_t *dma_addr)
++{
++// return dma_pool_alloc((struct dma_pool *)pool, GFP_KERNEL, dma_addr);
++ return dma_pool_alloc((struct dma_pool *)pool, M_WAITOK, dma_addr);
++}
++
++void *DWC_DMA_POOL_ZALLOC(dwc_pool_t *pool, uint64_t *dma_addr)
++{
++ void *vaddr = DWC_DMA_POOL_ALLOC(pool, dma_addr);
++ memset(..);
++}
++
++void DWC_DMA_POOL_FREE(dwc_pool_t *pool, void *vaddr, void *daddr)
++{
++ dma_pool_free(pool, vaddr, daddr);
++}
++#endif
++
++void *__DWC_DMA_ALLOC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr)
++{
++ dwc_dmactx_t *dma = (dwc_dmactx_t *)dma_ctx;
++ int error;
++
++ error = bus_dmamem_alloc(dma->dma_tag, size, 1, size, dma->segs,
++ sizeof(dma->segs) / sizeof(dma->segs[0]),
++ &dma->nsegs, BUS_DMA_NOWAIT);
++ if (error) {
++ printf("%s: bus_dmamem_alloc(%ju) failed: %d\n", __func__,
++ (uintmax_t)size, error);
++ goto fail_0;
++ }
++
++ error = bus_dmamem_map(dma->dma_tag, dma->segs, dma->nsegs, size,
++ (caddr_t *)&dma->dma_vaddr,
++ BUS_DMA_NOWAIT | BUS_DMA_COHERENT);
++ if (error) {
++ printf("%s: bus_dmamem_map failed: %d\n", __func__, error);
++ goto fail_1;
++ }
++
++ error = bus_dmamap_create(dma->dma_tag, size, 1, size, 0,
++ BUS_DMA_NOWAIT, &dma->dma_map);
++ if (error) {
++ printf("%s: bus_dmamap_create failed: %d\n", __func__, error);
++ goto fail_2;
++ }
++
++ error = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr,
++ size, NULL, BUS_DMA_NOWAIT);
++ if (error) {
++ printf("%s: bus_dmamap_load failed: %d\n", __func__, error);
++ goto fail_3;
++ }
++
++ dma->dma_paddr = (bus_addr_t)dma->segs[0].ds_addr;
++ *dma_addr = dma->dma_paddr;
++ return dma->dma_vaddr;
++
++fail_3:
++ bus_dmamap_destroy(dma->dma_tag, dma->dma_map);
++fail_2:
++ bus_dmamem_unmap(dma->dma_tag, dma->dma_vaddr, size);
++fail_1:
++ bus_dmamem_free(dma->dma_tag, dma->segs, dma->nsegs);
++fail_0:
++ dma->dma_map = NULL;
++ dma->dma_vaddr = NULL;
++ dma->nsegs = 0;
++
++ return NULL;
++}
++
++void __DWC_DMA_FREE(void *dma_ctx, uint32_t size, void *virt_addr, dwc_dma_t dma_addr)
++{
++ dwc_dmactx_t *dma = (dwc_dmactx_t *)dma_ctx;
++
++ if (dma->dma_map != NULL) {
++ bus_dmamap_sync(dma->dma_tag, dma->dma_map, 0, size,
++ BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
++ bus_dmamap_unload(dma->dma_tag, dma->dma_map);
++ bus_dmamap_destroy(dma->dma_tag, dma->dma_map);
++ bus_dmamem_unmap(dma->dma_tag, dma->dma_vaddr, size);
++ bus_dmamem_free(dma->dma_tag, dma->segs, dma->nsegs);
++ dma->dma_paddr = 0;
++ dma->dma_map = NULL;
++ dma->dma_vaddr = NULL;
++ dma->nsegs = 0;
++ }
++}
++
++void *__DWC_ALLOC(void *mem_ctx, uint32_t size)
++{
++ return malloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
++}
++
++void *__DWC_ALLOC_ATOMIC(void *mem_ctx, uint32_t size)
++{
++ return malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO);
++}
++
++void __DWC_FREE(void *mem_ctx, void *addr)
++{
++ free(addr, M_DEVBUF);
++}
++
++
++#ifdef DWC_CRYPTOLIB
++/* dwc_crypto.h */
++
++void DWC_RANDOM_BYTES(uint8_t *buffer, uint32_t length)
++{
++ get_random_bytes(buffer, length);
++}
++
++int DWC_AES_CBC(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t iv[16], uint8_t *out)
++{
++ struct crypto_blkcipher *tfm;
++ struct blkcipher_desc desc;
++ struct scatterlist sgd;
++ struct scatterlist sgs;
++
++ tfm = crypto_alloc_blkcipher("cbc(aes)", 0, CRYPTO_ALG_ASYNC);
++ if (tfm == NULL) {
++ printk("failed to load transform for aes CBC\n");
++ return -1;
++ }
++
++ crypto_blkcipher_setkey(tfm, key, keylen);
++ crypto_blkcipher_set_iv(tfm, iv, 16);
++
++ sg_init_one(&sgd, out, messagelen);
++ sg_init_one(&sgs, message, messagelen);
++
++ desc.tfm = tfm;
++ desc.flags = 0;
++
++ if (crypto_blkcipher_encrypt(&desc, &sgd, &sgs, messagelen)) {
++ crypto_free_blkcipher(tfm);
++ DWC_ERROR("AES CBC encryption failed");
++ return -1;
++ }
++
++ crypto_free_blkcipher(tfm);
++ return 0;
++}
++
++int DWC_SHA256(uint8_t *message, uint32_t len, uint8_t *out)
++{
++ struct crypto_hash *tfm;
++ struct hash_desc desc;
++ struct scatterlist sg;
++
++ tfm = crypto_alloc_hash("sha256", 0, CRYPTO_ALG_ASYNC);
++ if (IS_ERR(tfm)) {
++ DWC_ERROR("Failed to load transform for sha256: %ld", PTR_ERR(tfm));
++ return 0;
++ }
++ desc.tfm = tfm;
++ desc.flags = 0;
++
++ sg_init_one(&sg, message, len);
++ crypto_hash_digest(&desc, &sg, len, out);
++ crypto_free_hash(tfm);
++
++ return 1;
++}
++
++int DWC_HMAC_SHA256(uint8_t *message, uint32_t messagelen,
++ uint8_t *key, uint32_t keylen, uint8_t *out)
++{
++ struct crypto_hash *tfm;
++ struct hash_desc desc;
++ struct scatterlist sg;
++
++ tfm = crypto_alloc_hash("hmac(sha256)", 0, CRYPTO_ALG_ASYNC);
++ if (IS_ERR(tfm)) {
++ DWC_ERROR("Failed to load transform for hmac(sha256): %ld", PTR_ERR(tfm));
++ return 0;
++ }
++ desc.tfm = tfm;
++ desc.flags = 0;
++
++ sg_init_one(&sg, message, messagelen);
++ crypto_hash_setkey(tfm, key, keylen);
++ crypto_hash_digest(&desc, &sg, messagelen, out);
++ crypto_free_hash(tfm);
++
++ return 1;
++}
++
++#endif /* DWC_CRYPTOLIB */
++
++
++/* Byte Ordering Conversions */
++
++uint32_t DWC_CPU_TO_LE32(uint32_t *p)
++{
++#ifdef __LITTLE_ENDIAN
++ return *p;
++#else
++ uint8_t *u_p = (uint8_t *)p;
++
++ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
++#endif
++}
++
++uint32_t DWC_CPU_TO_BE32(uint32_t *p)
++{
++#ifdef __BIG_ENDIAN
++ return *p;
++#else
++ uint8_t *u_p = (uint8_t *)p;
++
++ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
++#endif
++}
++
++uint32_t DWC_LE32_TO_CPU(uint32_t *p)
++{
++#ifdef __LITTLE_ENDIAN
++ return *p;
++#else
++ uint8_t *u_p = (uint8_t *)p;
++
++ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
++#endif
++}
++
++uint32_t DWC_BE32_TO_CPU(uint32_t *p)
++{
++#ifdef __BIG_ENDIAN
++ return *p;
++#else
++ uint8_t *u_p = (uint8_t *)p;
++
++ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
++#endif
++}
++
++uint16_t DWC_CPU_TO_LE16(uint16_t *p)
++{
++#ifdef __LITTLE_ENDIAN
++ return *p;
++#else
++ uint8_t *u_p = (uint8_t *)p;
++ return (u_p[1] | (u_p[0] << 8));
++#endif
++}
++
++uint16_t DWC_CPU_TO_BE16(uint16_t *p)
++{
++#ifdef __BIG_ENDIAN
++ return *p;
++#else
++ uint8_t *u_p = (uint8_t *)p;
++ return (u_p[1] | (u_p[0] << 8));
++#endif
++}
++
++uint16_t DWC_LE16_TO_CPU(uint16_t *p)
++{
++#ifdef __LITTLE_ENDIAN
++ return *p;
++#else
++ uint8_t *u_p = (uint8_t *)p;
++ return (u_p[1] | (u_p[0] << 8));
++#endif
++}
++
++uint16_t DWC_BE16_TO_CPU(uint16_t *p)
++{
++#ifdef __BIG_ENDIAN
++ return *p;
++#else
++ uint8_t *u_p = (uint8_t *)p;
++ return (u_p[1] | (u_p[0] << 8));
++#endif
++}
++
++
++/* Registers */
++
++uint32_t DWC_READ_REG32(void *io_ctx, uint32_t volatile *reg)
++{
++ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
++ bus_size_t ior = (bus_size_t)reg;
++
++ return bus_space_read_4(io->iot, io->ioh, ior);
++}
++
++#if 0
++uint64_t DWC_READ_REG64(void *io_ctx, uint64_t volatile *reg)
++{
++ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
++ bus_size_t ior = (bus_size_t)reg;
++
++ return bus_space_read_8(io->iot, io->ioh, ior);
++}
++#endif
++
++void DWC_WRITE_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t value)
++{
++ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
++ bus_size_t ior = (bus_size_t)reg;
++
++ bus_space_write_4(io->iot, io->ioh, ior, value);
++}
++
++#if 0
++void DWC_WRITE_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t value)
++{
++ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
++ bus_size_t ior = (bus_size_t)reg;
++
++ bus_space_write_8(io->iot, io->ioh, ior, value);
++}
++#endif
++
++void DWC_MODIFY_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t clear_mask,
++ uint32_t set_mask)
++{
++ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
++ bus_size_t ior = (bus_size_t)reg;
++
++ bus_space_write_4(io->iot, io->ioh, ior,
++ (bus_space_read_4(io->iot, io->ioh, ior) &
++ ~clear_mask) | set_mask);
++}
++
++#if 0
++void DWC_MODIFY_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t clear_mask,
++ uint64_t set_mask)
++{
++ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
++ bus_size_t ior = (bus_size_t)reg;
++
++ bus_space_write_8(io->iot, io->ioh, ior,
++ (bus_space_read_8(io->iot, io->ioh, ior) &
++ ~clear_mask) | set_mask);
++}
++#endif
++
++
++/* Locking */
++
++dwc_spinlock_t *DWC_SPINLOCK_ALLOC(void)
++{
++ struct simplelock *sl = DWC_ALLOC(sizeof(*sl));
++
++ if (!sl) {
++ DWC_ERROR("Cannot allocate memory for spinlock");
++ return NULL;
++ }
++
++ simple_lock_init(sl);
++ return (dwc_spinlock_t *)sl;
++}
++
++void DWC_SPINLOCK_FREE(dwc_spinlock_t *lock)
++{
++ struct simplelock *sl = (struct simplelock *)lock;
++
++ DWC_FREE(sl);
++}
++
++void DWC_SPINLOCK(dwc_spinlock_t *lock)
++{
++ simple_lock((struct simplelock *)lock);
++}
++
++void DWC_SPINUNLOCK(dwc_spinlock_t *lock)
++{
++ simple_unlock((struct simplelock *)lock);
++}
++
++void DWC_SPINLOCK_IRQSAVE(dwc_spinlock_t *lock, dwc_irqflags_t *flags)
++{
++ simple_lock((struct simplelock *)lock);
++ *flags = splbio();
++}
++
++void DWC_SPINUNLOCK_IRQRESTORE(dwc_spinlock_t *lock, dwc_irqflags_t flags)
++{
++ splx(flags);
++ simple_unlock((struct simplelock *)lock);
++}
++
++dwc_mutex_t *DWC_MUTEX_ALLOC(void)
++{
++ dwc_mutex_t *mutex = DWC_ALLOC(sizeof(struct lock));
++
++ if (!mutex) {
++ DWC_ERROR("Cannot allocate memory for mutex");
++ return NULL;
++ }
++
++ lockinit((struct lock *)mutex, 0, "dw3mtx", 0, 0);
++ return mutex;
++}
++
++#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES))
++#else
++void DWC_MUTEX_FREE(dwc_mutex_t *mutex)
++{
++ DWC_FREE(mutex);
++}
++#endif
++
++void DWC_MUTEX_LOCK(dwc_mutex_t *mutex)
++{
++ lockmgr((struct lock *)mutex, LK_EXCLUSIVE, NULL);
++}
++
++int DWC_MUTEX_TRYLOCK(dwc_mutex_t *mutex)
++{
++ int status;
++
++ status = lockmgr((struct lock *)mutex, LK_EXCLUSIVE | LK_NOWAIT, NULL);
++ return status == 0;
++}
++
++void DWC_MUTEX_UNLOCK(dwc_mutex_t *mutex)
++{
++ lockmgr((struct lock *)mutex, LK_RELEASE, NULL);
++}
++
++
++/* Timing */
++
++void DWC_UDELAY(uint32_t usecs)
++{
++ DELAY(usecs);
++}
++
++void DWC_MDELAY(uint32_t msecs)
++{
++ do {
++ DELAY(1000);
++ } while (--msecs);
++}
++
++void DWC_MSLEEP(uint32_t msecs)
++{
++ struct timeval tv;
++
++ tv.tv_sec = msecs / 1000;
++ tv.tv_usec = (msecs - tv.tv_sec * 1000) * 1000;
++ tsleep(&tv, 0, "dw3slp", tvtohz(&tv));
++}
++
++uint32_t DWC_TIME(void)
++{
++ struct timeval tv;
++
++ microuptime(&tv); // or getmicrouptime? (less precise, but faster)
++ return tv.tv_sec * 1000 + tv.tv_usec / 1000;
++}
++
++
++/* Timers */
++
++struct dwc_timer {
++ struct callout t;
++ char *name;
++ dwc_spinlock_t *lock;
++ dwc_timer_callback_t cb;
++ void *data;
++};
++
++dwc_timer_t *DWC_TIMER_ALLOC(char *name, dwc_timer_callback_t cb, void *data)
++{
++ dwc_timer_t *t = DWC_ALLOC(sizeof(*t));
++
++ if (!t) {
++ DWC_ERROR("Cannot allocate memory for timer");
++ return NULL;
++ }
++
++ callout_init(&t->t);
++
++ t->name = DWC_STRDUP(name);
++ if (!t->name) {
++ DWC_ERROR("Cannot allocate memory for timer->name");
++ goto no_name;
++ }
++
++ t->lock = DWC_SPINLOCK_ALLOC();
++ if (!t->lock) {
++ DWC_ERROR("Cannot allocate memory for timer->lock");
++ goto no_lock;
++ }
++
++ t->cb = cb;
++ t->data = data;
++
++ return t;
++
++ no_lock:
++ DWC_FREE(t->name);
++ no_name:
++ DWC_FREE(t);
++
++ return NULL;
++}
++
++void DWC_TIMER_FREE(dwc_timer_t *timer)
++{
++ callout_stop(&timer->t);
++ DWC_SPINLOCK_FREE(timer->lock);
++ DWC_FREE(timer->name);
++ DWC_FREE(timer);
++}
++
++void DWC_TIMER_SCHEDULE(dwc_timer_t *timer, uint32_t time)
++{
++ struct timeval tv;
++
++ tv.tv_sec = time / 1000;
++ tv.tv_usec = (time - tv.tv_sec * 1000) * 1000;
++ callout_reset(&timer->t, tvtohz(&tv), timer->cb, timer->data);
++}
++
++void DWC_TIMER_CANCEL(dwc_timer_t *timer)
++{
++ callout_stop(&timer->t);
++}
++
++
++/* Wait Queues */
++
++struct dwc_waitq {
++ struct simplelock lock;
++ int abort;
++};
++
++dwc_waitq_t *DWC_WAITQ_ALLOC(void)
++{
++ dwc_waitq_t *wq = DWC_ALLOC(sizeof(*wq));
++
++ if (!wq) {
++ DWC_ERROR("Cannot allocate memory for waitqueue");
++ return NULL;
++ }
++
++ simple_lock_init(&wq->lock);
++ wq->abort = 0;
++
++ return wq;
++}
++
++void DWC_WAITQ_FREE(dwc_waitq_t *wq)
++{
++ DWC_FREE(wq);
++}
++
++int32_t DWC_WAITQ_WAIT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, void *data)
++{
++ int ipl;
++ int result = 0;
++
++ simple_lock(&wq->lock);
++ ipl = splbio();
++
++ /* Skip the sleep if already aborted or triggered */
++ if (!wq->abort && !cond(data)) {
++ splx(ipl);
++ result = ltsleep(wq, PCATCH, "dw3wat", 0, &wq->lock); // infinite timeout
++ ipl = splbio();
++ }
++
++ if (result == 0) { // awoken
++ if (wq->abort) {
++ wq->abort = 0;
++ result = -DWC_E_ABORT;
++ } else {
++ result = 0;
++ }
++
++ splx(ipl);
++ simple_unlock(&wq->lock);
++ } else {
++ wq->abort = 0;
++ splx(ipl);
++ simple_unlock(&wq->lock);
++
++ if (result == ERESTART) { // signaled - restart
++ result = -DWC_E_RESTART;
++ } else { // signaled - must be EINTR
++ result = -DWC_E_ABORT;
++ }
++ }
++
++ return result;
++}
++
++int32_t DWC_WAITQ_WAIT_TIMEOUT(dwc_waitq_t *wq, dwc_waitq_condition_t cond,
++ void *data, int32_t msecs)
++{
++ struct timeval tv, tv1, tv2;
++ int ipl;
++ int result = 0;
++
++ tv.tv_sec = msecs / 1000;
++ tv.tv_usec = (msecs - tv.tv_sec * 1000) * 1000;
++
++ simple_lock(&wq->lock);
++ ipl = splbio();
++
++ /* Skip the sleep if already aborted or triggered */
++ if (!wq->abort && !cond(data)) {
++ splx(ipl);
++ getmicrouptime(&tv1);
++ result = ltsleep(wq, PCATCH, "dw3wto", tvtohz(&tv), &wq->lock);
++ getmicrouptime(&tv2);
++ ipl = splbio();
++ }
++
++ if (result == 0) { // awoken
++ if (wq->abort) {
++ wq->abort = 0;
++ splx(ipl);
++ simple_unlock(&wq->lock);
++ result = -DWC_E_ABORT;
++ } else {
++ splx(ipl);
++ simple_unlock(&wq->lock);
++
++ tv2.tv_usec -= tv1.tv_usec;
++ if (tv2.tv_usec < 0) {
++ tv2.tv_usec += 1000000;
++ tv2.tv_sec--;
++ }
++
++ tv2.tv_sec -= tv1.tv_sec;
++ result = tv2.tv_sec * 1000 + tv2.tv_usec / 1000;
++ result = msecs - result;
++ if (result <= 0)
++ result = 1;
++ }
++ } else {
++ wq->abort = 0;
++ splx(ipl);
++ simple_unlock(&wq->lock);
++
++ if (result == ERESTART) { // signaled - restart
++ result = -DWC_E_RESTART;
++
++ } else if (result == EINTR) { // signaled - interrupt
++ result = -DWC_E_ABORT;
++
++ } else { // timed out
++ result = -DWC_E_TIMEOUT;
++ }
++ }
++
++ return result;
++}
++
++void DWC_WAITQ_TRIGGER(dwc_waitq_t *wq)
++{
++ wakeup(wq);
++}
++
++void DWC_WAITQ_ABORT(dwc_waitq_t *wq)
++{
++ int ipl;
++
++ simple_lock(&wq->lock);
++ ipl = splbio();
++ wq->abort = 1;
++ wakeup(wq);
++ splx(ipl);
++ simple_unlock(&wq->lock);
++}
++
++
++/* Threading */
++
++struct dwc_thread {
++ struct proc *proc;
++ int abort;
++};
++
++dwc_thread_t *DWC_THREAD_RUN(dwc_thread_function_t func, char *name, void *data)
++{
++ int retval;
++ dwc_thread_t *thread = DWC_ALLOC(sizeof(*thread));
++
++ if (!thread) {
++ return NULL;
++ }
++
++ thread->abort = 0;
++ retval = kthread_create1((void (*)(void *))func, data, &thread->proc,
++ "%s", name);
++ if (retval) {
++ DWC_FREE(thread);
++ return NULL;
++ }
++
++ return thread;
++}
++
++int DWC_THREAD_STOP(dwc_thread_t *thread)
++{
++ int retval;
++
++ thread->abort = 1;
++ retval = tsleep(&thread->abort, 0, "dw3stp", 60 * hz);
++
++ if (retval == 0) {
++ /* DWC_THREAD_EXIT() will free the thread struct */
++ return 0;
++ }
++
++ /* NOTE: We leak the thread struct if thread doesn't die */
++
++ if (retval == EWOULDBLOCK) {
++ return -DWC_E_TIMEOUT;
++ }
++
++ return -DWC_E_UNKNOWN;
++}
++
++dwc_bool_t DWC_THREAD_SHOULD_STOP(dwc_thread_t *thread)
++{
++ return thread->abort;
++}
++
++void DWC_THREAD_EXIT(dwc_thread_t *thread)
++{
++ wakeup(&thread->abort);
++ DWC_FREE(thread);
++ kthread_exit(0);
++}
++
++/* tasklets
++ - Runs in interrupt context (cannot sleep)
++ - Each tasklet runs on a single CPU
++ - Different tasklets can be running simultaneously on different CPUs
++ [ On NetBSD there is no corresponding mechanism, drivers don't have bottom-
++ halves. So we just call the callback directly from DWC_TASK_SCHEDULE() ]
++ */
++struct dwc_tasklet {
++ dwc_tasklet_callback_t cb;
++ void *data;
++};
++
++static void tasklet_callback(void *data)
++{
++ dwc_tasklet_t *task = (dwc_tasklet_t *)data;
++
++ task->cb(task->data);
++}
++
++dwc_tasklet_t *DWC_TASK_ALLOC(char *name, dwc_tasklet_callback_t cb, void *data)
++{
++ dwc_tasklet_t *task = DWC_ALLOC(sizeof(*task));
++
++ if (task) {
++ task->cb = cb;
++ task->data = data;
++ } else {
++ DWC_ERROR("Cannot allocate memory for tasklet");
++ }
++
++ return task;
++}
++
++void DWC_TASK_FREE(dwc_tasklet_t *task)
++{
++ DWC_FREE(task);
++}
++
++void DWC_TASK_SCHEDULE(dwc_tasklet_t *task)
++{
++ tasklet_callback(task);
++}
++
++
++/* workqueues
++ - Runs in process context (can sleep)
++ */
++typedef struct work_container {
++ dwc_work_callback_t cb;
++ void *data;
++ dwc_workq_t *wq;
++ char *name;
++ int hz;
++ struct work task;
++} work_container_t;
++
++struct dwc_workq {
++ struct workqueue *taskq;
++ dwc_spinlock_t *lock;
++ dwc_waitq_t *waitq;
++ int pending;
++ struct work_container *container;
++};
++
++static void do_work(struct work *task, void *data)
++{
++ dwc_workq_t *wq = (dwc_workq_t *)data;
++ work_container_t *container = wq->container;
++ dwc_irqflags_t flags;
++
++ if (container->hz) {
++ tsleep(container, 0, "dw3wrk", container->hz);
++ }
++
++ container->cb(container->data);
++ DWC_DEBUG("Work done: %s, container=%p", container->name, container);
++
++ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
++ if (container->name)
++ DWC_FREE(container->name);
++ DWC_FREE(container);
++ wq->pending--;
++ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
++ DWC_WAITQ_TRIGGER(wq->waitq);
++}
++
++static int work_done(void *data)
++{
++ dwc_workq_t *workq = (dwc_workq_t *)data;
++
++ return workq->pending == 0;
++}
++
++int DWC_WORKQ_WAIT_WORK_DONE(dwc_workq_t *workq, int timeout)
++{
++ return DWC_WAITQ_WAIT_TIMEOUT(workq->waitq, work_done, workq, timeout);
++}
++
++dwc_workq_t *DWC_WORKQ_ALLOC(char *name)
++{
++ int result;
++ dwc_workq_t *wq = DWC_ALLOC(sizeof(*wq));
++
++ if (!wq) {
++ DWC_ERROR("Cannot allocate memory for workqueue");
++ return NULL;
++ }
++
++ result = workqueue_create(&wq->taskq, name, do_work, wq, 0 /*PWAIT*/,
++ IPL_BIO, 0);
++ if (result) {
++ DWC_ERROR("Cannot create workqueue");
++ goto no_taskq;
++ }
++
++ wq->pending = 0;
++
++ wq->lock = DWC_SPINLOCK_ALLOC();
++ if (!wq->lock) {
++ DWC_ERROR("Cannot allocate memory for spinlock");
++ goto no_lock;
++ }
++
++ wq->waitq = DWC_WAITQ_ALLOC();
++ if (!wq->waitq) {
++ DWC_ERROR("Cannot allocate memory for waitqueue");
++ goto no_waitq;
++ }
++
++ return wq;
++
++ no_waitq:
++ DWC_SPINLOCK_FREE(wq->lock);
++ no_lock:
++ workqueue_destroy(wq->taskq);
++ no_taskq:
++ DWC_FREE(wq);
++
++ return NULL;
++}
++
++void DWC_WORKQ_FREE(dwc_workq_t *wq)
++{
++#ifdef DEBUG
++ dwc_irqflags_t flags;
++
++ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
++
++ if (wq->pending != 0) {
++ struct work_container *container = wq->container;
++
++ DWC_ERROR("Destroying work queue with pending work");
++
++ if (container && container->name) {
++ DWC_ERROR("Work %s still pending", container->name);
++ }
++ }
++
++ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
++#endif
++ DWC_WAITQ_FREE(wq->waitq);
++ DWC_SPINLOCK_FREE(wq->lock);
++ workqueue_destroy(wq->taskq);
++ DWC_FREE(wq);
++}
++
++void DWC_WORKQ_SCHEDULE(dwc_workq_t *wq, dwc_work_callback_t cb, void *data,
++ char *format, ...)
++{
++ dwc_irqflags_t flags;
++ work_container_t *container;
++ static char name[128];
++ va_list args;
++
++ va_start(args, format);
++ DWC_VSNPRINTF(name, 128, format, args);
++ va_end(args);
++
++ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
++ wq->pending++;
++ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
++ DWC_WAITQ_TRIGGER(wq->waitq);
++
++ container = DWC_ALLOC_ATOMIC(sizeof(*container));
++ if (!container) {
++ DWC_ERROR("Cannot allocate memory for container");
++ return;
++ }
++
++ container->name = DWC_STRDUP(name);
++ if (!container->name) {
++ DWC_ERROR("Cannot allocate memory for container->name");
++ DWC_FREE(container);
++ return;
++ }
++
++ container->cb = cb;
++ container->data = data;
++ container->wq = wq;
++ container->hz = 0;
++ wq->container = container;
++
++ DWC_DEBUG("Queueing work: %s, container=%p", container->name, container);
++ workqueue_enqueue(wq->taskq, &container->task);
++}
++
++void DWC_WORKQ_SCHEDULE_DELAYED(dwc_workq_t *wq, dwc_work_callback_t cb,
++ void *data, uint32_t time, char *format, ...)
++{
++ dwc_irqflags_t flags;
++ work_container_t *container;
++ static char name[128];
++ struct timeval tv;
++ va_list args;
++
++ va_start(args, format);
++ DWC_VSNPRINTF(name, 128, format, args);
++ va_end(args);
++
++ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
++ wq->pending++;
++ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
++ DWC_WAITQ_TRIGGER(wq->waitq);
++
++ container = DWC_ALLOC_ATOMIC(sizeof(*container));
++ if (!container) {
++ DWC_ERROR("Cannot allocate memory for container");
++ return;
++ }
++
++ container->name = DWC_STRDUP(name);
++ if (!container->name) {
++ DWC_ERROR("Cannot allocate memory for container->name");
++ DWC_FREE(container);
++ return;
++ }
++
++ container->cb = cb;
++ container->data = data;
++ container->wq = wq;
++ tv.tv_sec = time / 1000;
++ tv.tv_usec = (time - tv.tv_sec * 1000) * 1000;
++ container->hz = tvtohz(&tv);
++ wq->container = container;
++
++ DWC_DEBUG("Queueing work: %s, container=%p", container->name, container);
++ workqueue_enqueue(wq->taskq, &container->task);
++}
++
++int DWC_WORKQ_PENDING(dwc_workq_t *wq)
++{
++ return wq->pending;
++}
+diff -Nur linux-4.1.3/drivers/usb/host/dwc_common_port/dwc_crypto.c linux-xbian-rpi/drivers/usb/host/dwc_common_port/dwc_crypto.c
+--- linux-4.1.3/drivers/usb/host/dwc_common_port/dwc_crypto.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/usb/host/dwc_common_port/dwc_crypto.c 2015-07-28 01:20:58.441170694 +0200
+@@ -0,0 +1,308 @@
++/* =========================================================================
++ * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_crypto.c $
++ * $Revision: #5 $
++ * $Date: 2010/09/28 $
++ * $Change: 1596182 $
++ *
++ * Synopsys Portability Library Software and documentation
++ * (hereinafter, "Software") is an Unsupported proprietary work of
++ * Synopsys, Inc. unless otherwise expressly agreed to in writing
++ * between Synopsys and you.
++ *
++ * The Software IS NOT an item of Licensed Software or Licensed Product
++ * under any End User Software License Agreement or Agreement for
++ * Licensed Product with Synopsys or any supplement thereto. You are
++ * permitted to use and redistribute this Software in source and binary
++ * forms, with or without modification, provided that redistributions
++ * of source code must retain this notice. You may not view, use,
++ * disclose, copy or distribute this file or any information contained
++ * herein except pursuant to this license grant from Synopsys. If you
++ * do not agree with this notice, including the disclaimer below, then
++ * you are not authorized to use the Software.
++ *
++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
++ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL
++ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
++ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
++ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++ * DAMAGE.
++ * ========================================================================= */
++
++/** @file
++ * This file contains the WUSB cryptographic routines.
++ */
++
++#ifdef DWC_CRYPTOLIB
++
++#include "dwc_crypto.h"
++#include "usb.h"
++
++#ifdef DEBUG
++static inline void dump_bytes(char *name, uint8_t *bytes, int len)
++{
++ int i;
++ DWC_PRINTF("%s: ", name);
++ for (i=0; i<len; i++) {
++ DWC_PRINTF("%02x ", bytes[i]);
++ }
++ DWC_PRINTF("\n");
++}
++#else
++#define dump_bytes(x...)
++#endif
++
++/* Display a block */
++void show_block(const u8 *blk, const char *prefix, const char *suffix, int a)
++{
++#ifdef DWC_DEBUG_CRYPTO
++ int i, blksize = 16;
++
++ DWC_DEBUG("%s", prefix);
++
++ if (suffix == NULL) {
++ suffix = "\n";
++ blksize = a;
++ }
++
++ for (i = 0; i < blksize; i++)
++ DWC_PRINT("%02x%s", *blk++, ((i & 3) == 3) ? " " : " ");
++ DWC_PRINT(suffix);
++#endif
++}
++
++/**
++ * Encrypts an array of bytes using the AES encryption engine.
++ * If <code>dst</code> == <code>src</code>, then the bytes will be encrypted
++ * in-place.
++ *
++ * @return 0 on success, negative error code on error.
++ */
++int dwc_wusb_aes_encrypt(u8 *src, u8 *key, u8 *dst)
++{
++ u8 block_t[16];
++ DWC_MEMSET(block_t, 0, 16);
++
++ return DWC_AES_CBC(src, 16, key, 16, block_t, dst);
++}
++
++/**
++ * The CCM-MAC-FUNCTION described in section 6.5 of the WUSB spec.
++ * This function takes a data string and returns the encrypted CBC
++ * Counter-mode MIC.
++ *
++ * @param key The 128-bit symmetric key.
++ * @param nonce The CCM nonce.
++ * @param label The unique 14-byte ASCII text label.
++ * @param bytes The byte array to be encrypted.
++ * @param len Length of the byte array.
++ * @param result Byte array to receive the 8-byte encrypted MIC.
++ */
++void dwc_wusb_cmf(u8 *key, u8 *nonce,
++ char *label, u8 *bytes, int len, u8 *result)
++{
++ u8 block_m[16];
++ u8 block_x[16];
++ u8 block_t[8];
++ int idx, blkNum;
++ u16 la = (u16)(len + 14);
++
++ /* Set the AES-128 key */
++ //dwc_aes_setkey(tfm, key, 16);
++
++ /* Fill block B0 from flags = 0x59, N, and l(m) = 0 */
++ block_m[0] = 0x59;
++ for (idx = 0; idx < 13; idx++)
++ block_m[idx + 1] = nonce[idx];
++ block_m[14] = 0;
++ block_m[15] = 0;
++
++ /* Produce the CBC IV */
++ dwc_wusb_aes_encrypt(block_m, key, block_x);
++ show_block(block_m, "CBC IV in: ", "\n", 0);
++ show_block(block_x, "CBC IV out:", "\n", 0);
++
++ /* Fill block B1 from l(a) = Blen + 14, and A */
++ block_x[0] ^= (u8)(la >> 8);
++ block_x[1] ^= (u8)la;
++ for (idx = 0; idx < 14; idx++)
++ block_x[idx + 2] ^= label[idx];
++ show_block(block_x, "After xor: ", "b1\n", 16);
++
++ dwc_wusb_aes_encrypt(block_x, key, block_x);
++ show_block(block_x, "After AES: ", "b1\n", 16);
++
++ idx = 0;
++ blkNum = 0;
++
++ /* Fill remaining blocks with B */
++ while (len-- > 0) {
++ block_x[idx] ^= *bytes++;
++ if (++idx >= 16) {
++ idx = 0;
++ show_block(block_x, "After xor: ", "\n", blkNum);
++ dwc_wusb_aes_encrypt(block_x, key, block_x);
++ show_block(block_x, "After AES: ", "\n", blkNum);
++ blkNum++;
++ }
++ }
++
++ /* Handle partial last block */
++ if (idx > 0) {
++ show_block(block_x, "After xor: ", "\n", blkNum);
++ dwc_wusb_aes_encrypt(block_x, key, block_x);
++ show_block(block_x, "After AES: ", "\n", blkNum);
++ }
++
++ /* Save the MIC tag */
++ DWC_MEMCPY(block_t, block_x, 8);
++ show_block(block_t, "MIC tag : ", NULL, 8);
++
++ /* Fill block A0 from flags = 0x01, N, and counter = 0 */
++ block_m[0] = 0x01;
++ block_m[14] = 0;
++ block_m[15] = 0;
++
++ /* Encrypt the counter */
++ dwc_wusb_aes_encrypt(block_m, key, block_x);
++ show_block(block_x, "CTR[MIC] : ", NULL, 8);
++
++ /* XOR with MIC tag */
++ for (idx = 0; idx < 8; idx++) {
++ block_t[idx] ^= block_x[idx];
++ }
++
++ /* Return result to caller */
++ DWC_MEMCPY(result, block_t, 8);
++ show_block(result, "CCM-MIC : ", NULL, 8);
++
++}
++
++/**
++ * The PRF function described in section 6.5 of the WUSB spec. This function
++ * concatenates MIC values returned from dwc_cmf() to create a value of
++ * the requested length.
++ *
++ * @param prf_len Length of the PRF function in bits (64, 128, or 256).
++ * @param key, nonce, label, bytes, len Same as for dwc_cmf().
++ * @param result Byte array to receive the result.
++ */
++void dwc_wusb_prf(int prf_len, u8 *key,
++ u8 *nonce, char *label, u8 *bytes, int len, u8 *result)
++{
++ int i;
++
++ nonce[0] = 0;
++ for (i = 0; i < prf_len >> 6; i++, nonce[0]++) {
++ dwc_wusb_cmf(key, nonce, label, bytes, len, result);
++ result += 8;
++ }
++}
++
++/**
++ * Fills in CCM Nonce per the WUSB spec.
++ *
++ * @param[in] haddr Host address.
++ * @param[in] daddr Device address.
++ * @param[in] tkid Session Key(PTK) identifier.
++ * @param[out] nonce Pointer to where the CCM Nonce output is to be written.
++ */
++void dwc_wusb_fill_ccm_nonce(uint16_t haddr, uint16_t daddr, uint8_t *tkid,
++ uint8_t *nonce)
++{
++
++ DWC_DEBUG("%s %x %x\n", __func__, daddr, haddr);
++
++ DWC_MEMSET(&nonce[0], 0, 16);
++
++ DWC_MEMCPY(&nonce[6], tkid, 3);
++ nonce[9] = daddr & 0xFF;
++ nonce[10] = (daddr >> 8) & 0xFF;
++ nonce[11] = haddr & 0xFF;
++ nonce[12] = (haddr >> 8) & 0xFF;
++
++ dump_bytes("CCM nonce", nonce, 16);
++}
++
++/**
++ * Generates a 16-byte cryptographic-grade random number for the Host/Device
++ * Nonce.
++ */
++void dwc_wusb_gen_nonce(uint16_t addr, uint8_t *nonce)
++{
++ uint8_t inonce[16];
++ uint32_t temp[4];
++
++ /* Fill in the Nonce */
++ DWC_MEMSET(&inonce[0], 0, sizeof(inonce));
++ inonce[9] = addr & 0xFF;
++ inonce[10] = (addr >> 8) & 0xFF;
++ inonce[11] = inonce[9];
++ inonce[12] = inonce[10];
++
++ /* Collect "randomness samples" */
++ DWC_RANDOM_BYTES((uint8_t *)temp, 16);
++
++ dwc_wusb_prf_128((uint8_t *)temp, nonce,
++ "Random Numbers", (uint8_t *)temp, sizeof(temp),
++ nonce);
++}
++
++/**
++ * Generates the Session Key (PTK) and Key Confirmation Key (KCK) per the
++ * WUSB spec.
++ *
++ * @param[in] ccm_nonce Pointer to CCM Nonce.
++ * @param[in] mk Master Key to derive the session from
++ * @param[in] hnonce Pointer to Host Nonce.
++ * @param[in] dnonce Pointer to Device Nonce.
++ * @param[out] kck Pointer to where the KCK output is to be written.
++ * @param[out] ptk Pointer to where the PTK output is to be written.
++ */
++void dwc_wusb_gen_key(uint8_t *ccm_nonce, uint8_t *mk, uint8_t *hnonce,
++ uint8_t *dnonce, uint8_t *kck, uint8_t *ptk)
++{
++ uint8_t idata[32];
++ uint8_t odata[32];
++
++ dump_bytes("ck", mk, 16);
++ dump_bytes("hnonce", hnonce, 16);
++ dump_bytes("dnonce", dnonce, 16);
++
++ /* The data is the HNonce and DNonce concatenated */
++ DWC_MEMCPY(&idata[0], hnonce, 16);
++ DWC_MEMCPY(&idata[16], dnonce, 16);
++
++ dwc_wusb_prf_256(mk, ccm_nonce, "Pair-wise keys", idata, 32, odata);
++
++ /* Low 16 bytes of the result is the KCK, high 16 is the PTK */
++ DWC_MEMCPY(kck, &odata[0], 16);
++ DWC_MEMCPY(ptk, &odata[16], 16);
++
++ dump_bytes("kck", kck, 16);
++ dump_bytes("ptk", ptk, 16);
++}
++
++/**
++ * Generates the Message Integrity Code over the Handshake data per the
++ * WUSB spec.
++ *
++ * @param ccm_nonce Pointer to CCM Nonce.
++ * @param kck Pointer to Key Confirmation Key.
++ * @param data Pointer to Handshake data to be checked.
++ * @param mic Pointer to where the MIC output is to be written.
++ */
++void dwc_wusb_gen_mic(uint8_t *ccm_nonce, uint8_t *kck,
++ uint8_t *data, uint8_t *mic)
++{
++
++ dwc_wusb_prf_64(kck, ccm_nonce, "out-of-bandMIC",
++ data, WUSB_HANDSHAKE_LEN_FOR_MIC, mic);
++}
++
++#endif /* DWC_CRYPTOLIB */
+diff -Nur linux-4.1.3/drivers/usb/host/dwc_common_port/dwc_crypto.h linux-xbian-rpi/drivers/usb/host/dwc_common_port/dwc_crypto.h
+--- linux-4.1.3/drivers/usb/host/dwc_common_port/dwc_crypto.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/usb/host/dwc_common_port/dwc_crypto.h 2015-07-28 01:20:58.441170694 +0200
+@@ -0,0 +1,111 @@
++/* =========================================================================
++ * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_crypto.h $
++ * $Revision: #3 $
++ * $Date: 2010/09/28 $
++ * $Change: 1596182 $
++ *
++ * Synopsys Portability Library Software and documentation
++ * (hereinafter, "Software") is an Unsupported proprietary work of
++ * Synopsys, Inc. unless otherwise expressly agreed to in writing
++ * between Synopsys and you.
++ *
++ * The Software IS NOT an item of Licensed Software or Licensed Product
++ * under any End User Software License Agreement or Agreement for
++ * Licensed Product with Synopsys or any supplement thereto. You are
++ * permitted to use and redistribute this Software in source and binary
++ * forms, with or without modification, provided that redistributions
++ * of source code must retain this notice. You may not view, use,
++ * disclose, copy or distribute this file or any information contained
++ * herein except pursuant to this license grant from Synopsys. If you
++ * do not agree with this notice, including the disclaimer below, then
++ * you are not authorized to use the Software.
++ *
++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
++ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL
++ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
++ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
++ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++ * DAMAGE.
++ * ========================================================================= */
++
++#ifndef _DWC_CRYPTO_H_
++#define _DWC_CRYPTO_H_
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/** @file
++ *
++ * This file contains declarations for the WUSB Cryptographic routines as
++ * defined in the WUSB spec. They are only to be used internally by the DWC UWB
++ * modules.
++ */
++
++#include "dwc_os.h"
++
++int dwc_wusb_aes_encrypt(u8 *src, u8 *key, u8 *dst);
++
++void dwc_wusb_cmf(u8 *key, u8 *nonce,
++ char *label, u8 *bytes, int len, u8 *result);
++void dwc_wusb_prf(int prf_len, u8 *key,
++ u8 *nonce, char *label, u8 *bytes, int len, u8 *result);
++
++/**
++ * The PRF-64 function described in section 6.5 of the WUSB spec.
++ *
++ * @param key, nonce, label, bytes, len, result Same as for dwc_prf().
++ */
++static inline void dwc_wusb_prf_64(u8 *key, u8 *nonce,
++ char *label, u8 *bytes, int len, u8 *result)
++{
++ dwc_wusb_prf(64, key, nonce, label, bytes, len, result);
++}
++
++/**
++ * The PRF-128 function described in section 6.5 of the WUSB spec.
++ *
++ * @param key, nonce, label, bytes, len, result Same as for dwc_prf().
++ */
++static inline void dwc_wusb_prf_128(u8 *key, u8 *nonce,
++ char *label, u8 *bytes, int len, u8 *result)
++{
++ dwc_wusb_prf(128, key, nonce, label, bytes, len, result);
++}
++
++/**
++ * The PRF-256 function described in section 6.5 of the WUSB spec.
++ *
++ * @param key, nonce, label, bytes, len, result Same as for dwc_prf().
++ */
++static inline void dwc_wusb_prf_256(u8 *key, u8 *nonce,
++ char *label, u8 *bytes, int len, u8 *result)
++{
++ dwc_wusb_prf(256, key, nonce, label, bytes, len, result);
++}
++
++
++void dwc_wusb_fill_ccm_nonce(uint16_t haddr, uint16_t daddr, uint8_t *tkid,
++ uint8_t *nonce);
++void dwc_wusb_gen_nonce(uint16_t addr,
++ uint8_t *nonce);
++
++void dwc_wusb_gen_key(uint8_t *ccm_nonce, uint8_t *mk,
++ uint8_t *hnonce, uint8_t *dnonce,
++ uint8_t *kck, uint8_t *ptk);
++
++
++void dwc_wusb_gen_mic(uint8_t *ccm_nonce, uint8_t
++ *kck, uint8_t *data, uint8_t *mic);
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* _DWC_CRYPTO_H_ */
+diff -Nur linux-4.1.3/drivers/usb/host/dwc_common_port/dwc_dh.c linux-xbian-rpi/drivers/usb/host/dwc_common_port/dwc_dh.c
+--- linux-4.1.3/drivers/usb/host/dwc_common_port/dwc_dh.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/usb/host/dwc_common_port/dwc_dh.c 2015-07-28 01:20:58.441170694 +0200
+@@ -0,0 +1,291 @@
++/* =========================================================================
++ * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_dh.c $
++ * $Revision: #3 $
++ * $Date: 2010/09/28 $
++ * $Change: 1596182 $
++ *
++ * Synopsys Portability Library Software and documentation
++ * (hereinafter, "Software") is an Unsupported proprietary work of
++ * Synopsys, Inc. unless otherwise expressly agreed to in writing
++ * between Synopsys and you.
++ *
++ * The Software IS NOT an item of Licensed Software or Licensed Product
++ * under any End User Software License Agreement or Agreement for
++ * Licensed Product with Synopsys or any supplement thereto. You are
++ * permitted to use and redistribute this Software in source and binary
++ * forms, with or without modification, provided that redistributions
++ * of source code must retain this notice. You may not view, use,
++ * disclose, copy or distribute this file or any information contained
++ * herein except pursuant to this license grant from Synopsys. If you
++ * do not agree with this notice, including the disclaimer below, then
++ * you are not authorized to use the Software.
++ *
++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
++ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL
++ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
++ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
++ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++ * DAMAGE.
++ * ========================================================================= */
++#ifdef DWC_CRYPTOLIB
++
++#ifndef CONFIG_MACH_IPMATE
++
++#include "dwc_dh.h"
++#include "dwc_modpow.h"
++
++#ifdef DEBUG
++/* This function prints out a buffer in the format described in the Association
++ * Model specification. */
++static void dh_dump(char *str, void *_num, int len)
++{
++ uint8_t *num = _num;
++ int i;
++ DWC_PRINTF("%s\n", str);
++ for (i = 0; i < len; i ++) {
++ DWC_PRINTF("%02x", num[i]);
++ if (((i + 1) % 2) == 0) DWC_PRINTF(" ");
++ if (((i + 1) % 26) == 0) DWC_PRINTF("\n");
++ }
++
++ DWC_PRINTF("\n");
++}
++#else
++#define dh_dump(_x...) do {; } while(0)
++#endif
++
++/* Constant g value */
++static __u32 dh_g[] = {
++ 0x02000000,
++};
++
++/* Constant p value */
++static __u32 dh_p[] = {
++ 0xFFFFFFFF, 0xFFFFFFFF, 0xA2DA0FC9, 0x34C26821, 0x8B62C6C4, 0xD11CDC80, 0x084E0229, 0x74CC678A,
++ 0xA6BE0B02, 0x229B133B, 0x79084A51, 0xDD04348E, 0xB31995EF, 0x1B433ACD, 0x6D0A2B30, 0x37145FF2,
++ 0x6D35E14F, 0x45C2516D, 0x76B585E4, 0xC67E5E62, 0xE9424CF4, 0x6BED37A6, 0xB65CFF0B, 0xEDB706F4,
++ 0xFB6B38EE, 0xA59F895A, 0x11249FAE, 0xE61F4B7C, 0x51662849, 0x3D5BE4EC, 0xB87C00C2, 0x05BF63A1,
++ 0x3648DA98, 0x9AD3551C, 0xA83F1669, 0x5FCF24FD, 0x235D6583, 0x96ADA3DC, 0x56F3621C, 0xBB528520,
++ 0x0729D59E, 0x6D969670, 0x4E350C67, 0x0498BC4A, 0x086C74F1, 0x7C2118CA, 0x465E9032, 0x3BCE362E,
++ 0x2C779EE3, 0x03860E18, 0xA283279B, 0x8FA207EC, 0xF05DC5B5, 0xC9524C6F, 0xF6CB2BDE, 0x18175895,
++ 0x7C499539, 0xE56A95EA, 0x1826D215, 0x1005FA98, 0x5A8E7215, 0x2DC4AA8A, 0x0D1733AD, 0x337A5004,
++ 0xAB2155A8, 0x64BA1CDF, 0x0485FBEC, 0x0AEFDB58, 0x5771EA8A, 0x7D0C065D, 0x850F97B3, 0xC7E4E1A6,
++ 0x8CAEF5AB, 0xD73309DB, 0xE0948C1E, 0x9D61254A, 0x26D2E3CE, 0x6BEED21A, 0x06FA2FF1, 0x64088AD9,
++ 0x730276D8, 0x646AC83E, 0x182B1F52, 0x0C207B17, 0x5717E1BB, 0x6C5D617A, 0xC0880977, 0xE246D9BA,
++ 0xA04FE208, 0x31ABE574, 0xFC5BDB43, 0x8E10FDE0, 0x20D1824B, 0xCAD23AA9, 0xFFFFFFFF, 0xFFFFFFFF,
++};
++
++static void dh_swap_bytes(void *_in, void *_out, uint32_t len)
++{
++ uint8_t *in = _in;
++ uint8_t *out = _out;
++ int i;
++ for (i=0; i<len; i++) {
++ out[i] = in[len-1-i];
++ }
++}
++
++/* Computes the modular exponentiation (num^exp % mod). num, exp, and mod are
++ * big endian numbers of size len, in bytes. Each len value must be a multiple
++ * of 4. */
++int dwc_dh_modpow(void *mem_ctx, void *num, uint32_t num_len,
++ void *exp, uint32_t exp_len,
++ void *mod, uint32_t mod_len,
++ void *out)
++{
++ /* modpow() takes little endian numbers. AM uses big-endian. This
++ * function swaps bytes of numbers before passing onto modpow. */
++
++ int retval = 0;
++ uint32_t *result;
++
++ uint32_t *bignum_num = dwc_alloc(mem_ctx, num_len + 4);
++ uint32_t *bignum_exp = dwc_alloc(mem_ctx, exp_len + 4);
++ uint32_t *bignum_mod = dwc_alloc(mem_ctx, mod_len + 4);
++
++ dh_swap_bytes(num, &bignum_num[1], num_len);
++ bignum_num[0] = num_len / 4;
++
++ dh_swap_bytes(exp, &bignum_exp[1], exp_len);
++ bignum_exp[0] = exp_len / 4;
++
++ dh_swap_bytes(mod, &bignum_mod[1], mod_len);
++ bignum_mod[0] = mod_len / 4;
++
++ result = dwc_modpow(mem_ctx, bignum_num, bignum_exp, bignum_mod);
++ if (!result) {
++ retval = -1;
++ goto dh_modpow_nomem;
++ }
++
++ dh_swap_bytes(&result[1], out, result[0] * 4);
++ dwc_free(mem_ctx, result);
++
++ dh_modpow_nomem:
++ dwc_free(mem_ctx, bignum_num);
++ dwc_free(mem_ctx, bignum_exp);
++ dwc_free(mem_ctx, bignum_mod);
++ return retval;
++}
++
++
++int dwc_dh_pk(void *mem_ctx, uint8_t nd, uint8_t *exp, uint8_t *pk, uint8_t *hash)
++{
++ int retval;
++ uint8_t m3[385];
++
++#ifndef DH_TEST_VECTORS
++ DWC_RANDOM_BYTES(exp, 32);
++#endif
++
++ /* Compute the pkd */
++ if ((retval = dwc_dh_modpow(mem_ctx, dh_g, 4,
++ exp, 32,
++ dh_p, 384, pk))) {
++ return retval;
++ }
++
++ m3[384] = nd;
++ DWC_MEMCPY(&m3[0], pk, 384);
++ DWC_SHA256(m3, 385, hash);
++
++ dh_dump("PK", pk, 384);
++ dh_dump("SHA-256(M3)", hash, 32);
++ return 0;
++}
++
++int dwc_dh_derive_keys(void *mem_ctx, uint8_t nd, uint8_t *pkh, uint8_t *pkd,
++ uint8_t *exp, int is_host,
++ char *dd, uint8_t *ck, uint8_t *kdk)
++{
++ int retval;
++ uint8_t mv[784];
++ uint8_t sha_result[32];
++ uint8_t dhkey[384];
++ uint8_t shared_secret[384];
++ char *message;
++ uint32_t vd;
++
++ uint8_t *pk;
++
++ if (is_host) {
++ pk = pkd;
++ }
++ else {
++ pk = pkh;
++ }
++
++ if ((retval = dwc_dh_modpow(mem_ctx, pk, 384,
++ exp, 32,
++ dh_p, 384, shared_secret))) {
++ return retval;
++ }
++ dh_dump("Shared Secret", shared_secret, 384);
++
++ DWC_SHA256(shared_secret, 384, dhkey);
++ dh_dump("DHKEY", dhkey, 384);
++
++ DWC_MEMCPY(&mv[0], pkd, 384);
++ DWC_MEMCPY(&mv[384], pkh, 384);
++ DWC_MEMCPY(&mv[768], "displayed digest", 16);
++ dh_dump("MV", mv, 784);
++
++ DWC_SHA256(mv, 784, sha_result);
++ dh_dump("SHA-256(MV)", sha_result, 32);
++ dh_dump("First 32-bits of SHA-256(MV)", sha_result, 4);
++
++ dh_swap_bytes(sha_result, &vd, 4);
++#ifdef DEBUG
++ DWC_PRINTF("Vd (decimal) = %d\n", vd);
++#endif
++
++ switch (nd) {
++ case 2:
++ vd = vd % 100;
++ DWC_SPRINTF(dd, "%02d", vd);
++ break;
++ case 3:
++ vd = vd % 1000;
++ DWC_SPRINTF(dd, "%03d", vd);
++ break;
++ case 4:
++ vd = vd % 10000;
++ DWC_SPRINTF(dd, "%04d", vd);
++ break;
++ }
++#ifdef DEBUG
++ DWC_PRINTF("Display Digits: %s\n", dd);
++#endif
++
++ message = "connection key";
++ DWC_HMAC_SHA256(message, DWC_STRLEN(message), dhkey, 32, sha_result);
++ dh_dump("HMAC(SHA-256, DHKey, connection key)", sha_result, 32);
++ DWC_MEMCPY(ck, sha_result, 16);
++
++ message = "key derivation key";
++ DWC_HMAC_SHA256(message, DWC_STRLEN(message), dhkey, 32, sha_result);
++ dh_dump("HMAC(SHA-256, DHKey, key derivation key)", sha_result, 32);
++ DWC_MEMCPY(kdk, sha_result, 32);
++
++ return 0;
++}
++
++
++#ifdef DH_TEST_VECTORS
++
++static __u8 dh_a[] = {
++ 0x44, 0x00, 0x51, 0xd6,
++ 0xf0, 0xb5, 0x5e, 0xa9,
++ 0x67, 0xab, 0x31, 0xc6,
++ 0x8a, 0x8b, 0x5e, 0x37,
++ 0xd9, 0x10, 0xda, 0xe0,
++ 0xe2, 0xd4, 0x59, 0xa4,
++ 0x86, 0x45, 0x9c, 0xaa,
++ 0xdf, 0x36, 0x75, 0x16,
++};
++
++static __u8 dh_b[] = {
++ 0x5d, 0xae, 0xc7, 0x86,
++ 0x79, 0x80, 0xa3, 0x24,
++ 0x8c, 0xe3, 0x57, 0x8f,
++ 0xc7, 0x5f, 0x1b, 0x0f,
++ 0x2d, 0xf8, 0x9d, 0x30,
++ 0x6f, 0xa4, 0x52, 0xcd,
++ 0xe0, 0x7a, 0x04, 0x8a,
++ 0xde, 0xd9, 0x26, 0x56,
++};
++
++void dwc_run_dh_test_vectors(void *mem_ctx)
++{
++ uint8_t pkd[384];
++ uint8_t pkh[384];
++ uint8_t hashd[32];
++ uint8_t hashh[32];
++ uint8_t ck[16];
++ uint8_t kdk[32];
++ char dd[5];
++
++ DWC_PRINTF("\n\n\nDH_TEST_VECTORS\n\n");
++
++ /* compute the PKd and SHA-256(PKd || Nd) */
++ DWC_PRINTF("Computing PKd\n");
++ dwc_dh_pk(mem_ctx, 2, dh_a, pkd, hashd);
++
++ /* compute the PKd and SHA-256(PKh || Nd) */
++ DWC_PRINTF("Computing PKh\n");
++ dwc_dh_pk(mem_ctx, 2, dh_b, pkh, hashh);
++
++ /* compute the dhkey */
++ dwc_dh_derive_keys(mem_ctx, 2, pkh, pkd, dh_a, 0, dd, ck, kdk);
++}
++#endif /* DH_TEST_VECTORS */
++
++#endif /* !CONFIG_MACH_IPMATE */
++
++#endif /* DWC_CRYPTOLIB */
+diff -Nur linux-4.1.3/drivers/usb/host/dwc_common_port/dwc_dh.h linux-xbian-rpi/drivers/usb/host/dwc_common_port/dwc_dh.h
+--- linux-4.1.3/drivers/usb/host/dwc_common_port/dwc_dh.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/usb/host/dwc_common_port/dwc_dh.h 2015-07-28 01:20:58.441170694 +0200
+@@ -0,0 +1,106 @@
++/* =========================================================================
++ * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_dh.h $
++ * $Revision: #4 $
++ * $Date: 2010/09/28 $
++ * $Change: 1596182 $
++ *
++ * Synopsys Portability Library Software and documentation
++ * (hereinafter, "Software") is an Unsupported proprietary work of
++ * Synopsys, Inc. unless otherwise expressly agreed to in writing
++ * between Synopsys and you.
++ *
++ * The Software IS NOT an item of Licensed Software or Licensed Product
++ * under any End User Software License Agreement or Agreement for
++ * Licensed Product with Synopsys or any supplement thereto. You are
++ * permitted to use and redistribute this Software in source and binary
++ * forms, with or without modification, provided that redistributions
++ * of source code must retain this notice. You may not view, use,
++ * disclose, copy or distribute this file or any information contained
++ * herein except pursuant to this license grant from Synopsys. If you
++ * do not agree with this notice, including the disclaimer below, then
++ * you are not authorized to use the Software.
++ *
++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
++ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL
++ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
++ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
++ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++ * DAMAGE.
++ * ========================================================================= */
++#ifndef _DWC_DH_H_
++#define _DWC_DH_H_
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++#include "dwc_os.h"
++
++/** @file
++ *
++ * This file defines the common functions on device and host for performing
++ * numeric association as defined in the WUSB spec. They are only to be
++ * used internally by the DWC UWB modules. */
++
++extern int dwc_dh_sha256(uint8_t *message, uint32_t len, uint8_t *out);
++extern int dwc_dh_hmac_sha256(uint8_t *message, uint32_t messagelen,
++ uint8_t *key, uint32_t keylen,
++ uint8_t *out);
++extern int dwc_dh_modpow(void *mem_ctx, void *num, uint32_t num_len,
++ void *exp, uint32_t exp_len,
++ void *mod, uint32_t mod_len,
++ void *out);
++
++/** Computes PKD or PKH, and SHA-256(PKd || Nd)
++ *
++ * PK = g^exp mod p.
++ *
++ * Input:
++ * Nd = Number of digits on the device.
++ *
++ * Output:
++ * exp = A 32-byte buffer to be filled with a randomly generated number.
++ * used as either A or B.
++ * pk = A 384-byte buffer to be filled with the PKH or PKD.
++ * hash = A 32-byte buffer to be filled with SHA-256(PK || ND).
++ */
++extern int dwc_dh_pk(void *mem_ctx, uint8_t nd, uint8_t *exp, uint8_t *pkd, uint8_t *hash);
++
++/** Computes the DHKEY, and VD.
++ *
++ * If called from host, then it will comput DHKEY=PKD^exp % p.
++ * If called from device, then it will comput DHKEY=PKH^exp % p.
++ *
++ * Input:
++ * pkd = The PKD value.
++ * pkh = The PKH value.
++ * exp = The A value (if device) or B value (if host) generated in dwc_wudev_dh_pk.
++ * is_host = Set to non zero if a WUSB host is calling this function.
++ *
++ * Output:
++
++ * dd = A pointer to an buffer to be set to the displayed digits string to be shown
++ * to the user. This buffer should be at 5 bytes long to hold 4 digits plus a
++ * null termination character. This buffer can be used directly for display.
++ * ck = A 16-byte buffer to be filled with the CK.
++ * kdk = A 32-byte buffer to be filled with the KDK.
++ */
++extern int dwc_dh_derive_keys(void *mem_ctx, uint8_t nd, uint8_t *pkh, uint8_t *pkd,
++ uint8_t *exp, int is_host,
++ char *dd, uint8_t *ck, uint8_t *kdk);
++
++#ifdef DH_TEST_VECTORS
++extern void dwc_run_dh_test_vectors(void);
++#endif
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* _DWC_DH_H_ */
+diff -Nur linux-4.1.3/drivers/usb/host/dwc_common_port/dwc_list.h linux-xbian-rpi/drivers/usb/host/dwc_common_port/dwc_list.h
+--- linux-4.1.3/drivers/usb/host/dwc_common_port/dwc_list.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/usb/host/dwc_common_port/dwc_list.h 2015-07-28 01:20:58.441170694 +0200
+@@ -0,0 +1,594 @@
++/* $OpenBSD: queue.h,v 1.26 2004/05/04 16:59:32 grange Exp $ */
++/* $NetBSD: queue.h,v 1.11 1996/05/16 05:17:14 mycroft Exp $ */
++
++/*
++ * Copyright (c) 1991, 1993
++ * The Regents of the University of California. All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ * 1. Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ * 2. Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * 3. Neither the name of the University nor the names of its contributors
++ * may be used to endorse or promote products derived from this software
++ * without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
++ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
++ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
++ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
++ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
++ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
++ * SUCH DAMAGE.
++ *
++ * @(#)queue.h 8.5 (Berkeley) 8/20/94
++ */
++
++#ifndef _DWC_LIST_H_
++#define _DWC_LIST_H_
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/** @file
++ *
++ * This file defines linked list operations. It is derived from BSD with
++ * only the MACRO names being prefixed with DWC_. This is because a few of
++ * these names conflict with those on Linux. For documentation on use, see the
++ * inline comments in the source code. The original license for this source
++ * code applies and is preserved in the dwc_list.h source file.
++ */
++
++/*
++ * This file defines five types of data structures: singly-linked lists,
++ * lists, simple queues, tail queues, and circular queues.
++ *
++ *
++ * A singly-linked list is headed by a single forward pointer. The elements
++ * are singly linked for minimum space and pointer manipulation overhead at
++ * the expense of O(n) removal for arbitrary elements. New elements can be
++ * added to the list after an existing element or at the head of the list.
++ * Elements being removed from the head of the list should use the explicit
++ * macro for this purpose for optimum efficiency. A singly-linked list may
++ * only be traversed in the forward direction. Singly-linked lists are ideal
++ * for applications with large datasets and few or no removals or for
++ * implementing a LIFO queue.
++ *
++ * A list is headed by a single forward pointer (or an array of forward
++ * pointers for a hash table header). The elements are doubly linked
++ * so that an arbitrary element can be removed without a need to
++ * traverse the list. New elements can be added to the list before
++ * or after an existing element or at the head of the list. A list
++ * may only be traversed in the forward direction.
++ *
++ * A simple queue is headed by a pair of pointers, one the head of the
++ * list and the other to the tail of the list. The elements are singly
++ * linked to save space, so elements can only be removed from the
++ * head of the list. New elements can be added to the list before or after
++ * an existing element, at the head of the list, or at the end of the
++ * list. A simple queue may only be traversed in the forward direction.
++ *
++ * A tail queue is headed by a pair of pointers, one to the head of the
++ * list and the other to the tail of the list. The elements are doubly
++ * linked so that an arbitrary element can be removed without a need to
++ * traverse the list. New elements can be added to the list before or
++ * after an existing element, at the head of the list, or at the end of
++ * the list. A tail queue may be traversed in either direction.
++ *
++ * A circle queue is headed by a pair of pointers, one to the head of the
++ * list and the other to the tail of the list. The elements are doubly
++ * linked so that an arbitrary element can be removed without a need to
++ * traverse the list. New elements can be added to the list before or after
++ * an existing element, at the head of the list, or at the end of the list.
++ * A circle queue may be traversed in either direction, but has a more
++ * complex end of list detection.
++ *
++ * For details on the use of these macros, see the queue(3) manual page.
++ */
++
++/*
++ * Double-linked List.
++ */
++
++typedef struct dwc_list_link {
++ struct dwc_list_link *next;
++ struct dwc_list_link *prev;
++} dwc_list_link_t;
++
++#define DWC_LIST_INIT(link) do { \
++ (link)->next = (link); \
++ (link)->prev = (link); \
++} while (0)
++
++#define DWC_LIST_FIRST(link) ((link)->next)
++#define DWC_LIST_LAST(link) ((link)->prev)
++#define DWC_LIST_END(link) (link)
++#define DWC_LIST_NEXT(link) ((link)->next)
++#define DWC_LIST_PREV(link) ((link)->prev)
++#define DWC_LIST_EMPTY(link) \
++ (DWC_LIST_FIRST(link) == DWC_LIST_END(link))
++#define DWC_LIST_ENTRY(link, type, field) \
++ (type *)((uint8_t *)(link) - (size_t)(&((type *)0)->field))
++
++#if 0
++#define DWC_LIST_INSERT_HEAD(list, link) do { \
++ (link)->next = (list)->next; \
++ (link)->prev = (list); \
++ (list)->next->prev = (link); \
++ (list)->next = (link); \
++} while (0)
++
++#define DWC_LIST_INSERT_TAIL(list, link) do { \
++ (link)->next = (list); \
++ (link)->prev = (list)->prev; \
++ (list)->prev->next = (link); \
++ (list)->prev = (link); \
++} while (0)
++#else
++#define DWC_LIST_INSERT_HEAD(list, link) do { \
++ dwc_list_link_t *__next__ = (list)->next; \
++ __next__->prev = (link); \
++ (link)->next = __next__; \
++ (link)->prev = (list); \
++ (list)->next = (link); \
++} while (0)
++
++#define DWC_LIST_INSERT_TAIL(list, link) do { \
++ dwc_list_link_t *__prev__ = (list)->prev; \
++ (list)->prev = (link); \
++ (link)->next = (list); \
++ (link)->prev = __prev__; \
++ __prev__->next = (link); \
++} while (0)
++#endif
++
++#if 0
++static inline void __list_add(struct list_head *new,
++ struct list_head *prev,
++ struct list_head *next)
++{
++ next->prev = new;
++ new->next = next;
++ new->prev = prev;
++ prev->next = new;
++}
++
++static inline void list_add(struct list_head *new, struct list_head *head)
++{
++ __list_add(new, head, head->next);
++}
++
++static inline void list_add_tail(struct list_head *new, struct list_head *head)
++{
++ __list_add(new, head->prev, head);
++}
++
++static inline void __list_del(struct list_head * prev, struct list_head * next)
++{
++ next->prev = prev;
++ prev->next = next;
++}
++
++static inline void list_del(struct list_head *entry)
++{
++ __list_del(entry->prev, entry->next);
++ entry->next = LIST_POISON1;
++ entry->prev = LIST_POISON2;
++}
++#endif
++
++#define DWC_LIST_REMOVE(link) do { \
++ (link)->next->prev = (link)->prev; \
++ (link)->prev->next = (link)->next; \
++} while (0)
++
++#define DWC_LIST_REMOVE_INIT(link) do { \
++ DWC_LIST_REMOVE(link); \
++ DWC_LIST_INIT(link); \
++} while (0)
++
++#define DWC_LIST_MOVE_HEAD(list, link) do { \
++ DWC_LIST_REMOVE(link); \
++ DWC_LIST_INSERT_HEAD(list, link); \
++} while (0)
++
++#define DWC_LIST_MOVE_TAIL(list, link) do { \
++ DWC_LIST_REMOVE(link); \
++ DWC_LIST_INSERT_TAIL(list, link); \
++} while (0)
++
++#define DWC_LIST_FOREACH(var, list) \
++ for((var) = DWC_LIST_FIRST(list); \
++ (var) != DWC_LIST_END(list); \
++ (var) = DWC_LIST_NEXT(var))
++
++#define DWC_LIST_FOREACH_SAFE(var, var2, list) \
++ for((var) = DWC_LIST_FIRST(list), (var2) = DWC_LIST_NEXT(var); \
++ (var) != DWC_LIST_END(list); \
++ (var) = (var2), (var2) = DWC_LIST_NEXT(var2))
++
++#define DWC_LIST_FOREACH_REVERSE(var, list) \
++ for((var) = DWC_LIST_LAST(list); \
++ (var) != DWC_LIST_END(list); \
++ (var) = DWC_LIST_PREV(var))
++
++/*
++ * Singly-linked List definitions.
++ */
++#define DWC_SLIST_HEAD(name, type) \
++struct name { \
++ struct type *slh_first; /* first element */ \
++}
++
++#define DWC_SLIST_HEAD_INITIALIZER(head) \
++ { NULL }
++
++#define DWC_SLIST_ENTRY(type) \
++struct { \
++ struct type *sle_next; /* next element */ \
++}
++
++/*
++ * Singly-linked List access methods.
++ */
++#define DWC_SLIST_FIRST(head) ((head)->slh_first)
++#define DWC_SLIST_END(head) NULL
++#define DWC_SLIST_EMPTY(head) (SLIST_FIRST(head) == SLIST_END(head))
++#define DWC_SLIST_NEXT(elm, field) ((elm)->field.sle_next)
++
++#define DWC_SLIST_FOREACH(var, head, field) \
++ for((var) = SLIST_FIRST(head); \
++ (var) != SLIST_END(head); \
++ (var) = SLIST_NEXT(var, field))
++
++#define DWC_SLIST_FOREACH_PREVPTR(var, varp, head, field) \
++ for((varp) = &SLIST_FIRST((head)); \
++ ((var) = *(varp)) != SLIST_END(head); \
++ (varp) = &SLIST_NEXT((var), field))
++
++/*
++ * Singly-linked List functions.
++ */
++#define DWC_SLIST_INIT(head) { \
++ SLIST_FIRST(head) = SLIST_END(head); \
++}
++
++#define DWC_SLIST_INSERT_AFTER(slistelm, elm, field) do { \
++ (elm)->field.sle_next = (slistelm)->field.sle_next; \
++ (slistelm)->field.sle_next = (elm); \
++} while (0)
++
++#define DWC_SLIST_INSERT_HEAD(head, elm, field) do { \
++ (elm)->field.sle_next = (head)->slh_first; \
++ (head)->slh_first = (elm); \
++} while (0)
++
++#define DWC_SLIST_REMOVE_NEXT(head, elm, field) do { \
++ (elm)->field.sle_next = (elm)->field.sle_next->field.sle_next; \
++} while (0)
++
++#define DWC_SLIST_REMOVE_HEAD(head, field) do { \
++ (head)->slh_first = (head)->slh_first->field.sle_next; \
++} while (0)
++
++#define DWC_SLIST_REMOVE(head, elm, type, field) do { \
++ if ((head)->slh_first == (elm)) { \
++ SLIST_REMOVE_HEAD((head), field); \
++ } \
++ else { \
++ struct type *curelm = (head)->slh_first; \
++ while( curelm->field.sle_next != (elm) ) \
++ curelm = curelm->field.sle_next; \
++ curelm->field.sle_next = \
++ curelm->field.sle_next->field.sle_next; \
++ } \
++} while (0)
++
++/*
++ * Simple queue definitions.
++ */
++#define DWC_SIMPLEQ_HEAD(name, type) \
++struct name { \
++ struct type *sqh_first; /* first element */ \
++ struct type **sqh_last; /* addr of last next element */ \
++}
++
++#define DWC_SIMPLEQ_HEAD_INITIALIZER(head) \
++ { NULL, &(head).sqh_first }
++
++#define DWC_SIMPLEQ_ENTRY(type) \
++struct { \
++ struct type *sqe_next; /* next element */ \
++}
++
++/*
++ * Simple queue access methods.
++ */
++#define DWC_SIMPLEQ_FIRST(head) ((head)->sqh_first)
++#define DWC_SIMPLEQ_END(head) NULL
++#define DWC_SIMPLEQ_EMPTY(head) (SIMPLEQ_FIRST(head) == SIMPLEQ_END(head))
++#define DWC_SIMPLEQ_NEXT(elm, field) ((elm)->field.sqe_next)
++
++#define DWC_SIMPLEQ_FOREACH(var, head, field) \
++ for((var) = SIMPLEQ_FIRST(head); \
++ (var) != SIMPLEQ_END(head); \
++ (var) = SIMPLEQ_NEXT(var, field))
++
++/*
++ * Simple queue functions.
++ */
++#define DWC_SIMPLEQ_INIT(head) do { \
++ (head)->sqh_first = NULL; \
++ (head)->sqh_last = &(head)->sqh_first; \
++} while (0)
++
++#define DWC_SIMPLEQ_INSERT_HEAD(head, elm, field) do { \
++ if (((elm)->field.sqe_next = (head)->sqh_first) == NULL) \
++ (head)->sqh_last = &(elm)->field.sqe_next; \
++ (head)->sqh_first = (elm); \
++} while (0)
++
++#define DWC_SIMPLEQ_INSERT_TAIL(head, elm, field) do { \
++ (elm)->field.sqe_next = NULL; \
++ *(head)->sqh_last = (elm); \
++ (head)->sqh_last = &(elm)->field.sqe_next; \
++} while (0)
++
++#define DWC_SIMPLEQ_INSERT_AFTER(head, listelm, elm, field) do { \
++ if (((elm)->field.sqe_next = (listelm)->field.sqe_next) == NULL)\
++ (head)->sqh_last = &(elm)->field.sqe_next; \
++ (listelm)->field.sqe_next = (elm); \
++} while (0)
++
++#define DWC_SIMPLEQ_REMOVE_HEAD(head, field) do { \
++ if (((head)->sqh_first = (head)->sqh_first->field.sqe_next) == NULL) \
++ (head)->sqh_last = &(head)->sqh_first; \
++} while (0)
++
++/*
++ * Tail queue definitions.
++ */
++#define DWC_TAILQ_HEAD(name, type) \
++struct name { \
++ struct type *tqh_first; /* first element */ \
++ struct type **tqh_last; /* addr of last next element */ \
++}
++
++#define DWC_TAILQ_HEAD_INITIALIZER(head) \
++ { NULL, &(head).tqh_first }
++
++#define DWC_TAILQ_ENTRY(type) \
++struct { \
++ struct type *tqe_next; /* next element */ \
++ struct type **tqe_prev; /* address of previous next element */ \
++}
++
++/*
++ * tail queue access methods
++ */
++#define DWC_TAILQ_FIRST(head) ((head)->tqh_first)
++#define DWC_TAILQ_END(head) NULL
++#define DWC_TAILQ_NEXT(elm, field) ((elm)->field.tqe_next)
++#define DWC_TAILQ_LAST(head, headname) \
++ (*(((struct headname *)((head)->tqh_last))->tqh_last))
++/* XXX */
++#define DWC_TAILQ_PREV(elm, headname, field) \
++ (*(((struct headname *)((elm)->field.tqe_prev))->tqh_last))
++#define DWC_TAILQ_EMPTY(head) \
++ (DWC_TAILQ_FIRST(head) == DWC_TAILQ_END(head))
++
++#define DWC_TAILQ_FOREACH(var, head, field) \
++ for ((var) = DWC_TAILQ_FIRST(head); \
++ (var) != DWC_TAILQ_END(head); \
++ (var) = DWC_TAILQ_NEXT(var, field))
++
++#define DWC_TAILQ_FOREACH_REVERSE(var, head, headname, field) \
++ for ((var) = DWC_TAILQ_LAST(head, headname); \
++ (var) != DWC_TAILQ_END(head); \
++ (var) = DWC_TAILQ_PREV(var, headname, field))
++
++/*
++ * Tail queue functions.
++ */
++#define DWC_TAILQ_INIT(head) do { \
++ (head)->tqh_first = NULL; \
++ (head)->tqh_last = &(head)->tqh_first; \
++} while (0)
++
++#define DWC_TAILQ_INSERT_HEAD(head, elm, field) do { \
++ if (((elm)->field.tqe_next = (head)->tqh_first) != NULL) \
++ (head)->tqh_first->field.tqe_prev = \
++ &(elm)->field.tqe_next; \
++ else \
++ (head)->tqh_last = &(elm)->field.tqe_next; \
++ (head)->tqh_first = (elm); \
++ (elm)->field.tqe_prev = &(head)->tqh_first; \
++} while (0)
++
++#define DWC_TAILQ_INSERT_TAIL(head, elm, field) do { \
++ (elm)->field.tqe_next = NULL; \
++ (elm)->field.tqe_prev = (head)->tqh_last; \
++ *(head)->tqh_last = (elm); \
++ (head)->tqh_last = &(elm)->field.tqe_next; \
++} while (0)
++
++#define DWC_TAILQ_INSERT_AFTER(head, listelm, elm, field) do { \
++ if (((elm)->field.tqe_next = (listelm)->field.tqe_next) != NULL)\
++ (elm)->field.tqe_next->field.tqe_prev = \
++ &(elm)->field.tqe_next; \
++ else \
++ (head)->tqh_last = &(elm)->field.tqe_next; \
++ (listelm)->field.tqe_next = (elm); \
++ (elm)->field.tqe_prev = &(listelm)->field.tqe_next; \
++} while (0)
++
++#define DWC_TAILQ_INSERT_BEFORE(listelm, elm, field) do { \
++ (elm)->field.tqe_prev = (listelm)->field.tqe_prev; \
++ (elm)->field.tqe_next = (listelm); \
++ *(listelm)->field.tqe_prev = (elm); \
++ (listelm)->field.tqe_prev = &(elm)->field.tqe_next; \
++} while (0)
++
++#define DWC_TAILQ_REMOVE(head, elm, field) do { \
++ if (((elm)->field.tqe_next) != NULL) \
++ (elm)->field.tqe_next->field.tqe_prev = \
++ (elm)->field.tqe_prev; \
++ else \
++ (head)->tqh_last = (elm)->field.tqe_prev; \
++ *(elm)->field.tqe_prev = (elm)->field.tqe_next; \
++} while (0)
++
++#define DWC_TAILQ_REPLACE(head, elm, elm2, field) do { \
++ if (((elm2)->field.tqe_next = (elm)->field.tqe_next) != NULL) \
++ (elm2)->field.tqe_next->field.tqe_prev = \
++ &(elm2)->field.tqe_next; \
++ else \
++ (head)->tqh_last = &(elm2)->field.tqe_next; \
++ (elm2)->field.tqe_prev = (elm)->field.tqe_prev; \
++ *(elm2)->field.tqe_prev = (elm2); \
++} while (0)
++
++/*
++ * Circular queue definitions.
++ */
++#define DWC_CIRCLEQ_HEAD(name, type) \
++struct name { \
++ struct type *cqh_first; /* first element */ \
++ struct type *cqh_last; /* last element */ \
++}
++
++#define DWC_CIRCLEQ_HEAD_INITIALIZER(head) \
++ { DWC_CIRCLEQ_END(&head), DWC_CIRCLEQ_END(&head) }
++
++#define DWC_CIRCLEQ_ENTRY(type) \
++struct { \
++ struct type *cqe_next; /* next element */ \
++ struct type *cqe_prev; /* previous element */ \
++}
++
++/*
++ * Circular queue access methods
++ */
++#define DWC_CIRCLEQ_FIRST(head) ((head)->cqh_first)
++#define DWC_CIRCLEQ_LAST(head) ((head)->cqh_last)
++#define DWC_CIRCLEQ_END(head) ((void *)(head))
++#define DWC_CIRCLEQ_NEXT(elm, field) ((elm)->field.cqe_next)
++#define DWC_CIRCLEQ_PREV(elm, field) ((elm)->field.cqe_prev)
++#define DWC_CIRCLEQ_EMPTY(head) \
++ (DWC_CIRCLEQ_FIRST(head) == DWC_CIRCLEQ_END(head))
++
++#define DWC_CIRCLEQ_EMPTY_ENTRY(elm, field) (((elm)->field.cqe_next == NULL) && ((elm)->field.cqe_prev == NULL))
++
++#define DWC_CIRCLEQ_FOREACH(var, head, field) \
++ for((var) = DWC_CIRCLEQ_FIRST(head); \
++ (var) != DWC_CIRCLEQ_END(head); \
++ (var) = DWC_CIRCLEQ_NEXT(var, field))
++
++#define DWC_CIRCLEQ_FOREACH_SAFE(var, var2, head, field) \
++ for((var) = DWC_CIRCLEQ_FIRST(head), var2 = DWC_CIRCLEQ_NEXT(var, field); \
++ (var) != DWC_CIRCLEQ_END(head); \
++ (var) = var2, var2 = DWC_CIRCLEQ_NEXT(var, field))
++
++#define DWC_CIRCLEQ_FOREACH_REVERSE(var, head, field) \
++ for((var) = DWC_CIRCLEQ_LAST(head); \
++ (var) != DWC_CIRCLEQ_END(head); \
++ (var) = DWC_CIRCLEQ_PREV(var, field))
++
++/*
++ * Circular queue functions.
++ */
++#define DWC_CIRCLEQ_INIT(head) do { \
++ (head)->cqh_first = DWC_CIRCLEQ_END(head); \
++ (head)->cqh_last = DWC_CIRCLEQ_END(head); \
++} while (0)
++
++#define DWC_CIRCLEQ_INIT_ENTRY(elm, field) do { \
++ (elm)->field.cqe_next = NULL; \
++ (elm)->field.cqe_prev = NULL; \
++} while (0)
++
++#define DWC_CIRCLEQ_INSERT_AFTER(head, listelm, elm, field) do { \
++ (elm)->field.cqe_next = (listelm)->field.cqe_next; \
++ (elm)->field.cqe_prev = (listelm); \
++ if ((listelm)->field.cqe_next == DWC_CIRCLEQ_END(head)) \
++ (head)->cqh_last = (elm); \
++ else \
++ (listelm)->field.cqe_next->field.cqe_prev = (elm); \
++ (listelm)->field.cqe_next = (elm); \
++} while (0)
++
++#define DWC_CIRCLEQ_INSERT_BEFORE(head, listelm, elm, field) do { \
++ (elm)->field.cqe_next = (listelm); \
++ (elm)->field.cqe_prev = (listelm)->field.cqe_prev; \
++ if ((listelm)->field.cqe_prev == DWC_CIRCLEQ_END(head)) \
++ (head)->cqh_first = (elm); \
++ else \
++ (listelm)->field.cqe_prev->field.cqe_next = (elm); \
++ (listelm)->field.cqe_prev = (elm); \
++} while (0)
++
++#define DWC_CIRCLEQ_INSERT_HEAD(head, elm, field) do { \
++ (elm)->field.cqe_next = (head)->cqh_first; \
++ (elm)->field.cqe_prev = DWC_CIRCLEQ_END(head); \
++ if ((head)->cqh_last == DWC_CIRCLEQ_END(head)) \
++ (head)->cqh_last = (elm); \
++ else \
++ (head)->cqh_first->field.cqe_prev = (elm); \
++ (head)->cqh_first = (elm); \
++} while (0)
++
++#define DWC_CIRCLEQ_INSERT_TAIL(head, elm, field) do { \
++ (elm)->field.cqe_next = DWC_CIRCLEQ_END(head); \
++ (elm)->field.cqe_prev = (head)->cqh_last; \
++ if ((head)->cqh_first == DWC_CIRCLEQ_END(head)) \
++ (head)->cqh_first = (elm); \
++ else \
++ (head)->cqh_last->field.cqe_next = (elm); \
++ (head)->cqh_last = (elm); \
++} while (0)
++
++#define DWC_CIRCLEQ_REMOVE(head, elm, field) do { \
++ if ((elm)->field.cqe_next == DWC_CIRCLEQ_END(head)) \
++ (head)->cqh_last = (elm)->field.cqe_prev; \
++ else \
++ (elm)->field.cqe_next->field.cqe_prev = \
++ (elm)->field.cqe_prev; \
++ if ((elm)->field.cqe_prev == DWC_CIRCLEQ_END(head)) \
++ (head)->cqh_first = (elm)->field.cqe_next; \
++ else \
++ (elm)->field.cqe_prev->field.cqe_next = \
++ (elm)->field.cqe_next; \
++} while (0)
++
++#define DWC_CIRCLEQ_REMOVE_INIT(head, elm, field) do { \
++ DWC_CIRCLEQ_REMOVE(head, elm, field); \
++ DWC_CIRCLEQ_INIT_ENTRY(elm, field); \
++} while (0)
++
++#define DWC_CIRCLEQ_REPLACE(head, elm, elm2, field) do { \
++ if (((elm2)->field.cqe_next = (elm)->field.cqe_next) == \
++ DWC_CIRCLEQ_END(head)) \
++ (head).cqh_last = (elm2); \
++ else \
++ (elm2)->field.cqe_next->field.cqe_prev = (elm2); \
++ if (((elm2)->field.cqe_prev = (elm)->field.cqe_prev) == \
++ DWC_CIRCLEQ_END(head)) \
++ (head).cqh_first = (elm2); \
++ else \
++ (elm2)->field.cqe_prev->field.cqe_next = (elm2); \
++} while (0)
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* _DWC_LIST_H_ */
+diff -Nur linux-4.1.3/drivers/usb/host/dwc_common_port/dwc_mem.c linux-xbian-rpi/drivers/usb/host/dwc_common_port/dwc_mem.c
+--- linux-4.1.3/drivers/usb/host/dwc_common_port/dwc_mem.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/usb/host/dwc_common_port/dwc_mem.c 2015-07-28 01:20:58.441170694 +0200
+@@ -0,0 +1,245 @@
++/* Memory Debugging */
++#ifdef DWC_DEBUG_MEMORY
++
++#include "dwc_os.h"
++#include "dwc_list.h"
++
++struct allocation {
++ void *addr;
++ void *ctx;
++ char *func;
++ int line;
++ uint32_t size;
++ int dma;
++ DWC_CIRCLEQ_ENTRY(allocation) entry;
++};
++
++DWC_CIRCLEQ_HEAD(allocation_queue, allocation);
++
++struct allocation_manager {
++ void *mem_ctx;
++ struct allocation_queue allocations;
++
++ /* statistics */
++ int num;
++ int num_freed;
++ int num_active;
++ uint32_t total;
++ uint32_t cur;
++ uint32_t max;
++};
++
++static struct allocation_manager *manager = NULL;
++
++static int add_allocation(void *ctx, uint32_t size, char const *func, int line, void *addr,
++ int dma)
++{
++ struct allocation *a;
++
++ DWC_ASSERT(manager != NULL, "manager not allocated");
++
++ a = __DWC_ALLOC_ATOMIC(manager->mem_ctx, sizeof(*a));
++ if (!a) {
++ return -DWC_E_NO_MEMORY;
++ }
++
++ a->func = __DWC_ALLOC_ATOMIC(manager->mem_ctx, DWC_STRLEN(func) + 1);
++ if (!a->func) {
++ __DWC_FREE(manager->mem_ctx, a);
++ return -DWC_E_NO_MEMORY;
++ }
++
++ DWC_MEMCPY(a->func, func, DWC_STRLEN(func) + 1);
++ a->addr = addr;
++ a->ctx = ctx;
++ a->line = line;
++ a->size = size;
++ a->dma = dma;
++ DWC_CIRCLEQ_INSERT_TAIL(&manager->allocations, a, entry);
++
++ /* Update stats */
++ manager->num++;
++ manager->num_active++;
++ manager->total += size;
++ manager->cur += size;
++
++ if (manager->max < manager->cur) {
++ manager->max = manager->cur;
++ }
++
++ return 0;
++}
++
++static struct allocation *find_allocation(void *ctx, void *addr)
++{
++ struct allocation *a;
++
++ DWC_CIRCLEQ_FOREACH(a, &manager->allocations, entry) {
++ if (a->ctx == ctx && a->addr == addr) {
++ return a;
++ }
++ }
++
++ return NULL;
++}
++
++static void free_allocation(void *ctx, void *addr, char const *func, int line)
++{
++ struct allocation *a = find_allocation(ctx, addr);
++
++ if (!a) {
++ DWC_ASSERT(0,
++ "Free of address %p that was never allocated or already freed %s:%d",
++ addr, func, line);
++ return;
++ }
++
++ DWC_CIRCLEQ_REMOVE(&manager->allocations, a, entry);
++
++ manager->num_active--;
++ manager->num_freed++;
++ manager->cur -= a->size;
++ __DWC_FREE(manager->mem_ctx, a->func);
++ __DWC_FREE(manager->mem_ctx, a);
++}
++
++int dwc_memory_debug_start(void *mem_ctx)
++{
++ DWC_ASSERT(manager == NULL, "Memory debugging has already started\n");
++
++ if (manager) {
++ return -DWC_E_BUSY;
++ }
++
++ manager = __DWC_ALLOC(mem_ctx, sizeof(*manager));
++ if (!manager) {
++ return -DWC_E_NO_MEMORY;
++ }
++
++ DWC_CIRCLEQ_INIT(&manager->allocations);
++ manager->mem_ctx = mem_ctx;
++ manager->num = 0;
++ manager->num_freed = 0;
++ manager->num_active = 0;
++ manager->total = 0;
++ manager->cur = 0;
++ manager->max = 0;
++
++ return 0;
++}
++
++void dwc_memory_debug_stop(void)
++{
++ struct allocation *a;
++
++ dwc_memory_debug_report();
++
++ DWC_CIRCLEQ_FOREACH(a, &manager->allocations, entry) {
++ DWC_ERROR("Memory leaked from %s:%d\n", a->func, a->line);
++ free_allocation(a->ctx, a->addr, NULL, -1);
++ }
++
++ __DWC_FREE(manager->mem_ctx, manager);
++}
++
++void dwc_memory_debug_report(void)
++{
++ struct allocation *a;
++
++ DWC_PRINTF("\n\n\n----------------- Memory Debugging Report -----------------\n\n");
++ DWC_PRINTF("Num Allocations = %d\n", manager->num);
++ DWC_PRINTF("Freed = %d\n", manager->num_freed);
++ DWC_PRINTF("Active = %d\n", manager->num_active);
++ DWC_PRINTF("Current Memory Used = %d\n", manager->cur);
++ DWC_PRINTF("Total Memory Used = %d\n", manager->total);
++ DWC_PRINTF("Maximum Memory Used at Once = %d\n", manager->max);
++ DWC_PRINTF("Unfreed allocations:\n");
++
++ DWC_CIRCLEQ_FOREACH(a, &manager->allocations, entry) {
++ DWC_PRINTF(" addr=%p, size=%d from %s:%d, DMA=%d\n",
++ a->addr, a->size, a->func, a->line, a->dma);
++ }
++}
++
++/* The replacement functions */
++void *dwc_alloc_debug(void *mem_ctx, uint32_t size, char const *func, int line)
++{
++ void *addr = __DWC_ALLOC(mem_ctx, size);
++
++ if (!addr) {
++ return NULL;
++ }
++
++ if (add_allocation(mem_ctx, size, func, line, addr, 0)) {
++ __DWC_FREE(mem_ctx, addr);
++ return NULL;
++ }
++
++ return addr;
++}
++
++void *dwc_alloc_atomic_debug(void *mem_ctx, uint32_t size, char const *func,
++ int line)
++{
++ void *addr = __DWC_ALLOC_ATOMIC(mem_ctx, size);
++
++ if (!addr) {
++ return NULL;
++ }
++
++ if (add_allocation(mem_ctx, size, func, line, addr, 0)) {
++ __DWC_FREE(mem_ctx, addr);
++ return NULL;
++ }
++
++ return addr;
++}
++
++void dwc_free_debug(void *mem_ctx, void *addr, char const *func, int line)
++{
++ free_allocation(mem_ctx, addr, func, line);
++ __DWC_FREE(mem_ctx, addr);
++}
++
++void *dwc_dma_alloc_debug(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr,
++ char const *func, int line)
++{
++ void *addr = __DWC_DMA_ALLOC(dma_ctx, size, dma_addr);
++
++ if (!addr) {
++ return NULL;
++ }
++
++ if (add_allocation(dma_ctx, size, func, line, addr, 1)) {
++ __DWC_DMA_FREE(dma_ctx, size, addr, *dma_addr);
++ return NULL;
++ }
++
++ return addr;
++}
++
++void *dwc_dma_alloc_atomic_debug(void *dma_ctx, uint32_t size,
++ dwc_dma_t *dma_addr, char const *func, int line)
++{
++ void *addr = __DWC_DMA_ALLOC_ATOMIC(dma_ctx, size, dma_addr);
++
++ if (!addr) {
++ return NULL;
++ }
++
++ if (add_allocation(dma_ctx, size, func, line, addr, 1)) {
++ __DWC_DMA_FREE(dma_ctx, size, addr, *dma_addr);
++ return NULL;
++ }
++
++ return addr;
++}
++
++void dwc_dma_free_debug(void *dma_ctx, uint32_t size, void *virt_addr,
++ dwc_dma_t dma_addr, char const *func, int line)
++{
++ free_allocation(dma_ctx, virt_addr, func, line);
++ __DWC_DMA_FREE(dma_ctx, size, virt_addr, dma_addr);
++}
++
++#endif /* DWC_DEBUG_MEMORY */
+diff -Nur linux-4.1.3/drivers/usb/host/dwc_common_port/dwc_modpow.c linux-xbian-rpi/drivers/usb/host/dwc_common_port/dwc_modpow.c
+--- linux-4.1.3/drivers/usb/host/dwc_common_port/dwc_modpow.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/usb/host/dwc_common_port/dwc_modpow.c 2015-07-28 01:20:58.441170694 +0200
+@@ -0,0 +1,636 @@
++/* Bignum routines adapted from PUTTY sources. PuTTY copyright notice follows.
++ *
++ * PuTTY is copyright 1997-2007 Simon Tatham.
++ *
++ * Portions copyright Robert de Bath, Joris van Rantwijk, Delian
++ * Delchev, Andreas Schultz, Jeroen Massar, Wez Furlong, Nicolas Barry,
++ * Justin Bradford, Ben Harris, Malcolm Smith, Ahmad Khalifa, Markus
++ * Kuhn, and CORE SDI S.A.
++ *
++ * Permission is hereby granted, free of charge, to any person
++ * obtaining a copy of this software and associated documentation files
++ * (the "Software"), to deal in the Software without restriction,
++ * including without limitation the rights to use, copy, modify, merge,
++ * publish, distribute, sublicense, and/or sell copies of the Software,
++ * and to permit persons to whom the Software is furnished to do so,
++ * subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be
++ * included in all copies or substantial portions of the Software.
++
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ * NONINFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE
++ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
++ * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
++ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++#ifdef DWC_CRYPTOLIB
++
++#ifndef CONFIG_MACH_IPMATE
++
++#include "dwc_modpow.h"
++
++#define BIGNUM_INT_MASK 0xFFFFFFFFUL
++#define BIGNUM_TOP_BIT 0x80000000UL
++#define BIGNUM_INT_BITS 32
++
++
++static void *snmalloc(void *mem_ctx, size_t n, size_t size)
++{
++ void *p;
++ size *= n;
++ if (size == 0) size = 1;
++ p = dwc_alloc(mem_ctx, size);
++ return p;
++}
++
++#define snewn(ctx, n, type) ((type *)snmalloc((ctx), (n), sizeof(type)))
++#define sfree dwc_free
++
++/*
++ * Usage notes:
++ * * Do not call the DIVMOD_WORD macro with expressions such as array
++ * subscripts, as some implementations object to this (see below).
++ * * Note that none of the division methods below will cope if the
++ * quotient won't fit into BIGNUM_INT_BITS. Callers should be careful
++ * to avoid this case.
++ * If this condition occurs, in the case of the x86 DIV instruction,
++ * an overflow exception will occur, which (according to a correspondent)
++ * will manifest on Windows as something like
++ * 0xC0000095: Integer overflow
++ * The C variant won't give the right answer, either.
++ */
++
++#define MUL_WORD(w1, w2) ((BignumDblInt)w1 * w2)
++
++#if defined __GNUC__ && defined __i386__
++#define DIVMOD_WORD(q, r, hi, lo, w) \
++ __asm__("div %2" : \
++ "=d" (r), "=a" (q) : \
++ "r" (w), "d" (hi), "a" (lo))
++#else
++#define DIVMOD_WORD(q, r, hi, lo, w) do { \
++ BignumDblInt n = (((BignumDblInt)hi) << BIGNUM_INT_BITS) | lo; \
++ q = n / w; \
++ r = n % w; \
++} while (0)
++#endif
++
++// q = n / w;
++// r = n % w;
++
++#define BIGNUM_INT_BYTES (BIGNUM_INT_BITS / 8)
++
++#define BIGNUM_INTERNAL
++
++static Bignum newbn(void *mem_ctx, int length)
++{
++ Bignum b = snewn(mem_ctx, length + 1, BignumInt);
++ //if (!b)
++ //abort(); /* FIXME */
++ DWC_MEMSET(b, 0, (length + 1) * sizeof(*b));
++ b[0] = length;
++ return b;
++}
++
++void freebn(void *mem_ctx, Bignum b)
++{
++ /*
++ * Burn the evidence, just in case.
++ */
++ DWC_MEMSET(b, 0, sizeof(b[0]) * (b[0] + 1));
++ sfree(mem_ctx, b);
++}
++
++/*
++ * Compute c = a * b.
++ * Input is in the first len words of a and b.
++ * Result is returned in the first 2*len words of c.
++ */
++static void internal_mul(BignumInt *a, BignumInt *b,
++ BignumInt *c, int len)
++{
++ int i, j;
++ BignumDblInt t;
++
++ for (j = 0; j < 2 * len; j++)
++ c[j] = 0;
++
++ for (i = len - 1; i >= 0; i--) {
++ t = 0;
++ for (j = len - 1; j >= 0; j--) {
++ t += MUL_WORD(a[i], (BignumDblInt) b[j]);
++ t += (BignumDblInt) c[i + j + 1];
++ c[i + j + 1] = (BignumInt) t;
++ t = t >> BIGNUM_INT_BITS;
++ }
++ c[i] = (BignumInt) t;
++ }
++}
++
++static void internal_add_shifted(BignumInt *number,
++ unsigned n, int shift)
++{
++ int word = 1 + (shift / BIGNUM_INT_BITS);
++ int bshift = shift % BIGNUM_INT_BITS;
++ BignumDblInt addend;
++
++ addend = (BignumDblInt)n << bshift;
++
++ while (addend) {
++ addend += number[word];
++ number[word] = (BignumInt) addend & BIGNUM_INT_MASK;
++ addend >>= BIGNUM_INT_BITS;
++ word++;
++ }
++}
++
++/*
++ * Compute a = a % m.
++ * Input in first alen words of a and first mlen words of m.
++ * Output in first alen words of a
++ * (of which first alen-mlen words will be zero).
++ * The MSW of m MUST have its high bit set.
++ * Quotient is accumulated in the `quotient' array, which is a Bignum
++ * rather than the internal bigendian format. Quotient parts are shifted
++ * left by `qshift' before adding into quot.
++ */
++static void internal_mod(BignumInt *a, int alen,
++ BignumInt *m, int mlen,
++ BignumInt *quot, int qshift)
++{
++ BignumInt m0, m1;
++ unsigned int h;
++ int i, k;
++
++ m0 = m[0];
++ if (mlen > 1)
++ m1 = m[1];
++ else
++ m1 = 0;
++
++ for (i = 0; i <= alen - mlen; i++) {
++ BignumDblInt t;
++ unsigned int q, r, c, ai1;
++
++ if (i == 0) {
++ h = 0;
++ } else {
++ h = a[i - 1];
++ a[i - 1] = 0;
++ }
++
++ if (i == alen - 1)
++ ai1 = 0;
++ else
++ ai1 = a[i + 1];
++
++ /* Find q = h:a[i] / m0 */
++ if (h >= m0) {
++ /*
++ * Special case.
++ *
++ * To illustrate it, suppose a BignumInt is 8 bits, and
++ * we are dividing (say) A1:23:45:67 by A1:B2:C3. Then
++ * our initial division will be 0xA123 / 0xA1, which
++ * will give a quotient of 0x100 and a divide overflow.
++ * However, the invariants in this division algorithm
++ * are not violated, since the full number A1:23:... is
++ * _less_ than the quotient prefix A1:B2:... and so the
++ * following correction loop would have sorted it out.
++ *
++ * In this situation we set q to be the largest
++ * quotient we _can_ stomach (0xFF, of course).
++ */
++ q = BIGNUM_INT_MASK;
++ } else {
++ /* Macro doesn't want an array subscript expression passed
++ * into it (see definition), so use a temporary. */
++ BignumInt tmplo = a[i];
++ DIVMOD_WORD(q, r, h, tmplo, m0);
++
++ /* Refine our estimate of q by looking at
++ h:a[i]:a[i+1] / m0:m1 */
++ t = MUL_WORD(m1, q);
++ if (t > ((BignumDblInt) r << BIGNUM_INT_BITS) + ai1) {
++ q--;
++ t -= m1;
++ r = (r + m0) & BIGNUM_INT_MASK; /* overflow? */
++ if (r >= (BignumDblInt) m0 &&
++ t > ((BignumDblInt) r << BIGNUM_INT_BITS) + ai1) q--;
++ }
++ }
++
++ /* Subtract q * m from a[i...] */
++ c = 0;
++ for (k = mlen - 1; k >= 0; k--) {
++ t = MUL_WORD(q, m[k]);
++ t += c;
++ c = (unsigned)(t >> BIGNUM_INT_BITS);
++ if ((BignumInt) t > a[i + k])
++ c++;
++ a[i + k] -= (BignumInt) t;
++ }
++
++ /* Add back m in case of borrow */
++ if (c != h) {
++ t = 0;
++ for (k = mlen - 1; k >= 0; k--) {
++ t += m[k];
++ t += a[i + k];
++ a[i + k] = (BignumInt) t;
++ t = t >> BIGNUM_INT_BITS;
++ }
++ q--;
++ }
++ if (quot)
++ internal_add_shifted(quot, q, qshift + BIGNUM_INT_BITS * (alen - mlen - i));
++ }
++}
++
++/*
++ * Compute p % mod.
++ * The most significant word of mod MUST be non-zero.
++ * We assume that the result array is the same size as the mod array.
++ * We optionally write out a quotient if `quotient' is non-NULL.
++ * We can avoid writing out the result if `result' is NULL.
++ */
++void bigdivmod(void *mem_ctx, Bignum p, Bignum mod, Bignum result, Bignum quotient)
++{
++ BignumInt *n, *m;
++ int mshift;
++ int plen, mlen, i, j;
++
++ /* Allocate m of size mlen, copy mod to m */
++ /* We use big endian internally */
++ mlen = mod[0];
++ m = snewn(mem_ctx, mlen, BignumInt);
++ //if (!m)
++ //abort(); /* FIXME */
++ for (j = 0; j < mlen; j++)
++ m[j] = mod[mod[0] - j];
++
++ /* Shift m left to make msb bit set */
++ for (mshift = 0; mshift < BIGNUM_INT_BITS-1; mshift++)
++ if ((m[0] << mshift) & BIGNUM_TOP_BIT)
++ break;
++ if (mshift) {
++ for (i = 0; i < mlen - 1; i++)
++ m[i] = (m[i] << mshift) | (m[i + 1] >> (BIGNUM_INT_BITS - mshift));
++ m[mlen - 1] = m[mlen - 1] << mshift;
++ }
++
++ plen = p[0];
++ /* Ensure plen > mlen */
++ if (plen <= mlen)
++ plen = mlen + 1;
++
++ /* Allocate n of size plen, copy p to n */
++ n = snewn(mem_ctx, plen, BignumInt);
++ //if (!n)
++ //abort(); /* FIXME */
++ for (j = 0; j < plen; j++)
++ n[j] = 0;
++ for (j = 1; j <= (int)p[0]; j++)
++ n[plen - j] = p[j];
++
++ /* Main computation */
++ internal_mod(n, plen, m, mlen, quotient, mshift);
++
++ /* Fixup result in case the modulus was shifted */
++ if (mshift) {
++ for (i = plen - mlen - 1; i < plen - 1; i++)
++ n[i] = (n[i] << mshift) | (n[i + 1] >> (BIGNUM_INT_BITS - mshift));
++ n[plen - 1] = n[plen - 1] << mshift;
++ internal_mod(n, plen, m, mlen, quotient, 0);
++ for (i = plen - 1; i >= plen - mlen; i--)
++ n[i] = (n[i] >> mshift) | (n[i - 1] << (BIGNUM_INT_BITS - mshift));
++ }
++
++ /* Copy result to buffer */
++ if (result) {
++ for (i = 1; i <= (int)result[0]; i++) {
++ int j = plen - i;
++ result[i] = j >= 0 ? n[j] : 0;
++ }
++ }
++
++ /* Free temporary arrays */
++ for (i = 0; i < mlen; i++)
++ m[i] = 0;
++ sfree(mem_ctx, m);
++ for (i = 0; i < plen; i++)
++ n[i] = 0;
++ sfree(mem_ctx, n);
++}
++
++/*
++ * Simple remainder.
++ */
++Bignum bigmod(void *mem_ctx, Bignum a, Bignum b)
++{
++ Bignum r = newbn(mem_ctx, b[0]);
++ bigdivmod(mem_ctx, a, b, r, NULL);
++ return r;
++}
++
++/*
++ * Compute (base ^ exp) % mod.
++ */
++Bignum dwc_modpow(void *mem_ctx, Bignum base_in, Bignum exp, Bignum mod)
++{
++ BignumInt *a, *b, *n, *m;
++ int mshift;
++ int mlen, i, j;
++ Bignum base, result;
++
++ /*
++ * The most significant word of mod needs to be non-zero. It
++ * should already be, but let's make sure.
++ */
++ //assert(mod[mod[0]] != 0);
++
++ /*
++ * Make sure the base is smaller than the modulus, by reducing
++ * it modulo the modulus if not.
++ */
++ base = bigmod(mem_ctx, base_in, mod);
++
++ /* Allocate m of size mlen, copy mod to m */
++ /* We use big endian internally */
++ mlen = mod[0];
++ m = snewn(mem_ctx, mlen, BignumInt);
++ //if (!m)
++ //abort(); /* FIXME */
++ for (j = 0; j < mlen; j++)
++ m[j] = mod[mod[0] - j];
++
++ /* Shift m left to make msb bit set */
++ for (mshift = 0; mshift < BIGNUM_INT_BITS - 1; mshift++)
++ if ((m[0] << mshift) & BIGNUM_TOP_BIT)
++ break;
++ if (mshift) {
++ for (i = 0; i < mlen - 1; i++)
++ m[i] =
++ (m[i] << mshift) | (m[i + 1] >>
++ (BIGNUM_INT_BITS - mshift));
++ m[mlen - 1] = m[mlen - 1] << mshift;
++ }
++
++ /* Allocate n of size mlen, copy base to n */
++ n = snewn(mem_ctx, mlen, BignumInt);
++ //if (!n)
++ //abort(); /* FIXME */
++ i = mlen - base[0];
++ for (j = 0; j < i; j++)
++ n[j] = 0;
++ for (j = 0; j < base[0]; j++)
++ n[i + j] = base[base[0] - j];
++
++ /* Allocate a and b of size 2*mlen. Set a = 1 */
++ a = snewn(mem_ctx, 2 * mlen, BignumInt);
++ //if (!a)
++ //abort(); /* FIXME */
++ b = snewn(mem_ctx, 2 * mlen, BignumInt);
++ //if (!b)
++ //abort(); /* FIXME */
++ for (i = 0; i < 2 * mlen; i++)
++ a[i] = 0;
++ a[2 * mlen - 1] = 1;
++
++ /* Skip leading zero bits of exp. */
++ i = 0;
++ j = BIGNUM_INT_BITS - 1;
++ while (i < exp[0] && (exp[exp[0] - i] & (1 << j)) == 0) {
++ j--;
++ if (j < 0) {
++ i++;
++ j = BIGNUM_INT_BITS - 1;
++ }
++ }
++
++ /* Main computation */
++ while (i < exp[0]) {
++ while (j >= 0) {
++ internal_mul(a + mlen, a + mlen, b, mlen);
++ internal_mod(b, mlen * 2, m, mlen, NULL, 0);
++ if ((exp[exp[0] - i] & (1 << j)) != 0) {
++ internal_mul(b + mlen, n, a, mlen);
++ internal_mod(a, mlen * 2, m, mlen, NULL, 0);
++ } else {
++ BignumInt *t;
++ t = a;
++ a = b;
++ b = t;
++ }
++ j--;
++ }
++ i++;
++ j = BIGNUM_INT_BITS - 1;
++ }
++
++ /* Fixup result in case the modulus was shifted */
++ if (mshift) {
++ for (i = mlen - 1; i < 2 * mlen - 1; i++)
++ a[i] =
++ (a[i] << mshift) | (a[i + 1] >>
++ (BIGNUM_INT_BITS - mshift));
++ a[2 * mlen - 1] = a[2 * mlen - 1] << mshift;
++ internal_mod(a, mlen * 2, m, mlen, NULL, 0);
++ for (i = 2 * mlen - 1; i >= mlen; i--)
++ a[i] =
++ (a[i] >> mshift) | (a[i - 1] <<
++ (BIGNUM_INT_BITS - mshift));
++ }
++
++ /* Copy result to buffer */
++ result = newbn(mem_ctx, mod[0]);
++ for (i = 0; i < mlen; i++)
++ result[result[0] - i] = a[i + mlen];
++ while (result[0] > 1 && result[result[0]] == 0)
++ result[0]--;
++
++ /* Free temporary arrays */
++ for (i = 0; i < 2 * mlen; i++)
++ a[i] = 0;
++ sfree(mem_ctx, a);
++ for (i = 0; i < 2 * mlen; i++)
++ b[i] = 0;
++ sfree(mem_ctx, b);
++ for (i = 0; i < mlen; i++)
++ m[i] = 0;
++ sfree(mem_ctx, m);
++ for (i = 0; i < mlen; i++)
++ n[i] = 0;
++ sfree(mem_ctx, n);
++
++ freebn(mem_ctx, base);
++
++ return result;
++}
++
++
++#ifdef UNITTEST
++
++static __u32 dh_p[] = {
++ 96,
++ 0xFFFFFFFF,
++ 0xFFFFFFFF,
++ 0xA93AD2CA,
++ 0x4B82D120,
++ 0xE0FD108E,
++ 0x43DB5BFC,
++ 0x74E5AB31,
++ 0x08E24FA0,
++ 0xBAD946E2,
++ 0x770988C0,
++ 0x7A615D6C,
++ 0xBBE11757,
++ 0x177B200C,
++ 0x521F2B18,
++ 0x3EC86A64,
++ 0xD8760273,
++ 0xD98A0864,
++ 0xF12FFA06,
++ 0x1AD2EE6B,
++ 0xCEE3D226,
++ 0x4A25619D,
++ 0x1E8C94E0,
++ 0xDB0933D7,
++ 0xABF5AE8C,
++ 0xA6E1E4C7,
++ 0xB3970F85,
++ 0x5D060C7D,
++ 0x8AEA7157,
++ 0x58DBEF0A,
++ 0xECFB8504,
++ 0xDF1CBA64,
++ 0xA85521AB,
++ 0x04507A33,
++ 0xAD33170D,
++ 0x8AAAC42D,
++ 0x15728E5A,
++ 0x98FA0510,
++ 0x15D22618,
++ 0xEA956AE5,
++ 0x3995497C,
++ 0x95581718,
++ 0xDE2BCBF6,
++ 0x6F4C52C9,
++ 0xB5C55DF0,
++ 0xEC07A28F,
++ 0x9B2783A2,
++ 0x180E8603,
++ 0xE39E772C,
++ 0x2E36CE3B,
++ 0x32905E46,
++ 0xCA18217C,
++ 0xF1746C08,
++ 0x4ABC9804,
++ 0x670C354E,
++ 0x7096966D,
++ 0x9ED52907,
++ 0x208552BB,
++ 0x1C62F356,
++ 0xDCA3AD96,
++ 0x83655D23,
++ 0xFD24CF5F,
++ 0x69163FA8,
++ 0x1C55D39A,
++ 0x98DA4836,
++ 0xA163BF05,
++ 0xC2007CB8,
++ 0xECE45B3D,
++ 0x49286651,
++ 0x7C4B1FE6,
++ 0xAE9F2411,
++ 0x5A899FA5,
++ 0xEE386BFB,
++ 0xF406B7ED,
++ 0x0BFF5CB6,
++ 0xA637ED6B,
++ 0xF44C42E9,
++ 0x625E7EC6,
++ 0xE485B576,
++ 0x6D51C245,
++ 0x4FE1356D,
++ 0xF25F1437,
++ 0x302B0A6D,
++ 0xCD3A431B,
++ 0xEF9519B3,
++ 0x8E3404DD,
++ 0x514A0879,
++ 0x3B139B22,
++ 0x020BBEA6,
++ 0x8A67CC74,
++ 0x29024E08,
++ 0x80DC1CD1,
++ 0xC4C6628B,
++ 0x2168C234,
++ 0xC90FDAA2,
++ 0xFFFFFFFF,
++ 0xFFFFFFFF,
++};
++
++static __u32 dh_a[] = {
++ 8,
++ 0xdf367516,
++ 0x86459caa,
++ 0xe2d459a4,
++ 0xd910dae0,
++ 0x8a8b5e37,
++ 0x67ab31c6,
++ 0xf0b55ea9,
++ 0x440051d6,
++};
++
++static __u32 dh_b[] = {
++ 8,
++ 0xded92656,
++ 0xe07a048a,
++ 0x6fa452cd,
++ 0x2df89d30,
++ 0xc75f1b0f,
++ 0x8ce3578f,
++ 0x7980a324,
++ 0x5daec786,
++};
++
++static __u32 dh_g[] = {
++ 1,
++ 2,
++};
++
++int main(void)
++{
++ int i;
++ __u32 *k;
++ k = dwc_modpow(NULL, dh_g, dh_a, dh_p);
++
++ printf("\n\n");
++ for (i=0; i<k[0]; i++) {
++ __u32 word32 = k[k[0] - i];
++ __u16 l = word32 & 0xffff;
++ __u16 m = (word32 & 0xffff0000) >> 16;
++ printf("%04x %04x ", m, l);
++ if (!((i + 1)%13)) printf("\n");
++ }
++ printf("\n\n");
++
++ if ((k[0] == 0x60) && (k[1] == 0x28e490e5) && (k[0x60] == 0x5a0d3d4e)) {
++ printf("PASS\n\n");
++ }
++ else {
++ printf("FAIL\n\n");
++ }
++
++}
++
++#endif /* UNITTEST */
++
++#endif /* CONFIG_MACH_IPMATE */
++
++#endif /*DWC_CRYPTOLIB */
+diff -Nur linux-4.1.3/drivers/usb/host/dwc_common_port/dwc_modpow.h linux-xbian-rpi/drivers/usb/host/dwc_common_port/dwc_modpow.h
+--- linux-4.1.3/drivers/usb/host/dwc_common_port/dwc_modpow.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/usb/host/dwc_common_port/dwc_modpow.h 2015-07-28 01:20:58.441170694 +0200
+@@ -0,0 +1,34 @@
++/*
++ * dwc_modpow.h
++ * See dwc_modpow.c for license and changes
++ */
++#ifndef _DWC_MODPOW_H
++#define _DWC_MODPOW_H
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++#include "dwc_os.h"
++
++/** @file
++ *
++ * This file defines the module exponentiation function which is only used
++ * internally by the DWC UWB modules for calculation of PKs during numeric
++ * association. The routine is taken from the PUTTY, an open source terminal
++ * emulator. The PUTTY License is preserved in the dwc_modpow.c file.
++ *
++ */
++
++typedef uint32_t BignumInt;
++typedef uint64_t BignumDblInt;
++typedef BignumInt *Bignum;
++
++/* Compute modular exponentiaion */
++extern Bignum dwc_modpow(void *mem_ctx, Bignum base_in, Bignum exp, Bignum mod);
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* _LINUX_BIGNUM_H */
+diff -Nur linux-4.1.3/drivers/usb/host/dwc_common_port/dwc_notifier.c linux-xbian-rpi/drivers/usb/host/dwc_common_port/dwc_notifier.c
+--- linux-4.1.3/drivers/usb/host/dwc_common_port/dwc_notifier.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/usb/host/dwc_common_port/dwc_notifier.c 2015-07-28 01:20:58.441170694 +0200
+@@ -0,0 +1,319 @@
++#ifdef DWC_NOTIFYLIB
++
++#include "dwc_notifier.h"
++#include "dwc_list.h"
++
++typedef struct dwc_observer {
++ void *observer;
++ dwc_notifier_callback_t callback;
++ void *data;
++ char *notification;
++ DWC_CIRCLEQ_ENTRY(dwc_observer) list_entry;
++} observer_t;
++
++DWC_CIRCLEQ_HEAD(observer_queue, dwc_observer);
++
++typedef struct dwc_notifier {
++ void *mem_ctx;
++ void *object;
++ struct observer_queue observers;
++ DWC_CIRCLEQ_ENTRY(dwc_notifier) list_entry;
++} notifier_t;
++
++DWC_CIRCLEQ_HEAD(notifier_queue, dwc_notifier);
++
++typedef struct manager {
++ void *mem_ctx;
++ void *wkq_ctx;
++ dwc_workq_t *wq;
++// dwc_mutex_t *mutex;
++ struct notifier_queue notifiers;
++} manager_t;
++
++static manager_t *manager = NULL;
++
++static int create_manager(void *mem_ctx, void *wkq_ctx)
++{
++ manager = dwc_alloc(mem_ctx, sizeof(manager_t));
++ if (!manager) {
++ return -DWC_E_NO_MEMORY;
++ }
++
++ DWC_CIRCLEQ_INIT(&manager->notifiers);
++
++ manager->wq = dwc_workq_alloc(wkq_ctx, "DWC Notification WorkQ");
++ if (!manager->wq) {
++ return -DWC_E_NO_MEMORY;
++ }
++
++ return 0;
++}
++
++static void free_manager(void)
++{
++ dwc_workq_free(manager->wq);
++
++ /* All notifiers must have unregistered themselves before this module
++ * can be removed. Hitting this assertion indicates a programmer
++ * error. */
++ DWC_ASSERT(DWC_CIRCLEQ_EMPTY(&manager->notifiers),
++ "Notification manager being freed before all notifiers have been removed");
++ dwc_free(manager->mem_ctx, manager);
++}
++
++#ifdef DEBUG
++static void dump_manager(void)
++{
++ notifier_t *n;
++ observer_t *o;
++
++ DWC_ASSERT(manager, "Notification manager not found");
++
++ DWC_DEBUG("List of all notifiers and observers:\n");
++ DWC_CIRCLEQ_FOREACH(n, &manager->notifiers, list_entry) {
++ DWC_DEBUG("Notifier %p has observers:\n", n->object);
++ DWC_CIRCLEQ_FOREACH(o, &n->observers, list_entry) {
++ DWC_DEBUG(" %p watching %s\n", o->observer, o->notification);
++ }
++ }
++}
++#else
++#define dump_manager(...)
++#endif
++
++static observer_t *alloc_observer(void *mem_ctx, void *observer, char *notification,
++ dwc_notifier_callback_t callback, void *data)
++{
++ observer_t *new_observer = dwc_alloc(mem_ctx, sizeof(observer_t));
++
++ if (!new_observer) {
++ return NULL;
++ }
++
++ DWC_CIRCLEQ_INIT_ENTRY(new_observer, list_entry);
++ new_observer->observer = observer;
++ new_observer->notification = notification;
++ new_observer->callback = callback;
++ new_observer->data = data;
++ return new_observer;
++}
++
++static void free_observer(void *mem_ctx, observer_t *observer)
++{
++ dwc_free(mem_ctx, observer);
++}
++
++static notifier_t *alloc_notifier(void *mem_ctx, void *object)
++{
++ notifier_t *notifier;
++
++ if (!object) {
++ return NULL;
++ }
++
++ notifier = dwc_alloc(mem_ctx, sizeof(notifier_t));
++ if (!notifier) {
++ return NULL;
++ }
++
++ DWC_CIRCLEQ_INIT(&notifier->observers);
++ DWC_CIRCLEQ_INIT_ENTRY(notifier, list_entry);
++
++ notifier->mem_ctx = mem_ctx;
++ notifier->object = object;
++ return notifier;
++}
++
++static void free_notifier(notifier_t *notifier)
++{
++ observer_t *observer;
++
++ DWC_CIRCLEQ_FOREACH(observer, &notifier->observers, list_entry) {
++ free_observer(notifier->mem_ctx, observer);
++ }
++
++ dwc_free(notifier->mem_ctx, notifier);
++}
++
++static notifier_t *find_notifier(void *object)
++{
++ notifier_t *notifier;
++
++ DWC_ASSERT(manager, "Notification manager not found");
++
++ if (!object) {
++ return NULL;
++ }
++
++ DWC_CIRCLEQ_FOREACH(notifier, &manager->notifiers, list_entry) {
++ if (notifier->object == object) {
++ return notifier;
++ }
++ }
++
++ return NULL;
++}
++
++int dwc_alloc_notification_manager(void *mem_ctx, void *wkq_ctx)
++{
++ return create_manager(mem_ctx, wkq_ctx);
++}
++
++void dwc_free_notification_manager(void)
++{
++ free_manager();
++}
++
++dwc_notifier_t *dwc_register_notifier(void *mem_ctx, void *object)
++{
++ notifier_t *notifier;
++
++ DWC_ASSERT(manager, "Notification manager not found");
++
++ notifier = find_notifier(object);
++ if (notifier) {
++ DWC_ERROR("Notifier %p is already registered\n", object);
++ return NULL;
++ }
++
++ notifier = alloc_notifier(mem_ctx, object);
++ if (!notifier) {
++ return NULL;
++ }
++
++ DWC_CIRCLEQ_INSERT_TAIL(&manager->notifiers, notifier, list_entry);
++
++ DWC_INFO("Notifier %p registered", object);
++ dump_manager();
++
++ return notifier;
++}
++
++void dwc_unregister_notifier(dwc_notifier_t *notifier)
++{
++ DWC_ASSERT(manager, "Notification manager not found");
++
++ if (!DWC_CIRCLEQ_EMPTY(&notifier->observers)) {
++ observer_t *o;
++
++ DWC_ERROR("Notifier %p has active observers when removing\n", notifier->object);
++ DWC_CIRCLEQ_FOREACH(o, &notifier->observers, list_entry) {
++ DWC_DEBUGC(" %p watching %s\n", o->observer, o->notification);
++ }
++
++ DWC_ASSERT(DWC_CIRCLEQ_EMPTY(&notifier->observers),
++ "Notifier %p has active observers when removing", notifier);
++ }
++
++ DWC_CIRCLEQ_REMOVE_INIT(&manager->notifiers, notifier, list_entry);
++ free_notifier(notifier);
++
++ DWC_INFO("Notifier unregistered");
++ dump_manager();
++}
++
++/* Add an observer to observe the notifier for a particular state, event, or notification. */
++int dwc_add_observer(void *observer, void *object, char *notification,
++ dwc_notifier_callback_t callback, void *data)
++{
++ notifier_t *notifier = find_notifier(object);
++ observer_t *new_observer;
++
++ if (!notifier) {
++ DWC_ERROR("Notifier %p is not found when adding observer\n", object);
++ return -DWC_E_INVALID;
++ }
++
++ new_observer = alloc_observer(notifier->mem_ctx, observer, notification, callback, data);
++ if (!new_observer) {
++ return -DWC_E_NO_MEMORY;
++ }
++
++ DWC_CIRCLEQ_INSERT_TAIL(&notifier->observers, new_observer, list_entry);
++
++ DWC_INFO("Added observer %p to notifier %p observing notification %s, callback=%p, data=%p",
++ observer, object, notification, callback, data);
++
++ dump_manager();
++ return 0;
++}
++
++int dwc_remove_observer(void *observer)
++{
++ notifier_t *n;
++
++ DWC_ASSERT(manager, "Notification manager not found");
++
++ DWC_CIRCLEQ_FOREACH(n, &manager->notifiers, list_entry) {
++ observer_t *o;
++ observer_t *o2;
++
++ DWC_CIRCLEQ_FOREACH_SAFE(o, o2, &n->observers, list_entry) {
++ if (o->observer == observer) {
++ DWC_CIRCLEQ_REMOVE_INIT(&n->observers, o, list_entry);
++ DWC_INFO("Removing observer %p from notifier %p watching notification %s:",
++ o->observer, n->object, o->notification);
++ free_observer(n->mem_ctx, o);
++ }
++ }
++ }
++
++ dump_manager();
++ return 0;
++}
++
++typedef struct callback_data {
++ void *mem_ctx;
++ dwc_notifier_callback_t cb;
++ void *observer;
++ void *data;
++ void *object;
++ char *notification;
++ void *notification_data;
++} cb_data_t;
++
++static void cb_task(void *data)
++{
++ cb_data_t *cb = (cb_data_t *)data;
++
++ cb->cb(cb->object, cb->notification, cb->observer, cb->notification_data, cb->data);
++ dwc_free(cb->mem_ctx, cb);
++}
++
++void dwc_notify(dwc_notifier_t *notifier, char *notification, void *notification_data)
++{
++ observer_t *o;
++
++ DWC_ASSERT(manager, "Notification manager not found");
++
++ DWC_CIRCLEQ_FOREACH(o, &notifier->observers, list_entry) {
++ int len = DWC_STRLEN(notification);
++
++ if (DWC_STRLEN(o->notification) != len) {
++ continue;
++ }
++
++ if (DWC_STRNCMP(o->notification, notification, len) == 0) {
++ cb_data_t *cb_data = dwc_alloc(notifier->mem_ctx, sizeof(cb_data_t));
++
++ if (!cb_data) {
++ DWC_ERROR("Failed to allocate callback data\n");
++ return;
++ }
++
++ cb_data->mem_ctx = notifier->mem_ctx;
++ cb_data->cb = o->callback;
++ cb_data->observer = o->observer;
++ cb_data->data = o->data;
++ cb_data->object = notifier->object;
++ cb_data->notification = notification;
++ cb_data->notification_data = notification_data;
++ DWC_DEBUGC("Observer found %p for notification %s\n", o->observer, notification);
++ DWC_WORKQ_SCHEDULE(manager->wq, cb_task, cb_data,
++ "Notify callback from %p for Notification %s, to observer %p",
++ cb_data->object, notification, cb_data->observer);
++ }
++ }
++}
++
++#endif /* DWC_NOTIFYLIB */
+diff -Nur linux-4.1.3/drivers/usb/host/dwc_common_port/dwc_notifier.h linux-xbian-rpi/drivers/usb/host/dwc_common_port/dwc_notifier.h
+--- linux-4.1.3/drivers/usb/host/dwc_common_port/dwc_notifier.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/usb/host/dwc_common_port/dwc_notifier.h 2015-07-28 01:20:58.441170694 +0200
+@@ -0,0 +1,122 @@
++
++#ifndef __DWC_NOTIFIER_H__
++#define __DWC_NOTIFIER_H__
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++#include "dwc_os.h"
++
++/** @file
++ *
++ * A simple implementation of the Observer pattern. Any "module" can
++ * register as an observer or notifier. The notion of "module" is abstract and
++ * can mean anything used to identify either an observer or notifier. Usually
++ * it will be a pointer to a data structure which contains some state, ie an
++ * object.
++ *
++ * Before any notifiers can be added, the global notification manager must be
++ * brought up with dwc_alloc_notification_manager().
++ * dwc_free_notification_manager() will bring it down and free all resources.
++ * These would typically be called upon module load and unload. The
++ * notification manager is a single global instance that handles all registered
++ * observable modules and observers so this should be done only once.
++ *
++ * A module can be observable by using Notifications to publicize some general
++ * information about it's state or operation. It does not care who listens, or
++ * even if anyone listens, or what they do with the information. The observable
++ * modules do not need to know any information about it's observers or their
++ * interface, or their state or data.
++ *
++ * Any module can register to emit Notifications. It should publish a list of
++ * notifications that it can emit and their behavior, such as when they will get
++ * triggered, and what information will be provided to the observer. Then it
++ * should register itself as an observable module. See dwc_register_notifier().
++ *
++ * Any module can observe any observable, registered module, provided it has a
++ * handle to the other module and knows what notifications to observe. See
++ * dwc_add_observer().
++ *
++ * A function of type dwc_notifier_callback_t is called whenever a notification
++ * is triggered with one or more observers observing it. This function is
++ * called in it's own process so it may sleep or block if needed. It is
++ * guaranteed to be called sometime after the notification has occurred and will
++ * be called once per each time the notification is triggered. It will NOT be
++ * called in the same process context used to trigger the notification.
++ *
++ * @section Limitiations
++ *
++ * Keep in mind that Notifications that can be triggered in rapid sucession may
++ * schedule too many processes too handle. Be aware of this limitation when
++ * designing to use notifications, and only add notifications for appropriate
++ * observable information.
++ *
++ * Also Notification callbacks are not synchronous. If you need to synchronize
++ * the behavior between module/observer you must use other means. And perhaps
++ * that will mean Notifications are not the proper solution.
++ */
++
++struct dwc_notifier;
++typedef struct dwc_notifier dwc_notifier_t;
++
++/** The callback function must be of this type.
++ *
++ * @param object This is the object that is being observed.
++ * @param notification This is the notification that was triggered.
++ * @param observer This is the observer
++ * @param notification_data This is notification-specific data that the notifier
++ * has included in this notification. The value of this should be published in
++ * the documentation of the observable module with the notifications.
++ * @param user_data This is any custom data that the observer provided when
++ * adding itself as an observer to the notification. */
++typedef void (*dwc_notifier_callback_t)(void *object, char *notification, void *observer,
++ void *notification_data, void *user_data);
++
++/** Brings up the notification manager. */
++extern int dwc_alloc_notification_manager(void *mem_ctx, void *wkq_ctx);
++/** Brings down the notification manager. */
++extern void dwc_free_notification_manager(void);
++
++/** This function registers an observable module. A dwc_notifier_t object is
++ * returned to the observable module. This is an opaque object that is used by
++ * the observable module to trigger notifications. This object should only be
++ * accessible to functions that are authorized to trigger notifications for this
++ * module. Observers do not need this object. */
++extern dwc_notifier_t *dwc_register_notifier(void *mem_ctx, void *object);
++
++/** This function unregisters an observable module. All observers have to be
++ * removed prior to unregistration. */
++extern void dwc_unregister_notifier(dwc_notifier_t *notifier);
++
++/** Add a module as an observer to the observable module. The observable module
++ * needs to have previously registered with the notification manager.
++ *
++ * @param observer The observer module
++ * @param object The module to observe
++ * @param notification The notification to observe
++ * @param callback The callback function to call
++ * @param user_data Any additional user data to pass into the callback function */
++extern int dwc_add_observer(void *observer, void *object, char *notification,
++ dwc_notifier_callback_t callback, void *user_data);
++
++/** Removes the specified observer from all notifications that it is currently
++ * observing. */
++extern int dwc_remove_observer(void *observer);
++
++/** This function triggers a Notification. It should be called by the
++ * observable module, or any module or library which the observable module
++ * allows to trigger notification on it's behalf. Such as the dwc_cc_t.
++ *
++ * dwc_notify is a non-blocking function. Callbacks are scheduled called in
++ * their own process context for each trigger. Callbacks can be blocking.
++ * dwc_notify can be called from interrupt context if needed.
++ *
++ */
++void dwc_notify(dwc_notifier_t *notifier, char *notification, void *notification_data);
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __DWC_NOTIFIER_H__ */
+diff -Nur linux-4.1.3/drivers/usb/host/dwc_common_port/dwc_os.h linux-xbian-rpi/drivers/usb/host/dwc_common_port/dwc_os.h
+--- linux-4.1.3/drivers/usb/host/dwc_common_port/dwc_os.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/usb/host/dwc_common_port/dwc_os.h 2015-07-28 01:20:58.441170694 +0200
+@@ -0,0 +1,1276 @@
++/* =========================================================================
++ * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_os.h $
++ * $Revision: #14 $
++ * $Date: 2010/11/04 $
++ * $Change: 1621695 $
++ *
++ * Synopsys Portability Library Software and documentation
++ * (hereinafter, "Software") is an Unsupported proprietary work of
++ * Synopsys, Inc. unless otherwise expressly agreed to in writing
++ * between Synopsys and you.
++ *
++ * The Software IS NOT an item of Licensed Software or Licensed Product
++ * under any End User Software License Agreement or Agreement for
++ * Licensed Product with Synopsys or any supplement thereto. You are
++ * permitted to use and redistribute this Software in source and binary
++ * forms, with or without modification, provided that redistributions
++ * of source code must retain this notice. You may not view, use,
++ * disclose, copy or distribute this file or any information contained
++ * herein except pursuant to this license grant from Synopsys. If you
++ * do not agree with this notice, including the disclaimer below, then
++ * you are not authorized to use the Software.
++ *
++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
++ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL
++ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
++ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
++ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++ * DAMAGE.
++ * ========================================================================= */
++#ifndef _DWC_OS_H_
++#define _DWC_OS_H_
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/** @file
++ *
++ * DWC portability library, low level os-wrapper functions
++ *
++ */
++
++/* These basic types need to be defined by some OS header file or custom header
++ * file for your specific target architecture.
++ *
++ * uint8_t, int8_t, uint16_t, int16_t, uint32_t, int32_t, uint64_t, int64_t
++ *
++ * Any custom or alternate header file must be added and enabled here.
++ */
++
++#ifdef DWC_LINUX
++# include <linux/types.h>
++# ifdef CONFIG_DEBUG_MUTEXES
++# include <linux/mutex.h>
++# endif
++# include <linux/spinlock.h>
++# include <linux/errno.h>
++# include <stdarg.h>
++#endif
++
++#if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
++# include <os_dep.h>
++#endif
++
++
++/** @name Primitive Types and Values */
++
++/** We define a boolean type for consistency. Can be either YES or NO */
++typedef uint8_t dwc_bool_t;
++#define YES 1
++#define NO 0
++
++#ifdef DWC_LINUX
++
++/** @name Error Codes */
++#define DWC_E_INVALID EINVAL
++#define DWC_E_NO_MEMORY ENOMEM
++#define DWC_E_NO_DEVICE ENODEV
++#define DWC_E_NOT_SUPPORTED EOPNOTSUPP
++#define DWC_E_TIMEOUT ETIMEDOUT
++#define DWC_E_BUSY EBUSY
++#define DWC_E_AGAIN EAGAIN
++#define DWC_E_RESTART ERESTART
++#define DWC_E_ABORT ECONNABORTED
++#define DWC_E_SHUTDOWN ESHUTDOWN
++#define DWC_E_NO_DATA ENODATA
++#define DWC_E_DISCONNECT ECONNRESET
++#define DWC_E_UNKNOWN EINVAL
++#define DWC_E_NO_STREAM_RES ENOSR
++#define DWC_E_COMMUNICATION ECOMM
++#define DWC_E_OVERFLOW EOVERFLOW
++#define DWC_E_PROTOCOL EPROTO
++#define DWC_E_IN_PROGRESS EINPROGRESS
++#define DWC_E_PIPE EPIPE
++#define DWC_E_IO EIO
++#define DWC_E_NO_SPACE ENOSPC
++
++#else
++
++/** @name Error Codes */
++#define DWC_E_INVALID 1001
++#define DWC_E_NO_MEMORY 1002
++#define DWC_E_NO_DEVICE 1003
++#define DWC_E_NOT_SUPPORTED 1004
++#define DWC_E_TIMEOUT 1005
++#define DWC_E_BUSY 1006
++#define DWC_E_AGAIN 1007
++#define DWC_E_RESTART 1008
++#define DWC_E_ABORT 1009
++#define DWC_E_SHUTDOWN 1010
++#define DWC_E_NO_DATA 1011
++#define DWC_E_DISCONNECT 2000
++#define DWC_E_UNKNOWN 3000
++#define DWC_E_NO_STREAM_RES 4001
++#define DWC_E_COMMUNICATION 4002
++#define DWC_E_OVERFLOW 4003
++#define DWC_E_PROTOCOL 4004
++#define DWC_E_IN_PROGRESS 4005
++#define DWC_E_PIPE 4006
++#define DWC_E_IO 4007
++#define DWC_E_NO_SPACE 4008
++
++#endif
++
++
++/** @name Tracing/Logging Functions
++ *
++ * These function provide the capability to add tracing, debugging, and error
++ * messages, as well exceptions as assertions. The WUDEV uses these
++ * extensively. These could be logged to the main console, the serial port, an
++ * internal buffer, etc. These functions could also be no-op if they are too
++ * expensive on your system. By default undefining the DEBUG macro already
++ * no-ops some of these functions. */
++
++/** Returns non-zero if in interrupt context. */
++extern dwc_bool_t DWC_IN_IRQ(void);
++#define dwc_in_irq DWC_IN_IRQ
++
++/** Returns "IRQ" if DWC_IN_IRQ is true. */
++static inline char *dwc_irq(void) {
++ return DWC_IN_IRQ() ? "IRQ" : "";
++}
++
++/** Returns non-zero if in bottom-half context. */
++extern dwc_bool_t DWC_IN_BH(void);
++#define dwc_in_bh DWC_IN_BH
++
++/** Returns "BH" if DWC_IN_BH is true. */
++static inline char *dwc_bh(void) {
++ return DWC_IN_BH() ? "BH" : "";
++}
++
++/**
++ * A vprintf() clone. Just call vprintf if you've got it.
++ */
++extern void DWC_VPRINTF(char *format, va_list args);
++#define dwc_vprintf DWC_VPRINTF
++
++/**
++ * A vsnprintf() clone. Just call vprintf if you've got it.
++ */
++extern int DWC_VSNPRINTF(char *str, int size, char *format, va_list args);
++#define dwc_vsnprintf DWC_VSNPRINTF
++
++/**
++ * printf() clone. Just call printf if you've go it.
++ */
++extern void DWC_PRINTF(char *format, ...)
++/* This provides compiler level static checking of the parameters if you're
++ * using GCC. */
++#ifdef __GNUC__
++ __attribute__ ((format(printf, 1, 2)));
++#else
++ ;
++#endif
++#define dwc_printf DWC_PRINTF
++
++/**
++ * sprintf() clone. Just call sprintf if you've got it.
++ */
++extern int DWC_SPRINTF(char *string, char *format, ...)
++#ifdef __GNUC__
++ __attribute__ ((format(printf, 2, 3)));
++#else
++ ;
++#endif
++#define dwc_sprintf DWC_SPRINTF
++
++/**
++ * snprintf() clone. Just call snprintf if you've got it.
++ */
++extern int DWC_SNPRINTF(char *string, int size, char *format, ...)
++#ifdef __GNUC__
++ __attribute__ ((format(printf, 3, 4)));
++#else
++ ;
++#endif
++#define dwc_snprintf DWC_SNPRINTF
++
++/**
++ * Prints a WARNING message. On systems that don't differentiate between
++ * warnings and regular log messages, just print it. Indicates that something
++ * may be wrong with the driver. Works like printf().
++ *
++ * Use the DWC_WARN macro to call this function.
++ */
++extern void __DWC_WARN(char *format, ...)
++#ifdef __GNUC__
++ __attribute__ ((format(printf, 1, 2)));
++#else
++ ;
++#endif
++
++/**
++ * Prints an error message. On systems that don't differentiate between errors
++ * and regular log messages, just print it. Indicates that something went wrong
++ * with the driver. Works like printf().
++ *
++ * Use the DWC_ERROR macro to call this function.
++ */
++extern void __DWC_ERROR(char *format, ...)
++#ifdef __GNUC__
++ __attribute__ ((format(printf, 1, 2)));
++#else
++ ;
++#endif
++
++/**
++ * Prints an exception error message and takes some user-defined action such as
++ * print out a backtrace or trigger a breakpoint. Indicates that something went
++ * abnormally wrong with the driver such as programmer error, or other
++ * exceptional condition. It should not be ignored so even on systems without
++ * printing capability, some action should be taken to notify the developer of
++ * it. Works like printf().
++ */
++extern void DWC_EXCEPTION(char *format, ...)
++#ifdef __GNUC__
++ __attribute__ ((format(printf, 1, 2)));
++#else
++ ;
++#endif
++#define dwc_exception DWC_EXCEPTION
++
++#ifndef DWC_OTG_DEBUG_LEV
++#define DWC_OTG_DEBUG_LEV 0
++#endif
++
++#ifdef DEBUG
++/**
++ * Prints out a debug message. Used for logging/trace messages.
++ *
++ * Use the DWC_DEBUG macro to call this function
++ */
++extern void __DWC_DEBUG(char *format, ...)
++#ifdef __GNUC__
++ __attribute__ ((format(printf, 1, 2)));
++#else
++ ;
++#endif
++#else
++#define __DWC_DEBUG printk
++#endif
++
++/**
++ * Prints out a Debug message.
++ */
++#define DWC_DEBUG(_format, _args...) __DWC_DEBUG("DEBUG:%s:%s: " _format "\n", \
++ __func__, dwc_irq(), ## _args)
++#define dwc_debug DWC_DEBUG
++/**
++ * Prints out a Debug message if enabled at compile time.
++ */
++#if DWC_OTG_DEBUG_LEV > 0
++#define DWC_DEBUGC(_format, _args...) DWC_DEBUG(_format, ##_args )
++#else
++#define DWC_DEBUGC(_format, _args...)
++#endif
++#define dwc_debugc DWC_DEBUGC
++/**
++ * Prints out an informative message.
++ */
++#define DWC_INFO(_format, _args...) DWC_PRINTF("INFO:%s: " _format "\n", \
++ dwc_irq(), ## _args)
++#define dwc_info DWC_INFO
++/**
++ * Prints out an informative message if enabled at compile time.
++ */
++#if DWC_OTG_DEBUG_LEV > 1
++#define DWC_INFOC(_format, _args...) DWC_INFO(_format, ##_args )
++#else
++#define DWC_INFOC(_format, _args...)
++#endif
++#define dwc_infoc DWC_INFOC
++/**
++ * Prints out a warning message.
++ */
++#define DWC_WARN(_format, _args...) __DWC_WARN("WARN:%s:%s:%d: " _format "\n", \
++ dwc_irq(), __func__, __LINE__, ## _args)
++#define dwc_warn DWC_WARN
++/**
++ * Prints out an error message.
++ */
++#define DWC_ERROR(_format, _args...) __DWC_ERROR("ERROR:%s:%s:%d: " _format "\n", \
++ dwc_irq(), __func__, __LINE__, ## _args)
++#define dwc_error DWC_ERROR
++
++#define DWC_PROTO_ERROR(_format, _args...) __DWC_WARN("ERROR:%s:%s:%d: " _format "\n", \
++ dwc_irq(), __func__, __LINE__, ## _args)
++#define dwc_proto_error DWC_PROTO_ERROR
++
++#ifdef DEBUG
++/** Prints out a exception error message if the _expr expression fails. Disabled
++ * if DEBUG is not enabled. */
++#define DWC_ASSERT(_expr, _format, _args...) do { \
++ if (!(_expr)) { DWC_EXCEPTION("%s:%s:%d: " _format "\n", dwc_irq(), \
++ __FILE__, __LINE__, ## _args); } \
++ } while (0)
++#else
++#define DWC_ASSERT(_x...)
++#endif
++#define dwc_assert DWC_ASSERT
++
++
++/** @name Byte Ordering
++ * The following functions are for conversions between processor's byte ordering
++ * and specific ordering you want.
++ */
++
++/** Converts 32 bit data in CPU byte ordering to little endian. */
++extern uint32_t DWC_CPU_TO_LE32(uint32_t *p);
++#define dwc_cpu_to_le32 DWC_CPU_TO_LE32
++
++/** Converts 32 bit data in CPU byte orderint to big endian. */
++extern uint32_t DWC_CPU_TO_BE32(uint32_t *p);
++#define dwc_cpu_to_be32 DWC_CPU_TO_BE32
++
++/** Converts 32 bit little endian data to CPU byte ordering. */
++extern uint32_t DWC_LE32_TO_CPU(uint32_t *p);
++#define dwc_le32_to_cpu DWC_LE32_TO_CPU
++
++/** Converts 32 bit big endian data to CPU byte ordering. */
++extern uint32_t DWC_BE32_TO_CPU(uint32_t *p);
++#define dwc_be32_to_cpu DWC_BE32_TO_CPU
++
++/** Converts 16 bit data in CPU byte ordering to little endian. */
++extern uint16_t DWC_CPU_TO_LE16(uint16_t *p);
++#define dwc_cpu_to_le16 DWC_CPU_TO_LE16
++
++/** Converts 16 bit data in CPU byte orderint to big endian. */
++extern uint16_t DWC_CPU_TO_BE16(uint16_t *p);
++#define dwc_cpu_to_be16 DWC_CPU_TO_BE16
++
++/** Converts 16 bit little endian data to CPU byte ordering. */
++extern uint16_t DWC_LE16_TO_CPU(uint16_t *p);
++#define dwc_le16_to_cpu DWC_LE16_TO_CPU
++
++/** Converts 16 bit bi endian data to CPU byte ordering. */
++extern uint16_t DWC_BE16_TO_CPU(uint16_t *p);
++#define dwc_be16_to_cpu DWC_BE16_TO_CPU
++
++
++/** @name Register Read/Write
++ *
++ * The following six functions should be implemented to read/write registers of
++ * 32-bit and 64-bit sizes. All modules use this to read/write register values.
++ * The reg value is a pointer to the register calculated from the void *base
++ * variable passed into the driver when it is started. */
++
++#ifdef DWC_LINUX
++/* Linux doesn't need any extra parameters for register read/write, so we
++ * just throw away the IO context parameter.
++ */
++/** Reads the content of a 32-bit register. */
++extern uint32_t DWC_READ_REG32(uint32_t volatile *reg);
++#define dwc_read_reg32(_ctx_,_reg_) DWC_READ_REG32(_reg_)
++
++/** Reads the content of a 64-bit register. */
++extern uint64_t DWC_READ_REG64(uint64_t volatile *reg);
++#define dwc_read_reg64(_ctx_,_reg_) DWC_READ_REG64(_reg_)
++
++/** Writes to a 32-bit register. */
++extern void DWC_WRITE_REG32(uint32_t volatile *reg, uint32_t value);
++#define dwc_write_reg32(_ctx_,_reg_,_val_) DWC_WRITE_REG32(_reg_, _val_)
++
++/** Writes to a 64-bit register. */
++extern void DWC_WRITE_REG64(uint64_t volatile *reg, uint64_t value);
++#define dwc_write_reg64(_ctx_,_reg_,_val_) DWC_WRITE_REG64(_reg_, _val_)
++
++/**
++ * Modify bit values in a register. Using the
++ * algorithm: (reg_contents & ~clear_mask) | set_mask.
++ */
++extern void DWC_MODIFY_REG32(uint32_t volatile *reg, uint32_t clear_mask, uint32_t set_mask);
++#define dwc_modify_reg32(_ctx_,_reg_,_cmsk_,_smsk_) DWC_MODIFY_REG32(_reg_,_cmsk_,_smsk_)
++extern void DWC_MODIFY_REG64(uint64_t volatile *reg, uint64_t clear_mask, uint64_t set_mask);
++#define dwc_modify_reg64(_ctx_,_reg_,_cmsk_,_smsk_) DWC_MODIFY_REG64(_reg_,_cmsk_,_smsk_)
++
++#endif /* DWC_LINUX */
++
++#if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
++typedef struct dwc_ioctx {
++ struct device *dev;
++ bus_space_tag_t iot;
++ bus_space_handle_t ioh;
++} dwc_ioctx_t;
++
++/** BSD needs two extra parameters for register read/write, so we pass
++ * them in using the IO context parameter.
++ */
++/** Reads the content of a 32-bit register. */
++extern uint32_t DWC_READ_REG32(void *io_ctx, uint32_t volatile *reg);
++#define dwc_read_reg32 DWC_READ_REG32
++
++/** Reads the content of a 64-bit register. */
++extern uint64_t DWC_READ_REG64(void *io_ctx, uint64_t volatile *reg);
++#define dwc_read_reg64 DWC_READ_REG64
++
++/** Writes to a 32-bit register. */
++extern void DWC_WRITE_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t value);
++#define dwc_write_reg32 DWC_WRITE_REG32
++
++/** Writes to a 64-bit register. */
++extern void DWC_WRITE_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t value);
++#define dwc_write_reg64 DWC_WRITE_REG64
++
++/**
++ * Modify bit values in a register. Using the
++ * algorithm: (reg_contents & ~clear_mask) | set_mask.
++ */
++extern void DWC_MODIFY_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t clear_mask, uint32_t set_mask);
++#define dwc_modify_reg32 DWC_MODIFY_REG32
++extern void DWC_MODIFY_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t clear_mask, uint64_t set_mask);
++#define dwc_modify_reg64 DWC_MODIFY_REG64
++
++#endif /* DWC_FREEBSD || DWC_NETBSD */
++
++/** @cond */
++
++/** @name Some convenience MACROS used internally. Define DWC_DEBUG_REGS to log the
++ * register writes. */
++
++#ifdef DWC_LINUX
++
++# ifdef DWC_DEBUG_REGS
++
++#define dwc_define_read_write_reg_n(_reg,_container_type) \
++static inline uint32_t dwc_read_##_reg##_n(_container_type *container, int num) { \
++ return DWC_READ_REG32(&container->regs->_reg[num]); \
++} \
++static inline void dwc_write_##_reg##_n(_container_type *container, int num, uint32_t data) { \
++ DWC_DEBUG("WRITING %8s[%d]: %p: %08x", #_reg, num, \
++ &(((uint32_t*)container->regs->_reg)[num]), data); \
++ DWC_WRITE_REG32(&(((uint32_t*)container->regs->_reg)[num]), data); \
++}
++
++#define dwc_define_read_write_reg(_reg,_container_type) \
++static inline uint32_t dwc_read_##_reg(_container_type *container) { \
++ return DWC_READ_REG32(&container->regs->_reg); \
++} \
++static inline void dwc_write_##_reg(_container_type *container, uint32_t data) { \
++ DWC_DEBUG("WRITING %11s: %p: %08x", #_reg, &container->regs->_reg, data); \
++ DWC_WRITE_REG32(&container->regs->_reg, data); \
++}
++
++# else /* DWC_DEBUG_REGS */
++
++#define dwc_define_read_write_reg_n(_reg,_container_type) \
++static inline uint32_t dwc_read_##_reg##_n(_container_type *container, int num) { \
++ return DWC_READ_REG32(&container->regs->_reg[num]); \
++} \
++static inline void dwc_write_##_reg##_n(_container_type *container, int num, uint32_t data) { \
++ DWC_WRITE_REG32(&(((uint32_t*)container->regs->_reg)[num]), data); \
++}
++
++#define dwc_define_read_write_reg(_reg,_container_type) \
++static inline uint32_t dwc_read_##_reg(_container_type *container) { \
++ return DWC_READ_REG32(&container->regs->_reg); \
++} \
++static inline void dwc_write_##_reg(_container_type *container, uint32_t data) { \
++ DWC_WRITE_REG32(&container->regs->_reg, data); \
++}
++
++# endif /* DWC_DEBUG_REGS */
++
++#endif /* DWC_LINUX */
++
++#if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
++
++# ifdef DWC_DEBUG_REGS
++
++#define dwc_define_read_write_reg_n(_reg,_container_type) \
++static inline uint32_t dwc_read_##_reg##_n(void *io_ctx, _container_type *container, int num) { \
++ return DWC_READ_REG32(io_ctx, &container->regs->_reg[num]); \
++} \
++static inline void dwc_write_##_reg##_n(void *io_ctx, _container_type *container, int num, uint32_t data) { \
++ DWC_DEBUG("WRITING %8s[%d]: %p: %08x", #_reg, num, \
++ &(((uint32_t*)container->regs->_reg)[num]), data); \
++ DWC_WRITE_REG32(io_ctx, &(((uint32_t*)container->regs->_reg)[num]), data); \
++}
++
++#define dwc_define_read_write_reg(_reg,_container_type) \
++static inline uint32_t dwc_read_##_reg(void *io_ctx, _container_type *container) { \
++ return DWC_READ_REG32(io_ctx, &container->regs->_reg); \
++} \
++static inline void dwc_write_##_reg(void *io_ctx, _container_type *container, uint32_t data) { \
++ DWC_DEBUG("WRITING %11s: %p: %08x", #_reg, &container->regs->_reg, data); \
++ DWC_WRITE_REG32(io_ctx, &container->regs->_reg, data); \
++}
++
++# else /* DWC_DEBUG_REGS */
++
++#define dwc_define_read_write_reg_n(_reg,_container_type) \
++static inline uint32_t dwc_read_##_reg##_n(void *io_ctx, _container_type *container, int num) { \
++ return DWC_READ_REG32(io_ctx, &container->regs->_reg[num]); \
++} \
++static inline void dwc_write_##_reg##_n(void *io_ctx, _container_type *container, int num, uint32_t data) { \
++ DWC_WRITE_REG32(io_ctx, &(((uint32_t*)container->regs->_reg)[num]), data); \
++}
++
++#define dwc_define_read_write_reg(_reg,_container_type) \
++static inline uint32_t dwc_read_##_reg(void *io_ctx, _container_type *container) { \
++ return DWC_READ_REG32(io_ctx, &container->regs->_reg); \
++} \
++static inline void dwc_write_##_reg(void *io_ctx, _container_type *container, uint32_t data) { \
++ DWC_WRITE_REG32(io_ctx, &container->regs->_reg, data); \
++}
++
++# endif /* DWC_DEBUG_REGS */
++
++#endif /* DWC_FREEBSD || DWC_NETBSD */
++
++/** @endcond */
++
++
++#ifdef DWC_CRYPTOLIB
++/** @name Crypto Functions
++ *
++ * These are the low-level cryptographic functions used by the driver. */
++
++/** Perform AES CBC */
++extern int DWC_AES_CBC(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t iv[16], uint8_t *out);
++#define dwc_aes_cbc DWC_AES_CBC
++
++/** Fill the provided buffer with random bytes. These should be cryptographic grade random numbers. */
++extern void DWC_RANDOM_BYTES(uint8_t *buffer, uint32_t length);
++#define dwc_random_bytes DWC_RANDOM_BYTES
++
++/** Perform the SHA-256 hash function */
++extern int DWC_SHA256(uint8_t *message, uint32_t len, uint8_t *out);
++#define dwc_sha256 DWC_SHA256
++
++/** Calculated the HMAC-SHA256 */
++extern int DWC_HMAC_SHA256(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t *out);
++#define dwc_hmac_sha256 DWC_HMAC_SHA256
++
++#endif /* DWC_CRYPTOLIB */
++
++
++/** @name Memory Allocation
++ *
++ * These function provide access to memory allocation. There are only 2 DMA
++ * functions and 3 Regular memory functions that need to be implemented. None
++ * of the memory debugging routines need to be implemented. The allocation
++ * routines all ZERO the contents of the memory.
++ *
++ * Defining DWC_DEBUG_MEMORY turns on memory debugging and statistic gathering.
++ * This checks for memory leaks, keeping track of alloc/free pairs. It also
++ * keeps track of how much memory the driver is using at any given time. */
++
++#define DWC_PAGE_SIZE 4096
++#define DWC_PAGE_OFFSET(addr) (((uint32_t)addr) & 0xfff)
++#define DWC_PAGE_ALIGNED(addr) ((((uint32_t)addr) & 0xfff) == 0)
++
++#define DWC_INVALID_DMA_ADDR 0x0
++
++#ifdef DWC_LINUX
++/** Type for a DMA address */
++typedef dma_addr_t dwc_dma_t;
++#endif
++
++#if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
++typedef bus_addr_t dwc_dma_t;
++#endif
++
++#ifdef DWC_FREEBSD
++typedef struct dwc_dmactx {
++ struct device *dev;
++ bus_dma_tag_t dma_tag;
++ bus_dmamap_t dma_map;
++ bus_addr_t dma_paddr;
++ void *dma_vaddr;
++} dwc_dmactx_t;
++#endif
++
++#ifdef DWC_NETBSD
++typedef struct dwc_dmactx {
++ struct device *dev;
++ bus_dma_tag_t dma_tag;
++ bus_dmamap_t dma_map;
++ bus_dma_segment_t segs[1];
++ int nsegs;
++ bus_addr_t dma_paddr;
++ void *dma_vaddr;
++} dwc_dmactx_t;
++#endif
++
++/* @todo these functions will be added in the future */
++#if 0
++/**
++ * Creates a DMA pool from which you can allocate DMA buffers. Buffers
++ * allocated from this pool will be guaranteed to meet the size, alignment, and
++ * boundary requirements specified.
++ *
++ * @param[in] size Specifies the size of the buffers that will be allocated from
++ * this pool.
++ * @param[in] align Specifies the byte alignment requirements of the buffers
++ * allocated from this pool. Must be a power of 2.
++ * @param[in] boundary Specifies the N-byte boundary that buffers allocated from
++ * this pool must not cross.
++ *
++ * @returns A pointer to an internal opaque structure which is not to be
++ * accessed outside of these library functions. Use this handle to specify
++ * which pools to allocate/free DMA buffers from and also to destroy the pool,
++ * when you are done with it.
++ */
++extern dwc_pool_t *DWC_DMA_POOL_CREATE(uint32_t size, uint32_t align, uint32_t boundary);
++
++/**
++ * Destroy a DMA pool. All buffers allocated from that pool must be freed first.
++ */
++extern void DWC_DMA_POOL_DESTROY(dwc_pool_t *pool);
++
++/**
++ * Allocate a buffer from the specified DMA pool and zeros its contents.
++ */
++extern void *DWC_DMA_POOL_ALLOC(dwc_pool_t *pool, uint64_t *dma_addr);
++
++/**
++ * Free a previously allocated buffer from the DMA pool.
++ */
++extern void DWC_DMA_POOL_FREE(dwc_pool_t *pool, void *vaddr, void *daddr);
++#endif
++
++/** Allocates a DMA capable buffer and zeroes its contents. */
++extern void *__DWC_DMA_ALLOC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr);
++
++/** Allocates a DMA capable buffer and zeroes its contents in atomic contest */
++extern void *__DWC_DMA_ALLOC_ATOMIC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr);
++
++/** Frees a previously allocated buffer. */
++extern void __DWC_DMA_FREE(void *dma_ctx, uint32_t size, void *virt_addr, dwc_dma_t dma_addr);
++
++/** Allocates a block of memory and zeroes its contents. */
++extern void *__DWC_ALLOC(void *mem_ctx, uint32_t size);
++
++/** Allocates a block of memory and zeroes its contents, in an atomic manner
++ * which can be used inside interrupt context. The size should be sufficiently
++ * small, a few KB at most, such that failures are not likely to occur. Can just call
++ * __DWC_ALLOC if it is atomic. */
++extern void *__DWC_ALLOC_ATOMIC(void *mem_ctx, uint32_t size);
++
++/** Frees a previously allocated buffer. */
++extern void __DWC_FREE(void *mem_ctx, void *addr);
++
++#ifndef DWC_DEBUG_MEMORY
++
++#define DWC_ALLOC(_size_) __DWC_ALLOC(NULL, _size_)
++#define DWC_ALLOC_ATOMIC(_size_) __DWC_ALLOC_ATOMIC(NULL, _size_)
++#define DWC_FREE(_addr_) __DWC_FREE(NULL, _addr_)
++
++# ifdef DWC_LINUX
++#define DWC_DMA_ALLOC(_size_,_dma_) __DWC_DMA_ALLOC(NULL, _size_, _dma_)
++#define DWC_DMA_ALLOC_ATOMIC(_size_,_dma_) __DWC_DMA_ALLOC_ATOMIC(NULL, _size_,_dma_)
++#define DWC_DMA_FREE(_size_,_virt_,_dma_) __DWC_DMA_FREE(NULL, _size_, _virt_, _dma_)
++# endif
++
++# if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
++#define DWC_DMA_ALLOC __DWC_DMA_ALLOC
++#define DWC_DMA_FREE __DWC_DMA_FREE
++# endif
++extern void *dwc_dma_alloc_atomic_debug(uint32_t size, dwc_dma_t *dma_addr, char const *func, int line);
++
++#else /* DWC_DEBUG_MEMORY */
++
++extern void *dwc_alloc_debug(void *mem_ctx, uint32_t size, char const *func, int line);
++extern void *dwc_alloc_atomic_debug(void *mem_ctx, uint32_t size, char const *func, int line);
++extern void dwc_free_debug(void *mem_ctx, void *addr, char const *func, int line);
++extern void *dwc_dma_alloc_debug(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr,
++ char const *func, int line);
++extern void *dwc_dma_alloc_atomic_debug(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr,
++ char const *func, int line);
++extern void dwc_dma_free_debug(void *dma_ctx, uint32_t size, void *virt_addr,
++ dwc_dma_t dma_addr, char const *func, int line);
++
++extern int dwc_memory_debug_start(void *mem_ctx);
++extern void dwc_memory_debug_stop(void);
++extern void dwc_memory_debug_report(void);
++
++#define DWC_ALLOC(_size_) dwc_alloc_debug(NULL, _size_, __func__, __LINE__)
++#define DWC_ALLOC_ATOMIC(_size_) dwc_alloc_atomic_debug(NULL, _size_, \
++ __func__, __LINE__)
++#define DWC_FREE(_addr_) dwc_free_debug(NULL, _addr_, __func__, __LINE__)
++
++# ifdef DWC_LINUX
++#define DWC_DMA_ALLOC(_size_,_dma_) dwc_dma_alloc_debug(NULL, _size_, \
++ _dma_, __func__, __LINE__)
++#define DWC_DMA_ALLOC_ATOMIC(_size_,_dma_) dwc_dma_alloc_atomic_debug(NULL, _size_, \
++ _dma_, __func__, __LINE__)
++#define DWC_DMA_FREE(_size_,_virt_,_dma_) dwc_dma_free_debug(NULL, _size_, \
++ _virt_, _dma_, __func__, __LINE__)
++# endif
++
++# if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
++#define DWC_DMA_ALLOC(_ctx_,_size_,_dma_) dwc_dma_alloc_debug(_ctx_, _size_, \
++ _dma_, __func__, __LINE__)
++#define DWC_DMA_FREE(_ctx_,_size_,_virt_,_dma_) dwc_dma_free_debug(_ctx_, _size_, \
++ _virt_, _dma_, __func__, __LINE__)
++# endif
++
++#endif /* DWC_DEBUG_MEMORY */
++
++#define dwc_alloc(_ctx_,_size_) DWC_ALLOC(_size_)
++#define dwc_alloc_atomic(_ctx_,_size_) DWC_ALLOC_ATOMIC(_size_)
++#define dwc_free(_ctx_,_addr_) DWC_FREE(_addr_)
++
++#ifdef DWC_LINUX
++/* Linux doesn't need any extra parameters for DMA buffer allocation, so we
++ * just throw away the DMA context parameter.
++ */
++#define dwc_dma_alloc(_ctx_,_size_,_dma_) DWC_DMA_ALLOC(_size_, _dma_)
++#define dwc_dma_alloc_atomic(_ctx_,_size_,_dma_) DWC_DMA_ALLOC_ATOMIC(_size_, _dma_)
++#define dwc_dma_free(_ctx_,_size_,_virt_,_dma_) DWC_DMA_FREE(_size_, _virt_, _dma_)
++#endif
++
++#if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
++/** BSD needs several extra parameters for DMA buffer allocation, so we pass
++ * them in using the DMA context parameter.
++ */
++#define dwc_dma_alloc DWC_DMA_ALLOC
++#define dwc_dma_free DWC_DMA_FREE
++#endif
++
++
++/** @name Memory and String Processing */
++
++/** memset() clone */
++extern void *DWC_MEMSET(void *dest, uint8_t byte, uint32_t size);
++#define dwc_memset DWC_MEMSET
++
++/** memcpy() clone */
++extern void *DWC_MEMCPY(void *dest, void const *src, uint32_t size);
++#define dwc_memcpy DWC_MEMCPY
++
++/** memmove() clone */
++extern void *DWC_MEMMOVE(void *dest, void *src, uint32_t size);
++#define dwc_memmove DWC_MEMMOVE
++
++/** memcmp() clone */
++extern int DWC_MEMCMP(void *m1, void *m2, uint32_t size);
++#define dwc_memcmp DWC_MEMCMP
++
++/** strcmp() clone */
++extern int DWC_STRCMP(void *s1, void *s2);
++#define dwc_strcmp DWC_STRCMP
++
++/** strncmp() clone */
++extern int DWC_STRNCMP(void *s1, void *s2, uint32_t size);
++#define dwc_strncmp DWC_STRNCMP
++
++/** strlen() clone, for NULL terminated ASCII strings */
++extern int DWC_STRLEN(char const *str);
++#define dwc_strlen DWC_STRLEN
++
++/** strcpy() clone, for NULL terminated ASCII strings */
++extern char *DWC_STRCPY(char *to, const char *from);
++#define dwc_strcpy DWC_STRCPY
++
++/** strdup() clone. If you wish to use memory allocation debugging, this
++ * implementation of strdup should use the DWC_* memory routines instead of
++ * calling a predefined strdup. Otherwise the memory allocated by this routine
++ * will not be seen by the debugging routines. */
++extern char *DWC_STRDUP(char const *str);
++#define dwc_strdup(_ctx_,_str_) DWC_STRDUP(_str_)
++
++/** NOT an atoi() clone. Read the description carefully. Returns an integer
++ * converted from the string str in base 10 unless the string begins with a "0x"
++ * in which case it is base 16. String must be a NULL terminated sequence of
++ * ASCII characters and may optionally begin with whitespace, a + or -, and a
++ * "0x" prefix if base 16. The remaining characters must be valid digits for
++ * the number and end with a NULL character. If any invalid characters are
++ * encountered or it returns with a negative error code and the results of the
++ * conversion are undefined. On sucess it returns 0. Overflow conditions are
++ * undefined. An example implementation using atoi() can be referenced from the
++ * Linux implementation. */
++extern int DWC_ATOI(const char *str, int32_t *value);
++#define dwc_atoi DWC_ATOI
++
++/** Same as above but for unsigned. */
++extern int DWC_ATOUI(const char *str, uint32_t *value);
++#define dwc_atoui DWC_ATOUI
++
++#ifdef DWC_UTFLIB
++/** This routine returns a UTF16LE unicode encoded string from a UTF8 string. */
++extern int DWC_UTF8_TO_UTF16LE(uint8_t const *utf8string, uint16_t *utf16string, unsigned len);
++#define dwc_utf8_to_utf16le DWC_UTF8_TO_UTF16LE
++#endif
++
++
++/** @name Wait queues
++ *
++ * Wait queues provide a means of synchronizing between threads or processes. A
++ * process can block on a waitq if some condition is not true, waiting for it to
++ * become true. When the waitq is triggered all waiting process will get
++ * unblocked and the condition will be check again. Waitqs should be triggered
++ * every time a condition can potentially change.*/
++struct dwc_waitq;
++
++/** Type for a waitq */
++typedef struct dwc_waitq dwc_waitq_t;
++
++/** The type of waitq condition callback function. This is called every time
++ * condition is evaluated. */
++typedef int (*dwc_waitq_condition_t)(void *data);
++
++/** Allocate a waitq */
++extern dwc_waitq_t *DWC_WAITQ_ALLOC(void);
++#define dwc_waitq_alloc(_ctx_) DWC_WAITQ_ALLOC()
++
++/** Free a waitq */
++extern void DWC_WAITQ_FREE(dwc_waitq_t *wq);
++#define dwc_waitq_free DWC_WAITQ_FREE
++
++/** Check the condition and if it is false, block on the waitq. When unblocked, check the
++ * condition again. The function returns when the condition becomes true. The return value
++ * is 0 on condition true, DWC_WAITQ_ABORTED on abort or killed, or DWC_WAITQ_UNKNOWN on error. */
++extern int32_t DWC_WAITQ_WAIT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, void *data);
++#define dwc_waitq_wait DWC_WAITQ_WAIT
++
++/** Check the condition and if it is false, block on the waitq. When unblocked,
++ * check the condition again. The function returns when the condition become
++ * true or the timeout has passed. The return value is 0 on condition true or
++ * DWC_TIMED_OUT on timeout, or DWC_WAITQ_ABORTED, or DWC_WAITQ_UNKNOWN on
++ * error. */
++extern int32_t DWC_WAITQ_WAIT_TIMEOUT(dwc_waitq_t *wq, dwc_waitq_condition_t cond,
++ void *data, int32_t msecs);
++#define dwc_waitq_wait_timeout DWC_WAITQ_WAIT_TIMEOUT
++
++/** Trigger a waitq, unblocking all processes. This should be called whenever a condition
++ * has potentially changed. */
++extern void DWC_WAITQ_TRIGGER(dwc_waitq_t *wq);
++#define dwc_waitq_trigger DWC_WAITQ_TRIGGER
++
++/** Unblock all processes waiting on the waitq with an ABORTED result. */
++extern void DWC_WAITQ_ABORT(dwc_waitq_t *wq);
++#define dwc_waitq_abort DWC_WAITQ_ABORT
++
++
++/** @name Threads
++ *
++ * A thread must be explicitly stopped. It must check DWC_THREAD_SHOULD_STOP
++ * whenever it is woken up, and then return. The DWC_THREAD_STOP function
++ * returns the value from the thread.
++ */
++
++struct dwc_thread;
++
++/** Type for a thread */
++typedef struct dwc_thread dwc_thread_t;
++
++/** The thread function */
++typedef int (*dwc_thread_function_t)(void *data);
++
++/** Create a thread and start it running the thread_function. Returns a handle
++ * to the thread */
++extern dwc_thread_t *DWC_THREAD_RUN(dwc_thread_function_t func, char *name, void *data);
++#define dwc_thread_run(_ctx_,_func_,_name_,_data_) DWC_THREAD_RUN(_func_, _name_, _data_)
++
++/** Stops a thread. Return the value returned by the thread. Or will return
++ * DWC_ABORT if the thread never started. */
++extern int DWC_THREAD_STOP(dwc_thread_t *thread);
++#define dwc_thread_stop DWC_THREAD_STOP
++
++/** Signifies to the thread that it must stop. */
++#ifdef DWC_LINUX
++/* Linux doesn't need any parameters for kthread_should_stop() */
++extern dwc_bool_t DWC_THREAD_SHOULD_STOP(void);
++#define dwc_thread_should_stop(_thrd_) DWC_THREAD_SHOULD_STOP()
++
++/* No thread_exit function in Linux */
++#define dwc_thread_exit(_thrd_)
++#endif
++
++#if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
++/** BSD needs the thread pointer for kthread_suspend_check() */
++extern dwc_bool_t DWC_THREAD_SHOULD_STOP(dwc_thread_t *thread);
++#define dwc_thread_should_stop DWC_THREAD_SHOULD_STOP
++
++/** The thread must call this to exit. */
++extern void DWC_THREAD_EXIT(dwc_thread_t *thread);
++#define dwc_thread_exit DWC_THREAD_EXIT
++#endif
++
++
++/** @name Work queues
++ *
++ * Workqs are used to queue a callback function to be called at some later time,
++ * in another thread. */
++struct dwc_workq;
++
++/** Type for a workq */
++typedef struct dwc_workq dwc_workq_t;
++
++/** The type of the callback function to be called. */
++typedef void (*dwc_work_callback_t)(void *data);
++
++/** Allocate a workq */
++extern dwc_workq_t *DWC_WORKQ_ALLOC(char *name);
++#define dwc_workq_alloc(_ctx_,_name_) DWC_WORKQ_ALLOC(_name_)
++
++/** Free a workq. All work must be completed before being freed. */
++extern void DWC_WORKQ_FREE(dwc_workq_t *workq);
++#define dwc_workq_free DWC_WORKQ_FREE
++
++/** Schedule a callback on the workq, passing in data. The function will be
++ * scheduled at some later time. */
++extern void DWC_WORKQ_SCHEDULE(dwc_workq_t *workq, dwc_work_callback_t cb,
++ void *data, char *format, ...)
++#ifdef __GNUC__
++ __attribute__ ((format(printf, 4, 5)));
++#else
++ ;
++#endif
++#define dwc_workq_schedule DWC_WORKQ_SCHEDULE
++
++/** Schedule a callback on the workq, that will be called until at least
++ * given number miliseconds have passed. */
++extern void DWC_WORKQ_SCHEDULE_DELAYED(dwc_workq_t *workq, dwc_work_callback_t cb,
++ void *data, uint32_t time, char *format, ...)
++#ifdef __GNUC__
++ __attribute__ ((format(printf, 5, 6)));
++#else
++ ;
++#endif
++#define dwc_workq_schedule_delayed DWC_WORKQ_SCHEDULE_DELAYED
++
++/** The number of processes in the workq */
++extern int DWC_WORKQ_PENDING(dwc_workq_t *workq);
++#define dwc_workq_pending DWC_WORKQ_PENDING
++
++/** Blocks until all the work in the workq is complete or timed out. Returns <
++ * 0 on timeout. */
++extern int DWC_WORKQ_WAIT_WORK_DONE(dwc_workq_t *workq, int timeout);
++#define dwc_workq_wait_work_done DWC_WORKQ_WAIT_WORK_DONE
++
++
++/** @name Tasklets
++ *
++ */
++struct dwc_tasklet;
++
++/** Type for a tasklet */
++typedef struct dwc_tasklet dwc_tasklet_t;
++
++/** The type of the callback function to be called */
++typedef void (*dwc_tasklet_callback_t)(void *data);
++
++/** Allocates a tasklet */
++extern dwc_tasklet_t *DWC_TASK_ALLOC(char *name, dwc_tasklet_callback_t cb, void *data);
++#define dwc_task_alloc(_ctx_,_name_,_cb_,_data_) DWC_TASK_ALLOC(_name_, _cb_, _data_)
++
++/** Frees a tasklet */
++extern void DWC_TASK_FREE(dwc_tasklet_t *task);
++#define dwc_task_free DWC_TASK_FREE
++
++/** Schedules a tasklet to run */
++extern void DWC_TASK_SCHEDULE(dwc_tasklet_t *task);
++#define dwc_task_schedule DWC_TASK_SCHEDULE
++
++extern void DWC_TASK_HI_SCHEDULE(dwc_tasklet_t *task);
++#define dwc_task_hi_schedule DWC_TASK_HI_SCHEDULE
++
++/** @name Timer
++ *
++ * Callbacks must be small and atomic.
++ */
++struct dwc_timer;
++
++/** Type for a timer */
++typedef struct dwc_timer dwc_timer_t;
++
++/** The type of the callback function to be called */
++typedef void (*dwc_timer_callback_t)(void *data);
++
++/** Allocates a timer */
++extern dwc_timer_t *DWC_TIMER_ALLOC(char *name, dwc_timer_callback_t cb, void *data);
++#define dwc_timer_alloc(_ctx_,_name_,_cb_,_data_) DWC_TIMER_ALLOC(_name_,_cb_,_data_)
++
++/** Frees a timer */
++extern void DWC_TIMER_FREE(dwc_timer_t *timer);
++#define dwc_timer_free DWC_TIMER_FREE
++
++/** Schedules the timer to run at time ms from now. And will repeat at every
++ * repeat_interval msec therafter
++ *
++ * Modifies a timer that is still awaiting execution to a new expiration time.
++ * The mod_time is added to the old time. */
++extern void DWC_TIMER_SCHEDULE(dwc_timer_t *timer, uint32_t time);
++#define dwc_timer_schedule DWC_TIMER_SCHEDULE
++
++/** Disables the timer from execution. */
++extern void DWC_TIMER_CANCEL(dwc_timer_t *timer);
++#define dwc_timer_cancel DWC_TIMER_CANCEL
++
++
++/** @name Spinlocks
++ *
++ * These locks are used when the work between the lock/unlock is atomic and
++ * short. Interrupts are also disabled during the lock/unlock and thus they are
++ * suitable to lock between interrupt/non-interrupt context. They also lock
++ * between processes if you have multiple CPUs or Preemption. If you don't have
++ * multiple CPUS or Preemption, then the you can simply implement the
++ * DWC_SPINLOCK and DWC_SPINUNLOCK to disable and enable interrupts. Because
++ * the work between the lock/unlock is atomic, the process context will never
++ * change, and so you never have to lock between processes. */
++
++struct dwc_spinlock;
++
++/** Type for a spinlock */
++typedef struct dwc_spinlock dwc_spinlock_t;
++
++/** Type for the 'flags' argument to spinlock funtions */
++typedef unsigned long dwc_irqflags_t;
++
++/** Returns an initialized lock variable. This function should allocate and
++ * initialize the OS-specific data structure used for locking. This data
++ * structure is to be used for the DWC_LOCK and DWC_UNLOCK functions and should
++ * be freed by the DWC_FREE_LOCK when it is no longer used.
++ *
++ * For Linux Spinlock Debugging make it macro because the debugging routines use
++ * the symbol name to determine recursive locking. Using a wrapper function
++ * makes it falsely think recursive locking occurs. */
++#if defined(DWC_LINUX) && defined(CONFIG_DEBUG_SPINLOCK)
++#define DWC_SPINLOCK_ALLOC_LINUX_DEBUG(lock) ({ \
++ lock = DWC_ALLOC(sizeof(spinlock_t)); \
++ if (lock) { \
++ spin_lock_init((spinlock_t *)lock); \
++ } \
++})
++#else
++extern dwc_spinlock_t *DWC_SPINLOCK_ALLOC(void);
++#define dwc_spinlock_alloc(_ctx_) DWC_SPINLOCK_ALLOC()
++#endif
++
++/** Frees an initialized lock variable. */
++extern void DWC_SPINLOCK_FREE(dwc_spinlock_t *lock);
++#define dwc_spinlock_free(_ctx_,_lock_) DWC_SPINLOCK_FREE(_lock_)
++
++/** Disables interrupts and blocks until it acquires the lock.
++ *
++ * @param lock Pointer to the spinlock.
++ * @param flags Unsigned long for irq flags storage.
++ */
++extern void DWC_SPINLOCK_IRQSAVE(dwc_spinlock_t *lock, dwc_irqflags_t *flags);
++#define dwc_spinlock_irqsave DWC_SPINLOCK_IRQSAVE
++
++/** Re-enables the interrupt and releases the lock.
++ *
++ * @param lock Pointer to the spinlock.
++ * @param flags Unsigned long for irq flags storage. Must be the same as was
++ * passed into DWC_LOCK.
++ */
++extern void DWC_SPINUNLOCK_IRQRESTORE(dwc_spinlock_t *lock, dwc_irqflags_t flags);
++#define dwc_spinunlock_irqrestore DWC_SPINUNLOCK_IRQRESTORE
++
++/** Blocks until it acquires the lock.
++ *
++ * @param lock Pointer to the spinlock.
++ */
++extern void DWC_SPINLOCK(dwc_spinlock_t *lock);
++#define dwc_spinlock DWC_SPINLOCK
++
++/** Releases the lock.
++ *
++ * @param lock Pointer to the spinlock.
++ */
++extern void DWC_SPINUNLOCK(dwc_spinlock_t *lock);
++#define dwc_spinunlock DWC_SPINUNLOCK
++
++
++/** @name Mutexes
++ *
++ * Unlike spinlocks Mutexes lock only between processes and the work between the
++ * lock/unlock CAN block, therefore it CANNOT be called from interrupt context.
++ */
++
++struct dwc_mutex;
++
++/** Type for a mutex */
++typedef struct dwc_mutex dwc_mutex_t;
++
++/* For Linux Mutex Debugging make it inline because the debugging routines use
++ * the symbol to determine recursive locking. This makes it falsely think
++ * recursive locking occurs. */
++#if defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES)
++#define DWC_MUTEX_ALLOC_LINUX_DEBUG(__mutexp) ({ \
++ __mutexp = (dwc_mutex_t *)DWC_ALLOC(sizeof(struct mutex)); \
++ mutex_init((struct mutex *)__mutexp); \
++})
++#endif
++
++/** Allocate a mutex */
++extern dwc_mutex_t *DWC_MUTEX_ALLOC(void);
++#define dwc_mutex_alloc(_ctx_) DWC_MUTEX_ALLOC()
++
++/* For memory leak debugging when using Linux Mutex Debugging */
++#if defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES)
++#define DWC_MUTEX_FREE(__mutexp) do { \
++ mutex_destroy((struct mutex *)__mutexp); \
++ DWC_FREE(__mutexp); \
++} while(0)
++#else
++/** Free a mutex */
++extern void DWC_MUTEX_FREE(dwc_mutex_t *mutex);
++#define dwc_mutex_free(_ctx_,_mutex_) DWC_MUTEX_FREE(_mutex_)
++#endif
++
++/** Lock a mutex */
++extern void DWC_MUTEX_LOCK(dwc_mutex_t *mutex);
++#define dwc_mutex_lock DWC_MUTEX_LOCK
++
++/** Non-blocking lock returns 1 on successful lock. */
++extern int DWC_MUTEX_TRYLOCK(dwc_mutex_t *mutex);
++#define dwc_mutex_trylock DWC_MUTEX_TRYLOCK
++
++/** Unlock a mutex */
++extern void DWC_MUTEX_UNLOCK(dwc_mutex_t *mutex);
++#define dwc_mutex_unlock DWC_MUTEX_UNLOCK
++
++
++/** @name Time */
++
++/** Microsecond delay.
++ *
++ * @param usecs Microseconds to delay.
++ */
++extern void DWC_UDELAY(uint32_t usecs);
++#define dwc_udelay DWC_UDELAY
++
++/** Millisecond delay.
++ *
++ * @param msecs Milliseconds to delay.
++ */
++extern void DWC_MDELAY(uint32_t msecs);
++#define dwc_mdelay DWC_MDELAY
++
++/** Non-busy waiting.
++ * Sleeps for specified number of milliseconds.
++ *
++ * @param msecs Milliseconds to sleep.
++ */
++extern void DWC_MSLEEP(uint32_t msecs);
++#define dwc_msleep DWC_MSLEEP
++
++/**
++ * Returns number of milliseconds since boot.
++ */
++extern uint32_t DWC_TIME(void);
++#define dwc_time DWC_TIME
++
++
++
++
++/* @mainpage DWC Portability and Common Library
++ *
++ * This is the documentation for the DWC Portability and Common Library.
++ *
++ * @section intro Introduction
++ *
++ * The DWC Portability library consists of wrapper calls and data structures to
++ * all low-level functions which are typically provided by the OS. The WUDEV
++ * driver uses only these functions. In order to port the WUDEV driver, only
++ * the functions in this library need to be re-implemented, with the same
++ * behavior as documented here.
++ *
++ * The Common library consists of higher level functions, which rely only on
++ * calling the functions from the DWC Portability library. These common
++ * routines are shared across modules. Some of the common libraries need to be
++ * used directly by the driver programmer when porting WUDEV. Such as the
++ * parameter and notification libraries.
++ *
++ * @section low Portability Library OS Wrapper Functions
++ *
++ * Any function starting with DWC and in all CAPS is a low-level OS-wrapper that
++ * needs to be implemented when porting, for example DWC_MUTEX_ALLOC(). All of
++ * these functions are included in the dwc_os.h file.
++ *
++ * There are many functions here covering a wide array of OS services. Please
++ * see dwc_os.h for details, and implementation notes for each function.
++ *
++ * @section common Common Library Functions
++ *
++ * Any function starting with dwc and in all lowercase is a common library
++ * routine. These functions have a portable implementation and do not need to
++ * be reimplemented when porting. The common routines can be used by any
++ * driver, and some must be used by the end user to control the drivers. For
++ * example, you must use the Parameter common library in order to set the
++ * parameters in the WUDEV module.
++ *
++ * The common libraries consist of the following:
++ *
++ * - Connection Contexts - Used internally and can be used by end-user. See dwc_cc.h
++ * - Parameters - Used internally and can be used by end-user. See dwc_params.h
++ * - Notifications - Used internally and can be used by end-user. See dwc_notifier.h
++ * - Lists - Used internally and can be used by end-user. See dwc_list.h
++ * - Memory Debugging - Used internally and can be used by end-user. See dwc_os.h
++ * - Modpow - Used internally only. See dwc_modpow.h
++ * - DH - Used internally only. See dwc_dh.h
++ * - Crypto - Used internally only. See dwc_crypto.h
++ *
++ *
++ * @section prereq Prerequistes For dwc_os.h
++ * @subsection types Data Types
++ *
++ * The dwc_os.h file assumes that several low-level data types are pre defined for the
++ * compilation environment. These data types are:
++ *
++ * - uint8_t - unsigned 8-bit data type
++ * - int8_t - signed 8-bit data type
++ * - uint16_t - unsigned 16-bit data type
++ * - int16_t - signed 16-bit data type
++ * - uint32_t - unsigned 32-bit data type
++ * - int32_t - signed 32-bit data type
++ * - uint64_t - unsigned 64-bit data type
++ * - int64_t - signed 64-bit data type
++ *
++ * Ensure that these are defined before using dwc_os.h. The easiest way to do
++ * that is to modify the top of the file to include the appropriate header.
++ * This is already done for the Linux environment. If the DWC_LINUX macro is
++ * defined, the correct header will be added. A standard header <stdint.h> is
++ * also used for environments where standard C headers are available.
++ *
++ * @subsection stdarg Variable Arguments
++ *
++ * Variable arguments are provided by a standard C header <stdarg.h>. it is
++ * available in Both the Linux and ANSI C enviornment. An equivalent must be
++ * provided in your enviornment in order to use dwc_os.h with the debug and
++ * tracing message functionality.
++ *
++ * @subsection thread Threading
++ *
++ * WUDEV Core must be run on an operating system that provides for multiple
++ * threads/processes. Threading can be implemented in many ways, even in
++ * embedded systems without an operating system. At the bare minimum, the
++ * system should be able to start any number of processes at any time to handle
++ * special work. It need not be a pre-emptive system. Process context can
++ * change upon a call to a blocking function. The hardware interrupt context
++ * that calls the module's ISR() function must be differentiable from process
++ * context, even if your processes are impemented via a hardware interrupt.
++ * Further locking mechanism between process must exist (or be implemented), and
++ * process context must have a way to disable interrupts for a period of time to
++ * lock them out. If all of this exists, the functions in dwc_os.h related to
++ * threading should be able to be implemented with the defined behavior.
++ *
++ */
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* _DWC_OS_H_ */
+diff -Nur linux-4.1.3/drivers/usb/host/dwc_common_port/Makefile linux-xbian-rpi/drivers/usb/host/dwc_common_port/Makefile
+--- linux-4.1.3/drivers/usb/host/dwc_common_port/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/usb/host/dwc_common_port/Makefile 2015-07-28 01:20:58.441170694 +0200
+@@ -0,0 +1,58 @@
++#
++# Makefile for DWC_common library
++#
++
++ifneq ($(KERNELRELEASE),)
++
++ccflags-y += -DDWC_LINUX
++#ccflags-y += -DDEBUG
++#ccflags-y += -DDWC_DEBUG_REGS
++#ccflags-y += -DDWC_DEBUG_MEMORY
++
++ccflags-y += -DDWC_LIBMODULE
++ccflags-y += -DDWC_CCLIB
++#ccflags-y += -DDWC_CRYPTOLIB
++ccflags-y += -DDWC_NOTIFYLIB
++ccflags-y += -DDWC_UTFLIB
++
++obj-$(CONFIG_USB_DWCOTG) += dwc_common_port_lib.o
++dwc_common_port_lib-objs := dwc_cc.o dwc_modpow.o dwc_dh.o \
++ dwc_crypto.o dwc_notifier.o \
++ dwc_common_linux.o dwc_mem.o
++
++kernrelwd := $(subst ., ,$(KERNELRELEASE))
++kernrel3 := $(word 1,$(kernrelwd)).$(word 2,$(kernrelwd)).$(word 3,$(kernrelwd))
++
++ifneq ($(kernrel3),2.6.20)
++# grayg - I only know that we use ccflags-y in 2.6.31 actually
++ccflags-y += $(CPPFLAGS)
++endif
++
++else
++
++#ifeq ($(KDIR),)
++#$(error Must give "KDIR=/path/to/kernel/source" on command line or in environment)
++#endif
++
++ifeq ($(ARCH),)
++$(error Must give "ARCH=<arch>" on command line or in environment. Also, if \
++ cross-compiling, must give "CROSS_COMPILE=/path/to/compiler/plus/tool-prefix-")
++endif
++
++ifeq ($(DOXYGEN),)
++DOXYGEN := doxygen
++endif
++
++default:
++ $(MAKE) -C$(KDIR) M=$(PWD) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) modules
++
++docs: $(wildcard *.[hc]) doc/doxygen.cfg
++ $(DOXYGEN) doc/doxygen.cfg
++
++tags: $(wildcard *.[hc])
++ $(CTAGS) -e $(wildcard *.[hc]) $(wildcard linux/*.[hc]) $(wildcard $(KDIR)/include/linux/usb*.h)
++
++endif
++
++clean:
++ rm -rf *.o *.ko .*.cmd *.mod.c .*.o.d .*.o.tmp modules.order Module.markers Module.symvers .tmp_versions/
+diff -Nur linux-4.1.3/drivers/usb/host/dwc_common_port/Makefile.fbsd linux-xbian-rpi/drivers/usb/host/dwc_common_port/Makefile.fbsd
+--- linux-4.1.3/drivers/usb/host/dwc_common_port/Makefile.fbsd 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/usb/host/dwc_common_port/Makefile.fbsd 2015-07-28 01:20:58.441170694 +0200
+@@ -0,0 +1,17 @@
++CFLAGS += -I/sys/i386/compile/GENERIC -I/sys/i386/include -I/usr/include
++CFLAGS += -DDWC_FREEBSD
++CFLAGS += -DDEBUG
++#CFLAGS += -DDWC_DEBUG_REGS
++#CFLAGS += -DDWC_DEBUG_MEMORY
++
++#CFLAGS += -DDWC_LIBMODULE
++#CFLAGS += -DDWC_CCLIB
++#CFLAGS += -DDWC_CRYPTOLIB
++#CFLAGS += -DDWC_NOTIFYLIB
++#CFLAGS += -DDWC_UTFLIB
++
++KMOD = dwc_common_port_lib
++SRCS = dwc_cc.c dwc_modpow.c dwc_dh.c dwc_crypto.c dwc_notifier.c \
++ dwc_common_fbsd.c dwc_mem.c
++
++.include <bsd.kmod.mk>
+diff -Nur linux-4.1.3/drivers/usb/host/dwc_common_port/Makefile.linux linux-xbian-rpi/drivers/usb/host/dwc_common_port/Makefile.linux
+--- linux-4.1.3/drivers/usb/host/dwc_common_port/Makefile.linux 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/usb/host/dwc_common_port/Makefile.linux 2015-07-28 01:20:58.441170694 +0200
+@@ -0,0 +1,49 @@
++#
++# Makefile for DWC_common library
++#
++ifneq ($(KERNELRELEASE),)
++
++ccflags-y += -DDWC_LINUX
++#ccflags-y += -DDEBUG
++#ccflags-y += -DDWC_DEBUG_REGS
++#ccflags-y += -DDWC_DEBUG_MEMORY
++
++ccflags-y += -DDWC_LIBMODULE
++ccflags-y += -DDWC_CCLIB
++ccflags-y += -DDWC_CRYPTOLIB
++ccflags-y += -DDWC_NOTIFYLIB
++ccflags-y += -DDWC_UTFLIB
++
++obj-m := dwc_common_port_lib.o
++dwc_common_port_lib-objs := dwc_cc.o dwc_modpow.o dwc_dh.o \
++ dwc_crypto.o dwc_notifier.o \
++ dwc_common_linux.o dwc_mem.o
++
++else
++
++ifeq ($(KDIR),)
++$(error Must give "KDIR=/path/to/kernel/source" on command line or in environment)
++endif
++
++ifeq ($(ARCH),)
++$(error Must give "ARCH=<arch>" on command line or in environment. Also, if \
++ cross-compiling, must give "CROSS_COMPILE=/path/to/compiler/plus/tool-prefix-")
++endif
++
++ifeq ($(DOXYGEN),)
++DOXYGEN := doxygen
++endif
++
++default:
++ $(MAKE) -C$(KDIR) M=$(PWD) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) modules
++
++docs: $(wildcard *.[hc]) doc/doxygen.cfg
++ $(DOXYGEN) doc/doxygen.cfg
++
++tags: $(wildcard *.[hc])
++ $(CTAGS) -e $(wildcard *.[hc]) $(wildcard linux/*.[hc]) $(wildcard $(KDIR)/include/linux/usb*.h)
++
++endif
++
++clean:
++ rm -rf *.o *.ko .*.cmd *.mod.c .*.o.d .*.o.tmp modules.order Module.markers Module.symvers .tmp_versions/
+diff -Nur linux-4.1.3/drivers/usb/host/dwc_common_port/usb.h linux-xbian-rpi/drivers/usb/host/dwc_common_port/usb.h
+--- linux-4.1.3/drivers/usb/host/dwc_common_port/usb.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/usb/host/dwc_common_port/usb.h 2015-07-28 01:20:58.445156473 +0200
+@@ -0,0 +1,946 @@
++/*
++ * Copyright (c) 1998 The NetBSD Foundation, Inc.
++ * All rights reserved.
++ *
++ * This code is derived from software contributed to The NetBSD Foundation
++ * by Lennart Augustsson (lennart@augustsson.net) at
++ * Carlstedt Research & Technology.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ * 1. Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ * 2. Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * 3. All advertising materials mentioning features or use of this software
++ * must display the following acknowledgement:
++ * This product includes software developed by the NetBSD
++ * Foundation, Inc. and its contributors.
++ * 4. Neither the name of The NetBSD Foundation nor the names of its
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
++ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
++ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
++ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ */
++
++/* Modified by Synopsys, Inc, 12/12/2007 */
++
++
++#ifndef _USB_H_
++#define _USB_H_
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/*
++ * The USB records contain some unaligned little-endian word
++ * components. The U[SG]ETW macros take care of both the alignment
++ * and endian problem and should always be used to access non-byte
++ * values.
++ */
++typedef u_int8_t uByte;
++typedef u_int8_t uWord[2];
++typedef u_int8_t uDWord[4];
++
++#define USETW2(w,h,l) ((w)[0] = (u_int8_t)(l), (w)[1] = (u_int8_t)(h))
++#define UCONSTW(x) { (x) & 0xff, ((x) >> 8) & 0xff }
++#define UCONSTDW(x) { (x) & 0xff, ((x) >> 8) & 0xff, \
++ ((x) >> 16) & 0xff, ((x) >> 24) & 0xff }
++
++#if 1
++#define UGETW(w) ((w)[0] | ((w)[1] << 8))
++#define USETW(w,v) ((w)[0] = (u_int8_t)(v), (w)[1] = (u_int8_t)((v) >> 8))
++#define UGETDW(w) ((w)[0] | ((w)[1] << 8) | ((w)[2] << 16) | ((w)[3] << 24))
++#define USETDW(w,v) ((w)[0] = (u_int8_t)(v), \
++ (w)[1] = (u_int8_t)((v) >> 8), \
++ (w)[2] = (u_int8_t)((v) >> 16), \
++ (w)[3] = (u_int8_t)((v) >> 24))
++#else
++/*
++ * On little-endian machines that can handle unanliged accesses
++ * (e.g. i386) these macros can be replaced by the following.
++ */
++#define UGETW(w) (*(u_int16_t *)(w))
++#define USETW(w,v) (*(u_int16_t *)(w) = (v))
++#define UGETDW(w) (*(u_int32_t *)(w))
++#define USETDW(w,v) (*(u_int32_t *)(w) = (v))
++#endif
++
++/*
++ * Macros for accessing UAS IU fields, which are big-endian
++ */
++#define IUSETW2(w,h,l) ((w)[0] = (u_int8_t)(h), (w)[1] = (u_int8_t)(l))
++#define IUCONSTW(x) { ((x) >> 8) & 0xff, (x) & 0xff }
++#define IUCONSTDW(x) { ((x) >> 24) & 0xff, ((x) >> 16) & 0xff, \
++ ((x) >> 8) & 0xff, (x) & 0xff }
++#define IUGETW(w) (((w)[0] << 8) | (w)[1])
++#define IUSETW(w,v) ((w)[0] = (u_int8_t)((v) >> 8), (w)[1] = (u_int8_t)(v))
++#define IUGETDW(w) (((w)[0] << 24) | ((w)[1] << 16) | ((w)[2] << 8) | (w)[3])
++#define IUSETDW(w,v) ((w)[0] = (u_int8_t)((v) >> 24), \
++ (w)[1] = (u_int8_t)((v) >> 16), \
++ (w)[2] = (u_int8_t)((v) >> 8), \
++ (w)[3] = (u_int8_t)(v))
++
++#define UPACKED __attribute__((__packed__))
++
++typedef struct {
++ uByte bmRequestType;
++ uByte bRequest;
++ uWord wValue;
++ uWord wIndex;
++ uWord wLength;
++} UPACKED usb_device_request_t;
++
++#define UT_GET_DIR(a) ((a) & 0x80)
++#define UT_WRITE 0x00
++#define UT_READ 0x80
++
++#define UT_GET_TYPE(a) ((a) & 0x60)
++#define UT_STANDARD 0x00
++#define UT_CLASS 0x20
++#define UT_VENDOR 0x40
++
++#define UT_GET_RECIPIENT(a) ((a) & 0x1f)
++#define UT_DEVICE 0x00
++#define UT_INTERFACE 0x01
++#define UT_ENDPOINT 0x02
++#define UT_OTHER 0x03
++
++#define UT_READ_DEVICE (UT_READ | UT_STANDARD | UT_DEVICE)
++#define UT_READ_INTERFACE (UT_READ | UT_STANDARD | UT_INTERFACE)
++#define UT_READ_ENDPOINT (UT_READ | UT_STANDARD | UT_ENDPOINT)
++#define UT_WRITE_DEVICE (UT_WRITE | UT_STANDARD | UT_DEVICE)
++#define UT_WRITE_INTERFACE (UT_WRITE | UT_STANDARD | UT_INTERFACE)
++#define UT_WRITE_ENDPOINT (UT_WRITE | UT_STANDARD | UT_ENDPOINT)
++#define UT_READ_CLASS_DEVICE (UT_READ | UT_CLASS | UT_DEVICE)
++#define UT_READ_CLASS_INTERFACE (UT_READ | UT_CLASS | UT_INTERFACE)
++#define UT_READ_CLASS_OTHER (UT_READ | UT_CLASS | UT_OTHER)
++#define UT_READ_CLASS_ENDPOINT (UT_READ | UT_CLASS | UT_ENDPOINT)
++#define UT_WRITE_CLASS_DEVICE (UT_WRITE | UT_CLASS | UT_DEVICE)
++#define UT_WRITE_CLASS_INTERFACE (UT_WRITE | UT_CLASS | UT_INTERFACE)
++#define UT_WRITE_CLASS_OTHER (UT_WRITE | UT_CLASS | UT_OTHER)
++#define UT_WRITE_CLASS_ENDPOINT (UT_WRITE | UT_CLASS | UT_ENDPOINT)
++#define UT_READ_VENDOR_DEVICE (UT_READ | UT_VENDOR | UT_DEVICE)
++#define UT_READ_VENDOR_INTERFACE (UT_READ | UT_VENDOR | UT_INTERFACE)
++#define UT_READ_VENDOR_OTHER (UT_READ | UT_VENDOR | UT_OTHER)
++#define UT_READ_VENDOR_ENDPOINT (UT_READ | UT_VENDOR | UT_ENDPOINT)
++#define UT_WRITE_VENDOR_DEVICE (UT_WRITE | UT_VENDOR | UT_DEVICE)
++#define UT_WRITE_VENDOR_INTERFACE (UT_WRITE | UT_VENDOR | UT_INTERFACE)
++#define UT_WRITE_VENDOR_OTHER (UT_WRITE | UT_VENDOR | UT_OTHER)
++#define UT_WRITE_VENDOR_ENDPOINT (UT_WRITE | UT_VENDOR | UT_ENDPOINT)
++
++/* Requests */
++#define UR_GET_STATUS 0x00
++#define USTAT_STANDARD_STATUS 0x00
++#define WUSTAT_WUSB_FEATURE 0x01
++#define WUSTAT_CHANNEL_INFO 0x02
++#define WUSTAT_RECEIVED_DATA 0x03
++#define WUSTAT_MAS_AVAILABILITY 0x04
++#define WUSTAT_CURRENT_TRANSMIT_POWER 0x05
++#define UR_CLEAR_FEATURE 0x01
++#define UR_SET_FEATURE 0x03
++#define UR_SET_AND_TEST_FEATURE 0x0c
++#define UR_SET_ADDRESS 0x05
++#define UR_GET_DESCRIPTOR 0x06
++#define UDESC_DEVICE 0x01
++#define UDESC_CONFIG 0x02
++#define UDESC_STRING 0x03
++#define UDESC_INTERFACE 0x04
++#define UDESC_ENDPOINT 0x05
++#define UDESC_SS_USB_COMPANION 0x30
++#define UDESC_DEVICE_QUALIFIER 0x06
++#define UDESC_OTHER_SPEED_CONFIGURATION 0x07
++#define UDESC_INTERFACE_POWER 0x08
++#define UDESC_OTG 0x09
++#define WUDESC_SECURITY 0x0c
++#define WUDESC_KEY 0x0d
++#define WUD_GET_KEY_INDEX(_wValue_) ((_wValue_) & 0xf)
++#define WUD_GET_KEY_TYPE(_wValue_) (((_wValue_) & 0x30) >> 4)
++#define WUD_KEY_TYPE_ASSOC 0x01
++#define WUD_KEY_TYPE_GTK 0x02
++#define WUD_GET_KEY_ORIGIN(_wValue_) (((_wValue_) & 0x40) >> 6)
++#define WUD_KEY_ORIGIN_HOST 0x00
++#define WUD_KEY_ORIGIN_DEVICE 0x01
++#define WUDESC_ENCRYPTION_TYPE 0x0e
++#define WUDESC_BOS 0x0f
++#define WUDESC_DEVICE_CAPABILITY 0x10
++#define WUDESC_WIRELESS_ENDPOINT_COMPANION 0x11
++#define UDESC_BOS 0x0f
++#define UDESC_DEVICE_CAPABILITY 0x10
++#define UDESC_CS_DEVICE 0x21 /* class specific */
++#define UDESC_CS_CONFIG 0x22
++#define UDESC_CS_STRING 0x23
++#define UDESC_CS_INTERFACE 0x24
++#define UDESC_CS_ENDPOINT 0x25
++#define UDESC_HUB 0x29
++#define UR_SET_DESCRIPTOR 0x07
++#define UR_GET_CONFIG 0x08
++#define UR_SET_CONFIG 0x09
++#define UR_GET_INTERFACE 0x0a
++#define UR_SET_INTERFACE 0x0b
++#define UR_SYNCH_FRAME 0x0c
++#define WUR_SET_ENCRYPTION 0x0d
++#define WUR_GET_ENCRYPTION 0x0e
++#define WUR_SET_HANDSHAKE 0x0f
++#define WUR_GET_HANDSHAKE 0x10
++#define WUR_SET_CONNECTION 0x11
++#define WUR_SET_SECURITY_DATA 0x12
++#define WUR_GET_SECURITY_DATA 0x13
++#define WUR_SET_WUSB_DATA 0x14
++#define WUDATA_DRPIE_INFO 0x01
++#define WUDATA_TRANSMIT_DATA 0x02
++#define WUDATA_TRANSMIT_PARAMS 0x03
++#define WUDATA_RECEIVE_PARAMS 0x04
++#define WUDATA_TRANSMIT_POWER 0x05
++#define WUR_LOOPBACK_DATA_WRITE 0x15
++#define WUR_LOOPBACK_DATA_READ 0x16
++#define WUR_SET_INTERFACE_DS 0x17
++
++/* Feature numbers */
++#define UF_ENDPOINT_HALT 0
++#define UF_DEVICE_REMOTE_WAKEUP 1
++#define UF_TEST_MODE 2
++#define UF_DEVICE_B_HNP_ENABLE 3
++#define UF_DEVICE_A_HNP_SUPPORT 4
++#define UF_DEVICE_A_ALT_HNP_SUPPORT 5
++#define WUF_WUSB 3
++#define WUF_TX_DRPIE 0x0
++#define WUF_DEV_XMIT_PACKET 0x1
++#define WUF_COUNT_PACKETS 0x2
++#define WUF_CAPTURE_PACKETS 0x3
++#define UF_FUNCTION_SUSPEND 0
++#define UF_U1_ENABLE 48
++#define UF_U2_ENABLE 49
++#define UF_LTM_ENABLE 50
++
++/* Class requests from the USB 2.0 hub spec, table 11-15 */
++#define UCR_CLEAR_HUB_FEATURE (0x2000 | UR_CLEAR_FEATURE)
++#define UCR_CLEAR_PORT_FEATURE (0x2300 | UR_CLEAR_FEATURE)
++#define UCR_GET_HUB_DESCRIPTOR (0xa000 | UR_GET_DESCRIPTOR)
++#define UCR_GET_HUB_STATUS (0xa000 | UR_GET_STATUS)
++#define UCR_GET_PORT_STATUS (0xa300 | UR_GET_STATUS)
++#define UCR_SET_HUB_FEATURE (0x2000 | UR_SET_FEATURE)
++#define UCR_SET_PORT_FEATURE (0x2300 | UR_SET_FEATURE)
++#define UCR_SET_AND_TEST_PORT_FEATURE (0xa300 | UR_SET_AND_TEST_FEATURE)
++
++#ifdef _MSC_VER
++#include <pshpack1.h>
++#endif
++
++typedef struct {
++ uByte bLength;
++ uByte bDescriptorType;
++ uByte bDescriptorSubtype;
++} UPACKED usb_descriptor_t;
++
++typedef struct {
++ uByte bLength;
++ uByte bDescriptorType;
++} UPACKED usb_descriptor_header_t;
++
++typedef struct {
++ uByte bLength;
++ uByte bDescriptorType;
++ uWord bcdUSB;
++#define UD_USB_2_0 0x0200
++#define UD_IS_USB2(d) (UGETW((d)->bcdUSB) >= UD_USB_2_0)
++ uByte bDeviceClass;
++ uByte bDeviceSubClass;
++ uByte bDeviceProtocol;
++ uByte bMaxPacketSize;
++ /* The fields below are not part of the initial descriptor. */
++ uWord idVendor;
++ uWord idProduct;
++ uWord bcdDevice;
++ uByte iManufacturer;
++ uByte iProduct;
++ uByte iSerialNumber;
++ uByte bNumConfigurations;
++} UPACKED usb_device_descriptor_t;
++#define USB_DEVICE_DESCRIPTOR_SIZE 18
++
++typedef struct {
++ uByte bLength;
++ uByte bDescriptorType;
++ uWord wTotalLength;
++ uByte bNumInterface;
++ uByte bConfigurationValue;
++ uByte iConfiguration;
++#define UC_ATT_ONE (1 << 7) /* must be set */
++#define UC_ATT_SELFPOWER (1 << 6) /* self powered */
++#define UC_ATT_WAKEUP (1 << 5) /* can wakeup */
++#define UC_ATT_BATTERY (1 << 4) /* battery powered */
++ uByte bmAttributes;
++#define UC_BUS_POWERED 0x80
++#define UC_SELF_POWERED 0x40
++#define UC_REMOTE_WAKEUP 0x20
++ uByte bMaxPower; /* max current in 2 mA units */
++#define UC_POWER_FACTOR 2
++} UPACKED usb_config_descriptor_t;
++#define USB_CONFIG_DESCRIPTOR_SIZE 9
++
++typedef struct {
++ uByte bLength;
++ uByte bDescriptorType;
++ uByte bInterfaceNumber;
++ uByte bAlternateSetting;
++ uByte bNumEndpoints;
++ uByte bInterfaceClass;
++ uByte bInterfaceSubClass;
++ uByte bInterfaceProtocol;
++ uByte iInterface;
++} UPACKED usb_interface_descriptor_t;
++#define USB_INTERFACE_DESCRIPTOR_SIZE 9
++
++typedef struct {
++ uByte bLength;
++ uByte bDescriptorType;
++ uByte bEndpointAddress;
++#define UE_GET_DIR(a) ((a) & 0x80)
++#define UE_SET_DIR(a,d) ((a) | (((d)&1) << 7))
++#define UE_DIR_IN 0x80
++#define UE_DIR_OUT 0x00
++#define UE_ADDR 0x0f
++#define UE_GET_ADDR(a) ((a) & UE_ADDR)
++ uByte bmAttributes;
++#define UE_XFERTYPE 0x03
++#define UE_CONTROL 0x00
++#define UE_ISOCHRONOUS 0x01
++#define UE_BULK 0x02
++#define UE_INTERRUPT 0x03
++#define UE_GET_XFERTYPE(a) ((a) & UE_XFERTYPE)
++#define UE_ISO_TYPE 0x0c
++#define UE_ISO_ASYNC 0x04
++#define UE_ISO_ADAPT 0x08
++#define UE_ISO_SYNC 0x0c
++#define UE_GET_ISO_TYPE(a) ((a) & UE_ISO_TYPE)
++ uWord wMaxPacketSize;
++ uByte bInterval;
++} UPACKED usb_endpoint_descriptor_t;
++#define USB_ENDPOINT_DESCRIPTOR_SIZE 7
++
++typedef struct ss_endpoint_companion_descriptor {
++ uByte bLength;
++ uByte bDescriptorType;
++ uByte bMaxBurst;
++#define USSE_GET_MAX_STREAMS(a) ((a) & 0x1f)
++#define USSE_SET_MAX_STREAMS(a, b) ((a) | ((b) & 0x1f))
++#define USSE_GET_MAX_PACKET_NUM(a) ((a) & 0x03)
++#define USSE_SET_MAX_PACKET_NUM(a, b) ((a) | ((b) & 0x03))
++ uByte bmAttributes;
++ uWord wBytesPerInterval;
++} UPACKED ss_endpoint_companion_descriptor_t;
++#define USB_SS_ENDPOINT_COMPANION_DESCRIPTOR_SIZE 6
++
++typedef struct {
++ uByte bLength;
++ uByte bDescriptorType;
++ uWord bString[127];
++} UPACKED usb_string_descriptor_t;
++#define USB_MAX_STRING_LEN 128
++#define USB_LANGUAGE_TABLE 0 /* # of the string language id table */
++
++/* Hub specific request */
++#define UR_GET_BUS_STATE 0x02
++#define UR_CLEAR_TT_BUFFER 0x08
++#define UR_RESET_TT 0x09
++#define UR_GET_TT_STATE 0x0a
++#define UR_STOP_TT 0x0b
++
++/* Hub features */
++#define UHF_C_HUB_LOCAL_POWER 0
++#define UHF_C_HUB_OVER_CURRENT 1
++#define UHF_PORT_CONNECTION 0
++#define UHF_PORT_ENABLE 1
++#define UHF_PORT_SUSPEND 2
++#define UHF_PORT_OVER_CURRENT 3
++#define UHF_PORT_RESET 4
++#define UHF_PORT_L1 5
++#define UHF_PORT_POWER 8
++#define UHF_PORT_LOW_SPEED 9
++#define UHF_PORT_HIGH_SPEED 10
++#define UHF_C_PORT_CONNECTION 16
++#define UHF_C_PORT_ENABLE 17
++#define UHF_C_PORT_SUSPEND 18
++#define UHF_C_PORT_OVER_CURRENT 19
++#define UHF_C_PORT_RESET 20
++#define UHF_C_PORT_L1 23
++#define UHF_PORT_TEST 21
++#define UHF_PORT_INDICATOR 22
++
++typedef struct {
++ uByte bDescLength;
++ uByte bDescriptorType;
++ uByte bNbrPorts;
++ uWord wHubCharacteristics;
++#define UHD_PWR 0x0003
++#define UHD_PWR_GANGED 0x0000
++#define UHD_PWR_INDIVIDUAL 0x0001
++#define UHD_PWR_NO_SWITCH 0x0002
++#define UHD_COMPOUND 0x0004
++#define UHD_OC 0x0018
++#define UHD_OC_GLOBAL 0x0000
++#define UHD_OC_INDIVIDUAL 0x0008
++#define UHD_OC_NONE 0x0010
++#define UHD_TT_THINK 0x0060
++#define UHD_TT_THINK_8 0x0000
++#define UHD_TT_THINK_16 0x0020
++#define UHD_TT_THINK_24 0x0040
++#define UHD_TT_THINK_32 0x0060
++#define UHD_PORT_IND 0x0080
++ uByte bPwrOn2PwrGood; /* delay in 2 ms units */
++#define UHD_PWRON_FACTOR 2
++ uByte bHubContrCurrent;
++ uByte DeviceRemovable[32]; /* max 255 ports */
++#define UHD_NOT_REMOV(desc, i) \
++ (((desc)->DeviceRemovable[(i)/8] >> ((i) % 8)) & 1)
++ /* deprecated */ uByte PortPowerCtrlMask[1];
++} UPACKED usb_hub_descriptor_t;
++#define USB_HUB_DESCRIPTOR_SIZE 9 /* includes deprecated PortPowerCtrlMask */
++
++typedef struct {
++ uByte bLength;
++ uByte bDescriptorType;
++ uWord bcdUSB;
++ uByte bDeviceClass;
++ uByte bDeviceSubClass;
++ uByte bDeviceProtocol;
++ uByte bMaxPacketSize0;
++ uByte bNumConfigurations;
++ uByte bReserved;
++} UPACKED usb_device_qualifier_t;
++#define USB_DEVICE_QUALIFIER_SIZE 10
++
++typedef struct {
++ uByte bLength;
++ uByte bDescriptorType;
++ uByte bmAttributes;
++#define UOTG_SRP 0x01
++#define UOTG_HNP 0x02
++} UPACKED usb_otg_descriptor_t;
++
++/* OTG feature selectors */
++#define UOTG_B_HNP_ENABLE 3
++#define UOTG_A_HNP_SUPPORT 4
++#define UOTG_A_ALT_HNP_SUPPORT 5
++
++typedef struct {
++ uWord wStatus;
++/* Device status flags */
++#define UDS_SELF_POWERED 0x0001
++#define UDS_REMOTE_WAKEUP 0x0002
++/* Endpoint status flags */
++#define UES_HALT 0x0001
++} UPACKED usb_status_t;
++
++typedef struct {
++ uWord wHubStatus;
++#define UHS_LOCAL_POWER 0x0001
++#define UHS_OVER_CURRENT 0x0002
++ uWord wHubChange;
++} UPACKED usb_hub_status_t;
++
++typedef struct {
++ uWord wPortStatus;
++#define UPS_CURRENT_CONNECT_STATUS 0x0001
++#define UPS_PORT_ENABLED 0x0002
++#define UPS_SUSPEND 0x0004
++#define UPS_OVERCURRENT_INDICATOR 0x0008
++#define UPS_RESET 0x0010
++#define UPS_PORT_POWER 0x0100
++#define UPS_LOW_SPEED 0x0200
++#define UPS_HIGH_SPEED 0x0400
++#define UPS_PORT_TEST 0x0800
++#define UPS_PORT_INDICATOR 0x1000
++ uWord wPortChange;
++#define UPS_C_CONNECT_STATUS 0x0001
++#define UPS_C_PORT_ENABLED 0x0002
++#define UPS_C_SUSPEND 0x0004
++#define UPS_C_OVERCURRENT_INDICATOR 0x0008
++#define UPS_C_PORT_RESET 0x0010
++} UPACKED usb_port_status_t;
++
++#ifdef _MSC_VER
++#include <poppack.h>
++#endif
++
++/* Device class codes */
++#define UDCLASS_IN_INTERFACE 0x00
++#define UDCLASS_COMM 0x02
++#define UDCLASS_HUB 0x09
++#define UDSUBCLASS_HUB 0x00
++#define UDPROTO_FSHUB 0x00
++#define UDPROTO_HSHUBSTT 0x01
++#define UDPROTO_HSHUBMTT 0x02
++#define UDCLASS_DIAGNOSTIC 0xdc
++#define UDCLASS_WIRELESS 0xe0
++#define UDSUBCLASS_RF 0x01
++#define UDPROTO_BLUETOOTH 0x01
++#define UDCLASS_VENDOR 0xff
++
++/* Interface class codes */
++#define UICLASS_UNSPEC 0x00
++
++#define UICLASS_AUDIO 0x01
++#define UISUBCLASS_AUDIOCONTROL 1
++#define UISUBCLASS_AUDIOSTREAM 2
++#define UISUBCLASS_MIDISTREAM 3
++
++#define UICLASS_CDC 0x02 /* communication */
++#define UISUBCLASS_DIRECT_LINE_CONTROL_MODEL 1
++#define UISUBCLASS_ABSTRACT_CONTROL_MODEL 2
++#define UISUBCLASS_TELEPHONE_CONTROL_MODEL 3
++#define UISUBCLASS_MULTICHANNEL_CONTROL_MODEL 4
++#define UISUBCLASS_CAPI_CONTROLMODEL 5
++#define UISUBCLASS_ETHERNET_NETWORKING_CONTROL_MODEL 6
++#define UISUBCLASS_ATM_NETWORKING_CONTROL_MODEL 7
++#define UIPROTO_CDC_AT 1
++
++#define UICLASS_HID 0x03
++#define UISUBCLASS_BOOT 1
++#define UIPROTO_BOOT_KEYBOARD 1
++
++#define UICLASS_PHYSICAL 0x05
++
++#define UICLASS_IMAGE 0x06
++
++#define UICLASS_PRINTER 0x07
++#define UISUBCLASS_PRINTER 1
++#define UIPROTO_PRINTER_UNI 1
++#define UIPROTO_PRINTER_BI 2
++#define UIPROTO_PRINTER_1284 3
++
++#define UICLASS_MASS 0x08
++#define UISUBCLASS_RBC 1
++#define UISUBCLASS_SFF8020I 2
++#define UISUBCLASS_QIC157 3
++#define UISUBCLASS_UFI 4
++#define UISUBCLASS_SFF8070I 5
++#define UISUBCLASS_SCSI 6
++#define UIPROTO_MASS_CBI_I 0
++#define UIPROTO_MASS_CBI 1
++#define UIPROTO_MASS_BBB_OLD 2 /* Not in the spec anymore */
++#define UIPROTO_MASS_BBB 80 /* 'P' for the Iomega Zip drive */
++
++#define UICLASS_HUB 0x09
++#define UISUBCLASS_HUB 0
++#define UIPROTO_FSHUB 0
++#define UIPROTO_HSHUBSTT 0 /* Yes, same as previous */
++#define UIPROTO_HSHUBMTT 1
++
++#define UICLASS_CDC_DATA 0x0a
++#define UISUBCLASS_DATA 0
++#define UIPROTO_DATA_ISDNBRI 0x30 /* Physical iface */
++#define UIPROTO_DATA_HDLC 0x31 /* HDLC */
++#define UIPROTO_DATA_TRANSPARENT 0x32 /* Transparent */
++#define UIPROTO_DATA_Q921M 0x50 /* Management for Q921 */
++#define UIPROTO_DATA_Q921 0x51 /* Data for Q921 */
++#define UIPROTO_DATA_Q921TM 0x52 /* TEI multiplexer for Q921 */
++#define UIPROTO_DATA_V42BIS 0x90 /* Data compression */
++#define UIPROTO_DATA_Q931 0x91 /* Euro-ISDN */
++#define UIPROTO_DATA_V120 0x92 /* V.24 rate adaption */
++#define UIPROTO_DATA_CAPI 0x93 /* CAPI 2.0 commands */
++#define UIPROTO_DATA_HOST_BASED 0xfd /* Host based driver */
++#define UIPROTO_DATA_PUF 0xfe /* see Prot. Unit Func. Desc.*/
++#define UIPROTO_DATA_VENDOR 0xff /* Vendor specific */
++
++#define UICLASS_SMARTCARD 0x0b
++
++/*#define UICLASS_FIRM_UPD 0x0c*/
++
++#define UICLASS_SECURITY 0x0d
++
++#define UICLASS_DIAGNOSTIC 0xdc
++
++#define UICLASS_WIRELESS 0xe0
++#define UISUBCLASS_RF 0x01
++#define UIPROTO_BLUETOOTH 0x01
++
++#define UICLASS_APPL_SPEC 0xfe
++#define UISUBCLASS_FIRMWARE_DOWNLOAD 1
++#define UISUBCLASS_IRDA 2
++#define UIPROTO_IRDA 0
++
++#define UICLASS_VENDOR 0xff
++
++#define USB_HUB_MAX_DEPTH 5
++
++/*
++ * Minimum time a device needs to be powered down to go through
++ * a power cycle. XXX Are these time in the spec?
++ */
++#define USB_POWER_DOWN_TIME 200 /* ms */
++#define USB_PORT_POWER_DOWN_TIME 100 /* ms */
++
++#if 0
++/* These are the values from the spec. */
++#define USB_PORT_RESET_DELAY 10 /* ms */
++#define USB_PORT_ROOT_RESET_DELAY 50 /* ms */
++#define USB_PORT_RESET_RECOVERY 10 /* ms */
++#define USB_PORT_POWERUP_DELAY 100 /* ms */
++#define USB_SET_ADDRESS_SETTLE 2 /* ms */
++#define USB_RESUME_DELAY (20*5) /* ms */
++#define USB_RESUME_WAIT 10 /* ms */
++#define USB_RESUME_RECOVERY 10 /* ms */
++#define USB_EXTRA_POWER_UP_TIME 0 /* ms */
++#else
++/* Allow for marginal (i.e. non-conforming) devices. */
++#define USB_PORT_RESET_DELAY 50 /* ms */
++#define USB_PORT_ROOT_RESET_DELAY 250 /* ms */
++#define USB_PORT_RESET_RECOVERY 250 /* ms */
++#define USB_PORT_POWERUP_DELAY 300 /* ms */
++#define USB_SET_ADDRESS_SETTLE 10 /* ms */
++#define USB_RESUME_DELAY (50*5) /* ms */
++#define USB_RESUME_WAIT 50 /* ms */
++#define USB_RESUME_RECOVERY 50 /* ms */
++#define USB_EXTRA_POWER_UP_TIME 20 /* ms */
++#endif
++
++#define USB_MIN_POWER 100 /* mA */
++#define USB_MAX_POWER 500 /* mA */
++
++#define USB_BUS_RESET_DELAY 100 /* ms XXX?*/
++
++#define USB_UNCONFIG_NO 0
++#define USB_UNCONFIG_INDEX (-1)
++
++/*** ioctl() related stuff ***/
++
++struct usb_ctl_request {
++ int ucr_addr;
++ usb_device_request_t ucr_request;
++ void *ucr_data;
++ int ucr_flags;
++#define USBD_SHORT_XFER_OK 0x04 /* allow short reads */
++ int ucr_actlen; /* actual length transferred */
++};
++
++struct usb_alt_interface {
++ int uai_config_index;
++ int uai_interface_index;
++ int uai_alt_no;
++};
++
++#define USB_CURRENT_CONFIG_INDEX (-1)
++#define USB_CURRENT_ALT_INDEX (-1)
++
++struct usb_config_desc {
++ int ucd_config_index;
++ usb_config_descriptor_t ucd_desc;
++};
++
++struct usb_interface_desc {
++ int uid_config_index;
++ int uid_interface_index;
++ int uid_alt_index;
++ usb_interface_descriptor_t uid_desc;
++};
++
++struct usb_endpoint_desc {
++ int ued_config_index;
++ int ued_interface_index;
++ int ued_alt_index;
++ int ued_endpoint_index;
++ usb_endpoint_descriptor_t ued_desc;
++};
++
++struct usb_full_desc {
++ int ufd_config_index;
++ u_int ufd_size;
++ u_char *ufd_data;
++};
++
++struct usb_string_desc {
++ int usd_string_index;
++ int usd_language_id;
++ usb_string_descriptor_t usd_desc;
++};
++
++struct usb_ctl_report_desc {
++ int ucrd_size;
++ u_char ucrd_data[1024]; /* filled data size will vary */
++};
++
++typedef struct { u_int32_t cookie; } usb_event_cookie_t;
++
++#define USB_MAX_DEVNAMES 4
++#define USB_MAX_DEVNAMELEN 16
++struct usb_device_info {
++ u_int8_t udi_bus;
++ u_int8_t udi_addr; /* device address */
++ usb_event_cookie_t udi_cookie;
++ char udi_product[USB_MAX_STRING_LEN];
++ char udi_vendor[USB_MAX_STRING_LEN];
++ char udi_release[8];
++ u_int16_t udi_productNo;
++ u_int16_t udi_vendorNo;
++ u_int16_t udi_releaseNo;
++ u_int8_t udi_class;
++ u_int8_t udi_subclass;
++ u_int8_t udi_protocol;
++ u_int8_t udi_config;
++ u_int8_t udi_speed;
++#define USB_SPEED_UNKNOWN 0
++#define USB_SPEED_LOW 1
++#define USB_SPEED_FULL 2
++#define USB_SPEED_HIGH 3
++#define USB_SPEED_VARIABLE 4
++#define USB_SPEED_SUPER 5
++ int udi_power; /* power consumption in mA, 0 if selfpowered */
++ int udi_nports;
++ char udi_devnames[USB_MAX_DEVNAMES][USB_MAX_DEVNAMELEN];
++ u_int8_t udi_ports[16];/* hub only: addresses of devices on ports */
++#define USB_PORT_ENABLED 0xff
++#define USB_PORT_SUSPENDED 0xfe
++#define USB_PORT_POWERED 0xfd
++#define USB_PORT_DISABLED 0xfc
++};
++
++struct usb_ctl_report {
++ int ucr_report;
++ u_char ucr_data[1024]; /* filled data size will vary */
++};
++
++struct usb_device_stats {
++ u_long uds_requests[4]; /* indexed by transfer type UE_* */
++};
++
++#define WUSB_MIN_IE 0x80
++#define WUSB_WCTA_IE 0x80
++#define WUSB_WCONNECTACK_IE 0x81
++#define WUSB_WHOSTINFO_IE 0x82
++#define WUHI_GET_CA(_bmAttributes_) ((_bmAttributes_) & 0x3)
++#define WUHI_CA_RECONN 0x00
++#define WUHI_CA_LIMITED 0x01
++#define WUHI_CA_ALL 0x03
++#define WUHI_GET_MLSI(_bmAttributes_) (((_bmAttributes_) & 0x38) >> 3)
++#define WUSB_WCHCHANGEANNOUNCE_IE 0x83
++#define WUSB_WDEV_DISCONNECT_IE 0x84
++#define WUSB_WHOST_DISCONNECT_IE 0x85
++#define WUSB_WRELEASE_CHANNEL_IE 0x86
++#define WUSB_WWORK_IE 0x87
++#define WUSB_WCHANNEL_STOP_IE 0x88
++#define WUSB_WDEV_KEEPALIVE_IE 0x89
++#define WUSB_WISOCH_DISCARD_IE 0x8A
++#define WUSB_WRESETDEVICE_IE 0x8B
++#define WUSB_WXMIT_PACKET_ADJUST_IE 0x8C
++#define WUSB_MAX_IE 0x8C
++
++/* Device Notification Types */
++
++#define WUSB_DN_MIN 0x01
++#define WUSB_DN_CONNECT 0x01
++# define WUSB_DA_OLDCONN 0x00
++# define WUSB_DA_NEWCONN 0x01
++# define WUSB_DA_SELF_BEACON 0x02
++# define WUSB_DA_DIR_BEACON 0x04
++# define WUSB_DA_NO_BEACON 0x06
++#define WUSB_DN_DISCONNECT 0x02
++#define WUSB_DN_EPRDY 0x03
++#define WUSB_DN_MASAVAILCHANGED 0x04
++#define WUSB_DN_REMOTEWAKEUP 0x05
++#define WUSB_DN_SLEEP 0x06
++#define WUSB_DN_ALIVE 0x07
++#define WUSB_DN_MAX 0x07
++
++#ifdef _MSC_VER
++#include <pshpack1.h>
++#endif
++
++/* WUSB Handshake Data. Used during the SET/GET HANDSHAKE requests */
++typedef struct wusb_hndshk_data {
++ uByte bMessageNumber;
++ uByte bStatus;
++ uByte tTKID[3];
++ uByte bReserved;
++ uByte CDID[16];
++ uByte Nonce[16];
++ uByte MIC[8];
++} UPACKED wusb_hndshk_data_t;
++#define WUSB_HANDSHAKE_LEN_FOR_MIC 38
++
++/* WUSB Connection Context */
++typedef struct wusb_conn_context {
++ uByte CHID [16];
++ uByte CDID [16];
++ uByte CK [16];
++} UPACKED wusb_conn_context_t;
++
++/* WUSB Security Descriptor */
++typedef struct wusb_security_desc {
++ uByte bLength;
++ uByte bDescriptorType;
++ uWord wTotalLength;
++ uByte bNumEncryptionTypes;
++} UPACKED wusb_security_desc_t;
++
++/* WUSB Encryption Type Descriptor */
++typedef struct wusb_encrypt_type_desc {
++ uByte bLength;
++ uByte bDescriptorType;
++
++ uByte bEncryptionType;
++#define WUETD_UNSECURE 0
++#define WUETD_WIRED 1
++#define WUETD_CCM_1 2
++#define WUETD_RSA_1 3
++
++ uByte bEncryptionValue;
++ uByte bAuthKeyIndex;
++} UPACKED wusb_encrypt_type_desc_t;
++
++/* WUSB Key Descriptor */
++typedef struct wusb_key_desc {
++ uByte bLength;
++ uByte bDescriptorType;
++ uByte tTKID[3];
++ uByte bReserved;
++ uByte KeyData[1]; /* variable length */
++} UPACKED wusb_key_desc_t;
++
++/* WUSB BOS Descriptor (Binary device Object Store) */
++typedef struct wusb_bos_desc {
++ uByte bLength;
++ uByte bDescriptorType;
++ uWord wTotalLength;
++ uByte bNumDeviceCaps;
++} UPACKED wusb_bos_desc_t;
++
++#define USB_DEVICE_CAPABILITY_20_EXTENSION 0x02
++typedef struct usb_dev_cap_20_ext_desc {
++ uByte bLength;
++ uByte bDescriptorType;
++ uByte bDevCapabilityType;
++#define USB_20_EXT_LPM 0x02
++ uDWord bmAttributes;
++} UPACKED usb_dev_cap_20_ext_desc_t;
++
++#define USB_DEVICE_CAPABILITY_SS_USB 0x03
++typedef struct usb_dev_cap_ss_usb {
++ uByte bLength;
++ uByte bDescriptorType;
++ uByte bDevCapabilityType;
++#define USB_DC_SS_USB_LTM_CAPABLE 0x02
++ uByte bmAttributes;
++#define USB_DC_SS_USB_SPEED_SUPPORT_LOW 0x01
++#define USB_DC_SS_USB_SPEED_SUPPORT_FULL 0x02
++#define USB_DC_SS_USB_SPEED_SUPPORT_HIGH 0x04
++#define USB_DC_SS_USB_SPEED_SUPPORT_SS 0x08
++ uWord wSpeedsSupported;
++ uByte bFunctionalitySupport;
++ uByte bU1DevExitLat;
++ uWord wU2DevExitLat;
++} UPACKED usb_dev_cap_ss_usb_t;
++
++#define USB_DEVICE_CAPABILITY_CONTAINER_ID 0x04
++typedef struct usb_dev_cap_container_id {
++ uByte bLength;
++ uByte bDescriptorType;
++ uByte bDevCapabilityType;
++ uByte bReserved;
++ uByte containerID[16];
++} UPACKED usb_dev_cap_container_id_t;
++
++/* Device Capability Type Codes */
++#define WUSB_DEVICE_CAPABILITY_WIRELESS_USB 0x01
++
++/* Device Capability Descriptor */
++typedef struct wusb_dev_cap_desc {
++ uByte bLength;
++ uByte bDescriptorType;
++ uByte bDevCapabilityType;
++ uByte caps[1]; /* Variable length */
++} UPACKED wusb_dev_cap_desc_t;
++
++/* Device Capability Descriptor */
++typedef struct wusb_dev_cap_uwb_desc {
++ uByte bLength;
++ uByte bDescriptorType;
++ uByte bDevCapabilityType;
++ uByte bmAttributes;
++ uWord wPHYRates; /* Bitmap */
++ uByte bmTFITXPowerInfo;
++ uByte bmFFITXPowerInfo;
++ uWord bmBandGroup;
++ uByte bReserved;
++} UPACKED wusb_dev_cap_uwb_desc_t;
++
++/* Wireless USB Endpoint Companion Descriptor */
++typedef struct wusb_endpoint_companion_desc {
++ uByte bLength;
++ uByte bDescriptorType;
++ uByte bMaxBurst;
++ uByte bMaxSequence;
++ uWord wMaxStreamDelay;
++ uWord wOverTheAirPacketSize;
++ uByte bOverTheAirInterval;
++ uByte bmCompAttributes;
++} UPACKED wusb_endpoint_companion_desc_t;
++
++/* Wireless USB Numeric Association M1 Data Structure */
++typedef struct wusb_m1_data {
++ uByte version;
++ uWord langId;
++ uByte deviceFriendlyNameLength;
++ uByte sha_256_m3[32];
++ uByte deviceFriendlyName[256];
++} UPACKED wusb_m1_data_t;
++
++typedef struct wusb_m2_data {
++ uByte version;
++ uWord langId;
++ uByte hostFriendlyNameLength;
++ uByte pkh[384];
++ uByte hostFriendlyName[256];
++} UPACKED wusb_m2_data_t;
++
++typedef struct wusb_m3_data {
++ uByte pkd[384];
++ uByte nd;
++} UPACKED wusb_m3_data_t;
++
++typedef struct wusb_m4_data {
++ uDWord _attributeTypeIdAndLength_1;
++ uWord associationTypeId;
++
++ uDWord _attributeTypeIdAndLength_2;
++ uWord associationSubTypeId;
++
++ uDWord _attributeTypeIdAndLength_3;
++ uDWord length;
++
++ uDWord _attributeTypeIdAndLength_4;
++ uDWord associationStatus;
++
++ uDWord _attributeTypeIdAndLength_5;
++ uByte chid[16];
++
++ uDWord _attributeTypeIdAndLength_6;
++ uByte cdid[16];
++
++ uDWord _attributeTypeIdAndLength_7;
++ uByte bandGroups[2];
++} UPACKED wusb_m4_data_t;
++
++#ifdef _MSC_VER
++#include <poppack.h>
++#endif
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* _USB_H_ */
+diff -Nur linux-4.1.3/drivers/usb/host/dwc_otg/doc/doxygen.cfg linux-xbian-rpi/drivers/usb/host/dwc_otg/doc/doxygen.cfg
+--- linux-4.1.3/drivers/usb/host/dwc_otg/doc/doxygen.cfg 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/usb/host/dwc_otg/doc/doxygen.cfg 2015-07-28 01:20:58.445156473 +0200
+@@ -0,0 +1,224 @@
++# Doxyfile 1.3.9.1
++
++#---------------------------------------------------------------------------
++# Project related configuration options
++#---------------------------------------------------------------------------
++PROJECT_NAME = "DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver"
++PROJECT_NUMBER = v3.00a
++OUTPUT_DIRECTORY = ./doc/
++CREATE_SUBDIRS = NO
++OUTPUT_LANGUAGE = English
++BRIEF_MEMBER_DESC = YES
++REPEAT_BRIEF = YES
++ABBREVIATE_BRIEF = "The $name class" \
++ "The $name widget" \
++ "The $name file" \
++ is \
++ provides \
++ specifies \
++ contains \
++ represents \
++ a \
++ an \
++ the
++ALWAYS_DETAILED_SEC = NO
++INLINE_INHERITED_MEMB = NO
++FULL_PATH_NAMES = NO
++STRIP_FROM_PATH =
++STRIP_FROM_INC_PATH =
++SHORT_NAMES = NO
++JAVADOC_AUTOBRIEF = YES
++MULTILINE_CPP_IS_BRIEF = NO
++INHERIT_DOCS = YES
++DISTRIBUTE_GROUP_DOC = NO
++TAB_SIZE = 8
++ALIASES =
++OPTIMIZE_OUTPUT_FOR_C = YES
++OPTIMIZE_OUTPUT_JAVA = NO
++SUBGROUPING = YES
++#---------------------------------------------------------------------------
++# Build related configuration options
++#---------------------------------------------------------------------------
++EXTRACT_ALL = NO
++EXTRACT_PRIVATE = YES
++EXTRACT_STATIC = YES
++EXTRACT_LOCAL_CLASSES = YES
++EXTRACT_LOCAL_METHODS = NO
++HIDE_UNDOC_MEMBERS = NO
++HIDE_UNDOC_CLASSES = NO
++HIDE_FRIEND_COMPOUNDS = NO
++HIDE_IN_BODY_DOCS = NO
++INTERNAL_DOCS = NO
++CASE_SENSE_NAMES = NO
++HIDE_SCOPE_NAMES = NO
++SHOW_INCLUDE_FILES = YES
++INLINE_INFO = YES
++SORT_MEMBER_DOCS = NO
++SORT_BRIEF_DOCS = NO
++SORT_BY_SCOPE_NAME = NO
++GENERATE_TODOLIST = YES
++GENERATE_TESTLIST = YES
++GENERATE_BUGLIST = YES
++GENERATE_DEPRECATEDLIST= YES
++ENABLED_SECTIONS =
++MAX_INITIALIZER_LINES = 30
++SHOW_USED_FILES = YES
++SHOW_DIRECTORIES = YES
++#---------------------------------------------------------------------------
++# configuration options related to warning and progress messages
++#---------------------------------------------------------------------------
++QUIET = YES
++WARNINGS = YES
++WARN_IF_UNDOCUMENTED = NO
++WARN_IF_DOC_ERROR = YES
++WARN_FORMAT = "$file:$line: $text"
++WARN_LOGFILE =
++#---------------------------------------------------------------------------
++# configuration options related to the input files
++#---------------------------------------------------------------------------
++INPUT = .
++FILE_PATTERNS = *.c \
++ *.h \
++ ./linux/*.c \
++ ./linux/*.h
++RECURSIVE = NO
++EXCLUDE = ./test/ \
++ ./dwc_otg/.AppleDouble/
++EXCLUDE_SYMLINKS = YES
++EXCLUDE_PATTERNS = *.mod.*
++EXAMPLE_PATH =
++EXAMPLE_PATTERNS = *
++EXAMPLE_RECURSIVE = NO
++IMAGE_PATH =
++INPUT_FILTER =
++FILTER_PATTERNS =
++FILTER_SOURCE_FILES = NO
++#---------------------------------------------------------------------------
++# configuration options related to source browsing
++#---------------------------------------------------------------------------
++SOURCE_BROWSER = YES
++INLINE_SOURCES = NO
++STRIP_CODE_COMMENTS = YES
++REFERENCED_BY_RELATION = NO
++REFERENCES_RELATION = NO
++VERBATIM_HEADERS = NO
++#---------------------------------------------------------------------------
++# configuration options related to the alphabetical class index
++#---------------------------------------------------------------------------
++ALPHABETICAL_INDEX = NO
++COLS_IN_ALPHA_INDEX = 5
++IGNORE_PREFIX =
++#---------------------------------------------------------------------------
++# configuration options related to the HTML output
++#---------------------------------------------------------------------------
++GENERATE_HTML = YES
++HTML_OUTPUT = html
++HTML_FILE_EXTENSION = .html
++HTML_HEADER =
++HTML_FOOTER =
++HTML_STYLESHEET =
++HTML_ALIGN_MEMBERS = YES
++GENERATE_HTMLHELP = NO
++CHM_FILE =
++HHC_LOCATION =
++GENERATE_CHI = NO
++BINARY_TOC = NO
++TOC_EXPAND = NO
++DISABLE_INDEX = NO
++ENUM_VALUES_PER_LINE = 4
++GENERATE_TREEVIEW = YES
++TREEVIEW_WIDTH = 250
++#---------------------------------------------------------------------------
++# configuration options related to the LaTeX output
++#---------------------------------------------------------------------------
++GENERATE_LATEX = NO
++LATEX_OUTPUT = latex
++LATEX_CMD_NAME = latex
++MAKEINDEX_CMD_NAME = makeindex
++COMPACT_LATEX = NO
++PAPER_TYPE = a4wide
++EXTRA_PACKAGES =
++LATEX_HEADER =
++PDF_HYPERLINKS = NO
++USE_PDFLATEX = NO
++LATEX_BATCHMODE = NO
++LATEX_HIDE_INDICES = NO
++#---------------------------------------------------------------------------
++# configuration options related to the RTF output
++#---------------------------------------------------------------------------
++GENERATE_RTF = NO
++RTF_OUTPUT = rtf
++COMPACT_RTF = NO
++RTF_HYPERLINKS = NO
++RTF_STYLESHEET_FILE =
++RTF_EXTENSIONS_FILE =
++#---------------------------------------------------------------------------
++# configuration options related to the man page output
++#---------------------------------------------------------------------------
++GENERATE_MAN = NO
++MAN_OUTPUT = man
++MAN_EXTENSION = .3
++MAN_LINKS = NO
++#---------------------------------------------------------------------------
++# configuration options related to the XML output
++#---------------------------------------------------------------------------
++GENERATE_XML = NO
++XML_OUTPUT = xml
++XML_SCHEMA =
++XML_DTD =
++XML_PROGRAMLISTING = YES
++#---------------------------------------------------------------------------
++# configuration options for the AutoGen Definitions output
++#---------------------------------------------------------------------------
++GENERATE_AUTOGEN_DEF = NO
++#---------------------------------------------------------------------------
++# configuration options related to the Perl module output
++#---------------------------------------------------------------------------
++GENERATE_PERLMOD = NO
++PERLMOD_LATEX = NO
++PERLMOD_PRETTY = YES
++PERLMOD_MAKEVAR_PREFIX =
++#---------------------------------------------------------------------------
++# Configuration options related to the preprocessor
++#---------------------------------------------------------------------------
++ENABLE_PREPROCESSING = YES
++MACRO_EXPANSION = YES
++EXPAND_ONLY_PREDEF = YES
++SEARCH_INCLUDES = YES
++INCLUDE_PATH =
++INCLUDE_FILE_PATTERNS =
++PREDEFINED = DEVICE_ATTR DWC_EN_ISOC
++EXPAND_AS_DEFINED = DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW DWC_OTG_DEVICE_ATTR_BITFIELD_STORE DWC_OTG_DEVICE_ATTR_BITFIELD_RW DWC_OTG_DEVICE_ATTR_BITFIELD_RO DWC_OTG_DEVICE_ATTR_REG_SHOW DWC_OTG_DEVICE_ATTR_REG_STORE DWC_OTG_DEVICE_ATTR_REG32_RW DWC_OTG_DEVICE_ATTR_REG32_RO DWC_EN_ISOC
++SKIP_FUNCTION_MACROS = NO
++#---------------------------------------------------------------------------
++# Configuration::additions related to external references
++#---------------------------------------------------------------------------
++TAGFILES =
++GENERATE_TAGFILE =
++ALLEXTERNALS = NO
++EXTERNAL_GROUPS = YES
++PERL_PATH = /usr/bin/perl
++#---------------------------------------------------------------------------
++# Configuration options related to the dot tool
++#---------------------------------------------------------------------------
++CLASS_DIAGRAMS = YES
++HIDE_UNDOC_RELATIONS = YES
++HAVE_DOT = NO
++CLASS_GRAPH = YES
++COLLABORATION_GRAPH = YES
++UML_LOOK = NO
++TEMPLATE_RELATIONS = NO
++INCLUDE_GRAPH = YES
++INCLUDED_BY_GRAPH = YES
++CALL_GRAPH = NO
++GRAPHICAL_HIERARCHY = YES
++DOT_IMAGE_FORMAT = png
++DOT_PATH =
++DOTFILE_DIRS =
++MAX_DOT_GRAPH_DEPTH = 1000
++GENERATE_LEGEND = YES
++DOT_CLEANUP = YES
++#---------------------------------------------------------------------------
++# Configuration::additions related to the search engine
++#---------------------------------------------------------------------------
++SEARCHENGINE = NO
+diff -Nur linux-4.1.3/drivers/usb/host/dwc_otg/dummy_audio.c linux-xbian-rpi/drivers/usb/host/dwc_otg/dummy_audio.c
+--- linux-4.1.3/drivers/usb/host/dwc_otg/dummy_audio.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/usb/host/dwc_otg/dummy_audio.c 2015-07-28 01:20:58.445156473 +0200
+@@ -0,0 +1,1575 @@
++/*
++ * zero.c -- Gadget Zero, for USB development
++ *
++ * Copyright (C) 2003-2004 David Brownell
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ * 1. Redistributions of source code must retain the above copyright
++ * notice, this list of conditions, and the following disclaimer,
++ * without modification.
++ * 2. Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * 3. The names of the above-listed copyright holders may not be used
++ * to endorse or promote products derived from this software without
++ * specific prior written permission.
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++
++/*
++ * Gadget Zero only needs two bulk endpoints, and is an example of how you
++ * can write a hardware-agnostic gadget driver running inside a USB device.
++ *
++ * Hardware details are visible (see CONFIG_USB_ZERO_* below) but don't
++ * affect most of the driver.
++ *
++ * Use it with the Linux host/master side "usbtest" driver to get a basic
++ * functional test of your device-side usb stack, or with "usb-skeleton".
++ *
++ * It supports two similar configurations. One sinks whatever the usb host
++ * writes, and in return sources zeroes. The other loops whatever the host
++ * writes back, so the host can read it. Module options include:
++ *
++ * buflen=N default N=4096, buffer size used
++ * qlen=N default N=32, how many buffers in the loopback queue
++ * loopdefault default false, list loopback config first
++ *
++ * Many drivers will only have one configuration, letting them be much
++ * simpler if they also don't support high speed operation (like this
++ * driver does).
++ */
++
++#include <linux/config.h>
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/delay.h>
++#include <linux/ioport.h>
++#include <linux/sched.h>
++#include <linux/slab.h>
++#include <linux/smp_lock.h>
++#include <linux/errno.h>
++#include <linux/init.h>
++#include <linux/timer.h>
++#include <linux/list.h>
++#include <linux/interrupt.h>
++#include <linux/uts.h>
++#include <linux/version.h>
++#include <linux/device.h>
++#include <linux/moduleparam.h>
++#include <linux/proc_fs.h>
++
++#include <asm/byteorder.h>
++#include <asm/io.h>
++#include <asm/irq.h>
++#include <asm/system.h>
++#include <asm/unaligned.h>
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21)
++# include <linux/usb/ch9.h>
++#else
++# include <linux/usb_ch9.h>
++#endif
++
++#include <linux/usb_gadget.h>
++
++
++/*-------------------------------------------------------------------------*/
++/*-------------------------------------------------------------------------*/
++
++
++static int utf8_to_utf16le(const char *s, u16 *cp, unsigned len)
++{
++ int count = 0;
++ u8 c;
++ u16 uchar;
++
++ /* this insists on correct encodings, though not minimal ones.
++ * BUT it currently rejects legit 4-byte UTF-8 code points,
++ * which need surrogate pairs. (Unicode 3.1 can use them.)
++ */
++ while (len != 0 && (c = (u8) *s++) != 0) {
++ if (unlikely(c & 0x80)) {
++ // 2-byte sequence:
++ // 00000yyyyyxxxxxx = 110yyyyy 10xxxxxx
++ if ((c & 0xe0) == 0xc0) {
++ uchar = (c & 0x1f) << 6;
++
++ c = (u8) *s++;
++ if ((c & 0xc0) != 0xc0)
++ goto fail;
++ c &= 0x3f;
++ uchar |= c;
++
++ // 3-byte sequence (most CJKV characters):
++ // zzzzyyyyyyxxxxxx = 1110zzzz 10yyyyyy 10xxxxxx
++ } else if ((c & 0xf0) == 0xe0) {
++ uchar = (c & 0x0f) << 12;
++
++ c = (u8) *s++;
++ if ((c & 0xc0) != 0xc0)
++ goto fail;
++ c &= 0x3f;
++ uchar |= c << 6;
++
++ c = (u8) *s++;
++ if ((c & 0xc0) != 0xc0)
++ goto fail;
++ c &= 0x3f;
++ uchar |= c;
++
++ /* no bogus surrogates */
++ if (0xd800 <= uchar && uchar <= 0xdfff)
++ goto fail;
++
++ // 4-byte sequence (surrogate pairs, currently rare):
++ // 11101110wwwwzzzzyy + 110111yyyyxxxxxx
++ // = 11110uuu 10uuzzzz 10yyyyyy 10xxxxxx
++ // (uuuuu = wwww + 1)
++ // FIXME accept the surrogate code points (only)
++
++ } else
++ goto fail;
++ } else
++ uchar = c;
++ put_unaligned (cpu_to_le16 (uchar), cp++);
++ count++;
++ len--;
++ }
++ return count;
++fail:
++ return -1;
++}
++
++
++/**
++ * usb_gadget_get_string - fill out a string descriptor
++ * @table: of c strings encoded using UTF-8
++ * @id: string id, from low byte of wValue in get string descriptor
++ * @buf: at least 256 bytes
++ *
++ * Finds the UTF-8 string matching the ID, and converts it into a
++ * string descriptor in utf16-le.
++ * Returns length of descriptor (always even) or negative errno
++ *
++ * If your driver needs stings in multiple languages, you'll probably
++ * "switch (wIndex) { ... }" in your ep0 string descriptor logic,
++ * using this routine after choosing which set of UTF-8 strings to use.
++ * Note that US-ASCII is a strict subset of UTF-8; any string bytes with
++ * the eighth bit set will be multibyte UTF-8 characters, not ISO-8859/1
++ * characters (which are also widely used in C strings).
++ */
++int
++usb_gadget_get_string (struct usb_gadget_strings *table, int id, u8 *buf)
++{
++ struct usb_string *s;
++ int len;
++
++ /* descriptor 0 has the language id */
++ if (id == 0) {
++ buf [0] = 4;
++ buf [1] = USB_DT_STRING;
++ buf [2] = (u8) table->language;
++ buf [3] = (u8) (table->language >> 8);
++ return 4;
++ }
++ for (s = table->strings; s && s->s; s++)
++ if (s->id == id)
++ break;
++
++ /* unrecognized: stall. */
++ if (!s || !s->s)
++ return -EINVAL;
++
++ /* string descriptors have length, tag, then UTF16-LE text */
++ len = min ((size_t) 126, strlen (s->s));
++ memset (buf + 2, 0, 2 * len); /* zero all the bytes */
++ len = utf8_to_utf16le(s->s, (u16 *)&buf[2], len);
++ if (len < 0)
++ return -EINVAL;
++ buf [0] = (len + 1) * 2;
++ buf [1] = USB_DT_STRING;
++ return buf [0];
++}
++
++
++/*-------------------------------------------------------------------------*/
++/*-------------------------------------------------------------------------*/
++
++
++/**
++ * usb_descriptor_fillbuf - fill buffer with descriptors
++ * @buf: Buffer to be filled
++ * @buflen: Size of buf
++ * @src: Array of descriptor pointers, terminated by null pointer.
++ *
++ * Copies descriptors into the buffer, returning the length or a
++ * negative error code if they can't all be copied. Useful when
++ * assembling descriptors for an associated set of interfaces used
++ * as part of configuring a composite device; or in other cases where
++ * sets of descriptors need to be marshaled.
++ */
++int
++usb_descriptor_fillbuf(void *buf, unsigned buflen,
++ const struct usb_descriptor_header **src)
++{
++ u8 *dest = buf;
++
++ if (!src)
++ return -EINVAL;
++
++ /* fill buffer from src[] until null descriptor ptr */
++ for (; 0 != *src; src++) {
++ unsigned len = (*src)->bLength;
++
++ if (len > buflen)
++ return -EINVAL;
++ memcpy(dest, *src, len);
++ buflen -= len;
++ dest += len;
++ }
++ return dest - (u8 *)buf;
++}
++
++
++/**
++ * usb_gadget_config_buf - builts a complete configuration descriptor
++ * @config: Header for the descriptor, including characteristics such
++ * as power requirements and number of interfaces.
++ * @desc: Null-terminated vector of pointers to the descriptors (interface,
++ * endpoint, etc) defining all functions in this device configuration.
++ * @buf: Buffer for the resulting configuration descriptor.
++ * @length: Length of buffer. If this is not big enough to hold the
++ * entire configuration descriptor, an error code will be returned.
++ *
++ * This copies descriptors into the response buffer, building a descriptor
++ * for that configuration. It returns the buffer length or a negative
++ * status code. The config.wTotalLength field is set to match the length
++ * of the result, but other descriptor fields (including power usage and
++ * interface count) must be set by the caller.
++ *
++ * Gadget drivers could use this when constructing a config descriptor
++ * in response to USB_REQ_GET_DESCRIPTOR. They will need to patch the
++ * resulting bDescriptorType value if USB_DT_OTHER_SPEED_CONFIG is needed.
++ */
++int usb_gadget_config_buf(
++ const struct usb_config_descriptor *config,
++ void *buf,
++ unsigned length,
++ const struct usb_descriptor_header **desc
++)
++{
++ struct usb_config_descriptor *cp = buf;
++ int len;
++
++ /* config descriptor first */
++ if (length < USB_DT_CONFIG_SIZE || !desc)
++ return -EINVAL;
++ *cp = *config;
++
++ /* then interface/endpoint/class/vendor/... */
++ len = usb_descriptor_fillbuf(USB_DT_CONFIG_SIZE + (u8*)buf,
++ length - USB_DT_CONFIG_SIZE, desc);
++ if (len < 0)
++ return len;
++ len += USB_DT_CONFIG_SIZE;
++ if (len > 0xffff)
++ return -EINVAL;
++
++ /* patch up the config descriptor */
++ cp->bLength = USB_DT_CONFIG_SIZE;
++ cp->bDescriptorType = USB_DT_CONFIG;
++ cp->wTotalLength = cpu_to_le16(len);
++ cp->bmAttributes |= USB_CONFIG_ATT_ONE;
++ return len;
++}
++
++/*-------------------------------------------------------------------------*/
++/*-------------------------------------------------------------------------*/
++
++
++#define RBUF_LEN (1024*1024)
++static int rbuf_start;
++static int rbuf_len;
++static __u8 rbuf[RBUF_LEN];
++
++/*-------------------------------------------------------------------------*/
++
++#define DRIVER_VERSION "St Patrick's Day 2004"
++
++static const char shortname [] = "zero";
++static const char longname [] = "YAMAHA YST-MS35D USB Speaker ";
++
++static const char source_sink [] = "source and sink data";
++static const char loopback [] = "loop input to output";
++
++/*-------------------------------------------------------------------------*/
++
++/*
++ * driver assumes self-powered hardware, and
++ * has no way for users to trigger remote wakeup.
++ *
++ * this version autoconfigures as much as possible,
++ * which is reasonable for most "bulk-only" drivers.
++ */
++static const char *EP_IN_NAME; /* source */
++static const char *EP_OUT_NAME; /* sink */
++
++/*-------------------------------------------------------------------------*/
++
++/* big enough to hold our biggest descriptor */
++#define USB_BUFSIZ 512
++
++struct zero_dev {
++ spinlock_t lock;
++ struct usb_gadget *gadget;
++ struct usb_request *req; /* for control responses */
++
++ /* when configured, we have one of two configs:
++ * - source data (in to host) and sink it (out from host)
++ * - or loop it back (out from host back in to host)
++ */
++ u8 config;
++ struct usb_ep *in_ep, *out_ep;
++
++ /* autoresume timer */
++ struct timer_list resume;
++};
++
++#define xprintk(d,level,fmt,args...) \
++ dev_printk(level , &(d)->gadget->dev , fmt , ## args)
++
++#ifdef DEBUG
++#define DBG(dev,fmt,args...) \
++ xprintk(dev , KERN_DEBUG , fmt , ## args)
++#else
++#define DBG(dev,fmt,args...) \
++ do { } while (0)
++#endif /* DEBUG */
++
++#ifdef VERBOSE
++#define VDBG DBG
++#else
++#define VDBG(dev,fmt,args...) \
++ do { } while (0)
++#endif /* VERBOSE */
++
++#define ERROR(dev,fmt,args...) \
++ xprintk(dev , KERN_ERR , fmt , ## args)
++#define WARN(dev,fmt,args...) \
++ xprintk(dev , KERN_WARNING , fmt , ## args)
++#define INFO(dev,fmt,args...) \
++ xprintk(dev , KERN_INFO , fmt , ## args)
++
++/*-------------------------------------------------------------------------*/
++
++static unsigned buflen = 4096;
++static unsigned qlen = 32;
++static unsigned pattern = 0;
++
++module_param (buflen, uint, S_IRUGO|S_IWUSR);
++module_param (qlen, uint, S_IRUGO|S_IWUSR);
++module_param (pattern, uint, S_IRUGO|S_IWUSR);
++
++/*
++ * if it's nonzero, autoresume says how many seconds to wait
++ * before trying to wake up the host after suspend.
++ */
++static unsigned autoresume = 0;
++module_param (autoresume, uint, 0);
++
++/*
++ * Normally the "loopback" configuration is second (index 1) so
++ * it's not the default. Here's where to change that order, to
++ * work better with hosts where config changes are problematic.
++ * Or controllers (like superh) that only support one config.
++ */
++static int loopdefault = 0;
++
++module_param (loopdefault, bool, S_IRUGO|S_IWUSR);
++
++/*-------------------------------------------------------------------------*/
++
++/* Thanks to NetChip Technologies for donating this product ID.
++ *
++ * DO NOT REUSE THESE IDs with a protocol-incompatible driver!! Ever!!
++ * Instead: allocate your own, using normal USB-IF procedures.
++ */
++#ifndef CONFIG_USB_ZERO_HNPTEST
++#define DRIVER_VENDOR_NUM 0x0525 /* NetChip */
++#define DRIVER_PRODUCT_NUM 0xa4a0 /* Linux-USB "Gadget Zero" */
++#else
++#define DRIVER_VENDOR_NUM 0x1a0a /* OTG test device IDs */
++#define DRIVER_PRODUCT_NUM 0xbadd
++#endif
++
++/*-------------------------------------------------------------------------*/
++
++/*
++ * DESCRIPTORS ... most are static, but strings and (full)
++ * configuration descriptors are built on demand.
++ */
++
++/*
++#define STRING_MANUFACTURER 25
++#define STRING_PRODUCT 42
++#define STRING_SERIAL 101
++*/
++#define STRING_MANUFACTURER 1
++#define STRING_PRODUCT 2
++#define STRING_SERIAL 3
++
++#define STRING_SOURCE_SINK 250
++#define STRING_LOOPBACK 251
++
++/*
++ * This device advertises two configurations; these numbers work
++ * on a pxa250 as well as more flexible hardware.
++ */
++#define CONFIG_SOURCE_SINK 3
++#define CONFIG_LOOPBACK 2
++
++/*
++static struct usb_device_descriptor
++device_desc = {
++ .bLength = sizeof device_desc,
++ .bDescriptorType = USB_DT_DEVICE,
++
++ .bcdUSB = __constant_cpu_to_le16 (0x0200),
++ .bDeviceClass = USB_CLASS_VENDOR_SPEC,
++
++ .idVendor = __constant_cpu_to_le16 (DRIVER_VENDOR_NUM),
++ .idProduct = __constant_cpu_to_le16 (DRIVER_PRODUCT_NUM),
++ .iManufacturer = STRING_MANUFACTURER,
++ .iProduct = STRING_PRODUCT,
++ .iSerialNumber = STRING_SERIAL,
++ .bNumConfigurations = 2,
++};
++*/
++static struct usb_device_descriptor
++device_desc = {
++ .bLength = sizeof device_desc,
++ .bDescriptorType = USB_DT_DEVICE,
++ .bcdUSB = __constant_cpu_to_le16 (0x0100),
++ .bDeviceClass = USB_CLASS_PER_INTERFACE,
++ .bDeviceSubClass = 0,
++ .bDeviceProtocol = 0,
++ .bMaxPacketSize0 = 64,
++ .bcdDevice = __constant_cpu_to_le16 (0x0100),
++ .idVendor = __constant_cpu_to_le16 (0x0499),
++ .idProduct = __constant_cpu_to_le16 (0x3002),
++ .iManufacturer = STRING_MANUFACTURER,
++ .iProduct = STRING_PRODUCT,
++ .iSerialNumber = STRING_SERIAL,
++ .bNumConfigurations = 1,
++};
++
++static struct usb_config_descriptor
++z_config = {
++ .bLength = sizeof z_config,
++ .bDescriptorType = USB_DT_CONFIG,
++
++ /* compute wTotalLength on the fly */
++ .bNumInterfaces = 2,
++ .bConfigurationValue = 1,
++ .iConfiguration = 0,
++ .bmAttributes = 0x40,
++ .bMaxPower = 0, /* self-powered */
++};
++
++
++static struct usb_otg_descriptor
++otg_descriptor = {
++ .bLength = sizeof otg_descriptor,
++ .bDescriptorType = USB_DT_OTG,
++
++ .bmAttributes = USB_OTG_SRP,
++};
++
++/* one interface in each configuration */
++#ifdef CONFIG_USB_GADGET_DUALSPEED
++
++/*
++ * usb 2.0 devices need to expose both high speed and full speed
++ * descriptors, unless they only run at full speed.
++ *
++ * that means alternate endpoint descriptors (bigger packets)
++ * and a "device qualifier" ... plus more construction options
++ * for the config descriptor.
++ */
++
++static struct usb_qualifier_descriptor
++dev_qualifier = {
++ .bLength = sizeof dev_qualifier,
++ .bDescriptorType = USB_DT_DEVICE_QUALIFIER,
++
++ .bcdUSB = __constant_cpu_to_le16 (0x0200),
++ .bDeviceClass = USB_CLASS_VENDOR_SPEC,
++
++ .bNumConfigurations = 2,
++};
++
++
++struct usb_cs_as_general_descriptor {
++ __u8 bLength;
++ __u8 bDescriptorType;
++
++ __u8 bDescriptorSubType;
++ __u8 bTerminalLink;
++ __u8 bDelay;
++ __u16 wFormatTag;
++} __attribute__ ((packed));
++
++struct usb_cs_as_format_descriptor {
++ __u8 bLength;
++ __u8 bDescriptorType;
++
++ __u8 bDescriptorSubType;
++ __u8 bFormatType;
++ __u8 bNrChannels;
++ __u8 bSubframeSize;
++ __u8 bBitResolution;
++ __u8 bSamfreqType;
++ __u8 tLowerSamFreq[3];
++ __u8 tUpperSamFreq[3];
++} __attribute__ ((packed));
++
++static const struct usb_interface_descriptor
++z_audio_control_if_desc = {
++ .bLength = sizeof z_audio_control_if_desc,
++ .bDescriptorType = USB_DT_INTERFACE,
++ .bInterfaceNumber = 0,
++ .bAlternateSetting = 0,
++ .bNumEndpoints = 0,
++ .bInterfaceClass = USB_CLASS_AUDIO,
++ .bInterfaceSubClass = 0x1,
++ .bInterfaceProtocol = 0,
++ .iInterface = 0,
++};
++
++static const struct usb_interface_descriptor
++z_audio_if_desc = {
++ .bLength = sizeof z_audio_if_desc,
++ .bDescriptorType = USB_DT_INTERFACE,
++ .bInterfaceNumber = 1,
++ .bAlternateSetting = 0,
++ .bNumEndpoints = 0,
++ .bInterfaceClass = USB_CLASS_AUDIO,
++ .bInterfaceSubClass = 0x2,
++ .bInterfaceProtocol = 0,
++ .iInterface = 0,
++};
++
++static const struct usb_interface_descriptor
++z_audio_if_desc2 = {
++ .bLength = sizeof z_audio_if_desc,
++ .bDescriptorType = USB_DT_INTERFACE,
++ .bInterfaceNumber = 1,
++ .bAlternateSetting = 1,
++ .bNumEndpoints = 1,
++ .bInterfaceClass = USB_CLASS_AUDIO,
++ .bInterfaceSubClass = 0x2,
++ .bInterfaceProtocol = 0,
++ .iInterface = 0,
++};
++
++static const struct usb_cs_as_general_descriptor
++z_audio_cs_as_if_desc = {
++ .bLength = 7,
++ .bDescriptorType = 0x24,
++
++ .bDescriptorSubType = 0x01,
++ .bTerminalLink = 0x01,
++ .bDelay = 0x0,
++ .wFormatTag = __constant_cpu_to_le16 (0x0001)
++};
++
++
++static const struct usb_cs_as_format_descriptor
++z_audio_cs_as_format_desc = {
++ .bLength = 0xe,
++ .bDescriptorType = 0x24,
++
++ .bDescriptorSubType = 2,
++ .bFormatType = 1,
++ .bNrChannels = 1,
++ .bSubframeSize = 1,
++ .bBitResolution = 8,
++ .bSamfreqType = 0,
++ .tLowerSamFreq = {0x7e, 0x13, 0x00},
++ .tUpperSamFreq = {0xe2, 0xd6, 0x00},
++};
++
++static const struct usb_endpoint_descriptor
++z_iso_ep = {
++ .bLength = 0x09,
++ .bDescriptorType = 0x05,
++ .bEndpointAddress = 0x04,
++ .bmAttributes = 0x09,
++ .wMaxPacketSize = 0x0038,
++ .bInterval = 0x01,
++ .bRefresh = 0x00,
++ .bSynchAddress = 0x00,
++};
++
++static char z_iso_ep2[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
++
++// 9 bytes
++static char z_ac_interface_header_desc[] =
++{ 0x09, 0x24, 0x01, 0x00, 0x01, 0x2b, 0x00, 0x01, 0x01 };
++
++// 12 bytes
++static char z_0[] = {0x0c, 0x24, 0x02, 0x01, 0x01, 0x01, 0x00, 0x02,
++ 0x03, 0x00, 0x00, 0x00};
++// 13 bytes
++static char z_1[] = {0x0d, 0x24, 0x06, 0x02, 0x01, 0x02, 0x15, 0x00,
++ 0x02, 0x00, 0x02, 0x00, 0x00};
++// 9 bytes
++static char z_2[] = {0x09, 0x24, 0x03, 0x03, 0x01, 0x03, 0x00, 0x02,
++ 0x00};
++
++static char za_0[] = {0x09, 0x04, 0x01, 0x02, 0x01, 0x01, 0x02, 0x00,
++ 0x00};
++
++static char za_1[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
++
++static char za_2[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x01, 0x08, 0x00,
++ 0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00};
++
++static char za_3[] = {0x09, 0x05, 0x04, 0x09, 0x70, 0x00, 0x01, 0x00,
++ 0x00};
++
++static char za_4[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
++
++static char za_5[] = {0x09, 0x04, 0x01, 0x03, 0x01, 0x01, 0x02, 0x00,
++ 0x00};
++
++static char za_6[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
++
++static char za_7[] = {0x0e, 0x24, 0x02, 0x01, 0x01, 0x02, 0x10, 0x00,
++ 0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00};
++
++static char za_8[] = {0x09, 0x05, 0x04, 0x09, 0x70, 0x00, 0x01, 0x00,
++ 0x00};
++
++static char za_9[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
++
++static char za_10[] = {0x09, 0x04, 0x01, 0x04, 0x01, 0x01, 0x02, 0x00,
++ 0x00};
++
++static char za_11[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
++
++static char za_12[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x02, 0x10, 0x00,
++ 0x73, 0x13, 0x00, 0xe2, 0xd6, 0x00};
++
++static char za_13[] = {0x09, 0x05, 0x04, 0x09, 0xe0, 0x00, 0x01, 0x00,
++ 0x00};
++
++static char za_14[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
++
++static char za_15[] = {0x09, 0x04, 0x01, 0x05, 0x01, 0x01, 0x02, 0x00,
++ 0x00};
++
++static char za_16[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
++
++static char za_17[] = {0x0e, 0x24, 0x02, 0x01, 0x01, 0x03, 0x14, 0x00,
++ 0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00};
++
++static char za_18[] = {0x09, 0x05, 0x04, 0x09, 0xa8, 0x00, 0x01, 0x00,
++ 0x00};
++
++static char za_19[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
++
++static char za_20[] = {0x09, 0x04, 0x01, 0x06, 0x01, 0x01, 0x02, 0x00,
++ 0x00};
++
++static char za_21[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
++
++static char za_22[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x03, 0x14, 0x00,
++ 0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00};
++
++static char za_23[] = {0x09, 0x05, 0x04, 0x09, 0x50, 0x01, 0x01, 0x00,
++ 0x00};
++
++static char za_24[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
++
++
++
++static const struct usb_descriptor_header *z_function [] = {
++ (struct usb_descriptor_header *) &z_audio_control_if_desc,
++ (struct usb_descriptor_header *) &z_ac_interface_header_desc,
++ (struct usb_descriptor_header *) &z_0,
++ (struct usb_descriptor_header *) &z_1,
++ (struct usb_descriptor_header *) &z_2,
++ (struct usb_descriptor_header *) &z_audio_if_desc,
++ (struct usb_descriptor_header *) &z_audio_if_desc2,
++ (struct usb_descriptor_header *) &z_audio_cs_as_if_desc,
++ (struct usb_descriptor_header *) &z_audio_cs_as_format_desc,
++ (struct usb_descriptor_header *) &z_iso_ep,
++ (struct usb_descriptor_header *) &z_iso_ep2,
++ (struct usb_descriptor_header *) &za_0,
++ (struct usb_descriptor_header *) &za_1,
++ (struct usb_descriptor_header *) &za_2,
++ (struct usb_descriptor_header *) &za_3,
++ (struct usb_descriptor_header *) &za_4,
++ (struct usb_descriptor_header *) &za_5,
++ (struct usb_descriptor_header *) &za_6,
++ (struct usb_descriptor_header *) &za_7,
++ (struct usb_descriptor_header *) &za_8,
++ (struct usb_descriptor_header *) &za_9,
++ (struct usb_descriptor_header *) &za_10,
++ (struct usb_descriptor_header *) &za_11,
++ (struct usb_descriptor_header *) &za_12,
++ (struct usb_descriptor_header *) &za_13,
++ (struct usb_descriptor_header *) &za_14,
++ (struct usb_descriptor_header *) &za_15,
++ (struct usb_descriptor_header *) &za_16,
++ (struct usb_descriptor_header *) &za_17,
++ (struct usb_descriptor_header *) &za_18,
++ (struct usb_descriptor_header *) &za_19,
++ (struct usb_descriptor_header *) &za_20,
++ (struct usb_descriptor_header *) &za_21,
++ (struct usb_descriptor_header *) &za_22,
++ (struct usb_descriptor_header *) &za_23,
++ (struct usb_descriptor_header *) &za_24,
++ NULL,
++};
++
++/* maxpacket and other transfer characteristics vary by speed. */
++#define ep_desc(g,hs,fs) (((g)->speed==USB_SPEED_HIGH)?(hs):(fs))
++
++#else
++
++/* if there's no high speed support, maxpacket doesn't change. */
++#define ep_desc(g,hs,fs) fs
++
++#endif /* !CONFIG_USB_GADGET_DUALSPEED */
++
++static char manufacturer [40];
++//static char serial [40];
++static char serial [] = "Ser 00 em";
++
++/* static strings, in UTF-8 */
++static struct usb_string strings [] = {
++ { STRING_MANUFACTURER, manufacturer, },
++ { STRING_PRODUCT, longname, },
++ { STRING_SERIAL, serial, },
++ { STRING_LOOPBACK, loopback, },
++ { STRING_SOURCE_SINK, source_sink, },
++ { } /* end of list */
++};
++
++static struct usb_gadget_strings stringtab = {
++ .language = 0x0409, /* en-us */
++ .strings = strings,
++};
++
++/*
++ * config descriptors are also handcrafted. these must agree with code
++ * that sets configurations, and with code managing interfaces and their
++ * altsettings. other complexity may come from:
++ *
++ * - high speed support, including "other speed config" rules
++ * - multiple configurations
++ * - interfaces with alternate settings
++ * - embedded class or vendor-specific descriptors
++ *
++ * this handles high speed, and has a second config that could as easily
++ * have been an alternate interface setting (on most hardware).
++ *
++ * NOTE: to demonstrate (and test) more USB capabilities, this driver
++ * should include an altsetting to test interrupt transfers, including
++ * high bandwidth modes at high speed. (Maybe work like Intel's test
++ * device?)
++ */
++static int
++config_buf (struct usb_gadget *gadget, u8 *buf, u8 type, unsigned index)
++{
++ int len;
++ const struct usb_descriptor_header **function;
++
++ function = z_function;
++ len = usb_gadget_config_buf (&z_config, buf, USB_BUFSIZ, function);
++ if (len < 0)
++ return len;
++ ((struct usb_config_descriptor *) buf)->bDescriptorType = type;
++ return len;
++}
++
++/*-------------------------------------------------------------------------*/
++
++static struct usb_request *
++alloc_ep_req (struct usb_ep *ep, unsigned length)
++{
++ struct usb_request *req;
++
++ req = usb_ep_alloc_request (ep, GFP_ATOMIC);
++ if (req) {
++ req->length = length;
++ req->buf = usb_ep_alloc_buffer (ep, length,
++ &req->dma, GFP_ATOMIC);
++ if (!req->buf) {
++ usb_ep_free_request (ep, req);
++ req = NULL;
++ }
++ }
++ return req;
++}
++
++static void free_ep_req (struct usb_ep *ep, struct usb_request *req)
++{
++ if (req->buf)
++ usb_ep_free_buffer (ep, req->buf, req->dma, req->length);
++ usb_ep_free_request (ep, req);
++}
++
++/*-------------------------------------------------------------------------*/
++
++/* optionally require specific source/sink data patterns */
++
++static int
++check_read_data (
++ struct zero_dev *dev,
++ struct usb_ep *ep,
++ struct usb_request *req
++)
++{
++ unsigned i;
++ u8 *buf = req->buf;
++
++ for (i = 0; i < req->actual; i++, buf++) {
++ switch (pattern) {
++ /* all-zeroes has no synchronization issues */
++ case 0:
++ if (*buf == 0)
++ continue;
++ break;
++ /* mod63 stays in sync with short-terminated transfers,
++ * or otherwise when host and gadget agree on how large
++ * each usb transfer request should be. resync is done
++ * with set_interface or set_config.
++ */
++ case 1:
++ if (*buf == (u8)(i % 63))
++ continue;
++ break;
++ }
++ ERROR (dev, "bad OUT byte, buf [%d] = %d\n", i, *buf);
++ usb_ep_set_halt (ep);
++ return -EINVAL;
++ }
++ return 0;
++}
++
++/*-------------------------------------------------------------------------*/
++
++static void zero_reset_config (struct zero_dev *dev)
++{
++ if (dev->config == 0)
++ return;
++
++ DBG (dev, "reset config\n");
++
++ /* just disable endpoints, forcing completion of pending i/o.
++ * all our completion handlers free their requests in this case.
++ */
++ if (dev->in_ep) {
++ usb_ep_disable (dev->in_ep);
++ dev->in_ep = NULL;
++ }
++ if (dev->out_ep) {
++ usb_ep_disable (dev->out_ep);
++ dev->out_ep = NULL;
++ }
++ dev->config = 0;
++ del_timer (&dev->resume);
++}
++
++#define _write(f, buf, sz) (f->f_op->write(f, buf, sz, &f->f_pos))
++
++static void
++zero_isoc_complete (struct usb_ep *ep, struct usb_request *req)
++{
++ struct zero_dev *dev = ep->driver_data;
++ int status = req->status;
++ int i, j;
++
++ switch (status) {
++
++ case 0: /* normal completion? */
++ //printk ("\nzero ---------------> isoc normal completion %d bytes\n", req->actual);
++ for (i=0, j=rbuf_start; i<req->actual; i++) {
++ //printk ("%02x ", ((__u8*)req->buf)[i]);
++ rbuf[j] = ((__u8*)req->buf)[i];
++ j++;
++ if (j >= RBUF_LEN) j=0;
++ }
++ rbuf_start = j;
++ //printk ("\n\n");
++
++ if (rbuf_len < RBUF_LEN) {
++ rbuf_len += req->actual;
++ if (rbuf_len > RBUF_LEN) {
++ rbuf_len = RBUF_LEN;
++ }
++ }
++
++ break;
++
++ /* this endpoint is normally active while we're configured */
++ case -ECONNABORTED: /* hardware forced ep reset */
++ case -ECONNRESET: /* request dequeued */
++ case -ESHUTDOWN: /* disconnect from host */
++ VDBG (dev, "%s gone (%d), %d/%d\n", ep->name, status,
++ req->actual, req->length);
++ if (ep == dev->out_ep)
++ check_read_data (dev, ep, req);
++ free_ep_req (ep, req);
++ return;
++
++ case -EOVERFLOW: /* buffer overrun on read means that
++ * we didn't provide a big enough
++ * buffer.
++ */
++ default:
++#if 1
++ DBG (dev, "%s complete --> %d, %d/%d\n", ep->name,
++ status, req->actual, req->length);
++#endif
++ case -EREMOTEIO: /* short read */
++ break;
++ }
++
++ status = usb_ep_queue (ep, req, GFP_ATOMIC);
++ if (status) {
++ ERROR (dev, "kill %s: resubmit %d bytes --> %d\n",
++ ep->name, req->length, status);
++ usb_ep_set_halt (ep);
++ /* FIXME recover later ... somehow */
++ }
++}
++
++static struct usb_request *
++zero_start_isoc_ep (struct usb_ep *ep, int gfp_flags)
++{
++ struct usb_request *req;
++ int status;
++
++ req = alloc_ep_req (ep, 512);
++ if (!req)
++ return NULL;
++
++ req->complete = zero_isoc_complete;
++
++ status = usb_ep_queue (ep, req, gfp_flags);
++ if (status) {
++ struct zero_dev *dev = ep->driver_data;
++
++ ERROR (dev, "start %s --> %d\n", ep->name, status);
++ free_ep_req (ep, req);
++ req = NULL;
++ }
++
++ return req;
++}
++
++/* change our operational config. this code must agree with the code
++ * that returns config descriptors, and altsetting code.
++ *
++ * it's also responsible for power management interactions. some
++ * configurations might not work with our current power sources.
++ *
++ * note that some device controller hardware will constrain what this
++ * code can do, perhaps by disallowing more than one configuration or
++ * by limiting configuration choices (like the pxa2xx).
++ */
++static int
++zero_set_config (struct zero_dev *dev, unsigned number, int gfp_flags)
++{
++ int result = 0;
++ struct usb_gadget *gadget = dev->gadget;
++ const struct usb_endpoint_descriptor *d;
++ struct usb_ep *ep;
++
++ if (number == dev->config)
++ return 0;
++
++ zero_reset_config (dev);
++
++ gadget_for_each_ep (ep, gadget) {
++
++ if (strcmp (ep->name, "ep4") == 0) {
++
++ d = (struct usb_endpoint_descripter *)&za_23; // isoc ep desc for audio i/f alt setting 6
++ result = usb_ep_enable (ep, d);
++
++ if (result == 0) {
++ ep->driver_data = dev;
++ dev->in_ep = ep;
++
++ if (zero_start_isoc_ep (ep, gfp_flags) != 0) {
++
++ dev->in_ep = ep;
++ continue;
++ }
++
++ usb_ep_disable (ep);
++ result = -EIO;
++ }
++ }
++
++ }
++
++ dev->config = number;
++ return result;
++}
++
++/*-------------------------------------------------------------------------*/
++
++static void zero_setup_complete (struct usb_ep *ep, struct usb_request *req)
++{
++ if (req->status || req->actual != req->length)
++ DBG ((struct zero_dev *) ep->driver_data,
++ "setup complete --> %d, %d/%d\n",
++ req->status, req->actual, req->length);
++}
++
++/*
++ * The setup() callback implements all the ep0 functionality that's
++ * not handled lower down, in hardware or the hardware driver (like
++ * device and endpoint feature flags, and their status). It's all
++ * housekeeping for the gadget function we're implementing. Most of
++ * the work is in config-specific setup.
++ */
++static int
++zero_setup (struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl)
++{
++ struct zero_dev *dev = get_gadget_data (gadget);
++ struct usb_request *req = dev->req;
++ int value = -EOPNOTSUPP;
++
++ /* usually this stores reply data in the pre-allocated ep0 buffer,
++ * but config change events will reconfigure hardware.
++ */
++ req->zero = 0;
++ switch (ctrl->bRequest) {
++
++ case USB_REQ_GET_DESCRIPTOR:
++
++ switch (ctrl->wValue >> 8) {
++
++ case USB_DT_DEVICE:
++ value = min (ctrl->wLength, (u16) sizeof device_desc);
++ memcpy (req->buf, &device_desc, value);
++ break;
++#ifdef CONFIG_USB_GADGET_DUALSPEED
++ case USB_DT_DEVICE_QUALIFIER:
++ if (!gadget->is_dualspeed)
++ break;
++ value = min (ctrl->wLength, (u16) sizeof dev_qualifier);
++ memcpy (req->buf, &dev_qualifier, value);
++ break;
++
++ case USB_DT_OTHER_SPEED_CONFIG:
++ if (!gadget->is_dualspeed)
++ break;
++ // FALLTHROUGH
++#endif /* CONFIG_USB_GADGET_DUALSPEED */
++ case USB_DT_CONFIG:
++ value = config_buf (gadget, req->buf,
++ ctrl->wValue >> 8,
++ ctrl->wValue & 0xff);
++ if (value >= 0)
++ value = min (ctrl->wLength, (u16) value);
++ break;
++
++ case USB_DT_STRING:
++ /* wIndex == language code.
++ * this driver only handles one language, you can
++ * add string tables for other languages, using
++ * any UTF-8 characters
++ */
++ value = usb_gadget_get_string (&stringtab,
++ ctrl->wValue & 0xff, req->buf);
++ if (value >= 0) {
++ value = min (ctrl->wLength, (u16) value);
++ }
++ break;
++ }
++ break;
++
++ /* currently two configs, two speeds */
++ case USB_REQ_SET_CONFIGURATION:
++ if (ctrl->bRequestType != 0)
++ goto unknown;
++
++ spin_lock (&dev->lock);
++ value = zero_set_config (dev, ctrl->wValue, GFP_ATOMIC);
++ spin_unlock (&dev->lock);
++ break;
++ case USB_REQ_GET_CONFIGURATION:
++ if (ctrl->bRequestType != USB_DIR_IN)
++ goto unknown;
++ *(u8 *)req->buf = dev->config;
++ value = min (ctrl->wLength, (u16) 1);
++ break;
++
++ /* until we add altsetting support, or other interfaces,
++ * only 0/0 are possible. pxa2xx only supports 0/0 (poorly)
++ * and already killed pending endpoint I/O.
++ */
++ case USB_REQ_SET_INTERFACE:
++
++ if (ctrl->bRequestType != USB_RECIP_INTERFACE)
++ goto unknown;
++ spin_lock (&dev->lock);
++ if (dev->config) {
++ u8 config = dev->config;
++
++ /* resets interface configuration, forgets about
++ * previous transaction state (queued bufs, etc)
++ * and re-inits endpoint state (toggle etc)
++ * no response queued, just zero status == success.
++ * if we had more than one interface we couldn't
++ * use this "reset the config" shortcut.
++ */
++ zero_reset_config (dev);
++ zero_set_config (dev, config, GFP_ATOMIC);
++ value = 0;
++ }
++ spin_unlock (&dev->lock);
++ break;
++ case USB_REQ_GET_INTERFACE:
++ if ((ctrl->bRequestType == 0x21) && (ctrl->wIndex == 0x02)) {
++ value = ctrl->wLength;
++ break;
++ }
++ else {
++ if (ctrl->bRequestType != (USB_DIR_IN|USB_RECIP_INTERFACE))
++ goto unknown;
++ if (!dev->config)
++ break;
++ if (ctrl->wIndex != 0) {
++ value = -EDOM;
++ break;
++ }
++ *(u8 *)req->buf = 0;
++ value = min (ctrl->wLength, (u16) 1);
++ }
++ break;
++
++ /*
++ * These are the same vendor-specific requests supported by
++ * Intel's USB 2.0 compliance test devices. We exceed that
++ * device spec by allowing multiple-packet requests.
++ */
++ case 0x5b: /* control WRITE test -- fill the buffer */
++ if (ctrl->bRequestType != (USB_DIR_OUT|USB_TYPE_VENDOR))
++ goto unknown;
++ if (ctrl->wValue || ctrl->wIndex)
++ break;
++ /* just read that many bytes into the buffer */
++ if (ctrl->wLength > USB_BUFSIZ)
++ break;
++ value = ctrl->wLength;
++ break;
++ case 0x5c: /* control READ test -- return the buffer */
++ if (ctrl->bRequestType != (USB_DIR_IN|USB_TYPE_VENDOR))
++ goto unknown;
++ if (ctrl->wValue || ctrl->wIndex)
++ break;
++ /* expect those bytes are still in the buffer; send back */
++ if (ctrl->wLength > USB_BUFSIZ
++ || ctrl->wLength != req->length)
++ break;
++ value = ctrl->wLength;
++ break;
++
++ case 0x01: // SET_CUR
++ case 0x02:
++ case 0x03:
++ case 0x04:
++ case 0x05:
++ value = ctrl->wLength;
++ break;
++ case 0x81:
++ switch (ctrl->wValue) {
++ case 0x0201:
++ case 0x0202:
++ ((u8*)req->buf)[0] = 0x00;
++ ((u8*)req->buf)[1] = 0xe3;
++ break;
++ case 0x0300:
++ case 0x0500:
++ ((u8*)req->buf)[0] = 0x00;
++ break;
++ }
++ //((u8*)req->buf)[0] = 0x81;
++ //((u8*)req->buf)[1] = 0x81;
++ value = ctrl->wLength;
++ break;
++ case 0x82:
++ switch (ctrl->wValue) {
++ case 0x0201:
++ case 0x0202:
++ ((u8*)req->buf)[0] = 0x00;
++ ((u8*)req->buf)[1] = 0xc3;
++ break;
++ case 0x0300:
++ case 0x0500:
++ ((u8*)req->buf)[0] = 0x00;
++ break;
++ }
++ //((u8*)req->buf)[0] = 0x82;
++ //((u8*)req->buf)[1] = 0x82;
++ value = ctrl->wLength;
++ break;
++ case 0x83:
++ switch (ctrl->wValue) {
++ case 0x0201:
++ case 0x0202:
++ ((u8*)req->buf)[0] = 0x00;
++ ((u8*)req->buf)[1] = 0x00;
++ break;
++ case 0x0300:
++ ((u8*)req->buf)[0] = 0x60;
++ break;
++ case 0x0500:
++ ((u8*)req->buf)[0] = 0x18;
++ break;
++ }
++ //((u8*)req->buf)[0] = 0x83;
++ //((u8*)req->buf)[1] = 0x83;
++ value = ctrl->wLength;
++ break;
++ case 0x84:
++ switch (ctrl->wValue) {
++ case 0x0201:
++ case 0x0202:
++ ((u8*)req->buf)[0] = 0x00;
++ ((u8*)req->buf)[1] = 0x01;
++ break;
++ case 0x0300:
++ case 0x0500:
++ ((u8*)req->buf)[0] = 0x08;
++ break;
++ }
++ //((u8*)req->buf)[0] = 0x84;
++ //((u8*)req->buf)[1] = 0x84;
++ value = ctrl->wLength;
++ break;
++ case 0x85:
++ ((u8*)req->buf)[0] = 0x85;
++ ((u8*)req->buf)[1] = 0x85;
++ value = ctrl->wLength;
++ break;
++
++
++ default:
++unknown:
++ printk("unknown control req%02x.%02x v%04x i%04x l%d\n",
++ ctrl->bRequestType, ctrl->bRequest,
++ ctrl->wValue, ctrl->wIndex, ctrl->wLength);
++ }
++
++ /* respond with data transfer before status phase? */
++ if (value >= 0) {
++ req->length = value;
++ req->zero = value < ctrl->wLength
++ && (value % gadget->ep0->maxpacket) == 0;
++ value = usb_ep_queue (gadget->ep0, req, GFP_ATOMIC);
++ if (value < 0) {
++ DBG (dev, "ep_queue < 0 --> %d\n", value);
++ req->status = 0;
++ zero_setup_complete (gadget->ep0, req);
++ }
++ }
++
++ /* device either stalls (value < 0) or reports success */
++ return value;
++}
++
++static void
++zero_disconnect (struct usb_gadget *gadget)
++{
++ struct zero_dev *dev = get_gadget_data (gadget);
++ unsigned long flags;
++
++ spin_lock_irqsave (&dev->lock, flags);
++ zero_reset_config (dev);
++
++ /* a more significant application might have some non-usb
++ * activities to quiesce here, saving resources like power
++ * or pushing the notification up a network stack.
++ */
++ spin_unlock_irqrestore (&dev->lock, flags);
++
++ /* next we may get setup() calls to enumerate new connections;
++ * or an unbind() during shutdown (including removing module).
++ */
++}
++
++static void
++zero_autoresume (unsigned long _dev)
++{
++ struct zero_dev *dev = (struct zero_dev *) _dev;
++ int status;
++
++ /* normally the host would be woken up for something
++ * more significant than just a timer firing...
++ */
++ if (dev->gadget->speed != USB_SPEED_UNKNOWN) {
++ status = usb_gadget_wakeup (dev->gadget);
++ DBG (dev, "wakeup --> %d\n", status);
++ }
++}
++
++/*-------------------------------------------------------------------------*/
++
++static void
++zero_unbind (struct usb_gadget *gadget)
++{
++ struct zero_dev *dev = get_gadget_data (gadget);
++
++ DBG (dev, "unbind\n");
++
++ /* we've already been disconnected ... no i/o is active */
++ if (dev->req)
++ free_ep_req (gadget->ep0, dev->req);
++ del_timer_sync (&dev->resume);
++ kfree (dev);
++ set_gadget_data (gadget, NULL);
++}
++
++static int
++zero_bind (struct usb_gadget *gadget)
++{
++ struct zero_dev *dev;
++ //struct usb_ep *ep;
++
++ printk("binding\n");
++ /*
++ * DRIVER POLICY CHOICE: you may want to do this differently.
++ * One thing to avoid is reusing a bcdDevice revision code
++ * with different host-visible configurations or behavior
++ * restrictions -- using ep1in/ep2out vs ep1out/ep3in, etc
++ */
++ //device_desc.bcdDevice = __constant_cpu_to_le16 (0x0201);
++
++
++ /* ok, we made sense of the hardware ... */
++ dev = kmalloc (sizeof *dev, SLAB_KERNEL);
++ if (!dev)
++ return -ENOMEM;
++ memset (dev, 0, sizeof *dev);
++ spin_lock_init (&dev->lock);
++ dev->gadget = gadget;
++ set_gadget_data (gadget, dev);
++
++ /* preallocate control response and buffer */
++ dev->req = usb_ep_alloc_request (gadget->ep0, GFP_KERNEL);
++ if (!dev->req)
++ goto enomem;
++ dev->req->buf = usb_ep_alloc_buffer (gadget->ep0, USB_BUFSIZ,
++ &dev->req->dma, GFP_KERNEL);
++ if (!dev->req->buf)
++ goto enomem;
++
++ dev->req->complete = zero_setup_complete;
++
++ device_desc.bMaxPacketSize0 = gadget->ep0->maxpacket;
++
++#ifdef CONFIG_USB_GADGET_DUALSPEED
++ /* assume ep0 uses the same value for both speeds ... */
++ dev_qualifier.bMaxPacketSize0 = device_desc.bMaxPacketSize0;
++
++ /* and that all endpoints are dual-speed */
++ //hs_source_desc.bEndpointAddress = fs_source_desc.bEndpointAddress;
++ //hs_sink_desc.bEndpointAddress = fs_sink_desc.bEndpointAddress;
++#endif
++
++ usb_gadget_set_selfpowered (gadget);
++
++ init_timer (&dev->resume);
++ dev->resume.function = zero_autoresume;
++ dev->resume.data = (unsigned long) dev;
++
++ gadget->ep0->driver_data = dev;
++
++ INFO (dev, "%s, version: " DRIVER_VERSION "\n", longname);
++ INFO (dev, "using %s, OUT %s IN %s\n", gadget->name,
++ EP_OUT_NAME, EP_IN_NAME);
++
++ snprintf (manufacturer, sizeof manufacturer,
++ UTS_SYSNAME " " UTS_RELEASE " with %s",
++ gadget->name);
++
++ return 0;
++
++enomem:
++ zero_unbind (gadget);
++ return -ENOMEM;
++}
++
++/*-------------------------------------------------------------------------*/
++
++static void
++zero_suspend (struct usb_gadget *gadget)
++{
++ struct zero_dev *dev = get_gadget_data (gadget);
++
++ if (gadget->speed == USB_SPEED_UNKNOWN)
++ return;
++
++ if (autoresume) {
++ mod_timer (&dev->resume, jiffies + (HZ * autoresume));
++ DBG (dev, "suspend, wakeup in %d seconds\n", autoresume);
++ } else
++ DBG (dev, "suspend\n");
++}
++
++static void
++zero_resume (struct usb_gadget *gadget)
++{
++ struct zero_dev *dev = get_gadget_data (gadget);
++
++ DBG (dev, "resume\n");
++ del_timer (&dev->resume);
++}
++
++
++/*-------------------------------------------------------------------------*/
++
++static struct usb_gadget_driver zero_driver = {
++#ifdef CONFIG_USB_GADGET_DUALSPEED
++ .speed = USB_SPEED_HIGH,
++#else
++ .speed = USB_SPEED_FULL,
++#endif
++ .function = (char *) longname,
++ .bind = zero_bind,
++ .unbind = zero_unbind,
++
++ .setup = zero_setup,
++ .disconnect = zero_disconnect,
++
++ .suspend = zero_suspend,
++ .resume = zero_resume,
++
++ .driver = {
++ .name = (char *) shortname,
++ // .shutdown = ...
++ // .suspend = ...
++ // .resume = ...
++ },
++};
++
++MODULE_AUTHOR ("David Brownell");
++MODULE_LICENSE ("Dual BSD/GPL");
++
++static struct proc_dir_entry *pdir, *pfile;
++
++static int isoc_read_data (char *page, char **start,
++ off_t off, int count,
++ int *eof, void *data)
++{
++ int i;
++ static int c = 0;
++ static int done = 0;
++ static int s = 0;
++
++/*
++ printk ("\ncount: %d\n", count);
++ printk ("rbuf_start: %d\n", rbuf_start);
++ printk ("rbuf_len: %d\n", rbuf_len);
++ printk ("off: %d\n", off);
++ printk ("start: %p\n\n", *start);
++*/
++ if (done) {
++ c = 0;
++ done = 0;
++ *eof = 1;
++ return 0;
++ }
++
++ if (c == 0) {
++ if (rbuf_len == RBUF_LEN)
++ s = rbuf_start;
++ else s = 0;
++ }
++
++ for (i=0; i<count && c<rbuf_len; i++, c++) {
++ page[i] = rbuf[(c+s) % RBUF_LEN];
++ }
++ *start = page;
++
++ if (c >= rbuf_len) {
++ *eof = 1;
++ done = 1;
++ }
++
++
++ return i;
++}
++
++static int __init init (void)
++{
++
++ int retval = 0;
++
++ pdir = proc_mkdir("isoc_test", NULL);
++ if(pdir == NULL) {
++ retval = -ENOMEM;
++ printk("Error creating dir\n");
++ goto done;
++ }
++ pdir->owner = THIS_MODULE;
++
++ pfile = create_proc_read_entry("isoc_data",
++ 0444, pdir,
++ isoc_read_data,
++ NULL);
++ if (pfile == NULL) {
++ retval = -ENOMEM;
++ printk("Error creating file\n");
++ goto no_file;
++ }
++ pfile->owner = THIS_MODULE;
++
++ return usb_gadget_register_driver (&zero_driver);
++
++ no_file:
++ remove_proc_entry("isoc_data", NULL);
++ done:
++ return retval;
++}
++module_init (init);
++
++static void __exit cleanup (void)
++{
++
++ usb_gadget_unregister_driver (&zero_driver);
++
++ remove_proc_entry("isoc_data", pdir);
++ remove_proc_entry("isoc_test", NULL);
++}
++module_exit (cleanup);
+diff -Nur linux-4.1.3/drivers/usb/host/dwc_otg/dwc_cfi_common.h linux-xbian-rpi/drivers/usb/host/dwc_otg/dwc_cfi_common.h
+--- linux-4.1.3/drivers/usb/host/dwc_otg/dwc_cfi_common.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/usb/host/dwc_otg/dwc_cfi_common.h 2015-07-28 01:20:58.445156473 +0200
+@@ -0,0 +1,142 @@
++/* ==========================================================================
++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++ * otherwise expressly agreed to in writing between Synopsys and you.
++ *
++ * The Software IS NOT an item of Licensed Software or Licensed Product under
++ * any End User Software License Agreement or Agreement for Licensed Product
++ * with Synopsys or any supplement thereto. You are permitted to use and
++ * redistribute this Software in source and binary forms, with or without
++ * modification, provided that redistributions of source code must retain this
++ * notice. You may not view, use, disclose, copy or distribute this file or
++ * any information contained herein except pursuant to this license grant from
++ * Synopsys. If you do not agree with this notice, including the disclaimer
++ * below, then you are not authorized to use the Software.
++ *
++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++ * DAMAGE.
++ * ========================================================================== */
++
++#if !defined(__DWC_CFI_COMMON_H__)
++#define __DWC_CFI_COMMON_H__
++
++//#include <linux/types.h>
++
++/**
++ * @file
++ *
++ * This file contains the CFI specific common constants, interfaces
++ * (functions and macros) and structures for Linux. No PCD specific
++ * data structure or definition is to be included in this file.
++ *
++ */
++
++/** This is a request for all Core Features */
++#define VEN_CORE_GET_FEATURES 0xB1
++
++/** This is a request to get the value of a specific Core Feature */
++#define VEN_CORE_GET_FEATURE 0xB2
++
++/** This command allows the host to set the value of a specific Core Feature */
++#define VEN_CORE_SET_FEATURE 0xB3
++
++/** This command allows the host to set the default values of
++ * either all or any specific Core Feature
++ */
++#define VEN_CORE_RESET_FEATURES 0xB4
++
++/** This command forces the PCD to write the deferred values of a Core Features */
++#define VEN_CORE_ACTIVATE_FEATURES 0xB5
++
++/** This request reads a DWORD value from a register at the specified offset */
++#define VEN_CORE_READ_REGISTER 0xB6
++
++/** This request writes a DWORD value into a register at the specified offset */
++#define VEN_CORE_WRITE_REGISTER 0xB7
++
++/** This structure is the header of the Core Features dataset returned to
++ * the Host
++ */
++struct cfi_all_features_header {
++/** The features header structure length is */
++#define CFI_ALL_FEATURES_HDR_LEN 8
++ /**
++ * The total length of the features dataset returned to the Host
++ */
++ uint16_t wTotalLen;
++
++ /**
++ * CFI version number inBinary-Coded Decimal (i.e., 1.00 is 100H).
++ * This field identifies the version of the CFI Specification with which
++ * the device is compliant.
++ */
++ uint16_t wVersion;
++
++ /** The ID of the Core */
++ uint16_t wCoreID;
++#define CFI_CORE_ID_UDC 1
++#define CFI_CORE_ID_OTG 2
++#define CFI_CORE_ID_WUDEV 3
++
++ /** Number of features returned by VEN_CORE_GET_FEATURES request */
++ uint16_t wNumFeatures;
++} UPACKED;
++
++typedef struct cfi_all_features_header cfi_all_features_header_t;
++
++/** This structure is a header of the Core Feature descriptor dataset returned to
++ * the Host after the VEN_CORE_GET_FEATURES request
++ */
++struct cfi_feature_desc_header {
++#define CFI_FEATURE_DESC_HDR_LEN 8
++
++ /** The feature ID */
++ uint16_t wFeatureID;
++
++ /** Length of this feature descriptor in bytes - including the
++ * length of the feature name string
++ */
++ uint16_t wLength;
++
++ /** The data length of this feature in bytes */
++ uint16_t wDataLength;
++
++ /**
++ * Attributes of this features
++ * D0: Access rights
++ * 0 - Read/Write
++ * 1 - Read only
++ */
++ uint8_t bmAttributes;
++#define CFI_FEATURE_ATTR_RO 1
++#define CFI_FEATURE_ATTR_RW 0
++
++ /** Length of the feature name in bytes */
++ uint8_t bNameLen;
++
++ /** The feature name buffer */
++ //uint8_t *name;
++} UPACKED;
++
++typedef struct cfi_feature_desc_header cfi_feature_desc_header_t;
++
++/**
++ * This structure describes a NULL terminated string referenced by its id field.
++ * It is very similar to usb_string structure but has the id field type set to 16-bit.
++ */
++struct cfi_string {
++ uint16_t id;
++ const uint8_t *s;
++};
++typedef struct cfi_string cfi_string_t;
++
++#endif
+diff -Nur linux-4.1.3/drivers/usb/host/dwc_otg/dwc_otg_adp.c linux-xbian-rpi/drivers/usb/host/dwc_otg/dwc_otg_adp.c
+--- linux-4.1.3/drivers/usb/host/dwc_otg/dwc_otg_adp.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/usb/host/dwc_otg/dwc_otg_adp.c 2015-07-28 01:20:58.445156473 +0200
+@@ -0,0 +1,854 @@
++/* ==========================================================================
++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_adp.c $
++ * $Revision: #12 $
++ * $Date: 2011/10/26 $
++ * $Change: 1873028 $
++ *
++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++ * otherwise expressly agreed to in writing between Synopsys and you.
++ *
++ * The Software IS NOT an item of Licensed Software or Licensed Product under
++ * any End User Software License Agreement or Agreement for Licensed Product
++ * with Synopsys or any supplement thereto. You are permitted to use and
++ * redistribute this Software in source and binary forms, with or without
++ * modification, provided that redistributions of source code must retain this
++ * notice. You may not view, use, disclose, copy or distribute this file or
++ * any information contained herein except pursuant to this license grant from
++ * Synopsys. If you do not agree with this notice, including the disclaimer
++ * below, then you are not authorized to use the Software.
++ *
++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++ * DAMAGE.
++ * ========================================================================== */
++
++#include "dwc_os.h"
++#include "dwc_otg_regs.h"
++#include "dwc_otg_cil.h"
++#include "dwc_otg_adp.h"
++
++/** @file
++ *
++ * This file contains the most of the Attach Detect Protocol implementation for
++ * the driver to support OTG Rev2.0.
++ *
++ */
++
++void dwc_otg_adp_write_reg(dwc_otg_core_if_t * core_if, uint32_t value)
++{
++ adpctl_data_t adpctl;
++
++ adpctl.d32 = value;
++ adpctl.b.ar = 0x2;
++
++ DWC_WRITE_REG32(&core_if->core_global_regs->adpctl, adpctl.d32);
++
++ while (adpctl.b.ar) {
++ adpctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->adpctl);
++ }
++
++}
++
++/**
++ * Function is called to read ADP registers
++ */
++uint32_t dwc_otg_adp_read_reg(dwc_otg_core_if_t * core_if)
++{
++ adpctl_data_t adpctl;
++
++ adpctl.d32 = 0;
++ adpctl.b.ar = 0x1;
++
++ DWC_WRITE_REG32(&core_if->core_global_regs->adpctl, adpctl.d32);
++
++ while (adpctl.b.ar) {
++ adpctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->adpctl);
++ }
++
++ return adpctl.d32;
++}
++
++/**
++ * Function is called to read ADPCTL register and filter Write-clear bits
++ */
++uint32_t dwc_otg_adp_read_reg_filter(dwc_otg_core_if_t * core_if)
++{
++ adpctl_data_t adpctl;
++
++ adpctl.d32 = dwc_otg_adp_read_reg(core_if);
++ adpctl.b.adp_tmout_int = 0;
++ adpctl.b.adp_prb_int = 0;
++ adpctl.b.adp_tmout_int = 0;
++
++ return adpctl.d32;
++}
++
++/**
++ * Function is called to write ADP registers
++ */
++void dwc_otg_adp_modify_reg(dwc_otg_core_if_t * core_if, uint32_t clr,
++ uint32_t set)
++{
++ dwc_otg_adp_write_reg(core_if,
++ (dwc_otg_adp_read_reg(core_if) & (~clr)) | set);
++}
++
++static void adp_sense_timeout(void *ptr)
++{
++ dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr;
++ core_if->adp.sense_timer_started = 0;
++ DWC_PRINTF("ADP SENSE TIMEOUT\n");
++ if (core_if->adp_enable) {
++ dwc_otg_adp_sense_stop(core_if);
++ dwc_otg_adp_probe_start(core_if);
++ }
++}
++
++/**
++ * This function is called when the ADP vbus timer expires. Timeout is 1.1s.
++ */
++static void adp_vbuson_timeout(void *ptr)
++{
++ gpwrdn_data_t gpwrdn;
++ dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr;
++ hprt0_data_t hprt0 = {.d32 = 0 };
++ pcgcctl_data_t pcgcctl = {.d32 = 0 };
++ DWC_PRINTF("%s: 1.1 seconds expire after turning on VBUS\n",__FUNCTION__);
++ if (core_if) {
++ core_if->adp.vbuson_timer_started = 0;
++ /* Turn off vbus */
++ hprt0.b.prtpwr = 1;
++ DWC_MODIFY_REG32(core_if->host_if->hprt0, hprt0.d32, 0);
++ gpwrdn.d32 = 0;
++
++ /* Power off the core */
++ if (core_if->power_down == 2) {
++ /* Enable Wakeup Logic */
++// gpwrdn.b.wkupactiv = 1;
++ gpwrdn.b.pmuactv = 0;
++ gpwrdn.b.pwrdnrstn = 1;
++ gpwrdn.b.pwrdnclmp = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0,
++ gpwrdn.d32);
++
++ /* Suspend the Phy Clock */
++ pcgcctl.b.stoppclk = 1;
++ DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32);
++
++ /* Switch on VDD */
++// gpwrdn.b.wkupactiv = 1;
++ gpwrdn.b.pmuactv = 1;
++ gpwrdn.b.pwrdnrstn = 1;
++ gpwrdn.b.pwrdnclmp = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0,
++ gpwrdn.d32);
++ } else {
++ /* Enable Power Down Logic */
++ gpwrdn.b.pmuintsel = 1;
++ gpwrdn.b.pmuactv = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
++ }
++
++ /* Power off the core */
++ if (core_if->power_down == 2) {
++ gpwrdn.d32 = 0;
++ gpwrdn.b.pwrdnswtch = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn,
++ gpwrdn.d32, 0);
++ }
++
++ /* Unmask SRP detected interrupt from Power Down Logic */
++ gpwrdn.d32 = 0;
++ gpwrdn.b.srp_det_msk = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
++
++ dwc_otg_adp_probe_start(core_if);
++ dwc_otg_dump_global_registers(core_if);
++ dwc_otg_dump_host_registers(core_if);
++ }
++
++}
++
++/**
++ * Start the ADP Initial Probe timer to detect if Port Connected interrupt is
++ * not asserted within 1.1 seconds.
++ *
++ * @param core_if the pointer to core_if strucure.
++ */
++void dwc_otg_adp_vbuson_timer_start(dwc_otg_core_if_t * core_if)
++{
++ core_if->adp.vbuson_timer_started = 1;
++ if (core_if->adp.vbuson_timer)
++ {
++ DWC_PRINTF("SCHEDULING VBUSON TIMER\n");
++ /* 1.1 secs + 60ms necessary for cil_hcd_start*/
++ DWC_TIMER_SCHEDULE(core_if->adp.vbuson_timer, 1160);
++ } else {
++ DWC_WARN("VBUSON_TIMER = %p\n",core_if->adp.vbuson_timer);
++ }
++}
++
++#if 0
++/**
++ * Masks all DWC OTG core interrupts
++ *
++ */
++static void mask_all_interrupts(dwc_otg_core_if_t * core_if)
++{
++ int i;
++ gahbcfg_data_t ahbcfg = {.d32 = 0 };
++
++ /* Mask Host Interrupts */
++
++ /* Clear and disable HCINTs */
++ for (i = 0; i < core_if->core_params->host_channels; i++) {
++ DWC_WRITE_REG32(&core_if->host_if->hc_regs[i]->hcintmsk, 0);
++ DWC_WRITE_REG32(&core_if->host_if->hc_regs[i]->hcint, 0xFFFFFFFF);
++
++ }
++
++ /* Clear and disable HAINT */
++ DWC_WRITE_REG32(&core_if->host_if->host_global_regs->haintmsk, 0x0000);
++ DWC_WRITE_REG32(&core_if->host_if->host_global_regs->haint, 0xFFFFFFFF);
++
++ /* Mask Device Interrupts */
++ if (!core_if->multiproc_int_enable) {
++ /* Clear and disable IN Endpoint interrupts */
++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->diepmsk, 0);
++ for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
++ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->
++ diepint, 0xFFFFFFFF);
++ }
++
++ /* Clear and disable OUT Endpoint interrupts */
++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->doepmsk, 0);
++ for (i = 0; i <= core_if->dev_if->num_out_eps; i++) {
++ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]->
++ doepint, 0xFFFFFFFF);
++ }
++
++ /* Clear and disable DAINT */
++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->daint,
++ 0xFFFFFFFF);
++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->daintmsk, 0);
++ } else {
++ for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->
++ diepeachintmsk[i], 0);
++ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->
++ diepint, 0xFFFFFFFF);
++ }
++
++ for (i = 0; i < core_if->dev_if->num_out_eps; ++i) {
++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->
++ doepeachintmsk[i], 0);
++ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]->
++ doepint, 0xFFFFFFFF);
++ }
++
++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->deachintmsk,
++ 0);
++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->deachint,
++ 0xFFFFFFFF);
++
++ }
++
++ /* Disable interrupts */
++ ahbcfg.b.glblintrmsk = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, ahbcfg.d32, 0);
++
++ /* Disable all interrupts. */
++ DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, 0);
++
++ /* Clear any pending interrupts */
++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
++
++ /* Clear any pending OTG Interrupts */
++ DWC_WRITE_REG32(&core_if->core_global_regs->gotgint, 0xFFFFFFFF);
++}
++
++/**
++ * Unmask Port Connection Detected interrupt
++ *
++ */
++static void unmask_conn_det_intr(dwc_otg_core_if_t * core_if)
++{
++ gintmsk_data_t gintmsk = {.d32 = 0,.b.portintr = 1 };
++
++ DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32);
++}
++#endif
++
++/**
++ * Starts the ADP Probing
++ *
++ * @param core_if the pointer to core_if structure.
++ */
++uint32_t dwc_otg_adp_probe_start(dwc_otg_core_if_t * core_if)
++{
++
++ adpctl_data_t adpctl = {.d32 = 0};
++ gpwrdn_data_t gpwrdn;
++#if 0
++ adpctl_data_t adpctl_int = {.d32 = 0, .b.adp_prb_int = 1,
++ .b.adp_sns_int = 1, b.adp_tmout_int};
++#endif
++ dwc_otg_disable_global_interrupts(core_if);
++ DWC_PRINTF("ADP Probe Start\n");
++ core_if->adp.probe_enabled = 1;
++
++ adpctl.b.adpres = 1;
++ dwc_otg_adp_write_reg(core_if, adpctl.d32);
++
++ while (adpctl.b.adpres) {
++ adpctl.d32 = dwc_otg_adp_read_reg(core_if);
++ }
++
++ adpctl.d32 = 0;
++ gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
++
++ /* In Host mode unmask SRP detected interrupt */
++ gpwrdn.d32 = 0;
++ gpwrdn.b.sts_chngint_msk = 1;
++ if (!gpwrdn.b.idsts) {
++ gpwrdn.b.srp_det_msk = 1;
++ }
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
++
++ adpctl.b.adp_tmout_int_msk = 1;
++ adpctl.b.adp_prb_int_msk = 1;
++ adpctl.b.prb_dschg = 1;
++ adpctl.b.prb_delta = 1;
++ adpctl.b.prb_per = 1;
++ adpctl.b.adpen = 1;
++ adpctl.b.enaprb = 1;
++
++ dwc_otg_adp_write_reg(core_if, adpctl.d32);
++ DWC_PRINTF("ADP Probe Finish\n");
++ return 0;
++}
++
++/**
++ * Starts the ADP Sense timer to detect if ADP Sense interrupt is not asserted
++ * within 3 seconds.
++ *
++ * @param core_if the pointer to core_if strucure.
++ */
++void dwc_otg_adp_sense_timer_start(dwc_otg_core_if_t * core_if)
++{
++ core_if->adp.sense_timer_started = 1;
++ DWC_TIMER_SCHEDULE(core_if->adp.sense_timer, 3000 /* 3 secs */ );
++}
++
++/**
++ * Starts the ADP Sense
++ *
++ * @param core_if the pointer to core_if strucure.
++ */
++uint32_t dwc_otg_adp_sense_start(dwc_otg_core_if_t * core_if)
++{
++ adpctl_data_t adpctl;
++
++ DWC_PRINTF("ADP Sense Start\n");
++
++ /* Unmask ADP sense interrupt and mask all other from the core */
++ adpctl.d32 = dwc_otg_adp_read_reg_filter(core_if);
++ adpctl.b.adp_sns_int_msk = 1;
++ dwc_otg_adp_write_reg(core_if, adpctl.d32);
++ dwc_otg_disable_global_interrupts(core_if); // vahrama
++
++ /* Set ADP reset bit*/
++ adpctl.d32 = dwc_otg_adp_read_reg_filter(core_if);
++ adpctl.b.adpres = 1;
++ dwc_otg_adp_write_reg(core_if, adpctl.d32);
++
++ while (adpctl.b.adpres) {
++ adpctl.d32 = dwc_otg_adp_read_reg(core_if);
++ }
++
++ adpctl.b.adpres = 0;
++ adpctl.b.adpen = 1;
++ adpctl.b.enasns = 1;
++ dwc_otg_adp_write_reg(core_if, adpctl.d32);
++
++ dwc_otg_adp_sense_timer_start(core_if);
++
++ return 0;
++}
++
++/**
++ * Stops the ADP Probing
++ *
++ * @param core_if the pointer to core_if strucure.
++ */
++uint32_t dwc_otg_adp_probe_stop(dwc_otg_core_if_t * core_if)
++{
++
++ adpctl_data_t adpctl;
++ DWC_PRINTF("Stop ADP probe\n");
++ core_if->adp.probe_enabled = 0;
++ core_if->adp.probe_counter = 0;
++ adpctl.d32 = dwc_otg_adp_read_reg(core_if);
++
++ adpctl.b.adpen = 0;
++ adpctl.b.adp_prb_int = 1;
++ adpctl.b.adp_tmout_int = 1;
++ adpctl.b.adp_sns_int = 1;
++ dwc_otg_adp_write_reg(core_if, adpctl.d32);
++
++ return 0;
++}
++
++/**
++ * Stops the ADP Sensing
++ *
++ * @param core_if the pointer to core_if strucure.
++ */
++uint32_t dwc_otg_adp_sense_stop(dwc_otg_core_if_t * core_if)
++{
++ adpctl_data_t adpctl;
++
++ core_if->adp.sense_enabled = 0;
++
++ adpctl.d32 = dwc_otg_adp_read_reg_filter(core_if);
++ adpctl.b.enasns = 0;
++ adpctl.b.adp_sns_int = 1;
++ dwc_otg_adp_write_reg(core_if, adpctl.d32);
++
++ return 0;
++}
++
++/**
++ * Called to turn on the VBUS after initial ADP probe in host mode.
++ * If port power was already enabled in cil_hcd_start function then
++ * only schedule a timer.
++ *
++ * @param core_if the pointer to core_if structure.
++ */
++void dwc_otg_adp_turnon_vbus(dwc_otg_core_if_t * core_if)
++{
++ hprt0_data_t hprt0 = {.d32 = 0 };
++ hprt0.d32 = dwc_otg_read_hprt0(core_if);
++ DWC_PRINTF("Turn on VBUS for 1.1s, port power is %d\n", hprt0.b.prtpwr);
++
++ if (hprt0.b.prtpwr == 0) {
++ hprt0.b.prtpwr = 1;
++ //DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
++ }
++
++ dwc_otg_adp_vbuson_timer_start(core_if);
++}
++
++/**
++ * Called right after driver is loaded
++ * to perform initial actions for ADP
++ *
++ * @param core_if the pointer to core_if structure.
++ * @param is_host - flag for current mode of operation either from GINTSTS or GPWRDN
++ */
++void dwc_otg_adp_start(dwc_otg_core_if_t * core_if, uint8_t is_host)
++{
++ gpwrdn_data_t gpwrdn;
++
++ DWC_PRINTF("ADP Initial Start\n");
++ core_if->adp.adp_started = 1;
++
++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
++ dwc_otg_disable_global_interrupts(core_if);
++ if (is_host) {
++ DWC_PRINTF("HOST MODE\n");
++ /* Enable Power Down Logic Interrupt*/
++ gpwrdn.d32 = 0;
++ gpwrdn.b.pmuintsel = 1;
++ gpwrdn.b.pmuactv = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
++ /* Initialize first ADP probe to obtain Ramp Time value */
++ core_if->adp.initial_probe = 1;
++ dwc_otg_adp_probe_start(core_if);
++ } else {
++ gotgctl_data_t gotgctl;
++ gotgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
++ DWC_PRINTF("DEVICE MODE\n");
++ if (gotgctl.b.bsesvld == 0) {
++ /* Enable Power Down Logic Interrupt*/
++ gpwrdn.d32 = 0;
++ DWC_PRINTF("VBUS is not valid - start ADP probe\n");
++ gpwrdn.b.pmuintsel = 1;
++ gpwrdn.b.pmuactv = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
++ core_if->adp.initial_probe = 1;
++ dwc_otg_adp_probe_start(core_if);
++ } else {
++ DWC_PRINTF("VBUS is valid - initialize core as a Device\n");
++ core_if->op_state = B_PERIPHERAL;
++ dwc_otg_core_init(core_if);
++ dwc_otg_enable_global_interrupts(core_if);
++ cil_pcd_start(core_if);
++ dwc_otg_dump_global_registers(core_if);
++ dwc_otg_dump_dev_registers(core_if);
++ }
++ }
++}
++
++void dwc_otg_adp_init(dwc_otg_core_if_t * core_if)
++{
++ core_if->adp.adp_started = 0;
++ core_if->adp.initial_probe = 0;
++ core_if->adp.probe_timer_values[0] = -1;
++ core_if->adp.probe_timer_values[1] = -1;
++ core_if->adp.probe_enabled = 0;
++ core_if->adp.sense_enabled = 0;
++ core_if->adp.sense_timer_started = 0;
++ core_if->adp.vbuson_timer_started = 0;
++ core_if->adp.probe_counter = 0;
++ core_if->adp.gpwrdn = 0;
++ core_if->adp.attached = DWC_OTG_ADP_UNKOWN;
++ /* Initialize timers */
++ core_if->adp.sense_timer =
++ DWC_TIMER_ALLOC("ADP SENSE TIMER", adp_sense_timeout, core_if);
++ core_if->adp.vbuson_timer =
++ DWC_TIMER_ALLOC("ADP VBUS ON TIMER", adp_vbuson_timeout, core_if);
++ if (!core_if->adp.sense_timer || !core_if->adp.vbuson_timer)
++ {
++ DWC_ERROR("Could not allocate memory for ADP timers\n");
++ }
++}
++
++void dwc_otg_adp_remove(dwc_otg_core_if_t * core_if)
++{
++ gpwrdn_data_t gpwrdn = { .d32 = 0 };
++ gpwrdn.b.pmuintsel = 1;
++ gpwrdn.b.pmuactv = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++
++ if (core_if->adp.probe_enabled)
++ dwc_otg_adp_probe_stop(core_if);
++ if (core_if->adp.sense_enabled)
++ dwc_otg_adp_sense_stop(core_if);
++ if (core_if->adp.sense_timer_started)
++ DWC_TIMER_CANCEL(core_if->adp.sense_timer);
++ if (core_if->adp.vbuson_timer_started)
++ DWC_TIMER_CANCEL(core_if->adp.vbuson_timer);
++ DWC_TIMER_FREE(core_if->adp.sense_timer);
++ DWC_TIMER_FREE(core_if->adp.vbuson_timer);
++}
++
++/////////////////////////////////////////////////////////////////////
++////////////// ADP Interrupt Handlers ///////////////////////////////
++/////////////////////////////////////////////////////////////////////
++/**
++ * This function sets Ramp Timer values
++ */
++static uint32_t set_timer_value(dwc_otg_core_if_t * core_if, uint32_t val)
++{
++ if (core_if->adp.probe_timer_values[0] == -1) {
++ core_if->adp.probe_timer_values[0] = val;
++ core_if->adp.probe_timer_values[1] = -1;
++ return 1;
++ } else {
++ core_if->adp.probe_timer_values[1] =
++ core_if->adp.probe_timer_values[0];
++ core_if->adp.probe_timer_values[0] = val;
++ return 0;
++ }
++}
++
++/**
++ * This function compares Ramp Timer values
++ */
++static uint32_t compare_timer_values(dwc_otg_core_if_t * core_if)
++{
++ uint32_t diff;
++ if (core_if->adp.probe_timer_values[0]>=core_if->adp.probe_timer_values[1])
++ diff = core_if->adp.probe_timer_values[0]-core_if->adp.probe_timer_values[1];
++ else
++ diff = core_if->adp.probe_timer_values[1]-core_if->adp.probe_timer_values[0];
++ if(diff < 2) {
++ return 0;
++ } else {
++ return 1;
++ }
++}
++
++/**
++ * This function handles ADP Probe Interrupts
++ */
++static int32_t dwc_otg_adp_handle_prb_intr(dwc_otg_core_if_t * core_if,
++ uint32_t val)
++{
++ adpctl_data_t adpctl = {.d32 = 0 };
++ gpwrdn_data_t gpwrdn, temp;
++ adpctl.d32 = val;
++
++ temp.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
++ core_if->adp.probe_counter++;
++ core_if->adp.gpwrdn = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
++ if (adpctl.b.rtim == 0 && !temp.b.idsts){
++ DWC_PRINTF("RTIM value is 0\n");
++ goto exit;
++ }
++ if (set_timer_value(core_if, adpctl.b.rtim) &&
++ core_if->adp.initial_probe) {
++ core_if->adp.initial_probe = 0;
++ dwc_otg_adp_probe_stop(core_if);
++ gpwrdn.d32 = 0;
++ gpwrdn.b.pmuactv = 1;
++ gpwrdn.b.pmuintsel = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
++
++ /* check which value is for device mode and which for Host mode */
++ if (!temp.b.idsts) { /* considered host mode value is 0 */
++ /*
++ * Turn on VBUS after initial ADP probe.
++ */
++ core_if->op_state = A_HOST;
++ dwc_otg_enable_global_interrupts(core_if);
++ DWC_SPINUNLOCK(core_if->lock);
++ cil_hcd_start(core_if);
++ dwc_otg_adp_turnon_vbus(core_if);
++ DWC_SPINLOCK(core_if->lock);
++ } else {
++ /*
++ * Initiate SRP after initial ADP probe.
++ */
++ dwc_otg_enable_global_interrupts(core_if);
++ dwc_otg_initiate_srp(core_if);
++ }
++ } else if (core_if->adp.probe_counter > 2){
++ gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
++ if (compare_timer_values(core_if)) {
++ DWC_PRINTF("Difference in timer values !!! \n");
++// core_if->adp.attached = DWC_OTG_ADP_ATTACHED;
++ dwc_otg_adp_probe_stop(core_if);
++
++ /* Power on the core */
++ if (core_if->power_down == 2) {
++ gpwrdn.b.pwrdnswtch = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->
++ gpwrdn, 0, gpwrdn.d32);
++ }
++
++ /* check which value is for device mode and which for Host mode */
++ if (!temp.b.idsts) { /* considered host mode value is 0 */
++ /* Disable Interrupt from Power Down Logic */
++ gpwrdn.d32 = 0;
++ gpwrdn.b.pmuintsel = 1;
++ gpwrdn.b.pmuactv = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->
++ gpwrdn, gpwrdn.d32, 0);
++
++ /*
++ * Initialize the Core for Host mode.
++ */
++ core_if->op_state = A_HOST;
++ dwc_otg_core_init(core_if);
++ dwc_otg_enable_global_interrupts(core_if);
++ cil_hcd_start(core_if);
++ } else {
++ gotgctl_data_t gotgctl;
++ /* Mask SRP detected interrupt from Power Down Logic */
++ gpwrdn.d32 = 0;
++ gpwrdn.b.srp_det_msk = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->
++ gpwrdn, gpwrdn.d32, 0);
++
++ /* Disable Power Down Logic */
++ gpwrdn.d32 = 0;
++ gpwrdn.b.pmuintsel = 1;
++ gpwrdn.b.pmuactv = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->
++ gpwrdn, gpwrdn.d32, 0);
++
++ /*
++ * Initialize the Core for Device mode.
++ */
++ core_if->op_state = B_PERIPHERAL;
++ dwc_otg_core_init(core_if);
++ dwc_otg_enable_global_interrupts(core_if);
++ cil_pcd_start(core_if);
++
++ gotgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
++ if (!gotgctl.b.bsesvld) {
++ dwc_otg_initiate_srp(core_if);
++ }
++ }
++ }
++ if (core_if->power_down == 2) {
++ if (gpwrdn.b.bsessvld) {
++ /* Mask SRP detected interrupt from Power Down Logic */
++ gpwrdn.d32 = 0;
++ gpwrdn.b.srp_det_msk = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++
++ /* Disable Power Down Logic */
++ gpwrdn.d32 = 0;
++ gpwrdn.b.pmuactv = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++
++ /*
++ * Initialize the Core for Device mode.
++ */
++ core_if->op_state = B_PERIPHERAL;
++ dwc_otg_core_init(core_if);
++ dwc_otg_enable_global_interrupts(core_if);
++ cil_pcd_start(core_if);
++ }
++ }
++ }
++exit:
++ /* Clear interrupt */
++ adpctl.d32 = dwc_otg_adp_read_reg(core_if);
++ adpctl.b.adp_prb_int = 1;
++ dwc_otg_adp_write_reg(core_if, adpctl.d32);
++
++ return 0;
++}
++
++/**
++ * This function hadles ADP Sense Interrupt
++ */
++static int32_t dwc_otg_adp_handle_sns_intr(dwc_otg_core_if_t * core_if)
++{
++ adpctl_data_t adpctl;
++ /* Stop ADP Sense timer */
++ DWC_TIMER_CANCEL(core_if->adp.sense_timer);
++
++ /* Restart ADP Sense timer */
++ dwc_otg_adp_sense_timer_start(core_if);
++
++ /* Clear interrupt */
++ adpctl.d32 = dwc_otg_adp_read_reg(core_if);
++ adpctl.b.adp_sns_int = 1;
++ dwc_otg_adp_write_reg(core_if, adpctl.d32);
++
++ return 0;
++}
++
++/**
++ * This function handles ADP Probe Interrupts
++ */
++static int32_t dwc_otg_adp_handle_prb_tmout_intr(dwc_otg_core_if_t * core_if,
++ uint32_t val)
++{
++ adpctl_data_t adpctl = {.d32 = 0 };
++ adpctl.d32 = val;
++ set_timer_value(core_if, adpctl.b.rtim);
++
++ /* Clear interrupt */
++ adpctl.d32 = dwc_otg_adp_read_reg(core_if);
++ adpctl.b.adp_tmout_int = 1;
++ dwc_otg_adp_write_reg(core_if, adpctl.d32);
++
++ return 0;
++}
++
++/**
++ * ADP Interrupt handler.
++ *
++ */
++int32_t dwc_otg_adp_handle_intr(dwc_otg_core_if_t * core_if)
++{
++ int retval = 0;
++ adpctl_data_t adpctl = {.d32 = 0};
++
++ adpctl.d32 = dwc_otg_adp_read_reg(core_if);
++ DWC_PRINTF("ADPCTL = %08x\n",adpctl.d32);
++
++ if (adpctl.b.adp_sns_int & adpctl.b.adp_sns_int_msk) {
++ DWC_PRINTF("ADP Sense interrupt\n");
++ retval |= dwc_otg_adp_handle_sns_intr(core_if);
++ }
++ if (adpctl.b.adp_tmout_int & adpctl.b.adp_tmout_int_msk) {
++ DWC_PRINTF("ADP timeout interrupt\n");
++ retval |= dwc_otg_adp_handle_prb_tmout_intr(core_if, adpctl.d32);
++ }
++ if (adpctl.b.adp_prb_int & adpctl.b.adp_prb_int_msk) {
++ DWC_PRINTF("ADP Probe interrupt\n");
++ adpctl.b.adp_prb_int = 1;
++ retval |= dwc_otg_adp_handle_prb_intr(core_if, adpctl.d32);
++ }
++
++// dwc_otg_adp_modify_reg(core_if, adpctl.d32, 0);
++ //dwc_otg_adp_write_reg(core_if, adpctl.d32);
++ DWC_PRINTF("RETURN FROM ADP ISR\n");
++
++ return retval;
++}
++
++/**
++ *
++ * @param core_if Programming view of DWC_otg controller.
++ */
++int32_t dwc_otg_adp_handle_srp_intr(dwc_otg_core_if_t * core_if)
++{
++
++#ifndef DWC_HOST_ONLY
++ hprt0_data_t hprt0;
++ gpwrdn_data_t gpwrdn;
++ DWC_DEBUGPL(DBG_ANY, "++ Power Down Logic Session Request Interrupt++\n");
++
++ gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
++ /* check which value is for device mode and which for Host mode */
++ if (!gpwrdn.b.idsts) { /* considered host mode value is 0 */
++ DWC_PRINTF("SRP: Host mode\n");
++
++ if (core_if->adp_enable) {
++ dwc_otg_adp_probe_stop(core_if);
++
++ /* Power on the core */
++ if (core_if->power_down == 2) {
++ gpwrdn.b.pwrdnswtch = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->
++ gpwrdn, 0, gpwrdn.d32);
++ }
++
++ core_if->op_state = A_HOST;
++ dwc_otg_core_init(core_if);
++ dwc_otg_enable_global_interrupts(core_if);
++ cil_hcd_start(core_if);
++ }
++
++ /* Turn on the port power bit. */
++ hprt0.d32 = dwc_otg_read_hprt0(core_if);
++ hprt0.b.prtpwr = 1;
++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
++
++ /* Start the Connection timer. So a message can be displayed
++ * if connect does not occur within 10 seconds. */
++ cil_hcd_session_start(core_if);
++ } else {
++ DWC_PRINTF("SRP: Device mode %s\n", __FUNCTION__);
++ if (core_if->adp_enable) {
++ dwc_otg_adp_probe_stop(core_if);
++
++ /* Power on the core */
++ if (core_if->power_down == 2) {
++ gpwrdn.b.pwrdnswtch = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->
++ gpwrdn, 0, gpwrdn.d32);
++ }
++
++ gpwrdn.d32 = 0;
++ gpwrdn.b.pmuactv = 0;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0,
++ gpwrdn.d32);
++
++ core_if->op_state = B_PERIPHERAL;
++ dwc_otg_core_init(core_if);
++ dwc_otg_enable_global_interrupts(core_if);
++ cil_pcd_start(core_if);
++ }
++ }
++#endif
++ return 1;
++}
+diff -Nur linux-4.1.3/drivers/usb/host/dwc_otg/dwc_otg_adp.h linux-xbian-rpi/drivers/usb/host/dwc_otg/dwc_otg_adp.h
+--- linux-4.1.3/drivers/usb/host/dwc_otg/dwc_otg_adp.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/usb/host/dwc_otg/dwc_otg_adp.h 2015-07-28 01:20:58.445156473 +0200
+@@ -0,0 +1,80 @@
++/* ==========================================================================
++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_adp.h $
++ * $Revision: #7 $
++ * $Date: 2011/10/24 $
++ * $Change: 1871159 $
++ *
++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++ * otherwise expressly agreed to in writing between Synopsys and you.
++ *
++ * The Software IS NOT an item of Licensed Software or Licensed Product under
++ * any End User Software License Agreement or Agreement for Licensed Product
++ * with Synopsys or any supplement thereto. You are permitted to use and
++ * redistribute this Software in source and binary forms, with or without
++ * modification, provided that redistributions of source code must retain this
++ * notice. You may not view, use, disclose, copy or distribute this file or
++ * any information contained herein except pursuant to this license grant from
++ * Synopsys. If you do not agree with this notice, including the disclaimer
++ * below, then you are not authorized to use the Software.
++ *
++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++ * DAMAGE.
++ * ========================================================================== */
++
++#ifndef __DWC_OTG_ADP_H__
++#define __DWC_OTG_ADP_H__
++
++/**
++ * @file
++ *
++ * This file contains the Attach Detect Protocol interfaces and defines
++ * (functions) and structures for Linux.
++ *
++ */
++
++#define DWC_OTG_ADP_UNATTACHED 0
++#define DWC_OTG_ADP_ATTACHED 1
++#define DWC_OTG_ADP_UNKOWN 2
++
++typedef struct dwc_otg_adp {
++ uint32_t adp_started;
++ uint32_t initial_probe;
++ int32_t probe_timer_values[2];
++ uint32_t probe_enabled;
++ uint32_t sense_enabled;
++ dwc_timer_t *sense_timer;
++ uint32_t sense_timer_started;
++ dwc_timer_t *vbuson_timer;
++ uint32_t vbuson_timer_started;
++ uint32_t attached;
++ uint32_t probe_counter;
++ uint32_t gpwrdn;
++} dwc_otg_adp_t;
++
++/**
++ * Attach Detect Protocol functions
++ */
++
++extern void dwc_otg_adp_write_reg(dwc_otg_core_if_t * core_if, uint32_t value);
++extern uint32_t dwc_otg_adp_read_reg(dwc_otg_core_if_t * core_if);
++extern uint32_t dwc_otg_adp_probe_start(dwc_otg_core_if_t * core_if);
++extern uint32_t dwc_otg_adp_sense_start(dwc_otg_core_if_t * core_if);
++extern uint32_t dwc_otg_adp_probe_stop(dwc_otg_core_if_t * core_if);
++extern uint32_t dwc_otg_adp_sense_stop(dwc_otg_core_if_t * core_if);
++extern void dwc_otg_adp_start(dwc_otg_core_if_t * core_if, uint8_t is_host);
++extern void dwc_otg_adp_init(dwc_otg_core_if_t * core_if);
++extern void dwc_otg_adp_remove(dwc_otg_core_if_t * core_if);
++extern int32_t dwc_otg_adp_handle_intr(dwc_otg_core_if_t * core_if);
++extern int32_t dwc_otg_adp_handle_srp_intr(dwc_otg_core_if_t * core_if);
++
++#endif //__DWC_OTG_ADP_H__
+diff -Nur linux-4.1.3/drivers/usb/host/dwc_otg/dwc_otg_attr.c linux-xbian-rpi/drivers/usb/host/dwc_otg/dwc_otg_attr.c
+--- linux-4.1.3/drivers/usb/host/dwc_otg/dwc_otg_attr.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/usb/host/dwc_otg/dwc_otg_attr.c 2015-07-28 01:20:58.445156473 +0200
+@@ -0,0 +1,1210 @@
++/* ==========================================================================
++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_attr.c $
++ * $Revision: #44 $
++ * $Date: 2010/11/29 $
++ * $Change: 1636033 $
++ *
++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++ * otherwise expressly agreed to in writing between Synopsys and you.
++ *
++ * The Software IS NOT an item of Licensed Software or Licensed Product under
++ * any End User Software License Agreement or Agreement for Licensed Product
++ * with Synopsys or any supplement thereto. You are permitted to use and
++ * redistribute this Software in source and binary forms, with or without
++ * modification, provided that redistributions of source code must retain this
++ * notice. You may not view, use, disclose, copy or distribute this file or
++ * any information contained herein except pursuant to this license grant from
++ * Synopsys. If you do not agree with this notice, including the disclaimer
++ * below, then you are not authorized to use the Software.
++ *
++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++ * DAMAGE.
++ * ========================================================================== */
++
++/** @file
++ *
++ * The diagnostic interface will provide access to the controller for
++ * bringing up the hardware and testing. The Linux driver attributes
++ * feature will be used to provide the Linux Diagnostic
++ * Interface. These attributes are accessed through sysfs.
++ */
++
++/** @page "Linux Module Attributes"
++ *
++ * The Linux module attributes feature is used to provide the Linux
++ * Diagnostic Interface. These attributes are accessed through sysfs.
++ * The diagnostic interface will provide access to the controller for
++ * bringing up the hardware and testing.
++
++ The following table shows the attributes.
++ <table>
++ <tr>
++ <td><b> Name</b></td>
++ <td><b> Description</b></td>
++ <td><b> Access</b></td>
++ </tr>
++
++ <tr>
++ <td> mode </td>
++ <td> Returns the current mode: 0 for device mode, 1 for host mode</td>
++ <td> Read</td>
++ </tr>
++
++ <tr>
++ <td> hnpcapable </td>
++ <td> Gets or sets the "HNP-capable" bit in the Core USB Configuraton Register.
++ Read returns the current value.</td>
++ <td> Read/Write</td>
++ </tr>
++
++ <tr>
++ <td> srpcapable </td>
++ <td> Gets or sets the "SRP-capable" bit in the Core USB Configuraton Register.
++ Read returns the current value.</td>
++ <td> Read/Write</td>
++ </tr>
++
++ <tr>
++ <td> hsic_connect </td>
++ <td> Gets or sets the "HSIC-Connect" bit in the GLPMCFG Register.
++ Read returns the current value.</td>
++ <td> Read/Write</td>
++ </tr>
++
++ <tr>
++ <td> inv_sel_hsic </td>
++ <td> Gets or sets the "Invert Select HSIC" bit in the GLPMFG Register.
++ Read returns the current value.</td>
++ <td> Read/Write</td>
++ </tr>
++
++ <tr>
++ <td> hnp </td>
++ <td> Initiates the Host Negotiation Protocol. Read returns the status.</td>
++ <td> Read/Write</td>
++ </tr>
++
++ <tr>
++ <td> srp </td>
++ <td> Initiates the Session Request Protocol. Read returns the status.</td>
++ <td> Read/Write</td>
++ </tr>
++
++ <tr>
++ <td> buspower </td>
++ <td> Gets or sets the Power State of the bus (0 - Off or 1 - On)</td>
++ <td> Read/Write</td>
++ </tr>
++
++ <tr>
++ <td> bussuspend </td>
++ <td> Suspends the USB bus.</td>
++ <td> Read/Write</td>
++ </tr>
++
++ <tr>
++ <td> busconnected </td>
++ <td> Gets the connection status of the bus</td>
++ <td> Read</td>
++ </tr>
++
++ <tr>
++ <td> gotgctl </td>
++ <td> Gets or sets the Core Control Status Register.</td>
++ <td> Read/Write</td>
++ </tr>
++
++ <tr>
++ <td> gusbcfg </td>
++ <td> Gets or sets the Core USB Configuration Register</td>
++ <td> Read/Write</td>
++ </tr>
++
++ <tr>
++ <td> grxfsiz </td>
++ <td> Gets or sets the Receive FIFO Size Register</td>
++ <td> Read/Write</td>
++ </tr>
++
++ <tr>
++ <td> gnptxfsiz </td>
++ <td> Gets or sets the non-periodic Transmit Size Register</td>
++ <td> Read/Write</td>
++ </tr>
++
++ <tr>
++ <td> gpvndctl </td>
++ <td> Gets or sets the PHY Vendor Control Register</td>
++ <td> Read/Write</td>
++ </tr>
++
++ <tr>
++ <td> ggpio </td>
++ <td> Gets the value in the lower 16-bits of the General Purpose IO Register
++ or sets the upper 16 bits.</td>
++ <td> Read/Write</td>
++ </tr>
++
++ <tr>
++ <td> guid </td>
++ <td> Gets or sets the value of the User ID Register</td>
++ <td> Read/Write</td>
++ </tr>
++
++ <tr>
++ <td> gsnpsid </td>
++ <td> Gets the value of the Synopsys ID Regester</td>
++ <td> Read</td>
++ </tr>
++
++ <tr>
++ <td> devspeed </td>
++ <td> Gets or sets the device speed setting in the DCFG register</td>
++ <td> Read/Write</td>
++ </tr>
++
++ <tr>
++ <td> enumspeed </td>
++ <td> Gets the device enumeration Speed.</td>
++ <td> Read</td>
++ </tr>
++
++ <tr>
++ <td> hptxfsiz </td>
++ <td> Gets the value of the Host Periodic Transmit FIFO</td>
++ <td> Read</td>
++ </tr>
++
++ <tr>
++ <td> hprt0 </td>
++ <td> Gets or sets the value in the Host Port Control and Status Register</td>
++ <td> Read/Write</td>
++ </tr>
++
++ <tr>
++ <td> regoffset </td>
++ <td> Sets the register offset for the next Register Access</td>
++ <td> Read/Write</td>
++ </tr>
++
++ <tr>
++ <td> regvalue </td>
++ <td> Gets or sets the value of the register at the offset in the regoffset attribute.</td>
++ <td> Read/Write</td>
++ </tr>
++
++ <tr>
++ <td> remote_wakeup </td>
++ <td> On read, shows the status of Remote Wakeup. On write, initiates a remote
++ wakeup of the host. When bit 0 is 1 and Remote Wakeup is enabled, the Remote
++ Wakeup signalling bit in the Device Control Register is set for 1
++ milli-second.</td>
++ <td> Read/Write</td>
++ </tr>
++
++ <tr>
++ <td> rem_wakeup_pwrdn </td>
++ <td> On read, shows the status core - hibernated or not. On write, initiates
++ a remote wakeup of the device from Hibernation. </td>
++ <td> Read/Write</td>
++ </tr>
++
++ <tr>
++ <td> mode_ch_tim_en </td>
++ <td> This bit is used to enable or disable the host core to wait for 200 PHY
++ clock cycles at the end of Resume to change the opmode signal to the PHY to 00
++ after Suspend or LPM. </td>
++ <td> Read/Write</td>
++ </tr>
++
++ <tr>
++ <td> fr_interval </td>
++ <td> On read, shows the value of HFIR Frame Interval. On write, dynamically
++ reload HFIR register during runtime. The application can write a value to this
++ register only after the Port Enable bit of the Host Port Control and Status
++ register (HPRT.PrtEnaPort) has been set </td>
++ <td> Read/Write</td>
++ </tr>
++
++ <tr>
++ <td> disconnect_us </td>
++ <td> On read, shows the status of disconnect_device_us. On write, sets disconnect_us
++ which causes soft disconnect for 100us. Applicable only for device mode of operation.</td>
++ <td> Read/Write</td>
++ </tr>
++
++ <tr>
++ <td> regdump </td>
++ <td> Dumps the contents of core registers.</td>
++ <td> Read</td>
++ </tr>
++
++ <tr>
++ <td> spramdump </td>
++ <td> Dumps the contents of core registers.</td>
++ <td> Read</td>
++ </tr>
++
++ <tr>
++ <td> hcddump </td>
++ <td> Dumps the current HCD state.</td>
++ <td> Read</td>
++ </tr>
++
++ <tr>
++ <td> hcd_frrem </td>
++ <td> Shows the average value of the Frame Remaining
++ field in the Host Frame Number/Frame Remaining register when an SOF interrupt
++ occurs. This can be used to determine the average interrupt latency. Also
++ shows the average Frame Remaining value for start_transfer and the "a" and
++ "b" sample points. The "a" and "b" sample points may be used during debugging
++ bto determine how long it takes to execute a section of the HCD code.</td>
++ <td> Read</td>
++ </tr>
++
++ <tr>
++ <td> rd_reg_test </td>
++ <td> Displays the time required to read the GNPTXFSIZ register many times
++ (the output shows the number of times the register is read).
++ <td> Read</td>
++ </tr>
++
++ <tr>
++ <td> wr_reg_test </td>
++ <td> Displays the time required to write the GNPTXFSIZ register many times
++ (the output shows the number of times the register is written).
++ <td> Read</td>
++ </tr>
++
++ <tr>
++ <td> lpm_response </td>
++ <td> Gets or sets lpm_response mode. Applicable only in device mode.
++ <td> Write</td>
++ </tr>
++
++ <tr>
++ <td> sleep_status </td>
++ <td> Shows sleep status of device.
++ <td> Read</td>
++ </tr>
++
++ </table>
++
++ Example usage:
++ To get the current mode:
++ cat /sys/devices/lm0/mode
++
++ To power down the USB:
++ echo 0 > /sys/devices/lm0/buspower
++ */
++
++#include "dwc_otg_os_dep.h"
++#include "dwc_os.h"
++#include "dwc_otg_driver.h"
++#include "dwc_otg_attr.h"
++#include "dwc_otg_core_if.h"
++#include "dwc_otg_pcd_if.h"
++#include "dwc_otg_hcd_if.h"
++
++/*
++ * MACROs for defining sysfs attribute
++ */
++#ifdef LM_INTERFACE
++
++#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
++static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
++{ \
++ struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \
++ dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \
++ uint32_t val; \
++ val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
++ return sprintf (buf, "%s = 0x%x\n", _string_, val); \
++}
++#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \
++static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
++ const char *buf, size_t count) \
++{ \
++ struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \
++ dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \
++ uint32_t set = simple_strtoul(buf, NULL, 16); \
++ dwc_otg_set_##_otg_attr_name_(otg_dev->core_if, set);\
++ return count; \
++}
++
++#elif defined(PCI_INTERFACE)
++
++#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
++static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
++{ \
++ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); \
++ uint32_t val; \
++ val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
++ return sprintf (buf, "%s = 0x%x\n", _string_, val); \
++}
++#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \
++static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
++ const char *buf, size_t count) \
++{ \
++ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); \
++ uint32_t set = simple_strtoul(buf, NULL, 16); \
++ dwc_otg_set_##_otg_attr_name_(otg_dev->core_if, set);\
++ return count; \
++}
++
++#elif defined(PLATFORM_INTERFACE)
++
++#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
++static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
++{ \
++ struct platform_device *platform_dev = \
++ container_of(_dev, struct platform_device, dev); \
++ dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); \
++ uint32_t val; \
++ DWC_PRINTF("%s(%p) -> platform_dev %p, otg_dev %p\n", \
++ __func__, _dev, platform_dev, otg_dev); \
++ val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
++ return sprintf (buf, "%s = 0x%x\n", _string_, val); \
++}
++#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \
++static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
++ const char *buf, size_t count) \
++{ \
++ struct platform_device *platform_dev = container_of(_dev, struct platform_device, dev); \
++ dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); \
++ uint32_t set = simple_strtoul(buf, NULL, 16); \
++ dwc_otg_set_##_otg_attr_name_(otg_dev->core_if, set);\
++ return count; \
++}
++#endif
++
++/*
++ * MACROs for defining sysfs attribute for 32-bit registers
++ */
++#ifdef LM_INTERFACE
++#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
++static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
++{ \
++ struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \
++ dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \
++ uint32_t val; \
++ val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
++ return sprintf (buf, "%s = 0x%08x\n", _string_, val); \
++}
++#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \
++static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
++ const char *buf, size_t count) \
++{ \
++ struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \
++ dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \
++ uint32_t val = simple_strtoul(buf, NULL, 16); \
++ dwc_otg_set_##_otg_attr_name_ (otg_dev->core_if, val); \
++ return count; \
++}
++#elif defined(PCI_INTERFACE)
++#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
++static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
++{ \
++ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); \
++ uint32_t val; \
++ val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
++ return sprintf (buf, "%s = 0x%08x\n", _string_, val); \
++}
++#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \
++static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
++ const char *buf, size_t count) \
++{ \
++ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); \
++ uint32_t val = simple_strtoul(buf, NULL, 16); \
++ dwc_otg_set_##_otg_attr_name_ (otg_dev->core_if, val); \
++ return count; \
++}
++
++#elif defined(PLATFORM_INTERFACE)
++#include "dwc_otg_dbg.h"
++#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
++static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
++{ \
++ struct platform_device *platform_dev = container_of(_dev, struct platform_device, dev); \
++ dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); \
++ uint32_t val; \
++ DWC_PRINTF("%s(%p) -> platform_dev %p, otg_dev %p\n", \
++ __func__, _dev, platform_dev, otg_dev); \
++ val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
++ return sprintf (buf, "%s = 0x%08x\n", _string_, val); \
++}
++#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \
++static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
++ const char *buf, size_t count) \
++{ \
++ struct platform_device *platform_dev = container_of(_dev, struct platform_device, dev); \
++ dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); \
++ uint32_t val = simple_strtoul(buf, NULL, 16); \
++ dwc_otg_set_##_otg_attr_name_ (otg_dev->core_if, val); \
++ return count; \
++}
++
++#endif
++
++#define DWC_OTG_DEVICE_ATTR_BITFIELD_RW(_otg_attr_name_,_string_) \
++DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
++DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \
++DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store);
++
++#define DWC_OTG_DEVICE_ATTR_BITFIELD_RO(_otg_attr_name_,_string_) \
++DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
++DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL);
++
++#define DWC_OTG_DEVICE_ATTR_REG32_RW(_otg_attr_name_,_addr_,_string_) \
++DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
++DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \
++DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store);
++
++#define DWC_OTG_DEVICE_ATTR_REG32_RO(_otg_attr_name_,_addr_,_string_) \
++DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
++DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL);
++
++/** @name Functions for Show/Store of Attributes */
++/**@{*/
++
++/**
++ * Helper function returning the otg_device structure of the given device
++ */
++static dwc_otg_device_t *dwc_otg_drvdev(struct device *_dev)
++{
++ dwc_otg_device_t *otg_dev;
++ DWC_OTG_GETDRVDEV(otg_dev, _dev);
++ return otg_dev;
++}
++
++/**
++ * Show the register offset of the Register Access.
++ */
++static ssize_t regoffset_show(struct device *_dev,
++ struct device_attribute *attr, char *buf)
++{
++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
++ return snprintf(buf, sizeof("0xFFFFFFFF\n") + 1, "0x%08x\n",
++ otg_dev->os_dep.reg_offset);
++}
++
++/**
++ * Set the register offset for the next Register Access Read/Write
++ */
++static ssize_t regoffset_store(struct device *_dev,
++ struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
++ uint32_t offset = simple_strtoul(buf, NULL, 16);
++#if defined(LM_INTERFACE) || defined(PLATFORM_INTERFACE)
++ if (offset < SZ_256K) {
++#elif defined(PCI_INTERFACE)
++ if (offset < 0x00040000) {
++#endif
++ otg_dev->os_dep.reg_offset = offset;
++ } else {
++ dev_err(_dev, "invalid offset\n");
++ }
++
++ return count;
++}
++
++DEVICE_ATTR(regoffset, S_IRUGO | S_IWUSR, regoffset_show, regoffset_store);
++
++/**
++ * Show the value of the register at the offset in the reg_offset
++ * attribute.
++ */
++static ssize_t regvalue_show(struct device *_dev,
++ struct device_attribute *attr, char *buf)
++{
++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
++ uint32_t val;
++ volatile uint32_t *addr;
++
++ if (otg_dev->os_dep.reg_offset != 0xFFFFFFFF && 0 != otg_dev->os_dep.base) {
++ /* Calculate the address */
++ addr = (uint32_t *) (otg_dev->os_dep.reg_offset +
++ (uint8_t *) otg_dev->os_dep.base);
++ val = DWC_READ_REG32(addr);
++ return snprintf(buf,
++ sizeof("Reg@0xFFFFFFFF = 0xFFFFFFFF\n") + 1,
++ "Reg@0x%06x = 0x%08x\n", otg_dev->os_dep.reg_offset,
++ val);
++ } else {
++ dev_err(_dev, "Invalid offset (0x%0x)\n", otg_dev->os_dep.reg_offset);
++ return sprintf(buf, "invalid offset\n");
++ }
++}
++
++/**
++ * Store the value in the register at the offset in the reg_offset
++ * attribute.
++ *
++ */
++static ssize_t regvalue_store(struct device *_dev,
++ struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
++ volatile uint32_t *addr;
++ uint32_t val = simple_strtoul(buf, NULL, 16);
++ //dev_dbg(_dev, "Offset=0x%08x Val=0x%08x\n", otg_dev->reg_offset, val);
++ if (otg_dev->os_dep.reg_offset != 0xFFFFFFFF && 0 != otg_dev->os_dep.base) {
++ /* Calculate the address */
++ addr = (uint32_t *) (otg_dev->os_dep.reg_offset +
++ (uint8_t *) otg_dev->os_dep.base);
++ DWC_WRITE_REG32(addr, val);
++ } else {
++ dev_err(_dev, "Invalid Register Offset (0x%08x)\n",
++ otg_dev->os_dep.reg_offset);
++ }
++ return count;
++}
++
++DEVICE_ATTR(regvalue, S_IRUGO | S_IWUSR, regvalue_show, regvalue_store);
++
++/*
++ * Attributes
++ */
++DWC_OTG_DEVICE_ATTR_BITFIELD_RO(mode, "Mode");
++DWC_OTG_DEVICE_ATTR_BITFIELD_RW(hnpcapable, "HNPCapable");
++DWC_OTG_DEVICE_ATTR_BITFIELD_RW(srpcapable, "SRPCapable");
++DWC_OTG_DEVICE_ATTR_BITFIELD_RW(hsic_connect, "HSIC Connect");
++DWC_OTG_DEVICE_ATTR_BITFIELD_RW(inv_sel_hsic, "Invert Select HSIC");
++
++//DWC_OTG_DEVICE_ATTR_BITFIELD_RW(buspower,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode");
++//DWC_OTG_DEVICE_ATTR_BITFIELD_RW(bussuspend,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode");
++DWC_OTG_DEVICE_ATTR_BITFIELD_RO(busconnected, "Bus Connected");
++
++DWC_OTG_DEVICE_ATTR_REG32_RW(gotgctl, 0, "GOTGCTL");
++DWC_OTG_DEVICE_ATTR_REG32_RW(gusbcfg,
++ &(otg_dev->core_if->core_global_regs->gusbcfg),
++ "GUSBCFG");
++DWC_OTG_DEVICE_ATTR_REG32_RW(grxfsiz,
++ &(otg_dev->core_if->core_global_regs->grxfsiz),
++ "GRXFSIZ");
++DWC_OTG_DEVICE_ATTR_REG32_RW(gnptxfsiz,
++ &(otg_dev->core_if->core_global_regs->gnptxfsiz),
++ "GNPTXFSIZ");
++DWC_OTG_DEVICE_ATTR_REG32_RW(gpvndctl,
++ &(otg_dev->core_if->core_global_regs->gpvndctl),
++ "GPVNDCTL");
++DWC_OTG_DEVICE_ATTR_REG32_RW(ggpio,
++ &(otg_dev->core_if->core_global_regs->ggpio),
++ "GGPIO");
++DWC_OTG_DEVICE_ATTR_REG32_RW(guid, &(otg_dev->core_if->core_global_regs->guid),
++ "GUID");
++DWC_OTG_DEVICE_ATTR_REG32_RO(gsnpsid,
++ &(otg_dev->core_if->core_global_regs->gsnpsid),
++ "GSNPSID");
++DWC_OTG_DEVICE_ATTR_BITFIELD_RW(devspeed, "Device Speed");
++DWC_OTG_DEVICE_ATTR_BITFIELD_RO(enumspeed, "Device Enumeration Speed");
++
++DWC_OTG_DEVICE_ATTR_REG32_RO(hptxfsiz,
++ &(otg_dev->core_if->core_global_regs->hptxfsiz),
++ "HPTXFSIZ");
++DWC_OTG_DEVICE_ATTR_REG32_RW(hprt0, otg_dev->core_if->host_if->hprt0, "HPRT0");
++
++/**
++ * @todo Add code to initiate the HNP.
++ */
++/**
++ * Show the HNP status bit
++ */
++static ssize_t hnp_show(struct device *_dev,
++ struct device_attribute *attr, char *buf)
++{
++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
++ return sprintf(buf, "HstNegScs = 0x%x\n",
++ dwc_otg_get_hnpstatus(otg_dev->core_if));
++}
++
++/**
++ * Set the HNP Request bit
++ */
++static ssize_t hnp_store(struct device *_dev,
++ struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
++ uint32_t in = simple_strtoul(buf, NULL, 16);
++ dwc_otg_set_hnpreq(otg_dev->core_if, in);
++ return count;
++}
++
++DEVICE_ATTR(hnp, 0644, hnp_show, hnp_store);
++
++/**
++ * @todo Add code to initiate the SRP.
++ */
++/**
++ * Show the SRP status bit
++ */
++static ssize_t srp_show(struct device *_dev,
++ struct device_attribute *attr, char *buf)
++{
++#ifndef DWC_HOST_ONLY
++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
++ return sprintf(buf, "SesReqScs = 0x%x\n",
++ dwc_otg_get_srpstatus(otg_dev->core_if));
++#else
++ return sprintf(buf, "Host Only Mode!\n");
++#endif
++}
++
++/**
++ * Set the SRP Request bit
++ */
++static ssize_t srp_store(struct device *_dev,
++ struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++#ifndef DWC_HOST_ONLY
++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
++ dwc_otg_pcd_initiate_srp(otg_dev->pcd);
++#endif
++ return count;
++}
++
++DEVICE_ATTR(srp, 0644, srp_show, srp_store);
++
++/**
++ * @todo Need to do more for power on/off?
++ */
++/**
++ * Show the Bus Power status
++ */
++static ssize_t buspower_show(struct device *_dev,
++ struct device_attribute *attr, char *buf)
++{
++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
++ return sprintf(buf, "Bus Power = 0x%x\n",
++ dwc_otg_get_prtpower(otg_dev->core_if));
++}
++
++/**
++ * Set the Bus Power status
++ */
++static ssize_t buspower_store(struct device *_dev,
++ struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
++ uint32_t on = simple_strtoul(buf, NULL, 16);
++ dwc_otg_set_prtpower(otg_dev->core_if, on);
++ return count;
++}
++
++DEVICE_ATTR(buspower, 0644, buspower_show, buspower_store);
++
++/**
++ * @todo Need to do more for suspend?
++ */
++/**
++ * Show the Bus Suspend status
++ */
++static ssize_t bussuspend_show(struct device *_dev,
++ struct device_attribute *attr, char *buf)
++{
++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
++ return sprintf(buf, "Bus Suspend = 0x%x\n",
++ dwc_otg_get_prtsuspend(otg_dev->core_if));
++}
++
++/**
++ * Set the Bus Suspend status
++ */
++static ssize_t bussuspend_store(struct device *_dev,
++ struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
++ uint32_t in = simple_strtoul(buf, NULL, 16);
++ dwc_otg_set_prtsuspend(otg_dev->core_if, in);
++ return count;
++}
++
++DEVICE_ATTR(bussuspend, 0644, bussuspend_show, bussuspend_store);
++
++/**
++ * Show the Mode Change Ready Timer status
++ */
++static ssize_t mode_ch_tim_en_show(struct device *_dev,
++ struct device_attribute *attr, char *buf)
++{
++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
++ return sprintf(buf, "Mode Change Ready Timer Enable = 0x%x\n",
++ dwc_otg_get_mode_ch_tim(otg_dev->core_if));
++}
++
++/**
++ * Set the Mode Change Ready Timer status
++ */
++static ssize_t mode_ch_tim_en_store(struct device *_dev,
++ struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
++ uint32_t in = simple_strtoul(buf, NULL, 16);
++ dwc_otg_set_mode_ch_tim(otg_dev->core_if, in);
++ return count;
++}
++
++DEVICE_ATTR(mode_ch_tim_en, 0644, mode_ch_tim_en_show, mode_ch_tim_en_store);
++
++/**
++ * Show the value of HFIR Frame Interval bitfield
++ */
++static ssize_t fr_interval_show(struct device *_dev,
++ struct device_attribute *attr, char *buf)
++{
++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
++ return sprintf(buf, "Frame Interval = 0x%x\n",
++ dwc_otg_get_fr_interval(otg_dev->core_if));
++}
++
++/**
++ * Set the HFIR Frame Interval value
++ */
++static ssize_t fr_interval_store(struct device *_dev,
++ struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
++ uint32_t in = simple_strtoul(buf, NULL, 10);
++ dwc_otg_set_fr_interval(otg_dev->core_if, in);
++ return count;
++}
++
++DEVICE_ATTR(fr_interval, 0644, fr_interval_show, fr_interval_store);
++
++/**
++ * Show the status of Remote Wakeup.
++ */
++static ssize_t remote_wakeup_show(struct device *_dev,
++ struct device_attribute *attr, char *buf)
++{
++#ifndef DWC_HOST_ONLY
++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
++
++ return sprintf(buf,
++ "Remote Wakeup Sig = %d Enabled = %d LPM Remote Wakeup = %d\n",
++ dwc_otg_get_remotewakesig(otg_dev->core_if),
++ dwc_otg_pcd_get_rmwkup_enable(otg_dev->pcd),
++ dwc_otg_get_lpm_remotewakeenabled(otg_dev->core_if));
++#else
++ return sprintf(buf, "Host Only Mode!\n");
++#endif /* DWC_HOST_ONLY */
++}
++
++/**
++ * Initiate a remote wakeup of the host. The Device control register
++ * Remote Wakeup Signal bit is written if the PCD Remote wakeup enable
++ * flag is set.
++ *
++ */
++static ssize_t remote_wakeup_store(struct device *_dev,
++ struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++#ifndef DWC_HOST_ONLY
++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
++ uint32_t val = simple_strtoul(buf, NULL, 16);
++
++ if (val & 1) {
++ dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 1);
++ } else {
++ dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 0);
++ }
++#endif /* DWC_HOST_ONLY */
++ return count;
++}
++
++DEVICE_ATTR(remote_wakeup, S_IRUGO | S_IWUSR, remote_wakeup_show,
++ remote_wakeup_store);
++
++/**
++ * Show the whether core is hibernated or not.
++ */
++static ssize_t rem_wakeup_pwrdn_show(struct device *_dev,
++ struct device_attribute *attr, char *buf)
++{
++#ifndef DWC_HOST_ONLY
++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
++
++ if (dwc_otg_get_core_state(otg_dev->core_if)) {
++ DWC_PRINTF("Core is in hibernation\n");
++ } else {
++ DWC_PRINTF("Core is not in hibernation\n");
++ }
++#endif /* DWC_HOST_ONLY */
++ return 0;
++}
++
++extern int dwc_otg_device_hibernation_restore(dwc_otg_core_if_t * core_if,
++ int rem_wakeup, int reset);
++
++/**
++ * Initiate a remote wakeup of the device to exit from hibernation.
++ */
++static ssize_t rem_wakeup_pwrdn_store(struct device *_dev,
++ struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++#ifndef DWC_HOST_ONLY
++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
++ dwc_otg_device_hibernation_restore(otg_dev->core_if, 1, 0);
++#endif
++ return count;
++}
++
++DEVICE_ATTR(rem_wakeup_pwrdn, S_IRUGO | S_IWUSR, rem_wakeup_pwrdn_show,
++ rem_wakeup_pwrdn_store);
++
++static ssize_t disconnect_us(struct device *_dev,
++ struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++
++#ifndef DWC_HOST_ONLY
++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
++ uint32_t val = simple_strtoul(buf, NULL, 16);
++ DWC_PRINTF("The Passed value is %04x\n", val);
++
++ dwc_otg_pcd_disconnect_us(otg_dev->pcd, 50);
++
++#endif /* DWC_HOST_ONLY */
++ return count;
++}
++
++DEVICE_ATTR(disconnect_us, S_IWUSR, 0, disconnect_us);
++
++/**
++ * Dump global registers and either host or device registers (depending on the
++ * current mode of the core).
++ */
++static ssize_t regdump_show(struct device *_dev,
++ struct device_attribute *attr, char *buf)
++{
++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
++
++ dwc_otg_dump_global_registers(otg_dev->core_if);
++ if (dwc_otg_is_host_mode(otg_dev->core_if)) {
++ dwc_otg_dump_host_registers(otg_dev->core_if);
++ } else {
++ dwc_otg_dump_dev_registers(otg_dev->core_if);
++
++ }
++ return sprintf(buf, "Register Dump\n");
++}
++
++DEVICE_ATTR(regdump, S_IRUGO, regdump_show, 0);
++
++/**
++ * Dump global registers and either host or device registers (depending on the
++ * current mode of the core).
++ */
++static ssize_t spramdump_show(struct device *_dev,
++ struct device_attribute *attr, char *buf)
++{
++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
++
++ //dwc_otg_dump_spram(otg_dev->core_if);
++
++ return sprintf(buf, "SPRAM Dump\n");
++}
++
++DEVICE_ATTR(spramdump, S_IRUGO, spramdump_show, 0);
++
++/**
++ * Dump the current hcd state.
++ */
++static ssize_t hcddump_show(struct device *_dev,
++ struct device_attribute *attr, char *buf)
++{
++#ifndef DWC_DEVICE_ONLY
++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
++ dwc_otg_hcd_dump_state(otg_dev->hcd);
++#endif /* DWC_DEVICE_ONLY */
++ return sprintf(buf, "HCD Dump\n");
++}
++
++DEVICE_ATTR(hcddump, S_IRUGO, hcddump_show, 0);
++
++/**
++ * Dump the average frame remaining at SOF. This can be used to
++ * determine average interrupt latency. Frame remaining is also shown for
++ * start transfer and two additional sample points.
++ */
++static ssize_t hcd_frrem_show(struct device *_dev,
++ struct device_attribute *attr, char *buf)
++{
++#ifndef DWC_DEVICE_ONLY
++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
++
++ dwc_otg_hcd_dump_frrem(otg_dev->hcd);
++#endif /* DWC_DEVICE_ONLY */
++ return sprintf(buf, "HCD Dump Frame Remaining\n");
++}
++
++DEVICE_ATTR(hcd_frrem, S_IRUGO, hcd_frrem_show, 0);
++
++/**
++ * Displays the time required to read the GNPTXFSIZ register many times (the
++ * output shows the number of times the register is read).
++ */
++#define RW_REG_COUNT 10000000
++#define MSEC_PER_JIFFIE 1000/HZ
++static ssize_t rd_reg_test_show(struct device *_dev,
++ struct device_attribute *attr, char *buf)
++{
++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
++ int i;
++ int time;
++ int start_jiffies;
++
++ printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n",
++ HZ, MSEC_PER_JIFFIE, loops_per_jiffy);
++ start_jiffies = jiffies;
++ for (i = 0; i < RW_REG_COUNT; i++) {
++ dwc_otg_get_gnptxfsiz(otg_dev->core_if);
++ }
++ time = jiffies - start_jiffies;
++ return sprintf(buf,
++ "Time to read GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n",
++ RW_REG_COUNT, time * MSEC_PER_JIFFIE, time);
++}
++
++DEVICE_ATTR(rd_reg_test, S_IRUGO, rd_reg_test_show, 0);
++
++/**
++ * Displays the time required to write the GNPTXFSIZ register many times (the
++ * output shows the number of times the register is written).
++ */
++static ssize_t wr_reg_test_show(struct device *_dev,
++ struct device_attribute *attr, char *buf)
++{
++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
++ uint32_t reg_val;
++ int i;
++ int time;
++ int start_jiffies;
++
++ printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n",
++ HZ, MSEC_PER_JIFFIE, loops_per_jiffy);
++ reg_val = dwc_otg_get_gnptxfsiz(otg_dev->core_if);
++ start_jiffies = jiffies;
++ for (i = 0; i < RW_REG_COUNT; i++) {
++ dwc_otg_set_gnptxfsiz(otg_dev->core_if, reg_val);
++ }
++ time = jiffies - start_jiffies;
++ return sprintf(buf,
++ "Time to write GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n",
++ RW_REG_COUNT, time * MSEC_PER_JIFFIE, time);
++}
++
++DEVICE_ATTR(wr_reg_test, S_IRUGO, wr_reg_test_show, 0);
++
++#ifdef CONFIG_USB_DWC_OTG_LPM
++
++/**
++* Show the lpm_response attribute.
++*/
++static ssize_t lpmresp_show(struct device *_dev,
++ struct device_attribute *attr, char *buf)
++{
++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
++
++ if (!dwc_otg_get_param_lpm_enable(otg_dev->core_if))
++ return sprintf(buf, "** LPM is DISABLED **\n");
++
++ if (!dwc_otg_is_device_mode(otg_dev->core_if)) {
++ return sprintf(buf, "** Current mode is not device mode\n");
++ }
++ return sprintf(buf, "lpm_response = %d\n",
++ dwc_otg_get_lpmresponse(otg_dev->core_if));
++}
++
++/**
++* Store the lpm_response attribute.
++*/
++static ssize_t lpmresp_store(struct device *_dev,
++ struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
++ uint32_t val = simple_strtoul(buf, NULL, 16);
++
++ if (!dwc_otg_get_param_lpm_enable(otg_dev->core_if)) {
++ return 0;
++ }
++
++ if (!dwc_otg_is_device_mode(otg_dev->core_if)) {
++ return 0;
++ }
++
++ dwc_otg_set_lpmresponse(otg_dev->core_if, val);
++ return count;
++}
++
++DEVICE_ATTR(lpm_response, S_IRUGO | S_IWUSR, lpmresp_show, lpmresp_store);
++
++/**
++* Show the sleep_status attribute.
++*/
++static ssize_t sleepstatus_show(struct device *_dev,
++ struct device_attribute *attr, char *buf)
++{
++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
++ return sprintf(buf, "Sleep Status = %d\n",
++ dwc_otg_get_lpm_portsleepstatus(otg_dev->core_if));
++}
++
++/**
++ * Store the sleep_status attribure.
++ */
++static ssize_t sleepstatus_store(struct device *_dev,
++ struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
++ dwc_otg_core_if_t *core_if = otg_dev->core_if;
++
++ if (dwc_otg_get_lpm_portsleepstatus(otg_dev->core_if)) {
++ if (dwc_otg_is_host_mode(core_if)) {
++
++ DWC_PRINTF("Host initiated resume\n");
++ dwc_otg_set_prtresume(otg_dev->core_if, 1);
++ }
++ }
++
++ return count;
++}
++
++DEVICE_ATTR(sleep_status, S_IRUGO | S_IWUSR, sleepstatus_show,
++ sleepstatus_store);
++
++#endif /* CONFIG_USB_DWC_OTG_LPM_ENABLE */
++
++/**@}*/
++
++/**
++ * Create the device files
++ */
++void dwc_otg_attr_create(
++#ifdef LM_INTERFACE
++ struct lm_device *dev
++#elif defined(PCI_INTERFACE)
++ struct pci_dev *dev
++#elif defined(PLATFORM_INTERFACE)
++ struct platform_device *dev
++#endif
++ )
++{
++ int error;
++
++ error = device_create_file(&dev->dev, &dev_attr_regoffset);
++ error = device_create_file(&dev->dev, &dev_attr_regvalue);
++ error = device_create_file(&dev->dev, &dev_attr_mode);
++ error = device_create_file(&dev->dev, &dev_attr_hnpcapable);
++ error = device_create_file(&dev->dev, &dev_attr_srpcapable);
++ error = device_create_file(&dev->dev, &dev_attr_hsic_connect);
++ error = device_create_file(&dev->dev, &dev_attr_inv_sel_hsic);
++ error = device_create_file(&dev->dev, &dev_attr_hnp);
++ error = device_create_file(&dev->dev, &dev_attr_srp);
++ error = device_create_file(&dev->dev, &dev_attr_buspower);
++ error = device_create_file(&dev->dev, &dev_attr_bussuspend);
++ error = device_create_file(&dev->dev, &dev_attr_mode_ch_tim_en);
++ error = device_create_file(&dev->dev, &dev_attr_fr_interval);
++ error = device_create_file(&dev->dev, &dev_attr_busconnected);
++ error = device_create_file(&dev->dev, &dev_attr_gotgctl);
++ error = device_create_file(&dev->dev, &dev_attr_gusbcfg);
++ error = device_create_file(&dev->dev, &dev_attr_grxfsiz);
++ error = device_create_file(&dev->dev, &dev_attr_gnptxfsiz);
++ error = device_create_file(&dev->dev, &dev_attr_gpvndctl);
++ error = device_create_file(&dev->dev, &dev_attr_ggpio);
++ error = device_create_file(&dev->dev, &dev_attr_guid);
++ error = device_create_file(&dev->dev, &dev_attr_gsnpsid);
++ error = device_create_file(&dev->dev, &dev_attr_devspeed);
++ error = device_create_file(&dev->dev, &dev_attr_enumspeed);
++ error = device_create_file(&dev->dev, &dev_attr_hptxfsiz);
++ error = device_create_file(&dev->dev, &dev_attr_hprt0);
++ error = device_create_file(&dev->dev, &dev_attr_remote_wakeup);
++ error = device_create_file(&dev->dev, &dev_attr_rem_wakeup_pwrdn);
++ error = device_create_file(&dev->dev, &dev_attr_disconnect_us);
++ error = device_create_file(&dev->dev, &dev_attr_regdump);
++ error = device_create_file(&dev->dev, &dev_attr_spramdump);
++ error = device_create_file(&dev->dev, &dev_attr_hcddump);
++ error = device_create_file(&dev->dev, &dev_attr_hcd_frrem);
++ error = device_create_file(&dev->dev, &dev_attr_rd_reg_test);
++ error = device_create_file(&dev->dev, &dev_attr_wr_reg_test);
++#ifdef CONFIG_USB_DWC_OTG_LPM
++ error = device_create_file(&dev->dev, &dev_attr_lpm_response);
++ error = device_create_file(&dev->dev, &dev_attr_sleep_status);
++#endif
++}
++
++/**
++ * Remove the device files
++ */
++void dwc_otg_attr_remove(
++#ifdef LM_INTERFACE
++ struct lm_device *dev
++#elif defined(PCI_INTERFACE)
++ struct pci_dev *dev
++#elif defined(PLATFORM_INTERFACE)
++ struct platform_device *dev
++#endif
++ )
++{
++ device_remove_file(&dev->dev, &dev_attr_regoffset);
++ device_remove_file(&dev->dev, &dev_attr_regvalue);
++ device_remove_file(&dev->dev, &dev_attr_mode);
++ device_remove_file(&dev->dev, &dev_attr_hnpcapable);
++ device_remove_file(&dev->dev, &dev_attr_srpcapable);
++ device_remove_file(&dev->dev, &dev_attr_hsic_connect);
++ device_remove_file(&dev->dev, &dev_attr_inv_sel_hsic);
++ device_remove_file(&dev->dev, &dev_attr_hnp);
++ device_remove_file(&dev->dev, &dev_attr_srp);
++ device_remove_file(&dev->dev, &dev_attr_buspower);
++ device_remove_file(&dev->dev, &dev_attr_bussuspend);
++ device_remove_file(&dev->dev, &dev_attr_mode_ch_tim_en);
++ device_remove_file(&dev->dev, &dev_attr_fr_interval);
++ device_remove_file(&dev->dev, &dev_attr_busconnected);
++ device_remove_file(&dev->dev, &dev_attr_gotgctl);
++ device_remove_file(&dev->dev, &dev_attr_gusbcfg);
++ device_remove_file(&dev->dev, &dev_attr_grxfsiz);
++ device_remove_file(&dev->dev, &dev_attr_gnptxfsiz);
++ device_remove_file(&dev->dev, &dev_attr_gpvndctl);
++ device_remove_file(&dev->dev, &dev_attr_ggpio);
++ device_remove_file(&dev->dev, &dev_attr_guid);
++ device_remove_file(&dev->dev, &dev_attr_gsnpsid);
++ device_remove_file(&dev->dev, &dev_attr_devspeed);
++ device_remove_file(&dev->dev, &dev_attr_enumspeed);
++ device_remove_file(&dev->dev, &dev_attr_hptxfsiz);
++ device_remove_file(&dev->dev, &dev_attr_hprt0);
++ device_remove_file(&dev->dev, &dev_attr_remote_wakeup);
++ device_remove_file(&dev->dev, &dev_attr_rem_wakeup_pwrdn);
++ device_remove_file(&dev->dev, &dev_attr_disconnect_us);
++ device_remove_file(&dev->dev, &dev_attr_regdump);
++ device_remove_file(&dev->dev, &dev_attr_spramdump);
++ device_remove_file(&dev->dev, &dev_attr_hcddump);
++ device_remove_file(&dev->dev, &dev_attr_hcd_frrem);
++ device_remove_file(&dev->dev, &dev_attr_rd_reg_test);
++ device_remove_file(&dev->dev, &dev_attr_wr_reg_test);
++#ifdef CONFIG_USB_DWC_OTG_LPM
++ device_remove_file(&dev->dev, &dev_attr_lpm_response);
++ device_remove_file(&dev->dev, &dev_attr_sleep_status);
++#endif
++}
+diff -Nur linux-4.1.3/drivers/usb/host/dwc_otg/dwc_otg_attr.h linux-xbian-rpi/drivers/usb/host/dwc_otg/dwc_otg_attr.h
+--- linux-4.1.3/drivers/usb/host/dwc_otg/dwc_otg_attr.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/usb/host/dwc_otg/dwc_otg_attr.h 2015-07-28 01:20:58.445156473 +0200
+@@ -0,0 +1,89 @@
++/* ==========================================================================
++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_attr.h $
++ * $Revision: #13 $
++ * $Date: 2010/06/21 $
++ * $Change: 1532021 $
++ *
++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++ * otherwise expressly agreed to in writing between Synopsys and you.
++ *
++ * The Software IS NOT an item of Licensed Software or Licensed Product under
++ * any End User Software License Agreement or Agreement for Licensed Product
++ * with Synopsys or any supplement thereto. You are permitted to use and
++ * redistribute this Software in source and binary forms, with or without
++ * modification, provided that redistributions of source code must retain this
++ * notice. You may not view, use, disclose, copy or distribute this file or
++ * any information contained herein except pursuant to this license grant from
++ * Synopsys. If you do not agree with this notice, including the disclaimer
++ * below, then you are not authorized to use the Software.
++ *
++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++ * DAMAGE.
++ * ========================================================================== */
++
++#if !defined(__DWC_OTG_ATTR_H__)
++#define __DWC_OTG_ATTR_H__
++
++/** @file
++ * This file contains the interface to the Linux device attributes.
++ */
++extern struct device_attribute dev_attr_regoffset;
++extern struct device_attribute dev_attr_regvalue;
++
++extern struct device_attribute dev_attr_mode;
++extern struct device_attribute dev_attr_hnpcapable;
++extern struct device_attribute dev_attr_srpcapable;
++extern struct device_attribute dev_attr_hnp;
++extern struct device_attribute dev_attr_srp;
++extern struct device_attribute dev_attr_buspower;
++extern struct device_attribute dev_attr_bussuspend;
++extern struct device_attribute dev_attr_mode_ch_tim_en;
++extern struct device_attribute dev_attr_fr_interval;
++extern struct device_attribute dev_attr_busconnected;
++extern struct device_attribute dev_attr_gotgctl;
++extern struct device_attribute dev_attr_gusbcfg;
++extern struct device_attribute dev_attr_grxfsiz;
++extern struct device_attribute dev_attr_gnptxfsiz;
++extern struct device_attribute dev_attr_gpvndctl;
++extern struct device_attribute dev_attr_ggpio;
++extern struct device_attribute dev_attr_guid;
++extern struct device_attribute dev_attr_gsnpsid;
++extern struct device_attribute dev_attr_devspeed;
++extern struct device_attribute dev_attr_enumspeed;
++extern struct device_attribute dev_attr_hptxfsiz;
++extern struct device_attribute dev_attr_hprt0;
++#ifdef CONFIG_USB_DWC_OTG_LPM
++extern struct device_attribute dev_attr_lpm_response;
++extern struct device_attribute devi_attr_sleep_status;
++#endif
++
++void dwc_otg_attr_create(
++#ifdef LM_INTERFACE
++ struct lm_device *dev
++#elif defined(PCI_INTERFACE)
++ struct pci_dev *dev
++#elif defined(PLATFORM_INTERFACE)
++ struct platform_device *dev
++#endif
++ );
++
++void dwc_otg_attr_remove(
++#ifdef LM_INTERFACE
++ struct lm_device *dev
++#elif defined(PCI_INTERFACE)
++ struct pci_dev *dev
++#elif defined(PLATFORM_INTERFACE)
++ struct platform_device *dev
++#endif
++ );
++#endif
+diff -Nur linux-4.1.3/drivers/usb/host/dwc_otg/dwc_otg_cfi.c linux-xbian-rpi/drivers/usb/host/dwc_otg/dwc_otg_cfi.c
+--- linux-4.1.3/drivers/usb/host/dwc_otg/dwc_otg_cfi.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/usb/host/dwc_otg/dwc_otg_cfi.c 2015-07-28 01:20:58.445156473 +0200
+@@ -0,0 +1,1876 @@
++/* ==========================================================================
++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++ * otherwise expressly agreed to in writing between Synopsys and you.
++ *
++ * The Software IS NOT an item of Licensed Software or Licensed Product under
++ * any End User Software License Agreement or Agreement for Licensed Product
++ * with Synopsys or any supplement thereto. You are permitted to use and
++ * redistribute this Software in source and binary forms, with or without
++ * modification, provided that redistributions of source code must retain this
++ * notice. You may not view, use, disclose, copy or distribute this file or
++ * any information contained herein except pursuant to this license grant from
++ * Synopsys. If you do not agree with this notice, including the disclaimer
++ * below, then you are not authorized to use the Software.
++ *
++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++ * DAMAGE.
++ * ========================================================================== */
++
++/** @file
++ *
++ * This file contains the most of the CFI(Core Feature Interface)
++ * implementation for the OTG.
++ */
++
++#ifdef DWC_UTE_CFI
++
++#include "dwc_otg_pcd.h"
++#include "dwc_otg_cfi.h"
++
++/** This definition should actually migrate to the Portability Library */
++#define DWC_CONSTANT_CPU_TO_LE16(x) (x)
++
++extern dwc_otg_pcd_ep_t *get_ep_by_addr(dwc_otg_pcd_t * pcd, u16 wIndex);
++
++static int cfi_core_features_buf(uint8_t * buf, uint16_t buflen);
++static int cfi_get_feature_value(uint8_t * buf, uint16_t buflen,
++ struct dwc_otg_pcd *pcd,
++ struct cfi_usb_ctrlrequest *ctrl_req);
++static int cfi_set_feature_value(struct dwc_otg_pcd *pcd);
++static int cfi_ep_get_sg_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
++ struct cfi_usb_ctrlrequest *req);
++static int cfi_ep_get_concat_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
++ struct cfi_usb_ctrlrequest *req);
++static int cfi_ep_get_align_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
++ struct cfi_usb_ctrlrequest *req);
++static int cfi_preproc_reset(struct dwc_otg_pcd *pcd,
++ struct cfi_usb_ctrlrequest *req);
++static void cfi_free_ep_bs_dyn_data(cfi_ep_t * cfiep);
++
++static uint16_t get_dfifo_size(dwc_otg_core_if_t * core_if);
++static int32_t get_rxfifo_size(dwc_otg_core_if_t * core_if, uint16_t wValue);
++static int32_t get_txfifo_size(struct dwc_otg_pcd *pcd, uint16_t wValue);
++
++static uint8_t resize_fifos(dwc_otg_core_if_t * core_if);
++
++/** This is the header of the all features descriptor */
++static cfi_all_features_header_t all_props_desc_header = {
++ .wVersion = DWC_CONSTANT_CPU_TO_LE16(0x100),
++ .wCoreID = DWC_CONSTANT_CPU_TO_LE16(CFI_CORE_ID_OTG),
++ .wNumFeatures = DWC_CONSTANT_CPU_TO_LE16(9),
++};
++
++/** This is an array of statically allocated feature descriptors */
++static cfi_feature_desc_header_t prop_descs[] = {
++
++ /* FT_ID_DMA_MODE */
++ {
++ .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_MODE),
++ .bmAttributes = CFI_FEATURE_ATTR_RW,
++ .wDataLength = DWC_CONSTANT_CPU_TO_LE16(1),
++ },
++
++ /* FT_ID_DMA_BUFFER_SETUP */
++ {
++ .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_BUFFER_SETUP),
++ .bmAttributes = CFI_FEATURE_ATTR_RW,
++ .wDataLength = DWC_CONSTANT_CPU_TO_LE16(6),
++ },
++
++ /* FT_ID_DMA_BUFF_ALIGN */
++ {
++ .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_BUFF_ALIGN),
++ .bmAttributes = CFI_FEATURE_ATTR_RW,
++ .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2),
++ },
++
++ /* FT_ID_DMA_CONCAT_SETUP */
++ {
++ .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_CONCAT_SETUP),
++ .bmAttributes = CFI_FEATURE_ATTR_RW,
++ //.wDataLength = DWC_CONSTANT_CPU_TO_LE16(6),
++ },
++
++ /* FT_ID_DMA_CIRCULAR */
++ {
++ .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_CIRCULAR),
++ .bmAttributes = CFI_FEATURE_ATTR_RW,
++ .wDataLength = DWC_CONSTANT_CPU_TO_LE16(6),
++ },
++
++ /* FT_ID_THRESHOLD_SETUP */
++ {
++ .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_THRESHOLD_SETUP),
++ .bmAttributes = CFI_FEATURE_ATTR_RW,
++ .wDataLength = DWC_CONSTANT_CPU_TO_LE16(6),
++ },
++
++ /* FT_ID_DFIFO_DEPTH */
++ {
++ .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DFIFO_DEPTH),
++ .bmAttributes = CFI_FEATURE_ATTR_RO,
++ .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2),
++ },
++
++ /* FT_ID_TX_FIFO_DEPTH */
++ {
++ .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_TX_FIFO_DEPTH),
++ .bmAttributes = CFI_FEATURE_ATTR_RW,
++ .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2),
++ },
++
++ /* FT_ID_RX_FIFO_DEPTH */
++ {
++ .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_RX_FIFO_DEPTH),
++ .bmAttributes = CFI_FEATURE_ATTR_RW,
++ .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2),
++ }
++};
++
++/** The table of feature names */
++cfi_string_t prop_name_table[] = {
++ {FT_ID_DMA_MODE, "dma_mode"},
++ {FT_ID_DMA_BUFFER_SETUP, "buffer_setup"},
++ {FT_ID_DMA_BUFF_ALIGN, "buffer_align"},
++ {FT_ID_DMA_CONCAT_SETUP, "concat_setup"},
++ {FT_ID_DMA_CIRCULAR, "buffer_circular"},
++ {FT_ID_THRESHOLD_SETUP, "threshold_setup"},
++ {FT_ID_DFIFO_DEPTH, "dfifo_depth"},
++ {FT_ID_TX_FIFO_DEPTH, "txfifo_depth"},
++ {FT_ID_RX_FIFO_DEPTH, "rxfifo_depth"},
++ {}
++};
++
++/************************************************************************/
++
++/**
++ * Returns the name of the feature by its ID
++ * or NULL if no featute ID matches.
++ *
++ */
++const uint8_t *get_prop_name(uint16_t prop_id, int *len)
++{
++ cfi_string_t *pstr;
++ *len = 0;
++
++ for (pstr = prop_name_table; pstr && pstr->s; pstr++) {
++ if (pstr->id == prop_id) {
++ *len = DWC_STRLEN(pstr->s);
++ return pstr->s;
++ }
++ }
++ return NULL;
++}
++
++/**
++ * This function handles all CFI specific control requests.
++ *
++ * Return a negative value to stall the DCE.
++ */
++int cfi_setup(struct dwc_otg_pcd *pcd, struct cfi_usb_ctrlrequest *ctrl)
++{
++ int retval = 0;
++ dwc_otg_pcd_ep_t *ep = NULL;
++ cfiobject_t *cfi = pcd->cfi;
++ struct dwc_otg_core_if *coreif = GET_CORE_IF(pcd);
++ uint16_t wLen = DWC_LE16_TO_CPU(&ctrl->wLength);
++ uint16_t wValue = DWC_LE16_TO_CPU(&ctrl->wValue);
++ uint16_t wIndex = DWC_LE16_TO_CPU(&ctrl->wIndex);
++ uint32_t regaddr = 0;
++ uint32_t regval = 0;
++
++ /* Save this Control Request in the CFI object.
++ * The data field will be assigned in the data stage completion CB function.
++ */
++ cfi->ctrl_req = *ctrl;
++ cfi->ctrl_req.data = NULL;
++
++ cfi->need_gadget_att = 0;
++ cfi->need_status_in_complete = 0;
++
++ switch (ctrl->bRequest) {
++ case VEN_CORE_GET_FEATURES:
++ retval = cfi_core_features_buf(cfi->buf_in.buf, CFI_IN_BUF_LEN);
++ if (retval >= 0) {
++ //dump_msg(cfi->buf_in.buf, retval);
++ ep = &pcd->ep0;
++
++ retval = min((uint16_t) retval, wLen);
++ /* Transfer this buffer to the host through the EP0-IN EP */
++ ep->dwc_ep.dma_addr = cfi->buf_in.addr;
++ ep->dwc_ep.start_xfer_buff = cfi->buf_in.buf;
++ ep->dwc_ep.xfer_buff = cfi->buf_in.buf;
++ ep->dwc_ep.xfer_len = retval;
++ ep->dwc_ep.xfer_count = 0;
++ ep->dwc_ep.sent_zlp = 0;
++ ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
++
++ pcd->ep0_pending = 1;
++ dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);
++ }
++ retval = 0;
++ break;
++
++ case VEN_CORE_GET_FEATURE:
++ CFI_INFO("VEN_CORE_GET_FEATURE\n");
++ retval = cfi_get_feature_value(cfi->buf_in.buf, CFI_IN_BUF_LEN,
++ pcd, ctrl);
++ if (retval >= 0) {
++ ep = &pcd->ep0;
++
++ retval = min((uint16_t) retval, wLen);
++ /* Transfer this buffer to the host through the EP0-IN EP */
++ ep->dwc_ep.dma_addr = cfi->buf_in.addr;
++ ep->dwc_ep.start_xfer_buff = cfi->buf_in.buf;
++ ep->dwc_ep.xfer_buff = cfi->buf_in.buf;
++ ep->dwc_ep.xfer_len = retval;
++ ep->dwc_ep.xfer_count = 0;
++ ep->dwc_ep.sent_zlp = 0;
++ ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
++
++ pcd->ep0_pending = 1;
++ dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);
++ }
++ CFI_INFO("VEN_CORE_GET_FEATURE=%d\n", retval);
++ dump_msg(cfi->buf_in.buf, retval);
++ break;
++
++ case VEN_CORE_SET_FEATURE:
++ CFI_INFO("VEN_CORE_SET_FEATURE\n");
++ /* Set up an XFER to get the data stage of the control request,
++ * which is the new value of the feature to be modified.
++ */
++ ep = &pcd->ep0;
++ ep->dwc_ep.is_in = 0;
++ ep->dwc_ep.dma_addr = cfi->buf_out.addr;
++ ep->dwc_ep.start_xfer_buff = cfi->buf_out.buf;
++ ep->dwc_ep.xfer_buff = cfi->buf_out.buf;
++ ep->dwc_ep.xfer_len = wLen;
++ ep->dwc_ep.xfer_count = 0;
++ ep->dwc_ep.sent_zlp = 0;
++ ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
++
++ pcd->ep0_pending = 1;
++ /* Read the control write's data stage */
++ dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);
++ retval = 0;
++ break;
++
++ case VEN_CORE_RESET_FEATURES:
++ CFI_INFO("VEN_CORE_RESET_FEATURES\n");
++ cfi->need_gadget_att = 1;
++ cfi->need_status_in_complete = 1;
++ retval = cfi_preproc_reset(pcd, ctrl);
++ CFI_INFO("VEN_CORE_RESET_FEATURES = (%d)\n", retval);
++ break;
++
++ case VEN_CORE_ACTIVATE_FEATURES:
++ CFI_INFO("VEN_CORE_ACTIVATE_FEATURES\n");
++ break;
++
++ case VEN_CORE_READ_REGISTER:
++ CFI_INFO("VEN_CORE_READ_REGISTER\n");
++ /* wValue optionally contains the HI WORD of the register offset and
++ * wIndex contains the LOW WORD of the register offset
++ */
++ if (wValue == 0) {
++ /* @TODO - MAS - fix the access to the base field */
++ regaddr = 0;
++ //regaddr = (uint32_t) pcd->otg_dev->os_dep.base;
++ //GET_CORE_IF(pcd)->co
++ regaddr |= wIndex;
++ } else {
++ regaddr = (wValue << 16) | wIndex;
++ }
++
++ /* Read a 32-bit value of the memory at the regaddr */
++ regval = DWC_READ_REG32((uint32_t *) regaddr);
++
++ ep = &pcd->ep0;
++ dwc_memcpy(cfi->buf_in.buf, &regval, sizeof(uint32_t));
++ ep->dwc_ep.is_in = 1;
++ ep->dwc_ep.dma_addr = cfi->buf_in.addr;
++ ep->dwc_ep.start_xfer_buff = cfi->buf_in.buf;
++ ep->dwc_ep.xfer_buff = cfi->buf_in.buf;
++ ep->dwc_ep.xfer_len = wLen;
++ ep->dwc_ep.xfer_count = 0;
++ ep->dwc_ep.sent_zlp = 0;
++ ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
++
++ pcd->ep0_pending = 1;
++ dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);
++ cfi->need_gadget_att = 0;
++ retval = 0;
++ break;
++
++ case VEN_CORE_WRITE_REGISTER:
++ CFI_INFO("VEN_CORE_WRITE_REGISTER\n");
++ /* Set up an XFER to get the data stage of the control request,
++ * which is the new value of the register to be modified.
++ */
++ ep = &pcd->ep0;
++ ep->dwc_ep.is_in = 0;
++ ep->dwc_ep.dma_addr = cfi->buf_out.addr;
++ ep->dwc_ep.start_xfer_buff = cfi->buf_out.buf;
++ ep->dwc_ep.xfer_buff = cfi->buf_out.buf;
++ ep->dwc_ep.xfer_len = wLen;
++ ep->dwc_ep.xfer_count = 0;
++ ep->dwc_ep.sent_zlp = 0;
++ ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
++
++ pcd->ep0_pending = 1;
++ /* Read the control write's data stage */
++ dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);
++ retval = 0;
++ break;
++
++ default:
++ retval = -DWC_E_NOT_SUPPORTED;
++ break;
++ }
++
++ return retval;
++}
++
++/**
++ * This function prepares the core features descriptors and copies its
++ * raw representation into the buffer <buf>.
++ *
++ * The buffer structure is as follows:
++ * all_features_header (8 bytes)
++ * features_#1 (8 bytes + feature name string length)
++ * features_#2 (8 bytes + feature name string length)
++ * .....
++ * features_#n - where n=the total count of feature descriptors
++ */
++static int cfi_core_features_buf(uint8_t * buf, uint16_t buflen)
++{
++ cfi_feature_desc_header_t *prop_hdr = prop_descs;
++ cfi_feature_desc_header_t *prop;
++ cfi_all_features_header_t *all_props_hdr = &all_props_desc_header;
++ cfi_all_features_header_t *tmp;
++ uint8_t *tmpbuf = buf;
++ const uint8_t *pname = NULL;
++ int i, j, namelen = 0, totlen;
++
++ /* Prepare and copy the core features into the buffer */
++ CFI_INFO("%s:\n", __func__);
++
++ tmp = (cfi_all_features_header_t *) tmpbuf;
++ *tmp = *all_props_hdr;
++ tmpbuf += CFI_ALL_FEATURES_HDR_LEN;
++
++ j = sizeof(prop_descs) / sizeof(cfi_all_features_header_t);
++ for (i = 0; i < j; i++, prop_hdr++) {
++ pname = get_prop_name(prop_hdr->wFeatureID, &namelen);
++ prop = (cfi_feature_desc_header_t *) tmpbuf;
++ *prop = *prop_hdr;
++
++ prop->bNameLen = namelen;
++ prop->wLength =
++ DWC_CONSTANT_CPU_TO_LE16(CFI_FEATURE_DESC_HDR_LEN +
++ namelen);
++
++ tmpbuf += CFI_FEATURE_DESC_HDR_LEN;
++ dwc_memcpy(tmpbuf, pname, namelen);
++ tmpbuf += namelen;
++ }
++
++ totlen = tmpbuf - buf;
++
++ if (totlen > 0) {
++ tmp = (cfi_all_features_header_t *) buf;
++ tmp->wTotalLen = DWC_CONSTANT_CPU_TO_LE16(totlen);
++ }
++
++ return totlen;
++}
++
++/**
++ * This function releases all the dynamic memory in the CFI object.
++ */
++static void cfi_release(cfiobject_t * cfiobj)
++{
++ cfi_ep_t *cfiep;
++ dwc_list_link_t *tmp;
++
++ CFI_INFO("%s\n", __func__);
++
++ if (cfiobj->buf_in.buf) {
++ DWC_DMA_FREE(CFI_IN_BUF_LEN, cfiobj->buf_in.buf,
++ cfiobj->buf_in.addr);
++ cfiobj->buf_in.buf = NULL;
++ }
++
++ if (cfiobj->buf_out.buf) {
++ DWC_DMA_FREE(CFI_OUT_BUF_LEN, cfiobj->buf_out.buf,
++ cfiobj->buf_out.addr);
++ cfiobj->buf_out.buf = NULL;
++ }
++
++ /* Free the Buffer Setup values for each EP */
++ //list_for_each_entry(cfiep, &cfiobj->active_eps, lh) {
++ DWC_LIST_FOREACH(tmp, &cfiobj->active_eps) {
++ cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
++ cfi_free_ep_bs_dyn_data(cfiep);
++ }
++}
++
++/**
++ * This function frees the dynamically allocated EP buffer setup data.
++ */
++static void cfi_free_ep_bs_dyn_data(cfi_ep_t * cfiep)
++{
++ if (cfiep->bm_sg) {
++ DWC_FREE(cfiep->bm_sg);
++ cfiep->bm_sg = NULL;
++ }
++
++ if (cfiep->bm_align) {
++ DWC_FREE(cfiep->bm_align);
++ cfiep->bm_align = NULL;
++ }
++
++ if (cfiep->bm_concat) {
++ if (NULL != cfiep->bm_concat->wTxBytes) {
++ DWC_FREE(cfiep->bm_concat->wTxBytes);
++ cfiep->bm_concat->wTxBytes = NULL;
++ }
++ DWC_FREE(cfiep->bm_concat);
++ cfiep->bm_concat = NULL;
++ }
++}
++
++/**
++ * This function initializes the default values of the features
++ * for a specific endpoint and should be called only once when
++ * the EP is enabled first time.
++ */
++static int cfi_ep_init_defaults(struct dwc_otg_pcd *pcd, cfi_ep_t * cfiep)
++{
++ int retval = 0;
++
++ cfiep->bm_sg = DWC_ALLOC(sizeof(ddma_sg_buffer_setup_t));
++ if (NULL == cfiep->bm_sg) {
++ CFI_INFO("Failed to allocate memory for SG feature value\n");
++ return -DWC_E_NO_MEMORY;
++ }
++ dwc_memset(cfiep->bm_sg, 0, sizeof(ddma_sg_buffer_setup_t));
++
++ /* For the Concatenation feature's default value we do not allocate
++ * memory for the wTxBytes field - it will be done in the set_feature_value
++ * request handler.
++ */
++ cfiep->bm_concat = DWC_ALLOC(sizeof(ddma_concat_buffer_setup_t));
++ if (NULL == cfiep->bm_concat) {
++ CFI_INFO
++ ("Failed to allocate memory for CONCATENATION feature value\n");
++ DWC_FREE(cfiep->bm_sg);
++ return -DWC_E_NO_MEMORY;
++ }
++ dwc_memset(cfiep->bm_concat, 0, sizeof(ddma_concat_buffer_setup_t));
++
++ cfiep->bm_align = DWC_ALLOC(sizeof(ddma_align_buffer_setup_t));
++ if (NULL == cfiep->bm_align) {
++ CFI_INFO
++ ("Failed to allocate memory for Alignment feature value\n");
++ DWC_FREE(cfiep->bm_sg);
++ DWC_FREE(cfiep->bm_concat);
++ return -DWC_E_NO_MEMORY;
++ }
++ dwc_memset(cfiep->bm_align, 0, sizeof(ddma_align_buffer_setup_t));
++
++ return retval;
++}
++
++/**
++ * The callback function that notifies the CFI on the activation of
++ * an endpoint in the PCD. The following steps are done in this function:
++ *
++ * Create a dynamically allocated cfi_ep_t object (a CFI wrapper to the PCD's
++ * active endpoint)
++ * Create MAX_DMA_DESCS_PER_EP count DMA Descriptors for the EP
++ * Set the Buffer Mode to standard
++ * Initialize the default values for all EP modes (SG, Circular, Concat, Align)
++ * Add the cfi_ep_t object to the list of active endpoints in the CFI object
++ */
++static int cfi_ep_enable(struct cfiobject *cfi, struct dwc_otg_pcd *pcd,
++ struct dwc_otg_pcd_ep *ep)
++{
++ cfi_ep_t *cfiep;
++ int retval = -DWC_E_NOT_SUPPORTED;
++
++ CFI_INFO("%s: epname=%s; epnum=0x%02x\n", __func__,
++ "EP_" /*ep->ep.name */ , ep->desc->bEndpointAddress);
++ /* MAS - Check whether this endpoint already is in the list */
++ cfiep = get_cfi_ep_by_pcd_ep(cfi, ep);
++
++ if (NULL == cfiep) {
++ /* Allocate a cfi_ep_t object */
++ cfiep = DWC_ALLOC(sizeof(cfi_ep_t));
++ if (NULL == cfiep) {
++ CFI_INFO
++ ("Unable to allocate memory for <cfiep> in function %s\n",
++ __func__);
++ return -DWC_E_NO_MEMORY;
++ }
++ dwc_memset(cfiep, 0, sizeof(cfi_ep_t));
++
++ /* Save the dwc_otg_pcd_ep pointer in the cfiep object */
++ cfiep->ep = ep;
++
++ /* Allocate the DMA Descriptors chain of MAX_DMA_DESCS_PER_EP count */
++ ep->dwc_ep.descs =
++ DWC_DMA_ALLOC(MAX_DMA_DESCS_PER_EP *
++ sizeof(dwc_otg_dma_desc_t),
++ &ep->dwc_ep.descs_dma_addr);
++
++ if (NULL == ep->dwc_ep.descs) {
++ DWC_FREE(cfiep);
++ return -DWC_E_NO_MEMORY;
++ }
++
++ DWC_LIST_INIT(&cfiep->lh);
++
++ /* Set the buffer mode to BM_STANDARD. It will be modified
++ * when building descriptors for a specific buffer mode */
++ ep->dwc_ep.buff_mode = BM_STANDARD;
++
++ /* Create and initialize the default values for this EP's Buffer modes */
++ if ((retval = cfi_ep_init_defaults(pcd, cfiep)) < 0)
++ return retval;
++
++ /* Add the cfi_ep_t object to the CFI object's list of active endpoints */
++ DWC_LIST_INSERT_TAIL(&cfi->active_eps, &cfiep->lh);
++ retval = 0;
++ } else { /* The sought EP already is in the list */
++ CFI_INFO("%s: The sought EP already is in the list\n",
++ __func__);
++ }
++
++ return retval;
++}
++
++/**
++ * This function is called when the data stage of a 3-stage Control Write request
++ * is complete.
++ *
++ */
++static int cfi_ctrl_write_complete(struct cfiobject *cfi,
++ struct dwc_otg_pcd *pcd)
++{
++ uint32_t addr, reg_value;
++ uint16_t wIndex, wValue;
++ uint8_t bRequest;
++ uint8_t *buf = cfi->buf_out.buf;
++ //struct usb_ctrlrequest *ctrl_req = &cfi->ctrl_req_saved;
++ struct cfi_usb_ctrlrequest *ctrl_req = &cfi->ctrl_req;
++ int retval = -DWC_E_NOT_SUPPORTED;
++
++ CFI_INFO("%s\n", __func__);
++
++ bRequest = ctrl_req->bRequest;
++ wIndex = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wIndex);
++ wValue = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wValue);
++
++ /*
++ * Save the pointer to the data stage in the ctrl_req's <data> field.
++ * The request should be already saved in the command stage by now.
++ */
++ ctrl_req->data = cfi->buf_out.buf;
++ cfi->need_status_in_complete = 0;
++ cfi->need_gadget_att = 0;
++
++ switch (bRequest) {
++ case VEN_CORE_WRITE_REGISTER:
++ /* The buffer contains raw data of the new value for the register */
++ reg_value = *((uint32_t *) buf);
++ if (wValue == 0) {
++ addr = 0;
++ //addr = (uint32_t) pcd->otg_dev->os_dep.base;
++ addr += wIndex;
++ } else {
++ addr = (wValue << 16) | wIndex;
++ }
++
++ //writel(reg_value, addr);
++
++ retval = 0;
++ cfi->need_status_in_complete = 1;
++ break;
++
++ case VEN_CORE_SET_FEATURE:
++ /* The buffer contains raw data of the new value of the feature */
++ retval = cfi_set_feature_value(pcd);
++ if (retval < 0)
++ return retval;
++
++ cfi->need_status_in_complete = 1;
++ break;
++
++ default:
++ break;
++ }
++
++ return retval;
++}
++
++/**
++ * This function builds the DMA descriptors for the SG buffer mode.
++ */
++static void cfi_build_sg_descs(struct cfiobject *cfi, cfi_ep_t * cfiep,
++ dwc_otg_pcd_request_t * req)
++{
++ struct dwc_otg_pcd_ep *ep = cfiep->ep;
++ ddma_sg_buffer_setup_t *sgval = cfiep->bm_sg;
++ struct dwc_otg_dma_desc *desc = cfiep->ep->dwc_ep.descs;
++ struct dwc_otg_dma_desc *desc_last = cfiep->ep->dwc_ep.descs;
++ dma_addr_t buff_addr = req->dma;
++ int i;
++ uint32_t txsize, off;
++
++ txsize = sgval->wSize;
++ off = sgval->bOffset;
++
++// CFI_INFO("%s: %s TXSIZE=0x%08x; OFFSET=0x%08x\n",
++// __func__, cfiep->ep->ep.name, txsize, off);
++
++ for (i = 0; i < sgval->bCount; i++) {
++ desc->status.b.bs = BS_HOST_BUSY;
++ desc->buf = buff_addr;
++ desc->status.b.l = 0;
++ desc->status.b.ioc = 0;
++ desc->status.b.sp = 0;
++ desc->status.b.bytes = txsize;
++ desc->status.b.bs = BS_HOST_READY;
++
++ /* Set the next address of the buffer */
++ buff_addr += txsize + off;
++ desc_last = desc;
++ desc++;
++ }
++
++ /* Set the last, ioc and sp bits on the Last DMA Descriptor */
++ desc_last->status.b.l = 1;
++ desc_last->status.b.ioc = 1;
++ desc_last->status.b.sp = ep->dwc_ep.sent_zlp;
++ /* Save the last DMA descriptor pointer */
++ cfiep->dma_desc_last = desc_last;
++ cfiep->desc_count = sgval->bCount;
++}
++
++/**
++ * This function builds the DMA descriptors for the Concatenation buffer mode.
++ */
++static void cfi_build_concat_descs(struct cfiobject *cfi, cfi_ep_t * cfiep,
++ dwc_otg_pcd_request_t * req)
++{
++ struct dwc_otg_pcd_ep *ep = cfiep->ep;
++ ddma_concat_buffer_setup_t *concatval = cfiep->bm_concat;
++ struct dwc_otg_dma_desc *desc = cfiep->ep->dwc_ep.descs;
++ struct dwc_otg_dma_desc *desc_last = cfiep->ep->dwc_ep.descs;
++ dma_addr_t buff_addr = req->dma;
++ int i;
++ uint16_t *txsize;
++
++ txsize = concatval->wTxBytes;
++
++ for (i = 0; i < concatval->hdr.bDescCount; i++) {
++ desc->buf = buff_addr;
++ desc->status.b.bs = BS_HOST_BUSY;
++ desc->status.b.l = 0;
++ desc->status.b.ioc = 0;
++ desc->status.b.sp = 0;
++ desc->status.b.bytes = *txsize;
++ desc->status.b.bs = BS_HOST_READY;
++
++ txsize++;
++ /* Set the next address of the buffer */
++ buff_addr += UGETW(ep->desc->wMaxPacketSize);
++ desc_last = desc;
++ desc++;
++ }
++
++ /* Set the last, ioc and sp bits on the Last DMA Descriptor */
++ desc_last->status.b.l = 1;
++ desc_last->status.b.ioc = 1;
++ desc_last->status.b.sp = ep->dwc_ep.sent_zlp;
++ cfiep->dma_desc_last = desc_last;
++ cfiep->desc_count = concatval->hdr.bDescCount;
++}
++
++/**
++ * This function builds the DMA descriptors for the Circular buffer mode
++ */
++static void cfi_build_circ_descs(struct cfiobject *cfi, cfi_ep_t * cfiep,
++ dwc_otg_pcd_request_t * req)
++{
++ /* @todo: MAS - add implementation when this feature needs to be tested */
++}
++
++/**
++ * This function builds the DMA descriptors for the Alignment buffer mode
++ */
++static void cfi_build_align_descs(struct cfiobject *cfi, cfi_ep_t * cfiep,
++ dwc_otg_pcd_request_t * req)
++{
++ struct dwc_otg_pcd_ep *ep = cfiep->ep;
++ ddma_align_buffer_setup_t *alignval = cfiep->bm_align;
++ struct dwc_otg_dma_desc *desc = cfiep->ep->dwc_ep.descs;
++ dma_addr_t buff_addr = req->dma;
++
++ desc->status.b.bs = BS_HOST_BUSY;
++ desc->status.b.l = 1;
++ desc->status.b.ioc = 1;
++ desc->status.b.sp = ep->dwc_ep.sent_zlp;
++ desc->status.b.bytes = req->length;
++ /* Adjust the buffer alignment */
++ desc->buf = (buff_addr + alignval->bAlign);
++ desc->status.b.bs = BS_HOST_READY;
++ cfiep->dma_desc_last = desc;
++ cfiep->desc_count = 1;
++}
++
++/**
++ * This function builds the DMA descriptors chain for different modes of the
++ * buffer setup of an endpoint.
++ */
++static void cfi_build_descriptors(struct cfiobject *cfi,
++ struct dwc_otg_pcd *pcd,
++ struct dwc_otg_pcd_ep *ep,
++ dwc_otg_pcd_request_t * req)
++{
++ cfi_ep_t *cfiep;
++
++ /* Get the cfiep by the dwc_otg_pcd_ep */
++ cfiep = get_cfi_ep_by_pcd_ep(cfi, ep);
++ if (NULL == cfiep) {
++ CFI_INFO("%s: Unable to find a matching active endpoint\n",
++ __func__);
++ return;
++ }
++
++ cfiep->xfer_len = req->length;
++
++ /* Iterate through all the DMA descriptors */
++ switch (cfiep->ep->dwc_ep.buff_mode) {
++ case BM_SG:
++ cfi_build_sg_descs(cfi, cfiep, req);
++ break;
++
++ case BM_CONCAT:
++ cfi_build_concat_descs(cfi, cfiep, req);
++ break;
++
++ case BM_CIRCULAR:
++ cfi_build_circ_descs(cfi, cfiep, req);
++ break;
++
++ case BM_ALIGN:
++ cfi_build_align_descs(cfi, cfiep, req);
++ break;
++
++ default:
++ break;
++ }
++}
++
++/**
++ * Allocate DMA buffer for different Buffer modes.
++ */
++static void *cfi_ep_alloc_buf(struct cfiobject *cfi, struct dwc_otg_pcd *pcd,
++ struct dwc_otg_pcd_ep *ep, dma_addr_t * dma,
++ unsigned size, gfp_t flags)
++{
++ return DWC_DMA_ALLOC(size, dma);
++}
++
++/**
++ * This function initializes the CFI object.
++ */
++int init_cfi(cfiobject_t * cfiobj)
++{
++ CFI_INFO("%s\n", __func__);
++
++ /* Allocate a buffer for IN XFERs */
++ cfiobj->buf_in.buf =
++ DWC_DMA_ALLOC(CFI_IN_BUF_LEN, &cfiobj->buf_in.addr);
++ if (NULL == cfiobj->buf_in.buf) {
++ CFI_INFO("Unable to allocate buffer for INs\n");
++ return -DWC_E_NO_MEMORY;
++ }
++
++ /* Allocate a buffer for OUT XFERs */
++ cfiobj->buf_out.buf =
++ DWC_DMA_ALLOC(CFI_OUT_BUF_LEN, &cfiobj->buf_out.addr);
++ if (NULL == cfiobj->buf_out.buf) {
++ CFI_INFO("Unable to allocate buffer for OUT\n");
++ return -DWC_E_NO_MEMORY;
++ }
++
++ /* Initialize the callback function pointers */
++ cfiobj->ops.release = cfi_release;
++ cfiobj->ops.ep_enable = cfi_ep_enable;
++ cfiobj->ops.ctrl_write_complete = cfi_ctrl_write_complete;
++ cfiobj->ops.build_descriptors = cfi_build_descriptors;
++ cfiobj->ops.ep_alloc_buf = cfi_ep_alloc_buf;
++
++ /* Initialize the list of active endpoints in the CFI object */
++ DWC_LIST_INIT(&cfiobj->active_eps);
++
++ return 0;
++}
++
++/**
++ * This function reads the required feature's current value into the buffer
++ *
++ * @retval: Returns negative as error, or the data length of the feature
++ */
++static int cfi_get_feature_value(uint8_t * buf, uint16_t buflen,
++ struct dwc_otg_pcd *pcd,
++ struct cfi_usb_ctrlrequest *ctrl_req)
++{
++ int retval = -DWC_E_NOT_SUPPORTED;
++ struct dwc_otg_core_if *coreif = GET_CORE_IF(pcd);
++ uint16_t dfifo, rxfifo, txfifo;
++
++ switch (ctrl_req->wIndex) {
++ /* Whether the DDMA is enabled or not */
++ case FT_ID_DMA_MODE:
++ *buf = (coreif->dma_enable && coreif->dma_desc_enable) ? 1 : 0;
++ retval = 1;
++ break;
++
++ case FT_ID_DMA_BUFFER_SETUP:
++ retval = cfi_ep_get_sg_val(buf, pcd, ctrl_req);
++ break;
++
++ case FT_ID_DMA_BUFF_ALIGN:
++ retval = cfi_ep_get_align_val(buf, pcd, ctrl_req);
++ break;
++
++ case FT_ID_DMA_CONCAT_SETUP:
++ retval = cfi_ep_get_concat_val(buf, pcd, ctrl_req);
++ break;
++
++ case FT_ID_DMA_CIRCULAR:
++ CFI_INFO("GetFeature value (FT_ID_DMA_CIRCULAR)\n");
++ break;
++
++ case FT_ID_THRESHOLD_SETUP:
++ CFI_INFO("GetFeature value (FT_ID_THRESHOLD_SETUP)\n");
++ break;
++
++ case FT_ID_DFIFO_DEPTH:
++ dfifo = get_dfifo_size(coreif);
++ *((uint16_t *) buf) = dfifo;
++ retval = sizeof(uint16_t);
++ break;
++
++ case FT_ID_TX_FIFO_DEPTH:
++ retval = get_txfifo_size(pcd, ctrl_req->wValue);
++ if (retval >= 0) {
++ txfifo = retval;
++ *((uint16_t *) buf) = txfifo;
++ retval = sizeof(uint16_t);
++ }
++ break;
++
++ case FT_ID_RX_FIFO_DEPTH:
++ retval = get_rxfifo_size(coreif, ctrl_req->wValue);
++ if (retval >= 0) {
++ rxfifo = retval;
++ *((uint16_t *) buf) = rxfifo;
++ retval = sizeof(uint16_t);
++ }
++ break;
++ }
++
++ return retval;
++}
++
++/**
++ * This function resets the SG for the specified EP to its default value
++ */
++static int cfi_reset_sg_val(cfi_ep_t * cfiep)
++{
++ dwc_memset(cfiep->bm_sg, 0, sizeof(ddma_sg_buffer_setup_t));
++ return 0;
++}
++
++/**
++ * This function resets the Alignment for the specified EP to its default value
++ */
++static int cfi_reset_align_val(cfi_ep_t * cfiep)
++{
++ dwc_memset(cfiep->bm_sg, 0, sizeof(ddma_sg_buffer_setup_t));
++ return 0;
++}
++
++/**
++ * This function resets the Concatenation for the specified EP to its default value
++ * This function will also set the value of the wTxBytes field to NULL after
++ * freeing the memory previously allocated for this field.
++ */
++static int cfi_reset_concat_val(cfi_ep_t * cfiep)
++{
++ /* First we need to free the wTxBytes field */
++ if (cfiep->bm_concat->wTxBytes) {
++ DWC_FREE(cfiep->bm_concat->wTxBytes);
++ cfiep->bm_concat->wTxBytes = NULL;
++ }
++
++ dwc_memset(cfiep->bm_concat, 0, sizeof(ddma_concat_buffer_setup_t));
++ return 0;
++}
++
++/**
++ * This function resets all the buffer setups of the specified endpoint
++ */
++static int cfi_ep_reset_all_setup_vals(cfi_ep_t * cfiep)
++{
++ cfi_reset_sg_val(cfiep);
++ cfi_reset_align_val(cfiep);
++ cfi_reset_concat_val(cfiep);
++ return 0;
++}
++
++static int cfi_handle_reset_fifo_val(struct dwc_otg_pcd *pcd, uint8_t ep_addr,
++ uint8_t rx_rst, uint8_t tx_rst)
++{
++ int retval = -DWC_E_INVALID;
++ uint16_t tx_siz[15];
++ uint16_t rx_siz = 0;
++ dwc_otg_pcd_ep_t *ep = NULL;
++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++ dwc_otg_core_params_t *params = GET_CORE_IF(pcd)->core_params;
++
++ if (rx_rst) {
++ rx_siz = params->dev_rx_fifo_size;
++ params->dev_rx_fifo_size = GET_CORE_IF(pcd)->init_rxfsiz;
++ }
++
++ if (tx_rst) {
++ if (ep_addr == 0) {
++ int i;
++
++ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
++ tx_siz[i] =
++ core_if->core_params->dev_tx_fifo_size[i];
++ core_if->core_params->dev_tx_fifo_size[i] =
++ core_if->init_txfsiz[i];
++ }
++ } else {
++
++ ep = get_ep_by_addr(pcd, ep_addr);
++
++ if (NULL == ep) {
++ CFI_INFO
++ ("%s: Unable to get the endpoint addr=0x%02x\n",
++ __func__, ep_addr);
++ return -DWC_E_INVALID;
++ }
++
++ tx_siz[0] =
++ params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num -
++ 1];
++ params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1] =
++ GET_CORE_IF(pcd)->init_txfsiz[ep->
++ dwc_ep.tx_fifo_num -
++ 1];
++ }
++ }
++
++ if (resize_fifos(GET_CORE_IF(pcd))) {
++ retval = 0;
++ } else {
++ CFI_INFO
++ ("%s: Error resetting the feature Reset All(FIFO size)\n",
++ __func__);
++ if (rx_rst) {
++ params->dev_rx_fifo_size = rx_siz;
++ }
++
++ if (tx_rst) {
++ if (ep_addr == 0) {
++ int i;
++ for (i = 0; i < core_if->hwcfg4.b.num_in_eps;
++ i++) {
++ core_if->
++ core_params->dev_tx_fifo_size[i] =
++ tx_siz[i];
++ }
++ } else {
++ params->dev_tx_fifo_size[ep->
++ dwc_ep.tx_fifo_num -
++ 1] = tx_siz[0];
++ }
++ }
++ retval = -DWC_E_INVALID;
++ }
++ return retval;
++}
++
++static int cfi_handle_reset_all(struct dwc_otg_pcd *pcd, uint8_t addr)
++{
++ int retval = 0;
++ cfi_ep_t *cfiep;
++ cfiobject_t *cfi = pcd->cfi;
++ dwc_list_link_t *tmp;
++
++ retval = cfi_handle_reset_fifo_val(pcd, addr, 1, 1);
++ if (retval < 0) {
++ return retval;
++ }
++
++ /* If the EP address is known then reset the features for only that EP */
++ if (addr) {
++ cfiep = get_cfi_ep_by_addr(pcd->cfi, addr);
++ if (NULL == cfiep) {
++ CFI_INFO("%s: Error getting the EP address 0x%02x\n",
++ __func__, addr);
++ return -DWC_E_INVALID;
++ }
++ retval = cfi_ep_reset_all_setup_vals(cfiep);
++ cfiep->ep->dwc_ep.buff_mode = BM_STANDARD;
++ }
++ /* Otherwise (wValue == 0), reset all features of all EP's */
++ else {
++ /* Traverse all the active EP's and reset the feature(s) value(s) */
++ //list_for_each_entry(cfiep, &cfi->active_eps, lh) {
++ DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
++ cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
++ retval = cfi_ep_reset_all_setup_vals(cfiep);
++ cfiep->ep->dwc_ep.buff_mode = BM_STANDARD;
++ if (retval < 0) {
++ CFI_INFO
++ ("%s: Error resetting the feature Reset All\n",
++ __func__);
++ return retval;
++ }
++ }
++ }
++ return retval;
++}
++
++static int cfi_handle_reset_dma_buff_setup(struct dwc_otg_pcd *pcd,
++ uint8_t addr)
++{
++ int retval = 0;
++ cfi_ep_t *cfiep;
++ cfiobject_t *cfi = pcd->cfi;
++ dwc_list_link_t *tmp;
++
++ /* If the EP address is known then reset the features for only that EP */
++ if (addr) {
++ cfiep = get_cfi_ep_by_addr(pcd->cfi, addr);
++ if (NULL == cfiep) {
++ CFI_INFO("%s: Error getting the EP address 0x%02x\n",
++ __func__, addr);
++ return -DWC_E_INVALID;
++ }
++ retval = cfi_reset_sg_val(cfiep);
++ }
++ /* Otherwise (wValue == 0), reset all features of all EP's */
++ else {
++ /* Traverse all the active EP's and reset the feature(s) value(s) */
++ //list_for_each_entry(cfiep, &cfi->active_eps, lh) {
++ DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
++ cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
++ retval = cfi_reset_sg_val(cfiep);
++ if (retval < 0) {
++ CFI_INFO
++ ("%s: Error resetting the feature Buffer Setup\n",
++ __func__);
++ return retval;
++ }
++ }
++ }
++ return retval;
++}
++
++static int cfi_handle_reset_concat_val(struct dwc_otg_pcd *pcd, uint8_t addr)
++{
++ int retval = 0;
++ cfi_ep_t *cfiep;
++ cfiobject_t *cfi = pcd->cfi;
++ dwc_list_link_t *tmp;
++
++ /* If the EP address is known then reset the features for only that EP */
++ if (addr) {
++ cfiep = get_cfi_ep_by_addr(pcd->cfi, addr);
++ if (NULL == cfiep) {
++ CFI_INFO("%s: Error getting the EP address 0x%02x\n",
++ __func__, addr);
++ return -DWC_E_INVALID;
++ }
++ retval = cfi_reset_concat_val(cfiep);
++ }
++ /* Otherwise (wValue == 0), reset all features of all EP's */
++ else {
++ /* Traverse all the active EP's and reset the feature(s) value(s) */
++ //list_for_each_entry(cfiep, &cfi->active_eps, lh) {
++ DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
++ cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
++ retval = cfi_reset_concat_val(cfiep);
++ if (retval < 0) {
++ CFI_INFO
++ ("%s: Error resetting the feature Concatenation Value\n",
++ __func__);
++ return retval;
++ }
++ }
++ }
++ return retval;
++}
++
++static int cfi_handle_reset_align_val(struct dwc_otg_pcd *pcd, uint8_t addr)
++{
++ int retval = 0;
++ cfi_ep_t *cfiep;
++ cfiobject_t *cfi = pcd->cfi;
++ dwc_list_link_t *tmp;
++
++ /* If the EP address is known then reset the features for only that EP */
++ if (addr) {
++ cfiep = get_cfi_ep_by_addr(pcd->cfi, addr);
++ if (NULL == cfiep) {
++ CFI_INFO("%s: Error getting the EP address 0x%02x\n",
++ __func__, addr);
++ return -DWC_E_INVALID;
++ }
++ retval = cfi_reset_align_val(cfiep);
++ }
++ /* Otherwise (wValue == 0), reset all features of all EP's */
++ else {
++ /* Traverse all the active EP's and reset the feature(s) value(s) */
++ //list_for_each_entry(cfiep, &cfi->active_eps, lh) {
++ DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
++ cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
++ retval = cfi_reset_align_val(cfiep);
++ if (retval < 0) {
++ CFI_INFO
++ ("%s: Error resetting the feature Aliignment Value\n",
++ __func__);
++ return retval;
++ }
++ }
++ }
++ return retval;
++
++}
++
++static int cfi_preproc_reset(struct dwc_otg_pcd *pcd,
++ struct cfi_usb_ctrlrequest *req)
++{
++ int retval = 0;
++
++ switch (req->wIndex) {
++ case 0:
++ /* Reset all features */
++ retval = cfi_handle_reset_all(pcd, req->wValue & 0xff);
++ break;
++
++ case FT_ID_DMA_BUFFER_SETUP:
++ /* Reset the SG buffer setup */
++ retval =
++ cfi_handle_reset_dma_buff_setup(pcd, req->wValue & 0xff);
++ break;
++
++ case FT_ID_DMA_CONCAT_SETUP:
++ /* Reset the Concatenation buffer setup */
++ retval = cfi_handle_reset_concat_val(pcd, req->wValue & 0xff);
++ break;
++
++ case FT_ID_DMA_BUFF_ALIGN:
++ /* Reset the Alignment buffer setup */
++ retval = cfi_handle_reset_align_val(pcd, req->wValue & 0xff);
++ break;
++
++ case FT_ID_TX_FIFO_DEPTH:
++ retval =
++ cfi_handle_reset_fifo_val(pcd, req->wValue & 0xff, 0, 1);
++ pcd->cfi->need_gadget_att = 0;
++ break;
++
++ case FT_ID_RX_FIFO_DEPTH:
++ retval = cfi_handle_reset_fifo_val(pcd, 0, 1, 0);
++ pcd->cfi->need_gadget_att = 0;
++ break;
++ default:
++ break;
++ }
++ return retval;
++}
++
++/**
++ * This function sets a new value for the SG buffer setup.
++ */
++static int cfi_ep_set_sg_val(uint8_t * buf, struct dwc_otg_pcd *pcd)
++{
++ uint8_t inaddr, outaddr;
++ cfi_ep_t *epin, *epout;
++ ddma_sg_buffer_setup_t *psgval;
++ uint32_t desccount, size;
++
++ CFI_INFO("%s\n", __func__);
++
++ psgval = (ddma_sg_buffer_setup_t *) buf;
++ desccount = (uint32_t) psgval->bCount;
++ size = (uint32_t) psgval->wSize;
++
++ /* Check the DMA descriptor count */
++ if ((desccount > MAX_DMA_DESCS_PER_EP) || (desccount == 0)) {
++ CFI_INFO
++ ("%s: The count of DMA Descriptors should be between 1 and %d\n",
++ __func__, MAX_DMA_DESCS_PER_EP);
++ return -DWC_E_INVALID;
++ }
++
++ /* Check the DMA descriptor count */
++
++ if (size == 0) {
++
++ CFI_INFO("%s: The transfer size should be at least 1 byte\n",
++ __func__);
++
++ return -DWC_E_INVALID;
++
++ }
++
++ inaddr = psgval->bInEndpointAddress;
++ outaddr = psgval->bOutEndpointAddress;
++
++ epin = get_cfi_ep_by_addr(pcd->cfi, inaddr);
++ epout = get_cfi_ep_by_addr(pcd->cfi, outaddr);
++
++ if (NULL == epin || NULL == epout) {
++ CFI_INFO
++ ("%s: Unable to get the endpoints inaddr=0x%02x outaddr=0x%02x\n",
++ __func__, inaddr, outaddr);
++ return -DWC_E_INVALID;
++ }
++
++ epin->ep->dwc_ep.buff_mode = BM_SG;
++ dwc_memcpy(epin->bm_sg, psgval, sizeof(ddma_sg_buffer_setup_t));
++
++ epout->ep->dwc_ep.buff_mode = BM_SG;
++ dwc_memcpy(epout->bm_sg, psgval, sizeof(ddma_sg_buffer_setup_t));
++
++ return 0;
++}
++
++/**
++ * This function sets a new value for the buffer Alignment setup.
++ */
++static int cfi_ep_set_alignment_val(uint8_t * buf, struct dwc_otg_pcd *pcd)
++{
++ cfi_ep_t *ep;
++ uint8_t addr;
++ ddma_align_buffer_setup_t *palignval;
++
++ palignval = (ddma_align_buffer_setup_t *) buf;
++ addr = palignval->bEndpointAddress;
++
++ ep = get_cfi_ep_by_addr(pcd->cfi, addr);
++
++ if (NULL == ep) {
++ CFI_INFO("%s: Unable to get the endpoint addr=0x%02x\n",
++ __func__, addr);
++ return -DWC_E_INVALID;
++ }
++
++ ep->ep->dwc_ep.buff_mode = BM_ALIGN;
++ dwc_memcpy(ep->bm_align, palignval, sizeof(ddma_align_buffer_setup_t));
++
++ return 0;
++}
++
++/**
++ * This function sets a new value for the Concatenation buffer setup.
++ */
++static int cfi_ep_set_concat_val(uint8_t * buf, struct dwc_otg_pcd *pcd)
++{
++ uint8_t addr;
++ cfi_ep_t *ep;
++ struct _ddma_concat_buffer_setup_hdr *pConcatValHdr;
++ uint16_t *pVals;
++ uint32_t desccount;
++ int i;
++ uint16_t mps;
++
++ pConcatValHdr = (struct _ddma_concat_buffer_setup_hdr *)buf;
++ desccount = (uint32_t) pConcatValHdr->bDescCount;
++ pVals = (uint16_t *) (buf + BS_CONCAT_VAL_HDR_LEN);
++
++ /* Check the DMA descriptor count */
++ if (desccount > MAX_DMA_DESCS_PER_EP) {
++ CFI_INFO("%s: Maximum DMA Descriptor count should be %d\n",
++ __func__, MAX_DMA_DESCS_PER_EP);
++ return -DWC_E_INVALID;
++ }
++
++ addr = pConcatValHdr->bEndpointAddress;
++ ep = get_cfi_ep_by_addr(pcd->cfi, addr);
++ if (NULL == ep) {
++ CFI_INFO("%s: Unable to get the endpoint addr=0x%02x\n",
++ __func__, addr);
++ return -DWC_E_INVALID;
++ }
++
++ mps = UGETW(ep->ep->desc->wMaxPacketSize);
++
++#if 0
++ for (i = 0; i < desccount; i++) {
++ CFI_INFO("%s: wTxSize[%d]=0x%04x\n", __func__, i, pVals[i]);
++ }
++ CFI_INFO("%s: epname=%s; mps=%d\n", __func__, ep->ep->ep.name, mps);
++#endif
++
++ /* Check the wTxSizes to be less than or equal to the mps */
++ for (i = 0; i < desccount; i++) {
++ if (pVals[i] > mps) {
++ CFI_INFO
++ ("%s: ERROR - the wTxSize[%d] should be <= MPS (wTxSize=%d)\n",
++ __func__, i, pVals[i]);
++ return -DWC_E_INVALID;
++ }
++ }
++
++ ep->ep->dwc_ep.buff_mode = BM_CONCAT;
++ dwc_memcpy(ep->bm_concat, pConcatValHdr, BS_CONCAT_VAL_HDR_LEN);
++
++ /* Free the previously allocated storage for the wTxBytes */
++ if (ep->bm_concat->wTxBytes) {
++ DWC_FREE(ep->bm_concat->wTxBytes);
++ }
++
++ /* Allocate a new storage for the wTxBytes field */
++ ep->bm_concat->wTxBytes =
++ DWC_ALLOC(sizeof(uint16_t) * pConcatValHdr->bDescCount);
++ if (NULL == ep->bm_concat->wTxBytes) {
++ CFI_INFO("%s: Unable to allocate memory\n", __func__);
++ return -DWC_E_NO_MEMORY;
++ }
++
++ /* Copy the new values into the wTxBytes filed */
++ dwc_memcpy(ep->bm_concat->wTxBytes, buf + BS_CONCAT_VAL_HDR_LEN,
++ sizeof(uint16_t) * pConcatValHdr->bDescCount);
++
++ return 0;
++}
++
++/**
++ * This function calculates the total of all FIFO sizes
++ *
++ * @param core_if Programming view of DWC_otg controller
++ *
++ * @return The total of data FIFO sizes.
++ *
++ */
++static uint16_t get_dfifo_size(dwc_otg_core_if_t * core_if)
++{
++ dwc_otg_core_params_t *params = core_if->core_params;
++ uint16_t dfifo_total = 0;
++ int i;
++
++ /* The shared RxFIFO size */
++ dfifo_total =
++ params->dev_rx_fifo_size + params->dev_nperio_tx_fifo_size;
++
++ /* Add up each TxFIFO size to the total */
++ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
++ dfifo_total += params->dev_tx_fifo_size[i];
++ }
++
++ return dfifo_total;
++}
++
++/**
++ * This function returns Rx FIFO size
++ *
++ * @param core_if Programming view of DWC_otg controller
++ *
++ * @return The total of data FIFO sizes.
++ *
++ */
++static int32_t get_rxfifo_size(dwc_otg_core_if_t * core_if, uint16_t wValue)
++{
++ switch (wValue >> 8) {
++ case 0:
++ return (core_if->pwron_rxfsiz <
++ 32768) ? core_if->pwron_rxfsiz : 32768;
++ break;
++ case 1:
++ return core_if->core_params->dev_rx_fifo_size;
++ break;
++ default:
++ return -DWC_E_INVALID;
++ break;
++ }
++}
++
++/**
++ * This function returns Tx FIFO size for IN EP
++ *
++ * @param core_if Programming view of DWC_otg controller
++ *
++ * @return The total of data FIFO sizes.
++ *
++ */
++static int32_t get_txfifo_size(struct dwc_otg_pcd *pcd, uint16_t wValue)
++{
++ dwc_otg_pcd_ep_t *ep;
++
++ ep = get_ep_by_addr(pcd, wValue & 0xff);
++
++ if (NULL == ep) {
++ CFI_INFO("%s: Unable to get the endpoint addr=0x%02x\n",
++ __func__, wValue & 0xff);
++ return -DWC_E_INVALID;
++ }
++
++ if (!ep->dwc_ep.is_in) {
++ CFI_INFO
++ ("%s: No Tx FIFO assingned to the Out endpoint addr=0x%02x\n",
++ __func__, wValue & 0xff);
++ return -DWC_E_INVALID;
++ }
++
++ switch (wValue >> 8) {
++ case 0:
++ return (GET_CORE_IF(pcd)->pwron_txfsiz
++ [ep->dwc_ep.tx_fifo_num - 1] <
++ 768) ? GET_CORE_IF(pcd)->pwron_txfsiz[ep->
++ dwc_ep.tx_fifo_num
++ - 1] : 32768;
++ break;
++ case 1:
++ return GET_CORE_IF(pcd)->core_params->
++ dev_tx_fifo_size[ep->dwc_ep.num - 1];
++ break;
++ default:
++ return -DWC_E_INVALID;
++ break;
++ }
++}
++
++/**
++ * This function checks if the submitted combination of
++ * device mode FIFO sizes is possible or not.
++ *
++ * @param core_if Programming view of DWC_otg controller
++ *
++ * @return 1 if possible, 0 otherwise.
++ *
++ */
++static uint8_t check_fifo_sizes(dwc_otg_core_if_t * core_if)
++{
++ uint16_t dfifo_actual = 0;
++ dwc_otg_core_params_t *params = core_if->core_params;
++ uint16_t start_addr = 0;
++ int i;
++
++ dfifo_actual =
++ params->dev_rx_fifo_size + params->dev_nperio_tx_fifo_size;
++
++ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
++ dfifo_actual += params->dev_tx_fifo_size[i];
++ }
++
++ if (dfifo_actual > core_if->total_fifo_size) {
++ return 0;
++ }
++
++ if (params->dev_rx_fifo_size > 32768 || params->dev_rx_fifo_size < 16)
++ return 0;
++
++ if (params->dev_nperio_tx_fifo_size > 32768
++ || params->dev_nperio_tx_fifo_size < 16)
++ return 0;
++
++ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
++
++ if (params->dev_tx_fifo_size[i] > 768
++ || params->dev_tx_fifo_size[i] < 4)
++ return 0;
++ }
++
++ if (params->dev_rx_fifo_size > core_if->pwron_rxfsiz)
++ return 0;
++ start_addr = params->dev_rx_fifo_size;
++
++ if (params->dev_nperio_tx_fifo_size > core_if->pwron_gnptxfsiz)
++ return 0;
++ start_addr += params->dev_nperio_tx_fifo_size;
++
++ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
++
++ if (params->dev_tx_fifo_size[i] > core_if->pwron_txfsiz[i])
++ return 0;
++ start_addr += params->dev_tx_fifo_size[i];
++ }
++
++ return 1;
++}
++
++/**
++ * This function resizes Device mode FIFOs
++ *
++ * @param core_if Programming view of DWC_otg controller
++ *
++ * @return 1 if successful, 0 otherwise
++ *
++ */
++static uint8_t resize_fifos(dwc_otg_core_if_t * core_if)
++{
++ int i = 0;
++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
++ dwc_otg_core_params_t *params = core_if->core_params;
++ uint32_t rx_fifo_size;
++ fifosize_data_t nptxfifosize;
++ fifosize_data_t txfifosize[15];
++
++ uint32_t rx_fsz_bak;
++ uint32_t nptxfsz_bak;
++ uint32_t txfsz_bak[15];
++
++ uint16_t start_address;
++ uint8_t retval = 1;
++
++ if (!check_fifo_sizes(core_if)) {
++ return 0;
++ }
++
++ /* Configure data FIFO sizes */
++ if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) {
++ rx_fsz_bak = DWC_READ_REG32(&global_regs->grxfsiz);
++ rx_fifo_size = params->dev_rx_fifo_size;
++ DWC_WRITE_REG32(&global_regs->grxfsiz, rx_fifo_size);
++
++ /*
++ * Tx FIFOs These FIFOs are numbered from 1 to 15.
++ * Indexes of the FIFO size module parameters in the
++ * dev_tx_fifo_size array and the FIFO size registers in
++ * the dtxfsiz array run from 0 to 14.
++ */
++
++ /* Non-periodic Tx FIFO */
++ nptxfsz_bak = DWC_READ_REG32(&global_regs->gnptxfsiz);
++ nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size;
++ start_address = params->dev_rx_fifo_size;
++ nptxfifosize.b.startaddr = start_address;
++
++ DWC_WRITE_REG32(&global_regs->gnptxfsiz, nptxfifosize.d32);
++
++ start_address += nptxfifosize.b.depth;
++
++ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
++ txfsz_bak[i] = DWC_READ_REG32(&global_regs->dtxfsiz[i]);
++
++ txfifosize[i].b.depth = params->dev_tx_fifo_size[i];
++ txfifosize[i].b.startaddr = start_address;
++ DWC_WRITE_REG32(&global_regs->dtxfsiz[i],
++ txfifosize[i].d32);
++
++ start_address += txfifosize[i].b.depth;
++ }
++
++ /** Check if register values are set correctly */
++ if (rx_fifo_size != DWC_READ_REG32(&global_regs->grxfsiz)) {
++ retval = 0;
++ }
++
++ if (nptxfifosize.d32 != DWC_READ_REG32(&global_regs->gnptxfsiz)) {
++ retval = 0;
++ }
++
++ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
++ if (txfifosize[i].d32 !=
++ DWC_READ_REG32(&global_regs->dtxfsiz[i])) {
++ retval = 0;
++ }
++ }
++
++ /** If register values are not set correctly, reset old values */
++ if (retval == 0) {
++ DWC_WRITE_REG32(&global_regs->grxfsiz, rx_fsz_bak);
++
++ /* Non-periodic Tx FIFO */
++ DWC_WRITE_REG32(&global_regs->gnptxfsiz, nptxfsz_bak);
++
++ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
++ DWC_WRITE_REG32(&global_regs->dtxfsiz[i],
++ txfsz_bak[i]);
++ }
++ }
++ } else {
++ return 0;
++ }
++
++ /* Flush the FIFOs */
++ dwc_otg_flush_tx_fifo(core_if, 0x10); /* all Tx FIFOs */
++ dwc_otg_flush_rx_fifo(core_if);
++
++ return retval;
++}
++
++/**
++ * This function sets a new value for the buffer Alignment setup.
++ */
++static int cfi_ep_set_tx_fifo_val(uint8_t * buf, dwc_otg_pcd_t * pcd)
++{
++ int retval;
++ uint32_t fsiz;
++ uint16_t size;
++ uint16_t ep_addr;
++ dwc_otg_pcd_ep_t *ep;
++ dwc_otg_core_params_t *params = GET_CORE_IF(pcd)->core_params;
++ tx_fifo_size_setup_t *ptxfifoval;
++
++ ptxfifoval = (tx_fifo_size_setup_t *) buf;
++ ep_addr = ptxfifoval->bEndpointAddress;
++ size = ptxfifoval->wDepth;
++
++ ep = get_ep_by_addr(pcd, ep_addr);
++
++ CFI_INFO
++ ("%s: Set Tx FIFO size: endpoint addr=0x%02x, depth=%d, FIFO Num=%d\n",
++ __func__, ep_addr, size, ep->dwc_ep.tx_fifo_num);
++
++ if (NULL == ep) {
++ CFI_INFO("%s: Unable to get the endpoint addr=0x%02x\n",
++ __func__, ep_addr);
++ return -DWC_E_INVALID;
++ }
++
++ fsiz = params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1];
++ params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1] = size;
++
++ if (resize_fifos(GET_CORE_IF(pcd))) {
++ retval = 0;
++ } else {
++ CFI_INFO
++ ("%s: Error setting the feature Tx FIFO Size for EP%d\n",
++ __func__, ep_addr);
++ params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1] = fsiz;
++ retval = -DWC_E_INVALID;
++ }
++
++ return retval;
++}
++
++/**
++ * This function sets a new value for the buffer Alignment setup.
++ */
++static int cfi_set_rx_fifo_val(uint8_t * buf, dwc_otg_pcd_t * pcd)
++{
++ int retval;
++ uint32_t fsiz;
++ uint16_t size;
++ dwc_otg_core_params_t *params = GET_CORE_IF(pcd)->core_params;
++ rx_fifo_size_setup_t *prxfifoval;
++
++ prxfifoval = (rx_fifo_size_setup_t *) buf;
++ size = prxfifoval->wDepth;
++
++ fsiz = params->dev_rx_fifo_size;
++ params->dev_rx_fifo_size = size;
++
++ if (resize_fifos(GET_CORE_IF(pcd))) {
++ retval = 0;
++ } else {
++ CFI_INFO("%s: Error setting the feature Rx FIFO Size\n",
++ __func__);
++ params->dev_rx_fifo_size = fsiz;
++ retval = -DWC_E_INVALID;
++ }
++
++ return retval;
++}
++
++/**
++ * This function reads the SG of an EP's buffer setup into the buffer buf
++ */
++static int cfi_ep_get_sg_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
++ struct cfi_usb_ctrlrequest *req)
++{
++ int retval = -DWC_E_INVALID;
++ uint8_t addr;
++ cfi_ep_t *ep;
++
++ /* The Low Byte of the wValue contains a non-zero address of the endpoint */
++ addr = req->wValue & 0xFF;
++ if (addr == 0) /* The address should be non-zero */
++ return retval;
++
++ ep = get_cfi_ep_by_addr(pcd->cfi, addr);
++ if (NULL == ep) {
++ CFI_INFO("%s: Unable to get the endpoint address(0x%02x)\n",
++ __func__, addr);
++ return retval;
++ }
++
++ dwc_memcpy(buf, ep->bm_sg, BS_SG_VAL_DESC_LEN);
++ retval = BS_SG_VAL_DESC_LEN;
++ return retval;
++}
++
++/**
++ * This function reads the Concatenation value of an EP's buffer mode into
++ * the buffer buf
++ */
++static int cfi_ep_get_concat_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
++ struct cfi_usb_ctrlrequest *req)
++{
++ int retval = -DWC_E_INVALID;
++ uint8_t addr;
++ cfi_ep_t *ep;
++ uint8_t desc_count;
++
++ /* The Low Byte of the wValue contains a non-zero address of the endpoint */
++ addr = req->wValue & 0xFF;
++ if (addr == 0) /* The address should be non-zero */
++ return retval;
++
++ ep = get_cfi_ep_by_addr(pcd->cfi, addr);
++ if (NULL == ep) {
++ CFI_INFO("%s: Unable to get the endpoint address(0x%02x)\n",
++ __func__, addr);
++ return retval;
++ }
++
++ /* Copy the header to the buffer */
++ dwc_memcpy(buf, ep->bm_concat, BS_CONCAT_VAL_HDR_LEN);
++ /* Advance the buffer pointer by the header size */
++ buf += BS_CONCAT_VAL_HDR_LEN;
++
++ desc_count = ep->bm_concat->hdr.bDescCount;
++ /* Copy alll the wTxBytes to the buffer */
++ dwc_memcpy(buf, ep->bm_concat->wTxBytes, sizeof(uid16_t) * desc_count);
++
++ retval = BS_CONCAT_VAL_HDR_LEN + sizeof(uid16_t) * desc_count;
++ return retval;
++}
++
++/**
++ * This function reads the buffer Alignment value of an EP's buffer mode into
++ * the buffer buf
++ *
++ * @return The total number of bytes copied to the buffer or negative error code.
++ */
++static int cfi_ep_get_align_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
++ struct cfi_usb_ctrlrequest *req)
++{
++ int retval = -DWC_E_INVALID;
++ uint8_t addr;
++ cfi_ep_t *ep;
++
++ /* The Low Byte of the wValue contains a non-zero address of the endpoint */
++ addr = req->wValue & 0xFF;
++ if (addr == 0) /* The address should be non-zero */
++ return retval;
++
++ ep = get_cfi_ep_by_addr(pcd->cfi, addr);
++ if (NULL == ep) {
++ CFI_INFO("%s: Unable to get the endpoint address(0x%02x)\n",
++ __func__, addr);
++ return retval;
++ }
++
++ dwc_memcpy(buf, ep->bm_align, BS_ALIGN_VAL_HDR_LEN);
++ retval = BS_ALIGN_VAL_HDR_LEN;
++
++ return retval;
++}
++
++/**
++ * This function sets a new value for the specified feature
++ *
++ * @param pcd A pointer to the PCD object
++ *
++ * @return 0 if successful, negative error code otherwise to stall the DCE.
++ */
++static int cfi_set_feature_value(struct dwc_otg_pcd *pcd)
++{
++ int retval = -DWC_E_NOT_SUPPORTED;
++ uint16_t wIndex, wValue;
++ uint8_t bRequest;
++ struct dwc_otg_core_if *coreif;
++ cfiobject_t *cfi = pcd->cfi;
++ struct cfi_usb_ctrlrequest *ctrl_req;
++ uint8_t *buf;
++ ctrl_req = &cfi->ctrl_req;
++
++ buf = pcd->cfi->ctrl_req.data;
++
++ coreif = GET_CORE_IF(pcd);
++ bRequest = ctrl_req->bRequest;
++ wIndex = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wIndex);
++ wValue = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wValue);
++
++ /* See which feature is to be modified */
++ switch (wIndex) {
++ case FT_ID_DMA_BUFFER_SETUP:
++ /* Modify the feature */
++ if ((retval = cfi_ep_set_sg_val(buf, pcd)) < 0)
++ return retval;
++
++ /* And send this request to the gadget */
++ cfi->need_gadget_att = 1;
++ break;
++
++ case FT_ID_DMA_BUFF_ALIGN:
++ if ((retval = cfi_ep_set_alignment_val(buf, pcd)) < 0)
++ return retval;
++ cfi->need_gadget_att = 1;
++ break;
++
++ case FT_ID_DMA_CONCAT_SETUP:
++ /* Modify the feature */
++ if ((retval = cfi_ep_set_concat_val(buf, pcd)) < 0)
++ return retval;
++ cfi->need_gadget_att = 1;
++ break;
++
++ case FT_ID_DMA_CIRCULAR:
++ CFI_INFO("FT_ID_DMA_CIRCULAR\n");
++ break;
++
++ case FT_ID_THRESHOLD_SETUP:
++ CFI_INFO("FT_ID_THRESHOLD_SETUP\n");
++ break;
++
++ case FT_ID_DFIFO_DEPTH:
++ CFI_INFO("FT_ID_DFIFO_DEPTH\n");
++ break;
++
++ case FT_ID_TX_FIFO_DEPTH:
++ CFI_INFO("FT_ID_TX_FIFO_DEPTH\n");
++ if ((retval = cfi_ep_set_tx_fifo_val(buf, pcd)) < 0)
++ return retval;
++ cfi->need_gadget_att = 0;
++ break;
++
++ case FT_ID_RX_FIFO_DEPTH:
++ CFI_INFO("FT_ID_RX_FIFO_DEPTH\n");
++ if ((retval = cfi_set_rx_fifo_val(buf, pcd)) < 0)
++ return retval;
++ cfi->need_gadget_att = 0;
++ break;
++ }
++
++ return retval;
++}
++
++#endif //DWC_UTE_CFI
+diff -Nur linux-4.1.3/drivers/usb/host/dwc_otg/dwc_otg_cfi.h linux-xbian-rpi/drivers/usb/host/dwc_otg/dwc_otg_cfi.h
+--- linux-4.1.3/drivers/usb/host/dwc_otg/dwc_otg_cfi.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/usb/host/dwc_otg/dwc_otg_cfi.h 2015-07-28 01:20:58.445156473 +0200
+@@ -0,0 +1,320 @@
++/* ==========================================================================
++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++ * otherwise expressly agreed to in writing between Synopsys and you.
++ *
++ * The Software IS NOT an item of Licensed Software or Licensed Product under
++ * any End User Software License Agreement or Agreement for Licensed Product
++ * with Synopsys or any supplement thereto. You are permitted to use and
++ * redistribute this Software in source and binary forms, with or without
++ * modification, provided that redistributions of source code must retain this
++ * notice. You may not view, use, disclose, copy or distribute this file or
++ * any information contained herein except pursuant to this license grant from
++ * Synopsys. If you do not agree with this notice, including the disclaimer
++ * below, then you are not authorized to use the Software.
++ *
++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++ * DAMAGE.
++ * ========================================================================== */
++
++#if !defined(__DWC_OTG_CFI_H__)
++#define __DWC_OTG_CFI_H__
++
++#include "dwc_otg_pcd.h"
++#include "dwc_cfi_common.h"
++
++/**
++ * @file
++ * This file contains the CFI related OTG PCD specific common constants,
++ * interfaces(functions and macros) and data structures.The CFI Protocol is an
++ * optional interface for internal testing purposes that a DUT may implement to
++ * support testing of configurable features.
++ *
++ */
++
++struct dwc_otg_pcd;
++struct dwc_otg_pcd_ep;
++
++/** OTG CFI Features (properties) ID constants */
++/** This is a request for all Core Features */
++#define FT_ID_DMA_MODE 0x0001
++#define FT_ID_DMA_BUFFER_SETUP 0x0002
++#define FT_ID_DMA_BUFF_ALIGN 0x0003
++#define FT_ID_DMA_CONCAT_SETUP 0x0004
++#define FT_ID_DMA_CIRCULAR 0x0005
++#define FT_ID_THRESHOLD_SETUP 0x0006
++#define FT_ID_DFIFO_DEPTH 0x0007
++#define FT_ID_TX_FIFO_DEPTH 0x0008
++#define FT_ID_RX_FIFO_DEPTH 0x0009
++
++/**********************************************************/
++#define CFI_INFO_DEF
++
++#ifdef CFI_INFO_DEF
++#define CFI_INFO(fmt...) DWC_PRINTF("CFI: " fmt);
++#else
++#define CFI_INFO(fmt...)
++#endif
++
++#define min(x,y) ({ \
++ x < y ? x : y; })
++
++#define max(x,y) ({ \
++ x > y ? x : y; })
++
++/**
++ * Descriptor DMA SG Buffer setup structure (SG buffer). This structure is
++ * also used for setting up a buffer for Circular DDMA.
++ */
++struct _ddma_sg_buffer_setup {
++#define BS_SG_VAL_DESC_LEN 6
++ /* The OUT EP address */
++ uint8_t bOutEndpointAddress;
++ /* The IN EP address */
++ uint8_t bInEndpointAddress;
++ /* Number of bytes to put between transfer segments (must be DWORD boundaries) */
++ uint8_t bOffset;
++ /* The number of transfer segments (a DMA descriptors per each segment) */
++ uint8_t bCount;
++ /* Size (in byte) of each transfer segment */
++ uint16_t wSize;
++} __attribute__ ((packed));
++typedef struct _ddma_sg_buffer_setup ddma_sg_buffer_setup_t;
++
++/** Descriptor DMA Concatenation Buffer setup structure */
++struct _ddma_concat_buffer_setup_hdr {
++#define BS_CONCAT_VAL_HDR_LEN 4
++ /* The endpoint for which the buffer is to be set up */
++ uint8_t bEndpointAddress;
++ /* The count of descriptors to be used */
++ uint8_t bDescCount;
++ /* The total size of the transfer */
++ uint16_t wSize;
++} __attribute__ ((packed));
++typedef struct _ddma_concat_buffer_setup_hdr ddma_concat_buffer_setup_hdr_t;
++
++/** Descriptor DMA Concatenation Buffer setup structure */
++struct _ddma_concat_buffer_setup {
++ /* The SG header */
++ ddma_concat_buffer_setup_hdr_t hdr;
++
++ /* The XFER sizes pointer (allocated dynamically) */
++ uint16_t *wTxBytes;
++} __attribute__ ((packed));
++typedef struct _ddma_concat_buffer_setup ddma_concat_buffer_setup_t;
++
++/** Descriptor DMA Alignment Buffer setup structure */
++struct _ddma_align_buffer_setup {
++#define BS_ALIGN_VAL_HDR_LEN 2
++ uint8_t bEndpointAddress;
++ uint8_t bAlign;
++} __attribute__ ((packed));
++typedef struct _ddma_align_buffer_setup ddma_align_buffer_setup_t;
++
++/** Transmit FIFO Size setup structure */
++struct _tx_fifo_size_setup {
++ uint8_t bEndpointAddress;
++ uint16_t wDepth;
++} __attribute__ ((packed));
++typedef struct _tx_fifo_size_setup tx_fifo_size_setup_t;
++
++/** Transmit FIFO Size setup structure */
++struct _rx_fifo_size_setup {
++ uint16_t wDepth;
++} __attribute__ ((packed));
++typedef struct _rx_fifo_size_setup rx_fifo_size_setup_t;
++
++/**
++ * struct cfi_usb_ctrlrequest - the CFI implementation of the struct usb_ctrlrequest
++ * This structure encapsulates the standard usb_ctrlrequest and adds a pointer
++ * to the data returned in the data stage of a 3-stage Control Write requests.
++ */
++struct cfi_usb_ctrlrequest {
++ uint8_t bRequestType;
++ uint8_t bRequest;
++ uint16_t wValue;
++ uint16_t wIndex;
++ uint16_t wLength;
++ uint8_t *data;
++} UPACKED;
++
++/*---------------------------------------------------------------------------*/
++
++/**
++ * The CFI wrapper of the enabled and activated dwc_otg_pcd_ep structures.
++ * This structure is used to store the buffer setup data for any
++ * enabled endpoint in the PCD.
++ */
++struct cfi_ep {
++ /* Entry for the list container */
++ dwc_list_link_t lh;
++ /* Pointer to the active PCD endpoint structure */
++ struct dwc_otg_pcd_ep *ep;
++ /* The last descriptor in the chain of DMA descriptors of the endpoint */
++ struct dwc_otg_dma_desc *dma_desc_last;
++ /* The SG feature value */
++ ddma_sg_buffer_setup_t *bm_sg;
++ /* The Circular feature value */
++ ddma_sg_buffer_setup_t *bm_circ;
++ /* The Concatenation feature value */
++ ddma_concat_buffer_setup_t *bm_concat;
++ /* The Alignment feature value */
++ ddma_align_buffer_setup_t *bm_align;
++ /* XFER length */
++ uint32_t xfer_len;
++ /*
++ * Count of DMA descriptors currently used.
++ * The total should not exceed the MAX_DMA_DESCS_PER_EP value
++ * defined in the dwc_otg_cil.h
++ */
++ uint32_t desc_count;
++};
++typedef struct cfi_ep cfi_ep_t;
++
++typedef struct cfi_dma_buff {
++#define CFI_IN_BUF_LEN 1024
++#define CFI_OUT_BUF_LEN 1024
++ dma_addr_t addr;
++ uint8_t *buf;
++} cfi_dma_buff_t;
++
++struct cfiobject;
++
++/**
++ * This is the interface for the CFI operations.
++ *
++ * @param ep_enable Called when any endpoint is enabled and activated.
++ * @param release Called when the CFI object is released and it needs to correctly
++ * deallocate the dynamic memory
++ * @param ctrl_write_complete Called when the data stage of the request is complete
++ */
++typedef struct cfi_ops {
++ int (*ep_enable) (struct cfiobject * cfi, struct dwc_otg_pcd * pcd,
++ struct dwc_otg_pcd_ep * ep);
++ void *(*ep_alloc_buf) (struct cfiobject * cfi, struct dwc_otg_pcd * pcd,
++ struct dwc_otg_pcd_ep * ep, dma_addr_t * dma,
++ unsigned size, gfp_t flags);
++ void (*release) (struct cfiobject * cfi);
++ int (*ctrl_write_complete) (struct cfiobject * cfi,
++ struct dwc_otg_pcd * pcd);
++ void (*build_descriptors) (struct cfiobject * cfi,
++ struct dwc_otg_pcd * pcd,
++ struct dwc_otg_pcd_ep * ep,
++ dwc_otg_pcd_request_t * req);
++} cfi_ops_t;
++
++struct cfiobject {
++ cfi_ops_t ops;
++ struct dwc_otg_pcd *pcd;
++ struct usb_gadget *gadget;
++
++ /* Buffers used to send/receive CFI-related request data */
++ cfi_dma_buff_t buf_in;
++ cfi_dma_buff_t buf_out;
++
++ /* CFI specific Control request wrapper */
++ struct cfi_usb_ctrlrequest ctrl_req;
++
++ /* The list of active EP's in the PCD of type cfi_ep_t */
++ dwc_list_link_t active_eps;
++
++ /* This flag shall control the propagation of a specific request
++ * to the gadget's processing routines.
++ * 0 - no gadget handling
++ * 1 - the gadget needs to know about this request (w/o completing a status
++ * phase - just return a 0 to the _setup callback)
++ */
++ uint8_t need_gadget_att;
++
++ /* Flag indicating whether the status IN phase needs to be
++ * completed by the PCD
++ */
++ uint8_t need_status_in_complete;
++};
++typedef struct cfiobject cfiobject_t;
++
++#define DUMP_MSG
++
++#if defined(DUMP_MSG)
++static inline void dump_msg(const u8 * buf, unsigned int length)
++{
++ unsigned int start, num, i;
++ char line[52], *p;
++
++ if (length >= 512)
++ return;
++
++ start = 0;
++ while (length > 0) {
++ num = min(length, 16u);
++ p = line;
++ for (i = 0; i < num; ++i) {
++ if (i == 8)
++ *p++ = ' ';
++ DWC_SPRINTF(p, " %02x", buf[i]);
++ p += 3;
++ }
++ *p = 0;
++ DWC_DEBUG("%6x: %s\n", start, line);
++ buf += num;
++ start += num;
++ length -= num;
++ }
++}
++#else
++static inline void dump_msg(const u8 * buf, unsigned int length)
++{
++}
++#endif
++
++/**
++ * This function returns a pointer to cfi_ep_t object with the addr address.
++ */
++static inline struct cfi_ep *get_cfi_ep_by_addr(struct cfiobject *cfi,
++ uint8_t addr)
++{
++ struct cfi_ep *pcfiep;
++ dwc_list_link_t *tmp;
++
++ DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
++ pcfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
++
++ if (pcfiep->ep->desc->bEndpointAddress == addr) {
++ return pcfiep;
++ }
++ }
++
++ return NULL;
++}
++
++/**
++ * This function returns a pointer to cfi_ep_t object that matches
++ * the dwc_otg_pcd_ep object.
++ */
++static inline struct cfi_ep *get_cfi_ep_by_pcd_ep(struct cfiobject *cfi,
++ struct dwc_otg_pcd_ep *ep)
++{
++ struct cfi_ep *pcfiep = NULL;
++ dwc_list_link_t *tmp;
++
++ DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
++ pcfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
++ if (pcfiep->ep == ep) {
++ return pcfiep;
++ }
++ }
++ return NULL;
++}
++
++int cfi_setup(struct dwc_otg_pcd *pcd, struct cfi_usb_ctrlrequest *ctrl);
++
++#endif /* (__DWC_OTG_CFI_H__) */
+diff -Nur linux-4.1.3/drivers/usb/host/dwc_otg/dwc_otg_cil.c linux-xbian-rpi/drivers/usb/host/dwc_otg/dwc_otg_cil.c
+--- linux-4.1.3/drivers/usb/host/dwc_otg/dwc_otg_cil.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/usb/host/dwc_otg/dwc_otg_cil.c 2015-07-28 01:20:58.445156473 +0200
+@@ -0,0 +1,7141 @@
++/* ==========================================================================
++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil.c $
++ * $Revision: #191 $
++ * $Date: 2012/08/10 $
++ * $Change: 2047372 $
++ *
++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++ * otherwise expressly agreed to in writing between Synopsys and you.
++ *
++ * The Software IS NOT an item of Licensed Software or Licensed Product under
++ * any End User Software License Agreement or Agreement for Licensed Product
++ * with Synopsys or any supplement thereto. You are permitted to use and
++ * redistribute this Software in source and binary forms, with or without
++ * modification, provided that redistributions of source code must retain this
++ * notice. You may not view, use, disclose, copy or distribute this file or
++ * any information contained herein except pursuant to this license grant from
++ * Synopsys. If you do not agree with this notice, including the disclaimer
++ * below, then you are not authorized to use the Software.
++ *
++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++ * DAMAGE.
++ * ========================================================================== */
++
++/** @file
++ *
++ * The Core Interface Layer provides basic services for accessing and
++ * managing the DWC_otg hardware. These services are used by both the
++ * Host Controller Driver and the Peripheral Controller Driver.
++ *
++ * The CIL manages the memory map for the core so that the HCD and PCD
++ * don't have to do this separately. It also handles basic tasks like
++ * reading/writing the registers and data FIFOs in the controller.
++ * Some of the data access functions provide encapsulation of several
++ * operations required to perform a task, such as writing multiple
++ * registers to start a transfer. Finally, the CIL performs basic
++ * services that are not specific to either the host or device modes
++ * of operation. These services include management of the OTG Host
++ * Negotiation Protocol (HNP) and Session Request Protocol (SRP). A
++ * Diagnostic API is also provided to allow testing of the controller
++ * hardware.
++ *
++ * The Core Interface Layer has the following requirements:
++ * - Provides basic controller operations.
++ * - Minimal use of OS services.
++ * - The OS services used will be abstracted by using inline functions
++ * or macros.
++ *
++ */
++
++#include "dwc_os.h"
++#include "dwc_otg_regs.h"
++#include "dwc_otg_cil.h"
++
++static int dwc_otg_setup_params(dwc_otg_core_if_t * core_if);
++
++/**
++ * This function is called to initialize the DWC_otg CSR data
++ * structures. The register addresses in the device and host
++ * structures are initialized from the base address supplied by the
++ * caller. The calling function must make the OS calls to get the
++ * base address of the DWC_otg controller registers. The core_params
++ * argument holds the parameters that specify how the core should be
++ * configured.
++ *
++ * @param reg_base_addr Base address of DWC_otg core registers
++ *
++ */
++dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t * reg_base_addr)
++{
++ dwc_otg_core_if_t *core_if = 0;
++ dwc_otg_dev_if_t *dev_if = 0;
++ dwc_otg_host_if_t *host_if = 0;
++ uint8_t *reg_base = (uint8_t *) reg_base_addr;
++ int i = 0;
++
++ DWC_DEBUGPL(DBG_CILV, "%s(%p)\n", __func__, reg_base_addr);
++
++ core_if = DWC_ALLOC(sizeof(dwc_otg_core_if_t));
++
++ if (core_if == NULL) {
++ DWC_DEBUGPL(DBG_CIL,
++ "Allocation of dwc_otg_core_if_t failed\n");
++ return 0;
++ }
++ core_if->core_global_regs = (dwc_otg_core_global_regs_t *) reg_base;
++
++ /*
++ * Allocate the Device Mode structures.
++ */
++ dev_if = DWC_ALLOC(sizeof(dwc_otg_dev_if_t));
++
++ if (dev_if == NULL) {
++ DWC_DEBUGPL(DBG_CIL, "Allocation of dwc_otg_dev_if_t failed\n");
++ DWC_FREE(core_if);
++ return 0;
++ }
++
++ dev_if->dev_global_regs =
++ (dwc_otg_device_global_regs_t *) (reg_base +
++ DWC_DEV_GLOBAL_REG_OFFSET);
++
++ for (i = 0; i < MAX_EPS_CHANNELS; i++) {
++ dev_if->in_ep_regs[i] = (dwc_otg_dev_in_ep_regs_t *)
++ (reg_base + DWC_DEV_IN_EP_REG_OFFSET +
++ (i * DWC_EP_REG_OFFSET));
++
++ dev_if->out_ep_regs[i] = (dwc_otg_dev_out_ep_regs_t *)
++ (reg_base + DWC_DEV_OUT_EP_REG_OFFSET +
++ (i * DWC_EP_REG_OFFSET));
++ DWC_DEBUGPL(DBG_CILV, "in_ep_regs[%d]->diepctl=%p\n",
++ i, &dev_if->in_ep_regs[i]->diepctl);
++ DWC_DEBUGPL(DBG_CILV, "out_ep_regs[%d]->doepctl=%p\n",
++ i, &dev_if->out_ep_regs[i]->doepctl);
++ }
++
++ dev_if->speed = 0; // unknown
++
++ core_if->dev_if = dev_if;
++
++ /*
++ * Allocate the Host Mode structures.
++ */
++ host_if = DWC_ALLOC(sizeof(dwc_otg_host_if_t));
++
++ if (host_if == NULL) {
++ DWC_DEBUGPL(DBG_CIL,
++ "Allocation of dwc_otg_host_if_t failed\n");
++ DWC_FREE(dev_if);
++ DWC_FREE(core_if);
++ return 0;
++ }
++
++ host_if->host_global_regs = (dwc_otg_host_global_regs_t *)
++ (reg_base + DWC_OTG_HOST_GLOBAL_REG_OFFSET);
++
++ host_if->hprt0 =
++ (uint32_t *) (reg_base + DWC_OTG_HOST_PORT_REGS_OFFSET);
++
++ for (i = 0; i < MAX_EPS_CHANNELS; i++) {
++ host_if->hc_regs[i] = (dwc_otg_hc_regs_t *)
++ (reg_base + DWC_OTG_HOST_CHAN_REGS_OFFSET +
++ (i * DWC_OTG_CHAN_REGS_OFFSET));
++ DWC_DEBUGPL(DBG_CILV, "hc_reg[%d]->hcchar=%p\n",
++ i, &host_if->hc_regs[i]->hcchar);
++ }
++
++ host_if->num_host_channels = MAX_EPS_CHANNELS;
++ core_if->host_if = host_if;
++
++ for (i = 0; i < MAX_EPS_CHANNELS; i++) {
++ core_if->data_fifo[i] =
++ (uint32_t *) (reg_base + DWC_OTG_DATA_FIFO_OFFSET +
++ (i * DWC_OTG_DATA_FIFO_SIZE));
++ DWC_DEBUGPL(DBG_CILV, "data_fifo[%d]=0x%08lx\n",
++ i, (unsigned long)core_if->data_fifo[i]);
++ }
++
++ core_if->pcgcctl = (uint32_t *) (reg_base + DWC_OTG_PCGCCTL_OFFSET);
++
++ /* Initiate lx_state to L3 disconnected state */
++ core_if->lx_state = DWC_OTG_L3;
++ /*
++ * Store the contents of the hardware configuration registers here for
++ * easy access later.
++ */
++ core_if->hwcfg1.d32 =
++ DWC_READ_REG32(&core_if->core_global_regs->ghwcfg1);
++ core_if->hwcfg2.d32 =
++ DWC_READ_REG32(&core_if->core_global_regs->ghwcfg2);
++ core_if->hwcfg3.d32 =
++ DWC_READ_REG32(&core_if->core_global_regs->ghwcfg3);
++ core_if->hwcfg4.d32 =
++ DWC_READ_REG32(&core_if->core_global_regs->ghwcfg4);
++
++ /* Force host mode to get HPTXFSIZ exact power on value */
++ {
++ gusbcfg_data_t gusbcfg = {.d32 = 0 };
++ gusbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
++ gusbcfg.b.force_host_mode = 1;
++ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gusbcfg.d32);
++ dwc_mdelay(100);
++ core_if->hptxfsiz.d32 =
++ DWC_READ_REG32(&core_if->core_global_regs->hptxfsiz);
++ gusbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
++ gusbcfg.b.force_host_mode = 0;
++ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gusbcfg.d32);
++ dwc_mdelay(100);
++ }
++
++ DWC_DEBUGPL(DBG_CILV, "hwcfg1=%08x\n", core_if->hwcfg1.d32);
++ DWC_DEBUGPL(DBG_CILV, "hwcfg2=%08x\n", core_if->hwcfg2.d32);
++ DWC_DEBUGPL(DBG_CILV, "hwcfg3=%08x\n", core_if->hwcfg3.d32);
++ DWC_DEBUGPL(DBG_CILV, "hwcfg4=%08x\n", core_if->hwcfg4.d32);
++
++ core_if->hcfg.d32 =
++ DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
++ core_if->dcfg.d32 =
++ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
++
++ DWC_DEBUGPL(DBG_CILV, "hcfg=%08x\n", core_if->hcfg.d32);
++ DWC_DEBUGPL(DBG_CILV, "dcfg=%08x\n", core_if->dcfg.d32);
++
++ DWC_DEBUGPL(DBG_CILV, "op_mode=%0x\n", core_if->hwcfg2.b.op_mode);
++ DWC_DEBUGPL(DBG_CILV, "arch=%0x\n", core_if->hwcfg2.b.architecture);
++ DWC_DEBUGPL(DBG_CILV, "num_dev_ep=%d\n", core_if->hwcfg2.b.num_dev_ep);
++ DWC_DEBUGPL(DBG_CILV, "num_host_chan=%d\n",
++ core_if->hwcfg2.b.num_host_chan);
++ DWC_DEBUGPL(DBG_CILV, "nonperio_tx_q_depth=0x%0x\n",
++ core_if->hwcfg2.b.nonperio_tx_q_depth);
++ DWC_DEBUGPL(DBG_CILV, "host_perio_tx_q_depth=0x%0x\n",
++ core_if->hwcfg2.b.host_perio_tx_q_depth);
++ DWC_DEBUGPL(DBG_CILV, "dev_token_q_depth=0x%0x\n",
++ core_if->hwcfg2.b.dev_token_q_depth);
++
++ DWC_DEBUGPL(DBG_CILV, "Total FIFO SZ=%d\n",
++ core_if->hwcfg3.b.dfifo_depth);
++ DWC_DEBUGPL(DBG_CILV, "xfer_size_cntr_width=%0x\n",
++ core_if->hwcfg3.b.xfer_size_cntr_width);
++
++ /*
++ * Set the SRP sucess bit for FS-I2c
++ */
++ core_if->srp_success = 0;
++ core_if->srp_timer_started = 0;
++
++ /*
++ * Create new workqueue and init works
++ */
++ core_if->wq_otg = DWC_WORKQ_ALLOC("dwc_otg");
++ if (core_if->wq_otg == 0) {
++ DWC_WARN("DWC_WORKQ_ALLOC failed\n");
++ DWC_FREE(host_if);
++ DWC_FREE(dev_if);
++ DWC_FREE(core_if);
++ return 0;
++ }
++
++ core_if->snpsid = DWC_READ_REG32(&core_if->core_global_regs->gsnpsid);
++
++ DWC_PRINTF("Core Release: %x.%x%x%x\n",
++ (core_if->snpsid >> 12 & 0xF),
++ (core_if->snpsid >> 8 & 0xF),
++ (core_if->snpsid >> 4 & 0xF), (core_if->snpsid & 0xF));
++
++ core_if->wkp_timer = DWC_TIMER_ALLOC("Wake Up Timer",
++ w_wakeup_detected, core_if);
++ if (core_if->wkp_timer == 0) {
++ DWC_WARN("DWC_TIMER_ALLOC failed\n");
++ DWC_FREE(host_if);
++ DWC_FREE(dev_if);
++ DWC_WORKQ_FREE(core_if->wq_otg);
++ DWC_FREE(core_if);
++ return 0;
++ }
++
++ if (dwc_otg_setup_params(core_if)) {
++ DWC_WARN("Error while setting core params\n");
++ }
++
++ core_if->hibernation_suspend = 0;
++
++ /** ADP initialization */
++ dwc_otg_adp_init(core_if);
++
++ return core_if;
++}
++
++/**
++ * This function frees the structures allocated by dwc_otg_cil_init().
++ *
++ * @param core_if The core interface pointer returned from
++ * dwc_otg_cil_init().
++ *
++ */
++void dwc_otg_cil_remove(dwc_otg_core_if_t * core_if)
++{
++ dctl_data_t dctl = {.d32 = 0 };
++ DWC_DEBUGPL(DBG_CILV, "%s(%p)\n", __func__, core_if);
++
++ /* Disable all interrupts */
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, 1, 0);
++ DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, 0);
++
++ dctl.b.sftdiscon = 1;
++ if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0,
++ dctl.d32);
++ }
++
++ if (core_if->wq_otg) {
++ DWC_WORKQ_WAIT_WORK_DONE(core_if->wq_otg, 500);
++ DWC_WORKQ_FREE(core_if->wq_otg);
++ }
++ if (core_if->dev_if) {
++ DWC_FREE(core_if->dev_if);
++ }
++ if (core_if->host_if) {
++ DWC_FREE(core_if->host_if);
++ }
++
++ /** Remove ADP Stuff */
++ dwc_otg_adp_remove(core_if);
++ if (core_if->core_params) {
++ DWC_FREE(core_if->core_params);
++ }
++ if (core_if->wkp_timer) {
++ DWC_TIMER_FREE(core_if->wkp_timer);
++ }
++ if (core_if->srp_timer) {
++ DWC_TIMER_FREE(core_if->srp_timer);
++ }
++ DWC_FREE(core_if);
++}
++
++/**
++ * This function enables the controller's Global Interrupt in the AHB Config
++ * register.
++ *
++ * @param core_if Programming view of DWC_otg controller.
++ */
++void dwc_otg_enable_global_interrupts(dwc_otg_core_if_t * core_if)
++{
++ gahbcfg_data_t ahbcfg = {.d32 = 0 };
++ ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, 0, ahbcfg.d32);
++}
++
++/**
++ * This function disables the controller's Global Interrupt in the AHB Config
++ * register.
++ *
++ * @param core_if Programming view of DWC_otg controller.
++ */
++void dwc_otg_disable_global_interrupts(dwc_otg_core_if_t * core_if)
++{
++ gahbcfg_data_t ahbcfg = {.d32 = 0 };
++ ahbcfg.b.glblintrmsk = 1; /* Disable interrupts */
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, ahbcfg.d32, 0);
++}
++
++/**
++ * This function initializes the commmon interrupts, used in both
++ * device and host modes.
++ *
++ * @param core_if Programming view of the DWC_otg controller
++ *
++ */
++static void dwc_otg_enable_common_interrupts(dwc_otg_core_if_t * core_if)
++{
++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
++ gintmsk_data_t intr_mask = {.d32 = 0 };
++
++ /* Clear any pending OTG Interrupts */
++ DWC_WRITE_REG32(&global_regs->gotgint, 0xFFFFFFFF);
++
++ /* Clear any pending interrupts */
++ DWC_WRITE_REG32(&global_regs->gintsts, 0xFFFFFFFF);
++
++ /*
++ * Enable the interrupts in the GINTMSK.
++ */
++ intr_mask.b.modemismatch = 1;
++ intr_mask.b.otgintr = 1;
++
++ if (!core_if->dma_enable) {
++ intr_mask.b.rxstsqlvl = 1;
++ }
++
++ intr_mask.b.conidstschng = 1;
++ intr_mask.b.wkupintr = 1;
++ intr_mask.b.disconnect = 0;
++ intr_mask.b.usbsuspend = 1;
++ intr_mask.b.sessreqintr = 1;
++#ifdef CONFIG_USB_DWC_OTG_LPM
++ if (core_if->core_params->lpm_enable) {
++ intr_mask.b.lpmtranrcvd = 1;
++ }
++#endif
++ DWC_WRITE_REG32(&global_regs->gintmsk, intr_mask.d32);
++}
++
++/*
++ * The restore operation is modified to support Synopsys Emulated Powerdown and
++ * Hibernation. This function is for exiting from Device mode hibernation by
++ * Host Initiated Resume/Reset and Device Initiated Remote-Wakeup.
++ * @param core_if Programming view of DWC_otg controller.
++ * @param rem_wakeup - indicates whether resume is initiated by Device or Host.
++ * @param reset - indicates whether resume is initiated by Reset.
++ */
++int dwc_otg_device_hibernation_restore(dwc_otg_core_if_t * core_if,
++ int rem_wakeup, int reset)
++{
++ gpwrdn_data_t gpwrdn = {.d32 = 0 };
++ pcgcctl_data_t pcgcctl = {.d32 = 0 };
++ dctl_data_t dctl = {.d32 = 0 };
++
++ int timeout = 2000;
++
++ if (!core_if->hibernation_suspend) {
++ DWC_PRINTF("Already exited from Hibernation\n");
++ return 1;
++ }
++
++ DWC_DEBUGPL(DBG_PCD, "%s called\n", __FUNCTION__);
++ /* Switch-on voltage to the core */
++ gpwrdn.b.pwrdnswtch = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++ dwc_udelay(10);
++
++ /* Reset core */
++ gpwrdn.d32 = 0;
++ gpwrdn.b.pwrdnrstn = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++ dwc_udelay(10);
++
++ /* Assert Restore signal */
++ gpwrdn.d32 = 0;
++ gpwrdn.b.restore = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
++ dwc_udelay(10);
++
++ /* Disable power clamps */
++ gpwrdn.d32 = 0;
++ gpwrdn.b.pwrdnclmp = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++
++ if (rem_wakeup) {
++ dwc_udelay(70);
++ }
++
++ /* Deassert Reset core */
++ gpwrdn.d32 = 0;
++ gpwrdn.b.pwrdnrstn = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
++ dwc_udelay(10);
++
++ /* Disable PMU interrupt */
++ gpwrdn.d32 = 0;
++ gpwrdn.b.pmuintsel = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++
++ /* Mask interrupts from gpwrdn */
++ gpwrdn.d32 = 0;
++ gpwrdn.b.connect_det_msk = 1;
++ gpwrdn.b.srp_det_msk = 1;
++ gpwrdn.b.disconn_det_msk = 1;
++ gpwrdn.b.rst_det_msk = 1;
++ gpwrdn.b.lnstchng_msk = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++
++ /* Indicates that we are going out from hibernation */
++ core_if->hibernation_suspend = 0;
++
++ /*
++ * Set Restore Essential Regs bit in PCGCCTL register, restore_mode = 1
++ * indicates restore from remote_wakeup
++ */
++ restore_essential_regs(core_if, rem_wakeup, 0);
++
++ /*
++ * Wait a little for seeing new value of variable hibernation_suspend if
++ * Restore done interrupt received before polling
++ */
++ dwc_udelay(10);
++
++ if (core_if->hibernation_suspend == 0) {
++ /*
++ * Wait For Restore_done Interrupt. This mechanism of polling the
++ * interrupt is introduced to avoid any possible race conditions
++ */
++ do {
++ gintsts_data_t gintsts;
++ gintsts.d32 =
++ DWC_READ_REG32(&core_if->core_global_regs->gintsts);
++ if (gintsts.b.restoredone) {
++ gintsts.d32 = 0;
++ gintsts.b.restoredone = 1;
++ DWC_WRITE_REG32(&core_if->core_global_regs->
++ gintsts, gintsts.d32);
++ DWC_PRINTF("Restore Done Interrupt seen\n");
++ break;
++ }
++ dwc_udelay(10);
++ } while (--timeout);
++ if (!timeout) {
++ DWC_PRINTF("Restore Done interrupt wasn't generated here\n");
++ }
++ }
++ /* Clear all pending interupts */
++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
++
++ /* De-assert Restore */
++ gpwrdn.d32 = 0;
++ gpwrdn.b.restore = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++ dwc_udelay(10);
++
++ if (!rem_wakeup) {
++ pcgcctl.d32 = 0;
++ pcgcctl.b.rstpdwnmodule = 1;
++ DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
++ }
++
++ /* Restore GUSBCFG and DCFG */
++ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg,
++ core_if->gr_backup->gusbcfg_local);
++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg,
++ core_if->dr_backup->dcfg);
++
++ /* De-assert Wakeup Logic */
++ gpwrdn.d32 = 0;
++ gpwrdn.b.pmuactv = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++ dwc_udelay(10);
++
++ if (!rem_wakeup) {
++ /* Set Device programming done bit */
++ dctl.b.pwronprgdone = 1;
++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
++ } else {
++ /* Start Remote Wakeup Signaling */
++ dctl.d32 = core_if->dr_backup->dctl;
++ dctl.b.rmtwkupsig = 1;
++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
++ }
++
++ dwc_mdelay(2);
++ /* Clear all pending interupts */
++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
++
++ /* Restore global registers */
++ dwc_otg_restore_global_regs(core_if);
++ /* Restore device global registers */
++ dwc_otg_restore_dev_regs(core_if, rem_wakeup);
++
++ if (rem_wakeup) {
++ dwc_mdelay(7);
++ dctl.d32 = 0;
++ dctl.b.rmtwkupsig = 1;
++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, 0);
++ }
++
++ core_if->hibernation_suspend = 0;
++ /* The core will be in ON STATE */
++ core_if->lx_state = DWC_OTG_L0;
++ DWC_PRINTF("Hibernation recovery completes here\n");
++
++ return 1;
++}
++
++/*
++ * The restore operation is modified to support Synopsys Emulated Powerdown and
++ * Hibernation. This function is for exiting from Host mode hibernation by
++ * Host Initiated Resume/Reset and Device Initiated Remote-Wakeup.
++ * @param core_if Programming view of DWC_otg controller.
++ * @param rem_wakeup - indicates whether resume is initiated by Device or Host.
++ * @param reset - indicates whether resume is initiated by Reset.
++ */
++int dwc_otg_host_hibernation_restore(dwc_otg_core_if_t * core_if,
++ int rem_wakeup, int reset)
++{
++ gpwrdn_data_t gpwrdn = {.d32 = 0 };
++ hprt0_data_t hprt0 = {.d32 = 0 };
++
++ int timeout = 2000;
++
++ DWC_DEBUGPL(DBG_HCD, "%s called\n", __FUNCTION__);
++ /* Switch-on voltage to the core */
++ gpwrdn.b.pwrdnswtch = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++ dwc_udelay(10);
++
++ /* Reset core */
++ gpwrdn.d32 = 0;
++ gpwrdn.b.pwrdnrstn = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++ dwc_udelay(10);
++
++ /* Assert Restore signal */
++ gpwrdn.d32 = 0;
++ gpwrdn.b.restore = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
++ dwc_udelay(10);
++
++ /* Disable power clamps */
++ gpwrdn.d32 = 0;
++ gpwrdn.b.pwrdnclmp = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++
++ if (!rem_wakeup) {
++ dwc_udelay(50);
++ }
++
++ /* Deassert Reset core */
++ gpwrdn.d32 = 0;
++ gpwrdn.b.pwrdnrstn = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
++ dwc_udelay(10);
++
++ /* Disable PMU interrupt */
++ gpwrdn.d32 = 0;
++ gpwrdn.b.pmuintsel = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++
++ gpwrdn.d32 = 0;
++ gpwrdn.b.connect_det_msk = 1;
++ gpwrdn.b.srp_det_msk = 1;
++ gpwrdn.b.disconn_det_msk = 1;
++ gpwrdn.b.rst_det_msk = 1;
++ gpwrdn.b.lnstchng_msk = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++
++ /* Indicates that we are going out from hibernation */
++ core_if->hibernation_suspend = 0;
++
++ /* Set Restore Essential Regs bit in PCGCCTL register */
++ restore_essential_regs(core_if, rem_wakeup, 1);
++
++ /* Wait a little for seeing new value of variable hibernation_suspend if
++ * Restore done interrupt received before polling */
++ dwc_udelay(10);
++
++ if (core_if->hibernation_suspend == 0) {
++ /* Wait For Restore_done Interrupt. This mechanism of polling the
++ * interrupt is introduced to avoid any possible race conditions
++ */
++ do {
++ gintsts_data_t gintsts;
++ gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
++ if (gintsts.b.restoredone) {
++ gintsts.d32 = 0;
++ gintsts.b.restoredone = 1;
++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
++ DWC_DEBUGPL(DBG_HCD,"Restore Done Interrupt seen\n");
++ break;
++ }
++ dwc_udelay(10);
++ } while (--timeout);
++ if (!timeout) {
++ DWC_WARN("Restore Done interrupt wasn't generated\n");
++ }
++ }
++
++ /* Set the flag's value to 0 again after receiving restore done interrupt */
++ core_if->hibernation_suspend = 0;
++
++ /* This step is not described in functional spec but if not wait for this
++ * delay, mismatch interrupts occurred because just after restore core is
++ * in Device mode(gintsts.curmode == 0) */
++ dwc_mdelay(100);
++
++ /* Clear all pending interrupts */
++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
++
++ /* De-assert Restore */
++ gpwrdn.d32 = 0;
++ gpwrdn.b.restore = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++ dwc_udelay(10);
++
++ /* Restore GUSBCFG and HCFG */
++ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg,
++ core_if->gr_backup->gusbcfg_local);
++ DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg,
++ core_if->hr_backup->hcfg_local);
++
++ /* De-assert Wakeup Logic */
++ gpwrdn.d32 = 0;
++ gpwrdn.b.pmuactv = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++ dwc_udelay(10);
++
++ /* Start the Resume operation by programming HPRT0 */
++ hprt0.d32 = core_if->hr_backup->hprt0_local;
++ hprt0.b.prtpwr = 1;
++ hprt0.b.prtena = 0;
++ hprt0.b.prtsusp = 0;
++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
++
++ DWC_PRINTF("Resume Starts Now\n");
++ if (!reset) { // Indicates it is Resume Operation
++ hprt0.d32 = core_if->hr_backup->hprt0_local;
++ hprt0.b.prtres = 1;
++ hprt0.b.prtpwr = 1;
++ hprt0.b.prtena = 0;
++ hprt0.b.prtsusp = 0;
++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
++
++ if (!rem_wakeup)
++ hprt0.b.prtres = 0;
++ /* Wait for Resume time and then program HPRT again */
++ dwc_mdelay(100);
++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
++
++ } else { // Indicates it is Reset Operation
++ hprt0.d32 = core_if->hr_backup->hprt0_local;
++ hprt0.b.prtrst = 1;
++ hprt0.b.prtpwr = 1;
++ hprt0.b.prtena = 0;
++ hprt0.b.prtsusp = 0;
++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
++ /* Wait for Reset time and then program HPRT again */
++ dwc_mdelay(60);
++ hprt0.b.prtrst = 0;
++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
++ }
++ /* Clear all interrupt status */
++ hprt0.d32 = dwc_otg_read_hprt0(core_if);
++ hprt0.b.prtconndet = 1;
++ hprt0.b.prtenchng = 1;
++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
++
++ /* Clear all pending interupts */
++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
++
++ /* Restore global registers */
++ dwc_otg_restore_global_regs(core_if);
++ /* Restore host global registers */
++ dwc_otg_restore_host_regs(core_if, reset);
++
++ /* The core will be in ON STATE */
++ core_if->lx_state = DWC_OTG_L0;
++ DWC_PRINTF("Hibernation recovery is complete here\n");
++ return 0;
++}
++
++/** Saves some register values into system memory. */
++int dwc_otg_save_global_regs(dwc_otg_core_if_t * core_if)
++{
++ struct dwc_otg_global_regs_backup *gr;
++ int i;
++
++ gr = core_if->gr_backup;
++ if (!gr) {
++ gr = DWC_ALLOC(sizeof(*gr));
++ if (!gr) {
++ return -DWC_E_NO_MEMORY;
++ }
++ core_if->gr_backup = gr;
++ }
++
++ gr->gotgctl_local = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
++ gr->gintmsk_local = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
++ gr->gahbcfg_local = DWC_READ_REG32(&core_if->core_global_regs->gahbcfg);
++ gr->gusbcfg_local = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
++ gr->grxfsiz_local = DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
++ gr->gnptxfsiz_local = DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz);
++ gr->hptxfsiz_local = DWC_READ_REG32(&core_if->core_global_regs->hptxfsiz);
++#ifdef CONFIG_USB_DWC_OTG_LPM
++ gr->glpmcfg_local = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
++#endif
++ gr->gi2cctl_local = DWC_READ_REG32(&core_if->core_global_regs->gi2cctl);
++ gr->pcgcctl_local = DWC_READ_REG32(core_if->pcgcctl);
++ gr->gdfifocfg_local =
++ DWC_READ_REG32(&core_if->core_global_regs->gdfifocfg);
++ for (i = 0; i < MAX_EPS_CHANNELS; i++) {
++ gr->dtxfsiz_local[i] =
++ DWC_READ_REG32(&(core_if->core_global_regs->dtxfsiz[i]));
++ }
++
++ DWC_DEBUGPL(DBG_ANY, "===========Backing Global registers==========\n");
++ DWC_DEBUGPL(DBG_ANY, "Backed up gotgctl = %08x\n", gr->gotgctl_local);
++ DWC_DEBUGPL(DBG_ANY, "Backed up gintmsk = %08x\n", gr->gintmsk_local);
++ DWC_DEBUGPL(DBG_ANY, "Backed up gahbcfg = %08x\n", gr->gahbcfg_local);
++ DWC_DEBUGPL(DBG_ANY, "Backed up gusbcfg = %08x\n", gr->gusbcfg_local);
++ DWC_DEBUGPL(DBG_ANY, "Backed up grxfsiz = %08x\n", gr->grxfsiz_local);
++ DWC_DEBUGPL(DBG_ANY, "Backed up gnptxfsiz = %08x\n",
++ gr->gnptxfsiz_local);
++ DWC_DEBUGPL(DBG_ANY, "Backed up hptxfsiz = %08x\n",
++ gr->hptxfsiz_local);
++#ifdef CONFIG_USB_DWC_OTG_LPM
++ DWC_DEBUGPL(DBG_ANY, "Backed up glpmcfg = %08x\n", gr->glpmcfg_local);
++#endif
++ DWC_DEBUGPL(DBG_ANY, "Backed up gi2cctl = %08x\n", gr->gi2cctl_local);
++ DWC_DEBUGPL(DBG_ANY, "Backed up pcgcctl = %08x\n", gr->pcgcctl_local);
++ DWC_DEBUGPL(DBG_ANY,"Backed up gdfifocfg = %08x\n",gr->gdfifocfg_local);
++
++ return 0;
++}
++
++/** Saves GINTMSK register before setting the msk bits. */
++int dwc_otg_save_gintmsk_reg(dwc_otg_core_if_t * core_if)
++{
++ struct dwc_otg_global_regs_backup *gr;
++
++ gr = core_if->gr_backup;
++ if (!gr) {
++ gr = DWC_ALLOC(sizeof(*gr));
++ if (!gr) {
++ return -DWC_E_NO_MEMORY;
++ }
++ core_if->gr_backup = gr;
++ }
++
++ gr->gintmsk_local = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
++
++ DWC_DEBUGPL(DBG_ANY,"=============Backing GINTMSK registers============\n");
++ DWC_DEBUGPL(DBG_ANY, "Backed up gintmsk = %08x\n", gr->gintmsk_local);
++
++ return 0;
++}
++
++int dwc_otg_save_dev_regs(dwc_otg_core_if_t * core_if)
++{
++ struct dwc_otg_dev_regs_backup *dr;
++ int i;
++
++ dr = core_if->dr_backup;
++ if (!dr) {
++ dr = DWC_ALLOC(sizeof(*dr));
++ if (!dr) {
++ return -DWC_E_NO_MEMORY;
++ }
++ core_if->dr_backup = dr;
++ }
++
++ dr->dcfg = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
++ dr->dctl = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
++ dr->daintmsk =
++ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daintmsk);
++ dr->diepmsk =
++ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->diepmsk);
++ dr->doepmsk =
++ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->doepmsk);
++
++ for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
++ dr->diepctl[i] =
++ DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->diepctl);
++ dr->dieptsiz[i] =
++ DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->dieptsiz);
++ dr->diepdma[i] =
++ DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->diepdma);
++ }
++
++ DWC_DEBUGPL(DBG_ANY,
++ "=============Backing Host registers==============\n");
++ DWC_DEBUGPL(DBG_ANY, "Backed up dcfg = %08x\n", dr->dcfg);
++ DWC_DEBUGPL(DBG_ANY, "Backed up dctl = %08x\n", dr->dctl);
++ DWC_DEBUGPL(DBG_ANY, "Backed up daintmsk = %08x\n",
++ dr->daintmsk);
++ DWC_DEBUGPL(DBG_ANY, "Backed up diepmsk = %08x\n", dr->diepmsk);
++ DWC_DEBUGPL(DBG_ANY, "Backed up doepmsk = %08x\n", dr->doepmsk);
++ for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
++ DWC_DEBUGPL(DBG_ANY, "Backed up diepctl[%d] = %08x\n", i,
++ dr->diepctl[i]);
++ DWC_DEBUGPL(DBG_ANY, "Backed up dieptsiz[%d] = %08x\n",
++ i, dr->dieptsiz[i]);
++ DWC_DEBUGPL(DBG_ANY, "Backed up diepdma[%d] = %08x\n", i,
++ dr->diepdma[i]);
++ }
++
++ return 0;
++}
++
++int dwc_otg_save_host_regs(dwc_otg_core_if_t * core_if)
++{
++ struct dwc_otg_host_regs_backup *hr;
++ int i;
++
++ hr = core_if->hr_backup;
++ if (!hr) {
++ hr = DWC_ALLOC(sizeof(*hr));
++ if (!hr) {
++ return -DWC_E_NO_MEMORY;
++ }
++ core_if->hr_backup = hr;
++ }
++
++ hr->hcfg_local =
++ DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
++ hr->haintmsk_local =
++ DWC_READ_REG32(&core_if->host_if->host_global_regs->haintmsk);
++ for (i = 0; i < dwc_otg_get_param_host_channels(core_if); ++i) {
++ hr->hcintmsk_local[i] =
++ DWC_READ_REG32(&core_if->host_if->hc_regs[i]->hcintmsk);
++ }
++ hr->hprt0_local = DWC_READ_REG32(core_if->host_if->hprt0);
++ hr->hfir_local =
++ DWC_READ_REG32(&core_if->host_if->host_global_regs->hfir);
++
++ DWC_DEBUGPL(DBG_ANY,
++ "=============Backing Host registers===============\n");
++ DWC_DEBUGPL(DBG_ANY, "Backed up hcfg = %08x\n",
++ hr->hcfg_local);
++ DWC_DEBUGPL(DBG_ANY, "Backed up haintmsk = %08x\n", hr->haintmsk_local);
++ for (i = 0; i < dwc_otg_get_param_host_channels(core_if); ++i) {
++ DWC_DEBUGPL(DBG_ANY, "Backed up hcintmsk[%02d]=%08x\n", i,
++ hr->hcintmsk_local[i]);
++ }
++ DWC_DEBUGPL(DBG_ANY, "Backed up hprt0 = %08x\n",
++ hr->hprt0_local);
++ DWC_DEBUGPL(DBG_ANY, "Backed up hfir = %08x\n",
++ hr->hfir_local);
++
++ return 0;
++}
++
++int dwc_otg_restore_global_regs(dwc_otg_core_if_t *core_if)
++{
++ struct dwc_otg_global_regs_backup *gr;
++ int i;
++
++ gr = core_if->gr_backup;
++ if (!gr) {
++ return -DWC_E_INVALID;
++ }
++
++ DWC_WRITE_REG32(&core_if->core_global_regs->gotgctl, gr->gotgctl_local);
++ DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gr->gintmsk_local);
++ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gr->gusbcfg_local);
++ DWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg, gr->gahbcfg_local);
++ DWC_WRITE_REG32(&core_if->core_global_regs->grxfsiz, gr->grxfsiz_local);
++ DWC_WRITE_REG32(&core_if->core_global_regs->gnptxfsiz,
++ gr->gnptxfsiz_local);
++ DWC_WRITE_REG32(&core_if->core_global_regs->hptxfsiz,
++ gr->hptxfsiz_local);
++ DWC_WRITE_REG32(&core_if->core_global_regs->gdfifocfg,
++ gr->gdfifocfg_local);
++ for (i = 0; i < MAX_EPS_CHANNELS; i++) {
++ DWC_WRITE_REG32(&core_if->core_global_regs->dtxfsiz[i],
++ gr->dtxfsiz_local[i]);
++ }
++
++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
++ DWC_WRITE_REG32(core_if->host_if->hprt0, 0x0000100A);
++ DWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg,
++ (gr->gahbcfg_local));
++ return 0;
++}
++
++int dwc_otg_restore_dev_regs(dwc_otg_core_if_t * core_if, int rem_wakeup)
++{
++ struct dwc_otg_dev_regs_backup *dr;
++ int i;
++
++ dr = core_if->dr_backup;
++
++ if (!dr) {
++ return -DWC_E_INVALID;
++ }
++
++ if (!rem_wakeup) {
++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl,
++ dr->dctl);
++ }
++
++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->daintmsk, dr->daintmsk);
++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->diepmsk, dr->diepmsk);
++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->doepmsk, dr->doepmsk);
++
++ for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
++ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->dieptsiz, dr->dieptsiz[i]);
++ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->diepdma, dr->diepdma[i]);
++ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->diepctl, dr->diepctl[i]);
++ }
++
++ return 0;
++}
++
++int dwc_otg_restore_host_regs(dwc_otg_core_if_t * core_if, int reset)
++{
++ struct dwc_otg_host_regs_backup *hr;
++ int i;
++ hr = core_if->hr_backup;
++
++ if (!hr) {
++ return -DWC_E_INVALID;
++ }
++
++ DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg, hr->hcfg_local);
++ //if (!reset)
++ //{
++ // DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hfir, hr->hfir_local);
++ //}
++
++ DWC_WRITE_REG32(&core_if->host_if->host_global_regs->haintmsk,
++ hr->haintmsk_local);
++ for (i = 0; i < dwc_otg_get_param_host_channels(core_if); ++i) {
++ DWC_WRITE_REG32(&core_if->host_if->hc_regs[i]->hcintmsk,
++ hr->hcintmsk_local[i]);
++ }
++
++ return 0;
++}
++
++int restore_lpm_i2c_regs(dwc_otg_core_if_t * core_if)
++{
++ struct dwc_otg_global_regs_backup *gr;
++
++ gr = core_if->gr_backup;
++
++ /* Restore values for LPM and I2C */
++#ifdef CONFIG_USB_DWC_OTG_LPM
++ DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, gr->glpmcfg_local);
++#endif
++ DWC_WRITE_REG32(&core_if->core_global_regs->gi2cctl, gr->gi2cctl_local);
++
++ return 0;
++}
++
++int restore_essential_regs(dwc_otg_core_if_t * core_if, int rmode, int is_host)
++{
++ struct dwc_otg_global_regs_backup *gr;
++ pcgcctl_data_t pcgcctl = {.d32 = 0 };
++ gahbcfg_data_t gahbcfg = {.d32 = 0 };
++ gusbcfg_data_t gusbcfg = {.d32 = 0 };
++ gintmsk_data_t gintmsk = {.d32 = 0 };
++
++ /* Restore LPM and I2C registers */
++ restore_lpm_i2c_regs(core_if);
++
++ /* Set PCGCCTL to 0 */
++ DWC_WRITE_REG32(core_if->pcgcctl, 0x00000000);
++
++ gr = core_if->gr_backup;
++ /* Load restore values for [31:14] bits */
++ DWC_WRITE_REG32(core_if->pcgcctl,
++ ((gr->pcgcctl_local & 0xffffc000) | 0x00020000));
++
++ /* Umnask global Interrupt in GAHBCFG and restore it */
++ gahbcfg.d32 = gr->gahbcfg_local;
++ gahbcfg.b.glblintrmsk = 1;
++ DWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg, gahbcfg.d32);
++
++ /* Clear all pending interupts */
++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
++
++ /* Unmask restore done interrupt */
++ gintmsk.b.restoredone = 1;
++ DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32);
++
++ /* Restore GUSBCFG and HCFG/DCFG */
++ gusbcfg.d32 = core_if->gr_backup->gusbcfg_local;
++ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gusbcfg.d32);
++
++ if (is_host) {
++ hcfg_data_t hcfg = {.d32 = 0 };
++ hcfg.d32 = core_if->hr_backup->hcfg_local;
++ DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg,
++ hcfg.d32);
++
++ /* Load restore values for [31:14] bits */
++ pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000;
++ pcgcctl.d32 = gr->pcgcctl_local | 0x00020000;
++
++ if (rmode)
++ pcgcctl.b.restoremode = 1;
++ DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
++ dwc_udelay(10);
++
++ /* Load restore values for [31:14] bits and set EssRegRestored bit */
++ pcgcctl.d32 = gr->pcgcctl_local | 0xffffc000;
++ pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000;
++ pcgcctl.b.ess_reg_restored = 1;
++ if (rmode)
++ pcgcctl.b.restoremode = 1;
++ DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
++ } else {
++ dcfg_data_t dcfg = {.d32 = 0 };
++ dcfg.d32 = core_if->dr_backup->dcfg;
++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32);
++
++ /* Load restore values for [31:14] bits */
++ pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000;
++ pcgcctl.d32 = gr->pcgcctl_local | 0x00020000;
++ if (!rmode) {
++ pcgcctl.d32 |= 0x208;
++ }
++ DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
++ dwc_udelay(10);
++
++ /* Load restore values for [31:14] bits */
++ pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000;
++ pcgcctl.d32 = gr->pcgcctl_local | 0x00020000;
++ pcgcctl.b.ess_reg_restored = 1;
++ if (!rmode)
++ pcgcctl.d32 |= 0x208;
++ DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
++ }
++
++ return 0;
++}
++
++/**
++ * Initializes the FSLSPClkSel field of the HCFG register depending on the PHY
++ * type.
++ */
++static void init_fslspclksel(dwc_otg_core_if_t * core_if)
++{
++ uint32_t val;
++ hcfg_data_t hcfg;
++
++ if (((core_if->hwcfg2.b.hs_phy_type == 2) &&
++ (core_if->hwcfg2.b.fs_phy_type == 1) &&
++ (core_if->core_params->ulpi_fs_ls)) ||
++ (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
++ /* Full speed PHY */
++ val = DWC_HCFG_48_MHZ;
++ } else {
++ /* High speed PHY running at full speed or high speed */
++ val = DWC_HCFG_30_60_MHZ;
++ }
++
++ DWC_DEBUGPL(DBG_CIL, "Initializing HCFG.FSLSPClkSel to 0x%1x\n", val);
++ hcfg.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
++ hcfg.b.fslspclksel = val;
++ DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg, hcfg.d32);
++}
++
++/**
++ * Initializes the DevSpd field of the DCFG register depending on the PHY type
++ * and the enumeration speed of the device.
++ */
++static void init_devspd(dwc_otg_core_if_t * core_if)
++{
++ uint32_t val;
++ dcfg_data_t dcfg;
++
++ if (((core_if->hwcfg2.b.hs_phy_type == 2) &&
++ (core_if->hwcfg2.b.fs_phy_type == 1) &&
++ (core_if->core_params->ulpi_fs_ls)) ||
++ (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
++ /* Full speed PHY */
++ val = 0x3;
++ } else if (core_if->core_params->speed == DWC_SPEED_PARAM_FULL) {
++ /* High speed PHY running at full speed */
++ val = 0x1;
++ } else {
++ /* High speed PHY running at high speed */
++ val = 0x0;
++ }
++
++ DWC_DEBUGPL(DBG_CIL, "Initializing DCFG.DevSpd to 0x%1x\n", val);
++
++ dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
++ dcfg.b.devspd = val;
++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32);
++}
++
++/**
++ * This function calculates the number of IN EPS
++ * using GHWCFG1 and GHWCFG2 registers values
++ *
++ * @param core_if Programming view of the DWC_otg controller
++ */
++static uint32_t calc_num_in_eps(dwc_otg_core_if_t * core_if)
++{
++ uint32_t num_in_eps = 0;
++ uint32_t num_eps = core_if->hwcfg2.b.num_dev_ep;
++ uint32_t hwcfg1 = core_if->hwcfg1.d32 >> 3;
++ uint32_t num_tx_fifos = core_if->hwcfg4.b.num_in_eps;
++ int i;
++
++ for (i = 0; i < num_eps; ++i) {
++ if (!(hwcfg1 & 0x1))
++ num_in_eps++;
++
++ hwcfg1 >>= 2;
++ }
++
++ if (core_if->hwcfg4.b.ded_fifo_en) {
++ num_in_eps =
++ (num_in_eps > num_tx_fifos) ? num_tx_fifos : num_in_eps;
++ }
++
++ return num_in_eps;
++}
++
++/**
++ * This function calculates the number of OUT EPS
++ * using GHWCFG1 and GHWCFG2 registers values
++ *
++ * @param core_if Programming view of the DWC_otg controller
++ */
++static uint32_t calc_num_out_eps(dwc_otg_core_if_t * core_if)
++{
++ uint32_t num_out_eps = 0;
++ uint32_t num_eps = core_if->hwcfg2.b.num_dev_ep;
++ uint32_t hwcfg1 = core_if->hwcfg1.d32 >> 2;
++ int i;
++
++ for (i = 0; i < num_eps; ++i) {
++ if (!(hwcfg1 & 0x1))
++ num_out_eps++;
++
++ hwcfg1 >>= 2;
++ }
++ return num_out_eps;
++}
++
++/**
++ * This function initializes the DWC_otg controller registers and
++ * prepares the core for device mode or host mode operation.
++ *
++ * @param core_if Programming view of the DWC_otg controller
++ *
++ */
++void dwc_otg_core_init(dwc_otg_core_if_t * core_if)
++{
++ int i = 0;
++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
++ dwc_otg_dev_if_t *dev_if = core_if->dev_if;
++ gahbcfg_data_t ahbcfg = {.d32 = 0 };
++ gusbcfg_data_t usbcfg = {.d32 = 0 };
++ gi2cctl_data_t i2cctl = {.d32 = 0 };
++
++ DWC_DEBUGPL(DBG_CILV, "dwc_otg_core_init(%p) regs at %p\n",
++ core_if, global_regs);
++
++ /* Common Initialization */
++ usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
++
++ /* Program the ULPI External VBUS bit if needed */
++ usbcfg.b.ulpi_ext_vbus_drv =
++ (core_if->core_params->phy_ulpi_ext_vbus ==
++ DWC_PHY_ULPI_EXTERNAL_VBUS) ? 1 : 0;
++
++ /* Set external TS Dline pulsing */
++ usbcfg.b.term_sel_dl_pulse =
++ (core_if->core_params->ts_dline == 1) ? 1 : 0;
++ DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
++
++ /* Reset the Controller */
++ dwc_otg_core_reset(core_if);
++
++ core_if->adp_enable = core_if->core_params->adp_supp_enable;
++ core_if->power_down = core_if->core_params->power_down;
++ core_if->otg_sts = 0;
++
++ /* Initialize parameters from Hardware configuration registers. */
++ dev_if->num_in_eps = calc_num_in_eps(core_if);
++ dev_if->num_out_eps = calc_num_out_eps(core_if);
++
++ DWC_DEBUGPL(DBG_CIL, "num_dev_perio_in_ep=%d\n",
++ core_if->hwcfg4.b.num_dev_perio_in_ep);
++
++ for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; i++) {
++ dev_if->perio_tx_fifo_size[i] =
++ DWC_READ_REG32(&global_regs->dtxfsiz[i]) >> 16;
++ DWC_DEBUGPL(DBG_CIL, "Periodic Tx FIFO SZ #%d=0x%0x\n",
++ i, dev_if->perio_tx_fifo_size[i]);
++ }
++
++ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
++ dev_if->tx_fifo_size[i] =
++ DWC_READ_REG32(&global_regs->dtxfsiz[i]) >> 16;
++ DWC_DEBUGPL(DBG_CIL, "Tx FIFO SZ #%d=0x%0x\n",
++ i, dev_if->tx_fifo_size[i]);
++ }
++
++ core_if->total_fifo_size = core_if->hwcfg3.b.dfifo_depth;
++ core_if->rx_fifo_size = DWC_READ_REG32(&global_regs->grxfsiz);
++ core_if->nperio_tx_fifo_size =
++ DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16;
++
++ DWC_DEBUGPL(DBG_CIL, "Total FIFO SZ=%d\n", core_if->total_fifo_size);
++ DWC_DEBUGPL(DBG_CIL, "Rx FIFO SZ=%d\n", core_if->rx_fifo_size);
++ DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO SZ=%d\n",
++ core_if->nperio_tx_fifo_size);
++
++ /* This programming sequence needs to happen in FS mode before any other
++ * programming occurs */
++ if ((core_if->core_params->speed == DWC_SPEED_PARAM_FULL) &&
++ (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
++ /* If FS mode with FS PHY */
++
++ /* core_init() is now called on every switch so only call the
++ * following for the first time through. */
++ if (!core_if->phy_init_done) {
++ core_if->phy_init_done = 1;
++ DWC_DEBUGPL(DBG_CIL, "FS_PHY detected\n");
++ usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
++ usbcfg.b.physel = 1;
++ DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
++
++ /* Reset after a PHY select */
++ dwc_otg_core_reset(core_if);
++ }
++
++ /* Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also
++ * do this on HNP Dev/Host mode switches (done in dev_init and
++ * host_init). */
++ if (dwc_otg_is_host_mode(core_if)) {
++ init_fslspclksel(core_if);
++ } else {
++ init_devspd(core_if);
++ }
++
++ if (core_if->core_params->i2c_enable) {
++ DWC_DEBUGPL(DBG_CIL, "FS_PHY Enabling I2c\n");
++ /* Program GUSBCFG.OtgUtmifsSel to I2C */
++ usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
++ usbcfg.b.otgutmifssel = 1;
++ DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
++
++ /* Program GI2CCTL.I2CEn */
++ i2cctl.d32 = DWC_READ_REG32(&global_regs->gi2cctl);
++ i2cctl.b.i2cdevaddr = 1;
++ i2cctl.b.i2cen = 0;
++ DWC_WRITE_REG32(&global_regs->gi2cctl, i2cctl.d32);
++ i2cctl.b.i2cen = 1;
++ DWC_WRITE_REG32(&global_regs->gi2cctl, i2cctl.d32);
++ }
++
++ } /* endif speed == DWC_SPEED_PARAM_FULL */
++ else {
++ /* High speed PHY. */
++ if (!core_if->phy_init_done) {
++ core_if->phy_init_done = 1;
++ /* HS PHY parameters. These parameters are preserved
++ * during soft reset so only program the first time. Do
++ * a soft reset immediately after setting phyif. */
++
++ if (core_if->core_params->phy_type == 2) {
++ /* ULPI interface */
++ usbcfg.b.ulpi_utmi_sel = 1;
++ usbcfg.b.phyif = 0;
++ usbcfg.b.ddrsel =
++ core_if->core_params->phy_ulpi_ddr;
++ } else if (core_if->core_params->phy_type == 1) {
++ /* UTMI+ interface */
++ usbcfg.b.ulpi_utmi_sel = 0;
++ if (core_if->core_params->phy_utmi_width == 16) {
++ usbcfg.b.phyif = 1;
++
++ } else {
++ usbcfg.b.phyif = 0;
++ }
++ } else {
++ DWC_ERROR("FS PHY TYPE\n");
++ }
++ DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
++ /* Reset after setting the PHY parameters */
++ dwc_otg_core_reset(core_if);
++ }
++ }
++
++ if ((core_if->hwcfg2.b.hs_phy_type == 2) &&
++ (core_if->hwcfg2.b.fs_phy_type == 1) &&
++ (core_if->core_params->ulpi_fs_ls)) {
++ DWC_DEBUGPL(DBG_CIL, "Setting ULPI FSLS\n");
++ usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
++ usbcfg.b.ulpi_fsls = 1;
++ usbcfg.b.ulpi_clk_sus_m = 1;
++ DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
++ } else {
++ usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
++ usbcfg.b.ulpi_fsls = 0;
++ usbcfg.b.ulpi_clk_sus_m = 0;
++ DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
++ }
++
++ /* Program the GAHBCFG Register. */
++ switch (core_if->hwcfg2.b.architecture) {
++
++ case DWC_SLAVE_ONLY_ARCH:
++ DWC_DEBUGPL(DBG_CIL, "Slave Only Mode\n");
++ ahbcfg.b.nptxfemplvl_txfemplvl =
++ DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY;
++ ahbcfg.b.ptxfemplvl = DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY;
++ core_if->dma_enable = 0;
++ core_if->dma_desc_enable = 0;
++ break;
++
++ case DWC_EXT_DMA_ARCH:
++ DWC_DEBUGPL(DBG_CIL, "External DMA Mode\n");
++ {
++ uint8_t brst_sz = core_if->core_params->dma_burst_size;
++ ahbcfg.b.hburstlen = 0;
++ while (brst_sz > 1) {
++ ahbcfg.b.hburstlen++;
++ brst_sz >>= 1;
++ }
++ }
++ core_if->dma_enable = (core_if->core_params->dma_enable != 0);
++ core_if->dma_desc_enable =
++ (core_if->core_params->dma_desc_enable != 0);
++ break;
++
++ case DWC_INT_DMA_ARCH:
++ DWC_DEBUGPL(DBG_CIL, "Internal DMA Mode\n");
++ /* Old value was DWC_GAHBCFG_INT_DMA_BURST_INCR - done for
++ Host mode ISOC in issue fix - vahrama */
++ /* Broadcom had altered to (1<<3)|(0<<0) - WRESP=1, max 4 beats */
++ ahbcfg.b.hburstlen = (1<<3)|(0<<0);//DWC_GAHBCFG_INT_DMA_BURST_INCR4;
++ core_if->dma_enable = (core_if->core_params->dma_enable != 0);
++ core_if->dma_desc_enable =
++ (core_if->core_params->dma_desc_enable != 0);
++ break;
++
++ }
++ if (core_if->dma_enable) {
++ if (core_if->dma_desc_enable) {
++ DWC_PRINTF("Using Descriptor DMA mode\n");
++ } else {
++ DWC_PRINTF("Using Buffer DMA mode\n");
++
++ }
++ } else {
++ DWC_PRINTF("Using Slave mode\n");
++ core_if->dma_desc_enable = 0;
++ }
++
++ if (core_if->core_params->ahb_single) {
++ ahbcfg.b.ahbsingle = 1;
++ }
++
++ ahbcfg.b.dmaenable = core_if->dma_enable;
++ DWC_WRITE_REG32(&global_regs->gahbcfg, ahbcfg.d32);
++
++ core_if->en_multiple_tx_fifo = core_if->hwcfg4.b.ded_fifo_en;
++
++ core_if->pti_enh_enable = core_if->core_params->pti_enable != 0;
++ core_if->multiproc_int_enable = core_if->core_params->mpi_enable;
++ DWC_PRINTF("Periodic Transfer Interrupt Enhancement - %s\n",
++ ((core_if->pti_enh_enable) ? "enabled" : "disabled"));
++ DWC_PRINTF("Multiprocessor Interrupt Enhancement - %s\n",
++ ((core_if->multiproc_int_enable) ? "enabled" : "disabled"));
++
++ /*
++ * Program the GUSBCFG register.
++ */
++ usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
++
++ switch (core_if->hwcfg2.b.op_mode) {
++ case DWC_MODE_HNP_SRP_CAPABLE:
++ usbcfg.b.hnpcap = (core_if->core_params->otg_cap ==
++ DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE);
++ usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
++ DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
++ break;
++
++ case DWC_MODE_SRP_ONLY_CAPABLE:
++ usbcfg.b.hnpcap = 0;
++ usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
++ DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
++ break;
++
++ case DWC_MODE_NO_HNP_SRP_CAPABLE:
++ usbcfg.b.hnpcap = 0;
++ usbcfg.b.srpcap = 0;
++ break;
++
++ case DWC_MODE_SRP_CAPABLE_DEVICE:
++ usbcfg.b.hnpcap = 0;
++ usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
++ DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
++ break;
++
++ case DWC_MODE_NO_SRP_CAPABLE_DEVICE:
++ usbcfg.b.hnpcap = 0;
++ usbcfg.b.srpcap = 0;
++ break;
++
++ case DWC_MODE_SRP_CAPABLE_HOST:
++ usbcfg.b.hnpcap = 0;
++ usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
++ DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
++ break;
++
++ case DWC_MODE_NO_SRP_CAPABLE_HOST:
++ usbcfg.b.hnpcap = 0;
++ usbcfg.b.srpcap = 0;
++ break;
++ }
++
++ DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
++
++#ifdef CONFIG_USB_DWC_OTG_LPM
++ if (core_if->core_params->lpm_enable) {
++ glpmcfg_data_t lpmcfg = {.d32 = 0 };
++
++ /* To enable LPM support set lpm_cap_en bit */
++ lpmcfg.b.lpm_cap_en = 1;
++
++ /* Make AppL1Res ACK */
++ lpmcfg.b.appl_resp = 1;
++
++ /* Retry 3 times */
++ lpmcfg.b.retry_count = 3;
++
++ DWC_MODIFY_REG32(&core_if->core_global_regs->glpmcfg,
++ 0, lpmcfg.d32);
++
++ }
++#endif
++ if (core_if->core_params->ic_usb_cap) {
++ gusbcfg_data_t gusbcfg = {.d32 = 0 };
++ gusbcfg.b.ic_usb_cap = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gusbcfg,
++ 0, gusbcfg.d32);
++ }
++ {
++ gotgctl_data_t gotgctl = {.d32 = 0 };
++ gotgctl.b.otgver = core_if->core_params->otg_ver;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gotgctl, 0,
++ gotgctl.d32);
++ /* Set OTG version supported */
++ core_if->otg_ver = core_if->core_params->otg_ver;
++ DWC_PRINTF("OTG VER PARAM: %d, OTG VER FLAG: %d\n",
++ core_if->core_params->otg_ver, core_if->otg_ver);
++ }
++
++
++ /* Enable common interrupts */
++ dwc_otg_enable_common_interrupts(core_if);
++
++ /* Do device or host intialization based on mode during PCD
++ * and HCD initialization */
++ if (dwc_otg_is_host_mode(core_if)) {
++ DWC_DEBUGPL(DBG_ANY, "Host Mode\n");
++ core_if->op_state = A_HOST;
++ } else {
++ DWC_DEBUGPL(DBG_ANY, "Device Mode\n");
++ core_if->op_state = B_PERIPHERAL;
++#ifdef DWC_DEVICE_ONLY
++ dwc_otg_core_dev_init(core_if);
++#endif
++ }
++}
++
++/**
++ * This function enables the Device mode interrupts.
++ *
++ * @param core_if Programming view of DWC_otg controller
++ */
++void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t * core_if)
++{
++ gintmsk_data_t intr_mask = {.d32 = 0 };
++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
++
++ DWC_DEBUGPL(DBG_CIL, "%s()\n", __func__);
++
++ /* Disable all interrupts. */
++ DWC_WRITE_REG32(&global_regs->gintmsk, 0);
++
++ /* Clear any pending interrupts */
++ DWC_WRITE_REG32(&global_regs->gintsts, 0xFFFFFFFF);
++
++ /* Enable the common interrupts */
++ dwc_otg_enable_common_interrupts(core_if);
++
++ /* Enable interrupts */
++ intr_mask.b.usbreset = 1;
++ intr_mask.b.enumdone = 1;
++ /* Disable Disconnect interrupt in Device mode */
++ intr_mask.b.disconnect = 0;
++
++ if (!core_if->multiproc_int_enable) {
++ intr_mask.b.inepintr = 1;
++ intr_mask.b.outepintr = 1;
++ }
++
++ intr_mask.b.erlysuspend = 1;
++
++ if (core_if->en_multiple_tx_fifo == 0) {
++ intr_mask.b.epmismatch = 1;
++ }
++
++ //intr_mask.b.incomplisoout = 1;
++ intr_mask.b.incomplisoin = 1;
++
++/* Enable the ignore frame number for ISOC xfers - MAS */
++/* Disable to support high bandwith ISOC transfers - manukz */
++#if 0
++#ifdef DWC_UTE_PER_IO
++ if (core_if->dma_enable) {
++ if (core_if->dma_desc_enable) {
++ dctl_data_t dctl1 = {.d32 = 0 };
++ dctl1.b.ifrmnum = 1;
++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
++ dctl, 0, dctl1.d32);
++ DWC_DEBUG("----Enabled Ignore frame number (0x%08x)",
++ DWC_READ_REG32(&core_if->dev_if->
++ dev_global_regs->dctl));
++ }
++ }
++#endif
++#endif
++#ifdef DWC_EN_ISOC
++ if (core_if->dma_enable) {
++ if (core_if->dma_desc_enable == 0) {
++ if (core_if->pti_enh_enable) {
++ dctl_data_t dctl = {.d32 = 0 };
++ dctl.b.ifrmnum = 1;
++ DWC_MODIFY_REG32(&core_if->
++ dev_if->dev_global_regs->dctl,
++ 0, dctl.d32);
++ } else {
++ intr_mask.b.incomplisoin = 1;
++ intr_mask.b.incomplisoout = 1;
++ }
++ }
++ } else {
++ intr_mask.b.incomplisoin = 1;
++ intr_mask.b.incomplisoout = 1;
++ }
++#endif /* DWC_EN_ISOC */
++
++ /** @todo NGS: Should this be a module parameter? */
++#ifdef USE_PERIODIC_EP
++ intr_mask.b.isooutdrop = 1;
++ intr_mask.b.eopframe = 1;
++ intr_mask.b.incomplisoin = 1;
++ intr_mask.b.incomplisoout = 1;
++#endif
++
++ DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
++
++ DWC_DEBUGPL(DBG_CIL, "%s() gintmsk=%0x\n", __func__,
++ DWC_READ_REG32(&global_regs->gintmsk));
++}
++
++/**
++ * This function initializes the DWC_otg controller registers for
++ * device mode.
++ *
++ * @param core_if Programming view of DWC_otg controller
++ *
++ */
++void dwc_otg_core_dev_init(dwc_otg_core_if_t * core_if)
++{
++ int i;
++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
++ dwc_otg_dev_if_t *dev_if = core_if->dev_if;
++ dwc_otg_core_params_t *params = core_if->core_params;
++ dcfg_data_t dcfg = {.d32 = 0 };
++ depctl_data_t diepctl = {.d32 = 0 };
++ grstctl_t resetctl = {.d32 = 0 };
++ uint32_t rx_fifo_size;
++ fifosize_data_t nptxfifosize;
++ fifosize_data_t txfifosize;
++ dthrctl_data_t dthrctl;
++ fifosize_data_t ptxfifosize;
++ uint16_t rxfsiz, nptxfsiz;
++ gdfifocfg_data_t gdfifocfg = {.d32 = 0 };
++ hwcfg3_data_t hwcfg3 = {.d32 = 0 };
++
++ /* Restart the Phy Clock */
++ DWC_WRITE_REG32(core_if->pcgcctl, 0);
++
++ /* Device configuration register */
++ init_devspd(core_if);
++ dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);
++ dcfg.b.descdma = (core_if->dma_desc_enable) ? 1 : 0;
++ dcfg.b.perfrint = DWC_DCFG_FRAME_INTERVAL_80;
++ /* Enable Device OUT NAK in case of DDMA mode*/
++ if (core_if->core_params->dev_out_nak) {
++ dcfg.b.endevoutnak = 1;
++ }
++
++ if (core_if->core_params->cont_on_bna) {
++ dctl_data_t dctl = {.d32 = 0 };
++ dctl.b.encontonbna = 1;
++ DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, 0, dctl.d32);
++ }
++
++
++ DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
++
++ /* Configure data FIFO sizes */
++ if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) {
++ DWC_DEBUGPL(DBG_CIL, "Total FIFO Size=%d\n",
++ core_if->total_fifo_size);
++ DWC_DEBUGPL(DBG_CIL, "Rx FIFO Size=%d\n",
++ params->dev_rx_fifo_size);
++ DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO Size=%d\n",
++ params->dev_nperio_tx_fifo_size);
++
++ /* Rx FIFO */
++ DWC_DEBUGPL(DBG_CIL, "initial grxfsiz=%08x\n",
++ DWC_READ_REG32(&global_regs->grxfsiz));
++
++#ifdef DWC_UTE_CFI
++ core_if->pwron_rxfsiz = DWC_READ_REG32(&global_regs->grxfsiz);
++ core_if->init_rxfsiz = params->dev_rx_fifo_size;
++#endif
++ rx_fifo_size = params->dev_rx_fifo_size;
++ DWC_WRITE_REG32(&global_regs->grxfsiz, rx_fifo_size);
++
++ DWC_DEBUGPL(DBG_CIL, "new grxfsiz=%08x\n",
++ DWC_READ_REG32(&global_regs->grxfsiz));
++
++ /** Set Periodic Tx FIFO Mask all bits 0 */
++ core_if->p_tx_msk = 0;
++
++ /** Set Tx FIFO Mask all bits 0 */
++ core_if->tx_msk = 0;
++
++ if (core_if->en_multiple_tx_fifo == 0) {
++ /* Non-periodic Tx FIFO */
++ DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n",
++ DWC_READ_REG32(&global_regs->gnptxfsiz));
++
++ nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size;
++ nptxfifosize.b.startaddr = params->dev_rx_fifo_size;
++
++ DWC_WRITE_REG32(&global_regs->gnptxfsiz,
++ nptxfifosize.d32);
++
++ DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n",
++ DWC_READ_REG32(&global_regs->gnptxfsiz));
++
++ /**@todo NGS: Fix Periodic FIFO Sizing! */
++ /*
++ * Periodic Tx FIFOs These FIFOs are numbered from 1 to 15.
++ * Indexes of the FIFO size module parameters in the
++ * dev_perio_tx_fifo_size array and the FIFO size registers in
++ * the dptxfsiz array run from 0 to 14.
++ */
++ /** @todo Finish debug of this */
++ ptxfifosize.b.startaddr =
++ nptxfifosize.b.startaddr + nptxfifosize.b.depth;
++ for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; i++) {
++ ptxfifosize.b.depth =
++ params->dev_perio_tx_fifo_size[i];
++ DWC_DEBUGPL(DBG_CIL,
++ "initial dtxfsiz[%d]=%08x\n", i,
++ DWC_READ_REG32(&global_regs->dtxfsiz
++ [i]));
++ DWC_WRITE_REG32(&global_regs->dtxfsiz[i],
++ ptxfifosize.d32);
++ DWC_DEBUGPL(DBG_CIL, "new dtxfsiz[%d]=%08x\n",
++ i,
++ DWC_READ_REG32(&global_regs->dtxfsiz
++ [i]));
++ ptxfifosize.b.startaddr += ptxfifosize.b.depth;
++ }
++ } else {
++ /*
++ * Tx FIFOs These FIFOs are numbered from 1 to 15.
++ * Indexes of the FIFO size module parameters in the
++ * dev_tx_fifo_size array and the FIFO size registers in
++ * the dtxfsiz array run from 0 to 14.
++ */
++
++ /* Non-periodic Tx FIFO */
++ DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n",
++ DWC_READ_REG32(&global_regs->gnptxfsiz));
++
++#ifdef DWC_UTE_CFI
++ core_if->pwron_gnptxfsiz =
++ (DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16);
++ core_if->init_gnptxfsiz =
++ params->dev_nperio_tx_fifo_size;
++#endif
++ nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size;
++ nptxfifosize.b.startaddr = params->dev_rx_fifo_size;
++
++ DWC_WRITE_REG32(&global_regs->gnptxfsiz,
++ nptxfifosize.d32);
++
++ DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n",
++ DWC_READ_REG32(&global_regs->gnptxfsiz));
++
++ txfifosize.b.startaddr =
++ nptxfifosize.b.startaddr + nptxfifosize.b.depth;
++
++ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
++
++ txfifosize.b.depth =
++ params->dev_tx_fifo_size[i];
++
++ DWC_DEBUGPL(DBG_CIL,
++ "initial dtxfsiz[%d]=%08x\n",
++ i,
++ DWC_READ_REG32(&global_regs->dtxfsiz
++ [i]));
++
++#ifdef DWC_UTE_CFI
++ core_if->pwron_txfsiz[i] =
++ (DWC_READ_REG32
++ (&global_regs->dtxfsiz[i]) >> 16);
++ core_if->init_txfsiz[i] =
++ params->dev_tx_fifo_size[i];
++#endif
++ DWC_WRITE_REG32(&global_regs->dtxfsiz[i],
++ txfifosize.d32);
++
++ DWC_DEBUGPL(DBG_CIL,
++ "new dtxfsiz[%d]=%08x\n",
++ i,
++ DWC_READ_REG32(&global_regs->dtxfsiz
++ [i]));
++
++ txfifosize.b.startaddr += txfifosize.b.depth;
++ }
++ if (core_if->snpsid <= OTG_CORE_REV_2_94a) {
++ /* Calculating DFIFOCFG for Device mode to include RxFIFO and NPTXFIFO */
++ gdfifocfg.d32 = DWC_READ_REG32(&global_regs->gdfifocfg);
++ hwcfg3.d32 = DWC_READ_REG32(&global_regs->ghwcfg3);
++ gdfifocfg.b.gdfifocfg = (DWC_READ_REG32(&global_regs->ghwcfg3) >> 16);
++ DWC_WRITE_REG32(&global_regs->gdfifocfg, gdfifocfg.d32);
++ rxfsiz = (DWC_READ_REG32(&global_regs->grxfsiz) & 0x0000ffff);
++ nptxfsiz = (DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16);
++ gdfifocfg.b.epinfobase = rxfsiz + nptxfsiz;
++ DWC_WRITE_REG32(&global_regs->gdfifocfg, gdfifocfg.d32);
++ }
++ }
++
++ /* Flush the FIFOs */
++ dwc_otg_flush_tx_fifo(core_if, 0x10); /* all Tx FIFOs */
++ dwc_otg_flush_rx_fifo(core_if);
++
++ /* Flush the Learning Queue. */
++ resetctl.b.intknqflsh = 1;
++ DWC_WRITE_REG32(&core_if->core_global_regs->grstctl, resetctl.d32);
++
++ if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable) {
++ core_if->start_predict = 0;
++ for (i = 0; i<= core_if->dev_if->num_in_eps; ++i) {
++ core_if->nextep_seq[i] = 0xff; // 0xff - EP not active
++ }
++ core_if->nextep_seq[0] = 0;
++ core_if->first_in_nextep_seq = 0;
++ diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl);
++ diepctl.b.nextep = 0;
++ DWC_WRITE_REG32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32);
++
++ /* Update IN Endpoint Mismatch Count by active IN NP EP count + 1 */
++ dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);
++ dcfg.b.epmscnt = 2;
++ DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
++
++ DWC_DEBUGPL(DBG_CILV,"%s first_in_nextep_seq= %2d; nextep_seq[]:\n",
++ __func__, core_if->first_in_nextep_seq);
++ for (i=0; i <= core_if->dev_if->num_in_eps; i++) {
++ DWC_DEBUGPL(DBG_CILV, "%2d ", core_if->nextep_seq[i]);
++ }
++ DWC_DEBUGPL(DBG_CILV,"\n");
++ }
++
++ /* Clear all pending Device Interrupts */
++ /** @todo - if the condition needed to be checked
++ * or in any case all pending interrutps should be cleared?
++ */
++ if (core_if->multiproc_int_enable) {
++ for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
++ DWC_WRITE_REG32(&dev_if->
++ dev_global_regs->diepeachintmsk[i], 0);
++ }
++ }
++
++ for (i = 0; i < core_if->dev_if->num_out_eps; ++i) {
++ DWC_WRITE_REG32(&dev_if->
++ dev_global_regs->doepeachintmsk[i], 0);
++ }
++
++ DWC_WRITE_REG32(&dev_if->dev_global_regs->deachint, 0xFFFFFFFF);
++ DWC_WRITE_REG32(&dev_if->dev_global_regs->deachintmsk, 0);
++ } else {
++ DWC_WRITE_REG32(&dev_if->dev_global_regs->diepmsk, 0);
++ DWC_WRITE_REG32(&dev_if->dev_global_regs->doepmsk, 0);
++ DWC_WRITE_REG32(&dev_if->dev_global_regs->daint, 0xFFFFFFFF);
++ DWC_WRITE_REG32(&dev_if->dev_global_regs->daintmsk, 0);
++ }
++
++ for (i = 0; i <= dev_if->num_in_eps; i++) {
++ depctl_data_t depctl;
++ depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
++ if (depctl.b.epena) {
++ depctl.d32 = 0;
++ depctl.b.epdis = 1;
++ depctl.b.snak = 1;
++ } else {
++ depctl.d32 = 0;
++ }
++
++ DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32);
++
++ DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->dieptsiz, 0);
++ DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepdma, 0);
++ DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepint, 0xFF);
++ }
++
++ for (i = 0; i <= dev_if->num_out_eps; i++) {
++ depctl_data_t depctl;
++ depctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[i]->doepctl);
++ if (depctl.b.epena) {
++ dctl_data_t dctl = {.d32 = 0 };
++ gintmsk_data_t gintsts = {.d32 = 0 };
++ doepint_data_t doepint = {.d32 = 0 };
++ dctl.b.sgoutnak = 1;
++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
++ do {
++ dwc_udelay(10);
++ gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
++ } while (!gintsts.b.goutnakeff);
++ gintsts.d32 = 0;
++ gintsts.b.goutnakeff = 1;
++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
++
++ depctl.d32 = 0;
++ depctl.b.epdis = 1;
++ depctl.b.snak = 1;
++ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]->doepctl, depctl.d32);
++ do {
++ dwc_udelay(10);
++ doepint.d32 = DWC_READ_REG32(&core_if->dev_if->
++ out_ep_regs[i]->doepint);
++ } while (!doepint.b.epdisabled);
++
++ doepint.b.epdisabled = 1;
++ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]->doepint, doepint.d32);
++
++ dctl.d32 = 0;
++ dctl.b.cgoutnak = 1;
++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
++ } else {
++ depctl.d32 = 0;
++ }
++
++ DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepctl, depctl.d32);
++
++ DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doeptsiz, 0);
++ DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepdma, 0);
++ DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepint, 0xFF);
++ }
++
++ if (core_if->en_multiple_tx_fifo && core_if->dma_enable) {
++ dev_if->non_iso_tx_thr_en = params->thr_ctl & 0x1;
++ dev_if->iso_tx_thr_en = (params->thr_ctl >> 1) & 0x1;
++ dev_if->rx_thr_en = (params->thr_ctl >> 2) & 0x1;
++
++ dev_if->rx_thr_length = params->rx_thr_length;
++ dev_if->tx_thr_length = params->tx_thr_length;
++
++ dev_if->setup_desc_index = 0;
++
++ dthrctl.d32 = 0;
++ dthrctl.b.non_iso_thr_en = dev_if->non_iso_tx_thr_en;
++ dthrctl.b.iso_thr_en = dev_if->iso_tx_thr_en;
++ dthrctl.b.tx_thr_len = dev_if->tx_thr_length;
++ dthrctl.b.rx_thr_en = dev_if->rx_thr_en;
++ dthrctl.b.rx_thr_len = dev_if->rx_thr_length;
++ dthrctl.b.ahb_thr_ratio = params->ahb_thr_ratio;
++
++ DWC_WRITE_REG32(&dev_if->dev_global_regs->dtknqr3_dthrctl,
++ dthrctl.d32);
++
++ DWC_DEBUGPL(DBG_CIL,
++ "Non ISO Tx Thr - %d\nISO Tx Thr - %d\nRx Thr - %d\nTx Thr Len - %d\nRx Thr Len - %d\n",
++ dthrctl.b.non_iso_thr_en, dthrctl.b.iso_thr_en,
++ dthrctl.b.rx_thr_en, dthrctl.b.tx_thr_len,
++ dthrctl.b.rx_thr_len);
++
++ }
++
++ dwc_otg_enable_device_interrupts(core_if);
++
++ {
++ diepmsk_data_t msk = {.d32 = 0 };
++ msk.b.txfifoundrn = 1;
++ if (core_if->multiproc_int_enable) {
++ DWC_MODIFY_REG32(&dev_if->dev_global_regs->
++ diepeachintmsk[0], msk.d32, msk.d32);
++ } else {
++ DWC_MODIFY_REG32(&dev_if->dev_global_regs->diepmsk,
++ msk.d32, msk.d32);
++ }
++ }
++
++ if (core_if->multiproc_int_enable) {
++ /* Set NAK on Babble */
++ dctl_data_t dctl = {.d32 = 0 };
++ dctl.b.nakonbble = 1;
++ DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, 0, dctl.d32);
++ }
++
++ if (core_if->snpsid >= OTG_CORE_REV_2_94a) {
++ dctl_data_t dctl = {.d32 = 0 };
++ dctl.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dctl);
++ dctl.b.sftdiscon = 0;
++ DWC_WRITE_REG32(&dev_if->dev_global_regs->dctl, dctl.d32);
++ }
++}
++
++/**
++ * This function enables the Host mode interrupts.
++ *
++ * @param core_if Programming view of DWC_otg controller
++ */
++void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t * core_if)
++{
++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
++ gintmsk_data_t intr_mask = {.d32 = 0 };
++
++ DWC_DEBUGPL(DBG_CIL, "%s(%p)\n", __func__, core_if);
++
++ /* Disable all interrupts. */
++ DWC_WRITE_REG32(&global_regs->gintmsk, 0);
++
++ /* Clear any pending interrupts. */
++ DWC_WRITE_REG32(&global_regs->gintsts, 0xFFFFFFFF);
++
++ /* Enable the common interrupts */
++ dwc_otg_enable_common_interrupts(core_if);
++
++ /*
++ * Enable host mode interrupts without disturbing common
++ * interrupts.
++ */
++
++ intr_mask.b.disconnect = 1;
++ intr_mask.b.portintr = 1;
++ intr_mask.b.hcintr = 1;
++
++ DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
++}
++
++/**
++ * This function disables the Host Mode interrupts.
++ *
++ * @param core_if Programming view of DWC_otg controller
++ */
++void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t * core_if)
++{
++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
++ gintmsk_data_t intr_mask = {.d32 = 0 };
++
++ DWC_DEBUGPL(DBG_CILV, "%s()\n", __func__);
++
++ /*
++ * Disable host mode interrupts without disturbing common
++ * interrupts.
++ */
++ intr_mask.b.sofintr = 1;
++ intr_mask.b.portintr = 1;
++ intr_mask.b.hcintr = 1;
++ intr_mask.b.ptxfempty = 1;
++ intr_mask.b.nptxfempty = 1;
++
++ DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32, 0);
++}
++
++/**
++ * This function initializes the DWC_otg controller registers for
++ * host mode.
++ *
++ * This function flushes the Tx and Rx FIFOs and it flushes any entries in the
++ * request queues. Host channels are reset to ensure that they are ready for
++ * performing transfers.
++ *
++ * @param core_if Programming view of DWC_otg controller
++ *
++ */
++void dwc_otg_core_host_init(dwc_otg_core_if_t * core_if)
++{
++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
++ dwc_otg_host_if_t *host_if = core_if->host_if;
++ dwc_otg_core_params_t *params = core_if->core_params;
++ hprt0_data_t hprt0 = {.d32 = 0 };
++ fifosize_data_t nptxfifosize;
++ fifosize_data_t ptxfifosize;
++ uint16_t rxfsiz, nptxfsiz, hptxfsiz;
++ gdfifocfg_data_t gdfifocfg = {.d32 = 0 };
++ int i;
++ hcchar_data_t hcchar;
++ hcfg_data_t hcfg;
++ hfir_data_t hfir;
++ dwc_otg_hc_regs_t *hc_regs;
++ int num_channels;
++ gotgctl_data_t gotgctl = {.d32 = 0 };
++
++ DWC_DEBUGPL(DBG_CILV, "%s(%p)\n", __func__, core_if);
++
++ /* Restart the Phy Clock */
++ DWC_WRITE_REG32(core_if->pcgcctl, 0);
++
++ /* Initialize Host Configuration Register */
++ init_fslspclksel(core_if);
++ if (core_if->core_params->speed == DWC_SPEED_PARAM_FULL) {
++ hcfg.d32 = DWC_READ_REG32(&host_if->host_global_regs->hcfg);
++ hcfg.b.fslssupp = 1;
++ DWC_WRITE_REG32(&host_if->host_global_regs->hcfg, hcfg.d32);
++
++ }
++
++ /* This bit allows dynamic reloading of the HFIR register
++ * during runtime. This bit needs to be programmed during
++ * initial configuration and its value must not be changed
++ * during runtime.*/
++ if (core_if->core_params->reload_ctl == 1) {
++ hfir.d32 = DWC_READ_REG32(&host_if->host_global_regs->hfir);
++ hfir.b.hfirrldctrl = 1;
++ DWC_WRITE_REG32(&host_if->host_global_regs->hfir, hfir.d32);
++ }
++
++ if (core_if->core_params->dma_desc_enable) {
++ uint8_t op_mode = core_if->hwcfg2.b.op_mode;
++ if (!
++ (core_if->hwcfg4.b.desc_dma
++ && (core_if->snpsid >= OTG_CORE_REV_2_90a)
++ && ((op_mode == DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
++ || (op_mode == DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG)
++ || (op_mode ==
++ DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG)
++ || (op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)
++ || (op_mode ==
++ DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST)))) {
++
++ DWC_ERROR("Host can't operate in Descriptor DMA mode.\n"
++ "Either core version is below 2.90a or "
++ "GHWCFG2, GHWCFG4 registers' values do not allow Descriptor DMA in host mode.\n"
++ "To run the driver in Buffer DMA host mode set dma_desc_enable "
++ "module parameter to 0.\n");
++ return;
++ }
++ hcfg.d32 = DWC_READ_REG32(&host_if->host_global_regs->hcfg);
++ hcfg.b.descdma = 1;
++ DWC_WRITE_REG32(&host_if->host_global_regs->hcfg, hcfg.d32);
++ }
++
++ /* Configure data FIFO sizes */
++ if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) {
++ DWC_DEBUGPL(DBG_CIL, "Total FIFO Size=%d\n",
++ core_if->total_fifo_size);
++ DWC_DEBUGPL(DBG_CIL, "Rx FIFO Size=%d\n",
++ params->host_rx_fifo_size);
++ DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO Size=%d\n",
++ params->host_nperio_tx_fifo_size);
++ DWC_DEBUGPL(DBG_CIL, "P Tx FIFO Size=%d\n",
++ params->host_perio_tx_fifo_size);
++
++ /* Rx FIFO */
++ DWC_DEBUGPL(DBG_CIL, "initial grxfsiz=%08x\n",
++ DWC_READ_REG32(&global_regs->grxfsiz));
++ DWC_WRITE_REG32(&global_regs->grxfsiz,
++ params->host_rx_fifo_size);
++ DWC_DEBUGPL(DBG_CIL, "new grxfsiz=%08x\n",
++ DWC_READ_REG32(&global_regs->grxfsiz));
++
++ /* Non-periodic Tx FIFO */
++ DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n",
++ DWC_READ_REG32(&global_regs->gnptxfsiz));
++ nptxfifosize.b.depth = params->host_nperio_tx_fifo_size;
++ nptxfifosize.b.startaddr = params->host_rx_fifo_size;
++ DWC_WRITE_REG32(&global_regs->gnptxfsiz, nptxfifosize.d32);
++ DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n",
++ DWC_READ_REG32(&global_regs->gnptxfsiz));
++
++ /* Periodic Tx FIFO */
++ DWC_DEBUGPL(DBG_CIL, "initial hptxfsiz=%08x\n",
++ DWC_READ_REG32(&global_regs->hptxfsiz));
++ ptxfifosize.b.depth = params->host_perio_tx_fifo_size;
++ ptxfifosize.b.startaddr =
++ nptxfifosize.b.startaddr + nptxfifosize.b.depth;
++ DWC_WRITE_REG32(&global_regs->hptxfsiz, ptxfifosize.d32);
++ DWC_DEBUGPL(DBG_CIL, "new hptxfsiz=%08x\n",
++ DWC_READ_REG32(&global_regs->hptxfsiz));
++
++ if (core_if->en_multiple_tx_fifo
++ && core_if->snpsid <= OTG_CORE_REV_2_94a) {
++ /* Global DFIFOCFG calculation for Host mode - include RxFIFO, NPTXFIFO and HPTXFIFO */
++ gdfifocfg.d32 = DWC_READ_REG32(&global_regs->gdfifocfg);
++ rxfsiz = (DWC_READ_REG32(&global_regs->grxfsiz) & 0x0000ffff);
++ nptxfsiz = (DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16);
++ hptxfsiz = (DWC_READ_REG32(&global_regs->hptxfsiz) >> 16);
++ gdfifocfg.b.epinfobase = rxfsiz + nptxfsiz + hptxfsiz;
++ DWC_WRITE_REG32(&global_regs->gdfifocfg, gdfifocfg.d32);
++ }
++ }
++
++ /* TODO - check this */
++ /* Clear Host Set HNP Enable in the OTG Control Register */
++ gotgctl.b.hstsethnpen = 1;
++ DWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0);
++ /* Make sure the FIFOs are flushed. */
++ dwc_otg_flush_tx_fifo(core_if, 0x10 /* all TX FIFOs */ );
++ dwc_otg_flush_rx_fifo(core_if);
++
++ /* Clear Host Set HNP Enable in the OTG Control Register */
++ gotgctl.b.hstsethnpen = 1;
++ DWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0);
++
++ if (!core_if->core_params->dma_desc_enable) {
++ /* Flush out any leftover queued requests. */
++ num_channels = core_if->core_params->host_channels;
++
++ for (i = 0; i < num_channels; i++) {
++ hc_regs = core_if->host_if->hc_regs[i];
++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
++ hcchar.b.chen = 0;
++ hcchar.b.chdis = 1;
++ hcchar.b.epdir = 0;
++ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
++ }
++
++ /* Halt all channels to put them into a known state. */
++ for (i = 0; i < num_channels; i++) {
++ int count = 0;
++ hc_regs = core_if->host_if->hc_regs[i];
++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
++ hcchar.b.chen = 1;
++ hcchar.b.chdis = 1;
++ hcchar.b.epdir = 0;
++ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
++ DWC_DEBUGPL(DBG_HCDV, "%s: Halt channel %d regs %p\n", __func__, i, hc_regs);
++ do {
++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
++ if (++count > 1000) {
++ DWC_ERROR
++ ("%s: Unable to clear halt on channel %d (timeout HCCHAR 0x%X @%p)\n",
++ __func__, i, hcchar.d32, &hc_regs->hcchar);
++ break;
++ }
++ dwc_udelay(1);
++ } while (hcchar.b.chen);
++ }
++ }
++
++ /* Turn on the vbus power. */
++ DWC_PRINTF("Init: Port Power? op_state=%d\n", core_if->op_state);
++ if (core_if->op_state == A_HOST) {
++ hprt0.d32 = dwc_otg_read_hprt0(core_if);
++ DWC_PRINTF("Init: Power Port (%d)\n", hprt0.b.prtpwr);
++ if (hprt0.b.prtpwr == 0) {
++ hprt0.b.prtpwr = 1;
++ DWC_WRITE_REG32(host_if->hprt0, hprt0.d32);
++ }
++ }
++
++ dwc_otg_enable_host_interrupts(core_if);
++}
++
++/**
++ * Prepares a host channel for transferring packets to/from a specific
++ * endpoint. The HCCHARn register is set up with the characteristics specified
++ * in _hc. Host channel interrupts that may need to be serviced while this
++ * transfer is in progress are enabled.
++ *
++ * @param core_if Programming view of DWC_otg controller
++ * @param hc Information needed to initialize the host channel
++ */
++void dwc_otg_hc_init(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
++{
++ hcintmsk_data_t hc_intr_mask;
++ hcchar_data_t hcchar;
++ hcsplt_data_t hcsplt;
++
++ uint8_t hc_num = hc->hc_num;
++ dwc_otg_host_if_t *host_if = core_if->host_if;
++ dwc_otg_hc_regs_t *hc_regs = host_if->hc_regs[hc_num];
++
++ /* Clear old interrupt conditions for this host channel. */
++ hc_intr_mask.d32 = 0xFFFFFFFF;
++ hc_intr_mask.b.reserved14_31 = 0;
++ DWC_WRITE_REG32(&hc_regs->hcint, hc_intr_mask.d32);
++
++ /* Enable channel interrupts required for this transfer. */
++ hc_intr_mask.d32 = 0;
++ hc_intr_mask.b.chhltd = 1;
++ if (core_if->dma_enable) {
++ /* For Descriptor DMA mode core halts the channel on AHB error. Interrupt is not required */
++ if (!core_if->dma_desc_enable)
++ hc_intr_mask.b.ahberr = 1;
++ else {
++ if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)
++ hc_intr_mask.b.xfercompl = 1;
++ }
++
++ if (hc->error_state && !hc->do_split &&
++ hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
++ hc_intr_mask.b.ack = 1;
++ if (hc->ep_is_in) {
++ hc_intr_mask.b.datatglerr = 1;
++ if (hc->ep_type != DWC_OTG_EP_TYPE_INTR) {
++ hc_intr_mask.b.nak = 1;
++ }
++ }
++ }
++ } else {
++ switch (hc->ep_type) {
++ case DWC_OTG_EP_TYPE_CONTROL:
++ case DWC_OTG_EP_TYPE_BULK:
++ hc_intr_mask.b.xfercompl = 1;
++ hc_intr_mask.b.stall = 1;
++ hc_intr_mask.b.xacterr = 1;
++ hc_intr_mask.b.datatglerr = 1;
++ if (hc->ep_is_in) {
++ hc_intr_mask.b.bblerr = 1;
++ } else {
++ hc_intr_mask.b.nak = 1;
++ hc_intr_mask.b.nyet = 1;
++ if (hc->do_ping) {
++ hc_intr_mask.b.ack = 1;
++ }
++ }
++
++ if (hc->do_split) {
++ hc_intr_mask.b.nak = 1;
++ if (hc->complete_split) {
++ hc_intr_mask.b.nyet = 1;
++ } else {
++ hc_intr_mask.b.ack = 1;
++ }
++ }
++
++ if (hc->error_state) {
++ hc_intr_mask.b.ack = 1;
++ }
++ break;
++ case DWC_OTG_EP_TYPE_INTR:
++ hc_intr_mask.b.xfercompl = 1;
++ hc_intr_mask.b.nak = 1;
++ hc_intr_mask.b.stall = 1;
++ hc_intr_mask.b.xacterr = 1;
++ hc_intr_mask.b.datatglerr = 1;
++ hc_intr_mask.b.frmovrun = 1;
++
++ if (hc->ep_is_in) {
++ hc_intr_mask.b.bblerr = 1;
++ }
++ if (hc->error_state) {
++ hc_intr_mask.b.ack = 1;
++ }
++ if (hc->do_split) {
++ if (hc->complete_split) {
++ hc_intr_mask.b.nyet = 1;
++ } else {
++ hc_intr_mask.b.ack = 1;
++ }
++ }
++ break;
++ case DWC_OTG_EP_TYPE_ISOC:
++ hc_intr_mask.b.xfercompl = 1;
++ hc_intr_mask.b.frmovrun = 1;
++ hc_intr_mask.b.ack = 1;
++
++ if (hc->ep_is_in) {
++ hc_intr_mask.b.xacterr = 1;
++ hc_intr_mask.b.bblerr = 1;
++ }
++ break;
++ }
++ }
++ DWC_WRITE_REG32(&hc_regs->hcintmsk, hc_intr_mask.d32);
++
++ /*
++ * Program the HCCHARn register with the endpoint characteristics for
++ * the current transfer.
++ */
++ hcchar.d32 = 0;
++ hcchar.b.devaddr = hc->dev_addr;
++ hcchar.b.epnum = hc->ep_num;
++ hcchar.b.epdir = hc->ep_is_in;
++ hcchar.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW);
++ hcchar.b.eptype = hc->ep_type;
++ hcchar.b.mps = hc->max_packet;
++
++ DWC_WRITE_REG32(&host_if->hc_regs[hc_num]->hcchar, hcchar.d32);
++
++ DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d, Dev Addr %d, EP #%d\n",
++ __func__, hc->hc_num, hcchar.b.devaddr, hcchar.b.epnum);
++ DWC_DEBUGPL(DBG_HCDV, " Is In %d, Is Low Speed %d, EP Type %d, "
++ "Max Pkt %d, Multi Cnt %d\n",
++ hcchar.b.epdir, hcchar.b.lspddev, hcchar.b.eptype,
++ hcchar.b.mps, hcchar.b.multicnt);
++
++ /*
++ * Program the HCSPLIT register for SPLITs
++ */
++ hcsplt.d32 = 0;
++ if (hc->do_split) {
++ DWC_DEBUGPL(DBG_HCDV, "Programming HC %d with split --> %s\n",
++ hc->hc_num,
++ hc->complete_split ? "CSPLIT" : "SSPLIT");
++ hcsplt.b.compsplt = hc->complete_split;
++ hcsplt.b.xactpos = hc->xact_pos;
++ hcsplt.b.hubaddr = hc->hub_addr;
++ hcsplt.b.prtaddr = hc->port_addr;
++ DWC_DEBUGPL(DBG_HCDV, "\t comp split %d\n", hc->complete_split);
++ DWC_DEBUGPL(DBG_HCDV, "\t xact pos %d\n", hc->xact_pos);
++ DWC_DEBUGPL(DBG_HCDV, "\t hub addr %d\n", hc->hub_addr);
++ DWC_DEBUGPL(DBG_HCDV, "\t port addr %d\n", hc->port_addr);
++ DWC_DEBUGPL(DBG_HCDV, "\t is_in %d\n", hc->ep_is_in);
++ DWC_DEBUGPL(DBG_HCDV, "\t Max Pkt: %d\n", hcchar.b.mps);
++ DWC_DEBUGPL(DBG_HCDV, "\t xferlen: %d\n", hc->xfer_len);
++ }
++ DWC_WRITE_REG32(&host_if->hc_regs[hc_num]->hcsplt, hcsplt.d32);
++
++}
++
++/**
++ * Attempts to halt a host channel. This function should only be called in
++ * Slave mode or to abort a transfer in either Slave mode or DMA mode. Under
++ * normal circumstances in DMA mode, the controller halts the channel when the
++ * transfer is complete or a condition occurs that requires application
++ * intervention.
++ *
++ * In slave mode, checks for a free request queue entry, then sets the Channel
++ * Enable and Channel Disable bits of the Host Channel Characteristics
++ * register of the specified channel to intiate the halt. If there is no free
++ * request queue entry, sets only the Channel Disable bit of the HCCHARn
++ * register to flush requests for this channel. In the latter case, sets a
++ * flag to indicate that the host channel needs to be halted when a request
++ * queue slot is open.
++ *
++ * In DMA mode, always sets the Channel Enable and Channel Disable bits of the
++ * HCCHARn register. The controller ensures there is space in the request
++ * queue before submitting the halt request.
++ *
++ * Some time may elapse before the core flushes any posted requests for this
++ * host channel and halts. The Channel Halted interrupt handler completes the
++ * deactivation of the host channel.
++ *
++ * @param core_if Controller register interface.
++ * @param hc Host channel to halt.
++ * @param halt_status Reason for halting the channel.
++ */
++void dwc_otg_hc_halt(dwc_otg_core_if_t * core_if,
++ dwc_hc_t * hc, dwc_otg_halt_status_e halt_status)
++{
++ gnptxsts_data_t nptxsts;
++ hptxsts_data_t hptxsts;
++ hcchar_data_t hcchar;
++ dwc_otg_hc_regs_t *hc_regs;
++ dwc_otg_core_global_regs_t *global_regs;
++ dwc_otg_host_global_regs_t *host_global_regs;
++
++ hc_regs = core_if->host_if->hc_regs[hc->hc_num];
++ global_regs = core_if->core_global_regs;
++ host_global_regs = core_if->host_if->host_global_regs;
++
++ DWC_ASSERT(!(halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS),
++ "halt_status = %d\n", halt_status);
++
++ if (halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE ||
++ halt_status == DWC_OTG_HC_XFER_AHB_ERR) {
++ /*
++ * Disable all channel interrupts except Ch Halted. The QTD
++ * and QH state associated with this transfer has been cleared
++ * (in the case of URB_DEQUEUE), so the channel needs to be
++ * shut down carefully to prevent crashes.
++ */
++ hcintmsk_data_t hcintmsk;
++ hcintmsk.d32 = 0;
++ hcintmsk.b.chhltd = 1;
++ DWC_WRITE_REG32(&hc_regs->hcintmsk, hcintmsk.d32);
++
++ /*
++ * Make sure no other interrupts besides halt are currently
++ * pending. Handling another interrupt could cause a crash due
++ * to the QTD and QH state.
++ */
++ DWC_WRITE_REG32(&hc_regs->hcint, ~hcintmsk.d32);
++
++ /*
++ * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR
++ * even if the channel was already halted for some other
++ * reason.
++ */
++ hc->halt_status = halt_status;
++
++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
++ if (hcchar.b.chen == 0) {
++ /*
++ * The channel is either already halted or it hasn't
++ * started yet. In DMA mode, the transfer may halt if
++ * it finishes normally or a condition occurs that
++ * requires driver intervention. Don't want to halt
++ * the channel again. In either Slave or DMA mode,
++ * it's possible that the transfer has been assigned
++ * to a channel, but not started yet when an URB is
++ * dequeued. Don't want to halt a channel that hasn't
++ * started yet.
++ */
++ return;
++ }
++ }
++ if (hc->halt_pending) {
++ /*
++ * A halt has already been issued for this channel. This might
++ * happen when a transfer is aborted by a higher level in
++ * the stack.
++ */
++#ifdef DEBUG
++ DWC_PRINTF
++ ("*** %s: Channel %d, _hc->halt_pending already set ***\n",
++ __func__, hc->hc_num);
++
++#endif
++ return;
++ }
++
++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
++
++ /* No need to set the bit in DDMA for disabling the channel */
++ //TODO check it everywhere channel is disabled
++ if (!core_if->core_params->dma_desc_enable)
++ hcchar.b.chen = 1;
++ hcchar.b.chdis = 1;
++
++ if (!core_if->dma_enable) {
++ /* Check for space in the request queue to issue the halt. */
++ if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
++ hc->ep_type == DWC_OTG_EP_TYPE_BULK) {
++ nptxsts.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
++ if (nptxsts.b.nptxqspcavail == 0) {
++ hcchar.b.chen = 0;
++ }
++ } else {
++ hptxsts.d32 =
++ DWC_READ_REG32(&host_global_regs->hptxsts);
++ if ((hptxsts.b.ptxqspcavail == 0)
++ || (core_if->queuing_high_bandwidth)) {
++ hcchar.b.chen = 0;
++ }
++ }
++ }
++ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
++
++ hc->halt_status = halt_status;
++
++ if (hcchar.b.chen) {
++ hc->halt_pending = 1;
++ hc->halt_on_queue = 0;
++ } else {
++ hc->halt_on_queue = 1;
++ }
++
++ DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
++ DWC_DEBUGPL(DBG_HCDV, " hcchar: 0x%08x\n", hcchar.d32);
++ DWC_DEBUGPL(DBG_HCDV, " halt_pending: %d\n", hc->halt_pending);
++ DWC_DEBUGPL(DBG_HCDV, " halt_on_queue: %d\n", hc->halt_on_queue);
++ DWC_DEBUGPL(DBG_HCDV, " halt_status: %d\n", hc->halt_status);
++
++ return;
++}
++
++/**
++ * Clears the transfer state for a host channel. This function is normally
++ * called after a transfer is done and the host channel is being released.
++ *
++ * @param core_if Programming view of DWC_otg controller.
++ * @param hc Identifies the host channel to clean up.
++ */
++void dwc_otg_hc_cleanup(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
++{
++ dwc_otg_hc_regs_t *hc_regs;
++
++ hc->xfer_started = 0;
++
++ /*
++ * Clear channel interrupt enables and any unhandled channel interrupt
++ * conditions.
++ */
++ hc_regs = core_if->host_if->hc_regs[hc->hc_num];
++ DWC_WRITE_REG32(&hc_regs->hcintmsk, 0);
++ DWC_WRITE_REG32(&hc_regs->hcint, 0xFFFFFFFF);
++#ifdef DEBUG
++ DWC_TIMER_CANCEL(core_if->hc_xfer_timer[hc->hc_num]);
++#endif
++}
++
++/**
++ * Sets the channel property that indicates in which frame a periodic transfer
++ * should occur. This is always set to the _next_ frame. This function has no
++ * effect on non-periodic transfers.
++ *
++ * @param core_if Programming view of DWC_otg controller.
++ * @param hc Identifies the host channel to set up and its properties.
++ * @param hcchar Current value of the HCCHAR register for the specified host
++ * channel.
++ */
++static inline void hc_set_even_odd_frame(dwc_otg_core_if_t * core_if,
++ dwc_hc_t * hc, hcchar_data_t * hcchar)
++{
++ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
++ hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
++ hfnum_data_t hfnum;
++ hfnum.d32 =
++ DWC_READ_REG32(&core_if->host_if->host_global_regs->hfnum);
++
++ /* 1 if _next_ frame is odd, 0 if it's even */
++ hcchar->b.oddfrm = (hfnum.b.frnum & 0x1) ? 0 : 1;
++#ifdef DEBUG
++ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR && hc->do_split
++ && !hc->complete_split) {
++ switch (hfnum.b.frnum & 0x7) {
++ case 7:
++ core_if->hfnum_7_samples++;
++ core_if->hfnum_7_frrem_accum += hfnum.b.frrem;
++ break;
++ case 0:
++ core_if->hfnum_0_samples++;
++ core_if->hfnum_0_frrem_accum += hfnum.b.frrem;
++ break;
++ default:
++ core_if->hfnum_other_samples++;
++ core_if->hfnum_other_frrem_accum +=
++ hfnum.b.frrem;
++ break;
++ }
++ }
++#endif
++ }
++}
++
++#ifdef DEBUG
++void hc_xfer_timeout(void *ptr)
++{
++ hc_xfer_info_t *xfer_info = NULL;
++ int hc_num = 0;
++
++ if (ptr)
++ xfer_info = (hc_xfer_info_t *) ptr;
++
++ if (!xfer_info->hc) {
++ DWC_ERROR("xfer_info->hc = %p\n", xfer_info->hc);
++ return;
++ }
++
++ hc_num = xfer_info->hc->hc_num;
++ DWC_WARN("%s: timeout on channel %d\n", __func__, hc_num);
++ DWC_WARN(" start_hcchar_val 0x%08x\n",
++ xfer_info->core_if->start_hcchar_val[hc_num]);
++}
++#endif
++
++void ep_xfer_timeout(void *ptr)
++{
++ ep_xfer_info_t *xfer_info = NULL;
++ int ep_num = 0;
++ dctl_data_t dctl = {.d32 = 0 };
++ gintsts_data_t gintsts = {.d32 = 0 };
++ gintmsk_data_t gintmsk = {.d32 = 0 };
++
++ if (ptr)
++ xfer_info = (ep_xfer_info_t *) ptr;
++
++ if (!xfer_info->ep) {
++ DWC_ERROR("xfer_info->ep = %p\n", xfer_info->ep);
++ return;
++ }
++
++ ep_num = xfer_info->ep->num;
++ DWC_WARN("%s: timeout on endpoit %d\n", __func__, ep_num);
++ /* Put the sate to 2 as it was time outed */
++ xfer_info->state = 2;
++
++ dctl.d32 =
++ DWC_READ_REG32(&xfer_info->core_if->dev_if->dev_global_regs->dctl);
++ gintsts.d32 =
++ DWC_READ_REG32(&xfer_info->core_if->core_global_regs->gintsts);
++ gintmsk.d32 =
++ DWC_READ_REG32(&xfer_info->core_if->core_global_regs->gintmsk);
++
++ if (!gintmsk.b.goutnakeff) {
++ /* Unmask it */
++ gintmsk.b.goutnakeff = 1;
++ DWC_WRITE_REG32(&xfer_info->core_if->core_global_regs->gintmsk,
++ gintmsk.d32);
++
++ }
++
++ if (!gintsts.b.goutnakeff) {
++ dctl.b.sgoutnak = 1;
++ }
++ DWC_WRITE_REG32(&xfer_info->core_if->dev_if->dev_global_regs->dctl,
++ dctl.d32);
++
++}
++
++void set_pid_isoc(dwc_hc_t * hc)
++{
++ /* Set up the initial PID for the transfer. */
++ if (hc->speed == DWC_OTG_EP_SPEED_HIGH) {
++ if (hc->ep_is_in) {
++ if (hc->multi_count == 1) {
++ hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
++ } else if (hc->multi_count == 2) {
++ hc->data_pid_start = DWC_OTG_HC_PID_DATA1;
++ } else {
++ hc->data_pid_start = DWC_OTG_HC_PID_DATA2;
++ }
++ } else {
++ if (hc->multi_count == 1) {
++ hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
++ } else {
++ hc->data_pid_start = DWC_OTG_HC_PID_MDATA;
++ }
++ }
++ } else {
++ hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
++ }
++}
++
++/**
++ * This function does the setup for a data transfer for a host channel and
++ * starts the transfer. May be called in either Slave mode or DMA mode. In
++ * Slave mode, the caller must ensure that there is sufficient space in the
++ * request queue and Tx Data FIFO.
++ *
++ * For an OUT transfer in Slave mode, it loads a data packet into the
++ * appropriate FIFO. If necessary, additional data packets will be loaded in
++ * the Host ISR.
++ *
++ * For an IN transfer in Slave mode, a data packet is requested. The data
++ * packets are unloaded from the Rx FIFO in the Host ISR. If necessary,
++ * additional data packets are requested in the Host ISR.
++ *
++ * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ
++ * register along with a packet count of 1 and the channel is enabled. This
++ * causes a single PING transaction to occur. Other fields in HCTSIZ are
++ * simply set to 0 since no data transfer occurs in this case.
++ *
++ * For a PING transfer in DMA mode, the HCTSIZ register is initialized with
++ * all the information required to perform the subsequent data transfer. In
++ * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the
++ * controller performs the entire PING protocol, then starts the data
++ * transfer.
++ *
++ * @param core_if Programming view of DWC_otg controller.
++ * @param hc Information needed to initialize the host channel. The xfer_len
++ * value may be reduced to accommodate the max widths of the XferSize and
++ * PktCnt fields in the HCTSIZn register. The multi_count value may be changed
++ * to reflect the final xfer_len value.
++ */
++void dwc_otg_hc_start_transfer(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
++{
++ hcchar_data_t hcchar;
++ hctsiz_data_t hctsiz;
++ uint16_t num_packets;
++ uint32_t max_hc_xfer_size = core_if->core_params->max_transfer_size;
++ uint16_t max_hc_pkt_count = core_if->core_params->max_packet_count;
++ dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];
++
++ hctsiz.d32 = 0;
++
++ if (hc->do_ping) {
++ if (!core_if->dma_enable) {
++ dwc_otg_hc_do_ping(core_if, hc);
++ hc->xfer_started = 1;
++ return;
++ } else {
++ hctsiz.b.dopng = 1;
++ }
++ }
++
++ if (hc->do_split) {
++ num_packets = 1;
++
++ if (hc->complete_split && !hc->ep_is_in) {
++ /* For CSPLIT OUT Transfer, set the size to 0 so the
++ * core doesn't expect any data written to the FIFO */
++ hc->xfer_len = 0;
++ } else if (hc->ep_is_in || (hc->xfer_len > hc->max_packet)) {
++ hc->xfer_len = hc->max_packet;
++ } else if (!hc->ep_is_in && (hc->xfer_len > 188)) {
++ hc->xfer_len = 188;
++ }
++
++ hctsiz.b.xfersize = hc->xfer_len;
++ } else {
++ /*
++ * Ensure that the transfer length and packet count will fit
++ * in the widths allocated for them in the HCTSIZn register.
++ */
++ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
++ hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
++ /*
++ * Make sure the transfer size is no larger than one
++ * (micro)frame's worth of data. (A check was done
++ * when the periodic transfer was accepted to ensure
++ * that a (micro)frame's worth of data can be
++ * programmed into a channel.)
++ */
++ uint32_t max_periodic_len =
++ hc->multi_count * hc->max_packet;
++ if (hc->xfer_len > max_periodic_len) {
++ hc->xfer_len = max_periodic_len;
++ } else {
++ }
++ } else if (hc->xfer_len > max_hc_xfer_size) {
++ /* Make sure that xfer_len is a multiple of max packet size. */
++ hc->xfer_len = max_hc_xfer_size - hc->max_packet + 1;
++ }
++
++ if (hc->xfer_len > 0) {
++ num_packets =
++ (hc->xfer_len + hc->max_packet -
++ 1) / hc->max_packet;
++ if (num_packets > max_hc_pkt_count) {
++ num_packets = max_hc_pkt_count;
++ hc->xfer_len = num_packets * hc->max_packet;
++ }
++ } else {
++ /* Need 1 packet for transfer length of 0. */
++ num_packets = 1;
++ }
++
++ if (hc->ep_is_in) {
++ /* Always program an integral # of max packets for IN transfers. */
++ hc->xfer_len = num_packets * hc->max_packet;
++ }
++
++ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
++ hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
++ /*
++ * Make sure that the multi_count field matches the
++ * actual transfer length.
++ */
++ hc->multi_count = num_packets;
++ }
++
++ if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)
++ set_pid_isoc(hc);
++
++ hctsiz.b.xfersize = hc->xfer_len;
++ }
++
++ hc->start_pkt_count = num_packets;
++ hctsiz.b.pktcnt = num_packets;
++ hctsiz.b.pid = hc->data_pid_start;
++ DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
++
++ DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
++ DWC_DEBUGPL(DBG_HCDV, " Xfer Size: %d\n", hctsiz.b.xfersize);
++ DWC_DEBUGPL(DBG_HCDV, " Num Pkts: %d\n", hctsiz.b.pktcnt);
++ DWC_DEBUGPL(DBG_HCDV, " Start PID: %d\n", hctsiz.b.pid);
++
++ if (core_if->dma_enable) {
++ dwc_dma_t dma_addr;
++ if (hc->align_buff) {
++ dma_addr = hc->align_buff;
++ } else {
++ dma_addr = ((unsigned long)hc->xfer_buff & 0xffffffff);
++ }
++ DWC_WRITE_REG32(&hc_regs->hcdma, dma_addr);
++ }
++
++ /* Start the split */
++ if (hc->do_split) {
++ hcsplt_data_t hcsplt;
++ hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
++ hcsplt.b.spltena = 1;
++ DWC_WRITE_REG32(&hc_regs->hcsplt, hcsplt.d32);
++ }
++
++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
++ hcchar.b.multicnt = hc->multi_count;
++ hc_set_even_odd_frame(core_if, hc, &hcchar);
++#ifdef DEBUG
++ core_if->start_hcchar_val[hc->hc_num] = hcchar.d32;
++ if (hcchar.b.chdis) {
++ DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n",
++ __func__, hc->hc_num, hcchar.d32);
++ }
++#endif
++
++ /* Set host channel enable after all other setup is complete. */
++ hcchar.b.chen = 1;
++ hcchar.b.chdis = 0;
++ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
++
++ hc->xfer_started = 1;
++ hc->requests++;
++
++ if (!core_if->dma_enable && !hc->ep_is_in && hc->xfer_len > 0) {
++ /* Load OUT packet into the appropriate Tx FIFO. */
++ dwc_otg_hc_write_packet(core_if, hc);
++ }
++#ifdef DEBUG
++ if (hc->ep_type != DWC_OTG_EP_TYPE_INTR) {
++ DWC_DEBUGPL(DBG_HCDV, "transfer %d from core_if %p\n",
++ hc->hc_num, core_if);//GRAYG
++ core_if->hc_xfer_info[hc->hc_num].core_if = core_if;
++ core_if->hc_xfer_info[hc->hc_num].hc = hc;
++
++ /* Start a timer for this transfer. */
++ DWC_TIMER_SCHEDULE(core_if->hc_xfer_timer[hc->hc_num], 10000);
++ }
++#endif
++}
++
++/**
++ * This function does the setup for a data transfer for a host channel
++ * and starts the transfer in Descriptor DMA mode.
++ *
++ * Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set.
++ * Sets PID and NTD values. For periodic transfers
++ * initializes SCHED_INFO field with micro-frame bitmap.
++ *
++ * Initializes HCDMA register with descriptor list address and CTD value
++ * then starts the transfer via enabling the channel.
++ *
++ * @param core_if Programming view of DWC_otg controller.
++ * @param hc Information needed to initialize the host channel.
++ */
++void dwc_otg_hc_start_transfer_ddma(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
++{
++ dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];
++ hcchar_data_t hcchar;
++ hctsiz_data_t hctsiz;
++ hcdma_data_t hcdma;
++
++ hctsiz.d32 = 0;
++
++ if (hc->do_ping)
++ hctsiz.b_ddma.dopng = 1;
++
++ if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)
++ set_pid_isoc(hc);
++
++ /* Packet Count and Xfer Size are not used in Descriptor DMA mode */
++ hctsiz.b_ddma.pid = hc->data_pid_start;
++ hctsiz.b_ddma.ntd = hc->ntd - 1; /* 0 - 1 descriptor, 1 - 2 descriptors, etc. */
++ hctsiz.b_ddma.schinfo = hc->schinfo; /* Non-zero only for high-speed interrupt endpoints */
++
++ DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
++ DWC_DEBUGPL(DBG_HCDV, " Start PID: %d\n", hctsiz.b.pid);
++ DWC_DEBUGPL(DBG_HCDV, " NTD: %d\n", hctsiz.b_ddma.ntd);
++
++ DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
++
++ hcdma.d32 = 0;
++ hcdma.b.dma_addr = ((uint32_t) hc->desc_list_addr) >> 11;
++
++ /* Always start from first descriptor. */
++ hcdma.b.ctd = 0;
++ DWC_WRITE_REG32(&hc_regs->hcdma, hcdma.d32);
++
++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
++ hcchar.b.multicnt = hc->multi_count;
++
++#ifdef DEBUG
++ core_if->start_hcchar_val[hc->hc_num] = hcchar.d32;
++ if (hcchar.b.chdis) {
++ DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n",
++ __func__, hc->hc_num, hcchar.d32);
++ }
++#endif
++
++ /* Set host channel enable after all other setup is complete. */
++ hcchar.b.chen = 1;
++ hcchar.b.chdis = 0;
++
++ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
++
++ hc->xfer_started = 1;
++ hc->requests++;
++
++#ifdef DEBUG
++ if ((hc->ep_type != DWC_OTG_EP_TYPE_INTR)
++ && (hc->ep_type != DWC_OTG_EP_TYPE_ISOC)) {
++ DWC_DEBUGPL(DBG_HCDV, "DMA transfer %d from core_if %p\n",
++ hc->hc_num, core_if);//GRAYG
++ core_if->hc_xfer_info[hc->hc_num].core_if = core_if;
++ core_if->hc_xfer_info[hc->hc_num].hc = hc;
++ /* Start a timer for this transfer. */
++ DWC_TIMER_SCHEDULE(core_if->hc_xfer_timer[hc->hc_num], 10000);
++ }
++#endif
++
++}
++
++/**
++ * This function continues a data transfer that was started by previous call
++ * to <code>dwc_otg_hc_start_transfer</code>. The caller must ensure there is
++ * sufficient space in the request queue and Tx Data FIFO. This function
++ * should only be called in Slave mode. In DMA mode, the controller acts
++ * autonomously to complete transfers programmed to a host channel.
++ *
++ * For an OUT transfer, a new data packet is loaded into the appropriate FIFO
++ * if there is any data remaining to be queued. For an IN transfer, another
++ * data packet is always requested. For the SETUP phase of a control transfer,
++ * this function does nothing.
++ *
++ * @return 1 if a new request is queued, 0 if no more requests are required
++ * for this transfer.
++ */
++int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
++{
++ DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
++
++ if (hc->do_split) {
++ /* SPLITs always queue just once per channel */
++ return 0;
++ } else if (hc->data_pid_start == DWC_OTG_HC_PID_SETUP) {
++ /* SETUPs are queued only once since they can't be NAKed. */
++ return 0;
++ } else if (hc->ep_is_in) {
++ /*
++ * Always queue another request for other IN transfers. If
++ * back-to-back INs are issued and NAKs are received for both,
++ * the driver may still be processing the first NAK when the
++ * second NAK is received. When the interrupt handler clears
++ * the NAK interrupt for the first NAK, the second NAK will
++ * not be seen. So we can't depend on the NAK interrupt
++ * handler to requeue a NAKed request. Instead, IN requests
++ * are issued each time this function is called. When the
++ * transfer completes, the extra requests for the channel will
++ * be flushed.
++ */
++ hcchar_data_t hcchar;
++ dwc_otg_hc_regs_t *hc_regs =
++ core_if->host_if->hc_regs[hc->hc_num];
++
++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
++ hc_set_even_odd_frame(core_if, hc, &hcchar);
++ hcchar.b.chen = 1;
++ hcchar.b.chdis = 0;
++ DWC_DEBUGPL(DBG_HCDV, " IN xfer: hcchar = 0x%08x\n",
++ hcchar.d32);
++ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
++ hc->requests++;
++ return 1;
++ } else {
++ /* OUT transfers. */
++ if (hc->xfer_count < hc->xfer_len) {
++ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
++ hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
++ hcchar_data_t hcchar;
++ dwc_otg_hc_regs_t *hc_regs;
++ hc_regs = core_if->host_if->hc_regs[hc->hc_num];
++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
++ hc_set_even_odd_frame(core_if, hc, &hcchar);
++ }
++
++ /* Load OUT packet into the appropriate Tx FIFO. */
++ dwc_otg_hc_write_packet(core_if, hc);
++ hc->requests++;
++ return 1;
++ } else {
++ return 0;
++ }
++ }
++}
++
++/**
++ * Starts a PING transfer. This function should only be called in Slave mode.
++ * The Do Ping bit is set in the HCTSIZ register, then the channel is enabled.
++ */
++void dwc_otg_hc_do_ping(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
++{
++ hcchar_data_t hcchar;
++ hctsiz_data_t hctsiz;
++ dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];
++
++ DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
++
++ hctsiz.d32 = 0;
++ hctsiz.b.dopng = 1;
++ hctsiz.b.pktcnt = 1;
++ DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
++
++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
++ hcchar.b.chen = 1;
++ hcchar.b.chdis = 0;
++ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
++}
++
++/*
++ * This function writes a packet into the Tx FIFO associated with the Host
++ * Channel. For a channel associated with a non-periodic EP, the non-periodic
++ * Tx FIFO is written. For a channel associated with a periodic EP, the
++ * periodic Tx FIFO is written. This function should only be called in Slave
++ * mode.
++ *
++ * Upon return the xfer_buff and xfer_count fields in _hc are incremented by
++ * then number of bytes written to the Tx FIFO.
++ */
++void dwc_otg_hc_write_packet(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
++{
++ uint32_t i;
++ uint32_t remaining_count;
++ uint32_t byte_count;
++ uint32_t dword_count;
++
++ uint32_t *data_buff = (uint32_t *) (hc->xfer_buff);
++ uint32_t *data_fifo = core_if->data_fifo[hc->hc_num];
++
++ remaining_count = hc->xfer_len - hc->xfer_count;
++ if (remaining_count > hc->max_packet) {
++ byte_count = hc->max_packet;
++ } else {
++ byte_count = remaining_count;
++ }
++
++ dword_count = (byte_count + 3) / 4;
++
++ if ((((unsigned long)data_buff) & 0x3) == 0) {
++ /* xfer_buff is DWORD aligned. */
++ for (i = 0; i < dword_count; i++, data_buff++) {
++ DWC_WRITE_REG32(data_fifo, *data_buff);
++ }
++ } else {
++ /* xfer_buff is not DWORD aligned. */
++ for (i = 0; i < dword_count; i++, data_buff++) {
++ uint32_t data;
++ data =
++ (data_buff[0] | data_buff[1] << 8 | data_buff[2] <<
++ 16 | data_buff[3] << 24);
++ DWC_WRITE_REG32(data_fifo, data);
++ }
++ }
++
++ hc->xfer_count += byte_count;
++ hc->xfer_buff += byte_count;
++}
++
++/**
++ * Gets the current USB frame number. This is the frame number from the last
++ * SOF packet.
++ */
++uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t * core_if)
++{
++ dsts_data_t dsts;
++ dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
++
++ /* read current frame/microframe number from DSTS register */
++ return dsts.b.soffn;
++}
++
++/**
++ * Calculates and gets the frame Interval value of HFIR register according PHY
++ * type and speed.The application can modify a value of HFIR register only after
++ * the Port Enable bit of the Host Port Control and Status register
++ * (HPRT.PrtEnaPort) has been set.
++*/
++
++uint32_t calc_frame_interval(dwc_otg_core_if_t * core_if)
++{
++ gusbcfg_data_t usbcfg;
++ hwcfg2_data_t hwcfg2;
++ hprt0_data_t hprt0;
++ int clock = 60; // default value
++ usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
++ hwcfg2.d32 = DWC_READ_REG32(&core_if->core_global_regs->ghwcfg2);
++ hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
++ if (!usbcfg.b.physel && usbcfg.b.ulpi_utmi_sel && !usbcfg.b.phyif)
++ clock = 60;
++ if (usbcfg.b.physel && hwcfg2.b.fs_phy_type == 3)
++ clock = 48;
++ if (!usbcfg.b.phylpwrclksel && !usbcfg.b.physel &&
++ !usbcfg.b.ulpi_utmi_sel && usbcfg.b.phyif)
++ clock = 30;
++ if (!usbcfg.b.phylpwrclksel && !usbcfg.b.physel &&
++ !usbcfg.b.ulpi_utmi_sel && !usbcfg.b.phyif)
++ clock = 60;
++ if (usbcfg.b.phylpwrclksel && !usbcfg.b.physel &&
++ !usbcfg.b.ulpi_utmi_sel && usbcfg.b.phyif)
++ clock = 48;
++ if (usbcfg.b.physel && !usbcfg.b.phyif && hwcfg2.b.fs_phy_type == 2)
++ clock = 48;
++ if (usbcfg.b.physel && hwcfg2.b.fs_phy_type == 1)
++ clock = 48;
++ if (hprt0.b.prtspd == 0)
++ /* High speed case */
++ return 125 * clock;
++ else
++ /* FS/LS case */
++ return 1000 * clock;
++}
++
++/**
++ * This function reads a setup packet from the Rx FIFO into the destination
++ * buffer. This function is called from the Rx Status Queue Level (RxStsQLvl)
++ * Interrupt routine when a SETUP packet has been received in Slave mode.
++ *
++ * @param core_if Programming view of DWC_otg controller.
++ * @param dest Destination buffer for packet data.
++ */
++void dwc_otg_read_setup_packet(dwc_otg_core_if_t * core_if, uint32_t * dest)
++{
++ device_grxsts_data_t status;
++ /* Get the 8 bytes of a setup transaction data */
++
++ /* Pop 2 DWORDS off the receive data FIFO into memory */
++ dest[0] = DWC_READ_REG32(core_if->data_fifo[0]);
++ dest[1] = DWC_READ_REG32(core_if->data_fifo[0]);
++ if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
++ status.d32 =
++ DWC_READ_REG32(&core_if->core_global_regs->grxstsp);
++ DWC_DEBUGPL(DBG_ANY,
++ "EP:%d BCnt:%d " "pktsts:%x Frame:%d(0x%0x)\n",
++ status.b.epnum, status.b.bcnt, status.b.pktsts,
++ status.b.fn, status.b.fn);
++ }
++}
++
++/**
++ * This function enables EP0 OUT to receive SETUP packets and configures EP0
++ * IN for transmitting packets. It is normally called when the
++ * "Enumeration Done" interrupt occurs.
++ *
++ * @param core_if Programming view of DWC_otg controller.
++ * @param ep The EP0 data.
++ */
++void dwc_otg_ep0_activate(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
++{
++ dwc_otg_dev_if_t *dev_if = core_if->dev_if;
++ dsts_data_t dsts;
++ depctl_data_t diepctl;
++ depctl_data_t doepctl;
++ dctl_data_t dctl = {.d32 = 0 };
++
++ ep->stp_rollover = 0;
++ /* Read the Device Status and Endpoint 0 Control registers */
++ dsts.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dsts);
++ diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl);
++ doepctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl);
++
++ /* Set the MPS of the IN EP based on the enumeration speed */
++ switch (dsts.b.enumspd) {
++ case DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ:
++ case DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ:
++ case DWC_DSTS_ENUMSPD_FS_PHY_48MHZ:
++ diepctl.b.mps = DWC_DEP0CTL_MPS_64;
++ break;
++ case DWC_DSTS_ENUMSPD_LS_PHY_6MHZ:
++ diepctl.b.mps = DWC_DEP0CTL_MPS_8;
++ break;
++ }
++
++ DWC_WRITE_REG32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32);
++
++ /* Enable OUT EP for receive */
++ if (core_if->snpsid <= OTG_CORE_REV_2_94a) {
++ doepctl.b.epena = 1;
++ DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepctl, doepctl.d32);
++ }
++#ifdef VERBOSE
++ DWC_DEBUGPL(DBG_PCDV, "doepctl0=%0x\n",
++ DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl));
++ DWC_DEBUGPL(DBG_PCDV, "diepctl0=%0x\n",
++ DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl));
++#endif
++ dctl.b.cgnpinnak = 1;
++
++ DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);
++ DWC_DEBUGPL(DBG_PCDV, "dctl=%0x\n",
++ DWC_READ_REG32(&dev_if->dev_global_regs->dctl));
++
++}
++
++/**
++ * This function activates an EP. The Device EP control register for
++ * the EP is configured as defined in the ep structure. Note: This
++ * function is not used for EP0.
++ *
++ * @param core_if Programming view of DWC_otg controller.
++ * @param ep The EP to activate.
++ */
++void dwc_otg_ep_activate(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
++{
++ dwc_otg_dev_if_t *dev_if = core_if->dev_if;
++ depctl_data_t depctl;
++ volatile uint32_t *addr;
++ daint_data_t daintmsk = {.d32 = 0 };
++ dcfg_data_t dcfg;
++ uint8_t i;
++
++ DWC_DEBUGPL(DBG_PCDV, "%s() EP%d-%s\n", __func__, ep->num,
++ (ep->is_in ? "IN" : "OUT"));
++
++#ifdef DWC_UTE_PER_IO
++ ep->xiso_frame_num = 0xFFFFFFFF;
++ ep->xiso_active_xfers = 0;
++ ep->xiso_queued_xfers = 0;
++#endif
++ /* Read DEPCTLn register */
++ if (ep->is_in == 1) {
++ addr = &dev_if->in_ep_regs[ep->num]->diepctl;
++ daintmsk.ep.in = 1 << ep->num;
++ } else {
++ addr = &dev_if->out_ep_regs[ep->num]->doepctl;
++ daintmsk.ep.out = 1 << ep->num;
++ }
++
++ /* If the EP is already active don't change the EP Control
++ * register. */
++ depctl.d32 = DWC_READ_REG32(addr);
++ if (!depctl.b.usbactep) {
++ depctl.b.mps = ep->maxpacket;
++ depctl.b.eptype = ep->type;
++ depctl.b.txfnum = ep->tx_fifo_num;
++
++ if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
++ depctl.b.setd0pid = 1; // ???
++ } else {
++ depctl.b.setd0pid = 1;
++ }
++ depctl.b.usbactep = 1;
++
++ /* Update nextep_seq array and EPMSCNT in DCFG*/
++ if (!(depctl.b.eptype & 1) && (ep->is_in == 1)) { // NP IN EP
++ for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
++ if (core_if->nextep_seq[i] == core_if->first_in_nextep_seq)
++ break;
++ }
++ core_if->nextep_seq[i] = ep->num;
++ core_if->nextep_seq[ep->num] = core_if->first_in_nextep_seq;
++ depctl.b.nextep = core_if->nextep_seq[ep->num];
++ dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);
++ dcfg.b.epmscnt++;
++ DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
++
++ DWC_DEBUGPL(DBG_PCDV,
++ "%s first_in_nextep_seq= %2d; nextep_seq[]:\n",
++ __func__, core_if->first_in_nextep_seq);
++ for (i=0; i <= core_if->dev_if->num_in_eps; i++) {
++ DWC_DEBUGPL(DBG_PCDV, "%2d\n",
++ core_if->nextep_seq[i]);
++ }
++
++ }
++
++
++ DWC_WRITE_REG32(addr, depctl.d32);
++ DWC_DEBUGPL(DBG_PCDV, "DEPCTL=%08x\n", DWC_READ_REG32(addr));
++ }
++
++ /* Enable the Interrupt for this EP */
++ if (core_if->multiproc_int_enable) {
++ if (ep->is_in == 1) {
++ diepmsk_data_t diepmsk = {.d32 = 0 };
++ diepmsk.b.xfercompl = 1;
++ diepmsk.b.timeout = 1;
++ diepmsk.b.epdisabled = 1;
++ diepmsk.b.ahberr = 1;
++ diepmsk.b.intknepmis = 1;
++ if (!core_if->en_multiple_tx_fifo && core_if->dma_enable)
++ diepmsk.b.intknepmis = 0;
++ diepmsk.b.txfifoundrn = 1; //?????
++ if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
++ diepmsk.b.nak = 1;
++ }
++
++
++
++/*
++ if (core_if->dma_desc_enable) {
++ diepmsk.b.bna = 1;
++ }
++*/
++/*
++ if (core_if->dma_enable) {
++ doepmsk.b.nak = 1;
++ }
++*/
++ DWC_WRITE_REG32(&dev_if->dev_global_regs->
++ diepeachintmsk[ep->num], diepmsk.d32);
++
++ } else {
++ doepmsk_data_t doepmsk = {.d32 = 0 };
++ doepmsk.b.xfercompl = 1;
++ doepmsk.b.ahberr = 1;
++ doepmsk.b.epdisabled = 1;
++ if (ep->type == DWC_OTG_EP_TYPE_ISOC)
++ doepmsk.b.outtknepdis = 1;
++
++/*
++
++ if (core_if->dma_desc_enable) {
++ doepmsk.b.bna = 1;
++ }
++*/
++/*
++ doepmsk.b.babble = 1;
++ doepmsk.b.nyet = 1;
++ doepmsk.b.nak = 1;
++*/
++ DWC_WRITE_REG32(&dev_if->dev_global_regs->
++ doepeachintmsk[ep->num], doepmsk.d32);
++ }
++ DWC_MODIFY_REG32(&dev_if->dev_global_regs->deachintmsk,
++ 0, daintmsk.d32);
++ } else {
++ if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
++ if (ep->is_in) {
++ diepmsk_data_t diepmsk = {.d32 = 0 };
++ diepmsk.b.nak = 1;
++ DWC_MODIFY_REG32(&dev_if->dev_global_regs->diepmsk, 0, diepmsk.d32);
++ } else {
++ doepmsk_data_t doepmsk = {.d32 = 0 };
++ doepmsk.b.outtknepdis = 1;
++ DWC_MODIFY_REG32(&dev_if->dev_global_regs->doepmsk, 0, doepmsk.d32);
++ }
++ }
++ DWC_MODIFY_REG32(&dev_if->dev_global_regs->daintmsk,
++ 0, daintmsk.d32);
++ }
++
++ DWC_DEBUGPL(DBG_PCDV, "DAINTMSK=%0x\n",
++ DWC_READ_REG32(&dev_if->dev_global_regs->daintmsk));
++
++ ep->stall_clear_flag = 0;
++
++ return;
++}
++
++/**
++ * This function deactivates an EP. This is done by clearing the USB Active
++ * EP bit in the Device EP control register. Note: This function is not used
++ * for EP0. EP0 cannot be deactivated.
++ *
++ * @param core_if Programming view of DWC_otg controller.
++ * @param ep The EP to deactivate.
++ */
++void dwc_otg_ep_deactivate(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
++{
++ depctl_data_t depctl = {.d32 = 0 };
++ volatile uint32_t *addr;
++ daint_data_t daintmsk = {.d32 = 0 };
++ dcfg_data_t dcfg;
++ uint8_t i = 0;
++
++#ifdef DWC_UTE_PER_IO
++ ep->xiso_frame_num = 0xFFFFFFFF;
++ ep->xiso_active_xfers = 0;
++ ep->xiso_queued_xfers = 0;
++#endif
++
++ /* Read DEPCTLn register */
++ if (ep->is_in == 1) {
++ addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
++ daintmsk.ep.in = 1 << ep->num;
++ } else {
++ addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
++ daintmsk.ep.out = 1 << ep->num;
++ }
++
++ depctl.d32 = DWC_READ_REG32(addr);
++
++ depctl.b.usbactep = 0;
++
++ /* Update nextep_seq array and EPMSCNT in DCFG*/
++ if (!(depctl.b.eptype & 1) && ep->is_in == 1) { // NP EP IN
++ for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
++ if (core_if->nextep_seq[i] == ep->num)
++ break;
++ }
++ core_if->nextep_seq[i] = core_if->nextep_seq[ep->num];
++ if (core_if->first_in_nextep_seq == ep->num)
++ core_if->first_in_nextep_seq = i;
++ core_if->nextep_seq[ep->num] = 0xff;
++ depctl.b.nextep = 0;
++ dcfg.d32 =
++ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
++ dcfg.b.epmscnt--;
++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg,
++ dcfg.d32);
++
++ DWC_DEBUGPL(DBG_PCDV,
++ "%s first_in_nextep_seq= %2d; nextep_seq[]:\n",
++ __func__, core_if->first_in_nextep_seq);
++ for (i=0; i <= core_if->dev_if->num_in_eps; i++) {
++ DWC_DEBUGPL(DBG_PCDV, "%2d\n", core_if->nextep_seq[i]);
++ }
++ }
++
++ if (ep->is_in == 1)
++ depctl.b.txfnum = 0;
++
++ if (core_if->dma_desc_enable)
++ depctl.b.epdis = 1;
++
++ DWC_WRITE_REG32(addr, depctl.d32);
++ depctl.d32 = DWC_READ_REG32(addr);
++ if (core_if->dma_enable && ep->type == DWC_OTG_EP_TYPE_ISOC
++ && depctl.b.epena) {
++ depctl_data_t depctl = {.d32 = 0};
++ if (ep->is_in) {
++ diepint_data_t diepint = {.d32 = 0};
++
++ depctl.b.snak = 1;
++ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
++ diepctl, depctl.d32);
++ do {
++ dwc_udelay(10);
++ diepint.d32 =
++ DWC_READ_REG32(&core_if->
++ dev_if->in_ep_regs[ep->num]->
++ diepint);
++ } while (!diepint.b.inepnakeff);
++ diepint.b.inepnakeff = 1;
++ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
++ diepint, diepint.d32);
++ depctl.d32 = 0;
++ depctl.b.epdis = 1;
++ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
++ diepctl, depctl.d32);
++ do {
++ dwc_udelay(10);
++ diepint.d32 =
++ DWC_READ_REG32(&core_if->
++ dev_if->in_ep_regs[ep->num]->
++ diepint);
++ } while (!diepint.b.epdisabled);
++ diepint.b.epdisabled = 1;
++ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
++ diepint, diepint.d32);
++ } else {
++ dctl_data_t dctl = {.d32 = 0};
++ gintmsk_data_t gintsts = {.d32 = 0};
++ doepint_data_t doepint = {.d32 = 0};
++ dctl.b.sgoutnak = 1;
++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
++ dctl, 0, dctl.d32);
++ do {
++ dwc_udelay(10);
++ gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
++ } while (!gintsts.b.goutnakeff);
++ gintsts.d32 = 0;
++ gintsts.b.goutnakeff = 1;
++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
++
++ depctl.d32 = 0;
++ depctl.b.epdis = 1;
++ depctl.b.snak = 1;
++ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[ep->num]->doepctl, depctl.d32);
++ do
++ {
++ dwc_udelay(10);
++ doepint.d32 = DWC_READ_REG32(&core_if->dev_if->
++ out_ep_regs[ep->num]->doepint);
++ } while (!doepint.b.epdisabled);
++
++ doepint.b.epdisabled = 1;
++ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[ep->num]->doepint, doepint.d32);
++
++ dctl.d32 = 0;
++ dctl.b.cgoutnak = 1;
++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
++ }
++ }
++
++ /* Disable the Interrupt for this EP */
++ if (core_if->multiproc_int_enable) {
++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->deachintmsk,
++ daintmsk.d32, 0);
++
++ if (ep->is_in == 1) {
++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->
++ diepeachintmsk[ep->num], 0);
++ } else {
++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->
++ doepeachintmsk[ep->num], 0);
++ }
++ } else {
++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->daintmsk,
++ daintmsk.d32, 0);
++ }
++
++}
++
++/**
++ * This function initializes dma descriptor chain.
++ *
++ * @param core_if Programming view of DWC_otg controller.
++ * @param ep The EP to start the transfer on.
++ */
++static void init_dma_desc_chain(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
++{
++ dwc_otg_dev_dma_desc_t *dma_desc;
++ uint32_t offset;
++ uint32_t xfer_est;
++ int i;
++ unsigned maxxfer_local, total_len;
++
++ if (!ep->is_in && ep->type == DWC_OTG_EP_TYPE_INTR &&
++ (ep->maxpacket%4)) {
++ maxxfer_local = ep->maxpacket;
++ total_len = ep->xfer_len;
++ } else {
++ maxxfer_local = ep->maxxfer;
++ total_len = ep->total_len;
++ }
++
++ ep->desc_cnt = (total_len / maxxfer_local) +
++ ((total_len % maxxfer_local) ? 1 : 0);
++
++ if (!ep->desc_cnt)
++ ep->desc_cnt = 1;
++
++ if (ep->desc_cnt > MAX_DMA_DESC_CNT)
++ ep->desc_cnt = MAX_DMA_DESC_CNT;
++
++ dma_desc = ep->desc_addr;
++ if (maxxfer_local == ep->maxpacket) {
++ if ((total_len % maxxfer_local) &&
++ (total_len/maxxfer_local < MAX_DMA_DESC_CNT)) {
++ xfer_est = (ep->desc_cnt - 1) * maxxfer_local +
++ (total_len % maxxfer_local);
++ } else
++ xfer_est = ep->desc_cnt * maxxfer_local;
++ } else
++ xfer_est = total_len;
++ offset = 0;
++ for (i = 0; i < ep->desc_cnt; ++i) {
++ /** DMA Descriptor Setup */
++ if (xfer_est > maxxfer_local) {
++ dma_desc->status.b.bs = BS_HOST_BUSY;
++ dma_desc->status.b.l = 0;
++ dma_desc->status.b.ioc = 0;
++ dma_desc->status.b.sp = 0;
++ dma_desc->status.b.bytes = maxxfer_local;
++ dma_desc->buf = ep->dma_addr + offset;
++ dma_desc->status.b.sts = 0;
++ dma_desc->status.b.bs = BS_HOST_READY;
++
++ xfer_est -= maxxfer_local;
++ offset += maxxfer_local;
++ } else {
++ dma_desc->status.b.bs = BS_HOST_BUSY;
++ dma_desc->status.b.l = 1;
++ dma_desc->status.b.ioc = 1;
++ if (ep->is_in) {
++ dma_desc->status.b.sp =
++ (xfer_est %
++ ep->maxpacket) ? 1 : ((ep->
++ sent_zlp) ? 1 : 0);
++ dma_desc->status.b.bytes = xfer_est;
++ } else {
++ if (maxxfer_local == ep->maxpacket)
++ dma_desc->status.b.bytes = xfer_est;
++ else
++ dma_desc->status.b.bytes =
++ xfer_est + ((4 - (xfer_est & 0x3)) & 0x3);
++ }
++
++ dma_desc->buf = ep->dma_addr + offset;
++ dma_desc->status.b.sts = 0;
++ dma_desc->status.b.bs = BS_HOST_READY;
++ }
++ dma_desc++;
++ }
++}
++/**
++ * This function is called when to write ISOC data into appropriate dedicated
++ * periodic FIFO.
++ */
++static int32_t write_isoc_tx_fifo(dwc_otg_core_if_t * core_if, dwc_ep_t * dwc_ep)
++{
++ dwc_otg_dev_if_t *dev_if = core_if->dev_if;
++ dwc_otg_dev_in_ep_regs_t *ep_regs;
++ dtxfsts_data_t txstatus = {.d32 = 0 };
++ uint32_t len = 0;
++ int epnum = dwc_ep->num;
++ int dwords;
++
++ DWC_DEBUGPL(DBG_PCD, "Dedicated TxFifo Empty: %d \n", epnum);
++
++ ep_regs = core_if->dev_if->in_ep_regs[epnum];
++
++ len = dwc_ep->xfer_len - dwc_ep->xfer_count;
++
++ if (len > dwc_ep->maxpacket) {
++ len = dwc_ep->maxpacket;
++ }
++
++ dwords = (len + 3) / 4;
++
++ /* While there is space in the queue and space in the FIFO and
++ * More data to tranfer, Write packets to the Tx FIFO */
++ txstatus.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts);
++ DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum, txstatus.d32);
++
++ while (txstatus.b.txfspcavail > dwords &&
++ dwc_ep->xfer_count < dwc_ep->xfer_len && dwc_ep->xfer_len != 0) {
++ /* Write the FIFO */
++ dwc_otg_ep_write_packet(core_if, dwc_ep, 0);
++
++ len = dwc_ep->xfer_len - dwc_ep->xfer_count;
++ if (len > dwc_ep->maxpacket) {
++ len = dwc_ep->maxpacket;
++ }
++
++ dwords = (len + 3) / 4;
++ txstatus.d32 =
++ DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts);
++ DWC_DEBUGPL(DBG_PCDV, "dtxfsts[%d]=0x%08x\n", epnum,
++ txstatus.d32);
++ }
++
++ DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum,
++ DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts));
++
++ return 1;
++}
++/**
++ * This function does the setup for a data transfer for an EP and
++ * starts the transfer. For an IN transfer, the packets will be
++ * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers,
++ * the packets are unloaded from the Rx FIFO in the ISR. the ISR.
++ *
++ * @param core_if Programming view of DWC_otg controller.
++ * @param ep The EP to start the transfer on.
++ */
++
++void dwc_otg_ep_start_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
++{
++ depctl_data_t depctl;
++ deptsiz_data_t deptsiz;
++ gintmsk_data_t intr_mask = {.d32 = 0 };
++
++ DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s()\n", __func__);
++ DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d "
++ "xfer_buff=%p start_xfer_buff=%p, total_len = %d\n",
++ ep->num, (ep->is_in ? "IN" : "OUT"), ep->xfer_len,
++ ep->xfer_count, ep->xfer_buff, ep->start_xfer_buff,
++ ep->total_len);
++ /* IN endpoint */
++ if (ep->is_in == 1) {
++ dwc_otg_dev_in_ep_regs_t *in_regs =
++ core_if->dev_if->in_ep_regs[ep->num];
++
++ gnptxsts_data_t gtxstatus;
++
++ gtxstatus.d32 =
++ DWC_READ_REG32(&core_if->core_global_regs->gnptxsts);
++
++ if (core_if->en_multiple_tx_fifo == 0
++ && gtxstatus.b.nptxqspcavail == 0 && !core_if->dma_enable) {
++#ifdef DEBUG
++ DWC_PRINTF("TX Queue Full (0x%0x)\n", gtxstatus.d32);
++#endif
++ return;
++ }
++
++ depctl.d32 = DWC_READ_REG32(&(in_regs->diepctl));
++ deptsiz.d32 = DWC_READ_REG32(&(in_regs->dieptsiz));
++
++ if (ep->maxpacket > ep->maxxfer / MAX_PKT_CNT)
++ ep->xfer_len += (ep->maxxfer < (ep->total_len - ep->xfer_len)) ?
++ ep->maxxfer : (ep->total_len - ep->xfer_len);
++ else
++ ep->xfer_len += (MAX_PKT_CNT * ep->maxpacket < (ep->total_len - ep->xfer_len)) ?
++ MAX_PKT_CNT * ep->maxpacket : (ep->total_len - ep->xfer_len);
++
++
++ /* Zero Length Packet? */
++ if ((ep->xfer_len - ep->xfer_count) == 0) {
++ deptsiz.b.xfersize = 0;
++ deptsiz.b.pktcnt = 1;
++ } else {
++ /* Program the transfer size and packet count
++ * as follows: xfersize = N * maxpacket +
++ * short_packet pktcnt = N + (short_packet
++ * exist ? 1 : 0)
++ */
++ deptsiz.b.xfersize = ep->xfer_len - ep->xfer_count;
++ deptsiz.b.pktcnt =
++ (ep->xfer_len - ep->xfer_count - 1 +
++ ep->maxpacket) / ep->maxpacket;
++ if (deptsiz.b.pktcnt > MAX_PKT_CNT) {
++ deptsiz.b.pktcnt = MAX_PKT_CNT;
++ deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket;
++ }
++ if (ep->type == DWC_OTG_EP_TYPE_ISOC)
++ deptsiz.b.mc = deptsiz.b.pktcnt;
++ }
++
++ /* Write the DMA register */
++ if (core_if->dma_enable) {
++ if (core_if->dma_desc_enable == 0) {
++ if (ep->type != DWC_OTG_EP_TYPE_ISOC)
++ deptsiz.b.mc = 1;
++ DWC_WRITE_REG32(&in_regs->dieptsiz,
++ deptsiz.d32);
++ DWC_WRITE_REG32(&(in_regs->diepdma),
++ (uint32_t) ep->dma_addr);
++ } else {
++#ifdef DWC_UTE_CFI
++ /* The descriptor chain should be already initialized by now */
++ if (ep->buff_mode != BM_STANDARD) {
++ DWC_WRITE_REG32(&in_regs->diepdma,
++ ep->descs_dma_addr);
++ } else {
++#endif
++ init_dma_desc_chain(core_if, ep);
++ /** DIEPDMAn Register write */
++ DWC_WRITE_REG32(&in_regs->diepdma,
++ ep->dma_desc_addr);
++#ifdef DWC_UTE_CFI
++ }
++#endif
++ }
++ } else {
++ DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32);
++ if (ep->type != DWC_OTG_EP_TYPE_ISOC) {
++ /**
++ * Enable the Non-Periodic Tx FIFO empty interrupt,
++ * or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode,
++ * the data will be written into the fifo by the ISR.
++ */
++ if (core_if->en_multiple_tx_fifo == 0) {
++ intr_mask.b.nptxfempty = 1;
++ DWC_MODIFY_REG32
++ (&core_if->core_global_regs->gintmsk,
++ intr_mask.d32, intr_mask.d32);
++ } else {
++ /* Enable the Tx FIFO Empty Interrupt for this EP */
++ if (ep->xfer_len > 0) {
++ uint32_t fifoemptymsk = 0;
++ fifoemptymsk = 1 << ep->num;
++ DWC_MODIFY_REG32
++ (&core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
++ 0, fifoemptymsk);
++
++ }
++ }
++ } else {
++ write_isoc_tx_fifo(core_if, ep);
++ }
++ }
++ if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable)
++ depctl.b.nextep = core_if->nextep_seq[ep->num];
++
++ if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
++ dsts_data_t dsts = {.d32 = 0};
++ if (ep->bInterval == 1) {
++ dsts.d32 =
++ DWC_READ_REG32(&core_if->dev_if->
++ dev_global_regs->dsts);
++ ep->frame_num = dsts.b.soffn + ep->bInterval;
++ if (ep->frame_num > 0x3FFF) {
++ ep->frm_overrun = 1;
++ ep->frame_num &= 0x3FFF;
++ } else
++ ep->frm_overrun = 0;
++ if (ep->frame_num & 0x1) {
++ depctl.b.setd1pid = 1;
++ } else {
++ depctl.b.setd0pid = 1;
++ }
++ }
++ }
++ /* EP enable, IN data in FIFO */
++ depctl.b.cnak = 1;
++ depctl.b.epena = 1;
++ DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32);
++
++ } else {
++ /* OUT endpoint */
++ dwc_otg_dev_out_ep_regs_t *out_regs =
++ core_if->dev_if->out_ep_regs[ep->num];
++
++ depctl.d32 = DWC_READ_REG32(&(out_regs->doepctl));
++ deptsiz.d32 = DWC_READ_REG32(&(out_regs->doeptsiz));
++
++ if (!core_if->dma_desc_enable) {
++ if (ep->maxpacket > ep->maxxfer / MAX_PKT_CNT)
++ ep->xfer_len += (ep->maxxfer < (ep->total_len - ep->xfer_len)) ?
++ ep->maxxfer : (ep->total_len - ep->xfer_len);
++ else
++ ep->xfer_len += (MAX_PKT_CNT * ep->maxpacket < (ep->total_len
++ - ep->xfer_len)) ? MAX_PKT_CNT * ep->maxpacket : (ep->total_len - ep->xfer_len);
++ }
++
++ /* Program the transfer size and packet count as follows:
++ *
++ * pktcnt = N
++ * xfersize = N * maxpacket
++ */
++ if ((ep->xfer_len - ep->xfer_count) == 0) {
++ /* Zero Length Packet */
++ deptsiz.b.xfersize = ep->maxpacket;
++ deptsiz.b.pktcnt = 1;
++ } else {
++ deptsiz.b.pktcnt =
++ (ep->xfer_len - ep->xfer_count +
++ (ep->maxpacket - 1)) / ep->maxpacket;
++ if (deptsiz.b.pktcnt > MAX_PKT_CNT) {
++ deptsiz.b.pktcnt = MAX_PKT_CNT;
++ }
++ if (!core_if->dma_desc_enable) {
++ ep->xfer_len =
++ deptsiz.b.pktcnt * ep->maxpacket + ep->xfer_count;
++ }
++ deptsiz.b.xfersize = ep->xfer_len - ep->xfer_count;
++ }
++
++ DWC_DEBUGPL(DBG_PCDV, "ep%d xfersize=%d pktcnt=%d\n",
++ ep->num, deptsiz.b.xfersize, deptsiz.b.pktcnt);
++
++ if (core_if->dma_enable) {
++ if (!core_if->dma_desc_enable) {
++ DWC_WRITE_REG32(&out_regs->doeptsiz,
++ deptsiz.d32);
++
++ DWC_WRITE_REG32(&(out_regs->doepdma),
++ (uint32_t) ep->dma_addr);
++ } else {
++#ifdef DWC_UTE_CFI
++ /* The descriptor chain should be already initialized by now */
++ if (ep->buff_mode != BM_STANDARD) {
++ DWC_WRITE_REG32(&out_regs->doepdma,
++ ep->descs_dma_addr);
++ } else {
++#endif
++ /** This is used for interrupt out transfers*/
++ if (!ep->xfer_len)
++ ep->xfer_len = ep->total_len;
++ init_dma_desc_chain(core_if, ep);
++
++ if (core_if->core_params->dev_out_nak) {
++ if (ep->type == DWC_OTG_EP_TYPE_BULK) {
++ deptsiz.b.pktcnt = (ep->total_len +
++ (ep->maxpacket - 1)) / ep->maxpacket;
++ deptsiz.b.xfersize = ep->total_len;
++ /* Remember initial value of doeptsiz */
++ core_if->start_doeptsiz_val[ep->num] = deptsiz.d32;
++ DWC_WRITE_REG32(&out_regs->doeptsiz,
++ deptsiz.d32);
++ }
++ }
++ /** DOEPDMAn Register write */
++ DWC_WRITE_REG32(&out_regs->doepdma,
++ ep->dma_desc_addr);
++#ifdef DWC_UTE_CFI
++ }
++#endif
++ }
++ } else {
++ DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32);
++ }
++
++ if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
++ dsts_data_t dsts = {.d32 = 0};
++ if (ep->bInterval == 1) {
++ dsts.d32 =
++ DWC_READ_REG32(&core_if->dev_if->
++ dev_global_regs->dsts);
++ ep->frame_num = dsts.b.soffn + ep->bInterval;
++ if (ep->frame_num > 0x3FFF) {
++ ep->frm_overrun = 1;
++ ep->frame_num &= 0x3FFF;
++ } else
++ ep->frm_overrun = 0;
++
++ if (ep->frame_num & 0x1) {
++ depctl.b.setd1pid = 1;
++ } else {
++ depctl.b.setd0pid = 1;
++ }
++ }
++ }
++
++ /* EP enable */
++ depctl.b.cnak = 1;
++ depctl.b.epena = 1;
++
++ DWC_WRITE_REG32(&out_regs->doepctl, depctl.d32);
++
++ DWC_DEBUGPL(DBG_PCD, "DOEPCTL=%08x DOEPTSIZ=%08x\n",
++ DWC_READ_REG32(&out_regs->doepctl),
++ DWC_READ_REG32(&out_regs->doeptsiz));
++ DWC_DEBUGPL(DBG_PCD, "DAINTMSK=%08x GINTMSK=%08x\n",
++ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->
++ daintmsk),
++ DWC_READ_REG32(&core_if->core_global_regs->
++ gintmsk));
++
++ /* Timer is scheduling only for out bulk transfers for
++ * "Device DDMA OUT NAK Enhancement" feature to inform user
++ * about received data payload in case of timeout
++ */
++ if (core_if->core_params->dev_out_nak) {
++ if (ep->type == DWC_OTG_EP_TYPE_BULK) {
++ core_if->ep_xfer_info[ep->num].core_if = core_if;
++ core_if->ep_xfer_info[ep->num].ep = ep;
++ core_if->ep_xfer_info[ep->num].state = 1;
++
++ /* Start a timer for this transfer. */
++ DWC_TIMER_SCHEDULE(core_if->ep_xfer_timer[ep->num], 10000);
++ }
++ }
++ }
++}
++
++/**
++ * This function setup a zero length transfer in Buffer DMA and
++ * Slave modes for usb requests with zero field set
++ *
++ * @param core_if Programming view of DWC_otg controller.
++ * @param ep The EP to start the transfer on.
++ *
++ */
++void dwc_otg_ep_start_zl_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
++{
++
++ depctl_data_t depctl;
++ deptsiz_data_t deptsiz;
++ gintmsk_data_t intr_mask = {.d32 = 0 };
++
++ DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s()\n", __func__);
++ DWC_PRINTF("zero length transfer is called\n");
++
++ /* IN endpoint */
++ if (ep->is_in == 1) {
++ dwc_otg_dev_in_ep_regs_t *in_regs =
++ core_if->dev_if->in_ep_regs[ep->num];
++
++ depctl.d32 = DWC_READ_REG32(&(in_regs->diepctl));
++ deptsiz.d32 = DWC_READ_REG32(&(in_regs->dieptsiz));
++
++ deptsiz.b.xfersize = 0;
++ deptsiz.b.pktcnt = 1;
++
++ /* Write the DMA register */
++ if (core_if->dma_enable) {
++ if (core_if->dma_desc_enable == 0) {
++ deptsiz.b.mc = 1;
++ DWC_WRITE_REG32(&in_regs->dieptsiz,
++ deptsiz.d32);
++ DWC_WRITE_REG32(&(in_regs->diepdma),
++ (uint32_t) ep->dma_addr);
++ }
++ } else {
++ DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32);
++ /**
++ * Enable the Non-Periodic Tx FIFO empty interrupt,
++ * or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode,
++ * the data will be written into the fifo by the ISR.
++ */
++ if (core_if->en_multiple_tx_fifo == 0) {
++ intr_mask.b.nptxfempty = 1;
++ DWC_MODIFY_REG32(&core_if->
++ core_global_regs->gintmsk,
++ intr_mask.d32, intr_mask.d32);
++ } else {
++ /* Enable the Tx FIFO Empty Interrupt for this EP */
++ if (ep->xfer_len > 0) {
++ uint32_t fifoemptymsk = 0;
++ fifoemptymsk = 1 << ep->num;
++ DWC_MODIFY_REG32(&core_if->
++ dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
++ 0, fifoemptymsk);
++ }
++ }
++ }
++
++ if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable)
++ depctl.b.nextep = core_if->nextep_seq[ep->num];
++ /* EP enable, IN data in FIFO */
++ depctl.b.cnak = 1;
++ depctl.b.epena = 1;
++ DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32);
++
++ } else {
++ /* OUT endpoint */
++ dwc_otg_dev_out_ep_regs_t *out_regs =
++ core_if->dev_if->out_ep_regs[ep->num];
++
++ depctl.d32 = DWC_READ_REG32(&(out_regs->doepctl));
++ deptsiz.d32 = DWC_READ_REG32(&(out_regs->doeptsiz));
++
++ /* Zero Length Packet */
++ deptsiz.b.xfersize = ep->maxpacket;
++ deptsiz.b.pktcnt = 1;
++
++ if (core_if->dma_enable) {
++ if (!core_if->dma_desc_enable) {
++ DWC_WRITE_REG32(&out_regs->doeptsiz,
++ deptsiz.d32);
++
++ DWC_WRITE_REG32(&(out_regs->doepdma),
++ (uint32_t) ep->dma_addr);
++ }
++ } else {
++ DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32);
++ }
++
++ /* EP enable */
++ depctl.b.cnak = 1;
++ depctl.b.epena = 1;
++
++ DWC_WRITE_REG32(&out_regs->doepctl, depctl.d32);
++
++ }
++}
++
++/**
++ * This function does the setup for a data transfer for EP0 and starts
++ * the transfer. For an IN transfer, the packets will be loaded into
++ * the appropriate Tx FIFO in the ISR. For OUT transfers, the packets are
++ * unloaded from the Rx FIFO in the ISR.
++ *
++ * @param core_if Programming view of DWC_otg controller.
++ * @param ep The EP0 data.
++ */
++void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
++{
++ depctl_data_t depctl;
++ deptsiz0_data_t deptsiz;
++ gintmsk_data_t intr_mask = {.d32 = 0 };
++ dwc_otg_dev_dma_desc_t *dma_desc;
++
++ DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d "
++ "xfer_buff=%p start_xfer_buff=%p \n",
++ ep->num, (ep->is_in ? "IN" : "OUT"), ep->xfer_len,
++ ep->xfer_count, ep->xfer_buff, ep->start_xfer_buff);
++
++ ep->total_len = ep->xfer_len;
++
++ /* IN endpoint */
++ if (ep->is_in == 1) {
++ dwc_otg_dev_in_ep_regs_t *in_regs =
++ core_if->dev_if->in_ep_regs[0];
++
++ gnptxsts_data_t gtxstatus;
++
++ if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
++ depctl.d32 = DWC_READ_REG32(&in_regs->diepctl);
++ if (depctl.b.epena)
++ return;
++ }
++
++ gtxstatus.d32 =
++ DWC_READ_REG32(&core_if->core_global_regs->gnptxsts);
++
++ /* If dedicated FIFO every time flush fifo before enable ep*/
++ if (core_if->en_multiple_tx_fifo && core_if->snpsid >= OTG_CORE_REV_3_00a)
++ dwc_otg_flush_tx_fifo(core_if, ep->tx_fifo_num);
++
++ if (core_if->en_multiple_tx_fifo == 0
++ && gtxstatus.b.nptxqspcavail == 0
++ && !core_if->dma_enable) {
++#ifdef DEBUG
++ deptsiz.d32 = DWC_READ_REG32(&in_regs->dieptsiz);
++ DWC_DEBUGPL(DBG_PCD, "DIEPCTL0=%0x\n",
++ DWC_READ_REG32(&in_regs->diepctl));
++ DWC_DEBUGPL(DBG_PCD, "DIEPTSIZ0=%0x (sz=%d, pcnt=%d)\n",
++ deptsiz.d32,
++ deptsiz.b.xfersize, deptsiz.b.pktcnt);
++ DWC_PRINTF("TX Queue or FIFO Full (0x%0x)\n",
++ gtxstatus.d32);
++#endif
++ return;
++ }
++
++ depctl.d32 = DWC_READ_REG32(&in_regs->diepctl);
++ deptsiz.d32 = DWC_READ_REG32(&in_regs->dieptsiz);
++
++ /* Zero Length Packet? */
++ if (ep->xfer_len == 0) {
++ deptsiz.b.xfersize = 0;
++ deptsiz.b.pktcnt = 1;
++ } else {
++ /* Program the transfer size and packet count
++ * as follows: xfersize = N * maxpacket +
++ * short_packet pktcnt = N + (short_packet
++ * exist ? 1 : 0)
++ */
++ if (ep->xfer_len > ep->maxpacket) {
++ ep->xfer_len = ep->maxpacket;
++ deptsiz.b.xfersize = ep->maxpacket;
++ } else {
++ deptsiz.b.xfersize = ep->xfer_len;
++ }
++ deptsiz.b.pktcnt = 1;
++
++ }
++ DWC_DEBUGPL(DBG_PCDV,
++ "IN len=%d xfersize=%d pktcnt=%d [%08x]\n",
++ ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt,
++ deptsiz.d32);
++
++ /* Write the DMA register */
++ if (core_if->dma_enable) {
++ if (core_if->dma_desc_enable == 0) {
++ DWC_WRITE_REG32(&in_regs->dieptsiz,
++ deptsiz.d32);
++
++ DWC_WRITE_REG32(&(in_regs->diepdma),
++ (uint32_t) ep->dma_addr);
++ } else {
++ dma_desc = core_if->dev_if->in_desc_addr;
++
++ /** DMA Descriptor Setup */
++ dma_desc->status.b.bs = BS_HOST_BUSY;
++ dma_desc->status.b.l = 1;
++ dma_desc->status.b.ioc = 1;
++ dma_desc->status.b.sp =
++ (ep->xfer_len == ep->maxpacket) ? 0 : 1;
++ dma_desc->status.b.bytes = ep->xfer_len;
++ dma_desc->buf = ep->dma_addr;
++ dma_desc->status.b.sts = 0;
++ dma_desc->status.b.bs = BS_HOST_READY;
++
++ /** DIEPDMA0 Register write */
++ DWC_WRITE_REG32(&in_regs->diepdma,
++ core_if->
++ dev_if->dma_in_desc_addr);
++ }
++ } else {
++ DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32);
++ }
++
++ if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable)
++ depctl.b.nextep = core_if->nextep_seq[ep->num];
++ /* EP enable, IN data in FIFO */
++ depctl.b.cnak = 1;
++ depctl.b.epena = 1;
++ DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32);
++
++ /**
++ * Enable the Non-Periodic Tx FIFO empty interrupt, the
++ * data will be written into the fifo by the ISR.
++ */
++ if (!core_if->dma_enable) {
++ if (core_if->en_multiple_tx_fifo == 0) {
++ intr_mask.b.nptxfempty = 1;
++ DWC_MODIFY_REG32(&core_if->
++ core_global_regs->gintmsk,
++ intr_mask.d32, intr_mask.d32);
++ } else {
++ /* Enable the Tx FIFO Empty Interrupt for this EP */
++ if (ep->xfer_len > 0) {
++ uint32_t fifoemptymsk = 0;
++ fifoemptymsk |= 1 << ep->num;
++ DWC_MODIFY_REG32(&core_if->
++ dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
++ 0, fifoemptymsk);
++ }
++ }
++ }
++ } else {
++ /* OUT endpoint */
++ dwc_otg_dev_out_ep_regs_t *out_regs =
++ core_if->dev_if->out_ep_regs[0];
++
++ depctl.d32 = DWC_READ_REG32(&out_regs->doepctl);
++ deptsiz.d32 = DWC_READ_REG32(&out_regs->doeptsiz);
++
++ /* Program the transfer size and packet count as follows:
++ * xfersize = N * (maxpacket + 4 - (maxpacket % 4))
++ * pktcnt = N */
++ /* Zero Length Packet */
++ deptsiz.b.xfersize = ep->maxpacket;
++ deptsiz.b.pktcnt = 1;
++ if (core_if->snpsid >= OTG_CORE_REV_3_00a)
++ deptsiz.b.supcnt = 3;
++
++ DWC_DEBUGPL(DBG_PCDV, "len=%d xfersize=%d pktcnt=%d\n",
++ ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt);
++
++ if (core_if->dma_enable) {
++ if (!core_if->dma_desc_enable) {
++ DWC_WRITE_REG32(&out_regs->doeptsiz,
++ deptsiz.d32);
++
++ DWC_WRITE_REG32(&(out_regs->doepdma),
++ (uint32_t) ep->dma_addr);
++ } else {
++ dma_desc = core_if->dev_if->out_desc_addr;
++
++ /** DMA Descriptor Setup */
++ dma_desc->status.b.bs = BS_HOST_BUSY;
++ if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
++ dma_desc->status.b.mtrf = 0;
++ dma_desc->status.b.sr = 0;
++ }
++ dma_desc->status.b.l = 1;
++ dma_desc->status.b.ioc = 1;
++ dma_desc->status.b.bytes = ep->maxpacket;
++ dma_desc->buf = ep->dma_addr;
++ dma_desc->status.b.sts = 0;
++ dma_desc->status.b.bs = BS_HOST_READY;
++
++ /** DOEPDMA0 Register write */
++ DWC_WRITE_REG32(&out_regs->doepdma,
++ core_if->dev_if->
++ dma_out_desc_addr);
++ }
++ } else {
++ DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32);
++ }
++
++ /* EP enable */
++ depctl.b.cnak = 1;
++ depctl.b.epena = 1;
++ DWC_WRITE_REG32(&(out_regs->doepctl), depctl.d32);
++ }
++}
++
++/**
++ * This function continues control IN transfers started by
++ * dwc_otg_ep0_start_transfer, when the transfer does not fit in a
++ * single packet. NOTE: The DIEPCTL0/DOEPCTL0 registers only have one
++ * bit for the packet count.
++ *
++ * @param core_if Programming view of DWC_otg controller.
++ * @param ep The EP0 data.
++ */
++void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
++{
++ depctl_data_t depctl;
++ deptsiz0_data_t deptsiz;
++ gintmsk_data_t intr_mask = {.d32 = 0 };
++ dwc_otg_dev_dma_desc_t *dma_desc;
++
++ if (ep->is_in == 1) {
++ dwc_otg_dev_in_ep_regs_t *in_regs =
++ core_if->dev_if->in_ep_regs[0];
++ gnptxsts_data_t tx_status = {.d32 = 0 };
++
++ tx_status.d32 =
++ DWC_READ_REG32(&core_if->core_global_regs->gnptxsts);
++ /** @todo Should there be check for room in the Tx
++ * Status Queue. If not remove the code above this comment. */
++
++ depctl.d32 = DWC_READ_REG32(&in_regs->diepctl);
++ deptsiz.d32 = DWC_READ_REG32(&in_regs->dieptsiz);
++
++ /* Program the transfer size and packet count
++ * as follows: xfersize = N * maxpacket +
++ * short_packet pktcnt = N + (short_packet
++ * exist ? 1 : 0)
++ */
++
++ if (core_if->dma_desc_enable == 0) {
++ deptsiz.b.xfersize =
++ (ep->total_len - ep->xfer_count) >
++ ep->maxpacket ? ep->maxpacket : (ep->total_len -
++ ep->xfer_count);
++ deptsiz.b.pktcnt = 1;
++ if (core_if->dma_enable == 0) {
++ ep->xfer_len += deptsiz.b.xfersize;
++ } else {
++ ep->xfer_len = deptsiz.b.xfersize;
++ }
++ DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32);
++ } else {
++ ep->xfer_len =
++ (ep->total_len - ep->xfer_count) >
++ ep->maxpacket ? ep->maxpacket : (ep->total_len -
++ ep->xfer_count);
++
++ dma_desc = core_if->dev_if->in_desc_addr;
++
++ /** DMA Descriptor Setup */
++ dma_desc->status.b.bs = BS_HOST_BUSY;
++ dma_desc->status.b.l = 1;
++ dma_desc->status.b.ioc = 1;
++ dma_desc->status.b.sp =
++ (ep->xfer_len == ep->maxpacket) ? 0 : 1;
++ dma_desc->status.b.bytes = ep->xfer_len;
++ dma_desc->buf = ep->dma_addr;
++ dma_desc->status.b.sts = 0;
++ dma_desc->status.b.bs = BS_HOST_READY;
++
++ /** DIEPDMA0 Register write */
++ DWC_WRITE_REG32(&in_regs->diepdma,
++ core_if->dev_if->dma_in_desc_addr);
++ }
++
++ DWC_DEBUGPL(DBG_PCDV,
++ "IN len=%d xfersize=%d pktcnt=%d [%08x]\n",
++ ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt,
++ deptsiz.d32);
++
++ /* Write the DMA register */
++ if (core_if->hwcfg2.b.architecture == DWC_INT_DMA_ARCH) {
++ if (core_if->dma_desc_enable == 0)
++ DWC_WRITE_REG32(&(in_regs->diepdma),
++ (uint32_t) ep->dma_addr);
++ }
++ if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable)
++ depctl.b.nextep = core_if->nextep_seq[ep->num];
++ /* EP enable, IN data in FIFO */
++ depctl.b.cnak = 1;
++ depctl.b.epena = 1;
++ DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32);
++
++ /**
++ * Enable the Non-Periodic Tx FIFO empty interrupt, the
++ * data will be written into the fifo by the ISR.
++ */
++ if (!core_if->dma_enable) {
++ if (core_if->en_multiple_tx_fifo == 0) {
++ /* First clear it from GINTSTS */
++ intr_mask.b.nptxfempty = 1;
++ DWC_MODIFY_REG32(&core_if->
++ core_global_regs->gintmsk,
++ intr_mask.d32, intr_mask.d32);
++
++ } else {
++ /* Enable the Tx FIFO Empty Interrupt for this EP */
++ if (ep->xfer_len > 0) {
++ uint32_t fifoemptymsk = 0;
++ fifoemptymsk |= 1 << ep->num;
++ DWC_MODIFY_REG32(&core_if->
++ dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
++ 0, fifoemptymsk);
++ }
++ }
++ }
++ } else {
++ dwc_otg_dev_out_ep_regs_t *out_regs =
++ core_if->dev_if->out_ep_regs[0];
++
++ depctl.d32 = DWC_READ_REG32(&out_regs->doepctl);
++ deptsiz.d32 = DWC_READ_REG32(&out_regs->doeptsiz);
++
++ /* Program the transfer size and packet count
++ * as follows: xfersize = N * maxpacket +
++ * short_packet pktcnt = N + (short_packet
++ * exist ? 1 : 0)
++ */
++ deptsiz.b.xfersize = ep->maxpacket;
++ deptsiz.b.pktcnt = 1;
++
++ if (core_if->dma_desc_enable == 0) {
++ DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32);
++ } else {
++ dma_desc = core_if->dev_if->out_desc_addr;
++
++ /** DMA Descriptor Setup */
++ dma_desc->status.b.bs = BS_HOST_BUSY;
++ dma_desc->status.b.l = 1;
++ dma_desc->status.b.ioc = 1;
++ dma_desc->status.b.bytes = ep->maxpacket;
++ dma_desc->buf = ep->dma_addr;
++ dma_desc->status.b.sts = 0;
++ dma_desc->status.b.bs = BS_HOST_READY;
++
++ /** DOEPDMA0 Register write */
++ DWC_WRITE_REG32(&out_regs->doepdma,
++ core_if->dev_if->dma_out_desc_addr);
++ }
++
++ DWC_DEBUGPL(DBG_PCDV,
++ "IN len=%d xfersize=%d pktcnt=%d [%08x]\n",
++ ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt,
++ deptsiz.d32);
++
++ /* Write the DMA register */
++ if (core_if->hwcfg2.b.architecture == DWC_INT_DMA_ARCH) {
++ if (core_if->dma_desc_enable == 0)
++ DWC_WRITE_REG32(&(out_regs->doepdma),
++ (uint32_t) ep->dma_addr);
++
++ }
++
++ /* EP enable, IN data in FIFO */
++ depctl.b.cnak = 1;
++ depctl.b.epena = 1;
++ DWC_WRITE_REG32(&out_regs->doepctl, depctl.d32);
++
++ }
++}
++
++#ifdef DEBUG
++void dump_msg(const u8 * buf, unsigned int length)
++{
++ unsigned int start, num, i;
++ char line[52], *p;
++
++ if (length >= 512)
++ return;
++ start = 0;
++ while (length > 0) {
++ num = length < 16u ? length : 16u;
++ p = line;
++ for (i = 0; i < num; ++i) {
++ if (i == 8)
++ *p++ = ' ';
++ DWC_SPRINTF(p, " %02x", buf[i]);
++ p += 3;
++ }
++ *p = 0;
++ DWC_PRINTF("%6x: %s\n", start, line);
++ buf += num;
++ start += num;
++ length -= num;
++ }
++}
++#else
++static inline void dump_msg(const u8 * buf, unsigned int length)
++{
++}
++#endif
++
++/**
++ * This function writes a packet into the Tx FIFO associated with the
++ * EP. For non-periodic EPs the non-periodic Tx FIFO is written. For
++ * periodic EPs the periodic Tx FIFO associated with the EP is written
++ * with all packets for the next micro-frame.
++ *
++ * @param core_if Programming view of DWC_otg controller.
++ * @param ep The EP to write packet for.
++ * @param dma Indicates if DMA is being used.
++ */
++void dwc_otg_ep_write_packet(dwc_otg_core_if_t * core_if, dwc_ep_t * ep,
++ int dma)
++{
++ /**
++ * The buffer is padded to DWORD on a per packet basis in
++ * slave/dma mode if the MPS is not DWORD aligned. The last
++ * packet, if short, is also padded to a multiple of DWORD.
++ *
++ * ep->xfer_buff always starts DWORD aligned in memory and is a
++ * multiple of DWORD in length
++ *
++ * ep->xfer_len can be any number of bytes
++ *
++ * ep->xfer_count is a multiple of ep->maxpacket until the last
++ * packet
++ *
++ * FIFO access is DWORD */
++
++ uint32_t i;
++ uint32_t byte_count;
++ uint32_t dword_count;
++ uint32_t *fifo;
++ uint32_t *data_buff = (uint32_t *) ep->xfer_buff;
++
++ DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p)\n", __func__, core_if,
++ ep);
++ if (ep->xfer_count >= ep->xfer_len) {
++ DWC_WARN("%s() No data for EP%d!!!\n", __func__, ep->num);
++ return;
++ }
++
++ /* Find the byte length of the packet either short packet or MPS */
++ if ((ep->xfer_len - ep->xfer_count) < ep->maxpacket) {
++ byte_count = ep->xfer_len - ep->xfer_count;
++ } else {
++ byte_count = ep->maxpacket;
++ }
++
++ /* Find the DWORD length, padded by extra bytes as neccessary if MPS
++ * is not a multiple of DWORD */
++ dword_count = (byte_count + 3) / 4;
++
++#ifdef VERBOSE
++ dump_msg(ep->xfer_buff, byte_count);
++#endif
++
++ /**@todo NGS Where are the Periodic Tx FIFO addresses
++ * intialized? What should this be? */
++
++ fifo = core_if->data_fifo[ep->num];
++
++ DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "fifo=%p buff=%p *p=%08x bc=%d\n",
++ fifo, data_buff, *data_buff, byte_count);
++
++ if (!dma) {
++ for (i = 0; i < dword_count; i++, data_buff++) {
++ DWC_WRITE_REG32(fifo, *data_buff);
++ }
++ }
++
++ ep->xfer_count += byte_count;
++ ep->xfer_buff += byte_count;
++ ep->dma_addr += byte_count;
++}
++
++/**
++ * Set the EP STALL.
++ *
++ * @param core_if Programming view of DWC_otg controller.
++ * @param ep The EP to set the stall on.
++ */
++void dwc_otg_ep_set_stall(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
++{
++ depctl_data_t depctl;
++ volatile uint32_t *depctl_addr;
++
++ DWC_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, ep->num,
++ (ep->is_in ? "IN" : "OUT"));
++
++ if (ep->is_in == 1) {
++ depctl_addr = &(core_if->dev_if->in_ep_regs[ep->num]->diepctl);
++ depctl.d32 = DWC_READ_REG32(depctl_addr);
++
++ /* set the disable and stall bits */
++ if (depctl.b.epena) {
++ depctl.b.epdis = 1;
++ }
++ depctl.b.stall = 1;
++ DWC_WRITE_REG32(depctl_addr, depctl.d32);
++ } else {
++ depctl_addr = &(core_if->dev_if->out_ep_regs[ep->num]->doepctl);
++ depctl.d32 = DWC_READ_REG32(depctl_addr);
++
++ /* set the stall bit */
++ depctl.b.stall = 1;
++ DWC_WRITE_REG32(depctl_addr, depctl.d32);
++ }
++
++ DWC_DEBUGPL(DBG_PCD, "DEPCTL=%0x\n", DWC_READ_REG32(depctl_addr));
++
++ return;
++}
++
++/**
++ * Clear the EP STALL.
++ *
++ * @param core_if Programming view of DWC_otg controller.
++ * @param ep The EP to clear stall from.
++ */
++void dwc_otg_ep_clear_stall(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
++{
++ depctl_data_t depctl;
++ volatile uint32_t *depctl_addr;
++
++ DWC_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, ep->num,
++ (ep->is_in ? "IN" : "OUT"));
++
++ if (ep->is_in == 1) {
++ depctl_addr = &(core_if->dev_if->in_ep_regs[ep->num]->diepctl);
++ } else {
++ depctl_addr = &(core_if->dev_if->out_ep_regs[ep->num]->doepctl);
++ }
++
++ depctl.d32 = DWC_READ_REG32(depctl_addr);
++
++ /* clear the stall bits */
++ depctl.b.stall = 0;
++
++ /*
++ * USB Spec 9.4.5: For endpoints using data toggle, regardless
++ * of whether an endpoint has the Halt feature set, a
++ * ClearFeature(ENDPOINT_HALT) request always results in the
++ * data toggle being reinitialized to DATA0.
++ */
++ if (ep->type == DWC_OTG_EP_TYPE_INTR ||
++ ep->type == DWC_OTG_EP_TYPE_BULK) {
++ depctl.b.setd0pid = 1; /* DATA0 */
++ }
++
++ DWC_WRITE_REG32(depctl_addr, depctl.d32);
++ DWC_DEBUGPL(DBG_PCD, "DEPCTL=%0x\n", DWC_READ_REG32(depctl_addr));
++ return;
++}
++
++/**
++ * This function reads a packet from the Rx FIFO into the destination
++ * buffer. To read SETUP data use dwc_otg_read_setup_packet.
++ *
++ * @param core_if Programming view of DWC_otg controller.
++ * @param dest Destination buffer for the packet.
++ * @param bytes Number of bytes to copy to the destination.
++ */
++void dwc_otg_read_packet(dwc_otg_core_if_t * core_if,
++ uint8_t * dest, uint16_t bytes)
++{
++ int i;
++ int word_count = (bytes + 3) / 4;
++
++ volatile uint32_t *fifo = core_if->data_fifo[0];
++ uint32_t *data_buff = (uint32_t *) dest;
++
++ /**
++ * @todo Account for the case where _dest is not dword aligned. This
++ * requires reading data from the FIFO into a uint32_t temp buffer,
++ * then moving it into the data buffer.
++ */
++
++ DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p,%d)\n", __func__,
++ core_if, dest, bytes);
++
++ for (i = 0; i < word_count; i++, data_buff++) {
++ *data_buff = DWC_READ_REG32(fifo);
++ }
++
++ return;
++}
++
++/**
++ * This functions reads the device registers and prints them
++ *
++ * @param core_if Programming view of DWC_otg controller.
++ */
++void dwc_otg_dump_dev_registers(dwc_otg_core_if_t * core_if)
++{
++ int i;
++ volatile uint32_t *addr;
++
++ DWC_PRINTF("Device Global Registers\n");
++ addr = &core_if->dev_if->dev_global_regs->dcfg;
++ DWC_PRINTF("DCFG @0x%08lX : 0x%08X\n",
++ (unsigned long)addr, DWC_READ_REG32(addr));
++ addr = &core_if->dev_if->dev_global_regs->dctl;
++ DWC_PRINTF("DCTL @0x%08lX : 0x%08X\n",
++ (unsigned long)addr, DWC_READ_REG32(addr));
++ addr = &core_if->dev_if->dev_global_regs->dsts;
++ DWC_PRINTF("DSTS @0x%08lX : 0x%08X\n",
++ (unsigned long)addr, DWC_READ_REG32(addr));
++ addr = &core_if->dev_if->dev_global_regs->diepmsk;
++ DWC_PRINTF("DIEPMSK @0x%08lX : 0x%08X\n", (unsigned long)addr,
++ DWC_READ_REG32(addr));
++ addr = &core_if->dev_if->dev_global_regs->doepmsk;
++ DWC_PRINTF("DOEPMSK @0x%08lX : 0x%08X\n", (unsigned long)addr,
++ DWC_READ_REG32(addr));
++ addr = &core_if->dev_if->dev_global_regs->daint;
++ DWC_PRINTF("DAINT @0x%08lX : 0x%08X\n", (unsigned long)addr,
++ DWC_READ_REG32(addr));
++ addr = &core_if->dev_if->dev_global_regs->daintmsk;
++ DWC_PRINTF("DAINTMSK @0x%08lX : 0x%08X\n", (unsigned long)addr,
++ DWC_READ_REG32(addr));
++ addr = &core_if->dev_if->dev_global_regs->dtknqr1;
++ DWC_PRINTF("DTKNQR1 @0x%08lX : 0x%08X\n", (unsigned long)addr,
++ DWC_READ_REG32(addr));
++ if (core_if->hwcfg2.b.dev_token_q_depth > 6) {
++ addr = &core_if->dev_if->dev_global_regs->dtknqr2;
++ DWC_PRINTF("DTKNQR2 @0x%08lX : 0x%08X\n",
++ (unsigned long)addr, DWC_READ_REG32(addr));
++ }
++
++ addr = &core_if->dev_if->dev_global_regs->dvbusdis;
++ DWC_PRINTF("DVBUSID @0x%08lX : 0x%08X\n", (unsigned long)addr,
++ DWC_READ_REG32(addr));
++
++ addr = &core_if->dev_if->dev_global_regs->dvbuspulse;
++ DWC_PRINTF("DVBUSPULSE @0x%08lX : 0x%08X\n",
++ (unsigned long)addr, DWC_READ_REG32(addr));
++
++ addr = &core_if->dev_if->dev_global_regs->dtknqr3_dthrctl;
++ DWC_PRINTF("DTKNQR3_DTHRCTL @0x%08lX : 0x%08X\n",
++ (unsigned long)addr, DWC_READ_REG32(addr));
++
++ if (core_if->hwcfg2.b.dev_token_q_depth > 22) {
++ addr = &core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk;
++ DWC_PRINTF("DTKNQR4 @0x%08lX : 0x%08X\n",
++ (unsigned long)addr, DWC_READ_REG32(addr));
++ }
++
++ addr = &core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk;
++ DWC_PRINTF("FIFOEMPMSK @0x%08lX : 0x%08X\n", (unsigned long)addr,
++ DWC_READ_REG32(addr));
++
++ if (core_if->hwcfg2.b.multi_proc_int) {
++
++ addr = &core_if->dev_if->dev_global_regs->deachint;
++ DWC_PRINTF("DEACHINT @0x%08lX : 0x%08X\n",
++ (unsigned long)addr, DWC_READ_REG32(addr));
++ addr = &core_if->dev_if->dev_global_regs->deachintmsk;
++ DWC_PRINTF("DEACHINTMSK @0x%08lX : 0x%08X\n",
++ (unsigned long)addr, DWC_READ_REG32(addr));
++
++ for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
++ addr =
++ &core_if->dev_if->
++ dev_global_regs->diepeachintmsk[i];
++ DWC_PRINTF("DIEPEACHINTMSK[%d] @0x%08lX : 0x%08X\n",
++ i, (unsigned long)addr,
++ DWC_READ_REG32(addr));
++ }
++
++ for (i = 0; i <= core_if->dev_if->num_out_eps; i++) {
++ addr =
++ &core_if->dev_if->
++ dev_global_regs->doepeachintmsk[i];
++ DWC_PRINTF("DOEPEACHINTMSK[%d] @0x%08lX : 0x%08X\n",
++ i, (unsigned long)addr,
++ DWC_READ_REG32(addr));
++ }
++ }
++
++ for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
++ DWC_PRINTF("Device IN EP %d Registers\n", i);
++ addr = &core_if->dev_if->in_ep_regs[i]->diepctl;
++ DWC_PRINTF("DIEPCTL @0x%08lX : 0x%08X\n",
++ (unsigned long)addr, DWC_READ_REG32(addr));
++ addr = &core_if->dev_if->in_ep_regs[i]->diepint;
++ DWC_PRINTF("DIEPINT @0x%08lX : 0x%08X\n",
++ (unsigned long)addr, DWC_READ_REG32(addr));
++ addr = &core_if->dev_if->in_ep_regs[i]->dieptsiz;
++ DWC_PRINTF("DIETSIZ @0x%08lX : 0x%08X\n",
++ (unsigned long)addr, DWC_READ_REG32(addr));
++ addr = &core_if->dev_if->in_ep_regs[i]->diepdma;
++ DWC_PRINTF("DIEPDMA @0x%08lX : 0x%08X\n",
++ (unsigned long)addr, DWC_READ_REG32(addr));
++ addr = &core_if->dev_if->in_ep_regs[i]->dtxfsts;
++ DWC_PRINTF("DTXFSTS @0x%08lX : 0x%08X\n",
++ (unsigned long)addr, DWC_READ_REG32(addr));
++ addr = &core_if->dev_if->in_ep_regs[i]->diepdmab;
++ DWC_PRINTF("DIEPDMAB @0x%08lX : 0x%08X\n",
++ (unsigned long)addr, 0 /*DWC_READ_REG32(addr) */ );
++ }
++
++ for (i = 0; i <= core_if->dev_if->num_out_eps; i++) {
++ DWC_PRINTF("Device OUT EP %d Registers\n", i);
++ addr = &core_if->dev_if->out_ep_regs[i]->doepctl;
++ DWC_PRINTF("DOEPCTL @0x%08lX : 0x%08X\n",
++ (unsigned long)addr, DWC_READ_REG32(addr));
++ addr = &core_if->dev_if->out_ep_regs[i]->doepint;
++ DWC_PRINTF("DOEPINT @0x%08lX : 0x%08X\n",
++ (unsigned long)addr, DWC_READ_REG32(addr));
++ addr = &core_if->dev_if->out_ep_regs[i]->doeptsiz;
++ DWC_PRINTF("DOETSIZ @0x%08lX : 0x%08X\n",
++ (unsigned long)addr, DWC_READ_REG32(addr));
++ addr = &core_if->dev_if->out_ep_regs[i]->doepdma;
++ DWC_PRINTF("DOEPDMA @0x%08lX : 0x%08X\n",
++ (unsigned long)addr, DWC_READ_REG32(addr));
++ if (core_if->dma_enable) { /* Don't access this register in SLAVE mode */
++ addr = &core_if->dev_if->out_ep_regs[i]->doepdmab;
++ DWC_PRINTF("DOEPDMAB @0x%08lX : 0x%08X\n",
++ (unsigned long)addr, DWC_READ_REG32(addr));
++ }
++
++ }
++}
++
++/**
++ * This functions reads the SPRAM and prints its content
++ *
++ * @param core_if Programming view of DWC_otg controller.
++ */
++void dwc_otg_dump_spram(dwc_otg_core_if_t * core_if)
++{
++ volatile uint8_t *addr, *start_addr, *end_addr;
++
++ DWC_PRINTF("SPRAM Data:\n");
++ start_addr = (void *)core_if->core_global_regs;
++ DWC_PRINTF("Base Address: 0x%8lX\n", (unsigned long)start_addr);
++ start_addr += 0x00028000;
++ end_addr = (void *)core_if->core_global_regs;
++ end_addr += 0x000280e0;
++
++ for (addr = start_addr; addr < end_addr; addr += 16) {
++ DWC_PRINTF
++ ("0x%8lX:\t%2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X\n",
++ (unsigned long)addr, addr[0], addr[1], addr[2], addr[3],
++ addr[4], addr[5], addr[6], addr[7], addr[8], addr[9],
++ addr[10], addr[11], addr[12], addr[13], addr[14], addr[15]
++ );
++ }
++
++ return;
++}
++
++/**
++ * This function reads the host registers and prints them
++ *
++ * @param core_if Programming view of DWC_otg controller.
++ */
++void dwc_otg_dump_host_registers(dwc_otg_core_if_t * core_if)
++{
++ int i;
++ volatile uint32_t *addr;
++
++ DWC_PRINTF("Host Global Registers\n");
++ addr = &core_if->host_if->host_global_regs->hcfg;
++ DWC_PRINTF("HCFG @0x%08lX : 0x%08X\n",
++ (unsigned long)addr, DWC_READ_REG32(addr));
++ addr = &core_if->host_if->host_global_regs->hfir;
++ DWC_PRINTF("HFIR @0x%08lX : 0x%08X\n",
++ (unsigned long)addr, DWC_READ_REG32(addr));
++ addr = &core_if->host_if->host_global_regs->hfnum;
++ DWC_PRINTF("HFNUM @0x%08lX : 0x%08X\n", (unsigned long)addr,
++ DWC_READ_REG32(addr));
++ addr = &core_if->host_if->host_global_regs->hptxsts;
++ DWC_PRINTF("HPTXSTS @0x%08lX : 0x%08X\n", (unsigned long)addr,
++ DWC_READ_REG32(addr));
++ addr = &core_if->host_if->host_global_regs->haint;
++ DWC_PRINTF("HAINT @0x%08lX : 0x%08X\n", (unsigned long)addr,
++ DWC_READ_REG32(addr));
++ addr = &core_if->host_if->host_global_regs->haintmsk;
++ DWC_PRINTF("HAINTMSK @0x%08lX : 0x%08X\n", (unsigned long)addr,
++ DWC_READ_REG32(addr));
++ if (core_if->dma_desc_enable) {
++ addr = &core_if->host_if->host_global_regs->hflbaddr;
++ DWC_PRINTF("HFLBADDR @0x%08lX : 0x%08X\n",
++ (unsigned long)addr, DWC_READ_REG32(addr));
++ }
++
++ addr = core_if->host_if->hprt0;
++ DWC_PRINTF("HPRT0 @0x%08lX : 0x%08X\n", (unsigned long)addr,
++ DWC_READ_REG32(addr));
++
++ for (i = 0; i < core_if->core_params->host_channels; i++) {
++ DWC_PRINTF("Host Channel %d Specific Registers\n", i);
++ addr = &core_if->host_if->hc_regs[i]->hcchar;
++ DWC_PRINTF("HCCHAR @0x%08lX : 0x%08X\n",
++ (unsigned long)addr, DWC_READ_REG32(addr));
++ addr = &core_if->host_if->hc_regs[i]->hcsplt;
++ DWC_PRINTF("HCSPLT @0x%08lX : 0x%08X\n",
++ (unsigned long)addr, DWC_READ_REG32(addr));
++ addr = &core_if->host_if->hc_regs[i]->hcint;
++ DWC_PRINTF("HCINT @0x%08lX : 0x%08X\n",
++ (unsigned long)addr, DWC_READ_REG32(addr));
++ addr = &core_if->host_if->hc_regs[i]->hcintmsk;
++ DWC_PRINTF("HCINTMSK @0x%08lX : 0x%08X\n",
++ (unsigned long)addr, DWC_READ_REG32(addr));
++ addr = &core_if->host_if->hc_regs[i]->hctsiz;
++ DWC_PRINTF("HCTSIZ @0x%08lX : 0x%08X\n",
++ (unsigned long)addr, DWC_READ_REG32(addr));
++ addr = &core_if->host_if->hc_regs[i]->hcdma;
++ DWC_PRINTF("HCDMA @0x%08lX : 0x%08X\n",
++ (unsigned long)addr, DWC_READ_REG32(addr));
++ if (core_if->dma_desc_enable) {
++ addr = &core_if->host_if->hc_regs[i]->hcdmab;
++ DWC_PRINTF("HCDMAB @0x%08lX : 0x%08X\n",
++ (unsigned long)addr, DWC_READ_REG32(addr));
++ }
++
++ }
++ return;
++}
++
++/**
++ * This function reads the core global registers and prints them
++ *
++ * @param core_if Programming view of DWC_otg controller.
++ */
++void dwc_otg_dump_global_registers(dwc_otg_core_if_t * core_if)
++{
++ int i, ep_num;
++ volatile uint32_t *addr;
++ char *txfsiz;
++
++ DWC_PRINTF("Core Global Registers\n");
++ addr = &core_if->core_global_regs->gotgctl;
++ DWC_PRINTF("GOTGCTL @0x%08lX : 0x%08X\n", (unsigned long)addr,
++ DWC_READ_REG32(addr));
++ addr = &core_if->core_global_regs->gotgint;
++ DWC_PRINTF("GOTGINT @0x%08lX : 0x%08X\n", (unsigned long)addr,
++ DWC_READ_REG32(addr));
++ addr = &core_if->core_global_regs->gahbcfg;
++ DWC_PRINTF("GAHBCFG @0x%08lX : 0x%08X\n", (unsigned long)addr,
++ DWC_READ_REG32(addr));
++ addr = &core_if->core_global_regs->gusbcfg;
++ DWC_PRINTF("GUSBCFG @0x%08lX : 0x%08X\n", (unsigned long)addr,
++ DWC_READ_REG32(addr));
++ addr = &core_if->core_global_regs->grstctl;
++ DWC_PRINTF("GRSTCTL @0x%08lX : 0x%08X\n", (unsigned long)addr,
++ DWC_READ_REG32(addr));
++ addr = &core_if->core_global_regs->gintsts;
++ DWC_PRINTF("GINTSTS @0x%08lX : 0x%08X\n", (unsigned long)addr,
++ DWC_READ_REG32(addr));
++ addr = &core_if->core_global_regs->gintmsk;
++ DWC_PRINTF("GINTMSK @0x%08lX : 0x%08X\n", (unsigned long)addr,
++ DWC_READ_REG32(addr));
++ addr = &core_if->core_global_regs->grxstsr;
++ DWC_PRINTF("GRXSTSR @0x%08lX : 0x%08X\n", (unsigned long)addr,
++ DWC_READ_REG32(addr));
++ addr = &core_if->core_global_regs->grxfsiz;
++ DWC_PRINTF("GRXFSIZ @0x%08lX : 0x%08X\n", (unsigned long)addr,
++ DWC_READ_REG32(addr));
++ addr = &core_if->core_global_regs->gnptxfsiz;
++ DWC_PRINTF("GNPTXFSIZ @0x%08lX : 0x%08X\n", (unsigned long)addr,
++ DWC_READ_REG32(addr));
++ addr = &core_if->core_global_regs->gnptxsts;
++ DWC_PRINTF("GNPTXSTS @0x%08lX : 0x%08X\n", (unsigned long)addr,
++ DWC_READ_REG32(addr));
++ addr = &core_if->core_global_regs->gi2cctl;
++ DWC_PRINTF("GI2CCTL @0x%08lX : 0x%08X\n", (unsigned long)addr,
++ DWC_READ_REG32(addr));
++ addr = &core_if->core_global_regs->gpvndctl;
++ DWC_PRINTF("GPVNDCTL @0x%08lX : 0x%08X\n", (unsigned long)addr,
++ DWC_READ_REG32(addr));
++ addr = &core_if->core_global_regs->ggpio;
++ DWC_PRINTF("GGPIO @0x%08lX : 0x%08X\n", (unsigned long)addr,
++ DWC_READ_REG32(addr));
++ addr = &core_if->core_global_regs->guid;
++ DWC_PRINTF("GUID @0x%08lX : 0x%08X\n",
++ (unsigned long)addr, DWC_READ_REG32(addr));
++ addr = &core_if->core_global_regs->gsnpsid;
++ DWC_PRINTF("GSNPSID @0x%08lX : 0x%08X\n", (unsigned long)addr,
++ DWC_READ_REG32(addr));
++ addr = &core_if->core_global_regs->ghwcfg1;
++ DWC_PRINTF("GHWCFG1 @0x%08lX : 0x%08X\n", (unsigned long)addr,
++ DWC_READ_REG32(addr));
++ addr = &core_if->core_global_regs->ghwcfg2;
++ DWC_PRINTF("GHWCFG2 @0x%08lX : 0x%08X\n", (unsigned long)addr,
++ DWC_READ_REG32(addr));
++ addr = &core_if->core_global_regs->ghwcfg3;
++ DWC_PRINTF("GHWCFG3 @0x%08lX : 0x%08X\n", (unsigned long)addr,
++ DWC_READ_REG32(addr));
++ addr = &core_if->core_global_regs->ghwcfg4;
++ DWC_PRINTF("GHWCFG4 @0x%08lX : 0x%08X\n", (unsigned long)addr,
++ DWC_READ_REG32(addr));
++ addr = &core_if->core_global_regs->glpmcfg;
++ DWC_PRINTF("GLPMCFG @0x%08lX : 0x%08X\n", (unsigned long)addr,
++ DWC_READ_REG32(addr));
++ addr = &core_if->core_global_regs->gpwrdn;
++ DWC_PRINTF("GPWRDN @0x%08lX : 0x%08X\n", (unsigned long)addr,
++ DWC_READ_REG32(addr));
++ addr = &core_if->core_global_regs->gdfifocfg;
++ DWC_PRINTF("GDFIFOCFG @0x%08lX : 0x%08X\n", (unsigned long)addr,
++ DWC_READ_REG32(addr));
++ addr = &core_if->core_global_regs->adpctl;
++ DWC_PRINTF("ADPCTL @0x%08lX : 0x%08X\n", (unsigned long)addr,
++ dwc_otg_adp_read_reg(core_if));
++ addr = &core_if->core_global_regs->hptxfsiz;
++ DWC_PRINTF("HPTXFSIZ @0x%08lX : 0x%08X\n", (unsigned long)addr,
++ DWC_READ_REG32(addr));
++
++ if (core_if->en_multiple_tx_fifo == 0) {
++ ep_num = core_if->hwcfg4.b.num_dev_perio_in_ep;
++ txfsiz = "DPTXFSIZ";
++ } else {
++ ep_num = core_if->hwcfg4.b.num_in_eps;
++ txfsiz = "DIENPTXF";
++ }
++ for (i = 0; i < ep_num; i++) {
++ addr = &core_if->core_global_regs->dtxfsiz[i];
++ DWC_PRINTF("%s[%d] @0x%08lX : 0x%08X\n", txfsiz, i + 1,
++ (unsigned long)addr, DWC_READ_REG32(addr));
++ }
++ addr = core_if->pcgcctl;
++ DWC_PRINTF("PCGCCTL @0x%08lX : 0x%08X\n", (unsigned long)addr,
++ DWC_READ_REG32(addr));
++}
++
++/**
++ * Flush a Tx FIFO.
++ *
++ * @param core_if Programming view of DWC_otg controller.
++ * @param num Tx FIFO to flush.
++ */
++void dwc_otg_flush_tx_fifo(dwc_otg_core_if_t * core_if, const int num)
++{
++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
++ volatile grstctl_t greset = {.d32 = 0 };
++ int count = 0;
++
++ DWC_DEBUGPL((DBG_CIL | DBG_PCDV), "Flush Tx FIFO %d\n", num);
++
++ greset.b.txfflsh = 1;
++ greset.b.txfnum = num;
++ DWC_WRITE_REG32(&global_regs->grstctl, greset.d32);
++
++ do {
++ greset.d32 = DWC_READ_REG32(&global_regs->grstctl);
++ if (++count > 10000) {
++ DWC_WARN("%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n",
++ __func__, greset.d32,
++ DWC_READ_REG32(&global_regs->gnptxsts));
++ break;
++ }
++ dwc_udelay(1);
++ } while (greset.b.txfflsh == 1);
++
++ /* Wait for 3 PHY Clocks */
++ dwc_udelay(1);
++}
++
++/**
++ * Flush Rx FIFO.
++ *
++ * @param core_if Programming view of DWC_otg controller.
++ */
++void dwc_otg_flush_rx_fifo(dwc_otg_core_if_t * core_if)
++{
++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
++ volatile grstctl_t greset = {.d32 = 0 };
++ int count = 0;
++
++ DWC_DEBUGPL((DBG_CIL | DBG_PCDV), "%s\n", __func__);
++ /*
++ *
++ */
++ greset.b.rxfflsh = 1;
++ DWC_WRITE_REG32(&global_regs->grstctl, greset.d32);
++
++ do {
++ greset.d32 = DWC_READ_REG32(&global_regs->grstctl);
++ if (++count > 10000) {
++ DWC_WARN("%s() HANG! GRSTCTL=%0x\n", __func__,
++ greset.d32);
++ break;
++ }
++ dwc_udelay(1);
++ } while (greset.b.rxfflsh == 1);
++
++ /* Wait for 3 PHY Clocks */
++ dwc_udelay(1);
++}
++
++/**
++ * Do core a soft reset of the core. Be careful with this because it
++ * resets all the internal state machines of the core.
++ */
++void dwc_otg_core_reset(dwc_otg_core_if_t * core_if)
++{
++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
++ volatile grstctl_t greset = {.d32 = 0 };
++ int count = 0;
++
++ DWC_DEBUGPL(DBG_CILV, "%s\n", __func__);
++ /* Wait for AHB master IDLE state. */
++ do {
++ dwc_udelay(10);
++ greset.d32 = DWC_READ_REG32(&global_regs->grstctl);
++ if (++count > 100000) {
++ DWC_WARN("%s() HANG! AHB Idle GRSTCTL=%0x\n", __func__,
++ greset.d32);
++ return;
++ }
++ }
++ while (greset.b.ahbidle == 0);
++
++ /* Core Soft Reset */
++ count = 0;
++ greset.b.csftrst = 1;
++ DWC_WRITE_REG32(&global_regs->grstctl, greset.d32);
++ do {
++ greset.d32 = DWC_READ_REG32(&global_regs->grstctl);
++ if (++count > 10000) {
++ DWC_WARN("%s() HANG! Soft Reset GRSTCTL=%0x\n",
++ __func__, greset.d32);
++ break;
++ }
++ dwc_udelay(1);
++ }
++ while (greset.b.csftrst == 1);
++
++ /* Wait for 3 PHY Clocks */
++ dwc_mdelay(100);
++}
++
++uint8_t dwc_otg_is_device_mode(dwc_otg_core_if_t * _core_if)
++{
++ return (dwc_otg_mode(_core_if) != DWC_HOST_MODE);
++}
++
++uint8_t dwc_otg_is_host_mode(dwc_otg_core_if_t * _core_if)
++{
++ return (dwc_otg_mode(_core_if) == DWC_HOST_MODE);
++}
++
++/**
++ * Register HCD callbacks. The callbacks are used to start and stop
++ * the HCD for interrupt processing.
++ *
++ * @param core_if Programming view of DWC_otg controller.
++ * @param cb the HCD callback structure.
++ * @param p pointer to be passed to callback function (usb_hcd*).
++ */
++void dwc_otg_cil_register_hcd_callbacks(dwc_otg_core_if_t * core_if,
++ dwc_otg_cil_callbacks_t * cb, void *p)
++{
++ core_if->hcd_cb = cb;
++ cb->p = p;
++}
++
++/**
++ * Register PCD callbacks. The callbacks are used to start and stop
++ * the PCD for interrupt processing.
++ *
++ * @param core_if Programming view of DWC_otg controller.
++ * @param cb the PCD callback structure.
++ * @param p pointer to be passed to callback function (pcd*).
++ */
++void dwc_otg_cil_register_pcd_callbacks(dwc_otg_core_if_t * core_if,
++ dwc_otg_cil_callbacks_t * cb, void *p)
++{
++ core_if->pcd_cb = cb;
++ cb->p = p;
++}
++
++#ifdef DWC_EN_ISOC
++
++/**
++ * This function writes isoc data per 1 (micro)frame into tx fifo
++ *
++ * @param core_if Programming view of DWC_otg controller.
++ * @param ep The EP to start the transfer on.
++ *
++ */
++void write_isoc_frame_data(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
++{
++ dwc_otg_dev_in_ep_regs_t *ep_regs;
++ dtxfsts_data_t txstatus = {.d32 = 0 };
++ uint32_t len = 0;
++ uint32_t dwords;
++
++ ep->xfer_len = ep->data_per_frame;
++ ep->xfer_count = 0;
++
++ ep_regs = core_if->dev_if->in_ep_regs[ep->num];
++
++ len = ep->xfer_len - ep->xfer_count;
++
++ if (len > ep->maxpacket) {
++ len = ep->maxpacket;
++ }
++
++ dwords = (len + 3) / 4;
++
++ /* While there is space in the queue and space in the FIFO and
++ * More data to tranfer, Write packets to the Tx FIFO */
++ txstatus.d32 =
++ DWC_READ_REG32(&core_if->dev_if->in_ep_regs[ep->num]->dtxfsts);
++ DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", ep->num, txstatus.d32);
++
++ while (txstatus.b.txfspcavail > dwords &&
++ ep->xfer_count < ep->xfer_len && ep->xfer_len != 0) {
++ /* Write the FIFO */
++ dwc_otg_ep_write_packet(core_if, ep, 0);
++
++ len = ep->xfer_len - ep->xfer_count;
++ if (len > ep->maxpacket) {
++ len = ep->maxpacket;
++ }
++
++ dwords = (len + 3) / 4;
++ txstatus.d32 =
++ DWC_READ_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
++ dtxfsts);
++ DWC_DEBUGPL(DBG_PCDV, "dtxfsts[%d]=0x%08x\n", ep->num,
++ txstatus.d32);
++ }
++}
++
++/**
++ * This function initializes a descriptor chain for Isochronous transfer
++ *
++ * @param core_if Programming view of DWC_otg controller.
++ * @param ep The EP to start the transfer on.
++ *
++ */
++void dwc_otg_iso_ep_start_frm_transfer(dwc_otg_core_if_t * core_if,
++ dwc_ep_t * ep)
++{
++ deptsiz_data_t deptsiz = {.d32 = 0 };
++ depctl_data_t depctl = {.d32 = 0 };
++ dsts_data_t dsts = {.d32 = 0 };
++ volatile uint32_t *addr;
++
++ if (ep->is_in) {
++ addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
++ } else {
++ addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
++ }
++
++ ep->xfer_len = ep->data_per_frame;
++ ep->xfer_count = 0;
++ ep->xfer_buff = ep->cur_pkt_addr;
++ ep->dma_addr = ep->cur_pkt_dma_addr;
++
++ if (ep->is_in) {
++ /* Program the transfer size and packet count
++ * as follows: xfersize = N * maxpacket +
++ * short_packet pktcnt = N + (short_packet
++ * exist ? 1 : 0)
++ */
++ deptsiz.b.xfersize = ep->xfer_len;
++ deptsiz.b.pktcnt =
++ (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket;
++ deptsiz.b.mc = deptsiz.b.pktcnt;
++ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->dieptsiz,
++ deptsiz.d32);
++
++ /* Write the DMA register */
++ if (core_if->dma_enable) {
++ DWC_WRITE_REG32(&
++ (core_if->dev_if->in_ep_regs[ep->num]->
++ diepdma), (uint32_t) ep->dma_addr);
++ }
++ } else {
++ deptsiz.b.pktcnt =
++ (ep->xfer_len + (ep->maxpacket - 1)) / ep->maxpacket;
++ deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket;
++
++ DWC_WRITE_REG32(&core_if->dev_if->
++ out_ep_regs[ep->num]->doeptsiz, deptsiz.d32);
++
++ if (core_if->dma_enable) {
++ DWC_WRITE_REG32(&
++ (core_if->dev_if->
++ out_ep_regs[ep->num]->doepdma),
++ (uint32_t) ep->dma_addr);
++ }
++ }
++
++ /** Enable endpoint, clear nak */
++
++ depctl.d32 = 0;
++ if (ep->bInterval == 1) {
++ dsts.d32 =
++ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
++ ep->next_frame = dsts.b.soffn + ep->bInterval;
++
++ if (ep->next_frame & 0x1) {
++ depctl.b.setd1pid = 1;
++ } else {
++ depctl.b.setd0pid = 1;
++ }
++ } else {
++ ep->next_frame += ep->bInterval;
++
++ if (ep->next_frame & 0x1) {
++ depctl.b.setd1pid = 1;
++ } else {
++ depctl.b.setd0pid = 1;
++ }
++ }
++ depctl.b.epena = 1;
++ depctl.b.cnak = 1;
++
++ DWC_MODIFY_REG32(addr, 0, depctl.d32);
++ depctl.d32 = DWC_READ_REG32(addr);
++
++ if (ep->is_in && core_if->dma_enable == 0) {
++ write_isoc_frame_data(core_if, ep);
++ }
++
++}
++#endif /* DWC_EN_ISOC */
++
++static void dwc_otg_set_uninitialized(int32_t * p, int size)
++{
++ int i;
++ for (i = 0; i < size; i++) {
++ p[i] = -1;
++ }
++}
++
++static int dwc_otg_param_initialized(int32_t val)
++{
++ return val != -1;
++}
++
++static int dwc_otg_setup_params(dwc_otg_core_if_t * core_if)
++{
++ int i;
++ core_if->core_params = DWC_ALLOC(sizeof(*core_if->core_params));
++ if (!core_if->core_params) {
++ return -DWC_E_NO_MEMORY;
++ }
++ dwc_otg_set_uninitialized((int32_t *) core_if->core_params,
++ sizeof(*core_if->core_params) /
++ sizeof(int32_t));
++ DWC_PRINTF("Setting default values for core params\n");
++ dwc_otg_set_param_otg_cap(core_if, dwc_param_otg_cap_default);
++ dwc_otg_set_param_dma_enable(core_if, dwc_param_dma_enable_default);
++ dwc_otg_set_param_dma_desc_enable(core_if,
++ dwc_param_dma_desc_enable_default);
++ dwc_otg_set_param_opt(core_if, dwc_param_opt_default);
++ dwc_otg_set_param_dma_burst_size(core_if,
++ dwc_param_dma_burst_size_default);
++ dwc_otg_set_param_host_support_fs_ls_low_power(core_if,
++ dwc_param_host_support_fs_ls_low_power_default);
++ dwc_otg_set_param_enable_dynamic_fifo(core_if,
++ dwc_param_enable_dynamic_fifo_default);
++ dwc_otg_set_param_data_fifo_size(core_if,
++ dwc_param_data_fifo_size_default);
++ dwc_otg_set_param_dev_rx_fifo_size(core_if,
++ dwc_param_dev_rx_fifo_size_default);
++ dwc_otg_set_param_dev_nperio_tx_fifo_size(core_if,
++ dwc_param_dev_nperio_tx_fifo_size_default);
++ dwc_otg_set_param_host_rx_fifo_size(core_if,
++ dwc_param_host_rx_fifo_size_default);
++ dwc_otg_set_param_host_nperio_tx_fifo_size(core_if,
++ dwc_param_host_nperio_tx_fifo_size_default);
++ dwc_otg_set_param_host_perio_tx_fifo_size(core_if,
++ dwc_param_host_perio_tx_fifo_size_default);
++ dwc_otg_set_param_max_transfer_size(core_if,
++ dwc_param_max_transfer_size_default);
++ dwc_otg_set_param_max_packet_count(core_if,
++ dwc_param_max_packet_count_default);
++ dwc_otg_set_param_host_channels(core_if,
++ dwc_param_host_channels_default);
++ dwc_otg_set_param_dev_endpoints(core_if,
++ dwc_param_dev_endpoints_default);
++ dwc_otg_set_param_phy_type(core_if, dwc_param_phy_type_default);
++ dwc_otg_set_param_speed(core_if, dwc_param_speed_default);
++ dwc_otg_set_param_host_ls_low_power_phy_clk(core_if,
++ dwc_param_host_ls_low_power_phy_clk_default);
++ dwc_otg_set_param_phy_ulpi_ddr(core_if, dwc_param_phy_ulpi_ddr_default);
++ dwc_otg_set_param_phy_ulpi_ext_vbus(core_if,
++ dwc_param_phy_ulpi_ext_vbus_default);
++ dwc_otg_set_param_phy_utmi_width(core_if,
++ dwc_param_phy_utmi_width_default);
++ dwc_otg_set_param_ts_dline(core_if, dwc_param_ts_dline_default);
++ dwc_otg_set_param_i2c_enable(core_if, dwc_param_i2c_enable_default);
++ dwc_otg_set_param_ulpi_fs_ls(core_if, dwc_param_ulpi_fs_ls_default);
++ dwc_otg_set_param_en_multiple_tx_fifo(core_if,
++ dwc_param_en_multiple_tx_fifo_default);
++ for (i = 0; i < 15; i++) {
++ dwc_otg_set_param_dev_perio_tx_fifo_size(core_if,
++ dwc_param_dev_perio_tx_fifo_size_default,
++ i);
++ }
++
++ for (i = 0; i < 15; i++) {
++ dwc_otg_set_param_dev_tx_fifo_size(core_if,
++ dwc_param_dev_tx_fifo_size_default,
++ i);
++ }
++ dwc_otg_set_param_thr_ctl(core_if, dwc_param_thr_ctl_default);
++ dwc_otg_set_param_mpi_enable(core_if, dwc_param_mpi_enable_default);
++ dwc_otg_set_param_pti_enable(core_if, dwc_param_pti_enable_default);
++ dwc_otg_set_param_lpm_enable(core_if, dwc_param_lpm_enable_default);
++ dwc_otg_set_param_ic_usb_cap(core_if, dwc_param_ic_usb_cap_default);
++ dwc_otg_set_param_tx_thr_length(core_if,
++ dwc_param_tx_thr_length_default);
++ dwc_otg_set_param_rx_thr_length(core_if,
++ dwc_param_rx_thr_length_default);
++ dwc_otg_set_param_ahb_thr_ratio(core_if,
++ dwc_param_ahb_thr_ratio_default);
++ dwc_otg_set_param_power_down(core_if, dwc_param_power_down_default);
++ dwc_otg_set_param_reload_ctl(core_if, dwc_param_reload_ctl_default);
++ dwc_otg_set_param_dev_out_nak(core_if, dwc_param_dev_out_nak_default);
++ dwc_otg_set_param_cont_on_bna(core_if, dwc_param_cont_on_bna_default);
++ dwc_otg_set_param_ahb_single(core_if, dwc_param_ahb_single_default);
++ dwc_otg_set_param_otg_ver(core_if, dwc_param_otg_ver_default);
++ dwc_otg_set_param_adp_enable(core_if, dwc_param_adp_enable_default);
++ DWC_PRINTF("Finished setting default values for core params\n");
++
++ return 0;
++}
++
++uint8_t dwc_otg_is_dma_enable(dwc_otg_core_if_t * core_if)
++{
++ return core_if->dma_enable;
++}
++
++/* Checks if the parameter is outside of its valid range of values */
++#define DWC_OTG_PARAM_TEST(_param_, _low_, _high_) \
++ (((_param_) < (_low_)) || \
++ ((_param_) > (_high_)))
++
++/* Parameter access functions */
++int dwc_otg_set_param_otg_cap(dwc_otg_core_if_t * core_if, int32_t val)
++{
++ int valid;
++ int retval = 0;
++ if (DWC_OTG_PARAM_TEST(val, 0, 2)) {
++ DWC_WARN("Wrong value for otg_cap parameter\n");
++ DWC_WARN("otg_cap parameter must be 0,1 or 2\n");
++ retval = -DWC_E_INVALID;
++ goto out;
++ }
++
++ valid = 1;
++ switch (val) {
++ case DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE:
++ if (core_if->hwcfg2.b.op_mode !=
++ DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
++ valid = 0;
++ break;
++ case DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE:
++ if ((core_if->hwcfg2.b.op_mode !=
++ DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
++ && (core_if->hwcfg2.b.op_mode !=
++ DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG)
++ && (core_if->hwcfg2.b.op_mode !=
++ DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE)
++ && (core_if->hwcfg2.b.op_mode !=
++ DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) {
++ valid = 0;
++ }
++ break;
++ case DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE:
++ /* always valid */
++ break;
++ }
++ if (!valid) {
++ if (dwc_otg_param_initialized(core_if->core_params->otg_cap)) {
++ DWC_ERROR
++ ("%d invalid for otg_cap paremter. Check HW configuration.\n",
++ val);
++ }
++ val =
++ (((core_if->hwcfg2.b.op_mode ==
++ DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
++ || (core_if->hwcfg2.b.op_mode ==
++ DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG)
++ || (core_if->hwcfg2.b.op_mode ==
++ DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE)
++ || (core_if->hwcfg2.b.op_mode ==
++ DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) ?
++ DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE :
++ DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
++ retval = -DWC_E_INVALID;
++ }
++
++ core_if->core_params->otg_cap = val;
++out:
++ return retval;
++}
++
++int32_t dwc_otg_get_param_otg_cap(dwc_otg_core_if_t * core_if)
++{
++ return core_if->core_params->otg_cap;
++}
++
++int dwc_otg_set_param_opt(dwc_otg_core_if_t * core_if, int32_t val)
++{
++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
++ DWC_WARN("Wrong value for opt parameter\n");
++ return -DWC_E_INVALID;
++ }
++ core_if->core_params->opt = val;
++ return 0;
++}
++
++int32_t dwc_otg_get_param_opt(dwc_otg_core_if_t * core_if)
++{
++ return core_if->core_params->opt;
++}
++
++int dwc_otg_set_param_dma_enable(dwc_otg_core_if_t * core_if, int32_t val)
++{
++ int retval = 0;
++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
++ DWC_WARN("Wrong value for dma enable\n");
++ return -DWC_E_INVALID;
++ }
++
++ if ((val == 1) && (core_if->hwcfg2.b.architecture == 0)) {
++ if (dwc_otg_param_initialized(core_if->core_params->dma_enable)) {
++ DWC_ERROR
++ ("%d invalid for dma_enable paremter. Check HW configuration.\n",
++ val);
++ }
++ val = 0;
++ retval = -DWC_E_INVALID;
++ }
++
++ core_if->core_params->dma_enable = val;
++ if (val == 0) {
++ dwc_otg_set_param_dma_desc_enable(core_if, 0);
++ }
++ return retval;
++}
++
++int32_t dwc_otg_get_param_dma_enable(dwc_otg_core_if_t * core_if)
++{
++ return core_if->core_params->dma_enable;
++}
++
++int dwc_otg_set_param_dma_desc_enable(dwc_otg_core_if_t * core_if, int32_t val)
++{
++ int retval = 0;
++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
++ DWC_WARN("Wrong value for dma_enable\n");
++ DWC_WARN("dma_desc_enable must be 0 or 1\n");
++ return -DWC_E_INVALID;
++ }
++
++ if ((val == 1)
++ && ((dwc_otg_get_param_dma_enable(core_if) == 0)
++ || (core_if->hwcfg4.b.desc_dma == 0))) {
++ if (dwc_otg_param_initialized
++ (core_if->core_params->dma_desc_enable)) {
++ DWC_ERROR
++ ("%d invalid for dma_desc_enable paremter. Check HW configuration.\n",
++ val);
++ }
++ val = 0;
++ retval = -DWC_E_INVALID;
++ }
++ core_if->core_params->dma_desc_enable = val;
++ return retval;
++}
++
++int32_t dwc_otg_get_param_dma_desc_enable(dwc_otg_core_if_t * core_if)
++{
++ return core_if->core_params->dma_desc_enable;
++}
++
++int dwc_otg_set_param_host_support_fs_ls_low_power(dwc_otg_core_if_t * core_if,
++ int32_t val)
++{
++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
++ DWC_WARN("Wrong value for host_support_fs_low_power\n");
++ DWC_WARN("host_support_fs_low_power must be 0 or 1\n");
++ return -DWC_E_INVALID;
++ }
++ core_if->core_params->host_support_fs_ls_low_power = val;
++ return 0;
++}
++
++int32_t dwc_otg_get_param_host_support_fs_ls_low_power(dwc_otg_core_if_t *
++ core_if)
++{
++ return core_if->core_params->host_support_fs_ls_low_power;
++}
++
++int dwc_otg_set_param_enable_dynamic_fifo(dwc_otg_core_if_t * core_if,
++ int32_t val)
++{
++ int retval = 0;
++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
++ DWC_WARN("Wrong value for enable_dynamic_fifo\n");
++ DWC_WARN("enable_dynamic_fifo must be 0 or 1\n");
++ return -DWC_E_INVALID;
++ }
++
++ if ((val == 1) && (core_if->hwcfg2.b.dynamic_fifo == 0)) {
++ if (dwc_otg_param_initialized
++ (core_if->core_params->enable_dynamic_fifo)) {
++ DWC_ERROR
++ ("%d invalid for enable_dynamic_fifo paremter. Check HW configuration.\n",
++ val);
++ }
++ val = 0;
++ retval = -DWC_E_INVALID;
++ }
++ core_if->core_params->enable_dynamic_fifo = val;
++ return retval;
++}
++
++int32_t dwc_otg_get_param_enable_dynamic_fifo(dwc_otg_core_if_t * core_if)
++{
++ return core_if->core_params->enable_dynamic_fifo;
++}
++
++int dwc_otg_set_param_data_fifo_size(dwc_otg_core_if_t * core_if, int32_t val)
++{
++ int retval = 0;
++ if (DWC_OTG_PARAM_TEST(val, 32, 32768)) {
++ DWC_WARN("Wrong value for data_fifo_size\n");
++ DWC_WARN("data_fifo_size must be 32-32768\n");
++ return -DWC_E_INVALID;
++ }
++
++ if (val > core_if->hwcfg3.b.dfifo_depth) {
++ if (dwc_otg_param_initialized
++ (core_if->core_params->data_fifo_size)) {
++ DWC_ERROR
++ ("%d invalid for data_fifo_size parameter. Check HW configuration.\n",
++ val);
++ }
++ val = core_if->hwcfg3.b.dfifo_depth;
++ retval = -DWC_E_INVALID;
++ }
++
++ core_if->core_params->data_fifo_size = val;
++ return retval;
++}
++
++int32_t dwc_otg_get_param_data_fifo_size(dwc_otg_core_if_t * core_if)
++{
++ return core_if->core_params->data_fifo_size;
++}
++
++int dwc_otg_set_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if, int32_t val)
++{
++ int retval = 0;
++ if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
++ DWC_WARN("Wrong value for dev_rx_fifo_size\n");
++ DWC_WARN("dev_rx_fifo_size must be 16-32768\n");
++ return -DWC_E_INVALID;
++ }
++
++ if (val > DWC_READ_REG32(&core_if->core_global_regs->grxfsiz)) {
++ if (dwc_otg_param_initialized(core_if->core_params->dev_rx_fifo_size)) {
++ DWC_WARN("%d invalid for dev_rx_fifo_size parameter\n", val);
++ }
++ val = DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
++ retval = -DWC_E_INVALID;
++ }
++
++ core_if->core_params->dev_rx_fifo_size = val;
++ return retval;
++}
++
++int32_t dwc_otg_get_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if)
++{
++ return core_if->core_params->dev_rx_fifo_size;
++}
++
++int dwc_otg_set_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if,
++ int32_t val)
++{
++ int retval = 0;
++
++ if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
++ DWC_WARN("Wrong value for dev_nperio_tx_fifo\n");
++ DWC_WARN("dev_nperio_tx_fifo must be 16-32768\n");
++ return -DWC_E_INVALID;
++ }
++
++ if (val > (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >> 16)) {
++ if (dwc_otg_param_initialized
++ (core_if->core_params->dev_nperio_tx_fifo_size)) {
++ DWC_ERROR
++ ("%d invalid for dev_nperio_tx_fifo_size. Check HW configuration.\n",
++ val);
++ }
++ val =
++ (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >>
++ 16);
++ retval = -DWC_E_INVALID;
++ }
++
++ core_if->core_params->dev_nperio_tx_fifo_size = val;
++ return retval;
++}
++
++int32_t dwc_otg_get_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if)
++{
++ return core_if->core_params->dev_nperio_tx_fifo_size;
++}
++
++int dwc_otg_set_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if,
++ int32_t val)
++{
++ int retval = 0;
++
++ if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
++ DWC_WARN("Wrong value for host_rx_fifo_size\n");
++ DWC_WARN("host_rx_fifo_size must be 16-32768\n");
++ return -DWC_E_INVALID;
++ }
++
++ if (val > DWC_READ_REG32(&core_if->core_global_regs->grxfsiz)) {
++ if (dwc_otg_param_initialized
++ (core_if->core_params->host_rx_fifo_size)) {
++ DWC_ERROR
++ ("%d invalid for host_rx_fifo_size. Check HW configuration.\n",
++ val);
++ }
++ val = DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
++ retval = -DWC_E_INVALID;
++ }
++
++ core_if->core_params->host_rx_fifo_size = val;
++ return retval;
++
++}
++
++int32_t dwc_otg_get_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if)
++{
++ return core_if->core_params->host_rx_fifo_size;
++}
++
++int dwc_otg_set_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if,
++ int32_t val)
++{
++ int retval = 0;
++
++ if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
++ DWC_WARN("Wrong value for host_nperio_tx_fifo_size\n");
++ DWC_WARN("host_nperio_tx_fifo_size must be 16-32768\n");
++ return -DWC_E_INVALID;
++ }
++
++ if (val > (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >> 16)) {
++ if (dwc_otg_param_initialized
++ (core_if->core_params->host_nperio_tx_fifo_size)) {
++ DWC_ERROR
++ ("%d invalid for host_nperio_tx_fifo_size. Check HW configuration.\n",
++ val);
++ }
++ val =
++ (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >>
++ 16);
++ retval = -DWC_E_INVALID;
++ }
++
++ core_if->core_params->host_nperio_tx_fifo_size = val;
++ return retval;
++}
++
++int32_t dwc_otg_get_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if)
++{
++ return core_if->core_params->host_nperio_tx_fifo_size;
++}
++
++int dwc_otg_set_param_host_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,
++ int32_t val)
++{
++ int retval = 0;
++ if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
++ DWC_WARN("Wrong value for host_perio_tx_fifo_size\n");
++ DWC_WARN("host_perio_tx_fifo_size must be 16-32768\n");
++ return -DWC_E_INVALID;
++ }
++
++ if (val > ((core_if->hptxfsiz.d32) >> 16)) {
++ if (dwc_otg_param_initialized
++ (core_if->core_params->host_perio_tx_fifo_size)) {
++ DWC_ERROR
++ ("%d invalid for host_perio_tx_fifo_size. Check HW configuration.\n",
++ val);
++ }
++ val = (core_if->hptxfsiz.d32) >> 16;
++ retval = -DWC_E_INVALID;
++ }
++
++ core_if->core_params->host_perio_tx_fifo_size = val;
++ return retval;
++}
++
++int32_t dwc_otg_get_param_host_perio_tx_fifo_size(dwc_otg_core_if_t * core_if)
++{
++ return core_if->core_params->host_perio_tx_fifo_size;
++}
++
++int dwc_otg_set_param_max_transfer_size(dwc_otg_core_if_t * core_if,
++ int32_t val)
++{
++ int retval = 0;
++
++ if (DWC_OTG_PARAM_TEST(val, 2047, 524288)) {
++ DWC_WARN("Wrong value for max_transfer_size\n");
++ DWC_WARN("max_transfer_size must be 2047-524288\n");
++ return -DWC_E_INVALID;
++ }
++
++ if (val >= (1 << (core_if->hwcfg3.b.xfer_size_cntr_width + 11))) {
++ if (dwc_otg_param_initialized
++ (core_if->core_params->max_transfer_size)) {
++ DWC_ERROR
++ ("%d invalid for max_transfer_size. Check HW configuration.\n",
++ val);
++ }
++ val =
++ ((1 << (core_if->hwcfg3.b.packet_size_cntr_width + 11)) -
++ 1);
++ retval = -DWC_E_INVALID;
++ }
++
++ core_if->core_params->max_transfer_size = val;
++ return retval;
++}
++
++int32_t dwc_otg_get_param_max_transfer_size(dwc_otg_core_if_t * core_if)
++{
++ return core_if->core_params->max_transfer_size;
++}
++
++int dwc_otg_set_param_max_packet_count(dwc_otg_core_if_t * core_if, int32_t val)
++{
++ int retval = 0;
++
++ if (DWC_OTG_PARAM_TEST(val, 15, 511)) {
++ DWC_WARN("Wrong value for max_packet_count\n");
++ DWC_WARN("max_packet_count must be 15-511\n");
++ return -DWC_E_INVALID;
++ }
++
++ if (val > (1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4))) {
++ if (dwc_otg_param_initialized
++ (core_if->core_params->max_packet_count)) {
++ DWC_ERROR
++ ("%d invalid for max_packet_count. Check HW configuration.\n",
++ val);
++ }
++ val =
++ ((1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4)) - 1);
++ retval = -DWC_E_INVALID;
++ }
++
++ core_if->core_params->max_packet_count = val;
++ return retval;
++}
++
++int32_t dwc_otg_get_param_max_packet_count(dwc_otg_core_if_t * core_if)
++{
++ return core_if->core_params->max_packet_count;
++}
++
++int dwc_otg_set_param_host_channels(dwc_otg_core_if_t * core_if, int32_t val)
++{
++ int retval = 0;
++
++ if (DWC_OTG_PARAM_TEST(val, 1, 16)) {
++ DWC_WARN("Wrong value for host_channels\n");
++ DWC_WARN("host_channels must be 1-16\n");
++ return -DWC_E_INVALID;
++ }
++
++ if (val > (core_if->hwcfg2.b.num_host_chan + 1)) {
++ if (dwc_otg_param_initialized
++ (core_if->core_params->host_channels)) {
++ DWC_ERROR
++ ("%d invalid for host_channels. Check HW configurations.\n",
++ val);
++ }
++ val = (core_if->hwcfg2.b.num_host_chan + 1);
++ retval = -DWC_E_INVALID;
++ }
++
++ core_if->core_params->host_channels = val;
++ return retval;
++}
++
++int32_t dwc_otg_get_param_host_channels(dwc_otg_core_if_t * core_if)
++{
++ return core_if->core_params->host_channels;
++}
++
++int dwc_otg_set_param_dev_endpoints(dwc_otg_core_if_t * core_if, int32_t val)
++{
++ int retval = 0;
++
++ if (DWC_OTG_PARAM_TEST(val, 1, 15)) {
++ DWC_WARN("Wrong value for dev_endpoints\n");
++ DWC_WARN("dev_endpoints must be 1-15\n");
++ return -DWC_E_INVALID;
++ }
++
++ if (val > (core_if->hwcfg2.b.num_dev_ep)) {
++ if (dwc_otg_param_initialized
++ (core_if->core_params->dev_endpoints)) {
++ DWC_ERROR
++ ("%d invalid for dev_endpoints. Check HW configurations.\n",
++ val);
++ }
++ val = core_if->hwcfg2.b.num_dev_ep;
++ retval = -DWC_E_INVALID;
++ }
++
++ core_if->core_params->dev_endpoints = val;
++ return retval;
++}
++
++int32_t dwc_otg_get_param_dev_endpoints(dwc_otg_core_if_t * core_if)
++{
++ return core_if->core_params->dev_endpoints;
++}
++
++int dwc_otg_set_param_phy_type(dwc_otg_core_if_t * core_if, int32_t val)
++{
++ int retval = 0;
++ int valid = 0;
++
++ if (DWC_OTG_PARAM_TEST(val, 0, 2)) {
++ DWC_WARN("Wrong value for phy_type\n");
++ DWC_WARN("phy_type must be 0,1 or 2\n");
++ return -DWC_E_INVALID;
++ }
++#ifndef NO_FS_PHY_HW_CHECKS
++ if ((val == DWC_PHY_TYPE_PARAM_UTMI) &&
++ ((core_if->hwcfg2.b.hs_phy_type == 1) ||
++ (core_if->hwcfg2.b.hs_phy_type == 3))) {
++ valid = 1;
++ } else if ((val == DWC_PHY_TYPE_PARAM_ULPI) &&
++ ((core_if->hwcfg2.b.hs_phy_type == 2) ||
++ (core_if->hwcfg2.b.hs_phy_type == 3))) {
++ valid = 1;
++ } else if ((val == DWC_PHY_TYPE_PARAM_FS) &&
++ (core_if->hwcfg2.b.fs_phy_type == 1)) {
++ valid = 1;
++ }
++ if (!valid) {
++ if (dwc_otg_param_initialized(core_if->core_params->phy_type)) {
++ DWC_ERROR
++ ("%d invalid for phy_type. Check HW configurations.\n",
++ val);
++ }
++ if (core_if->hwcfg2.b.hs_phy_type) {
++ if ((core_if->hwcfg2.b.hs_phy_type == 3) ||
++ (core_if->hwcfg2.b.hs_phy_type == 1)) {
++ val = DWC_PHY_TYPE_PARAM_UTMI;
++ } else {
++ val = DWC_PHY_TYPE_PARAM_ULPI;
++ }
++ }
++ retval = -DWC_E_INVALID;
++ }
++#endif
++ core_if->core_params->phy_type = val;
++ return retval;
++}
++
++int32_t dwc_otg_get_param_phy_type(dwc_otg_core_if_t * core_if)
++{
++ return core_if->core_params->phy_type;
++}
++
++int dwc_otg_set_param_speed(dwc_otg_core_if_t * core_if, int32_t val)
++{
++ int retval = 0;
++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
++ DWC_WARN("Wrong value for speed parameter\n");
++ DWC_WARN("max_speed parameter must be 0 or 1\n");
++ return -DWC_E_INVALID;
++ }
++ if ((val == 0)
++ && dwc_otg_get_param_phy_type(core_if) == DWC_PHY_TYPE_PARAM_FS) {
++ if (dwc_otg_param_initialized(core_if->core_params->speed)) {
++ DWC_ERROR
++ ("%d invalid for speed paremter. Check HW configuration.\n",
++ val);
++ }
++ val =
++ (dwc_otg_get_param_phy_type(core_if) ==
++ DWC_PHY_TYPE_PARAM_FS ? 1 : 0);
++ retval = -DWC_E_INVALID;
++ }
++ core_if->core_params->speed = val;
++ return retval;
++}
++
++int32_t dwc_otg_get_param_speed(dwc_otg_core_if_t * core_if)
++{
++ return core_if->core_params->speed;
++}
++
++int dwc_otg_set_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t * core_if,
++ int32_t val)
++{
++ int retval = 0;
++
++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
++ DWC_WARN
++ ("Wrong value for host_ls_low_power_phy_clk parameter\n");
++ DWC_WARN("host_ls_low_power_phy_clk must be 0 or 1\n");
++ return -DWC_E_INVALID;
++ }
++
++ if ((val == DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ)
++ && (dwc_otg_get_param_phy_type(core_if) == DWC_PHY_TYPE_PARAM_FS)) {
++ if (dwc_otg_param_initialized
++ (core_if->core_params->host_ls_low_power_phy_clk)) {
++ DWC_ERROR
++ ("%d invalid for host_ls_low_power_phy_clk. Check HW configuration.\n",
++ val);
++ }
++ val =
++ (dwc_otg_get_param_phy_type(core_if) ==
++ DWC_PHY_TYPE_PARAM_FS) ?
++ DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ :
++ DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ;
++ retval = -DWC_E_INVALID;
++ }
++
++ core_if->core_params->host_ls_low_power_phy_clk = val;
++ return retval;
++}
++
++int32_t dwc_otg_get_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t * core_if)
++{
++ return core_if->core_params->host_ls_low_power_phy_clk;
++}
++
++int dwc_otg_set_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if, int32_t val)
++{
++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
++ DWC_WARN("Wrong value for phy_ulpi_ddr\n");
++ DWC_WARN("phy_upli_ddr must be 0 or 1\n");
++ return -DWC_E_INVALID;
++ }
++
++ core_if->core_params->phy_ulpi_ddr = val;
++ return 0;
++}
++
++int32_t dwc_otg_get_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if)
++{
++ return core_if->core_params->phy_ulpi_ddr;
++}
++
++int dwc_otg_set_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if,
++ int32_t val)
++{
++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
++ DWC_WARN("Wrong valaue for phy_ulpi_ext_vbus\n");
++ DWC_WARN("phy_ulpi_ext_vbus must be 0 or 1\n");
++ return -DWC_E_INVALID;
++ }
++
++ core_if->core_params->phy_ulpi_ext_vbus = val;
++ return 0;
++}
++
++int32_t dwc_otg_get_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if)
++{
++ return core_if->core_params->phy_ulpi_ext_vbus;
++}
++
++int dwc_otg_set_param_phy_utmi_width(dwc_otg_core_if_t * core_if, int32_t val)
++{
++ if (DWC_OTG_PARAM_TEST(val, 8, 8) && DWC_OTG_PARAM_TEST(val, 16, 16)) {
++ DWC_WARN("Wrong valaue for phy_utmi_width\n");
++ DWC_WARN("phy_utmi_width must be 8 or 16\n");
++ return -DWC_E_INVALID;
++ }
++
++ core_if->core_params->phy_utmi_width = val;
++ return 0;
++}
++
++int32_t dwc_otg_get_param_phy_utmi_width(dwc_otg_core_if_t * core_if)
++{
++ return core_if->core_params->phy_utmi_width;
++}
++
++int dwc_otg_set_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if, int32_t val)
++{
++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
++ DWC_WARN("Wrong valaue for ulpi_fs_ls\n");
++ DWC_WARN("ulpi_fs_ls must be 0 or 1\n");
++ return -DWC_E_INVALID;
++ }
++
++ core_if->core_params->ulpi_fs_ls = val;
++ return 0;
++}
++
++int32_t dwc_otg_get_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if)
++{
++ return core_if->core_params->ulpi_fs_ls;
++}
++
++int dwc_otg_set_param_ts_dline(dwc_otg_core_if_t * core_if, int32_t val)
++{
++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
++ DWC_WARN("Wrong valaue for ts_dline\n");
++ DWC_WARN("ts_dline must be 0 or 1\n");
++ return -DWC_E_INVALID;
++ }
++
++ core_if->core_params->ts_dline = val;
++ return 0;
++}
++
++int32_t dwc_otg_get_param_ts_dline(dwc_otg_core_if_t * core_if)
++{
++ return core_if->core_params->ts_dline;
++}
++
++int dwc_otg_set_param_i2c_enable(dwc_otg_core_if_t * core_if, int32_t val)
++{
++ int retval = 0;
++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
++ DWC_WARN("Wrong valaue for i2c_enable\n");
++ DWC_WARN("i2c_enable must be 0 or 1\n");
++ return -DWC_E_INVALID;
++ }
++#ifndef NO_FS_PHY_HW_CHECK
++ if (val == 1 && core_if->hwcfg3.b.i2c == 0) {
++ if (dwc_otg_param_initialized(core_if->core_params->i2c_enable)) {
++ DWC_ERROR
++ ("%d invalid for i2c_enable. Check HW configuration.\n",
++ val);
++ }
++ val = 0;
++ retval = -DWC_E_INVALID;
++ }
++#endif
++
++ core_if->core_params->i2c_enable = val;
++ return retval;
++}
++
++int32_t dwc_otg_get_param_i2c_enable(dwc_otg_core_if_t * core_if)
++{
++ return core_if->core_params->i2c_enable;
++}
++
++int dwc_otg_set_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,
++ int32_t val, int fifo_num)
++{
++ int retval = 0;
++
++ if (DWC_OTG_PARAM_TEST(val, 4, 768)) {
++ DWC_WARN("Wrong value for dev_perio_tx_fifo_size\n");
++ DWC_WARN("dev_perio_tx_fifo_size must be 4-768\n");
++ return -DWC_E_INVALID;
++ }
++
++ if (val >
++ (DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num]))) {
++ if (dwc_otg_param_initialized
++ (core_if->core_params->dev_perio_tx_fifo_size[fifo_num])) {
++ DWC_ERROR
++ ("`%d' invalid for parameter `dev_perio_fifo_size_%d'. Check HW configuration.\n",
++ val, fifo_num);
++ }
++ val = (DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num]));
++ retval = -DWC_E_INVALID;
++ }
++
++ core_if->core_params->dev_perio_tx_fifo_size[fifo_num] = val;
++ return retval;
++}
++
++int32_t dwc_otg_get_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,
++ int fifo_num)
++{
++ return core_if->core_params->dev_perio_tx_fifo_size[fifo_num];
++}
++
++int dwc_otg_set_param_en_multiple_tx_fifo(dwc_otg_core_if_t * core_if,
++ int32_t val)
++{
++ int retval = 0;
++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
++ DWC_WARN("Wrong valaue for en_multiple_tx_fifo,\n");
++ DWC_WARN("en_multiple_tx_fifo must be 0 or 1\n");
++ return -DWC_E_INVALID;
++ }
++
++ if (val == 1 && core_if->hwcfg4.b.ded_fifo_en == 0) {
++ if (dwc_otg_param_initialized
++ (core_if->core_params->en_multiple_tx_fifo)) {
++ DWC_ERROR
++ ("%d invalid for parameter en_multiple_tx_fifo. Check HW configuration.\n",
++ val);
++ }
++ val = 0;
++ retval = -DWC_E_INVALID;
++ }
++
++ core_if->core_params->en_multiple_tx_fifo = val;
++ return retval;
++}
++
++int32_t dwc_otg_get_param_en_multiple_tx_fifo(dwc_otg_core_if_t * core_if)
++{
++ return core_if->core_params->en_multiple_tx_fifo;
++}
++
++int dwc_otg_set_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if, int32_t val,
++ int fifo_num)
++{
++ int retval = 0;
++
++ if (DWC_OTG_PARAM_TEST(val, 4, 768)) {
++ DWC_WARN("Wrong value for dev_tx_fifo_size\n");
++ DWC_WARN("dev_tx_fifo_size must be 4-768\n");
++ return -DWC_E_INVALID;
++ }
++
++ if (val >
++ (DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num]))) {
++ if (dwc_otg_param_initialized
++ (core_if->core_params->dev_tx_fifo_size[fifo_num])) {
++ DWC_ERROR
++ ("`%d' invalid for parameter `dev_tx_fifo_size_%d'. Check HW configuration.\n",
++ val, fifo_num);
++ }
++ val = (DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num]));
++ retval = -DWC_E_INVALID;
++ }
++
++ core_if->core_params->dev_tx_fifo_size[fifo_num] = val;
++ return retval;
++}
++
++int32_t dwc_otg_get_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if,
++ int fifo_num)
++{
++ return core_if->core_params->dev_tx_fifo_size[fifo_num];
++}
++
++int dwc_otg_set_param_thr_ctl(dwc_otg_core_if_t * core_if, int32_t val)
++{
++ int retval = 0;
++
++ if (DWC_OTG_PARAM_TEST(val, 0, 7)) {
++ DWC_WARN("Wrong value for thr_ctl\n");
++ DWC_WARN("thr_ctl must be 0-7\n");
++ return -DWC_E_INVALID;
++ }
++
++ if ((val != 0) &&
++ (!dwc_otg_get_param_dma_enable(core_if) ||
++ !core_if->hwcfg4.b.ded_fifo_en)) {
++ if (dwc_otg_param_initialized(core_if->core_params->thr_ctl)) {
++ DWC_ERROR
++ ("%d invalid for parameter thr_ctl. Check HW configuration.\n",
++ val);
++ }
++ val = 0;
++ retval = -DWC_E_INVALID;
++ }
++
++ core_if->core_params->thr_ctl = val;
++ return retval;
++}
++
++int32_t dwc_otg_get_param_thr_ctl(dwc_otg_core_if_t * core_if)
++{
++ return core_if->core_params->thr_ctl;
++}
++
++int dwc_otg_set_param_lpm_enable(dwc_otg_core_if_t * core_if, int32_t val)
++{
++ int retval = 0;
++
++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
++ DWC_WARN("Wrong value for lpm_enable\n");
++ DWC_WARN("lpm_enable must be 0 or 1\n");
++ return -DWC_E_INVALID;
++ }
++
++ if (val && !core_if->hwcfg3.b.otg_lpm_en) {
++ if (dwc_otg_param_initialized(core_if->core_params->lpm_enable)) {
++ DWC_ERROR
++ ("%d invalid for parameter lpm_enable. Check HW configuration.\n",
++ val);
++ }
++ val = 0;
++ retval = -DWC_E_INVALID;
++ }
++
++ core_if->core_params->lpm_enable = val;
++ return retval;
++}
++
++int32_t dwc_otg_get_param_lpm_enable(dwc_otg_core_if_t * core_if)
++{
++ return core_if->core_params->lpm_enable;
++}
++
++int dwc_otg_set_param_tx_thr_length(dwc_otg_core_if_t * core_if, int32_t val)
++{
++ if (DWC_OTG_PARAM_TEST(val, 8, 128)) {
++ DWC_WARN("Wrong valaue for tx_thr_length\n");
++ DWC_WARN("tx_thr_length must be 8 - 128\n");
++ return -DWC_E_INVALID;
++ }
++
++ core_if->core_params->tx_thr_length = val;
++ return 0;
++}
++
++int32_t dwc_otg_get_param_tx_thr_length(dwc_otg_core_if_t * core_if)
++{
++ return core_if->core_params->tx_thr_length;
++}
++
++int dwc_otg_set_param_rx_thr_length(dwc_otg_core_if_t * core_if, int32_t val)
++{
++ if (DWC_OTG_PARAM_TEST(val, 8, 128)) {
++ DWC_WARN("Wrong valaue for rx_thr_length\n");
++ DWC_WARN("rx_thr_length must be 8 - 128\n");
++ return -DWC_E_INVALID;
++ }
++
++ core_if->core_params->rx_thr_length = val;
++ return 0;
++}
++
++int32_t dwc_otg_get_param_rx_thr_length(dwc_otg_core_if_t * core_if)
++{
++ return core_if->core_params->rx_thr_length;
++}
++
++int dwc_otg_set_param_dma_burst_size(dwc_otg_core_if_t * core_if, int32_t val)
++{
++ if (DWC_OTG_PARAM_TEST(val, 1, 1) &&
++ DWC_OTG_PARAM_TEST(val, 4, 4) &&
++ DWC_OTG_PARAM_TEST(val, 8, 8) &&
++ DWC_OTG_PARAM_TEST(val, 16, 16) &&
++ DWC_OTG_PARAM_TEST(val, 32, 32) &&
++ DWC_OTG_PARAM_TEST(val, 64, 64) &&
++ DWC_OTG_PARAM_TEST(val, 128, 128) &&
++ DWC_OTG_PARAM_TEST(val, 256, 256)) {
++ DWC_WARN("`%d' invalid for parameter `dma_burst_size'\n", val);
++ return -DWC_E_INVALID;
++ }
++ core_if->core_params->dma_burst_size = val;
++ return 0;
++}
++
++int32_t dwc_otg_get_param_dma_burst_size(dwc_otg_core_if_t * core_if)
++{
++ return core_if->core_params->dma_burst_size;
++}
++
++int dwc_otg_set_param_pti_enable(dwc_otg_core_if_t * core_if, int32_t val)
++{
++ int retval = 0;
++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
++ DWC_WARN("`%d' invalid for parameter `pti_enable'\n", val);
++ return -DWC_E_INVALID;
++ }
++ if (val && (core_if->snpsid < OTG_CORE_REV_2_72a)) {
++ if (dwc_otg_param_initialized(core_if->core_params->pti_enable)) {
++ DWC_ERROR
++ ("%d invalid for parameter pti_enable. Check HW configuration.\n",
++ val);
++ }
++ retval = -DWC_E_INVALID;
++ val = 0;
++ }
++ core_if->core_params->pti_enable = val;
++ return retval;
++}
++
++int32_t dwc_otg_get_param_pti_enable(dwc_otg_core_if_t * core_if)
++{
++ return core_if->core_params->pti_enable;
++}
++
++int dwc_otg_set_param_mpi_enable(dwc_otg_core_if_t * core_if, int32_t val)
++{
++ int retval = 0;
++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
++ DWC_WARN("`%d' invalid for parameter `mpi_enable'\n", val);
++ return -DWC_E_INVALID;
++ }
++ if (val && (core_if->hwcfg2.b.multi_proc_int == 0)) {
++ if (dwc_otg_param_initialized(core_if->core_params->mpi_enable)) {
++ DWC_ERROR
++ ("%d invalid for parameter mpi_enable. Check HW configuration.\n",
++ val);
++ }
++ retval = -DWC_E_INVALID;
++ val = 0;
++ }
++ core_if->core_params->mpi_enable = val;
++ return retval;
++}
++
++int32_t dwc_otg_get_param_mpi_enable(dwc_otg_core_if_t * core_if)
++{
++ return core_if->core_params->mpi_enable;
++}
++
++int dwc_otg_set_param_adp_enable(dwc_otg_core_if_t * core_if, int32_t val)
++{
++ int retval = 0;
++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
++ DWC_WARN("`%d' invalid for parameter `adp_enable'\n", val);
++ return -DWC_E_INVALID;
++ }
++ if (val && (core_if->hwcfg3.b.adp_supp == 0)) {
++ if (dwc_otg_param_initialized
++ (core_if->core_params->adp_supp_enable)) {
++ DWC_ERROR
++ ("%d invalid for parameter adp_enable. Check HW configuration.\n",
++ val);
++ }
++ retval = -DWC_E_INVALID;
++ val = 0;
++ }
++ core_if->core_params->adp_supp_enable = val;
++ /*Set OTG version 2.0 in case of enabling ADP*/
++ if (val)
++ dwc_otg_set_param_otg_ver(core_if, 1);
++
++ return retval;
++}
++
++int32_t dwc_otg_get_param_adp_enable(dwc_otg_core_if_t * core_if)
++{
++ return core_if->core_params->adp_supp_enable;
++}
++
++int dwc_otg_set_param_ic_usb_cap(dwc_otg_core_if_t * core_if, int32_t val)
++{
++ int retval = 0;
++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
++ DWC_WARN("`%d' invalid for parameter `ic_usb_cap'\n", val);
++ DWC_WARN("ic_usb_cap must be 0 or 1\n");
++ return -DWC_E_INVALID;
++ }
++
++ if (val && (core_if->hwcfg2.b.otg_enable_ic_usb == 0)) {
++ if (dwc_otg_param_initialized(core_if->core_params->ic_usb_cap)) {
++ DWC_ERROR
++ ("%d invalid for parameter ic_usb_cap. Check HW configuration.\n",
++ val);
++ }
++ retval = -DWC_E_INVALID;
++ val = 0;
++ }
++ core_if->core_params->ic_usb_cap = val;
++ return retval;
++}
++
++int32_t dwc_otg_get_param_ic_usb_cap(dwc_otg_core_if_t * core_if)
++{
++ return core_if->core_params->ic_usb_cap;
++}
++
++int dwc_otg_set_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if, int32_t val)
++{
++ int retval = 0;
++ int valid = 1;
++
++ if (DWC_OTG_PARAM_TEST(val, 0, 3)) {
++ DWC_WARN("`%d' invalid for parameter `ahb_thr_ratio'\n", val);
++ DWC_WARN("ahb_thr_ratio must be 0 - 3\n");
++ return -DWC_E_INVALID;
++ }
++
++ if (val
++ && (core_if->snpsid < OTG_CORE_REV_2_81a
++ || !dwc_otg_get_param_thr_ctl(core_if))) {
++ valid = 0;
++ } else if (val
++ && ((dwc_otg_get_param_tx_thr_length(core_if) / (1 << val)) <
++ 4)) {
++ valid = 0;
++ }
++ if (valid == 0) {
++ if (dwc_otg_param_initialized
++ (core_if->core_params->ahb_thr_ratio)) {
++ DWC_ERROR
++ ("%d invalid for parameter ahb_thr_ratio. Check HW configuration.\n",
++ val);
++ }
++ retval = -DWC_E_INVALID;
++ val = 0;
++ }
++
++ core_if->core_params->ahb_thr_ratio = val;
++ return retval;
++}
++
++int32_t dwc_otg_get_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if)
++{
++ return core_if->core_params->ahb_thr_ratio;
++}
++
++int dwc_otg_set_param_power_down(dwc_otg_core_if_t * core_if, int32_t val)
++{
++ int retval = 0;
++ int valid = 1;
++ hwcfg4_data_t hwcfg4 = {.d32 = 0 };
++ hwcfg4.d32 = DWC_READ_REG32(&core_if->core_global_regs->ghwcfg4);
++
++ if (DWC_OTG_PARAM_TEST(val, 0, 3)) {
++ DWC_WARN("`%d' invalid for parameter `power_down'\n", val);
++ DWC_WARN("power_down must be 0 - 2\n");
++ return -DWC_E_INVALID;
++ }
++
++ if ((val == 2) && (core_if->snpsid < OTG_CORE_REV_2_91a)) {
++ valid = 0;
++ }
++ if ((val == 3)
++ && ((core_if->snpsid < OTG_CORE_REV_3_00a)
++ || (hwcfg4.b.xhiber == 0))) {
++ valid = 0;
++ }
++ if (valid == 0) {
++ if (dwc_otg_param_initialized(core_if->core_params->power_down)) {
++ DWC_ERROR
++ ("%d invalid for parameter power_down. Check HW configuration.\n",
++ val);
++ }
++ retval = -DWC_E_INVALID;
++ val = 0;
++ }
++ core_if->core_params->power_down = val;
++ return retval;
++}
++
++int32_t dwc_otg_get_param_power_down(dwc_otg_core_if_t * core_if)
++{
++ return core_if->core_params->power_down;
++}
++
++int dwc_otg_set_param_reload_ctl(dwc_otg_core_if_t * core_if, int32_t val)
++{
++ int retval = 0;
++ int valid = 1;
++
++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
++ DWC_WARN("`%d' invalid for parameter `reload_ctl'\n", val);
++ DWC_WARN("reload_ctl must be 0 or 1\n");
++ return -DWC_E_INVALID;
++ }
++
++ if ((val == 1) && (core_if->snpsid < OTG_CORE_REV_2_92a)) {
++ valid = 0;
++ }
++ if (valid == 0) {
++ if (dwc_otg_param_initialized(core_if->core_params->reload_ctl)) {
++ DWC_ERROR("%d invalid for parameter reload_ctl."
++ "Check HW configuration.\n", val);
++ }
++ retval = -DWC_E_INVALID;
++ val = 0;
++ }
++ core_if->core_params->reload_ctl = val;
++ return retval;
++}
++
++int32_t dwc_otg_get_param_reload_ctl(dwc_otg_core_if_t * core_if)
++{
++ return core_if->core_params->reload_ctl;
++}
++
++int dwc_otg_set_param_dev_out_nak(dwc_otg_core_if_t * core_if, int32_t val)
++{
++ int retval = 0;
++ int valid = 1;
++
++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
++ DWC_WARN("`%d' invalid for parameter `dev_out_nak'\n", val);
++ DWC_WARN("dev_out_nak must be 0 or 1\n");
++ return -DWC_E_INVALID;
++ }
++
++ if ((val == 1) && ((core_if->snpsid < OTG_CORE_REV_2_93a) ||
++ !(core_if->core_params->dma_desc_enable))) {
++ valid = 0;
++ }
++ if (valid == 0) {
++ if (dwc_otg_param_initialized(core_if->core_params->dev_out_nak)) {
++ DWC_ERROR("%d invalid for parameter dev_out_nak."
++ "Check HW configuration.\n", val);
++ }
++ retval = -DWC_E_INVALID;
++ val = 0;
++ }
++ core_if->core_params->dev_out_nak = val;
++ return retval;
++}
++
++int32_t dwc_otg_get_param_dev_out_nak(dwc_otg_core_if_t * core_if)
++{
++ return core_if->core_params->dev_out_nak;
++}
++
++int dwc_otg_set_param_cont_on_bna(dwc_otg_core_if_t * core_if, int32_t val)
++{
++ int retval = 0;
++ int valid = 1;
++
++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
++ DWC_WARN("`%d' invalid for parameter `cont_on_bna'\n", val);
++ DWC_WARN("cont_on_bna must be 0 or 1\n");
++ return -DWC_E_INVALID;
++ }
++
++ if ((val == 1) && ((core_if->snpsid < OTG_CORE_REV_2_94a) ||
++ !(core_if->core_params->dma_desc_enable))) {
++ valid = 0;
++ }
++ if (valid == 0) {
++ if (dwc_otg_param_initialized(core_if->core_params->cont_on_bna)) {
++ DWC_ERROR("%d invalid for parameter cont_on_bna."
++ "Check HW configuration.\n", val);
++ }
++ retval = -DWC_E_INVALID;
++ val = 0;
++ }
++ core_if->core_params->cont_on_bna = val;
++ return retval;
++}
++
++int32_t dwc_otg_get_param_cont_on_bna(dwc_otg_core_if_t * core_if)
++{
++ return core_if->core_params->cont_on_bna;
++}
++
++int dwc_otg_set_param_ahb_single(dwc_otg_core_if_t * core_if, int32_t val)
++{
++ int retval = 0;
++ int valid = 1;
++
++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
++ DWC_WARN("`%d' invalid for parameter `ahb_single'\n", val);
++ DWC_WARN("ahb_single must be 0 or 1\n");
++ return -DWC_E_INVALID;
++ }
++
++ if ((val == 1) && (core_if->snpsid < OTG_CORE_REV_2_94a)) {
++ valid = 0;
++ }
++ if (valid == 0) {
++ if (dwc_otg_param_initialized(core_if->core_params->ahb_single)) {
++ DWC_ERROR("%d invalid for parameter ahb_single."
++ "Check HW configuration.\n", val);
++ }
++ retval = -DWC_E_INVALID;
++ val = 0;
++ }
++ core_if->core_params->ahb_single = val;
++ return retval;
++}
++
++int32_t dwc_otg_get_param_ahb_single(dwc_otg_core_if_t * core_if)
++{
++ return core_if->core_params->ahb_single;
++}
++
++int dwc_otg_set_param_otg_ver(dwc_otg_core_if_t * core_if, int32_t val)
++{
++ int retval = 0;
++
++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
++ DWC_WARN("`%d' invalid for parameter `otg_ver'\n", val);
++ DWC_WARN
++ ("otg_ver must be 0(for OTG 1.3 support) or 1(for OTG 2.0 support)\n");
++ return -DWC_E_INVALID;
++ }
++
++ core_if->core_params->otg_ver = val;
++ return retval;
++}
++
++int32_t dwc_otg_get_param_otg_ver(dwc_otg_core_if_t * core_if)
++{
++ return core_if->core_params->otg_ver;
++}
++
++uint32_t dwc_otg_get_hnpstatus(dwc_otg_core_if_t * core_if)
++{
++ gotgctl_data_t otgctl;
++ otgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
++ return otgctl.b.hstnegscs;
++}
++
++uint32_t dwc_otg_get_srpstatus(dwc_otg_core_if_t * core_if)
++{
++ gotgctl_data_t otgctl;
++ otgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
++ return otgctl.b.sesreqscs;
++}
++
++void dwc_otg_set_hnpreq(dwc_otg_core_if_t * core_if, uint32_t val)
++{
++ if(core_if->otg_ver == 0) {
++ gotgctl_data_t otgctl;
++ otgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
++ otgctl.b.hnpreq = val;
++ DWC_WRITE_REG32(&core_if->core_global_regs->gotgctl, otgctl.d32);
++ } else {
++ core_if->otg_sts = val;
++ }
++}
++
++uint32_t dwc_otg_get_gsnpsid(dwc_otg_core_if_t * core_if)
++{
++ return core_if->snpsid;
++}
++
++uint32_t dwc_otg_get_mode(dwc_otg_core_if_t * core_if)
++{
++ gintsts_data_t gintsts;
++ gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
++ return gintsts.b.curmode;
++}
++
++uint32_t dwc_otg_get_hnpcapable(dwc_otg_core_if_t * core_if)
++{
++ gusbcfg_data_t usbcfg;
++ usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
++ return usbcfg.b.hnpcap;
++}
++
++void dwc_otg_set_hnpcapable(dwc_otg_core_if_t * core_if, uint32_t val)
++{
++ gusbcfg_data_t usbcfg;
++ usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
++ usbcfg.b.hnpcap = val;
++ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, usbcfg.d32);
++}
++
++uint32_t dwc_otg_get_srpcapable(dwc_otg_core_if_t * core_if)
++{
++ gusbcfg_data_t usbcfg;
++ usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
++ return usbcfg.b.srpcap;
++}
++
++void dwc_otg_set_srpcapable(dwc_otg_core_if_t * core_if, uint32_t val)
++{
++ gusbcfg_data_t usbcfg;
++ usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
++ usbcfg.b.srpcap = val;
++ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, usbcfg.d32);
++}
++
++uint32_t dwc_otg_get_devspeed(dwc_otg_core_if_t * core_if)
++{
++ dcfg_data_t dcfg;
++ /* originally: dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg); */
++
++ dcfg.d32 = -1; //GRAYG
++ DWC_DEBUGPL(DBG_CILV, "%s - core_if(%p)\n", __func__, core_if);
++ if (NULL == core_if)
++ DWC_ERROR("reg request with NULL core_if\n");
++ DWC_DEBUGPL(DBG_CILV, "%s - core_if(%p)->dev_if(%p)\n", __func__,
++ core_if, core_if->dev_if);
++ if (NULL == core_if->dev_if)
++ DWC_ERROR("reg request with NULL dev_if\n");
++ DWC_DEBUGPL(DBG_CILV, "%s - core_if(%p)->dev_if(%p)->"
++ "dev_global_regs(%p)\n", __func__,
++ core_if, core_if->dev_if,
++ core_if->dev_if->dev_global_regs);
++ if (NULL == core_if->dev_if->dev_global_regs)
++ DWC_ERROR("reg request with NULL dev_global_regs\n");
++ else {
++ DWC_DEBUGPL(DBG_CILV, "%s - &core_if(%p)->dev_if(%p)->"
++ "dev_global_regs(%p)->dcfg = %p\n", __func__,
++ core_if, core_if->dev_if,
++ core_if->dev_if->dev_global_regs,
++ &core_if->dev_if->dev_global_regs->dcfg);
++ dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
++ }
++ return dcfg.b.devspd;
++}
++
++void dwc_otg_set_devspeed(dwc_otg_core_if_t * core_if, uint32_t val)
++{
++ dcfg_data_t dcfg;
++ dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
++ dcfg.b.devspd = val;
++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32);
++}
++
++uint32_t dwc_otg_get_busconnected(dwc_otg_core_if_t * core_if)
++{
++ hprt0_data_t hprt0;
++ hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
++ return hprt0.b.prtconnsts;
++}
++
++uint32_t dwc_otg_get_enumspeed(dwc_otg_core_if_t * core_if)
++{
++ dsts_data_t dsts;
++ dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
++ return dsts.b.enumspd;
++}
++
++uint32_t dwc_otg_get_prtpower(dwc_otg_core_if_t * core_if)
++{
++ hprt0_data_t hprt0;
++ hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
++ return hprt0.b.prtpwr;
++
++}
++
++uint32_t dwc_otg_get_core_state(dwc_otg_core_if_t * core_if)
++{
++ return core_if->hibernation_suspend;
++}
++
++void dwc_otg_set_prtpower(dwc_otg_core_if_t * core_if, uint32_t val)
++{
++ hprt0_data_t hprt0;
++ hprt0.d32 = dwc_otg_read_hprt0(core_if);
++ hprt0.b.prtpwr = val;
++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
++}
++
++uint32_t dwc_otg_get_prtsuspend(dwc_otg_core_if_t * core_if)
++{
++ hprt0_data_t hprt0;
++ hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
++ return hprt0.b.prtsusp;
++
++}
++
++void dwc_otg_set_prtsuspend(dwc_otg_core_if_t * core_if, uint32_t val)
++{
++ hprt0_data_t hprt0;
++ hprt0.d32 = dwc_otg_read_hprt0(core_if);
++ hprt0.b.prtsusp = val;
++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
++}
++
++uint32_t dwc_otg_get_fr_interval(dwc_otg_core_if_t * core_if)
++{
++ hfir_data_t hfir;
++ hfir.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hfir);
++ return hfir.b.frint;
++
++}
++
++void dwc_otg_set_fr_interval(dwc_otg_core_if_t * core_if, uint32_t val)
++{
++ hfir_data_t hfir;
++ uint32_t fram_int;
++ fram_int = calc_frame_interval(core_if);
++ hfir.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hfir);
++ if (!core_if->core_params->reload_ctl) {
++ DWC_WARN("\nCannot reload HFIR register.HFIR.HFIRRldCtrl bit is"
++ "not set to 1.\nShould load driver with reload_ctl=1"
++ " module parameter\n");
++ return;
++ }
++ switch (fram_int) {
++ case 3750:
++ if ((val < 3350) || (val > 4150)) {
++ DWC_WARN("HFIR interval for HS core and 30 MHz"
++ "clock freq should be from 3350 to 4150\n");
++ return;
++ }
++ break;
++ case 30000:
++ if ((val < 26820) || (val > 33180)) {
++ DWC_WARN("HFIR interval for FS/LS core and 30 MHz"
++ "clock freq should be from 26820 to 33180\n");
++ return;
++ }
++ break;
++ case 6000:
++ if ((val < 5360) || (val > 6640)) {
++ DWC_WARN("HFIR interval for HS core and 48 MHz"
++ "clock freq should be from 5360 to 6640\n");
++ return;
++ }
++ break;
++ case 48000:
++ if ((val < 42912) || (val > 53088)) {
++ DWC_WARN("HFIR interval for FS/LS core and 48 MHz"
++ "clock freq should be from 42912 to 53088\n");
++ return;
++ }
++ break;
++ case 7500:
++ if ((val < 6700) || (val > 8300)) {
++ DWC_WARN("HFIR interval for HS core and 60 MHz"
++ "clock freq should be from 6700 to 8300\n");
++ return;
++ }
++ break;
++ case 60000:
++ if ((val < 53640) || (val > 65536)) {
++ DWC_WARN("HFIR interval for FS/LS core and 60 MHz"
++ "clock freq should be from 53640 to 65536\n");
++ return;
++ }
++ break;
++ default:
++ DWC_WARN("Unknown frame interval\n");
++ return;
++ break;
++
++ }
++ hfir.b.frint = val;
++ DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hfir, hfir.d32);
++}
++
++uint32_t dwc_otg_get_mode_ch_tim(dwc_otg_core_if_t * core_if)
++{
++ hcfg_data_t hcfg;
++ hcfg.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
++ return hcfg.b.modechtimen;
++
++}
++
++void dwc_otg_set_mode_ch_tim(dwc_otg_core_if_t * core_if, uint32_t val)
++{
++ hcfg_data_t hcfg;
++ hcfg.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
++ hcfg.b.modechtimen = val;
++ DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg, hcfg.d32);
++}
++
++void dwc_otg_set_prtresume(dwc_otg_core_if_t * core_if, uint32_t val)
++{
++ hprt0_data_t hprt0;
++ hprt0.d32 = dwc_otg_read_hprt0(core_if);
++ hprt0.b.prtres = val;
++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
++}
++
++uint32_t dwc_otg_get_remotewakesig(dwc_otg_core_if_t * core_if)
++{
++ dctl_data_t dctl;
++ dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
++ return dctl.b.rmtwkupsig;
++}
++
++uint32_t dwc_otg_get_lpm_portsleepstatus(dwc_otg_core_if_t * core_if)
++{
++ glpmcfg_data_t lpmcfg;
++ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
++
++ DWC_ASSERT(!
++ ((core_if->lx_state == DWC_OTG_L1) ^ lpmcfg.b.prt_sleep_sts),
++ "lx_state = %d, lmpcfg.prt_sleep_sts = %d\n",
++ core_if->lx_state, lpmcfg.b.prt_sleep_sts);
++
++ return lpmcfg.b.prt_sleep_sts;
++}
++
++uint32_t dwc_otg_get_lpm_remotewakeenabled(dwc_otg_core_if_t * core_if)
++{
++ glpmcfg_data_t lpmcfg;
++ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
++ return lpmcfg.b.rem_wkup_en;
++}
++
++uint32_t dwc_otg_get_lpmresponse(dwc_otg_core_if_t * core_if)
++{
++ glpmcfg_data_t lpmcfg;
++ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
++ return lpmcfg.b.appl_resp;
++}
++
++void dwc_otg_set_lpmresponse(dwc_otg_core_if_t * core_if, uint32_t val)
++{
++ glpmcfg_data_t lpmcfg;
++ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
++ lpmcfg.b.appl_resp = val;
++ DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
++}
++
++uint32_t dwc_otg_get_hsic_connect(dwc_otg_core_if_t * core_if)
++{
++ glpmcfg_data_t lpmcfg;
++ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
++ return lpmcfg.b.hsic_connect;
++}
++
++void dwc_otg_set_hsic_connect(dwc_otg_core_if_t * core_if, uint32_t val)
++{
++ glpmcfg_data_t lpmcfg;
++ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
++ lpmcfg.b.hsic_connect = val;
++ DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
++}
++
++uint32_t dwc_otg_get_inv_sel_hsic(dwc_otg_core_if_t * core_if)
++{
++ glpmcfg_data_t lpmcfg;
++ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
++ return lpmcfg.b.inv_sel_hsic;
++
++}
++
++void dwc_otg_set_inv_sel_hsic(dwc_otg_core_if_t * core_if, uint32_t val)
++{
++ glpmcfg_data_t lpmcfg;
++ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
++ lpmcfg.b.inv_sel_hsic = val;
++ DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
++}
++
++uint32_t dwc_otg_get_gotgctl(dwc_otg_core_if_t * core_if)
++{
++ return DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
++}
++
++void dwc_otg_set_gotgctl(dwc_otg_core_if_t * core_if, uint32_t val)
++{
++ DWC_WRITE_REG32(&core_if->core_global_regs->gotgctl, val);
++}
++
++uint32_t dwc_otg_get_gusbcfg(dwc_otg_core_if_t * core_if)
++{
++ return DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
++}
++
++void dwc_otg_set_gusbcfg(dwc_otg_core_if_t * core_if, uint32_t val)
++{
++ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, val);
++}
++
++uint32_t dwc_otg_get_grxfsiz(dwc_otg_core_if_t * core_if)
++{
++ return DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
++}
++
++void dwc_otg_set_grxfsiz(dwc_otg_core_if_t * core_if, uint32_t val)
++{
++ DWC_WRITE_REG32(&core_if->core_global_regs->grxfsiz, val);
++}
++
++uint32_t dwc_otg_get_gnptxfsiz(dwc_otg_core_if_t * core_if)
++{
++ return DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz);
++}
++
++void dwc_otg_set_gnptxfsiz(dwc_otg_core_if_t * core_if, uint32_t val)
++{
++ DWC_WRITE_REG32(&core_if->core_global_regs->gnptxfsiz, val);
++}
++
++uint32_t dwc_otg_get_gpvndctl(dwc_otg_core_if_t * core_if)
++{
++ return DWC_READ_REG32(&core_if->core_global_regs->gpvndctl);
++}
++
++void dwc_otg_set_gpvndctl(dwc_otg_core_if_t * core_if, uint32_t val)
++{
++ DWC_WRITE_REG32(&core_if->core_global_regs->gpvndctl, val);
++}
++
++uint32_t dwc_otg_get_ggpio(dwc_otg_core_if_t * core_if)
++{
++ return DWC_READ_REG32(&core_if->core_global_regs->ggpio);
++}
++
++void dwc_otg_set_ggpio(dwc_otg_core_if_t * core_if, uint32_t val)
++{
++ DWC_WRITE_REG32(&core_if->core_global_regs->ggpio, val);
++}
++
++uint32_t dwc_otg_get_hprt0(dwc_otg_core_if_t * core_if)
++{
++ return DWC_READ_REG32(core_if->host_if->hprt0);
++
++}
++
++void dwc_otg_set_hprt0(dwc_otg_core_if_t * core_if, uint32_t val)
++{
++ DWC_WRITE_REG32(core_if->host_if->hprt0, val);
++}
++
++uint32_t dwc_otg_get_guid(dwc_otg_core_if_t * core_if)
++{
++ return DWC_READ_REG32(&core_if->core_global_regs->guid);
++}
++
++void dwc_otg_set_guid(dwc_otg_core_if_t * core_if, uint32_t val)
++{
++ DWC_WRITE_REG32(&core_if->core_global_regs->guid, val);
++}
++
++uint32_t dwc_otg_get_hptxfsiz(dwc_otg_core_if_t * core_if)
++{
++ return DWC_READ_REG32(&core_if->core_global_regs->hptxfsiz);
++}
++
++uint16_t dwc_otg_get_otg_version(dwc_otg_core_if_t * core_if)
++{
++ return ((core_if->otg_ver == 1) ? (uint16_t)0x0200 : (uint16_t)0x0103);
++}
++
++/**
++ * Start the SRP timer to detect when the SRP does not complete within
++ * 6 seconds.
++ *
++ * @param core_if the pointer to core_if strucure.
++ */
++void dwc_otg_pcd_start_srp_timer(dwc_otg_core_if_t * core_if)
++{
++ core_if->srp_timer_started = 1;
++ DWC_TIMER_SCHEDULE(core_if->srp_timer, 6000 /* 6 secs */ );
++}
++
++void dwc_otg_initiate_srp(dwc_otg_core_if_t * core_if)
++{
++ uint32_t *addr = (uint32_t *) & (core_if->core_global_regs->gotgctl);
++ gotgctl_data_t mem;
++ gotgctl_data_t val;
++
++ val.d32 = DWC_READ_REG32(addr);
++ if (val.b.sesreq) {
++ DWC_ERROR("Session Request Already active!\n");
++ return;
++ }
++
++ DWC_INFO("Session Request Initated\n"); //NOTICE
++ mem.d32 = DWC_READ_REG32(addr);
++ mem.b.sesreq = 1;
++ DWC_WRITE_REG32(addr, mem.d32);
++
++ /* Start the SRP timer */
++ dwc_otg_pcd_start_srp_timer(core_if);
++ return;
++}
+diff -Nur linux-4.1.3/drivers/usb/host/dwc_otg/dwc_otg_cil.h linux-xbian-rpi/drivers/usb/host/dwc_otg/dwc_otg_cil.h
+--- linux-4.1.3/drivers/usb/host/dwc_otg/dwc_otg_cil.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/usb/host/dwc_otg/dwc_otg_cil.h 2015-07-28 01:20:58.445156473 +0200
+@@ -0,0 +1,1464 @@
++/* ==========================================================================
++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil.h $
++ * $Revision: #123 $
++ * $Date: 2012/08/10 $
++ * $Change: 2047372 $
++ *
++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++ * otherwise expressly agreed to in writing between Synopsys and you.
++ *
++ * The Software IS NOT an item of Licensed Software or Licensed Product under
++ * any End User Software License Agreement or Agreement for Licensed Product
++ * with Synopsys or any supplement thereto. You are permitted to use and
++ * redistribute this Software in source and binary forms, with or without
++ * modification, provided that redistributions of source code must retain this
++ * notice. You may not view, use, disclose, copy or distribute this file or
++ * any information contained herein except pursuant to this license grant from
++ * Synopsys. If you do not agree with this notice, including the disclaimer
++ * below, then you are not authorized to use the Software.
++ *
++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++ * DAMAGE.
++ * ========================================================================== */
++
++#if !defined(__DWC_CIL_H__)
++#define __DWC_CIL_H__
++
++#include "dwc_list.h"
++#include "dwc_otg_dbg.h"
++#include "dwc_otg_regs.h"
++
++#include "dwc_otg_core_if.h"
++#include "dwc_otg_adp.h"
++
++/**
++ * @file
++ * This file contains the interface to the Core Interface Layer.
++ */
++
++#ifdef DWC_UTE_CFI
++
++#define MAX_DMA_DESCS_PER_EP 256
++
++/**
++ * Enumeration for the data buffer mode
++ */
++typedef enum _data_buffer_mode {
++ BM_STANDARD = 0, /* data buffer is in normal mode */
++ BM_SG = 1, /* data buffer uses the scatter/gather mode */
++ BM_CONCAT = 2, /* data buffer uses the concatenation mode */
++ BM_CIRCULAR = 3, /* data buffer uses the circular DMA mode */
++ BM_ALIGN = 4 /* data buffer is in buffer alignment mode */
++} data_buffer_mode_e;
++#endif //DWC_UTE_CFI
++
++/** Macros defined for DWC OTG HW Release version */
++
++#define OTG_CORE_REV_2_60a 0x4F54260A
++#define OTG_CORE_REV_2_71a 0x4F54271A
++#define OTG_CORE_REV_2_72a 0x4F54272A
++#define OTG_CORE_REV_2_80a 0x4F54280A
++#define OTG_CORE_REV_2_81a 0x4F54281A
++#define OTG_CORE_REV_2_90a 0x4F54290A
++#define OTG_CORE_REV_2_91a 0x4F54291A
++#define OTG_CORE_REV_2_92a 0x4F54292A
++#define OTG_CORE_REV_2_93a 0x4F54293A
++#define OTG_CORE_REV_2_94a 0x4F54294A
++#define OTG_CORE_REV_3_00a 0x4F54300A
++
++/**
++ * Information for each ISOC packet.
++ */
++typedef struct iso_pkt_info {
++ uint32_t offset;
++ uint32_t length;
++ int32_t status;
++} iso_pkt_info_t;
++
++/**
++ * The <code>dwc_ep</code> structure represents the state of a single
++ * endpoint when acting in device mode. It contains the data items
++ * needed for an endpoint to be activated and transfer packets.
++ */
++typedef struct dwc_ep {
++ /** EP number used for register address lookup */
++ uint8_t num;
++ /** EP direction 0 = OUT */
++ unsigned is_in:1;
++ /** EP active. */
++ unsigned active:1;
++
++ /**
++ * Periodic Tx FIFO # for IN EPs For INTR EP set to 0 to use non-periodic
++ * Tx FIFO. If dedicated Tx FIFOs are enabled Tx FIFO # FOR IN EPs*/
++ unsigned tx_fifo_num:4;
++ /** EP type: 0 - Control, 1 - ISOC, 2 - BULK, 3 - INTR */
++ unsigned type:2;
++#define DWC_OTG_EP_TYPE_CONTROL 0
++#define DWC_OTG_EP_TYPE_ISOC 1
++#define DWC_OTG_EP_TYPE_BULK 2
++#define DWC_OTG_EP_TYPE_INTR 3
++
++ /** DATA start PID for INTR and BULK EP */
++ unsigned data_pid_start:1;
++ /** Frame (even/odd) for ISOC EP */
++ unsigned even_odd_frame:1;
++ /** Max Packet bytes */
++ unsigned maxpacket:11;
++
++ /** Max Transfer size */
++ uint32_t maxxfer;
++
++ /** @name Transfer state */
++ /** @{ */
++
++ /**
++ * Pointer to the beginning of the transfer buffer -- do not modify
++ * during transfer.
++ */
++
++ dwc_dma_t dma_addr;
++
++ dwc_dma_t dma_desc_addr;
++ dwc_otg_dev_dma_desc_t *desc_addr;
++
++ uint8_t *start_xfer_buff;
++ /** pointer to the transfer buffer */
++ uint8_t *xfer_buff;
++ /** Number of bytes to transfer */
++ unsigned xfer_len:19;
++ /** Number of bytes transferred. */
++ unsigned xfer_count:19;
++ /** Sent ZLP */
++ unsigned sent_zlp:1;
++ /** Total len for control transfer */
++ unsigned total_len:19;
++
++ /** stall clear flag */
++ unsigned stall_clear_flag:1;
++
++ /** SETUP pkt cnt rollover flag for EP0 out*/
++ unsigned stp_rollover;
++
++#ifdef DWC_UTE_CFI
++ /* The buffer mode */
++ data_buffer_mode_e buff_mode;
++
++ /* The chain of DMA descriptors.
++ * MAX_DMA_DESCS_PER_EP will be allocated for each active EP.
++ */
++ dwc_otg_dma_desc_t *descs;
++
++ /* The DMA address of the descriptors chain start */
++ dma_addr_t descs_dma_addr;
++ /** This variable stores the length of the last enqueued request */
++ uint32_t cfi_req_len;
++#endif //DWC_UTE_CFI
++
++/** Max DMA Descriptor count for any EP */
++#define MAX_DMA_DESC_CNT 256
++ /** Allocated DMA Desc count */
++ uint32_t desc_cnt;
++
++ /** bInterval */
++ uint32_t bInterval;
++ /** Next frame num to setup next ISOC transfer */
++ uint32_t frame_num;
++ /** Indicates SOF number overrun in DSTS */
++ uint8_t frm_overrun;
++
++#ifdef DWC_UTE_PER_IO
++ /** Next frame num for which will be setup DMA Desc */
++ uint32_t xiso_frame_num;
++ /** bInterval */
++ uint32_t xiso_bInterval;
++ /** Count of currently active transfers - shall be either 0 or 1 */
++ int xiso_active_xfers;
++ int xiso_queued_xfers;
++#endif
++#ifdef DWC_EN_ISOC
++ /**
++ * Variables specific for ISOC EPs
++ *
++ */
++ /** DMA addresses of ISOC buffers */
++ dwc_dma_t dma_addr0;
++ dwc_dma_t dma_addr1;
++
++ dwc_dma_t iso_dma_desc_addr;
++ dwc_otg_dev_dma_desc_t *iso_desc_addr;
++
++ /** pointer to the transfer buffers */
++ uint8_t *xfer_buff0;
++ uint8_t *xfer_buff1;
++
++ /** number of ISOC Buffer is processing */
++ uint32_t proc_buf_num;
++ /** Interval of ISOC Buffer processing */
++ uint32_t buf_proc_intrvl;
++ /** Data size for regular frame */
++ uint32_t data_per_frame;
++
++ /* todo - pattern data support is to be implemented in the future */
++ /** Data size for pattern frame */
++ uint32_t data_pattern_frame;
++ /** Frame number of pattern data */
++ uint32_t sync_frame;
++
++ /** bInterval */
++ uint32_t bInterval;
++ /** ISO Packet number per frame */
++ uint32_t pkt_per_frm;
++ /** Next frame num for which will be setup DMA Desc */
++ uint32_t next_frame;
++ /** Number of packets per buffer processing */
++ uint32_t pkt_cnt;
++ /** Info for all isoc packets */
++ iso_pkt_info_t *pkt_info;
++ /** current pkt number */
++ uint32_t cur_pkt;
++ /** current pkt number */
++ uint8_t *cur_pkt_addr;
++ /** current pkt number */
++ uint32_t cur_pkt_dma_addr;
++#endif /* DWC_EN_ISOC */
++
++/** @} */
++} dwc_ep_t;
++
++/*
++ * Reasons for halting a host channel.
++ */
++typedef enum dwc_otg_halt_status {
++ DWC_OTG_HC_XFER_NO_HALT_STATUS,
++ DWC_OTG_HC_XFER_COMPLETE,
++ DWC_OTG_HC_XFER_URB_COMPLETE,
++ DWC_OTG_HC_XFER_ACK,
++ DWC_OTG_HC_XFER_NAK,
++ DWC_OTG_HC_XFER_NYET,
++ DWC_OTG_HC_XFER_STALL,
++ DWC_OTG_HC_XFER_XACT_ERR,
++ DWC_OTG_HC_XFER_FRAME_OVERRUN,
++ DWC_OTG_HC_XFER_BABBLE_ERR,
++ DWC_OTG_HC_XFER_DATA_TOGGLE_ERR,
++ DWC_OTG_HC_XFER_AHB_ERR,
++ DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE,
++ DWC_OTG_HC_XFER_URB_DEQUEUE
++} dwc_otg_halt_status_e;
++
++/**
++ * Host channel descriptor. This structure represents the state of a single
++ * host channel when acting in host mode. It contains the data items needed to
++ * transfer packets to an endpoint via a host channel.
++ */
++typedef struct dwc_hc {
++ /** Host channel number used for register address lookup */
++ uint8_t hc_num;
++
++ /** Device to access */
++ unsigned dev_addr:7;
++
++ /** EP to access */
++ unsigned ep_num:4;
++
++ /** EP direction. 0: OUT, 1: IN */
++ unsigned ep_is_in:1;
++
++ /**
++ * EP speed.
++ * One of the following values:
++ * - DWC_OTG_EP_SPEED_LOW
++ * - DWC_OTG_EP_SPEED_FULL
++ * - DWC_OTG_EP_SPEED_HIGH
++ */
++ unsigned speed:2;
++#define DWC_OTG_EP_SPEED_LOW 0
++#define DWC_OTG_EP_SPEED_FULL 1
++#define DWC_OTG_EP_SPEED_HIGH 2
++
++ /**
++ * Endpoint type.
++ * One of the following values:
++ * - DWC_OTG_EP_TYPE_CONTROL: 0
++ * - DWC_OTG_EP_TYPE_ISOC: 1
++ * - DWC_OTG_EP_TYPE_BULK: 2
++ * - DWC_OTG_EP_TYPE_INTR: 3
++ */
++ unsigned ep_type:2;
++
++ /** Max packet size in bytes */
++ unsigned max_packet:11;
++
++ /**
++ * PID for initial transaction.
++ * 0: DATA0,<br>
++ * 1: DATA2,<br>
++ * 2: DATA1,<br>
++ * 3: MDATA (non-Control EP),
++ * SETUP (Control EP)
++ */
++ unsigned data_pid_start:2;
++#define DWC_OTG_HC_PID_DATA0 0
++#define DWC_OTG_HC_PID_DATA2 1
++#define DWC_OTG_HC_PID_DATA1 2
++#define DWC_OTG_HC_PID_MDATA 3
++#define DWC_OTG_HC_PID_SETUP 3
++
++ /** Number of periodic transactions per (micro)frame */
++ unsigned multi_count:2;
++
++ /** @name Transfer State */
++ /** @{ */
++
++ /** Pointer to the current transfer buffer position. */
++ uint8_t *xfer_buff;
++ /**
++ * In Buffer DMA mode this buffer will be used
++ * if xfer_buff is not DWORD aligned.
++ */
++ dwc_dma_t align_buff;
++ /** Total number of bytes to transfer. */
++ uint32_t xfer_len;
++ /** Number of bytes transferred so far. */
++ uint32_t xfer_count;
++ /** Packet count at start of transfer.*/
++ uint16_t start_pkt_count;
++
++ /**
++ * Flag to indicate whether the transfer has been started. Set to 1 if
++ * it has been started, 0 otherwise.
++ */
++ uint8_t xfer_started;
++
++ /**
++ * Set to 1 to indicate that a PING request should be issued on this
++ * channel. If 0, process normally.
++ */
++ uint8_t do_ping;
++
++ /**
++ * Set to 1 to indicate that the error count for this transaction is
++ * non-zero. Set to 0 if the error count is 0.
++ */
++ uint8_t error_state;
++
++ /**
++ * Set to 1 to indicate that this channel should be halted the next
++ * time a request is queued for the channel. This is necessary in
++ * slave mode if no request queue space is available when an attempt
++ * is made to halt the channel.
++ */
++ uint8_t halt_on_queue;
++
++ /**
++ * Set to 1 if the host channel has been halted, but the core is not
++ * finished flushing queued requests. Otherwise 0.
++ */
++ uint8_t halt_pending;
++
++ /**
++ * Reason for halting the host channel.
++ */
++ dwc_otg_halt_status_e halt_status;
++
++ /*
++ * Split settings for the host channel
++ */
++ uint8_t do_split; /**< Enable split for the channel */
++ uint8_t complete_split; /**< Enable complete split */
++ uint8_t hub_addr; /**< Address of high speed hub */
++
++ uint8_t port_addr; /**< Port of the low/full speed device */
++ /** Split transaction position
++ * One of the following values:
++ * - DWC_HCSPLIT_XACTPOS_MID
++ * - DWC_HCSPLIT_XACTPOS_BEGIN
++ * - DWC_HCSPLIT_XACTPOS_END
++ * - DWC_HCSPLIT_XACTPOS_ALL */
++ uint8_t xact_pos;
++
++ /** Set when the host channel does a short read. */
++ uint8_t short_read;
++
++ /**
++ * Number of requests issued for this channel since it was assigned to
++ * the current transfer (not counting PINGs).
++ */
++ uint8_t requests;
++
++ /**
++ * Queue Head for the transfer being processed by this channel.
++ */
++ struct dwc_otg_qh *qh;
++
++ /** @} */
++
++ /** Entry in list of host channels. */
++ DWC_CIRCLEQ_ENTRY(dwc_hc) hc_list_entry;
++
++ /** @name Descriptor DMA support */
++ /** @{ */
++
++ /** Number of Transfer Descriptors */
++ uint16_t ntd;
++
++ /** Descriptor List DMA address */
++ dwc_dma_t desc_list_addr;
++
++ /** Scheduling micro-frame bitmap. */
++ uint8_t schinfo;
++
++ /** @} */
++} dwc_hc_t;
++
++/**
++ * The following parameters may be specified when starting the module. These
++ * parameters define how the DWC_otg controller should be configured.
++ */
++typedef struct dwc_otg_core_params {
++ int32_t opt;
++
++ /**
++ * Specifies the OTG capabilities. The driver will automatically
++ * detect the value for this parameter if none is specified.
++ * 0 - HNP and SRP capable (default)
++ * 1 - SRP Only capable
++ * 2 - No HNP/SRP capable
++ */
++ int32_t otg_cap;
++
++ /**
++ * Specifies whether to use slave or DMA mode for accessing the data
++ * FIFOs. The driver will automatically detect the value for this
++ * parameter if none is specified.
++ * 0 - Slave
++ * 1 - DMA (default, if available)
++ */
++ int32_t dma_enable;
++
++ /**
++ * When DMA mode is enabled specifies whether to use address DMA or DMA
++ * Descriptor mode for accessing the data FIFOs in device mode. The driver
++ * will automatically detect the value for this if none is specified.
++ * 0 - address DMA
++ * 1 - DMA Descriptor(default, if available)
++ */
++ int32_t dma_desc_enable;
++ /** The DMA Burst size (applicable only for External DMA
++ * Mode). 1, 4, 8 16, 32, 64, 128, 256 (default 32)
++ */
++ int32_t dma_burst_size; /* Translate this to GAHBCFG values */
++
++ /**
++ * Specifies the maximum speed of operation in host and device mode.
++ * The actual speed depends on the speed of the attached device and
++ * the value of phy_type. The actual speed depends on the speed of the
++ * attached device.
++ * 0 - High Speed (default)
++ * 1 - Full Speed
++ */
++ int32_t speed;
++ /** Specifies whether low power mode is supported when attached
++ * to a Full Speed or Low Speed device in host mode.
++ * 0 - Don't support low power mode (default)
++ * 1 - Support low power mode
++ */
++ int32_t host_support_fs_ls_low_power;
++
++ /** Specifies the PHY clock rate in low power mode when connected to a
++ * Low Speed device in host mode. This parameter is applicable only if
++ * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS
++ * then defaults to 6 MHZ otherwise 48 MHZ.
++ *
++ * 0 - 48 MHz
++ * 1 - 6 MHz
++ */
++ int32_t host_ls_low_power_phy_clk;
++
++ /**
++ * 0 - Use cC FIFO size parameters
++ * 1 - Allow dynamic FIFO sizing (default)
++ */
++ int32_t enable_dynamic_fifo;
++
++ /** Total number of 4-byte words in the data FIFO memory. This
++ * memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic
++ * Tx FIFOs.
++ * 32 to 32768 (default 8192)
++ * Note: The total FIFO memory depth in the FPGA configuration is 8192.
++ */
++ int32_t data_fifo_size;
++
++ /** Number of 4-byte words in the Rx FIFO in device mode when dynamic
++ * FIFO sizing is enabled.
++ * 16 to 32768 (default 1064)
++ */
++ int32_t dev_rx_fifo_size;
++
++ /** Number of 4-byte words in the non-periodic Tx FIFO in device mode
++ * when dynamic FIFO sizing is enabled.
++ * 16 to 32768 (default 1024)
++ */
++ int32_t dev_nperio_tx_fifo_size;
++
++ /** Number of 4-byte words in each of the periodic Tx FIFOs in device
++ * mode when dynamic FIFO sizing is enabled.
++ * 4 to 768 (default 256)
++ */
++ uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];
++
++ /** Number of 4-byte words in the Rx FIFO in host mode when dynamic
++ * FIFO sizing is enabled.
++ * 16 to 32768 (default 1024)
++ */
++ int32_t host_rx_fifo_size;
++
++ /** Number of 4-byte words in the non-periodic Tx FIFO in host mode
++ * when Dynamic FIFO sizing is enabled in the core.
++ * 16 to 32768 (default 1024)
++ */
++ int32_t host_nperio_tx_fifo_size;
++
++ /** Number of 4-byte words in the host periodic Tx FIFO when dynamic
++ * FIFO sizing is enabled.
++ * 16 to 32768 (default 1024)
++ */
++ int32_t host_perio_tx_fifo_size;
++
++ /** The maximum transfer size supported in bytes.
++ * 2047 to 65,535 (default 65,535)
++ */
++ int32_t max_transfer_size;
++
++ /** The maximum number of packets in a transfer.
++ * 15 to 511 (default 511)
++ */
++ int32_t max_packet_count;
++
++ /** The number of host channel registers to use.
++ * 1 to 16 (default 12)
++ * Note: The FPGA configuration supports a maximum of 12 host channels.
++ */
++ int32_t host_channels;
++
++ /** The number of endpoints in addition to EP0 available for device
++ * mode operations.
++ * 1 to 15 (default 6 IN and OUT)
++ * Note: The FPGA configuration supports a maximum of 6 IN and OUT
++ * endpoints in addition to EP0.
++ */
++ int32_t dev_endpoints;
++
++ /**
++ * Specifies the type of PHY interface to use. By default, the driver
++ * will automatically detect the phy_type.
++ *
++ * 0 - Full Speed PHY
++ * 1 - UTMI+ (default)
++ * 2 - ULPI
++ */
++ int32_t phy_type;
++
++ /**
++ * Specifies the UTMI+ Data Width. This parameter is
++ * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI
++ * PHY_TYPE, this parameter indicates the data width between
++ * the MAC and the ULPI Wrapper.) Also, this parameter is
++ * applicable only if the OTG_HSPHY_WIDTH cC parameter was set
++ * to "8 and 16 bits", meaning that the core has been
++ * configured to work at either data path width.
++ *
++ * 8 or 16 bits (default 16)
++ */
++ int32_t phy_utmi_width;
++
++ /**
++ * Specifies whether the ULPI operates at double or single
++ * data rate. This parameter is only applicable if PHY_TYPE is
++ * ULPI.
++ *
++ * 0 - single data rate ULPI interface with 8 bit wide data
++ * bus (default)
++ * 1 - double data rate ULPI interface with 4 bit wide data
++ * bus
++ */
++ int32_t phy_ulpi_ddr;
++
++ /**
++ * Specifies whether to use the internal or external supply to
++ * drive the vbus with a ULPI phy.
++ */
++ int32_t phy_ulpi_ext_vbus;
++
++ /**
++ * Specifies whether to use the I2Cinterface for full speed PHY. This
++ * parameter is only applicable if PHY_TYPE is FS.
++ * 0 - No (default)
++ * 1 - Yes
++ */
++ int32_t i2c_enable;
++
++ int32_t ulpi_fs_ls;
++
++ int32_t ts_dline;
++
++ /**
++ * Specifies whether dedicated transmit FIFOs are
++ * enabled for non periodic IN endpoints in device mode
++ * 0 - No
++ * 1 - Yes
++ */
++ int32_t en_multiple_tx_fifo;
++
++ /** Number of 4-byte words in each of the Tx FIFOs in device
++ * mode when dynamic FIFO sizing is enabled.
++ * 4 to 768 (default 256)
++ */
++ uint32_t dev_tx_fifo_size[MAX_TX_FIFOS];
++
++ /** Thresholding enable flag-
++ * bit 0 - enable non-ISO Tx thresholding
++ * bit 1 - enable ISO Tx thresholding
++ * bit 2 - enable Rx thresholding
++ */
++ uint32_t thr_ctl;
++
++ /** Thresholding length for Tx
++ * FIFOs in 32 bit DWORDs
++ */
++ uint32_t tx_thr_length;
++
++ /** Thresholding length for Rx
++ * FIFOs in 32 bit DWORDs
++ */
++ uint32_t rx_thr_length;
++
++ /**
++ * Specifies whether LPM (Link Power Management) support is enabled
++ */
++ int32_t lpm_enable;
++
++ /** Per Transfer Interrupt
++ * mode enable flag
++ * 1 - Enabled
++ * 0 - Disabled
++ */
++ int32_t pti_enable;
++
++ /** Multi Processor Interrupt
++ * mode enable flag
++ * 1 - Enabled
++ * 0 - Disabled
++ */
++ int32_t mpi_enable;
++
++ /** IS_USB Capability
++ * 1 - Enabled
++ * 0 - Disabled
++ */
++ int32_t ic_usb_cap;
++
++ /** AHB Threshold Ratio
++ * 2'b00 AHB Threshold = MAC Threshold
++ * 2'b01 AHB Threshold = 1/2 MAC Threshold
++ * 2'b10 AHB Threshold = 1/4 MAC Threshold
++ * 2'b11 AHB Threshold = 1/8 MAC Threshold
++ */
++ int32_t ahb_thr_ratio;
++
++ /** ADP Support
++ * 1 - Enabled
++ * 0 - Disabled
++ */
++ int32_t adp_supp_enable;
++
++ /** HFIR Reload Control
++ * 0 - The HFIR cannot be reloaded dynamically.
++ * 1 - Allow dynamic reloading of the HFIR register during runtime.
++ */
++ int32_t reload_ctl;
++
++ /** DCFG: Enable device Out NAK
++ * 0 - The core does not set NAK after Bulk Out transfer complete.
++ * 1 - The core sets NAK after Bulk OUT transfer complete.
++ */
++ int32_t dev_out_nak;
++
++ /** DCFG: Enable Continue on BNA
++ * After receiving BNA interrupt the core disables the endpoint,when the
++ * endpoint is re-enabled by the application the core starts processing
++ * 0 - from the DOEPDMA descriptor
++ * 1 - from the descriptor which received the BNA.
++ */
++ int32_t cont_on_bna;
++
++ /** GAHBCFG: AHB Single Support
++ * This bit when programmed supports SINGLE transfers for remainder
++ * data in a transfer for DMA mode of operation.
++ * 0 - in this case the remainder data will be sent using INCR burst size.
++ * 1 - in this case the remainder data will be sent using SINGLE burst size.
++ */
++ int32_t ahb_single;
++
++ /** Core Power down mode
++ * 0 - No Power Down is enabled
++ * 1 - Reserved
++ * 2 - Complete Power Down (Hibernation)
++ */
++ int32_t power_down;
++
++ /** OTG revision supported
++ * 0 - OTG 1.3 revision
++ * 1 - OTG 2.0 revision
++ */
++ int32_t otg_ver;
++
++} dwc_otg_core_params_t;
++
++#ifdef DEBUG
++struct dwc_otg_core_if;
++typedef struct hc_xfer_info {
++ struct dwc_otg_core_if *core_if;
++ dwc_hc_t *hc;
++} hc_xfer_info_t;
++#endif
++
++typedef struct ep_xfer_info {
++ struct dwc_otg_core_if *core_if;
++ dwc_ep_t *ep;
++ uint8_t state;
++} ep_xfer_info_t;
++/*
++ * Device States
++ */
++typedef enum dwc_otg_lx_state {
++ /** On state */
++ DWC_OTG_L0,
++ /** LPM sleep state*/
++ DWC_OTG_L1,
++ /** USB suspend state*/
++ DWC_OTG_L2,
++ /** Off state*/
++ DWC_OTG_L3
++} dwc_otg_lx_state_e;
++
++struct dwc_otg_global_regs_backup {
++ uint32_t gotgctl_local;
++ uint32_t gintmsk_local;
++ uint32_t gahbcfg_local;
++ uint32_t gusbcfg_local;
++ uint32_t grxfsiz_local;
++ uint32_t gnptxfsiz_local;
++#ifdef CONFIG_USB_DWC_OTG_LPM
++ uint32_t glpmcfg_local;
++#endif
++ uint32_t gi2cctl_local;
++ uint32_t hptxfsiz_local;
++ uint32_t pcgcctl_local;
++ uint32_t gdfifocfg_local;
++ uint32_t dtxfsiz_local[MAX_EPS_CHANNELS];
++ uint32_t gpwrdn_local;
++ uint32_t xhib_pcgcctl;
++ uint32_t xhib_gpwrdn;
++};
++
++struct dwc_otg_host_regs_backup {
++ uint32_t hcfg_local;
++ uint32_t haintmsk_local;
++ uint32_t hcintmsk_local[MAX_EPS_CHANNELS];
++ uint32_t hprt0_local;
++ uint32_t hfir_local;
++};
++
++struct dwc_otg_dev_regs_backup {
++ uint32_t dcfg;
++ uint32_t dctl;
++ uint32_t daintmsk;
++ uint32_t diepmsk;
++ uint32_t doepmsk;
++ uint32_t diepctl[MAX_EPS_CHANNELS];
++ uint32_t dieptsiz[MAX_EPS_CHANNELS];
++ uint32_t diepdma[MAX_EPS_CHANNELS];
++};
++/**
++ * The <code>dwc_otg_core_if</code> structure contains information needed to manage
++ * the DWC_otg controller acting in either host or device mode. It
++ * represents the programming view of the controller as a whole.
++ */
++struct dwc_otg_core_if {
++ /** Parameters that define how the core should be configured.*/
++ dwc_otg_core_params_t *core_params;
++
++ /** Core Global registers starting at offset 000h. */
++ dwc_otg_core_global_regs_t *core_global_regs;
++
++ /** Device-specific information */
++ dwc_otg_dev_if_t *dev_if;
++ /** Host-specific information */
++ dwc_otg_host_if_t *host_if;
++
++ /** Value from SNPSID register */
++ uint32_t snpsid;
++
++ /*
++ * Set to 1 if the core PHY interface bits in USBCFG have been
++ * initialized.
++ */
++ uint8_t phy_init_done;
++
++ /*
++ * SRP Success flag, set by srp success interrupt in FS I2C mode
++ */
++ uint8_t srp_success;
++ uint8_t srp_timer_started;
++ /** Timer for SRP. If it expires before SRP is successful
++ * clear the SRP. */
++ dwc_timer_t *srp_timer;
++
++#ifdef DWC_DEV_SRPCAP
++ /* This timer is needed to power on the hibernated host core if SRP is not
++ * initiated on connected SRP capable device for limited period of time
++ */
++ uint8_t pwron_timer_started;
++ dwc_timer_t *pwron_timer;
++#endif
++ /* Common configuration information */
++ /** Power and Clock Gating Control Register */
++ volatile uint32_t *pcgcctl;
++#define DWC_OTG_PCGCCTL_OFFSET 0xE00
++
++ /** Push/pop addresses for endpoints or host channels.*/
++ uint32_t *data_fifo[MAX_EPS_CHANNELS];
++#define DWC_OTG_DATA_FIFO_OFFSET 0x1000
++#define DWC_OTG_DATA_FIFO_SIZE 0x1000
++
++ /** Total RAM for FIFOs (Bytes) */
++ uint16_t total_fifo_size;
++ /** Size of Rx FIFO (Bytes) */
++ uint16_t rx_fifo_size;
++ /** Size of Non-periodic Tx FIFO (Bytes) */
++ uint16_t nperio_tx_fifo_size;
++
++ /** 1 if DMA is enabled, 0 otherwise. */
++ uint8_t dma_enable;
++
++ /** 1 if DMA descriptor is enabled, 0 otherwise. */
++ uint8_t dma_desc_enable;
++
++ /** 1 if PTI Enhancement mode is enabled, 0 otherwise. */
++ uint8_t pti_enh_enable;
++
++ /** 1 if MPI Enhancement mode is enabled, 0 otherwise. */
++ uint8_t multiproc_int_enable;
++
++ /** 1 if dedicated Tx FIFOs are enabled, 0 otherwise. */
++ uint8_t en_multiple_tx_fifo;
++
++ /** Set to 1 if multiple packets of a high-bandwidth transfer is in
++ * process of being queued */
++ uint8_t queuing_high_bandwidth;
++
++ /** Hardware Configuration -- stored here for convenience.*/
++ hwcfg1_data_t hwcfg1;
++ hwcfg2_data_t hwcfg2;
++ hwcfg3_data_t hwcfg3;
++ hwcfg4_data_t hwcfg4;
++ fifosize_data_t hptxfsiz;
++
++ /** Host and Device Configuration -- stored here for convenience.*/
++ hcfg_data_t hcfg;
++ dcfg_data_t dcfg;
++
++ /** The operational State, during transations
++ * (a_host>>a_peripherial and b_device=>b_host) this may not
++ * match the core but allows the software to determine
++ * transitions.
++ */
++ uint8_t op_state;
++
++ /**
++ * Set to 1 if the HCD needs to be restarted on a session request
++ * interrupt. This is required if no connector ID status change has
++ * occurred since the HCD was last disconnected.
++ */
++ uint8_t restart_hcd_on_session_req;
++
++ /** HCD callbacks */
++ /** A-Device is a_host */
++#define A_HOST (1)
++ /** A-Device is a_suspend */
++#define A_SUSPEND (2)
++ /** A-Device is a_peripherial */
++#define A_PERIPHERAL (3)
++ /** B-Device is operating as a Peripheral. */
++#define B_PERIPHERAL (4)
++ /** B-Device is operating as a Host. */
++#define B_HOST (5)
++
++ /** HCD callbacks */
++ struct dwc_otg_cil_callbacks *hcd_cb;
++ /** PCD callbacks */
++ struct dwc_otg_cil_callbacks *pcd_cb;
++
++ /** Device mode Periodic Tx FIFO Mask */
++ uint32_t p_tx_msk;
++ /** Device mode Periodic Tx FIFO Mask */
++ uint32_t tx_msk;
++
++ /** Workqueue object used for handling several interrupts */
++ dwc_workq_t *wq_otg;
++
++ /** Timer object used for handling "Wakeup Detected" Interrupt */
++ dwc_timer_t *wkp_timer;
++ /** This arrays used for debug purposes for DEV OUT NAK enhancement */
++ uint32_t start_doeptsiz_val[MAX_EPS_CHANNELS];
++ ep_xfer_info_t ep_xfer_info[MAX_EPS_CHANNELS];
++ dwc_timer_t *ep_xfer_timer[MAX_EPS_CHANNELS];
++#ifdef DEBUG
++ uint32_t start_hcchar_val[MAX_EPS_CHANNELS];
++
++ hc_xfer_info_t hc_xfer_info[MAX_EPS_CHANNELS];
++ dwc_timer_t *hc_xfer_timer[MAX_EPS_CHANNELS];
++
++ uint32_t hfnum_7_samples;
++ uint64_t hfnum_7_frrem_accum;
++ uint32_t hfnum_0_samples;
++ uint64_t hfnum_0_frrem_accum;
++ uint32_t hfnum_other_samples;
++ uint64_t hfnum_other_frrem_accum;
++#endif
++
++#ifdef DWC_UTE_CFI
++ uint16_t pwron_rxfsiz;
++ uint16_t pwron_gnptxfsiz;
++ uint16_t pwron_txfsiz[15];
++
++ uint16_t init_rxfsiz;
++ uint16_t init_gnptxfsiz;
++ uint16_t init_txfsiz[15];
++#endif
++
++ /** Lx state of device */
++ dwc_otg_lx_state_e lx_state;
++
++ /** Saved Core Global registers */
++ struct dwc_otg_global_regs_backup *gr_backup;
++ /** Saved Host registers */
++ struct dwc_otg_host_regs_backup *hr_backup;
++ /** Saved Device registers */
++ struct dwc_otg_dev_regs_backup *dr_backup;
++
++ /** Power Down Enable */
++ uint32_t power_down;
++
++ /** ADP support Enable */
++ uint32_t adp_enable;
++
++ /** ADP structure object */
++ dwc_otg_adp_t adp;
++
++ /** hibernation/suspend flag */
++ int hibernation_suspend;
++
++ /** Device mode extended hibernation flag */
++ int xhib;
++
++ /** OTG revision supported */
++ uint32_t otg_ver;
++
++ /** OTG status flag used for HNP polling */
++ uint8_t otg_sts;
++
++ /** Pointer to either hcd->lock or pcd->lock */
++ dwc_spinlock_t *lock;
++
++ /** Start predict NextEP based on Learning Queue if equal 1,
++ * also used as counter of disabled NP IN EP's */
++ uint8_t start_predict;
++
++ /** NextEp sequence, including EP0: nextep_seq[] = EP if non-periodic and
++ * active, 0xff otherwise */
++ uint8_t nextep_seq[MAX_EPS_CHANNELS];
++
++ /** Index of fisrt EP in nextep_seq array which should be re-enabled **/
++ uint8_t first_in_nextep_seq;
++
++ /** Frame number while entering to ISR - needed for ISOCs **/
++ uint32_t frame_num;
++
++};
++
++#ifdef DEBUG
++/*
++ * This function is called when transfer is timed out.
++ */
++extern void hc_xfer_timeout(void *ptr);
++#endif
++
++/*
++ * This function is called when transfer is timed out on endpoint.
++ */
++extern void ep_xfer_timeout(void *ptr);
++
++/*
++ * The following functions are functions for works
++ * using during handling some interrupts
++ */
++extern void w_conn_id_status_change(void *p);
++
++extern void w_wakeup_detected(void *p);
++
++/** Saves global register values into system memory. */
++extern int dwc_otg_save_global_regs(dwc_otg_core_if_t * core_if);
++/** Saves device register values into system memory. */
++extern int dwc_otg_save_dev_regs(dwc_otg_core_if_t * core_if);
++/** Saves host register values into system memory. */
++extern int dwc_otg_save_host_regs(dwc_otg_core_if_t * core_if);
++/** Restore global register values. */
++extern int dwc_otg_restore_global_regs(dwc_otg_core_if_t * core_if);
++/** Restore host register values. */
++extern int dwc_otg_restore_host_regs(dwc_otg_core_if_t * core_if, int reset);
++/** Restore device register values. */
++extern int dwc_otg_restore_dev_regs(dwc_otg_core_if_t * core_if,
++ int rem_wakeup);
++extern int restore_lpm_i2c_regs(dwc_otg_core_if_t * core_if);
++extern int restore_essential_regs(dwc_otg_core_if_t * core_if, int rmode,
++ int is_host);
++
++extern int dwc_otg_host_hibernation_restore(dwc_otg_core_if_t * core_if,
++ int restore_mode, int reset);
++extern int dwc_otg_device_hibernation_restore(dwc_otg_core_if_t * core_if,
++ int rem_wakeup, int reset);
++
++/*
++ * The following functions support initialization of the CIL driver component
++ * and the DWC_otg controller.
++ */
++extern void dwc_otg_core_host_init(dwc_otg_core_if_t * _core_if);
++extern void dwc_otg_core_dev_init(dwc_otg_core_if_t * _core_if);
++
++/** @name Device CIL Functions
++ * The following functions support managing the DWC_otg controller in device
++ * mode.
++ */
++/**@{*/
++extern void dwc_otg_wakeup(dwc_otg_core_if_t * _core_if);
++extern void dwc_otg_read_setup_packet(dwc_otg_core_if_t * _core_if,
++ uint32_t * _dest);
++extern uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t * _core_if);
++extern void dwc_otg_ep0_activate(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);
++extern void dwc_otg_ep_activate(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);
++extern void dwc_otg_ep_deactivate(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);
++extern void dwc_otg_ep_start_transfer(dwc_otg_core_if_t * _core_if,
++ dwc_ep_t * _ep);
++extern void dwc_otg_ep_start_zl_transfer(dwc_otg_core_if_t * _core_if,
++ dwc_ep_t * _ep);
++extern void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t * _core_if,
++ dwc_ep_t * _ep);
++extern void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t * _core_if,
++ dwc_ep_t * _ep);
++extern void dwc_otg_ep_write_packet(dwc_otg_core_if_t * _core_if,
++ dwc_ep_t * _ep, int _dma);
++extern void dwc_otg_ep_set_stall(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);
++extern void dwc_otg_ep_clear_stall(dwc_otg_core_if_t * _core_if,
++ dwc_ep_t * _ep);
++extern void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t * _core_if);
++
++#ifdef DWC_EN_ISOC
++extern void dwc_otg_iso_ep_start_frm_transfer(dwc_otg_core_if_t * core_if,
++ dwc_ep_t * ep);
++extern void dwc_otg_iso_ep_start_buf_transfer(dwc_otg_core_if_t * core_if,
++ dwc_ep_t * ep);
++#endif /* DWC_EN_ISOC */
++/**@}*/
++
++/** @name Host CIL Functions
++ * The following functions support managing the DWC_otg controller in host
++ * mode.
++ */
++/**@{*/
++extern void dwc_otg_hc_init(dwc_otg_core_if_t * _core_if, dwc_hc_t * _hc);
++extern void dwc_otg_hc_halt(dwc_otg_core_if_t * _core_if,
++ dwc_hc_t * _hc, dwc_otg_halt_status_e _halt_status);
++extern void dwc_otg_hc_cleanup(dwc_otg_core_if_t * _core_if, dwc_hc_t * _hc);
++extern void dwc_otg_hc_start_transfer(dwc_otg_core_if_t * _core_if,
++ dwc_hc_t * _hc);
++extern int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t * _core_if,
++ dwc_hc_t * _hc);
++extern void dwc_otg_hc_do_ping(dwc_otg_core_if_t * _core_if, dwc_hc_t * _hc);
++extern void dwc_otg_hc_write_packet(dwc_otg_core_if_t * _core_if,
++ dwc_hc_t * _hc);
++extern void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t * _core_if);
++extern void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t * _core_if);
++
++extern void dwc_otg_hc_start_transfer_ddma(dwc_otg_core_if_t * core_if,
++ dwc_hc_t * hc);
++
++extern uint32_t calc_frame_interval(dwc_otg_core_if_t * core_if);
++
++/* Macro used to clear one channel interrupt */
++#define clear_hc_int(_hc_regs_, _intr_) \
++do { \
++ hcint_data_t hcint_clear = {.d32 = 0}; \
++ hcint_clear.b._intr_ = 1; \
++ DWC_WRITE_REG32(&(_hc_regs_)->hcint, hcint_clear.d32); \
++} while (0)
++
++/*
++ * Macro used to disable one channel interrupt. Channel interrupts are
++ * disabled when the channel is halted or released by the interrupt handler.
++ * There is no need to handle further interrupts of that type until the
++ * channel is re-assigned. In fact, subsequent handling may cause crashes
++ * because the channel structures are cleaned up when the channel is released.
++ */
++#define disable_hc_int(_hc_regs_, _intr_) \
++do { \
++ hcintmsk_data_t hcintmsk = {.d32 = 0}; \
++ hcintmsk.b._intr_ = 1; \
++ DWC_MODIFY_REG32(&(_hc_regs_)->hcintmsk, hcintmsk.d32, 0); \
++} while (0)
++
++/**
++ * This function Reads HPRT0 in preparation to modify. It keeps the
++ * WC bits 0 so that if they are read as 1, they won't clear when you
++ * write it back
++ */
++static inline uint32_t dwc_otg_read_hprt0(dwc_otg_core_if_t * _core_if)
++{
++ hprt0_data_t hprt0;
++ hprt0.d32 = DWC_READ_REG32(_core_if->host_if->hprt0);
++ hprt0.b.prtena = 0;
++ hprt0.b.prtconndet = 0;
++ hprt0.b.prtenchng = 0;
++ hprt0.b.prtovrcurrchng = 0;
++ return hprt0.d32;
++}
++
++/**@}*/
++
++/** @name Common CIL Functions
++ * The following functions support managing the DWC_otg controller in either
++ * device or host mode.
++ */
++/**@{*/
++
++extern void dwc_otg_read_packet(dwc_otg_core_if_t * core_if,
++ uint8_t * dest, uint16_t bytes);
++
++extern void dwc_otg_flush_tx_fifo(dwc_otg_core_if_t * _core_if, const int _num);
++extern void dwc_otg_flush_rx_fifo(dwc_otg_core_if_t * _core_if);
++extern void dwc_otg_core_reset(dwc_otg_core_if_t * _core_if);
++
++/**
++ * This function returns the Core Interrupt register.
++ */
++static inline uint32_t dwc_otg_read_core_intr(dwc_otg_core_if_t * core_if)
++{
++ return (DWC_READ_REG32(&core_if->core_global_regs->gintsts) &
++ DWC_READ_REG32(&core_if->core_global_regs->gintmsk));
++}
++
++/**
++ * This function returns the OTG Interrupt register.
++ */
++static inline uint32_t dwc_otg_read_otg_intr(dwc_otg_core_if_t * core_if)
++{
++ return (DWC_READ_REG32(&core_if->core_global_regs->gotgint));
++}
++
++/**
++ * This function reads the Device All Endpoints Interrupt register and
++ * returns the IN endpoint interrupt bits.
++ */
++static inline uint32_t dwc_otg_read_dev_all_in_ep_intr(dwc_otg_core_if_t *
++ core_if)
++{
++
++ uint32_t v;
++
++ if (core_if->multiproc_int_enable) {
++ v = DWC_READ_REG32(&core_if->dev_if->
++ dev_global_regs->deachint) &
++ DWC_READ_REG32(&core_if->
++ dev_if->dev_global_regs->deachintmsk);
++ } else {
++ v = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daint) &
++ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daintmsk);
++ }
++ return (v & 0xffff);
++}
++
++/**
++ * This function reads the Device All Endpoints Interrupt register and
++ * returns the OUT endpoint interrupt bits.
++ */
++static inline uint32_t dwc_otg_read_dev_all_out_ep_intr(dwc_otg_core_if_t *
++ core_if)
++{
++ uint32_t v;
++
++ if (core_if->multiproc_int_enable) {
++ v = DWC_READ_REG32(&core_if->dev_if->
++ dev_global_regs->deachint) &
++ DWC_READ_REG32(&core_if->
++ dev_if->dev_global_regs->deachintmsk);
++ } else {
++ v = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daint) &
++ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daintmsk);
++ }
++
++ return ((v & 0xffff0000) >> 16);
++}
++
++/**
++ * This function returns the Device IN EP Interrupt register
++ */
++static inline uint32_t dwc_otg_read_dev_in_ep_intr(dwc_otg_core_if_t * core_if,
++ dwc_ep_t * ep)
++{
++ dwc_otg_dev_if_t *dev_if = core_if->dev_if;
++ uint32_t v, msk, emp;
++
++ if (core_if->multiproc_int_enable) {
++ msk =
++ DWC_READ_REG32(&dev_if->
++ dev_global_regs->diepeachintmsk[ep->num]);
++ emp =
++ DWC_READ_REG32(&dev_if->
++ dev_global_regs->dtknqr4_fifoemptymsk);
++ msk |= ((emp >> ep->num) & 0x1) << 7;
++ v = DWC_READ_REG32(&dev_if->in_ep_regs[ep->num]->diepint) & msk;
++ } else {
++ msk = DWC_READ_REG32(&dev_if->dev_global_regs->diepmsk);
++ emp =
++ DWC_READ_REG32(&dev_if->
++ dev_global_regs->dtknqr4_fifoemptymsk);
++ msk |= ((emp >> ep->num) & 0x1) << 7;
++ v = DWC_READ_REG32(&dev_if->in_ep_regs[ep->num]->diepint) & msk;
++ }
++
++ return v;
++}
++
++/**
++ * This function returns the Device OUT EP Interrupt register
++ */
++static inline uint32_t dwc_otg_read_dev_out_ep_intr(dwc_otg_core_if_t *
++ _core_if, dwc_ep_t * _ep)
++{
++ dwc_otg_dev_if_t *dev_if = _core_if->dev_if;
++ uint32_t v;
++ doepmsk_data_t msk = {.d32 = 0 };
++
++ if (_core_if->multiproc_int_enable) {
++ msk.d32 =
++ DWC_READ_REG32(&dev_if->
++ dev_global_regs->doepeachintmsk[_ep->num]);
++ if (_core_if->pti_enh_enable) {
++ msk.b.pktdrpsts = 1;
++ }
++ v = DWC_READ_REG32(&dev_if->
++ out_ep_regs[_ep->num]->doepint) & msk.d32;
++ } else {
++ msk.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->doepmsk);
++ if (_core_if->pti_enh_enable) {
++ msk.b.pktdrpsts = 1;
++ }
++ v = DWC_READ_REG32(&dev_if->
++ out_ep_regs[_ep->num]->doepint) & msk.d32;
++ }
++ return v;
++}
++
++/**
++ * This function returns the Host All Channel Interrupt register
++ */
++static inline uint32_t dwc_otg_read_host_all_channels_intr(dwc_otg_core_if_t *
++ _core_if)
++{
++ return (DWC_READ_REG32(&_core_if->host_if->host_global_regs->haint));
++}
++
++static inline uint32_t dwc_otg_read_host_channel_intr(dwc_otg_core_if_t *
++ _core_if, dwc_hc_t * _hc)
++{
++ return (DWC_READ_REG32
++ (&_core_if->host_if->hc_regs[_hc->hc_num]->hcint));
++}
++
++/**
++ * This function returns the mode of the operation, host or device.
++ *
++ * @return 0 - Device Mode, 1 - Host Mode
++ */
++static inline uint32_t dwc_otg_mode(dwc_otg_core_if_t * _core_if)
++{
++ return (DWC_READ_REG32(&_core_if->core_global_regs->gintsts) & 0x1);
++}
++
++/**@}*/
++
++/**
++ * DWC_otg CIL callback structure. This structure allows the HCD and
++ * PCD to register functions used for starting and stopping the PCD
++ * and HCD for role change on for a DRD.
++ */
++typedef struct dwc_otg_cil_callbacks {
++ /** Start function for role change */
++ int (*start) (void *_p);
++ /** Stop Function for role change */
++ int (*stop) (void *_p);
++ /** Disconnect Function for role change */
++ int (*disconnect) (void *_p);
++ /** Resume/Remote wakeup Function */
++ int (*resume_wakeup) (void *_p);
++ /** Suspend function */
++ int (*suspend) (void *_p);
++ /** Session Start (SRP) */
++ int (*session_start) (void *_p);
++#ifdef CONFIG_USB_DWC_OTG_LPM
++ /** Sleep (switch to L0 state) */
++ int (*sleep) (void *_p);
++#endif
++ /** Pointer passed to start() and stop() */
++ void *p;
++} dwc_otg_cil_callbacks_t;
++
++extern void dwc_otg_cil_register_pcd_callbacks(dwc_otg_core_if_t * _core_if,
++ dwc_otg_cil_callbacks_t * _cb,
++ void *_p);
++extern void dwc_otg_cil_register_hcd_callbacks(dwc_otg_core_if_t * _core_if,
++ dwc_otg_cil_callbacks_t * _cb,
++ void *_p);
++
++void dwc_otg_initiate_srp(dwc_otg_core_if_t * core_if);
++
++//////////////////////////////////////////////////////////////////////
++/** Start the HCD. Helper function for using the HCD callbacks.
++ *
++ * @param core_if Programming view of DWC_otg controller.
++ */
++static inline void cil_hcd_start(dwc_otg_core_if_t * core_if)
++{
++ if (core_if->hcd_cb && core_if->hcd_cb->start) {
++ core_if->hcd_cb->start(core_if->hcd_cb->p);
++ }
++}
++
++/** Stop the HCD. Helper function for using the HCD callbacks.
++ *
++ * @param core_if Programming view of DWC_otg controller.
++ */
++static inline void cil_hcd_stop(dwc_otg_core_if_t * core_if)
++{
++ if (core_if->hcd_cb && core_if->hcd_cb->stop) {
++ core_if->hcd_cb->stop(core_if->hcd_cb->p);
++ }
++}
++
++/** Disconnect the HCD. Helper function for using the HCD callbacks.
++ *
++ * @param core_if Programming view of DWC_otg controller.
++ */
++static inline void cil_hcd_disconnect(dwc_otg_core_if_t * core_if)
++{
++ if (core_if->hcd_cb && core_if->hcd_cb->disconnect) {
++ core_if->hcd_cb->disconnect(core_if->hcd_cb->p);
++ }
++}
++
++/** Inform the HCD the a New Session has begun. Helper function for
++ * using the HCD callbacks.
++ *
++ * @param core_if Programming view of DWC_otg controller.
++ */
++static inline void cil_hcd_session_start(dwc_otg_core_if_t * core_if)
++{
++ if (core_if->hcd_cb && core_if->hcd_cb->session_start) {
++ core_if->hcd_cb->session_start(core_if->hcd_cb->p);
++ }
++}
++
++#ifdef CONFIG_USB_DWC_OTG_LPM
++/**
++ * Inform the HCD about LPM sleep.
++ * Helper function for using the HCD callbacks.
++ *
++ * @param core_if Programming view of DWC_otg controller.
++ */
++static inline void cil_hcd_sleep(dwc_otg_core_if_t * core_if)
++{
++ if (core_if->hcd_cb && core_if->hcd_cb->sleep) {
++ core_if->hcd_cb->sleep(core_if->hcd_cb->p);
++ }
++}
++#endif
++
++/** Resume the HCD. Helper function for using the HCD callbacks.
++ *
++ * @param core_if Programming view of DWC_otg controller.
++ */
++static inline void cil_hcd_resume(dwc_otg_core_if_t * core_if)
++{
++ if (core_if->hcd_cb && core_if->hcd_cb->resume_wakeup) {
++ core_if->hcd_cb->resume_wakeup(core_if->hcd_cb->p);
++ }
++}
++
++/** Start the PCD. Helper function for using the PCD callbacks.
++ *
++ * @param core_if Programming view of DWC_otg controller.
++ */
++static inline void cil_pcd_start(dwc_otg_core_if_t * core_if)
++{
++ if (core_if->pcd_cb && core_if->pcd_cb->start) {
++ core_if->pcd_cb->start(core_if->pcd_cb->p);
++ }
++}
++
++/** Stop the PCD. Helper function for using the PCD callbacks.
++ *
++ * @param core_if Programming view of DWC_otg controller.
++ */
++static inline void cil_pcd_stop(dwc_otg_core_if_t * core_if)
++{
++ if (core_if->pcd_cb && core_if->pcd_cb->stop) {
++ core_if->pcd_cb->stop(core_if->pcd_cb->p);
++ }
++}
++
++/** Suspend the PCD. Helper function for using the PCD callbacks.
++ *
++ * @param core_if Programming view of DWC_otg controller.
++ */
++static inline void cil_pcd_suspend(dwc_otg_core_if_t * core_if)
++{
++ if (core_if->pcd_cb && core_if->pcd_cb->suspend) {
++ core_if->pcd_cb->suspend(core_if->pcd_cb->p);
++ }
++}
++
++/** Resume the PCD. Helper function for using the PCD callbacks.
++ *
++ * @param core_if Programming view of DWC_otg controller.
++ */
++static inline void cil_pcd_resume(dwc_otg_core_if_t * core_if)
++{
++ if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
++ core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);
++ }
++}
++
++//////////////////////////////////////////////////////////////////////
++
++#endif
+diff -Nur linux-4.1.3/drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c linux-xbian-rpi/drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c
+--- linux-4.1.3/drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c 2015-07-28 01:20:58.445156473 +0200
+@@ -0,0 +1,1594 @@
++/* ==========================================================================
++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil_intr.c $
++ * $Revision: #32 $
++ * $Date: 2012/08/10 $
++ * $Change: 2047372 $
++ *
++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++ * otherwise expressly agreed to in writing between Synopsys and you.
++ *
++ * The Software IS NOT an item of Licensed Software or Licensed Product under
++ * any End User Software License Agreement or Agreement for Licensed Product
++ * with Synopsys or any supplement thereto. You are permitted to use and
++ * redistribute this Software in source and binary forms, with or without
++ * modification, provided that redistributions of source code must retain this
++ * notice. You may not view, use, disclose, copy or distribute this file or
++ * any information contained herein except pursuant to this license grant from
++ * Synopsys. If you do not agree with this notice, including the disclaimer
++ * below, then you are not authorized to use the Software.
++ *
++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++ * DAMAGE.
++ * ========================================================================== */
++
++/** @file
++ *
++ * The Core Interface Layer provides basic services for accessing and
++ * managing the DWC_otg hardware. These services are used by both the
++ * Host Controller Driver and the Peripheral Controller Driver.
++ *
++ * This file contains the Common Interrupt handlers.
++ */
++#include "dwc_os.h"
++#include "dwc_otg_regs.h"
++#include "dwc_otg_cil.h"
++#include "dwc_otg_driver.h"
++#include "dwc_otg_pcd.h"
++#include "dwc_otg_hcd.h"
++
++#ifdef DEBUG
++inline const char *op_state_str(dwc_otg_core_if_t * core_if)
++{
++ return (core_if->op_state == A_HOST ? "a_host" :
++ (core_if->op_state == A_SUSPEND ? "a_suspend" :
++ (core_if->op_state == A_PERIPHERAL ? "a_peripheral" :
++ (core_if->op_state == B_PERIPHERAL ? "b_peripheral" :
++ (core_if->op_state == B_HOST ? "b_host" : "unknown")))));
++}
++#endif
++
++/** This function will log a debug message
++ *
++ * @param core_if Programming view of DWC_otg controller.
++ */
++int32_t dwc_otg_handle_mode_mismatch_intr(dwc_otg_core_if_t * core_if)
++{
++ gintsts_data_t gintsts;
++ DWC_WARN("Mode Mismatch Interrupt: currently in %s mode\n",
++ dwc_otg_mode(core_if) ? "Host" : "Device");
++
++ /* Clear interrupt */
++ gintsts.d32 = 0;
++ gintsts.b.modemismatch = 1;
++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
++ return 1;
++}
++
++/**
++ * This function handles the OTG Interrupts. It reads the OTG
++ * Interrupt Register (GOTGINT) to determine what interrupt has
++ * occurred.
++ *
++ * @param core_if Programming view of DWC_otg controller.
++ */
++int32_t dwc_otg_handle_otg_intr(dwc_otg_core_if_t * core_if)
++{
++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
++ gotgint_data_t gotgint;
++ gotgctl_data_t gotgctl;
++ gintmsk_data_t gintmsk;
++ gpwrdn_data_t gpwrdn;
++
++ gotgint.d32 = DWC_READ_REG32(&global_regs->gotgint);
++ gotgctl.d32 = DWC_READ_REG32(&global_regs->gotgctl);
++ DWC_DEBUGPL(DBG_CIL, "++OTG Interrupt gotgint=%0x [%s]\n", gotgint.d32,
++ op_state_str(core_if));
++
++ if (gotgint.b.sesenddet) {
++ DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
++ "Session End Detected++ (%s)\n",
++ op_state_str(core_if));
++ gotgctl.d32 = DWC_READ_REG32(&global_regs->gotgctl);
++
++ if (core_if->op_state == B_HOST) {
++ cil_pcd_start(core_if);
++ core_if->op_state = B_PERIPHERAL;
++ } else {
++ /* If not B_HOST and Device HNP still set. HNP
++ * Did not succeed!*/
++ if (gotgctl.b.devhnpen) {
++ DWC_DEBUGPL(DBG_ANY, "Session End Detected\n");
++ __DWC_ERROR("Device Not Connected/Responding!\n");
++ }
++
++ /* If Session End Detected the B-Cable has
++ * been disconnected. */
++ /* Reset PCD and Gadget driver to a
++ * clean state. */
++ core_if->lx_state = DWC_OTG_L0;
++ DWC_SPINUNLOCK(core_if->lock);
++ cil_pcd_stop(core_if);
++ DWC_SPINLOCK(core_if->lock);
++
++ if (core_if->adp_enable) {
++ if (core_if->power_down == 2) {
++ gpwrdn.d32 = 0;
++ gpwrdn.b.pwrdnswtch = 1;
++ DWC_MODIFY_REG32(&core_if->
++ core_global_regs->
++ gpwrdn, gpwrdn.d32, 0);
++ }
++
++ gpwrdn.d32 = 0;
++ gpwrdn.b.pmuintsel = 1;
++ gpwrdn.b.pmuactv = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->
++ gpwrdn, 0, gpwrdn.d32);
++
++ dwc_otg_adp_sense_start(core_if);
++ }
++ }
++
++ gotgctl.d32 = 0;
++ gotgctl.b.devhnpen = 1;
++ DWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0);
++ }
++ if (gotgint.b.sesreqsucstschng) {
++ DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
++ "Session Reqeust Success Status Change++\n");
++ gotgctl.d32 = DWC_READ_REG32(&global_regs->gotgctl);
++ if (gotgctl.b.sesreqscs) {
++
++ if ((core_if->core_params->phy_type ==
++ DWC_PHY_TYPE_PARAM_FS) && (core_if->core_params->i2c_enable)) {
++ core_if->srp_success = 1;
++ } else {
++ DWC_SPINUNLOCK(core_if->lock);
++ cil_pcd_resume(core_if);
++ DWC_SPINLOCK(core_if->lock);
++ /* Clear Session Request */
++ gotgctl.d32 = 0;
++ gotgctl.b.sesreq = 1;
++ DWC_MODIFY_REG32(&global_regs->gotgctl,
++ gotgctl.d32, 0);
++ }
++ }
++ }
++ if (gotgint.b.hstnegsucstschng) {
++ /* Print statements during the HNP interrupt handling
++ * can cause it to fail.*/
++ gotgctl.d32 = DWC_READ_REG32(&global_regs->gotgctl);
++ /* WA for 3.00a- HW is not setting cur_mode, even sometimes
++ * this does not help*/
++ if (core_if->snpsid >= OTG_CORE_REV_3_00a)
++ dwc_udelay(100);
++ if (gotgctl.b.hstnegscs) {
++ if (dwc_otg_is_host_mode(core_if)) {
++ core_if->op_state = B_HOST;
++ /*
++ * Need to disable SOF interrupt immediately.
++ * When switching from device to host, the PCD
++ * interrupt handler won't handle the
++ * interrupt if host mode is already set. The
++ * HCD interrupt handler won't get called if
++ * the HCD state is HALT. This means that the
++ * interrupt does not get handled and Linux
++ * complains loudly.
++ */
++ gintmsk.d32 = 0;
++ gintmsk.b.sofintr = 1;
++ DWC_MODIFY_REG32(&global_regs->gintmsk,
++ gintmsk.d32, 0);
++ /* Call callback function with spin lock released */
++ DWC_SPINUNLOCK(core_if->lock);
++ cil_pcd_stop(core_if);
++ /*
++ * Initialize the Core for Host mode.
++ */
++ cil_hcd_start(core_if);
++ DWC_SPINLOCK(core_if->lock);
++ core_if->op_state = B_HOST;
++ }
++ } else {
++ gotgctl.d32 = 0;
++ gotgctl.b.hnpreq = 1;
++ gotgctl.b.devhnpen = 1;
++ DWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0);
++ DWC_DEBUGPL(DBG_ANY, "HNP Failed\n");
++ __DWC_ERROR("Device Not Connected/Responding\n");
++ }
++ }
++ if (gotgint.b.hstnegdet) {
++ /* The disconnect interrupt is set at the same time as
++ * Host Negotiation Detected. During the mode
++ * switch all interrupts are cleared so the disconnect
++ * interrupt handler will not get executed.
++ */
++ DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
++ "Host Negotiation Detected++ (%s)\n",
++ (dwc_otg_is_host_mode(core_if) ? "Host" :
++ "Device"));
++ if (dwc_otg_is_device_mode(core_if)) {
++ DWC_DEBUGPL(DBG_ANY, "a_suspend->a_peripheral (%d)\n",
++ core_if->op_state);
++ DWC_SPINUNLOCK(core_if->lock);
++ cil_hcd_disconnect(core_if);
++ cil_pcd_start(core_if);
++ DWC_SPINLOCK(core_if->lock);
++ core_if->op_state = A_PERIPHERAL;
++ } else {
++ /*
++ * Need to disable SOF interrupt immediately. When
++ * switching from device to host, the PCD interrupt
++ * handler won't handle the interrupt if host mode is
++ * already set. The HCD interrupt handler won't get
++ * called if the HCD state is HALT. This means that
++ * the interrupt does not get handled and Linux
++ * complains loudly.
++ */
++ gintmsk.d32 = 0;
++ gintmsk.b.sofintr = 1;
++ DWC_MODIFY_REG32(&global_regs->gintmsk, gintmsk.d32, 0);
++ DWC_SPINUNLOCK(core_if->lock);
++ cil_pcd_stop(core_if);
++ cil_hcd_start(core_if);
++ DWC_SPINLOCK(core_if->lock);
++ core_if->op_state = A_HOST;
++ }
++ }
++ if (gotgint.b.adevtoutchng) {
++ DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
++ "A-Device Timeout Change++\n");
++ }
++ if (gotgint.b.debdone) {
++ DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: " "Debounce Done++\n");
++ }
++
++ /* Clear GOTGINT */
++ DWC_WRITE_REG32(&core_if->core_global_regs->gotgint, gotgint.d32);
++
++ return 1;
++}
++
++void w_conn_id_status_change(void *p)
++{
++ dwc_otg_core_if_t *core_if = p;
++ uint32_t count = 0;
++ gotgctl_data_t gotgctl = {.d32 = 0 };
++
++ gotgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
++ DWC_DEBUGPL(DBG_CIL, "gotgctl=%0x\n", gotgctl.d32);
++ DWC_DEBUGPL(DBG_CIL, "gotgctl.b.conidsts=%d\n", gotgctl.b.conidsts);
++
++ /* B-Device connector (Device Mode) */
++ if (gotgctl.b.conidsts) {
++ /* Wait for switch to device mode. */
++ while (!dwc_otg_is_device_mode(core_if)) {
++ DWC_PRINTF("Waiting for Peripheral Mode, Mode=%s\n",
++ (dwc_otg_is_host_mode(core_if) ? "Host" :
++ "Peripheral"));
++ dwc_mdelay(100);
++ if (++count > 10000)
++ break;
++ }
++ DWC_ASSERT(++count < 10000,
++ "Connection id status change timed out");
++ core_if->op_state = B_PERIPHERAL;
++ dwc_otg_core_init(core_if);
++ dwc_otg_enable_global_interrupts(core_if);
++ cil_pcd_start(core_if);
++ } else {
++ /* A-Device connector (Host Mode) */
++ while (!dwc_otg_is_host_mode(core_if)) {
++ DWC_PRINTF("Waiting for Host Mode, Mode=%s\n",
++ (dwc_otg_is_host_mode(core_if) ? "Host" :
++ "Peripheral"));
++ dwc_mdelay(100);
++ if (++count > 10000)
++ break;
++ }
++ DWC_ASSERT(++count < 10000,
++ "Connection id status change timed out");
++ core_if->op_state = A_HOST;
++ /*
++ * Initialize the Core for Host mode.
++ */
++ dwc_otg_core_init(core_if);
++ dwc_otg_enable_global_interrupts(core_if);
++ cil_hcd_start(core_if);
++ }
++}
++
++/**
++ * This function handles the Connector ID Status Change Interrupt. It
++ * reads the OTG Interrupt Register (GOTCTL) to determine whether this
++ * is a Device to Host Mode transition or a Host Mode to Device
++ * Transition.
++ *
++ * This only occurs when the cable is connected/removed from the PHY
++ * connector.
++ *
++ * @param core_if Programming view of DWC_otg controller.
++ */
++int32_t dwc_otg_handle_conn_id_status_change_intr(dwc_otg_core_if_t * core_if)
++{
++
++ /*
++ * Need to disable SOF interrupt immediately. If switching from device
++ * to host, the PCD interrupt handler won't handle the interrupt if
++ * host mode is already set. The HCD interrupt handler won't get
++ * called if the HCD state is HALT. This means that the interrupt does
++ * not get handled and Linux complains loudly.
++ */
++ gintmsk_data_t gintmsk = {.d32 = 0 };
++ gintsts_data_t gintsts = {.d32 = 0 };
++
++ gintmsk.b.sofintr = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
++
++ DWC_DEBUGPL(DBG_CIL,
++ " ++Connector ID Status Change Interrupt++ (%s)\n",
++ (dwc_otg_is_host_mode(core_if) ? "Host" : "Device"));
++
++ DWC_SPINUNLOCK(core_if->lock);
++
++ /*
++ * Need to schedule a work, as there are possible DELAY function calls
++ * Release lock before scheduling workq as it holds spinlock during scheduling
++ */
++
++ DWC_WORKQ_SCHEDULE(core_if->wq_otg, w_conn_id_status_change,
++ core_if, "connection id status change");
++ DWC_SPINLOCK(core_if->lock);
++
++ /* Set flag and clear interrupt */
++ gintsts.b.conidstschng = 1;
++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
++
++ return 1;
++}
++
++/**
++ * This interrupt indicates that a device is initiating the Session
++ * Request Protocol to request the host to turn on bus power so a new
++ * session can begin. The handler responds by turning on bus power. If
++ * the DWC_otg controller is in low power mode, the handler brings the
++ * controller out of low power mode before turning on bus power.
++ *
++ * @param core_if Programming view of DWC_otg controller.
++ */
++int32_t dwc_otg_handle_session_req_intr(dwc_otg_core_if_t * core_if)
++{
++ gintsts_data_t gintsts;
++
++#ifndef DWC_HOST_ONLY
++ DWC_DEBUGPL(DBG_ANY, "++Session Request Interrupt++\n");
++
++ if (dwc_otg_is_device_mode(core_if)) {
++ DWC_PRINTF("SRP: Device mode\n");
++ } else {
++ hprt0_data_t hprt0;
++ DWC_PRINTF("SRP: Host mode\n");
++
++ /* Turn on the port power bit. */
++ hprt0.d32 = dwc_otg_read_hprt0(core_if);
++ hprt0.b.prtpwr = 1;
++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
++
++ /* Start the Connection timer. So a message can be displayed
++ * if connect does not occur within 10 seconds. */
++ cil_hcd_session_start(core_if);
++ }
++#endif
++
++ /* Clear interrupt */
++ gintsts.d32 = 0;
++ gintsts.b.sessreqintr = 1;
++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
++
++ return 1;
++}
++
++void w_wakeup_detected(void *p)
++{
++ dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) p;
++ /*
++ * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
++ * so that OPT tests pass with all PHYs).
++ */
++ hprt0_data_t hprt0 = {.d32 = 0 };
++#if 0
++ pcgcctl_data_t pcgcctl = {.d32 = 0 };
++ /* Restart the Phy Clock */
++ pcgcctl.b.stoppclk = 1;
++ DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
++ dwc_udelay(10);
++#endif //0
++ hprt0.d32 = dwc_otg_read_hprt0(core_if);
++ DWC_DEBUGPL(DBG_ANY, "Resume: HPRT0=%0x\n", hprt0.d32);
++// dwc_mdelay(70);
++ hprt0.b.prtres = 0; /* Resume */
++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
++ DWC_DEBUGPL(DBG_ANY, "Clear Resume: HPRT0=%0x\n",
++ DWC_READ_REG32(core_if->host_if->hprt0));
++
++ cil_hcd_resume(core_if);
++
++ /** Change to L0 state*/
++ core_if->lx_state = DWC_OTG_L0;
++}
++
++/**
++ * This interrupt indicates that the DWC_otg controller has detected a
++ * resume or remote wakeup sequence. If the DWC_otg controller is in
++ * low power mode, the handler must brings the controller out of low
++ * power mode. The controller automatically begins resume
++ * signaling. The handler schedules a time to stop resume signaling.
++ */
++int32_t dwc_otg_handle_wakeup_detected_intr(dwc_otg_core_if_t * core_if)
++{
++ gintsts_data_t gintsts;
++
++ DWC_DEBUGPL(DBG_ANY,
++ "++Resume and Remote Wakeup Detected Interrupt++\n");
++
++ DWC_PRINTF("%s lxstate = %d\n", __func__, core_if->lx_state);
++
++ if (dwc_otg_is_device_mode(core_if)) {
++ dctl_data_t dctl = {.d32 = 0 };
++ DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n",
++ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->
++ dsts));
++ if (core_if->lx_state == DWC_OTG_L2) {
++#ifdef PARTIAL_POWER_DOWN
++ if (core_if->hwcfg4.b.power_optimiz) {
++ pcgcctl_data_t power = {.d32 = 0 };
++
++ power.d32 = DWC_READ_REG32(core_if->pcgcctl);
++ DWC_DEBUGPL(DBG_CIL, "PCGCCTL=%0x\n",
++ power.d32);
++
++ power.b.stoppclk = 0;
++ DWC_WRITE_REG32(core_if->pcgcctl, power.d32);
++
++ power.b.pwrclmp = 0;
++ DWC_WRITE_REG32(core_if->pcgcctl, power.d32);
++
++ power.b.rstpdwnmodule = 0;
++ DWC_WRITE_REG32(core_if->pcgcctl, power.d32);
++ }
++#endif
++ /* Clear the Remote Wakeup Signaling */
++ dctl.b.rmtwkupsig = 1;
++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
++ dctl, dctl.d32, 0);
++
++ DWC_SPINUNLOCK(core_if->lock);
++ if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
++ core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);
++ }
++ DWC_SPINLOCK(core_if->lock);
++ } else {
++ glpmcfg_data_t lpmcfg;
++ lpmcfg.d32 =
++ DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
++ lpmcfg.b.hird_thres &= (~(1 << 4));
++ DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg,
++ lpmcfg.d32);
++ }
++ /** Change to L0 state*/
++ core_if->lx_state = DWC_OTG_L0;
++ } else {
++ if (core_if->lx_state != DWC_OTG_L1) {
++ pcgcctl_data_t pcgcctl = {.d32 = 0 };
++
++ /* Restart the Phy Clock */
++ pcgcctl.b.stoppclk = 1;
++ DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
++ DWC_TIMER_SCHEDULE(core_if->wkp_timer, 71);
++ } else {
++ /** Change to L0 state*/
++ core_if->lx_state = DWC_OTG_L0;
++ }
++ }
++
++ /* Clear interrupt */
++ gintsts.d32 = 0;
++ gintsts.b.wkupintr = 1;
++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
++
++ return 1;
++}
++
++/**
++ * This interrupt indicates that the Wakeup Logic has detected a
++ * Device disconnect.
++ */
++static int32_t dwc_otg_handle_pwrdn_disconnect_intr(dwc_otg_core_if_t *core_if)
++{
++ gpwrdn_data_t gpwrdn = { .d32 = 0 };
++ gpwrdn_data_t gpwrdn_temp = { .d32 = 0 };
++ gpwrdn_temp.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
++
++ DWC_PRINTF("%s called\n", __FUNCTION__);
++
++ if (!core_if->hibernation_suspend) {
++ DWC_PRINTF("Already exited from Hibernation\n");
++ return 1;
++ }
++
++ /* Switch on the voltage to the core */
++ gpwrdn.b.pwrdnswtch = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++ dwc_udelay(10);
++
++ /* Reset the core */
++ gpwrdn.d32 = 0;
++ gpwrdn.b.pwrdnrstn = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++ dwc_udelay(10);
++
++ /* Disable power clamps*/
++ gpwrdn.d32 = 0;
++ gpwrdn.b.pwrdnclmp = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++
++ /* Remove reset the core signal */
++ gpwrdn.d32 = 0;
++ gpwrdn.b.pwrdnrstn = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
++ dwc_udelay(10);
++
++ /* Disable PMU interrupt */
++ gpwrdn.d32 = 0;
++ gpwrdn.b.pmuintsel = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++
++ core_if->hibernation_suspend = 0;
++
++ /* Disable PMU */
++ gpwrdn.d32 = 0;
++ gpwrdn.b.pmuactv = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++ dwc_udelay(10);
++
++ if (gpwrdn_temp.b.idsts) {
++ core_if->op_state = B_PERIPHERAL;
++ dwc_otg_core_init(core_if);
++ dwc_otg_enable_global_interrupts(core_if);
++ cil_pcd_start(core_if);
++ } else {
++ core_if->op_state = A_HOST;
++ dwc_otg_core_init(core_if);
++ dwc_otg_enable_global_interrupts(core_if);
++ cil_hcd_start(core_if);
++ }
++
++ return 1;
++}
++
++/**
++ * This interrupt indicates that the Wakeup Logic has detected a
++ * remote wakeup sequence.
++ */
++static int32_t dwc_otg_handle_pwrdn_wakeup_detected_intr(dwc_otg_core_if_t * core_if)
++{
++ gpwrdn_data_t gpwrdn = {.d32 = 0 };
++ DWC_DEBUGPL(DBG_ANY,
++ "++Powerdown Remote Wakeup Detected Interrupt++\n");
++
++ if (!core_if->hibernation_suspend) {
++ DWC_PRINTF("Already exited from Hibernation\n");
++ return 1;
++ }
++
++ gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
++ if (gpwrdn.b.idsts) { // Device Mode
++ if ((core_if->power_down == 2)
++ && (core_if->hibernation_suspend == 1)) {
++ dwc_otg_device_hibernation_restore(core_if, 0, 0);
++ }
++ } else {
++ if ((core_if->power_down == 2)
++ && (core_if->hibernation_suspend == 1)) {
++ dwc_otg_host_hibernation_restore(core_if, 1, 0);
++ }
++ }
++ return 1;
++}
++
++static int32_t dwc_otg_handle_pwrdn_idsts_change(dwc_otg_device_t *otg_dev)
++{
++ gpwrdn_data_t gpwrdn = {.d32 = 0 };
++ gpwrdn_data_t gpwrdn_temp = {.d32 = 0 };
++ dwc_otg_core_if_t *core_if = otg_dev->core_if;
++
++ DWC_DEBUGPL(DBG_ANY, "%s called\n", __FUNCTION__);
++ gpwrdn_temp.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
++ if (core_if->power_down == 2) {
++ if (!core_if->hibernation_suspend) {
++ DWC_PRINTF("Already exited from Hibernation\n");
++ return 1;
++ }
++ DWC_DEBUGPL(DBG_ANY, "Exit from hibernation on ID sts change\n");
++ /* Switch on the voltage to the core */
++ gpwrdn.b.pwrdnswtch = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++ dwc_udelay(10);
++
++ /* Reset the core */
++ gpwrdn.d32 = 0;
++ gpwrdn.b.pwrdnrstn = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++ dwc_udelay(10);
++
++ /* Disable power clamps */
++ gpwrdn.d32 = 0;
++ gpwrdn.b.pwrdnclmp = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++
++ /* Remove reset the core signal */
++ gpwrdn.d32 = 0;
++ gpwrdn.b.pwrdnrstn = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
++ dwc_udelay(10);
++
++ /* Disable PMU interrupt */
++ gpwrdn.d32 = 0;
++ gpwrdn.b.pmuintsel = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++
++ /*Indicates that we are exiting from hibernation */
++ core_if->hibernation_suspend = 0;
++
++ /* Disable PMU */
++ gpwrdn.d32 = 0;
++ gpwrdn.b.pmuactv = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++ dwc_udelay(10);
++
++ gpwrdn.d32 = core_if->gr_backup->gpwrdn_local;
++ if (gpwrdn.b.dis_vbus == 1) {
++ gpwrdn.d32 = 0;
++ gpwrdn.b.dis_vbus = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++ }
++
++ if (gpwrdn_temp.b.idsts) {
++ core_if->op_state = B_PERIPHERAL;
++ dwc_otg_core_init(core_if);
++ dwc_otg_enable_global_interrupts(core_if);
++ cil_pcd_start(core_if);
++ } else {
++ core_if->op_state = A_HOST;
++ dwc_otg_core_init(core_if);
++ dwc_otg_enable_global_interrupts(core_if);
++ cil_hcd_start(core_if);
++ }
++ }
++
++ if (core_if->adp_enable) {
++ uint8_t is_host = 0;
++ DWC_SPINUNLOCK(core_if->lock);
++ /* Change the core_if's lock to hcd/pcd lock depend on mode? */
++#ifndef DWC_HOST_ONLY
++ if (gpwrdn_temp.b.idsts)
++ core_if->lock = otg_dev->pcd->lock;
++#endif
++#ifndef DWC_DEVICE_ONLY
++ if (!gpwrdn_temp.b.idsts) {
++ core_if->lock = otg_dev->hcd->lock;
++ is_host = 1;
++ }
++#endif
++ DWC_PRINTF("RESTART ADP\n");
++ if (core_if->adp.probe_enabled)
++ dwc_otg_adp_probe_stop(core_if);
++ if (core_if->adp.sense_enabled)
++ dwc_otg_adp_sense_stop(core_if);
++ if (core_if->adp.sense_timer_started)
++ DWC_TIMER_CANCEL(core_if->adp.sense_timer);
++ if (core_if->adp.vbuson_timer_started)
++ DWC_TIMER_CANCEL(core_if->adp.vbuson_timer);
++ core_if->adp.probe_timer_values[0] = -1;
++ core_if->adp.probe_timer_values[1] = -1;
++ core_if->adp.sense_timer_started = 0;
++ core_if->adp.vbuson_timer_started = 0;
++ core_if->adp.probe_counter = 0;
++ core_if->adp.gpwrdn = 0;
++
++ /* Disable PMU and restart ADP */
++ gpwrdn_temp.d32 = 0;
++ gpwrdn_temp.b.pmuactv = 1;
++ gpwrdn_temp.b.pmuintsel = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++ DWC_PRINTF("Check point 1\n");
++ dwc_mdelay(110);
++ dwc_otg_adp_start(core_if, is_host);
++ DWC_SPINLOCK(core_if->lock);
++ }
++
++
++ return 1;
++}
++
++static int32_t dwc_otg_handle_pwrdn_session_change(dwc_otg_core_if_t * core_if)
++{
++ gpwrdn_data_t gpwrdn = {.d32 = 0 };
++ int32_t otg_cap_param = core_if->core_params->otg_cap;
++ DWC_DEBUGPL(DBG_ANY, "%s called\n", __FUNCTION__);
++
++ gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
++ if (core_if->power_down == 2) {
++ if (!core_if->hibernation_suspend) {
++ DWC_PRINTF("Already exited from Hibernation\n");
++ return 1;
++ }
++
++ if ((otg_cap_param != DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE ||
++ otg_cap_param != DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE) &&
++ gpwrdn.b.bsessvld == 0) {
++ /* Save gpwrdn register for further usage if stschng interrupt */
++ core_if->gr_backup->gpwrdn_local =
++ DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
++ /*Exit from ISR and wait for stschng interrupt with bsessvld = 1 */
++ return 1;
++ }
++
++ /* Switch on the voltage to the core */
++ gpwrdn.d32 = 0;
++ gpwrdn.b.pwrdnswtch = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++ dwc_udelay(10);
++
++ /* Reset the core */
++ gpwrdn.d32 = 0;
++ gpwrdn.b.pwrdnrstn = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++ dwc_udelay(10);
++
++ /* Disable power clamps */
++ gpwrdn.d32 = 0;
++ gpwrdn.b.pwrdnclmp = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++
++ /* Remove reset the core signal */
++ gpwrdn.d32 = 0;
++ gpwrdn.b.pwrdnrstn = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
++ dwc_udelay(10);
++
++ /* Disable PMU interrupt */
++ gpwrdn.d32 = 0;
++ gpwrdn.b.pmuintsel = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++ dwc_udelay(10);
++
++ /*Indicates that we are exiting from hibernation */
++ core_if->hibernation_suspend = 0;
++
++ /* Disable PMU */
++ gpwrdn.d32 = 0;
++ gpwrdn.b.pmuactv = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++ dwc_udelay(10);
++
++ core_if->op_state = B_PERIPHERAL;
++ dwc_otg_core_init(core_if);
++ dwc_otg_enable_global_interrupts(core_if);
++ cil_pcd_start(core_if);
++
++ if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE ||
++ otg_cap_param == DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE) {
++ /*
++ * Initiate SRP after initial ADP probe.
++ */
++ dwc_otg_initiate_srp(core_if);
++ }
++ }
++
++ return 1;
++}
++/**
++ * This interrupt indicates that the Wakeup Logic has detected a
++ * status change either on IDDIG or BSessVld.
++ */
++static uint32_t dwc_otg_handle_pwrdn_stschng_intr(dwc_otg_device_t *otg_dev)
++{
++ int retval;
++ gpwrdn_data_t gpwrdn = {.d32 = 0 };
++ gpwrdn_data_t gpwrdn_temp = {.d32 = 0 };
++ dwc_otg_core_if_t *core_if = otg_dev->core_if;
++
++ DWC_PRINTF("%s called\n", __FUNCTION__);
++
++ if (core_if->power_down == 2) {
++ if (core_if->hibernation_suspend <= 0) {
++ DWC_PRINTF("Already exited from Hibernation\n");
++ return 1;
++ } else
++ gpwrdn_temp.d32 = core_if->gr_backup->gpwrdn_local;
++
++ } else {
++ gpwrdn_temp.d32 = core_if->adp.gpwrdn;
++ }
++
++ gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
++
++ if (gpwrdn.b.idsts ^ gpwrdn_temp.b.idsts) {
++ retval = dwc_otg_handle_pwrdn_idsts_change(otg_dev);
++ } else if (gpwrdn.b.bsessvld ^ gpwrdn_temp.b.bsessvld) {
++ retval = dwc_otg_handle_pwrdn_session_change(core_if);
++ }
++
++ return retval;
++}
++
++/**
++ * This interrupt indicates that the Wakeup Logic has detected a
++ * SRP.
++ */
++static int32_t dwc_otg_handle_pwrdn_srp_intr(dwc_otg_core_if_t * core_if)
++{
++ gpwrdn_data_t gpwrdn = {.d32 = 0 };
++
++ DWC_PRINTF("%s called\n", __FUNCTION__);
++
++ if (!core_if->hibernation_suspend) {
++ DWC_PRINTF("Already exited from Hibernation\n");
++ return 1;
++ }
++#ifdef DWC_DEV_SRPCAP
++ if (core_if->pwron_timer_started) {
++ core_if->pwron_timer_started = 0;
++ DWC_TIMER_CANCEL(core_if->pwron_timer);
++ }
++#endif
++
++ /* Switch on the voltage to the core */
++ gpwrdn.b.pwrdnswtch = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++ dwc_udelay(10);
++
++ /* Reset the core */
++ gpwrdn.d32 = 0;
++ gpwrdn.b.pwrdnrstn = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++ dwc_udelay(10);
++
++ /* Disable power clamps */
++ gpwrdn.d32 = 0;
++ gpwrdn.b.pwrdnclmp = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++
++ /* Remove reset the core signal */
++ gpwrdn.d32 = 0;
++ gpwrdn.b.pwrdnrstn = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
++ dwc_udelay(10);
++
++ /* Disable PMU interrupt */
++ gpwrdn.d32 = 0;
++ gpwrdn.b.pmuintsel = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++
++ /* Indicates that we are exiting from hibernation */
++ core_if->hibernation_suspend = 0;
++
++ /* Disable PMU */
++ gpwrdn.d32 = 0;
++ gpwrdn.b.pmuactv = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++ dwc_udelay(10);
++
++ /* Programm Disable VBUS to 0 */
++ gpwrdn.d32 = 0;
++ gpwrdn.b.dis_vbus = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++
++ /*Initialize the core as Host */
++ core_if->op_state = A_HOST;
++ dwc_otg_core_init(core_if);
++ dwc_otg_enable_global_interrupts(core_if);
++ cil_hcd_start(core_if);
++
++ return 1;
++}
++
++/** This interrupt indicates that restore command after Hibernation
++ * was completed by the core. */
++int32_t dwc_otg_handle_restore_done_intr(dwc_otg_core_if_t * core_if)
++{
++ pcgcctl_data_t pcgcctl;
++ DWC_DEBUGPL(DBG_ANY, "++Restore Done Interrupt++\n");
++
++ //TODO De-assert restore signal. 8.a
++ pcgcctl.d32 = DWC_READ_REG32(core_if->pcgcctl);
++ if (pcgcctl.b.restoremode == 1) {
++ gintmsk_data_t gintmsk = {.d32 = 0 };
++ /*
++ * If restore mode is Remote Wakeup,
++ * unmask Remote Wakeup interrupt.
++ */
++ gintmsk.b.wkupintr = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk,
++ 0, gintmsk.d32);
++ }
++
++ return 1;
++}
++
++/**
++ * This interrupt indicates that a device has been disconnected from
++ * the root port.
++ */
++int32_t dwc_otg_handle_disconnect_intr(dwc_otg_core_if_t * core_if)
++{
++ gintsts_data_t gintsts;
++
++ DWC_DEBUGPL(DBG_ANY, "++Disconnect Detected Interrupt++ (%s) %s\n",
++ (dwc_otg_is_host_mode(core_if) ? "Host" : "Device"),
++ op_state_str(core_if));
++
++/** @todo Consolidate this if statement. */
++#ifndef DWC_HOST_ONLY
++ if (core_if->op_state == B_HOST) {
++ /* If in device mode Disconnect and stop the HCD, then
++ * start the PCD. */
++ DWC_SPINUNLOCK(core_if->lock);
++ cil_hcd_disconnect(core_if);
++ cil_pcd_start(core_if);
++ DWC_SPINLOCK(core_if->lock);
++ core_if->op_state = B_PERIPHERAL;
++ } else if (dwc_otg_is_device_mode(core_if)) {
++ gotgctl_data_t gotgctl = {.d32 = 0 };
++ gotgctl.d32 =
++ DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
++ if (gotgctl.b.hstsethnpen == 1) {
++ /* Do nothing, if HNP in process the OTG
++ * interrupt "Host Negotiation Detected"
++ * interrupt will do the mode switch.
++ */
++ } else if (gotgctl.b.devhnpen == 0) {
++ /* If in device mode Disconnect and stop the HCD, then
++ * start the PCD. */
++ DWC_SPINUNLOCK(core_if->lock);
++ cil_hcd_disconnect(core_if);
++ cil_pcd_start(core_if);
++ DWC_SPINLOCK(core_if->lock);
++ core_if->op_state = B_PERIPHERAL;
++ } else {
++ DWC_DEBUGPL(DBG_ANY, "!a_peripheral && !devhnpen\n");
++ }
++ } else {
++ if (core_if->op_state == A_HOST) {
++ /* A-Cable still connected but device disconnected. */
++ cil_hcd_disconnect(core_if);
++ if (core_if->adp_enable) {
++ gpwrdn_data_t gpwrdn = { .d32 = 0 };
++ cil_hcd_stop(core_if);
++ /* Enable Power Down Logic */
++ gpwrdn.b.pmuintsel = 1;
++ gpwrdn.b.pmuactv = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->
++ gpwrdn, 0, gpwrdn.d32);
++ dwc_otg_adp_probe_start(core_if);
++
++ /* Power off the core */
++ if (core_if->power_down == 2) {
++ gpwrdn.d32 = 0;
++ gpwrdn.b.pwrdnswtch = 1;
++ DWC_MODIFY_REG32
++ (&core_if->core_global_regs->gpwrdn,
++ gpwrdn.d32, 0);
++ }
++ }
++ }
++ }
++#endif
++ /* Change to L3(OFF) state */
++ core_if->lx_state = DWC_OTG_L3;
++
++ gintsts.d32 = 0;
++ gintsts.b.disconnect = 1;
++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
++ return 1;
++}
++
++/**
++ * This interrupt indicates that SUSPEND state has been detected on
++ * the USB.
++ *
++ * For HNP the USB Suspend interrupt signals the change from
++ * "a_peripheral" to "a_host".
++ *
++ * When power management is enabled the core will be put in low power
++ * mode.
++ */
++int32_t dwc_otg_handle_usb_suspend_intr(dwc_otg_core_if_t * core_if)
++{
++ dsts_data_t dsts;
++ gintsts_data_t gintsts;
++ dcfg_data_t dcfg;
++
++ DWC_DEBUGPL(DBG_ANY, "USB SUSPEND\n");
++
++ if (dwc_otg_is_device_mode(core_if)) {
++ /* Check the Device status register to determine if the Suspend
++ * state is active. */
++ dsts.d32 =
++ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
++ DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n", dsts.d32);
++ DWC_DEBUGPL(DBG_PCD, "DSTS.Suspend Status=%d "
++ "HWCFG4.power Optimize=%d\n",
++ dsts.b.suspsts, core_if->hwcfg4.b.power_optimiz);
++
++#ifdef PARTIAL_POWER_DOWN
++/** @todo Add a module parameter for power management. */
++
++ if (dsts.b.suspsts && core_if->hwcfg4.b.power_optimiz) {
++ pcgcctl_data_t power = {.d32 = 0 };
++ DWC_DEBUGPL(DBG_CIL, "suspend\n");
++
++ power.b.pwrclmp = 1;
++ DWC_WRITE_REG32(core_if->pcgcctl, power.d32);
++
++ power.b.rstpdwnmodule = 1;
++ DWC_MODIFY_REG32(core_if->pcgcctl, 0, power.d32);
++
++ power.b.stoppclk = 1;
++ DWC_MODIFY_REG32(core_if->pcgcctl, 0, power.d32);
++
++ } else {
++ DWC_DEBUGPL(DBG_ANY, "disconnect?\n");
++ }
++#endif
++ /* PCD callback for suspend. Release the lock inside of callback function */
++ cil_pcd_suspend(core_if);
++ if (core_if->power_down == 2)
++ {
++ dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
++ DWC_DEBUGPL(DBG_ANY,"lx_state = %08x\n",core_if->lx_state);
++ DWC_DEBUGPL(DBG_ANY," device address = %08d\n",dcfg.b.devaddr);
++
++ if (core_if->lx_state != DWC_OTG_L3 && dcfg.b.devaddr) {
++ pcgcctl_data_t pcgcctl = {.d32 = 0 };
++ gpwrdn_data_t gpwrdn = {.d32 = 0 };
++ gusbcfg_data_t gusbcfg = {.d32 = 0 };
++
++ /* Change to L2(suspend) state */
++ core_if->lx_state = DWC_OTG_L2;
++
++ /* Clear interrupt in gintsts */
++ gintsts.d32 = 0;
++ gintsts.b.usbsuspend = 1;
++ DWC_WRITE_REG32(&core_if->core_global_regs->
++ gintsts, gintsts.d32);
++ DWC_PRINTF("Start of hibernation completed\n");
++ dwc_otg_save_global_regs(core_if);
++ dwc_otg_save_dev_regs(core_if);
++
++ gusbcfg.d32 =
++ DWC_READ_REG32(&core_if->core_global_regs->
++ gusbcfg);
++ if (gusbcfg.b.ulpi_utmi_sel == 1) {
++ /* ULPI interface */
++ /* Suspend the Phy Clock */
++ pcgcctl.d32 = 0;
++ pcgcctl.b.stoppclk = 1;
++ DWC_MODIFY_REG32(core_if->pcgcctl, 0,
++ pcgcctl.d32);
++ dwc_udelay(10);
++ gpwrdn.b.pmuactv = 1;
++ DWC_MODIFY_REG32(&core_if->
++ core_global_regs->
++ gpwrdn, 0, gpwrdn.d32);
++ } else {
++ /* UTMI+ Interface */
++ gpwrdn.b.pmuactv = 1;
++ DWC_MODIFY_REG32(&core_if->
++ core_global_regs->
++ gpwrdn, 0, gpwrdn.d32);
++ dwc_udelay(10);
++ pcgcctl.b.stoppclk = 1;
++ DWC_MODIFY_REG32(core_if->pcgcctl, 0,
++ pcgcctl.d32);
++ dwc_udelay(10);
++ }
++
++ /* Set flag to indicate that we are in hibernation */
++ core_if->hibernation_suspend = 1;
++ /* Enable interrupts from wake up logic */
++ gpwrdn.d32 = 0;
++ gpwrdn.b.pmuintsel = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->
++ gpwrdn, 0, gpwrdn.d32);
++ dwc_udelay(10);
++
++ /* Unmask device mode interrupts in GPWRDN */
++ gpwrdn.d32 = 0;
++ gpwrdn.b.rst_det_msk = 1;
++ gpwrdn.b.lnstchng_msk = 1;
++ gpwrdn.b.sts_chngint_msk = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->
++ gpwrdn, 0, gpwrdn.d32);
++ dwc_udelay(10);
++
++ /* Enable Power Down Clamp */
++ gpwrdn.d32 = 0;
++ gpwrdn.b.pwrdnclmp = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->
++ gpwrdn, 0, gpwrdn.d32);
++ dwc_udelay(10);
++
++ /* Switch off VDD */
++ gpwrdn.d32 = 0;
++ gpwrdn.b.pwrdnswtch = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->
++ gpwrdn, 0, gpwrdn.d32);
++
++ /* Save gpwrdn register for further usage if stschng interrupt */
++ core_if->gr_backup->gpwrdn_local =
++ DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
++ DWC_PRINTF("Hibernation completed\n");
++
++ return 1;
++ }
++ } else if (core_if->power_down == 3) {
++ pcgcctl_data_t pcgcctl = {.d32 = 0 };
++ dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
++ DWC_DEBUGPL(DBG_ANY, "lx_state = %08x\n",core_if->lx_state);
++ DWC_DEBUGPL(DBG_ANY, " device address = %08d\n",dcfg.b.devaddr);
++
++ if (core_if->lx_state != DWC_OTG_L3 && dcfg.b.devaddr) {
++ DWC_DEBUGPL(DBG_ANY, "Start entering to extended hibernation\n");
++ core_if->xhib = 1;
++
++ /* Clear interrupt in gintsts */
++ gintsts.d32 = 0;
++ gintsts.b.usbsuspend = 1;
++ DWC_WRITE_REG32(&core_if->core_global_regs->
++ gintsts, gintsts.d32);
++
++ dwc_otg_save_global_regs(core_if);
++ dwc_otg_save_dev_regs(core_if);
++
++ /* Wait for 10 PHY clocks */
++ dwc_udelay(10);
++
++ /* Program GPIO register while entering to xHib */
++ DWC_WRITE_REG32(&core_if->core_global_regs->ggpio, 0x1);
++
++ pcgcctl.b.enbl_extnd_hiber = 1;
++ DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32);
++ DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32);
++
++ pcgcctl.d32 = 0;
++ pcgcctl.b.extnd_hiber_pwrclmp = 1;
++ DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32);
++
++ pcgcctl.d32 = 0;
++ pcgcctl.b.extnd_hiber_switch = 1;
++ core_if->gr_backup->xhib_gpwrdn = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
++ core_if->gr_backup->xhib_pcgcctl = DWC_READ_REG32(core_if->pcgcctl) | pcgcctl.d32;
++ DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32);
++
++ DWC_DEBUGPL(DBG_ANY, "Finished entering to extended hibernation\n");
++
++ return 1;
++ }
++ }
++ } else {
++ if (core_if->op_state == A_PERIPHERAL) {
++ DWC_DEBUGPL(DBG_ANY, "a_peripheral->a_host\n");
++ /* Clear the a_peripheral flag, back to a_host. */
++ DWC_SPINUNLOCK(core_if->lock);
++ cil_pcd_stop(core_if);
++ cil_hcd_start(core_if);
++ DWC_SPINLOCK(core_if->lock);
++ core_if->op_state = A_HOST;
++ }
++ }
++
++ /* Change to L2(suspend) state */
++ core_if->lx_state = DWC_OTG_L2;
++
++ /* Clear interrupt */
++ gintsts.d32 = 0;
++ gintsts.b.usbsuspend = 1;
++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
++
++ return 1;
++}
++
++static int32_t dwc_otg_handle_xhib_exit_intr(dwc_otg_core_if_t * core_if)
++{
++ gpwrdn_data_t gpwrdn = {.d32 = 0 };
++ pcgcctl_data_t pcgcctl = {.d32 = 0 };
++ gahbcfg_data_t gahbcfg = {.d32 = 0 };
++
++ dwc_udelay(10);
++
++ /* Program GPIO register while entering to xHib */
++ DWC_WRITE_REG32(&core_if->core_global_regs->ggpio, 0x0);
++
++ pcgcctl.d32 = core_if->gr_backup->xhib_pcgcctl;
++ pcgcctl.b.extnd_hiber_pwrclmp = 0;
++ DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
++ dwc_udelay(10);
++
++ gpwrdn.d32 = core_if->gr_backup->xhib_gpwrdn;
++ gpwrdn.b.restore = 1;
++ DWC_WRITE_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32);
++ dwc_udelay(10);
++
++ restore_lpm_i2c_regs(core_if);
++
++ pcgcctl.d32 = core_if->gr_backup->pcgcctl_local & (0x3FFFF << 14);
++ pcgcctl.b.max_xcvrselect = 1;
++ pcgcctl.b.ess_reg_restored = 0;
++ pcgcctl.b.extnd_hiber_switch = 0;
++ pcgcctl.b.extnd_hiber_pwrclmp = 0;
++ pcgcctl.b.enbl_extnd_hiber = 1;
++ DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
++
++ gahbcfg.d32 = core_if->gr_backup->gahbcfg_local;
++ gahbcfg.b.glblintrmsk = 1;
++ DWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg, gahbcfg.d32);
++
++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
++ DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, 0x1 << 16);
++
++ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg,
++ core_if->gr_backup->gusbcfg_local);
++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg,
++ core_if->dr_backup->dcfg);
++
++ pcgcctl.d32 = 0;
++ pcgcctl.d32 = core_if->gr_backup->pcgcctl_local & (0x3FFFF << 14);
++ pcgcctl.b.max_xcvrselect = 1;
++ pcgcctl.d32 |= 0x608;
++ DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
++ dwc_udelay(10);
++
++ pcgcctl.d32 = 0;
++ pcgcctl.d32 = core_if->gr_backup->pcgcctl_local & (0x3FFFF << 14);
++ pcgcctl.b.max_xcvrselect = 1;
++ pcgcctl.b.ess_reg_restored = 1;
++ pcgcctl.b.enbl_extnd_hiber = 1;
++ pcgcctl.b.rstpdwnmodule = 1;
++ pcgcctl.b.restoremode = 1;
++ DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
++
++ DWC_DEBUGPL(DBG_ANY, "%s called\n", __FUNCTION__);
++
++ return 1;
++}
++
++#ifdef CONFIG_USB_DWC_OTG_LPM
++/**
++ * This function hadles LPM transaction received interrupt.
++ */
++static int32_t dwc_otg_handle_lpm_intr(dwc_otg_core_if_t * core_if)
++{
++ glpmcfg_data_t lpmcfg;
++ gintsts_data_t gintsts;
++
++ if (!core_if->core_params->lpm_enable) {
++ DWC_PRINTF("Unexpected LPM interrupt\n");
++ }
++
++ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
++ DWC_PRINTF("LPM config register = 0x%08x\n", lpmcfg.d32);
++
++ if (dwc_otg_is_host_mode(core_if)) {
++ cil_hcd_sleep(core_if);
++ } else {
++ lpmcfg.b.hird_thres |= (1 << 4);
++ DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg,
++ lpmcfg.d32);
++ }
++
++ /* Examine prt_sleep_sts after TL1TokenTetry period max (10 us) */
++ dwc_udelay(10);
++ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
++ if (lpmcfg.b.prt_sleep_sts) {
++ /* Save the current state */
++ core_if->lx_state = DWC_OTG_L1;
++ }
++
++ /* Clear interrupt */
++ gintsts.d32 = 0;
++ gintsts.b.lpmtranrcvd = 1;
++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
++ return 1;
++}
++#endif /* CONFIG_USB_DWC_OTG_LPM */
++
++/**
++ * This function returns the Core Interrupt register.
++ */
++static inline uint32_t dwc_otg_read_common_intr(dwc_otg_core_if_t * core_if, gintmsk_data_t *reenable_gintmsk, dwc_otg_hcd_t *hcd)
++{
++ gahbcfg_data_t gahbcfg = {.d32 = 0 };
++ gintsts_data_t gintsts;
++ gintmsk_data_t gintmsk;
++ gintmsk_data_t gintmsk_common = {.d32 = 0 };
++ gintmsk_common.b.wkupintr = 1;
++ gintmsk_common.b.sessreqintr = 1;
++ gintmsk_common.b.conidstschng = 1;
++ gintmsk_common.b.otgintr = 1;
++ gintmsk_common.b.modemismatch = 1;
++ gintmsk_common.b.disconnect = 1;
++ gintmsk_common.b.usbsuspend = 1;
++#ifdef CONFIG_USB_DWC_OTG_LPM
++ gintmsk_common.b.lpmtranrcvd = 1;
++#endif
++ gintmsk_common.b.restoredone = 1;
++ if(dwc_otg_is_device_mode(core_if))
++ {
++ /** @todo: The port interrupt occurs while in device
++ * mode. Added code to CIL to clear the interrupt for now!
++ */
++ gintmsk_common.b.portintr = 1;
++ }
++ gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
++ gintmsk.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
++ if(fiq_enable) {
++ local_fiq_disable();
++ /* Pull in the interrupts that the FIQ has masked */
++ gintmsk.d32 |= ~(hcd->fiq_state->gintmsk_saved.d32);
++ gintmsk.d32 |= gintmsk_common.d32;
++ /* for the upstairs function to reenable - have to read it here in case FIQ triggers again */
++ reenable_gintmsk->d32 = gintmsk.d32;
++ local_fiq_enable();
++ }
++
++ gahbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gahbcfg);
++
++#ifdef DEBUG
++ /* if any common interrupts set */
++ if (gintsts.d32 & gintmsk_common.d32) {
++ DWC_DEBUGPL(DBG_ANY, "common_intr: gintsts=%08x gintmsk=%08x\n",
++ gintsts.d32, gintmsk.d32);
++ }
++#endif
++ if (!fiq_enable){
++ if (gahbcfg.b.glblintrmsk)
++ return ((gintsts.d32 & gintmsk.d32) & gintmsk_common.d32);
++ else
++ return 0;
++ } else {
++ /* Our IRQ kicker is no longer the USB hardware, it's the MPHI interface.
++ * Can't trust the global interrupt mask bit in this case.
++ */
++ return ((gintsts.d32 & gintmsk.d32) & gintmsk_common.d32);
++ }
++
++}
++
++/* MACRO for clearing interupt bits in GPWRDN register */
++#define CLEAR_GPWRDN_INTR(__core_if,__intr) \
++do { \
++ gpwrdn_data_t gpwrdn = {.d32=0}; \
++ gpwrdn.b.__intr = 1; \
++ DWC_MODIFY_REG32(&__core_if->core_global_regs->gpwrdn, \
++ 0, gpwrdn.d32); \
++} while (0)
++
++/**
++ * Common interrupt handler.
++ *
++ * The common interrupts are those that occur in both Host and Device mode.
++ * This handler handles the following interrupts:
++ * - Mode Mismatch Interrupt
++ * - Disconnect Interrupt
++ * - OTG Interrupt
++ * - Connector ID Status Change Interrupt
++ * - Session Request Interrupt.
++ * - Resume / Remote Wakeup Detected Interrupt.
++ * - LPM Transaction Received Interrupt
++ * - ADP Transaction Received Interrupt
++ *
++ */
++int32_t dwc_otg_handle_common_intr(void *dev)
++{
++ int retval = 0;
++ gintsts_data_t gintsts;
++ gintmsk_data_t gintmsk_reenable = { .d32 = 0 };
++ gpwrdn_data_t gpwrdn = {.d32 = 0 };
++ dwc_otg_device_t *otg_dev = dev;
++ dwc_otg_core_if_t *core_if = otg_dev->core_if;
++ gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
++ if (dwc_otg_is_device_mode(core_if))
++ core_if->frame_num = dwc_otg_get_frame_number(core_if);
++
++ if (core_if->lock)
++ DWC_SPINLOCK(core_if->lock);
++
++ if (core_if->power_down == 3 && core_if->xhib == 1) {
++ DWC_DEBUGPL(DBG_ANY, "Exiting from xHIB state\n");
++ retval |= dwc_otg_handle_xhib_exit_intr(core_if);
++ core_if->xhib = 2;
++ if (core_if->lock)
++ DWC_SPINUNLOCK(core_if->lock);
++
++ return retval;
++ }
++
++ if (core_if->hibernation_suspend <= 0) {
++ /* read_common will have to poke the FIQ's saved mask. We must then clear this mask at the end
++ * of this handler - god only knows why it's done like this
++ */
++ gintsts.d32 = dwc_otg_read_common_intr(core_if, &gintmsk_reenable, otg_dev->hcd);
++
++ if (gintsts.b.modemismatch) {
++ retval |= dwc_otg_handle_mode_mismatch_intr(core_if);
++ }
++ if (gintsts.b.otgintr) {
++ retval |= dwc_otg_handle_otg_intr(core_if);
++ }
++ if (gintsts.b.conidstschng) {
++ retval |=
++ dwc_otg_handle_conn_id_status_change_intr(core_if);
++ }
++ if (gintsts.b.disconnect) {
++ retval |= dwc_otg_handle_disconnect_intr(core_if);
++ }
++ if (gintsts.b.sessreqintr) {
++ retval |= dwc_otg_handle_session_req_intr(core_if);
++ }
++ if (gintsts.b.wkupintr) {
++ retval |= dwc_otg_handle_wakeup_detected_intr(core_if);
++ }
++ if (gintsts.b.usbsuspend) {
++ retval |= dwc_otg_handle_usb_suspend_intr(core_if);
++ }
++#ifdef CONFIG_USB_DWC_OTG_LPM
++ if (gintsts.b.lpmtranrcvd) {
++ retval |= dwc_otg_handle_lpm_intr(core_if);
++ }
++#endif
++ if (gintsts.b.restoredone) {
++ gintsts.d32 = 0;
++ if (core_if->power_down == 2)
++ core_if->hibernation_suspend = -1;
++ else if (core_if->power_down == 3 && core_if->xhib == 2) {
++ gpwrdn_data_t gpwrdn = {.d32 = 0 };
++ pcgcctl_data_t pcgcctl = {.d32 = 0 };
++ dctl_data_t dctl = {.d32 = 0 };
++
++ DWC_WRITE_REG32(&core_if->core_global_regs->
++ gintsts, 0xFFFFFFFF);
++
++ DWC_DEBUGPL(DBG_ANY,
++ "RESTORE DONE generated\n");
++
++ gpwrdn.b.restore = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++ dwc_udelay(10);
++
++ pcgcctl.b.rstpdwnmodule = 1;
++ DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
++
++ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, core_if->gr_backup->gusbcfg_local);
++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, core_if->dr_backup->dcfg);
++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, core_if->dr_backup->dctl);
++ dwc_udelay(50);
++
++ dctl.b.pwronprgdone = 1;
++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
++ dwc_udelay(10);
++
++ dwc_otg_restore_global_regs(core_if);
++ dwc_otg_restore_dev_regs(core_if, 0);
++
++ dctl.d32 = 0;
++ dctl.b.pwronprgdone = 1;
++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, 0);
++ dwc_udelay(10);
++
++ pcgcctl.d32 = 0;
++ pcgcctl.b.enbl_extnd_hiber = 1;
++ DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
++
++ /* The core will be in ON STATE */
++ core_if->lx_state = DWC_OTG_L0;
++ core_if->xhib = 0;
++
++ DWC_SPINUNLOCK(core_if->lock);
++ if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
++ core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);
++ }
++ DWC_SPINLOCK(core_if->lock);
++
++ }
++
++ gintsts.b.restoredone = 1;
++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts,gintsts.d32);
++ DWC_PRINTF(" --Restore done interrupt received-- \n");
++ retval |= 1;
++ }
++ if (gintsts.b.portintr && dwc_otg_is_device_mode(core_if)) {
++ /* The port interrupt occurs while in device mode with HPRT0
++ * Port Enable/Disable.
++ */
++ gintsts.d32 = 0;
++ gintsts.b.portintr = 1;
++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts,gintsts.d32);
++ retval |= 1;
++ gintmsk_reenable.b.portintr = 1;
++
++ }
++ /* Did we actually handle anything? if so, unmask the interrupt */
++// fiq_print(FIQDBG_INT, otg_dev->hcd->fiq_state, "CILOUT %1d", retval);
++// fiq_print(FIQDBG_INT, otg_dev->hcd->fiq_state, "%08x", gintsts.d32);
++// fiq_print(FIQDBG_INT, otg_dev->hcd->fiq_state, "%08x", gintmsk_reenable.d32);
++ if (retval && fiq_enable) {
++ DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gintmsk_reenable.d32);
++ }
++
++ } else {
++ DWC_DEBUGPL(DBG_ANY, "gpwrdn=%08x\n", gpwrdn.d32);
++
++ if (gpwrdn.b.disconn_det && gpwrdn.b.disconn_det_msk) {
++ CLEAR_GPWRDN_INTR(core_if, disconn_det);
++ if (gpwrdn.b.linestate == 0) {
++ dwc_otg_handle_pwrdn_disconnect_intr(core_if);
++ } else {
++ DWC_PRINTF("Disconnect detected while linestate is not 0\n");
++ }
++
++ retval |= 1;
++ }
++ if (gpwrdn.b.lnstschng && gpwrdn.b.lnstchng_msk) {
++ CLEAR_GPWRDN_INTR(core_if, lnstschng);
++ /* remote wakeup from hibernation */
++ if (gpwrdn.b.linestate == 2 || gpwrdn.b.linestate == 1) {
++ dwc_otg_handle_pwrdn_wakeup_detected_intr(core_if);
++ } else {
++ DWC_PRINTF("gpwrdn.linestate = %d\n", gpwrdn.b.linestate);
++ }
++ retval |= 1;
++ }
++ if (gpwrdn.b.rst_det && gpwrdn.b.rst_det_msk) {
++ CLEAR_GPWRDN_INTR(core_if, rst_det);
++ if (gpwrdn.b.linestate == 0) {
++ DWC_PRINTF("Reset detected\n");
++ retval |= dwc_otg_device_hibernation_restore(core_if, 0, 1);
++ }
++ }
++ if (gpwrdn.b.srp_det && gpwrdn.b.srp_det_msk) {
++ CLEAR_GPWRDN_INTR(core_if, srp_det);
++ dwc_otg_handle_pwrdn_srp_intr(core_if);
++ retval |= 1;
++ }
++ }
++ /* Handle ADP interrupt here */
++ if (gpwrdn.b.adp_int) {
++ DWC_PRINTF("ADP interrupt\n");
++ CLEAR_GPWRDN_INTR(core_if, adp_int);
++ dwc_otg_adp_handle_intr(core_if);
++ retval |= 1;
++ }
++ if (gpwrdn.b.sts_chngint && gpwrdn.b.sts_chngint_msk) {
++ DWC_PRINTF("STS CHNG interrupt asserted\n");
++ CLEAR_GPWRDN_INTR(core_if, sts_chngint);
++ dwc_otg_handle_pwrdn_stschng_intr(otg_dev);
++
++ retval |= 1;
++ }
++ if (core_if->lock)
++ DWC_SPINUNLOCK(core_if->lock);
++ return retval;
++}
+diff -Nur linux-4.1.3/drivers/usb/host/dwc_otg/dwc_otg_core_if.h linux-xbian-rpi/drivers/usb/host/dwc_otg/dwc_otg_core_if.h
+--- linux-4.1.3/drivers/usb/host/dwc_otg/dwc_otg_core_if.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/usb/host/dwc_otg/dwc_otg_core_if.h 2015-07-28 01:20:58.445156473 +0200
+@@ -0,0 +1,705 @@
++/* ==========================================================================
++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_core_if.h $
++ * $Revision: #13 $
++ * $Date: 2012/08/10 $
++ * $Change: 2047372 $
++ *
++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++ * otherwise expressly agreed to in writing between Synopsys and you.
++ *
++ * The Software IS NOT an item of Licensed Software or Licensed Product under
++ * any End User Software License Agreement or Agreement for Licensed Product
++ * with Synopsys or any supplement thereto. You are permitted to use and
++ * redistribute this Software in source and binary forms, with or without
++ * modification, provided that redistributions of source code must retain this
++ * notice. You may not view, use, disclose, copy or distribute this file or
++ * any information contained herein except pursuant to this license grant from
++ * Synopsys. If you do not agree with this notice, including the disclaimer
++ * below, then you are not authorized to use the Software.
++ *
++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++ * DAMAGE.
++ * ========================================================================== */
++#if !defined(__DWC_CORE_IF_H__)
++#define __DWC_CORE_IF_H__
++
++#include "dwc_os.h"
++
++/** @file
++ * This file defines DWC_OTG Core API
++ */
++
++struct dwc_otg_core_if;
++typedef struct dwc_otg_core_if dwc_otg_core_if_t;
++
++/** Maximum number of Periodic FIFOs */
++#define MAX_PERIO_FIFOS 15
++/** Maximum number of Periodic FIFOs */
++#define MAX_TX_FIFOS 15
++
++/** Maximum number of Endpoints/HostChannels */
++#define MAX_EPS_CHANNELS 16
++
++extern dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t * _reg_base_addr);
++extern void dwc_otg_core_init(dwc_otg_core_if_t * _core_if);
++extern void dwc_otg_cil_remove(dwc_otg_core_if_t * _core_if);
++
++extern void dwc_otg_enable_global_interrupts(dwc_otg_core_if_t * _core_if);
++extern void dwc_otg_disable_global_interrupts(dwc_otg_core_if_t * _core_if);
++
++extern uint8_t dwc_otg_is_device_mode(dwc_otg_core_if_t * _core_if);
++extern uint8_t dwc_otg_is_host_mode(dwc_otg_core_if_t * _core_if);
++
++extern uint8_t dwc_otg_is_dma_enable(dwc_otg_core_if_t * core_if);
++
++/** This function should be called on every hardware interrupt. */
++extern int32_t dwc_otg_handle_common_intr(void *otg_dev);
++
++/** @name OTG Core Parameters */
++/** @{ */
++
++/**
++ * Specifies the OTG capabilities. The driver will automatically
++ * detect the value for this parameter if none is specified.
++ * 0 - HNP and SRP capable (default)
++ * 1 - SRP Only capable
++ * 2 - No HNP/SRP capable
++ */
++extern int dwc_otg_set_param_otg_cap(dwc_otg_core_if_t * core_if, int32_t val);
++extern int32_t dwc_otg_get_param_otg_cap(dwc_otg_core_if_t * core_if);
++#define DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE 0
++#define DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE 1
++#define DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
++#define dwc_param_otg_cap_default DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE
++
++extern int dwc_otg_set_param_opt(dwc_otg_core_if_t * core_if, int32_t val);
++extern int32_t dwc_otg_get_param_opt(dwc_otg_core_if_t * core_if);
++#define dwc_param_opt_default 1
++
++/**
++ * Specifies whether to use slave or DMA mode for accessing the data
++ * FIFOs. The driver will automatically detect the value for this
++ * parameter if none is specified.
++ * 0 - Slave
++ * 1 - DMA (default, if available)
++ */
++extern int dwc_otg_set_param_dma_enable(dwc_otg_core_if_t * core_if,
++ int32_t val);
++extern int32_t dwc_otg_get_param_dma_enable(dwc_otg_core_if_t * core_if);
++#define dwc_param_dma_enable_default 1
++
++/**
++ * When DMA mode is enabled specifies whether to use
++ * address DMA or DMA Descritor mode for accessing the data
++ * FIFOs in device mode. The driver will automatically detect
++ * the value for this parameter if none is specified.
++ * 0 - address DMA
++ * 1 - DMA Descriptor(default, if available)
++ */
++extern int dwc_otg_set_param_dma_desc_enable(dwc_otg_core_if_t * core_if,
++ int32_t val);
++extern int32_t dwc_otg_get_param_dma_desc_enable(dwc_otg_core_if_t * core_if);
++//#define dwc_param_dma_desc_enable_default 1
++#define dwc_param_dma_desc_enable_default 0 // Broadcom BCM2708
++
++/** The DMA Burst size (applicable only for External DMA
++ * Mode). 1, 4, 8 16, 32, 64, 128, 256 (default 32)
++ */
++extern int dwc_otg_set_param_dma_burst_size(dwc_otg_core_if_t * core_if,
++ int32_t val);
++extern int32_t dwc_otg_get_param_dma_burst_size(dwc_otg_core_if_t * core_if);
++#define dwc_param_dma_burst_size_default 32
++
++/**
++ * Specifies the maximum speed of operation in host and device mode.
++ * The actual speed depends on the speed of the attached device and
++ * the value of phy_type. The actual speed depends on the speed of the
++ * attached device.
++ * 0 - High Speed (default)
++ * 1 - Full Speed
++ */
++extern int dwc_otg_set_param_speed(dwc_otg_core_if_t * core_if, int32_t val);
++extern int32_t dwc_otg_get_param_speed(dwc_otg_core_if_t * core_if);
++#define dwc_param_speed_default 0
++#define DWC_SPEED_PARAM_HIGH 0
++#define DWC_SPEED_PARAM_FULL 1
++
++/** Specifies whether low power mode is supported when attached
++ * to a Full Speed or Low Speed device in host mode.
++ * 0 - Don't support low power mode (default)
++ * 1 - Support low power mode
++ */
++extern int dwc_otg_set_param_host_support_fs_ls_low_power(dwc_otg_core_if_t *
++ core_if, int32_t val);
++extern int32_t dwc_otg_get_param_host_support_fs_ls_low_power(dwc_otg_core_if_t
++ * core_if);
++#define dwc_param_host_support_fs_ls_low_power_default 0
++
++/** Specifies the PHY clock rate in low power mode when connected to a
++ * Low Speed device in host mode. This parameter is applicable only if
++ * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS
++ * then defaults to 6 MHZ otherwise 48 MHZ.
++ *
++ * 0 - 48 MHz
++ * 1 - 6 MHz
++ */
++extern int dwc_otg_set_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t *
++ core_if, int32_t val);
++extern int32_t dwc_otg_get_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t *
++ core_if);
++#define dwc_param_host_ls_low_power_phy_clk_default 0
++#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0
++#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1
++
++/**
++ * 0 - Use cC FIFO size parameters
++ * 1 - Allow dynamic FIFO sizing (default)
++ */
++extern int dwc_otg_set_param_enable_dynamic_fifo(dwc_otg_core_if_t * core_if,
++ int32_t val);
++extern int32_t dwc_otg_get_param_enable_dynamic_fifo(dwc_otg_core_if_t *
++ core_if);
++#define dwc_param_enable_dynamic_fifo_default 1
++
++/** Total number of 4-byte words in the data FIFO memory. This
++ * memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic
++ * Tx FIFOs.
++ * 32 to 32768 (default 8192)
++ * Note: The total FIFO memory depth in the FPGA configuration is 8192.
++ */
++extern int dwc_otg_set_param_data_fifo_size(dwc_otg_core_if_t * core_if,
++ int32_t val);
++extern int32_t dwc_otg_get_param_data_fifo_size(dwc_otg_core_if_t * core_if);
++//#define dwc_param_data_fifo_size_default 8192
++#define dwc_param_data_fifo_size_default 0xFF0 // Broadcom BCM2708
++
++/** Number of 4-byte words in the Rx FIFO in device mode when dynamic
++ * FIFO sizing is enabled.
++ * 16 to 32768 (default 1064)
++ */
++extern int dwc_otg_set_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if,
++ int32_t val);
++extern int32_t dwc_otg_get_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if);
++#define dwc_param_dev_rx_fifo_size_default 1064
++
++/** Number of 4-byte words in the non-periodic Tx FIFO in device mode
++ * when dynamic FIFO sizing is enabled.
++ * 16 to 32768 (default 1024)
++ */
++extern int dwc_otg_set_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t *
++ core_if, int32_t val);
++extern int32_t dwc_otg_get_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t *
++ core_if);
++#define dwc_param_dev_nperio_tx_fifo_size_default 1024
++
++/** Number of 4-byte words in each of the periodic Tx FIFOs in device
++ * mode when dynamic FIFO sizing is enabled.
++ * 4 to 768 (default 256)
++ */
++extern int dwc_otg_set_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,
++ int32_t val, int fifo_num);
++extern int32_t dwc_otg_get_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t *
++ core_if, int fifo_num);
++#define dwc_param_dev_perio_tx_fifo_size_default 256
++
++/** Number of 4-byte words in the Rx FIFO in host mode when dynamic
++ * FIFO sizing is enabled.
++ * 16 to 32768 (default 1024)
++ */
++extern int dwc_otg_set_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if,
++ int32_t val);
++extern int32_t dwc_otg_get_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if);
++//#define dwc_param_host_rx_fifo_size_default 1024
++#define dwc_param_host_rx_fifo_size_default 774 // Broadcom BCM2708
++
++/** Number of 4-byte words in the non-periodic Tx FIFO in host mode
++ * when Dynamic FIFO sizing is enabled in the core.
++ * 16 to 32768 (default 1024)
++ */
++extern int dwc_otg_set_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t *
++ core_if, int32_t val);
++extern int32_t dwc_otg_get_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t *
++ core_if);
++//#define dwc_param_host_nperio_tx_fifo_size_default 1024
++#define dwc_param_host_nperio_tx_fifo_size_default 0x100 // Broadcom BCM2708
++
++/** Number of 4-byte words in the host periodic Tx FIFO when dynamic
++ * FIFO sizing is enabled.
++ * 16 to 32768 (default 1024)
++ */
++extern int dwc_otg_set_param_host_perio_tx_fifo_size(dwc_otg_core_if_t *
++ core_if, int32_t val);
++extern int32_t dwc_otg_get_param_host_perio_tx_fifo_size(dwc_otg_core_if_t *
++ core_if);
++//#define dwc_param_host_perio_tx_fifo_size_default 1024
++#define dwc_param_host_perio_tx_fifo_size_default 0x200 // Broadcom BCM2708
++
++/** The maximum transfer size supported in bytes.
++ * 2047 to 65,535 (default 65,535)
++ */
++extern int dwc_otg_set_param_max_transfer_size(dwc_otg_core_if_t * core_if,
++ int32_t val);
++extern int32_t dwc_otg_get_param_max_transfer_size(dwc_otg_core_if_t * core_if);
++#define dwc_param_max_transfer_size_default 65535
++
++/** The maximum number of packets in a transfer.
++ * 15 to 511 (default 511)
++ */
++extern int dwc_otg_set_param_max_packet_count(dwc_otg_core_if_t * core_if,
++ int32_t val);
++extern int32_t dwc_otg_get_param_max_packet_count(dwc_otg_core_if_t * core_if);
++#define dwc_param_max_packet_count_default 511
++
++/** The number of host channel registers to use.
++ * 1 to 16 (default 12)
++ * Note: The FPGA configuration supports a maximum of 12 host channels.
++ */
++extern int dwc_otg_set_param_host_channels(dwc_otg_core_if_t * core_if,
++ int32_t val);
++extern int32_t dwc_otg_get_param_host_channels(dwc_otg_core_if_t * core_if);
++//#define dwc_param_host_channels_default 12
++#define dwc_param_host_channels_default 8 // Broadcom BCM2708
++
++/** The number of endpoints in addition to EP0 available for device
++ * mode operations.
++ * 1 to 15 (default 6 IN and OUT)
++ * Note: The FPGA configuration supports a maximum of 6 IN and OUT
++ * endpoints in addition to EP0.
++ */
++extern int dwc_otg_set_param_dev_endpoints(dwc_otg_core_if_t * core_if,
++ int32_t val);
++extern int32_t dwc_otg_get_param_dev_endpoints(dwc_otg_core_if_t * core_if);
++#define dwc_param_dev_endpoints_default 6
++
++/**
++ * Specifies the type of PHY interface to use. By default, the driver
++ * will automatically detect the phy_type.
++ *
++ * 0 - Full Speed PHY
++ * 1 - UTMI+ (default)
++ * 2 - ULPI
++ */
++extern int dwc_otg_set_param_phy_type(dwc_otg_core_if_t * core_if, int32_t val);
++extern int32_t dwc_otg_get_param_phy_type(dwc_otg_core_if_t * core_if);
++#define DWC_PHY_TYPE_PARAM_FS 0
++#define DWC_PHY_TYPE_PARAM_UTMI 1
++#define DWC_PHY_TYPE_PARAM_ULPI 2
++#define dwc_param_phy_type_default DWC_PHY_TYPE_PARAM_UTMI
++
++/**
++ * Specifies the UTMI+ Data Width. This parameter is
++ * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI
++ * PHY_TYPE, this parameter indicates the data width between
++ * the MAC and the ULPI Wrapper.) Also, this parameter is
++ * applicable only if the OTG_HSPHY_WIDTH cC parameter was set
++ * to "8 and 16 bits", meaning that the core has been
++ * configured to work at either data path width.
++ *
++ * 8 or 16 bits (default 16)
++ */
++extern int dwc_otg_set_param_phy_utmi_width(dwc_otg_core_if_t * core_if,
++ int32_t val);
++extern int32_t dwc_otg_get_param_phy_utmi_width(dwc_otg_core_if_t * core_if);
++//#define dwc_param_phy_utmi_width_default 16
++#define dwc_param_phy_utmi_width_default 8 // Broadcom BCM2708
++
++/**
++ * Specifies whether the ULPI operates at double or single
++ * data rate. This parameter is only applicable if PHY_TYPE is
++ * ULPI.
++ *
++ * 0 - single data rate ULPI interface with 8 bit wide data
++ * bus (default)
++ * 1 - double data rate ULPI interface with 4 bit wide data
++ * bus
++ */
++extern int dwc_otg_set_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if,
++ int32_t val);
++extern int32_t dwc_otg_get_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if);
++#define dwc_param_phy_ulpi_ddr_default 0
++
++/**
++ * Specifies whether to use the internal or external supply to
++ * drive the vbus with a ULPI phy.
++ */
++extern int dwc_otg_set_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if,
++ int32_t val);
++extern int32_t dwc_otg_get_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if);
++#define DWC_PHY_ULPI_INTERNAL_VBUS 0
++#define DWC_PHY_ULPI_EXTERNAL_VBUS 1
++#define dwc_param_phy_ulpi_ext_vbus_default DWC_PHY_ULPI_INTERNAL_VBUS
++
++/**
++ * Specifies whether to use the I2Cinterface for full speed PHY. This
++ * parameter is only applicable if PHY_TYPE is FS.
++ * 0 - No (default)
++ * 1 - Yes
++ */
++extern int dwc_otg_set_param_i2c_enable(dwc_otg_core_if_t * core_if,
++ int32_t val);
++extern int32_t dwc_otg_get_param_i2c_enable(dwc_otg_core_if_t * core_if);
++#define dwc_param_i2c_enable_default 0
++
++extern int dwc_otg_set_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if,
++ int32_t val);
++extern int32_t dwc_otg_get_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if);
++#define dwc_param_ulpi_fs_ls_default 0
++
++extern int dwc_otg_set_param_ts_dline(dwc_otg_core_if_t * core_if, int32_t val);
++extern int32_t dwc_otg_get_param_ts_dline(dwc_otg_core_if_t * core_if);
++#define dwc_param_ts_dline_default 0
++
++/**
++ * Specifies whether dedicated transmit FIFOs are
++ * enabled for non periodic IN endpoints in device mode
++ * 0 - No
++ * 1 - Yes
++ */
++extern int dwc_otg_set_param_en_multiple_tx_fifo(dwc_otg_core_if_t * core_if,
++ int32_t val);
++extern int32_t dwc_otg_get_param_en_multiple_tx_fifo(dwc_otg_core_if_t *
++ core_if);
++#define dwc_param_en_multiple_tx_fifo_default 1
++
++/** Number of 4-byte words in each of the Tx FIFOs in device
++ * mode when dynamic FIFO sizing is enabled.
++ * 4 to 768 (default 256)
++ */
++extern int dwc_otg_set_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if,
++ int fifo_num, int32_t val);
++extern int32_t dwc_otg_get_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if,
++ int fifo_num);
++#define dwc_param_dev_tx_fifo_size_default 768
++
++/** Thresholding enable flag-
++ * bit 0 - enable non-ISO Tx thresholding
++ * bit 1 - enable ISO Tx thresholding
++ * bit 2 - enable Rx thresholding
++ */
++extern int dwc_otg_set_param_thr_ctl(dwc_otg_core_if_t * core_if, int32_t val);
++extern int32_t dwc_otg_get_thr_ctl(dwc_otg_core_if_t * core_if, int fifo_num);
++#define dwc_param_thr_ctl_default 0
++
++/** Thresholding length for Tx
++ * FIFOs in 32 bit DWORDs
++ */
++extern int dwc_otg_set_param_tx_thr_length(dwc_otg_core_if_t * core_if,
++ int32_t val);
++extern int32_t dwc_otg_get_tx_thr_length(dwc_otg_core_if_t * core_if);
++#define dwc_param_tx_thr_length_default 64
++
++/** Thresholding length for Rx
++ * FIFOs in 32 bit DWORDs
++ */
++extern int dwc_otg_set_param_rx_thr_length(dwc_otg_core_if_t * core_if,
++ int32_t val);
++extern int32_t dwc_otg_get_rx_thr_length(dwc_otg_core_if_t * core_if);
++#define dwc_param_rx_thr_length_default 64
++
++/**
++ * Specifies whether LPM (Link Power Management) support is enabled
++ */
++extern int dwc_otg_set_param_lpm_enable(dwc_otg_core_if_t * core_if,
++ int32_t val);
++extern int32_t dwc_otg_get_param_lpm_enable(dwc_otg_core_if_t * core_if);
++#define dwc_param_lpm_enable_default 1
++
++/**
++ * Specifies whether PTI enhancement is enabled
++ */
++extern int dwc_otg_set_param_pti_enable(dwc_otg_core_if_t * core_if,
++ int32_t val);
++extern int32_t dwc_otg_get_param_pti_enable(dwc_otg_core_if_t * core_if);
++#define dwc_param_pti_enable_default 0
++
++/**
++ * Specifies whether MPI enhancement is enabled
++ */
++extern int dwc_otg_set_param_mpi_enable(dwc_otg_core_if_t * core_if,
++ int32_t val);
++extern int32_t dwc_otg_get_param_mpi_enable(dwc_otg_core_if_t * core_if);
++#define dwc_param_mpi_enable_default 0
++
++/**
++ * Specifies whether ADP capability is enabled
++ */
++extern int dwc_otg_set_param_adp_enable(dwc_otg_core_if_t * core_if,
++ int32_t val);
++extern int32_t dwc_otg_get_param_adp_enable(dwc_otg_core_if_t * core_if);
++#define dwc_param_adp_enable_default 0
++
++/**
++ * Specifies whether IC_USB capability is enabled
++ */
++
++extern int dwc_otg_set_param_ic_usb_cap(dwc_otg_core_if_t * core_if,
++ int32_t val);
++extern int32_t dwc_otg_get_param_ic_usb_cap(dwc_otg_core_if_t * core_if);
++#define dwc_param_ic_usb_cap_default 0
++
++extern int dwc_otg_set_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if,
++ int32_t val);
++extern int32_t dwc_otg_get_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if);
++#define dwc_param_ahb_thr_ratio_default 0
++
++extern int dwc_otg_set_param_power_down(dwc_otg_core_if_t * core_if,
++ int32_t val);
++extern int32_t dwc_otg_get_param_power_down(dwc_otg_core_if_t * core_if);
++#define dwc_param_power_down_default 0
++
++extern int dwc_otg_set_param_reload_ctl(dwc_otg_core_if_t * core_if,
++ int32_t val);
++extern int32_t dwc_otg_get_param_reload_ctl(dwc_otg_core_if_t * core_if);
++#define dwc_param_reload_ctl_default 0
++
++extern int dwc_otg_set_param_dev_out_nak(dwc_otg_core_if_t * core_if,
++ int32_t val);
++extern int32_t dwc_otg_get_param_dev_out_nak(dwc_otg_core_if_t * core_if);
++#define dwc_param_dev_out_nak_default 0
++
++extern int dwc_otg_set_param_cont_on_bna(dwc_otg_core_if_t * core_if,
++ int32_t val);
++extern int32_t dwc_otg_get_param_cont_on_bna(dwc_otg_core_if_t * core_if);
++#define dwc_param_cont_on_bna_default 0
++
++extern int dwc_otg_set_param_ahb_single(dwc_otg_core_if_t * core_if,
++ int32_t val);
++extern int32_t dwc_otg_get_param_ahb_single(dwc_otg_core_if_t * core_if);
++#define dwc_param_ahb_single_default 0
++
++extern int dwc_otg_set_param_otg_ver(dwc_otg_core_if_t * core_if, int32_t val);
++extern int32_t dwc_otg_get_param_otg_ver(dwc_otg_core_if_t * core_if);
++#define dwc_param_otg_ver_default 0
++
++/** @} */
++
++/** @name Access to registers and bit-fields */
++
++/**
++ * Dump core registers and SPRAM
++ */
++extern void dwc_otg_dump_dev_registers(dwc_otg_core_if_t * _core_if);
++extern void dwc_otg_dump_spram(dwc_otg_core_if_t * _core_if);
++extern void dwc_otg_dump_host_registers(dwc_otg_core_if_t * _core_if);
++extern void dwc_otg_dump_global_registers(dwc_otg_core_if_t * _core_if);
++
++/**
++ * Get host negotiation status.
++ */
++extern uint32_t dwc_otg_get_hnpstatus(dwc_otg_core_if_t * core_if);
++
++/**
++ * Get srp status
++ */
++extern uint32_t dwc_otg_get_srpstatus(dwc_otg_core_if_t * core_if);
++
++/**
++ * Set hnpreq bit in the GOTGCTL register.
++ */
++extern void dwc_otg_set_hnpreq(dwc_otg_core_if_t * core_if, uint32_t val);
++
++/**
++ * Get Content of SNPSID register.
++ */
++extern uint32_t dwc_otg_get_gsnpsid(dwc_otg_core_if_t * core_if);
++
++/**
++ * Get current mode.
++ * Returns 0 if in device mode, and 1 if in host mode.
++ */
++extern uint32_t dwc_otg_get_mode(dwc_otg_core_if_t * core_if);
++
++/**
++ * Get value of hnpcapable field in the GUSBCFG register
++ */
++extern uint32_t dwc_otg_get_hnpcapable(dwc_otg_core_if_t * core_if);
++/**
++ * Set value of hnpcapable field in the GUSBCFG register
++ */
++extern void dwc_otg_set_hnpcapable(dwc_otg_core_if_t * core_if, uint32_t val);
++
++/**
++ * Get value of srpcapable field in the GUSBCFG register
++ */
++extern uint32_t dwc_otg_get_srpcapable(dwc_otg_core_if_t * core_if);
++/**
++ * Set value of srpcapable field in the GUSBCFG register
++ */
++extern void dwc_otg_set_srpcapable(dwc_otg_core_if_t * core_if, uint32_t val);
++
++/**
++ * Get value of devspeed field in the DCFG register
++ */
++extern uint32_t dwc_otg_get_devspeed(dwc_otg_core_if_t * core_if);
++/**
++ * Set value of devspeed field in the DCFG register
++ */
++extern void dwc_otg_set_devspeed(dwc_otg_core_if_t * core_if, uint32_t val);
++
++/**
++ * Get the value of busconnected field from the HPRT0 register
++ */
++extern uint32_t dwc_otg_get_busconnected(dwc_otg_core_if_t * core_if);
++
++/**
++ * Gets the device enumeration Speed.
++ */
++extern uint32_t dwc_otg_get_enumspeed(dwc_otg_core_if_t * core_if);
++
++/**
++ * Get value of prtpwr field from the HPRT0 register
++ */
++extern uint32_t dwc_otg_get_prtpower(dwc_otg_core_if_t * core_if);
++
++/**
++ * Get value of flag indicating core state - hibernated or not
++ */
++extern uint32_t dwc_otg_get_core_state(dwc_otg_core_if_t * core_if);
++
++/**
++ * Set value of prtpwr field from the HPRT0 register
++ */
++extern void dwc_otg_set_prtpower(dwc_otg_core_if_t * core_if, uint32_t val);
++
++/**
++ * Get value of prtsusp field from the HPRT0 regsiter
++ */
++extern uint32_t dwc_otg_get_prtsuspend(dwc_otg_core_if_t * core_if);
++/**
++ * Set value of prtpwr field from the HPRT0 register
++ */
++extern void dwc_otg_set_prtsuspend(dwc_otg_core_if_t * core_if, uint32_t val);
++
++/**
++ * Get value of ModeChTimEn field from the HCFG regsiter
++ */
++extern uint32_t dwc_otg_get_mode_ch_tim(dwc_otg_core_if_t * core_if);
++/**
++ * Set value of ModeChTimEn field from the HCFG regsiter
++ */
++extern void dwc_otg_set_mode_ch_tim(dwc_otg_core_if_t * core_if, uint32_t val);
++
++/**
++ * Get value of Fram Interval field from the HFIR regsiter
++ */
++extern uint32_t dwc_otg_get_fr_interval(dwc_otg_core_if_t * core_if);
++/**
++ * Set value of Frame Interval field from the HFIR regsiter
++ */
++extern void dwc_otg_set_fr_interval(dwc_otg_core_if_t * core_if, uint32_t val);
++
++/**
++ * Set value of prtres field from the HPRT0 register
++ *FIXME Remove?
++ */
++extern void dwc_otg_set_prtresume(dwc_otg_core_if_t * core_if, uint32_t val);
++
++/**
++ * Get value of rmtwkupsig bit in DCTL register
++ */
++extern uint32_t dwc_otg_get_remotewakesig(dwc_otg_core_if_t * core_if);
++
++/**
++ * Get value of prt_sleep_sts field from the GLPMCFG register
++ */
++extern uint32_t dwc_otg_get_lpm_portsleepstatus(dwc_otg_core_if_t * core_if);
++
++/**
++ * Get value of rem_wkup_en field from the GLPMCFG register
++ */
++extern uint32_t dwc_otg_get_lpm_remotewakeenabled(dwc_otg_core_if_t * core_if);
++
++/**
++ * Get value of appl_resp field from the GLPMCFG register
++ */
++extern uint32_t dwc_otg_get_lpmresponse(dwc_otg_core_if_t * core_if);
++/**
++ * Set value of appl_resp field from the GLPMCFG register
++ */
++extern void dwc_otg_set_lpmresponse(dwc_otg_core_if_t * core_if, uint32_t val);
++
++/**
++ * Get value of hsic_connect field from the GLPMCFG register
++ */
++extern uint32_t dwc_otg_get_hsic_connect(dwc_otg_core_if_t * core_if);
++/**
++ * Set value of hsic_connect field from the GLPMCFG register
++ */
++extern void dwc_otg_set_hsic_connect(dwc_otg_core_if_t * core_if, uint32_t val);
++
++/**
++ * Get value of inv_sel_hsic field from the GLPMCFG register.
++ */
++extern uint32_t dwc_otg_get_inv_sel_hsic(dwc_otg_core_if_t * core_if);
++/**
++ * Set value of inv_sel_hsic field from the GLPMFG register.
++ */
++extern void dwc_otg_set_inv_sel_hsic(dwc_otg_core_if_t * core_if, uint32_t val);
++
++/*
++ * Some functions for accessing registers
++ */
++
++/**
++ * GOTGCTL register
++ */
++extern uint32_t dwc_otg_get_gotgctl(dwc_otg_core_if_t * core_if);
++extern void dwc_otg_set_gotgctl(dwc_otg_core_if_t * core_if, uint32_t val);
++
++/**
++ * GUSBCFG register
++ */
++extern uint32_t dwc_otg_get_gusbcfg(dwc_otg_core_if_t * core_if);
++extern void dwc_otg_set_gusbcfg(dwc_otg_core_if_t * core_if, uint32_t val);
++
++/**
++ * GRXFSIZ register
++ */
++extern uint32_t dwc_otg_get_grxfsiz(dwc_otg_core_if_t * core_if);
++extern void dwc_otg_set_grxfsiz(dwc_otg_core_if_t * core_if, uint32_t val);
++
++/**
++ * GNPTXFSIZ register
++ */
++extern uint32_t dwc_otg_get_gnptxfsiz(dwc_otg_core_if_t * core_if);
++extern void dwc_otg_set_gnptxfsiz(dwc_otg_core_if_t * core_if, uint32_t val);
++
++extern uint32_t dwc_otg_get_gpvndctl(dwc_otg_core_if_t * core_if);
++extern void dwc_otg_set_gpvndctl(dwc_otg_core_if_t * core_if, uint32_t val);
++
++/**
++ * GGPIO register
++ */
++extern uint32_t dwc_otg_get_ggpio(dwc_otg_core_if_t * core_if);
++extern void dwc_otg_set_ggpio(dwc_otg_core_if_t * core_if, uint32_t val);
++
++/**
++ * GUID register
++ */
++extern uint32_t dwc_otg_get_guid(dwc_otg_core_if_t * core_if);
++extern void dwc_otg_set_guid(dwc_otg_core_if_t * core_if, uint32_t val);
++
++/**
++ * HPRT0 register
++ */
++extern uint32_t dwc_otg_get_hprt0(dwc_otg_core_if_t * core_if);
++extern void dwc_otg_set_hprt0(dwc_otg_core_if_t * core_if, uint32_t val);
++
++/**
++ * GHPTXFSIZE
++ */
++extern uint32_t dwc_otg_get_hptxfsiz(dwc_otg_core_if_t * core_if);
++
++/** @} */
++
++#endif /* __DWC_CORE_IF_H__ */
+diff -Nur linux-4.1.3/drivers/usb/host/dwc_otg/dwc_otg_dbg.h linux-xbian-rpi/drivers/usb/host/dwc_otg/dwc_otg_dbg.h
+--- linux-4.1.3/drivers/usb/host/dwc_otg/dwc_otg_dbg.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/usb/host/dwc_otg/dwc_otg_dbg.h 2015-07-28 01:20:58.445156473 +0200
+@@ -0,0 +1,117 @@
++/* ==========================================================================
++ *
++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++ * otherwise expressly agreed to in writing between Synopsys and you.
++ *
++ * The Software IS NOT an item of Licensed Software or Licensed Product under
++ * any End User Software License Agreement or Agreement for Licensed Product
++ * with Synopsys or any supplement thereto. You are permitted to use and
++ * redistribute this Software in source and binary forms, with or without
++ * modification, provided that redistributions of source code must retain this
++ * notice. You may not view, use, disclose, copy or distribute this file or
++ * any information contained herein except pursuant to this license grant from
++ * Synopsys. If you do not agree with this notice, including the disclaimer
++ * below, then you are not authorized to use the Software.
++ *
++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++ * DAMAGE.
++ * ========================================================================== */
++
++#ifndef __DWC_OTG_DBG_H__
++#define __DWC_OTG_DBG_H__
++
++/** @file
++ * This file defines debug levels.
++ * Debugging support vanishes in non-debug builds.
++ */
++
++/**
++ * The Debug Level bit-mask variable.
++ */
++extern uint32_t g_dbg_lvl;
++/**
++ * Set the Debug Level variable.
++ */
++static inline uint32_t SET_DEBUG_LEVEL(const uint32_t new)
++{
++ uint32_t old = g_dbg_lvl;
++ g_dbg_lvl = new;
++ return old;
++}
++
++#define DBG_USER (0x1)
++/** When debug level has the DBG_CIL bit set, display CIL Debug messages. */
++#define DBG_CIL (0x2)
++/** When debug level has the DBG_CILV bit set, display CIL Verbose debug
++ * messages */
++#define DBG_CILV (0x20)
++/** When debug level has the DBG_PCD bit set, display PCD (Device) debug
++ * messages */
++#define DBG_PCD (0x4)
++/** When debug level has the DBG_PCDV set, display PCD (Device) Verbose debug
++ * messages */
++#define DBG_PCDV (0x40)
++/** When debug level has the DBG_HCD bit set, display Host debug messages */
++#define DBG_HCD (0x8)
++/** When debug level has the DBG_HCDV bit set, display Verbose Host debug
++ * messages */
++#define DBG_HCDV (0x80)
++/** When debug level has the DBG_HCD_URB bit set, display enqueued URBs in host
++ * mode. */
++#define DBG_HCD_URB (0x800)
++/** When debug level has the DBG_HCDI bit set, display host interrupt
++ * messages. */
++#define DBG_HCDI (0x1000)
++
++/** When debug level has any bit set, display debug messages */
++#define DBG_ANY (0xFF)
++
++/** All debug messages off */
++#define DBG_OFF 0
++
++/** Prefix string for DWC_DEBUG print macros. */
++#define USB_DWC "DWC_otg: "
++
++/**
++ * Print a debug message when the Global debug level variable contains
++ * the bit defined in <code>lvl</code>.
++ *
++ * @param[in] lvl - Debug level, use one of the DBG_ constants above.
++ * @param[in] x - like printf
++ *
++ * Example:<p>
++ * <code>
++ * DWC_DEBUGPL( DBG_ANY, "%s(%p)\n", __func__, _reg_base_addr);
++ * </code>
++ * <br>
++ * results in:<br>
++ * <code>
++ * usb-DWC_otg: dwc_otg_cil_init(ca867000)
++ * </code>
++ */
++#ifdef DEBUG
++
++# define DWC_DEBUGPL(lvl, x...) do{ if ((lvl)&g_dbg_lvl)__DWC_DEBUG(USB_DWC x ); }while(0)
++# define DWC_DEBUGP(x...) DWC_DEBUGPL(DBG_ANY, x )
++
++# define CHK_DEBUG_LEVEL(level) ((level) & g_dbg_lvl)
++
++#else
++
++# define DWC_DEBUGPL(lvl, x...) do{}while(0)
++# define DWC_DEBUGP(x...)
++
++# define CHK_DEBUG_LEVEL(level) (0)
++
++#endif /*DEBUG*/
++#endif
+diff -Nur linux-4.1.3/drivers/usb/host/dwc_otg/dwc_otg_driver.c linux-xbian-rpi/drivers/usb/host/dwc_otg/dwc_otg_driver.c
+--- linux-4.1.3/drivers/usb/host/dwc_otg/dwc_otg_driver.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/usb/host/dwc_otg/dwc_otg_driver.c 2015-07-28 01:20:58.445156473 +0200
+@@ -0,0 +1,1757 @@
++/* ==========================================================================
++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.c $
++ * $Revision: #92 $
++ * $Date: 2012/08/10 $
++ * $Change: 2047372 $
++ *
++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++ * otherwise expressly agreed to in writing between Synopsys and you.
++ *
++ * The Software IS NOT an item of Licensed Software or Licensed Product under
++ * any End User Software License Agreement or Agreement for Licensed Product
++ * with Synopsys or any supplement thereto. You are permitted to use and
++ * redistribute this Software in source and binary forms, with or without
++ * modification, provided that redistributions of source code must retain this
++ * notice. You may not view, use, disclose, copy or distribute this file or
++ * any information contained herein except pursuant to this license grant from
++ * Synopsys. If you do not agree with this notice, including the disclaimer
++ * below, then you are not authorized to use the Software.
++ *
++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++ * DAMAGE.
++ * ========================================================================== */
++
++/** @file
++ * The dwc_otg_driver module provides the initialization and cleanup entry
++ * points for the DWC_otg driver. This module will be dynamically installed
++ * after Linux is booted using the insmod command. When the module is
++ * installed, the dwc_otg_driver_init function is called. When the module is
++ * removed (using rmmod), the dwc_otg_driver_cleanup function is called.
++ *
++ * This module also defines a data structure for the dwc_otg_driver, which is
++ * used in conjunction with the standard ARM lm_device structure. These
++ * structures allow the OTG driver to comply with the standard Linux driver
++ * model in which devices and drivers are registered with a bus driver. This
++ * has the benefit that Linux can expose attributes of the driver and device
++ * in its special sysfs file system. Users can then read or write files in
++ * this file system to perform diagnostics on the driver components or the
++ * device.
++ */
++
++#include "dwc_otg_os_dep.h"
++#include "dwc_os.h"
++#include "dwc_otg_dbg.h"
++#include "dwc_otg_driver.h"
++#include "dwc_otg_attr.h"
++#include "dwc_otg_core_if.h"
++#include "dwc_otg_pcd_if.h"
++#include "dwc_otg_hcd_if.h"
++#include "dwc_otg_fiq_fsm.h"
++
++#define DWC_DRIVER_VERSION "3.00a 10-AUG-2012"
++#define DWC_DRIVER_DESC "HS OTG USB Controller driver"
++
++bool microframe_schedule=true;
++
++static const char dwc_driver_name[] = "dwc_otg";
++
++
++extern int pcd_init(
++#ifdef LM_INTERFACE
++ struct lm_device *_dev
++#elif defined(PCI_INTERFACE)
++ struct pci_dev *_dev
++#elif defined(PLATFORM_INTERFACE)
++ struct platform_device *dev
++#endif
++ );
++extern int hcd_init(
++#ifdef LM_INTERFACE
++ struct lm_device *_dev
++#elif defined(PCI_INTERFACE)
++ struct pci_dev *_dev
++#elif defined(PLATFORM_INTERFACE)
++ struct platform_device *dev
++#endif
++ );
++
++extern int pcd_remove(
++#ifdef LM_INTERFACE
++ struct lm_device *_dev
++#elif defined(PCI_INTERFACE)
++ struct pci_dev *_dev
++#elif defined(PLATFORM_INTERFACE)
++ struct platform_device *_dev
++#endif
++ );
++
++extern void hcd_remove(
++#ifdef LM_INTERFACE
++ struct lm_device *_dev
++#elif defined(PCI_INTERFACE)
++ struct pci_dev *_dev
++#elif defined(PLATFORM_INTERFACE)
++ struct platform_device *_dev
++#endif
++ );
++
++extern void dwc_otg_adp_start(dwc_otg_core_if_t * core_if, uint8_t is_host);
++
++/*-------------------------------------------------------------------------*/
++/* Encapsulate the module parameter settings */
++
++struct dwc_otg_driver_module_params {
++ int32_t opt;
++ int32_t otg_cap;
++ int32_t dma_enable;
++ int32_t dma_desc_enable;
++ int32_t dma_burst_size;
++ int32_t speed;
++ int32_t host_support_fs_ls_low_power;
++ int32_t host_ls_low_power_phy_clk;
++ int32_t enable_dynamic_fifo;
++ int32_t data_fifo_size;
++ int32_t dev_rx_fifo_size;
++ int32_t dev_nperio_tx_fifo_size;
++ uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];
++ int32_t host_rx_fifo_size;
++ int32_t host_nperio_tx_fifo_size;
++ int32_t host_perio_tx_fifo_size;
++ int32_t max_transfer_size;
++ int32_t max_packet_count;
++ int32_t host_channels;
++ int32_t dev_endpoints;
++ int32_t phy_type;
++ int32_t phy_utmi_width;
++ int32_t phy_ulpi_ddr;
++ int32_t phy_ulpi_ext_vbus;
++ int32_t i2c_enable;
++ int32_t ulpi_fs_ls;
++ int32_t ts_dline;
++ int32_t en_multiple_tx_fifo;
++ uint32_t dev_tx_fifo_size[MAX_TX_FIFOS];
++ uint32_t thr_ctl;
++ uint32_t tx_thr_length;
++ uint32_t rx_thr_length;
++ int32_t pti_enable;
++ int32_t mpi_enable;
++ int32_t lpm_enable;
++ int32_t ic_usb_cap;
++ int32_t ahb_thr_ratio;
++ int32_t power_down;
++ int32_t reload_ctl;
++ int32_t dev_out_nak;
++ int32_t cont_on_bna;
++ int32_t ahb_single;
++ int32_t otg_ver;
++ int32_t adp_enable;
++};
++
++static struct dwc_otg_driver_module_params dwc_otg_module_params = {
++ .opt = -1,
++ .otg_cap = -1,
++ .dma_enable = -1,
++ .dma_desc_enable = -1,
++ .dma_burst_size = -1,
++ .speed = -1,
++ .host_support_fs_ls_low_power = -1,
++ .host_ls_low_power_phy_clk = -1,
++ .enable_dynamic_fifo = -1,
++ .data_fifo_size = -1,
++ .dev_rx_fifo_size = -1,
++ .dev_nperio_tx_fifo_size = -1,
++ .dev_perio_tx_fifo_size = {
++ /* dev_perio_tx_fifo_size_1 */
++ -1,
++ -1,
++ -1,
++ -1,
++ -1,
++ -1,
++ -1,
++ -1,
++ -1,
++ -1,
++ -1,
++ -1,
++ -1,
++ -1,
++ -1
++ /* 15 */
++ },
++ .host_rx_fifo_size = -1,
++ .host_nperio_tx_fifo_size = -1,
++ .host_perio_tx_fifo_size = -1,
++ .max_transfer_size = -1,
++ .max_packet_count = -1,
++ .host_channels = -1,
++ .dev_endpoints = -1,
++ .phy_type = -1,
++ .phy_utmi_width = -1,
++ .phy_ulpi_ddr = -1,
++ .phy_ulpi_ext_vbus = -1,
++ .i2c_enable = -1,
++ .ulpi_fs_ls = -1,
++ .ts_dline = -1,
++ .en_multiple_tx_fifo = -1,
++ .dev_tx_fifo_size = {
++ /* dev_tx_fifo_size */
++ -1,
++ -1,
++ -1,
++ -1,
++ -1,
++ -1,
++ -1,
++ -1,
++ -1,
++ -1,
++ -1,
++ -1,
++ -1,
++ -1,
++ -1
++ /* 15 */
++ },
++ .thr_ctl = -1,
++ .tx_thr_length = -1,
++ .rx_thr_length = -1,
++ .pti_enable = -1,
++ .mpi_enable = -1,
++ .lpm_enable = 0,
++ .ic_usb_cap = -1,
++ .ahb_thr_ratio = -1,
++ .power_down = -1,
++ .reload_ctl = -1,
++ .dev_out_nak = -1,
++ .cont_on_bna = -1,
++ .ahb_single = -1,
++ .otg_ver = -1,
++ .adp_enable = -1,
++};
++
++//Global variable to switch the fiq fix on or off
++bool fiq_enable = 1;
++// Global variable to enable the split transaction fix
++bool fiq_fsm_enable = true;
++//Bulk split-transaction NAK holdoff in microframes
++uint16_t nak_holdoff = 8;
++
++unsigned short fiq_fsm_mask = 0x07;
++
++/**
++ * This function shows the Driver Version.
++ */
++static ssize_t version_show(struct device_driver *dev, char *buf)
++{
++ return snprintf(buf, sizeof(DWC_DRIVER_VERSION) + 2, "%s\n",
++ DWC_DRIVER_VERSION);
++}
++
++static DRIVER_ATTR(version, S_IRUGO, version_show, NULL);
++
++/**
++ * Global Debug Level Mask.
++ */
++uint32_t g_dbg_lvl = 0; /* OFF */
++
++/**
++ * This function shows the driver Debug Level.
++ */
++static ssize_t dbg_level_show(struct device_driver *drv, char *buf)
++{
++ return sprintf(buf, "0x%0x\n", g_dbg_lvl);
++}
++
++/**
++ * This function stores the driver Debug Level.
++ */
++static ssize_t dbg_level_store(struct device_driver *drv, const char *buf,
++ size_t count)
++{
++ g_dbg_lvl = simple_strtoul(buf, NULL, 16);
++ return count;
++}
++
++static DRIVER_ATTR(debuglevel, S_IRUGO | S_IWUSR, dbg_level_show,
++ dbg_level_store);
++
++/**
++ * This function is called during module intialization
++ * to pass module parameters to the DWC_OTG CORE.
++ */
++static int set_parameters(dwc_otg_core_if_t * core_if)
++{
++ int retval = 0;
++ int i;
++
++ if (dwc_otg_module_params.otg_cap != -1) {
++ retval +=
++ dwc_otg_set_param_otg_cap(core_if,
++ dwc_otg_module_params.otg_cap);
++ }
++ if (dwc_otg_module_params.dma_enable != -1) {
++ retval +=
++ dwc_otg_set_param_dma_enable(core_if,
++ dwc_otg_module_params.
++ dma_enable);
++ }
++ if (dwc_otg_module_params.dma_desc_enable != -1) {
++ retval +=
++ dwc_otg_set_param_dma_desc_enable(core_if,
++ dwc_otg_module_params.
++ dma_desc_enable);
++ }
++ if (dwc_otg_module_params.opt != -1) {
++ retval +=
++ dwc_otg_set_param_opt(core_if, dwc_otg_module_params.opt);
++ }
++ if (dwc_otg_module_params.dma_burst_size != -1) {
++ retval +=
++ dwc_otg_set_param_dma_burst_size(core_if,
++ dwc_otg_module_params.
++ dma_burst_size);
++ }
++ if (dwc_otg_module_params.host_support_fs_ls_low_power != -1) {
++ retval +=
++ dwc_otg_set_param_host_support_fs_ls_low_power(core_if,
++ dwc_otg_module_params.
++ host_support_fs_ls_low_power);
++ }
++ if (dwc_otg_module_params.enable_dynamic_fifo != -1) {
++ retval +=
++ dwc_otg_set_param_enable_dynamic_fifo(core_if,
++ dwc_otg_module_params.
++ enable_dynamic_fifo);
++ }
++ if (dwc_otg_module_params.data_fifo_size != -1) {
++ retval +=
++ dwc_otg_set_param_data_fifo_size(core_if,
++ dwc_otg_module_params.
++ data_fifo_size);
++ }
++ if (dwc_otg_module_params.dev_rx_fifo_size != -1) {
++ retval +=
++ dwc_otg_set_param_dev_rx_fifo_size(core_if,
++ dwc_otg_module_params.
++ dev_rx_fifo_size);
++ }
++ if (dwc_otg_module_params.dev_nperio_tx_fifo_size != -1) {
++ retval +=
++ dwc_otg_set_param_dev_nperio_tx_fifo_size(core_if,
++ dwc_otg_module_params.
++ dev_nperio_tx_fifo_size);
++ }
++ if (dwc_otg_module_params.host_rx_fifo_size != -1) {
++ retval +=
++ dwc_otg_set_param_host_rx_fifo_size(core_if,
++ dwc_otg_module_params.host_rx_fifo_size);
++ }
++ if (dwc_otg_module_params.host_nperio_tx_fifo_size != -1) {
++ retval +=
++ dwc_otg_set_param_host_nperio_tx_fifo_size(core_if,
++ dwc_otg_module_params.
++ host_nperio_tx_fifo_size);
++ }
++ if (dwc_otg_module_params.host_perio_tx_fifo_size != -1) {
++ retval +=
++ dwc_otg_set_param_host_perio_tx_fifo_size(core_if,
++ dwc_otg_module_params.
++ host_perio_tx_fifo_size);
++ }
++ if (dwc_otg_module_params.max_transfer_size != -1) {
++ retval +=
++ dwc_otg_set_param_max_transfer_size(core_if,
++ dwc_otg_module_params.
++ max_transfer_size);
++ }
++ if (dwc_otg_module_params.max_packet_count != -1) {
++ retval +=
++ dwc_otg_set_param_max_packet_count(core_if,
++ dwc_otg_module_params.
++ max_packet_count);
++ }
++ if (dwc_otg_module_params.host_channels != -1) {
++ retval +=
++ dwc_otg_set_param_host_channels(core_if,
++ dwc_otg_module_params.
++ host_channels);
++ }
++ if (dwc_otg_module_params.dev_endpoints != -1) {
++ retval +=
++ dwc_otg_set_param_dev_endpoints(core_if,
++ dwc_otg_module_params.
++ dev_endpoints);
++ }
++ if (dwc_otg_module_params.phy_type != -1) {
++ retval +=
++ dwc_otg_set_param_phy_type(core_if,
++ dwc_otg_module_params.phy_type);
++ }
++ if (dwc_otg_module_params.speed != -1) {
++ retval +=
++ dwc_otg_set_param_speed(core_if,
++ dwc_otg_module_params.speed);
++ }
++ if (dwc_otg_module_params.host_ls_low_power_phy_clk != -1) {
++ retval +=
++ dwc_otg_set_param_host_ls_low_power_phy_clk(core_if,
++ dwc_otg_module_params.
++ host_ls_low_power_phy_clk);
++ }
++ if (dwc_otg_module_params.phy_ulpi_ddr != -1) {
++ retval +=
++ dwc_otg_set_param_phy_ulpi_ddr(core_if,
++ dwc_otg_module_params.
++ phy_ulpi_ddr);
++ }
++ if (dwc_otg_module_params.phy_ulpi_ext_vbus != -1) {
++ retval +=
++ dwc_otg_set_param_phy_ulpi_ext_vbus(core_if,
++ dwc_otg_module_params.
++ phy_ulpi_ext_vbus);
++ }
++ if (dwc_otg_module_params.phy_utmi_width != -1) {
++ retval +=
++ dwc_otg_set_param_phy_utmi_width(core_if,
++ dwc_otg_module_params.
++ phy_utmi_width);
++ }
++ if (dwc_otg_module_params.ulpi_fs_ls != -1) {
++ retval +=
++ dwc_otg_set_param_ulpi_fs_ls(core_if,
++ dwc_otg_module_params.ulpi_fs_ls);
++ }
++ if (dwc_otg_module_params.ts_dline != -1) {
++ retval +=
++ dwc_otg_set_param_ts_dline(core_if,
++ dwc_otg_module_params.ts_dline);
++ }
++ if (dwc_otg_module_params.i2c_enable != -1) {
++ retval +=
++ dwc_otg_set_param_i2c_enable(core_if,
++ dwc_otg_module_params.
++ i2c_enable);
++ }
++ if (dwc_otg_module_params.en_multiple_tx_fifo != -1) {
++ retval +=
++ dwc_otg_set_param_en_multiple_tx_fifo(core_if,
++ dwc_otg_module_params.
++ en_multiple_tx_fifo);
++ }
++ for (i = 0; i < 15; i++) {
++ if (dwc_otg_module_params.dev_perio_tx_fifo_size[i] != -1) {
++ retval +=
++ dwc_otg_set_param_dev_perio_tx_fifo_size(core_if,
++ dwc_otg_module_params.
++ dev_perio_tx_fifo_size
++ [i], i);
++ }
++ }
++
++ for (i = 0; i < 15; i++) {
++ if (dwc_otg_module_params.dev_tx_fifo_size[i] != -1) {
++ retval += dwc_otg_set_param_dev_tx_fifo_size(core_if,
++ dwc_otg_module_params.
++ dev_tx_fifo_size
++ [i], i);
++ }
++ }
++ if (dwc_otg_module_params.thr_ctl != -1) {
++ retval +=
++ dwc_otg_set_param_thr_ctl(core_if,
++ dwc_otg_module_params.thr_ctl);
++ }
++ if (dwc_otg_module_params.mpi_enable != -1) {
++ retval +=
++ dwc_otg_set_param_mpi_enable(core_if,
++ dwc_otg_module_params.
++ mpi_enable);
++ }
++ if (dwc_otg_module_params.pti_enable != -1) {
++ retval +=
++ dwc_otg_set_param_pti_enable(core_if,
++ dwc_otg_module_params.
++ pti_enable);
++ }
++ if (dwc_otg_module_params.lpm_enable != -1) {
++ retval +=
++ dwc_otg_set_param_lpm_enable(core_if,
++ dwc_otg_module_params.
++ lpm_enable);
++ }
++ if (dwc_otg_module_params.ic_usb_cap != -1) {
++ retval +=
++ dwc_otg_set_param_ic_usb_cap(core_if,
++ dwc_otg_module_params.
++ ic_usb_cap);
++ }
++ if (dwc_otg_module_params.tx_thr_length != -1) {
++ retval +=
++ dwc_otg_set_param_tx_thr_length(core_if,
++ dwc_otg_module_params.tx_thr_length);
++ }
++ if (dwc_otg_module_params.rx_thr_length != -1) {
++ retval +=
++ dwc_otg_set_param_rx_thr_length(core_if,
++ dwc_otg_module_params.
++ rx_thr_length);
++ }
++ if (dwc_otg_module_params.ahb_thr_ratio != -1) {
++ retval +=
++ dwc_otg_set_param_ahb_thr_ratio(core_if,
++ dwc_otg_module_params.ahb_thr_ratio);
++ }
++ if (dwc_otg_module_params.power_down != -1) {
++ retval +=
++ dwc_otg_set_param_power_down(core_if,
++ dwc_otg_module_params.power_down);
++ }
++ if (dwc_otg_module_params.reload_ctl != -1) {
++ retval +=
++ dwc_otg_set_param_reload_ctl(core_if,
++ dwc_otg_module_params.reload_ctl);
++ }
++
++ if (dwc_otg_module_params.dev_out_nak != -1) {
++ retval +=
++ dwc_otg_set_param_dev_out_nak(core_if,
++ dwc_otg_module_params.dev_out_nak);
++ }
++
++ if (dwc_otg_module_params.cont_on_bna != -1) {
++ retval +=
++ dwc_otg_set_param_cont_on_bna(core_if,
++ dwc_otg_module_params.cont_on_bna);
++ }
++
++ if (dwc_otg_module_params.ahb_single != -1) {
++ retval +=
++ dwc_otg_set_param_ahb_single(core_if,
++ dwc_otg_module_params.ahb_single);
++ }
++
++ if (dwc_otg_module_params.otg_ver != -1) {
++ retval +=
++ dwc_otg_set_param_otg_ver(core_if,
++ dwc_otg_module_params.otg_ver);
++ }
++ if (dwc_otg_module_params.adp_enable != -1) {
++ retval +=
++ dwc_otg_set_param_adp_enable(core_if,
++ dwc_otg_module_params.
++ adp_enable);
++ }
++ return retval;
++}
++
++/**
++ * This function is the top level interrupt handler for the Common
++ * (Device and host modes) interrupts.
++ */
++static irqreturn_t dwc_otg_common_irq(int irq, void *dev)
++{
++ int32_t retval = IRQ_NONE;
++
++ retval = dwc_otg_handle_common_intr(dev);
++ if (retval != 0) {
++ S3C2410X_CLEAR_EINTPEND();
++ }
++ return IRQ_RETVAL(retval);
++}
++
++/**
++ * This function is called when a lm_device is unregistered with the
++ * dwc_otg_driver. This happens, for example, when the rmmod command is
++ * executed. The device may or may not be electrically present. If it is
++ * present, the driver stops device processing. Any resources used on behalf
++ * of this device are freed.
++ *
++ * @param _dev
++ */
++#ifdef LM_INTERFACE
++#define REM_RETVAL(n)
++static void dwc_otg_driver_remove( struct lm_device *_dev )
++{ dwc_otg_device_t *otg_dev = lm_get_drvdata(_dev);
++#elif defined(PCI_INTERFACE)
++#define REM_RETVAL(n)
++static void dwc_otg_driver_remove( struct pci_dev *_dev )
++{ dwc_otg_device_t *otg_dev = pci_get_drvdata(_dev);
++#elif defined(PLATFORM_INTERFACE)
++#define REM_RETVAL(n) n
++static int dwc_otg_driver_remove( struct platform_device *_dev )
++{ dwc_otg_device_t *otg_dev = platform_get_drvdata(_dev);
++#endif
++
++ DWC_DEBUGPL(DBG_ANY, "%s(%p) otg_dev %p\n", __func__, _dev, otg_dev);
++
++ if (!otg_dev) {
++ /* Memory allocation for the dwc_otg_device failed. */
++ DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
++ return REM_RETVAL(-ENOMEM);
++ }
++#ifndef DWC_DEVICE_ONLY
++ if (otg_dev->hcd) {
++ hcd_remove(_dev);
++ } else {
++ DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
++ return REM_RETVAL(-EINVAL);
++ }
++#endif
++
++#ifndef DWC_HOST_ONLY
++ if (otg_dev->pcd) {
++ pcd_remove(_dev);
++ } else {
++ DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->pcd NULL!\n", __func__);
++ return REM_RETVAL(-EINVAL);
++ }
++#endif
++ /*
++ * Free the IRQ
++ */
++ if (otg_dev->common_irq_installed) {
++#ifdef PLATFORM_INTERFACE
++ free_irq(platform_get_irq(_dev, 0), otg_dev);
++#else
++ free_irq(_dev->irq, otg_dev);
++#endif
++ } else {
++ DWC_DEBUGPL(DBG_ANY, "%s: There is no installed irq!\n", __func__);
++ return REM_RETVAL(-ENXIO);
++ }
++
++ if (otg_dev->core_if) {
++ dwc_otg_cil_remove(otg_dev->core_if);
++ } else {
++ DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->core_if NULL!\n", __func__);
++ return REM_RETVAL(-ENXIO);
++ }
++
++ /*
++ * Remove the device attributes
++ */
++ dwc_otg_attr_remove(_dev);
++
++ /*
++ * Return the memory.
++ */
++ if (otg_dev->os_dep.base) {
++ iounmap(otg_dev->os_dep.base);
++ }
++ DWC_FREE(otg_dev);
++
++ /*
++ * Clear the drvdata pointer.
++ */
++#ifdef LM_INTERFACE
++ lm_set_drvdata(_dev, 0);
++#elif defined(PCI_INTERFACE)
++ release_mem_region(otg_dev->os_dep.rsrc_start,
++ otg_dev->os_dep.rsrc_len);
++ pci_set_drvdata(_dev, 0);
++#elif defined(PLATFORM_INTERFACE)
++ platform_set_drvdata(_dev, 0);
++#endif
++ return REM_RETVAL(0);
++}
++
++/**
++ * This function is called when an lm_device is bound to a
++ * dwc_otg_driver. It creates the driver components required to
++ * control the device (CIL, HCD, and PCD) and it initializes the
++ * device. The driver components are stored in a dwc_otg_device
++ * structure. A reference to the dwc_otg_device is saved in the
++ * lm_device. This allows the driver to access the dwc_otg_device
++ * structure on subsequent calls to driver methods for this device.
++ *
++ * @param _dev Bus device
++ */
++static int dwc_otg_driver_probe(
++#ifdef LM_INTERFACE
++ struct lm_device *_dev
++#elif defined(PCI_INTERFACE)
++ struct pci_dev *_dev,
++ const struct pci_device_id *id
++#elif defined(PLATFORM_INTERFACE)
++ struct platform_device *_dev
++#endif
++ )
++{
++ int retval = 0;
++ dwc_otg_device_t *dwc_otg_device;
++ int devirq;
++
++ dev_dbg(&_dev->dev, "dwc_otg_driver_probe(%p)\n", _dev);
++#ifdef LM_INTERFACE
++ dev_dbg(&_dev->dev, "start=0x%08x\n", (unsigned)_dev->resource.start);
++#elif defined(PCI_INTERFACE)
++ if (!id) {
++ DWC_ERROR("Invalid pci_device_id %p", id);
++ return -EINVAL;
++ }
++
++ if (!_dev || (pci_enable_device(_dev) < 0)) {
++ DWC_ERROR("Invalid pci_device %p", _dev);
++ return -ENODEV;
++ }
++ dev_dbg(&_dev->dev, "start=0x%08x\n", (unsigned)pci_resource_start(_dev,0));
++ /* other stuff needed as well? */
++
++#elif defined(PLATFORM_INTERFACE)
++ dev_dbg(&_dev->dev, "start=0x%08x (len 0x%x)\n",
++ (unsigned)_dev->resource->start,
++ (unsigned)(_dev->resource->end - _dev->resource->start));
++#endif
++
++ dwc_otg_device = DWC_ALLOC(sizeof(dwc_otg_device_t));
++
++ if (!dwc_otg_device) {
++ dev_err(&_dev->dev, "kmalloc of dwc_otg_device failed\n");
++ return -ENOMEM;
++ }
++
++ memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
++ dwc_otg_device->os_dep.reg_offset = 0xFFFFFFFF;
++ dwc_otg_device->os_dep.platformdev = _dev;
++
++ /*
++ * Map the DWC_otg Core memory into virtual address space.
++ */
++#ifdef LM_INTERFACE
++ dwc_otg_device->os_dep.base = ioremap(_dev->resource.start, SZ_256K);
++
++ if (!dwc_otg_device->os_dep.base) {
++ dev_err(&_dev->dev, "ioremap() failed\n");
++ DWC_FREE(dwc_otg_device);
++ return -ENOMEM;
++ }
++ dev_dbg(&_dev->dev, "base=0x%08x\n",
++ (unsigned)dwc_otg_device->os_dep.base);
++#elif defined(PCI_INTERFACE)
++ _dev->current_state = PCI_D0;
++ _dev->dev.power.power_state = PMSG_ON;
++
++ if (!_dev->irq) {
++ DWC_ERROR("Found HC with no IRQ. Check BIOS/PCI %s setup!",
++ pci_name(_dev));
++ iounmap(dwc_otg_device->os_dep.base);
++ DWC_FREE(dwc_otg_device);
++ return -ENODEV;
++ }
++
++ dwc_otg_device->os_dep.rsrc_start = pci_resource_start(_dev, 0);
++ dwc_otg_device->os_dep.rsrc_len = pci_resource_len(_dev, 0);
++ DWC_DEBUGPL(DBG_ANY, "PCI resource: start=%08x, len=%08x\n",
++ (unsigned)dwc_otg_device->os_dep.rsrc_start,
++ (unsigned)dwc_otg_device->os_dep.rsrc_len);
++ if (!request_mem_region
++ (dwc_otg_device->os_dep.rsrc_start, dwc_otg_device->os_dep.rsrc_len,
++ "dwc_otg")) {
++ dev_dbg(&_dev->dev, "error requesting memory\n");
++ iounmap(dwc_otg_device->os_dep.base);
++ DWC_FREE(dwc_otg_device);
++ return -EFAULT;
++ }
++
++ dwc_otg_device->os_dep.base =
++ ioremap_nocache(dwc_otg_device->os_dep.rsrc_start,
++ dwc_otg_device->os_dep.rsrc_len);
++ if (dwc_otg_device->os_dep.base == NULL) {
++ dev_dbg(&_dev->dev, "error mapping memory\n");
++ release_mem_region(dwc_otg_device->os_dep.rsrc_start,
++ dwc_otg_device->os_dep.rsrc_len);
++ iounmap(dwc_otg_device->os_dep.base);
++ DWC_FREE(dwc_otg_device);
++ return -EFAULT;
++ }
++ dev_dbg(&_dev->dev, "base=0x%p (before adjust) \n",
++ dwc_otg_device->os_dep.base);
++ dwc_otg_device->os_dep.base = (char *)dwc_otg_device->os_dep.base;
++ dev_dbg(&_dev->dev, "base=0x%p (after adjust) \n",
++ dwc_otg_device->os_dep.base);
++ dev_dbg(&_dev->dev, "%s: mapped PA 0x%x to VA 0x%p\n", __func__,
++ (unsigned)dwc_otg_device->os_dep.rsrc_start,
++ dwc_otg_device->os_dep.base);
++
++ pci_set_master(_dev);
++ pci_set_drvdata(_dev, dwc_otg_device);
++#elif defined(PLATFORM_INTERFACE)
++ DWC_DEBUGPL(DBG_ANY,"Platform resource: start=%08x, len=%08x\n",
++ _dev->resource->start,
++ _dev->resource->end - _dev->resource->start + 1);
++#if 1
++ if (!request_mem_region(_dev->resource[0].start,
++ _dev->resource[0].end - _dev->resource[0].start + 1,
++ "dwc_otg")) {
++ dev_dbg(&_dev->dev, "error reserving mapped memory\n");
++ retval = -EFAULT;
++ goto fail;
++ }
++
++ dwc_otg_device->os_dep.base = ioremap_nocache(_dev->resource[0].start,
++ _dev->resource[0].end -
++ _dev->resource[0].start+1);
++ if (fiq_enable)
++ {
++ if (!request_mem_region(_dev->resource[1].start,
++ _dev->resource[1].end - _dev->resource[1].start + 1,
++ "dwc_otg")) {
++ dev_dbg(&_dev->dev, "error reserving mapped memory\n");
++ retval = -EFAULT;
++ goto fail;
++ }
++
++ dwc_otg_device->os_dep.mphi_base = ioremap_nocache(_dev->resource[1].start,
++ _dev->resource[1].end -
++ _dev->resource[1].start + 1);
++ }
++
++#else
++ {
++ struct map_desc desc = {
++ .virtual = IO_ADDRESS((unsigned)_dev->resource->start),
++ .pfn = __phys_to_pfn((unsigned)_dev->resource->start),
++ .length = SZ_128K,
++ .type = MT_DEVICE
++ };
++ iotable_init(&desc, 1);
++ dwc_otg_device->os_dep.base = (void *)desc.virtual;
++ }
++#endif
++ if (!dwc_otg_device->os_dep.base) {
++ dev_err(&_dev->dev, "ioremap() failed\n");
++ retval = -ENOMEM;
++ goto fail;
++ }
++ dev_dbg(&_dev->dev, "base=0x%08x\n",
++ (unsigned)dwc_otg_device->os_dep.base);
++#endif
++
++ /*
++ * Initialize driver data to point to the global DWC_otg
++ * Device structure.
++ */
++#ifdef LM_INTERFACE
++ lm_set_drvdata(_dev, dwc_otg_device);
++#elif defined(PLATFORM_INTERFACE)
++ platform_set_drvdata(_dev, dwc_otg_device);
++#endif
++ dev_dbg(&_dev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device);
++
++ dwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->os_dep.base);
++ DWC_DEBUGPL(DBG_HCDV, "probe of device %p given core_if %p\n",
++ dwc_otg_device, dwc_otg_device->core_if);//GRAYG
++
++ if (!dwc_otg_device->core_if) {
++ dev_err(&_dev->dev, "CIL initialization failed!\n");
++ retval = -ENOMEM;
++ goto fail;
++ }
++
++ dev_dbg(&_dev->dev, "Calling get_gsnpsid\n");
++ /*
++ * Attempt to ensure this device is really a DWC_otg Controller.
++ * Read and verify the SNPSID register contents. The value should be
++ * 0x45F42XXX or 0x45F42XXX, which corresponds to either "OT2" or "OTG3",
++ * as in "OTG version 2.XX" or "OTG version 3.XX".
++ */
++
++ if (((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) != 0x4F542000) &&
++ ((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) != 0x4F543000)) {
++ dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n",
++ dwc_otg_get_gsnpsid(dwc_otg_device->core_if));
++ retval = -EINVAL;
++ goto fail;
++ }
++
++ /*
++ * Validate parameter values.
++ */
++ dev_dbg(&_dev->dev, "Calling set_parameters\n");
++ if (set_parameters(dwc_otg_device->core_if)) {
++ retval = -EINVAL;
++ goto fail;
++ }
++
++ /*
++ * Create Device Attributes in sysfs
++ */
++ dev_dbg(&_dev->dev, "Calling attr_create\n");
++ dwc_otg_attr_create(_dev);
++
++ /*
++ * Disable the global interrupt until all the interrupt
++ * handlers are installed.
++ */
++ dev_dbg(&_dev->dev, "Calling disable_global_interrupts\n");
++ dwc_otg_disable_global_interrupts(dwc_otg_device->core_if);
++
++ /*
++ * Install the interrupt handler for the common interrupts before
++ * enabling common interrupts in core_init below.
++ */
++
++#if defined(PLATFORM_INTERFACE)
++ devirq = platform_get_irq(_dev, fiq_enable ? 0 : 1);
++#else
++ devirq = _dev->irq;
++#endif
++ DWC_DEBUGPL(DBG_CIL, "registering (common) handler for irq%d\n",
++ devirq);
++ dev_dbg(&_dev->dev, "Calling request_irq(%d)\n", devirq);
++ retval = request_irq(devirq, dwc_otg_common_irq,
++ IRQF_SHARED,
++ "dwc_otg", dwc_otg_device);
++ if (retval) {
++ DWC_ERROR("request of irq%d failed\n", devirq);
++ retval = -EBUSY;
++ goto fail;
++ } else {
++ dwc_otg_device->common_irq_installed = 1;
++ }
++
++#ifndef IRQF_TRIGGER_LOW
++#if defined(LM_INTERFACE) || defined(PLATFORM_INTERFACE)
++ dev_dbg(&_dev->dev, "Calling set_irq_type\n");
++ set_irq_type(devirq,
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30))
++ IRQT_LOW
++#else
++ IRQ_TYPE_LEVEL_LOW
++#endif
++ );
++#endif
++#endif /*IRQF_TRIGGER_LOW*/
++
++ /*
++ * Initialize the DWC_otg core.
++ */
++ dev_dbg(&_dev->dev, "Calling dwc_otg_core_init\n");
++ dwc_otg_core_init(dwc_otg_device->core_if);
++
++#ifndef DWC_HOST_ONLY
++ /*
++ * Initialize the PCD
++ */
++ dev_dbg(&_dev->dev, "Calling pcd_init\n");
++ retval = pcd_init(_dev);
++ if (retval != 0) {
++ DWC_ERROR("pcd_init failed\n");
++ dwc_otg_device->pcd = NULL;
++ goto fail;
++ }
++#endif
++#ifndef DWC_DEVICE_ONLY
++ /*
++ * Initialize the HCD
++ */
++ dev_dbg(&_dev->dev, "Calling hcd_init\n");
++ retval = hcd_init(_dev);
++ if (retval != 0) {
++ DWC_ERROR("hcd_init failed\n");
++ dwc_otg_device->hcd = NULL;
++ goto fail;
++ }
++#endif
++ /* Recover from drvdata having been overwritten by hcd_init() */
++#ifdef LM_INTERFACE
++ lm_set_drvdata(_dev, dwc_otg_device);
++#elif defined(PLATFORM_INTERFACE)
++ platform_set_drvdata(_dev, dwc_otg_device);
++#elif defined(PCI_INTERFACE)
++ pci_set_drvdata(_dev, dwc_otg_device);
++ dwc_otg_device->os_dep.pcidev = _dev;
++#endif
++
++ /*
++ * Enable the global interrupt after all the interrupt
++ * handlers are installed if there is no ADP support else
++ * perform initial actions required for Internal ADP logic.
++ */
++ if (!dwc_otg_get_param_adp_enable(dwc_otg_device->core_if)) {
++ dev_dbg(&_dev->dev, "Calling enable_global_interrupts\n");
++ dwc_otg_enable_global_interrupts(dwc_otg_device->core_if);
++ dev_dbg(&_dev->dev, "Done\n");
++ } else
++ dwc_otg_adp_start(dwc_otg_device->core_if,
++ dwc_otg_is_host_mode(dwc_otg_device->core_if));
++
++ return 0;
++
++fail:
++ dwc_otg_driver_remove(_dev);
++ return retval;
++}
++
++/**
++ * This structure defines the methods to be called by a bus driver
++ * during the lifecycle of a device on that bus. Both drivers and
++ * devices are registered with a bus driver. The bus driver matches
++ * devices to drivers based on information in the device and driver
++ * structures.
++ *
++ * The probe function is called when the bus driver matches a device
++ * to this driver. The remove function is called when a device is
++ * unregistered with the bus driver.
++ */
++#ifdef LM_INTERFACE
++static struct lm_driver dwc_otg_driver = {
++ .drv = {.name = (char *)dwc_driver_name,},
++ .probe = dwc_otg_driver_probe,
++ .remove = dwc_otg_driver_remove,
++ // 'suspend' and 'resume' absent
++};
++#elif defined(PCI_INTERFACE)
++static const struct pci_device_id pci_ids[] = { {
++ PCI_DEVICE(0x16c3, 0xabcd),
++ .driver_data =
++ (unsigned long)0xdeadbeef,
++ }, { /* end: all zeroes */ }
++};
++
++MODULE_DEVICE_TABLE(pci, pci_ids);
++
++/* pci driver glue; this is a "new style" PCI driver module */
++static struct pci_driver dwc_otg_driver = {
++ .name = "dwc_otg",
++ .id_table = pci_ids,
++
++ .probe = dwc_otg_driver_probe,
++ .remove = dwc_otg_driver_remove,
++
++ .driver = {
++ .name = (char *)dwc_driver_name,
++ },
++};
++#elif defined(PLATFORM_INTERFACE)
++static struct platform_device_id platform_ids[] = {
++ {
++ .name = "bcm2708_usb",
++ .driver_data = (kernel_ulong_t) 0xdeadbeef,
++ },
++ { /* end: all zeroes */ }
++};
++MODULE_DEVICE_TABLE(platform, platform_ids);
++
++static const struct of_device_id dwc_otg_of_match_table[] = {
++ { .compatible = "brcm,bcm2708-usb", },
++ {},
++};
++MODULE_DEVICE_TABLE(of, dwc_otg_of_match_table);
++
++static struct platform_driver dwc_otg_driver = {
++ .driver = {
++ .name = (char *)dwc_driver_name,
++ .of_match_table = dwc_otg_of_match_table,
++ },
++ .id_table = platform_ids,
++
++ .probe = dwc_otg_driver_probe,
++ .remove = dwc_otg_driver_remove,
++ // no 'shutdown', 'suspend', 'resume', 'suspend_late' or 'resume_early'
++};
++#endif
++
++/**
++ * This function is called when the dwc_otg_driver is installed with the
++ * insmod command. It registers the dwc_otg_driver structure with the
++ * appropriate bus driver. This will cause the dwc_otg_driver_probe function
++ * to be called. In addition, the bus driver will automatically expose
++ * attributes defined for the device and driver in the special sysfs file
++ * system.
++ *
++ * @return
++ */
++static int __init dwc_otg_driver_init(void)
++{
++ int retval = 0;
++ int error;
++ struct device_driver *drv;
++
++ if(fiq_fsm_enable && !fiq_enable) {
++ printk(KERN_WARNING "dwc_otg: fiq_fsm_enable was set without fiq_enable! Correcting.\n");
++ fiq_enable = 1;
++ }
++
++ printk(KERN_INFO "%s: version %s (%s bus)\n", dwc_driver_name,
++ DWC_DRIVER_VERSION,
++#ifdef LM_INTERFACE
++ "logicmodule");
++ retval = lm_driver_register(&dwc_otg_driver);
++ drv = &dwc_otg_driver.drv;
++#elif defined(PCI_INTERFACE)
++ "pci");
++ retval = pci_register_driver(&dwc_otg_driver);
++ drv = &dwc_otg_driver.driver;
++#elif defined(PLATFORM_INTERFACE)
++ "platform");
++ retval = platform_driver_register(&dwc_otg_driver);
++ drv = &dwc_otg_driver.driver;
++#endif
++ if (retval < 0) {
++ printk(KERN_ERR "%s retval=%d\n", __func__, retval);
++ return retval;
++ }
++ printk(KERN_DEBUG "dwc_otg: FIQ %s\n", fiq_enable ? "enabled":"disabled");
++ printk(KERN_DEBUG "dwc_otg: NAK holdoff %s\n", nak_holdoff ? "enabled":"disabled");
++ printk(KERN_DEBUG "dwc_otg: FIQ split-transaction FSM %s\n", fiq_fsm_enable ? "enabled":"disabled");
++
++ error = driver_create_file(drv, &driver_attr_version);
++#ifdef DEBUG
++ error = driver_create_file(drv, &driver_attr_debuglevel);
++#endif
++ return retval;
++}
++
++module_init(dwc_otg_driver_init);
++
++/**
++ * This function is called when the driver is removed from the kernel
++ * with the rmmod command. The driver unregisters itself with its bus
++ * driver.
++ *
++ */
++static void __exit dwc_otg_driver_cleanup(void)
++{
++ printk(KERN_DEBUG "dwc_otg_driver_cleanup()\n");
++
++#ifdef LM_INTERFACE
++ driver_remove_file(&dwc_otg_driver.drv, &driver_attr_debuglevel);
++ driver_remove_file(&dwc_otg_driver.drv, &driver_attr_version);
++ lm_driver_unregister(&dwc_otg_driver);
++#elif defined(PCI_INTERFACE)
++ driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
++ driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version);
++ pci_unregister_driver(&dwc_otg_driver);
++#elif defined(PLATFORM_INTERFACE)
++ driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
++ driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version);
++ platform_driver_unregister(&dwc_otg_driver);
++#endif
++
++ printk(KERN_INFO "%s module removed\n", dwc_driver_name);
++}
++
++module_exit(dwc_otg_driver_cleanup);
++
++MODULE_DESCRIPTION(DWC_DRIVER_DESC);
++MODULE_AUTHOR("Synopsys Inc.");
++MODULE_LICENSE("GPL");
++
++module_param_named(otg_cap, dwc_otg_module_params.otg_cap, int, 0444);
++MODULE_PARM_DESC(otg_cap, "OTG Capabilities 0=HNP&SRP 1=SRP Only 2=None");
++module_param_named(opt, dwc_otg_module_params.opt, int, 0444);
++MODULE_PARM_DESC(opt, "OPT Mode");
++module_param_named(dma_enable, dwc_otg_module_params.dma_enable, int, 0444);
++MODULE_PARM_DESC(dma_enable, "DMA Mode 0=Slave 1=DMA enabled");
++
++module_param_named(dma_desc_enable, dwc_otg_module_params.dma_desc_enable, int,
++ 0444);
++MODULE_PARM_DESC(dma_desc_enable,
++ "DMA Desc Mode 0=Address DMA 1=DMA Descriptor enabled");
++
++module_param_named(dma_burst_size, dwc_otg_module_params.dma_burst_size, int,
++ 0444);
++MODULE_PARM_DESC(dma_burst_size,
++ "DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256");
++module_param_named(speed, dwc_otg_module_params.speed, int, 0444);
++MODULE_PARM_DESC(speed, "Speed 0=High Speed 1=Full Speed");
++module_param_named(host_support_fs_ls_low_power,
++ dwc_otg_module_params.host_support_fs_ls_low_power, int,
++ 0444);
++MODULE_PARM_DESC(host_support_fs_ls_low_power,
++ "Support Low Power w/FS or LS 0=Support 1=Don't Support");
++module_param_named(host_ls_low_power_phy_clk,
++ dwc_otg_module_params.host_ls_low_power_phy_clk, int, 0444);
++MODULE_PARM_DESC(host_ls_low_power_phy_clk,
++ "Low Speed Low Power Clock 0=48Mhz 1=6Mhz");
++module_param_named(enable_dynamic_fifo,
++ dwc_otg_module_params.enable_dynamic_fifo, int, 0444);
++MODULE_PARM_DESC(enable_dynamic_fifo, "0=cC Setting 1=Allow Dynamic Sizing");
++module_param_named(data_fifo_size, dwc_otg_module_params.data_fifo_size, int,
++ 0444);
++MODULE_PARM_DESC(data_fifo_size,
++ "Total number of words in the data FIFO memory 32-32768");
++module_param_named(dev_rx_fifo_size, dwc_otg_module_params.dev_rx_fifo_size,
++ int, 0444);
++MODULE_PARM_DESC(dev_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
++module_param_named(dev_nperio_tx_fifo_size,
++ dwc_otg_module_params.dev_nperio_tx_fifo_size, int, 0444);
++MODULE_PARM_DESC(dev_nperio_tx_fifo_size,
++ "Number of words in the non-periodic Tx FIFO 16-32768");
++module_param_named(dev_perio_tx_fifo_size_1,
++ dwc_otg_module_params.dev_perio_tx_fifo_size[0], int, 0444);
++MODULE_PARM_DESC(dev_perio_tx_fifo_size_1,
++ "Number of words in the periodic Tx FIFO 4-768");
++module_param_named(dev_perio_tx_fifo_size_2,
++ dwc_otg_module_params.dev_perio_tx_fifo_size[1], int, 0444);
++MODULE_PARM_DESC(dev_perio_tx_fifo_size_2,
++ "Number of words in the periodic Tx FIFO 4-768");
++module_param_named(dev_perio_tx_fifo_size_3,
++ dwc_otg_module_params.dev_perio_tx_fifo_size[2], int, 0444);
++MODULE_PARM_DESC(dev_perio_tx_fifo_size_3,
++ "Number of words in the periodic Tx FIFO 4-768");
++module_param_named(dev_perio_tx_fifo_size_4,
++ dwc_otg_module_params.dev_perio_tx_fifo_size[3], int, 0444);
++MODULE_PARM_DESC(dev_perio_tx_fifo_size_4,
++ "Number of words in the periodic Tx FIFO 4-768");
++module_param_named(dev_perio_tx_fifo_size_5,
++ dwc_otg_module_params.dev_perio_tx_fifo_size[4], int, 0444);
++MODULE_PARM_DESC(dev_perio_tx_fifo_size_5,
++ "Number of words in the periodic Tx FIFO 4-768");
++module_param_named(dev_perio_tx_fifo_size_6,
++ dwc_otg_module_params.dev_perio_tx_fifo_size[5], int, 0444);
++MODULE_PARM_DESC(dev_perio_tx_fifo_size_6,
++ "Number of words in the periodic Tx FIFO 4-768");
++module_param_named(dev_perio_tx_fifo_size_7,
++ dwc_otg_module_params.dev_perio_tx_fifo_size[6], int, 0444);
++MODULE_PARM_DESC(dev_perio_tx_fifo_size_7,
++ "Number of words in the periodic Tx FIFO 4-768");
++module_param_named(dev_perio_tx_fifo_size_8,
++ dwc_otg_module_params.dev_perio_tx_fifo_size[7], int, 0444);
++MODULE_PARM_DESC(dev_perio_tx_fifo_size_8,
++ "Number of words in the periodic Tx FIFO 4-768");
++module_param_named(dev_perio_tx_fifo_size_9,
++ dwc_otg_module_params.dev_perio_tx_fifo_size[8], int, 0444);
++MODULE_PARM_DESC(dev_perio_tx_fifo_size_9,
++ "Number of words in the periodic Tx FIFO 4-768");
++module_param_named(dev_perio_tx_fifo_size_10,
++ dwc_otg_module_params.dev_perio_tx_fifo_size[9], int, 0444);
++MODULE_PARM_DESC(dev_perio_tx_fifo_size_10,
++ "Number of words in the periodic Tx FIFO 4-768");
++module_param_named(dev_perio_tx_fifo_size_11,
++ dwc_otg_module_params.dev_perio_tx_fifo_size[10], int, 0444);
++MODULE_PARM_DESC(dev_perio_tx_fifo_size_11,
++ "Number of words in the periodic Tx FIFO 4-768");
++module_param_named(dev_perio_tx_fifo_size_12,
++ dwc_otg_module_params.dev_perio_tx_fifo_size[11], int, 0444);
++MODULE_PARM_DESC(dev_perio_tx_fifo_size_12,
++ "Number of words in the periodic Tx FIFO 4-768");
++module_param_named(dev_perio_tx_fifo_size_13,
++ dwc_otg_module_params.dev_perio_tx_fifo_size[12], int, 0444);
++MODULE_PARM_DESC(dev_perio_tx_fifo_size_13,
++ "Number of words in the periodic Tx FIFO 4-768");
++module_param_named(dev_perio_tx_fifo_size_14,
++ dwc_otg_module_params.dev_perio_tx_fifo_size[13], int, 0444);
++MODULE_PARM_DESC(dev_perio_tx_fifo_size_14,
++ "Number of words in the periodic Tx FIFO 4-768");
++module_param_named(dev_perio_tx_fifo_size_15,
++ dwc_otg_module_params.dev_perio_tx_fifo_size[14], int, 0444);
++MODULE_PARM_DESC(dev_perio_tx_fifo_size_15,
++ "Number of words in the periodic Tx FIFO 4-768");
++module_param_named(host_rx_fifo_size, dwc_otg_module_params.host_rx_fifo_size,
++ int, 0444);
++MODULE_PARM_DESC(host_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
++module_param_named(host_nperio_tx_fifo_size,
++ dwc_otg_module_params.host_nperio_tx_fifo_size, int, 0444);
++MODULE_PARM_DESC(host_nperio_tx_fifo_size,
++ "Number of words in the non-periodic Tx FIFO 16-32768");
++module_param_named(host_perio_tx_fifo_size,
++ dwc_otg_module_params.host_perio_tx_fifo_size, int, 0444);
++MODULE_PARM_DESC(host_perio_tx_fifo_size,
++ "Number of words in the host periodic Tx FIFO 16-32768");
++module_param_named(max_transfer_size, dwc_otg_module_params.max_transfer_size,
++ int, 0444);
++/** @todo Set the max to 512K, modify checks */
++MODULE_PARM_DESC(max_transfer_size,
++ "The maximum transfer size supported in bytes 2047-65535");
++module_param_named(max_packet_count, dwc_otg_module_params.max_packet_count,
++ int, 0444);
++MODULE_PARM_DESC(max_packet_count,
++ "The maximum number of packets in a transfer 15-511");
++module_param_named(host_channels, dwc_otg_module_params.host_channels, int,
++ 0444);
++MODULE_PARM_DESC(host_channels,
++ "The number of host channel registers to use 1-16");
++module_param_named(dev_endpoints, dwc_otg_module_params.dev_endpoints, int,
++ 0444);
++MODULE_PARM_DESC(dev_endpoints,
++ "The number of endpoints in addition to EP0 available for device mode 1-15");
++module_param_named(phy_type, dwc_otg_module_params.phy_type, int, 0444);
++MODULE_PARM_DESC(phy_type, "0=Reserved 1=UTMI+ 2=ULPI");
++module_param_named(phy_utmi_width, dwc_otg_module_params.phy_utmi_width, int,
++ 0444);
++MODULE_PARM_DESC(phy_utmi_width, "Specifies the UTMI+ Data Width 8 or 16 bits");
++module_param_named(phy_ulpi_ddr, dwc_otg_module_params.phy_ulpi_ddr, int, 0444);
++MODULE_PARM_DESC(phy_ulpi_ddr,
++ "ULPI at double or single data rate 0=Single 1=Double");
++module_param_named(phy_ulpi_ext_vbus, dwc_otg_module_params.phy_ulpi_ext_vbus,
++ int, 0444);
++MODULE_PARM_DESC(phy_ulpi_ext_vbus,
++ "ULPI PHY using internal or external vbus 0=Internal");
++module_param_named(i2c_enable, dwc_otg_module_params.i2c_enable, int, 0444);
++MODULE_PARM_DESC(i2c_enable, "FS PHY Interface");
++module_param_named(ulpi_fs_ls, dwc_otg_module_params.ulpi_fs_ls, int, 0444);
++MODULE_PARM_DESC(ulpi_fs_ls, "ULPI PHY FS/LS mode only");
++module_param_named(ts_dline, dwc_otg_module_params.ts_dline, int, 0444);
++MODULE_PARM_DESC(ts_dline, "Term select Dline pulsing for all PHYs");
++module_param_named(debug, g_dbg_lvl, int, 0444);
++MODULE_PARM_DESC(debug, "");
++
++module_param_named(en_multiple_tx_fifo,
++ dwc_otg_module_params.en_multiple_tx_fifo, int, 0444);
++MODULE_PARM_DESC(en_multiple_tx_fifo,
++ "Dedicated Non Periodic Tx FIFOs 0=disabled 1=enabled");
++module_param_named(dev_tx_fifo_size_1,
++ dwc_otg_module_params.dev_tx_fifo_size[0], int, 0444);
++MODULE_PARM_DESC(dev_tx_fifo_size_1, "Number of words in the Tx FIFO 4-768");
++module_param_named(dev_tx_fifo_size_2,
++ dwc_otg_module_params.dev_tx_fifo_size[1], int, 0444);
++MODULE_PARM_DESC(dev_tx_fifo_size_2, "Number of words in the Tx FIFO 4-768");
++module_param_named(dev_tx_fifo_size_3,
++ dwc_otg_module_params.dev_tx_fifo_size[2], int, 0444);
++MODULE_PARM_DESC(dev_tx_fifo_size_3, "Number of words in the Tx FIFO 4-768");
++module_param_named(dev_tx_fifo_size_4,
++ dwc_otg_module_params.dev_tx_fifo_size[3], int, 0444);
++MODULE_PARM_DESC(dev_tx_fifo_size_4, "Number of words in the Tx FIFO 4-768");
++module_param_named(dev_tx_fifo_size_5,
++ dwc_otg_module_params.dev_tx_fifo_size[4], int, 0444);
++MODULE_PARM_DESC(dev_tx_fifo_size_5, "Number of words in the Tx FIFO 4-768");
++module_param_named(dev_tx_fifo_size_6,
++ dwc_otg_module_params.dev_tx_fifo_size[5], int, 0444);
++MODULE_PARM_DESC(dev_tx_fifo_size_6, "Number of words in the Tx FIFO 4-768");
++module_param_named(dev_tx_fifo_size_7,
++ dwc_otg_module_params.dev_tx_fifo_size[6], int, 0444);
++MODULE_PARM_DESC(dev_tx_fifo_size_7, "Number of words in the Tx FIFO 4-768");
++module_param_named(dev_tx_fifo_size_8,
++ dwc_otg_module_params.dev_tx_fifo_size[7], int, 0444);
++MODULE_PARM_DESC(dev_tx_fifo_size_8, "Number of words in the Tx FIFO 4-768");
++module_param_named(dev_tx_fifo_size_9,
++ dwc_otg_module_params.dev_tx_fifo_size[8], int, 0444);
++MODULE_PARM_DESC(dev_tx_fifo_size_9, "Number of words in the Tx FIFO 4-768");
++module_param_named(dev_tx_fifo_size_10,
++ dwc_otg_module_params.dev_tx_fifo_size[9], int, 0444);
++MODULE_PARM_DESC(dev_tx_fifo_size_10, "Number of words in the Tx FIFO 4-768");
++module_param_named(dev_tx_fifo_size_11,
++ dwc_otg_module_params.dev_tx_fifo_size[10], int, 0444);
++MODULE_PARM_DESC(dev_tx_fifo_size_11, "Number of words in the Tx FIFO 4-768");
++module_param_named(dev_tx_fifo_size_12,
++ dwc_otg_module_params.dev_tx_fifo_size[11], int, 0444);
++MODULE_PARM_DESC(dev_tx_fifo_size_12, "Number of words in the Tx FIFO 4-768");
++module_param_named(dev_tx_fifo_size_13,
++ dwc_otg_module_params.dev_tx_fifo_size[12], int, 0444);
++MODULE_PARM_DESC(dev_tx_fifo_size_13, "Number of words in the Tx FIFO 4-768");
++module_param_named(dev_tx_fifo_size_14,
++ dwc_otg_module_params.dev_tx_fifo_size[13], int, 0444);
++MODULE_PARM_DESC(dev_tx_fifo_size_14, "Number of words in the Tx FIFO 4-768");
++module_param_named(dev_tx_fifo_size_15,
++ dwc_otg_module_params.dev_tx_fifo_size[14], int, 0444);
++MODULE_PARM_DESC(dev_tx_fifo_size_15, "Number of words in the Tx FIFO 4-768");
++
++module_param_named(thr_ctl, dwc_otg_module_params.thr_ctl, int, 0444);
++MODULE_PARM_DESC(thr_ctl,
++ "Thresholding enable flag bit 0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled");
++module_param_named(tx_thr_length, dwc_otg_module_params.tx_thr_length, int,
++ 0444);
++MODULE_PARM_DESC(tx_thr_length, "Tx Threshold length in 32 bit DWORDs");
++module_param_named(rx_thr_length, dwc_otg_module_params.rx_thr_length, int,
++ 0444);
++MODULE_PARM_DESC(rx_thr_length, "Rx Threshold length in 32 bit DWORDs");
++
++module_param_named(pti_enable, dwc_otg_module_params.pti_enable, int, 0444);
++module_param_named(mpi_enable, dwc_otg_module_params.mpi_enable, int, 0444);
++module_param_named(lpm_enable, dwc_otg_module_params.lpm_enable, int, 0444);
++MODULE_PARM_DESC(lpm_enable, "LPM Enable 0=LPM Disabled 1=LPM Enabled");
++module_param_named(ic_usb_cap, dwc_otg_module_params.ic_usb_cap, int, 0444);
++MODULE_PARM_DESC(ic_usb_cap,
++ "IC_USB Capability 0=IC_USB Disabled 1=IC_USB Enabled");
++module_param_named(ahb_thr_ratio, dwc_otg_module_params.ahb_thr_ratio, int,
++ 0444);
++MODULE_PARM_DESC(ahb_thr_ratio, "AHB Threshold Ratio");
++module_param_named(power_down, dwc_otg_module_params.power_down, int, 0444);
++MODULE_PARM_DESC(power_down, "Power Down Mode");
++module_param_named(reload_ctl, dwc_otg_module_params.reload_ctl, int, 0444);
++MODULE_PARM_DESC(reload_ctl, "HFIR Reload Control");
++module_param_named(dev_out_nak, dwc_otg_module_params.dev_out_nak, int, 0444);
++MODULE_PARM_DESC(dev_out_nak, "Enable Device OUT NAK");
++module_param_named(cont_on_bna, dwc_otg_module_params.cont_on_bna, int, 0444);
++MODULE_PARM_DESC(cont_on_bna, "Enable Enable Continue on BNA");
++module_param_named(ahb_single, dwc_otg_module_params.ahb_single, int, 0444);
++MODULE_PARM_DESC(ahb_single, "Enable AHB Single Support");
++module_param_named(adp_enable, dwc_otg_module_params.adp_enable, int, 0444);
++MODULE_PARM_DESC(adp_enable, "ADP Enable 0=ADP Disabled 1=ADP Enabled");
++module_param_named(otg_ver, dwc_otg_module_params.otg_ver, int, 0444);
++MODULE_PARM_DESC(otg_ver, "OTG revision supported 0=OTG 1.3 1=OTG 2.0");
++module_param(microframe_schedule, bool, 0444);
++MODULE_PARM_DESC(microframe_schedule, "Enable the microframe scheduler");
++
++module_param(fiq_enable, bool, 0444);
++MODULE_PARM_DESC(fiq_enable, "Enable the FIQ");
++module_param(nak_holdoff, ushort, 0644);
++MODULE_PARM_DESC(nak_holdoff, "Throttle duration for bulk split-transaction endpoints on a NAK. Default 8");
++module_param(fiq_fsm_enable, bool, 0444);
++MODULE_PARM_DESC(fiq_fsm_enable, "Enable the FIQ to perform split transactions as defined by fiq_fsm_mask");
++module_param(fiq_fsm_mask, ushort, 0444);
++MODULE_PARM_DESC(fiq_fsm_mask, "Bitmask of transactions to perform in the FIQ.\n"
++ "Bit 0 : Non-periodic split transactions\n"
++ "Bit 1 : Periodic split transactions\n"
++ "Bit 2 : High-speed multi-transfer isochronous\n"
++ "All other bits should be set 0.");
++
++
++/** @page "Module Parameters"
++ *
++ * The following parameters may be specified when starting the module.
++ * These parameters define how the DWC_otg controller should be
++ * configured. Parameter values are passed to the CIL initialization
++ * function dwc_otg_cil_init
++ *
++ * Example: <code>modprobe dwc_otg speed=1 otg_cap=1</code>
++ *
++
++ <table>
++ <tr><td>Parameter Name</td><td>Meaning</td></tr>
++
++ <tr>
++ <td>otg_cap</td>
++ <td>Specifies the OTG capabilities. The driver will automatically detect the
++ value for this parameter if none is specified.
++ - 0: HNP and SRP capable (default, if available)
++ - 1: SRP Only capable
++ - 2: No HNP/SRP capable
++ </td></tr>
++
++ <tr>
++ <td>dma_enable</td>
++ <td>Specifies whether to use slave or DMA mode for accessing the data FIFOs.
++ The driver will automatically detect the value for this parameter if none is
++ specified.
++ - 0: Slave
++ - 1: DMA (default, if available)
++ </td></tr>
++
++ <tr>
++ <td>dma_burst_size</td>
++ <td>The DMA Burst size (applicable only for External DMA Mode).
++ - Values: 1, 4, 8 16, 32, 64, 128, 256 (default 32)
++ </td></tr>
++
++ <tr>
++ <td>speed</td>
++ <td>Specifies the maximum speed of operation in host and device mode. The
++ actual speed depends on the speed of the attached device and the value of
++ phy_type.
++ - 0: High Speed (default)
++ - 1: Full Speed
++ </td></tr>
++
++ <tr>
++ <td>host_support_fs_ls_low_power</td>
++ <td>Specifies whether low power mode is supported when attached to a Full
++ Speed or Low Speed device in host mode.
++ - 0: Don't support low power mode (default)
++ - 1: Support low power mode
++ </td></tr>
++
++ <tr>
++ <td>host_ls_low_power_phy_clk</td>
++ <td>Specifies the PHY clock rate in low power mode when connected to a Low
++ Speed device in host mode. This parameter is applicable only if
++ HOST_SUPPORT_FS_LS_LOW_POWER is enabled.
++ - 0: 48 MHz (default)
++ - 1: 6 MHz
++ </td></tr>
++
++ <tr>
++ <td>enable_dynamic_fifo</td>
++ <td> Specifies whether FIFOs may be resized by the driver software.
++ - 0: Use cC FIFO size parameters
++ - 1: Allow dynamic FIFO sizing (default)
++ </td></tr>
++
++ <tr>
++ <td>data_fifo_size</td>
++ <td>Total number of 4-byte words in the data FIFO memory. This memory
++ includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs.
++ - Values: 32 to 32768 (default 8192)
++
++ Note: The total FIFO memory depth in the FPGA configuration is 8192.
++ </td></tr>
++
++ <tr>
++ <td>dev_rx_fifo_size</td>
++ <td>Number of 4-byte words in the Rx FIFO in device mode when dynamic
++ FIFO sizing is enabled.
++ - Values: 16 to 32768 (default 1064)
++ </td></tr>
++
++ <tr>
++ <td>dev_nperio_tx_fifo_size</td>
++ <td>Number of 4-byte words in the non-periodic Tx FIFO in device mode when
++ dynamic FIFO sizing is enabled.
++ - Values: 16 to 32768 (default 1024)
++ </td></tr>
++
++ <tr>
++ <td>dev_perio_tx_fifo_size_n (n = 1 to 15)</td>
++ <td>Number of 4-byte words in each of the periodic Tx FIFOs in device mode
++ when dynamic FIFO sizing is enabled.
++ - Values: 4 to 768 (default 256)
++ </td></tr>
++
++ <tr>
++ <td>host_rx_fifo_size</td>
++ <td>Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO
++ sizing is enabled.
++ - Values: 16 to 32768 (default 1024)
++ </td></tr>
++
++ <tr>
++ <td>host_nperio_tx_fifo_size</td>
++ <td>Number of 4-byte words in the non-periodic Tx FIFO in host mode when
++ dynamic FIFO sizing is enabled in the core.
++ - Values: 16 to 32768 (default 1024)
++ </td></tr>
++
++ <tr>
++ <td>host_perio_tx_fifo_size</td>
++ <td>Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO
++ sizing is enabled.
++ - Values: 16 to 32768 (default 1024)
++ </td></tr>
++
++ <tr>
++ <td>max_transfer_size</td>
++ <td>The maximum transfer size supported in bytes.
++ - Values: 2047 to 65,535 (default 65,535)
++ </td></tr>
++
++ <tr>
++ <td>max_packet_count</td>
++ <td>The maximum number of packets in a transfer.
++ - Values: 15 to 511 (default 511)
++ </td></tr>
++
++ <tr>
++ <td>host_channels</td>
++ <td>The number of host channel registers to use.
++ - Values: 1 to 16 (default 12)
++
++ Note: The FPGA configuration supports a maximum of 12 host channels.
++ </td></tr>
++
++ <tr>
++ <td>dev_endpoints</td>
++ <td>The number of endpoints in addition to EP0 available for device mode
++ operations.
++ - Values: 1 to 15 (default 6 IN and OUT)
++
++ Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in
++ addition to EP0.
++ </td></tr>
++
++ <tr>
++ <td>phy_type</td>
++ <td>Specifies the type of PHY interface to use. By default, the driver will
++ automatically detect the phy_type.
++ - 0: Full Speed
++ - 1: UTMI+ (default, if available)
++ - 2: ULPI
++ </td></tr>
++
++ <tr>
++ <td>phy_utmi_width</td>
++ <td>Specifies the UTMI+ Data Width. This parameter is applicable for a
++ phy_type of UTMI+. Also, this parameter is applicable only if the
++ OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the
++ core has been configured to work at either data path width.
++ - Values: 8 or 16 bits (default 16)
++ </td></tr>
++
++ <tr>
++ <td>phy_ulpi_ddr</td>
++ <td>Specifies whether the ULPI operates at double or single data rate. This
++ parameter is only applicable if phy_type is ULPI.
++ - 0: single data rate ULPI interface with 8 bit wide data bus (default)
++ - 1: double data rate ULPI interface with 4 bit wide data bus
++ </td></tr>
++
++ <tr>
++ <td>i2c_enable</td>
++ <td>Specifies whether to use the I2C interface for full speed PHY. This
++ parameter is only applicable if PHY_TYPE is FS.
++ - 0: Disabled (default)
++ - 1: Enabled
++ </td></tr>
++
++ <tr>
++ <td>ulpi_fs_ls</td>
++ <td>Specifies whether to use ULPI FS/LS mode only.
++ - 0: Disabled (default)
++ - 1: Enabled
++ </td></tr>
++
++ <tr>
++ <td>ts_dline</td>
++ <td>Specifies whether term select D-Line pulsing for all PHYs is enabled.
++ - 0: Disabled (default)
++ - 1: Enabled
++ </td></tr>
++
++ <tr>
++ <td>en_multiple_tx_fifo</td>
++ <td>Specifies whether dedicatedto tx fifos are enabled for non periodic IN EPs.
++ The driver will automatically detect the value for this parameter if none is
++ specified.
++ - 0: Disabled
++ - 1: Enabled (default, if available)
++ </td></tr>
++
++ <tr>
++ <td>dev_tx_fifo_size_n (n = 1 to 15)</td>
++ <td>Number of 4-byte words in each of the Tx FIFOs in device mode
++ when dynamic FIFO sizing is enabled.
++ - Values: 4 to 768 (default 256)
++ </td></tr>
++
++ <tr>
++ <td>tx_thr_length</td>
++ <td>Transmit Threshold length in 32 bit double words
++ - Values: 8 to 128 (default 64)
++ </td></tr>
++
++ <tr>
++ <td>rx_thr_length</td>
++ <td>Receive Threshold length in 32 bit double words
++ - Values: 8 to 128 (default 64)
++ </td></tr>
++
++<tr>
++ <td>thr_ctl</td>
++ <td>Specifies whether to enable Thresholding for Device mode. Bits 0, 1, 2 of
++ this parmater specifies if thresholding is enabled for non-Iso Tx, Iso Tx and
++ Rx transfers accordingly.
++ The driver will automatically detect the value for this parameter if none is
++ specified.
++ - Values: 0 to 7 (default 0)
++ Bit values indicate:
++ - 0: Thresholding disabled
++ - 1: Thresholding enabled
++ </td></tr>
++
++<tr>
++ <td>dma_desc_enable</td>
++ <td>Specifies whether to enable Descriptor DMA mode.
++ The driver will automatically detect the value for this parameter if none is
++ specified.
++ - 0: Descriptor DMA disabled
++ - 1: Descriptor DMA (default, if available)
++ </td></tr>
++
++<tr>
++ <td>mpi_enable</td>
++ <td>Specifies whether to enable MPI enhancement mode.
++ The driver will automatically detect the value for this parameter if none is
++ specified.
++ - 0: MPI disabled (default)
++ - 1: MPI enable
++ </td></tr>
++
++<tr>
++ <td>pti_enable</td>
++ <td>Specifies whether to enable PTI enhancement support.
++ The driver will automatically detect the value for this parameter if none is
++ specified.
++ - 0: PTI disabled (default)
++ - 1: PTI enable
++ </td></tr>
++
++<tr>
++ <td>lpm_enable</td>
++ <td>Specifies whether to enable LPM support.
++ The driver will automatically detect the value for this parameter if none is
++ specified.
++ - 0: LPM disabled
++ - 1: LPM enable (default, if available)
++ </td></tr>
++
++<tr>
++ <td>ic_usb_cap</td>
++ <td>Specifies whether to enable IC_USB capability.
++ The driver will automatically detect the value for this parameter if none is
++ specified.
++ - 0: IC_USB disabled (default, if available)
++ - 1: IC_USB enable
++ </td></tr>
++
++<tr>
++ <td>ahb_thr_ratio</td>
++ <td>Specifies AHB Threshold ratio.
++ - Values: 0 to 3 (default 0)
++ </td></tr>
++
++<tr>
++ <td>power_down</td>
++ <td>Specifies Power Down(Hibernation) Mode.
++ The driver will automatically detect the value for this parameter if none is
++ specified.
++ - 0: Power Down disabled (default)
++ - 2: Power Down enabled
++ </td></tr>
++
++ <tr>
++ <td>reload_ctl</td>
++ <td>Specifies whether dynamic reloading of the HFIR register is allowed during
++ run time. The driver will automatically detect the value for this parameter if
++ none is specified. In case the HFIR value is reloaded when HFIR.RldCtrl == 1'b0
++ the core might misbehave.
++ - 0: Reload Control disabled (default)
++ - 1: Reload Control enabled
++ </td></tr>
++
++ <tr>
++ <td>dev_out_nak</td>
++ <td>Specifies whether Device OUT NAK enhancement enabled or no.
++ The driver will automatically detect the value for this parameter if
++ none is specified. This parameter is valid only when OTG_EN_DESC_DMA == 1b1.
++ - 0: The core does not set NAK after Bulk OUT transfer complete (default)
++ - 1: The core sets NAK after Bulk OUT transfer complete
++ </td></tr>
++
++ <tr>
++ <td>cont_on_bna</td>
++ <td>Specifies whether Enable Continue on BNA enabled or no.
++ After receiving BNA interrupt the core disables the endpoint,when the
++ endpoint is re-enabled by the application the
++ - 0: Core starts processing from the DOEPDMA descriptor (default)
++ - 1: Core starts processing from the descriptor which received the BNA.
++ This parameter is valid only when OTG_EN_DESC_DMA == 1b1.
++ </td></tr>
++
++ <tr>
++ <td>ahb_single</td>
++ <td>This bit when programmed supports SINGLE transfers for remainder data
++ in a transfer for DMA mode of operation.
++ - 0: The remainder data will be sent using INCR burst size (default)
++ - 1: The remainder data will be sent using SINGLE burst size.
++ </td></tr>
++
++<tr>
++ <td>adp_enable</td>
++ <td>Specifies whether ADP feature is enabled.
++ The driver will automatically detect the value for this parameter if none is
++ specified.
++ - 0: ADP feature disabled (default)
++ - 1: ADP feature enabled
++ </td></tr>
++
++ <tr>
++ <td>otg_ver</td>
++ <td>Specifies whether OTG is performing as USB OTG Revision 2.0 or Revision 1.3
++ USB OTG device.
++ - 0: OTG 2.0 support disabled (default)
++ - 1: OTG 2.0 support enabled
++ </td></tr>
++
++*/
+diff -Nur linux-4.1.3/drivers/usb/host/dwc_otg/dwc_otg_driver.h linux-xbian-rpi/drivers/usb/host/dwc_otg/dwc_otg_driver.h
+--- linux-4.1.3/drivers/usb/host/dwc_otg/dwc_otg_driver.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/usb/host/dwc_otg/dwc_otg_driver.h 2015-07-28 01:20:58.445156473 +0200
+@@ -0,0 +1,86 @@
++/* ==========================================================================
++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.h $
++ * $Revision: #19 $
++ * $Date: 2010/11/15 $
++ * $Change: 1627671 $
++ *
++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++ * otherwise expressly agreed to in writing between Synopsys and you.
++ *
++ * The Software IS NOT an item of Licensed Software or Licensed Product under
++ * any End User Software License Agreement or Agreement for Licensed Product
++ * with Synopsys or any supplement thereto. You are permitted to use and
++ * redistribute this Software in source and binary forms, with or without
++ * modification, provided that redistributions of source code must retain this
++ * notice. You may not view, use, disclose, copy or distribute this file or
++ * any information contained herein except pursuant to this license grant from
++ * Synopsys. If you do not agree with this notice, including the disclaimer
++ * below, then you are not authorized to use the Software.
++ *
++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++ * DAMAGE.
++ * ========================================================================== */
++
++#ifndef __DWC_OTG_DRIVER_H__
++#define __DWC_OTG_DRIVER_H__
++
++/** @file
++ * This file contains the interface to the Linux driver.
++ */
++#include "dwc_otg_os_dep.h"
++#include "dwc_otg_core_if.h"
++
++/* Type declarations */
++struct dwc_otg_pcd;
++struct dwc_otg_hcd;
++
++/**
++ * This structure is a wrapper that encapsulates the driver components used to
++ * manage a single DWC_otg controller.
++ */
++typedef struct dwc_otg_device {
++ /** Structure containing OS-dependent stuff. KEEP THIS STRUCT AT THE
++ * VERY BEGINNING OF THE DEVICE STRUCT. OSes such as FreeBSD and NetBSD
++ * require this. */
++ struct os_dependent os_dep;
++
++ /** Pointer to the core interface structure. */
++ dwc_otg_core_if_t *core_if;
++
++ /** Pointer to the PCD structure. */
++ struct dwc_otg_pcd *pcd;
++
++ /** Pointer to the HCD structure. */
++ struct dwc_otg_hcd *hcd;
++
++ /** Flag to indicate whether the common IRQ handler is installed. */
++ uint8_t common_irq_installed;
++
++} dwc_otg_device_t;
++
++/*We must clear S3C24XX_EINTPEND external interrupt register
++ * because after clearing in this register trigerred IRQ from
++ * H/W core in kernel interrupt can be occured again before OTG
++ * handlers clear all IRQ sources of Core registers because of
++ * timing latencies and Low Level IRQ Type.
++ */
++#ifdef CONFIG_MACH_IPMATE
++#define S3C2410X_CLEAR_EINTPEND() \
++do { \
++ __raw_writel(1UL << 11,S3C24XX_EINTPEND); \
++} while (0)
++#else
++#define S3C2410X_CLEAR_EINTPEND() do { } while (0)
++#endif
++
++#endif
+diff -Nur linux-4.1.3/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c linux-xbian-rpi/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c
+--- linux-4.1.3/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c 2015-07-28 01:20:58.445156473 +0200
+@@ -0,0 +1,1346 @@
++/*
++ * dwc_otg_fiq_fsm.c - The finite state machine FIQ
++ *
++ * Copyright (c) 2013 Raspberry Pi Foundation
++ *
++ * Author: Jonathan Bell <jonathan@raspberrypi.org>
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * * Neither the name of Raspberry Pi nor the
++ * names of its contributors may be used to endorse or promote products
++ * derived from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
++ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
++ * DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ *
++ * This FIQ implements functionality that performs split transactions on
++ * the dwc_otg hardware without any outside intervention. A split transaction
++ * is "queued" by nominating a specific host channel to perform the entirety
++ * of a split transaction. This FIQ will then perform the microframe-precise
++ * scheduling required in each phase of the transaction until completion.
++ *
++ * The FIQ functionality is glued into the Synopsys driver via the entry point
++ * in the FSM enqueue function, and at the exit point in handling a HC interrupt
++ * for a FSM-enabled channel.
++ *
++ * NB: Large parts of this implementation have architecture-specific code.
++ * For porting this functionality to other ARM machines, the minimum is required:
++ * - An interrupt controller allowing the top-level dwc USB interrupt to be routed
++ * to the FIQ
++ * - A method of forcing a software generated interrupt from FIQ mode that then
++ * triggers an IRQ entry (with the dwc USB handler called by this IRQ number)
++ * - Guaranteed interrupt routing such that both the FIQ and SGI occur on the same
++ * processor core - there is no locking between the FIQ and IRQ (aside from
++ * local_fiq_disable)
++ *
++ */
++
++#include "dwc_otg_fiq_fsm.h"
++
++
++char buffer[1000*16];
++int wptr;
++void notrace _fiq_print(enum fiq_debug_level dbg_lvl, volatile struct fiq_state *state, char *fmt, ...)
++{
++ enum fiq_debug_level dbg_lvl_req = FIQDBG_ERR;
++ va_list args;
++ char text[17];
++ hfnum_data_t hfnum = { .d32 = FIQ_READ(state->dwc_regs_base + 0x408) };
++
++ if((dbg_lvl & dbg_lvl_req) || dbg_lvl == FIQDBG_ERR)
++ {
++ snprintf(text, 9, " %4d:%1u ", hfnum.b.frnum/8, hfnum.b.frnum & 7);
++ va_start(args, fmt);
++ vsnprintf(text+8, 9, fmt, args);
++ va_end(args);
++
++ memcpy(buffer + wptr, text, 16);
++ wptr = (wptr + 16) % sizeof(buffer);
++ }
++}
++
++/**
++ * fiq_fsm_spin_lock() - ARMv6+ bare bones spinlock
++ * Must be called with local interrupts and FIQ disabled.
++ */
++#if defined(CONFIG_ARCH_BCM2709) && defined(CONFIG_SMP)
++inline void fiq_fsm_spin_lock(fiq_lock_t *lock)
++{
++ unsigned long tmp;
++ uint32_t newval;
++ fiq_lock_t lockval;
++ smp_mb__before_spinlock();
++ /* Nested locking, yay. If we are on the same CPU as the fiq, then the disable
++ * will be sufficient. If we are on a different CPU, then the lock protects us. */
++ prefetchw(&lock->slock);
++ asm volatile (
++ "1: ldrex %0, [%3]\n"
++ " add %1, %0, %4\n"
++ " strex %2, %1, [%3]\n"
++ " teq %2, #0\n"
++ " bne 1b"
++ : "=&r" (lockval), "=&r" (newval), "=&r" (tmp)
++ : "r" (&lock->slock), "I" (1 << 16)
++ : "cc");
++
++ while (lockval.tickets.next != lockval.tickets.owner) {
++ wfe();
++ lockval.tickets.owner = ACCESS_ONCE(lock->tickets.owner);
++ }
++ smp_mb();
++}
++#else
++inline void fiq_fsm_spin_lock(fiq_lock_t *lock) { }
++#endif
++
++/**
++ * fiq_fsm_spin_unlock() - ARMv6+ bare bones spinunlock
++ */
++#if defined(CONFIG_ARCH_BCM2709) && defined(CONFIG_SMP)
++inline void fiq_fsm_spin_unlock(fiq_lock_t *lock)
++{
++ smp_mb();
++ lock->tickets.owner++;
++ dsb_sev();
++}
++#else
++inline void fiq_fsm_spin_unlock(fiq_lock_t *lock) { }
++#endif
++
++/**
++ * fiq_fsm_restart_channel() - Poke channel enable bit for a split transaction
++ * @channel: channel to re-enable
++ */
++static void fiq_fsm_restart_channel(struct fiq_state *st, int n, int force)
++{
++ hcchar_data_t hcchar = { .d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR) };
++
++ hcchar.b.chen = 0;
++ if (st->channel[n].hcchar_copy.b.eptype & 0x1) {
++ hfnum_data_t hfnum = { .d32 = FIQ_READ(st->dwc_regs_base + HFNUM) };
++ /* Hardware bug workaround: update the ssplit index */
++ if (st->channel[n].hcsplt_copy.b.spltena)
++ st->channel[n].expected_uframe = (hfnum.b.frnum + 1) & 0x3FFF;
++
++ hcchar.b.oddfrm = (hfnum.b.frnum & 0x1) ? 0 : 1;
++ }
++
++ FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR, hcchar.d32);
++ hcchar.d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR);
++ hcchar.b.chen = 1;
++
++ FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR, hcchar.d32);
++ fiq_print(FIQDBG_INT, st, "HCGO %01d %01d", n, force);
++}
++
++/**
++ * fiq_fsm_setup_csplit() - Prepare a host channel for a CSplit transaction stage
++ * @st: Pointer to the channel's state
++ * @n : channel number
++ *
++ * Change host channel registers to perform a complete-split transaction. Being mindful of the
++ * endpoint direction, set control regs up correctly.
++ */
++static void notrace fiq_fsm_setup_csplit(struct fiq_state *st, int n)
++{
++ hcsplt_data_t hcsplt = { .d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCSPLT) };
++ hctsiz_data_t hctsiz = { .d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ) };
++
++ hcsplt.b.compsplt = 1;
++ if (st->channel[n].hcchar_copy.b.epdir == 1) {
++ // If IN, the CSPLIT result contains the data or a hub handshake. hctsiz = maxpacket.
++ hctsiz.b.xfersize = st->channel[n].hctsiz_copy.b.xfersize;
++ } else {
++ // If OUT, the CSPLIT result contains handshake only.
++ hctsiz.b.xfersize = 0;
++ }
++ FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCSPLT, hcsplt.d32);
++ FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ, hctsiz.d32);
++ mb();
++}
++
++static inline int notrace fiq_get_xfer_len(struct fiq_state *st, int n)
++{
++ /* The xfersize register is a bit wonky. For IN transfers, it decrements by the packet size. */
++ hctsiz_data_t hctsiz = { .d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ) };
++
++ if (st->channel[n].hcchar_copy.b.epdir == 0) {
++ return st->channel[n].hctsiz_copy.b.xfersize;
++ } else {
++ return st->channel[n].hctsiz_copy.b.xfersize - hctsiz.b.xfersize;
++ }
++
++}
++
++
++/**
++ * fiq_increment_dma_buf() - update DMA address for bounce buffers after a CSPLIT
++ *
++ * Of use only for IN periodic transfers.
++ */
++static int notrace fiq_increment_dma_buf(struct fiq_state *st, int num_channels, int n)
++{
++ hcdma_data_t hcdma;
++ int i = st->channel[n].dma_info.index;
++ int len;
++ struct fiq_dma_blob *blob = (struct fiq_dma_blob *) st->dma_base;
++
++ len = fiq_get_xfer_len(st, n);
++ fiq_print(FIQDBG_INT, st, "LEN: %03d", len);
++ st->channel[n].dma_info.slot_len[i] = len;
++ i++;
++ if (i > 6)
++ BUG();
++
++ hcdma.d32 = (dma_addr_t) &blob->channel[n].index[i].buf[0];
++ FIQ_WRITE(st->dwc_regs_base + HC_DMA + (HC_OFFSET * n), hcdma.d32);
++ st->channel[n].dma_info.index = i;
++ return 0;
++}
++
++/**
++ * fiq_reload_hctsiz() - for IN transactions, reset HCTSIZ
++ */
++static void notrace fiq_fsm_reload_hctsiz(struct fiq_state *st, int n)
++{
++ hctsiz_data_t hctsiz = { .d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ) };
++ hctsiz.b.xfersize = st->channel[n].hctsiz_copy.b.xfersize;
++ hctsiz.b.pktcnt = 1;
++ FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ, hctsiz.d32);
++}
++
++/**
++ * fiq_iso_out_advance() - update DMA address and split position bits
++ * for isochronous OUT transactions.
++ *
++ * Returns 1 if this is the last packet queued, 0 otherwise. Split-ALL and
++ * Split-BEGIN states are not handled - this is done when the transaction was queued.
++ *
++ * This function must only be called from the FIQ_ISO_OUT_ACTIVE state.
++ */
++static int notrace fiq_iso_out_advance(struct fiq_state *st, int num_channels, int n)
++{
++ hcsplt_data_t hcsplt;
++ hctsiz_data_t hctsiz;
++ hcdma_data_t hcdma;
++ struct fiq_dma_blob *blob = (struct fiq_dma_blob *) st->dma_base;
++ int last = 0;
++ int i = st->channel[n].dma_info.index;
++
++ fiq_print(FIQDBG_INT, st, "ADV %01d %01d ", n, i);
++ i++;
++ if (i == 4)
++ last = 1;
++ if (st->channel[n].dma_info.slot_len[i+1] == 255)
++ last = 1;
++
++ /* New DMA address - address of bounce buffer referred to in index */
++ hcdma.d32 = (uint32_t) &blob->channel[n].index[i].buf[0];
++ //hcdma.d32 = FIQ_READ(st->dwc_regs_base + HC_DMA + (HC_OFFSET * n));
++ //hcdma.d32 += st->channel[n].dma_info.slot_len[i];
++ fiq_print(FIQDBG_INT, st, "LAST: %01d ", last);
++ fiq_print(FIQDBG_INT, st, "LEN: %03d", st->channel[n].dma_info.slot_len[i]);
++ hcsplt.d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCSPLT);
++ hctsiz.d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ);
++ hcsplt.b.xactpos = (last) ? ISOC_XACTPOS_END : ISOC_XACTPOS_MID;
++ /* Set up new packet length */
++ hctsiz.b.pktcnt = 1;
++ hctsiz.b.xfersize = st->channel[n].dma_info.slot_len[i];
++ fiq_print(FIQDBG_INT, st, "%08x", hctsiz.d32);
++
++ st->channel[n].dma_info.index++;
++ FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCSPLT, hcsplt.d32);
++ FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ, hctsiz.d32);
++ FIQ_WRITE(st->dwc_regs_base + HC_DMA + (HC_OFFSET * n), hcdma.d32);
++ return last;
++}
++
++/**
++ * fiq_fsm_tt_next_isoc() - queue next pending isochronous out start-split on a TT
++ *
++ * Despite the limitations of the DWC core, we can force a microframe pipeline of
++ * isochronous OUT start-split transactions while waiting for a corresponding other-type
++ * of endpoint to finish its CSPLITs. TTs have big periodic buffers therefore it
++ * is very unlikely that filling the start-split FIFO will cause data loss.
++ * This allows much better interleaving of transactions in an order-independent way-
++ * there is no requirement to prioritise isochronous, just a state-space search has
++ * to be performed on each periodic start-split complete interrupt.
++ */
++static int notrace fiq_fsm_tt_next_isoc(struct fiq_state *st, int num_channels, int n)
++{
++ int hub_addr = st->channel[n].hub_addr;
++ int port_addr = st->channel[n].port_addr;
++ int i, poked = 0;
++ for (i = 0; i < num_channels; i++) {
++ if (i == n || st->channel[i].fsm == FIQ_PASSTHROUGH)
++ continue;
++ if (st->channel[i].hub_addr == hub_addr &&
++ st->channel[i].port_addr == port_addr) {
++ switch (st->channel[i].fsm) {
++ case FIQ_PER_ISO_OUT_PENDING:
++ if (st->channel[i].nrpackets == 1) {
++ st->channel[i].fsm = FIQ_PER_ISO_OUT_LAST;
++ } else {
++ st->channel[i].fsm = FIQ_PER_ISO_OUT_ACTIVE;
++ }
++ fiq_fsm_restart_channel(st, i, 0);
++ poked = 1;
++ break;
++
++ default:
++ break;
++ }
++ }
++ if (poked)
++ break;
++ }
++ return poked;
++}
++
++/**
++ * fiq_fsm_tt_in_use() - search for host channels using this TT
++ * @n: Channel to use as reference
++ *
++ */
++int notrace noinline fiq_fsm_tt_in_use(struct fiq_state *st, int num_channels, int n)
++{
++ int hub_addr = st->channel[n].hub_addr;
++ int port_addr = st->channel[n].port_addr;
++ int i, in_use = 0;
++ for (i = 0; i < num_channels; i++) {
++ if (i == n || st->channel[i].fsm == FIQ_PASSTHROUGH)
++ continue;
++ switch (st->channel[i].fsm) {
++ /* TT is reserved for channels that are in the middle of a periodic
++ * split transaction.
++ */
++ case FIQ_PER_SSPLIT_STARTED:
++ case FIQ_PER_CSPLIT_WAIT:
++ case FIQ_PER_CSPLIT_NYET1:
++ //case FIQ_PER_CSPLIT_POLL:
++ case FIQ_PER_ISO_OUT_ACTIVE:
++ case FIQ_PER_ISO_OUT_LAST:
++ if (st->channel[i].hub_addr == hub_addr &&
++ st->channel[i].port_addr == port_addr) {
++ in_use = 1;
++ }
++ break;
++ default:
++ break;
++ }
++ if (in_use)
++ break;
++ }
++ return in_use;
++}
++
++/**
++ * fiq_fsm_more_csplits() - determine whether additional CSPLITs need
++ * to be issued for this IN transaction.
++ *
++ * We cannot tell the inbound PID of a data packet due to hardware limitations.
++ * we need to make an educated guess as to whether we need to queue another CSPLIT
++ * or not. A no-brainer is when we have received enough data to fill the endpoint
++ * size, but for endpoints that give variable-length data then we have to resort
++ * to heuristics.
++ *
++ * We also return whether this is the last CSPLIT to be queued, again based on
++ * heuristics. This is to allow a 1-uframe overlap of periodic split transactions.
++ * Note: requires at least 1 CSPLIT to have been performed prior to being called.
++ */
++
++/*
++ * We need some way of guaranteeing if a returned periodic packet of size X
++ * has a DATA0 PID.
++ * The heuristic value of 144 bytes assumes that the received data has maximal
++ * bit-stuffing and the clock frequency of the transmitting device is at the lowest
++ * permissible limit. If the transfer length results in a final packet size
++ * 144 < p <= 188, then an erroneous CSPLIT will be issued.
++ * Also used to ensure that an endpoint will nominally only return a single
++ * complete-split worth of data.
++ */
++#define DATA0_PID_HEURISTIC 144
++
++static int notrace noinline fiq_fsm_more_csplits(struct fiq_state *state, int n, int *probably_last)
++{
++
++ int i;
++ int total_len = 0;
++ int more_needed = 1;
++ struct fiq_channel_state *st = &state->channel[n];
++
++ for (i = 0; i < st->dma_info.index; i++) {
++ total_len += st->dma_info.slot_len[i];
++ }
++
++ *probably_last = 0;
++
++ if (st->hcchar_copy.b.eptype == 0x3) {
++ /*
++ * An interrupt endpoint will take max 2 CSPLITs. if we are receiving data
++ * then this is definitely the last CSPLIT.
++ */
++ *probably_last = 1;
++ } else {
++ /* Isoc IN. This is a bit risky if we are the first transaction:
++ * we may have been held off slightly. */
++ if (i > 1 && st->dma_info.slot_len[st->dma_info.index-1] <= DATA0_PID_HEURISTIC) {
++ more_needed = 0;
++ }
++ /* If in the next uframe we will receive enough data to fill the endpoint,
++ * then only issue 1 more csplit.
++ */
++ if (st->hctsiz_copy.b.xfersize - total_len <= DATA0_PID_HEURISTIC)
++ *probably_last = 1;
++ }
++
++ if (total_len >= st->hctsiz_copy.b.xfersize ||
++ i == 6 || total_len == 0)
++ /* Note: due to bit stuffing it is possible to have > 6 CSPLITs for
++ * a single endpoint. Accepting more would completely break our scheduling mechanism though
++ * - in these extreme cases we will pass through a truncated packet.
++ */
++ more_needed = 0;
++
++ return more_needed;
++}
++
++/**
++ * fiq_fsm_too_late() - Test transaction for lateness
++ *
++ * If a SSPLIT for a large IN transaction is issued too late in a frame,
++ * the hub will disable the port to the device and respond with ERR handshakes.
++ * The hub status endpoint will not reflect this change.
++ * Returns 1 if we will issue a SSPLIT that will result in a device babble.
++ */
++int notrace fiq_fsm_too_late(struct fiq_state *st, int n)
++{
++ int uframe;
++ hfnum_data_t hfnum = { .d32 = FIQ_READ(st->dwc_regs_base + HFNUM) };
++ uframe = hfnum.b.frnum & 0x7;
++ if ((uframe < 6) && (st->channel[n].nrpackets + 1 + uframe > 7)) {
++ return 1;
++ } else {
++ return 0;
++ }
++}
++
++
++/**
++ * fiq_fsm_start_next_periodic() - A half-arsed attempt at a microframe pipeline
++ *
++ * Search pending transactions in the start-split pending state and queue them.
++ * Don't queue packets in uframe .5 (comes out in .6) (USB2.0 11.18.4).
++ * Note: we specifically don't do isochronous OUT transactions first because better
++ * use of the TT's start-split fifo can be achieved by pipelining an IN before an OUT.
++ */
++static void notrace noinline fiq_fsm_start_next_periodic(struct fiq_state *st, int num_channels)
++{
++ int n;
++ hfnum_data_t hfnum = { .d32 = FIQ_READ(st->dwc_regs_base + HFNUM) };
++ if ((hfnum.b.frnum & 0x7) == 5)
++ return;
++ for (n = 0; n < num_channels; n++) {
++ if (st->channel[n].fsm == FIQ_PER_SSPLIT_QUEUED) {
++ /* Check to see if any other transactions are using this TT */
++ if(!fiq_fsm_tt_in_use(st, num_channels, n)) {
++ if (!fiq_fsm_too_late(st, n)) {
++ st->channel[n].fsm = FIQ_PER_SSPLIT_STARTED;
++ fiq_print(FIQDBG_INT, st, "NEXTPER ");
++ fiq_fsm_restart_channel(st, n, 0);
++ } else {
++ st->channel[n].fsm = FIQ_PER_SPLIT_TIMEOUT;
++ }
++ break;
++ }
++ }
++ }
++ for (n = 0; n < num_channels; n++) {
++ if (st->channel[n].fsm == FIQ_PER_ISO_OUT_PENDING) {
++ if (!fiq_fsm_tt_in_use(st, num_channels, n)) {
++ fiq_print(FIQDBG_INT, st, "NEXTISO ");
++ st->channel[n].fsm = FIQ_PER_ISO_OUT_ACTIVE;
++ fiq_fsm_restart_channel(st, n, 0);
++ break;
++ }
++ }
++ }
++}
++
++/**
++ * fiq_fsm_update_hs_isoc() - update isochronous frame and transfer data
++ * @state: Pointer to fiq_state
++ * @n: Channel transaction is active on
++ * @hcint: Copy of host channel interrupt register
++ *
++ * Returns 0 if there are no more transactions for this HC to do, 1
++ * otherwise.
++ */
++static int notrace noinline fiq_fsm_update_hs_isoc(struct fiq_state *state, int n, hcint_data_t hcint)
++{
++ struct fiq_channel_state *st = &state->channel[n];
++ int xfer_len = 0, nrpackets = 0;
++ hcdma_data_t hcdma;
++ fiq_print(FIQDBG_INT, state, "HSISO %02d", n);
++
++ xfer_len = fiq_get_xfer_len(state, n);
++ st->hs_isoc_info.iso_desc[st->hs_isoc_info.index].actual_length = xfer_len;
++
++ st->hs_isoc_info.iso_desc[st->hs_isoc_info.index].status = hcint.d32;
++
++ st->hs_isoc_info.index++;
++ if (st->hs_isoc_info.index == st->hs_isoc_info.nrframes) {
++ return 0;
++ }
++
++ /* grab the next DMA address offset from the array */
++ hcdma.d32 = st->hcdma_copy.d32 + st->hs_isoc_info.iso_desc[st->hs_isoc_info.index].offset;
++ FIQ_WRITE(state->dwc_regs_base + HC_DMA + (HC_OFFSET * n), hcdma.d32);
++
++ /* We need to set multi_count. This is a bit tricky - has to be set per-transaction as
++ * the core needs to be told to send the correct number. Caution: for IN transfers,
++ * this is always set to the maximum size of the endpoint. */
++ xfer_len = st->hs_isoc_info.iso_desc[st->hs_isoc_info.index].length;
++ /* Integer divide in a FIQ: fun. FIXME: make this not suck */
++ nrpackets = (xfer_len + st->hcchar_copy.b.mps - 1) / st->hcchar_copy.b.mps;
++ if (nrpackets == 0)
++ nrpackets = 1;
++ st->hcchar_copy.b.multicnt = nrpackets;
++ st->hctsiz_copy.b.pktcnt = nrpackets;
++
++ /* Initial PID also needs to be set */
++ if (st->hcchar_copy.b.epdir == 0) {
++ st->hctsiz_copy.b.xfersize = xfer_len;
++ switch (st->hcchar_copy.b.multicnt) {
++ case 1:
++ st->hctsiz_copy.b.pid = DWC_PID_DATA0;
++ break;
++ case 2:
++ case 3:
++ st->hctsiz_copy.b.pid = DWC_PID_MDATA;
++ break;
++ }
++
++ } else {
++ switch (st->hcchar_copy.b.multicnt) {
++ st->hctsiz_copy.b.xfersize = nrpackets * st->hcchar_copy.b.mps;
++ case 1:
++ st->hctsiz_copy.b.pid = DWC_PID_DATA0;
++ break;
++ case 2:
++ st->hctsiz_copy.b.pid = DWC_PID_DATA1;
++ break;
++ case 3:
++ st->hctsiz_copy.b.pid = DWC_PID_DATA2;
++ break;
++ }
++ }
++ FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ, st->hctsiz_copy.d32);
++ FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR, st->hcchar_copy.d32);
++ /* Channel is enabled on hcint handler exit */
++ fiq_print(FIQDBG_INT, state, "HSISOOUT");
++ return 1;
++}
++
++
++/**
++ * fiq_fsm_do_sof() - FSM start-of-frame interrupt handler
++ * @state: Pointer to the state struct passed from banked FIQ mode registers.
++ * @num_channels: set according to the DWC hardware configuration
++ *
++ * The SOF handler in FSM mode has two functions
++ * 1. Hold off SOF from causing schedule advancement in IRQ context if there's
++ * nothing to do
++ * 2. Advance certain FSM states that require either a microframe delay, or a microframe
++ * of holdoff.
++ *
++ * The second part is architecture-specific to mach-bcm2835 -
++ * a sane interrupt controller would have a mask register for ARM interrupt sources
++ * to be promoted to the nFIQ line, but it doesn't. Instead a single interrupt
++ * number (USB) can be enabled. This means that certain parts of the USB specification
++ * that require "wait a little while, then issue another packet" cannot be fulfilled with
++ * the timing granularity required to achieve optimal throughout. The workaround is to use
++ * the SOF "timer" (125uS) to perform this task.
++ */
++static int notrace noinline fiq_fsm_do_sof(struct fiq_state *state, int num_channels)
++{
++ hfnum_data_t hfnum = { .d32 = FIQ_READ(state->dwc_regs_base + HFNUM) };
++ int n;
++ int kick_irq = 0;
++
++ if ((hfnum.b.frnum & 0x7) == 1) {
++ /* We cannot issue csplits for transactions in the last frame past (n+1).1
++ * Check to see if there are any transactions that are stale.
++ * Boot them out.
++ */
++ for (n = 0; n < num_channels; n++) {
++ switch (state->channel[n].fsm) {
++ case FIQ_PER_CSPLIT_WAIT:
++ case FIQ_PER_CSPLIT_NYET1:
++ case FIQ_PER_CSPLIT_POLL:
++ case FIQ_PER_CSPLIT_LAST:
++ /* Check if we are no longer in the same full-speed frame. */
++ if (((state->channel[n].expected_uframe & 0x3FFF) & ~0x7) <
++ (hfnum.b.frnum & ~0x7))
++ state->channel[n].fsm = FIQ_PER_SPLIT_TIMEOUT;
++ break;
++ default:
++ break;
++ }
++ }
++ }
++
++ for (n = 0; n < num_channels; n++) {
++ switch (state->channel[n].fsm) {
++
++ case FIQ_NP_SSPLIT_RETRY:
++ case FIQ_NP_IN_CSPLIT_RETRY:
++ case FIQ_NP_OUT_CSPLIT_RETRY:
++ fiq_fsm_restart_channel(state, n, 0);
++ break;
++
++ case FIQ_HS_ISOC_SLEEPING:
++ state->channel[n].fsm = FIQ_HS_ISOC_TURBO;
++ fiq_fsm_restart_channel(state, n, 0);
++ break;
++
++ case FIQ_PER_SSPLIT_QUEUED:
++ if ((hfnum.b.frnum & 0x7) == 5)
++ break;
++ if(!fiq_fsm_tt_in_use(state, num_channels, n)) {
++ if (!fiq_fsm_too_late(state, n)) {
++ fiq_print(FIQDBG_INT, st, "SOF GO %01d", n);
++ fiq_fsm_restart_channel(state, n, 0);
++ state->channel[n].fsm = FIQ_PER_SSPLIT_STARTED;
++ } else {
++ /* Transaction cannot be started without risking a device babble error */
++ state->channel[n].fsm = FIQ_PER_SPLIT_TIMEOUT;
++ state->haintmsk_saved.b2.chint &= ~(1 << n);
++ FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINTMSK, 0);
++ kick_irq |= 1;
++ }
++ }
++ break;
++
++ case FIQ_PER_ISO_OUT_PENDING:
++ /* Ordinarily, this should be poked after the SSPLIT
++ * complete interrupt for a competing transfer on the same
++ * TT. Doesn't happen for aborted transactions though.
++ */
++ if ((hfnum.b.frnum & 0x7) >= 5)
++ break;
++ if (!fiq_fsm_tt_in_use(state, num_channels, n)) {
++ /* Hardware bug. SOF can sometimes occur after the channel halt interrupt
++ * that caused this.
++ */
++ fiq_fsm_restart_channel(state, n, 0);
++ fiq_print(FIQDBG_INT, state, "SOF ISOC");
++ if (state->channel[n].nrpackets == 1) {
++ state->channel[n].fsm = FIQ_PER_ISO_OUT_LAST;
++ } else {
++ state->channel[n].fsm = FIQ_PER_ISO_OUT_ACTIVE;
++ }
++ }
++ break;
++
++ case FIQ_PER_CSPLIT_WAIT:
++ /* we are guaranteed to be in this state if and only if the SSPLIT interrupt
++ * occurred when the bus transaction occurred. The SOF interrupt reversal bug
++ * will utterly bugger this up though.
++ */
++ if (hfnum.b.frnum != state->channel[n].expected_uframe) {
++ fiq_print(FIQDBG_INT, state, "SOFCS %d ", n);
++ state->channel[n].fsm = FIQ_PER_CSPLIT_POLL;
++ fiq_fsm_restart_channel(state, n, 0);
++ fiq_fsm_start_next_periodic(state, num_channels);
++
++ }
++ break;
++
++ case FIQ_PER_SPLIT_TIMEOUT:
++ case FIQ_DEQUEUE_ISSUED:
++ /* Ugly: we have to force a HCD interrupt.
++ * Poke the mask for the channel in question.
++ * We will take a fake SOF because of this, but
++ * that's OK.
++ */
++ state->haintmsk_saved.b2.chint &= ~(1 << n);
++ FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINTMSK, 0);
++ kick_irq |= 1;
++ break;
++
++ default:
++ break;
++ }
++ }
++
++ if (state->kick_np_queues ||
++ dwc_frame_num_le(state->next_sched_frame, hfnum.b.frnum))
++ kick_irq |= 1;
++
++ return !kick_irq;
++}
++
++
++/**
++ * fiq_fsm_do_hcintr() - FSM host channel interrupt handler
++ * @state: Pointer to the FIQ state struct
++ * @num_channels: Number of channels as per hardware config
++ * @n: channel for which HAINT(i) was raised
++ *
++ * An important property is that only the CHHLT interrupt is unmasked. Unfortunately, AHBerr is as well.
++ */
++static int notrace noinline fiq_fsm_do_hcintr(struct fiq_state *state, int num_channels, int n)
++{
++ hcint_data_t hcint;
++ hcintmsk_data_t hcintmsk;
++ hcint_data_t hcint_probe;
++ hcchar_data_t hcchar;
++ int handled = 0;
++ int restart = 0;
++ int last_csplit = 0;
++ int start_next_periodic = 0;
++ struct fiq_channel_state *st = &state->channel[n];
++ hfnum_data_t hfnum;
++
++ hcint.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINT);
++ hcintmsk.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINTMSK);
++ hcint_probe.d32 = hcint.d32 & hcintmsk.d32;
++
++ if (st->fsm != FIQ_PASSTHROUGH) {
++ fiq_print(FIQDBG_INT, state, "HC%01d ST%02d", n, st->fsm);
++ fiq_print(FIQDBG_INT, state, "%08x", hcint.d32);
++ }
++
++ switch (st->fsm) {
++
++ case FIQ_PASSTHROUGH:
++ case FIQ_DEQUEUE_ISSUED:
++ /* doesn't belong to us, kick it upstairs */
++ break;
++
++ case FIQ_PASSTHROUGH_ERRORSTATE:
++ /* We are here to emulate the error recovery mechanism of the dwc HCD.
++ * Several interrupts are unmasked if a previous transaction failed - it's
++ * death for the FIQ to attempt to handle them as the channel isn't halted.
++ * Emulate what the HCD does in this situation: mask and continue.
++ * The FSM has no other state setup so this has to be handled out-of-band.
++ */
++ fiq_print(FIQDBG_ERR, state, "ERRST %02d", n);
++ if (hcint_probe.b.nak || hcint_probe.b.ack || hcint_probe.b.datatglerr) {
++ fiq_print(FIQDBG_ERR, state, "RESET %02d", n);
++ /* In some random cases we can get a NAK interrupt coincident with a Xacterr
++ * interrupt, after the device has disappeared.
++ */
++ if (!hcint.b.xacterr)
++ st->nr_errors = 0;
++ hcintmsk.b.nak = 0;
++ hcintmsk.b.ack = 0;
++ hcintmsk.b.datatglerr = 0;
++ FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINTMSK, hcintmsk.d32);
++ return 1;
++ }
++ if (hcint_probe.b.chhltd) {
++ fiq_print(FIQDBG_ERR, state, "CHHLT %02d", n);
++ fiq_print(FIQDBG_ERR, state, "%08x", hcint.d32);
++ return 0;
++ }
++ break;
++
++ /* Non-periodic state groups */
++ case FIQ_NP_SSPLIT_STARTED:
++ case FIQ_NP_SSPLIT_RETRY:
++ /* Got a HCINT for a NP SSPLIT. Expected ACK / NAK / fail */
++ if (hcint.b.ack) {
++ /* SSPLIT complete. For OUT, the data has been sent. For IN, the LS transaction
++ * will start shortly. SOF needs to kick the transaction to prevent a NYET flood.
++ */
++ if(st->hcchar_copy.b.epdir == 1)
++ st->fsm = FIQ_NP_IN_CSPLIT_RETRY;
++ else
++ st->fsm = FIQ_NP_OUT_CSPLIT_RETRY;
++ st->nr_errors = 0;
++ handled = 1;
++ fiq_fsm_setup_csplit(state, n);
++ } else if (hcint.b.nak) {
++ // No buffer space in TT. Retry on a uframe boundary.
++ st->fsm = FIQ_NP_SSPLIT_RETRY;
++ handled = 1;
++ } else if (hcint.b.xacterr) {
++ // The only other one we care about is xacterr. This implies HS bus error - retry.
++ st->nr_errors++;
++ st->fsm = FIQ_NP_SSPLIT_RETRY;
++ if (st->nr_errors >= 3) {
++ st->fsm = FIQ_NP_SPLIT_HS_ABORTED;
++ } else {
++ handled = 1;
++ restart = 1;
++ }
++ } else {
++ st->fsm = FIQ_NP_SPLIT_LS_ABORTED;
++ handled = 0;
++ restart = 0;
++ }
++ break;
++
++ case FIQ_NP_IN_CSPLIT_RETRY:
++ /* Received a CSPLIT done interrupt.
++ * Expected Data/NAK/STALL/NYET for IN.
++ */
++ if (hcint.b.xfercomp) {
++ /* For IN, data is present. */
++ st->fsm = FIQ_NP_SPLIT_DONE;
++ } else if (hcint.b.nak) {
++ /* no endpoint data. Punt it upstairs */
++ st->fsm = FIQ_NP_SPLIT_DONE;
++ } else if (hcint.b.nyet) {
++ /* CSPLIT NYET - retry on a uframe boundary. */
++ handled = 1;
++ st->nr_errors = 0;
++ } else if (hcint.b.datatglerr) {
++ /* data toggle errors do not set the xfercomp bit. */
++ st->fsm = FIQ_NP_SPLIT_LS_ABORTED;
++ } else if (hcint.b.xacterr) {
++ /* HS error. Retry immediate */
++ st->fsm = FIQ_NP_IN_CSPLIT_RETRY;
++ st->nr_errors++;
++ if (st->nr_errors >= 3) {
++ st->fsm = FIQ_NP_SPLIT_HS_ABORTED;
++ } else {
++ handled = 1;
++ restart = 1;
++ }
++ } else if (hcint.b.stall || hcint.b.bblerr) {
++ /* A STALL implies either a LS bus error or a genuine STALL. */
++ st->fsm = FIQ_NP_SPLIT_LS_ABORTED;
++ } else {
++ /* Hardware bug. It's possible in some cases to
++ * get a channel halt with nothing else set when
++ * the response was a NYET. Treat as local 3-strikes retry.
++ */
++ hcint_data_t hcint_test = hcint;
++ hcint_test.b.chhltd = 0;
++ if (!hcint_test.d32) {
++ st->nr_errors++;
++ if (st->nr_errors >= 3) {
++ st->fsm = FIQ_NP_SPLIT_HS_ABORTED;
++ } else {
++ handled = 1;
++ }
++ } else {
++ /* Bail out if something unexpected happened */
++ st->fsm = FIQ_NP_SPLIT_HS_ABORTED;
++ }
++ }
++ break;
++
++ case FIQ_NP_OUT_CSPLIT_RETRY:
++ /* Received a CSPLIT done interrupt.
++ * Expected ACK/NAK/STALL/NYET/XFERCOMP for OUT.*/
++ if (hcint.b.xfercomp) {
++ st->fsm = FIQ_NP_SPLIT_DONE;
++ } else if (hcint.b.nak) {
++ // The HCD will implement the holdoff on frame boundaries.
++ st->fsm = FIQ_NP_SPLIT_DONE;
++ } else if (hcint.b.nyet) {
++ // Hub still processing.
++ st->fsm = FIQ_NP_OUT_CSPLIT_RETRY;
++ handled = 1;
++ st->nr_errors = 0;
++ //restart = 1;
++ } else if (hcint.b.xacterr) {
++ /* HS error. retry immediate */
++ st->fsm = FIQ_NP_OUT_CSPLIT_RETRY;
++ st->nr_errors++;
++ if (st->nr_errors >= 3) {
++ st->fsm = FIQ_NP_SPLIT_HS_ABORTED;
++ } else {
++ handled = 1;
++ restart = 1;
++ }
++ } else if (hcint.b.stall) {
++ /* LS bus error or genuine stall */
++ st->fsm = FIQ_NP_SPLIT_LS_ABORTED;
++ } else {
++ /*
++ * Hardware bug. It's possible in some cases to get a
++ * channel halt with nothing else set when the response was a NYET.
++ * Treat as local 3-strikes retry.
++ */
++ hcint_data_t hcint_test = hcint;
++ hcint_test.b.chhltd = 0;
++ if (!hcint_test.d32) {
++ st->nr_errors++;
++ if (st->nr_errors >= 3) {
++ st->fsm = FIQ_NP_SPLIT_HS_ABORTED;
++ } else {
++ handled = 1;
++ }
++ } else {
++ // Something unexpected happened. AHBerror or babble perhaps. Let the IRQ deal with it.
++ st->fsm = FIQ_NP_SPLIT_HS_ABORTED;
++ }
++ }
++ break;
++
++ /* Periodic split states (except isoc out) */
++ case FIQ_PER_SSPLIT_STARTED:
++ /* Expect an ACK or failure for SSPLIT */
++ if (hcint.b.ack) {
++ /*
++ * SSPLIT transfer complete interrupt - the generation of this interrupt is fraught with bugs.
++ * For a packet queued in microframe n-3 to appear in n-2, if the channel is enabled near the EOF1
++ * point for microframe n-3, the packet will not appear on the bus until microframe n.
++ * Additionally, the generation of the actual interrupt is dodgy. For a packet appearing on the bus
++ * in microframe n, sometimes the interrupt is generated immediately. Sometimes, it appears in n+1
++ * coincident with SOF for n+1.
++ * SOF is also buggy. It can sometimes be raised AFTER the first bus transaction has taken place.
++ * These appear to be caused by timing/clock crossing bugs within the core itself.
++ * State machine workaround.
++ */
++ hfnum.d32 = FIQ_READ(state->dwc_regs_base + HFNUM);
++ hcchar.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR);
++ fiq_fsm_setup_csplit(state, n);
++ /* Poke the oddfrm bit. If we are equivalent, we received the interrupt at the correct
++ * time. If not, then we're in the next SOF.
++ */
++ if ((hfnum.b.frnum & 0x1) == hcchar.b.oddfrm) {
++ fiq_print(FIQDBG_INT, state, "CSWAIT %01d", n);
++ st->expected_uframe = hfnum.b.frnum;
++ st->fsm = FIQ_PER_CSPLIT_WAIT;
++ } else {
++ fiq_print(FIQDBG_INT, state, "CSPOL %01d", n);
++ /* For isochronous IN endpoints,
++ * we need to hold off if we are expecting a lot of data */
++ if (st->hcchar_copy.b.mps < DATA0_PID_HEURISTIC) {
++ start_next_periodic = 1;
++ }
++ /* Danger will robinson: we are in a broken state. If our first interrupt after
++ * this is a NYET, it will be delayed by 1 uframe and result in an unrecoverable
++ * lag. Unmask the NYET interrupt.
++ */
++ st->expected_uframe = (hfnum.b.frnum + 1) & 0x3FFF;
++ st->fsm = FIQ_PER_CSPLIT_BROKEN_NYET1;
++ restart = 1;
++ }
++ handled = 1;
++ } else if (hcint.b.xacterr) {
++ /* 3-strikes retry is enabled, we have hit our max nr_errors */
++ st->fsm = FIQ_PER_SPLIT_HS_ABORTED;
++ start_next_periodic = 1;
++ } else {
++ st->fsm = FIQ_PER_SPLIT_HS_ABORTED;
++ start_next_periodic = 1;
++ }
++ /* We can now queue the next isochronous OUT transaction, if one is pending. */
++ if(fiq_fsm_tt_next_isoc(state, num_channels, n)) {
++ fiq_print(FIQDBG_INT, state, "NEXTISO ");
++ }
++ break;
++
++ case FIQ_PER_CSPLIT_NYET1:
++ /* First CSPLIT attempt was a NYET. If we get a subsequent NYET,
++ * we are too late and the TT has dropped its CSPLIT fifo.
++ */
++ hfnum.d32 = FIQ_READ(state->dwc_regs_base + HFNUM);
++ hcchar.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR);
++ start_next_periodic = 1;
++ if (hcint.b.nak) {
++ st->fsm = FIQ_PER_SPLIT_DONE;
++ } else if (hcint.b.xfercomp) {
++ fiq_increment_dma_buf(state, num_channels, n);
++ st->fsm = FIQ_PER_CSPLIT_POLL;
++ st->nr_errors = 0;
++ if (fiq_fsm_more_csplits(state, n, &last_csplit)) {
++ handled = 1;
++ restart = 1;
++ if (!last_csplit)
++ start_next_periodic = 0;
++ } else {
++ st->fsm = FIQ_PER_SPLIT_DONE;
++ }
++ } else if (hcint.b.nyet) {
++ /* Doh. Data lost. */
++ st->fsm = FIQ_PER_SPLIT_NYET_ABORTED;
++ } else if (hcint.b.xacterr || hcint.b.stall || hcint.b.bblerr) {
++ st->fsm = FIQ_PER_SPLIT_LS_ABORTED;
++ } else {
++ st->fsm = FIQ_PER_SPLIT_HS_ABORTED;
++ }
++ break;
++
++ case FIQ_PER_CSPLIT_BROKEN_NYET1:
++ /*
++ * we got here because our host channel is in the delayed-interrupt
++ * state and we cannot take a NYET interrupt any later than when it
++ * occurred. Disable then re-enable the channel if this happens to force
++ * CSPLITs to occur at the right time.
++ */
++ hfnum.d32 = FIQ_READ(state->dwc_regs_base + HFNUM);
++ hcchar.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR);
++ fiq_print(FIQDBG_INT, state, "BROK: %01d ", n);
++ if (hcint.b.nak) {
++ st->fsm = FIQ_PER_SPLIT_DONE;
++ start_next_periodic = 1;
++ } else if (hcint.b.xfercomp) {
++ fiq_increment_dma_buf(state, num_channels, n);
++ if (fiq_fsm_more_csplits(state, n, &last_csplit)) {
++ st->fsm = FIQ_PER_CSPLIT_POLL;
++ handled = 1;
++ restart = 1;
++ start_next_periodic = 1;
++ /* Reload HCTSIZ for the next transfer */
++ fiq_fsm_reload_hctsiz(state, n);
++ if (!last_csplit)
++ start_next_periodic = 0;
++ } else {
++ st->fsm = FIQ_PER_SPLIT_DONE;
++ }
++ } else if (hcint.b.nyet) {
++ st->fsm = FIQ_PER_SPLIT_NYET_ABORTED;
++ start_next_periodic = 1;
++ } else if (hcint.b.xacterr || hcint.b.stall || hcint.b.bblerr) {
++ /* Local 3-strikes retry is handled by the core. This is a ERR response.*/
++ st->fsm = FIQ_PER_SPLIT_LS_ABORTED;
++ } else {
++ st->fsm = FIQ_PER_SPLIT_HS_ABORTED;
++ }
++ break;
++
++ case FIQ_PER_CSPLIT_POLL:
++ hfnum.d32 = FIQ_READ(state->dwc_regs_base + HFNUM);
++ hcchar.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR);
++ start_next_periodic = 1;
++ if (hcint.b.nak) {
++ st->fsm = FIQ_PER_SPLIT_DONE;
++ } else if (hcint.b.xfercomp) {
++ fiq_increment_dma_buf(state, num_channels, n);
++ if (fiq_fsm_more_csplits(state, n, &last_csplit)) {
++ handled = 1;
++ restart = 1;
++ /* Reload HCTSIZ for the next transfer */
++ fiq_fsm_reload_hctsiz(state, n);
++ if (!last_csplit)
++ start_next_periodic = 0;
++ } else {
++ st->fsm = FIQ_PER_SPLIT_DONE;
++ }
++ } else if (hcint.b.nyet) {
++ /* Are we a NYET after the first data packet? */
++ if (st->nrpackets == 0) {
++ st->fsm = FIQ_PER_CSPLIT_NYET1;
++ handled = 1;
++ restart = 1;
++ } else {
++ /* We got a NYET when polling CSPLITs. Can happen
++ * if our heuristic fails, or if someone disables us
++ * for any significant length of time.
++ */
++ if (st->nr_errors >= 3) {
++ st->fsm = FIQ_PER_SPLIT_NYET_ABORTED;
++ } else {
++ st->fsm = FIQ_PER_SPLIT_DONE;
++ }
++ }
++ } else if (hcint.b.xacterr || hcint.b.stall || hcint.b.bblerr) {
++ /* For xacterr, Local 3-strikes retry is handled by the core. This is a ERR response.*/
++ st->fsm = FIQ_PER_SPLIT_LS_ABORTED;
++ } else {
++ st->fsm = FIQ_PER_SPLIT_HS_ABORTED;
++ }
++ break;
++
++ case FIQ_HS_ISOC_TURBO:
++ if (fiq_fsm_update_hs_isoc(state, n, hcint)) {
++ /* more transactions to come */
++ handled = 1;
++ restart = 1;
++ fiq_print(FIQDBG_INT, state, "HSISO M ");
++ } else {
++ st->fsm = FIQ_HS_ISOC_DONE;
++ fiq_print(FIQDBG_INT, state, "HSISO F ");
++ }
++ break;
++
++ case FIQ_HS_ISOC_ABORTED:
++ /* This abort is called by the driver rewriting the state mid-transaction
++ * which allows the dequeue mechanism to work more effectively.
++ */
++ break;
++
++ case FIQ_PER_ISO_OUT_ACTIVE:
++ if (hcint.b.ack) {
++ if(fiq_iso_out_advance(state, num_channels, n)) {
++ /* last OUT transfer */
++ st->fsm = FIQ_PER_ISO_OUT_LAST;
++ /*
++ * Assuming the periodic FIFO in the dwc core
++ * actually does its job properly, we can queue
++ * the next ssplit now and in theory, the wire
++ * transactions will be in-order.
++ */
++ // No it doesn't. It appears to process requests in host channel order.
++ //start_next_periodic = 1;
++ }
++ handled = 1;
++ restart = 1;
++ } else {
++ /*
++ * Isochronous transactions carry on regardless. Log the error
++ * and continue.
++ */
++ //explode += 1;
++ st->nr_errors++;
++ if(fiq_iso_out_advance(state, num_channels, n)) {
++ st->fsm = FIQ_PER_ISO_OUT_LAST;
++ //start_next_periodic = 1;
++ }
++ handled = 1;
++ restart = 1;
++ }
++ break;
++
++ case FIQ_PER_ISO_OUT_LAST:
++ if (hcint.b.ack) {
++ /* All done here */
++ st->fsm = FIQ_PER_ISO_OUT_DONE;
++ } else {
++ st->fsm = FIQ_PER_ISO_OUT_DONE;
++ st->nr_errors++;
++ }
++ start_next_periodic = 1;
++ break;
++
++ case FIQ_PER_SPLIT_TIMEOUT:
++ /* SOF kicked us because we overran. */
++ start_next_periodic = 1;
++ break;
++
++ default:
++ break;
++ }
++
++ if (handled) {
++ FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINT, hcint.d32);
++ } else {
++ /* Copy the regs into the state so the IRQ knows what to do */
++ st->hcint_copy.d32 = hcint.d32;
++ }
++
++ if (restart) {
++ /* Restart always implies handled. */
++ if (restart == 2) {
++ /* For complete-split INs, the show must go on.
++ * Force a channel restart */
++ fiq_fsm_restart_channel(state, n, 1);
++ } else {
++ fiq_fsm_restart_channel(state, n, 0);
++ }
++ }
++ if (start_next_periodic) {
++ fiq_fsm_start_next_periodic(state, num_channels);
++ }
++ if (st->fsm != FIQ_PASSTHROUGH)
++ fiq_print(FIQDBG_INT, state, "FSMOUT%02d", st->fsm);
++
++ return handled;
++}
++
++
++/**
++ * dwc_otg_fiq_fsm() - Flying State Machine (monster) FIQ
++ * @state: pointer to state struct passed from the banked FIQ mode registers.
++ * @num_channels: set according to the DWC hardware configuration
++ * @dma: pointer to DMA bounce buffers for split transaction slots
++ *
++ * The FSM FIQ performs the low-level tasks that normally would be performed by the microcode
++ * inside an EHCI or similar host controller regarding split transactions. The DWC core
++ * interrupts each and every time a split transaction packet is received or sent successfully.
++ * This results in either an interrupt storm when everything is working "properly", or
++ * the interrupt latency of the system in general breaks time-sensitive periodic split
++ * transactions. Pushing the low-level, but relatively easy state machine work into the FIQ
++ * solves these problems.
++ *
++ * Return: void
++ */
++void notrace dwc_otg_fiq_fsm(struct fiq_state *state, int num_channels)
++{
++ gintsts_data_t gintsts, gintsts_handled;
++ gintmsk_data_t gintmsk;
++ //hfnum_data_t hfnum;
++ haint_data_t haint, haint_handled;
++ haintmsk_data_t haintmsk;
++ int kick_irq = 0;
++
++ gintsts_handled.d32 = 0;
++ haint_handled.d32 = 0;
++
++ fiq_fsm_spin_lock(&state->lock);
++ gintsts.d32 = FIQ_READ(state->dwc_regs_base + GINTSTS);
++ gintmsk.d32 = FIQ_READ(state->dwc_regs_base + GINTMSK);
++ gintsts.d32 &= gintmsk.d32;
++
++ if (gintsts.b.sofintr) {
++ /* For FSM mode, SOF is required to keep the state machine advance for
++ * certain stages of the periodic pipeline. It's death to mask this
++ * interrupt in that case.
++ */
++
++ if (!fiq_fsm_do_sof(state, num_channels)) {
++ /* Kick IRQ once. Queue advancement means that all pending transactions
++ * will get serviced when the IRQ finally executes.
++ */
++ if (state->gintmsk_saved.b.sofintr == 1)
++ kick_irq |= 1;
++ state->gintmsk_saved.b.sofintr = 0;
++ }
++ gintsts_handled.b.sofintr = 1;
++ }
++
++ if (gintsts.b.hcintr) {
++ int i;
++ haint.d32 = FIQ_READ(state->dwc_regs_base + HAINT);
++ haintmsk.d32 = FIQ_READ(state->dwc_regs_base + HAINTMSK);
++ haint.d32 &= haintmsk.d32;
++ haint_handled.d32 = 0;
++ for (i=0; i<num_channels; i++) {
++ if (haint.b2.chint & (1 << i)) {
++ if(!fiq_fsm_do_hcintr(state, num_channels, i)) {
++ /* HCINT was not handled in FIQ
++ * HAINT is level-sensitive, leading to level-sensitive ginststs.b.hcint bit.
++ * Mask HAINT(i) but keep top-level hcint unmasked.
++ */
++ state->haintmsk_saved.b2.chint &= ~(1 << i);
++ } else {
++ /* do_hcintr cleaned up after itself, but clear haint */
++ haint_handled.b2.chint |= (1 << i);
++ }
++ }
++ }
++
++ if (haint_handled.b2.chint) {
++ FIQ_WRITE(state->dwc_regs_base + HAINT, haint_handled.d32);
++ }
++
++ if (haintmsk.d32 != (haintmsk.d32 & state->haintmsk_saved.d32)) {
++ /*
++ * This is necessary to avoid multiple retriggers of the MPHI in the case
++ * where interrupts are held off and HCINTs start to pile up.
++ * Only wake up the IRQ if a new interrupt came in, was not handled and was
++ * masked.
++ */
++ haintmsk.d32 &= state->haintmsk_saved.d32;
++ FIQ_WRITE(state->dwc_regs_base + HAINTMSK, haintmsk.d32);
++ kick_irq |= 1;
++ }
++ /* Top-Level interrupt - always handled because it's level-sensitive */
++ gintsts_handled.b.hcintr = 1;
++ }
++
++
++ /* Clear the bits in the saved register that were not handled but were triggered. */
++ state->gintmsk_saved.d32 &= ~(gintsts.d32 & ~gintsts_handled.d32);
++
++ /* FIQ didn't handle something - mask has changed - write new mask */
++ if (gintmsk.d32 != (gintmsk.d32 & state->gintmsk_saved.d32)) {
++ gintmsk.d32 &= state->gintmsk_saved.d32;
++ gintmsk.b.sofintr = 1;
++ FIQ_WRITE(state->dwc_regs_base + GINTMSK, gintmsk.d32);
++// fiq_print(FIQDBG_INT, state, "KICKGINT");
++// fiq_print(FIQDBG_INT, state, "%08x", gintmsk.d32);
++// fiq_print(FIQDBG_INT, state, "%08x", state->gintmsk_saved.d32);
++ kick_irq |= 1;
++ }
++
++ if (gintsts_handled.d32) {
++ /* Only applies to edge-sensitive bits in GINTSTS */
++ FIQ_WRITE(state->dwc_regs_base + GINTSTS, gintsts_handled.d32);
++ }
++
++ /* We got an interrupt, didn't handle it. */
++ if (kick_irq) {
++ state->mphi_int_count++;
++ FIQ_WRITE(state->mphi_regs.outdda, (int) state->dummy_send);
++ FIQ_WRITE(state->mphi_regs.outddb, (1<<29));
++
++ }
++ state->fiq_done++;
++ mb();
++ fiq_fsm_spin_unlock(&state->lock);
++}
++
++
++/**
++ * dwc_otg_fiq_nop() - FIQ "lite"
++ * @state: pointer to state struct passed from the banked FIQ mode registers.
++ *
++ * The "nop" handler does not intervene on any interrupts other than SOF.
++ * It is limited in scope to deciding at each SOF if the IRQ SOF handler (which deals
++ * with non-periodic/periodic queues) needs to be kicked.
++ *
++ * This is done to hold off the SOF interrupt, which occurs at a rate of 8000 per second.
++ *
++ * Return: void
++ */
++void notrace dwc_otg_fiq_nop(struct fiq_state *state)
++{
++ gintsts_data_t gintsts, gintsts_handled;
++ gintmsk_data_t gintmsk;
++ hfnum_data_t hfnum;
++
++ fiq_fsm_spin_lock(&state->lock);
++ hfnum.d32 = FIQ_READ(state->dwc_regs_base + HFNUM);
++ gintsts.d32 = FIQ_READ(state->dwc_regs_base + GINTSTS);
++ gintmsk.d32 = FIQ_READ(state->dwc_regs_base + GINTMSK);
++ gintsts.d32 &= gintmsk.d32;
++ gintsts_handled.d32 = 0;
++
++ if (gintsts.b.sofintr) {
++ if (!state->kick_np_queues &&
++ dwc_frame_num_gt(state->next_sched_frame, hfnum.b.frnum)) {
++ /* SOF handled, no work to do, just ACK interrupt */
++ gintsts_handled.b.sofintr = 1;
++ } else {
++ /* Kick IRQ */
++ state->gintmsk_saved.b.sofintr = 0;
++ }
++ }
++
++ /* Reset handled interrupts */
++ if(gintsts_handled.d32) {
++ FIQ_WRITE(state->dwc_regs_base + GINTSTS, gintsts_handled.d32);
++ }
++
++ /* Clear the bits in the saved register that were not handled but were triggered. */
++ state->gintmsk_saved.d32 &= ~(gintsts.d32 & ~gintsts_handled.d32);
++
++ /* We got an interrupt, didn't handle it and want to mask it */
++ if (~(state->gintmsk_saved.d32)) {
++ state->mphi_int_count++;
++ gintmsk.d32 &= state->gintmsk_saved.d32;
++ FIQ_WRITE(state->dwc_regs_base + GINTMSK, gintmsk.d32);
++ /* Force a clear before another dummy send */
++ FIQ_WRITE(state->mphi_regs.intstat, (1<<29));
++ FIQ_WRITE(state->mphi_regs.outdda, (int) state->dummy_send);
++ FIQ_WRITE(state->mphi_regs.outddb, (1<<29));
++
++ }
++ state->fiq_done++;
++ mb();
++ fiq_fsm_spin_unlock(&state->lock);
++}
+diff -Nur linux-4.1.3/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h linux-xbian-rpi/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h
+--- linux-4.1.3/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h 2015-07-28 01:20:58.445156473 +0200
+@@ -0,0 +1,367 @@
++/*
++ * dwc_otg_fiq_fsm.h - Finite state machine FIQ header definitions
++ *
++ * Copyright (c) 2013 Raspberry Pi Foundation
++ *
++ * Author: Jonathan Bell <jonathan@raspberrypi.org>
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * * Neither the name of Raspberry Pi nor the
++ * names of its contributors may be used to endorse or promote products
++ * derived from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
++ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
++ * DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ *
++ * This FIQ implements functionality that performs split transactions on
++ * the dwc_otg hardware without any outside intervention. A split transaction
++ * is "queued" by nominating a specific host channel to perform the entirety
++ * of a split transaction. This FIQ will then perform the microframe-precise
++ * scheduling required in each phase of the transaction until completion.
++ *
++ * The FIQ functionality has been surgically implanted into the Synopsys
++ * vendor-provided driver.
++ *
++ */
++
++#ifndef DWC_OTG_FIQ_FSM_H_
++#define DWC_OTG_FIQ_FSM_H_
++
++#include "dwc_otg_regs.h"
++#include "dwc_otg_cil.h"
++#include "dwc_otg_hcd.h"
++#include <linux/kernel.h>
++#include <linux/irqflags.h>
++#include <linux/string.h>
++#include <asm/barrier.h>
++
++#if 0
++#define FLAME_ON(x) \
++do { \
++ int gpioreg; \
++ \
++ gpioreg = readl(__io_address(0x20200000+0x8)); \
++ gpioreg &= ~(7 << (x-20)*3); \
++ gpioreg |= 0x1 << (x-20)*3; \
++ writel(gpioreg, __io_address(0x20200000+0x8)); \
++ \
++ writel(1<<x, __io_address(0x20200000+(0x1C))); \
++} while (0)
++
++#define FLAME_OFF(x) \
++do { \
++ writel(1<<x, __io_address(0x20200000+(0x28))); \
++} while (0)
++#else
++#define FLAME_ON(x) do { } while (0)
++#define FLAME_OFF(X) do { } while (0)
++#endif
++
++/* This is a quick-and-dirty arch-specific register read/write. We know that
++ * writes to a peripheral on BCM2835 will always arrive in-order, also that
++ * reads and writes are executed in-order therefore the need for memory barriers
++ * is obviated if we're only talking to USB.
++ */
++#define FIQ_WRITE(_addr_,_data_) (*(volatile unsigned int *) (_addr_) = (_data_))
++#define FIQ_READ(_addr_) (*(volatile unsigned int *) (_addr_))
++
++/* FIQ-ified register definitions. Offsets are from dwc_regs_base. */
++#define GINTSTS 0x014
++#define GINTMSK 0x018
++/* Debug register. Poll the top of the received packets FIFO. */
++#define GRXSTSR 0x01C
++#define HFNUM 0x408
++#define HAINT 0x414
++#define HAINTMSK 0x418
++#define HPRT0 0x440
++
++/* HC_regs start from an offset of 0x500 */
++#define HC_START 0x500
++#define HC_OFFSET 0x020
++
++#define HC_DMA 0x514
++
++#define HCCHAR 0x00
++#define HCSPLT 0x04
++#define HCINT 0x08
++#define HCINTMSK 0x0C
++#define HCTSIZ 0x10
++
++#define ISOC_XACTPOS_ALL 0b11
++#define ISOC_XACTPOS_BEGIN 0b10
++#define ISOC_XACTPOS_MID 0b00
++#define ISOC_XACTPOS_END 0b01
++
++#define DWC_PID_DATA2 0b01
++#define DWC_PID_MDATA 0b11
++#define DWC_PID_DATA1 0b10
++#define DWC_PID_DATA0 0b00
++
++typedef struct {
++ volatile void* base;
++ volatile void* ctrl;
++ volatile void* outdda;
++ volatile void* outddb;
++ volatile void* intstat;
++} mphi_regs_t;
++
++enum fiq_debug_level {
++ FIQDBG_SCHED = (1 << 0),
++ FIQDBG_INT = (1 << 1),
++ FIQDBG_ERR = (1 << 2),
++ FIQDBG_PORTHUB = (1 << 3),
++};
++
++typedef struct {
++ union {
++ uint32_t slock;
++ struct _tickets {
++ uint16_t owner;
++ uint16_t next;
++ } tickets;
++ };
++} fiq_lock_t;
++
++struct fiq_state;
++
++extern void _fiq_print (enum fiq_debug_level dbg_lvl, volatile struct fiq_state *state, char *fmt, ...);
++#if 0
++#define fiq_print _fiq_print
++#else
++#define fiq_print(x, y, ...)
++#endif
++
++extern bool fiq_enable, fiq_fsm_enable;
++extern ushort nak_holdoff;
++
++/**
++ * enum fiq_fsm_state - The FIQ FSM states.
++ *
++ * This is the "core" of the FIQ FSM. Broadly, the FSM states follow the
++ * USB2.0 specification for host responses to various transaction states.
++ * There are modifications to this host state machine because of a variety of
++ * quirks and limitations in the dwc_otg hardware.
++ *
++ * The fsm state is also used to communicate back to the driver on completion of
++ * a split transaction. The end states are used in conjunction with the interrupts
++ * raised by the final transaction.
++ */
++enum fiq_fsm_state {
++ /* FIQ isn't enabled for this host channel */
++ FIQ_PASSTHROUGH = 0,
++ /* For the first interrupt received for this channel,
++ * the FIQ has to ack any interrupts indicating success. */
++ FIQ_PASSTHROUGH_ERRORSTATE = 31,
++ /* Nonperiodic state groups */
++ FIQ_NP_SSPLIT_STARTED = 1,
++ FIQ_NP_SSPLIT_RETRY = 2,
++ FIQ_NP_OUT_CSPLIT_RETRY = 3,
++ FIQ_NP_IN_CSPLIT_RETRY = 4,
++ FIQ_NP_SPLIT_DONE = 5,
++ FIQ_NP_SPLIT_LS_ABORTED = 6,
++ /* This differentiates a HS transaction error from a LS one
++ * (handling the hub state is different) */
++ FIQ_NP_SPLIT_HS_ABORTED = 7,
++
++ /* Periodic state groups */
++ /* Periodic transactions are either started directly by the IRQ handler
++ * or deferred if the TT is already in use.
++ */
++ FIQ_PER_SSPLIT_QUEUED = 8,
++ FIQ_PER_SSPLIT_STARTED = 9,
++ FIQ_PER_SSPLIT_LAST = 10,
++
++
++ FIQ_PER_ISO_OUT_PENDING = 11,
++ FIQ_PER_ISO_OUT_ACTIVE = 12,
++ FIQ_PER_ISO_OUT_LAST = 13,
++ FIQ_PER_ISO_OUT_DONE = 27,
++
++ FIQ_PER_CSPLIT_WAIT = 14,
++ FIQ_PER_CSPLIT_NYET1 = 15,
++ FIQ_PER_CSPLIT_BROKEN_NYET1 = 28,
++ FIQ_PER_CSPLIT_NYET_FAFF = 29,
++ /* For multiple CSPLITs (large isoc IN, or delayed interrupt) */
++ FIQ_PER_CSPLIT_POLL = 16,
++ /* The last CSPLIT for a transaction has been issued, differentiates
++ * for the state machine to queue the next packet.
++ */
++ FIQ_PER_CSPLIT_LAST = 17,
++
++ FIQ_PER_SPLIT_DONE = 18,
++ FIQ_PER_SPLIT_LS_ABORTED = 19,
++ FIQ_PER_SPLIT_HS_ABORTED = 20,
++ FIQ_PER_SPLIT_NYET_ABORTED = 21,
++ /* Frame rollover has occurred without the transaction finishing. */
++ FIQ_PER_SPLIT_TIMEOUT = 22,
++
++ /* FIQ-accelerated HS Isochronous state groups */
++ FIQ_HS_ISOC_TURBO = 23,
++ /* For interval > 1, SOF wakes up the isochronous FSM */
++ FIQ_HS_ISOC_SLEEPING = 24,
++ FIQ_HS_ISOC_DONE = 25,
++ FIQ_HS_ISOC_ABORTED = 26,
++ FIQ_DEQUEUE_ISSUED = 30,
++ FIQ_TEST = 32,
++};
++
++struct fiq_stack {
++ int magic1;
++ uint8_t stack[2048];
++ int magic2;
++};
++
++
++/**
++ * struct fiq_dma_info - DMA bounce buffer utilisation information (per-channel)
++ * @index: Number of slots reported used for IN transactions / number of slots
++ * transmitted for an OUT transaction
++ * @slot_len[6]: Number of actual transfer bytes in each slot (255 if unused)
++ *
++ * Split transaction transfers can have variable length depending on other bus
++ * traffic. The OTG core DMA engine requires 4-byte aligned addresses therefore
++ * each transaction needs a guaranteed aligned address. A maximum of 6 split transfers
++ * can happen per-frame.
++ */
++struct fiq_dma_info {
++ u8 index;
++ u8 slot_len[6];
++};
++
++struct __attribute__((packed)) fiq_split_dma_slot {
++ u8 buf[188];
++};
++
++struct fiq_dma_channel {
++ struct __attribute__((packed)) fiq_split_dma_slot index[6];
++};
++
++struct fiq_dma_blob {
++ struct __attribute__((packed)) fiq_dma_channel channel[0];
++};
++
++/**
++ * struct fiq_hs_isoc_info - USB2.0 isochronous data
++ * @iso_frame: Pointer to the array of OTG URB iso_frame_descs.
++ * @nrframes: Total length of iso_frame_desc array
++ * @index: Current index (FIQ-maintained)
++ *
++ */
++struct fiq_hs_isoc_info {
++ struct dwc_otg_hcd_iso_packet_desc *iso_desc;
++ unsigned int nrframes;
++ unsigned int index;
++};
++
++/**
++ * struct fiq_channel_state - FIQ state machine storage
++ * @fsm: Current state of the channel as understood by the FIQ
++ * @nr_errors: Number of transaction errors on this split-transaction
++ * @hub_addr: SSPLIT/CSPLIT destination hub
++ * @port_addr: SSPLIT/CSPLIT destination port - always 1 if single TT hub
++ * @nrpackets: For isoc OUT, the number of split-OUT packets to transmit. For
++ * split-IN, number of CSPLIT data packets that were received.
++ * @hcchar_copy:
++ * @hcsplt_copy:
++ * @hcintmsk_copy:
++ * @hctsiz_copy: Copies of the host channel registers.
++ * For use as scratch, or for returning state.
++ *
++ * The fiq_channel_state is state storage between interrupts for a host channel. The
++ * FSM state is stored here. Members of this structure must only be set up by the
++ * driver prior to enabling the FIQ for this host channel, and not touched until the FIQ
++ * has updated the state to either a COMPLETE state group or ABORT state group.
++ */
++
++struct fiq_channel_state {
++ enum fiq_fsm_state fsm;
++ unsigned int nr_errors;
++ unsigned int hub_addr;
++ unsigned int port_addr;
++ /* Hardware bug workaround: sometimes channel halt interrupts are
++ * delayed until the next SOF. Keep track of when we expected to get interrupted. */
++ unsigned int expected_uframe;
++ /* in/out for communicating number of dma buffers used, or number of ISOC to do */
++ unsigned int nrpackets;
++ struct fiq_dma_info dma_info;
++ struct fiq_hs_isoc_info hs_isoc_info;
++ /* Copies of HC registers - in/out communication from/to IRQ handler
++ * and for ease of channel setup. A bit of mungeing is performed - for
++ * example the hctsiz.b.maxp is _always_ the max packet size of the endpoint.
++ */
++ hcchar_data_t hcchar_copy;
++ hcsplt_data_t hcsplt_copy;
++ hcint_data_t hcint_copy;
++ hcintmsk_data_t hcintmsk_copy;
++ hctsiz_data_t hctsiz_copy;
++ hcdma_data_t hcdma_copy;
++};
++
++/**
++ * struct fiq_state - top-level FIQ state machine storage
++ * @mphi_regs: virtual address of the MPHI peripheral register file
++ * @dwc_regs_base: virtual address of the base of the DWC core register file
++ * @dma_base: physical address for the base of the DMA bounce buffers
++ * @dummy_send: Scratch area for sending a fake message to the MPHI peripheral
++ * @gintmsk_saved: Top-level mask of interrupts that the FIQ has not handled.
++ * Used for determining which interrupts fired to set off the IRQ handler.
++ * @haintmsk_saved: Mask of interrupts from host channels that the FIQ did not handle internally.
++ * @np_count: Non-periodic transactions in the active queue
++ * @np_sent: Count of non-periodic transactions that have completed
++ * @next_sched_frame: For periodic transactions handled by the driver's SOF-driven queuing mechanism,
++ * this is the next frame on which a SOF interrupt is required. Used to hold off
++ * passing SOF through to the driver until necessary.
++ * @channel[n]: Per-channel FIQ state. Allocated during init depending on the number of host
++ * channels configured into the core logic.
++ *
++ * This is passed as the first argument to the dwc_otg_fiq_fsm top-level FIQ handler from the asm stub.
++ * It contains top-level state information.
++ */
++struct fiq_state {
++ fiq_lock_t lock;
++ mphi_regs_t mphi_regs;
++ void *dwc_regs_base;
++ dma_addr_t dma_base;
++ struct fiq_dma_blob *fiq_dmab;
++ void *dummy_send;
++ gintmsk_data_t gintmsk_saved;
++ haintmsk_data_t haintmsk_saved;
++ int mphi_int_count;
++ unsigned int fiq_done;
++ unsigned int kick_np_queues;
++ unsigned int next_sched_frame;
++#ifdef FIQ_DEBUG
++ char * buffer;
++ unsigned int bufsiz;
++#endif
++ struct fiq_channel_state channel[0];
++};
++
++extern void fiq_fsm_spin_lock(fiq_lock_t *lock);
++
++extern void fiq_fsm_spin_unlock(fiq_lock_t *lock);
++
++extern int fiq_fsm_too_late(struct fiq_state *st, int n);
++
++extern int fiq_fsm_tt_in_use(struct fiq_state *st, int num_channels, int n);
++
++extern void dwc_otg_fiq_fsm(struct fiq_state *state, int num_channels);
++
++extern void dwc_otg_fiq_nop(struct fiq_state *state);
++
++#endif /* DWC_OTG_FIQ_FSM_H_ */
+diff -Nur linux-4.1.3/drivers/usb/host/dwc_otg/dwc_otg_fiq_stub.S linux-xbian-rpi/drivers/usb/host/dwc_otg/dwc_otg_fiq_stub.S
+--- linux-4.1.3/drivers/usb/host/dwc_otg/dwc_otg_fiq_stub.S 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/usb/host/dwc_otg/dwc_otg_fiq_stub.S 2015-07-28 01:20:58.445156473 +0200
+@@ -0,0 +1,80 @@
++/*
++ * dwc_otg_fiq_fsm.S - assembly stub for the FSM FIQ
++ *
++ * Copyright (c) 2013 Raspberry Pi Foundation
++ *
++ * Author: Jonathan Bell <jonathan@raspberrypi.org>
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * * Neither the name of Raspberry Pi nor the
++ * names of its contributors may be used to endorse or promote products
++ * derived from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
++ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
++ * DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++
++#include <asm/assembler.h>
++#include <linux/linkage.h>
++
++
++.text
++
++.global _dwc_otg_fiq_stub_end;
++
++/**
++ * _dwc_otg_fiq_stub() - entry copied to the FIQ vector page to allow
++ * a C-style function call with arguments from the FIQ banked registers.
++ * r0 = &hcd->fiq_state
++ * r1 = &hcd->num_channels
++ * r2 = &hcd->dma_buffers
++ * Tramples: r0, r1, r2, r4, fp, ip
++ */
++
++ENTRY(_dwc_otg_fiq_stub)
++ /* Stash unbanked regs - SP will have been set up for us */
++ mov ip, sp;
++ stmdb sp!, {r0-r12, lr};
++#ifdef FIQ_DEBUG
++ // Cycle profiling - read cycle counter at start
++ mrc p15, 0, r5, c15, c12, 1;
++#endif
++ /* r11 = fp, don't trample it */
++ mov r4, fp;
++ /* set EABI frame size */
++ sub fp, ip, #512;
++
++ /* for fiq NOP mode - just need state */
++ mov r0, r8;
++ /* r9 = num_channels */
++ mov r1, r9;
++ /* r10 = struct *dma_bufs */
++// mov r2, r10;
++
++ /* r4 = &fiq_c_function */
++ blx r4;
++#ifdef FIQ_DEBUG
++ mrc p15, 0, r4, c15, c12, 1;
++ subs r5, r5, r4;
++ // r5 is now the cycle count time for executing the FIQ. Store it somewhere?
++#endif
++ ldmia sp!, {r0-r12, lr};
++ subs pc, lr, #4;
++_dwc_otg_fiq_stub_end:
++END(_dwc_otg_fiq_stub)
+diff -Nur linux-4.1.3/drivers/usb/host/dwc_otg/dwc_otg_hcd.c linux-xbian-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd.c
+--- linux-4.1.3/drivers/usb/host/dwc_otg/dwc_otg_hcd.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd.c 2015-07-28 01:20:58.449142252 +0200
+@@ -0,0 +1,4252 @@
++
++/* ==========================================================================
++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.c $
++ * $Revision: #104 $
++ * $Date: 2011/10/24 $
++ * $Change: 1871159 $
++ *
++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++ * otherwise expressly agreed to in writing between Synopsys and you.
++ *
++ * The Software IS NOT an item of Licensed Software or Licensed Product under
++ * any End User Software License Agreement or Agreement for Licensed Product
++ * with Synopsys or any supplement thereto. You are permitted to use and
++ * redistribute this Software in source and binary forms, with or without
++ * modification, provided that redistributions of source code must retain this
++ * notice. You may not view, use, disclose, copy or distribute this file or
++ * any information contained herein except pursuant to this license grant from
++ * Synopsys. If you do not agree with this notice, including the disclaimer
++ * below, then you are not authorized to use the Software.
++ *
++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++ * DAMAGE.
++ * ========================================================================== */
++#ifndef DWC_DEVICE_ONLY
++
++/** @file
++ * This file implements HCD Core. All code in this file is portable and doesn't
++ * use any OS specific functions.
++ * Interface provided by HCD Core is defined in <code><hcd_if.h></code>
++ * header file.
++ */
++
++#include <linux/usb.h>
++#include <linux/usb/hcd.h>
++
++#include "dwc_otg_hcd.h"
++#include "dwc_otg_regs.h"
++#include "dwc_otg_fiq_fsm.h"
++
++extern bool microframe_schedule;
++extern uint16_t fiq_fsm_mask, nak_holdoff;
++
++//#define DEBUG_HOST_CHANNELS
++#ifdef DEBUG_HOST_CHANNELS
++static int last_sel_trans_num_per_scheduled = 0;
++static int last_sel_trans_num_nonper_scheduled = 0;
++static int last_sel_trans_num_avail_hc_at_start = 0;
++static int last_sel_trans_num_avail_hc_at_end = 0;
++#endif /* DEBUG_HOST_CHANNELS */
++
++
++dwc_otg_hcd_t *dwc_otg_hcd_alloc_hcd(void)
++{
++ return DWC_ALLOC(sizeof(dwc_otg_hcd_t));
++}
++
++/**
++ * Connection timeout function. An OTG host is required to display a
++ * message if the device does not connect within 10 seconds.
++ */
++void dwc_otg_hcd_connect_timeout(void *ptr)
++{
++ DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, ptr);
++ DWC_PRINTF("Connect Timeout\n");
++ __DWC_ERROR("Device Not Connected/Responding\n");
++}
++
++#if defined(DEBUG)
++static void dump_channel_info(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
++{
++ if (qh->channel != NULL) {
++ dwc_hc_t *hc = qh->channel;
++ dwc_list_link_t *item;
++ dwc_otg_qh_t *qh_item;
++ int num_channels = hcd->core_if->core_params->host_channels;
++ int i;
++
++ dwc_otg_hc_regs_t *hc_regs;
++ hcchar_data_t hcchar;
++ hcsplt_data_t hcsplt;
++ hctsiz_data_t hctsiz;
++ uint32_t hcdma;
++
++ hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num];
++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
++ hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
++ hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
++ hcdma = DWC_READ_REG32(&hc_regs->hcdma);
++
++ DWC_PRINTF(" Assigned to channel %p:\n", hc);
++ DWC_PRINTF(" hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32,
++ hcsplt.d32);
++ DWC_PRINTF(" hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32,
++ hcdma);
++ DWC_PRINTF(" dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
++ hc->dev_addr, hc->ep_num, hc->ep_is_in);
++ DWC_PRINTF(" ep_type: %d\n", hc->ep_type);
++ DWC_PRINTF(" max_packet: %d\n", hc->max_packet);
++ DWC_PRINTF(" data_pid_start: %d\n", hc->data_pid_start);
++ DWC_PRINTF(" xfer_started: %d\n", hc->xfer_started);
++ DWC_PRINTF(" halt_status: %d\n", hc->halt_status);
++ DWC_PRINTF(" xfer_buff: %p\n", hc->xfer_buff);
++ DWC_PRINTF(" xfer_len: %d\n", hc->xfer_len);
++ DWC_PRINTF(" qh: %p\n", hc->qh);
++ DWC_PRINTF(" NP inactive sched:\n");
++ DWC_LIST_FOREACH(item, &hcd->non_periodic_sched_inactive) {
++ qh_item =
++ DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
++ DWC_PRINTF(" %p\n", qh_item);
++ }
++ DWC_PRINTF(" NP active sched:\n");
++ DWC_LIST_FOREACH(item, &hcd->non_periodic_sched_active) {
++ qh_item =
++ DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
++ DWC_PRINTF(" %p\n", qh_item);
++ }
++ DWC_PRINTF(" Channels: \n");
++ for (i = 0; i < num_channels; i++) {
++ dwc_hc_t *hc = hcd->hc_ptr_array[i];
++ DWC_PRINTF(" %2d: %p\n", i, hc);
++ }
++ }
++}
++#else
++#define dump_channel_info(hcd, qh)
++#endif /* DEBUG */
++
++/**
++ * Work queue function for starting the HCD when A-Cable is connected.
++ * The hcd_start() must be called in a process context.
++ */
++static void hcd_start_func(void *_vp)
++{
++ dwc_otg_hcd_t *hcd = (dwc_otg_hcd_t *) _vp;
++
++ DWC_DEBUGPL(DBG_HCDV, "%s() %p\n", __func__, hcd);
++ if (hcd) {
++ hcd->fops->start(hcd);
++ }
++}
++
++static void del_xfer_timers(dwc_otg_hcd_t * hcd)
++{
++#ifdef DEBUG
++ int i;
++ int num_channels = hcd->core_if->core_params->host_channels;
++ for (i = 0; i < num_channels; i++) {
++ DWC_TIMER_CANCEL(hcd->core_if->hc_xfer_timer[i]);
++ }
++#endif
++}
++
++static void del_timers(dwc_otg_hcd_t * hcd)
++{
++ del_xfer_timers(hcd);
++ DWC_TIMER_CANCEL(hcd->conn_timer);
++}
++
++/**
++ * Processes all the URBs in a single list of QHs. Completes them with
++ * -ESHUTDOWN and frees the QTD.
++ */
++static void kill_urbs_in_qh_list(dwc_otg_hcd_t * hcd, dwc_list_link_t * qh_list)
++{
++ dwc_list_link_t *qh_item, *qh_tmp;
++ dwc_otg_qh_t *qh;
++ dwc_otg_qtd_t *qtd, *qtd_tmp;
++
++ DWC_LIST_FOREACH_SAFE(qh_item, qh_tmp, qh_list) {
++ qh = DWC_LIST_ENTRY(qh_item, dwc_otg_qh_t, qh_list_entry);
++ DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp,
++ &qh->qtd_list, qtd_list_entry) {
++ qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
++ if (qtd->urb != NULL) {
++ hcd->fops->complete(hcd, qtd->urb->priv,
++ qtd->urb, -DWC_E_SHUTDOWN);
++ dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
++ }
++
++ }
++ if(qh->channel) {
++ /* Using hcchar.chen == 1 is not a reliable test.
++ * It is possible that the channel has already halted
++ * but not yet been through the IRQ handler.
++ */
++ dwc_otg_hc_halt(hcd->core_if, qh->channel,
++ DWC_OTG_HC_XFER_URB_DEQUEUE);
++ if(microframe_schedule)
++ hcd->available_host_channels++;
++ qh->channel = NULL;
++ }
++ dwc_otg_hcd_qh_remove(hcd, qh);
++ }
++}
++
++/**
++ * Responds with an error status of ESHUTDOWN to all URBs in the non-periodic
++ * and periodic schedules. The QTD associated with each URB is removed from
++ * the schedule and freed. This function may be called when a disconnect is
++ * detected or when the HCD is being stopped.
++ */
++static void kill_all_urbs(dwc_otg_hcd_t * hcd)
++{
++ kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_inactive);
++ kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_active);
++ kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_inactive);
++ kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_ready);
++ kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_assigned);
++ kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_queued);
++}
++
++/**
++ * Start the connection timer. An OTG host is required to display a
++ * message if the device does not connect within 10 seconds. The
++ * timer is deleted if a port connect interrupt occurs before the
++ * timer expires.
++ */
++static void dwc_otg_hcd_start_connect_timer(dwc_otg_hcd_t * hcd)
++{
++ DWC_TIMER_SCHEDULE(hcd->conn_timer, 10000 /* 10 secs */ );
++}
++
++/**
++ * HCD Callback function for disconnect of the HCD.
++ *
++ * @param p void pointer to the <code>struct usb_hcd</code>
++ */
++static int32_t dwc_otg_hcd_session_start_cb(void *p)
++{
++ dwc_otg_hcd_t *dwc_otg_hcd;
++ DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p);
++ dwc_otg_hcd = p;
++ dwc_otg_hcd_start_connect_timer(dwc_otg_hcd);
++ return 1;
++}
++
++/**
++ * HCD Callback function for starting the HCD when A-Cable is
++ * connected.
++ *
++ * @param p void pointer to the <code>struct usb_hcd</code>
++ */
++static int32_t dwc_otg_hcd_start_cb(void *p)
++{
++ dwc_otg_hcd_t *dwc_otg_hcd = p;
++ dwc_otg_core_if_t *core_if;
++ hprt0_data_t hprt0;
++
++ core_if = dwc_otg_hcd->core_if;
++
++ if (core_if->op_state == B_HOST) {
++ /*
++ * Reset the port. During a HNP mode switch the reset
++ * needs to occur within 1ms and have a duration of at
++ * least 50ms.
++ */
++ hprt0.d32 = dwc_otg_read_hprt0(core_if);
++ hprt0.b.prtrst = 1;
++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
++ }
++ DWC_WORKQ_SCHEDULE_DELAYED(core_if->wq_otg,
++ hcd_start_func, dwc_otg_hcd, 50,
++ "start hcd");
++
++ return 1;
++}
++
++/**
++ * HCD Callback function for disconnect of the HCD.
++ *
++ * @param p void pointer to the <code>struct usb_hcd</code>
++ */
++static int32_t dwc_otg_hcd_disconnect_cb(void *p)
++{
++ gintsts_data_t intr;
++ dwc_otg_hcd_t *dwc_otg_hcd = p;
++
++ /*
++ * Set status flags for the hub driver.
++ */
++ dwc_otg_hcd->flags.b.port_connect_status_change = 1;
++ dwc_otg_hcd->flags.b.port_connect_status = 0;
++ if(fiq_enable)
++ local_fiq_disable();
++ /*
++ * Shutdown any transfers in process by clearing the Tx FIFO Empty
++ * interrupt mask and status bits and disabling subsequent host
++ * channel interrupts.
++ */
++ intr.d32 = 0;
++ intr.b.nptxfempty = 1;
++ intr.b.ptxfempty = 1;
++ intr.b.hcintr = 1;
++ DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk,
++ intr.d32, 0);
++ DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintsts,
++ intr.d32, 0);
++
++ del_timers(dwc_otg_hcd);
++
++ /*
++ * Turn off the vbus power only if the core has transitioned to device
++ * mode. If still in host mode, need to keep power on to detect a
++ * reconnection.
++ */
++ if (dwc_otg_is_device_mode(dwc_otg_hcd->core_if)) {
++ if (dwc_otg_hcd->core_if->op_state != A_SUSPEND) {
++ hprt0_data_t hprt0 = {.d32 = 0 };
++ DWC_PRINTF("Disconnect: PortPower off\n");
++ hprt0.b.prtpwr = 0;
++ DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0,
++ hprt0.d32);
++ }
++
++ dwc_otg_disable_host_interrupts(dwc_otg_hcd->core_if);
++ }
++
++ /* Respond with an error status to all URBs in the schedule. */
++ kill_all_urbs(dwc_otg_hcd);
++
++ if (dwc_otg_is_host_mode(dwc_otg_hcd->core_if)) {
++ /* Clean up any host channels that were in use. */
++ int num_channels;
++ int i;
++ dwc_hc_t *channel;
++ dwc_otg_hc_regs_t *hc_regs;
++ hcchar_data_t hcchar;
++
++ num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
++
++ if (!dwc_otg_hcd->core_if->dma_enable) {
++ /* Flush out any channel requests in slave mode. */
++ for (i = 0; i < num_channels; i++) {
++ channel = dwc_otg_hcd->hc_ptr_array[i];
++ if (DWC_CIRCLEQ_EMPTY_ENTRY
++ (channel, hc_list_entry)) {
++ hc_regs =
++ dwc_otg_hcd->core_if->
++ host_if->hc_regs[i];
++ hcchar.d32 =
++ DWC_READ_REG32(&hc_regs->hcchar);
++ if (hcchar.b.chen) {
++ hcchar.b.chen = 0;
++ hcchar.b.chdis = 1;
++ hcchar.b.epdir = 0;
++ DWC_WRITE_REG32
++ (&hc_regs->hcchar,
++ hcchar.d32);
++ }
++ }
++ }
++ }
++
++ for (i = 0; i < num_channels; i++) {
++ channel = dwc_otg_hcd->hc_ptr_array[i];
++ if (DWC_CIRCLEQ_EMPTY_ENTRY(channel, hc_list_entry)) {
++ hc_regs =
++ dwc_otg_hcd->core_if->host_if->hc_regs[i];
++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
++ if (hcchar.b.chen) {
++ /* Halt the channel. */
++ hcchar.b.chdis = 1;
++ DWC_WRITE_REG32(&hc_regs->hcchar,
++ hcchar.d32);
++ }
++
++ dwc_otg_hc_cleanup(dwc_otg_hcd->core_if,
++ channel);
++ DWC_CIRCLEQ_INSERT_TAIL
++ (&dwc_otg_hcd->free_hc_list, channel,
++ hc_list_entry);
++ /*
++ * Added for Descriptor DMA to prevent channel double cleanup
++ * in release_channel_ddma(). Which called from ep_disable
++ * when device disconnect.
++ */
++ channel->qh = NULL;
++ }
++ }
++ if(fiq_fsm_enable) {
++ for(i=0; i < 128; i++) {
++ dwc_otg_hcd->hub_port[i] = 0;
++ }
++ }
++
++ }
++
++ if(fiq_enable)
++ local_fiq_enable();
++
++ if (dwc_otg_hcd->fops->disconnect) {
++ dwc_otg_hcd->fops->disconnect(dwc_otg_hcd);
++ }
++
++ return 1;
++}
++
++/**
++ * HCD Callback function for stopping the HCD.
++ *
++ * @param p void pointer to the <code>struct usb_hcd</code>
++ */
++static int32_t dwc_otg_hcd_stop_cb(void *p)
++{
++ dwc_otg_hcd_t *dwc_otg_hcd = p;
++
++ DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p);
++ dwc_otg_hcd_stop(dwc_otg_hcd);
++ return 1;
++}
++
++#ifdef CONFIG_USB_DWC_OTG_LPM
++/**
++ * HCD Callback function for sleep of HCD.
++ *
++ * @param p void pointer to the <code>struct usb_hcd</code>
++ */
++static int dwc_otg_hcd_sleep_cb(void *p)
++{
++ dwc_otg_hcd_t *hcd = p;
++
++ dwc_otg_hcd_free_hc_from_lpm(hcd);
++
++ return 0;
++}
++#endif
++
++
++/**
++ * HCD Callback function for Remote Wakeup.
++ *
++ * @param p void pointer to the <code>struct usb_hcd</code>
++ */
++static int dwc_otg_hcd_rem_wakeup_cb(void *p)
++{
++ dwc_otg_hcd_t *hcd = p;
++
++ if (hcd->core_if->lx_state == DWC_OTG_L2) {
++ hcd->flags.b.port_suspend_change = 1;
++ }
++#ifdef CONFIG_USB_DWC_OTG_LPM
++ else {
++ hcd->flags.b.port_l1_change = 1;
++ }
++#endif
++ return 0;
++}
++
++/**
++ * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
++ * stopped.
++ */
++void dwc_otg_hcd_stop(dwc_otg_hcd_t * hcd)
++{
++ hprt0_data_t hprt0 = {.d32 = 0 };
++
++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD STOP\n");
++
++ /*
++ * The root hub should be disconnected before this function is called.
++ * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
++ * and the QH lists (via ..._hcd_endpoint_disable).
++ */
++
++ /* Turn off all host-specific interrupts. */
++ dwc_otg_disable_host_interrupts(hcd->core_if);
++
++ /* Turn off the vbus power */
++ DWC_PRINTF("PortPower off\n");
++ hprt0.b.prtpwr = 0;
++ DWC_WRITE_REG32(hcd->core_if->host_if->hprt0, hprt0.d32);
++ dwc_mdelay(1);
++}
++
++int dwc_otg_hcd_urb_enqueue(dwc_otg_hcd_t * hcd,
++ dwc_otg_hcd_urb_t * dwc_otg_urb, void **ep_handle,
++ int atomic_alloc)
++{
++ int retval = 0;
++ uint8_t needs_scheduling = 0;
++ dwc_otg_transaction_type_e tr_type;
++ dwc_otg_qtd_t *qtd;
++ gintmsk_data_t intr_mask = {.d32 = 0 };
++ hprt0_data_t hprt0 = { .d32 = 0 };
++
++#ifdef DEBUG /* integrity checks (Broadcom) */
++ if (NULL == hcd->core_if) {
++ DWC_ERROR("**** DWC OTG HCD URB Enqueue - HCD has NULL core_if\n");
++ /* No longer connected. */
++ return -DWC_E_INVALID;
++ }
++#endif
++ if (!hcd->flags.b.port_connect_status) {
++ /* No longer connected. */
++ DWC_ERROR("Not connected\n");
++ return -DWC_E_NO_DEVICE;
++ }
++
++ /* Some core configurations cannot support LS traffic on a FS root port */
++ if ((hcd->fops->speed(hcd, dwc_otg_urb->priv) == USB_SPEED_LOW) &&
++ (hcd->core_if->hwcfg2.b.fs_phy_type == 1) &&
++ (hcd->core_if->hwcfg2.b.hs_phy_type == 1)) {
++ hprt0.d32 = DWC_READ_REG32(hcd->core_if->host_if->hprt0);
++ if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_FULL_SPEED) {
++ return -DWC_E_NO_DEVICE;
++ }
++ }
++
++ qtd = dwc_otg_hcd_qtd_create(dwc_otg_urb, atomic_alloc);
++ if (qtd == NULL) {
++ DWC_ERROR("DWC OTG HCD URB Enqueue failed creating QTD\n");
++ return -DWC_E_NO_MEMORY;
++ }
++#ifdef DEBUG /* integrity checks (Broadcom) */
++ if (qtd->urb == NULL) {
++ DWC_ERROR("**** DWC OTG HCD URB Enqueue created QTD with no URBs\n");
++ return -DWC_E_NO_MEMORY;
++ }
++ if (qtd->urb->priv == NULL) {
++ DWC_ERROR("**** DWC OTG HCD URB Enqueue created QTD URB with no URB handle\n");
++ return -DWC_E_NO_MEMORY;
++ }
++#endif
++ intr_mask.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->gintmsk);
++ if(!intr_mask.b.sofintr || fiq_enable) needs_scheduling = 1;
++ if((((dwc_otg_qh_t *)ep_handle)->ep_type == UE_BULK) && !(qtd->urb->flags & URB_GIVEBACK_ASAP))
++ /* Do not schedule SG transactions until qtd has URB_GIVEBACK_ASAP set */
++ needs_scheduling = 0;
++
++ retval = dwc_otg_hcd_qtd_add(qtd, hcd, (dwc_otg_qh_t **) ep_handle, atomic_alloc);
++ // creates a new queue in ep_handle if it doesn't exist already
++ if (retval < 0) {
++ DWC_ERROR("DWC OTG HCD URB Enqueue failed adding QTD. "
++ "Error status %d\n", retval);
++ dwc_otg_hcd_qtd_free(qtd);
++ return retval;
++ }
++
++ if(needs_scheduling) {
++ tr_type = dwc_otg_hcd_select_transactions(hcd);
++ if (tr_type != DWC_OTG_TRANSACTION_NONE) {
++ dwc_otg_hcd_queue_transactions(hcd, tr_type);
++ }
++ }
++ return retval;
++}
++
++int dwc_otg_hcd_urb_dequeue(dwc_otg_hcd_t * hcd,
++ dwc_otg_hcd_urb_t * dwc_otg_urb)
++{
++ dwc_otg_qh_t *qh;
++ dwc_otg_qtd_t *urb_qtd;
++ BUG_ON(!hcd);
++ BUG_ON(!dwc_otg_urb);
++
++#ifdef DEBUG /* integrity checks (Broadcom) */
++
++ if (hcd == NULL) {
++ DWC_ERROR("**** DWC OTG HCD URB Dequeue has NULL HCD\n");
++ return -DWC_E_INVALID;
++ }
++ if (dwc_otg_urb == NULL) {
++ DWC_ERROR("**** DWC OTG HCD URB Dequeue has NULL URB\n");
++ return -DWC_E_INVALID;
++ }
++ if (dwc_otg_urb->qtd == NULL) {
++ DWC_ERROR("**** DWC OTG HCD URB Dequeue with NULL QTD\n");
++ return -DWC_E_INVALID;
++ }
++ urb_qtd = dwc_otg_urb->qtd;
++ BUG_ON(!urb_qtd);
++ if (urb_qtd->qh == NULL) {
++ DWC_ERROR("**** DWC OTG HCD URB Dequeue with QTD with NULL Q handler\n");
++ return -DWC_E_INVALID;
++ }
++#else
++ urb_qtd = dwc_otg_urb->qtd;
++ BUG_ON(!urb_qtd);
++#endif
++ qh = urb_qtd->qh;
++ BUG_ON(!qh);
++ if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
++ if (urb_qtd->in_process) {
++ dump_channel_info(hcd, qh);
++ }
++ }
++#ifdef DEBUG /* integrity checks (Broadcom) */
++ if (hcd->core_if == NULL) {
++ DWC_ERROR("**** DWC OTG HCD URB Dequeue HCD has NULL core_if\n");
++ return -DWC_E_INVALID;
++ }
++#endif
++ if (urb_qtd->in_process && qh->channel) {
++ /* The QTD is in process (it has been assigned to a channel). */
++ if (hcd->flags.b.port_connect_status) {
++ int n = qh->channel->hc_num;
++ /*
++ * If still connected (i.e. in host mode), halt the
++ * channel so it can be used for other transfers. If
++ * no longer connected, the host registers can't be
++ * written to halt the channel since the core is in
++ * device mode.
++ */
++ /* In FIQ FSM mode, we need to shut down carefully.
++ * The FIQ may attempt to restart a disabled channel */
++ if (fiq_fsm_enable && (hcd->fiq_state->channel[n].fsm != FIQ_PASSTHROUGH)) {
++ qh->channel->halt_status = DWC_OTG_HC_XFER_URB_DEQUEUE;
++ qh->channel->halt_pending = 1;
++ hcd->fiq_state->channel[n].fsm = FIQ_DEQUEUE_ISSUED;
++ } else {
++ dwc_otg_hc_halt(hcd->core_if, qh->channel,
++ DWC_OTG_HC_XFER_URB_DEQUEUE);
++ }
++ }
++ }
++
++ /*
++ * Free the QTD and clean up the associated QH. Leave the QH in the
++ * schedule if it has any remaining QTDs.
++ */
++
++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue - "
++ "delete %sQueue handler\n",
++ hcd->core_if->dma_desc_enable?"DMA ":"");
++ if (!hcd->core_if->dma_desc_enable) {
++ uint8_t b = urb_qtd->in_process;
++ dwc_otg_hcd_qtd_remove_and_free(hcd, urb_qtd, qh);
++ if (b) {
++ dwc_otg_hcd_qh_deactivate(hcd, qh, 0);
++ qh->channel = NULL;
++ } else if (DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
++ dwc_otg_hcd_qh_remove(hcd, qh);
++ }
++ } else {
++ dwc_otg_hcd_qtd_remove_and_free(hcd, urb_qtd, qh);
++ }
++ return 0;
++}
++
++int dwc_otg_hcd_endpoint_disable(dwc_otg_hcd_t * hcd, void *ep_handle,
++ int retry)
++{
++ dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
++ int retval = 0;
++ dwc_irqflags_t flags;
++
++ if (retry < 0) {
++ retval = -DWC_E_INVALID;
++ goto done;
++ }
++
++ if (!qh) {
++ retval = -DWC_E_INVALID;
++ goto done;
++ }
++
++ DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
++
++ while (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list) && retry) {
++ DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
++ retry--;
++ dwc_msleep(5);
++ DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
++ }
++
++ dwc_otg_hcd_qh_remove(hcd, qh);
++
++ DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
++ /*
++ * Split dwc_otg_hcd_qh_remove_and_free() into qh_remove
++ * and qh_free to prevent stack dump on DWC_DMA_FREE() with
++ * irq_disabled (spinlock_irqsave) in dwc_otg_hcd_desc_list_free()
++ * and dwc_otg_hcd_frame_list_alloc().
++ */
++ dwc_otg_hcd_qh_free(hcd, qh);
++
++done:
++ return retval;
++}
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30)
++int dwc_otg_hcd_endpoint_reset(dwc_otg_hcd_t * hcd, void *ep_handle)
++{
++ int retval = 0;
++ dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
++ if (!qh)
++ return -DWC_E_INVALID;
++
++ qh->data_toggle = DWC_OTG_HC_PID_DATA0;
++ return retval;
++}
++#endif
++
++/**
++ * HCD Callback structure for handling mode switching.
++ */
++static dwc_otg_cil_callbacks_t hcd_cil_callbacks = {
++ .start = dwc_otg_hcd_start_cb,
++ .stop = dwc_otg_hcd_stop_cb,
++ .disconnect = dwc_otg_hcd_disconnect_cb,
++ .session_start = dwc_otg_hcd_session_start_cb,
++ .resume_wakeup = dwc_otg_hcd_rem_wakeup_cb,
++#ifdef CONFIG_USB_DWC_OTG_LPM
++ .sleep = dwc_otg_hcd_sleep_cb,
++#endif
++ .p = 0,
++};
++
++/**
++ * Reset tasklet function
++ */
++static void reset_tasklet_func(void *data)
++{
++ dwc_otg_hcd_t *dwc_otg_hcd = (dwc_otg_hcd_t *) data;
++ dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
++ hprt0_data_t hprt0;
++
++ DWC_DEBUGPL(DBG_HCDV, "USB RESET tasklet called\n");
++
++ hprt0.d32 = dwc_otg_read_hprt0(core_if);
++ hprt0.b.prtrst = 1;
++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
++ dwc_mdelay(60);
++
++ hprt0.b.prtrst = 0;
++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
++ dwc_otg_hcd->flags.b.port_reset_change = 1;
++}
++
++static void completion_tasklet_func(void *ptr)
++{
++ dwc_otg_hcd_t *hcd = (dwc_otg_hcd_t *) ptr;
++ struct urb *urb;
++ urb_tq_entry_t *item;
++ dwc_irqflags_t flags;
++
++ /* This could just be spin_lock_irq */
++ DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
++ while (!DWC_TAILQ_EMPTY(&hcd->completed_urb_list)) {
++ item = DWC_TAILQ_FIRST(&hcd->completed_urb_list);
++ urb = item->urb;
++ DWC_TAILQ_REMOVE(&hcd->completed_urb_list, item,
++ urb_tq_entries);
++ DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
++ DWC_FREE(item);
++
++ usb_hcd_giveback_urb(hcd->priv, urb, urb->status);
++
++
++ DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
++ }
++ DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
++ return;
++}
++
++static void qh_list_free(dwc_otg_hcd_t * hcd, dwc_list_link_t * qh_list)
++{
++ dwc_list_link_t *item;
++ dwc_otg_qh_t *qh;
++ dwc_irqflags_t flags;
++
++ if (!qh_list->next) {
++ /* The list hasn't been initialized yet. */
++ return;
++ }
++ /*
++ * Hold spinlock here. Not needed in that case if bellow
++ * function is being called from ISR
++ */
++ DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
++ /* Ensure there are no QTDs or URBs left. */
++ kill_urbs_in_qh_list(hcd, qh_list);
++ DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
++
++ DWC_LIST_FOREACH(item, qh_list) {
++ qh = DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
++ dwc_otg_hcd_qh_remove_and_free(hcd, qh);
++ }
++}
++
++/**
++ * Exit from Hibernation if Host did not detect SRP from connected SRP capable
++ * Device during SRP time by host power up.
++ */
++void dwc_otg_hcd_power_up(void *ptr)
++{
++ gpwrdn_data_t gpwrdn = {.d32 = 0 };
++ dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr;
++
++ DWC_PRINTF("%s called\n", __FUNCTION__);
++
++ if (!core_if->hibernation_suspend) {
++ DWC_PRINTF("Already exited from Hibernation\n");
++ return;
++ }
++
++ /* Switch on the voltage to the core */
++ gpwrdn.b.pwrdnswtch = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++ dwc_udelay(10);
++
++ /* Reset the core */
++ gpwrdn.d32 = 0;
++ gpwrdn.b.pwrdnrstn = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++ dwc_udelay(10);
++
++ /* Disable power clamps */
++ gpwrdn.d32 = 0;
++ gpwrdn.b.pwrdnclmp = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++
++ /* Remove reset the core signal */
++ gpwrdn.d32 = 0;
++ gpwrdn.b.pwrdnrstn = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
++ dwc_udelay(10);
++
++ /* Disable PMU interrupt */
++ gpwrdn.d32 = 0;
++ gpwrdn.b.pmuintsel = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++
++ core_if->hibernation_suspend = 0;
++
++ /* Disable PMU */
++ gpwrdn.d32 = 0;
++ gpwrdn.b.pmuactv = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++ dwc_udelay(10);
++
++ /* Enable VBUS */
++ gpwrdn.d32 = 0;
++ gpwrdn.b.dis_vbus = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++
++ core_if->op_state = A_HOST;
++ dwc_otg_core_init(core_if);
++ dwc_otg_enable_global_interrupts(core_if);
++ cil_hcd_start(core_if);
++}
++
++void dwc_otg_cleanup_fiq_channel(dwc_otg_hcd_t *hcd, uint32_t num)
++{
++ struct fiq_channel_state *st = &hcd->fiq_state->channel[num];
++ struct fiq_dma_blob *blob = hcd->fiq_dmab;
++ int i;
++
++ st->fsm = FIQ_PASSTHROUGH;
++ st->hcchar_copy.d32 = 0;
++ st->hcsplt_copy.d32 = 0;
++ st->hcint_copy.d32 = 0;
++ st->hcintmsk_copy.d32 = 0;
++ st->hctsiz_copy.d32 = 0;
++ st->hcdma_copy.d32 = 0;
++ st->nr_errors = 0;
++ st->hub_addr = 0;
++ st->port_addr = 0;
++ st->expected_uframe = 0;
++ st->nrpackets = 0;
++ st->dma_info.index = 0;
++ for (i = 0; i < 6; i++)
++ st->dma_info.slot_len[i] = 255;
++ st->hs_isoc_info.index = 0;
++ st->hs_isoc_info.iso_desc = NULL;
++ st->hs_isoc_info.nrframes = 0;
++
++ DWC_MEMSET(&blob->channel[num].index[0], 0x6b, 1128);
++}
++
++/**
++ * Frees secondary storage associated with the dwc_otg_hcd structure contained
++ * in the struct usb_hcd field.
++ */
++static void dwc_otg_hcd_free(dwc_otg_hcd_t * dwc_otg_hcd)
++{
++ int i;
++
++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD FREE\n");
++
++ del_timers(dwc_otg_hcd);
++
++ /* Free memory for QH/QTD lists */
++ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_inactive);
++ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_active);
++ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_inactive);
++ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_ready);
++ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_assigned);
++ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_queued);
++
++ /* Free memory for the host channels. */
++ for (i = 0; i < MAX_EPS_CHANNELS; i++) {
++ dwc_hc_t *hc = dwc_otg_hcd->hc_ptr_array[i];
++
++#ifdef DEBUG
++ if (dwc_otg_hcd->core_if->hc_xfer_timer[i]) {
++ DWC_TIMER_FREE(dwc_otg_hcd->core_if->hc_xfer_timer[i]);
++ }
++#endif
++ if (hc != NULL) {
++ DWC_DEBUGPL(DBG_HCDV, "HCD Free channel #%i, hc=%p\n",
++ i, hc);
++ DWC_FREE(hc);
++ }
++ }
++
++ if (dwc_otg_hcd->core_if->dma_enable) {
++ if (dwc_otg_hcd->status_buf_dma) {
++ DWC_DMA_FREE(DWC_OTG_HCD_STATUS_BUF_SIZE,
++ dwc_otg_hcd->status_buf,
++ dwc_otg_hcd->status_buf_dma);
++ }
++ } else if (dwc_otg_hcd->status_buf != NULL) {
++ DWC_FREE(dwc_otg_hcd->status_buf);
++ }
++ DWC_SPINLOCK_FREE(dwc_otg_hcd->channel_lock);
++ DWC_SPINLOCK_FREE(dwc_otg_hcd->lock);
++ /* Set core_if's lock pointer to NULL */
++ dwc_otg_hcd->core_if->lock = NULL;
++
++ DWC_TIMER_FREE(dwc_otg_hcd->conn_timer);
++ DWC_TASK_FREE(dwc_otg_hcd->reset_tasklet);
++ DWC_TASK_FREE(dwc_otg_hcd->completion_tasklet);
++ DWC_FREE(dwc_otg_hcd->fiq_state);
++
++#ifdef DWC_DEV_SRPCAP
++ if (dwc_otg_hcd->core_if->power_down == 2 &&
++ dwc_otg_hcd->core_if->pwron_timer) {
++ DWC_TIMER_FREE(dwc_otg_hcd->core_if->pwron_timer);
++ }
++#endif
++ DWC_FREE(dwc_otg_hcd);
++}
++
++int init_hcd_usecs(dwc_otg_hcd_t *_hcd);
++
++int dwc_otg_hcd_init(dwc_otg_hcd_t * hcd, dwc_otg_core_if_t * core_if)
++{
++ int retval = 0;
++ int num_channels;
++ int i;
++ dwc_hc_t *channel;
++
++#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_SPINLOCK))
++ DWC_SPINLOCK_ALLOC_LINUX_DEBUG(hcd->lock);
++ DWC_SPINLOCK_ALLOC_LINUX_DEBUG(hcd->channel_lock);
++#else
++ hcd->lock = DWC_SPINLOCK_ALLOC();
++ hcd->channel_lock = DWC_SPINLOCK_ALLOC();
++#endif
++ DWC_DEBUGPL(DBG_HCDV, "init of HCD %p given core_if %p\n",
++ hcd, core_if);
++ if (!hcd->lock) {
++ DWC_ERROR("Could not allocate lock for pcd");
++ DWC_FREE(hcd);
++ retval = -DWC_E_NO_MEMORY;
++ goto out;
++ }
++ hcd->core_if = core_if;
++
++ /* Register the HCD CIL Callbacks */
++ dwc_otg_cil_register_hcd_callbacks(hcd->core_if,
++ &hcd_cil_callbacks, hcd);
++
++ /* Initialize the non-periodic schedule. */
++ DWC_LIST_INIT(&hcd->non_periodic_sched_inactive);
++ DWC_LIST_INIT(&hcd->non_periodic_sched_active);
++
++ /* Initialize the periodic schedule. */
++ DWC_LIST_INIT(&hcd->periodic_sched_inactive);
++ DWC_LIST_INIT(&hcd->periodic_sched_ready);
++ DWC_LIST_INIT(&hcd->periodic_sched_assigned);
++ DWC_LIST_INIT(&hcd->periodic_sched_queued);
++ DWC_TAILQ_INIT(&hcd->completed_urb_list);
++ /*
++ * Create a host channel descriptor for each host channel implemented
++ * in the controller. Initialize the channel descriptor array.
++ */
++ DWC_CIRCLEQ_INIT(&hcd->free_hc_list);
++ num_channels = hcd->core_if->core_params->host_channels;
++ DWC_MEMSET(hcd->hc_ptr_array, 0, sizeof(hcd->hc_ptr_array));
++ for (i = 0; i < num_channels; i++) {
++ channel = DWC_ALLOC(sizeof(dwc_hc_t));
++ if (channel == NULL) {
++ retval = -DWC_E_NO_MEMORY;
++ DWC_ERROR("%s: host channel allocation failed\n",
++ __func__);
++ dwc_otg_hcd_free(hcd);
++ goto out;
++ }
++ channel->hc_num = i;
++ hcd->hc_ptr_array[i] = channel;
++#ifdef DEBUG
++ hcd->core_if->hc_xfer_timer[i] =
++ DWC_TIMER_ALLOC("hc timer", hc_xfer_timeout,
++ &hcd->core_if->hc_xfer_info[i]);
++#endif
++ DWC_DEBUGPL(DBG_HCDV, "HCD Added channel #%d, hc=%p\n", i,
++ channel);
++ }
++
++ if (fiq_enable) {
++ hcd->fiq_state = DWC_ALLOC(sizeof(struct fiq_state) + (sizeof(struct fiq_channel_state) * num_channels));
++ if (!hcd->fiq_state) {
++ retval = -DWC_E_NO_MEMORY;
++ DWC_ERROR("%s: cannot allocate fiq_state structure\n", __func__);
++ dwc_otg_hcd_free(hcd);
++ goto out;
++ }
++ DWC_MEMSET(hcd->fiq_state, 0, (sizeof(struct fiq_state) + (sizeof(struct fiq_channel_state) * num_channels)));
++
++ for (i = 0; i < num_channels; i++) {
++ hcd->fiq_state->channel[i].fsm = FIQ_PASSTHROUGH;
++ }
++ hcd->fiq_state->dummy_send = DWC_ALLOC_ATOMIC(16);
++
++ hcd->fiq_stack = DWC_ALLOC(sizeof(struct fiq_stack));
++ if (!hcd->fiq_stack) {
++ retval = -DWC_E_NO_MEMORY;
++ DWC_ERROR("%s: cannot allocate fiq_stack structure\n", __func__);
++ dwc_otg_hcd_free(hcd);
++ goto out;
++ }
++ hcd->fiq_stack->magic1 = 0xDEADBEEF;
++ hcd->fiq_stack->magic2 = 0xD00DFEED;
++ hcd->fiq_state->gintmsk_saved.d32 = ~0;
++ hcd->fiq_state->haintmsk_saved.b2.chint = ~0;
++
++ /* This bit is terrible and uses no API, but necessary. The FIQ has no concept of DMA pools
++ * (and if it did, would be a lot slower). This allocates a chunk of memory (~9kiB for 8 host channels)
++ * for use as transaction bounce buffers in a 2-D array. Our access into this chunk is done by some
++ * moderately readable array casts.
++ */
++ hcd->fiq_dmab = DWC_DMA_ALLOC((sizeof(struct fiq_dma_channel) * num_channels), &hcd->fiq_state->dma_base);
++ DWC_WARN("FIQ DMA bounce buffers: virt = 0x%08x dma = 0x%08x len=%d",
++ (unsigned int)hcd->fiq_dmab, (unsigned int)hcd->fiq_state->dma_base,
++ sizeof(struct fiq_dma_channel) * num_channels);
++
++ DWC_MEMSET(hcd->fiq_dmab, 0x6b, 9024);
++
++ /* pointer for debug in fiq_print */
++ hcd->fiq_state->fiq_dmab = hcd->fiq_dmab;
++ if (fiq_fsm_enable) {
++ int i;
++ for (i=0; i < hcd->core_if->core_params->host_channels; i++) {
++ dwc_otg_cleanup_fiq_channel(hcd, i);
++ }
++ DWC_PRINTF("FIQ FSM acceleration enabled for :\n%s%s%s%s",
++ (fiq_fsm_mask & 0x1) ? "Non-periodic Split Transactions\n" : "",
++ (fiq_fsm_mask & 0x2) ? "Periodic Split Transactions\n" : "",
++ (fiq_fsm_mask & 0x4) ? "High-Speed Isochronous Endpoints\n" : "",
++ (fiq_fsm_mask & 0x8) ? "Interrupt/Control Split Transaction hack enabled\n" : "");
++ }
++ }
++
++ /* Initialize the Connection timeout timer. */
++ hcd->conn_timer = DWC_TIMER_ALLOC("Connection timer",
++ dwc_otg_hcd_connect_timeout, 0);
++
++ printk(KERN_DEBUG "dwc_otg: Microframe scheduler %s\n", microframe_schedule ? "enabled":"disabled");
++ if (microframe_schedule)
++ init_hcd_usecs(hcd);
++
++ /* Initialize reset tasklet. */
++ hcd->reset_tasklet = DWC_TASK_ALLOC("reset_tasklet", reset_tasklet_func, hcd);
++
++ hcd->completion_tasklet = DWC_TASK_ALLOC("completion_tasklet",
++ completion_tasklet_func, hcd);
++#ifdef DWC_DEV_SRPCAP
++ if (hcd->core_if->power_down == 2) {
++ /* Initialize Power on timer for Host power up in case hibernation */
++ hcd->core_if->pwron_timer = DWC_TIMER_ALLOC("PWRON TIMER",
++ dwc_otg_hcd_power_up, core_if);
++ }
++#endif
++
++ /*
++ * Allocate space for storing data on status transactions. Normally no
++ * data is sent, but this space acts as a bit bucket. This must be
++ * done after usb_add_hcd since that function allocates the DMA buffer
++ * pool.
++ */
++ if (hcd->core_if->dma_enable) {
++ hcd->status_buf =
++ DWC_DMA_ALLOC(DWC_OTG_HCD_STATUS_BUF_SIZE,
++ &hcd->status_buf_dma);
++ } else {
++ hcd->status_buf = DWC_ALLOC(DWC_OTG_HCD_STATUS_BUF_SIZE);
++ }
++ if (!hcd->status_buf) {
++ retval = -DWC_E_NO_MEMORY;
++ DWC_ERROR("%s: status_buf allocation failed\n", __func__);
++ dwc_otg_hcd_free(hcd);
++ goto out;
++ }
++
++ hcd->otg_port = 1;
++ hcd->frame_list = NULL;
++ hcd->frame_list_dma = 0;
++ hcd->periodic_qh_count = 0;
++
++ DWC_MEMSET(hcd->hub_port, 0, sizeof(hcd->hub_port));
++#ifdef FIQ_DEBUG
++ DWC_MEMSET(hcd->hub_port_alloc, -1, sizeof(hcd->hub_port_alloc));
++#endif
++
++out:
++ return retval;
++}
++
++void dwc_otg_hcd_remove(dwc_otg_hcd_t * hcd)
++{
++ /* Turn off all host-specific interrupts. */
++ dwc_otg_disable_host_interrupts(hcd->core_if);
++
++ dwc_otg_hcd_free(hcd);
++}
++
++/**
++ * Initializes dynamic portions of the DWC_otg HCD state.
++ */
++static void dwc_otg_hcd_reinit(dwc_otg_hcd_t * hcd)
++{
++ int num_channels;
++ int i;
++ dwc_hc_t *channel;
++ dwc_hc_t *channel_tmp;
++
++ hcd->flags.d32 = 0;
++
++ hcd->non_periodic_qh_ptr = &hcd->non_periodic_sched_active;
++ if (!microframe_schedule) {
++ hcd->non_periodic_channels = 0;
++ hcd->periodic_channels = 0;
++ } else {
++ hcd->available_host_channels = hcd->core_if->core_params->host_channels;
++ }
++ /*
++ * Put all channels in the free channel list and clean up channel
++ * states.
++ */
++ DWC_CIRCLEQ_FOREACH_SAFE(channel, channel_tmp,
++ &hcd->free_hc_list, hc_list_entry) {
++ DWC_CIRCLEQ_REMOVE(&hcd->free_hc_list, channel, hc_list_entry);
++ }
++
++ num_channels = hcd->core_if->core_params->host_channels;
++ for (i = 0; i < num_channels; i++) {
++ channel = hcd->hc_ptr_array[i];
++ DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, channel,
++ hc_list_entry);
++ dwc_otg_hc_cleanup(hcd->core_if, channel);
++ }
++
++ /* Initialize the DWC core for host mode operation. */
++ dwc_otg_core_host_init(hcd->core_if);
++
++ /* Set core_if's lock pointer to the hcd->lock */
++ hcd->core_if->lock = hcd->lock;
++}
++
++/**
++ * Assigns transactions from a QTD to a free host channel and initializes the
++ * host channel to perform the transactions. The host channel is removed from
++ * the free list.
++ *
++ * @param hcd The HCD state structure.
++ * @param qh Transactions from the first QTD for this QH are selected and
++ * assigned to a free host channel.
++ */
++static void assign_and_init_hc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
++{
++ dwc_hc_t *hc;
++ dwc_otg_qtd_t *qtd;
++ dwc_otg_hcd_urb_t *urb;
++ void* ptr = NULL;
++ uint32_t intr_enable;
++ unsigned long flags;
++ gintmsk_data_t gintmsk = { .d32 = 0, };
++
++ qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
++
++ urb = qtd->urb;
++
++ DWC_DEBUGPL(DBG_HCDV, "%s(%p,%p) - urb %x, actual_length %d\n", __func__, hcd, qh, (unsigned int)urb, urb->actual_length);
++
++ if (((urb->actual_length < 0) || (urb->actual_length > urb->length)) && !dwc_otg_hcd_is_pipe_in(&urb->pipe_info))
++ urb->actual_length = urb->length;
++
++
++ hc = DWC_CIRCLEQ_FIRST(&hcd->free_hc_list);
++
++ /* Remove the host channel from the free list. */
++ DWC_CIRCLEQ_REMOVE_INIT(&hcd->free_hc_list, hc, hc_list_entry);
++
++ qh->channel = hc;
++
++ qtd->in_process = 1;
++
++ /*
++ * Use usb_pipedevice to determine device address. This address is
++ * 0 before the SET_ADDRESS command and the correct address afterward.
++ */
++ hc->dev_addr = dwc_otg_hcd_get_dev_addr(&urb->pipe_info);
++ hc->ep_num = dwc_otg_hcd_get_ep_num(&urb->pipe_info);
++ hc->speed = qh->dev_speed;
++ hc->max_packet = dwc_max_packet(qh->maxp);
++
++ hc->xfer_started = 0;
++ hc->halt_status = DWC_OTG_HC_XFER_NO_HALT_STATUS;
++ hc->error_state = (qtd->error_count > 0);
++ hc->halt_on_queue = 0;
++ hc->halt_pending = 0;
++ hc->requests = 0;
++
++ /*
++ * The following values may be modified in the transfer type section
++ * below. The xfer_len value may be reduced when the transfer is
++ * started to accommodate the max widths of the XferSize and PktCnt
++ * fields in the HCTSIZn register.
++ */
++
++ hc->ep_is_in = (dwc_otg_hcd_is_pipe_in(&urb->pipe_info) != 0);
++ if (hc->ep_is_in) {
++ hc->do_ping = 0;
++ } else {
++ hc->do_ping = qh->ping_state;
++ }
++
++ hc->data_pid_start = qh->data_toggle;
++ hc->multi_count = 1;
++
++ if (hcd->core_if->dma_enable) {
++ hc->xfer_buff = (uint8_t *) urb->dma + urb->actual_length;
++
++ /* For non-dword aligned case */
++ if (((unsigned long)hc->xfer_buff & 0x3)
++ && !hcd->core_if->dma_desc_enable) {
++ ptr = (uint8_t *) urb->buf + urb->actual_length;
++ }
++ } else {
++ hc->xfer_buff = (uint8_t *) urb->buf + urb->actual_length;
++ }
++ hc->xfer_len = urb->length - urb->actual_length;
++ hc->xfer_count = 0;
++
++ /*
++ * Set the split attributes
++ */
++ hc->do_split = 0;
++ if (qh->do_split) {
++ uint32_t hub_addr, port_addr;
++ hc->do_split = 1;
++ hc->xact_pos = qtd->isoc_split_pos;
++ /* We don't need to do complete splits anymore */
++// if(fiq_fsm_enable)
++ if (0)
++ hc->complete_split = qtd->complete_split = 0;
++ else
++ hc->complete_split = qtd->complete_split;
++
++ hcd->fops->hub_info(hcd, urb->priv, &hub_addr, &port_addr);
++ hc->hub_addr = (uint8_t) hub_addr;
++ hc->port_addr = (uint8_t) port_addr;
++ }
++
++ switch (dwc_otg_hcd_get_pipe_type(&urb->pipe_info)) {
++ case UE_CONTROL:
++ hc->ep_type = DWC_OTG_EP_TYPE_CONTROL;
++ switch (qtd->control_phase) {
++ case DWC_OTG_CONTROL_SETUP:
++ DWC_DEBUGPL(DBG_HCDV, " Control setup transaction\n");
++ hc->do_ping = 0;
++ hc->ep_is_in = 0;
++ hc->data_pid_start = DWC_OTG_HC_PID_SETUP;
++ if (hcd->core_if->dma_enable) {
++ hc->xfer_buff = (uint8_t *) urb->setup_dma;
++ } else {
++ hc->xfer_buff = (uint8_t *) urb->setup_packet;
++ }
++ hc->xfer_len = 8;
++ ptr = NULL;
++ break;
++ case DWC_OTG_CONTROL_DATA:
++ DWC_DEBUGPL(DBG_HCDV, " Control data transaction\n");
++ hc->data_pid_start = qtd->data_toggle;
++ break;
++ case DWC_OTG_CONTROL_STATUS:
++ /*
++ * Direction is opposite of data direction or IN if no
++ * data.
++ */
++ DWC_DEBUGPL(DBG_HCDV, " Control status transaction\n");
++ if (urb->length == 0) {
++ hc->ep_is_in = 1;
++ } else {
++ hc->ep_is_in =
++ dwc_otg_hcd_is_pipe_out(&urb->pipe_info);
++ }
++ if (hc->ep_is_in) {
++ hc->do_ping = 0;
++ }
++
++ hc->data_pid_start = DWC_OTG_HC_PID_DATA1;
++
++ hc->xfer_len = 0;
++ if (hcd->core_if->dma_enable) {
++ hc->xfer_buff = (uint8_t *) hcd->status_buf_dma;
++ } else {
++ hc->xfer_buff = (uint8_t *) hcd->status_buf;
++ }
++ ptr = NULL;
++ break;
++ }
++ break;
++ case UE_BULK:
++ hc->ep_type = DWC_OTG_EP_TYPE_BULK;
++ break;
++ case UE_INTERRUPT:
++ hc->ep_type = DWC_OTG_EP_TYPE_INTR;
++ break;
++ case UE_ISOCHRONOUS:
++ {
++ struct dwc_otg_hcd_iso_packet_desc *frame_desc;
++
++ hc->ep_type = DWC_OTG_EP_TYPE_ISOC;
++
++ if (hcd->core_if->dma_desc_enable)
++ break;
++
++ frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
++
++ frame_desc->status = 0;
++
++ if (hcd->core_if->dma_enable) {
++ hc->xfer_buff = (uint8_t *) urb->dma;
++ } else {
++ hc->xfer_buff = (uint8_t *) urb->buf;
++ }
++ hc->xfer_buff +=
++ frame_desc->offset + qtd->isoc_split_offset;
++ hc->xfer_len =
++ frame_desc->length - qtd->isoc_split_offset;
++
++ /* For non-dword aligned buffers */
++ if (((unsigned long)hc->xfer_buff & 0x3)
++ && hcd->core_if->dma_enable) {
++ ptr =
++ (uint8_t *) urb->buf + frame_desc->offset +
++ qtd->isoc_split_offset;
++ } else
++ ptr = NULL;
++
++ if (hc->xact_pos == DWC_HCSPLIT_XACTPOS_ALL) {
++ if (hc->xfer_len <= 188) {
++ hc->xact_pos = DWC_HCSPLIT_XACTPOS_ALL;
++ } else {
++ hc->xact_pos =
++ DWC_HCSPLIT_XACTPOS_BEGIN;
++ }
++ }
++ }
++ break;
++ }
++ /* non DWORD-aligned buffer case */
++ if (ptr) {
++ uint32_t buf_size;
++ if (hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
++ buf_size = hcd->core_if->core_params->max_transfer_size;
++ } else {
++ buf_size = 4096;
++ }
++ if (!qh->dw_align_buf) {
++ qh->dw_align_buf = DWC_DMA_ALLOC_ATOMIC(buf_size,
++ &qh->dw_align_buf_dma);
++ if (!qh->dw_align_buf) {
++ DWC_ERROR
++ ("%s: Failed to allocate memory to handle "
++ "non-dword aligned buffer case\n",
++ __func__);
++ return;
++ }
++ }
++ if (!hc->ep_is_in) {
++ dwc_memcpy(qh->dw_align_buf, ptr, hc->xfer_len);
++ }
++ hc->align_buff = qh->dw_align_buf_dma;
++ } else {
++ hc->align_buff = 0;
++ }
++
++ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
++ hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
++ /*
++ * This value may be modified when the transfer is started to
++ * reflect the actual transfer length.
++ */
++ hc->multi_count = dwc_hb_mult(qh->maxp);
++ }
++
++ if (hcd->core_if->dma_desc_enable)
++ hc->desc_list_addr = qh->desc_list_dma;
++
++ dwc_otg_hc_init(hcd->core_if, hc);
++
++ local_irq_save(flags);
++
++ if (fiq_enable) {
++ local_fiq_disable();
++ fiq_fsm_spin_lock(&hcd->fiq_state->lock);
++ }
++
++ /* Enable the top level host channel interrupt. */
++ intr_enable = (1 << hc->hc_num);
++ DWC_MODIFY_REG32(&hcd->core_if->host_if->host_global_regs->haintmsk, 0, intr_enable);
++
++ /* Make sure host channel interrupts are enabled. */
++ gintmsk.b.hcintr = 1;
++ DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, 0, gintmsk.d32);
++
++ if (fiq_enable) {
++ fiq_fsm_spin_unlock(&hcd->fiq_state->lock);
++ local_fiq_enable();
++ }
++
++ local_irq_restore(flags);
++ hc->qh = qh;
++}
++
++
++/**
++ * fiq_fsm_transaction_suitable() - Test a QH for compatibility with the FIQ
++ * @qh: pointer to the endpoint's queue head
++ *
++ * Transaction start/end control flow is grafted onto the existing dwc_otg
++ * mechanisms, to avoid spaghettifying the functions more than they already are.
++ * This function's eligibility check is altered by debug parameter.
++ *
++ * Returns: 0 for unsuitable, 1 implies the FIQ can be enabled for this transaction.
++ */
++
++int fiq_fsm_transaction_suitable(dwc_otg_qh_t *qh)
++{
++ if (qh->do_split) {
++ switch (qh->ep_type) {
++ case UE_CONTROL:
++ case UE_BULK:
++ if (fiq_fsm_mask & (1 << 0))
++ return 1;
++ break;
++ case UE_INTERRUPT:
++ case UE_ISOCHRONOUS:
++ if (fiq_fsm_mask & (1 << 1))
++ return 1;
++ break;
++ default:
++ break;
++ }
++ } else if (qh->ep_type == UE_ISOCHRONOUS) {
++ if (fiq_fsm_mask & (1 << 2)) {
++ /* HS ISOCH support. We test for compatibility:
++ * - DWORD aligned buffers
++ * - Must be at least 2 transfers (otherwise pointless to use the FIQ)
++ * If yes, then the fsm enqueue function will handle the state machine setup.
++ */
++ dwc_otg_qtd_t *qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
++ dwc_otg_hcd_urb_t *urb = qtd->urb;
++ struct dwc_otg_hcd_iso_packet_desc (*iso_descs)[0] = &urb->iso_descs;
++ int nr_iso_frames = urb->packet_count;
++ int i;
++ uint32_t ptr;
++
++ if (nr_iso_frames < 2)
++ return 0;
++ for (i = 0; i < nr_iso_frames; i++) {
++ ptr = urb->dma + iso_descs[i]->offset;
++ if (ptr & 0x3) {
++ printk_ratelimited("%s: Non-Dword aligned isochronous frame offset."
++ " Cannot queue FIQ-accelerated transfer to device %d endpoint %d\n",
++ __FUNCTION__, qh->channel->dev_addr, qh->channel->ep_num);
++ return 0;
++ }
++ }
++ return 1;
++ }
++ }
++ return 0;
++}
++
++/**
++ * fiq_fsm_setup_periodic_dma() - Set up DMA bounce buffers
++ * @hcd: Pointer to the dwc_otg_hcd struct
++ * @qh: Pointer to the endpoint's queue head
++ *
++ * Periodic split transactions are transmitted modulo 188 bytes.
++ * This necessitates slicing data up into buckets for isochronous out
++ * and fixing up the DMA address for all IN transfers.
++ *
++ * Returns 1 if the DMA bounce buffers have been used, 0 if the default
++ * HC buffer has been used.
++ */
++int fiq_fsm_setup_periodic_dma(dwc_otg_hcd_t *hcd, struct fiq_channel_state *st, dwc_otg_qh_t *qh)
++ {
++ int frame_length, i = 0;
++ uint8_t *ptr = NULL;
++ dwc_hc_t *hc = qh->channel;
++ struct fiq_dma_blob *blob;
++ struct dwc_otg_hcd_iso_packet_desc *frame_desc;
++
++ for (i = 0; i < 6; i++) {
++ st->dma_info.slot_len[i] = 255;
++ }
++ st->dma_info.index = 0;
++ i = 0;
++ if (hc->ep_is_in) {
++ /*
++ * Set dma_regs to bounce buffer. FIQ will update the
++ * state depending on transaction progress.
++ */
++ blob = (struct fiq_dma_blob *) hcd->fiq_state->dma_base;
++ st->hcdma_copy.d32 = (uint32_t) &blob->channel[hc->hc_num].index[0].buf[0];
++ /* Calculate the max number of CSPLITS such that the FIQ can time out
++ * a transaction if it fails.
++ */
++ frame_length = st->hcchar_copy.b.mps;
++ do {
++ i++;
++ frame_length -= 188;
++ } while (frame_length >= 0);
++ st->nrpackets = i;
++ return 1;
++ } else {
++ if (qh->ep_type == UE_ISOCHRONOUS) {
++
++ dwc_otg_qtd_t *qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
++
++ frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
++ frame_length = frame_desc->length;
++
++ /* Virtual address for bounce buffers */
++ blob = hcd->fiq_dmab;
++
++ ptr = qtd->urb->buf + frame_desc->offset;
++ if (frame_length == 0) {
++ /*
++ * for isochronous transactions, we must still transmit a packet
++ * even if the length is zero.
++ */
++ st->dma_info.slot_len[0] = 0;
++ st->nrpackets = 1;
++ } else {
++ do {
++ if (frame_length <= 188) {
++ dwc_memcpy(&blob->channel[hc->hc_num].index[i].buf[0], ptr, frame_length);
++ st->dma_info.slot_len[i] = frame_length;
++ ptr += frame_length;
++ } else {
++ dwc_memcpy(&blob->channel[hc->hc_num].index[i].buf[0], ptr, 188);
++ st->dma_info.slot_len[i] = 188;
++ ptr += 188;
++ }
++ i++;
++ frame_length -= 188;
++ } while (frame_length > 0);
++ st->nrpackets = i;
++ }
++ ptr = qtd->urb->buf + frame_desc->offset;
++ /* Point the HC at the DMA address of the bounce buffers */
++ blob = (struct fiq_dma_blob *) hcd->fiq_state->dma_base;
++ st->hcdma_copy.d32 = (uint32_t) &blob->channel[hc->hc_num].index[0].buf[0];
++
++ /* fixup xfersize to the actual packet size */
++ st->hctsiz_copy.b.pid = 0;
++ st->hctsiz_copy.b.xfersize = st->dma_info.slot_len[0];
++ return 1;
++ } else {
++ /* For interrupt, single OUT packet required, goes in the SSPLIT from hc_buff. */
++ return 0;
++ }
++ }
++}
++
++/*
++ * Pushing a periodic request into the queue near the EOF1 point
++ * in a microframe causes erroneous behaviour (frmovrun) interrupt.
++ * Usually, the request goes out on the bus causing a transfer but
++ * the core does not transfer the data to memory.
++ * This guard interval (in number of 60MHz clocks) is required which
++ * must cater for CPU latency between reading the value and enabling
++ * the channel.
++ */
++#define PERIODIC_FRREM_BACKOFF 1000
++
++int fiq_fsm_queue_isoc_transaction(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
++{
++ dwc_hc_t *hc = qh->channel;
++ dwc_otg_hc_regs_t *hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num];
++ dwc_otg_qtd_t *qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
++ int frame;
++ struct fiq_channel_state *st = &hcd->fiq_state->channel[hc->hc_num];
++ int xfer_len, nrpackets;
++ hcdma_data_t hcdma;
++ hfnum_data_t hfnum;
++
++ if (st->fsm != FIQ_PASSTHROUGH)
++ return 0;
++
++ st->nr_errors = 0;
++
++ st->hcchar_copy.d32 = 0;
++ st->hcchar_copy.b.mps = hc->max_packet;
++ st->hcchar_copy.b.epdir = hc->ep_is_in;
++ st->hcchar_copy.b.devaddr = hc->dev_addr;
++ st->hcchar_copy.b.epnum = hc->ep_num;
++ st->hcchar_copy.b.eptype = hc->ep_type;
++
++ st->hcintmsk_copy.b.chhltd = 1;
++
++ frame = dwc_otg_hcd_get_frame_number(hcd);
++ st->hcchar_copy.b.oddfrm = (frame & 0x1) ? 0 : 1;
++
++ st->hcchar_copy.b.lspddev = 0;
++ /* Enable the channel later as a final register write. */
++
++ st->hcsplt_copy.d32 = 0;
++
++ st->hs_isoc_info.iso_desc = (struct dwc_otg_hcd_iso_packet_desc *) &qtd->urb->iso_descs;
++ st->hs_isoc_info.nrframes = qtd->urb->packet_count;
++ /* grab the next DMA address offset from the array */
++ st->hcdma_copy.d32 = qtd->urb->dma;
++ hcdma.d32 = st->hcdma_copy.d32 + st->hs_isoc_info.iso_desc[0].offset;
++
++ /* We need to set multi_count. This is a bit tricky - has to be set per-transaction as
++ * the core needs to be told to send the correct number. Caution: for IN transfers,
++ * this is always set to the maximum size of the endpoint. */
++ xfer_len = st->hs_isoc_info.iso_desc[0].length;
++ nrpackets = (xfer_len + st->hcchar_copy.b.mps - 1) / st->hcchar_copy.b.mps;
++ if (nrpackets == 0)
++ nrpackets = 1;
++ st->hcchar_copy.b.multicnt = nrpackets;
++ st->hctsiz_copy.b.pktcnt = nrpackets;
++
++ /* Initial PID also needs to be set */
++ if (st->hcchar_copy.b.epdir == 0) {
++ st->hctsiz_copy.b.xfersize = xfer_len;
++ switch (st->hcchar_copy.b.multicnt) {
++ case 1:
++ st->hctsiz_copy.b.pid = DWC_PID_DATA0;
++ break;
++ case 2:
++ case 3:
++ st->hctsiz_copy.b.pid = DWC_PID_MDATA;
++ break;
++ }
++
++ } else {
++ st->hctsiz_copy.b.xfersize = nrpackets * st->hcchar_copy.b.mps;
++ switch (st->hcchar_copy.b.multicnt) {
++ case 1:
++ st->hctsiz_copy.b.pid = DWC_PID_DATA0;
++ break;
++ case 2:
++ st->hctsiz_copy.b.pid = DWC_PID_DATA1;
++ break;
++ case 3:
++ st->hctsiz_copy.b.pid = DWC_PID_DATA2;
++ break;
++ }
++ }
++
++ fiq_print(FIQDBG_INT, hcd->fiq_state, "FSMQ %01d ", hc->hc_num);
++ fiq_print(FIQDBG_INT, hcd->fiq_state, "%08x", st->hcchar_copy.d32);
++ fiq_print(FIQDBG_INT, hcd->fiq_state, "%08x", st->hctsiz_copy.d32);
++ fiq_print(FIQDBG_INT, hcd->fiq_state, "%08x", st->hcdma_copy.d32);
++ hfnum.d32 = DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hfnum);
++ local_fiq_disable();
++ fiq_fsm_spin_lock(&hcd->fiq_state->lock);
++ DWC_WRITE_REG32(&hc_regs->hctsiz, st->hctsiz_copy.d32);
++ DWC_WRITE_REG32(&hc_regs->hcsplt, st->hcsplt_copy.d32);
++ DWC_WRITE_REG32(&hc_regs->hcdma, st->hcdma_copy.d32);
++ DWC_WRITE_REG32(&hc_regs->hcchar, st->hcchar_copy.d32);
++ DWC_WRITE_REG32(&hc_regs->hcintmsk, st->hcintmsk_copy.d32);
++ if (hfnum.b.frrem < PERIODIC_FRREM_BACKOFF) {
++ /* Prevent queueing near EOF1. Bad things happen if a periodic
++ * split transaction is queued very close to EOF.
++ */
++ st->fsm = FIQ_HS_ISOC_SLEEPING;
++ } else {
++ st->fsm = FIQ_HS_ISOC_TURBO;
++ st->hcchar_copy.b.chen = 1;
++ DWC_WRITE_REG32(&hc_regs->hcchar, st->hcchar_copy.d32);
++ }
++ mb();
++ st->hcchar_copy.b.chen = 0;
++ fiq_fsm_spin_unlock(&hcd->fiq_state->lock);
++ local_fiq_enable();
++ return 0;
++}
++
++
++/**
++ * fiq_fsm_queue_split_transaction() - Set up a host channel and FIQ state
++ * @hcd: Pointer to the dwc_otg_hcd struct
++ * @qh: Pointer to the endpoint's queue head
++ *
++ * This overrides the dwc_otg driver's normal method of queueing a transaction.
++ * Called from dwc_otg_hcd_queue_transactions(), this performs specific setup
++ * for the nominated host channel.
++ *
++ * For periodic transfers, it also peeks at the FIQ state to see if an immediate
++ * start is possible. If not, then the FIQ is left to start the transfer.
++ */
++int fiq_fsm_queue_split_transaction(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
++{
++ int start_immediate = 1, i;
++ hfnum_data_t hfnum;
++ dwc_hc_t *hc = qh->channel;
++ dwc_otg_hc_regs_t *hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num];
++ /* Program HC registers, setup FIQ_state, examine FIQ if periodic, start transfer (not if uframe 5) */
++ int hub_addr, port_addr, frame, uframe;
++ struct fiq_channel_state *st = &hcd->fiq_state->channel[hc->hc_num];
++
++ if (st->fsm != FIQ_PASSTHROUGH)
++ return 0;
++ st->nr_errors = 0;
++
++ st->hcchar_copy.d32 = 0;
++ st->hcchar_copy.b.mps = hc->max_packet;
++ st->hcchar_copy.b.epdir = hc->ep_is_in;
++ st->hcchar_copy.b.devaddr = hc->dev_addr;
++ st->hcchar_copy.b.epnum = hc->ep_num;
++ st->hcchar_copy.b.eptype = hc->ep_type;
++ if (hc->ep_type & 0x1) {
++ if (hc->ep_is_in)
++ st->hcchar_copy.b.multicnt = 3;
++ else
++ /* Docs say set this to 1, but driver sets to 0! */
++ st->hcchar_copy.b.multicnt = 0;
++ } else {
++ st->hcchar_copy.b.multicnt = 1;
++ st->hcchar_copy.b.oddfrm = 0;
++ }
++ st->hcchar_copy.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW) ? 1 : 0;
++ /* Enable the channel later as a final register write. */
++
++ st->hcsplt_copy.d32 = 0;
++ if(qh->do_split) {
++ hcd->fops->hub_info(hcd, DWC_CIRCLEQ_FIRST(&qh->qtd_list)->urb->priv, &hub_addr, &port_addr);
++ st->hcsplt_copy.b.compsplt = 0;
++ st->hcsplt_copy.b.spltena = 1;
++ // XACTPOS is for isoc-out only but needs initialising anyway.
++ st->hcsplt_copy.b.xactpos = ISOC_XACTPOS_ALL;
++ if((qh->ep_type == DWC_OTG_EP_TYPE_ISOC) && (!qh->ep_is_in)) {
++ /* For packetsize 0 < L < 188, ISOC_XACTPOS_ALL.
++ * for longer than this, ISOC_XACTPOS_BEGIN and the FIQ
++ * will update as necessary.
++ */
++ if (hc->xfer_len > 188) {
++ st->hcsplt_copy.b.xactpos = ISOC_XACTPOS_BEGIN;
++ }
++ }
++ st->hcsplt_copy.b.hubaddr = (uint8_t) hub_addr;
++ st->hcsplt_copy.b.prtaddr = (uint8_t) port_addr;
++ st->hub_addr = hub_addr;
++ st->port_addr = port_addr;
++ }
++
++ st->hctsiz_copy.d32 = 0;
++ st->hctsiz_copy.b.dopng = 0;
++ st->hctsiz_copy.b.pid = hc->data_pid_start;
++
++ if (hc->ep_is_in || (hc->xfer_len > hc->max_packet)) {
++ hc->xfer_len = hc->max_packet;
++ } else if (!hc->ep_is_in && (hc->xfer_len > 188)) {
++ hc->xfer_len = 188;
++ }
++ st->hctsiz_copy.b.xfersize = hc->xfer_len;
++
++ st->hctsiz_copy.b.pktcnt = 1;
++
++ if (hc->ep_type & 0x1) {
++ /*
++ * For potentially multi-packet transfers, must use the DMA bounce buffers. For IN transfers,
++ * the DMA address is the address of the first 188byte slot buffer in the bounce buffer array.
++ * For multi-packet OUT transfers, we need to copy the data into the bounce buffer array so the FIQ can punt
++ * the right address out as necessary. hc->xfer_buff and hc->xfer_len have already been set
++ * in assign_and_init_hc(), but this is for the eventual transaction completion only. The FIQ
++ * must not touch internal driver state.
++ */
++ if(!fiq_fsm_setup_periodic_dma(hcd, st, qh)) {
++ if (hc->align_buff) {
++ st->hcdma_copy.d32 = hc->align_buff;
++ } else {
++ st->hcdma_copy.d32 = ((unsigned long) hc->xfer_buff & 0xFFFFFFFF);
++ }
++ }
++ } else {
++ if (hc->align_buff) {
++ st->hcdma_copy.d32 = hc->align_buff;
++ } else {
++ st->hcdma_copy.d32 = ((unsigned long) hc->xfer_buff & 0xFFFFFFFF);
++ }
++ }
++ /* The FIQ depends upon no other interrupts being enabled except channel halt.
++ * Fixup channel interrupt mask. */
++ st->hcintmsk_copy.d32 = 0;
++ st->hcintmsk_copy.b.chhltd = 1;
++ st->hcintmsk_copy.b.ahberr = 1;
++
++ /* Hack courtesy of FreeBSD: apparently forcing Interrupt Split transactions
++ * as Control puts the transfer into the non-periodic request queue and the
++ * non-periodic handler in the hub. Makes things lots easier.
++ */
++ if ((fiq_fsm_mask & 0x8) && hc->ep_type == UE_INTERRUPT) {
++ st->hcchar_copy.b.multicnt = 0;
++ st->hcchar_copy.b.oddfrm = 0;
++ st->hcchar_copy.b.eptype = UE_CONTROL;
++ if (hc->align_buff) {
++ st->hcdma_copy.d32 = hc->align_buff;
++ } else {
++ st->hcdma_copy.d32 = ((unsigned long) hc->xfer_buff & 0xFFFFFFFF);
++ }
++ }
++ DWC_WRITE_REG32(&hc_regs->hcdma, st->hcdma_copy.d32);
++ DWC_WRITE_REG32(&hc_regs->hctsiz, st->hctsiz_copy.d32);
++ DWC_WRITE_REG32(&hc_regs->hcsplt, st->hcsplt_copy.d32);
++ DWC_WRITE_REG32(&hc_regs->hcchar, st->hcchar_copy.d32);
++ DWC_WRITE_REG32(&hc_regs->hcintmsk, st->hcintmsk_copy.d32);
++
++ local_fiq_disable();
++ fiq_fsm_spin_lock(&hcd->fiq_state->lock);
++
++ if (hc->ep_type & 0x1) {
++ hfnum.d32 = DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hfnum);
++ frame = (hfnum.b.frnum & ~0x7) >> 3;
++ uframe = hfnum.b.frnum & 0x7;
++ if (hfnum.b.frrem < PERIODIC_FRREM_BACKOFF) {
++ /* Prevent queueing near EOF1. Bad things happen if a periodic
++ * split transaction is queued very close to EOF.
++ */
++ start_immediate = 0;
++ } else if (uframe == 5) {
++ start_immediate = 0;
++ } else if (hc->ep_type == UE_ISOCHRONOUS && !hc->ep_is_in) {
++ start_immediate = 0;
++ } else if (hc->ep_is_in && fiq_fsm_too_late(hcd->fiq_state, hc->hc_num)) {
++ start_immediate = 0;
++ } else {
++ /* Search through all host channels to determine if a transaction
++ * is currently in progress */
++ for (i = 0; i < hcd->core_if->core_params->host_channels; i++) {
++ if (i == hc->hc_num || hcd->fiq_state->channel[i].fsm == FIQ_PASSTHROUGH)
++ continue;
++ switch (hcd->fiq_state->channel[i].fsm) {
++ /* TT is reserved for channels that are in the middle of a periodic
++ * split transaction.
++ */
++ case FIQ_PER_SSPLIT_STARTED:
++ case FIQ_PER_CSPLIT_WAIT:
++ case FIQ_PER_CSPLIT_NYET1:
++ case FIQ_PER_CSPLIT_POLL:
++ case FIQ_PER_ISO_OUT_ACTIVE:
++ case FIQ_PER_ISO_OUT_LAST:
++ if (hcd->fiq_state->channel[i].hub_addr == hub_addr &&
++ hcd->fiq_state->channel[i].port_addr == port_addr) {
++ start_immediate = 0;
++ }
++ break;
++ default:
++ break;
++ }
++ if (!start_immediate)
++ break;
++ }
++ }
++ }
++ if ((fiq_fsm_mask & 0x8) && hc->ep_type == UE_INTERRUPT)
++ start_immediate = 1;
++
++ fiq_print(FIQDBG_INT, hcd->fiq_state, "FSMQ %01d %01d", hc->hc_num, start_immediate);
++ fiq_print(FIQDBG_INT, hcd->fiq_state, "%08d", hfnum.b.frrem);
++ //fiq_print(FIQDBG_INT, hcd->fiq_state, "H:%02dP:%02d", hub_addr, port_addr);
++ //fiq_print(FIQDBG_INT, hcd->fiq_state, "%08x", st->hctsiz_copy.d32);
++ //fiq_print(FIQDBG_INT, hcd->fiq_state, "%08x", st->hcdma_copy.d32);
++ switch (hc->ep_type) {
++ case UE_CONTROL:
++ case UE_BULK:
++ st->fsm = FIQ_NP_SSPLIT_STARTED;
++ break;
++ case UE_ISOCHRONOUS:
++ if (hc->ep_is_in) {
++ if (start_immediate) {
++ st->fsm = FIQ_PER_SSPLIT_STARTED;
++ } else {
++ st->fsm = FIQ_PER_SSPLIT_QUEUED;
++ }
++ } else {
++ if (start_immediate) {
++ /* Single-isoc OUT packets don't require FIQ involvement */
++ if (st->nrpackets == 1) {
++ st->fsm = FIQ_PER_ISO_OUT_LAST;
++ } else {
++ st->fsm = FIQ_PER_ISO_OUT_ACTIVE;
++ }
++ } else {
++ st->fsm = FIQ_PER_ISO_OUT_PENDING;
++ }
++ }
++ break;
++ case UE_INTERRUPT:
++ if (fiq_fsm_mask & 0x8) {
++ st->fsm = FIQ_NP_SSPLIT_STARTED;
++ } else if (start_immediate) {
++ st->fsm = FIQ_PER_SSPLIT_STARTED;
++ } else {
++ st->fsm = FIQ_PER_SSPLIT_QUEUED;
++ }
++ default:
++ break;
++ }
++ if (start_immediate) {
++ /* Set the oddfrm bit as close as possible to actual queueing */
++ frame = dwc_otg_hcd_get_frame_number(hcd);
++ st->expected_uframe = (frame + 1) & 0x3FFF;
++ st->hcchar_copy.b.oddfrm = (frame & 0x1) ? 0 : 1;
++ st->hcchar_copy.b.chen = 1;
++ DWC_WRITE_REG32(&hc_regs->hcchar, st->hcchar_copy.d32);
++ }
++ mb();
++ fiq_fsm_spin_unlock(&hcd->fiq_state->lock);
++ local_fiq_enable();
++ return 0;
++}
++
++
++/**
++ * This function selects transactions from the HCD transfer schedule and
++ * assigns them to available host channels. It is called from HCD interrupt
++ * handler functions.
++ *
++ * @param hcd The HCD state structure.
++ *
++ * @return The types of new transactions that were assigned to host channels.
++ */
++dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t * hcd)
++{
++ dwc_list_link_t *qh_ptr;
++ dwc_otg_qh_t *qh;
++ int num_channels;
++ dwc_irqflags_t flags;
++ dwc_spinlock_t *channel_lock = hcd->channel_lock;
++ dwc_otg_transaction_type_e ret_val = DWC_OTG_TRANSACTION_NONE;
++
++#ifdef DEBUG_HOST_CHANNELS
++ last_sel_trans_num_per_scheduled = 0;
++ last_sel_trans_num_nonper_scheduled = 0;
++ last_sel_trans_num_avail_hc_at_start = hcd->available_host_channels;
++#endif /* DEBUG_HOST_CHANNELS */
++
++ /* Process entries in the periodic ready list. */
++ qh_ptr = DWC_LIST_FIRST(&hcd->periodic_sched_ready);
++
++ while (qh_ptr != &hcd->periodic_sched_ready &&
++ !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
++
++ qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
++
++ if (microframe_schedule) {
++ // Make sure we leave one channel for non periodic transactions.
++ DWC_SPINLOCK_IRQSAVE(channel_lock, &flags);
++ if (hcd->available_host_channels <= 1) {
++ DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags);
++ break;
++ }
++ hcd->available_host_channels--;
++ DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags);
++#ifdef DEBUG_HOST_CHANNELS
++ last_sel_trans_num_per_scheduled++;
++#endif /* DEBUG_HOST_CHANNELS */
++ }
++ qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
++ assign_and_init_hc(hcd, qh);
++
++ /*
++ * Move the QH from the periodic ready schedule to the
++ * periodic assigned schedule.
++ */
++ qh_ptr = DWC_LIST_NEXT(qh_ptr);
++ DWC_SPINLOCK_IRQSAVE(channel_lock, &flags);
++ DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned,
++ &qh->qh_list_entry);
++ DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags);
++ }
++
++ /*
++ * Process entries in the inactive portion of the non-periodic
++ * schedule. Some free host channels may not be used if they are
++ * reserved for periodic transfers.
++ */
++ qh_ptr = hcd->non_periodic_sched_inactive.next;
++ num_channels = hcd->core_if->core_params->host_channels;
++ while (qh_ptr != &hcd->non_periodic_sched_inactive &&
++ (microframe_schedule || hcd->non_periodic_channels <
++ num_channels - hcd->periodic_channels) &&
++ !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
++
++ qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
++ /*
++ * Check to see if this is a NAK'd retransmit, in which case ignore for retransmission
++ * we hold off on bulk retransmissions to reduce NAK interrupt overhead for full-speed
++ * cheeky devices that just hold off using NAKs
++ */
++ if (fiq_enable && nak_holdoff && qh->do_split) {
++ if (qh->nak_frame != 0xffff) {
++ uint16_t next_frame = dwc_frame_num_inc(qh->nak_frame, (qh->ep_type == UE_BULK) ? nak_holdoff : 8);
++ uint16_t frame = dwc_otg_hcd_get_frame_number(hcd);
++ if (dwc_frame_num_le(frame, next_frame)) {
++ if(dwc_frame_num_le(next_frame, hcd->fiq_state->next_sched_frame)) {
++ hcd->fiq_state->next_sched_frame = next_frame;
++ }
++ qh_ptr = DWC_LIST_NEXT(qh_ptr);
++ continue;
++ } else {
++ qh->nak_frame = 0xFFFF;
++ }
++ }
++ }
++
++ if (microframe_schedule) {
++ DWC_SPINLOCK_IRQSAVE(channel_lock, &flags);
++ if (hcd->available_host_channels < 1) {
++ DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags);
++ break;
++ }
++ hcd->available_host_channels--;
++ DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags);
++#ifdef DEBUG_HOST_CHANNELS
++ last_sel_trans_num_nonper_scheduled++;
++#endif /* DEBUG_HOST_CHANNELS */
++ }
++
++ assign_and_init_hc(hcd, qh);
++
++ /*
++ * Move the QH from the non-periodic inactive schedule to the
++ * non-periodic active schedule.
++ */
++ qh_ptr = DWC_LIST_NEXT(qh_ptr);
++ DWC_SPINLOCK_IRQSAVE(channel_lock, &flags);
++ DWC_LIST_MOVE_HEAD(&hcd->non_periodic_sched_active,
++ &qh->qh_list_entry);
++ DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags);
++
++
++ if (!microframe_schedule)
++ hcd->non_periodic_channels++;
++ }
++ /* we moved a non-periodic QH to the active schedule. If the inactive queue is empty,
++ * stop the FIQ from kicking us. We could potentially still have elements here if we
++ * ran out of host channels.
++ */
++ if (fiq_enable) {
++ if (DWC_LIST_EMPTY(&hcd->non_periodic_sched_inactive)) {
++ hcd->fiq_state->kick_np_queues = 0;
++ } else {
++ /* For each entry remaining in the NP inactive queue,
++ * if this a NAK'd retransmit then don't set the kick flag.
++ */
++ if(nak_holdoff) {
++ DWC_LIST_FOREACH(qh_ptr, &hcd->non_periodic_sched_inactive) {
++ qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
++ if (qh->nak_frame == 0xFFFF) {
++ hcd->fiq_state->kick_np_queues = 1;
++ }
++ }
++ }
++ }
++ }
++ if(!DWC_LIST_EMPTY(&hcd->periodic_sched_assigned))
++ ret_val |= DWC_OTG_TRANSACTION_PERIODIC;
++
++ if(!DWC_LIST_EMPTY(&hcd->non_periodic_sched_active))
++ ret_val |= DWC_OTG_TRANSACTION_NON_PERIODIC;
++
++
++#ifdef DEBUG_HOST_CHANNELS
++ last_sel_trans_num_avail_hc_at_end = hcd->available_host_channels;
++#endif /* DEBUG_HOST_CHANNELS */
++ return ret_val;
++}
++
++/**
++ * Attempts to queue a single transaction request for a host channel
++ * associated with either a periodic or non-periodic transfer. This function
++ * assumes that there is space available in the appropriate request queue. For
++ * an OUT transfer or SETUP transaction in Slave mode, it checks whether space
++ * is available in the appropriate Tx FIFO.
++ *
++ * @param hcd The HCD state structure.
++ * @param hc Host channel descriptor associated with either a periodic or
++ * non-periodic transfer.
++ * @param fifo_dwords_avail Number of DWORDs available in the periodic Tx
++ * FIFO for periodic transfers or the non-periodic Tx FIFO for non-periodic
++ * transfers.
++ *
++ * @return 1 if a request is queued and more requests may be needed to
++ * complete the transfer, 0 if no more requests are required for this
++ * transfer, -1 if there is insufficient space in the Tx FIFO.
++ */
++static int queue_transaction(dwc_otg_hcd_t * hcd,
++ dwc_hc_t * hc, uint16_t fifo_dwords_avail)
++{
++ int retval;
++
++ if (hcd->core_if->dma_enable) {
++ if (hcd->core_if->dma_desc_enable) {
++ if (!hc->xfer_started
++ || (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)) {
++ dwc_otg_hcd_start_xfer_ddma(hcd, hc->qh);
++ hc->qh->ping_state = 0;
++ }
++ } else if (!hc->xfer_started) {
++ if (fiq_fsm_enable && hc->error_state) {
++ hcd->fiq_state->channel[hc->hc_num].nr_errors =
++ DWC_CIRCLEQ_FIRST(&hc->qh->qtd_list)->error_count;
++ hcd->fiq_state->channel[hc->hc_num].fsm =
++ FIQ_PASSTHROUGH_ERRORSTATE;
++ }
++ dwc_otg_hc_start_transfer(hcd->core_if, hc);
++ hc->qh->ping_state = 0;
++ }
++ retval = 0;
++ } else if (hc->halt_pending) {
++ /* Don't queue a request if the channel has been halted. */
++ retval = 0;
++ } else if (hc->halt_on_queue) {
++ dwc_otg_hc_halt(hcd->core_if, hc, hc->halt_status);
++ retval = 0;
++ } else if (hc->do_ping) {
++ if (!hc->xfer_started) {
++ dwc_otg_hc_start_transfer(hcd->core_if, hc);
++ }
++ retval = 0;
++ } else if (!hc->ep_is_in || hc->data_pid_start == DWC_OTG_HC_PID_SETUP) {
++ if ((fifo_dwords_avail * 4) >= hc->max_packet) {
++ if (!hc->xfer_started) {
++ dwc_otg_hc_start_transfer(hcd->core_if, hc);
++ retval = 1;
++ } else {
++ retval =
++ dwc_otg_hc_continue_transfer(hcd->core_if,
++ hc);
++ }
++ } else {
++ retval = -1;
++ }
++ } else {
++ if (!hc->xfer_started) {
++ dwc_otg_hc_start_transfer(hcd->core_if, hc);
++ retval = 1;
++ } else {
++ retval = dwc_otg_hc_continue_transfer(hcd->core_if, hc);
++ }
++ }
++
++ return retval;
++}
++
++/**
++ * Processes periodic channels for the next frame and queues transactions for
++ * these channels to the DWC_otg controller. After queueing transactions, the
++ * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
++ * to queue as Periodic Tx FIFO or request queue space becomes available.
++ * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
++ */
++static void process_periodic_channels(dwc_otg_hcd_t * hcd)
++{
++ hptxsts_data_t tx_status;
++ dwc_list_link_t *qh_ptr;
++ dwc_otg_qh_t *qh;
++ int status = 0;
++ int no_queue_space = 0;
++ int no_fifo_space = 0;
++
++ dwc_otg_host_global_regs_t *host_regs;
++ host_regs = hcd->core_if->host_if->host_global_regs;
++
++ DWC_DEBUGPL(DBG_HCDV, "Queue periodic transactions\n");
++#ifdef DEBUG
++ tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);
++ DWC_DEBUGPL(DBG_HCDV,
++ " P Tx Req Queue Space Avail (before queue): %d\n",
++ tx_status.b.ptxqspcavail);
++ DWC_DEBUGPL(DBG_HCDV, " P Tx FIFO Space Avail (before queue): %d\n",
++ tx_status.b.ptxfspcavail);
++#endif
++
++ qh_ptr = hcd->periodic_sched_assigned.next;
++ while (qh_ptr != &hcd->periodic_sched_assigned) {
++ tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);
++ if (tx_status.b.ptxqspcavail == 0) {
++ no_queue_space = 1;
++ break;
++ }
++
++ qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
++
++ // Do not send a split start transaction any later than frame .6
++ // Note, we have to schedule a periodic in .5 to make it go in .6
++ if(fiq_fsm_enable && qh->do_split && ((dwc_otg_hcd_get_frame_number(hcd) + 1) & 7) > 6)
++ {
++ qh_ptr = qh_ptr->next;
++ hcd->fiq_state->next_sched_frame = dwc_otg_hcd_get_frame_number(hcd) | 7;
++ continue;
++ }
++
++ if (fiq_fsm_enable && fiq_fsm_transaction_suitable(qh)) {
++ if (qh->do_split)
++ fiq_fsm_queue_split_transaction(hcd, qh);
++ else
++ fiq_fsm_queue_isoc_transaction(hcd, qh);
++ } else {
++
++ /*
++ * Set a flag if we're queueing high-bandwidth in slave mode.
++ * The flag prevents any halts to get into the request queue in
++ * the middle of multiple high-bandwidth packets getting queued.
++ */
++ if (!hcd->core_if->dma_enable && qh->channel->multi_count > 1) {
++ hcd->core_if->queuing_high_bandwidth = 1;
++ }
++ status = queue_transaction(hcd, qh->channel,
++ tx_status.b.ptxfspcavail);
++ if (status < 0) {
++ no_fifo_space = 1;
++ break;
++ }
++ }
++
++ /*
++ * In Slave mode, stay on the current transfer until there is
++ * nothing more to do or the high-bandwidth request count is
++ * reached. In DMA mode, only need to queue one request. The
++ * controller automatically handles multiple packets for
++ * high-bandwidth transfers.
++ */
++ if (hcd->core_if->dma_enable || status == 0 ||
++ qh->channel->requests == qh->channel->multi_count) {
++ qh_ptr = qh_ptr->next;
++ /*
++ * Move the QH from the periodic assigned schedule to
++ * the periodic queued schedule.
++ */
++ DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_queued,
++ &qh->qh_list_entry);
++
++ /* done queuing high bandwidth */
++ hcd->core_if->queuing_high_bandwidth = 0;
++ }
++ }
++
++ if (!hcd->core_if->dma_enable) {
++ dwc_otg_core_global_regs_t *global_regs;
++ gintmsk_data_t intr_mask = {.d32 = 0 };
++
++ global_regs = hcd->core_if->core_global_regs;
++ intr_mask.b.ptxfempty = 1;
++#ifdef DEBUG
++ tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);
++ DWC_DEBUGPL(DBG_HCDV,
++ " P Tx Req Queue Space Avail (after queue): %d\n",
++ tx_status.b.ptxqspcavail);
++ DWC_DEBUGPL(DBG_HCDV,
++ " P Tx FIFO Space Avail (after queue): %d\n",
++ tx_status.b.ptxfspcavail);
++#endif
++ if (!DWC_LIST_EMPTY(&hcd->periodic_sched_assigned) ||
++ no_queue_space || no_fifo_space) {
++ /*
++ * May need to queue more transactions as the request
++ * queue or Tx FIFO empties. Enable the periodic Tx
++ * FIFO empty interrupt. (Always use the half-empty
++ * level to ensure that new requests are loaded as
++ * soon as possible.)
++ */
++ DWC_MODIFY_REG32(&global_regs->gintmsk, 0,
++ intr_mask.d32);
++ } else {
++ /*
++ * Disable the Tx FIFO empty interrupt since there are
++ * no more transactions that need to be queued right
++ * now. This function is called from interrupt
++ * handlers to queue more transactions as transfer
++ * states change.
++ */
++ DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32,
++ 0);
++ }
++ }
++}
++
++/**
++ * Processes active non-periodic channels and queues transactions for these
++ * channels to the DWC_otg controller. After queueing transactions, the NP Tx
++ * FIFO Empty interrupt is enabled if there are more transactions to queue as
++ * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
++ * FIFO Empty interrupt is disabled.
++ */
++static void process_non_periodic_channels(dwc_otg_hcd_t * hcd)
++{
++ gnptxsts_data_t tx_status;
++ dwc_list_link_t *orig_qh_ptr;
++ dwc_otg_qh_t *qh;
++ int status;
++ int no_queue_space = 0;
++ int no_fifo_space = 0;
++ int more_to_do = 0;
++
++ dwc_otg_core_global_regs_t *global_regs =
++ hcd->core_if->core_global_regs;
++
++ DWC_DEBUGPL(DBG_HCDV, "Queue non-periodic transactions\n");
++#ifdef DEBUG
++ tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
++ DWC_DEBUGPL(DBG_HCDV,
++ " NP Tx Req Queue Space Avail (before queue): %d\n",
++ tx_status.b.nptxqspcavail);
++ DWC_DEBUGPL(DBG_HCDV, " NP Tx FIFO Space Avail (before queue): %d\n",
++ tx_status.b.nptxfspcavail);
++#endif
++ /*
++ * Keep track of the starting point. Skip over the start-of-list
++ * entry.
++ */
++ if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) {
++ hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
++ }
++ orig_qh_ptr = hcd->non_periodic_qh_ptr;
++
++ /*
++ * Process once through the active list or until no more space is
++ * available in the request queue or the Tx FIFO.
++ */
++ do {
++ tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
++ if (!hcd->core_if->dma_enable && tx_status.b.nptxqspcavail == 0) {
++ no_queue_space = 1;
++ break;
++ }
++
++ qh = DWC_LIST_ENTRY(hcd->non_periodic_qh_ptr, dwc_otg_qh_t,
++ qh_list_entry);
++
++ if(fiq_fsm_enable && fiq_fsm_transaction_suitable(qh)) {
++ fiq_fsm_queue_split_transaction(hcd, qh);
++ } else {
++ status = queue_transaction(hcd, qh->channel,
++ tx_status.b.nptxfspcavail);
++
++ if (status > 0) {
++ more_to_do = 1;
++ } else if (status < 0) {
++ no_fifo_space = 1;
++ break;
++ }
++ }
++ /* Advance to next QH, skipping start-of-list entry. */
++ hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
++ if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) {
++ hcd->non_periodic_qh_ptr =
++ hcd->non_periodic_qh_ptr->next;
++ }
++
++ } while (hcd->non_periodic_qh_ptr != orig_qh_ptr);
++
++ if (!hcd->core_if->dma_enable) {
++ gintmsk_data_t intr_mask = {.d32 = 0 };
++ intr_mask.b.nptxfempty = 1;
++
++#ifdef DEBUG
++ tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
++ DWC_DEBUGPL(DBG_HCDV,
++ " NP Tx Req Queue Space Avail (after queue): %d\n",
++ tx_status.b.nptxqspcavail);
++ DWC_DEBUGPL(DBG_HCDV,
++ " NP Tx FIFO Space Avail (after queue): %d\n",
++ tx_status.b.nptxfspcavail);
++#endif
++ if (more_to_do || no_queue_space || no_fifo_space) {
++ /*
++ * May need to queue more transactions as the request
++ * queue or Tx FIFO empties. Enable the non-periodic
++ * Tx FIFO empty interrupt. (Always use the half-empty
++ * level to ensure that new requests are loaded as
++ * soon as possible.)
++ */
++ DWC_MODIFY_REG32(&global_regs->gintmsk, 0,
++ intr_mask.d32);
++ } else {
++ /*
++ * Disable the Tx FIFO empty interrupt since there are
++ * no more transactions that need to be queued right
++ * now. This function is called from interrupt
++ * handlers to queue more transactions as transfer
++ * states change.
++ */
++ DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32,
++ 0);
++ }
++ }
++}
++
++/**
++ * This function processes the currently active host channels and queues
++ * transactions for these channels to the DWC_otg controller. It is called
++ * from HCD interrupt handler functions.
++ *
++ * @param hcd The HCD state structure.
++ * @param tr_type The type(s) of transactions to queue (non-periodic,
++ * periodic, or both).
++ */
++void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t * hcd,
++ dwc_otg_transaction_type_e tr_type)
++{
++#ifdef DEBUG_SOF
++ DWC_DEBUGPL(DBG_HCD, "Queue Transactions\n");
++#endif
++ /* Process host channels associated with periodic transfers. */
++ if ((tr_type == DWC_OTG_TRANSACTION_PERIODIC ||
++ tr_type == DWC_OTG_TRANSACTION_ALL) &&
++ !DWC_LIST_EMPTY(&hcd->periodic_sched_assigned)) {
++
++ process_periodic_channels(hcd);
++ }
++
++ /* Process host channels associated with non-periodic transfers. */
++ if (tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC ||
++ tr_type == DWC_OTG_TRANSACTION_ALL) {
++ if (!DWC_LIST_EMPTY(&hcd->non_periodic_sched_active)) {
++ process_non_periodic_channels(hcd);
++ } else {
++ /*
++ * Ensure NP Tx FIFO empty interrupt is disabled when
++ * there are no non-periodic transfers to process.
++ */
++ gintmsk_data_t gintmsk = {.d32 = 0 };
++ gintmsk.b.nptxfempty = 1;
++
++ if (fiq_enable) {
++ local_fiq_disable();
++ fiq_fsm_spin_lock(&hcd->fiq_state->lock);
++ DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
++ fiq_fsm_spin_unlock(&hcd->fiq_state->lock);
++ local_fiq_enable();
++ } else {
++ DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
++ }
++ }
++ }
++}
++
++#ifdef DWC_HS_ELECT_TST
++/*
++ * Quick and dirty hack to implement the HS Electrical Test
++ * SINGLE_STEP_GET_DEVICE_DESCRIPTOR feature.
++ *
++ * This code was copied from our userspace app "hset". It sends a
++ * Get Device Descriptor control sequence in two parts, first the
++ * Setup packet by itself, followed some time later by the In and
++ * Ack packets. Rather than trying to figure out how to add this
++ * functionality to the normal driver code, we just hijack the
++ * hardware, using these two function to drive the hardware
++ * directly.
++ */
++
++static dwc_otg_core_global_regs_t *global_regs;
++static dwc_otg_host_global_regs_t *hc_global_regs;
++static dwc_otg_hc_regs_t *hc_regs;
++static uint32_t *data_fifo;
++
++static void do_setup(void)
++{
++ gintsts_data_t gintsts;
++ hctsiz_data_t hctsiz;
++ hcchar_data_t hcchar;
++ haint_data_t haint;
++ hcint_data_t hcint;
++
++ /* Enable HAINTs */
++ DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0001);
++
++ /* Enable HCINTs */
++ DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x04a3);
++
++ /* Read GINTSTS */
++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
++
++ /* Read HAINT */
++ haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
++
++ /* Read HCINT */
++ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
++
++ /* Read HCCHAR */
++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
++
++ /* Clear HCINT */
++ DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
++
++ /* Clear HAINT */
++ DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
++
++ /* Clear GINTSTS */
++ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
++
++ /* Read GINTSTS */
++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
++
++ /*
++ * Send Setup packet (Get Device Descriptor)
++ */
++
++ /* Make sure channel is disabled */
++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
++ if (hcchar.b.chen) {
++ hcchar.b.chdis = 1;
++// hcchar.b.chen = 1;
++ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
++ //sleep(1);
++ dwc_mdelay(1000);
++
++ /* Read GINTSTS */
++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
++
++ /* Read HAINT */
++ haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
++
++ /* Read HCINT */
++ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
++
++ /* Read HCCHAR */
++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
++
++ /* Clear HCINT */
++ DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
++
++ /* Clear HAINT */
++ DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
++
++ /* Clear GINTSTS */
++ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
++
++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
++ }
++
++ /* Set HCTSIZ */
++ hctsiz.d32 = 0;
++ hctsiz.b.xfersize = 8;
++ hctsiz.b.pktcnt = 1;
++ hctsiz.b.pid = DWC_OTG_HC_PID_SETUP;
++ DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
++
++ /* Set HCCHAR */
++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
++ hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
++ hcchar.b.epdir = 0;
++ hcchar.b.epnum = 0;
++ hcchar.b.mps = 8;
++ hcchar.b.chen = 1;
++ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
++
++ /* Fill FIFO with Setup data for Get Device Descriptor */
++ data_fifo = (uint32_t *) ((char *)global_regs + 0x1000);
++ DWC_WRITE_REG32(data_fifo++, 0x01000680);
++ DWC_WRITE_REG32(data_fifo++, 0x00080000);
++
++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
++
++ /* Wait for host channel interrupt */
++ do {
++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
++ } while (gintsts.b.hcintr == 0);
++
++ /* Disable HCINTs */
++ DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x0000);
++
++ /* Disable HAINTs */
++ DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0000);
++
++ /* Read HAINT */
++ haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
++
++ /* Read HCINT */
++ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
++
++ /* Read HCCHAR */
++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
++
++ /* Clear HCINT */
++ DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
++
++ /* Clear HAINT */
++ DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
++
++ /* Clear GINTSTS */
++ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
++
++ /* Read GINTSTS */
++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
++}
++
++static void do_in_ack(void)
++{
++ gintsts_data_t gintsts;
++ hctsiz_data_t hctsiz;
++ hcchar_data_t hcchar;
++ haint_data_t haint;
++ hcint_data_t hcint;
++ host_grxsts_data_t grxsts;
++
++ /* Enable HAINTs */
++ DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0001);
++
++ /* Enable HCINTs */
++ DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x04a3);
++
++ /* Read GINTSTS */
++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
++
++ /* Read HAINT */
++ haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
++
++ /* Read HCINT */
++ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
++
++ /* Read HCCHAR */
++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
++
++ /* Clear HCINT */
++ DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
++
++ /* Clear HAINT */
++ DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
++
++ /* Clear GINTSTS */
++ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
++
++ /* Read GINTSTS */
++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
++
++ /*
++ * Receive Control In packet
++ */
++
++ /* Make sure channel is disabled */
++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
++ if (hcchar.b.chen) {
++ hcchar.b.chdis = 1;
++ hcchar.b.chen = 1;
++ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
++ //sleep(1);
++ dwc_mdelay(1000);
++
++ /* Read GINTSTS */
++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
++
++ /* Read HAINT */
++ haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
++
++ /* Read HCINT */
++ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
++
++ /* Read HCCHAR */
++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
++
++ /* Clear HCINT */
++ DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
++
++ /* Clear HAINT */
++ DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
++
++ /* Clear GINTSTS */
++ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
++
++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
++ }
++
++ /* Set HCTSIZ */
++ hctsiz.d32 = 0;
++ hctsiz.b.xfersize = 8;
++ hctsiz.b.pktcnt = 1;
++ hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
++ DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
++
++ /* Set HCCHAR */
++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
++ hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
++ hcchar.b.epdir = 1;
++ hcchar.b.epnum = 0;
++ hcchar.b.mps = 8;
++ hcchar.b.chen = 1;
++ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
++
++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
++
++ /* Wait for receive status queue interrupt */
++ do {
++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
++ } while (gintsts.b.rxstsqlvl == 0);
++
++ /* Read RXSTS */
++ grxsts.d32 = DWC_READ_REG32(&global_regs->grxstsp);
++
++ /* Clear RXSTSQLVL in GINTSTS */
++ gintsts.d32 = 0;
++ gintsts.b.rxstsqlvl = 1;
++ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
++
++ switch (grxsts.b.pktsts) {
++ case DWC_GRXSTS_PKTSTS_IN:
++ /* Read the data into the host buffer */
++ if (grxsts.b.bcnt > 0) {
++ int i;
++ int word_count = (grxsts.b.bcnt + 3) / 4;
++
++ data_fifo = (uint32_t *) ((char *)global_regs + 0x1000);
++
++ for (i = 0; i < word_count; i++) {
++ (void)DWC_READ_REG32(data_fifo++);
++ }
++ }
++ break;
++
++ default:
++ break;
++ }
++
++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
++
++ /* Wait for receive status queue interrupt */
++ do {
++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
++ } while (gintsts.b.rxstsqlvl == 0);
++
++ /* Read RXSTS */
++ grxsts.d32 = DWC_READ_REG32(&global_regs->grxstsp);
++
++ /* Clear RXSTSQLVL in GINTSTS */
++ gintsts.d32 = 0;
++ gintsts.b.rxstsqlvl = 1;
++ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
++
++ switch (grxsts.b.pktsts) {
++ case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
++ break;
++
++ default:
++ break;
++ }
++
++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
++
++ /* Wait for host channel interrupt */
++ do {
++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
++ } while (gintsts.b.hcintr == 0);
++
++ /* Read HAINT */
++ haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
++
++ /* Read HCINT */
++ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
++
++ /* Read HCCHAR */
++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
++
++ /* Clear HCINT */
++ DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
++
++ /* Clear HAINT */
++ DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
++
++ /* Clear GINTSTS */
++ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
++
++ /* Read GINTSTS */
++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
++
++// usleep(100000);
++// mdelay(100);
++ dwc_mdelay(1);
++
++ /*
++ * Send handshake packet
++ */
++
++ /* Read HAINT */
++ haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
++
++ /* Read HCINT */
++ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
++
++ /* Read HCCHAR */
++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
++
++ /* Clear HCINT */
++ DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
++
++ /* Clear HAINT */
++ DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
++
++ /* Clear GINTSTS */
++ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
++
++ /* Read GINTSTS */
++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
++
++ /* Make sure channel is disabled */
++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
++ if (hcchar.b.chen) {
++ hcchar.b.chdis = 1;
++ hcchar.b.chen = 1;
++ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
++ //sleep(1);
++ dwc_mdelay(1000);
++
++ /* Read GINTSTS */
++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
++
++ /* Read HAINT */
++ haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
++
++ /* Read HCINT */
++ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
++
++ /* Read HCCHAR */
++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
++
++ /* Clear HCINT */
++ DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
++
++ /* Clear HAINT */
++ DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
++
++ /* Clear GINTSTS */
++ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
++
++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
++ }
++
++ /* Set HCTSIZ */
++ hctsiz.d32 = 0;
++ hctsiz.b.xfersize = 0;
++ hctsiz.b.pktcnt = 1;
++ hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
++ DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
++
++ /* Set HCCHAR */
++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
++ hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
++ hcchar.b.epdir = 0;
++ hcchar.b.epnum = 0;
++ hcchar.b.mps = 8;
++ hcchar.b.chen = 1;
++ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
++
++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
++
++ /* Wait for host channel interrupt */
++ do {
++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
++ } while (gintsts.b.hcintr == 0);
++
++ /* Disable HCINTs */
++ DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x0000);
++
++ /* Disable HAINTs */
++ DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0000);
++
++ /* Read HAINT */
++ haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
++
++ /* Read HCINT */
++ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
++
++ /* Read HCCHAR */
++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
++
++ /* Clear HCINT */
++ DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
++
++ /* Clear HAINT */
++ DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
++
++ /* Clear GINTSTS */
++ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
++
++ /* Read GINTSTS */
++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
++}
++#endif
++
++/** Handles hub class-specific requests. */
++int dwc_otg_hcd_hub_control(dwc_otg_hcd_t * dwc_otg_hcd,
++ uint16_t typeReq,
++ uint16_t wValue,
++ uint16_t wIndex, uint8_t * buf, uint16_t wLength)
++{
++ int retval = 0;
++
++ dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
++ usb_hub_descriptor_t *hub_desc;
++ hprt0_data_t hprt0 = {.d32 = 0 };
++
++ uint32_t port_status;
++
++ switch (typeReq) {
++ case UCR_CLEAR_HUB_FEATURE:
++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
++ "ClearHubFeature 0x%x\n", wValue);
++ switch (wValue) {
++ case UHF_C_HUB_LOCAL_POWER:
++ case UHF_C_HUB_OVER_CURRENT:
++ /* Nothing required here */
++ break;
++ default:
++ retval = -DWC_E_INVALID;
++ DWC_ERROR("DWC OTG HCD - "
++ "ClearHubFeature request %xh unknown\n",
++ wValue);
++ }
++ break;
++ case UCR_CLEAR_PORT_FEATURE:
++#ifdef CONFIG_USB_DWC_OTG_LPM
++ if (wValue != UHF_PORT_L1)
++#endif
++ if (!wIndex || wIndex > 1)
++ goto error;
++
++ switch (wValue) {
++ case UHF_PORT_ENABLE:
++ DWC_DEBUGPL(DBG_ANY, "DWC OTG HCD HUB CONTROL - "
++ "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
++ hprt0.d32 = dwc_otg_read_hprt0(core_if);
++ hprt0.b.prtena = 1;
++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
++ break;
++ case UHF_PORT_SUSPEND:
++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
++ "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
++
++ if (core_if->power_down == 2) {
++ dwc_otg_host_hibernation_restore(core_if, 0, 0);
++ } else {
++ DWC_WRITE_REG32(core_if->pcgcctl, 0);
++ dwc_mdelay(5);
++
++ hprt0.d32 = dwc_otg_read_hprt0(core_if);
++ hprt0.b.prtres = 1;
++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
++ hprt0.b.prtsusp = 0;
++ /* Clear Resume bit */
++ dwc_mdelay(100);
++ hprt0.b.prtres = 0;
++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
++ }
++ break;
++#ifdef CONFIG_USB_DWC_OTG_LPM
++ case UHF_PORT_L1:
++ {
++ pcgcctl_data_t pcgcctl = {.d32 = 0 };
++ glpmcfg_data_t lpmcfg = {.d32 = 0 };
++
++ lpmcfg.d32 =
++ DWC_READ_REG32(&core_if->
++ core_global_regs->glpmcfg);
++ lpmcfg.b.en_utmi_sleep = 0;
++ lpmcfg.b.hird_thres &= (~(1 << 4));
++ lpmcfg.b.prt_sleep_sts = 1;
++ DWC_WRITE_REG32(&core_if->
++ core_global_regs->glpmcfg,
++ lpmcfg.d32);
++
++ /* Clear Enbl_L1Gating bit. */
++ pcgcctl.b.enbl_sleep_gating = 1;
++ DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32,
++ 0);
++
++ dwc_mdelay(5);
++
++ hprt0.d32 = dwc_otg_read_hprt0(core_if);
++ hprt0.b.prtres = 1;
++ DWC_WRITE_REG32(core_if->host_if->hprt0,
++ hprt0.d32);
++ /* This bit will be cleared in wakeup interrupt handle */
++ break;
++ }
++#endif
++ case UHF_PORT_POWER:
++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
++ "ClearPortFeature USB_PORT_FEAT_POWER\n");
++ hprt0.d32 = dwc_otg_read_hprt0(core_if);
++ hprt0.b.prtpwr = 0;
++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
++ break;
++ case UHF_PORT_INDICATOR:
++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
++ "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
++ /* Port inidicator not supported */
++ break;
++ case UHF_C_PORT_CONNECTION:
++ /* Clears drivers internal connect status change
++ * flag */
++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
++ "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
++ dwc_otg_hcd->flags.b.port_connect_status_change = 0;
++ break;
++ case UHF_C_PORT_RESET:
++ /* Clears the driver's internal Port Reset Change
++ * flag */
++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
++ "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
++ dwc_otg_hcd->flags.b.port_reset_change = 0;
++ break;
++ case UHF_C_PORT_ENABLE:
++ /* Clears the driver's internal Port
++ * Enable/Disable Change flag */
++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
++ "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
++ dwc_otg_hcd->flags.b.port_enable_change = 0;
++ break;
++ case UHF_C_PORT_SUSPEND:
++ /* Clears the driver's internal Port Suspend
++ * Change flag, which is set when resume signaling on
++ * the host port is complete */
++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
++ "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
++ dwc_otg_hcd->flags.b.port_suspend_change = 0;
++ break;
++#ifdef CONFIG_USB_DWC_OTG_LPM
++ case UHF_C_PORT_L1:
++ dwc_otg_hcd->flags.b.port_l1_change = 0;
++ break;
++#endif
++ case UHF_C_PORT_OVER_CURRENT:
++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
++ "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
++ dwc_otg_hcd->flags.b.port_over_current_change = 0;
++ break;
++ default:
++ retval = -DWC_E_INVALID;
++ DWC_ERROR("DWC OTG HCD - "
++ "ClearPortFeature request %xh "
++ "unknown or unsupported\n", wValue);
++ }
++ break;
++ case UCR_GET_HUB_DESCRIPTOR:
++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
++ "GetHubDescriptor\n");
++ hub_desc = (usb_hub_descriptor_t *) buf;
++ hub_desc->bDescLength = 9;
++ hub_desc->bDescriptorType = 0x29;
++ hub_desc->bNbrPorts = 1;
++ USETW(hub_desc->wHubCharacteristics, 0x08);
++ hub_desc->bPwrOn2PwrGood = 1;
++ hub_desc->bHubContrCurrent = 0;
++ hub_desc->DeviceRemovable[0] = 0;
++ hub_desc->DeviceRemovable[1] = 0xff;
++ break;
++ case UCR_GET_HUB_STATUS:
++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
++ "GetHubStatus\n");
++ DWC_MEMSET(buf, 0, 4);
++ break;
++ case UCR_GET_PORT_STATUS:
++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
++ "GetPortStatus wIndex = 0x%04x FLAGS=0x%08x\n",
++ wIndex, dwc_otg_hcd->flags.d32);
++ if (!wIndex || wIndex > 1)
++ goto error;
++
++ port_status = 0;
++
++ if (dwc_otg_hcd->flags.b.port_connect_status_change)
++ port_status |= (1 << UHF_C_PORT_CONNECTION);
++
++ if (dwc_otg_hcd->flags.b.port_enable_change)
++ port_status |= (1 << UHF_C_PORT_ENABLE);
++
++ if (dwc_otg_hcd->flags.b.port_suspend_change)
++ port_status |= (1 << UHF_C_PORT_SUSPEND);
++
++ if (dwc_otg_hcd->flags.b.port_l1_change)
++ port_status |= (1 << UHF_C_PORT_L1);
++
++ if (dwc_otg_hcd->flags.b.port_reset_change) {
++ port_status |= (1 << UHF_C_PORT_RESET);
++ }
++
++ if (dwc_otg_hcd->flags.b.port_over_current_change) {
++ DWC_WARN("Overcurrent change detected\n");
++ port_status |= (1 << UHF_C_PORT_OVER_CURRENT);
++ }
++
++ if (!dwc_otg_hcd->flags.b.port_connect_status) {
++ /*
++ * The port is disconnected, which means the core is
++ * either in device mode or it soon will be. Just
++ * return 0's for the remainder of the port status
++ * since the port register can't be read if the core
++ * is in device mode.
++ */
++ *((__le32 *) buf) = dwc_cpu_to_le32(&port_status);
++ break;
++ }
++
++ hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
++ DWC_DEBUGPL(DBG_HCDV, " HPRT0: 0x%08x\n", hprt0.d32);
++
++ if (hprt0.b.prtconnsts)
++ port_status |= (1 << UHF_PORT_CONNECTION);
++
++ if (hprt0.b.prtena)
++ port_status |= (1 << UHF_PORT_ENABLE);
++
++ if (hprt0.b.prtsusp)
++ port_status |= (1 << UHF_PORT_SUSPEND);
++
++ if (hprt0.b.prtovrcurract)
++ port_status |= (1 << UHF_PORT_OVER_CURRENT);
++
++ if (hprt0.b.prtrst)
++ port_status |= (1 << UHF_PORT_RESET);
++
++ if (hprt0.b.prtpwr)
++ port_status |= (1 << UHF_PORT_POWER);
++
++ if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED)
++ port_status |= (1 << UHF_PORT_HIGH_SPEED);
++ else if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED)
++ port_status |= (1 << UHF_PORT_LOW_SPEED);
++
++ if (hprt0.b.prttstctl)
++ port_status |= (1 << UHF_PORT_TEST);
++ if (dwc_otg_get_lpm_portsleepstatus(dwc_otg_hcd->core_if)) {
++ port_status |= (1 << UHF_PORT_L1);
++ }
++ /*
++ For Synopsys HW emulation of Power down wkup_control asserts the
++ hreset_n and prst_n on suspned. This causes the HPRT0 to be zero.
++ We intentionally tell the software that port is in L2Suspend state.
++ Only for STE.
++ */
++ if ((core_if->power_down == 2)
++ && (core_if->hibernation_suspend == 1)) {
++ port_status |= (1 << UHF_PORT_SUSPEND);
++ }
++ /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
++
++ *((__le32 *) buf) = dwc_cpu_to_le32(&port_status);
++
++ break;
++ case UCR_SET_HUB_FEATURE:
++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
++ "SetHubFeature\n");
++ /* No HUB features supported */
++ break;
++ case UCR_SET_PORT_FEATURE:
++ if (wValue != UHF_PORT_TEST && (!wIndex || wIndex > 1))
++ goto error;
++
++ if (!dwc_otg_hcd->flags.b.port_connect_status) {
++ /*
++ * The port is disconnected, which means the core is
++ * either in device mode or it soon will be. Just
++ * return without doing anything since the port
++ * register can't be written if the core is in device
++ * mode.
++ */
++ break;
++ }
++
++ switch (wValue) {
++ case UHF_PORT_SUSPEND:
++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
++ "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
++ if (dwc_otg_hcd_otg_port(dwc_otg_hcd) != wIndex) {
++ goto error;
++ }
++ if (core_if->power_down == 2) {
++ int timeout = 300;
++ dwc_irqflags_t flags;
++ pcgcctl_data_t pcgcctl = {.d32 = 0 };
++ gpwrdn_data_t gpwrdn = {.d32 = 0 };
++ gusbcfg_data_t gusbcfg = {.d32 = 0 };
++#ifdef DWC_DEV_SRPCAP
++ int32_t otg_cap_param = core_if->core_params->otg_cap;
++#endif
++ DWC_PRINTF("Preparing for complete power-off\n");
++
++ /* Save registers before hibernation */
++ dwc_otg_save_global_regs(core_if);
++ dwc_otg_save_host_regs(core_if);
++
++ hprt0.d32 = dwc_otg_read_hprt0(core_if);
++ hprt0.b.prtsusp = 1;
++ hprt0.b.prtena = 0;
++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
++ /* Spin hprt0.b.prtsusp to became 1 */
++ do {
++ hprt0.d32 = dwc_otg_read_hprt0(core_if);
++ if (hprt0.b.prtsusp) {
++ break;
++ }
++ dwc_mdelay(1);
++ } while (--timeout);
++ if (!timeout) {
++ DWC_WARN("Suspend wasn't genereted\n");
++ }
++ dwc_udelay(10);
++
++ /*
++ * We need to disable interrupts to prevent servicing of any IRQ
++ * during going to hibernation
++ */
++ DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
++ core_if->lx_state = DWC_OTG_L2;
++#ifdef DWC_DEV_SRPCAP
++ hprt0.d32 = dwc_otg_read_hprt0(core_if);
++ hprt0.b.prtpwr = 0;
++ hprt0.b.prtena = 0;
++ DWC_WRITE_REG32(core_if->host_if->hprt0,
++ hprt0.d32);
++#endif
++ gusbcfg.d32 =
++ DWC_READ_REG32(&core_if->core_global_regs->
++ gusbcfg);
++ if (gusbcfg.b.ulpi_utmi_sel == 1) {
++ /* ULPI interface */
++ /* Suspend the Phy Clock */
++ pcgcctl.d32 = 0;
++ pcgcctl.b.stoppclk = 1;
++ DWC_MODIFY_REG32(core_if->pcgcctl, 0,
++ pcgcctl.d32);
++ dwc_udelay(10);
++ gpwrdn.b.pmuactv = 1;
++ DWC_MODIFY_REG32(&core_if->
++ core_global_regs->
++ gpwrdn, 0, gpwrdn.d32);
++ } else {
++ /* UTMI+ Interface */
++ gpwrdn.b.pmuactv = 1;
++ DWC_MODIFY_REG32(&core_if->
++ core_global_regs->
++ gpwrdn, 0, gpwrdn.d32);
++ dwc_udelay(10);
++ pcgcctl.b.stoppclk = 1;
++ DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32);
++ dwc_udelay(10);
++ }
++#ifdef DWC_DEV_SRPCAP
++ gpwrdn.d32 = 0;
++ gpwrdn.b.dis_vbus = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->
++ gpwrdn, 0, gpwrdn.d32);
++#endif
++ gpwrdn.d32 = 0;
++ gpwrdn.b.pmuintsel = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->
++ gpwrdn, 0, gpwrdn.d32);
++ dwc_udelay(10);
++
++ gpwrdn.d32 = 0;
++#ifdef DWC_DEV_SRPCAP
++ gpwrdn.b.srp_det_msk = 1;
++#endif
++ gpwrdn.b.disconn_det_msk = 1;
++ gpwrdn.b.lnstchng_msk = 1;
++ gpwrdn.b.sts_chngint_msk = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->
++ gpwrdn, 0, gpwrdn.d32);
++ dwc_udelay(10);
++
++ /* Enable Power Down Clamp and all interrupts in GPWRDN */
++ gpwrdn.d32 = 0;
++ gpwrdn.b.pwrdnclmp = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->
++ gpwrdn, 0, gpwrdn.d32);
++ dwc_udelay(10);
++
++ /* Switch off VDD */
++ gpwrdn.d32 = 0;
++ gpwrdn.b.pwrdnswtch = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->
++ gpwrdn, 0, gpwrdn.d32);
++
++#ifdef DWC_DEV_SRPCAP
++ if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE)
++ {
++ core_if->pwron_timer_started = 1;
++ DWC_TIMER_SCHEDULE(core_if->pwron_timer, 6000 /* 6 secs */ );
++ }
++#endif
++ /* Save gpwrdn register for further usage if stschng interrupt */
++ core_if->gr_backup->gpwrdn_local =
++ DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
++
++ /* Set flag to indicate that we are in hibernation */
++ core_if->hibernation_suspend = 1;
++ DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock,flags);
++
++ DWC_PRINTF("Host hibernation completed\n");
++ // Exit from case statement
++ break;
++
++ }
++ if (dwc_otg_hcd_otg_port(dwc_otg_hcd) == wIndex &&
++ dwc_otg_hcd->fops->get_b_hnp_enable(dwc_otg_hcd)) {
++ gotgctl_data_t gotgctl = {.d32 = 0 };
++ gotgctl.b.hstsethnpen = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->
++ gotgctl, 0, gotgctl.d32);
++ core_if->op_state = A_SUSPEND;
++ }
++ hprt0.d32 = dwc_otg_read_hprt0(core_if);
++ hprt0.b.prtsusp = 1;
++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
++ {
++ dwc_irqflags_t flags;
++ /* Update lx_state */
++ DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
++ core_if->lx_state = DWC_OTG_L2;
++ DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags);
++ }
++ /* Suspend the Phy Clock */
++ {
++ pcgcctl_data_t pcgcctl = {.d32 = 0 };
++ pcgcctl.b.stoppclk = 1;
++ DWC_MODIFY_REG32(core_if->pcgcctl, 0,
++ pcgcctl.d32);
++ dwc_udelay(10);
++ }
++
++ /* For HNP the bus must be suspended for at least 200ms. */
++ if (dwc_otg_hcd->fops->get_b_hnp_enable(dwc_otg_hcd)) {
++ pcgcctl_data_t pcgcctl = {.d32 = 0 };
++ pcgcctl.b.stoppclk = 1;
++ DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
++ dwc_mdelay(200);
++ }
++
++ /** @todo - check how sw can wait for 1 sec to check asesvld??? */
++#if 0 //vahrama !!!!!!!!!!!!!!!!!!
++ if (core_if->adp_enable) {
++ gotgctl_data_t gotgctl = {.d32 = 0 };
++ gpwrdn_data_t gpwrdn;
++
++ while (gotgctl.b.asesvld == 1) {
++ gotgctl.d32 =
++ DWC_READ_REG32(&core_if->
++ core_global_regs->
++ gotgctl);
++ dwc_mdelay(100);
++ }
++
++ /* Enable Power Down Logic */
++ gpwrdn.d32 = 0;
++ gpwrdn.b.pmuactv = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->
++ gpwrdn, 0, gpwrdn.d32);
++
++ /* Unmask SRP detected interrupt from Power Down Logic */
++ gpwrdn.d32 = 0;
++ gpwrdn.b.srp_det_msk = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->
++ gpwrdn, 0, gpwrdn.d32);
++
++ dwc_otg_adp_probe_start(core_if);
++ }
++#endif
++ break;
++ case UHF_PORT_POWER:
++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
++ "SetPortFeature - USB_PORT_FEAT_POWER\n");
++ hprt0.d32 = dwc_otg_read_hprt0(core_if);
++ hprt0.b.prtpwr = 1;
++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
++ break;
++ case UHF_PORT_RESET:
++ if ((core_if->power_down == 2)
++ && (core_if->hibernation_suspend == 1)) {
++ /* If we are going to exit from Hibernated
++ * state via USB RESET.
++ */
++ dwc_otg_host_hibernation_restore(core_if, 0, 1);
++ } else {
++ hprt0.d32 = dwc_otg_read_hprt0(core_if);
++
++ DWC_DEBUGPL(DBG_HCD,
++ "DWC OTG HCD HUB CONTROL - "
++ "SetPortFeature - USB_PORT_FEAT_RESET\n");
++ {
++ pcgcctl_data_t pcgcctl = {.d32 = 0 };
++ pcgcctl.b.enbl_sleep_gating = 1;
++ pcgcctl.b.stoppclk = 1;
++ DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
++ DWC_WRITE_REG32(core_if->pcgcctl, 0);
++ }
++#ifdef CONFIG_USB_DWC_OTG_LPM
++ {
++ glpmcfg_data_t lpmcfg;
++ lpmcfg.d32 =
++ DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
++ if (lpmcfg.b.prt_sleep_sts) {
++ lpmcfg.b.en_utmi_sleep = 0;
++ lpmcfg.b.hird_thres &= (~(1 << 4));
++ DWC_WRITE_REG32
++ (&core_if->core_global_regs->glpmcfg,
++ lpmcfg.d32);
++ dwc_mdelay(1);
++ }
++ }
++#endif
++ hprt0.d32 = dwc_otg_read_hprt0(core_if);
++ /* Clear suspend bit if resetting from suspended state. */
++ hprt0.b.prtsusp = 0;
++ /* When B-Host the Port reset bit is set in
++ * the Start HCD Callback function, so that
++ * the reset is started within 1ms of the HNP
++ * success interrupt. */
++ if (!dwc_otg_hcd_is_b_host(dwc_otg_hcd)) {
++ hprt0.b.prtpwr = 1;
++ hprt0.b.prtrst = 1;
++ DWC_PRINTF("Indeed it is in host mode hprt0 = %08x\n",hprt0.d32);
++ DWC_WRITE_REG32(core_if->host_if->hprt0,
++ hprt0.d32);
++ }
++ /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
++ dwc_mdelay(60);
++ hprt0.b.prtrst = 0;
++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
++ core_if->lx_state = DWC_OTG_L0; /* Now back to the on state */
++ }
++ break;
++#ifdef DWC_HS_ELECT_TST
++ case UHF_PORT_TEST:
++ {
++ uint32_t t;
++ gintmsk_data_t gintmsk;
++
++ t = (wIndex >> 8); /* MSB wIndex USB */
++ DWC_DEBUGPL(DBG_HCD,
++ "DWC OTG HCD HUB CONTROL - "
++ "SetPortFeature - USB_PORT_FEAT_TEST %d\n",
++ t);
++ DWC_WARN("USB_PORT_FEAT_TEST %d\n", t);
++ if (t < 6) {
++ hprt0.d32 = dwc_otg_read_hprt0(core_if);
++ hprt0.b.prttstctl = t;
++ DWC_WRITE_REG32(core_if->host_if->hprt0,
++ hprt0.d32);
++ } else {
++ /* Setup global vars with reg addresses (quick and
++ * dirty hack, should be cleaned up)
++ */
++ global_regs = core_if->core_global_regs;
++ hc_global_regs =
++ core_if->host_if->host_global_regs;
++ hc_regs =
++ (dwc_otg_hc_regs_t *) ((char *)
++ global_regs +
++ 0x500);
++ data_fifo =
++ (uint32_t *) ((char *)global_regs +
++ 0x1000);
++
++ if (t == 6) { /* HS_HOST_PORT_SUSPEND_RESUME */
++ /* Save current interrupt mask */
++ gintmsk.d32 =
++ DWC_READ_REG32
++ (&global_regs->gintmsk);
++
++ /* Disable all interrupts while we muck with
++ * the hardware directly
++ */
++ DWC_WRITE_REG32(&global_regs->gintmsk, 0);
++
++ /* 15 second delay per the test spec */
++ dwc_mdelay(15000);
++
++ /* Drive suspend on the root port */
++ hprt0.d32 =
++ dwc_otg_read_hprt0(core_if);
++ hprt0.b.prtsusp = 1;
++ hprt0.b.prtres = 0;
++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
++
++ /* 15 second delay per the test spec */
++ dwc_mdelay(15000);
++
++ /* Drive resume on the root port */
++ hprt0.d32 =
++ dwc_otg_read_hprt0(core_if);
++ hprt0.b.prtsusp = 0;
++ hprt0.b.prtres = 1;
++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
++ dwc_mdelay(100);
++
++ /* Clear the resume bit */
++ hprt0.b.prtres = 0;
++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
++
++ /* Restore interrupts */
++ DWC_WRITE_REG32(&global_regs->gintmsk, gintmsk.d32);
++ } else if (t == 7) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */
++ /* Save current interrupt mask */
++ gintmsk.d32 =
++ DWC_READ_REG32
++ (&global_regs->gintmsk);
++
++ /* Disable all interrupts while we muck with
++ * the hardware directly
++ */
++ DWC_WRITE_REG32(&global_regs->gintmsk, 0);
++
++ /* 15 second delay per the test spec */
++ dwc_mdelay(15000);
++
++ /* Send the Setup packet */
++ do_setup();
++
++ /* 15 second delay so nothing else happens for awhile */
++ dwc_mdelay(15000);
++
++ /* Restore interrupts */
++ DWC_WRITE_REG32(&global_regs->gintmsk, gintmsk.d32);
++ } else if (t == 8) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */
++ /* Save current interrupt mask */
++ gintmsk.d32 =
++ DWC_READ_REG32
++ (&global_regs->gintmsk);
++
++ /* Disable all interrupts while we muck with
++ * the hardware directly
++ */
++ DWC_WRITE_REG32(&global_regs->gintmsk, 0);
++
++ /* Send the Setup packet */
++ do_setup();
++
++ /* 15 second delay so nothing else happens for awhile */
++ dwc_mdelay(15000);
++
++ /* Send the In and Ack packets */
++ do_in_ack();
++
++ /* 15 second delay so nothing else happens for awhile */
++ dwc_mdelay(15000);
++
++ /* Restore interrupts */
++ DWC_WRITE_REG32(&global_regs->gintmsk, gintmsk.d32);
++ }
++ }
++ break;
++ }
++#endif /* DWC_HS_ELECT_TST */
++
++ case UHF_PORT_INDICATOR:
++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
++ "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
++ /* Not supported */
++ break;
++ default:
++ retval = -DWC_E_INVALID;
++ DWC_ERROR("DWC OTG HCD - "
++ "SetPortFeature request %xh "
++ "unknown or unsupported\n", wValue);
++ break;
++ }
++ break;
++#ifdef CONFIG_USB_DWC_OTG_LPM
++ case UCR_SET_AND_TEST_PORT_FEATURE:
++ if (wValue != UHF_PORT_L1) {
++ goto error;
++ }
++ {
++ int portnum, hird, devaddr, remwake;
++ glpmcfg_data_t lpmcfg;
++ uint32_t time_usecs;
++ gintsts_data_t gintsts;
++ gintmsk_data_t gintmsk;
++
++ if (!dwc_otg_get_param_lpm_enable(core_if)) {
++ goto error;
++ }
++ if (wValue != UHF_PORT_L1 || wLength != 1) {
++ goto error;
++ }
++ /* Check if the port currently is in SLEEP state */
++ lpmcfg.d32 =
++ DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
++ if (lpmcfg.b.prt_sleep_sts) {
++ DWC_INFO("Port is already in sleep mode\n");
++ buf[0] = 0; /* Return success */
++ break;
++ }
++
++ portnum = wIndex & 0xf;
++ hird = (wIndex >> 4) & 0xf;
++ devaddr = (wIndex >> 8) & 0x7f;
++ remwake = (wIndex >> 15);
++
++ if (portnum != 1) {
++ retval = -DWC_E_INVALID;
++ DWC_WARN
++ ("Wrong port number(%d) in SetandTestPortFeature request\n",
++ portnum);
++ break;
++ }
++
++ DWC_PRINTF
++ ("SetandTestPortFeature request: portnum = %d, hird = %d, devaddr = %d, rewake = %d\n",
++ portnum, hird, devaddr, remwake);
++ /* Disable LPM interrupt */
++ gintmsk.d32 = 0;
++ gintmsk.b.lpmtranrcvd = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk,
++ gintmsk.d32, 0);
++
++ if (dwc_otg_hcd_send_lpm
++ (dwc_otg_hcd, devaddr, hird, remwake)) {
++ retval = -DWC_E_INVALID;
++ break;
++ }
++
++ time_usecs = 10 * (lpmcfg.b.retry_count + 1);
++ /* We will consider timeout if time_usecs microseconds pass,
++ * and we don't receive LPM transaction status.
++ * After receiving non-error responce(ACK/NYET/STALL) from device,
++ * core will set lpmtranrcvd bit.
++ */
++ do {
++ gintsts.d32 =
++ DWC_READ_REG32(&core_if->core_global_regs->gintsts);
++ if (gintsts.b.lpmtranrcvd) {
++ break;
++ }
++ dwc_udelay(1);
++ } while (--time_usecs);
++ /* lpm_int bit will be cleared in LPM interrupt handler */
++
++ /* Now fill status
++ * 0x00 - Success
++ * 0x10 - NYET
++ * 0x11 - Timeout
++ */
++ if (!gintsts.b.lpmtranrcvd) {
++ buf[0] = 0x3; /* Completion code is Timeout */
++ dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd);
++ } else {
++ lpmcfg.d32 =
++ DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
++ if (lpmcfg.b.lpm_resp == 0x3) {
++ /* ACK responce from the device */
++ buf[0] = 0x00; /* Success */
++ } else if (lpmcfg.b.lpm_resp == 0x2) {
++ /* NYET responce from the device */
++ buf[0] = 0x2;
++ } else {
++ /* Otherwise responce with Timeout */
++ buf[0] = 0x3;
++ }
++ }
++ DWC_PRINTF("Device responce to LPM trans is %x\n",
++ lpmcfg.b.lpm_resp);
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0,
++ gintmsk.d32);
++
++ break;
++ }
++#endif /* CONFIG_USB_DWC_OTG_LPM */
++ default:
++error:
++ retval = -DWC_E_INVALID;
++ DWC_WARN("DWC OTG HCD - "
++ "Unknown hub control request type or invalid typeReq: %xh wIndex: %xh wValue: %xh\n",
++ typeReq, wIndex, wValue);
++ break;
++ }
++
++ return retval;
++}
++
++#ifdef CONFIG_USB_DWC_OTG_LPM
++/** Returns index of host channel to perform LPM transaction. */
++int dwc_otg_hcd_get_hc_for_lpm_tran(dwc_otg_hcd_t * hcd, uint8_t devaddr)
++{
++ dwc_otg_core_if_t *core_if = hcd->core_if;
++ dwc_hc_t *hc;
++ hcchar_data_t hcchar;
++ gintmsk_data_t gintmsk = {.d32 = 0 };
++
++ if (DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
++ DWC_PRINTF("No free channel to select for LPM transaction\n");
++ return -1;
++ }
++
++ hc = DWC_CIRCLEQ_FIRST(&hcd->free_hc_list);
++
++ /* Mask host channel interrupts. */
++ gintmsk.b.hcintr = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
++
++ /* Fill fields that core needs for LPM transaction */
++ hcchar.b.devaddr = devaddr;
++ hcchar.b.epnum = 0;
++ hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
++ hcchar.b.mps = 64;
++ hcchar.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW);
++ hcchar.b.epdir = 0; /* OUT */
++ DWC_WRITE_REG32(&core_if->host_if->hc_regs[hc->hc_num]->hcchar,
++ hcchar.d32);
++
++ /* Remove the host channel from the free list. */
++ DWC_CIRCLEQ_REMOVE_INIT(&hcd->free_hc_list, hc, hc_list_entry);
++
++ DWC_PRINTF("hcnum = %d devaddr = %d\n", hc->hc_num, devaddr);
++
++ return hc->hc_num;
++}
++
++/** Release hc after performing LPM transaction */
++void dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd_t * hcd)
++{
++ dwc_hc_t *hc;
++ glpmcfg_data_t lpmcfg;
++ uint8_t hc_num;
++
++ lpmcfg.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->glpmcfg);
++ hc_num = lpmcfg.b.lpm_chan_index;
++
++ hc = hcd->hc_ptr_array[hc_num];
++
++ DWC_PRINTF("Freeing channel %d after LPM\n", hc_num);
++ /* Return host channel to free list */
++ DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry);
++}
++
++int dwc_otg_hcd_send_lpm(dwc_otg_hcd_t * hcd, uint8_t devaddr, uint8_t hird,
++ uint8_t bRemoteWake)
++{
++ glpmcfg_data_t lpmcfg;
++ pcgcctl_data_t pcgcctl = {.d32 = 0 };
++ int channel;
++
++ channel = dwc_otg_hcd_get_hc_for_lpm_tran(hcd, devaddr);
++ if (channel < 0) {
++ return channel;
++ }
++
++ pcgcctl.b.enbl_sleep_gating = 1;
++ DWC_MODIFY_REG32(hcd->core_if->pcgcctl, 0, pcgcctl.d32);
++
++ /* Read LPM config register */
++ lpmcfg.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->glpmcfg);
++
++ /* Program LPM transaction fields */
++ lpmcfg.b.rem_wkup_en = bRemoteWake;
++ lpmcfg.b.hird = hird;
++ lpmcfg.b.hird_thres = 0x1c;
++ lpmcfg.b.lpm_chan_index = channel;
++ lpmcfg.b.en_utmi_sleep = 1;
++ /* Program LPM config register */
++ DWC_WRITE_REG32(&hcd->core_if->core_global_regs->glpmcfg, lpmcfg.d32);
++
++ /* Send LPM transaction */
++ lpmcfg.b.send_lpm = 1;
++ DWC_WRITE_REG32(&hcd->core_if->core_global_regs->glpmcfg, lpmcfg.d32);
++
++ return 0;
++}
++
++#endif /* CONFIG_USB_DWC_OTG_LPM */
++
++int dwc_otg_hcd_is_status_changed(dwc_otg_hcd_t * hcd, int port)
++{
++ int retval;
++
++ if (port != 1) {
++ return -DWC_E_INVALID;
++ }
++
++ retval = (hcd->flags.b.port_connect_status_change ||
++ hcd->flags.b.port_reset_change ||
++ hcd->flags.b.port_enable_change ||
++ hcd->flags.b.port_suspend_change ||
++ hcd->flags.b.port_over_current_change);
++#ifdef DEBUG
++ if (retval) {
++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB STATUS DATA:"
++ " Root port status changed\n");
++ DWC_DEBUGPL(DBG_HCDV, " port_connect_status_change: %d\n",
++ hcd->flags.b.port_connect_status_change);
++ DWC_DEBUGPL(DBG_HCDV, " port_reset_change: %d\n",
++ hcd->flags.b.port_reset_change);
++ DWC_DEBUGPL(DBG_HCDV, " port_enable_change: %d\n",
++ hcd->flags.b.port_enable_change);
++ DWC_DEBUGPL(DBG_HCDV, " port_suspend_change: %d\n",
++ hcd->flags.b.port_suspend_change);
++ DWC_DEBUGPL(DBG_HCDV, " port_over_current_change: %d\n",
++ hcd->flags.b.port_over_current_change);
++ }
++#endif
++ return retval;
++}
++
++int dwc_otg_hcd_get_frame_number(dwc_otg_hcd_t * dwc_otg_hcd)
++{
++ hfnum_data_t hfnum;
++ hfnum.d32 =
++ DWC_READ_REG32(&dwc_otg_hcd->core_if->host_if->host_global_regs->
++ hfnum);
++
++#ifdef DEBUG_SOF
++ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD GET FRAME NUMBER %d\n",
++ hfnum.b.frnum);
++#endif
++ return hfnum.b.frnum;
++}
++
++int dwc_otg_hcd_start(dwc_otg_hcd_t * hcd,
++ struct dwc_otg_hcd_function_ops *fops)
++{
++ int retval = 0;
++
++ hcd->fops = fops;
++ if (!dwc_otg_is_device_mode(hcd->core_if) &&
++ (!hcd->core_if->adp_enable || hcd->core_if->adp.adp_started)) {
++ dwc_otg_hcd_reinit(hcd);
++ } else {
++ retval = -DWC_E_NO_DEVICE;
++ }
++
++ return retval;
++}
++
++void *dwc_otg_hcd_get_priv_data(dwc_otg_hcd_t * hcd)
++{
++ return hcd->priv;
++}
++
++void dwc_otg_hcd_set_priv_data(dwc_otg_hcd_t * hcd, void *priv_data)
++{
++ hcd->priv = priv_data;
++}
++
++uint32_t dwc_otg_hcd_otg_port(dwc_otg_hcd_t * hcd)
++{
++ return hcd->otg_port;
++}
++
++uint32_t dwc_otg_hcd_is_b_host(dwc_otg_hcd_t * hcd)
++{
++ uint32_t is_b_host;
++ if (hcd->core_if->op_state == B_HOST) {
++ is_b_host = 1;
++ } else {
++ is_b_host = 0;
++ }
++
++ return is_b_host;
++}
++
++dwc_otg_hcd_urb_t *dwc_otg_hcd_urb_alloc(dwc_otg_hcd_t * hcd,
++ int iso_desc_count, int atomic_alloc)
++{
++ dwc_otg_hcd_urb_t *dwc_otg_urb;
++ uint32_t size;
++
++ size =
++ sizeof(*dwc_otg_urb) +
++ iso_desc_count * sizeof(struct dwc_otg_hcd_iso_packet_desc);
++ if (atomic_alloc)
++ dwc_otg_urb = DWC_ALLOC_ATOMIC(size);
++ else
++ dwc_otg_urb = DWC_ALLOC(size);
++
++ if (dwc_otg_urb)
++ dwc_otg_urb->packet_count = iso_desc_count;
++ else {
++ DWC_ERROR("**** DWC OTG HCD URB alloc - "
++ "%salloc of %db failed\n",
++ atomic_alloc?"atomic ":"", size);
++ }
++ return dwc_otg_urb;
++}
++
++void dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_hcd_urb_t * dwc_otg_urb,
++ uint8_t dev_addr, uint8_t ep_num,
++ uint8_t ep_type, uint8_t ep_dir, uint16_t mps)
++{
++ dwc_otg_hcd_fill_pipe(&dwc_otg_urb->pipe_info, dev_addr, ep_num,
++ ep_type, ep_dir, mps);
++#if 0
++ DWC_PRINTF
++ ("addr = %d, ep_num = %d, ep_dir = 0x%x, ep_type = 0x%x, mps = %d\n",
++ dev_addr, ep_num, ep_dir, ep_type, mps);
++#endif
++}
++
++void dwc_otg_hcd_urb_set_params(dwc_otg_hcd_urb_t * dwc_otg_urb,
++ void *urb_handle, void *buf, dwc_dma_t dma,
++ uint32_t buflen, void *setup_packet,
++ dwc_dma_t setup_dma, uint32_t flags,
++ uint16_t interval)
++{
++ dwc_otg_urb->priv = urb_handle;
++ dwc_otg_urb->buf = buf;
++ dwc_otg_urb->dma = dma;
++ dwc_otg_urb->length = buflen;
++ dwc_otg_urb->setup_packet = setup_packet;
++ dwc_otg_urb->setup_dma = setup_dma;
++ dwc_otg_urb->flags = flags;
++ dwc_otg_urb->interval = interval;
++ dwc_otg_urb->status = -DWC_E_IN_PROGRESS;
++}
++
++uint32_t dwc_otg_hcd_urb_get_status(dwc_otg_hcd_urb_t * dwc_otg_urb)
++{
++ return dwc_otg_urb->status;
++}
++
++uint32_t dwc_otg_hcd_urb_get_actual_length(dwc_otg_hcd_urb_t * dwc_otg_urb)
++{
++ return dwc_otg_urb->actual_length;
++}
++
++uint32_t dwc_otg_hcd_urb_get_error_count(dwc_otg_hcd_urb_t * dwc_otg_urb)
++{
++ return dwc_otg_urb->error_count;
++}
++
++void dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_hcd_urb_t * dwc_otg_urb,
++ int desc_num, uint32_t offset,
++ uint32_t length)
++{
++ dwc_otg_urb->iso_descs[desc_num].offset = offset;
++ dwc_otg_urb->iso_descs[desc_num].length = length;
++}
++
++uint32_t dwc_otg_hcd_urb_get_iso_desc_status(dwc_otg_hcd_urb_t * dwc_otg_urb,
++ int desc_num)
++{
++ return dwc_otg_urb->iso_descs[desc_num].status;
++}
++
++uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length(dwc_otg_hcd_urb_t *
++ dwc_otg_urb, int desc_num)
++{
++ return dwc_otg_urb->iso_descs[desc_num].actual_length;
++}
++
++int dwc_otg_hcd_is_bandwidth_allocated(dwc_otg_hcd_t * hcd, void *ep_handle)
++{
++ int allocated = 0;
++ dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
++
++ if (qh) {
++ if (!DWC_LIST_EMPTY(&qh->qh_list_entry)) {
++ allocated = 1;
++ }
++ }
++ return allocated;
++}
++
++int dwc_otg_hcd_is_bandwidth_freed(dwc_otg_hcd_t * hcd, void *ep_handle)
++{
++ dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
++ int freed = 0;
++ DWC_ASSERT(qh, "qh is not allocated\n");
++
++ if (DWC_LIST_EMPTY(&qh->qh_list_entry)) {
++ freed = 1;
++ }
++
++ return freed;
++}
++
++uint8_t dwc_otg_hcd_get_ep_bandwidth(dwc_otg_hcd_t * hcd, void *ep_handle)
++{
++ dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
++ DWC_ASSERT(qh, "qh is not allocated\n");
++ return qh->usecs;
++}
++
++void dwc_otg_hcd_dump_state(dwc_otg_hcd_t * hcd)
++{
++#ifdef DEBUG
++ int num_channels;
++ int i;
++ gnptxsts_data_t np_tx_status;
++ hptxsts_data_t p_tx_status;
++
++ num_channels = hcd->core_if->core_params->host_channels;
++ DWC_PRINTF("\n");
++ DWC_PRINTF
++ ("************************************************************\n");
++ DWC_PRINTF("HCD State:\n");
++ DWC_PRINTF(" Num channels: %d\n", num_channels);
++ for (i = 0; i < num_channels; i++) {
++ dwc_hc_t *hc = hcd->hc_ptr_array[i];
++ DWC_PRINTF(" Channel %d:\n", i);
++ DWC_PRINTF(" dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
++ hc->dev_addr, hc->ep_num, hc->ep_is_in);
++ DWC_PRINTF(" speed: %d\n", hc->speed);
++ DWC_PRINTF(" ep_type: %d\n", hc->ep_type);
++ DWC_PRINTF(" max_packet: %d\n", hc->max_packet);
++ DWC_PRINTF(" data_pid_start: %d\n", hc->data_pid_start);
++ DWC_PRINTF(" multi_count: %d\n", hc->multi_count);
++ DWC_PRINTF(" xfer_started: %d\n", hc->xfer_started);
++ DWC_PRINTF(" xfer_buff: %p\n", hc->xfer_buff);
++ DWC_PRINTF(" xfer_len: %d\n", hc->xfer_len);
++ DWC_PRINTF(" xfer_count: %d\n", hc->xfer_count);
++ DWC_PRINTF(" halt_on_queue: %d\n", hc->halt_on_queue);
++ DWC_PRINTF(" halt_pending: %d\n", hc->halt_pending);
++ DWC_PRINTF(" halt_status: %d\n", hc->halt_status);
++ DWC_PRINTF(" do_split: %d\n", hc->do_split);
++ DWC_PRINTF(" complete_split: %d\n", hc->complete_split);
++ DWC_PRINTF(" hub_addr: %d\n", hc->hub_addr);
++ DWC_PRINTF(" port_addr: %d\n", hc->port_addr);
++ DWC_PRINTF(" xact_pos: %d\n", hc->xact_pos);
++ DWC_PRINTF(" requests: %d\n", hc->requests);
++ DWC_PRINTF(" qh: %p\n", hc->qh);
++ if (hc->xfer_started) {
++ hfnum_data_t hfnum;
++ hcchar_data_t hcchar;
++ hctsiz_data_t hctsiz;
++ hcint_data_t hcint;
++ hcintmsk_data_t hcintmsk;
++ hfnum.d32 =
++ DWC_READ_REG32(&hcd->core_if->
++ host_if->host_global_regs->hfnum);
++ hcchar.d32 =
++ DWC_READ_REG32(&hcd->core_if->host_if->
++ hc_regs[i]->hcchar);
++ hctsiz.d32 =
++ DWC_READ_REG32(&hcd->core_if->host_if->
++ hc_regs[i]->hctsiz);
++ hcint.d32 =
++ DWC_READ_REG32(&hcd->core_if->host_if->
++ hc_regs[i]->hcint);
++ hcintmsk.d32 =
++ DWC_READ_REG32(&hcd->core_if->host_if->
++ hc_regs[i]->hcintmsk);
++ DWC_PRINTF(" hfnum: 0x%08x\n", hfnum.d32);
++ DWC_PRINTF(" hcchar: 0x%08x\n", hcchar.d32);
++ DWC_PRINTF(" hctsiz: 0x%08x\n", hctsiz.d32);
++ DWC_PRINTF(" hcint: 0x%08x\n", hcint.d32);
++ DWC_PRINTF(" hcintmsk: 0x%08x\n", hcintmsk.d32);
++ }
++ if (hc->xfer_started && hc->qh) {
++ dwc_otg_qtd_t *qtd;
++ dwc_otg_hcd_urb_t *urb;
++
++ DWC_CIRCLEQ_FOREACH(qtd, &hc->qh->qtd_list, qtd_list_entry) {
++ if (!qtd->in_process)
++ break;
++
++ urb = qtd->urb;
++ DWC_PRINTF(" URB Info:\n");
++ DWC_PRINTF(" qtd: %p, urb: %p\n", qtd, urb);
++ if (urb) {
++ DWC_PRINTF(" Dev: %d, EP: %d %s\n",
++ dwc_otg_hcd_get_dev_addr(&urb->
++ pipe_info),
++ dwc_otg_hcd_get_ep_num(&urb->
++ pipe_info),
++ dwc_otg_hcd_is_pipe_in(&urb->
++ pipe_info) ?
++ "IN" : "OUT");
++ DWC_PRINTF(" Max packet size: %d\n",
++ dwc_otg_hcd_get_mps(&urb->
++ pipe_info));
++ DWC_PRINTF(" transfer_buffer: %p\n",
++ urb->buf);
++ DWC_PRINTF(" transfer_dma: %p\n",
++ (void *)urb->dma);
++ DWC_PRINTF(" transfer_buffer_length: %d\n",
++ urb->length);
++ DWC_PRINTF(" actual_length: %d\n",
++ urb->actual_length);
++ }
++ }
++ }
++ }
++ DWC_PRINTF(" non_periodic_channels: %d\n", hcd->non_periodic_channels);
++ DWC_PRINTF(" periodic_channels: %d\n", hcd->periodic_channels);
++ DWC_PRINTF(" periodic_usecs: %d\n", hcd->periodic_usecs);
++ np_tx_status.d32 =
++ DWC_READ_REG32(&hcd->core_if->core_global_regs->gnptxsts);
++ DWC_PRINTF(" NP Tx Req Queue Space Avail: %d\n",
++ np_tx_status.b.nptxqspcavail);
++ DWC_PRINTF(" NP Tx FIFO Space Avail: %d\n",
++ np_tx_status.b.nptxfspcavail);
++ p_tx_status.d32 =
++ DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hptxsts);
++ DWC_PRINTF(" P Tx Req Queue Space Avail: %d\n",
++ p_tx_status.b.ptxqspcavail);
++ DWC_PRINTF(" P Tx FIFO Space Avail: %d\n", p_tx_status.b.ptxfspcavail);
++ dwc_otg_hcd_dump_frrem(hcd);
++ dwc_otg_dump_global_registers(hcd->core_if);
++ dwc_otg_dump_host_registers(hcd->core_if);
++ DWC_PRINTF
++ ("************************************************************\n");
++ DWC_PRINTF("\n");
++#endif
++}
++
++#ifdef DEBUG
++void dwc_print_setup_data(uint8_t * setup)
++{
++ int i;
++ if (CHK_DEBUG_LEVEL(DBG_HCD)) {
++ DWC_PRINTF("Setup Data = MSB ");
++ for (i = 7; i >= 0; i--)
++ DWC_PRINTF("%02x ", setup[i]);
++ DWC_PRINTF("\n");
++ DWC_PRINTF(" bmRequestType Tranfer = %s\n",
++ (setup[0] & 0x80) ? "Device-to-Host" :
++ "Host-to-Device");
++ DWC_PRINTF(" bmRequestType Type = ");
++ switch ((setup[0] & 0x60) >> 5) {
++ case 0:
++ DWC_PRINTF("Standard\n");
++ break;
++ case 1:
++ DWC_PRINTF("Class\n");
++ break;
++ case 2:
++ DWC_PRINTF("Vendor\n");
++ break;
++ case 3:
++ DWC_PRINTF("Reserved\n");
++ break;
++ }
++ DWC_PRINTF(" bmRequestType Recipient = ");
++ switch (setup[0] & 0x1f) {
++ case 0:
++ DWC_PRINTF("Device\n");
++ break;
++ case 1:
++ DWC_PRINTF("Interface\n");
++ break;
++ case 2:
++ DWC_PRINTF("Endpoint\n");
++ break;
++ case 3:
++ DWC_PRINTF("Other\n");
++ break;
++ default:
++ DWC_PRINTF("Reserved\n");
++ break;
++ }
++ DWC_PRINTF(" bRequest = 0x%0x\n", setup[1]);
++ DWC_PRINTF(" wValue = 0x%0x\n", *((uint16_t *) & setup[2]));
++ DWC_PRINTF(" wIndex = 0x%0x\n", *((uint16_t *) & setup[4]));
++ DWC_PRINTF(" wLength = 0x%0x\n\n", *((uint16_t *) & setup[6]));
++ }
++}
++#endif
++
++void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t * hcd)
++{
++#if 0
++ DWC_PRINTF("Frame remaining at SOF:\n");
++ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
++ hcd->frrem_samples, hcd->frrem_accum,
++ (hcd->frrem_samples > 0) ?
++ hcd->frrem_accum / hcd->frrem_samples : 0);
++
++ DWC_PRINTF("\n");
++ DWC_PRINTF("Frame remaining at start_transfer (uframe 7):\n");
++ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
++ hcd->core_if->hfnum_7_samples,
++ hcd->core_if->hfnum_7_frrem_accum,
++ (hcd->core_if->hfnum_7_samples >
++ 0) ? hcd->core_if->hfnum_7_frrem_accum /
++ hcd->core_if->hfnum_7_samples : 0);
++ DWC_PRINTF("Frame remaining at start_transfer (uframe 0):\n");
++ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
++ hcd->core_if->hfnum_0_samples,
++ hcd->core_if->hfnum_0_frrem_accum,
++ (hcd->core_if->hfnum_0_samples >
++ 0) ? hcd->core_if->hfnum_0_frrem_accum /
++ hcd->core_if->hfnum_0_samples : 0);
++ DWC_PRINTF("Frame remaining at start_transfer (uframe 1-6):\n");
++ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
++ hcd->core_if->hfnum_other_samples,
++ hcd->core_if->hfnum_other_frrem_accum,
++ (hcd->core_if->hfnum_other_samples >
++ 0) ? hcd->core_if->hfnum_other_frrem_accum /
++ hcd->core_if->hfnum_other_samples : 0);
++
++ DWC_PRINTF("\n");
++ DWC_PRINTF("Frame remaining at sample point A (uframe 7):\n");
++ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
++ hcd->hfnum_7_samples_a, hcd->hfnum_7_frrem_accum_a,
++ (hcd->hfnum_7_samples_a > 0) ?
++ hcd->hfnum_7_frrem_accum_a / hcd->hfnum_7_samples_a : 0);
++ DWC_PRINTF("Frame remaining at sample point A (uframe 0):\n");
++ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
++ hcd->hfnum_0_samples_a, hcd->hfnum_0_frrem_accum_a,
++ (hcd->hfnum_0_samples_a > 0) ?
++ hcd->hfnum_0_frrem_accum_a / hcd->hfnum_0_samples_a : 0);
++ DWC_PRINTF("Frame remaining at sample point A (uframe 1-6):\n");
++ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
++ hcd->hfnum_other_samples_a, hcd->hfnum_other_frrem_accum_a,
++ (hcd->hfnum_other_samples_a > 0) ?
++ hcd->hfnum_other_frrem_accum_a /
++ hcd->hfnum_other_samples_a : 0);
++
++ DWC_PRINTF("\n");
++ DWC_PRINTF("Frame remaining at sample point B (uframe 7):\n");
++ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
++ hcd->hfnum_7_samples_b, hcd->hfnum_7_frrem_accum_b,
++ (hcd->hfnum_7_samples_b > 0) ?
++ hcd->hfnum_7_frrem_accum_b / hcd->hfnum_7_samples_b : 0);
++ DWC_PRINTF("Frame remaining at sample point B (uframe 0):\n");
++ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
++ hcd->hfnum_0_samples_b, hcd->hfnum_0_frrem_accum_b,
++ (hcd->hfnum_0_samples_b > 0) ?
++ hcd->hfnum_0_frrem_accum_b / hcd->hfnum_0_samples_b : 0);
++ DWC_PRINTF("Frame remaining at sample point B (uframe 1-6):\n");
++ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
++ hcd->hfnum_other_samples_b, hcd->hfnum_other_frrem_accum_b,
++ (hcd->hfnum_other_samples_b > 0) ?
++ hcd->hfnum_other_frrem_accum_b /
++ hcd->hfnum_other_samples_b : 0);
++#endif
++}
++
++#endif /* DWC_DEVICE_ONLY */
+diff -Nur linux-4.1.3/drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c linux-xbian-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c
+--- linux-4.1.3/drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c 2015-07-28 01:20:58.449142252 +0200
+@@ -0,0 +1,1132 @@
++/*==========================================================================
++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_ddma.c $
++ * $Revision: #10 $
++ * $Date: 2011/10/20 $
++ * $Change: 1869464 $
++ *
++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++ * otherwise expressly agreed to in writing between Synopsys and you.
++ *
++ * The Software IS NOT an item of Licensed Software or Licensed Product under
++ * any End User Software License Agreement or Agreement for Licensed Product
++ * with Synopsys or any supplement thereto. You are permitted to use and
++ * redistribute this Software in source and binary forms, with or without
++ * modification, provided that redistributions of source code must retain this
++ * notice. You may not view, use, disclose, copy or distribute this file or
++ * any information contained herein except pursuant to this license grant from
++ * Synopsys. If you do not agree with this notice, including the disclaimer
++ * below, then you are not authorized to use the Software.
++ *
++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++ * DAMAGE.
++ * ========================================================================== */
++#ifndef DWC_DEVICE_ONLY
++
++/** @file
++ * This file contains Descriptor DMA support implementation for host mode.
++ */
++
++#include "dwc_otg_hcd.h"
++#include "dwc_otg_regs.h"
++
++extern bool microframe_schedule;
++
++static inline uint8_t frame_list_idx(uint16_t frame)
++{
++ return (frame & (MAX_FRLIST_EN_NUM - 1));
++}
++
++static inline uint16_t desclist_idx_inc(uint16_t idx, uint16_t inc, uint8_t speed)
++{
++ return (idx + inc) &
++ (((speed ==
++ DWC_OTG_EP_SPEED_HIGH) ? MAX_DMA_DESC_NUM_HS_ISOC :
++ MAX_DMA_DESC_NUM_GENERIC) - 1);
++}
++
++static inline uint16_t desclist_idx_dec(uint16_t idx, uint16_t inc, uint8_t speed)
++{
++ return (idx - inc) &
++ (((speed ==
++ DWC_OTG_EP_SPEED_HIGH) ? MAX_DMA_DESC_NUM_HS_ISOC :
++ MAX_DMA_DESC_NUM_GENERIC) - 1);
++}
++
++static inline uint16_t max_desc_num(dwc_otg_qh_t * qh)
++{
++ return (((qh->ep_type == UE_ISOCHRONOUS)
++ && (qh->dev_speed == DWC_OTG_EP_SPEED_HIGH))
++ ? MAX_DMA_DESC_NUM_HS_ISOC : MAX_DMA_DESC_NUM_GENERIC);
++}
++static inline uint16_t frame_incr_val(dwc_otg_qh_t * qh)
++{
++ return ((qh->dev_speed == DWC_OTG_EP_SPEED_HIGH)
++ ? ((qh->interval + 8 - 1) / 8)
++ : qh->interval);
++}
++
++static int desc_list_alloc(dwc_otg_qh_t * qh)
++{
++ int retval = 0;
++
++ qh->desc_list = (dwc_otg_host_dma_desc_t *)
++ DWC_DMA_ALLOC(sizeof(dwc_otg_host_dma_desc_t) * max_desc_num(qh),
++ &qh->desc_list_dma);
++
++ if (!qh->desc_list) {
++ retval = -DWC_E_NO_MEMORY;
++ DWC_ERROR("%s: DMA descriptor list allocation failed\n", __func__);
++
++ }
++
++ dwc_memset(qh->desc_list, 0x00,
++ sizeof(dwc_otg_host_dma_desc_t) * max_desc_num(qh));
++
++ qh->n_bytes =
++ (uint32_t *) DWC_ALLOC(sizeof(uint32_t) * max_desc_num(qh));
++
++ if (!qh->n_bytes) {
++ retval = -DWC_E_NO_MEMORY;
++ DWC_ERROR
++ ("%s: Failed to allocate array for descriptors' size actual values\n",
++ __func__);
++
++ }
++ return retval;
++
++}
++
++static void desc_list_free(dwc_otg_qh_t * qh)
++{
++ if (qh->desc_list) {
++ DWC_DMA_FREE(max_desc_num(qh), qh->desc_list,
++ qh->desc_list_dma);
++ qh->desc_list = NULL;
++ }
++
++ if (qh->n_bytes) {
++ DWC_FREE(qh->n_bytes);
++ qh->n_bytes = NULL;
++ }
++}
++
++static int frame_list_alloc(dwc_otg_hcd_t * hcd)
++{
++ int retval = 0;
++ if (hcd->frame_list)
++ return 0;
++
++ hcd->frame_list = DWC_DMA_ALLOC(4 * MAX_FRLIST_EN_NUM,
++ &hcd->frame_list_dma);
++ if (!hcd->frame_list) {
++ retval = -DWC_E_NO_MEMORY;
++ DWC_ERROR("%s: Frame List allocation failed\n", __func__);
++ }
++
++ dwc_memset(hcd->frame_list, 0x00, 4 * MAX_FRLIST_EN_NUM);
++
++ return retval;
++}
++
++static void frame_list_free(dwc_otg_hcd_t * hcd)
++{
++ if (!hcd->frame_list)
++ return;
++
++ DWC_DMA_FREE(4 * MAX_FRLIST_EN_NUM, hcd->frame_list, hcd->frame_list_dma);
++ hcd->frame_list = NULL;
++}
++
++static void per_sched_enable(dwc_otg_hcd_t * hcd, uint16_t fr_list_en)
++{
++
++ hcfg_data_t hcfg;
++
++ hcfg.d32 = DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hcfg);
++
++ if (hcfg.b.perschedena) {
++ /* already enabled */
++ return;
++ }
++
++ DWC_WRITE_REG32(&hcd->core_if->host_if->host_global_regs->hflbaddr,
++ hcd->frame_list_dma);
++
++ switch (fr_list_en) {
++ case 64:
++ hcfg.b.frlisten = 3;
++ break;
++ case 32:
++ hcfg.b.frlisten = 2;
++ break;
++ case 16:
++ hcfg.b.frlisten = 1;
++ break;
++ case 8:
++ hcfg.b.frlisten = 0;
++ break;
++ default:
++ break;
++ }
++
++ hcfg.b.perschedena = 1;
++
++ DWC_DEBUGPL(DBG_HCD, "Enabling Periodic schedule\n");
++ DWC_WRITE_REG32(&hcd->core_if->host_if->host_global_regs->hcfg, hcfg.d32);
++
++}
++
++static void per_sched_disable(dwc_otg_hcd_t * hcd)
++{
++ hcfg_data_t hcfg;
++
++ hcfg.d32 = DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hcfg);
++
++ if (!hcfg.b.perschedena) {
++ /* already disabled */
++ return;
++ }
++ hcfg.b.perschedena = 0;
++
++ DWC_DEBUGPL(DBG_HCD, "Disabling Periodic schedule\n");
++ DWC_WRITE_REG32(&hcd->core_if->host_if->host_global_regs->hcfg, hcfg.d32);
++}
++
++/*
++ * Activates/Deactivates FrameList entries for the channel
++ * based on endpoint servicing period.
++ */
++void update_frame_list(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, uint8_t enable)
++{
++ uint16_t i, j, inc;
++ dwc_hc_t *hc = NULL;
++
++ if (!qh->channel) {
++ DWC_ERROR("qh->channel = %p", qh->channel);
++ return;
++ }
++
++ if (!hcd) {
++ DWC_ERROR("------hcd = %p", hcd);
++ return;
++ }
++
++ if (!hcd->frame_list) {
++ DWC_ERROR("-------hcd->frame_list = %p", hcd->frame_list);
++ return;
++ }
++
++ hc = qh->channel;
++ inc = frame_incr_val(qh);
++ if (qh->ep_type == UE_ISOCHRONOUS)
++ i = frame_list_idx(qh->sched_frame);
++ else
++ i = 0;
++
++ j = i;
++ do {
++ if (enable)
++ hcd->frame_list[j] |= (1 << hc->hc_num);
++ else
++ hcd->frame_list[j] &= ~(1 << hc->hc_num);
++ j = (j + inc) & (MAX_FRLIST_EN_NUM - 1);
++ }
++ while (j != i);
++ if (!enable)
++ return;
++ hc->schinfo = 0;
++ if (qh->channel->speed == DWC_OTG_EP_SPEED_HIGH) {
++ j = 1;
++ /* TODO - check this */
++ inc = (8 + qh->interval - 1) / qh->interval;
++ for (i = 0; i < inc; i++) {
++ hc->schinfo |= j;
++ j = j << qh->interval;
++ }
++ } else {
++ hc->schinfo = 0xff;
++ }
++}
++
++#if 1
++void dump_frame_list(dwc_otg_hcd_t * hcd)
++{
++ int i = 0;
++ DWC_PRINTF("--FRAME LIST (hex) --\n");
++ for (i = 0; i < MAX_FRLIST_EN_NUM; i++) {
++ DWC_PRINTF("%x\t", hcd->frame_list[i]);
++ if (!(i % 8) && i)
++ DWC_PRINTF("\n");
++ }
++ DWC_PRINTF("\n----\n");
++
++}
++#endif
++
++static void release_channel_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
++{
++ dwc_irqflags_t flags;
++ dwc_spinlock_t *channel_lock = hcd->channel_lock;
++
++ dwc_hc_t *hc = qh->channel;
++ if (dwc_qh_is_non_per(qh)) {
++ DWC_SPINLOCK_IRQSAVE(channel_lock, &flags);
++ if (!microframe_schedule)
++ hcd->non_periodic_channels--;
++ else
++ hcd->available_host_channels++;
++ DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags);
++ } else
++ update_frame_list(hcd, qh, 0);
++
++ /*
++ * The condition is added to prevent double cleanup try in case of device
++ * disconnect. See channel cleanup in dwc_otg_hcd_disconnect_cb().
++ */
++ if (hc->qh) {
++ dwc_otg_hc_cleanup(hcd->core_if, hc);
++ DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry);
++ hc->qh = NULL;
++ }
++
++ qh->channel = NULL;
++ qh->ntd = 0;
++
++ if (qh->desc_list) {
++ dwc_memset(qh->desc_list, 0x00,
++ sizeof(dwc_otg_host_dma_desc_t) * max_desc_num(qh));
++ }
++}
++
++/**
++ * Initializes a QH structure's Descriptor DMA related members.
++ * Allocates memory for descriptor list.
++ * On first periodic QH, allocates memory for FrameList
++ * and enables periodic scheduling.
++ *
++ * @param hcd The HCD state structure for the DWC OTG controller.
++ * @param qh The QH to init.
++ *
++ * @return 0 if successful, negative error code otherwise.
++ */
++int dwc_otg_hcd_qh_init_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
++{
++ int retval = 0;
++
++ if (qh->do_split) {
++ DWC_ERROR("SPLIT Transfers are not supported in Descriptor DMA.\n");
++ return -1;
++ }
++
++ retval = desc_list_alloc(qh);
++
++ if ((retval == 0)
++ && (qh->ep_type == UE_ISOCHRONOUS || qh->ep_type == UE_INTERRUPT)) {
++ if (!hcd->frame_list) {
++ retval = frame_list_alloc(hcd);
++ /* Enable periodic schedule on first periodic QH */
++ if (retval == 0)
++ per_sched_enable(hcd, MAX_FRLIST_EN_NUM);
++ }
++ }
++
++ qh->ntd = 0;
++
++ return retval;
++}
++
++/**
++ * Frees descriptor list memory associated with the QH.
++ * If QH is periodic and the last, frees FrameList memory
++ * and disables periodic scheduling.
++ *
++ * @param hcd The HCD state structure for the DWC OTG controller.
++ * @param qh The QH to init.
++ */
++void dwc_otg_hcd_qh_free_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
++{
++ desc_list_free(qh);
++
++ /*
++ * Channel still assigned due to some reasons.
++ * Seen on Isoc URB dequeue. Channel halted but no subsequent
++ * ChHalted interrupt to release the channel. Afterwards
++ * when it comes here from endpoint disable routine
++ * channel remains assigned.
++ */
++ if (qh->channel)
++ release_channel_ddma(hcd, qh);
++
++ if ((qh->ep_type == UE_ISOCHRONOUS || qh->ep_type == UE_INTERRUPT)
++ && (microframe_schedule || !hcd->periodic_channels) && hcd->frame_list) {
++
++ per_sched_disable(hcd);
++ frame_list_free(hcd);
++ }
++}
++
++static uint8_t frame_to_desc_idx(dwc_otg_qh_t * qh, uint16_t frame_idx)
++{
++ if (qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) {
++ /*
++ * Descriptor set(8 descriptors) index
++ * which is 8-aligned.
++ */
++ return (frame_idx & ((MAX_DMA_DESC_NUM_HS_ISOC / 8) - 1)) * 8;
++ } else {
++ return (frame_idx & (MAX_DMA_DESC_NUM_GENERIC - 1));
++ }
++}
++
++/*
++ * Determine starting frame for Isochronous transfer.
++ * Few frames skipped to prevent race condition with HC.
++ */
++static uint8_t calc_starting_frame(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh,
++ uint8_t * skip_frames)
++{
++ uint16_t frame = 0;
++ hcd->frame_number = dwc_otg_hcd_get_frame_number(hcd);
++
++ /* sched_frame is always frame number(not uFrame) both in FS and HS !! */
++
++ /*
++ * skip_frames is used to limit activated descriptors number
++ * to avoid the situation when HC services the last activated
++ * descriptor firstly.
++ * Example for FS:
++ * Current frame is 1, scheduled frame is 3. Since HC always fetches the descriptor
++ * corresponding to curr_frame+1, the descriptor corresponding to frame 2
++ * will be fetched. If the number of descriptors is max=64 (or greather) the
++ * list will be fully programmed with Active descriptors and it is possible
++ * case(rare) that the latest descriptor(considering rollback) corresponding
++ * to frame 2 will be serviced first. HS case is more probable because, in fact,
++ * up to 11 uframes(16 in the code) may be skipped.
++ */
++ if (qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) {
++ /*
++ * Consider uframe counter also, to start xfer asap.
++ * If half of the frame elapsed skip 2 frames otherwise
++ * just 1 frame.
++ * Starting descriptor index must be 8-aligned, so
++ * if the current frame is near to complete the next one
++ * is skipped as well.
++ */
++
++ if (dwc_micro_frame_num(hcd->frame_number) >= 5) {
++ *skip_frames = 2 * 8;
++ frame = dwc_frame_num_inc(hcd->frame_number, *skip_frames);
++ } else {
++ *skip_frames = 1 * 8;
++ frame = dwc_frame_num_inc(hcd->frame_number, *skip_frames);
++ }
++
++ frame = dwc_full_frame_num(frame);
++ } else {
++ /*
++ * Two frames are skipped for FS - the current and the next.
++ * But for descriptor programming, 1 frame(descriptor) is enough,
++ * see example above.
++ */
++ *skip_frames = 1;
++ frame = dwc_frame_num_inc(hcd->frame_number, 2);
++ }
++
++ return frame;
++}
++
++/*
++ * Calculate initial descriptor index for isochronous transfer
++ * based on scheduled frame.
++ */
++static uint8_t recalc_initial_desc_idx(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
++{
++ uint16_t frame = 0, fr_idx, fr_idx_tmp;
++ uint8_t skip_frames = 0;
++ /*
++ * With current ISOC processing algorithm the channel is being
++ * released when no more QTDs in the list(qh->ntd == 0).
++ * Thus this function is called only when qh->ntd == 0 and qh->channel == 0.
++ *
++ * So qh->channel != NULL branch is not used and just not removed from the
++ * source file. It is required for another possible approach which is,
++ * do not disable and release the channel when ISOC session completed,
++ * just move QH to inactive schedule until new QTD arrives.
++ * On new QTD, the QH moved back to 'ready' schedule,
++ * starting frame and therefore starting desc_index are recalculated.
++ * In this case channel is released only on ep_disable.
++ */
++
++ /* Calculate starting descriptor index. For INTERRUPT endpoint it is always 0. */
++ if (qh->channel) {
++ frame = calc_starting_frame(hcd, qh, &skip_frames);
++ /*
++ * Calculate initial descriptor index based on FrameList current bitmap
++ * and servicing period.
++ */
++ fr_idx_tmp = frame_list_idx(frame);
++ fr_idx =
++ (MAX_FRLIST_EN_NUM + frame_list_idx(qh->sched_frame) -
++ fr_idx_tmp)
++ % frame_incr_val(qh);
++ fr_idx = (fr_idx + fr_idx_tmp) % MAX_FRLIST_EN_NUM;
++ } else {
++ qh->sched_frame = calc_starting_frame(hcd, qh, &skip_frames);
++ fr_idx = frame_list_idx(qh->sched_frame);
++ }
++
++ qh->td_first = qh->td_last = frame_to_desc_idx(qh, fr_idx);
++
++ return skip_frames;
++}
++
++#define ISOC_URB_GIVEBACK_ASAP
++
++#define MAX_ISOC_XFER_SIZE_FS 1023
++#define MAX_ISOC_XFER_SIZE_HS 3072
++#define DESCNUM_THRESHOLD 4
++
++static void init_isoc_dma_desc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh,
++ uint8_t skip_frames)
++{
++ struct dwc_otg_hcd_iso_packet_desc *frame_desc;
++ dwc_otg_qtd_t *qtd;
++ dwc_otg_host_dma_desc_t *dma_desc;
++ uint16_t idx, inc, n_desc, ntd_max, max_xfer_size;
++
++ idx = qh->td_last;
++ inc = qh->interval;
++ n_desc = 0;
++
++ ntd_max = (max_desc_num(qh) + qh->interval - 1) / qh->interval;
++ if (skip_frames && !qh->channel)
++ ntd_max = ntd_max - skip_frames / qh->interval;
++
++ max_xfer_size =
++ (qh->dev_speed ==
++ DWC_OTG_EP_SPEED_HIGH) ? MAX_ISOC_XFER_SIZE_HS :
++ MAX_ISOC_XFER_SIZE_FS;
++
++ DWC_CIRCLEQ_FOREACH(qtd, &qh->qtd_list, qtd_list_entry) {
++ while ((qh->ntd < ntd_max)
++ && (qtd->isoc_frame_index_last <
++ qtd->urb->packet_count)) {
++
++ dma_desc = &qh->desc_list[idx];
++ dwc_memset(dma_desc, 0x00, sizeof(dwc_otg_host_dma_desc_t));
++
++ frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index_last];
++
++ if (frame_desc->length > max_xfer_size)
++ qh->n_bytes[idx] = max_xfer_size;
++ else
++ qh->n_bytes[idx] = frame_desc->length;
++ dma_desc->status.b_isoc.n_bytes = qh->n_bytes[idx];
++ dma_desc->status.b_isoc.a = 1;
++ dma_desc->status.b_isoc.sts = 0;
++
++ dma_desc->buf = qtd->urb->dma + frame_desc->offset;
++
++ qh->ntd++;
++
++ qtd->isoc_frame_index_last++;
++
++#ifdef ISOC_URB_GIVEBACK_ASAP
++ /*
++ * Set IOC for each descriptor corresponding to the
++ * last frame of the URB.
++ */
++ if (qtd->isoc_frame_index_last ==
++ qtd->urb->packet_count)
++ dma_desc->status.b_isoc.ioc = 1;
++
++#endif
++ idx = desclist_idx_inc(idx, inc, qh->dev_speed);
++ n_desc++;
++
++ }
++ qtd->in_process = 1;
++ }
++
++ qh->td_last = idx;
++
++#ifdef ISOC_URB_GIVEBACK_ASAP
++ /* Set IOC for the last descriptor if descriptor list is full */
++ if (qh->ntd == ntd_max) {
++ idx = desclist_idx_dec(qh->td_last, inc, qh->dev_speed);
++ qh->desc_list[idx].status.b_isoc.ioc = 1;
++ }
++#else
++ /*
++ * Set IOC bit only for one descriptor.
++ * Always try to be ahead of HW processing,
++ * i.e. on IOC generation driver activates next descriptors but
++ * core continues to process descriptors followed the one with IOC set.
++ */
++
++ if (n_desc > DESCNUM_THRESHOLD) {
++ /*
++ * Move IOC "up". Required even if there is only one QTD
++ * in the list, cause QTDs migth continue to be queued,
++ * but during the activation it was only one queued.
++ * Actually more than one QTD might be in the list if this function called
++ * from XferCompletion - QTDs was queued during HW processing of the previous
++ * descriptor chunk.
++ */
++ idx = dwc_desclist_idx_dec(idx, inc * ((qh->ntd + 1) / 2), qh->dev_speed);
++ } else {
++ /*
++ * Set the IOC for the latest descriptor
++ * if either number of descriptor is not greather than threshold
++ * or no more new descriptors activated.
++ */
++ idx = dwc_desclist_idx_dec(qh->td_last, inc, qh->dev_speed);
++ }
++
++ qh->desc_list[idx].status.b_isoc.ioc = 1;
++#endif
++}
++
++static void init_non_isoc_dma_desc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
++{
++
++ dwc_hc_t *hc;
++ dwc_otg_host_dma_desc_t *dma_desc;
++ dwc_otg_qtd_t *qtd;
++ int num_packets, len, n_desc = 0;
++
++ hc = qh->channel;
++
++ /*
++ * Start with hc->xfer_buff initialized in
++ * assign_and_init_hc(), then if SG transfer consists of multiple URBs,
++ * this pointer re-assigned to the buffer of the currently processed QTD.
++ * For non-SG request there is always one QTD active.
++ */
++
++ DWC_CIRCLEQ_FOREACH(qtd, &qh->qtd_list, qtd_list_entry) {
++
++ if (n_desc) {
++ /* SG request - more than 1 QTDs */
++ hc->xfer_buff = (uint8_t *)qtd->urb->dma + qtd->urb->actual_length;
++ hc->xfer_len = qtd->urb->length - qtd->urb->actual_length;
++ }
++
++ qtd->n_desc = 0;
++
++ do {
++ dma_desc = &qh->desc_list[n_desc];
++ len = hc->xfer_len;
++
++ if (len > MAX_DMA_DESC_SIZE)
++ len = MAX_DMA_DESC_SIZE - hc->max_packet + 1;
++
++ if (hc->ep_is_in) {
++ if (len > 0) {
++ num_packets = (len + hc->max_packet - 1) / hc->max_packet;
++ } else {
++ /* Need 1 packet for transfer length of 0. */
++ num_packets = 1;
++ }
++ /* Always program an integral # of max packets for IN transfers. */
++ len = num_packets * hc->max_packet;
++ }
++
++ dma_desc->status.b.n_bytes = len;
++
++ qh->n_bytes[n_desc] = len;
++
++ if ((qh->ep_type == UE_CONTROL)
++ && (qtd->control_phase == DWC_OTG_CONTROL_SETUP))
++ dma_desc->status.b.sup = 1; /* Setup Packet */
++
++ dma_desc->status.b.a = 1; /* Active descriptor */
++ dma_desc->status.b.sts = 0;
++
++ dma_desc->buf =
++ ((unsigned long)hc->xfer_buff & 0xffffffff);
++
++ /*
++ * Last descriptor(or single) of IN transfer
++ * with actual size less than MaxPacket.
++ */
++ if (len > hc->xfer_len) {
++ hc->xfer_len = 0;
++ } else {
++ hc->xfer_buff += len;
++ hc->xfer_len -= len;
++ }
++
++ qtd->n_desc++;
++ n_desc++;
++ }
++ while ((hc->xfer_len > 0) && (n_desc != MAX_DMA_DESC_NUM_GENERIC));
++
++
++ qtd->in_process = 1;
++
++ if (qh->ep_type == UE_CONTROL)
++ break;
++
++ if (n_desc == MAX_DMA_DESC_NUM_GENERIC)
++ break;
++ }
++
++ if (n_desc) {
++ /* Request Transfer Complete interrupt for the last descriptor */
++ qh->desc_list[n_desc - 1].status.b.ioc = 1;
++ /* End of List indicator */
++ qh->desc_list[n_desc - 1].status.b.eol = 1;
++
++ hc->ntd = n_desc;
++ }
++}
++
++/**
++ * For Control and Bulk endpoints initializes descriptor list
++ * and starts the transfer.
++ *
++ * For Interrupt and Isochronous endpoints initializes descriptor list
++ * then updates FrameList, marking appropriate entries as active.
++ * In case of Isochronous, the starting descriptor index is calculated based
++ * on the scheduled frame, but only on the first transfer descriptor within a session.
++ * Then starts the transfer via enabling the channel.
++ * For Isochronous endpoint the channel is not halted on XferComplete
++ * interrupt so remains assigned to the endpoint(QH) until session is done.
++ *
++ * @param hcd The HCD state structure for the DWC OTG controller.
++ * @param qh The QH to init.
++ *
++ * @return 0 if successful, negative error code otherwise.
++ */
++void dwc_otg_hcd_start_xfer_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
++{
++ /* Channel is already assigned */
++ dwc_hc_t *hc = qh->channel;
++ uint8_t skip_frames = 0;
++
++ switch (hc->ep_type) {
++ case DWC_OTG_EP_TYPE_CONTROL:
++ case DWC_OTG_EP_TYPE_BULK:
++ init_non_isoc_dma_desc(hcd, qh);
++
++ dwc_otg_hc_start_transfer_ddma(hcd->core_if, hc);
++ break;
++ case DWC_OTG_EP_TYPE_INTR:
++ init_non_isoc_dma_desc(hcd, qh);
++
++ update_frame_list(hcd, qh, 1);
++
++ dwc_otg_hc_start_transfer_ddma(hcd->core_if, hc);
++ break;
++ case DWC_OTG_EP_TYPE_ISOC:
++
++ if (!qh->ntd)
++ skip_frames = recalc_initial_desc_idx(hcd, qh);
++
++ init_isoc_dma_desc(hcd, qh, skip_frames);
++
++ if (!hc->xfer_started) {
++
++ update_frame_list(hcd, qh, 1);
++
++ /*
++ * Always set to max, instead of actual size.
++ * Otherwise ntd will be changed with
++ * channel being enabled. Not recommended.
++ *
++ */
++ hc->ntd = max_desc_num(qh);
++ /* Enable channel only once for ISOC */
++ dwc_otg_hc_start_transfer_ddma(hcd->core_if, hc);
++ }
++
++ break;
++ default:
++
++ break;
++ }
++}
++
++static void complete_isoc_xfer_ddma(dwc_otg_hcd_t * hcd,
++ dwc_hc_t * hc,
++ dwc_otg_hc_regs_t * hc_regs,
++ dwc_otg_halt_status_e halt_status)
++{
++ struct dwc_otg_hcd_iso_packet_desc *frame_desc;
++ dwc_otg_qtd_t *qtd, *qtd_tmp;
++ dwc_otg_qh_t *qh;
++ dwc_otg_host_dma_desc_t *dma_desc;
++ uint16_t idx, remain;
++ uint8_t urb_compl;
++
++ qh = hc->qh;
++ idx = qh->td_first;
++
++ if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) {
++ DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry)
++ qtd->in_process = 0;
++ return;
++ } else if ((halt_status == DWC_OTG_HC_XFER_AHB_ERR) ||
++ (halt_status == DWC_OTG_HC_XFER_BABBLE_ERR)) {
++ /*
++ * Channel is halted in these error cases.
++ * Considered as serious issues.
++ * Complete all URBs marking all frames as failed,
++ * irrespective whether some of the descriptors(frames) succeeded or no.
++ * Pass error code to completion routine as well, to
++ * update urb->status, some of class drivers might use it to stop
++ * queing transfer requests.
++ */
++ int err = (halt_status == DWC_OTG_HC_XFER_AHB_ERR)
++ ? (-DWC_E_IO)
++ : (-DWC_E_OVERFLOW);
++
++ DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry) {
++ for (idx = 0; idx < qtd->urb->packet_count; idx++) {
++ frame_desc = &qtd->urb->iso_descs[idx];
++ frame_desc->status = err;
++ }
++ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, err);
++ dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
++ }
++ return;
++ }
++
++ DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry) {
++
++ if (!qtd->in_process)
++ break;
++
++ urb_compl = 0;
++
++ do {
++
++ dma_desc = &qh->desc_list[idx];
++
++ frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
++ remain = hc->ep_is_in ? dma_desc->status.b_isoc.n_bytes : 0;
++
++ if (dma_desc->status.b_isoc.sts == DMA_DESC_STS_PKTERR) {
++ /*
++ * XactError or, unable to complete all the transactions
++ * in the scheduled micro-frame/frame,
++ * both indicated by DMA_DESC_STS_PKTERR.
++ */
++ qtd->urb->error_count++;
++ frame_desc->actual_length = qh->n_bytes[idx] - remain;
++ frame_desc->status = -DWC_E_PROTOCOL;
++ } else {
++ /* Success */
++
++ frame_desc->actual_length = qh->n_bytes[idx] - remain;
++ frame_desc->status = 0;
++ }
++
++ if (++qtd->isoc_frame_index == qtd->urb->packet_count) {
++ /*
++ * urb->status is not used for isoc transfers here.
++ * The individual frame_desc status are used instead.
++ */
++
++ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
++ dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
++
++ /*
++ * This check is necessary because urb_dequeue can be called
++ * from urb complete callback(sound driver example).
++ * All pending URBs are dequeued there, so no need for
++ * further processing.
++ */
++ if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) {
++ return;
++ }
++
++ urb_compl = 1;
++
++ }
++
++ qh->ntd--;
++
++ /* Stop if IOC requested descriptor reached */
++ if (dma_desc->status.b_isoc.ioc) {
++ idx = desclist_idx_inc(idx, qh->interval, hc->speed);
++ goto stop_scan;
++ }
++
++ idx = desclist_idx_inc(idx, qh->interval, hc->speed);
++
++ if (urb_compl)
++ break;
++ }
++ while (idx != qh->td_first);
++ }
++stop_scan:
++ qh->td_first = idx;
++}
++
++uint8_t update_non_isoc_urb_state_ddma(dwc_otg_hcd_t * hcd,
++ dwc_hc_t * hc,
++ dwc_otg_qtd_t * qtd,
++ dwc_otg_host_dma_desc_t * dma_desc,
++ dwc_otg_halt_status_e halt_status,
++ uint32_t n_bytes, uint8_t * xfer_done)
++{
++
++ uint16_t remain = hc->ep_is_in ? dma_desc->status.b.n_bytes : 0;
++ dwc_otg_hcd_urb_t *urb = qtd->urb;
++
++ if (halt_status == DWC_OTG_HC_XFER_AHB_ERR) {
++ urb->status = -DWC_E_IO;
++ return 1;
++ }
++ if (dma_desc->status.b.sts == DMA_DESC_STS_PKTERR) {
++ switch (halt_status) {
++ case DWC_OTG_HC_XFER_STALL:
++ urb->status = -DWC_E_PIPE;
++ break;
++ case DWC_OTG_HC_XFER_BABBLE_ERR:
++ urb->status = -DWC_E_OVERFLOW;
++ break;
++ case DWC_OTG_HC_XFER_XACT_ERR:
++ urb->status = -DWC_E_PROTOCOL;
++ break;
++ default:
++ DWC_ERROR("%s: Unhandled descriptor error status (%d)\n", __func__,
++ halt_status);
++ break;
++ }
++ return 1;
++ }
++
++ if (dma_desc->status.b.a == 1) {
++ DWC_DEBUGPL(DBG_HCDV,
++ "Active descriptor encountered on channel %d\n",
++ hc->hc_num);
++ return 0;
++ }
++
++ if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL) {
++ if (qtd->control_phase == DWC_OTG_CONTROL_DATA) {
++ urb->actual_length += n_bytes - remain;
++ if (remain || urb->actual_length == urb->length) {
++ /*
++ * For Control Data stage do not set urb->status=0 to prevent
++ * URB callback. Set it when Status phase done. See below.
++ */
++ *xfer_done = 1;
++ }
++
++ } else if (qtd->control_phase == DWC_OTG_CONTROL_STATUS) {
++ urb->status = 0;
++ *xfer_done = 1;
++ }
++ /* No handling for SETUP stage */
++ } else {
++ /* BULK and INTR */
++ urb->actual_length += n_bytes - remain;
++ if (remain || urb->actual_length == urb->length) {
++ urb->status = 0;
++ *xfer_done = 1;
++ }
++ }
++
++ return 0;
++}
++
++static void complete_non_isoc_xfer_ddma(dwc_otg_hcd_t * hcd,
++ dwc_hc_t * hc,
++ dwc_otg_hc_regs_t * hc_regs,
++ dwc_otg_halt_status_e halt_status)
++{
++ dwc_otg_hcd_urb_t *urb = NULL;
++ dwc_otg_qtd_t *qtd, *qtd_tmp;
++ dwc_otg_qh_t *qh;
++ dwc_otg_host_dma_desc_t *dma_desc;
++ uint32_t n_bytes, n_desc, i;
++ uint8_t failed = 0, xfer_done;
++
++ n_desc = 0;
++
++ qh = hc->qh;
++
++ if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) {
++ DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry) {
++ qtd->in_process = 0;
++ }
++ return;
++ }
++
++ DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry) {
++
++ urb = qtd->urb;
++
++ n_bytes = 0;
++ xfer_done = 0;
++
++ for (i = 0; i < qtd->n_desc; i++) {
++ dma_desc = &qh->desc_list[n_desc];
++
++ n_bytes = qh->n_bytes[n_desc];
++
++ failed =
++ update_non_isoc_urb_state_ddma(hcd, hc, qtd,
++ dma_desc,
++ halt_status, n_bytes,
++ &xfer_done);
++
++ if (failed
++ || (xfer_done
++ && (urb->status != -DWC_E_IN_PROGRESS))) {
++
++ hcd->fops->complete(hcd, urb->priv, urb,
++ urb->status);
++ dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
++
++ if (failed)
++ goto stop_scan;
++ } else if (qh->ep_type == UE_CONTROL) {
++ if (qtd->control_phase == DWC_OTG_CONTROL_SETUP) {
++ if (urb->length > 0) {
++ qtd->control_phase = DWC_OTG_CONTROL_DATA;
++ } else {
++ qtd->control_phase = DWC_OTG_CONTROL_STATUS;
++ }
++ DWC_DEBUGPL(DBG_HCDV, " Control setup transaction done\n");
++ } else if (qtd->control_phase == DWC_OTG_CONTROL_DATA) {
++ if (xfer_done) {
++ qtd->control_phase = DWC_OTG_CONTROL_STATUS;
++ DWC_DEBUGPL(DBG_HCDV, " Control data transfer done\n");
++ } else if (i + 1 == qtd->n_desc) {
++ /*
++ * Last descriptor for Control data stage which is
++ * not completed yet.
++ */
++ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
++ }
++ }
++ }
++
++ n_desc++;
++ }
++
++ }
++
++stop_scan:
++
++ if (qh->ep_type != UE_CONTROL) {
++ /*
++ * Resetting the data toggle for bulk
++ * and interrupt endpoints in case of stall. See handle_hc_stall_intr()
++ */
++ if (halt_status == DWC_OTG_HC_XFER_STALL)
++ qh->data_toggle = DWC_OTG_HC_PID_DATA0;
++ else
++ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
++ }
++
++ if (halt_status == DWC_OTG_HC_XFER_COMPLETE) {
++ hcint_data_t hcint;
++ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
++ if (hcint.b.nyet) {
++ /*
++ * Got a NYET on the last transaction of the transfer. It
++ * means that the endpoint should be in the PING state at the
++ * beginning of the next transfer.
++ */
++ qh->ping_state = 1;
++ clear_hc_int(hc_regs, nyet);
++ }
++
++ }
++
++}
++
++/**
++ * This function is called from interrupt handlers.
++ * Scans the descriptor list, updates URB's status and
++ * calls completion routine for the URB if it's done.
++ * Releases the channel to be used by other transfers.
++ * In case of Isochronous endpoint the channel is not halted until
++ * the end of the session, i.e. QTD list is empty.
++ * If periodic channel released the FrameList is updated accordingly.
++ *
++ * Calls transaction selection routines to activate pending transfers.
++ *
++ * @param hcd The HCD state structure for the DWC OTG controller.
++ * @param hc Host channel, the transfer is completed on.
++ * @param hc_regs Host channel registers.
++ * @param halt_status Reason the channel is being halted,
++ * or just XferComplete for isochronous transfer
++ */
++void dwc_otg_hcd_complete_xfer_ddma(dwc_otg_hcd_t * hcd,
++ dwc_hc_t * hc,
++ dwc_otg_hc_regs_t * hc_regs,
++ dwc_otg_halt_status_e halt_status)
++{
++ uint8_t continue_isoc_xfer = 0;
++ dwc_otg_transaction_type_e tr_type;
++ dwc_otg_qh_t *qh = hc->qh;
++
++ if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
++
++ complete_isoc_xfer_ddma(hcd, hc, hc_regs, halt_status);
++
++ /* Release the channel if halted or session completed */
++ if (halt_status != DWC_OTG_HC_XFER_COMPLETE ||
++ DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
++
++ /* Halt the channel if session completed */
++ if (halt_status == DWC_OTG_HC_XFER_COMPLETE) {
++ dwc_otg_hc_halt(hcd->core_if, hc, halt_status);
++ }
++
++ release_channel_ddma(hcd, qh);
++ dwc_otg_hcd_qh_remove(hcd, qh);
++ } else {
++ /* Keep in assigned schedule to continue transfer */
++ DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned,
++ &qh->qh_list_entry);
++ continue_isoc_xfer = 1;
++
++ }
++ /** @todo Consider the case when period exceeds FrameList size.
++ * Frame Rollover interrupt should be used.
++ */
++ } else {
++ /* Scan descriptor list to complete the URB(s), then release the channel */
++ complete_non_isoc_xfer_ddma(hcd, hc, hc_regs, halt_status);
++
++ release_channel_ddma(hcd, qh);
++ dwc_otg_hcd_qh_remove(hcd, qh);
++
++ if (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
++ /* Add back to inactive non-periodic schedule on normal completion */
++ dwc_otg_hcd_qh_add(hcd, qh);
++ }
++
++ }
++ tr_type = dwc_otg_hcd_select_transactions(hcd);
++ if (tr_type != DWC_OTG_TRANSACTION_NONE || continue_isoc_xfer) {
++ if (continue_isoc_xfer) {
++ if (tr_type == DWC_OTG_TRANSACTION_NONE) {
++ tr_type = DWC_OTG_TRANSACTION_PERIODIC;
++ } else if (tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC) {
++ tr_type = DWC_OTG_TRANSACTION_ALL;
++ }
++ }
++ dwc_otg_hcd_queue_transactions(hcd, tr_type);
++ }
++}
++
++#endif /* DWC_DEVICE_ONLY */
+diff -Nur linux-4.1.3/drivers/usb/host/dwc_otg/dwc_otg_hcd.h linux-xbian-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd.h
+--- linux-4.1.3/drivers/usb/host/dwc_otg/dwc_otg_hcd.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd.h 2015-07-28 01:20:58.449142252 +0200
+@@ -0,0 +1,862 @@
++/* ==========================================================================
++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.h $
++ * $Revision: #58 $
++ * $Date: 2011/09/15 $
++ * $Change: 1846647 $
++ *
++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++ * otherwise expressly agreed to in writing between Synopsys and you.
++ *
++ * The Software IS NOT an item of Licensed Software or Licensed Product under
++ * any End User Software License Agreement or Agreement for Licensed Product
++ * with Synopsys or any supplement thereto. You are permitted to use and
++ * redistribute this Software in source and binary forms, with or without
++ * modification, provided that redistributions of source code must retain this
++ * notice. You may not view, use, disclose, copy or distribute this file or
++ * any information contained herein except pursuant to this license grant from
++ * Synopsys. If you do not agree with this notice, including the disclaimer
++ * below, then you are not authorized to use the Software.
++ *
++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++ * DAMAGE.
++ * ========================================================================== */
++#ifndef DWC_DEVICE_ONLY
++#ifndef __DWC_HCD_H__
++#define __DWC_HCD_H__
++
++#include "dwc_otg_os_dep.h"
++#include "usb.h"
++#include "dwc_otg_hcd_if.h"
++#include "dwc_otg_core_if.h"
++#include "dwc_list.h"
++#include "dwc_otg_cil.h"
++#include "dwc_otg_fiq_fsm.h"
++
++
++/**
++ * @file
++ *
++ * This file contains the structures, constants, and interfaces for
++ * the Host Contoller Driver (HCD).
++ *
++ * The Host Controller Driver (HCD) is responsible for translating requests
++ * from the USB Driver into the appropriate actions on the DWC_otg controller.
++ * It isolates the USBD from the specifics of the controller by providing an
++ * API to the USBD.
++ */
++
++struct dwc_otg_hcd_pipe_info {
++ uint8_t dev_addr;
++ uint8_t ep_num;
++ uint8_t pipe_type;
++ uint8_t pipe_dir;
++ uint16_t mps;
++};
++
++struct dwc_otg_hcd_iso_packet_desc {
++ uint32_t offset;
++ uint32_t length;
++ uint32_t actual_length;
++ uint32_t status;
++};
++
++struct dwc_otg_qtd;
++
++struct dwc_otg_hcd_urb {
++ void *priv;
++ struct dwc_otg_qtd *qtd;
++ void *buf;
++ dwc_dma_t dma;
++ void *setup_packet;
++ dwc_dma_t setup_dma;
++ uint32_t length;
++ uint32_t actual_length;
++ uint32_t status;
++ uint32_t error_count;
++ uint32_t packet_count;
++ uint32_t flags;
++ uint16_t interval;
++ struct dwc_otg_hcd_pipe_info pipe_info;
++ struct dwc_otg_hcd_iso_packet_desc iso_descs[0];
++};
++
++static inline uint8_t dwc_otg_hcd_get_ep_num(struct dwc_otg_hcd_pipe_info *pipe)
++{
++ return pipe->ep_num;
++}
++
++static inline uint8_t dwc_otg_hcd_get_pipe_type(struct dwc_otg_hcd_pipe_info
++ *pipe)
++{
++ return pipe->pipe_type;
++}
++
++static inline uint16_t dwc_otg_hcd_get_mps(struct dwc_otg_hcd_pipe_info *pipe)
++{
++ return pipe->mps;
++}
++
++static inline uint8_t dwc_otg_hcd_get_dev_addr(struct dwc_otg_hcd_pipe_info
++ *pipe)
++{
++ return pipe->dev_addr;
++}
++
++static inline uint8_t dwc_otg_hcd_is_pipe_isoc(struct dwc_otg_hcd_pipe_info
++ *pipe)
++{
++ return (pipe->pipe_type == UE_ISOCHRONOUS);
++}
++
++static inline uint8_t dwc_otg_hcd_is_pipe_int(struct dwc_otg_hcd_pipe_info
++ *pipe)
++{
++ return (pipe->pipe_type == UE_INTERRUPT);
++}
++
++static inline uint8_t dwc_otg_hcd_is_pipe_bulk(struct dwc_otg_hcd_pipe_info
++ *pipe)
++{
++ return (pipe->pipe_type == UE_BULK);
++}
++
++static inline uint8_t dwc_otg_hcd_is_pipe_control(struct dwc_otg_hcd_pipe_info
++ *pipe)
++{
++ return (pipe->pipe_type == UE_CONTROL);
++}
++
++static inline uint8_t dwc_otg_hcd_is_pipe_in(struct dwc_otg_hcd_pipe_info *pipe)
++{
++ return (pipe->pipe_dir == UE_DIR_IN);
++}
++
++static inline uint8_t dwc_otg_hcd_is_pipe_out(struct dwc_otg_hcd_pipe_info
++ *pipe)
++{
++ return (!dwc_otg_hcd_is_pipe_in(pipe));
++}
++
++static inline void dwc_otg_hcd_fill_pipe(struct dwc_otg_hcd_pipe_info *pipe,
++ uint8_t devaddr, uint8_t ep_num,
++ uint8_t pipe_type, uint8_t pipe_dir,
++ uint16_t mps)
++{
++ pipe->dev_addr = devaddr;
++ pipe->ep_num = ep_num;
++ pipe->pipe_type = pipe_type;
++ pipe->pipe_dir = pipe_dir;
++ pipe->mps = mps;
++}
++
++/**
++ * Phases for control transfers.
++ */
++typedef enum dwc_otg_control_phase {
++ DWC_OTG_CONTROL_SETUP,
++ DWC_OTG_CONTROL_DATA,
++ DWC_OTG_CONTROL_STATUS
++} dwc_otg_control_phase_e;
++
++/** Transaction types. */
++typedef enum dwc_otg_transaction_type {
++ DWC_OTG_TRANSACTION_NONE = 0,
++ DWC_OTG_TRANSACTION_PERIODIC = 1,
++ DWC_OTG_TRANSACTION_NON_PERIODIC = 2,
++ DWC_OTG_TRANSACTION_ALL = DWC_OTG_TRANSACTION_PERIODIC + DWC_OTG_TRANSACTION_NON_PERIODIC
++} dwc_otg_transaction_type_e;
++
++struct dwc_otg_qh;
++
++/**
++ * A Queue Transfer Descriptor (QTD) holds the state of a bulk, control,
++ * interrupt, or isochronous transfer. A single QTD is created for each URB
++ * (of one of these types) submitted to the HCD. The transfer associated with
++ * a QTD may require one or multiple transactions.
++ *
++ * A QTD is linked to a Queue Head, which is entered in either the
++ * non-periodic or periodic schedule for execution. When a QTD is chosen for
++ * execution, some or all of its transactions may be executed. After
++ * execution, the state of the QTD is updated. The QTD may be retired if all
++ * its transactions are complete or if an error occurred. Otherwise, it
++ * remains in the schedule so more transactions can be executed later.
++ */
++typedef struct dwc_otg_qtd {
++ /**
++ * Determines the PID of the next data packet for the data phase of
++ * control transfers. Ignored for other transfer types.<br>
++ * One of the following values:
++ * - DWC_OTG_HC_PID_DATA0
++ * - DWC_OTG_HC_PID_DATA1
++ */
++ uint8_t data_toggle;
++
++ /** Current phase for control transfers (Setup, Data, or Status). */
++ dwc_otg_control_phase_e control_phase;
++
++ /** Keep track of the current split type
++ * for FS/LS endpoints on a HS Hub */
++ uint8_t complete_split;
++
++ /** How many bytes transferred during SSPLIT OUT */
++ uint32_t ssplit_out_xfer_count;
++
++ /**
++ * Holds the number of bus errors that have occurred for a transaction
++ * within this transfer.
++ */
++ uint8_t error_count;
++
++ /**
++ * Index of the next frame descriptor for an isochronous transfer. A
++ * frame descriptor describes the buffer position and length of the
++ * data to be transferred in the next scheduled (micro)frame of an
++ * isochronous transfer. It also holds status for that transaction.
++ * The frame index starts at 0.
++ */
++ uint16_t isoc_frame_index;
++
++ /** Position of the ISOC split on full/low speed */
++ uint8_t isoc_split_pos;
++
++ /** Position of the ISOC split in the buffer for the current frame */
++ uint16_t isoc_split_offset;
++
++ /** URB for this transfer */
++ struct dwc_otg_hcd_urb *urb;
++
++ struct dwc_otg_qh *qh;
++
++ /** This list of QTDs */
++ DWC_CIRCLEQ_ENTRY(dwc_otg_qtd) qtd_list_entry;
++
++ /** Indicates if this QTD is currently processed by HW. */
++ uint8_t in_process;
++
++ /** Number of DMA descriptors for this QTD */
++ uint8_t n_desc;
++
++ /**
++ * Last activated frame(packet) index.
++ * Used in Descriptor DMA mode only.
++ */
++ uint16_t isoc_frame_index_last;
++
++} dwc_otg_qtd_t;
++
++DWC_CIRCLEQ_HEAD(dwc_otg_qtd_list, dwc_otg_qtd);
++
++/**
++ * A Queue Head (QH) holds the static characteristics of an endpoint and
++ * maintains a list of transfers (QTDs) for that endpoint. A QH structure may
++ * be entered in either the non-periodic or periodic schedule.
++ */
++typedef struct dwc_otg_qh {
++ /**
++ * Endpoint type.
++ * One of the following values:
++ * - UE_CONTROL
++ * - UE_BULK
++ * - UE_INTERRUPT
++ * - UE_ISOCHRONOUS
++ */
++ uint8_t ep_type;
++ uint8_t ep_is_in;
++
++ /** wMaxPacketSize Field of Endpoint Descriptor. */
++ uint16_t maxp;
++
++ /**
++ * Device speed.
++ * One of the following values:
++ * - DWC_OTG_EP_SPEED_LOW
++ * - DWC_OTG_EP_SPEED_FULL
++ * - DWC_OTG_EP_SPEED_HIGH
++ */
++ uint8_t dev_speed;
++
++ /**
++ * Determines the PID of the next data packet for non-control
++ * transfers. Ignored for control transfers.<br>
++ * One of the following values:
++ * - DWC_OTG_HC_PID_DATA0
++ * - DWC_OTG_HC_PID_DATA1
++ */
++ uint8_t data_toggle;
++
++ /** Ping state if 1. */
++ uint8_t ping_state;
++
++ /**
++ * List of QTDs for this QH.
++ */
++ struct dwc_otg_qtd_list qtd_list;
++
++ /** Host channel currently processing transfers for this QH. */
++ struct dwc_hc *channel;
++
++ /** Full/low speed endpoint on high-speed hub requires split. */
++ uint8_t do_split;
++
++ /** @name Periodic schedule information */
++ /** @{ */
++
++ /** Bandwidth in microseconds per (micro)frame. */
++ uint16_t usecs;
++
++ /** Interval between transfers in (micro)frames. */
++ uint16_t interval;
++
++ /**
++ * (micro)frame to initialize a periodic transfer. The transfer
++ * executes in the following (micro)frame.
++ */
++ uint16_t sched_frame;
++
++ /*
++ ** Frame a NAK was received on this queue head, used to minimise NAK retransmission
++ */
++ uint16_t nak_frame;
++
++ /** (micro)frame at which last start split was initialized. */
++ uint16_t start_split_frame;
++
++ /** @} */
++
++ /**
++ * Used instead of original buffer if
++ * it(physical address) is not dword-aligned.
++ */
++ uint8_t *dw_align_buf;
++ dwc_dma_t dw_align_buf_dma;
++
++ /** Entry for QH in either the periodic or non-periodic schedule. */
++ dwc_list_link_t qh_list_entry;
++
++ /** @name Descriptor DMA support */
++ /** @{ */
++
++ /** Descriptor List. */
++ dwc_otg_host_dma_desc_t *desc_list;
++
++ /** Descriptor List physical address. */
++ dwc_dma_t desc_list_dma;
++
++ /**
++ * Xfer Bytes array.
++ * Each element corresponds to a descriptor and indicates
++ * original XferSize size value for the descriptor.
++ */
++ uint32_t *n_bytes;
++
++ /** Actual number of transfer descriptors in a list. */
++ uint16_t ntd;
++
++ /** First activated isochronous transfer descriptor index. */
++ uint8_t td_first;
++ /** Last activated isochronous transfer descriptor index. */
++ uint8_t td_last;
++
++ /** @} */
++
++
++ uint16_t speed;
++ uint16_t frame_usecs[8];
++
++ uint32_t skip_count;
++} dwc_otg_qh_t;
++
++DWC_CIRCLEQ_HEAD(hc_list, dwc_hc);
++
++typedef struct urb_tq_entry {
++ struct urb *urb;
++ DWC_TAILQ_ENTRY(urb_tq_entry) urb_tq_entries;
++} urb_tq_entry_t;
++
++DWC_TAILQ_HEAD(urb_list, urb_tq_entry);
++
++/**
++ * This structure holds the state of the HCD, including the non-periodic and
++ * periodic schedules.
++ */
++struct dwc_otg_hcd {
++ /** The DWC otg device pointer */
++ struct dwc_otg_device *otg_dev;
++ /** DWC OTG Core Interface Layer */
++ dwc_otg_core_if_t *core_if;
++
++ /** Function HCD driver callbacks */
++ struct dwc_otg_hcd_function_ops *fops;
++
++ /** Internal DWC HCD Flags */
++ volatile union dwc_otg_hcd_internal_flags {
++ uint32_t d32;
++ struct {
++ unsigned port_connect_status_change:1;
++ unsigned port_connect_status:1;
++ unsigned port_reset_change:1;
++ unsigned port_enable_change:1;
++ unsigned port_suspend_change:1;
++ unsigned port_over_current_change:1;
++ unsigned port_l1_change:1;
++ unsigned reserved:26;
++ } b;
++ } flags;
++
++ /**
++ * Inactive items in the non-periodic schedule. This is a list of
++ * Queue Heads. Transfers associated with these Queue Heads are not
++ * currently assigned to a host channel.
++ */
++ dwc_list_link_t non_periodic_sched_inactive;
++
++ /**
++ * Active items in the non-periodic schedule. This is a list of
++ * Queue Heads. Transfers associated with these Queue Heads are
++ * currently assigned to a host channel.
++ */
++ dwc_list_link_t non_periodic_sched_active;
++
++ /**
++ * Pointer to the next Queue Head to process in the active
++ * non-periodic schedule.
++ */
++ dwc_list_link_t *non_periodic_qh_ptr;
++
++ /**
++ * Inactive items in the periodic schedule. This is a list of QHs for
++ * periodic transfers that are _not_ scheduled for the next frame.
++ * Each QH in the list has an interval counter that determines when it
++ * needs to be scheduled for execution. This scheduling mechanism
++ * allows only a simple calculation for periodic bandwidth used (i.e.
++ * must assume that all periodic transfers may need to execute in the
++ * same frame). However, it greatly simplifies scheduling and should
++ * be sufficient for the vast majority of OTG hosts, which need to
++ * connect to a small number of peripherals at one time.
++ *
++ * Items move from this list to periodic_sched_ready when the QH
++ * interval counter is 0 at SOF.
++ */
++ dwc_list_link_t periodic_sched_inactive;
++
++ /**
++ * List of periodic QHs that are ready for execution in the next
++ * frame, but have not yet been assigned to host channels.
++ *
++ * Items move from this list to periodic_sched_assigned as host
++ * channels become available during the current frame.
++ */
++ dwc_list_link_t periodic_sched_ready;
++
++ /**
++ * List of periodic QHs to be executed in the next frame that are
++ * assigned to host channels.
++ *
++ * Items move from this list to periodic_sched_queued as the
++ * transactions for the QH are queued to the DWC_otg controller.
++ */
++ dwc_list_link_t periodic_sched_assigned;
++
++ /**
++ * List of periodic QHs that have been queued for execution.
++ *
++ * Items move from this list to either periodic_sched_inactive or
++ * periodic_sched_ready when the channel associated with the transfer
++ * is released. If the interval for the QH is 1, the item moves to
++ * periodic_sched_ready because it must be rescheduled for the next
++ * frame. Otherwise, the item moves to periodic_sched_inactive.
++ */
++ dwc_list_link_t periodic_sched_queued;
++
++ /**
++ * Total bandwidth claimed so far for periodic transfers. This value
++ * is in microseconds per (micro)frame. The assumption is that all
++ * periodic transfers may occur in the same (micro)frame.
++ */
++ uint16_t periodic_usecs;
++
++ /**
++ * Total bandwidth claimed so far for all periodic transfers
++ * in a frame.
++ * This will include a mixture of HS and FS transfers.
++ * Units are microseconds per (micro)frame.
++ * We have a budget per frame and have to schedule
++ * transactions accordingly.
++ * Watch out for the fact that things are actually scheduled for the
++ * "next frame".
++ */
++ uint16_t frame_usecs[8];
++
++
++ /**
++ * Frame number read from the core at SOF. The value ranges from 0 to
++ * DWC_HFNUM_MAX_FRNUM.
++ */
++ uint16_t frame_number;
++
++ /**
++ * Count of periodic QHs, if using several eps. For SOF enable/disable.
++ */
++ uint16_t periodic_qh_count;
++
++ /**
++ * Free host channels in the controller. This is a list of
++ * dwc_hc_t items.
++ */
++ struct hc_list free_hc_list;
++ /**
++ * Number of host channels assigned to periodic transfers. Currently
++ * assuming that there is a dedicated host channel for each periodic
++ * transaction and at least one host channel available for
++ * non-periodic transactions.
++ */
++ int periodic_channels; /* microframe_schedule==0 */
++
++ /**
++ * Number of host channels assigned to non-periodic transfers.
++ */
++ int non_periodic_channels; /* microframe_schedule==0 */
++
++ /**
++ * Number of host channels assigned to non-periodic transfers.
++ */
++ int available_host_channels;
++
++ /**
++ * Array of pointers to the host channel descriptors. Allows accessing
++ * a host channel descriptor given the host channel number. This is
++ * useful in interrupt handlers.
++ */
++ struct dwc_hc *hc_ptr_array[MAX_EPS_CHANNELS];
++
++ /**
++ * Buffer to use for any data received during the status phase of a
++ * control transfer. Normally no data is transferred during the status
++ * phase. This buffer is used as a bit bucket.
++ */
++ uint8_t *status_buf;
++
++ /**
++ * DMA address for status_buf.
++ */
++ dma_addr_t status_buf_dma;
++#define DWC_OTG_HCD_STATUS_BUF_SIZE 64
++
++ /**
++ * Connection timer. An OTG host must display a message if the device
++ * does not connect. Started when the VBus power is turned on via
++ * sysfs attribute "buspower".
++ */
++ dwc_timer_t *conn_timer;
++
++ /* Tasket to do a reset */
++ dwc_tasklet_t *reset_tasklet;
++
++ dwc_tasklet_t *completion_tasklet;
++ struct urb_list completed_urb_list;
++
++ /* */
++ dwc_spinlock_t *lock;
++ dwc_spinlock_t *channel_lock;
++ /**
++ * Private data that could be used by OS wrapper.
++ */
++ void *priv;
++
++ uint8_t otg_port;
++
++ /** Frame List */
++ uint32_t *frame_list;
++
++ /** Hub - Port assignment */
++ int hub_port[128];
++#ifdef FIQ_DEBUG
++ int hub_port_alloc[2048];
++#endif
++
++ /** Frame List DMA address */
++ dma_addr_t frame_list_dma;
++
++ struct fiq_stack *fiq_stack;
++ struct fiq_state *fiq_state;
++
++ /** Virtual address for split transaction DMA bounce buffers */
++ struct fiq_dma_blob *fiq_dmab;
++
++#ifdef DEBUG
++ uint32_t frrem_samples;
++ uint64_t frrem_accum;
++
++ uint32_t hfnum_7_samples_a;
++ uint64_t hfnum_7_frrem_accum_a;
++ uint32_t hfnum_0_samples_a;
++ uint64_t hfnum_0_frrem_accum_a;
++ uint32_t hfnum_other_samples_a;
++ uint64_t hfnum_other_frrem_accum_a;
++
++ uint32_t hfnum_7_samples_b;
++ uint64_t hfnum_7_frrem_accum_b;
++ uint32_t hfnum_0_samples_b;
++ uint64_t hfnum_0_frrem_accum_b;
++ uint32_t hfnum_other_samples_b;
++ uint64_t hfnum_other_frrem_accum_b;
++#endif
++};
++
++/** @name Transaction Execution Functions */
++/** @{ */
++extern dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t
++ * hcd);
++extern void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t * hcd,
++ dwc_otg_transaction_type_e tr_type);
++
++int dwc_otg_hcd_allocate_port(dwc_otg_hcd_t * hcd, dwc_otg_qh_t *qh);
++void dwc_otg_hcd_release_port(dwc_otg_hcd_t * dwc_otg_hcd, dwc_otg_qh_t *qh);
++
++extern int fiq_fsm_queue_transaction(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh);
++extern int fiq_fsm_transaction_suitable(dwc_otg_qh_t *qh);
++extern void dwc_otg_cleanup_fiq_channel(dwc_otg_hcd_t *hcd, uint32_t num);
++
++/** @} */
++
++/** @name Interrupt Handler Functions */
++/** @{ */
++extern int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd);
++extern int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t * dwc_otg_hcd);
++extern int32_t dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd_t *
++ dwc_otg_hcd);
++extern int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd_t *
++ dwc_otg_hcd);
++extern int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd_t *
++ dwc_otg_hcd);
++extern int32_t dwc_otg_hcd_handle_incomplete_periodic_intr(dwc_otg_hcd_t *
++ dwc_otg_hcd);
++extern int32_t dwc_otg_hcd_handle_port_intr(dwc_otg_hcd_t * dwc_otg_hcd);
++extern int32_t dwc_otg_hcd_handle_conn_id_status_change_intr(dwc_otg_hcd_t *
++ dwc_otg_hcd);
++extern int32_t dwc_otg_hcd_handle_disconnect_intr(dwc_otg_hcd_t * dwc_otg_hcd);
++extern int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t * dwc_otg_hcd);
++extern int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t * dwc_otg_hcd,
++ uint32_t num);
++extern int32_t dwc_otg_hcd_handle_session_req_intr(dwc_otg_hcd_t * dwc_otg_hcd);
++extern int32_t dwc_otg_hcd_handle_wakeup_detected_intr(dwc_otg_hcd_t *
++ dwc_otg_hcd);
++/** @} */
++
++/** @name Schedule Queue Functions */
++/** @{ */
++
++/* Implemented in dwc_otg_hcd_queue.c */
++extern dwc_otg_qh_t *dwc_otg_hcd_qh_create(dwc_otg_hcd_t * hcd,
++ dwc_otg_hcd_urb_t * urb, int atomic_alloc);
++extern void dwc_otg_hcd_qh_free(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
++extern int dwc_otg_hcd_qh_add(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
++extern void dwc_otg_hcd_qh_remove(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
++extern void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh,
++ int sched_csplit);
++
++/** Remove and free a QH */
++static inline void dwc_otg_hcd_qh_remove_and_free(dwc_otg_hcd_t * hcd,
++ dwc_otg_qh_t * qh)
++{
++ dwc_irqflags_t flags;
++ DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
++ dwc_otg_hcd_qh_remove(hcd, qh);
++ DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
++ dwc_otg_hcd_qh_free(hcd, qh);
++}
++
++/** Allocates memory for a QH structure.
++ * @return Returns the memory allocate or NULL on error. */
++static inline dwc_otg_qh_t *dwc_otg_hcd_qh_alloc(int atomic_alloc)
++{
++ if (atomic_alloc)
++ return (dwc_otg_qh_t *) DWC_ALLOC_ATOMIC(sizeof(dwc_otg_qh_t));
++ else
++ return (dwc_otg_qh_t *) DWC_ALLOC(sizeof(dwc_otg_qh_t));
++}
++
++extern dwc_otg_qtd_t *dwc_otg_hcd_qtd_create(dwc_otg_hcd_urb_t * urb,
++ int atomic_alloc);
++extern void dwc_otg_hcd_qtd_init(dwc_otg_qtd_t * qtd, dwc_otg_hcd_urb_t * urb);
++extern int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t * qtd, dwc_otg_hcd_t * dwc_otg_hcd,
++ dwc_otg_qh_t ** qh, int atomic_alloc);
++
++/** Allocates memory for a QTD structure.
++ * @return Returns the memory allocate or NULL on error. */
++static inline dwc_otg_qtd_t *dwc_otg_hcd_qtd_alloc(int atomic_alloc)
++{
++ if (atomic_alloc)
++ return (dwc_otg_qtd_t *) DWC_ALLOC_ATOMIC(sizeof(dwc_otg_qtd_t));
++ else
++ return (dwc_otg_qtd_t *) DWC_ALLOC(sizeof(dwc_otg_qtd_t));
++}
++
++/** Frees the memory for a QTD structure. QTD should already be removed from
++ * list.
++ * @param qtd QTD to free.*/
++static inline void dwc_otg_hcd_qtd_free(dwc_otg_qtd_t * qtd)
++{
++ DWC_FREE(qtd);
++}
++
++/** Removes a QTD from list.
++ * @param hcd HCD instance.
++ * @param qtd QTD to remove from list.
++ * @param qh QTD belongs to.
++ */
++static inline void dwc_otg_hcd_qtd_remove(dwc_otg_hcd_t * hcd,
++ dwc_otg_qtd_t * qtd,
++ dwc_otg_qh_t * qh)
++{
++ DWC_CIRCLEQ_REMOVE(&qh->qtd_list, qtd, qtd_list_entry);
++}
++
++/** Remove and free a QTD
++ * Need to disable IRQ and hold hcd lock while calling this function out of
++ * interrupt servicing chain */
++static inline void dwc_otg_hcd_qtd_remove_and_free(dwc_otg_hcd_t * hcd,
++ dwc_otg_qtd_t * qtd,
++ dwc_otg_qh_t * qh)
++{
++ dwc_otg_hcd_qtd_remove(hcd, qtd, qh);
++ dwc_otg_hcd_qtd_free(qtd);
++}
++
++/** @} */
++
++/** @name Descriptor DMA Supporting Functions */
++/** @{ */
++
++extern void dwc_otg_hcd_start_xfer_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
++extern void dwc_otg_hcd_complete_xfer_ddma(dwc_otg_hcd_t * hcd,
++ dwc_hc_t * hc,
++ dwc_otg_hc_regs_t * hc_regs,
++ dwc_otg_halt_status_e halt_status);
++
++extern int dwc_otg_hcd_qh_init_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
++extern void dwc_otg_hcd_qh_free_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
++
++/** @} */
++
++/** @name Internal Functions */
++/** @{ */
++dwc_otg_qh_t *dwc_urb_to_qh(dwc_otg_hcd_urb_t * urb);
++/** @} */
++
++#ifdef CONFIG_USB_DWC_OTG_LPM
++extern int dwc_otg_hcd_get_hc_for_lpm_tran(dwc_otg_hcd_t * hcd,
++ uint8_t devaddr);
++extern void dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd_t * hcd);
++#endif
++
++/** Gets the QH that contains the list_head */
++#define dwc_list_to_qh(_list_head_ptr_) container_of(_list_head_ptr_, dwc_otg_qh_t, qh_list_entry)
++
++/** Gets the QTD that contains the list_head */
++#define dwc_list_to_qtd(_list_head_ptr_) container_of(_list_head_ptr_, dwc_otg_qtd_t, qtd_list_entry)
++
++/** Check if QH is non-periodic */
++#define dwc_qh_is_non_per(_qh_ptr_) ((_qh_ptr_->ep_type == UE_BULK) || \
++ (_qh_ptr_->ep_type == UE_CONTROL))
++
++/** High bandwidth multiplier as encoded in highspeed endpoint descriptors */
++#define dwc_hb_mult(wMaxPacketSize) (1 + (((wMaxPacketSize) >> 11) & 0x03))
++
++/** Packet size for any kind of endpoint descriptor */
++#define dwc_max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
++
++/**
++ * Returns true if _frame1 is less than or equal to _frame2. The comparison is
++ * done modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the
++ * frame number when the max frame number is reached.
++ */
++static inline int dwc_frame_num_le(uint16_t frame1, uint16_t frame2)
++{
++ return ((frame2 - frame1) & DWC_HFNUM_MAX_FRNUM) <=
++ (DWC_HFNUM_MAX_FRNUM >> 1);
++}
++
++/**
++ * Returns true if _frame1 is greater than _frame2. The comparison is done
++ * modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the frame
++ * number when the max frame number is reached.
++ */
++static inline int dwc_frame_num_gt(uint16_t frame1, uint16_t frame2)
++{
++ return (frame1 != frame2) &&
++ (((frame1 - frame2) & DWC_HFNUM_MAX_FRNUM) <
++ (DWC_HFNUM_MAX_FRNUM >> 1));
++}
++
++/**
++ * Increments _frame by the amount specified by _inc. The addition is done
++ * modulo DWC_HFNUM_MAX_FRNUM. Returns the incremented value.
++ */
++static inline uint16_t dwc_frame_num_inc(uint16_t frame, uint16_t inc)
++{
++ return (frame + inc) & DWC_HFNUM_MAX_FRNUM;
++}
++
++static inline uint16_t dwc_full_frame_num(uint16_t frame)
++{
++ return (frame & DWC_HFNUM_MAX_FRNUM) >> 3;
++}
++
++static inline uint16_t dwc_micro_frame_num(uint16_t frame)
++{
++ return frame & 0x7;
++}
++
++void dwc_otg_hcd_save_data_toggle(dwc_hc_t * hc,
++ dwc_otg_hc_regs_t * hc_regs,
++ dwc_otg_qtd_t * qtd);
++
++#ifdef DEBUG
++/**
++ * Macro to sample the remaining PHY clocks left in the current frame. This
++ * may be used during debugging to determine the average time it takes to
++ * execute sections of code. There are two possible sample points, "a" and
++ * "b", so the _letter argument must be one of these values.
++ *
++ * To dump the average sample times, read the "hcd_frrem" sysfs attribute. For
++ * example, "cat /sys/devices/lm0/hcd_frrem".
++ */
++#define dwc_sample_frrem(_hcd, _qh, _letter) \
++{ \
++ hfnum_data_t hfnum; \
++ dwc_otg_qtd_t *qtd; \
++ qtd = list_entry(_qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry); \
++ if (usb_pipeint(qtd->urb->pipe) && _qh->start_split_frame != 0 && !qtd->complete_split) { \
++ hfnum.d32 = DWC_READ_REG32(&_hcd->core_if->host_if->host_global_regs->hfnum); \
++ switch (hfnum.b.frnum & 0x7) { \
++ case 7: \
++ _hcd->hfnum_7_samples_##_letter++; \
++ _hcd->hfnum_7_frrem_accum_##_letter += hfnum.b.frrem; \
++ break; \
++ case 0: \
++ _hcd->hfnum_0_samples_##_letter++; \
++ _hcd->hfnum_0_frrem_accum_##_letter += hfnum.b.frrem; \
++ break; \
++ default: \
++ _hcd->hfnum_other_samples_##_letter++; \
++ _hcd->hfnum_other_frrem_accum_##_letter += hfnum.b.frrem; \
++ break; \
++ } \
++ } \
++}
++#else
++#define dwc_sample_frrem(_hcd, _qh, _letter)
++#endif
++#endif
++#endif /* DWC_DEVICE_ONLY */
+diff -Nur linux-4.1.3/drivers/usb/host/dwc_otg/dwc_otg_hcd_if.h linux-xbian-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd_if.h
+--- linux-4.1.3/drivers/usb/host/dwc_otg/dwc_otg_hcd_if.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd_if.h 2015-07-28 01:20:58.449142252 +0200
+@@ -0,0 +1,417 @@
++/* ==========================================================================
++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_if.h $
++ * $Revision: #12 $
++ * $Date: 2011/10/26 $
++ * $Change: 1873028 $
++ *
++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++ * otherwise expressly agreed to in writing between Synopsys and you.
++ *
++ * The Software IS NOT an item of Licensed Software or Licensed Product under
++ * any End User Software License Agreement or Agreement for Licensed Product
++ * with Synopsys or any supplement thereto. You are permitted to use and
++ * redistribute this Software in source and binary forms, with or without
++ * modification, provided that redistributions of source code must retain this
++ * notice. You may not view, use, disclose, copy or distribute this file or
++ * any information contained herein except pursuant to this license grant from
++ * Synopsys. If you do not agree with this notice, including the disclaimer
++ * below, then you are not authorized to use the Software.
++ *
++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++ * DAMAGE.
++ * ========================================================================== */
++#ifndef DWC_DEVICE_ONLY
++#ifndef __DWC_HCD_IF_H__
++#define __DWC_HCD_IF_H__
++
++#include "dwc_otg_core_if.h"
++
++/** @file
++ * This file defines DWC_OTG HCD Core API.
++ */
++
++struct dwc_otg_hcd;
++typedef struct dwc_otg_hcd dwc_otg_hcd_t;
++
++struct dwc_otg_hcd_urb;
++typedef struct dwc_otg_hcd_urb dwc_otg_hcd_urb_t;
++
++/** @name HCD Function Driver Callbacks */
++/** @{ */
++
++/** This function is called whenever core switches to host mode. */
++typedef int (*dwc_otg_hcd_start_cb_t) (dwc_otg_hcd_t * hcd);
++
++/** This function is called when device has been disconnected */
++typedef int (*dwc_otg_hcd_disconnect_cb_t) (dwc_otg_hcd_t * hcd);
++
++/** Wrapper provides this function to HCD to core, so it can get hub information to which device is connected */
++typedef int (*dwc_otg_hcd_hub_info_from_urb_cb_t) (dwc_otg_hcd_t * hcd,
++ void *urb_handle,
++ uint32_t * hub_addr,
++ uint32_t * port_addr);
++/** Via this function HCD core gets device speed */
++typedef int (*dwc_otg_hcd_speed_from_urb_cb_t) (dwc_otg_hcd_t * hcd,
++ void *urb_handle);
++
++/** This function is called when urb is completed */
++typedef int (*dwc_otg_hcd_complete_urb_cb_t) (dwc_otg_hcd_t * hcd,
++ void *urb_handle,
++ dwc_otg_hcd_urb_t * dwc_otg_urb,
++ int32_t status);
++
++/** Via this function HCD core gets b_hnp_enable parameter */
++typedef int (*dwc_otg_hcd_get_b_hnp_enable) (dwc_otg_hcd_t * hcd);
++
++struct dwc_otg_hcd_function_ops {
++ dwc_otg_hcd_start_cb_t start;
++ dwc_otg_hcd_disconnect_cb_t disconnect;
++ dwc_otg_hcd_hub_info_from_urb_cb_t hub_info;
++ dwc_otg_hcd_speed_from_urb_cb_t speed;
++ dwc_otg_hcd_complete_urb_cb_t complete;
++ dwc_otg_hcd_get_b_hnp_enable get_b_hnp_enable;
++};
++/** @} */
++
++/** @name HCD Core API */
++/** @{ */
++/** This function allocates dwc_otg_hcd structure and returns pointer on it. */
++extern dwc_otg_hcd_t *dwc_otg_hcd_alloc_hcd(void);
++
++/** This function should be called to initiate HCD Core.
++ *
++ * @param hcd The HCD
++ * @param core_if The DWC_OTG Core
++ *
++ * Returns -DWC_E_NO_MEMORY if no enough memory.
++ * Returns 0 on success
++ */
++extern int dwc_otg_hcd_init(dwc_otg_hcd_t * hcd, dwc_otg_core_if_t * core_if);
++
++/** Frees HCD
++ *
++ * @param hcd The HCD
++ */
++extern void dwc_otg_hcd_remove(dwc_otg_hcd_t * hcd);
++
++/** This function should be called on every hardware interrupt.
++ *
++ * @param dwc_otg_hcd The HCD
++ *
++ * Returns non zero if interrupt is handled
++ * Return 0 if interrupt is not handled
++ */
++extern int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd);
++
++/** This function is used to handle the fast interrupt
++ *
++ */
++extern void __attribute__ ((naked)) dwc_otg_hcd_handle_fiq(void);
++
++/**
++ * Returns private data set by
++ * dwc_otg_hcd_set_priv_data function.
++ *
++ * @param hcd The HCD
++ */
++extern void *dwc_otg_hcd_get_priv_data(dwc_otg_hcd_t * hcd);
++
++/**
++ * Set private data.
++ *
++ * @param hcd The HCD
++ * @param priv_data pointer to be stored in private data
++ */
++extern void dwc_otg_hcd_set_priv_data(dwc_otg_hcd_t * hcd, void *priv_data);
++
++/**
++ * This function initializes the HCD Core.
++ *
++ * @param hcd The HCD
++ * @param fops The Function Driver Operations data structure containing pointers to all callbacks.
++ *
++ * Returns -DWC_E_NO_DEVICE if Core is currently is in device mode.
++ * Returns 0 on success
++ */
++extern int dwc_otg_hcd_start(dwc_otg_hcd_t * hcd,
++ struct dwc_otg_hcd_function_ops *fops);
++
++/**
++ * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
++ * stopped.
++ *
++ * @param hcd The HCD
++ */
++extern void dwc_otg_hcd_stop(dwc_otg_hcd_t * hcd);
++
++/**
++ * Handles hub class-specific requests.
++ *
++ * @param dwc_otg_hcd The HCD
++ * @param typeReq Request Type
++ * @param wValue wValue from control request
++ * @param wIndex wIndex from control request
++ * @param buf data buffer
++ * @param wLength data buffer length
++ *
++ * Returns -DWC_E_INVALID if invalid argument is passed
++ * Returns 0 on success
++ */
++extern int dwc_otg_hcd_hub_control(dwc_otg_hcd_t * dwc_otg_hcd,
++ uint16_t typeReq, uint16_t wValue,
++ uint16_t wIndex, uint8_t * buf,
++ uint16_t wLength);
++
++/**
++ * Returns otg port number.
++ *
++ * @param hcd The HCD
++ */
++extern uint32_t dwc_otg_hcd_otg_port(dwc_otg_hcd_t * hcd);
++
++/**
++ * Returns OTG version - either 1.3 or 2.0.
++ *
++ * @param core_if The core_if structure pointer
++ */
++extern uint16_t dwc_otg_get_otg_version(dwc_otg_core_if_t * core_if);
++
++/**
++ * Returns 1 if currently core is acting as B host, and 0 otherwise.
++ *
++ * @param hcd The HCD
++ */
++extern uint32_t dwc_otg_hcd_is_b_host(dwc_otg_hcd_t * hcd);
++
++/**
++ * Returns current frame number.
++ *
++ * @param hcd The HCD
++ */
++extern int dwc_otg_hcd_get_frame_number(dwc_otg_hcd_t * hcd);
++
++/**
++ * Dumps hcd state.
++ *
++ * @param hcd The HCD
++ */
++extern void dwc_otg_hcd_dump_state(dwc_otg_hcd_t * hcd);
++
++/**
++ * Dump the average frame remaining at SOF. This can be used to
++ * determine average interrupt latency. Frame remaining is also shown for
++ * start transfer and two additional sample points.
++ * Currently this function is not implemented.
++ *
++ * @param hcd The HCD
++ */
++extern void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t * hcd);
++
++/**
++ * Sends LPM transaction to the local device.
++ *
++ * @param hcd The HCD
++ * @param devaddr Device Address
++ * @param hird Host initiated resume duration
++ * @param bRemoteWake Value of bRemoteWake field in LPM transaction
++ *
++ * Returns negative value if sending LPM transaction was not succeeded.
++ * Returns 0 on success.
++ */
++extern int dwc_otg_hcd_send_lpm(dwc_otg_hcd_t * hcd, uint8_t devaddr,
++ uint8_t hird, uint8_t bRemoteWake);
++
++/* URB interface */
++
++/**
++ * Allocates memory for dwc_otg_hcd_urb structure.
++ * Allocated memory should be freed by call of DWC_FREE.
++ *
++ * @param hcd The HCD
++ * @param iso_desc_count Count of ISOC descriptors
++ * @param atomic_alloc Specefies whether to perform atomic allocation.
++ */
++extern dwc_otg_hcd_urb_t *dwc_otg_hcd_urb_alloc(dwc_otg_hcd_t * hcd,
++ int iso_desc_count,
++ int atomic_alloc);
++
++/**
++ * Set pipe information in URB.
++ *
++ * @param hcd_urb DWC_OTG URB
++ * @param devaddr Device Address
++ * @param ep_num Endpoint Number
++ * @param ep_type Endpoint Type
++ * @param ep_dir Endpoint Direction
++ * @param mps Max Packet Size
++ */
++extern void dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_hcd_urb_t * hcd_urb,
++ uint8_t devaddr, uint8_t ep_num,
++ uint8_t ep_type, uint8_t ep_dir,
++ uint16_t mps);
++
++/* Transfer flags */
++#define URB_GIVEBACK_ASAP 0x1
++#define URB_SEND_ZERO_PACKET 0x2
++
++/**
++ * Sets dwc_otg_hcd_urb parameters.
++ *
++ * @param urb DWC_OTG URB allocated by dwc_otg_hcd_urb_alloc function.
++ * @param urb_handle Unique handle for request, this will be passed back
++ * to function driver in completion callback.
++ * @param buf The buffer for the data
++ * @param dma The DMA buffer for the data
++ * @param buflen Transfer length
++ * @param sp Buffer for setup data
++ * @param sp_dma DMA address of setup data buffer
++ * @param flags Transfer flags
++ * @param interval Polling interval for interrupt or isochronous transfers.
++ */
++extern void dwc_otg_hcd_urb_set_params(dwc_otg_hcd_urb_t * urb,
++ void *urb_handle, void *buf,
++ dwc_dma_t dma, uint32_t buflen, void *sp,
++ dwc_dma_t sp_dma, uint32_t flags,
++ uint16_t interval);
++
++/** Gets status from dwc_otg_hcd_urb
++ *
++ * @param dwc_otg_urb DWC_OTG URB
++ */
++extern uint32_t dwc_otg_hcd_urb_get_status(dwc_otg_hcd_urb_t * dwc_otg_urb);
++
++/** Gets actual length from dwc_otg_hcd_urb
++ *
++ * @param dwc_otg_urb DWC_OTG URB
++ */
++extern uint32_t dwc_otg_hcd_urb_get_actual_length(dwc_otg_hcd_urb_t *
++ dwc_otg_urb);
++
++/** Gets error count from dwc_otg_hcd_urb. Only for ISOC URBs
++ *
++ * @param dwc_otg_urb DWC_OTG URB
++ */
++extern uint32_t dwc_otg_hcd_urb_get_error_count(dwc_otg_hcd_urb_t *
++ dwc_otg_urb);
++
++/** Set ISOC descriptor offset and length
++ *
++ * @param dwc_otg_urb DWC_OTG URB
++ * @param desc_num ISOC descriptor number
++ * @param offset Offset from beginig of buffer.
++ * @param length Transaction length
++ */
++extern void dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_hcd_urb_t * dwc_otg_urb,
++ int desc_num, uint32_t offset,
++ uint32_t length);
++
++/** Get status of ISOC descriptor, specified by desc_num
++ *
++ * @param dwc_otg_urb DWC_OTG URB
++ * @param desc_num ISOC descriptor number
++ */
++extern uint32_t dwc_otg_hcd_urb_get_iso_desc_status(dwc_otg_hcd_urb_t *
++ dwc_otg_urb, int desc_num);
++
++/** Get actual length of ISOC descriptor, specified by desc_num
++ *
++ * @param dwc_otg_urb DWC_OTG URB
++ * @param desc_num ISOC descriptor number
++ */
++extern uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length(dwc_otg_hcd_urb_t *
++ dwc_otg_urb,
++ int desc_num);
++
++/** Queue URB. After transfer is completes, the complete callback will be called with the URB status
++ *
++ * @param dwc_otg_hcd The HCD
++ * @param dwc_otg_urb DWC_OTG URB
++ * @param ep_handle Out parameter for returning endpoint handle
++ * @param atomic_alloc Flag to do atomic allocation if needed
++ *
++ * Returns -DWC_E_NO_DEVICE if no device is connected.
++ * Returns -DWC_E_NO_MEMORY if there is no enough memory.
++ * Returns 0 on success.
++ */
++extern int dwc_otg_hcd_urb_enqueue(dwc_otg_hcd_t * dwc_otg_hcd,
++ dwc_otg_hcd_urb_t * dwc_otg_urb,
++ void **ep_handle, int atomic_alloc);
++
++/** De-queue the specified URB
++ *
++ * @param dwc_otg_hcd The HCD
++ * @param dwc_otg_urb DWC_OTG URB
++ */
++extern int dwc_otg_hcd_urb_dequeue(dwc_otg_hcd_t * dwc_otg_hcd,
++ dwc_otg_hcd_urb_t * dwc_otg_urb);
++
++/** Frees resources in the DWC_otg controller related to a given endpoint.
++ * Any URBs for the endpoint must already be dequeued.
++ *
++ * @param hcd The HCD
++ * @param ep_handle Endpoint handle, returned by dwc_otg_hcd_urb_enqueue function
++ * @param retry Number of retries if there are queued transfers.
++ *
++ * Returns -DWC_E_INVALID if invalid arguments are passed.
++ * Returns 0 on success
++ */
++extern int dwc_otg_hcd_endpoint_disable(dwc_otg_hcd_t * hcd, void *ep_handle,
++ int retry);
++
++/* Resets the data toggle in qh structure. This function can be called from
++ * usb_clear_halt routine.
++ *
++ * @param hcd The HCD
++ * @param ep_handle Endpoint handle, returned by dwc_otg_hcd_urb_enqueue function
++ *
++ * Returns -DWC_E_INVALID if invalid arguments are passed.
++ * Returns 0 on success
++ */
++extern int dwc_otg_hcd_endpoint_reset(dwc_otg_hcd_t * hcd, void *ep_handle);
++
++/** Returns 1 if status of specified port is changed and 0 otherwise.
++ *
++ * @param hcd The HCD
++ * @param port Port number
++ */
++extern int dwc_otg_hcd_is_status_changed(dwc_otg_hcd_t * hcd, int port);
++
++/** Call this function to check if bandwidth was allocated for specified endpoint.
++ * Only for ISOC and INTERRUPT endpoints.
++ *
++ * @param hcd The HCD
++ * @param ep_handle Endpoint handle
++ */
++extern int dwc_otg_hcd_is_bandwidth_allocated(dwc_otg_hcd_t * hcd,
++ void *ep_handle);
++
++/** Call this function to check if bandwidth was freed for specified endpoint.
++ *
++ * @param hcd The HCD
++ * @param ep_handle Endpoint handle
++ */
++extern int dwc_otg_hcd_is_bandwidth_freed(dwc_otg_hcd_t * hcd, void *ep_handle);
++
++/** Returns bandwidth allocated for specified endpoint in microseconds.
++ * Only for ISOC and INTERRUPT endpoints.
++ *
++ * @param hcd The HCD
++ * @param ep_handle Endpoint handle
++ */
++extern uint8_t dwc_otg_hcd_get_ep_bandwidth(dwc_otg_hcd_t * hcd,
++ void *ep_handle);
++
++/** @} */
++
++#endif /* __DWC_HCD_IF_H__ */
++#endif /* DWC_DEVICE_ONLY */
+diff -Nur linux-4.1.3/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c linux-xbian-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c
+--- linux-4.1.3/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c 2015-07-28 01:20:58.449142252 +0200
+@@ -0,0 +1,2712 @@
++/* ==========================================================================
++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_intr.c $
++ * $Revision: #89 $
++ * $Date: 2011/10/20 $
++ * $Change: 1869487 $
++ *
++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++ * otherwise expressly agreed to in writing between Synopsys and you.
++ *
++ * The Software IS NOT an item of Licensed Software or Licensed Product under
++ * any End User Software License Agreement or Agreement for Licensed Product
++ * with Synopsys or any supplement thereto. You are permitted to use and
++ * redistribute this Software in source and binary forms, with or without
++ * modification, provided that redistributions of source code must retain this
++ * notice. You may not view, use, disclose, copy or distribute this file or
++ * any information contained herein except pursuant to this license grant from
++ * Synopsys. If you do not agree with this notice, including the disclaimer
++ * below, then you are not authorized to use the Software.
++ *
++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++ * DAMAGE.
++ * ========================================================================== */
++#ifndef DWC_DEVICE_ONLY
++
++#include "dwc_otg_hcd.h"
++#include "dwc_otg_regs.h"
++
++#include <linux/jiffies.h>
++#include <asm/fiq.h>
++
++
++extern bool microframe_schedule;
++
++/** @file
++ * This file contains the implementation of the HCD Interrupt handlers.
++ */
++
++int fiq_done, int_done;
++
++#ifdef FIQ_DEBUG
++char buffer[1000*16];
++int wptr;
++void notrace _fiq_print(FIQDBG_T dbg_lvl, char *fmt, ...)
++{
++ FIQDBG_T dbg_lvl_req = FIQDBG_PORTHUB;
++ va_list args;
++ char text[17];
++ hfnum_data_t hfnum = { .d32 = FIQ_READ(dwc_regs_base + 0x408) };
++
++ if(dbg_lvl & dbg_lvl_req || dbg_lvl == FIQDBG_ERR)
++ {
++ local_fiq_disable();
++ snprintf(text, 9, "%4d%d:%d ", hfnum.b.frnum/8, hfnum.b.frnum%8, 8 - hfnum.b.frrem/937);
++ va_start(args, fmt);
++ vsnprintf(text+8, 9, fmt, args);
++ va_end(args);
++
++ memcpy(buffer + wptr, text, 16);
++ wptr = (wptr + 16) % sizeof(buffer);
++ local_fiq_enable();
++ }
++}
++#endif
++
++/** This function handles interrupts for the HCD. */
++int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd)
++{
++ int retval = 0;
++ static int last_time;
++ dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
++ gintsts_data_t gintsts;
++ gintmsk_data_t gintmsk;
++ hfnum_data_t hfnum;
++ haintmsk_data_t haintmsk;
++
++#ifdef DEBUG
++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
++
++#endif
++
++ gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
++ gintmsk.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
++
++ /* Exit from ISR if core is hibernated */
++ if (core_if->hibernation_suspend == 1) {
++ goto exit_handler_routine;
++ }
++ DWC_SPINLOCK(dwc_otg_hcd->lock);
++ /* Check if HOST Mode */
++ if (dwc_otg_is_host_mode(core_if)) {
++ if (fiq_enable) {
++ local_fiq_disable();
++ fiq_fsm_spin_lock(&dwc_otg_hcd->fiq_state->lock);
++ /* Pull in from the FIQ's disabled mask */
++ gintmsk.d32 = gintmsk.d32 | ~(dwc_otg_hcd->fiq_state->gintmsk_saved.d32);
++ dwc_otg_hcd->fiq_state->gintmsk_saved.d32 = ~0;
++ }
++
++ if (fiq_fsm_enable && ( 0x0000FFFF & ~(dwc_otg_hcd->fiq_state->haintmsk_saved.b2.chint))) {
++ gintsts.b.hcintr = 1;
++ }
++
++ /* Danger will robinson: fake a SOF if necessary */
++ if (fiq_fsm_enable && (dwc_otg_hcd->fiq_state->gintmsk_saved.b.sofintr == 1)) {
++ gintsts.b.sofintr = 1;
++ }
++ gintsts.d32 &= gintmsk.d32;
++
++ if (fiq_enable) {
++ fiq_fsm_spin_unlock(&dwc_otg_hcd->fiq_state->lock);
++ local_fiq_enable();
++ }
++
++ if (!gintsts.d32) {
++ goto exit_handler_routine;
++ }
++
++#ifdef DEBUG
++ // We should be OK doing this because the common interrupts should already have been serviced
++ /* Don't print debug message in the interrupt handler on SOF */
++#ifndef DEBUG_SOF
++ if (gintsts.d32 != DWC_SOF_INTR_MASK)
++#endif
++ DWC_DEBUGPL(DBG_HCDI, "\n");
++#endif
++
++#ifdef DEBUG
++#ifndef DEBUG_SOF
++ if (gintsts.d32 != DWC_SOF_INTR_MASK)
++#endif
++ DWC_DEBUGPL(DBG_HCDI,
++ "DWC OTG HCD Interrupt Detected gintsts&gintmsk=0x%08x core_if=%p\n",
++ gintsts.d32, core_if);
++#endif
++ hfnum.d32 = DWC_READ_REG32(&dwc_otg_hcd->core_if->host_if->host_global_regs->hfnum);
++ if (gintsts.b.sofintr) {
++ retval |= dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd);
++ }
++
++ if (gintsts.b.rxstsqlvl) {
++ retval |=
++ dwc_otg_hcd_handle_rx_status_q_level_intr
++ (dwc_otg_hcd);
++ }
++ if (gintsts.b.nptxfempty) {
++ retval |=
++ dwc_otg_hcd_handle_np_tx_fifo_empty_intr
++ (dwc_otg_hcd);
++ }
++ if (gintsts.b.i2cintr) {
++ /** @todo Implement i2cintr handler. */
++ }
++ if (gintsts.b.portintr) {
++
++ gintmsk_data_t gintmsk = { .b.portintr = 1};
++ retval |= dwc_otg_hcd_handle_port_intr(dwc_otg_hcd);
++ if (fiq_enable) {
++ local_fiq_disable();
++ fiq_fsm_spin_lock(&dwc_otg_hcd->fiq_state->lock);
++ DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk, 0, gintmsk.d32);
++ fiq_fsm_spin_unlock(&dwc_otg_hcd->fiq_state->lock);
++ local_fiq_enable();
++ } else {
++ DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk, 0, gintmsk.d32);
++ }
++ }
++ if (gintsts.b.hcintr) {
++ retval |= dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd);
++ }
++ if (gintsts.b.ptxfempty) {
++ retval |=
++ dwc_otg_hcd_handle_perio_tx_fifo_empty_intr
++ (dwc_otg_hcd);
++ }
++#ifdef DEBUG
++#ifndef DEBUG_SOF
++ if (gintsts.d32 != DWC_SOF_INTR_MASK)
++#endif
++ {
++ DWC_DEBUGPL(DBG_HCDI,
++ "DWC OTG HCD Finished Servicing Interrupts\n");
++ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintsts=0x%08x\n",
++ DWC_READ_REG32(&global_regs->gintsts));
++ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintmsk=0x%08x\n",
++ DWC_READ_REG32(&global_regs->gintmsk));
++ }
++#endif
++
++#ifdef DEBUG
++#ifndef DEBUG_SOF
++ if (gintsts.d32 != DWC_SOF_INTR_MASK)
++#endif
++ DWC_DEBUGPL(DBG_HCDI, "\n");
++#endif
++
++ }
++
++exit_handler_routine:
++ if (fiq_enable) {
++ gintmsk_data_t gintmsk_new;
++ haintmsk_data_t haintmsk_new;
++ local_fiq_disable();
++ fiq_fsm_spin_lock(&dwc_otg_hcd->fiq_state->lock);
++ gintmsk_new.d32 = *(volatile uint32_t *)&dwc_otg_hcd->fiq_state->gintmsk_saved.d32;
++ if(fiq_fsm_enable)
++ haintmsk_new.d32 = *(volatile uint32_t *)&dwc_otg_hcd->fiq_state->haintmsk_saved.d32;
++ else
++ haintmsk_new.d32 = 0x0000FFFF;
++
++ /* The FIQ could have sneaked another interrupt in. If so, don't clear MPHI */
++ if ((gintmsk_new.d32 == ~0) && (haintmsk_new.d32 == 0x0000FFFF)) {
++ DWC_WRITE_REG32(dwc_otg_hcd->fiq_state->mphi_regs.intstat, (1<<16));
++ if (dwc_otg_hcd->fiq_state->mphi_int_count >= 50) {
++ fiq_print(FIQDBG_INT, dwc_otg_hcd->fiq_state, "MPHI CLR");
++ DWC_WRITE_REG32(dwc_otg_hcd->fiq_state->mphi_regs.ctrl, ((1<<31) + (1<<16)));
++ while (!(DWC_READ_REG32(dwc_otg_hcd->fiq_state->mphi_regs.ctrl) & (1 << 17)))
++ ;
++ DWC_WRITE_REG32(dwc_otg_hcd->fiq_state->mphi_regs.ctrl, (1<<31));
++ dwc_otg_hcd->fiq_state->mphi_int_count = 0;
++ }
++ int_done++;
++ }
++ haintmsk.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->haintmsk);
++ /* Re-enable interrupts that the FIQ masked (first time round) */
++ FIQ_WRITE(dwc_otg_hcd->fiq_state->dwc_regs_base + GINTMSK, gintmsk.d32);
++ fiq_fsm_spin_unlock(&dwc_otg_hcd->fiq_state->lock);
++ local_fiq_enable();
++
++ if ((jiffies / HZ) > last_time) {
++ //dwc_otg_qh_t *qh;
++ //dwc_list_link_t *cur;
++ /* Once a second output the fiq and irq numbers, useful for debug */
++ last_time = jiffies / HZ;
++ // DWC_WARN("np_kick=%d AHC=%d sched_frame=%d cur_frame=%d int_done=%d fiq_done=%d",
++ // dwc_otg_hcd->fiq_state->kick_np_queues, dwc_otg_hcd->available_host_channels,
++ // dwc_otg_hcd->fiq_state->next_sched_frame, hfnum.b.frnum, int_done, dwc_otg_hcd->fiq_state->fiq_done);
++ //printk(KERN_WARNING "Periodic queues:\n");
++ }
++ }
++
++ DWC_SPINUNLOCK(dwc_otg_hcd->lock);
++ return retval;
++}
++
++#ifdef DWC_TRACK_MISSED_SOFS
++
++#warning Compiling code to track missed SOFs
++#define FRAME_NUM_ARRAY_SIZE 1000
++/**
++ * This function is for debug only.
++ */
++static inline void track_missed_sofs(uint16_t curr_frame_number)
++{
++ static uint16_t frame_num_array[FRAME_NUM_ARRAY_SIZE];
++ static uint16_t last_frame_num_array[FRAME_NUM_ARRAY_SIZE];
++ static int frame_num_idx = 0;
++ static uint16_t last_frame_num = DWC_HFNUM_MAX_FRNUM;
++ static int dumped_frame_num_array = 0;
++
++ if (frame_num_idx < FRAME_NUM_ARRAY_SIZE) {
++ if (((last_frame_num + 1) & DWC_HFNUM_MAX_FRNUM) !=
++ curr_frame_number) {
++ frame_num_array[frame_num_idx] = curr_frame_number;
++ last_frame_num_array[frame_num_idx++] = last_frame_num;
++ }
++ } else if (!dumped_frame_num_array) {
++ int i;
++ DWC_PRINTF("Frame Last Frame\n");
++ DWC_PRINTF("----- ----------\n");
++ for (i = 0; i < FRAME_NUM_ARRAY_SIZE; i++) {
++ DWC_PRINTF("0x%04x 0x%04x\n",
++ frame_num_array[i], last_frame_num_array[i]);
++ }
++ dumped_frame_num_array = 1;
++ }
++ last_frame_num = curr_frame_number;
++}
++#endif
++
++/**
++ * Handles the start-of-frame interrupt in host mode. Non-periodic
++ * transactions may be queued to the DWC_otg controller for the current
++ * (micro)frame. Periodic transactions may be queued to the controller for the
++ * next (micro)frame.
++ */
++int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t * hcd)
++{
++ hfnum_data_t hfnum;
++ gintsts_data_t gintsts = { .d32 = 0 };
++ dwc_list_link_t *qh_entry;
++ dwc_otg_qh_t *qh;
++ dwc_otg_transaction_type_e tr_type;
++ int did_something = 0;
++ int32_t next_sched_frame = -1;
++
++ hfnum.d32 =
++ DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hfnum);
++
++#ifdef DEBUG_SOF
++ DWC_DEBUGPL(DBG_HCD, "--Start of Frame Interrupt--\n");
++#endif
++ hcd->frame_number = hfnum.b.frnum;
++
++#ifdef DEBUG
++ hcd->frrem_accum += hfnum.b.frrem;
++ hcd->frrem_samples++;
++#endif
++
++#ifdef DWC_TRACK_MISSED_SOFS
++ track_missed_sofs(hcd->frame_number);
++#endif
++ /* Determine whether any periodic QHs should be executed. */
++ qh_entry = DWC_LIST_FIRST(&hcd->periodic_sched_inactive);
++ while (qh_entry != &hcd->periodic_sched_inactive) {
++ qh = DWC_LIST_ENTRY(qh_entry, dwc_otg_qh_t, qh_list_entry);
++ qh_entry = qh_entry->next;
++ if (dwc_frame_num_le(qh->sched_frame, hcd->frame_number)) {
++
++ /*
++ * Move QH to the ready list to be executed next
++ * (micro)frame.
++ */
++ DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_ready,
++ &qh->qh_list_entry);
++
++ did_something = 1;
++ }
++ else
++ {
++ if(next_sched_frame < 0 || dwc_frame_num_le(qh->sched_frame, next_sched_frame))
++ {
++ next_sched_frame = qh->sched_frame;
++ }
++ }
++ }
++ if (fiq_enable)
++ hcd->fiq_state->next_sched_frame = next_sched_frame;
++
++ tr_type = dwc_otg_hcd_select_transactions(hcd);
++ if (tr_type != DWC_OTG_TRANSACTION_NONE) {
++ dwc_otg_hcd_queue_transactions(hcd, tr_type);
++ did_something = 1;
++ }
++
++ /* Clear interrupt - but do not trample on the FIQ sof */
++ if (!fiq_fsm_enable) {
++ gintsts.b.sofintr = 1;
++ DWC_WRITE_REG32(&hcd->core_if->core_global_regs->gintsts, gintsts.d32);
++ }
++ return 1;
++}
++
++/** Handles the Rx Status Queue Level Interrupt, which indicates that there is at
++ * least one packet in the Rx FIFO. The packets are moved from the FIFO to
++ * memory if the DWC_otg controller is operating in Slave mode. */
++int32_t dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd_t * dwc_otg_hcd)
++{
++ host_grxsts_data_t grxsts;
++ dwc_hc_t *hc = NULL;
++
++ DWC_DEBUGPL(DBG_HCD, "--RxStsQ Level Interrupt--\n");
++
++ grxsts.d32 =
++ DWC_READ_REG32(&dwc_otg_hcd->core_if->core_global_regs->grxstsp);
++
++ hc = dwc_otg_hcd->hc_ptr_array[grxsts.b.chnum];
++ if (!hc) {
++ DWC_ERROR("Unable to get corresponding channel\n");
++ return 0;
++ }
++
++ /* Packet Status */
++ DWC_DEBUGPL(DBG_HCDV, " Ch num = %d\n", grxsts.b.chnum);
++ DWC_DEBUGPL(DBG_HCDV, " Count = %d\n", grxsts.b.bcnt);
++ DWC_DEBUGPL(DBG_HCDV, " DPID = %d, hc.dpid = %d\n", grxsts.b.dpid,
++ hc->data_pid_start);
++ DWC_DEBUGPL(DBG_HCDV, " PStatus = %d\n", grxsts.b.pktsts);
++
++ switch (grxsts.b.pktsts) {
++ case DWC_GRXSTS_PKTSTS_IN:
++ /* Read the data into the host buffer. */
++ if (grxsts.b.bcnt > 0) {
++ dwc_otg_read_packet(dwc_otg_hcd->core_if,
++ hc->xfer_buff, grxsts.b.bcnt);
++
++ /* Update the HC fields for the next packet received. */
++ hc->xfer_count += grxsts.b.bcnt;
++ hc->xfer_buff += grxsts.b.bcnt;
++ }
++
++ case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
++ case DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR:
++ case DWC_GRXSTS_PKTSTS_CH_HALTED:
++ /* Handled in interrupt, just ignore data */
++ break;
++ default:
++ DWC_ERROR("RX_STS_Q Interrupt: Unknown status %d\n",
++ grxsts.b.pktsts);
++ break;
++ }
++
++ return 1;
++}
++
++/** This interrupt occurs when the non-periodic Tx FIFO is half-empty. More
++ * data packets may be written to the FIFO for OUT transfers. More requests
++ * may be written to the non-periodic request queue for IN transfers. This
++ * interrupt is enabled only in Slave mode. */
++int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd_t * dwc_otg_hcd)
++{
++ DWC_DEBUGPL(DBG_HCD, "--Non-Periodic TxFIFO Empty Interrupt--\n");
++ dwc_otg_hcd_queue_transactions(dwc_otg_hcd,
++ DWC_OTG_TRANSACTION_NON_PERIODIC);
++ return 1;
++}
++
++/** This interrupt occurs when the periodic Tx FIFO is half-empty. More data
++ * packets may be written to the FIFO for OUT transfers. More requests may be
++ * written to the periodic request queue for IN transfers. This interrupt is
++ * enabled only in Slave mode. */
++int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd_t * dwc_otg_hcd)
++{
++ DWC_DEBUGPL(DBG_HCD, "--Periodic TxFIFO Empty Interrupt--\n");
++ dwc_otg_hcd_queue_transactions(dwc_otg_hcd,
++ DWC_OTG_TRANSACTION_PERIODIC);
++ return 1;
++}
++
++/** There are multiple conditions that can cause a port interrupt. This function
++ * determines which interrupt conditions have occurred and handles them
++ * appropriately. */
++int32_t dwc_otg_hcd_handle_port_intr(dwc_otg_hcd_t * dwc_otg_hcd)
++{
++ int retval = 0;
++ hprt0_data_t hprt0;
++ hprt0_data_t hprt0_modify;
++
++ hprt0.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
++ hprt0_modify.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
++
++ /* Clear appropriate bits in HPRT0 to clear the interrupt bit in
++ * GINTSTS */
++
++ hprt0_modify.b.prtena = 0;
++ hprt0_modify.b.prtconndet = 0;
++ hprt0_modify.b.prtenchng = 0;
++ hprt0_modify.b.prtovrcurrchng = 0;
++
++ /* Port Connect Detected
++ * Set flag and clear if detected */
++ if (dwc_otg_hcd->core_if->hibernation_suspend == 1) {
++ // Dont modify port status if we are in hibernation state
++ hprt0_modify.b.prtconndet = 1;
++ hprt0_modify.b.prtenchng = 1;
++ DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0_modify.d32);
++ hprt0.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
++ return retval;
++ }
++
++ if (hprt0.b.prtconndet) {
++ /** @todo - check if steps performed in 'else' block should be perfromed regardles adp */
++ if (dwc_otg_hcd->core_if->adp_enable &&
++ dwc_otg_hcd->core_if->adp.vbuson_timer_started == 1) {
++ DWC_PRINTF("PORT CONNECT DETECTED ----------------\n");
++ DWC_TIMER_CANCEL(dwc_otg_hcd->core_if->adp.vbuson_timer);
++ dwc_otg_hcd->core_if->adp.vbuson_timer_started = 0;
++ /* TODO - check if this is required, as
++ * host initialization was already performed
++ * after initial ADP probing
++ */
++ /*dwc_otg_hcd->core_if->adp.vbuson_timer_started = 0;
++ dwc_otg_core_init(dwc_otg_hcd->core_if);
++ dwc_otg_enable_global_interrupts(dwc_otg_hcd->core_if);
++ cil_hcd_start(dwc_otg_hcd->core_if);*/
++ } else {
++
++ DWC_DEBUGPL(DBG_HCD, "--Port Interrupt HPRT0=0x%08x "
++ "Port Connect Detected--\n", hprt0.d32);
++ dwc_otg_hcd->flags.b.port_connect_status_change = 1;
++ dwc_otg_hcd->flags.b.port_connect_status = 1;
++ hprt0_modify.b.prtconndet = 1;
++
++ /* B-Device has connected, Delete the connection timer. */
++ DWC_TIMER_CANCEL(dwc_otg_hcd->conn_timer);
++ }
++ /* The Hub driver asserts a reset when it sees port connect
++ * status change flag */
++ retval |= 1;
++ }
++
++ /* Port Enable Changed
++ * Clear if detected - Set internal flag if disabled */
++ if (hprt0.b.prtenchng) {
++ DWC_DEBUGPL(DBG_HCD, " --Port Interrupt HPRT0=0x%08x "
++ "Port Enable Changed--\n", hprt0.d32);
++ hprt0_modify.b.prtenchng = 1;
++ if (hprt0.b.prtena == 1) {
++ hfir_data_t hfir;
++ int do_reset = 0;
++ dwc_otg_core_params_t *params =
++ dwc_otg_hcd->core_if->core_params;
++ dwc_otg_core_global_regs_t *global_regs =
++ dwc_otg_hcd->core_if->core_global_regs;
++ dwc_otg_host_if_t *host_if =
++ dwc_otg_hcd->core_if->host_if;
++
++ /* Every time when port enables calculate
++ * HFIR.FrInterval
++ */
++ hfir.d32 = DWC_READ_REG32(&host_if->host_global_regs->hfir);
++ hfir.b.frint = calc_frame_interval(dwc_otg_hcd->core_if);
++ DWC_WRITE_REG32(&host_if->host_global_regs->hfir, hfir.d32);
++
++ /* Check if we need to adjust the PHY clock speed for
++ * low power and adjust it */
++ if (params->host_support_fs_ls_low_power) {
++ gusbcfg_data_t usbcfg;
++
++ usbcfg.d32 =
++ DWC_READ_REG32(&global_regs->gusbcfg);
++
++ if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED
++ || hprt0.b.prtspd ==
++ DWC_HPRT0_PRTSPD_FULL_SPEED) {
++ /*
++ * Low power
++ */
++ hcfg_data_t hcfg;
++ if (usbcfg.b.phylpwrclksel == 0) {
++ /* Set PHY low power clock select for FS/LS devices */
++ usbcfg.b.phylpwrclksel = 1;
++ DWC_WRITE_REG32
++ (&global_regs->gusbcfg,
++ usbcfg.d32);
++ do_reset = 1;
++ }
++
++ hcfg.d32 =
++ DWC_READ_REG32
++ (&host_if->host_global_regs->hcfg);
++
++ if (hprt0.b.prtspd ==
++ DWC_HPRT0_PRTSPD_LOW_SPEED
++ && params->host_ls_low_power_phy_clk
++ ==
++ DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ)
++ {
++ /* 6 MHZ */
++ DWC_DEBUGPL(DBG_CIL,
++ "FS_PHY programming HCFG to 6 MHz (Low Power)\n");
++ if (hcfg.b.fslspclksel !=
++ DWC_HCFG_6_MHZ) {
++ hcfg.b.fslspclksel =
++ DWC_HCFG_6_MHZ;
++ DWC_WRITE_REG32
++ (&host_if->host_global_regs->hcfg,
++ hcfg.d32);
++ do_reset = 1;
++ }
++ } else {
++ /* 48 MHZ */
++ DWC_DEBUGPL(DBG_CIL,
++ "FS_PHY programming HCFG to 48 MHz ()\n");
++ if (hcfg.b.fslspclksel !=
++ DWC_HCFG_48_MHZ) {
++ hcfg.b.fslspclksel =
++ DWC_HCFG_48_MHZ;
++ DWC_WRITE_REG32
++ (&host_if->host_global_regs->hcfg,
++ hcfg.d32);
++ do_reset = 1;
++ }
++ }
++ } else {
++ /*
++ * Not low power
++ */
++ if (usbcfg.b.phylpwrclksel == 1) {
++ usbcfg.b.phylpwrclksel = 0;
++ DWC_WRITE_REG32
++ (&global_regs->gusbcfg,
++ usbcfg.d32);
++ do_reset = 1;
++ }
++ }
++
++ if (do_reset) {
++ DWC_TASK_SCHEDULE(dwc_otg_hcd->reset_tasklet);
++ }
++ }
++
++ if (!do_reset) {
++ /* Port has been enabled set the reset change flag */
++ dwc_otg_hcd->flags.b.port_reset_change = 1;
++ }
++ } else {
++ dwc_otg_hcd->flags.b.port_enable_change = 1;
++ }
++ retval |= 1;
++ }
++
++ /** Overcurrent Change Interrupt */
++ if (hprt0.b.prtovrcurrchng) {
++ DWC_DEBUGPL(DBG_HCD, " --Port Interrupt HPRT0=0x%08x "
++ "Port Overcurrent Changed--\n", hprt0.d32);
++ dwc_otg_hcd->flags.b.port_over_current_change = 1;
++ hprt0_modify.b.prtovrcurrchng = 1;
++ retval |= 1;
++ }
++
++ /* Clear Port Interrupts */
++ DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0_modify.d32);
++
++ return retval;
++}
++
++/** This interrupt indicates that one or more host channels has a pending
++ * interrupt. There are multiple conditions that can cause each host channel
++ * interrupt. This function determines which conditions have occurred for each
++ * host channel interrupt and handles them appropriately. */
++int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t * dwc_otg_hcd)
++{
++ int i;
++ int retval = 0;
++ haint_data_t haint = { .d32 = 0 } ;
++
++ /* Clear appropriate bits in HCINTn to clear the interrupt bit in
++ * GINTSTS */
++
++ if (!fiq_fsm_enable)
++ haint.d32 = dwc_otg_read_host_all_channels_intr(dwc_otg_hcd->core_if);
++
++ // Overwrite with saved interrupts from fiq handler
++ if(fiq_fsm_enable)
++ {
++ /* check the mask? */
++ local_fiq_disable();
++ fiq_fsm_spin_lock(&dwc_otg_hcd->fiq_state->lock);
++ haint.b2.chint |= ~(dwc_otg_hcd->fiq_state->haintmsk_saved.b2.chint);
++ dwc_otg_hcd->fiq_state->haintmsk_saved.b2.chint = ~0;
++ fiq_fsm_spin_unlock(&dwc_otg_hcd->fiq_state->lock);
++ local_fiq_enable();
++ }
++
++ for (i = 0; i < dwc_otg_hcd->core_if->core_params->host_channels; i++) {
++ if (haint.b2.chint & (1 << i)) {
++ retval |= dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd, i);
++ }
++ }
++
++ return retval;
++}
++
++/**
++ * Gets the actual length of a transfer after the transfer halts. _halt_status
++ * holds the reason for the halt.
++ *
++ * For IN transfers where halt_status is DWC_OTG_HC_XFER_COMPLETE,
++ * *short_read is set to 1 upon return if less than the requested
++ * number of bytes were transferred. Otherwise, *short_read is set to 0 upon
++ * return. short_read may also be NULL on entry, in which case it remains
++ * unchanged.
++ */
++static uint32_t get_actual_xfer_length(dwc_hc_t * hc,
++ dwc_otg_hc_regs_t * hc_regs,
++ dwc_otg_qtd_t * qtd,
++ dwc_otg_halt_status_e halt_status,
++ int *short_read)
++{
++ hctsiz_data_t hctsiz;
++ uint32_t length;
++
++ if (short_read != NULL) {
++ *short_read = 0;
++ }
++ hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
++
++ if (halt_status == DWC_OTG_HC_XFER_COMPLETE) {
++ if (hc->ep_is_in) {
++ length = hc->xfer_len - hctsiz.b.xfersize;
++ if (short_read != NULL) {
++ *short_read = (hctsiz.b.xfersize != 0);
++ }
++ } else if (hc->qh->do_split) {
++ //length = split_out_xfersize[hc->hc_num];
++ length = qtd->ssplit_out_xfer_count;
++ } else {
++ length = hc->xfer_len;
++ }
++ } else {
++ /*
++ * Must use the hctsiz.pktcnt field to determine how much data
++ * has been transferred. This field reflects the number of
++ * packets that have been transferred via the USB. This is
++ * always an integral number of packets if the transfer was
++ * halted before its normal completion. (Can't use the
++ * hctsiz.xfersize field because that reflects the number of
++ * bytes transferred via the AHB, not the USB).
++ */
++ length =
++ (hc->start_pkt_count - hctsiz.b.pktcnt) * hc->max_packet;
++ }
++
++ return length;
++}
++
++/**
++ * Updates the state of the URB after a Transfer Complete interrupt on the
++ * host channel. Updates the actual_length field of the URB based on the
++ * number of bytes transferred via the host channel. Sets the URB status
++ * if the data transfer is finished.
++ *
++ * @return 1 if the data transfer specified by the URB is completely finished,
++ * 0 otherwise.
++ */
++static int update_urb_state_xfer_comp(dwc_hc_t * hc,
++ dwc_otg_hc_regs_t * hc_regs,
++ dwc_otg_hcd_urb_t * urb,
++ dwc_otg_qtd_t * qtd)
++{
++ int xfer_done = 0;
++ int short_read = 0;
++
++ int xfer_length;
++
++ xfer_length = get_actual_xfer_length(hc, hc_regs, qtd,
++ DWC_OTG_HC_XFER_COMPLETE,
++ &short_read);
++
++ /* non DWORD-aligned buffer case handling. */
++ if (hc->align_buff && xfer_length && hc->ep_is_in) {
++ dwc_memcpy(urb->buf + urb->actual_length, hc->qh->dw_align_buf,
++ xfer_length);
++ }
++
++ urb->actual_length += xfer_length;
++
++ if (xfer_length && (hc->ep_type == DWC_OTG_EP_TYPE_BULK) &&
++ (urb->flags & URB_SEND_ZERO_PACKET)
++ && (urb->actual_length == urb->length)
++ && !(urb->length % hc->max_packet)) {
++ xfer_done = 0;
++ } else if (short_read || urb->actual_length >= urb->length) {
++ xfer_done = 1;
++ urb->status = 0;
++ }
++
++#ifdef DEBUG
++ {
++ hctsiz_data_t hctsiz;
++ hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
++ DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n",
++ __func__, (hc->ep_is_in ? "IN" : "OUT"),
++ hc->hc_num);
++ DWC_DEBUGPL(DBG_HCDV, " hc->xfer_len %d\n", hc->xfer_len);
++ DWC_DEBUGPL(DBG_HCDV, " hctsiz.xfersize %d\n",
++ hctsiz.b.xfersize);
++ DWC_DEBUGPL(DBG_HCDV, " urb->transfer_buffer_length %d\n",
++ urb->length);
++ DWC_DEBUGPL(DBG_HCDV, " urb->actual_length %d\n",
++ urb->actual_length);
++ DWC_DEBUGPL(DBG_HCDV, " short_read %d, xfer_done %d\n",
++ short_read, xfer_done);
++ }
++#endif
++
++ return xfer_done;
++}
++
++/*
++ * Save the starting data toggle for the next transfer. The data toggle is
++ * saved in the QH for non-control transfers and it's saved in the QTD for
++ * control transfers.
++ */
++void dwc_otg_hcd_save_data_toggle(dwc_hc_t * hc,
++ dwc_otg_hc_regs_t * hc_regs, dwc_otg_qtd_t * qtd)
++{
++ hctsiz_data_t hctsiz;
++ hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
++
++ if (hc->ep_type != DWC_OTG_EP_TYPE_CONTROL) {
++ dwc_otg_qh_t *qh = hc->qh;
++ if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) {
++ qh->data_toggle = DWC_OTG_HC_PID_DATA0;
++ } else {
++ qh->data_toggle = DWC_OTG_HC_PID_DATA1;
++ }
++ } else {
++ if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) {
++ qtd->data_toggle = DWC_OTG_HC_PID_DATA0;
++ } else {
++ qtd->data_toggle = DWC_OTG_HC_PID_DATA1;
++ }
++ }
++}
++
++/**
++ * Updates the state of an Isochronous URB when the transfer is stopped for
++ * any reason. The fields of the current entry in the frame descriptor array
++ * are set based on the transfer state and the input _halt_status. Completes
++ * the Isochronous URB if all the URB frames have been completed.
++ *
++ * @return DWC_OTG_HC_XFER_COMPLETE if there are more frames remaining to be
++ * transferred in the URB. Otherwise return DWC_OTG_HC_XFER_URB_COMPLETE.
++ */
++static dwc_otg_halt_status_e
++update_isoc_urb_state(dwc_otg_hcd_t * hcd,
++ dwc_hc_t * hc,
++ dwc_otg_hc_regs_t * hc_regs,
++ dwc_otg_qtd_t * qtd, dwc_otg_halt_status_e halt_status)
++{
++ dwc_otg_hcd_urb_t *urb = qtd->urb;
++ dwc_otg_halt_status_e ret_val = halt_status;
++ struct dwc_otg_hcd_iso_packet_desc *frame_desc;
++
++ frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
++ switch (halt_status) {
++ case DWC_OTG_HC_XFER_COMPLETE:
++ frame_desc->status = 0;
++ frame_desc->actual_length =
++ get_actual_xfer_length(hc, hc_regs, qtd, halt_status, NULL);
++
++ /* non DWORD-aligned buffer case handling. */
++ if (hc->align_buff && frame_desc->actual_length && hc->ep_is_in) {
++ dwc_memcpy(urb->buf + frame_desc->offset + qtd->isoc_split_offset,
++ hc->qh->dw_align_buf, frame_desc->actual_length);
++ }
++
++ break;
++ case DWC_OTG_HC_XFER_FRAME_OVERRUN:
++ urb->error_count++;
++ if (hc->ep_is_in) {
++ frame_desc->status = -DWC_E_NO_STREAM_RES;
++ } else {
++ frame_desc->status = -DWC_E_COMMUNICATION;
++ }
++ frame_desc->actual_length = 0;
++ break;
++ case DWC_OTG_HC_XFER_BABBLE_ERR:
++ urb->error_count++;
++ frame_desc->status = -DWC_E_OVERFLOW;
++ /* Don't need to update actual_length in this case. */
++ break;
++ case DWC_OTG_HC_XFER_XACT_ERR:
++ urb->error_count++;
++ frame_desc->status = -DWC_E_PROTOCOL;
++ frame_desc->actual_length =
++ get_actual_xfer_length(hc, hc_regs, qtd, halt_status, NULL);
++
++ /* non DWORD-aligned buffer case handling. */
++ if (hc->align_buff && frame_desc->actual_length && hc->ep_is_in) {
++ dwc_memcpy(urb->buf + frame_desc->offset + qtd->isoc_split_offset,
++ hc->qh->dw_align_buf, frame_desc->actual_length);
++ }
++ /* Skip whole frame */
++ if (hc->qh->do_split && (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) &&
++ hc->ep_is_in && hcd->core_if->dma_enable) {
++ qtd->complete_split = 0;
++ qtd->isoc_split_offset = 0;
++ }
++
++ break;
++ default:
++ DWC_ASSERT(1, "Unhandled _halt_status (%d)\n", halt_status);
++ break;
++ }
++ if (++qtd->isoc_frame_index == urb->packet_count) {
++ /*
++ * urb->status is not used for isoc transfers.
++ * The individual frame_desc statuses are used instead.
++ */
++ hcd->fops->complete(hcd, urb->priv, urb, 0);
++ ret_val = DWC_OTG_HC_XFER_URB_COMPLETE;
++ } else {
++ ret_val = DWC_OTG_HC_XFER_COMPLETE;
++ }
++ return ret_val;
++}
++
++/**
++ * Frees the first QTD in the QH's list if free_qtd is 1. For non-periodic
++ * QHs, removes the QH from the active non-periodic schedule. If any QTDs are
++ * still linked to the QH, the QH is added to the end of the inactive
++ * non-periodic schedule. For periodic QHs, removes the QH from the periodic
++ * schedule if no more QTDs are linked to the QH.
++ */
++static void deactivate_qh(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, int free_qtd)
++{
++ int continue_split = 0;
++ dwc_otg_qtd_t *qtd;
++
++ DWC_DEBUGPL(DBG_HCDV, " %s(%p,%p,%d)\n", __func__, hcd, qh, free_qtd);
++
++ qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
++
++ if (qtd->complete_split) {
++ continue_split = 1;
++ } else if (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_MID ||
++ qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_END) {
++ continue_split = 1;
++ }
++
++ if (free_qtd) {
++ dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
++ continue_split = 0;
++ }
++
++ qh->channel = NULL;
++ dwc_otg_hcd_qh_deactivate(hcd, qh, continue_split);
++}
++
++/**
++ * Releases a host channel for use by other transfers. Attempts to select and
++ * queue more transactions since at least one host channel is available.
++ *
++ * @param hcd The HCD state structure.
++ * @param hc The host channel to release.
++ * @param qtd The QTD associated with the host channel. This QTD may be freed
++ * if the transfer is complete or an error has occurred.
++ * @param halt_status Reason the channel is being released. This status
++ * determines the actions taken by this function.
++ */
++static void release_channel(dwc_otg_hcd_t * hcd,
++ dwc_hc_t * hc,
++ dwc_otg_qtd_t * qtd,
++ dwc_otg_halt_status_e halt_status)
++{
++ dwc_otg_transaction_type_e tr_type;
++ int free_qtd;
++ dwc_irqflags_t flags;
++ dwc_spinlock_t *channel_lock = hcd->channel_lock;
++
++ int hog_port = 0;
++
++ DWC_DEBUGPL(DBG_HCDV, " %s: channel %d, halt_status %d, xfer_len %d\n",
++ __func__, hc->hc_num, halt_status, hc->xfer_len);
++
++ if(fiq_fsm_enable && hc->do_split) {
++ if(!hc->ep_is_in && hc->ep_type == UE_ISOCHRONOUS) {
++ if(hc->xact_pos == DWC_HCSPLIT_XACTPOS_MID ||
++ hc->xact_pos == DWC_HCSPLIT_XACTPOS_BEGIN) {
++ hog_port = 0;
++ }
++ }
++ }
++
++ switch (halt_status) {
++ case DWC_OTG_HC_XFER_URB_COMPLETE:
++ free_qtd = 1;
++ break;
++ case DWC_OTG_HC_XFER_AHB_ERR:
++ case DWC_OTG_HC_XFER_STALL:
++ case DWC_OTG_HC_XFER_BABBLE_ERR:
++ free_qtd = 1;
++ break;
++ case DWC_OTG_HC_XFER_XACT_ERR:
++ if (qtd->error_count >= 3) {
++ DWC_DEBUGPL(DBG_HCDV,
++ " Complete URB with transaction error\n");
++ free_qtd = 1;
++ qtd->urb->status = -DWC_E_PROTOCOL;
++ hcd->fops->complete(hcd, qtd->urb->priv,
++ qtd->urb, -DWC_E_PROTOCOL);
++ } else {
++ free_qtd = 0;
++ }
++ break;
++ case DWC_OTG_HC_XFER_URB_DEQUEUE:
++ /*
++ * The QTD has already been removed and the QH has been
++ * deactivated. Don't want to do anything except release the
++ * host channel and try to queue more transfers.
++ */
++ goto cleanup;
++ case DWC_OTG_HC_XFER_NO_HALT_STATUS:
++ free_qtd = 0;
++ break;
++ case DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE:
++ DWC_DEBUGPL(DBG_HCDV,
++ " Complete URB with I/O error\n");
++ free_qtd = 1;
++ qtd->urb->status = -DWC_E_IO;
++ hcd->fops->complete(hcd, qtd->urb->priv,
++ qtd->urb, -DWC_E_IO);
++ break;
++ default:
++ free_qtd = 0;
++ break;
++ }
++
++ deactivate_qh(hcd, hc->qh, free_qtd);
++
++cleanup:
++ /*
++ * Release the host channel for use by other transfers. The cleanup
++ * function clears the channel interrupt enables and conditions, so
++ * there's no need to clear the Channel Halted interrupt separately.
++ */
++ if (fiq_fsm_enable && hcd->fiq_state->channel[hc->hc_num].fsm != FIQ_PASSTHROUGH)
++ dwc_otg_cleanup_fiq_channel(hcd, hc->hc_num);
++ dwc_otg_hc_cleanup(hcd->core_if, hc);
++ DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry);
++
++ if (!microframe_schedule) {
++ switch (hc->ep_type) {
++ case DWC_OTG_EP_TYPE_CONTROL:
++ case DWC_OTG_EP_TYPE_BULK:
++ hcd->non_periodic_channels--;
++ break;
++
++ default:
++ /*
++ * Don't release reservations for periodic channels here.
++ * That's done when a periodic transfer is descheduled (i.e.
++ * when the QH is removed from the periodic schedule).
++ */
++ break;
++ }
++ } else {
++
++ DWC_SPINLOCK_IRQSAVE(channel_lock, &flags);
++ hcd->available_host_channels++;
++ fiq_print(FIQDBG_INT, hcd->fiq_state, "AHC = %d ", hcd->available_host_channels);
++ DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags);
++ }
++
++ /* Try to queue more transfers now that there's a free channel. */
++ tr_type = dwc_otg_hcd_select_transactions(hcd);
++ if (tr_type != DWC_OTG_TRANSACTION_NONE) {
++ dwc_otg_hcd_queue_transactions(hcd, tr_type);
++ }
++}
++
++/**
++ * Halts a host channel. If the channel cannot be halted immediately because
++ * the request queue is full, this function ensures that the FIFO empty
++ * interrupt for the appropriate queue is enabled so that the halt request can
++ * be queued when there is space in the request queue.
++ *
++ * This function may also be called in DMA mode. In that case, the channel is
++ * simply released since the core always halts the channel automatically in
++ * DMA mode.
++ */
++static void halt_channel(dwc_otg_hcd_t * hcd,
++ dwc_hc_t * hc,
++ dwc_otg_qtd_t * qtd, dwc_otg_halt_status_e halt_status)
++{
++ if (hcd->core_if->dma_enable) {
++ release_channel(hcd, hc, qtd, halt_status);
++ return;
++ }
++
++ /* Slave mode processing... */
++ dwc_otg_hc_halt(hcd->core_if, hc, halt_status);
++
++ if (hc->halt_on_queue) {
++ gintmsk_data_t gintmsk = {.d32 = 0 };
++ dwc_otg_core_global_regs_t *global_regs;
++ global_regs = hcd->core_if->core_global_regs;
++
++ if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
++ hc->ep_type == DWC_OTG_EP_TYPE_BULK) {
++ /*
++ * Make sure the Non-periodic Tx FIFO empty interrupt
++ * is enabled so that the non-periodic schedule will
++ * be processed.
++ */
++ gintmsk.b.nptxfempty = 1;
++ if (fiq_enable) {
++ local_fiq_disable();
++ fiq_fsm_spin_lock(&hcd->fiq_state->lock);
++ DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);
++ fiq_fsm_spin_unlock(&hcd->fiq_state->lock);
++ local_fiq_enable();
++ } else {
++ DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);
++ }
++ } else {
++ /*
++ * Move the QH from the periodic queued schedule to
++ * the periodic assigned schedule. This allows the
++ * halt to be queued when the periodic schedule is
++ * processed.
++ */
++ DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned,
++ &hc->qh->qh_list_entry);
++
++ /*
++ * Make sure the Periodic Tx FIFO Empty interrupt is
++ * enabled so that the periodic schedule will be
++ * processed.
++ */
++ gintmsk.b.ptxfempty = 1;
++ if (fiq_enable) {
++ local_fiq_disable();
++ fiq_fsm_spin_lock(&hcd->fiq_state->lock);
++ DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);
++ fiq_fsm_spin_unlock(&hcd->fiq_state->lock);
++ local_fiq_enable();
++ } else {
++ DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);
++ }
++ }
++ }
++}
++
++/**
++ * Performs common cleanup for non-periodic transfers after a Transfer
++ * Complete interrupt. This function should be called after any endpoint type
++ * specific handling is finished to release the host channel.
++ */
++static void complete_non_periodic_xfer(dwc_otg_hcd_t * hcd,
++ dwc_hc_t * hc,
++ dwc_otg_hc_regs_t * hc_regs,
++ dwc_otg_qtd_t * qtd,
++ dwc_otg_halt_status_e halt_status)
++{
++ hcint_data_t hcint;
++
++ qtd->error_count = 0;
++
++ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
++ if (hcint.b.nyet) {
++ /*
++ * Got a NYET on the last transaction of the transfer. This
++ * means that the endpoint should be in the PING state at the
++ * beginning of the next transfer.
++ */
++ hc->qh->ping_state = 1;
++ clear_hc_int(hc_regs, nyet);
++ }
++
++ /*
++ * Always halt and release the host channel to make it available for
++ * more transfers. There may still be more phases for a control
++ * transfer or more data packets for a bulk transfer at this point,
++ * but the host channel is still halted. A channel will be reassigned
++ * to the transfer when the non-periodic schedule is processed after
++ * the channel is released. This allows transactions to be queued
++ * properly via dwc_otg_hcd_queue_transactions, which also enables the
++ * Tx FIFO Empty interrupt if necessary.
++ */
++ if (hc->ep_is_in) {
++ /*
++ * IN transfers in Slave mode require an explicit disable to
++ * halt the channel. (In DMA mode, this call simply releases
++ * the channel.)
++ */
++ halt_channel(hcd, hc, qtd, halt_status);
++ } else {
++ /*
++ * The channel is automatically disabled by the core for OUT
++ * transfers in Slave mode.
++ */
++ release_channel(hcd, hc, qtd, halt_status);
++ }
++}
++
++/**
++ * Performs common cleanup for periodic transfers after a Transfer Complete
++ * interrupt. This function should be called after any endpoint type specific
++ * handling is finished to release the host channel.
++ */
++static void complete_periodic_xfer(dwc_otg_hcd_t * hcd,
++ dwc_hc_t * hc,
++ dwc_otg_hc_regs_t * hc_regs,
++ dwc_otg_qtd_t * qtd,
++ dwc_otg_halt_status_e halt_status)
++{
++ hctsiz_data_t hctsiz;
++ qtd->error_count = 0;
++
++ hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
++ if (!hc->ep_is_in || hctsiz.b.pktcnt == 0) {
++ /* Core halts channel in these cases. */
++ release_channel(hcd, hc, qtd, halt_status);
++ } else {
++ /* Flush any outstanding requests from the Tx queue. */
++ halt_channel(hcd, hc, qtd, halt_status);
++ }
++}
++
++static int32_t handle_xfercomp_isoc_split_in(dwc_otg_hcd_t * hcd,
++ dwc_hc_t * hc,
++ dwc_otg_hc_regs_t * hc_regs,
++ dwc_otg_qtd_t * qtd)
++{
++ uint32_t len;
++ struct dwc_otg_hcd_iso_packet_desc *frame_desc;
++ frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
++
++ len = get_actual_xfer_length(hc, hc_regs, qtd,
++ DWC_OTG_HC_XFER_COMPLETE, NULL);
++
++ if (!len) {
++ qtd->complete_split = 0;
++ qtd->isoc_split_offset = 0;
++ return 0;
++ }
++ frame_desc->actual_length += len;
++
++ if (hc->align_buff && len)
++ dwc_memcpy(qtd->urb->buf + frame_desc->offset +
++ qtd->isoc_split_offset, hc->qh->dw_align_buf, len);
++ qtd->isoc_split_offset += len;
++
++ if (frame_desc->length == frame_desc->actual_length) {
++ frame_desc->status = 0;
++ qtd->isoc_frame_index++;
++ qtd->complete_split = 0;
++ qtd->isoc_split_offset = 0;
++ }
++
++ if (qtd->isoc_frame_index == qtd->urb->packet_count) {
++ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
++ } else {
++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
++ }
++
++ return 1; /* Indicates that channel released */
++}
++
++/**
++ * Handles a host channel Transfer Complete interrupt. This handler may be
++ * called in either DMA mode or Slave mode.
++ */
++static int32_t handle_hc_xfercomp_intr(dwc_otg_hcd_t * hcd,
++ dwc_hc_t * hc,
++ dwc_otg_hc_regs_t * hc_regs,
++ dwc_otg_qtd_t * qtd)
++{
++ int urb_xfer_done;
++ dwc_otg_halt_status_e halt_status = DWC_OTG_HC_XFER_COMPLETE;
++ dwc_otg_hcd_urb_t *urb = qtd->urb;
++ int pipe_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info);
++
++ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
++ "Transfer Complete--\n", hc->hc_num);
++
++ if (hcd->core_if->dma_desc_enable) {
++ dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, halt_status);
++ if (pipe_type == UE_ISOCHRONOUS) {
++ /* Do not disable the interrupt, just clear it */
++ clear_hc_int(hc_regs, xfercomp);
++ return 1;
++ }
++ goto handle_xfercomp_done;
++ }
++
++ /*
++ * Handle xfer complete on CSPLIT.
++ */
++
++ if (hc->qh->do_split) {
++ if ((hc->ep_type == DWC_OTG_EP_TYPE_ISOC) && hc->ep_is_in
++ && hcd->core_if->dma_enable) {
++ if (qtd->complete_split
++ && handle_xfercomp_isoc_split_in(hcd, hc, hc_regs,
++ qtd))
++ goto handle_xfercomp_done;
++ } else {
++ qtd->complete_split = 0;
++ }
++ }
++
++ /* Update the QTD and URB states. */
++ switch (pipe_type) {
++ case UE_CONTROL:
++ switch (qtd->control_phase) {
++ case DWC_OTG_CONTROL_SETUP:
++ if (urb->length > 0) {
++ qtd->control_phase = DWC_OTG_CONTROL_DATA;
++ } else {
++ qtd->control_phase = DWC_OTG_CONTROL_STATUS;
++ }
++ DWC_DEBUGPL(DBG_HCDV,
++ " Control setup transaction done\n");
++ halt_status = DWC_OTG_HC_XFER_COMPLETE;
++ break;
++ case DWC_OTG_CONTROL_DATA:{
++ urb_xfer_done =
++ update_urb_state_xfer_comp(hc, hc_regs, urb,
++ qtd);
++ if (urb_xfer_done) {
++ qtd->control_phase =
++ DWC_OTG_CONTROL_STATUS;
++ DWC_DEBUGPL(DBG_HCDV,
++ " Control data transfer done\n");
++ } else {
++ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
++ }
++ halt_status = DWC_OTG_HC_XFER_COMPLETE;
++ break;
++ }
++ case DWC_OTG_CONTROL_STATUS:
++ DWC_DEBUGPL(DBG_HCDV, " Control transfer complete\n");
++ if (urb->status == -DWC_E_IN_PROGRESS) {
++ urb->status = 0;
++ }
++ hcd->fops->complete(hcd, urb->priv, urb, urb->status);
++ halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
++ break;
++ }
++
++ complete_non_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
++ break;
++ case UE_BULK:
++ DWC_DEBUGPL(DBG_HCDV, " Bulk transfer complete\n");
++ urb_xfer_done =
++ update_urb_state_xfer_comp(hc, hc_regs, urb, qtd);
++ if (urb_xfer_done) {
++ hcd->fops->complete(hcd, urb->priv, urb, urb->status);
++ halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
++ } else {
++ halt_status = DWC_OTG_HC_XFER_COMPLETE;
++ }
++
++ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
++ complete_non_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
++ break;
++ case UE_INTERRUPT:
++ DWC_DEBUGPL(DBG_HCDV, " Interrupt transfer complete\n");
++ urb_xfer_done =
++ update_urb_state_xfer_comp(hc, hc_regs, urb, qtd);
++
++ /*
++ * Interrupt URB is done on the first transfer complete
++ * interrupt.
++ */
++ if (urb_xfer_done) {
++ hcd->fops->complete(hcd, urb->priv, urb, urb->status);
++ halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
++ } else {
++ halt_status = DWC_OTG_HC_XFER_COMPLETE;
++ }
++
++ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
++ complete_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
++ break;
++ case UE_ISOCHRONOUS:
++ DWC_DEBUGPL(DBG_HCDV, " Isochronous transfer complete\n");
++ if (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_ALL) {
++ halt_status =
++ update_isoc_urb_state(hcd, hc, hc_regs, qtd,
++ DWC_OTG_HC_XFER_COMPLETE);
++ }
++ complete_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
++ break;
++ }
++
++handle_xfercomp_done:
++ disable_hc_int(hc_regs, xfercompl);
++
++ return 1;
++}
++
++/**
++ * Handles a host channel STALL interrupt. This handler may be called in
++ * either DMA mode or Slave mode.
++ */
++static int32_t handle_hc_stall_intr(dwc_otg_hcd_t * hcd,
++ dwc_hc_t * hc,
++ dwc_otg_hc_regs_t * hc_regs,
++ dwc_otg_qtd_t * qtd)
++{
++ dwc_otg_hcd_urb_t *urb = qtd->urb;
++ int pipe_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info);
++
++ DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
++ "STALL Received--\n", hc->hc_num);
++
++ if (hcd->core_if->dma_desc_enable) {
++ dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, DWC_OTG_HC_XFER_STALL);
++ goto handle_stall_done;
++ }
++
++ if (pipe_type == UE_CONTROL) {
++ hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_PIPE);
++ }
++
++ if (pipe_type == UE_BULK || pipe_type == UE_INTERRUPT) {
++ hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_PIPE);
++ /*
++ * USB protocol requires resetting the data toggle for bulk
++ * and interrupt endpoints when a CLEAR_FEATURE(ENDPOINT_HALT)
++ * setup command is issued to the endpoint. Anticipate the
++ * CLEAR_FEATURE command since a STALL has occurred and reset
++ * the data toggle now.
++ */
++ hc->qh->data_toggle = 0;
++ }
++
++ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_STALL);
++
++handle_stall_done:
++ disable_hc_int(hc_regs, stall);
++
++ return 1;
++}
++
++/*
++ * Updates the state of the URB when a transfer has been stopped due to an
++ * abnormal condition before the transfer completes. Modifies the
++ * actual_length field of the URB to reflect the number of bytes that have
++ * actually been transferred via the host channel.
++ */
++static void update_urb_state_xfer_intr(dwc_hc_t * hc,
++ dwc_otg_hc_regs_t * hc_regs,
++ dwc_otg_hcd_urb_t * urb,
++ dwc_otg_qtd_t * qtd,
++ dwc_otg_halt_status_e halt_status)
++{
++ uint32_t bytes_transferred = get_actual_xfer_length(hc, hc_regs, qtd,
++ halt_status, NULL);
++ /* non DWORD-aligned buffer case handling. */
++ if (hc->align_buff && bytes_transferred && hc->ep_is_in) {
++ dwc_memcpy(urb->buf + urb->actual_length, hc->qh->dw_align_buf,
++ bytes_transferred);
++ }
++
++ urb->actual_length += bytes_transferred;
++
++#ifdef DEBUG
++ {
++ hctsiz_data_t hctsiz;
++ hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
++ DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n",
++ __func__, (hc->ep_is_in ? "IN" : "OUT"),
++ hc->hc_num);
++ DWC_DEBUGPL(DBG_HCDV, " hc->start_pkt_count %d\n",
++ hc->start_pkt_count);
++ DWC_DEBUGPL(DBG_HCDV, " hctsiz.pktcnt %d\n", hctsiz.b.pktcnt);
++ DWC_DEBUGPL(DBG_HCDV, " hc->max_packet %d\n", hc->max_packet);
++ DWC_DEBUGPL(DBG_HCDV, " bytes_transferred %d\n",
++ bytes_transferred);
++ DWC_DEBUGPL(DBG_HCDV, " urb->actual_length %d\n",
++ urb->actual_length);
++ DWC_DEBUGPL(DBG_HCDV, " urb->transfer_buffer_length %d\n",
++ urb->length);
++ }
++#endif
++}
++
++/**
++ * Handles a host channel NAK interrupt. This handler may be called in either
++ * DMA mode or Slave mode.
++ */
++static int32_t handle_hc_nak_intr(dwc_otg_hcd_t * hcd,
++ dwc_hc_t * hc,
++ dwc_otg_hc_regs_t * hc_regs,
++ dwc_otg_qtd_t * qtd)
++{
++ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
++ "NAK Received--\n", hc->hc_num);
++
++ /*
++ * When we get bulk NAKs then remember this so we holdoff on this qh until
++ * the beginning of the next frame
++ */
++ switch(dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
++ case UE_BULK:
++ case UE_CONTROL:
++ if (nak_holdoff && qtd->qh->do_split)
++ hc->qh->nak_frame = dwc_otg_hcd_get_frame_number(hcd);
++ }
++
++ /*
++ * Handle NAK for IN/OUT SSPLIT/CSPLIT transfers, bulk, control, and
++ * interrupt. Re-start the SSPLIT transfer.
++ */
++ if (hc->do_split) {
++ if (hc->complete_split) {
++ qtd->error_count = 0;
++ }
++ qtd->complete_split = 0;
++ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
++ goto handle_nak_done;
++ }
++
++ switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
++ case UE_CONTROL:
++ case UE_BULK:
++ if (hcd->core_if->dma_enable && hc->ep_is_in) {
++ /*
++ * NAK interrupts are enabled on bulk/control IN
++ * transfers in DMA mode for the sole purpose of
++ * resetting the error count after a transaction error
++ * occurs. The core will continue transferring data.
++ * Disable other interrupts unmasked for the same
++ * reason.
++ */
++ disable_hc_int(hc_regs, datatglerr);
++ disable_hc_int(hc_regs, ack);
++ qtd->error_count = 0;
++ goto handle_nak_done;
++ }
++
++ /*
++ * NAK interrupts normally occur during OUT transfers in DMA
++ * or Slave mode. For IN transfers, more requests will be
++ * queued as request queue space is available.
++ */
++ qtd->error_count = 0;
++
++ if (!hc->qh->ping_state) {
++ update_urb_state_xfer_intr(hc, hc_regs,
++ qtd->urb, qtd,
++ DWC_OTG_HC_XFER_NAK);
++ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
++
++ if (hc->speed == DWC_OTG_EP_SPEED_HIGH)
++ hc->qh->ping_state = 1;
++ }
++
++ /*
++ * Halt the channel so the transfer can be re-started from
++ * the appropriate point or the PING protocol will
++ * start/continue.
++ */
++ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
++ break;
++ case UE_INTERRUPT:
++ qtd->error_count = 0;
++ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
++ break;
++ case UE_ISOCHRONOUS:
++ /* Should never get called for isochronous transfers. */
++ DWC_ASSERT(1, "NACK interrupt for ISOC transfer\n");
++ break;
++ }
++
++handle_nak_done:
++ disable_hc_int(hc_regs, nak);
++
++ return 1;
++}
++
++/**
++ * Handles a host channel ACK interrupt. This interrupt is enabled when
++ * performing the PING protocol in Slave mode, when errors occur during
++ * either Slave mode or DMA mode, and during Start Split transactions.
++ */
++static int32_t handle_hc_ack_intr(dwc_otg_hcd_t * hcd,
++ dwc_hc_t * hc,
++ dwc_otg_hc_regs_t * hc_regs,
++ dwc_otg_qtd_t * qtd)
++{
++ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
++ "ACK Received--\n", hc->hc_num);
++
++ if (hc->do_split) {
++ /*
++ * Handle ACK on SSPLIT.
++ * ACK should not occur in CSPLIT.
++ */
++ if (!hc->ep_is_in && hc->data_pid_start != DWC_OTG_HC_PID_SETUP) {
++ qtd->ssplit_out_xfer_count = hc->xfer_len;
++ }
++ if (!(hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in)) {
++ /* Don't need complete for isochronous out transfers. */
++ qtd->complete_split = 1;
++ }
++
++ /* ISOC OUT */
++ if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) {
++ switch (hc->xact_pos) {
++ case DWC_HCSPLIT_XACTPOS_ALL:
++ break;
++ case DWC_HCSPLIT_XACTPOS_END:
++ qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL;
++ qtd->isoc_split_offset = 0;
++ break;
++ case DWC_HCSPLIT_XACTPOS_BEGIN:
++ case DWC_HCSPLIT_XACTPOS_MID:
++ /*
++ * For BEGIN or MID, calculate the length for
++ * the next microframe to determine the correct
++ * SSPLIT token, either MID or END.
++ */
++ {
++ struct dwc_otg_hcd_iso_packet_desc
++ *frame_desc;
++
++ frame_desc =
++ &qtd->urb->
++ iso_descs[qtd->isoc_frame_index];
++ qtd->isoc_split_offset += 188;
++
++ if ((frame_desc->length -
++ qtd->isoc_split_offset) <= 188) {
++ qtd->isoc_split_pos =
++ DWC_HCSPLIT_XACTPOS_END;
++ } else {
++ qtd->isoc_split_pos =
++ DWC_HCSPLIT_XACTPOS_MID;
++ }
++
++ }
++ break;
++ }
++ } else {
++ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK);
++ }
++ } else {
++ /*
++ * An unmasked ACK on a non-split DMA transaction is
++ * for the sole purpose of resetting error counts. Disable other
++ * interrupts unmasked for the same reason.
++ */
++ if(hcd->core_if->dma_enable) {
++ disable_hc_int(hc_regs, datatglerr);
++ disable_hc_int(hc_regs, nak);
++ }
++ qtd->error_count = 0;
++
++ if (hc->qh->ping_state) {
++ hc->qh->ping_state = 0;
++ /*
++ * Halt the channel so the transfer can be re-started
++ * from the appropriate point. This only happens in
++ * Slave mode. In DMA mode, the ping_state is cleared
++ * when the transfer is started because the core
++ * automatically executes the PING, then the transfer.
++ */
++ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK);
++ }
++ }
++
++ /*
++ * If the ACK occurred when _not_ in the PING state, let the channel
++ * continue transferring data after clearing the error count.
++ */
++
++ disable_hc_int(hc_regs, ack);
++
++ return 1;
++}
++
++/**
++ * Handles a host channel NYET interrupt. This interrupt should only occur on
++ * Bulk and Control OUT endpoints and for complete split transactions. If a
++ * NYET occurs at the same time as a Transfer Complete interrupt, it is
++ * handled in the xfercomp interrupt handler, not here. This handler may be
++ * called in either DMA mode or Slave mode.
++ */
++static int32_t handle_hc_nyet_intr(dwc_otg_hcd_t * hcd,
++ dwc_hc_t * hc,
++ dwc_otg_hc_regs_t * hc_regs,
++ dwc_otg_qtd_t * qtd)
++{
++ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
++ "NYET Received--\n", hc->hc_num);
++
++ /*
++ * NYET on CSPLIT
++ * re-do the CSPLIT immediately on non-periodic
++ */
++ if (hc->do_split && hc->complete_split) {
++ if (hc->ep_is_in && (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)
++ && hcd->core_if->dma_enable) {
++ qtd->complete_split = 0;
++ qtd->isoc_split_offset = 0;
++ if (++qtd->isoc_frame_index == qtd->urb->packet_count) {
++ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
++ }
++ else
++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
++ goto handle_nyet_done;
++ }
++
++ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
++ hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
++ int frnum = dwc_otg_hcd_get_frame_number(hcd);
++
++ // With the FIQ running we only ever see the failed NYET
++ if (dwc_full_frame_num(frnum) !=
++ dwc_full_frame_num(hc->qh->sched_frame) ||
++ fiq_fsm_enable) {
++ /*
++ * No longer in the same full speed frame.
++ * Treat this as a transaction error.
++ */
++#if 0
++ /** @todo Fix system performance so this can
++ * be treated as an error. Right now complete
++ * splits cannot be scheduled precisely enough
++ * due to other system activity, so this error
++ * occurs regularly in Slave mode.
++ */
++ qtd->error_count++;
++#endif
++ qtd->complete_split = 0;
++ halt_channel(hcd, hc, qtd,
++ DWC_OTG_HC_XFER_XACT_ERR);
++ /** @todo add support for isoc release */
++ goto handle_nyet_done;
++ }
++ }
++
++ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET);
++ goto handle_nyet_done;
++ }
++
++ hc->qh->ping_state = 1;
++ qtd->error_count = 0;
++
++ update_urb_state_xfer_intr(hc, hc_regs, qtd->urb, qtd,
++ DWC_OTG_HC_XFER_NYET);
++ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
++
++ /*
++ * Halt the channel and re-start the transfer so the PING
++ * protocol will start.
++ */
++ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET);
++
++handle_nyet_done:
++ disable_hc_int(hc_regs, nyet);
++ return 1;
++}
++
++/**
++ * Handles a host channel babble interrupt. This handler may be called in
++ * either DMA mode or Slave mode.
++ */
++static int32_t handle_hc_babble_intr(dwc_otg_hcd_t * hcd,
++ dwc_hc_t * hc,
++ dwc_otg_hc_regs_t * hc_regs,
++ dwc_otg_qtd_t * qtd)
++{
++ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
++ "Babble Error--\n", hc->hc_num);
++
++ if (hcd->core_if->dma_desc_enable) {
++ dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
++ DWC_OTG_HC_XFER_BABBLE_ERR);
++ goto handle_babble_done;
++ }
++
++ if (hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
++ hcd->fops->complete(hcd, qtd->urb->priv,
++ qtd->urb, -DWC_E_OVERFLOW);
++ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_BABBLE_ERR);
++ } else {
++ dwc_otg_halt_status_e halt_status;
++ halt_status = update_isoc_urb_state(hcd, hc, hc_regs, qtd,
++ DWC_OTG_HC_XFER_BABBLE_ERR);
++ halt_channel(hcd, hc, qtd, halt_status);
++ }
++
++handle_babble_done:
++ disable_hc_int(hc_regs, bblerr);
++ return 1;
++}
++
++/**
++ * Handles a host channel AHB error interrupt. This handler is only called in
++ * DMA mode.
++ */
++static int32_t handle_hc_ahberr_intr(dwc_otg_hcd_t * hcd,
++ dwc_hc_t * hc,
++ dwc_otg_hc_regs_t * hc_regs,
++ dwc_otg_qtd_t * qtd)
++{
++ hcchar_data_t hcchar;
++ hcsplt_data_t hcsplt;
++ hctsiz_data_t hctsiz;
++ uint32_t hcdma;
++ char *pipetype, *speed;
++
++ dwc_otg_hcd_urb_t *urb = qtd->urb;
++
++ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
++ "AHB Error--\n", hc->hc_num);
++
++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
++ hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
++ hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
++ hcdma = DWC_READ_REG32(&hc_regs->hcdma);
++
++ DWC_ERROR("AHB ERROR, Channel %d\n", hc->hc_num);
++ DWC_ERROR(" hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, hcsplt.d32);
++ DWC_ERROR(" hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32, hcdma);
++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Enqueue\n");
++ DWC_ERROR(" Device address: %d\n",
++ dwc_otg_hcd_get_dev_addr(&urb->pipe_info));
++ DWC_ERROR(" Endpoint: %d, %s\n",
++ dwc_otg_hcd_get_ep_num(&urb->pipe_info),
++ (dwc_otg_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT"));
++
++ switch (dwc_otg_hcd_get_pipe_type(&urb->pipe_info)) {
++ case UE_CONTROL:
++ pipetype = "CONTROL";
++ break;
++ case UE_BULK:
++ pipetype = "BULK";
++ break;
++ case UE_INTERRUPT:
++ pipetype = "INTERRUPT";
++ break;
++ case UE_ISOCHRONOUS:
++ pipetype = "ISOCHRONOUS";
++ break;
++ default:
++ pipetype = "UNKNOWN";
++ break;
++ }
++
++ DWC_ERROR(" Endpoint type: %s\n", pipetype);
++
++ switch (hc->speed) {
++ case DWC_OTG_EP_SPEED_HIGH:
++ speed = "HIGH";
++ break;
++ case DWC_OTG_EP_SPEED_FULL:
++ speed = "FULL";
++ break;
++ case DWC_OTG_EP_SPEED_LOW:
++ speed = "LOW";
++ break;
++ default:
++ speed = "UNKNOWN";
++ break;
++ };
++
++ DWC_ERROR(" Speed: %s\n", speed);
++
++ DWC_ERROR(" Max packet size: %d\n",
++ dwc_otg_hcd_get_mps(&urb->pipe_info));
++ DWC_ERROR(" Data buffer length: %d\n", urb->length);
++ DWC_ERROR(" Transfer buffer: %p, Transfer DMA: %p\n",
++ urb->buf, (void *)urb->dma);
++ DWC_ERROR(" Setup buffer: %p, Setup DMA: %p\n",
++ urb->setup_packet, (void *)urb->setup_dma);
++ DWC_ERROR(" Interval: %d\n", urb->interval);
++
++ /* Core haltes the channel for Descriptor DMA mode */
++ if (hcd->core_if->dma_desc_enable) {
++ dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
++ DWC_OTG_HC_XFER_AHB_ERR);
++ goto handle_ahberr_done;
++ }
++
++ hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_IO);
++
++ /*
++ * Force a channel halt. Don't call halt_channel because that won't
++ * write to the HCCHARn register in DMA mode to force the halt.
++ */
++ dwc_otg_hc_halt(hcd->core_if, hc, DWC_OTG_HC_XFER_AHB_ERR);
++handle_ahberr_done:
++ disable_hc_int(hc_regs, ahberr);
++ return 1;
++}
++
++/**
++ * Handles a host channel transaction error interrupt. This handler may be
++ * called in either DMA mode or Slave mode.
++ */
++static int32_t handle_hc_xacterr_intr(dwc_otg_hcd_t * hcd,
++ dwc_hc_t * hc,
++ dwc_otg_hc_regs_t * hc_regs,
++ dwc_otg_qtd_t * qtd)
++{
++ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
++ "Transaction Error--\n", hc->hc_num);
++
++ if (hcd->core_if->dma_desc_enable) {
++ dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
++ DWC_OTG_HC_XFER_XACT_ERR);
++ goto handle_xacterr_done;
++ }
++
++ switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
++ case UE_CONTROL:
++ case UE_BULK:
++ qtd->error_count++;
++ if (!hc->qh->ping_state) {
++
++ update_urb_state_xfer_intr(hc, hc_regs,
++ qtd->urb, qtd,
++ DWC_OTG_HC_XFER_XACT_ERR);
++ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
++ if (!hc->ep_is_in && hc->speed == DWC_OTG_EP_SPEED_HIGH) {
++ hc->qh->ping_state = 1;
++ }
++ }
++
++ /*
++ * Halt the channel so the transfer can be re-started from
++ * the appropriate point or the PING protocol will start.
++ */
++ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
++ break;
++ case UE_INTERRUPT:
++ qtd->error_count++;
++ if (hc->do_split && hc->complete_split) {
++ qtd->complete_split = 0;
++ }
++ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
++ break;
++ case UE_ISOCHRONOUS:
++ {
++ dwc_otg_halt_status_e halt_status;
++ halt_status =
++ update_isoc_urb_state(hcd, hc, hc_regs, qtd,
++ DWC_OTG_HC_XFER_XACT_ERR);
++
++ halt_channel(hcd, hc, qtd, halt_status);
++ }
++ break;
++ }
++handle_xacterr_done:
++ disable_hc_int(hc_regs, xacterr);
++
++ return 1;
++}
++
++/**
++ * Handles a host channel frame overrun interrupt. This handler may be called
++ * in either DMA mode or Slave mode.
++ */
++static int32_t handle_hc_frmovrun_intr(dwc_otg_hcd_t * hcd,
++ dwc_hc_t * hc,
++ dwc_otg_hc_regs_t * hc_regs,
++ dwc_otg_qtd_t * qtd)
++{
++ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
++ "Frame Overrun--\n", hc->hc_num);
++
++ switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
++ case UE_CONTROL:
++ case UE_BULK:
++ break;
++ case UE_INTERRUPT:
++ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_FRAME_OVERRUN);
++ break;
++ case UE_ISOCHRONOUS:
++ {
++ dwc_otg_halt_status_e halt_status;
++ halt_status =
++ update_isoc_urb_state(hcd, hc, hc_regs, qtd,
++ DWC_OTG_HC_XFER_FRAME_OVERRUN);
++
++ halt_channel(hcd, hc, qtd, halt_status);
++ }
++ break;
++ }
++
++ disable_hc_int(hc_regs, frmovrun);
++
++ return 1;
++}
++
++/**
++ * Handles a host channel data toggle error interrupt. This handler may be
++ * called in either DMA mode or Slave mode.
++ */
++static int32_t handle_hc_datatglerr_intr(dwc_otg_hcd_t * hcd,
++ dwc_hc_t * hc,
++ dwc_otg_hc_regs_t * hc_regs,
++ dwc_otg_qtd_t * qtd)
++{
++ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
++ "Data Toggle Error on %s transfer--\n",
++ hc->hc_num, (hc->ep_is_in ? "IN" : "OUT"));
++
++ /* Data toggles on split transactions cause the hc to halt.
++ * restart transfer */
++ if(hc->qh->do_split)
++ {
++ qtd->error_count++;
++ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
++ update_urb_state_xfer_intr(hc, hc_regs,
++ qtd->urb, qtd, DWC_OTG_HC_XFER_XACT_ERR);
++ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
++ } else if (hc->ep_is_in) {
++ /* An unmasked data toggle error on a non-split DMA transaction is
++ * for the sole purpose of resetting error counts. Disable other
++ * interrupts unmasked for the same reason.
++ */
++ if(hcd->core_if->dma_enable) {
++ disable_hc_int(hc_regs, ack);
++ disable_hc_int(hc_regs, nak);
++ }
++ qtd->error_count = 0;
++ }
++
++ disable_hc_int(hc_regs, datatglerr);
++
++ return 1;
++}
++
++#ifdef DEBUG
++/**
++ * This function is for debug only. It checks that a valid halt status is set
++ * and that HCCHARn.chdis is clear. If there's a problem, corrective action is
++ * taken and a warning is issued.
++ * @return 1 if halt status is ok, 0 otherwise.
++ */
++static inline int halt_status_ok(dwc_otg_hcd_t * hcd,
++ dwc_hc_t * hc,
++ dwc_otg_hc_regs_t * hc_regs,
++ dwc_otg_qtd_t * qtd)
++{
++ hcchar_data_t hcchar;
++ hctsiz_data_t hctsiz;
++ hcint_data_t hcint;
++ hcintmsk_data_t hcintmsk;
++ hcsplt_data_t hcsplt;
++
++ if (hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS) {
++ /*
++ * This code is here only as a check. This condition should
++ * never happen. Ignore the halt if it does occur.
++ */
++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
++ hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
++ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
++ hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk);
++ hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
++ DWC_WARN
++ ("%s: hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS, "
++ "channel %d, hcchar 0x%08x, hctsiz 0x%08x, "
++ "hcint 0x%08x, hcintmsk 0x%08x, "
++ "hcsplt 0x%08x, qtd->complete_split %d\n", __func__,
++ hc->hc_num, hcchar.d32, hctsiz.d32, hcint.d32,
++ hcintmsk.d32, hcsplt.d32, qtd->complete_split);
++
++ DWC_WARN("%s: no halt status, channel %d, ignoring interrupt\n",
++ __func__, hc->hc_num);
++ DWC_WARN("\n");
++ clear_hc_int(hc_regs, chhltd);
++ return 0;
++ }
++
++ /*
++ * This code is here only as a check. hcchar.chdis should
++ * never be set when the halt interrupt occurs. Halt the
++ * channel again if it does occur.
++ */
++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
++ if (hcchar.b.chdis) {
++ DWC_WARN("%s: hcchar.chdis set unexpectedly, "
++ "hcchar 0x%08x, trying to halt again\n",
++ __func__, hcchar.d32);
++ clear_hc_int(hc_regs, chhltd);
++ hc->halt_pending = 0;
++ halt_channel(hcd, hc, qtd, hc->halt_status);
++ return 0;
++ }
++
++ return 1;
++}
++#endif
++
++/**
++ * Handles a host Channel Halted interrupt in DMA mode. This handler
++ * determines the reason the channel halted and proceeds accordingly.
++ */
++static void handle_hc_chhltd_intr_dma(dwc_otg_hcd_t * hcd,
++ dwc_hc_t * hc,
++ dwc_otg_hc_regs_t * hc_regs,
++ dwc_otg_qtd_t * qtd)
++{
++ int out_nak_enh = 0;
++ hcint_data_t hcint;
++ hcintmsk_data_t hcintmsk;
++ /* For core with OUT NAK enhancement, the flow for high-
++ * speed CONTROL/BULK OUT is handled a little differently.
++ */
++ if (hcd->core_if->snpsid >= OTG_CORE_REV_2_71a) {
++ if (hc->speed == DWC_OTG_EP_SPEED_HIGH && !hc->ep_is_in &&
++ (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
++ hc->ep_type == DWC_OTG_EP_TYPE_BULK)) {
++ out_nak_enh = 1;
++ }
++ }
++
++ if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE ||
++ (hc->halt_status == DWC_OTG_HC_XFER_AHB_ERR
++ && !hcd->core_if->dma_desc_enable)) {
++ /*
++ * Just release the channel. A dequeue can happen on a
++ * transfer timeout. In the case of an AHB Error, the channel
++ * was forced to halt because there's no way to gracefully
++ * recover.
++ */
++ if (hcd->core_if->dma_desc_enable)
++ dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
++ hc->halt_status);
++ else
++ release_channel(hcd, hc, qtd, hc->halt_status);
++ return;
++ }
++
++ /* Read the HCINTn register to determine the cause for the halt. */
++
++ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
++ hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk);
++
++ if (hcint.b.xfercomp) {
++ /** @todo This is here because of a possible hardware bug. Spec
++ * says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT
++ * interrupt w/ACK bit set should occur, but I only see the
++ * XFERCOMP bit, even with it masked out. This is a workaround
++ * for that behavior. Should fix this when hardware is fixed.
++ */
++ if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) {
++ handle_hc_ack_intr(hcd, hc, hc_regs, qtd);
++ }
++ handle_hc_xfercomp_intr(hcd, hc, hc_regs, qtd);
++ } else if (hcint.b.stall) {
++ handle_hc_stall_intr(hcd, hc, hc_regs, qtd);
++ } else if (hcint.b.xacterr && !hcd->core_if->dma_desc_enable) {
++ if (out_nak_enh) {
++ if (hcint.b.nyet || hcint.b.nak || hcint.b.ack) {
++ DWC_DEBUGPL(DBG_HCD, "XactErr with NYET/NAK/ACK\n");
++ qtd->error_count = 0;
++ } else {
++ DWC_DEBUGPL(DBG_HCD, "XactErr without NYET/NAK/ACK\n");
++ }
++ }
++
++ /*
++ * Must handle xacterr before nak or ack. Could get a xacterr
++ * at the same time as either of these on a BULK/CONTROL OUT
++ * that started with a PING. The xacterr takes precedence.
++ */
++ handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
++ } else if (hcint.b.xcs_xact && hcd->core_if->dma_desc_enable) {
++ handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
++ } else if (hcint.b.ahberr && hcd->core_if->dma_desc_enable) {
++ handle_hc_ahberr_intr(hcd, hc, hc_regs, qtd);
++ } else if (hcint.b.bblerr) {
++ handle_hc_babble_intr(hcd, hc, hc_regs, qtd);
++ } else if (hcint.b.frmovrun) {
++ handle_hc_frmovrun_intr(hcd, hc, hc_regs, qtd);
++ } else if (hcint.b.datatglerr) {
++ handle_hc_datatglerr_intr(hcd, hc, hc_regs, qtd);
++ } else if (!out_nak_enh) {
++ if (hcint.b.nyet) {
++ /*
++ * Must handle nyet before nak or ack. Could get a nyet at the
++ * same time as either of those on a BULK/CONTROL OUT that
++ * started with a PING. The nyet takes precedence.
++ */
++ handle_hc_nyet_intr(hcd, hc, hc_regs, qtd);
++ } else if (hcint.b.nak && !hcintmsk.b.nak) {
++ /*
++ * If nak is not masked, it's because a non-split IN transfer
++ * is in an error state. In that case, the nak is handled by
++ * the nak interrupt handler, not here. Handle nak here for
++ * BULK/CONTROL OUT transfers, which halt on a NAK to allow
++ * rewinding the buffer pointer.
++ */
++ handle_hc_nak_intr(hcd, hc, hc_regs, qtd);
++ } else if (hcint.b.ack && !hcintmsk.b.ack) {
++ /*
++ * If ack is not masked, it's because a non-split IN transfer
++ * is in an error state. In that case, the ack is handled by
++ * the ack interrupt handler, not here. Handle ack here for
++ * split transfers. Start splits halt on ACK.
++ */
++ handle_hc_ack_intr(hcd, hc, hc_regs, qtd);
++ } else {
++ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
++ hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
++ /*
++ * A periodic transfer halted with no other channel
++ * interrupts set. Assume it was halted by the core
++ * because it could not be completed in its scheduled
++ * (micro)frame.
++ */
++#ifdef DEBUG
++ DWC_PRINTF
++ ("%s: Halt channel %d (assume incomplete periodic transfer)\n",
++ __func__, hc->hc_num);
++#endif
++ halt_channel(hcd, hc, qtd,
++ DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE);
++ } else {
++ DWC_ERROR
++ ("%s: Channel %d, DMA Mode -- ChHltd set, but reason "
++ "for halting is unknown, hcint 0x%08x, intsts 0x%08x\n",
++ __func__, hc->hc_num, hcint.d32,
++ DWC_READ_REG32(&hcd->
++ core_if->core_global_regs->
++ gintsts));
++ /* Failthrough: use 3-strikes rule */
++ qtd->error_count++;
++ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
++ update_urb_state_xfer_intr(hc, hc_regs,
++ qtd->urb, qtd, DWC_OTG_HC_XFER_XACT_ERR);
++ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
++ }
++
++ }
++ } else {
++ DWC_PRINTF("NYET/NAK/ACK/other in non-error case, 0x%08x\n",
++ hcint.d32);
++ /* Failthrough: use 3-strikes rule */
++ qtd->error_count++;
++ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
++ update_urb_state_xfer_intr(hc, hc_regs,
++ qtd->urb, qtd, DWC_OTG_HC_XFER_XACT_ERR);
++ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
++ }
++}
++
++/**
++ * Handles a host channel Channel Halted interrupt.
++ *
++ * In slave mode, this handler is called only when the driver specifically
++ * requests a halt. This occurs during handling other host channel interrupts
++ * (e.g. nak, xacterr, stall, nyet, etc.).
++ *
++ * In DMA mode, this is the interrupt that occurs when the core has finished
++ * processing a transfer on a channel. Other host channel interrupts (except
++ * ahberr) are disabled in DMA mode.
++ */
++static int32_t handle_hc_chhltd_intr(dwc_otg_hcd_t * hcd,
++ dwc_hc_t * hc,
++ dwc_otg_hc_regs_t * hc_regs,
++ dwc_otg_qtd_t * qtd)
++{
++ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
++ "Channel Halted--\n", hc->hc_num);
++
++ if (hcd->core_if->dma_enable) {
++ handle_hc_chhltd_intr_dma(hcd, hc, hc_regs, qtd);
++ } else {
++#ifdef DEBUG
++ if (!halt_status_ok(hcd, hc, hc_regs, qtd)) {
++ return 1;
++ }
++#endif
++ release_channel(hcd, hc, qtd, hc->halt_status);
++ }
++
++ return 1;
++}
++
++
++/**
++ * dwc_otg_fiq_unmangle_isoc() - Update the iso_frame_desc structure on
++ * FIQ transfer completion
++ * @hcd: Pointer to dwc_otg_hcd struct
++ * @num: Host channel number
++ *
++ * 1. Un-mangle the status as recorded in each iso_frame_desc status
++ * 2. Copy it from the dwc_otg_urb into the real URB
++ */
++void dwc_otg_fiq_unmangle_isoc(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, dwc_otg_qtd_t *qtd, uint32_t num)
++{
++ struct dwc_otg_hcd_urb *dwc_urb = qtd->urb;
++ int nr_frames = dwc_urb->packet_count;
++ int i;
++ hcint_data_t frame_hcint;
++
++ for (i = 0; i < nr_frames; i++) {
++ frame_hcint.d32 = dwc_urb->iso_descs[i].status;
++ if (frame_hcint.b.xfercomp) {
++ dwc_urb->iso_descs[i].status = 0;
++ dwc_urb->actual_length += dwc_urb->iso_descs[i].actual_length;
++ } else if (frame_hcint.b.frmovrun) {
++ if (qh->ep_is_in)
++ dwc_urb->iso_descs[i].status = -DWC_E_NO_STREAM_RES;
++ else
++ dwc_urb->iso_descs[i].status = -DWC_E_COMMUNICATION;
++ dwc_urb->error_count++;
++ dwc_urb->iso_descs[i].actual_length = 0;
++ } else if (frame_hcint.b.xacterr) {
++ dwc_urb->iso_descs[i].status = -DWC_E_PROTOCOL;
++ dwc_urb->error_count++;
++ dwc_urb->iso_descs[i].actual_length = 0;
++ } else if (frame_hcint.b.bblerr) {
++ dwc_urb->iso_descs[i].status = -DWC_E_OVERFLOW;
++ dwc_urb->error_count++;
++ dwc_urb->iso_descs[i].actual_length = 0;
++ } else {
++ /* Something went wrong */
++ dwc_urb->iso_descs[i].status = -1;
++ dwc_urb->iso_descs[i].actual_length = 0;
++ dwc_urb->error_count++;
++ }
++ }
++ //printk_ratelimited(KERN_INFO "%s: HS isochronous of %d/%d frames with %d errors complete\n",
++ // __FUNCTION__, i, dwc_urb->packet_count, dwc_urb->error_count);
++ hcd->fops->complete(hcd, dwc_urb->priv, dwc_urb, 0);
++ release_channel(hcd, qh->channel, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
++}
++
++/**
++ * dwc_otg_fiq_unsetup_per_dma() - Remove data from bounce buffers for split transactions
++ * @hcd: Pointer to dwc_otg_hcd struct
++ * @num: Host channel number
++ *
++ * Copies data from the FIQ bounce buffers into the URB's transfer buffer. Does not modify URB state.
++ * Returns total length of data or -1 if the buffers were not used.
++ *
++ */
++int dwc_otg_fiq_unsetup_per_dma(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, dwc_otg_qtd_t *qtd, uint32_t num)
++{
++ dwc_hc_t *hc = qh->channel;
++ struct fiq_dma_blob *blob = hcd->fiq_dmab;
++ struct fiq_channel_state *st = &hcd->fiq_state->channel[num];
++ uint8_t *ptr = NULL;
++ int index = 0, len = 0;
++ int i = 0;
++ if (hc->ep_is_in) {
++ /* Copy data out of the DMA bounce buffers to the URB's buffer.
++ * The align_buf is ignored as this is ignored on FSM enqueue. */
++ ptr = qtd->urb->buf;
++ if (qh->ep_type == UE_ISOCHRONOUS) {
++ /* Isoc IN transactions - grab the offset of the iso_frame_desc into the URB transfer buffer */
++ index = qtd->isoc_frame_index;
++ ptr += qtd->urb->iso_descs[index].offset;
++ } else {
++ /* Need to increment by actual_length for interrupt IN */
++ ptr += qtd->urb->actual_length;
++ }
++
++ for (i = 0; i < st->dma_info.index; i++) {
++ len += st->dma_info.slot_len[i];
++ dwc_memcpy(ptr, &blob->channel[num].index[i].buf[0], st->dma_info.slot_len[i]);
++ ptr += st->dma_info.slot_len[i];
++ }
++ return len;
++ } else {
++ /* OUT endpoints - nothing to do. */
++ return -1;
++ }
++
++}
++/**
++ * dwc_otg_hcd_handle_hc_fsm() - handle an unmasked channel interrupt
++ * from a channel handled in the FIQ
++ * @hcd: Pointer to dwc_otg_hcd struct
++ * @num: Host channel number
++ *
++ * If a host channel interrupt was received by the IRQ and this was a channel
++ * used by the FIQ, the execution flow for transfer completion is substantially
++ * different from the normal (messy) path. This function and its friends handles
++ * channel cleanup and transaction completion from a FIQ transaction.
++ */
++void dwc_otg_hcd_handle_hc_fsm(dwc_otg_hcd_t *hcd, uint32_t num)
++{
++ struct fiq_channel_state *st = &hcd->fiq_state->channel[num];
++ dwc_hc_t *hc = hcd->hc_ptr_array[num];
++ dwc_otg_qtd_t *qtd = DWC_CIRCLEQ_FIRST(&hc->qh->qtd_list);
++ dwc_otg_qh_t *qh = hc->qh;
++ dwc_otg_hc_regs_t *hc_regs = hcd->core_if->host_if->hc_regs[num];
++ hcint_data_t hcint = hcd->fiq_state->channel[num].hcint_copy;
++ int hostchannels = 0;
++ fiq_print(FIQDBG_INT, hcd->fiq_state, "OUT %01d %01d ", num , st->fsm);
++
++ hostchannels = hcd->available_host_channels;
++ switch (st->fsm) {
++ case FIQ_TEST:
++ break;
++
++ case FIQ_DEQUEUE_ISSUED:
++ /* hc_halt was called. QTD no longer exists. */
++ /* TODO: for a nonperiodic split transaction, need to issue a
++ * CLEAR_TT_BUFFER hub command if we were in the start-split phase.
++ */
++ release_channel(hcd, hc, NULL, hc->halt_status);
++ break;
++
++ case FIQ_NP_SPLIT_DONE:
++ /* Nonperiodic transaction complete. */
++ if (!hc->ep_is_in) {
++ qtd->ssplit_out_xfer_count = hc->xfer_len;
++ }
++ if (hcint.b.xfercomp) {
++ handle_hc_xfercomp_intr(hcd, hc, hc_regs, qtd);
++ } else if (hcint.b.nak) {
++ handle_hc_nak_intr(hcd, hc, hc_regs, qtd);
++ }
++ break;
++
++ case FIQ_NP_SPLIT_HS_ABORTED:
++ /* A HS abort is a 3-strikes on the HS bus at any point in the transaction.
++ * Normally a CLEAR_TT_BUFFER hub command would be required: we can't do that
++ * because there's no guarantee which order a non-periodic split happened in.
++ * We could end up clearing a perfectly good transaction out of the buffer.
++ */
++ if (hcint.b.xacterr) {
++ qtd->error_count += st->nr_errors;
++ handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
++ } else if (hcint.b.ahberr) {
++ handle_hc_ahberr_intr(hcd, hc, hc_regs, qtd);
++ } else {
++ local_fiq_disable();
++ BUG();
++ }
++ break;
++
++ case FIQ_NP_SPLIT_LS_ABORTED:
++ /* A few cases can cause this - either an unknown state on a SSPLIT or
++ * STALL/data toggle error response on a CSPLIT */
++ if (hcint.b.stall) {
++ handle_hc_stall_intr(hcd, hc, hc_regs, qtd);
++ } else if (hcint.b.datatglerr) {
++ handle_hc_datatglerr_intr(hcd, hc, hc_regs, qtd);
++ } else if (hcint.b.bblerr) {
++ handle_hc_babble_intr(hcd, hc, hc_regs, qtd);
++ } else if (hcint.b.ahberr) {
++ handle_hc_ahberr_intr(hcd, hc, hc_regs, qtd);
++ } else {
++ local_fiq_disable();
++ BUG();
++ }
++ break;
++
++ case FIQ_PER_SPLIT_DONE:
++ /* Isoc IN or Interrupt IN/OUT */
++
++ /* Flow control here is different from the normal execution by the driver.
++ * We need to completely ignore most of the driver's method of handling
++ * split transactions and do it ourselves.
++ */
++ if (hc->ep_type == UE_INTERRUPT) {
++ if (hcint.b.nak) {
++ handle_hc_nak_intr(hcd, hc, hc_regs, qtd);
++ } else if (hc->ep_is_in) {
++ int len;
++ len = dwc_otg_fiq_unsetup_per_dma(hcd, hc->qh, qtd, num);
++ //printk(KERN_NOTICE "FIQ Transaction: hc=%d len=%d urb_len = %d\n", num, len, qtd->urb->length);
++ qtd->urb->actual_length += len;
++ if (qtd->urb->actual_length >= qtd->urb->length) {
++ qtd->urb->status = 0;
++ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, qtd->urb->status);
++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
++ } else {
++ /* Interrupt transfer not complete yet - is it a short read? */
++ if (len < hc->max_packet) {
++ /* Interrupt transaction complete */
++ qtd->urb->status = 0;
++ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, qtd->urb->status);
++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
++ } else {
++ /* Further transactions required */
++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE);
++ }
++ }
++ } else {
++ /* Interrupt OUT complete. */
++ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
++ qtd->urb->actual_length += hc->xfer_len;
++ if (qtd->urb->actual_length >= qtd->urb->length) {
++ qtd->urb->status = 0;
++ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, qtd->urb->status);
++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
++ } else {
++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE);
++ }
++ }
++ } else {
++ /* ISOC IN complete. */
++ struct dwc_otg_hcd_iso_packet_desc *frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
++ int len = 0;
++ /* Record errors, update qtd. */
++ if (st->nr_errors) {
++ frame_desc->actual_length = 0;
++ frame_desc->status = -DWC_E_PROTOCOL;
++ } else {
++ frame_desc->status = 0;
++ /* Unswizzle dma */
++ len = dwc_otg_fiq_unsetup_per_dma(hcd, qh, qtd, num);
++ frame_desc->actual_length = len;
++ }
++ qtd->isoc_frame_index++;
++ if (qtd->isoc_frame_index == qtd->urb->packet_count) {
++ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
++ } else {
++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE);
++ }
++ }
++ break;
++
++ case FIQ_PER_ISO_OUT_DONE: {
++ struct dwc_otg_hcd_iso_packet_desc *frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
++ /* Record errors, update qtd. */
++ if (st->nr_errors) {
++ frame_desc->actual_length = 0;
++ frame_desc->status = -DWC_E_PROTOCOL;
++ } else {
++ frame_desc->status = 0;
++ frame_desc->actual_length = frame_desc->length;
++ }
++ qtd->isoc_frame_index++;
++ qtd->isoc_split_offset = 0;
++ if (qtd->isoc_frame_index == qtd->urb->packet_count) {
++ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
++ } else {
++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE);
++ }
++ }
++ break;
++
++ case FIQ_PER_SPLIT_NYET_ABORTED:
++ /* Doh. lost the data. */
++ printk_ratelimited(KERN_INFO "Transfer to device %d endpoint 0x%x frame %d failed "
++ "- FIQ reported NYET. Data may have been lost.\n",
++ hc->dev_addr, hc->ep_num, dwc_otg_hcd_get_frame_number(hcd) >> 3);
++ if (hc->ep_type == UE_ISOCHRONOUS) {
++ struct dwc_otg_hcd_iso_packet_desc *frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
++ /* Record errors, update qtd. */
++ frame_desc->actual_length = 0;
++ frame_desc->status = -DWC_E_PROTOCOL;
++ qtd->isoc_frame_index++;
++ qtd->isoc_split_offset = 0;
++ if (qtd->isoc_frame_index == qtd->urb->packet_count) {
++ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
++ } else {
++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE);
++ }
++ } else {
++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
++ }
++ break;
++
++ case FIQ_HS_ISOC_DONE:
++ /* The FIQ has performed a whole pile of isochronous transactions.
++ * The status is recorded as the interrupt state should the transaction
++ * fail.
++ */
++ dwc_otg_fiq_unmangle_isoc(hcd, qh, qtd, num);
++ break;
++
++ case FIQ_PER_SPLIT_LS_ABORTED:
++ if (hcint.b.xacterr) {
++ /* Hub has responded with an ERR packet. Device
++ * has been unplugged or the port has been disabled.
++ * TODO: need to issue a reset to the hub port. */
++ qtd->error_count += 3;
++ handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
++ } else if (hcint.b.stall) {
++ handle_hc_stall_intr(hcd, hc, hc_regs, qtd);
++ } else if (hcint.b.bblerr) {
++ handle_hc_babble_intr(hcd, hc, hc_regs, qtd);
++ } else {
++ printk_ratelimited(KERN_INFO "Transfer to device %d endpoint 0x%x failed "
++ "- FIQ reported FSM=%d. Data may have been lost.\n",
++ st->fsm, hc->dev_addr, hc->ep_num);
++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
++ }
++ break;
++
++ case FIQ_PER_SPLIT_HS_ABORTED:
++ /* Either the SSPLIT phase suffered transaction errors or something
++ * unexpected happened.
++ */
++ qtd->error_count += 3;
++ handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
++ break;
++
++ case FIQ_PER_SPLIT_TIMEOUT:
++ /* Couldn't complete in the nominated frame */
++ printk(KERN_INFO "Transfer to device %d endpoint 0x%x frame %d failed "
++ "- FIQ timed out. Data may have been lost.\n",
++ hc->dev_addr, hc->ep_num, dwc_otg_hcd_get_frame_number(hcd) >> 3);
++ if (hc->ep_type == UE_ISOCHRONOUS) {
++ struct dwc_otg_hcd_iso_packet_desc *frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
++ /* Record errors, update qtd. */
++ frame_desc->actual_length = 0;
++ if (hc->ep_is_in) {
++ frame_desc->status = -DWC_E_NO_STREAM_RES;
++ } else {
++ frame_desc->status = -DWC_E_COMMUNICATION;
++ }
++ qtd->isoc_frame_index++;
++ if (qtd->isoc_frame_index == qtd->urb->packet_count) {
++ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
++ } else {
++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE);
++ }
++ } else {
++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
++ }
++ break;
++
++ default:
++ DWC_WARN("Unexpected state received on hc=%d fsm=%d on transfer to device %d ep 0x%x",
++ hc->hc_num, st->fsm, hc->dev_addr, hc->ep_num);
++ qtd->error_count++;
++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
++ }
++ return;
++}
++
++/** Handles interrupt for a specific Host Channel */
++int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t * dwc_otg_hcd, uint32_t num)
++{
++ int retval = 0;
++ hcint_data_t hcint;
++ hcintmsk_data_t hcintmsk;
++ dwc_hc_t *hc;
++ dwc_otg_hc_regs_t *hc_regs;
++ dwc_otg_qtd_t *qtd;
++
++ DWC_DEBUGPL(DBG_HCDV, "--Host Channel Interrupt--, Channel %d\n", num);
++
++ hc = dwc_otg_hcd->hc_ptr_array[num];
++ hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[num];
++ if(hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) {
++ /* We are responding to a channel disable. Driver
++ * state is cleared - our qtd has gone away.
++ */
++ release_channel(dwc_otg_hcd, hc, NULL, hc->halt_status);
++ return 1;
++ }
++ qtd = DWC_CIRCLEQ_FIRST(&hc->qh->qtd_list);
++
++ /*
++ * FSM mode: Check to see if this is a HC interrupt from a channel handled by the FIQ.
++ * Execution path is fundamentally different for the channels after a FIQ has completed
++ * a split transaction.
++ */
++ if (fiq_fsm_enable) {
++ switch (dwc_otg_hcd->fiq_state->channel[num].fsm) {
++ case FIQ_PASSTHROUGH:
++ break;
++ case FIQ_PASSTHROUGH_ERRORSTATE:
++ /* Hook into the error count */
++ fiq_print(FIQDBG_ERR, dwc_otg_hcd->fiq_state, "HCDERR%02d", num);
++ if (!dwc_otg_hcd->fiq_state->channel[num].nr_errors) {
++ qtd->error_count = 0;
++ fiq_print(FIQDBG_ERR, dwc_otg_hcd->fiq_state, "RESET ");
++ }
++ break;
++ default:
++ dwc_otg_hcd_handle_hc_fsm(dwc_otg_hcd, num);
++ return 1;
++ }
++ }
++
++ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
++ hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk);
++ hcint.d32 = hcint.d32 & hcintmsk.d32;
++ if (!dwc_otg_hcd->core_if->dma_enable) {
++ if (hcint.b.chhltd && hcint.d32 != 0x2) {
++ hcint.b.chhltd = 0;
++ }
++ }
++
++ if (hcint.b.xfercomp) {
++ retval |=
++ handle_hc_xfercomp_intr(dwc_otg_hcd, hc, hc_regs, qtd);
++ /*
++ * If NYET occurred at same time as Xfer Complete, the NYET is
++ * handled by the Xfer Complete interrupt handler. Don't want
++ * to call the NYET interrupt handler in this case.
++ */
++ hcint.b.nyet = 0;
++ }
++ if (hcint.b.chhltd) {
++ retval |= handle_hc_chhltd_intr(dwc_otg_hcd, hc, hc_regs, qtd);
++ }
++ if (hcint.b.ahberr) {
++ retval |= handle_hc_ahberr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
++ }
++ if (hcint.b.stall) {
++ retval |= handle_hc_stall_intr(dwc_otg_hcd, hc, hc_regs, qtd);
++ }
++ if (hcint.b.nak) {
++ retval |= handle_hc_nak_intr(dwc_otg_hcd, hc, hc_regs, qtd);
++ }
++ if (hcint.b.ack) {
++ if(!hcint.b.chhltd)
++ retval |= handle_hc_ack_intr(dwc_otg_hcd, hc, hc_regs, qtd);
++ }
++ if (hcint.b.nyet) {
++ retval |= handle_hc_nyet_intr(dwc_otg_hcd, hc, hc_regs, qtd);
++ }
++ if (hcint.b.xacterr) {
++ retval |= handle_hc_xacterr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
++ }
++ if (hcint.b.bblerr) {
++ retval |= handle_hc_babble_intr(dwc_otg_hcd, hc, hc_regs, qtd);
++ }
++ if (hcint.b.frmovrun) {
++ retval |=
++ handle_hc_frmovrun_intr(dwc_otg_hcd, hc, hc_regs, qtd);
++ }
++ if (hcint.b.datatglerr) {
++ retval |=
++ handle_hc_datatglerr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
++ }
++
++ return retval;
++}
++#endif /* DWC_DEVICE_ONLY */
+diff -Nur linux-4.1.3/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c linux-xbian-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c
+--- linux-4.1.3/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c 2015-07-28 01:20:58.449142252 +0200
+@@ -0,0 +1,999 @@
++
++/* ==========================================================================
++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_linux.c $
++ * $Revision: #20 $
++ * $Date: 2011/10/26 $
++ * $Change: 1872981 $
++ *
++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++ * otherwise expressly agreed to in writing between Synopsys and you.
++ *
++ * The Software IS NOT an item of Licensed Software or Licensed Product under
++ * any End User Software License Agreement or Agreement for Licensed Product
++ * with Synopsys or any supplement thereto. You are permitted to use and
++ * redistribute this Software in source and binary forms, with or without
++ * modification, provided that redistributions of source code must retain this
++ * notice. You may not view, use, disclose, copy or distribute this file or
++ * any information contained herein except pursuant to this license grant from
++ * Synopsys. If you do not agree with this notice, including the disclaimer
++ * below, then you are not authorized to use the Software.
++ *
++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++ * DAMAGE.
++ * ========================================================================== */
++#ifndef DWC_DEVICE_ONLY
++
++/**
++ * @file
++ *
++ * This file contains the implementation of the HCD. In Linux, the HCD
++ * implements the hc_driver API.
++ */
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/init.h>
++#include <linux/device.h>
++#include <linux/errno.h>
++#include <linux/list.h>
++#include <linux/interrupt.h>
++#include <linux/string.h>
++#include <linux/dma-mapping.h>
++#include <linux/version.h>
++#include <asm/io.h>
++#include <asm/fiq.h>
++#include <linux/usb.h>
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35)
++#include <../drivers/usb/core/hcd.h>
++#else
++#include <linux/usb/hcd.h>
++#endif
++#include <asm/bug.h>
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30))
++#define USB_URB_EP_LINKING 1
++#else
++#define USB_URB_EP_LINKING 0
++#endif
++
++#include "dwc_otg_hcd_if.h"
++#include "dwc_otg_dbg.h"
++#include "dwc_otg_driver.h"
++#include "dwc_otg_hcd.h"
++
++extern unsigned char _dwc_otg_fiq_stub, _dwc_otg_fiq_stub_end;
++
++/**
++ * Gets the endpoint number from a _bEndpointAddress argument. The endpoint is
++ * qualified with its direction (possible 32 endpoints per device).
++ */
++#define dwc_ep_addr_to_endpoint(_bEndpointAddress_) ((_bEndpointAddress_ & USB_ENDPOINT_NUMBER_MASK) | \
++ ((_bEndpointAddress_ & USB_DIR_IN) != 0) << 4)
++
++static const char dwc_otg_hcd_name[] = "dwc_otg_hcd";
++
++extern bool fiq_enable;
++
++/** @name Linux HC Driver API Functions */
++/** @{ */
++/* manage i/o requests, device state */
++static int dwc_otg_urb_enqueue(struct usb_hcd *hcd,
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
++ struct usb_host_endpoint *ep,
++#endif
++ struct urb *urb, gfp_t mem_flags);
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
++static int dwc_otg_urb_dequeue(struct usb_hcd *hcd, struct urb *urb);
++#endif
++#else /* kernels at or post 2.6.30 */
++static int dwc_otg_urb_dequeue(struct usb_hcd *hcd,
++ struct urb *urb, int status);
++#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30) */
++
++static void endpoint_disable(struct usb_hcd *hcd, struct usb_host_endpoint *ep);
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30)
++static void endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep);
++#endif
++static irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *hcd);
++extern int hcd_start(struct usb_hcd *hcd);
++extern void hcd_stop(struct usb_hcd *hcd);
++static int get_frame_number(struct usb_hcd *hcd);
++extern int hub_status_data(struct usb_hcd *hcd, char *buf);
++extern int hub_control(struct usb_hcd *hcd,
++ u16 typeReq,
++ u16 wValue, u16 wIndex, char *buf, u16 wLength);
++
++struct wrapper_priv_data {
++ dwc_otg_hcd_t *dwc_otg_hcd;
++};
++
++/** @} */
++
++static struct hc_driver dwc_otg_hc_driver = {
++
++ .description = dwc_otg_hcd_name,
++ .product_desc = "DWC OTG Controller",
++ .hcd_priv_size = sizeof(struct wrapper_priv_data),
++
++ .irq = dwc_otg_hcd_irq,
++
++ .flags = HCD_MEMORY | HCD_USB2,
++
++ //.reset =
++ .start = hcd_start,
++ //.suspend =
++ //.resume =
++ .stop = hcd_stop,
++
++ .urb_enqueue = dwc_otg_urb_enqueue,
++ .urb_dequeue = dwc_otg_urb_dequeue,
++ .endpoint_disable = endpoint_disable,
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30)
++ .endpoint_reset = endpoint_reset,
++#endif
++ .get_frame_number = get_frame_number,
++
++ .hub_status_data = hub_status_data,
++ .hub_control = hub_control,
++ //.bus_suspend =
++ //.bus_resume =
++};
++
++/** Gets the dwc_otg_hcd from a struct usb_hcd */
++static inline dwc_otg_hcd_t *hcd_to_dwc_otg_hcd(struct usb_hcd *hcd)
++{
++ struct wrapper_priv_data *p;
++ p = (struct wrapper_priv_data *)(hcd->hcd_priv);
++ return p->dwc_otg_hcd;
++}
++
++/** Gets the struct usb_hcd that contains a dwc_otg_hcd_t. */
++static inline struct usb_hcd *dwc_otg_hcd_to_hcd(dwc_otg_hcd_t * dwc_otg_hcd)
++{
++ return dwc_otg_hcd_get_priv_data(dwc_otg_hcd);
++}
++
++/** Gets the usb_host_endpoint associated with an URB. */
++inline struct usb_host_endpoint *dwc_urb_to_endpoint(struct urb *urb)
++{
++ struct usb_device *dev = urb->dev;
++ int ep_num = usb_pipeendpoint(urb->pipe);
++
++ if (usb_pipein(urb->pipe))
++ return dev->ep_in[ep_num];
++ else
++ return dev->ep_out[ep_num];
++}
++
++static int _disconnect(dwc_otg_hcd_t * hcd)
++{
++ struct usb_hcd *usb_hcd = dwc_otg_hcd_to_hcd(hcd);
++
++ usb_hcd->self.is_b_host = 0;
++ return 0;
++}
++
++static int _start(dwc_otg_hcd_t * hcd)
++{
++ struct usb_hcd *usb_hcd = dwc_otg_hcd_to_hcd(hcd);
++
++ usb_hcd->self.is_b_host = dwc_otg_hcd_is_b_host(hcd);
++ hcd_start(usb_hcd);
++
++ return 0;
++}
++
++static int _hub_info(dwc_otg_hcd_t * hcd, void *urb_handle, uint32_t * hub_addr,
++ uint32_t * port_addr)
++{
++ struct urb *urb = (struct urb *)urb_handle;
++ struct usb_bus *bus;
++#if 1 //GRAYG - temporary
++ if (NULL == urb_handle)
++ DWC_ERROR("**** %s - NULL URB handle\n", __func__);//GRAYG
++ if (NULL == urb->dev)
++ DWC_ERROR("**** %s - URB has no device\n", __func__);//GRAYG
++ if (NULL == port_addr)
++ DWC_ERROR("**** %s - NULL port_address\n", __func__);//GRAYG
++#endif
++ if (urb->dev->tt) {
++ if (NULL == urb->dev->tt->hub) {
++ DWC_ERROR("**** %s - (URB's transactor has no TT - giving no hub)\n",
++ __func__); //GRAYG
++ //*hub_addr = (u8)usb_pipedevice(urb->pipe); //GRAYG
++ *hub_addr = 0; //GRAYG
++ // we probably shouldn't have a transaction translator if
++ // there's no associated hub?
++ } else {
++ bus = hcd_to_bus(dwc_otg_hcd_to_hcd(hcd));
++ if (urb->dev->tt->hub == bus->root_hub)
++ *hub_addr = 0;
++ else
++ *hub_addr = urb->dev->tt->hub->devnum;
++ }
++ *port_addr = urb->dev->tt->multi ? urb->dev->ttport : 1;
++ } else {
++ *hub_addr = 0;
++ *port_addr = urb->dev->ttport;
++ }
++ return 0;
++}
++
++static int _speed(dwc_otg_hcd_t * hcd, void *urb_handle)
++{
++ struct urb *urb = (struct urb *)urb_handle;
++ return urb->dev->speed;
++}
++
++static int _get_b_hnp_enable(dwc_otg_hcd_t * hcd)
++{
++ struct usb_hcd *usb_hcd = dwc_otg_hcd_to_hcd(hcd);
++ return usb_hcd->self.b_hnp_enable;
++}
++
++static void allocate_bus_bandwidth(struct usb_hcd *hcd, uint32_t bw,
++ struct urb *urb)
++{
++ hcd_to_bus(hcd)->bandwidth_allocated += bw / urb->interval;
++ if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
++ hcd_to_bus(hcd)->bandwidth_isoc_reqs++;
++ } else {
++ hcd_to_bus(hcd)->bandwidth_int_reqs++;
++ }
++}
++
++static void free_bus_bandwidth(struct usb_hcd *hcd, uint32_t bw,
++ struct urb *urb)
++{
++ hcd_to_bus(hcd)->bandwidth_allocated -= bw / urb->interval;
++ if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
++ hcd_to_bus(hcd)->bandwidth_isoc_reqs--;
++ } else {
++ hcd_to_bus(hcd)->bandwidth_int_reqs--;
++ }
++}
++
++/**
++ * Sets the final status of an URB and returns it to the device driver. Any
++ * required cleanup of the URB is performed. The HCD lock should be held on
++ * entry.
++ */
++static int _complete(dwc_otg_hcd_t * hcd, void *urb_handle,
++ dwc_otg_hcd_urb_t * dwc_otg_urb, int32_t status)
++{
++ struct urb *urb = (struct urb *)urb_handle;
++ urb_tq_entry_t *new_entry;
++ int rc = 0;
++ if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
++ DWC_PRINTF("%s: urb %p, device %d, ep %d %s, status=%d\n",
++ __func__, urb, usb_pipedevice(urb->pipe),
++ usb_pipeendpoint(urb->pipe),
++ usb_pipein(urb->pipe) ? "IN" : "OUT", status);
++ if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
++ int i;
++ for (i = 0; i < urb->number_of_packets; i++) {
++ DWC_PRINTF(" ISO Desc %d status: %d\n",
++ i, urb->iso_frame_desc[i].status);
++ }
++ }
++ }
++ new_entry = DWC_ALLOC_ATOMIC(sizeof(urb_tq_entry_t));
++ urb->actual_length = dwc_otg_hcd_urb_get_actual_length(dwc_otg_urb);
++ /* Convert status value. */
++ switch (status) {
++ case -DWC_E_PROTOCOL:
++ status = -EPROTO;
++ break;
++ case -DWC_E_IN_PROGRESS:
++ status = -EINPROGRESS;
++ break;
++ case -DWC_E_PIPE:
++ status = -EPIPE;
++ break;
++ case -DWC_E_IO:
++ status = -EIO;
++ break;
++ case -DWC_E_TIMEOUT:
++ status = -ETIMEDOUT;
++ break;
++ case -DWC_E_OVERFLOW:
++ status = -EOVERFLOW;
++ break;
++ case -DWC_E_SHUTDOWN:
++ status = -ESHUTDOWN;
++ break;
++ default:
++ if (status) {
++ DWC_PRINTF("Uknown urb status %d\n", status);
++
++ }
++ }
++
++ if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
++ int i;
++
++ urb->error_count = dwc_otg_hcd_urb_get_error_count(dwc_otg_urb);
++ for (i = 0; i < urb->number_of_packets; ++i) {
++ urb->iso_frame_desc[i].actual_length =
++ dwc_otg_hcd_urb_get_iso_desc_actual_length
++ (dwc_otg_urb, i);
++ urb->iso_frame_desc[i].status =
++ dwc_otg_hcd_urb_get_iso_desc_status(dwc_otg_urb, i);
++ }
++ }
++
++ urb->status = status;
++ urb->hcpriv = NULL;
++ if (!status) {
++ if ((urb->transfer_flags & URB_SHORT_NOT_OK) &&
++ (urb->actual_length < urb->transfer_buffer_length)) {
++ urb->status = -EREMOTEIO;
++ }
++ }
++
++ if ((usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) ||
++ (usb_pipetype(urb->pipe) == PIPE_INTERRUPT)) {
++ struct usb_host_endpoint *ep = dwc_urb_to_endpoint(urb);
++ if (ep) {
++ free_bus_bandwidth(dwc_otg_hcd_to_hcd(hcd),
++ dwc_otg_hcd_get_ep_bandwidth(hcd,
++ ep->hcpriv),
++ urb);
++ }
++ }
++ DWC_FREE(dwc_otg_urb);
++ if (!new_entry) {
++ DWC_ERROR("dwc_otg_hcd: complete: cannot allocate URB TQ entry\n");
++ urb->status = -EPROTO;
++ /* don't schedule the tasklet -
++ * directly return the packet here with error. */
++#if USB_URB_EP_LINKING
++ usb_hcd_unlink_urb_from_ep(dwc_otg_hcd_to_hcd(hcd), urb);
++#endif
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
++ usb_hcd_giveback_urb(dwc_otg_hcd_to_hcd(hcd), urb);
++#else
++ usb_hcd_giveback_urb(dwc_otg_hcd_to_hcd(hcd), urb, urb->status);
++#endif
++ } else {
++ new_entry->urb = urb;
++#if USB_URB_EP_LINKING
++ rc = usb_hcd_check_unlink_urb(dwc_otg_hcd_to_hcd(hcd), urb, urb->status);
++ if(0 == rc) {
++ usb_hcd_unlink_urb_from_ep(dwc_otg_hcd_to_hcd(hcd), urb);
++ }
++#endif
++ if(0 == rc) {
++ DWC_TAILQ_INSERT_TAIL(&hcd->completed_urb_list, new_entry,
++ urb_tq_entries);
++ DWC_TASK_HI_SCHEDULE(hcd->completion_tasklet);
++ }
++ }
++ return 0;
++}
++
++static struct dwc_otg_hcd_function_ops hcd_fops = {
++ .start = _start,
++ .disconnect = _disconnect,
++ .hub_info = _hub_info,
++ .speed = _speed,
++ .complete = _complete,
++ .get_b_hnp_enable = _get_b_hnp_enable,
++};
++
++static struct fiq_handler fh = {
++ .name = "usb_fiq",
++};
++
++static void hcd_init_fiq(void *cookie)
++{
++ dwc_otg_device_t *otg_dev = cookie;
++ dwc_otg_hcd_t *dwc_otg_hcd = otg_dev->hcd;
++ struct pt_regs regs;
++
++ if (claim_fiq(&fh)) {
++ DWC_ERROR("Can't claim FIQ");
++ BUG();
++ }
++ DWC_WARN("FIQ on core %d at 0x%08x",
++ smp_processor_id(),
++ (fiq_fsm_enable ? (int)&dwc_otg_fiq_fsm : (int)&dwc_otg_fiq_nop));
++ DWC_WARN("FIQ ASM at 0x%08x length %d", (int)&_dwc_otg_fiq_stub, (int)(&_dwc_otg_fiq_stub_end - &_dwc_otg_fiq_stub));
++ set_fiq_handler((void *) &_dwc_otg_fiq_stub, &_dwc_otg_fiq_stub_end - &_dwc_otg_fiq_stub);
++ memset(&regs,0,sizeof(regs));
++
++ regs.ARM_r8 = (long) dwc_otg_hcd->fiq_state;
++ if (fiq_fsm_enable) {
++ regs.ARM_r9 = dwc_otg_hcd->core_if->core_params->host_channels;
++ //regs.ARM_r10 = dwc_otg_hcd->dma;
++ regs.ARM_fp = (long) dwc_otg_fiq_fsm;
++ } else {
++ regs.ARM_fp = (long) dwc_otg_fiq_nop;
++ }
++
++ regs.ARM_sp = (long) dwc_otg_hcd->fiq_stack + (sizeof(struct fiq_stack) - 4);
++
++// __show_regs(&regs);
++ set_fiq_regs(&regs);
++
++ //Set the mphi periph to the required registers
++ dwc_otg_hcd->fiq_state->mphi_regs.base = otg_dev->os_dep.mphi_base;
++ dwc_otg_hcd->fiq_state->mphi_regs.ctrl = otg_dev->os_dep.mphi_base + 0x4c;
++ dwc_otg_hcd->fiq_state->mphi_regs.outdda = otg_dev->os_dep.mphi_base + 0x28;
++ dwc_otg_hcd->fiq_state->mphi_regs.outddb = otg_dev->os_dep.mphi_base + 0x2c;
++ dwc_otg_hcd->fiq_state->mphi_regs.intstat = otg_dev->os_dep.mphi_base + 0x50;
++ dwc_otg_hcd->fiq_state->dwc_regs_base = otg_dev->os_dep.base;
++ DWC_WARN("MPHI regs_base at 0x%08x", (int)dwc_otg_hcd->fiq_state->mphi_regs.base);
++ //Enable mphi peripheral
++ writel((1<<31),dwc_otg_hcd->fiq_state->mphi_regs.ctrl);
++#ifdef DEBUG
++ if (readl(dwc_otg_hcd->fiq_state->mphi_regs.ctrl) & 0x80000000)
++ DWC_WARN("MPHI periph has been enabled");
++ else
++ DWC_WARN("MPHI periph has NOT been enabled");
++#endif
++ // Enable FIQ interrupt from USB peripheral
++#ifdef CONFIG_ARCH_BCM2835
++ enable_fiq(platform_get_irq(otg_dev->os_dep.platformdev, 1));
++#else
++ enable_fiq(INTERRUPT_VC_USB);
++#endif
++ local_fiq_enable();
++}
++
++/**
++ * Initializes the HCD. This function allocates memory for and initializes the
++ * static parts of the usb_hcd and dwc_otg_hcd structures. It also registers the
++ * USB bus with the core and calls the hc_driver->start() function. It returns
++ * a negative error on failure.
++ */
++int hcd_init(dwc_bus_dev_t *_dev)
++{
++ struct usb_hcd *hcd = NULL;
++ dwc_otg_hcd_t *dwc_otg_hcd = NULL;
++ dwc_otg_device_t *otg_dev = DWC_OTG_BUSDRVDATA(_dev);
++ int retval = 0;
++ u64 dmamask;
++
++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD INIT otg_dev=%p\n", otg_dev);
++
++ /* Set device flags indicating whether the HCD supports DMA. */
++ if (dwc_otg_is_dma_enable(otg_dev->core_if))
++ dmamask = DMA_BIT_MASK(32);
++ else
++ dmamask = 0;
++
++#if defined(LM_INTERFACE) || defined(PLATFORM_INTERFACE)
++ dma_set_mask(&_dev->dev, dmamask);
++ dma_set_coherent_mask(&_dev->dev, dmamask);
++#elif defined(PCI_INTERFACE)
++ pci_set_dma_mask(_dev, dmamask);
++ pci_set_consistent_dma_mask(_dev, dmamask);
++#endif
++
++ /*
++ * Allocate memory for the base HCD plus the DWC OTG HCD.
++ * Initialize the base HCD.
++ */
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)
++ hcd = usb_create_hcd(&dwc_otg_hc_driver, &_dev->dev, _dev->dev.bus_id);
++#else
++ hcd = usb_create_hcd(&dwc_otg_hc_driver, &_dev->dev, dev_name(&_dev->dev));
++ hcd->has_tt = 1;
++// hcd->uses_new_polling = 1;
++// hcd->poll_rh = 0;
++#endif
++ if (!hcd) {
++ retval = -ENOMEM;
++ goto error1;
++ }
++
++ hcd->regs = otg_dev->os_dep.base;
++
++
++ /* Initialize the DWC OTG HCD. */
++ dwc_otg_hcd = dwc_otg_hcd_alloc_hcd();
++ if (!dwc_otg_hcd) {
++ goto error2;
++ }
++ ((struct wrapper_priv_data *)(hcd->hcd_priv))->dwc_otg_hcd =
++ dwc_otg_hcd;
++ otg_dev->hcd = dwc_otg_hcd;
++
++ if (dwc_otg_hcd_init(dwc_otg_hcd, otg_dev->core_if)) {
++ goto error2;
++ }
++
++ if (fiq_enable) {
++ if (num_online_cpus() > 1) {
++ /* bcm2709: can run the FIQ on a separate core to IRQs */
++ smp_call_function_single(1, hcd_init_fiq, otg_dev, 1);
++ } else {
++ smp_call_function_single(0, hcd_init_fiq, otg_dev, 1);
++ }
++ }
++
++ otg_dev->hcd->otg_dev = otg_dev;
++ hcd->self.otg_port = dwc_otg_hcd_otg_port(dwc_otg_hcd);
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,33) //don't support for LM(with 2.6.20.1 kernel)
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35) //version field absent later
++ hcd->self.otg_version = dwc_otg_get_otg_version(otg_dev->core_if);
++#endif
++ /* Don't support SG list at this point */
++ hcd->self.sg_tablesize = 0;
++#endif
++ /*
++ * Finish generic HCD initialization and start the HCD. This function
++ * allocates the DMA buffer pool, registers the USB bus, requests the
++ * IRQ line, and calls hcd_start method.
++ */
++#ifdef PLATFORM_INTERFACE
++ retval = usb_add_hcd(hcd, platform_get_irq(_dev, fiq_enable ? 0 : 1), IRQF_SHARED);
++#else
++ retval = usb_add_hcd(hcd, _dev->irq, IRQF_SHARED);
++#endif
++ if (retval < 0) {
++ goto error2;
++ }
++
++ dwc_otg_hcd_set_priv_data(dwc_otg_hcd, hcd);
++ return 0;
++
++error2:
++ usb_put_hcd(hcd);
++error1:
++ return retval;
++}
++
++/**
++ * Removes the HCD.
++ * Frees memory and resources associated with the HCD and deregisters the bus.
++ */
++void hcd_remove(dwc_bus_dev_t *_dev)
++{
++ dwc_otg_device_t *otg_dev = DWC_OTG_BUSDRVDATA(_dev);
++ dwc_otg_hcd_t *dwc_otg_hcd;
++ struct usb_hcd *hcd;
++
++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD REMOVE otg_dev=%p\n", otg_dev);
++
++ if (!otg_dev) {
++ DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
++ return;
++ }
++
++ dwc_otg_hcd = otg_dev->hcd;
++
++ if (!dwc_otg_hcd) {
++ DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
++ return;
++ }
++
++ hcd = dwc_otg_hcd_to_hcd(dwc_otg_hcd);
++
++ if (!hcd) {
++ DWC_DEBUGPL(DBG_ANY,
++ "%s: dwc_otg_hcd_to_hcd(dwc_otg_hcd) NULL!\n",
++ __func__);
++ return;
++ }
++ usb_remove_hcd(hcd);
++ dwc_otg_hcd_set_priv_data(dwc_otg_hcd, NULL);
++ dwc_otg_hcd_remove(dwc_otg_hcd);
++ usb_put_hcd(hcd);
++}
++
++/* =========================================================================
++ * Linux HC Driver Functions
++ * ========================================================================= */
++
++/** Initializes the DWC_otg controller and its root hub and prepares it for host
++ * mode operation. Activates the root port. Returns 0 on success and a negative
++ * error code on failure. */
++int hcd_start(struct usb_hcd *hcd)
++{
++ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
++ struct usb_bus *bus;
++
++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD START\n");
++ bus = hcd_to_bus(hcd);
++
++ hcd->state = HC_STATE_RUNNING;
++ if (dwc_otg_hcd_start(dwc_otg_hcd, &hcd_fops)) {
++ return 0;
++ }
++
++ /* Initialize and connect root hub if one is not already attached */
++ if (bus->root_hub) {
++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Has Root Hub\n");
++ /* Inform the HUB driver to resume. */
++ usb_hcd_resume_root_hub(hcd);
++ }
++
++ return 0;
++}
++
++/**
++ * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
++ * stopped.
++ */
++void hcd_stop(struct usb_hcd *hcd)
++{
++ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
++
++ dwc_otg_hcd_stop(dwc_otg_hcd);
++}
++
++/** Returns the current frame number. */
++static int get_frame_number(struct usb_hcd *hcd)
++{
++ hprt0_data_t hprt0;
++ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
++ hprt0.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
++ if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED)
++ return dwc_otg_hcd_get_frame_number(dwc_otg_hcd) >> 3;
++ else
++ return dwc_otg_hcd_get_frame_number(dwc_otg_hcd);
++}
++
++#ifdef DEBUG
++static void dump_urb_info(struct urb *urb, char *fn_name)
++{
++ DWC_PRINTF("%s, urb %p\n", fn_name, urb);
++ DWC_PRINTF(" Device address: %d\n", usb_pipedevice(urb->pipe));
++ DWC_PRINTF(" Endpoint: %d, %s\n", usb_pipeendpoint(urb->pipe),
++ (usb_pipein(urb->pipe) ? "IN" : "OUT"));
++ DWC_PRINTF(" Endpoint type: %s\n", ( {
++ char *pipetype;
++ switch (usb_pipetype(urb->pipe)) {
++case PIPE_CONTROL:
++pipetype = "CONTROL"; break; case PIPE_BULK:
++pipetype = "BULK"; break; case PIPE_INTERRUPT:
++pipetype = "INTERRUPT"; break; case PIPE_ISOCHRONOUS:
++pipetype = "ISOCHRONOUS"; break; default:
++ pipetype = "UNKNOWN"; break;};
++ pipetype;}
++ )) ;
++ DWC_PRINTF(" Speed: %s\n", ( {
++ char *speed; switch (urb->dev->speed) {
++case USB_SPEED_HIGH:
++speed = "HIGH"; break; case USB_SPEED_FULL:
++speed = "FULL"; break; case USB_SPEED_LOW:
++speed = "LOW"; break; default:
++ speed = "UNKNOWN"; break;};
++ speed;}
++ )) ;
++ DWC_PRINTF(" Max packet size: %d\n",
++ usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
++ DWC_PRINTF(" Data buffer length: %d\n", urb->transfer_buffer_length);
++ DWC_PRINTF(" Transfer buffer: %p, Transfer DMA: %p\n",
++ urb->transfer_buffer, (void *)urb->transfer_dma);
++ DWC_PRINTF(" Setup buffer: %p, Setup DMA: %p\n",
++ urb->setup_packet, (void *)urb->setup_dma);
++ DWC_PRINTF(" Interval: %d\n", urb->interval);
++ if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
++ int i;
++ for (i = 0; i < urb->number_of_packets; i++) {
++ DWC_PRINTF(" ISO Desc %d:\n", i);
++ DWC_PRINTF(" offset: %d, length %d\n",
++ urb->iso_frame_desc[i].offset,
++ urb->iso_frame_desc[i].length);
++ }
++ }
++}
++#endif
++
++/** Starts processing a USB transfer request specified by a USB Request Block
++ * (URB). mem_flags indicates the type of memory allocation to use while
++ * processing this URB. */
++static int dwc_otg_urb_enqueue(struct usb_hcd *hcd,
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
++ struct usb_host_endpoint *ep,
++#endif
++ struct urb *urb, gfp_t mem_flags)
++{
++ int retval = 0;
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,28)
++ struct usb_host_endpoint *ep = urb->ep;
++#endif
++ dwc_irqflags_t irqflags;
++ void **ref_ep_hcpriv = &ep->hcpriv;
++ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
++ dwc_otg_hcd_urb_t *dwc_otg_urb;
++ int i;
++ int alloc_bandwidth = 0;
++ uint8_t ep_type = 0;
++ uint32_t flags = 0;
++ void *buf;
++
++#ifdef DEBUG
++ if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
++ dump_urb_info(urb, "dwc_otg_urb_enqueue");
++ }
++#endif
++
++ if (!urb->transfer_buffer && urb->transfer_buffer_length)
++ return -EINVAL;
++
++ if ((usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
++ || (usb_pipetype(urb->pipe) == PIPE_INTERRUPT)) {
++ if (!dwc_otg_hcd_is_bandwidth_allocated
++ (dwc_otg_hcd, ref_ep_hcpriv)) {
++ alloc_bandwidth = 1;
++ }
++ }
++
++ switch (usb_pipetype(urb->pipe)) {
++ case PIPE_CONTROL:
++ ep_type = USB_ENDPOINT_XFER_CONTROL;
++ break;
++ case PIPE_ISOCHRONOUS:
++ ep_type = USB_ENDPOINT_XFER_ISOC;
++ break;
++ case PIPE_BULK:
++ ep_type = USB_ENDPOINT_XFER_BULK;
++ break;
++ case PIPE_INTERRUPT:
++ ep_type = USB_ENDPOINT_XFER_INT;
++ break;
++ default:
++ DWC_WARN("Wrong EP type - %d\n", usb_pipetype(urb->pipe));
++ }
++
++ /* # of packets is often 0 - do we really need to call this then? */
++ dwc_otg_urb = dwc_otg_hcd_urb_alloc(dwc_otg_hcd,
++ urb->number_of_packets,
++ mem_flags == GFP_ATOMIC ? 1 : 0);
++
++ if(dwc_otg_urb == NULL)
++ return -ENOMEM;
++
++ if (!dwc_otg_urb && urb->number_of_packets)
++ return -ENOMEM;
++
++ dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_urb, usb_pipedevice(urb->pipe),
++ usb_pipeendpoint(urb->pipe), ep_type,
++ usb_pipein(urb->pipe),
++ usb_maxpacket(urb->dev, urb->pipe,
++ !(usb_pipein(urb->pipe))));
++
++ buf = urb->transfer_buffer;
++ if (hcd->self.uses_dma && !buf && urb->transfer_buffer_length) {
++ /*
++ * Calculate virtual address from physical address,
++ * because some class driver may not fill transfer_buffer.
++ * In Buffer DMA mode virual address is used,
++ * when handling non DWORD aligned buffers.
++ */
++ buf = (void *)__bus_to_virt((unsigned long)urb->transfer_dma);
++ dev_warn_once(&urb->dev->dev,
++ "USB transfer_buffer was NULL, will use __bus_to_virt(%pad)=%p\n",
++ &urb->transfer_dma, buf);
++ }
++
++ if (!(urb->transfer_flags & URB_NO_INTERRUPT))
++ flags |= URB_GIVEBACK_ASAP;
++ if (urb->transfer_flags & URB_ZERO_PACKET)
++ flags |= URB_SEND_ZERO_PACKET;
++
++ dwc_otg_hcd_urb_set_params(dwc_otg_urb, urb, buf,
++ urb->transfer_dma,
++ urb->transfer_buffer_length,
++ urb->setup_packet,
++ urb->setup_dma, flags, urb->interval);
++
++ for (i = 0; i < urb->number_of_packets; ++i) {
++ dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_urb, i,
++ urb->
++ iso_frame_desc[i].offset,
++ urb->
++ iso_frame_desc[i].length);
++ }
++
++ DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &irqflags);
++ urb->hcpriv = dwc_otg_urb;
++#if USB_URB_EP_LINKING
++ retval = usb_hcd_link_urb_to_ep(hcd, urb);
++ if (0 == retval)
++#endif
++ {
++ retval = dwc_otg_hcd_urb_enqueue(dwc_otg_hcd, dwc_otg_urb,
++ /*(dwc_otg_qh_t **)*/
++ ref_ep_hcpriv, 1);
++ if (0 == retval) {
++ if (alloc_bandwidth) {
++ allocate_bus_bandwidth(hcd,
++ dwc_otg_hcd_get_ep_bandwidth(
++ dwc_otg_hcd, *ref_ep_hcpriv),
++ urb);
++ }
++ } else {
++ DWC_DEBUGPL(DBG_HCD, "DWC OTG dwc_otg_hcd_urb_enqueue failed rc %d\n", retval);
++#if USB_URB_EP_LINKING
++ usb_hcd_unlink_urb_from_ep(hcd, urb);
++#endif
++ DWC_FREE(dwc_otg_urb);
++ urb->hcpriv = NULL;
++ if (retval == -DWC_E_NO_DEVICE)
++ retval = -ENODEV;
++ }
++ }
++#if USB_URB_EP_LINKING
++ else
++ {
++ DWC_FREE(dwc_otg_urb);
++ urb->hcpriv = NULL;
++ }
++#endif
++ DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, irqflags);
++ return retval;
++}
++
++/** Aborts/cancels a USB transfer request. Always returns 0 to indicate
++ * success. */
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
++static int dwc_otg_urb_dequeue(struct usb_hcd *hcd, struct urb *urb)
++#else
++static int dwc_otg_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
++#endif
++{
++ dwc_irqflags_t flags;
++ dwc_otg_hcd_t *dwc_otg_hcd;
++ int rc;
++
++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue\n");
++
++ dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
++
++#ifdef DEBUG
++ if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
++ dump_urb_info(urb, "dwc_otg_urb_dequeue");
++ }
++#endif
++
++ DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
++ rc = usb_hcd_check_unlink_urb(hcd, urb, status);
++ if (0 == rc) {
++ if(urb->hcpriv != NULL) {
++ dwc_otg_hcd_urb_dequeue(dwc_otg_hcd,
++ (dwc_otg_hcd_urb_t *)urb->hcpriv);
++
++ DWC_FREE(urb->hcpriv);
++ urb->hcpriv = NULL;
++ }
++ }
++
++ if (0 == rc) {
++ /* Higher layer software sets URB status. */
++#if USB_URB_EP_LINKING
++ usb_hcd_unlink_urb_from_ep(hcd, urb);
++#endif
++ DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags);
++
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
++ usb_hcd_giveback_urb(hcd, urb);
++#else
++ usb_hcd_giveback_urb(hcd, urb, status);
++#endif
++ if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
++ DWC_PRINTF("Called usb_hcd_giveback_urb() \n");
++ DWC_PRINTF(" 1urb->status = %d\n", urb->status);
++ }
++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue OK\n");
++ } else {
++ DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags);
++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue failed - rc %d\n",
++ rc);
++ }
++
++ return rc;
++}
++
++/* Frees resources in the DWC_otg controller related to a given endpoint. Also
++ * clears state in the HCD related to the endpoint. Any URBs for the endpoint
++ * must already be dequeued. */
++static void endpoint_disable(struct usb_hcd *hcd, struct usb_host_endpoint *ep)
++{
++ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
++
++ DWC_DEBUGPL(DBG_HCD,
++ "DWC OTG HCD EP DISABLE: _bEndpointAddress=0x%02x, "
++ "endpoint=%d\n", ep->desc.bEndpointAddress,
++ dwc_ep_addr_to_endpoint(ep->desc.bEndpointAddress));
++ dwc_otg_hcd_endpoint_disable(dwc_otg_hcd, ep->hcpriv, 250);
++ ep->hcpriv = NULL;
++}
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30)
++/* Resets endpoint specific parameter values, in current version used to reset
++ * the data toggle(as a WA). This function can be called from usb_clear_halt routine */
++static void endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep)
++{
++ dwc_irqflags_t flags;
++ struct usb_device *udev = NULL;
++ int epnum = usb_endpoint_num(&ep->desc);
++ int is_out = usb_endpoint_dir_out(&ep->desc);
++ int is_control = usb_endpoint_xfer_control(&ep->desc);
++ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
++ struct device *dev = DWC_OTG_OS_GETDEV(dwc_otg_hcd->otg_dev->os_dep);
++
++ if (dev)
++ udev = to_usb_device(dev);
++ else
++ return;
++
++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD EP RESET: Endpoint Num=0x%02d\n", epnum);
++
++ DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
++ usb_settoggle(udev, epnum, is_out, 0);
++ if (is_control)
++ usb_settoggle(udev, epnum, !is_out, 0);
++
++ if (ep->hcpriv) {
++ dwc_otg_hcd_endpoint_reset(dwc_otg_hcd, ep->hcpriv);
++ }
++ DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags);
++}
++#endif
++
++/** Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if
++ * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid
++ * interrupt.
++ *
++ * This function is called by the USB core when an interrupt occurs */
++static irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *hcd)
++{
++ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
++ int32_t retval = dwc_otg_hcd_handle_intr(dwc_otg_hcd);
++ if (retval != 0) {
++ S3C2410X_CLEAR_EINTPEND();
++ }
++ return IRQ_RETVAL(retval);
++}
++
++/** Creates Status Change bitmap for the root hub and root port. The bitmap is
++ * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1
++ * is the status change indicator for the single root port. Returns 1 if either
++ * change indicator is 1, otherwise returns 0. */
++int hub_status_data(struct usb_hcd *hcd, char *buf)
++{
++ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
++
++ buf[0] = 0;
++ buf[0] |= (dwc_otg_hcd_is_status_changed(dwc_otg_hcd, 1)) << 1;
++
++ return (buf[0] != 0);
++}
++
++/** Handles hub class-specific requests. */
++int hub_control(struct usb_hcd *hcd,
++ u16 typeReq, u16 wValue, u16 wIndex, char *buf, u16 wLength)
++{
++ int retval;
++
++ retval = dwc_otg_hcd_hub_control(hcd_to_dwc_otg_hcd(hcd),
++ typeReq, wValue, wIndex, buf, wLength);
++
++ switch (retval) {
++ case -DWC_E_INVALID:
++ retval = -EINVAL;
++ break;
++ }
++
++ return retval;
++}
++
++#endif /* DWC_DEVICE_ONLY */
+diff -Nur linux-4.1.3/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c linux-xbian-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c
+--- linux-4.1.3/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c 2015-07-28 01:20:58.449142252 +0200
+@@ -0,0 +1,957 @@
++/* ==========================================================================
++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_queue.c $
++ * $Revision: #44 $
++ * $Date: 2011/10/26 $
++ * $Change: 1873028 $
++ *
++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++ * otherwise expressly agreed to in writing between Synopsys and you.
++ *
++ * The Software IS NOT an item of Licensed Software or Licensed Product under
++ * any End User Software License Agreement or Agreement for Licensed Product
++ * with Synopsys or any supplement thereto. You are permitted to use and
++ * redistribute this Software in source and binary forms, with or without
++ * modification, provided that redistributions of source code must retain this
++ * notice. You may not view, use, disclose, copy or distribute this file or
++ * any information contained herein except pursuant to this license grant from
++ * Synopsys. If you do not agree with this notice, including the disclaimer
++ * below, then you are not authorized to use the Software.
++ *
++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++ * DAMAGE.
++ * ========================================================================== */
++#ifndef DWC_DEVICE_ONLY
++
++/**
++ * @file
++ *
++ * This file contains the functions to manage Queue Heads and Queue
++ * Transfer Descriptors.
++ */
++
++#include "dwc_otg_hcd.h"
++#include "dwc_otg_regs.h"
++
++extern bool microframe_schedule;
++
++/**
++ * Free each QTD in the QH's QTD-list then free the QH. QH should already be
++ * removed from a list. QTD list should already be empty if called from URB
++ * Dequeue.
++ *
++ * @param hcd HCD instance.
++ * @param qh The QH to free.
++ */
++void dwc_otg_hcd_qh_free(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
++{
++ dwc_otg_qtd_t *qtd, *qtd_tmp;
++ dwc_irqflags_t flags;
++
++ /* Free each QTD in the QTD list */
++ DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
++ DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry) {
++ DWC_CIRCLEQ_REMOVE(&qh->qtd_list, qtd, qtd_list_entry);
++ dwc_otg_hcd_qtd_free(qtd);
++ }
++
++ if (hcd->core_if->dma_desc_enable) {
++ dwc_otg_hcd_qh_free_ddma(hcd, qh);
++ } else if (qh->dw_align_buf) {
++ uint32_t buf_size;
++ if (qh->ep_type == UE_ISOCHRONOUS) {
++ buf_size = 4096;
++ } else {
++ buf_size = hcd->core_if->core_params->max_transfer_size;
++ }
++ DWC_DMA_FREE(buf_size, qh->dw_align_buf, qh->dw_align_buf_dma);
++ }
++
++ DWC_FREE(qh);
++ DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
++ return;
++}
++
++#define BitStuffTime(bytecount) ((8 * 7* bytecount) / 6)
++#define HS_HOST_DELAY 5 /* nanoseconds */
++#define FS_LS_HOST_DELAY 1000 /* nanoseconds */
++#define HUB_LS_SETUP 333 /* nanoseconds */
++#define NS_TO_US(ns) ((ns + 500) / 1000)
++ /* convert & round nanoseconds to microseconds */
++
++static uint32_t calc_bus_time(int speed, int is_in, int is_isoc, int bytecount)
++{
++ unsigned long retval;
++
++ switch (speed) {
++ case USB_SPEED_HIGH:
++ if (is_isoc) {
++ retval =
++ ((38 * 8 * 2083) +
++ (2083 * (3 + BitStuffTime(bytecount)))) / 1000 +
++ HS_HOST_DELAY;
++ } else {
++ retval =
++ ((55 * 8 * 2083) +
++ (2083 * (3 + BitStuffTime(bytecount)))) / 1000 +
++ HS_HOST_DELAY;
++ }
++ break;
++ case USB_SPEED_FULL:
++ if (is_isoc) {
++ retval =
++ (8354 * (31 + 10 * BitStuffTime(bytecount))) / 1000;
++ if (is_in) {
++ retval = 7268 + FS_LS_HOST_DELAY + retval;
++ } else {
++ retval = 6265 + FS_LS_HOST_DELAY + retval;
++ }
++ } else {
++ retval =
++ (8354 * (31 + 10 * BitStuffTime(bytecount))) / 1000;
++ retval = 9107 + FS_LS_HOST_DELAY + retval;
++ }
++ break;
++ case USB_SPEED_LOW:
++ if (is_in) {
++ retval =
++ (67667 * (31 + 10 * BitStuffTime(bytecount))) /
++ 1000;
++ retval =
++ 64060 + (2 * HUB_LS_SETUP) + FS_LS_HOST_DELAY +
++ retval;
++ } else {
++ retval =
++ (66700 * (31 + 10 * BitStuffTime(bytecount))) /
++ 1000;
++ retval =
++ 64107 + (2 * HUB_LS_SETUP) + FS_LS_HOST_DELAY +
++ retval;
++ }
++ break;
++ default:
++ DWC_WARN("Unknown device speed\n");
++ retval = -1;
++ }
++
++ return NS_TO_US(retval);
++}
++
++/**
++ * Initializes a QH structure.
++ *
++ * @param hcd The HCD state structure for the DWC OTG controller.
++ * @param qh The QH to init.
++ * @param urb Holds the information about the device/endpoint that we need
++ * to initialize the QH.
++ */
++#define SCHEDULE_SLOP 10
++void qh_init(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, dwc_otg_hcd_urb_t * urb)
++{
++ char *speed, *type;
++ int dev_speed;
++ uint32_t hub_addr, hub_port;
++
++ dwc_memset(qh, 0, sizeof(dwc_otg_qh_t));
++
++ /* Initialize QH */
++ qh->ep_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info);
++ qh->ep_is_in = dwc_otg_hcd_is_pipe_in(&urb->pipe_info) ? 1 : 0;
++
++ qh->data_toggle = DWC_OTG_HC_PID_DATA0;
++ qh->maxp = dwc_otg_hcd_get_mps(&urb->pipe_info);
++ DWC_CIRCLEQ_INIT(&qh->qtd_list);
++ DWC_LIST_INIT(&qh->qh_list_entry);
++ qh->channel = NULL;
++
++ /* FS/LS Enpoint on HS Hub
++ * NOT virtual root hub */
++ dev_speed = hcd->fops->speed(hcd, urb->priv);
++
++ hcd->fops->hub_info(hcd, urb->priv, &hub_addr, &hub_port);
++ qh->do_split = 0;
++ if (microframe_schedule)
++ qh->speed = dev_speed;
++
++ qh->nak_frame = 0xffff;
++
++ if (((dev_speed == USB_SPEED_LOW) ||
++ (dev_speed == USB_SPEED_FULL)) &&
++ (hub_addr != 0 && hub_addr != 1)) {
++ DWC_DEBUGPL(DBG_HCD,
++ "QH init: EP %d: TT found at hub addr %d, for port %d\n",
++ dwc_otg_hcd_get_ep_num(&urb->pipe_info), hub_addr,
++ hub_port);
++ qh->do_split = 1;
++ qh->skip_count = 0;
++ }
++
++ if (qh->ep_type == UE_INTERRUPT || qh->ep_type == UE_ISOCHRONOUS) {
++ /* Compute scheduling parameters once and save them. */
++ hprt0_data_t hprt;
++
++ /** @todo Account for split transfers in the bus time. */
++ int bytecount =
++ dwc_hb_mult(qh->maxp) * dwc_max_packet(qh->maxp);
++
++ qh->usecs =
++ calc_bus_time((qh->do_split ? USB_SPEED_HIGH : dev_speed),
++ qh->ep_is_in, (qh->ep_type == UE_ISOCHRONOUS),
++ bytecount);
++ /* Start in a slightly future (micro)frame. */
++ qh->sched_frame = dwc_frame_num_inc(hcd->frame_number,
++ SCHEDULE_SLOP);
++ qh->interval = urb->interval;
++
++#if 0
++ /* Increase interrupt polling rate for debugging. */
++ if (qh->ep_type == UE_INTERRUPT) {
++ qh->interval = 8;
++ }
++#endif
++ hprt.d32 = DWC_READ_REG32(hcd->core_if->host_if->hprt0);
++ if ((hprt.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED) &&
++ ((dev_speed == USB_SPEED_LOW) ||
++ (dev_speed == USB_SPEED_FULL))) {
++ qh->interval *= 8;
++ qh->sched_frame |= 0x7;
++ qh->start_split_frame = qh->sched_frame;
++ }
++
++ }
++
++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD QH Initialized\n");
++ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - qh = %p\n", qh);
++ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Device Address = %d\n",
++ dwc_otg_hcd_get_dev_addr(&urb->pipe_info));
++ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Endpoint %d, %s\n",
++ dwc_otg_hcd_get_ep_num(&urb->pipe_info),
++ dwc_otg_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT");
++ switch (dev_speed) {
++ case USB_SPEED_LOW:
++ qh->dev_speed = DWC_OTG_EP_SPEED_LOW;
++ speed = "low";
++ break;
++ case USB_SPEED_FULL:
++ qh->dev_speed = DWC_OTG_EP_SPEED_FULL;
++ speed = "full";
++ break;
++ case USB_SPEED_HIGH:
++ qh->dev_speed = DWC_OTG_EP_SPEED_HIGH;
++ speed = "high";
++ break;
++ default:
++ speed = "?";
++ break;
++ }
++ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Speed = %s\n", speed);
++
++ switch (qh->ep_type) {
++ case UE_ISOCHRONOUS:
++ type = "isochronous";
++ break;
++ case UE_INTERRUPT:
++ type = "interrupt";
++ break;
++ case UE_CONTROL:
++ type = "control";
++ break;
++ case UE_BULK:
++ type = "bulk";
++ break;
++ default:
++ type = "?";
++ break;
++ }
++
++ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Type = %s\n", type);
++
++#ifdef DEBUG
++ if (qh->ep_type == UE_INTERRUPT) {
++ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - usecs = %d\n",
++ qh->usecs);
++ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - interval = %d\n",
++ qh->interval);
++ }
++#endif
++
++}
++
++/**
++ * This function allocates and initializes a QH.
++ *
++ * @param hcd The HCD state structure for the DWC OTG controller.
++ * @param urb Holds the information about the device/endpoint that we need
++ * to initialize the QH.
++ * @param atomic_alloc Flag to do atomic allocation if needed
++ *
++ * @return Returns pointer to the newly allocated QH, or NULL on error. */
++dwc_otg_qh_t *dwc_otg_hcd_qh_create(dwc_otg_hcd_t * hcd,
++ dwc_otg_hcd_urb_t * urb, int atomic_alloc)
++{
++ dwc_otg_qh_t *qh;
++
++ /* Allocate memory */
++ /** @todo add memflags argument */
++ qh = dwc_otg_hcd_qh_alloc(atomic_alloc);
++ if (qh == NULL) {
++ DWC_ERROR("qh allocation failed");
++ return NULL;
++ }
++
++ qh_init(hcd, qh, urb);
++
++ if (hcd->core_if->dma_desc_enable
++ && (dwc_otg_hcd_qh_init_ddma(hcd, qh) < 0)) {
++ dwc_otg_hcd_qh_free(hcd, qh);
++ return NULL;
++ }
++
++ return qh;
++}
++
++/* microframe_schedule=0 start */
++
++/**
++ * Checks that a channel is available for a periodic transfer.
++ *
++ * @return 0 if successful, negative error code otherise.
++ */
++static int periodic_channel_available(dwc_otg_hcd_t * hcd)
++{
++ /*
++ * Currently assuming that there is a dedicated host channnel for each
++ * periodic transaction plus at least one host channel for
++ * non-periodic transactions.
++ */
++ int status;
++ int num_channels;
++
++ num_channels = hcd->core_if->core_params->host_channels;
++ if ((hcd->periodic_channels + hcd->non_periodic_channels < num_channels)
++ && (hcd->periodic_channels < num_channels - 1)) {
++ status = 0;
++ } else {
++ DWC_INFO("%s: Total channels: %d, Periodic: %d, Non-periodic: %d\n",
++ __func__, num_channels, hcd->periodic_channels, hcd->non_periodic_channels); //NOTICE
++ status = -DWC_E_NO_SPACE;
++ }
++
++ return status;
++}
++
++/**
++ * Checks that there is sufficient bandwidth for the specified QH in the
++ * periodic schedule. For simplicity, this calculation assumes that all the
++ * transfers in the periodic schedule may occur in the same (micro)frame.
++ *
++ * @param hcd The HCD state structure for the DWC OTG controller.
++ * @param qh QH containing periodic bandwidth required.
++ *
++ * @return 0 if successful, negative error code otherwise.
++ */
++static int check_periodic_bandwidth(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
++{
++ int status;
++ int16_t max_claimed_usecs;
++
++ status = 0;
++
++ if ((qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) || qh->do_split) {
++ /*
++ * High speed mode.
++ * Max periodic usecs is 80% x 125 usec = 100 usec.
++ */
++
++ max_claimed_usecs = 100 - qh->usecs;
++ } else {
++ /*
++ * Full speed mode.
++ * Max periodic usecs is 90% x 1000 usec = 900 usec.
++ */
++ max_claimed_usecs = 900 - qh->usecs;
++ }
++
++ if (hcd->periodic_usecs > max_claimed_usecs) {
++ DWC_INFO("%s: already claimed usecs %d, required usecs %d\n", __func__, hcd->periodic_usecs, qh->usecs); //NOTICE
++ status = -DWC_E_NO_SPACE;
++ }
++
++ return status;
++}
++
++/* microframe_schedule=0 end */
++
++/**
++ * Microframe scheduler
++ * track the total use in hcd->frame_usecs
++ * keep each qh use in qh->frame_usecs
++ * when surrendering the qh then donate the time back
++ */
++const unsigned short max_uframe_usecs[]={ 100, 100, 100, 100, 100, 100, 30, 0 };
++
++/*
++ * called from dwc_otg_hcd.c:dwc_otg_hcd_init
++ */
++int init_hcd_usecs(dwc_otg_hcd_t *_hcd)
++{
++ int i;
++ for (i=0; i<8; i++) {
++ _hcd->frame_usecs[i] = max_uframe_usecs[i];
++ }
++ return 0;
++}
++
++static int find_single_uframe(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh)
++{
++ int i;
++ unsigned short utime;
++ int t_left;
++ int ret;
++ int done;
++
++ ret = -1;
++ utime = _qh->usecs;
++ t_left = utime;
++ i = 0;
++ done = 0;
++ while (done == 0) {
++ /* At the start _hcd->frame_usecs[i] = max_uframe_usecs[i]; */
++ if (utime <= _hcd->frame_usecs[i]) {
++ _hcd->frame_usecs[i] -= utime;
++ _qh->frame_usecs[i] += utime;
++ t_left -= utime;
++ ret = i;
++ done = 1;
++ return ret;
++ } else {
++ i++;
++ if (i == 8) {
++ done = 1;
++ ret = -1;
++ }
++ }
++ }
++ return ret;
++ }
++
++/*
++ * use this for FS apps that can span multiple uframes
++ */
++static int find_multi_uframe(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh)
++{
++ int i;
++ int j;
++ unsigned short utime;
++ int t_left;
++ int ret;
++ int done;
++ unsigned short xtime;
++
++ ret = -1;
++ utime = _qh->usecs;
++ t_left = utime;
++ i = 0;
++ done = 0;
++loop:
++ while (done == 0) {
++ if(_hcd->frame_usecs[i] <= 0) {
++ i++;
++ if (i == 8) {
++ done = 1;
++ ret = -1;
++ }
++ goto loop;
++ }
++
++ /*
++ * we need n consecutive slots
++ * so use j as a start slot j plus j+1 must be enough time (for now)
++ */
++ xtime= _hcd->frame_usecs[i];
++ for (j = i+1 ; j < 8 ; j++ ) {
++ /*
++ * if we add this frame remaining time to xtime we may
++ * be OK, if not we need to test j for a complete frame
++ */
++ if ((xtime+_hcd->frame_usecs[j]) < utime) {
++ if (_hcd->frame_usecs[j] < max_uframe_usecs[j]) {
++ j = 8;
++ ret = -1;
++ continue;
++ }
++ }
++ if (xtime >= utime) {
++ ret = i;
++ j = 8; /* stop loop with a good value ret */
++ continue;
++ }
++ /* add the frame time to x time */
++ xtime += _hcd->frame_usecs[j];
++ /* we must have a fully available next frame or break */
++ if ((xtime < utime)
++ && (_hcd->frame_usecs[j] == max_uframe_usecs[j])) {
++ ret = -1;
++ j = 8; /* stop loop with a bad value ret */
++ continue;
++ }
++ }
++ if (ret >= 0) {
++ t_left = utime;
++ for (j = i; (t_left>0) && (j < 8); j++ ) {
++ t_left -= _hcd->frame_usecs[j];
++ if ( t_left <= 0 ) {
++ _qh->frame_usecs[j] += _hcd->frame_usecs[j] + t_left;
++ _hcd->frame_usecs[j]= -t_left;
++ ret = i;
++ done = 1;
++ } else {
++ _qh->frame_usecs[j] += _hcd->frame_usecs[j];
++ _hcd->frame_usecs[j] = 0;
++ }
++ }
++ } else {
++ i++;
++ if (i == 8) {
++ done = 1;
++ ret = -1;
++ }
++ }
++ }
++ return ret;
++}
++
++static int find_uframe(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh)
++{
++ int ret;
++ ret = -1;
++
++ if (_qh->speed == USB_SPEED_HIGH) {
++ /* if this is a hs transaction we need a full frame */
++ ret = find_single_uframe(_hcd, _qh);
++ } else {
++ /* if this is a fs transaction we may need a sequence of frames */
++ ret = find_multi_uframe(_hcd, _qh);
++ }
++ return ret;
++}
++
++/**
++ * Checks that the max transfer size allowed in a host channel is large enough
++ * to handle the maximum data transfer in a single (micro)frame for a periodic
++ * transfer.
++ *
++ * @param hcd The HCD state structure for the DWC OTG controller.
++ * @param qh QH for a periodic endpoint.
++ *
++ * @return 0 if successful, negative error code otherwise.
++ */
++static int check_max_xfer_size(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
++{
++ int status;
++ uint32_t max_xfer_size;
++ uint32_t max_channel_xfer_size;
++
++ status = 0;
++
++ max_xfer_size = dwc_max_packet(qh->maxp) * dwc_hb_mult(qh->maxp);
++ max_channel_xfer_size = hcd->core_if->core_params->max_transfer_size;
++
++ if (max_xfer_size > max_channel_xfer_size) {
++ DWC_INFO("%s: Periodic xfer length %d > " "max xfer length for channel %d\n",
++ __func__, max_xfer_size, max_channel_xfer_size); //NOTICE
++ status = -DWC_E_NO_SPACE;
++ }
++
++ return status;
++}
++
++
++
++/**
++ * Schedules an interrupt or isochronous transfer in the periodic schedule.
++ *
++ * @param hcd The HCD state structure for the DWC OTG controller.
++ * @param qh QH for the periodic transfer. The QH should already contain the
++ * scheduling information.
++ *
++ * @return 0 if successful, negative error code otherwise.
++ */
++static int schedule_periodic(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
++{
++ int status = 0;
++
++ if (microframe_schedule) {
++ int frame;
++ status = find_uframe(hcd, qh);
++ frame = -1;
++ if (status == 0) {
++ frame = 7;
++ } else {
++ if (status > 0 )
++ frame = status-1;
++ }
++
++ /* Set the new frame up */
++ if (frame > -1) {
++ qh->sched_frame &= ~0x7;
++ qh->sched_frame |= (frame & 7);
++ }
++
++ if (status != -1)
++ status = 0;
++ } else {
++ status = periodic_channel_available(hcd);
++ if (status) {
++ DWC_INFO("%s: No host channel available for periodic " "transfer.\n", __func__); //NOTICE
++ return status;
++ }
++
++ status = check_periodic_bandwidth(hcd, qh);
++ }
++ if (status) {
++ DWC_INFO("%s: Insufficient periodic bandwidth for "
++ "periodic transfer.\n", __func__);
++ return status;
++ }
++ status = check_max_xfer_size(hcd, qh);
++ if (status) {
++ DWC_INFO("%s: Channel max transfer size too small "
++ "for periodic transfer.\n", __func__);
++ return status;
++ }
++
++ if (hcd->core_if->dma_desc_enable) {
++ /* Don't rely on SOF and start in ready schedule */
++ DWC_LIST_INSERT_TAIL(&hcd->periodic_sched_ready, &qh->qh_list_entry);
++ }
++ else {
++ if(fiq_enable && (DWC_LIST_EMPTY(&hcd->periodic_sched_inactive) || dwc_frame_num_le(qh->sched_frame, hcd->fiq_state->next_sched_frame)))
++ {
++ hcd->fiq_state->next_sched_frame = qh->sched_frame;
++
++ }
++ /* Always start in the inactive schedule. */
++ DWC_LIST_INSERT_TAIL(&hcd->periodic_sched_inactive, &qh->qh_list_entry);
++ }
++
++ if (!microframe_schedule) {
++ /* Reserve the periodic channel. */
++ hcd->periodic_channels++;
++ }
++
++ /* Update claimed usecs per (micro)frame. */
++ hcd->periodic_usecs += qh->usecs;
++
++ return status;
++}
++
++
++/**
++ * This function adds a QH to either the non periodic or periodic schedule if
++ * it is not already in the schedule. If the QH is already in the schedule, no
++ * action is taken.
++ *
++ * @return 0 if successful, negative error code otherwise.
++ */
++int dwc_otg_hcd_qh_add(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
++{
++ int status = 0;
++ gintmsk_data_t intr_mask = {.d32 = 0 };
++
++ if (!DWC_LIST_EMPTY(&qh->qh_list_entry)) {
++ /* QH already in a schedule. */
++ return status;
++ }
++
++ /* Add the new QH to the appropriate schedule */
++ if (dwc_qh_is_non_per(qh)) {
++ /* Always start in the inactive schedule. */
++ DWC_LIST_INSERT_TAIL(&hcd->non_periodic_sched_inactive,
++ &qh->qh_list_entry);
++ //hcd->fiq_state->kick_np_queues = 1;
++ } else {
++ status = schedule_periodic(hcd, qh);
++ if ( !hcd->periodic_qh_count ) {
++ intr_mask.b.sofintr = 1;
++ if (fiq_enable) {
++ local_fiq_disable();
++ fiq_fsm_spin_lock(&hcd->fiq_state->lock);
++ DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
++ fiq_fsm_spin_unlock(&hcd->fiq_state->lock);
++ local_fiq_enable();
++ } else {
++ DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
++ }
++ }
++ hcd->periodic_qh_count++;
++ }
++
++ return status;
++}
++
++/**
++ * Removes an interrupt or isochronous transfer from the periodic schedule.
++ *
++ * @param hcd The HCD state structure for the DWC OTG controller.
++ * @param qh QH for the periodic transfer.
++ */
++static void deschedule_periodic(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
++{
++ int i;
++ DWC_LIST_REMOVE_INIT(&qh->qh_list_entry);
++
++ /* Update claimed usecs per (micro)frame. */
++ hcd->periodic_usecs -= qh->usecs;
++
++ if (!microframe_schedule) {
++ /* Release the periodic channel reservation. */
++ hcd->periodic_channels--;
++ } else {
++ for (i = 0; i < 8; i++) {
++ hcd->frame_usecs[i] += qh->frame_usecs[i];
++ qh->frame_usecs[i] = 0;
++ }
++ }
++}
++
++/**
++ * Removes a QH from either the non-periodic or periodic schedule. Memory is
++ * not freed.
++ *
++ * @param hcd The HCD state structure.
++ * @param qh QH to remove from schedule. */
++void dwc_otg_hcd_qh_remove(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
++{
++ gintmsk_data_t intr_mask = {.d32 = 0 };
++
++ if (DWC_LIST_EMPTY(&qh->qh_list_entry)) {
++ /* QH is not in a schedule. */
++ return;
++ }
++
++ if (dwc_qh_is_non_per(qh)) {
++ if (hcd->non_periodic_qh_ptr == &qh->qh_list_entry) {
++ hcd->non_periodic_qh_ptr =
++ hcd->non_periodic_qh_ptr->next;
++ }
++ DWC_LIST_REMOVE_INIT(&qh->qh_list_entry);
++ //if (!DWC_LIST_EMPTY(&hcd->non_periodic_sched_inactive))
++ // hcd->fiq_state->kick_np_queues = 1;
++ } else {
++ deschedule_periodic(hcd, qh);
++ hcd->periodic_qh_count--;
++ if( !hcd->periodic_qh_count && !fiq_fsm_enable ) {
++ intr_mask.b.sofintr = 1;
++ if (fiq_enable) {
++ local_fiq_disable();
++ fiq_fsm_spin_lock(&hcd->fiq_state->lock);
++ DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, intr_mask.d32, 0);
++ fiq_fsm_spin_unlock(&hcd->fiq_state->lock);
++ local_fiq_enable();
++ } else {
++ DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, intr_mask.d32, 0);
++ }
++ }
++ }
++}
++
++/**
++ * Deactivates a QH. For non-periodic QHs, removes the QH from the active
++ * non-periodic schedule. The QH is added to the inactive non-periodic
++ * schedule if any QTDs are still attached to the QH.
++ *
++ * For periodic QHs, the QH is removed from the periodic queued schedule. If
++ * there are any QTDs still attached to the QH, the QH is added to either the
++ * periodic inactive schedule or the periodic ready schedule and its next
++ * scheduled frame is calculated. The QH is placed in the ready schedule if
++ * the scheduled frame has been reached already. Otherwise it's placed in the
++ * inactive schedule. If there are no QTDs attached to the QH, the QH is
++ * completely removed from the periodic schedule.
++ */
++void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh,
++ int sched_next_periodic_split)
++{
++ if (dwc_qh_is_non_per(qh)) {
++ dwc_otg_hcd_qh_remove(hcd, qh);
++ if (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
++ /* Add back to inactive non-periodic schedule. */
++ dwc_otg_hcd_qh_add(hcd, qh);
++ //hcd->fiq_state->kick_np_queues = 1;
++ }
++ } else {
++ uint16_t frame_number = dwc_otg_hcd_get_frame_number(hcd);
++
++ if (qh->do_split) {
++ /* Schedule the next continuing periodic split transfer */
++ if (sched_next_periodic_split) {
++
++ qh->sched_frame = frame_number;
++
++ if (dwc_frame_num_le(frame_number,
++ dwc_frame_num_inc
++ (qh->start_split_frame,
++ 1))) {
++ /*
++ * Allow one frame to elapse after start
++ * split microframe before scheduling
++ * complete split, but DONT if we are
++ * doing the next start split in the
++ * same frame for an ISOC out.
++ */
++ if ((qh->ep_type != UE_ISOCHRONOUS) ||
++ (qh->ep_is_in != 0)) {
++ qh->sched_frame =
++ dwc_frame_num_inc(qh->sched_frame, 1);
++ }
++ }
++ } else {
++ qh->sched_frame =
++ dwc_frame_num_inc(qh->start_split_frame,
++ qh->interval);
++ if (dwc_frame_num_le
++ (qh->sched_frame, frame_number)) {
++ qh->sched_frame = frame_number;
++ }
++ qh->sched_frame |= 0x7;
++ qh->start_split_frame = qh->sched_frame;
++ }
++ } else {
++ qh->sched_frame =
++ dwc_frame_num_inc(qh->sched_frame, qh->interval);
++ if (dwc_frame_num_le(qh->sched_frame, frame_number)) {
++ qh->sched_frame = frame_number;
++ }
++ }
++
++ if (DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
++ dwc_otg_hcd_qh_remove(hcd, qh);
++ } else {
++ /*
++ * Remove from periodic_sched_queued and move to
++ * appropriate queue.
++ */
++ if ((microframe_schedule && dwc_frame_num_le(qh->sched_frame, frame_number)) ||
++ (!microframe_schedule && qh->sched_frame == frame_number)) {
++ DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_ready,
++ &qh->qh_list_entry);
++ } else {
++ if(fiq_enable && !dwc_frame_num_le(hcd->fiq_state->next_sched_frame, qh->sched_frame))
++ {
++ hcd->fiq_state->next_sched_frame = qh->sched_frame;
++ }
++
++ DWC_LIST_MOVE_HEAD
++ (&hcd->periodic_sched_inactive,
++ &qh->qh_list_entry);
++ }
++ }
++ }
++}
++
++/**
++ * This function allocates and initializes a QTD.
++ *
++ * @param urb The URB to create a QTD from. Each URB-QTD pair will end up
++ * pointing to each other so each pair should have a unique correlation.
++ * @param atomic_alloc Flag to do atomic alloc if needed
++ *
++ * @return Returns pointer to the newly allocated QTD, or NULL on error. */
++dwc_otg_qtd_t *dwc_otg_hcd_qtd_create(dwc_otg_hcd_urb_t * urb, int atomic_alloc)
++{
++ dwc_otg_qtd_t *qtd;
++
++ qtd = dwc_otg_hcd_qtd_alloc(atomic_alloc);
++ if (qtd == NULL) {
++ return NULL;
++ }
++
++ dwc_otg_hcd_qtd_init(qtd, urb);
++ return qtd;
++}
++
++/**
++ * Initializes a QTD structure.
++ *
++ * @param qtd The QTD to initialize.
++ * @param urb The URB to use for initialization. */
++void dwc_otg_hcd_qtd_init(dwc_otg_qtd_t * qtd, dwc_otg_hcd_urb_t * urb)
++{
++ dwc_memset(qtd, 0, sizeof(dwc_otg_qtd_t));
++ qtd->urb = urb;
++ if (dwc_otg_hcd_get_pipe_type(&urb->pipe_info) == UE_CONTROL) {
++ /*
++ * The only time the QTD data toggle is used is on the data
++ * phase of control transfers. This phase always starts with
++ * DATA1.
++ */
++ qtd->data_toggle = DWC_OTG_HC_PID_DATA1;
++ qtd->control_phase = DWC_OTG_CONTROL_SETUP;
++ }
++
++ /* start split */
++ qtd->complete_split = 0;
++ qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL;
++ qtd->isoc_split_offset = 0;
++ qtd->in_process = 0;
++
++ /* Store the qtd ptr in the urb to reference what QTD. */
++ urb->qtd = qtd;
++ return;
++}
++
++/**
++ * This function adds a QTD to the QTD-list of a QH. It will find the correct
++ * QH to place the QTD into. If it does not find a QH, then it will create a
++ * new QH. If the QH to which the QTD is added is not currently scheduled, it
++ * is placed into the proper schedule based on its EP type.
++ * HCD lock must be held and interrupts must be disabled on entry
++ *
++ * @param[in] qtd The QTD to add
++ * @param[in] hcd The DWC HCD structure
++ * @param[out] qh out parameter to return queue head
++ * @param atomic_alloc Flag to do atomic alloc if needed
++ *
++ * @return 0 if successful, negative error code otherwise.
++ */
++int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t * qtd,
++ dwc_otg_hcd_t * hcd, dwc_otg_qh_t ** qh, int atomic_alloc)
++{
++ int retval = 0;
++ dwc_otg_hcd_urb_t *urb = qtd->urb;
++
++ /*
++ * Get the QH which holds the QTD-list to insert to. Create QH if it
++ * doesn't exist.
++ */
++ if (*qh == NULL) {
++ *qh = dwc_otg_hcd_qh_create(hcd, urb, atomic_alloc);
++ if (*qh == NULL) {
++ retval = -DWC_E_NO_MEMORY;
++ goto done;
++ } else {
++ if (fiq_enable)
++ hcd->fiq_state->kick_np_queues = 1;
++ }
++ }
++ retval = dwc_otg_hcd_qh_add(hcd, *qh);
++ if (retval == 0) {
++ DWC_CIRCLEQ_INSERT_TAIL(&((*qh)->qtd_list), qtd,
++ qtd_list_entry);
++ qtd->qh = *qh;
++ }
++done:
++
++ return retval;
++}
++
++#endif /* DWC_DEVICE_ONLY */
+diff -Nur linux-4.1.3/drivers/usb/host/dwc_otg/dwc_otg_os_dep.h linux-xbian-rpi/drivers/usb/host/dwc_otg/dwc_otg_os_dep.h
+--- linux-4.1.3/drivers/usb/host/dwc_otg/dwc_otg_os_dep.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/usb/host/dwc_otg/dwc_otg_os_dep.h 2015-07-28 01:20:58.449142252 +0200
+@@ -0,0 +1,188 @@
++#ifndef _DWC_OS_DEP_H_
++#define _DWC_OS_DEP_H_
++
++/**
++ * @file
++ *
++ * This file contains OS dependent structures.
++ *
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/init.h>
++#include <linux/device.h>
++#include <linux/errno.h>
++#include <linux/types.h>
++#include <linux/slab.h>
++#include <linux/list.h>
++#include <linux/interrupt.h>
++#include <linux/ctype.h>
++#include <linux/string.h>
++#include <linux/dma-mapping.h>
++#include <linux/jiffies.h>
++#include <linux/delay.h>
++#include <linux/timer.h>
++#include <linux/workqueue.h>
++#include <linux/stat.h>
++#include <linux/pci.h>
++
++#include <linux/version.h>
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
++# include <linux/irq.h>
++#endif
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21)
++# include <linux/usb/ch9.h>
++#else
++# include <linux/usb_ch9.h>
++#endif
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)
++# include <linux/usb/gadget.h>
++#else
++# include <linux/usb_gadget.h>
++#endif
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
++# include <asm/irq.h>
++#endif
++
++#ifdef PCI_INTERFACE
++# include <asm/io.h>
++#endif
++
++#ifdef LM_INTERFACE
++# include <asm/unaligned.h>
++# include <asm/sizes.h>
++# include <asm/param.h>
++# include <asm/io.h>
++# if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30))
++# include <asm/arch/hardware.h>
++# include <asm/arch/lm.h>
++# include <asm/arch/irqs.h>
++# include <asm/arch/regs-irq.h>
++# else
++/* in 2.6.31, at least, we seem to have lost the generic LM infrastructure -
++ here we assume that the machine architecture provides definitions
++ in its own header
++*/
++# include <mach/lm.h>
++# include <mach/hardware.h>
++# endif
++#endif
++
++#ifdef PLATFORM_INTERFACE
++#include <linux/platform_device.h>
++#include <asm/mach/map.h>
++#endif
++
++/** The OS page size */
++#define DWC_OS_PAGE_SIZE PAGE_SIZE
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,14)
++typedef int gfp_t;
++#endif
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)
++# define IRQF_SHARED SA_SHIRQ
++#endif
++
++typedef struct os_dependent {
++ /** Base address returned from ioremap() */
++ void *base;
++
++ /** Register offset for Diagnostic API */
++ uint32_t reg_offset;
++
++ /** Base address for MPHI peripheral */
++ void *mphi_base;
++
++#ifdef LM_INTERFACE
++ struct lm_device *lmdev;
++#elif defined(PCI_INTERFACE)
++ struct pci_dev *pcidev;
++
++ /** Start address of a PCI region */
++ resource_size_t rsrc_start;
++
++ /** Length address of a PCI region */
++ resource_size_t rsrc_len;
++#elif defined(PLATFORM_INTERFACE)
++ struct platform_device *platformdev;
++#endif
++
++} os_dependent_t;
++
++#ifdef __cplusplus
++}
++#endif
++
++
++
++/* Type for the our device on the chosen bus */
++#if defined(LM_INTERFACE)
++typedef struct lm_device dwc_bus_dev_t;
++#elif defined(PCI_INTERFACE)
++typedef struct pci_dev dwc_bus_dev_t;
++#elif defined(PLATFORM_INTERFACE)
++typedef struct platform_device dwc_bus_dev_t;
++#endif
++
++/* Helper macro to retrieve drvdata from the device on the chosen bus */
++#if defined(LM_INTERFACE)
++#define DWC_OTG_BUSDRVDATA(_dev) lm_get_drvdata(_dev)
++#elif defined(PCI_INTERFACE)
++#define DWC_OTG_BUSDRVDATA(_dev) pci_get_drvdata(_dev)
++#elif defined(PLATFORM_INTERFACE)
++#define DWC_OTG_BUSDRVDATA(_dev) platform_get_drvdata(_dev)
++#endif
++
++/**
++ * Helper macro returning the otg_device structure of a given struct device
++ *
++ * c.f. static dwc_otg_device_t *dwc_otg_drvdev(struct device *_dev)
++ */
++#ifdef LM_INTERFACE
++#define DWC_OTG_GETDRVDEV(_var, _dev) do { \
++ struct lm_device *lm_dev = \
++ container_of(_dev, struct lm_device, dev); \
++ _var = lm_get_drvdata(lm_dev); \
++ } while (0)
++
++#elif defined(PCI_INTERFACE)
++#define DWC_OTG_GETDRVDEV(_var, _dev) do { \
++ _var = dev_get_drvdata(_dev); \
++ } while (0)
++
++#elif defined(PLATFORM_INTERFACE)
++#define DWC_OTG_GETDRVDEV(_var, _dev) do { \
++ struct platform_device *platform_dev = \
++ container_of(_dev, struct platform_device, dev); \
++ _var = platform_get_drvdata(platform_dev); \
++ } while (0)
++#endif
++
++
++/**
++ * Helper macro returning the struct dev of the given struct os_dependent
++ *
++ * c.f. static struct device *dwc_otg_getdev(struct os_dependent *osdep)
++ */
++#ifdef LM_INTERFACE
++#define DWC_OTG_OS_GETDEV(_osdep) \
++ ((_osdep).lmdev == NULL? NULL: &(_osdep).lmdev->dev)
++#elif defined(PCI_INTERFACE)
++#define DWC_OTG_OS_GETDEV(_osdep) \
++ ((_osdep).pci_dev == NULL? NULL: &(_osdep).pci_dev->dev)
++#elif defined(PLATFORM_INTERFACE)
++#define DWC_OTG_OS_GETDEV(_osdep) \
++ ((_osdep).platformdev == NULL? NULL: &(_osdep).platformdev->dev)
++#endif
++
++
++
++
++#endif /* _DWC_OS_DEP_H_ */
+diff -Nur linux-4.1.3/drivers/usb/host/dwc_otg/dwc_otg_pcd.c linux-xbian-rpi/drivers/usb/host/dwc_otg/dwc_otg_pcd.c
+--- linux-4.1.3/drivers/usb/host/dwc_otg/dwc_otg_pcd.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/usb/host/dwc_otg/dwc_otg_pcd.c 2015-07-28 01:20:58.449142252 +0200
+@@ -0,0 +1,2712 @@
++/* ==========================================================================
++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd.c $
++ * $Revision: #101 $
++ * $Date: 2012/08/10 $
++ * $Change: 2047372 $
++ *
++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++ * otherwise expressly agreed to in writing between Synopsys and you.
++ *
++ * The Software IS NOT an item of Licensed Software or Licensed Product under
++ * any End User Software License Agreement or Agreement for Licensed Product
++ * with Synopsys or any supplement thereto. You are permitted to use and
++ * redistribute this Software in source and binary forms, with or without
++ * modification, provided that redistributions of source code must retain this
++ * notice. You may not view, use, disclose, copy or distribute this file or
++ * any information contained herein except pursuant to this license grant from
++ * Synopsys. If you do not agree with this notice, including the disclaimer
++ * below, then you are not authorized to use the Software.
++ *
++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++ * DAMAGE.
++ * ========================================================================== */
++#ifndef DWC_HOST_ONLY
++
++/** @file
++ * This file implements PCD Core. All code in this file is portable and doesn't
++ * use any OS specific functions.
++ * PCD Core provides Interface, defined in <code><dwc_otg_pcd_if.h></code>
++ * header file, which can be used to implement OS specific PCD interface.
++ *
++ * An important function of the PCD is managing interrupts generated
++ * by the DWC_otg controller. The implementation of the DWC_otg device
++ * mode interrupt service routines is in dwc_otg_pcd_intr.c.
++ *
++ * @todo Add Device Mode test modes (Test J mode, Test K mode, etc).
++ * @todo Does it work when the request size is greater than DEPTSIZ
++ * transfer size
++ *
++ */
++
++#include "dwc_otg_pcd.h"
++
++#ifdef DWC_UTE_CFI
++#include "dwc_otg_cfi.h"
++
++extern int init_cfi(cfiobject_t * cfiobj);
++#endif
++
++/**
++ * Choose endpoint from ep arrays using usb_ep structure.
++ */
++static dwc_otg_pcd_ep_t *get_ep_from_handle(dwc_otg_pcd_t * pcd, void *handle)
++{
++ int i;
++ if (pcd->ep0.priv == handle) {
++ return &pcd->ep0;
++ }
++ for (i = 0; i < MAX_EPS_CHANNELS - 1; i++) {
++ if (pcd->in_ep[i].priv == handle)
++ return &pcd->in_ep[i];
++ if (pcd->out_ep[i].priv == handle)
++ return &pcd->out_ep[i];
++ }
++
++ return NULL;
++}
++
++/**
++ * This function completes a request. It call's the request call back.
++ */
++void dwc_otg_request_done(dwc_otg_pcd_ep_t * ep, dwc_otg_pcd_request_t * req,
++ int32_t status)
++{
++ unsigned stopped = ep->stopped;
++
++ DWC_DEBUGPL(DBG_PCDV, "%s(ep %p req %p)\n", __func__, ep, req);
++ DWC_CIRCLEQ_REMOVE_INIT(&ep->queue, req, queue_entry);
++
++ /* don't modify queue heads during completion callback */
++ ep->stopped = 1;
++ /* spin_unlock/spin_lock now done in fops->complete() */
++ ep->pcd->fops->complete(ep->pcd, ep->priv, req->priv, status,
++ req->actual);
++
++ if (ep->pcd->request_pending > 0) {
++ --ep->pcd->request_pending;
++ }
++
++ ep->stopped = stopped;
++ DWC_FREE(req);
++}
++
++/**
++ * This function terminates all the requsts in the EP request queue.
++ */
++void dwc_otg_request_nuke(dwc_otg_pcd_ep_t * ep)
++{
++ dwc_otg_pcd_request_t *req;
++
++ ep->stopped = 1;
++
++ /* called with irqs blocked?? */
++ while (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
++ req = DWC_CIRCLEQ_FIRST(&ep->queue);
++ dwc_otg_request_done(ep, req, -DWC_E_SHUTDOWN);
++ }
++}
++
++void dwc_otg_pcd_start(dwc_otg_pcd_t * pcd,
++ const struct dwc_otg_pcd_function_ops *fops)
++{
++ pcd->fops = fops;
++}
++
++/**
++ * PCD Callback function for initializing the PCD when switching to
++ * device mode.
++ *
++ * @param p void pointer to the <code>dwc_otg_pcd_t</code>
++ */
++static int32_t dwc_otg_pcd_start_cb(void *p)
++{
++ dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p;
++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++
++ /*
++ * Initialized the Core for Device mode.
++ */
++ if (dwc_otg_is_device_mode(core_if)) {
++ dwc_otg_core_dev_init(core_if);
++ /* Set core_if's lock pointer to the pcd->lock */
++ core_if->lock = pcd->lock;
++ }
++ return 1;
++}
++
++/** CFI-specific buffer allocation function for EP */
++#ifdef DWC_UTE_CFI
++uint8_t *cfiw_ep_alloc_buffer(dwc_otg_pcd_t * pcd, void *pep, dwc_dma_t * addr,
++ size_t buflen, int flags)
++{
++ dwc_otg_pcd_ep_t *ep;
++ ep = get_ep_from_handle(pcd, pep);
++ if (!ep) {
++ DWC_WARN("bad ep\n");
++ return -DWC_E_INVALID;
++ }
++
++ return pcd->cfi->ops.ep_alloc_buf(pcd->cfi, pcd, ep, addr, buflen,
++ flags);
++}
++#else
++uint8_t *cfiw_ep_alloc_buffer(dwc_otg_pcd_t * pcd, void *pep, dwc_dma_t * addr,
++ size_t buflen, int flags);
++#endif
++
++/**
++ * PCD Callback function for notifying the PCD when resuming from
++ * suspend.
++ *
++ * @param p void pointer to the <code>dwc_otg_pcd_t</code>
++ */
++static int32_t dwc_otg_pcd_resume_cb(void *p)
++{
++ dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p;
++
++ if (pcd->fops->resume) {
++ pcd->fops->resume(pcd);
++ }
++
++ /* Stop the SRP timeout timer. */
++ if ((GET_CORE_IF(pcd)->core_params->phy_type != DWC_PHY_TYPE_PARAM_FS)
++ || (!GET_CORE_IF(pcd)->core_params->i2c_enable)) {
++ if (GET_CORE_IF(pcd)->srp_timer_started) {
++ GET_CORE_IF(pcd)->srp_timer_started = 0;
++ DWC_TIMER_CANCEL(GET_CORE_IF(pcd)->srp_timer);
++ }
++ }
++ return 1;
++}
++
++/**
++ * PCD Callback function for notifying the PCD device is suspended.
++ *
++ * @param p void pointer to the <code>dwc_otg_pcd_t</code>
++ */
++static int32_t dwc_otg_pcd_suspend_cb(void *p)
++{
++ dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p;
++
++ if (pcd->fops->suspend) {
++ DWC_SPINUNLOCK(pcd->lock);
++ pcd->fops->suspend(pcd);
++ DWC_SPINLOCK(pcd->lock);
++ }
++
++ return 1;
++}
++
++/**
++ * PCD Callback function for stopping the PCD when switching to Host
++ * mode.
++ *
++ * @param p void pointer to the <code>dwc_otg_pcd_t</code>
++ */
++static int32_t dwc_otg_pcd_stop_cb(void *p)
++{
++ dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p;
++ extern void dwc_otg_pcd_stop(dwc_otg_pcd_t * _pcd);
++
++ dwc_otg_pcd_stop(pcd);
++ return 1;
++}
++
++/**
++ * PCD Callback structure for handling mode switching.
++ */
++static dwc_otg_cil_callbacks_t pcd_callbacks = {
++ .start = dwc_otg_pcd_start_cb,
++ .stop = dwc_otg_pcd_stop_cb,
++ .suspend = dwc_otg_pcd_suspend_cb,
++ .resume_wakeup = dwc_otg_pcd_resume_cb,
++ .p = 0, /* Set at registration */
++};
++
++/**
++ * This function allocates a DMA Descriptor chain for the Endpoint
++ * buffer to be used for a transfer to/from the specified endpoint.
++ */
++dwc_otg_dev_dma_desc_t *dwc_otg_ep_alloc_desc_chain(dwc_dma_t * dma_desc_addr,
++ uint32_t count)
++{
++ return DWC_DMA_ALLOC_ATOMIC(count * sizeof(dwc_otg_dev_dma_desc_t),
++ dma_desc_addr);
++}
++
++/**
++ * This function frees a DMA Descriptor chain that was allocated by ep_alloc_desc.
++ */
++void dwc_otg_ep_free_desc_chain(dwc_otg_dev_dma_desc_t * desc_addr,
++ uint32_t dma_desc_addr, uint32_t count)
++{
++ DWC_DMA_FREE(count * sizeof(dwc_otg_dev_dma_desc_t), desc_addr,
++ dma_desc_addr);
++}
++
++#ifdef DWC_EN_ISOC
++
++/**
++ * This function initializes a descriptor chain for Isochronous transfer
++ *
++ * @param core_if Programming view of DWC_otg controller.
++ * @param dwc_ep The EP to start the transfer on.
++ *
++ */
++void dwc_otg_iso_ep_start_ddma_transfer(dwc_otg_core_if_t * core_if,
++ dwc_ep_t * dwc_ep)
++{
++
++ dsts_data_t dsts = {.d32 = 0 };
++ depctl_data_t depctl = {.d32 = 0 };
++ volatile uint32_t *addr;
++ int i, j;
++ uint32_t len;
++
++ if (dwc_ep->is_in)
++ dwc_ep->desc_cnt = dwc_ep->buf_proc_intrvl / dwc_ep->bInterval;
++ else
++ dwc_ep->desc_cnt =
++ dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm /
++ dwc_ep->bInterval;
++
++ /** Allocate descriptors for double buffering */
++ dwc_ep->iso_desc_addr =
++ dwc_otg_ep_alloc_desc_chain(&dwc_ep->iso_dma_desc_addr,
++ dwc_ep->desc_cnt * 2);
++ if (dwc_ep->desc_addr) {
++ DWC_WARN("%s, can't allocate DMA descriptor chain\n", __func__);
++ return;
++ }
++
++ dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
++
++ /** ISO OUT EP */
++ if (dwc_ep->is_in == 0) {
++ dev_dma_desc_sts_t sts = {.d32 = 0 };
++ dwc_otg_dev_dma_desc_t *dma_desc = dwc_ep->iso_desc_addr;
++ dma_addr_t dma_ad;
++ uint32_t data_per_desc;
++ dwc_otg_dev_out_ep_regs_t *out_regs =
++ core_if->dev_if->out_ep_regs[dwc_ep->num];
++ int offset;
++
++ addr = &core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl;
++ dma_ad = (dma_addr_t) DWC_READ_REG32(&(out_regs->doepdma));
++
++ /** Buffer 0 descriptors setup */
++ dma_ad = dwc_ep->dma_addr0;
++
++ sts.b_iso_out.bs = BS_HOST_READY;
++ sts.b_iso_out.rxsts = 0;
++ sts.b_iso_out.l = 0;
++ sts.b_iso_out.sp = 0;
++ sts.b_iso_out.ioc = 0;
++ sts.b_iso_out.pid = 0;
++ sts.b_iso_out.framenum = 0;
++
++ offset = 0;
++ for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
++ i += dwc_ep->pkt_per_frm) {
++
++ for (j = 0; j < dwc_ep->pkt_per_frm; ++j) {
++ uint32_t len = (j + 1) * dwc_ep->maxpacket;
++ if (len > dwc_ep->data_per_frame)
++ data_per_desc =
++ dwc_ep->data_per_frame -
++ j * dwc_ep->maxpacket;
++ else
++ data_per_desc = dwc_ep->maxpacket;
++ len = data_per_desc % 4;
++ if (len)
++ data_per_desc += 4 - len;
++
++ sts.b_iso_out.rxbytes = data_per_desc;
++ dma_desc->buf = dma_ad;
++ dma_desc->status.d32 = sts.d32;
++
++ offset += data_per_desc;
++ dma_desc++;
++ dma_ad += data_per_desc;
++ }
++ }
++
++ for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) {
++ uint32_t len = (j + 1) * dwc_ep->maxpacket;
++ if (len > dwc_ep->data_per_frame)
++ data_per_desc =
++ dwc_ep->data_per_frame -
++ j * dwc_ep->maxpacket;
++ else
++ data_per_desc = dwc_ep->maxpacket;
++ len = data_per_desc % 4;
++ if (len)
++ data_per_desc += 4 - len;
++ sts.b_iso_out.rxbytes = data_per_desc;
++ dma_desc->buf = dma_ad;
++ dma_desc->status.d32 = sts.d32;
++
++ offset += data_per_desc;
++ dma_desc++;
++ dma_ad += data_per_desc;
++ }
++
++ sts.b_iso_out.ioc = 1;
++ len = (j + 1) * dwc_ep->maxpacket;
++ if (len > dwc_ep->data_per_frame)
++ data_per_desc =
++ dwc_ep->data_per_frame - j * dwc_ep->maxpacket;
++ else
++ data_per_desc = dwc_ep->maxpacket;
++ len = data_per_desc % 4;
++ if (len)
++ data_per_desc += 4 - len;
++ sts.b_iso_out.rxbytes = data_per_desc;
++
++ dma_desc->buf = dma_ad;
++ dma_desc->status.d32 = sts.d32;
++ dma_desc++;
++
++ /** Buffer 1 descriptors setup */
++ sts.b_iso_out.ioc = 0;
++ dma_ad = dwc_ep->dma_addr1;
++
++ offset = 0;
++ for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
++ i += dwc_ep->pkt_per_frm) {
++ for (j = 0; j < dwc_ep->pkt_per_frm; ++j) {
++ uint32_t len = (j + 1) * dwc_ep->maxpacket;
++ if (len > dwc_ep->data_per_frame)
++ data_per_desc =
++ dwc_ep->data_per_frame -
++ j * dwc_ep->maxpacket;
++ else
++ data_per_desc = dwc_ep->maxpacket;
++ len = data_per_desc % 4;
++ if (len)
++ data_per_desc += 4 - len;
++
++ data_per_desc =
++ sts.b_iso_out.rxbytes = data_per_desc;
++ dma_desc->buf = dma_ad;
++ dma_desc->status.d32 = sts.d32;
++
++ offset += data_per_desc;
++ dma_desc++;
++ dma_ad += data_per_desc;
++ }
++ }
++ for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) {
++ data_per_desc =
++ ((j + 1) * dwc_ep->maxpacket >
++ dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
++ j * dwc_ep->maxpacket : dwc_ep->maxpacket;
++ data_per_desc +=
++ (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
++ sts.b_iso_out.rxbytes = data_per_desc;
++ dma_desc->buf = dma_ad;
++ dma_desc->status.d32 = sts.d32;
++
++ offset += data_per_desc;
++ dma_desc++;
++ dma_ad += data_per_desc;
++ }
++
++ sts.b_iso_out.ioc = 1;
++ sts.b_iso_out.l = 1;
++ data_per_desc =
++ ((j + 1) * dwc_ep->maxpacket >
++ dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
++ j * dwc_ep->maxpacket : dwc_ep->maxpacket;
++ data_per_desc +=
++ (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
++ sts.b_iso_out.rxbytes = data_per_desc;
++
++ dma_desc->buf = dma_ad;
++ dma_desc->status.d32 = sts.d32;
++
++ dwc_ep->next_frame = 0;
++
++ /** Write dma_ad into DOEPDMA register */
++ DWC_WRITE_REG32(&(out_regs->doepdma),
++ (uint32_t) dwc_ep->iso_dma_desc_addr);
++
++ }
++ /** ISO IN EP */
++ else {
++ dev_dma_desc_sts_t sts = {.d32 = 0 };
++ dwc_otg_dev_dma_desc_t *dma_desc = dwc_ep->iso_desc_addr;
++ dma_addr_t dma_ad;
++ dwc_otg_dev_in_ep_regs_t *in_regs =
++ core_if->dev_if->in_ep_regs[dwc_ep->num];
++ unsigned int frmnumber;
++ fifosize_data_t txfifosize, rxfifosize;
++
++ txfifosize.d32 =
++ DWC_READ_REG32(&core_if->dev_if->in_ep_regs[dwc_ep->num]->
++ dtxfsts);
++ rxfifosize.d32 =
++ DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
++
++ addr = &core_if->dev_if->in_ep_regs[dwc_ep->num]->diepctl;
++
++ dma_ad = dwc_ep->dma_addr0;
++
++ dsts.d32 =
++ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
++
++ sts.b_iso_in.bs = BS_HOST_READY;
++ sts.b_iso_in.txsts = 0;
++ sts.b_iso_in.sp =
++ (dwc_ep->data_per_frame % dwc_ep->maxpacket) ? 1 : 0;
++ sts.b_iso_in.ioc = 0;
++ sts.b_iso_in.pid = dwc_ep->pkt_per_frm;
++
++ frmnumber = dwc_ep->next_frame;
++
++ sts.b_iso_in.framenum = frmnumber;
++ sts.b_iso_in.txbytes = dwc_ep->data_per_frame;
++ sts.b_iso_in.l = 0;
++
++ /** Buffer 0 descriptors setup */
++ for (i = 0; i < dwc_ep->desc_cnt - 1; i++) {
++ dma_desc->buf = dma_ad;
++ dma_desc->status.d32 = sts.d32;
++ dma_desc++;
++
++ dma_ad += dwc_ep->data_per_frame;
++ sts.b_iso_in.framenum += dwc_ep->bInterval;
++ }
++
++ sts.b_iso_in.ioc = 1;
++ dma_desc->buf = dma_ad;
++ dma_desc->status.d32 = sts.d32;
++ ++dma_desc;
++
++ /** Buffer 1 descriptors setup */
++ sts.b_iso_in.ioc = 0;
++ dma_ad = dwc_ep->dma_addr1;
++
++ for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
++ i += dwc_ep->pkt_per_frm) {
++ dma_desc->buf = dma_ad;
++ dma_desc->status.d32 = sts.d32;
++ dma_desc++;
++
++ dma_ad += dwc_ep->data_per_frame;
++ sts.b_iso_in.framenum += dwc_ep->bInterval;
++
++ sts.b_iso_in.ioc = 0;
++ }
++ sts.b_iso_in.ioc = 1;
++ sts.b_iso_in.l = 1;
++
++ dma_desc->buf = dma_ad;
++ dma_desc->status.d32 = sts.d32;
++
++ dwc_ep->next_frame = sts.b_iso_in.framenum + dwc_ep->bInterval;
++
++ /** Write dma_ad into diepdma register */
++ DWC_WRITE_REG32(&(in_regs->diepdma),
++ (uint32_t) dwc_ep->iso_dma_desc_addr);
++ }
++ /** Enable endpoint, clear nak */
++ depctl.d32 = 0;
++ depctl.b.epena = 1;
++ depctl.b.usbactep = 1;
++ depctl.b.cnak = 1;
++
++ DWC_MODIFY_REG32(addr, depctl.d32, depctl.d32);
++ depctl.d32 = DWC_READ_REG32(addr);
++}
++
++/**
++ * This function initializes a descriptor chain for Isochronous transfer
++ *
++ * @param core_if Programming view of DWC_otg controller.
++ * @param ep The EP to start the transfer on.
++ *
++ */
++void dwc_otg_iso_ep_start_buf_transfer(dwc_otg_core_if_t * core_if,
++ dwc_ep_t * ep)
++{
++ depctl_data_t depctl = {.d32 = 0 };
++ volatile uint32_t *addr;
++
++ if (ep->is_in) {
++ addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
++ } else {
++ addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
++ }
++
++ if (core_if->dma_enable == 0 || core_if->dma_desc_enable != 0) {
++ return;
++ } else {
++ deptsiz_data_t deptsiz = {.d32 = 0 };
++
++ ep->xfer_len =
++ ep->data_per_frame * ep->buf_proc_intrvl / ep->bInterval;
++ ep->pkt_cnt =
++ (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket;
++ ep->xfer_count = 0;
++ ep->xfer_buff =
++ (ep->proc_buf_num) ? ep->xfer_buff1 : ep->xfer_buff0;
++ ep->dma_addr =
++ (ep->proc_buf_num) ? ep->dma_addr1 : ep->dma_addr0;
++
++ if (ep->is_in) {
++ /* Program the transfer size and packet count
++ * as follows: xfersize = N * maxpacket +
++ * short_packet pktcnt = N + (short_packet
++ * exist ? 1 : 0)
++ */
++ deptsiz.b.mc = ep->pkt_per_frm;
++ deptsiz.b.xfersize = ep->xfer_len;
++ deptsiz.b.pktcnt =
++ (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket;
++ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
++ dieptsiz, deptsiz.d32);
++
++ /* Write the DMA register */
++ DWC_WRITE_REG32(&
++ (core_if->dev_if->in_ep_regs[ep->num]->
++ diepdma), (uint32_t) ep->dma_addr);
++
++ } else {
++ deptsiz.b.pktcnt =
++ (ep->xfer_len + (ep->maxpacket - 1)) /
++ ep->maxpacket;
++ deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket;
++
++ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[ep->num]->
++ doeptsiz, deptsiz.d32);
++
++ /* Write the DMA register */
++ DWC_WRITE_REG32(&
++ (core_if->dev_if->out_ep_regs[ep->num]->
++ doepdma), (uint32_t) ep->dma_addr);
++
++ }
++ /** Enable endpoint, clear nak */
++ depctl.d32 = 0;
++ depctl.b.epena = 1;
++ depctl.b.cnak = 1;
++
++ DWC_MODIFY_REG32(addr, depctl.d32, depctl.d32);
++ }
++}
++
++/**
++ * This function does the setup for a data transfer for an EP and
++ * starts the transfer. For an IN transfer, the packets will be
++ * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers,
++ * the packets are unloaded from the Rx FIFO in the ISR.
++ *
++ * @param core_if Programming view of DWC_otg controller.
++ * @param ep The EP to start the transfer on.
++ */
++
++static void dwc_otg_iso_ep_start_transfer(dwc_otg_core_if_t * core_if,
++ dwc_ep_t * ep)
++{
++ if (core_if->dma_enable) {
++ if (core_if->dma_desc_enable) {
++ if (ep->is_in) {
++ ep->desc_cnt = ep->pkt_cnt / ep->pkt_per_frm;
++ } else {
++ ep->desc_cnt = ep->pkt_cnt;
++ }
++ dwc_otg_iso_ep_start_ddma_transfer(core_if, ep);
++ } else {
++ if (core_if->pti_enh_enable) {
++ dwc_otg_iso_ep_start_buf_transfer(core_if, ep);
++ } else {
++ ep->cur_pkt_addr =
++ (ep->proc_buf_num) ? ep->xfer_buff1 : ep->
++ xfer_buff0;
++ ep->cur_pkt_dma_addr =
++ (ep->proc_buf_num) ? ep->dma_addr1 : ep->
++ dma_addr0;
++ dwc_otg_iso_ep_start_frm_transfer(core_if, ep);
++ }
++ }
++ } else {
++ ep->cur_pkt_addr =
++ (ep->proc_buf_num) ? ep->xfer_buff1 : ep->xfer_buff0;
++ ep->cur_pkt_dma_addr =
++ (ep->proc_buf_num) ? ep->dma_addr1 : ep->dma_addr0;
++ dwc_otg_iso_ep_start_frm_transfer(core_if, ep);
++ }
++}
++
++/**
++ * This function stops transfer for an EP and
++ * resets the ep's variables.
++ *
++ * @param core_if Programming view of DWC_otg controller.
++ * @param ep The EP to start the transfer on.
++ */
++
++void dwc_otg_iso_ep_stop_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
++{
++ depctl_data_t depctl = {.d32 = 0 };
++ volatile uint32_t *addr;
++
++ if (ep->is_in == 1) {
++ addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
++ } else {
++ addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
++ }
++
++ /* disable the ep */
++ depctl.d32 = DWC_READ_REG32(addr);
++
++ depctl.b.epdis = 1;
++ depctl.b.snak = 1;
++
++ DWC_WRITE_REG32(addr, depctl.d32);
++
++ if (core_if->dma_desc_enable &&
++ ep->iso_desc_addr && ep->iso_dma_desc_addr) {
++ dwc_otg_ep_free_desc_chain(ep->iso_desc_addr,
++ ep->iso_dma_desc_addr,
++ ep->desc_cnt * 2);
++ }
++
++ /* reset varibales */
++ ep->dma_addr0 = 0;
++ ep->dma_addr1 = 0;
++ ep->xfer_buff0 = 0;
++ ep->xfer_buff1 = 0;
++ ep->data_per_frame = 0;
++ ep->data_pattern_frame = 0;
++ ep->sync_frame = 0;
++ ep->buf_proc_intrvl = 0;
++ ep->bInterval = 0;
++ ep->proc_buf_num = 0;
++ ep->pkt_per_frm = 0;
++ ep->pkt_per_frm = 0;
++ ep->desc_cnt = 0;
++ ep->iso_desc_addr = 0;
++ ep->iso_dma_desc_addr = 0;
++}
++
++int dwc_otg_pcd_iso_ep_start(dwc_otg_pcd_t * pcd, void *ep_handle,
++ uint8_t * buf0, uint8_t * buf1, dwc_dma_t dma0,
++ dwc_dma_t dma1, int sync_frame, int dp_frame,
++ int data_per_frame, int start_frame,
++ int buf_proc_intrvl, void *req_handle,
++ int atomic_alloc)
++{
++ dwc_otg_pcd_ep_t *ep;
++ dwc_irqflags_t flags = 0;
++ dwc_ep_t *dwc_ep;
++ int32_t frm_data;
++ dsts_data_t dsts;
++ dwc_otg_core_if_t *core_if;
++
++ ep = get_ep_from_handle(pcd, ep_handle);
++
++ if (!ep || !ep->desc || ep->dwc_ep.num == 0) {
++ DWC_WARN("bad ep\n");
++ return -DWC_E_INVALID;
++ }
++
++ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
++ core_if = GET_CORE_IF(pcd);
++ dwc_ep = &ep->dwc_ep;
++
++ if (ep->iso_req_handle) {
++ DWC_WARN("ISO request in progress\n");
++ }
++
++ dwc_ep->dma_addr0 = dma0;
++ dwc_ep->dma_addr1 = dma1;
++
++ dwc_ep->xfer_buff0 = buf0;
++ dwc_ep->xfer_buff1 = buf1;
++
++ dwc_ep->data_per_frame = data_per_frame;
++
++ /** @todo - pattern data support is to be implemented in the future */
++ dwc_ep->data_pattern_frame = dp_frame;
++ dwc_ep->sync_frame = sync_frame;
++
++ dwc_ep->buf_proc_intrvl = buf_proc_intrvl;
++
++ dwc_ep->bInterval = 1 << (ep->desc->bInterval - 1);
++
++ dwc_ep->proc_buf_num = 0;
++
++ dwc_ep->pkt_per_frm = 0;
++ frm_data = ep->dwc_ep.data_per_frame;
++ while (frm_data > 0) {
++ dwc_ep->pkt_per_frm++;
++ frm_data -= ep->dwc_ep.maxpacket;
++ }
++
++ dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
++
++ if (start_frame == -1) {
++ dwc_ep->next_frame = dsts.b.soffn + 1;
++ if (dwc_ep->bInterval != 1) {
++ dwc_ep->next_frame =
++ dwc_ep->next_frame + (dwc_ep->bInterval - 1 -
++ dwc_ep->next_frame %
++ dwc_ep->bInterval);
++ }
++ } else {
++ dwc_ep->next_frame = start_frame;
++ }
++
++ if (!core_if->pti_enh_enable) {
++ dwc_ep->pkt_cnt =
++ dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm /
++ dwc_ep->bInterval;
++ } else {
++ dwc_ep->pkt_cnt =
++ (dwc_ep->data_per_frame *
++ (dwc_ep->buf_proc_intrvl / dwc_ep->bInterval)
++ - 1 + dwc_ep->maxpacket) / dwc_ep->maxpacket;
++ }
++
++ if (core_if->dma_desc_enable) {
++ dwc_ep->desc_cnt =
++ dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm /
++ dwc_ep->bInterval;
++ }
++
++ if (atomic_alloc) {
++ dwc_ep->pkt_info =
++ DWC_ALLOC_ATOMIC(sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt);
++ } else {
++ dwc_ep->pkt_info =
++ DWC_ALLOC(sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt);
++ }
++ if (!dwc_ep->pkt_info) {
++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
++ return -DWC_E_NO_MEMORY;
++ }
++ if (core_if->pti_enh_enable) {
++ dwc_memset(dwc_ep->pkt_info, 0,
++ sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt);
++ }
++
++ dwc_ep->cur_pkt = 0;
++ ep->iso_req_handle = req_handle;
++
++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
++ dwc_otg_iso_ep_start_transfer(core_if, dwc_ep);
++ return 0;
++}
++
++int dwc_otg_pcd_iso_ep_stop(dwc_otg_pcd_t * pcd, void *ep_handle,
++ void *req_handle)
++{
++ dwc_irqflags_t flags = 0;
++ dwc_otg_pcd_ep_t *ep;
++ dwc_ep_t *dwc_ep;
++
++ ep = get_ep_from_handle(pcd, ep_handle);
++ if (!ep || !ep->desc || ep->dwc_ep.num == 0) {
++ DWC_WARN("bad ep\n");
++ return -DWC_E_INVALID;
++ }
++ dwc_ep = &ep->dwc_ep;
++
++ dwc_otg_iso_ep_stop_transfer(GET_CORE_IF(pcd), dwc_ep);
++
++ DWC_FREE(dwc_ep->pkt_info);
++ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
++ if (ep->iso_req_handle != req_handle) {
++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
++ return -DWC_E_INVALID;
++ }
++
++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
++
++ ep->iso_req_handle = 0;
++ return 0;
++}
++
++/**
++ * This function is used for perodical data exchnage between PCD and gadget drivers.
++ * for Isochronous EPs
++ *
++ * - Every time a sync period completes this function is called to
++ * perform data exchange between PCD and gadget
++ */
++void dwc_otg_iso_buffer_done(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep,
++ void *req_handle)
++{
++ int i;
++ dwc_ep_t *dwc_ep;
++
++ dwc_ep = &ep->dwc_ep;
++
++ DWC_SPINUNLOCK(ep->pcd->lock);
++ pcd->fops->isoc_complete(pcd, ep->priv, ep->iso_req_handle,
++ dwc_ep->proc_buf_num ^ 0x1);
++ DWC_SPINLOCK(ep->pcd->lock);
++
++ for (i = 0; i < dwc_ep->pkt_cnt; ++i) {
++ dwc_ep->pkt_info[i].status = 0;
++ dwc_ep->pkt_info[i].offset = 0;
++ dwc_ep->pkt_info[i].length = 0;
++ }
++}
++
++int dwc_otg_pcd_get_iso_packet_count(dwc_otg_pcd_t * pcd, void *ep_handle,
++ void *iso_req_handle)
++{
++ dwc_otg_pcd_ep_t *ep;
++ dwc_ep_t *dwc_ep;
++
++ ep = get_ep_from_handle(pcd, ep_handle);
++ if (!ep->desc || ep->dwc_ep.num == 0) {
++ DWC_WARN("bad ep\n");
++ return -DWC_E_INVALID;
++ }
++ dwc_ep = &ep->dwc_ep;
++
++ return dwc_ep->pkt_cnt;
++}
++
++void dwc_otg_pcd_get_iso_packet_params(dwc_otg_pcd_t * pcd, void *ep_handle,
++ void *iso_req_handle, int packet,
++ int *status, int *actual, int *offset)
++{
++ dwc_otg_pcd_ep_t *ep;
++ dwc_ep_t *dwc_ep;
++
++ ep = get_ep_from_handle(pcd, ep_handle);
++ if (!ep)
++ DWC_WARN("bad ep\n");
++
++ dwc_ep = &ep->dwc_ep;
++
++ *status = dwc_ep->pkt_info[packet].status;
++ *actual = dwc_ep->pkt_info[packet].length;
++ *offset = dwc_ep->pkt_info[packet].offset;
++}
++
++#endif /* DWC_EN_ISOC */
++
++static void dwc_otg_pcd_init_ep(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * pcd_ep,
++ uint32_t is_in, uint32_t ep_num)
++{
++ /* Init EP structure */
++ pcd_ep->desc = 0;
++ pcd_ep->pcd = pcd;
++ pcd_ep->stopped = 1;
++ pcd_ep->queue_sof = 0;
++
++ /* Init DWC ep structure */
++ pcd_ep->dwc_ep.is_in = is_in;
++ pcd_ep->dwc_ep.num = ep_num;
++ pcd_ep->dwc_ep.active = 0;
++ pcd_ep->dwc_ep.tx_fifo_num = 0;
++ /* Control until ep is actvated */
++ pcd_ep->dwc_ep.type = DWC_OTG_EP_TYPE_CONTROL;
++ pcd_ep->dwc_ep.maxpacket = MAX_PACKET_SIZE;
++ pcd_ep->dwc_ep.dma_addr = 0;
++ pcd_ep->dwc_ep.start_xfer_buff = 0;
++ pcd_ep->dwc_ep.xfer_buff = 0;
++ pcd_ep->dwc_ep.xfer_len = 0;
++ pcd_ep->dwc_ep.xfer_count = 0;
++ pcd_ep->dwc_ep.sent_zlp = 0;
++ pcd_ep->dwc_ep.total_len = 0;
++ pcd_ep->dwc_ep.desc_addr = 0;
++ pcd_ep->dwc_ep.dma_desc_addr = 0;
++ DWC_CIRCLEQ_INIT(&pcd_ep->queue);
++}
++
++/**
++ * Initialize ep's
++ */
++static void dwc_otg_pcd_reinit(dwc_otg_pcd_t * pcd)
++{
++ int i;
++ uint32_t hwcfg1;
++ dwc_otg_pcd_ep_t *ep;
++ int in_ep_cntr, out_ep_cntr;
++ uint32_t num_in_eps = (GET_CORE_IF(pcd))->dev_if->num_in_eps;
++ uint32_t num_out_eps = (GET_CORE_IF(pcd))->dev_if->num_out_eps;
++
++ /**
++ * Initialize the EP0 structure.
++ */
++ ep = &pcd->ep0;
++ dwc_otg_pcd_init_ep(pcd, ep, 0, 0);
++
++ in_ep_cntr = 0;
++ hwcfg1 = (GET_CORE_IF(pcd))->hwcfg1.d32 >> 3;
++ for (i = 1; in_ep_cntr < num_in_eps; i++) {
++ if ((hwcfg1 & 0x1) == 0) {
++ dwc_otg_pcd_ep_t *ep = &pcd->in_ep[in_ep_cntr];
++ in_ep_cntr++;
++ /**
++ * @todo NGS: Add direction to EP, based on contents
++ * of HWCFG1. Need a copy of HWCFG1 in pcd structure?
++ * sprintf(";r
++ */
++ dwc_otg_pcd_init_ep(pcd, ep, 1 /* IN */ , i);
++
++ DWC_CIRCLEQ_INIT(&ep->queue);
++ }
++ hwcfg1 >>= 2;
++ }
++
++ out_ep_cntr = 0;
++ hwcfg1 = (GET_CORE_IF(pcd))->hwcfg1.d32 >> 2;
++ for (i = 1; out_ep_cntr < num_out_eps; i++) {
++ if ((hwcfg1 & 0x1) == 0) {
++ dwc_otg_pcd_ep_t *ep = &pcd->out_ep[out_ep_cntr];
++ out_ep_cntr++;
++ /**
++ * @todo NGS: Add direction to EP, based on contents
++ * of HWCFG1. Need a copy of HWCFG1 in pcd structure?
++ * sprintf(";r
++ */
++ dwc_otg_pcd_init_ep(pcd, ep, 0 /* OUT */ , i);
++ DWC_CIRCLEQ_INIT(&ep->queue);
++ }
++ hwcfg1 >>= 2;
++ }
++
++ pcd->ep0state = EP0_DISCONNECT;
++ pcd->ep0.dwc_ep.maxpacket = MAX_EP0_SIZE;
++ pcd->ep0.dwc_ep.type = DWC_OTG_EP_TYPE_CONTROL;
++}
++
++/**
++ * This function is called when the SRP timer expires. The SRP should
++ * complete within 6 seconds.
++ */
++static void srp_timeout(void *ptr)
++{
++ gotgctl_data_t gotgctl;
++ dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr;
++ volatile uint32_t *addr = &core_if->core_global_regs->gotgctl;
++
++ gotgctl.d32 = DWC_READ_REG32(addr);
++
++ core_if->srp_timer_started = 0;
++
++ if (core_if->adp_enable) {
++ if (gotgctl.b.bsesvld == 0) {
++ gpwrdn_data_t gpwrdn = {.d32 = 0 };
++ DWC_PRINTF("SRP Timeout BSESSVLD = 0\n");
++ /* Power off the core */
++ if (core_if->power_down == 2) {
++ gpwrdn.b.pwrdnswtch = 1;
++ DWC_MODIFY_REG32(&core_if->
++ core_global_regs->gpwrdn,
++ gpwrdn.d32, 0);
++ }
++
++ gpwrdn.d32 = 0;
++ gpwrdn.b.pmuintsel = 1;
++ gpwrdn.b.pmuactv = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0,
++ gpwrdn.d32);
++ dwc_otg_adp_probe_start(core_if);
++ } else {
++ DWC_PRINTF("SRP Timeout BSESSVLD = 1\n");
++ core_if->op_state = B_PERIPHERAL;
++ dwc_otg_core_init(core_if);
++ dwc_otg_enable_global_interrupts(core_if);
++ cil_pcd_start(core_if);
++ }
++ }
++
++ if ((core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS) &&
++ (core_if->core_params->i2c_enable)) {
++ DWC_PRINTF("SRP Timeout\n");
++
++ if ((core_if->srp_success) && (gotgctl.b.bsesvld)) {
++ if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
++ core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);
++ }
++
++ /* Clear Session Request */
++ gotgctl.d32 = 0;
++ gotgctl.b.sesreq = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gotgctl,
++ gotgctl.d32, 0);
++
++ core_if->srp_success = 0;
++ } else {
++ __DWC_ERROR("Device not connected/responding\n");
++ gotgctl.b.sesreq = 0;
++ DWC_WRITE_REG32(addr, gotgctl.d32);
++ }
++ } else if (gotgctl.b.sesreq) {
++ DWC_PRINTF("SRP Timeout\n");
++
++ __DWC_ERROR("Device not connected/responding\n");
++ gotgctl.b.sesreq = 0;
++ DWC_WRITE_REG32(addr, gotgctl.d32);
++ } else {
++ DWC_PRINTF(" SRP GOTGCTL=%0x\n", gotgctl.d32);
++ }
++}
++
++/**
++ * Tasklet
++ *
++ */
++extern void start_next_request(dwc_otg_pcd_ep_t * ep);
++
++static void start_xfer_tasklet_func(void *data)
++{
++ dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) data;
++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++
++ int i;
++ depctl_data_t diepctl;
++
++ DWC_DEBUGPL(DBG_PCDV, "Start xfer tasklet\n");
++
++ diepctl.d32 = DWC_READ_REG32(&core_if->dev_if->in_ep_regs[0]->diepctl);
++
++ if (pcd->ep0.queue_sof) {
++ pcd->ep0.queue_sof = 0;
++ start_next_request(&pcd->ep0);
++ // break;
++ }
++
++ for (i = 0; i < core_if->dev_if->num_in_eps; i++) {
++ depctl_data_t diepctl;
++ diepctl.d32 =
++ DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->diepctl);
++
++ if (pcd->in_ep[i].queue_sof) {
++ pcd->in_ep[i].queue_sof = 0;
++ start_next_request(&pcd->in_ep[i]);
++ // break;
++ }
++ }
++
++ return;
++}
++
++/**
++ * This function initialized the PCD portion of the driver.
++ *
++ */
++dwc_otg_pcd_t *dwc_otg_pcd_init(dwc_otg_core_if_t * core_if)
++{
++ dwc_otg_pcd_t *pcd = NULL;
++ dwc_otg_dev_if_t *dev_if;
++ int i;
++
++ /*
++ * Allocate PCD structure
++ */
++ pcd = DWC_ALLOC(sizeof(dwc_otg_pcd_t));
++
++ if (pcd == NULL) {
++ return NULL;
++ }
++
++#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_SPINLOCK))
++ DWC_SPINLOCK_ALLOC_LINUX_DEBUG(pcd->lock);
++#else
++ pcd->lock = DWC_SPINLOCK_ALLOC();
++#endif
++ DWC_DEBUGPL(DBG_HCDV, "Init of PCD %p given core_if %p\n",
++ pcd, core_if);//GRAYG
++ if (!pcd->lock) {
++ DWC_ERROR("Could not allocate lock for pcd");
++ DWC_FREE(pcd);
++ return NULL;
++ }
++ /* Set core_if's lock pointer to hcd->lock */
++ core_if->lock = pcd->lock;
++ pcd->core_if = core_if;
++
++ dev_if = core_if->dev_if;
++ dev_if->isoc_ep = NULL;
++
++ if (core_if->hwcfg4.b.ded_fifo_en) {
++ DWC_PRINTF("Dedicated Tx FIFOs mode\n");
++ } else {
++ DWC_PRINTF("Shared Tx FIFO mode\n");
++ }
++
++ /*
++ * Initialized the Core for Device mode here if there is nod ADP support.
++ * Otherwise it will be done later in dwc_otg_adp_start routine.
++ */
++ if (dwc_otg_is_device_mode(core_if) /*&& !core_if->adp_enable*/) {
++ dwc_otg_core_dev_init(core_if);
++ }
++
++ /*
++ * Register the PCD Callbacks.
++ */
++ dwc_otg_cil_register_pcd_callbacks(core_if, &pcd_callbacks, pcd);
++
++ /*
++ * Initialize the DMA buffer for SETUP packets
++ */
++ if (GET_CORE_IF(pcd)->dma_enable) {
++ pcd->setup_pkt =
++ DWC_DMA_ALLOC(sizeof(*pcd->setup_pkt) * 5,
++ &pcd->setup_pkt_dma_handle);
++ if (pcd->setup_pkt == NULL) {
++ DWC_FREE(pcd);
++ return NULL;
++ }
++
++ pcd->status_buf =
++ DWC_DMA_ALLOC(sizeof(uint16_t),
++ &pcd->status_buf_dma_handle);
++ if (pcd->status_buf == NULL) {
++ DWC_DMA_FREE(sizeof(*pcd->setup_pkt) * 5,
++ pcd->setup_pkt, pcd->setup_pkt_dma_handle);
++ DWC_FREE(pcd);
++ return NULL;
++ }
++
++ if (GET_CORE_IF(pcd)->dma_desc_enable) {
++ dev_if->setup_desc_addr[0] =
++ dwc_otg_ep_alloc_desc_chain
++ (&dev_if->dma_setup_desc_addr[0], 1);
++ dev_if->setup_desc_addr[1] =
++ dwc_otg_ep_alloc_desc_chain
++ (&dev_if->dma_setup_desc_addr[1], 1);
++ dev_if->in_desc_addr =
++ dwc_otg_ep_alloc_desc_chain
++ (&dev_if->dma_in_desc_addr, 1);
++ dev_if->out_desc_addr =
++ dwc_otg_ep_alloc_desc_chain
++ (&dev_if->dma_out_desc_addr, 1);
++ pcd->data_terminated = 0;
++
++ if (dev_if->setup_desc_addr[0] == 0
++ || dev_if->setup_desc_addr[1] == 0
++ || dev_if->in_desc_addr == 0
++ || dev_if->out_desc_addr == 0) {
++
++ if (dev_if->out_desc_addr)
++ dwc_otg_ep_free_desc_chain
++ (dev_if->out_desc_addr,
++ dev_if->dma_out_desc_addr, 1);
++ if (dev_if->in_desc_addr)
++ dwc_otg_ep_free_desc_chain
++ (dev_if->in_desc_addr,
++ dev_if->dma_in_desc_addr, 1);
++ if (dev_if->setup_desc_addr[1])
++ dwc_otg_ep_free_desc_chain
++ (dev_if->setup_desc_addr[1],
++ dev_if->dma_setup_desc_addr[1], 1);
++ if (dev_if->setup_desc_addr[0])
++ dwc_otg_ep_free_desc_chain
++ (dev_if->setup_desc_addr[0],
++ dev_if->dma_setup_desc_addr[0], 1);
++
++ DWC_DMA_FREE(sizeof(*pcd->setup_pkt) * 5,
++ pcd->setup_pkt,
++ pcd->setup_pkt_dma_handle);
++ DWC_DMA_FREE(sizeof(*pcd->status_buf),
++ pcd->status_buf,
++ pcd->status_buf_dma_handle);
++
++ DWC_FREE(pcd);
++
++ return NULL;
++ }
++ }
++ } else {
++ pcd->setup_pkt = DWC_ALLOC(sizeof(*pcd->setup_pkt) * 5);
++ if (pcd->setup_pkt == NULL) {
++ DWC_FREE(pcd);
++ return NULL;
++ }
++
++ pcd->status_buf = DWC_ALLOC(sizeof(uint16_t));
++ if (pcd->status_buf == NULL) {
++ DWC_FREE(pcd->setup_pkt);
++ DWC_FREE(pcd);
++ return NULL;
++ }
++ }
++
++ dwc_otg_pcd_reinit(pcd);
++
++ /* Allocate the cfi object for the PCD */
++#ifdef DWC_UTE_CFI
++ pcd->cfi = DWC_ALLOC(sizeof(cfiobject_t));
++ if (NULL == pcd->cfi)
++ goto fail;
++ if (init_cfi(pcd->cfi)) {
++ CFI_INFO("%s: Failed to init the CFI object\n", __func__);
++ goto fail;
++ }
++#endif
++
++ /* Initialize tasklets */
++ pcd->start_xfer_tasklet = DWC_TASK_ALLOC("xfer_tasklet",
++ start_xfer_tasklet_func, pcd);
++ pcd->test_mode_tasklet = DWC_TASK_ALLOC("test_mode_tasklet",
++ do_test_mode, pcd);
++
++ /* Initialize SRP timer */
++ core_if->srp_timer = DWC_TIMER_ALLOC("SRP TIMER", srp_timeout, core_if);
++
++ if (core_if->core_params->dev_out_nak) {
++ /**
++ * Initialize xfer timeout timer. Implemented for
++ * 2.93a feature "Device DDMA OUT NAK Enhancement"
++ */
++ for(i = 0; i < MAX_EPS_CHANNELS; i++) {
++ pcd->core_if->ep_xfer_timer[i] =
++ DWC_TIMER_ALLOC("ep timer", ep_xfer_timeout,
++ &pcd->core_if->ep_xfer_info[i]);
++ }
++ }
++
++ return pcd;
++#ifdef DWC_UTE_CFI
++fail:
++#endif
++ if (pcd->setup_pkt)
++ DWC_FREE(pcd->setup_pkt);
++ if (pcd->status_buf)
++ DWC_FREE(pcd->status_buf);
++#ifdef DWC_UTE_CFI
++ if (pcd->cfi)
++ DWC_FREE(pcd->cfi);
++#endif
++ if (pcd)
++ DWC_FREE(pcd);
++ return NULL;
++
++}
++
++/**
++ * Remove PCD specific data
++ */
++void dwc_otg_pcd_remove(dwc_otg_pcd_t * pcd)
++{
++ dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if;
++ int i;
++ if (pcd->core_if->core_params->dev_out_nak) {
++ for (i = 0; i < MAX_EPS_CHANNELS; i++) {
++ DWC_TIMER_CANCEL(pcd->core_if->ep_xfer_timer[i]);
++ pcd->core_if->ep_xfer_info[i].state = 0;
++ }
++ }
++
++ if (GET_CORE_IF(pcd)->dma_enable) {
++ DWC_DMA_FREE(sizeof(*pcd->setup_pkt) * 5, pcd->setup_pkt,
++ pcd->setup_pkt_dma_handle);
++ DWC_DMA_FREE(sizeof(uint16_t), pcd->status_buf,
++ pcd->status_buf_dma_handle);
++ if (GET_CORE_IF(pcd)->dma_desc_enable) {
++ dwc_otg_ep_free_desc_chain(dev_if->setup_desc_addr[0],
++ dev_if->dma_setup_desc_addr
++ [0], 1);
++ dwc_otg_ep_free_desc_chain(dev_if->setup_desc_addr[1],
++ dev_if->dma_setup_desc_addr
++ [1], 1);
++ dwc_otg_ep_free_desc_chain(dev_if->in_desc_addr,
++ dev_if->dma_in_desc_addr, 1);
++ dwc_otg_ep_free_desc_chain(dev_if->out_desc_addr,
++ dev_if->dma_out_desc_addr,
++ 1);
++ }
++ } else {
++ DWC_FREE(pcd->setup_pkt);
++ DWC_FREE(pcd->status_buf);
++ }
++ DWC_SPINLOCK_FREE(pcd->lock);
++ /* Set core_if's lock pointer to NULL */
++ pcd->core_if->lock = NULL;
++
++ DWC_TASK_FREE(pcd->start_xfer_tasklet);
++ DWC_TASK_FREE(pcd->test_mode_tasklet);
++ if (pcd->core_if->core_params->dev_out_nak) {
++ for (i = 0; i < MAX_EPS_CHANNELS; i++) {
++ if (pcd->core_if->ep_xfer_timer[i]) {
++ DWC_TIMER_FREE(pcd->core_if->ep_xfer_timer[i]);
++ }
++ }
++ }
++
++/* Release the CFI object's dynamic memory */
++#ifdef DWC_UTE_CFI
++ if (pcd->cfi->ops.release) {
++ pcd->cfi->ops.release(pcd->cfi);
++ }
++#endif
++
++ DWC_FREE(pcd);
++}
++
++/**
++ * Returns whether registered pcd is dual speed or not
++ */
++uint32_t dwc_otg_pcd_is_dualspeed(dwc_otg_pcd_t * pcd)
++{
++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++
++ if ((core_if->core_params->speed == DWC_SPEED_PARAM_FULL) ||
++ ((core_if->hwcfg2.b.hs_phy_type == 2) &&
++ (core_if->hwcfg2.b.fs_phy_type == 1) &&
++ (core_if->core_params->ulpi_fs_ls))) {
++ return 0;
++ }
++
++ return 1;
++}
++
++/**
++ * Returns whether registered pcd is OTG capable or not
++ */
++uint32_t dwc_otg_pcd_is_otg(dwc_otg_pcd_t * pcd)
++{
++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++ gusbcfg_data_t usbcfg = {.d32 = 0 };
++
++ usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
++ if (!usbcfg.b.srpcap || !usbcfg.b.hnpcap) {
++ return 0;
++ }
++
++ return 1;
++}
++
++/**
++ * This function assigns periodic Tx FIFO to an periodic EP
++ * in shared Tx FIFO mode
++ */
++static uint32_t assign_tx_fifo(dwc_otg_core_if_t * core_if)
++{
++ uint32_t TxMsk = 1;
++ int i;
++
++ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; ++i) {
++ if ((TxMsk & core_if->tx_msk) == 0) {
++ core_if->tx_msk |= TxMsk;
++ return i + 1;
++ }
++ TxMsk <<= 1;
++ }
++ return 0;
++}
++
++/**
++ * This function assigns periodic Tx FIFO to an periodic EP
++ * in shared Tx FIFO mode
++ */
++static uint32_t assign_perio_tx_fifo(dwc_otg_core_if_t * core_if)
++{
++ uint32_t PerTxMsk = 1;
++ int i;
++ for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; ++i) {
++ if ((PerTxMsk & core_if->p_tx_msk) == 0) {
++ core_if->p_tx_msk |= PerTxMsk;
++ return i + 1;
++ }
++ PerTxMsk <<= 1;
++ }
++ return 0;
++}
++
++/**
++ * This function releases periodic Tx FIFO
++ * in shared Tx FIFO mode
++ */
++static void release_perio_tx_fifo(dwc_otg_core_if_t * core_if,
++ uint32_t fifo_num)
++{
++ core_if->p_tx_msk =
++ (core_if->p_tx_msk & (1 << (fifo_num - 1))) ^ core_if->p_tx_msk;
++}
++
++/**
++ * This function releases periodic Tx FIFO
++ * in shared Tx FIFO mode
++ */
++static void release_tx_fifo(dwc_otg_core_if_t * core_if, uint32_t fifo_num)
++{
++ core_if->tx_msk =
++ (core_if->tx_msk & (1 << (fifo_num - 1))) ^ core_if->tx_msk;
++}
++
++/**
++ * This function is being called from gadget
++ * to enable PCD endpoint.
++ */
++int dwc_otg_pcd_ep_enable(dwc_otg_pcd_t * pcd,
++ const uint8_t * ep_desc, void *usb_ep)
++{
++ int num, dir;
++ dwc_otg_pcd_ep_t *ep = NULL;
++ const usb_endpoint_descriptor_t *desc;
++ dwc_irqflags_t flags;
++ fifosize_data_t dptxfsiz = {.d32 = 0 };
++ gdfifocfg_data_t gdfifocfg = {.d32 = 0 };
++ gdfifocfg_data_t gdfifocfgbase = {.d32 = 0 };
++ int retval = 0;
++ int i, epcount;
++
++ desc = (const usb_endpoint_descriptor_t *)ep_desc;
++
++ if (!desc) {
++ pcd->ep0.priv = usb_ep;
++ ep = &pcd->ep0;
++ retval = -DWC_E_INVALID;
++ goto out;
++ }
++
++ num = UE_GET_ADDR(desc->bEndpointAddress);
++ dir = UE_GET_DIR(desc->bEndpointAddress);
++
++ if (!desc->wMaxPacketSize) {
++ DWC_WARN("bad maxpacketsize\n");
++ retval = -DWC_E_INVALID;
++ goto out;
++ }
++
++ if (dir == UE_DIR_IN) {
++ epcount = pcd->core_if->dev_if->num_in_eps;
++ for (i = 0; i < epcount; i++) {
++ if (num == pcd->in_ep[i].dwc_ep.num) {
++ ep = &pcd->in_ep[i];
++ break;
++ }
++ }
++ } else {
++ epcount = pcd->core_if->dev_if->num_out_eps;
++ for (i = 0; i < epcount; i++) {
++ if (num == pcd->out_ep[i].dwc_ep.num) {
++ ep = &pcd->out_ep[i];
++ break;
++ }
++ }
++ }
++
++ if (!ep) {
++ DWC_WARN("bad address\n");
++ retval = -DWC_E_INVALID;
++ goto out;
++ }
++
++ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
++
++ ep->desc = desc;
++ ep->priv = usb_ep;
++
++ /*
++ * Activate the EP
++ */
++ ep->stopped = 0;
++
++ ep->dwc_ep.is_in = (dir == UE_DIR_IN);
++ ep->dwc_ep.maxpacket = UGETW(desc->wMaxPacketSize);
++
++ ep->dwc_ep.type = desc->bmAttributes & UE_XFERTYPE;
++
++ if (ep->dwc_ep.is_in) {
++ if (!GET_CORE_IF(pcd)->en_multiple_tx_fifo) {
++ ep->dwc_ep.tx_fifo_num = 0;
++
++ if (ep->dwc_ep.type == UE_ISOCHRONOUS) {
++ /*
++ * if ISOC EP then assign a Periodic Tx FIFO.
++ */
++ ep->dwc_ep.tx_fifo_num =
++ assign_perio_tx_fifo(GET_CORE_IF(pcd));
++ }
++ } else {
++ /*
++ * if Dedicated FIFOs mode is on then assign a Tx FIFO.
++ */
++ ep->dwc_ep.tx_fifo_num =
++ assign_tx_fifo(GET_CORE_IF(pcd));
++ }
++
++ /* Calculating EP info controller base address */
++ if (ep->dwc_ep.tx_fifo_num
++ && GET_CORE_IF(pcd)->en_multiple_tx_fifo) {
++ gdfifocfg.d32 =
++ DWC_READ_REG32(&GET_CORE_IF(pcd)->
++ core_global_regs->gdfifocfg);
++ gdfifocfgbase.d32 = gdfifocfg.d32 >> 16;
++ dptxfsiz.d32 =
++ (DWC_READ_REG32
++ (&GET_CORE_IF(pcd)->core_global_regs->
++ dtxfsiz[ep->dwc_ep.tx_fifo_num - 1]) >> 16);
++ gdfifocfg.b.epinfobase =
++ gdfifocfgbase.d32 + dptxfsiz.d32;
++ if (GET_CORE_IF(pcd)->snpsid <= OTG_CORE_REV_2_94a) {
++ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->
++ core_global_regs->gdfifocfg,
++ gdfifocfg.d32);
++ }
++ }
++ }
++ /* Set initial data PID. */
++ if (ep->dwc_ep.type == UE_BULK) {
++ ep->dwc_ep.data_pid_start = 0;
++ }
++
++ /* Alloc DMA Descriptors */
++ if (GET_CORE_IF(pcd)->dma_desc_enable) {
++#ifndef DWC_UTE_PER_IO
++ if (ep->dwc_ep.type != UE_ISOCHRONOUS) {
++#endif
++ ep->dwc_ep.desc_addr =
++ dwc_otg_ep_alloc_desc_chain(&ep->
++ dwc_ep.dma_desc_addr,
++ MAX_DMA_DESC_CNT);
++ if (!ep->dwc_ep.desc_addr) {
++ DWC_WARN("%s, can't allocate DMA descriptor\n",
++ __func__);
++ retval = -DWC_E_SHUTDOWN;
++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
++ goto out;
++ }
++#ifndef DWC_UTE_PER_IO
++ }
++#endif
++ }
++
++ DWC_DEBUGPL(DBG_PCD, "Activate %s: type=%d, mps=%d desc=%p\n",
++ (ep->dwc_ep.is_in ? "IN" : "OUT"),
++ ep->dwc_ep.type, ep->dwc_ep.maxpacket, ep->desc);
++#ifdef DWC_UTE_PER_IO
++ ep->dwc_ep.xiso_bInterval = 1 << (ep->desc->bInterval - 1);
++#endif
++ if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
++ ep->dwc_ep.bInterval = 1 << (ep->desc->bInterval - 1);
++ ep->dwc_ep.frame_num = 0xFFFFFFFF;
++ }
++
++ dwc_otg_ep_activate(GET_CORE_IF(pcd), &ep->dwc_ep);
++
++#ifdef DWC_UTE_CFI
++ if (pcd->cfi->ops.ep_enable) {
++ pcd->cfi->ops.ep_enable(pcd->cfi, pcd, ep);
++ }
++#endif
++
++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
++
++out:
++ return retval;
++}
++
++/**
++ * This function is being called from gadget
++ * to disable PCD endpoint.
++ */
++int dwc_otg_pcd_ep_disable(dwc_otg_pcd_t * pcd, void *ep_handle)
++{
++ dwc_otg_pcd_ep_t *ep;
++ dwc_irqflags_t flags;
++ dwc_otg_dev_dma_desc_t *desc_addr;
++ dwc_dma_t dma_desc_addr;
++ gdfifocfg_data_t gdfifocfgbase = {.d32 = 0 };
++ gdfifocfg_data_t gdfifocfg = {.d32 = 0 };
++ fifosize_data_t dptxfsiz = {.d32 = 0 };
++
++ ep = get_ep_from_handle(pcd, ep_handle);
++
++ if (!ep || !ep->desc) {
++ DWC_DEBUGPL(DBG_PCD, "bad ep address\n");
++ return -DWC_E_INVALID;
++ }
++
++ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
++
++ dwc_otg_request_nuke(ep);
++
++ dwc_otg_ep_deactivate(GET_CORE_IF(pcd), &ep->dwc_ep);
++ if (pcd->core_if->core_params->dev_out_nak) {
++ DWC_TIMER_CANCEL(pcd->core_if->ep_xfer_timer[ep->dwc_ep.num]);
++ pcd->core_if->ep_xfer_info[ep->dwc_ep.num].state = 0;
++ }
++ ep->desc = NULL;
++ ep->stopped = 1;
++
++ gdfifocfg.d32 =
++ DWC_READ_REG32(&GET_CORE_IF(pcd)->core_global_regs->gdfifocfg);
++ gdfifocfgbase.d32 = gdfifocfg.d32 >> 16;
++
++ if (ep->dwc_ep.is_in) {
++ if (GET_CORE_IF(pcd)->en_multiple_tx_fifo) {
++ /* Flush the Tx FIFO */
++ dwc_otg_flush_tx_fifo(GET_CORE_IF(pcd),
++ ep->dwc_ep.tx_fifo_num);
++ }
++ release_perio_tx_fifo(GET_CORE_IF(pcd), ep->dwc_ep.tx_fifo_num);
++ release_tx_fifo(GET_CORE_IF(pcd), ep->dwc_ep.tx_fifo_num);
++ if (GET_CORE_IF(pcd)->en_multiple_tx_fifo) {
++ /* Decreasing EPinfo Base Addr */
++ dptxfsiz.d32 =
++ (DWC_READ_REG32
++ (&GET_CORE_IF(pcd)->
++ core_global_regs->dtxfsiz[ep->dwc_ep.tx_fifo_num-1]) >> 16);
++ gdfifocfg.b.epinfobase = gdfifocfgbase.d32 - dptxfsiz.d32;
++ if (GET_CORE_IF(pcd)->snpsid <= OTG_CORE_REV_2_94a) {
++ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gdfifocfg,
++ gdfifocfg.d32);
++ }
++ }
++ }
++
++ /* Free DMA Descriptors */
++ if (GET_CORE_IF(pcd)->dma_desc_enable) {
++ if (ep->dwc_ep.type != UE_ISOCHRONOUS) {
++ desc_addr = ep->dwc_ep.desc_addr;
++ dma_desc_addr = ep->dwc_ep.dma_desc_addr;
++
++ /* Cannot call dma_free_coherent() with IRQs disabled */
++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
++ dwc_otg_ep_free_desc_chain(desc_addr, dma_desc_addr,
++ MAX_DMA_DESC_CNT);
++
++ goto out_unlocked;
++ }
++ }
++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
++
++out_unlocked:
++ DWC_DEBUGPL(DBG_PCD, "%d %s disabled\n", ep->dwc_ep.num,
++ ep->dwc_ep.is_in ? "IN" : "OUT");
++ return 0;
++
++}
++
++/******************************************************************************/
++#ifdef DWC_UTE_PER_IO
++
++/**
++ * Free the request and its extended parts
++ *
++ */
++void dwc_pcd_xiso_ereq_free(dwc_otg_pcd_ep_t * ep, dwc_otg_pcd_request_t * req)
++{
++ DWC_FREE(req->ext_req.per_io_frame_descs);
++ DWC_FREE(req);
++}
++
++/**
++ * Start the next request in the endpoint's queue.
++ *
++ */
++int dwc_otg_pcd_xiso_start_next_request(dwc_otg_pcd_t * pcd,
++ dwc_otg_pcd_ep_t * ep)
++{
++ int i;
++ dwc_otg_pcd_request_t *req = NULL;
++ dwc_ep_t *dwcep = NULL;
++ struct dwc_iso_xreq_port *ereq = NULL;
++ struct dwc_iso_pkt_desc_port *ddesc_iso;
++ uint16_t nat;
++ depctl_data_t diepctl;
++
++ dwcep = &ep->dwc_ep;
++
++ if (dwcep->xiso_active_xfers > 0) {
++#if 0 //Disable this to decrease s/w overhead that is crucial for Isoc transfers
++ DWC_WARN("There are currently active transfers for EP%d \
++ (active=%d; queued=%d)", dwcep->num, dwcep->xiso_active_xfers,
++ dwcep->xiso_queued_xfers);
++#endif
++ return 0;
++ }
++
++ nat = UGETW(ep->desc->wMaxPacketSize);
++ nat = (nat >> 11) & 0x03;
++
++ if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
++ req = DWC_CIRCLEQ_FIRST(&ep->queue);
++ ereq = &req->ext_req;
++ ep->stopped = 0;
++
++ /* Get the frame number */
++ dwcep->xiso_frame_num =
++ dwc_otg_get_frame_number(GET_CORE_IF(pcd));
++ DWC_DEBUG("FRM_NUM=%d", dwcep->xiso_frame_num);
++
++ ddesc_iso = ereq->per_io_frame_descs;
++
++ if (dwcep->is_in) {
++ /* Setup DMA Descriptor chain for IN Isoc request */
++ for (i = 0; i < ereq->pio_pkt_count; i++) {
++ //if ((i % (nat + 1)) == 0)
++ if ( i > 0 )
++ dwcep->xiso_frame_num =
++ (dwcep->xiso_bInterval +
++ dwcep->xiso_frame_num) & 0x3FFF;
++ dwcep->desc_addr[i].buf =
++ req->dma + ddesc_iso[i].offset;
++ dwcep->desc_addr[i].status.b_iso_in.txbytes =
++ ddesc_iso[i].length;
++ dwcep->desc_addr[i].status.b_iso_in.framenum =
++ dwcep->xiso_frame_num;
++ dwcep->desc_addr[i].status.b_iso_in.bs =
++ BS_HOST_READY;
++ dwcep->desc_addr[i].status.b_iso_in.txsts = 0;
++ dwcep->desc_addr[i].status.b_iso_in.sp =
++ (ddesc_iso[i].length %
++ dwcep->maxpacket) ? 1 : 0;
++ dwcep->desc_addr[i].status.b_iso_in.ioc = 0;
++ dwcep->desc_addr[i].status.b_iso_in.pid = nat + 1;
++ dwcep->desc_addr[i].status.b_iso_in.l = 0;
++
++ /* Process the last descriptor */
++ if (i == ereq->pio_pkt_count - 1) {
++ dwcep->desc_addr[i].status.b_iso_in.ioc = 1;
++ dwcep->desc_addr[i].status.b_iso_in.l = 1;
++ }
++ }
++
++ /* Setup and start the transfer for this endpoint */
++ dwcep->xiso_active_xfers++;
++ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->dev_if->
++ in_ep_regs[dwcep->num]->diepdma,
++ dwcep->dma_desc_addr);
++ diepctl.d32 = 0;
++ diepctl.b.epena = 1;
++ diepctl.b.cnak = 1;
++ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->dev_if->
++ in_ep_regs[dwcep->num]->diepctl, 0,
++ diepctl.d32);
++ } else {
++ /* Setup DMA Descriptor chain for OUT Isoc request */
++ for (i = 0; i < ereq->pio_pkt_count; i++) {
++ //if ((i % (nat + 1)) == 0)
++ dwcep->xiso_frame_num = (dwcep->xiso_bInterval +
++ dwcep->xiso_frame_num) & 0x3FFF;
++ dwcep->desc_addr[i].buf =
++ req->dma + ddesc_iso[i].offset;
++ dwcep->desc_addr[i].status.b_iso_out.rxbytes =
++ ddesc_iso[i].length;
++ dwcep->desc_addr[i].status.b_iso_out.framenum =
++ dwcep->xiso_frame_num;
++ dwcep->desc_addr[i].status.b_iso_out.bs =
++ BS_HOST_READY;
++ dwcep->desc_addr[i].status.b_iso_out.rxsts = 0;
++ dwcep->desc_addr[i].status.b_iso_out.sp =
++ (ddesc_iso[i].length %
++ dwcep->maxpacket) ? 1 : 0;
++ dwcep->desc_addr[i].status.b_iso_out.ioc = 0;
++ dwcep->desc_addr[i].status.b_iso_out.pid = nat + 1;
++ dwcep->desc_addr[i].status.b_iso_out.l = 0;
++
++ /* Process the last descriptor */
++ if (i == ereq->pio_pkt_count - 1) {
++ dwcep->desc_addr[i].status.b_iso_out.ioc = 1;
++ dwcep->desc_addr[i].status.b_iso_out.l = 1;
++ }
++ }
++
++ /* Setup and start the transfer for this endpoint */
++ dwcep->xiso_active_xfers++;
++ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->
++ dev_if->out_ep_regs[dwcep->num]->
++ doepdma, dwcep->dma_desc_addr);
++ diepctl.d32 = 0;
++ diepctl.b.epena = 1;
++ diepctl.b.cnak = 1;
++ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->
++ dev_if->out_ep_regs[dwcep->num]->
++ doepctl, 0, diepctl.d32);
++ }
++
++ } else {
++ ep->stopped = 1;
++ }
++
++ return 0;
++}
++
++/**
++ * - Remove the request from the queue
++ */
++void complete_xiso_ep(dwc_otg_pcd_ep_t * ep)
++{
++ dwc_otg_pcd_request_t *req = NULL;
++ struct dwc_iso_xreq_port *ereq = NULL;
++ struct dwc_iso_pkt_desc_port *ddesc_iso = NULL;
++ dwc_ep_t *dwcep = NULL;
++ int i;
++
++ //DWC_DEBUG();
++ dwcep = &ep->dwc_ep;
++
++ /* Get the first pending request from the queue */
++ if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
++ req = DWC_CIRCLEQ_FIRST(&ep->queue);
++ if (!req) {
++ DWC_PRINTF("complete_ep 0x%p, req = NULL!\n", ep);
++ return;
++ }
++ dwcep->xiso_active_xfers--;
++ dwcep->xiso_queued_xfers--;
++ /* Remove this request from the queue */
++ DWC_CIRCLEQ_REMOVE_INIT(&ep->queue, req, queue_entry);
++ } else {
++ DWC_PRINTF("complete_ep 0x%p, ep->queue empty!\n", ep);
++ return;
++ }
++
++ ep->stopped = 1;
++ ereq = &req->ext_req;
++ ddesc_iso = ereq->per_io_frame_descs;
++
++ if (dwcep->xiso_active_xfers < 0) {
++ DWC_WARN("EP#%d (xiso_active_xfers=%d)", dwcep->num,
++ dwcep->xiso_active_xfers);
++ }
++
++ /* Fill the Isoc descs of portable extended req from dma descriptors */
++ for (i = 0; i < ereq->pio_pkt_count; i++) {
++ if (dwcep->is_in) { /* IN endpoints */
++ ddesc_iso[i].actual_length = ddesc_iso[i].length -
++ dwcep->desc_addr[i].status.b_iso_in.txbytes;
++ ddesc_iso[i].status =
++ dwcep->desc_addr[i].status.b_iso_in.txsts;
++ } else { /* OUT endpoints */
++ ddesc_iso[i].actual_length = ddesc_iso[i].length -
++ dwcep->desc_addr[i].status.b_iso_out.rxbytes;
++ ddesc_iso[i].status =
++ dwcep->desc_addr[i].status.b_iso_out.rxsts;
++ }
++ }
++
++ DWC_SPINUNLOCK(ep->pcd->lock);
++
++ /* Call the completion function in the non-portable logic */
++ ep->pcd->fops->xisoc_complete(ep->pcd, ep->priv, req->priv, 0,
++ &req->ext_req);
++
++ DWC_SPINLOCK(ep->pcd->lock);
++
++ /* Free the request - specific freeing needed for extended request object */
++ dwc_pcd_xiso_ereq_free(ep, req);
++
++ /* Start the next request */
++ dwc_otg_pcd_xiso_start_next_request(ep->pcd, ep);
++
++ return;
++}
++
++/**
++ * Create and initialize the Isoc pkt descriptors of the extended request.
++ *
++ */
++static int dwc_otg_pcd_xiso_create_pkt_descs(dwc_otg_pcd_request_t * req,
++ void *ereq_nonport,
++ int atomic_alloc)
++{
++ struct dwc_iso_xreq_port *ereq = NULL;
++ struct dwc_iso_xreq_port *req_mapped = NULL;
++ struct dwc_iso_pkt_desc_port *ipds = NULL; /* To be created in this function */
++ uint32_t pkt_count;
++ int i;
++
++ ereq = &req->ext_req;
++ req_mapped = (struct dwc_iso_xreq_port *)ereq_nonport;
++ pkt_count = req_mapped->pio_pkt_count;
++
++ /* Create the isoc descs */
++ if (atomic_alloc) {
++ ipds = DWC_ALLOC_ATOMIC(sizeof(*ipds) * pkt_count);
++ } else {
++ ipds = DWC_ALLOC(sizeof(*ipds) * pkt_count);
++ }
++
++ if (!ipds) {
++ DWC_ERROR("Failed to allocate isoc descriptors");
++ return -DWC_E_NO_MEMORY;
++ }
++
++ /* Initialize the extended request fields */
++ ereq->per_io_frame_descs = ipds;
++ ereq->error_count = 0;
++ ereq->pio_alloc_pkt_count = pkt_count;
++ ereq->pio_pkt_count = pkt_count;
++ ereq->tr_sub_flags = req_mapped->tr_sub_flags;
++
++ /* Init the Isoc descriptors */
++ for (i = 0; i < pkt_count; i++) {
++ ipds[i].length = req_mapped->per_io_frame_descs[i].length;
++ ipds[i].offset = req_mapped->per_io_frame_descs[i].offset;
++ ipds[i].status = req_mapped->per_io_frame_descs[i].status; /* 0 */
++ ipds[i].actual_length =
++ req_mapped->per_io_frame_descs[i].actual_length;
++ }
++
++ return 0;
++}
++
++static void prn_ext_request(struct dwc_iso_xreq_port *ereq)
++{
++ struct dwc_iso_pkt_desc_port *xfd = NULL;
++ int i;
++
++ DWC_DEBUG("per_io_frame_descs=%p", ereq->per_io_frame_descs);
++ DWC_DEBUG("tr_sub_flags=%d", ereq->tr_sub_flags);
++ DWC_DEBUG("error_count=%d", ereq->error_count);
++ DWC_DEBUG("pio_alloc_pkt_count=%d", ereq->pio_alloc_pkt_count);
++ DWC_DEBUG("pio_pkt_count=%d", ereq->pio_pkt_count);
++ DWC_DEBUG("res=%d", ereq->res);
++
++ for (i = 0; i < ereq->pio_pkt_count; i++) {
++ xfd = &ereq->per_io_frame_descs[0];
++ DWC_DEBUG("FD #%d", i);
++
++ DWC_DEBUG("xfd->actual_length=%d", xfd->actual_length);
++ DWC_DEBUG("xfd->length=%d", xfd->length);
++ DWC_DEBUG("xfd->offset=%d", xfd->offset);
++ DWC_DEBUG("xfd->status=%d", xfd->status);
++ }
++}
++
++/**
++ *
++ */
++int dwc_otg_pcd_xiso_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle,
++ uint8_t * buf, dwc_dma_t dma_buf, uint32_t buflen,
++ int zero, void *req_handle, int atomic_alloc,
++ void *ereq_nonport)
++{
++ dwc_otg_pcd_request_t *req = NULL;
++ dwc_otg_pcd_ep_t *ep;
++ dwc_irqflags_t flags;
++ int res;
++
++ ep = get_ep_from_handle(pcd, ep_handle);
++ if (!ep) {
++ DWC_WARN("bad ep\n");
++ return -DWC_E_INVALID;
++ }
++
++ /* We support this extension only for DDMA mode */
++ if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC)
++ if (!GET_CORE_IF(pcd)->dma_desc_enable)
++ return -DWC_E_INVALID;
++
++ /* Create a dwc_otg_pcd_request_t object */
++ if (atomic_alloc) {
++ req = DWC_ALLOC_ATOMIC(sizeof(*req));
++ } else {
++ req = DWC_ALLOC(sizeof(*req));
++ }
++
++ if (!req) {
++ return -DWC_E_NO_MEMORY;
++ }
++
++ /* Create the Isoc descs for this request which shall be the exact match
++ * of the structure sent to us from the non-portable logic */
++ res =
++ dwc_otg_pcd_xiso_create_pkt_descs(req, ereq_nonport, atomic_alloc);
++ if (res) {
++ DWC_WARN("Failed to init the Isoc descriptors");
++ DWC_FREE(req);
++ return res;
++ }
++
++ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
++
++ DWC_CIRCLEQ_INIT_ENTRY(req, queue_entry);
++ req->buf = buf;
++ req->dma = dma_buf;
++ req->length = buflen;
++ req->sent_zlp = zero;
++ req->priv = req_handle;
++
++ //DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
++ ep->dwc_ep.dma_addr = dma_buf;
++ ep->dwc_ep.start_xfer_buff = buf;
++ ep->dwc_ep.xfer_buff = buf;
++ ep->dwc_ep.xfer_len = 0;
++ ep->dwc_ep.xfer_count = 0;
++ ep->dwc_ep.sent_zlp = 0;
++ ep->dwc_ep.total_len = buflen;
++
++ /* Add this request to the tail */
++ DWC_CIRCLEQ_INSERT_TAIL(&ep->queue, req, queue_entry);
++ ep->dwc_ep.xiso_queued_xfers++;
++
++//DWC_DEBUG("CP_0");
++//DWC_DEBUG("req->ext_req.tr_sub_flags=%d", req->ext_req.tr_sub_flags);
++//prn_ext_request((struct dwc_iso_xreq_port *) ereq_nonport);
++//prn_ext_request(&req->ext_req);
++
++ //DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
++
++ /* If the req->status == ASAP then check if there is any active transfer
++ * for this endpoint. If no active transfers, then get the first entry
++ * from the queue and start that transfer
++ */
++ if (req->ext_req.tr_sub_flags == DWC_EREQ_TF_ASAP) {
++ res = dwc_otg_pcd_xiso_start_next_request(pcd, ep);
++ if (res) {
++ DWC_WARN("Failed to start the next Isoc transfer");
++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
++ DWC_FREE(req);
++ return res;
++ }
++ }
++
++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
++ return 0;
++}
++
++#endif
++/* END ifdef DWC_UTE_PER_IO ***************************************************/
++int dwc_otg_pcd_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle,
++ uint8_t * buf, dwc_dma_t dma_buf, uint32_t buflen,
++ int zero, void *req_handle, int atomic_alloc)
++{
++ dwc_irqflags_t flags;
++ dwc_otg_pcd_request_t *req;
++ dwc_otg_pcd_ep_t *ep;
++ uint32_t max_transfer;
++
++ ep = get_ep_from_handle(pcd, ep_handle);
++ if (!ep || (!ep->desc && ep->dwc_ep.num != 0)) {
++ DWC_WARN("bad ep\n");
++ return -DWC_E_INVALID;
++ }
++
++ if (atomic_alloc) {
++ req = DWC_ALLOC_ATOMIC(sizeof(*req));
++ } else {
++ req = DWC_ALLOC(sizeof(*req));
++ }
++
++ if (!req) {
++ return -DWC_E_NO_MEMORY;
++ }
++ DWC_CIRCLEQ_INIT_ENTRY(req, queue_entry);
++ if (!GET_CORE_IF(pcd)->core_params->opt) {
++ if (ep->dwc_ep.num != 0) {
++ DWC_ERROR("queue req %p, len %d buf %p\n",
++ req_handle, buflen, buf);
++ }
++ }
++
++ req->buf = buf;
++ req->dma = dma_buf;
++ req->length = buflen;
++ req->sent_zlp = zero;
++ req->priv = req_handle;
++ req->dw_align_buf = NULL;
++ if ((dma_buf & 0x3) && GET_CORE_IF(pcd)->dma_enable
++ && !GET_CORE_IF(pcd)->dma_desc_enable)
++ req->dw_align_buf = DWC_DMA_ALLOC(buflen,
++ &req->dw_align_buf_dma);
++ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
++
++ /*
++ * After adding request to the queue for IN ISOC wait for In Token Received
++ * when TX FIFO is empty interrupt and for OUT ISOC wait for OUT Token
++ * Received when EP is disabled interrupt to obtain starting microframe
++ * (odd/even) start transfer
++ */
++ if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
++ if (req != 0) {
++ depctl_data_t depctl = {.d32 =
++ DWC_READ_REG32(&pcd->core_if->dev_if->
++ in_ep_regs[ep->dwc_ep.num]->
++ diepctl) };
++ ++pcd->request_pending;
++
++ DWC_CIRCLEQ_INSERT_TAIL(&ep->queue, req, queue_entry);
++ if (ep->dwc_ep.is_in) {
++ depctl.b.cnak = 1;
++ DWC_WRITE_REG32(&pcd->core_if->dev_if->
++ in_ep_regs[ep->dwc_ep.num]->
++ diepctl, depctl.d32);
++ }
++
++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
++ }
++ return 0;
++ }
++
++ /*
++ * For EP0 IN without premature status, zlp is required?
++ */
++ if (ep->dwc_ep.num == 0 && ep->dwc_ep.is_in) {
++ DWC_DEBUGPL(DBG_PCDV, "%d-OUT ZLP\n", ep->dwc_ep.num);
++ //_req->zero = 1;
++ }
++
++ /* Start the transfer */
++ if (DWC_CIRCLEQ_EMPTY(&ep->queue) && !ep->stopped) {
++ /* EP0 Transfer? */
++ if (ep->dwc_ep.num == 0) {
++ switch (pcd->ep0state) {
++ case EP0_IN_DATA_PHASE:
++ DWC_DEBUGPL(DBG_PCD,
++ "%s ep0: EP0_IN_DATA_PHASE\n",
++ __func__);
++ break;
++
++ case EP0_OUT_DATA_PHASE:
++ DWC_DEBUGPL(DBG_PCD,
++ "%s ep0: EP0_OUT_DATA_PHASE\n",
++ __func__);
++ if (pcd->request_config) {
++ /* Complete STATUS PHASE */
++ ep->dwc_ep.is_in = 1;
++ pcd->ep0state = EP0_IN_STATUS_PHASE;
++ }
++ break;
++
++ case EP0_IN_STATUS_PHASE:
++ DWC_DEBUGPL(DBG_PCD,
++ "%s ep0: EP0_IN_STATUS_PHASE\n",
++ __func__);
++ break;
++
++ default:
++ DWC_DEBUGPL(DBG_ANY, "ep0: odd state %d\n",
++ pcd->ep0state);
++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
++ return -DWC_E_SHUTDOWN;
++ }
++
++ ep->dwc_ep.dma_addr = dma_buf;
++ ep->dwc_ep.start_xfer_buff = buf;
++ ep->dwc_ep.xfer_buff = buf;
++ ep->dwc_ep.xfer_len = buflen;
++ ep->dwc_ep.xfer_count = 0;
++ ep->dwc_ep.sent_zlp = 0;
++ ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
++
++ if (zero) {
++ if ((ep->dwc_ep.xfer_len %
++ ep->dwc_ep.maxpacket == 0)
++ && (ep->dwc_ep.xfer_len != 0)) {
++ ep->dwc_ep.sent_zlp = 1;
++ }
++
++ }
++
++ dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd),
++ &ep->dwc_ep);
++ } // non-ep0 endpoints
++ else {
++#ifdef DWC_UTE_CFI
++ if (ep->dwc_ep.buff_mode != BM_STANDARD) {
++ /* store the request length */
++ ep->dwc_ep.cfi_req_len = buflen;
++ pcd->cfi->ops.build_descriptors(pcd->cfi, pcd,
++ ep, req);
++ } else {
++#endif
++ max_transfer =
++ GET_CORE_IF(ep->pcd)->core_params->
++ max_transfer_size;
++
++ /* Setup and start the Transfer */
++ if (req->dw_align_buf){
++ if (ep->dwc_ep.is_in)
++ dwc_memcpy(req->dw_align_buf,
++ buf, buflen);
++ ep->dwc_ep.dma_addr =
++ req->dw_align_buf_dma;
++ ep->dwc_ep.start_xfer_buff =
++ req->dw_align_buf;
++ ep->dwc_ep.xfer_buff =
++ req->dw_align_buf;
++ } else {
++ ep->dwc_ep.dma_addr = dma_buf;
++ ep->dwc_ep.start_xfer_buff = buf;
++ ep->dwc_ep.xfer_buff = buf;
++ }
++ ep->dwc_ep.xfer_len = 0;
++ ep->dwc_ep.xfer_count = 0;
++ ep->dwc_ep.sent_zlp = 0;
++ ep->dwc_ep.total_len = buflen;
++
++ ep->dwc_ep.maxxfer = max_transfer;
++ if (GET_CORE_IF(pcd)->dma_desc_enable) {
++ uint32_t out_max_xfer =
++ DDMA_MAX_TRANSFER_SIZE -
++ (DDMA_MAX_TRANSFER_SIZE % 4);
++ if (ep->dwc_ep.is_in) {
++ if (ep->dwc_ep.maxxfer >
++ DDMA_MAX_TRANSFER_SIZE) {
++ ep->dwc_ep.maxxfer =
++ DDMA_MAX_TRANSFER_SIZE;
++ }
++ } else {
++ if (ep->dwc_ep.maxxfer >
++ out_max_xfer) {
++ ep->dwc_ep.maxxfer =
++ out_max_xfer;
++ }
++ }
++ }
++ if (ep->dwc_ep.maxxfer < ep->dwc_ep.total_len) {
++ ep->dwc_ep.maxxfer -=
++ (ep->dwc_ep.maxxfer %
++ ep->dwc_ep.maxpacket);
++ }
++
++ if (zero) {
++ if ((ep->dwc_ep.total_len %
++ ep->dwc_ep.maxpacket == 0)
++ && (ep->dwc_ep.total_len != 0)) {
++ ep->dwc_ep.sent_zlp = 1;
++ }
++ }
++#ifdef DWC_UTE_CFI
++ }
++#endif
++ dwc_otg_ep_start_transfer(GET_CORE_IF(pcd),
++ &ep->dwc_ep);
++ }
++ }
++
++ if (req != 0) {
++ ++pcd->request_pending;
++ DWC_CIRCLEQ_INSERT_TAIL(&ep->queue, req, queue_entry);
++ if (ep->dwc_ep.is_in && ep->stopped
++ && !(GET_CORE_IF(pcd)->dma_enable)) {
++ /** @todo NGS Create a function for this. */
++ diepmsk_data_t diepmsk = {.d32 = 0 };
++ diepmsk.b.intktxfemp = 1;
++ if (GET_CORE_IF(pcd)->multiproc_int_enable) {
++ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->
++ dev_if->dev_global_regs->diepeachintmsk
++ [ep->dwc_ep.num], 0,
++ diepmsk.d32);
++ } else {
++ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->
++ dev_if->dev_global_regs->
++ diepmsk, 0, diepmsk.d32);
++ }
++
++ }
++ }
++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
++
++ return 0;
++}
++
++int dwc_otg_pcd_ep_dequeue(dwc_otg_pcd_t * pcd, void *ep_handle,
++ void *req_handle)
++{
++ dwc_irqflags_t flags;
++ dwc_otg_pcd_request_t *req;
++ dwc_otg_pcd_ep_t *ep;
++
++ ep = get_ep_from_handle(pcd, ep_handle);
++ if (!ep || (!ep->desc && ep->dwc_ep.num != 0)) {
++ DWC_WARN("bad argument\n");
++ return -DWC_E_INVALID;
++ }
++
++ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
++
++ /* make sure it's actually queued on this endpoint */
++ DWC_CIRCLEQ_FOREACH(req, &ep->queue, queue_entry) {
++ if (req->priv == (void *)req_handle) {
++ break;
++ }
++ }
++
++ if (req->priv != (void *)req_handle) {
++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
++ return -DWC_E_INVALID;
++ }
++
++ if (!DWC_CIRCLEQ_EMPTY_ENTRY(req, queue_entry)) {
++ dwc_otg_request_done(ep, req, -DWC_E_RESTART);
++ } else {
++ req = NULL;
++ }
++
++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
++
++ return req ? 0 : -DWC_E_SHUTDOWN;
++
++}
++
++/**
++ * dwc_otg_pcd_ep_wedge - sets the halt feature and ignores clear requests
++ *
++ * Use this to stall an endpoint and ignore CLEAR_FEATURE(HALT_ENDPOINT)
++ * requests. If the gadget driver clears the halt status, it will
++ * automatically unwedge the endpoint.
++ *
++ * Returns zero on success, else negative DWC error code.
++ */
++int dwc_otg_pcd_ep_wedge(dwc_otg_pcd_t * pcd, void *ep_handle)
++{
++ dwc_otg_pcd_ep_t *ep;
++ dwc_irqflags_t flags;
++ int retval = 0;
++
++ ep = get_ep_from_handle(pcd, ep_handle);
++
++ if ((!ep->desc && ep != &pcd->ep0) ||
++ (ep->desc && (ep->desc->bmAttributes == UE_ISOCHRONOUS))) {
++ DWC_WARN("%s, bad ep\n", __func__);
++ return -DWC_E_INVALID;
++ }
++
++ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
++ if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
++ DWC_WARN("%d %s XFer In process\n", ep->dwc_ep.num,
++ ep->dwc_ep.is_in ? "IN" : "OUT");
++ retval = -DWC_E_AGAIN;
++ } else {
++ /* This code needs to be reviewed */
++ if (ep->dwc_ep.is_in == 1 && GET_CORE_IF(pcd)->dma_desc_enable) {
++ dtxfsts_data_t txstatus;
++ fifosize_data_t txfifosize;
++
++ txfifosize.d32 =
++ DWC_READ_REG32(&GET_CORE_IF(pcd)->
++ core_global_regs->dtxfsiz[ep->dwc_ep.
++ tx_fifo_num]);
++ txstatus.d32 =
++ DWC_READ_REG32(&GET_CORE_IF(pcd)->
++ dev_if->in_ep_regs[ep->dwc_ep.num]->
++ dtxfsts);
++
++ if (txstatus.b.txfspcavail < txfifosize.b.depth) {
++ DWC_WARN("%s() Data In Tx Fifo\n", __func__);
++ retval = -DWC_E_AGAIN;
++ } else {
++ if (ep->dwc_ep.num == 0) {
++ pcd->ep0state = EP0_STALL;
++ }
++
++ ep->stopped = 1;
++ dwc_otg_ep_set_stall(GET_CORE_IF(pcd),
++ &ep->dwc_ep);
++ }
++ } else {
++ if (ep->dwc_ep.num == 0) {
++ pcd->ep0state = EP0_STALL;
++ }
++
++ ep->stopped = 1;
++ dwc_otg_ep_set_stall(GET_CORE_IF(pcd), &ep->dwc_ep);
++ }
++ }
++
++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
++
++ return retval;
++}
++
++int dwc_otg_pcd_ep_halt(dwc_otg_pcd_t * pcd, void *ep_handle, int value)
++{
++ dwc_otg_pcd_ep_t *ep;
++ dwc_irqflags_t flags;
++ int retval = 0;
++
++ ep = get_ep_from_handle(pcd, ep_handle);
++
++ if (!ep || (!ep->desc && ep != &pcd->ep0) ||
++ (ep->desc && (ep->desc->bmAttributes == UE_ISOCHRONOUS))) {
++ DWC_WARN("%s, bad ep\n", __func__);
++ return -DWC_E_INVALID;
++ }
++
++ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
++ if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
++ DWC_WARN("%d %s XFer In process\n", ep->dwc_ep.num,
++ ep->dwc_ep.is_in ? "IN" : "OUT");
++ retval = -DWC_E_AGAIN;
++ } else if (value == 0) {
++ dwc_otg_ep_clear_stall(GET_CORE_IF(pcd), &ep->dwc_ep);
++ } else if (value == 1) {
++ if (ep->dwc_ep.is_in == 1 && GET_CORE_IF(pcd)->dma_desc_enable) {
++ dtxfsts_data_t txstatus;
++ fifosize_data_t txfifosize;
++
++ txfifosize.d32 =
++ DWC_READ_REG32(&GET_CORE_IF(pcd)->core_global_regs->
++ dtxfsiz[ep->dwc_ep.tx_fifo_num]);
++ txstatus.d32 =
++ DWC_READ_REG32(&GET_CORE_IF(pcd)->dev_if->
++ in_ep_regs[ep->dwc_ep.num]->dtxfsts);
++
++ if (txstatus.b.txfspcavail < txfifosize.b.depth) {
++ DWC_WARN("%s() Data In Tx Fifo\n", __func__);
++ retval = -DWC_E_AGAIN;
++ } else {
++ if (ep->dwc_ep.num == 0) {
++ pcd->ep0state = EP0_STALL;
++ }
++
++ ep->stopped = 1;
++ dwc_otg_ep_set_stall(GET_CORE_IF(pcd),
++ &ep->dwc_ep);
++ }
++ } else {
++ if (ep->dwc_ep.num == 0) {
++ pcd->ep0state = EP0_STALL;
++ }
++
++ ep->stopped = 1;
++ dwc_otg_ep_set_stall(GET_CORE_IF(pcd), &ep->dwc_ep);
++ }
++ } else if (value == 2) {
++ ep->dwc_ep.stall_clear_flag = 0;
++ } else if (value == 3) {
++ ep->dwc_ep.stall_clear_flag = 1;
++ }
++
++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
++
++ return retval;
++}
++
++/**
++ * This function initiates remote wakeup of the host from suspend state.
++ */
++void dwc_otg_pcd_rem_wkup_from_suspend(dwc_otg_pcd_t * pcd, int set)
++{
++ dctl_data_t dctl = { 0 };
++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++ dsts_data_t dsts;
++
++ dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
++ if (!dsts.b.suspsts) {
++ DWC_WARN("Remote wakeup while is not in suspend state\n");
++ }
++ /* Check if DEVICE_REMOTE_WAKEUP feature enabled */
++ if (pcd->remote_wakeup_enable) {
++ if (set) {
++
++ if (core_if->adp_enable) {
++ gpwrdn_data_t gpwrdn;
++
++ dwc_otg_adp_probe_stop(core_if);
++
++ /* Mask SRP detected interrupt from Power Down Logic */
++ gpwrdn.d32 = 0;
++ gpwrdn.b.srp_det_msk = 1;
++ DWC_MODIFY_REG32(&core_if->
++ core_global_regs->gpwrdn,
++ gpwrdn.d32, 0);
++
++ /* Disable Power Down Logic */
++ gpwrdn.d32 = 0;
++ gpwrdn.b.pmuactv = 1;
++ DWC_MODIFY_REG32(&core_if->
++ core_global_regs->gpwrdn,
++ gpwrdn.d32, 0);
++
++ /*
++ * Initialize the Core for Device mode.
++ */
++ core_if->op_state = B_PERIPHERAL;
++ dwc_otg_core_init(core_if);
++ dwc_otg_enable_global_interrupts(core_if);
++ cil_pcd_start(core_if);
++
++ dwc_otg_initiate_srp(core_if);
++ }
++
++ dctl.b.rmtwkupsig = 1;
++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
++ dctl, 0, dctl.d32);
++ DWC_DEBUGPL(DBG_PCD, "Set Remote Wakeup\n");
++
++ dwc_mdelay(2);
++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
++ dctl, dctl.d32, 0);
++ DWC_DEBUGPL(DBG_PCD, "Clear Remote Wakeup\n");
++ }
++ } else {
++ DWC_DEBUGPL(DBG_PCD, "Remote Wakeup is disabled\n");
++ }
++}
++
++#ifdef CONFIG_USB_DWC_OTG_LPM
++/**
++ * This function initiates remote wakeup of the host from L1 sleep state.
++ */
++void dwc_otg_pcd_rem_wkup_from_sleep(dwc_otg_pcd_t * pcd, int set)
++{
++ glpmcfg_data_t lpmcfg;
++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++
++ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
++
++ /* Check if we are in L1 state */
++ if (!lpmcfg.b.prt_sleep_sts) {
++ DWC_DEBUGPL(DBG_PCD, "Device is not in sleep state\n");
++ return;
++ }
++
++ /* Check if host allows remote wakeup */
++ if (!lpmcfg.b.rem_wkup_en) {
++ DWC_DEBUGPL(DBG_PCD, "Host does not allow remote wakeup\n");
++ return;
++ }
++
++ /* Check if Resume OK */
++ if (!lpmcfg.b.sleep_state_resumeok) {
++ DWC_DEBUGPL(DBG_PCD, "Sleep state resume is not OK\n");
++ return;
++ }
++
++ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
++ lpmcfg.b.en_utmi_sleep = 0;
++ lpmcfg.b.hird_thres &= (~(1 << 4));
++ DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
++
++ if (set) {
++ dctl_data_t dctl = {.d32 = 0 };
++ dctl.b.rmtwkupsig = 1;
++ /* Set RmtWkUpSig bit to start remote wakup signaling.
++ * Hardware will automatically clear this bit.
++ */
++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl,
++ 0, dctl.d32);
++ DWC_DEBUGPL(DBG_PCD, "Set Remote Wakeup\n");
++ }
++
++}
++#endif
++
++/**
++ * Performs remote wakeup.
++ */
++void dwc_otg_pcd_remote_wakeup(dwc_otg_pcd_t * pcd, int set)
++{
++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++ dwc_irqflags_t flags;
++ if (dwc_otg_is_device_mode(core_if)) {
++ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
++#ifdef CONFIG_USB_DWC_OTG_LPM
++ if (core_if->lx_state == DWC_OTG_L1) {
++ dwc_otg_pcd_rem_wkup_from_sleep(pcd, set);
++ } else {
++#endif
++ dwc_otg_pcd_rem_wkup_from_suspend(pcd, set);
++#ifdef CONFIG_USB_DWC_OTG_LPM
++ }
++#endif
++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
++ }
++ return;
++}
++
++void dwc_otg_pcd_disconnect_us(dwc_otg_pcd_t * pcd, int no_of_usecs)
++{
++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++ dctl_data_t dctl = { 0 };
++
++ if (dwc_otg_is_device_mode(core_if)) {
++ dctl.b.sftdiscon = 1;
++ DWC_PRINTF("Soft disconnect for %d useconds\n",no_of_usecs);
++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
++ dwc_udelay(no_of_usecs);
++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32,0);
++
++ } else{
++ DWC_PRINTF("NOT SUPPORTED IN HOST MODE\n");
++ }
++ return;
++
++}
++
++int dwc_otg_pcd_wakeup(dwc_otg_pcd_t * pcd)
++{
++ dsts_data_t dsts;
++ gotgctl_data_t gotgctl;
++
++ /*
++ * This function starts the Protocol if no session is in progress. If
++ * a session is already in progress, but the device is suspended,
++ * remote wakeup signaling is started.
++ */
++
++ /* Check if valid session */
++ gotgctl.d32 =
++ DWC_READ_REG32(&(GET_CORE_IF(pcd)->core_global_regs->gotgctl));
++ if (gotgctl.b.bsesvld) {
++ /* Check if suspend state */
++ dsts.d32 =
++ DWC_READ_REG32(&
++ (GET_CORE_IF(pcd)->dev_if->
++ dev_global_regs->dsts));
++ if (dsts.b.suspsts) {
++ dwc_otg_pcd_remote_wakeup(pcd, 1);
++ }
++ } else {
++ dwc_otg_pcd_initiate_srp(pcd);
++ }
++
++ return 0;
++
++}
++
++/**
++ * Start the SRP timer to detect when the SRP does not complete within
++ * 6 seconds.
++ *
++ * @param pcd the pcd structure.
++ */
++void dwc_otg_pcd_initiate_srp(dwc_otg_pcd_t * pcd)
++{
++ dwc_irqflags_t flags;
++ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
++ dwc_otg_initiate_srp(GET_CORE_IF(pcd));
++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
++}
++
++int dwc_otg_pcd_get_frame_number(dwc_otg_pcd_t * pcd)
++{
++ return dwc_otg_get_frame_number(GET_CORE_IF(pcd));
++}
++
++int dwc_otg_pcd_is_lpm_enabled(dwc_otg_pcd_t * pcd)
++{
++ return GET_CORE_IF(pcd)->core_params->lpm_enable;
++}
++
++uint32_t get_b_hnp_enable(dwc_otg_pcd_t * pcd)
++{
++ return pcd->b_hnp_enable;
++}
++
++uint32_t get_a_hnp_support(dwc_otg_pcd_t * pcd)
++{
++ return pcd->a_hnp_support;
++}
++
++uint32_t get_a_alt_hnp_support(dwc_otg_pcd_t * pcd)
++{
++ return pcd->a_alt_hnp_support;
++}
++
++int dwc_otg_pcd_get_rmwkup_enable(dwc_otg_pcd_t * pcd)
++{
++ return pcd->remote_wakeup_enable;
++}
++
++#endif /* DWC_HOST_ONLY */
+diff -Nur linux-4.1.3/drivers/usb/host/dwc_otg/dwc_otg_pcd.h linux-xbian-rpi/drivers/usb/host/dwc_otg/dwc_otg_pcd.h
+--- linux-4.1.3/drivers/usb/host/dwc_otg/dwc_otg_pcd.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/usb/host/dwc_otg/dwc_otg_pcd.h 2015-07-28 01:20:58.449142252 +0200
+@@ -0,0 +1,266 @@
++/* ==========================================================================
++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd.h $
++ * $Revision: #48 $
++ * $Date: 2012/08/10 $
++ * $Change: 2047372 $
++ *
++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++ * otherwise expressly agreed to in writing between Synopsys and you.
++ *
++ * The Software IS NOT an item of Licensed Software or Licensed Product under
++ * any End User Software License Agreement or Agreement for Licensed Product
++ * with Synopsys or any supplement thereto. You are permitted to use and
++ * redistribute this Software in source and binary forms, with or without
++ * modification, provided that redistributions of source code must retain this
++ * notice. You may not view, use, disclose, copy or distribute this file or
++ * any information contained herein except pursuant to this license grant from
++ * Synopsys. If you do not agree with this notice, including the disclaimer
++ * below, then you are not authorized to use the Software.
++ *
++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++ * DAMAGE.
++ * ========================================================================== */
++#ifndef DWC_HOST_ONLY
++#if !defined(__DWC_PCD_H__)
++#define __DWC_PCD_H__
++
++#include "dwc_otg_os_dep.h"
++#include "usb.h"
++#include "dwc_otg_cil.h"
++#include "dwc_otg_pcd_if.h"
++struct cfiobject;
++
++/**
++ * @file
++ *
++ * This file contains the structures, constants, and interfaces for
++ * the Perpherial Contoller Driver (PCD).
++ *
++ * The Peripheral Controller Driver (PCD) for Linux will implement the
++ * Gadget API, so that the existing Gadget drivers can be used. For
++ * the Mass Storage Function driver the File-backed USB Storage Gadget
++ * (FBS) driver will be used. The FBS driver supports the
++ * Control-Bulk (CB), Control-Bulk-Interrupt (CBI), and Bulk-Only
++ * transports.
++ *
++ */
++
++/** Invalid DMA Address */
++#define DWC_DMA_ADDR_INVALID (~(dwc_dma_t)0)
++
++/** Max Transfer size for any EP */
++#define DDMA_MAX_TRANSFER_SIZE 65535
++
++/**
++ * Get the pointer to the core_if from the pcd pointer.
++ */
++#define GET_CORE_IF( _pcd ) (_pcd->core_if)
++
++/**
++ * States of EP0.
++ */
++typedef enum ep0_state {
++ EP0_DISCONNECT, /* no host */
++ EP0_IDLE,
++ EP0_IN_DATA_PHASE,
++ EP0_OUT_DATA_PHASE,
++ EP0_IN_STATUS_PHASE,
++ EP0_OUT_STATUS_PHASE,
++ EP0_STALL,
++} ep0state_e;
++
++/** Fordward declaration.*/
++struct dwc_otg_pcd;
++
++/** DWC_otg iso request structure.
++ *
++ */
++typedef struct usb_iso_request dwc_otg_pcd_iso_request_t;
++
++#ifdef DWC_UTE_PER_IO
++
++/**
++ * This shall be the exact analogy of the same type structure defined in the
++ * usb_gadget.h. Each descriptor contains
++ */
++struct dwc_iso_pkt_desc_port {
++ uint32_t offset;
++ uint32_t length; /* expected length */
++ uint32_t actual_length;
++ uint32_t status;
++};
++
++struct dwc_iso_xreq_port {
++ /** transfer/submission flag */
++ uint32_t tr_sub_flags;
++ /** Start the request ASAP */
++#define DWC_EREQ_TF_ASAP 0x00000002
++ /** Just enqueue the request w/o initiating a transfer */
++#define DWC_EREQ_TF_ENQUEUE 0x00000004
++
++ /**
++ * count of ISO packets attached to this request - shall
++ * not exceed the pio_alloc_pkt_count
++ */
++ uint32_t pio_pkt_count;
++ /** count of ISO packets allocated for this request */
++ uint32_t pio_alloc_pkt_count;
++ /** number of ISO packet errors */
++ uint32_t error_count;
++ /** reserved for future extension */
++ uint32_t res;
++ /** Will be allocated and freed in the UTE gadget and based on the CFC value */
++ struct dwc_iso_pkt_desc_port *per_io_frame_descs;
++};
++#endif
++/** DWC_otg request structure.
++ * This structure is a list of requests.
++ */
++typedef struct dwc_otg_pcd_request {
++ void *priv;
++ void *buf;
++ dwc_dma_t dma;
++ uint32_t length;
++ uint32_t actual;
++ unsigned sent_zlp:1;
++ /**
++ * Used instead of original buffer if
++ * it(physical address) is not dword-aligned.
++ **/
++ uint8_t *dw_align_buf;
++ dwc_dma_t dw_align_buf_dma;
++
++ DWC_CIRCLEQ_ENTRY(dwc_otg_pcd_request) queue_entry;
++#ifdef DWC_UTE_PER_IO
++ struct dwc_iso_xreq_port ext_req;
++ //void *priv_ereq_nport; /* */
++#endif
++} dwc_otg_pcd_request_t;
++
++DWC_CIRCLEQ_HEAD(req_list, dwc_otg_pcd_request);
++
++/** PCD EP structure.
++ * This structure describes an EP, there is an array of EPs in the PCD
++ * structure.
++ */
++typedef struct dwc_otg_pcd_ep {
++ /** USB EP Descriptor */
++ const usb_endpoint_descriptor_t *desc;
++
++ /** queue of dwc_otg_pcd_requests. */
++ struct req_list queue;
++ unsigned stopped:1;
++ unsigned disabling:1;
++ unsigned dma:1;
++ unsigned queue_sof:1;
++
++#ifdef DWC_EN_ISOC
++ /** ISOC req handle passed */
++ void *iso_req_handle;
++#endif //_EN_ISOC_
++
++ /** DWC_otg ep data. */
++ dwc_ep_t dwc_ep;
++
++ /** Pointer to PCD */
++ struct dwc_otg_pcd *pcd;
++
++ void *priv;
++} dwc_otg_pcd_ep_t;
++
++/** DWC_otg PCD Structure.
++ * This structure encapsulates the data for the dwc_otg PCD.
++ */
++struct dwc_otg_pcd {
++ const struct dwc_otg_pcd_function_ops *fops;
++ /** The DWC otg device pointer */
++ struct dwc_otg_device *otg_dev;
++ /** Core Interface */
++ dwc_otg_core_if_t *core_if;
++ /** State of EP0 */
++ ep0state_e ep0state;
++ /** EP0 Request is pending */
++ unsigned ep0_pending:1;
++ /** Indicates when SET CONFIGURATION Request is in process */
++ unsigned request_config:1;
++ /** The state of the Remote Wakeup Enable. */
++ unsigned remote_wakeup_enable:1;
++ /** The state of the B-Device HNP Enable. */
++ unsigned b_hnp_enable:1;
++ /** The state of A-Device HNP Support. */
++ unsigned a_hnp_support:1;
++ /** The state of the A-Device Alt HNP support. */
++ unsigned a_alt_hnp_support:1;
++ /** Count of pending Requests */
++ unsigned request_pending;
++
++ /** SETUP packet for EP0
++ * This structure is allocated as a DMA buffer on PCD initialization
++ * with enough space for up to 3 setup packets.
++ */
++ union {
++ usb_device_request_t req;
++ uint32_t d32[2];
++ } *setup_pkt;
++
++ dwc_dma_t setup_pkt_dma_handle;
++
++ /* Additional buffer and flag for CTRL_WR premature case */
++ uint8_t *backup_buf;
++ unsigned data_terminated;
++
++ /** 2-byte dma buffer used to return status from GET_STATUS */
++ uint16_t *status_buf;
++ dwc_dma_t status_buf_dma_handle;
++
++ /** EP0 */
++ dwc_otg_pcd_ep_t ep0;
++
++ /** Array of IN EPs. */
++ dwc_otg_pcd_ep_t in_ep[MAX_EPS_CHANNELS - 1];
++ /** Array of OUT EPs. */
++ dwc_otg_pcd_ep_t out_ep[MAX_EPS_CHANNELS - 1];
++ /** number of valid EPs in the above array. */
++// unsigned num_eps : 4;
++ dwc_spinlock_t *lock;
++
++ /** Tasklet to defer starting of TEST mode transmissions until
++ * Status Phase has been completed.
++ */
++ dwc_tasklet_t *test_mode_tasklet;
++
++ /** Tasklet to delay starting of xfer in DMA mode */
++ dwc_tasklet_t *start_xfer_tasklet;
++
++ /** The test mode to enter when the tasklet is executed. */
++ unsigned test_mode;
++ /** The cfi_api structure that implements most of the CFI API
++ * and OTG specific core configuration functionality
++ */
++#ifdef DWC_UTE_CFI
++ struct cfiobject *cfi;
++#endif
++
++};
++
++//FIXME this functions should be static, and this prototypes should be removed
++extern void dwc_otg_request_nuke(dwc_otg_pcd_ep_t * ep);
++extern void dwc_otg_request_done(dwc_otg_pcd_ep_t * ep,
++ dwc_otg_pcd_request_t * req, int32_t status);
++
++void dwc_otg_iso_buffer_done(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep,
++ void *req_handle);
++
++extern void do_test_mode(void *data);
++#endif
++#endif /* DWC_HOST_ONLY */
+diff -Nur linux-4.1.3/drivers/usb/host/dwc_otg/dwc_otg_pcd_if.h linux-xbian-rpi/drivers/usb/host/dwc_otg/dwc_otg_pcd_if.h
+--- linux-4.1.3/drivers/usb/host/dwc_otg/dwc_otg_pcd_if.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/usb/host/dwc_otg/dwc_otg_pcd_if.h 2015-07-28 01:20:58.449142252 +0200
+@@ -0,0 +1,360 @@
++/* ==========================================================================
++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_if.h $
++ * $Revision: #11 $
++ * $Date: 2011/10/26 $
++ * $Change: 1873028 $
++ *
++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++ * otherwise expressly agreed to in writing between Synopsys and you.
++ *
++ * The Software IS NOT an item of Licensed Software or Licensed Product under
++ * any End User Software License Agreement or Agreement for Licensed Product
++ * with Synopsys or any supplement thereto. You are permitted to use and
++ * redistribute this Software in source and binary forms, with or without
++ * modification, provided that redistributions of source code must retain this
++ * notice. You may not view, use, disclose, copy or distribute this file or
++ * any information contained herein except pursuant to this license grant from
++ * Synopsys. If you do not agree with this notice, including the disclaimer
++ * below, then you are not authorized to use the Software.
++ *
++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++ * DAMAGE.
++ * ========================================================================== */
++#ifndef DWC_HOST_ONLY
++
++#if !defined(__DWC_PCD_IF_H__)
++#define __DWC_PCD_IF_H__
++
++//#include "dwc_os.h"
++#include "dwc_otg_core_if.h"
++
++/** @file
++ * This file defines DWC_OTG PCD Core API.
++ */
++
++struct dwc_otg_pcd;
++typedef struct dwc_otg_pcd dwc_otg_pcd_t;
++
++/** Maxpacket size for EP0 */
++#define MAX_EP0_SIZE 64
++/** Maxpacket size for any EP */
++#define MAX_PACKET_SIZE 1024
++
++/** @name Function Driver Callbacks */
++/** @{ */
++
++/** This function will be called whenever a previously queued request has
++ * completed. The status value will be set to -DWC_E_SHUTDOWN to indicated a
++ * failed or aborted transfer, or -DWC_E_RESTART to indicate the device was reset,
++ * or -DWC_E_TIMEOUT to indicate it timed out, or -DWC_E_INVALID to indicate invalid
++ * parameters. */
++typedef int (*dwc_completion_cb_t) (dwc_otg_pcd_t * pcd, void *ep_handle,
++ void *req_handle, int32_t status,
++ uint32_t actual);
++/**
++ * This function will be called whenever a previousle queued ISOC request has
++ * completed. Count of ISOC packets could be read using dwc_otg_pcd_get_iso_packet_count
++ * function.
++ * The status of each ISOC packet could be read using dwc_otg_pcd_get_iso_packet_*
++ * functions.
++ */
++typedef int (*dwc_isoc_completion_cb_t) (dwc_otg_pcd_t * pcd, void *ep_handle,
++ void *req_handle, int proc_buf_num);
++/** This function should handle any SETUP request that cannot be handled by the
++ * PCD Core. This includes most GET_DESCRIPTORs, SET_CONFIGS, Any
++ * class-specific requests, etc. The function must non-blocking.
++ *
++ * Returns 0 on success.
++ * Returns -DWC_E_NOT_SUPPORTED if the request is not supported.
++ * Returns -DWC_E_INVALID if the setup request had invalid parameters or bytes.
++ * Returns -DWC_E_SHUTDOWN on any other error. */
++typedef int (*dwc_setup_cb_t) (dwc_otg_pcd_t * pcd, uint8_t * bytes);
++/** This is called whenever the device has been disconnected. The function
++ * driver should take appropriate action to clean up all pending requests in the
++ * PCD Core, remove all endpoints (except ep0), and initialize back to reset
++ * state. */
++typedef int (*dwc_disconnect_cb_t) (dwc_otg_pcd_t * pcd);
++/** This function is called when device has been connected. */
++typedef int (*dwc_connect_cb_t) (dwc_otg_pcd_t * pcd, int speed);
++/** This function is called when device has been suspended */
++typedef int (*dwc_suspend_cb_t) (dwc_otg_pcd_t * pcd);
++/** This function is called when device has received LPM tokens, i.e.
++ * device has been sent to sleep state. */
++typedef int (*dwc_sleep_cb_t) (dwc_otg_pcd_t * pcd);
++/** This function is called when device has been resumed
++ * from suspend(L2) or L1 sleep state. */
++typedef int (*dwc_resume_cb_t) (dwc_otg_pcd_t * pcd);
++/** This function is called whenever hnp params has been changed.
++ * User can call get_b_hnp_enable, get_a_hnp_support, get_a_alt_hnp_support functions
++ * to get hnp parameters. */
++typedef int (*dwc_hnp_params_changed_cb_t) (dwc_otg_pcd_t * pcd);
++/** This function is called whenever USB RESET is detected. */
++typedef int (*dwc_reset_cb_t) (dwc_otg_pcd_t * pcd);
++
++typedef int (*cfi_setup_cb_t) (dwc_otg_pcd_t * pcd, void *ctrl_req_bytes);
++
++/**
++ *
++ * @param ep_handle Void pointer to the usb_ep structure
++ * @param ereq_port Pointer to the extended request structure created in the
++ * portable part.
++ */
++typedef int (*xiso_completion_cb_t) (dwc_otg_pcd_t * pcd, void *ep_handle,
++ void *req_handle, int32_t status,
++ void *ereq_port);
++/** Function Driver Ops Data Structure */
++struct dwc_otg_pcd_function_ops {
++ dwc_connect_cb_t connect;
++ dwc_disconnect_cb_t disconnect;
++ dwc_setup_cb_t setup;
++ dwc_completion_cb_t complete;
++ dwc_isoc_completion_cb_t isoc_complete;
++ dwc_suspend_cb_t suspend;
++ dwc_sleep_cb_t sleep;
++ dwc_resume_cb_t resume;
++ dwc_reset_cb_t reset;
++ dwc_hnp_params_changed_cb_t hnp_changed;
++ cfi_setup_cb_t cfi_setup;
++#ifdef DWC_UTE_PER_IO
++ xiso_completion_cb_t xisoc_complete;
++#endif
++};
++/** @} */
++
++/** @name Function Driver Functions */
++/** @{ */
++
++/** Call this function to get pointer on dwc_otg_pcd_t,
++ * this pointer will be used for all PCD API functions.
++ *
++ * @param core_if The DWC_OTG Core
++ */
++extern dwc_otg_pcd_t *dwc_otg_pcd_init(dwc_otg_core_if_t * core_if);
++
++/** Frees PCD allocated by dwc_otg_pcd_init
++ *
++ * @param pcd The PCD
++ */
++extern void dwc_otg_pcd_remove(dwc_otg_pcd_t * pcd);
++
++/** Call this to bind the function driver to the PCD Core.
++ *
++ * @param pcd Pointer on dwc_otg_pcd_t returned by dwc_otg_pcd_init function.
++ * @param fops The Function Driver Ops data structure containing pointers to all callbacks.
++ */
++extern void dwc_otg_pcd_start(dwc_otg_pcd_t * pcd,
++ const struct dwc_otg_pcd_function_ops *fops);
++
++/** Enables an endpoint for use. This function enables an endpoint in
++ * the PCD. The endpoint is described by the ep_desc which has the
++ * same format as a USB ep descriptor. The ep_handle parameter is used to refer
++ * to the endpoint from other API functions and in callbacks. Normally this
++ * should be called after a SET_CONFIGURATION/SET_INTERFACE to configure the
++ * core for that interface.
++ *
++ * Returns -DWC_E_INVALID if invalid parameters were passed.
++ * Returns -DWC_E_SHUTDOWN if any other error ocurred.
++ * Returns 0 on success.
++ *
++ * @param pcd The PCD
++ * @param ep_desc Endpoint descriptor
++ * @param usb_ep Handle on endpoint, that will be used to identify endpoint.
++ */
++extern int dwc_otg_pcd_ep_enable(dwc_otg_pcd_t * pcd,
++ const uint8_t * ep_desc, void *usb_ep);
++
++/** Disable the endpoint referenced by ep_handle.
++ *
++ * Returns -DWC_E_INVALID if invalid parameters were passed.
++ * Returns -DWC_E_SHUTDOWN if any other error occurred.
++ * Returns 0 on success. */
++extern int dwc_otg_pcd_ep_disable(dwc_otg_pcd_t * pcd, void *ep_handle);
++
++/** Queue a data transfer request on the endpoint referenced by ep_handle.
++ * After the transfer is completes, the complete callback will be called with
++ * the request status.
++ *
++ * @param pcd The PCD
++ * @param ep_handle The handle of the endpoint
++ * @param buf The buffer for the data
++ * @param dma_buf The DMA buffer for the data
++ * @param buflen The length of the data transfer
++ * @param zero Specifies whether to send zero length last packet.
++ * @param req_handle Set this handle to any value to use to reference this
++ * request in the ep_dequeue function or from the complete callback
++ * @param atomic_alloc If driver need to perform atomic allocations
++ * for internal data structures.
++ *
++ * Returns -DWC_E_INVALID if invalid parameters were passed.
++ * Returns -DWC_E_SHUTDOWN if any other error ocurred.
++ * Returns 0 on success. */
++extern int dwc_otg_pcd_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle,
++ uint8_t * buf, dwc_dma_t dma_buf,
++ uint32_t buflen, int zero, void *req_handle,
++ int atomic_alloc);
++#ifdef DWC_UTE_PER_IO
++/**
++ *
++ * @param ereq_nonport Pointer to the extended request part of the
++ * usb_request structure defined in usb_gadget.h file.
++ */
++extern int dwc_otg_pcd_xiso_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle,
++ uint8_t * buf, dwc_dma_t dma_buf,
++ uint32_t buflen, int zero,
++ void *req_handle, int atomic_alloc,
++ void *ereq_nonport);
++
++#endif
++
++/** De-queue the specified data transfer that has not yet completed.
++ *
++ * Returns -DWC_E_INVALID if invalid parameters were passed.
++ * Returns -DWC_E_SHUTDOWN if any other error ocurred.
++ * Returns 0 on success. */
++extern int dwc_otg_pcd_ep_dequeue(dwc_otg_pcd_t * pcd, void *ep_handle,
++ void *req_handle);
++
++/** Halt (STALL) an endpoint or clear it.
++ *
++ * Returns -DWC_E_INVALID if invalid parameters were passed.
++ * Returns -DWC_E_SHUTDOWN if any other error ocurred.
++ * Returns -DWC_E_AGAIN if the STALL cannot be sent and must be tried again later
++ * Returns 0 on success. */
++extern int dwc_otg_pcd_ep_halt(dwc_otg_pcd_t * pcd, void *ep_handle, int value);
++
++/** This function */
++extern int dwc_otg_pcd_ep_wedge(dwc_otg_pcd_t * pcd, void *ep_handle);
++
++/** This function should be called on every hardware interrupt */
++extern int32_t dwc_otg_pcd_handle_intr(dwc_otg_pcd_t * pcd);
++
++/** This function returns current frame number */
++extern int dwc_otg_pcd_get_frame_number(dwc_otg_pcd_t * pcd);
++
++/**
++ * Start isochronous transfers on the endpoint referenced by ep_handle.
++ * For isochronous transfers duble buffering is used.
++ * After processing each of buffers comlete callback will be called with
++ * status for each transaction.
++ *
++ * @param pcd The PCD
++ * @param ep_handle The handle of the endpoint
++ * @param buf0 The virtual address of first data buffer
++ * @param buf1 The virtual address of second data buffer
++ * @param dma0 The DMA address of first data buffer
++ * @param dma1 The DMA address of second data buffer
++ * @param sync_frame Data pattern frame number
++ * @param dp_frame Data size for pattern frame
++ * @param data_per_frame Data size for regular frame
++ * @param start_frame Frame number to start transfers, if -1 then start transfers ASAP.
++ * @param buf_proc_intrvl Interval of ISOC Buffer processing
++ * @param req_handle Handle of ISOC request
++ * @param atomic_alloc Specefies whether to perform atomic allocation for
++ * internal data structures.
++ *
++ * Returns -DWC_E_NO_MEMORY if there is no enough memory.
++ * Returns -DWC_E_INVALID if incorrect arguments are passed to the function.
++ * Returns -DW_E_SHUTDOWN for any other error.
++ * Returns 0 on success
++ */
++extern int dwc_otg_pcd_iso_ep_start(dwc_otg_pcd_t * pcd, void *ep_handle,
++ uint8_t * buf0, uint8_t * buf1,
++ dwc_dma_t dma0, dwc_dma_t dma1,
++ int sync_frame, int dp_frame,
++ int data_per_frame, int start_frame,
++ int buf_proc_intrvl, void *req_handle,
++ int atomic_alloc);
++
++/** Stop ISOC transfers on endpoint referenced by ep_handle.
++ *
++ * @param pcd The PCD
++ * @param ep_handle The handle of the endpoint
++ * @param req_handle Handle of ISOC request
++ *
++ * Returns -DWC_E_INVALID if incorrect arguments are passed to the function
++ * Returns 0 on success
++ */
++int dwc_otg_pcd_iso_ep_stop(dwc_otg_pcd_t * pcd, void *ep_handle,
++ void *req_handle);
++
++/** Get ISOC packet status.
++ *
++ * @param pcd The PCD
++ * @param ep_handle The handle of the endpoint
++ * @param iso_req_handle Isochronoush request handle
++ * @param packet Number of packet
++ * @param status Out parameter for returning status
++ * @param actual Out parameter for returning actual length
++ * @param offset Out parameter for returning offset
++ *
++ */
++extern void dwc_otg_pcd_get_iso_packet_params(dwc_otg_pcd_t * pcd,
++ void *ep_handle,
++ void *iso_req_handle, int packet,
++ int *status, int *actual,
++ int *offset);
++
++/** Get ISOC packet count.
++ *
++ * @param pcd The PCD
++ * @param ep_handle The handle of the endpoint
++ * @param iso_req_handle
++ */
++extern int dwc_otg_pcd_get_iso_packet_count(dwc_otg_pcd_t * pcd,
++ void *ep_handle,
++ void *iso_req_handle);
++
++/** This function starts the SRP Protocol if no session is in progress. If
++ * a session is already in progress, but the device is suspended,
++ * remote wakeup signaling is started.
++ */
++extern int dwc_otg_pcd_wakeup(dwc_otg_pcd_t * pcd);
++
++/** This function returns 1 if LPM support is enabled, and 0 otherwise. */
++extern int dwc_otg_pcd_is_lpm_enabled(dwc_otg_pcd_t * pcd);
++
++/** This function returns 1 if remote wakeup is allowed and 0, otherwise. */
++extern int dwc_otg_pcd_get_rmwkup_enable(dwc_otg_pcd_t * pcd);
++
++/** Initiate SRP */
++extern void dwc_otg_pcd_initiate_srp(dwc_otg_pcd_t * pcd);
++
++/** Starts remote wakeup signaling. */
++extern void dwc_otg_pcd_remote_wakeup(dwc_otg_pcd_t * pcd, int set);
++
++/** Starts micorsecond soft disconnect. */
++extern void dwc_otg_pcd_disconnect_us(dwc_otg_pcd_t * pcd, int no_of_usecs);
++/** This function returns whether device is dualspeed.*/
++extern uint32_t dwc_otg_pcd_is_dualspeed(dwc_otg_pcd_t * pcd);
++
++/** This function returns whether device is otg. */
++extern uint32_t dwc_otg_pcd_is_otg(dwc_otg_pcd_t * pcd);
++
++/** These functions allow to get hnp parameters */
++extern uint32_t get_b_hnp_enable(dwc_otg_pcd_t * pcd);
++extern uint32_t get_a_hnp_support(dwc_otg_pcd_t * pcd);
++extern uint32_t get_a_alt_hnp_support(dwc_otg_pcd_t * pcd);
++
++/** CFI specific Interface functions */
++/** Allocate a cfi buffer */
++extern uint8_t *cfiw_ep_alloc_buffer(dwc_otg_pcd_t * pcd, void *pep,
++ dwc_dma_t * addr, size_t buflen,
++ int flags);
++
++/******************************************************************************/
++
++/** @} */
++
++#endif /* __DWC_PCD_IF_H__ */
++
++#endif /* DWC_HOST_ONLY */
+diff -Nur linux-4.1.3/drivers/usb/host/dwc_otg/dwc_otg_pcd_intr.c linux-xbian-rpi/drivers/usb/host/dwc_otg/dwc_otg_pcd_intr.c
+--- linux-4.1.3/drivers/usb/host/dwc_otg/dwc_otg_pcd_intr.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/usb/host/dwc_otg/dwc_otg_pcd_intr.c 2015-07-28 01:20:58.449142252 +0200
+@@ -0,0 +1,5147 @@
++/* ==========================================================================
++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_intr.c $
++ * $Revision: #116 $
++ * $Date: 2012/08/10 $
++ * $Change: 2047372 $
++ *
++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++ * otherwise expressly agreed to in writing between Synopsys and you.
++ *
++ * The Software IS NOT an item of Licensed Software or Licensed Product under
++ * any End User Software License Agreement or Agreement for Licensed Product
++ * with Synopsys or any supplement thereto. You are permitted to use and
++ * redistribute this Software in source and binary forms, with or without
++ * modification, provided that redistributions of source code must retain this
++ * notice. You may not view, use, disclose, copy or distribute this file or
++ * any information contained herein except pursuant to this license grant from
++ * Synopsys. If you do not agree with this notice, including the disclaimer
++ * below, then you are not authorized to use the Software.
++ *
++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++ * DAMAGE.
++ * ========================================================================== */
++#ifndef DWC_HOST_ONLY
++
++#include "dwc_otg_pcd.h"
++
++#ifdef DWC_UTE_CFI
++#include "dwc_otg_cfi.h"
++#endif
++
++#ifdef DWC_UTE_PER_IO
++extern void complete_xiso_ep(dwc_otg_pcd_ep_t * ep);
++#endif
++//#define PRINT_CFI_DMA_DESCS
++
++#define DEBUG_EP0
++
++/**
++ * This function updates OTG.
++ */
++static void dwc_otg_pcd_update_otg(dwc_otg_pcd_t * pcd, const unsigned reset)
++{
++
++ if (reset) {
++ pcd->b_hnp_enable = 0;
++ pcd->a_hnp_support = 0;
++ pcd->a_alt_hnp_support = 0;
++ }
++
++ if (pcd->fops->hnp_changed) {
++ pcd->fops->hnp_changed(pcd);
++ }
++}
++
++/** @file
++ * This file contains the implementation of the PCD Interrupt handlers.
++ *
++ * The PCD handles the device interrupts. Many conditions can cause a
++ * device interrupt. When an interrupt occurs, the device interrupt
++ * service routine determines the cause of the interrupt and
++ * dispatches handling to the appropriate function. These interrupt
++ * handling functions are described below.
++ * All interrupt registers are processed from LSB to MSB.
++ */
++
++/**
++ * This function prints the ep0 state for debug purposes.
++ */
++static inline void print_ep0_state(dwc_otg_pcd_t * pcd)
++{
++#ifdef DEBUG
++ char str[40];
++
++ switch (pcd->ep0state) {
++ case EP0_DISCONNECT:
++ dwc_strcpy(str, "EP0_DISCONNECT");
++ break;
++ case EP0_IDLE:
++ dwc_strcpy(str, "EP0_IDLE");
++ break;
++ case EP0_IN_DATA_PHASE:
++ dwc_strcpy(str, "EP0_IN_DATA_PHASE");
++ break;
++ case EP0_OUT_DATA_PHASE:
++ dwc_strcpy(str, "EP0_OUT_DATA_PHASE");
++ break;
++ case EP0_IN_STATUS_PHASE:
++ dwc_strcpy(str, "EP0_IN_STATUS_PHASE");
++ break;
++ case EP0_OUT_STATUS_PHASE:
++ dwc_strcpy(str, "EP0_OUT_STATUS_PHASE");
++ break;
++ case EP0_STALL:
++ dwc_strcpy(str, "EP0_STALL");
++ break;
++ default:
++ dwc_strcpy(str, "EP0_INVALID");
++ }
++
++ DWC_DEBUGPL(DBG_ANY, "%s(%d)\n", str, pcd->ep0state);
++#endif
++}
++
++/**
++ * This function calculate the size of the payload in the memory
++ * for out endpoints and prints size for debug purposes(used in
++ * 2.93a DevOutNak feature).
++ */
++static inline void print_memory_payload(dwc_otg_pcd_t * pcd, dwc_ep_t * ep)
++{
++#ifdef DEBUG
++ deptsiz_data_t deptsiz_init = {.d32 = 0 };
++ deptsiz_data_t deptsiz_updt = {.d32 = 0 };
++ int pack_num;
++ unsigned payload;
++
++ deptsiz_init.d32 = pcd->core_if->start_doeptsiz_val[ep->num];
++ deptsiz_updt.d32 =
++ DWC_READ_REG32(&pcd->core_if->dev_if->
++ out_ep_regs[ep->num]->doeptsiz);
++ /* Payload will be */
++ payload = deptsiz_init.b.xfersize - deptsiz_updt.b.xfersize;
++ /* Packet count is decremented every time a packet
++ * is written to the RxFIFO not in to the external memory
++ * So, if payload == 0, then it means no packet was sent to ext memory*/
++ pack_num = (!payload) ? 0 : (deptsiz_init.b.pktcnt - deptsiz_updt.b.pktcnt);
++ DWC_DEBUGPL(DBG_PCDV,
++ "Payload for EP%d-%s\n",
++ ep->num, (ep->is_in ? "IN" : "OUT"));
++ DWC_DEBUGPL(DBG_PCDV,
++ "Number of transfered bytes = 0x%08x\n", payload);
++ DWC_DEBUGPL(DBG_PCDV,
++ "Number of transfered packets = %d\n", pack_num);
++#endif
++}
++
++
++#ifdef DWC_UTE_CFI
++static inline void print_desc(struct dwc_otg_dma_desc *ddesc,
++ const uint8_t * epname, int descnum)
++{
++ CFI_INFO
++ ("%s DMA_DESC(%d) buf=0x%08x bytes=0x%04x; sp=0x%x; l=0x%x; sts=0x%02x; bs=0x%02x\n",
++ epname, descnum, ddesc->buf, ddesc->status.b.bytes,
++ ddesc->status.b.sp, ddesc->status.b.l, ddesc->status.b.sts,
++ ddesc->status.b.bs);
++}
++#endif
++
++/**
++ * This function returns pointer to in ep struct with number ep_num
++ */
++static inline dwc_otg_pcd_ep_t *get_in_ep(dwc_otg_pcd_t * pcd, uint32_t ep_num)
++{
++ int i;
++ int num_in_eps = GET_CORE_IF(pcd)->dev_if->num_in_eps;
++ if (ep_num == 0) {
++ return &pcd->ep0;
++ } else {
++ for (i = 0; i < num_in_eps; ++i) {
++ if (pcd->in_ep[i].dwc_ep.num == ep_num)
++ return &pcd->in_ep[i];
++ }
++ return 0;
++ }
++}
++
++/**
++ * This function returns pointer to out ep struct with number ep_num
++ */
++static inline dwc_otg_pcd_ep_t *get_out_ep(dwc_otg_pcd_t * pcd, uint32_t ep_num)
++{
++ int i;
++ int num_out_eps = GET_CORE_IF(pcd)->dev_if->num_out_eps;
++ if (ep_num == 0) {
++ return &pcd->ep0;
++ } else {
++ for (i = 0; i < num_out_eps; ++i) {
++ if (pcd->out_ep[i].dwc_ep.num == ep_num)
++ return &pcd->out_ep[i];
++ }
++ return 0;
++ }
++}
++
++/**
++ * This functions gets a pointer to an EP from the wIndex address
++ * value of the control request.
++ */
++dwc_otg_pcd_ep_t *get_ep_by_addr(dwc_otg_pcd_t * pcd, u16 wIndex)
++{
++ dwc_otg_pcd_ep_t *ep;
++ uint32_t ep_num = UE_GET_ADDR(wIndex);
++
++ if (ep_num == 0) {
++ ep = &pcd->ep0;
++ } else if (UE_GET_DIR(wIndex) == UE_DIR_IN) { /* in ep */
++ ep = &pcd->in_ep[ep_num - 1];
++ } else {
++ ep = &pcd->out_ep[ep_num - 1];
++ }
++
++ return ep;
++}
++
++/**
++ * This function checks the EP request queue, if the queue is not
++ * empty the next request is started.
++ */
++void start_next_request(dwc_otg_pcd_ep_t * ep)
++{
++ dwc_otg_pcd_request_t *req = 0;
++ uint32_t max_transfer =
++ GET_CORE_IF(ep->pcd)->core_params->max_transfer_size;
++
++#ifdef DWC_UTE_CFI
++ struct dwc_otg_pcd *pcd;
++ pcd = ep->pcd;
++#endif
++
++ if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
++ req = DWC_CIRCLEQ_FIRST(&ep->queue);
++
++#ifdef DWC_UTE_CFI
++ if (ep->dwc_ep.buff_mode != BM_STANDARD) {
++ ep->dwc_ep.cfi_req_len = req->length;
++ pcd->cfi->ops.build_descriptors(pcd->cfi, pcd, ep, req);
++ } else {
++#endif
++ /* Setup and start the Transfer */
++ if (req->dw_align_buf) {
++ ep->dwc_ep.dma_addr = req->dw_align_buf_dma;
++ ep->dwc_ep.start_xfer_buff = req->dw_align_buf;
++ ep->dwc_ep.xfer_buff = req->dw_align_buf;
++ } else {
++ ep->dwc_ep.dma_addr = req->dma;
++ ep->dwc_ep.start_xfer_buff = req->buf;
++ ep->dwc_ep.xfer_buff = req->buf;
++ }
++ ep->dwc_ep.sent_zlp = 0;
++ ep->dwc_ep.total_len = req->length;
++ ep->dwc_ep.xfer_len = 0;
++ ep->dwc_ep.xfer_count = 0;
++
++ ep->dwc_ep.maxxfer = max_transfer;
++ if (GET_CORE_IF(ep->pcd)->dma_desc_enable) {
++ uint32_t out_max_xfer = DDMA_MAX_TRANSFER_SIZE
++ - (DDMA_MAX_TRANSFER_SIZE % 4);
++ if (ep->dwc_ep.is_in) {
++ if (ep->dwc_ep.maxxfer >
++ DDMA_MAX_TRANSFER_SIZE) {
++ ep->dwc_ep.maxxfer =
++ DDMA_MAX_TRANSFER_SIZE;
++ }
++ } else {
++ if (ep->dwc_ep.maxxfer > out_max_xfer) {
++ ep->dwc_ep.maxxfer =
++ out_max_xfer;
++ }
++ }
++ }
++ if (ep->dwc_ep.maxxfer < ep->dwc_ep.total_len) {
++ ep->dwc_ep.maxxfer -=
++ (ep->dwc_ep.maxxfer % ep->dwc_ep.maxpacket);
++ }
++ if (req->sent_zlp) {
++ if ((ep->dwc_ep.total_len %
++ ep->dwc_ep.maxpacket == 0)
++ && (ep->dwc_ep.total_len != 0)) {
++ ep->dwc_ep.sent_zlp = 1;
++ }
++
++ }
++#ifdef DWC_UTE_CFI
++ }
++#endif
++ dwc_otg_ep_start_transfer(GET_CORE_IF(ep->pcd), &ep->dwc_ep);
++ } else if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
++ DWC_PRINTF("There are no more ISOC requests \n");
++ ep->dwc_ep.frame_num = 0xFFFFFFFF;
++ }
++}
++
++/**
++ * This function handles the SOF Interrupts. At this time the SOF
++ * Interrupt is disabled.
++ */
++int32_t dwc_otg_pcd_handle_sof_intr(dwc_otg_pcd_t * pcd)
++{
++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++
++ gintsts_data_t gintsts;
++
++ DWC_DEBUGPL(DBG_PCD, "SOF\n");
++
++ /* Clear interrupt */
++ gintsts.d32 = 0;
++ gintsts.b.sofintr = 1;
++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
++
++ return 1;
++}
++
++/**
++ * This function handles the Rx Status Queue Level Interrupt, which
++ * indicates that there is a least one packet in the Rx FIFO. The
++ * packets are moved from the FIFO to memory, where they will be
++ * processed when the Endpoint Interrupt Register indicates Transfer
++ * Complete or SETUP Phase Done.
++ *
++ * Repeat the following until the Rx Status Queue is empty:
++ * -# Read the Receive Status Pop Register (GRXSTSP) to get Packet
++ * info
++ * -# If Receive FIFO is empty then skip to step Clear the interrupt
++ * and exit
++ * -# If SETUP Packet call dwc_otg_read_setup_packet to copy the
++ * SETUP data to the buffer
++ * -# If OUT Data Packet call dwc_otg_read_packet to copy the data
++ * to the destination buffer
++ */
++int32_t dwc_otg_pcd_handle_rx_status_q_level_intr(dwc_otg_pcd_t * pcd)
++{
++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
++ gintmsk_data_t gintmask = {.d32 = 0 };
++ device_grxsts_data_t status;
++ dwc_otg_pcd_ep_t *ep;
++ gintsts_data_t gintsts;
++#ifdef DEBUG
++ static char *dpid_str[] = { "D0", "D2", "D1", "MDATA" };
++#endif
++
++ //DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, _pcd);
++ /* Disable the Rx Status Queue Level interrupt */
++ gintmask.b.rxstsqlvl = 1;
++ DWC_MODIFY_REG32(&global_regs->gintmsk, gintmask.d32, 0);
++
++ /* Get the Status from the top of the FIFO */
++ status.d32 = DWC_READ_REG32(&global_regs->grxstsp);
++
++ DWC_DEBUGPL(DBG_PCD, "EP:%d BCnt:%d DPID:%s "
++ "pktsts:%x Frame:%d(0x%0x)\n",
++ status.b.epnum, status.b.bcnt,
++ dpid_str[status.b.dpid],
++ status.b.pktsts, status.b.fn, status.b.fn);
++ /* Get pointer to EP structure */
++ ep = get_out_ep(pcd, status.b.epnum);
++
++ switch (status.b.pktsts) {
++ case DWC_DSTS_GOUT_NAK:
++ DWC_DEBUGPL(DBG_PCDV, "Global OUT NAK\n");
++ break;
++ case DWC_STS_DATA_UPDT:
++ DWC_DEBUGPL(DBG_PCDV, "OUT Data Packet\n");
++ if (status.b.bcnt && ep->dwc_ep.xfer_buff) {
++ /** @todo NGS Check for buffer overflow? */
++ dwc_otg_read_packet(core_if,
++ ep->dwc_ep.xfer_buff,
++ status.b.bcnt);
++ ep->dwc_ep.xfer_count += status.b.bcnt;
++ ep->dwc_ep.xfer_buff += status.b.bcnt;
++ }
++ break;
++ case DWC_STS_XFER_COMP:
++ DWC_DEBUGPL(DBG_PCDV, "OUT Complete\n");
++ break;
++ case DWC_DSTS_SETUP_COMP:
++#ifdef DEBUG_EP0
++ DWC_DEBUGPL(DBG_PCDV, "Setup Complete\n");
++#endif
++ break;
++ case DWC_DSTS_SETUP_UPDT:
++ dwc_otg_read_setup_packet(core_if, pcd->setup_pkt->d32);
++#ifdef DEBUG_EP0
++ DWC_DEBUGPL(DBG_PCD,
++ "SETUP PKT: %02x.%02x v%04x i%04x l%04x\n",
++ pcd->setup_pkt->req.bmRequestType,
++ pcd->setup_pkt->req.bRequest,
++ UGETW(pcd->setup_pkt->req.wValue),
++ UGETW(pcd->setup_pkt->req.wIndex),
++ UGETW(pcd->setup_pkt->req.wLength));
++#endif
++ ep->dwc_ep.xfer_count += status.b.bcnt;
++ break;
++ default:
++ DWC_DEBUGPL(DBG_PCDV, "Invalid Packet Status (0x%0x)\n",
++ status.b.pktsts);
++ break;
++ }
++
++ /* Enable the Rx Status Queue Level interrupt */
++ DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmask.d32);
++ /* Clear interrupt */
++ gintsts.d32 = 0;
++ gintsts.b.rxstsqlvl = 1;
++ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
++
++ //DWC_DEBUGPL(DBG_PCDV, "EXIT: %s\n", __func__);
++ return 1;
++}
++
++/**
++ * This function examines the Device IN Token Learning Queue to
++ * determine the EP number of the last IN token received. This
++ * implementation is for the Mass Storage device where there are only
++ * 2 IN EPs (Control-IN and BULK-IN).
++ *
++ * The EP numbers for the first six IN Tokens are in DTKNQR1 and there
++ * are 8 EP Numbers in each of the other possible DTKNQ Registers.
++ *
++ * @param core_if Programming view of DWC_otg controller.
++ *
++ */
++static inline int get_ep_of_last_in_token(dwc_otg_core_if_t * core_if)
++{
++ dwc_otg_device_global_regs_t *dev_global_regs =
++ core_if->dev_if->dev_global_regs;
++ const uint32_t TOKEN_Q_DEPTH = core_if->hwcfg2.b.dev_token_q_depth;
++ /* Number of Token Queue Registers */
++ const int DTKNQ_REG_CNT = (TOKEN_Q_DEPTH + 7) / 8;
++ dtknq1_data_t dtknqr1;
++ uint32_t in_tkn_epnums[4];
++ int ndx = 0;
++ int i = 0;
++ volatile uint32_t *addr = &dev_global_regs->dtknqr1;
++ int epnum = 0;
++
++ //DWC_DEBUGPL(DBG_PCD,"dev_token_q_depth=%d\n",TOKEN_Q_DEPTH);
++
++ /* Read the DTKNQ Registers */
++ for (i = 0; i < DTKNQ_REG_CNT; i++) {
++ in_tkn_epnums[i] = DWC_READ_REG32(addr);
++ DWC_DEBUGPL(DBG_PCDV, "DTKNQR%d=0x%08x\n", i + 1,
++ in_tkn_epnums[i]);
++ if (addr == &dev_global_regs->dvbusdis) {
++ addr = &dev_global_regs->dtknqr3_dthrctl;
++ } else {
++ ++addr;
++ }
++
++ }
++
++ /* Copy the DTKNQR1 data to the bit field. */
++ dtknqr1.d32 = in_tkn_epnums[0];
++ /* Get the EP numbers */
++ in_tkn_epnums[0] = dtknqr1.b.epnums0_5;
++ ndx = dtknqr1.b.intknwptr - 1;
++
++ //DWC_DEBUGPL(DBG_PCDV,"ndx=%d\n",ndx);
++ if (ndx == -1) {
++ /** @todo Find a simpler way to calculate the max
++ * queue position.*/
++ int cnt = TOKEN_Q_DEPTH;
++ if (TOKEN_Q_DEPTH <= 6) {
++ cnt = TOKEN_Q_DEPTH - 1;
++ } else if (TOKEN_Q_DEPTH <= 14) {
++ cnt = TOKEN_Q_DEPTH - 7;
++ } else if (TOKEN_Q_DEPTH <= 22) {
++ cnt = TOKEN_Q_DEPTH - 15;
++ } else {
++ cnt = TOKEN_Q_DEPTH - 23;
++ }
++ epnum = (in_tkn_epnums[DTKNQ_REG_CNT - 1] >> (cnt * 4)) & 0xF;
++ } else {
++ if (ndx <= 5) {
++ epnum = (in_tkn_epnums[0] >> (ndx * 4)) & 0xF;
++ } else if (ndx <= 13) {
++ ndx -= 6;
++ epnum = (in_tkn_epnums[1] >> (ndx * 4)) & 0xF;
++ } else if (ndx <= 21) {
++ ndx -= 14;
++ epnum = (in_tkn_epnums[2] >> (ndx * 4)) & 0xF;
++ } else if (ndx <= 29) {
++ ndx -= 22;
++ epnum = (in_tkn_epnums[3] >> (ndx * 4)) & 0xF;
++ }
++ }
++ //DWC_DEBUGPL(DBG_PCD,"epnum=%d\n",epnum);
++ return epnum;
++}
++
++/**
++ * This interrupt occurs when the non-periodic Tx FIFO is half-empty.
++ * The active request is checked for the next packet to be loaded into
++ * the non-periodic Tx FIFO.
++ */
++int32_t dwc_otg_pcd_handle_np_tx_fifo_empty_intr(dwc_otg_pcd_t * pcd)
++{
++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
++ dwc_otg_dev_in_ep_regs_t *ep_regs;
++ gnptxsts_data_t txstatus = {.d32 = 0 };
++ gintsts_data_t gintsts;
++
++ int epnum = 0;
++ dwc_otg_pcd_ep_t *ep = 0;
++ uint32_t len = 0;
++ int dwords;
++
++ /* Get the epnum from the IN Token Learning Queue. */
++ epnum = get_ep_of_last_in_token(core_if);
++ ep = get_in_ep(pcd, epnum);
++
++ DWC_DEBUGPL(DBG_PCD, "NP TxFifo Empty: %d \n", epnum);
++
++ ep_regs = core_if->dev_if->in_ep_regs[epnum];
++
++ len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
++ if (len > ep->dwc_ep.maxpacket) {
++ len = ep->dwc_ep.maxpacket;
++ }
++ dwords = (len + 3) / 4;
++
++ /* While there is space in the queue and space in the FIFO and
++ * More data to tranfer, Write packets to the Tx FIFO */
++ txstatus.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
++ DWC_DEBUGPL(DBG_PCDV, "b4 GNPTXSTS=0x%08x\n", txstatus.d32);
++
++ while (txstatus.b.nptxqspcavail > 0 &&
++ txstatus.b.nptxfspcavail > dwords &&
++ ep->dwc_ep.xfer_count < ep->dwc_ep.xfer_len) {
++ /* Write the FIFO */
++ dwc_otg_ep_write_packet(core_if, &ep->dwc_ep, 0);
++ len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
++
++ if (len > ep->dwc_ep.maxpacket) {
++ len = ep->dwc_ep.maxpacket;
++ }
++
++ dwords = (len + 3) / 4;
++ txstatus.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
++ DWC_DEBUGPL(DBG_PCDV, "GNPTXSTS=0x%08x\n", txstatus.d32);
++ }
++
++ DWC_DEBUGPL(DBG_PCDV, "GNPTXSTS=0x%08x\n",
++ DWC_READ_REG32(&global_regs->gnptxsts));
++
++ /* Clear interrupt */
++ gintsts.d32 = 0;
++ gintsts.b.nptxfempty = 1;
++ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
++
++ return 1;
++}
++
++/**
++ * This function is called when dedicated Tx FIFO Empty interrupt occurs.
++ * The active request is checked for the next packet to be loaded into
++ * apropriate Tx FIFO.
++ */
++static int32_t write_empty_tx_fifo(dwc_otg_pcd_t * pcd, uint32_t epnum)
++{
++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++ dwc_otg_dev_if_t *dev_if = core_if->dev_if;
++ dwc_otg_dev_in_ep_regs_t *ep_regs;
++ dtxfsts_data_t txstatus = {.d32 = 0 };
++ dwc_otg_pcd_ep_t *ep = 0;
++ uint32_t len = 0;
++ int dwords;
++
++ ep = get_in_ep(pcd, epnum);
++
++ DWC_DEBUGPL(DBG_PCD, "Dedicated TxFifo Empty: %d \n", epnum);
++
++ ep_regs = core_if->dev_if->in_ep_regs[epnum];
++
++ len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
++
++ if (len > ep->dwc_ep.maxpacket) {
++ len = ep->dwc_ep.maxpacket;
++ }
++
++ dwords = (len + 3) / 4;
++
++ /* While there is space in the queue and space in the FIFO and
++ * More data to tranfer, Write packets to the Tx FIFO */
++ txstatus.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts);
++ DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum, txstatus.d32);
++
++ while (txstatus.b.txfspcavail > dwords &&
++ ep->dwc_ep.xfer_count < ep->dwc_ep.xfer_len &&
++ ep->dwc_ep.xfer_len != 0) {
++ /* Write the FIFO */
++ dwc_otg_ep_write_packet(core_if, &ep->dwc_ep, 0);
++
++ len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
++ if (len > ep->dwc_ep.maxpacket) {
++ len = ep->dwc_ep.maxpacket;
++ }
++
++ dwords = (len + 3) / 4;
++ txstatus.d32 =
++ DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts);
++ DWC_DEBUGPL(DBG_PCDV, "dtxfsts[%d]=0x%08x\n", epnum,
++ txstatus.d32);
++ }
++
++ DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum,
++ DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts));
++
++ return 1;
++}
++
++/**
++ * This function is called when the Device is disconnected. It stops
++ * any active requests and informs the Gadget driver of the
++ * disconnect.
++ */
++void dwc_otg_pcd_stop(dwc_otg_pcd_t * pcd)
++{
++ int i, num_in_eps, num_out_eps;
++ dwc_otg_pcd_ep_t *ep;
++
++ gintmsk_data_t intr_mask = {.d32 = 0 };
++
++ DWC_SPINLOCK(pcd->lock);
++
++ num_in_eps = GET_CORE_IF(pcd)->dev_if->num_in_eps;
++ num_out_eps = GET_CORE_IF(pcd)->dev_if->num_out_eps;
++
++ DWC_DEBUGPL(DBG_PCDV, "%s() \n", __func__);
++ /* don't disconnect drivers more than once */
++ if (pcd->ep0state == EP0_DISCONNECT) {
++ DWC_DEBUGPL(DBG_ANY, "%s() Already Disconnected\n", __func__);
++ DWC_SPINUNLOCK(pcd->lock);
++ return;
++ }
++ pcd->ep0state = EP0_DISCONNECT;
++
++ /* Reset the OTG state. */
++ dwc_otg_pcd_update_otg(pcd, 1);
++
++ /* Disable the NP Tx Fifo Empty Interrupt. */
++ intr_mask.b.nptxfempty = 1;
++ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
++ intr_mask.d32, 0);
++
++ /* Flush the FIFOs */
++ /**@todo NGS Flush Periodic FIFOs */
++ dwc_otg_flush_tx_fifo(GET_CORE_IF(pcd), 0x10);
++ dwc_otg_flush_rx_fifo(GET_CORE_IF(pcd));
++
++ /* prevent new request submissions, kill any outstanding requests */
++ ep = &pcd->ep0;
++ dwc_otg_request_nuke(ep);
++ /* prevent new request submissions, kill any outstanding requests */
++ for (i = 0; i < num_in_eps; i++) {
++ dwc_otg_pcd_ep_t *ep = &pcd->in_ep[i];
++ dwc_otg_request_nuke(ep);
++ }
++ /* prevent new request submissions, kill any outstanding requests */
++ for (i = 0; i < num_out_eps; i++) {
++ dwc_otg_pcd_ep_t *ep = &pcd->out_ep[i];
++ dwc_otg_request_nuke(ep);
++ }
++
++ /* report disconnect; the driver is already quiesced */
++ if (pcd->fops->disconnect) {
++ DWC_SPINUNLOCK(pcd->lock);
++ pcd->fops->disconnect(pcd);
++ DWC_SPINLOCK(pcd->lock);
++ }
++ DWC_SPINUNLOCK(pcd->lock);
++}
++
++/**
++ * This interrupt indicates that ...
++ */
++int32_t dwc_otg_pcd_handle_i2c_intr(dwc_otg_pcd_t * pcd)
++{
++ gintmsk_data_t intr_mask = {.d32 = 0 };
++ gintsts_data_t gintsts;
++
++ DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "i2cintr");
++ intr_mask.b.i2cintr = 1;
++ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
++ intr_mask.d32, 0);
++
++ /* Clear interrupt */
++ gintsts.d32 = 0;
++ gintsts.b.i2cintr = 1;
++ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
++ gintsts.d32);
++ return 1;
++}
++
++/**
++ * This interrupt indicates that ...
++ */
++int32_t dwc_otg_pcd_handle_early_suspend_intr(dwc_otg_pcd_t * pcd)
++{
++ gintsts_data_t gintsts;
++#if defined(VERBOSE)
++ DWC_PRINTF("Early Suspend Detected\n");
++#endif
++
++ /* Clear interrupt */
++ gintsts.d32 = 0;
++ gintsts.b.erlysuspend = 1;
++ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
++ gintsts.d32);
++ return 1;
++}
++
++/**
++ * This function configures EPO to receive SETUP packets.
++ *
++ * @todo NGS: Update the comments from the HW FS.
++ *
++ * -# Program the following fields in the endpoint specific registers
++ * for Control OUT EP 0, in order to receive a setup packet
++ * - DOEPTSIZ0.Packet Count = 3 (To receive up to 3 back to back
++ * setup packets)
++ * - DOEPTSIZE0.Transfer Size = 24 Bytes (To receive up to 3 back
++ * to back setup packets)
++ * - In DMA mode, DOEPDMA0 Register with a memory address to
++ * store any setup packets received
++ *
++ * @param core_if Programming view of DWC_otg controller.
++ * @param pcd Programming view of the PCD.
++ */
++static inline void ep0_out_start(dwc_otg_core_if_t * core_if,
++ dwc_otg_pcd_t * pcd)
++{
++ dwc_otg_dev_if_t *dev_if = core_if->dev_if;
++ deptsiz0_data_t doeptsize0 = {.d32 = 0 };
++ dwc_otg_dev_dma_desc_t *dma_desc;
++ depctl_data_t doepctl = {.d32 = 0 };
++
++#ifdef VERBOSE
++ DWC_DEBUGPL(DBG_PCDV, "%s() doepctl0=%0x\n", __func__,
++ DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl));
++#endif
++ if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
++ doepctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl);
++ if (doepctl.b.epena) {
++ return;
++ }
++ }
++
++ doeptsize0.b.supcnt = 3;
++ doeptsize0.b.pktcnt = 1;
++ doeptsize0.b.xfersize = 8 * 3;
++
++ if (core_if->dma_enable) {
++ if (!core_if->dma_desc_enable) {
++ /** put here as for Hermes mode deptisz register should not be written */
++ DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doeptsiz,
++ doeptsize0.d32);
++
++ /** @todo dma needs to handle multiple setup packets (up to 3) */
++ DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepdma,
++ pcd->setup_pkt_dma_handle);
++ } else {
++ dev_if->setup_desc_index =
++ (dev_if->setup_desc_index + 1) & 1;
++ dma_desc =
++ dev_if->setup_desc_addr[dev_if->setup_desc_index];
++
++ /** DMA Descriptor Setup */
++ dma_desc->status.b.bs = BS_HOST_BUSY;
++ if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
++ dma_desc->status.b.sr = 0;
++ dma_desc->status.b.mtrf = 0;
++ }
++ dma_desc->status.b.l = 1;
++ dma_desc->status.b.ioc = 1;
++ dma_desc->status.b.bytes = pcd->ep0.dwc_ep.maxpacket;
++ dma_desc->buf = pcd->setup_pkt_dma_handle;
++ dma_desc->status.b.sts = 0;
++ dma_desc->status.b.bs = BS_HOST_READY;
++
++ /** DOEPDMA0 Register write */
++ DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepdma,
++ dev_if->dma_setup_desc_addr
++ [dev_if->setup_desc_index]);
++ }
++
++ } else {
++ /** put here as for Hermes mode deptisz register should not be written */
++ DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doeptsiz,
++ doeptsize0.d32);
++ }
++
++ /** DOEPCTL0 Register write cnak will be set after setup interrupt */
++ doepctl.d32 = 0;
++ doepctl.b.epena = 1;
++ if (core_if->snpsid <= OTG_CORE_REV_2_94a) {
++ doepctl.b.cnak = 1;
++ DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepctl, doepctl.d32);
++ } else {
++ DWC_MODIFY_REG32(&dev_if->out_ep_regs[0]->doepctl, 0, doepctl.d32);
++ }
++
++#ifdef VERBOSE
++ DWC_DEBUGPL(DBG_PCDV, "doepctl0=%0x\n",
++ DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl));
++ DWC_DEBUGPL(DBG_PCDV, "diepctl0=%0x\n",
++ DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl));
++#endif
++}
++
++/**
++ * This interrupt occurs when a USB Reset is detected. When the USB
++ * Reset Interrupt occurs the device state is set to DEFAULT and the
++ * EP0 state is set to IDLE.
++ * -# Set the NAK bit for all OUT endpoints (DOEPCTLn.SNAK = 1)
++ * -# Unmask the following interrupt bits
++ * - DAINTMSK.INEP0 = 1 (Control 0 IN endpoint)
++ * - DAINTMSK.OUTEP0 = 1 (Control 0 OUT endpoint)
++ * - DOEPMSK.SETUP = 1
++ * - DOEPMSK.XferCompl = 1
++ * - DIEPMSK.XferCompl = 1
++ * - DIEPMSK.TimeOut = 1
++ * -# Program the following fields in the endpoint specific registers
++ * for Control OUT EP 0, in order to receive a setup packet
++ * - DOEPTSIZ0.Packet Count = 3 (To receive up to 3 back to back
++ * setup packets)
++ * - DOEPTSIZE0.Transfer Size = 24 Bytes (To receive up to 3 back
++ * to back setup packets)
++ * - In DMA mode, DOEPDMA0 Register with a memory address to
++ * store any setup packets received
++ * At this point, all the required initialization, except for enabling
++ * the control 0 OUT endpoint is done, for receiving SETUP packets.
++ */
++int32_t dwc_otg_pcd_handle_usb_reset_intr(dwc_otg_pcd_t * pcd)
++{
++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++ dwc_otg_dev_if_t *dev_if = core_if->dev_if;
++ depctl_data_t doepctl = {.d32 = 0 };
++ depctl_data_t diepctl = {.d32 = 0 };
++ daint_data_t daintmsk = {.d32 = 0 };
++ doepmsk_data_t doepmsk = {.d32 = 0 };
++ diepmsk_data_t diepmsk = {.d32 = 0 };
++ dcfg_data_t dcfg = {.d32 = 0 };
++ grstctl_t resetctl = {.d32 = 0 };
++ dctl_data_t dctl = {.d32 = 0 };
++ int i = 0;
++ gintsts_data_t gintsts;
++ pcgcctl_data_t power = {.d32 = 0 };
++
++ power.d32 = DWC_READ_REG32(core_if->pcgcctl);
++ if (power.b.stoppclk) {
++ power.d32 = 0;
++ power.b.stoppclk = 1;
++ DWC_MODIFY_REG32(core_if->pcgcctl, power.d32, 0);
++
++ power.b.pwrclmp = 1;
++ DWC_MODIFY_REG32(core_if->pcgcctl, power.d32, 0);
++
++ power.b.rstpdwnmodule = 1;
++ DWC_MODIFY_REG32(core_if->pcgcctl, power.d32, 0);
++ }
++
++ core_if->lx_state = DWC_OTG_L0;
++
++ DWC_PRINTF("USB RESET\n");
++#ifdef DWC_EN_ISOC
++ for (i = 1; i < 16; ++i) {
++ dwc_otg_pcd_ep_t *ep;
++ dwc_ep_t *dwc_ep;
++ ep = get_in_ep(pcd, i);
++ if (ep != 0) {
++ dwc_ep = &ep->dwc_ep;
++ dwc_ep->next_frame = 0xffffffff;
++ }
++ }
++#endif /* DWC_EN_ISOC */
++
++ /* reset the HNP settings */
++ dwc_otg_pcd_update_otg(pcd, 1);
++
++ /* Clear the Remote Wakeup Signalling */
++ dctl.b.rmtwkupsig = 1;
++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, 0);
++
++ /* Set NAK for all OUT EPs */
++ doepctl.b.snak = 1;
++ for (i = 0; i <= dev_if->num_out_eps; i++) {
++ DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepctl, doepctl.d32);
++ }
++
++ /* Flush the NP Tx FIFO */
++ dwc_otg_flush_tx_fifo(core_if, 0x10);
++ /* Flush the Learning Queue */
++ resetctl.b.intknqflsh = 1;
++ DWC_WRITE_REG32(&core_if->core_global_regs->grstctl, resetctl.d32);
++
++ if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable) {
++ core_if->start_predict = 0;
++ for (i = 0; i<= core_if->dev_if->num_in_eps; ++i) {
++ core_if->nextep_seq[i] = 0xff; // 0xff - EP not active
++ }
++ core_if->nextep_seq[0] = 0;
++ core_if->first_in_nextep_seq = 0;
++ diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl);
++ diepctl.b.nextep = 0;
++ DWC_WRITE_REG32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32);
++
++ /* Update IN Endpoint Mismatch Count by active IN NP EP count + 1 */
++ dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);
++ dcfg.b.epmscnt = 2;
++ DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
++
++ DWC_DEBUGPL(DBG_PCDV,
++ "%s first_in_nextep_seq= %2d; nextep_seq[]:\n",
++ __func__, core_if->first_in_nextep_seq);
++ for (i=0; i <= core_if->dev_if->num_in_eps; i++) {
++ DWC_DEBUGPL(DBG_PCDV, "%2d\n", core_if->nextep_seq[i]);
++ }
++ }
++
++ if (core_if->multiproc_int_enable) {
++ daintmsk.b.inep0 = 1;
++ daintmsk.b.outep0 = 1;
++ DWC_WRITE_REG32(&dev_if->dev_global_regs->deachintmsk,
++ daintmsk.d32);
++
++ doepmsk.b.setup = 1;
++ doepmsk.b.xfercompl = 1;
++ doepmsk.b.ahberr = 1;
++ doepmsk.b.epdisabled = 1;
++
++ if ((core_if->dma_desc_enable) ||
++ (core_if->dma_enable
++ && core_if->snpsid >= OTG_CORE_REV_3_00a)) {
++ doepmsk.b.stsphsercvd = 1;
++ }
++ if (core_if->dma_desc_enable)
++ doepmsk.b.bna = 1;
++/*
++ doepmsk.b.babble = 1;
++ doepmsk.b.nyet = 1;
++
++ if (core_if->dma_enable) {
++ doepmsk.b.nak = 1;
++ }
++*/
++ DWC_WRITE_REG32(&dev_if->dev_global_regs->doepeachintmsk[0],
++ doepmsk.d32);
++
++ diepmsk.b.xfercompl = 1;
++ diepmsk.b.timeout = 1;
++ diepmsk.b.epdisabled = 1;
++ diepmsk.b.ahberr = 1;
++ diepmsk.b.intknepmis = 1;
++ if (!core_if->en_multiple_tx_fifo && core_if->dma_enable)
++ diepmsk.b.intknepmis = 0;
++
++/* if (core_if->dma_desc_enable) {
++ diepmsk.b.bna = 1;
++ }
++*/
++/*
++ if (core_if->dma_enable) {
++ diepmsk.b.nak = 1;
++ }
++*/
++ DWC_WRITE_REG32(&dev_if->dev_global_regs->diepeachintmsk[0],
++ diepmsk.d32);
++ } else {
++ daintmsk.b.inep0 = 1;
++ daintmsk.b.outep0 = 1;
++ DWC_WRITE_REG32(&dev_if->dev_global_regs->daintmsk,
++ daintmsk.d32);
++
++ doepmsk.b.setup = 1;
++ doepmsk.b.xfercompl = 1;
++ doepmsk.b.ahberr = 1;
++ doepmsk.b.epdisabled = 1;
++
++ if ((core_if->dma_desc_enable) ||
++ (core_if->dma_enable
++ && core_if->snpsid >= OTG_CORE_REV_3_00a)) {
++ doepmsk.b.stsphsercvd = 1;
++ }
++ if (core_if->dma_desc_enable)
++ doepmsk.b.bna = 1;
++ DWC_WRITE_REG32(&dev_if->dev_global_regs->doepmsk, doepmsk.d32);
++
++ diepmsk.b.xfercompl = 1;
++ diepmsk.b.timeout = 1;
++ diepmsk.b.epdisabled = 1;
++ diepmsk.b.ahberr = 1;
++ if (!core_if->en_multiple_tx_fifo && core_if->dma_enable)
++ diepmsk.b.intknepmis = 0;
++/*
++ if (core_if->dma_desc_enable) {
++ diepmsk.b.bna = 1;
++ }
++*/
++
++ DWC_WRITE_REG32(&dev_if->dev_global_regs->diepmsk, diepmsk.d32);
++ }
++
++ /* Reset Device Address */
++ dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);
++ dcfg.b.devaddr = 0;
++ DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
++
++ /* setup EP0 to receive SETUP packets */
++ if (core_if->snpsid <= OTG_CORE_REV_2_94a)
++ ep0_out_start(core_if, pcd);
++
++ /* Clear interrupt */
++ gintsts.d32 = 0;
++ gintsts.b.usbreset = 1;
++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
++
++ return 1;
++}
++
++/**
++ * Get the device speed from the device status register and convert it
++ * to USB speed constant.
++ *
++ * @param core_if Programming view of DWC_otg controller.
++ */
++static int get_device_speed(dwc_otg_core_if_t * core_if)
++{
++ dsts_data_t dsts;
++ int speed = 0;
++ dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
++
++ switch (dsts.b.enumspd) {
++ case DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ:
++ speed = USB_SPEED_HIGH;
++ break;
++ case DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ:
++ case DWC_DSTS_ENUMSPD_FS_PHY_48MHZ:
++ speed = USB_SPEED_FULL;
++ break;
++
++ case DWC_DSTS_ENUMSPD_LS_PHY_6MHZ:
++ speed = USB_SPEED_LOW;
++ break;
++ }
++
++ return speed;
++}
++
++/**
++ * Read the device status register and set the device speed in the
++ * data structure.
++ * Set up EP0 to receive SETUP packets by calling dwc_ep0_activate.
++ */
++int32_t dwc_otg_pcd_handle_enum_done_intr(dwc_otg_pcd_t * pcd)
++{
++ dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
++ gintsts_data_t gintsts;
++ gusbcfg_data_t gusbcfg;
++ dwc_otg_core_global_regs_t *global_regs =
++ GET_CORE_IF(pcd)->core_global_regs;
++ uint8_t utmi16b, utmi8b;
++ int speed;
++ DWC_DEBUGPL(DBG_PCD, "SPEED ENUM\n");
++
++ if (GET_CORE_IF(pcd)->snpsid >= OTG_CORE_REV_2_60a) {
++ utmi16b = 6; //vahrama old value was 6;
++ utmi8b = 9;
++ } else {
++ utmi16b = 4;
++ utmi8b = 8;
++ }
++ dwc_otg_ep0_activate(GET_CORE_IF(pcd), &ep0->dwc_ep);
++ if (GET_CORE_IF(pcd)->snpsid >= OTG_CORE_REV_3_00a) {
++ ep0_out_start(GET_CORE_IF(pcd), pcd);
++ }
++
++#ifdef DEBUG_EP0
++ print_ep0_state(pcd);
++#endif
++
++ if (pcd->ep0state == EP0_DISCONNECT) {
++ pcd->ep0state = EP0_IDLE;
++ } else if (pcd->ep0state == EP0_STALL) {
++ pcd->ep0state = EP0_IDLE;
++ }
++
++ pcd->ep0state = EP0_IDLE;
++
++ ep0->stopped = 0;
++
++ speed = get_device_speed(GET_CORE_IF(pcd));
++ pcd->fops->connect(pcd, speed);
++
++ /* Set USB turnaround time based on device speed and PHY interface. */
++ gusbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
++ if (speed == USB_SPEED_HIGH) {
++ if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type ==
++ DWC_HWCFG2_HS_PHY_TYPE_ULPI) {
++ /* ULPI interface */
++ gusbcfg.b.usbtrdtim = 9;
++ }
++ if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type ==
++ DWC_HWCFG2_HS_PHY_TYPE_UTMI) {
++ /* UTMI+ interface */
++ if (GET_CORE_IF(pcd)->hwcfg4.b.utmi_phy_data_width == 0) {
++ gusbcfg.b.usbtrdtim = utmi8b;
++ } else if (GET_CORE_IF(pcd)->hwcfg4.
++ b.utmi_phy_data_width == 1) {
++ gusbcfg.b.usbtrdtim = utmi16b;
++ } else if (GET_CORE_IF(pcd)->
++ core_params->phy_utmi_width == 8) {
++ gusbcfg.b.usbtrdtim = utmi8b;
++ } else {
++ gusbcfg.b.usbtrdtim = utmi16b;
++ }
++ }
++ if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type ==
++ DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI) {
++ /* UTMI+ OR ULPI interface */
++ if (gusbcfg.b.ulpi_utmi_sel == 1) {
++ /* ULPI interface */
++ gusbcfg.b.usbtrdtim = 9;
++ } else {
++ /* UTMI+ interface */
++ if (GET_CORE_IF(pcd)->
++ core_params->phy_utmi_width == 16) {
++ gusbcfg.b.usbtrdtim = utmi16b;
++ } else {
++ gusbcfg.b.usbtrdtim = utmi8b;
++ }
++ }
++ }
++ } else {
++ /* Full or low speed */
++ gusbcfg.b.usbtrdtim = 9;
++ }
++ DWC_WRITE_REG32(&global_regs->gusbcfg, gusbcfg.d32);
++
++ /* Clear interrupt */
++ gintsts.d32 = 0;
++ gintsts.b.enumdone = 1;
++ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
++ gintsts.d32);
++ return 1;
++}
++
++/**
++ * This interrupt indicates that the ISO OUT Packet was dropped due to
++ * Rx FIFO full or Rx Status Queue Full. If this interrupt occurs
++ * read all the data from the Rx FIFO.
++ */
++int32_t dwc_otg_pcd_handle_isoc_out_packet_dropped_intr(dwc_otg_pcd_t * pcd)
++{
++ gintmsk_data_t intr_mask = {.d32 = 0 };
++ gintsts_data_t gintsts;
++
++ DWC_WARN("INTERRUPT Handler not implemented for %s\n",
++ "ISOC Out Dropped");
++
++ intr_mask.b.isooutdrop = 1;
++ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
++ intr_mask.d32, 0);
++
++ /* Clear interrupt */
++ gintsts.d32 = 0;
++ gintsts.b.isooutdrop = 1;
++ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
++ gintsts.d32);
++
++ return 1;
++}
++
++/**
++ * This interrupt indicates the end of the portion of the micro-frame
++ * for periodic transactions. If there is a periodic transaction for
++ * the next frame, load the packets into the EP periodic Tx FIFO.
++ */
++int32_t dwc_otg_pcd_handle_end_periodic_frame_intr(dwc_otg_pcd_t * pcd)
++{
++ gintmsk_data_t intr_mask = {.d32 = 0 };
++ gintsts_data_t gintsts;
++ DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "EOP");
++
++ intr_mask.b.eopframe = 1;
++ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
++ intr_mask.d32, 0);
++
++ /* Clear interrupt */
++ gintsts.d32 = 0;
++ gintsts.b.eopframe = 1;
++ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
++ gintsts.d32);
++
++ return 1;
++}
++
++/**
++ * This interrupt indicates that EP of the packet on the top of the
++ * non-periodic Tx FIFO does not match EP of the IN Token received.
++ *
++ * The "Device IN Token Queue" Registers are read to determine the
++ * order the IN Tokens have been received. The non-periodic Tx FIFO
++ * is flushed, so it can be reloaded in the order seen in the IN Token
++ * Queue.
++ */
++int32_t dwc_otg_pcd_handle_ep_mismatch_intr(dwc_otg_pcd_t * pcd)
++{
++ gintsts_data_t gintsts;
++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++ dctl_data_t dctl;
++ gintmsk_data_t intr_mask = {.d32 = 0 };
++
++ if (!core_if->en_multiple_tx_fifo && core_if->dma_enable) {
++ core_if->start_predict = 1;
++
++ DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, core_if);
++
++ gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
++ if (!gintsts.b.ginnakeff) {
++ /* Disable EP Mismatch interrupt */
++ intr_mask.d32 = 0;
++ intr_mask.b.epmismatch = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, intr_mask.d32, 0);
++ /* Enable the Global IN NAK Effective Interrupt */
++ intr_mask.d32 = 0;
++ intr_mask.b.ginnakeff = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0, intr_mask.d32);
++ /* Set the global non-periodic IN NAK handshake */
++ dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
++ dctl.b.sgnpinnak = 1;
++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
++ } else {
++ DWC_PRINTF("gintsts.b.ginnakeff = 1! dctl.b.sgnpinnak not set\n");
++ }
++ /* Disabling of all EP's will be done in dwc_otg_pcd_handle_in_nak_effective()
++ * handler after Global IN NAK Effective interrupt will be asserted */
++ }
++ /* Clear interrupt */
++ gintsts.d32 = 0;
++ gintsts.b.epmismatch = 1;
++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
++
++ return 1;
++}
++
++/**
++ * This interrupt is valid only in DMA mode. This interrupt indicates that the
++ * core has stopped fetching data for IN endpoints due to the unavailability of
++ * TxFIFO space or Request Queue space. This interrupt is used by the
++ * application for an endpoint mismatch algorithm.
++ *
++ * @param pcd The PCD
++ */
++int32_t dwc_otg_pcd_handle_ep_fetsusp_intr(dwc_otg_pcd_t * pcd)
++{
++ gintsts_data_t gintsts;
++ gintmsk_data_t gintmsk_data;
++ dctl_data_t dctl;
++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++ DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, core_if);
++
++ /* Clear the global non-periodic IN NAK handshake */
++ dctl.d32 = 0;
++ dctl.b.cgnpinnak = 1;
++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);
++
++ /* Mask GINTSTS.FETSUSP interrupt */
++ gintmsk_data.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
++ gintmsk_data.b.fetsusp = 0;
++ DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gintmsk_data.d32);
++
++ /* Clear interrupt */
++ gintsts.d32 = 0;
++ gintsts.b.fetsusp = 1;
++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
++
++ return 1;
++}
++/**
++ * This funcion stalls EP0.
++ */
++static inline void ep0_do_stall(dwc_otg_pcd_t * pcd, const int err_val)
++{
++ dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
++ usb_device_request_t *ctrl = &pcd->setup_pkt->req;
++ DWC_WARN("req %02x.%02x protocol STALL; err %d\n",
++ ctrl->bmRequestType, ctrl->bRequest, err_val);
++
++ ep0->dwc_ep.is_in = 1;
++ dwc_otg_ep_set_stall(GET_CORE_IF(pcd), &ep0->dwc_ep);
++ pcd->ep0.stopped = 1;
++ pcd->ep0state = EP0_IDLE;
++ ep0_out_start(GET_CORE_IF(pcd), pcd);
++}
++
++/**
++ * This functions delegates the setup command to the gadget driver.
++ */
++static inline void do_gadget_setup(dwc_otg_pcd_t * pcd,
++ usb_device_request_t * ctrl)
++{
++ int ret = 0;
++ DWC_SPINUNLOCK(pcd->lock);
++ ret = pcd->fops->setup(pcd, (uint8_t *) ctrl);
++ DWC_SPINLOCK(pcd->lock);
++ if (ret < 0) {
++ ep0_do_stall(pcd, ret);
++ }
++
++ /** @todo This is a g_file_storage gadget driver specific
++ * workaround: a DELAYED_STATUS result from the fsg_setup
++ * routine will result in the gadget queueing a EP0 IN status
++ * phase for a two-stage control transfer. Exactly the same as
++ * a SET_CONFIGURATION/SET_INTERFACE except that this is a class
++ * specific request. Need a generic way to know when the gadget
++ * driver will queue the status phase. Can we assume when we
++ * call the gadget driver setup() function that it will always
++ * queue and require the following flag? Need to look into
++ * this.
++ */
++
++ if (ret == 256 + 999) {
++ pcd->request_config = 1;
++ }
++}
++
++#ifdef DWC_UTE_CFI
++/**
++ * This functions delegates the CFI setup commands to the gadget driver.
++ * This function will return a negative value to indicate a failure.
++ */
++static inline int cfi_gadget_setup(dwc_otg_pcd_t * pcd,
++ struct cfi_usb_ctrlrequest *ctrl_req)
++{
++ int ret = 0;
++
++ if (pcd->fops && pcd->fops->cfi_setup) {
++ DWC_SPINUNLOCK(pcd->lock);
++ ret = pcd->fops->cfi_setup(pcd, ctrl_req);
++ DWC_SPINLOCK(pcd->lock);
++ if (ret < 0) {
++ ep0_do_stall(pcd, ret);
++ return ret;
++ }
++ }
++
++ return ret;
++}
++#endif
++
++/**
++ * This function starts the Zero-Length Packet for the IN status phase
++ * of a 2 stage control transfer.
++ */
++static inline void do_setup_in_status_phase(dwc_otg_pcd_t * pcd)
++{
++ dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
++ if (pcd->ep0state == EP0_STALL) {
++ return;
++ }
++
++ pcd->ep0state = EP0_IN_STATUS_PHASE;
++
++ /* Prepare for more SETUP Packets */
++ DWC_DEBUGPL(DBG_PCD, "EP0 IN ZLP\n");
++ if ((GET_CORE_IF(pcd)->snpsid >= OTG_CORE_REV_3_00a)
++ && (pcd->core_if->dma_desc_enable)
++ && (ep0->dwc_ep.xfer_count < ep0->dwc_ep.total_len)) {
++ DWC_DEBUGPL(DBG_PCDV,
++ "Data terminated wait next packet in out_desc_addr\n");
++ pcd->backup_buf = phys_to_virt(ep0->dwc_ep.dma_addr);
++ pcd->data_terminated = 1;
++ }
++ ep0->dwc_ep.xfer_len = 0;
++ ep0->dwc_ep.xfer_count = 0;
++ ep0->dwc_ep.is_in = 1;
++ ep0->dwc_ep.dma_addr = pcd->setup_pkt_dma_handle;
++ dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep);
++
++ /* Prepare for more SETUP Packets */
++ //ep0_out_start(GET_CORE_IF(pcd), pcd);
++}
++
++/**
++ * This function starts the Zero-Length Packet for the OUT status phase
++ * of a 2 stage control transfer.
++ */
++static inline void do_setup_out_status_phase(dwc_otg_pcd_t * pcd)
++{
++ dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
++ if (pcd->ep0state == EP0_STALL) {
++ DWC_DEBUGPL(DBG_PCD, "EP0 STALLED\n");
++ return;
++ }
++ pcd->ep0state = EP0_OUT_STATUS_PHASE;
++
++ DWC_DEBUGPL(DBG_PCD, "EP0 OUT ZLP\n");
++ ep0->dwc_ep.xfer_len = 0;
++ ep0->dwc_ep.xfer_count = 0;
++ ep0->dwc_ep.is_in = 0;
++ ep0->dwc_ep.dma_addr = pcd->setup_pkt_dma_handle;
++ dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep);
++
++ /* Prepare for more SETUP Packets */
++ if (GET_CORE_IF(pcd)->dma_enable == 0) {
++ ep0_out_start(GET_CORE_IF(pcd), pcd);
++ }
++}
++
++/**
++ * Clear the EP halt (STALL) and if pending requests start the
++ * transfer.
++ */
++static inline void pcd_clear_halt(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep)
++{
++ if (ep->dwc_ep.stall_clear_flag == 0)
++ dwc_otg_ep_clear_stall(GET_CORE_IF(pcd), &ep->dwc_ep);
++
++ /* Reactive the EP */
++ dwc_otg_ep_activate(GET_CORE_IF(pcd), &ep->dwc_ep);
++ if (ep->stopped) {
++ ep->stopped = 0;
++ /* If there is a request in the EP queue start it */
++
++ /** @todo FIXME: this causes an EP mismatch in DMA mode.
++ * epmismatch not yet implemented. */
++
++ /*
++ * Above fixme is solved by implmenting a tasklet to call the
++ * start_next_request(), outside of interrupt context at some
++ * time after the current time, after a clear-halt setup packet.
++ * Still need to implement ep mismatch in the future if a gadget
++ * ever uses more than one endpoint at once
++ */
++ ep->queue_sof = 1;
++ DWC_TASK_SCHEDULE(pcd->start_xfer_tasklet);
++ }
++ /* Start Control Status Phase */
++ do_setup_in_status_phase(pcd);
++}
++
++/**
++ * This function is called when the SET_FEATURE TEST_MODE Setup packet
++ * is sent from the host. The Device Control register is written with
++ * the Test Mode bits set to the specified Test Mode. This is done as
++ * a tasklet so that the "Status" phase of the control transfer
++ * completes before transmitting the TEST packets.
++ *
++ * @todo This has not been tested since the tasklet struct was put
++ * into the PCD struct!
++ *
++ */
++void do_test_mode(void *data)
++{
++ dctl_data_t dctl;
++ dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) data;
++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++ int test_mode = pcd->test_mode;
++
++// DWC_WARN("%s() has not been tested since being rewritten!\n", __func__);
++
++ dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
++ switch (test_mode) {
++ case 1: // TEST_J
++ dctl.b.tstctl = 1;
++ break;
++
++ case 2: // TEST_K
++ dctl.b.tstctl = 2;
++ break;
++
++ case 3: // TEST_SE0_NAK
++ dctl.b.tstctl = 3;
++ break;
++
++ case 4: // TEST_PACKET
++ dctl.b.tstctl = 4;
++ break;
++
++ case 5: // TEST_FORCE_ENABLE
++ dctl.b.tstctl = 5;
++ break;
++ }
++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
++}
++
++/**
++ * This function process the GET_STATUS Setup Commands.
++ */
++static inline void do_get_status(dwc_otg_pcd_t * pcd)
++{
++ usb_device_request_t ctrl = pcd->setup_pkt->req;
++ dwc_otg_pcd_ep_t *ep;
++ dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
++ uint16_t *status = pcd->status_buf;
++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++
++#ifdef DEBUG_EP0
++ DWC_DEBUGPL(DBG_PCD,
++ "GET_STATUS %02x.%02x v%04x i%04x l%04x\n",
++ ctrl.bmRequestType, ctrl.bRequest,
++ UGETW(ctrl.wValue), UGETW(ctrl.wIndex),
++ UGETW(ctrl.wLength));
++#endif
++
++ switch (UT_GET_RECIPIENT(ctrl.bmRequestType)) {
++ case UT_DEVICE:
++ if(UGETW(ctrl.wIndex) == 0xF000) { /* OTG Status selector */
++ DWC_PRINTF("wIndex - %d\n", UGETW(ctrl.wIndex));
++ DWC_PRINTF("OTG VERSION - %d\n", core_if->otg_ver);
++ DWC_PRINTF("OTG CAP - %d, %d\n",
++ core_if->core_params->otg_cap,
++ DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE);
++ if (core_if->otg_ver == 1
++ && core_if->core_params->otg_cap ==
++ DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
++ uint8_t *otgsts = (uint8_t*)pcd->status_buf;
++ *otgsts = (core_if->otg_sts & 0x1);
++ pcd->ep0_pending = 1;
++ ep0->dwc_ep.start_xfer_buff =
++ (uint8_t *) otgsts;
++ ep0->dwc_ep.xfer_buff = (uint8_t *) otgsts;
++ ep0->dwc_ep.dma_addr =
++ pcd->status_buf_dma_handle;
++ ep0->dwc_ep.xfer_len = 1;
++ ep0->dwc_ep.xfer_count = 0;
++ ep0->dwc_ep.total_len = ep0->dwc_ep.xfer_len;
++ dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd),
++ &ep0->dwc_ep);
++ return;
++ } else {
++ ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
++ return;
++ }
++ break;
++ } else {
++ *status = 0x1; /* Self powered */
++ *status |= pcd->remote_wakeup_enable << 1;
++ break;
++ }
++ case UT_INTERFACE:
++ *status = 0;
++ break;
++
++ case UT_ENDPOINT:
++ ep = get_ep_by_addr(pcd, UGETW(ctrl.wIndex));
++ if (ep == 0 || UGETW(ctrl.wLength) > 2) {
++ ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
++ return;
++ }
++ /** @todo check for EP stall */
++ *status = ep->stopped;
++ break;
++ }
++ pcd->ep0_pending = 1;
++ ep0->dwc_ep.start_xfer_buff = (uint8_t *) status;
++ ep0->dwc_ep.xfer_buff = (uint8_t *) status;
++ ep0->dwc_ep.dma_addr = pcd->status_buf_dma_handle;
++ ep0->dwc_ep.xfer_len = 2;
++ ep0->dwc_ep.xfer_count = 0;
++ ep0->dwc_ep.total_len = ep0->dwc_ep.xfer_len;
++ dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep);
++}
++
++/**
++ * This function process the SET_FEATURE Setup Commands.
++ */
++static inline void do_set_feature(dwc_otg_pcd_t * pcd)
++{
++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
++ usb_device_request_t ctrl = pcd->setup_pkt->req;
++ dwc_otg_pcd_ep_t *ep = 0;
++ int32_t otg_cap_param = core_if->core_params->otg_cap;
++ gotgctl_data_t gotgctl = {.d32 = 0 };
++
++ DWC_DEBUGPL(DBG_PCD, "SET_FEATURE:%02x.%02x v%04x i%04x l%04x\n",
++ ctrl.bmRequestType, ctrl.bRequest,
++ UGETW(ctrl.wValue), UGETW(ctrl.wIndex),
++ UGETW(ctrl.wLength));
++ DWC_DEBUGPL(DBG_PCD, "otg_cap=%d\n", otg_cap_param);
++
++ switch (UT_GET_RECIPIENT(ctrl.bmRequestType)) {
++ case UT_DEVICE:
++ switch (UGETW(ctrl.wValue)) {
++ case UF_DEVICE_REMOTE_WAKEUP:
++ pcd->remote_wakeup_enable = 1;
++ break;
++
++ case UF_TEST_MODE:
++ /* Setup the Test Mode tasklet to do the Test
++ * Packet generation after the SETUP Status
++ * phase has completed. */
++
++ /** @todo This has not been tested since the
++ * tasklet struct was put into the PCD
++ * struct! */
++ pcd->test_mode = UGETW(ctrl.wIndex) >> 8;
++ DWC_TASK_SCHEDULE(pcd->test_mode_tasklet);
++ break;
++
++ case UF_DEVICE_B_HNP_ENABLE:
++ DWC_DEBUGPL(DBG_PCDV,
++ "SET_FEATURE: USB_DEVICE_B_HNP_ENABLE\n");
++
++ /* dev may initiate HNP */
++ if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
++ pcd->b_hnp_enable = 1;
++ dwc_otg_pcd_update_otg(pcd, 0);
++ DWC_DEBUGPL(DBG_PCD, "Request B HNP\n");
++ /**@todo Is the gotgctl.devhnpen cleared
++ * by a USB Reset? */
++ gotgctl.b.devhnpen = 1;
++ gotgctl.b.hnpreq = 1;
++ DWC_WRITE_REG32(&global_regs->gotgctl,
++ gotgctl.d32);
++ } else {
++ ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
++ return;
++ }
++ break;
++
++ case UF_DEVICE_A_HNP_SUPPORT:
++ /* RH port supports HNP */
++ DWC_DEBUGPL(DBG_PCDV,
++ "SET_FEATURE: USB_DEVICE_A_HNP_SUPPORT\n");
++ if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
++ pcd->a_hnp_support = 1;
++ dwc_otg_pcd_update_otg(pcd, 0);
++ } else {
++ ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
++ return;
++ }
++ break;
++
++ case UF_DEVICE_A_ALT_HNP_SUPPORT:
++ /* other RH port does */
++ DWC_DEBUGPL(DBG_PCDV,
++ "SET_FEATURE: USB_DEVICE_A_ALT_HNP_SUPPORT\n");
++ if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
++ pcd->a_alt_hnp_support = 1;
++ dwc_otg_pcd_update_otg(pcd, 0);
++ } else {
++ ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
++ return;
++ }
++ break;
++
++ default:
++ ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
++ return;
++
++ }
++ do_setup_in_status_phase(pcd);
++ break;
++
++ case UT_INTERFACE:
++ do_gadget_setup(pcd, &ctrl);
++ break;
++
++ case UT_ENDPOINT:
++ if (UGETW(ctrl.wValue) == UF_ENDPOINT_HALT) {
++ ep = get_ep_by_addr(pcd, UGETW(ctrl.wIndex));
++ if (ep == 0) {
++ ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
++ return;
++ }
++ ep->stopped = 1;
++ dwc_otg_ep_set_stall(core_if, &ep->dwc_ep);
++ }
++ do_setup_in_status_phase(pcd);
++ break;
++ }
++}
++
++/**
++ * This function process the CLEAR_FEATURE Setup Commands.
++ */
++static inline void do_clear_feature(dwc_otg_pcd_t * pcd)
++{
++ usb_device_request_t ctrl = pcd->setup_pkt->req;
++ dwc_otg_pcd_ep_t *ep = 0;
++
++ DWC_DEBUGPL(DBG_PCD,
++ "CLEAR_FEATURE:%02x.%02x v%04x i%04x l%04x\n",
++ ctrl.bmRequestType, ctrl.bRequest,
++ UGETW(ctrl.wValue), UGETW(ctrl.wIndex),
++ UGETW(ctrl.wLength));
++
++ switch (UT_GET_RECIPIENT(ctrl.bmRequestType)) {
++ case UT_DEVICE:
++ switch (UGETW(ctrl.wValue)) {
++ case UF_DEVICE_REMOTE_WAKEUP:
++ pcd->remote_wakeup_enable = 0;
++ break;
++
++ case UF_TEST_MODE:
++ /** @todo Add CLEAR_FEATURE for TEST modes. */
++ break;
++
++ default:
++ ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
++ return;
++ }
++ do_setup_in_status_phase(pcd);
++ break;
++
++ case UT_ENDPOINT:
++ ep = get_ep_by_addr(pcd, UGETW(ctrl.wIndex));
++ if (ep == 0) {
++ ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
++ return;
++ }
++
++ pcd_clear_halt(pcd, ep);
++
++ break;
++ }
++}
++
++/**
++ * This function process the SET_ADDRESS Setup Commands.
++ */
++static inline void do_set_address(dwc_otg_pcd_t * pcd)
++{
++ dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if;
++ usb_device_request_t ctrl = pcd->setup_pkt->req;
++
++ if (ctrl.bmRequestType == UT_DEVICE) {
++ dcfg_data_t dcfg = {.d32 = 0 };
++
++#ifdef DEBUG_EP0
++// DWC_DEBUGPL(DBG_PCDV, "SET_ADDRESS:%d\n", ctrl.wValue);
++#endif
++ dcfg.b.devaddr = UGETW(ctrl.wValue);
++ DWC_MODIFY_REG32(&dev_if->dev_global_regs->dcfg, 0, dcfg.d32);
++ do_setup_in_status_phase(pcd);
++ }
++}
++
++/**
++ * This function processes SETUP commands. In Linux, the USB Command
++ * processing is done in two places - the first being the PCD and the
++ * second in the Gadget Driver (for example, the File-Backed Storage
++ * Gadget Driver).
++ *
++ * <table>
++ * <tr><td>Command </td><td>Driver </td><td>Description</td></tr>
++ *
++ * <tr><td>GET_STATUS </td><td>PCD </td><td>Command is processed as
++ * defined in chapter 9 of the USB 2.0 Specification chapter 9
++ * </td></tr>
++ *
++ * <tr><td>CLEAR_FEATURE </td><td>PCD </td><td>The Device and Endpoint
++ * requests are the ENDPOINT_HALT feature is procesed, all others the
++ * interface requests are ignored.</td></tr>
++ *
++ * <tr><td>SET_FEATURE </td><td>PCD </td><td>The Device and Endpoint
++ * requests are processed by the PCD. Interface requests are passed
++ * to the Gadget Driver.</td></tr>
++ *
++ * <tr><td>SET_ADDRESS </td><td>PCD </td><td>Program the DCFG reg,
++ * with device address received </td></tr>
++ *
++ * <tr><td>GET_DESCRIPTOR </td><td>Gadget Driver </td><td>Return the
++ * requested descriptor</td></tr>
++ *
++ * <tr><td>SET_DESCRIPTOR </td><td>Gadget Driver </td><td>Optional -
++ * not implemented by any of the existing Gadget Drivers.</td></tr>
++ *
++ * <tr><td>SET_CONFIGURATION </td><td>Gadget Driver </td><td>Disable
++ * all EPs and enable EPs for new configuration.</td></tr>
++ *
++ * <tr><td>GET_CONFIGURATION </td><td>Gadget Driver </td><td>Return
++ * the current configuration</td></tr>
++ *
++ * <tr><td>SET_INTERFACE </td><td>Gadget Driver </td><td>Disable all
++ * EPs and enable EPs for new configuration.</td></tr>
++ *
++ * <tr><td>GET_INTERFACE </td><td>Gadget Driver </td><td>Return the
++ * current interface.</td></tr>
++ *
++ * <tr><td>SYNC_FRAME </td><td>PCD </td><td>Display debug
++ * message.</td></tr>
++ * </table>
++ *
++ * When the SETUP Phase Done interrupt occurs, the PCD SETUP commands are
++ * processed by pcd_setup. Calling the Function Driver's setup function from
++ * pcd_setup processes the gadget SETUP commands.
++ */
++static inline void pcd_setup(dwc_otg_pcd_t * pcd)
++{
++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++ dwc_otg_dev_if_t *dev_if = core_if->dev_if;
++ usb_device_request_t ctrl = pcd->setup_pkt->req;
++ dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
++
++ deptsiz0_data_t doeptsize0 = {.d32 = 0 };
++
++#ifdef DWC_UTE_CFI
++ int retval = 0;
++ struct cfi_usb_ctrlrequest cfi_req;
++#endif
++
++ doeptsize0.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[0]->doeptsiz);
++
++ /** In BDMA more then 1 setup packet is not supported till 3.00a */
++ if (core_if->dma_enable && core_if->dma_desc_enable == 0
++ && (doeptsize0.b.supcnt < 2)
++ && (core_if->snpsid < OTG_CORE_REV_2_94a)) {
++ DWC_ERROR
++ ("\n\n----------- CANNOT handle > 1 setup packet in DMA mode\n\n");
++ }
++ if ((core_if->snpsid >= OTG_CORE_REV_3_00a)
++ && (core_if->dma_enable == 1) && (core_if->dma_desc_enable == 0)) {
++ ctrl =
++ (pcd->setup_pkt +
++ (3 - doeptsize0.b.supcnt - 1 +
++ ep0->dwc_ep.stp_rollover))->req;
++ }
++#ifdef DEBUG_EP0
++ DWC_DEBUGPL(DBG_PCD, "SETUP %02x.%02x v%04x i%04x l%04x\n",
++ ctrl.bmRequestType, ctrl.bRequest,
++ UGETW(ctrl.wValue), UGETW(ctrl.wIndex),
++ UGETW(ctrl.wLength));
++#endif
++
++ /* Clean up the request queue */
++ dwc_otg_request_nuke(ep0);
++ ep0->stopped = 0;
++
++ if (ctrl.bmRequestType & UE_DIR_IN) {
++ ep0->dwc_ep.is_in = 1;
++ pcd->ep0state = EP0_IN_DATA_PHASE;
++ } else {
++ ep0->dwc_ep.is_in = 0;
++ pcd->ep0state = EP0_OUT_DATA_PHASE;
++ }
++
++ if (UGETW(ctrl.wLength) == 0) {
++ ep0->dwc_ep.is_in = 1;
++ pcd->ep0state = EP0_IN_STATUS_PHASE;
++ }
++
++ if (UT_GET_TYPE(ctrl.bmRequestType) != UT_STANDARD) {
++
++#ifdef DWC_UTE_CFI
++ DWC_MEMCPY(&cfi_req, &ctrl, sizeof(usb_device_request_t));
++
++ //printk(KERN_ALERT "CFI: req_type=0x%02x; req=0x%02x\n",
++ ctrl.bRequestType, ctrl.bRequest);
++ if (UT_GET_TYPE(cfi_req.bRequestType) == UT_VENDOR) {
++ if (cfi_req.bRequest > 0xB0 && cfi_req.bRequest < 0xBF) {
++ retval = cfi_setup(pcd, &cfi_req);
++ if (retval < 0) {
++ ep0_do_stall(pcd, retval);
++ pcd->ep0_pending = 0;
++ return;
++ }
++
++ /* if need gadget setup then call it and check the retval */
++ if (pcd->cfi->need_gadget_att) {
++ retval =
++ cfi_gadget_setup(pcd,
++ &pcd->
++ cfi->ctrl_req);
++ if (retval < 0) {
++ pcd->ep0_pending = 0;
++ return;
++ }
++ }
++
++ if (pcd->cfi->need_status_in_complete) {
++ do_setup_in_status_phase(pcd);
++ }
++ return;
++ }
++ }
++#endif
++
++ /* handle non-standard (class/vendor) requests in the gadget driver */
++ do_gadget_setup(pcd, &ctrl);
++ return;
++ }
++
++ /** @todo NGS: Handle bad setup packet? */
++
++///////////////////////////////////////////
++//// --- Standard Request handling --- ////
++
++ switch (ctrl.bRequest) {
++ case UR_GET_STATUS:
++ do_get_status(pcd);
++ break;
++
++ case UR_CLEAR_FEATURE:
++ do_clear_feature(pcd);
++ break;
++
++ case UR_SET_FEATURE:
++ do_set_feature(pcd);
++ break;
++
++ case UR_SET_ADDRESS:
++ do_set_address(pcd);
++ break;
++
++ case UR_SET_INTERFACE:
++ case UR_SET_CONFIG:
++// _pcd->request_config = 1; /* Configuration changed */
++ do_gadget_setup(pcd, &ctrl);
++ break;
++
++ case UR_SYNCH_FRAME:
++ do_gadget_setup(pcd, &ctrl);
++ break;
++
++ default:
++ /* Call the Gadget Driver's setup functions */
++ do_gadget_setup(pcd, &ctrl);
++ break;
++ }
++}
++
++/**
++ * This function completes the ep0 control transfer.
++ */
++static int32_t ep0_complete_request(dwc_otg_pcd_ep_t * ep)
++{
++ dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd);
++ dwc_otg_dev_if_t *dev_if = core_if->dev_if;
++ dwc_otg_dev_in_ep_regs_t *in_ep_regs =
++ dev_if->in_ep_regs[ep->dwc_ep.num];
++#ifdef DEBUG_EP0
++ dwc_otg_dev_out_ep_regs_t *out_ep_regs =
++ dev_if->out_ep_regs[ep->dwc_ep.num];
++#endif
++ deptsiz0_data_t deptsiz;
++ dev_dma_desc_sts_t desc_sts;
++ dwc_otg_pcd_request_t *req;
++ int is_last = 0;
++ dwc_otg_pcd_t *pcd = ep->pcd;
++
++#ifdef DWC_UTE_CFI
++ struct cfi_usb_ctrlrequest *ctrlreq;
++ int retval = -DWC_E_NOT_SUPPORTED;
++#endif
++
++ desc_sts.b.bytes = 0;
++
++ if (pcd->ep0_pending && DWC_CIRCLEQ_EMPTY(&ep->queue)) {
++ if (ep->dwc_ep.is_in) {
++#ifdef DEBUG_EP0
++ DWC_DEBUGPL(DBG_PCDV, "Do setup OUT status phase\n");
++#endif
++ do_setup_out_status_phase(pcd);
++ } else {
++#ifdef DEBUG_EP0
++ DWC_DEBUGPL(DBG_PCDV, "Do setup IN status phase\n");
++#endif
++
++#ifdef DWC_UTE_CFI
++ ctrlreq = &pcd->cfi->ctrl_req;
++
++ if (UT_GET_TYPE(ctrlreq->bRequestType) == UT_VENDOR) {
++ if (ctrlreq->bRequest > 0xB0
++ && ctrlreq->bRequest < 0xBF) {
++
++ /* Return if the PCD failed to handle the request */
++ if ((retval =
++ pcd->cfi->ops.
++ ctrl_write_complete(pcd->cfi,
++ pcd)) < 0) {
++ CFI_INFO
++ ("ERROR setting a new value in the PCD(%d)\n",
++ retval);
++ ep0_do_stall(pcd, retval);
++ pcd->ep0_pending = 0;
++ return 0;
++ }
++
++ /* If the gadget needs to be notified on the request */
++ if (pcd->cfi->need_gadget_att == 1) {
++ //retval = do_gadget_setup(pcd, &pcd->cfi->ctrl_req);
++ retval =
++ cfi_gadget_setup(pcd,
++ &pcd->cfi->
++ ctrl_req);
++
++ /* Return from the function if the gadget failed to process
++ * the request properly - this should never happen !!!
++ */
++ if (retval < 0) {
++ CFI_INFO
++ ("ERROR setting a new value in the gadget(%d)\n",
++ retval);
++ pcd->ep0_pending = 0;
++ return 0;
++ }
++ }
++
++ CFI_INFO("%s: RETVAL=%d\n", __func__,
++ retval);
++ /* If we hit here then the PCD and the gadget has properly
++ * handled the request - so send the ZLP IN to the host.
++ */
++ /* @todo: MAS - decide whether we need to start the setup
++ * stage based on the need_setup value of the cfi object
++ */
++ do_setup_in_status_phase(pcd);
++ pcd->ep0_pending = 0;
++ return 1;
++ }
++ }
++#endif
++
++ do_setup_in_status_phase(pcd);
++ }
++ pcd->ep0_pending = 0;
++ return 1;
++ }
++
++ if (DWC_CIRCLEQ_EMPTY(&ep->queue)) {
++ return 0;
++ }
++ req = DWC_CIRCLEQ_FIRST(&ep->queue);
++
++ if (pcd->ep0state == EP0_OUT_STATUS_PHASE
++ || pcd->ep0state == EP0_IN_STATUS_PHASE) {
++ is_last = 1;
++ } else if (ep->dwc_ep.is_in) {
++ deptsiz.d32 = DWC_READ_REG32(&in_ep_regs->dieptsiz);
++ if (core_if->dma_desc_enable != 0)
++ desc_sts = dev_if->in_desc_addr->status;
++#ifdef DEBUG_EP0
++ DWC_DEBUGPL(DBG_PCDV, "%d len=%d xfersize=%d pktcnt=%d\n",
++ ep->dwc_ep.num, ep->dwc_ep.xfer_len,
++ deptsiz.b.xfersize, deptsiz.b.pktcnt);
++#endif
++
++ if (((core_if->dma_desc_enable == 0)
++ && (deptsiz.b.xfersize == 0))
++ || ((core_if->dma_desc_enable != 0)
++ && (desc_sts.b.bytes == 0))) {
++ req->actual = ep->dwc_ep.xfer_count;
++ /* Is a Zero Len Packet needed? */
++ if (req->sent_zlp) {
++#ifdef DEBUG_EP0
++ DWC_DEBUGPL(DBG_PCD, "Setup Rx ZLP\n");
++#endif
++ req->sent_zlp = 0;
++ }
++ do_setup_out_status_phase(pcd);
++ }
++ } else {
++ /* ep0-OUT */
++#ifdef DEBUG_EP0
++ deptsiz.d32 = DWC_READ_REG32(&out_ep_regs->doeptsiz);
++ DWC_DEBUGPL(DBG_PCDV, "%d len=%d xsize=%d pktcnt=%d\n",
++ ep->dwc_ep.num, ep->dwc_ep.xfer_len,
++ deptsiz.b.xfersize, deptsiz.b.pktcnt);
++#endif
++ req->actual = ep->dwc_ep.xfer_count;
++
++ /* Is a Zero Len Packet needed? */
++ if (req->sent_zlp) {
++#ifdef DEBUG_EP0
++ DWC_DEBUGPL(DBG_PCDV, "Setup Tx ZLP\n");
++#endif
++ req->sent_zlp = 0;
++ }
++ /* For older cores do setup in status phase in Slave/BDMA modes,
++ * starting from 3.00 do that only in slave, and for DMA modes
++ * just re-enable ep 0 OUT here*/
++ if (core_if->dma_enable == 0
++ || (core_if->dma_desc_enable == 0
++ && core_if->snpsid <= OTG_CORE_REV_2_94a)) {
++ do_setup_in_status_phase(pcd);
++ } else if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
++ DWC_DEBUGPL(DBG_PCDV,
++ "Enable out ep before in status phase\n");
++ ep0_out_start(core_if, pcd);
++ }
++ }
++
++ /* Complete the request */
++ if (is_last) {
++ dwc_otg_request_done(ep, req, 0);
++ ep->dwc_ep.start_xfer_buff = 0;
++ ep->dwc_ep.xfer_buff = 0;
++ ep->dwc_ep.xfer_len = 0;
++ return 1;
++ }
++ return 0;
++}
++
++#ifdef DWC_UTE_CFI
++/**
++ * This function calculates traverses all the CFI DMA descriptors and
++ * and accumulates the bytes that are left to be transfered.
++ *
++ * @return The total bytes left to transfered, or a negative value as failure
++ */
++static inline int cfi_calc_desc_residue(dwc_otg_pcd_ep_t * ep)
++{
++ int32_t ret = 0;
++ int i;
++ struct dwc_otg_dma_desc *ddesc = NULL;
++ struct cfi_ep *cfiep;
++
++ /* See if the pcd_ep has its respective cfi_ep mapped */
++ cfiep = get_cfi_ep_by_pcd_ep(ep->pcd->cfi, ep);
++ if (!cfiep) {
++ CFI_INFO("%s: Failed to find ep\n", __func__);
++ return -1;
++ }
++
++ ddesc = ep->dwc_ep.descs;
++
++ for (i = 0; (i < cfiep->desc_count) && (i < MAX_DMA_DESCS_PER_EP); i++) {
++
++#if defined(PRINT_CFI_DMA_DESCS)
++ print_desc(ddesc, ep->ep.name, i);
++#endif
++ ret += ddesc->status.b.bytes;
++ ddesc++;
++ }
++
++ if (ret)
++ CFI_INFO("!!!!!!!!!! WARNING (%s) - residue=%d\n", __func__,
++ ret);
++
++ return ret;
++}
++#endif
++
++/**
++ * This function completes the request for the EP. If there are
++ * additional requests for the EP in the queue they will be started.
++ */
++static void complete_ep(dwc_otg_pcd_ep_t * ep)
++{
++ dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd);
++ dwc_otg_dev_if_t *dev_if = core_if->dev_if;
++ dwc_otg_dev_in_ep_regs_t *in_ep_regs =
++ dev_if->in_ep_regs[ep->dwc_ep.num];
++ deptsiz_data_t deptsiz;
++ dev_dma_desc_sts_t desc_sts;
++ dwc_otg_pcd_request_t *req = 0;
++ dwc_otg_dev_dma_desc_t *dma_desc;
++ uint32_t byte_count = 0;
++ int is_last = 0;
++ int i;
++
++ DWC_DEBUGPL(DBG_PCDV, "%s() %d-%s\n", __func__, ep->dwc_ep.num,
++ (ep->dwc_ep.is_in ? "IN" : "OUT"));
++
++ /* Get any pending requests */
++ if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
++ req = DWC_CIRCLEQ_FIRST(&ep->queue);
++ if (!req) {
++ DWC_PRINTF("complete_ep 0x%p, req = NULL!\n", ep);
++ return;
++ }
++ } else {
++ DWC_PRINTF("complete_ep 0x%p, ep->queue empty!\n", ep);
++ return;
++ }
++
++ DWC_DEBUGPL(DBG_PCD, "Requests %d\n", ep->pcd->request_pending);
++
++ if (ep->dwc_ep.is_in) {
++ deptsiz.d32 = DWC_READ_REG32(&in_ep_regs->dieptsiz);
++
++ if (core_if->dma_enable) {
++ if (core_if->dma_desc_enable == 0) {
++ if (deptsiz.b.xfersize == 0
++ && deptsiz.b.pktcnt == 0) {
++ byte_count =
++ ep->dwc_ep.xfer_len -
++ ep->dwc_ep.xfer_count;
++
++ ep->dwc_ep.xfer_buff += byte_count;
++ ep->dwc_ep.dma_addr += byte_count;
++ ep->dwc_ep.xfer_count += byte_count;
++
++ DWC_DEBUGPL(DBG_PCDV,
++ "%d-%s len=%d xfersize=%d pktcnt=%d\n",
++ ep->dwc_ep.num,
++ (ep->dwc_ep.
++ is_in ? "IN" : "OUT"),
++ ep->dwc_ep.xfer_len,
++ deptsiz.b.xfersize,
++ deptsiz.b.pktcnt);
++
++ if (ep->dwc_ep.xfer_len <
++ ep->dwc_ep.total_len) {
++ dwc_otg_ep_start_transfer
++ (core_if, &ep->dwc_ep);
++ } else if (ep->dwc_ep.sent_zlp) {
++ /*
++ * This fragment of code should initiate 0
++ * length transfer in case if it is queued
++ * a transfer with size divisible to EPs max
++ * packet size and with usb_request zero field
++ * is set, which means that after data is transfered,
++ * it is also should be transfered
++ * a 0 length packet at the end. For Slave and
++ * Buffer DMA modes in this case SW has
++ * to initiate 2 transfers one with transfer size,
++ * and the second with 0 size. For Descriptor
++ * DMA mode SW is able to initiate a transfer,
++ * which will handle all the packets including
++ * the last 0 length.
++ */
++ ep->dwc_ep.sent_zlp = 0;
++ dwc_otg_ep_start_zl_transfer
++ (core_if, &ep->dwc_ep);
++ } else {
++ is_last = 1;
++ }
++ } else {
++ if (ep->dwc_ep.type ==
++ DWC_OTG_EP_TYPE_ISOC) {
++ req->actual = 0;
++ dwc_otg_request_done(ep, req, 0);
++
++ ep->dwc_ep.start_xfer_buff = 0;
++ ep->dwc_ep.xfer_buff = 0;
++ ep->dwc_ep.xfer_len = 0;
++
++ /* If there is a request in the queue start it. */
++ start_next_request(ep);
++ } else
++ DWC_WARN
++ ("Incomplete transfer (%d - %s [siz=%d pkt=%d])\n",
++ ep->dwc_ep.num,
++ (ep->dwc_ep.is_in ? "IN" : "OUT"),
++ deptsiz.b.xfersize,
++ deptsiz.b.pktcnt);
++ }
++ } else {
++ dma_desc = ep->dwc_ep.desc_addr;
++ byte_count = 0;
++ ep->dwc_ep.sent_zlp = 0;
++
++#ifdef DWC_UTE_CFI
++ CFI_INFO("%s: BUFFER_MODE=%d\n", __func__,
++ ep->dwc_ep.buff_mode);
++ if (ep->dwc_ep.buff_mode != BM_STANDARD) {
++ int residue;
++
++ residue = cfi_calc_desc_residue(ep);
++ if (residue < 0)
++ return;
++
++ byte_count = residue;
++ } else {
++#endif
++ for (i = 0; i < ep->dwc_ep.desc_cnt;
++ ++i) {
++ desc_sts = dma_desc->status;
++ byte_count += desc_sts.b.bytes;
++ dma_desc++;
++ }
++#ifdef DWC_UTE_CFI
++ }
++#endif
++ if (byte_count == 0) {
++ ep->dwc_ep.xfer_count =
++ ep->dwc_ep.total_len;
++ is_last = 1;
++ } else {
++ DWC_WARN("Incomplete transfer\n");
++ }
++ }
++ } else {
++ if (deptsiz.b.xfersize == 0 && deptsiz.b.pktcnt == 0) {
++ DWC_DEBUGPL(DBG_PCDV,
++ "%d-%s len=%d xfersize=%d pktcnt=%d\n",
++ ep->dwc_ep.num,
++ ep->dwc_ep.is_in ? "IN" : "OUT",
++ ep->dwc_ep.xfer_len,
++ deptsiz.b.xfersize,
++ deptsiz.b.pktcnt);
++
++ /* Check if the whole transfer was completed,
++ * if no, setup transfer for next portion of data
++ */
++ if (ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) {
++ dwc_otg_ep_start_transfer(core_if,
++ &ep->dwc_ep);
++ } else if (ep->dwc_ep.sent_zlp) {
++ /*
++ * This fragment of code should initiate 0
++ * length trasfer in case if it is queued
++ * a trasfer with size divisible to EPs max
++ * packet size and with usb_request zero field
++ * is set, which means that after data is transfered,
++ * it is also should be transfered
++ * a 0 length packet at the end. For Slave and
++ * Buffer DMA modes in this case SW has
++ * to initiate 2 transfers one with transfer size,
++ * and the second with 0 size. For Desriptor
++ * DMA mode SW is able to initiate a transfer,
++ * which will handle all the packets including
++ * the last 0 legth.
++ */
++ ep->dwc_ep.sent_zlp = 0;
++ dwc_otg_ep_start_zl_transfer(core_if,
++ &ep->dwc_ep);
++ } else {
++ is_last = 1;
++ }
++ } else {
++ DWC_WARN
++ ("Incomplete transfer (%d-%s [siz=%d pkt=%d])\n",
++ ep->dwc_ep.num,
++ (ep->dwc_ep.is_in ? "IN" : "OUT"),
++ deptsiz.b.xfersize, deptsiz.b.pktcnt);
++ }
++ }
++ } else {
++ dwc_otg_dev_out_ep_regs_t *out_ep_regs =
++ dev_if->out_ep_regs[ep->dwc_ep.num];
++ desc_sts.d32 = 0;
++ if (core_if->dma_enable) {
++ if (core_if->dma_desc_enable) {
++ dma_desc = ep->dwc_ep.desc_addr;
++ byte_count = 0;
++ ep->dwc_ep.sent_zlp = 0;
++
++#ifdef DWC_UTE_CFI
++ CFI_INFO("%s: BUFFER_MODE=%d\n", __func__,
++ ep->dwc_ep.buff_mode);
++ if (ep->dwc_ep.buff_mode != BM_STANDARD) {
++ int residue;
++ residue = cfi_calc_desc_residue(ep);
++ if (residue < 0)
++ return;
++ byte_count = residue;
++ } else {
++#endif
++
++ for (i = 0; i < ep->dwc_ep.desc_cnt;
++ ++i) {
++ desc_sts = dma_desc->status;
++ byte_count += desc_sts.b.bytes;
++ dma_desc++;
++ }
++
++#ifdef DWC_UTE_CFI
++ }
++#endif
++ /* Checking for interrupt Out transfers with not
++ * dword aligned mps sizes
++ */
++ if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_INTR &&
++ (ep->dwc_ep.maxpacket%4)) {
++ ep->dwc_ep.xfer_count =
++ ep->dwc_ep.total_len - byte_count;
++ if ((ep->dwc_ep.xfer_len %
++ ep->dwc_ep.maxpacket)
++ && (ep->dwc_ep.xfer_len /
++ ep->dwc_ep.maxpacket <
++ MAX_DMA_DESC_CNT))
++ ep->dwc_ep.xfer_len -=
++ (ep->dwc_ep.desc_cnt -
++ 1) * ep->dwc_ep.maxpacket +
++ ep->dwc_ep.xfer_len %
++ ep->dwc_ep.maxpacket;
++ else
++ ep->dwc_ep.xfer_len -=
++ ep->dwc_ep.desc_cnt *
++ ep->dwc_ep.maxpacket;
++ if (ep->dwc_ep.xfer_len > 0) {
++ dwc_otg_ep_start_transfer
++ (core_if, &ep->dwc_ep);
++ } else {
++ is_last = 1;
++ }
++ } else {
++ ep->dwc_ep.xfer_count =
++ ep->dwc_ep.total_len - byte_count +
++ ((4 -
++ (ep->dwc_ep.
++ total_len & 0x3)) & 0x3);
++ is_last = 1;
++ }
++ } else {
++ deptsiz.d32 = 0;
++ deptsiz.d32 =
++ DWC_READ_REG32(&out_ep_regs->doeptsiz);
++
++ byte_count = (ep->dwc_ep.xfer_len -
++ ep->dwc_ep.xfer_count -
++ deptsiz.b.xfersize);
++ ep->dwc_ep.xfer_buff += byte_count;
++ ep->dwc_ep.dma_addr += byte_count;
++ ep->dwc_ep.xfer_count += byte_count;
++
++ /* Check if the whole transfer was completed,
++ * if no, setup transfer for next portion of data
++ */
++ if (ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) {
++ dwc_otg_ep_start_transfer(core_if,
++ &ep->dwc_ep);
++ } else if (ep->dwc_ep.sent_zlp) {
++ /*
++ * This fragment of code should initiate 0
++ * length trasfer in case if it is queued
++ * a trasfer with size divisible to EPs max
++ * packet size and with usb_request zero field
++ * is set, which means that after data is transfered,
++ * it is also should be transfered
++ * a 0 length packet at the end. For Slave and
++ * Buffer DMA modes in this case SW has
++ * to initiate 2 transfers one with transfer size,
++ * and the second with 0 size. For Desriptor
++ * DMA mode SW is able to initiate a transfer,
++ * which will handle all the packets including
++ * the last 0 legth.
++ */
++ ep->dwc_ep.sent_zlp = 0;
++ dwc_otg_ep_start_zl_transfer(core_if,
++ &ep->dwc_ep);
++ } else {
++ is_last = 1;
++ }
++ }
++ } else {
++ /* Check if the whole transfer was completed,
++ * if no, setup transfer for next portion of data
++ */
++ if (ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) {
++ dwc_otg_ep_start_transfer(core_if, &ep->dwc_ep);
++ } else if (ep->dwc_ep.sent_zlp) {
++ /*
++ * This fragment of code should initiate 0
++ * length transfer in case if it is queued
++ * a transfer with size divisible to EPs max
++ * packet size and with usb_request zero field
++ * is set, which means that after data is transfered,
++ * it is also should be transfered
++ * a 0 length packet at the end. For Slave and
++ * Buffer DMA modes in this case SW has
++ * to initiate 2 transfers one with transfer size,
++ * and the second with 0 size. For Descriptor
++ * DMA mode SW is able to initiate a transfer,
++ * which will handle all the packets including
++ * the last 0 length.
++ */
++ ep->dwc_ep.sent_zlp = 0;
++ dwc_otg_ep_start_zl_transfer(core_if,
++ &ep->dwc_ep);
++ } else {
++ is_last = 1;
++ }
++ }
++
++ DWC_DEBUGPL(DBG_PCDV,
++ "addr %p, %d-%s len=%d cnt=%d xsize=%d pktcnt=%d\n",
++ &out_ep_regs->doeptsiz, ep->dwc_ep.num,
++ ep->dwc_ep.is_in ? "IN" : "OUT",
++ ep->dwc_ep.xfer_len, ep->dwc_ep.xfer_count,
++ deptsiz.b.xfersize, deptsiz.b.pktcnt);
++ }
++
++ /* Complete the request */
++ if (is_last) {
++#ifdef DWC_UTE_CFI
++ if (ep->dwc_ep.buff_mode != BM_STANDARD) {
++ req->actual = ep->dwc_ep.cfi_req_len - byte_count;
++ } else {
++#endif
++ req->actual = ep->dwc_ep.xfer_count;
++#ifdef DWC_UTE_CFI
++ }
++#endif
++ if (req->dw_align_buf) {
++ if (!ep->dwc_ep.is_in) {
++ dwc_memcpy(req->buf, req->dw_align_buf, req->length);
++ }
++ DWC_DMA_FREE(req->length, req->dw_align_buf,
++ req->dw_align_buf_dma);
++ }
++
++ dwc_otg_request_done(ep, req, 0);
++
++ ep->dwc_ep.start_xfer_buff = 0;
++ ep->dwc_ep.xfer_buff = 0;
++ ep->dwc_ep.xfer_len = 0;
++
++ /* If there is a request in the queue start it. */
++ start_next_request(ep);
++ }
++}
++
++#ifdef DWC_EN_ISOC
++
++/**
++ * This function BNA interrupt for Isochronous EPs
++ *
++ */
++static void dwc_otg_pcd_handle_iso_bna(dwc_otg_pcd_ep_t * ep)
++{
++ dwc_ep_t *dwc_ep = &ep->dwc_ep;
++ volatile uint32_t *addr;
++ depctl_data_t depctl = {.d32 = 0 };
++ dwc_otg_pcd_t *pcd = ep->pcd;
++ dwc_otg_dev_dma_desc_t *dma_desc;
++ int i;
++
++ dma_desc =
++ dwc_ep->iso_desc_addr + dwc_ep->desc_cnt * (dwc_ep->proc_buf_num);
++
++ if (dwc_ep->is_in) {
++ dev_dma_desc_sts_t sts = {.d32 = 0 };
++ for (i = 0; i < dwc_ep->desc_cnt; ++i, ++dma_desc) {
++ sts.d32 = dma_desc->status.d32;
++ sts.b_iso_in.bs = BS_HOST_READY;
++ dma_desc->status.d32 = sts.d32;
++ }
++ } else {
++ dev_dma_desc_sts_t sts = {.d32 = 0 };
++ for (i = 0; i < dwc_ep->desc_cnt; ++i, ++dma_desc) {
++ sts.d32 = dma_desc->status.d32;
++ sts.b_iso_out.bs = BS_HOST_READY;
++ dma_desc->status.d32 = sts.d32;
++ }
++ }
++
++ if (dwc_ep->is_in == 0) {
++ addr =
++ &GET_CORE_IF(pcd)->dev_if->out_ep_regs[dwc_ep->
++ num]->doepctl;
++ } else {
++ addr =
++ &GET_CORE_IF(pcd)->dev_if->in_ep_regs[dwc_ep->num]->diepctl;
++ }
++ depctl.b.epena = 1;
++ DWC_MODIFY_REG32(addr, depctl.d32, depctl.d32);
++}
++
++/**
++ * This function sets latest iso packet information(non-PTI mode)
++ *
++ * @param core_if Programming view of DWC_otg controller.
++ * @param ep The EP to start the transfer on.
++ *
++ */
++void set_current_pkt_info(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
++{
++ deptsiz_data_t deptsiz = {.d32 = 0 };
++ dma_addr_t dma_addr;
++ uint32_t offset;
++
++ if (ep->proc_buf_num)
++ dma_addr = ep->dma_addr1;
++ else
++ dma_addr = ep->dma_addr0;
++
++ if (ep->is_in) {
++ deptsiz.d32 =
++ DWC_READ_REG32(&core_if->dev_if->
++ in_ep_regs[ep->num]->dieptsiz);
++ offset = ep->data_per_frame;
++ } else {
++ deptsiz.d32 =
++ DWC_READ_REG32(&core_if->dev_if->
++ out_ep_regs[ep->num]->doeptsiz);
++ offset =
++ ep->data_per_frame +
++ (0x4 & (0x4 - (ep->data_per_frame & 0x3)));
++ }
++
++ if (!deptsiz.b.xfersize) {
++ ep->pkt_info[ep->cur_pkt].length = ep->data_per_frame;
++ ep->pkt_info[ep->cur_pkt].offset =
++ ep->cur_pkt_dma_addr - dma_addr;
++ ep->pkt_info[ep->cur_pkt].status = 0;
++ } else {
++ ep->pkt_info[ep->cur_pkt].length = ep->data_per_frame;
++ ep->pkt_info[ep->cur_pkt].offset =
++ ep->cur_pkt_dma_addr - dma_addr;
++ ep->pkt_info[ep->cur_pkt].status = -DWC_E_NO_DATA;
++ }
++ ep->cur_pkt_addr += offset;
++ ep->cur_pkt_dma_addr += offset;
++ ep->cur_pkt++;
++}
++
++/**
++ * This function sets latest iso packet information(DDMA mode)
++ *
++ * @param core_if Programming view of DWC_otg controller.
++ * @param dwc_ep The EP to start the transfer on.
++ *
++ */
++static void set_ddma_iso_pkts_info(dwc_otg_core_if_t * core_if,
++ dwc_ep_t * dwc_ep)
++{
++ dwc_otg_dev_dma_desc_t *dma_desc;
++ dev_dma_desc_sts_t sts = {.d32 = 0 };
++ iso_pkt_info_t *iso_packet;
++ uint32_t data_per_desc;
++ uint32_t offset;
++ int i, j;
++
++ iso_packet = dwc_ep->pkt_info;
++
++ /** Reinit closed DMA Descriptors*/
++ /** ISO OUT EP */
++ if (dwc_ep->is_in == 0) {
++ dma_desc =
++ dwc_ep->iso_desc_addr +
++ dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
++ offset = 0;
++
++ for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
++ i += dwc_ep->pkt_per_frm) {
++ for (j = 0; j < dwc_ep->pkt_per_frm; ++j) {
++ data_per_desc =
++ ((j + 1) * dwc_ep->maxpacket >
++ dwc_ep->
++ data_per_frame) ? dwc_ep->data_per_frame -
++ j * dwc_ep->maxpacket : dwc_ep->maxpacket;
++ data_per_desc +=
++ (data_per_desc % 4) ? (4 -
++ data_per_desc %
++ 4) : 0;
++
++ sts.d32 = dma_desc->status.d32;
++
++ /* Write status in iso_packet_decsriptor */
++ iso_packet->status =
++ sts.b_iso_out.rxsts +
++ (sts.b_iso_out.bs ^ BS_DMA_DONE);
++ if (iso_packet->status) {
++ iso_packet->status = -DWC_E_NO_DATA;
++ }
++
++ /* Received data length */
++ if (!sts.b_iso_out.rxbytes) {
++ iso_packet->length =
++ data_per_desc -
++ sts.b_iso_out.rxbytes;
++ } else {
++ iso_packet->length =
++ data_per_desc -
++ sts.b_iso_out.rxbytes + (4 -
++ dwc_ep->data_per_frame
++ % 4);
++ }
++
++ iso_packet->offset = offset;
++
++ offset += data_per_desc;
++ dma_desc++;
++ iso_packet++;
++ }
++ }
++
++ for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) {
++ data_per_desc =
++ ((j + 1) * dwc_ep->maxpacket >
++ dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
++ j * dwc_ep->maxpacket : dwc_ep->maxpacket;
++ data_per_desc +=
++ (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
++
++ sts.d32 = dma_desc->status.d32;
++
++ /* Write status in iso_packet_decsriptor */
++ iso_packet->status =
++ sts.b_iso_out.rxsts +
++ (sts.b_iso_out.bs ^ BS_DMA_DONE);
++ if (iso_packet->status) {
++ iso_packet->status = -DWC_E_NO_DATA;
++ }
++
++ /* Received data length */
++ iso_packet->length =
++ dwc_ep->data_per_frame - sts.b_iso_out.rxbytes;
++
++ iso_packet->offset = offset;
++
++ offset += data_per_desc;
++ iso_packet++;
++ dma_desc++;
++ }
++
++ sts.d32 = dma_desc->status.d32;
++
++ /* Write status in iso_packet_decsriptor */
++ iso_packet->status =
++ sts.b_iso_out.rxsts + (sts.b_iso_out.bs ^ BS_DMA_DONE);
++ if (iso_packet->status) {
++ iso_packet->status = -DWC_E_NO_DATA;
++ }
++ /* Received data length */
++ if (!sts.b_iso_out.rxbytes) {
++ iso_packet->length =
++ dwc_ep->data_per_frame - sts.b_iso_out.rxbytes;
++ } else {
++ iso_packet->length =
++ dwc_ep->data_per_frame - sts.b_iso_out.rxbytes +
++ (4 - dwc_ep->data_per_frame % 4);
++ }
++
++ iso_packet->offset = offset;
++ } else {
++/** ISO IN EP */
++
++ dma_desc =
++ dwc_ep->iso_desc_addr +
++ dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
++
++ for (i = 0; i < dwc_ep->desc_cnt - 1; i++) {
++ sts.d32 = dma_desc->status.d32;
++
++ /* Write status in iso packet descriptor */
++ iso_packet->status =
++ sts.b_iso_in.txsts +
++ (sts.b_iso_in.bs ^ BS_DMA_DONE);
++ if (iso_packet->status != 0) {
++ iso_packet->status = -DWC_E_NO_DATA;
++
++ }
++ /* Bytes has been transfered */
++ iso_packet->length =
++ dwc_ep->data_per_frame - sts.b_iso_in.txbytes;
++
++ dma_desc++;
++ iso_packet++;
++ }
++
++ sts.d32 = dma_desc->status.d32;
++ while (sts.b_iso_in.bs == BS_DMA_BUSY) {
++ sts.d32 = dma_desc->status.d32;
++ }
++
++ /* Write status in iso packet descriptor ??? do be done with ERROR codes */
++ iso_packet->status =
++ sts.b_iso_in.txsts + (sts.b_iso_in.bs ^ BS_DMA_DONE);
++ if (iso_packet->status != 0) {
++ iso_packet->status = -DWC_E_NO_DATA;
++ }
++
++ /* Bytes has been transfered */
++ iso_packet->length =
++ dwc_ep->data_per_frame - sts.b_iso_in.txbytes;
++ }
++}
++
++/**
++ * This function reinitialize DMA Descriptors for Isochronous transfer
++ *
++ * @param core_if Programming view of DWC_otg controller.
++ * @param dwc_ep The EP to start the transfer on.
++ *
++ */
++static void reinit_ddma_iso_xfer(dwc_otg_core_if_t * core_if, dwc_ep_t * dwc_ep)
++{
++ int i, j;
++ dwc_otg_dev_dma_desc_t *dma_desc;
++ dma_addr_t dma_ad;
++ volatile uint32_t *addr;
++ dev_dma_desc_sts_t sts = {.d32 = 0 };
++ uint32_t data_per_desc;
++
++ if (dwc_ep->is_in == 0) {
++ addr = &core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl;
++ } else {
++ addr = &core_if->dev_if->in_ep_regs[dwc_ep->num]->diepctl;
++ }
++
++ if (dwc_ep->proc_buf_num == 0) {
++ /** Buffer 0 descriptors setup */
++ dma_ad = dwc_ep->dma_addr0;
++ } else {
++ /** Buffer 1 descriptors setup */
++ dma_ad = dwc_ep->dma_addr1;
++ }
++
++ /** Reinit closed DMA Descriptors*/
++ /** ISO OUT EP */
++ if (dwc_ep->is_in == 0) {
++ dma_desc =
++ dwc_ep->iso_desc_addr +
++ dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
++
++ sts.b_iso_out.bs = BS_HOST_READY;
++ sts.b_iso_out.rxsts = 0;
++ sts.b_iso_out.l = 0;
++ sts.b_iso_out.sp = 0;
++ sts.b_iso_out.ioc = 0;
++ sts.b_iso_out.pid = 0;
++ sts.b_iso_out.framenum = 0;
++
++ for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
++ i += dwc_ep->pkt_per_frm) {
++ for (j = 0; j < dwc_ep->pkt_per_frm; ++j) {
++ data_per_desc =
++ ((j + 1) * dwc_ep->maxpacket >
++ dwc_ep->
++ data_per_frame) ? dwc_ep->data_per_frame -
++ j * dwc_ep->maxpacket : dwc_ep->maxpacket;
++ data_per_desc +=
++ (data_per_desc % 4) ? (4 -
++ data_per_desc %
++ 4) : 0;
++ sts.b_iso_out.rxbytes = data_per_desc;
++ dma_desc->buf = dma_ad;
++ dma_desc->status.d32 = sts.d32;
++
++ dma_ad += data_per_desc;
++ dma_desc++;
++ }
++ }
++
++ for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) {
++
++ data_per_desc =
++ ((j + 1) * dwc_ep->maxpacket >
++ dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
++ j * dwc_ep->maxpacket : dwc_ep->maxpacket;
++ data_per_desc +=
++ (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
++ sts.b_iso_out.rxbytes = data_per_desc;
++
++ dma_desc->buf = dma_ad;
++ dma_desc->status.d32 = sts.d32;
++
++ dma_desc++;
++ dma_ad += data_per_desc;
++ }
++
++ sts.b_iso_out.ioc = 1;
++ sts.b_iso_out.l = dwc_ep->proc_buf_num;
++
++ data_per_desc =
++ ((j + 1) * dwc_ep->maxpacket >
++ dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
++ j * dwc_ep->maxpacket : dwc_ep->maxpacket;
++ data_per_desc +=
++ (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
++ sts.b_iso_out.rxbytes = data_per_desc;
++
++ dma_desc->buf = dma_ad;
++ dma_desc->status.d32 = sts.d32;
++ } else {
++/** ISO IN EP */
++
++ dma_desc =
++ dwc_ep->iso_desc_addr +
++ dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
++
++ sts.b_iso_in.bs = BS_HOST_READY;
++ sts.b_iso_in.txsts = 0;
++ sts.b_iso_in.sp = 0;
++ sts.b_iso_in.ioc = 0;
++ sts.b_iso_in.pid = dwc_ep->pkt_per_frm;
++ sts.b_iso_in.framenum = dwc_ep->next_frame;
++ sts.b_iso_in.txbytes = dwc_ep->data_per_frame;
++ sts.b_iso_in.l = 0;
++
++ for (i = 0; i < dwc_ep->desc_cnt - 1; i++) {
++ dma_desc->buf = dma_ad;
++ dma_desc->status.d32 = sts.d32;
++
++ sts.b_iso_in.framenum += dwc_ep->bInterval;
++ dma_ad += dwc_ep->data_per_frame;
++ dma_desc++;
++ }
++
++ sts.b_iso_in.ioc = 1;
++ sts.b_iso_in.l = dwc_ep->proc_buf_num;
++
++ dma_desc->buf = dma_ad;
++ dma_desc->status.d32 = sts.d32;
++
++ dwc_ep->next_frame =
++ sts.b_iso_in.framenum + dwc_ep->bInterval * 1;
++ }
++ dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1;
++}
++
++/**
++ * This function is to handle Iso EP transfer complete interrupt
++ * in case Iso out packet was dropped
++ *
++ * @param core_if Programming view of DWC_otg controller.
++ * @param dwc_ep The EP for wihich transfer complete was asserted
++ *
++ */
++static uint32_t handle_iso_out_pkt_dropped(dwc_otg_core_if_t * core_if,
++ dwc_ep_t * dwc_ep)
++{
++ uint32_t dma_addr;
++ uint32_t drp_pkt;
++ uint32_t drp_pkt_cnt;
++ deptsiz_data_t deptsiz = {.d32 = 0 };
++ depctl_data_t depctl = {.d32 = 0 };
++ int i;
++
++ deptsiz.d32 =
++ DWC_READ_REG32(&core_if->dev_if->
++ out_ep_regs[dwc_ep->num]->doeptsiz);
++
++ drp_pkt = dwc_ep->pkt_cnt - deptsiz.b.pktcnt;
++ drp_pkt_cnt = dwc_ep->pkt_per_frm - (drp_pkt % dwc_ep->pkt_per_frm);
++
++ /* Setting dropped packets status */
++ for (i = 0; i < drp_pkt_cnt; ++i) {
++ dwc_ep->pkt_info[drp_pkt].status = -DWC_E_NO_DATA;
++ drp_pkt++;
++ deptsiz.b.pktcnt--;
++ }
++
++ if (deptsiz.b.pktcnt > 0) {
++ deptsiz.b.xfersize =
++ dwc_ep->xfer_len - (dwc_ep->pkt_cnt -
++ deptsiz.b.pktcnt) * dwc_ep->maxpacket;
++ } else {
++ deptsiz.b.xfersize = 0;
++ deptsiz.b.pktcnt = 0;
++ }
++
++ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doeptsiz,
++ deptsiz.d32);
++
++ if (deptsiz.b.pktcnt > 0) {
++ if (dwc_ep->proc_buf_num) {
++ dma_addr =
++ dwc_ep->dma_addr1 + dwc_ep->xfer_len -
++ deptsiz.b.xfersize;
++ } else {
++ dma_addr =
++ dwc_ep->dma_addr0 + dwc_ep->xfer_len -
++ deptsiz.b.xfersize;;
++ }
++
++ DWC_WRITE_REG32(&core_if->dev_if->
++ out_ep_regs[dwc_ep->num]->doepdma, dma_addr);
++
++ /** Re-enable endpoint, clear nak */
++ depctl.d32 = 0;
++ depctl.b.epena = 1;
++ depctl.b.cnak = 1;
++
++ DWC_MODIFY_REG32(&core_if->dev_if->
++ out_ep_regs[dwc_ep->num]->doepctl, depctl.d32,
++ depctl.d32);
++ return 0;
++ } else {
++ return 1;
++ }
++}
++
++/**
++ * This function sets iso packets information(PTI mode)
++ *
++ * @param core_if Programming view of DWC_otg controller.
++ * @param ep The EP to start the transfer on.
++ *
++ */
++static uint32_t set_iso_pkts_info(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
++{
++ int i, j;
++ dma_addr_t dma_ad;
++ iso_pkt_info_t *packet_info = ep->pkt_info;
++ uint32_t offset;
++ uint32_t frame_data;
++ deptsiz_data_t deptsiz;
++
++ if (ep->proc_buf_num == 0) {
++ /** Buffer 0 descriptors setup */
++ dma_ad = ep->dma_addr0;
++ } else {
++ /** Buffer 1 descriptors setup */
++ dma_ad = ep->dma_addr1;
++ }
++
++ if (ep->is_in) {
++ deptsiz.d32 =
++ DWC_READ_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
++ dieptsiz);
++ } else {
++ deptsiz.d32 =
++ DWC_READ_REG32(&core_if->dev_if->out_ep_regs[ep->num]->
++ doeptsiz);
++ }
++
++ if (!deptsiz.b.xfersize) {
++ offset = 0;
++ for (i = 0; i < ep->pkt_cnt; i += ep->pkt_per_frm) {
++ frame_data = ep->data_per_frame;
++ for (j = 0; j < ep->pkt_per_frm; ++j) {
++
++ /* Packet status - is not set as initially
++ * it is set to 0 and if packet was sent
++ successfully, status field will remain 0*/
++
++ /* Bytes has been transfered */
++ packet_info->length =
++ (ep->maxpacket <
++ frame_data) ? ep->maxpacket : frame_data;
++
++ /* Received packet offset */
++ packet_info->offset = offset;
++ offset += packet_info->length;
++ frame_data -= packet_info->length;
++
++ packet_info++;
++ }
++ }
++ return 1;
++ } else {
++ /* This is a workaround for in case of Transfer Complete with
++ * PktDrpSts interrupts merging - in this case Transfer complete
++ * interrupt for Isoc Out Endpoint is asserted without PktDrpSts
++ * set and with DOEPTSIZ register non zero. Investigations showed,
++ * that this happens when Out packet is dropped, but because of
++ * interrupts merging during first interrupt handling PktDrpSts
++ * bit is cleared and for next merged interrupts it is not reset.
++ * In this case SW hadles the interrupt as if PktDrpSts bit is set.
++ */
++ if (ep->is_in) {
++ return 1;
++ } else {
++ return handle_iso_out_pkt_dropped(core_if, ep);
++ }
++ }
++}
++
++/**
++ * This function is to handle Iso EP transfer complete interrupt
++ *
++ * @param pcd The PCD
++ * @param ep The EP for which transfer complete was asserted
++ *
++ */
++static void complete_iso_ep(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep)
++{
++ dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd);
++ dwc_ep_t *dwc_ep = &ep->dwc_ep;
++ uint8_t is_last = 0;
++
++ if (ep->dwc_ep.next_frame == 0xffffffff) {
++ DWC_WARN("Next frame is not set!\n");
++ return;
++ }
++
++ if (core_if->dma_enable) {
++ if (core_if->dma_desc_enable) {
++ set_ddma_iso_pkts_info(core_if, dwc_ep);
++ reinit_ddma_iso_xfer(core_if, dwc_ep);
++ is_last = 1;
++ } else {
++ if (core_if->pti_enh_enable) {
++ if (set_iso_pkts_info(core_if, dwc_ep)) {
++ dwc_ep->proc_buf_num =
++ (dwc_ep->proc_buf_num ^ 1) & 0x1;
++ dwc_otg_iso_ep_start_buf_transfer
++ (core_if, dwc_ep);
++ is_last = 1;
++ }
++ } else {
++ set_current_pkt_info(core_if, dwc_ep);
++ if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
++ is_last = 1;
++ dwc_ep->cur_pkt = 0;
++ dwc_ep->proc_buf_num =
++ (dwc_ep->proc_buf_num ^ 1) & 0x1;
++ if (dwc_ep->proc_buf_num) {
++ dwc_ep->cur_pkt_addr =
++ dwc_ep->xfer_buff1;
++ dwc_ep->cur_pkt_dma_addr =
++ dwc_ep->dma_addr1;
++ } else {
++ dwc_ep->cur_pkt_addr =
++ dwc_ep->xfer_buff0;
++ dwc_ep->cur_pkt_dma_addr =
++ dwc_ep->dma_addr0;
++ }
++
++ }
++ dwc_otg_iso_ep_start_frm_transfer(core_if,
++ dwc_ep);
++ }
++ }
++ } else {
++ set_current_pkt_info(core_if, dwc_ep);
++ if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
++ is_last = 1;
++ dwc_ep->cur_pkt = 0;
++ dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1;
++ if (dwc_ep->proc_buf_num) {
++ dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff1;
++ dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr1;
++ } else {
++ dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff0;
++ dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr0;
++ }
++
++ }
++ dwc_otg_iso_ep_start_frm_transfer(core_if, dwc_ep);
++ }
++ if (is_last)
++ dwc_otg_iso_buffer_done(pcd, ep, ep->iso_req_handle);
++}
++#endif /* DWC_EN_ISOC */
++
++/**
++ * This function handle BNA interrupt for Non Isochronous EPs
++ *
++ */
++static void dwc_otg_pcd_handle_noniso_bna(dwc_otg_pcd_ep_t * ep)
++{
++ dwc_ep_t *dwc_ep = &ep->dwc_ep;
++ volatile uint32_t *addr;
++ depctl_data_t depctl = {.d32 = 0 };
++ dwc_otg_pcd_t *pcd = ep->pcd;
++ dwc_otg_dev_dma_desc_t *dma_desc;
++ dev_dma_desc_sts_t sts = {.d32 = 0 };
++ dwc_otg_core_if_t *core_if = ep->pcd->core_if;
++ int i, start;
++
++ if (!dwc_ep->desc_cnt)
++ DWC_WARN("Ep%d %s Descriptor count = %d \n", dwc_ep->num,
++ (dwc_ep->is_in ? "IN" : "OUT"), dwc_ep->desc_cnt);
++
++ if (core_if->core_params->cont_on_bna && !dwc_ep->is_in
++ && dwc_ep->type != DWC_OTG_EP_TYPE_CONTROL) {
++ uint32_t doepdma;
++ dwc_otg_dev_out_ep_regs_t *out_regs =
++ core_if->dev_if->out_ep_regs[dwc_ep->num];
++ doepdma = DWC_READ_REG32(&(out_regs->doepdma));
++ start = (doepdma - dwc_ep->dma_desc_addr)/sizeof(dwc_otg_dev_dma_desc_t);
++ dma_desc = &(dwc_ep->desc_addr[start]);
++ } else {
++ start = 0;
++ dma_desc = dwc_ep->desc_addr;
++ }
++
++
++ for (i = start; i < dwc_ep->desc_cnt; ++i, ++dma_desc) {
++ sts.d32 = dma_desc->status.d32;
++ sts.b.bs = BS_HOST_READY;
++ dma_desc->status.d32 = sts.d32;
++ }
++
++ if (dwc_ep->is_in == 0) {
++ addr =
++ &GET_CORE_IF(pcd)->dev_if->out_ep_regs[dwc_ep->num]->
++ doepctl;
++ } else {
++ addr =
++ &GET_CORE_IF(pcd)->dev_if->in_ep_regs[dwc_ep->num]->diepctl;
++ }
++ depctl.b.epena = 1;
++ depctl.b.cnak = 1;
++ DWC_MODIFY_REG32(addr, 0, depctl.d32);
++}
++
++/**
++ * This function handles EP0 Control transfers.
++ *
++ * The state of the control transfers are tracked in
++ * <code>ep0state</code>.
++ */
++static void handle_ep0(dwc_otg_pcd_t * pcd)
++{
++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++ dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
++ dev_dma_desc_sts_t desc_sts;
++ deptsiz0_data_t deptsiz;
++ uint32_t byte_count;
++
++#ifdef DEBUG_EP0
++ DWC_DEBUGPL(DBG_PCDV, "%s()\n", __func__);
++ print_ep0_state(pcd);
++#endif
++
++// DWC_PRINTF("HANDLE EP0\n");
++
++ switch (pcd->ep0state) {
++ case EP0_DISCONNECT:
++ break;
++
++ case EP0_IDLE:
++ pcd->request_config = 0;
++
++ pcd_setup(pcd);
++ break;
++
++ case EP0_IN_DATA_PHASE:
++#ifdef DEBUG_EP0
++ DWC_DEBUGPL(DBG_PCD, "DATA_IN EP%d-%s: type=%d, mps=%d\n",
++ ep0->dwc_ep.num, (ep0->dwc_ep.is_in ? "IN" : "OUT"),
++ ep0->dwc_ep.type, ep0->dwc_ep.maxpacket);
++#endif
++
++ if (core_if->dma_enable != 0) {
++ /*
++ * For EP0 we can only program 1 packet at a time so we
++ * need to do the make calculations after each complete.
++ * Call write_packet to make the calculations, as in
++ * slave mode, and use those values to determine if we
++ * can complete.
++ */
++ if (core_if->dma_desc_enable == 0) {
++ deptsiz.d32 =
++ DWC_READ_REG32(&core_if->
++ dev_if->in_ep_regs[0]->
++ dieptsiz);
++ byte_count =
++ ep0->dwc_ep.xfer_len - deptsiz.b.xfersize;
++ } else {
++ desc_sts =
++ core_if->dev_if->in_desc_addr->status;
++ byte_count =
++ ep0->dwc_ep.xfer_len - desc_sts.b.bytes;
++ }
++ ep0->dwc_ep.xfer_count += byte_count;
++ ep0->dwc_ep.xfer_buff += byte_count;
++ ep0->dwc_ep.dma_addr += byte_count;
++ }
++ if (ep0->dwc_ep.xfer_count < ep0->dwc_ep.total_len) {
++ dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd),
++ &ep0->dwc_ep);
++ DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n");
++ } else if (ep0->dwc_ep.sent_zlp) {
++ dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd),
++ &ep0->dwc_ep);
++ ep0->dwc_ep.sent_zlp = 0;
++ DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER sent zlp\n");
++ } else {
++ ep0_complete_request(ep0);
++ DWC_DEBUGPL(DBG_PCD, "COMPLETE TRANSFER\n");
++ }
++ break;
++ case EP0_OUT_DATA_PHASE:
++#ifdef DEBUG_EP0
++ DWC_DEBUGPL(DBG_PCD, "DATA_OUT EP%d-%s: type=%d, mps=%d\n",
++ ep0->dwc_ep.num, (ep0->dwc_ep.is_in ? "IN" : "OUT"),
++ ep0->dwc_ep.type, ep0->dwc_ep.maxpacket);
++#endif
++ if (core_if->dma_enable != 0) {
++ if (core_if->dma_desc_enable == 0) {
++ deptsiz.d32 =
++ DWC_READ_REG32(&core_if->
++ dev_if->out_ep_regs[0]->
++ doeptsiz);
++ byte_count =
++ ep0->dwc_ep.maxpacket - deptsiz.b.xfersize;
++ } else {
++ desc_sts =
++ core_if->dev_if->out_desc_addr->status;
++ byte_count =
++ ep0->dwc_ep.maxpacket - desc_sts.b.bytes;
++ }
++ ep0->dwc_ep.xfer_count += byte_count;
++ ep0->dwc_ep.xfer_buff += byte_count;
++ ep0->dwc_ep.dma_addr += byte_count;
++ }
++ if (ep0->dwc_ep.xfer_count < ep0->dwc_ep.total_len) {
++ dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd),
++ &ep0->dwc_ep);
++ DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n");
++ } else if (ep0->dwc_ep.sent_zlp) {
++ dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd),
++ &ep0->dwc_ep);
++ ep0->dwc_ep.sent_zlp = 0;
++ DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER sent zlp\n");
++ } else {
++ ep0_complete_request(ep0);
++ DWC_DEBUGPL(DBG_PCD, "COMPLETE TRANSFER\n");
++ }
++ break;
++
++ case EP0_IN_STATUS_PHASE:
++ case EP0_OUT_STATUS_PHASE:
++ DWC_DEBUGPL(DBG_PCD, "CASE: EP0_STATUS\n");
++ ep0_complete_request(ep0);
++ pcd->ep0state = EP0_IDLE;
++ ep0->stopped = 1;
++ ep0->dwc_ep.is_in = 0; /* OUT for next SETUP */
++
++ /* Prepare for more SETUP Packets */
++ if (core_if->dma_enable) {
++ ep0_out_start(core_if, pcd);
++ }
++ break;
++
++ case EP0_STALL:
++ DWC_ERROR("EP0 STALLed, should not get here pcd_setup()\n");
++ break;
++ }
++#ifdef DEBUG_EP0
++ print_ep0_state(pcd);
++#endif
++}
++
++/**
++ * Restart transfer
++ */
++static void restart_transfer(dwc_otg_pcd_t * pcd, const uint32_t epnum)
++{
++ dwc_otg_core_if_t *core_if;
++ dwc_otg_dev_if_t *dev_if;
++ deptsiz_data_t dieptsiz = {.d32 = 0 };
++ dwc_otg_pcd_ep_t *ep;
++
++ ep = get_in_ep(pcd, epnum);
++
++#ifdef DWC_EN_ISOC
++ if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
++ return;
++ }
++#endif /* DWC_EN_ISOC */
++
++ core_if = GET_CORE_IF(pcd);
++ dev_if = core_if->dev_if;
++
++ dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dieptsiz);
++
++ DWC_DEBUGPL(DBG_PCD, "xfer_buff=%p xfer_count=%0x xfer_len=%0x"
++ " stopped=%d\n", ep->dwc_ep.xfer_buff,
++ ep->dwc_ep.xfer_count, ep->dwc_ep.xfer_len, ep->stopped);
++ /*
++ * If xfersize is 0 and pktcnt in not 0, resend the last packet.
++ */
++ if (dieptsiz.b.pktcnt && dieptsiz.b.xfersize == 0 &&
++ ep->dwc_ep.start_xfer_buff != 0) {
++ if (ep->dwc_ep.total_len <= ep->dwc_ep.maxpacket) {
++ ep->dwc_ep.xfer_count = 0;
++ ep->dwc_ep.xfer_buff = ep->dwc_ep.start_xfer_buff;
++ ep->dwc_ep.xfer_len = ep->dwc_ep.xfer_count;
++ } else {
++ ep->dwc_ep.xfer_count -= ep->dwc_ep.maxpacket;
++ /* convert packet size to dwords. */
++ ep->dwc_ep.xfer_buff -= ep->dwc_ep.maxpacket;
++ ep->dwc_ep.xfer_len = ep->dwc_ep.xfer_count;
++ }
++ ep->stopped = 0;
++ DWC_DEBUGPL(DBG_PCD, "xfer_buff=%p xfer_count=%0x "
++ "xfer_len=%0x stopped=%d\n",
++ ep->dwc_ep.xfer_buff,
++ ep->dwc_ep.xfer_count, ep->dwc_ep.xfer_len,
++ ep->stopped);
++ if (epnum == 0) {
++ dwc_otg_ep0_start_transfer(core_if, &ep->dwc_ep);
++ } else {
++ dwc_otg_ep_start_transfer(core_if, &ep->dwc_ep);
++ }
++ }
++}
++
++/*
++ * This function create new nextep sequnce based on Learn Queue.
++ *
++ * @param core_if Programming view of DWC_otg controller
++ */
++void predict_nextep_seq( dwc_otg_core_if_t * core_if)
++{
++ dwc_otg_device_global_regs_t *dev_global_regs =
++ core_if->dev_if->dev_global_regs;
++ const uint32_t TOKEN_Q_DEPTH = core_if->hwcfg2.b.dev_token_q_depth;
++ /* Number of Token Queue Registers */
++ const int DTKNQ_REG_CNT = (TOKEN_Q_DEPTH + 7) / 8;
++ dtknq1_data_t dtknqr1;
++ uint32_t in_tkn_epnums[4];
++ uint8_t seqnum[MAX_EPS_CHANNELS];
++ uint8_t intkn_seq[TOKEN_Q_DEPTH];
++ grstctl_t resetctl = {.d32 = 0 };
++ uint8_t temp;
++ int ndx = 0;
++ int start = 0;
++ int end = 0;
++ int sort_done = 0;
++ int i = 0;
++ volatile uint32_t *addr = &dev_global_regs->dtknqr1;
++
++
++ DWC_DEBUGPL(DBG_PCD,"dev_token_q_depth=%d\n",TOKEN_Q_DEPTH);
++
++ /* Read the DTKNQ Registers */
++ for (i = 0; i < DTKNQ_REG_CNT; i++) {
++ in_tkn_epnums[i] = DWC_READ_REG32(addr);
++ DWC_DEBUGPL(DBG_PCDV, "DTKNQR%d=0x%08x\n", i + 1,
++ in_tkn_epnums[i]);
++ if (addr == &dev_global_regs->dvbusdis) {
++ addr = &dev_global_regs->dtknqr3_dthrctl;
++ } else {
++ ++addr;
++ }
++
++ }
++
++ /* Copy the DTKNQR1 data to the bit field. */
++ dtknqr1.d32 = in_tkn_epnums[0];
++ if (dtknqr1.b.wrap_bit) {
++ ndx = dtknqr1.b.intknwptr;
++ end = ndx -1;
++ if (end < 0)
++ end = TOKEN_Q_DEPTH -1;
++ } else {
++ ndx = 0;
++ end = dtknqr1.b.intknwptr -1;
++ if (end < 0)
++ end = 0;
++ }
++ start = ndx;
++
++ /* Fill seqnum[] by initial values: EP number + 31 */
++ for (i=0; i <= core_if->dev_if->num_in_eps; i++) {
++ seqnum[i] = i +31;
++ }
++
++ /* Fill intkn_seq[] from in_tkn_epnums[0] */
++ for (i=0; i < 6; i++)
++ intkn_seq[i] = (in_tkn_epnums[0] >> ((7-i) * 4)) & 0xf;
++
++ if (TOKEN_Q_DEPTH > 6) {
++ /* Fill intkn_seq[] from in_tkn_epnums[1] */
++ for (i=6; i < 14; i++)
++ intkn_seq[i] =
++ (in_tkn_epnums[1] >> ((7 - (i - 6)) * 4)) & 0xf;
++ }
++
++ if (TOKEN_Q_DEPTH > 14) {
++ /* Fill intkn_seq[] from in_tkn_epnums[1] */
++ for (i=14; i < 22; i++)
++ intkn_seq[i] =
++ (in_tkn_epnums[2] >> ((7 - (i - 14)) * 4)) & 0xf;
++ }
++
++ if (TOKEN_Q_DEPTH > 22) {
++ /* Fill intkn_seq[] from in_tkn_epnums[1] */
++ for (i=22; i < 30; i++)
++ intkn_seq[i] =
++ (in_tkn_epnums[3] >> ((7 - (i - 22)) * 4)) & 0xf;
++ }
++
++ DWC_DEBUGPL(DBG_PCDV, "%s start=%d end=%d intkn_seq[]:\n", __func__,
++ start, end);
++ for (i=0; i<TOKEN_Q_DEPTH; i++)
++ DWC_DEBUGPL(DBG_PCDV,"%d\n", intkn_seq[i]);
++
++ /* Update seqnum based on intkn_seq[] */
++ i = 0;
++ do {
++ seqnum[intkn_seq[ndx]] = i;
++ ndx++;
++ i++;
++ if (ndx == TOKEN_Q_DEPTH)
++ ndx = 0;
++ } while ( i < TOKEN_Q_DEPTH );
++
++ /* Mark non active EP's in seqnum[] by 0xff */
++ for (i=0; i<=core_if->dev_if->num_in_eps; i++) {
++ if (core_if->nextep_seq[i] == 0xff )
++ seqnum[i] = 0xff;
++ }
++
++ /* Sort seqnum[] */
++ sort_done = 0;
++ while (!sort_done) {
++ sort_done = 1;
++ for (i=0; i<core_if->dev_if->num_in_eps; i++) {
++ if (seqnum[i] > seqnum[i+1]) {
++ temp = seqnum[i];
++ seqnum[i] = seqnum[i+1];
++ seqnum[i+1] = temp;
++ sort_done = 0;
++ }
++ }
++ }
++
++ ndx = start + seqnum[0];
++ if (ndx >= TOKEN_Q_DEPTH)
++ ndx = ndx % TOKEN_Q_DEPTH;
++ core_if->first_in_nextep_seq = intkn_seq[ndx];
++
++ /* Update seqnum[] by EP numbers */
++ for (i=0; i<=core_if->dev_if->num_in_eps; i++) {
++ ndx = start + i;
++ if (seqnum[i] < 31) {
++ ndx = start + seqnum[i];
++ if (ndx >= TOKEN_Q_DEPTH)
++ ndx = ndx % TOKEN_Q_DEPTH;
++ seqnum[i] = intkn_seq[ndx];
++ } else {
++ if (seqnum[i] < 0xff) {
++ seqnum[i] = seqnum[i] - 31;
++ } else {
++ break;
++ }
++ }
++ }
++
++ /* Update nextep_seq[] based on seqnum[] */
++ for (i=0; i<core_if->dev_if->num_in_eps; i++) {
++ if (seqnum[i] != 0xff) {
++ if (seqnum[i+1] != 0xff) {
++ core_if->nextep_seq[seqnum[i]] = seqnum[i+1];
++ } else {
++ core_if->nextep_seq[seqnum[i]] = core_if->first_in_nextep_seq;
++ break;
++ }
++ } else {
++ break;
++ }
++ }
++
++ DWC_DEBUGPL(DBG_PCDV, "%s first_in_nextep_seq= %2d; nextep_seq[]:\n",
++ __func__, core_if->first_in_nextep_seq);
++ for (i=0; i <= core_if->dev_if->num_in_eps; i++) {
++ DWC_DEBUGPL(DBG_PCDV,"%2d\n", core_if->nextep_seq[i]);
++ }
++
++ /* Flush the Learning Queue */
++ resetctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->grstctl);
++ resetctl.b.intknqflsh = 1;
++ DWC_WRITE_REG32(&core_if->core_global_regs->grstctl, resetctl.d32);
++
++
++}
++
++/**
++ * handle the IN EP disable interrupt.
++ */
++static inline void handle_in_ep_disable_intr(dwc_otg_pcd_t * pcd,
++ const uint32_t epnum)
++{
++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++ dwc_otg_dev_if_t *dev_if = core_if->dev_if;
++ deptsiz_data_t dieptsiz = {.d32 = 0 };
++ dctl_data_t dctl = {.d32 = 0 };
++ dwc_otg_pcd_ep_t *ep;
++ dwc_ep_t *dwc_ep;
++ gintmsk_data_t gintmsk_data;
++ depctl_data_t depctl;
++ uint32_t diepdma;
++ uint32_t remain_to_transfer = 0;
++ uint8_t i;
++ uint32_t xfer_size;
++
++ ep = get_in_ep(pcd, epnum);
++ dwc_ep = &ep->dwc_ep;
++
++ if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
++ dwc_otg_flush_tx_fifo(core_if, dwc_ep->tx_fifo_num);
++ complete_ep(ep);
++ return;
++ }
++
++ DWC_DEBUGPL(DBG_PCD, "diepctl%d=%0x\n", epnum,
++ DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->diepctl));
++ dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dieptsiz);
++ depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->diepctl);
++
++ DWC_DEBUGPL(DBG_ANY, "pktcnt=%d size=%d\n",
++ dieptsiz.b.pktcnt, dieptsiz.b.xfersize);
++
++ if ((core_if->start_predict == 0) || (depctl.b.eptype & 1)) {
++ if (ep->stopped) {
++ if (core_if->en_multiple_tx_fifo)
++ /* Flush the Tx FIFO */
++ dwc_otg_flush_tx_fifo(core_if, dwc_ep->tx_fifo_num);
++ /* Clear the Global IN NP NAK */
++ dctl.d32 = 0;
++ dctl.b.cgnpinnak = 1;
++ DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);
++ /* Restart the transaction */
++ if (dieptsiz.b.pktcnt != 0 || dieptsiz.b.xfersize != 0) {
++ restart_transfer(pcd, epnum);
++ }
++ } else {
++ /* Restart the transaction */
++ if (dieptsiz.b.pktcnt != 0 || dieptsiz.b.xfersize != 0) {
++ restart_transfer(pcd, epnum);
++ }
++ DWC_DEBUGPL(DBG_ANY, "STOPPED!!!\n");
++ }
++ return;
++ }
++
++ if (core_if->start_predict > 2) { // NP IN EP
++ core_if->start_predict--;
++ return;
++ }
++
++ core_if->start_predict--;
++
++ if (core_if->start_predict == 1) { // All NP IN Ep's disabled now
++
++ predict_nextep_seq(core_if);
++
++ /* Update all active IN EP's NextEP field based of nextep_seq[] */
++ for ( i = 0; i <= core_if->dev_if->num_in_eps; i++) {
++ depctl.d32 =
++ DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
++ if (core_if->nextep_seq[i] != 0xff) { // Active NP IN EP
++ depctl.b.nextep = core_if->nextep_seq[i];
++ DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32);
++ }
++ }
++ /* Flush Shared NP TxFIFO */
++ dwc_otg_flush_tx_fifo(core_if, 0);
++ /* Rewind buffers */
++ if (!core_if->dma_desc_enable) {
++ i = core_if->first_in_nextep_seq;
++ do {
++ ep = get_in_ep(pcd, i);
++ dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->dieptsiz);
++ xfer_size = ep->dwc_ep.total_len - ep->dwc_ep.xfer_count;
++ if (xfer_size > ep->dwc_ep.maxxfer)
++ xfer_size = ep->dwc_ep.maxxfer;
++ depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
++ if (dieptsiz.b.pktcnt != 0) {
++ if (xfer_size == 0) {
++ remain_to_transfer = 0;
++ } else {
++ if ((xfer_size % ep->dwc_ep.maxpacket) == 0) {
++ remain_to_transfer =
++ dieptsiz.b.pktcnt * ep->dwc_ep.maxpacket;
++ } else {
++ remain_to_transfer = ((dieptsiz.b.pktcnt -1) * ep->dwc_ep.maxpacket)
++ + (xfer_size % ep->dwc_ep.maxpacket);
++ }
++ }
++ diepdma = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepdma);
++ dieptsiz.b.xfersize = remain_to_transfer;
++ DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->dieptsiz, dieptsiz.d32);
++ diepdma = ep->dwc_ep.dma_addr + (xfer_size - remain_to_transfer);
++ DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepdma, diepdma);
++ }
++ i = core_if->nextep_seq[i];
++ } while (i != core_if->first_in_nextep_seq);
++ } else { // dma_desc_enable
++ DWC_PRINTF("%s Learning Queue not supported in DDMA\n", __func__);
++ }
++
++ /* Restart transfers in predicted sequences */
++ i = core_if->first_in_nextep_seq;
++ do {
++ dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->dieptsiz);
++ depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
++ if (dieptsiz.b.pktcnt != 0) {
++ depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
++ depctl.b.epena = 1;
++ depctl.b.cnak = 1;
++ DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32);
++ }
++ i = core_if->nextep_seq[i];
++ } while (i != core_if->first_in_nextep_seq);
++
++ /* Clear the global non-periodic IN NAK handshake */
++ dctl.d32 = 0;
++ dctl.b.cgnpinnak = 1;
++ DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);
++
++ /* Unmask EP Mismatch interrupt */
++ gintmsk_data.d32 = 0;
++ gintmsk_data.b.epmismatch = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0, gintmsk_data.d32);
++
++ core_if->start_predict = 0;
++
++ }
++}
++
++/**
++ * Handler for the IN EP timeout handshake interrupt.
++ */
++static inline void handle_in_ep_timeout_intr(dwc_otg_pcd_t * pcd,
++ const uint32_t epnum)
++{
++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++ dwc_otg_dev_if_t *dev_if = core_if->dev_if;
++
++#ifdef DEBUG
++ deptsiz_data_t dieptsiz = {.d32 = 0 };
++ uint32_t num = 0;
++#endif
++ dctl_data_t dctl = {.d32 = 0 };
++ dwc_otg_pcd_ep_t *ep;
++
++ gintmsk_data_t intr_mask = {.d32 = 0 };
++
++ ep = get_in_ep(pcd, epnum);
++
++ /* Disable the NP Tx Fifo Empty Interrrupt */
++ if (!core_if->dma_enable) {
++ intr_mask.b.nptxfempty = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk,
++ intr_mask.d32, 0);
++ }
++ /** @todo NGS Check EP type.
++ * Implement for Periodic EPs */
++ /*
++ * Non-periodic EP
++ */
++ /* Enable the Global IN NAK Effective Interrupt */
++ intr_mask.b.ginnakeff = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0, intr_mask.d32);
++
++ /* Set Global IN NAK */
++ dctl.b.sgnpinnak = 1;
++ DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);
++
++ ep->stopped = 1;
++
++#ifdef DEBUG
++ dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[num]->dieptsiz);
++ DWC_DEBUGPL(DBG_ANY, "pktcnt=%d size=%d\n",
++ dieptsiz.b.pktcnt, dieptsiz.b.xfersize);
++#endif
++
++#ifdef DISABLE_PERIODIC_EP
++ /*
++ * Set the NAK bit for this EP to
++ * start the disable process.
++ */
++ diepctl.d32 = 0;
++ diepctl.b.snak = 1;
++ DWC_MODIFY_REG32(&dev_if->in_ep_regs[num]->diepctl, diepctl.d32,
++ diepctl.d32);
++ ep->disabling = 1;
++ ep->stopped = 1;
++#endif
++}
++
++/**
++ * Handler for the IN EP NAK interrupt.
++ */
++static inline int32_t handle_in_ep_nak_intr(dwc_otg_pcd_t * pcd,
++ const uint32_t epnum)
++{
++ /** @todo implement ISR */
++ dwc_otg_core_if_t *core_if;
++ diepmsk_data_t intr_mask = {.d32 = 0 };
++
++ DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "IN EP NAK");
++ core_if = GET_CORE_IF(pcd);
++ intr_mask.b.nak = 1;
++
++ if (core_if->multiproc_int_enable) {
++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
++ diepeachintmsk[epnum], intr_mask.d32, 0);
++ } else {
++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->diepmsk,
++ intr_mask.d32, 0);
++ }
++
++ return 1;
++}
++
++/**
++ * Handler for the OUT EP Babble interrupt.
++ */
++static inline int32_t handle_out_ep_babble_intr(dwc_otg_pcd_t * pcd,
++ const uint32_t epnum)
++{
++ /** @todo implement ISR */
++ dwc_otg_core_if_t *core_if;
++ doepmsk_data_t intr_mask = {.d32 = 0 };
++
++ DWC_PRINTF("INTERRUPT Handler not implemented for %s\n",
++ "OUT EP Babble");
++ core_if = GET_CORE_IF(pcd);
++ intr_mask.b.babble = 1;
++
++ if (core_if->multiproc_int_enable) {
++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
++ doepeachintmsk[epnum], intr_mask.d32, 0);
++ } else {
++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->doepmsk,
++ intr_mask.d32, 0);
++ }
++
++ return 1;
++}
++
++/**
++ * Handler for the OUT EP NAK interrupt.
++ */
++static inline int32_t handle_out_ep_nak_intr(dwc_otg_pcd_t * pcd,
++ const uint32_t epnum)
++{
++ /** @todo implement ISR */
++ dwc_otg_core_if_t *core_if;
++ doepmsk_data_t intr_mask = {.d32 = 0 };
++
++ DWC_DEBUGPL(DBG_ANY, "INTERRUPT Handler not implemented for %s\n", "OUT EP NAK");
++ core_if = GET_CORE_IF(pcd);
++ intr_mask.b.nak = 1;
++
++ if (core_if->multiproc_int_enable) {
++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
++ doepeachintmsk[epnum], intr_mask.d32, 0);
++ } else {
++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->doepmsk,
++ intr_mask.d32, 0);
++ }
++
++ return 1;
++}
++
++/**
++ * Handler for the OUT EP NYET interrupt.
++ */
++static inline int32_t handle_out_ep_nyet_intr(dwc_otg_pcd_t * pcd,
++ const uint32_t epnum)
++{
++ /** @todo implement ISR */
++ dwc_otg_core_if_t *core_if;
++ doepmsk_data_t intr_mask = {.d32 = 0 };
++
++ DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "OUT EP NYET");
++ core_if = GET_CORE_IF(pcd);
++ intr_mask.b.nyet = 1;
++
++ if (core_if->multiproc_int_enable) {
++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
++ doepeachintmsk[epnum], intr_mask.d32, 0);
++ } else {
++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->doepmsk,
++ intr_mask.d32, 0);
++ }
++
++ return 1;
++}
++
++/**
++ * This interrupt indicates that an IN EP has a pending Interrupt.
++ * The sequence for handling the IN EP interrupt is shown below:
++ * -# Read the Device All Endpoint Interrupt register
++ * -# Repeat the following for each IN EP interrupt bit set (from
++ * LSB to MSB).
++ * -# Read the Device Endpoint Interrupt (DIEPINTn) register
++ * -# If "Transfer Complete" call the request complete function
++ * -# If "Endpoint Disabled" complete the EP disable procedure.
++ * -# If "AHB Error Interrupt" log error
++ * -# If "Time-out Handshake" log error
++ * -# If "IN Token Received when TxFIFO Empty" write packet to Tx
++ * FIFO.
++ * -# If "IN Token EP Mismatch" (disable, this is handled by EP
++ * Mismatch Interrupt)
++ */
++static int32_t dwc_otg_pcd_handle_in_ep_intr(dwc_otg_pcd_t * pcd)
++{
++#define CLEAR_IN_EP_INTR(__core_if,__epnum,__intr) \
++do { \
++ diepint_data_t diepint = {.d32=0}; \
++ diepint.b.__intr = 1; \
++ DWC_WRITE_REG32(&__core_if->dev_if->in_ep_regs[__epnum]->diepint, \
++ diepint.d32); \
++} while (0)
++
++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++ dwc_otg_dev_if_t *dev_if = core_if->dev_if;
++ diepint_data_t diepint = {.d32 = 0 };
++ depctl_data_t depctl = {.d32 = 0 };
++ uint32_t ep_intr;
++ uint32_t epnum = 0;
++ dwc_otg_pcd_ep_t *ep;
++ dwc_ep_t *dwc_ep;
++ gintmsk_data_t intr_mask = {.d32 = 0 };
++
++ DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, pcd);
++
++ /* Read in the device interrupt bits */
++ ep_intr = dwc_otg_read_dev_all_in_ep_intr(core_if);
++
++ /* Service the Device IN interrupts for each endpoint */
++ while (ep_intr) {
++ if (ep_intr & 0x1) {
++ uint32_t empty_msk;
++ /* Get EP pointer */
++ ep = get_in_ep(pcd, epnum);
++ dwc_ep = &ep->dwc_ep;
++
++ depctl.d32 =
++ DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->diepctl);
++ empty_msk =
++ DWC_READ_REG32(&dev_if->
++ dev_global_regs->dtknqr4_fifoemptymsk);
++
++ DWC_DEBUGPL(DBG_PCDV,
++ "IN EP INTERRUPT - %d\nepmty_msk - %8x diepctl - %8x\n",
++ epnum, empty_msk, depctl.d32);
++
++ DWC_DEBUGPL(DBG_PCD,
++ "EP%d-%s: type=%d, mps=%d\n",
++ dwc_ep->num, (dwc_ep->is_in ? "IN" : "OUT"),
++ dwc_ep->type, dwc_ep->maxpacket);
++
++ diepint.d32 =
++ dwc_otg_read_dev_in_ep_intr(core_if, dwc_ep);
++
++ DWC_DEBUGPL(DBG_PCDV,
++ "EP %d Interrupt Register - 0x%x\n", epnum,
++ diepint.d32);
++ /* Transfer complete */
++ if (diepint.b.xfercompl) {
++ /* Disable the NP Tx FIFO Empty
++ * Interrupt */
++ if (core_if->en_multiple_tx_fifo == 0) {
++ intr_mask.b.nptxfempty = 1;
++ DWC_MODIFY_REG32
++ (&core_if->core_global_regs->gintmsk,
++ intr_mask.d32, 0);
++ } else {
++ /* Disable the Tx FIFO Empty Interrupt for this EP */
++ uint32_t fifoemptymsk =
++ 0x1 << dwc_ep->num;
++ DWC_MODIFY_REG32(&core_if->
++ dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
++ fifoemptymsk, 0);
++ }
++ /* Clear the bit in DIEPINTn for this interrupt */
++ CLEAR_IN_EP_INTR(core_if, epnum, xfercompl);
++
++ /* Complete the transfer */
++ if (epnum == 0) {
++ handle_ep0(pcd);
++ }
++#ifdef DWC_EN_ISOC
++ else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
++ if (!ep->stopped)
++ complete_iso_ep(pcd, ep);
++ }
++#endif /* DWC_EN_ISOC */
++#ifdef DWC_UTE_PER_IO
++ else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
++ if (!ep->stopped)
++ complete_xiso_ep(ep);
++ }
++#endif /* DWC_UTE_PER_IO */
++ else {
++ if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC &&
++ dwc_ep->bInterval > 1) {
++ dwc_ep->frame_num += dwc_ep->bInterval;
++ if (dwc_ep->frame_num > 0x3FFF)
++ {
++ dwc_ep->frm_overrun = 1;
++ dwc_ep->frame_num &= 0x3FFF;
++ } else
++ dwc_ep->frm_overrun = 0;
++ }
++ complete_ep(ep);
++ if(diepint.b.nak)
++ CLEAR_IN_EP_INTR(core_if, epnum, nak);
++ }
++ }
++ /* Endpoint disable */
++ if (diepint.b.epdisabled) {
++ DWC_DEBUGPL(DBG_ANY, "EP%d IN disabled\n",
++ epnum);
++ handle_in_ep_disable_intr(pcd, epnum);
++
++ /* Clear the bit in DIEPINTn for this interrupt */
++ CLEAR_IN_EP_INTR(core_if, epnum, epdisabled);
++ }
++ /* AHB Error */
++ if (diepint.b.ahberr) {
++ DWC_ERROR("EP%d IN AHB Error\n", epnum);
++ /* Clear the bit in DIEPINTn for this interrupt */
++ CLEAR_IN_EP_INTR(core_if, epnum, ahberr);
++ }
++ /* TimeOUT Handshake (non-ISOC IN EPs) */
++ if (diepint.b.timeout) {
++ DWC_ERROR("EP%d IN Time-out\n", epnum);
++ handle_in_ep_timeout_intr(pcd, epnum);
++
++ CLEAR_IN_EP_INTR(core_if, epnum, timeout);
++ }
++ /** IN Token received with TxF Empty */
++ if (diepint.b.intktxfemp) {
++ DWC_DEBUGPL(DBG_ANY,
++ "EP%d IN TKN TxFifo Empty\n",
++ epnum);
++ if (!ep->stopped && epnum != 0) {
++
++ diepmsk_data_t diepmsk = {.d32 = 0 };
++ diepmsk.b.intktxfemp = 1;
++
++ if (core_if->multiproc_int_enable) {
++ DWC_MODIFY_REG32
++ (&dev_if->dev_global_regs->diepeachintmsk
++ [epnum], diepmsk.d32, 0);
++ } else {
++ DWC_MODIFY_REG32
++ (&dev_if->dev_global_regs->diepmsk,
++ diepmsk.d32, 0);
++ }
++ } else if (core_if->dma_desc_enable
++ && epnum == 0
++ && pcd->ep0state ==
++ EP0_OUT_STATUS_PHASE) {
++ // EP0 IN set STALL
++ depctl.d32 =
++ DWC_READ_REG32(&dev_if->in_ep_regs
++ [epnum]->diepctl);
++
++ /* set the disable and stall bits */
++ if (depctl.b.epena) {
++ depctl.b.epdis = 1;
++ }
++ depctl.b.stall = 1;
++ DWC_WRITE_REG32(&dev_if->in_ep_regs
++ [epnum]->diepctl,
++ depctl.d32);
++ }
++ CLEAR_IN_EP_INTR(core_if, epnum, intktxfemp);
++ }
++ /** IN Token Received with EP mismatch */
++ if (diepint.b.intknepmis) {
++ DWC_DEBUGPL(DBG_ANY,
++ "EP%d IN TKN EP Mismatch\n", epnum);
++ CLEAR_IN_EP_INTR(core_if, epnum, intknepmis);
++ }
++ /** IN Endpoint NAK Effective */
++ if (diepint.b.inepnakeff) {
++ DWC_DEBUGPL(DBG_ANY,
++ "EP%d IN EP NAK Effective\n",
++ epnum);
++ /* Periodic EP */
++ if (ep->disabling) {
++ depctl.d32 = 0;
++ depctl.b.snak = 1;
++ depctl.b.epdis = 1;
++ DWC_MODIFY_REG32(&dev_if->in_ep_regs
++ [epnum]->diepctl,
++ depctl.d32,
++ depctl.d32);
++ }
++ CLEAR_IN_EP_INTR(core_if, epnum, inepnakeff);
++
++ }
++
++ /** IN EP Tx FIFO Empty Intr */
++ if (diepint.b.emptyintr) {
++ DWC_DEBUGPL(DBG_ANY,
++ "EP%d Tx FIFO Empty Intr \n",
++ epnum);
++ write_empty_tx_fifo(pcd, epnum);
++
++ CLEAR_IN_EP_INTR(core_if, epnum, emptyintr);
++
++ }
++
++ /** IN EP BNA Intr */
++ if (diepint.b.bna) {
++ CLEAR_IN_EP_INTR(core_if, epnum, bna);
++ if (core_if->dma_desc_enable) {
++#ifdef DWC_EN_ISOC
++ if (dwc_ep->type ==
++ DWC_OTG_EP_TYPE_ISOC) {
++ /*
++ * This checking is performed to prevent first "false" BNA
++ * handling occuring right after reconnect
++ */
++ if (dwc_ep->next_frame !=
++ 0xffffffff)
++ dwc_otg_pcd_handle_iso_bna(ep);
++ } else
++#endif /* DWC_EN_ISOC */
++ {
++ dwc_otg_pcd_handle_noniso_bna(ep);
++ }
++ }
++ }
++ /* NAK Interrutp */
++ if (diepint.b.nak) {
++ DWC_DEBUGPL(DBG_ANY, "EP%d IN NAK Interrupt\n",
++ epnum);
++ if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
++ depctl_data_t depctl;
++ if (ep->dwc_ep.frame_num == 0xFFFFFFFF) {
++ ep->dwc_ep.frame_num = core_if->frame_num;
++ if (ep->dwc_ep.bInterval > 1) {
++ depctl.d32 = 0;
++ depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->diepctl);
++ if (ep->dwc_ep.frame_num & 0x1) {
++ depctl.b.setd1pid = 1;
++ depctl.b.setd0pid = 0;
++ } else {
++ depctl.b.setd0pid = 1;
++ depctl.b.setd1pid = 0;
++ }
++ DWC_WRITE_REG32(&dev_if->in_ep_regs[epnum]->diepctl, depctl.d32);
++ }
++ start_next_request(ep);
++ }
++ ep->dwc_ep.frame_num += ep->dwc_ep.bInterval;
++ if (dwc_ep->frame_num > 0x3FFF) {
++ dwc_ep->frm_overrun = 1;
++ dwc_ep->frame_num &= 0x3FFF;
++ } else
++ dwc_ep->frm_overrun = 0;
++ }
++
++ CLEAR_IN_EP_INTR(core_if, epnum, nak);
++ }
++ }
++ epnum++;
++ ep_intr >>= 1;
++ }
++
++ return 1;
++#undef CLEAR_IN_EP_INTR
++}
++
++/**
++ * This interrupt indicates that an OUT EP has a pending Interrupt.
++ * The sequence for handling the OUT EP interrupt is shown below:
++ * -# Read the Device All Endpoint Interrupt register
++ * -# Repeat the following for each OUT EP interrupt bit set (from
++ * LSB to MSB).
++ * -# Read the Device Endpoint Interrupt (DOEPINTn) register
++ * -# If "Transfer Complete" call the request complete function
++ * -# If "Endpoint Disabled" complete the EP disable procedure.
++ * -# If "AHB Error Interrupt" log error
++ * -# If "Setup Phase Done" process Setup Packet (See Standard USB
++ * Command Processing)
++ */
++static int32_t dwc_otg_pcd_handle_out_ep_intr(dwc_otg_pcd_t * pcd)
++{
++#define CLEAR_OUT_EP_INTR(__core_if,__epnum,__intr) \
++do { \
++ doepint_data_t doepint = {.d32=0}; \
++ doepint.b.__intr = 1; \
++ DWC_WRITE_REG32(&__core_if->dev_if->out_ep_regs[__epnum]->doepint, \
++ doepint.d32); \
++} while (0)
++
++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++ uint32_t ep_intr;
++ doepint_data_t doepint = {.d32 = 0 };
++ uint32_t epnum = 0;
++ dwc_otg_pcd_ep_t *ep;
++ dwc_ep_t *dwc_ep;
++ dctl_data_t dctl = {.d32 = 0 };
++ gintmsk_data_t gintmsk = {.d32 = 0 };
++
++
++ DWC_DEBUGPL(DBG_PCDV, "%s()\n", __func__);
++
++ /* Read in the device interrupt bits */
++ ep_intr = dwc_otg_read_dev_all_out_ep_intr(core_if);
++
++ while (ep_intr) {
++ if (ep_intr & 0x1) {
++ /* Get EP pointer */
++ ep = get_out_ep(pcd, epnum);
++ dwc_ep = &ep->dwc_ep;
++
++#ifdef VERBOSE
++ DWC_DEBUGPL(DBG_PCDV,
++ "EP%d-%s: type=%d, mps=%d\n",
++ dwc_ep->num, (dwc_ep->is_in ? "IN" : "OUT"),
++ dwc_ep->type, dwc_ep->maxpacket);
++#endif
++ doepint.d32 =
++ dwc_otg_read_dev_out_ep_intr(core_if, dwc_ep);
++ /* Moved this interrupt upper due to core deffect of asserting
++ * OUT EP 0 xfercompl along with stsphsrcvd in BDMA */
++ if (doepint.b.stsphsercvd) {
++ deptsiz0_data_t deptsiz;
++ CLEAR_OUT_EP_INTR(core_if, epnum, stsphsercvd);
++ deptsiz.d32 =
++ DWC_READ_REG32(&core_if->dev_if->
++ out_ep_regs[0]->doeptsiz);
++ if (core_if->snpsid >= OTG_CORE_REV_3_00a
++ && core_if->dma_enable
++ && core_if->dma_desc_enable == 0
++ && doepint.b.xfercompl
++ && deptsiz.b.xfersize == 24) {
++ CLEAR_OUT_EP_INTR(core_if, epnum,
++ xfercompl);
++ doepint.b.xfercompl = 0;
++ ep0_out_start(core_if, pcd);
++ }
++ if ((core_if->dma_desc_enable) ||
++ (core_if->dma_enable
++ && core_if->snpsid >=
++ OTG_CORE_REV_3_00a)) {
++ do_setup_in_status_phase(pcd);
++ }
++ }
++ /* Transfer complete */
++ if (doepint.b.xfercompl) {
++
++ if (epnum == 0) {
++ /* Clear the bit in DOEPINTn for this interrupt */
++ CLEAR_OUT_EP_INTR(core_if, epnum, xfercompl);
++ if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
++ DWC_DEBUGPL(DBG_PCDV, "DOEPINT=%x doepint=%x\n",
++ DWC_READ_REG32(&core_if->dev_if->out_ep_regs[0]->doepint),
++ doepint.d32);
++ DWC_DEBUGPL(DBG_PCDV, "DOEPCTL=%x \n",
++ DWC_READ_REG32(&core_if->dev_if->out_ep_regs[0]->doepctl));
++
++ if (core_if->snpsid >= OTG_CORE_REV_3_00a
++ && core_if->dma_enable == 0) {
++ doepint_data_t doepint;
++ doepint.d32 = DWC_READ_REG32(&core_if->dev_if->
++ out_ep_regs[0]->doepint);
++ if (pcd->ep0state == EP0_IDLE && doepint.b.sr) {
++ CLEAR_OUT_EP_INTR(core_if, epnum, sr);
++ goto exit_xfercompl;
++ }
++ }
++ /* In case of DDMA look at SR bit to go to the Data Stage */
++ if (core_if->dma_desc_enable) {
++ dev_dma_desc_sts_t status = {.d32 = 0};
++ if (pcd->ep0state == EP0_IDLE) {
++ status.d32 = core_if->dev_if->setup_desc_addr[core_if->
++ dev_if->setup_desc_index]->status.d32;
++ if(pcd->data_terminated) {
++ pcd->data_terminated = 0;
++ status.d32 = core_if->dev_if->out_desc_addr->status.d32;
++ dwc_memcpy(&pcd->setup_pkt->req, pcd->backup_buf, 8);
++ }
++ if (status.b.sr) {
++ if (doepint.b.setup) {
++ DWC_DEBUGPL(DBG_PCDV, "DMA DESC EP0_IDLE SR=1 setup=1\n");
++ /* Already started data stage, clear setup */
++ CLEAR_OUT_EP_INTR(core_if, epnum, setup);
++ doepint.b.setup = 0;
++ handle_ep0(pcd);
++ /* Prepare for more setup packets */
++ if (pcd->ep0state == EP0_IN_STATUS_PHASE ||
++ pcd->ep0state == EP0_IN_DATA_PHASE) {
++ ep0_out_start(core_if, pcd);
++ }
++
++ goto exit_xfercompl;
++ } else {
++ /* Prepare for more setup packets */
++ DWC_DEBUGPL(DBG_PCDV,
++ "EP0_IDLE SR=1 setup=0 new setup comes\n");
++ ep0_out_start(core_if, pcd);
++ }
++ }
++ } else {
++ dwc_otg_pcd_request_t *req;
++ dev_dma_desc_sts_t status = {.d32 = 0};
++ diepint_data_t diepint0;
++ diepint0.d32 = DWC_READ_REG32(&core_if->dev_if->
++ in_ep_regs[0]->diepint);
++
++ if (pcd->ep0state == EP0_STALL || pcd->ep0state == EP0_DISCONNECT) {
++ DWC_ERROR("EP0 is stalled/disconnected\n");
++ }
++
++ /* Clear IN xfercompl if set */
++ if (diepint0.b.xfercompl && (pcd->ep0state == EP0_IN_STATUS_PHASE
++ || pcd->ep0state == EP0_IN_DATA_PHASE)) {
++ DWC_WRITE_REG32(&core_if->dev_if->
++ in_ep_regs[0]->diepint, diepint0.d32);
++ }
++
++ status.d32 = core_if->dev_if->setup_desc_addr[core_if->
++ dev_if->setup_desc_index]->status.d32;
++
++ if (ep->dwc_ep.xfer_count != ep->dwc_ep.total_len
++ && (pcd->ep0state == EP0_OUT_DATA_PHASE))
++ status.d32 = core_if->dev_if->out_desc_addr->status.d32;
++ if (pcd->ep0state == EP0_OUT_STATUS_PHASE)
++ status.d32 = core_if->dev_if->
++ out_desc_addr->status.d32;
++
++ if (status.b.sr) {
++ if (DWC_CIRCLEQ_EMPTY(&ep->queue)) {
++ DWC_DEBUGPL(DBG_PCDV, "Request queue empty!!\n");
++ } else {
++ DWC_DEBUGPL(DBG_PCDV, "complete req!!\n");
++ req = DWC_CIRCLEQ_FIRST(&ep->queue);
++ if (ep->dwc_ep.xfer_count != ep->dwc_ep.total_len &&
++ pcd->ep0state == EP0_OUT_DATA_PHASE) {
++ /* Read arrived setup packet from req->buf */
++ dwc_memcpy(&pcd->setup_pkt->req,
++ req->buf + ep->dwc_ep.xfer_count, 8);
++ }
++ req->actual = ep->dwc_ep.xfer_count;
++ dwc_otg_request_done(ep, req, -ECONNRESET);
++ ep->dwc_ep.start_xfer_buff = 0;
++ ep->dwc_ep.xfer_buff = 0;
++ ep->dwc_ep.xfer_len = 0;
++ }
++ pcd->ep0state = EP0_IDLE;
++ if (doepint.b.setup) {
++ DWC_DEBUGPL(DBG_PCDV, "EP0_IDLE SR=1 setup=1\n");
++ /* Data stage started, clear setup */
++ CLEAR_OUT_EP_INTR(core_if, epnum, setup);
++ doepint.b.setup = 0;
++ handle_ep0(pcd);
++ /* Prepare for setup packets if ep0in was enabled*/
++ if (pcd->ep0state == EP0_IN_STATUS_PHASE) {
++ ep0_out_start(core_if, pcd);
++ }
++
++ goto exit_xfercompl;
++ } else {
++ /* Prepare for more setup packets */
++ DWC_DEBUGPL(DBG_PCDV,
++ "EP0_IDLE SR=1 setup=0 new setup comes 2\n");
++ ep0_out_start(core_if, pcd);
++ }
++ }
++ }
++ }
++ if (core_if->snpsid >= OTG_CORE_REV_2_94a && core_if->dma_enable
++ && core_if->dma_desc_enable == 0) {
++ doepint_data_t doepint_temp = {.d32 = 0};
++ deptsiz0_data_t doeptsize0 = {.d32 = 0 };
++ doepint_temp.d32 = DWC_READ_REG32(&core_if->dev_if->
++ out_ep_regs[ep->dwc_ep.num]->doepint);
++ doeptsize0.d32 = DWC_READ_REG32(&core_if->dev_if->
++ out_ep_regs[ep->dwc_ep.num]->doeptsiz);
++ if (pcd->ep0state == EP0_IDLE) {
++ if (doepint_temp.b.sr) {
++ CLEAR_OUT_EP_INTR(core_if, epnum, sr);
++ }
++ doepint.d32 = DWC_READ_REG32(&core_if->dev_if->
++ out_ep_regs[0]->doepint);
++ if (doeptsize0.b.supcnt == 3) {
++ DWC_DEBUGPL(DBG_ANY, "Rolling over!!!!!!!\n");
++ ep->dwc_ep.stp_rollover = 1;
++ }
++ if (doepint.b.setup) {
++retry:
++ /* Already started data stage, clear setup */
++ CLEAR_OUT_EP_INTR(core_if, epnum, setup);
++ doepint.b.setup = 0;
++ handle_ep0(pcd);
++ ep->dwc_ep.stp_rollover = 0;
++ /* Prepare for more setup packets */
++ if (pcd->ep0state == EP0_IN_STATUS_PHASE ||
++ pcd->ep0state == EP0_IN_DATA_PHASE) {
++ ep0_out_start(core_if, pcd);
++ }
++ goto exit_xfercompl;
++ } else {
++ /* Prepare for more setup packets */
++ DWC_DEBUGPL(DBG_ANY,
++ "EP0_IDLE SR=1 setup=0 new setup comes\n");
++ doepint.d32 = DWC_READ_REG32(&core_if->dev_if->
++ out_ep_regs[0]->doepint);
++ if(doepint.b.setup)
++ goto retry;
++ ep0_out_start(core_if, pcd);
++ }
++ } else {
++ dwc_otg_pcd_request_t *req;
++ diepint_data_t diepint0 = {.d32 = 0};
++ doepint_data_t doepint_temp = {.d32 = 0};
++ depctl_data_t diepctl0;
++ diepint0.d32 = DWC_READ_REG32(&core_if->dev_if->
++ in_ep_regs[0]->diepint);
++ diepctl0.d32 = DWC_READ_REG32(&core_if->dev_if->
++ in_ep_regs[0]->diepctl);
++
++ if (pcd->ep0state == EP0_IN_DATA_PHASE
++ || pcd->ep0state == EP0_IN_STATUS_PHASE) {
++ if (diepint0.b.xfercompl) {
++ DWC_WRITE_REG32(&core_if->dev_if->
++ in_ep_regs[0]->diepint, diepint0.d32);
++ }
++ if (diepctl0.b.epena) {
++ diepint_data_t diepint = {.d32 = 0};
++ diepctl0.b.snak = 1;
++ DWC_WRITE_REG32(&core_if->dev_if->
++ in_ep_regs[0]->diepctl, diepctl0.d32);
++ do {
++ dwc_udelay(10);
++ diepint.d32 = DWC_READ_REG32(&core_if->dev_if->
++ in_ep_regs[0]->diepint);
++ } while (!diepint.b.inepnakeff);
++ diepint.b.inepnakeff = 1;
++ DWC_WRITE_REG32(&core_if->dev_if->
++ in_ep_regs[0]->diepint, diepint.d32);
++ diepctl0.d32 = 0;
++ diepctl0.b.epdis = 1;
++ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[0]->diepctl,
++ diepctl0.d32);
++ do {
++ dwc_udelay(10);
++ diepint.d32 = DWC_READ_REG32(&core_if->dev_if->
++ in_ep_regs[0]->diepint);
++ } while (!diepint.b.epdisabled);
++ diepint.b.epdisabled = 1;
++ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[0]->diepint,
++ diepint.d32);
++ }
++ }
++ doepint_temp.d32 = DWC_READ_REG32(&core_if->dev_if->
++ out_ep_regs[ep->dwc_ep.num]->doepint);
++ if (doepint_temp.b.sr) {
++ CLEAR_OUT_EP_INTR(core_if, epnum, sr);
++ if (DWC_CIRCLEQ_EMPTY(&ep->queue)) {
++ DWC_DEBUGPL(DBG_PCDV, "Request queue empty!!\n");
++ } else {
++ DWC_DEBUGPL(DBG_PCDV, "complete req!!\n");
++ req = DWC_CIRCLEQ_FIRST(&ep->queue);
++ if (ep->dwc_ep.xfer_count != ep->dwc_ep.total_len &&
++ pcd->ep0state == EP0_OUT_DATA_PHASE) {
++ /* Read arrived setup packet from req->buf */
++ dwc_memcpy(&pcd->setup_pkt->req,
++ req->buf + ep->dwc_ep.xfer_count, 8);
++ }
++ req->actual = ep->dwc_ep.xfer_count;
++ dwc_otg_request_done(ep, req, -ECONNRESET);
++ ep->dwc_ep.start_xfer_buff = 0;
++ ep->dwc_ep.xfer_buff = 0;
++ ep->dwc_ep.xfer_len = 0;
++ }
++ pcd->ep0state = EP0_IDLE;
++ if (doepint.b.setup) {
++ DWC_DEBUGPL(DBG_PCDV, "EP0_IDLE SR=1 setup=1\n");
++ /* Data stage started, clear setup */
++ CLEAR_OUT_EP_INTR(core_if, epnum, setup);
++ doepint.b.setup = 0;
++ handle_ep0(pcd);
++ /* Prepare for setup packets if ep0in was enabled*/
++ if (pcd->ep0state == EP0_IN_STATUS_PHASE) {
++ ep0_out_start(core_if, pcd);
++ }
++ goto exit_xfercompl;
++ } else {
++ /* Prepare for more setup packets */
++ DWC_DEBUGPL(DBG_PCDV,
++ "EP0_IDLE SR=1 setup=0 new setup comes 2\n");
++ ep0_out_start(core_if, pcd);
++ }
++ }
++ }
++ }
++ if (core_if->dma_enable == 0 || pcd->ep0state != EP0_IDLE)
++ handle_ep0(pcd);
++exit_xfercompl:
++ DWC_DEBUGPL(DBG_PCDV, "DOEPINT=%x doepint=%x\n",
++ dwc_otg_read_dev_out_ep_intr(core_if, dwc_ep), doepint.d32);
++ } else {
++ if (core_if->dma_desc_enable == 0
++ || pcd->ep0state != EP0_IDLE)
++ handle_ep0(pcd);
++ }
++#ifdef DWC_EN_ISOC
++ } else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
++ if (doepint.b.pktdrpsts == 0) {
++ /* Clear the bit in DOEPINTn for this interrupt */
++ CLEAR_OUT_EP_INTR(core_if,
++ epnum,
++ xfercompl);
++ complete_iso_ep(pcd, ep);
++ } else {
++
++ doepint_data_t doepint = {.d32 = 0 };
++ doepint.b.xfercompl = 1;
++ doepint.b.pktdrpsts = 1;
++ DWC_WRITE_REG32
++ (&core_if->dev_if->out_ep_regs
++ [epnum]->doepint,
++ doepint.d32);
++ if (handle_iso_out_pkt_dropped
++ (core_if, dwc_ep)) {
++ complete_iso_ep(pcd,
++ ep);
++ }
++ }
++#endif /* DWC_EN_ISOC */
++#ifdef DWC_UTE_PER_IO
++ } else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
++ CLEAR_OUT_EP_INTR(core_if, epnum, xfercompl);
++ if (!ep->stopped)
++ complete_xiso_ep(ep);
++#endif /* DWC_UTE_PER_IO */
++ } else {
++ /* Clear the bit in DOEPINTn for this interrupt */
++ CLEAR_OUT_EP_INTR(core_if, epnum,
++ xfercompl);
++
++ if (core_if->core_params->dev_out_nak) {
++ DWC_TIMER_CANCEL(pcd->core_if->ep_xfer_timer[epnum]);
++ pcd->core_if->ep_xfer_info[epnum].state = 0;
++#ifdef DEBUG
++ print_memory_payload(pcd, dwc_ep);
++#endif
++ }
++ complete_ep(ep);
++ }
++
++ }
++
++ /* Endpoint disable */
++ if (doepint.b.epdisabled) {
++
++ /* Clear the bit in DOEPINTn for this interrupt */
++ CLEAR_OUT_EP_INTR(core_if, epnum, epdisabled);
++ if (core_if->core_params->dev_out_nak) {
++#ifdef DEBUG
++ print_memory_payload(pcd, dwc_ep);
++#endif
++ /* In case of timeout condition */
++ if (core_if->ep_xfer_info[epnum].state == 2) {
++ dctl.d32 = DWC_READ_REG32(&core_if->dev_if->
++ dev_global_regs->dctl);
++ dctl.b.cgoutnak = 1;
++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl,
++ dctl.d32);
++ /* Unmask goutnakeff interrupt which was masked
++ * during handle nak out interrupt */
++ gintmsk.b.goutnakeff = 1;
++ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk,
++ 0, gintmsk.d32);
++
++ complete_ep(ep);
++ }
++ }
++ if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC)
++ {
++ dctl_data_t dctl;
++ gintmsk_data_t intr_mask = {.d32 = 0};
++ dwc_otg_pcd_request_t *req = 0;
++
++ dctl.d32 = DWC_READ_REG32(&core_if->dev_if->
++ dev_global_regs->dctl);
++ dctl.b.cgoutnak = 1;
++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl,
++ dctl.d32);
++
++ intr_mask.d32 = 0;
++ intr_mask.b.incomplisoout = 1;
++
++ /* Get any pending requests */
++ if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
++ req = DWC_CIRCLEQ_FIRST(&ep->queue);
++ if (!req) {
++ DWC_PRINTF("complete_ep 0x%p, req = NULL!\n", ep);
++ } else {
++ dwc_otg_request_done(ep, req, 0);
++ start_next_request(ep);
++ }
++ } else {
++ DWC_PRINTF("complete_ep 0x%p, ep->queue empty!\n", ep);
++ }
++ }
++ }
++ /* AHB Error */
++ if (doepint.b.ahberr) {
++ DWC_ERROR("EP%d OUT AHB Error\n", epnum);
++ DWC_ERROR("EP%d DEPDMA=0x%08x \n",
++ epnum, core_if->dev_if->out_ep_regs[epnum]->doepdma);
++ CLEAR_OUT_EP_INTR(core_if, epnum, ahberr);
++ }
++ /* Setup Phase Done (contorl EPs) */
++ if (doepint.b.setup) {
++#ifdef DEBUG_EP0
++ DWC_DEBUGPL(DBG_PCD, "EP%d SETUP Done\n", epnum);
++#endif
++ CLEAR_OUT_EP_INTR(core_if, epnum, setup);
++
++ handle_ep0(pcd);
++ }
++
++ /** OUT EP BNA Intr */
++ if (doepint.b.bna) {
++ CLEAR_OUT_EP_INTR(core_if, epnum, bna);
++ if (core_if->dma_desc_enable) {
++#ifdef DWC_EN_ISOC
++ if (dwc_ep->type ==
++ DWC_OTG_EP_TYPE_ISOC) {
++ /*
++ * This checking is performed to prevent first "false" BNA
++ * handling occuring right after reconnect
++ */
++ if (dwc_ep->next_frame !=
++ 0xffffffff)
++ dwc_otg_pcd_handle_iso_bna(ep);
++ } else
++#endif /* DWC_EN_ISOC */
++ {
++ dwc_otg_pcd_handle_noniso_bna(ep);
++ }
++ }
++ }
++ /* Babble Interrupt */
++ if (doepint.b.babble) {
++ DWC_DEBUGPL(DBG_ANY, "EP%d OUT Babble\n",
++ epnum);
++ handle_out_ep_babble_intr(pcd, epnum);
++
++ CLEAR_OUT_EP_INTR(core_if, epnum, babble);
++ }
++ if (doepint.b.outtknepdis) {
++ DWC_DEBUGPL(DBG_ANY, "EP%d OUT Token received when EP is \
++ disabled\n",epnum);
++ if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
++ doepmsk_data_t doepmsk = {.d32 = 0};
++ ep->dwc_ep.frame_num = core_if->frame_num;
++ if (ep->dwc_ep.bInterval > 1) {
++ depctl_data_t depctl;
++ depctl.d32 = DWC_READ_REG32(&core_if->dev_if->
++ out_ep_regs[epnum]->doepctl);
++ if (ep->dwc_ep.frame_num & 0x1) {
++ depctl.b.setd1pid = 1;
++ depctl.b.setd0pid = 0;
++ } else {
++ depctl.b.setd0pid = 1;
++ depctl.b.setd1pid = 0;
++ }
++ DWC_WRITE_REG32(&core_if->dev_if->
++ out_ep_regs[epnum]->doepctl, depctl.d32);
++ }
++ start_next_request(ep);
++ doepmsk.b.outtknepdis = 1;
++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->doepmsk,
++ doepmsk.d32, 0);
++ }
++ CLEAR_OUT_EP_INTR(core_if, epnum, outtknepdis);
++ }
++
++ /* NAK Interrutp */
++ if (doepint.b.nak) {
++ DWC_DEBUGPL(DBG_ANY, "EP%d OUT NAK\n", epnum);
++ handle_out_ep_nak_intr(pcd, epnum);
++
++ CLEAR_OUT_EP_INTR(core_if, epnum, nak);
++ }
++ /* NYET Interrutp */
++ if (doepint.b.nyet) {
++ DWC_DEBUGPL(DBG_ANY, "EP%d OUT NYET\n", epnum);
++ handle_out_ep_nyet_intr(pcd, epnum);
++
++ CLEAR_OUT_EP_INTR(core_if, epnum, nyet);
++ }
++ }
++
++ epnum++;
++ ep_intr >>= 1;
++ }
++
++ return 1;
++
++#undef CLEAR_OUT_EP_INTR
++}
++static int drop_transfer(uint32_t trgt_fr, uint32_t curr_fr, uint8_t frm_overrun)
++{
++ int retval = 0;
++ if(!frm_overrun && curr_fr >= trgt_fr)
++ retval = 1;
++ else if (frm_overrun
++ && (curr_fr >= trgt_fr && ((curr_fr - trgt_fr) < 0x3FFF / 2)))
++ retval = 1;
++ return retval;
++}
++/**
++ * Incomplete ISO IN Transfer Interrupt.
++ * This interrupt indicates one of the following conditions occurred
++ * while transmitting an ISOC transaction.
++ * - Corrupted IN Token for ISOC EP.
++ * - Packet not complete in FIFO.
++ * The follow actions will be taken:
++ * -# Determine the EP
++ * -# Set incomplete flag in dwc_ep structure
++ * -# Disable EP; when "Endpoint Disabled" interrupt is received
++ * Flush FIFO
++ */
++int32_t dwc_otg_pcd_handle_incomplete_isoc_in_intr(dwc_otg_pcd_t * pcd)
++{
++ gintsts_data_t gintsts;
++
++#ifdef DWC_EN_ISOC
++ dwc_otg_dev_if_t *dev_if;
++ deptsiz_data_t deptsiz = {.d32 = 0 };
++ depctl_data_t depctl = {.d32 = 0 };
++ dsts_data_t dsts = {.d32 = 0 };
++ dwc_ep_t *dwc_ep;
++ int i;
++
++ dev_if = GET_CORE_IF(pcd)->dev_if;
++
++ for (i = 1; i <= dev_if->num_in_eps; ++i) {
++ dwc_ep = &pcd->in_ep[i].dwc_ep;
++ if (dwc_ep->active && dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
++ deptsiz.d32 =
++ DWC_READ_REG32(&dev_if->in_ep_regs[i]->dieptsiz);
++ depctl.d32 =
++ DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
++
++ if (depctl.b.epdis && deptsiz.d32) {
++ set_current_pkt_info(GET_CORE_IF(pcd), dwc_ep);
++ if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
++ dwc_ep->cur_pkt = 0;
++ dwc_ep->proc_buf_num =
++ (dwc_ep->proc_buf_num ^ 1) & 0x1;
++
++ if (dwc_ep->proc_buf_num) {
++ dwc_ep->cur_pkt_addr =
++ dwc_ep->xfer_buff1;
++ dwc_ep->cur_pkt_dma_addr =
++ dwc_ep->dma_addr1;
++ } else {
++ dwc_ep->cur_pkt_addr =
++ dwc_ep->xfer_buff0;
++ dwc_ep->cur_pkt_dma_addr =
++ dwc_ep->dma_addr0;
++ }
++
++ }
++
++ dsts.d32 =
++ DWC_READ_REG32(&GET_CORE_IF(pcd)->dev_if->
++ dev_global_regs->dsts);
++ dwc_ep->next_frame = dsts.b.soffn;
++
++ dwc_otg_iso_ep_start_frm_transfer(GET_CORE_IF
++ (pcd),
++ dwc_ep);
++ }
++ }
++ }
++
++#else
++ depctl_data_t depctl = {.d32 = 0 };
++ dwc_ep_t *dwc_ep;
++ dwc_otg_dev_if_t *dev_if;
++ int i;
++ dev_if = GET_CORE_IF(pcd)->dev_if;
++
++ DWC_DEBUGPL(DBG_PCD,"Incomplete ISO IN \n");
++
++ for (i = 1; i <= dev_if->num_in_eps; ++i) {
++ dwc_ep = &pcd->in_ep[i-1].dwc_ep;
++ depctl.d32 =
++ DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
++ if (depctl.b.epena && dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
++ if (drop_transfer(dwc_ep->frame_num, GET_CORE_IF(pcd)->frame_num,
++ dwc_ep->frm_overrun))
++ {
++ depctl.d32 =
++ DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
++ depctl.b.snak = 1;
++ depctl.b.epdis = 1;
++ DWC_MODIFY_REG32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32, depctl.d32);
++ }
++ }
++ }
++
++ /*intr_mask.b.incomplisoin = 1;
++ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
++ intr_mask.d32, 0); */
++#endif //DWC_EN_ISOC
++
++ /* Clear interrupt */
++ gintsts.d32 = 0;
++ gintsts.b.incomplisoin = 1;
++ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
++ gintsts.d32);
++
++ return 1;
++}
++
++/**
++ * Incomplete ISO OUT Transfer Interrupt.
++ *
++ * This interrupt indicates that the core has dropped an ISO OUT
++ * packet. The following conditions can be the cause:
++ * - FIFO Full, the entire packet would not fit in the FIFO.
++ * - CRC Error
++ * - Corrupted Token
++ * The follow actions will be taken:
++ * -# Determine the EP
++ * -# Set incomplete flag in dwc_ep structure
++ * -# Read any data from the FIFO
++ * -# Disable EP. When "Endpoint Disabled" interrupt is received
++ * re-enable EP.
++ */
++int32_t dwc_otg_pcd_handle_incomplete_isoc_out_intr(dwc_otg_pcd_t * pcd)
++{
++
++ gintsts_data_t gintsts;
++
++#ifdef DWC_EN_ISOC
++ dwc_otg_dev_if_t *dev_if;
++ deptsiz_data_t deptsiz = {.d32 = 0 };
++ depctl_data_t depctl = {.d32 = 0 };
++ dsts_data_t dsts = {.d32 = 0 };
++ dwc_ep_t *dwc_ep;
++ int i;
++
++ dev_if = GET_CORE_IF(pcd)->dev_if;
++
++ for (i = 1; i <= dev_if->num_out_eps; ++i) {
++ dwc_ep = &pcd->in_ep[i].dwc_ep;
++ if (pcd->out_ep[i].dwc_ep.active &&
++ pcd->out_ep[i].dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
++ deptsiz.d32 =
++ DWC_READ_REG32(&dev_if->out_ep_regs[i]->doeptsiz);
++ depctl.d32 =
++ DWC_READ_REG32(&dev_if->out_ep_regs[i]->doepctl);
++
++ if (depctl.b.epdis && deptsiz.d32) {
++ set_current_pkt_info(GET_CORE_IF(pcd),
++ &pcd->out_ep[i].dwc_ep);
++ if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
++ dwc_ep->cur_pkt = 0;
++ dwc_ep->proc_buf_num =
++ (dwc_ep->proc_buf_num ^ 1) & 0x1;
++
++ if (dwc_ep->proc_buf_num) {
++ dwc_ep->cur_pkt_addr =
++ dwc_ep->xfer_buff1;
++ dwc_ep->cur_pkt_dma_addr =
++ dwc_ep->dma_addr1;
++ } else {
++ dwc_ep->cur_pkt_addr =
++ dwc_ep->xfer_buff0;
++ dwc_ep->cur_pkt_dma_addr =
++ dwc_ep->dma_addr0;
++ }
++
++ }
++
++ dsts.d32 =
++ DWC_READ_REG32(&GET_CORE_IF(pcd)->dev_if->
++ dev_global_regs->dsts);
++ dwc_ep->next_frame = dsts.b.soffn;
++
++ dwc_otg_iso_ep_start_frm_transfer(GET_CORE_IF
++ (pcd),
++ dwc_ep);
++ }
++ }
++ }
++#else
++ /** @todo implement ISR */
++ gintmsk_data_t intr_mask = {.d32 = 0 };
++ dwc_otg_core_if_t *core_if;
++ deptsiz_data_t deptsiz = {.d32 = 0 };
++ depctl_data_t depctl = {.d32 = 0 };
++ dctl_data_t dctl = {.d32 = 0 };
++ dwc_ep_t *dwc_ep = NULL;
++ int i;
++ core_if = GET_CORE_IF(pcd);
++
++ for (i = 0; i < core_if->dev_if->num_out_eps; ++i) {
++ dwc_ep = &pcd->out_ep[i].dwc_ep;
++ depctl.d32 =
++ DWC_READ_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl);
++ if (depctl.b.epena && depctl.b.dpid == (core_if->frame_num & 0x1)) {
++ core_if->dev_if->isoc_ep = dwc_ep;
++ deptsiz.d32 =
++ DWC_READ_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doeptsiz);
++ break;
++ }
++ }
++ dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
++ gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
++ intr_mask.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
++
++ if (!intr_mask.b.goutnakeff) {
++ /* Unmask it */
++ intr_mask.b.goutnakeff = 1;
++ DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, intr_mask.d32);
++ }
++ if (!gintsts.b.goutnakeff) {
++ dctl.b.sgoutnak = 1;
++ }
++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
++
++ depctl.d32 = DWC_READ_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl);
++ if (depctl.b.epena) {
++ depctl.b.epdis = 1;
++ depctl.b.snak = 1;
++ }
++ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl, depctl.d32);
++
++ intr_mask.d32 = 0;
++ intr_mask.b.incomplisoout = 1;
++
++#endif /* DWC_EN_ISOC */
++
++ /* Clear interrupt */
++ gintsts.d32 = 0;
++ gintsts.b.incomplisoout = 1;
++ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
++ gintsts.d32);
++
++ return 1;
++}
++
++/**
++ * This function handles the Global IN NAK Effective interrupt.
++ *
++ */
++int32_t dwc_otg_pcd_handle_in_nak_effective(dwc_otg_pcd_t * pcd)
++{
++ dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if;
++ depctl_data_t diepctl = {.d32 = 0 };
++ gintmsk_data_t intr_mask = {.d32 = 0 };
++ gintsts_data_t gintsts;
++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++ int i;
++
++ DWC_DEBUGPL(DBG_PCD, "Global IN NAK Effective\n");
++
++ /* Disable all active IN EPs */
++ for (i = 0; i <= dev_if->num_in_eps; i++) {
++ diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
++ if (!(diepctl.b.eptype & 1) && diepctl.b.epena) {
++ if (core_if->start_predict > 0)
++ core_if->start_predict++;
++ diepctl.b.epdis = 1;
++ diepctl.b.snak = 1;
++ DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl, diepctl.d32);
++ }
++ }
++
++
++ /* Disable the Global IN NAK Effective Interrupt */
++ intr_mask.b.ginnakeff = 1;
++ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
++ intr_mask.d32, 0);
++
++ /* Clear interrupt */
++ gintsts.d32 = 0;
++ gintsts.b.ginnakeff = 1;
++ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
++ gintsts.d32);
++
++ return 1;
++}
++
++/**
++ * OUT NAK Effective.
++ *
++ */
++int32_t dwc_otg_pcd_handle_out_nak_effective(dwc_otg_pcd_t * pcd)
++{
++ dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if;
++ gintmsk_data_t intr_mask = {.d32 = 0 };
++ gintsts_data_t gintsts;
++ depctl_data_t doepctl;
++ int i;
++
++ /* Disable the Global OUT NAK Effective Interrupt */
++ intr_mask.b.goutnakeff = 1;
++ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
++ intr_mask.d32, 0);
++
++ /* If DEV OUT NAK enabled*/
++ if (pcd->core_if->core_params->dev_out_nak) {
++ /* Run over all out endpoints to determine the ep number on
++ * which the timeout has happened
++ */
++ for (i = 0; i <= dev_if->num_out_eps; i++) {
++ if ( pcd->core_if->ep_xfer_info[i].state == 2 )
++ break;
++ }
++ if (i > dev_if->num_out_eps) {
++ dctl_data_t dctl;
++ dctl.d32 =
++ DWC_READ_REG32(&dev_if->dev_global_regs->dctl);
++ dctl.b.cgoutnak = 1;
++ DWC_WRITE_REG32(&dev_if->dev_global_regs->dctl,
++ dctl.d32);
++ goto out;
++ }
++
++ /* Disable the endpoint */
++ doepctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[i]->doepctl);
++ if (doepctl.b.epena) {
++ doepctl.b.epdis = 1;
++ doepctl.b.snak = 1;
++ }
++ DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepctl, doepctl.d32);
++ return 1;
++ }
++ /* We come here from Incomplete ISO OUT handler */
++ if (dev_if->isoc_ep) {
++ dwc_ep_t *dwc_ep = (dwc_ep_t *)dev_if->isoc_ep;
++ uint32_t epnum = dwc_ep->num;
++ doepint_data_t doepint;
++ doepint.d32 =
++ DWC_READ_REG32(&dev_if->out_ep_regs[dwc_ep->num]->doepint);
++ dev_if->isoc_ep = NULL;
++ doepctl.d32 =
++ DWC_READ_REG32(&dev_if->out_ep_regs[epnum]->doepctl);
++ DWC_PRINTF("Before disable DOEPCTL = %08x\n", doepctl.d32);
++ if (doepctl.b.epena) {
++ doepctl.b.epdis = 1;
++ doepctl.b.snak = 1;
++ }
++ DWC_WRITE_REG32(&dev_if->out_ep_regs[epnum]->doepctl,
++ doepctl.d32);
++ return 1;
++ } else
++ DWC_PRINTF("INTERRUPT Handler not implemented for %s\n",
++ "Global OUT NAK Effective\n");
++
++out:
++ /* Clear interrupt */
++ gintsts.d32 = 0;
++ gintsts.b.goutnakeff = 1;
++ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
++ gintsts.d32);
++
++ return 1;
++}
++
++/**
++ * PCD interrupt handler.
++ *
++ * The PCD handles the device interrupts. Many conditions can cause a
++ * device interrupt. When an interrupt occurs, the device interrupt
++ * service routine determines the cause of the interrupt and
++ * dispatches handling to the appropriate function. These interrupt
++ * handling functions are described below.
++ *
++ * All interrupt registers are processed from LSB to MSB.
++ *
++ */
++int32_t dwc_otg_pcd_handle_intr(dwc_otg_pcd_t * pcd)
++{
++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++#ifdef VERBOSE
++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
++#endif
++ gintsts_data_t gintr_status;
++ int32_t retval = 0;
++
++ /* Exit from ISR if core is hibernated */
++ if (core_if->hibernation_suspend == 1) {
++ return retval;
++ }
++#ifdef VERBOSE
++ DWC_DEBUGPL(DBG_ANY, "%s() gintsts=%08x gintmsk=%08x\n",
++ __func__,
++ DWC_READ_REG32(&global_regs->gintsts),
++ DWC_READ_REG32(&global_regs->gintmsk));
++#endif
++
++ if (dwc_otg_is_device_mode(core_if)) {
++ DWC_SPINLOCK(pcd->lock);
++#ifdef VERBOSE
++ DWC_DEBUGPL(DBG_PCDV, "%s() gintsts=%08x gintmsk=%08x\n",
++ __func__,
++ DWC_READ_REG32(&global_regs->gintsts),
++ DWC_READ_REG32(&global_regs->gintmsk));
++#endif
++
++ gintr_status.d32 = dwc_otg_read_core_intr(core_if);
++
++ DWC_DEBUGPL(DBG_PCDV, "%s: gintsts&gintmsk=%08x\n",
++ __func__, gintr_status.d32);
++
++ if (gintr_status.b.sofintr) {
++ retval |= dwc_otg_pcd_handle_sof_intr(pcd);
++ }
++ if (gintr_status.b.rxstsqlvl) {
++ retval |=
++ dwc_otg_pcd_handle_rx_status_q_level_intr(pcd);
++ }
++ if (gintr_status.b.nptxfempty) {
++ retval |= dwc_otg_pcd_handle_np_tx_fifo_empty_intr(pcd);
++ }
++ if (gintr_status.b.goutnakeff) {
++ retval |= dwc_otg_pcd_handle_out_nak_effective(pcd);
++ }
++ if (gintr_status.b.i2cintr) {
++ retval |= dwc_otg_pcd_handle_i2c_intr(pcd);
++ }
++ if (gintr_status.b.erlysuspend) {
++ retval |= dwc_otg_pcd_handle_early_suspend_intr(pcd);
++ }
++ if (gintr_status.b.usbreset) {
++ retval |= dwc_otg_pcd_handle_usb_reset_intr(pcd);
++ }
++ if (gintr_status.b.enumdone) {
++ retval |= dwc_otg_pcd_handle_enum_done_intr(pcd);
++ }
++ if (gintr_status.b.isooutdrop) {
++ retval |=
++ dwc_otg_pcd_handle_isoc_out_packet_dropped_intr
++ (pcd);
++ }
++ if (gintr_status.b.eopframe) {
++ retval |=
++ dwc_otg_pcd_handle_end_periodic_frame_intr(pcd);
++ }
++ if (gintr_status.b.inepint) {
++ if (!core_if->multiproc_int_enable) {
++ retval |= dwc_otg_pcd_handle_in_ep_intr(pcd);
++ }
++ }
++ if (gintr_status.b.outepintr) {
++ if (!core_if->multiproc_int_enable) {
++ retval |= dwc_otg_pcd_handle_out_ep_intr(pcd);
++ }
++ }
++ if (gintr_status.b.epmismatch) {
++ retval |= dwc_otg_pcd_handle_ep_mismatch_intr(pcd);
++ }
++ if (gintr_status.b.fetsusp) {
++ retval |= dwc_otg_pcd_handle_ep_fetsusp_intr(pcd);
++ }
++ if (gintr_status.b.ginnakeff) {
++ retval |= dwc_otg_pcd_handle_in_nak_effective(pcd);
++ }
++ if (gintr_status.b.incomplisoin) {
++ retval |=
++ dwc_otg_pcd_handle_incomplete_isoc_in_intr(pcd);
++ }
++ if (gintr_status.b.incomplisoout) {
++ retval |=
++ dwc_otg_pcd_handle_incomplete_isoc_out_intr(pcd);
++ }
++
++ /* In MPI mode Device Endpoints interrupts are asserted
++ * without setting outepintr and inepint bits set, so these
++ * Interrupt handlers are called without checking these bit-fields
++ */
++ if (core_if->multiproc_int_enable) {
++ retval |= dwc_otg_pcd_handle_in_ep_intr(pcd);
++ retval |= dwc_otg_pcd_handle_out_ep_intr(pcd);
++ }
++#ifdef VERBOSE
++ DWC_DEBUGPL(DBG_PCDV, "%s() gintsts=%0x\n", __func__,
++ DWC_READ_REG32(&global_regs->gintsts));
++#endif
++ DWC_SPINUNLOCK(pcd->lock);
++ }
++ return retval;
++}
++
++#endif /* DWC_HOST_ONLY */
+diff -Nur linux-4.1.3/drivers/usb/host/dwc_otg/dwc_otg_pcd_linux.c linux-xbian-rpi/drivers/usb/host/dwc_otg/dwc_otg_pcd_linux.c
+--- linux-4.1.3/drivers/usb/host/dwc_otg/dwc_otg_pcd_linux.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/usb/host/dwc_otg/dwc_otg_pcd_linux.c 2015-07-28 01:20:58.449142252 +0200
+@@ -0,0 +1,1360 @@
++ /* ==========================================================================
++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_linux.c $
++ * $Revision: #21 $
++ * $Date: 2012/08/10 $
++ * $Change: 2047372 $
++ *
++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++ * otherwise expressly agreed to in writing between Synopsys and you.
++ *
++ * The Software IS NOT an item of Licensed Software or Licensed Product under
++ * any End User Software License Agreement or Agreement for Licensed Product
++ * with Synopsys or any supplement thereto. You are permitted to use and
++ * redistribute this Software in source and binary forms, with or without
++ * modification, provided that redistributions of source code must retain this
++ * notice. You may not view, use, disclose, copy or distribute this file or
++ * any information contained herein except pursuant to this license grant from
++ * Synopsys. If you do not agree with this notice, including the disclaimer
++ * below, then you are not authorized to use the Software.
++ *
++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++ * DAMAGE.
++ * ========================================================================== */
++#ifndef DWC_HOST_ONLY
++
++/** @file
++ * This file implements the Peripheral Controller Driver.
++ *
++ * The Peripheral Controller Driver (PCD) is responsible for
++ * translating requests from the Function Driver into the appropriate
++ * actions on the DWC_otg controller. It isolates the Function Driver
++ * from the specifics of the controller by providing an API to the
++ * Function Driver.
++ *
++ * The Peripheral Controller Driver for Linux will implement the
++ * Gadget API, so that the existing Gadget drivers can be used.
++ * (Gadget Driver is the Linux terminology for a Function Driver.)
++ *
++ * The Linux Gadget API is defined in the header file
++ * <code><linux/usb_gadget.h></code>. The USB EP operations API is
++ * defined in the structure <code>usb_ep_ops</code> and the USB
++ * Controller API is defined in the structure
++ * <code>usb_gadget_ops</code>.
++ *
++ */
++
++#include "dwc_otg_os_dep.h"
++#include "dwc_otg_pcd_if.h"
++#include "dwc_otg_pcd.h"
++#include "dwc_otg_driver.h"
++#include "dwc_otg_dbg.h"
++
++extern bool fiq_enable;
++
++static struct gadget_wrapper {
++ dwc_otg_pcd_t *pcd;
++
++ struct usb_gadget gadget;
++ struct usb_gadget_driver *driver;
++
++ struct usb_ep ep0;
++ struct usb_ep in_ep[16];
++ struct usb_ep out_ep[16];
++
++} *gadget_wrapper;
++
++/* Display the contents of the buffer */
++extern void dump_msg(const u8 * buf, unsigned int length);
++/**
++ * Get the dwc_otg_pcd_ep_t* from usb_ep* pointer - NULL in case
++ * if the endpoint is not found
++ */
++static struct dwc_otg_pcd_ep *ep_from_handle(dwc_otg_pcd_t * pcd, void *handle)
++{
++ int i;
++ if (pcd->ep0.priv == handle) {
++ return &pcd->ep0;
++ }
++
++ for (i = 0; i < MAX_EPS_CHANNELS - 1; i++) {
++ if (pcd->in_ep[i].priv == handle)
++ return &pcd->in_ep[i];
++ if (pcd->out_ep[i].priv == handle)
++ return &pcd->out_ep[i];
++ }
++
++ return NULL;
++}
++
++/* USB Endpoint Operations */
++/*
++ * The following sections briefly describe the behavior of the Gadget
++ * API endpoint operations implemented in the DWC_otg driver
++ * software. Detailed descriptions of the generic behavior of each of
++ * these functions can be found in the Linux header file
++ * include/linux/usb_gadget.h.
++ *
++ * The Gadget API provides wrapper functions for each of the function
++ * pointers defined in usb_ep_ops. The Gadget Driver calls the wrapper
++ * function, which then calls the underlying PCD function. The
++ * following sections are named according to the wrapper
++ * functions. Within each section, the corresponding DWC_otg PCD
++ * function name is specified.
++ *
++ */
++
++/**
++ * This function is called by the Gadget Driver for each EP to be
++ * configured for the current configuration (SET_CONFIGURATION).
++ *
++ * This function initializes the dwc_otg_ep_t data structure, and then
++ * calls dwc_otg_ep_activate.
++ */
++static int ep_enable(struct usb_ep *usb_ep,
++ const struct usb_endpoint_descriptor *ep_desc)
++{
++ int retval;
++
++ DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p)\n", __func__, usb_ep, ep_desc);
++
++ if (!usb_ep || !ep_desc || ep_desc->bDescriptorType != USB_DT_ENDPOINT) {
++ DWC_WARN("%s, bad ep or descriptor\n", __func__);
++ return -EINVAL;
++ }
++ if (usb_ep == &gadget_wrapper->ep0) {
++ DWC_WARN("%s, bad ep(0)\n", __func__);
++ return -EINVAL;
++ }
++
++ /* Check FIFO size? */
++ if (!ep_desc->wMaxPacketSize) {
++ DWC_WARN("%s, bad %s maxpacket\n", __func__, usb_ep->name);
++ return -ERANGE;
++ }
++
++ if (!gadget_wrapper->driver ||
++ gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) {
++ DWC_WARN("%s, bogus device state\n", __func__);
++ return -ESHUTDOWN;
++ }
++
++ /* Delete after check - MAS */
++#if 0
++ nat = (uint32_t) ep_desc->wMaxPacketSize;
++ printk(KERN_ALERT "%s: nat (before) =%d\n", __func__, nat);
++ nat = (nat >> 11) & 0x03;
++ printk(KERN_ALERT "%s: nat (after) =%d\n", __func__, nat);
++#endif
++ retval = dwc_otg_pcd_ep_enable(gadget_wrapper->pcd,
++ (const uint8_t *)ep_desc,
++ (void *)usb_ep);
++ if (retval) {
++ DWC_WARN("dwc_otg_pcd_ep_enable failed\n");
++ return -EINVAL;
++ }
++
++ usb_ep->maxpacket = le16_to_cpu(ep_desc->wMaxPacketSize);
++
++ return 0;
++}
++
++/**
++ * This function is called when an EP is disabled due to disconnect or
++ * change in configuration. Any pending requests will terminate with a
++ * status of -ESHUTDOWN.
++ *
++ * This function modifies the dwc_otg_ep_t data structure for this EP,
++ * and then calls dwc_otg_ep_deactivate.
++ */
++static int ep_disable(struct usb_ep *usb_ep)
++{
++ int retval;
++
++ DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, usb_ep);
++ if (!usb_ep) {
++ DWC_DEBUGPL(DBG_PCD, "%s, %s not enabled\n", __func__,
++ usb_ep ? usb_ep->name : NULL);
++ return -EINVAL;
++ }
++
++ retval = dwc_otg_pcd_ep_disable(gadget_wrapper->pcd, usb_ep);
++ if (retval) {
++ retval = -EINVAL;
++ }
++
++ return retval;
++}
++
++/**
++ * This function allocates a request object to use with the specified
++ * endpoint.
++ *
++ * @param ep The endpoint to be used with with the request
++ * @param gfp_flags the GFP_* flags to use.
++ */
++static struct usb_request *dwc_otg_pcd_alloc_request(struct usb_ep *ep,
++ gfp_t gfp_flags)
++{
++ struct usb_request *usb_req;
++
++ DWC_DEBUGPL(DBG_PCDV, "%s(%p,%d)\n", __func__, ep, gfp_flags);
++ if (0 == ep) {
++ DWC_WARN("%s() %s\n", __func__, "Invalid EP!\n");
++ return 0;
++ }
++ usb_req = kmalloc(sizeof(*usb_req), gfp_flags);
++ if (0 == usb_req) {
++ DWC_WARN("%s() %s\n", __func__, "request allocation failed!\n");
++ return 0;
++ }
++ memset(usb_req, 0, sizeof(*usb_req));
++ usb_req->dma = DWC_DMA_ADDR_INVALID;
++
++ return usb_req;
++}
++
++/**
++ * This function frees a request object.
++ *
++ * @param ep The endpoint associated with the request
++ * @param req The request being freed
++ */
++static void dwc_otg_pcd_free_request(struct usb_ep *ep, struct usb_request *req)
++{
++ DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p)\n", __func__, ep, req);
++
++ if (0 == ep || 0 == req) {
++ DWC_WARN("%s() %s\n", __func__,
++ "Invalid ep or req argument!\n");
++ return;
++ }
++
++ kfree(req);
++}
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
++/**
++ * This function allocates an I/O buffer to be used for a transfer
++ * to/from the specified endpoint.
++ *
++ * @param usb_ep The endpoint to be used with with the request
++ * @param bytes The desired number of bytes for the buffer
++ * @param dma Pointer to the buffer's DMA address; must be valid
++ * @param gfp_flags the GFP_* flags to use.
++ * @return address of a new buffer or null is buffer could not be allocated.
++ */
++static void *dwc_otg_pcd_alloc_buffer(struct usb_ep *usb_ep, unsigned bytes,
++ dma_addr_t * dma, gfp_t gfp_flags)
++{
++ void *buf;
++ dwc_otg_pcd_t *pcd = 0;
++
++ pcd = gadget_wrapper->pcd;
++
++ DWC_DEBUGPL(DBG_PCDV, "%s(%p,%d,%p,%0x)\n", __func__, usb_ep, bytes,
++ dma, gfp_flags);
++
++ /* Check dword alignment */
++ if ((bytes & 0x3UL) != 0) {
++ DWC_WARN("%s() Buffer size is not a multiple of"
++ "DWORD size (%d)", __func__, bytes);
++ }
++
++ buf = dma_alloc_coherent(NULL, bytes, dma, gfp_flags);
++
++ /* Check dword alignment */
++ if (((int)buf & 0x3UL) != 0) {
++ DWC_WARN("%s() Buffer is not DWORD aligned (%p)",
++ __func__, buf);
++ }
++
++ return buf;
++}
++
++/**
++ * This function frees an I/O buffer that was allocated by alloc_buffer.
++ *
++ * @param usb_ep the endpoint associated with the buffer
++ * @param buf address of the buffer
++ * @param dma The buffer's DMA address
++ * @param bytes The number of bytes of the buffer
++ */
++static void dwc_otg_pcd_free_buffer(struct usb_ep *usb_ep, void *buf,
++ dma_addr_t dma, unsigned bytes)
++{
++ dwc_otg_pcd_t *pcd = 0;
++
++ pcd = gadget_wrapper->pcd;
++
++ DWC_DEBUGPL(DBG_PCDV, "%s(%p,%0x,%d)\n", __func__, buf, dma, bytes);
++
++ dma_free_coherent(NULL, bytes, buf, dma);
++}
++#endif
++
++/**
++ * This function is used to submit an I/O Request to an EP.
++ *
++ * - When the request completes the request's completion callback
++ * is called to return the request to the driver.
++ * - An EP, except control EPs, may have multiple requests
++ * pending.
++ * - Once submitted the request cannot be examined or modified.
++ * - Each request is turned into one or more packets.
++ * - A BULK EP can queue any amount of data; the transfer is
++ * packetized.
++ * - Zero length Packets are specified with the request 'zero'
++ * flag.
++ */
++static int ep_queue(struct usb_ep *usb_ep, struct usb_request *usb_req,
++ gfp_t gfp_flags)
++{
++ dwc_otg_pcd_t *pcd;
++ struct dwc_otg_pcd_ep *ep = NULL;
++ int retval = 0, is_isoc_ep = 0;
++ dma_addr_t dma_addr = DWC_DMA_ADDR_INVALID;
++
++ DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p,%d)\n",
++ __func__, usb_ep, usb_req, gfp_flags);
++
++ if (!usb_req || !usb_req->complete || !usb_req->buf) {
++ DWC_WARN("bad params\n");
++ return -EINVAL;
++ }
++
++ if (!usb_ep) {
++ DWC_WARN("bad ep\n");
++ return -EINVAL;
++ }
++
++ pcd = gadget_wrapper->pcd;
++ if (!gadget_wrapper->driver ||
++ gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) {
++ DWC_DEBUGPL(DBG_PCDV, "gadget.speed=%d\n",
++ gadget_wrapper->gadget.speed);
++ DWC_WARN("bogus device state\n");
++ return -ESHUTDOWN;
++ }
++
++ DWC_DEBUGPL(DBG_PCD, "%s queue req %p, len %d buf %p\n",
++ usb_ep->name, usb_req, usb_req->length, usb_req->buf);
++
++ usb_req->status = -EINPROGRESS;
++ usb_req->actual = 0;
++
++ ep = ep_from_handle(pcd, usb_ep);
++ if (ep == NULL)
++ is_isoc_ep = 0;
++ else
++ is_isoc_ep = (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) ? 1 : 0;
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
++ dma_addr = usb_req->dma;
++#else
++ if (GET_CORE_IF(pcd)->dma_enable) {
++ dwc_otg_device_t *otg_dev = gadget_wrapper->pcd->otg_dev;
++ struct device *dev = NULL;
++
++ if (otg_dev != NULL)
++ dev = DWC_OTG_OS_GETDEV(otg_dev->os_dep);
++
++ if (usb_req->length != 0 &&
++ usb_req->dma == DWC_DMA_ADDR_INVALID) {
++ dma_addr = dma_map_single(dev, usb_req->buf,
++ usb_req->length,
++ ep->dwc_ep.is_in ?
++ DMA_TO_DEVICE:
++ DMA_FROM_DEVICE);
++ }
++ }
++#endif
++
++#ifdef DWC_UTE_PER_IO
++ if (is_isoc_ep == 1) {
++ retval = dwc_otg_pcd_xiso_ep_queue(pcd, usb_ep, usb_req->buf, dma_addr,
++ usb_req->length, usb_req->zero, usb_req,
++ gfp_flags == GFP_ATOMIC ? 1 : 0, &usb_req->ext_req);
++ if (retval)
++ return -EINVAL;
++
++ return 0;
++ }
++#endif
++ retval = dwc_otg_pcd_ep_queue(pcd, usb_ep, usb_req->buf, dma_addr,
++ usb_req->length, usb_req->zero, usb_req,
++ gfp_flags == GFP_ATOMIC ? 1 : 0);
++ if (retval) {
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++/**
++ * This function cancels an I/O request from an EP.
++ */
++static int ep_dequeue(struct usb_ep *usb_ep, struct usb_request *usb_req)
++{
++ DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p)\n", __func__, usb_ep, usb_req);
++
++ if (!usb_ep || !usb_req) {
++ DWC_WARN("bad argument\n");
++ return -EINVAL;
++ }
++ if (!gadget_wrapper->driver ||
++ gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) {
++ DWC_WARN("bogus device state\n");
++ return -ESHUTDOWN;
++ }
++ if (dwc_otg_pcd_ep_dequeue(gadget_wrapper->pcd, usb_ep, usb_req)) {
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++/**
++ * usb_ep_set_halt stalls an endpoint.
++ *
++ * usb_ep_clear_halt clears an endpoint halt and resets its data
++ * toggle.
++ *
++ * Both of these functions are implemented with the same underlying
++ * function. The behavior depends on the value argument.
++ *
++ * @param[in] usb_ep the Endpoint to halt or clear halt.
++ * @param[in] value
++ * - 0 means clear_halt.
++ * - 1 means set_halt,
++ * - 2 means clear stall lock flag.
++ * - 3 means set stall lock flag.
++ */
++static int ep_halt(struct usb_ep *usb_ep, int value)
++{
++ int retval = 0;
++
++ DWC_DEBUGPL(DBG_PCD, "HALT %s %d\n", usb_ep->name, value);
++
++ if (!usb_ep) {
++ DWC_WARN("bad ep\n");
++ return -EINVAL;
++ }
++
++ retval = dwc_otg_pcd_ep_halt(gadget_wrapper->pcd, usb_ep, value);
++ if (retval == -DWC_E_AGAIN) {
++ return -EAGAIN;
++ } else if (retval) {
++ retval = -EINVAL;
++ }
++
++ return retval;
++}
++
++//#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30))
++#if 0
++/**
++ * ep_wedge: sets the halt feature and ignores clear requests
++ *
++ * @usb_ep: the endpoint being wedged
++ *
++ * Use this to stall an endpoint and ignore CLEAR_FEATURE(HALT_ENDPOINT)
++ * requests. If the gadget driver clears the halt status, it will
++ * automatically unwedge the endpoint.
++ *
++ * Returns zero on success, else negative errno. *
++ * Check usb_ep_set_wedge() at "usb_gadget.h" for details
++ */
++static int ep_wedge(struct usb_ep *usb_ep)
++{
++ int retval = 0;
++
++ DWC_DEBUGPL(DBG_PCD, "WEDGE %s\n", usb_ep->name);
++
++ if (!usb_ep) {
++ DWC_WARN("bad ep\n");
++ return -EINVAL;
++ }
++
++ retval = dwc_otg_pcd_ep_wedge(gadget_wrapper->pcd, usb_ep);
++ if (retval == -DWC_E_AGAIN) {
++ retval = -EAGAIN;
++ } else if (retval) {
++ retval = -EINVAL;
++ }
++
++ return retval;
++}
++#endif
++
++#ifdef DWC_EN_ISOC
++/**
++ * This function is used to submit an ISOC Transfer Request to an EP.
++ *
++ * - Every time a sync period completes the request's completion callback
++ * is called to provide data to the gadget driver.
++ * - Once submitted the request cannot be modified.
++ * - Each request is turned into periodic data packets untill ISO
++ * Transfer is stopped..
++ */
++static int iso_ep_start(struct usb_ep *usb_ep, struct usb_iso_request *req,
++ gfp_t gfp_flags)
++{
++ int retval = 0;
++
++ if (!req || !req->process_buffer || !req->buf0 || !req->buf1) {
++ DWC_WARN("bad params\n");
++ return -EINVAL;
++ }
++
++ if (!usb_ep) {
++ DWC_PRINTF("bad params\n");
++ return -EINVAL;
++ }
++
++ req->status = -EINPROGRESS;
++
++ retval =
++ dwc_otg_pcd_iso_ep_start(gadget_wrapper->pcd, usb_ep, req->buf0,
++ req->buf1, req->dma0, req->dma1,
++ req->sync_frame, req->data_pattern_frame,
++ req->data_per_frame,
++ req->
++ flags & USB_REQ_ISO_ASAP ? -1 :
++ req->start_frame, req->buf_proc_intrvl,
++ req, gfp_flags == GFP_ATOMIC ? 1 : 0);
++
++ if (retval) {
++ return -EINVAL;
++ }
++
++ return retval;
++}
++
++/**
++ * This function stops ISO EP Periodic Data Transfer.
++ */
++static int iso_ep_stop(struct usb_ep *usb_ep, struct usb_iso_request *req)
++{
++ int retval = 0;
++ if (!usb_ep) {
++ DWC_WARN("bad ep\n");
++ }
++
++ if (!gadget_wrapper->driver ||
++ gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) {
++ DWC_DEBUGPL(DBG_PCDV, "gadget.speed=%d\n",
++ gadget_wrapper->gadget.speed);
++ DWC_WARN("bogus device state\n");
++ }
++
++ dwc_otg_pcd_iso_ep_stop(gadget_wrapper->pcd, usb_ep, req);
++ if (retval) {
++ retval = -EINVAL;
++ }
++
++ return retval;
++}
++
++static struct usb_iso_request *alloc_iso_request(struct usb_ep *ep,
++ int packets, gfp_t gfp_flags)
++{
++ struct usb_iso_request *pReq = NULL;
++ uint32_t req_size;
++
++ req_size = sizeof(struct usb_iso_request);
++ req_size +=
++ (2 * packets * (sizeof(struct usb_gadget_iso_packet_descriptor)));
++
++ pReq = kmalloc(req_size, gfp_flags);
++ if (!pReq) {
++ DWC_WARN("Can't allocate Iso Request\n");
++ return 0;
++ }
++ pReq->iso_packet_desc0 = (void *)(pReq + 1);
++
++ pReq->iso_packet_desc1 = pReq->iso_packet_desc0 + packets;
++
++ return pReq;
++}
++
++static void free_iso_request(struct usb_ep *ep, struct usb_iso_request *req)
++{
++ kfree(req);
++}
++
++static struct usb_isoc_ep_ops dwc_otg_pcd_ep_ops = {
++ .ep_ops = {
++ .enable = ep_enable,
++ .disable = ep_disable,
++
++ .alloc_request = dwc_otg_pcd_alloc_request,
++ .free_request = dwc_otg_pcd_free_request,
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
++ .alloc_buffer = dwc_otg_pcd_alloc_buffer,
++ .free_buffer = dwc_otg_pcd_free_buffer,
++#endif
++
++ .queue = ep_queue,
++ .dequeue = ep_dequeue,
++
++ .set_halt = ep_halt,
++ .fifo_status = 0,
++ .fifo_flush = 0,
++ },
++ .iso_ep_start = iso_ep_start,
++ .iso_ep_stop = iso_ep_stop,
++ .alloc_iso_request = alloc_iso_request,
++ .free_iso_request = free_iso_request,
++};
++
++#else
++
++ int (*enable) (struct usb_ep *ep,
++ const struct usb_endpoint_descriptor *desc);
++ int (*disable) (struct usb_ep *ep);
++
++ struct usb_request *(*alloc_request) (struct usb_ep *ep,
++ gfp_t gfp_flags);
++ void (*free_request) (struct usb_ep *ep, struct usb_request *req);
++
++ int (*queue) (struct usb_ep *ep, struct usb_request *req,
++ gfp_t gfp_flags);
++ int (*dequeue) (struct usb_ep *ep, struct usb_request *req);
++
++ int (*set_halt) (struct usb_ep *ep, int value);
++ int (*set_wedge) (struct usb_ep *ep);
++
++ int (*fifo_status) (struct usb_ep *ep);
++ void (*fifo_flush) (struct usb_ep *ep);
++static struct usb_ep_ops dwc_otg_pcd_ep_ops = {
++ .enable = ep_enable,
++ .disable = ep_disable,
++
++ .alloc_request = dwc_otg_pcd_alloc_request,
++ .free_request = dwc_otg_pcd_free_request,
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
++ .alloc_buffer = dwc_otg_pcd_alloc_buffer,
++ .free_buffer = dwc_otg_pcd_free_buffer,
++#else
++ /* .set_wedge = ep_wedge, */
++ .set_wedge = NULL, /* uses set_halt instead */
++#endif
++
++ .queue = ep_queue,
++ .dequeue = ep_dequeue,
++
++ .set_halt = ep_halt,
++ .fifo_status = 0,
++ .fifo_flush = 0,
++
++};
++
++#endif /* _EN_ISOC_ */
++/* Gadget Operations */
++/**
++ * The following gadget operations will be implemented in the DWC_otg
++ * PCD. Functions in the API that are not described below are not
++ * implemented.
++ *
++ * The Gadget API provides wrapper functions for each of the function
++ * pointers defined in usb_gadget_ops. The Gadget Driver calls the
++ * wrapper function, which then calls the underlying PCD function. The
++ * following sections are named according to the wrapper functions
++ * (except for ioctl, which doesn't have a wrapper function). Within
++ * each section, the corresponding DWC_otg PCD function name is
++ * specified.
++ *
++ */
++
++/**
++ *Gets the USB Frame number of the last SOF.
++ */
++static int get_frame_number(struct usb_gadget *gadget)
++{
++ struct gadget_wrapper *d;
++
++ DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, gadget);
++
++ if (gadget == 0) {
++ return -ENODEV;
++ }
++
++ d = container_of(gadget, struct gadget_wrapper, gadget);
++ return dwc_otg_pcd_get_frame_number(d->pcd);
++}
++
++#ifdef CONFIG_USB_DWC_OTG_LPM
++static int test_lpm_enabled(struct usb_gadget *gadget)
++{
++ struct gadget_wrapper *d;
++
++ d = container_of(gadget, struct gadget_wrapper, gadget);
++
++ return dwc_otg_pcd_is_lpm_enabled(d->pcd);
++}
++#endif
++
++/**
++ * Initiates Session Request Protocol (SRP) to wakeup the host if no
++ * session is in progress. If a session is already in progress, but
++ * the device is suspended, remote wakeup signaling is started.
++ *
++ */
++static int wakeup(struct usb_gadget *gadget)
++{
++ struct gadget_wrapper *d;
++
++ DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, gadget);
++
++ if (gadget == 0) {
++ return -ENODEV;
++ } else {
++ d = container_of(gadget, struct gadget_wrapper, gadget);
++ }
++ dwc_otg_pcd_wakeup(d->pcd);
++ return 0;
++}
++
++static const struct usb_gadget_ops dwc_otg_pcd_ops = {
++ .get_frame = get_frame_number,
++ .wakeup = wakeup,
++#ifdef CONFIG_USB_DWC_OTG_LPM
++ .lpm_support = test_lpm_enabled,
++#endif
++ // current versions must always be self-powered
++};
++
++static int _setup(dwc_otg_pcd_t * pcd, uint8_t * bytes)
++{
++ int retval = -DWC_E_NOT_SUPPORTED;
++ if (gadget_wrapper->driver && gadget_wrapper->driver->setup) {
++ retval = gadget_wrapper->driver->setup(&gadget_wrapper->gadget,
++ (struct usb_ctrlrequest
++ *)bytes);
++ }
++
++ if (retval == -ENOTSUPP) {
++ retval = -DWC_E_NOT_SUPPORTED;
++ } else if (retval < 0) {
++ retval = -DWC_E_INVALID;
++ }
++
++ return retval;
++}
++
++#ifdef DWC_EN_ISOC
++static int _isoc_complete(dwc_otg_pcd_t * pcd, void *ep_handle,
++ void *req_handle, int proc_buf_num)
++{
++ int i, packet_count;
++ struct usb_gadget_iso_packet_descriptor *iso_packet = 0;
++ struct usb_iso_request *iso_req = req_handle;
++
++ if (proc_buf_num) {
++ iso_packet = iso_req->iso_packet_desc1;
++ } else {
++ iso_packet = iso_req->iso_packet_desc0;
++ }
++ packet_count =
++ dwc_otg_pcd_get_iso_packet_count(pcd, ep_handle, req_handle);
++ for (i = 0; i < packet_count; ++i) {
++ int status;
++ int actual;
++ int offset;
++ dwc_otg_pcd_get_iso_packet_params(pcd, ep_handle, req_handle,
++ i, &status, &actual, &offset);
++ switch (status) {
++ case -DWC_E_NO_DATA:
++ status = -ENODATA;
++ break;
++ default:
++ if (status) {
++ DWC_PRINTF("unknown status in isoc packet\n");
++ }
++
++ }
++ iso_packet[i].status = status;
++ iso_packet[i].offset = offset;
++ iso_packet[i].actual_length = actual;
++ }
++
++ iso_req->status = 0;
++ iso_req->process_buffer(ep_handle, iso_req);
++
++ return 0;
++}
++#endif /* DWC_EN_ISOC */
++
++#ifdef DWC_UTE_PER_IO
++/**
++ * Copy the contents of the extended request to the Linux usb_request's
++ * extended part and call the gadget's completion.
++ *
++ * @param pcd Pointer to the pcd structure
++ * @param ep_handle Void pointer to the usb_ep structure
++ * @param req_handle Void pointer to the usb_request structure
++ * @param status Request status returned from the portable logic
++ * @param ereq_port Void pointer to the extended request structure
++ * created in the the portable part that contains the
++ * results of the processed iso packets.
++ */
++static int _xisoc_complete(dwc_otg_pcd_t * pcd, void *ep_handle,
++ void *req_handle, int32_t status, void *ereq_port)
++{
++ struct dwc_ute_iso_req_ext *ereqorg = NULL;
++ struct dwc_iso_xreq_port *ereqport = NULL;
++ struct dwc_ute_iso_packet_descriptor *desc_org = NULL;
++ int i;
++ struct usb_request *req;
++ //struct dwc_ute_iso_packet_descriptor *
++ //int status = 0;
++
++ req = (struct usb_request *)req_handle;
++ ereqorg = &req->ext_req;
++ ereqport = (struct dwc_iso_xreq_port *)ereq_port;
++ desc_org = ereqorg->per_io_frame_descs;
++
++ if (req && req->complete) {
++ /* Copy the request data from the portable logic to our request */
++ for (i = 0; i < ereqport->pio_pkt_count; i++) {
++ desc_org[i].actual_length =
++ ereqport->per_io_frame_descs[i].actual_length;
++ desc_org[i].status =
++ ereqport->per_io_frame_descs[i].status;
++ }
++
++ switch (status) {
++ case -DWC_E_SHUTDOWN:
++ req->status = -ESHUTDOWN;
++ break;
++ case -DWC_E_RESTART:
++ req->status = -ECONNRESET;
++ break;
++ case -DWC_E_INVALID:
++ req->status = -EINVAL;
++ break;
++ case -DWC_E_TIMEOUT:
++ req->status = -ETIMEDOUT;
++ break;
++ default:
++ req->status = status;
++ }
++
++ /* And call the gadget's completion */
++ req->complete(ep_handle, req);
++ }
++
++ return 0;
++}
++#endif /* DWC_UTE_PER_IO */
++
++static int _complete(dwc_otg_pcd_t * pcd, void *ep_handle,
++ void *req_handle, int32_t status, uint32_t actual)
++{
++ struct usb_request *req = (struct usb_request *)req_handle;
++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,27)
++ struct dwc_otg_pcd_ep *ep = NULL;
++#endif
++
++ if (req && req->complete) {
++ switch (status) {
++ case -DWC_E_SHUTDOWN:
++ req->status = -ESHUTDOWN;
++ break;
++ case -DWC_E_RESTART:
++ req->status = -ECONNRESET;
++ break;
++ case -DWC_E_INVALID:
++ req->status = -EINVAL;
++ break;
++ case -DWC_E_TIMEOUT:
++ req->status = -ETIMEDOUT;
++ break;
++ default:
++ req->status = status;
++
++ }
++
++ req->actual = actual;
++ DWC_SPINUNLOCK(pcd->lock);
++ req->complete(ep_handle, req);
++ DWC_SPINLOCK(pcd->lock);
++ }
++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,27)
++ ep = ep_from_handle(pcd, ep_handle);
++ if (GET_CORE_IF(pcd)->dma_enable) {
++ if (req->length != 0) {
++ dwc_otg_device_t *otg_dev = gadget_wrapper->pcd->otg_dev;
++ struct device *dev = NULL;
++
++ if (otg_dev != NULL)
++ dev = DWC_OTG_OS_GETDEV(otg_dev->os_dep);
++
++ dma_unmap_single(dev, req->dma, req->length,
++ ep->dwc_ep.is_in ?
++ DMA_TO_DEVICE: DMA_FROM_DEVICE);
++ }
++ }
++#endif
++
++ return 0;
++}
++
++static int _connect(dwc_otg_pcd_t * pcd, int speed)
++{
++ gadget_wrapper->gadget.speed = speed;
++ return 0;
++}
++
++static int _disconnect(dwc_otg_pcd_t * pcd)
++{
++ if (gadget_wrapper->driver && gadget_wrapper->driver->disconnect) {
++ gadget_wrapper->driver->disconnect(&gadget_wrapper->gadget);
++ }
++ return 0;
++}
++
++static int _resume(dwc_otg_pcd_t * pcd)
++{
++ if (gadget_wrapper->driver && gadget_wrapper->driver->resume) {
++ gadget_wrapper->driver->resume(&gadget_wrapper->gadget);
++ }
++
++ return 0;
++}
++
++static int _suspend(dwc_otg_pcd_t * pcd)
++{
++ if (gadget_wrapper->driver && gadget_wrapper->driver->suspend) {
++ gadget_wrapper->driver->suspend(&gadget_wrapper->gadget);
++ }
++ return 0;
++}
++
++/**
++ * This function updates the otg values in the gadget structure.
++ */
++static int _hnp_changed(dwc_otg_pcd_t * pcd)
++{
++
++ if (!gadget_wrapper->gadget.is_otg)
++ return 0;
++
++ gadget_wrapper->gadget.b_hnp_enable = get_b_hnp_enable(pcd);
++ gadget_wrapper->gadget.a_hnp_support = get_a_hnp_support(pcd);
++ gadget_wrapper->gadget.a_alt_hnp_support = get_a_alt_hnp_support(pcd);
++ return 0;
++}
++
++static int _reset(dwc_otg_pcd_t * pcd)
++{
++ return 0;
++}
++
++#ifdef DWC_UTE_CFI
++static int _cfi_setup(dwc_otg_pcd_t * pcd, void *cfi_req)
++{
++ int retval = -DWC_E_INVALID;
++ if (gadget_wrapper->driver->cfi_feature_setup) {
++ retval =
++ gadget_wrapper->driver->
++ cfi_feature_setup(&gadget_wrapper->gadget,
++ (struct cfi_usb_ctrlrequest *)cfi_req);
++ }
++
++ return retval;
++}
++#endif
++
++static const struct dwc_otg_pcd_function_ops fops = {
++ .complete = _complete,
++#ifdef DWC_EN_ISOC
++ .isoc_complete = _isoc_complete,
++#endif
++ .setup = _setup,
++ .disconnect = _disconnect,
++ .connect = _connect,
++ .resume = _resume,
++ .suspend = _suspend,
++ .hnp_changed = _hnp_changed,
++ .reset = _reset,
++#ifdef DWC_UTE_CFI
++ .cfi_setup = _cfi_setup,
++#endif
++#ifdef DWC_UTE_PER_IO
++ .xisoc_complete = _xisoc_complete,
++#endif
++};
++
++/**
++ * This function is the top level PCD interrupt handler.
++ */
++static irqreturn_t dwc_otg_pcd_irq(int irq, void *dev)
++{
++ dwc_otg_pcd_t *pcd = dev;
++ int32_t retval = IRQ_NONE;
++
++ retval = dwc_otg_pcd_handle_intr(pcd);
++ if (retval != 0) {
++ S3C2410X_CLEAR_EINTPEND();
++ }
++ return IRQ_RETVAL(retval);
++}
++
++/**
++ * This function initialized the usb_ep structures to there default
++ * state.
++ *
++ * @param d Pointer on gadget_wrapper.
++ */
++void gadget_add_eps(struct gadget_wrapper *d)
++{
++ static const char *names[] = {
++
++ "ep0",
++ "ep1in",
++ "ep2in",
++ "ep3in",
++ "ep4in",
++ "ep5in",
++ "ep6in",
++ "ep7in",
++ "ep8in",
++ "ep9in",
++ "ep10in",
++ "ep11in",
++ "ep12in",
++ "ep13in",
++ "ep14in",
++ "ep15in",
++ "ep1out",
++ "ep2out",
++ "ep3out",
++ "ep4out",
++ "ep5out",
++ "ep6out",
++ "ep7out",
++ "ep8out",
++ "ep9out",
++ "ep10out",
++ "ep11out",
++ "ep12out",
++ "ep13out",
++ "ep14out",
++ "ep15out"
++ };
++
++ int i;
++ struct usb_ep *ep;
++ int8_t dev_endpoints;
++
++ DWC_DEBUGPL(DBG_PCDV, "%s\n", __func__);
++
++ INIT_LIST_HEAD(&d->gadget.ep_list);
++ d->gadget.ep0 = &d->ep0;
++ d->gadget.speed = USB_SPEED_UNKNOWN;
++
++ INIT_LIST_HEAD(&d->gadget.ep0->ep_list);
++
++ /**
++ * Initialize the EP0 structure.
++ */
++ ep = &d->ep0;
++
++ /* Init the usb_ep structure. */
++ ep->name = names[0];
++ ep->ops = (struct usb_ep_ops *)&dwc_otg_pcd_ep_ops;
++
++ /**
++ * @todo NGS: What should the max packet size be set to
++ * here? Before EP type is set?
++ */
++ ep->maxpacket = MAX_PACKET_SIZE;
++ dwc_otg_pcd_ep_enable(d->pcd, NULL, ep);
++
++ list_add_tail(&ep->ep_list, &d->gadget.ep_list);
++
++ /**
++ * Initialize the EP structures.
++ */
++ dev_endpoints = d->pcd->core_if->dev_if->num_in_eps;
++
++ for (i = 0; i < dev_endpoints; i++) {
++ ep = &d->in_ep[i];
++
++ /* Init the usb_ep structure. */
++ ep->name = names[d->pcd->in_ep[i].dwc_ep.num];
++ ep->ops = (struct usb_ep_ops *)&dwc_otg_pcd_ep_ops;
++
++ /**
++ * @todo NGS: What should the max packet size be set to
++ * here? Before EP type is set?
++ */
++ ep->maxpacket = MAX_PACKET_SIZE;
++ list_add_tail(&ep->ep_list, &d->gadget.ep_list);
++ }
++
++ dev_endpoints = d->pcd->core_if->dev_if->num_out_eps;
++
++ for (i = 0; i < dev_endpoints; i++) {
++ ep = &d->out_ep[i];
++
++ /* Init the usb_ep structure. */
++ ep->name = names[15 + d->pcd->out_ep[i].dwc_ep.num];
++ ep->ops = (struct usb_ep_ops *)&dwc_otg_pcd_ep_ops;
++
++ /**
++ * @todo NGS: What should the max packet size be set to
++ * here? Before EP type is set?
++ */
++ ep->maxpacket = MAX_PACKET_SIZE;
++
++ list_add_tail(&ep->ep_list, &d->gadget.ep_list);
++ }
++
++ /* remove ep0 from the list. There is a ep0 pointer. */
++ list_del_init(&d->ep0.ep_list);
++
++ d->ep0.maxpacket = MAX_EP0_SIZE;
++}
++
++/**
++ * This function releases the Gadget device.
++ * required by device_unregister().
++ *
++ * @todo Should this do something? Should it free the PCD?
++ */
++static void dwc_otg_pcd_gadget_release(struct device *dev)
++{
++ DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, dev);
++}
++
++static struct gadget_wrapper *alloc_wrapper(dwc_bus_dev_t *_dev)
++{
++ static char pcd_name[] = "dwc_otg_pcd";
++ dwc_otg_device_t *otg_dev = DWC_OTG_BUSDRVDATA(_dev);
++ struct gadget_wrapper *d;
++ int retval;
++
++ d = DWC_ALLOC(sizeof(*d));
++ if (d == NULL) {
++ return NULL;
++ }
++
++ memset(d, 0, sizeof(*d));
++
++ d->gadget.name = pcd_name;
++ d->pcd = otg_dev->pcd;
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)
++ strcpy(d->gadget.dev.bus_id, "gadget");
++#else
++ dev_set_name(&d->gadget.dev, "%s", "gadget");
++#endif
++
++ d->gadget.dev.parent = &_dev->dev;
++ d->gadget.dev.release = dwc_otg_pcd_gadget_release;
++ d->gadget.ops = &dwc_otg_pcd_ops;
++ d->gadget.max_speed = dwc_otg_pcd_is_dualspeed(otg_dev->pcd) ? USB_SPEED_HIGH:USB_SPEED_FULL;
++ d->gadget.is_otg = dwc_otg_pcd_is_otg(otg_dev->pcd);
++
++ d->driver = 0;
++ /* Register the gadget device */
++ retval = device_register(&d->gadget.dev);
++ if (retval != 0) {
++ DWC_ERROR("device_register failed\n");
++ DWC_FREE(d);
++ return NULL;
++ }
++
++ return d;
++}
++
++static void free_wrapper(struct gadget_wrapper *d)
++{
++ if (d->driver) {
++ /* should have been done already by driver model core */
++ DWC_WARN("driver '%s' is still registered\n",
++ d->driver->driver.name);
++ usb_gadget_unregister_driver(d->driver);
++ }
++
++ device_unregister(&d->gadget.dev);
++ DWC_FREE(d);
++}
++
++/**
++ * This function initialized the PCD portion of the driver.
++ *
++ */
++int pcd_init(dwc_bus_dev_t *_dev)
++{
++ dwc_otg_device_t *otg_dev = DWC_OTG_BUSDRVDATA(_dev);
++ int retval = 0;
++
++ DWC_DEBUGPL(DBG_PCDV, "%s(%p) otg_dev=%p\n", __func__, _dev, otg_dev);
++
++ otg_dev->pcd = dwc_otg_pcd_init(otg_dev->core_if);
++
++ if (!otg_dev->pcd) {
++ DWC_ERROR("dwc_otg_pcd_init failed\n");
++ return -ENOMEM;
++ }
++
++ otg_dev->pcd->otg_dev = otg_dev;
++ gadget_wrapper = alloc_wrapper(_dev);
++
++ /*
++ * Initialize EP structures
++ */
++ gadget_add_eps(gadget_wrapper);
++ /*
++ * Setup interupt handler
++ */
++#ifdef PLATFORM_INTERFACE
++ DWC_DEBUGPL(DBG_ANY, "registering handler for irq%d\n",
++ platform_get_irq(_dev, fiq_enable ? 0 : 1));
++ retval = request_irq(platform_get_irq(_dev, fiq_enable ? 0 : 1), dwc_otg_pcd_irq,
++ IRQF_SHARED, gadget_wrapper->gadget.name,
++ otg_dev->pcd);
++ if (retval != 0) {
++ DWC_ERROR("request of irq%d failed\n",
++ platform_get_irq(_dev, fiq_enable ? 0 : 1));
++ free_wrapper(gadget_wrapper);
++ return -EBUSY;
++ }
++#else
++ DWC_DEBUGPL(DBG_ANY, "registering handler for irq%d\n",
++ _dev->irq);
++ retval = request_irq(_dev->irq, dwc_otg_pcd_irq,
++ IRQF_SHARED | IRQF_DISABLED,
++ gadget_wrapper->gadget.name, otg_dev->pcd);
++ if (retval != 0) {
++ DWC_ERROR("request of irq%d failed\n", _dev->irq);
++ free_wrapper(gadget_wrapper);
++ return -EBUSY;
++ }
++#endif
++
++ dwc_otg_pcd_start(gadget_wrapper->pcd, &fops);
++
++ return retval;
++}
++
++/**
++ * Cleanup the PCD.
++ */
++void pcd_remove(dwc_bus_dev_t *_dev)
++{
++ dwc_otg_device_t *otg_dev = DWC_OTG_BUSDRVDATA(_dev);
++ dwc_otg_pcd_t *pcd = otg_dev->pcd;
++
++ DWC_DEBUGPL(DBG_PCDV, "%s(%p) otg_dev %p\n", __func__, _dev, otg_dev);
++
++ /*
++ * Free the IRQ
++ */
++#ifdef PLATFORM_INTERFACE
++ free_irq(platform_get_irq(_dev, 0), pcd);
++#else
++ free_irq(_dev->irq, pcd);
++#endif
++ dwc_otg_pcd_remove(otg_dev->pcd);
++ free_wrapper(gadget_wrapper);
++ otg_dev->pcd = 0;
++}
++
++/**
++ * This function registers a gadget driver with the PCD.
++ *
++ * When a driver is successfully registered, it will receive control
++ * requests including set_configuration(), which enables non-control
++ * requests. then usb traffic follows until a disconnect is reported.
++ * then a host may connect again, or the driver might get unbound.
++ *
++ * @param driver The driver being registered
++ * @param bind The bind function of gadget driver
++ */
++
++int usb_gadget_probe_driver(struct usb_gadget_driver *driver)
++{
++ int retval;
++
++ DWC_DEBUGPL(DBG_PCD, "registering gadget driver '%s'\n",
++ driver->driver.name);
++
++ if (!driver || driver->max_speed == USB_SPEED_UNKNOWN ||
++ !driver->bind ||
++ !driver->unbind || !driver->disconnect || !driver->setup) {
++ DWC_DEBUGPL(DBG_PCDV, "EINVAL\n");
++ return -EINVAL;
++ }
++ if (gadget_wrapper == 0) {
++ DWC_DEBUGPL(DBG_PCDV, "ENODEV\n");
++ return -ENODEV;
++ }
++ if (gadget_wrapper->driver != 0) {
++ DWC_DEBUGPL(DBG_PCDV, "EBUSY (%p)\n", gadget_wrapper->driver);
++ return -EBUSY;
++ }
++
++ /* hook up the driver */
++ gadget_wrapper->driver = driver;
++ gadget_wrapper->gadget.dev.driver = &driver->driver;
++
++ DWC_DEBUGPL(DBG_PCD, "bind to driver %s\n", driver->driver.name);
++ retval = driver->bind(&gadget_wrapper->gadget, gadget_wrapper->driver);
++ if (retval) {
++ DWC_ERROR("bind to driver %s --> error %d\n",
++ driver->driver.name, retval);
++ gadget_wrapper->driver = 0;
++ gadget_wrapper->gadget.dev.driver = 0;
++ return retval;
++ }
++ DWC_DEBUGPL(DBG_ANY, "registered gadget driver '%s'\n",
++ driver->driver.name);
++ return 0;
++}
++EXPORT_SYMBOL(usb_gadget_probe_driver);
++
++/**
++ * This function unregisters a gadget driver
++ *
++ * @param driver The driver being unregistered
++ */
++int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
++{
++ //DWC_DEBUGPL(DBG_PCDV,"%s(%p)\n", __func__, _driver);
++
++ if (gadget_wrapper == 0) {
++ DWC_DEBUGPL(DBG_ANY, "%s Return(%d): s_pcd==0\n", __func__,
++ -ENODEV);
++ return -ENODEV;
++ }
++ if (driver == 0 || driver != gadget_wrapper->driver) {
++ DWC_DEBUGPL(DBG_ANY, "%s Return(%d): driver?\n", __func__,
++ -EINVAL);
++ return -EINVAL;
++ }
++
++ driver->unbind(&gadget_wrapper->gadget);
++ gadget_wrapper->driver = 0;
++
++ DWC_DEBUGPL(DBG_ANY, "unregistered driver '%s'\n", driver->driver.name);
++ return 0;
++}
++
++EXPORT_SYMBOL(usb_gadget_unregister_driver);
++
++#endif /* DWC_HOST_ONLY */
+diff -Nur linux-4.1.3/drivers/usb/host/dwc_otg/dwc_otg_regs.h linux-xbian-rpi/drivers/usb/host/dwc_otg/dwc_otg_regs.h
+--- linux-4.1.3/drivers/usb/host/dwc_otg/dwc_otg_regs.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/usb/host/dwc_otg/dwc_otg_regs.h 2015-07-28 01:20:58.449142252 +0200
+@@ -0,0 +1,2550 @@
++/* ==========================================================================
++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_regs.h $
++ * $Revision: #98 $
++ * $Date: 2012/08/10 $
++ * $Change: 2047372 $
++ *
++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++ * otherwise expressly agreed to in writing between Synopsys and you.
++ *
++ * The Software IS NOT an item of Licensed Software or Licensed Product under
++ * any End User Software License Agreement or Agreement for Licensed Product
++ * with Synopsys or any supplement thereto. You are permitted to use and
++ * redistribute this Software in source and binary forms, with or without
++ * modification, provided that redistributions of source code must retain this
++ * notice. You may not view, use, disclose, copy or distribute this file or
++ * any information contained herein except pursuant to this license grant from
++ * Synopsys. If you do not agree with this notice, including the disclaimer
++ * below, then you are not authorized to use the Software.
++ *
++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++ * DAMAGE.
++ * ========================================================================== */
++
++#ifndef __DWC_OTG_REGS_H__
++#define __DWC_OTG_REGS_H__
++
++#include "dwc_otg_core_if.h"
++
++/**
++ * @file
++ *
++ * This file contains the data structures for accessing the DWC_otg core registers.
++ *
++ * The application interfaces with the HS OTG core by reading from and
++ * writing to the Control and Status Register (CSR) space through the
++ * AHB Slave interface. These registers are 32 bits wide, and the
++ * addresses are 32-bit-block aligned.
++ * CSRs are classified as follows:
++ * - Core Global Registers
++ * - Device Mode Registers
++ * - Device Global Registers
++ * - Device Endpoint Specific Registers
++ * - Host Mode Registers
++ * - Host Global Registers
++ * - Host Port CSRs
++ * - Host Channel Specific Registers
++ *
++ * Only the Core Global registers can be accessed in both Device and
++ * Host modes. When the HS OTG core is operating in one mode, either
++ * Device or Host, the application must not access registers from the
++ * other mode. When the core switches from one mode to another, the
++ * registers in the new mode of operation must be reprogrammed as they
++ * would be after a power-on reset.
++ */
++
++/****************************************************************************/
++/** DWC_otg Core registers .
++ * The dwc_otg_core_global_regs structure defines the size
++ * and relative field offsets for the Core Global registers.
++ */
++typedef struct dwc_otg_core_global_regs {
++ /** OTG Control and Status Register. <i>Offset: 000h</i> */
++ volatile uint32_t gotgctl;
++ /** OTG Interrupt Register. <i>Offset: 004h</i> */
++ volatile uint32_t gotgint;
++ /**Core AHB Configuration Register. <i>Offset: 008h</i> */
++ volatile uint32_t gahbcfg;
++
++#define DWC_GLBINTRMASK 0x0001
++#define DWC_DMAENABLE 0x0020
++#define DWC_NPTXEMPTYLVL_EMPTY 0x0080
++#define DWC_NPTXEMPTYLVL_HALFEMPTY 0x0000
++#define DWC_PTXEMPTYLVL_EMPTY 0x0100
++#define DWC_PTXEMPTYLVL_HALFEMPTY 0x0000
++
++ /**Core USB Configuration Register. <i>Offset: 00Ch</i> */
++ volatile uint32_t gusbcfg;
++ /**Core Reset Register. <i>Offset: 010h</i> */
++ volatile uint32_t grstctl;
++ /**Core Interrupt Register. <i>Offset: 014h</i> */
++ volatile uint32_t gintsts;
++ /**Core Interrupt Mask Register. <i>Offset: 018h</i> */
++ volatile uint32_t gintmsk;
++ /**Receive Status Queue Read Register (Read Only). <i>Offset: 01Ch</i> */
++ volatile uint32_t grxstsr;
++ /**Receive Status Queue Read & POP Register (Read Only). <i>Offset: 020h</i>*/
++ volatile uint32_t grxstsp;
++ /**Receive FIFO Size Register. <i>Offset: 024h</i> */
++ volatile uint32_t grxfsiz;
++ /**Non Periodic Transmit FIFO Size Register. <i>Offset: 028h</i> */
++ volatile uint32_t gnptxfsiz;
++ /**Non Periodic Transmit FIFO/Queue Status Register (Read
++ * Only). <i>Offset: 02Ch</i> */
++ volatile uint32_t gnptxsts;
++ /**I2C Access Register. <i>Offset: 030h</i> */
++ volatile uint32_t gi2cctl;
++ /**PHY Vendor Control Register. <i>Offset: 034h</i> */
++ volatile uint32_t gpvndctl;
++ /**General Purpose Input/Output Register. <i>Offset: 038h</i> */
++ volatile uint32_t ggpio;
++ /**User ID Register. <i>Offset: 03Ch</i> */
++ volatile uint32_t guid;
++ /**Synopsys ID Register (Read Only). <i>Offset: 040h</i> */
++ volatile uint32_t gsnpsid;
++ /**User HW Config1 Register (Read Only). <i>Offset: 044h</i> */
++ volatile uint32_t ghwcfg1;
++ /**User HW Config2 Register (Read Only). <i>Offset: 048h</i> */
++ volatile uint32_t ghwcfg2;
++#define DWC_SLAVE_ONLY_ARCH 0
++#define DWC_EXT_DMA_ARCH 1
++#define DWC_INT_DMA_ARCH 2
++
++#define DWC_MODE_HNP_SRP_CAPABLE 0
++#define DWC_MODE_SRP_ONLY_CAPABLE 1
++#define DWC_MODE_NO_HNP_SRP_CAPABLE 2
++#define DWC_MODE_SRP_CAPABLE_DEVICE 3
++#define DWC_MODE_NO_SRP_CAPABLE_DEVICE 4
++#define DWC_MODE_SRP_CAPABLE_HOST 5
++#define DWC_MODE_NO_SRP_CAPABLE_HOST 6
++
++ /**User HW Config3 Register (Read Only). <i>Offset: 04Ch</i> */
++ volatile uint32_t ghwcfg3;
++ /**User HW Config4 Register (Read Only). <i>Offset: 050h</i>*/
++ volatile uint32_t ghwcfg4;
++ /** Core LPM Configuration register <i>Offset: 054h</i>*/
++ volatile uint32_t glpmcfg;
++ /** Global PowerDn Register <i>Offset: 058h</i> */
++ volatile uint32_t gpwrdn;
++ /** Global DFIFO SW Config Register <i>Offset: 05Ch</i> */
++ volatile uint32_t gdfifocfg;
++ /** ADP Control Register <i>Offset: 060h</i> */
++ volatile uint32_t adpctl;
++ /** Reserved <i>Offset: 064h-0FFh</i> */
++ volatile uint32_t reserved39[39];
++ /** Host Periodic Transmit FIFO Size Register. <i>Offset: 100h</i> */
++ volatile uint32_t hptxfsiz;
++ /** Device Periodic Transmit FIFO#n Register if dedicated fifos are disabled,
++ otherwise Device Transmit FIFO#n Register.
++ * <i>Offset: 104h + (FIFO_Number-1)*04h, 1 <= FIFO Number <= 15 (1<=n<=15).</i> */
++ volatile uint32_t dtxfsiz[15];
++} dwc_otg_core_global_regs_t;
++
++/**
++ * This union represents the bit fields of the Core OTG Control
++ * and Status Register (GOTGCTL). Set the bits using the bit
++ * fields then write the <i>d32</i> value to the register.
++ */
++typedef union gotgctl_data {
++ /** raw register data */
++ uint32_t d32;
++ /** register bits */
++ struct {
++ unsigned sesreqscs:1;
++ unsigned sesreq:1;
++ unsigned vbvalidoven:1;
++ unsigned vbvalidovval:1;
++ unsigned avalidoven:1;
++ unsigned avalidovval:1;
++ unsigned bvalidoven:1;
++ unsigned bvalidovval:1;
++ unsigned hstnegscs:1;
++ unsigned hnpreq:1;
++ unsigned hstsethnpen:1;
++ unsigned devhnpen:1;
++ unsigned reserved12_15:4;
++ unsigned conidsts:1;
++ unsigned dbnctime:1;
++ unsigned asesvld:1;
++ unsigned bsesvld:1;
++ unsigned otgver:1;
++ unsigned reserved1:1;
++ unsigned multvalidbc:5;
++ unsigned chirpen:1;
++ unsigned reserved28_31:4;
++ } b;
++} gotgctl_data_t;
++
++/**
++ * This union represents the bit fields of the Core OTG Interrupt Register
++ * (GOTGINT). Set/clear the bits using the bit fields then write the <i>d32</i>
++ * value to the register.
++ */
++typedef union gotgint_data {
++ /** raw register data */
++ uint32_t d32;
++ /** register bits */
++ struct {
++ /** Current Mode */
++ unsigned reserved0_1:2;
++
++ /** Session End Detected */
++ unsigned sesenddet:1;
++
++ unsigned reserved3_7:5;
++
++ /** Session Request Success Status Change */
++ unsigned sesreqsucstschng:1;
++ /** Host Negotiation Success Status Change */
++ unsigned hstnegsucstschng:1;
++
++ unsigned reserved10_16:7;
++
++ /** Host Negotiation Detected */
++ unsigned hstnegdet:1;
++ /** A-Device Timeout Change */
++ unsigned adevtoutchng:1;
++ /** Debounce Done */
++ unsigned debdone:1;
++ /** Multi-Valued input changed */
++ unsigned mvic:1;
++
++ unsigned reserved31_21:11;
++
++ } b;
++} gotgint_data_t;
++
++/**
++ * This union represents the bit fields of the Core AHB Configuration
++ * Register (GAHBCFG). Set/clear the bits using the bit fields then
++ * write the <i>d32</i> value to the register.
++ */
++typedef union gahbcfg_data {
++ /** raw register data */
++ uint32_t d32;
++ /** register bits */
++ struct {
++ unsigned glblintrmsk:1;
++#define DWC_GAHBCFG_GLBINT_ENABLE 1
++
++ unsigned hburstlen:4;
++#define DWC_GAHBCFG_INT_DMA_BURST_SINGLE 0
++#define DWC_GAHBCFG_INT_DMA_BURST_INCR 1
++#define DWC_GAHBCFG_INT_DMA_BURST_INCR4 3
++#define DWC_GAHBCFG_INT_DMA_BURST_INCR8 5
++#define DWC_GAHBCFG_INT_DMA_BURST_INCR16 7
++
++ unsigned dmaenable:1;
++#define DWC_GAHBCFG_DMAENABLE 1
++ unsigned reserved:1;
++ unsigned nptxfemplvl_txfemplvl:1;
++ unsigned ptxfemplvl:1;
++#define DWC_GAHBCFG_TXFEMPTYLVL_EMPTY 1
++#define DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY 0
++ unsigned reserved9_20:12;
++ unsigned remmemsupp:1;
++ unsigned notialldmawrit:1;
++ unsigned ahbsingle:1;
++ unsigned reserved24_31:8;
++ } b;
++} gahbcfg_data_t;
++
++/**
++ * This union represents the bit fields of the Core USB Configuration
++ * Register (GUSBCFG). Set the bits using the bit fields then write
++ * the <i>d32</i> value to the register.
++ */
++typedef union gusbcfg_data {
++ /** raw register data */
++ uint32_t d32;
++ /** register bits */
++ struct {
++ unsigned toutcal:3;
++ unsigned phyif:1;
++ unsigned ulpi_utmi_sel:1;
++ unsigned fsintf:1;
++ unsigned physel:1;
++ unsigned ddrsel:1;
++ unsigned srpcap:1;
++ unsigned hnpcap:1;
++ unsigned usbtrdtim:4;
++ unsigned reserved1:1;
++ unsigned phylpwrclksel:1;
++ unsigned otgutmifssel:1;
++ unsigned ulpi_fsls:1;
++ unsigned ulpi_auto_res:1;
++ unsigned ulpi_clk_sus_m:1;
++ unsigned ulpi_ext_vbus_drv:1;
++ unsigned ulpi_int_vbus_indicator:1;
++ unsigned term_sel_dl_pulse:1;
++ unsigned indicator_complement:1;
++ unsigned indicator_pass_through:1;
++ unsigned ulpi_int_prot_dis:1;
++ unsigned ic_usb_cap:1;
++ unsigned ic_traffic_pull_remove:1;
++ unsigned tx_end_delay:1;
++ unsigned force_host_mode:1;
++ unsigned force_dev_mode:1;
++ unsigned reserved31:1;
++ } b;
++} gusbcfg_data_t;
++
++/**
++ * This union represents the bit fields of the Core Reset Register
++ * (GRSTCTL). Set/clear the bits using the bit fields then write the
++ * <i>d32</i> value to the register.
++ */
++typedef union grstctl_data {
++ /** raw register data */
++ uint32_t d32;
++ /** register bits */
++ struct {
++ /** Core Soft Reset (CSftRst) (Device and Host)
++ *
++ * The application can flush the control logic in the
++ * entire core using this bit. This bit resets the
++ * pipelines in the AHB Clock domain as well as the
++ * PHY Clock domain.
++ *
++ * The state machines are reset to an IDLE state, the
++ * control bits in the CSRs are cleared, all the
++ * transmit FIFOs and the receive FIFO are flushed.
++ *
++ * The status mask bits that control the generation of
++ * the interrupt, are cleared, to clear the
++ * interrupt. The interrupt status bits are not
++ * cleared, so the application can get the status of
++ * any events that occurred in the core after it has
++ * set this bit.
++ *
++ * Any transactions on the AHB are terminated as soon
++ * as possible following the protocol. Any
++ * transactions on the USB are terminated immediately.
++ *
++ * The configuration settings in the CSRs are
++ * unchanged, so the software doesn't have to
++ * reprogram these registers (Device
++ * Configuration/Host Configuration/Core System
++ * Configuration/Core PHY Configuration).
++ *
++ * The application can write to this bit, any time it
++ * wants to reset the core. This is a self clearing
++ * bit and the core clears this bit after all the
++ * necessary logic is reset in the core, which may
++ * take several clocks, depending on the current state
++ * of the core.
++ */
++ unsigned csftrst:1;
++ /** Hclk Soft Reset
++ *
++ * The application uses this bit to reset the control logic in
++ * the AHB clock domain. Only AHB clock domain pipelines are
++ * reset.
++ */
++ unsigned hsftrst:1;
++ /** Host Frame Counter Reset (Host Only)<br>
++ *
++ * The application can reset the (micro)frame number
++ * counter inside the core, using this bit. When the
++ * (micro)frame counter is reset, the subsequent SOF
++ * sent out by the core, will have a (micro)frame
++ * number of 0.
++ */
++ unsigned hstfrm:1;
++ /** In Token Sequence Learning Queue Flush
++ * (INTknQFlsh) (Device Only)
++ */
++ unsigned intknqflsh:1;
++ /** RxFIFO Flush (RxFFlsh) (Device and Host)
++ *
++ * The application can flush the entire Receive FIFO
++ * using this bit. The application must first
++ * ensure that the core is not in the middle of a
++ * transaction. The application should write into
++ * this bit, only after making sure that neither the
++ * DMA engine is reading from the RxFIFO nor the MAC
++ * is writing the data in to the FIFO. The
++ * application should wait until the bit is cleared
++ * before performing any other operations. This bit
++ * will takes 8 clocks (slowest of PHY or AHB clock)
++ * to clear.
++ */
++ unsigned rxfflsh:1;
++ /** TxFIFO Flush (TxFFlsh) (Device and Host).
++ *
++ * This bit is used to selectively flush a single or
++ * all transmit FIFOs. The application must first
++ * ensure that the core is not in the middle of a
++ * transaction. The application should write into
++ * this bit, only after making sure that neither the
++ * DMA engine is writing into the TxFIFO nor the MAC
++ * is reading the data out of the FIFO. The
++ * application should wait until the core clears this
++ * bit, before performing any operations. This bit
++ * will takes 8 clocks (slowest of PHY or AHB clock)
++ * to clear.
++ */
++ unsigned txfflsh:1;
++
++ /** TxFIFO Number (TxFNum) (Device and Host).
++ *
++ * This is the FIFO number which needs to be flushed,
++ * using the TxFIFO Flush bit. This field should not
++ * be changed until the TxFIFO Flush bit is cleared by
++ * the core.
++ * - 0x0 : Non Periodic TxFIFO Flush
++ * - 0x1 : Periodic TxFIFO #1 Flush in device mode
++ * or Periodic TxFIFO in host mode
++ * - 0x2 : Periodic TxFIFO #2 Flush in device mode.
++ * - ...
++ * - 0xF : Periodic TxFIFO #15 Flush in device mode
++ * - 0x10: Flush all the Transmit NonPeriodic and
++ * Transmit Periodic FIFOs in the core
++ */
++ unsigned txfnum:5;
++ /** Reserved */
++ unsigned reserved11_29:19;
++ /** DMA Request Signal. Indicated DMA request is in
++ * probress. Used for debug purpose. */
++ unsigned dmareq:1;
++ /** AHB Master Idle. Indicates the AHB Master State
++ * Machine is in IDLE condition. */
++ unsigned ahbidle:1;
++ } b;
++} grstctl_t;
++
++/**
++ * This union represents the bit fields of the Core Interrupt Mask
++ * Register (GINTMSK). Set/clear the bits using the bit fields then
++ * write the <i>d32</i> value to the register.
++ */
++typedef union gintmsk_data {
++ /** raw register data */
++ uint32_t d32;
++ /** register bits */
++ struct {
++ unsigned reserved0:1;
++ unsigned modemismatch:1;
++ unsigned otgintr:1;
++ unsigned sofintr:1;
++ unsigned rxstsqlvl:1;
++ unsigned nptxfempty:1;
++ unsigned ginnakeff:1;
++ unsigned goutnakeff:1;
++ unsigned ulpickint:1;
++ unsigned i2cintr:1;
++ unsigned erlysuspend:1;
++ unsigned usbsuspend:1;
++ unsigned usbreset:1;
++ unsigned enumdone:1;
++ unsigned isooutdrop:1;
++ unsigned eopframe:1;
++ unsigned restoredone:1;
++ unsigned epmismatch:1;
++ unsigned inepintr:1;
++ unsigned outepintr:1;
++ unsigned incomplisoin:1;
++ unsigned incomplisoout:1;
++ unsigned fetsusp:1;
++ unsigned resetdet:1;
++ unsigned portintr:1;
++ unsigned hcintr:1;
++ unsigned ptxfempty:1;
++ unsigned lpmtranrcvd:1;
++ unsigned conidstschng:1;
++ unsigned disconnect:1;
++ unsigned sessreqintr:1;
++ unsigned wkupintr:1;
++ } b;
++} gintmsk_data_t;
++/**
++ * This union represents the bit fields of the Core Interrupt Register
++ * (GINTSTS). Set/clear the bits using the bit fields then write the
++ * <i>d32</i> value to the register.
++ */
++typedef union gintsts_data {
++ /** raw register data */
++ uint32_t d32;
++#define DWC_SOF_INTR_MASK 0x0008
++ /** register bits */
++ struct {
++#define DWC_HOST_MODE 1
++ unsigned curmode:1;
++ unsigned modemismatch:1;
++ unsigned otgintr:1;
++ unsigned sofintr:1;
++ unsigned rxstsqlvl:1;
++ unsigned nptxfempty:1;
++ unsigned ginnakeff:1;
++ unsigned goutnakeff:1;
++ unsigned ulpickint:1;
++ unsigned i2cintr:1;
++ unsigned erlysuspend:1;
++ unsigned usbsuspend:1;
++ unsigned usbreset:1;
++ unsigned enumdone:1;
++ unsigned isooutdrop:1;
++ unsigned eopframe:1;
++ unsigned restoredone:1;
++ unsigned epmismatch:1;
++ unsigned inepint:1;
++ unsigned outepintr:1;
++ unsigned incomplisoin:1;
++ unsigned incomplisoout:1;
++ unsigned fetsusp:1;
++ unsigned resetdet:1;
++ unsigned portintr:1;
++ unsigned hcintr:1;
++ unsigned ptxfempty:1;
++ unsigned lpmtranrcvd:1;
++ unsigned conidstschng:1;
++ unsigned disconnect:1;
++ unsigned sessreqintr:1;
++ unsigned wkupintr:1;
++ } b;
++} gintsts_data_t;
++
++/**
++ * This union represents the bit fields in the Device Receive Status Read and
++ * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the <i>d32</i>
++ * element then read out the bits using the <i>b</i>it elements.
++ */
++typedef union device_grxsts_data {
++ /** raw register data */
++ uint32_t d32;
++ /** register bits */
++ struct {
++ unsigned epnum:4;
++ unsigned bcnt:11;
++ unsigned dpid:2;
++
++#define DWC_STS_DATA_UPDT 0x2 // OUT Data Packet
++#define DWC_STS_XFER_COMP 0x3 // OUT Data Transfer Complete
++
++#define DWC_DSTS_GOUT_NAK 0x1 // Global OUT NAK
++#define DWC_DSTS_SETUP_COMP 0x4 // Setup Phase Complete
++#define DWC_DSTS_SETUP_UPDT 0x6 // SETUP Packet
++ unsigned pktsts:4;
++ unsigned fn:4;
++ unsigned reserved25_31:7;
++ } b;
++} device_grxsts_data_t;
++
++/**
++ * This union represents the bit fields in the Host Receive Status Read and
++ * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the <i>d32</i>
++ * element then read out the bits using the <i>b</i>it elements.
++ */
++typedef union host_grxsts_data {
++ /** raw register data */
++ uint32_t d32;
++ /** register bits */
++ struct {
++ unsigned chnum:4;
++ unsigned bcnt:11;
++ unsigned dpid:2;
++
++ unsigned pktsts:4;
++#define DWC_GRXSTS_PKTSTS_IN 0x2
++#define DWC_GRXSTS_PKTSTS_IN_XFER_COMP 0x3
++#define DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR 0x5
++#define DWC_GRXSTS_PKTSTS_CH_HALTED 0x7
++
++ unsigned reserved21_31:11;
++ } b;
++} host_grxsts_data_t;
++
++/**
++ * This union represents the bit fields in the FIFO Size Registers (HPTXFSIZ,
++ * GNPTXFSIZ, DPTXFSIZn, DIEPTXFn). Read the register into the <i>d32</i> element
++ * then read out the bits using the <i>b</i>it elements.
++ */
++typedef union fifosize_data {
++ /** raw register data */
++ uint32_t d32;
++ /** register bits */
++ struct {
++ unsigned startaddr:16;
++ unsigned depth:16;
++ } b;
++} fifosize_data_t;
++
++/**
++ * This union represents the bit fields in the Non-Periodic Transmit
++ * FIFO/Queue Status Register (GNPTXSTS). Read the register into the
++ * <i>d32</i> element then read out the bits using the <i>b</i>it
++ * elements.
++ */
++typedef union gnptxsts_data {
++ /** raw register data */
++ uint32_t d32;
++ /** register bits */
++ struct {
++ unsigned nptxfspcavail:16;
++ unsigned nptxqspcavail:8;
++ /** Top of the Non-Periodic Transmit Request Queue
++ * - bit 24 - Terminate (Last entry for the selected
++ * channel/EP)
++ * - bits 26:25 - Token Type
++ * - 2'b00 - IN/OUT
++ * - 2'b01 - Zero Length OUT
++ * - 2'b10 - PING/Complete Split
++ * - 2'b11 - Channel Halt
++ * - bits 30:27 - Channel/EP Number
++ */
++ unsigned nptxqtop_terminate:1;
++ unsigned nptxqtop_token:2;
++ unsigned nptxqtop_chnep:4;
++ unsigned reserved:1;
++ } b;
++} gnptxsts_data_t;
++
++/**
++ * This union represents the bit fields in the Transmit
++ * FIFO Status Register (DTXFSTS). Read the register into the
++ * <i>d32</i> element then read out the bits using the <i>b</i>it
++ * elements.
++ */
++typedef union dtxfsts_data {
++ /** raw register data */
++ uint32_t d32;
++ /** register bits */
++ struct {
++ unsigned txfspcavail:16;
++ unsigned reserved:16;
++ } b;
++} dtxfsts_data_t;
++
++/**
++ * This union represents the bit fields in the I2C Control Register
++ * (I2CCTL). Read the register into the <i>d32</i> element then read out the
++ * bits using the <i>b</i>it elements.
++ */
++typedef union gi2cctl_data {
++ /** raw register data */
++ uint32_t d32;
++ /** register bits */
++ struct {
++ unsigned rwdata:8;
++ unsigned regaddr:8;
++ unsigned addr:7;
++ unsigned i2cen:1;
++ unsigned ack:1;
++ unsigned i2csuspctl:1;
++ unsigned i2cdevaddr:2;
++ unsigned i2cdatse0:1;
++ unsigned reserved:1;
++ unsigned rw:1;
++ unsigned bsydne:1;
++ } b;
++} gi2cctl_data_t;
++
++/**
++ * This union represents the bit fields in the PHY Vendor Control Register
++ * (GPVNDCTL). Read the register into the <i>d32</i> element then read out the
++ * bits using the <i>b</i>it elements.
++ */
++typedef union gpvndctl_data {
++ /** raw register data */
++ uint32_t d32;
++ /** register bits */
++ struct {
++ unsigned regdata:8;
++ unsigned vctrl:8;
++ unsigned regaddr16_21:6;
++ unsigned regwr:1;
++ unsigned reserved23_24:2;
++ unsigned newregreq:1;
++ unsigned vstsbsy:1;
++ unsigned vstsdone:1;
++ unsigned reserved28_30:3;
++ unsigned disulpidrvr:1;
++ } b;
++} gpvndctl_data_t;
++
++/**
++ * This union represents the bit fields in the General Purpose
++ * Input/Output Register (GGPIO).
++ * Read the register into the <i>d32</i> element then read out the
++ * bits using the <i>b</i>it elements.
++ */
++typedef union ggpio_data {
++ /** raw register data */
++ uint32_t d32;
++ /** register bits */
++ struct {
++ unsigned gpi:16;
++ unsigned gpo:16;
++ } b;
++} ggpio_data_t;
++
++/**
++ * This union represents the bit fields in the User ID Register
++ * (GUID). Read the register into the <i>d32</i> element then read out the
++ * bits using the <i>b</i>it elements.
++ */
++typedef union guid_data {
++ /** raw register data */
++ uint32_t d32;
++ /** register bits */
++ struct {
++ unsigned rwdata:32;
++ } b;
++} guid_data_t;
++
++/**
++ * This union represents the bit fields in the Synopsys ID Register
++ * (GSNPSID). Read the register into the <i>d32</i> element then read out the
++ * bits using the <i>b</i>it elements.
++ */
++typedef union gsnpsid_data {
++ /** raw register data */
++ uint32_t d32;
++ /** register bits */
++ struct {
++ unsigned rwdata:32;
++ } b;
++} gsnpsid_data_t;
++
++/**
++ * This union represents the bit fields in the User HW Config1
++ * Register. Read the register into the <i>d32</i> element then read
++ * out the bits using the <i>b</i>it elements.
++ */
++typedef union hwcfg1_data {
++ /** raw register data */
++ uint32_t d32;
++ /** register bits */
++ struct {
++ unsigned ep_dir0:2;
++ unsigned ep_dir1:2;
++ unsigned ep_dir2:2;
++ unsigned ep_dir3:2;
++ unsigned ep_dir4:2;
++ unsigned ep_dir5:2;
++ unsigned ep_dir6:2;
++ unsigned ep_dir7:2;
++ unsigned ep_dir8:2;
++ unsigned ep_dir9:2;
++ unsigned ep_dir10:2;
++ unsigned ep_dir11:2;
++ unsigned ep_dir12:2;
++ unsigned ep_dir13:2;
++ unsigned ep_dir14:2;
++ unsigned ep_dir15:2;
++ } b;
++} hwcfg1_data_t;
++
++/**
++ * This union represents the bit fields in the User HW Config2
++ * Register. Read the register into the <i>d32</i> element then read
++ * out the bits using the <i>b</i>it elements.
++ */
++typedef union hwcfg2_data {
++ /** raw register data */
++ uint32_t d32;
++ /** register bits */
++ struct {
++ /* GHWCFG2 */
++ unsigned op_mode:3;
++#define DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG 0
++#define DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG 1
++#define DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG 2
++#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3
++#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE 4
++#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST 5
++#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6
++
++ unsigned architecture:2;
++ unsigned point2point:1;
++ unsigned hs_phy_type:2;
++#define DWC_HWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0
++#define DWC_HWCFG2_HS_PHY_TYPE_UTMI 1
++#define DWC_HWCFG2_HS_PHY_TYPE_ULPI 2
++#define DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI 3
++
++ unsigned fs_phy_type:2;
++ unsigned num_dev_ep:4;
++ unsigned num_host_chan:4;
++ unsigned perio_ep_supported:1;
++ unsigned dynamic_fifo:1;
++ unsigned multi_proc_int:1;
++ unsigned reserved21:1;
++ unsigned nonperio_tx_q_depth:2;
++ unsigned host_perio_tx_q_depth:2;
++ unsigned dev_token_q_depth:5;
++ unsigned otg_enable_ic_usb:1;
++ } b;
++} hwcfg2_data_t;
++
++/**
++ * This union represents the bit fields in the User HW Config3
++ * Register. Read the register into the <i>d32</i> element then read
++ * out the bits using the <i>b</i>it elements.
++ */
++typedef union hwcfg3_data {
++ /** raw register data */
++ uint32_t d32;
++ /** register bits */
++ struct {
++ /* GHWCFG3 */
++ unsigned xfer_size_cntr_width:4;
++ unsigned packet_size_cntr_width:3;
++ unsigned otg_func:1;
++ unsigned i2c:1;
++ unsigned vendor_ctrl_if:1;
++ unsigned optional_features:1;
++ unsigned synch_reset_type:1;
++ unsigned adp_supp:1;
++ unsigned otg_enable_hsic:1;
++ unsigned bc_support:1;
++ unsigned otg_lpm_en:1;
++ unsigned dfifo_depth:16;
++ } b;
++} hwcfg3_data_t;
++
++/**
++ * This union represents the bit fields in the User HW Config4
++ * Register. Read the register into the <i>d32</i> element then read
++ * out the bits using the <i>b</i>it elements.
++ */
++typedef union hwcfg4_data {
++ /** raw register data */
++ uint32_t d32;
++ /** register bits */
++ struct {
++ unsigned num_dev_perio_in_ep:4;
++ unsigned power_optimiz:1;
++ unsigned min_ahb_freq:1;
++ unsigned hiber:1;
++ unsigned xhiber:1;
++ unsigned reserved:6;
++ unsigned utmi_phy_data_width:2;
++ unsigned num_dev_mode_ctrl_ep:4;
++ unsigned iddig_filt_en:1;
++ unsigned vbus_valid_filt_en:1;
++ unsigned a_valid_filt_en:1;
++ unsigned b_valid_filt_en:1;
++ unsigned session_end_filt_en:1;
++ unsigned ded_fifo_en:1;
++ unsigned num_in_eps:4;
++ unsigned desc_dma:1;
++ unsigned desc_dma_dyn:1;
++ } b;
++} hwcfg4_data_t;
++
++/**
++ * This union represents the bit fields of the Core LPM Configuration
++ * Register (GLPMCFG). Set the bits using bit fields then write
++ * the <i>d32</i> value to the register.
++ */
++typedef union glpmctl_data {
++ /** raw register data */
++ uint32_t d32;
++ /** register bits */
++ struct {
++ /** LPM-Capable (LPMCap) (Device and Host)
++ * The application uses this bit to control
++ * the DWC_otg core LPM capabilities.
++ */
++ unsigned lpm_cap_en:1;
++ /** LPM response programmed by application (AppL1Res) (Device)
++ * Handshake response to LPM token pre-programmed
++ * by device application software.
++ */
++ unsigned appl_resp:1;
++ /** Host Initiated Resume Duration (HIRD) (Device and Host)
++ * In Host mode this field indicates the value of HIRD
++ * to be sent in an LPM transaction.
++ * In Device mode this field is updated with the
++ * Received LPM Token HIRD bmAttribute
++ * when an ACK/NYET/STALL response is sent
++ * to an LPM transaction.
++ */
++ unsigned hird:4;
++ /** RemoteWakeEnable (bRemoteWake) (Device and Host)
++ * In Host mode this bit indicates the value of remote
++ * wake up to be sent in wIndex field of LPM transaction.
++ * In Device mode this field is updated with the
++ * Received LPM Token bRemoteWake bmAttribute
++ * when an ACK/NYET/STALL response is sent
++ * to an LPM transaction.
++ */
++ unsigned rem_wkup_en:1;
++ /** Enable utmi_sleep_n (EnblSlpM) (Device and Host)
++ * The application uses this bit to control
++ * the utmi_sleep_n assertion to the PHY when in L1 state.
++ */
++ unsigned en_utmi_sleep:1;
++ /** HIRD Threshold (HIRD_Thres) (Device and Host)
++ */
++ unsigned hird_thres:5;
++ /** LPM Response (CoreL1Res) (Device and Host)
++ * In Host mode this bit contains handsake response to
++ * LPM transaction.
++ * In Device mode the response of the core to
++ * LPM transaction received is reflected in these two bits.
++ - 0x0 : ERROR (No handshake response)
++ - 0x1 : STALL
++ - 0x2 : NYET
++ - 0x3 : ACK
++ */
++ unsigned lpm_resp:2;
++ /** Port Sleep Status (SlpSts) (Device and Host)
++ * This bit is set as long as a Sleep condition
++ * is present on the USB bus.
++ */
++ unsigned prt_sleep_sts:1;
++ /** Sleep State Resume OK (L1ResumeOK) (Device and Host)
++ * Indicates that the application or host
++ * can start resume from Sleep state.
++ */
++ unsigned sleep_state_resumeok:1;
++ /** LPM channel Index (LPM_Chnl_Indx) (Host)
++ * The channel number on which the LPM transaction
++ * has to be applied while sending
++ * an LPM transaction to the local device.
++ */
++ unsigned lpm_chan_index:4;
++ /** LPM Retry Count (LPM_Retry_Cnt) (Host)
++ * Number host retries that would be performed
++ * if the device response was not valid response.
++ */
++ unsigned retry_count:3;
++ /** Send LPM Transaction (SndLPM) (Host)
++ * When set by application software,
++ * an LPM transaction containing two tokens
++ * is sent.
++ */
++ unsigned send_lpm:1;
++ /** LPM Retry status (LPM_RetryCnt_Sts) (Host)
++ * Number of LPM Host Retries still remaining
++ * to be transmitted for the current LPM sequence
++ */
++ unsigned retry_count_sts:3;
++ unsigned reserved28_29:2;
++ /** In host mode once this bit is set, the host
++ * configures to drive the HSIC Idle state on the bus.
++ * It then waits for the device to initiate the Connect sequence.
++ * In device mode once this bit is set, the device waits for
++ * the HSIC Idle line state on the bus. Upon receving the Idle
++ * line state, it initiates the HSIC Connect sequence.
++ */
++ unsigned hsic_connect:1;
++ /** This bit overrides and functionally inverts
++ * the if_select_hsic input port signal.
++ */
++ unsigned inv_sel_hsic:1;
++ } b;
++} glpmcfg_data_t;
++
++/**
++ * This union represents the bit fields of the Core ADP Timer, Control and
++ * Status Register (ADPTIMCTLSTS). Set the bits using bit fields then write
++ * the <i>d32</i> value to the register.
++ */
++typedef union adpctl_data {
++ /** raw register data */
++ uint32_t d32;
++ /** register bits */
++ struct {
++ /** Probe Discharge (PRB_DSCHG)
++ * These bits set the times for TADP_DSCHG.
++ * These bits are defined as follows:
++ * 2'b00 - 4 msec
++ * 2'b01 - 8 msec
++ * 2'b10 - 16 msec
++ * 2'b11 - 32 msec
++ */
++ unsigned prb_dschg:2;
++ /** Probe Delta (PRB_DELTA)
++ * These bits set the resolution for RTIM value.
++ * The bits are defined in units of 32 kHz clock cycles as follows:
++ * 2'b00 - 1 cycles
++ * 2'b01 - 2 cycles
++ * 2'b10 - 3 cycles
++ * 2'b11 - 4 cycles
++ * For example if this value is chosen to 2'b01, it means that RTIM
++ * increments for every 3(three) 32Khz clock cycles.
++ */
++ unsigned prb_delta:2;
++ /** Probe Period (PRB_PER)
++ * These bits sets the TADP_PRD as shown in Figure 4 as follows:
++ * 2'b00 - 0.625 to 0.925 sec (typical 0.775 sec)
++ * 2'b01 - 1.25 to 1.85 sec (typical 1.55 sec)
++ * 2'b10 - 1.9 to 2.6 sec (typical 2.275 sec)
++ * 2'b11 - Reserved
++ */
++ unsigned prb_per:2;
++ /** These bits capture the latest time it took for VBUS to ramp from
++ * VADP_SINK to VADP_PRB.
++ * 0x000 - 1 cycles
++ * 0x001 - 2 cycles
++ * 0x002 - 3 cycles
++ * etc
++ * 0x7FF - 2048 cycles
++ * A time of 1024 cycles at 32 kHz corresponds to a time of 32 msec.
++ */
++ unsigned rtim:11;
++ /** Enable Probe (EnaPrb)
++ * When programmed to 1'b1, the core performs a probe operation.
++ * This bit is valid only if OTG_Ver = 1'b1.
++ */
++ unsigned enaprb:1;
++ /** Enable Sense (EnaSns)
++ * When programmed to 1'b1, the core performs a Sense operation.
++ * This bit is valid only if OTG_Ver = 1'b1.
++ */
++ unsigned enasns:1;
++ /** ADP Reset (ADPRes)
++ * When set, ADP controller is reset.
++ * This bit is valid only if OTG_Ver = 1'b1.
++ */
++ unsigned adpres:1;
++ /** ADP Enable (ADPEn)
++ * When set, the core performs either ADP probing or sensing
++ * based on EnaPrb or EnaSns.
++ * This bit is valid only if OTG_Ver = 1'b1.
++ */
++ unsigned adpen:1;
++ /** ADP Probe Interrupt (ADP_PRB_INT)
++ * When this bit is set, it means that the VBUS
++ * voltage is greater than VADP_PRB or VADP_PRB is reached.
++ * This bit is valid only if OTG_Ver = 1'b1.
++ */
++ unsigned adp_prb_int:1;
++ /**
++ * ADP Sense Interrupt (ADP_SNS_INT)
++ * When this bit is set, it means that the VBUS voltage is greater than
++ * VADP_SNS value or VADP_SNS is reached.
++ * This bit is valid only if OTG_Ver = 1'b1.
++ */
++ unsigned adp_sns_int:1;
++ /** ADP Tomeout Interrupt (ADP_TMOUT_INT)
++ * This bit is relevant only for an ADP probe.
++ * When this bit is set, it means that the ramp time has
++ * completed ie ADPCTL.RTIM has reached its terminal value
++ * of 0x7FF. This is a debug feature that allows software
++ * to read the ramp time after each cycle.
++ * This bit is valid only if OTG_Ver = 1'b1.
++ */
++ unsigned adp_tmout_int:1;
++ /** ADP Probe Interrupt Mask (ADP_PRB_INT_MSK)
++ * When this bit is set, it unmasks the interrupt due to ADP_PRB_INT.
++ * This bit is valid only if OTG_Ver = 1'b1.
++ */
++ unsigned adp_prb_int_msk:1;
++ /** ADP Sense Interrupt Mask (ADP_SNS_INT_MSK)
++ * When this bit is set, it unmasks the interrupt due to ADP_SNS_INT.
++ * This bit is valid only if OTG_Ver = 1'b1.
++ */
++ unsigned adp_sns_int_msk:1;
++ /** ADP Timoeout Interrupt Mask (ADP_TMOUT_MSK)
++ * When this bit is set, it unmasks the interrupt due to ADP_TMOUT_INT.
++ * This bit is valid only if OTG_Ver = 1'b1.
++ */
++ unsigned adp_tmout_int_msk:1;
++ /** Access Request
++ * 2'b00 - Read/Write Valid (updated by the core)
++ * 2'b01 - Read
++ * 2'b00 - Write
++ * 2'b00 - Reserved
++ */
++ unsigned ar:2;
++ /** Reserved */
++ unsigned reserved29_31:3;
++ } b;
++} adpctl_data_t;
++
++////////////////////////////////////////////
++// Device Registers
++/**
++ * Device Global Registers. <i>Offsets 800h-BFFh</i>
++ *
++ * The following structures define the size and relative field offsets
++ * for the Device Mode Registers.
++ *
++ * <i>These registers are visible only in Device mode and must not be
++ * accessed in Host mode, as the results are unknown.</i>
++ */
++typedef struct dwc_otg_dev_global_regs {
++ /** Device Configuration Register. <i>Offset 800h</i> */
++ volatile uint32_t dcfg;
++ /** Device Control Register. <i>Offset: 804h</i> */
++ volatile uint32_t dctl;
++ /** Device Status Register (Read Only). <i>Offset: 808h</i> */
++ volatile uint32_t dsts;
++ /** Reserved. <i>Offset: 80Ch</i> */
++ uint32_t unused;
++ /** Device IN Endpoint Common Interrupt Mask
++ * Register. <i>Offset: 810h</i> */
++ volatile uint32_t diepmsk;
++ /** Device OUT Endpoint Common Interrupt Mask
++ * Register. <i>Offset: 814h</i> */
++ volatile uint32_t doepmsk;
++ /** Device All Endpoints Interrupt Register. <i>Offset: 818h</i> */
++ volatile uint32_t daint;
++ /** Device All Endpoints Interrupt Mask Register. <i>Offset:
++ * 81Ch</i> */
++ volatile uint32_t daintmsk;
++ /** Device IN Token Queue Read Register-1 (Read Only).
++ * <i>Offset: 820h</i> */
++ volatile uint32_t dtknqr1;
++ /** Device IN Token Queue Read Register-2 (Read Only).
++ * <i>Offset: 824h</i> */
++ volatile uint32_t dtknqr2;
++ /** Device VBUS discharge Register. <i>Offset: 828h</i> */
++ volatile uint32_t dvbusdis;
++ /** Device VBUS Pulse Register. <i>Offset: 82Ch</i> */
++ volatile uint32_t dvbuspulse;
++ /** Device IN Token Queue Read Register-3 (Read Only). /
++ * Device Thresholding control register (Read/Write)
++ * <i>Offset: 830h</i> */
++ volatile uint32_t dtknqr3_dthrctl;
++ /** Device IN Token Queue Read Register-4 (Read Only). /
++ * Device IN EPs empty Inr. Mask Register (Read/Write)
++ * <i>Offset: 834h</i> */
++ volatile uint32_t dtknqr4_fifoemptymsk;
++ /** Device Each Endpoint Interrupt Register (Read Only). /
++ * <i>Offset: 838h</i> */
++ volatile uint32_t deachint;
++ /** Device Each Endpoint Interrupt mask Register (Read/Write). /
++ * <i>Offset: 83Ch</i> */
++ volatile uint32_t deachintmsk;
++ /** Device Each In Endpoint Interrupt mask Register (Read/Write). /
++ * <i>Offset: 840h</i> */
++ volatile uint32_t diepeachintmsk[MAX_EPS_CHANNELS];
++ /** Device Each Out Endpoint Interrupt mask Register (Read/Write). /
++ * <i>Offset: 880h</i> */
++ volatile uint32_t doepeachintmsk[MAX_EPS_CHANNELS];
++} dwc_otg_device_global_regs_t;
++
++/**
++ * This union represents the bit fields in the Device Configuration
++ * Register. Read the register into the <i>d32</i> member then
++ * set/clear the bits using the <i>b</i>it elements. Write the
++ * <i>d32</i> member to the dcfg register.
++ */
++typedef union dcfg_data {
++ /** raw register data */
++ uint32_t d32;
++ /** register bits */
++ struct {
++ /** Device Speed */
++ unsigned devspd:2;
++ /** Non Zero Length Status OUT Handshake */
++ unsigned nzstsouthshk:1;
++#define DWC_DCFG_SEND_STALL 1
++
++ unsigned ena32khzs:1;
++ /** Device Addresses */
++ unsigned devaddr:7;
++ /** Periodic Frame Interval */
++ unsigned perfrint:2;
++#define DWC_DCFG_FRAME_INTERVAL_80 0
++#define DWC_DCFG_FRAME_INTERVAL_85 1
++#define DWC_DCFG_FRAME_INTERVAL_90 2
++#define DWC_DCFG_FRAME_INTERVAL_95 3
++
++ /** Enable Device OUT NAK for bulk in DDMA mode */
++ unsigned endevoutnak:1;
++
++ unsigned reserved14_17:4;
++ /** In Endpoint Mis-match count */
++ unsigned epmscnt:5;
++ /** Enable Descriptor DMA in Device mode */
++ unsigned descdma:1;
++ unsigned perschintvl:2;
++ unsigned resvalid:6;
++ } b;
++} dcfg_data_t;
++
++/**
++ * This union represents the bit fields in the Device Control
++ * Register. Read the register into the <i>d32</i> member then
++ * set/clear the bits using the <i>b</i>it elements.
++ */
++typedef union dctl_data {
++ /** raw register data */
++ uint32_t d32;
++ /** register bits */
++ struct {
++ /** Remote Wakeup */
++ unsigned rmtwkupsig:1;
++ /** Soft Disconnect */
++ unsigned sftdiscon:1;
++ /** Global Non-Periodic IN NAK Status */
++ unsigned gnpinnaksts:1;
++ /** Global OUT NAK Status */
++ unsigned goutnaksts:1;
++ /** Test Control */
++ unsigned tstctl:3;
++ /** Set Global Non-Periodic IN NAK */
++ unsigned sgnpinnak:1;
++ /** Clear Global Non-Periodic IN NAK */
++ unsigned cgnpinnak:1;
++ /** Set Global OUT NAK */
++ unsigned sgoutnak:1;
++ /** Clear Global OUT NAK */
++ unsigned cgoutnak:1;
++ /** Power-On Programming Done */
++ unsigned pwronprgdone:1;
++ /** Reserved */
++ unsigned reserved:1;
++ /** Global Multi Count */
++ unsigned gmc:2;
++ /** Ignore Frame Number for ISOC EPs */
++ unsigned ifrmnum:1;
++ /** NAK on Babble */
++ unsigned nakonbble:1;
++ /** Enable Continue on BNA */
++ unsigned encontonbna:1;
++
++ unsigned reserved18_31:14;
++ } b;
++} dctl_data_t;
++
++/**
++ * This union represents the bit fields in the Device Status
++ * Register. Read the register into the <i>d32</i> member then
++ * set/clear the bits using the <i>b</i>it elements.
++ */
++typedef union dsts_data {
++ /** raw register data */
++ uint32_t d32;
++ /** register bits */
++ struct {
++ /** Suspend Status */
++ unsigned suspsts:1;
++ /** Enumerated Speed */
++ unsigned enumspd:2;
++#define DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0
++#define DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1
++#define DWC_DSTS_ENUMSPD_LS_PHY_6MHZ 2
++#define DWC_DSTS_ENUMSPD_FS_PHY_48MHZ 3
++ /** Erratic Error */
++ unsigned errticerr:1;
++ unsigned reserved4_7:4;
++ /** Frame or Microframe Number of the received SOF */
++ unsigned soffn:14;
++ unsigned reserved22_31:10;
++ } b;
++} dsts_data_t;
++
++/**
++ * This union represents the bit fields in the Device IN EP Interrupt
++ * Register and the Device IN EP Common Mask Register.
++ *
++ * - Read the register into the <i>d32</i> member then set/clear the
++ * bits using the <i>b</i>it elements.
++ */
++typedef union diepint_data {
++ /** raw register data */
++ uint32_t d32;
++ /** register bits */
++ struct {
++ /** Transfer complete mask */
++ unsigned xfercompl:1;
++ /** Endpoint disable mask */
++ unsigned epdisabled:1;
++ /** AHB Error mask */
++ unsigned ahberr:1;
++ /** TimeOUT Handshake mask (non-ISOC EPs) */
++ unsigned timeout:1;
++ /** IN Token received with TxF Empty mask */
++ unsigned intktxfemp:1;
++ /** IN Token Received with EP mismatch mask */
++ unsigned intknepmis:1;
++ /** IN Endpoint NAK Effective mask */
++ unsigned inepnakeff:1;
++ /** Reserved */
++ unsigned emptyintr:1;
++
++ unsigned txfifoundrn:1;
++
++ /** BNA Interrupt mask */
++ unsigned bna:1;
++
++ unsigned reserved10_12:3;
++ /** BNA Interrupt mask */
++ unsigned nak:1;
++
++ unsigned reserved14_31:18;
++ } b;
++} diepint_data_t;
++
++/**
++ * This union represents the bit fields in the Device IN EP
++ * Common/Dedicated Interrupt Mask Register.
++ */
++typedef union diepint_data diepmsk_data_t;
++
++/**
++ * This union represents the bit fields in the Device OUT EP Interrupt
++ * Registerand Device OUT EP Common Interrupt Mask Register.
++ *
++ * - Read the register into the <i>d32</i> member then set/clear the
++ * bits using the <i>b</i>it elements.
++ */
++typedef union doepint_data {
++ /** raw register data */
++ uint32_t d32;
++ /** register bits */
++ struct {
++ /** Transfer complete */
++ unsigned xfercompl:1;
++ /** Endpoint disable */
++ unsigned epdisabled:1;
++ /** AHB Error */
++ unsigned ahberr:1;
++ /** Setup Phase Done (contorl EPs) */
++ unsigned setup:1;
++ /** OUT Token Received when Endpoint Disabled */
++ unsigned outtknepdis:1;
++
++ unsigned stsphsercvd:1;
++ /** Back-to-Back SETUP Packets Received */
++ unsigned back2backsetup:1;
++
++ unsigned reserved7:1;
++ /** OUT packet Error */
++ unsigned outpkterr:1;
++ /** BNA Interrupt */
++ unsigned bna:1;
++
++ unsigned reserved10:1;
++ /** Packet Drop Status */
++ unsigned pktdrpsts:1;
++ /** Babble Interrupt */
++ unsigned babble:1;
++ /** NAK Interrupt */
++ unsigned nak:1;
++ /** NYET Interrupt */
++ unsigned nyet:1;
++ /** Bit indicating setup packet received */
++ unsigned sr:1;
++
++ unsigned reserved16_31:16;
++ } b;
++} doepint_data_t;
++
++/**
++ * This union represents the bit fields in the Device OUT EP
++ * Common/Dedicated Interrupt Mask Register.
++ */
++typedef union doepint_data doepmsk_data_t;
++
++/**
++ * This union represents the bit fields in the Device All EP Interrupt
++ * and Mask Registers.
++ * - Read the register into the <i>d32</i> member then set/clear the
++ * bits using the <i>b</i>it elements.
++ */
++typedef union daint_data {
++ /** raw register data */
++ uint32_t d32;
++ /** register bits */
++ struct {
++ /** IN Endpoint bits */
++ unsigned in:16;
++ /** OUT Endpoint bits */
++ unsigned out:16;
++ } ep;
++ struct {
++ /** IN Endpoint bits */
++ unsigned inep0:1;
++ unsigned inep1:1;
++ unsigned inep2:1;
++ unsigned inep3:1;
++ unsigned inep4:1;
++ unsigned inep5:1;
++ unsigned inep6:1;
++ unsigned inep7:1;
++ unsigned inep8:1;
++ unsigned inep9:1;
++ unsigned inep10:1;
++ unsigned inep11:1;
++ unsigned inep12:1;
++ unsigned inep13:1;
++ unsigned inep14:1;
++ unsigned inep15:1;
++ /** OUT Endpoint bits */
++ unsigned outep0:1;
++ unsigned outep1:1;
++ unsigned outep2:1;
++ unsigned outep3:1;
++ unsigned outep4:1;
++ unsigned outep5:1;
++ unsigned outep6:1;
++ unsigned outep7:1;
++ unsigned outep8:1;
++ unsigned outep9:1;
++ unsigned outep10:1;
++ unsigned outep11:1;
++ unsigned outep12:1;
++ unsigned outep13:1;
++ unsigned outep14:1;
++ unsigned outep15:1;
++ } b;
++} daint_data_t;
++
++/**
++ * This union represents the bit fields in the Device IN Token Queue
++ * Read Registers.
++ * - Read the register into the <i>d32</i> member.
++ * - READ-ONLY Register
++ */
++typedef union dtknq1_data {
++ /** raw register data */
++ uint32_t d32;
++ /** register bits */
++ struct {
++ /** In Token Queue Write Pointer */
++ unsigned intknwptr:5;
++ /** Reserved */
++ unsigned reserved05_06:2;
++ /** write pointer has wrapped. */
++ unsigned wrap_bit:1;
++ /** EP Numbers of IN Tokens 0 ... 4 */
++ unsigned epnums0_5:24;
++ } b;
++} dtknq1_data_t;
++
++/**
++ * This union represents Threshold control Register
++ * - Read and write the register into the <i>d32</i> member.
++ * - READ-WRITABLE Register
++ */
++typedef union dthrctl_data {
++ /** raw register data */
++ uint32_t d32;
++ /** register bits */
++ struct {
++ /** non ISO Tx Thr. Enable */
++ unsigned non_iso_thr_en:1;
++ /** ISO Tx Thr. Enable */
++ unsigned iso_thr_en:1;
++ /** Tx Thr. Length */
++ unsigned tx_thr_len:9;
++ /** AHB Threshold ratio */
++ unsigned ahb_thr_ratio:2;
++ /** Reserved */
++ unsigned reserved13_15:3;
++ /** Rx Thr. Enable */
++ unsigned rx_thr_en:1;
++ /** Rx Thr. Length */
++ unsigned rx_thr_len:9;
++ unsigned reserved26:1;
++ /** Arbiter Parking Enable*/
++ unsigned arbprken:1;
++ /** Reserved */
++ unsigned reserved28_31:4;
++ } b;
++} dthrctl_data_t;
++
++/**
++ * Device Logical IN Endpoint-Specific Registers. <i>Offsets
++ * 900h-AFCh</i>
++ *
++ * There will be one set of endpoint registers per logical endpoint
++ * implemented.
++ *
++ * <i>These registers are visible only in Device mode and must not be
++ * accessed in Host mode, as the results are unknown.</i>
++ */
++typedef struct dwc_otg_dev_in_ep_regs {
++ /** Device IN Endpoint Control Register. <i>Offset:900h +
++ * (ep_num * 20h) + 00h</i> */
++ volatile uint32_t diepctl;
++ /** Reserved. <i>Offset:900h + (ep_num * 20h) + 04h</i> */
++ uint32_t reserved04;
++ /** Device IN Endpoint Interrupt Register. <i>Offset:900h +
++ * (ep_num * 20h) + 08h</i> */
++ volatile uint32_t diepint;
++ /** Reserved. <i>Offset:900h + (ep_num * 20h) + 0Ch</i> */
++ uint32_t reserved0C;
++ /** Device IN Endpoint Transfer Size
++ * Register. <i>Offset:900h + (ep_num * 20h) + 10h</i> */
++ volatile uint32_t dieptsiz;
++ /** Device IN Endpoint DMA Address Register. <i>Offset:900h +
++ * (ep_num * 20h) + 14h</i> */
++ volatile uint32_t diepdma;
++ /** Device IN Endpoint Transmit FIFO Status Register. <i>Offset:900h +
++ * (ep_num * 20h) + 18h</i> */
++ volatile uint32_t dtxfsts;
++ /** Device IN Endpoint DMA Buffer Register. <i>Offset:900h +
++ * (ep_num * 20h) + 1Ch</i> */
++ volatile uint32_t diepdmab;
++} dwc_otg_dev_in_ep_regs_t;
++
++/**
++ * Device Logical OUT Endpoint-Specific Registers. <i>Offsets:
++ * B00h-CFCh</i>
++ *
++ * There will be one set of endpoint registers per logical endpoint
++ * implemented.
++ *
++ * <i>These registers are visible only in Device mode and must not be
++ * accessed in Host mode, as the results are unknown.</i>
++ */
++typedef struct dwc_otg_dev_out_ep_regs {
++ /** Device OUT Endpoint Control Register. <i>Offset:B00h +
++ * (ep_num * 20h) + 00h</i> */
++ volatile uint32_t doepctl;
++ /** Reserved. <i>Offset:B00h + (ep_num * 20h) + 04h</i> */
++ uint32_t reserved04;
++ /** Device OUT Endpoint Interrupt Register. <i>Offset:B00h +
++ * (ep_num * 20h) + 08h</i> */
++ volatile uint32_t doepint;
++ /** Reserved. <i>Offset:B00h + (ep_num * 20h) + 0Ch</i> */
++ uint32_t reserved0C;
++ /** Device OUT Endpoint Transfer Size Register. <i>Offset:
++ * B00h + (ep_num * 20h) + 10h</i> */
++ volatile uint32_t doeptsiz;
++ /** Device OUT Endpoint DMA Address Register. <i>Offset:B00h
++ * + (ep_num * 20h) + 14h</i> */
++ volatile uint32_t doepdma;
++ /** Reserved. <i>Offset:B00h + * (ep_num * 20h) + 18h</i> */
++ uint32_t unused;
++ /** Device OUT Endpoint DMA Buffer Register. <i>Offset:B00h
++ * + (ep_num * 20h) + 1Ch</i> */
++ uint32_t doepdmab;
++} dwc_otg_dev_out_ep_regs_t;
++
++/**
++ * This union represents the bit fields in the Device EP Control
++ * Register. Read the register into the <i>d32</i> member then
++ * set/clear the bits using the <i>b</i>it elements.
++ */
++typedef union depctl_data {
++ /** raw register data */
++ uint32_t d32;
++ /** register bits */
++ struct {
++ /** Maximum Packet Size
++ * IN/OUT EPn
++ * IN/OUT EP0 - 2 bits
++ * 2'b00: 64 Bytes
++ * 2'b01: 32
++ * 2'b10: 16
++ * 2'b11: 8 */
++ unsigned mps:11;
++#define DWC_DEP0CTL_MPS_64 0
++#define DWC_DEP0CTL_MPS_32 1
++#define DWC_DEP0CTL_MPS_16 2
++#define DWC_DEP0CTL_MPS_8 3
++
++ /** Next Endpoint
++ * IN EPn/IN EP0
++ * OUT EPn/OUT EP0 - reserved */
++ unsigned nextep:4;
++
++ /** USB Active Endpoint */
++ unsigned usbactep:1;
++
++ /** Endpoint DPID (INTR/Bulk IN and OUT endpoints)
++ * This field contains the PID of the packet going to
++ * be received or transmitted on this endpoint. The
++ * application should program the PID of the first
++ * packet going to be received or transmitted on this
++ * endpoint , after the endpoint is
++ * activated. Application use the SetD1PID and
++ * SetD0PID fields of this register to program either
++ * D0 or D1 PID.
++ *
++ * The encoding for this field is
++ * - 0: D0
++ * - 1: D1
++ */
++ unsigned dpid:1;
++
++ /** NAK Status */
++ unsigned naksts:1;
++
++ /** Endpoint Type
++ * 2'b00: Control
++ * 2'b01: Isochronous
++ * 2'b10: Bulk
++ * 2'b11: Interrupt */
++ unsigned eptype:2;
++
++ /** Snoop Mode
++ * OUT EPn/OUT EP0
++ * IN EPn/IN EP0 - reserved */
++ unsigned snp:1;
++
++ /** Stall Handshake */
++ unsigned stall:1;
++
++ /** Tx Fifo Number
++ * IN EPn/IN EP0
++ * OUT EPn/OUT EP0 - reserved */
++ unsigned txfnum:4;
++
++ /** Clear NAK */
++ unsigned cnak:1;
++ /** Set NAK */
++ unsigned snak:1;
++ /** Set DATA0 PID (INTR/Bulk IN and OUT endpoints)
++ * Writing to this field sets the Endpoint DPID (DPID)
++ * field in this register to DATA0. Set Even
++ * (micro)frame (SetEvenFr) (ISO IN and OUT Endpoints)
++ * Writing to this field sets the Even/Odd
++ * (micro)frame (EO_FrNum) field to even (micro)
++ * frame.
++ */
++ unsigned setd0pid:1;
++ /** Set DATA1 PID (INTR/Bulk IN and OUT endpoints)
++ * Writing to this field sets the Endpoint DPID (DPID)
++ * field in this register to DATA1 Set Odd
++ * (micro)frame (SetOddFr) (ISO IN and OUT Endpoints)
++ * Writing to this field sets the Even/Odd
++ * (micro)frame (EO_FrNum) field to odd (micro) frame.
++ */
++ unsigned setd1pid:1;
++
++ /** Endpoint Disable */
++ unsigned epdis:1;
++ /** Endpoint Enable */
++ unsigned epena:1;
++ } b;
++} depctl_data_t;
++
++/**
++ * This union represents the bit fields in the Device EP Transfer
++ * Size Register. Read the register into the <i>d32</i> member then
++ * set/clear the bits using the <i>b</i>it elements.
++ */
++typedef union deptsiz_data {
++ /** raw register data */
++ uint32_t d32;
++ /** register bits */
++ struct {
++ /** Transfer size */
++ unsigned xfersize:19;
++/** Max packet count for EP (pow(2,10)-1) */
++#define MAX_PKT_CNT 1023
++ /** Packet Count */
++ unsigned pktcnt:10;
++ /** Multi Count - Periodic IN endpoints */
++ unsigned mc:2;
++ unsigned reserved:1;
++ } b;
++} deptsiz_data_t;
++
++/**
++ * This union represents the bit fields in the Device EP 0 Transfer
++ * Size Register. Read the register into the <i>d32</i> member then
++ * set/clear the bits using the <i>b</i>it elements.
++ */
++typedef union deptsiz0_data {
++ /** raw register data */
++ uint32_t d32;
++ /** register bits */
++ struct {
++ /** Transfer size */
++ unsigned xfersize:7;
++ /** Reserved */
++ unsigned reserved7_18:12;
++ /** Packet Count */
++ unsigned pktcnt:2;
++ /** Reserved */
++ unsigned reserved21_28:8;
++ /**Setup Packet Count (DOEPTSIZ0 Only) */
++ unsigned supcnt:2;
++ unsigned reserved31;
++ } b;
++} deptsiz0_data_t;
++
++/////////////////////////////////////////////////
++// DMA Descriptor Specific Structures
++//
++
++/** Buffer status definitions */
++
++#define BS_HOST_READY 0x0
++#define BS_DMA_BUSY 0x1
++#define BS_DMA_DONE 0x2
++#define BS_HOST_BUSY 0x3
++
++/** Receive/Transmit status definitions */
++
++#define RTS_SUCCESS 0x0
++#define RTS_BUFFLUSH 0x1
++#define RTS_RESERVED 0x2
++#define RTS_BUFERR 0x3
++
++/**
++ * This union represents the bit fields in the DMA Descriptor
++ * status quadlet. Read the quadlet into the <i>d32</i> member then
++ * set/clear the bits using the <i>b</i>it, <i>b_iso_out</i> and
++ * <i>b_iso_in</i> elements.
++ */
++typedef union dev_dma_desc_sts {
++ /** raw register data */
++ uint32_t d32;
++ /** quadlet bits */
++ struct {
++ /** Received number of bytes */
++ unsigned bytes:16;
++ /** NAK bit - only for OUT EPs */
++ unsigned nak:1;
++ unsigned reserved17_22:6;
++ /** Multiple Transfer - only for OUT EPs */
++ unsigned mtrf:1;
++ /** Setup Packet received - only for OUT EPs */
++ unsigned sr:1;
++ /** Interrupt On Complete */
++ unsigned ioc:1;
++ /** Short Packet */
++ unsigned sp:1;
++ /** Last */
++ unsigned l:1;
++ /** Receive Status */
++ unsigned sts:2;
++ /** Buffer Status */
++ unsigned bs:2;
++ } b;
++
++//#ifdef DWC_EN_ISOC
++ /** iso out quadlet bits */
++ struct {
++ /** Received number of bytes */
++ unsigned rxbytes:11;
++
++ unsigned reserved11:1;
++ /** Frame Number */
++ unsigned framenum:11;
++ /** Received ISO Data PID */
++ unsigned pid:2;
++ /** Interrupt On Complete */
++ unsigned ioc:1;
++ /** Short Packet */
++ unsigned sp:1;
++ /** Last */
++ unsigned l:1;
++ /** Receive Status */
++ unsigned rxsts:2;
++ /** Buffer Status */
++ unsigned bs:2;
++ } b_iso_out;
++
++ /** iso in quadlet bits */
++ struct {
++ /** Transmited number of bytes */
++ unsigned txbytes:12;
++ /** Frame Number */
++ unsigned framenum:11;
++ /** Transmited ISO Data PID */
++ unsigned pid:2;
++ /** Interrupt On Complete */
++ unsigned ioc:1;
++ /** Short Packet */
++ unsigned sp:1;
++ /** Last */
++ unsigned l:1;
++ /** Transmit Status */
++ unsigned txsts:2;
++ /** Buffer Status */
++ unsigned bs:2;
++ } b_iso_in;
++//#endif /* DWC_EN_ISOC */
++} dev_dma_desc_sts_t;
++
++/**
++ * DMA Descriptor structure
++ *
++ * DMA Descriptor structure contains two quadlets:
++ * Status quadlet and Data buffer pointer.
++ */
++typedef struct dwc_otg_dev_dma_desc {
++ /** DMA Descriptor status quadlet */
++ dev_dma_desc_sts_t status;
++ /** DMA Descriptor data buffer pointer */
++ uint32_t buf;
++} dwc_otg_dev_dma_desc_t;
++
++/**
++ * The dwc_otg_dev_if structure contains information needed to manage
++ * the DWC_otg controller acting in device mode. It represents the
++ * programming view of the device-specific aspects of the controller.
++ */
++typedef struct dwc_otg_dev_if {
++ /** Pointer to device Global registers.
++ * Device Global Registers starting at offset 800h
++ */
++ dwc_otg_device_global_regs_t *dev_global_regs;
++#define DWC_DEV_GLOBAL_REG_OFFSET 0x800
++
++ /**
++ * Device Logical IN Endpoint-Specific Registers 900h-AFCh
++ */
++ dwc_otg_dev_in_ep_regs_t *in_ep_regs[MAX_EPS_CHANNELS];
++#define DWC_DEV_IN_EP_REG_OFFSET 0x900
++#define DWC_EP_REG_OFFSET 0x20
++
++ /** Device Logical OUT Endpoint-Specific Registers B00h-CFCh */
++ dwc_otg_dev_out_ep_regs_t *out_ep_regs[MAX_EPS_CHANNELS];
++#define DWC_DEV_OUT_EP_REG_OFFSET 0xB00
++
++ /* Device configuration information */
++ uint8_t speed; /**< Device Speed 0: Unknown, 1: LS, 2:FS, 3: HS */
++ uint8_t num_in_eps; /**< Number # of Tx EP range: 0-15 exept ep0 */
++ uint8_t num_out_eps; /**< Number # of Rx EP range: 0-15 exept ep 0*/
++
++ /** Size of periodic FIFOs (Bytes) */
++ uint16_t perio_tx_fifo_size[MAX_PERIO_FIFOS];
++
++ /** Size of Tx FIFOs (Bytes) */
++ uint16_t tx_fifo_size[MAX_TX_FIFOS];
++
++ /** Thresholding enable flags and length varaiables **/
++ uint16_t rx_thr_en;
++ uint16_t iso_tx_thr_en;
++ uint16_t non_iso_tx_thr_en;
++
++ uint16_t rx_thr_length;
++ uint16_t tx_thr_length;
++
++ /**
++ * Pointers to the DMA Descriptors for EP0 Control
++ * transfers (virtual and physical)
++ */
++
++ /** 2 descriptors for SETUP packets */
++ dwc_dma_t dma_setup_desc_addr[2];
++ dwc_otg_dev_dma_desc_t *setup_desc_addr[2];
++
++ /** Pointer to Descriptor with latest SETUP packet */
++ dwc_otg_dev_dma_desc_t *psetup;
++
++ /** Index of current SETUP handler descriptor */
++ uint32_t setup_desc_index;
++
++ /** Descriptor for Data In or Status In phases */
++ dwc_dma_t dma_in_desc_addr;
++ dwc_otg_dev_dma_desc_t *in_desc_addr;
++
++ /** Descriptor for Data Out or Status Out phases */
++ dwc_dma_t dma_out_desc_addr;
++ dwc_otg_dev_dma_desc_t *out_desc_addr;
++
++ /** Setup Packet Detected - if set clear NAK when queueing */
++ uint32_t spd;
++ /** Isoc ep pointer on which incomplete happens */
++ void *isoc_ep;
++
++} dwc_otg_dev_if_t;
++
++/////////////////////////////////////////////////
++// Host Mode Register Structures
++//
++/**
++ * The Host Global Registers structure defines the size and relative
++ * field offsets for the Host Mode Global Registers. Host Global
++ * Registers offsets 400h-7FFh.
++*/
++typedef struct dwc_otg_host_global_regs {
++ /** Host Configuration Register. <i>Offset: 400h</i> */
++ volatile uint32_t hcfg;
++ /** Host Frame Interval Register. <i>Offset: 404h</i> */
++ volatile uint32_t hfir;
++ /** Host Frame Number / Frame Remaining Register. <i>Offset: 408h</i> */
++ volatile uint32_t hfnum;
++ /** Reserved. <i>Offset: 40Ch</i> */
++ uint32_t reserved40C;
++ /** Host Periodic Transmit FIFO/ Queue Status Register. <i>Offset: 410h</i> */
++ volatile uint32_t hptxsts;
++ /** Host All Channels Interrupt Register. <i>Offset: 414h</i> */
++ volatile uint32_t haint;
++ /** Host All Channels Interrupt Mask Register. <i>Offset: 418h</i> */
++ volatile uint32_t haintmsk;
++ /** Host Frame List Base Address Register . <i>Offset: 41Ch</i> */
++ volatile uint32_t hflbaddr;
++} dwc_otg_host_global_regs_t;
++
++/**
++ * This union represents the bit fields in the Host Configuration Register.
++ * Read the register into the <i>d32</i> member then set/clear the bits using
++ * the <i>b</i>it elements. Write the <i>d32</i> member to the hcfg register.
++ */
++typedef union hcfg_data {
++ /** raw register data */
++ uint32_t d32;
++
++ /** register bits */
++ struct {
++ /** FS/LS Phy Clock Select */
++ unsigned fslspclksel:2;
++#define DWC_HCFG_30_60_MHZ 0
++#define DWC_HCFG_48_MHZ 1
++#define DWC_HCFG_6_MHZ 2
++
++ /** FS/LS Only Support */
++ unsigned fslssupp:1;
++ unsigned reserved3_6:4;
++ /** Enable 32-KHz Suspend Mode */
++ unsigned ena32khzs:1;
++ /** Resume Validation Periiod */
++ unsigned resvalid:8;
++ unsigned reserved16_22:7;
++ /** Enable Scatter/gather DMA in Host mode */
++ unsigned descdma:1;
++ /** Frame List Entries */
++ unsigned frlisten:2;
++ /** Enable Periodic Scheduling */
++ unsigned perschedena:1;
++ unsigned reserved27_30:4;
++ unsigned modechtimen:1;
++ } b;
++} hcfg_data_t;
++
++/**
++ * This union represents the bit fields in the Host Frame Remaing/Number
++ * Register.
++ */
++typedef union hfir_data {
++ /** raw register data */
++ uint32_t d32;
++
++ /** register bits */
++ struct {
++ unsigned frint:16;
++ unsigned hfirrldctrl:1;
++ unsigned reserved:15;
++ } b;
++} hfir_data_t;
++
++/**
++ * This union represents the bit fields in the Host Frame Remaing/Number
++ * Register.
++ */
++typedef union hfnum_data {
++ /** raw register data */
++ uint32_t d32;
++
++ /** register bits */
++ struct {
++ unsigned frnum:16;
++#define DWC_HFNUM_MAX_FRNUM 0x3FFF
++ unsigned frrem:16;
++ } b;
++} hfnum_data_t;
++
++typedef union hptxsts_data {
++ /** raw register data */
++ uint32_t d32;
++
++ /** register bits */
++ struct {
++ unsigned ptxfspcavail:16;
++ unsigned ptxqspcavail:8;
++ /** Top of the Periodic Transmit Request Queue
++ * - bit 24 - Terminate (last entry for the selected channel)
++ * - bits 26:25 - Token Type
++ * - 2'b00 - Zero length
++ * - 2'b01 - Ping
++ * - 2'b10 - Disable
++ * - bits 30:27 - Channel Number
++ * - bit 31 - Odd/even microframe
++ */
++ unsigned ptxqtop_terminate:1;
++ unsigned ptxqtop_token:2;
++ unsigned ptxqtop_chnum:4;
++ unsigned ptxqtop_odd:1;
++ } b;
++} hptxsts_data_t;
++
++/**
++ * This union represents the bit fields in the Host Port Control and Status
++ * Register. Read the register into the <i>d32</i> member then set/clear the
++ * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
++ * hprt0 register.
++ */
++typedef union hprt0_data {
++ /** raw register data */
++ uint32_t d32;
++ /** register bits */
++ struct {
++ unsigned prtconnsts:1;
++ unsigned prtconndet:1;
++ unsigned prtena:1;
++ unsigned prtenchng:1;
++ unsigned prtovrcurract:1;
++ unsigned prtovrcurrchng:1;
++ unsigned prtres:1;
++ unsigned prtsusp:1;
++ unsigned prtrst:1;
++ unsigned reserved9:1;
++ unsigned prtlnsts:2;
++ unsigned prtpwr:1;
++ unsigned prttstctl:4;
++ unsigned prtspd:2;
++#define DWC_HPRT0_PRTSPD_HIGH_SPEED 0
++#define DWC_HPRT0_PRTSPD_FULL_SPEED 1
++#define DWC_HPRT0_PRTSPD_LOW_SPEED 2
++ unsigned reserved19_31:13;
++ } b;
++} hprt0_data_t;
++
++/**
++ * This union represents the bit fields in the Host All Interrupt
++ * Register.
++ */
++typedef union haint_data {
++ /** raw register data */
++ uint32_t d32;
++ /** register bits */
++ struct {
++ unsigned ch0:1;
++ unsigned ch1:1;
++ unsigned ch2:1;
++ unsigned ch3:1;
++ unsigned ch4:1;
++ unsigned ch5:1;
++ unsigned ch6:1;
++ unsigned ch7:1;
++ unsigned ch8:1;
++ unsigned ch9:1;
++ unsigned ch10:1;
++ unsigned ch11:1;
++ unsigned ch12:1;
++ unsigned ch13:1;
++ unsigned ch14:1;
++ unsigned ch15:1;
++ unsigned reserved:16;
++ } b;
++
++ struct {
++ unsigned chint:16;
++ unsigned reserved:16;
++ } b2;
++} haint_data_t;
++
++/**
++ * This union represents the bit fields in the Host All Interrupt
++ * Register.
++ */
++typedef union haintmsk_data {
++ /** raw register data */
++ uint32_t d32;
++ /** register bits */
++ struct {
++ unsigned ch0:1;
++ unsigned ch1:1;
++ unsigned ch2:1;
++ unsigned ch3:1;
++ unsigned ch4:1;
++ unsigned ch5:1;
++ unsigned ch6:1;
++ unsigned ch7:1;
++ unsigned ch8:1;
++ unsigned ch9:1;
++ unsigned ch10:1;
++ unsigned ch11:1;
++ unsigned ch12:1;
++ unsigned ch13:1;
++ unsigned ch14:1;
++ unsigned ch15:1;
++ unsigned reserved:16;
++ } b;
++
++ struct {
++ unsigned chint:16;
++ unsigned reserved:16;
++ } b2;
++} haintmsk_data_t;
++
++/**
++ * Host Channel Specific Registers. <i>500h-5FCh</i>
++ */
++typedef struct dwc_otg_hc_regs {
++ /** Host Channel 0 Characteristic Register. <i>Offset: 500h + (chan_num * 20h) + 00h</i> */
++ volatile uint32_t hcchar;
++ /** Host Channel 0 Split Control Register. <i>Offset: 500h + (chan_num * 20h) + 04h</i> */
++ volatile uint32_t hcsplt;
++ /** Host Channel 0 Interrupt Register. <i>Offset: 500h + (chan_num * 20h) + 08h</i> */
++ volatile uint32_t hcint;
++ /** Host Channel 0 Interrupt Mask Register. <i>Offset: 500h + (chan_num * 20h) + 0Ch</i> */
++ volatile uint32_t hcintmsk;
++ /** Host Channel 0 Transfer Size Register. <i>Offset: 500h + (chan_num * 20h) + 10h</i> */
++ volatile uint32_t hctsiz;
++ /** Host Channel 0 DMA Address Register. <i>Offset: 500h + (chan_num * 20h) + 14h</i> */
++ volatile uint32_t hcdma;
++ volatile uint32_t reserved;
++ /** Host Channel 0 DMA Buffer Address Register. <i>Offset: 500h + (chan_num * 20h) + 1Ch</i> */
++ volatile uint32_t hcdmab;
++} dwc_otg_hc_regs_t;
++
++/**
++ * This union represents the bit fields in the Host Channel Characteristics
++ * Register. Read the register into the <i>d32</i> member then set/clear the
++ * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
++ * hcchar register.
++ */
++typedef union hcchar_data {
++ /** raw register data */
++ uint32_t d32;
++
++ /** register bits */
++ struct {
++ /** Maximum packet size in bytes */
++ unsigned mps:11;
++
++ /** Endpoint number */
++ unsigned epnum:4;
++
++ /** 0: OUT, 1: IN */
++ unsigned epdir:1;
++
++ unsigned reserved:1;
++
++ /** 0: Full/high speed device, 1: Low speed device */
++ unsigned lspddev:1;
++
++ /** 0: Control, 1: Isoc, 2: Bulk, 3: Intr */
++ unsigned eptype:2;
++
++ /** Packets per frame for periodic transfers. 0 is reserved. */
++ unsigned multicnt:2;
++
++ /** Device address */
++ unsigned devaddr:7;
++
++ /**
++ * Frame to transmit periodic transaction.
++ * 0: even, 1: odd
++ */
++ unsigned oddfrm:1;
++
++ /** Channel disable */
++ unsigned chdis:1;
++
++ /** Channel enable */
++ unsigned chen:1;
++ } b;
++} hcchar_data_t;
++
++typedef union hcsplt_data {
++ /** raw register data */
++ uint32_t d32;
++
++ /** register bits */
++ struct {
++ /** Port Address */
++ unsigned prtaddr:7;
++
++ /** Hub Address */
++ unsigned hubaddr:7;
++
++ /** Transaction Position */
++ unsigned xactpos:2;
++#define DWC_HCSPLIT_XACTPOS_MID 0
++#define DWC_HCSPLIT_XACTPOS_END 1
++#define DWC_HCSPLIT_XACTPOS_BEGIN 2
++#define DWC_HCSPLIT_XACTPOS_ALL 3
++
++ /** Do Complete Split */
++ unsigned compsplt:1;
++
++ /** Reserved */
++ unsigned reserved:14;
++
++ /** Split Enble */
++ unsigned spltena:1;
++ } b;
++} hcsplt_data_t;
++
++/**
++ * This union represents the bit fields in the Host All Interrupt
++ * Register.
++ */
++typedef union hcint_data {
++ /** raw register data */
++ uint32_t d32;
++ /** register bits */
++ struct {
++ /** Transfer Complete */
++ unsigned xfercomp:1;
++ /** Channel Halted */
++ unsigned chhltd:1;
++ /** AHB Error */
++ unsigned ahberr:1;
++ /** STALL Response Received */
++ unsigned stall:1;
++ /** NAK Response Received */
++ unsigned nak:1;
++ /** ACK Response Received */
++ unsigned ack:1;
++ /** NYET Response Received */
++ unsigned nyet:1;
++ /** Transaction Err */
++ unsigned xacterr:1;
++ /** Babble Error */
++ unsigned bblerr:1;
++ /** Frame Overrun */
++ unsigned frmovrun:1;
++ /** Data Toggle Error */
++ unsigned datatglerr:1;
++ /** Buffer Not Available (only for DDMA mode) */
++ unsigned bna:1;
++ /** Exessive transaction error (only for DDMA mode) */
++ unsigned xcs_xact:1;
++ /** Frame List Rollover interrupt */
++ unsigned frm_list_roll:1;
++ /** Reserved */
++ unsigned reserved14_31:18;
++ } b;
++} hcint_data_t;
++
++/**
++ * This union represents the bit fields in the Host Channel Interrupt Mask
++ * Register. Read the register into the <i>d32</i> member then set/clear the
++ * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
++ * hcintmsk register.
++ */
++typedef union hcintmsk_data {
++ /** raw register data */
++ uint32_t d32;
++
++ /** register bits */
++ struct {
++ unsigned xfercompl:1;
++ unsigned chhltd:1;
++ unsigned ahberr:1;
++ unsigned stall:1;
++ unsigned nak:1;
++ unsigned ack:1;
++ unsigned nyet:1;
++ unsigned xacterr:1;
++ unsigned bblerr:1;
++ unsigned frmovrun:1;
++ unsigned datatglerr:1;
++ unsigned bna:1;
++ unsigned xcs_xact:1;
++ unsigned frm_list_roll:1;
++ unsigned reserved14_31:18;
++ } b;
++} hcintmsk_data_t;
++
++/**
++ * This union represents the bit fields in the Host Channel Transfer Size
++ * Register. Read the register into the <i>d32</i> member then set/clear the
++ * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
++ * hcchar register.
++ */
++
++typedef union hctsiz_data {
++ /** raw register data */
++ uint32_t d32;
++
++ /** register bits */
++ struct {
++ /** Total transfer size in bytes */
++ unsigned xfersize:19;
++
++ /** Data packets to transfer */
++ unsigned pktcnt:10;
++
++ /**
++ * Packet ID for next data packet
++ * 0: DATA0
++ * 1: DATA2
++ * 2: DATA1
++ * 3: MDATA (non-Control), SETUP (Control)
++ */
++ unsigned pid:2;
++#define DWC_HCTSIZ_DATA0 0
++#define DWC_HCTSIZ_DATA1 2
++#define DWC_HCTSIZ_DATA2 1
++#define DWC_HCTSIZ_MDATA 3
++#define DWC_HCTSIZ_SETUP 3
++
++ /** Do PING protocol when 1 */
++ unsigned dopng:1;
++ } b;
++
++ /** register bits */
++ struct {
++ /** Scheduling information */
++ unsigned schinfo:8;
++
++ /** Number of transfer descriptors.
++ * Max value:
++ * 64 in general,
++ * 256 only for HS isochronous endpoint.
++ */
++ unsigned ntd:8;
++
++ /** Data packets to transfer */
++ unsigned reserved16_28:13;
++
++ /**
++ * Packet ID for next data packet
++ * 0: DATA0
++ * 1: DATA2
++ * 2: DATA1
++ * 3: MDATA (non-Control)
++ */
++ unsigned pid:2;
++
++ /** Do PING protocol when 1 */
++ unsigned dopng:1;
++ } b_ddma;
++} hctsiz_data_t;
++
++/**
++ * This union represents the bit fields in the Host DMA Address
++ * Register used in Descriptor DMA mode.
++ */
++typedef union hcdma_data {
++ /** raw register data */
++ uint32_t d32;
++ /** register bits */
++ struct {
++ unsigned reserved0_2:3;
++ /** Current Transfer Descriptor. Not used for ISOC */
++ unsigned ctd:8;
++ /** Start Address of Descriptor List */
++ unsigned dma_addr:21;
++ } b;
++} hcdma_data_t;
++
++/**
++ * This union represents the bit fields in the DMA Descriptor
++ * status quadlet for host mode. Read the quadlet into the <i>d32</i> member then
++ * set/clear the bits using the <i>b</i>it elements.
++ */
++typedef union host_dma_desc_sts {
++ /** raw register data */
++ uint32_t d32;
++ /** quadlet bits */
++
++ /* for non-isochronous */
++ struct {
++ /** Number of bytes */
++ unsigned n_bytes:17;
++ /** QTD offset to jump when Short Packet received - only for IN EPs */
++ unsigned qtd_offset:6;
++ /**
++ * Set to request the core to jump to alternate QTD if
++ * Short Packet received - only for IN EPs
++ */
++ unsigned a_qtd:1;
++ /**
++ * Setup Packet bit. When set indicates that buffer contains
++ * setup packet.
++ */
++ unsigned sup:1;
++ /** Interrupt On Complete */
++ unsigned ioc:1;
++ /** End of List */
++ unsigned eol:1;
++ unsigned reserved27:1;
++ /** Rx/Tx Status */
++ unsigned sts:2;
++#define DMA_DESC_STS_PKTERR 1
++ unsigned reserved30:1;
++ /** Active Bit */
++ unsigned a:1;
++ } b;
++ /* for isochronous */
++ struct {
++ /** Number of bytes */
++ unsigned n_bytes:12;
++ unsigned reserved12_24:13;
++ /** Interrupt On Complete */
++ unsigned ioc:1;
++ unsigned reserved26_27:2;
++ /** Rx/Tx Status */
++ unsigned sts:2;
++ unsigned reserved30:1;
++ /** Active Bit */
++ unsigned a:1;
++ } b_isoc;
++} host_dma_desc_sts_t;
++
++#define MAX_DMA_DESC_SIZE 131071
++#define MAX_DMA_DESC_NUM_GENERIC 64
++#define MAX_DMA_DESC_NUM_HS_ISOC 256
++#define MAX_FRLIST_EN_NUM 64
++/**
++ * Host-mode DMA Descriptor structure
++ *
++ * DMA Descriptor structure contains two quadlets:
++ * Status quadlet and Data buffer pointer.
++ */
++typedef struct dwc_otg_host_dma_desc {
++ /** DMA Descriptor status quadlet */
++ host_dma_desc_sts_t status;
++ /** DMA Descriptor data buffer pointer */
++ uint32_t buf;
++} dwc_otg_host_dma_desc_t;
++
++/** OTG Host Interface Structure.
++ *
++ * The OTG Host Interface Structure structure contains information
++ * needed to manage the DWC_otg controller acting in host mode. It
++ * represents the programming view of the host-specific aspects of the
++ * controller.
++ */
++typedef struct dwc_otg_host_if {
++ /** Host Global Registers starting at offset 400h.*/
++ dwc_otg_host_global_regs_t *host_global_regs;
++#define DWC_OTG_HOST_GLOBAL_REG_OFFSET 0x400
++
++ /** Host Port 0 Control and Status Register */
++ volatile uint32_t *hprt0;
++#define DWC_OTG_HOST_PORT_REGS_OFFSET 0x440
++
++ /** Host Channel Specific Registers at offsets 500h-5FCh. */
++ dwc_otg_hc_regs_t *hc_regs[MAX_EPS_CHANNELS];
++#define DWC_OTG_HOST_CHAN_REGS_OFFSET 0x500
++#define DWC_OTG_CHAN_REGS_OFFSET 0x20
++
++ /* Host configuration information */
++ /** Number of Host Channels (range: 1-16) */
++ uint8_t num_host_channels;
++ /** Periodic EPs supported (0: no, 1: yes) */
++ uint8_t perio_eps_supported;
++ /** Periodic Tx FIFO Size (Only 1 host periodic Tx FIFO) */
++ uint16_t perio_tx_fifo_size;
++
++} dwc_otg_host_if_t;
++
++/**
++ * This union represents the bit fields in the Power and Clock Gating Control
++ * Register. Read the register into the <i>d32</i> member then set/clear the
++ * bits using the <i>b</i>it elements.
++ */
++typedef union pcgcctl_data {
++ /** raw register data */
++ uint32_t d32;
++
++ /** register bits */
++ struct {
++ /** Stop Pclk */
++ unsigned stoppclk:1;
++ /** Gate Hclk */
++ unsigned gatehclk:1;
++ /** Power Clamp */
++ unsigned pwrclmp:1;
++ /** Reset Power Down Modules */
++ unsigned rstpdwnmodule:1;
++ /** Reserved */
++ unsigned reserved:1;
++ /** Enable Sleep Clock Gating (Enbl_L1Gating) */
++ unsigned enbl_sleep_gating:1;
++ /** PHY In Sleep (PhySleep) */
++ unsigned phy_in_sleep:1;
++ /** Deep Sleep*/
++ unsigned deep_sleep:1;
++ unsigned resetaftsusp:1;
++ unsigned restoremode:1;
++ unsigned enbl_extnd_hiber:1;
++ unsigned extnd_hiber_pwrclmp:1;
++ unsigned extnd_hiber_switch:1;
++ unsigned ess_reg_restored:1;
++ unsigned prt_clk_sel:2;
++ unsigned port_power:1;
++ unsigned max_xcvrselect:2;
++ unsigned max_termsel:1;
++ unsigned mac_dev_addr:7;
++ unsigned p2hd_dev_enum_spd:2;
++ unsigned p2hd_prt_spd:2;
++ unsigned if_dev_mode:1;
++ } b;
++} pcgcctl_data_t;
++
++/**
++ * This union represents the bit fields in the Global Data FIFO Software
++ * Configuration Register. Read the register into the <i>d32</i> member then
++ * set/clear the bits using the <i>b</i>it elements.
++ */
++typedef union gdfifocfg_data {
++ /* raw register data */
++ uint32_t d32;
++ /** register bits */
++ struct {
++ /** OTG Data FIFO depth */
++ unsigned gdfifocfg:16;
++ /** Start address of EP info controller */
++ unsigned epinfobase:16;
++ } b;
++} gdfifocfg_data_t;
++
++/**
++ * This union represents the bit fields in the Global Power Down Register
++ * Register. Read the register into the <i>d32</i> member then set/clear the
++ * bits using the <i>b</i>it elements.
++ */
++typedef union gpwrdn_data {
++ /* raw register data */
++ uint32_t d32;
++
++ /** register bits */
++ struct {
++ /** PMU Interrupt Select */
++ unsigned pmuintsel:1;
++ /** PMU Active */
++ unsigned pmuactv:1;
++ /** Restore */
++ unsigned restore:1;
++ /** Power Down Clamp */
++ unsigned pwrdnclmp:1;
++ /** Power Down Reset */
++ unsigned pwrdnrstn:1;
++ /** Power Down Switch */
++ unsigned pwrdnswtch:1;
++ /** Disable VBUS */
++ unsigned dis_vbus:1;
++ /** Line State Change */
++ unsigned lnstschng:1;
++ /** Line state change mask */
++ unsigned lnstchng_msk:1;
++ /** Reset Detected */
++ unsigned rst_det:1;
++ /** Reset Detect mask */
++ unsigned rst_det_msk:1;
++ /** Disconnect Detected */
++ unsigned disconn_det:1;
++ /** Disconnect Detect mask */
++ unsigned disconn_det_msk:1;
++ /** Connect Detected*/
++ unsigned connect_det:1;
++ /** Connect Detected Mask*/
++ unsigned connect_det_msk:1;
++ /** SRP Detected */
++ unsigned srp_det:1;
++ /** SRP Detect mask */
++ unsigned srp_det_msk:1;
++ /** Status Change Interrupt */
++ unsigned sts_chngint:1;
++ /** Status Change Interrupt Mask */
++ unsigned sts_chngint_msk:1;
++ /** Line State */
++ unsigned linestate:2;
++ /** Indicates current mode(status of IDDIG signal) */
++ unsigned idsts:1;
++ /** B Session Valid signal status*/
++ unsigned bsessvld:1;
++ /** ADP Event Detected */
++ unsigned adp_int:1;
++ /** Multi Valued ID pin */
++ unsigned mult_val_id_bc:5;
++ /** Reserved 24_31 */
++ unsigned reserved29_31:3;
++ } b;
++} gpwrdn_data_t;
++
++#endif
+diff -Nur linux-4.1.3/drivers/usb/host/dwc_otg/Makefile linux-xbian-rpi/drivers/usb/host/dwc_otg/Makefile
+--- linux-4.1.3/drivers/usb/host/dwc_otg/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/usb/host/dwc_otg/Makefile 2015-07-28 01:20:58.445156473 +0200
+@@ -0,0 +1,82 @@
++#
++# Makefile for DWC_otg Highspeed USB controller driver
++#
++
++ifneq ($(KERNELRELEASE),)
++
++# Use the BUS_INTERFACE variable to compile the software for either
++# PCI(PCI_INTERFACE) or LM(LM_INTERFACE) bus.
++ifeq ($(BUS_INTERFACE),)
++# BUS_INTERFACE = -DPCI_INTERFACE
++# BUS_INTERFACE = -DLM_INTERFACE
++ BUS_INTERFACE = -DPLATFORM_INTERFACE
++endif
++
++#ccflags-y += -DDEBUG
++#ccflags-y += -DDWC_OTG_DEBUGLEV=1 # reduce common debug msgs
++
++# Use one of the following flags to compile the software in host-only or
++# device-only mode.
++#ccflags-y += -DDWC_HOST_ONLY
++#ccflags-y += -DDWC_DEVICE_ONLY
++
++ccflags-y += -Dlinux -DDWC_HS_ELECT_TST
++#ccflags-y += -DDWC_EN_ISOC
++ccflags-y += -I$(obj)/../dwc_common_port
++#ccflags-y += -I$(PORTLIB)
++ccflags-y += -DDWC_LINUX
++ccflags-y += $(CFI)
++ccflags-y += $(BUS_INTERFACE)
++#ccflags-y += -DDWC_DEV_SRPCAP
++
++obj-$(CONFIG_USB_DWCOTG) += dwc_otg.o
++
++dwc_otg-objs := dwc_otg_driver.o dwc_otg_attr.o
++dwc_otg-objs += dwc_otg_cil.o dwc_otg_cil_intr.o
++dwc_otg-objs += dwc_otg_pcd_linux.o dwc_otg_pcd.o dwc_otg_pcd_intr.o
++dwc_otg-objs += dwc_otg_hcd.o dwc_otg_hcd_linux.o dwc_otg_hcd_intr.o dwc_otg_hcd_queue.o dwc_otg_hcd_ddma.o
++dwc_otg-objs += dwc_otg_adp.o
++dwc_otg-objs += dwc_otg_fiq_fsm.o
++dwc_otg-objs += dwc_otg_fiq_stub.o
++ifneq ($(CFI),)
++dwc_otg-objs += dwc_otg_cfi.o
++endif
++
++kernrelwd := $(subst ., ,$(KERNELRELEASE))
++kernrel3 := $(word 1,$(kernrelwd)).$(word 2,$(kernrelwd)).$(word 3,$(kernrelwd))
++
++ifneq ($(kernrel3),2.6.20)
++ccflags-y += $(CPPFLAGS)
++endif
++
++else
++
++PWD := $(shell pwd)
++PORTLIB := $(PWD)/../dwc_common_port
++
++# Command paths
++CTAGS := $(CTAGS)
++DOXYGEN := $(DOXYGEN)
++
++default: portlib
++ $(MAKE) -C$(KDIR) M=$(PWD) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) modules
++
++install: default
++ $(MAKE) -C$(KDIR) M=$(PORTLIB) modules_install
++ $(MAKE) -C$(KDIR) M=$(PWD) modules_install
++
++portlib:
++ $(MAKE) -C$(KDIR) M=$(PORTLIB) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) modules
++ cp $(PORTLIB)/Module.symvers $(PWD)/
++
++docs: $(wildcard *.[hc]) doc/doxygen.cfg
++ $(DOXYGEN) doc/doxygen.cfg
++
++tags: $(wildcard *.[hc])
++ $(CTAGS) -e $(wildcard *.[hc]) $(wildcard linux/*.[hc]) $(wildcard $(KDIR)/include/linux/usb*.h)
++
++
++clean:
++ rm -rf *.o *.ko .*cmd *.mod.c .tmp_versions Module.symvers
++
++endif
+diff -Nur linux-4.1.3/drivers/usb/host/dwc_otg/test/dwc_otg_test.pm linux-xbian-rpi/drivers/usb/host/dwc_otg/test/dwc_otg_test.pm
+--- linux-4.1.3/drivers/usb/host/dwc_otg/test/dwc_otg_test.pm 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/usb/host/dwc_otg/test/dwc_otg_test.pm 2015-07-28 01:20:58.449142252 +0200
+@@ -0,0 +1,337 @@
++package dwc_otg_test;
++
++use strict;
++use Exporter ();
++
++use vars qw(@ISA @EXPORT
++$sysfsdir $paramdir $errors $params
++);
++
++@ISA = qw(Exporter);
++
++#
++# Globals
++#
++$sysfsdir = "/sys/devices/lm0";
++$paramdir = "/sys/module/dwc_otg";
++$errors = 0;
++
++$params = [
++ {
++ NAME => "otg_cap",
++ DEFAULT => 0,
++ ENUM => [],
++ LOW => 0,
++ HIGH => 2
++ },
++ {
++ NAME => "dma_enable",
++ DEFAULT => 0,
++ ENUM => [],
++ LOW => 0,
++ HIGH => 1
++ },
++ {
++ NAME => "dma_burst_size",
++ DEFAULT => 32,
++ ENUM => [1, 4, 8, 16, 32, 64, 128, 256],
++ LOW => 1,
++ HIGH => 256
++ },
++ {
++ NAME => "host_speed",
++ DEFAULT => 0,
++ ENUM => [],
++ LOW => 0,
++ HIGH => 1
++ },
++ {
++ NAME => "host_support_fs_ls_low_power",
++ DEFAULT => 0,
++ ENUM => [],
++ LOW => 0,
++ HIGH => 1
++ },
++ {
++ NAME => "host_ls_low_power_phy_clk",
++ DEFAULT => 0,
++ ENUM => [],
++ LOW => 0,
++ HIGH => 1
++ },
++ {
++ NAME => "dev_speed",
++ DEFAULT => 0,
++ ENUM => [],
++ LOW => 0,
++ HIGH => 1
++ },
++ {
++ NAME => "enable_dynamic_fifo",
++ DEFAULT => 1,
++ ENUM => [],
++ LOW => 0,
++ HIGH => 1
++ },
++ {
++ NAME => "data_fifo_size",
++ DEFAULT => 8192,
++ ENUM => [],
++ LOW => 32,
++ HIGH => 32768
++ },
++ {
++ NAME => "dev_rx_fifo_size",
++ DEFAULT => 1064,
++ ENUM => [],
++ LOW => 16,
++ HIGH => 32768
++ },
++ {
++ NAME => "dev_nperio_tx_fifo_size",
++ DEFAULT => 1024,
++ ENUM => [],
++ LOW => 16,
++ HIGH => 32768
++ },
++ {
++ NAME => "dev_perio_tx_fifo_size_1",
++ DEFAULT => 256,
++ ENUM => [],
++ LOW => 4,
++ HIGH => 768
++ },
++ {
++ NAME => "dev_perio_tx_fifo_size_2",
++ DEFAULT => 256,
++ ENUM => [],
++ LOW => 4,
++ HIGH => 768
++ },
++ {
++ NAME => "dev_perio_tx_fifo_size_3",
++ DEFAULT => 256,
++ ENUM => [],
++ LOW => 4,
++ HIGH => 768
++ },
++ {
++ NAME => "dev_perio_tx_fifo_size_4",
++ DEFAULT => 256,
++ ENUM => [],
++ LOW => 4,
++ HIGH => 768
++ },
++ {
++ NAME => "dev_perio_tx_fifo_size_5",
++ DEFAULT => 256,
++ ENUM => [],
++ LOW => 4,
++ HIGH => 768
++ },
++ {
++ NAME => "dev_perio_tx_fifo_size_6",
++ DEFAULT => 256,
++ ENUM => [],
++ LOW => 4,
++ HIGH => 768
++ },
++ {
++ NAME => "dev_perio_tx_fifo_size_7",
++ DEFAULT => 256,
++ ENUM => [],
++ LOW => 4,
++ HIGH => 768
++ },
++ {
++ NAME => "dev_perio_tx_fifo_size_8",
++ DEFAULT => 256,
++ ENUM => [],
++ LOW => 4,
++ HIGH => 768
++ },
++ {
++ NAME => "dev_perio_tx_fifo_size_9",
++ DEFAULT => 256,
++ ENUM => [],
++ LOW => 4,
++ HIGH => 768
++ },
++ {
++ NAME => "dev_perio_tx_fifo_size_10",
++ DEFAULT => 256,
++ ENUM => [],
++ LOW => 4,
++ HIGH => 768
++ },
++ {
++ NAME => "dev_perio_tx_fifo_size_11",
++ DEFAULT => 256,
++ ENUM => [],
++ LOW => 4,
++ HIGH => 768
++ },
++ {
++ NAME => "dev_perio_tx_fifo_size_12",
++ DEFAULT => 256,
++ ENUM => [],
++ LOW => 4,
++ HIGH => 768
++ },
++ {
++ NAME => "dev_perio_tx_fifo_size_13",
++ DEFAULT => 256,
++ ENUM => [],
++ LOW => 4,
++ HIGH => 768
++ },
++ {
++ NAME => "dev_perio_tx_fifo_size_14",
++ DEFAULT => 256,
++ ENUM => [],
++ LOW => 4,
++ HIGH => 768
++ },
++ {
++ NAME => "dev_perio_tx_fifo_size_15",
++ DEFAULT => 256,
++ ENUM => [],
++ LOW => 4,
++ HIGH => 768
++ },
++ {
++ NAME => "host_rx_fifo_size",
++ DEFAULT => 1024,
++ ENUM => [],
++ LOW => 16,
++ HIGH => 32768
++ },
++ {
++ NAME => "host_nperio_tx_fifo_size",
++ DEFAULT => 1024,
++ ENUM => [],
++ LOW => 16,
++ HIGH => 32768
++ },
++ {
++ NAME => "host_perio_tx_fifo_size",
++ DEFAULT => 1024,
++ ENUM => [],
++ LOW => 16,
++ HIGH => 32768
++ },
++ {
++ NAME => "max_transfer_size",
++ DEFAULT => 65535,
++ ENUM => [],
++ LOW => 2047,
++ HIGH => 65535
++ },
++ {
++ NAME => "max_packet_count",
++ DEFAULT => 511,
++ ENUM => [],
++ LOW => 15,
++ HIGH => 511
++ },
++ {
++ NAME => "host_channels",
++ DEFAULT => 12,
++ ENUM => [],
++ LOW => 1,
++ HIGH => 16
++ },
++ {
++ NAME => "dev_endpoints",
++ DEFAULT => 6,
++ ENUM => [],
++ LOW => 1,
++ HIGH => 15
++ },
++ {
++ NAME => "phy_type",
++ DEFAULT => 1,
++ ENUM => [],
++ LOW => 0,
++ HIGH => 2
++ },
++ {
++ NAME => "phy_utmi_width",
++ DEFAULT => 16,
++ ENUM => [8, 16],
++ LOW => 8,
++ HIGH => 16
++ },
++ {
++ NAME => "phy_ulpi_ddr",
++ DEFAULT => 0,
++ ENUM => [],
++ LOW => 0,
++ HIGH => 1
++ },
++ ];
++
++
++#
++#
++sub check_arch {
++ $_ = `uname -m`;
++ chomp;
++ unless (m/armv4tl/) {
++ warn "# \n# Can't execute on $_. Run on integrator platform.\n# \n";
++ return 0;
++ }
++ return 1;
++}
++
++#
++#
++sub load_module {
++ my $params = shift;
++ print "\nRemoving Module\n";
++ system "rmmod dwc_otg";
++ print "Loading Module\n";
++ if ($params ne "") {
++ print "Module Parameters: $params\n";
++ }
++ if (system("modprobe dwc_otg $params")) {
++ warn "Unable to load module\n";
++ return 0;
++ }
++ return 1;
++}
++
++#
++#
++sub test_status {
++ my $arg = shift;
++
++ print "\n";
++
++ if (defined $arg) {
++ warn "WARNING: $arg\n";
++ }
++
++ if ($errors > 0) {
++ warn "TEST FAILED with $errors errors\n";
++ return 0;
++ } else {
++ print "TEST PASSED\n";
++ return 0 if (defined $arg);
++ }
++ return 1;
++}
++
++#
++#
++@EXPORT = qw(
++$sysfsdir
++$paramdir
++$params
++$errors
++check_arch
++load_module
++test_status
++);
++
++1;
+diff -Nur linux-4.1.3/drivers/usb/host/dwc_otg/test/Makefile linux-xbian-rpi/drivers/usb/host/dwc_otg/test/Makefile
+--- linux-4.1.3/drivers/usb/host/dwc_otg/test/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/usb/host/dwc_otg/test/Makefile 2015-07-28 01:20:58.449142252 +0200
+@@ -0,0 +1,16 @@
++
++PERL=/usr/bin/perl
++PL_TESTS=test_sysfs.pl test_mod_param.pl
++
++.PHONY : test
++test : perl_tests
++
++perl_tests :
++ @echo
++ @echo Running perl tests
++ @for test in $(PL_TESTS); do \
++ if $(PERL) ./$$test ; then \
++ echo "=======> $$test, PASSED" ; \
++ else echo "=======> $$test, FAILED" ; \
++ fi \
++ done
+diff -Nur linux-4.1.3/drivers/usb/host/dwc_otg/test/test_mod_param.pl linux-xbian-rpi/drivers/usb/host/dwc_otg/test/test_mod_param.pl
+--- linux-4.1.3/drivers/usb/host/dwc_otg/test/test_mod_param.pl 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/usb/host/dwc_otg/test/test_mod_param.pl 2015-07-28 01:20:58.449142252 +0200
+@@ -0,0 +1,133 @@
++#!/usr/bin/perl -w
++#
++# Run this program on the integrator.
++#
++# - Tests module parameter default values.
++# - Tests setting of valid module parameter values via modprobe.
++# - Tests invalid module parameter values.
++# -----------------------------------------------------------------------------
++use strict;
++use dwc_otg_test;
++
++check_arch() or die;
++
++#
++#
++sub test {
++ my ($param,$expected) = @_;
++ my $value = get($param);
++
++ if ($value == $expected) {
++ print "$param = $value, okay\n";
++ }
++
++ else {
++ warn "ERROR: value of $param != $expected, $value\n";
++ $errors ++;
++ }
++}
++
++#
++#
++sub get {
++ my $param = shift;
++ my $tmp = `cat $paramdir/$param`;
++ chomp $tmp;
++ return $tmp;
++}
++
++#
++#
++sub test_main {
++
++ print "\nTesting Module Parameters\n";
++
++ load_module("") or die;
++
++ # Test initial values
++ print "\nTesting Default Values\n";
++ foreach (@{$params}) {
++ test ($_->{NAME}, $_->{DEFAULT});
++ }
++
++ # Test low value
++ print "\nTesting Low Value\n";
++ my $cmd_params = "";
++ foreach (@{$params}) {
++ $cmd_params = $cmd_params . "$_->{NAME}=$_->{LOW} ";
++ }
++ load_module($cmd_params) or die;
++
++ foreach (@{$params}) {
++ test ($_->{NAME}, $_->{LOW});
++ }
++
++ # Test high value
++ print "\nTesting High Value\n";
++ $cmd_params = "";
++ foreach (@{$params}) {
++ $cmd_params = $cmd_params . "$_->{NAME}=$_->{HIGH} ";
++ }
++ load_module($cmd_params) or die;
++
++ foreach (@{$params}) {
++ test ($_->{NAME}, $_->{HIGH});
++ }
++
++ # Test Enum
++ print "\nTesting Enumerated\n";
++ foreach (@{$params}) {
++ if (defined $_->{ENUM}) {
++ my $value;
++ foreach $value (@{$_->{ENUM}}) {
++ $cmd_params = "$_->{NAME}=$value";
++ load_module($cmd_params) or die;
++ test ($_->{NAME}, $value);
++ }
++ }
++ }
++
++ # Test Invalid Values
++ print "\nTesting Invalid Values\n";
++ $cmd_params = "";
++ foreach (@{$params}) {
++ $cmd_params = $cmd_params . sprintf "$_->{NAME}=%d ", $_->{LOW}-1;
++ }
++ load_module($cmd_params) or die;
++
++ foreach (@{$params}) {
++ test ($_->{NAME}, $_->{DEFAULT});
++ }
++
++ $cmd_params = "";
++ foreach (@{$params}) {
++ $cmd_params = $cmd_params . sprintf "$_->{NAME}=%d ", $_->{HIGH}+1;
++ }
++ load_module($cmd_params) or die;
++
++ foreach (@{$params}) {
++ test ($_->{NAME}, $_->{DEFAULT});
++ }
++
++ print "\nTesting Enumerated\n";
++ foreach (@{$params}) {
++ if (defined $_->{ENUM}) {
++ my $value;
++ foreach $value (@{$_->{ENUM}}) {
++ $value = $value + 1;
++ $cmd_params = "$_->{NAME}=$value";
++ load_module($cmd_params) or die;
++ test ($_->{NAME}, $_->{DEFAULT});
++ $value = $value - 2;
++ $cmd_params = "$_->{NAME}=$value";
++ load_module($cmd_params) or die;
++ test ($_->{NAME}, $_->{DEFAULT});
++ }
++ }
++ }
++
++ test_status() or die;
++}
++
++test_main();
++0;
+diff -Nur linux-4.1.3/drivers/usb/host/dwc_otg/test/test_sysfs.pl linux-xbian-rpi/drivers/usb/host/dwc_otg/test/test_sysfs.pl
+--- linux-4.1.3/drivers/usb/host/dwc_otg/test/test_sysfs.pl 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/usb/host/dwc_otg/test/test_sysfs.pl 2015-07-28 01:20:58.449142252 +0200
+@@ -0,0 +1,193 @@
++#!/usr/bin/perl -w
++#
++# Run this program on the integrator
++# - Tests select sysfs attributes.
++# - Todo ... test more attributes, hnp/srp, buspower/bussuspend, etc.
++# -----------------------------------------------------------------------------
++use strict;
++use dwc_otg_test;
++
++check_arch() or die;
++
++#
++#
++sub test {
++ my ($attr,$expected) = @_;
++ my $string = get($attr);
++
++ if ($string eq $expected) {
++ printf("$attr = $string, okay\n");
++ }
++ else {
++ warn "ERROR: value of $attr != $expected, $string\n";
++ $errors ++;
++ }
++}
++
++#
++#
++sub set {
++ my ($reg, $value) = @_;
++ system "echo $value > $sysfsdir/$reg";
++}
++
++#
++#
++sub get {
++ my $attr = shift;
++ my $string = `cat $sysfsdir/$attr`;
++ chomp $string;
++ if ($string =~ m/\s\=\s/) {
++ my $tmp;
++ ($tmp, $string) = split /\s=\s/, $string;
++ }
++ return $string;
++}
++
++#
++#
++sub test_main {
++ print("\nTesting Sysfs Attributes\n");
++
++ load_module("") or die;
++
++ # Test initial values of regoffset/regvalue/guid/gsnpsid
++ print("\nTesting Default Values\n");
++
++ test("regoffset", "0xffffffff");
++ test("regvalue", "invalid offset");
++ test("guid", "0x12345678"); # this will fail if it has been changed
++ test("gsnpsid", "0x4f54200a");
++
++ # Test operation of regoffset/regvalue
++ print("\nTesting regoffset\n");
++ set('regoffset', '5a5a5a5a');
++ test("regoffset", "0xffffffff");
++
++ set('regoffset', '0');
++ test("regoffset", "0x00000000");
++
++ set('regoffset', '40000');
++ test("regoffset", "0x00000000");
++
++ set('regoffset', '3ffff');
++ test("regoffset", "0x0003ffff");
++
++ set('regoffset', '1');
++ test("regoffset", "0x00000001");
++
++ print("\nTesting regvalue\n");
++ set('regoffset', '3c');
++ test("regvalue", "0x12345678");
++ set('regvalue', '5a5a5a5a');
++ test("regvalue", "0x5a5a5a5a");
++ set('regvalue','a5a5a5a5');
++ test("regvalue", "0xa5a5a5a5");
++ set('guid','12345678');
++
++ # Test HNP Capable
++ print("\nTesting HNP Capable bit\n");
++ set('hnpcapable', '1');
++ test("hnpcapable", "0x1");
++ set('hnpcapable','0');
++ test("hnpcapable", "0x0");
++
++ set('regoffset','0c');
++
++ my $old = get('gusbcfg');
++ print("setting hnpcapable\n");
++ set('hnpcapable', '1');
++ test("hnpcapable", "0x1");
++ test('gusbcfg', sprintf "0x%08x", (oct ($old) | (1<<9)));
++ test('regvalue', sprintf "0x%08x", (oct ($old) | (1<<9)));
++
++ $old = get('gusbcfg');
++ print("clearing hnpcapable\n");
++ set('hnpcapable', '0');
++ test("hnpcapable", "0x0");
++ test ('gusbcfg', sprintf "0x%08x", oct ($old) & (~(1<<9)));
++ test ('regvalue', sprintf "0x%08x", oct ($old) & (~(1<<9)));
++
++ # Test SRP Capable
++ print("\nTesting SRP Capable bit\n");
++ set('srpcapable', '1');
++ test("srpcapable", "0x1");
++ set('srpcapable','0');
++ test("srpcapable", "0x0");
++
++ set('regoffset','0c');
++
++ $old = get('gusbcfg');
++ print("setting srpcapable\n");
++ set('srpcapable', '1');
++ test("srpcapable", "0x1");
++ test('gusbcfg', sprintf "0x%08x", (oct ($old) | (1<<8)));
++ test('regvalue', sprintf "0x%08x", (oct ($old) | (1<<8)));
++
++ $old = get('gusbcfg');
++ print("clearing srpcapable\n");
++ set('srpcapable', '0');
++ test("srpcapable", "0x0");
++ test('gusbcfg', sprintf "0x%08x", oct ($old) & (~(1<<8)));
++ test('regvalue', sprintf "0x%08x", oct ($old) & (~(1<<8)));
++
++ # Test GGPIO
++ print("\nTesting GGPIO\n");
++ set('ggpio','5a5a5a5a');
++ test('ggpio','0x5a5a0000');
++ set('ggpio','a5a5a5a5');
++ test('ggpio','0xa5a50000');
++ set('ggpio','11110000');
++ test('ggpio','0x11110000');
++ set('ggpio','00001111');
++ test('ggpio','0x00000000');
++
++ # Test DEVSPEED
++ print("\nTesting DEVSPEED\n");
++ set('regoffset','800');
++ $old = get('regvalue');
++ set('devspeed','0');
++ test('devspeed','0x0');
++ test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3)));
++ set('devspeed','1');
++ test('devspeed','0x1');
++ test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3) | 1));
++ set('devspeed','2');
++ test('devspeed','0x2');
++ test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3) | 2));
++ set('devspeed','3');
++ test('devspeed','0x3');
++ test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3) | 3));
++ set('devspeed','4');
++ test('devspeed','0x0');
++ test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3)));
++ set('devspeed','5');
++ test('devspeed','0x1');
++ test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3) | 1));
++
++
++ # mode Returns the current mode:0 for device mode1 for host mode Read
++ # hnp Initiate the Host Negotiation Protocol. Read returns the status. Read/Write
++ # srp Initiate the Session Request Protocol. Read returns the status. Read/Write
++ # buspower Get or Set the Power State of the bus (0 - Off or 1 - On) Read/Write
++ # bussuspend Suspend the USB bus. Read/Write
++ # busconnected Get the connection status of the bus Read
++
++ # gotgctl Get or set the Core Control Status Register. Read/Write
++ ## gusbcfg Get or set the Core USB Configuration Register Read/Write
++ # grxfsiz Get or set the Receive FIFO Size Register Read/Write
++ # gnptxfsiz Get or set the non-periodic Transmit Size Register Read/Write
++ # gpvndctl Get or set the PHY Vendor Control Register Read/Write
++ ## ggpio Get the value in the lower 16-bits of the General Purpose IO Register or Set the upper 16 bits. Read/Write
++ ## guid Get or set the value of the User ID Register Read/Write
++ ## gsnpsid Get the value of the Synopsys ID Regester Read
++ ## devspeed Get or set the device speed setting in the DCFG register Read/Write
++ # enumspeed Gets the device enumeration Speed. Read
++ # hptxfsiz Get the value of the Host Periodic Transmit FIFO Read
++ # hprt0 Get or Set the value in the Host Port Control and Status Register Read/Write
++
++ test_status("TEST NYI") or die;
++}
++
++test_main();
++0;
+diff -Nur linux-4.1.3/drivers/usb/host/Kconfig linux-xbian-rpi/drivers/usb/host/Kconfig
+--- linux-4.1.3/drivers/usb/host/Kconfig 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/usb/host/Kconfig 2015-07-28 01:20:58.441170694 +0200
+@@ -738,6 +738,19 @@
+ To compile this driver a module, choose M here: the module
+ will be called "hwa-hc".
+
++config USB_DWCOTG
++ tristate "Synopsis DWC host support"
++ depends on USB
++ help
++ The Synopsis DWC controller is a dual-role
++ host/peripheral/OTG ("On The Go") USB controllers.
++
++ Enable this option to support this IP in host controller mode.
++ If unsure, say N.
++
++ To compile this driver as a module, choose M here: the
++ modules built will be called dwc_otg and dwc_common_port.
++
+ config USB_IMX21_HCD
+ tristate "i.MX21 HCD support"
+ depends on ARM && ARCH_MXC
+diff -Nur linux-4.1.3/drivers/usb/host/Makefile linux-xbian-rpi/drivers/usb/host/Makefile
+--- linux-4.1.3/drivers/usb/host/Makefile 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/usb/host/Makefile 2015-07-28 01:20:58.441170694 +0200
+@@ -68,6 +68,8 @@
+ obj-$(CONFIG_USB_U132_HCD) += u132-hcd.o
+ obj-$(CONFIG_USB_R8A66597_HCD) += r8a66597-hcd.o
+ obj-$(CONFIG_USB_HWA_HCD) += hwa-hc.o
++
++obj-$(CONFIG_USB_DWCOTG) += dwc_otg/ dwc_common_port/
+ obj-$(CONFIG_USB_IMX21_HCD) += imx21-hcd.o
+ obj-$(CONFIG_USB_FSL_MPH_DR_OF) += fsl-mph-dr-of.o
+ obj-$(CONFIG_USB_HCD_BCMA) += bcma-hcd.o
+diff -Nur linux-4.1.3/drivers/usb/Makefile linux-xbian-rpi/drivers/usb/Makefile
+--- linux-4.1.3/drivers/usb/Makefile 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/usb/Makefile 2015-07-28 01:20:58.437184915 +0200
+@@ -7,6 +7,7 @@
+ obj-$(CONFIG_USB) += core/
+ obj-$(CONFIG_USB_SUPPORT) += phy/
+
++obj-$(CONFIG_USB_DWCOTG) += host/
+ obj-$(CONFIG_USB_DWC3) += dwc3/
+ obj-$(CONFIG_USB_DWC2) += dwc2/
+ obj-$(CONFIG_USB_ISP1760) += isp1760/
+diff -Nur linux-4.1.3/drivers/video/fbdev/bcm2708_fb.c linux-xbian-rpi/drivers/video/fbdev/bcm2708_fb.c
+--- linux-4.1.3/drivers/video/fbdev/bcm2708_fb.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/video/fbdev/bcm2708_fb.c 2015-07-28 01:20:58.453128032 +0200
+@@ -0,0 +1,853 @@
++/*
++ * linux/drivers/video/bcm2708_fb.c
++ *
++ * Copyright (C) 2010 Broadcom
++ *
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file COPYING in the main directory of this archive
++ * for more details.
++ *
++ * Broadcom simple framebuffer driver
++ *
++ * This file is derived from cirrusfb.c
++ * Copyright 1999-2001 Jeff Garzik <jgarzik@pobox.com>
++ *
++ */
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/errno.h>
++#include <linux/string.h>
++#include <linux/slab.h>
++#include <linux/mm.h>
++#include <linux/fb.h>
++#include <linux/init.h>
++#include <linux/interrupt.h>
++#include <linux/ioport.h>
++#include <linux/list.h>
++#include <linux/platform_data/dma-bcm2708.h>
++#include <linux/platform_device.h>
++#include <linux/clk.h>
++#include <linux/printk.h>
++#include <linux/console.h>
++#include <linux/debugfs.h>
++#include <asm/sizes.h>
++#include <linux/io.h>
++#include <linux/dma-mapping.h>
++#include <soc/bcm2835/raspberrypi-firmware.h>
++
++//#define BCM2708_FB_DEBUG
++#define MODULE_NAME "bcm2708_fb"
++
++#ifdef BCM2708_FB_DEBUG
++#define print_debug(fmt,...) pr_debug("%s:%s:%d: "fmt, MODULE_NAME, __func__, __LINE__, ##__VA_ARGS__)
++#else
++#define print_debug(fmt,...)
++#endif
++
++/* This is limited to 16 characters when displayed by X startup */
++static const char *bcm2708_name = "BCM2708 FB";
++
++#define DRIVER_NAME "bcm2708_fb"
++
++static int fbwidth = 800; /* module parameter */
++static int fbheight = 480; /* module parameter */
++static int fbdepth = 16; /* module parameter */
++static int fbswap = 0; /* module parameter */
++
++static u32 dma_busy_wait_threshold = 1<<15;
++module_param(dma_busy_wait_threshold, int, 0644);
++MODULE_PARM_DESC(dma_busy_wait_threshold, "Busy-wait for DMA completion below this area");
++
++struct fb_alloc_tags {
++ struct rpi_firmware_property_tag_header tag1;
++ u32 xres, yres;
++ struct rpi_firmware_property_tag_header tag2;
++ u32 xres_virtual, yres_virtual;
++ struct rpi_firmware_property_tag_header tag3;
++ u32 bpp;
++ struct rpi_firmware_property_tag_header tag4;
++ u32 xoffset, yoffset;
++ struct rpi_firmware_property_tag_header tag5;
++ u32 base, screen_size;
++ struct rpi_firmware_property_tag_header tag6;
++ u32 pitch;
++};
++
++struct bcm2708_fb_stats {
++ struct debugfs_regset32 regset;
++ u32 dma_copies;
++ u32 dma_irqs;
++};
++
++struct bcm2708_fb {
++ struct fb_info fb;
++ struct platform_device *dev;
++ struct rpi_firmware *fw;
++ u32 cmap[16];
++ u32 gpu_cmap[256];
++ int dma_chan;
++ int dma_irq;
++ void __iomem *dma_chan_base;
++ void *cb_base; /* DMA control blocks */
++ dma_addr_t cb_handle;
++ struct dentry *debugfs_dir;
++ wait_queue_head_t dma_waitq;
++ struct bcm2708_fb_stats stats;
++ unsigned long fb_bus_address;
++};
++
++#define to_bcm2708(info) container_of(info, struct bcm2708_fb, fb)
++
++static void bcm2708_fb_debugfs_deinit(struct bcm2708_fb *fb)
++{
++ debugfs_remove_recursive(fb->debugfs_dir);
++ fb->debugfs_dir = NULL;
++}
++
++static int bcm2708_fb_debugfs_init(struct bcm2708_fb *fb)
++{
++ static struct debugfs_reg32 stats_registers[] = {
++ {
++ "dma_copies",
++ offsetof(struct bcm2708_fb_stats, dma_copies)
++ },
++ {
++ "dma_irqs",
++ offsetof(struct bcm2708_fb_stats, dma_irqs)
++ },
++ };
++
++ fb->debugfs_dir = debugfs_create_dir(DRIVER_NAME, NULL);
++ if (!fb->debugfs_dir) {
++ pr_warn("%s: could not create debugfs entry\n",
++ __func__);
++ return -EFAULT;
++ }
++
++ fb->stats.regset.regs = stats_registers;
++ fb->stats.regset.nregs = ARRAY_SIZE(stats_registers);
++ fb->stats.regset.base = &fb->stats;
++
++ if (!debugfs_create_regset32(
++ "stats", 0444, fb->debugfs_dir, &fb->stats.regset)) {
++ pr_warn("%s: could not create statistics registers\n",
++ __func__);
++ goto fail;
++ }
++ return 0;
++
++fail:
++ bcm2708_fb_debugfs_deinit(fb);
++ return -EFAULT;
++}
++
++static int bcm2708_fb_set_bitfields(struct fb_var_screeninfo *var)
++{
++ int ret = 0;
++
++ memset(&var->transp, 0, sizeof(var->transp));
++
++ var->red.msb_right = 0;
++ var->green.msb_right = 0;
++ var->blue.msb_right = 0;
++
++ switch (var->bits_per_pixel) {
++ case 1:
++ case 2:
++ case 4:
++ case 8:
++ var->red.length = var->bits_per_pixel;
++ var->red.offset = 0;
++ var->green.length = var->bits_per_pixel;
++ var->green.offset = 0;
++ var->blue.length = var->bits_per_pixel;
++ var->blue.offset = 0;
++ break;
++ case 16:
++ var->red.length = 5;
++ var->blue.length = 5;
++ /*
++ * Green length can be 5 or 6 depending whether
++ * we're operating in RGB555 or RGB565 mode.
++ */
++ if (var->green.length != 5 && var->green.length != 6)
++ var->green.length = 6;
++ break;
++ case 24:
++ var->red.length = 8;
++ var->blue.length = 8;
++ var->green.length = 8;
++ break;
++ case 32:
++ var->red.length = 8;
++ var->green.length = 8;
++ var->blue.length = 8;
++ var->transp.length = 8;
++ break;
++ default:
++ ret = -EINVAL;
++ break;
++ }
++
++ /*
++ * >= 16bpp displays have separate colour component bitfields
++ * encoded in the pixel data. Calculate their position from
++ * the bitfield length defined above.
++ */
++ if (ret == 0 && var->bits_per_pixel >= 24 && fbswap) {
++ var->blue.offset = 0;
++ var->green.offset = var->blue.offset + var->blue.length;
++ var->red.offset = var->green.offset + var->green.length;
++ var->transp.offset = var->red.offset + var->red.length;
++ } else if (ret == 0 && var->bits_per_pixel >= 24) {
++ var->red.offset = 0;
++ var->green.offset = var->red.offset + var->red.length;
++ var->blue.offset = var->green.offset + var->green.length;
++ var->transp.offset = var->blue.offset + var->blue.length;
++ } else if (ret == 0 && var->bits_per_pixel >= 16) {
++ var->blue.offset = 0;
++ var->green.offset = var->blue.offset + var->blue.length;
++ var->red.offset = var->green.offset + var->green.length;
++ var->transp.offset = var->red.offset + var->red.length;
++ }
++
++ return ret;
++}
++
++static int bcm2708_fb_check_var(struct fb_var_screeninfo *var,
++ struct fb_info *info)
++{
++ /* info input, var output */
++ int yres;
++
++ /* info input, var output */
++ print_debug("bcm2708_fb_check_var info(%p) %dx%d (%dx%d), %d, %d\n", info,
++ info->var.xres, info->var.yres, info->var.xres_virtual,
++ info->var.yres_virtual, (int)info->screen_size,
++ info->var.bits_per_pixel);
++ print_debug("bcm2708_fb_check_var var(%p) %dx%d (%dx%d), %d\n", var,
++ var->xres, var->yres, var->xres_virtual, var->yres_virtual,
++ var->bits_per_pixel);
++
++ if (!var->bits_per_pixel)
++ var->bits_per_pixel = 16;
++
++ if (bcm2708_fb_set_bitfields(var) != 0) {
++ pr_err("bcm2708_fb_check_var: invalid bits_per_pixel %d\n",
++ var->bits_per_pixel);
++ return -EINVAL;
++ }
++
++
++ if (var->xres_virtual < var->xres)
++ var->xres_virtual = var->xres;
++ /* use highest possible virtual resolution */
++ if (var->yres_virtual == -1) {
++ var->yres_virtual = 480;
++
++ pr_err
++ ("bcm2708_fb_check_var: virtual resolution set to maximum of %dx%d\n",
++ var->xres_virtual, var->yres_virtual);
++ }
++ if (var->yres_virtual < var->yres)
++ var->yres_virtual = var->yres;
++
++ if (var->xoffset < 0)
++ var->xoffset = 0;
++ if (var->yoffset < 0)
++ var->yoffset = 0;
++
++ /* truncate xoffset and yoffset to maximum if too high */
++ if (var->xoffset > var->xres_virtual - var->xres)
++ var->xoffset = var->xres_virtual - var->xres - 1;
++ if (var->yoffset > var->yres_virtual - var->yres)
++ var->yoffset = var->yres_virtual - var->yres - 1;
++
++ yres = var->yres;
++ if (var->vmode & FB_VMODE_DOUBLE)
++ yres *= 2;
++ else if (var->vmode & FB_VMODE_INTERLACED)
++ yres = (yres + 1) / 2;
++
++ return 0;
++}
++
++static int bcm2708_fb_set_par(struct fb_info *info)
++{
++ struct bcm2708_fb *fb = to_bcm2708(info);
++ struct fb_alloc_tags fbinfo = {
++ .tag1 = { RPI_FIRMWARE_FRAMEBUFFER_SET_PHYSICAL_WIDTH_HEIGHT,
++ 8, 0, },
++ .xres = info->var.xres,
++ .yres = info->var.yres,
++ .tag2 = { RPI_FIRMWARE_FRAMEBUFFER_SET_VIRTUAL_WIDTH_HEIGHT,
++ 8, 0, },
++ .xres_virtual = info->var.xres_virtual,
++ .yres_virtual = info->var.yres_virtual,
++ .tag3 = { RPI_FIRMWARE_FRAMEBUFFER_SET_DEPTH, 4, 0 },
++ .bpp = info->var.bits_per_pixel,
++ .tag4 = { RPI_FIRMWARE_FRAMEBUFFER_SET_VIRTUAL_OFFSET, 8, 0 },
++ .xoffset = info->var.xoffset,
++ .yoffset = info->var.yoffset,
++ .tag5 = { RPI_FIRMWARE_FRAMEBUFFER_ALLOCATE, 8, 0 },
++ .base = 0,
++ .screen_size = 0,
++ .tag6 = { RPI_FIRMWARE_FRAMEBUFFER_GET_PITCH, 4, 0 },
++ .pitch = 0,
++ };
++ int ret;
++
++ print_debug("bcm2708_fb_set_par info(%p) %dx%d (%dx%d), %d, %d\n", info,
++ info->var.xres, info->var.yres, info->var.xres_virtual,
++ info->var.yres_virtual, (int)info->screen_size,
++ info->var.bits_per_pixel);
++
++ ret = rpi_firmware_property_list(fb->fw, &fbinfo, sizeof(fbinfo));
++ if (ret) {
++ dev_err(info->device,
++ "Failed to allocate GPU framebuffer (%d)\n", ret);
++ return ret;
++ }
++
++ if (info->var.bits_per_pixel <= 8)
++ fb->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
++ else
++ fb->fb.fix.visual = FB_VISUAL_TRUECOLOR;
++
++ fb->fb.fix.line_length = fbinfo.pitch;
++ fbinfo.base |= 0x40000000;
++ fb->fb_bus_address = fbinfo.base;
++ fbinfo.base &= ~0xc0000000;
++ fb->fb.fix.smem_start = fbinfo.base;
++ fb->fb.fix.smem_len = fbinfo.pitch * fbinfo.yres_virtual;
++ fb->fb.screen_size = fbinfo.screen_size;
++ if (fb->fb.screen_base)
++ iounmap(fb->fb.screen_base);
++ fb->fb.screen_base = ioremap_wc(fbinfo.base, fb->fb.screen_size);
++ if (!fb->fb.screen_base) {
++ /* the console may currently be locked */
++ console_trylock();
++ console_unlock();
++ dev_err(info->device, "Failed to set screen_base\n");
++ return -ENOMEM;
++ }
++
++ print_debug
++ ("BCM2708FB: start = %p,%p width=%d, height=%d, bpp=%d, pitch=%d size=%d\n",
++ (void *)fb->fb.screen_base, (void *)fb->fb_bus_address,
++ fbinfo.xres, fbinfo.yres, fbinfo.bpp,
++ fbinfo.pitch, (int)fb->fb.screen_size);
++
++ return 0;
++}
++
++static inline u32 convert_bitfield(int val, struct fb_bitfield *bf)
++{
++ unsigned int mask = (1 << bf->length) - 1;
++
++ return (val >> (16 - bf->length) & mask) << bf->offset;
++}
++
++
++static int bcm2708_fb_setcolreg(unsigned int regno, unsigned int red,
++ unsigned int green, unsigned int blue,
++ unsigned int transp, struct fb_info *info)
++{
++ struct bcm2708_fb *fb = to_bcm2708(info);
++
++ /*print_debug("BCM2708FB: setcolreg %d:(%02x,%02x,%02x,%02x) %x\n", regno, red, green, blue, transp, fb->fb.fix.visual);*/
++ if (fb->fb.var.bits_per_pixel <= 8) {
++ if (regno < 256) {
++ /* blue [23:16], green [15:8], red [7:0] */
++ fb->gpu_cmap[regno] = ((red >> 8) & 0xff) << 0 |
++ ((green >> 8) & 0xff) << 8 |
++ ((blue >> 8) & 0xff) << 16;
++ }
++ /* Hack: we need to tell GPU the palette has changed, but currently bcm2708_fb_set_par takes noticable time when called for every (256) colour */
++ /* So just call it for what looks like the last colour in a list for now. */
++ if (regno == 15 || regno == 255) {
++ struct packet {
++ u32 offset;
++ u32 length;
++ u32 cmap[256];
++ } *packet;
++ int ret;
++
++ packet = kmalloc(sizeof(*packet), GFP_KERNEL);
++ if (!packet)
++ return -ENOMEM;
++ packet->offset = 0;
++ packet->length = regno + 1;
++ memcpy(packet->cmap, fb->gpu_cmap, sizeof(packet->cmap));
++ ret = rpi_firmware_property(fb->fw, RPI_FIRMWARE_FRAMEBUFFER_SET_PALETTE,
++ packet, (2 + packet->length) * sizeof(u32));
++ if (ret || packet->offset)
++ dev_err(info->device, "Failed to set palette (%d,%u)\n",
++ ret, packet->offset);
++ kfree(packet);
++ }
++ } else if (regno < 16) {
++ fb->cmap[regno] = convert_bitfield(transp, &fb->fb.var.transp) |
++ convert_bitfield(blue, &fb->fb.var.blue) |
++ convert_bitfield(green, &fb->fb.var.green) |
++ convert_bitfield(red, &fb->fb.var.red);
++ }
++ return regno > 255;
++}
++
++static int bcm2708_fb_blank(int blank_mode, struct fb_info *info)
++{
++ struct bcm2708_fb *fb = to_bcm2708(info);
++ u32 value;
++ int ret;
++
++ switch (blank_mode) {
++ case FB_BLANK_UNBLANK:
++ value = 0;
++ break;
++ case FB_BLANK_NORMAL:
++ case FB_BLANK_VSYNC_SUSPEND:
++ case FB_BLANK_HSYNC_SUSPEND:
++ case FB_BLANK_POWERDOWN:
++ value = 1;
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ ret = rpi_firmware_property(fb->fw, RPI_FIRMWARE_FRAMEBUFFER_BLANK,
++ &value, sizeof(value));
++ if (ret)
++ dev_err(info->device, "bcm2708_fb_blank(%d) failed: %d\n",
++ blank_mode, ret);
++
++ return ret;
++}
++
++static int bcm2708_fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
++{
++ s32 result = -1;
++ info->var.xoffset = var->xoffset;
++ info->var.yoffset = var->yoffset;
++ result = bcm2708_fb_set_par(info);
++ if (result != 0)
++ pr_err("bcm2708_fb_pan_display(%d,%d) returns=%d\n", var->xoffset, var->yoffset, result);
++ return result;
++}
++
++static int bcm2708_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg)
++{
++ struct bcm2708_fb *fb = to_bcm2708(info);
++ u32 dummy = 0;
++ int ret;
++
++ switch (cmd) {
++ case FBIO_WAITFORVSYNC:
++ ret = rpi_firmware_property(fb->fw,
++ RPI_FIRMWARE_FRAMEBUFFER_SET_VSYNC,
++ &dummy, sizeof(dummy));
++ break;
++ default:
++ dev_err(info->device, "Unknown ioctl 0x%x\n", cmd);
++ return -EINVAL;
++ }
++
++ if (ret)
++ dev_err(info->device, "ioctl 0x%x failed (%d)\n", cmd, ret);
++
++ return ret;
++}
++static void bcm2708_fb_fillrect(struct fb_info *info,
++ const struct fb_fillrect *rect)
++{
++ /* (is called) print_debug("bcm2708_fb_fillrect\n"); */
++ cfb_fillrect(info, rect);
++}
++
++/* A helper function for configuring dma control block */
++static void set_dma_cb(struct bcm2708_dma_cb *cb,
++ int burst_size,
++ dma_addr_t dst,
++ int dst_stride,
++ dma_addr_t src,
++ int src_stride,
++ int w,
++ int h)
++{
++ cb->info = BCM2708_DMA_BURST(burst_size) | BCM2708_DMA_S_WIDTH |
++ BCM2708_DMA_S_INC | BCM2708_DMA_D_WIDTH |
++ BCM2708_DMA_D_INC | BCM2708_DMA_TDMODE;
++ cb->dst = dst;
++ cb->src = src;
++ /*
++ * This is not really obvious from the DMA documentation,
++ * but the top 16 bits must be programmmed to "height -1"
++ * and not "height" in 2D mode.
++ */
++ cb->length = ((h - 1) << 16) | w;
++ cb->stride = ((dst_stride - w) << 16) | (u16)(src_stride - w);
++ cb->pad[0] = 0;
++ cb->pad[1] = 0;
++}
++
++static void bcm2708_fb_copyarea(struct fb_info *info,
++ const struct fb_copyarea *region)
++{
++ struct bcm2708_fb *fb = to_bcm2708(info);
++ struct bcm2708_dma_cb *cb = fb->cb_base;
++ int bytes_per_pixel = (info->var.bits_per_pixel + 7) >> 3;
++ /* Channel 0 supports larger bursts and is a bit faster */
++ int burst_size = (fb->dma_chan == 0) ? 8 : 2;
++ int pixels = region->width * region->height;
++
++ /* Fallback to cfb_copyarea() if we don't like something */
++ if (in_atomic() ||
++ bytes_per_pixel > 4 ||
++ info->var.xres * info->var.yres > 1920 * 1200 ||
++ region->width <= 0 || region->width > info->var.xres ||
++ region->height <= 0 || region->height > info->var.yres ||
++ region->sx < 0 || region->sx >= info->var.xres ||
++ region->sy < 0 || region->sy >= info->var.yres ||
++ region->dx < 0 || region->dx >= info->var.xres ||
++ region->dy < 0 || region->dy >= info->var.yres ||
++ region->sx + region->width > info->var.xres ||
++ region->dx + region->width > info->var.xres ||
++ region->sy + region->height > info->var.yres ||
++ region->dy + region->height > info->var.yres) {
++ cfb_copyarea(info, region);
++ return;
++ }
++
++ if (region->dy == region->sy && region->dx > region->sx) {
++ /*
++ * A difficult case of overlapped copy. Because DMA can't
++ * copy individual scanlines in backwards direction, we need
++ * two-pass processing. We do it by programming a chain of dma
++ * control blocks in the first 16K part of the buffer and use
++ * the remaining 48K as the intermediate temporary scratch
++ * buffer. The buffer size is sufficient to handle up to
++ * 1920x1200 resolution at 32bpp pixel depth.
++ */
++ int y;
++ dma_addr_t control_block_pa = fb->cb_handle;
++ dma_addr_t scratchbuf = fb->cb_handle + 16 * 1024;
++ int scanline_size = bytes_per_pixel * region->width;
++ int scanlines_per_cb = (64 * 1024 - 16 * 1024) / scanline_size;
++
++ for (y = 0; y < region->height; y += scanlines_per_cb) {
++ dma_addr_t src =
++ fb->fb_bus_address +
++ bytes_per_pixel * region->sx +
++ (region->sy + y) * fb->fb.fix.line_length;
++ dma_addr_t dst =
++ fb->fb_bus_address +
++ bytes_per_pixel * region->dx +
++ (region->dy + y) * fb->fb.fix.line_length;
++
++ if (region->height - y < scanlines_per_cb)
++ scanlines_per_cb = region->height - y;
++
++ set_dma_cb(cb, burst_size, scratchbuf, scanline_size,
++ src, fb->fb.fix.line_length,
++ scanline_size, scanlines_per_cb);
++ control_block_pa += sizeof(struct bcm2708_dma_cb);
++ cb->next = control_block_pa;
++ cb++;
++
++ set_dma_cb(cb, burst_size, dst, fb->fb.fix.line_length,
++ scratchbuf, scanline_size,
++ scanline_size, scanlines_per_cb);
++ control_block_pa += sizeof(struct bcm2708_dma_cb);
++ cb->next = control_block_pa;
++ cb++;
++ }
++ /* move the pointer back to the last dma control block */
++ cb--;
++ } else {
++ /* A single dma control block is enough. */
++ int sy, dy, stride;
++ if (region->dy <= region->sy) {
++ /* processing from top to bottom */
++ dy = region->dy;
++ sy = region->sy;
++ stride = fb->fb.fix.line_length;
++ } else {
++ /* processing from bottom to top */
++ dy = region->dy + region->height - 1;
++ sy = region->sy + region->height - 1;
++ stride = -fb->fb.fix.line_length;
++ }
++ set_dma_cb(cb, burst_size,
++ fb->fb_bus_address + dy * fb->fb.fix.line_length +
++ bytes_per_pixel * region->dx,
++ stride,
++ fb->fb_bus_address + sy * fb->fb.fix.line_length +
++ bytes_per_pixel * region->sx,
++ stride,
++ region->width * bytes_per_pixel,
++ region->height);
++ }
++
++ /* end of dma control blocks chain */
++ cb->next = 0;
++
++
++ if (pixels < dma_busy_wait_threshold) {
++ bcm_dma_start(fb->dma_chan_base, fb->cb_handle);
++ bcm_dma_wait_idle(fb->dma_chan_base);
++ } else {
++ void __iomem *dma_chan = fb->dma_chan_base;
++ cb->info |= BCM2708_DMA_INT_EN;
++ bcm_dma_start(fb->dma_chan_base, fb->cb_handle);
++ while (bcm_dma_is_busy(dma_chan)) {
++ wait_event_interruptible(
++ fb->dma_waitq,
++ !bcm_dma_is_busy(dma_chan));
++ }
++ fb->stats.dma_irqs++;
++ }
++ fb->stats.dma_copies++;
++}
++
++static void bcm2708_fb_imageblit(struct fb_info *info,
++ const struct fb_image *image)
++{
++ /* (is called) print_debug("bcm2708_fb_imageblit\n"); */
++ cfb_imageblit(info, image);
++}
++
++static irqreturn_t bcm2708_fb_dma_irq(int irq, void *cxt)
++{
++ struct bcm2708_fb *fb = cxt;
++
++ /* FIXME: should read status register to check if this is
++ * actually interrupting us or not, in case this interrupt
++ * ever becomes shared amongst several DMA channels
++ *
++ * readl(dma_chan_base + BCM2708_DMA_CS) & BCM2708_DMA_IRQ;
++ */
++
++ /* acknowledge the interrupt */
++ writel(BCM2708_DMA_INT, fb->dma_chan_base + BCM2708_DMA_CS);
++
++ wake_up(&fb->dma_waitq);
++ return IRQ_HANDLED;
++}
++
++static struct fb_ops bcm2708_fb_ops = {
++ .owner = THIS_MODULE,
++ .fb_check_var = bcm2708_fb_check_var,
++ .fb_set_par = bcm2708_fb_set_par,
++ .fb_setcolreg = bcm2708_fb_setcolreg,
++ .fb_blank = bcm2708_fb_blank,
++ .fb_fillrect = bcm2708_fb_fillrect,
++ .fb_copyarea = bcm2708_fb_copyarea,
++ .fb_imageblit = bcm2708_fb_imageblit,
++ .fb_pan_display = bcm2708_fb_pan_display,
++ .fb_ioctl = bcm2708_ioctl,
++};
++
++static int bcm2708_fb_register(struct bcm2708_fb *fb)
++{
++ int ret;
++
++ fb->fb.fbops = &bcm2708_fb_ops;
++ fb->fb.flags = FBINFO_FLAG_DEFAULT | FBINFO_HWACCEL_COPYAREA;
++ fb->fb.pseudo_palette = fb->cmap;
++
++ strncpy(fb->fb.fix.id, bcm2708_name, sizeof(fb->fb.fix.id));
++ fb->fb.fix.type = FB_TYPE_PACKED_PIXELS;
++ fb->fb.fix.type_aux = 0;
++ fb->fb.fix.xpanstep = 1;
++ fb->fb.fix.ypanstep = 1;
++ fb->fb.fix.ywrapstep = 0;
++ fb->fb.fix.accel = FB_ACCEL_NONE;
++
++ fb->fb.var.xres = fbwidth;
++ fb->fb.var.yres = fbheight;
++ fb->fb.var.xres_virtual = fbwidth;
++ fb->fb.var.yres_virtual = fbheight;
++ fb->fb.var.bits_per_pixel = fbdepth;
++ fb->fb.var.vmode = FB_VMODE_NONINTERLACED;
++ fb->fb.var.activate = FB_ACTIVATE_NOW;
++ fb->fb.var.nonstd = 0;
++ fb->fb.var.height = -1; /* height of picture in mm */
++ fb->fb.var.width = -1; /* width of picture in mm */
++ fb->fb.var.accel_flags = 0;
++
++ fb->fb.monspecs.hfmin = 0;
++ fb->fb.monspecs.hfmax = 100000;
++ fb->fb.monspecs.vfmin = 0;
++ fb->fb.monspecs.vfmax = 400;
++ fb->fb.monspecs.dclkmin = 1000000;
++ fb->fb.monspecs.dclkmax = 100000000;
++
++ bcm2708_fb_set_bitfields(&fb->fb.var);
++ init_waitqueue_head(&fb->dma_waitq);
++
++ /*
++ * Allocate colourmap.
++ */
++
++ fb_set_var(&fb->fb, &fb->fb.var);
++ ret = bcm2708_fb_set_par(&fb->fb);
++ if (ret)
++ return ret;
++
++ print_debug("BCM2708FB: registering framebuffer (%dx%d@%d) (%d)\n", fbwidth,
++ fbheight, fbdepth, fbswap);
++
++ ret = register_framebuffer(&fb->fb);
++ print_debug("BCM2708FB: register framebuffer (%d)\n", ret);
++ if (ret == 0)
++ goto out;
++
++ print_debug("BCM2708FB: cannot register framebuffer (%d)\n", ret);
++out:
++ return ret;
++}
++
++static int bcm2708_fb_probe(struct platform_device *dev)
++{
++ struct device_node *fw_np;
++ struct rpi_firmware *fw;
++ struct bcm2708_fb *fb;
++ int ret;
++
++ fw_np = of_parse_phandle(dev->dev.of_node, "firmware", 0);
++/* Remove comment when booting without Device Tree is no longer supported
++ if (!fw_np) {
++ dev_err(&dev->dev, "Missing firmware node\n");
++ return -ENOENT;
++ }
++*/
++ fw = rpi_firmware_get(fw_np);
++ if (!fw)
++ return -EPROBE_DEFER;
++
++ fb = kzalloc(sizeof(struct bcm2708_fb), GFP_KERNEL);
++ if (!fb) {
++ dev_err(&dev->dev,
++ "could not allocate new bcm2708_fb struct\n");
++ ret = -ENOMEM;
++ goto free_region;
++ }
++
++ fb->fw = fw;
++ bcm2708_fb_debugfs_init(fb);
++
++ fb->cb_base = dma_alloc_writecombine(&dev->dev, SZ_64K,
++ &fb->cb_handle, GFP_KERNEL);
++ if (!fb->cb_base) {
++ dev_err(&dev->dev, "cannot allocate DMA CBs\n");
++ ret = -ENOMEM;
++ goto free_fb;
++ }
++
++ pr_info("BCM2708FB: allocated DMA memory %08x\n",
++ fb->cb_handle);
++
++ ret = bcm_dma_chan_alloc(BCM_DMA_FEATURE_BULK,
++ &fb->dma_chan_base, &fb->dma_irq);
++ if (ret < 0) {
++ dev_err(&dev->dev, "couldn't allocate a DMA channel\n");
++ goto free_cb;
++ }
++ fb->dma_chan = ret;
++
++ ret = request_irq(fb->dma_irq, bcm2708_fb_dma_irq,
++ 0, "bcm2708_fb dma", fb);
++ if (ret) {
++ pr_err("%s: failed to request DMA irq\n", __func__);
++ goto free_dma_chan;
++ }
++
++
++ pr_info("BCM2708FB: allocated DMA channel %d @ %p\n",
++ fb->dma_chan, fb->dma_chan_base);
++
++ fb->dev = dev;
++ fb->fb.device = &dev->dev;
++
++ ret = bcm2708_fb_register(fb);
++ if (ret == 0) {
++ platform_set_drvdata(dev, fb);
++ goto out;
++ }
++
++free_dma_chan:
++ bcm_dma_chan_free(fb->dma_chan);
++free_cb:
++ dma_free_writecombine(&dev->dev, SZ_64K, fb->cb_base, fb->cb_handle);
++free_fb:
++ kfree(fb);
++free_region:
++ dev_err(&dev->dev, "probe failed, err %d\n", ret);
++out:
++ return ret;
++}
++
++static int bcm2708_fb_remove(struct platform_device *dev)
++{
++ struct bcm2708_fb *fb = platform_get_drvdata(dev);
++
++ platform_set_drvdata(dev, NULL);
++
++ if (fb->fb.screen_base)
++ iounmap(fb->fb.screen_base);
++ unregister_framebuffer(&fb->fb);
++
++ dma_free_writecombine(&dev->dev, SZ_64K, fb->cb_base, fb->cb_handle);
++ bcm_dma_chan_free(fb->dma_chan);
++
++ bcm2708_fb_debugfs_deinit(fb);
++
++ free_irq(fb->dma_irq, fb);
++
++ kfree(fb);
++
++ return 0;
++}
++
++static const struct of_device_id bcm2708_fb_of_match_table[] = {
++ { .compatible = "brcm,bcm2708-fb", },
++ {},
++};
++MODULE_DEVICE_TABLE(of, bcm2708_fb_of_match_table);
++
++static struct platform_driver bcm2708_fb_driver = {
++ .probe = bcm2708_fb_probe,
++ .remove = bcm2708_fb_remove,
++ .driver = {
++ .name = DRIVER_NAME,
++ .owner = THIS_MODULE,
++ .of_match_table = bcm2708_fb_of_match_table,
++ },
++};
++
++static int __init bcm2708_fb_init(void)
++{
++ return platform_driver_register(&bcm2708_fb_driver);
++}
++
++module_init(bcm2708_fb_init);
++
++static void __exit bcm2708_fb_exit(void)
++{
++ platform_driver_unregister(&bcm2708_fb_driver);
++}
++
++module_exit(bcm2708_fb_exit);
++
++module_param(fbwidth, int, 0644);
++module_param(fbheight, int, 0644);
++module_param(fbdepth, int, 0644);
++module_param(fbswap, int, 0644);
++
++MODULE_DESCRIPTION("BCM2708 framebuffer driver");
++MODULE_LICENSE("GPL");
++
++MODULE_PARM_DESC(fbwidth, "Width of ARM Framebuffer");
++MODULE_PARM_DESC(fbheight, "Height of ARM Framebuffer");
++MODULE_PARM_DESC(fbdepth, "Bit depth of ARM Framebuffer");
++MODULE_PARM_DESC(fbswap, "Swap order of red and blue in 24 and 32 bit modes");
+diff -Nur linux-4.1.3/drivers/video/fbdev/core/cfbimgblt.c linux-xbian-rpi/drivers/video/fbdev/core/cfbimgblt.c
+--- linux-4.1.3/drivers/video/fbdev/core/cfbimgblt.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/video/fbdev/core/cfbimgblt.c 2015-07-28 01:20:58.453128032 +0200
+@@ -28,6 +28,11 @@
+ *
+ * Also need to add code to deal with cards endians that are different than
+ * the native cpu endians. I also need to deal with MSB position in the word.
++ * Modified by Harm Hanemaaijer (fgenfb@yahoo.com) 2013:
++ * - Provide optimized versions of fast_imageblit for 16 and 32bpp that are
++ * significantly faster than the previous implementation.
++ * - Simplify the fast/slow_imageblit selection code, avoiding integer
++ * divides.
+ */
+ #include <linux/module.h>
+ #include <linux/string.h>
+@@ -262,6 +267,133 @@
+ }
+ }
+
++/*
++ * Optimized fast_imageblit for bpp == 16. ppw = 2, bit_mask = 3 folded
++ * into the code, main loop unrolled.
++ */
++
++static inline void fast_imageblit16(const struct fb_image *image,
++ struct fb_info *p, u8 __iomem * dst1,
++ u32 fgcolor, u32 bgcolor)
++{
++ u32 fgx = fgcolor, bgx = bgcolor;
++ u32 spitch = (image->width + 7) / 8;
++ u32 end_mask, eorx;
++ const char *s = image->data, *src;
++ u32 __iomem *dst;
++ const u32 *tab = NULL;
++ int i, j, k;
++
++ tab = fb_be_math(p) ? cfb_tab16_be : cfb_tab16_le;
++
++ fgx <<= 16;
++ bgx <<= 16;
++ fgx |= fgcolor;
++ bgx |= bgcolor;
++
++ eorx = fgx ^ bgx;
++ k = image->width / 2;
++
++ for (i = image->height; i--;) {
++ dst = (u32 __iomem *) dst1;
++ src = s;
++
++ j = k;
++ while (j >= 4) {
++ u8 bits = *src;
++ end_mask = tab[(bits >> 6) & 3];
++ FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
++ end_mask = tab[(bits >> 4) & 3];
++ FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
++ end_mask = tab[(bits >> 2) & 3];
++ FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
++ end_mask = tab[bits & 3];
++ FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
++ src++;
++ j -= 4;
++ }
++ if (j != 0) {
++ u8 bits = *src;
++ end_mask = tab[(bits >> 6) & 3];
++ FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
++ if (j >= 2) {
++ end_mask = tab[(bits >> 4) & 3];
++ FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
++ if (j == 3) {
++ end_mask = tab[(bits >> 2) & 3];
++ FB_WRITEL((end_mask & eorx) ^ bgx, dst);
++ }
++ }
++ }
++ dst1 += p->fix.line_length;
++ s += spitch;
++ }
++}
++
++/*
++ * Optimized fast_imageblit for bpp == 32. ppw = 1, bit_mask = 1 folded
++ * into the code, main loop unrolled.
++ */
++
++static inline void fast_imageblit32(const struct fb_image *image,
++ struct fb_info *p, u8 __iomem * dst1,
++ u32 fgcolor, u32 bgcolor)
++{
++ u32 fgx = fgcolor, bgx = bgcolor;
++ u32 spitch = (image->width + 7) / 8;
++ u32 end_mask, eorx;
++ const char *s = image->data, *src;
++ u32 __iomem *dst;
++ const u32 *tab = NULL;
++ int i, j, k;
++
++ tab = cfb_tab32;
++
++ eorx = fgx ^ bgx;
++ k = image->width;
++
++ for (i = image->height; i--;) {
++ dst = (u32 __iomem *) dst1;
++ src = s;
++
++ j = k;
++ while (j >= 8) {
++ u8 bits = *src;
++ end_mask = tab[(bits >> 7) & 1];
++ FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
++ end_mask = tab[(bits >> 6) & 1];
++ FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
++ end_mask = tab[(bits >> 5) & 1];
++ FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
++ end_mask = tab[(bits >> 4) & 1];
++ FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
++ end_mask = tab[(bits >> 3) & 1];
++ FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
++ end_mask = tab[(bits >> 2) & 1];
++ FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
++ end_mask = tab[(bits >> 1) & 1];
++ FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
++ end_mask = tab[bits & 1];
++ FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
++ src++;
++ j -= 8;
++ }
++ if (j != 0) {
++ u32 bits = (u32) * src;
++ while (j > 1) {
++ end_mask = tab[(bits >> 7) & 1];
++ FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
++ bits <<= 1;
++ j--;
++ }
++ end_mask = tab[(bits >> 7) & 1];
++ FB_WRITEL((end_mask & eorx) ^ bgx, dst);
++ }
++ dst1 += p->fix.line_length;
++ s += spitch;
++ }
++}
++
+ void cfb_imageblit(struct fb_info *p, const struct fb_image *image)
+ {
+ u32 fgcolor, bgcolor, start_index, bitstart, pitch_index = 0;
+@@ -294,11 +426,21 @@
+ bgcolor = image->bg_color;
+ }
+
+- if (32 % bpp == 0 && !start_index && !pitch_index &&
+- ((width & (32/bpp-1)) == 0) &&
+- bpp >= 8 && bpp <= 32)
+- fast_imageblit(image, p, dst1, fgcolor, bgcolor);
+- else
++ if (!start_index && !pitch_index) {
++ if (bpp == 32)
++ fast_imageblit32(image, p, dst1, fgcolor,
++ bgcolor);
++ else if (bpp == 16 && (width & 1) == 0)
++ fast_imageblit16(image, p, dst1, fgcolor,
++ bgcolor);
++ else if (bpp == 8 && (width & 3) == 0)
++ fast_imageblit(image, p, dst1, fgcolor,
++ bgcolor);
++ else
++ slow_imageblit(image, p, dst1, fgcolor,
++ bgcolor,
++ start_index, pitch_index);
++ } else
+ slow_imageblit(image, p, dst1, fgcolor, bgcolor,
+ start_index, pitch_index);
+ } else
+diff -Nur linux-4.1.3/drivers/video/fbdev/core/fbmem.c linux-xbian-rpi/drivers/video/fbdev/core/fbmem.c
+--- linux-4.1.3/drivers/video/fbdev/core/fbmem.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/video/fbdev/core/fbmem.c 2015-07-28 01:20:58.453128032 +0200
+@@ -1084,6 +1084,25 @@
+ }
+ EXPORT_SYMBOL(fb_blank);
+
++static int fb_copyarea_user(struct fb_info *info,
++ struct fb_copyarea *copy)
++{
++ int ret = 0;
++ if (!lock_fb_info(info))
++ return -ENODEV;
++ if (copy->dx + copy->width > info->var.xres ||
++ copy->sx + copy->width > info->var.xres ||
++ copy->dy + copy->height > info->var.yres ||
++ copy->sy + copy->height > info->var.yres) {
++ ret = -EINVAL;
++ goto out;
++ }
++ info->fbops->fb_copyarea(info, copy);
++out:
++ unlock_fb_info(info);
++ return ret;
++}
++
+ static long do_fb_ioctl(struct fb_info *info, unsigned int cmd,
+ unsigned long arg)
+ {
+@@ -1094,6 +1113,7 @@
+ struct fb_cmap cmap_from;
+ struct fb_cmap_user cmap;
+ struct fb_event event;
++ struct fb_copyarea copy;
+ void __user *argp = (void __user *)arg;
+ long ret = 0;
+
+@@ -1211,6 +1231,15 @@
+ unlock_fb_info(info);
+ console_unlock();
+ break;
++ case FBIOCOPYAREA:
++ if (info->flags & FBINFO_HWACCEL_COPYAREA) {
++ /* only provide this ioctl if it is accelerated */
++ if (copy_from_user(&copy, argp, sizeof(copy)))
++ return -EFAULT;
++ ret = fb_copyarea_user(info, &copy);
++ break;
++ }
++ /* fall through */
+ default:
+ if (!lock_fb_info(info))
+ return -ENODEV;
+@@ -1365,6 +1394,7 @@
+ case FBIOPAN_DISPLAY:
+ case FBIOGET_CON2FBMAP:
+ case FBIOPUT_CON2FBMAP:
++ case FBIOCOPYAREA:
+ arg = (unsigned long) compat_ptr(arg);
+ case FBIOBLANK:
+ ret = do_fb_ioctl(info, cmd, arg);
+diff -Nur linux-4.1.3/drivers/video/fbdev/Kconfig linux-xbian-rpi/drivers/video/fbdev/Kconfig
+--- linux-4.1.3/drivers/video/fbdev/Kconfig 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/video/fbdev/Kconfig 2015-07-28 01:20:58.453128032 +0200
+@@ -224,6 +224,20 @@
+ comment "Frame buffer hardware drivers"
+ depends on FB
+
++config FB_BCM2708
++ tristate "BCM2708 framebuffer support"
++ depends on FB && ARM && BCM2708_MBOX
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ help
++ This framebuffer device driver is for the BCM2708 framebuffer.
++
++ If you want to compile this as a module (=code which can be
++ inserted into and removed from the running kernel), say M
++ here and read <file:Documentation/kbuild/modules.txt>. The module
++ will be called bcm2708_fb.
++
+ config FB_GRVGA
+ tristate "Aeroflex Gaisler framebuffer support"
+ depends on FB && SPARC
+@@ -2481,3 +2495,16 @@
+ help
+ This driver implements support for the Solomon SSD1307
+ OLED controller over I2C.
++
++config FB_RPISENSE
++ tristate "Raspberry Pi Sense HAT framebuffer"
++ depends on FB
++ select MFD_RPISENSE_CORE
++ select FB_SYS_FOPS
++ select FB_SYS_FILLRECT
++ select FB_SYS_COPYAREA
++ select FB_SYS_IMAGEBLIT
++ select FB_DEFERRED_IO
++
++ help
++ This is the framebuffer driver for the Raspberry Pi Sense HAT
+diff -Nur linux-4.1.3/drivers/video/fbdev/Makefile linux-xbian-rpi/drivers/video/fbdev/Makefile
+--- linux-4.1.3/drivers/video/fbdev/Makefile 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/video/fbdev/Makefile 2015-07-28 01:20:58.453128032 +0200
+@@ -12,6 +12,7 @@
+ obj-$(CONFIG_FB_WMT_GE_ROPS) += wmt_ge_rops.o
+
+ # Hardware specific drivers go first
++obj-$(CONFIG_FB_BCM2708) += bcm2708_fb.o
+ obj-$(CONFIG_FB_AMIGA) += amifb.o c2p_planar.o
+ obj-$(CONFIG_FB_ARC) += arcfb.o
+ obj-$(CONFIG_FB_CLPS711X) += clps711x-fb.o
+@@ -149,6 +150,7 @@
+ obj-$(CONFIG_FB_MXS) += mxsfb.o
+ obj-$(CONFIG_FB_SSD1307) += ssd1307fb.o
+ obj-$(CONFIG_FB_SIMPLE) += simplefb.o
++obj-$(CONFIG_FB_RPISENSE) += rpisense-fb.o
+
+ # the test framebuffer is last
+ obj-$(CONFIG_FB_VIRTUAL) += vfb.o
+diff -Nur linux-4.1.3/drivers/video/fbdev/rpisense-fb.c linux-xbian-rpi/drivers/video/fbdev/rpisense-fb.c
+--- linux-4.1.3/drivers/video/fbdev/rpisense-fb.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/video/fbdev/rpisense-fb.c 2015-07-28 01:20:58.453128032 +0200
+@@ -0,0 +1,235 @@
++/*
++ * Raspberry Pi Sense HAT framebuffer driver
++ * http://raspberrypi.org
++ *
++ * Copyright (C) 2015 Raspberry Pi
++ *
++ * Author: Serge Schneider
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ */
++
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/errno.h>
++#include <linux/string.h>
++#include <linux/mm.h>
++#include <linux/slab.h>
++#include <linux/delay.h>
++#include <linux/fb.h>
++#include <linux/init.h>
++
++#include <linux/mfd/rpisense/framebuffer.h>
++#include <linux/mfd/rpisense/core.h>
++
++struct rpisense *rpisense;
++
++struct rpisense_fb_param {
++ char __iomem *vmem;
++ u8 *vmem_work;
++ u32 vmemsize;
++ u8 gamma[32];
++};
++
++static struct rpisense_fb_param rpisense_fb_param = {
++ .vmem = NULL,
++ .vmemsize = 128,
++ .gamma = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01,
++ 0x02, 0x02, 0x03, 0x03, 0x04, 0x05, 0x06, 0x07,
++ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0E, 0x0F, 0x11,
++ 0x12, 0x14, 0x15, 0x17, 0x19, 0x1B, 0x1D, 0x1F,},
++};
++
++static struct fb_deferred_io rpisense_fb_defio;
++
++static struct fb_fix_screeninfo rpisense_fb_fix = {
++ .id = "RPi-Sense FB",
++ .type = FB_TYPE_PACKED_PIXELS,
++ .visual = FB_VISUAL_TRUECOLOR,
++ .xpanstep = 0,
++ .ypanstep = 0,
++ .ywrapstep = 0,
++ .accel = FB_ACCEL_NONE,
++ .line_length = 16,
++};
++
++static struct fb_var_screeninfo rpisense_fb_var = {
++ .xres = 8,
++ .yres = 8,
++ .xres_virtual = 8,
++ .yres_virtual = 8,
++ .bits_per_pixel = 16,
++ .red = {11, 5, 0},
++ .green = {5, 6, 0},
++ .blue = {0, 5, 0},
++};
++
++static ssize_t rpisense_fb_write(struct fb_info *info,
++ const char __user *buf, size_t count,
++ loff_t *ppos)
++{
++ ssize_t res = fb_sys_write(info, buf, count, ppos);
++
++ schedule_delayed_work(&info->deferred_work, rpisense_fb_defio.delay);
++ return res;
++}
++
++static void rpisense_fb_fillrect(struct fb_info *info,
++ const struct fb_fillrect *rect)
++{
++ sys_fillrect(info, rect);
++ schedule_delayed_work(&info->deferred_work, rpisense_fb_defio.delay);
++}
++
++static void rpisense_fb_copyarea(struct fb_info *info,
++ const struct fb_copyarea *area)
++{
++ sys_copyarea(info, area);
++ schedule_delayed_work(&info->deferred_work, rpisense_fb_defio.delay);
++}
++
++static void rpisense_fb_imageblit(struct fb_info *info,
++ const struct fb_image *image)
++{
++ sys_imageblit(info, image);
++ schedule_delayed_work(&info->deferred_work, rpisense_fb_defio.delay);
++}
++
++static void rpisense_fb_deferred_io(struct fb_info *info,
++ struct list_head *pagelist)
++{
++ int i;
++ int j;
++ u8 *vmem_work = rpisense_fb_param.vmem_work;
++ u16 *mem = (u16 *)rpisense_fb_param.vmem;
++ u8 *gamma = rpisense_fb_param.gamma;
++
++ vmem_work[0] = 0;
++ for (j = 0; j < 8; j++) {
++ for (i = 0; i < 8; i++) {
++ vmem_work[(j * 24) + i + 1] =
++ gamma[(mem[(j * 8) + i] >> 11) & 0x1F];
++ vmem_work[(j * 24) + (i + 8) + 1] =
++ gamma[(mem[(j * 8) + i] >> 6) & 0x1F];
++ vmem_work[(j * 24) + (i + 16) + 1] =
++ gamma[(mem[(j * 8) + i]) & 0x1F];
++ }
++ }
++ rpisense_block_write(rpisense, vmem_work, 193);
++}
++
++static struct fb_deferred_io rpisense_fb_defio = {
++ .delay = HZ/100,
++ .deferred_io = rpisense_fb_deferred_io,
++};
++
++static struct fb_ops rpisense_fb_ops = {
++ .owner = THIS_MODULE,
++ .fb_read = fb_sys_read,
++ .fb_write = rpisense_fb_write,
++ .fb_fillrect = rpisense_fb_fillrect,
++ .fb_copyarea = rpisense_fb_copyarea,
++ .fb_imageblit = rpisense_fb_imageblit,
++};
++
++static int rpisense_fb_probe(struct platform_device *pdev)
++{
++ struct fb_info *info;
++ int ret = -ENOMEM;
++ struct rpisense_fb *rpisense_fb;
++
++ rpisense = rpisense_get_dev();
++ rpisense_fb = &rpisense->framebuffer;
++
++ rpisense_fb_param.vmem = vzalloc(rpisense_fb_param.vmemsize);
++ if (!rpisense_fb_param.vmem)
++ return ret;
++
++ rpisense_fb_param.vmem_work = devm_kmalloc(&pdev->dev, 193, GFP_KERNEL);
++ if (!rpisense_fb_param.vmem_work)
++ goto err_malloc;
++
++ info = framebuffer_alloc(0, &pdev->dev);
++ if (!info) {
++ dev_err(&pdev->dev, "Could not allocate framebuffer.\n");
++ goto err_malloc;
++ }
++ rpisense_fb->info = info;
++
++ rpisense_fb_fix.smem_start = (unsigned long)rpisense_fb_param.vmem;
++ rpisense_fb_fix.smem_len = rpisense_fb_param.vmemsize;
++
++ info->fbops = &rpisense_fb_ops;
++ info->fix = rpisense_fb_fix;
++ info->var = rpisense_fb_var;
++ info->fbdefio = &rpisense_fb_defio;
++ info->flags = FBINFO_FLAG_DEFAULT | FBINFO_VIRTFB;
++ info->screen_base = rpisense_fb_param.vmem;
++ info->screen_size = rpisense_fb_param.vmemsize;
++
++ fb_deferred_io_init(info);
++
++ ret = register_framebuffer(info);
++ if (ret < 0) {
++ dev_err(&pdev->dev, "Could not register framebuffer.\n");
++ goto err_fballoc;
++ }
++
++ fb_info(info, "%s frame buffer device\n", info->fix.id);
++ schedule_delayed_work(&info->deferred_work, rpisense_fb_defio.delay);
++ return 0;
++err_fballoc:
++ framebuffer_release(info);
++err_malloc:
++ vfree(rpisense_fb_param.vmem);
++ return ret;
++}
++
++static int rpisense_fb_remove(struct platform_device *pdev)
++{
++ struct rpisense_fb *rpisense_fb = &rpisense->framebuffer;
++ struct fb_info *info = rpisense_fb->info;
++
++ if (info) {
++ unregister_framebuffer(info);
++ fb_deferred_io_cleanup(info);
++ framebuffer_release(info);
++ vfree(rpisense_fb_param.vmem);
++ }
++
++ return 0;
++}
++
++#ifdef CONFIG_OF
++static const struct of_device_id rpisense_fb_id[] = {
++ { .compatible = "rpi,rpi-sense-fb" },
++ { },
++};
++MODULE_DEVICE_TABLE(of, rpisense_fb_id);
++#endif
++
++static struct platform_device_id rpisense_fb_device_id[] = {
++ { .name = "rpi-sense-fb" },
++ { },
++};
++MODULE_DEVICE_TABLE(platform, rpisense_fb_device_id);
++
++static struct platform_driver rpisense_fb_driver = {
++ .probe = rpisense_fb_probe,
++ .remove = rpisense_fb_remove,
++ .driver = {
++ .name = "rpi-sense-fb",
++ .owner = THIS_MODULE,
++ },
++};
++
++module_platform_driver(rpisense_fb_driver);
++
++MODULE_DESCRIPTION("Raspberry Pi Sense HAT framebuffer driver");
++MODULE_AUTHOR("Serge Schneider <serge@raspberrypi.org>");
++MODULE_LICENSE("GPL");
++
+diff -Nur linux-4.1.3/drivers/video/logo/logo_linux_clut224.ppm linux-xbian-rpi/drivers/video/logo/logo_linux_clut224.ppm
+--- linux-4.1.3/drivers/video/logo/logo_linux_clut224.ppm 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/video/logo/logo_linux_clut224.ppm 2015-07-28 01:20:58.453128032 +0200
+@@ -1,1604 +1,883 @@
+ P3
+-# Standard 224-color Linux logo
+-80 80
++63 80
+ 255
+- 0 0 0 0 0 0 0 0 0 0 0 0
+- 0 0 0 0 0 0 0 0 0 0 0 0
+- 0 0 0 0 0 0 0 0 0 0 0 0
+- 0 0 0 0 0 0 0 0 0 0 0 0
+- 0 0 0 0 0 0 0 0 0 0 0 0
+- 0 0 0 0 0 0 0 0 0 0 0 0
+- 0 0 0 0 0 0 0 0 0 0 0 0
+- 0 0 0 0 0 0 0 0 0 0 0 0
+- 0 0 0 0 0 0 0 0 0 0 0 0
+- 6 6 6 6 6 6 10 10 10 10 10 10
+- 10 10 10 6 6 6 6 6 6 6 6 6
+- 0 0 0 0 0 0 0 0 0 0 0 0
+- 0 0 0 0 0 0 0 0 0 0 0 0
+- 0 0 0 0 0 0 0 0 0 0 0 0
+- 0 0 0 0 0 0 0 0 0 0 0 0
+- 0 0 0 0 0 0 0 0 0 0 0 0
+- 0 0 0 0 0 0 0 0 0 0 0 0
+- 0 0 0 0 0 0 0 0 0 0 0 0
+- 0 0 0 0 0 0 0 0 0 0 0 0
+- 0 0 0 0 0 0 0 0 0 0 0 0
+- 0 0 0 0 0 0 0 0 0 0 0 0
+- 0 0 0 0 0 0 0 0 0 0 0 0
+- 0 0 0 0 0 0 0 0 0 0 0 0
+- 0 0 0 0 0 0 0 0 0 0 0 0
+- 0 0 0 0 0 0 0 0 0 0 0 0
+- 0 0 0 0 0 0 0 0 0 0 0 0
+- 0 0 0 0 0 0 0 0 0 0 0 0
+- 0 0 0 0 0 0 0 0 0 0 0 0
+- 0 0 0 6 6 6 10 10 10 14 14 14
+- 22 22 22 26 26 26 30 30 30 34 34 34
+- 30 30 30 30 30 30 26 26 26 18 18 18
+- 14 14 14 10 10 10 6 6 6 0 0 0
+- 0 0 0 0 0 0 0 0 0 0 0 0
+- 0 0 0 0 0 0 0 0 0 0 0 0
+- 0 0 0 0 0 0 0 0 0 0 0 0
+- 0 0 0 0 0 0 0 0 0 0 0 0
+- 0 0 0 0 0 0 0 0 0 0 0 0
+- 0 0 0 0 0 0 0 0 0 0 0 0
+- 0 0 0 0 0 0 0 0 0 0 0 0
+- 0 0 0 0 0 0 0 0 0 0 0 0
+- 0 0 0 0 0 0 0 0 0 0 0 0
+- 0 0 0 0 0 1 0 0 1 0 0 0
+- 0 0 0 0 0 0 0 0 0 0 0 0
+- 0 0 0 0 0 0 0 0 0 0 0 0
+- 0 0 0 0 0 0 0 0 0 0 0 0
+- 0 0 0 0 0 0 0 0 0 0 0 0
+- 0 0 0 0 0 0 0 0 0 0 0 0
+- 0 0 0 0 0 0 0 0 0 0 0 0
+- 6 6 6 14 14 14 26 26 26 42 42 42
+- 54 54 54 66 66 66 78 78 78 78 78 78
+- 78 78 78 74 74 74 66 66 66 54 54 54
+- 42 42 42 26 26 26 18 18 18 10 10 10
+- 6 6 6 0 0 0 0 0 0 0 0 0
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++0 0 0 0 0 0 0 0 0
++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
++0 0 0 0 0 0 0 0 0
+diff -Nur linux-4.1.3/drivers/w1/masters/w1-gpio.c linux-xbian-rpi/drivers/w1/masters/w1-gpio.c
+--- linux-4.1.3/drivers/w1/masters/w1-gpio.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/w1/masters/w1-gpio.c 2015-07-28 01:20:58.453128032 +0200
+@@ -23,6 +23,19 @@
+ #include "../w1.h"
+ #include "../w1_int.h"
+
++static int w1_gpio_pullup = 0;
++static int w1_gpio_pullup_orig = 0;
++module_param_named(pullup, w1_gpio_pullup, int, 0);
++MODULE_PARM_DESC(pullup, "Enable parasitic power (power on data) mode");
++static int w1_gpio_pullup_pin = -1;
++static int w1_gpio_pullup_pin_orig = -1;
++module_param_named(extpullup, w1_gpio_pullup_pin, int, 0);
++MODULE_PARM_DESC(extpullup, "GPIO external pullup pin number");
++static int w1_gpio_pin = -1;
++static int w1_gpio_pin_orig = -1;
++module_param_named(gpiopin, w1_gpio_pin, int, 0);
++MODULE_PARM_DESC(gpiopin, "GPIO pin number");
++
+ static u8 w1_gpio_set_pullup(void *data, int delay)
+ {
+ struct w1_gpio_platform_data *pdata = data;
+@@ -67,6 +80,16 @@
+ return gpio_get_value(pdata->pin) ? 1 : 0;
+ }
+
++static void w1_gpio_bitbang_pullup(void *data, u8 on)
++{
++ struct w1_gpio_platform_data *pdata = data;
++
++ if (on)
++ gpio_direction_output(pdata->pin, 1);
++ else
++ gpio_direction_input(pdata->pin);
++}
++
+ #if defined(CONFIG_OF)
+ static const struct of_device_id w1_gpio_dt_ids[] = {
+ { .compatible = "w1-gpio" },
+@@ -80,6 +103,7 @@
+ struct w1_gpio_platform_data *pdata = dev_get_platdata(&pdev->dev);
+ struct device_node *np = pdev->dev.of_node;
+ int gpio;
++ u32 value;
+
+ pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
+ if (!pdata)
+@@ -88,6 +112,9 @@
+ if (of_get_property(np, "linux,open-drain", NULL))
+ pdata->is_open_drain = 1;
+
++ if (of_property_read_u32(np, "rpi,parasitic-power", &value) == 0)
++ pdata->parasitic_power = (value != 0);
++
+ gpio = of_get_gpio(np, 0);
+ if (gpio < 0) {
+ if (gpio != -EPROBE_DEFER)
+@@ -103,7 +130,7 @@
+ if (gpio == -EPROBE_DEFER)
+ return gpio;
+ /* ignore other errors as the pullup gpio is optional */
+- pdata->ext_pullup_enable_pin = gpio;
++ pdata->ext_pullup_enable_pin = (gpio >= 0) ? gpio : -1;
+
+ pdev->dev.platform_data = pdata;
+
+@@ -113,13 +140,15 @@
+ static int w1_gpio_probe(struct platform_device *pdev)
+ {
+ struct w1_bus_master *master;
+- struct w1_gpio_platform_data *pdata;
++ struct w1_gpio_platform_data *pdata = pdev->dev.platform_data;
+ int err;
+
+- if (of_have_populated_dt()) {
+- err = w1_gpio_probe_dt(pdev);
+- if (err < 0)
+- return err;
++ if(pdata == NULL) {
++ if (of_have_populated_dt()) {
++ err = w1_gpio_probe_dt(pdev);
++ if (err < 0)
++ return err;
++ }
+ }
+
+ pdata = dev_get_platdata(&pdev->dev);
+@@ -136,6 +165,22 @@
+ return -ENOMEM;
+ }
+
++ w1_gpio_pin_orig = pdata->pin;
++ w1_gpio_pullup_pin_orig = pdata->ext_pullup_enable_pin;
++ w1_gpio_pullup_orig = pdata->parasitic_power;
++
++ if(gpio_is_valid(w1_gpio_pin)) {
++ pdata->pin = w1_gpio_pin;
++ pdata->ext_pullup_enable_pin = -1;
++ pdata->parasitic_power = -1;
++ }
++ pdata->parasitic_power |= w1_gpio_pullup;
++ if(gpio_is_valid(w1_gpio_pullup_pin)) {
++ pdata->ext_pullup_enable_pin = w1_gpio_pullup_pin;
++ }
++
++ dev_info(&pdev->dev, "gpio pin %d, external pullup pin %d, parasitic power %d\n", pdata->pin, pdata->ext_pullup_enable_pin, pdata->parasitic_power);
++
+ err = devm_gpio_request(&pdev->dev, pdata->pin, "w1");
+ if (err) {
+ dev_err(&pdev->dev, "gpio_request (pin) failed\n");
+@@ -165,6 +210,14 @@
+ master->set_pullup = w1_gpio_set_pullup;
+ }
+
++ if (pdata->parasitic_power) {
++ if (pdata->is_open_drain)
++ printk(KERN_ERR "w1-gpio 'pullup'(parasitic power) "
++ "option doesn't work with open drain GPIO\n");
++ else
++ master->bitbang_pullup = w1_gpio_bitbang_pullup;
++ }
++
+ err = w1_add_master_device(master);
+ if (err) {
+ dev_err(&pdev->dev, "w1_add_master device failed\n");
+@@ -195,6 +248,10 @@
+
+ w1_remove_master_device(master);
+
++ pdata->pin = w1_gpio_pin_orig;
++ pdata->ext_pullup_enable_pin = w1_gpio_pullup_pin_orig;
++ pdata->parasitic_power = w1_gpio_pullup_orig;
++
+ return 0;
+ }
+
+diff -Nur linux-4.1.3/drivers/w1/slaves/w1_therm.c linux-xbian-rpi/drivers/w1/slaves/w1_therm.c
+--- linux-4.1.3/drivers/w1/slaves/w1_therm.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/w1/slaves/w1_therm.c 2015-07-28 01:20:58.453128032 +0200
+@@ -59,16 +59,32 @@
+ static int w1_strong_pullup = 1;
+ module_param_named(strong_pullup, w1_strong_pullup, int, 0);
+
++struct w1_therm_family_data {
++ uint8_t rom[9];
++ atomic_t refcnt;
++};
++
++/* return the address of the refcnt in the family data */
++#define THERM_REFCNT(family_data) \
++ (&((struct w1_therm_family_data*)family_data)->refcnt)
++
+ static int w1_therm_add_slave(struct w1_slave *sl)
+ {
+- sl->family_data = kzalloc(9, GFP_KERNEL);
++ sl->family_data = kzalloc(sizeof(struct w1_therm_family_data),
++ GFP_KERNEL);
+ if (!sl->family_data)
+ return -ENOMEM;
++ atomic_set(THERM_REFCNT(sl->family_data), 1);
+ return 0;
+ }
+
+ static void w1_therm_remove_slave(struct w1_slave *sl)
+ {
++ int refcnt = atomic_sub_return(1, THERM_REFCNT(sl->family_data));
++ while(refcnt) {
++ msleep(1000);
++ refcnt = atomic_read(THERM_REFCNT(sl->family_data));
++ }
+ kfree(sl->family_data);
+ sl->family_data = NULL;
+ }
+@@ -76,13 +92,24 @@
+ static ssize_t w1_slave_show(struct device *device,
+ struct device_attribute *attr, char *buf);
+
++static ssize_t w1_seq_show(struct device *device,
++ struct device_attribute *attr, char *buf);
++
+ static DEVICE_ATTR_RO(w1_slave);
++static DEVICE_ATTR_RO(w1_seq);
+
+ static struct attribute *w1_therm_attrs[] = {
+ &dev_attr_w1_slave.attr,
+ NULL,
+ };
++
++static struct attribute *w1_ds28ea00_attrs[] = {
++ &dev_attr_w1_slave.attr,
++ &dev_attr_w1_seq.attr,
++ NULL,
++};
+ ATTRIBUTE_GROUPS(w1_therm);
++ATTRIBUTE_GROUPS(w1_ds28ea00);
+
+ static struct w1_family_ops w1_therm_fops = {
+ .add_slave = w1_therm_add_slave,
+@@ -90,6 +117,12 @@
+ .groups = w1_therm_groups,
+ };
+
++static struct w1_family_ops w1_ds28ea00_fops = {
++ .add_slave = w1_therm_add_slave,
++ .remove_slave = w1_therm_remove_slave,
++ .groups = w1_ds28ea00_groups,
++};
++
+ static struct w1_family w1_therm_family_DS18S20 = {
+ .fid = W1_THERM_DS18S20,
+ .fops = &w1_therm_fops,
+@@ -107,7 +140,7 @@
+
+ static struct w1_family w1_therm_family_DS28EA00 = {
+ .fid = W1_THERM_DS28EA00,
+- .fops = &w1_therm_fops,
++ .fops = &w1_ds28ea00_fops,
+ };
+
+ static struct w1_family w1_therm_family_DS1825 = {
+@@ -194,13 +227,22 @@
+ struct w1_slave *sl = dev_to_w1_slave(device);
+ struct w1_master *dev = sl->master;
+ u8 rom[9], crc, verdict, external_power;
+- int i, max_trying = 10;
++ int i, ret, max_trying = 10;
+ ssize_t c = PAGE_SIZE;
++ u8 *family_data = sl->family_data;
+
+- i = mutex_lock_interruptible(&dev->bus_mutex);
+- if (i != 0)
+- return i;
++ ret = mutex_lock_interruptible(&dev->bus_mutex);
++ if (ret != 0)
++ goto post_unlock;
++
++ if(!sl->family_data)
++ {
++ ret = -ENODEV;
++ goto pre_unlock;
++ }
+
++ /* prevent the slave from going away in sleep */
++ atomic_inc(THERM_REFCNT(family_data));
+ memset(rom, 0, sizeof(rom));
+
+ while (max_trying--) {
+@@ -230,17 +272,19 @@
+ mutex_unlock(&dev->bus_mutex);
+
+ sleep_rem = msleep_interruptible(tm);
+- if (sleep_rem != 0)
+- return -EINTR;
++ if (sleep_rem != 0) {
++ ret = -EINTR;
++ goto post_unlock;
++ }
+
+- i = mutex_lock_interruptible(&dev->bus_mutex);
+- if (i != 0)
+- return i;
++ ret = mutex_lock_interruptible(&dev->bus_mutex);
++ if (ret != 0)
++ goto post_unlock;
+ } else if (!w1_strong_pullup) {
+ sleep_rem = msleep_interruptible(tm);
+ if (sleep_rem != 0) {
+- mutex_unlock(&dev->bus_mutex);
+- return -EINTR;
++ ret = -EINTR;
++ goto pre_unlock;
+ }
+ }
+
+@@ -269,19 +313,107 @@
+ c -= snprintf(buf + PAGE_SIZE - c, c, ": crc=%02x %s\n",
+ crc, (verdict) ? "YES" : "NO");
+ if (verdict)
+- memcpy(sl->family_data, rom, sizeof(rom));
++ memcpy(family_data, rom, sizeof(rom));
+ else
+ dev_warn(device, "Read failed CRC check\n");
+
+ for (i = 0; i < 9; ++i)
+ c -= snprintf(buf + PAGE_SIZE - c, c, "%02x ",
+- ((u8 *)sl->family_data)[i]);
++ ((u8 *)family_data)[i]);
+
+ c -= snprintf(buf + PAGE_SIZE - c, c, "t=%d\n",
+ w1_convert_temp(rom, sl->family->fid));
++ ret = PAGE_SIZE - c;
++
++pre_unlock:
+ mutex_unlock(&dev->bus_mutex);
+
++post_unlock:
++ atomic_dec(THERM_REFCNT(family_data));
++ return ret;
++}
++
++#define W1_42_CHAIN 0x99
++#define W1_42_CHAIN_OFF 0x3C
++#define W1_42_CHAIN_OFF_INV 0xC3
++#define W1_42_CHAIN_ON 0x5A
++#define W1_42_CHAIN_ON_INV 0xA5
++#define W1_42_CHAIN_DONE 0x96
++#define W1_42_CHAIN_DONE_INV 0x69
++#define W1_42_COND_READ 0x0F
++#define W1_42_SUCCESS_CONFIRM_BYTE 0xAA
++#define W1_42_FINISHED_BYTE 0xFF
++static ssize_t w1_seq_show(struct device *device,
++ struct device_attribute *attr, char *buf)
++{
++ struct w1_slave *sl = dev_to_w1_slave(device);
++ ssize_t c = PAGE_SIZE;
++ int rv;
++ int i;
++ u8 ack;
++ u64 rn;
++ struct w1_reg_num *reg_num;
++ int seq = 0;
++
++ mutex_lock(&sl->master->bus_mutex);
++ /* Place all devices in CHAIN state */
++ if (w1_reset_bus(sl->master))
++ goto error;
++ w1_write_8(sl->master, W1_SKIP_ROM);
++ w1_write_8(sl->master, W1_42_CHAIN);
++ w1_write_8(sl->master, W1_42_CHAIN_ON);
++ w1_write_8(sl->master, W1_42_CHAIN_ON_INV);
++ msleep(sl->master->pullup_duration);
++
++ /* check for acknowledgment */
++ ack = w1_read_8(sl->master);
++ if (ack != W1_42_SUCCESS_CONFIRM_BYTE)
++ goto error;
++
++ /* In case the bus fails to send 0xFF, limit*/
++ for (i = 0; i <= 64; i++) {
++ if (w1_reset_bus(sl->master))
++ goto error;
++
++ w1_write_8(sl->master, W1_42_COND_READ);
++ rv = w1_read_block(sl->master, (u8 *)&rn, 8);
++ reg_num = (struct w1_reg_num *) &rn;
++ if (reg_num->family == W1_42_FINISHED_BYTE)
++ break;
++ if (sl->reg_num.id == reg_num->id)
++ seq = i;
++
++ w1_write_8(sl->master, W1_42_CHAIN);
++ w1_write_8(sl->master, W1_42_CHAIN_DONE);
++ w1_write_8(sl->master, W1_42_CHAIN_DONE_INV);
++ w1_read_block(sl->master, &ack, sizeof(ack));
++
++ /* check for acknowledgment */
++ ack = w1_read_8(sl->master);
++ if (ack != W1_42_SUCCESS_CONFIRM_BYTE)
++ goto error;
++
++ }
++
++ /* Exit from CHAIN state */
++ if (w1_reset_bus(sl->master))
++ goto error;
++ w1_write_8(sl->master, W1_SKIP_ROM);
++ w1_write_8(sl->master, W1_42_CHAIN);
++ w1_write_8(sl->master, W1_42_CHAIN_OFF);
++ w1_write_8(sl->master, W1_42_CHAIN_OFF_INV);
++
++ /* check for acknowledgment */
++ ack = w1_read_8(sl->master);
++ if (ack != W1_42_SUCCESS_CONFIRM_BYTE)
++ goto error;
++ mutex_unlock(&sl->master->bus_mutex);
++
++ c -= snprintf(buf + PAGE_SIZE - c, c, "%d\n", seq);
+ return PAGE_SIZE - c;
++error:
++ mutex_unlock(&sl->master->bus_mutex);
++ return -EIO;
+ }
+
+ static int __init w1_therm_init(void)
+diff -Nur linux-4.1.3/drivers/w1/w1.h linux-xbian-rpi/drivers/w1/w1.h
+--- linux-4.1.3/drivers/w1/w1.h 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/w1/w1.h 2015-07-28 01:20:58.453128032 +0200
+@@ -171,6 +171,12 @@
+
+ u8 (*set_pullup)(void *, int);
+
++ /**
++ * Turns the pullup on/off in bitbanging mode, takes an on/off argument.
++ * @return -1=Error, 0=completed
++ */
++ void (*bitbang_pullup) (void *, u8);
++
+ void (*search)(void *, struct w1_master *,
+ u8, w1_slave_found_callback);
+ };
+diff -Nur linux-4.1.3/drivers/w1/w1_int.c linux-xbian-rpi/drivers/w1/w1_int.c
+--- linux-4.1.3/drivers/w1/w1_int.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/w1/w1_int.c 2015-07-28 01:20:58.453128032 +0200
+@@ -123,6 +123,20 @@
+ return(-EINVAL);
+ }
+
++ /* bitbanging hardware uses bitbang_pullup, other hardware uses set_pullup
++ * and takes care of timing itself */
++ if (!master->write_byte && !master->touch_bit && master->set_pullup) {
++ printk(KERN_ERR "w1_add_master_device: set_pullup requires "
++ "write_byte or touch_bit, disabling\n");
++ master->set_pullup = NULL;
++ }
++
++ if (master->set_pullup && master->bitbang_pullup) {
++ printk(KERN_ERR "w1_add_master_device: set_pullup should not "
++ "be set when bitbang_pullup is used, disabling\n");
++ master->set_pullup = NULL;
++ }
++
+ /* Lock until the device is added (or not) to w1_masters. */
+ mutex_lock(&w1_mlock);
+ /* Search for the first available id (starting at 1). */
+diff -Nur linux-4.1.3/drivers/w1/w1_io.c linux-xbian-rpi/drivers/w1/w1_io.c
+--- linux-4.1.3/drivers/w1/w1_io.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/w1/w1_io.c 2015-07-28 01:20:58.453128032 +0200
+@@ -134,10 +134,22 @@
+ static void w1_post_write(struct w1_master *dev)
+ {
+ if (dev->pullup_duration) {
+- if (dev->enable_pullup && dev->bus_master->set_pullup)
+- dev->bus_master->set_pullup(dev->bus_master->data, 0);
+- else
++ if (dev->enable_pullup) {
++ if (dev->bus_master->set_pullup) {
++ dev->bus_master->set_pullup(dev->
++ bus_master->data,
++ 0);
++ } else if (dev->bus_master->bitbang_pullup) {
++ dev->bus_master->
++ bitbang_pullup(dev->bus_master->data, 1);
+ msleep(dev->pullup_duration);
++ dev->bus_master->
++ bitbang_pullup(dev->bus_master->data, 0);
++ }
++ } else {
++ msleep(dev->pullup_duration);
++ }
++
+ dev->pullup_duration = 0;
+ }
+ }
+diff -Nur linux-4.1.3/drivers/watchdog/bcm2708_wdog.c linux-xbian-rpi/drivers/watchdog/bcm2708_wdog.c
+--- linux-4.1.3/drivers/watchdog/bcm2708_wdog.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/drivers/watchdog/bcm2708_wdog.c 2015-07-28 01:20:58.453128032 +0200
+@@ -0,0 +1,382 @@
++/*
++ * Broadcom BCM2708 watchdog driver.
++ *
++ * (c) Copyright 2010 Broadcom Europe Ltd
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version
++ * 2 of the License, or (at your option) any later version.
++ *
++ * BCM2708 watchdog driver. Loosely based on wdt driver.
++ */
++
++#include <linux/interrupt.h>
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/types.h>
++#include <linux/miscdevice.h>
++#include <linux/watchdog.h>
++#include <linux/fs.h>
++#include <linux/ioport.h>
++#include <linux/notifier.h>
++#include <linux/reboot.h>
++#include <linux/init.h>
++#include <linux/io.h>
++#include <linux/uaccess.h>
++#include <mach/platform.h>
++
++#define SECS_TO_WDOG_TICKS(x) ((x) << 16)
++#define WDOG_TICKS_TO_SECS(x) ((x) >> 16)
++
++static unsigned long wdog_is_open;
++static uint32_t wdog_ticks; /* Ticks to load into wdog timer */
++static char expect_close;
++
++/*
++ * Module parameters
++ */
++
++#define WD_TIMO 10 /* Default heartbeat = 60 seconds */
++static int heartbeat = WD_TIMO; /* Heartbeat in seconds */
++
++module_param(heartbeat, int, 0);
++MODULE_PARM_DESC(heartbeat,
++ "Watchdog heartbeat in seconds. (0 < heartbeat < 65536, default="
++ __MODULE_STRING(WD_TIMO) ")");
++
++static int nowayout = WATCHDOG_NOWAYOUT;
++module_param(nowayout, int, 0);
++MODULE_PARM_DESC(nowayout,
++ "Watchdog cannot be stopped once started (default="
++ __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
++
++static DEFINE_SPINLOCK(wdog_lock);
++
++/**
++ * Start the watchdog driver.
++ */
++
++static int wdog_start(unsigned long timeout)
++{
++ uint32_t cur;
++ unsigned long flags;
++ spin_lock_irqsave(&wdog_lock, flags);
++
++ /* enable the watchdog */
++ iowrite32(PM_PASSWORD | (timeout & PM_WDOG_TIME_SET),
++ __io_address(PM_WDOG));
++ cur = ioread32(__io_address(PM_RSTC));
++ iowrite32(PM_PASSWORD | (cur & PM_RSTC_WRCFG_CLR) |
++ PM_RSTC_WRCFG_FULL_RESET, __io_address(PM_RSTC));
++
++ spin_unlock_irqrestore(&wdog_lock, flags);
++ return 0;
++}
++
++/**
++ * Stop the watchdog driver.
++ */
++
++static int wdog_stop(void)
++{
++ iowrite32(PM_PASSWORD | PM_RSTC_RESET, __io_address(PM_RSTC));
++ printk(KERN_INFO "watchdog stopped\n");
++ return 0;
++}
++
++/**
++ * Reload counter one with the watchdog heartbeat. We don't bother
++ * reloading the cascade counter.
++ */
++
++static void wdog_ping(void)
++{
++ wdog_start(wdog_ticks);
++}
++
++/**
++ * @t: the new heartbeat value that needs to be set.
++ *
++ * Set a new heartbeat value for the watchdog device. If the heartbeat
++ * value is incorrect we keep the old value and return -EINVAL. If
++ * successful we return 0.
++ */
++
++static int wdog_set_heartbeat(int t)
++{
++ if (t < 1 || t > WDOG_TICKS_TO_SECS(PM_WDOG_TIME_SET))
++ return -EINVAL;
++
++ heartbeat = t;
++ wdog_ticks = SECS_TO_WDOG_TICKS(t);
++ return 0;
++}
++
++/**
++ * @file: file handle to the watchdog
++ * @buf: buffer to write (unused as data does not matter here
++ * @count: count of bytes
++ * @ppos: pointer to the position to write. No seeks allowed
++ *
++ * A write to a watchdog device is defined as a keepalive signal.
++ *
++ * if 'nowayout' is set then normally a close() is ignored. But
++ * if you write 'V' first then the close() will stop the timer.
++ */
++
++static ssize_t wdog_write(struct file *file, const char __user *buf,
++ size_t count, loff_t *ppos)
++{
++ if (count) {
++ if (!nowayout) {
++ size_t i;
++
++ /* In case it was set long ago */
++ expect_close = 0;
++
++ for (i = 0; i != count; i++) {
++ char c;
++ if (get_user(c, buf + i))
++ return -EFAULT;
++ if (c == 'V')
++ expect_close = 42;
++ }
++ }
++ wdog_ping();
++ }
++ return count;
++}
++
++static int wdog_get_status(void)
++{
++ unsigned long flags;
++ int status = 0;
++ spin_lock_irqsave(&wdog_lock, flags);
++ /* FIXME: readback reset reason */
++ spin_unlock_irqrestore(&wdog_lock, flags);
++ return status;
++}
++
++static uint32_t wdog_get_remaining(void)
++{
++ uint32_t ret = ioread32(__io_address(PM_WDOG));
++ return ret & PM_WDOG_TIME_SET;
++}
++
++/**
++ * @file: file handle to the device
++ * @cmd: watchdog command
++ * @arg: argument pointer
++ *
++ * The watchdog API defines a common set of functions for all watchdogs
++ * according to their available features. We only actually usefully support
++ * querying capabilities and current status.
++ */
++
++static long wdog_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
++{
++ void __user *argp = (void __user *)arg;
++ int __user *p = argp;
++ int new_heartbeat;
++ int status;
++ int options;
++ uint32_t remaining;
++
++ struct watchdog_info ident = {
++ .options = WDIOF_SETTIMEOUT|
++ WDIOF_MAGICCLOSE|
++ WDIOF_KEEPALIVEPING,
++ .firmware_version = 1,
++ .identity = "BCM2708",
++ };
++
++ switch (cmd) {
++ case WDIOC_GETSUPPORT:
++ return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0;
++ case WDIOC_GETSTATUS:
++ status = wdog_get_status();
++ return put_user(status, p);
++ case WDIOC_GETBOOTSTATUS:
++ return put_user(0, p);
++ case WDIOC_KEEPALIVE:
++ wdog_ping();
++ return 0;
++ case WDIOC_SETTIMEOUT:
++ if (get_user(new_heartbeat, p))
++ return -EFAULT;
++ if (wdog_set_heartbeat(new_heartbeat))
++ return -EINVAL;
++ wdog_ping();
++ /* Fall */
++ case WDIOC_GETTIMEOUT:
++ return put_user(heartbeat, p);
++ case WDIOC_GETTIMELEFT:
++ remaining = WDOG_TICKS_TO_SECS(wdog_get_remaining());
++ return put_user(remaining, p);
++ case WDIOC_SETOPTIONS:
++ if (get_user(options, p))
++ return -EFAULT;
++ if (options & WDIOS_DISABLECARD)
++ wdog_stop();
++ if (options & WDIOS_ENABLECARD)
++ wdog_start(wdog_ticks);
++ return 0;
++ default:
++ return -ENOTTY;
++ }
++}
++
++/**
++ * @inode: inode of device
++ * @file: file handle to device
++ *
++ * The watchdog device has been opened. The watchdog device is single
++ * open and on opening we load the counters.
++ */
++
++static int wdog_open(struct inode *inode, struct file *file)
++{
++ if (test_and_set_bit(0, &wdog_is_open))
++ return -EBUSY;
++ /*
++ * Activate
++ */
++ wdog_start(wdog_ticks);
++ return nonseekable_open(inode, file);
++}
++
++/**
++ * @inode: inode to board
++ * @file: file handle to board
++ *
++ * The watchdog has a configurable API. There is a religious dispute
++ * between people who want their watchdog to be able to shut down and
++ * those who want to be sure if the watchdog manager dies the machine
++ * reboots. In the former case we disable the counters, in the latter
++ * case you have to open it again very soon.
++ */
++
++static int wdog_release(struct inode *inode, struct file *file)
++{
++ if (expect_close == 42) {
++ wdog_stop();
++ } else {
++ printk(KERN_CRIT
++ "wdt: WDT device closed unexpectedly. WDT will not stop!\n");
++ wdog_ping();
++ }
++ clear_bit(0, &wdog_is_open);
++ expect_close = 0;
++ return 0;
++}
++
++/**
++ * @this: our notifier block
++ * @code: the event being reported
++ * @unused: unused
++ *
++ * Our notifier is called on system shutdowns. Turn the watchdog
++ * off so that it does not fire during the next reboot.
++ */
++
++static int wdog_notify_sys(struct notifier_block *this, unsigned long code,
++ void *unused)
++{
++ if (code == SYS_DOWN || code == SYS_HALT)
++ wdog_stop();
++ return NOTIFY_DONE;
++}
++
++/*
++ * Kernel Interfaces
++ */
++
++
++static const struct file_operations wdog_fops = {
++ .owner = THIS_MODULE,
++ .llseek = no_llseek,
++ .write = wdog_write,
++ .unlocked_ioctl = wdog_ioctl,
++ .open = wdog_open,
++ .release = wdog_release,
++};
++
++static struct miscdevice wdog_miscdev = {
++ .minor = WATCHDOG_MINOR,
++ .name = "watchdog",
++ .fops = &wdog_fops,
++};
++
++/*
++ * The WDT card needs to learn about soft shutdowns in order to
++ * turn the timebomb registers off.
++ */
++
++static struct notifier_block wdog_notifier = {
++ .notifier_call = wdog_notify_sys,
++};
++
++/**
++ * cleanup_module:
++ *
++ * Unload the watchdog. You cannot do this with any file handles open.
++ * If your watchdog is set to continue ticking on close and you unload
++ * it, well it keeps ticking. We won't get the interrupt but the board
++ * will not touch PC memory so all is fine. You just have to load a new
++ * module in 60 seconds or reboot.
++ */
++
++static void __exit wdog_exit(void)
++{
++ misc_deregister(&wdog_miscdev);
++ unregister_reboot_notifier(&wdog_notifier);
++}
++
++static int __init wdog_init(void)
++{
++ int ret;
++
++ /* Check that the heartbeat value is within it's range;
++ if not reset to the default */
++ if (wdog_set_heartbeat(heartbeat)) {
++ wdog_set_heartbeat(WD_TIMO);
++ printk(KERN_INFO "bcm2708_wdog: heartbeat value must be "
++ "0 < heartbeat < %d, using %d\n",
++ WDOG_TICKS_TO_SECS(PM_WDOG_TIME_SET),
++ WD_TIMO);
++ }
++
++ ret = register_reboot_notifier(&wdog_notifier);
++ if (ret) {
++ printk(KERN_ERR
++ "wdt: cannot register reboot notifier (err=%d)\n", ret);
++ goto out_reboot;
++ }
++
++ ret = misc_register(&wdog_miscdev);
++ if (ret) {
++ printk(KERN_ERR
++ "wdt: cannot register miscdev on minor=%d (err=%d)\n",
++ WATCHDOG_MINOR, ret);
++ goto out_misc;
++ }
++
++ printk(KERN_INFO "bcm2708 watchdog, heartbeat=%d sec (nowayout=%d)\n",
++ heartbeat, nowayout);
++ return 0;
++
++out_misc:
++ unregister_reboot_notifier(&wdog_notifier);
++out_reboot:
++ return ret;
++}
++
++module_init(wdog_init);
++module_exit(wdog_exit);
++
++MODULE_AUTHOR("Luke Diamand");
++MODULE_DESCRIPTION("Driver for BCM2708 watchdog");
++MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
++MODULE_ALIAS_MISCDEV(TEMP_MINOR);
++MODULE_LICENSE("GPL");
+diff -Nur linux-4.1.3/drivers/watchdog/Kconfig linux-xbian-rpi/drivers/watchdog/Kconfig
+--- linux-4.1.3/drivers/watchdog/Kconfig 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/watchdog/Kconfig 2015-07-28 01:20:58.453128032 +0200
+@@ -451,6 +451,12 @@
+ To compile this driver as a module, choose M here: the
+ module will be called retu_wdt.
+
++config BCM2708_WDT
++ tristate "BCM2708 Watchdog"
++ depends on ARCH_BCM2708 || ARCH_BCM2709
++ help
++ Enables BCM2708 watchdog support.
++
+ config MOXART_WDT
+ tristate "MOXART watchdog"
+ depends on ARCH_MOXART
+@@ -1216,7 +1222,7 @@
+
+ config BCM2835_WDT
+ tristate "Broadcom BCM2835 hardware watchdog"
+- depends on ARCH_BCM2835
++ depends on ARCH_BCM2835 || ARCH_BCM2708 || ARCH_BCM2709
+ select WATCHDOG_CORE
+ help
+ Watchdog driver for the built in watchdog hardware in Broadcom
+diff -Nur linux-4.1.3/drivers/watchdog/Makefile linux-xbian-rpi/drivers/watchdog/Makefile
+--- linux-4.1.3/drivers/watchdog/Makefile 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/drivers/watchdog/Makefile 2015-07-28 01:20:58.453128032 +0200
+@@ -56,6 +56,7 @@
+ obj-$(CONFIG_IMX2_WDT) += imx2_wdt.o
+ obj-$(CONFIG_UX500_WATCHDOG) += ux500_wdt.o
+ obj-$(CONFIG_RETU_WATCHDOG) += retu_wdt.o
++obj-$(CONFIG_BCM2708_WDT) += bcm2708_wdog.o
+ obj-$(CONFIG_BCM2835_WDT) += bcm2835_wdt.o
+ obj-$(CONFIG_MOXART_WDT) += moxart_wdt.o
+ obj-$(CONFIG_SIRFSOC_WATCHDOG) += sirfsoc_wdt.o
+diff -Nur linux-4.1.3/fs/btrfs/compression.c linux-xbian-rpi/fs/btrfs/compression.c
+--- linux-4.1.3/fs/btrfs/compression.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/fs/btrfs/compression.c 2015-07-27 23:13:08.905209516 +0200
+@@ -753,6 +753,8 @@
+ static const struct btrfs_compress_op * const btrfs_compress_op[] = {
+ &btrfs_zlib_compress,
+ &btrfs_lzo_compress,
++ &btrfs_lz4_compress,
++ &btrfs_lz4hc_compress,
+ };
+
+ void __init btrfs_init_compress(void)
+diff -Nur linux-4.1.3/fs/btrfs/compression.h linux-xbian-rpi/fs/btrfs/compression.h
+--- linux-4.1.3/fs/btrfs/compression.h 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/fs/btrfs/compression.h 2015-07-27 23:13:08.905209516 +0200
+@@ -79,5 +79,7 @@
+
+ extern const struct btrfs_compress_op btrfs_zlib_compress;
+ extern const struct btrfs_compress_op btrfs_lzo_compress;
++extern const struct btrfs_compress_op btrfs_lz4_compress;
++extern const struct btrfs_compress_op btrfs_lz4hc_compress;
+
+ #endif
+diff -Nur linux-4.1.3/fs/btrfs/ctree.h linux-xbian-rpi/fs/btrfs/ctree.h
+--- linux-4.1.3/fs/btrfs/ctree.h 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/fs/btrfs/ctree.h 2015-07-27 23:13:08.909195295 +0200
+@@ -504,13 +504,7 @@
+ #define BTRFS_FEATURE_INCOMPAT_DEFAULT_SUBVOL (1ULL << 1)
+ #define BTRFS_FEATURE_INCOMPAT_MIXED_GROUPS (1ULL << 2)
+ #define BTRFS_FEATURE_INCOMPAT_COMPRESS_LZO (1ULL << 3)
+-/*
+- * some patches floated around with a second compression method
+- * lets save that incompat here for when they do get in
+- * Note we don't actually support it, we're just reserving the
+- * number
+- */
+-#define BTRFS_FEATURE_INCOMPAT_COMPRESS_LZOv2 (1ULL << 4)
++#define BTRFS_FEATURE_INCOMPAT_COMPRESS_LZ4 (1ULL << 4)
+
+ /*
+ * older kernels tried to do bigger metadata blocks, but the
+@@ -539,6 +533,7 @@
+ BTRFS_FEATURE_INCOMPAT_RAID56 | \
+ BTRFS_FEATURE_INCOMPAT_EXTENDED_IREF | \
+ BTRFS_FEATURE_INCOMPAT_SKINNY_METADATA | \
++ BTRFS_FEATURE_INCOMPAT_COMPRESS_LZ4 | \
+ BTRFS_FEATURE_INCOMPAT_NO_HOLES)
+
+ #define BTRFS_FEATURE_INCOMPAT_SAFE_SET \
+@@ -709,8 +704,10 @@
+ BTRFS_COMPRESS_NONE = 0,
+ BTRFS_COMPRESS_ZLIB = 1,
+ BTRFS_COMPRESS_LZO = 2,
+- BTRFS_COMPRESS_TYPES = 2,
+- BTRFS_COMPRESS_LAST = 3,
++ BTRFS_COMPRESS_LZ4 = 3,
++ BTRFS_COMPRESS_LZ4HC = 4,
++ BTRFS_COMPRESS_TYPES = 4,
++ BTRFS_COMPRESS_LAST = 5,
+ };
+
+ struct btrfs_inode_item {
+diff -Nur linux-4.1.3/fs/btrfs/disk-io.c linux-xbian-rpi/fs/btrfs/disk-io.c
+--- linux-4.1.3/fs/btrfs/disk-io.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/fs/btrfs/disk-io.c 2015-07-27 23:13:08.909195295 +0200
+@@ -2703,6 +2703,10 @@
+ if (tree_root->fs_info->compress_type == BTRFS_COMPRESS_LZO)
+ features |= BTRFS_FEATURE_INCOMPAT_COMPRESS_LZO;
+
++ if (tree_root->fs_info->compress_type == BTRFS_COMPRESS_LZ4 ||
++ tree_root->fs_info->compress_type == BTRFS_COMPRESS_LZ4HC)
++ features |= BTRFS_FEATURE_INCOMPAT_COMPRESS_LZ4;
++
+ if (features & BTRFS_FEATURE_INCOMPAT_SKINNY_METADATA)
+ printk(KERN_INFO "BTRFS: has skinny extents\n");
+
+diff -Nur linux-4.1.3/fs/btrfs/ioctl.c linux-xbian-rpi/fs/btrfs/ioctl.c
+--- linux-4.1.3/fs/btrfs/ioctl.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/fs/btrfs/ioctl.c 2015-07-27 23:13:08.921152633 +0200
+@@ -1439,6 +1439,10 @@
+ if (range->compress_type == BTRFS_COMPRESS_LZO) {
+ btrfs_set_fs_incompat(root->fs_info, COMPRESS_LZO);
+ }
++ if (range->compress_type == BTRFS_COMPRESS_LZ4 ||
++ range->compress_type == BTRFS_COMPRESS_LZ4HC) {
++ btrfs_set_fs_incompat(root->fs_info, COMPRESS_LZ4);
++ }
+
+ ret = defrag_count;
+
+diff -Nur linux-4.1.3/fs/btrfs/lz4_wrapper.c linux-xbian-rpi/fs/btrfs/lz4_wrapper.c
+--- linux-4.1.3/fs/btrfs/lz4_wrapper.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/fs/btrfs/lz4_wrapper.c 2015-07-27 23:13:08.921152633 +0200
+@@ -0,0 +1,487 @@
++/*
++ * Copyright (C) 2008 Oracle. All rights reserved.
++ * Copyright (C) 2013 SUSE. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public
++ * License v2 as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
++ * General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public
++ * License along with this program; if not, write to the
++ * Free Software Foundation, Inc., 59 Temple Place - Suite 330,
++ * Boston, MA 021110-1307, USA.
++ */
++
++#include <linux/kernel.h>
++#include <linux/slab.h>
++#include <linux/vmalloc.h>
++#include <linux/init.h>
++#include <linux/err.h>
++#include <linux/sched.h>
++#include <linux/pagemap.h>
++#include <linux/bio.h>
++#include <linux/lz4.h>
++#include "compression.h"
++
++#define LZ4_LEN 4
++#define LZ4_CHUNK_SIZE (4096)
++#define LZ4_MAX_WORKBUF 2*LZ4_CHUNK_SIZE
++
++struct workspace {
++ void *mem; /* work memory for compression */
++ void *buf; /* where compressed data goes */
++ void *cbuf; /* where decompressed data goes */
++ struct list_head list;
++};
++
++static void lz4_free_workspace(struct list_head *ws)
++{
++ struct workspace *workspace = list_entry(ws, struct workspace, list);
++
++ vfree(workspace->buf);
++ vfree(workspace->cbuf);
++ vfree(workspace->mem);
++ kfree(workspace);
++}
++
++static struct list_head *lz4_alloc_workspace_generic(int hi)
++{
++ struct workspace *workspace;
++
++ workspace = kzalloc(sizeof(*workspace), GFP_NOFS);
++ if (!workspace)
++ return ERR_PTR(-ENOMEM);
++
++ if (hi)
++ workspace->mem = vmalloc(LZ4HC_MEM_COMPRESS);
++ else
++ workspace->mem = vmalloc(LZ4_MEM_COMPRESS);
++ workspace->buf = vmalloc(LZ4_MAX_WORKBUF);
++ workspace->cbuf = vmalloc(LZ4_MAX_WORKBUF);
++ if (!workspace->mem || !workspace->buf || !workspace->cbuf)
++ goto fail;
++
++ INIT_LIST_HEAD(&workspace->list);
++
++ return &workspace->list;
++fail:
++ lz4_free_workspace(&workspace->list);
++ return ERR_PTR(-ENOMEM);
++}
++
++static struct list_head *lz4_alloc_workspace(void)
++{
++ return lz4_alloc_workspace_generic(0);
++}
++
++static struct list_head *lz4hc_alloc_workspace(void)
++{
++ return lz4_alloc_workspace_generic(1);
++}
++
++static inline void write_compress_length(char *buf, size_t len)
++{
++ __le32 dlen;
++
++ dlen = cpu_to_le32(len);
++ memcpy(buf, &dlen, LZ4_LEN);
++}
++
++static inline size_t read_compress_length(char *buf)
++{
++ __le32 dlen;
++
++ memcpy(&dlen, buf, LZ4_LEN);
++ return le32_to_cpu(dlen);
++}
++
++static int lz4_compress_pages_generic(struct list_head *ws,
++ struct address_space *mapping,
++ u64 start, unsigned long len,
++ struct page **pages,
++ unsigned long nr_dest_pages,
++ unsigned long *out_pages,
++ unsigned long *total_in,
++ unsigned long *total_out,
++ unsigned long max_out, int hi)
++{
++ struct workspace *workspace = list_entry(ws, struct workspace, list);
++ int ret = 0;
++ char *data_in;
++ char *cpage_out;
++ int nr_pages = 0;
++ struct page *in_page = NULL;
++ struct page *out_page = NULL;
++ unsigned long bytes_left;
++
++ size_t in_len;
++ size_t out_len;
++ char *buf;
++ unsigned long tot_in = 0;
++ unsigned long tot_out = 0;
++ unsigned long pg_bytes_left;
++ unsigned long out_offset;
++ unsigned long bytes;
++
++ *out_pages = 0;
++ *total_out = 0;
++ *total_in = 0;
++
++ in_page = find_get_page(mapping, start >> PAGE_CACHE_SHIFT);
++ data_in = kmap(in_page);
++
++ /*
++ * store the size of all chunks of compressed data in
++ * the first 4 bytes
++ */
++ out_page = alloc_page(GFP_NOFS | __GFP_HIGHMEM);
++ if (out_page == NULL) {
++ ret = -ENOMEM;
++ goto out;
++ }
++ cpage_out = kmap(out_page);
++ out_offset = LZ4_LEN;
++ tot_out = LZ4_LEN;
++ pages[0] = out_page;
++ nr_pages = 1;
++ pg_bytes_left = PAGE_CACHE_SIZE - LZ4_LEN;
++
++ /* compress at most one page of data each time */
++ in_len = min(len, PAGE_CACHE_SIZE);
++ while (tot_in < len) {
++ if (hi)
++ ret = lz4hc_compress(data_in, in_len, workspace->cbuf,
++ &out_len, workspace->mem);
++ else
++ ret = lz4_compress(data_in, in_len, workspace->cbuf, &out_len,
++ workspace->mem);
++ if (ret < 0) {
++ printk(KERN_DEBUG
++ "btrfs: lz4 compress in loop returned %d\n",
++ ret);
++ ret = -1;
++ goto out;
++ }
++
++ /* store the size of this chunk of compressed data */
++ write_compress_length(cpage_out + out_offset, out_len);
++ tot_out += LZ4_LEN;
++ out_offset += LZ4_LEN;
++ pg_bytes_left -= LZ4_LEN;
++
++ tot_in += in_len;
++ tot_out += out_len;
++
++ /* copy bytes from the working buffer into the pages */
++ buf = workspace->cbuf;
++ while (out_len) {
++ bytes = min_t(unsigned long, pg_bytes_left, out_len);
++
++ memcpy(cpage_out + out_offset, buf, bytes);
++
++ out_len -= bytes;
++ pg_bytes_left -= bytes;
++ buf += bytes;
++ out_offset += bytes;
++
++ /*
++ * we need another page for writing out.
++ *
++ * Note if there's less than 4 bytes left, we just
++ * skip to a new page.
++ */
++ if ((out_len == 0 && pg_bytes_left < LZ4_LEN) ||
++ pg_bytes_left == 0) {
++ if (pg_bytes_left) {
++ memset(cpage_out + out_offset, 0,
++ pg_bytes_left);
++ tot_out += pg_bytes_left;
++ }
++
++ /* we're done, don't allocate new page */
++ if (out_len == 0 && tot_in >= len)
++ break;
++
++ kunmap(out_page);
++ if (nr_pages == nr_dest_pages) {
++ out_page = NULL;
++ ret = -1;
++ goto out;
++ }
++
++ out_page = alloc_page(GFP_NOFS | __GFP_HIGHMEM);
++ if (out_page == NULL) {
++ ret = -ENOMEM;
++ goto out;
++ }
++ cpage_out = kmap(out_page);
++ pages[nr_pages++] = out_page;
++
++ pg_bytes_left = PAGE_CACHE_SIZE;
++ out_offset = 0;
++ }
++ }
++
++ /* we're making it bigger, give up */
++ if (tot_in > 8192 && tot_in < tot_out)
++ goto out;
++
++ /* we're all done */
++ if (tot_in >= len)
++ break;
++
++ if (tot_out > max_out)
++ break;
++
++ bytes_left = len - tot_in;
++ kunmap(in_page);
++ page_cache_release(in_page);
++
++ start += PAGE_CACHE_SIZE;
++ in_page = find_get_page(mapping, start >> PAGE_CACHE_SHIFT);
++ data_in = kmap(in_page);
++ in_len = min(bytes_left, PAGE_CACHE_SIZE);
++ }
++
++ if (tot_out > tot_in)
++ goto out;
++
++ /* store the size of all chunks of compressed data */
++ cpage_out = kmap(pages[0]);
++ write_compress_length(cpage_out, tot_out);
++
++ kunmap(pages[0]);
++
++ ret = 0;
++ *total_out = tot_out;
++ *total_in = tot_in;
++out:
++ *out_pages = nr_pages;
++ if (out_page)
++ kunmap(out_page);
++
++ if (in_page) {
++ kunmap(in_page);
++ page_cache_release(in_page);
++ }
++
++ return ret;
++}
++
++static int lz4_compress_pages(struct list_head *ws,
++ struct address_space *mapping,
++ u64 start, unsigned long len,
++ struct page **pages,
++ unsigned long nr_dest_pages,
++ unsigned long *out_pages,
++ unsigned long *total_in,
++ unsigned long *total_out,
++ unsigned long max_out)
++{
++ return lz4_compress_pages_generic(ws, mapping, start, len, pages,
++ nr_dest_pages, out_pages, total_in, total_out,
++ max_out, 0);
++}
++
++static int lz4hc_compress_pages(struct list_head *ws,
++ struct address_space *mapping,
++ u64 start, unsigned long len,
++ struct page **pages,
++ unsigned long nr_dest_pages,
++ unsigned long *out_pages,
++ unsigned long *total_in,
++ unsigned long *total_out,
++ unsigned long max_out)
++{
++ return lz4_compress_pages_generic(ws, mapping, start, len, pages,
++ nr_dest_pages, out_pages, total_in, total_out,
++ max_out, 1);
++}
++
++static int lz4_decompress_biovec(struct list_head *ws,
++ struct page **pages_in,
++ u64 disk_start,
++ struct bio_vec *bvec,
++ int vcnt,
++ size_t srclen)
++{
++ struct workspace *workspace = list_entry(ws, struct workspace, list);
++ int ret = 0, ret2;
++ char *data_in;
++ unsigned long page_in_index = 0;
++ unsigned long page_out_index = 0;
++ unsigned long total_pages_in = (srclen + PAGE_CACHE_SIZE - 1) /
++ PAGE_CACHE_SIZE;
++ unsigned long buf_start;
++ unsigned long buf_offset = 0;
++ unsigned long bytes;
++ unsigned long working_bytes;
++ unsigned long pg_offset;
++
++ size_t in_len;
++ size_t out_len;
++ unsigned long in_offset;
++ unsigned long in_page_bytes_left;
++ unsigned long tot_in;
++ unsigned long tot_out;
++ unsigned long tot_len;
++ char *buf;
++ bool may_late_unmap, need_unmap;
++
++ data_in = kmap(pages_in[0]);
++ tot_len = read_compress_length(data_in);
++
++ tot_in = LZ4_LEN;
++ in_offset = LZ4_LEN;
++ tot_len = min_t(size_t, srclen, tot_len);
++ in_page_bytes_left = PAGE_CACHE_SIZE - LZ4_LEN;
++
++ tot_out = 0;
++ pg_offset = 0;
++
++ while (tot_in < tot_len) {
++ in_len = read_compress_length(data_in + in_offset);
++ in_page_bytes_left -= LZ4_LEN;
++ in_offset += LZ4_LEN;
++ tot_in += LZ4_LEN;
++
++ tot_in += in_len;
++ working_bytes = in_len;
++ may_late_unmap = need_unmap = false;
++
++ /* fast path: avoid using the working buffer */
++ if (in_page_bytes_left >= in_len) {
++ buf = data_in + in_offset;
++ bytes = in_len;
++ may_late_unmap = true;
++ goto cont;
++ }
++
++ /* copy bytes from the pages into the working buffer */
++ buf = workspace->cbuf;
++ buf_offset = 0;
++ while (working_bytes) {
++ bytes = min(working_bytes, in_page_bytes_left);
++
++ memcpy(buf + buf_offset, data_in + in_offset, bytes);
++ buf_offset += bytes;
++cont:
++ working_bytes -= bytes;
++ in_page_bytes_left -= bytes;
++ in_offset += bytes;
++
++ /* check if we need to pick another page */
++ if ((working_bytes == 0 && in_page_bytes_left < LZ4_LEN)
++ || in_page_bytes_left == 0) {
++ tot_in += in_page_bytes_left;
++
++ if (working_bytes == 0 && tot_in >= tot_len)
++ break;
++
++ if (page_in_index + 1 >= total_pages_in) {
++ ret = -1;
++ goto done;
++ }
++
++ if (may_late_unmap)
++ need_unmap = true;
++ else
++ kunmap(pages_in[page_in_index]);
++
++ data_in = kmap(pages_in[++page_in_index]);
++
++ in_page_bytes_left = PAGE_CACHE_SIZE;
++ in_offset = 0;
++ }
++ }
++
++ out_len = LZ4_CHUNK_SIZE;
++ ret = lz4_decompress_unknownoutputsize(buf, in_len, workspace->buf,
++ &out_len);
++ if (need_unmap)
++ kunmap(pages_in[page_in_index - 1]);
++ if (ret < 0) {
++ printk(KERN_WARNING "btrfs: lz4 decompress failed\n");
++ ret = -1;
++ break;
++ }
++
++ buf_start = tot_out;
++ tot_out += out_len;
++
++ ret2 = btrfs_decompress_buf2page(workspace->buf, buf_start,
++ tot_out, disk_start,
++ bvec, vcnt,
++ &page_out_index, &pg_offset);
++ if (ret2 == 0)
++ break;
++ }
++done:
++ kunmap(pages_in[page_in_index]);
++ return ret;
++}
++
++static int lz4_decompress_wrapper(struct list_head *ws, unsigned char *data_in,
++ struct page *dest_page,
++ unsigned long start_byte,
++ size_t srclen, size_t destlen)
++{
++ struct workspace *workspace = list_entry(ws, struct workspace, list);
++ size_t in_len;
++ size_t out_len;
++ size_t tot_len;
++ int ret = 0;
++ char *kaddr;
++ unsigned long bytes;
++
++ BUG_ON(srclen < LZ4_LEN);
++
++ tot_len = read_compress_length(data_in);
++ data_in += LZ4_LEN;
++
++ in_len = read_compress_length(data_in);
++ data_in += LZ4_LEN;
++
++ out_len = LZ4_CHUNK_SIZE;
++ ret = lz4_decompress_unknownoutputsize(data_in, in_len, workspace->buf,
++ &out_len);
++ if (ret < 0) {
++ printk(KERN_WARNING "btrfs: lz4 decompress failed\n");
++ ret = -1;
++ goto out;
++ }
++
++ if (out_len < start_byte) {
++ ret = -1;
++ goto out;
++ }
++
++ bytes = min_t(unsigned long, destlen, out_len - start_byte);
++
++ kaddr = kmap_atomic(dest_page);
++ memcpy(kaddr, workspace->buf + start_byte, bytes);
++ kunmap_atomic(kaddr);
++out:
++ return ret;
++}
++
++const struct btrfs_compress_op btrfs_lz4_compress = {
++ .alloc_workspace = lz4_alloc_workspace,
++ .free_workspace = lz4_free_workspace,
++ .compress_pages = lz4_compress_pages,
++ .decompress_biovec = lz4_decompress_biovec,
++ .decompress = lz4_decompress_wrapper,
++};
++
++const struct btrfs_compress_op btrfs_lz4hc_compress = {
++ .alloc_workspace = lz4hc_alloc_workspace,
++ .free_workspace = lz4_free_workspace,
++ .compress_pages = lz4hc_compress_pages,
++ .decompress_biovec = lz4_decompress_biovec,
++ .decompress = lz4_decompress_wrapper,
++};
+diff -Nur linux-4.1.3/fs/btrfs/Makefile linux-xbian-rpi/fs/btrfs/Makefile
+--- linux-4.1.3/fs/btrfs/Makefile 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/fs/btrfs/Makefile 2015-07-27 23:13:08.901223737 +0200
+@@ -9,7 +9,7 @@
+ export.o tree-log.o free-space-cache.o zlib.o lzo.o \
+ compression.o delayed-ref.o relocation.o delayed-inode.o scrub.o \
+ reada.o backref.o ulist.o qgroup.o send.o dev-replace.o raid56.o \
+- uuid-tree.o props.o hash.o
++ uuid-tree.o props.o hash.o lz4_wrapper.o
+
+ btrfs-$(CONFIG_BTRFS_FS_POSIX_ACL) += acl.o
+ btrfs-$(CONFIG_BTRFS_FS_CHECK_INTEGRITY) += check-integrity.o
+diff -Nur linux-4.1.3/fs/btrfs/super.c linux-xbian-rpi/fs/btrfs/super.c
+--- linux-4.1.3/fs/btrfs/super.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/fs/btrfs/super.c 2015-07-27 23:13:08.961010425 +0200
+@@ -492,6 +492,20 @@
+ btrfs_clear_opt(info->mount_opt, COMPRESS);
+ btrfs_clear_opt(info->mount_opt, FORCE_COMPRESS);
+ compress_force = false;
++ } else if (strcmp(args[0].from, "lz4") == 0) {
++ compress_type = "lz4";
++ info->compress_type = BTRFS_COMPRESS_LZ4;
++ btrfs_set_opt(info->mount_opt, COMPRESS);
++ btrfs_clear_opt(info->mount_opt, NODATACOW);
++ btrfs_clear_opt(info->mount_opt, NODATASUM);
++ btrfs_set_fs_incompat(info, COMPRESS_LZ4);
++ } else if (strcmp(args[0].from, "lz4hc") == 0) {
++ compress_type = "lz4hc";
++ info->compress_type = BTRFS_COMPRESS_LZ4HC;
++ btrfs_set_opt(info->mount_opt, COMPRESS);
++ btrfs_clear_opt(info->mount_opt, NODATACOW);
++ btrfs_clear_opt(info->mount_opt, NODATASUM);
++ btrfs_set_fs_incompat(info, COMPRESS_LZ4);
+ } else {
+ ret = -EINVAL;
+ goto out;
+@@ -1051,8 +1065,14 @@
+ if (btrfs_test_opt(root, COMPRESS)) {
+ if (info->compress_type == BTRFS_COMPRESS_ZLIB)
+ compress_type = "zlib";
++ else if (info->compress_type == BTRFS_COMPRESS_LZ4)
++ compress_type = "lz4";
++ else if (info->compress_type == BTRFS_COMPRESS_LZ4HC)
++ compress_type = "lz4hc";
++ else if (info->compress_type == BTRFS_COMPRESS_LZO)
++ compress_type = "lzo";
+ else
+- compress_type = "lzo";
++ compress_type = "none";
+ if (btrfs_test_opt(root, FORCE_COMPRESS))
+ seq_printf(seq, ",compress-force=%s", compress_type);
+ else
+diff -Nur linux-4.1.3/fs/btrfs/xattr.c linux-xbian-rpi/fs/btrfs/xattr.c
+--- linux-4.1.3/fs/btrfs/xattr.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/fs/btrfs/xattr.c 2015-07-28 01:20:58.453128032 +0200
+@@ -411,6 +411,7 @@
+ ret = btrfs_is_valid_xattr(name);
+ if (ret)
+ return ret;
++
+ return __btrfs_getxattr(d_inode(dentry), name, buffer, size);
+ }
+
+diff -Nur linux-4.1.3/include/linux/broadcom/vc_cma.h linux-xbian-rpi/include/linux/broadcom/vc_cma.h
+--- linux-4.1.3/include/linux/broadcom/vc_cma.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/include/linux/broadcom/vc_cma.h 2015-07-28 01:20:58.453128032 +0200
+@@ -0,0 +1,29 @@
++/*****************************************************************************
++* Copyright 2012 Broadcom Corporation. All rights reserved.
++*
++* Unless you and Broadcom execute a separate written software license
++* agreement governing use of this software, this software is licensed to you
++* under the terms of the GNU General Public License version 2, available at
++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
++*
++* Notwithstanding the above, under no circumstances may you combine this
++* software in any way with any other Broadcom software provided under a
++* license other than the GPL, without Broadcom's express prior written
++* consent.
++*****************************************************************************/
++
++#if !defined( VC_CMA_H )
++#define VC_CMA_H
++
++#include <linux/ioctl.h>
++
++#define VC_CMA_IOC_MAGIC 0xc5
++
++#define VC_CMA_IOC_RESERVE _IO(VC_CMA_IOC_MAGIC, 0)
++
++#ifdef __KERNEL__
++extern void __init vc_cma_early_init(void);
++extern void __init vc_cma_reserve(void);
++#endif
++
++#endif /* VC_CMA_H */
+diff -Nur linux-4.1.3/include/linux/broadcom/vc_mem.h linux-xbian-rpi/include/linux/broadcom/vc_mem.h
+--- linux-4.1.3/include/linux/broadcom/vc_mem.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/include/linux/broadcom/vc_mem.h 2015-07-28 01:20:58.453128032 +0200
+@@ -0,0 +1,35 @@
++/*****************************************************************************
++* Copyright 2010 - 2011 Broadcom Corporation. All rights reserved.
++*
++* Unless you and Broadcom execute a separate written software license
++* agreement governing use of this software, this software is licensed to you
++* under the terms of the GNU General Public License version 2, available at
++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
++*
++* Notwithstanding the above, under no circumstances may you combine this
++* software in any way with any other Broadcom software provided under a
++* license other than the GPL, without Broadcom's express prior written
++* consent.
++*****************************************************************************/
++
++#ifndef _VC_MEM_H
++#define _VC_MEM_H
++
++#include <linux/ioctl.h>
++
++#define VC_MEM_IOC_MAGIC 'v'
++
++#define VC_MEM_IOC_MEM_PHYS_ADDR _IOR( VC_MEM_IOC_MAGIC, 0, unsigned long )
++#define VC_MEM_IOC_MEM_SIZE _IOR( VC_MEM_IOC_MAGIC, 1, unsigned int )
++#define VC_MEM_IOC_MEM_BASE _IOR( VC_MEM_IOC_MAGIC, 2, unsigned int )
++#define VC_MEM_IOC_MEM_LOAD _IOR( VC_MEM_IOC_MAGIC, 3, unsigned int )
++
++#if defined( __KERNEL__ )
++#define VC_MEM_TO_ARM_ADDR_MASK 0x3FFFFFFF
++
++extern unsigned long mm_vc_mem_phys_addr;
++extern unsigned int mm_vc_mem_size;
++extern int vc_mem_get_current_size( void );
++#endif
++
++#endif /* _VC_MEM_H */
+diff -Nur linux-4.1.3/include/linux/leds.h linux-xbian-rpi/include/linux/leds.h
+--- linux-4.1.3/include/linux/leds.h 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/include/linux/leds.h 2015-07-28 01:20:58.457113811 +0200
+@@ -47,6 +47,9 @@
+ #define SET_BRIGHTNESS_ASYNC (1 << 21)
+ #define SET_BRIGHTNESS_SYNC (1 << 22)
+ #define LED_DEV_CAP_FLASH (1 << 23)
++ /* Additions for Raspberry Pi PWR LED */
++#define SET_GPIO_INPUT (1 << 30)
++#define SET_GPIO_OUTPUT (1 << 31)
+
+ /* Set LED brightness level */
+ /* Must not sleep, use a workqueue if needed */
+diff -Nur linux-4.1.3/include/linux/mfd/rpisense/core.h linux-xbian-rpi/include/linux/mfd/rpisense/core.h
+--- linux-4.1.3/include/linux/mfd/rpisense/core.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/include/linux/mfd/rpisense/core.h 2015-07-28 01:20:58.457113811 +0200
+@@ -0,0 +1,47 @@
++/*
++ * Raspberry Pi Sense HAT core driver
++ * http://raspberrypi.org
++ *
++ * Copyright (C) 2015 Raspberry Pi
++ *
++ * Author: Serge Schneider
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ */
++
++#ifndef __LINUX_MFD_RPISENSE_CORE_H_
++#define __LINUX_MFD_RPISENSE_CORE_H_
++
++#include <linux/mfd/rpisense/joystick.h>
++#include <linux/mfd/rpisense/framebuffer.h>
++
++/*
++ * Register values.
++ */
++#define RPISENSE_FB 0x00
++#define RPISENSE_WAI 0xF0
++#define RPISENSE_VER 0xF1
++#define RPISENSE_KEYS 0xF2
++#define RPISENSE_EE_WP 0xF3
++
++#define RPISENSE_ID 's'
++
++struct rpisense {
++ struct device *dev;
++ struct i2c_client *i2c_client;
++
++ /* Client devices */
++ struct rpisense_js joystick;
++ struct rpisense_fb framebuffer;
++};
++
++struct rpisense *rpisense_get_dev(void);
++s32 rpisense_reg_read(struct rpisense *rpisense, int reg);
++int rpisense_reg_write(struct rpisense *rpisense, int reg, u16 val);
++int rpisense_block_write(struct rpisense *rpisense, const char *buf, int count);
++
++#endif
+diff -Nur linux-4.1.3/include/linux/mfd/rpisense/framebuffer.h linux-xbian-rpi/include/linux/mfd/rpisense/framebuffer.h
+--- linux-4.1.3/include/linux/mfd/rpisense/framebuffer.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/include/linux/mfd/rpisense/framebuffer.h 2015-07-28 01:20:58.457113811 +0200
+@@ -0,0 +1,28 @@
++/*
++ * Raspberry Pi Sense HAT framebuffer driver
++ * http://raspberrypi.org
++ *
++ * Copyright (C) 2015 Raspberry Pi
++ *
++ * Author: Serge Schneider
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ */
++
++#ifndef __LINUX_RPISENSE_FB_H_
++#define __LINUX_RPISENSE_FB_H_
++
++#include <linux/platform_device.h>
++
++struct rpisense;
++
++struct rpisense_fb {
++ struct platform_device *pdev;
++ struct fb_info *info;
++};
++
++#endif
+diff -Nur linux-4.1.3/include/linux/mfd/rpisense/joystick.h linux-xbian-rpi/include/linux/mfd/rpisense/joystick.h
+--- linux-4.1.3/include/linux/mfd/rpisense/joystick.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/include/linux/mfd/rpisense/joystick.h 2015-07-28 01:20:58.457113811 +0200
+@@ -0,0 +1,35 @@
++/*
++ * Raspberry Pi Sense HAT joystick driver
++ * http://raspberrypi.org
++ *
++ * Copyright (C) 2015 Raspberry Pi
++ *
++ * Author: Serge Schneider
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ */
++
++#ifndef __LINUX_RPISENSE_JOYSTICK_H_
++#define __LINUX_RPISENSE_JOYSTICK_H_
++
++#include <linux/input.h>
++#include <linux/interrupt.h>
++#include <linux/gpio/consumer.h>
++#include <linux/platform_device.h>
++
++struct rpisense;
++
++struct rpisense_js {
++ struct platform_device *pdev;
++ struct input_dev *keys_dev;
++ struct gpio_desc *keys_desc;
++ struct work_struct keys_work_s;
++ int keys_irq;
++};
++
++
++#endif
+diff -Nur linux-4.1.3/include/linux/mmc/host.h linux-xbian-rpi/include/linux/mmc/host.h
+--- linux-4.1.3/include/linux/mmc/host.h 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/include/linux/mmc/host.h 2015-07-28 01:20:58.457113811 +0200
+@@ -140,7 +140,9 @@
+ * I/O. Returns the number of supported blocks for the request.
+ */
+ int (*multi_io_quirk)(struct mmc_card *card,
+- unsigned int direction, int blk_size);
++ unsigned int direction,
++ u32 blk_pos,
++ int blk_size);
+ };
+
+ struct mmc_card;
+@@ -285,6 +287,7 @@
+ MMC_CAP2_HS400_1_2V)
+ #define MMC_CAP2_HSX00_1_2V (MMC_CAP2_HS200_1_2V_SDR | MMC_CAP2_HS400_1_2V)
+ #define MMC_CAP2_SDIO_IRQ_NOTHREAD (1 << 17)
++#define MMC_CAP2_FORCE_MULTIBLOCK (1 << 31) /* Always use multiblock transfers */
+
+ mmc_pm_flag_t pm_caps; /* supported pm features */
+
+diff -Nur linux-4.1.3/include/linux/platform_data/bcm2708.h linux-xbian-rpi/include/linux/platform_data/bcm2708.h
+--- linux-4.1.3/include/linux/platform_data/bcm2708.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/include/linux/platform_data/bcm2708.h 2015-07-28 01:20:58.457113811 +0200
+@@ -0,0 +1,23 @@
++/*
++ * include/linux/platform_data/bcm2708.h
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * (C) 2014 Julian Scheel <julian@jusst.de>
++ *
++ */
++#ifndef __BCM2708_H_
++#define __BCM2708_H_
++
++typedef enum {
++ BCM2708_PULL_OFF,
++ BCM2708_PULL_UP,
++ BCM2708_PULL_DOWN
++} bcm2708_gpio_pull_t;
++
++extern int bcm2708_gpio_setpull(struct gpio_chip *gc, unsigned offset,
++ bcm2708_gpio_pull_t value);
++
++#endif
+diff -Nur linux-4.1.3/include/linux/platform_data/dma-bcm2708.h linux-xbian-rpi/include/linux/platform_data/dma-bcm2708.h
+--- linux-4.1.3/include/linux/platform_data/dma-bcm2708.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/include/linux/platform_data/dma-bcm2708.h 2015-07-28 01:20:58.457113811 +0200
+@@ -0,0 +1,127 @@
++/*
++ * Copyright (C) 2010 Broadcom
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef _PLAT_BCM2708_DMA_H
++#define _PLAT_BCM2708_DMA_H
++
++/* DMA CS Control and Status bits */
++#define BCM2708_DMA_ACTIVE BIT(0)
++#define BCM2708_DMA_INT BIT(2)
++#define BCM2708_DMA_ISPAUSED BIT(4) /* Pause requested or not active */
++#define BCM2708_DMA_ISHELD BIT(5) /* Is held by DREQ flow control */
++#define BCM2708_DMA_ERR BIT(8)
++#define BCM2708_DMA_ABORT BIT(30) /* stop current CB, go to next, WO */
++#define BCM2708_DMA_RESET BIT(31) /* WO, self clearing */
++
++/* DMA control block "info" field bits */
++#define BCM2708_DMA_INT_EN BIT(0)
++#define BCM2708_DMA_TDMODE BIT(1)
++#define BCM2708_DMA_WAIT_RESP BIT(3)
++#define BCM2708_DMA_D_INC BIT(4)
++#define BCM2708_DMA_D_WIDTH BIT(5)
++#define BCM2708_DMA_D_DREQ BIT(6)
++#define BCM2708_DMA_S_INC BIT(8)
++#define BCM2708_DMA_S_WIDTH BIT(9)
++#define BCM2708_DMA_S_DREQ BIT(10)
++
++#define BCM2708_DMA_BURST(x) (((x) & 0xf) << 12)
++#define BCM2708_DMA_PER_MAP(x) ((x) << 16)
++#define BCM2708_DMA_WAITS(x) (((x) & 0x1f) << 21)
++
++#define BCM2708_DMA_DREQ_EMMC 11
++#define BCM2708_DMA_DREQ_SDHOST 13
++
++#define BCM2708_DMA_CS 0x00 /* Control and Status */
++#define BCM2708_DMA_ADDR 0x04
++/* the current control block appears in the following registers - read only */
++#define BCM2708_DMA_INFO 0x08
++#define BCM2708_DMA_SOURCE_AD 0x0c
++#define BCM2708_DMA_DEST_AD 0x10
++#define BCM2708_DMA_NEXTCB 0x1C
++#define BCM2708_DMA_DEBUG 0x20
++
++#define BCM2708_DMA4_CS (BCM2708_DMA_CHAN(4) + BCM2708_DMA_CS)
++#define BCM2708_DMA4_ADDR (BCM2708_DMA_CHAN(4) + BCM2708_DMA_ADDR)
++
++#define BCM2708_DMA_TDMODE_LEN(w, h) ((h) << 16 | (w))
++
++/* When listing features we can ask for when allocating DMA channels give
++ those with higher priority smaller ordinal numbers */
++#define BCM_DMA_FEATURE_FAST_ORD 0
++#define BCM_DMA_FEATURE_BULK_ORD 1
++#define BCM_DMA_FEATURE_NORMAL_ORD 2
++#define BCM_DMA_FEATURE_LITE_ORD 3
++#define BCM_DMA_FEATURE_FAST BIT(BCM_DMA_FEATURE_FAST_ORD)
++#define BCM_DMA_FEATURE_BULK BIT(BCM_DMA_FEATURE_BULK_ORD)
++#define BCM_DMA_FEATURE_NORMAL BIT(BCM_DMA_FEATURE_NORMAL_ORD)
++#define BCM_DMA_FEATURE_LITE BIT(BCM_DMA_FEATURE_LITE_ORD)
++#define BCM_DMA_FEATURE_COUNT 4
++
++struct bcm2708_dma_cb {
++ unsigned long info;
++ unsigned long src;
++ unsigned long dst;
++ unsigned long length;
++ unsigned long stride;
++ unsigned long next;
++ unsigned long pad[2];
++};
++
++struct scatterlist;
++
++#ifdef CONFIG_DMA_BCM2708_LEGACY
++
++int bcm_sg_suitable_for_dma(struct scatterlist *sg_ptr, int sg_len);
++void bcm_dma_start(void __iomem *dma_chan_base, dma_addr_t control_block);
++void bcm_dma_wait_idle(void __iomem *dma_chan_base);
++bool bcm_dma_is_busy(void __iomem *dma_chan_base);
++int bcm_dma_abort(void __iomem *dma_chan_base);
++
++/* return channel no or -ve error */
++int bcm_dma_chan_alloc(unsigned preferred_feature_set,
++ void __iomem **out_dma_base, int *out_dma_irq);
++int bcm_dma_chan_free(int channel);
++
++#else /* CONFIG_DMA_BCM2708_LEGACY */
++
++static inline int bcm_sg_suitable_for_dma(struct scatterlist *sg_ptr,
++ int sg_len)
++{
++ return 0;
++}
++
++static inline void bcm_dma_start(void __iomem *dma_chan_base,
++ dma_addr_t control_block) { }
++
++static inline void bcm_dma_wait_idle(void __iomem *dma_chan_base) { }
++
++static inline bool bcm_dma_is_busy(void __iomem *dma_chan_base)
++{
++ return false;
++}
++
++static inline int bcm_dma_abort(void __iomem *dma_chan_base)
++{
++ return -EINVAL;
++}
++
++static inline int bcm_dma_chan_alloc(unsigned preferred_feature_set,
++ void __iomem **out_dma_base,
++ int *out_dma_irq)
++{
++ return -EINVAL;
++}
++
++static inline int bcm_dma_chan_free(int channel)
++{
++ return -EINVAL;
++}
++
++#endif /* CONFIG_DMA_BCM2708_LEGACY */
++
++#endif /* _PLAT_BCM2708_DMA_H */
+diff -Nur linux-4.1.3/include/linux/platform_data/mailbox-bcm2708.h linux-xbian-rpi/include/linux/platform_data/mailbox-bcm2708.h
+--- linux-4.1.3/include/linux/platform_data/mailbox-bcm2708.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/include/linux/platform_data/mailbox-bcm2708.h 2015-07-28 01:20:58.457113811 +0200
+@@ -0,0 +1,127 @@
++/*
++ * Copyright (C) 2010 Broadcom
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ */
++#ifndef _PLAT_MAILBOX_BCM2708_H
++#define _PLAT_MAILBOX_BCM2708_H
++
++/* Routines to handle I/O via the VideoCore "ARM control" registers
++ * (semaphores, doorbells, mailboxes)
++ */
++
++/* Constants shared with the ARM identifying separate mailbox channels */
++#define MBOX_CHAN_POWER 0 /* for use by the power management interface */
++#define MBOX_CHAN_FB 1 /* for use by the frame buffer */
++#define MBOX_CHAN_VCHIQ 3 /* for use by the VCHIQ interface */
++#define MBOX_CHAN_PROPERTY 8 /* for use by the property channel */
++#define MBOX_CHAN_COUNT 9
++
++enum {
++ VCMSG_PROCESS_REQUEST = 0x00000000
++};
++
++enum {
++ VCMSG_REQUEST_SUCCESSFUL = 0x80000000,
++ VCMSG_REQUEST_FAILED = 0x80000001
++};
++
++/* Mailbox property tags */
++enum {
++ VCMSG_PROPERTY_END = 0x00000000,
++ VCMSG_GET_FIRMWARE_REVISION = 0x00000001,
++ VCMSG_GET_BOARD_MODEL = 0x00010001,
++ VCMSG_GET_BOARD_REVISION = 0x00010002,
++ VCMSG_GET_BOARD_MAC_ADDRESS = 0x00010003,
++ VCMSG_GET_BOARD_SERIAL = 0x00010004,
++ VCMSG_GET_ARM_MEMORY = 0x00010005,
++ VCMSG_GET_VC_MEMORY = 0x00010006,
++ VCMSG_GET_CLOCKS = 0x00010007,
++ VCMSG_GET_COMMAND_LINE = 0x00050001,
++ VCMSG_GET_DMA_CHANNELS = 0x00060001,
++ VCMSG_GET_POWER_STATE = 0x00020001,
++ VCMSG_GET_TIMING = 0x00020002,
++ VCMSG_SET_POWER_STATE = 0x00028001,
++ VCMSG_GET_CLOCK_STATE = 0x00030001,
++ VCMSG_SET_CLOCK_STATE = 0x00038001,
++ VCMSG_GET_CLOCK_RATE = 0x00030002,
++ VCMSG_SET_CLOCK_RATE = 0x00038002,
++ VCMSG_GET_VOLTAGE = 0x00030003,
++ VCMSG_SET_VOLTAGE = 0x00038003,
++ VCMSG_GET_MAX_CLOCK = 0x00030004,
++ VCMSG_GET_MAX_VOLTAGE = 0x00030005,
++ VCMSG_GET_TEMPERATURE = 0x00030006,
++ VCMSG_GET_MIN_CLOCK = 0x00030007,
++ VCMSG_GET_MIN_VOLTAGE = 0x00030008,
++ VCMSG_GET_TURBO = 0x00030009,
++ VCMSG_GET_MAX_TEMPERATURE = 0x0003000a,
++ VCMSG_GET_STC = 0x0003000b,
++ VCMSG_SET_TURBO = 0x00038009,
++ VCMSG_SET_ALLOCATE_MEM = 0x0003000c,
++ VCMSG_SET_LOCK_MEM = 0x0003000d,
++ VCMSG_SET_UNLOCK_MEM = 0x0003000e,
++ VCMSG_SET_RELEASE_MEM = 0x0003000f,
++ VCMSG_SET_EXECUTE_CODE = 0x00030010,
++ VCMSG_SET_EXECUTE_QPU = 0x00030011,
++ VCMSG_SET_ENABLE_QPU = 0x00030012,
++ VCMSG_GET_RESOURCE_HANDLE = 0x00030014,
++ VCMSG_GET_EDID_BLOCK = 0x00030020,
++ VCMSG_GET_CUSTOMER_OTP = 0x00030021,
++ VCMSG_SET_CUSTOMER_OTP = 0x00038021,
++ VCMSG_SET_ALLOCATE_BUFFER = 0x00040001,
++ VCMSG_SET_RELEASE_BUFFER = 0x00048001,
++ VCMSG_SET_BLANK_SCREEN = 0x00040002,
++ VCMSG_TST_BLANK_SCREEN = 0x00044002,
++ VCMSG_GET_PHYSICAL_WIDTH_HEIGHT = 0x00040003,
++ VCMSG_TST_PHYSICAL_WIDTH_HEIGHT = 0x00044003,
++ VCMSG_SET_PHYSICAL_WIDTH_HEIGHT = 0x00048003,
++ VCMSG_GET_VIRTUAL_WIDTH_HEIGHT = 0x00040004,
++ VCMSG_TST_VIRTUAL_WIDTH_HEIGHT = 0x00044004,
++ VCMSG_SET_VIRTUAL_WIDTH_HEIGHT = 0x00048004,
++ VCMSG_GET_DEPTH = 0x00040005,
++ VCMSG_TST_DEPTH = 0x00044005,
++ VCMSG_SET_DEPTH = 0x00048005,
++ VCMSG_GET_PIXEL_ORDER = 0x00040006,
++ VCMSG_TST_PIXEL_ORDER = 0x00044006,
++ VCMSG_SET_PIXEL_ORDER = 0x00048006,
++ VCMSG_GET_ALPHA_MODE = 0x00040007,
++ VCMSG_TST_ALPHA_MODE = 0x00044007,
++ VCMSG_SET_ALPHA_MODE = 0x00048007,
++ VCMSG_GET_PITCH = 0x00040008,
++ VCMSG_TST_PITCH = 0x00044008,
++ VCMSG_SET_PITCH = 0x00048008,
++ VCMSG_GET_VIRTUAL_OFFSET = 0x00040009,
++ VCMSG_TST_VIRTUAL_OFFSET = 0x00044009,
++ VCMSG_SET_VIRTUAL_OFFSET = 0x00048009,
++ VCMSG_GET_OVERSCAN = 0x0004000a,
++ VCMSG_TST_OVERSCAN = 0x0004400a,
++ VCMSG_SET_OVERSCAN = 0x0004800a,
++ VCMSG_GET_PALETTE = 0x0004000b,
++ VCMSG_TST_PALETTE = 0x0004400b,
++ VCMSG_SET_PALETTE = 0x0004800b,
++ VCMSG_GET_LAYER = 0x0004000c,
++ VCMSG_TST_LAYER = 0x0004400c,
++ VCMSG_SET_LAYER = 0x0004800c,
++ VCMSG_GET_TRANSFORM = 0x0004000d,
++ VCMSG_TST_TRANSFORM = 0x0004400d,
++ VCMSG_SET_TRANSFORM = 0x0004800d,
++ VCMSG_TST_VSYNC = 0x0004400e,
++ VCMSG_SET_VSYNC = 0x0004800e,
++ VCMSG_GET_TOUCHBUF = 0x0004000f,
++ VCMSG_SET_CURSOR_INFO = 0x00008010,
++ VCMSG_SET_CURSOR_STATE = 0x00008011,
++};
++
++int bcm_mailbox_read(unsigned chan, uint32_t *data28);
++int bcm_mailbox_write(unsigned chan, uint32_t data28);
++int bcm_mailbox_property(void *data, int size);
++
++#endif
+diff -Nur linux-4.1.3/include/linux/vmstat.h linux-xbian-rpi/include/linux/vmstat.h
+--- linux-4.1.3/include/linux/vmstat.h 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/include/linux/vmstat.h 2015-07-28 01:20:58.457113811 +0200
+@@ -241,7 +241,11 @@
+ static inline void __dec_zone_state(struct zone *zone, enum zone_stat_item item)
+ {
+ atomic_long_dec(&zone->vm_stat[item]);
++ if (item == NR_FILE_DIRTY && unlikely(atomic_long_read(&zone->vm_stat[item]) < 0))
++ atomic_long_set(&zone->vm_stat[item], 0);
+ atomic_long_dec(&vm_stat[item]);
++ if (item == NR_FILE_DIRTY && unlikely(atomic_long_read(&vm_stat[item]) < 0))
++ atomic_long_set(&vm_stat[item], 0);
+ }
+
+ static inline void __inc_zone_page_state(struct page *page,
+diff -Nur linux-4.1.3/include/linux/w1-gpio.h linux-xbian-rpi/include/linux/w1-gpio.h
+--- linux-4.1.3/include/linux/w1-gpio.h 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/include/linux/w1-gpio.h 2015-07-28 01:20:58.457113811 +0200
+@@ -18,6 +18,7 @@
+ struct w1_gpio_platform_data {
+ unsigned int pin;
+ unsigned int is_open_drain:1;
++ unsigned int parasitic_power:1;
+ void (*enable_external_pullup)(int enable);
+ unsigned int ext_pullup_enable_pin;
+ unsigned int pullup_duration;
+diff -Nur linux-4.1.3/include/soc/bcm2835/raspberrypi-firmware.h linux-xbian-rpi/include/soc/bcm2835/raspberrypi-firmware.h
+--- linux-4.1.3/include/soc/bcm2835/raspberrypi-firmware.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/include/soc/bcm2835/raspberrypi-firmware.h 2015-07-28 01:20:58.457113811 +0200
+@@ -0,0 +1,125 @@
++/*
++ * Copyright © 2015 Broadcom
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/types.h>
++#include <linux/of_device.h>
++
++struct rpi_firmware;
++
++enum rpi_firmware_property_status {
++ RPI_FIRMWARE_STATUS_REQUEST = 0,
++ RPI_FIRMWARE_STATUS_SUCCESS = 0x80000000,
++ RPI_FIRMWARE_STATUS_ERROR = 0x80000001,
++};
++
++/**
++ * struct rpi_firmware_property_tag_header - Firmware property tag header
++ * @tag: One of enum_mbox_property_tag.
++ * @buf_size: The number of bytes in the value buffer following this
++ * struct.
++ * @req_resp_size: On submit, the length of the request (though it doesn't
++ * appear to be currently used by the firmware). On return,
++ * the length of the response (always 4 byte aligned), with
++ * the low bit set.
++ */
++struct rpi_firmware_property_tag_header {
++ u32 tag;
++ u32 buf_size;
++ u32 req_resp_size;
++};
++
++enum rpi_firmware_property_tag {
++ RPI_FIRMWARE_PROPERTY_END = 0,
++ RPI_FIRMWARE_GET_FIRMWARE_REVISION = 0x00000001,
++
++ RPI_FIRMWARE_SET_CURSOR_INFO = 0x00008010,
++ RPI_FIRMWARE_SET_CURSOR_STATE = 0x00008011,
++
++ RPI_FIRMWARE_GET_BOARD_MODEL = 0x00010001,
++ RPI_FIRMWARE_GET_BOARD_REVISION = 0x00010002,
++ RPI_FIRMWARE_GET_BOARD_MAC_ADDRESS = 0x00010003,
++ RPI_FIRMWARE_GET_BOARD_SERIAL = 0x00010004,
++ RPI_FIRMWARE_GET_ARM_MEMORY = 0x00010005,
++ RPI_FIRMWARE_GET_VC_MEMORY = 0x00010006,
++ RPI_FIRMWARE_GET_CLOCKS = 0x00010007,
++ RPI_FIRMWARE_GET_POWER_STATE = 0x00020001,
++ RPI_FIRMWARE_GET_TIMING = 0x00020002,
++ RPI_FIRMWARE_SET_POWER_STATE = 0x00028001,
++ RPI_FIRMWARE_GET_CLOCK_STATE = 0x00030001,
++ RPI_FIRMWARE_GET_CLOCK_RATE = 0x00030002,
++ RPI_FIRMWARE_GET_VOLTAGE = 0x00030003,
++ RPI_FIRMWARE_GET_MAX_CLOCK_RATE = 0x00030004,
++ RPI_FIRMWARE_GET_MAX_VOLTAGE = 0x00030005,
++ RPI_FIRMWARE_GET_TEMPERATURE = 0x00030006,
++ RPI_FIRMWARE_GET_MIN_CLOCK_RATE = 0x00030007,
++ RPI_FIRMWARE_GET_MIN_VOLTAGE = 0x00030008,
++ RPI_FIRMWARE_GET_TURBO = 0x00030009,
++ RPI_FIRMWARE_GET_MAX_TEMPERATURE = 0x0003000a,
++ RPI_FIRMWARE_GET_STC = 0x0003000b,
++ RPI_FIRMWARE_ALLOCATE_MEMORY = 0x0003000c,
++ RPI_FIRMWARE_LOCK_MEMORY = 0x0003000d,
++ RPI_FIRMWARE_UNLOCK_MEMORY = 0x0003000e,
++ RPI_FIRMWARE_RELEASE_MEMORY = 0x0003000f,
++ RPI_FIRMWARE_EXECUTE_CODE = 0x00030010,
++ RPI_FIRMWARE_EXECUTE_QPU = 0x00030011,
++ RPI_FIRMWARE_SET_ENABLE_QPU = 0x00030012,
++ RPI_FIRMWARE_GET_DISPMANX_RESOURCE_MEM_HANDLE = 0x00030014,
++ RPI_FIRMWARE_GET_EDID_BLOCK = 0x00030020,
++ RPI_FIRMWARE_GET_CUSTOMER_OTP = 0x00030021,
++ RPI_FIRMWARE_SET_CLOCK_STATE = 0x00038001,
++ RPI_FIRMWARE_SET_CLOCK_RATE = 0x00038002,
++ RPI_FIRMWARE_SET_VOLTAGE = 0x00038003,
++ RPI_FIRMWARE_SET_TURBO = 0x00038009,
++ RPI_FIRMWARE_SET_CUSTOMER_OTP = 0x00038021,
++
++ /* Dispmanx TAGS */
++ RPI_FIRMWARE_FRAMEBUFFER_ALLOCATE = 0x00040001,
++ RPI_FIRMWARE_FRAMEBUFFER_BLANK = 0x00040002,
++ RPI_FIRMWARE_FRAMEBUFFER_GET_PHYSICAL_WIDTH_HEIGHT = 0x00040003,
++ RPI_FIRMWARE_FRAMEBUFFER_GET_VIRTUAL_WIDTH_HEIGHT = 0x00040004,
++ RPI_FIRMWARE_FRAMEBUFFER_GET_DEPTH = 0x00040005,
++ RPI_FIRMWARE_FRAMEBUFFER_GET_PIXEL_ORDER = 0x00040006,
++ RPI_FIRMWARE_FRAMEBUFFER_GET_ALPHA_MODE = 0x00040007,
++ RPI_FIRMWARE_FRAMEBUFFER_GET_PITCH = 0x00040008,
++ RPI_FIRMWARE_FRAMEBUFFER_GET_VIRTUAL_OFFSET = 0x00040009,
++ RPI_FIRMWARE_FRAMEBUFFER_GET_OVERSCAN = 0x0004000a,
++ RPI_FIRMWARE_FRAMEBUFFER_GET_PALETTE = 0x0004000b,
++ RPI_FIRMWARE_FRAMEBUFFER_GET_TOUCHBUF = 0x0004000f,
++ RPI_FIRMWARE_FRAMEBUFFER_RELEASE = 0x00048001,
++ RPI_FIRMWARE_FRAMEBUFFER_TEST_PHYSICAL_WIDTH_HEIGHT = 0x00044003,
++ RPI_FIRMWARE_FRAMEBUFFER_TEST_VIRTUAL_WIDTH_HEIGHT = 0x00044004,
++ RPI_FIRMWARE_FRAMEBUFFER_TEST_DEPTH = 0x00044005,
++ RPI_FIRMWARE_FRAMEBUFFER_TEST_PIXEL_ORDER = 0x00044006,
++ RPI_FIRMWARE_FRAMEBUFFER_TEST_ALPHA_MODE = 0x00044007,
++ RPI_FIRMWARE_FRAMEBUFFER_TEST_VIRTUAL_OFFSET = 0x00044009,
++ RPI_FIRMWARE_FRAMEBUFFER_TEST_OVERSCAN = 0x0004400a,
++ RPI_FIRMWARE_FRAMEBUFFER_TEST_PALETTE = 0x0004400b,
++ RPI_FIRMWARE_FRAMEBUFFER_TEST_VSYNC = 0x0004400e,
++ RPI_FIRMWARE_FRAMEBUFFER_SET_PHYSICAL_WIDTH_HEIGHT = 0x00048003,
++ RPI_FIRMWARE_FRAMEBUFFER_SET_VIRTUAL_WIDTH_HEIGHT = 0x00048004,
++ RPI_FIRMWARE_FRAMEBUFFER_SET_DEPTH = 0x00048005,
++ RPI_FIRMWARE_FRAMEBUFFER_SET_PIXEL_ORDER = 0x00048006,
++ RPI_FIRMWARE_FRAMEBUFFER_SET_ALPHA_MODE = 0x00048007,
++ RPI_FIRMWARE_FRAMEBUFFER_SET_VIRTUAL_OFFSET = 0x00048009,
++ RPI_FIRMWARE_FRAMEBUFFER_SET_OVERSCAN = 0x0004800a,
++ RPI_FIRMWARE_FRAMEBUFFER_SET_PALETTE = 0x0004800b,
++ RPI_FIRMWARE_FRAMEBUFFER_SET_VSYNC = 0x0004800e,
++
++ RPI_FIRMWARE_VCHIQ_INIT = 0x00048010,
++
++ RPI_FIRMWARE_GET_COMMAND_LINE = 0x00050001,
++ RPI_FIRMWARE_GET_DMA_CHANNELS = 0x00060001,
++};
++
++int rpi_firmware_transaction(struct rpi_firmware *fw, u32 chan, u32 data);
++u32 rpi_firmware_transaction_received(struct rpi_firmware *fw);
++int rpi_firmware_property(struct rpi_firmware *fw,
++ u32 tag, void *data, size_t len);
++int rpi_firmware_property_list(struct rpi_firmware *fw,
++ void *data, size_t tag_size);
++struct rpi_firmware *rpi_firmware_get(struct device_node *firmware_node);
+diff -Nur linux-4.1.3/include/uapi/linux/fb.h linux-xbian-rpi/include/uapi/linux/fb.h
+--- linux-4.1.3/include/uapi/linux/fb.h 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/include/uapi/linux/fb.h 2015-07-28 01:20:58.457113811 +0200
+@@ -34,6 +34,11 @@
+ #define FBIOPUT_MODEINFO 0x4617
+ #define FBIOGET_DISPINFO 0x4618
+ #define FBIO_WAITFORVSYNC _IOW('F', 0x20, __u32)
++/*
++ * HACK: use 'z' in order not to clash with any other ioctl numbers which might
++ * be concurrently added to the mainline kernel
++ */
++#define FBIOCOPYAREA _IOW('z', 0x21, struct fb_copyarea)
+
+ #define FB_TYPE_PACKED_PIXELS 0 /* Packed Pixels */
+ #define FB_TYPE_PLANES 1 /* Non interleaved planes */
+diff -Nur linux-4.1.3/kernel/cgroup.c linux-xbian-rpi/kernel/cgroup.c
+--- linux-4.1.3/kernel/cgroup.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/kernel/cgroup.c 2015-07-28 01:20:58.457113811 +0200
+@@ -5393,6 +5393,29 @@
+ }
+ __setup("cgroup_disable=", cgroup_disable);
+
++static int __init cgroup_enable(char *str)
++{
++ struct cgroup_subsys *ss;
++ char *token;
++ int i;
++
++ while ((token = strsep(&str, ",")) != NULL) {
++ if (!*token)
++ continue;
++
++ for_each_subsys(ss, i) {
++ if (!strcmp(token, ss->name)) {
++ ss->disabled = 0;
++ printk(KERN_INFO "Enabling %s control group"
++ " subsystem\n", ss->name);
++ break;
++ }
++ }
++ }
++ return 1;
++}
++__setup("cgroup_enable=", cgroup_enable);
++
+ static int __init cgroup_set_legacy_files_on_dfl(char *str)
+ {
+ printk("cgroup: using legacy files on the default hierarchy\n");
+diff -Nur linux-4.1.3/mm/memcontrol.c linux-xbian-rpi/mm/memcontrol.c
+--- linux-4.1.3/mm/memcontrol.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/mm/memcontrol.c 2015-07-28 01:20:58.461099590 +0200
+@@ -5388,6 +5388,7 @@
+ .dfl_cftypes = memory_files,
+ .legacy_cftypes = mem_cgroup_legacy_files,
+ .early_init = 0,
++ .disabled = 1,
+ };
+
+ /**
+diff -Nur linux-4.1.3/scripts/dtc/checks.c linux-xbian-rpi/scripts/dtc/checks.c
+--- linux-4.1.3/scripts/dtc/checks.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/scripts/dtc/checks.c 2015-07-28 01:20:58.461099590 +0200
+@@ -53,7 +53,7 @@
+ void *data;
+ bool warn, error;
+ enum checkstatus status;
+- int inprogress;
++ bool inprogress;
+ int num_prereqs;
+ struct check **prereq;
+ };
+@@ -113,6 +113,7 @@
+ vfprintf(stderr, fmt, ap);
+ fprintf(stderr, "\n");
+ }
++ va_end(ap);
+ }
+
+ #define FAIL(c, ...) \
+@@ -141,9 +142,9 @@
+ check_nodes_props(c, dt, child);
+ }
+
+-static int run_check(struct check *c, struct node *dt)
++static bool run_check(struct check *c, struct node *dt)
+ {
+- int error = 0;
++ bool error = false;
+ int i;
+
+ assert(!c->inprogress);
+@@ -151,11 +152,11 @@
+ if (c->status != UNCHECKED)
+ goto out;
+
+- c->inprogress = 1;
++ c->inprogress = true;
+
+ for (i = 0; i < c->num_prereqs; i++) {
+ struct check *prq = c->prereq[i];
+- error |= run_check(prq, dt);
++ error = error || run_check(prq, dt);
+ if (prq->status != PASSED) {
+ c->status = PREREQ;
+ check_msg(c, "Failed prerequisite '%s'",
+@@ -177,9 +178,9 @@
+ TRACE(c, "\tCompleted, status %d", c->status);
+
+ out:
+- c->inprogress = 0;
++ c->inprogress = false;
+ if ((c->status != PASSED) && (c->error))
+- error = 1;
++ error = true;
+ return error;
+ }
+
+@@ -457,22 +458,93 @@
+ struct node *node, struct property *prop)
+ {
+ struct marker *m = prop->val.markers;
++ struct fixup *f, **fp;
++ struct fixup_entry *fe, **fep;
+ struct node *refnode;
+ cell_t phandle;
++ int has_phandle_refs;
++
++ has_phandle_refs = 0;
++ for_each_marker_of_type(m, REF_PHANDLE) {
++ has_phandle_refs = 1;
++ break;
++ }
++
++ if (!has_phandle_refs)
++ return;
+
+ for_each_marker_of_type(m, REF_PHANDLE) {
+ assert(m->offset + sizeof(cell_t) <= prop->val.len);
+
+ refnode = get_node_by_ref(dt, m->ref);
+- if (! refnode) {
++ if (!refnode && !symbol_fixup_support) {
+ FAIL(c, "Reference to non-existent node or label \"%s\"\n",
+- m->ref);
++ m->ref);
+ continue;
+ }
+
+- phandle = get_node_phandle(dt, refnode);
+- *((cell_t *)(prop->val.val + m->offset)) = cpu_to_fdt32(phandle);
++ if (!refnode) {
++ /* allocate fixup entry */
++ fe = xmalloc(sizeof(*fe));
++
++ fe->node = node;
++ fe->prop = prop;
++ fe->offset = m->offset;
++ fe->next = NULL;
++
++ /* search for an already existing fixup */
++ for_each_fixup(dt, f)
++ if (strcmp(f->ref, m->ref) == 0)
++ break;
++
++ /* no fixup found, add new */
++ if (f == NULL) {
++ f = xmalloc(sizeof(*f));
++ f->ref = m->ref;
++ f->entries = NULL;
++ f->next = NULL;
++
++ /* add it to the tree */
++ fp = &dt->fixups;
++ while (*fp)
++ fp = &(*fp)->next;
++ *fp = f;
++ }
++
++ /* and now append fixup entry */
++ fep = &f->entries;
++ while (*fep)
++ fep = &(*fep)->next;
++ *fep = fe;
++
++ /* mark the entry as unresolved */
++ phandle = 0xdeadbeef;
++ } else {
++ phandle = get_node_phandle(dt, refnode);
++
++ /* if it's a plugin, we need to record it */
++ if (symbol_fixup_support && dt->is_plugin) {
++
++ /* allocate a new local fixup entry */
++ fe = xmalloc(sizeof(*fe));
++
++ fe->node = node;
++ fe->prop = prop;
++ fe->offset = m->offset;
++ fe->next = NULL;
++
++ /* append it to the local fixups */
++ fep = &dt->local_fixups;
++ while (*fep)
++ fep = &(*fep)->next;
++ *fep = fe;
++ }
++ }
++
++ *((cell_t *)(prop->val.val + m->offset)) =
++ cpu_to_fdt32(phandle);
+ }
++
+ }
+ ERROR(phandle_references, NULL, NULL, fixup_phandle_references, NULL,
+ &duplicate_node_names, &explicit_phandles);
+@@ -624,11 +696,11 @@
+ if (!reg && !ranges)
+ return;
+
+- if ((node->parent->addr_cells == -1))
++ if (node->parent->addr_cells == -1)
+ FAIL(c, "Relying on default #address-cells value for %s",
+ node->fullpath);
+
+- if ((node->parent->size_cells == -1))
++ if (node->parent->size_cells == -1)
+ FAIL(c, "Relying on default #size-cells value for %s",
+ node->fullpath);
+ }
+@@ -651,6 +723,45 @@
+ }
+ TREE_WARNING(obsolete_chosen_interrupt_controller, NULL);
+
++static void check_auto_label_phandles(struct check *c, struct node *dt,
++ struct node *node)
++{
++ struct label *l;
++ struct symbol *s, **sp;
++ int has_label;
++
++ if (!symbol_fixup_support)
++ return;
++
++ has_label = 0;
++ for_each_label(node->labels, l) {
++ has_label = 1;
++ break;
++ }
++
++ if (!has_label)
++ return;
++
++ /* force allocation of a phandle for this node */
++ (void)get_node_phandle(dt, node);
++
++ /* add the symbol */
++ for_each_label(node->labels, l) {
++
++ s = xmalloc(sizeof(*s));
++ s->label = l;
++ s->node = node;
++ s->next = NULL;
++
++ /* add it to the symbols list */
++ sp = &dt->symbols;
++ while (*sp)
++ sp = &((*sp)->next);
++ *sp = s;
++ }
++}
++NODE_WARNING(auto_label_phandles, NULL);
++
+ static struct check *check_table[] = {
+ &duplicate_node_names, &duplicate_property_names,
+ &node_name_chars, &node_name_format, &property_name_chars,
+@@ -669,6 +780,8 @@
+ &avoid_default_addr_size,
+ &obsolete_chosen_interrupt_controller,
+
++ &auto_label_phandles,
++
+ &always_fail,
+ };
+
+@@ -706,15 +819,15 @@
+ c->error = c->error && !error;
+ }
+
+-void parse_checks_option(bool warn, bool error, const char *optarg)
++void parse_checks_option(bool warn, bool error, const char *arg)
+ {
+ int i;
+- const char *name = optarg;
++ const char *name = arg;
+ bool enable = true;
+
+- if ((strncmp(optarg, "no-", 3) == 0)
+- || (strncmp(optarg, "no_", 3) == 0)) {
+- name = optarg + 3;
++ if ((strncmp(arg, "no-", 3) == 0)
++ || (strncmp(arg, "no_", 3) == 0)) {
++ name = arg + 3;
+ enable = false;
+ }
+
+@@ -733,7 +846,7 @@
+ die("Unrecognized check name \"%s\"\n", name);
+ }
+
+-void process_checks(int force, struct boot_info *bi)
++void process_checks(bool force, struct boot_info *bi)
+ {
+ struct node *dt = bi->dt;
+ int i;
+diff -Nur linux-4.1.3/scripts/dtc/data.c linux-xbian-rpi/scripts/dtc/data.c
+--- linux-4.1.3/scripts/dtc/data.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/scripts/dtc/data.c 2015-07-28 01:20:58.461099590 +0200
+@@ -74,7 +74,7 @@
+ struct data d;
+ char *q;
+
+- d = data_grow_for(empty_data, strlen(s)+1);
++ d = data_grow_for(empty_data, len + 1);
+
+ q = d.val;
+ while (i < len) {
+@@ -250,20 +250,20 @@
+ return data_append_markers(d, m);
+ }
+
+-int data_is_one_string(struct data d)
++bool data_is_one_string(struct data d)
+ {
+ int i;
+ int len = d.len;
+
+ if (len == 0)
+- return 0;
++ return false;
+
+ for (i = 0; i < len-1; i++)
+ if (d.val[i] == '\0')
+- return 0;
++ return false;
+
+ if (d.val[len-1] != '\0')
+- return 0;
++ return false;
+
+- return 1;
++ return true;
+ }
+diff -Nur linux-4.1.3/scripts/dtc/dtc.c linux-xbian-rpi/scripts/dtc/dtc.c
+--- linux-4.1.3/scripts/dtc/dtc.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/scripts/dtc/dtc.c 2015-07-28 01:20:58.461099590 +0200
+@@ -29,6 +29,7 @@
+ int minsize; /* Minimum blob size */
+ int padsize; /* Additional padding to blob */
+ int phandle_format = PHANDLE_BOTH; /* Use linux,phandle or phandle properties */
++int symbol_fixup_support = 0;
+
+ static void fill_fullpaths(struct node *tree, const char *prefix)
+ {
+@@ -48,8 +49,10 @@
+ }
+
+ /* Usage related data. */
++#define FDT_VERSION(version) _FDT_VERSION(version)
++#define _FDT_VERSION(version) #version
+ static const char usage_synopsis[] = "dtc [options] <input file>";
+-static const char usage_short_opts[] = "qI:O:o:V:d:R:S:p:fb:i:H:sW:E:hv";
++static const char usage_short_opts[] = "qI:O:o:V:d:R:S:p:fb:i:H:sW:E:hv@";
+ static struct option const usage_long_opts[] = {
+ {"quiet", no_argument, NULL, 'q'},
+ {"in-format", a_argument, NULL, 'I'},
+@@ -67,6 +70,7 @@
+ {"phandle", a_argument, NULL, 'H'},
+ {"warning", a_argument, NULL, 'W'},
+ {"error", a_argument, NULL, 'E'},
++ {"symbols", a_argument, NULL, '@'},
+ {"help", no_argument, NULL, 'h'},
+ {"version", no_argument, NULL, 'v'},
+ {NULL, no_argument, NULL, 0x0},
+@@ -82,9 +86,9 @@
+ "\t\tdts - device tree source text\n"
+ "\t\tdtb - device tree blob\n"
+ "\t\tasm - assembler source",
+- "\n\tBlob version to produce, defaults to %d (for dtb and asm output)", //, DEFAULT_FDT_VERSION);
++ "\n\tBlob version to produce, defaults to "FDT_VERSION(DEFAULT_FDT_VERSION)" (for dtb and asm output)",
+ "\n\tOutput dependency file",
+- "\n\ttMake space for <number> reserve map entries (for dtb and asm output)",
++ "\n\tMake space for <number> reserve map entries (for dtb and asm output)",
+ "\n\tMake the blob at least <bytes> long (extra space)",
+ "\n\tAdd padding to the blob of <bytes> long (extra space)",
+ "\n\tSet the physical boot cpu",
+@@ -97,6 +101,7 @@
+ "\t\tboth - Both \"linux,phandle\" and \"phandle\" properties",
+ "\n\tEnable/disable warnings (prefix with \"no-\")",
+ "\n\tEnable/disable errors (prefix with \"no-\")",
++ "\n\tSymbols and Fixups support",
+ "\n\tPrint this help and exit",
+ "\n\tPrint version and exit",
+ NULL,
+@@ -109,7 +114,7 @@
+ const char *outform = "dts";
+ const char *outname = "-";
+ const char *depname = NULL;
+- int force = 0, sort = 0;
++ bool force = false, sort = false;
+ const char *arg;
+ int opt;
+ FILE *outf = NULL;
+@@ -148,7 +153,7 @@
+ padsize = strtol(optarg, NULL, 0);
+ break;
+ case 'f':
+- force = 1;
++ force = true;
+ break;
+ case 'q':
+ quiet++;
+@@ -174,7 +179,7 @@
+ break;
+
+ case 's':
+- sort = 1;
++ sort = true;
+ break;
+
+ case 'W':
+@@ -184,7 +189,9 @@
+ case 'E':
+ parse_checks_option(false, true, optarg);
+ break;
+-
++ case '@':
++ symbol_fixup_support = 1;
++ break;
+ case 'h':
+ usage(NULL);
+ default:
+@@ -237,7 +244,7 @@
+ if (streq(outname, "-")) {
+ outf = stdout;
+ } else {
+- outf = fopen(outname, "w");
++ outf = fopen(outname, "wb");
+ if (! outf)
+ die("Couldn't open output file %s: %s\n",
+ outname, strerror(errno));
+diff -Nur linux-4.1.3/scripts/dtc/dtc.h linux-xbian-rpi/scripts/dtc/dtc.h
+--- linux-4.1.3/scripts/dtc/dtc.h 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/scripts/dtc/dtc.h 2015-07-28 01:20:58.461099590 +0200
+@@ -38,9 +38,9 @@
+ #include "util.h"
+
+ #ifdef DEBUG
+-#define debug(fmt,args...) printf(fmt, ##args)
++#define debug(...) printf(__VA_ARGS__)
+ #else
+-#define debug(fmt,args...)
++#define debug(...)
+ #endif
+
+
+@@ -54,6 +54,7 @@
+ extern int minsize; /* Minimum blob size */
+ extern int padsize; /* Additional padding to blob */
+ extern int phandle_format; /* Use linux,phandle or phandle properties */
++extern int symbol_fixup_support;/* enable symbols & fixup support */
+
+ #define PHANDLE_LEGACY 0x1
+ #define PHANDLE_EPAPR 0x2
+@@ -88,7 +89,7 @@
+ };
+
+
+-#define empty_data ((struct data){ /* all .members = 0 or NULL */ })
++#define empty_data ((struct data){ 0 /* all .members = 0 or NULL */ })
+
+ #define for_each_marker(m) \
+ for (; (m); (m) = (m)->next)
+@@ -118,7 +119,7 @@
+
+ struct data data_add_marker(struct data d, enum markertype type, char *ref);
+
+-int data_is_one_string(struct data d);
++bool data_is_one_string(struct data d);
+
+ /* DT constraints */
+
+@@ -127,13 +128,32 @@
+
+ /* Live trees */
+ struct label {
+- int deleted;
++ bool deleted;
+ char *label;
+ struct label *next;
+ };
+
++struct fixup_entry {
++ int offset;
++ struct node *node;
++ struct property *prop;
++ struct fixup_entry *next;
++};
++
++struct fixup {
++ char *ref;
++ struct fixup_entry *entries;
++ struct fixup *next;
++};
++
++struct symbol {
++ struct label *label;
++ struct node *node;
++ struct symbol *next;
++};
++
+ struct property {
+- int deleted;
++ bool deleted;
+ char *name;
+ struct data val;
+
+@@ -143,7 +163,7 @@
+ };
+
+ struct node {
+- int deleted;
++ bool deleted;
+ char *name;
+ struct property *proplist;
+ struct node *children;
+@@ -158,6 +178,12 @@
+ int addr_cells, size_cells;
+
+ struct label *labels;
++
++ int is_root;
++ int is_plugin;
++ struct fixup *fixups;
++ struct symbol *symbols;
++ struct fixup_entry *local_fixups;
+ };
+
+ #define for_each_label_withdel(l0, l) \
+@@ -181,6 +207,18 @@
+ for_each_child_withdel(n, c) \
+ if (!(c)->deleted)
+
++#define for_each_fixup(n, f) \
++ for ((f) = (n)->fixups; (f); (f) = (f)->next)
++
++#define for_each_fixup_entry(f, fe) \
++ for ((fe) = (f)->entries; (fe); (fe) = (fe)->next)
++
++#define for_each_symbol(n, s) \
++ for ((s) = (n)->symbols; (s); (s) = (s)->next)
++
++#define for_each_local_fixup_entry(n, fe) \
++ for ((fe) = (n)->local_fixups; (fe); (fe) = (fe)->next)
++
+ void add_label(struct label **labels, char *label);
+ void delete_labels(struct label **labels);
+
+@@ -247,8 +285,8 @@
+
+ /* Checks */
+
+-void parse_checks_option(bool warn, bool error, const char *optarg);
+-void process_checks(int force, struct boot_info *bi);
++void parse_checks_option(bool warn, bool error, const char *arg);
++void process_checks(bool force, struct boot_info *bi);
+
+ /* Flattened trees */
+
+diff -Nur linux-4.1.3/scripts/dtc/dtc-lexer.l linux-xbian-rpi/scripts/dtc/dtc-lexer.l
+--- linux-4.1.3/scripts/dtc/dtc-lexer.l 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/scripts/dtc/dtc-lexer.l 2015-07-28 01:20:58.461099590 +0200
+@@ -20,7 +20,6 @@
+
+ %option noyywrap nounput noinput never-interactive
+
+-%x INCLUDE
+ %x BYTESTRING
+ %x PROPNODENAME
+ %s V1
+@@ -40,6 +39,7 @@
+ #include "dtc-parser.tab.h"
+
+ YYLTYPE yylloc;
++extern bool treesource_error;
+
+ /* CAUTION: this will stop working if we ever use yyless() or yyunput() */
+ #define YY_USER_ACTION \
+@@ -61,7 +61,8 @@
+ BEGIN(V1); \
+
+ static void push_input_file(const char *filename);
+-static int pop_input_file(void);
++static bool pop_input_file(void);
++static void lexical_error(const char *fmt, ...);
+ %}
+
+ %%
+@@ -75,11 +76,11 @@
+ char *line, *tmp, *fn;
+ /* skip text before line # */
+ line = yytext;
+- while (!isdigit(*line))
++ while (!isdigit((unsigned char)*line))
+ line++;
+ /* skip digits in line # */
+ tmp = line;
+- while (!isspace(*tmp))
++ while (!isspace((unsigned char)*tmp))
+ tmp++;
+ /* "NULL"-terminate line # */
+ *tmp = '\0';
+@@ -112,6 +113,11 @@
+ return DT_V1;
+ }
+
++<*>"/plugin/" {
++ DPRINT("Keyword: /plugin/\n");
++ return DT_PLUGIN;
++ }
++
+ <*>"/memreserve/" {
+ DPRINT("Keyword: /memreserve/\n");
+ BEGIN_DEFAULT();
+@@ -146,15 +152,42 @@
+ }
+
+ <V1>([0-9]+|0[xX][0-9a-fA-F]+)(U|L|UL|LL|ULL)? {
+- yylval.literal = xstrdup(yytext);
+- DPRINT("Literal: '%s'\n", yylval.literal);
++ char *e;
++ DPRINT("Integer Literal: '%s'\n", yytext);
++
++ errno = 0;
++ yylval.integer = strtoull(yytext, &e, 0);
++
++ assert(!(*e) || !e[strspn(e, "UL")]);
++
++ if (errno == ERANGE)
++ lexical_error("Integer literal '%s' out of range",
++ yytext);
++ else
++ /* ERANGE is the only strtoull error triggerable
++ * by strings matching the pattern */
++ assert(errno == 0);
+ return DT_LITERAL;
+ }
+
+ <*>{CHAR_LITERAL} {
+- yytext[yyleng-1] = '\0';
+- yylval.literal = xstrdup(yytext+1);
+- DPRINT("Character literal: %s\n", yylval.literal);
++ struct data d;
++ DPRINT("Character literal: %s\n", yytext);
++
++ d = data_copy_escape_string(yytext+1, yyleng-2);
++ if (d.len == 1) {
++ lexical_error("Empty character literal");
++ yylval.integer = 0;
++ return DT_CHAR_LITERAL;
++ }
++
++ yylval.integer = (unsigned char)d.val[0];
++
++ if (d.len > 2)
++ lexical_error("Character literal has %d"
++ " characters instead of 1",
++ d.len - 1);
++
+ return DT_CHAR_LITERAL;
+ }
+
+@@ -164,7 +197,7 @@
+ return DT_REF;
+ }
+
+-<*>"&{/"{PATHCHAR}+\} { /* new-style path reference */
++<*>"&{/"{PATHCHAR}*\} { /* new-style path reference */
+ yytext[yyleng-1] = '\0';
+ DPRINT("Ref: %s\n", yytext+2);
+ yylval.labelref = xstrdup(yytext+2);
+@@ -238,13 +271,24 @@
+ }
+
+
+-static int pop_input_file(void)
++static bool pop_input_file(void)
+ {
+ if (srcfile_pop() == 0)
+- return 0;
++ return false;
+
+ yypop_buffer_state();
+ yyin = current_srcfile->f;
+
+- return 1;
++ return true;
++}
++
++static void lexical_error(const char *fmt, ...)
++{
++ va_list ap;
++
++ va_start(ap, fmt);
++ srcpos_verror(&yylloc, "Lexical error", fmt, ap);
++ va_end(ap);
++
++ treesource_error = true;
+ }
+diff -Nur linux-4.1.3/scripts/dtc/dtc-lexer.lex.c_shipped linux-xbian-rpi/scripts/dtc/dtc-lexer.lex.c_shipped
+--- linux-4.1.3/scripts/dtc/dtc-lexer.lex.c_shipped 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/scripts/dtc/dtc-lexer.lex.c_shipped 2015-07-28 01:20:58.461099590 +0200
+@@ -372,8 +372,8 @@
+ *yy_cp = '\0'; \
+ (yy_c_buf_p) = yy_cp;
+
+-#define YY_NUM_RULES 30
+-#define YY_END_OF_BUFFER 31
++#define YY_NUM_RULES 31
++#define YY_END_OF_BUFFER 32
+ /* This struct is not used in this scanner,
+ but its presence is necessary. */
+ struct yy_trans_info
+@@ -381,25 +381,26 @@
+ flex_int32_t yy_verify;
+ flex_int32_t yy_nxt;
+ };
+-static yyconst flex_int16_t yy_accept[161] =
++static yyconst flex_int16_t yy_accept[166] =
+ { 0,
++ 0, 0, 0, 0, 0, 0, 0, 0, 32, 30,
++ 19, 19, 30, 30, 30, 30, 30, 30, 30, 30,
++ 30, 30, 30, 30, 30, 30, 16, 17, 17, 30,
++ 17, 11, 11, 19, 27, 0, 3, 0, 28, 13,
++ 0, 0, 12, 0, 0, 0, 0, 0, 0, 0,
++ 0, 22, 24, 26, 25, 23, 0, 10, 29, 0,
++ 0, 0, 15, 15, 17, 17, 17, 11, 11, 11,
++ 0, 13, 0, 12, 0, 0, 0, 21, 0, 0,
++ 0, 0, 0, 0, 0, 0, 0, 17, 11, 11,
++ 11, 0, 14, 20, 0, 0, 0, 0, 0, 0,
++
++ 0, 0, 0, 0, 17, 0, 0, 0, 0, 0,
++ 0, 0, 0, 0, 0, 17, 7, 0, 0, 0,
++ 0, 0, 0, 0, 2, 0, 0, 0, 0, 0,
++ 0, 0, 0, 0, 4, 18, 0, 0, 5, 2,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+- 31, 29, 18, 18, 29, 29, 29, 29, 29, 29,
+- 29, 29, 29, 29, 29, 29, 29, 29, 15, 16,
+- 16, 29, 16, 10, 10, 18, 26, 0, 3, 0,
+- 27, 12, 0, 0, 11, 0, 0, 0, 0, 0,
+- 0, 0, 21, 23, 25, 24, 22, 0, 9, 28,
+- 0, 0, 0, 14, 14, 16, 16, 16, 10, 10,
+- 10, 0, 12, 0, 11, 0, 0, 0, 20, 0,
+- 0, 0, 0, 0, 0, 0, 0, 16, 10, 10,
+- 10, 0, 19, 0, 0, 0, 0, 0, 0, 0,
+-
+- 0, 0, 16, 13, 0, 0, 0, 0, 0, 0,
+- 0, 0, 0, 16, 6, 0, 0, 0, 0, 0,
+- 0, 2, 0, 0, 0, 0, 0, 0, 0, 0,
+- 4, 17, 0, 0, 2, 0, 0, 0, 0, 0,
+- 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
+- 0, 0, 5, 8, 0, 0, 0, 0, 7, 0
++ 0, 0, 1, 0, 0, 0, 0, 6, 9, 0,
++ 0, 0, 0, 8, 0
+ } ;
+
+ static yyconst flex_int32_t yy_ec[256] =
+@@ -415,9 +416,9 @@
+ 22, 22, 22, 22, 24, 22, 22, 25, 22, 22,
+ 1, 26, 27, 1, 22, 1, 21, 28, 29, 30,
+
+- 31, 21, 22, 22, 32, 22, 22, 33, 34, 35,
+- 36, 37, 22, 38, 39, 40, 41, 42, 22, 25,
+- 43, 22, 44, 45, 46, 1, 1, 1, 1, 1,
++ 31, 21, 32, 22, 33, 22, 22, 34, 35, 36,
++ 37, 38, 22, 39, 40, 41, 42, 43, 22, 25,
++ 44, 22, 45, 46, 47, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+@@ -434,163 +435,165 @@
+ 1, 1, 1, 1, 1
+ } ;
+
+-static yyconst flex_int32_t yy_meta[47] =
++static yyconst flex_int32_t yy_meta[48] =
+ { 0,
+ 1, 1, 1, 1, 1, 1, 2, 3, 1, 2,
+ 2, 2, 4, 5, 5, 5, 6, 1, 1, 1,
+ 7, 8, 8, 8, 8, 1, 1, 7, 7, 7,
+ 7, 8, 8, 8, 8, 8, 8, 8, 8, 8,
+- 8, 8, 8, 3, 1, 1
++ 8, 8, 8, 8, 3, 1, 4
+ } ;
+
+-static yyconst flex_int16_t yy_base[175] =
++static yyconst flex_int16_t yy_base[180] =
+ { 0,
+- 0, 385, 378, 40, 41, 383, 72, 382, 34, 44,
+- 388, 393, 61, 117, 368, 116, 115, 115, 115, 48,
+- 367, 107, 368, 339, 127, 120, 0, 147, 393, 0,
+- 127, 0, 133, 156, 168, 153, 393, 125, 393, 380,
+- 393, 0, 369, 127, 393, 160, 371, 377, 347, 21,
+- 343, 346, 393, 393, 393, 393, 393, 359, 393, 393,
+- 183, 343, 339, 393, 356, 0, 183, 340, 187, 348,
+- 347, 0, 0, 0, 178, 359, 195, 365, 354, 326,
+- 332, 325, 334, 328, 204, 326, 331, 324, 393, 335,
+- 150, 311, 343, 342, 315, 322, 340, 179, 313, 207,
+-
+- 319, 316, 317, 393, 337, 333, 305, 302, 311, 301,
+- 310, 190, 338, 337, 393, 307, 322, 301, 305, 277,
+- 208, 311, 307, 278, 271, 270, 248, 246, 213, 130,
+- 393, 393, 263, 235, 207, 221, 218, 229, 213, 213,
+- 206, 234, 218, 210, 208, 193, 219, 393, 223, 204,
+- 176, 157, 393, 393, 120, 106, 97, 119, 393, 393,
+- 245, 251, 259, 263, 267, 273, 280, 284, 292, 300,
+- 304, 310, 318, 326
++ 0, 393, 35, 392, 66, 391, 38, 107, 397, 401,
++ 55, 113, 377, 112, 111, 111, 114, 42, 376, 106,
++ 377, 347, 126, 120, 0, 147, 401, 0, 124, 0,
++ 137, 158, 170, 163, 401, 153, 401, 389, 401, 0,
++ 378, 120, 401, 131, 380, 386, 355, 139, 351, 355,
++ 351, 401, 401, 401, 401, 401, 367, 401, 401, 185,
++ 350, 346, 401, 364, 0, 185, 347, 189, 356, 355,
++ 0, 0, 330, 180, 366, 141, 372, 361, 332, 338,
++ 331, 341, 334, 326, 205, 331, 337, 329, 401, 341,
++ 167, 316, 401, 349, 348, 320, 328, 346, 180, 318,
++
++ 324, 209, 324, 320, 322, 342, 338, 309, 306, 315,
++ 305, 315, 312, 192, 342, 341, 401, 293, 306, 282,
++ 268, 252, 255, 203, 285, 282, 272, 268, 252, 233,
++ 232, 239, 208, 107, 401, 401, 238, 211, 401, 211,
++ 212, 208, 228, 203, 215, 207, 233, 222, 212, 211,
++ 203, 227, 401, 237, 225, 204, 185, 401, 401, 149,
++ 128, 88, 42, 401, 401, 253, 259, 267, 271, 275,
++ 281, 288, 292, 300, 308, 312, 318, 326, 334
+ } ;
+
+-static yyconst flex_int16_t yy_def[175] =
++static yyconst flex_int16_t yy_def[180] =
+ { 0,
+- 160, 1, 1, 1, 1, 5, 160, 7, 1, 1,
+- 160, 160, 160, 160, 160, 161, 162, 163, 160, 160,
+- 160, 160, 164, 160, 160, 160, 165, 164, 160, 166,
+- 167, 166, 166, 160, 160, 160, 160, 161, 160, 161,
+- 160, 168, 160, 163, 160, 163, 169, 170, 160, 160,
+- 160, 160, 160, 160, 160, 160, 160, 164, 160, 160,
+- 160, 160, 160, 160, 164, 166, 167, 166, 160, 160,
+- 160, 171, 168, 172, 163, 169, 169, 170, 160, 160,
+- 160, 160, 160, 160, 160, 160, 160, 166, 160, 160,
+- 171, 172, 160, 160, 160, 160, 160, 160, 160, 160,
+-
+- 160, 160, 166, 160, 160, 160, 160, 160, 160, 160,
+- 160, 173, 160, 166, 160, 160, 160, 160, 160, 160,
+- 173, 160, 173, 160, 160, 160, 160, 160, 160, 160,
+- 160, 160, 160, 160, 160, 160, 160, 160, 160, 160,
+- 160, 160, 174, 160, 160, 160, 174, 160, 174, 160,
+- 160, 160, 160, 160, 160, 160, 160, 160, 160, 0,
+- 160, 160, 160, 160, 160, 160, 160, 160, 160, 160,
+- 160, 160, 160, 160
++ 165, 1, 1, 3, 165, 5, 1, 1, 165, 165,
++ 165, 165, 165, 166, 167, 168, 165, 165, 165, 165,
++ 169, 165, 165, 165, 170, 169, 165, 171, 172, 171,
++ 171, 165, 165, 165, 165, 166, 165, 166, 165, 173,
++ 165, 168, 165, 168, 174, 175, 165, 165, 165, 165,
++ 165, 165, 165, 165, 165, 165, 169, 165, 165, 165,
++ 165, 165, 165, 169, 171, 172, 171, 165, 165, 165,
++ 176, 173, 177, 168, 174, 174, 175, 165, 165, 165,
++ 165, 165, 165, 165, 165, 165, 165, 171, 165, 165,
++ 176, 177, 165, 165, 165, 165, 165, 165, 165, 165,
++
++ 165, 165, 165, 165, 171, 165, 165, 165, 165, 165,
++ 165, 165, 165, 178, 165, 171, 165, 165, 165, 165,
++ 165, 165, 165, 178, 165, 178, 165, 165, 165, 165,
++ 165, 165, 165, 165, 165, 165, 165, 165, 165, 165,
++ 165, 165, 165, 165, 165, 165, 165, 179, 165, 165,
++ 165, 179, 165, 179, 165, 165, 165, 165, 165, 165,
++ 165, 165, 165, 165, 0, 165, 165, 165, 165, 165,
++ 165, 165, 165, 165, 165, 165, 165, 165, 165
+ } ;
+
+-static yyconst flex_int16_t yy_nxt[440] =
++static yyconst flex_int16_t yy_nxt[449] =
+ { 0,
+- 12, 13, 14, 13, 15, 16, 12, 17, 18, 12,
+- 12, 12, 19, 12, 12, 12, 12, 20, 21, 22,
+- 23, 23, 23, 23, 23, 12, 12, 23, 23, 23,
+- 23, 23, 23, 23, 23, 23, 23, 23, 23, 23,
+- 23, 23, 23, 12, 24, 12, 25, 34, 35, 35,
+- 25, 81, 26, 26, 27, 27, 27, 34, 35, 35,
+- 82, 28, 36, 36, 36, 53, 54, 29, 28, 28,
+- 28, 28, 12, 13, 14, 13, 15, 16, 30, 17,
+- 18, 30, 30, 30, 26, 30, 30, 30, 12, 20,
+- 21, 22, 31, 31, 31, 31, 31, 32, 12, 31,
+-
+- 31, 31, 31, 31, 31, 31, 31, 31, 31, 31,
+- 31, 31, 31, 31, 31, 12, 24, 12, 36, 36,
+- 36, 39, 41, 45, 47, 56, 57, 48, 61, 47,
+- 39, 159, 48, 66, 61, 45, 66, 66, 66, 158,
+- 46, 40, 49, 59, 50, 157, 51, 49, 52, 50,
+- 40, 63, 46, 52, 36, 36, 36, 156, 43, 62,
+- 65, 65, 65, 59, 136, 68, 137, 65, 75, 69,
+- 69, 69, 70, 71, 65, 65, 65, 65, 70, 71,
+- 72, 69, 69, 69, 61, 46, 45, 155, 154, 66,
+- 70, 71, 66, 66, 66, 122, 85, 85, 85, 59,
+-
+- 69, 69, 69, 46, 77, 100, 109, 93, 100, 70,
+- 71, 110, 112, 122, 129, 123, 153, 85, 85, 85,
+- 135, 135, 135, 148, 148, 160, 135, 135, 135, 152,
+- 142, 142, 142, 123, 143, 142, 142, 142, 151, 143,
+- 150, 146, 145, 149, 149, 38, 38, 38, 38, 38,
+- 38, 38, 38, 42, 144, 141, 140, 42, 42, 44,
+- 44, 44, 44, 44, 44, 44, 44, 58, 58, 58,
+- 58, 64, 139, 64, 66, 138, 134, 66, 133, 66,
+- 66, 67, 132, 131, 67, 67, 67, 67, 73, 130,
+- 73, 73, 76, 76, 76, 76, 76, 76, 76, 76,
+-
+- 78, 78, 78, 78, 78, 78, 78, 78, 91, 160,
+- 91, 92, 129, 92, 92, 128, 92, 92, 121, 121,
+- 121, 121, 121, 121, 121, 121, 147, 147, 147, 147,
+- 147, 147, 147, 147, 127, 126, 125, 124, 61, 61,
+- 120, 119, 118, 117, 116, 115, 47, 114, 110, 113,
+- 111, 108, 107, 106, 48, 105, 104, 89, 103, 102,
+- 101, 99, 98, 97, 96, 95, 94, 79, 77, 90,
+- 89, 88, 59, 87, 86, 59, 84, 83, 80, 79,
+- 77, 74, 160, 60, 59, 55, 37, 160, 33, 25,
+- 26, 25, 11, 160, 160, 160, 160, 160, 160, 160,
+-
+- 160, 160, 160, 160, 160, 160, 160, 160, 160, 160,
+- 160, 160, 160, 160, 160, 160, 160, 160, 160, 160,
+- 160, 160, 160, 160, 160, 160, 160, 160, 160, 160,
+- 160, 160, 160, 160, 160, 160, 160, 160, 160
++ 10, 11, 12, 11, 13, 14, 10, 15, 16, 10,
++ 10, 10, 17, 10, 10, 10, 10, 18, 19, 20,
++ 21, 21, 21, 21, 21, 10, 10, 21, 21, 21,
++ 21, 21, 21, 21, 21, 21, 21, 21, 21, 21,
++ 21, 21, 21, 21, 10, 22, 10, 24, 25, 25,
++ 25, 32, 33, 33, 164, 26, 34, 34, 34, 52,
++ 53, 27, 26, 26, 26, 26, 10, 11, 12, 11,
++ 13, 14, 28, 15, 16, 28, 28, 28, 24, 28,
++ 28, 28, 10, 18, 19, 20, 29, 29, 29, 29,
++ 29, 30, 10, 29, 29, 29, 29, 29, 29, 29,
++
++ 29, 29, 29, 29, 29, 29, 29, 29, 29, 29,
++ 10, 22, 10, 23, 34, 34, 34, 37, 39, 43,
++ 32, 33, 33, 45, 55, 56, 46, 60, 43, 45,
++ 65, 163, 46, 65, 65, 65, 44, 38, 60, 74,
++ 58, 47, 141, 48, 142, 44, 49, 47, 50, 48,
++ 76, 51, 62, 94, 50, 41, 44, 51, 37, 61,
++ 64, 64, 64, 58, 34, 34, 34, 64, 162, 80,
++ 67, 68, 68, 68, 64, 64, 64, 64, 38, 81,
++ 69, 70, 71, 68, 68, 68, 60, 161, 43, 69,
++ 70, 65, 69, 70, 65, 65, 65, 125, 85, 85,
++
++ 85, 58, 68, 68, 68, 44, 102, 110, 125, 133,
++ 102, 69, 70, 111, 114, 160, 159, 126, 85, 85,
++ 85, 140, 140, 140, 140, 140, 140, 153, 126, 147,
++ 147, 147, 153, 148, 147, 147, 147, 158, 148, 165,
++ 157, 156, 155, 151, 150, 149, 146, 154, 145, 144,
++ 143, 139, 154, 36, 36, 36, 36, 36, 36, 36,
++ 36, 40, 138, 137, 136, 40, 40, 42, 42, 42,
++ 42, 42, 42, 42, 42, 57, 57, 57, 57, 63,
++ 135, 63, 65, 134, 165, 65, 133, 65, 65, 66,
++ 132, 131, 66, 66, 66, 66, 72, 130, 72, 72,
++
++ 75, 75, 75, 75, 75, 75, 75, 75, 77, 77,
++ 77, 77, 77, 77, 77, 77, 91, 129, 91, 92,
++ 128, 92, 92, 127, 92, 92, 124, 124, 124, 124,
++ 124, 124, 124, 124, 152, 152, 152, 152, 152, 152,
++ 152, 152, 60, 60, 123, 122, 121, 120, 119, 118,
++ 117, 45, 116, 111, 115, 113, 112, 109, 108, 107,
++ 46, 106, 93, 89, 105, 104, 103, 101, 100, 99,
++ 98, 97, 96, 95, 78, 76, 93, 90, 89, 88,
++ 58, 87, 86, 58, 84, 83, 82, 79, 78, 76,
++ 73, 165, 59, 58, 54, 35, 165, 31, 23, 23,
++
++ 9, 165, 165, 165, 165, 165, 165, 165, 165, 165,
++ 165, 165, 165, 165, 165, 165, 165, 165, 165, 165,
++ 165, 165, 165, 165, 165, 165, 165, 165, 165, 165,
++ 165, 165, 165, 165, 165, 165, 165, 165, 165, 165,
++ 165, 165, 165, 165, 165, 165, 165, 165
+ } ;
+
+-static yyconst flex_int16_t yy_chk[440] =
++static yyconst flex_int16_t yy_chk[449] =
+ { 0,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+- 1, 1, 1, 1, 1, 1, 4, 9, 9, 9,
+- 10, 50, 4, 5, 5, 5, 5, 10, 10, 10,
+- 50, 5, 13, 13, 13, 20, 20, 5, 5, 5,
+- 5, 5, 7, 7, 7, 7, 7, 7, 7, 7,
+- 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
+- 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
+-
+- 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
+- 7, 7, 7, 7, 7, 7, 7, 7, 14, 14,
+- 14, 16, 17, 18, 19, 22, 22, 19, 25, 26,
+- 38, 158, 26, 31, 33, 44, 31, 31, 31, 157,
+- 18, 16, 19, 31, 19, 156, 19, 26, 19, 26,
+- 38, 26, 44, 26, 36, 36, 36, 155, 17, 25,
+- 28, 28, 28, 28, 130, 33, 130, 28, 46, 34,
+- 34, 34, 91, 91, 28, 28, 28, 28, 34, 34,
+- 34, 35, 35, 35, 61, 46, 75, 152, 151, 67,
+- 35, 35, 67, 67, 67, 112, 61, 61, 61, 67,
+-
+- 69, 69, 69, 75, 77, 85, 98, 77, 100, 69,
+- 69, 98, 100, 121, 129, 112, 150, 85, 85, 85,
+- 135, 135, 135, 143, 147, 149, 129, 129, 129, 146,
+- 138, 138, 138, 121, 138, 142, 142, 142, 145, 142,
+- 144, 141, 140, 143, 147, 161, 161, 161, 161, 161,
+- 161, 161, 161, 162, 139, 137, 136, 162, 162, 163,
+- 163, 163, 163, 163, 163, 163, 163, 164, 164, 164,
+- 164, 165, 134, 165, 166, 133, 128, 166, 127, 166,
+- 166, 167, 126, 125, 167, 167, 167, 167, 168, 124,
+- 168, 168, 169, 169, 169, 169, 169, 169, 169, 169,
+-
+- 170, 170, 170, 170, 170, 170, 170, 170, 171, 123,
+- 171, 172, 122, 172, 172, 120, 172, 172, 173, 173,
+- 173, 173, 173, 173, 173, 173, 174, 174, 174, 174,
+- 174, 174, 174, 174, 119, 118, 117, 116, 114, 113,
+- 111, 110, 109, 108, 107, 106, 105, 103, 102, 101,
+- 99, 97, 96, 95, 94, 93, 92, 90, 88, 87,
+- 86, 84, 83, 82, 81, 80, 79, 78, 76, 71,
+- 70, 68, 65, 63, 62, 58, 52, 51, 49, 48,
+- 47, 43, 40, 24, 23, 21, 15, 11, 8, 6,
+- 3, 2, 160, 160, 160, 160, 160, 160, 160, 160,
+-
+- 160, 160, 160, 160, 160, 160, 160, 160, 160, 160,
+- 160, 160, 160, 160, 160, 160, 160, 160, 160, 160,
+- 160, 160, 160, 160, 160, 160, 160, 160, 160, 160,
+- 160, 160, 160, 160, 160, 160, 160, 160, 160
++ 1, 1, 1, 1, 1, 1, 1, 3, 3, 3,
++ 3, 7, 7, 7, 163, 3, 11, 11, 11, 18,
++ 18, 3, 3, 3, 3, 3, 5, 5, 5, 5,
++ 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
++ 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
++ 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
++
++ 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
++ 5, 5, 5, 8, 12, 12, 12, 14, 15, 16,
++ 8, 8, 8, 17, 20, 20, 17, 23, 42, 24,
++ 29, 162, 24, 29, 29, 29, 16, 14, 31, 44,
++ 29, 17, 134, 17, 134, 42, 17, 24, 17, 24,
++ 76, 17, 24, 76, 24, 15, 44, 24, 36, 23,
++ 26, 26, 26, 26, 34, 34, 34, 26, 161, 48,
++ 31, 32, 32, 32, 26, 26, 26, 26, 36, 48,
++ 32, 32, 32, 33, 33, 33, 60, 160, 74, 91,
++ 91, 66, 33, 33, 66, 66, 66, 114, 60, 60,
++
++ 60, 66, 68, 68, 68, 74, 85, 99, 124, 133,
++ 102, 68, 68, 99, 102, 157, 156, 114, 85, 85,
++ 85, 133, 133, 133, 140, 140, 140, 148, 124, 143,
++ 143, 143, 152, 143, 147, 147, 147, 155, 147, 154,
++ 151, 150, 149, 146, 145, 144, 142, 148, 141, 138,
++ 137, 132, 152, 166, 166, 166, 166, 166, 166, 166,
++ 166, 167, 131, 130, 129, 167, 167, 168, 168, 168,
++ 168, 168, 168, 168, 168, 169, 169, 169, 169, 170,
++ 128, 170, 171, 127, 126, 171, 125, 171, 171, 172,
++ 123, 122, 172, 172, 172, 172, 173, 121, 173, 173,
++
++ 174, 174, 174, 174, 174, 174, 174, 174, 175, 175,
++ 175, 175, 175, 175, 175, 175, 176, 120, 176, 177,
++ 119, 177, 177, 118, 177, 177, 178, 178, 178, 178,
++ 178, 178, 178, 178, 179, 179, 179, 179, 179, 179,
++ 179, 179, 116, 115, 113, 112, 111, 110, 109, 108,
++ 107, 106, 105, 104, 103, 101, 100, 98, 97, 96,
++ 95, 94, 92, 90, 88, 87, 86, 84, 83, 82,
++ 81, 80, 79, 78, 77, 75, 73, 70, 69, 67,
++ 64, 62, 61, 57, 51, 50, 49, 47, 46, 45,
++ 41, 38, 22, 21, 19, 13, 9, 6, 4, 2,
++
++ 165, 165, 165, 165, 165, 165, 165, 165, 165, 165,
++ 165, 165, 165, 165, 165, 165, 165, 165, 165, 165,
++ 165, 165, 165, 165, 165, 165, 165, 165, 165, 165,
++ 165, 165, 165, 165, 165, 165, 165, 165, 165, 165,
++ 165, 165, 165, 165, 165, 165, 165, 165
+ } ;
+
+ static yy_state_type yy_last_accepting_state;
+@@ -631,13 +634,13 @@
+
+
+
+-
+-#line 38 "dtc-lexer.l"
++#line 37 "dtc-lexer.l"
+ #include "dtc.h"
+ #include "srcpos.h"
+ #include "dtc-parser.tab.h"
+
+ YYLTYPE yylloc;
++extern bool treesource_error;
+
+ /* CAUTION: this will stop working if we ever use yyless() or yyunput() */
+ #define YY_USER_ACTION \
+@@ -659,14 +662,14 @@
+ BEGIN(V1); \
+
+ static void push_input_file(const char *filename);
+-static int pop_input_file(void);
+-#line 664 "dtc-lexer.lex.c"
++static bool pop_input_file(void);
++static void lexical_error(const char *fmt, ...);
++#line 668 "dtc-lexer.lex.c"
+
+ #define INITIAL 0
+-#define INCLUDE 1
+-#define BYTESTRING 2
+-#define PROPNODENAME 3
+-#define V1 4
++#define BYTESTRING 1
++#define PROPNODENAME 2
++#define V1 3
+
+ #ifndef YY_NO_UNISTD_H
+ /* Special case for "unistd.h", since it is non-ANSI. We include it way
+@@ -852,9 +855,9 @@
+ register char *yy_cp, *yy_bp;
+ register int yy_act;
+
+-#line 67 "dtc-lexer.l"
++#line 68 "dtc-lexer.l"
+
+-#line 858 "dtc-lexer.lex.c"
++#line 861 "dtc-lexer.lex.c"
+
+ if ( !(yy_init) )
+ {
+@@ -908,13 +911,13 @@
+ while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state )
+ {
+ yy_current_state = (int) yy_def[yy_current_state];
+- if ( yy_current_state >= 161 )
++ if ( yy_current_state >= 166 )
+ yy_c = yy_meta[(unsigned int) yy_c];
+ }
+ yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c];
+ ++yy_cp;
+ }
+- while ( yy_current_state != 160 );
++ while ( yy_current_state != 165 );
+ yy_cp = (yy_last_accepting_cpos);
+ yy_current_state = (yy_last_accepting_state);
+
+@@ -937,7 +940,7 @@
+ case 1:
+ /* rule 1 can match eol */
+ YY_RULE_SETUP
+-#line 68 "dtc-lexer.l"
++#line 69 "dtc-lexer.l"
+ {
+ char *name = strchr(yytext, '\"') + 1;
+ yytext[yyleng-1] = '\0';
+@@ -947,16 +950,16 @@
+ case 2:
+ /* rule 2 can match eol */
+ YY_RULE_SETUP
+-#line 74 "dtc-lexer.l"
++#line 75 "dtc-lexer.l"
+ {
+ char *line, *tmp, *fn;
+ /* skip text before line # */
+ line = yytext;
+- while (!isdigit(*line))
++ while (!isdigit((unsigned char)*line))
+ line++;
+ /* skip digits in line # */
+ tmp = line;
+- while (!isspace(*tmp))
++ while (!isspace((unsigned char)*tmp))
+ tmp++;
+ /* "NULL"-terminate line # */
+ *tmp = '\0';
+@@ -970,11 +973,10 @@
+ }
+ YY_BREAK
+ case YY_STATE_EOF(INITIAL):
+-case YY_STATE_EOF(INCLUDE):
+ case YY_STATE_EOF(BYTESTRING):
+ case YY_STATE_EOF(PROPNODENAME):
+ case YY_STATE_EOF(V1):
+-#line 95 "dtc-lexer.l"
++#line 96 "dtc-lexer.l"
+ {
+ if (!pop_input_file()) {
+ yyterminate();
+@@ -984,7 +986,7 @@
+ case 3:
+ /* rule 3 can match eol */
+ YY_RULE_SETUP
+-#line 101 "dtc-lexer.l"
++#line 102 "dtc-lexer.l"
+ {
+ DPRINT("String: %s\n", yytext);
+ yylval.data = data_copy_escape_string(yytext+1,
+@@ -994,7 +996,7 @@
+ YY_BREAK
+ case 4:
+ YY_RULE_SETUP
+-#line 108 "dtc-lexer.l"
++#line 109 "dtc-lexer.l"
+ {
+ DPRINT("Keyword: /dts-v1/\n");
+ dts_version = 1;
+@@ -1004,25 +1006,33 @@
+ YY_BREAK
+ case 5:
+ YY_RULE_SETUP
+-#line 115 "dtc-lexer.l"
++#line 116 "dtc-lexer.l"
++{
++ DPRINT("Keyword: /plugin/\n");
++ return DT_PLUGIN;
++ }
++ YY_BREAK
++case 6:
++YY_RULE_SETUP
++#line 121 "dtc-lexer.l"
+ {
+ DPRINT("Keyword: /memreserve/\n");
+ BEGIN_DEFAULT();
+ return DT_MEMRESERVE;
+ }
+ YY_BREAK
+-case 6:
++case 7:
+ YY_RULE_SETUP
+-#line 121 "dtc-lexer.l"
++#line 127 "dtc-lexer.l"
+ {
+ DPRINT("Keyword: /bits/\n");
+ BEGIN_DEFAULT();
+ return DT_BITS;
+ }
+ YY_BREAK
+-case 7:
++case 8:
+ YY_RULE_SETUP
+-#line 127 "dtc-lexer.l"
++#line 133 "dtc-lexer.l"
+ {
+ DPRINT("Keyword: /delete-property/\n");
+ DPRINT("<PROPNODENAME>\n");
+@@ -1030,9 +1040,9 @@
+ return DT_DEL_PROP;
+ }
+ YY_BREAK
+-case 8:
++case 9:
+ YY_RULE_SETUP
+-#line 134 "dtc-lexer.l"
++#line 140 "dtc-lexer.l"
+ {
+ DPRINT("Keyword: /delete-node/\n");
+ DPRINT("<PROPNODENAME>\n");
+@@ -1040,9 +1050,9 @@
+ return DT_DEL_NODE;
+ }
+ YY_BREAK
+-case 9:
++case 10:
+ YY_RULE_SETUP
+-#line 141 "dtc-lexer.l"
++#line 147 "dtc-lexer.l"
+ {
+ DPRINT("Label: %s\n", yytext);
+ yylval.labelref = xstrdup(yytext);
+@@ -1050,38 +1060,65 @@
+ return DT_LABEL;
+ }
+ YY_BREAK
+-case 10:
++case 11:
+ YY_RULE_SETUP
+-#line 148 "dtc-lexer.l"
++#line 154 "dtc-lexer.l"
+ {
+- yylval.literal = xstrdup(yytext);
+- DPRINT("Literal: '%s'\n", yylval.literal);
++ char *e;
++ DPRINT("Integer Literal: '%s'\n", yytext);
++
++ errno = 0;
++ yylval.integer = strtoull(yytext, &e, 0);
++
++ assert(!(*e) || !e[strspn(e, "UL")]);
++
++ if (errno == ERANGE)
++ lexical_error("Integer literal '%s' out of range",
++ yytext);
++ else
++ /* ERANGE is the only strtoull error triggerable
++ * by strings matching the pattern */
++ assert(errno == 0);
+ return DT_LITERAL;
+ }
+ YY_BREAK
+-case 11:
+-/* rule 11 can match eol */
++case 12:
++/* rule 12 can match eol */
+ YY_RULE_SETUP
+-#line 154 "dtc-lexer.l"
++#line 173 "dtc-lexer.l"
+ {
+- yytext[yyleng-1] = '\0';
+- yylval.literal = xstrdup(yytext+1);
+- DPRINT("Character literal: %s\n", yylval.literal);
++ struct data d;
++ DPRINT("Character literal: %s\n", yytext);
++
++ d = data_copy_escape_string(yytext+1, yyleng-2);
++ if (d.len == 1) {
++ lexical_error("Empty character literal");
++ yylval.integer = 0;
++ return DT_CHAR_LITERAL;
++ }
++
++ yylval.integer = (unsigned char)d.val[0];
++
++ if (d.len > 2)
++ lexical_error("Character literal has %d"
++ " characters instead of 1",
++ d.len - 1);
++
+ return DT_CHAR_LITERAL;
+ }
+ YY_BREAK
+-case 12:
++case 13:
+ YY_RULE_SETUP
+-#line 161 "dtc-lexer.l"
++#line 194 "dtc-lexer.l"
+ { /* label reference */
+ DPRINT("Ref: %s\n", yytext+1);
+ yylval.labelref = xstrdup(yytext+1);
+ return DT_REF;
+ }
+ YY_BREAK
+-case 13:
++case 14:
+ YY_RULE_SETUP
+-#line 167 "dtc-lexer.l"
++#line 200 "dtc-lexer.l"
+ { /* new-style path reference */
+ yytext[yyleng-1] = '\0';
+ DPRINT("Ref: %s\n", yytext+2);
+@@ -1089,27 +1126,27 @@
+ return DT_REF;
+ }
+ YY_BREAK
+-case 14:
++case 15:
+ YY_RULE_SETUP
+-#line 174 "dtc-lexer.l"
++#line 207 "dtc-lexer.l"
+ {
+ yylval.byte = strtol(yytext, NULL, 16);
+ DPRINT("Byte: %02x\n", (int)yylval.byte);
+ return DT_BYTE;
+ }
+ YY_BREAK
+-case 15:
++case 16:
+ YY_RULE_SETUP
+-#line 180 "dtc-lexer.l"
++#line 213 "dtc-lexer.l"
+ {
+ DPRINT("/BYTESTRING\n");
+ BEGIN_DEFAULT();
+ return ']';
+ }
+ YY_BREAK
+-case 16:
++case 17:
+ YY_RULE_SETUP
+-#line 186 "dtc-lexer.l"
++#line 219 "dtc-lexer.l"
+ {
+ DPRINT("PropNodeName: %s\n", yytext);
+ yylval.propnodename = xstrdup((yytext[0] == '\\') ?
+@@ -1118,75 +1155,75 @@
+ return DT_PROPNODENAME;
+ }
+ YY_BREAK
+-case 17:
++case 18:
+ YY_RULE_SETUP
+-#line 194 "dtc-lexer.l"
++#line 227 "dtc-lexer.l"
+ {
+ DPRINT("Binary Include\n");
+ return DT_INCBIN;
+ }
+ YY_BREAK
+-case 18:
+-/* rule 18 can match eol */
+-YY_RULE_SETUP
+-#line 199 "dtc-lexer.l"
+-/* eat whitespace */
+- YY_BREAK
+ case 19:
+ /* rule 19 can match eol */
+ YY_RULE_SETUP
+-#line 200 "dtc-lexer.l"
+-/* eat C-style comments */
++#line 232 "dtc-lexer.l"
++/* eat whitespace */
+ YY_BREAK
+ case 20:
+ /* rule 20 can match eol */
+ YY_RULE_SETUP
+-#line 201 "dtc-lexer.l"
+-/* eat C++-style comments */
++#line 233 "dtc-lexer.l"
++/* eat C-style comments */
+ YY_BREAK
+ case 21:
++/* rule 21 can match eol */
+ YY_RULE_SETUP
+-#line 203 "dtc-lexer.l"
+-{ return DT_LSHIFT; };
++#line 234 "dtc-lexer.l"
++/* eat C++-style comments */
+ YY_BREAK
+ case 22:
+ YY_RULE_SETUP
+-#line 204 "dtc-lexer.l"
+-{ return DT_RSHIFT; };
++#line 236 "dtc-lexer.l"
++{ return DT_LSHIFT; };
+ YY_BREAK
+ case 23:
+ YY_RULE_SETUP
+-#line 205 "dtc-lexer.l"
+-{ return DT_LE; };
++#line 237 "dtc-lexer.l"
++{ return DT_RSHIFT; };
+ YY_BREAK
+ case 24:
+ YY_RULE_SETUP
+-#line 206 "dtc-lexer.l"
+-{ return DT_GE; };
++#line 238 "dtc-lexer.l"
++{ return DT_LE; };
+ YY_BREAK
+ case 25:
+ YY_RULE_SETUP
+-#line 207 "dtc-lexer.l"
+-{ return DT_EQ; };
++#line 239 "dtc-lexer.l"
++{ return DT_GE; };
+ YY_BREAK
+ case 26:
+ YY_RULE_SETUP
+-#line 208 "dtc-lexer.l"
+-{ return DT_NE; };
++#line 240 "dtc-lexer.l"
++{ return DT_EQ; };
+ YY_BREAK
+ case 27:
+ YY_RULE_SETUP
+-#line 209 "dtc-lexer.l"
+-{ return DT_AND; };
++#line 241 "dtc-lexer.l"
++{ return DT_NE; };
+ YY_BREAK
+ case 28:
+ YY_RULE_SETUP
+-#line 210 "dtc-lexer.l"
+-{ return DT_OR; };
++#line 242 "dtc-lexer.l"
++{ return DT_AND; };
+ YY_BREAK
+ case 29:
+ YY_RULE_SETUP
+-#line 212 "dtc-lexer.l"
++#line 243 "dtc-lexer.l"
++{ return DT_OR; };
++ YY_BREAK
++case 30:
++YY_RULE_SETUP
++#line 245 "dtc-lexer.l"
+ {
+ DPRINT("Char: %c (\\x%02x)\n", yytext[0],
+ (unsigned)yytext[0]);
+@@ -1202,12 +1239,12 @@
+ return yytext[0];
+ }
+ YY_BREAK
+-case 30:
++case 31:
+ YY_RULE_SETUP
+-#line 227 "dtc-lexer.l"
++#line 260 "dtc-lexer.l"
+ ECHO;
+ YY_BREAK
+-#line 1211 "dtc-lexer.lex.c"
++#line 1248 "dtc-lexer.lex.c"
+
+ case YY_END_OF_BUFFER:
+ {
+@@ -1499,7 +1536,7 @@
+ while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state )
+ {
+ yy_current_state = (int) yy_def[yy_current_state];
+- if ( yy_current_state >= 161 )
++ if ( yy_current_state >= 166 )
+ yy_c = yy_meta[(unsigned int) yy_c];
+ }
+ yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c];
+@@ -1527,11 +1564,11 @@
+ while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state )
+ {
+ yy_current_state = (int) yy_def[yy_current_state];
+- if ( yy_current_state >= 161 )
++ if ( yy_current_state >= 166 )
+ yy_c = yy_meta[(unsigned int) yy_c];
+ }
+ yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c];
+- yy_is_jam = (yy_current_state == 160);
++ yy_is_jam = (yy_current_state == 165);
+
+ return yy_is_jam ? 0 : yy_current_state;
+ }
+@@ -2166,7 +2203,7 @@
+
+ #define YYTABLES_NAME "yytables"
+
+-#line 227 "dtc-lexer.l"
++#line 260 "dtc-lexer.l"
+
+
+
+@@ -2182,14 +2219,25 @@
+ }
+
+
+-static int pop_input_file(void)
++static bool pop_input_file(void)
+ {
+ if (srcfile_pop() == 0)
+- return 0;
++ return false;
+
+ yypop_buffer_state();
+ yyin = current_srcfile->f;
+
+- return 1;
++ return true;
++}
++
++static void lexical_error(const char *fmt, ...)
++{
++ va_list ap;
++
++ va_start(ap, fmt);
++ srcpos_verror(&yylloc, "Lexical error", fmt, ap);
++ va_end(ap);
++
++ treesource_error = true;
+ }
+
+diff -Nur linux-4.1.3/scripts/dtc/dtc-parser.tab.c_shipped linux-xbian-rpi/scripts/dtc/dtc-parser.tab.c_shipped
+--- linux-4.1.3/scripts/dtc/dtc-parser.tab.c_shipped 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/scripts/dtc/dtc-parser.tab.c_shipped 2015-07-28 01:20:58.461099590 +0200
+@@ -1,19 +1,19 @@
+-/* A Bison parser, made by GNU Bison 2.7.12-4996. */
++/* A Bison parser, made by GNU Bison 3.0.2. */
+
+ /* Bison implementation for Yacc-like parsers in C
+-
+- Copyright (C) 1984, 1989-1990, 2000-2013 Free Software Foundation, Inc.
+-
++
++ Copyright (C) 1984, 1989-1990, 2000-2013 Free Software Foundation, Inc.
++
+ This program is free software: you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation, either version 3 of the License, or
+ (at your option) any later version.
+-
++
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+-
++
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+@@ -26,7 +26,7 @@
+ special exception, which will cause the skeleton and the resulting
+ Bison output files to be licensed under the GNU General Public
+ License without this special exception.
+-
++
+ This special exception was added by the Free Software Foundation in
+ version 2.2 of Bison. */
+
+@@ -44,7 +44,7 @@
+ #define YYBISON 1
+
+ /* Bison version. */
+-#define YYBISON_VERSION "2.7.12-4996"
++#define YYBISON_VERSION "3.0.2"
+
+ /* Skeleton name. */
+ #define YYSKELETON_NAME "yacc.c"
+@@ -62,34 +62,32 @@
+
+
+ /* Copy the first part of user declarations. */
+-/* Line 371 of yacc.c */
+-#line 21 "dtc-parser.y"
++#line 20 "dtc-parser.y" /* yacc.c:339 */
+
+ #include <stdio.h>
++#include <inttypes.h>
+
+ #include "dtc.h"
+ #include "srcpos.h"
+
+-YYLTYPE yylloc;
+-
+ extern int yylex(void);
+-extern void print_error(char const *fmt, ...);
+ extern void yyerror(char const *s);
++#define ERROR(loc, ...) \
++ do { \
++ srcpos_error((loc), "Error", __VA_ARGS__); \
++ treesource_error = true; \
++ } while (0)
+
+ extern struct boot_info *the_boot_info;
+-extern int treesource_error;
+-
+-static unsigned long long eval_literal(const char *s, int base, int bits);
+-static unsigned char eval_char_literal(const char *s);
++extern bool treesource_error;
+
+-/* Line 371 of yacc.c */
+-#line 87 "dtc-parser.tab.c"
++#line 85 "dtc-parser.tab.c" /* yacc.c:339 */
+
+-# ifndef YY_NULL
++# ifndef YY_NULLPTR
+ # if defined __cplusplus && 201103L <= __cplusplus
+-# define YY_NULL nullptr
++# define YY_NULLPTR nullptr
+ # else
+-# define YY_NULL 0
++# define YY_NULLPTR 0
+ # endif
+ # endif
+
+@@ -105,7 +103,7 @@
+ by #include "dtc-parser.tab.h". */
+ #ifndef YY_YY_DTC_PARSER_TAB_H_INCLUDED
+ # define YY_YY_DTC_PARSER_TAB_H_INCLUDED
+-/* Enabling traces. */
++/* Debug traces. */
+ #ifndef YYDEBUG
+ # define YYDEBUG 0
+ #endif
+@@ -113,48 +111,45 @@
+ extern int yydebug;
+ #endif
+
+-/* Tokens. */
++/* Token type. */
+ #ifndef YYTOKENTYPE
+ # define YYTOKENTYPE
+- /* Put the tokens into the symbol table, so that GDB and other debuggers
+- know about them. */
+- enum yytokentype {
+- DT_V1 = 258,
+- DT_MEMRESERVE = 259,
+- DT_LSHIFT = 260,
+- DT_RSHIFT = 261,
+- DT_LE = 262,
+- DT_GE = 263,
+- DT_EQ = 264,
+- DT_NE = 265,
+- DT_AND = 266,
+- DT_OR = 267,
+- DT_BITS = 268,
+- DT_DEL_PROP = 269,
+- DT_DEL_NODE = 270,
+- DT_PROPNODENAME = 271,
+- DT_LITERAL = 272,
+- DT_CHAR_LITERAL = 273,
+- DT_BASE = 274,
+- DT_BYTE = 275,
+- DT_STRING = 276,
+- DT_LABEL = 277,
+- DT_REF = 278,
+- DT_INCBIN = 279
+- };
++ enum yytokentype
++ {
++ DT_V1 = 258,
++ DT_PLUGIN = 259,
++ DT_MEMRESERVE = 260,
++ DT_LSHIFT = 261,
++ DT_RSHIFT = 262,
++ DT_LE = 263,
++ DT_GE = 264,
++ DT_EQ = 265,
++ DT_NE = 266,
++ DT_AND = 267,
++ DT_OR = 268,
++ DT_BITS = 269,
++ DT_DEL_PROP = 270,
++ DT_DEL_NODE = 271,
++ DT_PROPNODENAME = 272,
++ DT_LITERAL = 273,
++ DT_CHAR_LITERAL = 274,
++ DT_BYTE = 275,
++ DT_STRING = 276,
++ DT_LABEL = 277,
++ DT_REF = 278,
++ DT_INCBIN = 279
++ };
+ #endif
+
+-
++/* Value type. */
+ #if ! defined YYSTYPE && ! defined YYSTYPE_IS_DECLARED
+-typedef union YYSTYPE
++typedef union YYSTYPE YYSTYPE;
++union YYSTYPE
+ {
+-/* Line 387 of yacc.c */
+-#line 40 "dtc-parser.y"
++#line 39 "dtc-parser.y" /* yacc.c:355 */
+
+ char *propnodename;
+- char *literal;
+ char *labelref;
+- unsigned int cbase;
+ uint8_t byte;
+ struct data data;
+
+@@ -169,38 +164,38 @@
+ struct node *nodelist;
+ struct reserve_info *re;
+ uint64_t integer;
++ int is_plugin;
+
+-
+-/* Line 387 of yacc.c */
+-#line 176 "dtc-parser.tab.c"
+-} YYSTYPE;
++#line 170 "dtc-parser.tab.c" /* yacc.c:355 */
++};
+ # define YYSTYPE_IS_TRIVIAL 1
+-# define yystype YYSTYPE /* obsolescent; will be withdrawn */
+ # define YYSTYPE_IS_DECLARED 1
+ #endif
+
+-extern YYSTYPE yylval;
+-
+-#ifdef YYPARSE_PARAM
+-#if defined __STDC__ || defined __cplusplus
+-int yyparse (void *YYPARSE_PARAM);
+-#else
+-int yyparse ();
++/* Location type. */
++#if ! defined YYLTYPE && ! defined YYLTYPE_IS_DECLARED
++typedef struct YYLTYPE YYLTYPE;
++struct YYLTYPE
++{
++ int first_line;
++ int first_column;
++ int last_line;
++ int last_column;
++};
++# define YYLTYPE_IS_DECLARED 1
++# define YYLTYPE_IS_TRIVIAL 1
+ #endif
+-#else /* ! YYPARSE_PARAM */
+-#if defined __STDC__ || defined __cplusplus
++
++
++extern YYSTYPE yylval;
++extern YYLTYPE yylloc;
+ int yyparse (void);
+-#else
+-int yyparse ();
+-#endif
+-#endif /* ! YYPARSE_PARAM */
+
+ #endif /* !YY_YY_DTC_PARSER_TAB_H_INCLUDED */
+
+ /* Copy the second part of user declarations. */
+
+-/* Line 390 of yacc.c */
+-#line 204 "dtc-parser.tab.c"
++#line 199 "dtc-parser.tab.c" /* yacc.c:358 */
+
+ #ifdef short
+ # undef short
+@@ -214,11 +209,8 @@
+
+ #ifdef YYTYPE_INT8
+ typedef YYTYPE_INT8 yytype_int8;
+-#elif (defined __STDC__ || defined __C99__FUNC__ \
+- || defined __cplusplus || defined _MSC_VER)
+-typedef signed char yytype_int8;
+ #else
+-typedef short int yytype_int8;
++typedef signed char yytype_int8;
+ #endif
+
+ #ifdef YYTYPE_UINT16
+@@ -238,8 +230,7 @@
+ # define YYSIZE_T __SIZE_TYPE__
+ # elif defined size_t
+ # define YYSIZE_T size_t
+-# elif ! defined YYSIZE_T && (defined __STDC__ || defined __C99__FUNC__ \
+- || defined __cplusplus || defined _MSC_VER)
++# elif ! defined YYSIZE_T
+ # include <stddef.h> /* INFRINGES ON USER NAME SPACE */
+ # define YYSIZE_T size_t
+ # else
+@@ -261,11 +252,30 @@
+ # endif
+ #endif
+
+-#ifndef __attribute__
+-/* This feature is available in gcc versions 2.5 and later. */
+-# if (! defined __GNUC__ || __GNUC__ < 2 \
+- || (__GNUC__ == 2 && __GNUC_MINOR__ < 5))
+-# define __attribute__(Spec) /* empty */
++#ifndef YY_ATTRIBUTE
++# if (defined __GNUC__ \
++ && (2 < __GNUC__ || (__GNUC__ == 2 && 96 <= __GNUC_MINOR__))) \
++ || defined __SUNPRO_C && 0x5110 <= __SUNPRO_C
++# define YY_ATTRIBUTE(Spec) __attribute__(Spec)
++# else
++# define YY_ATTRIBUTE(Spec) /* empty */
++# endif
++#endif
++
++#ifndef YY_ATTRIBUTE_PURE
++# define YY_ATTRIBUTE_PURE YY_ATTRIBUTE ((__pure__))
++#endif
++
++#ifndef YY_ATTRIBUTE_UNUSED
++# define YY_ATTRIBUTE_UNUSED YY_ATTRIBUTE ((__unused__))
++#endif
++
++#if !defined _Noreturn \
++ && (!defined __STDC_VERSION__ || __STDC_VERSION__ < 201112)
++# if defined _MSC_VER && 1200 <= _MSC_VER
++# define _Noreturn __declspec (noreturn)
++# else
++# define _Noreturn YY_ATTRIBUTE ((__noreturn__))
+ # endif
+ #endif
+
+@@ -276,24 +286,25 @@
+ # define YYUSE(E) /* empty */
+ #endif
+
+-
+-/* Identity function, used to suppress warnings about constant conditions. */
+-#ifndef lint
+-# define YYID(N) (N)
+-#else
+-#if (defined __STDC__ || defined __C99__FUNC__ \
+- || defined __cplusplus || defined _MSC_VER)
+-static int
+-YYID (int yyi)
++#if defined __GNUC__ && 407 <= __GNUC__ * 100 + __GNUC_MINOR__
++/* Suppress an incorrect diagnostic about yylval being uninitialized. */
++# define YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN \
++ _Pragma ("GCC diagnostic push") \
++ _Pragma ("GCC diagnostic ignored \"-Wuninitialized\"")\
++ _Pragma ("GCC diagnostic ignored \"-Wmaybe-uninitialized\"")
++# define YY_IGNORE_MAYBE_UNINITIALIZED_END \
++ _Pragma ("GCC diagnostic pop")
+ #else
+-static int
+-YYID (yyi)
+- int yyi;
++# define YY_INITIAL_VALUE(Value) Value
+ #endif
+-{
+- return yyi;
+-}
++#ifndef YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN
++# define YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN
++# define YY_IGNORE_MAYBE_UNINITIALIZED_END
+ #endif
++#ifndef YY_INITIAL_VALUE
++# define YY_INITIAL_VALUE(Value) /* Nothing. */
++#endif
++
+
+ #if ! defined yyoverflow || YYERROR_VERBOSE
+
+@@ -312,8 +323,7 @@
+ # define alloca _alloca
+ # else
+ # define YYSTACK_ALLOC alloca
+-# if ! defined _ALLOCA_H && ! defined EXIT_SUCCESS && (defined __STDC__ || defined __C99__FUNC__ \
+- || defined __cplusplus || defined _MSC_VER)
++# if ! defined _ALLOCA_H && ! defined EXIT_SUCCESS
+ # include <stdlib.h> /* INFRINGES ON USER NAME SPACE */
+ /* Use EXIT_SUCCESS as a witness for stdlib.h. */
+ # ifndef EXIT_SUCCESS
+@@ -325,8 +335,8 @@
+ # endif
+
+ # ifdef YYSTACK_ALLOC
+- /* Pacify GCC's `empty if-body' warning. */
+-# define YYSTACK_FREE(Ptr) do { /* empty */; } while (YYID (0))
++ /* Pacify GCC's 'empty if-body' warning. */
++# define YYSTACK_FREE(Ptr) do { /* empty */; } while (0)
+ # ifndef YYSTACK_ALLOC_MAXIMUM
+ /* The OS might guarantee only one guard page at the bottom of the stack,
+ and a page size can be as small as 4096 bytes. So we cannot safely
+@@ -342,7 +352,7 @@
+ # endif
+ # if (defined __cplusplus && ! defined EXIT_SUCCESS \
+ && ! ((defined YYMALLOC || defined malloc) \
+- && (defined YYFREE || defined free)))
++ && (defined YYFREE || defined free)))
+ # include <stdlib.h> /* INFRINGES ON USER NAME SPACE */
+ # ifndef EXIT_SUCCESS
+ # define EXIT_SUCCESS 0
+@@ -350,15 +360,13 @@
+ # endif
+ # ifndef YYMALLOC
+ # define YYMALLOC malloc
+-# if ! defined malloc && ! defined EXIT_SUCCESS && (defined __STDC__ || defined __C99__FUNC__ \
+- || defined __cplusplus || defined _MSC_VER)
++# if ! defined malloc && ! defined EXIT_SUCCESS
+ void *malloc (YYSIZE_T); /* INFRINGES ON USER NAME SPACE */
+ # endif
+ # endif
+ # ifndef YYFREE
+ # define YYFREE free
+-# if ! defined free && ! defined EXIT_SUCCESS && (defined __STDC__ || defined __C99__FUNC__ \
+- || defined __cplusplus || defined _MSC_VER)
++# if ! defined free && ! defined EXIT_SUCCESS
+ void free (void *); /* INFRINGES ON USER NAME SPACE */
+ # endif
+ # endif
+@@ -368,13 +376,15 @@
+
+ #if (! defined yyoverflow \
+ && (! defined __cplusplus \
+- || (defined YYSTYPE_IS_TRIVIAL && YYSTYPE_IS_TRIVIAL)))
++ || (defined YYLTYPE_IS_TRIVIAL && YYLTYPE_IS_TRIVIAL \
++ && defined YYSTYPE_IS_TRIVIAL && YYSTYPE_IS_TRIVIAL)))
+
+ /* A type that is properly aligned for any stack member. */
+ union yyalloc
+ {
+ yytype_int16 yyss_alloc;
+ YYSTYPE yyvs_alloc;
++ YYLTYPE yyls_alloc;
+ };
+
+ /* The size of the maximum gap between one aligned stack and the next. */
+@@ -383,8 +393,8 @@
+ /* The size of an array large to enough to hold all stacks, each with
+ N elements. */
+ # define YYSTACK_BYTES(N) \
+- ((N) * (sizeof (yytype_int16) + sizeof (YYSTYPE)) \
+- + YYSTACK_GAP_MAXIMUM)
++ ((N) * (sizeof (yytype_int16) + sizeof (YYSTYPE) + sizeof (YYLTYPE)) \
++ + 2 * YYSTACK_GAP_MAXIMUM)
+
+ # define YYCOPY_NEEDED 1
+
+@@ -393,16 +403,16 @@
+ elements in the stack, and YYPTR gives the new location of the
+ stack. Advance YYPTR to a properly aligned location for the next
+ stack. */
+-# define YYSTACK_RELOCATE(Stack_alloc, Stack) \
+- do \
+- { \
+- YYSIZE_T yynewbytes; \
+- YYCOPY (&yyptr->Stack_alloc, Stack, yysize); \
+- Stack = &yyptr->Stack_alloc; \
+- yynewbytes = yystacksize * sizeof (*Stack) + YYSTACK_GAP_MAXIMUM; \
+- yyptr += yynewbytes / sizeof (*yyptr); \
+- } \
+- while (YYID (0))
++# define YYSTACK_RELOCATE(Stack_alloc, Stack) \
++ do \
++ { \
++ YYSIZE_T yynewbytes; \
++ YYCOPY (&yyptr->Stack_alloc, Stack, yysize); \
++ Stack = &yyptr->Stack_alloc; \
++ yynewbytes = yystacksize * sizeof (*Stack) + YYSTACK_GAP_MAXIMUM; \
++ yyptr += yynewbytes / sizeof (*yyptr); \
++ } \
++ while (0)
+
+ #endif
+
+@@ -421,7 +431,7 @@
+ for (yyi = 0; yyi < (Count); yyi++) \
+ (Dst)[yyi] = (Src)[yyi]; \
+ } \
+- while (YYID (0))
++ while (0)
+ # endif
+ # endif
+ #endif /* !YYCOPY_NEEDED */
+@@ -429,25 +439,27 @@
+ /* YYFINAL -- State number of the termination state. */
+ #define YYFINAL 4
+ /* YYLAST -- Last index in YYTABLE. */
+-#define YYLAST 133
++#define YYLAST 135
+
+ /* YYNTOKENS -- Number of terminals. */
+ #define YYNTOKENS 48
+ /* YYNNTS -- Number of nonterminals. */
+-#define YYNNTS 28
++#define YYNNTS 29
+ /* YYNRULES -- Number of rules. */
+-#define YYNRULES 79
+-/* YYNRULES -- Number of states. */
+-#define YYNSTATES 141
++#define YYNRULES 81
++/* YYNSTATES -- Number of states. */
++#define YYNSTATES 144
+
+-/* YYTRANSLATE(YYLEX) -- Bison symbol number corresponding to YYLEX. */
++/* YYTRANSLATE[YYX] -- Symbol number corresponding to YYX as returned
++ by yylex, with out-of-bounds checking. */
+ #define YYUNDEFTOK 2
+ #define YYMAXUTOK 279
+
+-#define YYTRANSLATE(YYX) \
++#define YYTRANSLATE(YYX) \
+ ((unsigned int) (YYX) <= YYMAXUTOK ? yytranslate[YYX] : YYUNDEFTOK)
+
+-/* YYTRANSLATE[YYLEX] -- Bison symbol number corresponding to YYLEX. */
++/* YYTRANSLATE[TOKEN-NUM] -- Symbol number corresponding to TOKEN-NUM
++ as returned by yylex, without out-of-bounds checking. */
+ static const yytype_uint8 yytranslate[] =
+ {
+ 0, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+@@ -481,63 +493,18 @@
+ };
+
+ #if YYDEBUG
+-/* YYPRHS[YYN] -- Index of the first RHS symbol of rule number YYN in
+- YYRHS. */
+-static const yytype_uint16 yyprhs[] =
+-{
+- 0, 0, 3, 8, 9, 12, 17, 20, 23, 27,
+- 31, 36, 42, 43, 46, 51, 54, 58, 61, 64,
+- 68, 73, 76, 86, 92, 95, 96, 99, 102, 106,
+- 108, 111, 114, 117, 119, 121, 125, 127, 129, 135,
+- 137, 141, 143, 147, 149, 153, 155, 159, 161, 165,
+- 167, 171, 175, 177, 181, 185, 189, 193, 197, 201,
+- 203, 207, 211, 213, 217, 221, 225, 227, 229, 232,
+- 235, 238, 239, 242, 245, 246, 249, 252, 255, 259
+-};
+-
+-/* YYRHS -- A `-1'-separated list of the rules' RHS. */
+-static const yytype_int8 yyrhs[] =
+-{
+- 49, 0, -1, 3, 25, 50, 52, -1, -1, 51,
+- 50, -1, 4, 59, 59, 25, -1, 22, 51, -1,
+- 26, 53, -1, 52, 26, 53, -1, 52, 23, 53,
+- -1, 52, 15, 23, 25, -1, 27, 54, 74, 28,
+- 25, -1, -1, 54, 55, -1, 16, 29, 56, 25,
+- -1, 16, 25, -1, 14, 16, 25, -1, 22, 55,
+- -1, 57, 21, -1, 57, 58, 30, -1, 57, 31,
+- 73, 32, -1, 57, 23, -1, 57, 24, 33, 21,
+- 34, 59, 34, 59, 35, -1, 57, 24, 33, 21,
+- 35, -1, 56, 22, -1, -1, 56, 34, -1, 57,
+- 22, -1, 13, 17, 36, -1, 36, -1, 58, 59,
+- -1, 58, 23, -1, 58, 22, -1, 17, -1, 18,
+- -1, 33, 60, 35, -1, 61, -1, 62, -1, 62,
+- 37, 60, 38, 61, -1, 63, -1, 62, 12, 63,
+- -1, 64, -1, 63, 11, 64, -1, 65, -1, 64,
+- 39, 65, -1, 66, -1, 65, 40, 66, -1, 67,
+- -1, 66, 41, 67, -1, 68, -1, 67, 9, 68,
+- -1, 67, 10, 68, -1, 69, -1, 68, 36, 69,
+- -1, 68, 30, 69, -1, 68, 7, 69, -1, 68,
+- 8, 69, -1, 69, 5, 70, -1, 69, 6, 70,
+- -1, 70, -1, 70, 42, 71, -1, 70, 43, 71,
+- -1, 71, -1, 71, 44, 72, -1, 71, 26, 72,
+- -1, 71, 45, 72, -1, 72, -1, 59, -1, 43,
+- 72, -1, 46, 72, -1, 47, 72, -1, -1, 73,
+- 20, -1, 73, 22, -1, -1, 75, 74, -1, 75,
+- 55, -1, 16, 53, -1, 15, 16, 25, -1, 22,
+- 75, -1
+-};
+-
+-/* YYRLINE[YYN] -- source line where rule number YYN was defined. */
++ /* YYRLINE[YYN] -- Source line where rule number YYN was defined. */
+ static const yytype_uint16 yyrline[] =
+ {
+- 0, 109, 109, 118, 121, 128, 132, 140, 144, 148,
+- 158, 172, 180, 183, 190, 194, 198, 202, 210, 214,
+- 218, 222, 226, 243, 253, 261, 264, 268, 275, 290,
+- 295, 315, 329, 336, 340, 344, 351, 355, 356, 360,
+- 361, 365, 366, 370, 371, 375, 376, 380, 381, 385,
+- 386, 387, 391, 392, 393, 394, 395, 399, 400, 401,
+- 405, 406, 407, 411, 412, 413, 414, 418, 419, 420,
+- 421, 426, 429, 433, 441, 444, 448, 456, 460, 464
++ 0, 108, 108, 119, 122, 130, 133, 140, 144, 152,
++ 156, 160, 170, 185, 193, 196, 203, 207, 211, 215,
++ 223, 227, 231, 235, 239, 255, 265, 273, 276, 280,
++ 287, 303, 308, 327, 341, 348, 349, 350, 357, 361,
++ 362, 366, 367, 371, 372, 376, 377, 381, 382, 386,
++ 387, 391, 392, 393, 397, 398, 399, 400, 401, 405,
++ 406, 407, 411, 412, 413, 417, 418, 419, 420, 424,
++ 425, 426, 427, 432, 435, 439, 447, 450, 454, 462,
++ 466, 470
+ };
+ #endif
+
+@@ -546,25 +513,25 @@
+ First, the terminals, then, starting at YYNTOKENS, nonterminals. */
+ static const char *const yytname[] =
+ {
+- "$end", "error", "$undefined", "DT_V1", "DT_MEMRESERVE", "DT_LSHIFT",
+- "DT_RSHIFT", "DT_LE", "DT_GE", "DT_EQ", "DT_NE", "DT_AND", "DT_OR",
+- "DT_BITS", "DT_DEL_PROP", "DT_DEL_NODE", "DT_PROPNODENAME", "DT_LITERAL",
+- "DT_CHAR_LITERAL", "DT_BASE", "DT_BYTE", "DT_STRING", "DT_LABEL",
++ "$end", "error", "$undefined", "DT_V1", "DT_PLUGIN", "DT_MEMRESERVE",
++ "DT_LSHIFT", "DT_RSHIFT", "DT_LE", "DT_GE", "DT_EQ", "DT_NE", "DT_AND",
++ "DT_OR", "DT_BITS", "DT_DEL_PROP", "DT_DEL_NODE", "DT_PROPNODENAME",
++ "DT_LITERAL", "DT_CHAR_LITERAL", "DT_BYTE", "DT_STRING", "DT_LABEL",
+ "DT_REF", "DT_INCBIN", "';'", "'/'", "'{'", "'}'", "'='", "'>'", "'['",
+ "']'", "'('", "','", "')'", "'<'", "'?'", "':'", "'|'", "'^'", "'&'",
+ "'+'", "'-'", "'*'", "'%'", "'~'", "'!'", "$accept", "sourcefile",
+- "memreserves", "memreserve", "devicetree", "nodedef", "proplist",
+- "propdef", "propdata", "propdataprefix", "arrayprefix", "integer_prim",
+- "integer_expr", "integer_trinary", "integer_or", "integer_and",
+- "integer_bitor", "integer_bitxor", "integer_bitand", "integer_eq",
+- "integer_rela", "integer_shift", "integer_add", "integer_mul",
+- "integer_unary", "bytestring", "subnodes", "subnode", YY_NULL
++ "plugindecl", "memreserves", "memreserve", "devicetree", "nodedef",
++ "proplist", "propdef", "propdata", "propdataprefix", "arrayprefix",
++ "integer_prim", "integer_expr", "integer_trinary", "integer_or",
++ "integer_and", "integer_bitor", "integer_bitxor", "integer_bitand",
++ "integer_eq", "integer_rela", "integer_shift", "integer_add",
++ "integer_mul", "integer_unary", "bytestring", "subnodes", "subnode", YY_NULLPTR
+ };
+ #endif
+
+ # ifdef YYPRINT
+-/* YYTOKNUM[YYLEX-NUM] -- Internal token number corresponding to
+- token YYLEX-NUM. */
++/* YYTOKNUM[NUM] -- (External) token number corresponding to the
++ (internal) symbol number NUM (which must be that of a token). */
+ static const yytype_uint16 yytoknum[] =
+ {
+ 0, 256, 257, 258, 259, 260, 261, 262, 263, 264,
+@@ -575,183 +542,173 @@
+ };
+ # endif
+
+-/* YYR1[YYN] -- Symbol number of symbol that rule YYN derives. */
+-static const yytype_uint8 yyr1[] =
+-{
+- 0, 48, 49, 50, 50, 51, 51, 52, 52, 52,
+- 52, 53, 54, 54, 55, 55, 55, 55, 56, 56,
+- 56, 56, 56, 56, 56, 57, 57, 57, 58, 58,
+- 58, 58, 58, 59, 59, 59, 60, 61, 61, 62,
+- 62, 63, 63, 64, 64, 65, 65, 66, 66, 67,
+- 67, 67, 68, 68, 68, 68, 68, 69, 69, 69,
+- 70, 70, 70, 71, 71, 71, 71, 72, 72, 72,
+- 72, 73, 73, 73, 74, 74, 74, 75, 75, 75
+-};
++#define YYPACT_NINF -41
+
+-/* YYR2[YYN] -- Number of symbols composing right hand side of rule YYN. */
+-static const yytype_uint8 yyr2[] =
++#define yypact_value_is_default(Yystate) \
++ (!!((Yystate) == (-41)))
++
++#define YYTABLE_NINF -1
++
++#define yytable_value_is_error(Yytable_value) \
++ 0
++
++ /* YYPACT[STATE-NUM] -- Index in YYTABLE of the portion describing
++ STATE-NUM. */
++static const yytype_int8 yypact[] =
+ {
+- 0, 2, 4, 0, 2, 4, 2, 2, 3, 3,
+- 4, 5, 0, 2, 4, 2, 3, 2, 2, 3,
+- 4, 2, 9, 5, 2, 0, 2, 2, 3, 1,
+- 2, 2, 2, 1, 1, 3, 1, 1, 5, 1,
+- 3, 1, 3, 1, 3, 1, 3, 1, 3, 1,
+- 3, 3, 1, 3, 3, 3, 3, 3, 3, 1,
+- 3, 3, 1, 3, 3, 3, 1, 1, 2, 2,
+- 2, 0, 2, 2, 0, 2, 2, 2, 3, 2
++ 37, 10, 24, 78, -41, 20, 9, -41, 8, 9,
++ 59, 9, -41, -41, -10, 8, -41, 60, 39, -41,
++ -10, -10, -10, -41, 51, -41, -7, 76, 50, 52,
++ 53, 49, 2, 65, 32, -1, -41, 66, -41, -41,
++ 67, 60, 60, -41, -41, -41, -41, -10, -10, -10,
++ -10, -10, -10, -10, -10, -10, -10, -10, -10, -10,
++ -10, -10, -10, -10, -10, -10, -41, 41, 68, -41,
++ -41, 76, 57, 50, 52, 53, 49, 2, 2, 65,
++ 65, 65, 65, 32, 32, -1, -1, -41, -41, -41,
++ 79, 80, -12, 41, -41, 70, 41, -41, -10, 74,
++ 75, -41, -41, -41, -41, -41, 77, -41, -41, -41,
++ -41, -41, 17, -2, -41, -41, -41, -41, 83, -41,
++ -41, -41, 71, -41, -41, 31, 69, 82, -4, -41,
++ -41, -41, -41, -41, 42, -41, -41, -41, 8, -41,
++ 72, 8, 73, -41
+ };
+
+-/* YYDEFACT[STATE-NAME] -- Default reduction number in state STATE-NUM.
+- Performed when YYTABLE doesn't specify something else to do. Zero
+- means the default is an error. */
++ /* YYDEFACT[STATE-NUM] -- Default reduction number in state STATE-NUM.
++ Performed when YYTABLE does not specify something else to do. Zero
++ means the default is an error. */
+ static const yytype_uint8 yydefact[] =
+ {
+- 0, 0, 0, 3, 1, 0, 0, 0, 3, 33,
+- 34, 0, 0, 6, 0, 2, 4, 0, 0, 0,
+- 67, 0, 36, 37, 39, 41, 43, 45, 47, 49,
+- 52, 59, 62, 66, 0, 12, 7, 0, 0, 0,
+- 68, 69, 70, 35, 0, 0, 0, 0, 0, 0,
++ 0, 0, 0, 3, 1, 0, 5, 4, 0, 0,
++ 0, 5, 35, 36, 0, 0, 8, 0, 2, 6,
++ 0, 0, 0, 69, 0, 38, 39, 41, 43, 45,
++ 47, 49, 51, 54, 61, 64, 68, 0, 14, 9,
++ 0, 0, 0, 70, 71, 72, 37, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+- 0, 0, 0, 5, 74, 0, 9, 8, 40, 0,
+- 42, 44, 46, 48, 50, 51, 55, 56, 54, 53,
+- 57, 58, 60, 61, 64, 63, 65, 0, 0, 0,
+- 0, 13, 0, 74, 10, 0, 0, 0, 15, 25,
+- 77, 17, 79, 0, 76, 75, 38, 16, 78, 0,
+- 0, 11, 24, 14, 26, 0, 18, 27, 21, 0,
+- 71, 29, 0, 0, 0, 0, 32, 31, 19, 30,
+- 28, 0, 72, 73, 20, 0, 23, 0, 0, 0,
+- 22
++ 0, 0, 0, 0, 0, 0, 7, 76, 0, 11,
++ 10, 42, 0, 44, 46, 48, 50, 52, 53, 57,
++ 58, 56, 55, 59, 60, 62, 63, 66, 65, 67,
++ 0, 0, 0, 0, 15, 0, 76, 12, 0, 0,
++ 0, 17, 27, 79, 19, 81, 0, 78, 77, 40,
++ 18, 80, 0, 0, 13, 26, 16, 28, 0, 20,
++ 29, 23, 0, 73, 31, 0, 0, 0, 0, 34,
++ 33, 21, 32, 30, 0, 74, 75, 22, 0, 25,
++ 0, 0, 0, 24
+ };
+
+-/* YYDEFGOTO[NTERM-NUM]. */
+-static const yytype_int8 yydefgoto[] =
++ /* YYPGOTO[NTERM-NUM]. */
++static const yytype_int8 yypgoto[] =
+ {
+- -1, 2, 7, 8, 15, 36, 64, 91, 109, 110,
+- 122, 20, 21, 22, 23, 24, 25, 26, 27, 28,
+- 29, 30, 31, 32, 33, 125, 92, 93
++ -41, -41, -41, 96, 100, -41, -40, -41, -23, -41,
++ -41, -41, -8, 62, 13, -41, 81, 63, 64, 84,
++ 61, 25, 11, 21, 22, -17, -41, 19, 23
+ };
+
+-/* YYPACT[STATE-NUM] -- Index in YYTABLE of the portion describing
+- STATE-NUM. */
+-#define YYPACT_NINF -78
+-static const yytype_int8 yypact[] =
++ /* YYDEFGOTO[NTERM-NUM]. */
++static const yytype_int16 yydefgoto[] =
+ {
+- 22, 11, 51, 10, -78, 23, 10, 2, 10, -78,
+- -78, -9, 23, -78, 30, 38, -78, -9, -9, -9,
+- -78, 35, -78, -6, 52, 29, 48, 49, 33, 3,
+- 71, 36, 0, -78, 64, -78, -78, 68, 30, 30,
+- -78, -78, -78, -78, -9, -9, -9, -9, -9, -9,
+- -9, -9, -9, -9, -9, -9, -9, -9, -9, -9,
+- -9, -9, -9, -78, 44, 67, -78, -78, 52, 55,
+- 29, 48, 49, 33, 3, 3, 71, 71, 71, 71,
+- 36, 36, 0, 0, -78, -78, -78, 78, 79, 42,
+- 44, -78, 69, 44, -78, -9, 73, 74, -78, -78,
+- -78, -78, -78, 75, -78, -78, -78, -78, -78, -7,
+- -1, -78, -78, -78, -78, 84, -78, -78, -78, 63,
+- -78, -78, 32, 66, 82, -3, -78, -78, -78, -78,
+- -78, 46, -78, -78, -78, 23, -78, 70, 23, 72,
+- -78
++ -1, 2, 6, 10, 11, 18, 39, 67, 94, 112,
++ 113, 125, 23, 24, 25, 26, 27, 28, 29, 30,
++ 31, 32, 33, 34, 35, 36, 128, 95, 96
+ };
+
+-/* YYPGOTO[NTERM-NUM]. */
+-static const yytype_int8 yypgoto[] =
++ /* YYTABLE[YYPACT[STATE-NUM]] -- What to do in state STATE-NUM. If
++ positive, shift that token. If negative, reduce the rule whose
++ number is the opposite. If YYTABLE_NINF, syntax error. */
++static const yytype_uint8 yytable[] =
+ {
+- -78, -78, 97, 100, -78, -37, -78, -77, -78, -78,
+- -78, -5, 65, 13, -78, 76, 77, 62, 80, 83,
+- 34, 20, 26, 28, -14, -78, 18, 24
++ 15, 69, 70, 43, 44, 45, 47, 37, 12, 13,
++ 55, 56, 118, 101, 8, 38, 135, 102, 136, 119,
++ 120, 121, 122, 14, 4, 63, 12, 13, 137, 123,
++ 48, 9, 57, 20, 124, 3, 21, 22, 58, 115,
++ 1, 14, 116, 64, 65, 7, 87, 88, 89, 12,
++ 13, 117, 103, 129, 130, 40, 90, 91, 92, 53,
++ 54, 131, 41, 93, 14, 42, 79, 80, 81, 82,
++ 104, 59, 60, 107, 61, 62, 138, 139, 77, 78,
++ 83, 84, 5, 85, 86, 17, 46, 38, 49, 50,
++ 68, 66, 51, 97, 52, 98, 99, 100, 106, 110,
++ 111, 126, 114, 134, 127, 133, 141, 19, 143, 16,
++ 72, 109, 73, 76, 74, 108, 105, 132, 0, 0,
++ 0, 0, 0, 0, 0, 0, 0, 0, 71, 0,
++ 140, 0, 0, 142, 0, 75
+ };
+
+-/* YYTABLE[YYPACT[STATE-NUM]]. What to do in state STATE-NUM. If
+- positive, shift that token. If negative, reduce the rule which
+- number is the opposite. If YYTABLE_NINF, syntax error. */
+-#define YYTABLE_NINF -1
+-static const yytype_uint8 yytable[] =
++static const yytype_int16 yycheck[] =
+ {
+- 12, 66, 67, 40, 41, 42, 44, 34, 9, 10,
+- 52, 53, 115, 101, 5, 112, 104, 132, 113, 133,
+- 116, 117, 118, 119, 11, 1, 60, 114, 14, 134,
+- 120, 45, 6, 54, 17, 121, 3, 18, 19, 55,
+- 9, 10, 50, 51, 61, 62, 84, 85, 86, 9,
+- 10, 4, 100, 37, 126, 127, 11, 35, 87, 88,
+- 89, 38, 128, 46, 39, 11, 90, 98, 47, 35,
+- 43, 99, 76, 77, 78, 79, 56, 57, 58, 59,
+- 135, 136, 80, 81, 74, 75, 82, 83, 48, 63,
+- 49, 65, 94, 95, 96, 97, 124, 103, 107, 108,
+- 111, 123, 130, 131, 138, 16, 13, 140, 106, 71,
+- 69, 105, 0, 0, 102, 0, 0, 129, 0, 0,
+- 68, 0, 0, 70, 0, 0, 0, 0, 72, 0,
+- 137, 0, 73, 139
++ 8, 41, 42, 20, 21, 22, 13, 15, 18, 19,
++ 8, 9, 14, 25, 5, 27, 20, 29, 22, 21,
++ 22, 23, 24, 33, 0, 26, 18, 19, 32, 31,
++ 37, 22, 30, 43, 36, 25, 46, 47, 36, 22,
++ 3, 33, 25, 44, 45, 25, 63, 64, 65, 18,
++ 19, 34, 92, 22, 23, 16, 15, 16, 17, 10,
++ 11, 30, 23, 22, 33, 26, 55, 56, 57, 58,
++ 93, 6, 7, 96, 42, 43, 34, 35, 53, 54,
++ 59, 60, 4, 61, 62, 26, 35, 27, 12, 39,
++ 23, 25, 40, 25, 41, 38, 17, 17, 28, 25,
++ 25, 18, 25, 21, 33, 36, 34, 11, 35, 9,
++ 48, 98, 49, 52, 50, 96, 93, 125, -1, -1,
++ -1, -1, -1, -1, -1, -1, -1, -1, 47, -1,
++ 138, -1, -1, 141, -1, 51
+ };
+
+-#define yypact_value_is_default(Yystate) \
+- (!!((Yystate) == (-78)))
+-
+-#define yytable_value_is_error(Yytable_value) \
+- YYID (0)
++ /* YYSTOS[STATE-NUM] -- The (internal number of the) accessing
++ symbol of state STATE-NUM. */
++static const yytype_uint8 yystos[] =
++{
++ 0, 3, 49, 25, 0, 4, 50, 25, 5, 22,
++ 51, 52, 18, 19, 33, 60, 52, 26, 53, 51,
++ 43, 46, 47, 60, 61, 62, 63, 64, 65, 66,
++ 67, 68, 69, 70, 71, 72, 73, 60, 27, 54,
++ 16, 23, 26, 73, 73, 73, 35, 13, 37, 12,
++ 39, 40, 41, 10, 11, 8, 9, 30, 36, 6,
++ 7, 42, 43, 26, 44, 45, 25, 55, 23, 54,
++ 54, 64, 61, 65, 66, 67, 68, 69, 69, 70,
++ 70, 70, 70, 71, 71, 72, 72, 73, 73, 73,
++ 15, 16, 17, 22, 56, 75, 76, 25, 38, 17,
++ 17, 25, 29, 54, 56, 76, 28, 56, 75, 62,
++ 25, 25, 57, 58, 25, 22, 25, 34, 14, 21,
++ 22, 23, 24, 31, 36, 59, 18, 33, 74, 22,
++ 23, 30, 60, 36, 21, 20, 22, 32, 34, 35,
++ 60, 34, 60, 35
++};
+
+-static const yytype_int16 yycheck[] =
++ /* YYR1[YYN] -- Symbol number of symbol that rule YYN derives. */
++static const yytype_uint8 yyr1[] =
+ {
+- 5, 38, 39, 17, 18, 19, 12, 12, 17, 18,
+- 7, 8, 13, 90, 4, 22, 93, 20, 25, 22,
+- 21, 22, 23, 24, 33, 3, 26, 34, 26, 32,
+- 31, 37, 22, 30, 43, 36, 25, 46, 47, 36,
+- 17, 18, 9, 10, 44, 45, 60, 61, 62, 17,
+- 18, 0, 89, 15, 22, 23, 33, 27, 14, 15,
+- 16, 23, 30, 11, 26, 33, 22, 25, 39, 27,
+- 35, 29, 52, 53, 54, 55, 5, 6, 42, 43,
+- 34, 35, 56, 57, 50, 51, 58, 59, 40, 25,
+- 41, 23, 25, 38, 16, 16, 33, 28, 25, 25,
+- 25, 17, 36, 21, 34, 8, 6, 35, 95, 47,
+- 45, 93, -1, -1, 90, -1, -1, 122, -1, -1,
+- 44, -1, -1, 46, -1, -1, -1, -1, 48, -1,
+- 135, -1, 49, 138
++ 0, 48, 49, 50, 50, 51, 51, 52, 52, 53,
++ 53, 53, 53, 54, 55, 55, 56, 56, 56, 56,
++ 57, 57, 57, 57, 57, 57, 57, 58, 58, 58,
++ 59, 59, 59, 59, 59, 60, 60, 60, 61, 62,
++ 62, 63, 63, 64, 64, 65, 65, 66, 66, 67,
++ 67, 68, 68, 68, 69, 69, 69, 69, 69, 70,
++ 70, 70, 71, 71, 71, 72, 72, 72, 72, 73,
++ 73, 73, 73, 74, 74, 74, 75, 75, 75, 76,
++ 76, 76
+ };
+
+-/* YYSTOS[STATE-NUM] -- The (internal number of the) accessing
+- symbol of state STATE-NUM. */
+-static const yytype_uint8 yystos[] =
++ /* YYR2[YYN] -- Number of symbols on the right hand side of rule YYN. */
++static const yytype_uint8 yyr2[] =
+ {
+- 0, 3, 49, 25, 0, 4, 22, 50, 51, 17,
+- 18, 33, 59, 51, 26, 52, 50, 43, 46, 47,
+- 59, 60, 61, 62, 63, 64, 65, 66, 67, 68,
+- 69, 70, 71, 72, 59, 27, 53, 15, 23, 26,
+- 72, 72, 72, 35, 12, 37, 11, 39, 40, 41,
+- 9, 10, 7, 8, 30, 36, 5, 6, 42, 43,
+- 26, 44, 45, 25, 54, 23, 53, 53, 63, 60,
+- 64, 65, 66, 67, 68, 68, 69, 69, 69, 69,
+- 70, 70, 71, 71, 72, 72, 72, 14, 15, 16,
+- 22, 55, 74, 75, 25, 38, 16, 16, 25, 29,
+- 53, 55, 75, 28, 55, 74, 61, 25, 25, 56,
+- 57, 25, 22, 25, 34, 13, 21, 22, 23, 24,
+- 31, 36, 58, 17, 33, 73, 22, 23, 30, 59,
+- 36, 21, 20, 22, 32, 34, 35, 59, 34, 59,
+- 35
++ 0, 2, 5, 0, 2, 0, 2, 4, 2, 2,
++ 3, 3, 4, 5, 0, 2, 4, 2, 3, 2,
++ 2, 3, 4, 2, 9, 5, 2, 0, 2, 2,
++ 3, 1, 2, 2, 2, 1, 1, 3, 1, 1,
++ 5, 1, 3, 1, 3, 1, 3, 1, 3, 1,
++ 3, 1, 3, 3, 1, 3, 3, 3, 3, 3,
++ 3, 1, 3, 3, 1, 3, 3, 3, 1, 1,
++ 2, 2, 2, 0, 2, 2, 0, 2, 2, 2,
++ 3, 2
+ };
+
+-#define yyerrok (yyerrstatus = 0)
+-#define yyclearin (yychar = YYEMPTY)
+-#define YYEMPTY (-2)
+-#define YYEOF 0
+-
+-#define YYACCEPT goto yyacceptlab
+-#define YYABORT goto yyabortlab
+-#define YYERROR goto yyerrorlab
+-
+-
+-/* Like YYERROR except do call yyerror. This remains here temporarily
+- to ease the transition to the new meaning of YYERROR, for GCC.
+- Once GCC version 2 has supplanted version 1, this can go. However,
+- YYFAIL appears to be in use. Nevertheless, it is formally deprecated
+- in Bison 2.4.2's NEWS entry, where a plan to phase it out is
+- discussed. */
+-
+-#define YYFAIL goto yyerrlab
+-#if defined YYFAIL
+- /* This is here to suppress warnings from the GCC cpp's
+- -Wunused-macros. Normally we don't worry about that warning, but
+- some users do, and we want to make it easy for users to remove
+- YYFAIL uses, which will produce warnings from Bison 2.5. */
+-#endif
++
++#define yyerrok (yyerrstatus = 0)
++#define yyclearin (yychar = YYEMPTY)
++#define YYEMPTY (-2)
++#define YYEOF 0
++
++#define YYACCEPT goto yyacceptlab
++#define YYABORT goto yyabortlab
++#define YYERROR goto yyerrorlab
++
+
+ #define YYRECOVERING() (!!yyerrstatus)
+
+@@ -768,27 +725,41 @@
+ else \
+ { \
+ yyerror (YY_("syntax error: cannot back up")); \
+- YYERROR; \
+- } \
+-while (YYID (0))
++ YYERROR; \
++ } \
++while (0)
+
+ /* Error token number */
+-#define YYTERROR 1
+-#define YYERRCODE 256
++#define YYTERROR 1
++#define YYERRCODE 256
+
+
+-/* This macro is provided for backward compatibility. */
+-#ifndef YY_LOCATION_PRINT
+-# define YY_LOCATION_PRINT(File, Loc) ((void) 0)
++/* YYLLOC_DEFAULT -- Set CURRENT to span from RHS[1] to RHS[N].
++ If N is 0, then set CURRENT to the empty location which ends
++ the previous symbol: RHS[0] (always defined). */
++
++#ifndef YYLLOC_DEFAULT
++# define YYLLOC_DEFAULT(Current, Rhs, N) \
++ do \
++ if (N) \
++ { \
++ (Current).first_line = YYRHSLOC (Rhs, 1).first_line; \
++ (Current).first_column = YYRHSLOC (Rhs, 1).first_column; \
++ (Current).last_line = YYRHSLOC (Rhs, N).last_line; \
++ (Current).last_column = YYRHSLOC (Rhs, N).last_column; \
++ } \
++ else \
++ { \
++ (Current).first_line = (Current).last_line = \
++ YYRHSLOC (Rhs, 0).last_line; \
++ (Current).first_column = (Current).last_column = \
++ YYRHSLOC (Rhs, 0).last_column; \
++ } \
++ while (0)
+ #endif
+
++#define YYRHSLOC(Rhs, K) ((Rhs)[K])
+
+-/* YYLEX -- calling `yylex' with the right arguments. */
+-#ifdef YYLEX_PARAM
+-# define YYLEX yylex (YYLEX_PARAM)
+-#else
+-# define YYLEX yylex ()
+-#endif
+
+ /* Enable debugging if requested. */
+ #if YYDEBUG
+@@ -798,50 +769,84 @@
+ # define YYFPRINTF fprintf
+ # endif
+
+-# define YYDPRINTF(Args) \
+-do { \
+- if (yydebug) \
+- YYFPRINTF Args; \
+-} while (YYID (0))
+-
+-# define YY_SYMBOL_PRINT(Title, Type, Value, Location) \
+-do { \
+- if (yydebug) \
+- { \
+- YYFPRINTF (stderr, "%s ", Title); \
+- yy_symbol_print (stderr, \
+- Type, Value); \
+- YYFPRINTF (stderr, "\n"); \
+- } \
+-} while (YYID (0))
++# define YYDPRINTF(Args) \
++do { \
++ if (yydebug) \
++ YYFPRINTF Args; \
++} while (0)
+
+
+-/*--------------------------------.
+-| Print this symbol on YYOUTPUT. |
+-`--------------------------------*/
++/* YY_LOCATION_PRINT -- Print the location on the stream.
++ This macro was not mandated originally: define only if we know
++ we won't break user code: when these are the locations we know. */
+
+-/*ARGSUSED*/
+-#if (defined __STDC__ || defined __C99__FUNC__ \
+- || defined __cplusplus || defined _MSC_VER)
+-static void
+-yy_symbol_value_print (FILE *yyoutput, int yytype, YYSTYPE const * const yyvaluep)
+-#else
+-static void
+-yy_symbol_value_print (yyoutput, yytype, yyvaluep)
+- FILE *yyoutput;
+- int yytype;
+- YYSTYPE const * const yyvaluep;
++#ifndef YY_LOCATION_PRINT
++# if defined YYLTYPE_IS_TRIVIAL && YYLTYPE_IS_TRIVIAL
++
++/* Print *YYLOCP on YYO. Private, do not rely on its existence. */
++
++YY_ATTRIBUTE_UNUSED
++static unsigned
++yy_location_print_ (FILE *yyo, YYLTYPE const * const yylocp)
++{
++ unsigned res = 0;
++ int end_col = 0 != yylocp->last_column ? yylocp->last_column - 1 : 0;
++ if (0 <= yylocp->first_line)
++ {
++ res += YYFPRINTF (yyo, "%d", yylocp->first_line);
++ if (0 <= yylocp->first_column)
++ res += YYFPRINTF (yyo, ".%d", yylocp->first_column);
++ }
++ if (0 <= yylocp->last_line)
++ {
++ if (yylocp->first_line < yylocp->last_line)
++ {
++ res += YYFPRINTF (yyo, "-%d", yylocp->last_line);
++ if (0 <= end_col)
++ res += YYFPRINTF (yyo, ".%d", end_col);
++ }
++ else if (0 <= end_col && yylocp->first_column < end_col)
++ res += YYFPRINTF (yyo, "-%d", end_col);
++ }
++ return res;
++ }
++
++# define YY_LOCATION_PRINT(File, Loc) \
++ yy_location_print_ (File, &(Loc))
++
++# else
++# define YY_LOCATION_PRINT(File, Loc) ((void) 0)
++# endif
+ #endif
++
++
++# define YY_SYMBOL_PRINT(Title, Type, Value, Location) \
++do { \
++ if (yydebug) \
++ { \
++ YYFPRINTF (stderr, "%s ", Title); \
++ yy_symbol_print (stderr, \
++ Type, Value, Location); \
++ YYFPRINTF (stderr, "\n"); \
++ } \
++} while (0)
++
++
++/*----------------------------------------.
++| Print this symbol's value on YYOUTPUT. |
++`----------------------------------------*/
++
++static void
++yy_symbol_value_print (FILE *yyoutput, int yytype, YYSTYPE const * const yyvaluep, YYLTYPE const * const yylocationp)
+ {
+ FILE *yyo = yyoutput;
+ YYUSE (yyo);
++ YYUSE (yylocationp);
+ if (!yyvaluep)
+ return;
+ # ifdef YYPRINT
+ if (yytype < YYNTOKENS)
+ YYPRINT (yyoutput, yytoknum[yytype], *yyvaluep);
+-# else
+- YYUSE (yyoutput);
+ # endif
+ YYUSE (yytype);
+ }
+@@ -851,24 +856,15 @@
+ | Print this symbol on YYOUTPUT. |
+ `--------------------------------*/
+
+-#if (defined __STDC__ || defined __C99__FUNC__ \
+- || defined __cplusplus || defined _MSC_VER)
+-static void
+-yy_symbol_print (FILE *yyoutput, int yytype, YYSTYPE const * const yyvaluep)
+-#else
+ static void
+-yy_symbol_print (yyoutput, yytype, yyvaluep)
+- FILE *yyoutput;
+- int yytype;
+- YYSTYPE const * const yyvaluep;
+-#endif
++yy_symbol_print (FILE *yyoutput, int yytype, YYSTYPE const * const yyvaluep, YYLTYPE const * const yylocationp)
+ {
+- if (yytype < YYNTOKENS)
+- YYFPRINTF (yyoutput, "token %s (", yytname[yytype]);
+- else
+- YYFPRINTF (yyoutput, "nterm %s (", yytname[yytype]);
++ YYFPRINTF (yyoutput, "%s %s (",
++ yytype < YYNTOKENS ? "token" : "nterm", yytname[yytype]);
+
+- yy_symbol_value_print (yyoutput, yytype, yyvaluep);
++ YY_LOCATION_PRINT (yyoutput, *yylocationp);
++ YYFPRINTF (yyoutput, ": ");
++ yy_symbol_value_print (yyoutput, yytype, yyvaluep, yylocationp);
+ YYFPRINTF (yyoutput, ")");
+ }
+
+@@ -877,16 +873,8 @@
+ | TOP (included). |
+ `------------------------------------------------------------------*/
+
+-#if (defined __STDC__ || defined __C99__FUNC__ \
+- || defined __cplusplus || defined _MSC_VER)
+ static void
+ yy_stack_print (yytype_int16 *yybottom, yytype_int16 *yytop)
+-#else
+-static void
+-yy_stack_print (yybottom, yytop)
+- yytype_int16 *yybottom;
+- yytype_int16 *yytop;
+-#endif
+ {
+ YYFPRINTF (stderr, "Stack now");
+ for (; yybottom <= yytop; yybottom++)
+@@ -897,49 +885,42 @@
+ YYFPRINTF (stderr, "\n");
+ }
+
+-# define YY_STACK_PRINT(Bottom, Top) \
+-do { \
+- if (yydebug) \
+- yy_stack_print ((Bottom), (Top)); \
+-} while (YYID (0))
++# define YY_STACK_PRINT(Bottom, Top) \
++do { \
++ if (yydebug) \
++ yy_stack_print ((Bottom), (Top)); \
++} while (0)
+
+
+ /*------------------------------------------------.
+ | Report that the YYRULE is going to be reduced. |
+ `------------------------------------------------*/
+
+-#if (defined __STDC__ || defined __C99__FUNC__ \
+- || defined __cplusplus || defined _MSC_VER)
+-static void
+-yy_reduce_print (YYSTYPE *yyvsp, int yyrule)
+-#else
+ static void
+-yy_reduce_print (yyvsp, yyrule)
+- YYSTYPE *yyvsp;
+- int yyrule;
+-#endif
++yy_reduce_print (yytype_int16 *yyssp, YYSTYPE *yyvsp, YYLTYPE *yylsp, int yyrule)
+ {
++ unsigned long int yylno = yyrline[yyrule];
+ int yynrhs = yyr2[yyrule];
+ int yyi;
+- unsigned long int yylno = yyrline[yyrule];
+ YYFPRINTF (stderr, "Reducing stack by rule %d (line %lu):\n",
+- yyrule - 1, yylno);
++ yyrule - 1, yylno);
+ /* The symbols being reduced. */
+ for (yyi = 0; yyi < yynrhs; yyi++)
+ {
+ YYFPRINTF (stderr, " $%d = ", yyi + 1);
+- yy_symbol_print (stderr, yyrhs[yyprhs[yyrule] + yyi],
+- &(yyvsp[(yyi + 1) - (yynrhs)])
+- );
++ yy_symbol_print (stderr,
++ yystos[yyssp[yyi + 1 - yynrhs]],
++ &(yyvsp[(yyi + 1) - (yynrhs)])
++ , &(yylsp[(yyi + 1) - (yynrhs)]) );
+ YYFPRINTF (stderr, "\n");
+ }
+ }
+
+-# define YY_REDUCE_PRINT(Rule) \
+-do { \
+- if (yydebug) \
+- yy_reduce_print (yyvsp, Rule); \
+-} while (YYID (0))
++# define YY_REDUCE_PRINT(Rule) \
++do { \
++ if (yydebug) \
++ yy_reduce_print (yyssp, yyvsp, yylsp, Rule); \
++} while (0)
+
+ /* Nonzero means print parse trace. It is left uninitialized so that
+ multiple parsers can coexist. */
+@@ -953,7 +934,7 @@
+
+
+ /* YYINITDEPTH -- initial size of the parser's stacks. */
+-#ifndef YYINITDEPTH
++#ifndef YYINITDEPTH
+ # define YYINITDEPTH 200
+ #endif
+
+@@ -976,15 +957,8 @@
+ # define yystrlen strlen
+ # else
+ /* Return the length of YYSTR. */
+-#if (defined __STDC__ || defined __C99__FUNC__ \
+- || defined __cplusplus || defined _MSC_VER)
+ static YYSIZE_T
+ yystrlen (const char *yystr)
+-#else
+-static YYSIZE_T
+-yystrlen (yystr)
+- const char *yystr;
+-#endif
+ {
+ YYSIZE_T yylen;
+ for (yylen = 0; yystr[yylen]; yylen++)
+@@ -1000,16 +974,8 @@
+ # else
+ /* Copy YYSRC to YYDEST, returning the address of the terminating '\0' in
+ YYDEST. */
+-#if (defined __STDC__ || defined __C99__FUNC__ \
+- || defined __cplusplus || defined _MSC_VER)
+ static char *
+ yystpcpy (char *yydest, const char *yysrc)
+-#else
+-static char *
+-yystpcpy (yydest, yysrc)
+- char *yydest;
+- const char *yysrc;
+-#endif
+ {
+ char *yyd = yydest;
+ const char *yys = yysrc;
+@@ -1039,27 +1005,27 @@
+ char const *yyp = yystr;
+
+ for (;;)
+- switch (*++yyp)
+- {
+- case '\'':
+- case ',':
+- goto do_not_strip_quotes;
+-
+- case '\\':
+- if (*++yyp != '\\')
+- goto do_not_strip_quotes;
+- /* Fall through. */
+- default:
+- if (yyres)
+- yyres[yyn] = *yyp;
+- yyn++;
+- break;
+-
+- case '"':
+- if (yyres)
+- yyres[yyn] = '\0';
+- return yyn;
+- }
++ switch (*++yyp)
++ {
++ case '\'':
++ case ',':
++ goto do_not_strip_quotes;
++
++ case '\\':
++ if (*++yyp != '\\')
++ goto do_not_strip_quotes;
++ /* Fall through. */
++ default:
++ if (yyres)
++ yyres[yyn] = *yyp;
++ yyn++;
++ break;
++
++ case '"':
++ if (yyres)
++ yyres[yyn] = '\0';
++ return yyn;
++ }
+ do_not_strip_quotes: ;
+ }
+
+@@ -1082,11 +1048,11 @@
+ yysyntax_error (YYSIZE_T *yymsg_alloc, char **yymsg,
+ yytype_int16 *yyssp, int yytoken)
+ {
+- YYSIZE_T yysize0 = yytnamerr (YY_NULL, yytname[yytoken]);
++ YYSIZE_T yysize0 = yytnamerr (YY_NULLPTR, yytname[yytoken]);
+ YYSIZE_T yysize = yysize0;
+ enum { YYERROR_VERBOSE_ARGS_MAXIMUM = 5 };
+ /* Internationalized format string. */
+- const char *yyformat = YY_NULL;
++ const char *yyformat = YY_NULLPTR;
+ /* Arguments of yyformat. */
+ char const *yyarg[YYERROR_VERBOSE_ARGS_MAXIMUM];
+ /* Number of reported tokens (one for the "unexpected", one per
+@@ -1094,10 +1060,6 @@
+ int yycount = 0;
+
+ /* There are many possibilities here to consider:
+- - Assume YYFAIL is not used. It's too flawed to consider. See
+- <http://lists.gnu.org/archive/html/bison-patches/2009-12/msg00024.html>
+- for details. YYERROR is fine as it does not invoke this
+- function.
+ - If this state is a consistent state with a default action, then
+ the only way this function was invoked is if the default action
+ is an error action. In that case, don't check for expected
+@@ -1147,7 +1109,7 @@
+ }
+ yyarg[yycount++] = yytname[yyx];
+ {
+- YYSIZE_T yysize1 = yysize + yytnamerr (YY_NULL, yytname[yyx]);
++ YYSIZE_T yysize1 = yysize + yytnamerr (YY_NULLPTR, yytname[yyx]);
+ if (! (yysize <= yysize1
+ && yysize1 <= YYSTACK_ALLOC_MAXIMUM))
+ return 2;
+@@ -1214,26 +1176,18 @@
+ | Release the memory associated to this symbol. |
+ `-----------------------------------------------*/
+
+-/*ARGSUSED*/
+-#if (defined __STDC__ || defined __C99__FUNC__ \
+- || defined __cplusplus || defined _MSC_VER)
+-static void
+-yydestruct (const char *yymsg, int yytype, YYSTYPE *yyvaluep)
+-#else
+ static void
+-yydestruct (yymsg, yytype, yyvaluep)
+- const char *yymsg;
+- int yytype;
+- YYSTYPE *yyvaluep;
+-#endif
++yydestruct (const char *yymsg, int yytype, YYSTYPE *yyvaluep, YYLTYPE *yylocationp)
+ {
+ YYUSE (yyvaluep);
+-
++ YYUSE (yylocationp);
+ if (!yymsg)
+ yymsg = "Deleting";
+ YY_SYMBOL_PRINT (yymsg, yytype, yyvaluep, yylocationp);
+
++ YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN
+ YYUSE (yytype);
++ YY_IGNORE_MAYBE_UNINITIALIZED_END
+ }
+
+
+@@ -1242,18 +1196,14 @@
+ /* The lookahead symbol. */
+ int yychar;
+
+-
+-#ifndef YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN
+-# define YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN
+-# define YY_IGNORE_MAYBE_UNINITIALIZED_END
+-#endif
+-#ifndef YY_INITIAL_VALUE
+-# define YY_INITIAL_VALUE(Value) /* Nothing. */
+-#endif
+-
+ /* The semantic value of the lookahead symbol. */
+-YYSTYPE yylval YY_INITIAL_VALUE(yyval_default);
+-
++YYSTYPE yylval;
++/* Location data for the lookahead symbol. */
++YYLTYPE yylloc
++# if defined YYLTYPE_IS_TRIVIAL && YYLTYPE_IS_TRIVIAL
++ = { 1, 1, 1, 1 }
++# endif
++;
+ /* Number of syntax errors so far. */
+ int yynerrs;
+
+@@ -1262,35 +1212,17 @@
+ | yyparse. |
+ `----------*/
+
+-#ifdef YYPARSE_PARAM
+-#if (defined __STDC__ || defined __C99__FUNC__ \
+- || defined __cplusplus || defined _MSC_VER)
+-int
+-yyparse (void *YYPARSE_PARAM)
+-#else
+-int
+-yyparse (YYPARSE_PARAM)
+- void *YYPARSE_PARAM;
+-#endif
+-#else /* ! YYPARSE_PARAM */
+-#if (defined __STDC__ || defined __C99__FUNC__ \
+- || defined __cplusplus || defined _MSC_VER)
+ int
+ yyparse (void)
+-#else
+-int
+-yyparse ()
+-
+-#endif
+-#endif
+ {
+ int yystate;
+ /* Number of tokens to shift before error messages enabled. */
+ int yyerrstatus;
+
+ /* The stacks and their tools:
+- `yyss': related to states.
+- `yyvs': related to semantic values.
++ 'yyss': related to states.
++ 'yyvs': related to semantic values.
++ 'yyls': related to locations.
+
+ Refer to the stacks through separate pointers, to allow yyoverflow
+ to reallocate them elsewhere. */
+@@ -1305,6 +1237,14 @@
+ YYSTYPE *yyvs;
+ YYSTYPE *yyvsp;
+
++ /* The location stack. */
++ YYLTYPE yylsa[YYINITDEPTH];
++ YYLTYPE *yyls;
++ YYLTYPE *yylsp;
++
++ /* The locations where the error started and ended. */
++ YYLTYPE yyerror_range[3];
++
+ YYSIZE_T yystacksize;
+
+ int yyn;
+@@ -1314,6 +1254,7 @@
+ /* The variables used to return semantic value and location from the
+ action routines. */
+ YYSTYPE yyval;
++ YYLTYPE yyloc;
+
+ #if YYERROR_VERBOSE
+ /* Buffer for error messages, and its allocated size. */
+@@ -1322,7 +1263,7 @@
+ YYSIZE_T yymsg_alloc = sizeof yymsgbuf;
+ #endif
+
+-#define YYPOPSTACK(N) (yyvsp -= (N), yyssp -= (N))
++#define YYPOPSTACK(N) (yyvsp -= (N), yyssp -= (N), yylsp -= (N))
+
+ /* The number of symbols on the RHS of the reduced rule.
+ Keep to zero when no symbol should be popped. */
+@@ -1330,6 +1271,7 @@
+
+ yyssp = yyss = yyssa;
+ yyvsp = yyvs = yyvsa;
++ yylsp = yyls = yylsa;
+ yystacksize = YYINITDEPTH;
+
+ YYDPRINTF ((stderr, "Starting parse\n"));
+@@ -1338,6 +1280,7 @@
+ yyerrstatus = 0;
+ yynerrs = 0;
+ yychar = YYEMPTY; /* Cause a token to be read. */
++ yylsp[0] = yylloc;
+ goto yysetstate;
+
+ /*------------------------------------------------------------.
+@@ -1358,23 +1301,26 @@
+
+ #ifdef yyoverflow
+ {
+- /* Give user a chance to reallocate the stack. Use copies of
+- these so that the &'s don't force the real ones into
+- memory. */
+- YYSTYPE *yyvs1 = yyvs;
+- yytype_int16 *yyss1 = yyss;
+-
+- /* Each stack pointer address is followed by the size of the
+- data in use in that stack, in bytes. This used to be a
+- conditional around just the two extra args, but that might
+- be undefined if yyoverflow is a macro. */
+- yyoverflow (YY_("memory exhausted"),
+- &yyss1, yysize * sizeof (*yyssp),
+- &yyvs1, yysize * sizeof (*yyvsp),
+- &yystacksize);
+-
+- yyss = yyss1;
+- yyvs = yyvs1;
++ /* Give user a chance to reallocate the stack. Use copies of
++ these so that the &'s don't force the real ones into
++ memory. */
++ YYSTYPE *yyvs1 = yyvs;
++ yytype_int16 *yyss1 = yyss;
++ YYLTYPE *yyls1 = yyls;
++
++ /* Each stack pointer address is followed by the size of the
++ data in use in that stack, in bytes. This used to be a
++ conditional around just the two extra args, but that might
++ be undefined if yyoverflow is a macro. */
++ yyoverflow (YY_("memory exhausted"),
++ &yyss1, yysize * sizeof (*yyssp),
++ &yyvs1, yysize * sizeof (*yyvsp),
++ &yyls1, yysize * sizeof (*yylsp),
++ &yystacksize);
++
++ yyls = yyls1;
++ yyss = yyss1;
++ yyvs = yyvs1;
+ }
+ #else /* no yyoverflow */
+ # ifndef YYSTACK_RELOCATE
+@@ -1382,34 +1328,36 @@
+ # else
+ /* Extend the stack our own way. */
+ if (YYMAXDEPTH <= yystacksize)
+- goto yyexhaustedlab;
++ goto yyexhaustedlab;
+ yystacksize *= 2;
+ if (YYMAXDEPTH < yystacksize)
+- yystacksize = YYMAXDEPTH;
++ yystacksize = YYMAXDEPTH;
+
+ {
+- yytype_int16 *yyss1 = yyss;
+- union yyalloc *yyptr =
+- (union yyalloc *) YYSTACK_ALLOC (YYSTACK_BYTES (yystacksize));
+- if (! yyptr)
+- goto yyexhaustedlab;
+- YYSTACK_RELOCATE (yyss_alloc, yyss);
+- YYSTACK_RELOCATE (yyvs_alloc, yyvs);
++ yytype_int16 *yyss1 = yyss;
++ union yyalloc *yyptr =
++ (union yyalloc *) YYSTACK_ALLOC (YYSTACK_BYTES (yystacksize));
++ if (! yyptr)
++ goto yyexhaustedlab;
++ YYSTACK_RELOCATE (yyss_alloc, yyss);
++ YYSTACK_RELOCATE (yyvs_alloc, yyvs);
++ YYSTACK_RELOCATE (yyls_alloc, yyls);
+ # undef YYSTACK_RELOCATE
+- if (yyss1 != yyssa)
+- YYSTACK_FREE (yyss1);
++ if (yyss1 != yyssa)
++ YYSTACK_FREE (yyss1);
+ }
+ # endif
+ #endif /* no yyoverflow */
+
+ yyssp = yyss + yysize - 1;
+ yyvsp = yyvs + yysize - 1;
++ yylsp = yyls + yysize - 1;
+
+ YYDPRINTF ((stderr, "Stack size increased to %lu\n",
+- (unsigned long int) yystacksize));
++ (unsigned long int) yystacksize));
+
+ if (yyss + yystacksize - 1 <= yyssp)
+- YYABORT;
++ YYABORT;
+ }
+
+ YYDPRINTF ((stderr, "Entering state %d\n", yystate));
+@@ -1438,7 +1386,7 @@
+ if (yychar == YYEMPTY)
+ {
+ YYDPRINTF ((stderr, "Reading a token: "));
+- yychar = YYLEX;
++ yychar = yylex ();
+ }
+
+ if (yychar <= YYEOF)
+@@ -1481,7 +1429,7 @@
+ YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN
+ *++yyvsp = yylval;
+ YY_IGNORE_MAYBE_UNINITIALIZED_END
+-
++ *++yylsp = yylloc;
+ goto yynewstate;
+
+
+@@ -1503,7 +1451,7 @@
+ yylen = yyr2[yyn];
+
+ /* If YYLEN is nonzero, implement the default value of the action:
+- `$$ = $1'.
++ '$$ = $1'.
+
+ Otherwise, the following line sets YYVAL to garbage.
+ This behavior is undocumented and Bison
+@@ -1512,287 +1460,306 @@
+ GCC warning that YYVAL may be used uninitialized. */
+ yyval = yyvsp[1-yylen];
+
+-
++ /* Default location. */
++ YYLLOC_DEFAULT (yyloc, (yylsp - yylen), yylen);
+ YY_REDUCE_PRINT (yyn);
+ switch (yyn)
+ {
+ case 2:
+-/* Line 1787 of yacc.c */
+-#line 110 "dtc-parser.y"
++#line 109 "dtc-parser.y" /* yacc.c:1646 */
+ {
+- the_boot_info = build_boot_info((yyvsp[(3) - (4)].re), (yyvsp[(4) - (4)].node),
+- guess_boot_cpuid((yyvsp[(4) - (4)].node)));
++ (yyvsp[0].node)->is_plugin = (yyvsp[-2].is_plugin);
++ (yyvsp[0].node)->is_root = 1;
++ the_boot_info = build_boot_info((yyvsp[-1].re), (yyvsp[0].node),
++ guess_boot_cpuid((yyvsp[0].node)));
+ }
++#line 1477 "dtc-parser.tab.c" /* yacc.c:1646 */
+ break;
+
+ case 3:
+-/* Line 1787 of yacc.c */
+-#line 118 "dtc-parser.y"
++#line 119 "dtc-parser.y" /* yacc.c:1646 */
+ {
+- (yyval.re) = NULL;
++ (yyval.is_plugin) = 0;
+ }
++#line 1485 "dtc-parser.tab.c" /* yacc.c:1646 */
+ break;
+
+ case 4:
+-/* Line 1787 of yacc.c */
+-#line 122 "dtc-parser.y"
++#line 123 "dtc-parser.y" /* yacc.c:1646 */
+ {
+- (yyval.re) = chain_reserve_entry((yyvsp[(1) - (2)].re), (yyvsp[(2) - (2)].re));
++ (yyval.is_plugin) = 1;
+ }
++#line 1493 "dtc-parser.tab.c" /* yacc.c:1646 */
+ break;
+
+ case 5:
+-/* Line 1787 of yacc.c */
+-#line 129 "dtc-parser.y"
++#line 130 "dtc-parser.y" /* yacc.c:1646 */
+ {
+- (yyval.re) = build_reserve_entry((yyvsp[(2) - (4)].integer), (yyvsp[(3) - (4)].integer));
++ (yyval.re) = NULL;
+ }
++#line 1501 "dtc-parser.tab.c" /* yacc.c:1646 */
+ break;
+
+ case 6:
+-/* Line 1787 of yacc.c */
+-#line 133 "dtc-parser.y"
++#line 134 "dtc-parser.y" /* yacc.c:1646 */
+ {
+- add_label(&(yyvsp[(2) - (2)].re)->labels, (yyvsp[(1) - (2)].labelref));
+- (yyval.re) = (yyvsp[(2) - (2)].re);
++ (yyval.re) = chain_reserve_entry((yyvsp[-1].re), (yyvsp[0].re));
+ }
++#line 1509 "dtc-parser.tab.c" /* yacc.c:1646 */
+ break;
+
+ case 7:
+-/* Line 1787 of yacc.c */
+-#line 141 "dtc-parser.y"
++#line 141 "dtc-parser.y" /* yacc.c:1646 */
+ {
+- (yyval.node) = name_node((yyvsp[(2) - (2)].node), "");
++ (yyval.re) = build_reserve_entry((yyvsp[-2].integer), (yyvsp[-1].integer));
+ }
++#line 1517 "dtc-parser.tab.c" /* yacc.c:1646 */
+ break;
+
+ case 8:
+-/* Line 1787 of yacc.c */
+-#line 145 "dtc-parser.y"
++#line 145 "dtc-parser.y" /* yacc.c:1646 */
+ {
+- (yyval.node) = merge_nodes((yyvsp[(1) - (3)].node), (yyvsp[(3) - (3)].node));
++ add_label(&(yyvsp[0].re)->labels, (yyvsp[-1].labelref));
++ (yyval.re) = (yyvsp[0].re);
+ }
++#line 1526 "dtc-parser.tab.c" /* yacc.c:1646 */
+ break;
+
+ case 9:
+-/* Line 1787 of yacc.c */
+-#line 149 "dtc-parser.y"
++#line 153 "dtc-parser.y" /* yacc.c:1646 */
+ {
+- struct node *target = get_node_by_ref((yyvsp[(1) - (3)].node), (yyvsp[(2) - (3)].labelref));
+-
+- if (target)
+- merge_nodes(target, (yyvsp[(3) - (3)].node));
+- else
+- print_error("label or path, '%s', not found", (yyvsp[(2) - (3)].labelref));
+- (yyval.node) = (yyvsp[(1) - (3)].node);
++ (yyval.node) = name_node((yyvsp[0].node), "");
+ }
++#line 1534 "dtc-parser.tab.c" /* yacc.c:1646 */
+ break;
+
+ case 10:
+-/* Line 1787 of yacc.c */
+-#line 159 "dtc-parser.y"
++#line 157 "dtc-parser.y" /* yacc.c:1646 */
+ {
+- struct node *target = get_node_by_ref((yyvsp[(1) - (4)].node), (yyvsp[(3) - (4)].labelref));
+-
+- if (!target)
+- print_error("label or path, '%s', not found", (yyvsp[(3) - (4)].labelref));
+- else
+- delete_node(target);
+-
+- (yyval.node) = (yyvsp[(1) - (4)].node);
++ (yyval.node) = merge_nodes((yyvsp[-2].node), (yyvsp[0].node));
+ }
++#line 1542 "dtc-parser.tab.c" /* yacc.c:1646 */
+ break;
+
+ case 11:
+-/* Line 1787 of yacc.c */
+-#line 173 "dtc-parser.y"
++#line 161 "dtc-parser.y" /* yacc.c:1646 */
+ {
+- (yyval.node) = build_node((yyvsp[(2) - (5)].proplist), (yyvsp[(3) - (5)].nodelist));
++ struct node *target = get_node_by_ref((yyvsp[-2].node), (yyvsp[-1].labelref));
++
++ if (target)
++ merge_nodes(target, (yyvsp[0].node));
++ else
++ ERROR(&(yylsp[-1]), "Label or path %s not found", (yyvsp[-1].labelref));
++ (yyval.node) = (yyvsp[-2].node);
+ }
++#line 1556 "dtc-parser.tab.c" /* yacc.c:1646 */
+ break;
+
+ case 12:
+-/* Line 1787 of yacc.c */
+-#line 180 "dtc-parser.y"
++#line 171 "dtc-parser.y" /* yacc.c:1646 */
+ {
+- (yyval.proplist) = NULL;
++ struct node *target = get_node_by_ref((yyvsp[-3].node), (yyvsp[-1].labelref));
++
++ if (target)
++ delete_node(target);
++ else
++ ERROR(&(yylsp[-1]), "Label or path %s not found", (yyvsp[-1].labelref));
++
++
++ (yyval.node) = (yyvsp[-3].node);
+ }
++#line 1572 "dtc-parser.tab.c" /* yacc.c:1646 */
+ break;
+
+ case 13:
+-/* Line 1787 of yacc.c */
+-#line 184 "dtc-parser.y"
++#line 186 "dtc-parser.y" /* yacc.c:1646 */
+ {
+- (yyval.proplist) = chain_property((yyvsp[(2) - (2)].prop), (yyvsp[(1) - (2)].proplist));
++ (yyval.node) = build_node((yyvsp[-3].proplist), (yyvsp[-2].nodelist));
+ }
++#line 1580 "dtc-parser.tab.c" /* yacc.c:1646 */
+ break;
+
+ case 14:
+-/* Line 1787 of yacc.c */
+-#line 191 "dtc-parser.y"
++#line 193 "dtc-parser.y" /* yacc.c:1646 */
+ {
+- (yyval.prop) = build_property((yyvsp[(1) - (4)].propnodename), (yyvsp[(3) - (4)].data));
++ (yyval.proplist) = NULL;
+ }
++#line 1588 "dtc-parser.tab.c" /* yacc.c:1646 */
+ break;
+
+ case 15:
+-/* Line 1787 of yacc.c */
+-#line 195 "dtc-parser.y"
++#line 197 "dtc-parser.y" /* yacc.c:1646 */
+ {
+- (yyval.prop) = build_property((yyvsp[(1) - (2)].propnodename), empty_data);
++ (yyval.proplist) = chain_property((yyvsp[0].prop), (yyvsp[-1].proplist));
+ }
++#line 1596 "dtc-parser.tab.c" /* yacc.c:1646 */
+ break;
+
+ case 16:
+-/* Line 1787 of yacc.c */
+-#line 199 "dtc-parser.y"
++#line 204 "dtc-parser.y" /* yacc.c:1646 */
+ {
+- (yyval.prop) = build_property_delete((yyvsp[(2) - (3)].propnodename));
++ (yyval.prop) = build_property((yyvsp[-3].propnodename), (yyvsp[-1].data));
+ }
++#line 1604 "dtc-parser.tab.c" /* yacc.c:1646 */
+ break;
+
+ case 17:
+-/* Line 1787 of yacc.c */
+-#line 203 "dtc-parser.y"
++#line 208 "dtc-parser.y" /* yacc.c:1646 */
+ {
+- add_label(&(yyvsp[(2) - (2)].prop)->labels, (yyvsp[(1) - (2)].labelref));
+- (yyval.prop) = (yyvsp[(2) - (2)].prop);
++ (yyval.prop) = build_property((yyvsp[-1].propnodename), empty_data);
+ }
++#line 1612 "dtc-parser.tab.c" /* yacc.c:1646 */
+ break;
+
+ case 18:
+-/* Line 1787 of yacc.c */
+-#line 211 "dtc-parser.y"
++#line 212 "dtc-parser.y" /* yacc.c:1646 */
+ {
+- (yyval.data) = data_merge((yyvsp[(1) - (2)].data), (yyvsp[(2) - (2)].data));
++ (yyval.prop) = build_property_delete((yyvsp[-1].propnodename));
+ }
++#line 1620 "dtc-parser.tab.c" /* yacc.c:1646 */
+ break;
+
+ case 19:
+-/* Line 1787 of yacc.c */
+-#line 215 "dtc-parser.y"
++#line 216 "dtc-parser.y" /* yacc.c:1646 */
+ {
+- (yyval.data) = data_merge((yyvsp[(1) - (3)].data), (yyvsp[(2) - (3)].array).data);
++ add_label(&(yyvsp[0].prop)->labels, (yyvsp[-1].labelref));
++ (yyval.prop) = (yyvsp[0].prop);
+ }
++#line 1629 "dtc-parser.tab.c" /* yacc.c:1646 */
+ break;
+
+ case 20:
+-/* Line 1787 of yacc.c */
+-#line 219 "dtc-parser.y"
++#line 224 "dtc-parser.y" /* yacc.c:1646 */
+ {
+- (yyval.data) = data_merge((yyvsp[(1) - (4)].data), (yyvsp[(3) - (4)].data));
++ (yyval.data) = data_merge((yyvsp[-1].data), (yyvsp[0].data));
+ }
++#line 1637 "dtc-parser.tab.c" /* yacc.c:1646 */
+ break;
+
+ case 21:
+-/* Line 1787 of yacc.c */
+-#line 223 "dtc-parser.y"
++#line 228 "dtc-parser.y" /* yacc.c:1646 */
+ {
+- (yyval.data) = data_add_marker((yyvsp[(1) - (2)].data), REF_PATH, (yyvsp[(2) - (2)].labelref));
++ (yyval.data) = data_merge((yyvsp[-2].data), (yyvsp[-1].array).data);
+ }
++#line 1645 "dtc-parser.tab.c" /* yacc.c:1646 */
+ break;
+
+ case 22:
+-/* Line 1787 of yacc.c */
+-#line 227 "dtc-parser.y"
++#line 232 "dtc-parser.y" /* yacc.c:1646 */
+ {
+- FILE *f = srcfile_relative_open((yyvsp[(4) - (9)].data).val, NULL);
++ (yyval.data) = data_merge((yyvsp[-3].data), (yyvsp[-1].data));
++ }
++#line 1653 "dtc-parser.tab.c" /* yacc.c:1646 */
++ break;
++
++ case 23:
++#line 236 "dtc-parser.y" /* yacc.c:1646 */
++ {
++ (yyval.data) = data_add_marker((yyvsp[-1].data), REF_PATH, (yyvsp[0].labelref));
++ }
++#line 1661 "dtc-parser.tab.c" /* yacc.c:1646 */
++ break;
++
++ case 24:
++#line 240 "dtc-parser.y" /* yacc.c:1646 */
++ {
++ FILE *f = srcfile_relative_open((yyvsp[-5].data).val, NULL);
+ struct data d;
+
+- if ((yyvsp[(6) - (9)].integer) != 0)
+- if (fseek(f, (yyvsp[(6) - (9)].integer), SEEK_SET) != 0)
+- print_error("Couldn't seek to offset %llu in \"%s\": %s",
+- (unsigned long long)(yyvsp[(6) - (9)].integer),
+- (yyvsp[(4) - (9)].data).val,
+- strerror(errno));
++ if ((yyvsp[-3].integer) != 0)
++ if (fseek(f, (yyvsp[-3].integer), SEEK_SET) != 0)
++ die("Couldn't seek to offset %llu in \"%s\": %s",
++ (unsigned long long)(yyvsp[-3].integer), (yyvsp[-5].data).val,
++ strerror(errno));
+
+- d = data_copy_file(f, (yyvsp[(8) - (9)].integer));
++ d = data_copy_file(f, (yyvsp[-1].integer));
+
+- (yyval.data) = data_merge((yyvsp[(1) - (9)].data), d);
++ (yyval.data) = data_merge((yyvsp[-8].data), d);
+ fclose(f);
+ }
++#line 1681 "dtc-parser.tab.c" /* yacc.c:1646 */
+ break;
+
+- case 23:
+-/* Line 1787 of yacc.c */
+-#line 244 "dtc-parser.y"
++ case 25:
++#line 256 "dtc-parser.y" /* yacc.c:1646 */
+ {
+- FILE *f = srcfile_relative_open((yyvsp[(4) - (5)].data).val, NULL);
++ FILE *f = srcfile_relative_open((yyvsp[-1].data).val, NULL);
+ struct data d = empty_data;
+
+ d = data_copy_file(f, -1);
+
+- (yyval.data) = data_merge((yyvsp[(1) - (5)].data), d);
++ (yyval.data) = data_merge((yyvsp[-4].data), d);
+ fclose(f);
+ }
++#line 1695 "dtc-parser.tab.c" /* yacc.c:1646 */
+ break;
+
+- case 24:
+-/* Line 1787 of yacc.c */
+-#line 254 "dtc-parser.y"
++ case 26:
++#line 266 "dtc-parser.y" /* yacc.c:1646 */
+ {
+- (yyval.data) = data_add_marker((yyvsp[(1) - (2)].data), LABEL, (yyvsp[(2) - (2)].labelref));
++ (yyval.data) = data_add_marker((yyvsp[-1].data), LABEL, (yyvsp[0].labelref));
+ }
++#line 1703 "dtc-parser.tab.c" /* yacc.c:1646 */
+ break;
+
+- case 25:
+-/* Line 1787 of yacc.c */
+-#line 261 "dtc-parser.y"
++ case 27:
++#line 273 "dtc-parser.y" /* yacc.c:1646 */
+ {
+ (yyval.data) = empty_data;
+ }
++#line 1711 "dtc-parser.tab.c" /* yacc.c:1646 */
+ break;
+
+- case 26:
+-/* Line 1787 of yacc.c */
+-#line 265 "dtc-parser.y"
++ case 28:
++#line 277 "dtc-parser.y" /* yacc.c:1646 */
+ {
+- (yyval.data) = (yyvsp[(1) - (2)].data);
++ (yyval.data) = (yyvsp[-1].data);
+ }
++#line 1719 "dtc-parser.tab.c" /* yacc.c:1646 */
+ break;
+
+- case 27:
+-/* Line 1787 of yacc.c */
+-#line 269 "dtc-parser.y"
++ case 29:
++#line 281 "dtc-parser.y" /* yacc.c:1646 */
+ {
+- (yyval.data) = data_add_marker((yyvsp[(1) - (2)].data), LABEL, (yyvsp[(2) - (2)].labelref));
++ (yyval.data) = data_add_marker((yyvsp[-1].data), LABEL, (yyvsp[0].labelref));
+ }
++#line 1727 "dtc-parser.tab.c" /* yacc.c:1646 */
+ break;
+
+- case 28:
+-/* Line 1787 of yacc.c */
+-#line 276 "dtc-parser.y"
++ case 30:
++#line 288 "dtc-parser.y" /* yacc.c:1646 */
+ {
+- (yyval.array).data = empty_data;
+- (yyval.array).bits = eval_literal((yyvsp[(2) - (3)].literal), 0, 7);
++ unsigned long long bits;
+
+- if (((yyval.array).bits != 8) &&
+- ((yyval.array).bits != 16) &&
+- ((yyval.array).bits != 32) &&
+- ((yyval.array).bits != 64))
+- {
+- print_error("Only 8, 16, 32 and 64-bit elements"
+- " are currently supported");
+- (yyval.array).bits = 32;
++ bits = (yyvsp[-1].integer);
++
++ if ((bits != 8) && (bits != 16) &&
++ (bits != 32) && (bits != 64)) {
++ ERROR(&(yylsp[-1]), "Array elements must be"
++ " 8, 16, 32 or 64-bits");
++ bits = 32;
+ }
++
++ (yyval.array).data = empty_data;
++ (yyval.array).bits = bits;
+ }
++#line 1747 "dtc-parser.tab.c" /* yacc.c:1646 */
+ break;
+
+- case 29:
+-/* Line 1787 of yacc.c */
+-#line 291 "dtc-parser.y"
++ case 31:
++#line 304 "dtc-parser.y" /* yacc.c:1646 */
+ {
+ (yyval.array).data = empty_data;
+ (yyval.array).bits = 32;
+ }
++#line 1756 "dtc-parser.tab.c" /* yacc.c:1646 */
+ break;
+
+- case 30:
+-/* Line 1787 of yacc.c */
+-#line 296 "dtc-parser.y"
++ case 32:
++#line 309 "dtc-parser.y" /* yacc.c:1646 */
+ {
+- if ((yyvsp[(1) - (2)].array).bits < 64) {
+- uint64_t mask = (1ULL << (yyvsp[(1) - (2)].array).bits) - 1;
++ if ((yyvsp[-1].array).bits < 64) {
++ uint64_t mask = (1ULL << (yyvsp[-1].array).bits) - 1;
+ /*
+ * Bits above mask must either be all zero
+ * (positive within range of mask) or all one
+@@ -1801,275 +1768,258 @@
+ * within the mask to one (i.e. | in the
+ * mask), all bits are one.
+ */
+- if (((yyvsp[(2) - (2)].integer) > mask) && (((yyvsp[(2) - (2)].integer) | mask) != -1ULL))
+- print_error(
+- "integer value out of range "
+- "%016lx (%d bits)", (yyvsp[(1) - (2)].array).bits);
++ if (((yyvsp[0].integer) > mask) && (((yyvsp[0].integer) | mask) != -1ULL))
++ ERROR(&(yylsp[0]), "Value out of range for"
++ " %d-bit array element", (yyvsp[-1].array).bits);
+ }
+
+- (yyval.array).data = data_append_integer((yyvsp[(1) - (2)].array).data, (yyvsp[(2) - (2)].integer), (yyvsp[(1) - (2)].array).bits);
++ (yyval.array).data = data_append_integer((yyvsp[-1].array).data, (yyvsp[0].integer), (yyvsp[-1].array).bits);
+ }
++#line 1779 "dtc-parser.tab.c" /* yacc.c:1646 */
+ break;
+
+- case 31:
+-/* Line 1787 of yacc.c */
+-#line 316 "dtc-parser.y"
++ case 33:
++#line 328 "dtc-parser.y" /* yacc.c:1646 */
+ {
+- uint64_t val = ~0ULL >> (64 - (yyvsp[(1) - (2)].array).bits);
++ uint64_t val = ~0ULL >> (64 - (yyvsp[-1].array).bits);
+
+- if ((yyvsp[(1) - (2)].array).bits == 32)
+- (yyvsp[(1) - (2)].array).data = data_add_marker((yyvsp[(1) - (2)].array).data,
++ if ((yyvsp[-1].array).bits == 32)
++ (yyvsp[-1].array).data = data_add_marker((yyvsp[-1].array).data,
+ REF_PHANDLE,
+- (yyvsp[(2) - (2)].labelref));
++ (yyvsp[0].labelref));
+ else
+- print_error("References are only allowed in "
++ ERROR(&(yylsp[0]), "References are only allowed in "
+ "arrays with 32-bit elements.");
+
+- (yyval.array).data = data_append_integer((yyvsp[(1) - (2)].array).data, val, (yyvsp[(1) - (2)].array).bits);
+- }
+- break;
+-
+- case 32:
+-/* Line 1787 of yacc.c */
+-#line 330 "dtc-parser.y"
+- {
+- (yyval.array).data = data_add_marker((yyvsp[(1) - (2)].array).data, LABEL, (yyvsp[(2) - (2)].labelref));
+- }
+- break;
+-
+- case 33:
+-/* Line 1787 of yacc.c */
+-#line 337 "dtc-parser.y"
+- {
+- (yyval.integer) = eval_literal((yyvsp[(1) - (1)].literal), 0, 64);
++ (yyval.array).data = data_append_integer((yyvsp[-1].array).data, val, (yyvsp[-1].array).bits);
+ }
++#line 1797 "dtc-parser.tab.c" /* yacc.c:1646 */
+ break;
+
+ case 34:
+-/* Line 1787 of yacc.c */
+-#line 341 "dtc-parser.y"
++#line 342 "dtc-parser.y" /* yacc.c:1646 */
+ {
+- (yyval.integer) = eval_char_literal((yyvsp[(1) - (1)].literal));
++ (yyval.array).data = data_add_marker((yyvsp[-1].array).data, LABEL, (yyvsp[0].labelref));
+ }
++#line 1805 "dtc-parser.tab.c" /* yacc.c:1646 */
+ break;
+
+- case 35:
+-/* Line 1787 of yacc.c */
+-#line 345 "dtc-parser.y"
++ case 37:
++#line 351 "dtc-parser.y" /* yacc.c:1646 */
+ {
+- (yyval.integer) = (yyvsp[(2) - (3)].integer);
++ (yyval.integer) = (yyvsp[-1].integer);
+ }
+- break;
+-
+- case 38:
+-/* Line 1787 of yacc.c */
+-#line 356 "dtc-parser.y"
+- { (yyval.integer) = (yyvsp[(1) - (5)].integer) ? (yyvsp[(3) - (5)].integer) : (yyvsp[(5) - (5)].integer); }
++#line 1813 "dtc-parser.tab.c" /* yacc.c:1646 */
+ break;
+
+ case 40:
+-/* Line 1787 of yacc.c */
+-#line 361 "dtc-parser.y"
+- { (yyval.integer) = (yyvsp[(1) - (3)].integer) || (yyvsp[(3) - (3)].integer); }
++#line 362 "dtc-parser.y" /* yacc.c:1646 */
++ { (yyval.integer) = (yyvsp[-4].integer) ? (yyvsp[-2].integer) : (yyvsp[0].integer); }
++#line 1819 "dtc-parser.tab.c" /* yacc.c:1646 */
+ break;
+
+ case 42:
+-/* Line 1787 of yacc.c */
+-#line 366 "dtc-parser.y"
+- { (yyval.integer) = (yyvsp[(1) - (3)].integer) && (yyvsp[(3) - (3)].integer); }
++#line 367 "dtc-parser.y" /* yacc.c:1646 */
++ { (yyval.integer) = (yyvsp[-2].integer) || (yyvsp[0].integer); }
++#line 1825 "dtc-parser.tab.c" /* yacc.c:1646 */
+ break;
+
+ case 44:
+-/* Line 1787 of yacc.c */
+-#line 371 "dtc-parser.y"
+- { (yyval.integer) = (yyvsp[(1) - (3)].integer) | (yyvsp[(3) - (3)].integer); }
++#line 372 "dtc-parser.y" /* yacc.c:1646 */
++ { (yyval.integer) = (yyvsp[-2].integer) && (yyvsp[0].integer); }
++#line 1831 "dtc-parser.tab.c" /* yacc.c:1646 */
+ break;
+
+ case 46:
+-/* Line 1787 of yacc.c */
+-#line 376 "dtc-parser.y"
+- { (yyval.integer) = (yyvsp[(1) - (3)].integer) ^ (yyvsp[(3) - (3)].integer); }
++#line 377 "dtc-parser.y" /* yacc.c:1646 */
++ { (yyval.integer) = (yyvsp[-2].integer) | (yyvsp[0].integer); }
++#line 1837 "dtc-parser.tab.c" /* yacc.c:1646 */
+ break;
+
+ case 48:
+-/* Line 1787 of yacc.c */
+-#line 381 "dtc-parser.y"
+- { (yyval.integer) = (yyvsp[(1) - (3)].integer) & (yyvsp[(3) - (3)].integer); }
++#line 382 "dtc-parser.y" /* yacc.c:1646 */
++ { (yyval.integer) = (yyvsp[-2].integer) ^ (yyvsp[0].integer); }
++#line 1843 "dtc-parser.tab.c" /* yacc.c:1646 */
+ break;
+
+ case 50:
+-/* Line 1787 of yacc.c */
+-#line 386 "dtc-parser.y"
+- { (yyval.integer) = (yyvsp[(1) - (3)].integer) == (yyvsp[(3) - (3)].integer); }
++#line 387 "dtc-parser.y" /* yacc.c:1646 */
++ { (yyval.integer) = (yyvsp[-2].integer) & (yyvsp[0].integer); }
++#line 1849 "dtc-parser.tab.c" /* yacc.c:1646 */
+ break;
+
+- case 51:
+-/* Line 1787 of yacc.c */
+-#line 387 "dtc-parser.y"
+- { (yyval.integer) = (yyvsp[(1) - (3)].integer) != (yyvsp[(3) - (3)].integer); }
++ case 52:
++#line 392 "dtc-parser.y" /* yacc.c:1646 */
++ { (yyval.integer) = (yyvsp[-2].integer) == (yyvsp[0].integer); }
++#line 1855 "dtc-parser.tab.c" /* yacc.c:1646 */
+ break;
+
+ case 53:
+-/* Line 1787 of yacc.c */
+-#line 392 "dtc-parser.y"
+- { (yyval.integer) = (yyvsp[(1) - (3)].integer) < (yyvsp[(3) - (3)].integer); }
+- break;
+-
+- case 54:
+-/* Line 1787 of yacc.c */
+-#line 393 "dtc-parser.y"
+- { (yyval.integer) = (yyvsp[(1) - (3)].integer) > (yyvsp[(3) - (3)].integer); }
++#line 393 "dtc-parser.y" /* yacc.c:1646 */
++ { (yyval.integer) = (yyvsp[-2].integer) != (yyvsp[0].integer); }
++#line 1861 "dtc-parser.tab.c" /* yacc.c:1646 */
+ break;
+
+ case 55:
+-/* Line 1787 of yacc.c */
+-#line 394 "dtc-parser.y"
+- { (yyval.integer) = (yyvsp[(1) - (3)].integer) <= (yyvsp[(3) - (3)].integer); }
++#line 398 "dtc-parser.y" /* yacc.c:1646 */
++ { (yyval.integer) = (yyvsp[-2].integer) < (yyvsp[0].integer); }
++#line 1867 "dtc-parser.tab.c" /* yacc.c:1646 */
+ break;
+
+ case 56:
+-/* Line 1787 of yacc.c */
+-#line 395 "dtc-parser.y"
+- { (yyval.integer) = (yyvsp[(1) - (3)].integer) >= (yyvsp[(3) - (3)].integer); }
++#line 399 "dtc-parser.y" /* yacc.c:1646 */
++ { (yyval.integer) = (yyvsp[-2].integer) > (yyvsp[0].integer); }
++#line 1873 "dtc-parser.tab.c" /* yacc.c:1646 */
+ break;
+
+ case 57:
+-/* Line 1787 of yacc.c */
+-#line 399 "dtc-parser.y"
+- { (yyval.integer) = (yyvsp[(1) - (3)].integer) << (yyvsp[(3) - (3)].integer); }
++#line 400 "dtc-parser.y" /* yacc.c:1646 */
++ { (yyval.integer) = (yyvsp[-2].integer) <= (yyvsp[0].integer); }
++#line 1879 "dtc-parser.tab.c" /* yacc.c:1646 */
+ break;
+
+ case 58:
+-/* Line 1787 of yacc.c */
+-#line 400 "dtc-parser.y"
+- { (yyval.integer) = (yyvsp[(1) - (3)].integer) >> (yyvsp[(3) - (3)].integer); }
++#line 401 "dtc-parser.y" /* yacc.c:1646 */
++ { (yyval.integer) = (yyvsp[-2].integer) >= (yyvsp[0].integer); }
++#line 1885 "dtc-parser.tab.c" /* yacc.c:1646 */
+ break;
+
+- case 60:
+-/* Line 1787 of yacc.c */
+-#line 405 "dtc-parser.y"
+- { (yyval.integer) = (yyvsp[(1) - (3)].integer) + (yyvsp[(3) - (3)].integer); }
++ case 59:
++#line 405 "dtc-parser.y" /* yacc.c:1646 */
++ { (yyval.integer) = (yyvsp[-2].integer) << (yyvsp[0].integer); }
++#line 1891 "dtc-parser.tab.c" /* yacc.c:1646 */
+ break;
+
+- case 61:
+-/* Line 1787 of yacc.c */
+-#line 406 "dtc-parser.y"
+- { (yyval.integer) = (yyvsp[(1) - (3)].integer) - (yyvsp[(3) - (3)].integer); }
++ case 60:
++#line 406 "dtc-parser.y" /* yacc.c:1646 */
++ { (yyval.integer) = (yyvsp[-2].integer) >> (yyvsp[0].integer); }
++#line 1897 "dtc-parser.tab.c" /* yacc.c:1646 */
+ break;
+
+- case 63:
+-/* Line 1787 of yacc.c */
+-#line 411 "dtc-parser.y"
+- { (yyval.integer) = (yyvsp[(1) - (3)].integer) * (yyvsp[(3) - (3)].integer); }
++ case 62:
++#line 411 "dtc-parser.y" /* yacc.c:1646 */
++ { (yyval.integer) = (yyvsp[-2].integer) + (yyvsp[0].integer); }
++#line 1903 "dtc-parser.tab.c" /* yacc.c:1646 */
+ break;
+
+- case 64:
+-/* Line 1787 of yacc.c */
+-#line 412 "dtc-parser.y"
+- { (yyval.integer) = (yyvsp[(1) - (3)].integer) / (yyvsp[(3) - (3)].integer); }
++ case 63:
++#line 412 "dtc-parser.y" /* yacc.c:1646 */
++ { (yyval.integer) = (yyvsp[-2].integer) - (yyvsp[0].integer); }
++#line 1909 "dtc-parser.tab.c" /* yacc.c:1646 */
+ break;
+
+ case 65:
+-/* Line 1787 of yacc.c */
+-#line 413 "dtc-parser.y"
+- { (yyval.integer) = (yyvsp[(1) - (3)].integer) % (yyvsp[(3) - (3)].integer); }
++#line 417 "dtc-parser.y" /* yacc.c:1646 */
++ { (yyval.integer) = (yyvsp[-2].integer) * (yyvsp[0].integer); }
++#line 1915 "dtc-parser.tab.c" /* yacc.c:1646 */
+ break;
+
+- case 68:
+-/* Line 1787 of yacc.c */
+-#line 419 "dtc-parser.y"
+- { (yyval.integer) = -(yyvsp[(2) - (2)].integer); }
++ case 66:
++#line 418 "dtc-parser.y" /* yacc.c:1646 */
++ { (yyval.integer) = (yyvsp[-2].integer) / (yyvsp[0].integer); }
++#line 1921 "dtc-parser.tab.c" /* yacc.c:1646 */
+ break;
+
+- case 69:
+-/* Line 1787 of yacc.c */
+-#line 420 "dtc-parser.y"
+- { (yyval.integer) = ~(yyvsp[(2) - (2)].integer); }
++ case 67:
++#line 419 "dtc-parser.y" /* yacc.c:1646 */
++ { (yyval.integer) = (yyvsp[-2].integer) % (yyvsp[0].integer); }
++#line 1927 "dtc-parser.tab.c" /* yacc.c:1646 */
+ break;
+
+ case 70:
+-/* Line 1787 of yacc.c */
+-#line 421 "dtc-parser.y"
+- { (yyval.integer) = !(yyvsp[(2) - (2)].integer); }
++#line 425 "dtc-parser.y" /* yacc.c:1646 */
++ { (yyval.integer) = -(yyvsp[0].integer); }
++#line 1933 "dtc-parser.tab.c" /* yacc.c:1646 */
+ break;
+
+ case 71:
+-/* Line 1787 of yacc.c */
+-#line 426 "dtc-parser.y"
+- {
+- (yyval.data) = empty_data;
+- }
++#line 426 "dtc-parser.y" /* yacc.c:1646 */
++ { (yyval.integer) = ~(yyvsp[0].integer); }
++#line 1939 "dtc-parser.tab.c" /* yacc.c:1646 */
+ break;
+
+ case 72:
+-/* Line 1787 of yacc.c */
+-#line 430 "dtc-parser.y"
+- {
+- (yyval.data) = data_append_byte((yyvsp[(1) - (2)].data), (yyvsp[(2) - (2)].byte));
+- }
++#line 427 "dtc-parser.y" /* yacc.c:1646 */
++ { (yyval.integer) = !(yyvsp[0].integer); }
++#line 1945 "dtc-parser.tab.c" /* yacc.c:1646 */
+ break;
+
+ case 73:
+-/* Line 1787 of yacc.c */
+-#line 434 "dtc-parser.y"
++#line 432 "dtc-parser.y" /* yacc.c:1646 */
+ {
+- (yyval.data) = data_add_marker((yyvsp[(1) - (2)].data), LABEL, (yyvsp[(2) - (2)].labelref));
++ (yyval.data) = empty_data;
+ }
++#line 1953 "dtc-parser.tab.c" /* yacc.c:1646 */
+ break;
+
+ case 74:
+-/* Line 1787 of yacc.c */
+-#line 441 "dtc-parser.y"
++#line 436 "dtc-parser.y" /* yacc.c:1646 */
+ {
+- (yyval.nodelist) = NULL;
++ (yyval.data) = data_append_byte((yyvsp[-1].data), (yyvsp[0].byte));
+ }
++#line 1961 "dtc-parser.tab.c" /* yacc.c:1646 */
+ break;
+
+ case 75:
+-/* Line 1787 of yacc.c */
+-#line 445 "dtc-parser.y"
++#line 440 "dtc-parser.y" /* yacc.c:1646 */
+ {
+- (yyval.nodelist) = chain_node((yyvsp[(1) - (2)].node), (yyvsp[(2) - (2)].nodelist));
++ (yyval.data) = data_add_marker((yyvsp[-1].data), LABEL, (yyvsp[0].labelref));
+ }
++#line 1969 "dtc-parser.tab.c" /* yacc.c:1646 */
+ break;
+
+ case 76:
+-/* Line 1787 of yacc.c */
+-#line 449 "dtc-parser.y"
++#line 447 "dtc-parser.y" /* yacc.c:1646 */
+ {
+- print_error("syntax error: properties must precede subnodes");
+- YYERROR;
++ (yyval.nodelist) = NULL;
+ }
++#line 1977 "dtc-parser.tab.c" /* yacc.c:1646 */
+ break;
+
+ case 77:
+-/* Line 1787 of yacc.c */
+-#line 457 "dtc-parser.y"
++#line 451 "dtc-parser.y" /* yacc.c:1646 */
+ {
+- (yyval.node) = name_node((yyvsp[(2) - (2)].node), (yyvsp[(1) - (2)].propnodename));
++ (yyval.nodelist) = chain_node((yyvsp[-1].node), (yyvsp[0].nodelist));
+ }
++#line 1985 "dtc-parser.tab.c" /* yacc.c:1646 */
+ break;
+
+ case 78:
+-/* Line 1787 of yacc.c */
+-#line 461 "dtc-parser.y"
++#line 455 "dtc-parser.y" /* yacc.c:1646 */
+ {
+- (yyval.node) = name_node(build_node_delete(), (yyvsp[(2) - (3)].propnodename));
++ ERROR(&(yylsp[0]), "Properties must precede subnodes");
++ YYERROR;
+ }
++#line 1994 "dtc-parser.tab.c" /* yacc.c:1646 */
+ break;
+
+ case 79:
+-/* Line 1787 of yacc.c */
+-#line 465 "dtc-parser.y"
++#line 463 "dtc-parser.y" /* yacc.c:1646 */
+ {
+- add_label(&(yyvsp[(2) - (2)].node)->labels, (yyvsp[(1) - (2)].labelref));
+- (yyval.node) = (yyvsp[(2) - (2)].node);
++ (yyval.node) = name_node((yyvsp[0].node), (yyvsp[-1].propnodename));
+ }
++#line 2002 "dtc-parser.tab.c" /* yacc.c:1646 */
+ break;
+
++ case 80:
++#line 467 "dtc-parser.y" /* yacc.c:1646 */
++ {
++ (yyval.node) = name_node(build_node_delete(), (yyvsp[-1].propnodename));
++ }
++#line 2010 "dtc-parser.tab.c" /* yacc.c:1646 */
++ break;
++
++ case 81:
++#line 471 "dtc-parser.y" /* yacc.c:1646 */
++ {
++ add_label(&(yyvsp[0].node)->labels, (yyvsp[-1].labelref));
++ (yyval.node) = (yyvsp[0].node);
++ }
++#line 2019 "dtc-parser.tab.c" /* yacc.c:1646 */
++ break;
+
+-/* Line 1787 of yacc.c */
+-#line 2073 "dtc-parser.tab.c"
++
++#line 2023 "dtc-parser.tab.c" /* yacc.c:1646 */
+ default: break;
+ }
+ /* User semantic actions sometimes alter yychar, and that requires
+@@ -2090,8 +2040,9 @@
+ YY_STACK_PRINT (yyss, yyssp);
+
+ *++yyvsp = yyval;
++ *++yylsp = yyloc;
+
+- /* Now `shift' the result of the reduction. Determine what state
++ /* Now 'shift' the result of the reduction. Determine what state
+ that goes to, based on the state we popped back to and the rule
+ number reduced by. */
+
+@@ -2106,9 +2057,9 @@
+ goto yynewstate;
+
+
+-/*------------------------------------.
+-| yyerrlab -- here on detecting error |
+-`------------------------------------*/
++/*--------------------------------------.
++| yyerrlab -- here on detecting error. |
++`--------------------------------------*/
+ yyerrlab:
+ /* Make sure we have latest lookahead translation. See comments at
+ user semantic actions for why this is necessary. */
+@@ -2154,25 +2105,25 @@
+ #endif
+ }
+
+-
++ yyerror_range[1] = yylloc;
+
+ if (yyerrstatus == 3)
+ {
+ /* If just tried and failed to reuse lookahead token after an
+- error, discard it. */
++ error, discard it. */
+
+ if (yychar <= YYEOF)
+- {
+- /* Return failure if at end of input. */
+- if (yychar == YYEOF)
+- YYABORT;
+- }
++ {
++ /* Return failure if at end of input. */
++ if (yychar == YYEOF)
++ YYABORT;
++ }
+ else
+- {
+- yydestruct ("Error: discarding",
+- yytoken, &yylval);
+- yychar = YYEMPTY;
+- }
++ {
++ yydestruct ("Error: discarding",
++ yytoken, &yylval, &yylloc);
++ yychar = YYEMPTY;
++ }
+ }
+
+ /* Else will try to reuse lookahead token after shifting the error
+@@ -2191,7 +2142,8 @@
+ if (/*CONSTCOND*/ 0)
+ goto yyerrorlab;
+
+- /* Do not reclaim the symbols of the rule which action triggered
++ yyerror_range[1] = yylsp[1-yylen];
++ /* Do not reclaim the symbols of the rule whose action triggered
+ this YYERROR. */
+ YYPOPSTACK (yylen);
+ yylen = 0;
+@@ -2204,29 +2156,29 @@
+ | yyerrlab1 -- common code for both syntax error and YYERROR. |
+ `-------------------------------------------------------------*/
+ yyerrlab1:
+- yyerrstatus = 3; /* Each real token shifted decrements this. */
++ yyerrstatus = 3; /* Each real token shifted decrements this. */
+
+ for (;;)
+ {
+ yyn = yypact[yystate];
+ if (!yypact_value_is_default (yyn))
+- {
+- yyn += YYTERROR;
+- if (0 <= yyn && yyn <= YYLAST && yycheck[yyn] == YYTERROR)
+- {
+- yyn = yytable[yyn];
+- if (0 < yyn)
+- break;
+- }
+- }
++ {
++ yyn += YYTERROR;
++ if (0 <= yyn && yyn <= YYLAST && yycheck[yyn] == YYTERROR)
++ {
++ yyn = yytable[yyn];
++ if (0 < yyn)
++ break;
++ }
++ }
+
+ /* Pop the current state because it cannot handle the error token. */
+ if (yyssp == yyss)
+- YYABORT;
+-
++ YYABORT;
+
++ yyerror_range[1] = *yylsp;
+ yydestruct ("Error: popping",
+- yystos[yystate], yyvsp);
++ yystos[yystate], yyvsp, yylsp);
+ YYPOPSTACK (1);
+ yystate = *yyssp;
+ YY_STACK_PRINT (yyss, yyssp);
+@@ -2236,6 +2188,11 @@
+ *++yyvsp = yylval;
+ YY_IGNORE_MAYBE_UNINITIALIZED_END
+
++ yyerror_range[2] = yylloc;
++ /* Using YYLLOC is tempting, but would change the location of
++ the lookahead. YYLOC is available though. */
++ YYLLOC_DEFAULT (yyloc, yyerror_range, 2);
++ *++yylsp = yyloc;
+
+ /* Shift the error token. */
+ YY_SYMBOL_PRINT ("Shifting", yystos[yyn], yyvsp, yylsp);
+@@ -2275,16 +2232,16 @@
+ user semantic actions for why this is necessary. */
+ yytoken = YYTRANSLATE (yychar);
+ yydestruct ("Cleanup: discarding lookahead",
+- yytoken, &yylval);
++ yytoken, &yylval, &yylloc);
+ }
+- /* Do not reclaim the symbols of the rule which action triggered
++ /* Do not reclaim the symbols of the rule whose action triggered
+ this YYABORT or YYACCEPT. */
+ YYPOPSTACK (yylen);
+ YY_STACK_PRINT (yyss, yyssp);
+ while (yyssp != yyss)
+ {
+ yydestruct ("Cleanup: popping",
+- yystos[*yyssp], yyvsp);
++ yystos[*yyssp], yyvsp, yylsp);
+ YYPOPSTACK (1);
+ }
+ #ifndef yyoverflow
+@@ -2295,72 +2252,12 @@
+ if (yymsg != yymsgbuf)
+ YYSTACK_FREE (yymsg);
+ #endif
+- /* Make sure YYID is used. */
+- return YYID (yyresult);
++ return yyresult;
+ }
++#line 477 "dtc-parser.y" /* yacc.c:1906 */
+
+
+-/* Line 2050 of yacc.c */
+-#line 471 "dtc-parser.y"
+-
+-
+-void print_error(char const *fmt, ...)
++void yyerror(char const *s)
+ {
+- va_list va;
+-
+- va_start(va, fmt);
+- srcpos_verror(&yylloc, fmt, va);
+- va_end(va);
+-
+- treesource_error = 1;
+-}
+-
+-void yyerror(char const *s) {
+- print_error("%s", s);
+-}
+-
+-static unsigned long long eval_literal(const char *s, int base, int bits)
+-{
+- unsigned long long val;
+- char *e;
+-
+- errno = 0;
+- val = strtoull(s, &e, base);
+- if (*e) {
+- size_t uls = strspn(e, "UL");
+- if (e[uls])
+- print_error("bad characters in literal");
+- }
+- if ((errno == ERANGE)
+- || ((bits < 64) && (val >= (1ULL << bits))))
+- print_error("literal out of range");
+- else if (errno != 0)
+- print_error("bad literal");
+- return val;
+-}
+-
+-static unsigned char eval_char_literal(const char *s)
+-{
+- int i = 1;
+- char c = s[0];
+-
+- if (c == '\0')
+- {
+- print_error("empty character literal");
+- return 0;
+- }
+-
+- /*
+- * If the first character in the character literal is a \ then process
+- * the remaining characters as an escape encoding. If the first
+- * character is neither an escape or a terminator it should be the only
+- * character in the literal and will be returned.
+- */
+- if (c == '\\')
+- c = get_escape_char(s, &i);
+-
+- if (s[i] != '\0')
+- print_error("malformed character literal");
+-
+- return c;
++ ERROR(&yylloc, "%s", s);
+ }
+diff -Nur linux-4.1.3/scripts/dtc/dtc-parser.tab.h_shipped linux-xbian-rpi/scripts/dtc/dtc-parser.tab.h_shipped
+--- linux-4.1.3/scripts/dtc/dtc-parser.tab.h_shipped 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/scripts/dtc/dtc-parser.tab.h_shipped 2015-07-28 01:20:58.461099590 +0200
+@@ -1,19 +1,19 @@
+-/* A Bison parser, made by GNU Bison 2.7.12-4996. */
++/* A Bison parser, made by GNU Bison 3.0.2. */
+
+ /* Bison interface for Yacc-like parsers in C
+-
+- Copyright (C) 1984, 1989-1990, 2000-2013 Free Software Foundation, Inc.
+-
++
++ Copyright (C) 1984, 1989-1990, 2000-2013 Free Software Foundation, Inc.
++
+ This program is free software: you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation, either version 3 of the License, or
+ (at your option) any later version.
+-
++
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+-
++
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+@@ -26,13 +26,13 @@
+ special exception, which will cause the skeleton and the resulting
+ Bison output files to be licensed under the GNU General Public
+ License without this special exception.
+-
++
+ This special exception was added by the Free Software Foundation in
+ version 2.2 of Bison. */
+
+ #ifndef YY_YY_DTC_PARSER_TAB_H_INCLUDED
+ # define YY_YY_DTC_PARSER_TAB_H_INCLUDED
+-/* Enabling traces. */
++/* Debug traces. */
+ #ifndef YYDEBUG
+ # define YYDEBUG 0
+ #endif
+@@ -40,48 +40,45 @@
+ extern int yydebug;
+ #endif
+
+-/* Tokens. */
++/* Token type. */
+ #ifndef YYTOKENTYPE
+ # define YYTOKENTYPE
+- /* Put the tokens into the symbol table, so that GDB and other debuggers
+- know about them. */
+- enum yytokentype {
+- DT_V1 = 258,
+- DT_MEMRESERVE = 259,
+- DT_LSHIFT = 260,
+- DT_RSHIFT = 261,
+- DT_LE = 262,
+- DT_GE = 263,
+- DT_EQ = 264,
+- DT_NE = 265,
+- DT_AND = 266,
+- DT_OR = 267,
+- DT_BITS = 268,
+- DT_DEL_PROP = 269,
+- DT_DEL_NODE = 270,
+- DT_PROPNODENAME = 271,
+- DT_LITERAL = 272,
+- DT_CHAR_LITERAL = 273,
+- DT_BASE = 274,
+- DT_BYTE = 275,
+- DT_STRING = 276,
+- DT_LABEL = 277,
+- DT_REF = 278,
+- DT_INCBIN = 279
+- };
++ enum yytokentype
++ {
++ DT_V1 = 258,
++ DT_PLUGIN = 259,
++ DT_MEMRESERVE = 260,
++ DT_LSHIFT = 261,
++ DT_RSHIFT = 262,
++ DT_LE = 263,
++ DT_GE = 264,
++ DT_EQ = 265,
++ DT_NE = 266,
++ DT_AND = 267,
++ DT_OR = 268,
++ DT_BITS = 269,
++ DT_DEL_PROP = 270,
++ DT_DEL_NODE = 271,
++ DT_PROPNODENAME = 272,
++ DT_LITERAL = 273,
++ DT_CHAR_LITERAL = 274,
++ DT_BYTE = 275,
++ DT_STRING = 276,
++ DT_LABEL = 277,
++ DT_REF = 278,
++ DT_INCBIN = 279
++ };
+ #endif
+
+-
++/* Value type. */
+ #if ! defined YYSTYPE && ! defined YYSTYPE_IS_DECLARED
+-typedef union YYSTYPE
++typedef union YYSTYPE YYSTYPE;
++union YYSTYPE
+ {
+-/* Line 2053 of yacc.c */
+-#line 40 "dtc-parser.y"
++#line 39 "dtc-parser.y" /* yacc.c:1909 */
+
+ char *propnodename;
+- char *literal;
+ char *labelref;
+- unsigned int cbase;
+ uint8_t byte;
+ struct data data;
+
+@@ -96,30 +93,31 @@
+ struct node *nodelist;
+ struct reserve_info *re;
+ uint64_t integer;
++ int is_plugin;
+
+-
+-/* Line 2053 of yacc.c */
+-#line 103 "dtc-parser.tab.h"
+-} YYSTYPE;
++#line 99 "dtc-parser.tab.h" /* yacc.c:1909 */
++};
+ # define YYSTYPE_IS_TRIVIAL 1
+-# define yystype YYSTYPE /* obsolescent; will be withdrawn */
+ # define YYSTYPE_IS_DECLARED 1
+ #endif
+
+-extern YYSTYPE yylval;
+-
+-#ifdef YYPARSE_PARAM
+-#if defined __STDC__ || defined __cplusplus
+-int yyparse (void *YYPARSE_PARAM);
+-#else
+-int yyparse ();
++/* Location type. */
++#if ! defined YYLTYPE && ! defined YYLTYPE_IS_DECLARED
++typedef struct YYLTYPE YYLTYPE;
++struct YYLTYPE
++{
++ int first_line;
++ int first_column;
++ int last_line;
++ int last_column;
++};
++# define YYLTYPE_IS_DECLARED 1
++# define YYLTYPE_IS_TRIVIAL 1
+ #endif
+-#else /* ! YYPARSE_PARAM */
+-#if defined __STDC__ || defined __cplusplus
++
++
++extern YYSTYPE yylval;
++extern YYLTYPE yylloc;
+ int yyparse (void);
+-#else
+-int yyparse ();
+-#endif
+-#endif /* ! YYPARSE_PARAM */
+
+ #endif /* !YY_YY_DTC_PARSER_TAB_H_INCLUDED */
+diff -Nur linux-4.1.3/scripts/dtc/dtc-parser.y linux-xbian-rpi/scripts/dtc/dtc-parser.y
+--- linux-4.1.3/scripts/dtc/dtc-parser.y 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/scripts/dtc/dtc-parser.y 2015-07-28 01:20:58.461099590 +0200
+@@ -17,31 +17,28 @@
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
+ * USA
+ */
+-
+ %{
+ #include <stdio.h>
++#include <inttypes.h>
+
+ #include "dtc.h"
+ #include "srcpos.h"
+
+-YYLTYPE yylloc;
+-
+ extern int yylex(void);
+-extern void print_error(char const *fmt, ...);
+ extern void yyerror(char const *s);
++#define ERROR(loc, ...) \
++ do { \
++ srcpos_error((loc), "Error", __VA_ARGS__); \
++ treesource_error = true; \
++ } while (0)
+
+ extern struct boot_info *the_boot_info;
+-extern int treesource_error;
+-
+-static unsigned long long eval_literal(const char *s, int base, int bits);
+-static unsigned char eval_char_literal(const char *s);
++extern bool treesource_error;
+ %}
+
+ %union {
+ char *propnodename;
+- char *literal;
+ char *labelref;
+- unsigned int cbase;
+ uint8_t byte;
+ struct data data;
+
+@@ -56,18 +53,19 @@
+ struct node *nodelist;
+ struct reserve_info *re;
+ uint64_t integer;
++ int is_plugin;
+ }
+
+ %token DT_V1
++%token DT_PLUGIN
+ %token DT_MEMRESERVE
+ %token DT_LSHIFT DT_RSHIFT DT_LE DT_GE DT_EQ DT_NE DT_AND DT_OR
+ %token DT_BITS
+ %token DT_DEL_PROP
+ %token DT_DEL_NODE
+ %token <propnodename> DT_PROPNODENAME
+-%token <literal> DT_LITERAL
+-%token <literal> DT_CHAR_LITERAL
+-%token <cbase> DT_BASE
++%token <integer> DT_LITERAL
++%token <integer> DT_CHAR_LITERAL
+ %token <byte> DT_BYTE
+ %token <data> DT_STRING
+ %token <labelref> DT_LABEL
+@@ -76,6 +74,7 @@
+
+ %type <data> propdata
+ %type <data> propdataprefix
++%type <is_plugin> plugindecl
+ %type <re> memreserve
+ %type <re> memreserves
+ %type <array> arrayprefix
+@@ -106,10 +105,23 @@
+ %%
+
+ sourcefile:
+- DT_V1 ';' memreserves devicetree
++ DT_V1 ';' plugindecl memreserves devicetree
++ {
++ $5->is_plugin = $3;
++ $5->is_root = 1;
++ the_boot_info = build_boot_info($4, $5,
++ guess_boot_cpuid($5));
++ }
++ ;
++
++plugindecl:
++ /* empty */
++ {
++ $$ = 0;
++ }
++ | DT_PLUGIN ';'
+ {
+- the_boot_info = build_boot_info($3, $4,
+- guess_boot_cpuid($4));
++ $$ = 1;
+ }
+ ;
+
+@@ -152,17 +164,18 @@
+ if (target)
+ merge_nodes(target, $3);
+ else
+- print_error("label or path, '%s', not found", $2);
++ ERROR(&@2, "Label or path %s not found", $2);
+ $$ = $1;
+ }
+ | devicetree DT_DEL_NODE DT_REF ';'
+ {
+ struct node *target = get_node_by_ref($1, $3);
+
+- if (!target)
+- print_error("label or path, '%s', not found", $3);
+- else
++ if (target)
+ delete_node(target);
++ else
++ ERROR(&@3, "Label or path %s not found", $3);
++
+
+ $$ = $1;
+ }
+@@ -230,10 +243,9 @@
+
+ if ($6 != 0)
+ if (fseek(f, $6, SEEK_SET) != 0)
+- print_error("Couldn't seek to offset %llu in \"%s\": %s",
+- (unsigned long long)$6,
+- $4.val,
+- strerror(errno));
++ die("Couldn't seek to offset %llu in \"%s\": %s",
++ (unsigned long long)$6, $4.val,
++ strerror(errno));
+
+ d = data_copy_file(f, $8);
+
+@@ -274,18 +286,19 @@
+ arrayprefix:
+ DT_BITS DT_LITERAL '<'
+ {
+- $$.data = empty_data;
+- $$.bits = eval_literal($2, 0, 7);
++ unsigned long long bits;
+
+- if (($$.bits != 8) &&
+- ($$.bits != 16) &&
+- ($$.bits != 32) &&
+- ($$.bits != 64))
+- {
+- print_error("Only 8, 16, 32 and 64-bit elements"
+- " are currently supported");
+- $$.bits = 32;
++ bits = $2;
++
++ if ((bits != 8) && (bits != 16) &&
++ (bits != 32) && (bits != 64)) {
++ ERROR(&@2, "Array elements must be"
++ " 8, 16, 32 or 64-bits");
++ bits = 32;
+ }
++
++ $$.data = empty_data;
++ $$.bits = bits;
+ }
+ | '<'
+ {
+@@ -305,9 +318,8 @@
+ * mask), all bits are one.
+ */
+ if (($2 > mask) && (($2 | mask) != -1ULL))
+- print_error(
+- "integer value out of range "
+- "%016lx (%d bits)", $1.bits);
++ ERROR(&@2, "Value out of range for"
++ " %d-bit array element", $1.bits);
+ }
+
+ $$.data = data_append_integer($1.data, $2, $1.bits);
+@@ -321,7 +333,7 @@
+ REF_PHANDLE,
+ $2);
+ else
+- print_error("References are only allowed in "
++ ERROR(&@2, "References are only allowed in "
+ "arrays with 32-bit elements.");
+
+ $$.data = data_append_integer($1.data, val, $1.bits);
+@@ -334,13 +346,7 @@
+
+ integer_prim:
+ DT_LITERAL
+- {
+- $$ = eval_literal($1, 0, 64);
+- }
+ | DT_CHAR_LITERAL
+- {
+- $$ = eval_char_literal($1);
+- }
+ | '(' integer_expr ')'
+ {
+ $$ = $2;
+@@ -447,7 +453,7 @@
+ }
+ | subnode propdef
+ {
+- print_error("syntax error: properties must precede subnodes");
++ ERROR(&@2, "Properties must precede subnodes");
+ YYERROR;
+ }
+ ;
+@@ -470,63 +476,7 @@
+
+ %%
+
+-void print_error(char const *fmt, ...)
++void yyerror(char const *s)
+ {
+- va_list va;
+-
+- va_start(va, fmt);
+- srcpos_verror(&yylloc, fmt, va);
+- va_end(va);
+-
+- treesource_error = 1;
+-}
+-
+-void yyerror(char const *s) {
+- print_error("%s", s);
+-}
+-
+-static unsigned long long eval_literal(const char *s, int base, int bits)
+-{
+- unsigned long long val;
+- char *e;
+-
+- errno = 0;
+- val = strtoull(s, &e, base);
+- if (*e) {
+- size_t uls = strspn(e, "UL");
+- if (e[uls])
+- print_error("bad characters in literal");
+- }
+- if ((errno == ERANGE)
+- || ((bits < 64) && (val >= (1ULL << bits))))
+- print_error("literal out of range");
+- else if (errno != 0)
+- print_error("bad literal");
+- return val;
+-}
+-
+-static unsigned char eval_char_literal(const char *s)
+-{
+- int i = 1;
+- char c = s[0];
+-
+- if (c == '\0')
+- {
+- print_error("empty character literal");
+- return 0;
+- }
+-
+- /*
+- * If the first character in the character literal is a \ then process
+- * the remaining characters as an escape encoding. If the first
+- * character is neither an escape or a terminator it should be the only
+- * character in the literal and will be returned.
+- */
+- if (c == '\\')
+- c = get_escape_char(s, &i);
+-
+- if (s[i] != '\0')
+- print_error("malformed character literal");
+-
+- return c;
++ ERROR(&yylloc, "%s", s);
+ }
+diff -Nur linux-4.1.3/scripts/dtc/flattree.c linux-xbian-rpi/scripts/dtc/flattree.c
+--- linux-4.1.3/scripts/dtc/flattree.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/scripts/dtc/flattree.c 2015-07-28 01:20:58.461099590 +0200
+@@ -261,7 +261,13 @@
+ {
+ struct property *prop;
+ struct node *child;
+- int seen_name_prop = 0;
++ bool seen_name_prop = false;
++ struct symbol *sym;
++ struct fixup *f;
++ struct fixup_entry *fe;
++ char *name, *s;
++ const char *fullpath;
++ int namesz, nameoff, vallen;
+
+ if (tree->deleted)
+ return;
+@@ -276,10 +282,8 @@
+ emit->align(etarget, sizeof(cell_t));
+
+ for_each_property(tree, prop) {
+- int nameoff;
+-
+ if (streq(prop->name, "name"))
+- seen_name_prop = 1;
++ seen_name_prop = true;
+
+ nameoff = stringtable_insert(strbuf, prop->name);
+
+@@ -310,6 +314,139 @@
+ flatten_tree(child, emit, etarget, strbuf, vi);
+ }
+
++ if (!symbol_fixup_support)
++ goto no_symbols;
++
++ /* add the symbol nodes (if any) */
++ if (tree->symbols) {
++
++ emit->beginnode(etarget, NULL);
++ emit->string(etarget, "__symbols__", 0);
++ emit->align(etarget, sizeof(cell_t));
++
++ for_each_symbol(tree, sym) {
++
++ vallen = strlen(sym->node->fullpath);
++
++ nameoff = stringtable_insert(strbuf, sym->label->label);
++
++ emit->property(etarget, NULL);
++ emit->cell(etarget, vallen + 1);
++ emit->cell(etarget, nameoff);
++
++ if ((vi->flags & FTF_VARALIGN) && vallen >= 8)
++ emit->align(etarget, 8);
++
++ emit->string(etarget, sym->node->fullpath,
++ strlen(sym->node->fullpath));
++ emit->align(etarget, sizeof(cell_t));
++ }
++
++ emit->endnode(etarget, NULL);
++ }
++
++ /* add the fixup nodes */
++ if (tree->fixups) {
++
++ /* emit the external fixups */
++ emit->beginnode(etarget, NULL);
++ emit->string(etarget, "__fixups__", 0);
++ emit->align(etarget, sizeof(cell_t));
++
++ for_each_fixup(tree, f) {
++
++ namesz = 0;
++ for_each_fixup_entry(f, fe) {
++ fullpath = fe->node->fullpath;
++ if (fullpath[0] == '\0')
++ fullpath = "/";
++ namesz += strlen(fullpath) + 1;
++ namesz += strlen(fe->prop->name) + 1;
++ namesz += 32; /* space for :<number> + '\0' */
++ }
++
++ name = xmalloc(namesz);
++
++ s = name;
++ for_each_fixup_entry(f, fe) {
++ fullpath = fe->node->fullpath;
++ if (fullpath[0] == '\0')
++ fullpath = "/";
++ snprintf(s, name + namesz - s, "%s:%s:%d",
++ fullpath,
++ fe->prop->name, fe->offset);
++ s += strlen(s) + 1;
++ }
++
++ nameoff = stringtable_insert(strbuf, f->ref);
++ vallen = s - name - 1;
++
++ emit->property(etarget, NULL);
++ emit->cell(etarget, vallen + 1);
++ emit->cell(etarget, nameoff);
++
++ if ((vi->flags & FTF_VARALIGN) && vallen >= 8)
++ emit->align(etarget, 8);
++
++ emit->string(etarget, name, vallen);
++ emit->align(etarget, sizeof(cell_t));
++
++ free(name);
++ }
++
++ emit->endnode(etarget, tree->labels);
++ }
++
++ /* add the local fixup property */
++ if (tree->local_fixups) {
++
++ /* emit the external fixups */
++ emit->beginnode(etarget, NULL);
++ emit->string(etarget, "__local_fixups__", 0);
++ emit->align(etarget, sizeof(cell_t));
++
++ namesz = 0;
++ for_each_local_fixup_entry(tree, fe) {
++ fullpath = fe->node->fullpath;
++ if (fullpath[0] == '\0')
++ fullpath = "/";
++ namesz += strlen(fullpath) + 1;
++ namesz += strlen(fe->prop->name) + 1;
++ namesz += 32; /* space for :<number> + '\0' */
++ }
++
++ name = xmalloc(namesz);
++
++ s = name;
++ for_each_local_fixup_entry(tree, fe) {
++ fullpath = fe->node->fullpath;
++ if (fullpath[0] == '\0')
++ fullpath = "/";
++ snprintf(s, name + namesz - s, "%s:%s:%d",
++ fullpath, fe->prop->name,
++ fe->offset);
++ s += strlen(s) + 1;
++ }
++
++ nameoff = stringtable_insert(strbuf, "fixup");
++ vallen = s - name - 1;
++
++ emit->property(etarget, NULL);
++ emit->cell(etarget, vallen + 1);
++ emit->cell(etarget, nameoff);
++
++ if ((vi->flags & FTF_VARALIGN) && vallen >= 8)
++ emit->align(etarget, 8);
++
++ emit->string(etarget, name, vallen);
++ emit->align(etarget, sizeof(cell_t));
++
++ free(name);
++
++ emit->endnode(etarget, tree->labels);
++ }
++
++no_symbols:
+ emit->endnode(etarget, tree->labels);
+ }
+
+diff -Nur linux-4.1.3/scripts/dtc/fstree.c linux-xbian-rpi/scripts/dtc/fstree.c
+--- linux-4.1.3/scripts/dtc/fstree.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/scripts/dtc/fstree.c 2015-07-28 01:20:58.461099590 +0200
+@@ -37,26 +37,26 @@
+ tree = build_node(NULL, NULL);
+
+ while ((de = readdir(d)) != NULL) {
+- char *tmpnam;
++ char *tmpname;
+
+ if (streq(de->d_name, ".")
+ || streq(de->d_name, ".."))
+ continue;
+
+- tmpnam = join_path(dirname, de->d_name);
++ tmpname = join_path(dirname, de->d_name);
+
+- if (lstat(tmpnam, &st) < 0)
+- die("stat(%s): %s\n", tmpnam, strerror(errno));
++ if (lstat(tmpname, &st) < 0)
++ die("stat(%s): %s\n", tmpname, strerror(errno));
+
+ if (S_ISREG(st.st_mode)) {
+ struct property *prop;
+ FILE *pfile;
+
+- pfile = fopen(tmpnam, "r");
++ pfile = fopen(tmpname, "rb");
+ if (! pfile) {
+ fprintf(stderr,
+ "WARNING: Cannot open %s: %s\n",
+- tmpnam, strerror(errno));
++ tmpname, strerror(errno));
+ } else {
+ prop = build_property(xstrdup(de->d_name),
+ data_copy_file(pfile,
+@@ -67,12 +67,12 @@
+ } else if (S_ISDIR(st.st_mode)) {
+ struct node *newchild;
+
+- newchild = read_fstree(tmpnam);
++ newchild = read_fstree(tmpname);
+ newchild = name_node(newchild, xstrdup(de->d_name));
+ add_child(tree, newchild);
+ }
+
+- free(tmpnam);
++ free(tmpname);
+ }
+
+ closedir(d);
+diff -Nur linux-4.1.3/scripts/dtc/livetree.c linux-xbian-rpi/scripts/dtc/livetree.c
+--- linux-4.1.3/scripts/dtc/livetree.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/scripts/dtc/livetree.c 2015-07-28 01:20:58.461099590 +0200
+@@ -511,7 +511,9 @@
+
+ struct node *get_node_by_ref(struct node *tree, const char *ref)
+ {
+- if (ref[0] == '/')
++ if (streq(ref, "/"))
++ return tree;
++ else if (ref[0] == '/')
+ return get_node_by_path(tree, ref);
+ else
+ return get_node_by_label(tree, ref);
+diff -Nur linux-4.1.3/scripts/dtc/srcpos.c linux-xbian-rpi/scripts/dtc/srcpos.c
+--- linux-4.1.3/scripts/dtc/srcpos.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/scripts/dtc/srcpos.c 2015-07-28 01:20:58.461099590 +0200
+@@ -34,7 +34,7 @@
+ static struct search_path *search_path_head, **search_path_tail;
+
+
+-static char *dirname(const char *path)
++static char *get_dirname(const char *path)
+ {
+ const char *slash = strrchr(path, '/');
+
+@@ -77,7 +77,7 @@
+ else
+ fullname = join_path(dirname, fname);
+
+- *fp = fopen(fullname, "r");
++ *fp = fopen(fullname, "rb");
+ if (!*fp) {
+ free(fullname);
+ fullname = NULL;
+@@ -150,7 +150,7 @@
+ srcfile = xmalloc(sizeof(*srcfile));
+
+ srcfile->f = srcfile_relative_open(fname, &srcfile->name);
+- srcfile->dir = dirname(srcfile->name);
++ srcfile->dir = get_dirname(srcfile->name);
+ srcfile->prev = current_srcfile;
+
+ srcfile->lineno = 1;
+@@ -159,7 +159,7 @@
+ current_srcfile = srcfile;
+ }
+
+-int srcfile_pop(void)
++bool srcfile_pop(void)
+ {
+ struct srcfile_state *srcfile = current_srcfile;
+
+@@ -177,7 +177,7 @@
+ * fix this we could either allocate all the files from a
+ * table, or use a pool allocator. */
+
+- return current_srcfile ? 1 : 0;
++ return current_srcfile ? true : false;
+ }
+
+ void srcfile_add_search_path(const char *dirname)
+@@ -290,42 +290,27 @@
+ return pos_str;
+ }
+
+-void
+-srcpos_verror(struct srcpos *pos, char const *fmt, va_list va)
++void srcpos_verror(struct srcpos *pos, const char *prefix,
++ const char *fmt, va_list va)
+ {
+- const char *srcstr;
+-
+- srcstr = srcpos_string(pos);
++ char *srcstr;
+
+- fprintf(stderr, "Error: %s ", srcstr);
+- vfprintf(stderr, fmt, va);
+- fprintf(stderr, "\n");
+-}
++ srcstr = srcpos_string(pos);
+
+-void
+-srcpos_error(struct srcpos *pos, char const *fmt, ...)
+-{
+- va_list va;
++ fprintf(stderr, "%s: %s ", prefix, srcstr);
++ vfprintf(stderr, fmt, va);
++ fprintf(stderr, "\n");
+
+- va_start(va, fmt);
+- srcpos_verror(pos, fmt, va);
+- va_end(va);
++ free(srcstr);
+ }
+
+-
+-void
+-srcpos_warn(struct srcpos *pos, char const *fmt, ...)
++void srcpos_error(struct srcpos *pos, const char *prefix,
++ const char *fmt, ...)
+ {
+- const char *srcstr;
+ va_list va;
+- va_start(va, fmt);
+-
+- srcstr = srcpos_string(pos);
+-
+- fprintf(stderr, "Warning: %s ", srcstr);
+- vfprintf(stderr, fmt, va);
+- fprintf(stderr, "\n");
+
++ va_start(va, fmt);
++ srcpos_verror(pos, prefix, fmt, va);
+ va_end(va);
+ }
+
+diff -Nur linux-4.1.3/scripts/dtc/srcpos.h linux-xbian-rpi/scripts/dtc/srcpos.h
+--- linux-4.1.3/scripts/dtc/srcpos.h 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/scripts/dtc/srcpos.h 2015-07-28 01:20:58.465085369 +0200
+@@ -21,6 +21,7 @@
+ #define _SRCPOS_H_
+
+ #include <stdio.h>
++#include <stdbool.h>
+
+ struct srcfile_state {
+ FILE *f;
+@@ -55,7 +56,7 @@
+ FILE *srcfile_relative_open(const char *fname, char **fullnamep);
+
+ void srcfile_push(const char *fname);
+-int srcfile_pop(void);
++bool srcfile_pop(void);
+
+ /**
+ * Add a new directory to the search path for input files
+@@ -106,12 +107,12 @@
+ extern char *srcpos_string(struct srcpos *pos);
+ extern void srcpos_dump(struct srcpos *pos);
+
+-extern void srcpos_verror(struct srcpos *pos, char const *, va_list va)
+- __attribute__((format(printf, 2, 0)));
+-extern void srcpos_error(struct srcpos *pos, char const *, ...)
+- __attribute__((format(printf, 2, 3)));
+-extern void srcpos_warn(struct srcpos *pos, char const *, ...)
+- __attribute__((format(printf, 2, 3)));
++extern void srcpos_verror(struct srcpos *pos, const char *prefix,
++ const char *fmt, va_list va)
++ __attribute__((format(printf, 3, 0)));
++extern void srcpos_error(struct srcpos *pos, const char *prefix,
++ const char *fmt, ...)
++ __attribute__((format(printf, 3, 4)));
+
+ extern void srcpos_set_line(char *f, int l);
+
+diff -Nur linux-4.1.3/scripts/dtc/treesource.c linux-xbian-rpi/scripts/dtc/treesource.c
+--- linux-4.1.3/scripts/dtc/treesource.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/scripts/dtc/treesource.c 2015-07-28 01:20:58.465085369 +0200
+@@ -26,12 +26,12 @@
+ extern YYLTYPE yylloc;
+
+ struct boot_info *the_boot_info;
+-int treesource_error;
++bool treesource_error;
+
+ struct boot_info *dt_from_source(const char *fname)
+ {
+ the_boot_info = NULL;
+- treesource_error = 0;
++ treesource_error = false;
+
+ srcfile_push(fname);
+ yyin = current_srcfile->f;
+@@ -54,9 +54,9 @@
+ fputc('\t', f);
+ }
+
+-static int isstring(char c)
++static bool isstring(char c)
+ {
+- return (isprint(c)
++ return (isprint((unsigned char)c)
+ || (c == '\0')
+ || strchr("\a\b\t\n\v\f\r", c));
+ }
+@@ -109,7 +109,7 @@
+ break;
+ case '\0':
+ fprintf(f, "\", ");
+- while (m && (m->offset < i)) {
++ while (m && (m->offset <= (i + 1))) {
+ if (m->type == LABEL) {
+ assert(m->offset == (i+1));
+ fprintf(f, "%s: ", m->ref);
+@@ -119,7 +119,7 @@
+ fprintf(f, "\"");
+ break;
+ default:
+- if (isprint(c))
++ if (isprint((unsigned char)c))
+ fprintf(f, "%c", c);
+ else
+ fprintf(f, "\\x%02hhx", c);
+@@ -178,7 +178,7 @@
+ m = m->next;
+ }
+
+- fprintf(f, "%02hhx", *bp++);
++ fprintf(f, "%02hhx", (unsigned char)(*bp++));
+ if ((const void *)bp >= propend)
+ break;
+ fprintf(f, " ");
+diff -Nur linux-4.1.3/scripts/dtc/util.c linux-xbian-rpi/scripts/dtc/util.c
+--- linux-4.1.3/scripts/dtc/util.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/scripts/dtc/util.c 2015-07-28 01:20:58.465085369 +0200
+@@ -39,11 +39,11 @@
+ char *xstrdup(const char *s)
+ {
+ int len = strlen(s) + 1;
+- char *dup = xmalloc(len);
++ char *d = xmalloc(len);
+
+- memcpy(dup, s, len);
++ memcpy(d, s, len);
+
+- return dup;
++ return d;
+ }
+
+ char *join_path(const char *path, const char *name)
+@@ -70,7 +70,7 @@
+ return str;
+ }
+
+-int util_is_printable_string(const void *data, int len)
++bool util_is_printable_string(const void *data, int len)
+ {
+ const char *s = data;
+ const char *ss, *se;
+@@ -87,7 +87,7 @@
+
+ while (s < se) {
+ ss = s;
+- while (s < se && *s && isprint(*s))
++ while (s < se && *s && isprint((unsigned char)*s))
+ s++;
+
+ /* not zero, or not done yet */
+@@ -219,10 +219,6 @@
+ if (offset == bufsize) {
+ bufsize *= 2;
+ buf = xrealloc(buf, bufsize);
+- if (!buf) {
+- ret = ENOMEM;
+- break;
+- }
+ }
+
+ ret = read(fd, &buf[offset], bufsize - offset);
+@@ -375,9 +371,9 @@
+ const uint32_t *cell = (const uint32_t *)data;
+
+ printf(" = <");
+- for (i = 0; i < len; i += 4)
++ for (i = 0, len /= 4; i < len; i++)
+ printf("0x%08x%s", fdt32_to_cpu(cell[i]),
+- i < (len - 4) ? " " : "");
++ i < (len - 1) ? " " : "");
+ printf(">");
+ } else {
+ printf(" = [");
+diff -Nur linux-4.1.3/scripts/dtc/util.h linux-xbian-rpi/scripts/dtc/util.h
+--- linux-4.1.3/scripts/dtc/util.h 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/scripts/dtc/util.h 2015-07-28 01:20:58.465085369 +0200
+@@ -2,6 +2,7 @@
+ #define _UTIL_H
+
+ #include <stdarg.h>
++#include <stdbool.h>
+ #include <getopt.h>
+
+ /*
+@@ -33,6 +34,7 @@
+ va_start(ap, str);
+ fprintf(stderr, "FATAL ERROR: ");
+ vfprintf(stderr, str, ap);
++ va_end(ap);
+ exit(1);
+ }
+
+@@ -68,7 +70,7 @@
+ * @param len The string length including terminator
+ * @return 1 if a valid printable string, 0 if not
+ */
+-int util_is_printable_string(const void *data, int len);
++bool util_is_printable_string(const void *data, int len);
+
+ /*
+ * Parse an escaped character starting at index i in string s. The resulting
+diff -Nur linux-4.1.3/scripts/dtc/version_gen.h linux-xbian-rpi/scripts/dtc/version_gen.h
+--- linux-4.1.3/scripts/dtc/version_gen.h 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/scripts/dtc/version_gen.h 2015-07-28 01:20:58.465085369 +0200
+@@ -1 +1 @@
+-#define DTC_VERSION "DTC 1.4.0-dirty"
++#define DTC_VERSION "DTC 1.4.1-g36c70742"
+diff -Nur linux-4.1.3/scripts/knlinfo linux-xbian-rpi/scripts/knlinfo
+--- linux-4.1.3/scripts/knlinfo 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/scripts/knlinfo 2015-07-28 01:20:58.465085369 +0200
+@@ -0,0 +1,168 @@
++#!/usr/bin/env perl
++# ----------------------------------------------------------------------
++# knlinfo by Phil Elwell for Raspberry Pi
++#
++# (c) 2014,2015 Raspberry Pi (Trading) Limited <info@raspberrypi.org>
++#
++# Licensed under the terms of the GNU General Public License.
++# ----------------------------------------------------------------------
++
++use strict;
++use integer;
++
++use Fcntl ":seek";
++
++my $trailer_magic = 'RPTL';
++
++my %atom_formats =
++(
++ 'DTOK' => \&format_bool,
++ 'KVer' => \&format_string,
++ '283x' => \&format_bool,
++);
++
++if (@ARGV != 1)
++{
++ print ("Usage: knlinfo <kernel image>\n");
++ exit(1);
++}
++
++my $kernel_file = $ARGV[0];
++
++
++my ($atoms, $pos) = read_trailer($kernel_file);
++
++exit(1) if (!$atoms);
++
++printf("Kernel trailer found at %d/0x%x:\n", $pos, $pos);
++
++foreach my $atom (@$atoms)
++{
++ printf(" %s: %s\n", $atom->[0], format_atom($atom));
++}
++
++exit(0);
++
++sub read_trailer
++{
++ my ($kernel_file) = @_;
++ my $fh;
++
++ if (!open($fh, '<', $kernel_file))
++ {
++ print ("* Failed to open '$kernel_file'\n");
++ return undef;
++ }
++
++ if (!seek($fh, -12, SEEK_END))
++ {
++ print ("* seek error in '$kernel_file'\n");
++ return undef;
++ }
++
++ my $last_bytes;
++ sysread($fh, $last_bytes, 12);
++
++ my ($trailer_len, $data_len, $magic) = unpack('VVa4', $last_bytes);
++
++ if (($magic ne $trailer_magic) || ($data_len != 4))
++ {
++ print ("* no trailer\n");
++ return undef;
++ }
++ if (!seek($fh, -12, SEEK_END))
++ {
++ print ("* seek error in '$kernel_file'\n");
++ return undef;
++ }
++
++ $trailer_len -= 12;
++
++ while ($trailer_len > 0)
++ {
++ if ($trailer_len < 8)
++ {
++ print ("* truncated atom header in trailer\n");
++ return undef;
++ }
++ if (!seek($fh, -8, SEEK_CUR))
++ {
++ print ("* seek error in '$kernel_file'\n");
++ return undef;
++ }
++ $trailer_len -= 8;
++
++ my $atom_hdr;
++ sysread($fh, $atom_hdr, 8);
++ my ($atom_len, $atom_type) = unpack('Va4', $atom_hdr);
++
++ if ($trailer_len < $atom_len)
++ {
++ print ("* truncated atom data in trailer\n");
++ return undef;
++ }
++
++ my $rounded_len = (($atom_len + 3) & ~3);
++ if (!seek($fh, -(8 + $rounded_len), SEEK_CUR))
++ {
++ print ("* seek error in '$kernel_file'\n");
++ return undef;
++ }
++ $trailer_len -= $rounded_len;
++
++ my $atom_data;
++ sysread($fh, $atom_data, $atom_len);
++
++ if (!seek($fh, -$atom_len, SEEK_CUR))
++ {
++ print ("* seek error in '$kernel_file'\n");
++ return undef;
++ }
++
++ push @$atoms, [ $atom_type, $atom_data ];
++ }
++
++ if (($$atoms[-1][0] eq "\x00\x00\x00\x00") &&
++ ($$atoms[-1][1] eq ""))
++ {
++ pop @$atoms;
++ }
++ else
++ {
++ print ("* end marker missing from trailer\n");
++ }
++
++ return ($atoms, tell($fh));
++}
++
++sub format_atom
++{
++ my ($atom) = @_;
++
++ my $format_func = $atom_formats{$atom->[0]} || \&format_hex;
++ return $format_func->($atom->[1]);
++}
++
++sub format_bool
++{
++ my ($data) = @_;
++ return unpack('V', $data) ? 'true' : 'false';
++}
++
++sub format_int
++{
++ my ($data) = @_;
++ return unpack('V', $data);
++}
++
++sub format_string
++{
++ my ($data) = @_;
++ return '"'.$data.'"';
++}
++
++sub format_hex
++{
++ my ($data) = @_;
++ return unpack('H*', $data);
++}
+diff -Nur linux-4.1.3/scripts/mkknlimg linux-xbian-rpi/scripts/mkknlimg
+--- linux-4.1.3/scripts/mkknlimg 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/scripts/mkknlimg 2015-07-28 01:20:58.465085369 +0200
+@@ -0,0 +1,275 @@
++#!/usr/bin/env perl
++# ----------------------------------------------------------------------
++# mkknlimg by Phil Elwell for Raspberry Pi
++# based on extract-ikconfig by Dick Streefland
++#
++# (c) 2009,2010 Dick Streefland <dick@streefland.net>
++# (c) 2014,2015 Raspberry Pi (Trading) Limited <info@raspberrypi.org>
++#
++# Licensed under the terms of the GNU General Public License.
++# ----------------------------------------------------------------------
++
++use strict;
++use warnings;
++use integer;
++
++my $trailer_magic = 'RPTL';
++
++my $tmpfile1 = "/tmp/mkknlimg_$$.1";
++my $tmpfile2 = "/tmp/mkknlimg_$$.2";
++
++my $dtok = 0;
++my $is_283x = 0;
++
++while (@ARGV && ($ARGV[0] =~ /^-/))
++{
++ my $arg = shift(@ARGV);
++ if ($arg eq '--dtok')
++ {
++ $dtok = 1;
++ }
++ elsif ($arg eq '--283x')
++ {
++ $is_283x = 1;
++ }
++ else
++ {
++ print ("* Unknown option '$arg'\n");
++ usage();
++ }
++}
++
++usage() if (@ARGV != 2);
++
++my $kernel_file = $ARGV[0];
++my $out_file = $ARGV[1];
++
++if (! -r $kernel_file)
++{
++ print ("* File '$kernel_file' not found\n");
++ usage();
++}
++
++my @wanted_config_lines =
++(
++ 'CONFIG_BCM2708_DT',
++ 'CONFIG_ARCH_BCM2835'
++);
++
++my @wanted_strings =
++(
++ 'bcm2708_fb',
++ 'brcm,bcm2835-mmc',
++ 'brcm,bcm2835-sdhost',
++ 'brcm,bcm2708-pinctrl',
++ 'brcm,bcm2835-gpio',
++ 'brcm,bcm2835-pm-wdt'
++);
++
++my $res = try_extract($kernel_file, $tmpfile1);
++$res = try_decompress('\037\213\010', 'xy', 'gunzip', 0,
++ $kernel_file, $tmpfile1, $tmpfile2) if (!$res);
++$res = try_decompress('\3757zXZ\000', 'abcde', 'unxz --single-stream', -1,
++ $kernel_file, $tmpfile1, $tmpfile2) if (!$res);
++$res = try_decompress('BZh', 'xy', 'bunzip2', 0,
++ $kernel_file, $tmpfile1, $tmpfile2) if (!$res);
++$res = try_decompress('\135\0\0\0', 'xxx', 'unlzma', 0,
++ $kernel_file, $tmpfile1, $tmpfile2) if (!$res);
++$res = try_decompress('\211\114\132', 'xy', 'lzop -d', 0,
++ $kernel_file, $tmpfile1, $tmpfile2) if (!$res);
++$res = try_decompress('\002\041\114\030', 'xy', 'lz4 -d', 1,
++ $kernel_file, $tmpfile1, $tmpfile2) if (!$res);
++
++my $append_trailer;
++my $trailer;
++my $kver = '?';
++
++$append_trailer = $dtok;
++
++if ($res)
++{
++ $kver = $res->{''} || '?';
++ print("Version: $kver\n");
++
++ $append_trailer = $dtok;
++ if (!$dtok)
++ {
++ if (config_bool($res, 'bcm2708_fb') ||
++ config_bool($res, 'brcm,bcm2835-mmc') ||
++ config_bool($res, 'brcm,bcm2835-sdhost'))
++ {
++ $dtok ||= config_bool($res, 'CONFIG_BCM2708_DT');
++ $dtok ||= config_bool($res, 'CONFIG_ARCH_BCM2835');
++ $dtok ||= config_bool($res, 'brcm,bcm2708-pinctrl');
++ $dtok ||= config_bool($res, 'brcm,bcm2835-gpio');
++ $is_283x ||= config_bool($res, 'CONFIG_ARCH_BCM2835');
++ $is_283x ||= config_bool($res, 'brcm,bcm2835-pm-wdt');
++ $append_trailer = 1;
++ }
++ else
++ {
++ print ("* This doesn't look like a Raspberry Pi kernel. In pass-through mode.\n");
++ }
++ }
++}
++elsif (!$dtok)
++{
++ print ("* Is this a valid kernel? In pass-through mode.\n");
++}
++
++if ($append_trailer)
++{
++ printf("DT: %s\n", $dtok ? "y" : "n");
++ printf("283x: %s\n", $is_283x ? "y" : "n");
++
++ my @atoms;
++
++ push @atoms, [ $trailer_magic, pack('V', 0) ];
++ push @atoms, [ 'KVer', $kver ];
++ push @atoms, [ 'DTOK', pack('V', $dtok) ];
++ push @atoms, [ '283x', pack('V', $is_283x) ];
++
++ $trailer = pack_trailer(\@atoms);
++ $atoms[0]->[1] = pack('V', length($trailer));
++
++ $trailer = pack_trailer(\@atoms);
++}
++
++my $ofh;
++my $total_len = 0;
++
++if ($out_file eq $kernel_file)
++{
++ die "* Failed to open '$out_file' for append\n"
++ if (!open($ofh, '>>', $out_file));
++ $total_len = tell($ofh);
++}
++else
++{
++ die "* Failed to open '$kernel_file'\n"
++ if (!open(my $ifh, '<', $kernel_file));
++ die "* Failed to create '$out_file'\n"
++ if (!open($ofh, '>', $out_file));
++
++ my $copybuf;
++ while (1)
++ {
++ my $bytes = sysread($ifh, $copybuf, 64*1024);
++ last if (!$bytes);
++ syswrite($ofh, $copybuf, $bytes);
++ $total_len += $bytes;
++ }
++ close($ifh);
++}
++
++if ($trailer)
++{
++ # Pad to word-alignment
++ syswrite($ofh, "\x000\x000\x000", (-$total_len & 0x3));
++ syswrite($ofh, $trailer);
++}
++
++close($ofh);
++
++exit($trailer ? 0 : 1);
++
++END {
++ unlink($tmpfile1) if ($tmpfile1);
++ unlink($tmpfile2) if ($tmpfile2);
++}
++
++
++sub usage
++{
++ print ("Usage: mkknlimg [--dtok] [--283x] <vmlinux|zImage|bzImage> <outfile>\n");
++ exit(1);
++}
++
++sub try_extract
++{
++ my ($knl, $tmp) = @_;
++
++ my $ver = `strings "$knl" | grep -a -E "^Linux version [1-9]"`;
++
++ return undef if (!$ver);
++
++ chomp($ver);
++
++ my $res = { ''=>$ver };
++ my $string_pattern = '^('.join('|', @wanted_strings).')$';
++
++ my @matches = `strings \"$knl\" | grep -E \"$string_pattern\"`;
++ foreach my $match (@matches)
++ {
++ chomp($match);
++ $res->{$match} = 1;
++ }
++
++ my $config_pattern = '^('.join('|', @wanted_config_lines).')=(.*)$';
++ my $cf1 = 'IKCFG_ST\037\213\010';
++ my $cf2 = '0123456789';
++
++ my $pos = `tr "$cf1\n$cf2" "\n$cf2=" < "$knl" | grep -abo "^$cf2"`;
++ if ($pos)
++ {
++ $pos =~ s/:.*[\r\n]*$//s;
++ $pos += 8;
++ my $err = (system("tail -c+$pos \"$knl\" | zcat > $tmp 2> /dev/null") >> 8);
++ if (($err == 0) || ($err == 2))
++ {
++ if (open(my $fh, '<', $tmp))
++ {
++ while (my $line = <$fh>)
++ {
++ chomp($line);
++ $res->{$1} = $2 if ($line =~ /$config_pattern/);
++ }
++
++ close($fh);
++ }
++ }
++ }
++
++ return $res;
++}
++
++
++sub try_decompress
++{
++ my ($magic, $subst, $zcat, $idx, $knl, $tmp1, $tmp2) = @_;
++
++ my $pos = `tr "$magic\n$subst" "\n$subst=" < "$knl" | grep -abo "^$subst"`;
++ if ($pos)
++ {
++ chomp($pos);
++ $pos = (split(/[\r\n]+/, $pos))[$idx];
++ return undef if (!defined($pos));
++ $pos =~ s/:.*[\r\n]*$//s;
++ my $cmd = "tail -c+$pos \"$knl\" | $zcat > $tmp2 2> /dev/null";
++ my $err = (system($cmd) >> 8);
++ return undef if (($err != 0) && ($err != 2));
++
++ return try_extract($tmp2, $tmp1);
++ }
++
++ return undef;
++}
++
++sub pack_trailer
++{
++ my ($atoms) = @_;
++ my $trailer = pack('VV', 0, 0);
++ for (my $i = $#$atoms; $i>=0; $i--)
++ {
++ my $atom = $atoms->[$i];
++ $trailer .= pack('a*x!4Va4', $atom->[1], length($atom->[1]), $atom->[0]);
++ }
++ return $trailer;
++}
++
++sub config_bool
++{
++ my ($configs, $wanted) = @_;
++ my $val = $configs->{$wanted} || 'n';
++ return (($val eq 'y') || ($val eq '1'));
++}
+diff -Nur linux-4.1.3/sound/arm/bcm2835.c linux-xbian-rpi/sound/arm/bcm2835.c
+--- linux-4.1.3/sound/arm/bcm2835.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/sound/arm/bcm2835.c 2015-07-28 01:20:58.465085369 +0200
+@@ -0,0 +1,511 @@
++/*****************************************************************************
++* Copyright 2011 Broadcom Corporation. All rights reserved.
++*
++* Unless you and Broadcom execute a separate written software license
++* agreement governing use of this software, this software is licensed to you
++* under the terms of the GNU General Public License version 2, available at
++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
++*
++* Notwithstanding the above, under no circumstances may you combine this
++* software in any way with any other Broadcom software provided under a
++* license other than the GPL, without Broadcom's express prior written
++* consent.
++*****************************************************************************/
++
++#include <linux/platform_device.h>
++
++#include <linux/init.h>
++#include <linux/slab.h>
++#include <linux/module.h>
++#include <linux/of.h>
++
++#include "bcm2835.h"
++
++/* module parameters (see "Module Parameters") */
++/* SNDRV_CARDS: maximum number of cards supported by this module */
++static int index[MAX_SUBSTREAMS] = {[0 ... (MAX_SUBSTREAMS - 1)] = -1 };
++static char *id[MAX_SUBSTREAMS] = {[0 ... (MAX_SUBSTREAMS - 1)] = NULL };
++static int enable[MAX_SUBSTREAMS] = {[0 ... (MAX_SUBSTREAMS - 1)] = 1 };
++
++/* HACKY global pointers needed for successive probes to work : ssp
++ * But compared against the changes we will have to do in VC audio_ipc code
++ * to export 8 audio_ipc devices as a single IPC device and then monitor all
++ * four devices in a thread, this gets things done quickly and should be easier
++ * to debug if we run into issues
++ */
++
++static struct snd_card *g_card = NULL;
++static bcm2835_chip_t *g_chip = NULL;
++
++static int snd_bcm2835_free(bcm2835_chip_t * chip)
++{
++ kfree(chip);
++ return 0;
++}
++
++/* component-destructor
++ * (see "Management of Cards and Components")
++ */
++static int snd_bcm2835_dev_free(struct snd_device *device)
++{
++ return snd_bcm2835_free(device->device_data);
++}
++
++/* chip-specific constructor
++ * (see "Management of Cards and Components")
++ */
++static int snd_bcm2835_create(struct snd_card *card,
++ struct platform_device *pdev,
++ bcm2835_chip_t ** rchip)
++{
++ bcm2835_chip_t *chip;
++ int err;
++ static struct snd_device_ops ops = {
++ .dev_free = snd_bcm2835_dev_free,
++ };
++
++ *rchip = NULL;
++
++ chip = kzalloc(sizeof(*chip), GFP_KERNEL);
++ if (chip == NULL)
++ return -ENOMEM;
++
++ chip->card = card;
++
++ err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
++ if (err < 0) {
++ snd_bcm2835_free(chip);
++ return err;
++ }
++
++ *rchip = chip;
++ return 0;
++}
++
++static int snd_bcm2835_alsa_probe_dt(struct platform_device *pdev)
++{
++ struct device *dev = &pdev->dev;
++ bcm2835_chip_t *chip;
++ struct snd_card *card;
++ u32 numchans;
++ int err, i;
++
++ err = of_property_read_u32(dev->of_node, "brcm,pwm-channels",
++ &numchans);
++ if (err) {
++ dev_err(dev, "Failed to get DT property 'brcm,pwm-channels'");
++ return err;
++ }
++
++ if (numchans == 0 || numchans > MAX_SUBSTREAMS) {
++ numchans = MAX_SUBSTREAMS;
++ dev_warn(dev, "Illegal 'brcm,pwm-channels' value, will use %u\n",
++ numchans);
++ }
++
++ err = snd_card_new(NULL, -1, NULL, THIS_MODULE, 0, &card);
++ if (err) {
++ dev_err(dev, "Failed to create soundcard structure\n");
++ return err;
++ }
++
++ snd_card_set_dev(card, dev);
++ strcpy(card->driver, "bcm2835");
++ strcpy(card->shortname, "bcm2835 ALSA");
++ sprintf(card->longname, "%s", card->shortname);
++
++ err = snd_bcm2835_create(card, pdev, &chip);
++ if (err < 0) {
++ dev_err(dev, "Failed to create bcm2835 chip\n");
++ goto err_free;
++ }
++
++ err = snd_bcm2835_new_pcm(chip);
++ if (err < 0) {
++ dev_err(dev, "Failed to create new bcm2835 pcm device\n");
++ goto err_free;
++ }
++
++ err = snd_bcm2835_new_spdif_pcm(chip);
++ if (err < 0) {
++ dev_err(dev, "Failed to create new bcm2835 spdif pcm device\n");
++ goto err_free;
++ }
++
++ err = snd_bcm2835_new_ctl(chip);
++ if (err < 0) {
++ dev_err(dev, "Failed to create new bcm2835 ctl\n");
++ goto err_free;
++ }
++
++ for (i = 0; i < numchans; i++) {
++ chip->avail_substreams |= (1 << i);
++ chip->pdev[i] = pdev;
++ }
++
++ err = snd_card_register(card);
++ if (err) {
++ dev_err(dev, "Failed to register bcm2835 ALSA card \n");
++ goto err_free;
++ }
++
++ g_card = card;
++ g_chip = chip;
++ platform_set_drvdata(pdev, card);
++ audio_info("bcm2835 ALSA card created with %u channels\n", numchans);
++
++ return 0;
++
++err_free:
++ snd_card_free(card);
++
++ return err;
++}
++
++static int snd_bcm2835_alsa_probe(struct platform_device *pdev)
++{
++ static int dev;
++ bcm2835_chip_t *chip;
++ struct snd_card *card;
++ int err;
++
++ if (pdev->dev.of_node)
++ return snd_bcm2835_alsa_probe_dt(pdev);
++
++ if (dev >= MAX_SUBSTREAMS)
++ return -ENODEV;
++
++ if (!enable[dev]) {
++ dev++;
++ return -ENOENT;
++ }
++
++ if (dev > 0)
++ goto add_register_map;
++
++ err = snd_card_new(NULL, index[dev], id[dev], THIS_MODULE, 0, &g_card);
++ if (err < 0)
++ goto out;
++
++ snd_card_set_dev(g_card, &pdev->dev);
++ strcpy(g_card->driver, "bcm2835");
++ strcpy(g_card->shortname, "bcm2835 ALSA");
++ sprintf(g_card->longname, "%s", g_card->shortname);
++
++ err = snd_bcm2835_create(g_card, pdev, &chip);
++ if (err < 0) {
++ dev_err(&pdev->dev, "Failed to create bcm2835 chip\n");
++ goto out_bcm2835_create;
++ }
++
++ g_chip = chip;
++ err = snd_bcm2835_new_pcm(chip);
++ if (err < 0) {
++ dev_err(&pdev->dev, "Failed to create new BCM2835 pcm device\n");
++ goto out_bcm2835_new_pcm;
++ }
++
++ err = snd_bcm2835_new_spdif_pcm(chip);
++ if (err < 0) {
++ dev_err(&pdev->dev, "Failed to create new BCM2835 spdif pcm device\n");
++ goto out_bcm2835_new_spdif;
++ }
++
++ err = snd_bcm2835_new_ctl(chip);
++ if (err < 0) {
++ dev_err(&pdev->dev, "Failed to create new BCM2835 ctl\n");
++ goto out_bcm2835_new_ctl;
++ }
++
++add_register_map:
++ card = g_card;
++ chip = g_chip;
++
++ BUG_ON(!(card && chip));
++
++ chip->avail_substreams |= (1 << dev);
++ chip->pdev[dev] = pdev;
++
++ if (dev == 0) {
++ err = snd_card_register(card);
++ if (err < 0) {
++ dev_err(&pdev->dev,
++ "Failed to register bcm2835 ALSA card \n");
++ goto out_card_register;
++ }
++ platform_set_drvdata(pdev, card);
++ audio_info("bcm2835 ALSA card created!\n");
++ } else {
++ audio_info("bcm2835 ALSA chip created!\n");
++ platform_set_drvdata(pdev, (void *)dev);
++ }
++
++ dev++;
++
++ return 0;
++
++out_card_register:
++out_bcm2835_new_ctl:
++out_bcm2835_new_spdif:
++out_bcm2835_new_pcm:
++out_bcm2835_create:
++ BUG_ON(!g_card);
++ if (snd_card_free(g_card))
++ dev_err(&pdev->dev, "Failed to free Registered alsa card\n");
++ g_card = NULL;
++out:
++ dev = SNDRV_CARDS; /* stop more avail_substreams from being probed */
++ dev_err(&pdev->dev, "BCM2835 ALSA Probe failed !!\n");
++ return err;
++}
++
++static int snd_bcm2835_alsa_remove(struct platform_device *pdev)
++{
++ uint32_t idx;
++ void *drv_data;
++
++ drv_data = platform_get_drvdata(pdev);
++
++ if (drv_data == (void *)g_card) {
++ /* This is the card device */
++ snd_card_free((struct snd_card *)drv_data);
++ g_card = NULL;
++ g_chip = NULL;
++ } else {
++ idx = (uint32_t) drv_data;
++ if (g_card != NULL) {
++ BUG_ON(!g_chip);
++ /* We pass chip device numbers in audio ipc devices
++ * other than the one we registered our card with
++ */
++ idx = (uint32_t) drv_data;
++ BUG_ON(!idx || idx > MAX_SUBSTREAMS);
++ g_chip->avail_substreams &= ~(1 << idx);
++ /* There should be atleast one substream registered
++ * after we are done here, as it wil be removed when
++ * the *remove* is called for the card device
++ */
++ BUG_ON(!g_chip->avail_substreams);
++ }
++ }
++
++ platform_set_drvdata(pdev, NULL);
++
++ return 0;
++}
++
++#ifdef CONFIG_PM
++static int snd_bcm2835_alsa_suspend(struct platform_device *pdev,
++ pm_message_t state)
++{
++ return 0;
++}
++
++static int snd_bcm2835_alsa_resume(struct platform_device *pdev)
++{
++ return 0;
++}
++
++#endif
++
++static const struct of_device_id snd_bcm2835_of_match_table[] = {
++ { .compatible = "brcm,bcm2835-audio", },
++ {},
++};
++MODULE_DEVICE_TABLE(of, snd_bcm2835_of_match_table);
++
++static struct platform_driver bcm2835_alsa0_driver = {
++ .probe = snd_bcm2835_alsa_probe,
++ .remove = snd_bcm2835_alsa_remove,
++#ifdef CONFIG_PM
++ .suspend = snd_bcm2835_alsa_suspend,
++ .resume = snd_bcm2835_alsa_resume,
++#endif
++ .driver = {
++ .name = "bcm2835_AUD0",
++ .owner = THIS_MODULE,
++ .of_match_table = snd_bcm2835_of_match_table,
++ },
++};
++
++static struct platform_driver bcm2835_alsa1_driver = {
++ .probe = snd_bcm2835_alsa_probe,
++ .remove = snd_bcm2835_alsa_remove,
++#ifdef CONFIG_PM
++ .suspend = snd_bcm2835_alsa_suspend,
++ .resume = snd_bcm2835_alsa_resume,
++#endif
++ .driver = {
++ .name = "bcm2835_AUD1",
++ .owner = THIS_MODULE,
++ },
++};
++
++static struct platform_driver bcm2835_alsa2_driver = {
++ .probe = snd_bcm2835_alsa_probe,
++ .remove = snd_bcm2835_alsa_remove,
++#ifdef CONFIG_PM
++ .suspend = snd_bcm2835_alsa_suspend,
++ .resume = snd_bcm2835_alsa_resume,
++#endif
++ .driver = {
++ .name = "bcm2835_AUD2",
++ .owner = THIS_MODULE,
++ },
++};
++
++static struct platform_driver bcm2835_alsa3_driver = {
++ .probe = snd_bcm2835_alsa_probe,
++ .remove = snd_bcm2835_alsa_remove,
++#ifdef CONFIG_PM
++ .suspend = snd_bcm2835_alsa_suspend,
++ .resume = snd_bcm2835_alsa_resume,
++#endif
++ .driver = {
++ .name = "bcm2835_AUD3",
++ .owner = THIS_MODULE,
++ },
++};
++
++static struct platform_driver bcm2835_alsa4_driver = {
++ .probe = snd_bcm2835_alsa_probe,
++ .remove = snd_bcm2835_alsa_remove,
++#ifdef CONFIG_PM
++ .suspend = snd_bcm2835_alsa_suspend,
++ .resume = snd_bcm2835_alsa_resume,
++#endif
++ .driver = {
++ .name = "bcm2835_AUD4",
++ .owner = THIS_MODULE,
++ },
++};
++
++static struct platform_driver bcm2835_alsa5_driver = {
++ .probe = snd_bcm2835_alsa_probe,
++ .remove = snd_bcm2835_alsa_remove,
++#ifdef CONFIG_PM
++ .suspend = snd_bcm2835_alsa_suspend,
++ .resume = snd_bcm2835_alsa_resume,
++#endif
++ .driver = {
++ .name = "bcm2835_AUD5",
++ .owner = THIS_MODULE,
++ },
++};
++
++static struct platform_driver bcm2835_alsa6_driver = {
++ .probe = snd_bcm2835_alsa_probe,
++ .remove = snd_bcm2835_alsa_remove,
++#ifdef CONFIG_PM
++ .suspend = snd_bcm2835_alsa_suspend,
++ .resume = snd_bcm2835_alsa_resume,
++#endif
++ .driver = {
++ .name = "bcm2835_AUD6",
++ .owner = THIS_MODULE,
++ },
++};
++
++static struct platform_driver bcm2835_alsa7_driver = {
++ .probe = snd_bcm2835_alsa_probe,
++ .remove = snd_bcm2835_alsa_remove,
++#ifdef CONFIG_PM
++ .suspend = snd_bcm2835_alsa_suspend,
++ .resume = snd_bcm2835_alsa_resume,
++#endif
++ .driver = {
++ .name = "bcm2835_AUD7",
++ .owner = THIS_MODULE,
++ },
++};
++
++static int bcm2835_alsa_device_init(void)
++{
++ int err;
++ err = platform_driver_register(&bcm2835_alsa0_driver);
++ if (err) {
++ pr_err("Error registering bcm2835_alsa0_driver %d .\n", err);
++ goto out;
++ }
++
++ err = platform_driver_register(&bcm2835_alsa1_driver);
++ if (err) {
++ pr_err("Error registering bcm2835_alsa0_driver %d .\n", err);
++ goto unregister_0;
++ }
++
++ err = platform_driver_register(&bcm2835_alsa2_driver);
++ if (err) {
++ pr_err("Error registering bcm2835_alsa0_driver %d .\n", err);
++ goto unregister_1;
++ }
++
++ err = platform_driver_register(&bcm2835_alsa3_driver);
++ if (err) {
++ pr_err("Error registering bcm2835_alsa0_driver %d .\n", err);
++ goto unregister_2;
++ }
++
++ err = platform_driver_register(&bcm2835_alsa4_driver);
++ if (err) {
++ pr_err("Error registering bcm2835_alsa0_driver %d .\n", err);
++ goto unregister_3;
++ }
++
++ err = platform_driver_register(&bcm2835_alsa5_driver);
++ if (err) {
++ pr_err("Error registering bcm2835_alsa0_driver %d .\n", err);
++ goto unregister_4;
++ }
++
++ err = platform_driver_register(&bcm2835_alsa6_driver);
++ if (err) {
++ pr_err("Error registering bcm2835_alsa0_driver %d .\n", err);
++ goto unregister_5;
++ }
++
++ err = platform_driver_register(&bcm2835_alsa7_driver);
++ if (err) {
++ pr_err("Error registering bcm2835_alsa0_driver %d .\n", err);
++ goto unregister_6;
++ }
++
++ return 0;
++
++unregister_6:
++ platform_driver_unregister(&bcm2835_alsa6_driver);
++unregister_5:
++ platform_driver_unregister(&bcm2835_alsa5_driver);
++unregister_4:
++ platform_driver_unregister(&bcm2835_alsa4_driver);
++unregister_3:
++ platform_driver_unregister(&bcm2835_alsa3_driver);
++unregister_2:
++ platform_driver_unregister(&bcm2835_alsa2_driver);
++unregister_1:
++ platform_driver_unregister(&bcm2835_alsa1_driver);
++unregister_0:
++ platform_driver_unregister(&bcm2835_alsa0_driver);
++out:
++ return err;
++}
++
++static void bcm2835_alsa_device_exit(void)
++{
++ platform_driver_unregister(&bcm2835_alsa0_driver);
++ platform_driver_unregister(&bcm2835_alsa1_driver);
++ platform_driver_unregister(&bcm2835_alsa2_driver);
++ platform_driver_unregister(&bcm2835_alsa3_driver);
++ platform_driver_unregister(&bcm2835_alsa4_driver);
++ platform_driver_unregister(&bcm2835_alsa5_driver);
++ platform_driver_unregister(&bcm2835_alsa6_driver);
++ platform_driver_unregister(&bcm2835_alsa7_driver);
++}
++
++late_initcall(bcm2835_alsa_device_init);
++module_exit(bcm2835_alsa_device_exit);
++
++MODULE_AUTHOR("Dom Cobley");
++MODULE_DESCRIPTION("Alsa driver for BCM2835 chip");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:bcm2835_alsa");
+diff -Nur linux-4.1.3/sound/arm/bcm2835-ctl.c linux-xbian-rpi/sound/arm/bcm2835-ctl.c
+--- linux-4.1.3/sound/arm/bcm2835-ctl.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/sound/arm/bcm2835-ctl.c 2015-07-28 01:20:58.465085369 +0200
+@@ -0,0 +1,323 @@
++/*****************************************************************************
++* Copyright 2011 Broadcom Corporation. All rights reserved.
++*
++* Unless you and Broadcom execute a separate written software license
++* agreement governing use of this software, this software is licensed to you
++* under the terms of the GNU General Public License version 2, available at
++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
++*
++* Notwithstanding the above, under no circumstances may you combine this
++* software in any way with any other Broadcom software provided under a
++* license other than the GPL, without Broadcom's express prior written
++* consent.
++*****************************************************************************/
++
++#include <linux/platform_device.h>
++#include <linux/init.h>
++#include <linux/io.h>
++#include <linux/jiffies.h>
++#include <linux/slab.h>
++#include <linux/time.h>
++#include <linux/wait.h>
++#include <linux/delay.h>
++#include <linux/moduleparam.h>
++#include <linux/sched.h>
++
++#include <sound/core.h>
++#include <sound/control.h>
++#include <sound/pcm.h>
++#include <sound/pcm_params.h>
++#include <sound/rawmidi.h>
++#include <sound/initval.h>
++#include <sound/tlv.h>
++#include <sound/asoundef.h>
++
++#include "bcm2835.h"
++
++/* volume maximum and minimum in terms of 0.01dB */
++#define CTRL_VOL_MAX 400
++#define CTRL_VOL_MIN -10239 /* originally -10240 */
++
++
++static int snd_bcm2835_ctl_info(struct snd_kcontrol *kcontrol,
++ struct snd_ctl_elem_info *uinfo)
++{
++ audio_info(" ... IN\n");
++ if (kcontrol->private_value == PCM_PLAYBACK_VOLUME) {
++ uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
++ uinfo->count = 1;
++ uinfo->value.integer.min = CTRL_VOL_MIN;
++ uinfo->value.integer.max = CTRL_VOL_MAX; /* 2303 */
++ } else if (kcontrol->private_value == PCM_PLAYBACK_MUTE) {
++ uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
++ uinfo->count = 1;
++ uinfo->value.integer.min = 0;
++ uinfo->value.integer.max = 1;
++ } else if (kcontrol->private_value == PCM_PLAYBACK_DEVICE) {
++ uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
++ uinfo->count = 1;
++ uinfo->value.integer.min = 0;
++ uinfo->value.integer.max = AUDIO_DEST_MAX-1;
++ }
++ audio_info(" ... OUT\n");
++ return 0;
++}
++
++/* toggles mute on or off depending on the value of nmute, and returns
++ * 1 if the mute value was changed, otherwise 0
++ */
++static int toggle_mute(struct bcm2835_chip *chip, int nmute)
++{
++ /* if settings are ok, just return 0 */
++ if(chip->mute == nmute)
++ return 0;
++
++ /* if the sound is muted then we need to unmute */
++ if(chip->mute == CTRL_VOL_MUTE)
++ {
++ chip->volume = chip->old_volume; /* copy the old volume back */
++ audio_info("Unmuting, old_volume = %d, volume = %d ...\n", chip->old_volume, chip->volume);
++ }
++ else /* otherwise we mute */
++ {
++ chip->old_volume = chip->volume;
++ chip->volume = 26214; /* set volume to minimum level AKA mute */
++ audio_info("Muting, old_volume = %d, volume = %d ...\n", chip->old_volume, chip->volume);
++ }
++
++ chip->mute = nmute;
++ return 1;
++}
++
++static int snd_bcm2835_ctl_get(struct snd_kcontrol *kcontrol,
++ struct snd_ctl_elem_value *ucontrol)
++{
++ struct bcm2835_chip *chip = snd_kcontrol_chip(kcontrol);
++
++ BUG_ON(!chip && !(chip->avail_substreams & AVAIL_SUBSTREAMS_MASK));
++
++ if (kcontrol->private_value == PCM_PLAYBACK_VOLUME)
++ ucontrol->value.integer.value[0] = chip2alsa(chip->volume);
++ else if (kcontrol->private_value == PCM_PLAYBACK_MUTE)
++ ucontrol->value.integer.value[0] = chip->mute;
++ else if (kcontrol->private_value == PCM_PLAYBACK_DEVICE)
++ ucontrol->value.integer.value[0] = chip->dest;
++
++ return 0;
++}
++
++static int snd_bcm2835_ctl_put(struct snd_kcontrol *kcontrol,
++ struct snd_ctl_elem_value *ucontrol)
++{
++ struct bcm2835_chip *chip = snd_kcontrol_chip(kcontrol);
++ int changed = 0;
++
++ if (kcontrol->private_value == PCM_PLAYBACK_VOLUME) {
++ audio_info("Volume change attempted.. volume = %d new_volume = %d\n", chip->volume, (int)ucontrol->value.integer.value[0]);
++ if (chip->mute == CTRL_VOL_MUTE) {
++ /* changed = toggle_mute(chip, CTRL_VOL_UNMUTE); */
++ return 1; /* should return 0 to signify no change but the mixer takes this as the opposite sign (no idea why) */
++ }
++ if (changed
++ || (ucontrol->value.integer.value[0] != chip2alsa(chip->volume))) {
++
++ chip->volume = alsa2chip(ucontrol->value.integer.value[0]);
++ changed = 1;
++ }
++
++ } else if (kcontrol->private_value == PCM_PLAYBACK_MUTE) {
++ /* Now implemented */
++ audio_info(" Mute attempted\n");
++ changed = toggle_mute(chip, ucontrol->value.integer.value[0]);
++
++ } else if (kcontrol->private_value == PCM_PLAYBACK_DEVICE) {
++ if (ucontrol->value.integer.value[0] != chip->dest) {
++ chip->dest = ucontrol->value.integer.value[0];
++ changed = 1;
++ }
++ }
++
++ if (changed) {
++ if (bcm2835_audio_set_ctls(chip))
++ printk(KERN_ERR "Failed to set ALSA controls..\n");
++ }
++
++ return changed;
++}
++
++static DECLARE_TLV_DB_SCALE(snd_bcm2835_db_scale, CTRL_VOL_MIN, 1, 1);
++
++static struct snd_kcontrol_new snd_bcm2835_ctl[] = {
++ {
++ .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
++ .name = "PCM Playback Volume",
++ .index = 0,
++ .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ,
++ .private_value = PCM_PLAYBACK_VOLUME,
++ .info = snd_bcm2835_ctl_info,
++ .get = snd_bcm2835_ctl_get,
++ .put = snd_bcm2835_ctl_put,
++ .count = 1,
++ .tlv = {.p = snd_bcm2835_db_scale}
++ },
++ {
++ .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
++ .name = "PCM Playback Switch",
++ .index = 0,
++ .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
++ .private_value = PCM_PLAYBACK_MUTE,
++ .info = snd_bcm2835_ctl_info,
++ .get = snd_bcm2835_ctl_get,
++ .put = snd_bcm2835_ctl_put,
++ .count = 1,
++ },
++ {
++ .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
++ .name = "PCM Playback Route",
++ .index = 0,
++ .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
++ .private_value = PCM_PLAYBACK_DEVICE,
++ .info = snd_bcm2835_ctl_info,
++ .get = snd_bcm2835_ctl_get,
++ .put = snd_bcm2835_ctl_put,
++ .count = 1,
++ },
++};
++
++static int snd_bcm2835_spdif_default_info(struct snd_kcontrol *kcontrol,
++ struct snd_ctl_elem_info *uinfo)
++{
++ uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
++ uinfo->count = 1;
++ return 0;
++}
++
++static int snd_bcm2835_spdif_default_get(struct snd_kcontrol *kcontrol,
++ struct snd_ctl_elem_value *ucontrol)
++{
++ struct bcm2835_chip *chip = snd_kcontrol_chip(kcontrol);
++ int i;
++
++ for (i = 0; i < 4; i++)
++ ucontrol->value.iec958.status[i] =
++ (chip->spdif_status >> (i * 8)) && 0xff;
++
++ return 0;
++}
++
++static int snd_bcm2835_spdif_default_put(struct snd_kcontrol *kcontrol,
++ struct snd_ctl_elem_value *ucontrol)
++{
++ struct bcm2835_chip *chip = snd_kcontrol_chip(kcontrol);
++ unsigned int val = 0;
++ int i, change;
++
++ for (i = 0; i < 4; i++)
++ val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
++
++ change = val != chip->spdif_status;
++ chip->spdif_status = val;
++
++ return change;
++}
++
++static int snd_bcm2835_spdif_mask_info(struct snd_kcontrol *kcontrol,
++ struct snd_ctl_elem_info *uinfo)
++{
++ uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
++ uinfo->count = 1;
++ return 0;
++}
++
++static int snd_bcm2835_spdif_mask_get(struct snd_kcontrol *kcontrol,
++ struct snd_ctl_elem_value *ucontrol)
++{
++ /* bcm2835 supports only consumer mode and sets all other format flags
++ * automatically. So the only thing left is signalling non-audio
++ * content */
++ ucontrol->value.iec958.status[0] = IEC958_AES0_NONAUDIO;
++ return 0;
++}
++
++static int snd_bcm2835_spdif_stream_info(struct snd_kcontrol *kcontrol,
++ struct snd_ctl_elem_info *uinfo)
++{
++ uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
++ uinfo->count = 1;
++ return 0;
++}
++
++static int snd_bcm2835_spdif_stream_get(struct snd_kcontrol *kcontrol,
++ struct snd_ctl_elem_value *ucontrol)
++{
++ struct bcm2835_chip *chip = snd_kcontrol_chip(kcontrol);
++ int i;
++
++ for (i = 0; i < 4; i++)
++ ucontrol->value.iec958.status[i] =
++ (chip->spdif_status >> (i * 8)) & 0xff;
++ return 0;
++}
++
++static int snd_bcm2835_spdif_stream_put(struct snd_kcontrol *kcontrol,
++ struct snd_ctl_elem_value *ucontrol)
++{
++ struct bcm2835_chip *chip = snd_kcontrol_chip(kcontrol);
++ unsigned int val = 0;
++ int i, change;
++
++ for (i = 0; i < 4; i++)
++ val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
++ change = val != chip->spdif_status;
++ chip->spdif_status = val;
++
++ return change;
++}
++
++static struct snd_kcontrol_new snd_bcm2835_spdif[] = {
++ {
++ .iface = SNDRV_CTL_ELEM_IFACE_PCM,
++ .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
++ .info = snd_bcm2835_spdif_default_info,
++ .get = snd_bcm2835_spdif_default_get,
++ .put = snd_bcm2835_spdif_default_put
++ },
++ {
++ .access = SNDRV_CTL_ELEM_ACCESS_READ,
++ .iface = SNDRV_CTL_ELEM_IFACE_PCM,
++ .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, CON_MASK),
++ .info = snd_bcm2835_spdif_mask_info,
++ .get = snd_bcm2835_spdif_mask_get,
++ },
++ {
++ .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
++ SNDRV_CTL_ELEM_ACCESS_INACTIVE,
++ .iface = SNDRV_CTL_ELEM_IFACE_PCM,
++ .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PCM_STREAM),
++ .info = snd_bcm2835_spdif_stream_info,
++ .get = snd_bcm2835_spdif_stream_get,
++ .put = snd_bcm2835_spdif_stream_put,
++ },
++};
++
++int snd_bcm2835_new_ctl(bcm2835_chip_t * chip)
++{
++ int err;
++ unsigned int idx;
++
++ strcpy(chip->card->mixername, "Broadcom Mixer");
++ for (idx = 0; idx < ARRAY_SIZE(snd_bcm2835_ctl); idx++) {
++ err =
++ snd_ctl_add(chip->card,
++ snd_ctl_new1(&snd_bcm2835_ctl[idx], chip));
++ if (err < 0)
++ return err;
++ }
++ for (idx = 0; idx < ARRAY_SIZE(snd_bcm2835_spdif); idx++) {
++ err = snd_ctl_add(chip->card,
++ snd_ctl_new1(&snd_bcm2835_spdif[idx], chip));
++ if (err < 0)
++ return err;
++ }
++ return 0;
++}
+diff -Nur linux-4.1.3/sound/arm/bcm2835.h linux-xbian-rpi/sound/arm/bcm2835.h
+--- linux-4.1.3/sound/arm/bcm2835.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/sound/arm/bcm2835.h 2015-07-28 01:20:58.465085369 +0200
+@@ -0,0 +1,167 @@
++/*****************************************************************************
++* Copyright 2011 Broadcom Corporation. All rights reserved.
++*
++* Unless you and Broadcom execute a separate written software license
++* agreement governing use of this software, this software is licensed to you
++* under the terms of the GNU General Public License version 2, available at
++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
++*
++* Notwithstanding the above, under no circumstances may you combine this
++* software in any way with any other Broadcom software provided under a
++* license other than the GPL, without Broadcom's express prior written
++* consent.
++*****************************************************************************/
++
++#ifndef __SOUND_ARM_BCM2835_H
++#define __SOUND_ARM_BCM2835_H
++
++#include <linux/device.h>
++#include <linux/list.h>
++#include <linux/interrupt.h>
++#include <linux/wait.h>
++#include <sound/core.h>
++#include <sound/initval.h>
++#include <sound/pcm.h>
++#include <sound/pcm_params.h>
++#include <sound/pcm-indirect.h>
++#include <linux/workqueue.h>
++
++/*
++#define AUDIO_DEBUG_ENABLE
++#define AUDIO_VERBOSE_DEBUG_ENABLE
++*/
++
++/* Debug macros */
++
++#ifdef AUDIO_DEBUG_ENABLE
++#ifdef AUDIO_VERBOSE_DEBUG_ENABLE
++
++#define audio_debug(fmt, arg...) \
++ printk(KERN_INFO"%s:%d " fmt, __func__, __LINE__, ##arg)
++
++#define audio_info(fmt, arg...) \
++ printk(KERN_INFO"%s:%d " fmt, __func__, __LINE__, ##arg)
++
++#else
++
++#define audio_debug(fmt, arg...)
++
++#define audio_info(fmt, arg...)
++
++#endif /* AUDIO_VERBOSE_DEBUG_ENABLE */
++
++#else
++
++#define audio_debug(fmt, arg...)
++
++#define audio_info(fmt, arg...)
++
++#endif /* AUDIO_DEBUG_ENABLE */
++
++#define audio_error(fmt, arg...) \
++ printk(KERN_ERR"%s:%d " fmt, __func__, __LINE__, ##arg)
++
++#define audio_warning(fmt, arg...) \
++ printk(KERN_WARNING"%s:%d " fmt, __func__, __LINE__, ##arg)
++
++#define audio_alert(fmt, arg...) \
++ printk(KERN_ALERT"%s:%d " fmt, __func__, __LINE__, ##arg)
++
++#define MAX_SUBSTREAMS (8)
++#define AVAIL_SUBSTREAMS_MASK (0xff)
++enum {
++ CTRL_VOL_MUTE,
++ CTRL_VOL_UNMUTE
++};
++
++/* macros for alsa2chip and chip2alsa, instead of functions */
++
++#define alsa2chip(vol) (uint)(-((vol << 8) / 100)) /* convert alsa to chip volume (defined as macro rather than function call) */
++#define chip2alsa(vol) -((vol * 100) >> 8) /* convert chip to alsa volume */
++
++/* Some constants for values .. */
++typedef enum {
++ AUDIO_DEST_AUTO = 0,
++ AUDIO_DEST_HEADPHONES = 1,
++ AUDIO_DEST_HDMI = 2,
++ AUDIO_DEST_MAX,
++} SND_BCM2835_ROUTE_T;
++
++typedef enum {
++ PCM_PLAYBACK_VOLUME,
++ PCM_PLAYBACK_MUTE,
++ PCM_PLAYBACK_DEVICE,
++} SND_BCM2835_CTRL_T;
++
++/* definition of the chip-specific record */
++typedef struct bcm2835_chip {
++ struct snd_card *card;
++ struct snd_pcm *pcm;
++ struct snd_pcm *pcm_spdif;
++ /* Bitmat for valid reg_base and irq numbers */
++ uint32_t avail_substreams;
++ struct platform_device *pdev[MAX_SUBSTREAMS];
++ struct bcm2835_alsa_stream *alsa_stream[MAX_SUBSTREAMS];
++
++ int volume;
++ int old_volume; /* stores the volume value whist muted */
++ int dest;
++ int mute;
++
++ unsigned int opened;
++ unsigned int spdif_status;
++ struct mutex audio_mutex;
++} bcm2835_chip_t;
++
++typedef struct bcm2835_alsa_stream {
++ bcm2835_chip_t *chip;
++ struct snd_pcm_substream *substream;
++ struct snd_pcm_indirect pcm_indirect;
++
++ struct semaphore buffers_update_sem;
++ struct semaphore control_sem;
++ spinlock_t lock;
++ volatile uint32_t control;
++ volatile uint32_t status;
++
++ int open;
++ int running;
++ int draining;
++
++ int channels;
++ int params_rate;
++ int pcm_format_width;
++
++ unsigned int pos;
++ unsigned int buffer_size;
++ unsigned int period_size;
++
++ uint32_t enable_fifo_irq;
++ irq_handler_t fifo_irq_handler;
++
++ atomic_t retrieved;
++ struct opaque_AUDIO_INSTANCE_T *instance;
++ struct workqueue_struct *my_wq;
++ int idx;
++} bcm2835_alsa_stream_t;
++
++int snd_bcm2835_new_ctl(bcm2835_chip_t * chip);
++int snd_bcm2835_new_pcm(bcm2835_chip_t * chip);
++int snd_bcm2835_new_spdif_pcm(bcm2835_chip_t * chip);
++
++int bcm2835_audio_open(bcm2835_alsa_stream_t * alsa_stream);
++int bcm2835_audio_close(bcm2835_alsa_stream_t * alsa_stream);
++int bcm2835_audio_set_params(bcm2835_alsa_stream_t * alsa_stream,
++ uint32_t channels, uint32_t samplerate,
++ uint32_t bps);
++int bcm2835_audio_setup(bcm2835_alsa_stream_t * alsa_stream);
++int bcm2835_audio_start(bcm2835_alsa_stream_t * alsa_stream);
++int bcm2835_audio_stop(bcm2835_alsa_stream_t * alsa_stream);
++int bcm2835_audio_set_ctls(bcm2835_chip_t * chip);
++int bcm2835_audio_write(bcm2835_alsa_stream_t * alsa_stream, uint32_t count,
++ void *src);
++uint32_t bcm2835_audio_retrieve_buffers(bcm2835_alsa_stream_t * alsa_stream);
++void bcm2835_audio_flush_buffers(bcm2835_alsa_stream_t * alsa_stream);
++void bcm2835_audio_flush_playback_buffers(bcm2835_alsa_stream_t * alsa_stream);
++
++#endif /* __SOUND_ARM_BCM2835_H */
+diff -Nur linux-4.1.3/sound/arm/bcm2835-pcm.c linux-xbian-rpi/sound/arm/bcm2835-pcm.c
+--- linux-4.1.3/sound/arm/bcm2835-pcm.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/sound/arm/bcm2835-pcm.c 2015-07-28 01:20:58.465085369 +0200
+@@ -0,0 +1,557 @@
++/*****************************************************************************
++* Copyright 2011 Broadcom Corporation. All rights reserved.
++*
++* Unless you and Broadcom execute a separate written software license
++* agreement governing use of this software, this software is licensed to you
++* under the terms of the GNU General Public License version 2, available at
++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
++*
++* Notwithstanding the above, under no circumstances may you combine this
++* software in any way with any other Broadcom software provided under a
++* license other than the GPL, without Broadcom's express prior written
++* consent.
++*****************************************************************************/
++
++#include <linux/interrupt.h>
++#include <linux/slab.h>
++
++#include <sound/asoundef.h>
++
++#include "bcm2835.h"
++
++/* hardware definition */
++static struct snd_pcm_hardware snd_bcm2835_playback_hw = {
++ .info = (SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER |
++ SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID),
++ .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
++ .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
++ .rate_min = 8000,
++ .rate_max = 48000,
++ .channels_min = 1,
++ .channels_max = 2,
++ .buffer_bytes_max = 128 * 1024,
++ .period_bytes_min = 1 * 1024,
++ .period_bytes_max = 128 * 1024,
++ .periods_min = 1,
++ .periods_max = 128,
++};
++
++static struct snd_pcm_hardware snd_bcm2835_playback_spdif_hw = {
++ .info = (SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER |
++ SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID),
++ .formats = SNDRV_PCM_FMTBIT_S16_LE,
++ .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_44100 |
++ SNDRV_PCM_RATE_48000,
++ .rate_min = 44100,
++ .rate_max = 48000,
++ .channels_min = 2,
++ .channels_max = 2,
++ .buffer_bytes_max = 128 * 1024,
++ .period_bytes_min = 1 * 1024,
++ .period_bytes_max = 128 * 1024,
++ .periods_min = 1,
++ .periods_max = 128,
++};
++
++static void snd_bcm2835_playback_free(struct snd_pcm_runtime *runtime)
++{
++ audio_info("Freeing up alsa stream here ..\n");
++ if (runtime->private_data)
++ kfree(runtime->private_data);
++ runtime->private_data = NULL;
++}
++
++static irqreturn_t bcm2835_playback_fifo_irq(int irq, void *dev_id)
++{
++ bcm2835_alsa_stream_t *alsa_stream = (bcm2835_alsa_stream_t *) dev_id;
++ uint32_t consumed = 0;
++ int new_period = 0;
++
++ audio_info(" .. IN\n");
++
++ audio_info("alsa_stream=%p substream=%p\n", alsa_stream,
++ alsa_stream ? alsa_stream->substream : 0);
++
++ if (alsa_stream->open)
++ consumed = bcm2835_audio_retrieve_buffers(alsa_stream);
++
++ /* We get called only if playback was triggered, So, the number of buffers we retrieve in
++ * each iteration are the buffers that have been played out already
++ */
++
++ if (alsa_stream->period_size) {
++ if ((alsa_stream->pos / alsa_stream->period_size) !=
++ ((alsa_stream->pos + consumed) / alsa_stream->period_size))
++ new_period = 1;
++ }
++ audio_debug("updating pos cur: %d + %d max:%d period_bytes:%d, hw_ptr: %d new_period:%d\n",
++ alsa_stream->pos,
++ consumed,
++ alsa_stream->buffer_size,
++ (int)(alsa_stream->period_size*alsa_stream->substream->runtime->periods),
++ frames_to_bytes(alsa_stream->substream->runtime, alsa_stream->substream->runtime->status->hw_ptr),
++ new_period);
++ if (alsa_stream->buffer_size) {
++ alsa_stream->pos += consumed &~ (1<<30);
++ alsa_stream->pos %= alsa_stream->buffer_size;
++ }
++
++ if (alsa_stream->substream) {
++ if (new_period)
++ snd_pcm_period_elapsed(alsa_stream->substream);
++ } else {
++ audio_warning(" unexpected NULL substream\n");
++ }
++ audio_info(" .. OUT\n");
++
++ return IRQ_HANDLED;
++}
++
++/* open callback */
++static int snd_bcm2835_playback_open_generic(
++ struct snd_pcm_substream *substream, int spdif)
++{
++ bcm2835_chip_t *chip = snd_pcm_substream_chip(substream);
++ struct snd_pcm_runtime *runtime = substream->runtime;
++ bcm2835_alsa_stream_t *alsa_stream;
++ int idx;
++ int err;
++
++ audio_info(" .. IN (%d)\n", substream->number);
++
++ if(mutex_lock_interruptible(&chip->audio_mutex))
++ {
++ audio_error("Interrupted whilst waiting for lock\n");
++ return -EINTR;
++ }
++ audio_info("Alsa open (%d)\n", substream->number);
++ idx = substream->number;
++
++ if (spdif && chip->opened != 0) {
++ err = -EBUSY;
++ goto out;
++ }
++ else if (!spdif && (chip->opened & (1 << idx))) {
++ err = -EBUSY;
++ goto out;
++ }
++ if (idx > MAX_SUBSTREAMS) {
++ audio_error
++ ("substream(%d) device doesn't exist max(%d) substreams allowed\n",
++ idx, MAX_SUBSTREAMS);
++ err = -ENODEV;
++ goto out;
++ }
++
++ /* Check if we are ready */
++ if (!(chip->avail_substreams & (1 << idx))) {
++ /* We are not ready yet */
++ audio_error("substream(%d) device is not ready yet\n", idx);
++ err = -EAGAIN;
++ goto out;
++ }
++
++ alsa_stream = kzalloc(sizeof(bcm2835_alsa_stream_t), GFP_KERNEL);
++ if (alsa_stream == NULL) {
++ err = -ENOMEM;
++ goto out;
++ }
++
++ /* Initialise alsa_stream */
++ alsa_stream->chip = chip;
++ alsa_stream->substream = substream;
++ alsa_stream->idx = idx;
++
++ sema_init(&alsa_stream->buffers_update_sem, 0);
++ sema_init(&alsa_stream->control_sem, 0);
++ spin_lock_init(&alsa_stream->lock);
++
++ /* Enabled in start trigger, called on each "fifo irq" after that */
++ alsa_stream->enable_fifo_irq = 0;
++ alsa_stream->fifo_irq_handler = bcm2835_playback_fifo_irq;
++
++ err = bcm2835_audio_open(alsa_stream);
++ if (err != 0) {
++ kfree(alsa_stream);
++ goto out;
++ }
++ runtime->private_data = alsa_stream;
++ runtime->private_free = snd_bcm2835_playback_free;
++ if (spdif) {
++ runtime->hw = snd_bcm2835_playback_spdif_hw;
++ } else {
++ /* clear spdif status, as we are not in spdif mode */
++ chip->spdif_status = 0;
++ runtime->hw = snd_bcm2835_playback_hw;
++ }
++ /* minimum 16 bytes alignment (for vchiq bulk transfers) */
++ snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
++ 16);
++
++ chip->alsa_stream[idx] = alsa_stream;
++
++ chip->opened |= (1 << idx);
++ alsa_stream->open = 1;
++ alsa_stream->draining = 1;
++
++out:
++ mutex_unlock(&chip->audio_mutex);
++
++ audio_info(" .. OUT =%d\n", err);
++
++ return err;
++}
++
++static int snd_bcm2835_playback_open(struct snd_pcm_substream *substream)
++{
++ return snd_bcm2835_playback_open_generic(substream, 0);
++}
++
++static int snd_bcm2835_playback_spdif_open(struct snd_pcm_substream *substream)
++{
++ return snd_bcm2835_playback_open_generic(substream, 1);
++}
++
++/* close callback */
++static int snd_bcm2835_playback_close(struct snd_pcm_substream *substream)
++{
++ /* the hardware-specific codes will be here */
++
++ bcm2835_chip_t *chip;
++ struct snd_pcm_runtime *runtime;
++ bcm2835_alsa_stream_t *alsa_stream;
++
++ audio_info(" .. IN\n");
++
++ chip = snd_pcm_substream_chip(substream);
++ if(mutex_lock_interruptible(&chip->audio_mutex))
++ {
++ audio_error("Interrupted whilst waiting for lock\n");
++ return -EINTR;
++ }
++ runtime = substream->runtime;
++ alsa_stream = runtime->private_data;
++
++ audio_info("Alsa close\n");
++
++ /*
++ * Call stop if it's still running. This happens when app
++ * is force killed and we don't get a stop trigger.
++ */
++ if (alsa_stream->running) {
++ int err;
++ err = bcm2835_audio_stop(alsa_stream);
++ alsa_stream->running = 0;
++ if (err != 0)
++ audio_error(" Failed to STOP alsa device\n");
++ }
++
++ alsa_stream->period_size = 0;
++ alsa_stream->buffer_size = 0;
++
++ if (alsa_stream->open) {
++ alsa_stream->open = 0;
++ bcm2835_audio_close(alsa_stream);
++ }
++ if (alsa_stream->chip)
++ alsa_stream->chip->alsa_stream[alsa_stream->idx] = NULL;
++ /*
++ * Do not free up alsa_stream here, it will be freed up by
++ * runtime->private_free callback we registered in *_open above
++ */
++
++ chip->opened &= ~(1 << substream->number);
++
++ mutex_unlock(&chip->audio_mutex);
++ audio_info(" .. OUT\n");
++
++ return 0;
++}
++
++/* hw_params callback */
++static int snd_bcm2835_pcm_hw_params(struct snd_pcm_substream *substream,
++ struct snd_pcm_hw_params *params)
++{
++ struct snd_pcm_runtime *runtime = substream->runtime;
++ bcm2835_alsa_stream_t *alsa_stream = runtime->private_data;
++ int err;
++
++ audio_info(" .. IN\n");
++
++ err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params));
++ if (err < 0) {
++ audio_error
++ (" pcm_lib_malloc failed to allocated pages for buffers\n");
++ return err;
++ }
++
++ alsa_stream->channels = params_channels(params);
++ alsa_stream->params_rate = params_rate(params);
++ alsa_stream->pcm_format_width = snd_pcm_format_width(params_format (params));
++ audio_info(" .. OUT\n");
++
++ return err;
++}
++
++/* hw_free callback */
++static int snd_bcm2835_pcm_hw_free(struct snd_pcm_substream *substream)
++{
++ audio_info(" .. IN\n");
++ return snd_pcm_lib_free_pages(substream);
++}
++
++/* prepare callback */
++static int snd_bcm2835_pcm_prepare(struct snd_pcm_substream *substream)
++{
++ bcm2835_chip_t *chip = snd_pcm_substream_chip(substream);
++ struct snd_pcm_runtime *runtime = substream->runtime;
++ bcm2835_alsa_stream_t *alsa_stream = runtime->private_data;
++ int channels;
++ int err;
++
++ audio_info(" .. IN\n");
++
++ /* notify the vchiq that it should enter spdif passthrough mode by
++ * setting channels=0 (see
++ * https://github.com/raspberrypi/linux/issues/528) */
++ if (chip->spdif_status & IEC958_AES0_NONAUDIO)
++ channels = 0;
++ else
++ channels = alsa_stream->channels;
++
++ err = bcm2835_audio_set_params(alsa_stream, channels,
++ alsa_stream->params_rate,
++ alsa_stream->pcm_format_width);
++ if (err < 0) {
++ audio_error(" error setting hw params\n");
++ }
++
++ bcm2835_audio_setup(alsa_stream);
++
++ /* in preparation of the stream, set the controls (volume level) of the stream */
++ bcm2835_audio_set_ctls(alsa_stream->chip);
++
++
++ memset(&alsa_stream->pcm_indirect, 0, sizeof(alsa_stream->pcm_indirect));
++
++ alsa_stream->pcm_indirect.hw_buffer_size =
++ alsa_stream->pcm_indirect.sw_buffer_size =
++ snd_pcm_lib_buffer_bytes(substream);
++
++ alsa_stream->buffer_size = snd_pcm_lib_buffer_bytes(substream);
++ alsa_stream->period_size = snd_pcm_lib_period_bytes(substream);
++ alsa_stream->pos = 0;
++
++ audio_debug("buffer_size=%d, period_size=%d pos=%d frame_bits=%d\n",
++ alsa_stream->buffer_size, alsa_stream->period_size,
++ alsa_stream->pos, runtime->frame_bits);
++
++ audio_info(" .. OUT\n");
++ return 0;
++}
++
++static void snd_bcm2835_pcm_transfer(struct snd_pcm_substream *substream,
++ struct snd_pcm_indirect *rec, size_t bytes)
++{
++ struct snd_pcm_runtime *runtime = substream->runtime;
++ bcm2835_alsa_stream_t *alsa_stream = runtime->private_data;
++ void *src = (void *)(substream->runtime->dma_area + rec->sw_data);
++ int err;
++
++ err = bcm2835_audio_write(alsa_stream, bytes, src);
++ if (err)
++ audio_error(" Failed to transfer to alsa device (%d)\n", err);
++
++}
++
++static int snd_bcm2835_pcm_ack(struct snd_pcm_substream *substream)
++{
++ struct snd_pcm_runtime *runtime = substream->runtime;
++ bcm2835_alsa_stream_t *alsa_stream = runtime->private_data;
++ struct snd_pcm_indirect *pcm_indirect = &alsa_stream->pcm_indirect;
++
++ pcm_indirect->hw_queue_size = runtime->hw.buffer_bytes_max;
++ snd_pcm_indirect_playback_transfer(substream, pcm_indirect,
++ snd_bcm2835_pcm_transfer);
++ return 0;
++}
++
++/* trigger callback */
++static int snd_bcm2835_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
++{
++ struct snd_pcm_runtime *runtime = substream->runtime;
++ bcm2835_alsa_stream_t *alsa_stream = runtime->private_data;
++ int err = 0;
++
++ audio_info(" .. IN\n");
++
++ switch (cmd) {
++ case SNDRV_PCM_TRIGGER_START:
++ audio_debug("bcm2835_AUDIO_TRIGGER_START running=%d\n",
++ alsa_stream->running);
++ if (!alsa_stream->running) {
++ err = bcm2835_audio_start(alsa_stream);
++ if (err == 0) {
++ alsa_stream->pcm_indirect.hw_io =
++ alsa_stream->pcm_indirect.hw_data =
++ bytes_to_frames(runtime,
++ alsa_stream->pos);
++ substream->ops->ack(substream);
++ alsa_stream->running = 1;
++ alsa_stream->draining = 1;
++ } else {
++ audio_error(" Failed to START alsa device (%d)\n", err);
++ }
++ }
++ break;
++ case SNDRV_PCM_TRIGGER_STOP:
++ audio_debug
++ ("bcm2835_AUDIO_TRIGGER_STOP running=%d draining=%d\n",
++ alsa_stream->running, runtime->status->state == SNDRV_PCM_STATE_DRAINING);
++ if (runtime->status->state == SNDRV_PCM_STATE_DRAINING) {
++ audio_info("DRAINING\n");
++ alsa_stream->draining = 1;
++ } else {
++ audio_info("DROPPING\n");
++ alsa_stream->draining = 0;
++ }
++ if (alsa_stream->running) {
++ err = bcm2835_audio_stop(alsa_stream);
++ if (err != 0)
++ audio_error(" Failed to STOP alsa device (%d)\n", err);
++ alsa_stream->running = 0;
++ }
++ break;
++ default:
++ err = -EINVAL;
++ }
++
++ audio_info(" .. OUT\n");
++ return err;
++}
++
++/* pointer callback */
++static snd_pcm_uframes_t
++snd_bcm2835_pcm_pointer(struct snd_pcm_substream *substream)
++{
++ struct snd_pcm_runtime *runtime = substream->runtime;
++ bcm2835_alsa_stream_t *alsa_stream = runtime->private_data;
++
++ audio_info(" .. IN\n");
++
++ audio_debug("pcm_pointer... (%d) hwptr=%d appl=%d pos=%d\n", 0,
++ frames_to_bytes(runtime, runtime->status->hw_ptr),
++ frames_to_bytes(runtime, runtime->control->appl_ptr),
++ alsa_stream->pos);
++
++ audio_info(" .. OUT\n");
++ return snd_pcm_indirect_playback_pointer(substream,
++ &alsa_stream->pcm_indirect,
++ alsa_stream->pos);
++}
++
++static int snd_bcm2835_pcm_lib_ioctl(struct snd_pcm_substream *substream,
++ unsigned int cmd, void *arg)
++{
++ int ret = snd_pcm_lib_ioctl(substream, cmd, arg);
++ audio_info(" .. substream=%p, cmd=%d, arg=%p (%x) ret=%d\n", substream,
++ cmd, arg, arg ? *(unsigned *)arg : 0, ret);
++ return ret;
++}
++
++/* operators */
++static struct snd_pcm_ops snd_bcm2835_playback_ops = {
++ .open = snd_bcm2835_playback_open,
++ .close = snd_bcm2835_playback_close,
++ .ioctl = snd_bcm2835_pcm_lib_ioctl,
++ .hw_params = snd_bcm2835_pcm_hw_params,
++ .hw_free = snd_bcm2835_pcm_hw_free,
++ .prepare = snd_bcm2835_pcm_prepare,
++ .trigger = snd_bcm2835_pcm_trigger,
++ .pointer = snd_bcm2835_pcm_pointer,
++ .ack = snd_bcm2835_pcm_ack,
++};
++
++static struct snd_pcm_ops snd_bcm2835_playback_spdif_ops = {
++ .open = snd_bcm2835_playback_spdif_open,
++ .close = snd_bcm2835_playback_close,
++ .ioctl = snd_bcm2835_pcm_lib_ioctl,
++ .hw_params = snd_bcm2835_pcm_hw_params,
++ .hw_free = snd_bcm2835_pcm_hw_free,
++ .prepare = snd_bcm2835_pcm_prepare,
++ .trigger = snd_bcm2835_pcm_trigger,
++ .pointer = snd_bcm2835_pcm_pointer,
++ .ack = snd_bcm2835_pcm_ack,
++};
++
++/* create a pcm device */
++int snd_bcm2835_new_pcm(bcm2835_chip_t * chip)
++{
++ struct snd_pcm *pcm;
++ int err;
++
++ audio_info(" .. IN\n");
++ mutex_init(&chip->audio_mutex);
++ if(mutex_lock_interruptible(&chip->audio_mutex))
++ {
++ audio_error("Interrupted whilst waiting for lock\n");
++ return -EINTR;
++ }
++ err =
++ snd_pcm_new(chip->card, "bcm2835 ALSA", 0, MAX_SUBSTREAMS, 0, &pcm);
++ if (err < 0)
++ goto out;
++ pcm->private_data = chip;
++ strcpy(pcm->name, "bcm2835 ALSA");
++ chip->pcm = pcm;
++ chip->dest = AUDIO_DEST_AUTO;
++ chip->volume = alsa2chip(0);
++ chip->mute = CTRL_VOL_UNMUTE; /*disable mute on startup */
++ /* set operators */
++ snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
++ &snd_bcm2835_playback_ops);
++
++ /* pre-allocation of buffers */
++ /* NOTE: this may fail */
++ snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_CONTINUOUS,
++ snd_dma_continuous_data
++ (GFP_KERNEL), 64 * 1024,
++ 64 * 1024);
++
++out:
++ mutex_unlock(&chip->audio_mutex);
++ audio_info(" .. OUT\n");
++
++ return 0;
++}
++
++int snd_bcm2835_new_spdif_pcm(bcm2835_chip_t * chip)
++{
++ struct snd_pcm *pcm;
++ int err;
++
++ audio_info(" .. IN\n");
++ if(mutex_lock_interruptible(&chip->audio_mutex))
++ {
++ audio_error("Interrupted whilst waiting for lock\n");
++ return -EINTR;
++ }
++ err = snd_pcm_new(chip->card, "bcm2835 ALSA", 1, 1, 0, &pcm);
++ if (err < 0)
++ goto out;
++
++ pcm->private_data = chip;
++ strcpy(pcm->name, "bcm2835 IEC958/HDMI");
++ chip->pcm_spdif = pcm;
++ snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
++ &snd_bcm2835_playback_spdif_ops);
++
++ snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_CONTINUOUS,
++ snd_dma_continuous_data (GFP_KERNEL),
++ 64 * 1024, 64 * 1024);
++out:
++ mutex_unlock(&chip->audio_mutex);
++ audio_info(" .. OUT\n");
++
++ return 0;
++}
+diff -Nur linux-4.1.3/sound/arm/bcm2835-vchiq.c linux-xbian-rpi/sound/arm/bcm2835-vchiq.c
+--- linux-4.1.3/sound/arm/bcm2835-vchiq.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/sound/arm/bcm2835-vchiq.c 2015-07-28 01:20:58.465085369 +0200
+@@ -0,0 +1,902 @@
++/*****************************************************************************
++* Copyright 2011 Broadcom Corporation. All rights reserved.
++*
++* Unless you and Broadcom execute a separate written software license
++* agreement governing use of this software, this software is licensed to you
++* under the terms of the GNU General Public License version 2, available at
++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
++*
++* Notwithstanding the above, under no circumstances may you combine this
++* software in any way with any other Broadcom software provided under a
++* license other than the GPL, without Broadcom's express prior written
++* consent.
++*****************************************************************************/
++
++#include <linux/device.h>
++#include <sound/core.h>
++#include <sound/initval.h>
++#include <sound/pcm.h>
++#include <linux/io.h>
++#include <linux/interrupt.h>
++#include <linux/fs.h>
++#include <linux/file.h>
++#include <linux/mm.h>
++#include <linux/syscalls.h>
++#include <asm/uaccess.h>
++#include <linux/slab.h>
++#include <linux/delay.h>
++#include <linux/atomic.h>
++#include <linux/module.h>
++#include <linux/completion.h>
++
++#include "bcm2835.h"
++
++/* ---- Include Files -------------------------------------------------------- */
++
++#include "interface/vchi/vchi.h"
++#include "vc_vchi_audioserv_defs.h"
++
++/* ---- Private Constants and Types ------------------------------------------ */
++
++#define BCM2835_AUDIO_STOP 0
++#define BCM2835_AUDIO_START 1
++#define BCM2835_AUDIO_WRITE 2
++
++/* Logging macros (for remapping to other logging mechanisms, i.e., printf) */
++#ifdef AUDIO_DEBUG_ENABLE
++ #define LOG_ERR( fmt, arg... ) pr_err( "%s:%d " fmt, __func__, __LINE__, ##arg)
++ #define LOG_WARN( fmt, arg... ) pr_info( "%s:%d " fmt, __func__, __LINE__, ##arg)
++ #define LOG_INFO( fmt, arg... ) pr_info( "%s:%d " fmt, __func__, __LINE__, ##arg)
++ #define LOG_DBG( fmt, arg... ) pr_info( "%s:%d " fmt, __func__, __LINE__, ##arg)
++#else
++ #define LOG_ERR( fmt, arg... ) pr_err( "%s:%d " fmt, __func__, __LINE__, ##arg)
++ #define LOG_WARN( fmt, arg... )
++ #define LOG_INFO( fmt, arg... )
++ #define LOG_DBG( fmt, arg... )
++#endif
++
++typedef struct opaque_AUDIO_INSTANCE_T {
++ uint32_t num_connections;
++ VCHI_SERVICE_HANDLE_T vchi_handle[VCHI_MAX_NUM_CONNECTIONS];
++ struct completion msg_avail_comp;
++ struct mutex vchi_mutex;
++ bcm2835_alsa_stream_t *alsa_stream;
++ int32_t result;
++ short peer_version;
++} AUDIO_INSTANCE_T;
++
++bool force_bulk = false;
++
++/* ---- Private Variables ---------------------------------------------------- */
++
++/* ---- Private Function Prototypes ------------------------------------------ */
++
++/* ---- Private Functions ---------------------------------------------------- */
++
++static int bcm2835_audio_stop_worker(bcm2835_alsa_stream_t * alsa_stream);
++static int bcm2835_audio_start_worker(bcm2835_alsa_stream_t * alsa_stream);
++static int bcm2835_audio_write_worker(bcm2835_alsa_stream_t *alsa_stream,
++ uint32_t count, void *src);
++
++typedef struct {
++ struct work_struct my_work;
++ bcm2835_alsa_stream_t *alsa_stream;
++ int cmd;
++ void *src;
++ uint32_t count;
++} my_work_t;
++
++static void my_wq_function(struct work_struct *work)
++{
++ my_work_t *w = (my_work_t *) work;
++ int ret = -9;
++ LOG_DBG(" .. IN %p:%d\n", w->alsa_stream, w->cmd);
++ switch (w->cmd) {
++ case BCM2835_AUDIO_START:
++ ret = bcm2835_audio_start_worker(w->alsa_stream);
++ break;
++ case BCM2835_AUDIO_STOP:
++ ret = bcm2835_audio_stop_worker(w->alsa_stream);
++ break;
++ case BCM2835_AUDIO_WRITE:
++ ret = bcm2835_audio_write_worker(w->alsa_stream, w->count,
++ w->src);
++ break;
++ default:
++ LOG_ERR(" Unexpected work: %p:%d\n", w->alsa_stream, w->cmd);
++ break;
++ }
++ kfree((void *)work);
++ LOG_DBG(" .. OUT %d\n", ret);
++}
++
++int bcm2835_audio_start(bcm2835_alsa_stream_t * alsa_stream)
++{
++ int ret = -1;
++ LOG_DBG(" .. IN\n");
++ if (alsa_stream->my_wq) {
++ my_work_t *work = kmalloc(sizeof(my_work_t), GFP_ATOMIC);
++ /*--- Queue some work (item 1) ---*/
++ if (work) {
++ INIT_WORK((struct work_struct *)work, my_wq_function);
++ work->alsa_stream = alsa_stream;
++ work->cmd = BCM2835_AUDIO_START;
++ if (queue_work
++ (alsa_stream->my_wq, (struct work_struct *)work))
++ ret = 0;
++ } else
++ LOG_ERR(" .. Error: NULL work kmalloc\n");
++ }
++ LOG_DBG(" .. OUT %d\n", ret);
++ return ret;
++}
++
++int bcm2835_audio_stop(bcm2835_alsa_stream_t * alsa_stream)
++{
++ int ret = -1;
++ LOG_DBG(" .. IN\n");
++ if (alsa_stream->my_wq) {
++ my_work_t *work = kmalloc(sizeof(my_work_t), GFP_ATOMIC);
++ /*--- Queue some work (item 1) ---*/
++ if (work) {
++ INIT_WORK((struct work_struct *)work, my_wq_function);
++ work->alsa_stream = alsa_stream;
++ work->cmd = BCM2835_AUDIO_STOP;
++ if (queue_work
++ (alsa_stream->my_wq, (struct work_struct *)work))
++ ret = 0;
++ } else
++ LOG_ERR(" .. Error: NULL work kmalloc\n");
++ }
++ LOG_DBG(" .. OUT %d\n", ret);
++ return ret;
++}
++
++int bcm2835_audio_write(bcm2835_alsa_stream_t *alsa_stream,
++ uint32_t count, void *src)
++{
++ int ret = -1;
++ LOG_DBG(" .. IN\n");
++ if (alsa_stream->my_wq) {
++ my_work_t *work = kmalloc(sizeof(my_work_t), GFP_ATOMIC);
++ /*--- Queue some work (item 1) ---*/
++ if (work) {
++ INIT_WORK((struct work_struct *)work, my_wq_function);
++ work->alsa_stream = alsa_stream;
++ work->cmd = BCM2835_AUDIO_WRITE;
++ work->src = src;
++ work->count = count;
++ if (queue_work
++ (alsa_stream->my_wq, (struct work_struct *)work))
++ ret = 0;
++ } else
++ LOG_ERR(" .. Error: NULL work kmalloc\n");
++ }
++ LOG_DBG(" .. OUT %d\n", ret);
++ return ret;
++}
++
++void my_workqueue_init(bcm2835_alsa_stream_t * alsa_stream)
++{
++ alsa_stream->my_wq = alloc_workqueue("my_queue", WQ_HIGHPRI, 1);
++ return;
++}
++
++void my_workqueue_quit(bcm2835_alsa_stream_t * alsa_stream)
++{
++ if (alsa_stream->my_wq) {
++ flush_workqueue(alsa_stream->my_wq);
++ destroy_workqueue(alsa_stream->my_wq);
++ alsa_stream->my_wq = NULL;
++ }
++ return;
++}
++
++static void audio_vchi_callback(void *param,
++ const VCHI_CALLBACK_REASON_T reason,
++ void *msg_handle)
++{
++ AUDIO_INSTANCE_T *instance = (AUDIO_INSTANCE_T *) param;
++ int32_t status;
++ int32_t msg_len;
++ VC_AUDIO_MSG_T m;
++ LOG_DBG(" .. IN instance=%p, handle=%p, alsa=%p, reason=%d, handle=%p\n",
++ instance, instance ? instance->vchi_handle[0] : NULL, instance ? instance->alsa_stream : NULL, reason, msg_handle);
++
++ if (reason != VCHI_CALLBACK_MSG_AVAILABLE) {
++ return;
++ }
++ if (!instance) {
++ LOG_ERR(" .. instance is null\n");
++ BUG();
++ return;
++ }
++ if (!instance->vchi_handle[0]) {
++ LOG_ERR(" .. instance->vchi_handle[0] is null\n");
++ BUG();
++ return;
++ }
++ status = vchi_msg_dequeue(instance->vchi_handle[0],
++ &m, sizeof m, &msg_len, VCHI_FLAGS_NONE);
++ if (m.type == VC_AUDIO_MSG_TYPE_RESULT) {
++ LOG_DBG
++ (" .. instance=%p, m.type=VC_AUDIO_MSG_TYPE_RESULT, success=%d\n",
++ instance, m.u.result.success);
++ instance->result = m.u.result.success;
++ complete(&instance->msg_avail_comp);
++ } else if (m.type == VC_AUDIO_MSG_TYPE_COMPLETE) {
++ bcm2835_alsa_stream_t *alsa_stream = instance->alsa_stream;
++ irq_handler_t callback = (irq_handler_t) m.u.complete.callback;
++ LOG_DBG
++ (" .. instance=%p, m.type=VC_AUDIO_MSG_TYPE_COMPLETE, complete=%d\n",
++ instance, m.u.complete.count);
++ if (alsa_stream && callback) {
++ atomic_add(m.u.complete.count, &alsa_stream->retrieved);
++ callback(0, alsa_stream);
++ } else {
++ LOG_ERR(" .. unexpected alsa_stream=%p, callback=%p\n",
++ alsa_stream, callback);
++ }
++ } else {
++ LOG_ERR(" .. unexpected m.type=%d\n", m.type);
++ }
++ LOG_DBG(" .. OUT\n");
++}
++
++static AUDIO_INSTANCE_T *vc_vchi_audio_init(VCHI_INSTANCE_T vchi_instance,
++ VCHI_CONNECTION_T **
++ vchi_connections,
++ uint32_t num_connections)
++{
++ uint32_t i;
++ AUDIO_INSTANCE_T *instance;
++ int status;
++
++ LOG_DBG("%s: start", __func__);
++
++ if (num_connections > VCHI_MAX_NUM_CONNECTIONS) {
++ LOG_ERR("%s: unsupported number of connections %u (max=%u)\n",
++ __func__, num_connections, VCHI_MAX_NUM_CONNECTIONS);
++
++ return NULL;
++ }
++ /* Allocate memory for this instance */
++ instance = kmalloc(sizeof(*instance), GFP_KERNEL);
++ if (!instance)
++ return NULL;
++
++ memset(instance, 0, sizeof(*instance));
++ instance->num_connections = num_connections;
++
++ /* Create a lock for exclusive, serialized VCHI connection access */
++ mutex_init(&instance->vchi_mutex);
++ /* Open the VCHI service connections */
++ for (i = 0; i < num_connections; i++) {
++ SERVICE_CREATION_T params = {
++ VCHI_VERSION_EX(VC_AUDIOSERV_VER, VC_AUDIOSERV_MIN_VER),
++ VC_AUDIO_SERVER_NAME, // 4cc service code
++ vchi_connections[i], // passed in fn pointers
++ 0, // rx fifo size (unused)
++ 0, // tx fifo size (unused)
++ audio_vchi_callback, // service callback
++ instance, // service callback parameter
++ 1, //TODO: remove VCOS_FALSE, // unaligned bulk recieves
++ 1, //TODO: remove VCOS_FALSE, // unaligned bulk transmits
++ 0 // want crc check on bulk transfers
++ };
++
++ LOG_DBG("%s: about to open %i\n", __func__, i);
++ status = vchi_service_open(vchi_instance, &params,
++ &instance->vchi_handle[i]);
++ LOG_DBG("%s: opened %i: %p=%d\n", __func__, i, instance->vchi_handle[i], status);
++ if (status) {
++ LOG_ERR
++ ("%s: failed to open VCHI service connection (status=%d)\n",
++ __func__, status);
++
++ goto err_close_services;
++ }
++ /* Finished with the service for now */
++ vchi_service_release(instance->vchi_handle[i]);
++ }
++
++ LOG_DBG("%s: okay\n", __func__);
++ return instance;
++
++err_close_services:
++ for (i = 0; i < instance->num_connections; i++) {
++ LOG_ERR("%s: closing %i: %p\n", __func__, i, instance->vchi_handle[i]);
++ if (instance->vchi_handle[i])
++ vchi_service_close(instance->vchi_handle[i]);
++ }
++
++ kfree(instance);
++ LOG_ERR("%s: error\n", __func__);
++
++ return NULL;
++}
++
++static int32_t vc_vchi_audio_deinit(AUDIO_INSTANCE_T * instance)
++{
++ uint32_t i;
++
++ LOG_DBG(" .. IN\n");
++
++ if (instance == NULL) {
++ LOG_ERR("%s: invalid handle %p\n", __func__, instance);
++
++ return -1;
++ }
++
++ LOG_DBG(" .. about to lock (%d)\n", instance->num_connections);
++ if(mutex_lock_interruptible(&instance->vchi_mutex))
++ {
++ LOG_DBG("Interrupted whilst waiting for lock on (%d)\n",instance->num_connections);
++ return -EINTR;
++ }
++
++ /* Close all VCHI service connections */
++ for (i = 0; i < instance->num_connections; i++) {
++ int32_t success;
++ LOG_DBG(" .. %i:closing %p\n", i, instance->vchi_handle[i]);
++ vchi_service_use(instance->vchi_handle[i]);
++
++ success = vchi_service_close(instance->vchi_handle[i]);
++ if (success != 0) {
++ LOG_DBG
++ ("%s: failed to close VCHI service connection (status=%d)\n",
++ __func__, success);
++ }
++ }
++
++ mutex_unlock(&instance->vchi_mutex);
++
++ kfree(instance);
++
++ LOG_DBG(" .. OUT\n");
++
++ return 0;
++}
++
++static int bcm2835_audio_open_connection(bcm2835_alsa_stream_t * alsa_stream)
++{
++ static VCHI_INSTANCE_T vchi_instance;
++ static VCHI_CONNECTION_T *vchi_connection;
++ static int initted;
++ AUDIO_INSTANCE_T *instance = alsa_stream->instance;
++ int ret;
++ LOG_DBG(" .. IN\n");
++
++ LOG_INFO("%s: start\n", __func__);
++ BUG_ON(instance);
++ if (instance) {
++ LOG_ERR("%s: VCHI instance already open (%p)\n",
++ __func__, instance);
++ instance->alsa_stream = alsa_stream;
++ alsa_stream->instance = instance;
++ ret = 0; // xxx todo -1;
++ goto err_free_mem;
++ }
++
++ /* Initialize and create a VCHI connection */
++ if (!initted) {
++ ret = vchi_initialise(&vchi_instance);
++ if (ret != 0) {
++ LOG_ERR("%s: failed to initialise VCHI instance (ret=%d)\n",
++ __func__, ret);
++
++ ret = -EIO;
++ goto err_free_mem;
++ }
++ ret = vchi_connect(NULL, 0, vchi_instance);
++ if (ret != 0) {
++ LOG_ERR("%s: failed to connect VCHI instance (ret=%d)\n",
++ __func__, ret);
++
++ ret = -EIO;
++ goto err_free_mem;
++ }
++ initted = 1;
++ }
++
++ /* Initialize an instance of the audio service */
++ instance = vc_vchi_audio_init(vchi_instance, &vchi_connection, 1);
++
++ if (instance == NULL) {
++ LOG_ERR("%s: failed to initialize audio service\n", __func__);
++
++ ret = -EPERM;
++ goto err_free_mem;
++ }
++
++ instance->alsa_stream = alsa_stream;
++ alsa_stream->instance = instance;
++
++ LOG_DBG(" success !\n");
++err_free_mem:
++ LOG_DBG(" .. OUT\n");
++
++ return ret;
++}
++
++int bcm2835_audio_open(bcm2835_alsa_stream_t * alsa_stream)
++{
++ AUDIO_INSTANCE_T *instance;
++ VC_AUDIO_MSG_T m;
++ int32_t success;
++ int ret;
++ LOG_DBG(" .. IN\n");
++
++ my_workqueue_init(alsa_stream);
++
++ ret = bcm2835_audio_open_connection(alsa_stream);
++ if (ret != 0) {
++ ret = -1;
++ goto exit;
++ }
++ instance = alsa_stream->instance;
++ LOG_DBG(" instance (%p)\n", instance);
++
++ if(mutex_lock_interruptible(&instance->vchi_mutex))
++ {
++ LOG_DBG("Interrupted whilst waiting for lock on (%d)\n",instance->num_connections);
++ return -EINTR;
++ }
++ vchi_service_use(instance->vchi_handle[0]);
++
++ m.type = VC_AUDIO_MSG_TYPE_OPEN;
++
++ /* Send the message to the videocore */
++ success = vchi_msg_queue(instance->vchi_handle[0],
++ &m, sizeof m,
++ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL);
++
++ if (success != 0) {
++ LOG_ERR("%s: failed on vchi_msg_queue (status=%d)\n",
++ __func__, success);
++
++ ret = -1;
++ goto unlock;
++ }
++
++ ret = 0;
++
++unlock:
++ vchi_service_release(instance->vchi_handle[0]);
++ mutex_unlock(&instance->vchi_mutex);
++exit:
++ LOG_DBG(" .. OUT\n");
++ return ret;
++}
++
++static int bcm2835_audio_set_ctls_chan(bcm2835_alsa_stream_t * alsa_stream,
++ bcm2835_chip_t * chip)
++{
++ VC_AUDIO_MSG_T m;
++ AUDIO_INSTANCE_T *instance = alsa_stream->instance;
++ int32_t success;
++ int ret;
++ LOG_DBG(" .. IN\n");
++
++ LOG_INFO
++ (" Setting ALSA dest(%d), volume(%d)\n", chip->dest, chip->volume);
++
++ if(mutex_lock_interruptible(&instance->vchi_mutex))
++ {
++ LOG_DBG("Interrupted whilst waiting for lock on (%d)\n",instance->num_connections);
++ return -EINTR;
++ }
++ vchi_service_use(instance->vchi_handle[0]);
++
++ instance->result = -1;
++
++ m.type = VC_AUDIO_MSG_TYPE_CONTROL;
++ m.u.control.dest = chip->dest;
++ m.u.control.volume = chip->volume;
++
++ /* Create the message available completion */
++ init_completion(&instance->msg_avail_comp);
++
++ /* Send the message to the videocore */
++ success = vchi_msg_queue(instance->vchi_handle[0],
++ &m, sizeof m,
++ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL);
++
++ if (success != 0) {
++ LOG_ERR("%s: failed on vchi_msg_queue (status=%d)\n",
++ __func__, success);
++
++ ret = -1;
++ goto unlock;
++ }
++
++ /* We are expecting a reply from the videocore */
++ ret = wait_for_completion_interruptible(&instance->msg_avail_comp);
++ if (ret) {
++ LOG_DBG("%s: failed on waiting for event (status=%d)\n",
++ __func__, success);
++ goto unlock;
++ }
++
++ if (instance->result != 0) {
++ LOG_ERR("%s: result=%d\n", __func__, instance->result);
++
++ ret = -1;
++ goto unlock;
++ }
++
++ ret = 0;
++
++unlock:
++ vchi_service_release(instance->vchi_handle[0]);
++ mutex_unlock(&instance->vchi_mutex);
++
++ LOG_DBG(" .. OUT\n");
++ return ret;
++}
++
++int bcm2835_audio_set_ctls(bcm2835_chip_t * chip)
++{
++ int i;
++ int ret = 0;
++ LOG_DBG(" .. IN\n");
++ LOG_DBG(" Setting ALSA dest(%d), volume(%d)\n", chip->dest, chip->volume);
++
++ /* change ctls for all substreams */
++ for (i = 0; i < MAX_SUBSTREAMS; i++) {
++ if (chip->avail_substreams & (1 << i)) {
++ if (!chip->alsa_stream[i])
++ {
++ LOG_DBG(" No ALSA stream available?! %i:%p (%x)\n", i, chip->alsa_stream[i], chip->avail_substreams);
++ ret = 0;
++ }
++ else if (bcm2835_audio_set_ctls_chan /* returns 0 on success */
++ (chip->alsa_stream[i], chip) != 0)
++ {
++ LOG_ERR("Couldn't set the controls for stream %d\n", i);
++ ret = -1;
++ }
++ else LOG_DBG(" Controls set for stream %d\n", i);
++ }
++ }
++ LOG_DBG(" .. OUT ret=%d\n", ret);
++ return ret;
++}
++
++int bcm2835_audio_set_params(bcm2835_alsa_stream_t * alsa_stream,
++ uint32_t channels, uint32_t samplerate,
++ uint32_t bps)
++{
++ VC_AUDIO_MSG_T m;
++ AUDIO_INSTANCE_T *instance = alsa_stream->instance;
++ int32_t success;
++ int ret;
++ LOG_DBG(" .. IN\n");
++
++ LOG_INFO
++ (" Setting ALSA channels(%d), samplerate(%d), bits-per-sample(%d)\n",
++ channels, samplerate, bps);
++
++ /* resend ctls - alsa_stream may not have been open when first send */
++ ret = bcm2835_audio_set_ctls_chan(alsa_stream, alsa_stream->chip);
++ if (ret != 0) {
++ LOG_ERR(" Alsa controls not supported\n");
++ return -EINVAL;
++ }
++
++ if(mutex_lock_interruptible(&instance->vchi_mutex))
++ {
++ LOG_DBG("Interrupted whilst waiting for lock on (%d)\n",instance->num_connections);
++ return -EINTR;
++ }
++ vchi_service_use(instance->vchi_handle[0]);
++
++ instance->result = -1;
++
++ m.type = VC_AUDIO_MSG_TYPE_CONFIG;
++ m.u.config.channels = channels;
++ m.u.config.samplerate = samplerate;
++ m.u.config.bps = bps;
++
++ /* Create the message available completion */
++ init_completion(&instance->msg_avail_comp);
++
++ /* Send the message to the videocore */
++ success = vchi_msg_queue(instance->vchi_handle[0],
++ &m, sizeof m,
++ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL);
++
++ if (success != 0) {
++ LOG_ERR("%s: failed on vchi_msg_queue (status=%d)\n",
++ __func__, success);
++
++ ret = -1;
++ goto unlock;
++ }
++
++ /* We are expecting a reply from the videocore */
++ ret = wait_for_completion_interruptible(&instance->msg_avail_comp);
++ if (ret) {
++ LOG_DBG("%s: failed on waiting for event (status=%d)\n",
++ __func__, success);
++ goto unlock;
++ }
++
++ if (instance->result != 0) {
++ LOG_ERR("%s: result=%d", __func__, instance->result);
++
++ ret = -1;
++ goto unlock;
++ }
++
++ ret = 0;
++
++unlock:
++ vchi_service_release(instance->vchi_handle[0]);
++ mutex_unlock(&instance->vchi_mutex);
++
++ LOG_DBG(" .. OUT\n");
++ return ret;
++}
++
++int bcm2835_audio_setup(bcm2835_alsa_stream_t * alsa_stream)
++{
++ LOG_DBG(" .. IN\n");
++
++ LOG_DBG(" .. OUT\n");
++
++ return 0;
++}
++
++static int bcm2835_audio_start_worker(bcm2835_alsa_stream_t * alsa_stream)
++{
++ VC_AUDIO_MSG_T m;
++ AUDIO_INSTANCE_T *instance = alsa_stream->instance;
++ int32_t success;
++ int ret;
++ LOG_DBG(" .. IN\n");
++
++ if(mutex_lock_interruptible(&instance->vchi_mutex))
++ {
++ LOG_DBG("Interrupted whilst waiting for lock on (%d)\n",instance->num_connections);
++ return -EINTR;
++ }
++ vchi_service_use(instance->vchi_handle[0]);
++
++ m.type = VC_AUDIO_MSG_TYPE_START;
++
++ /* Send the message to the videocore */
++ success = vchi_msg_queue(instance->vchi_handle[0],
++ &m, sizeof m,
++ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL);
++
++ if (success != 0) {
++ LOG_ERR("%s: failed on vchi_msg_queue (status=%d)\n",
++ __func__, success);
++
++ ret = -1;
++ goto unlock;
++ }
++
++ ret = 0;
++
++unlock:
++ vchi_service_release(instance->vchi_handle[0]);
++ mutex_unlock(&instance->vchi_mutex);
++ LOG_DBG(" .. OUT\n");
++ return ret;
++}
++
++static int bcm2835_audio_stop_worker(bcm2835_alsa_stream_t * alsa_stream)
++{
++ VC_AUDIO_MSG_T m;
++ AUDIO_INSTANCE_T *instance = alsa_stream->instance;
++ int32_t success;
++ int ret;
++ LOG_DBG(" .. IN\n");
++
++ if(mutex_lock_interruptible(&instance->vchi_mutex))
++ {
++ LOG_DBG("Interrupted whilst waiting for lock on (%d)\n",instance->num_connections);
++ return -EINTR;
++ }
++ vchi_service_use(instance->vchi_handle[0]);
++
++ m.type = VC_AUDIO_MSG_TYPE_STOP;
++ m.u.stop.draining = alsa_stream->draining;
++
++ /* Send the message to the videocore */
++ success = vchi_msg_queue(instance->vchi_handle[0],
++ &m, sizeof m,
++ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL);
++
++ if (success != 0) {
++ LOG_ERR("%s: failed on vchi_msg_queue (status=%d)\n",
++ __func__, success);
++
++ ret = -1;
++ goto unlock;
++ }
++
++ ret = 0;
++
++unlock:
++ vchi_service_release(instance->vchi_handle[0]);
++ mutex_unlock(&instance->vchi_mutex);
++ LOG_DBG(" .. OUT\n");
++ return ret;
++}
++
++int bcm2835_audio_close(bcm2835_alsa_stream_t * alsa_stream)
++{
++ VC_AUDIO_MSG_T m;
++ AUDIO_INSTANCE_T *instance = alsa_stream->instance;
++ int32_t success;
++ int ret;
++ LOG_DBG(" .. IN\n");
++
++ my_workqueue_quit(alsa_stream);
++
++ if(mutex_lock_interruptible(&instance->vchi_mutex))
++ {
++ LOG_DBG("Interrupted whilst waiting for lock on (%d)\n",instance->num_connections);
++ return -EINTR;
++ }
++ vchi_service_use(instance->vchi_handle[0]);
++
++ m.type = VC_AUDIO_MSG_TYPE_CLOSE;
++
++ /* Create the message available completion */
++ init_completion(&instance->msg_avail_comp);
++
++ /* Send the message to the videocore */
++ success = vchi_msg_queue(instance->vchi_handle[0],
++ &m, sizeof m,
++ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL);
++
++ if (success != 0) {
++ LOG_ERR("%s: failed on vchi_msg_queue (status=%d)\n",
++ __func__, success);
++ ret = -1;
++ goto unlock;
++ }
++
++ ret = wait_for_completion_interruptible(&instance->msg_avail_comp);
++ if (ret) {
++ LOG_DBG("%s: failed on waiting for event (status=%d)\n",
++ __func__, success);
++ goto unlock;
++ }
++ if (instance->result != 0) {
++ LOG_ERR("%s: failed result (status=%d)\n",
++ __func__, instance->result);
++
++ ret = -1;
++ goto unlock;
++ }
++
++ ret = 0;
++
++unlock:
++ vchi_service_release(instance->vchi_handle[0]);
++ mutex_unlock(&instance->vchi_mutex);
++
++ /* Stop the audio service */
++ if (instance) {
++ vc_vchi_audio_deinit(instance);
++ alsa_stream->instance = NULL;
++ }
++ LOG_DBG(" .. OUT\n");
++ return ret;
++}
++
++int bcm2835_audio_write_worker(bcm2835_alsa_stream_t *alsa_stream,
++ uint32_t count, void *src)
++{
++ VC_AUDIO_MSG_T m;
++ AUDIO_INSTANCE_T *instance = alsa_stream->instance;
++ int32_t success;
++ int ret;
++
++ LOG_DBG(" .. IN\n");
++
++ LOG_INFO(" Writing %d bytes from %p\n", count, src);
++
++ if(mutex_lock_interruptible(&instance->vchi_mutex))
++ {
++ LOG_DBG("Interrupted whilst waiting for lock on (%d)\n",instance->num_connections);
++ return -EINTR;
++ }
++ vchi_service_use(instance->vchi_handle[0]);
++
++ if ( instance->peer_version==0 && vchi_get_peer_version(instance->vchi_handle[0], &instance->peer_version) == 0 ) {
++ LOG_DBG("%s: client version %d connected\n", __func__, instance->peer_version);
++ }
++ m.type = VC_AUDIO_MSG_TYPE_WRITE;
++ m.u.write.count = count;
++ // old version uses bulk, new version uses control
++ m.u.write.max_packet = instance->peer_version < 2 || force_bulk ? 0:4000;
++ m.u.write.callback = alsa_stream->fifo_irq_handler;
++ m.u.write.cookie = alsa_stream;
++ m.u.write.silence = src == NULL;
++
++ /* Send the message to the videocore */
++ success = vchi_msg_queue(instance->vchi_handle[0],
++ &m, sizeof m,
++ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL);
++
++ if (success != 0) {
++ LOG_ERR("%s: failed on vchi_msg_queue (status=%d)\n",
++ __func__, success);
++
++ ret = -1;
++ goto unlock;
++ }
++ if (!m.u.write.silence) {
++ if (m.u.write.max_packet == 0) {
++ /* Send the message to the videocore */
++ success = vchi_bulk_queue_transmit(instance->vchi_handle[0],
++ src, count,
++ 0 *
++ VCHI_FLAGS_BLOCK_UNTIL_QUEUED
++ +
++ 1 *
++ VCHI_FLAGS_BLOCK_UNTIL_DATA_READ,
++ NULL);
++ } else {
++ while (count > 0) {
++ int bytes = min((int)m.u.write.max_packet, (int)count);
++ success = vchi_msg_queue(instance->vchi_handle[0],
++ src, bytes,
++ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL);
++ src = (char *)src + bytes;
++ count -= bytes;
++ }
++ }
++ if (success != 0) {
++ LOG_ERR
++ ("%s: failed on vchi_bulk_queue_transmit (status=%d)\n",
++ __func__, success);
++
++ ret = -1;
++ goto unlock;
++ }
++ }
++ ret = 0;
++
++unlock:
++ vchi_service_release(instance->vchi_handle[0]);
++ mutex_unlock(&instance->vchi_mutex);
++ LOG_DBG(" .. OUT\n");
++ return ret;
++}
++
++/**
++ * Returns all buffers from arm->vc
++ */
++void bcm2835_audio_flush_buffers(bcm2835_alsa_stream_t * alsa_stream)
++{
++ LOG_DBG(" .. IN\n");
++ LOG_DBG(" .. OUT\n");
++ return;
++}
++
++/**
++ * Forces VC to flush(drop) its filled playback buffers and
++ * return them the us. (VC->ARM)
++ */
++void bcm2835_audio_flush_playback_buffers(bcm2835_alsa_stream_t * alsa_stream)
++{
++ LOG_DBG(" .. IN\n");
++ LOG_DBG(" .. OUT\n");
++}
++
++uint32_t bcm2835_audio_retrieve_buffers(bcm2835_alsa_stream_t * alsa_stream)
++{
++ uint32_t count = atomic_read(&alsa_stream->retrieved);
++ atomic_sub(count, &alsa_stream->retrieved);
++ return count;
++}
++
++module_param(force_bulk, bool, 0444);
++MODULE_PARM_DESC(force_bulk, "Force use of vchiq bulk for audio");
+diff -Nur linux-4.1.3/sound/arm/Kconfig linux-xbian-rpi/sound/arm/Kconfig
+--- linux-4.1.3/sound/arm/Kconfig 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/sound/arm/Kconfig 2015-07-28 01:20:58.465085369 +0200
+@@ -39,5 +39,13 @@
+ Say Y or M if you want to support any AC97 codec attached to
+ the PXA2xx AC97 interface.
+
++config SND_BCM2835
++ tristate "BCM2835 ALSA driver"
++ depends on (ARCH_BCM2708 || ARCH_BCM2709 || ARCH_BCM2835) \
++ && BCM2708_VCHIQ && SND
++ select SND_PCM
++ help
++ Say Y or M if you want to support BCM2835 Alsa pcm card driver
++
+ endif # SND_ARM
+
+diff -Nur linux-4.1.3/sound/arm/Makefile linux-xbian-rpi/sound/arm/Makefile
+--- linux-4.1.3/sound/arm/Makefile 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/sound/arm/Makefile 2015-07-28 01:20:58.465085369 +0200
+@@ -14,3 +14,8 @@
+
+ obj-$(CONFIG_SND_PXA2XX_AC97) += snd-pxa2xx-ac97.o
+ snd-pxa2xx-ac97-objs := pxa2xx-ac97.o
++
++obj-$(CONFIG_SND_BCM2835) += snd-bcm2835.o
++snd-bcm2835-objs := bcm2835.o bcm2835-ctl.o bcm2835-pcm.o bcm2835-vchiq.o
++
++ccflags-y += -Idrivers/misc/vc04_services -Idrivers/misc/vc04_services/interface/vcos/linuxkernel -D__VCCOREVER__=0x04000000
+diff -Nur linux-4.1.3/sound/arm/vc_vchi_audioserv_defs.h linux-xbian-rpi/sound/arm/vc_vchi_audioserv_defs.h
+--- linux-4.1.3/sound/arm/vc_vchi_audioserv_defs.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/sound/arm/vc_vchi_audioserv_defs.h 2015-07-28 01:20:58.465085369 +0200
+@@ -0,0 +1,116 @@
++/*****************************************************************************
++* Copyright 2011 Broadcom Corporation. All rights reserved.
++*
++* Unless you and Broadcom execute a separate written software license
++* agreement governing use of this software, this software is licensed to you
++* under the terms of the GNU General Public License version 2, available at
++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
++*
++* Notwithstanding the above, under no circumstances may you combine this
++* software in any way with any other Broadcom software provided under a
++* license other than the GPL, without Broadcom's express prior written
++* consent.
++*****************************************************************************/
++
++#ifndef _VC_AUDIO_DEFS_H_
++#define _VC_AUDIO_DEFS_H_
++
++#define VC_AUDIOSERV_MIN_VER 1
++#define VC_AUDIOSERV_VER 2
++
++// FourCC code used for VCHI connection
++#define VC_AUDIO_SERVER_NAME MAKE_FOURCC("AUDS")
++
++// Maximum message length
++#define VC_AUDIO_MAX_MSG_LEN (sizeof( VC_AUDIO_MSG_T ))
++
++// List of screens that are currently supported
++// All message types supported for HOST->VC direction
++typedef enum {
++ VC_AUDIO_MSG_TYPE_RESULT, // Generic result
++ VC_AUDIO_MSG_TYPE_COMPLETE, // Generic result
++ VC_AUDIO_MSG_TYPE_CONFIG, // Configure audio
++ VC_AUDIO_MSG_TYPE_CONTROL, // Configure audio
++ VC_AUDIO_MSG_TYPE_OPEN, // Configure audio
++ VC_AUDIO_MSG_TYPE_CLOSE, // Configure audio
++ VC_AUDIO_MSG_TYPE_START, // Configure audio
++ VC_AUDIO_MSG_TYPE_STOP, // Configure audio
++ VC_AUDIO_MSG_TYPE_WRITE, // Configure audio
++ VC_AUDIO_MSG_TYPE_MAX
++} VC_AUDIO_MSG_TYPE;
++
++// configure the audio
++typedef struct {
++ uint32_t channels;
++ uint32_t samplerate;
++ uint32_t bps;
++
++} VC_AUDIO_CONFIG_T;
++
++typedef struct {
++ uint32_t volume;
++ uint32_t dest;
++
++} VC_AUDIO_CONTROL_T;
++
++// audio
++typedef struct {
++ uint32_t dummy;
++
++} VC_AUDIO_OPEN_T;
++
++// audio
++typedef struct {
++ uint32_t dummy;
++
++} VC_AUDIO_CLOSE_T;
++// audio
++typedef struct {
++ uint32_t dummy;
++
++} VC_AUDIO_START_T;
++// audio
++typedef struct {
++ uint32_t draining;
++
++} VC_AUDIO_STOP_T;
++
++// configure the write audio samples
++typedef struct {
++ uint32_t count; // in bytes
++ void *callback;
++ void *cookie;
++ uint16_t silence;
++ uint16_t max_packet;
++} VC_AUDIO_WRITE_T;
++
++// Generic result for a request (VC->HOST)
++typedef struct {
++ int32_t success; // Success value
++
++} VC_AUDIO_RESULT_T;
++
++// Generic result for a request (VC->HOST)
++typedef struct {
++ int32_t count; // Success value
++ void *callback;
++ void *cookie;
++} VC_AUDIO_COMPLETE_T;
++
++// Message header for all messages in HOST->VC direction
++typedef struct {
++ int32_t type; // Message type (VC_AUDIO_MSG_TYPE)
++ union {
++ VC_AUDIO_CONFIG_T config;
++ VC_AUDIO_CONTROL_T control;
++ VC_AUDIO_OPEN_T open;
++ VC_AUDIO_CLOSE_T close;
++ VC_AUDIO_START_T start;
++ VC_AUDIO_STOP_T stop;
++ VC_AUDIO_WRITE_T write;
++ VC_AUDIO_RESULT_T result;
++ VC_AUDIO_COMPLETE_T complete;
++ } u;
++} VC_AUDIO_MSG_T;
++
++#endif // _VC_AUDIO_DEFS_H_
+diff -Nur linux-4.1.3/sound/soc/bcm/bcm2708-i2s.c linux-xbian-rpi/sound/soc/bcm/bcm2708-i2s.c
+--- linux-4.1.3/sound/soc/bcm/bcm2708-i2s.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/sound/soc/bcm/bcm2708-i2s.c 2015-07-28 01:20:58.465085369 +0200
+@@ -0,0 +1,1014 @@
++/*
++ * ALSA SoC I2S Audio Layer for Broadcom BCM2708 SoC
++ *
++ * Author: Florian Meier <florian.meier@koalo.de>
++ * Copyright 2013
++ *
++ * Based on
++ * Raspberry Pi PCM I2S ALSA Driver
++ * Copyright (c) by Phil Poole 2013
++ *
++ * ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor
++ * Vladimir Barinov, <vbarinov@embeddedalley.com>
++ * Copyright (C) 2007 MontaVista Software, Inc., <source@mvista.com>
++ *
++ * OMAP ALSA SoC DAI driver using McBSP port
++ * Copyright (C) 2008 Nokia Corporation
++ * Contact: Jarkko Nikula <jarkko.nikula@bitmer.com>
++ * Peter Ujfalusi <peter.ujfalusi@ti.com>
++ *
++ * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver
++ * Author: Timur Tabi <timur@freescale.com>
++ * Copyright 2007-2010 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * version 2 as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
++ * General Public License for more details.
++ */
++
++#include "bcm2708-i2s.h"
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/device.h>
++#include <linux/slab.h>
++#include <linux/delay.h>
++#include <linux/io.h>
++#include <linux/clk.h>
++#include <mach/gpio.h>
++
++#include <sound/core.h>
++#include <sound/pcm.h>
++#include <sound/pcm_params.h>
++#include <sound/initval.h>
++#include <sound/soc.h>
++#include <sound/dmaengine_pcm.h>
++
++#include <asm/system_info.h>
++
++/* Clock registers */
++#define BCM2708_CLK_PCMCTL_REG 0x00
++#define BCM2708_CLK_PCMDIV_REG 0x04
++
++/* Clock register settings */
++#define BCM2708_CLK_PASSWD (0x5a000000)
++#define BCM2708_CLK_PASSWD_MASK (0xff000000)
++#define BCM2708_CLK_MASH(v) ((v) << 9)
++#define BCM2708_CLK_FLIP BIT(8)
++#define BCM2708_CLK_BUSY BIT(7)
++#define BCM2708_CLK_KILL BIT(5)
++#define BCM2708_CLK_ENAB BIT(4)
++#define BCM2708_CLK_SRC(v) (v)
++
++#define BCM2708_CLK_SHIFT (12)
++#define BCM2708_CLK_DIVI(v) ((v) << BCM2708_CLK_SHIFT)
++#define BCM2708_CLK_DIVF(v) (v)
++#define BCM2708_CLK_DIVF_MASK (0xFFF)
++
++enum {
++ BCM2708_CLK_MASH_0 = 0,
++ BCM2708_CLK_MASH_1,
++ BCM2708_CLK_MASH_2,
++ BCM2708_CLK_MASH_3,
++};
++
++enum {
++ BCM2708_CLK_SRC_GND = 0,
++ BCM2708_CLK_SRC_OSC,
++ BCM2708_CLK_SRC_DBG0,
++ BCM2708_CLK_SRC_DBG1,
++ BCM2708_CLK_SRC_PLLA,
++ BCM2708_CLK_SRC_PLLC,
++ BCM2708_CLK_SRC_PLLD,
++ BCM2708_CLK_SRC_HDMI,
++};
++
++/* Most clocks are not useable (freq = 0) */
++static const unsigned int bcm2708_clk_freq[BCM2708_CLK_SRC_HDMI+1] = {
++ [BCM2708_CLK_SRC_GND] = 0,
++ [BCM2708_CLK_SRC_OSC] = 19200000,
++ [BCM2708_CLK_SRC_DBG0] = 0,
++ [BCM2708_CLK_SRC_DBG1] = 0,
++ [BCM2708_CLK_SRC_PLLA] = 0,
++ [BCM2708_CLK_SRC_PLLC] = 0,
++ [BCM2708_CLK_SRC_PLLD] = 500000000,
++ [BCM2708_CLK_SRC_HDMI] = 0,
++};
++
++/* I2S registers */
++#define BCM2708_I2S_CS_A_REG 0x00
++#define BCM2708_I2S_FIFO_A_REG 0x04
++#define BCM2708_I2S_MODE_A_REG 0x08
++#define BCM2708_I2S_RXC_A_REG 0x0c
++#define BCM2708_I2S_TXC_A_REG 0x10
++#define BCM2708_I2S_DREQ_A_REG 0x14
++#define BCM2708_I2S_INTEN_A_REG 0x18
++#define BCM2708_I2S_INTSTC_A_REG 0x1c
++#define BCM2708_I2S_GRAY_REG 0x20
++
++/* I2S register settings */
++#define BCM2708_I2S_STBY BIT(25)
++#define BCM2708_I2S_SYNC BIT(24)
++#define BCM2708_I2S_RXSEX BIT(23)
++#define BCM2708_I2S_RXF BIT(22)
++#define BCM2708_I2S_TXE BIT(21)
++#define BCM2708_I2S_RXD BIT(20)
++#define BCM2708_I2S_TXD BIT(19)
++#define BCM2708_I2S_RXR BIT(18)
++#define BCM2708_I2S_TXW BIT(17)
++#define BCM2708_I2S_CS_RXERR BIT(16)
++#define BCM2708_I2S_CS_TXERR BIT(15)
++#define BCM2708_I2S_RXSYNC BIT(14)
++#define BCM2708_I2S_TXSYNC BIT(13)
++#define BCM2708_I2S_DMAEN BIT(9)
++#define BCM2708_I2S_RXTHR(v) ((v) << 7)
++#define BCM2708_I2S_TXTHR(v) ((v) << 5)
++#define BCM2708_I2S_RXCLR BIT(4)
++#define BCM2708_I2S_TXCLR BIT(3)
++#define BCM2708_I2S_TXON BIT(2)
++#define BCM2708_I2S_RXON BIT(1)
++#define BCM2708_I2S_EN (1)
++
++#define BCM2708_I2S_CLKDIS BIT(28)
++#define BCM2708_I2S_PDMN BIT(27)
++#define BCM2708_I2S_PDME BIT(26)
++#define BCM2708_I2S_FRXP BIT(25)
++#define BCM2708_I2S_FTXP BIT(24)
++#define BCM2708_I2S_CLKM BIT(23)
++#define BCM2708_I2S_CLKI BIT(22)
++#define BCM2708_I2S_FSM BIT(21)
++#define BCM2708_I2S_FSI BIT(20)
++#define BCM2708_I2S_FLEN(v) ((v) << 10)
++#define BCM2708_I2S_FSLEN(v) (v)
++
++#define BCM2708_I2S_CHWEX BIT(15)
++#define BCM2708_I2S_CHEN BIT(14)
++#define BCM2708_I2S_CHPOS(v) ((v) << 4)
++#define BCM2708_I2S_CHWID(v) (v)
++#define BCM2708_I2S_CH1(v) ((v) << 16)
++#define BCM2708_I2S_CH2(v) (v)
++
++#define BCM2708_I2S_TX_PANIC(v) ((v) << 24)
++#define BCM2708_I2S_RX_PANIC(v) ((v) << 16)
++#define BCM2708_I2S_TX(v) ((v) << 8)
++#define BCM2708_I2S_RX(v) (v)
++
++#define BCM2708_I2S_INT_RXERR BIT(3)
++#define BCM2708_I2S_INT_TXERR BIT(2)
++#define BCM2708_I2S_INT_RXR BIT(1)
++#define BCM2708_I2S_INT_TXW BIT(0)
++
++/* I2S DMA interface */
++#define BCM2708_I2S_FIFO_PHYSICAL_ADDR 0x7E203004
++#define BCM2708_DMA_DREQ_PCM_TX 2
++#define BCM2708_DMA_DREQ_PCM_RX 3
++
++/* I2S pin configuration */
++static int bcm2708_i2s_gpio=BCM2708_I2S_GPIO_AUTO;
++
++/* General device struct */
++struct bcm2708_i2s_dev {
++ struct device *dev;
++ struct snd_dmaengine_dai_dma_data dma_data[2];
++ unsigned int fmt;
++ unsigned int bclk_ratio;
++
++ struct regmap *i2s_regmap;
++ struct regmap *clk_regmap;
++};
++
++void bcm2708_i2s_set_gpio(int gpio) {
++ bcm2708_i2s_gpio=gpio;
++}
++EXPORT_SYMBOL(bcm2708_i2s_set_gpio);
++
++
++static void bcm2708_i2s_start_clock(struct bcm2708_i2s_dev *dev)
++{
++ /* Start the clock if in master mode */
++ unsigned int master = dev->fmt & SND_SOC_DAIFMT_MASTER_MASK;
++
++ switch (master) {
++ case SND_SOC_DAIFMT_CBS_CFS:
++ case SND_SOC_DAIFMT_CBS_CFM:
++ regmap_update_bits(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG,
++ BCM2708_CLK_PASSWD_MASK | BCM2708_CLK_ENAB,
++ BCM2708_CLK_PASSWD | BCM2708_CLK_ENAB);
++ break;
++ default:
++ break;
++ }
++}
++
++static void bcm2708_i2s_stop_clock(struct bcm2708_i2s_dev *dev)
++{
++ uint32_t clkreg;
++ int timeout = 1000;
++
++ /* Stop clock */
++ regmap_update_bits(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG,
++ BCM2708_CLK_PASSWD_MASK | BCM2708_CLK_ENAB,
++ BCM2708_CLK_PASSWD);
++
++ /* Wait for the BUSY flag going down */
++ while (--timeout) {
++ regmap_read(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG, &clkreg);
++ if (!(clkreg & BCM2708_CLK_BUSY))
++ break;
++ }
++
++ if (!timeout) {
++ /* KILL the clock */
++ dev_err(dev->dev, "I2S clock didn't stop. Kill the clock!\n");
++ regmap_update_bits(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG,
++ BCM2708_CLK_KILL | BCM2708_CLK_PASSWD_MASK,
++ BCM2708_CLK_KILL | BCM2708_CLK_PASSWD);
++ }
++}
++
++static void bcm2708_i2s_clear_fifos(struct bcm2708_i2s_dev *dev,
++ bool tx, bool rx)
++{
++ int timeout = 1000;
++ uint32_t syncval;
++ uint32_t csreg;
++ uint32_t i2s_active_state;
++ uint32_t clkreg;
++ uint32_t clk_active_state;
++ uint32_t off;
++ uint32_t clr;
++
++ off = tx ? BCM2708_I2S_TXON : 0;
++ off |= rx ? BCM2708_I2S_RXON : 0;
++
++ clr = tx ? BCM2708_I2S_TXCLR : 0;
++ clr |= rx ? BCM2708_I2S_RXCLR : 0;
++
++ /* Backup the current state */
++ regmap_read(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, &csreg);
++ i2s_active_state = csreg & (BCM2708_I2S_RXON | BCM2708_I2S_TXON);
++
++ regmap_read(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG, &clkreg);
++ clk_active_state = clkreg & BCM2708_CLK_ENAB;
++
++ /* Start clock if not running */
++ if (!clk_active_state) {
++ regmap_update_bits(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG,
++ BCM2708_CLK_PASSWD_MASK | BCM2708_CLK_ENAB,
++ BCM2708_CLK_PASSWD | BCM2708_CLK_ENAB);
++ }
++
++ /* Stop I2S module */
++ regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, off, 0);
++
++ /*
++ * Clear the FIFOs
++ * Requires at least 2 PCM clock cycles to take effect
++ */
++ regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, clr, clr);
++
++ /* Wait for 2 PCM clock cycles */
++
++ /*
++ * Toggle the SYNC flag. After 2 PCM clock cycles it can be read back
++ * FIXME: This does not seem to work for slave mode!
++ */
++ regmap_read(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, &syncval);
++ syncval &= BCM2708_I2S_SYNC;
++
++ regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG,
++ BCM2708_I2S_SYNC, ~syncval);
++
++ /* Wait for the SYNC flag changing it's state */
++ while (--timeout) {
++ regmap_read(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, &csreg);
++ if ((csreg & BCM2708_I2S_SYNC) != syncval)
++ break;
++ }
++
++ if (!timeout)
++ dev_err(dev->dev, "I2S SYNC error!\n");
++
++ /* Stop clock if it was not running before */
++ if (!clk_active_state)
++ bcm2708_i2s_stop_clock(dev);
++
++ /* Restore I2S state */
++ regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG,
++ BCM2708_I2S_RXON | BCM2708_I2S_TXON, i2s_active_state);
++}
++
++static int bcm2708_i2s_set_dai_fmt(struct snd_soc_dai *dai,
++ unsigned int fmt)
++{
++ struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
++ dev->fmt = fmt;
++ return 0;
++}
++
++static int bcm2708_i2s_set_dai_bclk_ratio(struct snd_soc_dai *dai,
++ unsigned int ratio)
++{
++ struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
++ dev->bclk_ratio = ratio;
++ return 0;
++}
++
++
++static int bcm2708_i2s_set_function(unsigned offset, int function)
++{
++ #define GPIOFSEL(x) (0x00+(x)*4)
++ void __iomem *gpio = __io_address(GPIO_BASE);
++ unsigned alt = function <= 3 ? function + 4: function == 4 ? 3 : 2;
++ unsigned gpiodir;
++ unsigned gpio_bank = offset / 10;
++ unsigned gpio_field_offset = (offset - 10 * gpio_bank) * 3;
++
++ if (offset >= BCM2708_NR_GPIOS)
++ return -EINVAL;
++
++ gpiodir = readl(gpio + GPIOFSEL(gpio_bank));
++ gpiodir &= ~(7 << gpio_field_offset);
++ gpiodir |= alt << gpio_field_offset;
++ writel(gpiodir, gpio + GPIOFSEL(gpio_bank));
++ return 0;
++}
++
++static void bcm2708_i2s_setup_gpio(void)
++{
++ /*
++ * This is the common way to handle the GPIO pins for
++ * the Raspberry Pi.
++ * TODO Better way would be to handle
++ * this in the device tree!
++ */
++ int pin,pinconfig,startpin,alt;
++
++ /* SPI is on different GPIOs on different boards */
++ /* for Raspberry Pi B+, this is pin GPIO18-21, for original on 28-31 */
++ if (bcm2708_i2s_gpio==BCM2708_I2S_GPIO_AUTO) {
++ if ((system_rev & 0xffffff) >= 0x10) {
++ /* Model B+ */
++ pinconfig=BCM2708_I2S_GPIO_PIN18;
++ } else {
++ /* original */
++ pinconfig=BCM2708_I2S_GPIO_PIN28;
++ }
++ } else {
++ pinconfig=bcm2708_i2s_gpio;
++ }
++
++ if (pinconfig==BCM2708_I2S_GPIO_PIN18) {
++ startpin=18;
++ alt=BCM2708_I2S_GPIO_PIN18_ALT;
++ } else if (pinconfig==BCM2708_I2S_GPIO_PIN28) {
++ startpin=28;
++ alt=BCM2708_I2S_GPIO_PIN28_ALT;
++ } else {
++ printk(KERN_INFO "Can't configure I2S GPIOs, unknown pin mode for I2S: %i\n",pinconfig);
++ return;
++ }
++
++ /* configure I2S pins to correct ALT mode */
++ for (pin = startpin; pin <= startpin+3; pin++) {
++ bcm2708_i2s_set_function(pin, alt);
++ }
++}
++
++static int bcm2708_i2s_hw_params(struct snd_pcm_substream *substream,
++ struct snd_pcm_hw_params *params,
++ struct snd_soc_dai *dai)
++{
++ struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
++
++ unsigned int sampling_rate = params_rate(params);
++ unsigned int data_length, data_delay, bclk_ratio;
++ unsigned int ch1pos, ch2pos, mode, format;
++ unsigned int mash = BCM2708_CLK_MASH_1;
++ unsigned int divi, divf, target_frequency;
++ int clk_src = -1;
++ unsigned int master = dev->fmt & SND_SOC_DAIFMT_MASTER_MASK;
++ bool bit_master = (master == SND_SOC_DAIFMT_CBS_CFS
++ || master == SND_SOC_DAIFMT_CBS_CFM);
++
++ bool frame_master = (master == SND_SOC_DAIFMT_CBS_CFS
++ || master == SND_SOC_DAIFMT_CBM_CFS);
++ uint32_t csreg;
++
++ /*
++ * If a stream is already enabled,
++ * the registers are already set properly.
++ */
++ regmap_read(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, &csreg);
++
++ if (csreg & (BCM2708_I2S_TXON | BCM2708_I2S_RXON))
++ return 0;
++
++ if (!dev->dev->of_node)
++ bcm2708_i2s_setup_gpio();
++
++ /*
++ * Adjust the data length according to the format.
++ * We prefill the half frame length with an integer
++ * divider of 2400 as explained at the clock settings.
++ * Maybe it is overwritten there, if the Integer mode
++ * does not apply.
++ */
++ switch (params_format(params)) {
++ case SNDRV_PCM_FORMAT_S16_LE:
++ data_length = 16;
++ bclk_ratio = 50;
++ break;
++ case SNDRV_PCM_FORMAT_S24_LE:
++ data_length = 24;
++ bclk_ratio = 50;
++ break;
++ case SNDRV_PCM_FORMAT_S32_LE:
++ data_length = 32;
++ bclk_ratio = 100;
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ /* If bclk_ratio already set, use that one. */
++ if (dev->bclk_ratio)
++ bclk_ratio = dev->bclk_ratio;
++
++ /*
++ * Clock Settings
++ *
++ * The target frequency of the bit clock is
++ * sampling rate * frame length
++ *
++ * Integer mode:
++ * Sampling rates that are multiples of 8000 kHz
++ * can be driven by the oscillator of 19.2 MHz
++ * with an integer divider as long as the frame length
++ * is an integer divider of 19200000/8000=2400 as set up above.
++ * This is no longer possible if the sampling rate
++ * is too high (e.g. 192 kHz), because the oscillator is too slow.
++ *
++ * MASH mode:
++ * For all other sampling rates, it is not possible to
++ * have an integer divider. Approximate the clock
++ * with the MASH module that induces a slight frequency
++ * variance. To minimize that it is best to have the fastest
++ * clock here. That is PLLD with 500 MHz.
++ */
++ target_frequency = sampling_rate * bclk_ratio;
++ clk_src = BCM2708_CLK_SRC_OSC;
++ mash = BCM2708_CLK_MASH_0;
++
++ if (bcm2708_clk_freq[clk_src] % target_frequency == 0
++ && bit_master && frame_master) {
++ divi = bcm2708_clk_freq[clk_src] / target_frequency;
++ divf = 0;
++ } else {
++ uint64_t dividend;
++
++ if (!dev->bclk_ratio) {
++ /*
++ * Overwrite bclk_ratio, because the
++ * above trick is not needed or can
++ * not be used.
++ */
++ bclk_ratio = 2 * data_length;
++ }
++
++ target_frequency = sampling_rate * bclk_ratio;
++
++ clk_src = BCM2708_CLK_SRC_PLLD;
++ mash = BCM2708_CLK_MASH_1;
++
++ dividend = bcm2708_clk_freq[clk_src];
++ dividend <<= BCM2708_CLK_SHIFT;
++ do_div(dividend, target_frequency);
++ divi = dividend >> BCM2708_CLK_SHIFT;
++ divf = dividend & BCM2708_CLK_DIVF_MASK;
++ }
++
++ /* Clock should only be set up here if CPU is clock master */
++ if (((dev->fmt & SND_SOC_DAIFMT_MASTER_MASK) == SND_SOC_DAIFMT_CBS_CFS) ||
++ ((dev->fmt & SND_SOC_DAIFMT_MASTER_MASK) == SND_SOC_DAIFMT_CBS_CFM)) {
++ /* Set clock divider */
++ regmap_write(dev->clk_regmap, BCM2708_CLK_PCMDIV_REG, BCM2708_CLK_PASSWD
++ | BCM2708_CLK_DIVI(divi)
++ | BCM2708_CLK_DIVF(divf));
++
++ /* Setup clock, but don't start it yet */
++ regmap_write(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG, BCM2708_CLK_PASSWD
++ | BCM2708_CLK_MASH(mash)
++ | BCM2708_CLK_SRC(clk_src));
++ }
++
++ /* Setup the frame format */
++ format = BCM2708_I2S_CHEN;
++
++ if (data_length >= 24)
++ format |= BCM2708_I2S_CHWEX;
++
++ format |= BCM2708_I2S_CHWID((data_length-8)&0xf);
++
++ switch (dev->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
++ case SND_SOC_DAIFMT_I2S:
++ data_delay = 1;
++ break;
++ default:
++ /*
++ * TODO
++ * Others are possible but are not implemented at the moment.
++ */
++ dev_err(dev->dev, "%s:bad format\n", __func__);
++ return -EINVAL;
++ }
++
++ ch1pos = data_delay;
++ ch2pos = bclk_ratio / 2 + data_delay;
++
++ switch (params_channels(params)) {
++ case 2:
++ format = BCM2708_I2S_CH1(format) | BCM2708_I2S_CH2(format);
++ format |= BCM2708_I2S_CH1(BCM2708_I2S_CHPOS(ch1pos));
++ format |= BCM2708_I2S_CH2(BCM2708_I2S_CHPOS(ch2pos));
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ /*
++ * Set format for both streams.
++ * We cannot set another frame length
++ * (and therefore word length) anyway,
++ * so the format will be the same.
++ */
++ regmap_write(dev->i2s_regmap, BCM2708_I2S_RXC_A_REG, format);
++ regmap_write(dev->i2s_regmap, BCM2708_I2S_TXC_A_REG, format);
++
++ /* Setup the I2S mode */
++ mode = 0;
++
++ if (data_length <= 16) {
++ /*
++ * Use frame packed mode (2 channels per 32 bit word)
++ * We cannot set another frame length in the second stream
++ * (and therefore word length) anyway,
++ * so the format will be the same.
++ */
++ mode |= BCM2708_I2S_FTXP | BCM2708_I2S_FRXP;
++ }
++
++ mode |= BCM2708_I2S_FLEN(bclk_ratio - 1);
++ mode |= BCM2708_I2S_FSLEN(bclk_ratio / 2);
++
++ /* Master or slave? */
++ switch (dev->fmt & SND_SOC_DAIFMT_MASTER_MASK) {
++ case SND_SOC_DAIFMT_CBS_CFS:
++ /* CPU is master */
++ break;
++ case SND_SOC_DAIFMT_CBM_CFS:
++ /*
++ * CODEC is bit clock master
++ * CPU is frame master
++ */
++ mode |= BCM2708_I2S_CLKM;
++ break;
++ case SND_SOC_DAIFMT_CBS_CFM:
++ /*
++ * CODEC is frame master
++ * CPU is bit clock master
++ */
++ mode |= BCM2708_I2S_FSM;
++ break;
++ case SND_SOC_DAIFMT_CBM_CFM:
++ /* CODEC is master */
++ mode |= BCM2708_I2S_CLKM;
++ mode |= BCM2708_I2S_FSM;
++ break;
++ default:
++ dev_err(dev->dev, "%s:bad master\n", __func__);
++ return -EINVAL;
++ }
++
++ /*
++ * Invert clocks?
++ *
++ * The BCM approach seems to be inverted to the classical I2S approach.
++ */
++ switch (dev->fmt & SND_SOC_DAIFMT_INV_MASK) {
++ case SND_SOC_DAIFMT_NB_NF:
++ /* None. Therefore, both for BCM */
++ mode |= BCM2708_I2S_CLKI;
++ mode |= BCM2708_I2S_FSI;
++ break;
++ case SND_SOC_DAIFMT_IB_IF:
++ /* Both. Therefore, none for BCM */
++ break;
++ case SND_SOC_DAIFMT_NB_IF:
++ /*
++ * Invert only frame sync. Therefore,
++ * invert only bit clock for BCM
++ */
++ mode |= BCM2708_I2S_CLKI;
++ break;
++ case SND_SOC_DAIFMT_IB_NF:
++ /*
++ * Invert only bit clock. Therefore,
++ * invert only frame sync for BCM
++ */
++ mode |= BCM2708_I2S_FSI;
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ regmap_write(dev->i2s_regmap, BCM2708_I2S_MODE_A_REG, mode);
++
++ /* Setup the DMA parameters */
++ regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG,
++ BCM2708_I2S_RXTHR(1)
++ | BCM2708_I2S_TXTHR(1)
++ | BCM2708_I2S_DMAEN, 0xffffffff);
++
++ regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_DREQ_A_REG,
++ BCM2708_I2S_TX_PANIC(0x10)
++ | BCM2708_I2S_RX_PANIC(0x30)
++ | BCM2708_I2S_TX(0x30)
++ | BCM2708_I2S_RX(0x20), 0xffffffff);
++
++ /* Clear FIFOs */
++ bcm2708_i2s_clear_fifos(dev, true, true);
++
++ return 0;
++}
++
++static int bcm2708_i2s_prepare(struct snd_pcm_substream *substream,
++ struct snd_soc_dai *dai)
++{
++ struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
++ uint32_t cs_reg;
++
++ bcm2708_i2s_start_clock(dev);
++
++ /*
++ * Clear both FIFOs if the one that should be started
++ * is not empty at the moment. This should only happen
++ * after overrun. Otherwise, hw_params would have cleared
++ * the FIFO.
++ */
++ regmap_read(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, &cs_reg);
++
++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK
++ && !(cs_reg & BCM2708_I2S_TXE))
++ bcm2708_i2s_clear_fifos(dev, true, false);
++ else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE
++ && (cs_reg & BCM2708_I2S_RXD))
++ bcm2708_i2s_clear_fifos(dev, false, true);
++
++ return 0;
++}
++
++static void bcm2708_i2s_stop(struct bcm2708_i2s_dev *dev,
++ struct snd_pcm_substream *substream,
++ struct snd_soc_dai *dai)
++{
++ uint32_t mask;
++
++ if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
++ mask = BCM2708_I2S_RXON;
++ else
++ mask = BCM2708_I2S_TXON;
++
++ regmap_update_bits(dev->i2s_regmap,
++ BCM2708_I2S_CS_A_REG, mask, 0);
++
++ /* Stop also the clock when not SND_SOC_DAIFMT_CONT */
++ if (!dai->active && !(dev->fmt & SND_SOC_DAIFMT_CONT))
++ bcm2708_i2s_stop_clock(dev);
++}
++
++static int bcm2708_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
++ struct snd_soc_dai *dai)
++{
++ struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
++ uint32_t mask;
++
++ switch (cmd) {
++ case SNDRV_PCM_TRIGGER_START:
++ case SNDRV_PCM_TRIGGER_RESUME:
++ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
++ bcm2708_i2s_start_clock(dev);
++
++ if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
++ mask = BCM2708_I2S_RXON;
++ else
++ mask = BCM2708_I2S_TXON;
++
++ regmap_update_bits(dev->i2s_regmap,
++ BCM2708_I2S_CS_A_REG, mask, mask);
++ break;
++
++ case SNDRV_PCM_TRIGGER_STOP:
++ case SNDRV_PCM_TRIGGER_SUSPEND:
++ case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
++ bcm2708_i2s_stop(dev, substream, dai);
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++static int bcm2708_i2s_startup(struct snd_pcm_substream *substream,
++ struct snd_soc_dai *dai)
++{
++ struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
++
++ if (dai->active)
++ return 0;
++
++ /* Should this still be running stop it */
++ bcm2708_i2s_stop_clock(dev);
++
++ /* Enable PCM block */
++ regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG,
++ BCM2708_I2S_EN, BCM2708_I2S_EN);
++
++ /*
++ * Disable STBY.
++ * Requires at least 4 PCM clock cycles to take effect.
++ */
++ regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG,
++ BCM2708_I2S_STBY, BCM2708_I2S_STBY);
++
++ return 0;
++}
++
++static void bcm2708_i2s_shutdown(struct snd_pcm_substream *substream,
++ struct snd_soc_dai *dai)
++{
++ struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
++
++ bcm2708_i2s_stop(dev, substream, dai);
++
++ /* If both streams are stopped, disable module and clock */
++ if (dai->active)
++ return;
++
++ /* Disable the module */
++ regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG,
++ BCM2708_I2S_EN, 0);
++
++ /*
++ * Stopping clock is necessary, because stop does
++ * not stop the clock when SND_SOC_DAIFMT_CONT
++ */
++ bcm2708_i2s_stop_clock(dev);
++}
++
++static const struct snd_soc_dai_ops bcm2708_i2s_dai_ops = {
++ .startup = bcm2708_i2s_startup,
++ .shutdown = bcm2708_i2s_shutdown,
++ .prepare = bcm2708_i2s_prepare,
++ .trigger = bcm2708_i2s_trigger,
++ .hw_params = bcm2708_i2s_hw_params,
++ .set_fmt = bcm2708_i2s_set_dai_fmt,
++ .set_bclk_ratio = bcm2708_i2s_set_dai_bclk_ratio
++};
++
++static int bcm2708_i2s_dai_probe(struct snd_soc_dai *dai)
++{
++ struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
++
++ dai->playback_dma_data = &dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
++ dai->capture_dma_data = &dev->dma_data[SNDRV_PCM_STREAM_CAPTURE];
++
++ return 0;
++}
++
++static struct snd_soc_dai_driver bcm2708_i2s_dai = {
++ .name = "bcm2708-i2s",
++ .probe = bcm2708_i2s_dai_probe,
++ .playback = {
++ .channels_min = 2,
++ .channels_max = 2,
++ .rates = SNDRV_PCM_RATE_8000_192000,
++ .formats = SNDRV_PCM_FMTBIT_S16_LE
++ | SNDRV_PCM_FMTBIT_S24_LE
++ | SNDRV_PCM_FMTBIT_S32_LE
++ },
++ .capture = {
++ .channels_min = 2,
++ .channels_max = 2,
++ .rates = SNDRV_PCM_RATE_8000_192000,
++ .formats = SNDRV_PCM_FMTBIT_S16_LE
++ | SNDRV_PCM_FMTBIT_S24_LE
++ | SNDRV_PCM_FMTBIT_S32_LE
++ },
++ .ops = &bcm2708_i2s_dai_ops,
++ .symmetric_rates = 1
++};
++
++static bool bcm2708_i2s_volatile_reg(struct device *dev, unsigned int reg)
++{
++ switch (reg) {
++ case BCM2708_I2S_CS_A_REG:
++ case BCM2708_I2S_FIFO_A_REG:
++ case BCM2708_I2S_INTSTC_A_REG:
++ case BCM2708_I2S_GRAY_REG:
++ return true;
++ default:
++ return false;
++ };
++}
++
++static bool bcm2708_i2s_precious_reg(struct device *dev, unsigned int reg)
++{
++ switch (reg) {
++ case BCM2708_I2S_FIFO_A_REG:
++ return true;
++ default:
++ return false;
++ };
++}
++
++static bool bcm2708_clk_volatile_reg(struct device *dev, unsigned int reg)
++{
++ switch (reg) {
++ case BCM2708_CLK_PCMCTL_REG:
++ return true;
++ default:
++ return false;
++ };
++}
++
++static const struct regmap_config bcm2708_regmap_config[] = {
++ {
++ .reg_bits = 32,
++ .reg_stride = 4,
++ .val_bits = 32,
++ .max_register = BCM2708_I2S_GRAY_REG,
++ .precious_reg = bcm2708_i2s_precious_reg,
++ .volatile_reg = bcm2708_i2s_volatile_reg,
++ .cache_type = REGCACHE_RBTREE,
++ .name = "i2s",
++ },
++ {
++ .reg_bits = 32,
++ .reg_stride = 4,
++ .val_bits = 32,
++ .max_register = BCM2708_CLK_PCMDIV_REG,
++ .volatile_reg = bcm2708_clk_volatile_reg,
++ .cache_type = REGCACHE_RBTREE,
++ .name = "clk",
++ },
++};
++
++static const struct snd_soc_component_driver bcm2708_i2s_component = {
++ .name = "bcm2708-i2s-comp",
++};
++
++static struct snd_pcm_hardware bcm2708_pcm_hardware = {
++ .info = SNDRV_PCM_INFO_INTERLEAVED |
++ SNDRV_PCM_INFO_JOINT_DUPLEX,
++ .formats = SNDRV_PCM_FMTBIT_S16_LE |
++ SNDRV_PCM_FMTBIT_S24_LE |
++ SNDRV_PCM_FMTBIT_S32_LE,
++ .period_bytes_min = 32,
++ .period_bytes_max = 64 * PAGE_SIZE,
++ .periods_min = 2,
++ .periods_max = 255,
++ .buffer_bytes_max = 128 * PAGE_SIZE,
++};
++
++static const struct snd_dmaengine_pcm_config bcm2708_dmaengine_pcm_config = {
++ .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
++ .pcm_hardware = &bcm2708_pcm_hardware,
++ .prealloc_buffer_size = 256 * PAGE_SIZE,
++};
++
++
++static int bcm2708_i2s_probe(struct platform_device *pdev)
++{
++ struct bcm2708_i2s_dev *dev;
++ int i;
++ int ret;
++ struct regmap *regmap[2];
++ struct resource *mem[2];
++
++ if (of_property_read_bool(pdev->dev.of_node, "brcm,enable-mmap"))
++ bcm2708_pcm_hardware.info |=
++ SNDRV_PCM_INFO_MMAP |
++ SNDRV_PCM_INFO_MMAP_VALID;
++
++ /* Request both ioareas */
++ for (i = 0; i <= 1; i++) {
++ void __iomem *base;
++
++ mem[i] = platform_get_resource(pdev, IORESOURCE_MEM, i);
++ base = devm_ioremap_resource(&pdev->dev, mem[i]);
++ if (IS_ERR(base))
++ return PTR_ERR(base);
++
++ regmap[i] = devm_regmap_init_mmio(&pdev->dev, base,
++ &bcm2708_regmap_config[i]);
++ if (IS_ERR(regmap[i])) {
++ dev_err(&pdev->dev, "I2S probe: regmap init failed\n");
++ return PTR_ERR(regmap[i]);
++ }
++ }
++
++ dev = devm_kzalloc(&pdev->dev, sizeof(*dev),
++ GFP_KERNEL);
++ if (IS_ERR(dev))
++ return PTR_ERR(dev);
++
++ dev->i2s_regmap = regmap[0];
++ dev->clk_regmap = regmap[1];
++
++ /* Set the DMA address */
++ dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].addr =
++ (dma_addr_t)BCM2708_I2S_FIFO_PHYSICAL_ADDR;
++
++ dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].addr =
++ (dma_addr_t)BCM2708_I2S_FIFO_PHYSICAL_ADDR;
++
++ /* Set the DREQ */
++ dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].slave_id =
++ BCM2708_DMA_DREQ_PCM_TX;
++ dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].slave_id =
++ BCM2708_DMA_DREQ_PCM_RX;
++
++ /* Set the bus width */
++ dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].addr_width =
++ DMA_SLAVE_BUSWIDTH_4_BYTES;
++ dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].addr_width =
++ DMA_SLAVE_BUSWIDTH_4_BYTES;
++
++ /* Set burst */
++ dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].maxburst = 2;
++ dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].maxburst = 2;
++
++ /* BCLK ratio - use default */
++ dev->bclk_ratio = 0;
++
++ /* Store the pdev */
++ dev->dev = &pdev->dev;
++ dev_set_drvdata(&pdev->dev, dev);
++
++ ret = snd_soc_register_component(&pdev->dev,
++ &bcm2708_i2s_component, &bcm2708_i2s_dai, 1);
++
++ if (ret) {
++ dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
++ ret = -ENOMEM;
++ return ret;
++ }
++
++ ret = snd_dmaengine_pcm_register(&pdev->dev,
++ &bcm2708_dmaengine_pcm_config,
++ SND_DMAENGINE_PCM_FLAG_COMPAT);
++ if (ret) {
++ dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
++ snd_soc_unregister_component(&pdev->dev);
++ return ret;
++ }
++
++ return 0;
++}
++
++static int bcm2708_i2s_remove(struct platform_device *pdev)
++{
++ snd_dmaengine_pcm_unregister(&pdev->dev);
++ snd_soc_unregister_component(&pdev->dev);
++ return 0;
++}
++
++static const struct of_device_id bcm2708_i2s_of_match[] = {
++ { .compatible = "brcm,bcm2708-i2s", },
++ {},
++};
++MODULE_DEVICE_TABLE(of, bcm2708_i2s_of_match);
++
++static struct platform_driver bcm2708_i2s_driver = {
++ .probe = bcm2708_i2s_probe,
++ .remove = bcm2708_i2s_remove,
++ .driver = {
++ .name = "bcm2708-i2s",
++ .owner = THIS_MODULE,
++ .of_match_table = bcm2708_i2s_of_match,
++ },
++};
++
++module_platform_driver(bcm2708_i2s_driver);
++
++MODULE_ALIAS("platform:bcm2708-i2s");
++MODULE_DESCRIPTION("BCM2708 I2S interface");
++MODULE_AUTHOR("Florian Meier <florian.meier@koalo.de>");
++MODULE_LICENSE("GPL v2");
+diff -Nur linux-4.1.3/sound/soc/bcm/bcm2708-i2s.h linux-xbian-rpi/sound/soc/bcm/bcm2708-i2s.h
+--- linux-4.1.3/sound/soc/bcm/bcm2708-i2s.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/sound/soc/bcm/bcm2708-i2s.h 2015-07-28 01:20:58.465085369 +0200
+@@ -0,0 +1,35 @@
++/*
++ * I2S configuration for sound cards.
++ *
++ * Copyright (c) 2014 Daniel Matuschek <daniel@hifiberry.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++
++#ifndef BCM2708_I2S_H
++#define BCM2708_I2S_H
++
++/* I2S pin assignment */
++#define BCM2708_I2S_GPIO_AUTO 0
++#define BCM2708_I2S_GPIO_PIN18 1
++#define BCM2708_I2S_GPIO_PIN28 2
++
++/* Alt mode to enable I2S */
++#define BCM2708_I2S_GPIO_PIN18_ALT 0
++#define BCM2708_I2S_GPIO_PIN28_ALT 2
++
++extern void bcm2708_i2s_set_gpio(int gpio);
++
++#endif
+diff -Nur linux-4.1.3/sound/soc/bcm/bcm2835-i2s.c linux-xbian-rpi/sound/soc/bcm/bcm2835-i2s.c
+--- linux-4.1.3/sound/soc/bcm/bcm2835-i2s.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/sound/soc/bcm/bcm2835-i2s.c 2015-07-28 01:20:58.465085369 +0200
+@@ -861,6 +861,7 @@
+ { .compatible = "brcm,bcm2835-i2s", },
+ {},
+ };
++MODULE_DEVICE_TABLE(of, bcm2835_i2s_of_match);
+
+ static struct platform_driver bcm2835_i2s_driver = {
+ .probe = bcm2835_i2s_probe,
+diff -Nur linux-4.1.3/sound/soc/bcm/hifiberry_amp.c linux-xbian-rpi/sound/soc/bcm/hifiberry_amp.c
+--- linux-4.1.3/sound/soc/bcm/hifiberry_amp.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/sound/soc/bcm/hifiberry_amp.c 2015-07-28 01:20:58.465085369 +0200
+@@ -0,0 +1,127 @@
++/*
++ * ASoC Driver for HifiBerry AMP
++ *
++ * Author: Sebastian Eickhoff <basti.eickhoff@googlemail.com>
++ * Copyright 2014
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * version 2 as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
++ * General Public License for more details.
++ */
++
++#include <linux/module.h>
++#include <linux/platform_device.h>
++
++#include <sound/core.h>
++#include <sound/pcm.h>
++#include <sound/pcm_params.h>
++#include <sound/soc.h>
++#include <sound/jack.h>
++
++static int snd_rpi_hifiberry_amp_init(struct snd_soc_pcm_runtime *rtd)
++{
++ // ToDo: init of the dsp-registers.
++ return 0;
++}
++
++static int snd_rpi_hifiberry_amp_hw_params( struct snd_pcm_substream *substream,
++ struct snd_pcm_hw_params *params )
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
++
++ return snd_soc_dai_set_bclk_ratio(cpu_dai, 64);
++}
++
++static struct snd_soc_ops snd_rpi_hifiberry_amp_ops = {
++ .hw_params = snd_rpi_hifiberry_amp_hw_params,
++};
++
++static struct snd_soc_dai_link snd_rpi_hifiberry_amp_dai[] = {
++ {
++ .name = "HifiBerry AMP",
++ .stream_name = "HifiBerry AMP HiFi",
++ .cpu_dai_name = "bcm2708-i2s.0",
++ .codec_dai_name = "tas5713-hifi",
++ .platform_name = "bcm2708-i2s.0",
++ .codec_name = "tas5713.1-001b",
++ .dai_fmt = SND_SOC_DAIFMT_I2S |
++ SND_SOC_DAIFMT_NB_NF |
++ SND_SOC_DAIFMT_CBS_CFS,
++ .ops = &snd_rpi_hifiberry_amp_ops,
++ .init = snd_rpi_hifiberry_amp_init,
++ },
++};
++
++
++static struct snd_soc_card snd_rpi_hifiberry_amp = {
++ .name = "snd_rpi_hifiberry_amp",
++ .dai_link = snd_rpi_hifiberry_amp_dai,
++ .num_links = ARRAY_SIZE(snd_rpi_hifiberry_amp_dai),
++};
++
++static const struct of_device_id snd_rpi_hifiberry_amp_of_match[] = {
++ { .compatible = "hifiberry,hifiberry-amp", },
++ {},
++};
++MODULE_DEVICE_TABLE(of, snd_rpi_hifiberry_amp_of_match);
++
++
++static int snd_rpi_hifiberry_amp_probe(struct platform_device *pdev)
++{
++ int ret = 0;
++
++ snd_rpi_hifiberry_amp.dev = &pdev->dev;
++
++ if (pdev->dev.of_node) {
++ struct device_node *i2s_node;
++ struct snd_soc_dai_link *dai = &snd_rpi_hifiberry_amp_dai[0];
++ i2s_node = of_parse_phandle(pdev->dev.of_node,
++ "i2s-controller", 0);
++
++ if (i2s_node) {
++ dai->cpu_dai_name = NULL;
++ dai->cpu_of_node = i2s_node;
++ dai->platform_name = NULL;
++ dai->platform_of_node = i2s_node;
++ }
++ }
++
++ ret = snd_soc_register_card(&snd_rpi_hifiberry_amp);
++
++ if (ret != 0) {
++ dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n", ret);
++ }
++
++ return ret;
++}
++
++
++static int snd_rpi_hifiberry_amp_remove(struct platform_device *pdev)
++{
++ return snd_soc_unregister_card(&snd_rpi_hifiberry_amp);
++}
++
++
++static struct platform_driver snd_rpi_hifiberry_amp_driver = {
++ .driver = {
++ .name = "snd-hifiberry-amp",
++ .owner = THIS_MODULE,
++ .of_match_table = snd_rpi_hifiberry_amp_of_match,
++ },
++ .probe = snd_rpi_hifiberry_amp_probe,
++ .remove = snd_rpi_hifiberry_amp_remove,
++};
++
++
++module_platform_driver(snd_rpi_hifiberry_amp_driver);
++
++
++MODULE_AUTHOR("Sebastian Eickhoff <basti.eickhoff@googlemail.com>");
++MODULE_DESCRIPTION("ASoC driver for HiFiBerry-AMP");
++MODULE_LICENSE("GPL v2");
+diff -Nur linux-4.1.3/sound/soc/bcm/hifiberry_dac.c linux-xbian-rpi/sound/soc/bcm/hifiberry_dac.c
+--- linux-4.1.3/sound/soc/bcm/hifiberry_dac.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/sound/soc/bcm/hifiberry_dac.c 2015-07-28 01:20:58.465085369 +0200
+@@ -0,0 +1,122 @@
++/*
++ * ASoC Driver for HifiBerry DAC
++ *
++ * Author: Florian Meier <florian.meier@koalo.de>
++ * Copyright 2013
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * version 2 as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
++ * General Public License for more details.
++ */
++
++#include <linux/module.h>
++#include <linux/platform_device.h>
++
++#include <sound/core.h>
++#include <sound/pcm.h>
++#include <sound/pcm_params.h>
++#include <sound/soc.h>
++#include <sound/jack.h>
++
++static int snd_rpi_hifiberry_dac_init(struct snd_soc_pcm_runtime *rtd)
++{
++ return 0;
++}
++
++static int snd_rpi_hifiberry_dac_hw_params(struct snd_pcm_substream *substream,
++ struct snd_pcm_hw_params *params)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
++
++ unsigned int sample_bits =
++ snd_pcm_format_physical_width(params_format(params));
++
++ return snd_soc_dai_set_bclk_ratio(cpu_dai, sample_bits * 2);
++}
++
++/* machine stream operations */
++static struct snd_soc_ops snd_rpi_hifiberry_dac_ops = {
++ .hw_params = snd_rpi_hifiberry_dac_hw_params,
++};
++
++static struct snd_soc_dai_link snd_rpi_hifiberry_dac_dai[] = {
++{
++ .name = "HifiBerry DAC",
++ .stream_name = "HifiBerry DAC HiFi",
++ .cpu_dai_name = "bcm2708-i2s.0",
++ .codec_dai_name = "pcm5102a-hifi",
++ .platform_name = "bcm2708-i2s.0",
++ .codec_name = "pcm5102a-codec",
++ .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
++ SND_SOC_DAIFMT_CBS_CFS,
++ .ops = &snd_rpi_hifiberry_dac_ops,
++ .init = snd_rpi_hifiberry_dac_init,
++},
++};
++
++/* audio machine driver */
++static struct snd_soc_card snd_rpi_hifiberry_dac = {
++ .name = "snd_rpi_hifiberry_dac",
++ .dai_link = snd_rpi_hifiberry_dac_dai,
++ .num_links = ARRAY_SIZE(snd_rpi_hifiberry_dac_dai),
++};
++
++static int snd_rpi_hifiberry_dac_probe(struct platform_device *pdev)
++{
++ int ret = 0;
++
++ snd_rpi_hifiberry_dac.dev = &pdev->dev;
++
++ if (pdev->dev.of_node) {
++ struct device_node *i2s_node;
++ struct snd_soc_dai_link *dai = &snd_rpi_hifiberry_dac_dai[0];
++ i2s_node = of_parse_phandle(pdev->dev.of_node,
++ "i2s-controller", 0);
++
++ if (i2s_node) {
++ dai->cpu_dai_name = NULL;
++ dai->cpu_of_node = i2s_node;
++ dai->platform_name = NULL;
++ dai->platform_of_node = i2s_node;
++ }
++ }
++
++ ret = snd_soc_register_card(&snd_rpi_hifiberry_dac);
++ if (ret)
++ dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n", ret);
++
++ return ret;
++}
++
++static int snd_rpi_hifiberry_dac_remove(struct platform_device *pdev)
++{
++ return snd_soc_unregister_card(&snd_rpi_hifiberry_dac);
++}
++
++static const struct of_device_id snd_rpi_hifiberry_dac_of_match[] = {
++ { .compatible = "hifiberry,hifiberry-dac", },
++ {},
++};
++MODULE_DEVICE_TABLE(of, snd_rpi_hifiberry_dac_of_match);
++
++static struct platform_driver snd_rpi_hifiberry_dac_driver = {
++ .driver = {
++ .name = "snd-hifiberry-dac",
++ .owner = THIS_MODULE,
++ .of_match_table = snd_rpi_hifiberry_dac_of_match,
++ },
++ .probe = snd_rpi_hifiberry_dac_probe,
++ .remove = snd_rpi_hifiberry_dac_remove,
++};
++
++module_platform_driver(snd_rpi_hifiberry_dac_driver);
++
++MODULE_AUTHOR("Florian Meier <florian.meier@koalo.de>");
++MODULE_DESCRIPTION("ASoC Driver for HifiBerry DAC");
++MODULE_LICENSE("GPL v2");
+diff -Nur linux-4.1.3/sound/soc/bcm/hifiberry_dacplus.c linux-xbian-rpi/sound/soc/bcm/hifiberry_dacplus.c
+--- linux-4.1.3/sound/soc/bcm/hifiberry_dacplus.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/sound/soc/bcm/hifiberry_dacplus.c 2015-07-28 01:20:58.465085369 +0200
+@@ -0,0 +1,141 @@
++/*
++ * ASoC Driver for HiFiBerry DAC+
++ *
++ * Author: Daniel Matuschek
++ * Copyright 2014
++ * based on code by Florian Meier <florian.meier@koalo.de>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * version 2 as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
++ * General Public License for more details.
++ */
++
++#include <linux/module.h>
++#include <linux/platform_device.h>
++
++#include <sound/core.h>
++#include <sound/pcm.h>
++#include <sound/pcm_params.h>
++#include <sound/soc.h>
++#include <sound/jack.h>
++
++#include "../codecs/pcm512x.h"
++
++static int snd_rpi_hifiberry_dacplus_init(struct snd_soc_pcm_runtime *rtd)
++{
++ struct snd_soc_codec *codec = rtd->codec;
++ snd_soc_update_bits(codec, PCM512x_GPIO_EN, 0x08, 0x08);
++ snd_soc_update_bits(codec, PCM512x_GPIO_OUTPUT_4, 0xf, 0x02);
++ snd_soc_update_bits(codec, PCM512x_GPIO_CONTROL_1, 0x08,0x08);
++ return 0;
++}
++
++static int snd_rpi_hifiberry_dacplus_hw_params(struct snd_pcm_substream *substream,
++ struct snd_pcm_hw_params *params)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
++ return snd_soc_dai_set_bclk_ratio(cpu_dai, 64);
++}
++
++static int snd_rpi_hifiberry_dacplus_startup(struct snd_pcm_substream *substream) {
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_soc_codec *codec = rtd->codec;
++ snd_soc_update_bits(codec, PCM512x_GPIO_CONTROL_1, 0x08,0x08);
++ return 0;
++}
++
++static void snd_rpi_hifiberry_dacplus_shutdown(struct snd_pcm_substream *substream) {
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_soc_codec *codec = rtd->codec;
++ snd_soc_update_bits(codec, PCM512x_GPIO_CONTROL_1, 0x08,0x00);
++}
++
++/* machine stream operations */
++static struct snd_soc_ops snd_rpi_hifiberry_dacplus_ops = {
++ .hw_params = snd_rpi_hifiberry_dacplus_hw_params,
++ .startup = snd_rpi_hifiberry_dacplus_startup,
++ .shutdown = snd_rpi_hifiberry_dacplus_shutdown,
++};
++
++static struct snd_soc_dai_link snd_rpi_hifiberry_dacplus_dai[] = {
++{
++ .name = "HiFiBerry DAC+",
++ .stream_name = "HiFiBerry DAC+ HiFi",
++ .cpu_dai_name = "bcm2708-i2s.0",
++ .codec_dai_name = "pcm512x-hifi",
++ .platform_name = "bcm2708-i2s.0",
++ .codec_name = "pcm512x.1-004d",
++ .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
++ SND_SOC_DAIFMT_CBS_CFS,
++ .ops = &snd_rpi_hifiberry_dacplus_ops,
++ .init = snd_rpi_hifiberry_dacplus_init,
++},
++};
++
++/* audio machine driver */
++static struct snd_soc_card snd_rpi_hifiberry_dacplus = {
++ .name = "snd_rpi_hifiberry_dacplus",
++ .dai_link = snd_rpi_hifiberry_dacplus_dai,
++ .num_links = ARRAY_SIZE(snd_rpi_hifiberry_dacplus_dai),
++};
++
++static int snd_rpi_hifiberry_dacplus_probe(struct platform_device *pdev)
++{
++ int ret = 0;
++
++ snd_rpi_hifiberry_dacplus.dev = &pdev->dev;
++
++ if (pdev->dev.of_node) {
++ struct device_node *i2s_node;
++ struct snd_soc_dai_link *dai = &snd_rpi_hifiberry_dacplus_dai[0];
++ i2s_node = of_parse_phandle(pdev->dev.of_node,
++ "i2s-controller", 0);
++
++ if (i2s_node) {
++ dai->cpu_dai_name = NULL;
++ dai->cpu_of_node = i2s_node;
++ dai->platform_name = NULL;
++ dai->platform_of_node = i2s_node;
++ }
++ }
++
++ ret = snd_soc_register_card(&snd_rpi_hifiberry_dacplus);
++ if (ret)
++ dev_err(&pdev->dev,
++ "snd_soc_register_card() failed: %d\n", ret);
++
++ return ret;
++}
++
++static int snd_rpi_hifiberry_dacplus_remove(struct platform_device *pdev)
++{
++ return snd_soc_unregister_card(&snd_rpi_hifiberry_dacplus);
++}
++
++static const struct of_device_id snd_rpi_hifiberry_dacplus_of_match[] = {
++ { .compatible = "hifiberry,hifiberry-dacplus", },
++ {},
++};
++MODULE_DEVICE_TABLE(of, snd_rpi_hifiberry_dacplus_of_match);
++
++static struct platform_driver snd_rpi_hifiberry_dacplus_driver = {
++ .driver = {
++ .name = "snd-rpi-hifiberry-dacplus",
++ .owner = THIS_MODULE,
++ .of_match_table = snd_rpi_hifiberry_dacplus_of_match,
++ },
++ .probe = snd_rpi_hifiberry_dacplus_probe,
++ .remove = snd_rpi_hifiberry_dacplus_remove,
++};
++
++module_platform_driver(snd_rpi_hifiberry_dacplus_driver);
++
++MODULE_AUTHOR("Daniel Matuschek <daniel@hifiberry.com>");
++MODULE_DESCRIPTION("ASoC Driver for HiFiBerry DAC+");
++MODULE_LICENSE("GPL v2");
+diff -Nur linux-4.1.3/sound/soc/bcm/hifiberry_digi.c linux-xbian-rpi/sound/soc/bcm/hifiberry_digi.c
+--- linux-4.1.3/sound/soc/bcm/hifiberry_digi.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/sound/soc/bcm/hifiberry_digi.c 2015-07-28 01:20:58.465085369 +0200
+@@ -0,0 +1,223 @@
++/*
++ * ASoC Driver for HifiBerry Digi
++ *
++ * Author: Daniel Matuschek <info@crazy-audio.com>
++ * based on the HifiBerry DAC driver by Florian Meier <florian.meier@koalo.de>
++ * Copyright 2013
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * version 2 as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
++ * General Public License for more details.
++ */
++
++#include <linux/module.h>
++#include <linux/platform_device.h>
++
++#include <sound/core.h>
++#include <sound/pcm.h>
++#include <sound/pcm_params.h>
++#include <sound/soc.h>
++#include <sound/jack.h>
++
++#include "../codecs/wm8804.h"
++
++static short int auto_shutdown_output = 0;
++module_param(auto_shutdown_output, short, S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP);
++MODULE_PARM_DESC(auto_shutdown_output, "Shutdown SP/DIF output if playback is stopped");
++
++
++static int samplerate=44100;
++
++static int snd_rpi_hifiberry_digi_init(struct snd_soc_pcm_runtime *rtd)
++{
++ struct snd_soc_codec *codec = rtd->codec;
++
++ /* enable TX output */
++ snd_soc_update_bits(codec, WM8804_PWRDN, 0x4, 0x0);
++
++ return 0;
++}
++
++static int snd_rpi_hifiberry_digi_startup(struct snd_pcm_substream *substream) {
++ /* turn on digital output */
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_soc_codec *codec = rtd->codec;
++ snd_soc_update_bits(codec, WM8804_PWRDN, 0x3c, 0x00);
++ return 0;
++}
++
++static void snd_rpi_hifiberry_digi_shutdown(struct snd_pcm_substream *substream) {
++ /* turn off output */
++ if (auto_shutdown_output) {
++ /* turn off output */
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_soc_codec *codec = rtd->codec;
++ snd_soc_update_bits(codec, WM8804_PWRDN, 0x3c, 0x3c);
++ }
++}
++
++
++static int snd_rpi_hifiberry_digi_hw_params(struct snd_pcm_substream *substream,
++ struct snd_pcm_hw_params *params)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_soc_dai *codec_dai = rtd->codec_dai;
++ struct snd_soc_codec *codec = rtd->codec;
++ struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
++
++ int sysclk = 27000000; /* This is fixed on this board */
++
++ long mclk_freq=0;
++ int mclk_div=1;
++ int sampling_freq=1;
++
++ int ret;
++
++ samplerate = params_rate(params);
++
++ if (samplerate<=96000) {
++ mclk_freq=samplerate*256;
++ mclk_div=WM8804_MCLKDIV_256FS;
++ } else {
++ mclk_freq=samplerate*128;
++ mclk_div=WM8804_MCLKDIV_128FS;
++ }
++
++ switch (samplerate) {
++ case 32000:
++ sampling_freq=0x03;
++ break;
++ case 44100:
++ sampling_freq=0x00;
++ break;
++ case 48000:
++ sampling_freq=0x02;
++ break;
++ case 88200:
++ sampling_freq=0x08;
++ break;
++ case 96000:
++ sampling_freq=0x0a;
++ break;
++ case 176400:
++ sampling_freq=0x0c;
++ break;
++ case 192000:
++ sampling_freq=0x0e;
++ break;
++ default:
++ dev_err(codec->dev,
++ "Failed to set WM8804 SYSCLK, unsupported samplerate %d\n",
++ samplerate);
++ }
++
++ snd_soc_dai_set_clkdiv(codec_dai, WM8804_MCLK_DIV, mclk_div);
++ snd_soc_dai_set_pll(codec_dai, 0, 0, sysclk, mclk_freq);
++
++ ret = snd_soc_dai_set_sysclk(codec_dai, WM8804_TX_CLKSRC_PLL,
++ sysclk, SND_SOC_CLOCK_OUT);
++ if (ret < 0) {
++ dev_err(codec->dev,
++ "Failed to set WM8804 SYSCLK: %d\n", ret);
++ return ret;
++ }
++
++ /* Enable TX output */
++ snd_soc_update_bits(codec, WM8804_PWRDN, 0x4, 0x0);
++
++ /* Power on */
++ snd_soc_update_bits(codec, WM8804_PWRDN, 0x9, 0);
++
++ /* set sampling frequency status bits */
++ snd_soc_update_bits(codec, WM8804_SPDTX4, 0x0f, sampling_freq);
++
++ return snd_soc_dai_set_bclk_ratio(cpu_dai,64);
++}
++
++/* machine stream operations */
++static struct snd_soc_ops snd_rpi_hifiberry_digi_ops = {
++ .hw_params = snd_rpi_hifiberry_digi_hw_params,
++ .startup = snd_rpi_hifiberry_digi_startup,
++ .shutdown = snd_rpi_hifiberry_digi_shutdown,
++};
++
++static struct snd_soc_dai_link snd_rpi_hifiberry_digi_dai[] = {
++{
++ .name = "HifiBerry Digi",
++ .stream_name = "HifiBerry Digi HiFi",
++ .cpu_dai_name = "bcm2708-i2s.0",
++ .codec_dai_name = "wm8804-spdif",
++ .platform_name = "bcm2708-i2s.0",
++ .codec_name = "wm8804.1-003b",
++ .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
++ SND_SOC_DAIFMT_CBM_CFM,
++ .ops = &snd_rpi_hifiberry_digi_ops,
++ .init = snd_rpi_hifiberry_digi_init,
++},
++};
++
++/* audio machine driver */
++static struct snd_soc_card snd_rpi_hifiberry_digi = {
++ .name = "snd_rpi_hifiberry_digi",
++ .dai_link = snd_rpi_hifiberry_digi_dai,
++ .num_links = ARRAY_SIZE(snd_rpi_hifiberry_digi_dai),
++};
++
++static int snd_rpi_hifiberry_digi_probe(struct platform_device *pdev)
++{
++ int ret = 0;
++
++ snd_rpi_hifiberry_digi.dev = &pdev->dev;
++
++ if (pdev->dev.of_node) {
++ struct device_node *i2s_node;
++ struct snd_soc_dai_link *dai = &snd_rpi_hifiberry_digi_dai[0];
++ i2s_node = of_parse_phandle(pdev->dev.of_node,
++ "i2s-controller", 0);
++
++ if (i2s_node) {
++ dai->cpu_dai_name = NULL;
++ dai->cpu_of_node = i2s_node;
++ dai->platform_name = NULL;
++ dai->platform_of_node = i2s_node;
++ }
++ }
++
++ ret = snd_soc_register_card(&snd_rpi_hifiberry_digi);
++ if (ret)
++ dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n", ret);
++
++ return ret;
++}
++
++static int snd_rpi_hifiberry_digi_remove(struct platform_device *pdev)
++{
++ return snd_soc_unregister_card(&snd_rpi_hifiberry_digi);
++}
++
++static const struct of_device_id snd_rpi_hifiberry_digi_of_match[] = {
++ { .compatible = "hifiberry,hifiberry-digi", },
++ {},
++};
++MODULE_DEVICE_TABLE(of, snd_rpi_hifiberry_digi_of_match);
++
++static struct platform_driver snd_rpi_hifiberry_digi_driver = {
++ .driver = {
++ .name = "snd-hifiberry-digi",
++ .owner = THIS_MODULE,
++ .of_match_table = snd_rpi_hifiberry_digi_of_match,
++ },
++ .probe = snd_rpi_hifiberry_digi_probe,
++ .remove = snd_rpi_hifiberry_digi_remove,
++};
++
++module_platform_driver(snd_rpi_hifiberry_digi_driver);
++
++MODULE_AUTHOR("Daniel Matuschek <info@crazy-audio.com>");
++MODULE_DESCRIPTION("ASoC Driver for HifiBerry Digi");
++MODULE_LICENSE("GPL v2");
+diff -Nur linux-4.1.3/sound/soc/bcm/iqaudio-dac.c linux-xbian-rpi/sound/soc/bcm/iqaudio-dac.c
+--- linux-4.1.3/sound/soc/bcm/iqaudio-dac.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/sound/soc/bcm/iqaudio-dac.c 2015-07-28 01:20:58.465085369 +0200
+@@ -0,0 +1,133 @@
++/*
++ * ASoC Driver for IQaudIO DAC
++ *
++ * Author: Florian Meier <florian.meier@koalo.de>
++ * Copyright 2013
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * version 2 as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
++ * General Public License for more details.
++ */
++
++#include <linux/module.h>
++#include <linux/platform_device.h>
++
++#include <sound/core.h>
++#include <sound/pcm.h>
++#include <sound/pcm_params.h>
++#include <sound/soc.h>
++#include <sound/jack.h>
++
++static int snd_rpi_iqaudio_dac_init(struct snd_soc_pcm_runtime *rtd)
++{
++ int ret;
++ struct snd_soc_card *card = rtd->card;
++ struct snd_soc_codec *codec = rtd->codec;
++
++ ret = snd_soc_limit_volume(codec, "Digital Playback Volume", 207);
++ if (ret < 0)
++ dev_warn(card->dev, "Failed to set volume limit: %d\n", ret);
++
++ return 0;
++}
++
++static int snd_rpi_iqaudio_dac_hw_params(struct snd_pcm_substream *substream,
++ struct snd_pcm_hw_params *params)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++// NOT USED struct snd_soc_dai *codec_dai = rtd->codec_dai;
++// NOT USED struct snd_soc_codec *codec = rtd->codec;
++ struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
++
++ unsigned int sample_bits =
++ snd_pcm_format_physical_width(params_format(params));
++
++ return snd_soc_dai_set_bclk_ratio(cpu_dai, sample_bits * 2);
++}
++
++/* machine stream operations */
++static struct snd_soc_ops snd_rpi_iqaudio_dac_ops = {
++ .hw_params = snd_rpi_iqaudio_dac_hw_params,
++};
++
++static struct snd_soc_dai_link snd_rpi_iqaudio_dac_dai[] = {
++{
++ .name = "IQaudIO DAC",
++ .stream_name = "IQaudIO DAC HiFi",
++ .cpu_dai_name = "bcm2708-i2s.0",
++ .codec_dai_name = "pcm512x-hifi",
++ .platform_name = "bcm2708-i2s.0",
++ .codec_name = "pcm512x.1-004c",
++ .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
++ SND_SOC_DAIFMT_CBS_CFS,
++ .ops = &snd_rpi_iqaudio_dac_ops,
++ .init = snd_rpi_iqaudio_dac_init,
++},
++};
++
++/* audio machine driver */
++static struct snd_soc_card snd_rpi_iqaudio_dac = {
++ .name = "IQaudIODAC",
++ .dai_link = snd_rpi_iqaudio_dac_dai,
++ .num_links = ARRAY_SIZE(snd_rpi_iqaudio_dac_dai),
++};
++
++static int snd_rpi_iqaudio_dac_probe(struct platform_device *pdev)
++{
++ int ret = 0;
++
++ snd_rpi_iqaudio_dac.dev = &pdev->dev;
++
++ if (pdev->dev.of_node) {
++ struct device_node *i2s_node;
++ struct snd_soc_dai_link *dai = &snd_rpi_iqaudio_dac_dai[0];
++ i2s_node = of_parse_phandle(pdev->dev.of_node,
++ "i2s-controller", 0);
++
++ if (i2s_node) {
++ dai->cpu_dai_name = NULL;
++ dai->cpu_of_node = i2s_node;
++ dai->platform_name = NULL;
++ dai->platform_of_node = i2s_node;
++ }
++ }
++
++ ret = snd_soc_register_card(&snd_rpi_iqaudio_dac);
++ if (ret)
++ dev_err(&pdev->dev,
++ "snd_soc_register_card() failed: %d\n", ret);
++
++ return ret;
++}
++
++static int snd_rpi_iqaudio_dac_remove(struct platform_device *pdev)
++{
++ return snd_soc_unregister_card(&snd_rpi_iqaudio_dac);
++}
++
++static const struct of_device_id iqaudio_of_match[] = {
++ { .compatible = "iqaudio,iqaudio-dac", },
++ {},
++};
++MODULE_DEVICE_TABLE(of, iqaudio_of_match);
++
++static struct platform_driver snd_rpi_iqaudio_dac_driver = {
++ .driver = {
++ .name = "snd-rpi-iqaudio-dac",
++ .owner = THIS_MODULE,
++ .of_match_table = iqaudio_of_match,
++ },
++ .probe = snd_rpi_iqaudio_dac_probe,
++ .remove = snd_rpi_iqaudio_dac_remove,
++};
++
++module_platform_driver(snd_rpi_iqaudio_dac_driver);
++
++MODULE_AUTHOR("Florian Meier <florian.meier@koalo.de>");
++MODULE_DESCRIPTION("ASoC Driver for IQAudio DAC");
++MODULE_LICENSE("GPL v2");
+diff -Nur linux-4.1.3/sound/soc/bcm/Kconfig linux-xbian-rpi/sound/soc/bcm/Kconfig
+--- linux-4.1.3/sound/soc/bcm/Kconfig 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/sound/soc/bcm/Kconfig 2015-07-28 01:20:58.465085369 +0200
+@@ -7,3 +7,63 @@
+ Say Y or M if you want to add support for codecs attached to
+ the BCM2835 I2S interface. You will also need
+ to select the audio interfaces to support below.
++
++config SND_BCM2708_SOC_I2S
++ tristate "SoC Audio support for the Broadcom BCM2708 I2S module"
++ depends on MACH_BCM2708 || MACH_BCM2709
++ select REGMAP_MMIO
++ select SND_SOC_DMAENGINE_PCM
++ select SND_SOC_GENERIC_DMAENGINE_PCM
++ help
++ Say Y or M if you want to add support for codecs attached to
++ the BCM2708 I2S interface. You will also need
++ to select the audio interfaces to support below.
++
++config SND_BCM2708_SOC_HIFIBERRY_DAC
++ tristate "Support for HifiBerry DAC"
++ depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S
++ select SND_SOC_PCM5102A
++ help
++ Say Y or M if you want to add support for HifiBerry DAC.
++
++config SND_BCM2708_SOC_HIFIBERRY_DACPLUS
++ tristate "Support for HifiBerry DAC+"
++ depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S
++ select SND_SOC_PCM512x
++ help
++ Say Y or M if you want to add support for HifiBerry DAC+.
++
++config SND_BCM2708_SOC_HIFIBERRY_DIGI
++ tristate "Support for HifiBerry Digi"
++ depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S
++ select SND_SOC_WM8804
++ help
++ Say Y or M if you want to add support for HifiBerry Digi S/PDIF output board.
++
++config SND_BCM2708_SOC_HIFIBERRY_AMP
++ tristate "Support for the HifiBerry Amp"
++ depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S
++ select SND_SOC_TAS5713
++ help
++ Say Y or M if you want to add support for the HifiBerry Amp amplifier board.
++
++config SND_BCM2708_SOC_RPI_DAC
++ tristate "Support for RPi-DAC"
++ depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S
++ select SND_SOC_PCM1794A
++ help
++ Say Y or M if you want to add support for RPi-DAC.
++
++config SND_BCM2708_SOC_RPI_PROTO
++ tristate "Support for Rpi-PROTO"
++ depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S
++ select SND_SOC_WM8731
++ help
++ Say Y or M if you want to add support for Audio Codec Board PROTO (WM8731).
++
++config SND_BCM2708_SOC_IQAUDIO_DAC
++ tristate "Support for IQaudIO-DAC"
++ depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S
++ select SND_SOC_PCM512x_I2C
++ help
++ Say Y or M if you want to add support for IQaudIO-DAC.
+diff -Nur linux-4.1.3/sound/soc/bcm/Makefile linux-xbian-rpi/sound/soc/bcm/Makefile
+--- linux-4.1.3/sound/soc/bcm/Makefile 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/sound/soc/bcm/Makefile 2015-07-28 01:20:58.465085369 +0200
+@@ -3,3 +3,24 @@
+
+ obj-$(CONFIG_SND_BCM2835_SOC_I2S) += snd-soc-bcm2835-i2s.o
+
++# BCM2708 Platform Support
++snd-soc-bcm2708-i2s-objs := bcm2708-i2s.o
++
++obj-$(CONFIG_SND_BCM2708_SOC_I2S) += snd-soc-bcm2708-i2s.o
++
++# BCM2708 Machine Support
++snd-soc-hifiberry-dac-objs := hifiberry_dac.o
++snd-soc-hifiberry-dacplus-objs := hifiberry_dacplus.o
++snd-soc-hifiberry-digi-objs := hifiberry_digi.o
++snd-soc-hifiberry-amp-objs := hifiberry_amp.o
++snd-soc-rpi-dac-objs := rpi-dac.o
++snd-soc-rpi-proto-objs := rpi-proto.o
++snd-soc-iqaudio-dac-objs := iqaudio-dac.o
++
++obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC) += snd-soc-hifiberry-dac.o
++obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS) += snd-soc-hifiberry-dacplus.o
++obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI) += snd-soc-hifiberry-digi.o
++obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP) += snd-soc-hifiberry-amp.o
++obj-$(CONFIG_SND_BCM2708_SOC_RPI_DAC) += snd-soc-rpi-dac.o
++obj-$(CONFIG_SND_BCM2708_SOC_RPI_PROTO) += snd-soc-rpi-proto.o
++obj-$(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC) += snd-soc-iqaudio-dac.o
+diff -Nur linux-4.1.3/sound/soc/bcm/rpi-dac.c linux-xbian-rpi/sound/soc/bcm/rpi-dac.c
+--- linux-4.1.3/sound/soc/bcm/rpi-dac.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/sound/soc/bcm/rpi-dac.c 2015-07-28 01:20:58.465085369 +0200
+@@ -0,0 +1,118 @@
++/*
++ * ASoC Driver for RPi-DAC.
++ *
++ * Author: Florian Meier <florian.meier@koalo.de>
++ * Copyright 2013
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * version 2 as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
++ * General Public License for more details.
++ */
++
++#include <linux/module.h>
++#include <linux/platform_device.h>
++
++#include <sound/core.h>
++#include <sound/pcm.h>
++#include <sound/pcm_params.h>
++#include <sound/soc.h>
++#include <sound/jack.h>
++
++static int snd_rpi_rpi_dac_init(struct snd_soc_pcm_runtime *rtd)
++{
++ return 0;
++}
++
++static int snd_rpi_rpi_dac_hw_params(struct snd_pcm_substream *substream,
++ struct snd_pcm_hw_params *params)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
++
++ return snd_soc_dai_set_bclk_ratio(cpu_dai, 32*2);
++}
++
++/* machine stream operations */
++static struct snd_soc_ops snd_rpi_rpi_dac_ops = {
++ .hw_params = snd_rpi_rpi_dac_hw_params,
++};
++
++static struct snd_soc_dai_link snd_rpi_rpi_dac_dai[] = {
++{
++ .name = "RPi-DAC",
++ .stream_name = "RPi-DAC HiFi",
++ .cpu_dai_name = "bcm2708-i2s.0",
++ .codec_dai_name = "pcm1794a-hifi",
++ .platform_name = "bcm2708-i2s.0",
++ .codec_name = "pcm1794a-codec",
++ .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
++ SND_SOC_DAIFMT_CBS_CFS,
++ .ops = &snd_rpi_rpi_dac_ops,
++ .init = snd_rpi_rpi_dac_init,
++},
++};
++
++/* audio machine driver */
++static struct snd_soc_card snd_rpi_rpi_dac = {
++ .name = "snd_rpi_rpi_dac",
++ .dai_link = snd_rpi_rpi_dac_dai,
++ .num_links = ARRAY_SIZE(snd_rpi_rpi_dac_dai),
++};
++
++static int snd_rpi_rpi_dac_probe(struct platform_device *pdev)
++{
++ int ret = 0;
++
++ snd_rpi_rpi_dac.dev = &pdev->dev;
++
++ if (pdev->dev.of_node) {
++ struct device_node *i2s_node;
++ struct snd_soc_dai_link *dai = &snd_rpi_rpi_dac_dai[0];
++ i2s_node = of_parse_phandle(pdev->dev.of_node, "i2s-controller", 0);
++
++ if (i2s_node) {
++ dai->cpu_dai_name = NULL;
++ dai->cpu_of_node = i2s_node;
++ dai->platform_name = NULL;
++ dai->platform_of_node = i2s_node;
++ }
++ }
++
++ ret = snd_soc_register_card(&snd_rpi_rpi_dac);
++ if (ret)
++ dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n", ret);
++
++ return ret;
++}
++
++static int snd_rpi_rpi_dac_remove(struct platform_device *pdev)
++{
++ return snd_soc_unregister_card(&snd_rpi_rpi_dac);
++}
++
++static const struct of_device_id snd_rpi_rpi_dac_of_match[] = {
++ { .compatible = "rpi,rpi-dac", },
++ {},
++};
++MODULE_DEVICE_TABLE(of, snd_rpi_rpi_dac_of_match);
++
++static struct platform_driver snd_rpi_rpi_dac_driver = {
++ .driver = {
++ .name = "snd-rpi-dac",
++ .owner = THIS_MODULE,
++ .of_match_table = snd_rpi_rpi_dac_of_match,
++ },
++ .probe = snd_rpi_rpi_dac_probe,
++ .remove = snd_rpi_rpi_dac_remove,
++};
++
++module_platform_driver(snd_rpi_rpi_dac_driver);
++
++MODULE_AUTHOR("Florian Meier <florian.meier@koalo.de>");
++MODULE_DESCRIPTION("ASoC Driver for RPi-DAC");
++MODULE_LICENSE("GPL v2");
+diff -Nur linux-4.1.3/sound/soc/bcm/rpi-proto.c linux-xbian-rpi/sound/soc/bcm/rpi-proto.c
+--- linux-4.1.3/sound/soc/bcm/rpi-proto.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/sound/soc/bcm/rpi-proto.c 2015-07-28 01:20:58.465085369 +0200
+@@ -0,0 +1,153 @@
++/*
++ * ASoC driver for PROTO AudioCODEC (with a WM8731)
++ * connected to a Raspberry Pi
++ *
++ * Author: Florian Meier, <koalo@koalo.de>
++ * Copyright 2013
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/module.h>
++#include <linux/platform_device.h>
++
++#include <sound/core.h>
++#include <sound/pcm.h>
++#include <sound/soc.h>
++#include <sound/jack.h>
++
++#include "../codecs/wm8731.h"
++
++static const unsigned int wm8731_rates_12288000[] = {
++ 8000, 32000, 48000, 96000,
++};
++
++static struct snd_pcm_hw_constraint_list wm8731_constraints_12288000 = {
++ .list = wm8731_rates_12288000,
++ .count = ARRAY_SIZE(wm8731_rates_12288000),
++};
++
++static int snd_rpi_proto_startup(struct snd_pcm_substream *substream)
++{
++ /* Setup constraints, because there is a 12.288 MHz XTAL on the board */
++ snd_pcm_hw_constraint_list(substream->runtime, 0,
++ SNDRV_PCM_HW_PARAM_RATE,
++ &wm8731_constraints_12288000);
++ return 0;
++}
++
++static int snd_rpi_proto_hw_params(struct snd_pcm_substream *substream,
++ struct snd_pcm_hw_params *params)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_soc_codec *codec = rtd->codec;
++ struct snd_soc_dai *codec_dai = rtd->codec_dai;
++ struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
++ int sysclk = 12288000; /* This is fixed on this board */
++
++ /* Set proto bclk */
++ int ret = snd_soc_dai_set_bclk_ratio(cpu_dai,32*2);
++ if (ret < 0){
++ dev_err(codec->dev,
++ "Failed to set BCLK ratio %d\n", ret);
++ return ret;
++ }
++
++ /* Set proto sysclk */
++ ret = snd_soc_dai_set_sysclk(codec_dai, WM8731_SYSCLK_XTAL,
++ sysclk, SND_SOC_CLOCK_IN);
++ if (ret < 0) {
++ dev_err(codec->dev,
++ "Failed to set WM8731 SYSCLK: %d\n", ret);
++ return ret;
++ }
++
++ return 0;
++}
++
++/* machine stream operations */
++static struct snd_soc_ops snd_rpi_proto_ops = {
++ .startup = snd_rpi_proto_startup,
++ .hw_params = snd_rpi_proto_hw_params,
++};
++
++static struct snd_soc_dai_link snd_rpi_proto_dai[] = {
++{
++ .name = "WM8731",
++ .stream_name = "WM8731 HiFi",
++ .cpu_dai_name = "bcm2708-i2s.0",
++ .codec_dai_name = "wm8731-hifi",
++ .platform_name = "bcm2708-i2s.0",
++ .codec_name = "wm8731.1-001a",
++ .dai_fmt = SND_SOC_DAIFMT_I2S
++ | SND_SOC_DAIFMT_NB_NF
++ | SND_SOC_DAIFMT_CBM_CFM,
++ .ops = &snd_rpi_proto_ops,
++},
++};
++
++/* audio machine driver */
++static struct snd_soc_card snd_rpi_proto = {
++ .name = "snd_rpi_proto",
++ .dai_link = snd_rpi_proto_dai,
++ .num_links = ARRAY_SIZE(snd_rpi_proto_dai),
++};
++
++static int snd_rpi_proto_probe(struct platform_device *pdev)
++{
++ int ret = 0;
++
++ snd_rpi_proto.dev = &pdev->dev;
++
++ if (pdev->dev.of_node) {
++ struct device_node *i2s_node;
++ struct snd_soc_dai_link *dai = &snd_rpi_proto_dai[0];
++ i2s_node = of_parse_phandle(pdev->dev.of_node,
++ "i2s-controller", 0);
++
++ if (i2s_node) {
++ dai->cpu_dai_name = NULL;
++ dai->cpu_of_node = i2s_node;
++ dai->platform_name = NULL;
++ dai->platform_of_node = i2s_node;
++ }
++ }
++
++ ret = snd_soc_register_card(&snd_rpi_proto);
++ if (ret) {
++ dev_err(&pdev->dev,
++ "snd_soc_register_card() failed: %d\n", ret);
++ }
++
++ return ret;
++}
++
++
++static int snd_rpi_proto_remove(struct platform_device *pdev)
++{
++ return snd_soc_unregister_card(&snd_rpi_proto);
++}
++
++static const struct of_device_id snd_rpi_proto_of_match[] = {
++ { .compatible = "rpi,rpi-proto", },
++ {},
++};
++MODULE_DEVICE_TABLE(of, snd_rpi_proto_of_match);
++
++static struct platform_driver snd_rpi_proto_driver = {
++ .driver = {
++ .name = "snd-rpi-proto",
++ .owner = THIS_MODULE,
++ .of_match_table = snd_rpi_proto_of_match,
++ },
++ .probe = snd_rpi_proto_probe,
++ .remove = snd_rpi_proto_remove,
++};
++
++module_platform_driver(snd_rpi_proto_driver);
++
++MODULE_AUTHOR("Florian Meier");
++MODULE_DESCRIPTION("ASoC Driver for Raspberry Pi connected to PROTO board (WM8731)");
++MODULE_LICENSE("GPL");
+diff -Nur linux-4.1.3/sound/soc/codecs/Kconfig linux-xbian-rpi/sound/soc/codecs/Kconfig
+--- linux-4.1.3/sound/soc/codecs/Kconfig 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/sound/soc/codecs/Kconfig 2015-07-28 01:20:58.465085369 +0200
+@@ -83,6 +83,8 @@
+ select SND_SOC_PCM512x_I2C if I2C
+ select SND_SOC_PCM512x_SPI if SPI_MASTER
+ select SND_SOC_RT286 if I2C
++ select SND_SOC_PCM5102A if I2C
++ select SND_SOC_PCM1794A if I2C
+ select SND_SOC_RT5631 if I2C
+ select SND_SOC_RT5640 if I2C
+ select SND_SOC_RT5645 if I2C
+@@ -107,6 +109,7 @@
+ select SND_SOC_TFA9879 if I2C
+ select SND_SOC_TLV320AIC23_I2C if I2C
+ select SND_SOC_TLV320AIC23_SPI if SPI_MASTER
++ select SND_SOC_TAS5713 if I2C
+ select SND_SOC_TLV320AIC26 if SPI_MASTER
+ select SND_SOC_TLV320AIC31XX if I2C
+ select SND_SOC_TLV320AIC32X4 if I2C
+@@ -511,6 +514,12 @@
+ tristate
+ depends on I2C
+
++config SND_SOC_PCM1794A
++ tristate
++
++config SND_SOC_PCM5102A
++ tristate
++
+ config SND_SOC_RT5631
+ tristate "Realtek ALC5631/RT5631 CODEC"
+ depends on I2C
+@@ -615,6 +624,9 @@
+ tristate "NXP Semiconductors TFA9879 amplifier"
+ depends on I2C
+
++config SND_SOC_TAS5713
++ tristate
++
+ config SND_SOC_TLV320AIC23
+ tristate
+
+diff -Nur linux-4.1.3/sound/soc/codecs/Makefile linux-xbian-rpi/sound/soc/codecs/Makefile
+--- linux-4.1.3/sound/soc/codecs/Makefile 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/sound/soc/codecs/Makefile 2015-07-28 01:20:58.465085369 +0200
+@@ -78,6 +78,8 @@
+ snd-soc-pcm512x-spi-objs := pcm512x-spi.o
+ snd-soc-rl6231-objs := rl6231.o
+ snd-soc-rt286-objs := rt286.o
++snd-soc-pcm1794a-objs := pcm1794a.o
++snd-soc-pcm5102a-objs := pcm5102a.o
+ snd-soc-rt5631-objs := rt5631.o
+ snd-soc-rt5640-objs := rt5640.o
+ snd-soc-rt5645-objs := rt5645.o
+@@ -107,6 +109,7 @@
+ snd-soc-stac9766-objs := stac9766.o
+ snd-soc-tas5086-objs := tas5086.o
+ snd-soc-tfa9879-objs := tfa9879.o
++snd-soc-tas5713-objs := tas5713.o
+ snd-soc-tlv320aic23-objs := tlv320aic23.o
+ snd-soc-tlv320aic23-i2c-objs := tlv320aic23-i2c.o
+ snd-soc-tlv320aic23-spi-objs := tlv320aic23-spi.o
+@@ -263,6 +266,8 @@
+ obj-$(CONFIG_SND_SOC_PCM512x_SPI) += snd-soc-pcm512x-spi.o
+ obj-$(CONFIG_SND_SOC_RL6231) += snd-soc-rl6231.o
+ obj-$(CONFIG_SND_SOC_RT286) += snd-soc-rt286.o
++obj-$(CONFIG_SND_SOC_PCM1794A) += snd-soc-pcm1794a.o
++obj-$(CONFIG_SND_SOC_PCM5102A) += snd-soc-pcm5102a.o
+ obj-$(CONFIG_SND_SOC_RT5631) += snd-soc-rt5631.o
+ obj-$(CONFIG_SND_SOC_RT5640) += snd-soc-rt5640.o
+ obj-$(CONFIG_SND_SOC_RT5645) += snd-soc-rt5645.o
+@@ -289,6 +294,7 @@
+ obj-$(CONFIG_SND_SOC_TAS2552) += snd-soc-tas2552.o
+ obj-$(CONFIG_SND_SOC_TAS5086) += snd-soc-tas5086.o
+ obj-$(CONFIG_SND_SOC_TFA9879) += snd-soc-tfa9879.o
++obj-$(CONFIG_SND_SOC_TAS5713) += snd-soc-tas5713.o
+ obj-$(CONFIG_SND_SOC_TLV320AIC23) += snd-soc-tlv320aic23.o
+ obj-$(CONFIG_SND_SOC_TLV320AIC23_I2C) += snd-soc-tlv320aic23-i2c.o
+ obj-$(CONFIG_SND_SOC_TLV320AIC23_SPI) += snd-soc-tlv320aic23-spi.o
+diff -Nur linux-4.1.3/sound/soc/codecs/pcm1794a.c linux-xbian-rpi/sound/soc/codecs/pcm1794a.c
+--- linux-4.1.3/sound/soc/codecs/pcm1794a.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/sound/soc/codecs/pcm1794a.c 2015-07-28 01:20:58.465085369 +0200
+@@ -0,0 +1,69 @@
++/*
++ * Driver for the PCM1794A codec
++ *
++ * Author: Florian Meier <florian.meier@koalo.de>
++ * Copyright 2013
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * version 2 as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
++ * General Public License for more details.
++ */
++
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++
++#include <sound/soc.h>
++
++static struct snd_soc_dai_driver pcm1794a_dai = {
++ .name = "pcm1794a-hifi",
++ .playback = {
++ .channels_min = 2,
++ .channels_max = 2,
++ .rates = SNDRV_PCM_RATE_8000_192000,
++ .formats = SNDRV_PCM_FMTBIT_S16_LE |
++ SNDRV_PCM_FMTBIT_S24_LE
++ },
++};
++
++static struct snd_soc_codec_driver soc_codec_dev_pcm1794a;
++
++static int pcm1794a_probe(struct platform_device *pdev)
++{
++ return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_pcm1794a,
++ &pcm1794a_dai, 1);
++}
++
++static int pcm1794a_remove(struct platform_device *pdev)
++{
++ snd_soc_unregister_codec(&pdev->dev);
++ return 0;
++}
++
++static const struct of_device_id pcm1794a_of_match[] = {
++ { .compatible = "ti,pcm1794a", },
++ { }
++};
++MODULE_DEVICE_TABLE(of, pcm1794a_of_match);
++
++static struct platform_driver pcm1794a_codec_driver = {
++ .probe = pcm1794a_probe,
++ .remove = pcm1794a_remove,
++ .driver = {
++ .name = "pcm1794a-codec",
++ .owner = THIS_MODULE,
++ .of_match_table = of_match_ptr(pcm1794a_of_match),
++ },
++};
++
++module_platform_driver(pcm1794a_codec_driver);
++
++MODULE_DESCRIPTION("ASoC PCM1794A codec driver");
++MODULE_AUTHOR("Florian Meier <florian.meier@koalo.de>");
++MODULE_LICENSE("GPL v2");
+diff -Nur linux-4.1.3/sound/soc/codecs/pcm5102a.c linux-xbian-rpi/sound/soc/codecs/pcm5102a.c
+--- linux-4.1.3/sound/soc/codecs/pcm5102a.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/sound/soc/codecs/pcm5102a.c 2015-07-28 01:20:58.465085369 +0200
+@@ -0,0 +1,70 @@
++/*
++ * Driver for the PCM5102A codec
++ *
++ * Author: Florian Meier <florian.meier@koalo.de>
++ * Copyright 2013
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * version 2 as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
++ * General Public License for more details.
++ */
++
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++
++#include <sound/soc.h>
++
++static struct snd_soc_dai_driver pcm5102a_dai = {
++ .name = "pcm5102a-hifi",
++ .playback = {
++ .channels_min = 2,
++ .channels_max = 2,
++ .rates = SNDRV_PCM_RATE_8000_192000,
++ .formats = SNDRV_PCM_FMTBIT_S16_LE |
++ SNDRV_PCM_FMTBIT_S24_LE |
++ SNDRV_PCM_FMTBIT_S32_LE
++ },
++};
++
++static struct snd_soc_codec_driver soc_codec_dev_pcm5102a;
++
++static int pcm5102a_probe(struct platform_device *pdev)
++{
++ return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_pcm5102a,
++ &pcm5102a_dai, 1);
++}
++
++static int pcm5102a_remove(struct platform_device *pdev)
++{
++ snd_soc_unregister_codec(&pdev->dev);
++ return 0;
++}
++
++static const struct of_device_id pcm5102a_of_match[] = {
++ { .compatible = "ti,pcm5102a", },
++ { }
++};
++MODULE_DEVICE_TABLE(of, pcm5102a_of_match);
++
++static struct platform_driver pcm5102a_codec_driver = {
++ .probe = pcm5102a_probe,
++ .remove = pcm5102a_remove,
++ .driver = {
++ .name = "pcm5102a-codec",
++ .owner = THIS_MODULE,
++ .of_match_table = pcm5102a_of_match,
++ },
++};
++
++module_platform_driver(pcm5102a_codec_driver);
++
++MODULE_DESCRIPTION("ASoC PCM5102A codec driver");
++MODULE_AUTHOR("Florian Meier <florian.meier@koalo.de>");
++MODULE_LICENSE("GPL v2");
+diff -Nur linux-4.1.3/sound/soc/codecs/tas5713.c linux-xbian-rpi/sound/soc/codecs/tas5713.c
+--- linux-4.1.3/sound/soc/codecs/tas5713.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/sound/soc/codecs/tas5713.c 2015-07-28 01:20:58.465085369 +0200
+@@ -0,0 +1,369 @@
++/*
++ * ASoC Driver for TAS5713
++ *
++ * Author: Sebastian Eickhoff <basti.eickhoff@googlemail.com>
++ * Copyright 2014
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * version 2 as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
++ * General Public License for more details.
++ */
++
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/init.h>
++#include <linux/delay.h>
++#include <linux/pm.h>
++#include <linux/i2c.h>
++#include <linux/of_device.h>
++#include <linux/spi/spi.h>
++#include <linux/regmap.h>
++#include <linux/regulator/consumer.h>
++#include <linux/slab.h>
++#include <sound/core.h>
++#include <sound/pcm.h>
++#include <sound/pcm_params.h>
++#include <sound/soc.h>
++#include <sound/initval.h>
++#include <sound/tlv.h>
++
++#include <linux/kernel.h>
++#include <linux/string.h>
++#include <linux/fs.h>
++#include <asm/uaccess.h>
++
++#include "tas5713.h"
++
++
++static struct i2c_client *i2c;
++
++struct tas5713_priv {
++ struct regmap *regmap;
++ int mclk_div;
++ struct snd_soc_codec *codec;
++};
++
++static struct tas5713_priv *priv_data;
++
++
++
++
++/*
++ * _ _ ___ _ ___ _ _
++ * /_\ | | / __| /_\ / __|___ _ _| |_ _ _ ___| |___
++ * / _ \| |__\__ \/ _ \ | (__/ _ \ ' \ _| '_/ _ \ (_-<
++ * /_/ \_\____|___/_/ \_\ \___\___/_||_\__|_| \___/_/__/
++ *
++ */
++
++static const DECLARE_TLV_DB_SCALE(tas5713_vol_tlv, -10000, 50, 1);
++
++
++static const struct snd_kcontrol_new tas5713_snd_controls[] = {
++ SOC_SINGLE_TLV ("Master" , TAS5713_VOL_MASTER, 0, 248, 1, tas5713_vol_tlv),
++ SOC_DOUBLE_R_TLV("Channels" , TAS5713_VOL_CH1, TAS5713_VOL_CH2, 0, 248, 1, tas5713_vol_tlv)
++};
++
++
++
++
++/*
++ * __ __ _ _ ___ _
++ * | \/ |__ _ __| |_ (_)_ _ ___ | \ _ _(_)_ _____ _ _
++ * | |\/| / _` / _| ' \| | ' \/ -_) | |) | '_| \ V / -_) '_|
++ * |_| |_\__,_\__|_||_|_|_||_\___| |___/|_| |_|\_/\___|_|
++ *
++ */
++
++static int tas5713_hw_params(struct snd_pcm_substream *substream,
++ struct snd_pcm_hw_params *params,
++ struct snd_soc_dai *dai)
++{
++ u16 blen = 0x00;
++
++ struct snd_soc_codec *codec;
++ codec = dai->codec;
++ priv_data->codec = dai->codec;
++
++ switch (params_format(params)) {
++ case SNDRV_PCM_FORMAT_S16_LE:
++ blen = 0x03;
++ break;
++ case SNDRV_PCM_FORMAT_S20_3LE:
++ blen = 0x1;
++ break;
++ case SNDRV_PCM_FORMAT_S24_LE:
++ blen = 0x04;
++ break;
++ case SNDRV_PCM_FORMAT_S32_LE:
++ blen = 0x05;
++ break;
++ default:
++ dev_err(dai->dev, "Unsupported word length: %u\n",
++ params_format(params));
++ return -EINVAL;
++ }
++
++ // set word length
++ snd_soc_update_bits(codec, TAS5713_SERIAL_DATA_INTERFACE, 0x7, blen);
++
++ return 0;
++}
++
++
++static int tas5713_mute_stream(struct snd_soc_dai *dai, int mute, int stream)
++{
++ unsigned int val = 0;
++
++ struct tas5713_priv *tas5713;
++ struct snd_soc_codec *codec = dai->codec;
++ tas5713 = snd_soc_codec_get_drvdata(codec);
++
++ if (mute) {
++ val = TAS5713_SOFT_MUTE_ALL;
++ }
++
++ return regmap_write(tas5713->regmap, TAS5713_SOFT_MUTE, val);
++}
++
++
++static const struct snd_soc_dai_ops tas5713_dai_ops = {
++ .hw_params = tas5713_hw_params,
++ .mute_stream = tas5713_mute_stream,
++};
++
++
++static struct snd_soc_dai_driver tas5713_dai = {
++ .name = "tas5713-hifi",
++ .playback = {
++ .stream_name = "Playback",
++ .channels_min = 2,
++ .channels_max = 2,
++ .rates = SNDRV_PCM_RATE_8000_48000,
++ .formats = (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE ),
++ },
++ .ops = &tas5713_dai_ops,
++};
++
++
++
++
++/*
++ * ___ _ ___ _
++ * / __|___ __| |___ __ | \ _ _(_)_ _____ _ _
++ * | (__/ _ \/ _` / -_) _| | |) | '_| \ V / -_) '_|
++ * \___\___/\__,_\___\__| |___/|_| |_|\_/\___|_|
++ *
++ */
++
++static int tas5713_remove(struct snd_soc_codec *codec)
++{
++ struct tas5713_priv *tas5713;
++
++ tas5713 = snd_soc_codec_get_drvdata(codec);
++
++ return 0;
++}
++
++
++static int tas5713_probe(struct snd_soc_codec *codec)
++{
++ struct tas5713_priv *tas5713;
++ int i, ret;
++
++ i2c = container_of(codec->dev, struct i2c_client, dev);
++
++ tas5713 = snd_soc_codec_get_drvdata(codec);
++
++ // Reset error
++ ret = snd_soc_write(codec, TAS5713_ERROR_STATUS, 0x00);
++ if (ret < 0) return ret;
++
++ // Trim oscillator
++ ret = snd_soc_write(codec, TAS5713_OSC_TRIM, 0x00);
++ if (ret < 0) return ret;
++ msleep(1000);
++
++ // Reset error
++ ret = snd_soc_write(codec, TAS5713_ERROR_STATUS, 0x00);
++ if (ret < 0) return ret;
++
++ // Clock mode: 44/48kHz, MCLK=64xfs
++ ret = snd_soc_write(codec, TAS5713_CLOCK_CTRL, 0x60);
++ if (ret < 0) return ret;
++
++ // I2S 24bit
++ ret = snd_soc_write(codec, TAS5713_SERIAL_DATA_INTERFACE, 0x05);
++ if (ret < 0) return ret;
++
++ // Unmute
++ ret = snd_soc_write(codec, TAS5713_SYSTEM_CTRL2, 0x00);
++ if (ret < 0) return ret;
++ ret = snd_soc_write(codec, TAS5713_SOFT_MUTE, 0x00);
++ if (ret < 0) return ret;
++
++ // Set volume to 0db
++ ret = snd_soc_write(codec, TAS5713_VOL_MASTER, 0x00);
++ if (ret < 0) return ret;
++
++ // Now start programming the default initialization sequence
++ for (i = 0; i < ARRAY_SIZE(tas5713_init_sequence); ++i) {
++ ret = i2c_master_send(i2c,
++ tas5713_init_sequence[i].data,
++ tas5713_init_sequence[i].size);
++ if (ret < 0) {
++ printk(KERN_INFO "TAS5713 CODEC PROBE: InitSeq returns: %d\n", ret);
++ }
++ }
++
++ // Unmute
++ ret = snd_soc_write(codec, TAS5713_SYSTEM_CTRL2, 0x00);
++ if (ret < 0) return ret;
++
++ return 0;
++}
++
++
++static struct snd_soc_codec_driver soc_codec_dev_tas5713 = {
++ .probe = tas5713_probe,
++ .remove = tas5713_remove,
++ .controls = tas5713_snd_controls,
++ .num_controls = ARRAY_SIZE(tas5713_snd_controls),
++};
++
++
++
++
++/*
++ * ___ ___ ___ ___ _
++ * |_ _|_ ) __| | \ _ _(_)_ _____ _ _
++ * | | / / (__ | |) | '_| \ V / -_) '_|
++ * |___/___\___| |___/|_| |_|\_/\___|_|
++ *
++ */
++
++static const struct reg_default tas5713_reg_defaults[] = {
++ { 0x07 ,0x80 }, // R7 - VOL_MASTER - -40dB
++ { 0x08 , 30 }, // R8 - VOL_CH1 - 0dB
++ { 0x09 , 30 }, // R9 - VOL_CH2 - 0dB
++ { 0x0A ,0x80 }, // R10 - VOL_HEADPHONE - -40dB
++};
++
++
++static bool tas5713_reg_volatile(struct device *dev, unsigned int reg)
++{
++ switch (reg) {
++ case TAS5713_DEVICE_ID:
++ case TAS5713_ERROR_STATUS:
++ return true;
++ default:
++ return false;
++ }
++}
++
++
++static const struct of_device_id tas5713_of_match[] = {
++ { .compatible = "ti,tas5713", },
++ { }
++};
++MODULE_DEVICE_TABLE(of, tas5713_of_match);
++
++
++static struct regmap_config tas5713_regmap_config = {
++ .reg_bits = 8,
++ .val_bits = 8,
++
++ .max_register = TAS5713_MAX_REGISTER,
++ .volatile_reg = tas5713_reg_volatile,
++
++ .cache_type = REGCACHE_RBTREE,
++ .reg_defaults = tas5713_reg_defaults,
++ .num_reg_defaults = ARRAY_SIZE(tas5713_reg_defaults),
++};
++
++
++static int tas5713_i2c_probe(struct i2c_client *i2c,
++ const struct i2c_device_id *id)
++{
++ int ret;
++
++ priv_data = devm_kzalloc(&i2c->dev, sizeof *priv_data, GFP_KERNEL);
++ if (!priv_data)
++ return -ENOMEM;
++
++ priv_data->regmap = devm_regmap_init_i2c(i2c, &tas5713_regmap_config);
++ if (IS_ERR(priv_data->regmap)) {
++ ret = PTR_ERR(priv_data->regmap);
++ return ret;
++ }
++
++ i2c_set_clientdata(i2c, priv_data);
++
++ ret = snd_soc_register_codec(&i2c->dev,
++ &soc_codec_dev_tas5713, &tas5713_dai, 1);
++
++ return ret;
++}
++
++
++static int tas5713_i2c_remove(struct i2c_client *i2c)
++{
++ snd_soc_unregister_codec(&i2c->dev);
++ i2c_set_clientdata(i2c, NULL);
++
++ kfree(priv_data);
++
++ return 0;
++}
++
++
++static const struct i2c_device_id tas5713_i2c_id[] = {
++ { "tas5713", 0 },
++ { }
++};
++
++MODULE_DEVICE_TABLE(i2c, tas5713_i2c_id);
++
++
++static struct i2c_driver tas5713_i2c_driver = {
++ .driver = {
++ .name = "tas5713",
++ .owner = THIS_MODULE,
++ .of_match_table = tas5713_of_match,
++ },
++ .probe = tas5713_i2c_probe,
++ .remove = tas5713_i2c_remove,
++ .id_table = tas5713_i2c_id
++};
++
++
++static int __init tas5713_modinit(void)
++{
++ int ret = 0;
++
++ ret = i2c_add_driver(&tas5713_i2c_driver);
++ if (ret) {
++ printk(KERN_ERR "Failed to register tas5713 I2C driver: %d\n",
++ ret);
++ }
++
++ return ret;
++}
++module_init(tas5713_modinit);
++
++
++static void __exit tas5713_exit(void)
++{
++ i2c_del_driver(&tas5713_i2c_driver);
++}
++module_exit(tas5713_exit);
++
++
++MODULE_AUTHOR("Sebastian Eickhoff <basti.eickhoff@googlemail.com>");
++MODULE_DESCRIPTION("ASoC driver for TAS5713");
++MODULE_LICENSE("GPL v2");
+diff -Nur linux-4.1.3/sound/soc/codecs/tas5713.h linux-xbian-rpi/sound/soc/codecs/tas5713.h
+--- linux-4.1.3/sound/soc/codecs/tas5713.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-rpi/sound/soc/codecs/tas5713.h 2015-07-28 01:20:58.465085369 +0200
+@@ -0,0 +1,210 @@
++/*
++ * ASoC Driver for TAS5713
++ *
++ * Author: Sebastian Eickhoff <basti.eickhoff@googlemail.com>
++ * Copyright 2014
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * version 2 as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
++ * General Public License for more details.
++ */
++
++#ifndef _TAS5713_H
++#define _TAS5713_H
++
++
++// TAS5713 I2C-bus register addresses
++
++#define TAS5713_CLOCK_CTRL 0x00
++#define TAS5713_DEVICE_ID 0x01
++#define TAS5713_ERROR_STATUS 0x02
++#define TAS5713_SYSTEM_CTRL1 0x03
++#define TAS5713_SERIAL_DATA_INTERFACE 0x04
++#define TAS5713_SYSTEM_CTRL2 0x05
++#define TAS5713_SOFT_MUTE 0x06
++#define TAS5713_VOL_MASTER 0x07
++#define TAS5713_VOL_CH1 0x08
++#define TAS5713_VOL_CH2 0x09
++#define TAS5713_VOL_HEADPHONE 0x0A
++#define TAS5713_VOL_CONFIG 0x0E
++#define TAS5713_MODULATION_LIMIT 0x10
++#define TAS5713_IC_DLY_CH1 0x11
++#define TAS5713_IC_DLY_CH2 0x12
++#define TAS5713_IC_DLY_CH3 0x13
++#define TAS5713_IC_DLY_CH4 0x14
++
++#define TAS5713_START_STOP_PERIOD 0x1A
++#define TAS5713_OSC_TRIM 0x1B
++#define TAS5713_BKND_ERR 0x1C
++
++#define TAS5713_INPUT_MUX 0x20
++#define TAS5713_SRC_SELECT_CH4 0x21
++#define TAS5713_PWM_MUX 0x25
++
++#define TAS5713_CH1_BQ0 0x29
++#define TAS5713_CH1_BQ1 0x2A
++#define TAS5713_CH1_BQ2 0x2B
++#define TAS5713_CH1_BQ3 0x2C
++#define TAS5713_CH1_BQ4 0x2D
++#define TAS5713_CH1_BQ5 0x2E
++#define TAS5713_CH1_BQ6 0x2F
++#define TAS5713_CH1_BQ7 0x58
++#define TAS5713_CH1_BQ8 0x59
++
++#define TAS5713_CH2_BQ0 0x30
++#define TAS5713_CH2_BQ1 0x31
++#define TAS5713_CH2_BQ2 0x32
++#define TAS5713_CH2_BQ3 0x33
++#define TAS5713_CH2_BQ4 0x34
++#define TAS5713_CH2_BQ5 0x35
++#define TAS5713_CH2_BQ6 0x36
++#define TAS5713_CH2_BQ7 0x5C
++#define TAS5713_CH2_BQ8 0x5D
++
++#define TAS5713_CH4_BQ0 0x5A
++#define TAS5713_CH4_BQ1 0x5B
++#define TAS5713_CH3_BQ0 0x5E
++#define TAS5713_CH3_BQ1 0x5F
++
++#define TAS5713_DRC1_SOFTENING_FILTER_ALPHA_OMEGA 0x3B
++#define TAS5713_DRC1_ATTACK_RELEASE_RATE 0x3C
++#define TAS5713_DRC2_SOFTENING_FILTER_ALPHA_OMEGA 0x3E
++#define TAS5713_DRC2_ATTACK_RELEASE_RATE 0x3F
++#define TAS5713_DRC1_ATTACK_RELEASE_THRES 0x40
++#define TAS5713_DRC2_ATTACK_RELEASE_THRES 0x43
++#define TAS5713_DRC_CTRL 0x46
++
++#define TAS5713_BANK_SW_CTRL 0x50
++#define TAS5713_CH1_OUTPUT_MIXER 0x51
++#define TAS5713_CH2_OUTPUT_MIXER 0x52
++#define TAS5713_CH1_INPUT_MIXER 0x53
++#define TAS5713_CH2_INPUT_MIXER 0x54
++#define TAS5713_OUTPUT_POST_SCALE 0x56
++#define TAS5713_OUTPUT_PRESCALE 0x57
++
++#define TAS5713_IDF_POST_SCALE 0x62
++
++#define TAS5713_CH1_INLINE_MIXER 0x70
++#define TAS5713_CH1_INLINE_DRC_EN_MIXER 0x71
++#define TAS5713_CH1_R_CHANNEL_MIXER 0x72
++#define TAS5713_CH1_L_CHANNEL_MIXER 0x73
++#define TAS5713_CH2_INLINE_MIXER 0x74
++#define TAS5713_CH2_INLINE_DRC_EN_MIXER 0x75
++#define TAS5713_CH2_L_CHANNEL_MIXER 0x76
++#define TAS5713_CH2_R_CHANNEL_MIXER 0x77
++
++#define TAS5713_UPDATE_DEV_ADDR_KEY 0xF8
++#define TAS5713_UPDATE_DEV_ADDR_REG 0xF9
++
++#define TAS5713_REGISTER_COUNT 0x46
++#define TAS5713_MAX_REGISTER 0xF9
++
++
++// Bitmasks for registers
++#define TAS5713_SOFT_MUTE_ALL 0x07
++
++
++
++struct tas5713_init_command {
++ const int size;
++ const char *const data;
++};
++
++static const struct tas5713_init_command tas5713_init_sequence[] = {
++
++ // Trim oscillator
++ { .size = 2, .data = "\x1B\x00" },
++ // System control register 1 (0x03): block DC
++ { .size = 2, .data = "\x03\x80" },
++ // Mute everything
++ { .size = 2, .data = "\x05\x40" },
++ // Modulation limit register (0x10): 97.7%
++ { .size = 2, .data = "\x10\x02" },
++ // Interchannel delay registers
++ // (0x11, 0x12, 0x13, and 0x14): BD mode
++ { .size = 2, .data = "\x11\xB8" },
++ { .size = 2, .data = "\x12\x60" },
++ { .size = 2, .data = "\x13\xA0" },
++ { .size = 2, .data = "\x14\x48" },
++ // PWM shutdown group register (0x19): no shutdown
++ { .size = 2, .data = "\x19\x00" },
++ // Input multiplexer register (0x20): BD mode
++ { .size = 2, .data = "\x20\x00\x89\x77\x72" },
++ // PWM output mux register (0x25)
++ // Channel 1 --> OUTA, channel 1 neg --> OUTB
++ // Channel 2 --> OUTC, channel 2 neg --> OUTD
++ { .size = 5, .data = "\x25\x01\x02\x13\x45" },
++ // DRC control (0x46): DRC off
++ { .size = 5, .data = "\x46\x00\x00\x00\x00" },
++ // BKND_ERR register (0x1C): 299ms reset period
++ { .size = 2, .data = "\x1C\x07" },
++ // Mute channel 3
++ { .size = 2, .data = "\x0A\xFF" },
++ // Volume configuration register (0x0E): volume slew 512 steps
++ { .size = 2, .data = "\x0E\x90" },
++ // Clock control register (0x00): 44/48kHz, MCLK=64xfs
++ { .size = 2, .data = "\x00\x60" },
++ // Bank switch and eq control (0x50): no bank switching
++ { .size = 5, .data = "\x50\x00\x00\x00\x00" },
++ // Volume registers (0x07, 0x08, 0x09, 0x0A)
++ { .size = 2, .data = "\x07\x20" },
++ { .size = 2, .data = "\x08\x30" },
++ { .size = 2, .data = "\x09\x30" },
++ { .size = 2, .data = "\x0A\xFF" },
++ // 0x72, 0x73, 0x76, 0x77 input mixer:
++ // no intermix between channels
++ { .size = 5, .data = "\x72\x00\x00\x00\x00" },
++ { .size = 5, .data = "\x73\x00\x80\x00\x00" },
++ { .size = 5, .data = "\x76\x00\x00\x00\x00" },
++ { .size = 5, .data = "\x77\x00\x80\x00\x00" },
++ // 0x70, 0x71, 0x74, 0x75 inline DRC mixer:
++ // no inline DRC inmix
++ { .size = 5, .data = "\x70\x00\x80\x00\x00" },
++ { .size = 5, .data = "\x71\x00\x00\x00\x00" },
++ { .size = 5, .data = "\x74\x00\x80\x00\x00" },
++ { .size = 5, .data = "\x75\x00\x00\x00\x00" },
++ // 0x56, 0x57 Output scale
++ { .size = 5, .data = "\x56\x00\x80\x00\x00" },
++ { .size = 5, .data = "\x57\x00\x02\x00\x00" },
++ // 0x3B, 0x3c
++ { .size = 9, .data = "\x3B\x00\x08\x00\x00\x00\x78\x00\x00" },
++ { .size = 9, .data = "\x3C\x00\x00\x01\x00\xFF\xFF\xFF\x00" },
++ { .size = 9, .data = "\x3E\x00\x08\x00\x00\x00\x78\x00\x00" },
++ { .size = 9, .data = "\x3F\x00\x00\x01\x00\xFF\xFF\xFF\x00" },
++ { .size = 9, .data = "\x40\x00\x00\x01\x00\xFF\xFF\xFF\x00" },
++ { .size = 9, .data = "\x43\x00\x00\x01\x00\xFF\xFF\xFF\x00" },
++ // 0x51, 0x52: output mixer
++ { .size = 9, .data = "\x51\x00\x80\x00\x00\x00\x00\x00\x00" },
++ { .size = 9, .data = "\x52\x00\x80\x00\x00\x00\x00\x00\x00" },
++ // PEQ defaults
++ { .size = 21, .data = "\x29\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
++ { .size = 21, .data = "\x2A\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
++ { .size = 21, .data = "\x2B\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
++ { .size = 21, .data = "\x2C\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
++ { .size = 21, .data = "\x2D\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
++ { .size = 21, .data = "\x2E\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
++ { .size = 21, .data = "\x2F\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
++ { .size = 21, .data = "\x30\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
++ { .size = 21, .data = "\x31\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
++ { .size = 21, .data = "\x32\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
++ { .size = 21, .data = "\x33\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
++ { .size = 21, .data = "\x34\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
++ { .size = 21, .data = "\x35\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
++ { .size = 21, .data = "\x36\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
++ { .size = 21, .data = "\x58\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
++ { .size = 21, .data = "\x59\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
++ { .size = 21, .data = "\x5C\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
++ { .size = 21, .data = "\x5D\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
++ { .size = 21, .data = "\x5E\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
++ { .size = 21, .data = "\x5F\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
++ { .size = 21, .data = "\x5A\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
++ { .size = 21, .data = "\x5B\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
++};
++
++
++#endif /* _TAS5713_H */
+diff -Nur linux-4.1.3/sound/soc/codecs/wm8804.c linux-xbian-rpi/sound/soc/codecs/wm8804.c
+--- linux-4.1.3/sound/soc/codecs/wm8804.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-rpi/sound/soc/codecs/wm8804.c 2015-07-28 01:20:58.465085369 +0200
+@@ -304,6 +304,7 @@
+ blen = 0x1;
+ break;
+ case 24:
++ case 32:
+ blen = 0x2;
+ break;
+ default:
+@@ -515,7 +516,7 @@
+ };
+
+ #define WM8804_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
+- SNDRV_PCM_FMTBIT_S24_LE)
++ SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
+
+ #define WM8804_RATES (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
+ SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 | \
+@@ -543,7 +544,7 @@
+ };
+
+ static const struct snd_soc_codec_driver soc_codec_dev_wm8804 = {
+- .idle_bias_off = true,
++ .idle_bias_off = false,
+
+ .dapm_widgets = wm8804_dapm_widgets,
+ .num_dapm_widgets = ARRAY_SIZE(wm8804_dapm_widgets),
diff --git a/target/arm/solidrun-imx6/patches/4.1.3/0001-xbian.patch b/target/arm/solidrun-imx6/patches/4.1.3/0001-xbian.patch
new file mode 100644
index 000000000..6286c0868
--- /dev/null
+++ b/target/arm/solidrun-imx6/patches/4.1.3/0001-xbian.patch
@@ -0,0 +1,171697 @@
+diff -Nur linux-4.1.3/arch/arm/boot/dts/imx6dl.dtsi linux-xbian-imx6/arch/arm/boot/dts/imx6dl.dtsi
+--- linux-4.1.3/arch/arm/boot/dts/imx6dl.dtsi 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/arch/arm/boot/dts/imx6dl.dtsi 2015-07-27 23:13:00.299912248 +0200
+@@ -60,17 +60,103 @@
+ };
+
+ soc {
+- ocram: sram@00900000 {
++ busfreq { /* BUSFREQ */
++ compatible = "fsl,imx6_busfreq";
++ clocks = <&clks 171>, <&clks 6>, <&clks 11>, <&clks 104>, <&clks 172>, <&clks 58>,
++ <&clks 18>, <&clks 60>, <&clks 20>, <&clks 3>, <&clks 22> , <&clks 8>;
++ clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", "pll3_usb_otg", "periph",
++ "periph_pre", "periph_clk2", "periph_clk2_sel", "osc", "axi_sel", "pll3_pfd1_540m";
++ interrupts = <0 107 0x04>, <0 112 0x4>;
++ interrupt-names = "irq_busfreq_0", "irq_busfreq_1";
++ fsl,max_ddr_freq = <400000000>;
++ };
++
++ gpu@00130000 {
++ compatible = "fsl,imx6dl-gpu", "fsl,imx6q-gpu";
++ reg = <0x00130000 0x4000>, <0x00134000 0x4000>,
++ <0x0 0x0>;
++ reg-names = "iobase_3d", "iobase_2d",
++ "phys_baseaddr";
++ interrupts = <0 9 0x04>, <0 10 0x04>;
++ interrupt-names = "irq_3d", "irq_2d";
++ clocks = <&clks 26>, <&clks 27>,
++ <&clks 121>, <&clks 122>,
++ <&clks 74>;
++ clock-names = "gpu2d_axi_clk", "gpu3d_axi_clk",
++ "gpu2d_clk", "gpu3d_clk",
++ "gpu3d_shader_clk";
++ resets = <&src 0>, <&src 3>;
++ reset-names = "gpu3d", "gpu2d";
++ power-domains = <&gpc 1>;
++ };
++
++ hdmi_core: hdmi_core@00120000 {
++ compatible = "fsl,imx6q-hdmi-core";
++ reg = <0x00120000 0x9000>;
++ clocks = <&clks 124>, <&clks 123>;
++ clock-names = "hdmi_isfr", "hdmi_iahb";
++ status = "disabled";
++ };
++
++ hdmi_video: hdmi_video@020e0000 {
++ compatible = "fsl,imx6q-hdmi-video";
++ reg = <0x020e0000 0x1000>;
++ reg-names = "hdmi_gpr";
++ interrupts = <0 115 0x04>;
++ clocks = <&clks 124>, <&clks 123>;
++ clock-names = "hdmi_isfr", "hdmi_iahb";
++ status = "disabled";
++ };
++
++ hdmi_audio: hdmi_audio@00120000 {
++ compatible = "fsl,imx6q-hdmi-audio";
++ clocks = <&clks 124>, <&clks 123>;
++ clock-names = "hdmi_isfr", "hdmi_iahb";
++ dmas = <&sdma 2 23 0>;
++ dma-names = "tx";
++ status = "disabled";
++ };
++
++ hdmi_cec: hdmi_cec@00120000 {
++ compatible = "fsl,imx6q-hdmi-cec";
++ interrupts = <0 115 0x04>;
++ status = "disabled";
++ };
++
++ ocrams: sram@00900000 {
++ compatible = "fsl,lpm-sram";
++ reg = <0x00900000 0x4000>;
++ clocks = <&clks IMX6QDL_CLK_OCRAM>;
++ };
++
++ ocrams_ddr: sram@00904000 {
++ compatible = "fsl,ddr-lpm-sram";
++ reg = <0x00904000 0x1000>;
++ clocks = <&clks IMX6QDL_CLK_OCRAM>;
++ };
++
++ ocram: sram@00905000 {
+ compatible = "mmio-sram";
+- reg = <0x00900000 0x20000>;
++ reg = <0x00905000 0x1B000>;
+ clocks = <&clks IMX6QDL_CLK_OCRAM>;
+ };
+
+ aips1: aips-bus@02000000 {
++ vpu@02040000 {
++ iramsize = <0>;
++ status = "okay";
++ };
++
+ iomuxc: iomuxc@020e0000 {
+ compatible = "fsl,imx6dl-iomuxc";
+ };
+
++ dcic2: dcic@020e8000 {
++ clocks = <&clks IMX6QDL_CLK_DCIC1 >,
++ <&clks IMX6QDL_CLK_DCIC2>; /* DCIC2 depend on DCIC1 clock in imx6dl*/
++ clock-names = "dcic", "disp-axi";
++ };
++
+ pxp: pxp@020f0000 {
+ reg = <0x020f0000 0x4000>;
+ interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
+@@ -99,26 +185,13 @@
+ };
+ };
+ };
+-
+- display-subsystem {
+- compatible = "fsl,imx-display-subsystem";
+- ports = <&ipu1_di0>, <&ipu1_di1>;
+- };
+-};
+-
+-&hdmi {
+- compatible = "fsl,imx6dl-hdmi";
+ };
+
+ &ldb {
+- clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
+- <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
+- <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
++ clocks = <&clks 33>, <&clks 34>,
++ <&clks 39>, <&clks 40>,
++ <&clks 135>, <&clks 136>;
+ clock-names = "di0_pll", "di1_pll",
+ "di0_sel", "di1_sel",
+ "di0", "di1";
+ };
+-
+-&vpu {
+- compatible = "fsl,imx6dl-vpu", "cnm,coda960";
+-};
+diff -Nur linux-4.1.3/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi linux-xbian-imx6/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi
+--- linux-4.1.3/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi 2015-07-27 23:13:00.303898027 +0200
+@@ -45,11 +45,22 @@
+ #include <dt-bindings/gpio/gpio.h>
+
+ / {
++ chosen {
++ bootargs = "quiet console=ttymxc0,115200 root=/dev/mmcblk0p2 rw";
++ };
++
++ aliases {
++ mmc0 = &usdhc2;
++ mmc1 = &usdhc1;
++ mxcfb0 = &mxcfb1;
++ };
++
+ ir_recv: ir-receiver {
+ compatible = "gpio-ir-receiver";
+ gpios = <&gpio3 9 1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_cubox_i_ir>;
++ linux,rc-map-name = "rc-rc6-mce";
+ };
+
+ pwmleds {
+@@ -78,6 +89,8 @@
+
+ reg_usbh1_vbus: usb-h1-vbus {
+ compatible = "regulator-fixed";
++ regulator-boot-on;
++ regulator-always-on;
+ enable-active-high;
+ gpio = <&gpio1 0 0>;
+ pinctrl-names = "default";
+@@ -89,6 +102,8 @@
+
+ reg_usbotg_vbus: usb-otg-vbus {
+ compatible = "regulator-fixed";
++ regulator-boot-on;
++ regulator-always-on;
+ enable-active-high;
+ gpio = <&gpio3 22 0>;
+ pinctrl-names = "default";
+@@ -101,8 +116,7 @@
+
+ sound-spdif {
+ compatible = "fsl,imx-audio-spdif";
+- model = "Integrated SPDIF";
+- /* IMX6 doesn't implement this yet */
++ model = "imx-spdif";
+ spdif-controller = <&spdif>;
+ spdif-out;
+ };
+@@ -118,12 +132,45 @@
+ linux,code = <BTN_0>;
+ };
+ };
++
++ sound-hdmi {
++ compatible = "fsl,imx6q-audio-hdmi",
++ "fsl,imx-audio-hdmi";
++ model = "imx-audio-hdmi";
++ hdmi-controller = <&hdmi_audio>;
++ };
++
++ mxcfb1: fb@0 {
++ compatible = "fsl,mxc_sdc_fb";
++ disp_dev = "hdmi";
++ interface_pix_fmt = "RGB24";
++ mode_str ="1920x1080M@60";
++ default_bpp = <32>;
++ int_clk = <0>;
++ late_init = <0>;
++ status = "okay";
++ };
++};
++
++&hdmi_core {
++ ipu_id = <0>;
++ disp_id = <0>;
++ status = "okay";
++};
++
++&hdmi_video {
++ fsl,phy_reg_vlev = <0x0294>;
++ fsl,phy_reg_cksymtx = <0x800d>;
++ status = "okay";
++};
++
++&hdmi_audio {
++ status = "okay";
+ };
+
+-&hdmi {
++&hdmi_cec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_cubox_i_hdmi>;
+- ddc-i2c-bus = <&i2c2>;
+ status = "okay";
+ };
+
+@@ -131,7 +178,13 @@
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_cubox_i_i2c2>;
++
+ status = "okay";
++
++ ddc: imx6_hdmi_i2c@50 {
++ compatible = "fsl,imx6-hdmi-i2c";
++ reg = <0x50>;
++ };
+ };
+
+ &i2c3 {
+@@ -228,6 +281,28 @@
+ MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x17059
+ >;
+ };
++
++ pinctrl_cubox_i_usdhc2_100mhz: cubox-i-usdhc2-100mhz {
++ fsl,pins = <
++ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9
++ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9
++ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
++ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
++ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
++ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x130b9
++ >;
++ };
++
++ pinctrl_cubox_i_usdhc2_200mhz: cubox-i-usdhc2-200mhz {
++ fsl,pins = <
++ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9
++ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9
++ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9
++ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9
++ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9
++ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x130f9
++ >;
++ };
+ };
+ };
+
+@@ -256,9 +331,24 @@
+ };
+
+ &usdhc2 {
+- pinctrl-names = "default";
++ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_cubox_i_usdhc2_aux &pinctrl_cubox_i_usdhc2>;
++ pinctrl-1 = <&pinctrl_cubox_i_usdhc2_aux &pinctrl_cubox_i_usdhc2_100mhz>;
++ pinctrl-2 = <&pinctrl_cubox_i_usdhc2_aux &pinctrl_cubox_i_usdhc2_200mhz>;
+ vmmc-supply = <&reg_3p3v>;
+ cd-gpios = <&gpio1 4 0>;
+ status = "okay";
++ no-1-8-v;
++};
++
++&dcic1 {
++ dcic_id = <0>;
++ dcic_mux = "dcic-hdmi";
++ status = "okay";
++};
++
++&dcic2 {
++ dcic_id = <1>;
++ dcic_mux = "dcic-lvds1";
++ status = "okay";
+ };
+diff -Nur linux-4.1.3/arch/arm/boot/dts/imx6qdl.dtsi linux-xbian-imx6/arch/arm/boot/dts/imx6qdl.dtsi
+--- linux-4.1.3/arch/arm/boot/dts/imx6qdl.dtsi 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/arch/arm/boot/dts/imx6qdl.dtsi 2015-07-27 23:13:00.303898027 +0200
+@@ -14,6 +14,7 @@
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ #include "skeleton.dtsi"
++#include <dt-bindings/gpio/gpio.h>
+
+ / {
+ aliases {
+@@ -30,6 +31,7 @@
+ i2c0 = &i2c1;
+ i2c1 = &i2c2;
+ i2c2 = &i2c3;
++ ipu0 = &ipu1;
+ mmc0 = &usdhc1;
+ mmc1 = &usdhc2;
+ mmc2 = &usdhc3;
+@@ -79,6 +81,10 @@
+ };
+ };
+
++ pu_dummy: pudummy_reg {
++ compatible = "fsl,imx6-dummy-pureg"; /* only used in ldo-bypass */
++ };
++
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+@@ -86,6 +92,11 @@
+ interrupt-parent = <&gpc>;
+ ranges;
+
++ caam_sm: caam-sm@00100000 {
++ compatible = "fsl,imx6q-caam-sm";
++ reg = <0x00100000 0x3fff>;
++ };
++
+ dma_apbh: dma-apbh@00110000 {
+ compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
+ reg = <0x00110000 0x2000>;
+@@ -99,6 +110,12 @@
+ clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
+ };
+
++ irq_sec_vio: caam_secvio {
++ compatible = "fsl,imx6q-caam-secvio";
++ interrupts = <0 20 0x04>;
++ secvio_src = <0x8000001d>;
++ };
++
+ gpmi: gpmi-nand@00112000 {
+ compatible = "fsl,imx6q-gpmi-nand";
+ #address-cells = <1>;
+@@ -190,16 +207,16 @@
+ dmas = <&sdma 14 18 0>,
+ <&sdma 15 18 0>;
+ dma-names = "rx", "tx";
+- clocks = <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_OSC>,
+- <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_DUMMY>,
+- <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_DUMMY>,
+- <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_DUMMY>,
+- <&clks IMX6QDL_CLK_DUMMY>;
++ clocks = <&clks IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>,
++ <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_ASRC>,
++ <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_ESAI_EXTAL>,
++ <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_MLB>,
++ <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_SPBA>;
+ clock-names = "core", "rxtx0",
+ "rxtx1", "rxtx2",
+ "rxtx3", "rxtx4",
+ "rxtx5", "rxtx6",
+- "rxtx7";
++ "rxtx7", "dma";
+ status = "disabled";
+ };
+
+@@ -274,7 +291,12 @@
+ esai: esai@02024000 {
+ reg = <0x02024000 0x4000>;
+ interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
+- };
++ compatible = "fsl,imx6q-esai";
++ clocks = <&clks 118>;
++ fsl,esai-dma-events = <24 23>;
++ fsl,flags = <1>;
++ status = "disabled";
++ };
+
+ ssi1: ssi@02028000 {
+ #sound-dai-cells = <0>;
+@@ -325,8 +347,30 @@
+ };
+
+ asrc: asrc@02034000 {
++ compatible = "fsl,imx53-asrc";
+ reg = <0x02034000 0x4000>;
+ interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6QDL_CLK_ASRC_MEM>,
++ <&clks IMX6QDL_CLK_ASRC_IPG>,
++ <&clks IMX6QDL_CLK_SPDIF>,
++ <&clks IMX6QDL_CLK_SPBA>;
++ clock-names = "mem", "ipg", "asrck_0", "dma";
++ dmas = <&sdma 17 20 1>, <&sdma 18 20 1>, <&sdma 19 20 1>,
++ <&sdma 20 20 1>, <&sdma 21 20 1>, <&sdma 22 20 1>;
++ dma-names = "rxa", "rxb", "rxc",
++ "txa", "txb", "txc";
++ fsl,asrc-rate = <48000>;
++ fsl,asrc-width = <16>;
++ status = "okay";
++ };
++
++ asrc_p2p: asrc_p2p {
++ compatible = "fsl,imx6q-asrc-p2p";
++ fsl,output-rate = <48000>;
++ fsl,output-width = <16>;
++ fsl,asrc-dma-rx-events = <17 18 19>;
++ fsl,asrc-dma-tx-events = <20 21 22>;
++ status = "okay";
+ };
+
+ spba@0203c000 {
+@@ -335,16 +379,20 @@
+ };
+
+ vpu: vpu@02040000 {
+- compatible = "cnm,coda960";
++ compatible = "cnm,coda960", "fsl,imx6-vpu";
+ reg = <0x02040000 0x3c000>;
++ reg-names = "vpu_regs";
+ interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
+ <0 3 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "bit", "jpeg";
+ clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
+- <&clks IMX6QDL_CLK_MMDC_CH0_AXI>;
+- clock-names = "per", "ahb";
+- resets = <&src 1>;
++ <&clks IMX6QDL_CLK_MMDC_CH0_AXI>,
++ <&clks IMX6QDL_CLK_OCRAM>;
++ clock-names = "per", "ahb", "ocram";
++ iramsize = <0x21000>;
+ iram = <&ocram>;
++ resets = <&src 1>;
++ power-domains = <&gpc 1>;
+ };
+
+ aipstz@0207c000 { /* AIPSTZ1 */
+@@ -552,20 +600,21 @@
+ anatop-min-bit-val = <4>;
+ anatop-min-voltage = <800000>;
+ anatop-max-voltage = <1375000>;
++ anatop-enable-bit = <0>;
+ };
+
+- regulator-3p0@120 {
++ reg_3p0: regulator-3p0@120 {
+ compatible = "fsl,anatop-regulator";
+ regulator-name = "vdd3p0";
+- regulator-min-microvolt = <2800000>;
+- regulator-max-microvolt = <3150000>;
+- regulator-always-on;
++ regulator-min-microvolt = <2625000>;
++ regulator-max-microvolt = <3400000>;
+ anatop-reg-offset = <0x120>;
+ anatop-vol-bit-shift = <8>;
+ anatop-vol-bit-width = <5>;
+ anatop-min-bit-val = <0>;
+ anatop-min-voltage = <2625000>;
+ anatop-max-voltage = <3400000>;
++ anatop-enable-bit = <0>;
+ };
+
+ regulator-2p5@130 {
+@@ -580,6 +629,7 @@
+ anatop-min-bit-val = <0>;
+ anatop-min-voltage = <2000000>;
+ anatop-max-voltage = <2750000>;
++ anatop-enable-bit = <0>;
+ };
+
+ reg_arm: regulator-vddcore@140 {
+@@ -647,6 +697,7 @@
+ reg = <0x020c9000 0x1000>;
+ interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_USBPHY1>;
++ phy-3p0-supply = <&reg_3p0>;
+ fsl,anatop = <&anatop>;
+ };
+
+@@ -655,9 +706,15 @@
+ reg = <0x020ca000 0x1000>;
+ interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_USBPHY2>;
++ phy-3p0-supply = <&reg_3p0>;
+ fsl,anatop = <&anatop>;
+ };
+
++ caam_snvs: caam-snvs@020cc000 {
++ compatible = "fsl,imx6q-caam-snvs";
++ reg = <0x020cc000 0x4000>;
++ };
++
+ snvs@020cc000 {
+ compatible = "fsl,sec-v4.0-mon", "simple-bus";
+ #address-cells = <1>;
+@@ -704,14 +761,12 @@
+ interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
+ <0 90 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&intc>;
+- pu-supply = <&reg_pu>;
+- clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
+- <&clks IMX6QDL_CLK_GPU3D_SHADER>,
+- <&clks IMX6QDL_CLK_GPU2D_CORE>,
+- <&clks IMX6QDL_CLK_GPU2D_AXI>,
+- <&clks IMX6QDL_CLK_OPENVG_AXI>,
+- <&clks IMX6QDL_CLK_VPU_AXI>;
+ #power-domain-cells = <1>;
++ clocks = <&clks 122>, <&clks 74>, <&clks 121>,
++ <&clks 26>, <&clks 143>, <&clks 168>;
++ clock-names = "gpu3d_core", "gpu3d_shader", "gpu2d_core",
++ "gpu2d_axi", "openvg_axi", "vpu_axi";
++ pu-supply = <&reg_pu>;
+ };
+
+ gpr: iomuxc-gpr@020e0000 {
+@@ -736,22 +791,6 @@
+ #size-cells = <0>;
+ reg = <0>;
+ status = "disabled";
+-
+- port@0 {
+- reg = <0>;
+-
+- lvds0_mux_0: endpoint {
+- remote-endpoint = <&ipu1_di0_lvds0>;
+- };
+- };
+-
+- port@1 {
+- reg = <1>;
+-
+- lvds0_mux_1: endpoint {
+- remote-endpoint = <&ipu1_di1_lvds0>;
+- };
+- };
+ };
+
+ lvds-channel@1 {
+@@ -759,22 +798,6 @@
+ #size-cells = <0>;
+ reg = <1>;
+ status = "disabled";
+-
+- port@0 {
+- reg = <0>;
+-
+- lvds1_mux_0: endpoint {
+- remote-endpoint = <&ipu1_di0_lvds1>;
+- };
+- };
+-
+- port@1 {
+- reg = <1>;
+-
+- lvds1_mux_1: endpoint {
+- remote-endpoint = <&ipu1_di1_lvds1>;
+- };
+- };
+ };
+ };
+
+@@ -788,32 +811,26 @@
+ <&clks IMX6QDL_CLK_HDMI_ISFR>;
+ clock-names = "iahb", "isfr";
+ status = "disabled";
+-
+- port@0 {
+- reg = <0>;
+-
+- hdmi_mux_0: endpoint {
+- remote-endpoint = <&ipu1_di0_hdmi>;
+- };
+- };
+-
+- port@1 {
+- reg = <1>;
+-
+- hdmi_mux_1: endpoint {
+- remote-endpoint = <&ipu1_di1_hdmi>;
+- };
+- };
+ };
+
+ dcic1: dcic@020e4000 {
++ compatible = "fsl,imx6q-dcic";
+ reg = <0x020e4000 0x4000>;
+ interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6QDL_CLK_DCIC1>, <&clks IMX6QDL_CLK_DCIC1>;
++ clock-names = "dcic", "disp-axi";
++ gpr = <&gpr>;
++ status = "disabled";
+ };
+
+ dcic2: dcic@020e8000 {
++ compatible = "fsl,imx6q-dcic";
+ reg = <0x020e8000 0x4000>;
+ interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6QDL_CLK_DCIC2>, <&clks IMX6QDL_CLK_DCIC2>;
++ clock-names = "dcic", "disp-axi";
++ gpr = <&gpr>;
++ status = "disabled";
+ };
+
+ sdma: sdma@020ec000 {
+@@ -824,6 +841,7 @@
+ <&clks IMX6QDL_CLK_SDMA>;
+ clock-names = "ipg", "ahb";
+ #dma-cells = <3>;
++ iram = <&ocram>;
+ fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
+ };
+ };
+@@ -835,10 +853,30 @@
+ reg = <0x02100000 0x100000>;
+ ranges;
+
+- caam@02100000 {
+- reg = <0x02100000 0x40000>;
+- interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>,
+- <0 106 IRQ_TYPE_LEVEL_HIGH>;
++ crypto: caam@2100000 {
++ compatible = "fsl,sec-v4.0";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ reg = <0x2100000 0x40000>;
++ ranges = <0 0x2100000 0x40000>;
++ interrupt-parent = <&intc>; /* interrupts = <0 92 0x4>; */
++ interrupts = <0 92 0x4>;
++ clocks = <&clks 213>, <&clks 214>, <&clks 215> ,<&clks 196>;
++ clock-names = "caam_mem", "caam_aclk", "caam_ipg", "caam_emi_slow";
++
++ sec_jr0: jr0@1000 {
++ compatible = "fsl,sec-v4.0-job-ring";
++ reg = <0x1000 0x1000>;
++ interrupt-parent = <&intc>;
++ interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
++ };
++
++ sec_jr1: jr1@2000 {
++ compatible = "fsl,sec-v4.0-job-ring";
++ reg = <0x2000 0x1000>;
++ interrupt-parent = <&intc>;
++ interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
++ };
+ };
+
+ aipstz@0217c000 { /* AIPSTZ2 */
+@@ -852,6 +890,7 @@
+ clocks = <&clks IMX6QDL_CLK_USBOH3>;
+ fsl,usbphy = <&usbphy1>;
+ fsl,usbmisc = <&usbmisc 0>;
++ fsl,anatop = <&anatop>;
+ status = "disabled";
+ };
+
+@@ -903,14 +942,21 @@
+ <&clks IMX6QDL_CLK_ENET>,
+ <&clks IMX6QDL_CLK_ENET_REF>;
+ clock-names = "ipg", "ahb", "ptp";
+- status = "disabled";
++ phy-mode = "rgmii";
++ fsl,magic-packet;
++ status = "okay";
+ };
+
+- mlb@0218c000 {
++ mlb: mlb@0218c000 {
+ reg = <0x0218c000 0x4000>;
+ interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
+ <0 117 IRQ_TYPE_LEVEL_HIGH>,
+ <0 126 IRQ_TYPE_LEVEL_HIGH>;
++ compatible = "fsl,imx6q-mlb150";
++ clocks = <&clks 139>, <&clks 175>;
++ clock-names = "mlb", "pll8_mlb";
++ iram = <&ocram>;
++ status = "disabled";
+ };
+
+ usdhc1: usdhc@02190000 {
+@@ -995,6 +1041,11 @@
+ reg = <0x021ac000 0x4000>;
+ };
+
++ mmdc0-1@021b0000 {
++ compatible = "fsl,imx6q-mmdc-combine";
++ reg = <0x021b0000 0x8000>;
++ };
++
+ mmdc0: mmdc@021b0000 { /* MMDC0 */
+ compatible = "fsl,imx6q-mmdc";
+ reg = <0x021b0000 0x4000>;
+@@ -1011,11 +1062,17 @@
+ clocks = <&clks IMX6QDL_CLK_EIM_SLOW>;
+ };
+
+- ocotp: ocotp@021bc000 {
+- compatible = "fsl,imx6q-ocotp", "syscon";
++ ocotp: ocotp-ctrl@021bc000 {
++ compatible = "syscon";
+ reg = <0x021bc000 0x4000>;
+ };
+
++ ocotp-fuse@021bc000 {
++ compatible = "fsl,imx6q-ocotp";
++ reg = <0x021bc000 0x4000>;
++ clocks = <&clks 128>;
++ };
++
+ tzasc@021d0000 { /* TZASC1 */
+ reg = <0x021d0000 0x4000>;
+ interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
+@@ -1034,39 +1091,38 @@
+
+ mipi_csi: mipi@021dc000 {
+ reg = <0x021dc000 0x4000>;
++ compatible = "fsl,imx6q-mipi-csi2";
++ interrupts = <0 100 0x04>, <0 101 0x04>;
++ clocks = <&clks IMX6QDL_CLK_HSI_TX>,
++ <&clks IMX6QDL_CLK_EIM_SEL>,
++ <&clks IMX6QDL_CLK_LVDS2_IN>;
++ /* Note: clks 138 is hsi_tx, however, the dphy_c
++ * hsi_tx and pll_refclk use the same clk gate.
++ * In current clk driver, open/close clk gate do
++ * use hsi_tx for a temporary debug purpose.
++ */
++ clock-names = "dphy_clk", "pixel_clk", "cfg_clk";
++ status = "disabled";
+ };
+
+ mipi_dsi: mipi@021e0000 {
++ compatible = "fsl,imx6q-mipi-dsi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x021e0000 0x4000>;
+ status = "disabled";
+-
+- ports {
+- #address-cells = <1>;
+- #size-cells = <0>;
+-
+- port@0 {
+- reg = <0>;
+-
+- mipi_mux_0: endpoint {
+- remote-endpoint = <&ipu1_di0_mipi>;
+- };
+- };
+-
+- port@1 {
+- reg = <1>;
+-
+- mipi_mux_1: endpoint {
+- remote-endpoint = <&ipu1_di1_mipi>;
+- };
+- };
+- };
++ interrupts = <0 102 0x04>;
++ gpr = <&gpr>;
++ clocks = <&clks IMX6QDL_CLK_HSI_TX>, <&clks IMX6QDL_CLK_VIDEO_27M>;
++ clock-names = "mipi_pllref_clk", "mipi_cfg_clk";
+ };
+
+ vdoa@021e4000 {
++ compatible = "fsl,imx6q-vdoa";
+ reg = <0x021e4000 0x4000>;
+ interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks 202>;
++ iram = <&ocram>;
+ };
+
+ uart2: serial@021e8000 {
+@@ -1127,67 +1183,14 @@
+ <0 5 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_IPU1>,
+ <&clks IMX6QDL_CLK_IPU1_DI0>,
+- <&clks IMX6QDL_CLK_IPU1_DI1>;
+- clock-names = "bus", "di0", "di1";
++ <&clks IMX6QDL_CLK_IPU1_DI1>,
++ <&clks 39>, <&clks 40>,
++ <&clks 135>, <&clks 136>;
++ clock-names = "bus", "di0", "di1",
++ "di0_sel", "di1_sel",
++ "ldb_di0", "ldb_di1";
+ resets = <&src 2>;
+-
+- ipu1_csi0: port@0 {
+- reg = <0>;
+- };
+-
+- ipu1_csi1: port@1 {
+- reg = <1>;
+- };
+-
+- ipu1_di0: port@2 {
+- #address-cells = <1>;
+- #size-cells = <0>;
+- reg = <2>;
+-
+- ipu1_di0_disp0: endpoint@0 {
+- };
+-
+- ipu1_di0_hdmi: endpoint@1 {
+- remote-endpoint = <&hdmi_mux_0>;
+- };
+-
+- ipu1_di0_mipi: endpoint@2 {
+- remote-endpoint = <&mipi_mux_0>;
+- };
+-
+- ipu1_di0_lvds0: endpoint@3 {
+- remote-endpoint = <&lvds0_mux_0>;
+- };
+-
+- ipu1_di0_lvds1: endpoint@4 {
+- remote-endpoint = <&lvds1_mux_0>;
+- };
+- };
+-
+- ipu1_di1: port@3 {
+- #address-cells = <1>;
+- #size-cells = <0>;
+- reg = <3>;
+-
+- ipu1_di0_disp1: endpoint@0 {
+- };
+-
+- ipu1_di1_hdmi: endpoint@1 {
+- remote-endpoint = <&hdmi_mux_1>;
+- };
+-
+- ipu1_di1_mipi: endpoint@2 {
+- remote-endpoint = <&mipi_mux_1>;
+- };
+-
+- ipu1_di1_lvds0: endpoint@3 {
+- remote-endpoint = <&lvds0_mux_1>;
+- };
+-
+- ipu1_di1_lvds1: endpoint@4 {
+- remote-endpoint = <&lvds1_mux_1>;
+- };
+- };
++ bypass_reset = <0>;
+ };
+ };
+ };
+diff -Nur linux-4.1.3/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi linux-xbian-imx6/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi
+--- linux-4.1.3/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi 2015-07-27 23:13:00.303898027 +0200
+@@ -43,8 +43,10 @@
+ #include "imx6qdl-microsom-ar8035.dtsi"
+
+ / {
+- chosen {
+- stdout-path = &uart1;
++ aliases {
++ mmc0 = &usdhc2;
++ mmc1 = &usdhc1;
++ mxcfb0 = &mxcfb1;
+ };
+
+ ir_recv: ir-receiver {
+@@ -52,6 +54,7 @@
+ gpios = <&gpio3 5 1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hummingboard_gpio3_5>;
++ linux,rc-map-name = "rc-rc6-mce";
+ };
+
+ regulators {
+@@ -98,32 +101,70 @@
+ model = "On-board Codec";
+ mux-ext-port = <5>;
+ mux-int-port = <1>;
++ cpu-dai = <&ssi1>;
+ ssi-controller = <&ssi1>;
+ };
+
+ sound-spdif {
+ compatible = "fsl,imx-audio-spdif";
+- model = "On-board SPDIF";
++ model = "imx-spdif";
+ /* IMX6 doesn't implement this yet */
+ spdif-controller = <&spdif>;
+ spdif-out;
+ };
++
++ sound-hdmi {
++ compatible = "fsl,imx6q-audio-hdmi",
++ "fsl,imx-audio-hdmi";
++ model = "imx-audio-hdmi";
++ hdmi-controller = <&hdmi_audio>;
++ };
++
++ mxcfb1: fb@0 {
++ compatible = "fsl,mxc_sdc_fb";
++ disp_dev = "hdmi";
++ interface_pix_fmt = "RGB24";
++ mode_str ="1920x1080M@60";
++ default_bpp = <32>;
++ int_clk = <0>;
++ late_init = <0>;
++ status = "okay";
++ };
+ };
+
+ &audmux {
+ status = "okay";
+ };
+
+-&can1 {
++/*&can1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hummingboard_flexcan1>;
+ status = "okay";
+ };
++*/
++&hdmi_core {
++ ipu_id = <0>;
++ disp_id = <0>;
++ status = "okay";
++};
++
++&hdmi_video {
++ fsl,phy_reg_vlev = <0x0294>;
++ fsl,phy_reg_cksymtx = <0x800d>;
++ status = "okay";
++};
++
++&hdmi_audio {
++ status = "okay";
++};
++
++&ocram {
++ status = "okay";
++};
+
+-&hdmi {
++&hdmi_cec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hummingboard_hdmi>;
+- ddc-i2c-bus = <&i2c2>;
+ status = "okay";
+ };
+
+@@ -136,6 +177,7 @@
+ rtc: pcf8523@68 {
+ compatible = "nxp,pcf8523";
+ reg = <0x68>;
++ nxp,12p5_pf;
+ };
+
+ /* Pro baseboard model */
+@@ -155,20 +197,57 @@
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hummingboard_i2c2>;
+ status = "okay";
++
++ ddc: imx6_hdmi_i2c@50 {
++ compatible = "fsl,imx6-hdmi-i2c";
++ reg = <0x50>;
++ };
+ };
+
+ &iomuxc {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hog>;
+ hummingboard {
+- pinctrl_hummingboard_flexcan1: hummingboard-flexcan1 {
++ pinctrl_hog: hoggrp {
++ fsl,pins = <
++ /*
++ * 26 pin header GPIO description. The pins.
++ * numbering as following -
++ * GPIO number | GPIO (bank,num) | PIN number
++ * ------------+-----------------+------------
++ * gpio1 | (1,1) | IO7
++ * gpio73 | (3,9) | IO11
++ * gpio72 | (3,8) | IO12
++ * gpio71 | (3,7) | IO13
++ * gpio70 | (3,6) | IO15
++ * gpio194 | (7,2) | IO16
++ * gpio195 | (7,3) | IO18
++ * gpio67 | (3,3) | IO22
++ *
++ * Notice the gpioX and GPIO (Y,Z) mapping forumla :
++ * X = (Y-1) * 32 + Z
++ */
++ MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x400130b1
++ MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x400130b1
++ MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x400130b1
++ MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x400130b1
++ MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x400130b1
++ MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x400130b1
++ MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x400130b1
++ MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x400130b1
++ >;
++ };
++
++/* pinctrl_hummingboard_flexcan1: hummingboard-flexcan1 {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x80000000
+ MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x80000000
+ >;
+ };
+-
++*/
+ pinctrl_hummingboard_gpio3_5: hummingboard-gpio3_5 {
+ fsl,pins = <
+- MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0b1
++ MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x80000000
+ >;
+ };
+
+@@ -198,10 +277,10 @@
+
+ pinctrl_hummingboard_sgtl5000: hummingboard-sgtl5000 {
+ fsl,pins = <
+- MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0
+- MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0
+- MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0
+- MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0
++ MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 /*brk*/
++ MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 /*ok*/
++ MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0 /*brk*/
++ MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 /*ok*/
+ MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0
+ >;
+ };
+@@ -219,7 +298,7 @@
+ * Similar to pinctrl_usbotg_2, but we want it
+ * pulled down for a fixed host connection.
+ */
+- fsl,pins = <MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059>;
++ fsl,pins = <MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x13059>;
+ };
+
+ pinctrl_hummingboard_usbotg_vbus: hummingboard-usbotg-vbus {
+@@ -242,6 +321,13 @@
+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059
+ >;
+ };
++
++ pinctrl_hummingboard_pcie_reset: hummingboard-pcie-reset {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x80000000
++ >;
++ };
++
+ };
+ };
+
+@@ -256,6 +342,14 @@
+ status = "okay";
+ };
+
++&pwm3 {
++ status = "disabled";
++};
++
++&pwm4 {
++ status = "disabled";
++};
++
+ &spdif {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hummingboard_spdif>;
+@@ -291,3 +385,48 @@
+ cd-gpios = <&gpio1 4 0>;
+ status = "okay";
+ };
++
++&gpc {
++ fsl,cpu_pupscr_sw2iso = <0xf>;
++ fsl,cpu_pupscr_sw = <0xf>;
++ fsl,cpu_pdnscr_iso2sw = <0x1>;
++ fsl,cpu_pdnscr_iso = <0x1>;
++ status = "okay";
++};
++
++&pcie {
++ pinctrl-names = "default";
++ pinctrl-0 = <
++ &pinctrl_hummingboard_pcie_reset
++ >;
++ reset-gpio = <&gpio3 4 0>;
++ status = "okay";
++ no-msi;
++};
++
++&ecspi1 {
++ status = "okay";
++ fsl,spi-num-chipselects = <1>;
++};
++
++&ecspi2 {
++ status = "okay";
++ fsl,spi-num-chipselects = <2>;
++};
++
++&ecspi3 {
++ status = "okay";
++ fsl,spi-num-chipselects = <3>;
++};
++
++&dcic1 {
++ dcic_id = <0>;
++ dcic_mux = "dcic-hdmi";
++ status = "okay";
++};
++
++&dcic2 {
++ dcic_id = <1>;
++ dcic_mux = "dcic-lvds1";
++ status = "okay";
++};
+diff -Nur linux-4.1.3/arch/arm/boot/dts/imx6qdl-microsom.dtsi linux-xbian-imx6/arch/arm/boot/dts/imx6qdl-microsom.dtsi
+--- linux-4.1.3/arch/arm/boot/dts/imx6qdl-microsom.dtsi 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/arch/arm/boot/dts/imx6qdl-microsom.dtsi 2015-07-27 23:13:00.303898027 +0200
+@@ -39,15 +39,98 @@
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
++#include <dt-bindings/gpio/gpio.h>
++/ {
++ clk_sdio: sdio-clock {
++ compatible = "gpio-gate-clock";
++ #clock-cells = <0>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_microsom_brcm_osc>;
++ enable-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
++ };
++
++ regulators {
++ compatible = "simple-bus";
++
++ reg_brcm: brcm-reg {
++ compatible = "regulator-fixed";
++ enable-active-high;
++ gpio = <&gpio3 19 0>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_microsom_brcm_reg>;
++ regulator-name = "brcm_reg";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ startup-delay-us = <200000>;
++ };
++ };
++
++ usdhc1_pwrseq: usdhc1_pwrseq {
++ compatible = "mmc-pwrseq-simple";
++ reset-gpios = <&gpio5 26 GPIO_ACTIVE_LOW>,
++ <&gpio6 0 GPIO_ACTIVE_LOW>;
++ clocks = <&clk_sdio>;
++ clock-names = "ext_clock";
++ };
++};
+
+ &iomuxc {
+ microsom {
++ pinctrl_microsom_brcm_bt: microsom-brcm-bt {
++ fsl,pins = <
++ MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x40013070
++ MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 0x40013070
++ MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x40013070
++ >;
++ };
++
++ pinctrl_microsom_brcm_osc: microsom-brcm-osc {
++ fsl,pins = <
++ MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x40013070
++ >;
++ };
++
++ pinctrl_microsom_brcm_reg: microsom-brcm-reg {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x40013070
++ >;
++ };
++
++ pinctrl_microsom_brcm_wifi: microsom-brcm-wifi {
++ fsl,pins = <
++ MX6QDL_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x1b0b0
++ MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x40013070
++ MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x40013070
++ MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x40013070
++ >;
++ };
++
+ pinctrl_microsom_uart1: microsom-uart1 {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
+ MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
+ >;
+ };
++
++ pinctrl_microsom_uart4: microsom-uart4 {
++ fsl,pins = <
++ MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
++ MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
++ MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1
++ MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1
++ >;
++ };
++
++ pinctrl_microsom_usdhc1: microsom-usdhc1 {
++ fsl,pins = <
++ MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
++ MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
++ MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
++ MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
++ MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
++ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
++ >;
++ };
+ };
+ };
+
+@@ -56,3 +139,23 @@
+ pinctrl-0 = <&pinctrl_microsom_uart1>;
+ status = "okay";
+ };
++
++/* UART4 - Connected to optional BRCM Wifi/BT/FM */
++&uart4 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_microsom_brcm_bt &pinctrl_microsom_uart4>;
++ fsl,uart-has-rtscts;
++ status = "okay";
++};
++
++/* USDHC1 - Connected to optional BRCM Wifi/BT/FM */
++&usdhc1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_microsom_brcm_wifi &pinctrl_microsom_usdhc1>;
++ bus-width = <4>;
++ mmc-pwrseq = <&usdhc1_pwrseq>;
++ keep-power-in-suspend;
++ non-removable;
++ vmmc-supply = <&reg_brcm>;
++ status = "okay";
++};
+diff -Nur linux-4.1.3/arch/arm/boot/dts/imx6q.dtsi linux-xbian-imx6/arch/arm/boot/dts/imx6q.dtsi
+--- linux-4.1.3/arch/arm/boot/dts/imx6q.dtsi 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/arch/arm/boot/dts/imx6q.dtsi 2015-07-27 23:13:00.303898027 +0200
+@@ -14,6 +14,7 @@
+
+ / {
+ aliases {
++ ipu1 = &ipu2;
+ spi4 = &ecspi5;
+ };
+
+@@ -47,9 +48,12 @@
+ <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
+ <&clks IMX6QDL_CLK_STEP>,
+ <&clks IMX6QDL_CLK_PLL1_SW>,
+- <&clks IMX6QDL_CLK_PLL1_SYS>;
++ <&clks IMX6QDL_CLK_PLL1_SYS>,
++ <&clks IMX6QDL_PLL1_BYPASS>,
++ <&clks IMX6QDL_CLK_PLL1>,
++ <&clks IMX6QDL_PLL1_BYPASS_SRC> ;
+ clock-names = "arm", "pll2_pfd2_396m", "step",
+- "pll1_sw", "pll1_sys";
++ "pll1_sw", "pll1_sys", "pll1_bypass", "pll1", "pll1_bypass_src";
+ arm-supply = <&reg_arm>;
+ pu-supply = <&reg_pu>;
+ soc-supply = <&reg_soc>;
+@@ -78,9 +82,85 @@
+ };
+
+ soc {
+- ocram: sram@00900000 {
++
++ busfreq { /* BUSFREQ */
++ compatible = "fsl,imx6_busfreq";
++ clocks = <&clks 171>, <&clks 6>, <&clks 11>, <&clks 104>, <&clks 172>, <&clks 58>,
++ <&clks 18>, <&clks 60>, <&clks 20>, <&clks 3>;
++ clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", "pll3_usb_otg", "periph",
++ "periph_pre", "periph_clk2", "periph_clk2_sel", "osc";
++ interrupts = <0 107 0x04>, <0 112 0x4>, <0 113 0x4>, <0 114 0x4>;
++ interrupt-names = "irq_busfreq_0", "irq_busfreq_1", "irq_busfreq_2", "irq_busfreq_3";
++ fsl,max_ddr_freq = <528000000>;
++ };
++
++ gpu@00130000 {
++ compatible = "fsl,imx6q-gpu";
++ reg = <0x00130000 0x4000>, <0x00134000 0x4000>,
++ <0x02204000 0x4000>, <0x0 0x0>;
++ reg-names = "iobase_3d", "iobase_2d",
++ "iobase_vg", "phys_baseaddr";
++ interrupts = <0 9 0x04>, <0 10 0x04>,<0 11 0x04>;
++ interrupt-names = "irq_3d", "irq_2d", "irq_vg";
++ clocks = <&clks 26>, <&clks 143>,
++ <&clks 27>, <&clks 121>,
++ <&clks 122>, <&clks 74>;
++ clock-names = "gpu2d_axi_clk", "openvg_axi_clk",
++ "gpu3d_axi_clk", "gpu2d_clk",
++ "gpu3d_clk", "gpu3d_shader_clk";
++ resets = <&src 0>, <&src 3>, <&src 3>;
++ reset-names = "gpu3d", "gpu2d", "gpuvg";
++ power-domains = <&gpc 1>;
++ };
++
++ hdmi_core: hdmi_core@00120000 {
++ compatible = "fsl,imx6q-hdmi-core";
++ reg = <0x00120000 0x9000>;
++ clocks = <&clks 124>, <&clks 123>;
++ clock-names = "hdmi_isfr", "hdmi_iahb";
++ status = "disabled";
++ };
++
++ hdmi_video: hdmi_video@020e0000 {
++ compatible = "fsl,imx6q-hdmi-video";
++ reg = <0x020e0000 0x1000>;
++ reg-names = "hdmi_gpr";
++ interrupts = <0 115 0x04>;
++ clocks = <&clks 124>, <&clks 123>;
++ clock-names = "hdmi_isfr", "hdmi_iahb";
++ status = "disabled";
++ };
++
++ hdmi_audio: hdmi_audio@00120000 {
++ compatible = "fsl,imx6q-hdmi-audio";
++ clocks = <&clks 124>, <&clks 123>;
++ clock-names = "hdmi_isfr", "hdmi_iahb";
++ dmas = <&sdma 2 23 0>;
++ dma-names = "tx";
++ status = "disabled";
++ };
++
++ hdmi_cec: hdmi_cec@00120000 {
++ compatible = "fsl,imx6q-hdmi-cec";
++ interrupts = <0 115 0x04>;
++ status = "disabled";
++ };
++
++ ocrams: sram@00900000 {
++ compatible = "fsl,lpm-sram";
++ reg = <0x00900000 0x4000>;
++ clocks = <&clks IMX6QDL_CLK_OCRAM>;
++ };
++
++ ocrams_ddr: sram@00904000 {
++ compatible = "fsl,ddr-lpm-sram";
++ reg = <0x00904000 0x1000>;
++ clocks = <&clks IMX6QDL_CLK_OCRAM>;
++ };
++
++ ocram: sram@00905000 {
+ compatible = "mmio-sram";
+- reg = <0x00900000 0x40000>;
++ reg = <0x00905000 0x3B000>;
+ clocks = <&clks IMX6QDL_CLK_OCRAM>;
+ };
+
+@@ -101,6 +181,10 @@
+ };
+ };
+
++ vpu@02040000 {
++ status = "okay";
++ };
++
+ iomuxc: iomuxc@020e0000 {
+ compatible = "fsl,imx6q-iomuxc";
+
+@@ -154,165 +238,33 @@
+ };
+
+ ipu2: ipu@02800000 {
+- #address-cells = <1>;
+- #size-cells = <0>;
+ compatible = "fsl,imx6q-ipu";
+ reg = <0x02800000 0x400000>;
+ interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
+ <0 7 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&clks IMX6QDL_CLK_IPU2>,
+- <&clks IMX6QDL_CLK_IPU2_DI0>,
+- <&clks IMX6QDL_CLK_IPU2_DI1>;
+- clock-names = "bus", "di0", "di1";
++ clocks = <&clks 133>, <&clks 134>, <&clks 137>,
++ <&clks 41>, <&clks 42>,
++ <&clks 135>, <&clks 136>;
++ clock-names = "bus", "di0", "di1",
++ "di0_sel", "di1_sel",
++ "ldb_di0", "ldb_di1";
+ resets = <&src 4>;
+-
+- ipu2_csi0: port@0 {
+- reg = <0>;
+- };
+-
+- ipu2_csi1: port@1 {
+- reg = <1>;
+- };
+-
+- ipu2_di0: port@2 {
+- #address-cells = <1>;
+- #size-cells = <0>;
+- reg = <2>;
+-
+- ipu2_di0_disp0: endpoint@0 {
+- };
+-
+- ipu2_di0_hdmi: endpoint@1 {
+- remote-endpoint = <&hdmi_mux_2>;
+- };
+-
+- ipu2_di0_mipi: endpoint@2 {
+- };
+-
+- ipu2_di0_lvds0: endpoint@3 {
+- remote-endpoint = <&lvds0_mux_2>;
+- };
+-
+- ipu2_di0_lvds1: endpoint@4 {
+- remote-endpoint = <&lvds1_mux_2>;
+- };
+- };
+-
+- ipu2_di1: port@3 {
+- #address-cells = <1>;
+- #size-cells = <0>;
+- reg = <3>;
+-
+- ipu2_di1_hdmi: endpoint@1 {
+- remote-endpoint = <&hdmi_mux_3>;
+- };
+-
+- ipu2_di1_mipi: endpoint@2 {
+- };
+-
+- ipu2_di1_lvds0: endpoint@3 {
+- remote-endpoint = <&lvds0_mux_3>;
+- };
+-
+- ipu2_di1_lvds1: endpoint@4 {
+- remote-endpoint = <&lvds1_mux_3>;
+- };
+- };
+- };
+- };
+-
+- display-subsystem {
+- compatible = "fsl,imx-display-subsystem";
+- ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>;
+- };
+-};
+-
+-&hdmi {
+- compatible = "fsl,imx6q-hdmi";
+-
+- port@2 {
+- reg = <2>;
+-
+- hdmi_mux_2: endpoint {
+- remote-endpoint = <&ipu2_di0_hdmi>;
+- };
+- };
+-
+- port@3 {
+- reg = <3>;
+-
+- hdmi_mux_3: endpoint {
+- remote-endpoint = <&ipu2_di1_hdmi>;
++ bypass_reset = <0>;
+ };
+ };
+ };
+
+ &ldb {
+- clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
++ clocks = <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>,
+ <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
+ <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
+- <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
+- clock-names = "di0_pll", "di1_pll",
+- "di0_sel", "di1_sel", "di2_sel", "di3_sel",
+- "di0", "di1";
+-
+- lvds-channel@0 {
+- port@2 {
+- reg = <2>;
+-
+- lvds0_mux_2: endpoint {
+- remote-endpoint = <&ipu2_di0_lvds0>;
+- };
+- };
+-
+- port@3 {
+- reg = <3>;
+-
+- lvds0_mux_3: endpoint {
+- remote-endpoint = <&ipu2_di1_lvds0>;
+- };
+- };
+- };
+-
+- lvds-channel@1 {
+- port@2 {
+- reg = <2>;
+-
+- lvds1_mux_2: endpoint {
+- remote-endpoint = <&ipu2_di0_lvds1>;
+- };
+- };
+-
+- port@3 {
+- reg = <3>;
+-
+- lvds1_mux_3: endpoint {
+- remote-endpoint = <&ipu2_di1_lvds1>;
+- };
+- };
+- };
+-};
+-
+-&mipi_dsi {
+- ports {
+- port@2 {
+- reg = <2>;
+-
+- mipi_mux_2: endpoint {
+- remote-endpoint = <&ipu2_di0_mipi>;
+- };
+- };
+-
+- port@3 {
+- reg = <3>;
+-
+- mipi_mux_3: endpoint {
+- remote-endpoint = <&ipu2_di1_mipi>;
+- };
+- };
+- };
+-};
+-
+-&vpu {
+- compatible = "fsl,imx6q-vpu", "cnm,coda960";
++ <&clks IMX6QDL_CLK_LDB_DI0_DIV_3_5>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_3_5>,
++ <&clks IMX6QDL_CLK_LDB_DI0_DIV_7>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_7>,
++ <&clks IMX6QDL_CLK_LDB_DI0_DIV_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_SEL>;
++ clock-names = "ldb_di0", "ldb_di1",
++ "di0_sel", "di1_sel",
++ "di2_sel", "di3_sel",
++ "ldb_di0_div_3_5", "ldb_di1_div_3_5",
++ "ldb_di0_div_7", "ldb_di1_div_7",
++ "ldb_di0_div_sel", "ldb_di1_div_sel";
+ };
+diff -Nur linux-4.1.3/arch/arm/boot/dts/imx6q-hummingboard.dts linux-xbian-imx6/arch/arm/boot/dts/imx6q-hummingboard.dts
+--- linux-4.1.3/arch/arm/boot/dts/imx6q-hummingboard.dts 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/arch/arm/boot/dts/imx6q-hummingboard.dts 2015-07-27 23:13:00.303898027 +0200
+@@ -57,3 +57,7 @@
+ fsl,transmit-atten-16ths = <9>;
+ fsl,receive-eq-mdB = <3000>;
+ };
++
++&sgtl5000 {
++ status = "okay";
++};
+diff -Nur linux-4.1.3/arch/arm/boot/dts/imx6sl.dtsi linux-xbian-imx6/arch/arm/boot/dts/imx6sl.dtsi
+--- linux-4.1.3/arch/arm/boot/dts/imx6sl.dtsi 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/arch/arm/boot/dts/imx6sl.dtsi 2015-07-27 23:13:00.307883804 +0200
+@@ -457,20 +457,21 @@
+ anatop-min-bit-val = <4>;
+ anatop-min-voltage = <800000>;
+ anatop-max-voltage = <1375000>;
++ anatop-enable-bit = <0>;
+ };
+
+- regulator-3p0@120 {
++ reg_3p0: regulator-3p0@120 {
+ compatible = "fsl,anatop-regulator";
+ regulator-name = "vdd3p0";
+- regulator-min-microvolt = <2800000>;
+- regulator-max-microvolt = <3150000>;
+- regulator-always-on;
++ regulator-min-microvolt = <2625000>;
++ regulator-max-microvolt = <3400000>;
+ anatop-reg-offset = <0x120>;
+ anatop-vol-bit-shift = <8>;
+ anatop-vol-bit-width = <5>;
+ anatop-min-bit-val = <0>;
+ anatop-min-voltage = <2625000>;
+ anatop-max-voltage = <3400000>;
++ anatop-enable-bit = <0>;
+ };
+
+ regulator-2p5@130 {
+@@ -485,6 +486,7 @@
+ anatop-min-bit-val = <0>;
+ anatop-min-voltage = <2100000>;
+ anatop-max-voltage = <2850000>;
++ anatop-enable-bit = <0>;
+ };
+
+ reg_arm: regulator-vddcore@140 {
+@@ -552,6 +554,7 @@
+ reg = <0x020c9000 0x1000>;
+ interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SL_CLK_USBPHY1>;
++ phy-3p0-supply = <&reg_3p0>;
+ fsl,anatop = <&anatop>;
+ };
+
+@@ -560,6 +563,7 @@
+ reg = <0x020ca000 0x1000>;
+ interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SL_CLK_USBPHY2>;
++ phy-3p0-supply = <&reg_3p0>;
+ fsl,anatop = <&anatop>;
+ };
+
+diff -Nur linux-4.1.3/arch/arm/boot/dts/imx6sx.dtsi linux-xbian-imx6/arch/arm/boot/dts/imx6sx.dtsi
+--- linux-4.1.3/arch/arm/boot/dts/imx6sx.dtsi 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/arch/arm/boot/dts/imx6sx.dtsi 2015-07-27 23:13:00.307883804 +0200
+@@ -556,20 +556,21 @@
+ anatop-min-bit-val = <4>;
+ anatop-min-voltage = <800000>;
+ anatop-max-voltage = <1375000>;
++ anatop-enable-bit = <0>;
+ };
+
+- regulator-3p0@120 {
++ reg_3p0: regulator-3p0@120 {
+ compatible = "fsl,anatop-regulator";
+ regulator-name = "vdd3p0";
+- regulator-min-microvolt = <2800000>;
+- regulator-max-microvolt = <3150000>;
+- regulator-always-on;
++ regulator-min-microvolt = <2625000>;
++ regulator-max-microvolt = <3400000>;
+ anatop-reg-offset = <0x120>;
+ anatop-vol-bit-shift = <8>;
+ anatop-vol-bit-width = <5>;
+ anatop-min-bit-val = <0>;
+ anatop-min-voltage = <2625000>;
+ anatop-max-voltage = <3400000>;
++ anatop-enable-bit = <0>;
+ };
+
+ regulator-2p5@130 {
+@@ -584,6 +585,7 @@
+ anatop-min-bit-val = <0>;
+ anatop-min-voltage = <2100000>;
+ anatop-max-voltage = <2875000>;
++ anatop-enable-bit = <0>;
+ };
+
+ reg_arm: regulator-vddcore@140 {
+@@ -650,6 +652,7 @@
+ reg = <0x020c9000 0x1000>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_USBPHY1>;
++ phy-3p0-supply = <&reg_3p0>;
+ fsl,anatop = <&anatop>;
+ };
+
+@@ -658,6 +661,7 @@
+ reg = <0x020ca000 0x1000>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_USBPHY2>;
++ phy-3p0-supply = <&reg_3p0>;
+ fsl,anatop = <&anatop>;
+ };
+
+diff -Nur linux-4.1.3/arch/arm/include/asm/glue-cache.h linux-xbian-imx6/arch/arm/include/asm/glue-cache.h
+--- linux-4.1.3/arch/arm/include/asm/glue-cache.h 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/arch/arm/include/asm/glue-cache.h 2015-07-27 23:13:00.746319518 +0200
+@@ -102,19 +102,19 @@
+ #endif
+
+ #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K)
+-# ifdef _CACHE
++//# ifdef _CACHE
+ # define MULTI_CACHE 1
+-# else
+-# define _CACHE v6
+-# endif
++//# else
++//# define _CACHE v6
++//# endif
+ #endif
+
+ #if defined(CONFIG_CPU_V7)
+-# ifdef _CACHE
++//# ifdef _CACHE
+ # define MULTI_CACHE 1
+-# else
+-# define _CACHE v7
+-# endif
++//# else
++//# define _CACHE v7
++//# endif
+ #endif
+
+ #if defined(CONFIG_CPU_V7M)
+diff -Nur linux-4.1.3/arch/arm/Kconfig linux-xbian-imx6/arch/arm/Kconfig
+--- linux-4.1.3/arch/arm/Kconfig 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/arch/arm/Kconfig 2015-07-27 23:13:00.128523741 +0200
+@@ -1688,6 +1688,7 @@
+ range 11 64 if ARCH_SHMOBILE_LEGACY
+ default "12" if SOC_AM33XX
+ default "9" if SA1111 || ARCH_EFM32
++ default "14" if ARCH_MXC
+ default "11"
+ help
+ The kernel memory allocator divides physically contiguous memory
+diff -Nur linux-4.1.3/arch/arm/mach-imx/busfreq_ddr3.c linux-xbian-imx6/arch/arm/mach-imx/busfreq_ddr3.c
+--- linux-4.1.3/arch/arm/mach-imx/busfreq_ddr3.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/arch/arm/mach-imx/busfreq_ddr3.c 2015-07-27 23:13:01.073153409 +0200
+@@ -0,0 +1,514 @@
++/*
++ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*!
++ * @file busfreq_ddr3.c
++ *
++ * @brief iMX6 DDR3 frequency change specific file.
++ *
++ * @ingroup PM
++ */
++#define DEBUG
++
++#include <asm/cacheflush.h>
++#include <asm/fncpy.h>
++#include <asm/io.h>
++#include <asm/mach/map.h>
++#include <asm/mach-types.h>
++#include <asm/tlb.h>
++#include <linux/clk.h>
++#include <linux/cpumask.h>
++#include <linux/delay.h>
++#include <linux/genalloc.h>
++#include <linux/interrupt.h>
++#include <linux/irqchip/arm-gic.h>
++#include <linux/kernel.h>
++#include <linux/mutex.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++#include <linux/proc_fs.h>
++#include <linux/sched.h>
++#include <linux/smp.h>
++#include <linux/slab.h>
++
++#include "hardware.h"
++
++/* DDR settings */
++static unsigned long (*iram_ddr_settings)[2];
++static unsigned long (*normal_mmdc_settings)[2];
++static unsigned long (*iram_iomux_settings)[2];
++static void __iomem *mmdc_base;
++static void __iomem *iomux_base;
++static void __iomem *ccm_base;
++static void __iomem *l2_base;
++static void __iomem *gic_dist_base;
++static u32 *irqs_used;
++
++static void *ddr_freq_change_iram_base;
++static int ddr_settings_size;
++static int iomux_settings_size;
++static volatile unsigned int cpus_in_wfe;
++static volatile bool wait_for_ddr_freq_update;
++static int curr_ddr_rate;
++
++void (*mx6_change_ddr_freq)(u32 freq, void *ddr_settings,
++ bool dll_mode, void *iomux_offsets) = NULL;
++
++extern unsigned int ddr_med_rate;
++extern unsigned int ddr_normal_rate;
++extern int low_bus_freq_mode;
++extern int audio_bus_freq_mode;
++extern void mx6_ddr3_freq_change(u32 freq, void *ddr_settings,
++ bool dll_mode, void *iomux_offsets);
++extern unsigned long save_ttbr1(void);
++extern void restore_ttbr1(unsigned long ttbr1);
++
++#ifdef CONFIG_SMP
++extern void __iomem *imx_scu_base;
++static unsigned int online_cpus;
++#endif
++
++#define MIN_DLL_ON_FREQ 333000000
++#define MAX_DLL_OFF_FREQ 125000000
++#define DDR_FREQ_CHANGE_SIZE 0x2000
++
++unsigned long ddr3_dll_mx6q[][2] = {
++ {0x0c, 0x0},
++ {0x10, 0x0},
++ {0x1C, 0x04088032},
++ {0x1C, 0x0408803a},
++ {0x1C, 0x08408030},
++ {0x1C, 0x08408038},
++ {0x818, 0x0},
++};
++
++unsigned long ddr3_calibration[][2] = {
++ {0x83c, 0x0},
++ {0x840, 0x0},
++ {0x483c, 0x0},
++ {0x4840, 0x0},
++ {0x848, 0x0},
++ {0x4848, 0x0},
++ {0x850, 0x0},
++ {0x4850, 0x0},
++};
++
++unsigned long ddr3_dll_mx6dl[][2] = {
++ {0x0c, 0x0},
++ {0x10, 0x0},
++ {0x1C, 0x04008032},
++ {0x1C, 0x0400803a},
++ {0x1C, 0x07208030},
++ {0x1C, 0x07208038},
++ {0x818, 0x0},
++};
++
++unsigned long iomux_offsets_mx6q[][2] = {
++ {0x5A8, 0x0},
++ {0x5B0, 0x0},
++ {0x524, 0x0},
++ {0x51C, 0x0},
++ {0x518, 0x0},
++ {0x50C, 0x0},
++ {0x5B8, 0x0},
++ {0x5C0, 0x0},
++};
++
++unsigned long iomux_offsets_mx6dl[][2] = {
++ {0x4BC, 0x0},
++ {0x4C0, 0x0},
++ {0x4C4, 0x0},
++ {0x4C8, 0x0},
++ {0x4CC, 0x0},
++ {0x4D0, 0x0},
++ {0x4D4, 0x0},
++ {0x4D8, 0x0},
++};
++
++unsigned long ddr3_400[][2] = {
++ {0x83c, 0x42490249},
++ {0x840, 0x02470247},
++ {0x483c, 0x42570257},
++ {0x4840, 0x02400240},
++ {0x848, 0x4039363C},
++ {0x4848, 0x3A39333F},
++ {0x850, 0x38414441},
++ {0x4850, 0x472D4833}
++};
++
++int can_change_ddr_freq(void)
++{
++ return 0;
++}
++
++/*
++ * each active core apart from the one changing
++ * the DDR frequency will execute this function.
++ * the rest of the cores have to remain in WFE
++ * state until the frequency is changed.
++ */
++irqreturn_t wait_in_wfe_irq(int irq, void *dev_id)
++{
++ u32 me = smp_processor_id();
++
++ *((char *)(&cpus_in_wfe) + (u8)me) = 0xff;
++
++ while (wait_for_ddr_freq_update)
++ wfe();
++
++ *((char *)(&cpus_in_wfe) + (u8)me) = 0;
++
++ return IRQ_HANDLED;
++}
++
++/* change the DDR frequency. */
++int update_ddr_freq(int ddr_rate)
++{
++ int i, j;
++ bool dll_off = false;
++ int me = 0;
++ unsigned long ttbr1;
++#ifdef CONFIG_SMP
++ unsigned int reg;
++ int cpu = 0;
++#endif
++
++ if (!can_change_ddr_freq())
++ return -1;
++
++ if (ddr_rate == curr_ddr_rate)
++ return 0;
++
++ printk(KERN_DEBUG "\nBus freq set to %d start...\n", ddr_rate);
++
++ if (low_bus_freq_mode || audio_bus_freq_mode)
++ dll_off = true;
++
++ iram_ddr_settings[0][0] = ddr_settings_size;
++ iram_iomux_settings[0][0] = iomux_settings_size;
++ if (ddr_rate == ddr_med_rate && cpu_is_imx6q() &&
++ ddr_med_rate != ddr_normal_rate) {
++ for (i = 0; i < ARRAY_SIZE(ddr3_dll_mx6q); i++) {
++ iram_ddr_settings[i + 1][0] =
++ normal_mmdc_settings[i][0];
++ iram_ddr_settings[i + 1][1] =
++ normal_mmdc_settings[i][1];
++ }
++ for (j = 0, i = ARRAY_SIZE(ddr3_dll_mx6q);
++ i < iram_ddr_settings[0][0]; j++, i++) {
++ iram_ddr_settings[i + 1][0] =
++ ddr3_400[j][0];
++ iram_ddr_settings[i + 1][1] =
++ ddr3_400[j][1];
++ }
++ } else if (ddr_rate == ddr_normal_rate) {
++ for (i = 0; i < iram_ddr_settings[0][0]; i++) {
++ iram_ddr_settings[i + 1][0] =
++ normal_mmdc_settings[i][0];
++ iram_ddr_settings[i + 1][1] =
++ normal_mmdc_settings[i][1];
++ }
++ }
++
++ /* ensure that all Cores are in WFE. */
++ local_irq_disable();
++
++#ifdef CONFIG_SMP
++ me = smp_processor_id();
++
++ /* Make sure all the online cores are active */
++ while (1) {
++ bool not_exited_busfreq = false;
++ for_each_online_cpu(cpu) {
++ u32 reg = __raw_readl(imx_scu_base + 0x08);
++ if (reg & (0x02 << (cpu * 8)))
++ not_exited_busfreq = true;
++ }
++ if (!not_exited_busfreq)
++ break;
++ }
++
++ wmb();
++ wait_for_ddr_freq_update = 1;
++ dsb();
++
++ online_cpus = readl_relaxed(imx_scu_base + 0x08);
++ for_each_online_cpu(cpu) {
++ *((char *)(&online_cpus) + (u8)cpu) = 0x02;
++ if (cpu != me) {
++ /* set the interrupt to be pending in the GIC. */
++ reg = 1 << (irqs_used[cpu] % 32);
++ writel_relaxed(reg, gic_dist_base + GIC_DIST_PENDING_SET
++ + (irqs_used[cpu] / 32) * 4);
++ }
++ }
++ /* Wait for the other active CPUs to idle */
++ while (1) {
++ u32 reg = readl_relaxed(imx_scu_base + 0x08);
++ reg |= (0x02 << (me * 8));
++ if (reg == online_cpus)
++ break;
++ }
++#endif
++
++ /* Ensure iram_tlb_phys_addr is flushed to DDR. */
++ /*__cpuc_flush_dcache_area(&iram_tlb_phys_addr, sizeof(iram_tlb_phys_addr));
++ outer_clean_range(virt_to_phys(&iram_tlb_phys_addr), virt_to_phys(&iram_tlb_phys_addr + 1));*/
++
++ /*
++ * Flush the TLB, to ensure no TLB maintenance occurs
++ * when DDR is in self-refresh.
++ */
++ local_flush_tlb_all();
++
++ ttbr1 = save_ttbr1();
++ /* Now we can change the DDR frequency. */
++ mx6_change_ddr_freq(ddr_rate, iram_ddr_settings,
++ dll_off, iram_iomux_settings);
++ restore_ttbr1(ttbr1);
++ curr_ddr_rate = ddr_rate;
++
++#ifdef CONFIG_SMP
++ wmb();
++ /* DDR frequency change is done . */
++ wait_for_ddr_freq_update = 0;
++ dsb();
++
++ /* wake up all the cores. */
++ sev();
++#endif
++
++ local_irq_enable();
++
++ printk(KERN_DEBUG "Bus freq set to %d done! cpu=%d\n", ddr_rate, me);
++
++ return 0;
++}
++
++int init_mmdc_ddr3_settings(struct platform_device *busfreq_pdev)
++{
++ struct device *dev = &busfreq_pdev->dev;
++ struct platform_device *ocram_dev;
++ unsigned int iram_paddr;
++ int i, err;
++ u32 cpu;
++ struct device_node *node;
++ struct gen_pool *iram_pool;
++
++ node = of_find_compatible_node(NULL, NULL, "fsl,imx6q-mmdc-combine");
++ if (!node) {
++ pr_err("failed to find imx6q-mmdc device tree data!\n");
++ return -EINVAL;
++ }
++ mmdc_base = of_iomap(node, 0);
++ WARN(!mmdc_base, "unable to map mmdc registers\n");
++
++ node = NULL;
++ if (cpu_is_imx6q())
++ node = of_find_compatible_node(NULL, NULL, "fsl,imx6q-iomuxc");
++ if (cpu_is_imx6dl())
++ node = of_find_compatible_node(NULL, NULL,
++ "fsl,imx6dl-iomuxc");
++ if (!node) {
++ pr_err("failed to find imx6q-iomux device tree data!\n");
++ return -EINVAL;
++ }
++ iomux_base = of_iomap(node, 0);
++ WARN(!iomux_base, "unable to map iomux registers\n");
++
++ node = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ccm");
++ if (!node) {
++ pr_err("failed to find imx6q-ccm device tree data!\n");
++ return -EINVAL;
++ }
++ ccm_base = of_iomap(node, 0);
++ WARN(!ccm_base, "unable to map mmdc registers\n");
++
++ node = of_find_compatible_node(NULL, NULL, "arm,pl310-cache");
++ if (!node) {
++ pr_err("failed to find imx6q-pl310-cache device tree data!\n");
++ return -EINVAL;
++ }
++ l2_base = of_iomap(node, 0);
++ WARN(!ccm_base, "unable to map mmdc registers\n");
++
++ node = NULL;
++ node = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic");
++ if (!node) {
++ pr_err("failed to find imx6q-a9-gic device tree data!\n");
++ return -EINVAL;
++ }
++ gic_dist_base = of_iomap(node, 0);
++ WARN(!gic_dist_base, "unable to map gic dist registers\n");
++
++ if (cpu_is_imx6q())
++ ddr_settings_size = ARRAY_SIZE(ddr3_dll_mx6q) +
++ ARRAY_SIZE(ddr3_calibration);
++ if (cpu_is_imx6dl())
++ ddr_settings_size = ARRAY_SIZE(ddr3_dll_mx6dl) +
++ ARRAY_SIZE(ddr3_calibration);
++
++ normal_mmdc_settings = kmalloc((ddr_settings_size * 8), GFP_KERNEL);
++ if (cpu_is_imx6q()) {
++ memcpy(normal_mmdc_settings, ddr3_dll_mx6q,
++ sizeof(ddr3_dll_mx6q));
++ memcpy(((char *)normal_mmdc_settings + sizeof(ddr3_dll_mx6q)),
++ ddr3_calibration, sizeof(ddr3_calibration));
++ }
++ if (cpu_is_imx6dl()) {
++ memcpy(normal_mmdc_settings, ddr3_dll_mx6dl,
++ sizeof(ddr3_dll_mx6dl));
++ memcpy(((char *)normal_mmdc_settings + sizeof(ddr3_dll_mx6dl)),
++ ddr3_calibration, sizeof(ddr3_calibration));
++ }
++ /* store the original DDR settings at boot. */
++ for (i = 0; i < ddr_settings_size; i++) {
++ /*
++ * writes via command mode register cannot be read back.
++ * hence hardcode them in the initial static array.
++ * this may require modification on a per customer basis.
++ */
++ if (normal_mmdc_settings[i][0] != 0x1C)
++ normal_mmdc_settings[i][1] =
++ readl_relaxed(mmdc_base
++ + normal_mmdc_settings[i][0]);
++ }
++
++ irqs_used = devm_kzalloc(dev, sizeof(u32) * num_present_cpus(),
++ GFP_KERNEL);
++
++ for_each_online_cpu(cpu) {
++ int irq;
++
++ /*
++ * set up a reserved interrupt to get all
++ * the active cores into a WFE state
++ * before changing the DDR frequency.
++ */
++ irq = platform_get_irq(busfreq_pdev, cpu);
++ err = request_irq(irq, wait_in_wfe_irq,
++ IRQF_PERCPU, "mmdc_1", NULL);
++ if (err) {
++ dev_err(dev,
++ "Busfreq:request_irq failed %d, err = %d\n",
++ irq, err);
++ return err;
++ }
++ err = irq_set_affinity(irq, cpumask_of(cpu));
++ if (err) {
++ dev_err(dev,
++ "Busfreq: Cannot set irq affinity irq=%d,\n",
++ irq);
++ return err;
++ }
++ irqs_used[cpu] = irq;
++ }
++
++ node = NULL;
++ node = of_find_compatible_node(NULL, NULL, "mmio-sram");
++ if (!node) {
++ dev_err(dev, "%s: failed to find ocram node\n",
++ __func__);
++ return -EINVAL;
++ }
++
++ ocram_dev = of_find_device_by_node(node);
++ if (!ocram_dev) {
++ dev_err(dev, "failed to find ocram device!\n");
++ return -EINVAL;
++ }
++
++ iram_pool = dev_get_gen_pool(&ocram_dev->dev);
++ if (!iram_pool) {
++ dev_err(dev, "iram pool unavailable!\n");
++ return -EINVAL;
++ }
++
++ iomux_settings_size = ARRAY_SIZE(iomux_offsets_mx6q);
++ iram_iomux_settings = (void*)gen_pool_alloc(iram_pool,
++ (iomux_settings_size * 8) + 8);
++ if (!iram_iomux_settings) {
++ dev_err(dev, "unable to alloc iram for IOMUX settings!\n");
++ return -ENOMEM;
++ }
++
++ /*
++ * Allocate extra space to store the number of entries in the
++ * ddr_settings plus 4 extra regsiter information that needs
++ * to be passed to the frequency change code.
++ * sizeof(iram_ddr_settings) = sizeof(ddr_settings) +
++ * entries in ddr_settings + 16.
++ * The last 4 enties store the addresses of the registers:
++ * CCM_BASE_ADDR
++ * MMDC_BASE_ADDR
++ * IOMUX_BASE_ADDR
++ * L2X0_BASE_ADDR
++ */
++ iram_ddr_settings = (void*)gen_pool_alloc(iram_pool,
++ (ddr_settings_size * 8) + 8 + 32);
++ if (!iram_ddr_settings) {
++ dev_err(dev, "unable to alloc iram for ddr settings!\n");
++ return -ENOMEM;
++ }
++ i = ddr_settings_size + 1;
++ iram_ddr_settings[i][0] = (unsigned long)mmdc_base;
++ iram_ddr_settings[i+1][0] = (unsigned long)ccm_base;
++ iram_ddr_settings[i+2][0] = (unsigned long)iomux_base;
++ iram_ddr_settings[i+3][0] = (unsigned long)l2_base;
++
++ if (cpu_is_imx6q()) {
++ /* store the IOMUX settings at boot. */
++ for (i = 0; i < iomux_settings_size; i++) {
++ iomux_offsets_mx6q[i][1] =
++ readl_relaxed(iomux_base +
++ iomux_offsets_mx6q[i][0]);
++ iram_iomux_settings[i+1][0] = iomux_offsets_mx6q[i][0];
++ iram_iomux_settings[i+1][1] = iomux_offsets_mx6q[i][1];
++ }
++ }
++
++ if (cpu_is_imx6dl()) {
++ for (i = 0; i < iomux_settings_size; i++) {
++ iomux_offsets_mx6dl[i][1] =
++ readl_relaxed(iomux_base +
++ iomux_offsets_mx6dl[i][0]);
++ iram_iomux_settings[i+1][0] = iomux_offsets_mx6dl[i][0];
++ iram_iomux_settings[i+1][1] = iomux_offsets_mx6dl[i][1];
++ }
++ }
++
++ ddr_freq_change_iram_base = (void*)gen_pool_alloc(iram_pool,
++ DDR_FREQ_CHANGE_SIZE);
++ if (!ddr_freq_change_iram_base) {
++ dev_err(dev, "Cannot alloc iram for ddr freq change code!\n");
++ return -ENOMEM;
++ }
++
++ iram_paddr = gen_pool_virt_to_phys(iram_pool,
++ (unsigned long)ddr_freq_change_iram_base);
++ /*
++ * Need to remap the area here since we want
++ * the memory region to be executable.
++ */
++ ddr_freq_change_iram_base = __arm_ioremap(iram_paddr,
++ DDR_FREQ_CHANGE_SIZE,
++ MT_MEMORY_RWX_NONCACHED);
++ mx6_change_ddr_freq = (void *)fncpy(ddr_freq_change_iram_base,
++ &mx6_ddr3_freq_change, DDR_FREQ_CHANGE_SIZE);
++
++ curr_ddr_rate = ddr_normal_rate;
++
++ return 0;
++}
+diff -Nur linux-4.1.3/arch/arm/mach-imx/busfreq-imx6.c linux-xbian-imx6/arch/arm/mach-imx/busfreq-imx6.c
+--- linux-4.1.3/arch/arm/mach-imx/busfreq-imx6.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/arch/arm/mach-imx/busfreq-imx6.c 2015-07-27 23:13:01.073153409 +0200
+@@ -0,0 +1,984 @@
++/*
++ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++/*!
++ * @file busfreq-imx6.c
++ *
++ * @brief A common API for the Freescale Semiconductor iMX6 Busfreq API
++ *
++ * The APIs are for setting bus frequency to different values based on the
++ * highest freqeuncy requested.
++ *
++ * @ingroup PM
++ */
++
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <asm/cacheflush.h>
++#include <asm/io.h>
++#include <asm/mach/map.h>
++#include <asm/mach-types.h>
++#include <asm/tlb.h>
++#include <linux/busfreq-imx6.h>
++#include <linux/clk.h>
++#include <linux/clk-provider.h>
++#include <linux/delay.h>
++#include <linux/module.h>
++#include <linux/mutex.h>
++#include <linux/of.h>
++#include <linux/platform_device.h>
++#include <linux/proc_fs.h>
++#include <linux/reboot.h>
++#include <linux/regulator/consumer.h>
++#include <linux/sched.h>
++#include <linux/suspend.h>
++#include "hardware.h"
++
++#define LPAPM_CLK 24000000
++#define DDR3_AUDIO_CLK 50000000
++#define LPDDR2_AUDIO_CLK 100000000
++
++int vpu352 = 0;
++
++int high_bus_freq_mode;
++int med_bus_freq_mode;
++int audio_bus_freq_mode;
++int low_bus_freq_mode;
++int ultra_low_bus_freq_mode;
++unsigned int ddr_med_rate;
++unsigned int ddr_normal_rate;
++
++#ifdef CONFIG_ARM_IMX6Q_CPUFREQ
++static int bus_freq_scaling_initialized;
++static struct device *busfreq_dev;
++static int busfreq_suspended;
++static u32 org_arm_rate;
++static int bus_freq_scaling_is_active;
++static int high_bus_count, med_bus_count, audio_bus_count, low_bus_count;
++static unsigned int ddr_low_rate;
++
++extern int init_mmdc_lpddr2_settings(struct platform_device *dev);
++extern int init_mmdc_ddr3_settings(struct platform_device *dev);
++extern int update_ddr_freq(int ddr_rate);
++extern int update_lpddr2_freq(int ddr_rate);
++
++DEFINE_MUTEX(bus_freq_mutex);
++static DEFINE_SPINLOCK(freq_lock);
++
++static struct clk *pll2_400;
++static struct clk *periph_clk;
++static struct clk *periph_pre_clk;
++static struct clk *periph_clk2_sel;
++static struct clk *periph_clk2;
++static struct clk *osc_clk;
++static struct clk *cpu_clk;
++static struct clk *pll3;
++static struct clk *pll2;
++static struct clk *pll2_200;
++static struct clk *pll1_sys;
++static struct clk *periph2_clk;
++static struct clk *ocram_clk;
++static struct clk *ahb_clk;
++static struct clk *pll1_sw_clk;
++static struct clk *periph2_pre_clk;
++static struct clk *periph2_clk2_sel;
++static struct clk *periph2_clk2;
++static struct clk *step_clk;
++static struct clk *axi_sel_clk;
++static struct clk *pll3_pfd1_540m;
++
++static u32 pll2_org_rate;
++static struct delayed_work low_bus_freq_handler;
++static struct delayed_work bus_freq_daemon;
++
++static void enter_lpm_imx6sl(void)
++{
++ unsigned long flags;
++
++ if (high_bus_freq_mode) {
++ pll2_org_rate = clk_get_rate(pll2);
++ /* Set periph_clk to be sourced from OSC_CLK */
++ clk_set_parent(periph_clk2_sel, osc_clk);
++ clk_set_parent(periph_clk, periph_clk2);
++ /* Ensure AHB/AXI clks are at 24MHz. */
++ clk_set_rate(ahb_clk, LPAPM_CLK);
++ clk_set_rate(ocram_clk, LPAPM_CLK);
++ }
++ if (audio_bus_count) {
++ /* Set AHB to 8MHz to lower pwer.*/
++ clk_set_rate(ahb_clk, LPAPM_CLK / 3);
++
++ /* Set up DDR to 100MHz. */
++ spin_lock_irqsave(&freq_lock, flags);
++ update_lpddr2_freq(LPDDR2_AUDIO_CLK);
++ spin_unlock_irqrestore(&freq_lock, flags);
++
++ /* Fix the clock tree in kernel */
++ clk_set_rate(pll2, pll2_org_rate);
++ clk_set_parent(periph2_pre_clk, pll2_200);
++ clk_set_parent(periph2_clk, periph2_pre_clk);
++
++ if (low_bus_freq_mode || ultra_low_bus_freq_mode) {
++ /*
++ * Swtich ARM to run off PLL2_PFD2_400MHz
++ * since DDR is anyway at 100MHz.
++ */
++ clk_set_parent(step_clk, pll2_400);
++ clk_set_parent(pll1_sw_clk, step_clk);
++ /*
++ * Ensure that the clock will be
++ * at original speed.
++ */
++ clk_set_rate(cpu_clk, org_arm_rate);
++ }
++ low_bus_freq_mode = 0;
++ ultra_low_bus_freq_mode = 0;
++ audio_bus_freq_mode = 1;
++ } else {
++ u32 arm_div, pll1_rate;
++ org_arm_rate = clk_get_rate(cpu_clk);
++ if (low_bus_freq_mode && low_bus_count == 0) {
++ /*
++ * We are already in DDR @ 24MHz state, but
++ * no one but ARM needs the DDR. In this case,
++ * we can lower the DDR freq to 1MHz when ARM
++ * enters WFI in this state. Keep track of this state.
++ */
++ ultra_low_bus_freq_mode = 1;
++ low_bus_freq_mode = 0;
++ audio_bus_freq_mode = 0;
++ } else {
++ if (!ultra_low_bus_freq_mode && !low_bus_freq_mode) {
++ /*
++ * Set DDR to 24MHz.
++ * Since we are going to bypass PLL2,
++ * we need to move ARM clk off PLL2_PFD2
++ * to PLL1. Make sure the PLL1 is running
++ * at the lowest possible freq.
++ */
++ clk_set_rate(pll1_sys,
++ clk_round_rate(pll1_sys, org_arm_rate));
++ pll1_rate = clk_get_rate(pll1_sys);
++ arm_div = pll1_rate / org_arm_rate + 1;
++ /*
++ * Ensure ARM CLK is lower before
++ * changing the parent.
++ */
++ clk_set_rate(cpu_clk, org_arm_rate / arm_div);
++ /* Now set the ARM clk parent to PLL1_SYS. */
++ clk_set_parent(pll1_sw_clk, pll1_sys);
++
++ /*
++ * Set STEP_CLK back to OSC to save power and
++ * also to maintain the parent.The WFI iram code
++ * will switch step_clk to osc, but the clock API
++ * is not aware of the change and when a new request
++ * to change the step_clk parent to pll2_pfd2_400M
++ * is requested sometime later, the change is ignored.
++ */
++ clk_set_parent(step_clk, osc_clk);
++ /* Now set DDR to 24MHz. */
++ spin_lock_irqsave(&freq_lock, flags);
++ update_lpddr2_freq(LPAPM_CLK);
++ spin_unlock_irqrestore(&freq_lock, flags);
++
++ /*
++ * Fix the clock tree in kernel.
++ * Make sure PLL2 rate is updated as it gets
++ * bypassed in the DDR freq change code.
++ */
++ clk_set_rate(pll2, LPAPM_CLK);
++ clk_set_parent(periph2_clk2_sel, pll2);
++ clk_set_parent(periph2_clk, periph2_clk2_sel);
++
++ }
++ if (low_bus_count == 0) {
++ ultra_low_bus_freq_mode = 1;
++ low_bus_freq_mode = 0;
++ } else {
++ ultra_low_bus_freq_mode = 0;
++ low_bus_freq_mode = 1;
++ }
++ audio_bus_freq_mode = 0;
++ }
++ }
++}
++
++static void exit_lpm_imx6sl(void)
++{
++ unsigned long flags;
++
++ spin_lock_irqsave(&freq_lock, flags);
++ /* Change DDR freq in IRAM. */
++ update_lpddr2_freq(ddr_normal_rate);
++ spin_unlock_irqrestore(&freq_lock, flags);
++
++ /*
++ * Fix the clock tree in kernel.
++ * Make sure PLL2 rate is updated as it gets
++ * un-bypassed in the DDR freq change code.
++ */
++ clk_set_rate(pll2, pll2_org_rate);
++ clk_set_parent(periph2_pre_clk, pll2_400);
++ clk_set_parent(periph2_clk, periph2_pre_clk);
++
++ /* Ensure that periph_clk is sourced from PLL2_400. */
++ clk_set_parent(periph_pre_clk, pll2_400);
++ /*
++ * Before switching the perhiph_clk, ensure that the
++ * AHB/AXI will not be too fast.
++ */
++ clk_set_rate(ahb_clk, LPAPM_CLK / 3);
++ clk_set_rate(ocram_clk, LPAPM_CLK / 2);
++ clk_set_parent(periph_clk, periph_pre_clk);
++
++ if (low_bus_freq_mode || ultra_low_bus_freq_mode) {
++ /* Move ARM from PLL1_SW_CLK to PLL2_400. */
++ clk_set_parent(step_clk, pll2_400);
++ clk_set_parent(pll1_sw_clk, step_clk);
++ clk_set_rate(cpu_clk, org_arm_rate);
++ ultra_low_bus_freq_mode = 0;
++ }
++}
++
++int reduce_bus_freq(void)
++{
++ int ret = 0;
++ clk_prepare_enable(pll3);
++ if (cpu_is_imx6sl())
++ enter_lpm_imx6sl();
++ else {
++ if (cpu_is_imx6dl() && (clk_get_parent(axi_sel_clk)
++ != periph_clk))
++ /* Set axi to periph_clk */
++ clk_set_parent(axi_sel_clk, periph_clk);
++
++ if (audio_bus_count) {
++ /* Need to ensure that PLL2_PFD_400M is kept ON. */
++ clk_prepare_enable(pll2_400);
++ update_ddr_freq(DDR3_AUDIO_CLK);
++ /* Make sure periph clk's parent also got updated */
++ ret = clk_set_parent(periph_clk2_sel, pll3);
++ if (ret)
++ dev_WARN(busfreq_dev,
++ "%s: %d: clk set parent fail!\n",
++ __func__, __LINE__);
++ ret = clk_set_parent(periph_pre_clk, pll2_200);
++ if (ret)
++ dev_WARN(busfreq_dev,
++ "%s: %d: clk set parent fail!\n",
++ __func__, __LINE__);
++ ret = clk_set_parent(periph_clk, periph_pre_clk);
++ if (ret)
++ dev_WARN(busfreq_dev,
++ "%s: %d: clk set parent fail!\n",
++ __func__, __LINE__);
++ audio_bus_freq_mode = 1;
++ low_bus_freq_mode = 0;
++ } else {
++ update_ddr_freq(LPAPM_CLK);
++ /* Make sure periph clk's parent also got updated */
++ ret = clk_set_parent(periph_clk2_sel, osc_clk);
++ if (ret)
++ dev_WARN(busfreq_dev,
++ "%s: %d: clk set parent fail!\n",
++ __func__, __LINE__);
++ /* Set periph_clk parent to OSC via periph_clk2_sel */
++ ret = clk_set_parent(periph_clk, periph_clk2);
++ if (ret)
++ dev_WARN(busfreq_dev,
++ "%s: %d: clk set parent fail!\n",
++ __func__, __LINE__);
++ if (audio_bus_freq_mode)
++ clk_disable_unprepare(pll2_400);
++ low_bus_freq_mode = 1;
++ audio_bus_freq_mode = 0;
++ }
++ }
++ clk_disable_unprepare(pll3);
++
++ med_bus_freq_mode = 0;
++ high_bus_freq_mode = 0;
++
++ if (audio_bus_freq_mode)
++ dev_dbg(busfreq_dev, "Bus freq set to audio mode. Count:\
++ high %d, med %d, audio %d\n",
++ high_bus_count, med_bus_count, audio_bus_count);
++ if (low_bus_freq_mode)
++ dev_dbg(busfreq_dev, "Bus freq set to low mode. Count:\
++ high %d, med %d, audio %d\n",
++ high_bus_count, med_bus_count, audio_bus_count);
++
++ return ret;
++}
++
++static void reduce_bus_freq_handler(struct work_struct *work)
++{
++ mutex_lock(&bus_freq_mutex);
++
++ reduce_bus_freq();
++
++ mutex_unlock(&bus_freq_mutex);
++}
++
++/*
++ * Set the DDR, AHB to 24MHz.
++ * This mode will be activated only when none of the modules that
++ * need a higher DDR or AHB frequency are active.
++ */
++int set_low_bus_freq(void)
++{
++ if (busfreq_suspended)
++ return 0;
++
++ if (!bus_freq_scaling_initialized || !bus_freq_scaling_is_active)
++ return 0;
++
++ /*
++ * Check to see if we need to got from
++ * low bus freq mode to audio bus freq mode.
++ * If so, the change needs to be done immediately.
++ */
++ if (audio_bus_count && (low_bus_freq_mode || ultra_low_bus_freq_mode))
++ reduce_bus_freq();
++ else
++ /*
++ * Don't lower the frequency immediately. Instead
++ * scheduled a delayed work and drop the freq if
++ * the conditions still remain the same.
++ */
++ schedule_delayed_work(&low_bus_freq_handler,
++ usecs_to_jiffies(3000000));
++ return 0;
++}
++
++/*
++ * Set the DDR to either 528MHz or 400MHz for iMX6qd
++ * or 400MHz for iMX6dl.
++ */
++int set_high_bus_freq(int high_bus_freq)
++{
++ int ret = 0;
++ struct clk *periph_clk_parent;
++
++ if (bus_freq_scaling_initialized && bus_freq_scaling_is_active)
++ cancel_delayed_work_sync(&low_bus_freq_handler);
++
++ if (busfreq_suspended)
++ return 0;
++
++ if (cpu_is_imx6q())
++ periph_clk_parent = pll2;
++ else
++ periph_clk_parent = pll2_400;
++
++ if (!bus_freq_scaling_initialized || !bus_freq_scaling_is_active)
++ return 0;
++
++ if (high_bus_freq_mode)
++ return 0;
++
++ /* medium bus freq is only supported for MX6DQ */
++ if (med_bus_freq_mode && !high_bus_freq)
++ return 0;
++
++ clk_prepare_enable(pll3);
++ if (cpu_is_imx6sl())
++ exit_lpm_imx6sl();
++ else {
++ if (high_bus_freq) {
++ update_ddr_freq(ddr_normal_rate);
++ /* Make sure periph clk's parent also got updated */
++ ret = clk_set_parent(periph_clk2_sel, pll3);
++ if (ret)
++ dev_WARN(busfreq_dev,
++ "%s: %d: clk set parent fail!\n",
++ __func__, __LINE__);
++ ret = clk_set_parent(periph_pre_clk, periph_clk_parent);
++ if (ret)
++ dev_WARN(busfreq_dev,
++ "%s: %d: clk set parent fail!\n",
++ __func__, __LINE__);
++ ret = clk_set_parent(periph_clk, periph_pre_clk);
++ if (ret)
++ dev_WARN(busfreq_dev,
++ "%s: %d: clk set parent fail!\n",
++ __func__, __LINE__);
++ if (cpu_is_imx6dl() && (clk_get_parent(axi_sel_clk)
++ != pll3_pfd1_540m))
++ /* Set axi to pll3_pfd1_540m */
++ clk_set_parent(axi_sel_clk, pll3_pfd1_540m);
++ } else {
++ update_ddr_freq(ddr_med_rate);
++ /* Make sure periph clk's parent also got updated */
++ ret = clk_set_parent(periph_clk2_sel, pll3);
++ if (ret)
++ dev_WARN(busfreq_dev,
++ "%s: %d: clk set parent fail!\n",
++ __func__, __LINE__);
++ ret = clk_set_parent(periph_pre_clk, pll2_400);
++ if (ret)
++ dev_WARN(busfreq_dev,
++ "%s: %d: clk set parent fail!\n",
++ __func__, __LINE__);
++ ret = clk_set_parent(periph_clk, periph_pre_clk);
++ if (ret)
++ dev_WARN(busfreq_dev,
++ "%s: %d: clk set parent fail!\n",
++ __func__, __LINE__);
++ }
++ if (audio_bus_freq_mode)
++ clk_disable_unprepare(pll2_400);
++ }
++
++ high_bus_freq_mode = 1;
++ med_bus_freq_mode = 0;
++ low_bus_freq_mode = 0;
++ audio_bus_freq_mode = 0;
++
++ clk_disable_unprepare(pll3);
++
++ if (high_bus_freq_mode)
++ dev_dbg(busfreq_dev, "Bus freq set to high mode. Count:\
++ high %d, med %d, audio %d\n",
++ high_bus_count, med_bus_count, audio_bus_count);
++ if (med_bus_freq_mode)
++ dev_dbg(busfreq_dev, "Bus freq set to med mode. Count:\
++ high %d, med %d, audio %d\n",
++ high_bus_count, med_bus_count, audio_bus_count);
++
++ return 0;
++}
++#endif
++
++void request_bus_freq(enum bus_freq_mode mode)
++{
++#ifdef CONFIG_ARM_IMX6Q_CPUFREQ
++ mutex_lock(&bus_freq_mutex);
++
++ if (mode == BUS_FREQ_HIGH)
++ high_bus_count++;
++ else if (mode == BUS_FREQ_MED)
++ med_bus_count++;
++ else if (mode == BUS_FREQ_AUDIO)
++ audio_bus_count++;
++ else if (mode == BUS_FREQ_LOW)
++ low_bus_count++;
++
++ if (busfreq_suspended || !bus_freq_scaling_initialized ||
++ !bus_freq_scaling_is_active) {
++ mutex_unlock(&bus_freq_mutex);
++ return;
++ }
++ cancel_delayed_work_sync(&low_bus_freq_handler);
++
++ if (cpu_is_imx6dl()) {
++ /* No support for medium setpoint on MX6DL. */
++ if (mode == BUS_FREQ_MED) {
++ high_bus_count++;
++ mode = BUS_FREQ_HIGH;
++ }
++ }
++
++ if ((mode == BUS_FREQ_HIGH) && (!high_bus_freq_mode)) {
++ set_high_bus_freq(1);
++ mutex_unlock(&bus_freq_mutex);
++ return;
++ }
++
++ if ((mode == BUS_FREQ_MED) && (!high_bus_freq_mode) &&
++ (!med_bus_freq_mode)) {
++ set_high_bus_freq(0);
++ mutex_unlock(&bus_freq_mutex);
++ return;
++ }
++ if ((mode == BUS_FREQ_AUDIO) && (!high_bus_freq_mode) &&
++ (!med_bus_freq_mode) && (!audio_bus_freq_mode)) {
++ set_low_bus_freq();
++ mutex_unlock(&bus_freq_mutex);
++ return;
++ }
++ mutex_unlock(&bus_freq_mutex);
++#endif
++ return;
++}
++EXPORT_SYMBOL(request_bus_freq);
++
++void release_bus_freq(enum bus_freq_mode mode)
++{
++#ifdef CONFIG_ARM_IMX6Q_CPUFREQ
++ mutex_lock(&bus_freq_mutex);
++
++ if (mode == BUS_FREQ_HIGH) {
++ if (high_bus_count == 0) {
++ dev_err(busfreq_dev, "high bus count mismatch!\n");
++ dump_stack();
++ mutex_unlock(&bus_freq_mutex);
++ return;
++ }
++ high_bus_count--;
++ } else if (mode == BUS_FREQ_MED) {
++ if (med_bus_count == 0) {
++ dev_err(busfreq_dev, "med bus count mismatch!\n");
++ dump_stack();
++ mutex_unlock(&bus_freq_mutex);
++ return;
++ }
++ med_bus_count--;
++ } else if (mode == BUS_FREQ_AUDIO) {
++ if (audio_bus_count == 0) {
++ dev_err(busfreq_dev, "audio bus count mismatch!\n");
++ dump_stack();
++ mutex_unlock(&bus_freq_mutex);
++ return;
++ }
++ audio_bus_count--;
++ } else if (mode == BUS_FREQ_LOW) {
++ if (low_bus_count == 0) {
++ dev_err(busfreq_dev, "low bus count mismatch!\n");
++ dump_stack();
++ mutex_unlock(&bus_freq_mutex);
++ return;
++ }
++ low_bus_count--;
++ }
++
++ if (busfreq_suspended || !bus_freq_scaling_initialized ||
++ !bus_freq_scaling_is_active) {
++ mutex_unlock(&bus_freq_mutex);
++ return;
++ }
++
++ if (cpu_is_imx6dl()) {
++ /* No support for medium setpoint on MX6DL. */
++ if (mode == BUS_FREQ_MED) {
++ high_bus_count--;
++ mode = BUS_FREQ_HIGH;
++ }
++ }
++
++ if ((!audio_bus_freq_mode) && (high_bus_count == 0) &&
++ (med_bus_count == 0) && (audio_bus_count != 0)) {
++ set_low_bus_freq();
++ mutex_unlock(&bus_freq_mutex);
++ return;
++ }
++ if ((!low_bus_freq_mode) && (high_bus_count == 0) &&
++ (med_bus_count == 0) && (audio_bus_count == 0) &&
++ (low_bus_count != 0)) {
++ set_low_bus_freq();
++ mutex_unlock(&bus_freq_mutex);
++ return;
++ }
++ if ((!ultra_low_bus_freq_mode) && (high_bus_count == 0) &&
++ (med_bus_count == 0) && (audio_bus_count == 0) &&
++ (low_bus_count == 0)) {
++ set_low_bus_freq();
++ mutex_unlock(&bus_freq_mutex);
++ return;
++ }
++
++ mutex_unlock(&bus_freq_mutex);
++#endif
++ return;
++}
++EXPORT_SYMBOL(release_bus_freq);
++
++#ifdef CONFIG_ARM_IMX6Q_CPUFREQ
++static void bus_freq_daemon_handler(struct work_struct *work)
++{
++ mutex_lock(&bus_freq_mutex);
++ if ((!low_bus_freq_mode) && (!ultra_low_bus_freq_mode) && (high_bus_count == 0) &&
++ (med_bus_count == 0) && (audio_bus_count == 0))
++ set_low_bus_freq();
++ mutex_unlock(&bus_freq_mutex);
++}
++
++static ssize_t bus_freq_scaling_enable_show(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ if (bus_freq_scaling_is_active)
++ return sprintf(buf, "Bus frequency scaling is enabled\n");
++ else
++ return sprintf(buf, "Bus frequency scaling is disabled\n");
++}
++
++static ssize_t vpu352_enable_show(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ if (vpu352)
++ return sprintf(buf, "VPU352M is enabled\n");
++ else
++ return sprintf(buf, "VPU352M is disabled\n");
++}
++
++static int vpu352_setup(char *options)
++{
++ return kstrtol(options, 0, (long int *)&vpu352);
++}
++
++static ssize_t bus_freq_scaling_enable_store(struct device *dev,
++ struct device_attribute *attr,
++ const char *buf, size_t size)
++{
++ if (strncmp(buf, "1", 1) == 0) {
++ bus_freq_scaling_is_active = 1;
++ set_high_bus_freq(1);
++ /*
++ * We set bus freq to highest at the beginning,
++ * so we use this daemon thread to make sure system
++ * can enter low bus mode if
++ * there is no high bus request pending
++ */
++ schedule_delayed_work(&bus_freq_daemon,
++ usecs_to_jiffies(5000000));
++ } else if (strncmp(buf, "0", 1) == 0) {
++ if (bus_freq_scaling_is_active)
++ set_high_bus_freq(1);
++ bus_freq_scaling_is_active = 0;
++ }
++ return size;
++}
++
++static int bus_freq_pm_notify(struct notifier_block *nb, unsigned long event,
++ void *dummy)
++{
++ mutex_lock(&bus_freq_mutex);
++
++ if (event == PM_SUSPEND_PREPARE) {
++ high_bus_count++;
++ set_high_bus_freq(1);
++ busfreq_suspended = 1;
++ } else if (event == PM_POST_SUSPEND) {
++ busfreq_suspended = 0;
++ high_bus_count--;
++ schedule_delayed_work(&bus_freq_daemon,
++ usecs_to_jiffies(5000000));
++ }
++
++ mutex_unlock(&bus_freq_mutex);
++
++ return NOTIFY_OK;
++}
++
++static int busfreq_reboot_notifier_event(struct notifier_block *this,
++ unsigned long event, void *ptr)
++{
++ /* System is rebooting. Set the system into high_bus_freq_mode. */
++ request_bus_freq(BUS_FREQ_HIGH);
++
++ return 0;
++}
++
++static struct notifier_block imx_bus_freq_pm_notifier = {
++ .notifier_call = bus_freq_pm_notify,
++};
++
++static struct notifier_block imx_busfreq_reboot_notifier = {
++ .notifier_call = busfreq_reboot_notifier_event,
++};
++
++
++static DEVICE_ATTR(enable, 0644, bus_freq_scaling_enable_show,
++ bus_freq_scaling_enable_store);
++static DEVICE_ATTR(vpu352, 0444, vpu352_enable_show,
++ NULL);
++#endif
++
++/*!
++ * This is the probe routine for the bus frequency driver.
++ *
++ * @param pdev The platform device structure
++ *
++ * @return The function returns 0 on success
++ *
++ */
++
++static int busfreq_probe(struct platform_device *pdev)
++{
++#ifdef CONFIG_ARM_IMX6Q_CPUFREQ
++ u32 err;
++
++ busfreq_dev = &pdev->dev;
++
++ pll2_400 = devm_clk_get(&pdev->dev, "pll2_pfd2_396m");
++ if (IS_ERR(pll2_400)) {
++ dev_err(busfreq_dev, "%s: failed to get pll2_pfd2_396m\n",
++ __func__);
++ return PTR_ERR(pll2_400);
++ }
++
++ pll2_200 = devm_clk_get(&pdev->dev, "pll2_198m");
++ if (IS_ERR(pll2_200)) {
++ dev_err(busfreq_dev, "%s: failed to get pll2_198m\n",
++ __func__);
++ return PTR_ERR(pll2_200);
++ }
++
++ pll2 = devm_clk_get(&pdev->dev, "pll2_bus");
++ if (IS_ERR(pll2)) {
++ dev_err(busfreq_dev, "%s: failed to get pll2_bus\n",
++ __func__);
++ return PTR_ERR(pll2);
++ }
++
++ cpu_clk = devm_clk_get(&pdev->dev, "arm");
++ if (IS_ERR(cpu_clk)) {
++ dev_err(busfreq_dev, "%s: failed to get cpu_clk\n",
++ __func__);
++ return PTR_ERR(cpu_clk);
++ }
++
++ pll3 = devm_clk_get(&pdev->dev, "pll3_usb_otg");
++ if (IS_ERR(pll3)) {
++ dev_err(busfreq_dev, "%s: failed to get pll3_usb_otg\n",
++ __func__);
++ return PTR_ERR(pll3);
++ }
++
++ periph_clk = devm_clk_get(&pdev->dev, "periph");
++ if (IS_ERR(periph_clk)) {
++ dev_err(busfreq_dev, "%s: failed to get periph\n",
++ __func__);
++ return PTR_ERR(periph_clk);
++ }
++
++ periph_pre_clk = devm_clk_get(&pdev->dev, "periph_pre");
++ if (IS_ERR(periph_pre_clk)) {
++ dev_err(busfreq_dev, "%s: failed to get periph_pre\n",
++ __func__);
++ return PTR_ERR(periph_pre_clk);
++ }
++
++ periph_clk2 = devm_clk_get(&pdev->dev, "periph_clk2");
++ if (IS_ERR(periph_clk2)) {
++ dev_err(busfreq_dev, "%s: failed to get periph_clk2\n",
++ __func__);
++ return PTR_ERR(periph_clk2);
++ }
++
++ periph_clk2_sel = devm_clk_get(&pdev->dev, "periph_clk2_sel");
++ if (IS_ERR(periph_clk2_sel)) {
++ dev_err(busfreq_dev, "%s: failed to get periph_clk2_sel\n",
++ __func__);
++ return PTR_ERR(periph_clk2_sel);
++ }
++
++ osc_clk = devm_clk_get(&pdev->dev, "osc");
++ if (IS_ERR(osc_clk)) {
++ dev_err(busfreq_dev, "%s: failed to get osc_clk\n",
++ __func__);
++ return PTR_ERR(osc_clk);
++ }
++
++ if (cpu_is_imx6dl()) {
++ axi_sel_clk = devm_clk_get(&pdev->dev, "axi_sel");
++ if (IS_ERR(axi_sel_clk)) {
++ dev_err(busfreq_dev, "%s: failed to get axi_sel_clk\n",
++ __func__);
++ return PTR_ERR(axi_sel_clk);
++ }
++
++ pll3_pfd1_540m = devm_clk_get(&pdev->dev, "pll3_pfd1_540m");
++ if (IS_ERR(pll3_pfd1_540m)) {
++ dev_err(busfreq_dev,
++ "%s: failed to get pll3_pfd1_540m\n", __func__);
++ return PTR_ERR(pll3_pfd1_540m);
++ }
++ }
++
++ if (cpu_is_imx6sl()) {
++ pll1_sys = devm_clk_get(&pdev->dev, "pll1_sys");
++ if (IS_ERR(pll1_sys)) {
++ dev_err(busfreq_dev, "%s: failed to get pll1_sys\n",
++ __func__);
++ return PTR_ERR(pll1_sys);
++ }
++
++ ahb_clk = devm_clk_get(&pdev->dev, "ahb");
++ if (IS_ERR(ahb_clk)) {
++ dev_err(busfreq_dev, "%s: failed to get ahb_clk\n",
++ __func__);
++ return PTR_ERR(ahb_clk);
++ }
++
++ ocram_clk = devm_clk_get(&pdev->dev, "ocram");
++ if (IS_ERR(ocram_clk)) {
++ dev_err(busfreq_dev, "%s: failed to get ocram_clk\n",
++ __func__);
++ return PTR_ERR(ocram_clk);
++ }
++
++ pll1_sw_clk = devm_clk_get(&pdev->dev, "pll1_sw");
++ if (IS_ERR(pll1_sw_clk)) {
++ dev_err(busfreq_dev, "%s: failed to get pll1_sw_clk\n",
++ __func__);
++ return PTR_ERR(pll1_sw_clk);
++ }
++
++ periph2_clk = devm_clk_get(&pdev->dev, "periph2");
++ if (IS_ERR(periph2_clk)) {
++ dev_err(busfreq_dev, "%s: failed to get periph2\n",
++ __func__);
++ return PTR_ERR(periph2_clk);
++ }
++
++ periph2_pre_clk = devm_clk_get(&pdev->dev, "periph2_pre");
++ if (IS_ERR(periph2_pre_clk)) {
++ dev_err(busfreq_dev,
++ "%s: failed to get periph2_pre_clk\n",
++ __func__);
++ return PTR_ERR(periph2_pre_clk);
++ }
++
++ periph2_clk2 = devm_clk_get(&pdev->dev, "periph2_clk2");
++ if (IS_ERR(periph2_clk2)) {
++ dev_err(busfreq_dev,
++ "%s: failed to get periph2_clk2\n",
++ __func__);
++ return PTR_ERR(periph2_clk2);
++ }
++
++ periph2_clk2_sel = devm_clk_get(&pdev->dev, "periph2_clk2_sel");
++ if (IS_ERR(periph2_clk2_sel)) {
++ dev_err(busfreq_dev,
++ "%s: failed to get periph2_clk2_sel\n",
++ __func__);
++ return PTR_ERR(periph2_clk2_sel);
++ }
++
++ step_clk = devm_clk_get(&pdev->dev, "step");
++ if (IS_ERR(step_clk)) {
++ dev_err(busfreq_dev,
++ "%s: failed to get step_clk\n",
++ __func__);
++ return PTR_ERR(periph2_clk2_sel);
++ }
++
++ }
++
++ err = sysfs_create_file(&busfreq_dev->kobj, &dev_attr_enable.attr);
++ if (err) {
++ dev_err(busfreq_dev,
++ "Unable to register sysdev entry for BUSFREQ");
++ return err;
++ }
++ err = sysfs_create_file(&busfreq_dev->kobj, &dev_attr_vpu352.attr);
++ if (err) {
++ dev_err(busfreq_dev,
++ "Unable to register sysdev entry for BUSFREQ");
++ return err;
++ }
++
++ if (of_property_read_u32(pdev->dev.of_node, "fsl,max_ddr_freq",
++ &ddr_normal_rate)) {
++ dev_err(busfreq_dev, "max_ddr_freq entry missing\n");
++ return -EINVAL;
++ }
++#endif
++
++ high_bus_freq_mode = 1;
++ med_bus_freq_mode = 0;
++ low_bus_freq_mode = 0;
++ audio_bus_freq_mode = 0;
++ ultra_low_bus_freq_mode = 0;
++
++#ifdef CONFIG_ARM_IMX6Q_CPUFREQ
++ bus_freq_scaling_is_active = 1;
++ bus_freq_scaling_initialized = 1;
++
++ ddr_low_rate = LPAPM_CLK;
++ if (cpu_is_imx6q()) {
++ if (of_property_read_u32(pdev->dev.of_node, "fsl,med_ddr_freq",
++ &ddr_med_rate)) {
++ dev_info(busfreq_dev,
++ "DDR medium rate not supported.\n");
++ ddr_med_rate = ddr_normal_rate;
++ }
++ }
++
++ INIT_DELAYED_WORK(&low_bus_freq_handler, reduce_bus_freq_handler);
++ INIT_DELAYED_WORK(&bus_freq_daemon, bus_freq_daemon_handler);
++ register_pm_notifier(&imx_bus_freq_pm_notifier);
++ register_reboot_notifier(&imx_busfreq_reboot_notifier);
++
++ if (cpu_is_imx6sl())
++ err = init_mmdc_lpddr2_settings(pdev);
++ else
++ err = init_mmdc_ddr3_settings(pdev);
++ if (err) {
++ dev_err(busfreq_dev, "Busfreq init of MMDC failed\n");
++ return err;
++ }
++#endif
++ return 0;
++}
++
++static const struct of_device_id imx6_busfreq_ids[] = {
++ { .compatible = "fsl,imx6_busfreq", },
++ { /* sentinel */ }
++};
++
++static struct platform_driver busfreq_driver = {
++ .driver = {
++ .name = "imx6_busfreq",
++ .owner = THIS_MODULE,
++ .of_match_table = imx6_busfreq_ids,
++ },
++ .probe = busfreq_probe,
++};
++
++/*!
++ * Initialise the busfreq_driver.
++ *
++ * @return The function always returns 0.
++ */
++
++static int __init busfreq_init(void)
++{
++ if (vpu352) {
++ printk(KERN_INFO "VPU@352Mhz activated. Bus freq driver module not loading\n");
++ return 0;
++ }
++
++ if (platform_driver_register(&busfreq_driver) != 0)
++ return -ENODEV;
++
++ printk(KERN_INFO "Bus freq driver module loaded\n");
++
++ return 0;
++}
++
++static void __exit busfreq_cleanup(void)
++{
++#ifdef CONFIG_ARM_IMX6Q_CPUFREQ
++ sysfs_remove_file(&busfreq_dev->kobj, &dev_attr_enable.attr);
++
++ bus_freq_scaling_initialized = 0;
++#endif
++ /* Unregister the device structure */
++ platform_driver_unregister(&busfreq_driver);
++}
++
++__setup("vpu352=", vpu352_setup);
++module_init(busfreq_init);
++module_exit(busfreq_cleanup);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("BusFreq driver");
++MODULE_LICENSE("GPL");
+diff -Nur linux-4.1.3/arch/arm/mach-imx/busfreq_lpddr2.c linux-xbian-imx6/arch/arm/mach-imx/busfreq_lpddr2.c
+--- linux-4.1.3/arch/arm/mach-imx/busfreq_lpddr2.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/arch/arm/mach-imx/busfreq_lpddr2.c 2015-07-27 23:13:01.073153409 +0200
+@@ -0,0 +1,183 @@
++/*
++ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*!
++ * @file busfreq_lpddr2.c
++ *
++ * @brief iMX6 LPDDR2 frequency change specific file.
++ *
++ * @ingroup PM
++ */
++#include <asm/cacheflush.h>
++#include <asm/fncpy.h>
++#include <asm/io.h>
++#include <asm/mach/map.h>
++#include <asm/mach-types.h>
++#include <asm/tlb.h>
++#include <linux/clk.h>
++#include <linux/cpumask.h>
++#include <linux/delay.h>
++#include <linux/genalloc.h>
++#include <linux/interrupt.h>
++#include <linux/irqchip/arm-gic.h>
++#include <linux/kernel.h>
++#include <linux/mutex.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++#include <linux/proc_fs.h>
++#include <linux/sched.h>
++#include <linux/smp.h>
++
++#include "hardware.h"
++
++/* DDR settings */
++static void __iomem *mmdc_base;
++static void __iomem *anatop_base;
++static void __iomem *ccm_base;
++static void __iomem *l2_base;
++static struct device *busfreq_dev;
++static void *ddr_freq_change_iram_base;
++static int curr_ddr_rate;
++
++unsigned long reg_addrs[4];
++
++void (*mx6_change_lpddr2_freq)(u32 ddr_freq, int bus_freq_mode,
++ void *iram_addr) = NULL;
++
++extern unsigned int ddr_normal_rate;
++extern int low_bus_freq_mode;
++extern int ultra_low_bus_freq_mode;
++extern void mx6_lpddr2_freq_change(u32 freq, int bus_freq_mode,
++ void *iram_addr);
++
++
++#define LPDDR2_FREQ_CHANGE_SIZE 0x1000
++
++
++/* change the DDR frequency. */
++int update_lpddr2_freq(int ddr_rate)
++{
++ if (ddr_rate == curr_ddr_rate)
++ return 0;
++
++ dev_dbg(busfreq_dev, "\nBus freq set to %d start...\n", ddr_rate);
++
++ /*
++ * Flush the TLB, to ensure no TLB maintenance occurs
++ * when DDR is in self-refresh.
++ */
++ local_flush_tlb_all();
++ /* Now change DDR frequency. */
++ mx6_change_lpddr2_freq(ddr_rate,
++ (low_bus_freq_mode | ultra_low_bus_freq_mode),
++ reg_addrs);
++
++ curr_ddr_rate = ddr_rate;
++
++ dev_dbg(busfreq_dev, "\nBus freq set to %d done...\n", ddr_rate);
++
++ return 0;
++}
++
++int init_mmdc_lpddr2_settings(struct platform_device *busfreq_pdev)
++{
++ struct platform_device *ocram_dev;
++ unsigned int iram_paddr;
++ struct device_node *node;
++ struct gen_pool *iram_pool;
++
++ busfreq_dev = &busfreq_pdev->dev;
++ node = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-mmdc");
++ if (!node) {
++ printk(KERN_ERR "failed to find imx6sl-mmdc device tree data!\n");
++ return -EINVAL;
++ }
++ mmdc_base = of_iomap(node, 0);
++ WARN(!mmdc_base, "unable to map mmdc registers\n");
++
++ node = NULL;
++ node = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-ccm");
++ if (!node) {
++ printk(KERN_ERR "failed to find imx6sl-ccm device tree data!\n");
++ return -EINVAL;
++ }
++ ccm_base = of_iomap(node, 0);
++ WARN(!ccm_base, "unable to map ccm registers\n");
++
++ node = of_find_compatible_node(NULL, NULL, "arm,pl310-cache");
++ if (!node) {
++ printk(KERN_ERR "failed to find imx6sl-pl310-cache device tree data!\n");
++ return -EINVAL;
++ }
++ l2_base = of_iomap(node, 0);
++ WARN(!l2_base, "unable to map PL310 registers\n");
++
++ node = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-anatop");
++ if (!node) {
++ printk(KERN_ERR "failed to find imx6sl-pl310-cache device tree data!\n");
++ return -EINVAL;
++ }
++ anatop_base = of_iomap(node, 0);
++ WARN(!anatop_base, "unable to map anatop registers\n");
++
++ node = NULL;
++ node = of_find_compatible_node(NULL, NULL, "mmio-sram");
++ if (!node) {
++ dev_err(busfreq_dev, "%s: failed to find ocram node\n",
++ __func__);
++ return -EINVAL;
++ }
++
++ ocram_dev = of_find_device_by_node(node);
++ if (!ocram_dev) {
++ dev_err(busfreq_dev, "failed to find ocram device!\n");
++ return -EINVAL;
++ }
++
++ iram_pool = dev_get_gen_pool(&ocram_dev->dev);
++ if (!iram_pool) {
++ dev_err(busfreq_dev, "iram pool unavailable!\n");
++ return -EINVAL;
++ }
++
++ reg_addrs[0] = (unsigned long)anatop_base;
++ reg_addrs[1] = (unsigned long)ccm_base;
++ reg_addrs[2] = (unsigned long)mmdc_base;
++ reg_addrs[3] = (unsigned long)l2_base;
++
++ ddr_freq_change_iram_base = (void *)gen_pool_alloc(iram_pool,
++ LPDDR2_FREQ_CHANGE_SIZE);
++ if (!ddr_freq_change_iram_base) {
++ dev_err(busfreq_dev,
++ "Cannot alloc iram for ddr freq change code!\n");
++ return -ENOMEM;
++ }
++
++ iram_paddr = gen_pool_virt_to_phys(iram_pool,
++ (unsigned long)ddr_freq_change_iram_base);
++ /*
++ * Need to remap the area here since we want
++ * the memory region to be executable.
++ */
++ ddr_freq_change_iram_base = __arm_ioremap(iram_paddr,
++ LPDDR2_FREQ_CHANGE_SIZE,
++ MT_MEMORY_RWX_NONCACHED);
++ mx6_change_lpddr2_freq = (void *)fncpy(ddr_freq_change_iram_base,
++ &mx6_lpddr2_freq_change, LPDDR2_FREQ_CHANGE_SIZE);
++
++ curr_ddr_rate = ddr_normal_rate;
++
++ return 0;
++}
+diff -Nur linux-4.1.3/arch/arm/mach-imx/clk.h linux-xbian-imx6/arch/arm/mach-imx/clk.h
+--- linux-4.1.3/arch/arm/mach-imx/clk.h 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/arch/arm/mach-imx/clk.h 2015-07-27 23:13:01.085110746 +0200
+@@ -55,6 +55,34 @@
+ shift, 0, &imx_ccm_lock, share_count);
+ }
+
++static inline void imx_clk_prepare_enable(struct clk *clk)
++{
++ int ret = clk_prepare_enable(clk);
++
++ if (ret)
++ pr_err("failed to prepare and enable clk %s: %d\n",
++ __clk_get_name(clk), ret);
++}
++
++static inline int imx_clk_set_parent(struct clk *clk, struct clk *parent)
++{
++ int ret = clk_set_parent(clk, parent);
++
++ if (ret)
++ pr_err("failed to set parent of clk %s to %s: %d\n",
++ __clk_get_name(clk), __clk_get_name(parent), ret);
++ return ret;
++}
++
++static inline void imx_clk_set_rate(struct clk *clk, unsigned long rate)
++{
++ int ret = clk_set_rate(clk, rate);
++
++ if (ret)
++ pr_err("failed to set rate of clk %s to %ld: %d\n",
++ __clk_get_name(clk), rate, ret);
++}
++
+ struct clk *imx_clk_pfd(const char *name, const char *parent_name,
+ void __iomem *reg, u8 idx);
+
+diff -Nur linux-4.1.3/arch/arm/mach-imx/clk-imx6q.c linux-xbian-imx6/arch/arm/mach-imx/clk-imx6q.c
+--- linux-4.1.3/arch/arm/mach-imx/clk-imx6q.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/arch/arm/mach-imx/clk-imx6q.c 2015-07-27 23:13:01.081124967 +0200
+@@ -24,7 +24,6 @@
+ #include "clk.h"
+ #include "common.h"
+ #include "hardware.h"
+-
+ static const char *step_sels[] = { "osc", "pll2_pfd2_396m", };
+ static const char *pll1_sw_sels[] = { "pll1_sys", "step", };
+ static const char *periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll2_198m", };
+@@ -41,6 +40,8 @@
+ static const char *ipu_sels[] = { "mmdc_ch0_axi", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", };
+ static const char *ldb_di_sels[] = { "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "mmdc_ch1_axi", "pll3_usb_otg", };
+ static const char *ipu_di_pre_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd1_540m", };
++static const char *ldb_di0_div_sels[] = { "ldb_di0_div_3_5", "ldb_di0_div_7", };
++static const char *ldb_di1_div_sels[] = { "ldb_di1_div_3_5", "ldb_di1_div_7", };
+ static const char *ipu1_di0_sels[] = { "ipu1_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
+ static const char *ipu1_di1_sels[] = { "ipu1_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
+ static const char *ipu2_di0_sels[] = { "ipu2_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
+@@ -119,8 +120,118 @@
+ static unsigned int share_count_ssi1;
+ static unsigned int share_count_ssi2;
+ static unsigned int share_count_ssi3;
++static unsigned int share_count_spdif;
+ static unsigned int share_count_mipi_core_cfg;
+
++static void __iomem *ccm_base;
++
++static void init_ldb_clks(struct clk *new_parent)
++{
++ u32 reg;
++
++ /*
++ * Need to follow a strict procedure when changing the LDB
++ * clock, else we can introduce a glitch. Things to keep in
++ * mind:
++ * 1. The current and new parent clocks must be disabled.
++ * 2. The default clock for ldb_dio_clk is mmdc_ch1 which has
++ * no CG bit.
++ * 3. In the RTL implementation of the LDB_DI_CLK_SEL mux
++ * the top four options are in one mux and the PLL3 option along
++ * with another option is in the second mux. There is third mux
++ * used to decide between the first and second mux.
++ * The code below switches the parent to the bottom mux first
++ * and then manipulates the top mux. This ensures that no glitch
++ * will enter the divider.
++ *
++ * Need to disable MMDC_CH1 clock manually as there is no CG bit
++ * for this clock. The only way to disable this clock is to move
++ * it topll3_sw_clk and then to disable pll3_sw_clk
++ * Make sure periph2_clk2_sel is set to pll3_sw_clk
++ */
++ reg = readl_relaxed(ccm_base + 0x18);
++ reg &= ~(1 << 20);
++ writel_relaxed(reg, ccm_base + 0x18);
++
++ /*
++ * Set MMDC_CH1 mask bit.
++ */
++ reg = readl_relaxed(ccm_base + 0x4);
++ reg |= 1 << 16;
++ writel_relaxed(reg, ccm_base + 0x4);
++
++ /*
++ * Set the periph2_clk_sel to the top mux so that
++ * mmdc_ch1 is from pll3_sw_clk.
++ */
++ reg = readl_relaxed(ccm_base + 0x14);
++ reg |= 1 << 26;
++ writel_relaxed(reg, ccm_base + 0x14);
++
++ /*
++ * Wait for the clock switch.
++ */
++ while (readl_relaxed(ccm_base + 0x48))
++ ;
++
++ /*
++ * Disable pll3_sw_clk by selecting the bypass clock source.
++ */
++ reg = readl_relaxed(ccm_base + 0xc);
++ reg |= 1 << 0;
++ writel_relaxed(reg, ccm_base + 0xc);
++
++ /*
++ * Set the ldb_di0_clk and ldb_di1_clk to 111b.
++ */
++ reg = readl_relaxed(ccm_base + 0x2c);
++ reg |= ((7 << 9) | (7 << 12));
++ writel_relaxed(reg, ccm_base + 0x2c);
++
++ /*
++ * Set the ldb_di0_clk and ldb_di1_clk to 100b.
++ */
++ reg = readl_relaxed(ccm_base + 0x2c);
++ reg &= ~((7 << 9) | (7 << 12));
++ reg |= ((4 << 9) | (4 << 12));
++ writel_relaxed(reg, ccm_base + 0x2c);
++
++ /*
++ * Perform the LDB parent clock switch.
++ */
++ imx_clk_set_parent(clk[IMX6QDL_CLK_LDB_DI0_SEL], new_parent);
++ imx_clk_set_parent(clk[IMX6QDL_CLK_LDB_DI1_SEL], new_parent);
++
++ /*
++ * Unbypass pll3_sw_clk.
++ */
++ reg = readl_relaxed(ccm_base + 0xc);
++ reg &= ~(1 << 0);
++ writel_relaxed(reg, ccm_base + 0xc);
++
++ /*
++ * Set the periph2_clk_sel back to the bottom mux so that
++ * mmdc_ch1 is from its original parent.
++ */
++ reg = readl_relaxed(ccm_base + 0x14);
++ reg &= ~(1 << 26);
++ writel_relaxed(reg, ccm_base + 0x14);
++
++ /*
++ * Wait for the clock switch.
++ */
++ while (readl_relaxed(ccm_base + 0x48))
++ ;
++
++ /*
++ * Clear MMDC_CH1 mask bit.
++ */
++ reg = readl_relaxed(ccm_base + 0x4);
++ reg &= ~(1 << 16);
++ writel_relaxed(reg, ccm_base + 0x4);
++
++}
++
+ static void __init imx6q_clocks_init(struct device_node *ccm_node)
+ {
+ struct device_node *np;
+@@ -174,13 +285,13 @@
+ clk[IMX6QDL_PLL7_BYPASS] = imx_clk_mux_flags("pll7_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT);
+
+ /* Do not bypass PLLs initially */
+- clk_set_parent(clk[IMX6QDL_PLL1_BYPASS], clk[IMX6QDL_CLK_PLL1]);
+- clk_set_parent(clk[IMX6QDL_PLL2_BYPASS], clk[IMX6QDL_CLK_PLL2]);
+- clk_set_parent(clk[IMX6QDL_PLL3_BYPASS], clk[IMX6QDL_CLK_PLL3]);
+- clk_set_parent(clk[IMX6QDL_PLL4_BYPASS], clk[IMX6QDL_CLK_PLL4]);
+- clk_set_parent(clk[IMX6QDL_PLL5_BYPASS], clk[IMX6QDL_CLK_PLL5]);
+- clk_set_parent(clk[IMX6QDL_PLL6_BYPASS], clk[IMX6QDL_CLK_PLL6]);
+- clk_set_parent(clk[IMX6QDL_PLL7_BYPASS], clk[IMX6QDL_CLK_PLL7]);
++ imx_clk_set_parent(clk[IMX6QDL_PLL1_BYPASS], clk[IMX6QDL_CLK_PLL1]);
++ imx_clk_set_parent(clk[IMX6QDL_PLL2_BYPASS], clk[IMX6QDL_CLK_PLL2]);
++ imx_clk_set_parent(clk[IMX6QDL_PLL3_BYPASS], clk[IMX6QDL_CLK_PLL3]);
++ imx_clk_set_parent(clk[IMX6QDL_PLL4_BYPASS], clk[IMX6QDL_CLK_PLL4]);
++ imx_clk_set_parent(clk[IMX6QDL_PLL5_BYPASS], clk[IMX6QDL_CLK_PLL5]);
++ imx_clk_set_parent(clk[IMX6QDL_PLL6_BYPASS], clk[IMX6QDL_CLK_PLL6]);
++ imx_clk_set_parent(clk[IMX6QDL_PLL7_BYPASS], clk[IMX6QDL_CLK_PLL7]);
+
+ clk[IMX6QDL_CLK_PLL1_SYS] = imx_clk_gate("pll1_sys", "pll1_bypass", base + 0x00, 13);
+ clk[IMX6QDL_CLK_PLL2_BUS] = imx_clk_gate("pll2_bus", "pll2_bypass", base + 0x30, 13);
+@@ -259,7 +370,7 @@
+ clk[IMX6QDL_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
+
+ np = ccm_node;
+- base = of_iomap(np, 0);
++ ccm_base = base = of_iomap(np, 0);
+ WARN_ON(!base);
+
+ imx6q_pm_set_ccm_base(base);
+@@ -286,6 +397,8 @@
+ clk[IMX6QDL_CLK_IPU2_SEL] = imx_clk_mux("ipu2_sel", base + 0x3c, 14, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
+ clk[IMX6QDL_CLK_LDB_DI0_SEL] = imx_clk_mux_flags("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
+ clk[IMX6QDL_CLK_LDB_DI1_SEL] = imx_clk_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
++ clk[IMX6QDL_CLK_LDB_DI0_DIV_SEL] = imx_clk_mux_flags("ldb_di0_div_sel", base + 0x20, 10, 1, ldb_di0_div_sels, ARRAY_SIZE(ldb_di0_div_sels), CLK_SET_RATE_PARENT);
++ clk[IMX6QDL_CLK_LDB_DI1_DIV_SEL] = imx_clk_mux_flags("ldb_di1_div_sel", base + 0x20, 11, 1, ldb_di1_div_sels, ARRAY_SIZE(ldb_di1_div_sels), CLK_SET_RATE_PARENT);
+ clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL] = imx_clk_mux_flags("ipu1_di0_pre_sel", base + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
+ clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL] = imx_clk_mux_flags("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
+ clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL] = imx_clk_mux_flags("ipu2_di0_pre_sel", base + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
+@@ -335,9 +448,9 @@
+ clk[IMX6QDL_CLK_IPU1_PODF] = imx_clk_divider("ipu1_podf", "ipu1_sel", base + 0x3c, 11, 3);
+ clk[IMX6QDL_CLK_IPU2_PODF] = imx_clk_divider("ipu2_podf", "ipu2_sel", base + 0x3c, 16, 3);
+ clk[IMX6QDL_CLK_LDB_DI0_DIV_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
+- clk[IMX6QDL_CLK_LDB_DI0_PODF] = imx_clk_divider_flags("ldb_di0_podf", "ldb_di0_div_3_5", base + 0x20, 10, 1, 0);
++ clk[IMX6QDL_CLK_LDB_DI0_DIV_7] = imx_clk_fixed_factor("ldb_di0_div_7", "ldb_di0_sel", 1, 7);
+ clk[IMX6QDL_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
+- clk[IMX6QDL_CLK_LDB_DI1_PODF] = imx_clk_divider_flags("ldb_di1_podf", "ldb_di1_div_3_5", base + 0x20, 11, 1, 0);
++ clk[IMX6QDL_CLK_LDB_DI1_DIV_7] = imx_clk_fixed_factor("ldb_di1_div_7", "ldb_di1_sel", 1, 7);
+ clk[IMX6QDL_CLK_IPU1_DI0_PRE] = imx_clk_divider("ipu1_di0_pre", "ipu1_di0_pre_sel", base + 0x34, 3, 3);
+ clk[IMX6QDL_CLK_IPU1_DI1_PRE] = imx_clk_divider("ipu1_di1_pre", "ipu1_di1_pre_sel", base + 0x34, 12, 3);
+ clk[IMX6QDL_CLK_IPU2_DI0_PRE] = imx_clk_divider("ipu2_di0_pre", "ipu2_di0_pre_sel", base + 0x38, 3, 3);
+@@ -378,6 +491,8 @@
+ clk[IMX6QDL_CLK_CAN1_SERIAL] = imx_clk_gate2("can1_serial", "can_root", base + 0x68, 16);
+ clk[IMX6QDL_CLK_CAN2_IPG] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18);
+ clk[IMX6QDL_CLK_CAN2_SERIAL] = imx_clk_gate2("can2_serial", "can_root", base + 0x68, 20);
++ clk[IMX6QDL_CLK_DCIC1] = imx_clk_gate2("dcic1", "ipu1_podf", base + 0x68, 24);
++ clk[IMX6QDL_CLK_DCIC2] = imx_clk_gate2("dcic2", "ipu2_podf", base + 0x68, 26);
+ clk[IMX6QDL_CLK_ECSPI1] = imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0);
+ clk[IMX6QDL_CLK_ECSPI2] = imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2);
+ clk[IMX6QDL_CLK_ECSPI3] = imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4);
+@@ -414,9 +529,9 @@
+ clk[IMX6QDL_CLK_IPU1_DI1] = imx_clk_gate2("ipu1_di1", "ipu1_di1_sel", base + 0x74, 4);
+ clk[IMX6QDL_CLK_IPU2] = imx_clk_gate2("ipu2", "ipu2_podf", base + 0x74, 6);
+ clk[IMX6QDL_CLK_IPU2_DI0] = imx_clk_gate2("ipu2_di0", "ipu2_di0_sel", base + 0x74, 8);
+- clk[IMX6QDL_CLK_LDB_DI0] = imx_clk_gate2("ldb_di0", "ldb_di0_podf", base + 0x74, 12);
+- clk[IMX6QDL_CLK_LDB_DI1] = imx_clk_gate2("ldb_di1", "ldb_di1_podf", base + 0x74, 14);
+ clk[IMX6QDL_CLK_IPU2_DI1] = imx_clk_gate2("ipu2_di1", "ipu2_di1_sel", base + 0x74, 10);
++ clk[IMX6QDL_CLK_LDB_DI0] = imx_clk_gate2("ldb_di0", "ldb_di0_div_sel", base + 0x74, 12);
++ clk[IMX6QDL_CLK_LDB_DI1] = imx_clk_gate2("ldb_di1", "ldb_di1_div_sel", base + 0x74, 14);
+ clk[IMX6QDL_CLK_HSI_TX] = imx_clk_gate2_shared("hsi_tx", "hsi_tx_podf", base + 0x74, 16, &share_count_mipi_core_cfg);
+ clk[IMX6QDL_CLK_MIPI_CORE_CFG] = imx_clk_gate2_shared("mipi_core_cfg", "video_27m", base + 0x74, 16, &share_count_mipi_core_cfg);
+ clk[IMX6QDL_CLK_MIPI_IPG] = imx_clk_gate2_shared("mipi_ipg", "ipg", base + 0x74, 16, &share_count_mipi_core_cfg);
+@@ -446,7 +561,8 @@
+ clk[IMX6QDL_CLK_SATA] = imx_clk_gate2("sata", "ahb", base + 0x7c, 4);
+ clk[IMX6QDL_CLK_SDMA] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6);
+ clk[IMX6QDL_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12);
+- clk[IMX6QDL_CLK_SPDIF] = imx_clk_gate2("spdif", "spdif_podf", base + 0x7c, 14);
++ clk[IMX6QDL_CLK_SPDIF] = imx_clk_gate2_shared("spdif", "spdif_podf", base + 0x7c, 14, &share_count_spdif);
++ clk[IMX6QDL_CLK_SPDIF_GCLK] = imx_clk_gate2_shared("spdif_gclk", "ipg", base + 0x7c, 14, &share_count_spdif);
+ clk[IMX6QDL_CLK_SSI1_IPG] = imx_clk_gate2_shared("ssi1_ipg", "ipg", base + 0x7c, 18, &share_count_ssi1);
+ clk[IMX6QDL_CLK_SSI2_IPG] = imx_clk_gate2_shared("ssi2_ipg", "ipg", base + 0x7c, 20, &share_count_ssi2);
+ clk[IMX6QDL_CLK_SSI3_IPG] = imx_clk_gate2_shared("ssi3_ipg", "ipg", base + 0x7c, 22, &share_count_ssi3);
+@@ -479,54 +595,104 @@
+ clk_data.clk_num = ARRAY_SIZE(clk);
+ of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+
++ clk_register_clkdev(clk[IMX6QDL_CLK_GPT_3M], "gpt_3m", "imx-gpt.0");
+ clk_register_clkdev(clk[IMX6QDL_CLK_ENET_REF], "enet_ref", NULL);
+
+ if ((imx_get_soc_revision() != IMX_CHIP_REVISION_1_0) ||
+ cpu_is_imx6dl()) {
+- clk_set_parent(clk[IMX6QDL_CLK_LDB_DI0_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
+- clk_set_parent(clk[IMX6QDL_CLK_LDB_DI1_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
++ imx_clk_set_parent(clk[IMX6QDL_CLK_LDB_DI0_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
++ imx_clk_set_parent(clk[IMX6QDL_CLK_LDB_DI1_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
+ }
+
+- clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
+- clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
+- clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
+- clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
+- clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_SEL], clk[IMX6QDL_CLK_IPU1_DI0_PRE]);
+- clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_SEL], clk[IMX6QDL_CLK_IPU1_DI1_PRE]);
+- clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_SEL], clk[IMX6QDL_CLK_IPU2_DI0_PRE]);
+- clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI1_SEL], clk[IMX6QDL_CLK_IPU2_DI1_PRE]);
++ init_ldb_clks(clk[IMX6QDL_CLK_PLL2_PFD0_352M]);
++ imx_clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
++ imx_clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
++ imx_clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
++ imx_clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
++ imx_clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_SEL], clk[IMX6QDL_CLK_IPU1_DI0_PRE]);
++ imx_clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_SEL], clk[IMX6QDL_CLK_IPU1_DI1_PRE]);
++ imx_clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_SEL], clk[IMX6QDL_CLK_IPU2_DI0_PRE]);
++ imx_clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI1_SEL], clk[IMX6QDL_CLK_IPU2_DI1_PRE]);
++
++ if (cpu_is_imx6dl())
++ imx_clk_set_parent(clk[IMX6QDL_CLK_IPU1_SEL], clk[IMX6QDL_CLK_PLL3_PFD1_540M]);
+
+ /*
+ * The gpmi needs 100MHz frequency in the EDO/Sync mode,
+ * We can not get the 100MHz from the pll2_pfd0_352m.
+ * So choose pll2_pfd2_396m as enfc_sel's parent.
+ */
+- clk_set_parent(clk[IMX6QDL_CLK_ENFC_SEL], clk[IMX6QDL_CLK_PLL2_PFD2_396M]);
+-
+- for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
+- clk_prepare_enable(clk[clks_init_on[i]]);
++ imx_clk_set_parent(clk[IMX6QDL_CLK_ENFC_SEL], clk[IMX6QDL_CLK_PLL2_PFD2_396M]);
+
++ /* gpu clock initilazation */
++ /*
++ * On mx6dl, 2d core clock sources(sel, podf) is from 3d
++ * shader core clock, but 3d shader clock multiplexer of
++ * mx6dl is different. For instance the equivalent of
++ * pll2_pfd_594M on mx6q is pll2_pfd_528M on mx6dl.
++ * Make a note here.
++ */
++#if 0
++ imx_clk_set_parent(clk[IMX6QDL_CLK_GPU3D_SHADER_SEL], clk[IMX6QDL_CLK_PLL2_PFD1_594M]);
++ if (cpu_is_imx6dl()) {
++ imx_clk_set_rate(clk[IMX6QDL_CLK_GPU3D_SHADER], 528000000);
++ /* for mx6dl, change gpu3d_core parent to 594_PFD*/
++ imx_clk_set_parent(clk[IMX6QDL_CLK_GPU3D_CORE_SEL], clk[IMX6QDL_CLK_PLL2_PFD1_594M]);
++ imx_clk_set_rate(clk[IMX6QDL_CLK_GPU3D_CORE], 528000000);
++ /* for mx6dl, change gpu2d_core parent to 594_PFD*/
++ imx_clk_set_parent(clk[IMX6QDL_CLK_GPU2D_CORE_SEL], clk[IMX6QDL_CLK_PLL2_PFD1_594M]);
++ imx_clk_set_rate(clk[IMX6QDL_CLK_GPU2D_CORE], 528000000);
++ } else if (cpu_is_imx6q()) {
++ imx_clk_set_rate(clk[IMX6QDL_CLK_GPU3D_SHADER], 594000000);
++ imx_clk_set_parent(clk[IMX6QDL_CLK_GPU3D_CORE_SEL], clk[IMX6QDL_CLK_MMDC_CH0_AXI]);
++ imx_clk_set_rate(clk[IMX6QDL_CLK_GPU3D_CORE], 528000000);
++ imx_clk_set_parent(clk[IMX6QDL_CLK_GPU2D_CORE_SEL], clk[IMX6QDL_CLK_PLL3_USB_OTG]);
++ imx_clk_set_rate(clk[IMX6QDL_CLK_GPU2D_CORE], 480000000);
++ }
++#endif
+ if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
+- clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY1_GATE]);
+- clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY2_GATE]);
++ imx_clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY1_GATE]);
++ imx_clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY2_GATE]);
+ }
+
+ /*
+ * Let's initially set up CLKO with OSC24M, since this configuration
+ * is widely used by imx6q board designs to clock audio codec.
+ */
+- ret = clk_set_parent(clk[IMX6QDL_CLK_CKO2_SEL], clk[IMX6QDL_CLK_OSC]);
++ ret = imx_clk_set_parent(clk[IMX6QDL_CLK_CKO2_SEL], clk[IMX6QDL_CLK_OSC]);
+ if (!ret)
+- ret = clk_set_parent(clk[IMX6QDL_CLK_CKO], clk[IMX6QDL_CLK_CKO2]);
++ ret = imx_clk_set_parent(clk[IMX6QDL_CLK_CKO], clk[IMX6QDL_CLK_CKO2]);
+ if (ret)
+ pr_warn("failed to set up CLKO: %d\n", ret);
+
+ /* Audio-related clocks configuration */
+- clk_set_parent(clk[IMX6QDL_CLK_SPDIF_SEL], clk[IMX6QDL_CLK_PLL3_PFD3_454M]);
++ imx_clk_set_parent(clk[IMX6QDL_CLK_SPDIF_SEL], clk[IMX6QDL_CLK_PLL3_PFD3_454M]);
+
+ /* All existing boards with PCIe use LVDS1 */
+ if (IS_ENABLED(CONFIG_PCI_IMX6))
+- clk_set_parent(clk[IMX6QDL_CLK_LVDS1_SEL], clk[IMX6QDL_CLK_SATA_REF_100M]);
++ imx_clk_set_parent(clk[IMX6QDL_CLK_LVDS1_SEL], clk[IMX6QDL_CLK_SATA_REF_100M]);
++
++ /*
++ * Enable clocks only after both parent and rate are all initialized
++ * as needed
++ */
++ for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
++ imx_clk_prepare_enable(clk[clks_init_on[i]]);
++
++ /*
++ * If VPU 352M is enabled, then PLL2_PDF2 need to be
++ * set to 352M, cpufreq will be disabled as VDDSOC/PU
++ * need to be at highest voltage, scaling cpu freq is
++ * not saving any power, and busfreq will be also disabled
++ * as the PLL2_PFD2 is not at default freq, in a word,
++ * all modules that sourceing clk from PLL2_PFD2 will
++ * be impacted.
++ */
++ if (vpu352) {
++ clk_set_rate(clk[IMX6QDL_CLK_PLL2_PFD2_396M], 352000000);
++ clk_set_parent(clk[IMX6QDL_CLK_VPU_AXI_SEL], clk[IMX6QDL_CLK_PLL2_PFD2_396M]);
++ pr_info("VPU 352M is enabled!\n");
++ }
+
+ /* Set initial power mode */
+ imx6q_set_lpm(WAIT_CLOCKED);
+diff -Nur linux-4.1.3/arch/arm/mach-imx/clk-pllv3.c linux-xbian-imx6/arch/arm/mach-imx/clk-pllv3.c
+--- linux-4.1.3/arch/arm/mach-imx/clk-pllv3.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/arch/arm/mach-imx/clk-pllv3.c 2015-07-27 23:13:01.085110746 +0200
+@@ -23,6 +23,7 @@
+ #define PLL_DENOM_OFFSET 0x20
+
+ #define BM_PLL_POWER (0x1 << 12)
++#define BM_PLL_BYPASS (0x1 << 16)
+ #define BM_PLL_LOCK (0x1 << 31)
+
+ /**
+@@ -237,9 +238,10 @@
+ struct clk_pllv3 *pll = to_clk_pllv3(hw);
+ unsigned long min_rate = parent_rate * 27;
+ unsigned long max_rate = parent_rate * 54;
+- u32 val, div;
++ u32 val, newval, div;
+ u32 mfn, mfd = 1000000;
+ s64 temp64;
++ int ret;
+
+ if (rate < min_rate || rate > max_rate)
+ return -EINVAL;
+@@ -251,13 +253,27 @@
+ mfn = temp64;
+
+ val = readl_relaxed(pll->base);
+- val &= ~pll->div_mask;
+- val |= div;
+- writel_relaxed(val, pll->base);
++
++ /* set the PLL into bypass mode */
++ newval = val | BM_PLL_BYPASS;
++ writel_relaxed(newval, pll->base);
++
++ /* configure the new frequency */
++ newval &= ~pll->div_mask;
++ newval |= div;
++ writel_relaxed(newval, pll->base);
+ writel_relaxed(mfn, pll->base + PLL_NUM_OFFSET);
+ writel_relaxed(mfd, pll->base + PLL_DENOM_OFFSET);
+
+- return clk_pllv3_wait_lock(pll);
++ ret = clk_pllv3_wait_lock(pll);
++ if (ret == 0 && val & BM_PLL_POWER) {
++ /* only if it locked can we switch back to the PLL */
++ newval &= ~BM_PLL_BYPASS;
++ newval |= val & BM_PLL_BYPASS;
++ writel_relaxed(newval, pll->base);
++ }
++
++ return ret;
+ }
+
+ static const struct clk_ops clk_pllv3_av_ops = {
+diff -Nur linux-4.1.3/arch/arm/mach-imx/common.h linux-xbian-imx6/arch/arm/mach-imx/common.h
+--- linux-4.1.3/arch/arm/mach-imx/common.h 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/arch/arm/mach-imx/common.h 2015-07-27 23:13:01.085110746 +0200
+@@ -56,6 +56,7 @@
+ void mxc_set_cpu_type(unsigned int type);
+ void mxc_restart(enum reboot_mode, const char *);
+ void mxc_arch_reset_init(void __iomem *);
++void mxc_arch_reset_init_dt(void);
+ int mx51_revision(void);
+ int mx53_revision(void);
+ void imx_set_aips(void __iomem *);
+@@ -86,6 +87,8 @@
+ MX3_SLEEP,
+ };
+
++extern int vpu352;
++
+ void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode);
+ void imx_print_silicon_rev(const char *cpu, int srev);
+
+@@ -102,6 +105,7 @@
+ static inline void imx_smp_prepare(void) {}
+ #endif
+ void imx_src_init(void);
++
+ void imx_gpc_pre_suspend(bool arm_power_off);
+ void imx_gpc_post_resume(void);
+ void imx_gpc_mask_all(void);
+diff -Nur linux-4.1.3/arch/arm/mach-imx/ddr3_freq_imx6.S linux-xbian-imx6/arch/arm/mach-imx/ddr3_freq_imx6.S
+--- linux-4.1.3/arch/arm/mach-imx/ddr3_freq_imx6.S 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/arch/arm/mach-imx/ddr3_freq_imx6.S 2015-07-27 23:13:01.089096525 +0200
+@@ -0,0 +1,893 @@
++/*
++ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++#include <linux/linkage.h>
++
++#define MMDC0_MDPDC 0x4
++#define MMDC0_MDCF0 0x0c
++#define MMDC0_MDCF1 0x10
++#define MMDC0_MDMISC 0x18
++#define MMDC0_MDSCR 0x1c
++#define MMDC0_MAPSR 0x404
++#define MMDC0_MADPCR0 0x410
++#define MMDC0_MPZQHWCTRL 0x800
++#define MMDC1_MPZQHWCTRL 0x4800
++#define MMDC0_MPODTCTRL 0x818
++#define MMDC1_MPODTCTRL 0x4818
++#define MMDC0_MPDGCTRL0 0x83c
++#define MMDC1_MPDGCTRL0 0x483c
++#define MMDC0_MPMUR0 0x8b8
++#define MMDC1_MPMUR0 0x48b8
++
++#define CCM_CBCDR 0x14
++#define CCM_CBCMR 0x18
++#define CCM_CSCMR1 0x1c
++#define CCM_CDHIPR 0x48
++
++#define L2_CACHE_SYNC 0x730
++
++ .align 3
++
++ .macro switch_to_528MHz
++
++ /* check if periph_clk_sel is already set */
++ ldr r0, [r6, #CCM_CBCDR]
++ and r0, r0, #(1 << 25)
++ cmp r0, #(1 << 25)
++ beq set_ahb_podf_before_switch
++
++ /* change periph_clk to be sourced from pll3_clk. */
++ ldr r0, [r6, #CCM_CBCMR]
++ bic r0, r0, #(3 << 12)
++ str r0, [r6, #CCM_CBCMR]
++
++ ldr r0, [r6, #CCM_CBCDR]
++ bic r0, r0, #(0x38 << 20)
++ str r0, [r6, #CCM_CBCDR]
++
++ /*
++ * set the AHB dividers before the switch,
++ * don't change AXI clock divider,
++ * set the MMDC_DIV=1, AXI_DIV = 2, AHB_DIV=4,
++ */
++ ldr r0, [r6, #CCM_CBCDR]
++ ldr r2, =0x3f1f00
++ bic r0, r0, r2
++ orr r0, r0, #0xd00
++ orr r0, r0, #(1 << 16)
++ str r0, [r6, #CCM_CBCDR]
++
++wait_div_update528:
++ ldr r0, [r6, #CCM_CDHIPR]
++ cmp r0, #0
++ bne wait_div_update528
++
++ /* now switch periph_clk to pll3_main_clk. */
++ ldr r0, [r6, #CCM_CBCDR]
++ orr r0, r0, #(1 << 25)
++ str r0, [r6, #CCM_CBCDR]
++
++periph_clk_switch3:
++ ldr r0, [r6, #CCM_CDHIPR]
++ cmp r0, #0
++ bne periph_clk_switch3
++
++ b switch_pre_periph_clk_528
++
++set_ahb_podf_before_switch:
++ /*
++ * set the MMDC_DIV=1, AXI_DIV = 2, AHB_DIV=4,
++ */
++ ldr r0, [r6, #CCM_CBCDR]
++ ldr r2, =0x3f1f00
++ bic r0, r0, r2
++ orr r0, r0, #0xd00
++ orr r0, r0, #(1 << 16)
++ str r0, [r6, #CCM_CBCDR]
++
++wait_div_update528_1:
++ ldr r0, [r6, #CCM_CDHIPR]
++ cmp r0, #0
++ bne wait_div_update528_1
++
++switch_pre_periph_clk_528:
++
++ /* now switch pre_periph_clk to PLL2_528MHz. */
++ ldr r0, [r6, #CCM_CBCMR]
++ bic r0, r0, #(0xc << 16)
++ str r0, [r6, #CCM_CBCMR]
++
++ /* now switch periph_clk back. */
++ ldr r0, [r6, #CCM_CBCDR]
++ bic r0, r0, #(1 << 25)
++ str r0, [r6, #CCM_CBCDR]
++
++periph_clk_switch4:
++ ldr r0, [r6, #CCM_CDHIPR]
++ cmp r0, #0
++ bne periph_clk_switch4
++
++ .endm
++
++ .macro switch_to_400MHz
++
++ /* check if periph_clk_sel is already set. */
++ ldr r0, [r6, #CCM_CBCDR]
++ and r0, r0, #(1 << 25)
++ cmp r0, #(1 << 25)
++ beq set_ahb_podf_before_switch1
++
++ /* change periph_clk to be sourced from pll3_clk. */
++ ldr r0, [r6, #CCM_CBCMR]
++ bic r0, r0, #(3 << 12)
++ str r0, [r6, #CCM_CBCMR]
++
++ ldr r0, [r6, #CCM_CBCDR]
++ bic r0, r0, #(0x38 << 24)
++ str r0, [r6, #CCM_CBCDR]
++
++ /* now switch periph_clk to pll3_main_clk. */
++ ldr r0, [r6, #CCM_CBCDR]
++ orr r0, r0, #(1 << 25)
++ str r0, [r6, #CCM_CBCDR]
++
++periph_clk_switch5:
++ ldr r0, [r6, #CCM_CDHIPR]
++ cmp r0, #0
++ bne periph_clk_switch5
++
++ b switch_pre_periph_clk_400
++
++set_ahb_podf_before_switch1:
++ /*
++ * set the MMDC_DIV=1, AXI_DIV = 2, AHB_DIV=4,
++ */
++ ldr r0, [r6, #CCM_CBCDR]
++ ldr r2, =0x3f1f00
++ bic r0, r0, r2
++ orr r0, r0, #(0x9 << 8)
++ orr r0, r0, #(1 << 16)
++ str r0, [r6, #CCM_CBCDR]
++
++wait_div_update400_1:
++ ldr r0, [r6, #CCM_CDHIPR]
++ cmp r0, #0
++ bne wait_div_update400_1
++
++switch_pre_periph_clk_400:
++
++ /* now switch pre_periph_clk to PFD_400MHz. */
++ ldr r0, [r6, #CCM_CBCMR]
++ bic r0, r0, #(0xc << 16)
++ orr r0, r0, #(0x4 << 16)
++ str r0, [r6, #CCM_CBCMR]
++
++ /* now switch periph_clk back. */
++ ldr r0, [r6, #CCM_CBCDR]
++ bic r0, r0, #(1 << 25)
++ str r0, [r6, #CCM_CBCDR]
++
++periph_clk_switch6:
++ ldr r0, [r6, #CCM_CDHIPR]
++ cmp r0, #0
++ bne periph_clk_switch6
++
++ /*
++ * change AHB divider so that we are at 400/3=133MHz.
++ * don't change AXI clock divider.
++ * set the MMDC_DIV=1, AXI_DIV=2, AHB_DIV=3,
++ */
++ ldr r0, [r6, #CCM_CBCDR]
++ ldr r2, =0x3f1f00
++ bic r0, r0, r2
++ orr r0, r0, #(0x9 << 8)
++ orr r0, r0, #(1 << 16)
++ str r0, [r6, #CCM_CBCDR]
++
++wait_div_update400_2:
++ ldr r0, [r6, #CCM_CDHIPR]
++ cmp r0, #0
++ bne wait_div_update400_2
++
++ .endm
++
++ .macro switch_to_50MHz
++
++ /* check if periph_clk_sel is already set. */
++ ldr r0, [r6, #CCM_CBCDR]
++ and r0, r0, #(1 << 25)
++ cmp r0, #(1 << 25)
++ beq switch_pre_periph_clk_50
++
++ /*
++ * set the periph_clk to be sourced from PLL2_PFD_200M
++ * change periph_clk to be sourced from pll3_clk.
++ * ensure PLL3 is the source and set the divider to 1.
++ */
++ ldr r0, [r6, #CCM_CBCMR]
++ bic r0, r0, #(0x3 << 12)
++ str r0, [r6, #CCM_CBCMR]
++
++ ldr r0, [r6, #CCM_CBCDR]
++ bic r0, r0, #(0x38 << 24)
++ str r0, [r6, #CCM_CBCDR]
++
++ /* now switch periph_clk to pll3_main_clk. */
++ ldr r0, [r6, #CCM_CBCDR]
++ orr r0, r0, #(1 << 25)
++ str r0, [r6, #CCM_CBCDR]
++
++periph_clk_switch_50:
++ ldr r0, [r6, #CCM_CDHIPR]
++ cmp r0, #0
++ bne periph_clk_switch_50
++
++switch_pre_periph_clk_50:
++
++ /* now switch pre_periph_clk to PFD_200MHz. */
++ ldr r0, [r6, #CCM_CBCMR]
++ orr r0, r0, #(0xc << 16)
++ str r0, [r6, #CCM_CBCMR]
++
++ /*
++ * set the MMDC_DIV=4, AXI_DIV = 4, AHB_DIV=8,
++ */
++ ldr r0, [r6, #CCM_CBCDR]
++ ldr r2, =0x3f1f00
++ bic r0, r0, r2
++ orr r0, r0, #(0x18 << 16)
++ orr r0, r0, #(0x3 << 16)
++
++ /*
++ * if changing AHB divider remember to change
++ * the IPGPER divider too below.
++ */
++ orr r0, r0, #0x1d00
++ str r0, [r6, #CCM_CBCDR]
++
++wait_div_update_50:
++ ldr r0, [r6, #CCM_CDHIPR]
++ cmp r0, #0
++ bne wait_div_update_50
++
++ /* now switch periph_clk back. */
++ ldr r0, [r6, #CCM_CBCDR]
++ bic r0, r0, #(1 << 25)
++ str r0, [r6, #CCM_CBCDR]
++
++periph_clk_switch2:
++ ldr r0, [r6, #CCM_CDHIPR]
++ cmp r0, #0
++ bne periph_clk_switch2
++
++ .endm
++
++ .macro switch_to_24MHz
++ /*
++ * change the freq now try setting DDR to 24MHz.
++ * source it from the periph_clk2 ensure the
++ * periph_clk2 is sourced from 24MHz and the
++ * divider is 1.
++ */
++
++ ldr r0, [r6, #CCM_CBCMR]
++ bic r0, r0, #(0x3 << 12)
++ orr r0, r0, #(1 << 12)
++ str r0, [r6, #CCM_CBCMR]
++
++ ldr r0, [r6, #CCM_CBCDR]
++ bic r0, r0, #(0x38 << 24)
++ str r0, [r6, #CCM_CBCDR]
++
++ /* now switch periph_clk to 24MHz. */
++ ldr r0, [r6, #CCM_CBCDR]
++ orr r0, r0, #(1 << 25)
++ str r0, [r6, #CCM_CBCDR]
++
++periph_clk_switch1:
++ ldr r0, [r6, #CCM_CDHIPR]
++ cmp r0, #0
++ bne periph_clk_switch1
++
++ /* change all the dividers to 1. */
++ ldr r0, [r6, #CCM_CBCDR]
++ ldr r2, =0x3f1f00
++ bic r0, r0, r2
++ orr r0, r0, #(1 << 8)
++ str r0, [r6, #CCM_CBCDR]
++
++ /* Wait for the divider to change. */
++wait_div_update:
++ ldr r0, [r6, #CCM_CDHIPR]
++ cmp r0, #0
++ bne wait_div_update
++
++ .endm
++
++/*
++ * mx6_ddr3_freq_change
++ *
++ * idle the processor (eg, wait for interrupt).
++ * make sure DDR is in self-refresh.
++ * IRQs are already disabled.
++ */
++ENTRY(mx6_ddr3_freq_change)
++
++ stmfd sp!, {r4-r12}
++
++ /*
++ * r5 -> mmdc_base
++ * r6 -> ccm_base
++ * r7 -> iomux_base
++ * r12 -> l2_base
++ */
++ mov r4, r0
++ mov r8, r1
++ mov r9, r2
++ mov r11, r3
++
++ /*
++ * Get the addresses of the registers.
++ * They are last few entries in the
++ * ddr_settings parameter.
++ * The first entry contains the count,
++ * and each entry is 2 words.
++ */
++ ldr r0, [r1]
++ add r0, r0, #1
++ lsl r0, r0, #3
++ add r1, r0, r1
++ /* mmdc_base. */
++ ldr r5, [r1]
++ add r1, #8
++ /* ccm_base */
++ ldr r6, [r1]
++ add r1, #8
++ /*iomux_base */
++ ldr r7, [r1]
++ add r1, #8
++ /*l2_base */
++ ldr r12, [r1]
++
++ddr_freq_change:
++ /*
++ * make sure no TLB miss will occur when
++ * the DDR is in self refresh. invalidate
++ * TLB single entry to ensure that the
++ * address is not already in the TLB.
++ */
++
++ adr r10, ddr_freq_change
++
++ ldr r2, [r6]
++ ldr r2, [r5]
++ ldr r2, [r7]
++ ldr r2, [r8]
++ ldr r2, [r10]
++ ldr r2, [r11]
++ ldr r2, [r12]
++
++#ifdef CONFIG_CACHE_L2X0
++ /*
++ * Make sure the L2 buffers are drained.
++ * Sync operation on L2 drains the buffers.
++ */
++ mov r1, #0x0
++ str r1, [r12, #L2_CACHE_SYNC]
++#endif
++
++ /* disable automatic power saving. */
++ ldr r0, [r5, #MMDC0_MAPSR]
++ orr r0, r0, #0x01
++ str r0, [r5, #MMDC0_MAPSR]
++
++ /* disable MMDC power down timer. */
++ ldr r0, [r5, #MMDC0_MDPDC]
++ bic r0, r0, #(0xff << 8)
++ str r0, [r5, #MMDC0_MDPDC]
++
++ /* delay for a while */
++ ldr r1, =4
++delay1:
++ ldr r2, =0
++cont1:
++ ldr r0, [r5, r2]
++ add r2, r2, #4
++ cmp r2, #16
++ bne cont1
++ sub r1, r1, #1
++ cmp r1, #0
++ bgt delay1
++
++ /* set CON_REG */
++ ldr r0, =0x8000
++ str r0, [r5, #MMDC0_MDSCR]
++poll_conreq_set_1:
++ ldr r0, [r5, #MMDC0_MDSCR]
++ and r0, r0, #(0x4 << 12)
++ cmp r0, #(0x4 << 12)
++ bne poll_conreq_set_1
++
++ ldr r0, =0x00008050
++ str r0, [r5, #MMDC0_MDSCR]
++ ldr r0, =0x00008058
++ str r0, [r5, #MMDC0_MDSCR]
++
++ /*
++ * if requested frequency is greater than
++ * 300MHz go to DLL on mode.
++ */
++ ldr r1, =300000000
++ cmp r4, r1
++ bge dll_on_mode
++
++dll_off_mode:
++
++ /* if DLL is currently on, turn it off. */
++ cmp r9, #1
++ beq continue_dll_off_1
++
++ ldr r0, =0x00018031
++ str r0, [r5, #MMDC0_MDSCR]
++
++ ldr r0, =0x00018039
++ str r0, [r5, #MMDC0_MDSCR]
++
++ ldr r1, =10
++delay1a:
++ ldr r2, =0
++cont1a:
++ ldr r0, [r5, r2]
++ add r2, r2, #4
++ cmp r2, #16
++ bne cont1a
++ sub r1, r1, #1
++ cmp r1, #0
++ bgt delay1a
++
++continue_dll_off_1:
++ /* set DVFS - enter self refresh mode */
++ ldr r0, [r5, #MMDC0_MAPSR]
++ orr r0, r0, #(1 << 21)
++ str r0, [r5, #MMDC0_MAPSR]
++
++ /* de-assert con_req */
++ mov r0, #0x0
++ str r0, [r5, #MMDC0_MDSCR]
++
++poll_dvfs_set_1:
++ ldr r0, [r5, #MMDC0_MAPSR]
++ and r0, r0, #(1 << 25)
++ cmp r0, #(1 << 25)
++ bne poll_dvfs_set_1
++
++ ldr r1, =24000000
++ cmp r4, r1
++ beq switch_freq_24
++
++ switch_to_50MHz
++ b continue_dll_off_2
++
++switch_freq_24:
++ switch_to_24MHz
++
++continue_dll_off_2:
++
++ /* set SBS - block ddr accesses */
++ ldr r0, [r5, #MMDC0_MADPCR0]
++ orr r0, r0, #(1 << 8)
++ str r0, [r5, #MMDC0_MADPCR0]
++
++ /* clear DVFS - exit from self refresh mode */
++ ldr r0, [r5, #MMDC0_MAPSR]
++ bic r0, r0, #(1 << 21)
++ str r0, [r5, #MMDC0_MAPSR]
++
++poll_dvfs_clear_1:
++ ldr r0, [r5, #MMDC0_MAPSR]
++ and r0, r0, #(1 << 25)
++ cmp r0, #(1 << 25)
++ beq poll_dvfs_clear_1
++
++ /* if DLL was previously on, continue DLL off routine. */
++ cmp r9, #1
++ beq continue_dll_off_3
++
++ ldr r0, =0x00018031
++ str r0, [r5, #MMDC0_MDSCR]
++
++ ldr r0, =0x00018039
++ str r0, [r5, #MMDC0_MDSCR]
++
++ ldr r0, =0x08208030
++ str r0, [r5, #MMDC0_MDSCR]
++
++ ldr r0, =0x08208038
++ str r0, [r5, #MMDC0_MDSCR]
++
++ ldr r0, =0x00088032
++ str r0, [r5, #MMDC0_MDSCR]
++
++ ldr r0, =0x0008803A
++ str r0, [r5, #MMDC0_MDSCR]
++
++ /* delay for a while. */
++ ldr r1, =4
++delay_1:
++ ldr r2, =0
++cont_1:
++ ldr r0, [r5, r2]
++ add r2, r2, #4
++ cmp r2, #16
++ bne cont_1
++ sub r1, r1, #1
++ cmp r1, #0
++ bgt delay_1
++
++ ldr r0, [r5, #MMDC0_MDCF0]
++ bic r0, r0, #0xf
++ orr r0, r0, #0x3
++ str r0, [r5, #MMDC0_MDCF0]
++
++ ldr r0, [r5, #MMDC0_MDCF1]
++ bic r0, r0, #0x7
++ orr r0, r0, #0x4
++ str r0, [r5, #MMDC0_MDCF1]
++
++ ldr r0, =0x00011680
++ str r0, [r5, #MMDC0_MDMISC]
++
++ /* enable dqs pull down in the IOMUX. */
++ ldr r1, [r11]
++ add r11, r11, #8
++ ldr r2, =0x3028
++update_iomux:
++ ldr r0, [r11, #0x0]
++ ldr r3, [r7, r0]
++ bic r3, r3, r2
++ orr r3, r3, #(0x3 << 12)
++ orr r3, r3, #0x28
++ str r3, [r7, r0]
++ add r11, r11, #8
++ sub r1, r1, #1
++ cmp r1, #0
++ bgt update_iomux
++
++ /* ODT disabled. */
++ ldr r0, =0x0
++ ldr r2, =MMDC0_MPODTCTRL
++ str r0, [r5, r2]
++ ldr r2, =MMDC1_MPODTCTRL
++ str r0, [r5, r2]
++
++ /* DQS gating disabled. */
++ ldr r2, =MMDC0_MPDGCTRL0
++ ldr r0, [r5, r2]
++ orr r0, r0, #(1 << 29)
++ str r0, [r5, r2]
++
++ ldr r2, =MMDC1_MPDGCTRL0
++ ldr r0, [r5, r2]
++ orr r0, r0, #(0x1 << 29)
++ str r0, [r5, r2]
++
++ /* MMDC0_MAPSR adopt power down enable. */
++ ldr r0, [r5, #MMDC0_MAPSR]
++ bic r0, r0, #0x01
++ str r0, [r5, #MMDC0_MAPSR]
++
++ /* frc_msr + mu bypass */
++ ldr r0, =0x00000060
++ str r0, [r5, #MMDC0_MPMUR0]
++ ldr r2, =MMDC1_MPMUR0
++ str r0, [r5, r2]
++ ldr r0, =0x00000460
++ str r0, [r5, #MMDC0_MPMUR0]
++ ldr r2, =MMDC1_MPMUR0
++ str r0, [r5, r2]
++ ldr r0, =0x00000c60
++ str r0, [r5, #MMDC0_MPMUR0]
++ ldr r2, =MMDC1_MPMUR0
++ str r0, [r5, r2]
++
++continue_dll_off_3:
++ /* clear SBS - unblock accesses to DDR. */
++ ldr r0, [r5, #MMDC0_MADPCR0]
++ bic r0, r0, #(0x1 << 8)
++ str r0, [r5, #MMDC0_MADPCR0]
++
++ mov r0, #0x0
++ str r0, [r5, #MMDC0_MDSCR]
++poll_conreq_clear_1:
++ ldr r0, [r5, #MMDC0_MDSCR]
++ and r0, r0, #(0x4 << 12)
++ cmp r0, #(0x4 << 12)
++ beq poll_conreq_clear_1
++
++ b done
++
++dll_on_mode:
++ /* assert DVFS - enter self refresh mode. */
++ ldr r0, [r5, #MMDC0_MAPSR]
++ orr r0, r0, #(1 << 21)
++ str r0, [r5, #MMDC0_MAPSR]
++
++ /* de-assert CON_REQ. */
++ mov r0, #0x0
++ str r0, [r5, #MMDC0_MDSCR]
++
++ /* poll DVFS ack. */
++poll_dvfs_set_2:
++ ldr r0, [r5, #MMDC0_MAPSR]
++ and r0, r0, #(1 << 25)
++ cmp r0, #(1 << 25)
++ bne poll_dvfs_set_2
++
++ ldr r1, =528000000
++ cmp r4, r1
++ beq switch_freq_528
++
++ switch_to_400MHz
++
++ b continue_dll_on
++
++switch_freq_528:
++ switch_to_528MHz
++
++continue_dll_on:
++
++ /* set SBS step-by-step mode. */
++ ldr r0, [r5, #MMDC0_MADPCR0]
++ orr r0, r0, #( 1 << 8)
++ str r0, [r5, #MMDC0_MADPCR0]
++
++ /* clear DVFS - exit self refresh mode. */
++ ldr r0, [r5, #MMDC0_MAPSR]
++ bic r0, r0, #(1 << 21)
++ str r0, [r5, #MMDC0_MAPSR]
++
++poll_dvfs_clear_2:
++ ldr r0, [r5, #MMDC0_MAPSR]
++ and r0, r0, #(1 << 25)
++ cmp r0, #(1 << 25)
++ beq poll_dvfs_clear_2
++
++ /* if DLL is currently off, turn it back on. */
++ cmp r9, #0
++ beq update_calibration_only
++
++ ldr r0, =0xa5390003
++ str r0, [r5, #MMDC0_MPZQHWCTRL]
++ ldr r2, =MMDC1_MPZQHWCTRL
++ str r0, [r5, r2]
++
++ /* enable DQS gating. */
++ ldr r2, =MMDC0_MPDGCTRL0
++ ldr r0, [r5, r2]
++ bic r0, r0, #(1 << 29)
++ str r0, [r5, r2]
++
++ ldr r2, =MMDC1_MPDGCTRL0
++ ldr r0, [r5, r2]
++ bic r0, r0, #(1 << 29)
++ str r0, [r5, r2]
++
++ /* force measure. */
++ ldr r0, =0x00000800
++ str r0, [r5, #MMDC0_MPMUR0]
++ ldr r2, =MMDC1_MPMUR0
++ str r0, [r5, r2]
++
++ /* delay for while. */
++ ldr r1, =4
++delay5:
++ ldr r2, =0
++cont5:
++ ldr r0, [r5, r2]
++ add r2, r2, #4
++ cmp r2, #16
++ bne cont5
++ sub r1, r1, #1
++ cmp r1, #0
++ bgt delay5
++
++ /* disable dqs pull down in the IOMUX. */
++ ldr r1, [r11]
++ add r11, r11, #8
++update_iomux1:
++ ldr r0, [r11, #0x0]
++ ldr r3, [r11, #0x4]
++ str r3, [r7, r0]
++ add r11, r11, #8
++ sub r1, r1, #1
++ cmp r1, #0
++ bgt update_iomux1
++
++ /* config MMDC timings to 528MHz. */
++ ldr r9, [r8]
++ add r8, r8, #8
++ ldr r0, [r8, #0x0]
++ ldr r3, [r8, #0x4]
++ str r3, [r5, r0]
++ add r8, r8, #8
++
++ ldr r0, [r8, #0x0]
++ ldr r3, [r8, #0x4]
++ str r3, [r5, r0]
++ add r8, r8, #8
++
++ /* update MISC register: WALAT, RALAT */
++ ldr r0, =0x00001740
++ str r0, [r5, #MMDC0_MDMISC]
++
++ /* configure ddr devices to dll on, odt. */
++ ldr r0, =0x00048031
++ str r0, [r5, #MMDC0_MDSCR]
++
++ ldr r0, =0x00048039
++ str r0, [r5, #MMDC0_MDSCR]
++
++ /* delay for while. */
++ ldr r1, =4
++delay7:
++ ldr r2, =0
++cont7:
++ ldr r0, [r5, r2]
++ add r2, r2, #4
++ cmp r2, #16
++ bne cont7
++ sub r1, r1, #1
++ cmp r1, #0
++ bgt delay7
++
++ /* reset dll. */
++ ldr r0, =0x09408030
++ str r0, [r5, #MMDC0_MDSCR]
++
++ ldr r0, =0x09408038
++ str r0, [r5, #MMDC0_MDSCR]
++
++ /* delay for while. */
++ ldr r1, =100
++delay8:
++ ldr r2, =0
++cont8:
++ ldr r0, [r5, r2]
++ add r2, r2, #4
++ cmp r2, #16
++ bne cont8
++ sub r1, r1, #1
++ cmp r1, #0
++ bgt delay8
++
++ ldr r0, [r8, #0x0]
++ ldr r3, [r8, #0x4]
++ str r3, [r5, r0]
++ add r8, r8, #8
++
++ ldr r0, [r8, #0x0]
++ ldr r3, [r8, #0x4]
++ str r3, [r5, r0]
++ add r8, r8, #8
++
++ ldr r0, =0x00428031
++ str r0, [r5, #MMDC0_MDSCR]
++
++ ldr r0, =0x00428039
++ str r0, [r5, #MMDC0_MDSCR]
++
++ ldr r0, [r8, #0x0]
++ ldr r3, [r8, #0x4]
++ str r3, [r5, r0]
++ add r8, r8, #8
++
++ ldr r0, [r8, #0x0]
++ ldr r3, [r8, #0x4]
++ str r3, [r5, r0]
++ add r8, r8, #8
++
++ /* issue a zq command. */
++ ldr r0, =0x04008040
++ str r0, [r5, #MMDC0_MDSCR]
++
++ ldr r0, =0x04008048
++ str r0, [r5, #MMDC0_MDSCR]
++
++ /* MMDC ODT enable. */
++ ldr r0, [r8, #0x0]
++ ldr r3, [r8, #0x4]
++ str r3, [r5, r0]
++ add r8, r8, #8
++
++ ldr r2, =0x4818
++ str r3, [r5, r2]
++
++ /* delay for while. */
++ ldr r1, =40
++delay15:
++ ldr r2, =0
++cont15:
++ ldr r0, [r5, r2]
++ add r2, r2, #4
++ cmp r2, #16
++ bne cont15
++ sub r1, r1, #1
++ cmp r1, #0
++ bgt delay15
++
++ /* MMDC0_MAPSR adopt power down enable. */
++ ldr r0, [r5, #MMDC0_MAPSR]
++ bic r0, r0, #0x01
++ str r0, [r5, #MMDC0_MAPSR]
++
++ /* enable MMDC power down timer. */
++ ldr r0, [r5, #MMDC0_MDPDC]
++ orr r0, r0, #(0x55 << 8)
++ str r0, [r5, #MMDC0_MDPDC]
++
++ b update_calibration
++
++update_calibration_only:
++ ldr r1, [r8]
++ sub r1, r1, #7
++ add r8, r8, #64
++ b update_calib
++
++update_calibration:
++ /* write the new calibration values. */
++ mov r1, r9
++ sub r1, r1, #7
++
++update_calib:
++ ldr r0, [r8, #0x0]
++ ldr r3, [r8, #0x4]
++ str r3, [r5, r0]
++ add r8, r8, #8
++ sub r1, r1, #1
++ cmp r1, #0
++ bgt update_calib
++
++ /* perform a force measurement. */
++ ldr r0, =0x800
++ str r0, [r5, #MMDC0_MPMUR0]
++ ldr r2, =MMDC1_MPMUR0
++ str r0, [r5, r2]
++
++ /* clear SBS - unblock DDR accesses. */
++ ldr r0, [r5, #MMDC0_MADPCR0]
++ bic r0, r0, #(1 << 8)
++ str r0, [r5, #MMDC0_MADPCR0]
++
++ mov r0, #0x0
++ str r0, [r5, #MMDC0_MDSCR]
++poll_conreq_clear_2:
++ ldr r0, [r5, #MMDC0_MDSCR]
++ and r0, r0, #(0x4 << 12)
++ cmp r0, #(0x4 << 12)
++ beq poll_conreq_clear_2
++
++done:
++ /* restore registers */
++
++ ldmfd sp!, {r4-r12}
++ mov pc, lr
++
++ .type mx6_do_ddr3_freq_change, #object
++ENTRY(mx6_do_ddr_freq_change)
++ .word mx6_ddr3_freq_change
++ .size mx6_ddr3_freq_change, . - mx6_ddr3_freq_change
+diff -Nur linux-4.1.3/arch/arm/mach-imx/Kconfig linux-xbian-imx6/arch/arm/mach-imx/Kconfig
+--- linux-4.1.3/arch/arm/mach-imx/Kconfig 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/arch/arm/mach-imx/Kconfig 2015-07-27 23:13:01.053224513 +0200
+@@ -1,5 +1,6 @@
+ menuconfig ARCH_MXC
+ bool "Freescale i.MX family" if ARCH_MULTI_V4_V5 || ARCH_MULTI_V6_V7
++ select ARCH_HAS_RESET_CONTROLLER
+ select ARCH_REQUIRE_GPIOLIB
+ select ARM_CPU_SUSPEND if PM
+ select CLKSRC_MMIO
+@@ -8,6 +9,7 @@
+ select PM_OPP if PM
+ select SOC_BUS
+ select SRAM
++ select ZONE_DMA
+ help
+ Support for Freescale MXC/iMX-based family of processors
+
+@@ -58,7 +60,6 @@
+
+ config HAVE_IMX_SRC
+ def_bool y if SMP
+- select ARCH_HAS_RESET_CONTROLLER
+
+ config IMX_HAVE_IOMUX_V1
+ bool
+diff -Nur linux-4.1.3/arch/arm/mach-imx/lpddr2_freq_imx6.S linux-xbian-imx6/arch/arm/mach-imx/lpddr2_freq_imx6.S
+--- linux-4.1.3/arch/arm/mach-imx/lpddr2_freq_imx6.S 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/arch/arm/mach-imx/lpddr2_freq_imx6.S 2015-07-27 23:13:01.093082305 +0200
+@@ -0,0 +1,484 @@
++/*
++ * Copyright (C) 2012-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++#include <linux/linkage.h>
++
++ .macro mx6sl_switch_to_24MHz
++
++ /*
++ * Set MMDC clock to be sourced from PLL3.
++ * Ensure first periph2_clk2 is sourced from PLL3.
++ * Set the PERIPH2_CLK2_PODF to divide by 2.
++ */
++ ldr r6, [r2, #0x14]
++ bic r6, r6, #0x7
++ orr r6, r6, #0x1
++ str r6, [r2, #0x14]
++
++ /* Select PLL3 to source MMDC. */
++ ldr r6, [r2, #0x18]
++ bic r6, r6, #0x100000
++ str r6, [r2, #0x18]
++
++ /* Swtich periph2_clk_sel to run from PLL3. */
++ ldr r6, [r2, #0x14]
++ orr r6, r6, #0x4000000
++ str r6, [r2, #0x14]
++
++periph2_clk_switch1:
++ ldr r6, [r2, #0x48]
++ cmp r6, #0
++ bne periph2_clk_switch1
++
++ /*
++ * Need to clock gate the 528 PFDs before
++ * powering down PLL2.
++ * Only the PLL2_PFD2_400M should be ON
++ * at this time, so only clock gate that one.
++ */
++ ldr r6, [r3, #0x100]
++ orr r6, r6, #0x800000
++ str r6, [r3, #0x100]
++
++ /*
++ * Set PLL2 to bypass state. We should be here
++ * only if MMDC is not sourced from PLL2.
++ */
++ ldr r6, [r3, #0x30]
++ orr r6, r6, #0x10000
++ str r6, [r3, #0x30]
++
++ ldr r6, [r3, #0x30]
++ orr r6, r6, #0x1000
++ str r6, [r3, #0x30]
++
++ /* Ensure pre_periph2_clk_mux is set to pll2 */
++ ldr r6, [r2, #0x18]
++ bic r6, r6, #0x600000
++ str r6, [r2, #0x18]
++
++ /* Set MMDC clock to be sourced from the bypassed PLL2. */
++ ldr r6, [r2, #0x14]
++ bic r6, r6, #0x4000000
++ str r6, [r2, #0x14]
++
++periph2_clk_switch2:
++ ldr r6, [r2, #0x48]
++ cmp r6, #0
++ bne periph2_clk_switch2
++
++ /*
++ * Now move MMDC back to periph2_clk2 source.
++ * after selecting PLL2 as the option.
++ * Select PLL2 as the source.
++ */
++ ldr r6, [r2, #0x18]
++ orr r6, r6, #0x100000
++ str r6, [r2, #0x18]
++
++ /* set periph2_clk2_podf to divide by 1. */
++ ldr r6, [r2, #0x14]
++ bic r6, r6, #0x7
++ str r6, [r2, #0x14]
++
++ /* Now move periph2_clk to periph2_clk2 source */
++ ldr r6, [r2, #0x14]
++ orr r6, r6, #0x4000000
++ str r6, [r2, #0x14]
++
++periph2_clk_switch3:
++ ldr r6, [r2, #0x48]
++ cmp r6, #0
++ bne periph2_clk_switch3
++
++ /* Now set the MMDC PODF back to 1.*/
++ ldr r6, [r2, #0x14]
++ bic r6, r6, #0x38
++ str r6, [r2, #0x14]
++
++mmdc_podf0:
++ ldr r6, [r2, #0x48]
++ cmp r6, #0
++ bne mmdc_podf0
++
++ .endm
++
++ .macro ddr_switch_400MHz
++
++ /* Set MMDC divider first, in case PLL3 is at 480MHz. */
++ ldr r6, [r3, #0x10]
++ and r6, r6, #0x10000
++ cmp r6, #0x10000
++ beq pll3_in_bypass
++
++ /* Set MMDC divder to divide by 2. */
++ ldr r6, [r2, #0x14]
++ bic r6, r6, #0x38
++ orr r6, r6, #0x8
++ str r6, [r2, #0x14]
++
++mmdc_podf:
++ ldr r6, [r2, #0x48]
++ cmp r6, #0
++ bne mmdc_podf
++
++pll3_in_bypass:
++ /*
++ * Check if we are switching between
++ * 400Mhz <-> 100MHz.If so, we should
++ * try to source MMDC from PLL2_200M.
++ */
++ cmp r1, #0
++ beq not_low_bus_freq
++
++ /* Ensure that MMDC is sourced from PLL2 mux first. */
++ ldr r6, [r2, #0x14]
++ bic r6, r6, #0x4000000
++ str r6, [r2, #0x14]
++
++periph2_clk_switch4:
++ ldr r6, [r2, #0x48]
++ cmp r6, #0
++ bne periph2_clk_switch4
++
++not_low_bus_freq:
++ /* Now ensure periph2_clk2_sel mux is set to PLL3 */
++ ldr r6, [r2, #0x18]
++ bic r6, r6, #0x100000
++ str r6, [r2, #0x18]
++
++ /* Now switch MMDC to PLL3. */
++ ldr r6, [r2, #0x14]
++ orr r6, r6, #0x4000000
++ str r6, [r2, #0x14]
++
++periph2_clk_switch5:
++ ldr r6, [r2, #0x48]
++ cmp r6, #0
++ bne periph2_clk_switch5
++
++ /*
++ * Check if PLL2 is already unlocked.
++ * If so do nothing with PLL2.
++ */
++ cmp r1, #0
++ beq pll2_already_on
++
++ /* Now power up PLL2 and unbypass it. */
++ ldr r6, [r3, #0x30]
++ bic r6, r6, #0x1000
++ str r6, [r3, #0x30]
++
++ /* Make sure PLL2 has locked.*/
++wait_for_pll_lock:
++ ldr r6, [r3, #0x30]
++ and r6, r6, #0x80000000
++ cmp r6, #0x80000000
++ bne wait_for_pll_lock
++
++ ldr r6, [r3, #0x30]
++ bic r6, r6, #0x10000
++ str r6, [r3, #0x30]
++
++ /*
++ * Need to enable the 528 PFDs after
++ * powering up PLL2.
++ * Only the PLL2_PFD2_400M should be ON
++ * as it feeds the MMDC. Rest should have
++ * been managed by clock code.
++ */
++ ldr r6, [r3, #0x100]
++ bic r6, r6, #0x800000
++ str r6, [r3, #0x100]
++
++pll2_already_on:
++ /*
++ * Now switch MMDC clk back to pll2_mux option.
++ * Ensure pre_periph2_clk2 is set to pll2_pfd_400M.
++ * If switching to audio DDR freq, set the
++ * pre_periph2_clk2 to PLL2_PFD_200M
++ */
++ ldr r6, =400000000
++ cmp r6, r0
++ bne use_pll2_pfd_200M
++
++ ldr r6, [r2, #0x18]
++ bic r6, r6, #0x600000
++ orr r6, r6, #0x200000
++ str r6, [r2, #0x18]
++ ldr r6, =400000000
++ b cont2
++
++use_pll2_pfd_200M:
++ ldr r6, [r2, #0x18]
++ orr r6, r6, #0x600000
++ str r6, [r2, #0x18]
++ ldr r6, =200000000
++
++cont2:
++ ldr r4, [r2, #0x14]
++ bic r4, r4, #0x4000000
++ str r4, [r2, #0x14]
++
++periph2_clk_switch6:
++ ldr r4, [r2, #0x48]
++ cmp r4, #0
++ bne periph2_clk_switch6
++
++change_divider_only:
++ /*
++ * Calculate the MMDC divider
++ * based on the requested freq.
++ */
++ ldr r4, =0
++Loop2:
++ sub r6, r6, r0
++ cmp r6, r0
++ blt Div_Found
++ add r4, r4, #1
++ bgt Loop2
++
++ /* Shift divider into correct offset. */
++ lsl r4, r4, #3
++Div_Found:
++ /* Set the MMDC PODF. */
++ ldr r6, [r2, #0x14]
++ bic r6, r6, #0x38
++ orr r6, r6, r4
++ str r6, [r2, #0x14]
++
++mmdc_podf1:
++ ldr r6, [r2, #0x48]
++ cmp r6, #0
++ bne mmdc_podf1
++
++ .endm
++
++ .macro mmdc_clk_lower_100MHz
++
++ /*
++ * Prior to reducing the DDR frequency (at 528/400 MHz),
++ * read the Measure unit count bits (MU_UNIT_DEL_NUM)
++ */
++ ldr r5, =0x8B8
++ ldr r6, [r8, r5]
++ /* Original MU unit count */
++ mov r6, r6, LSR #16
++ ldr r4, =0x3FF
++ and r6, r6, r4
++ /* Original MU unit count * 2 */
++ mov r7, r6, LSL #1
++ /*
++ * Bypass the automatic measure unit when below 100 MHz
++ * by setting the Measure unit bypass enable bit (MU_BYP_EN)
++ */
++ ldr r6, [r8, r5]
++ orr r6, r6, #0x400
++ str r6, [r8, r5]
++ /*
++ * Double the measure count value read in step 1 and program it in the
++ * measurement bypass bits (MU_BYP_VAL) of the MMDC PHY Measure Unit
++ * Register for the reduced frequency operation below 100 MHz
++ */
++ ldr r6, [r8, r5]
++ ldr r4, =0x3FF
++ bic r6, r6, r4
++ orr r6, r6, r7
++ str r6, [r8, r5]
++ /* Now perform a Force Measurement. */
++ ldr r6, [r8, r5]
++ orr r6, r6, #0x800
++ str r6, [r8, r5]
++ /* Wait for FRC_MSR to clear. */
++force_measure:
++ ldr r6, [r8, r5]
++ and r6, r6, #0x800
++ cmp r6, #0x0
++ bne force_measure
++
++ .endm
++
++ .macro mmdc_clk_above_100MHz
++
++ /* Make sure that the PHY measurement unit is NOT in bypass mode */
++ ldr r5, =0x8B8
++ ldr r6, [r8, r5]
++ bic r6, r6, #0x400
++ str r6, [r8, r5]
++ /* Now perform a Force Measurement. */
++ ldr r6, [r8, r5]
++ orr r6, r6, #0x800
++ str r6, [r8, r5]
++ /* Wait for FRC_MSR to clear. */
++force_measure1:
++ ldr r6, [r8, r5]
++ and r6, r6, #0x800
++ cmp r6, #0x0
++ bne force_measure1
++ .endm
++
++/*
++ * mx6_lpddr2_freq_change
++ *
++ * Make sure DDR is in self-refresh.
++ * IRQs are already disabled.
++ * r0 : DDR freq.
++ * r1: low_bus_freq_mode flag
++ * r2: Pointer to array containing addresses of registers.
++ */
++ .align 3
++ENTRY(mx6_lpddr2_freq_change)
++
++ push {r4-r10}
++
++ mov r4, r2
++ ldr r3, [r4] @ANATOP_BASE_ADDR
++ ldr r2, [r4, #0x4] @CCM_BASE_ADDR
++ ldr r8, [r4, #0x8] @MMDC_P0_BASE_ADDR
++ ldr r7, [r4, #0xC] @L2_BASE_ADDR
++
++lpddr2_freq_change:
++ adr r9, lpddr2_freq_change
++
++ /* Prime all TLB entries. */
++ ldr r6, [r9]
++ ldr r6, [r8]
++ ldr r6, [r3]
++ ldr r6, [r2]
++
++ /* Drain all the L1 buffers. */
++ dsb
++
++#ifdef CONFIG_CACHE_L2X0
++ /*
++ * Need to make sure the buffers in L2 are drained.
++ * Performing a sync operation does this.
++ */
++ mov r6, #0x0
++ str r6, [r7, #0x730]
++#endif
++
++ /*
++ * The second dsb might be needed to keep cache sync (device write)
++ * ordering with the memory accesses before it.
++ */
++ dsb
++ isb
++
++ /* Disable Automatic power savings. */
++ ldr r6, [r8, #0x404]
++ orr r6, r6, #0x01
++ str r6, [r8, #0x404]
++
++ /* MMDC0_MDPDC disable power down timer */
++ ldr r6, [r8, #0x4]
++ bic r6, r6, #0xff00
++ str r6, [r8, #0x4]
++
++ /* Delay for a while */
++ ldr r10, =10
++delay1:
++ ldr r7, =0
++cont1:
++ ldr r6, [r8, r7]
++ add r7, r7, #4
++ cmp r7, #16
++ bne cont1
++ sub r10, r10, #1
++ cmp r10, #0
++ bgt delay1
++
++ /* Make the DDR explicitly enter self-refresh. */
++ ldr r6, [r8, #0x404]
++ orr r6, r6, #0x200000
++ str r6, [r8, #0x404]
++
++poll_dvfs_set_1:
++ ldr r6, [r8, #0x404]
++ and r6, r6, #0x2000000
++ cmp r6, #0x2000000
++ bne poll_dvfs_set_1
++
++ /* set SBS step-by-step mode */
++ ldr r6, [r8, #0x410]
++ orr r6, r6, #0x100
++ str r6, [r8, #0x410]
++
++ ldr r10, =100000000
++ cmp r0, r10
++ bgt set_ddr_mu_above_100
++ mmdc_clk_lower_100MHz
++
++set_ddr_mu_above_100:
++ ldr r10, =24000000
++ cmp r0, r10
++ beq set_to_24MHz
++
++ ddr_switch_400MHz
++
++ ldr r10,=100000000
++ cmp r0, r10
++ blt done
++ mmdc_clk_above_100MHz
++
++ b done
++
++set_to_24MHz:
++ mx6sl_switch_to_24MHz
++
++done:
++ /* clear DVFS - exit from self refresh mode */
++ ldr r6, [r8, #0x404]
++ bic r6, r6, #0x200000
++ str r6, [r8, #0x404]
++
++poll_dvfs_clear_1:
++ ldr r6, [r8, #0x404]
++ and r6, r6, #0x2000000
++ cmp r6, #0x2000000
++ beq poll_dvfs_clear_1
++
++ /* Enable Automatic power savings. */
++ ldr r6, [r8, #0x404]
++ bic r6, r6, #0x01
++ str r6, [r8, #0x404]
++
++ ldr r10, =24000000
++ cmp r0, r10
++ beq skip_power_down
++
++ /* Enable MMDC power down timer. */
++ ldr r6, [r8, #0x4]
++ orr r6, r6, #0x5500
++ str r6, [r8, #0x4]
++
++skip_power_down:
++ /* clear SBS - unblock DDR accesses */
++ ldr r6, [r8, #0x410]
++ bic r6, r6, #0x100
++ str r6, [r8, #0x410]
++
++ pop {r4-r10}
++
++ /* Restore registers */
++ mov pc, lr
++
++ .type mx6_lpddr2_do_iram, #object
++ENTRY(mx6_lpddr2_do_iram)
++ .word mx6_lpddr2_freq_change
++ .size mx6_lpddr2_freq_change, . - mx6_lpddr2_freq_change
+diff -Nur linux-4.1.3/arch/arm/mach-imx/mach-imx6q.c linux-xbian-imx6/arch/arm/mach-imx/mach-imx6q.c
+--- linux-4.1.3/arch/arm/mach-imx/mach-imx6q.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/arch/arm/mach-imx/mach-imx6q.c 2015-07-27 23:13:01.097068084 +0200
+@@ -265,10 +265,12 @@
+ static void __init imx6q_init_machine(void)
+ {
+ struct device *parent;
++ void __iomem *p;
+
+ imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q",
+ imx_get_soc_revision());
+
++ mxc_arch_reset_init_dt();
+ parent = imx_soc_device_init();
+ if (parent == NULL)
+ pr_warn("failed to initialize soc device\n");
+@@ -281,6 +283,12 @@
+ cpu_is_imx6q() ? imx6q_pm_init() : imx6dl_pm_init();
+ imx6q_1588_init();
+ imx6q_axi_init();
++
++ p = ioremap(0x21b0000, SZ_4K);
++ if (p) {
++ writel(0x7f, p + 0x40);
++ iounmap(p);
++ }
+ }
+
+ #define OCOTP_CFG3 0x440
+@@ -330,6 +338,12 @@
+ if (dev_pm_opp_disable(cpu_dev, 852000000))
+ pr_warn("failed to disable 852 MHz OPP\n");
+ }
++ if (vpu352) {
++ if (dev_pm_opp_disable(cpu_dev, 396000000))
++ pr_warn("VPU352: failed to disable 396MHz OPP\n");
++ pr_info("VPU352: remove 396MHz OPP for VPU running at 352MHz!\n");
++ }
++
+ iounmap(base);
+ put_node:
+ of_node_put(np);
+@@ -408,4 +422,5 @@
+ .init_machine = imx6q_init_machine,
+ .init_late = imx6q_init_late,
+ .dt_compat = imx6q_dt_compat,
++ .restart = mxc_restart,
+ MACHINE_END
+diff -Nur linux-4.1.3/arch/arm/mach-imx/Makefile linux-xbian-imx6/arch/arm/mach-imx/Makefile
+--- linux-4.1.3/arch/arm/mach-imx/Makefile 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/arch/arm/mach-imx/Makefile 2015-07-27 23:13:01.053224513 +0200
+@@ -28,6 +28,12 @@
+ obj-$(CONFIG_MXC_USE_EPIT) += epit.o
+ obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o
+
++obj-y += busfreq-imx6.o
++ifdef CONFIG_ARM_IMX6Q_CPUFREQ
++obj-$(CONFIG_SOC_IMX6Q) += ddr3_freq_imx6.o busfreq_ddr3.o
++obj-$(CONFIG_SOC_IMX6SL) += lpddr2_freq_imx6.o busfreq_lpddr2.o
++endif
++
+ ifeq ($(CONFIG_CPU_IDLE),y)
+ obj-$(CONFIG_SOC_IMX5) += cpuidle-imx5.o
+ obj-$(CONFIG_SOC_IMX6Q) += cpuidle-imx6q.o
+diff -Nur linux-4.1.3/arch/arm/mach-imx/src.c linux-xbian-imx6/arch/arm/mach-imx/src.c
+--- linux-4.1.3/arch/arm/mach-imx/src.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/arch/arm/mach-imx/src.c 2015-07-27 23:13:01.097068084 +0200
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright 2011 Freescale Semiconductor, Inc.
++ * Copyright 2011-2014 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+@@ -18,6 +18,7 @@
+ #include <linux/smp.h>
+ #include <asm/smp_plat.h>
+ #include "common.h"
++#include "hardware.h"
+
+ #define SRC_SCR 0x000
+ #define SRC_GPR1 0x020
+@@ -32,6 +33,7 @@
+
+ static void __iomem *src_base;
+ static DEFINE_SPINLOCK(scr_lock);
++static bool m4_is_enabled;
+
+ static const int sw_reset_bits[5] = {
+ BP_SRC_SCR_SW_GPU_RST,
+@@ -41,6 +43,11 @@
+ BP_SRC_SCR_SW_IPU2_RST
+ };
+
++bool imx_src_is_m4_enabled(void)
++{
++ return m4_is_enabled;
++}
++
+ static int imx_src_reset_module(struct reset_controller_dev *rcdev,
+ unsigned long sw_reset_idx)
+ {
+@@ -136,6 +143,14 @@
+ */
+ spin_lock(&scr_lock);
+ val = readl_relaxed(src_base + SRC_SCR);
++
++ /* bit 4 is m4c_non_sclr_rst on i.MX6SX */
++ if (cpu_is_imx6sx() && ((val &
++ (1 << BP_SRC_SCR_SW_OPEN_VG_RST)) == 0))
++ m4_is_enabled = true;
++ else
++ m4_is_enabled = false;
++
+ val &= ~(1 << BP_SRC_SCR_WARM_RESET_ENABLE);
+ writel_relaxed(val, src_base + SRC_SCR);
+ spin_unlock(&scr_lock);
+diff -Nur linux-4.1.3/arch/arm/mach-imx/system.c linux-xbian-imx6/arch/arm/mach-imx/system.c
+--- linux-4.1.3/arch/arm/mach-imx/system.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/arch/arm/mach-imx/system.c 2015-07-27 23:13:01.101053863 +0200
+@@ -34,6 +34,7 @@
+
+ static void __iomem *wdog_base;
+ static struct clk *wdog_clk;
++static u32 wdog_source = 1; /* use WDOG1 default */
+
+ /*
+ * Reset the system. It is called by machine_restart().
+@@ -50,6 +51,17 @@
+
+ if (cpu_is_mx1())
+ wcr_enable = (1 << 0);
++ /*
++ * Some i.MX6 boards use WDOG2 to reset external pmic in bypass mode,
++ * so do WDOG2 reset here. Do not set SRS, since we will
++ * trigger external POR later. Use WDOG1 to reset in ldo-enable
++ * mode. You can set it by "fsl,wdog-reset" in dts.
++ * For i.MX6SX we have to trigger wdog-reset to reset QSPI-NOR flash to
++ * workaround qspi-nor reboot issue whatever ldo-bypass or not.
++ */
++ else if ((wdog_source == 2 && (cpu_is_imx6q() || cpu_is_imx6dl() ||
++ cpu_is_imx6sl())) || cpu_is_imx6sx())
++ wcr_enable = 0x14;
+ else
+ wcr_enable = (1 << 2);
+
+@@ -89,6 +101,41 @@
+ clk_prepare(wdog_clk);
+ }
+
++void __init mxc_arch_reset_init_dt(void)
++{
++ struct device_node *np = NULL;
++
++ if (cpu_is_imx6q() || cpu_is_imx6dl())
++ np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpc");
++ else if (cpu_is_imx6sl())
++ np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-gpc");
++
++ if (np)
++ of_property_read_u32(np, "fsl,wdog-reset", &wdog_source);
++ pr_info("Use WDOG%d as reset source\n", wdog_source);
++
++ np = of_find_compatible_node(NULL, NULL, "fsl,imx21-wdt");
++ wdog_base = of_iomap(np, 0);
++ WARN_ON(!wdog_base);
++
++ /* Some i.MX6 boards use WDOG2 to reset board in ldo-bypass mode */
++ if (wdog_source == 2 && (cpu_is_imx6q() || cpu_is_imx6dl() ||
++ cpu_is_imx6sl())) {
++ np = of_find_compatible_node(np, NULL, "fsl,imx21-wdt");
++ wdog_base = of_iomap(np, 0);
++ WARN_ON(!wdog_base);
++ }
++
++ wdog_clk = of_clk_get(np, 0);
++ if (IS_ERR(wdog_clk)) {
++ pr_warn("%s: failed to get wdog clock\n", __func__);
++ wdog_clk = NULL;
++ return;
++ }
++
++ clk_prepare(wdog_clk);
++}
++
+ #ifdef CONFIG_CACHE_L2X0
+ void __init imx_init_l2cache(void)
+ {
+diff -Nur linux-4.1.3/arch/arm/mm/cache-v7.S linux-xbian-imx6/arch/arm/mm/cache-v7.S
+--- linux-4.1.3/arch/arm/mm/cache-v7.S 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/arch/arm/mm/cache-v7.S 2015-07-27 23:13:01.503617563 +0200
+@@ -446,3 +446,5 @@
+
+ @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
+ define_cache_functions v7
++
++ .long v7_dma_flush_range
+diff -Nur linux-4.1.3/block/bfq-cgroup.c linux-xbian-imx6/block/bfq-cgroup.c
+--- linux-4.1.3/block/bfq-cgroup.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/block/bfq-cgroup.c 2015-07-27 23:13:03.600137415 +0200
+@@ -0,0 +1,936 @@
++/*
++ * BFQ: CGROUPS support.
++ *
++ * Based on ideas and code from CFQ:
++ * Copyright (C) 2003 Jens Axboe <axboe@kernel.dk>
++ *
++ * Copyright (C) 2008 Fabio Checconi <fabio@gandalf.sssup.it>
++ * Paolo Valente <paolo.valente@unimore.it>
++ *
++ * Copyright (C) 2010 Paolo Valente <paolo.valente@unimore.it>
++ *
++ * Licensed under the GPL-2 as detailed in the accompanying COPYING.BFQ
++ * file.
++ */
++
++#ifdef CONFIG_CGROUP_BFQIO
++
++static DEFINE_MUTEX(bfqio_mutex);
++
++static bool bfqio_is_removed(struct bfqio_cgroup *bgrp)
++{
++ return bgrp ? !bgrp->online : false;
++}
++
++static struct bfqio_cgroup bfqio_root_cgroup = {
++ .weight = BFQ_DEFAULT_GRP_WEIGHT,
++ .ioprio = BFQ_DEFAULT_GRP_IOPRIO,
++ .ioprio_class = BFQ_DEFAULT_GRP_CLASS,
++};
++
++static inline void bfq_init_entity(struct bfq_entity *entity,
++ struct bfq_group *bfqg)
++{
++ entity->weight = entity->new_weight;
++ entity->orig_weight = entity->new_weight;
++ entity->ioprio = entity->new_ioprio;
++ entity->ioprio_class = entity->new_ioprio_class;
++ entity->parent = bfqg->my_entity;
++ entity->sched_data = &bfqg->sched_data;
++}
++
++static struct bfqio_cgroup *css_to_bfqio(struct cgroup_subsys_state *css)
++{
++ return css ? container_of(css, struct bfqio_cgroup, css) : NULL;
++}
++
++/*
++ * Search the bfq_group for bfqd into the hash table (by now only a list)
++ * of bgrp. Must be called under rcu_read_lock().
++ */
++static struct bfq_group *bfqio_lookup_group(struct bfqio_cgroup *bgrp,
++ struct bfq_data *bfqd)
++{
++ struct bfq_group *bfqg;
++ void *key;
++
++ hlist_for_each_entry_rcu(bfqg, &bgrp->group_data, group_node) {
++ key = rcu_dereference(bfqg->bfqd);
++ if (key == bfqd)
++ return bfqg;
++ }
++
++ return NULL;
++}
++
++static inline void bfq_group_init_entity(struct bfqio_cgroup *bgrp,
++ struct bfq_group *bfqg)
++{
++ struct bfq_entity *entity = &bfqg->entity;
++
++ /*
++ * If the weight of the entity has never been set via the sysfs
++ * interface, then bgrp->weight == 0. In this case we initialize
++ * the weight from the current ioprio value. Otherwise, the group
++ * weight, if set, has priority over the ioprio value.
++ */
++ if (bgrp->weight == 0) {
++ entity->new_weight = bfq_ioprio_to_weight(bgrp->ioprio);
++ entity->new_ioprio = bgrp->ioprio;
++ } else {
++ if (bgrp->weight < BFQ_MIN_WEIGHT ||
++ bgrp->weight > BFQ_MAX_WEIGHT) {
++ printk(KERN_CRIT "bfq_group_init_entity: "
++ "bgrp->weight %d\n", bgrp->weight);
++ BUG();
++ }
++ entity->new_weight = bgrp->weight;
++ entity->new_ioprio = bfq_weight_to_ioprio(bgrp->weight);
++ }
++ entity->orig_weight = entity->weight = entity->new_weight;
++ entity->ioprio = entity->new_ioprio;
++ entity->ioprio_class = entity->new_ioprio_class = bgrp->ioprio_class;
++ entity->my_sched_data = &bfqg->sched_data;
++ bfqg->active_entities = 0;
++}
++
++static inline void bfq_group_set_parent(struct bfq_group *bfqg,
++ struct bfq_group *parent)
++{
++ struct bfq_entity *entity;
++
++ BUG_ON(parent == NULL);
++ BUG_ON(bfqg == NULL);
++
++ entity = &bfqg->entity;
++ entity->parent = parent->my_entity;
++ entity->sched_data = &parent->sched_data;
++}
++
++/**
++ * bfq_group_chain_alloc - allocate a chain of groups.
++ * @bfqd: queue descriptor.
++ * @css: the leaf cgroup_subsys_state this chain starts from.
++ *
++ * Allocate a chain of groups starting from the one belonging to
++ * @cgroup up to the root cgroup. Stop if a cgroup on the chain
++ * to the root has already an allocated group on @bfqd.
++ */
++static struct bfq_group *bfq_group_chain_alloc(struct bfq_data *bfqd,
++ struct cgroup_subsys_state *css)
++{
++ struct bfqio_cgroup *bgrp;
++ struct bfq_group *bfqg, *prev = NULL, *leaf = NULL;
++
++ for (; css != NULL; css = css->parent) {
++ bgrp = css_to_bfqio(css);
++
++ bfqg = bfqio_lookup_group(bgrp, bfqd);
++ if (bfqg != NULL) {
++ /*
++ * All the cgroups in the path from there to the
++ * root must have a bfq_group for bfqd, so we don't
++ * need any more allocations.
++ */
++ break;
++ }
++
++ bfqg = kzalloc(sizeof(*bfqg), GFP_ATOMIC);
++ if (bfqg == NULL)
++ goto cleanup;
++
++ bfq_group_init_entity(bgrp, bfqg);
++ bfqg->my_entity = &bfqg->entity;
++
++ if (leaf == NULL) {
++ leaf = bfqg;
++ prev = leaf;
++ } else {
++ bfq_group_set_parent(prev, bfqg);
++ /*
++ * Build a list of allocated nodes using the bfqd
++ * filed, that is still unused and will be
++ * initialized only after the node will be
++ * connected.
++ */
++ prev->bfqd = bfqg;
++ prev = bfqg;
++ }
++ }
++
++ return leaf;
++
++cleanup:
++ while (leaf != NULL) {
++ prev = leaf;
++ leaf = leaf->bfqd;
++ kfree(prev);
++ }
++
++ return NULL;
++}
++
++/**
++ * bfq_group_chain_link - link an allocated group chain to a cgroup
++ * hierarchy.
++ * @bfqd: the queue descriptor.
++ * @css: the leaf cgroup_subsys_state to start from.
++ * @leaf: the leaf group (to be associated to @cgroup).
++ *
++ * Try to link a chain of groups to a cgroup hierarchy, connecting the
++ * nodes bottom-up, so we can be sure that when we find a cgroup in the
++ * hierarchy that already as a group associated to @bfqd all the nodes
++ * in the path to the root cgroup have one too.
++ *
++ * On locking: the queue lock protects the hierarchy (there is a hierarchy
++ * per device) while the bfqio_cgroup lock protects the list of groups
++ * belonging to the same cgroup.
++ */
++static void bfq_group_chain_link(struct bfq_data *bfqd,
++ struct cgroup_subsys_state *css,
++ struct bfq_group *leaf)
++{
++ struct bfqio_cgroup *bgrp;
++ struct bfq_group *bfqg, *next, *prev = NULL;
++ unsigned long flags;
++
++ assert_spin_locked(bfqd->queue->queue_lock);
++
++ for (; css != NULL && leaf != NULL; css = css->parent) {
++ bgrp = css_to_bfqio(css);
++ next = leaf->bfqd;
++
++ bfqg = bfqio_lookup_group(bgrp, bfqd);
++ BUG_ON(bfqg != NULL);
++
++ spin_lock_irqsave(&bgrp->lock, flags);
++
++ rcu_assign_pointer(leaf->bfqd, bfqd);
++ hlist_add_head_rcu(&leaf->group_node, &bgrp->group_data);
++ hlist_add_head(&leaf->bfqd_node, &bfqd->group_list);
++
++ spin_unlock_irqrestore(&bgrp->lock, flags);
++
++ prev = leaf;
++ leaf = next;
++ }
++
++ BUG_ON(css == NULL && leaf != NULL);
++ if (css != NULL && prev != NULL) {
++ bgrp = css_to_bfqio(css);
++ bfqg = bfqio_lookup_group(bgrp, bfqd);
++ bfq_group_set_parent(prev, bfqg);
++ }
++}
++
++/**
++ * bfq_find_alloc_group - return the group associated to @bfqd in @cgroup.
++ * @bfqd: queue descriptor.
++ * @cgroup: cgroup being searched for.
++ *
++ * Return a group associated to @bfqd in @cgroup, allocating one if
++ * necessary. When a group is returned all the cgroups in the path
++ * to the root have a group associated to @bfqd.
++ *
++ * If the allocation fails, return the root group: this breaks guarantees
++ * but is a safe fallback. If this loss becomes a problem it can be
++ * mitigated using the equivalent weight (given by the product of the
++ * weights of the groups in the path from @group to the root) in the
++ * root scheduler.
++ *
++ * We allocate all the missing nodes in the path from the leaf cgroup
++ * to the root and we connect the nodes only after all the allocations
++ * have been successful.
++ */
++static struct bfq_group *bfq_find_alloc_group(struct bfq_data *bfqd,
++ struct cgroup_subsys_state *css)
++{
++ struct bfqio_cgroup *bgrp = css_to_bfqio(css);
++ struct bfq_group *bfqg;
++
++ bfqg = bfqio_lookup_group(bgrp, bfqd);
++ if (bfqg != NULL)
++ return bfqg;
++
++ bfqg = bfq_group_chain_alloc(bfqd, css);
++ if (bfqg != NULL)
++ bfq_group_chain_link(bfqd, css, bfqg);
++ else
++ bfqg = bfqd->root_group;
++
++ return bfqg;
++}
++
++/**
++ * bfq_bfqq_move - migrate @bfqq to @bfqg.
++ * @bfqd: queue descriptor.
++ * @bfqq: the queue to move.
++ * @entity: @bfqq's entity.
++ * @bfqg: the group to move to.
++ *
++ * Move @bfqq to @bfqg, deactivating it from its old group and reactivating
++ * it on the new one. Avoid putting the entity on the old group idle tree.
++ *
++ * Must be called under the queue lock; the cgroup owning @bfqg must
++ * not disappear (by now this just means that we are called under
++ * rcu_read_lock()).
++ */
++static void bfq_bfqq_move(struct bfq_data *bfqd, struct bfq_queue *bfqq,
++ struct bfq_entity *entity, struct bfq_group *bfqg)
++{
++ int busy, resume;
++
++ busy = bfq_bfqq_busy(bfqq);
++ resume = !RB_EMPTY_ROOT(&bfqq->sort_list);
++
++ BUG_ON(resume && !entity->on_st);
++ BUG_ON(busy && !resume && entity->on_st &&
++ bfqq != bfqd->in_service_queue);
++
++ if (busy) {
++ BUG_ON(atomic_read(&bfqq->ref) < 2);
++
++ if (!resume)
++ bfq_del_bfqq_busy(bfqd, bfqq, 0);
++ else
++ bfq_deactivate_bfqq(bfqd, bfqq, 0);
++ } else if (entity->on_st)
++ bfq_put_idle_entity(bfq_entity_service_tree(entity), entity);
++
++ /*
++ * Here we use a reference to bfqg. We don't need a refcounter
++ * as the cgroup reference will not be dropped, so that its
++ * destroy() callback will not be invoked.
++ */
++ entity->parent = bfqg->my_entity;
++ entity->sched_data = &bfqg->sched_data;
++
++ if (busy && resume)
++ bfq_activate_bfqq(bfqd, bfqq);
++
++ if (bfqd->in_service_queue == NULL && !bfqd->rq_in_driver)
++ bfq_schedule_dispatch(bfqd);
++}
++
++/**
++ * __bfq_bic_change_cgroup - move @bic to @cgroup.
++ * @bfqd: the queue descriptor.
++ * @bic: the bic to move.
++ * @cgroup: the cgroup to move to.
++ *
++ * Move bic to cgroup, assuming that bfqd->queue is locked; the caller
++ * has to make sure that the reference to cgroup is valid across the call.
++ *
++ * NOTE: an alternative approach might have been to store the current
++ * cgroup in bfqq and getting a reference to it, reducing the lookup
++ * time here, at the price of slightly more complex code.
++ */
++static struct bfq_group *__bfq_bic_change_cgroup(struct bfq_data *bfqd,
++ struct bfq_io_cq *bic,
++ struct cgroup_subsys_state *css)
++{
++ struct bfq_queue *async_bfqq = bic_to_bfqq(bic, 0);
++ struct bfq_queue *sync_bfqq = bic_to_bfqq(bic, 1);
++ struct bfq_entity *entity;
++ struct bfq_group *bfqg;
++ struct bfqio_cgroup *bgrp;
++
++ bgrp = css_to_bfqio(css);
++
++ bfqg = bfq_find_alloc_group(bfqd, css);
++ if (async_bfqq != NULL) {
++ entity = &async_bfqq->entity;
++
++ if (entity->sched_data != &bfqg->sched_data) {
++ bic_set_bfqq(bic, NULL, 0);
++ bfq_log_bfqq(bfqd, async_bfqq,
++ "bic_change_group: %p %d",
++ async_bfqq, atomic_read(&async_bfqq->ref));
++ bfq_put_queue(async_bfqq);
++ }
++ }
++
++ if (sync_bfqq != NULL) {
++ entity = &sync_bfqq->entity;
++ if (entity->sched_data != &bfqg->sched_data)
++ bfq_bfqq_move(bfqd, sync_bfqq, entity, bfqg);
++ }
++
++ return bfqg;
++}
++
++/**
++ * bfq_bic_change_cgroup - move @bic to @cgroup.
++ * @bic: the bic being migrated.
++ * @cgroup: the destination cgroup.
++ *
++ * When the task owning @bic is moved to @cgroup, @bic is immediately
++ * moved into its new parent group.
++ */
++static void bfq_bic_change_cgroup(struct bfq_io_cq *bic,
++ struct cgroup_subsys_state *css)
++{
++ struct bfq_data *bfqd;
++ unsigned long uninitialized_var(flags);
++
++ bfqd = bfq_get_bfqd_locked(&(bic->icq.q->elevator->elevator_data),
++ &flags);
++ if (bfqd != NULL) {
++ __bfq_bic_change_cgroup(bfqd, bic, css);
++ bfq_put_bfqd_unlock(bfqd, &flags);
++ }
++}
++
++/**
++ * bfq_bic_update_cgroup - update the cgroup of @bic.
++ * @bic: the @bic to update.
++ *
++ * Make sure that @bic is enqueued in the cgroup of the current task.
++ * We need this in addition to moving bics during the cgroup attach
++ * phase because the task owning @bic could be at its first disk
++ * access or we may end up in the root cgroup as the result of a
++ * memory allocation failure and here we try to move to the right
++ * group.
++ *
++ * Must be called under the queue lock. It is safe to use the returned
++ * value even after the rcu_read_unlock() as the migration/destruction
++ * paths act under the queue lock too. IOW it is impossible to race with
++ * group migration/destruction and end up with an invalid group as:
++ * a) here cgroup has not yet been destroyed, nor its destroy callback
++ * has started execution, as current holds a reference to it,
++ * b) if it is destroyed after rcu_read_unlock() [after current is
++ * migrated to a different cgroup] its attach() callback will have
++ * taken care of remove all the references to the old cgroup data.
++ */
++static struct bfq_group *bfq_bic_update_cgroup(struct bfq_io_cq *bic)
++{
++ struct bfq_data *bfqd = bic_to_bfqd(bic);
++ struct bfq_group *bfqg;
++ struct cgroup_subsys_state *css;
++
++ BUG_ON(bfqd == NULL);
++
++ rcu_read_lock();
++ css = task_css(current, bfqio_cgrp_id);
++ bfqg = __bfq_bic_change_cgroup(bfqd, bic, css);
++ rcu_read_unlock();
++
++ return bfqg;
++}
++
++/**
++ * bfq_flush_idle_tree - deactivate any entity on the idle tree of @st.
++ * @st: the service tree being flushed.
++ */
++static inline void bfq_flush_idle_tree(struct bfq_service_tree *st)
++{
++ struct bfq_entity *entity = st->first_idle;
++
++ for (; entity != NULL; entity = st->first_idle)
++ __bfq_deactivate_entity(entity, 0);
++}
++
++/**
++ * bfq_reparent_leaf_entity - move leaf entity to the root_group.
++ * @bfqd: the device data structure with the root group.
++ * @entity: the entity to move.
++ */
++static inline void bfq_reparent_leaf_entity(struct bfq_data *bfqd,
++ struct bfq_entity *entity)
++{
++ struct bfq_queue *bfqq = bfq_entity_to_bfqq(entity);
++
++ BUG_ON(bfqq == NULL);
++ bfq_bfqq_move(bfqd, bfqq, entity, bfqd->root_group);
++ return;
++}
++
++/**
++ * bfq_reparent_active_entities - move to the root group all active
++ * entities.
++ * @bfqd: the device data structure with the root group.
++ * @bfqg: the group to move from.
++ * @st: the service tree with the entities.
++ *
++ * Needs queue_lock to be taken and reference to be valid over the call.
++ */
++static inline void bfq_reparent_active_entities(struct bfq_data *bfqd,
++ struct bfq_group *bfqg,
++ struct bfq_service_tree *st)
++{
++ struct rb_root *active = &st->active;
++ struct bfq_entity *entity = NULL;
++
++ if (!RB_EMPTY_ROOT(&st->active))
++ entity = bfq_entity_of(rb_first(active));
++
++ for (; entity != NULL; entity = bfq_entity_of(rb_first(active)))
++ bfq_reparent_leaf_entity(bfqd, entity);
++
++ if (bfqg->sched_data.in_service_entity != NULL)
++ bfq_reparent_leaf_entity(bfqd,
++ bfqg->sched_data.in_service_entity);
++
++ return;
++}
++
++/**
++ * bfq_destroy_group - destroy @bfqg.
++ * @bgrp: the bfqio_cgroup containing @bfqg.
++ * @bfqg: the group being destroyed.
++ *
++ * Destroy @bfqg, making sure that it is not referenced from its parent.
++ */
++static void bfq_destroy_group(struct bfqio_cgroup *bgrp, struct bfq_group *bfqg)
++{
++ struct bfq_data *bfqd;
++ struct bfq_service_tree *st;
++ struct bfq_entity *entity = bfqg->my_entity;
++ unsigned long uninitialized_var(flags);
++ int i;
++
++ hlist_del(&bfqg->group_node);
++
++ /*
++ * Empty all service_trees belonging to this group before
++ * deactivating the group itself.
++ */
++ for (i = 0; i < BFQ_IOPRIO_CLASSES; i++) {
++ st = bfqg->sched_data.service_tree + i;
++
++ /*
++ * The idle tree may still contain bfq_queues belonging
++ * to exited task because they never migrated to a different
++ * cgroup from the one being destroyed now. No one else
++ * can access them so it's safe to act without any lock.
++ */
++ bfq_flush_idle_tree(st);
++
++ /*
++ * It may happen that some queues are still active
++ * (busy) upon group destruction (if the corresponding
++ * processes have been forced to terminate). We move
++ * all the leaf entities corresponding to these queues
++ * to the root_group.
++ * Also, it may happen that the group has an entity
++ * in service, which is disconnected from the active
++ * tree: it must be moved, too.
++ * There is no need to put the sync queues, as the
++ * scheduler has taken no reference.
++ */
++ bfqd = bfq_get_bfqd_locked(&bfqg->bfqd, &flags);
++ if (bfqd != NULL) {
++ bfq_reparent_active_entities(bfqd, bfqg, st);
++ bfq_put_bfqd_unlock(bfqd, &flags);
++ }
++ BUG_ON(!RB_EMPTY_ROOT(&st->active));
++ BUG_ON(!RB_EMPTY_ROOT(&st->idle));
++ }
++ BUG_ON(bfqg->sched_data.next_in_service != NULL);
++ BUG_ON(bfqg->sched_data.in_service_entity != NULL);
++
++ /*
++ * We may race with device destruction, take extra care when
++ * dereferencing bfqg->bfqd.
++ */
++ bfqd = bfq_get_bfqd_locked(&bfqg->bfqd, &flags);
++ if (bfqd != NULL) {
++ hlist_del(&bfqg->bfqd_node);
++ __bfq_deactivate_entity(entity, 0);
++ bfq_put_async_queues(bfqd, bfqg);
++ bfq_put_bfqd_unlock(bfqd, &flags);
++ }
++ BUG_ON(entity->tree != NULL);
++
++ /*
++ * No need to defer the kfree() to the end of the RCU grace
++ * period: we are called from the destroy() callback of our
++ * cgroup, so we can be sure that no one is a) still using
++ * this cgroup or b) doing lookups in it.
++ */
++ kfree(bfqg);
++}
++
++static void bfq_end_wr_async(struct bfq_data *bfqd)
++{
++ struct hlist_node *tmp;
++ struct bfq_group *bfqg;
++
++ hlist_for_each_entry_safe(bfqg, tmp, &bfqd->group_list, bfqd_node)
++ bfq_end_wr_async_queues(bfqd, bfqg);
++ bfq_end_wr_async_queues(bfqd, bfqd->root_group);
++}
++
++/**
++ * bfq_disconnect_groups - disconnect @bfqd from all its groups.
++ * @bfqd: the device descriptor being exited.
++ *
++ * When the device exits we just make sure that no lookup can return
++ * the now unused group structures. They will be deallocated on cgroup
++ * destruction.
++ */
++static void bfq_disconnect_groups(struct bfq_data *bfqd)
++{
++ struct hlist_node *tmp;
++ struct bfq_group *bfqg;
++
++ bfq_log(bfqd, "disconnect_groups beginning");
++ hlist_for_each_entry_safe(bfqg, tmp, &bfqd->group_list, bfqd_node) {
++ hlist_del(&bfqg->bfqd_node);
++
++ __bfq_deactivate_entity(bfqg->my_entity, 0);
++
++ /*
++ * Don't remove from the group hash, just set an
++ * invalid key. No lookups can race with the
++ * assignment as bfqd is being destroyed; this
++ * implies also that new elements cannot be added
++ * to the list.
++ */
++ rcu_assign_pointer(bfqg->bfqd, NULL);
++
++ bfq_log(bfqd, "disconnect_groups: put async for group %p",
++ bfqg);
++ bfq_put_async_queues(bfqd, bfqg);
++ }
++}
++
++static inline void bfq_free_root_group(struct bfq_data *bfqd)
++{
++ struct bfqio_cgroup *bgrp = &bfqio_root_cgroup;
++ struct bfq_group *bfqg = bfqd->root_group;
++
++ bfq_put_async_queues(bfqd, bfqg);
++
++ spin_lock_irq(&bgrp->lock);
++ hlist_del_rcu(&bfqg->group_node);
++ spin_unlock_irq(&bgrp->lock);
++
++ /*
++ * No need to synchronize_rcu() here: since the device is gone
++ * there cannot be any read-side access to its root_group.
++ */
++ kfree(bfqg);
++}
++
++static struct bfq_group *bfq_alloc_root_group(struct bfq_data *bfqd, int node)
++{
++ struct bfq_group *bfqg;
++ struct bfqio_cgroup *bgrp;
++ int i;
++
++ bfqg = kzalloc_node(sizeof(*bfqg), GFP_KERNEL, node);
++ if (bfqg == NULL)
++ return NULL;
++
++ bfqg->entity.parent = NULL;
++ for (i = 0; i < BFQ_IOPRIO_CLASSES; i++)
++ bfqg->sched_data.service_tree[i] = BFQ_SERVICE_TREE_INIT;
++
++ bgrp = &bfqio_root_cgroup;
++ spin_lock_irq(&bgrp->lock);
++ rcu_assign_pointer(bfqg->bfqd, bfqd);
++ hlist_add_head_rcu(&bfqg->group_node, &bgrp->group_data);
++ spin_unlock_irq(&bgrp->lock);
++
++ return bfqg;
++}
++
++#define SHOW_FUNCTION(__VAR) \
++static u64 bfqio_cgroup_##__VAR##_read(struct cgroup_subsys_state *css, \
++ struct cftype *cftype) \
++{ \
++ struct bfqio_cgroup *bgrp = css_to_bfqio(css); \
++ u64 ret = -ENODEV; \
++ \
++ mutex_lock(&bfqio_mutex); \
++ if (bfqio_is_removed(bgrp)) \
++ goto out_unlock; \
++ \
++ spin_lock_irq(&bgrp->lock); \
++ ret = bgrp->__VAR; \
++ spin_unlock_irq(&bgrp->lock); \
++ \
++out_unlock: \
++ mutex_unlock(&bfqio_mutex); \
++ return ret; \
++}
++
++SHOW_FUNCTION(weight);
++SHOW_FUNCTION(ioprio);
++SHOW_FUNCTION(ioprio_class);
++#undef SHOW_FUNCTION
++
++#define STORE_FUNCTION(__VAR, __MIN, __MAX) \
++static int bfqio_cgroup_##__VAR##_write(struct cgroup_subsys_state *css,\
++ struct cftype *cftype, \
++ u64 val) \
++{ \
++ struct bfqio_cgroup *bgrp = css_to_bfqio(css); \
++ struct bfq_group *bfqg; \
++ int ret = -EINVAL; \
++ \
++ if (val < (__MIN) || val > (__MAX)) \
++ return ret; \
++ \
++ ret = -ENODEV; \
++ mutex_lock(&bfqio_mutex); \
++ if (bfqio_is_removed(bgrp)) \
++ goto out_unlock; \
++ ret = 0; \
++ \
++ spin_lock_irq(&bgrp->lock); \
++ bgrp->__VAR = (unsigned short)val; \
++ hlist_for_each_entry(bfqg, &bgrp->group_data, group_node) { \
++ /* \
++ * Setting the ioprio_changed flag of the entity \
++ * to 1 with new_##__VAR == ##__VAR would re-set \
++ * the value of the weight to its ioprio mapping. \
++ * Set the flag only if necessary. \
++ */ \
++ if ((unsigned short)val != bfqg->entity.new_##__VAR) { \
++ bfqg->entity.new_##__VAR = (unsigned short)val; \
++ /* \
++ * Make sure that the above new value has been \
++ * stored in bfqg->entity.new_##__VAR before \
++ * setting the ioprio_changed flag. In fact, \
++ * this flag may be read asynchronously (in \
++ * critical sections protected by a different \
++ * lock than that held here), and finding this \
++ * flag set may cause the execution of the code \
++ * for updating parameters whose value may \
++ * depend also on bfqg->entity.new_##__VAR (in \
++ * __bfq_entity_update_weight_prio). \
++ * This barrier makes sure that the new value \
++ * of bfqg->entity.new_##__VAR is correctly \
++ * seen in that code. \
++ */ \
++ smp_wmb(); \
++ bfqg->entity.ioprio_changed = 1; \
++ } \
++ } \
++ spin_unlock_irq(&bgrp->lock); \
++ \
++out_unlock: \
++ mutex_unlock(&bfqio_mutex); \
++ return ret; \
++}
++
++STORE_FUNCTION(weight, BFQ_MIN_WEIGHT, BFQ_MAX_WEIGHT);
++STORE_FUNCTION(ioprio, 0, IOPRIO_BE_NR - 1);
++STORE_FUNCTION(ioprio_class, IOPRIO_CLASS_RT, IOPRIO_CLASS_IDLE);
++#undef STORE_FUNCTION
++
++static struct cftype bfqio_files[] = {
++ {
++ .name = "weight",
++ .read_u64 = bfqio_cgroup_weight_read,
++ .write_u64 = bfqio_cgroup_weight_write,
++ },
++ {
++ .name = "ioprio",
++ .read_u64 = bfqio_cgroup_ioprio_read,
++ .write_u64 = bfqio_cgroup_ioprio_write,
++ },
++ {
++ .name = "ioprio_class",
++ .read_u64 = bfqio_cgroup_ioprio_class_read,
++ .write_u64 = bfqio_cgroup_ioprio_class_write,
++ },
++ { }, /* terminate */
++};
++
++static struct cgroup_subsys_state *bfqio_create(struct cgroup_subsys_state
++ *parent_css)
++{
++ struct bfqio_cgroup *bgrp;
++
++ if (parent_css != NULL) {
++ bgrp = kzalloc(sizeof(*bgrp), GFP_KERNEL);
++ if (bgrp == NULL)
++ return ERR_PTR(-ENOMEM);
++ } else
++ bgrp = &bfqio_root_cgroup;
++
++ spin_lock_init(&bgrp->lock);
++ INIT_HLIST_HEAD(&bgrp->group_data);
++ bgrp->ioprio = BFQ_DEFAULT_GRP_IOPRIO;
++ bgrp->ioprio_class = BFQ_DEFAULT_GRP_CLASS;
++
++ return &bgrp->css;
++}
++
++/*
++ * We cannot support shared io contexts, as we have no means to support
++ * two tasks with the same ioc in two different groups without major rework
++ * of the main bic/bfqq data structures. By now we allow a task to change
++ * its cgroup only if it's the only owner of its ioc; the drawback of this
++ * behavior is that a group containing a task that forked using CLONE_IO
++ * will not be destroyed until the tasks sharing the ioc die.
++ */
++static int bfqio_can_attach(struct cgroup_subsys_state *css,
++ struct cgroup_taskset *tset)
++{
++ struct task_struct *task;
++ struct io_context *ioc;
++ int ret = 0;
++
++ cgroup_taskset_for_each(task, tset) {
++ /*
++ * task_lock() is needed to avoid races with
++ * exit_io_context()
++ */
++ task_lock(task);
++ ioc = task->io_context;
++ if (ioc != NULL && atomic_read(&ioc->nr_tasks) > 1)
++ /*
++ * ioc == NULL means that the task is either too
++ * young or exiting: if it has still no ioc the
++ * ioc can't be shared, if the task is exiting the
++ * attach will fail anyway, no matter what we
++ * return here.
++ */
++ ret = -EINVAL;
++ task_unlock(task);
++ if (ret)
++ break;
++ }
++
++ return ret;
++}
++
++static void bfqio_attach(struct cgroup_subsys_state *css,
++ struct cgroup_taskset *tset)
++{
++ struct task_struct *task;
++ struct io_context *ioc;
++ struct io_cq *icq;
++
++ /*
++ * IMPORTANT NOTE: The move of more than one process at a time to a
++ * new group has not yet been tested.
++ */
++ cgroup_taskset_for_each(task, tset) {
++ ioc = get_task_io_context(task, GFP_ATOMIC, NUMA_NO_NODE);
++ if (ioc) {
++ /*
++ * Handle cgroup change here.
++ */
++ rcu_read_lock();
++ hlist_for_each_entry_rcu(icq, &ioc->icq_list, ioc_node)
++ if (!strncmp(
++ icq->q->elevator->type->elevator_name,
++ "bfq", ELV_NAME_MAX))
++ bfq_bic_change_cgroup(icq_to_bic(icq),
++ css);
++ rcu_read_unlock();
++ put_io_context(ioc);
++ }
++ }
++}
++
++static void bfqio_destroy(struct cgroup_subsys_state *css)
++{
++ struct bfqio_cgroup *bgrp = css_to_bfqio(css);
++ struct hlist_node *tmp;
++ struct bfq_group *bfqg;
++
++ /*
++ * Since we are destroying the cgroup, there are no more tasks
++ * referencing it, and all the RCU grace periods that may have
++ * referenced it are ended (as the destruction of the parent
++ * cgroup is RCU-safe); bgrp->group_data will not be accessed by
++ * anything else and we don't need any synchronization.
++ */
++ hlist_for_each_entry_safe(bfqg, tmp, &bgrp->group_data, group_node)
++ bfq_destroy_group(bgrp, bfqg);
++
++ BUG_ON(!hlist_empty(&bgrp->group_data));
++
++ kfree(bgrp);
++}
++
++static int bfqio_css_online(struct cgroup_subsys_state *css)
++{
++ struct bfqio_cgroup *bgrp = css_to_bfqio(css);
++
++ mutex_lock(&bfqio_mutex);
++ bgrp->online = true;
++ mutex_unlock(&bfqio_mutex);
++
++ return 0;
++}
++
++static void bfqio_css_offline(struct cgroup_subsys_state *css)
++{
++ struct bfqio_cgroup *bgrp = css_to_bfqio(css);
++
++ mutex_lock(&bfqio_mutex);
++ bgrp->online = false;
++ mutex_unlock(&bfqio_mutex);
++}
++
++struct cgroup_subsys bfqio_cgrp_subsys = {
++ .css_alloc = bfqio_create,
++ .css_online = bfqio_css_online,
++ .css_offline = bfqio_css_offline,
++ .can_attach = bfqio_can_attach,
++ .attach = bfqio_attach,
++ .css_free = bfqio_destroy,
++ .legacy_cftypes = bfqio_files,
++};
++#else
++static inline void bfq_init_entity(struct bfq_entity *entity,
++ struct bfq_group *bfqg)
++{
++ entity->weight = entity->new_weight;
++ entity->orig_weight = entity->new_weight;
++ entity->ioprio = entity->new_ioprio;
++ entity->ioprio_class = entity->new_ioprio_class;
++ entity->sched_data = &bfqg->sched_data;
++}
++
++static inline struct bfq_group *
++bfq_bic_update_cgroup(struct bfq_io_cq *bic)
++{
++ struct bfq_data *bfqd = bic_to_bfqd(bic);
++ return bfqd->root_group;
++}
++
++static inline void bfq_bfqq_move(struct bfq_data *bfqd,
++ struct bfq_queue *bfqq,
++ struct bfq_entity *entity,
++ struct bfq_group *bfqg)
++{
++}
++
++static void bfq_end_wr_async(struct bfq_data *bfqd)
++{
++ bfq_end_wr_async_queues(bfqd, bfqd->root_group);
++}
++
++static inline void bfq_disconnect_groups(struct bfq_data *bfqd)
++{
++ bfq_put_async_queues(bfqd, bfqd->root_group);
++}
++
++static inline void bfq_free_root_group(struct bfq_data *bfqd)
++{
++ kfree(bfqd->root_group);
++}
++
++static struct bfq_group *bfq_alloc_root_group(struct bfq_data *bfqd, int node)
++{
++ struct bfq_group *bfqg;
++ int i;
++
++ bfqg = kmalloc_node(sizeof(*bfqg), GFP_KERNEL | __GFP_ZERO, node);
++ if (bfqg == NULL)
++ return NULL;
++
++ for (i = 0; i < BFQ_IOPRIO_CLASSES; i++)
++ bfqg->sched_data.service_tree[i] = BFQ_SERVICE_TREE_INIT;
++
++ return bfqg;
++}
++#endif
+diff -Nur linux-4.1.3/block/bfq.h linux-xbian-imx6/block/bfq.h
+--- linux-4.1.3/block/bfq.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/block/bfq.h 2015-07-27 23:13:03.604123194 +0200
+@@ -0,0 +1,811 @@
++/*
++ * BFQ-v7r7 for 4.0.0: data structures and common functions prototypes.
++ *
++ * Based on ideas and code from CFQ:
++ * Copyright (C) 2003 Jens Axboe <axboe@kernel.dk>
++ *
++ * Copyright (C) 2008 Fabio Checconi <fabio@gandalf.sssup.it>
++ * Paolo Valente <paolo.valente@unimore.it>
++ *
++ * Copyright (C) 2010 Paolo Valente <paolo.valente@unimore.it>
++ */
++
++#ifndef _BFQ_H
++#define _BFQ_H
++
++#include <linux/blktrace_api.h>
++#include <linux/hrtimer.h>
++#include <linux/ioprio.h>
++#include <linux/rbtree.h>
++
++#define BFQ_IOPRIO_CLASSES 3
++#define BFQ_CL_IDLE_TIMEOUT (HZ/5)
++
++#define BFQ_MIN_WEIGHT 1
++#define BFQ_MAX_WEIGHT 1000
++
++#define BFQ_DEFAULT_QUEUE_IOPRIO 4
++
++#define BFQ_DEFAULT_GRP_WEIGHT 10
++#define BFQ_DEFAULT_GRP_IOPRIO 0
++#define BFQ_DEFAULT_GRP_CLASS IOPRIO_CLASS_BE
++
++struct bfq_entity;
++
++/**
++ * struct bfq_service_tree - per ioprio_class service tree.
++ * @active: tree for active entities (i.e., those backlogged).
++ * @idle: tree for idle entities (i.e., those not backlogged, with V <= F_i).
++ * @first_idle: idle entity with minimum F_i.
++ * @last_idle: idle entity with maximum F_i.
++ * @vtime: scheduler virtual time.
++ * @wsum: scheduler weight sum; active and idle entities contribute to it.
++ *
++ * Each service tree represents a B-WF2Q+ scheduler on its own. Each
++ * ioprio_class has its own independent scheduler, and so its own
++ * bfq_service_tree. All the fields are protected by the queue lock
++ * of the containing bfqd.
++ */
++struct bfq_service_tree {
++ struct rb_root active;
++ struct rb_root idle;
++
++ struct bfq_entity *first_idle;
++ struct bfq_entity *last_idle;
++
++ u64 vtime;
++ unsigned long wsum;
++};
++
++/**
++ * struct bfq_sched_data - multi-class scheduler.
++ * @in_service_entity: entity in service.
++ * @next_in_service: head-of-the-line entity in the scheduler.
++ * @service_tree: array of service trees, one per ioprio_class.
++ *
++ * bfq_sched_data is the basic scheduler queue. It supports three
++ * ioprio_classes, and can be used either as a toplevel queue or as
++ * an intermediate queue on a hierarchical setup.
++ * @next_in_service points to the active entity of the sched_data
++ * service trees that will be scheduled next.
++ *
++ * The supported ioprio_classes are the same as in CFQ, in descending
++ * priority order, IOPRIO_CLASS_RT, IOPRIO_CLASS_BE, IOPRIO_CLASS_IDLE.
++ * Requests from higher priority queues are served before all the
++ * requests from lower priority queues; among requests of the same
++ * queue requests are served according to B-WF2Q+.
++ * All the fields are protected by the queue lock of the containing bfqd.
++ */
++struct bfq_sched_data {
++ struct bfq_entity *in_service_entity;
++ struct bfq_entity *next_in_service;
++ struct bfq_service_tree service_tree[BFQ_IOPRIO_CLASSES];
++};
++
++/**
++ * struct bfq_weight_counter - counter of the number of all active entities
++ * with a given weight.
++ * @weight: weight of the entities that this counter refers to.
++ * @num_active: number of active entities with this weight.
++ * @weights_node: weights tree member (see bfq_data's @queue_weights_tree
++ * and @group_weights_tree).
++ */
++struct bfq_weight_counter {
++ short int weight;
++ unsigned int num_active;
++ struct rb_node weights_node;
++};
++
++/**
++ * struct bfq_entity - schedulable entity.
++ * @rb_node: service_tree member.
++ * @weight_counter: pointer to the weight counter associated with this entity.
++ * @on_st: flag, true if the entity is on a tree (either the active or
++ * the idle one of its service_tree).
++ * @finish: B-WF2Q+ finish timestamp (aka F_i).
++ * @start: B-WF2Q+ start timestamp (aka S_i).
++ * @tree: tree the entity is enqueued into; %NULL if not on a tree.
++ * @min_start: minimum start time of the (active) subtree rooted at
++ * this entity; used for O(log N) lookups into active trees.
++ * @service: service received during the last round of service.
++ * @budget: budget used to calculate F_i; F_i = S_i + @budget / @weight.
++ * @weight: weight of the queue
++ * @parent: parent entity, for hierarchical scheduling.
++ * @my_sched_data: for non-leaf nodes in the cgroup hierarchy, the
++ * associated scheduler queue, %NULL on leaf nodes.
++ * @sched_data: the scheduler queue this entity belongs to.
++ * @ioprio: the ioprio in use.
++ * @new_weight: when a weight change is requested, the new weight value.
++ * @orig_weight: original weight, used to implement weight boosting
++ * @new_ioprio: when an ioprio change is requested, the new ioprio value.
++ * @ioprio_class: the ioprio_class in use.
++ * @new_ioprio_class: when an ioprio_class change is requested, the new
++ * ioprio_class value.
++ * @ioprio_changed: flag, true when the user requested a weight, ioprio or
++ * ioprio_class change.
++ *
++ * A bfq_entity is used to represent either a bfq_queue (leaf node in the
++ * cgroup hierarchy) or a bfq_group into the upper level scheduler. Each
++ * entity belongs to the sched_data of the parent group in the cgroup
++ * hierarchy. Non-leaf entities have also their own sched_data, stored
++ * in @my_sched_data.
++ *
++ * Each entity stores independently its priority values; this would
++ * allow different weights on different devices, but this
++ * functionality is not exported to userspace by now. Priorities and
++ * weights are updated lazily, first storing the new values into the
++ * new_* fields, then setting the @ioprio_changed flag. As soon as
++ * there is a transition in the entity state that allows the priority
++ * update to take place the effective and the requested priority
++ * values are synchronized.
++ *
++ * Unless cgroups are used, the weight value is calculated from the
++ * ioprio to export the same interface as CFQ. When dealing with
++ * ``well-behaved'' queues (i.e., queues that do not spend too much
++ * time to consume their budget and have true sequential behavior, and
++ * when there are no external factors breaking anticipation) the
++ * relative weights at each level of the cgroups hierarchy should be
++ * guaranteed. All the fields are protected by the queue lock of the
++ * containing bfqd.
++ */
++struct bfq_entity {
++ struct rb_node rb_node;
++ struct bfq_weight_counter *weight_counter;
++
++ int on_st;
++
++ u64 finish;
++ u64 start;
++
++ struct rb_root *tree;
++
++ u64 min_start;
++
++ unsigned long service, budget;
++ unsigned short weight, new_weight;
++ unsigned short orig_weight;
++
++ struct bfq_entity *parent;
++
++ struct bfq_sched_data *my_sched_data;
++ struct bfq_sched_data *sched_data;
++
++ unsigned short ioprio, new_ioprio;
++ unsigned short ioprio_class, new_ioprio_class;
++
++ int ioprio_changed;
++};
++
++struct bfq_group;
++
++/**
++ * struct bfq_queue - leaf schedulable entity.
++ * @ref: reference counter.
++ * @bfqd: parent bfq_data.
++ * @new_bfqq: shared bfq_queue if queue is cooperating with
++ * one or more other queues.
++ * @pos_node: request-position tree member (see bfq_data's @rq_pos_tree).
++ * @pos_root: request-position tree root (see bfq_data's @rq_pos_tree).
++ * @sort_list: sorted list of pending requests.
++ * @next_rq: if fifo isn't expired, next request to serve.
++ * @queued: nr of requests queued in @sort_list.
++ * @allocated: currently allocated requests.
++ * @meta_pending: pending metadata requests.
++ * @fifo: fifo list of requests in sort_list.
++ * @entity: entity representing this queue in the scheduler.
++ * @max_budget: maximum budget allowed from the feedback mechanism.
++ * @budget_timeout: budget expiration (in jiffies).
++ * @dispatched: number of requests on the dispatch list or inside driver.
++ * @flags: status flags.
++ * @bfqq_list: node for active/idle bfqq list inside our bfqd.
++ * @burst_list_node: node for the device's burst list.
++ * @seek_samples: number of seeks sampled
++ * @seek_total: sum of the distances of the seeks sampled
++ * @seek_mean: mean seek distance
++ * @last_request_pos: position of the last request enqueued
++ * @requests_within_timer: number of consecutive pairs of request completion
++ * and arrival, such that the queue becomes idle
++ * after the completion, but the next request arrives
++ * within an idle time slice; used only if the queue's
++ * IO_bound has been cleared.
++ * @pid: pid of the process owning the queue, used for logging purposes.
++ * @last_wr_start_finish: start time of the current weight-raising period if
++ * the @bfq-queue is being weight-raised, otherwise
++ * finish time of the last weight-raising period
++ * @wr_cur_max_time: current max raising time for this queue
++ * @soft_rt_next_start: minimum time instant such that, only if a new
++ * request is enqueued after this time instant in an
++ * idle @bfq_queue with no outstanding requests, then
++ * the task associated with the queue it is deemed as
++ * soft real-time (see the comments to the function
++ * bfq_bfqq_softrt_next_start())
++ * @last_idle_bklogged: time of the last transition of the @bfq_queue from
++ * idle to backlogged
++ * @service_from_backlogged: cumulative service received from the @bfq_queue
++ * since the last transition from idle to
++ * backlogged
++ * @bic: pointer to the bfq_io_cq owning the bfq_queue, set to %NULL if the
++ * queue is shared
++ *
++ * A bfq_queue is a leaf request queue; it can be associated with an
++ * io_context or more, if it is async or shared between cooperating
++ * processes. @cgroup holds a reference to the cgroup, to be sure that it
++ * does not disappear while a bfqq still references it (mostly to avoid
++ * races between request issuing and task migration followed by cgroup
++ * destruction).
++ * All the fields are protected by the queue lock of the containing bfqd.
++ */
++struct bfq_queue {
++ atomic_t ref;
++ struct bfq_data *bfqd;
++
++ /* fields for cooperating queues handling */
++ struct bfq_queue *new_bfqq;
++ struct rb_node pos_node;
++ struct rb_root *pos_root;
++
++ struct rb_root sort_list;
++ struct request *next_rq;
++ int queued[2];
++ int allocated[2];
++ int meta_pending;
++ struct list_head fifo;
++
++ struct bfq_entity entity;
++
++ unsigned long max_budget;
++ unsigned long budget_timeout;
++
++ int dispatched;
++
++ unsigned int flags;
++
++ struct list_head bfqq_list;
++
++ struct hlist_node burst_list_node;
++
++ unsigned int seek_samples;
++ u64 seek_total;
++ sector_t seek_mean;
++ sector_t last_request_pos;
++
++ unsigned int requests_within_timer;
++
++ pid_t pid;
++ struct bfq_io_cq *bic;
++
++ /* weight-raising fields */
++ unsigned long wr_cur_max_time;
++ unsigned long soft_rt_next_start;
++ unsigned long last_wr_start_finish;
++ unsigned int wr_coeff;
++ unsigned long last_idle_bklogged;
++ unsigned long service_from_backlogged;
++};
++
++/**
++ * struct bfq_ttime - per process thinktime stats.
++ * @ttime_total: total process thinktime
++ * @ttime_samples: number of thinktime samples
++ * @ttime_mean: average process thinktime
++ */
++struct bfq_ttime {
++ unsigned long last_end_request;
++
++ unsigned long ttime_total;
++ unsigned long ttime_samples;
++ unsigned long ttime_mean;
++};
++
++/**
++ * struct bfq_io_cq - per (request_queue, io_context) structure.
++ * @icq: associated io_cq structure
++ * @bfqq: array of two process queues, the sync and the async
++ * @ttime: associated @bfq_ttime struct
++ * @wr_time_left: snapshot of the time left before weight raising ends
++ * for the sync queue associated to this process; this
++ * snapshot is taken to remember this value while the weight
++ * raising is suspended because the queue is merged with a
++ * shared queue, and is used to set @raising_cur_max_time
++ * when the queue is split from the shared queue and its
++ * weight is raised again
++ * @saved_idle_window: same purpose as the previous field for the idle
++ * window
++ * @saved_IO_bound: same purpose as the previous two fields for the I/O
++ * bound classification of a queue
++ * @saved_in_large_burst: same purpose as the previous fields for the
++ * value of the field keeping the queue's belonging
++ * to a large burst
++ * @was_in_burst_list: true if the queue belonged to a burst list
++ * before its merge with another cooperating queue
++ * @cooperations: counter of consecutive successful queue merges underwent
++ * by any of the process' @bfq_queues
++ * @failed_cooperations: counter of consecutive failed queue merges of any
++ * of the process' @bfq_queues
++ */
++struct bfq_io_cq {
++ struct io_cq icq; /* must be the first member */
++ struct bfq_queue *bfqq[2];
++ struct bfq_ttime ttime;
++ int ioprio;
++
++ unsigned int wr_time_left;
++ bool saved_idle_window;
++ bool saved_IO_bound;
++
++ bool saved_in_large_burst;
++ bool was_in_burst_list;
++
++ unsigned int cooperations;
++ unsigned int failed_cooperations;
++};
++
++enum bfq_device_speed {
++ BFQ_BFQD_FAST,
++ BFQ_BFQD_SLOW,
++};
++
++/**
++ * struct bfq_data - per device data structure.
++ * @queue: request queue for the managed device.
++ * @root_group: root bfq_group for the device.
++ * @rq_pos_tree: rbtree sorted by next_request position, used when
++ * determining if two or more queues have interleaving
++ * requests (see bfq_close_cooperator()).
++ * @active_numerous_groups: number of bfq_groups containing more than one
++ * active @bfq_entity.
++ * @queue_weights_tree: rbtree of weight counters of @bfq_queues, sorted by
++ * weight. Used to keep track of whether all @bfq_queues
++ * have the same weight. The tree contains one counter
++ * for each distinct weight associated to some active
++ * and not weight-raised @bfq_queue (see the comments to
++ * the functions bfq_weights_tree_[add|remove] for
++ * further details).
++ * @group_weights_tree: rbtree of non-queue @bfq_entity weight counters, sorted
++ * by weight. Used to keep track of whether all
++ * @bfq_groups have the same weight. The tree contains
++ * one counter for each distinct weight associated to
++ * some active @bfq_group (see the comments to the
++ * functions bfq_weights_tree_[add|remove] for further
++ * details).
++ * @busy_queues: number of bfq_queues containing requests (including the
++ * queue in service, even if it is idling).
++ * @busy_in_flight_queues: number of @bfq_queues containing pending or
++ * in-flight requests, plus the @bfq_queue in
++ * service, even if idle but waiting for the
++ * possible arrival of its next sync request. This
++ * field is updated only if the device is rotational,
++ * but used only if the device is also NCQ-capable.
++ * The reason why the field is updated also for non-
++ * NCQ-capable rotational devices is related to the
++ * fact that the value of @hw_tag may be set also
++ * later than when busy_in_flight_queues may need to
++ * be incremented for the first time(s). Taking also
++ * this possibility into account, to avoid unbalanced
++ * increments/decrements, would imply more overhead
++ * than just updating busy_in_flight_queues
++ * regardless of the value of @hw_tag.
++ * @const_seeky_busy_in_flight_queues: number of constantly-seeky @bfq_queues
++ * (that is, seeky queues that expired
++ * for budget timeout at least once)
++ * containing pending or in-flight
++ * requests, including the in-service
++ * @bfq_queue if constantly seeky. This
++ * field is updated only if the device
++ * is rotational, but used only if the
++ * device is also NCQ-capable (see the
++ * comments to @busy_in_flight_queues).
++ * @wr_busy_queues: number of weight-raised busy @bfq_queues.
++ * @queued: number of queued requests.
++ * @rq_in_driver: number of requests dispatched and waiting for completion.
++ * @sync_flight: number of sync requests in the driver.
++ * @max_rq_in_driver: max number of reqs in driver in the last
++ * @hw_tag_samples completed requests.
++ * @hw_tag_samples: nr of samples used to calculate hw_tag.
++ * @hw_tag: flag set to one if the driver is showing a queueing behavior.
++ * @budgets_assigned: number of budgets assigned.
++ * @idle_slice_timer: timer set when idling for the next sequential request
++ * from the queue in service.
++ * @unplug_work: delayed work to restart dispatching on the request queue.
++ * @in_service_queue: bfq_queue in service.
++ * @in_service_bic: bfq_io_cq (bic) associated with the @in_service_queue.
++ * @last_position: on-disk position of the last served request.
++ * @last_budget_start: beginning of the last budget.
++ * @last_idling_start: beginning of the last idle slice.
++ * @peak_rate: peak transfer rate observed for a budget.
++ * @peak_rate_samples: number of samples used to calculate @peak_rate.
++ * @bfq_max_budget: maximum budget allotted to a bfq_queue before
++ * rescheduling.
++ * @group_list: list of all the bfq_groups active on the device.
++ * @active_list: list of all the bfq_queues active on the device.
++ * @idle_list: list of all the bfq_queues idle on the device.
++ * @bfq_quantum: max number of requests dispatched per dispatch round.
++ * @bfq_fifo_expire: timeout for async/sync requests; when it expires
++ * requests are served in fifo order.
++ * @bfq_back_penalty: weight of backward seeks wrt forward ones.
++ * @bfq_back_max: maximum allowed backward seek.
++ * @bfq_slice_idle: maximum idling time.
++ * @bfq_user_max_budget: user-configured max budget value
++ * (0 for auto-tuning).
++ * @bfq_max_budget_async_rq: maximum budget (in nr of requests) allotted to
++ * async queues.
++ * @bfq_timeout: timeout for bfq_queues to consume their budget; used to
++ * to prevent seeky queues to impose long latencies to well
++ * behaved ones (this also implies that seeky queues cannot
++ * receive guarantees in the service domain; after a timeout
++ * they are charged for the whole allocated budget, to try
++ * to preserve a behavior reasonably fair among them, but
++ * without service-domain guarantees).
++ * @bfq_coop_thresh: number of queue merges after which a @bfq_queue is
++ * no more granted any weight-raising.
++ * @bfq_failed_cooperations: number of consecutive failed cooperation
++ * chances after which weight-raising is restored
++ * to a queue subject to more than bfq_coop_thresh
++ * queue merges.
++ * @bfq_requests_within_timer: number of consecutive requests that must be
++ * issued within the idle time slice to set
++ * again idling to a queue which was marked as
++ * non-I/O-bound (see the definition of the
++ * IO_bound flag for further details).
++ * @last_ins_in_burst: last time at which a queue entered the current
++ * burst of queues being activated shortly after
++ * each other; for more details about this and the
++ * following parameters related to a burst of
++ * activations, see the comments to the function
++ * @bfq_handle_burst.
++ * @bfq_burst_interval: reference time interval used to decide whether a
++ * queue has been activated shortly after
++ * @last_ins_in_burst.
++ * @burst_size: number of queues in the current burst of queue activations.
++ * @bfq_large_burst_thresh: maximum burst size above which the current
++ * queue-activation burst is deemed as 'large'.
++ * @large_burst: true if a large queue-activation burst is in progress.
++ * @burst_list: head of the burst list (as for the above fields, more details
++ * in the comments to the function bfq_handle_burst).
++ * @low_latency: if set to true, low-latency heuristics are enabled.
++ * @bfq_wr_coeff: maximum factor by which the weight of a weight-raised
++ * queue is multiplied.
++ * @bfq_wr_max_time: maximum duration of a weight-raising period (jiffies).
++ * @bfq_wr_rt_max_time: maximum duration for soft real-time processes.
++ * @bfq_wr_min_idle_time: minimum idle period after which weight-raising
++ * may be reactivated for a queue (in jiffies).
++ * @bfq_wr_min_inter_arr_async: minimum period between request arrivals
++ * after which weight-raising may be
++ * reactivated for an already busy queue
++ * (in jiffies).
++ * @bfq_wr_max_softrt_rate: max service-rate for a soft real-time queue,
++ * sectors per seconds.
++ * @RT_prod: cached value of the product R*T used for computing the maximum
++ * duration of the weight raising automatically.
++ * @device_speed: device-speed class for the low-latency heuristic.
++ * @oom_bfqq: fallback dummy bfqq for extreme OOM conditions.
++ *
++ * All the fields are protected by the @queue lock.
++ */
++struct bfq_data {
++ struct request_queue *queue;
++
++ struct bfq_group *root_group;
++ struct rb_root rq_pos_tree;
++
++#ifdef CONFIG_CGROUP_BFQIO
++ int active_numerous_groups;
++#endif
++
++ struct rb_root queue_weights_tree;
++ struct rb_root group_weights_tree;
++
++ int busy_queues;
++ int busy_in_flight_queues;
++ int const_seeky_busy_in_flight_queues;
++ int wr_busy_queues;
++ int queued;
++ int rq_in_driver;
++ int sync_flight;
++
++ int max_rq_in_driver;
++ int hw_tag_samples;
++ int hw_tag;
++
++ int budgets_assigned;
++
++ struct timer_list idle_slice_timer;
++ struct work_struct unplug_work;
++
++ struct bfq_queue *in_service_queue;
++ struct bfq_io_cq *in_service_bic;
++
++ sector_t last_position;
++
++ ktime_t last_budget_start;
++ ktime_t last_idling_start;
++ int peak_rate_samples;
++ u64 peak_rate;
++ unsigned long bfq_max_budget;
++
++ struct hlist_head group_list;
++ struct list_head active_list;
++ struct list_head idle_list;
++
++ unsigned int bfq_quantum;
++ unsigned int bfq_fifo_expire[2];
++ unsigned int bfq_back_penalty;
++ unsigned int bfq_back_max;
++ unsigned int bfq_slice_idle;
++ u64 bfq_class_idle_last_service;
++
++ unsigned int bfq_user_max_budget;
++ unsigned int bfq_max_budget_async_rq;
++ unsigned int bfq_timeout[2];
++
++ unsigned int bfq_coop_thresh;
++ unsigned int bfq_failed_cooperations;
++ unsigned int bfq_requests_within_timer;
++
++ unsigned long last_ins_in_burst;
++ unsigned long bfq_burst_interval;
++ int burst_size;
++ unsigned long bfq_large_burst_thresh;
++ bool large_burst;
++ struct hlist_head burst_list;
++
++ bool low_latency;
++
++ /* parameters of the low_latency heuristics */
++ unsigned int bfq_wr_coeff;
++ unsigned int bfq_wr_max_time;
++ unsigned int bfq_wr_rt_max_time;
++ unsigned int bfq_wr_min_idle_time;
++ unsigned long bfq_wr_min_inter_arr_async;
++ unsigned int bfq_wr_max_softrt_rate;
++ u64 RT_prod;
++ enum bfq_device_speed device_speed;
++
++ struct bfq_queue oom_bfqq;
++};
++
++enum bfqq_state_flags {
++ BFQ_BFQQ_FLAG_busy = 0, /* has requests or is in service */
++ BFQ_BFQQ_FLAG_wait_request, /* waiting for a request */
++ BFQ_BFQQ_FLAG_must_alloc, /* must be allowed rq alloc */
++ BFQ_BFQQ_FLAG_fifo_expire, /* FIFO checked in this slice */
++ BFQ_BFQQ_FLAG_idle_window, /* slice idling enabled */
++ BFQ_BFQQ_FLAG_prio_changed, /* task priority has changed */
++ BFQ_BFQQ_FLAG_sync, /* synchronous queue */
++ BFQ_BFQQ_FLAG_budget_new, /* no completion with this budget */
++ BFQ_BFQQ_FLAG_IO_bound, /*
++ * bfqq has timed-out at least once
++ * having consumed at most 2/10 of
++ * its budget
++ */
++ BFQ_BFQQ_FLAG_in_large_burst, /*
++ * bfqq activated in a large burst,
++ * see comments to bfq_handle_burst.
++ */
++ BFQ_BFQQ_FLAG_constantly_seeky, /*
++ * bfqq has proved to be slow and
++ * seeky until budget timeout
++ */
++ BFQ_BFQQ_FLAG_softrt_update, /*
++ * may need softrt-next-start
++ * update
++ */
++ BFQ_BFQQ_FLAG_coop, /* bfqq is shared */
++ BFQ_BFQQ_FLAG_split_coop, /* shared bfqq will be split */
++ BFQ_BFQQ_FLAG_just_split, /* queue has just been split */
++};
++
++#define BFQ_BFQQ_FNS(name) \
++static inline void bfq_mark_bfqq_##name(struct bfq_queue *bfqq) \
++{ \
++ (bfqq)->flags |= (1 << BFQ_BFQQ_FLAG_##name); \
++} \
++static inline void bfq_clear_bfqq_##name(struct bfq_queue *bfqq) \
++{ \
++ (bfqq)->flags &= ~(1 << BFQ_BFQQ_FLAG_##name); \
++} \
++static inline int bfq_bfqq_##name(const struct bfq_queue *bfqq) \
++{ \
++ return ((bfqq)->flags & (1 << BFQ_BFQQ_FLAG_##name)) != 0; \
++}
++
++BFQ_BFQQ_FNS(busy);
++BFQ_BFQQ_FNS(wait_request);
++BFQ_BFQQ_FNS(must_alloc);
++BFQ_BFQQ_FNS(fifo_expire);
++BFQ_BFQQ_FNS(idle_window);
++BFQ_BFQQ_FNS(prio_changed);
++BFQ_BFQQ_FNS(sync);
++BFQ_BFQQ_FNS(budget_new);
++BFQ_BFQQ_FNS(IO_bound);
++BFQ_BFQQ_FNS(in_large_burst);
++BFQ_BFQQ_FNS(constantly_seeky);
++BFQ_BFQQ_FNS(coop);
++BFQ_BFQQ_FNS(split_coop);
++BFQ_BFQQ_FNS(just_split);
++BFQ_BFQQ_FNS(softrt_update);
++#undef BFQ_BFQQ_FNS
++
++/* Logging facilities. */
++#define bfq_log_bfqq(bfqd, bfqq, fmt, args...) \
++ blk_add_trace_msg((bfqd)->queue, "bfq%d " fmt, (bfqq)->pid, ##args)
++
++#define bfq_log(bfqd, fmt, args...) \
++ blk_add_trace_msg((bfqd)->queue, "bfq " fmt, ##args)
++
++/* Expiration reasons. */
++enum bfqq_expiration {
++ BFQ_BFQQ_TOO_IDLE = 0, /*
++ * queue has been idling for
++ * too long
++ */
++ BFQ_BFQQ_BUDGET_TIMEOUT, /* budget took too long to be used */
++ BFQ_BFQQ_BUDGET_EXHAUSTED, /* budget consumed */
++ BFQ_BFQQ_NO_MORE_REQUESTS, /* the queue has no more requests */
++};
++
++#ifdef CONFIG_CGROUP_BFQIO
++/**
++ * struct bfq_group - per (device, cgroup) data structure.
++ * @entity: schedulable entity to insert into the parent group sched_data.
++ * @sched_data: own sched_data, to contain child entities (they may be
++ * both bfq_queues and bfq_groups).
++ * @group_node: node to be inserted into the bfqio_cgroup->group_data
++ * list of the containing cgroup's bfqio_cgroup.
++ * @bfqd_node: node to be inserted into the @bfqd->group_list list
++ * of the groups active on the same device; used for cleanup.
++ * @bfqd: the bfq_data for the device this group acts upon.
++ * @async_bfqq: array of async queues for all the tasks belonging to
++ * the group, one queue per ioprio value per ioprio_class,
++ * except for the idle class that has only one queue.
++ * @async_idle_bfqq: async queue for the idle class (ioprio is ignored).
++ * @my_entity: pointer to @entity, %NULL for the toplevel group; used
++ * to avoid too many special cases during group creation/
++ * migration.
++ * @active_entities: number of active entities belonging to the group;
++ * unused for the root group. Used to know whether there
++ * are groups with more than one active @bfq_entity
++ * (see the comments to the function
++ * bfq_bfqq_must_not_expire()).
++ *
++ * Each (device, cgroup) pair has its own bfq_group, i.e., for each cgroup
++ * there is a set of bfq_groups, each one collecting the lower-level
++ * entities belonging to the group that are acting on the same device.
++ *
++ * Locking works as follows:
++ * o @group_node is protected by the bfqio_cgroup lock, and is accessed
++ * via RCU from its readers.
++ * o @bfqd is protected by the queue lock, RCU is used to access it
++ * from the readers.
++ * o All the other fields are protected by the @bfqd queue lock.
++ */
++struct bfq_group {
++ struct bfq_entity entity;
++ struct bfq_sched_data sched_data;
++
++ struct hlist_node group_node;
++ struct hlist_node bfqd_node;
++
++ void *bfqd;
++
++ struct bfq_queue *async_bfqq[2][IOPRIO_BE_NR];
++ struct bfq_queue *async_idle_bfqq;
++
++ struct bfq_entity *my_entity;
++
++ int active_entities;
++};
++
++/**
++ * struct bfqio_cgroup - bfq cgroup data structure.
++ * @css: subsystem state for bfq in the containing cgroup.
++ * @online: flag marked when the subsystem is inserted.
++ * @weight: cgroup weight.
++ * @ioprio: cgroup ioprio.
++ * @ioprio_class: cgroup ioprio_class.
++ * @lock: spinlock that protects @ioprio, @ioprio_class and @group_data.
++ * @group_data: list containing the bfq_group belonging to this cgroup.
++ *
++ * @group_data is accessed using RCU, with @lock protecting the updates,
++ * @ioprio and @ioprio_class are protected by @lock.
++ */
++struct bfqio_cgroup {
++ struct cgroup_subsys_state css;
++ bool online;
++
++ unsigned short weight, ioprio, ioprio_class;
++
++ spinlock_t lock;
++ struct hlist_head group_data;
++};
++#else
++struct bfq_group {
++ struct bfq_sched_data sched_data;
++
++ struct bfq_queue *async_bfqq[2][IOPRIO_BE_NR];
++ struct bfq_queue *async_idle_bfqq;
++};
++#endif
++
++static inline struct bfq_service_tree *
++bfq_entity_service_tree(struct bfq_entity *entity)
++{
++ struct bfq_sched_data *sched_data = entity->sched_data;
++ unsigned int idx = entity->ioprio_class - 1;
++
++ BUG_ON(idx >= BFQ_IOPRIO_CLASSES);
++ BUG_ON(sched_data == NULL);
++
++ return sched_data->service_tree + idx;
++}
++
++static inline struct bfq_queue *bic_to_bfqq(struct bfq_io_cq *bic,
++ bool is_sync)
++{
++ return bic->bfqq[is_sync];
++}
++
++static inline void bic_set_bfqq(struct bfq_io_cq *bic,
++ struct bfq_queue *bfqq, bool is_sync)
++{
++ bic->bfqq[is_sync] = bfqq;
++}
++
++static inline struct bfq_data *bic_to_bfqd(struct bfq_io_cq *bic)
++{
++ return bic->icq.q->elevator->elevator_data;
++}
++
++/**
++ * bfq_get_bfqd_locked - get a lock to a bfqd using a RCU protected pointer.
++ * @ptr: a pointer to a bfqd.
++ * @flags: storage for the flags to be saved.
++ *
++ * This function allows bfqg->bfqd to be protected by the
++ * queue lock of the bfqd they reference; the pointer is dereferenced
++ * under RCU, so the storage for bfqd is assured to be safe as long
++ * as the RCU read side critical section does not end. After the
++ * bfqd->queue->queue_lock is taken the pointer is rechecked, to be
++ * sure that no other writer accessed it. If we raced with a writer,
++ * the function returns NULL, with the queue unlocked, otherwise it
++ * returns the dereferenced pointer, with the queue locked.
++ */
++static inline struct bfq_data *bfq_get_bfqd_locked(void **ptr,
++ unsigned long *flags)
++{
++ struct bfq_data *bfqd;
++
++ rcu_read_lock();
++ bfqd = rcu_dereference(*(struct bfq_data **)ptr);
++
++ if (bfqd != NULL) {
++ spin_lock_irqsave(bfqd->queue->queue_lock, *flags);
++ if (*ptr == bfqd)
++ goto out;
++ spin_unlock_irqrestore(bfqd->queue->queue_lock, *flags);
++ }
++
++ bfqd = NULL;
++out:
++ rcu_read_unlock();
++ return bfqd;
++}
++
++static inline void bfq_put_bfqd_unlock(struct bfq_data *bfqd,
++ unsigned long *flags)
++{
++ spin_unlock_irqrestore(bfqd->queue->queue_lock, *flags);
++}
++
++static void bfq_changed_ioprio(struct bfq_io_cq *bic);
++static void bfq_put_queue(struct bfq_queue *bfqq);
++static void bfq_dispatch_insert(struct request_queue *q, struct request *rq);
++static struct bfq_queue *bfq_get_queue(struct bfq_data *bfqd,
++ struct bfq_group *bfqg, int is_sync,
++ struct bfq_io_cq *bic, gfp_t gfp_mask);
++static void bfq_end_wr_async_queues(struct bfq_data *bfqd,
++ struct bfq_group *bfqg);
++static void bfq_put_async_queues(struct bfq_data *bfqd, struct bfq_group *bfqg);
++static void bfq_exit_bfqq(struct bfq_data *bfqd, struct bfq_queue *bfqq);
++
++#endif /* _BFQ_H */
+diff -Nur linux-4.1.3/block/bfq-ioc.c linux-xbian-imx6/block/bfq-ioc.c
+--- linux-4.1.3/block/bfq-ioc.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/block/bfq-ioc.c 2015-07-27 23:13:03.600137415 +0200
+@@ -0,0 +1,36 @@
++/*
++ * BFQ: I/O context handling.
++ *
++ * Based on ideas and code from CFQ:
++ * Copyright (C) 2003 Jens Axboe <axboe@kernel.dk>
++ *
++ * Copyright (C) 2008 Fabio Checconi <fabio@gandalf.sssup.it>
++ * Paolo Valente <paolo.valente@unimore.it>
++ *
++ * Copyright (C) 2010 Paolo Valente <paolo.valente@unimore.it>
++ */
++
++/**
++ * icq_to_bic - convert iocontext queue structure to bfq_io_cq.
++ * @icq: the iocontext queue.
++ */
++static inline struct bfq_io_cq *icq_to_bic(struct io_cq *icq)
++{
++ /* bic->icq is the first member, %NULL will convert to %NULL */
++ return container_of(icq, struct bfq_io_cq, icq);
++}
++
++/**
++ * bfq_bic_lookup - search into @ioc a bic associated to @bfqd.
++ * @bfqd: the lookup key.
++ * @ioc: the io_context of the process doing I/O.
++ *
++ * Queue lock must be held.
++ */
++static inline struct bfq_io_cq *bfq_bic_lookup(struct bfq_data *bfqd,
++ struct io_context *ioc)
++{
++ if (ioc)
++ return icq_to_bic(ioc_lookup_icq(ioc, bfqd->queue));
++ return NULL;
++}
+diff -Nur linux-4.1.3/block/bfq-iosched.c linux-xbian-imx6/block/bfq-iosched.c
+--- linux-4.1.3/block/bfq-iosched.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/block/bfq-iosched.c 2015-07-27 23:13:03.600137415 +0200
+@@ -0,0 +1,4223 @@
++/*
++ * Budget Fair Queueing (BFQ) disk scheduler.
++ *
++ * Based on ideas and code from CFQ:
++ * Copyright (C) 2003 Jens Axboe <axboe@kernel.dk>
++ *
++ * Copyright (C) 2008 Fabio Checconi <fabio@gandalf.sssup.it>
++ * Paolo Valente <paolo.valente@unimore.it>
++ *
++ * Copyright (C) 2010 Paolo Valente <paolo.valente@unimore.it>
++ *
++ * Licensed under the GPL-2 as detailed in the accompanying COPYING.BFQ
++ * file.
++ *
++ * BFQ is a proportional-share storage-I/O scheduling algorithm based on
++ * the slice-by-slice service scheme of CFQ. But BFQ assigns budgets,
++ * measured in number of sectors, to processes instead of time slices. The
++ * device is not granted to the in-service process for a given time slice,
++ * but until it has exhausted its assigned budget. This change from the time
++ * to the service domain allows BFQ to distribute the device throughput
++ * among processes as desired, without any distortion due to ZBR, workload
++ * fluctuations or other factors. BFQ uses an ad hoc internal scheduler,
++ * called B-WF2Q+, to schedule processes according to their budgets. More
++ * precisely, BFQ schedules queues associated to processes. Thanks to the
++ * accurate policy of B-WF2Q+, BFQ can afford to assign high budgets to
++ * I/O-bound processes issuing sequential requests (to boost the
++ * throughput), and yet guarantee a low latency to interactive and soft
++ * real-time applications.
++ *
++ * BFQ is described in [1], where also a reference to the initial, more
++ * theoretical paper on BFQ can be found. The interested reader can find
++ * in the latter paper full details on the main algorithm, as well as
++ * formulas of the guarantees and formal proofs of all the properties.
++ * With respect to the version of BFQ presented in these papers, this
++ * implementation adds a few more heuristics, such as the one that
++ * guarantees a low latency to soft real-time applications, and a
++ * hierarchical extension based on H-WF2Q+.
++ *
++ * B-WF2Q+ is based on WF2Q+, that is described in [2], together with
++ * H-WF2Q+, while the augmented tree used to implement B-WF2Q+ with O(log N)
++ * complexity derives from the one introduced with EEVDF in [3].
++ *
++ * [1] P. Valente and M. Andreolini, ``Improving Application Responsiveness
++ * with the BFQ Disk I/O Scheduler'',
++ * Proceedings of the 5th Annual International Systems and Storage
++ * Conference (SYSTOR '12), June 2012.
++ *
++ * http://algogroup.unimo.it/people/paolo/disk_sched/bf1-v1-suite-results.pdf
++ *
++ * [2] Jon C.R. Bennett and H. Zhang, ``Hierarchical Packet Fair Queueing
++ * Algorithms,'' IEEE/ACM Transactions on Networking, 5(5):675-689,
++ * Oct 1997.
++ *
++ * http://www.cs.cmu.edu/~hzhang/papers/TON-97-Oct.ps.gz
++ *
++ * [3] I. Stoica and H. Abdel-Wahab, ``Earliest Eligible Virtual Deadline
++ * First: A Flexible and Accurate Mechanism for Proportional Share
++ * Resource Allocation,'' technical report.
++ *
++ * http://www.cs.berkeley.edu/~istoica/papers/eevdf-tr-95.pdf
++ */
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <linux/blkdev.h>
++#include <linux/cgroup.h>
++#include <linux/elevator.h>
++#include <linux/jiffies.h>
++#include <linux/rbtree.h>
++#include <linux/ioprio.h>
++#include "bfq.h"
++#include "blk.h"
++
++/* Max number of dispatches in one round of service. */
++static const int bfq_quantum = 4;
++
++/* Expiration time of sync (0) and async (1) requests, in jiffies. */
++static const int bfq_fifo_expire[2] = { HZ / 4, HZ / 8 };
++
++/* Maximum backwards seek, in KiB. */
++static const int bfq_back_max = 16 * 1024;
++
++/* Penalty of a backwards seek, in number of sectors. */
++static const int bfq_back_penalty = 2;
++
++/* Idling period duration, in jiffies. */
++static int bfq_slice_idle = HZ / 125;
++
++/* Default maximum budget values, in sectors and number of requests. */
++static const int bfq_default_max_budget = 16 * 1024;
++static const int bfq_max_budget_async_rq = 4;
++
++/*
++ * Async to sync throughput distribution is controlled as follows:
++ * when an async request is served, the entity is charged the number
++ * of sectors of the request, multiplied by the factor below
++ */
++static const int bfq_async_charge_factor = 10;
++
++/* Default timeout values, in jiffies, approximating CFQ defaults. */
++static const int bfq_timeout_sync = HZ / 8;
++static int bfq_timeout_async = HZ / 25;
++
++struct kmem_cache *bfq_pool;
++
++/* Below this threshold (in ms), we consider thinktime immediate. */
++#define BFQ_MIN_TT 2
++
++/* hw_tag detection: parallel requests threshold and min samples needed. */
++#define BFQ_HW_QUEUE_THRESHOLD 4
++#define BFQ_HW_QUEUE_SAMPLES 32
++
++#define BFQQ_SEEK_THR (sector_t)(8 * 1024)
++#define BFQQ_SEEKY(bfqq) ((bfqq)->seek_mean > BFQQ_SEEK_THR)
++
++/* Min samples used for peak rate estimation (for autotuning). */
++#define BFQ_PEAK_RATE_SAMPLES 32
++
++/* Shift used for peak rate fixed precision calculations. */
++#define BFQ_RATE_SHIFT 16
++
++/*
++ * By default, BFQ computes the duration of the weight raising for
++ * interactive applications automatically, using the following formula:
++ * duration = (R / r) * T, where r is the peak rate of the device, and
++ * R and T are two reference parameters.
++ * In particular, R is the peak rate of the reference device (see below),
++ * and T is a reference time: given the systems that are likely to be
++ * installed on the reference device according to its speed class, T is
++ * about the maximum time needed, under BFQ and while reading two files in
++ * parallel, to load typical large applications on these systems.
++ * In practice, the slower/faster the device at hand is, the more/less it
++ * takes to load applications with respect to the reference device.
++ * Accordingly, the longer/shorter BFQ grants weight raising to interactive
++ * applications.
++ *
++ * BFQ uses four different reference pairs (R, T), depending on:
++ * . whether the device is rotational or non-rotational;
++ * . whether the device is slow, such as old or portable HDDs, as well as
++ * SD cards, or fast, such as newer HDDs and SSDs.
++ *
++ * The device's speed class is dynamically (re)detected in
++ * bfq_update_peak_rate() every time the estimated peak rate is updated.
++ *
++ * In the following definitions, R_slow[0]/R_fast[0] and T_slow[0]/T_fast[0]
++ * are the reference values for a slow/fast rotational device, whereas
++ * R_slow[1]/R_fast[1] and T_slow[1]/T_fast[1] are the reference values for
++ * a slow/fast non-rotational device. Finally, device_speed_thresh are the
++ * thresholds used to switch between speed classes.
++ * Both the reference peak rates and the thresholds are measured in
++ * sectors/usec, left-shifted by BFQ_RATE_SHIFT.
++ */
++static int R_slow[2] = {1536, 10752};
++static int R_fast[2] = {17415, 34791};
++/*
++ * To improve readability, a conversion function is used to initialize the
++ * following arrays, which entails that they can be initialized only in a
++ * function.
++ */
++static int T_slow[2];
++static int T_fast[2];
++static int device_speed_thresh[2];
++
++#define BFQ_SERVICE_TREE_INIT ((struct bfq_service_tree) \
++ { RB_ROOT, RB_ROOT, NULL, NULL, 0, 0 })
++
++#define RQ_BIC(rq) ((struct bfq_io_cq *) (rq)->elv.priv[0])
++#define RQ_BFQQ(rq) ((rq)->elv.priv[1])
++
++static inline void bfq_schedule_dispatch(struct bfq_data *bfqd);
++
++#include "bfq-ioc.c"
++#include "bfq-sched.c"
++#include "bfq-cgroup.c"
++
++#define bfq_class_idle(bfqq) ((bfqq)->entity.ioprio_class ==\
++ IOPRIO_CLASS_IDLE)
++#define bfq_class_rt(bfqq) ((bfqq)->entity.ioprio_class ==\
++ IOPRIO_CLASS_RT)
++
++#define bfq_sample_valid(samples) ((samples) > 80)
++
++/*
++ * We regard a request as SYNC, if either it's a read or has the SYNC bit
++ * set (in which case it could also be a direct WRITE).
++ */
++static inline int bfq_bio_sync(struct bio *bio)
++{
++ if (bio_data_dir(bio) == READ || (bio->bi_rw & REQ_SYNC))
++ return 1;
++
++ return 0;
++}
++
++/*
++ * Scheduler run of queue, if there are requests pending and no one in the
++ * driver that will restart queueing.
++ */
++static inline void bfq_schedule_dispatch(struct bfq_data *bfqd)
++{
++ if (bfqd->queued != 0) {
++ bfq_log(bfqd, "schedule dispatch");
++ kblockd_schedule_work(&bfqd->unplug_work);
++ }
++}
++
++/*
++ * Lifted from AS - choose which of rq1 and rq2 that is best served now.
++ * We choose the request that is closesr to the head right now. Distance
++ * behind the head is penalized and only allowed to a certain extent.
++ */
++static struct request *bfq_choose_req(struct bfq_data *bfqd,
++ struct request *rq1,
++ struct request *rq2,
++ sector_t last)
++{
++ sector_t s1, s2, d1 = 0, d2 = 0;
++ unsigned long back_max;
++#define BFQ_RQ1_WRAP 0x01 /* request 1 wraps */
++#define BFQ_RQ2_WRAP 0x02 /* request 2 wraps */
++ unsigned wrap = 0; /* bit mask: requests behind the disk head? */
++
++ if (rq1 == NULL || rq1 == rq2)
++ return rq2;
++ if (rq2 == NULL)
++ return rq1;
++
++ if (rq_is_sync(rq1) && !rq_is_sync(rq2))
++ return rq1;
++ else if (rq_is_sync(rq2) && !rq_is_sync(rq1))
++ return rq2;
++ if ((rq1->cmd_flags & REQ_META) && !(rq2->cmd_flags & REQ_META))
++ return rq1;
++ else if ((rq2->cmd_flags & REQ_META) && !(rq1->cmd_flags & REQ_META))
++ return rq2;
++
++ s1 = blk_rq_pos(rq1);
++ s2 = blk_rq_pos(rq2);
++
++ /*
++ * By definition, 1KiB is 2 sectors.
++ */
++ back_max = bfqd->bfq_back_max * 2;
++
++ /*
++ * Strict one way elevator _except_ in the case where we allow
++ * short backward seeks which are biased as twice the cost of a
++ * similar forward seek.
++ */
++ if (s1 >= last)
++ d1 = s1 - last;
++ else if (s1 + back_max >= last)
++ d1 = (last - s1) * bfqd->bfq_back_penalty;
++ else
++ wrap |= BFQ_RQ1_WRAP;
++
++ if (s2 >= last)
++ d2 = s2 - last;
++ else if (s2 + back_max >= last)
++ d2 = (last - s2) * bfqd->bfq_back_penalty;
++ else
++ wrap |= BFQ_RQ2_WRAP;
++
++ /* Found required data */
++
++ /*
++ * By doing switch() on the bit mask "wrap" we avoid having to
++ * check two variables for all permutations: --> faster!
++ */
++ switch (wrap) {
++ case 0: /* common case for CFQ: rq1 and rq2 not wrapped */
++ if (d1 < d2)
++ return rq1;
++ else if (d2 < d1)
++ return rq2;
++ else {
++ if (s1 >= s2)
++ return rq1;
++ else
++ return rq2;
++ }
++
++ case BFQ_RQ2_WRAP:
++ return rq1;
++ case BFQ_RQ1_WRAP:
++ return rq2;
++ case (BFQ_RQ1_WRAP|BFQ_RQ2_WRAP): /* both rqs wrapped */
++ default:
++ /*
++ * Since both rqs are wrapped,
++ * start with the one that's further behind head
++ * (--> only *one* back seek required),
++ * since back seek takes more time than forward.
++ */
++ if (s1 <= s2)
++ return rq1;
++ else
++ return rq2;
++ }
++}
++
++static struct bfq_queue *
++bfq_rq_pos_tree_lookup(struct bfq_data *bfqd, struct rb_root *root,
++ sector_t sector, struct rb_node **ret_parent,
++ struct rb_node ***rb_link)
++{
++ struct rb_node **p, *parent;
++ struct bfq_queue *bfqq = NULL;
++
++ parent = NULL;
++ p = &root->rb_node;
++ while (*p) {
++ struct rb_node **n;
++
++ parent = *p;
++ bfqq = rb_entry(parent, struct bfq_queue, pos_node);
++
++ /*
++ * Sort strictly based on sector. Smallest to the left,
++ * largest to the right.
++ */
++ if (sector > blk_rq_pos(bfqq->next_rq))
++ n = &(*p)->rb_right;
++ else if (sector < blk_rq_pos(bfqq->next_rq))
++ n = &(*p)->rb_left;
++ else
++ break;
++ p = n;
++ bfqq = NULL;
++ }
++
++ *ret_parent = parent;
++ if (rb_link)
++ *rb_link = p;
++
++ bfq_log(bfqd, "rq_pos_tree_lookup %llu: returning %d",
++ (long long unsigned)sector,
++ bfqq != NULL ? bfqq->pid : 0);
++
++ return bfqq;
++}
++
++static void bfq_rq_pos_tree_add(struct bfq_data *bfqd, struct bfq_queue *bfqq)
++{
++ struct rb_node **p, *parent;
++ struct bfq_queue *__bfqq;
++
++ if (bfqq->pos_root != NULL) {
++ rb_erase(&bfqq->pos_node, bfqq->pos_root);
++ bfqq->pos_root = NULL;
++ }
++
++ if (bfq_class_idle(bfqq))
++ return;
++ if (!bfqq->next_rq)
++ return;
++
++ bfqq->pos_root = &bfqd->rq_pos_tree;
++ __bfqq = bfq_rq_pos_tree_lookup(bfqd, bfqq->pos_root,
++ blk_rq_pos(bfqq->next_rq), &parent, &p);
++ if (__bfqq == NULL) {
++ rb_link_node(&bfqq->pos_node, parent, p);
++ rb_insert_color(&bfqq->pos_node, bfqq->pos_root);
++ } else
++ bfqq->pos_root = NULL;
++}
++
++/*
++ * Tell whether there are active queues or groups with differentiated weights.
++ */
++static inline bool bfq_differentiated_weights(struct bfq_data *bfqd)
++{
++ BUG_ON(!bfqd->hw_tag);
++ /*
++ * For weights to differ, at least one of the trees must contain
++ * at least two nodes.
++ */
++ return (!RB_EMPTY_ROOT(&bfqd->queue_weights_tree) &&
++ (bfqd->queue_weights_tree.rb_node->rb_left ||
++ bfqd->queue_weights_tree.rb_node->rb_right)
++#ifdef CONFIG_CGROUP_BFQIO
++ ) ||
++ (!RB_EMPTY_ROOT(&bfqd->group_weights_tree) &&
++ (bfqd->group_weights_tree.rb_node->rb_left ||
++ bfqd->group_weights_tree.rb_node->rb_right)
++#endif
++ );
++}
++
++/*
++ * If the weight-counter tree passed as input contains no counter for
++ * the weight of the input entity, then add that counter; otherwise just
++ * increment the existing counter.
++ *
++ * Note that weight-counter trees contain few nodes in mostly symmetric
++ * scenarios. For example, if all queues have the same weight, then the
++ * weight-counter tree for the queues may contain at most one node.
++ * This holds even if low_latency is on, because weight-raised queues
++ * are not inserted in the tree.
++ * In most scenarios, the rate at which nodes are created/destroyed
++ * should be low too.
++ */
++static void bfq_weights_tree_add(struct bfq_data *bfqd,
++ struct bfq_entity *entity,
++ struct rb_root *root)
++{
++ struct rb_node **new = &(root->rb_node), *parent = NULL;
++
++ /*
++ * Do not insert if:
++ * - the device does not support queueing;
++ * - the entity is already associated with a counter, which happens if:
++ * 1) the entity is associated with a queue, 2) a request arrival
++ * has caused the queue to become both non-weight-raised, and hence
++ * change its weight, and backlogged; in this respect, each
++ * of the two events causes an invocation of this function,
++ * 3) this is the invocation of this function caused by the second
++ * event. This second invocation is actually useless, and we handle
++ * this fact by exiting immediately. More efficient or clearer
++ * solutions might possibly be adopted.
++ */
++ if (!bfqd->hw_tag || entity->weight_counter)
++ return;
++
++ while (*new) {
++ struct bfq_weight_counter *__counter = container_of(*new,
++ struct bfq_weight_counter,
++ weights_node);
++ parent = *new;
++
++ if (entity->weight == __counter->weight) {
++ entity->weight_counter = __counter;
++ goto inc_counter;
++ }
++ if (entity->weight < __counter->weight)
++ new = &((*new)->rb_left);
++ else
++ new = &((*new)->rb_right);
++ }
++
++ entity->weight_counter = kzalloc(sizeof(struct bfq_weight_counter),
++ GFP_ATOMIC);
++ entity->weight_counter->weight = entity->weight;
++ rb_link_node(&entity->weight_counter->weights_node, parent, new);
++ rb_insert_color(&entity->weight_counter->weights_node, root);
++
++inc_counter:
++ entity->weight_counter->num_active++;
++}
++
++/*
++ * Decrement the weight counter associated with the entity, and, if the
++ * counter reaches 0, remove the counter from the tree.
++ * See the comments to the function bfq_weights_tree_add() for considerations
++ * about overhead.
++ */
++static void bfq_weights_tree_remove(struct bfq_data *bfqd,
++ struct bfq_entity *entity,
++ struct rb_root *root)
++{
++ /*
++ * Check whether the entity is actually associated with a counter.
++ * In fact, the device may not be considered NCQ-capable for a while,
++ * which implies that no insertion in the weight trees is performed,
++ * after which the device may start to be deemed NCQ-capable, and hence
++ * this function may start to be invoked. This may cause the function
++ * to be invoked for entities that are not associated with any counter.
++ */
++ if (!entity->weight_counter)
++ return;
++
++ BUG_ON(RB_EMPTY_ROOT(root));
++ BUG_ON(entity->weight_counter->weight != entity->weight);
++
++ BUG_ON(!entity->weight_counter->num_active);
++ entity->weight_counter->num_active--;
++ if (entity->weight_counter->num_active > 0)
++ goto reset_entity_pointer;
++
++ rb_erase(&entity->weight_counter->weights_node, root);
++ kfree(entity->weight_counter);
++
++reset_entity_pointer:
++ entity->weight_counter = NULL;
++}
++
++static struct request *bfq_find_next_rq(struct bfq_data *bfqd,
++ struct bfq_queue *bfqq,
++ struct request *last)
++{
++ struct rb_node *rbnext = rb_next(&last->rb_node);
++ struct rb_node *rbprev = rb_prev(&last->rb_node);
++ struct request *next = NULL, *prev = NULL;
++
++ BUG_ON(RB_EMPTY_NODE(&last->rb_node));
++
++ if (rbprev != NULL)
++ prev = rb_entry_rq(rbprev);
++
++ if (rbnext != NULL)
++ next = rb_entry_rq(rbnext);
++ else {
++ rbnext = rb_first(&bfqq->sort_list);
++ if (rbnext && rbnext != &last->rb_node)
++ next = rb_entry_rq(rbnext);
++ }
++
++ return bfq_choose_req(bfqd, next, prev, blk_rq_pos(last));
++}
++
++/* see the definition of bfq_async_charge_factor for details */
++static inline unsigned long bfq_serv_to_charge(struct request *rq,
++ struct bfq_queue *bfqq)
++{
++ return blk_rq_sectors(rq) *
++ (1 + ((!bfq_bfqq_sync(bfqq)) * (bfqq->wr_coeff == 1) *
++ bfq_async_charge_factor));
++}
++
++/**
++ * bfq_updated_next_req - update the queue after a new next_rq selection.
++ * @bfqd: the device data the queue belongs to.
++ * @bfqq: the queue to update.
++ *
++ * If the first request of a queue changes we make sure that the queue
++ * has enough budget to serve at least its first request (if the
++ * request has grown). We do this because if the queue has not enough
++ * budget for its first request, it has to go through two dispatch
++ * rounds to actually get it dispatched.
++ */
++static void bfq_updated_next_req(struct bfq_data *bfqd,
++ struct bfq_queue *bfqq)
++{
++ struct bfq_entity *entity = &bfqq->entity;
++ struct bfq_service_tree *st = bfq_entity_service_tree(entity);
++ struct request *next_rq = bfqq->next_rq;
++ unsigned long new_budget;
++
++ if (next_rq == NULL)
++ return;
++
++ if (bfqq == bfqd->in_service_queue)
++ /*
++ * In order not to break guarantees, budgets cannot be
++ * changed after an entity has been selected.
++ */
++ return;
++
++ BUG_ON(entity->tree != &st->active);
++ BUG_ON(entity == entity->sched_data->in_service_entity);
++
++ new_budget = max_t(unsigned long, bfqq->max_budget,
++ bfq_serv_to_charge(next_rq, bfqq));
++ if (entity->budget != new_budget) {
++ entity->budget = new_budget;
++ bfq_log_bfqq(bfqd, bfqq, "updated next rq: new budget %lu",
++ new_budget);
++ bfq_activate_bfqq(bfqd, bfqq);
++ }
++}
++
++static inline unsigned int bfq_wr_duration(struct bfq_data *bfqd)
++{
++ u64 dur;
++
++ if (bfqd->bfq_wr_max_time > 0)
++ return bfqd->bfq_wr_max_time;
++
++ dur = bfqd->RT_prod;
++ do_div(dur, bfqd->peak_rate);
++
++ return dur;
++}
++
++static inline unsigned
++bfq_bfqq_cooperations(struct bfq_queue *bfqq)
++{
++ return bfqq->bic ? bfqq->bic->cooperations : 0;
++}
++
++static inline void
++bfq_bfqq_resume_state(struct bfq_queue *bfqq, struct bfq_io_cq *bic)
++{
++ if (bic->saved_idle_window)
++ bfq_mark_bfqq_idle_window(bfqq);
++ else
++ bfq_clear_bfqq_idle_window(bfqq);
++ if (bic->saved_IO_bound)
++ bfq_mark_bfqq_IO_bound(bfqq);
++ else
++ bfq_clear_bfqq_IO_bound(bfqq);
++ /* Assuming that the flag in_large_burst is already correctly set */
++ if (bic->wr_time_left && bfqq->bfqd->low_latency &&
++ !bfq_bfqq_in_large_burst(bfqq) &&
++ bic->cooperations < bfqq->bfqd->bfq_coop_thresh) {
++ /*
++ * Start a weight raising period with the duration given by
++ * the raising_time_left snapshot.
++ */
++ if (bfq_bfqq_busy(bfqq))
++ bfqq->bfqd->wr_busy_queues++;
++ bfqq->wr_coeff = bfqq->bfqd->bfq_wr_coeff;
++ bfqq->wr_cur_max_time = bic->wr_time_left;
++ bfqq->last_wr_start_finish = jiffies;
++ bfqq->entity.ioprio_changed = 1;
++ }
++ /*
++ * Clear wr_time_left to prevent bfq_bfqq_save_state() from
++ * getting confused about the queue's need of a weight-raising
++ * period.
++ */
++ bic->wr_time_left = 0;
++}
++
++/* Must be called with the queue_lock held. */
++static int bfqq_process_refs(struct bfq_queue *bfqq)
++{
++ int process_refs, io_refs;
++
++ io_refs = bfqq->allocated[READ] + bfqq->allocated[WRITE];
++ process_refs = atomic_read(&bfqq->ref) - io_refs - bfqq->entity.on_st;
++ BUG_ON(process_refs < 0);
++ return process_refs;
++}
++
++/* Empty burst list and add just bfqq (see comments to bfq_handle_burst) */
++static inline void bfq_reset_burst_list(struct bfq_data *bfqd,
++ struct bfq_queue *bfqq)
++{
++ struct bfq_queue *item;
++ struct hlist_node *n;
++
++ hlist_for_each_entry_safe(item, n, &bfqd->burst_list, burst_list_node)
++ hlist_del_init(&item->burst_list_node);
++ hlist_add_head(&bfqq->burst_list_node, &bfqd->burst_list);
++ bfqd->burst_size = 1;
++}
++
++/* Add bfqq to the list of queues in current burst (see bfq_handle_burst) */
++static void bfq_add_to_burst(struct bfq_data *bfqd, struct bfq_queue *bfqq)
++{
++ /* Increment burst size to take into account also bfqq */
++ bfqd->burst_size++;
++
++ if (bfqd->burst_size == bfqd->bfq_large_burst_thresh) {
++ struct bfq_queue *pos, *bfqq_item;
++ struct hlist_node *n;
++
++ /*
++ * Enough queues have been activated shortly after each
++ * other to consider this burst as large.
++ */
++ bfqd->large_burst = true;
++
++ /*
++ * We can now mark all queues in the burst list as
++ * belonging to a large burst.
++ */
++ hlist_for_each_entry(bfqq_item, &bfqd->burst_list,
++ burst_list_node)
++ bfq_mark_bfqq_in_large_burst(bfqq_item);
++ bfq_mark_bfqq_in_large_burst(bfqq);
++
++ /*
++ * From now on, and until the current burst finishes, any
++ * new queue being activated shortly after the last queue
++ * was inserted in the burst can be immediately marked as
++ * belonging to a large burst. So the burst list is not
++ * needed any more. Remove it.
++ */
++ hlist_for_each_entry_safe(pos, n, &bfqd->burst_list,
++ burst_list_node)
++ hlist_del_init(&pos->burst_list_node);
++ } else /* burst not yet large: add bfqq to the burst list */
++ hlist_add_head(&bfqq->burst_list_node, &bfqd->burst_list);
++}
++
++/*
++ * If many queues happen to become active shortly after each other, then,
++ * to help the processes associated to these queues get their job done as
++ * soon as possible, it is usually better to not grant either weight-raising
++ * or device idling to these queues. In this comment we describe, firstly,
++ * the reasons why this fact holds, and, secondly, the next function, which
++ * implements the main steps needed to properly mark these queues so that
++ * they can then be treated in a different way.
++ *
++ * As for the terminology, we say that a queue becomes active, i.e.,
++ * switches from idle to backlogged, either when it is created (as a
++ * consequence of the arrival of an I/O request), or, if already existing,
++ * when a new request for the queue arrives while the queue is idle.
++ * Bursts of activations, i.e., activations of different queues occurring
++ * shortly after each other, are typically caused by services or applications
++ * that spawn or reactivate many parallel threads/processes. Examples are
++ * systemd during boot or git grep.
++ *
++ * These services or applications benefit mostly from a high throughput:
++ * the quicker the requests of the activated queues are cumulatively served,
++ * the sooner the target job of these queues gets completed. As a consequence,
++ * weight-raising any of these queues, which also implies idling the device
++ * for it, is almost always counterproductive: in most cases it just lowers
++ * throughput.
++ *
++ * On the other hand, a burst of activations may be also caused by the start
++ * of an application that does not consist in a lot of parallel I/O-bound
++ * threads. In fact, with a complex application, the burst may be just a
++ * consequence of the fact that several processes need to be executed to
++ * start-up the application. To start an application as quickly as possible,
++ * the best thing to do is to privilege the I/O related to the application
++ * with respect to all other I/O. Therefore, the best strategy to start as
++ * quickly as possible an application that causes a burst of activations is
++ * to weight-raise all the queues activated during the burst. This is the
++ * exact opposite of the best strategy for the other type of bursts.
++ *
++ * In the end, to take the best action for each of the two cases, the two
++ * types of bursts need to be distinguished. Fortunately, this seems
++ * relatively easy to do, by looking at the sizes of the bursts. In
++ * particular, we found a threshold such that bursts with a larger size
++ * than that threshold are apparently caused only by services or commands
++ * such as systemd or git grep. For brevity, hereafter we call just 'large'
++ * these bursts. BFQ *does not* weight-raise queues whose activations occur
++ * in a large burst. In addition, for each of these queues BFQ performs or
++ * does not perform idling depending on which choice boosts the throughput
++ * most. The exact choice depends on the device and request pattern at
++ * hand.
++ *
++ * Turning back to the next function, it implements all the steps needed
++ * to detect the occurrence of a large burst and to properly mark all the
++ * queues belonging to it (so that they can then be treated in a different
++ * way). This goal is achieved by maintaining a special "burst list" that
++ * holds, temporarily, the queues that belong to the burst in progress. The
++ * list is then used to mark these queues as belonging to a large burst if
++ * the burst does become large. The main steps are the following.
++ *
++ * . when the very first queue is activated, the queue is inserted into the
++ * list (as it could be the first queue in a possible burst)
++ *
++ * . if the current burst has not yet become large, and a queue Q that does
++ * not yet belong to the burst is activated shortly after the last time
++ * at which a new queue entered the burst list, then the function appends
++ * Q to the burst list
++ *
++ * . if, as a consequence of the previous step, the burst size reaches
++ * the large-burst threshold, then
++ *
++ * . all the queues in the burst list are marked as belonging to a
++ * large burst
++ *
++ * . the burst list is deleted; in fact, the burst list already served
++ * its purpose (keeping temporarily track of the queues in a burst,
++ * so as to be able to mark them as belonging to a large burst in the
++ * previous sub-step), and now is not needed any more
++ *
++ * . the device enters a large-burst mode
++ *
++ * . if a queue Q that does not belong to the burst is activated while
++ * the device is in large-burst mode and shortly after the last time
++ * at which a queue either entered the burst list or was marked as
++ * belonging to the current large burst, then Q is immediately marked
++ * as belonging to a large burst.
++ *
++ * . if a queue Q that does not belong to the burst is activated a while
++ * later, i.e., not shortly after, than the last time at which a queue
++ * either entered the burst list or was marked as belonging to the
++ * current large burst, then the current burst is deemed as finished and:
++ *
++ * . the large-burst mode is reset if set
++ *
++ * . the burst list is emptied
++ *
++ * . Q is inserted in the burst list, as Q may be the first queue
++ * in a possible new burst (then the burst list contains just Q
++ * after this step).
++ */
++static void bfq_handle_burst(struct bfq_data *bfqd, struct bfq_queue *bfqq,
++ bool idle_for_long_time)
++{
++ /*
++ * If bfqq happened to be activated in a burst, but has been idle
++ * for at least as long as an interactive queue, then we assume
++ * that, in the overall I/O initiated in the burst, the I/O
++ * associated to bfqq is finished. So bfqq does not need to be
++ * treated as a queue belonging to a burst anymore. Accordingly,
++ * we reset bfqq's in_large_burst flag if set, and remove bfqq
++ * from the burst list if it's there. We do not decrement instead
++ * burst_size, because the fact that bfqq does not need to belong
++ * to the burst list any more does not invalidate the fact that
++ * bfqq may have been activated during the current burst.
++ */
++ if (idle_for_long_time) {
++ hlist_del_init(&bfqq->burst_list_node);
++ bfq_clear_bfqq_in_large_burst(bfqq);
++ }
++
++ /*
++ * If bfqq is already in the burst list or is part of a large
++ * burst, then there is nothing else to do.
++ */
++ if (!hlist_unhashed(&bfqq->burst_list_node) ||
++ bfq_bfqq_in_large_burst(bfqq))
++ return;
++
++ /*
++ * If bfqq's activation happens late enough, then the current
++ * burst is finished, and related data structures must be reset.
++ *
++ * In this respect, consider the special case where bfqq is the very
++ * first queue being activated. In this case, last_ins_in_burst is
++ * not yet significant when we get here. But it is easy to verify
++ * that, whether or not the following condition is true, bfqq will
++ * end up being inserted into the burst list. In particular the
++ * list will happen to contain only bfqq. And this is exactly what
++ * has to happen, as bfqq may be the first queue in a possible
++ * burst.
++ */
++ if (time_is_before_jiffies(bfqd->last_ins_in_burst +
++ bfqd->bfq_burst_interval)) {
++ bfqd->large_burst = false;
++ bfq_reset_burst_list(bfqd, bfqq);
++ return;
++ }
++
++ /*
++ * If we get here, then bfqq is being activated shortly after the
++ * last queue. So, if the current burst is also large, we can mark
++ * bfqq as belonging to this large burst immediately.
++ */
++ if (bfqd->large_burst) {
++ bfq_mark_bfqq_in_large_burst(bfqq);
++ return;
++ }
++
++ /*
++ * If we get here, then a large-burst state has not yet been
++ * reached, but bfqq is being activated shortly after the last
++ * queue. Then we add bfqq to the burst.
++ */
++ bfq_add_to_burst(bfqd, bfqq);
++}
++
++static void bfq_add_request(struct request *rq)
++{
++ struct bfq_queue *bfqq = RQ_BFQQ(rq);
++ struct bfq_entity *entity = &bfqq->entity;
++ struct bfq_data *bfqd = bfqq->bfqd;
++ struct request *next_rq, *prev;
++ unsigned long old_wr_coeff = bfqq->wr_coeff;
++ bool interactive = false;
++
++ bfq_log_bfqq(bfqd, bfqq, "add_request %d", rq_is_sync(rq));
++ bfqq->queued[rq_is_sync(rq)]++;
++ bfqd->queued++;
++
++ elv_rb_add(&bfqq->sort_list, rq);
++
++ /*
++ * Check if this request is a better next-serve candidate.
++ */
++ prev = bfqq->next_rq;
++ next_rq = bfq_choose_req(bfqd, bfqq->next_rq, rq, bfqd->last_position);
++ BUG_ON(next_rq == NULL);
++ bfqq->next_rq = next_rq;
++
++ /*
++ * Adjust priority tree position, if next_rq changes.
++ */
++ if (prev != bfqq->next_rq)
++ bfq_rq_pos_tree_add(bfqd, bfqq);
++
++ if (!bfq_bfqq_busy(bfqq)) {
++ bool soft_rt, coop_or_in_burst,
++ idle_for_long_time = time_is_before_jiffies(
++ bfqq->budget_timeout +
++ bfqd->bfq_wr_min_idle_time);
++
++ if (bfq_bfqq_sync(bfqq)) {
++ bool already_in_burst =
++ !hlist_unhashed(&bfqq->burst_list_node) ||
++ bfq_bfqq_in_large_burst(bfqq);
++ bfq_handle_burst(bfqd, bfqq, idle_for_long_time);
++ /*
++ * If bfqq was not already in the current burst,
++ * then, at this point, bfqq either has been
++ * added to the current burst or has caused the
++ * current burst to terminate. In particular, in
++ * the second case, bfqq has become the first
++ * queue in a possible new burst.
++ * In both cases last_ins_in_burst needs to be
++ * moved forward.
++ */
++ if (!already_in_burst)
++ bfqd->last_ins_in_burst = jiffies;
++ }
++
++ coop_or_in_burst = bfq_bfqq_in_large_burst(bfqq) ||
++ bfq_bfqq_cooperations(bfqq) >= bfqd->bfq_coop_thresh;
++ soft_rt = bfqd->bfq_wr_max_softrt_rate > 0 &&
++ !coop_or_in_burst &&
++ time_is_before_jiffies(bfqq->soft_rt_next_start);
++ interactive = !coop_or_in_burst && idle_for_long_time;
++ entity->budget = max_t(unsigned long, bfqq->max_budget,
++ bfq_serv_to_charge(next_rq, bfqq));
++
++ if (!bfq_bfqq_IO_bound(bfqq)) {
++ if (time_before(jiffies,
++ RQ_BIC(rq)->ttime.last_end_request +
++ bfqd->bfq_slice_idle)) {
++ bfqq->requests_within_timer++;
++ if (bfqq->requests_within_timer >=
++ bfqd->bfq_requests_within_timer)
++ bfq_mark_bfqq_IO_bound(bfqq);
++ } else
++ bfqq->requests_within_timer = 0;
++ }
++
++ if (!bfqd->low_latency)
++ goto add_bfqq_busy;
++
++ if (bfq_bfqq_just_split(bfqq))
++ goto set_ioprio_changed;
++
++ /*
++ * If the queue:
++ * - is not being boosted,
++ * - has been idle for enough time,
++ * - is not a sync queue or is linked to a bfq_io_cq (it is
++ * shared "for its nature" or it is not shared and its
++ * requests have not been redirected to a shared queue)
++ * start a weight-raising period.
++ */
++ if (old_wr_coeff == 1 && (interactive || soft_rt) &&
++ (!bfq_bfqq_sync(bfqq) || bfqq->bic != NULL)) {
++ bfqq->wr_coeff = bfqd->bfq_wr_coeff;
++ if (interactive)
++ bfqq->wr_cur_max_time = bfq_wr_duration(bfqd);
++ else
++ bfqq->wr_cur_max_time =
++ bfqd->bfq_wr_rt_max_time;
++ bfq_log_bfqq(bfqd, bfqq,
++ "wrais starting at %lu, rais_max_time %u",
++ jiffies,
++ jiffies_to_msecs(bfqq->wr_cur_max_time));
++ } else if (old_wr_coeff > 1) {
++ if (interactive)
++ bfqq->wr_cur_max_time = bfq_wr_duration(bfqd);
++ else if (coop_or_in_burst ||
++ (bfqq->wr_cur_max_time ==
++ bfqd->bfq_wr_rt_max_time &&
++ !soft_rt)) {
++ bfqq->wr_coeff = 1;
++ bfq_log_bfqq(bfqd, bfqq,
++ "wrais ending at %lu, rais_max_time %u",
++ jiffies,
++ jiffies_to_msecs(bfqq->
++ wr_cur_max_time));
++ } else if (time_before(
++ bfqq->last_wr_start_finish +
++ bfqq->wr_cur_max_time,
++ jiffies +
++ bfqd->bfq_wr_rt_max_time) &&
++ soft_rt) {
++ /*
++ *
++ * The remaining weight-raising time is lower
++ * than bfqd->bfq_wr_rt_max_time, which means
++ * that the application is enjoying weight
++ * raising either because deemed soft-rt in
++ * the near past, or because deemed interactive
++ * a long ago.
++ * In both cases, resetting now the current
++ * remaining weight-raising time for the
++ * application to the weight-raising duration
++ * for soft rt applications would not cause any
++ * latency increase for the application (as the
++ * new duration would be higher than the
++ * remaining time).
++ *
++ * In addition, the application is now meeting
++ * the requirements for being deemed soft rt.
++ * In the end we can correctly and safely
++ * (re)charge the weight-raising duration for
++ * the application with the weight-raising
++ * duration for soft rt applications.
++ *
++ * In particular, doing this recharge now, i.e.,
++ * before the weight-raising period for the
++ * application finishes, reduces the probability
++ * of the following negative scenario:
++ * 1) the weight of a soft rt application is
++ * raised at startup (as for any newly
++ * created application),
++ * 2) since the application is not interactive,
++ * at a certain time weight-raising is
++ * stopped for the application,
++ * 3) at that time the application happens to
++ * still have pending requests, and hence
++ * is destined to not have a chance to be
++ * deemed soft rt before these requests are
++ * completed (see the comments to the
++ * function bfq_bfqq_softrt_next_start()
++ * for details on soft rt detection),
++ * 4) these pending requests experience a high
++ * latency because the application is not
++ * weight-raised while they are pending.
++ */
++ bfqq->last_wr_start_finish = jiffies;
++ bfqq->wr_cur_max_time =
++ bfqd->bfq_wr_rt_max_time;
++ }
++ }
++set_ioprio_changed:
++ if (old_wr_coeff != bfqq->wr_coeff)
++ entity->ioprio_changed = 1;
++add_bfqq_busy:
++ bfqq->last_idle_bklogged = jiffies;
++ bfqq->service_from_backlogged = 0;
++ bfq_clear_bfqq_softrt_update(bfqq);
++ bfq_add_bfqq_busy(bfqd, bfqq);
++ } else {
++ if (bfqd->low_latency && old_wr_coeff == 1 && !rq_is_sync(rq) &&
++ time_is_before_jiffies(
++ bfqq->last_wr_start_finish +
++ bfqd->bfq_wr_min_inter_arr_async)) {
++ bfqq->wr_coeff = bfqd->bfq_wr_coeff;
++ bfqq->wr_cur_max_time = bfq_wr_duration(bfqd);
++
++ bfqd->wr_busy_queues++;
++ entity->ioprio_changed = 1;
++ bfq_log_bfqq(bfqd, bfqq,
++ "non-idle wrais starting at %lu, rais_max_time %u",
++ jiffies,
++ jiffies_to_msecs(bfqq->wr_cur_max_time));
++ }
++ if (prev != bfqq->next_rq)
++ bfq_updated_next_req(bfqd, bfqq);
++ }
++
++ if (bfqd->low_latency &&
++ (old_wr_coeff == 1 || bfqq->wr_coeff == 1 || interactive))
++ bfqq->last_wr_start_finish = jiffies;
++}
++
++static struct request *bfq_find_rq_fmerge(struct bfq_data *bfqd,
++ struct bio *bio)
++{
++ struct task_struct *tsk = current;
++ struct bfq_io_cq *bic;
++ struct bfq_queue *bfqq;
++
++ bic = bfq_bic_lookup(bfqd, tsk->io_context);
++ if (bic == NULL)
++ return NULL;
++
++ bfqq = bic_to_bfqq(bic, bfq_bio_sync(bio));
++ if (bfqq != NULL)
++ return elv_rb_find(&bfqq->sort_list, bio_end_sector(bio));
++
++ return NULL;
++}
++
++static void bfq_activate_request(struct request_queue *q, struct request *rq)
++{
++ struct bfq_data *bfqd = q->elevator->elevator_data;
++
++ bfqd->rq_in_driver++;
++ bfqd->last_position = blk_rq_pos(rq) + blk_rq_sectors(rq);
++ bfq_log(bfqd, "activate_request: new bfqd->last_position %llu",
++ (long long unsigned)bfqd->last_position);
++}
++
++static inline void bfq_deactivate_request(struct request_queue *q,
++ struct request *rq)
++{
++ struct bfq_data *bfqd = q->elevator->elevator_data;
++
++ BUG_ON(bfqd->rq_in_driver == 0);
++ bfqd->rq_in_driver--;
++}
++
++static void bfq_remove_request(struct request *rq)
++{
++ struct bfq_queue *bfqq = RQ_BFQQ(rq);
++ struct bfq_data *bfqd = bfqq->bfqd;
++ const int sync = rq_is_sync(rq);
++
++ if (bfqq->next_rq == rq) {
++ bfqq->next_rq = bfq_find_next_rq(bfqd, bfqq, rq);
++ bfq_updated_next_req(bfqd, bfqq);
++ }
++
++ list_del_init(&rq->queuelist);
++ BUG_ON(bfqq->queued[sync] == 0);
++ bfqq->queued[sync]--;
++ bfqd->queued--;
++ elv_rb_del(&bfqq->sort_list, rq);
++
++ if (RB_EMPTY_ROOT(&bfqq->sort_list)) {
++ if (bfq_bfqq_busy(bfqq) && bfqq != bfqd->in_service_queue)
++ bfq_del_bfqq_busy(bfqd, bfqq, 1);
++ /*
++ * Remove queue from request-position tree as it is empty.
++ */
++ if (bfqq->pos_root != NULL) {
++ rb_erase(&bfqq->pos_node, bfqq->pos_root);
++ bfqq->pos_root = NULL;
++ }
++ }
++
++ if (rq->cmd_flags & REQ_META) {
++ BUG_ON(bfqq->meta_pending == 0);
++ bfqq->meta_pending--;
++ }
++}
++
++static int bfq_merge(struct request_queue *q, struct request **req,
++ struct bio *bio)
++{
++ struct bfq_data *bfqd = q->elevator->elevator_data;
++ struct request *__rq;
++
++ __rq = bfq_find_rq_fmerge(bfqd, bio);
++ if (__rq != NULL && elv_rq_merge_ok(__rq, bio)) {
++ *req = __rq;
++ return ELEVATOR_FRONT_MERGE;
++ }
++
++ return ELEVATOR_NO_MERGE;
++}
++
++static void bfq_merged_request(struct request_queue *q, struct request *req,
++ int type)
++{
++ if (type == ELEVATOR_FRONT_MERGE &&
++ rb_prev(&req->rb_node) &&
++ blk_rq_pos(req) <
++ blk_rq_pos(container_of(rb_prev(&req->rb_node),
++ struct request, rb_node))) {
++ struct bfq_queue *bfqq = RQ_BFQQ(req);
++ struct bfq_data *bfqd = bfqq->bfqd;
++ struct request *prev, *next_rq;
++
++ /* Reposition request in its sort_list */
++ elv_rb_del(&bfqq->sort_list, req);
++ elv_rb_add(&bfqq->sort_list, req);
++ /* Choose next request to be served for bfqq */
++ prev = bfqq->next_rq;
++ next_rq = bfq_choose_req(bfqd, bfqq->next_rq, req,
++ bfqd->last_position);
++ BUG_ON(next_rq == NULL);
++ bfqq->next_rq = next_rq;
++ /*
++ * If next_rq changes, update both the queue's budget to
++ * fit the new request and the queue's position in its
++ * rq_pos_tree.
++ */
++ if (prev != bfqq->next_rq) {
++ bfq_updated_next_req(bfqd, bfqq);
++ bfq_rq_pos_tree_add(bfqd, bfqq);
++ }
++ }
++}
++
++static void bfq_merged_requests(struct request_queue *q, struct request *rq,
++ struct request *next)
++{
++ struct bfq_queue *bfqq = RQ_BFQQ(rq);
++
++ /*
++ * Reposition in fifo if next is older than rq.
++ */
++ if (!list_empty(&rq->queuelist) && !list_empty(&next->queuelist) &&
++ time_before(next->fifo_time, rq->fifo_time)) {
++ list_move(&rq->queuelist, &next->queuelist);
++ rq->fifo_time = next->fifo_time;
++ }
++
++ if (bfqq->next_rq == next)
++ bfqq->next_rq = rq;
++
++ bfq_remove_request(next);
++}
++
++/* Must be called with bfqq != NULL */
++static inline void bfq_bfqq_end_wr(struct bfq_queue *bfqq)
++{
++ BUG_ON(bfqq == NULL);
++ if (bfq_bfqq_busy(bfqq))
++ bfqq->bfqd->wr_busy_queues--;
++ bfqq->wr_coeff = 1;
++ bfqq->wr_cur_max_time = 0;
++ /* Trigger a weight change on the next activation of the queue */
++ bfqq->entity.ioprio_changed = 1;
++}
++
++static void bfq_end_wr_async_queues(struct bfq_data *bfqd,
++ struct bfq_group *bfqg)
++{
++ int i, j;
++
++ for (i = 0; i < 2; i++)
++ for (j = 0; j < IOPRIO_BE_NR; j++)
++ if (bfqg->async_bfqq[i][j] != NULL)
++ bfq_bfqq_end_wr(bfqg->async_bfqq[i][j]);
++ if (bfqg->async_idle_bfqq != NULL)
++ bfq_bfqq_end_wr(bfqg->async_idle_bfqq);
++}
++
++static void bfq_end_wr(struct bfq_data *bfqd)
++{
++ struct bfq_queue *bfqq;
++
++ spin_lock_irq(bfqd->queue->queue_lock);
++
++ list_for_each_entry(bfqq, &bfqd->active_list, bfqq_list)
++ bfq_bfqq_end_wr(bfqq);
++ list_for_each_entry(bfqq, &bfqd->idle_list, bfqq_list)
++ bfq_bfqq_end_wr(bfqq);
++ bfq_end_wr_async(bfqd);
++
++ spin_unlock_irq(bfqd->queue->queue_lock);
++}
++
++static inline sector_t bfq_io_struct_pos(void *io_struct, bool request)
++{
++ if (request)
++ return blk_rq_pos(io_struct);
++ else
++ return ((struct bio *)io_struct)->bi_iter.bi_sector;
++}
++
++static inline sector_t bfq_dist_from(sector_t pos1,
++ sector_t pos2)
++{
++ if (pos1 >= pos2)
++ return pos1 - pos2;
++ else
++ return pos2 - pos1;
++}
++
++static inline int bfq_rq_close_to_sector(void *io_struct, bool request,
++ sector_t sector)
++{
++ return bfq_dist_from(bfq_io_struct_pos(io_struct, request), sector) <=
++ BFQQ_SEEK_THR;
++}
++
++static struct bfq_queue *bfqq_close(struct bfq_data *bfqd, sector_t sector)
++{
++ struct rb_root *root = &bfqd->rq_pos_tree;
++ struct rb_node *parent, *node;
++ struct bfq_queue *__bfqq;
++
++ if (RB_EMPTY_ROOT(root))
++ return NULL;
++
++ /*
++ * First, if we find a request starting at the end of the last
++ * request, choose it.
++ */
++ __bfqq = bfq_rq_pos_tree_lookup(bfqd, root, sector, &parent, NULL);
++ if (__bfqq != NULL)
++ return __bfqq;
++
++ /*
++ * If the exact sector wasn't found, the parent of the NULL leaf
++ * will contain the closest sector (rq_pos_tree sorted by
++ * next_request position).
++ */
++ __bfqq = rb_entry(parent, struct bfq_queue, pos_node);
++ if (bfq_rq_close_to_sector(__bfqq->next_rq, true, sector))
++ return __bfqq;
++
++ if (blk_rq_pos(__bfqq->next_rq) < sector)
++ node = rb_next(&__bfqq->pos_node);
++ else
++ node = rb_prev(&__bfqq->pos_node);
++ if (node == NULL)
++ return NULL;
++
++ __bfqq = rb_entry(node, struct bfq_queue, pos_node);
++ if (bfq_rq_close_to_sector(__bfqq->next_rq, true, sector))
++ return __bfqq;
++
++ return NULL;
++}
++
++/*
++ * bfqd - obvious
++ * cur_bfqq - passed in so that we don't decide that the current queue
++ * is closely cooperating with itself
++ * sector - used as a reference point to search for a close queue
++ */
++static struct bfq_queue *bfq_close_cooperator(struct bfq_data *bfqd,
++ struct bfq_queue *cur_bfqq,
++ sector_t sector)
++{
++ struct bfq_queue *bfqq;
++
++ if (bfq_class_idle(cur_bfqq))
++ return NULL;
++ if (!bfq_bfqq_sync(cur_bfqq))
++ return NULL;
++ if (BFQQ_SEEKY(cur_bfqq))
++ return NULL;
++
++ /* If device has only one backlogged bfq_queue, don't search. */
++ if (bfqd->busy_queues == 1)
++ return NULL;
++
++ /*
++ * We should notice if some of the queues are cooperating, e.g.
++ * working closely on the same area of the disk. In that case,
++ * we can group them together and don't waste time idling.
++ */
++ bfqq = bfqq_close(bfqd, sector);
++ if (bfqq == NULL || bfqq == cur_bfqq)
++ return NULL;
++
++ /*
++ * Do not merge queues from different bfq_groups.
++ */
++ if (bfqq->entity.parent != cur_bfqq->entity.parent)
++ return NULL;
++
++ /*
++ * It only makes sense to merge sync queues.
++ */
++ if (!bfq_bfqq_sync(bfqq))
++ return NULL;
++ if (BFQQ_SEEKY(bfqq))
++ return NULL;
++
++ /*
++ * Do not merge queues of different priority classes.
++ */
++ if (bfq_class_rt(bfqq) != bfq_class_rt(cur_bfqq))
++ return NULL;
++
++ return bfqq;
++}
++
++static struct bfq_queue *
++bfq_setup_merge(struct bfq_queue *bfqq, struct bfq_queue *new_bfqq)
++{
++ int process_refs, new_process_refs;
++ struct bfq_queue *__bfqq;
++
++ /*
++ * If there are no process references on the new_bfqq, then it is
++ * unsafe to follow the ->new_bfqq chain as other bfqq's in the chain
++ * may have dropped their last reference (not just their last process
++ * reference).
++ */
++ if (!bfqq_process_refs(new_bfqq))
++ return NULL;
++
++ /* Avoid a circular list and skip interim queue merges. */
++ while ((__bfqq = new_bfqq->new_bfqq)) {
++ if (__bfqq == bfqq)
++ return NULL;
++ new_bfqq = __bfqq;
++ }
++
++ process_refs = bfqq_process_refs(bfqq);
++ new_process_refs = bfqq_process_refs(new_bfqq);
++ /*
++ * If the process for the bfqq has gone away, there is no
++ * sense in merging the queues.
++ */
++ if (process_refs == 0 || new_process_refs == 0)
++ return NULL;
++
++ bfq_log_bfqq(bfqq->bfqd, bfqq, "scheduling merge with queue %d",
++ new_bfqq->pid);
++
++ /*
++ * Merging is just a redirection: the requests of the process
++ * owning one of the two queues are redirected to the other queue.
++ * The latter queue, in its turn, is set as shared if this is the
++ * first time that the requests of some process are redirected to
++ * it.
++ *
++ * We redirect bfqq to new_bfqq and not the opposite, because we
++ * are in the context of the process owning bfqq, hence we have
++ * the io_cq of this process. So we can immediately configure this
++ * io_cq to redirect the requests of the process to new_bfqq.
++ *
++ * NOTE, even if new_bfqq coincides with the in-service queue, the
++ * io_cq of new_bfqq is not available, because, if the in-service
++ * queue is shared, bfqd->in_service_bic may not point to the
++ * io_cq of the in-service queue.
++ * Redirecting the requests of the process owning bfqq to the
++ * currently in-service queue is in any case the best option, as
++ * we feed the in-service queue with new requests close to the
++ * last request served and, by doing so, hopefully increase the
++ * throughput.
++ */
++ bfqq->new_bfqq = new_bfqq;
++ atomic_add(process_refs, &new_bfqq->ref);
++ return new_bfqq;
++}
++
++/*
++ * Attempt to schedule a merge of bfqq with the currently in-service queue
++ * or with a close queue among the scheduled queues.
++ * Return NULL if no merge was scheduled, a pointer to the shared bfq_queue
++ * structure otherwise.
++ *
++ * The OOM queue is not allowed to participate to cooperation: in fact, since
++ * the requests temporarily redirected to the OOM queue could be redirected
++ * again to dedicated queues at any time, the state needed to correctly
++ * handle merging with the OOM queue would be quite complex and expensive
++ * to maintain. Besides, in such a critical condition as an out of memory,
++ * the benefits of queue merging may be little relevant, or even negligible.
++ */
++static struct bfq_queue *
++bfq_setup_cooperator(struct bfq_data *bfqd, struct bfq_queue *bfqq,
++ void *io_struct, bool request)
++{
++ struct bfq_queue *in_service_bfqq, *new_bfqq;
++
++ if (bfqq->new_bfqq)
++ return bfqq->new_bfqq;
++
++ if (!io_struct || unlikely(bfqq == &bfqd->oom_bfqq))
++ return NULL;
++
++ in_service_bfqq = bfqd->in_service_queue;
++
++ if (in_service_bfqq == NULL || in_service_bfqq == bfqq ||
++ !bfqd->in_service_bic ||
++ unlikely(in_service_bfqq == &bfqd->oom_bfqq))
++ goto check_scheduled;
++
++ if (bfq_class_idle(in_service_bfqq) || bfq_class_idle(bfqq))
++ goto check_scheduled;
++
++ if (bfq_class_rt(in_service_bfqq) != bfq_class_rt(bfqq))
++ goto check_scheduled;
++
++ if (in_service_bfqq->entity.parent != bfqq->entity.parent)
++ goto check_scheduled;
++
++ if (bfq_rq_close_to_sector(io_struct, request, bfqd->last_position) &&
++ bfq_bfqq_sync(in_service_bfqq) && bfq_bfqq_sync(bfqq)) {
++ new_bfqq = bfq_setup_merge(bfqq, in_service_bfqq);
++ if (new_bfqq != NULL)
++ return new_bfqq; /* Merge with in-service queue */
++ }
++
++ /*
++ * Check whether there is a cooperator among currently scheduled
++ * queues. The only thing we need is that the bio/request is not
++ * NULL, as we need it to establish whether a cooperator exists.
++ */
++check_scheduled:
++ new_bfqq = bfq_close_cooperator(bfqd, bfqq,
++ bfq_io_struct_pos(io_struct, request));
++ if (new_bfqq && likely(new_bfqq != &bfqd->oom_bfqq))
++ return bfq_setup_merge(bfqq, new_bfqq);
++
++ return NULL;
++}
++
++static inline void
++bfq_bfqq_save_state(struct bfq_queue *bfqq)
++{
++ /*
++ * If bfqq->bic == NULL, the queue is already shared or its requests
++ * have already been redirected to a shared queue; both idle window
++ * and weight raising state have already been saved. Do nothing.
++ */
++ if (bfqq->bic == NULL)
++ return;
++ if (bfqq->bic->wr_time_left)
++ /*
++ * This is the queue of a just-started process, and would
++ * deserve weight raising: we set wr_time_left to the full
++ * weight-raising duration to trigger weight-raising when
++ * and if the queue is split and the first request of the
++ * queue is enqueued.
++ */
++ bfqq->bic->wr_time_left = bfq_wr_duration(bfqq->bfqd);
++ else if (bfqq->wr_coeff > 1) {
++ unsigned long wr_duration =
++ jiffies - bfqq->last_wr_start_finish;
++ /*
++ * It may happen that a queue's weight raising period lasts
++ * longer than its wr_cur_max_time, as weight raising is
++ * handled only when a request is enqueued or dispatched (it
++ * does not use any timer). If the weight raising period is
++ * about to end, don't save it.
++ */
++ if (bfqq->wr_cur_max_time <= wr_duration)
++ bfqq->bic->wr_time_left = 0;
++ else
++ bfqq->bic->wr_time_left =
++ bfqq->wr_cur_max_time - wr_duration;
++ /*
++ * The bfq_queue is becoming shared or the requests of the
++ * process owning the queue are being redirected to a shared
++ * queue. Stop the weight raising period of the queue, as in
++ * both cases it should not be owned by an interactive or
++ * soft real-time application.
++ */
++ bfq_bfqq_end_wr(bfqq);
++ } else
++ bfqq->bic->wr_time_left = 0;
++ bfqq->bic->saved_idle_window = bfq_bfqq_idle_window(bfqq);
++ bfqq->bic->saved_IO_bound = bfq_bfqq_IO_bound(bfqq);
++ bfqq->bic->saved_in_large_burst = bfq_bfqq_in_large_burst(bfqq);
++ bfqq->bic->was_in_burst_list = !hlist_unhashed(&bfqq->burst_list_node);
++ bfqq->bic->cooperations++;
++ bfqq->bic->failed_cooperations = 0;
++}
++
++static inline void
++bfq_get_bic_reference(struct bfq_queue *bfqq)
++{
++ /*
++ * If bfqq->bic has a non-NULL value, the bic to which it belongs
++ * is about to begin using a shared bfq_queue.
++ */
++ if (bfqq->bic)
++ atomic_long_inc(&bfqq->bic->icq.ioc->refcount);
++}
++
++static void
++bfq_merge_bfqqs(struct bfq_data *bfqd, struct bfq_io_cq *bic,
++ struct bfq_queue *bfqq, struct bfq_queue *new_bfqq)
++{
++ bfq_log_bfqq(bfqd, bfqq, "merging with queue %lu",
++ (long unsigned)new_bfqq->pid);
++ /* Save weight raising and idle window of the merged queues */
++ bfq_bfqq_save_state(bfqq);
++ bfq_bfqq_save_state(new_bfqq);
++ if (bfq_bfqq_IO_bound(bfqq))
++ bfq_mark_bfqq_IO_bound(new_bfqq);
++ bfq_clear_bfqq_IO_bound(bfqq);
++ /*
++ * Grab a reference to the bic, to prevent it from being destroyed
++ * before being possibly touched by a bfq_split_bfqq().
++ */
++ bfq_get_bic_reference(bfqq);
++ bfq_get_bic_reference(new_bfqq);
++ /*
++ * Merge queues (that is, let bic redirect its requests to new_bfqq)
++ */
++ bic_set_bfqq(bic, new_bfqq, 1);
++ bfq_mark_bfqq_coop(new_bfqq);
++ /*
++ * new_bfqq now belongs to at least two bics (it is a shared queue):
++ * set new_bfqq->bic to NULL. bfqq either:
++ * - does not belong to any bic any more, and hence bfqq->bic must
++ * be set to NULL, or
++ * - is a queue whose owning bics have already been redirected to a
++ * different queue, hence the queue is destined to not belong to
++ * any bic soon and bfqq->bic is already NULL (therefore the next
++ * assignment causes no harm).
++ */
++ new_bfqq->bic = NULL;
++ bfqq->bic = NULL;
++ bfq_put_queue(bfqq);
++}
++
++static inline void bfq_bfqq_increase_failed_cooperations(struct bfq_queue *bfqq)
++{
++ struct bfq_io_cq *bic = bfqq->bic;
++ struct bfq_data *bfqd = bfqq->bfqd;
++
++ if (bic && bfq_bfqq_cooperations(bfqq) >= bfqd->bfq_coop_thresh) {
++ bic->failed_cooperations++;
++ if (bic->failed_cooperations >= bfqd->bfq_failed_cooperations)
++ bic->cooperations = 0;
++ }
++}
++
++static int bfq_allow_merge(struct request_queue *q, struct request *rq,
++ struct bio *bio)
++{
++ struct bfq_data *bfqd = q->elevator->elevator_data;
++ struct bfq_io_cq *bic;
++ struct bfq_queue *bfqq, *new_bfqq;
++
++ /*
++ * Disallow merge of a sync bio into an async request.
++ */
++ if (bfq_bio_sync(bio) && !rq_is_sync(rq))
++ return 0;
++
++ /*
++ * Lookup the bfqq that this bio will be queued with. Allow
++ * merge only if rq is queued there.
++ * Queue lock is held here.
++ */
++ bic = bfq_bic_lookup(bfqd, current->io_context);
++ if (bic == NULL)
++ return 0;
++
++ bfqq = bic_to_bfqq(bic, bfq_bio_sync(bio));
++ /*
++ * We take advantage of this function to perform an early merge
++ * of the queues of possible cooperating processes.
++ */
++ if (bfqq != NULL) {
++ new_bfqq = bfq_setup_cooperator(bfqd, bfqq, bio, false);
++ if (new_bfqq != NULL) {
++ bfq_merge_bfqqs(bfqd, bic, bfqq, new_bfqq);
++ /*
++ * If we get here, the bio will be queued in the
++ * shared queue, i.e., new_bfqq, so use new_bfqq
++ * to decide whether bio and rq can be merged.
++ */
++ bfqq = new_bfqq;
++ } else
++ bfq_bfqq_increase_failed_cooperations(bfqq);
++ }
++
++ return bfqq == RQ_BFQQ(rq);
++}
++
++static void __bfq_set_in_service_queue(struct bfq_data *bfqd,
++ struct bfq_queue *bfqq)
++{
++ if (bfqq != NULL) {
++ bfq_mark_bfqq_must_alloc(bfqq);
++ bfq_mark_bfqq_budget_new(bfqq);
++ bfq_clear_bfqq_fifo_expire(bfqq);
++
++ bfqd->budgets_assigned = (bfqd->budgets_assigned*7 + 256) / 8;
++
++ bfq_log_bfqq(bfqd, bfqq,
++ "set_in_service_queue, cur-budget = %lu",
++ bfqq->entity.budget);
++ }
++
++ bfqd->in_service_queue = bfqq;
++}
++
++/*
++ * Get and set a new queue for service.
++ */
++static struct bfq_queue *bfq_set_in_service_queue(struct bfq_data *bfqd)
++{
++ struct bfq_queue *bfqq = bfq_get_next_queue(bfqd);
++
++ __bfq_set_in_service_queue(bfqd, bfqq);
++ return bfqq;
++}
++
++/*
++ * If enough samples have been computed, return the current max budget
++ * stored in bfqd, which is dynamically updated according to the
++ * estimated disk peak rate; otherwise return the default max budget
++ */
++static inline unsigned long bfq_max_budget(struct bfq_data *bfqd)
++{
++ if (bfqd->budgets_assigned < 194)
++ return bfq_default_max_budget;
++ else
++ return bfqd->bfq_max_budget;
++}
++
++/*
++ * Return min budget, which is a fraction of the current or default
++ * max budget (trying with 1/32)
++ */
++static inline unsigned long bfq_min_budget(struct bfq_data *bfqd)
++{
++ if (bfqd->budgets_assigned < 194)
++ return bfq_default_max_budget / 32;
++ else
++ return bfqd->bfq_max_budget / 32;
++}
++
++static void bfq_arm_slice_timer(struct bfq_data *bfqd)
++{
++ struct bfq_queue *bfqq = bfqd->in_service_queue;
++ struct bfq_io_cq *bic;
++ unsigned long sl;
++
++ BUG_ON(!RB_EMPTY_ROOT(&bfqq->sort_list));
++
++ /* Processes have exited, don't wait. */
++ bic = bfqd->in_service_bic;
++ if (bic == NULL || atomic_read(&bic->icq.ioc->active_ref) == 0)
++ return;
++
++ bfq_mark_bfqq_wait_request(bfqq);
++
++ /*
++ * We don't want to idle for seeks, but we do want to allow
++ * fair distribution of slice time for a process doing back-to-back
++ * seeks. So allow a little bit of time for him to submit a new rq.
++ *
++ * To prevent processes with (partly) seeky workloads from
++ * being too ill-treated, grant them a small fraction of the
++ * assigned budget before reducing the waiting time to
++ * BFQ_MIN_TT. This happened to help reduce latency.
++ */
++ sl = bfqd->bfq_slice_idle;
++ /*
++ * Unless the queue is being weight-raised, grant only minimum idle
++ * time if the queue either has been seeky for long enough or has
++ * already proved to be constantly seeky.
++ */
++ if (bfq_sample_valid(bfqq->seek_samples) &&
++ ((BFQQ_SEEKY(bfqq) && bfqq->entity.service >
++ bfq_max_budget(bfqq->bfqd) / 8) ||
++ bfq_bfqq_constantly_seeky(bfqq)) && bfqq->wr_coeff == 1)
++ sl = min(sl, msecs_to_jiffies(BFQ_MIN_TT));
++ else if (bfqq->wr_coeff > 1)
++ sl = sl * 3;
++ bfqd->last_idling_start = ktime_get();
++ mod_timer(&bfqd->idle_slice_timer, jiffies + sl);
++ bfq_log(bfqd, "arm idle: %u/%u ms",
++ jiffies_to_msecs(sl), jiffies_to_msecs(bfqd->bfq_slice_idle));
++}
++
++/*
++ * Set the maximum time for the in-service queue to consume its
++ * budget. This prevents seeky processes from lowering the disk
++ * throughput (always guaranteed with a time slice scheme as in CFQ).
++ */
++static void bfq_set_budget_timeout(struct bfq_data *bfqd)
++{
++ struct bfq_queue *bfqq = bfqd->in_service_queue;
++ unsigned int timeout_coeff;
++ if (bfqq->wr_cur_max_time == bfqd->bfq_wr_rt_max_time)
++ timeout_coeff = 1;
++ else
++ timeout_coeff = bfqq->entity.weight / bfqq->entity.orig_weight;
++
++ bfqd->last_budget_start = ktime_get();
++
++ bfq_clear_bfqq_budget_new(bfqq);
++ bfqq->budget_timeout = jiffies +
++ bfqd->bfq_timeout[bfq_bfqq_sync(bfqq)] * timeout_coeff;
++
++ bfq_log_bfqq(bfqd, bfqq, "set budget_timeout %u",
++ jiffies_to_msecs(bfqd->bfq_timeout[bfq_bfqq_sync(bfqq)] *
++ timeout_coeff));
++}
++
++/*
++ * Move request from internal lists to the request queue dispatch list.
++ */
++static void bfq_dispatch_insert(struct request_queue *q, struct request *rq)
++{
++ struct bfq_data *bfqd = q->elevator->elevator_data;
++ struct bfq_queue *bfqq = RQ_BFQQ(rq);
++
++ /*
++ * For consistency, the next instruction should have been executed
++ * after removing the request from the queue and dispatching it.
++ * We execute instead this instruction before bfq_remove_request()
++ * (and hence introduce a temporary inconsistency), for efficiency.
++ * In fact, in a forced_dispatch, this prevents two counters related
++ * to bfqq->dispatched to risk to be uselessly decremented if bfqq
++ * is not in service, and then to be incremented again after
++ * incrementing bfqq->dispatched.
++ */
++ bfqq->dispatched++;
++ bfq_remove_request(rq);
++ elv_dispatch_sort(q, rq);
++
++ if (bfq_bfqq_sync(bfqq))
++ bfqd->sync_flight++;
++}
++
++/*
++ * Return expired entry, or NULL to just start from scratch in rbtree.
++ */
++static struct request *bfq_check_fifo(struct bfq_queue *bfqq)
++{
++ struct request *rq = NULL;
++
++ if (bfq_bfqq_fifo_expire(bfqq))
++ return NULL;
++
++ bfq_mark_bfqq_fifo_expire(bfqq);
++
++ if (list_empty(&bfqq->fifo))
++ return NULL;
++
++ rq = rq_entry_fifo(bfqq->fifo.next);
++
++ if (time_before(jiffies, rq->fifo_time))
++ return NULL;
++
++ return rq;
++}
++
++static inline unsigned long bfq_bfqq_budget_left(struct bfq_queue *bfqq)
++{
++ struct bfq_entity *entity = &bfqq->entity;
++ return entity->budget - entity->service;
++}
++
++static void __bfq_bfqq_expire(struct bfq_data *bfqd, struct bfq_queue *bfqq)
++{
++ BUG_ON(bfqq != bfqd->in_service_queue);
++
++ __bfq_bfqd_reset_in_service(bfqd);
++
++ /*
++ * If this bfqq is shared between multiple processes, check
++ * to make sure that those processes are still issuing I/Os
++ * within the mean seek distance. If not, it may be time to
++ * break the queues apart again.
++ */
++ if (bfq_bfqq_coop(bfqq) && BFQQ_SEEKY(bfqq))
++ bfq_mark_bfqq_split_coop(bfqq);
++
++ if (RB_EMPTY_ROOT(&bfqq->sort_list)) {
++ /*
++ * Overloading budget_timeout field to store the time
++ * at which the queue remains with no backlog; used by
++ * the weight-raising mechanism.
++ */
++ bfqq->budget_timeout = jiffies;
++ bfq_del_bfqq_busy(bfqd, bfqq, 1);
++ } else {
++ bfq_activate_bfqq(bfqd, bfqq);
++ /*
++ * Resort priority tree of potential close cooperators.
++ */
++ bfq_rq_pos_tree_add(bfqd, bfqq);
++ }
++}
++
++/**
++ * __bfq_bfqq_recalc_budget - try to adapt the budget to the @bfqq behavior.
++ * @bfqd: device data.
++ * @bfqq: queue to update.
++ * @reason: reason for expiration.
++ *
++ * Handle the feedback on @bfqq budget. See the body for detailed
++ * comments.
++ */
++static void __bfq_bfqq_recalc_budget(struct bfq_data *bfqd,
++ struct bfq_queue *bfqq,
++ enum bfqq_expiration reason)
++{
++ struct request *next_rq;
++ unsigned long budget, min_budget;
++
++ budget = bfqq->max_budget;
++ min_budget = bfq_min_budget(bfqd);
++
++ BUG_ON(bfqq != bfqd->in_service_queue);
++
++ bfq_log_bfqq(bfqd, bfqq, "recalc_budg: last budg %lu, budg left %lu",
++ bfqq->entity.budget, bfq_bfqq_budget_left(bfqq));
++ bfq_log_bfqq(bfqd, bfqq, "recalc_budg: last max_budg %lu, min budg %lu",
++ budget, bfq_min_budget(bfqd));
++ bfq_log_bfqq(bfqd, bfqq, "recalc_budg: sync %d, seeky %d",
++ bfq_bfqq_sync(bfqq), BFQQ_SEEKY(bfqd->in_service_queue));
++
++ if (bfq_bfqq_sync(bfqq)) {
++ switch (reason) {
++ /*
++ * Caveat: in all the following cases we trade latency
++ * for throughput.
++ */
++ case BFQ_BFQQ_TOO_IDLE:
++ /*
++ * This is the only case where we may reduce
++ * the budget: if there is no request of the
++ * process still waiting for completion, then
++ * we assume (tentatively) that the timer has
++ * expired because the batch of requests of
++ * the process could have been served with a
++ * smaller budget. Hence, betting that
++ * process will behave in the same way when it
++ * becomes backlogged again, we reduce its
++ * next budget. As long as we guess right,
++ * this budget cut reduces the latency
++ * experienced by the process.
++ *
++ * However, if there are still outstanding
++ * requests, then the process may have not yet
++ * issued its next request just because it is
++ * still waiting for the completion of some of
++ * the still outstanding ones. So in this
++ * subcase we do not reduce its budget, on the
++ * contrary we increase it to possibly boost
++ * the throughput, as discussed in the
++ * comments to the BUDGET_TIMEOUT case.
++ */
++ if (bfqq->dispatched > 0) /* still outstanding reqs */
++ budget = min(budget * 2, bfqd->bfq_max_budget);
++ else {
++ if (budget > 5 * min_budget)
++ budget -= 4 * min_budget;
++ else
++ budget = min_budget;
++ }
++ break;
++ case BFQ_BFQQ_BUDGET_TIMEOUT:
++ /*
++ * We double the budget here because: 1) it
++ * gives the chance to boost the throughput if
++ * this is not a seeky process (which may have
++ * bumped into this timeout because of, e.g.,
++ * ZBR), 2) together with charge_full_budget
++ * it helps give seeky processes higher
++ * timestamps, and hence be served less
++ * frequently.
++ */
++ budget = min(budget * 2, bfqd->bfq_max_budget);
++ break;
++ case BFQ_BFQQ_BUDGET_EXHAUSTED:
++ /*
++ * The process still has backlog, and did not
++ * let either the budget timeout or the disk
++ * idling timeout expire. Hence it is not
++ * seeky, has a short thinktime and may be
++ * happy with a higher budget too. So
++ * definitely increase the budget of this good
++ * candidate to boost the disk throughput.
++ */
++ budget = min(budget * 4, bfqd->bfq_max_budget);
++ break;
++ case BFQ_BFQQ_NO_MORE_REQUESTS:
++ /*
++ * Leave the budget unchanged.
++ */
++ default:
++ return;
++ }
++ } else /* async queue */
++ /* async queues get always the maximum possible budget
++ * (their ability to dispatch is limited by
++ * @bfqd->bfq_max_budget_async_rq).
++ */
++ budget = bfqd->bfq_max_budget;
++
++ bfqq->max_budget = budget;
++
++ if (bfqd->budgets_assigned >= 194 && bfqd->bfq_user_max_budget == 0 &&
++ bfqq->max_budget > bfqd->bfq_max_budget)
++ bfqq->max_budget = bfqd->bfq_max_budget;
++
++ /*
++ * Make sure that we have enough budget for the next request.
++ * Since the finish time of the bfqq must be kept in sync with
++ * the budget, be sure to call __bfq_bfqq_expire() after the
++ * update.
++ */
++ next_rq = bfqq->next_rq;
++ if (next_rq != NULL)
++ bfqq->entity.budget = max_t(unsigned long, bfqq->max_budget,
++ bfq_serv_to_charge(next_rq, bfqq));
++ else
++ bfqq->entity.budget = bfqq->max_budget;
++
++ bfq_log_bfqq(bfqd, bfqq, "head sect: %u, new budget %lu",
++ next_rq != NULL ? blk_rq_sectors(next_rq) : 0,
++ bfqq->entity.budget);
++}
++
++static unsigned long bfq_calc_max_budget(u64 peak_rate, u64 timeout)
++{
++ unsigned long max_budget;
++
++ /*
++ * The max_budget calculated when autotuning is equal to the
++ * amount of sectors transfered in timeout_sync at the
++ * estimated peak rate.
++ */
++ max_budget = (unsigned long)(peak_rate * 1000 *
++ timeout >> BFQ_RATE_SHIFT);
++
++ return max_budget;
++}
++
++/*
++ * In addition to updating the peak rate, checks whether the process
++ * is "slow", and returns 1 if so. This slow flag is used, in addition
++ * to the budget timeout, to reduce the amount of service provided to
++ * seeky processes, and hence reduce their chances to lower the
++ * throughput. See the code for more details.
++ */
++static int bfq_update_peak_rate(struct bfq_data *bfqd, struct bfq_queue *bfqq,
++ int compensate, enum bfqq_expiration reason)
++{
++ u64 bw, usecs, expected, timeout;
++ ktime_t delta;
++ int update = 0;
++
++ if (!bfq_bfqq_sync(bfqq) || bfq_bfqq_budget_new(bfqq))
++ return 0;
++
++ if (compensate)
++ delta = bfqd->last_idling_start;
++ else
++ delta = ktime_get();
++ delta = ktime_sub(delta, bfqd->last_budget_start);
++ usecs = ktime_to_us(delta);
++
++ /* Don't trust short/unrealistic values. */
++ if (usecs < 100 || usecs >= LONG_MAX)
++ return 0;
++
++ /*
++ * Calculate the bandwidth for the last slice. We use a 64 bit
++ * value to store the peak rate, in sectors per usec in fixed
++ * point math. We do so to have enough precision in the estimate
++ * and to avoid overflows.
++ */
++ bw = (u64)bfqq->entity.service << BFQ_RATE_SHIFT;
++ do_div(bw, (unsigned long)usecs);
++
++ timeout = jiffies_to_msecs(bfqd->bfq_timeout[BLK_RW_SYNC]);
++
++ /*
++ * Use only long (> 20ms) intervals to filter out spikes for
++ * the peak rate estimation.
++ */
++ if (usecs > 20000) {
++ if (bw > bfqd->peak_rate ||
++ (!BFQQ_SEEKY(bfqq) &&
++ reason == BFQ_BFQQ_BUDGET_TIMEOUT)) {
++ bfq_log(bfqd, "measured bw =%llu", bw);
++ /*
++ * To smooth oscillations use a low-pass filter with
++ * alpha=7/8, i.e.,
++ * new_rate = (7/8) * old_rate + (1/8) * bw
++ */
++ do_div(bw, 8);
++ if (bw == 0)
++ return 0;
++ bfqd->peak_rate *= 7;
++ do_div(bfqd->peak_rate, 8);
++ bfqd->peak_rate += bw;
++ update = 1;
++ bfq_log(bfqd, "new peak_rate=%llu", bfqd->peak_rate);
++ }
++
++ update |= bfqd->peak_rate_samples == BFQ_PEAK_RATE_SAMPLES - 1;
++
++ if (bfqd->peak_rate_samples < BFQ_PEAK_RATE_SAMPLES)
++ bfqd->peak_rate_samples++;
++
++ if (bfqd->peak_rate_samples == BFQ_PEAK_RATE_SAMPLES &&
++ update) {
++ int dev_type = blk_queue_nonrot(bfqd->queue);
++ if (bfqd->bfq_user_max_budget == 0) {
++ bfqd->bfq_max_budget =
++ bfq_calc_max_budget(bfqd->peak_rate,
++ timeout);
++ bfq_log(bfqd, "new max_budget=%lu",
++ bfqd->bfq_max_budget);
++ }
++ if (bfqd->device_speed == BFQ_BFQD_FAST &&
++ bfqd->peak_rate < device_speed_thresh[dev_type]) {
++ bfqd->device_speed = BFQ_BFQD_SLOW;
++ bfqd->RT_prod = R_slow[dev_type] *
++ T_slow[dev_type];
++ } else if (bfqd->device_speed == BFQ_BFQD_SLOW &&
++ bfqd->peak_rate > device_speed_thresh[dev_type]) {
++ bfqd->device_speed = BFQ_BFQD_FAST;
++ bfqd->RT_prod = R_fast[dev_type] *
++ T_fast[dev_type];
++ }
++ }
++ }
++
++ /*
++ * If the process has been served for a too short time
++ * interval to let its possible sequential accesses prevail on
++ * the initial seek time needed to move the disk head on the
++ * first sector it requested, then give the process a chance
++ * and for the moment return false.
++ */
++ if (bfqq->entity.budget <= bfq_max_budget(bfqd) / 8)
++ return 0;
++
++ /*
++ * A process is considered ``slow'' (i.e., seeky, so that we
++ * cannot treat it fairly in the service domain, as it would
++ * slow down too much the other processes) if, when a slice
++ * ends for whatever reason, it has received service at a
++ * rate that would not be high enough to complete the budget
++ * before the budget timeout expiration.
++ */
++ expected = bw * 1000 * timeout >> BFQ_RATE_SHIFT;
++
++ /*
++ * Caveat: processes doing IO in the slower disk zones will
++ * tend to be slow(er) even if not seeky. And the estimated
++ * peak rate will actually be an average over the disk
++ * surface. Hence, to not be too harsh with unlucky processes,
++ * we keep a budget/3 margin of safety before declaring a
++ * process slow.
++ */
++ return expected > (4 * bfqq->entity.budget) / 3;
++}
++
++/*
++ * To be deemed as soft real-time, an application must meet two
++ * requirements. First, the application must not require an average
++ * bandwidth higher than the approximate bandwidth required to playback or
++ * record a compressed high-definition video.
++ * The next function is invoked on the completion of the last request of a
++ * batch, to compute the next-start time instant, soft_rt_next_start, such
++ * that, if the next request of the application does not arrive before
++ * soft_rt_next_start, then the above requirement on the bandwidth is met.
++ *
++ * The second requirement is that the request pattern of the application is
++ * isochronous, i.e., that, after issuing a request or a batch of requests,
++ * the application stops issuing new requests until all its pending requests
++ * have been completed. After that, the application may issue a new batch,
++ * and so on.
++ * For this reason the next function is invoked to compute
++ * soft_rt_next_start only for applications that meet this requirement,
++ * whereas soft_rt_next_start is set to infinity for applications that do
++ * not.
++ *
++ * Unfortunately, even a greedy application may happen to behave in an
++ * isochronous way if the CPU load is high. In fact, the application may
++ * stop issuing requests while the CPUs are busy serving other processes,
++ * then restart, then stop again for a while, and so on. In addition, if
++ * the disk achieves a low enough throughput with the request pattern
++ * issued by the application (e.g., because the request pattern is random
++ * and/or the device is slow), then the application may meet the above
++ * bandwidth requirement too. To prevent such a greedy application to be
++ * deemed as soft real-time, a further rule is used in the computation of
++ * soft_rt_next_start: soft_rt_next_start must be higher than the current
++ * time plus the maximum time for which the arrival of a request is waited
++ * for when a sync queue becomes idle, namely bfqd->bfq_slice_idle.
++ * This filters out greedy applications, as the latter issue instead their
++ * next request as soon as possible after the last one has been completed
++ * (in contrast, when a batch of requests is completed, a soft real-time
++ * application spends some time processing data).
++ *
++ * Unfortunately, the last filter may easily generate false positives if
++ * only bfqd->bfq_slice_idle is used as a reference time interval and one
++ * or both the following cases occur:
++ * 1) HZ is so low that the duration of a jiffy is comparable to or higher
++ * than bfqd->bfq_slice_idle. This happens, e.g., on slow devices with
++ * HZ=100.
++ * 2) jiffies, instead of increasing at a constant rate, may stop increasing
++ * for a while, then suddenly 'jump' by several units to recover the lost
++ * increments. This seems to happen, e.g., inside virtual machines.
++ * To address this issue, we do not use as a reference time interval just
++ * bfqd->bfq_slice_idle, but bfqd->bfq_slice_idle plus a few jiffies. In
++ * particular we add the minimum number of jiffies for which the filter
++ * seems to be quite precise also in embedded systems and KVM/QEMU virtual
++ * machines.
++ */
++static inline unsigned long bfq_bfqq_softrt_next_start(struct bfq_data *bfqd,
++ struct bfq_queue *bfqq)
++{
++ return max(bfqq->last_idle_bklogged +
++ HZ * bfqq->service_from_backlogged /
++ bfqd->bfq_wr_max_softrt_rate,
++ jiffies + bfqq->bfqd->bfq_slice_idle + 4);
++}
++
++/*
++ * Return the largest-possible time instant such that, for as long as possible,
++ * the current time will be lower than this time instant according to the macro
++ * time_is_before_jiffies().
++ */
++static inline unsigned long bfq_infinity_from_now(unsigned long now)
++{
++ return now + ULONG_MAX / 2;
++}
++
++/**
++ * bfq_bfqq_expire - expire a queue.
++ * @bfqd: device owning the queue.
++ * @bfqq: the queue to expire.
++ * @compensate: if true, compensate for the time spent idling.
++ * @reason: the reason causing the expiration.
++ *
++ *
++ * If the process associated to the queue is slow (i.e., seeky), or in
++ * case of budget timeout, or, finally, if it is async, we
++ * artificially charge it an entire budget (independently of the
++ * actual service it received). As a consequence, the queue will get
++ * higher timestamps than the correct ones upon reactivation, and
++ * hence it will be rescheduled as if it had received more service
++ * than what it actually received. In the end, this class of processes
++ * will receive less service in proportion to how slowly they consume
++ * their budgets (and hence how seriously they tend to lower the
++ * throughput).
++ *
++ * In contrast, when a queue expires because it has been idling for
++ * too much or because it exhausted its budget, we do not touch the
++ * amount of service it has received. Hence when the queue will be
++ * reactivated and its timestamps updated, the latter will be in sync
++ * with the actual service received by the queue until expiration.
++ *
++ * Charging a full budget to the first type of queues and the exact
++ * service to the others has the effect of using the WF2Q+ policy to
++ * schedule the former on a timeslice basis, without violating the
++ * service domain guarantees of the latter.
++ */
++static void bfq_bfqq_expire(struct bfq_data *bfqd,
++ struct bfq_queue *bfqq,
++ int compensate,
++ enum bfqq_expiration reason)
++{
++ int slow;
++ BUG_ON(bfqq != bfqd->in_service_queue);
++
++ /* Update disk peak rate for autotuning and check whether the
++ * process is slow (see bfq_update_peak_rate).
++ */
++ slow = bfq_update_peak_rate(bfqd, bfqq, compensate, reason);
++
++ /*
++ * As above explained, 'punish' slow (i.e., seeky), timed-out
++ * and async queues, to favor sequential sync workloads.
++ *
++ * Processes doing I/O in the slower disk zones will tend to be
++ * slow(er) even if not seeky. Hence, since the estimated peak
++ * rate is actually an average over the disk surface, these
++ * processes may timeout just for bad luck. To avoid punishing
++ * them we do not charge a full budget to a process that
++ * succeeded in consuming at least 2/3 of its budget.
++ */
++ if (slow || (reason == BFQ_BFQQ_BUDGET_TIMEOUT &&
++ bfq_bfqq_budget_left(bfqq) >= bfqq->entity.budget / 3))
++ bfq_bfqq_charge_full_budget(bfqq);
++
++ bfqq->service_from_backlogged += bfqq->entity.service;
++
++ if (BFQQ_SEEKY(bfqq) && reason == BFQ_BFQQ_BUDGET_TIMEOUT &&
++ !bfq_bfqq_constantly_seeky(bfqq)) {
++ bfq_mark_bfqq_constantly_seeky(bfqq);
++ if (!blk_queue_nonrot(bfqd->queue))
++ bfqd->const_seeky_busy_in_flight_queues++;
++ }
++
++ if (reason == BFQ_BFQQ_TOO_IDLE &&
++ bfqq->entity.service <= 2 * bfqq->entity.budget / 10 )
++ bfq_clear_bfqq_IO_bound(bfqq);
++
++ if (bfqd->low_latency && bfqq->wr_coeff == 1)
++ bfqq->last_wr_start_finish = jiffies;
++
++ if (bfqd->low_latency && bfqd->bfq_wr_max_softrt_rate > 0 &&
++ RB_EMPTY_ROOT(&bfqq->sort_list)) {
++ /*
++ * If we get here, and there are no outstanding requests,
++ * then the request pattern is isochronous (see the comments
++ * to the function bfq_bfqq_softrt_next_start()). Hence we
++ * can compute soft_rt_next_start. If, instead, the queue
++ * still has outstanding requests, then we have to wait
++ * for the completion of all the outstanding requests to
++ * discover whether the request pattern is actually
++ * isochronous.
++ */
++ if (bfqq->dispatched == 0)
++ bfqq->soft_rt_next_start =
++ bfq_bfqq_softrt_next_start(bfqd, bfqq);
++ else {
++ /*
++ * The application is still waiting for the
++ * completion of one or more requests:
++ * prevent it from possibly being incorrectly
++ * deemed as soft real-time by setting its
++ * soft_rt_next_start to infinity. In fact,
++ * without this assignment, the application
++ * would be incorrectly deemed as soft
++ * real-time if:
++ * 1) it issued a new request before the
++ * completion of all its in-flight
++ * requests, and
++ * 2) at that time, its soft_rt_next_start
++ * happened to be in the past.
++ */
++ bfqq->soft_rt_next_start =
++ bfq_infinity_from_now(jiffies);
++ /*
++ * Schedule an update of soft_rt_next_start to when
++ * the task may be discovered to be isochronous.
++ */
++ bfq_mark_bfqq_softrt_update(bfqq);
++ }
++ }
++
++ bfq_log_bfqq(bfqd, bfqq,
++ "expire (%d, slow %d, num_disp %d, idle_win %d)", reason,
++ slow, bfqq->dispatched, bfq_bfqq_idle_window(bfqq));
++
++ /*
++ * Increase, decrease or leave budget unchanged according to
++ * reason.
++ */
++ __bfq_bfqq_recalc_budget(bfqd, bfqq, reason);
++ __bfq_bfqq_expire(bfqd, bfqq);
++}
++
++/*
++ * Budget timeout is not implemented through a dedicated timer, but
++ * just checked on request arrivals and completions, as well as on
++ * idle timer expirations.
++ */
++static int bfq_bfqq_budget_timeout(struct bfq_queue *bfqq)
++{
++ if (bfq_bfqq_budget_new(bfqq) ||
++ time_before(jiffies, bfqq->budget_timeout))
++ return 0;
++ return 1;
++}
++
++/*
++ * If we expire a queue that is waiting for the arrival of a new
++ * request, we may prevent the fictitious timestamp back-shifting that
++ * allows the guarantees of the queue to be preserved (see [1] for
++ * this tricky aspect). Hence we return true only if this condition
++ * does not hold, or if the queue is slow enough to deserve only to be
++ * kicked off for preserving a high throughput.
++*/
++static inline int bfq_may_expire_for_budg_timeout(struct bfq_queue *bfqq)
++{
++ bfq_log_bfqq(bfqq->bfqd, bfqq,
++ "may_budget_timeout: wait_request %d left %d timeout %d",
++ bfq_bfqq_wait_request(bfqq),
++ bfq_bfqq_budget_left(bfqq) >= bfqq->entity.budget / 3,
++ bfq_bfqq_budget_timeout(bfqq));
++
++ return (!bfq_bfqq_wait_request(bfqq) ||
++ bfq_bfqq_budget_left(bfqq) >= bfqq->entity.budget / 3)
++ &&
++ bfq_bfqq_budget_timeout(bfqq);
++}
++
++/*
++ * Device idling is allowed only for the queues for which this function
++ * returns true. For this reason, the return value of this function plays a
++ * critical role for both throughput boosting and service guarantees. The
++ * return value is computed through a logical expression. In this rather
++ * long comment, we try to briefly describe all the details and motivations
++ * behind the components of this logical expression.
++ *
++ * First, the expression is false if bfqq is not sync, or if: bfqq happened
++ * to become active during a large burst of queue activations, and the
++ * pattern of requests bfqq contains boosts the throughput if bfqq is
++ * expired. In fact, queues that became active during a large burst benefit
++ * only from throughput, as discussed in the comments to bfq_handle_burst.
++ * In this respect, expiring bfqq certainly boosts the throughput on NCQ-
++ * capable flash-based devices, whereas, on rotational devices, it boosts
++ * the throughput only if bfqq contains random requests.
++ *
++ * On the opposite end, if (a) bfqq is sync, (b) the above burst-related
++ * condition does not hold, and (c) bfqq is being weight-raised, then the
++ * expression always evaluates to true, as device idling is instrumental
++ * for preserving low-latency guarantees (see [1]). If, instead, conditions
++ * (a) and (b) do hold, but (c) does not, then the expression evaluates to
++ * true only if: (1) bfqq is I/O-bound and has a non-null idle window, and
++ * (2) at least one of the following two conditions holds.
++ * The first condition is that the device is not performing NCQ, because
++ * idling the device most certainly boosts the throughput if this condition
++ * holds and bfqq is I/O-bound and has been granted a non-null idle window.
++ * The second compound condition is made of the logical AND of two components.
++ *
++ * The first component is true only if there is no weight-raised busy
++ * queue. This guarantees that the device is not idled for a sync non-
++ * weight-raised queue when there are busy weight-raised queues. The former
++ * is then expired immediately if empty. Combined with the timestamping
++ * rules of BFQ (see [1] for details), this causes sync non-weight-raised
++ * queues to get a lower number of requests served, and hence to ask for a
++ * lower number of requests from the request pool, before the busy weight-
++ * raised queues get served again.
++ *
++ * This is beneficial for the processes associated with weight-raised
++ * queues, when the request pool is saturated (e.g., in the presence of
++ * write hogs). In fact, if the processes associated with the other queues
++ * ask for requests at a lower rate, then weight-raised processes have a
++ * higher probability to get a request from the pool immediately (or at
++ * least soon) when they need one. Hence they have a higher probability to
++ * actually get a fraction of the disk throughput proportional to their
++ * high weight. This is especially true with NCQ-capable drives, which
++ * enqueue several requests in advance and further reorder internally-
++ * queued requests.
++ *
++ * In the end, mistreating non-weight-raised queues when there are busy
++ * weight-raised queues seems to mitigate starvation problems in the
++ * presence of heavy write workloads and NCQ, and hence to guarantee a
++ * higher application and system responsiveness in these hostile scenarios.
++ *
++ * If the first component of the compound condition is instead true, i.e.,
++ * there is no weight-raised busy queue, then the second component of the
++ * compound condition takes into account service-guarantee and throughput
++ * issues related to NCQ (recall that the compound condition is evaluated
++ * only if the device is detected as supporting NCQ).
++ *
++ * As for service guarantees, allowing the drive to enqueue more than one
++ * request at a time, and hence delegating de facto final scheduling
++ * decisions to the drive's internal scheduler, causes loss of control on
++ * the actual request service order. In this respect, when the drive is
++ * allowed to enqueue more than one request at a time, the service
++ * distribution enforced by the drive's internal scheduler is likely to
++ * coincide with the desired device-throughput distribution only in the
++ * following, perfectly symmetric, scenario:
++ * 1) all active queues have the same weight,
++ * 2) all active groups at the same level in the groups tree have the same
++ * weight,
++ * 3) all active groups at the same level in the groups tree have the same
++ * number of children.
++ *
++ * Even in such a scenario, sequential I/O may still receive a preferential
++ * treatment, but this is not likely to be a big issue with flash-based
++ * devices, because of their non-dramatic loss of throughput with random
++ * I/O. Things do differ with HDDs, for which additional care is taken, as
++ * explained after completing the discussion for flash-based devices.
++ *
++ * Unfortunately, keeping the necessary state for evaluating exactly the
++ * above symmetry conditions would be quite complex and time-consuming.
++ * Therefore BFQ evaluates instead the following stronger sub-conditions,
++ * for which it is much easier to maintain the needed state:
++ * 1) all active queues have the same weight,
++ * 2) all active groups have the same weight,
++ * 3) all active groups have at most one active child each.
++ * In particular, the last two conditions are always true if hierarchical
++ * support and the cgroups interface are not enabled, hence no state needs
++ * to be maintained in this case.
++ *
++ * According to the above considerations, the second component of the
++ * compound condition evaluates to true if any of the above symmetry
++ * sub-condition does not hold, or the device is not flash-based. Therefore,
++ * if also the first component is true, then idling is allowed for a sync
++ * queue. These are the only sub-conditions considered if the device is
++ * flash-based, as, for such a device, it is sensible to force idling only
++ * for service-guarantee issues. In fact, as for throughput, idling
++ * NCQ-capable flash-based devices would not boost the throughput even
++ * with sequential I/O; rather it would lower the throughput in proportion
++ * to how fast the device is. In the end, (only) if all the three
++ * sub-conditions hold and the device is flash-based, the compound
++ * condition evaluates to false and therefore no idling is performed.
++ *
++ * As already said, things change with a rotational device, where idling
++ * boosts the throughput with sequential I/O (even with NCQ). Hence, for
++ * such a device the second component of the compound condition evaluates
++ * to true also if the following additional sub-condition does not hold:
++ * the queue is constantly seeky. Unfortunately, this different behavior
++ * with respect to flash-based devices causes an additional asymmetry: if
++ * some sync queues enjoy idling and some other sync queues do not, then
++ * the latter get a low share of the device throughput, simply because the
++ * former get many requests served after being set as in service, whereas
++ * the latter do not. As a consequence, to guarantee the desired throughput
++ * distribution, on HDDs the compound expression evaluates to true (and
++ * hence device idling is performed) also if the following last symmetry
++ * condition does not hold: no other queue is benefiting from idling. Also
++ * this last condition is actually replaced with a simpler-to-maintain and
++ * stronger condition: there is no busy queue which is not constantly seeky
++ * (and hence may also benefit from idling).
++ *
++ * To sum up, when all the required symmetry and throughput-boosting
++ * sub-conditions hold, the second component of the compound condition
++ * evaluates to false, and hence no idling is performed. This helps to
++ * keep the drives' internal queues full on NCQ-capable devices, and hence
++ * to boost the throughput, without causing 'almost' any loss of service
++ * guarantees. The 'almost' follows from the fact that, if the internal
++ * queue of one such device is filled while all the sub-conditions hold,
++ * but at some point in time some sub-condition stops to hold, then it may
++ * become impossible to let requests be served in the new desired order
++ * until all the requests already queued in the device have been served.
++ */
++static inline bool bfq_bfqq_must_not_expire(struct bfq_queue *bfqq)
++{
++ struct bfq_data *bfqd = bfqq->bfqd;
++#ifdef CONFIG_CGROUP_BFQIO
++#define symmetric_scenario (!bfqd->active_numerous_groups && \
++ !bfq_differentiated_weights(bfqd))
++#else
++#define symmetric_scenario (!bfq_differentiated_weights(bfqd))
++#endif
++#define cond_for_seeky_on_ncq_hdd (bfq_bfqq_constantly_seeky(bfqq) && \
++ bfqd->busy_in_flight_queues == \
++ bfqd->const_seeky_busy_in_flight_queues)
++
++#define cond_for_expiring_in_burst (bfq_bfqq_in_large_burst(bfqq) && \
++ bfqd->hw_tag && \
++ (blk_queue_nonrot(bfqd->queue) || \
++ bfq_bfqq_constantly_seeky(bfqq)))
++
++/*
++ * Condition for expiring a non-weight-raised queue (and hence not idling
++ * the device).
++ */
++#define cond_for_expiring_non_wr (bfqd->hw_tag && \
++ (bfqd->wr_busy_queues > 0 || \
++ (symmetric_scenario && \
++ (blk_queue_nonrot(bfqd->queue) || \
++ cond_for_seeky_on_ncq_hdd))))
++
++ return bfq_bfqq_sync(bfqq) &&
++ !cond_for_expiring_in_burst &&
++ (bfqq->wr_coeff > 1 ||
++ (bfq_bfqq_IO_bound(bfqq) && bfq_bfqq_idle_window(bfqq) &&
++ !cond_for_expiring_non_wr)
++ );
++}
++
++/*
++ * If the in-service queue is empty but sync, and the function
++ * bfq_bfqq_must_not_expire returns true, then:
++ * 1) the queue must remain in service and cannot be expired, and
++ * 2) the disk must be idled to wait for the possible arrival of a new
++ * request for the queue.
++ * See the comments to the function bfq_bfqq_must_not_expire for the reasons
++ * why performing device idling is the best choice to boost the throughput
++ * and preserve service guarantees when bfq_bfqq_must_not_expire itself
++ * returns true.
++ */
++static inline bool bfq_bfqq_must_idle(struct bfq_queue *bfqq)
++{
++ struct bfq_data *bfqd = bfqq->bfqd;
++
++ return RB_EMPTY_ROOT(&bfqq->sort_list) && bfqd->bfq_slice_idle != 0 &&
++ bfq_bfqq_must_not_expire(bfqq);
++}
++
++/*
++ * Select a queue for service. If we have a current queue in service,
++ * check whether to continue servicing it, or retrieve and set a new one.
++ */
++static struct bfq_queue *bfq_select_queue(struct bfq_data *bfqd)
++{
++ struct bfq_queue *bfqq;
++ struct request *next_rq;
++ enum bfqq_expiration reason = BFQ_BFQQ_BUDGET_TIMEOUT;
++
++ bfqq = bfqd->in_service_queue;
++ if (bfqq == NULL)
++ goto new_queue;
++
++ bfq_log_bfqq(bfqd, bfqq, "select_queue: already in-service queue");
++
++ if (bfq_may_expire_for_budg_timeout(bfqq) &&
++ !timer_pending(&bfqd->idle_slice_timer) &&
++ !bfq_bfqq_must_idle(bfqq))
++ goto expire;
++
++ next_rq = bfqq->next_rq;
++ /*
++ * If bfqq has requests queued and it has enough budget left to
++ * serve them, keep the queue, otherwise expire it.
++ */
++ if (next_rq != NULL) {
++ if (bfq_serv_to_charge(next_rq, bfqq) >
++ bfq_bfqq_budget_left(bfqq)) {
++ reason = BFQ_BFQQ_BUDGET_EXHAUSTED;
++ goto expire;
++ } else {
++ /*
++ * The idle timer may be pending because we may
++ * not disable disk idling even when a new request
++ * arrives.
++ */
++ if (timer_pending(&bfqd->idle_slice_timer)) {
++ /*
++ * If we get here: 1) at least a new request
++ * has arrived but we have not disabled the
++ * timer because the request was too small,
++ * 2) then the block layer has unplugged
++ * the device, causing the dispatch to be
++ * invoked.
++ *
++ * Since the device is unplugged, now the
++ * requests are probably large enough to
++ * provide a reasonable throughput.
++ * So we disable idling.
++ */
++ bfq_clear_bfqq_wait_request(bfqq);
++ del_timer(&bfqd->idle_slice_timer);
++ }
++ goto keep_queue;
++ }
++ }
++
++ /*
++ * No requests pending. If the in-service queue still has requests
++ * in flight (possibly waiting for a completion) or is idling for a
++ * new request, then keep it.
++ */
++ if (timer_pending(&bfqd->idle_slice_timer) ||
++ (bfqq->dispatched != 0 && bfq_bfqq_must_not_expire(bfqq))) {
++ bfqq = NULL;
++ goto keep_queue;
++ }
++
++ reason = BFQ_BFQQ_NO_MORE_REQUESTS;
++expire:
++ bfq_bfqq_expire(bfqd, bfqq, 0, reason);
++new_queue:
++ bfqq = bfq_set_in_service_queue(bfqd);
++ bfq_log(bfqd, "select_queue: new queue %d returned",
++ bfqq != NULL ? bfqq->pid : 0);
++keep_queue:
++ return bfqq;
++}
++
++static void bfq_update_wr_data(struct bfq_data *bfqd, struct bfq_queue *bfqq)
++{
++ struct bfq_entity *entity = &bfqq->entity;
++ if (bfqq->wr_coeff > 1) { /* queue is being weight-raised */
++ bfq_log_bfqq(bfqd, bfqq,
++ "raising period dur %u/%u msec, old coeff %u, w %d(%d)",
++ jiffies_to_msecs(jiffies - bfqq->last_wr_start_finish),
++ jiffies_to_msecs(bfqq->wr_cur_max_time),
++ bfqq->wr_coeff,
++ bfqq->entity.weight, bfqq->entity.orig_weight);
++
++ BUG_ON(bfqq != bfqd->in_service_queue && entity->weight !=
++ entity->orig_weight * bfqq->wr_coeff);
++ if (entity->ioprio_changed)
++ bfq_log_bfqq(bfqd, bfqq, "WARN: pending prio change");
++
++ /*
++ * If the queue was activated in a burst, or
++ * too much time has elapsed from the beginning
++ * of this weight-raising period, or the queue has
++ * exceeded the acceptable number of cooperations,
++ * then end weight raising.
++ */
++ if (bfq_bfqq_in_large_burst(bfqq) ||
++ bfq_bfqq_cooperations(bfqq) >= bfqd->bfq_coop_thresh ||
++ time_is_before_jiffies(bfqq->last_wr_start_finish +
++ bfqq->wr_cur_max_time)) {
++ bfqq->last_wr_start_finish = jiffies;
++ bfq_log_bfqq(bfqd, bfqq,
++ "wrais ending at %lu, rais_max_time %u",
++ bfqq->last_wr_start_finish,
++ jiffies_to_msecs(bfqq->wr_cur_max_time));
++ bfq_bfqq_end_wr(bfqq);
++ }
++ }
++ /* Update weight both if it must be raised and if it must be lowered */
++ if ((entity->weight > entity->orig_weight) != (bfqq->wr_coeff > 1))
++ __bfq_entity_update_weight_prio(
++ bfq_entity_service_tree(entity),
++ entity);
++}
++
++/*
++ * Dispatch one request from bfqq, moving it to the request queue
++ * dispatch list.
++ */
++static int bfq_dispatch_request(struct bfq_data *bfqd,
++ struct bfq_queue *bfqq)
++{
++ int dispatched = 0;
++ struct request *rq;
++ unsigned long service_to_charge;
++
++ BUG_ON(RB_EMPTY_ROOT(&bfqq->sort_list));
++
++ /* Follow expired path, else get first next available. */
++ rq = bfq_check_fifo(bfqq);
++ if (rq == NULL)
++ rq = bfqq->next_rq;
++ service_to_charge = bfq_serv_to_charge(rq, bfqq);
++
++ if (service_to_charge > bfq_bfqq_budget_left(bfqq)) {
++ /*
++ * This may happen if the next rq is chosen in fifo order
++ * instead of sector order. The budget is properly
++ * dimensioned to be always sufficient to serve the next
++ * request only if it is chosen in sector order. The reason
++ * is that it would be quite inefficient and little useful
++ * to always make sure that the budget is large enough to
++ * serve even the possible next rq in fifo order.
++ * In fact, requests are seldom served in fifo order.
++ *
++ * Expire the queue for budget exhaustion, and make sure
++ * that the next act_budget is enough to serve the next
++ * request, even if it comes from the fifo expired path.
++ */
++ bfqq->next_rq = rq;
++ /*
++ * Since this dispatch is failed, make sure that
++ * a new one will be performed
++ */
++ if (!bfqd->rq_in_driver)
++ bfq_schedule_dispatch(bfqd);
++ goto expire;
++ }
++
++ /* Finally, insert request into driver dispatch list. */
++ bfq_bfqq_served(bfqq, service_to_charge);
++ bfq_dispatch_insert(bfqd->queue, rq);
++
++ bfq_update_wr_data(bfqd, bfqq);
++
++ bfq_log_bfqq(bfqd, bfqq,
++ "dispatched %u sec req (%llu), budg left %lu",
++ blk_rq_sectors(rq),
++ (long long unsigned)blk_rq_pos(rq),
++ bfq_bfqq_budget_left(bfqq));
++
++ dispatched++;
++
++ if (bfqd->in_service_bic == NULL) {
++ atomic_long_inc(&RQ_BIC(rq)->icq.ioc->refcount);
++ bfqd->in_service_bic = RQ_BIC(rq);
++ }
++
++ if (bfqd->busy_queues > 1 && ((!bfq_bfqq_sync(bfqq) &&
++ dispatched >= bfqd->bfq_max_budget_async_rq) ||
++ bfq_class_idle(bfqq)))
++ goto expire;
++
++ return dispatched;
++
++expire:
++ bfq_bfqq_expire(bfqd, bfqq, 0, BFQ_BFQQ_BUDGET_EXHAUSTED);
++ return dispatched;
++}
++
++static int __bfq_forced_dispatch_bfqq(struct bfq_queue *bfqq)
++{
++ int dispatched = 0;
++
++ while (bfqq->next_rq != NULL) {
++ bfq_dispatch_insert(bfqq->bfqd->queue, bfqq->next_rq);
++ dispatched++;
++ }
++
++ BUG_ON(!list_empty(&bfqq->fifo));
++ return dispatched;
++}
++
++/*
++ * Drain our current requests.
++ * Used for barriers and when switching io schedulers on-the-fly.
++ */
++static int bfq_forced_dispatch(struct bfq_data *bfqd)
++{
++ struct bfq_queue *bfqq, *n;
++ struct bfq_service_tree *st;
++ int dispatched = 0;
++
++ bfqq = bfqd->in_service_queue;
++ if (bfqq != NULL)
++ __bfq_bfqq_expire(bfqd, bfqq);
++
++ /*
++ * Loop through classes, and be careful to leave the scheduler
++ * in a consistent state, as feedback mechanisms and vtime
++ * updates cannot be disabled during the process.
++ */
++ list_for_each_entry_safe(bfqq, n, &bfqd->active_list, bfqq_list) {
++ st = bfq_entity_service_tree(&bfqq->entity);
++
++ dispatched += __bfq_forced_dispatch_bfqq(bfqq);
++ bfqq->max_budget = bfq_max_budget(bfqd);
++
++ bfq_forget_idle(st);
++ }
++
++ BUG_ON(bfqd->busy_queues != 0);
++
++ return dispatched;
++}
++
++static int bfq_dispatch_requests(struct request_queue *q, int force)
++{
++ struct bfq_data *bfqd = q->elevator->elevator_data;
++ struct bfq_queue *bfqq;
++ int max_dispatch;
++
++ bfq_log(bfqd, "dispatch requests: %d busy queues", bfqd->busy_queues);
++ if (bfqd->busy_queues == 0)
++ return 0;
++
++ if (unlikely(force))
++ return bfq_forced_dispatch(bfqd);
++
++ bfqq = bfq_select_queue(bfqd);
++ if (bfqq == NULL)
++ return 0;
++
++ max_dispatch = bfqd->bfq_quantum;
++ if (bfq_class_idle(bfqq))
++ max_dispatch = 1;
++
++ if (!bfq_bfqq_sync(bfqq))
++ max_dispatch = bfqd->bfq_max_budget_async_rq;
++
++ if (bfqq->dispatched >= max_dispatch) {
++ if (bfqd->busy_queues > 1)
++ return 0;
++ if (bfqq->dispatched >= 4 * max_dispatch)
++ return 0;
++ }
++
++ if (bfqd->sync_flight != 0 && !bfq_bfqq_sync(bfqq))
++ return 0;
++
++ bfq_clear_bfqq_wait_request(bfqq);
++ BUG_ON(timer_pending(&bfqd->idle_slice_timer));
++
++ if (!bfq_dispatch_request(bfqd, bfqq))
++ return 0;
++
++ bfq_log_bfqq(bfqd, bfqq, "dispatched one request of %d (max_disp %d)",
++ bfqq->pid, max_dispatch);
++
++ return 1;
++}
++
++/*
++ * Task holds one reference to the queue, dropped when task exits. Each rq
++ * in-flight on this queue also holds a reference, dropped when rq is freed.
++ *
++ * Queue lock must be held here.
++ */
++static void bfq_put_queue(struct bfq_queue *bfqq)
++{
++ struct bfq_data *bfqd = bfqq->bfqd;
++
++ BUG_ON(atomic_read(&bfqq->ref) <= 0);
++
++ bfq_log_bfqq(bfqd, bfqq, "put_queue: %p %d", bfqq,
++ atomic_read(&bfqq->ref));
++ if (!atomic_dec_and_test(&bfqq->ref))
++ return;
++
++ BUG_ON(rb_first(&bfqq->sort_list) != NULL);
++ BUG_ON(bfqq->allocated[READ] + bfqq->allocated[WRITE] != 0);
++ BUG_ON(bfqq->entity.tree != NULL);
++ BUG_ON(bfq_bfqq_busy(bfqq));
++ BUG_ON(bfqd->in_service_queue == bfqq);
++
++ if (bfq_bfqq_sync(bfqq))
++ /*
++ * The fact that this queue is being destroyed does not
++ * invalidate the fact that this queue may have been
++ * activated during the current burst. As a consequence,
++ * although the queue does not exist anymore, and hence
++ * needs to be removed from the burst list if there,
++ * the burst size has not to be decremented.
++ */
++ hlist_del_init(&bfqq->burst_list_node);
++
++ bfq_log_bfqq(bfqd, bfqq, "put_queue: %p freed", bfqq);
++
++ kmem_cache_free(bfq_pool, bfqq);
++}
++
++static void bfq_put_cooperator(struct bfq_queue *bfqq)
++{
++ struct bfq_queue *__bfqq, *next;
++
++ /*
++ * If this queue was scheduled to merge with another queue, be
++ * sure to drop the reference taken on that queue (and others in
++ * the merge chain). See bfq_setup_merge and bfq_merge_bfqqs.
++ */
++ __bfqq = bfqq->new_bfqq;
++ while (__bfqq) {
++ if (__bfqq == bfqq)
++ break;
++ next = __bfqq->new_bfqq;
++ bfq_put_queue(__bfqq);
++ __bfqq = next;
++ }
++}
++
++static void bfq_exit_bfqq(struct bfq_data *bfqd, struct bfq_queue *bfqq)
++{
++ if (bfqq == bfqd->in_service_queue) {
++ __bfq_bfqq_expire(bfqd, bfqq);
++ bfq_schedule_dispatch(bfqd);
++ }
++
++ bfq_log_bfqq(bfqd, bfqq, "exit_bfqq: %p, %d", bfqq,
++ atomic_read(&bfqq->ref));
++
++ bfq_put_cooperator(bfqq);
++
++ bfq_put_queue(bfqq);
++}
++
++static inline void bfq_init_icq(struct io_cq *icq)
++{
++ struct bfq_io_cq *bic = icq_to_bic(icq);
++
++ bic->ttime.last_end_request = jiffies;
++ /*
++ * A newly created bic indicates that the process has just
++ * started doing I/O, and is probably mapping into memory its
++ * executable and libraries: it definitely needs weight raising.
++ * There is however the possibility that the process performs,
++ * for a while, I/O close to some other process. EQM intercepts
++ * this behavior and may merge the queue corresponding to the
++ * process with some other queue, BEFORE the weight of the queue
++ * is raised. Merged queues are not weight-raised (they are assumed
++ * to belong to processes that benefit only from high throughput).
++ * If the merge is basically the consequence of an accident, then
++ * the queue will be split soon and will get back its old weight.
++ * It is then important to write down somewhere that this queue
++ * does need weight raising, even if it did not make it to get its
++ * weight raised before being merged. To this purpose, we overload
++ * the field raising_time_left and assign 1 to it, to mark the queue
++ * as needing weight raising.
++ */
++ bic->wr_time_left = 1;
++}
++
++static void bfq_exit_icq(struct io_cq *icq)
++{
++ struct bfq_io_cq *bic = icq_to_bic(icq);
++ struct bfq_data *bfqd = bic_to_bfqd(bic);
++
++ if (bic->bfqq[BLK_RW_ASYNC]) {
++ bfq_exit_bfqq(bfqd, bic->bfqq[BLK_RW_ASYNC]);
++ bic->bfqq[BLK_RW_ASYNC] = NULL;
++ }
++
++ if (bic->bfqq[BLK_RW_SYNC]) {
++ /*
++ * If the bic is using a shared queue, put the reference
++ * taken on the io_context when the bic started using a
++ * shared bfq_queue.
++ */
++ if (bfq_bfqq_coop(bic->bfqq[BLK_RW_SYNC]))
++ put_io_context(icq->ioc);
++ bfq_exit_bfqq(bfqd, bic->bfqq[BLK_RW_SYNC]);
++ bic->bfqq[BLK_RW_SYNC] = NULL;
++ }
++}
++
++/*
++ * Update the entity prio values; note that the new values will not
++ * be used until the next (re)activation.
++ */
++static void bfq_init_prio_data(struct bfq_queue *bfqq, struct bfq_io_cq *bic)
++{
++ struct task_struct *tsk = current;
++ int ioprio_class;
++
++ if (!bfq_bfqq_prio_changed(bfqq))
++ return;
++
++ ioprio_class = IOPRIO_PRIO_CLASS(bic->ioprio);
++ switch (ioprio_class) {
++ default:
++ dev_err(bfqq->bfqd->queue->backing_dev_info.dev,
++ "bfq: bad prio class %d\n", ioprio_class);
++ case IOPRIO_CLASS_NONE:
++ /*
++ * No prio set, inherit CPU scheduling settings.
++ */
++ bfqq->entity.new_ioprio = task_nice_ioprio(tsk);
++ bfqq->entity.new_ioprio_class = task_nice_ioclass(tsk);
++ break;
++ case IOPRIO_CLASS_RT:
++ bfqq->entity.new_ioprio = IOPRIO_PRIO_DATA(bic->ioprio);
++ bfqq->entity.new_ioprio_class = IOPRIO_CLASS_RT;
++ break;
++ case IOPRIO_CLASS_BE:
++ bfqq->entity.new_ioprio = IOPRIO_PRIO_DATA(bic->ioprio);
++ bfqq->entity.new_ioprio_class = IOPRIO_CLASS_BE;
++ break;
++ case IOPRIO_CLASS_IDLE:
++ bfqq->entity.new_ioprio_class = IOPRIO_CLASS_IDLE;
++ bfqq->entity.new_ioprio = 7;
++ bfq_clear_bfqq_idle_window(bfqq);
++ break;
++ }
++
++ if (bfqq->entity.new_ioprio < 0 ||
++ bfqq->entity.new_ioprio >= IOPRIO_BE_NR) {
++ printk(KERN_CRIT "bfq_init_prio_data: new_ioprio %d\n",
++ bfqq->entity.new_ioprio);
++ BUG();
++ }
++
++ bfqq->entity.ioprio_changed = 1;
++
++ bfq_clear_bfqq_prio_changed(bfqq);
++}
++
++static void bfq_changed_ioprio(struct bfq_io_cq *bic)
++{
++ struct bfq_data *bfqd;
++ struct bfq_queue *bfqq, *new_bfqq;
++ struct bfq_group *bfqg;
++ unsigned long uninitialized_var(flags);
++ int ioprio = bic->icq.ioc->ioprio;
++
++ bfqd = bfq_get_bfqd_locked(&(bic->icq.q->elevator->elevator_data),
++ &flags);
++ /*
++ * This condition may trigger on a newly created bic, be sure to
++ * drop the lock before returning.
++ */
++ if (unlikely(bfqd == NULL) || likely(bic->ioprio == ioprio))
++ goto out;
++
++ bfqq = bic->bfqq[BLK_RW_ASYNC];
++ if (bfqq != NULL) {
++ bfqg = container_of(bfqq->entity.sched_data, struct bfq_group,
++ sched_data);
++ new_bfqq = bfq_get_queue(bfqd, bfqg, BLK_RW_ASYNC, bic,
++ GFP_ATOMIC);
++ if (new_bfqq != NULL) {
++ bic->bfqq[BLK_RW_ASYNC] = new_bfqq;
++ bfq_log_bfqq(bfqd, bfqq,
++ "changed_ioprio: bfqq %p %d",
++ bfqq, atomic_read(&bfqq->ref));
++ bfq_put_queue(bfqq);
++ }
++ }
++
++ bfqq = bic->bfqq[BLK_RW_SYNC];
++ if (bfqq != NULL)
++ bfq_mark_bfqq_prio_changed(bfqq);
++
++ bic->ioprio = ioprio;
++
++out:
++ bfq_put_bfqd_unlock(bfqd, &flags);
++}
++
++static void bfq_init_bfqq(struct bfq_data *bfqd, struct bfq_queue *bfqq,
++ pid_t pid, int is_sync)
++{
++ RB_CLEAR_NODE(&bfqq->entity.rb_node);
++ INIT_LIST_HEAD(&bfqq->fifo);
++ INIT_HLIST_NODE(&bfqq->burst_list_node);
++
++ atomic_set(&bfqq->ref, 0);
++ bfqq->bfqd = bfqd;
++
++ bfq_mark_bfqq_prio_changed(bfqq);
++
++ if (is_sync) {
++ if (!bfq_class_idle(bfqq))
++ bfq_mark_bfqq_idle_window(bfqq);
++ bfq_mark_bfqq_sync(bfqq);
++ }
++ bfq_mark_bfqq_IO_bound(bfqq);
++
++ /* Tentative initial value to trade off between thr and lat */
++ bfqq->max_budget = (2 * bfq_max_budget(bfqd)) / 3;
++ bfqq->pid = pid;
++
++ bfqq->wr_coeff = 1;
++ bfqq->last_wr_start_finish = 0;
++ /*
++ * Set to the value for which bfqq will not be deemed as
++ * soft rt when it becomes backlogged.
++ */
++ bfqq->soft_rt_next_start = bfq_infinity_from_now(jiffies);
++}
++
++static struct bfq_queue *bfq_find_alloc_queue(struct bfq_data *bfqd,
++ struct bfq_group *bfqg,
++ int is_sync,
++ struct bfq_io_cq *bic,
++ gfp_t gfp_mask)
++{
++ struct bfq_queue *bfqq, *new_bfqq = NULL;
++
++retry:
++ /* bic always exists here */
++ bfqq = bic_to_bfqq(bic, is_sync);
++
++ /*
++ * Always try a new alloc if we fall back to the OOM bfqq
++ * originally, since it should just be a temporary situation.
++ */
++ if (bfqq == NULL || bfqq == &bfqd->oom_bfqq) {
++ bfqq = NULL;
++ if (new_bfqq != NULL) {
++ bfqq = new_bfqq;
++ new_bfqq = NULL;
++ } else if (gfp_mask & __GFP_WAIT) {
++ spin_unlock_irq(bfqd->queue->queue_lock);
++ new_bfqq = kmem_cache_alloc_node(bfq_pool,
++ gfp_mask | __GFP_ZERO,
++ bfqd->queue->node);
++ spin_lock_irq(bfqd->queue->queue_lock);
++ if (new_bfqq != NULL)
++ goto retry;
++ } else {
++ bfqq = kmem_cache_alloc_node(bfq_pool,
++ gfp_mask | __GFP_ZERO,
++ bfqd->queue->node);
++ }
++
++ if (bfqq != NULL) {
++ bfq_init_bfqq(bfqd, bfqq, current->pid, is_sync);
++ bfq_init_prio_data(bfqq, bic);
++ bfq_init_entity(&bfqq->entity, bfqg);
++ bfq_log_bfqq(bfqd, bfqq, "allocated");
++ } else {
++ bfqq = &bfqd->oom_bfqq;
++ bfq_log_bfqq(bfqd, bfqq, "using oom bfqq");
++ }
++ }
++
++ if (new_bfqq != NULL)
++ kmem_cache_free(bfq_pool, new_bfqq);
++
++ return bfqq;
++}
++
++static struct bfq_queue **bfq_async_queue_prio(struct bfq_data *bfqd,
++ struct bfq_group *bfqg,
++ int ioprio_class, int ioprio)
++{
++ switch (ioprio_class) {
++ case IOPRIO_CLASS_RT:
++ return &bfqg->async_bfqq[0][ioprio];
++ case IOPRIO_CLASS_NONE:
++ ioprio = IOPRIO_NORM;
++ /* fall through */
++ case IOPRIO_CLASS_BE:
++ return &bfqg->async_bfqq[1][ioprio];
++ case IOPRIO_CLASS_IDLE:
++ return &bfqg->async_idle_bfqq;
++ default:
++ BUG();
++ }
++}
++
++static struct bfq_queue *bfq_get_queue(struct bfq_data *bfqd,
++ struct bfq_group *bfqg, int is_sync,
++ struct bfq_io_cq *bic, gfp_t gfp_mask)
++{
++ const int ioprio = IOPRIO_PRIO_DATA(bic->ioprio);
++ const int ioprio_class = IOPRIO_PRIO_CLASS(bic->ioprio);
++ struct bfq_queue **async_bfqq = NULL;
++ struct bfq_queue *bfqq = NULL;
++
++ if (!is_sync) {
++ async_bfqq = bfq_async_queue_prio(bfqd, bfqg, ioprio_class,
++ ioprio);
++ bfqq = *async_bfqq;
++ }
++
++ if (bfqq == NULL)
++ bfqq = bfq_find_alloc_queue(bfqd, bfqg, is_sync, bic, gfp_mask);
++
++ /*
++ * Pin the queue now that it's allocated, scheduler exit will
++ * prune it.
++ */
++ if (!is_sync && *async_bfqq == NULL) {
++ atomic_inc(&bfqq->ref);
++ bfq_log_bfqq(bfqd, bfqq, "get_queue, bfqq not in async: %p, %d",
++ bfqq, atomic_read(&bfqq->ref));
++ *async_bfqq = bfqq;
++ }
++
++ atomic_inc(&bfqq->ref);
++ bfq_log_bfqq(bfqd, bfqq, "get_queue, at end: %p, %d", bfqq,
++ atomic_read(&bfqq->ref));
++ return bfqq;
++}
++
++static void bfq_update_io_thinktime(struct bfq_data *bfqd,
++ struct bfq_io_cq *bic)
++{
++ unsigned long elapsed = jiffies - bic->ttime.last_end_request;
++ unsigned long ttime = min(elapsed, 2UL * bfqd->bfq_slice_idle);
++
++ bic->ttime.ttime_samples = (7*bic->ttime.ttime_samples + 256) / 8;
++ bic->ttime.ttime_total = (7*bic->ttime.ttime_total + 256*ttime) / 8;
++ bic->ttime.ttime_mean = (bic->ttime.ttime_total + 128) /
++ bic->ttime.ttime_samples;
++}
++
++static void bfq_update_io_seektime(struct bfq_data *bfqd,
++ struct bfq_queue *bfqq,
++ struct request *rq)
++{
++ sector_t sdist;
++ u64 total;
++
++ if (bfqq->last_request_pos < blk_rq_pos(rq))
++ sdist = blk_rq_pos(rq) - bfqq->last_request_pos;
++ else
++ sdist = bfqq->last_request_pos - blk_rq_pos(rq);
++
++ /*
++ * Don't allow the seek distance to get too large from the
++ * odd fragment, pagein, etc.
++ */
++ if (bfqq->seek_samples == 0) /* first request, not really a seek */
++ sdist = 0;
++ else if (bfqq->seek_samples <= 60) /* second & third seek */
++ sdist = min(sdist, (bfqq->seek_mean * 4) + 2*1024*1024);
++ else
++ sdist = min(sdist, (bfqq->seek_mean * 4) + 2*1024*64);
++
++ bfqq->seek_samples = (7*bfqq->seek_samples + 256) / 8;
++ bfqq->seek_total = (7*bfqq->seek_total + (u64)256*sdist) / 8;
++ total = bfqq->seek_total + (bfqq->seek_samples/2);
++ do_div(total, bfqq->seek_samples);
++ bfqq->seek_mean = (sector_t)total;
++
++ bfq_log_bfqq(bfqd, bfqq, "dist=%llu mean=%llu", (u64)sdist,
++ (u64)bfqq->seek_mean);
++}
++
++/*
++ * Disable idle window if the process thinks too long or seeks so much that
++ * it doesn't matter.
++ */
++static void bfq_update_idle_window(struct bfq_data *bfqd,
++ struct bfq_queue *bfqq,
++ struct bfq_io_cq *bic)
++{
++ int enable_idle;
++
++ /* Don't idle for async or idle io prio class. */
++ if (!bfq_bfqq_sync(bfqq) || bfq_class_idle(bfqq))
++ return;
++
++ /* Idle window just restored, statistics are meaningless. */
++ if (bfq_bfqq_just_split(bfqq))
++ return;
++
++ enable_idle = bfq_bfqq_idle_window(bfqq);
++
++ if (atomic_read(&bic->icq.ioc->active_ref) == 0 ||
++ bfqd->bfq_slice_idle == 0 ||
++ (bfqd->hw_tag && BFQQ_SEEKY(bfqq) &&
++ bfqq->wr_coeff == 1))
++ enable_idle = 0;
++ else if (bfq_sample_valid(bic->ttime.ttime_samples)) {
++ if (bic->ttime.ttime_mean > bfqd->bfq_slice_idle &&
++ bfqq->wr_coeff == 1)
++ enable_idle = 0;
++ else
++ enable_idle = 1;
++ }
++ bfq_log_bfqq(bfqd, bfqq, "update_idle_window: enable_idle %d",
++ enable_idle);
++
++ if (enable_idle)
++ bfq_mark_bfqq_idle_window(bfqq);
++ else
++ bfq_clear_bfqq_idle_window(bfqq);
++}
++
++/*
++ * Called when a new fs request (rq) is added to bfqq. Check if there's
++ * something we should do about it.
++ */
++static void bfq_rq_enqueued(struct bfq_data *bfqd, struct bfq_queue *bfqq,
++ struct request *rq)
++{
++ struct bfq_io_cq *bic = RQ_BIC(rq);
++
++ if (rq->cmd_flags & REQ_META)
++ bfqq->meta_pending++;
++
++ bfq_update_io_thinktime(bfqd, bic);
++ bfq_update_io_seektime(bfqd, bfqq, rq);
++ if (!BFQQ_SEEKY(bfqq) && bfq_bfqq_constantly_seeky(bfqq)) {
++ bfq_clear_bfqq_constantly_seeky(bfqq);
++ if (!blk_queue_nonrot(bfqd->queue)) {
++ BUG_ON(!bfqd->const_seeky_busy_in_flight_queues);
++ bfqd->const_seeky_busy_in_flight_queues--;
++ }
++ }
++ if (bfqq->entity.service > bfq_max_budget(bfqd) / 8 ||
++ !BFQQ_SEEKY(bfqq))
++ bfq_update_idle_window(bfqd, bfqq, bic);
++ bfq_clear_bfqq_just_split(bfqq);
++
++ bfq_log_bfqq(bfqd, bfqq,
++ "rq_enqueued: idle_window=%d (seeky %d, mean %llu)",
++ bfq_bfqq_idle_window(bfqq), BFQQ_SEEKY(bfqq),
++ (long long unsigned)bfqq->seek_mean);
++
++ bfqq->last_request_pos = blk_rq_pos(rq) + blk_rq_sectors(rq);
++
++ if (bfqq == bfqd->in_service_queue && bfq_bfqq_wait_request(bfqq)) {
++ int small_req = bfqq->queued[rq_is_sync(rq)] == 1 &&
++ blk_rq_sectors(rq) < 32;
++ int budget_timeout = bfq_bfqq_budget_timeout(bfqq);
++
++ /*
++ * There is just this request queued: if the request
++ * is small and the queue is not to be expired, then
++ * just exit.
++ *
++ * In this way, if the disk is being idled to wait for
++ * a new request from the in-service queue, we avoid
++ * unplugging the device and committing the disk to serve
++ * just a small request. On the contrary, we wait for
++ * the block layer to decide when to unplug the device:
++ * hopefully, new requests will be merged to this one
++ * quickly, then the device will be unplugged and
++ * larger requests will be dispatched.
++ */
++ if (small_req && !budget_timeout)
++ return;
++
++ /*
++ * A large enough request arrived, or the queue is to
++ * be expired: in both cases disk idling is to be
++ * stopped, so clear wait_request flag and reset
++ * timer.
++ */
++ bfq_clear_bfqq_wait_request(bfqq);
++ del_timer(&bfqd->idle_slice_timer);
++
++ /*
++ * The queue is not empty, because a new request just
++ * arrived. Hence we can safely expire the queue, in
++ * case of budget timeout, without risking that the
++ * timestamps of the queue are not updated correctly.
++ * See [1] for more details.
++ */
++ if (budget_timeout)
++ bfq_bfqq_expire(bfqd, bfqq, 0, BFQ_BFQQ_BUDGET_TIMEOUT);
++
++ /*
++ * Let the request rip immediately, or let a new queue be
++ * selected if bfqq has just been expired.
++ */
++ __blk_run_queue(bfqd->queue);
++ }
++}
++
++static void bfq_insert_request(struct request_queue *q, struct request *rq)
++{
++ struct bfq_data *bfqd = q->elevator->elevator_data;
++ struct bfq_queue *bfqq = RQ_BFQQ(rq), *new_bfqq;
++
++ assert_spin_locked(bfqd->queue->queue_lock);
++
++ /*
++ * An unplug may trigger a requeue of a request from the device
++ * driver: make sure we are in process context while trying to
++ * merge two bfq_queues.
++ */
++ if (!in_interrupt()) {
++ new_bfqq = bfq_setup_cooperator(bfqd, bfqq, rq, true);
++ if (new_bfqq != NULL) {
++ if (bic_to_bfqq(RQ_BIC(rq), 1) != bfqq)
++ new_bfqq = bic_to_bfqq(RQ_BIC(rq), 1);
++ /*
++ * Release the request's reference to the old bfqq
++ * and make sure one is taken to the shared queue.
++ */
++ new_bfqq->allocated[rq_data_dir(rq)]++;
++ bfqq->allocated[rq_data_dir(rq)]--;
++ atomic_inc(&new_bfqq->ref);
++ bfq_put_queue(bfqq);
++ if (bic_to_bfqq(RQ_BIC(rq), 1) == bfqq)
++ bfq_merge_bfqqs(bfqd, RQ_BIC(rq),
++ bfqq, new_bfqq);
++ rq->elv.priv[1] = new_bfqq;
++ bfqq = new_bfqq;
++ } else
++ bfq_bfqq_increase_failed_cooperations(bfqq);
++ }
++
++ bfq_init_prio_data(bfqq, RQ_BIC(rq));
++
++ bfq_add_request(rq);
++
++ /*
++ * Here a newly-created bfq_queue has already started a weight-raising
++ * period: clear raising_time_left to prevent bfq_bfqq_save_state()
++ * from assigning it a full weight-raising period. See the detailed
++ * comments about this field in bfq_init_icq().
++ */
++ if (bfqq->bic != NULL)
++ bfqq->bic->wr_time_left = 0;
++ rq->fifo_time = jiffies + bfqd->bfq_fifo_expire[rq_is_sync(rq)];
++ list_add_tail(&rq->queuelist, &bfqq->fifo);
++
++ bfq_rq_enqueued(bfqd, bfqq, rq);
++}
++
++static void bfq_update_hw_tag(struct bfq_data *bfqd)
++{
++ bfqd->max_rq_in_driver = max(bfqd->max_rq_in_driver,
++ bfqd->rq_in_driver);
++
++ if (bfqd->hw_tag == 1)
++ return;
++
++ /*
++ * This sample is valid if the number of outstanding requests
++ * is large enough to allow a queueing behavior. Note that the
++ * sum is not exact, as it's not taking into account deactivated
++ * requests.
++ */
++ if (bfqd->rq_in_driver + bfqd->queued < BFQ_HW_QUEUE_THRESHOLD)
++ return;
++
++ if (bfqd->hw_tag_samples++ < BFQ_HW_QUEUE_SAMPLES)
++ return;
++
++ bfqd->hw_tag = bfqd->max_rq_in_driver > BFQ_HW_QUEUE_THRESHOLD;
++ bfqd->max_rq_in_driver = 0;
++ bfqd->hw_tag_samples = 0;
++}
++
++static void bfq_completed_request(struct request_queue *q, struct request *rq)
++{
++ struct bfq_queue *bfqq = RQ_BFQQ(rq);
++ struct bfq_data *bfqd = bfqq->bfqd;
++ bool sync = bfq_bfqq_sync(bfqq);
++
++ bfq_log_bfqq(bfqd, bfqq, "completed one req with %u sects left (%d)",
++ blk_rq_sectors(rq), sync);
++
++ bfq_update_hw_tag(bfqd);
++
++ BUG_ON(!bfqd->rq_in_driver);
++ BUG_ON(!bfqq->dispatched);
++ bfqd->rq_in_driver--;
++ bfqq->dispatched--;
++
++ if (!bfqq->dispatched && !bfq_bfqq_busy(bfqq)) {
++ bfq_weights_tree_remove(bfqd, &bfqq->entity,
++ &bfqd->queue_weights_tree);
++ if (!blk_queue_nonrot(bfqd->queue)) {
++ BUG_ON(!bfqd->busy_in_flight_queues);
++ bfqd->busy_in_flight_queues--;
++ if (bfq_bfqq_constantly_seeky(bfqq)) {
++ BUG_ON(!bfqd->
++ const_seeky_busy_in_flight_queues);
++ bfqd->const_seeky_busy_in_flight_queues--;
++ }
++ }
++ }
++
++ if (sync) {
++ bfqd->sync_flight--;
++ RQ_BIC(rq)->ttime.last_end_request = jiffies;
++ }
++
++ /*
++ * If we are waiting to discover whether the request pattern of the
++ * task associated with the queue is actually isochronous, and
++ * both requisites for this condition to hold are satisfied, then
++ * compute soft_rt_next_start (see the comments to the function
++ * bfq_bfqq_softrt_next_start()).
++ */
++ if (bfq_bfqq_softrt_update(bfqq) && bfqq->dispatched == 0 &&
++ RB_EMPTY_ROOT(&bfqq->sort_list))
++ bfqq->soft_rt_next_start =
++ bfq_bfqq_softrt_next_start(bfqd, bfqq);
++
++ /*
++ * If this is the in-service queue, check if it needs to be expired,
++ * or if we want to idle in case it has no pending requests.
++ */
++ if (bfqd->in_service_queue == bfqq) {
++ if (bfq_bfqq_budget_new(bfqq))
++ bfq_set_budget_timeout(bfqd);
++
++ if (bfq_bfqq_must_idle(bfqq)) {
++ bfq_arm_slice_timer(bfqd);
++ goto out;
++ } else if (bfq_may_expire_for_budg_timeout(bfqq))
++ bfq_bfqq_expire(bfqd, bfqq, 0, BFQ_BFQQ_BUDGET_TIMEOUT);
++ else if (RB_EMPTY_ROOT(&bfqq->sort_list) &&
++ (bfqq->dispatched == 0 ||
++ !bfq_bfqq_must_not_expire(bfqq)))
++ bfq_bfqq_expire(bfqd, bfqq, 0,
++ BFQ_BFQQ_NO_MORE_REQUESTS);
++ }
++
++ if (!bfqd->rq_in_driver)
++ bfq_schedule_dispatch(bfqd);
++
++out:
++ return;
++}
++
++static inline int __bfq_may_queue(struct bfq_queue *bfqq)
++{
++ if (bfq_bfqq_wait_request(bfqq) && bfq_bfqq_must_alloc(bfqq)) {
++ bfq_clear_bfqq_must_alloc(bfqq);
++ return ELV_MQUEUE_MUST;
++ }
++
++ return ELV_MQUEUE_MAY;
++}
++
++static int bfq_may_queue(struct request_queue *q, int rw)
++{
++ struct bfq_data *bfqd = q->elevator->elevator_data;
++ struct task_struct *tsk = current;
++ struct bfq_io_cq *bic;
++ struct bfq_queue *bfqq;
++
++ /*
++ * Don't force setup of a queue from here, as a call to may_queue
++ * does not necessarily imply that a request actually will be
++ * queued. So just lookup a possibly existing queue, or return
++ * 'may queue' if that fails.
++ */
++ bic = bfq_bic_lookup(bfqd, tsk->io_context);
++ if (bic == NULL)
++ return ELV_MQUEUE_MAY;
++
++ bfqq = bic_to_bfqq(bic, rw_is_sync(rw));
++ if (bfqq != NULL) {
++ bfq_init_prio_data(bfqq, bic);
++
++ return __bfq_may_queue(bfqq);
++ }
++
++ return ELV_MQUEUE_MAY;
++}
++
++/*
++ * Queue lock held here.
++ */
++static void bfq_put_request(struct request *rq)
++{
++ struct bfq_queue *bfqq = RQ_BFQQ(rq);
++
++ if (bfqq != NULL) {
++ const int rw = rq_data_dir(rq);
++
++ BUG_ON(!bfqq->allocated[rw]);
++ bfqq->allocated[rw]--;
++
++ rq->elv.priv[0] = NULL;
++ rq->elv.priv[1] = NULL;
++
++ bfq_log_bfqq(bfqq->bfqd, bfqq, "put_request %p, %d",
++ bfqq, atomic_read(&bfqq->ref));
++ bfq_put_queue(bfqq);
++ }
++}
++
++/*
++ * Returns NULL if a new bfqq should be allocated, or the old bfqq if this
++ * was the last process referring to said bfqq.
++ */
++static struct bfq_queue *
++bfq_split_bfqq(struct bfq_io_cq *bic, struct bfq_queue *bfqq)
++{
++ bfq_log_bfqq(bfqq->bfqd, bfqq, "splitting queue");
++
++ put_io_context(bic->icq.ioc);
++
++ if (bfqq_process_refs(bfqq) == 1) {
++ bfqq->pid = current->pid;
++ bfq_clear_bfqq_coop(bfqq);
++ bfq_clear_bfqq_split_coop(bfqq);
++ return bfqq;
++ }
++
++ bic_set_bfqq(bic, NULL, 1);
++
++ bfq_put_cooperator(bfqq);
++
++ bfq_put_queue(bfqq);
++ return NULL;
++}
++
++/*
++ * Allocate bfq data structures associated with this request.
++ */
++static int bfq_set_request(struct request_queue *q, struct request *rq,
++ struct bio *bio, gfp_t gfp_mask)
++{
++ struct bfq_data *bfqd = q->elevator->elevator_data;
++ struct bfq_io_cq *bic = icq_to_bic(rq->elv.icq);
++ const int rw = rq_data_dir(rq);
++ const int is_sync = rq_is_sync(rq);
++ struct bfq_queue *bfqq;
++ struct bfq_group *bfqg;
++ unsigned long flags;
++ bool split = false;
++
++ might_sleep_if(gfp_mask & __GFP_WAIT);
++
++ bfq_changed_ioprio(bic);
++
++ spin_lock_irqsave(q->queue_lock, flags);
++
++ if (bic == NULL)
++ goto queue_fail;
++
++ bfqg = bfq_bic_update_cgroup(bic);
++
++new_queue:
++ bfqq = bic_to_bfqq(bic, is_sync);
++ if (bfqq == NULL || bfqq == &bfqd->oom_bfqq) {
++ bfqq = bfq_get_queue(bfqd, bfqg, is_sync, bic, gfp_mask);
++ bic_set_bfqq(bic, bfqq, is_sync);
++ if (split && is_sync) {
++ if ((bic->was_in_burst_list && bfqd->large_burst) ||
++ bic->saved_in_large_burst)
++ bfq_mark_bfqq_in_large_burst(bfqq);
++ else {
++ bfq_clear_bfqq_in_large_burst(bfqq);
++ if (bic->was_in_burst_list)
++ hlist_add_head(&bfqq->burst_list_node,
++ &bfqd->burst_list);
++ }
++ }
++ } else {
++ /* If the queue was seeky for too long, break it apart. */
++ if (bfq_bfqq_coop(bfqq) && bfq_bfqq_split_coop(bfqq)) {
++ bfq_log_bfqq(bfqd, bfqq, "breaking apart bfqq");
++ bfqq = bfq_split_bfqq(bic, bfqq);
++ split = true;
++ if (!bfqq)
++ goto new_queue;
++ }
++ }
++
++ bfqq->allocated[rw]++;
++ atomic_inc(&bfqq->ref);
++ bfq_log_bfqq(bfqd, bfqq, "set_request: bfqq %p, %d", bfqq,
++ atomic_read(&bfqq->ref));
++
++ rq->elv.priv[0] = bic;
++ rq->elv.priv[1] = bfqq;
++
++ /*
++ * If a bfq_queue has only one process reference, it is owned
++ * by only one bfq_io_cq: we can set the bic field of the
++ * bfq_queue to the address of that structure. Also, if the
++ * queue has just been split, mark a flag so that the
++ * information is available to the other scheduler hooks.
++ */
++ if (likely(bfqq != &bfqd->oom_bfqq) && bfqq_process_refs(bfqq) == 1) {
++ bfqq->bic = bic;
++ if (split) {
++ bfq_mark_bfqq_just_split(bfqq);
++ /*
++ * If the queue has just been split from a shared
++ * queue, restore the idle window and the possible
++ * weight raising period.
++ */
++ bfq_bfqq_resume_state(bfqq, bic);
++ }
++ }
++
++ spin_unlock_irqrestore(q->queue_lock, flags);
++
++ return 0;
++
++queue_fail:
++ bfq_schedule_dispatch(bfqd);
++ spin_unlock_irqrestore(q->queue_lock, flags);
++
++ return 1;
++}
++
++static void bfq_kick_queue(struct work_struct *work)
++{
++ struct bfq_data *bfqd =
++ container_of(work, struct bfq_data, unplug_work);
++ struct request_queue *q = bfqd->queue;
++
++ spin_lock_irq(q->queue_lock);
++ __blk_run_queue(q);
++ spin_unlock_irq(q->queue_lock);
++}
++
++/*
++ * Handler of the expiration of the timer running if the in-service queue
++ * is idling inside its time slice.
++ */
++static void bfq_idle_slice_timer(unsigned long data)
++{
++ struct bfq_data *bfqd = (struct bfq_data *)data;
++ struct bfq_queue *bfqq;
++ unsigned long flags;
++ enum bfqq_expiration reason;
++
++ spin_lock_irqsave(bfqd->queue->queue_lock, flags);
++
++ bfqq = bfqd->in_service_queue;
++ /*
++ * Theoretical race here: the in-service queue can be NULL or
++ * different from the queue that was idling if the timer handler
++ * spins on the queue_lock and a new request arrives for the
++ * current queue and there is a full dispatch cycle that changes
++ * the in-service queue. This can hardly happen, but in the worst
++ * case we just expire a queue too early.
++ */
++ if (bfqq != NULL) {
++ bfq_log_bfqq(bfqd, bfqq, "slice_timer expired");
++ if (bfq_bfqq_budget_timeout(bfqq))
++ /*
++ * Also here the queue can be safely expired
++ * for budget timeout without wasting
++ * guarantees
++ */
++ reason = BFQ_BFQQ_BUDGET_TIMEOUT;
++ else if (bfqq->queued[0] == 0 && bfqq->queued[1] == 0)
++ /*
++ * The queue may not be empty upon timer expiration,
++ * because we may not disable the timer when the
++ * first request of the in-service queue arrives
++ * during disk idling.
++ */
++ reason = BFQ_BFQQ_TOO_IDLE;
++ else
++ goto schedule_dispatch;
++
++ bfq_bfqq_expire(bfqd, bfqq, 1, reason);
++ }
++
++schedule_dispatch:
++ bfq_schedule_dispatch(bfqd);
++
++ spin_unlock_irqrestore(bfqd->queue->queue_lock, flags);
++}
++
++static void bfq_shutdown_timer_wq(struct bfq_data *bfqd)
++{
++ del_timer_sync(&bfqd->idle_slice_timer);
++ cancel_work_sync(&bfqd->unplug_work);
++}
++
++static inline void __bfq_put_async_bfqq(struct bfq_data *bfqd,
++ struct bfq_queue **bfqq_ptr)
++{
++ struct bfq_group *root_group = bfqd->root_group;
++ struct bfq_queue *bfqq = *bfqq_ptr;
++
++ bfq_log(bfqd, "put_async_bfqq: %p", bfqq);
++ if (bfqq != NULL) {
++ bfq_bfqq_move(bfqd, bfqq, &bfqq->entity, root_group);
++ bfq_log_bfqq(bfqd, bfqq, "put_async_bfqq: putting %p, %d",
++ bfqq, atomic_read(&bfqq->ref));
++ bfq_put_queue(bfqq);
++ *bfqq_ptr = NULL;
++ }
++}
++
++/*
++ * Release all the bfqg references to its async queues. If we are
++ * deallocating the group these queues may still contain requests, so
++ * we reparent them to the root cgroup (i.e., the only one that will
++ * exist for sure until all the requests on a device are gone).
++ */
++static void bfq_put_async_queues(struct bfq_data *bfqd, struct bfq_group *bfqg)
++{
++ int i, j;
++
++ for (i = 0; i < 2; i++)
++ for (j = 0; j < IOPRIO_BE_NR; j++)
++ __bfq_put_async_bfqq(bfqd, &bfqg->async_bfqq[i][j]);
++
++ __bfq_put_async_bfqq(bfqd, &bfqg->async_idle_bfqq);
++}
++
++static void bfq_exit_queue(struct elevator_queue *e)
++{
++ struct bfq_data *bfqd = e->elevator_data;
++ struct request_queue *q = bfqd->queue;
++ struct bfq_queue *bfqq, *n;
++
++ bfq_shutdown_timer_wq(bfqd);
++
++ spin_lock_irq(q->queue_lock);
++
++ BUG_ON(bfqd->in_service_queue != NULL);
++ list_for_each_entry_safe(bfqq, n, &bfqd->idle_list, bfqq_list)
++ bfq_deactivate_bfqq(bfqd, bfqq, 0);
++
++ bfq_disconnect_groups(bfqd);
++ spin_unlock_irq(q->queue_lock);
++
++ bfq_shutdown_timer_wq(bfqd);
++
++ synchronize_rcu();
++
++ BUG_ON(timer_pending(&bfqd->idle_slice_timer));
++
++ bfq_free_root_group(bfqd);
++ kfree(bfqd);
++}
++
++static int bfq_init_queue(struct request_queue *q, struct elevator_type *e)
++{
++ struct bfq_group *bfqg;
++ struct bfq_data *bfqd;
++ struct elevator_queue *eq;
++
++ eq = elevator_alloc(q, e);
++ if (eq == NULL)
++ return -ENOMEM;
++
++ bfqd = kzalloc_node(sizeof(*bfqd), GFP_KERNEL, q->node);
++ if (bfqd == NULL) {
++ kobject_put(&eq->kobj);
++ return -ENOMEM;
++ }
++ eq->elevator_data = bfqd;
++
++ /*
++ * Our fallback bfqq if bfq_find_alloc_queue() runs into OOM issues.
++ * Grab a permanent reference to it, so that the normal code flow
++ * will not attempt to free it.
++ */
++ bfq_init_bfqq(bfqd, &bfqd->oom_bfqq, 1, 0);
++ atomic_inc(&bfqd->oom_bfqq.ref);
++ bfqd->oom_bfqq.entity.new_ioprio = BFQ_DEFAULT_QUEUE_IOPRIO;
++ bfqd->oom_bfqq.entity.new_ioprio_class = IOPRIO_CLASS_BE;
++ /*
++ * Trigger weight initialization, according to ioprio, at the
++ * oom_bfqq's first activation. The oom_bfqq's ioprio and ioprio
++ * class won't be changed any more.
++ */
++ bfqd->oom_bfqq.entity.ioprio_changed = 1;
++
++ bfqd->queue = q;
++
++ spin_lock_irq(q->queue_lock);
++ q->elevator = eq;
++ spin_unlock_irq(q->queue_lock);
++
++ bfqg = bfq_alloc_root_group(bfqd, q->node);
++ if (bfqg == NULL) {
++ kfree(bfqd);
++ kobject_put(&eq->kobj);
++ return -ENOMEM;
++ }
++
++ bfqd->root_group = bfqg;
++ bfq_init_entity(&bfqd->oom_bfqq.entity, bfqd->root_group);
++#ifdef CONFIG_CGROUP_BFQIO
++ bfqd->active_numerous_groups = 0;
++#endif
++
++ init_timer(&bfqd->idle_slice_timer);
++ bfqd->idle_slice_timer.function = bfq_idle_slice_timer;
++ bfqd->idle_slice_timer.data = (unsigned long)bfqd;
++
++ bfqd->rq_pos_tree = RB_ROOT;
++ bfqd->queue_weights_tree = RB_ROOT;
++ bfqd->group_weights_tree = RB_ROOT;
++
++ INIT_WORK(&bfqd->unplug_work, bfq_kick_queue);
++
++ INIT_LIST_HEAD(&bfqd->active_list);
++ INIT_LIST_HEAD(&bfqd->idle_list);
++ INIT_HLIST_HEAD(&bfqd->burst_list);
++
++ bfqd->hw_tag = -1;
++
++ bfqd->bfq_max_budget = bfq_default_max_budget;
++
++ bfqd->bfq_quantum = bfq_quantum;
++ bfqd->bfq_fifo_expire[0] = bfq_fifo_expire[0];
++ bfqd->bfq_fifo_expire[1] = bfq_fifo_expire[1];
++ bfqd->bfq_back_max = bfq_back_max;
++ bfqd->bfq_back_penalty = bfq_back_penalty;
++ bfqd->bfq_slice_idle = bfq_slice_idle;
++ bfqd->bfq_class_idle_last_service = 0;
++ bfqd->bfq_max_budget_async_rq = bfq_max_budget_async_rq;
++ bfqd->bfq_timeout[BLK_RW_ASYNC] = bfq_timeout_async;
++ bfqd->bfq_timeout[BLK_RW_SYNC] = bfq_timeout_sync;
++
++ bfqd->bfq_coop_thresh = 2;
++ bfqd->bfq_failed_cooperations = 7000;
++ bfqd->bfq_requests_within_timer = 120;
++
++ bfqd->bfq_large_burst_thresh = 11;
++ bfqd->bfq_burst_interval = msecs_to_jiffies(500);
++
++ bfqd->low_latency = true;
++
++ bfqd->bfq_wr_coeff = 20;
++ bfqd->bfq_wr_rt_max_time = msecs_to_jiffies(300);
++ bfqd->bfq_wr_max_time = 0;
++ bfqd->bfq_wr_min_idle_time = msecs_to_jiffies(2000);
++ bfqd->bfq_wr_min_inter_arr_async = msecs_to_jiffies(500);
++ bfqd->bfq_wr_max_softrt_rate = 7000; /*
++ * Approximate rate required
++ * to playback or record a
++ * high-definition compressed
++ * video.
++ */
++ bfqd->wr_busy_queues = 0;
++ bfqd->busy_in_flight_queues = 0;
++ bfqd->const_seeky_busy_in_flight_queues = 0;
++
++ /*
++ * Begin by assuming, optimistically, that the device peak rate is
++ * equal to the highest reference rate.
++ */
++ bfqd->RT_prod = R_fast[blk_queue_nonrot(bfqd->queue)] *
++ T_fast[blk_queue_nonrot(bfqd->queue)];
++ bfqd->peak_rate = R_fast[blk_queue_nonrot(bfqd->queue)];
++ bfqd->device_speed = BFQ_BFQD_FAST;
++
++ return 0;
++}
++
++static void bfq_slab_kill(void)
++{
++ if (bfq_pool != NULL)
++ kmem_cache_destroy(bfq_pool);
++}
++
++static int __init bfq_slab_setup(void)
++{
++ bfq_pool = KMEM_CACHE(bfq_queue, 0);
++ if (bfq_pool == NULL)
++ return -ENOMEM;
++ return 0;
++}
++
++static ssize_t bfq_var_show(unsigned int var, char *page)
++{
++ return sprintf(page, "%d\n", var);
++}
++
++static ssize_t bfq_var_store(unsigned long *var, const char *page,
++ size_t count)
++{
++ unsigned long new_val;
++ int ret = kstrtoul(page, 10, &new_val);
++
++ if (ret == 0)
++ *var = new_val;
++
++ return count;
++}
++
++static ssize_t bfq_wr_max_time_show(struct elevator_queue *e, char *page)
++{
++ struct bfq_data *bfqd = e->elevator_data;
++ return sprintf(page, "%d\n", bfqd->bfq_wr_max_time > 0 ?
++ jiffies_to_msecs(bfqd->bfq_wr_max_time) :
++ jiffies_to_msecs(bfq_wr_duration(bfqd)));
++}
++
++static ssize_t bfq_weights_show(struct elevator_queue *e, char *page)
++{
++ struct bfq_queue *bfqq;
++ struct bfq_data *bfqd = e->elevator_data;
++ ssize_t num_char = 0;
++
++ num_char += sprintf(page + num_char, "Tot reqs queued %d\n\n",
++ bfqd->queued);
++
++ spin_lock_irq(bfqd->queue->queue_lock);
++
++ num_char += sprintf(page + num_char, "Active:\n");
++ list_for_each_entry(bfqq, &bfqd->active_list, bfqq_list) {
++ num_char += sprintf(page + num_char,
++ "pid%d: weight %hu, nr_queued %d %d, dur %d/%u\n",
++ bfqq->pid,
++ bfqq->entity.weight,
++ bfqq->queued[0],
++ bfqq->queued[1],
++ jiffies_to_msecs(jiffies - bfqq->last_wr_start_finish),
++ jiffies_to_msecs(bfqq->wr_cur_max_time));
++ }
++
++ num_char += sprintf(page + num_char, "Idle:\n");
++ list_for_each_entry(bfqq, &bfqd->idle_list, bfqq_list) {
++ num_char += sprintf(page + num_char,
++ "pid%d: weight %hu, dur %d/%u\n",
++ bfqq->pid,
++ bfqq->entity.weight,
++ jiffies_to_msecs(jiffies -
++ bfqq->last_wr_start_finish),
++ jiffies_to_msecs(bfqq->wr_cur_max_time));
++ }
++
++ spin_unlock_irq(bfqd->queue->queue_lock);
++
++ return num_char;
++}
++
++#define SHOW_FUNCTION(__FUNC, __VAR, __CONV) \
++static ssize_t __FUNC(struct elevator_queue *e, char *page) \
++{ \
++ struct bfq_data *bfqd = e->elevator_data; \
++ unsigned int __data = __VAR; \
++ if (__CONV) \
++ __data = jiffies_to_msecs(__data); \
++ return bfq_var_show(__data, (page)); \
++}
++SHOW_FUNCTION(bfq_quantum_show, bfqd->bfq_quantum, 0);
++SHOW_FUNCTION(bfq_fifo_expire_sync_show, bfqd->bfq_fifo_expire[1], 1);
++SHOW_FUNCTION(bfq_fifo_expire_async_show, bfqd->bfq_fifo_expire[0], 1);
++SHOW_FUNCTION(bfq_back_seek_max_show, bfqd->bfq_back_max, 0);
++SHOW_FUNCTION(bfq_back_seek_penalty_show, bfqd->bfq_back_penalty, 0);
++SHOW_FUNCTION(bfq_slice_idle_show, bfqd->bfq_slice_idle, 1);
++SHOW_FUNCTION(bfq_max_budget_show, bfqd->bfq_user_max_budget, 0);
++SHOW_FUNCTION(bfq_max_budget_async_rq_show,
++ bfqd->bfq_max_budget_async_rq, 0);
++SHOW_FUNCTION(bfq_timeout_sync_show, bfqd->bfq_timeout[BLK_RW_SYNC], 1);
++SHOW_FUNCTION(bfq_timeout_async_show, bfqd->bfq_timeout[BLK_RW_ASYNC], 1);
++SHOW_FUNCTION(bfq_low_latency_show, bfqd->low_latency, 0);
++SHOW_FUNCTION(bfq_wr_coeff_show, bfqd->bfq_wr_coeff, 0);
++SHOW_FUNCTION(bfq_wr_rt_max_time_show, bfqd->bfq_wr_rt_max_time, 1);
++SHOW_FUNCTION(bfq_wr_min_idle_time_show, bfqd->bfq_wr_min_idle_time, 1);
++SHOW_FUNCTION(bfq_wr_min_inter_arr_async_show, bfqd->bfq_wr_min_inter_arr_async,
++ 1);
++SHOW_FUNCTION(bfq_wr_max_softrt_rate_show, bfqd->bfq_wr_max_softrt_rate, 0);
++#undef SHOW_FUNCTION
++
++#define STORE_FUNCTION(__FUNC, __PTR, MIN, MAX, __CONV) \
++static ssize_t \
++__FUNC(struct elevator_queue *e, const char *page, size_t count) \
++{ \
++ struct bfq_data *bfqd = e->elevator_data; \
++ unsigned long uninitialized_var(__data); \
++ int ret = bfq_var_store(&__data, (page), count); \
++ if (__data < (MIN)) \
++ __data = (MIN); \
++ else if (__data > (MAX)) \
++ __data = (MAX); \
++ if (__CONV) \
++ *(__PTR) = msecs_to_jiffies(__data); \
++ else \
++ *(__PTR) = __data; \
++ return ret; \
++}
++STORE_FUNCTION(bfq_quantum_store, &bfqd->bfq_quantum, 1, INT_MAX, 0);
++STORE_FUNCTION(bfq_fifo_expire_sync_store, &bfqd->bfq_fifo_expire[1], 1,
++ INT_MAX, 1);
++STORE_FUNCTION(bfq_fifo_expire_async_store, &bfqd->bfq_fifo_expire[0], 1,
++ INT_MAX, 1);
++STORE_FUNCTION(bfq_back_seek_max_store, &bfqd->bfq_back_max, 0, INT_MAX, 0);
++STORE_FUNCTION(bfq_back_seek_penalty_store, &bfqd->bfq_back_penalty, 1,
++ INT_MAX, 0);
++STORE_FUNCTION(bfq_slice_idle_store, &bfqd->bfq_slice_idle, 0, INT_MAX, 1);
++STORE_FUNCTION(bfq_max_budget_async_rq_store, &bfqd->bfq_max_budget_async_rq,
++ 1, INT_MAX, 0);
++STORE_FUNCTION(bfq_timeout_async_store, &bfqd->bfq_timeout[BLK_RW_ASYNC], 0,
++ INT_MAX, 1);
++STORE_FUNCTION(bfq_wr_coeff_store, &bfqd->bfq_wr_coeff, 1, INT_MAX, 0);
++STORE_FUNCTION(bfq_wr_max_time_store, &bfqd->bfq_wr_max_time, 0, INT_MAX, 1);
++STORE_FUNCTION(bfq_wr_rt_max_time_store, &bfqd->bfq_wr_rt_max_time, 0, INT_MAX,
++ 1);
++STORE_FUNCTION(bfq_wr_min_idle_time_store, &bfqd->bfq_wr_min_idle_time, 0,
++ INT_MAX, 1);
++STORE_FUNCTION(bfq_wr_min_inter_arr_async_store,
++ &bfqd->bfq_wr_min_inter_arr_async, 0, INT_MAX, 1);
++STORE_FUNCTION(bfq_wr_max_softrt_rate_store, &bfqd->bfq_wr_max_softrt_rate, 0,
++ INT_MAX, 0);
++#undef STORE_FUNCTION
++
++/* do nothing for the moment */
++static ssize_t bfq_weights_store(struct elevator_queue *e,
++ const char *page, size_t count)
++{
++ return count;
++}
++
++static inline unsigned long bfq_estimated_max_budget(struct bfq_data *bfqd)
++{
++ u64 timeout = jiffies_to_msecs(bfqd->bfq_timeout[BLK_RW_SYNC]);
++
++ if (bfqd->peak_rate_samples >= BFQ_PEAK_RATE_SAMPLES)
++ return bfq_calc_max_budget(bfqd->peak_rate, timeout);
++ else
++ return bfq_default_max_budget;
++}
++
++static ssize_t bfq_max_budget_store(struct elevator_queue *e,
++ const char *page, size_t count)
++{
++ struct bfq_data *bfqd = e->elevator_data;
++ unsigned long uninitialized_var(__data);
++ int ret = bfq_var_store(&__data, (page), count);
++
++ if (__data == 0)
++ bfqd->bfq_max_budget = bfq_estimated_max_budget(bfqd);
++ else {
++ if (__data > INT_MAX)
++ __data = INT_MAX;
++ bfqd->bfq_max_budget = __data;
++ }
++
++ bfqd->bfq_user_max_budget = __data;
++
++ return ret;
++}
++
++static ssize_t bfq_timeout_sync_store(struct elevator_queue *e,
++ const char *page, size_t count)
++{
++ struct bfq_data *bfqd = e->elevator_data;
++ unsigned long uninitialized_var(__data);
++ int ret = bfq_var_store(&__data, (page), count);
++
++ if (__data < 1)
++ __data = 1;
++ else if (__data > INT_MAX)
++ __data = INT_MAX;
++
++ bfqd->bfq_timeout[BLK_RW_SYNC] = msecs_to_jiffies(__data);
++ if (bfqd->bfq_user_max_budget == 0)
++ bfqd->bfq_max_budget = bfq_estimated_max_budget(bfqd);
++
++ return ret;
++}
++
++static ssize_t bfq_low_latency_store(struct elevator_queue *e,
++ const char *page, size_t count)
++{
++ struct bfq_data *bfqd = e->elevator_data;
++ unsigned long uninitialized_var(__data);
++ int ret = bfq_var_store(&__data, (page), count);
++
++ if (__data > 1)
++ __data = 1;
++ if (__data == 0 && bfqd->low_latency != 0)
++ bfq_end_wr(bfqd);
++ bfqd->low_latency = __data;
++
++ return ret;
++}
++
++#define BFQ_ATTR(name) \
++ __ATTR(name, S_IRUGO|S_IWUSR, bfq_##name##_show, bfq_##name##_store)
++
++static struct elv_fs_entry bfq_attrs[] = {
++ BFQ_ATTR(quantum),
++ BFQ_ATTR(fifo_expire_sync),
++ BFQ_ATTR(fifo_expire_async),
++ BFQ_ATTR(back_seek_max),
++ BFQ_ATTR(back_seek_penalty),
++ BFQ_ATTR(slice_idle),
++ BFQ_ATTR(max_budget),
++ BFQ_ATTR(max_budget_async_rq),
++ BFQ_ATTR(timeout_sync),
++ BFQ_ATTR(timeout_async),
++ BFQ_ATTR(low_latency),
++ BFQ_ATTR(wr_coeff),
++ BFQ_ATTR(wr_max_time),
++ BFQ_ATTR(wr_rt_max_time),
++ BFQ_ATTR(wr_min_idle_time),
++ BFQ_ATTR(wr_min_inter_arr_async),
++ BFQ_ATTR(wr_max_softrt_rate),
++ BFQ_ATTR(weights),
++ __ATTR_NULL
++};
++
++static struct elevator_type iosched_bfq = {
++ .ops = {
++ .elevator_merge_fn = bfq_merge,
++ .elevator_merged_fn = bfq_merged_request,
++ .elevator_merge_req_fn = bfq_merged_requests,
++ .elevator_allow_merge_fn = bfq_allow_merge,
++ .elevator_dispatch_fn = bfq_dispatch_requests,
++ .elevator_add_req_fn = bfq_insert_request,
++ .elevator_activate_req_fn = bfq_activate_request,
++ .elevator_deactivate_req_fn = bfq_deactivate_request,
++ .elevator_completed_req_fn = bfq_completed_request,
++ .elevator_former_req_fn = elv_rb_former_request,
++ .elevator_latter_req_fn = elv_rb_latter_request,
++ .elevator_init_icq_fn = bfq_init_icq,
++ .elevator_exit_icq_fn = bfq_exit_icq,
++ .elevator_set_req_fn = bfq_set_request,
++ .elevator_put_req_fn = bfq_put_request,
++ .elevator_may_queue_fn = bfq_may_queue,
++ .elevator_init_fn = bfq_init_queue,
++ .elevator_exit_fn = bfq_exit_queue,
++ },
++ .icq_size = sizeof(struct bfq_io_cq),
++ .icq_align = __alignof__(struct bfq_io_cq),
++ .elevator_attrs = bfq_attrs,
++ .elevator_name = "bfq",
++ .elevator_owner = THIS_MODULE,
++};
++
++static int __init bfq_init(void)
++{
++ /*
++ * Can be 0 on HZ < 1000 setups.
++ */
++ if (bfq_slice_idle == 0)
++ bfq_slice_idle = 1;
++
++ if (bfq_timeout_async == 0)
++ bfq_timeout_async = 1;
++
++ if (bfq_slab_setup())
++ return -ENOMEM;
++
++ /*
++ * Times to load large popular applications for the typical systems
++ * installed on the reference devices (see the comments before the
++ * definitions of the two arrays).
++ */
++ T_slow[0] = msecs_to_jiffies(2600);
++ T_slow[1] = msecs_to_jiffies(1000);
++ T_fast[0] = msecs_to_jiffies(5500);
++ T_fast[1] = msecs_to_jiffies(2000);
++
++ /*
++ * Thresholds that determine the switch between speed classes (see
++ * the comments before the definition of the array).
++ */
++ device_speed_thresh[0] = (R_fast[0] + R_slow[0]) / 2;
++ device_speed_thresh[1] = (R_fast[1] + R_slow[1]) / 2;
++
++ elv_register(&iosched_bfq);
++ pr_info("BFQ I/O-scheduler version: v7r7");
++
++ return 0;
++}
++
++static void __exit bfq_exit(void)
++{
++ elv_unregister(&iosched_bfq);
++ bfq_slab_kill();
++}
++
++module_init(bfq_init);
++module_exit(bfq_exit);
++
++MODULE_AUTHOR("Fabio Checconi, Paolo Valente");
++MODULE_LICENSE("GPL");
+diff -Nur linux-4.1.3/block/bfq-sched.c linux-xbian-imx6/block/bfq-sched.c
+--- linux-4.1.3/block/bfq-sched.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/block/bfq-sched.c 2015-07-27 23:13:03.604123194 +0200
+@@ -0,0 +1,1186 @@
++/*
++ * BFQ: Hierarchical B-WF2Q+ scheduler.
++ *
++ * Based on ideas and code from CFQ:
++ * Copyright (C) 2003 Jens Axboe <axboe@kernel.dk>
++ *
++ * Copyright (C) 2008 Fabio Checconi <fabio@gandalf.sssup.it>
++ * Paolo Valente <paolo.valente@unimore.it>
++ *
++ * Copyright (C) 2010 Paolo Valente <paolo.valente@unimore.it>
++ */
++
++#ifdef CONFIG_CGROUP_BFQIO
++#define for_each_entity(entity) \
++ for (; entity != NULL; entity = entity->parent)
++
++#define for_each_entity_safe(entity, parent) \
++ for (; entity && ({ parent = entity->parent; 1; }); entity = parent)
++
++static struct bfq_entity *bfq_lookup_next_entity(struct bfq_sched_data *sd,
++ int extract,
++ struct bfq_data *bfqd);
++
++static inline void bfq_update_budget(struct bfq_entity *next_in_service)
++{
++ struct bfq_entity *bfqg_entity;
++ struct bfq_group *bfqg;
++ struct bfq_sched_data *group_sd;
++
++ BUG_ON(next_in_service == NULL);
++
++ group_sd = next_in_service->sched_data;
++
++ bfqg = container_of(group_sd, struct bfq_group, sched_data);
++ /*
++ * bfq_group's my_entity field is not NULL only if the group
++ * is not the root group. We must not touch the root entity
++ * as it must never become an in-service entity.
++ */
++ bfqg_entity = bfqg->my_entity;
++ if (bfqg_entity != NULL)
++ bfqg_entity->budget = next_in_service->budget;
++}
++
++static int bfq_update_next_in_service(struct bfq_sched_data *sd)
++{
++ struct bfq_entity *next_in_service;
++
++ if (sd->in_service_entity != NULL)
++ /* will update/requeue at the end of service */
++ return 0;
++
++ /*
++ * NOTE: this can be improved in many ways, such as returning
++ * 1 (and thus propagating upwards the update) only when the
++ * budget changes, or caching the bfqq that will be scheduled
++ * next from this subtree. By now we worry more about
++ * correctness than about performance...
++ */
++ next_in_service = bfq_lookup_next_entity(sd, 0, NULL);
++ sd->next_in_service = next_in_service;
++
++ if (next_in_service != NULL)
++ bfq_update_budget(next_in_service);
++
++ return 1;
++}
++
++static inline void bfq_check_next_in_service(struct bfq_sched_data *sd,
++ struct bfq_entity *entity)
++{
++ BUG_ON(sd->next_in_service != entity);
++}
++#else
++#define for_each_entity(entity) \
++ for (; entity != NULL; entity = NULL)
++
++#define for_each_entity_safe(entity, parent) \
++ for (parent = NULL; entity != NULL; entity = parent)
++
++static inline int bfq_update_next_in_service(struct bfq_sched_data *sd)
++{
++ return 0;
++}
++
++static inline void bfq_check_next_in_service(struct bfq_sched_data *sd,
++ struct bfq_entity *entity)
++{
++}
++
++static inline void bfq_update_budget(struct bfq_entity *next_in_service)
++{
++}
++#endif
++
++/*
++ * Shift for timestamp calculations. This actually limits the maximum
++ * service allowed in one timestamp delta (small shift values increase it),
++ * the maximum total weight that can be used for the queues in the system
++ * (big shift values increase it), and the period of virtual time
++ * wraparounds.
++ */
++#define WFQ_SERVICE_SHIFT 22
++
++/**
++ * bfq_gt - compare two timestamps.
++ * @a: first ts.
++ * @b: second ts.
++ *
++ * Return @a > @b, dealing with wrapping correctly.
++ */
++static inline int bfq_gt(u64 a, u64 b)
++{
++ return (s64)(a - b) > 0;
++}
++
++static inline struct bfq_queue *bfq_entity_to_bfqq(struct bfq_entity *entity)
++{
++ struct bfq_queue *bfqq = NULL;
++
++ BUG_ON(entity == NULL);
++
++ if (entity->my_sched_data == NULL)
++ bfqq = container_of(entity, struct bfq_queue, entity);
++
++ return bfqq;
++}
++
++
++/**
++ * bfq_delta - map service into the virtual time domain.
++ * @service: amount of service.
++ * @weight: scale factor (weight of an entity or weight sum).
++ */
++static inline u64 bfq_delta(unsigned long service,
++ unsigned long weight)
++{
++ u64 d = (u64)service << WFQ_SERVICE_SHIFT;
++
++ do_div(d, weight);
++ return d;
++}
++
++/**
++ * bfq_calc_finish - assign the finish time to an entity.
++ * @entity: the entity to act upon.
++ * @service: the service to be charged to the entity.
++ */
++static inline void bfq_calc_finish(struct bfq_entity *entity,
++ unsigned long service)
++{
++ struct bfq_queue *bfqq = bfq_entity_to_bfqq(entity);
++
++ BUG_ON(entity->weight == 0);
++
++ entity->finish = entity->start +
++ bfq_delta(service, entity->weight);
++
++ if (bfqq != NULL) {
++ bfq_log_bfqq(bfqq->bfqd, bfqq,
++ "calc_finish: serv %lu, w %d",
++ service, entity->weight);
++ bfq_log_bfqq(bfqq->bfqd, bfqq,
++ "calc_finish: start %llu, finish %llu, delta %llu",
++ entity->start, entity->finish,
++ bfq_delta(service, entity->weight));
++ }
++}
++
++/**
++ * bfq_entity_of - get an entity from a node.
++ * @node: the node field of the entity.
++ *
++ * Convert a node pointer to the relative entity. This is used only
++ * to simplify the logic of some functions and not as the generic
++ * conversion mechanism because, e.g., in the tree walking functions,
++ * the check for a %NULL value would be redundant.
++ */
++static inline struct bfq_entity *bfq_entity_of(struct rb_node *node)
++{
++ struct bfq_entity *entity = NULL;
++
++ if (node != NULL)
++ entity = rb_entry(node, struct bfq_entity, rb_node);
++
++ return entity;
++}
++
++/**
++ * bfq_extract - remove an entity from a tree.
++ * @root: the tree root.
++ * @entity: the entity to remove.
++ */
++static inline void bfq_extract(struct rb_root *root,
++ struct bfq_entity *entity)
++{
++ BUG_ON(entity->tree != root);
++
++ entity->tree = NULL;
++ rb_erase(&entity->rb_node, root);
++}
++
++/**
++ * bfq_idle_extract - extract an entity from the idle tree.
++ * @st: the service tree of the owning @entity.
++ * @entity: the entity being removed.
++ */
++static void bfq_idle_extract(struct bfq_service_tree *st,
++ struct bfq_entity *entity)
++{
++ struct bfq_queue *bfqq = bfq_entity_to_bfqq(entity);
++ struct rb_node *next;
++
++ BUG_ON(entity->tree != &st->idle);
++
++ if (entity == st->first_idle) {
++ next = rb_next(&entity->rb_node);
++ st->first_idle = bfq_entity_of(next);
++ }
++
++ if (entity == st->last_idle) {
++ next = rb_prev(&entity->rb_node);
++ st->last_idle = bfq_entity_of(next);
++ }
++
++ bfq_extract(&st->idle, entity);
++
++ if (bfqq != NULL)
++ list_del(&bfqq->bfqq_list);
++}
++
++/**
++ * bfq_insert - generic tree insertion.
++ * @root: tree root.
++ * @entity: entity to insert.
++ *
++ * This is used for the idle and the active tree, since they are both
++ * ordered by finish time.
++ */
++static void bfq_insert(struct rb_root *root, struct bfq_entity *entity)
++{
++ struct bfq_entity *entry;
++ struct rb_node **node = &root->rb_node;
++ struct rb_node *parent = NULL;
++
++ BUG_ON(entity->tree != NULL);
++
++ while (*node != NULL) {
++ parent = *node;
++ entry = rb_entry(parent, struct bfq_entity, rb_node);
++
++ if (bfq_gt(entry->finish, entity->finish))
++ node = &parent->rb_left;
++ else
++ node = &parent->rb_right;
++ }
++
++ rb_link_node(&entity->rb_node, parent, node);
++ rb_insert_color(&entity->rb_node, root);
++
++ entity->tree = root;
++}
++
++/**
++ * bfq_update_min - update the min_start field of a entity.
++ * @entity: the entity to update.
++ * @node: one of its children.
++ *
++ * This function is called when @entity may store an invalid value for
++ * min_start due to updates to the active tree. The function assumes
++ * that the subtree rooted at @node (which may be its left or its right
++ * child) has a valid min_start value.
++ */
++static inline void bfq_update_min(struct bfq_entity *entity,
++ struct rb_node *node)
++{
++ struct bfq_entity *child;
++
++ if (node != NULL) {
++ child = rb_entry(node, struct bfq_entity, rb_node);
++ if (bfq_gt(entity->min_start, child->min_start))
++ entity->min_start = child->min_start;
++ }
++}
++
++/**
++ * bfq_update_active_node - recalculate min_start.
++ * @node: the node to update.
++ *
++ * @node may have changed position or one of its children may have moved,
++ * this function updates its min_start value. The left and right subtrees
++ * are assumed to hold a correct min_start value.
++ */
++static inline void bfq_update_active_node(struct rb_node *node)
++{
++ struct bfq_entity *entity = rb_entry(node, struct bfq_entity, rb_node);
++
++ entity->min_start = entity->start;
++ bfq_update_min(entity, node->rb_right);
++ bfq_update_min(entity, node->rb_left);
++}
++
++/**
++ * bfq_update_active_tree - update min_start for the whole active tree.
++ * @node: the starting node.
++ *
++ * @node must be the deepest modified node after an update. This function
++ * updates its min_start using the values held by its children, assuming
++ * that they did not change, and then updates all the nodes that may have
++ * changed in the path to the root. The only nodes that may have changed
++ * are the ones in the path or their siblings.
++ */
++static void bfq_update_active_tree(struct rb_node *node)
++{
++ struct rb_node *parent;
++
++up:
++ bfq_update_active_node(node);
++
++ parent = rb_parent(node);
++ if (parent == NULL)
++ return;
++
++ if (node == parent->rb_left && parent->rb_right != NULL)
++ bfq_update_active_node(parent->rb_right);
++ else if (parent->rb_left != NULL)
++ bfq_update_active_node(parent->rb_left);
++
++ node = parent;
++ goto up;
++}
++
++static void bfq_weights_tree_add(struct bfq_data *bfqd,
++ struct bfq_entity *entity,
++ struct rb_root *root);
++
++static void bfq_weights_tree_remove(struct bfq_data *bfqd,
++ struct bfq_entity *entity,
++ struct rb_root *root);
++
++
++/**
++ * bfq_active_insert - insert an entity in the active tree of its
++ * group/device.
++ * @st: the service tree of the entity.
++ * @entity: the entity being inserted.
++ *
++ * The active tree is ordered by finish time, but an extra key is kept
++ * per each node, containing the minimum value for the start times of
++ * its children (and the node itself), so it's possible to search for
++ * the eligible node with the lowest finish time in logarithmic time.
++ */
++static void bfq_active_insert(struct bfq_service_tree *st,
++ struct bfq_entity *entity)
++{
++ struct bfq_queue *bfqq = bfq_entity_to_bfqq(entity);
++ struct rb_node *node = &entity->rb_node;
++#ifdef CONFIG_CGROUP_BFQIO
++ struct bfq_sched_data *sd = NULL;
++ struct bfq_group *bfqg = NULL;
++ struct bfq_data *bfqd = NULL;
++#endif
++
++ bfq_insert(&st->active, entity);
++
++ if (node->rb_left != NULL)
++ node = node->rb_left;
++ else if (node->rb_right != NULL)
++ node = node->rb_right;
++
++ bfq_update_active_tree(node);
++
++#ifdef CONFIG_CGROUP_BFQIO
++ sd = entity->sched_data;
++ bfqg = container_of(sd, struct bfq_group, sched_data);
++ BUG_ON(!bfqg);
++ bfqd = (struct bfq_data *)bfqg->bfqd;
++#endif
++ if (bfqq != NULL)
++ list_add(&bfqq->bfqq_list, &bfqq->bfqd->active_list);
++#ifdef CONFIG_CGROUP_BFQIO
++ else { /* bfq_group */
++ BUG_ON(!bfqd);
++ bfq_weights_tree_add(bfqd, entity, &bfqd->group_weights_tree);
++ }
++ if (bfqg != bfqd->root_group) {
++ BUG_ON(!bfqg);
++ BUG_ON(!bfqd);
++ bfqg->active_entities++;
++ if (bfqg->active_entities == 2)
++ bfqd->active_numerous_groups++;
++ }
++#endif
++}
++
++/**
++ * bfq_ioprio_to_weight - calc a weight from an ioprio.
++ * @ioprio: the ioprio value to convert.
++ */
++static inline unsigned short bfq_ioprio_to_weight(int ioprio)
++{
++ BUG_ON(ioprio < 0 || ioprio >= IOPRIO_BE_NR);
++ return IOPRIO_BE_NR - ioprio;
++}
++
++/**
++ * bfq_weight_to_ioprio - calc an ioprio from a weight.
++ * @weight: the weight value to convert.
++ *
++ * To preserve as mush as possible the old only-ioprio user interface,
++ * 0 is used as an escape ioprio value for weights (numerically) equal or
++ * larger than IOPRIO_BE_NR
++ */
++static inline unsigned short bfq_weight_to_ioprio(int weight)
++{
++ BUG_ON(weight < BFQ_MIN_WEIGHT || weight > BFQ_MAX_WEIGHT);
++ return IOPRIO_BE_NR - weight < 0 ? 0 : IOPRIO_BE_NR - weight;
++}
++
++static inline void bfq_get_entity(struct bfq_entity *entity)
++{
++ struct bfq_queue *bfqq = bfq_entity_to_bfqq(entity);
++
++ if (bfqq != NULL) {
++ atomic_inc(&bfqq->ref);
++ bfq_log_bfqq(bfqq->bfqd, bfqq, "get_entity: %p %d",
++ bfqq, atomic_read(&bfqq->ref));
++ }
++}
++
++/**
++ * bfq_find_deepest - find the deepest node that an extraction can modify.
++ * @node: the node being removed.
++ *
++ * Do the first step of an extraction in an rb tree, looking for the
++ * node that will replace @node, and returning the deepest node that
++ * the following modifications to the tree can touch. If @node is the
++ * last node in the tree return %NULL.
++ */
++static struct rb_node *bfq_find_deepest(struct rb_node *node)
++{
++ struct rb_node *deepest;
++
++ if (node->rb_right == NULL && node->rb_left == NULL)
++ deepest = rb_parent(node);
++ else if (node->rb_right == NULL)
++ deepest = node->rb_left;
++ else if (node->rb_left == NULL)
++ deepest = node->rb_right;
++ else {
++ deepest = rb_next(node);
++ if (deepest->rb_right != NULL)
++ deepest = deepest->rb_right;
++ else if (rb_parent(deepest) != node)
++ deepest = rb_parent(deepest);
++ }
++
++ return deepest;
++}
++
++/**
++ * bfq_active_extract - remove an entity from the active tree.
++ * @st: the service_tree containing the tree.
++ * @entity: the entity being removed.
++ */
++static void bfq_active_extract(struct bfq_service_tree *st,
++ struct bfq_entity *entity)
++{
++ struct bfq_queue *bfqq = bfq_entity_to_bfqq(entity);
++ struct rb_node *node;
++#ifdef CONFIG_CGROUP_BFQIO
++ struct bfq_sched_data *sd = NULL;
++ struct bfq_group *bfqg = NULL;
++ struct bfq_data *bfqd = NULL;
++#endif
++
++ node = bfq_find_deepest(&entity->rb_node);
++ bfq_extract(&st->active, entity);
++
++ if (node != NULL)
++ bfq_update_active_tree(node);
++
++#ifdef CONFIG_CGROUP_BFQIO
++ sd = entity->sched_data;
++ bfqg = container_of(sd, struct bfq_group, sched_data);
++ BUG_ON(!bfqg);
++ bfqd = (struct bfq_data *)bfqg->bfqd;
++#endif
++ if (bfqq != NULL)
++ list_del(&bfqq->bfqq_list);
++#ifdef CONFIG_CGROUP_BFQIO
++ else { /* bfq_group */
++ BUG_ON(!bfqd);
++ bfq_weights_tree_remove(bfqd, entity,
++ &bfqd->group_weights_tree);
++ }
++ if (bfqg != bfqd->root_group) {
++ BUG_ON(!bfqg);
++ BUG_ON(!bfqd);
++ BUG_ON(!bfqg->active_entities);
++ bfqg->active_entities--;
++ if (bfqg->active_entities == 1) {
++ BUG_ON(!bfqd->active_numerous_groups);
++ bfqd->active_numerous_groups--;
++ }
++ }
++#endif
++}
++
++/**
++ * bfq_idle_insert - insert an entity into the idle tree.
++ * @st: the service tree containing the tree.
++ * @entity: the entity to insert.
++ */
++static void bfq_idle_insert(struct bfq_service_tree *st,
++ struct bfq_entity *entity)
++{
++ struct bfq_queue *bfqq = bfq_entity_to_bfqq(entity);
++ struct bfq_entity *first_idle = st->first_idle;
++ struct bfq_entity *last_idle = st->last_idle;
++
++ if (first_idle == NULL || bfq_gt(first_idle->finish, entity->finish))
++ st->first_idle = entity;
++ if (last_idle == NULL || bfq_gt(entity->finish, last_idle->finish))
++ st->last_idle = entity;
++
++ bfq_insert(&st->idle, entity);
++
++ if (bfqq != NULL)
++ list_add(&bfqq->bfqq_list, &bfqq->bfqd->idle_list);
++}
++
++/**
++ * bfq_forget_entity - remove an entity from the wfq trees.
++ * @st: the service tree.
++ * @entity: the entity being removed.
++ *
++ * Update the device status and forget everything about @entity, putting
++ * the device reference to it, if it is a queue. Entities belonging to
++ * groups are not refcounted.
++ */
++static void bfq_forget_entity(struct bfq_service_tree *st,
++ struct bfq_entity *entity)
++{
++ struct bfq_queue *bfqq = bfq_entity_to_bfqq(entity);
++ struct bfq_sched_data *sd;
++
++ BUG_ON(!entity->on_st);
++
++ entity->on_st = 0;
++ st->wsum -= entity->weight;
++ if (bfqq != NULL) {
++ sd = entity->sched_data;
++ bfq_log_bfqq(bfqq->bfqd, bfqq, "forget_entity: %p %d",
++ bfqq, atomic_read(&bfqq->ref));
++ bfq_put_queue(bfqq);
++ }
++}
++
++/**
++ * bfq_put_idle_entity - release the idle tree ref of an entity.
++ * @st: service tree for the entity.
++ * @entity: the entity being released.
++ */
++static void bfq_put_idle_entity(struct bfq_service_tree *st,
++ struct bfq_entity *entity)
++{
++ bfq_idle_extract(st, entity);
++ bfq_forget_entity(st, entity);
++}
++
++/**
++ * bfq_forget_idle - update the idle tree if necessary.
++ * @st: the service tree to act upon.
++ *
++ * To preserve the global O(log N) complexity we only remove one entry here;
++ * as the idle tree will not grow indefinitely this can be done safely.
++ */
++static void bfq_forget_idle(struct bfq_service_tree *st)
++{
++ struct bfq_entity *first_idle = st->first_idle;
++ struct bfq_entity *last_idle = st->last_idle;
++
++ if (RB_EMPTY_ROOT(&st->active) && last_idle != NULL &&
++ !bfq_gt(last_idle->finish, st->vtime)) {
++ /*
++ * Forget the whole idle tree, increasing the vtime past
++ * the last finish time of idle entities.
++ */
++ st->vtime = last_idle->finish;
++ }
++
++ if (first_idle != NULL && !bfq_gt(first_idle->finish, st->vtime))
++ bfq_put_idle_entity(st, first_idle);
++}
++
++static struct bfq_service_tree *
++__bfq_entity_update_weight_prio(struct bfq_service_tree *old_st,
++ struct bfq_entity *entity)
++{
++ struct bfq_service_tree *new_st = old_st;
++
++ if (entity->ioprio_changed) {
++ struct bfq_queue *bfqq = bfq_entity_to_bfqq(entity);
++ unsigned short prev_weight, new_weight;
++ struct bfq_data *bfqd = NULL;
++ struct rb_root *root;
++#ifdef CONFIG_CGROUP_BFQIO
++ struct bfq_sched_data *sd;
++ struct bfq_group *bfqg;
++#endif
++
++ if (bfqq != NULL)
++ bfqd = bfqq->bfqd;
++#ifdef CONFIG_CGROUP_BFQIO
++ else {
++ sd = entity->my_sched_data;
++ bfqg = container_of(sd, struct bfq_group, sched_data);
++ BUG_ON(!bfqg);
++ bfqd = (struct bfq_data *)bfqg->bfqd;
++ BUG_ON(!bfqd);
++ }
++#endif
++
++ BUG_ON(old_st->wsum < entity->weight);
++ old_st->wsum -= entity->weight;
++
++ if (entity->new_weight != entity->orig_weight) {
++ if (entity->new_weight < BFQ_MIN_WEIGHT ||
++ entity->new_weight > BFQ_MAX_WEIGHT) {
++ printk(KERN_CRIT "update_weight_prio: "
++ "new_weight %d\n",
++ entity->new_weight);
++ BUG();
++ }
++ entity->orig_weight = entity->new_weight;
++ entity->ioprio =
++ bfq_weight_to_ioprio(entity->orig_weight);
++ } else if (entity->new_ioprio != entity->ioprio) {
++ entity->ioprio = entity->new_ioprio;
++ entity->orig_weight =
++ bfq_ioprio_to_weight(entity->ioprio);
++ } else
++ entity->new_weight = entity->orig_weight =
++ bfq_ioprio_to_weight(entity->ioprio);
++
++ entity->ioprio_class = entity->new_ioprio_class;
++ entity->ioprio_changed = 0;
++
++ /*
++ * NOTE: here we may be changing the weight too early,
++ * this will cause unfairness. The correct approach
++ * would have required additional complexity to defer
++ * weight changes to the proper time instants (i.e.,
++ * when entity->finish <= old_st->vtime).
++ */
++ new_st = bfq_entity_service_tree(entity);
++
++ prev_weight = entity->weight;
++ new_weight = entity->orig_weight *
++ (bfqq != NULL ? bfqq->wr_coeff : 1);
++ /*
++ * If the weight of the entity changes, remove the entity
++ * from its old weight counter (if there is a counter
++ * associated with the entity), and add it to the counter
++ * associated with its new weight.
++ */
++ if (prev_weight != new_weight) {
++ root = bfqq ? &bfqd->queue_weights_tree :
++ &bfqd->group_weights_tree;
++ bfq_weights_tree_remove(bfqd, entity, root);
++ }
++ entity->weight = new_weight;
++ /*
++ * Add the entity to its weights tree only if it is
++ * not associated with a weight-raised queue.
++ */
++ if (prev_weight != new_weight &&
++ (bfqq ? bfqq->wr_coeff == 1 : 1))
++ /* If we get here, root has been initialized. */
++ bfq_weights_tree_add(bfqd, entity, root);
++
++ new_st->wsum += entity->weight;
++
++ if (new_st != old_st)
++ entity->start = new_st->vtime;
++ }
++
++ return new_st;
++}
++
++/**
++ * bfq_bfqq_served - update the scheduler status after selection for
++ * service.
++ * @bfqq: the queue being served.
++ * @served: bytes to transfer.
++ *
++ * NOTE: this can be optimized, as the timestamps of upper level entities
++ * are synchronized every time a new bfqq is selected for service. By now,
++ * we keep it to better check consistency.
++ */
++static void bfq_bfqq_served(struct bfq_queue *bfqq, unsigned long served)
++{
++ struct bfq_entity *entity = &bfqq->entity;
++ struct bfq_service_tree *st;
++
++ for_each_entity(entity) {
++ st = bfq_entity_service_tree(entity);
++
++ entity->service += served;
++ BUG_ON(entity->service > entity->budget);
++ BUG_ON(st->wsum == 0);
++
++ st->vtime += bfq_delta(served, st->wsum);
++ bfq_forget_idle(st);
++ }
++ bfq_log_bfqq(bfqq->bfqd, bfqq, "bfqq_served %lu secs", served);
++}
++
++/**
++ * bfq_bfqq_charge_full_budget - set the service to the entity budget.
++ * @bfqq: the queue that needs a service update.
++ *
++ * When it's not possible to be fair in the service domain, because
++ * a queue is not consuming its budget fast enough (the meaning of
++ * fast depends on the timeout parameter), we charge it a full
++ * budget. In this way we should obtain a sort of time-domain
++ * fairness among all the seeky/slow queues.
++ */
++static inline void bfq_bfqq_charge_full_budget(struct bfq_queue *bfqq)
++{
++ struct bfq_entity *entity = &bfqq->entity;
++
++ bfq_log_bfqq(bfqq->bfqd, bfqq, "charge_full_budget");
++
++ bfq_bfqq_served(bfqq, entity->budget - entity->service);
++}
++
++/**
++ * __bfq_activate_entity - activate an entity.
++ * @entity: the entity being activated.
++ *
++ * Called whenever an entity is activated, i.e., it is not active and one
++ * of its children receives a new request, or has to be reactivated due to
++ * budget exhaustion. It uses the current budget of the entity (and the
++ * service received if @entity is active) of the queue to calculate its
++ * timestamps.
++ */
++static void __bfq_activate_entity(struct bfq_entity *entity)
++{
++ struct bfq_sched_data *sd = entity->sched_data;
++ struct bfq_service_tree *st = bfq_entity_service_tree(entity);
++
++ if (entity == sd->in_service_entity) {
++ BUG_ON(entity->tree != NULL);
++ /*
++ * If we are requeueing the current entity we have
++ * to take care of not charging to it service it has
++ * not received.
++ */
++ bfq_calc_finish(entity, entity->service);
++ entity->start = entity->finish;
++ sd->in_service_entity = NULL;
++ } else if (entity->tree == &st->active) {
++ /*
++ * Requeueing an entity due to a change of some
++ * next_in_service entity below it. We reuse the
++ * old start time.
++ */
++ bfq_active_extract(st, entity);
++ } else if (entity->tree == &st->idle) {
++ /*
++ * Must be on the idle tree, bfq_idle_extract() will
++ * check for that.
++ */
++ bfq_idle_extract(st, entity);
++ entity->start = bfq_gt(st->vtime, entity->finish) ?
++ st->vtime : entity->finish;
++ } else {
++ /*
++ * The finish time of the entity may be invalid, and
++ * it is in the past for sure, otherwise the queue
++ * would have been on the idle tree.
++ */
++ entity->start = st->vtime;
++ st->wsum += entity->weight;
++ bfq_get_entity(entity);
++
++ BUG_ON(entity->on_st);
++ entity->on_st = 1;
++ }
++
++ st = __bfq_entity_update_weight_prio(st, entity);
++ bfq_calc_finish(entity, entity->budget);
++ bfq_active_insert(st, entity);
++}
++
++/**
++ * bfq_activate_entity - activate an entity and its ancestors if necessary.
++ * @entity: the entity to activate.
++ *
++ * Activate @entity and all the entities on the path from it to the root.
++ */
++static void bfq_activate_entity(struct bfq_entity *entity)
++{
++ struct bfq_sched_data *sd;
++
++ for_each_entity(entity) {
++ __bfq_activate_entity(entity);
++
++ sd = entity->sched_data;
++ if (!bfq_update_next_in_service(sd))
++ /*
++ * No need to propagate the activation to the
++ * upper entities, as they will be updated when
++ * the in-service entity is rescheduled.
++ */
++ break;
++ }
++}
++
++/**
++ * __bfq_deactivate_entity - deactivate an entity from its service tree.
++ * @entity: the entity to deactivate.
++ * @requeue: if false, the entity will not be put into the idle tree.
++ *
++ * Deactivate an entity, independently from its previous state. If the
++ * entity was not on a service tree just return, otherwise if it is on
++ * any scheduler tree, extract it from that tree, and if necessary
++ * and if the caller did not specify @requeue, put it on the idle tree.
++ *
++ * Return %1 if the caller should update the entity hierarchy, i.e.,
++ * if the entity was in service or if it was the next_in_service for
++ * its sched_data; return %0 otherwise.
++ */
++static int __bfq_deactivate_entity(struct bfq_entity *entity, int requeue)
++{
++ struct bfq_sched_data *sd = entity->sched_data;
++ struct bfq_service_tree *st = bfq_entity_service_tree(entity);
++ int was_in_service = entity == sd->in_service_entity;
++ int ret = 0;
++
++ if (!entity->on_st)
++ return 0;
++
++ BUG_ON(was_in_service && entity->tree != NULL);
++
++ if (was_in_service) {
++ bfq_calc_finish(entity, entity->service);
++ sd->in_service_entity = NULL;
++ } else if (entity->tree == &st->active)
++ bfq_active_extract(st, entity);
++ else if (entity->tree == &st->idle)
++ bfq_idle_extract(st, entity);
++ else if (entity->tree != NULL)
++ BUG();
++
++ if (was_in_service || sd->next_in_service == entity)
++ ret = bfq_update_next_in_service(sd);
++
++ if (!requeue || !bfq_gt(entity->finish, st->vtime))
++ bfq_forget_entity(st, entity);
++ else
++ bfq_idle_insert(st, entity);
++
++ BUG_ON(sd->in_service_entity == entity);
++ BUG_ON(sd->next_in_service == entity);
++
++ return ret;
++}
++
++/**
++ * bfq_deactivate_entity - deactivate an entity.
++ * @entity: the entity to deactivate.
++ * @requeue: true if the entity can be put on the idle tree
++ */
++static void bfq_deactivate_entity(struct bfq_entity *entity, int requeue)
++{
++ struct bfq_sched_data *sd;
++ struct bfq_entity *parent;
++
++ for_each_entity_safe(entity, parent) {
++ sd = entity->sched_data;
++
++ if (!__bfq_deactivate_entity(entity, requeue))
++ /*
++ * The parent entity is still backlogged, and
++ * we don't need to update it as it is still
++ * in service.
++ */
++ break;
++
++ if (sd->next_in_service != NULL)
++ /*
++ * The parent entity is still backlogged and
++ * the budgets on the path towards the root
++ * need to be updated.
++ */
++ goto update;
++
++ /*
++ * If we reach there the parent is no more backlogged and
++ * we want to propagate the dequeue upwards.
++ */
++ requeue = 1;
++ }
++
++ return;
++
++update:
++ entity = parent;
++ for_each_entity(entity) {
++ __bfq_activate_entity(entity);
++
++ sd = entity->sched_data;
++ if (!bfq_update_next_in_service(sd))
++ break;
++ }
++}
++
++/**
++ * bfq_update_vtime - update vtime if necessary.
++ * @st: the service tree to act upon.
++ *
++ * If necessary update the service tree vtime to have at least one
++ * eligible entity, skipping to its start time. Assumes that the
++ * active tree of the device is not empty.
++ *
++ * NOTE: this hierarchical implementation updates vtimes quite often,
++ * we may end up with reactivated processes getting timestamps after a
++ * vtime skip done because we needed a ->first_active entity on some
++ * intermediate node.
++ */
++static void bfq_update_vtime(struct bfq_service_tree *st)
++{
++ struct bfq_entity *entry;
++ struct rb_node *node = st->active.rb_node;
++
++ entry = rb_entry(node, struct bfq_entity, rb_node);
++ if (bfq_gt(entry->min_start, st->vtime)) {
++ st->vtime = entry->min_start;
++ bfq_forget_idle(st);
++ }
++}
++
++/**
++ * bfq_first_active_entity - find the eligible entity with
++ * the smallest finish time
++ * @st: the service tree to select from.
++ *
++ * This function searches the first schedulable entity, starting from the
++ * root of the tree and going on the left every time on this side there is
++ * a subtree with at least one eligible (start >= vtime) entity. The path on
++ * the right is followed only if a) the left subtree contains no eligible
++ * entities and b) no eligible entity has been found yet.
++ */
++static struct bfq_entity *bfq_first_active_entity(struct bfq_service_tree *st)
++{
++ struct bfq_entity *entry, *first = NULL;
++ struct rb_node *node = st->active.rb_node;
++
++ while (node != NULL) {
++ entry = rb_entry(node, struct bfq_entity, rb_node);
++left:
++ if (!bfq_gt(entry->start, st->vtime))
++ first = entry;
++
++ BUG_ON(bfq_gt(entry->min_start, st->vtime));
++
++ if (node->rb_left != NULL) {
++ entry = rb_entry(node->rb_left,
++ struct bfq_entity, rb_node);
++ if (!bfq_gt(entry->min_start, st->vtime)) {
++ node = node->rb_left;
++ goto left;
++ }
++ }
++ if (first != NULL)
++ break;
++ node = node->rb_right;
++ }
++
++ BUG_ON(first == NULL && !RB_EMPTY_ROOT(&st->active));
++ return first;
++}
++
++/**
++ * __bfq_lookup_next_entity - return the first eligible entity in @st.
++ * @st: the service tree.
++ *
++ * Update the virtual time in @st and return the first eligible entity
++ * it contains.
++ */
++static struct bfq_entity *__bfq_lookup_next_entity(struct bfq_service_tree *st,
++ bool force)
++{
++ struct bfq_entity *entity, *new_next_in_service = NULL;
++
++ if (RB_EMPTY_ROOT(&st->active))
++ return NULL;
++
++ bfq_update_vtime(st);
++ entity = bfq_first_active_entity(st);
++ BUG_ON(bfq_gt(entity->start, st->vtime));
++
++ /*
++ * If the chosen entity does not match with the sched_data's
++ * next_in_service and we are forcedly serving the IDLE priority
++ * class tree, bubble up budget update.
++ */
++ if (unlikely(force && entity != entity->sched_data->next_in_service)) {
++ new_next_in_service = entity;
++ for_each_entity(new_next_in_service)
++ bfq_update_budget(new_next_in_service);
++ }
++
++ return entity;
++}
++
++/**
++ * bfq_lookup_next_entity - return the first eligible entity in @sd.
++ * @sd: the sched_data.
++ * @extract: if true the returned entity will be also extracted from @sd.
++ *
++ * NOTE: since we cache the next_in_service entity at each level of the
++ * hierarchy, the complexity of the lookup can be decreased with
++ * absolutely no effort just returning the cached next_in_service value;
++ * we prefer to do full lookups to test the consistency of * the data
++ * structures.
++ */
++static struct bfq_entity *bfq_lookup_next_entity(struct bfq_sched_data *sd,
++ int extract,
++ struct bfq_data *bfqd)
++{
++ struct bfq_service_tree *st = sd->service_tree;
++ struct bfq_entity *entity;
++ int i = 0;
++
++ BUG_ON(sd->in_service_entity != NULL);
++
++ if (bfqd != NULL &&
++ jiffies - bfqd->bfq_class_idle_last_service > BFQ_CL_IDLE_TIMEOUT) {
++ entity = __bfq_lookup_next_entity(st + BFQ_IOPRIO_CLASSES - 1,
++ true);
++ if (entity != NULL) {
++ i = BFQ_IOPRIO_CLASSES - 1;
++ bfqd->bfq_class_idle_last_service = jiffies;
++ sd->next_in_service = entity;
++ }
++ }
++ for (; i < BFQ_IOPRIO_CLASSES; i++) {
++ entity = __bfq_lookup_next_entity(st + i, false);
++ if (entity != NULL) {
++ if (extract) {
++ bfq_check_next_in_service(sd, entity);
++ bfq_active_extract(st + i, entity);
++ sd->in_service_entity = entity;
++ sd->next_in_service = NULL;
++ }
++ break;
++ }
++ }
++
++ return entity;
++}
++
++/*
++ * Get next queue for service.
++ */
++static struct bfq_queue *bfq_get_next_queue(struct bfq_data *bfqd)
++{
++ struct bfq_entity *entity = NULL;
++ struct bfq_sched_data *sd;
++ struct bfq_queue *bfqq;
++
++ BUG_ON(bfqd->in_service_queue != NULL);
++
++ if (bfqd->busy_queues == 0)
++ return NULL;
++
++ sd = &bfqd->root_group->sched_data;
++ for (; sd != NULL; sd = entity->my_sched_data) {
++ entity = bfq_lookup_next_entity(sd, 1, bfqd);
++ BUG_ON(entity == NULL);
++ entity->service = 0;
++ }
++
++ bfqq = bfq_entity_to_bfqq(entity);
++ BUG_ON(bfqq == NULL);
++
++ return bfqq;
++}
++
++static void __bfq_bfqd_reset_in_service(struct bfq_data *bfqd)
++{
++ if (bfqd->in_service_bic != NULL) {
++ put_io_context(bfqd->in_service_bic->icq.ioc);
++ bfqd->in_service_bic = NULL;
++ }
++
++ bfqd->in_service_queue = NULL;
++ del_timer(&bfqd->idle_slice_timer);
++}
++
++static void bfq_deactivate_bfqq(struct bfq_data *bfqd, struct bfq_queue *bfqq,
++ int requeue)
++{
++ struct bfq_entity *entity = &bfqq->entity;
++
++ if (bfqq == bfqd->in_service_queue)
++ __bfq_bfqd_reset_in_service(bfqd);
++
++ bfq_deactivate_entity(entity, requeue);
++}
++
++static void bfq_activate_bfqq(struct bfq_data *bfqd, struct bfq_queue *bfqq)
++{
++ struct bfq_entity *entity = &bfqq->entity;
++
++ bfq_activate_entity(entity);
++}
++
++/*
++ * Called when the bfqq no longer has requests pending, remove it from
++ * the service tree.
++ */
++static void bfq_del_bfqq_busy(struct bfq_data *bfqd, struct bfq_queue *bfqq,
++ int requeue)
++{
++ BUG_ON(!bfq_bfqq_busy(bfqq));
++ BUG_ON(!RB_EMPTY_ROOT(&bfqq->sort_list));
++
++ bfq_log_bfqq(bfqd, bfqq, "del from busy");
++
++ bfq_clear_bfqq_busy(bfqq);
++
++ BUG_ON(bfqd->busy_queues == 0);
++ bfqd->busy_queues--;
++
++ if (!bfqq->dispatched) {
++ bfq_weights_tree_remove(bfqd, &bfqq->entity,
++ &bfqd->queue_weights_tree);
++ if (!blk_queue_nonrot(bfqd->queue)) {
++ BUG_ON(!bfqd->busy_in_flight_queues);
++ bfqd->busy_in_flight_queues--;
++ if (bfq_bfqq_constantly_seeky(bfqq)) {
++ BUG_ON(!bfqd->
++ const_seeky_busy_in_flight_queues);
++ bfqd->const_seeky_busy_in_flight_queues--;
++ }
++ }
++ }
++ if (bfqq->wr_coeff > 1)
++ bfqd->wr_busy_queues--;
++
++ bfq_deactivate_bfqq(bfqd, bfqq, requeue);
++}
++
++/*
++ * Called when an inactive queue receives a new request.
++ */
++static void bfq_add_bfqq_busy(struct bfq_data *bfqd, struct bfq_queue *bfqq)
++{
++ BUG_ON(bfq_bfqq_busy(bfqq));
++ BUG_ON(bfqq == bfqd->in_service_queue);
++
++ bfq_log_bfqq(bfqd, bfqq, "add to busy");
++
++ bfq_activate_bfqq(bfqd, bfqq);
++
++ bfq_mark_bfqq_busy(bfqq);
++ bfqd->busy_queues++;
++
++ if (!bfqq->dispatched) {
++ if (bfqq->wr_coeff == 1)
++ bfq_weights_tree_add(bfqd, &bfqq->entity,
++ &bfqd->queue_weights_tree);
++ if (!blk_queue_nonrot(bfqd->queue)) {
++ bfqd->busy_in_flight_queues++;
++ if (bfq_bfqq_constantly_seeky(bfqq))
++ bfqd->const_seeky_busy_in_flight_queues++;
++ }
++ }
++ if (bfqq->wr_coeff > 1)
++ bfqd->wr_busy_queues++;
++}
+diff -Nur linux-4.1.3/block/Kconfig.iosched linux-xbian-imx6/block/Kconfig.iosched
+--- linux-4.1.3/block/Kconfig.iosched 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/block/Kconfig.iosched 2015-07-27 23:13:03.600137415 +0200
+@@ -39,6 +39,27 @@
+ ---help---
+ Enable group IO scheduling in CFQ.
+
++config IOSCHED_BFQ
++ tristate "BFQ I/O scheduler"
++ default n
++ ---help---
++ The BFQ I/O scheduler tries to distribute bandwidth among
++ all processes according to their weights.
++ It aims at distributing the bandwidth as desired, independently of
++ the disk parameters and with any workload. It also tries to
++ guarantee low latency to interactive and soft real-time
++ applications. If compiled built-in (saying Y here), BFQ can
++ be configured to support hierarchical scheduling.
++
++config CGROUP_BFQIO
++ bool "BFQ hierarchical scheduling support"
++ depends on CGROUPS && IOSCHED_BFQ=y
++ default n
++ ---help---
++ Enable hierarchical scheduling in BFQ, using the cgroups
++ filesystem interface. The name of the subsystem will be
++ bfqio.
++
+ choice
+ prompt "Default I/O scheduler"
+ default DEFAULT_CFQ
+@@ -52,6 +73,16 @@
+ config DEFAULT_CFQ
+ bool "CFQ" if IOSCHED_CFQ=y
+
++ config DEFAULT_BFQ
++ bool "BFQ" if IOSCHED_BFQ=y
++ help
++ Selects BFQ as the default I/O scheduler which will be
++ used by default for all block devices.
++ The BFQ I/O scheduler aims at distributing the bandwidth
++ as desired, independently of the disk parameters and with
++ any workload. It also tries to guarantee low latency to
++ interactive and soft real-time applications.
++
+ config DEFAULT_NOOP
+ bool "No-op"
+
+@@ -61,6 +92,7 @@
+ string
+ default "deadline" if DEFAULT_DEADLINE
+ default "cfq" if DEFAULT_CFQ
++ default "bfq" if DEFAULT_BFQ
+ default "noop" if DEFAULT_NOOP
+
+ endmenu
+diff -Nur linux-4.1.3/block/Makefile linux-xbian-imx6/block/Makefile
+--- linux-4.1.3/block/Makefile 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/block/Makefile 2015-07-27 23:13:03.600137415 +0200
+@@ -18,6 +18,7 @@
+ obj-$(CONFIG_IOSCHED_NOOP) += noop-iosched.o
+ obj-$(CONFIG_IOSCHED_DEADLINE) += deadline-iosched.o
+ obj-$(CONFIG_IOSCHED_CFQ) += cfq-iosched.o
++obj-$(CONFIG_IOSCHED_BFQ) += bfq-iosched.o
+
+ obj-$(CONFIG_BLOCK_COMPAT) += compat_ioctl.o
+ obj-$(CONFIG_BLK_CMDLINE_PARSER) += cmdline-parser.o
+diff -Nur linux-4.1.3/Documentation/devicetree/bindings/mmc/mmc.txt linux-xbian-imx6/Documentation/devicetree/bindings/mmc/mmc.txt
+--- linux-4.1.3/Documentation/devicetree/bindings/mmc/mmc.txt 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/Documentation/devicetree/bindings/mmc/mmc.txt 2015-07-27 23:12:59.335353684 +0200
+@@ -5,6 +5,8 @@
+ Interpreted by the OF core:
+ - reg: Registers location and length.
+ - interrupts: Interrupts used by the MMC controller.
++- clocks: Clocks needed for the host controller, if any.
++- clock-names: Goes with clocks above.
+
+ Card detection:
+ If no property below is supplied, host native card detect is used.
+@@ -43,6 +45,15 @@
+ - dsr: Value the card's (optional) Driver Stage Register (DSR) should be
+ programmed with. Valid range: [0 .. 0xffff].
+
++Card power and reset control:
++The following properties can be specified for cases where the MMC
++peripheral needs additional reset, regulator and clock lines. It is for
++example common for WiFi/BT adapters to have these separate from the main
++MMC bus:
++ - card-reset-gpios: Specify GPIOs for card reset (reset active low)
++ - card-external-vcc-supply: Regulator to drive (independent) card VCC
++ - clock with name "card_ext_clock": External clock provided to the card
++
+ *NOTE* on CD and WP polarity. To use common for all SD/MMC host controllers line
+ polarity properties, we have to fix the meaning of the "normal" and "inverted"
+ line levels. We choose to follow the SDHCI standard, which specifies both those
+diff -Nur linux-4.1.3/Documentation/devicetree/bindings/vendor-prefixes.txt linux-xbian-imx6/Documentation/devicetree/bindings/vendor-prefixes.txt
+--- linux-4.1.3/Documentation/devicetree/bindings/vendor-prefixes.txt 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/Documentation/devicetree/bindings/vendor-prefixes.txt 2015-07-27 23:12:59.518699524 +0200
+@@ -201,6 +201,7 @@
+ variscite Variscite Ltd.
+ via VIA Technologies, Inc.
+ virtio Virtual I/O Device Specification, developed by the OASIS consortium
++vivante Vivante Corporation
+ voipac Voipac Technologies s.r.o.
+ winbond Winbond Electronics corp.
+ wlf Wolfson Microelectronics
+diff -Nur linux-4.1.3/drivers/char/frandom.c linux-xbian-imx6/drivers/char/frandom.c
+--- linux-4.1.3/drivers/char/frandom.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/char/frandom.c 2015-07-27 23:13:03.986757999 +0200
+@@ -0,0 +1,415 @@
++/*
++** frandom.c
++** Fast pseudo-random generator
++**
++** (c) Copyright 2003-2011 Eli Billauer
++** http://www.billauer.co.il
++**
++** This program is free software; you can redistribute it and/or modify
++** it under the terms of the GNU General Public License as published by
++** the Free Software Foundation; either version 2 of the License, or
++** (at your option) any later version.
++**
++**
++*/
++
++#include <linux/version.h>
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/slab.h>
++#include <linux/fs.h>
++#include <linux/errno.h>
++#include <linux/types.h>
++#include <linux/random.h>
++
++#include <asm/uaccess.h>
++#include <linux/cdev.h>
++#include <linux/err.h>
++#include <linux/device.h>
++
++#define INTERNAL_SEED 0
++#define EXTERNAL_SEED 1
++
++#define FRANDOM_MAJOR 235
++#define FRANDOM_MINOR 11
++#define ERANDOM_MINOR 12
++
++static struct file_operations frandom_fops; /* Values assigned below */
++
++static int erandom_seeded = 0; /* Internal flag */
++
++static int frandom_major = FRANDOM_MAJOR;
++static int frandom_minor = FRANDOM_MINOR;
++static int erandom_minor = ERANDOM_MINOR;
++static int frandom_bufsize = 256;
++static int frandom_chunklimit = 0; /* =0 means unlimited */
++
++static struct cdev frandom_cdev;
++static struct cdev erandom_cdev;
++static struct class *frandom_class;
++struct device *frandom_device;
++struct device *erandom_device;
++
++MODULE_DESCRIPTION("Fast pseudo-random number generator");
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Eli Billauer");
++module_param(frandom_major, int, 0);
++module_param(frandom_minor, int, 0);
++module_param(erandom_minor, int, 0);
++module_param(frandom_bufsize, int, 0);
++module_param(frandom_chunklimit, int, 0);
++
++MODULE_PARM_DESC(frandom_major,"Major number of /dev/frandom and /dev/erandom");
++MODULE_PARM_DESC(frandom_minor,"Minor number of /dev/frandom");
++MODULE_PARM_DESC(erandom_minor,"Minor number of /dev/erandom");
++MODULE_PARM_DESC(frandom_bufsize,"Internal buffer size in bytes. Default is 256. Must be >= 256");
++MODULE_PARM_DESC(frandom_chunklimit,"Limit for read() blocks size. 0 (default) is unlimited, otherwise must be >= 256");
++
++struct frandom_state
++{
++ struct semaphore sem; /* Semaphore on the state structure */
++
++ u8 S[256]; /* The state array */
++ u8 i;
++ u8 j;
++
++ char *buf;
++};
++
++static struct frandom_state *erandom_state;
++
++static inline void swap_byte(u8 *a, u8 *b)
++{
++ u8 swapByte;
++
++ swapByte = *a;
++ *a = *b;
++ *b = swapByte;
++}
++
++static void init_rand_state(struct frandom_state *state, int seedflag);
++
++void erandom_get_random_bytes(char *buf, size_t count)
++{
++ struct frandom_state *state = erandom_state;
++ int k;
++
++ unsigned int i;
++ unsigned int j;
++ u8 *S;
++
++ /* If we fail to get the semaphore, we revert to external random data.
++ Since semaphore blocking is expected to be very rare, and interrupts
++ during these rare and very short periods of time even less frequent,
++ we take the better-safe-than-sorry approach, and fill the buffer
++ some expensive random data, in case the caller wasn't aware of this
++ possibility, and expects random data anyhow.
++ */
++
++ if (down_interruptible(&state->sem)) {
++ get_random_bytes(buf, count);
++ return;
++ }
++
++ /* We seed erandom as late as possible, hoping that the kernel's main
++ RNG is already restored in the boot sequence (not critical, but
++ better.
++ */
++
++ if (!erandom_seeded) {
++ erandom_seeded = 1;
++ init_rand_state(state, EXTERNAL_SEED);
++ printk(KERN_INFO "frandom: Seeded global generator now (used by erandom)\n");
++ }
++
++ i = state->i;
++ j = state->j;
++ S = state->S;
++
++ for (k=0; k<count; k++) {
++ i = (i + 1) & 0xff;
++ j = (j + S[i]) & 0xff;
++ swap_byte(&S[i], &S[j]);
++ *buf++ = S[(S[i] + S[j]) & 0xff];
++ }
++
++ state->i = i;
++ state->j = j;
++
++ up(&state->sem);
++}
++
++static void init_rand_state(struct frandom_state *state, int seedflag)
++{
++ unsigned int i, j, k;
++ u8 *S;
++ u8 *seed = state->buf;
++
++ if (seedflag == INTERNAL_SEED)
++ erandom_get_random_bytes(seed, 256);
++ else
++ get_random_bytes(seed, 256);
++
++ S = state->S;
++ for (i=0; i<256; i++)
++ *S++=i;
++
++ j=0;
++ S = state->S;
++
++ for (i=0; i<256; i++) {
++ j = (j + S[i] + *seed++) & 0xff;
++ swap_byte(&S[i], &S[j]);
++ }
++
++ /* It's considered good practice to discard the first 256 bytes
++ generated. So we do it:
++ */
++
++ i=0; j=0;
++ for (k=0; k<256; k++) {
++ i = (i + 1) & 0xff;
++ j = (j + S[i]) & 0xff;
++ swap_byte(&S[i], &S[j]);
++ }
++
++ state->i = i; /* Save state */
++ state->j = j;
++}
++
++static int frandom_open(struct inode *inode, struct file *filp)
++{
++
++ struct frandom_state *state;
++
++ int num = iminor(inode);
++
++ /* This should never happen, now when the minors are regsitered
++ * explicitly
++ */
++ if ((num != frandom_minor) && (num != erandom_minor)) return -ENODEV;
++
++ state = kmalloc(sizeof(struct frandom_state), GFP_KERNEL);
++ if (!state)
++ return -ENOMEM;
++
++ state->buf = kmalloc(frandom_bufsize, GFP_KERNEL);
++ if (!state->buf) {
++ kfree(state);
++ return -ENOMEM;
++ }
++
++ sema_init(&state->sem, 1); /* Init semaphore as a mutex */
++
++ if (num == frandom_minor)
++ init_rand_state(state, EXTERNAL_SEED);
++ else
++ init_rand_state(state, INTERNAL_SEED);
++
++ filp->private_data = state;
++
++ return 0; /* Success */
++}
++
++static int frandom_release(struct inode *inode, struct file *filp)
++{
++
++ struct frandom_state *state = filp->private_data;
++
++ kfree(state->buf);
++ kfree(state);
++
++ return 0;
++}
++
++static ssize_t frandom_read(struct file *filp, char *buf, size_t count,
++ loff_t *f_pos)
++{
++ struct frandom_state *state = filp->private_data;
++ ssize_t ret;
++ int dobytes, k;
++ char *localbuf;
++
++ unsigned int i;
++ unsigned int j;
++ u8 *S;
++
++ if (down_interruptible(&state->sem))
++ return -ERESTARTSYS;
++
++ if ((frandom_chunklimit > 0) && (count > frandom_chunklimit))
++ count = frandom_chunklimit;
++
++ ret = count; /* It's either everything or an error... */
++
++ i = state->i;
++ j = state->j;
++ S = state->S;
++
++ while (count) {
++ if (count > frandom_bufsize)
++ dobytes = frandom_bufsize;
++ else
++ dobytes = count;
++
++ localbuf = state->buf;
++
++ for (k=0; k<dobytes; k++) {
++ i = (i + 1) & 0xff;
++ j = (j + S[i]) & 0xff;
++ swap_byte(&S[i], &S[j]);
++ *localbuf++ = S[(S[i] + S[j]) & 0xff];
++ }
++
++ if (copy_to_user(buf, state->buf, dobytes)) {
++ ret = -EFAULT;
++ goto out;
++ }
++
++ buf += dobytes;
++ count -= dobytes;
++ }
++
++ out:
++ state->i = i;
++ state->j = j;
++
++ up(&state->sem);
++ return ret;
++}
++
++static struct file_operations frandom_fops = {
++ read: frandom_read,
++ open: frandom_open,
++ release: frandom_release,
++};
++
++static void frandom_cleanup_module(void) {
++ unregister_chrdev_region(MKDEV(frandom_major, erandom_minor), 1);
++ cdev_del(&erandom_cdev);
++ device_destroy(frandom_class, MKDEV(frandom_major, erandom_minor));
++
++ unregister_chrdev_region(MKDEV(frandom_major, frandom_minor), 1);
++ cdev_del(&frandom_cdev);
++ device_destroy(frandom_class, MKDEV(frandom_major, frandom_minor));
++ class_destroy(frandom_class);
++
++ kfree(erandom_state->buf);
++ kfree(erandom_state);
++}
++
++
++static int frandom_init_module(void)
++{
++ int result;
++
++ /* The buffer size MUST be at least 256 bytes, because we assume that
++ minimal length in init_rand_state().
++ */
++ if (frandom_bufsize < 256) {
++ printk(KERN_ERR "frandom: Refused to load because frandom_bufsize=%d < 256\n",frandom_bufsize);
++ return -EINVAL;
++ }
++ if ((frandom_chunklimit != 0) && (frandom_chunklimit < 256)) {
++ printk(KERN_ERR "frandom: Refused to load because frandom_chunklimit=%d < 256 and != 0\n",frandom_chunklimit);
++ return -EINVAL;
++ }
++
++ erandom_state = kmalloc(sizeof(struct frandom_state), GFP_KERNEL);
++ if (!erandom_state)
++ return -ENOMEM;
++
++ /* This specific buffer is only used for seeding, so we need
++ 256 bytes exactly */
++ erandom_state->buf = kmalloc(256, GFP_KERNEL);
++ if (!erandom_state->buf) {
++ kfree(erandom_state);
++ return -ENOMEM;
++ }
++
++ sema_init(&erandom_state->sem, 1); /* Init semaphore as a mutex */
++
++ erandom_seeded = 0;
++
++ frandom_class = class_create(THIS_MODULE, "fastrng");
++ if (IS_ERR(frandom_class)) {
++ result = PTR_ERR(frandom_class);
++ printk(KERN_WARNING "frandom: Failed to register class fastrng\n");
++ goto error0;
++ }
++
++ /*
++ * Register your major, and accept a dynamic number. This is the
++ * first thing to do, in order to avoid releasing other module's
++ * fops in frandom_cleanup_module()
++ */
++
++ cdev_init(&frandom_cdev, &frandom_fops);
++ frandom_cdev.owner = THIS_MODULE;
++ result = cdev_add(&frandom_cdev, MKDEV(frandom_major, frandom_minor), 1);
++ if (result) {
++ printk(KERN_WARNING "frandom: Failed to add cdev for /dev/frandom\n");
++ goto error1;
++ }
++
++ result = register_chrdev_region(MKDEV(frandom_major, frandom_minor), 1, "/dev/frandom");
++ if (result < 0) {
++ printk(KERN_WARNING "frandom: can't get major/minor %d/%d\n", frandom_major, frandom_minor);
++ goto error2;
++ }
++
++ frandom_device = device_create(frandom_class, NULL, MKDEV(frandom_major, frandom_minor), NULL, "frandom");
++
++ if (IS_ERR(frandom_device)) {
++ printk(KERN_WARNING "frandom: Failed to create frandom device\n");
++ goto error3;
++ }
++
++ cdev_init(&erandom_cdev, &frandom_fops);
++ erandom_cdev.owner = THIS_MODULE;
++ result = cdev_add(&erandom_cdev, MKDEV(frandom_major, erandom_minor), 1);
++ if (result) {
++ printk(KERN_WARNING "frandom: Failed to add cdev for /dev/erandom\n");
++ goto error4;
++ }
++
++ result = register_chrdev_region(MKDEV(frandom_major, erandom_minor), 1, "/dev/erandom");
++ if (result < 0) {
++ printk(KERN_WARNING "frandom: can't get major/minor %d/%d\n", frandom_major, erandom_minor);
++ goto error5;
++ }
++
++ erandom_device = device_create(frandom_class, NULL, MKDEV(frandom_major, erandom_minor), NULL, "erandom");
++
++ if (IS_ERR(erandom_device)) {
++ printk(KERN_WARNING "frandom: Failed to create erandom device\n");
++ goto error6;
++ }
++ return 0; /* succeed */
++
++ error6:
++ unregister_chrdev_region(MKDEV(frandom_major, erandom_minor), 1);
++ error5:
++ cdev_del(&erandom_cdev);
++ error4:
++ device_destroy(frandom_class, MKDEV(frandom_major, frandom_minor));
++ error3:
++ unregister_chrdev_region(MKDEV(frandom_major, frandom_minor), 1);
++ error2:
++ cdev_del(&frandom_cdev);
++ error1:
++ class_destroy(frandom_class);
++ error0:
++ kfree(erandom_state->buf);
++ kfree(erandom_state);
++
++ return result;
++}
++
++module_init(frandom_init_module);
++module_exit(frandom_cleanup_module);
++
++EXPORT_SYMBOL(erandom_get_random_bytes);
+diff -Nur linux-4.1.3/drivers/char/Makefile linux-xbian-imx6/drivers/char/Makefile
+--- linux-4.1.3/drivers/char/Makefile 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/drivers/char/Makefile 2015-07-27 23:13:03.982772220 +0200
+@@ -2,6 +2,7 @@
+ # Makefile for the kernel character device drivers.
+ #
+
++obj-m += frandom.o
+ obj-y += mem.o random.o
+ obj-$(CONFIG_TTY_PRINTK) += ttyprintk.o
+ obj-y += misc.o
+diff -Nur linux-4.1.3/drivers/cpufreq/imx6q-cpufreq.c linux-xbian-imx6/drivers/cpufreq/imx6q-cpufreq.c
+--- linux-4.1.3/drivers/cpufreq/imx6q-cpufreq.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/drivers/cpufreq/imx6q-cpufreq.c 2015-07-27 23:13:04.158146502 +0200
+@@ -20,6 +20,8 @@
+ #define PU_SOC_VOLTAGE_HIGH 1275000
+ #define FREQ_1P2_GHZ 1200000000
+
++extern int vpu352;
++
+ static struct regulator *arm_reg;
+ static struct regulator *pu_reg;
+ static struct regulator *soc_reg;
+@@ -251,6 +253,10 @@
+ unsigned long volt = be32_to_cpup(val++);
+ if (freq_table[j].frequency == freq) {
+ imx6_soc_volt[soc_opp_count++] = volt;
++ if (vpu352 && freq == 792000) {
++ pr_info("VPU352: increase SOC/PU voltage for VPU352MHz\n");
++ imx6_soc_volt[soc_opp_count-1] = 1250000;
++ }
+ break;
+ }
+ }
+diff -Nur linux-4.1.3/drivers/crypto/caam/caamalg.c linux-xbian-imx6/drivers/crypto/caam/caamalg.c
+--- linux-4.1.3/drivers/crypto/caam/caamalg.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/drivers/crypto/caam/caamalg.c 2015-07-27 23:13:04.205975852 +0200
+@@ -1,7 +1,7 @@
+ /*
+ * caam - Freescale FSL CAAM support for crypto API
+ *
+- * Copyright 2008-2011 Freescale Semiconductor, Inc.
++ * Copyright (C) 2008-2013 Freescale Semiconductor, Inc.
+ *
+ * Based on talitos crypto API driver.
+ *
+@@ -53,6 +53,7 @@
+ #include "error.h"
+ #include "sg_sw_sec4.h"
+ #include "key_gen.h"
++#include <linux/string.h>
+
+ /*
+ * crypto alg
+@@ -60,68 +61,42 @@
+ #define CAAM_CRA_PRIORITY 3000
+ /* max key is sum of AES_MAX_KEY_SIZE, max split key size */
+ #define CAAM_MAX_KEY_SIZE (AES_MAX_KEY_SIZE + \
+- CTR_RFC3686_NONCE_SIZE + \
+ SHA512_DIGEST_SIZE * 2)
+ /* max IV is max of AES_BLOCK_SIZE, DES3_EDE_BLOCK_SIZE */
+ #define CAAM_MAX_IV_LENGTH 16
+
+ /* length of descriptors text */
++#define DESC_JOB_IO_LEN (CAAM_CMD_SZ * 5 + CAAM_PTR_SZ * 3)
++
+ #define DESC_AEAD_BASE (4 * CAAM_CMD_SZ)
+-#define DESC_AEAD_ENC_LEN (DESC_AEAD_BASE + 15 * CAAM_CMD_SZ)
+-#define DESC_AEAD_DEC_LEN (DESC_AEAD_BASE + 18 * CAAM_CMD_SZ)
++#define DESC_AEAD_ENC_LEN (DESC_AEAD_BASE + 16 * CAAM_CMD_SZ)
++#define DESC_AEAD_DEC_LEN (DESC_AEAD_BASE + 21 * CAAM_CMD_SZ)
+ #define DESC_AEAD_GIVENC_LEN (DESC_AEAD_ENC_LEN + 7 * CAAM_CMD_SZ)
+
+-/* Note: Nonce is counted in enckeylen */
+-#define DESC_AEAD_CTR_RFC3686_LEN (6 * CAAM_CMD_SZ)
+-
+-#define DESC_AEAD_NULL_BASE (3 * CAAM_CMD_SZ)
+-#define DESC_AEAD_NULL_ENC_LEN (DESC_AEAD_NULL_BASE + 14 * CAAM_CMD_SZ)
+-#define DESC_AEAD_NULL_DEC_LEN (DESC_AEAD_NULL_BASE + 17 * CAAM_CMD_SZ)
+-
+-#define DESC_GCM_BASE (3 * CAAM_CMD_SZ)
+-#define DESC_GCM_ENC_LEN (DESC_GCM_BASE + 23 * CAAM_CMD_SZ)
+-#define DESC_GCM_DEC_LEN (DESC_GCM_BASE + 19 * CAAM_CMD_SZ)
+-
+-#define DESC_RFC4106_BASE (3 * CAAM_CMD_SZ)
+-#define DESC_RFC4106_ENC_LEN (DESC_RFC4106_BASE + 15 * CAAM_CMD_SZ)
+-#define DESC_RFC4106_DEC_LEN (DESC_RFC4106_BASE + 14 * CAAM_CMD_SZ)
+-#define DESC_RFC4106_GIVENC_LEN (DESC_RFC4106_BASE + 21 * CAAM_CMD_SZ)
+-
+-#define DESC_RFC4543_BASE (3 * CAAM_CMD_SZ)
+-#define DESC_RFC4543_ENC_LEN (DESC_RFC4543_BASE + 25 * CAAM_CMD_SZ)
+-#define DESC_RFC4543_DEC_LEN (DESC_RFC4543_BASE + 27 * CAAM_CMD_SZ)
+-#define DESC_RFC4543_GIVENC_LEN (DESC_RFC4543_BASE + 30 * CAAM_CMD_SZ)
+-
+ #define DESC_ABLKCIPHER_BASE (3 * CAAM_CMD_SZ)
+ #define DESC_ABLKCIPHER_ENC_LEN (DESC_ABLKCIPHER_BASE + \
+ 20 * CAAM_CMD_SZ)
+ #define DESC_ABLKCIPHER_DEC_LEN (DESC_ABLKCIPHER_BASE + \
+ 15 * CAAM_CMD_SZ)
+
+-#define DESC_MAX_USED_BYTES (DESC_RFC4543_GIVENC_LEN + \
++#define DESC_MAX_USED_BYTES (DESC_AEAD_GIVENC_LEN + \
+ CAAM_MAX_KEY_SIZE)
+ #define DESC_MAX_USED_LEN (DESC_MAX_USED_BYTES / CAAM_CMD_SZ)
+
+ #ifdef DEBUG
+ /* for print_hex_dumps with line references */
++#define xstr(s) str(s)
++#define str(s) #s
+ #define debug(format, arg...) printk(format, arg)
+ #else
+ #define debug(format, arg...)
+ #endif
+-static struct list_head alg_list;
+
+ /* Set DK bit in class 1 operation if shared */
+ static inline void append_dec_op1(u32 *desc, u32 type)
+ {
+ u32 *jump_cmd, *uncond_jump_cmd;
+
+- /* DK bit is valid only for AES */
+- if ((type & OP_ALG_ALGSEL_MASK) != OP_ALG_ALGSEL_AES) {
+- append_operation(desc, type | OP_ALG_AS_INITFINAL |
+- OP_ALG_DECRYPT);
+- return;
+- }
+-
+ jump_cmd = append_jump(desc, JUMP_TEST_ALL | JUMP_COND_SHRD);
+ append_operation(desc, type | OP_ALG_AS_INITFINAL |
+ OP_ALG_DECRYPT);
+@@ -133,26 +108,37 @@
+ }
+
+ /*
++ * Wait for completion of class 1 key loading before allowing
++ * error propagation
++ */
++static inline void append_dec_shr_done(u32 *desc)
++{
++ u32 *jump_cmd;
++
++ jump_cmd = append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TEST_ALL);
++ set_jump_tgt_here(desc, jump_cmd);
++ append_cmd(desc, SET_OK_NO_PROP_ERRORS | CMD_LOAD);
++}
++
++/*
+ * For aead functions, read payload and write payload,
+ * both of which are specified in req->src and req->dst
+ */
+ static inline void aead_append_src_dst(u32 *desc, u32 msg_type)
+ {
+- append_seq_fifo_store(desc, 0, FIFOST_TYPE_MESSAGE_DATA | KEY_VLF);
+ append_seq_fifo_load(desc, 0, FIFOLD_CLASS_BOTH |
+ KEY_VLF | msg_type | FIFOLD_TYPE_LASTBOTH);
++ append_seq_fifo_store(desc, 0, FIFOST_TYPE_MESSAGE_DATA | KEY_VLF);
+ }
+
+ /*
+ * For aead encrypt and decrypt, read iv for both classes
+ */
+-static inline void aead_append_ld_iv(u32 *desc, int ivsize, int ivoffset)
++static inline void aead_append_ld_iv(u32 *desc, int ivsize)
+ {
+- append_seq_load(desc, ivsize, LDST_CLASS_1_CCB |
+- LDST_SRCDST_BYTE_CONTEXT |
+- (ivoffset << LDST_OFFSET_SHIFT));
+- append_move(desc, MOVE_SRC_CLASS1CTX | MOVE_DEST_CLASS2INFIFO |
+- (ivoffset << MOVE_OFFSET_SHIFT) | ivsize);
++ append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_BYTE_CONTEXT |
++ LDST_CLASS_1_CCB | ivsize);
++ append_move(desc, MOVE_SRC_CLASS1CTX | MOVE_DEST_CLASS2INFIFO | ivsize);
+ }
+
+ /*
+@@ -198,309 +184,68 @@
+ };
+
+ static void append_key_aead(u32 *desc, struct caam_ctx *ctx,
+- int keys_fit_inline, bool is_rfc3686)
++ int keys_fit_inline)
+ {
+- u32 *nonce;
+- unsigned int enckeylen = ctx->enckeylen;
+-
+- /*
+- * RFC3686 specific:
+- * | ctx->key = {AUTH_KEY, ENC_KEY, NONCE}
+- * | enckeylen = encryption key size + nonce size
+- */
+- if (is_rfc3686)
+- enckeylen -= CTR_RFC3686_NONCE_SIZE;
+-
+ if (keys_fit_inline) {
+ append_key_as_imm(desc, ctx->key, ctx->split_key_pad_len,
+ ctx->split_key_len, CLASS_2 |
+ KEY_DEST_MDHA_SPLIT | KEY_ENC);
+ append_key_as_imm(desc, (void *)ctx->key +
+- ctx->split_key_pad_len, enckeylen,
+- enckeylen, CLASS_1 | KEY_DEST_CLASS_REG);
++ ctx->split_key_pad_len, ctx->enckeylen,
++ ctx->enckeylen, CLASS_1 | KEY_DEST_CLASS_REG);
+ } else {
+ append_key(desc, ctx->key_dma, ctx->split_key_len, CLASS_2 |
+ KEY_DEST_MDHA_SPLIT | KEY_ENC);
+ append_key(desc, ctx->key_dma + ctx->split_key_pad_len,
+- enckeylen, CLASS_1 | KEY_DEST_CLASS_REG);
+- }
+-
+- /* Load Counter into CONTEXT1 reg */
+- if (is_rfc3686) {
+- nonce = (u32 *)((void *)ctx->key + ctx->split_key_pad_len +
+- enckeylen);
+- append_load_imm_u32(desc, *nonce, LDST_CLASS_IND_CCB |
+- LDST_SRCDST_BYTE_OUTFIFO | LDST_IMM);
+- append_move(desc,
+- MOVE_SRC_OUTFIFO |
+- MOVE_DEST_CLASS1CTX |
+- (16 << MOVE_OFFSET_SHIFT) |
+- (CTR_RFC3686_NONCE_SIZE << MOVE_LEN_SHIFT));
++ ctx->enckeylen, CLASS_1 | KEY_DEST_CLASS_REG);
+ }
+ }
+
+ static void init_sh_desc_key_aead(u32 *desc, struct caam_ctx *ctx,
+- int keys_fit_inline, bool is_rfc3686)
++ int keys_fit_inline)
+ {
+ u32 *key_jump_cmd;
+
+- /* Note: Context registers are saved. */
+- init_sh_desc(desc, HDR_SHARE_SERIAL | HDR_SAVECTX);
+-
+- /* Skip if already shared */
+- key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
+- JUMP_COND_SHRD);
+-
+- append_key_aead(desc, ctx, keys_fit_inline, is_rfc3686);
+-
+- set_jump_tgt_here(desc, key_jump_cmd);
+-}
+-
+-static int aead_null_set_sh_desc(struct crypto_aead *aead)
+-{
+- struct aead_tfm *tfm = &aead->base.crt_aead;
+- struct caam_ctx *ctx = crypto_aead_ctx(aead);
+- struct device *jrdev = ctx->jrdev;
+- bool keys_fit_inline = false;
+- u32 *key_jump_cmd, *jump_cmd, *read_move_cmd, *write_move_cmd;
+- u32 *desc;
+-
+- /*
+- * Job Descriptor and Shared Descriptors
+- * must all fit into the 64-word Descriptor h/w Buffer
+- */
+- if (DESC_AEAD_NULL_ENC_LEN + DESC_JOB_IO_LEN +
+- ctx->split_key_pad_len <= CAAM_DESC_BYTES_MAX)
+- keys_fit_inline = true;
+-
+- /* aead_encrypt shared descriptor */
+- desc = ctx->sh_desc_enc;
+-
+ init_sh_desc(desc, HDR_SHARE_SERIAL);
+
+ /* Skip if already shared */
+ key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
+ JUMP_COND_SHRD);
+- if (keys_fit_inline)
+- append_key_as_imm(desc, ctx->key, ctx->split_key_pad_len,
+- ctx->split_key_len, CLASS_2 |
+- KEY_DEST_MDHA_SPLIT | KEY_ENC);
+- else
+- append_key(desc, ctx->key_dma, ctx->split_key_len, CLASS_2 |
+- KEY_DEST_MDHA_SPLIT | KEY_ENC);
+- set_jump_tgt_here(desc, key_jump_cmd);
+-
+- /* cryptlen = seqoutlen - authsize */
+- append_math_sub_imm_u32(desc, REG3, SEQOUTLEN, IMM, ctx->authsize);
+-
+- /*
+- * NULL encryption; IV is zero
+- * assoclen = (assoclen + cryptlen) - cryptlen
+- */
+- append_math_sub(desc, VARSEQINLEN, SEQINLEN, REG3, CAAM_CMD_SZ);
+-
+- /* read assoc before reading payload */
+- append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS2 | FIFOLD_TYPE_MSG |
+- KEY_VLF);
+-
+- /* Prepare to read and write cryptlen bytes */
+- append_math_add(desc, VARSEQINLEN, ZERO, REG3, CAAM_CMD_SZ);
+- append_math_add(desc, VARSEQOUTLEN, ZERO, REG3, CAAM_CMD_SZ);
+-
+- /*
+- * MOVE_LEN opcode is not available in all SEC HW revisions,
+- * thus need to do some magic, i.e. self-patch the descriptor
+- * buffer.
+- */
+- read_move_cmd = append_move(desc, MOVE_SRC_DESCBUF |
+- MOVE_DEST_MATH3 |
+- (0x6 << MOVE_LEN_SHIFT));
+- write_move_cmd = append_move(desc, MOVE_SRC_MATH3 |
+- MOVE_DEST_DESCBUF |
+- MOVE_WAITCOMP |
+- (0x8 << MOVE_LEN_SHIFT));
+-
+- /* Class 2 operation */
+- append_operation(desc, ctx->class2_alg_type |
+- OP_ALG_AS_INITFINAL | OP_ALG_ENCRYPT);
+-
+- /* Read and write cryptlen bytes */
+- aead_append_src_dst(desc, FIFOLD_TYPE_MSG | FIFOLD_TYPE_FLUSH1);
+-
+- set_move_tgt_here(desc, read_move_cmd);
+- set_move_tgt_here(desc, write_move_cmd);
+- append_cmd(desc, CMD_LOAD | DISABLE_AUTO_INFO_FIFO);
+- append_move(desc, MOVE_SRC_INFIFO_CL | MOVE_DEST_OUTFIFO |
+- MOVE_AUX_LS);
+-
+- /* Write ICV */
+- append_seq_store(desc, ctx->authsize, LDST_CLASS_2_CCB |
+- LDST_SRCDST_BYTE_CONTEXT);
+-
+- ctx->sh_desc_enc_dma = dma_map_single(jrdev, desc,
+- desc_bytes(desc),
+- DMA_TO_DEVICE);
+- if (dma_mapping_error(jrdev, ctx->sh_desc_enc_dma)) {
+- dev_err(jrdev, "unable to map shared descriptor\n");
+- return -ENOMEM;
+- }
+-#ifdef DEBUG
+- print_hex_dump(KERN_ERR,
+- "aead null enc shdesc@"__stringify(__LINE__)": ",
+- DUMP_PREFIX_ADDRESS, 16, 4, desc,
+- desc_bytes(desc), 1);
+-#endif
+-
+- /*
+- * Job Descriptor and Shared Descriptors
+- * must all fit into the 64-word Descriptor h/w Buffer
+- */
+- keys_fit_inline = false;
+- if (DESC_AEAD_NULL_DEC_LEN + DESC_JOB_IO_LEN +
+- ctx->split_key_pad_len <= CAAM_DESC_BYTES_MAX)
+- keys_fit_inline = true;
+-
+- desc = ctx->sh_desc_dec;
+
+- /* aead_decrypt shared descriptor */
+- init_sh_desc(desc, HDR_SHARE_SERIAL);
++ append_key_aead(desc, ctx, keys_fit_inline);
+
+- /* Skip if already shared */
+- key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
+- JUMP_COND_SHRD);
+- if (keys_fit_inline)
+- append_key_as_imm(desc, ctx->key, ctx->split_key_pad_len,
+- ctx->split_key_len, CLASS_2 |
+- KEY_DEST_MDHA_SPLIT | KEY_ENC);
+- else
+- append_key(desc, ctx->key_dma, ctx->split_key_len, CLASS_2 |
+- KEY_DEST_MDHA_SPLIT | KEY_ENC);
+ set_jump_tgt_here(desc, key_jump_cmd);
+
+- /* Class 2 operation */
+- append_operation(desc, ctx->class2_alg_type |
+- OP_ALG_AS_INITFINAL | OP_ALG_DECRYPT | OP_ALG_ICV_ON);
+-
+- /* assoclen + cryptlen = seqinlen - ivsize - authsize */
+- append_math_sub_imm_u32(desc, REG3, SEQINLEN, IMM,
+- ctx->authsize + tfm->ivsize);
+- /* assoclen = (assoclen + cryptlen) - cryptlen */
+- append_math_sub(desc, REG2, SEQOUTLEN, REG0, CAAM_CMD_SZ);
+- append_math_sub(desc, VARSEQINLEN, REG3, REG2, CAAM_CMD_SZ);
+-
+- /* read assoc before reading payload */
+- append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS2 | FIFOLD_TYPE_MSG |
+- KEY_VLF);
+-
+- /* Prepare to read and write cryptlen bytes */
+- append_math_add(desc, VARSEQINLEN, ZERO, REG2, CAAM_CMD_SZ);
+- append_math_add(desc, VARSEQOUTLEN, ZERO, REG2, CAAM_CMD_SZ);
+-
+- /*
+- * MOVE_LEN opcode is not available in all SEC HW revisions,
+- * thus need to do some magic, i.e. self-patch the descriptor
+- * buffer.
+- */
+- read_move_cmd = append_move(desc, MOVE_SRC_DESCBUF |
+- MOVE_DEST_MATH2 |
+- (0x6 << MOVE_LEN_SHIFT));
+- write_move_cmd = append_move(desc, MOVE_SRC_MATH2 |
+- MOVE_DEST_DESCBUF |
+- MOVE_WAITCOMP |
+- (0x8 << MOVE_LEN_SHIFT));
+-
+- /* Read and write cryptlen bytes */
+- aead_append_src_dst(desc, FIFOLD_TYPE_MSG | FIFOLD_TYPE_FLUSH1);
+-
+- /*
+- * Insert a NOP here, since we need at least 4 instructions between
+- * code patching the descriptor buffer and the location being patched.
+- */
+- jump_cmd = append_jump(desc, JUMP_TEST_ALL);
+- set_jump_tgt_here(desc, jump_cmd);
+-
+- set_move_tgt_here(desc, read_move_cmd);
+- set_move_tgt_here(desc, write_move_cmd);
+- append_cmd(desc, CMD_LOAD | DISABLE_AUTO_INFO_FIFO);
+- append_move(desc, MOVE_SRC_INFIFO_CL | MOVE_DEST_OUTFIFO |
+- MOVE_AUX_LS);
+- append_cmd(desc, CMD_LOAD | ENABLE_AUTO_INFO_FIFO);
+-
+- /* Load ICV */
+- append_seq_fifo_load(desc, ctx->authsize, FIFOLD_CLASS_CLASS2 |
+- FIFOLD_TYPE_LAST2 | FIFOLD_TYPE_ICV);
+-
+- ctx->sh_desc_dec_dma = dma_map_single(jrdev, desc,
+- desc_bytes(desc),
+- DMA_TO_DEVICE);
+- if (dma_mapping_error(jrdev, ctx->sh_desc_dec_dma)) {
+- dev_err(jrdev, "unable to map shared descriptor\n");
+- return -ENOMEM;
+- }
+-#ifdef DEBUG
+- print_hex_dump(KERN_ERR,
+- "aead null dec shdesc@"__stringify(__LINE__)": ",
+- DUMP_PREFIX_ADDRESS, 16, 4, desc,
+- desc_bytes(desc), 1);
+-#endif
+-
+- return 0;
++ /* Propagate errors from shared to job descriptor */
++ append_cmd(desc, SET_OK_NO_PROP_ERRORS | CMD_LOAD);
+ }
+
+ static int aead_set_sh_desc(struct crypto_aead *aead)
+ {
+ struct aead_tfm *tfm = &aead->base.crt_aead;
+ struct caam_ctx *ctx = crypto_aead_ctx(aead);
+- struct crypto_tfm *ctfm = crypto_aead_tfm(aead);
+- const char *alg_name = crypto_tfm_alg_name(ctfm);
+ struct device *jrdev = ctx->jrdev;
+- bool keys_fit_inline;
++ bool keys_fit_inline = false;
++ u32 *key_jump_cmd, *jump_cmd;
+ u32 geniv, moveiv;
+- u32 ctx1_iv_off = 0;
+ u32 *desc;
+- const bool ctr_mode = ((ctx->class1_alg_type & OP_ALG_AAI_MASK) ==
+- OP_ALG_AAI_CTR_MOD128);
+- const bool is_rfc3686 = (ctr_mode &&
+- (strstr(alg_name, "rfc3686") != NULL));
+
+- if (!ctx->authsize)
++ if (!ctx->enckeylen || !ctx->authsize)
+ return 0;
+
+- /* NULL encryption / decryption */
+- if (!ctx->enckeylen)
+- return aead_null_set_sh_desc(aead);
+-
+- /*
+- * AES-CTR needs to load IV in CONTEXT1 reg
+- * at an offset of 128bits (16bytes)
+- * CONTEXT1[255:128] = IV
+- */
+- if (ctr_mode)
+- ctx1_iv_off = 16;
+-
+- /*
+- * RFC3686 specific:
+- * CONTEXT1[255:128] = {NONCE, IV, COUNTER}
+- */
+- if (is_rfc3686)
+- ctx1_iv_off = 16 + CTR_RFC3686_NONCE_SIZE;
+-
+ /*
+ * Job Descriptor and Shared Descriptors
+ * must all fit into the 64-word Descriptor h/w Buffer
+ */
+- keys_fit_inline = false;
+ if (DESC_AEAD_ENC_LEN + DESC_JOB_IO_LEN +
+- ctx->split_key_pad_len + ctx->enckeylen +
+- (is_rfc3686 ? DESC_AEAD_CTR_RFC3686_LEN : 0) <=
++ ctx->split_key_pad_len + ctx->enckeylen <=
+ CAAM_DESC_BYTES_MAX)
+ keys_fit_inline = true;
+
+ /* aead_encrypt shared descriptor */
+ desc = ctx->sh_desc_enc;
+
+- /* Note: Context registers are saved. */
+- init_sh_desc_key_aead(desc, ctx, keys_fit_inline, is_rfc3686);
++ init_sh_desc_key_aead(desc, ctx, keys_fit_inline);
+
+ /* Class 2 operation */
+ append_operation(desc, ctx->class2_alg_type |
+@@ -512,21 +257,13 @@
+ /* assoclen + cryptlen = seqinlen - ivsize */
+ append_math_sub_imm_u32(desc, REG2, SEQINLEN, IMM, tfm->ivsize);
+
+- /* assoclen = (assoclen + cryptlen) - cryptlen */
++ /* assoclen + cryptlen = (assoclen + cryptlen) - cryptlen */
+ append_math_sub(desc, VARSEQINLEN, REG2, REG3, CAAM_CMD_SZ);
+
+ /* read assoc before reading payload */
+ append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS2 | FIFOLD_TYPE_MSG |
+ KEY_VLF);
+- aead_append_ld_iv(desc, tfm->ivsize, ctx1_iv_off);
+-
+- /* Load Counter into CONTEXT1 reg */
+- if (is_rfc3686)
+- append_load_imm_u32(desc, be32_to_cpu(1), LDST_IMM |
+- LDST_CLASS_1_CCB |
+- LDST_SRCDST_BYTE_CONTEXT |
+- ((ctx1_iv_off + CTR_RFC3686_IV_SIZE) <<
+- LDST_OFFSET_SHIFT));
++ aead_append_ld_iv(desc, tfm->ivsize);
+
+ /* Class 1 operation */
+ append_operation(desc, ctx->class1_alg_type |
+@@ -549,35 +286,46 @@
+ return -ENOMEM;
+ }
+ #ifdef DEBUG
+- print_hex_dump(KERN_ERR, "aead enc shdesc@"__stringify(__LINE__)": ",
++ print_hex_dump(KERN_ERR, "aead enc shdesc@"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, desc,
+ desc_bytes(desc), 1);
+ #endif
+
++ dma_sync_single_for_cpu(jrdev, ctx->sh_desc_enc_dma, desc_bytes(desc),
++ DMA_TO_DEVICE);
+ /*
+ * Job Descriptor and Shared Descriptors
+ * must all fit into the 64-word Descriptor h/w Buffer
+ */
+- keys_fit_inline = false;
+ if (DESC_AEAD_DEC_LEN + DESC_JOB_IO_LEN +
+- ctx->split_key_pad_len + ctx->enckeylen +
+- (is_rfc3686 ? DESC_AEAD_CTR_RFC3686_LEN : 0) <=
++ ctx->split_key_pad_len + ctx->enckeylen <=
+ CAAM_DESC_BYTES_MAX)
+ keys_fit_inline = true;
+
+- /* aead_decrypt shared descriptor */
+ desc = ctx->sh_desc_dec;
+
+- /* Note: Context registers are saved. */
+- init_sh_desc_key_aead(desc, ctx, keys_fit_inline, is_rfc3686);
++ /* aead_decrypt shared descriptor */
++ init_sh_desc(desc, HDR_SHARE_SERIAL);
++
++ /* Skip if already shared */
++ key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
++ JUMP_COND_SHRD);
++
++ append_key_aead(desc, ctx, keys_fit_inline);
++
++ /* Only propagate error immediately if shared */
++ jump_cmd = append_jump(desc, JUMP_TEST_ALL);
++ set_jump_tgt_here(desc, key_jump_cmd);
++ append_cmd(desc, SET_OK_NO_PROP_ERRORS | CMD_LOAD);
++ set_jump_tgt_here(desc, jump_cmd);
+
+ /* Class 2 operation */
+ append_operation(desc, ctx->class2_alg_type |
+ OP_ALG_AS_INITFINAL | OP_ALG_DECRYPT | OP_ALG_ICV_ON);
+
+- /* assoclen + cryptlen = seqinlen - ivsize - authsize */
++ /* assoclen + cryptlen = seqinlen - ivsize */
+ append_math_sub_imm_u32(desc, REG3, SEQINLEN, IMM,
+- ctx->authsize + tfm->ivsize);
++ ctx->authsize + tfm->ivsize)
+ /* assoclen = (assoclen + cryptlen) - cryptlen */
+ append_math_sub(desc, REG2, SEQOUTLEN, REG0, CAAM_CMD_SZ);
+ append_math_sub(desc, VARSEQINLEN, REG3, REG2, CAAM_CMD_SZ);
+@@ -586,22 +334,9 @@
+ append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS2 | FIFOLD_TYPE_MSG |
+ KEY_VLF);
+
+- aead_append_ld_iv(desc, tfm->ivsize, ctx1_iv_off);
++ aead_append_ld_iv(desc, tfm->ivsize);
+
+- /* Load Counter into CONTEXT1 reg */
+- if (is_rfc3686)
+- append_load_imm_u32(desc, be32_to_cpu(1), LDST_IMM |
+- LDST_CLASS_1_CCB |
+- LDST_SRCDST_BYTE_CONTEXT |
+- ((ctx1_iv_off + CTR_RFC3686_IV_SIZE) <<
+- LDST_OFFSET_SHIFT));
+-
+- /* Choose operation */
+- if (ctr_mode)
+- append_operation(desc, ctx->class1_alg_type |
+- OP_ALG_AS_INITFINAL | OP_ALG_DECRYPT);
+- else
+- append_dec_op1(desc, ctx->class1_alg_type);
++ append_dec_op1(desc, ctx->class1_alg_type);
+
+ /* Read and write cryptlen bytes */
+ append_math_add(desc, VARSEQINLEN, ZERO, REG2, CAAM_CMD_SZ);
+@@ -611,6 +346,7 @@
+ /* Load ICV */
+ append_seq_fifo_load(desc, ctx->authsize, FIFOLD_CLASS_CLASS2 |
+ FIFOLD_TYPE_LAST2 | FIFOLD_TYPE_ICV);
++ append_dec_shr_done(desc);
+
+ ctx->sh_desc_dec_dma = dma_map_single(jrdev, desc,
+ desc_bytes(desc),
+@@ -620,27 +356,26 @@
+ return -ENOMEM;
+ }
+ #ifdef DEBUG
+- print_hex_dump(KERN_ERR, "aead dec shdesc@"__stringify(__LINE__)": ",
++ print_hex_dump(KERN_ERR, "aead dec shdesc@"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, desc,
+ desc_bytes(desc), 1);
+ #endif
++ dma_sync_single_for_cpu(jrdev, ctx->sh_desc_dec_dma, desc_bytes(desc),
++ DMA_TO_DEVICE);
+
+ /*
+ * Job Descriptor and Shared Descriptors
+ * must all fit into the 64-word Descriptor h/w Buffer
+ */
+- keys_fit_inline = false;
+ if (DESC_AEAD_GIVENC_LEN + DESC_JOB_IO_LEN +
+- ctx->split_key_pad_len + ctx->enckeylen +
+- (is_rfc3686 ? DESC_AEAD_CTR_RFC3686_LEN : 0) <=
++ ctx->split_key_pad_len + ctx->enckeylen <=
+ CAAM_DESC_BYTES_MAX)
+ keys_fit_inline = true;
+
+ /* aead_givencrypt shared descriptor */
+ desc = ctx->sh_desc_givenc;
+
+- /* Note: Context registers are saved. */
+- init_sh_desc_key_aead(desc, ctx, keys_fit_inline, is_rfc3686);
++ init_sh_desc_key_aead(desc, ctx, keys_fit_inline);
+
+ /* Generate IV */
+ geniv = NFIFOENTRY_STYPE_PAD | NFIFOENTRY_DEST_DECO |
+@@ -649,16 +384,13 @@
+ append_load_imm_u32(desc, geniv, LDST_CLASS_IND_CCB |
+ LDST_SRCDST_WORD_INFO_FIFO | LDST_IMM);
+ append_cmd(desc, CMD_LOAD | DISABLE_AUTO_INFO_FIFO);
+- append_move(desc, MOVE_WAITCOMP |
+- MOVE_SRC_INFIFO | MOVE_DEST_CLASS1CTX |
+- (ctx1_iv_off << MOVE_OFFSET_SHIFT) |
+- (tfm->ivsize << MOVE_LEN_SHIFT));
++ append_move(desc, MOVE_SRC_INFIFO |
++ MOVE_DEST_CLASS1CTX | (tfm->ivsize << MOVE_LEN_SHIFT));
+ append_cmd(desc, CMD_LOAD | ENABLE_AUTO_INFO_FIFO);
+
+ /* Copy IV to class 1 context */
+- append_move(desc, MOVE_SRC_CLASS1CTX | MOVE_DEST_OUTFIFO |
+- (ctx1_iv_off << MOVE_OFFSET_SHIFT) |
+- (tfm->ivsize << MOVE_LEN_SHIFT));
++ append_move(desc, MOVE_SRC_CLASS1CTX |
++ MOVE_DEST_OUTFIFO | (tfm->ivsize << MOVE_LEN_SHIFT));
+
+ /* Return to encryption */
+ append_operation(desc, ctx->class2_alg_type |
+@@ -674,7 +406,7 @@
+ append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS2 | FIFOLD_TYPE_MSG |
+ KEY_VLF);
+
+- /* Copy iv from outfifo to class 2 fifo */
++ /* Copy iv from class 1 ctx to class 2 fifo*/
+ moveiv = NFIFOENTRY_STYPE_OFIFO | NFIFOENTRY_DEST_CLASS2 |
+ NFIFOENTRY_DTYPE_MSG | (tfm->ivsize << NFIFOENTRY_DLEN_SHIFT);
+ append_load_imm_u32(desc, moveiv, LDST_CLASS_IND_CCB |
+@@ -682,14 +414,6 @@
+ append_load_imm_u32(desc, tfm->ivsize, LDST_CLASS_2_CCB |
+ LDST_SRCDST_WORD_DATASZ_REG | LDST_IMM);
+
+- /* Load Counter into CONTEXT1 reg */
+- if (is_rfc3686)
+- append_load_imm_u32(desc, be32_to_cpu(1), LDST_IMM |
+- LDST_CLASS_1_CCB |
+- LDST_SRCDST_BYTE_CONTEXT |
+- ((ctx1_iv_off + CTR_RFC3686_IV_SIZE) <<
+- LDST_OFFSET_SHIFT));
+-
+ /* Class 1 operation */
+ append_operation(desc, ctx->class1_alg_type |
+ OP_ALG_AS_INITFINAL | OP_ALG_ENCRYPT);
+@@ -717,10 +441,12 @@
+ return -ENOMEM;
+ }
+ #ifdef DEBUG
+- print_hex_dump(KERN_ERR, "aead givenc shdesc@"__stringify(__LINE__)": ",
++ print_hex_dump(KERN_ERR, "aead givenc shdesc@"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, desc,
+ desc_bytes(desc), 1);
+ #endif
++ dma_sync_single_for_cpu(jrdev, ctx->sh_desc_givenc_dma,
++ desc_bytes(desc), DMA_TO_DEVICE);
+
+ return 0;
+ }
+@@ -736,977 +462,84 @@
+ return 0;
+ }
+
+-static int gcm_set_sh_desc(struct crypto_aead *aead)
++static u32 gen_split_aead_key(struct caam_ctx *ctx, const u8 *key_in,
++ u32 authkeylen)
+ {
+- struct aead_tfm *tfm = &aead->base.crt_aead;
++ return gen_split_key(ctx->jrdev, ctx->key, ctx->split_key_len,
++ ctx->split_key_pad_len, key_in, authkeylen,
++ ctx->alg_op);
++}
++
++static int aead_setkey(struct crypto_aead *aead,
++ const u8 *key, unsigned int keylen)
++{
++ /* Sizes for MDHA pads (*not* keys): MD5, SHA1, 224, 256, 384, 512 */
++ static const u8 mdpadlen[] = { 16, 20, 32, 32, 64, 64 };
+ struct caam_ctx *ctx = crypto_aead_ctx(aead);
+ struct device *jrdev = ctx->jrdev;
+- bool keys_fit_inline = false;
+- u32 *key_jump_cmd, *zero_payload_jump_cmd,
+- *zero_assoc_jump_cmd1, *zero_assoc_jump_cmd2;
+- u32 *desc;
+-
+- if (!ctx->enckeylen || !ctx->authsize)
+- return 0;
+-
+- /*
+- * AES GCM encrypt shared descriptor
+- * Job Descriptor and Shared Descriptor
+- * must fit into the 64-word Descriptor h/w Buffer
+- */
+- if (DESC_GCM_ENC_LEN + DESC_JOB_IO_LEN +
+- ctx->enckeylen <= CAAM_DESC_BYTES_MAX)
+- keys_fit_inline = true;
++ struct rtattr *rta = (void *)key;
++ struct crypto_authenc_key_param *param;
++ unsigned int authkeylen;
++ unsigned int enckeylen;
++ int ret = 0;
+
+- desc = ctx->sh_desc_enc;
++ param = RTA_DATA(rta);
++ enckeylen = be32_to_cpu(param->enckeylen);
+
+- init_sh_desc(desc, HDR_SHARE_SERIAL);
++ key += RTA_ALIGN(rta->rta_len);
++ keylen -= RTA_ALIGN(rta->rta_len);
+
+- /* skip key loading if they are loaded due to sharing */
+- key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
+- JUMP_COND_SHRD | JUMP_COND_SELF);
+- if (keys_fit_inline)
+- append_key_as_imm(desc, (void *)ctx->key, ctx->enckeylen,
+- ctx->enckeylen, CLASS_1 | KEY_DEST_CLASS_REG);
+- else
+- append_key(desc, ctx->key_dma, ctx->enckeylen,
+- CLASS_1 | KEY_DEST_CLASS_REG);
+- set_jump_tgt_here(desc, key_jump_cmd);
++ if (keylen < enckeylen)
++ goto badkey;
+
+- /* class 1 operation */
+- append_operation(desc, ctx->class1_alg_type |
+- OP_ALG_AS_INITFINAL | OP_ALG_ENCRYPT);
++ authkeylen = keylen - enckeylen;
+
+- /* cryptlen = seqoutlen - authsize */
+- append_math_sub_imm_u32(desc, REG3, SEQOUTLEN, IMM, ctx->authsize);
++ if (keylen > CAAM_MAX_KEY_SIZE)
++ goto badkey;
+
+- /* assoclen + cryptlen = seqinlen - ivsize */
+- append_math_sub_imm_u32(desc, REG2, SEQINLEN, IMM, tfm->ivsize);
++ /* Pick class 2 key length from algorithm submask */
++ ctx->split_key_len = mdpadlen[(ctx->alg_op & OP_ALG_ALGSEL_SUBMASK) >>
++ OP_ALG_ALGSEL_SHIFT] * 2;
++ ctx->split_key_pad_len = ALIGN(ctx->split_key_len, 16);
+
+- /* assoclen = (assoclen + cryptlen) - cryptlen */
+- append_math_sub(desc, REG1, REG2, REG3, CAAM_CMD_SZ);
++#ifdef DEBUG
++ printk(KERN_ERR "keylen %d enckeylen %d authkeylen %d\n",
++ keylen, enckeylen, authkeylen);
++ printk(KERN_ERR "split_key_len %d split_key_pad_len %d\n",
++ ctx->split_key_len, ctx->split_key_pad_len);
++ print_hex_dump(KERN_ERR, "key in @"xstr(__LINE__)": ",
++ DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
++#endif
+
+- /* if cryptlen is ZERO jump to zero-payload commands */
+- append_math_add(desc, VARSEQOUTLEN, ZERO, REG3, CAAM_CMD_SZ);
+- zero_payload_jump_cmd = append_jump(desc, JUMP_TEST_ALL |
+- JUMP_COND_MATH_Z);
+- /* read IV */
+- append_seq_fifo_load(desc, tfm->ivsize, FIFOLD_CLASS_CLASS1 |
+- FIFOLD_TYPE_IV | FIFOLD_TYPE_FLUSH1);
+-
+- /* if assoclen is ZERO, skip reading the assoc data */
+- append_math_add(desc, VARSEQINLEN, ZERO, REG1, CAAM_CMD_SZ);
+- zero_assoc_jump_cmd1 = append_jump(desc, JUMP_TEST_ALL |
+- JUMP_COND_MATH_Z);
+-
+- /* read assoc data */
+- append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLDST_VLF |
+- FIFOLD_TYPE_AAD | FIFOLD_TYPE_FLUSH1);
+- set_jump_tgt_here(desc, zero_assoc_jump_cmd1);
++ ret = gen_split_aead_key(ctx, key, authkeylen);
++ if (ret) {
++ goto badkey;
++ }
+
+- append_math_add(desc, VARSEQINLEN, ZERO, REG3, CAAM_CMD_SZ);
++ /* postpend encryption key to auth split key */
++ memcpy(ctx->key + ctx->split_key_pad_len, key + authkeylen, enckeylen);
+
+- /* write encrypted data */
+- append_seq_fifo_store(desc, 0, FIFOST_TYPE_MESSAGE_DATA | FIFOLDST_VLF);
++ ctx->key_dma = dma_map_single(jrdev, ctx->key, ctx->split_key_pad_len +
++ enckeylen, DMA_TO_DEVICE);
++ if (dma_mapping_error(jrdev, ctx->key_dma)) {
++ dev_err(jrdev, "unable to map key i/o memory\n");
++ return -ENOMEM;
++ }
++#ifdef DEBUG
++ print_hex_dump(KERN_ERR, "ctx.key@"xstr(__LINE__)": ",
++ DUMP_PREFIX_ADDRESS, 16, 4, ctx->key,
++ ctx->split_key_pad_len + enckeylen, 1);
++#endif
++ dma_sync_single_for_device(jrdev, ctx->key_dma,
++ ctx->split_key_pad_len + enckeylen,
++ DMA_TO_DEVICE);
+
+- /* read payload data */
+- append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLDST_VLF |
+- FIFOLD_TYPE_MSG | FIFOLD_TYPE_LAST1);
+-
+- /* jump the zero-payload commands */
+- append_jump(desc, JUMP_TEST_ALL | 7);
+-
+- /* zero-payload commands */
+- set_jump_tgt_here(desc, zero_payload_jump_cmd);
+-
+- /* if assoclen is ZERO, jump to IV reading - is the only input data */
+- append_math_add(desc, VARSEQINLEN, ZERO, REG1, CAAM_CMD_SZ);
+- zero_assoc_jump_cmd2 = append_jump(desc, JUMP_TEST_ALL |
+- JUMP_COND_MATH_Z);
+- /* read IV */
+- append_seq_fifo_load(desc, tfm->ivsize, FIFOLD_CLASS_CLASS1 |
+- FIFOLD_TYPE_IV | FIFOLD_TYPE_FLUSH1);
+-
+- /* read assoc data */
+- append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLDST_VLF |
+- FIFOLD_TYPE_AAD | FIFOLD_TYPE_LAST1);
+-
+- /* jump to ICV writing */
+- append_jump(desc, JUMP_TEST_ALL | 2);
+-
+- /* read IV - is the only input data */
+- set_jump_tgt_here(desc, zero_assoc_jump_cmd2);
+- append_seq_fifo_load(desc, tfm->ivsize, FIFOLD_CLASS_CLASS1 |
+- FIFOLD_TYPE_IV | FIFOLD_TYPE_FLUSH1 |
+- FIFOLD_TYPE_LAST1);
+-
+- /* write ICV */
+- append_seq_store(desc, ctx->authsize, LDST_CLASS_1_CCB |
+- LDST_SRCDST_BYTE_CONTEXT);
+-
+- ctx->sh_desc_enc_dma = dma_map_single(jrdev, desc,
+- desc_bytes(desc),
+- DMA_TO_DEVICE);
+- if (dma_mapping_error(jrdev, ctx->sh_desc_enc_dma)) {
+- dev_err(jrdev, "unable to map shared descriptor\n");
+- return -ENOMEM;
+- }
+-#ifdef DEBUG
+- print_hex_dump(KERN_ERR, "gcm enc shdesc@"__stringify(__LINE__)": ",
+- DUMP_PREFIX_ADDRESS, 16, 4, desc,
+- desc_bytes(desc), 1);
+-#endif
+-
+- /*
+- * Job Descriptor and Shared Descriptors
+- * must all fit into the 64-word Descriptor h/w Buffer
+- */
+- keys_fit_inline = false;
+- if (DESC_GCM_DEC_LEN + DESC_JOB_IO_LEN +
+- ctx->enckeylen <= CAAM_DESC_BYTES_MAX)
+- keys_fit_inline = true;
+-
+- desc = ctx->sh_desc_dec;
+-
+- init_sh_desc(desc, HDR_SHARE_SERIAL);
+-
+- /* skip key loading if they are loaded due to sharing */
+- key_jump_cmd = append_jump(desc, JUMP_JSL |
+- JUMP_TEST_ALL | JUMP_COND_SHRD |
+- JUMP_COND_SELF);
+- if (keys_fit_inline)
+- append_key_as_imm(desc, (void *)ctx->key, ctx->enckeylen,
+- ctx->enckeylen, CLASS_1 | KEY_DEST_CLASS_REG);
+- else
+- append_key(desc, ctx->key_dma, ctx->enckeylen,
+- CLASS_1 | KEY_DEST_CLASS_REG);
+- set_jump_tgt_here(desc, key_jump_cmd);
+-
+- /* class 1 operation */
+- append_operation(desc, ctx->class1_alg_type |
+- OP_ALG_AS_INITFINAL | OP_ALG_DECRYPT | OP_ALG_ICV_ON);
+-
+- /* assoclen + cryptlen = seqinlen - ivsize - icvsize */
+- append_math_sub_imm_u32(desc, REG3, SEQINLEN, IMM,
+- ctx->authsize + tfm->ivsize);
+-
+- /* assoclen = (assoclen + cryptlen) - cryptlen */
+- append_math_sub(desc, REG2, SEQOUTLEN, REG0, CAAM_CMD_SZ);
+- append_math_sub(desc, REG1, REG3, REG2, CAAM_CMD_SZ);
+-
+- /* read IV */
+- append_seq_fifo_load(desc, tfm->ivsize, FIFOLD_CLASS_CLASS1 |
+- FIFOLD_TYPE_IV | FIFOLD_TYPE_FLUSH1);
+-
+- /* jump to zero-payload command if cryptlen is zero */
+- append_math_add(desc, VARSEQOUTLEN, ZERO, REG2, CAAM_CMD_SZ);
+- zero_payload_jump_cmd = append_jump(desc, JUMP_TEST_ALL |
+- JUMP_COND_MATH_Z);
+-
+- append_math_add(desc, VARSEQINLEN, ZERO, REG1, CAAM_CMD_SZ);
+- /* if asoclen is ZERO, skip reading assoc data */
+- zero_assoc_jump_cmd1 = append_jump(desc, JUMP_TEST_ALL |
+- JUMP_COND_MATH_Z);
+- /* read assoc data */
+- append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLDST_VLF |
+- FIFOLD_TYPE_AAD | FIFOLD_TYPE_FLUSH1);
+- set_jump_tgt_here(desc, zero_assoc_jump_cmd1);
+-
+- append_math_add(desc, VARSEQINLEN, ZERO, REG2, CAAM_CMD_SZ);
+-
+- /* store encrypted data */
+- append_seq_fifo_store(desc, 0, FIFOST_TYPE_MESSAGE_DATA | FIFOLDST_VLF);
+-
+- /* read payload data */
+- append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLDST_VLF |
+- FIFOLD_TYPE_MSG | FIFOLD_TYPE_FLUSH1);
+-
+- /* jump the zero-payload commands */
+- append_jump(desc, JUMP_TEST_ALL | 4);
+-
+- /* zero-payload command */
+- set_jump_tgt_here(desc, zero_payload_jump_cmd);
+-
+- /* if assoclen is ZERO, jump to ICV reading */
+- append_math_add(desc, VARSEQINLEN, ZERO, REG1, CAAM_CMD_SZ);
+- zero_assoc_jump_cmd2 = append_jump(desc, JUMP_TEST_ALL |
+- JUMP_COND_MATH_Z);
+- /* read assoc data */
+- append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLDST_VLF |
+- FIFOLD_TYPE_AAD | FIFOLD_TYPE_FLUSH1);
+- set_jump_tgt_here(desc, zero_assoc_jump_cmd2);
+-
+- /* read ICV */
+- append_seq_fifo_load(desc, ctx->authsize, FIFOLD_CLASS_CLASS1 |
+- FIFOLD_TYPE_ICV | FIFOLD_TYPE_LAST1);
+-
+- ctx->sh_desc_dec_dma = dma_map_single(jrdev, desc,
+- desc_bytes(desc),
+- DMA_TO_DEVICE);
+- if (dma_mapping_error(jrdev, ctx->sh_desc_dec_dma)) {
+- dev_err(jrdev, "unable to map shared descriptor\n");
+- return -ENOMEM;
+- }
+-#ifdef DEBUG
+- print_hex_dump(KERN_ERR, "gcm dec shdesc@"__stringify(__LINE__)": ",
+- DUMP_PREFIX_ADDRESS, 16, 4, desc,
+- desc_bytes(desc), 1);
+-#endif
+-
+- return 0;
+-}
+-
+-static int gcm_setauthsize(struct crypto_aead *authenc, unsigned int authsize)
+-{
+- struct caam_ctx *ctx = crypto_aead_ctx(authenc);
+-
+- ctx->authsize = authsize;
+- gcm_set_sh_desc(authenc);
+-
+- return 0;
+-}
+-
+-static int rfc4106_set_sh_desc(struct crypto_aead *aead)
+-{
+- struct aead_tfm *tfm = &aead->base.crt_aead;
+- struct caam_ctx *ctx = crypto_aead_ctx(aead);
+- struct device *jrdev = ctx->jrdev;
+- bool keys_fit_inline = false;
+- u32 *key_jump_cmd, *move_cmd, *write_iv_cmd;
+- u32 *desc;
+- u32 geniv;
+-
+- if (!ctx->enckeylen || !ctx->authsize)
+- return 0;
+-
+- /*
+- * RFC4106 encrypt shared descriptor
+- * Job Descriptor and Shared Descriptor
+- * must fit into the 64-word Descriptor h/w Buffer
+- */
+- if (DESC_RFC4106_ENC_LEN + DESC_JOB_IO_LEN +
+- ctx->enckeylen <= CAAM_DESC_BYTES_MAX)
+- keys_fit_inline = true;
+-
+- desc = ctx->sh_desc_enc;
+-
+- init_sh_desc(desc, HDR_SHARE_SERIAL);
+-
+- /* Skip key loading if it is loaded due to sharing */
+- key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
+- JUMP_COND_SHRD);
+- if (keys_fit_inline)
+- append_key_as_imm(desc, (void *)ctx->key, ctx->enckeylen,
+- ctx->enckeylen, CLASS_1 | KEY_DEST_CLASS_REG);
+- else
+- append_key(desc, ctx->key_dma, ctx->enckeylen,
+- CLASS_1 | KEY_DEST_CLASS_REG);
+- set_jump_tgt_here(desc, key_jump_cmd);
+-
+- /* Class 1 operation */
+- append_operation(desc, ctx->class1_alg_type |
+- OP_ALG_AS_INITFINAL | OP_ALG_ENCRYPT);
+-
+- /* cryptlen = seqoutlen - authsize */
+- append_math_sub_imm_u32(desc, REG3, SEQOUTLEN, IMM, ctx->authsize);
+- append_math_add(desc, VARSEQOUTLEN, ZERO, REG3, CAAM_CMD_SZ);
+-
+- /* assoclen + cryptlen = seqinlen - ivsize */
+- append_math_sub_imm_u32(desc, REG2, SEQINLEN, IMM, tfm->ivsize);
+-
+- /* assoclen = (assoclen + cryptlen) - cryptlen */
+- append_math_sub(desc, VARSEQINLEN, REG2, REG3, CAAM_CMD_SZ);
+-
+- /* Read Salt */
+- append_fifo_load_as_imm(desc, (void *)(ctx->key + ctx->enckeylen),
+- 4, FIFOLD_CLASS_CLASS1 | FIFOLD_TYPE_IV);
+- /* Read AES-GCM-ESP IV */
+- append_seq_fifo_load(desc, tfm->ivsize, FIFOLD_CLASS_CLASS1 |
+- FIFOLD_TYPE_IV | FIFOLD_TYPE_FLUSH1);
+-
+- /* Read assoc data */
+- append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLDST_VLF |
+- FIFOLD_TYPE_AAD | FIFOLD_TYPE_FLUSH1);
+-
+- /* Will read cryptlen bytes */
+- append_math_add(desc, VARSEQINLEN, ZERO, REG3, CAAM_CMD_SZ);
+-
+- /* Write encrypted data */
+- append_seq_fifo_store(desc, 0, FIFOST_TYPE_MESSAGE_DATA | FIFOLDST_VLF);
+-
+- /* Read payload data */
+- append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLDST_VLF |
+- FIFOLD_TYPE_MSG | FIFOLD_TYPE_LAST1);
+-
+- /* Write ICV */
+- append_seq_store(desc, ctx->authsize, LDST_CLASS_1_CCB |
+- LDST_SRCDST_BYTE_CONTEXT);
+-
+- ctx->sh_desc_enc_dma = dma_map_single(jrdev, desc,
+- desc_bytes(desc),
+- DMA_TO_DEVICE);
+- if (dma_mapping_error(jrdev, ctx->sh_desc_enc_dma)) {
+- dev_err(jrdev, "unable to map shared descriptor\n");
+- return -ENOMEM;
+- }
+-#ifdef DEBUG
+- print_hex_dump(KERN_ERR, "rfc4106 enc shdesc@"__stringify(__LINE__)": ",
+- DUMP_PREFIX_ADDRESS, 16, 4, desc,
+- desc_bytes(desc), 1);
+-#endif
+-
+- /*
+- * Job Descriptor and Shared Descriptors
+- * must all fit into the 64-word Descriptor h/w Buffer
+- */
+- keys_fit_inline = false;
+- if (DESC_RFC4106_DEC_LEN + DESC_JOB_IO_LEN +
+- ctx->enckeylen <= CAAM_DESC_BYTES_MAX)
+- keys_fit_inline = true;
+-
+- desc = ctx->sh_desc_dec;
+-
+- init_sh_desc(desc, HDR_SHARE_SERIAL);
+-
+- /* Skip key loading if it is loaded due to sharing */
+- key_jump_cmd = append_jump(desc, JUMP_JSL |
+- JUMP_TEST_ALL | JUMP_COND_SHRD);
+- if (keys_fit_inline)
+- append_key_as_imm(desc, (void *)ctx->key, ctx->enckeylen,
+- ctx->enckeylen, CLASS_1 | KEY_DEST_CLASS_REG);
+- else
+- append_key(desc, ctx->key_dma, ctx->enckeylen,
+- CLASS_1 | KEY_DEST_CLASS_REG);
+- set_jump_tgt_here(desc, key_jump_cmd);
+-
+- /* Class 1 operation */
+- append_operation(desc, ctx->class1_alg_type |
+- OP_ALG_AS_INITFINAL | OP_ALG_DECRYPT | OP_ALG_ICV_ON);
+-
+- /* assoclen + cryptlen = seqinlen - ivsize - icvsize */
+- append_math_sub_imm_u32(desc, REG3, SEQINLEN, IMM,
+- ctx->authsize + tfm->ivsize);
+-
+- /* assoclen = (assoclen + cryptlen) - cryptlen */
+- append_math_sub(desc, REG2, SEQOUTLEN, REG0, CAAM_CMD_SZ);
+- append_math_sub(desc, VARSEQINLEN, REG3, REG2, CAAM_CMD_SZ);
+-
+- /* Will write cryptlen bytes */
+- append_math_sub(desc, VARSEQOUTLEN, SEQOUTLEN, REG0, CAAM_CMD_SZ);
+-
+- /* Read Salt */
+- append_fifo_load_as_imm(desc, (void *)(ctx->key + ctx->enckeylen),
+- 4, FIFOLD_CLASS_CLASS1 | FIFOLD_TYPE_IV);
+- /* Read AES-GCM-ESP IV */
+- append_seq_fifo_load(desc, tfm->ivsize, FIFOLD_CLASS_CLASS1 |
+- FIFOLD_TYPE_IV | FIFOLD_TYPE_FLUSH1);
+-
+- /* Read assoc data */
+- append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLDST_VLF |
+- FIFOLD_TYPE_AAD | FIFOLD_TYPE_FLUSH1);
+-
+- /* Will read cryptlen bytes */
+- append_math_add(desc, VARSEQINLEN, ZERO, REG2, CAAM_CMD_SZ);
+-
+- /* Store payload data */
+- append_seq_fifo_store(desc, 0, FIFOST_TYPE_MESSAGE_DATA | FIFOLDST_VLF);
+-
+- /* Read encrypted data */
+- append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLDST_VLF |
+- FIFOLD_TYPE_MSG | FIFOLD_TYPE_FLUSH1);
+-
+- /* Read ICV */
+- append_seq_fifo_load(desc, ctx->authsize, FIFOLD_CLASS_CLASS1 |
+- FIFOLD_TYPE_ICV | FIFOLD_TYPE_LAST1);
+-
+- ctx->sh_desc_dec_dma = dma_map_single(jrdev, desc,
+- desc_bytes(desc),
+- DMA_TO_DEVICE);
+- if (dma_mapping_error(jrdev, ctx->sh_desc_dec_dma)) {
+- dev_err(jrdev, "unable to map shared descriptor\n");
+- return -ENOMEM;
+- }
+-#ifdef DEBUG
+- print_hex_dump(KERN_ERR, "rfc4106 dec shdesc@"__stringify(__LINE__)": ",
+- DUMP_PREFIX_ADDRESS, 16, 4, desc,
+- desc_bytes(desc), 1);
+-#endif
+-
+- /*
+- * Job Descriptor and Shared Descriptors
+- * must all fit into the 64-word Descriptor h/w Buffer
+- */
+- keys_fit_inline = false;
+- if (DESC_RFC4106_GIVENC_LEN + DESC_JOB_IO_LEN +
+- ctx->split_key_pad_len + ctx->enckeylen <=
+- CAAM_DESC_BYTES_MAX)
+- keys_fit_inline = true;
+-
+- /* rfc4106_givencrypt shared descriptor */
+- desc = ctx->sh_desc_givenc;
+-
+- init_sh_desc(desc, HDR_SHARE_SERIAL);
+-
+- /* Skip key loading if it is loaded due to sharing */
+- key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
+- JUMP_COND_SHRD);
+- if (keys_fit_inline)
+- append_key_as_imm(desc, (void *)ctx->key, ctx->enckeylen,
+- ctx->enckeylen, CLASS_1 | KEY_DEST_CLASS_REG);
+- else
+- append_key(desc, ctx->key_dma, ctx->enckeylen,
+- CLASS_1 | KEY_DEST_CLASS_REG);
+- set_jump_tgt_here(desc, key_jump_cmd);
+-
+- /* Generate IV */
+- geniv = NFIFOENTRY_STYPE_PAD | NFIFOENTRY_DEST_DECO |
+- NFIFOENTRY_DTYPE_MSG | NFIFOENTRY_LC1 |
+- NFIFOENTRY_PTYPE_RND | (tfm->ivsize << NFIFOENTRY_DLEN_SHIFT);
+- append_load_imm_u32(desc, geniv, LDST_CLASS_IND_CCB |
+- LDST_SRCDST_WORD_INFO_FIFO | LDST_IMM);
+- append_cmd(desc, CMD_LOAD | DISABLE_AUTO_INFO_FIFO);
+- move_cmd = append_move(desc, MOVE_SRC_INFIFO | MOVE_DEST_DESCBUF |
+- (tfm->ivsize << MOVE_LEN_SHIFT));
+- append_cmd(desc, CMD_LOAD | ENABLE_AUTO_INFO_FIFO);
+-
+- /* Copy generated IV to OFIFO */
+- write_iv_cmd = append_move(desc, MOVE_SRC_DESCBUF | MOVE_DEST_OUTFIFO |
+- (tfm->ivsize << MOVE_LEN_SHIFT));
+-
+- /* Class 1 operation */
+- append_operation(desc, ctx->class1_alg_type |
+- OP_ALG_AS_INITFINAL | OP_ALG_ENCRYPT);
+-
+- /* ivsize + cryptlen = seqoutlen - authsize */
+- append_math_sub_imm_u32(desc, REG3, SEQOUTLEN, IMM, ctx->authsize);
+-
+- /* assoclen = seqinlen - (ivsize + cryptlen) */
+- append_math_sub(desc, VARSEQINLEN, SEQINLEN, REG3, CAAM_CMD_SZ);
+-
+- /* Will write ivsize + cryptlen */
+- append_math_add(desc, VARSEQOUTLEN, REG3, REG0, CAAM_CMD_SZ);
+-
+- /* Read Salt and generated IV */
+- append_cmd(desc, CMD_FIFO_LOAD | FIFOLD_CLASS_CLASS1 | FIFOLD_TYPE_IV |
+- FIFOLD_TYPE_FLUSH1 | IMMEDIATE | 12);
+- /* Append Salt */
+- append_data(desc, (void *)(ctx->key + ctx->enckeylen), 4);
+- set_move_tgt_here(desc, move_cmd);
+- set_move_tgt_here(desc, write_iv_cmd);
+- /* Blank commands. Will be overwritten by generated IV. */
+- append_cmd(desc, 0x00000000);
+- append_cmd(desc, 0x00000000);
+- /* End of blank commands */
+-
+- /* No need to reload iv */
+- append_seq_fifo_load(desc, tfm->ivsize, FIFOLD_CLASS_SKIP);
+-
+- /* Read assoc data */
+- append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLDST_VLF |
+- FIFOLD_TYPE_AAD | FIFOLD_TYPE_FLUSH1);
+-
+- /* Will read cryptlen */
+- append_math_add(desc, VARSEQINLEN, SEQINLEN, REG0, CAAM_CMD_SZ);
+-
+- /* Store generated IV and encrypted data */
+- append_seq_fifo_store(desc, 0, FIFOST_TYPE_MESSAGE_DATA | FIFOLDST_VLF);
+-
+- /* Read payload data */
+- append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLDST_VLF |
+- FIFOLD_TYPE_MSG | FIFOLD_TYPE_LAST1);
+-
+- /* Write ICV */
+- append_seq_store(desc, ctx->authsize, LDST_CLASS_1_CCB |
+- LDST_SRCDST_BYTE_CONTEXT);
+-
+- ctx->sh_desc_givenc_dma = dma_map_single(jrdev, desc,
+- desc_bytes(desc),
+- DMA_TO_DEVICE);
+- if (dma_mapping_error(jrdev, ctx->sh_desc_givenc_dma)) {
+- dev_err(jrdev, "unable to map shared descriptor\n");
+- return -ENOMEM;
+- }
+-#ifdef DEBUG
+- print_hex_dump(KERN_ERR,
+- "rfc4106 givenc shdesc@"__stringify(__LINE__)": ",
+- DUMP_PREFIX_ADDRESS, 16, 4, desc,
+- desc_bytes(desc), 1);
+-#endif
+-
+- return 0;
+-}
+-
+-static int rfc4106_setauthsize(struct crypto_aead *authenc,
+- unsigned int authsize)
+-{
+- struct caam_ctx *ctx = crypto_aead_ctx(authenc);
+-
+- ctx->authsize = authsize;
+- rfc4106_set_sh_desc(authenc);
+-
+- return 0;
+-}
+-
+-static int rfc4543_set_sh_desc(struct crypto_aead *aead)
+-{
+- struct aead_tfm *tfm = &aead->base.crt_aead;
+- struct caam_ctx *ctx = crypto_aead_ctx(aead);
+- struct device *jrdev = ctx->jrdev;
+- bool keys_fit_inline = false;
+- u32 *key_jump_cmd, *write_iv_cmd, *write_aad_cmd;
+- u32 *read_move_cmd, *write_move_cmd;
+- u32 *desc;
+- u32 geniv;
+-
+- if (!ctx->enckeylen || !ctx->authsize)
+- return 0;
+-
+- /*
+- * RFC4543 encrypt shared descriptor
+- * Job Descriptor and Shared Descriptor
+- * must fit into the 64-word Descriptor h/w Buffer
+- */
+- if (DESC_RFC4543_ENC_LEN + DESC_JOB_IO_LEN +
+- ctx->enckeylen <= CAAM_DESC_BYTES_MAX)
+- keys_fit_inline = true;
+-
+- desc = ctx->sh_desc_enc;
+-
+- init_sh_desc(desc, HDR_SHARE_SERIAL);
+-
+- /* Skip key loading if it is loaded due to sharing */
+- key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
+- JUMP_COND_SHRD);
+- if (keys_fit_inline)
+- append_key_as_imm(desc, (void *)ctx->key, ctx->enckeylen,
+- ctx->enckeylen, CLASS_1 | KEY_DEST_CLASS_REG);
+- else
+- append_key(desc, ctx->key_dma, ctx->enckeylen,
+- CLASS_1 | KEY_DEST_CLASS_REG);
+- set_jump_tgt_here(desc, key_jump_cmd);
+-
+- /* Class 1 operation */
+- append_operation(desc, ctx->class1_alg_type |
+- OP_ALG_AS_INITFINAL | OP_ALG_ENCRYPT);
+-
+- /* Load AES-GMAC ESP IV into Math1 register */
+- append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_WORD_DECO_MATH1 |
+- LDST_CLASS_DECO | tfm->ivsize);
+-
+- /* Wait the DMA transaction to finish */
+- append_jump(desc, JUMP_TEST_ALL | JUMP_COND_CALM |
+- (1 << JUMP_OFFSET_SHIFT));
+-
+- /* Overwrite blank immediate AES-GMAC ESP IV data */
+- write_iv_cmd = append_move(desc, MOVE_SRC_MATH1 | MOVE_DEST_DESCBUF |
+- (tfm->ivsize << MOVE_LEN_SHIFT));
+-
+- /* Overwrite blank immediate AAD data */
+- write_aad_cmd = append_move(desc, MOVE_SRC_MATH1 | MOVE_DEST_DESCBUF |
+- (tfm->ivsize << MOVE_LEN_SHIFT));
+-
+- /* cryptlen = seqoutlen - authsize */
+- append_math_sub_imm_u32(desc, REG3, SEQOUTLEN, IMM, ctx->authsize);
+-
+- /* assoclen = (seqinlen - ivsize) - cryptlen */
+- append_math_sub(desc, VARSEQINLEN, SEQINLEN, REG3, CAAM_CMD_SZ);
+-
+- /* Read Salt and AES-GMAC ESP IV */
+- append_cmd(desc, CMD_FIFO_LOAD | FIFOLD_CLASS_CLASS1 | IMMEDIATE |
+- FIFOLD_TYPE_IV | FIFOLD_TYPE_FLUSH1 | (4 + tfm->ivsize));
+- /* Append Salt */
+- append_data(desc, (void *)(ctx->key + ctx->enckeylen), 4);
+- set_move_tgt_here(desc, write_iv_cmd);
+- /* Blank commands. Will be overwritten by AES-GMAC ESP IV. */
+- append_cmd(desc, 0x00000000);
+- append_cmd(desc, 0x00000000);
+- /* End of blank commands */
+-
+- /* Read assoc data */
+- append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLDST_VLF |
+- FIFOLD_TYPE_AAD);
+-
+- /* Will read cryptlen bytes */
+- append_math_add(desc, VARSEQINLEN, ZERO, REG3, CAAM_CMD_SZ);
+-
+- /* Will write cryptlen bytes */
+- append_math_add(desc, VARSEQOUTLEN, ZERO, REG3, CAAM_CMD_SZ);
+-
+- /*
+- * MOVE_LEN opcode is not available in all SEC HW revisions,
+- * thus need to do some magic, i.e. self-patch the descriptor
+- * buffer.
+- */
+- read_move_cmd = append_move(desc, MOVE_SRC_DESCBUF | MOVE_DEST_MATH3 |
+- (0x6 << MOVE_LEN_SHIFT));
+- write_move_cmd = append_move(desc, MOVE_SRC_MATH3 | MOVE_DEST_DESCBUF |
+- (0x8 << MOVE_LEN_SHIFT));
+-
+- /* Authenticate AES-GMAC ESP IV */
+- append_cmd(desc, CMD_FIFO_LOAD | FIFOLD_CLASS_CLASS1 | IMMEDIATE |
+- FIFOLD_TYPE_AAD | tfm->ivsize);
+- set_move_tgt_here(desc, write_aad_cmd);
+- /* Blank commands. Will be overwritten by AES-GMAC ESP IV. */
+- append_cmd(desc, 0x00000000);
+- append_cmd(desc, 0x00000000);
+- /* End of blank commands */
+-
+- /* Read and write cryptlen bytes */
+- aead_append_src_dst(desc, FIFOLD_TYPE_AAD);
+-
+- set_move_tgt_here(desc, read_move_cmd);
+- set_move_tgt_here(desc, write_move_cmd);
+- append_cmd(desc, CMD_LOAD | DISABLE_AUTO_INFO_FIFO);
+- /* Move payload data to OFIFO */
+- append_move(desc, MOVE_SRC_INFIFO_CL | MOVE_DEST_OUTFIFO);
+-
+- /* Write ICV */
+- append_seq_store(desc, ctx->authsize, LDST_CLASS_1_CCB |
+- LDST_SRCDST_BYTE_CONTEXT);
+-
+- ctx->sh_desc_enc_dma = dma_map_single(jrdev, desc,
+- desc_bytes(desc),
+- DMA_TO_DEVICE);
+- if (dma_mapping_error(jrdev, ctx->sh_desc_enc_dma)) {
+- dev_err(jrdev, "unable to map shared descriptor\n");
+- return -ENOMEM;
+- }
+-#ifdef DEBUG
+- print_hex_dump(KERN_ERR, "rfc4543 enc shdesc@"__stringify(__LINE__)": ",
+- DUMP_PREFIX_ADDRESS, 16, 4, desc,
+- desc_bytes(desc), 1);
+-#endif
+-
+- /*
+- * Job Descriptor and Shared Descriptors
+- * must all fit into the 64-word Descriptor h/w Buffer
+- */
+- keys_fit_inline = false;
+- if (DESC_RFC4543_DEC_LEN + DESC_JOB_IO_LEN +
+- ctx->enckeylen <= CAAM_DESC_BYTES_MAX)
+- keys_fit_inline = true;
+-
+- desc = ctx->sh_desc_dec;
+-
+- init_sh_desc(desc, HDR_SHARE_SERIAL);
+-
+- /* Skip key loading if it is loaded due to sharing */
+- key_jump_cmd = append_jump(desc, JUMP_JSL |
+- JUMP_TEST_ALL | JUMP_COND_SHRD);
+- if (keys_fit_inline)
+- append_key_as_imm(desc, (void *)ctx->key, ctx->enckeylen,
+- ctx->enckeylen, CLASS_1 | KEY_DEST_CLASS_REG);
+- else
+- append_key(desc, ctx->key_dma, ctx->enckeylen,
+- CLASS_1 | KEY_DEST_CLASS_REG);
+- set_jump_tgt_here(desc, key_jump_cmd);
+-
+- /* Class 1 operation */
+- append_operation(desc, ctx->class1_alg_type |
+- OP_ALG_AS_INITFINAL | OP_ALG_DECRYPT | OP_ALG_ICV_ON);
+-
+- /* Load AES-GMAC ESP IV into Math1 register */
+- append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_WORD_DECO_MATH1 |
+- LDST_CLASS_DECO | tfm->ivsize);
+-
+- /* Wait the DMA transaction to finish */
+- append_jump(desc, JUMP_TEST_ALL | JUMP_COND_CALM |
+- (1 << JUMP_OFFSET_SHIFT));
+-
+- /* assoclen + cryptlen = (seqinlen - ivsize) - icvsize */
+- append_math_sub_imm_u32(desc, REG3, SEQINLEN, IMM, ctx->authsize);
+-
+- /* Overwrite blank immediate AES-GMAC ESP IV data */
+- write_iv_cmd = append_move(desc, MOVE_SRC_MATH1 | MOVE_DEST_DESCBUF |
+- (tfm->ivsize << MOVE_LEN_SHIFT));
+-
+- /* Overwrite blank immediate AAD data */
+- write_aad_cmd = append_move(desc, MOVE_SRC_MATH1 | MOVE_DEST_DESCBUF |
+- (tfm->ivsize << MOVE_LEN_SHIFT));
+-
+- /* assoclen = (assoclen + cryptlen) - cryptlen */
+- append_math_sub(desc, REG2, SEQOUTLEN, REG0, CAAM_CMD_SZ);
+- append_math_sub(desc, VARSEQINLEN, REG3, REG2, CAAM_CMD_SZ);
+-
+- /*
+- * MOVE_LEN opcode is not available in all SEC HW revisions,
+- * thus need to do some magic, i.e. self-patch the descriptor
+- * buffer.
+- */
+- read_move_cmd = append_move(desc, MOVE_SRC_DESCBUF | MOVE_DEST_MATH3 |
+- (0x6 << MOVE_LEN_SHIFT));
+- write_move_cmd = append_move(desc, MOVE_SRC_MATH3 | MOVE_DEST_DESCBUF |
+- (0x8 << MOVE_LEN_SHIFT));
+-
+- /* Read Salt and AES-GMAC ESP IV */
+- append_cmd(desc, CMD_FIFO_LOAD | FIFOLD_CLASS_CLASS1 | IMMEDIATE |
+- FIFOLD_TYPE_IV | FIFOLD_TYPE_FLUSH1 | (4 + tfm->ivsize));
+- /* Append Salt */
+- append_data(desc, (void *)(ctx->key + ctx->enckeylen), 4);
+- set_move_tgt_here(desc, write_iv_cmd);
+- /* Blank commands. Will be overwritten by AES-GMAC ESP IV. */
+- append_cmd(desc, 0x00000000);
+- append_cmd(desc, 0x00000000);
+- /* End of blank commands */
+-
+- /* Read assoc data */
+- append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLDST_VLF |
+- FIFOLD_TYPE_AAD);
+-
+- /* Will read cryptlen bytes */
+- append_math_add(desc, VARSEQINLEN, ZERO, REG2, CAAM_CMD_SZ);
+-
+- /* Will write cryptlen bytes */
+- append_math_add(desc, VARSEQOUTLEN, ZERO, REG2, CAAM_CMD_SZ);
+-
+- /* Authenticate AES-GMAC ESP IV */
+- append_cmd(desc, CMD_FIFO_LOAD | FIFOLD_CLASS_CLASS1 | IMMEDIATE |
+- FIFOLD_TYPE_AAD | tfm->ivsize);
+- set_move_tgt_here(desc, write_aad_cmd);
+- /* Blank commands. Will be overwritten by AES-GMAC ESP IV. */
+- append_cmd(desc, 0x00000000);
+- append_cmd(desc, 0x00000000);
+- /* End of blank commands */
+-
+- /* Store payload data */
+- append_seq_fifo_store(desc, 0, FIFOST_TYPE_MESSAGE_DATA | FIFOLDST_VLF);
+-
+- /* In-snoop cryptlen data */
+- append_seq_fifo_load(desc, 0, FIFOLD_CLASS_BOTH | FIFOLDST_VLF |
+- FIFOLD_TYPE_AAD | FIFOLD_TYPE_LAST2FLUSH1);
+-
+- set_move_tgt_here(desc, read_move_cmd);
+- set_move_tgt_here(desc, write_move_cmd);
+- append_cmd(desc, CMD_LOAD | DISABLE_AUTO_INFO_FIFO);
+- /* Move payload data to OFIFO */
+- append_move(desc, MOVE_SRC_INFIFO_CL | MOVE_DEST_OUTFIFO);
+- append_cmd(desc, CMD_LOAD | ENABLE_AUTO_INFO_FIFO);
+-
+- /* Read ICV */
+- append_seq_fifo_load(desc, ctx->authsize, FIFOLD_CLASS_CLASS1 |
+- FIFOLD_TYPE_ICV | FIFOLD_TYPE_LAST1);
+-
+- ctx->sh_desc_dec_dma = dma_map_single(jrdev, desc,
+- desc_bytes(desc),
+- DMA_TO_DEVICE);
+- if (dma_mapping_error(jrdev, ctx->sh_desc_dec_dma)) {
+- dev_err(jrdev, "unable to map shared descriptor\n");
+- return -ENOMEM;
+- }
+-#ifdef DEBUG
+- print_hex_dump(KERN_ERR, "rfc4543 dec shdesc@"__stringify(__LINE__)": ",
+- DUMP_PREFIX_ADDRESS, 16, 4, desc,
+- desc_bytes(desc), 1);
+-#endif
+-
+- /*
+- * Job Descriptor and Shared Descriptors
+- * must all fit into the 64-word Descriptor h/w Buffer
+- */
+- keys_fit_inline = false;
+- if (DESC_RFC4543_GIVENC_LEN + DESC_JOB_IO_LEN +
+- ctx->enckeylen <= CAAM_DESC_BYTES_MAX)
+- keys_fit_inline = true;
+-
+- /* rfc4543_givencrypt shared descriptor */
+- desc = ctx->sh_desc_givenc;
+-
+- init_sh_desc(desc, HDR_SHARE_SERIAL);
+-
+- /* Skip key loading if it is loaded due to sharing */
+- key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
+- JUMP_COND_SHRD);
+- if (keys_fit_inline)
+- append_key_as_imm(desc, (void *)ctx->key, ctx->enckeylen,
+- ctx->enckeylen, CLASS_1 | KEY_DEST_CLASS_REG);
+- else
+- append_key(desc, ctx->key_dma, ctx->enckeylen,
+- CLASS_1 | KEY_DEST_CLASS_REG);
+- set_jump_tgt_here(desc, key_jump_cmd);
+-
+- /* Generate IV */
+- geniv = NFIFOENTRY_STYPE_PAD | NFIFOENTRY_DEST_DECO |
+- NFIFOENTRY_DTYPE_MSG | NFIFOENTRY_LC1 |
+- NFIFOENTRY_PTYPE_RND | (tfm->ivsize << NFIFOENTRY_DLEN_SHIFT);
+- append_load_imm_u32(desc, geniv, LDST_CLASS_IND_CCB |
+- LDST_SRCDST_WORD_INFO_FIFO | LDST_IMM);
+- append_cmd(desc, CMD_LOAD | DISABLE_AUTO_INFO_FIFO);
+- /* Move generated IV to Math1 register */
+- append_move(desc, MOVE_SRC_INFIFO | MOVE_DEST_MATH1 |
+- (tfm->ivsize << MOVE_LEN_SHIFT));
+- append_cmd(desc, CMD_LOAD | ENABLE_AUTO_INFO_FIFO);
+-
+- /* Overwrite blank immediate AES-GMAC IV data */
+- write_iv_cmd = append_move(desc, MOVE_SRC_MATH1 | MOVE_DEST_DESCBUF |
+- (tfm->ivsize << MOVE_LEN_SHIFT));
+-
+- /* Overwrite blank immediate AAD data */
+- write_aad_cmd = append_move(desc, MOVE_SRC_MATH1 | MOVE_DEST_DESCBUF |
+- (tfm->ivsize << MOVE_LEN_SHIFT));
+-
+- /* Copy generated IV to OFIFO */
+- append_move(desc, MOVE_SRC_MATH1 | MOVE_DEST_OUTFIFO |
+- (tfm->ivsize << MOVE_LEN_SHIFT));
+-
+- /* Class 1 operation */
+- append_operation(desc, ctx->class1_alg_type |
+- OP_ALG_AS_INITFINAL | OP_ALG_ENCRYPT);
+-
+- /* ivsize + cryptlen = seqoutlen - authsize */
+- append_math_sub_imm_u32(desc, REG3, SEQOUTLEN, IMM, ctx->authsize);
+-
+- /* assoclen = seqinlen - (ivsize + cryptlen) */
+- append_math_sub(desc, VARSEQINLEN, SEQINLEN, REG3, CAAM_CMD_SZ);
+-
+- /* Will write ivsize + cryptlen */
+- append_math_add(desc, VARSEQOUTLEN, REG3, REG0, CAAM_CMD_SZ);
+-
+- /*
+- * MOVE_LEN opcode is not available in all SEC HW revisions,
+- * thus need to do some magic, i.e. self-patch the descriptor
+- * buffer.
+- */
+- read_move_cmd = append_move(desc, MOVE_SRC_DESCBUF | MOVE_DEST_MATH3 |
+- (0x6 << MOVE_LEN_SHIFT));
+- write_move_cmd = append_move(desc, MOVE_SRC_MATH3 | MOVE_DEST_DESCBUF |
+- (0x8 << MOVE_LEN_SHIFT));
+-
+- /* Read Salt and AES-GMAC generated IV */
+- append_cmd(desc, CMD_FIFO_LOAD | FIFOLD_CLASS_CLASS1 | IMMEDIATE |
+- FIFOLD_TYPE_IV | FIFOLD_TYPE_FLUSH1 | (4 + tfm->ivsize));
+- /* Append Salt */
+- append_data(desc, (void *)(ctx->key + ctx->enckeylen), 4);
+- set_move_tgt_here(desc, write_iv_cmd);
+- /* Blank commands. Will be overwritten by AES-GMAC generated IV. */
+- append_cmd(desc, 0x00000000);
+- append_cmd(desc, 0x00000000);
+- /* End of blank commands */
+-
+- /* No need to reload iv */
+- append_seq_fifo_load(desc, tfm->ivsize, FIFOLD_CLASS_SKIP);
+-
+- /* Read assoc data */
+- append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLDST_VLF |
+- FIFOLD_TYPE_AAD);
+-
+- /* Will read cryptlen */
+- append_math_add(desc, VARSEQINLEN, SEQINLEN, REG0, CAAM_CMD_SZ);
+-
+- /* Authenticate AES-GMAC IV */
+- append_cmd(desc, CMD_FIFO_LOAD | FIFOLD_CLASS_CLASS1 | IMMEDIATE |
+- FIFOLD_TYPE_AAD | tfm->ivsize);
+- set_move_tgt_here(desc, write_aad_cmd);
+- /* Blank commands. Will be overwritten by AES-GMAC IV. */
+- append_cmd(desc, 0x00000000);
+- append_cmd(desc, 0x00000000);
+- /* End of blank commands */
+-
+- /* Read and write cryptlen bytes */
+- aead_append_src_dst(desc, FIFOLD_TYPE_AAD);
+-
+- set_move_tgt_here(desc, read_move_cmd);
+- set_move_tgt_here(desc, write_move_cmd);
+- append_cmd(desc, CMD_LOAD | DISABLE_AUTO_INFO_FIFO);
+- /* Move payload data to OFIFO */
+- append_move(desc, MOVE_SRC_INFIFO_CL | MOVE_DEST_OUTFIFO);
+-
+- /* Write ICV */
+- append_seq_store(desc, ctx->authsize, LDST_CLASS_1_CCB |
+- LDST_SRCDST_BYTE_CONTEXT);
+-
+- ctx->sh_desc_givenc_dma = dma_map_single(jrdev, desc,
+- desc_bytes(desc),
+- DMA_TO_DEVICE);
+- if (dma_mapping_error(jrdev, ctx->sh_desc_givenc_dma)) {
+- dev_err(jrdev, "unable to map shared descriptor\n");
+- return -ENOMEM;
+- }
+-#ifdef DEBUG
+- print_hex_dump(KERN_ERR,
+- "rfc4543 givenc shdesc@"__stringify(__LINE__)": ",
+- DUMP_PREFIX_ADDRESS, 16, 4, desc,
+- desc_bytes(desc), 1);
+-#endif
+-
+- return 0;
+-}
+-
+-static int rfc4543_setauthsize(struct crypto_aead *authenc,
+- unsigned int authsize)
+-{
+- struct caam_ctx *ctx = crypto_aead_ctx(authenc);
+-
+- ctx->authsize = authsize;
+- rfc4543_set_sh_desc(authenc);
+-
+- return 0;
+-}
+-
+-static u32 gen_split_aead_key(struct caam_ctx *ctx, const u8 *key_in,
+- u32 authkeylen)
+-{
+- return gen_split_key(ctx->jrdev, ctx->key, ctx->split_key_len,
+- ctx->split_key_pad_len, key_in, authkeylen,
+- ctx->alg_op);
+-}
+-
+-static int aead_setkey(struct crypto_aead *aead,
+- const u8 *key, unsigned int keylen)
+-{
+- /* Sizes for MDHA pads (*not* keys): MD5, SHA1, 224, 256, 384, 512 */
+- static const u8 mdpadlen[] = { 16, 20, 32, 32, 64, 64 };
+- struct caam_ctx *ctx = crypto_aead_ctx(aead);
+- struct device *jrdev = ctx->jrdev;
+- struct crypto_authenc_keys keys;
+- int ret = 0;
+-
+- if (crypto_authenc_extractkeys(&keys, key, keylen) != 0)
+- goto badkey;
+-
+- /* Pick class 2 key length from algorithm submask */
+- ctx->split_key_len = mdpadlen[(ctx->alg_op & OP_ALG_ALGSEL_SUBMASK) >>
+- OP_ALG_ALGSEL_SHIFT] * 2;
+- ctx->split_key_pad_len = ALIGN(ctx->split_key_len, 16);
+-
+- if (ctx->split_key_pad_len + keys.enckeylen > CAAM_MAX_KEY_SIZE)
+- goto badkey;
+-
+-#ifdef DEBUG
+- printk(KERN_ERR "keylen %d enckeylen %d authkeylen %d\n",
+- keys.authkeylen + keys.enckeylen, keys.enckeylen,
+- keys.authkeylen);
+- printk(KERN_ERR "split_key_len %d split_key_pad_len %d\n",
+- ctx->split_key_len, ctx->split_key_pad_len);
+- print_hex_dump(KERN_ERR, "key in @"__stringify(__LINE__)": ",
+- DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
+-#endif
+-
+- ret = gen_split_aead_key(ctx, keys.authkey, keys.authkeylen);
+- if (ret) {
+- goto badkey;
+- }
+-
+- /* postpend encryption key to auth split key */
+- memcpy(ctx->key + ctx->split_key_pad_len, keys.enckey, keys.enckeylen);
+-
+- ctx->key_dma = dma_map_single(jrdev, ctx->key, ctx->split_key_pad_len +
+- keys.enckeylen, DMA_TO_DEVICE);
+- if (dma_mapping_error(jrdev, ctx->key_dma)) {
+- dev_err(jrdev, "unable to map key i/o memory\n");
+- return -ENOMEM;
+- }
+-#ifdef DEBUG
+- print_hex_dump(KERN_ERR, "ctx.key@"__stringify(__LINE__)": ",
+- DUMP_PREFIX_ADDRESS, 16, 4, ctx->key,
+- ctx->split_key_pad_len + keys.enckeylen, 1);
+-#endif
+-
+- ctx->enckeylen = keys.enckeylen;
++ ctx->enckeylen = enckeylen;
+
+ ret = aead_set_sh_desc(aead);
+ if (ret) {
+ dma_unmap_single(jrdev, ctx->key_dma, ctx->split_key_pad_len +
+- keys.enckeylen, DMA_TO_DEVICE);
++ enckeylen, DMA_TO_DEVICE);
+ }
+
+ return ret;
+@@ -1715,154 +548,20 @@
+ return -EINVAL;
+ }
+
+-static int gcm_setkey(struct crypto_aead *aead,
+- const u8 *key, unsigned int keylen)
+-{
+- struct caam_ctx *ctx = crypto_aead_ctx(aead);
+- struct device *jrdev = ctx->jrdev;
+- int ret = 0;
+-
+-#ifdef DEBUG
+- print_hex_dump(KERN_ERR, "key in @"__stringify(__LINE__)": ",
+- DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
+-#endif
+-
+- memcpy(ctx->key, key, keylen);
+- ctx->key_dma = dma_map_single(jrdev, ctx->key, keylen,
+- DMA_TO_DEVICE);
+- if (dma_mapping_error(jrdev, ctx->key_dma)) {
+- dev_err(jrdev, "unable to map key i/o memory\n");
+- return -ENOMEM;
+- }
+- ctx->enckeylen = keylen;
+-
+- ret = gcm_set_sh_desc(aead);
+- if (ret) {
+- dma_unmap_single(jrdev, ctx->key_dma, ctx->enckeylen,
+- DMA_TO_DEVICE);
+- }
+-
+- return ret;
+-}
+-
+-static int rfc4106_setkey(struct crypto_aead *aead,
+- const u8 *key, unsigned int keylen)
+-{
+- struct caam_ctx *ctx = crypto_aead_ctx(aead);
+- struct device *jrdev = ctx->jrdev;
+- int ret = 0;
+-
+- if (keylen < 4)
+- return -EINVAL;
+-
+-#ifdef DEBUG
+- print_hex_dump(KERN_ERR, "key in @"__stringify(__LINE__)": ",
+- DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
+-#endif
+-
+- memcpy(ctx->key, key, keylen);
+-
+- /*
+- * The last four bytes of the key material are used as the salt value
+- * in the nonce. Update the AES key length.
+- */
+- ctx->enckeylen = keylen - 4;
+-
+- ctx->key_dma = dma_map_single(jrdev, ctx->key, ctx->enckeylen,
+- DMA_TO_DEVICE);
+- if (dma_mapping_error(jrdev, ctx->key_dma)) {
+- dev_err(jrdev, "unable to map key i/o memory\n");
+- return -ENOMEM;
+- }
+-
+- ret = rfc4106_set_sh_desc(aead);
+- if (ret) {
+- dma_unmap_single(jrdev, ctx->key_dma, ctx->enckeylen,
+- DMA_TO_DEVICE);
+- }
+-
+- return ret;
+-}
+-
+-static int rfc4543_setkey(struct crypto_aead *aead,
+- const u8 *key, unsigned int keylen)
+-{
+- struct caam_ctx *ctx = crypto_aead_ctx(aead);
+- struct device *jrdev = ctx->jrdev;
+- int ret = 0;
+-
+- if (keylen < 4)
+- return -EINVAL;
+-
+-#ifdef DEBUG
+- print_hex_dump(KERN_ERR, "key in @"__stringify(__LINE__)": ",
+- DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
+-#endif
+-
+- memcpy(ctx->key, key, keylen);
+-
+- /*
+- * The last four bytes of the key material are used as the salt value
+- * in the nonce. Update the AES key length.
+- */
+- ctx->enckeylen = keylen - 4;
+-
+- ctx->key_dma = dma_map_single(jrdev, ctx->key, ctx->enckeylen,
+- DMA_TO_DEVICE);
+- if (dma_mapping_error(jrdev, ctx->key_dma)) {
+- dev_err(jrdev, "unable to map key i/o memory\n");
+- return -ENOMEM;
+- }
+-
+- ret = rfc4543_set_sh_desc(aead);
+- if (ret) {
+- dma_unmap_single(jrdev, ctx->key_dma, ctx->enckeylen,
+- DMA_TO_DEVICE);
+- }
+-
+- return ret;
+-}
+-
+ static int ablkcipher_setkey(struct crypto_ablkcipher *ablkcipher,
+ const u8 *key, unsigned int keylen)
+ {
+ struct caam_ctx *ctx = crypto_ablkcipher_ctx(ablkcipher);
+- struct ablkcipher_tfm *crt = &ablkcipher->base.crt_ablkcipher;
+- struct crypto_tfm *tfm = crypto_ablkcipher_tfm(ablkcipher);
+- const char *alg_name = crypto_tfm_alg_name(tfm);
++ struct ablkcipher_tfm *tfm = &ablkcipher->base.crt_ablkcipher;
+ struct device *jrdev = ctx->jrdev;
+ int ret = 0;
+- u32 *key_jump_cmd;
++ u32 *key_jump_cmd, *jump_cmd;
+ u32 *desc;
+- u32 *nonce;
+- u32 geniv;
+- u32 ctx1_iv_off = 0;
+- const bool ctr_mode = ((ctx->class1_alg_type & OP_ALG_AAI_MASK) ==
+- OP_ALG_AAI_CTR_MOD128);
+- const bool is_rfc3686 = (ctr_mode &&
+- (strstr(alg_name, "rfc3686") != NULL));
+
+ #ifdef DEBUG
+- print_hex_dump(KERN_ERR, "key in @"__stringify(__LINE__)": ",
++ print_hex_dump(KERN_ERR, "key in @"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
+ #endif
+- /*
+- * AES-CTR needs to load IV in CONTEXT1 reg
+- * at an offset of 128bits (16bytes)
+- * CONTEXT1[255:128] = IV
+- */
+- if (ctr_mode)
+- ctx1_iv_off = 16;
+-
+- /*
+- * RFC3686 specific:
+- * | CONTEXT1[255:128] = {NONCE, IV, COUNTER}
+- * | *key = {KEY, NONCE}
+- */
+- if (is_rfc3686) {
+- ctx1_iv_off = 16 + CTR_RFC3686_NONCE_SIZE;
+- keylen -= CTR_RFC3686_NONCE_SIZE;
+- }
+
+ memcpy(ctx->key, key, keylen);
+ ctx->key_dma = dma_map_single(jrdev, ctx->key, keylen,
+@@ -1872,10 +571,11 @@
+ return -ENOMEM;
+ }
+ ctx->enckeylen = keylen;
++ dma_sync_single_for_device(jrdev, ctx->key_dma, keylen, DMA_TO_DEVICE);
+
+ /* ablkcipher_encrypt shared descriptor */
+ desc = ctx->sh_desc_enc;
+- init_sh_desc(desc, HDR_SHARE_SERIAL | HDR_SAVECTX);
++ init_sh_desc(desc, HDR_SHARE_SERIAL);
+ /* Skip if already shared */
+ key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
+ JUMP_COND_SHRD);
+@@ -1885,32 +585,20 @@
+ ctx->enckeylen, CLASS_1 |
+ KEY_DEST_CLASS_REG);
+
+- /* Load nonce into CONTEXT1 reg */
+- if (is_rfc3686) {
+- nonce = (u32 *)(key + keylen);
+- append_load_imm_u32(desc, *nonce, LDST_CLASS_IND_CCB |
+- LDST_SRCDST_BYTE_OUTFIFO | LDST_IMM);
+- append_move(desc, MOVE_WAITCOMP |
+- MOVE_SRC_OUTFIFO |
+- MOVE_DEST_CLASS1CTX |
+- (16 << MOVE_OFFSET_SHIFT) |
+- (CTR_RFC3686_NONCE_SIZE << MOVE_LEN_SHIFT));
+- }
+-
+ set_jump_tgt_here(desc, key_jump_cmd);
+
+- /* Load iv */
+- append_seq_load(desc, crt->ivsize, LDST_SRCDST_BYTE_CONTEXT |
+- LDST_CLASS_1_CCB | (ctx1_iv_off << LDST_OFFSET_SHIFT));
+-
+- /* Load counter into CONTEXT1 reg */
+- if (is_rfc3686)
+- append_load_imm_u32(desc, be32_to_cpu(1), LDST_IMM |
+- LDST_CLASS_1_CCB |
+- LDST_SRCDST_BYTE_CONTEXT |
+- ((ctx1_iv_off + CTR_RFC3686_IV_SIZE) <<
+- LDST_OFFSET_SHIFT));
++ /* Propagate errors from shared to job descriptor */
++ append_cmd(desc, SET_OK_NO_PROP_ERRORS | CMD_LOAD);
+
++ /* load IV */
++ if (strncmp(ablkcipher->base.__crt_alg->cra_name, "ctr(aes)", 8) == 0) {
++ append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_BYTE_CONTEXT |
++ LDST_CLASS_1_CCB | tfm->ivsize |
++ (16 << LDST_OFFSET_SHIFT));
++ } else {
++ append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_BYTE_CONTEXT |
++ LDST_CLASS_1_CCB | tfm->ivsize);
++ }
+ /* Load operation */
+ append_operation(desc, ctx->class1_alg_type |
+ OP_ALG_AS_INITFINAL | OP_ALG_ENCRYPT);
+@@ -1926,15 +614,17 @@
+ return -ENOMEM;
+ }
+ #ifdef DEBUG
+- print_hex_dump(KERN_ERR,
+- "ablkcipher enc shdesc@"__stringify(__LINE__)": ",
++ print_hex_dump(KERN_ERR, "ablkcipher enc shdesc@"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, desc,
+ desc_bytes(desc), 1);
+ #endif
++ dma_sync_single_for_device(jrdev, ctx->sh_desc_enc_dma,
++ desc_bytes(desc), DMA_TO_DEVICE);
++
+ /* ablkcipher_decrypt shared descriptor */
+ desc = ctx->sh_desc_dec;
+
+- init_sh_desc(desc, HDR_SHARE_SERIAL | HDR_SAVECTX);
++ init_sh_desc(desc, HDR_SHARE_SERIAL);
+ /* Skip if already shared */
+ key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
+ JUMP_COND_SHRD);
+@@ -1944,133 +634,49 @@
+ ctx->enckeylen, CLASS_1 |
+ KEY_DEST_CLASS_REG);
+
+- /* Load nonce into CONTEXT1 reg */
+- if (is_rfc3686) {
+- nonce = (u32 *)(key + keylen);
+- append_load_imm_u32(desc, *nonce, LDST_CLASS_IND_CCB |
+- LDST_SRCDST_BYTE_OUTFIFO | LDST_IMM);
+- append_move(desc, MOVE_WAITCOMP |
+- MOVE_SRC_OUTFIFO |
+- MOVE_DEST_CLASS1CTX |
+- (16 << MOVE_OFFSET_SHIFT) |
+- (CTR_RFC3686_NONCE_SIZE << MOVE_LEN_SHIFT));
+- }
+-
++ /* For aead, only propagate error immediately if shared */
++ jump_cmd = append_jump(desc, JUMP_TEST_ALL);
+ set_jump_tgt_here(desc, key_jump_cmd);
++ append_cmd(desc, SET_OK_NO_PROP_ERRORS | CMD_LOAD);
++ set_jump_tgt_here(desc, jump_cmd);
+
+ /* load IV */
+- append_seq_load(desc, crt->ivsize, LDST_SRCDST_BYTE_CONTEXT |
+- LDST_CLASS_1_CCB | (ctx1_iv_off << LDST_OFFSET_SHIFT));
+-
+- /* Load counter into CONTEXT1 reg */
+- if (is_rfc3686)
+- append_load_imm_u32(desc, be32_to_cpu(1), LDST_IMM |
+- LDST_CLASS_1_CCB |
+- LDST_SRCDST_BYTE_CONTEXT |
+- ((ctx1_iv_off + CTR_RFC3686_IV_SIZE) <<
+- LDST_OFFSET_SHIFT));
++ if (strncmp(ablkcipher->base.__crt_alg->cra_name, "ctr(aes)", 8) == 0) {
++ append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_BYTE_CONTEXT |
++ LDST_CLASS_1_CCB | tfm->ivsize |
++ (16 << LDST_OFFSET_SHIFT));
+
+- /* Choose operation */
+- if (ctr_mode)
+ append_operation(desc, ctx->class1_alg_type |
+- OP_ALG_AS_INITFINAL | OP_ALG_DECRYPT);
+- else
++ OP_ALG_AS_INITFINAL | OP_ALG_DECRYPT);
++ } else {
++ append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_BYTE_CONTEXT |
++ LDST_CLASS_1_CCB | tfm->ivsize);
++
++ /* Choose operation */
+ append_dec_op1(desc, ctx->class1_alg_type);
++ }
+
+ /* Perform operation */
+ ablkcipher_append_src_dst(desc);
+
++ /* Wait for key to load before allowing propagating error */
++ append_dec_shr_done(desc);
++
+ ctx->sh_desc_dec_dma = dma_map_single(jrdev, desc,
+ desc_bytes(desc),
+ DMA_TO_DEVICE);
+- if (dma_mapping_error(jrdev, ctx->sh_desc_dec_dma)) {
++ if (dma_mapping_error(jrdev, ctx->sh_desc_enc_dma)) {
+ dev_err(jrdev, "unable to map shared descriptor\n");
+ return -ENOMEM;
+ }
+
+ #ifdef DEBUG
+- print_hex_dump(KERN_ERR,
+- "ablkcipher dec shdesc@"__stringify(__LINE__)": ",
+- DUMP_PREFIX_ADDRESS, 16, 4, desc,
+- desc_bytes(desc), 1);
+-#endif
+- /* ablkcipher_givencrypt shared descriptor */
+- desc = ctx->sh_desc_givenc;
+-
+- init_sh_desc(desc, HDR_SHARE_SERIAL | HDR_SAVECTX);
+- /* Skip if already shared */
+- key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
+- JUMP_COND_SHRD);
+-
+- /* Load class1 key only */
+- append_key_as_imm(desc, (void *)ctx->key, ctx->enckeylen,
+- ctx->enckeylen, CLASS_1 |
+- KEY_DEST_CLASS_REG);
+-
+- /* Load Nonce into CONTEXT1 reg */
+- if (is_rfc3686) {
+- nonce = (u32 *)(key + keylen);
+- append_load_imm_u32(desc, *nonce, LDST_CLASS_IND_CCB |
+- LDST_SRCDST_BYTE_OUTFIFO | LDST_IMM);
+- append_move(desc, MOVE_WAITCOMP |
+- MOVE_SRC_OUTFIFO |
+- MOVE_DEST_CLASS1CTX |
+- (16 << MOVE_OFFSET_SHIFT) |
+- (CTR_RFC3686_NONCE_SIZE << MOVE_LEN_SHIFT));
+- }
+- set_jump_tgt_here(desc, key_jump_cmd);
+-
+- /* Generate IV */
+- geniv = NFIFOENTRY_STYPE_PAD | NFIFOENTRY_DEST_DECO |
+- NFIFOENTRY_DTYPE_MSG | NFIFOENTRY_LC1 |
+- NFIFOENTRY_PTYPE_RND | (crt->ivsize << NFIFOENTRY_DLEN_SHIFT);
+- append_load_imm_u32(desc, geniv, LDST_CLASS_IND_CCB |
+- LDST_SRCDST_WORD_INFO_FIFO | LDST_IMM);
+- append_cmd(desc, CMD_LOAD | DISABLE_AUTO_INFO_FIFO);
+- append_move(desc, MOVE_WAITCOMP |
+- MOVE_SRC_INFIFO |
+- MOVE_DEST_CLASS1CTX |
+- (crt->ivsize << MOVE_LEN_SHIFT) |
+- (ctx1_iv_off << MOVE_OFFSET_SHIFT));
+- append_cmd(desc, CMD_LOAD | ENABLE_AUTO_INFO_FIFO);
+-
+- /* Copy generated IV to memory */
+- append_seq_store(desc, crt->ivsize,
+- LDST_SRCDST_BYTE_CONTEXT | LDST_CLASS_1_CCB |
+- (ctx1_iv_off << LDST_OFFSET_SHIFT));
+-
+- /* Load Counter into CONTEXT1 reg */
+- if (is_rfc3686)
+- append_load_imm_u32(desc, (u32)1, LDST_IMM |
+- LDST_CLASS_1_CCB |
+- LDST_SRCDST_BYTE_CONTEXT |
+- ((ctx1_iv_off + CTR_RFC3686_IV_SIZE) <<
+- LDST_OFFSET_SHIFT));
+-
+- if (ctx1_iv_off)
+- append_jump(desc, JUMP_JSL | JUMP_TEST_ALL | JUMP_COND_NCP |
+- (1 << JUMP_OFFSET_SHIFT));
+-
+- /* Load operation */
+- append_operation(desc, ctx->class1_alg_type |
+- OP_ALG_AS_INITFINAL | OP_ALG_ENCRYPT);
+-
+- /* Perform operation */
+- ablkcipher_append_src_dst(desc);
+-
+- ctx->sh_desc_givenc_dma = dma_map_single(jrdev, desc,
+- desc_bytes(desc),
+- DMA_TO_DEVICE);
+- if (dma_mapping_error(jrdev, ctx->sh_desc_givenc_dma)) {
+- dev_err(jrdev, "unable to map shared descriptor\n");
+- return -ENOMEM;
+- }
+-#ifdef DEBUG
+- print_hex_dump(KERN_ERR,
+- "ablkcipher givenc shdesc@" __stringify(__LINE__) ": ",
++ print_hex_dump(KERN_ERR, "ablkcipher dec shdesc@"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, desc,
+ desc_bytes(desc), 1);
+ #endif
++ dma_sync_single_for_device(jrdev, ctx->sh_desc_dec_dma,
++ desc_bytes(desc), DMA_TO_DEVICE);
+
+ return ret;
+ }
+@@ -2195,19 +801,22 @@
+ edesc = (struct aead_edesc *)((char *)desc -
+ offsetof(struct aead_edesc, hw_desc));
+
+- if (err)
+- caam_jr_strstatus(jrdev, err);
++ if (err) {
++ char tmp[CAAM_ERROR_STR_MAX];
++
++ dev_err(jrdev, "%08x: %s\n", err, caam_jr_strstatus(tmp, err));
++ }
+
+ aead_unmap(jrdev, edesc, req);
+
+ #ifdef DEBUG
+- print_hex_dump(KERN_ERR, "assoc @"__stringify(__LINE__)": ",
++ print_hex_dump(KERN_ERR, "assoc @"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->assoc),
+ req->assoclen , 1);
+- print_hex_dump(KERN_ERR, "dstiv @"__stringify(__LINE__)": ",
++ print_hex_dump(KERN_ERR, "dstiv @"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->src) - ivsize,
+ edesc->src_nents ? 100 : ivsize, 1);
+- print_hex_dump(KERN_ERR, "dst @"__stringify(__LINE__)": ",
++ print_hex_dump(KERN_ERR, "dst @"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->src),
+ edesc->src_nents ? 100 : req->cryptlen +
+ ctx->authsize + 4, 1);
+@@ -2235,16 +844,19 @@
+ offsetof(struct aead_edesc, hw_desc));
+
+ #ifdef DEBUG
+- print_hex_dump(KERN_ERR, "dstiv @"__stringify(__LINE__)": ",
++ print_hex_dump(KERN_ERR, "dstiv @"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, req->iv,
+ ivsize, 1);
+- print_hex_dump(KERN_ERR, "dst @"__stringify(__LINE__)": ",
++ print_hex_dump(KERN_ERR, "dst @"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->dst),
+- req->cryptlen - ctx->authsize, 1);
++ req->cryptlen, 1);
+ #endif
+
+- if (err)
+- caam_jr_strstatus(jrdev, err);
++ if (err) {
++ char tmp[CAAM_ERROR_STR_MAX];
++
++ dev_err(jrdev, "%08x: %s\n", err, caam_jr_strstatus(tmp, err));
++ }
+
+ aead_unmap(jrdev, edesc, req);
+
+@@ -2255,7 +867,7 @@
+ err = -EBADMSG;
+
+ #ifdef DEBUG
+- print_hex_dump(KERN_ERR, "iphdrout@"__stringify(__LINE__)": ",
++ print_hex_dump(KERN_ERR, "iphdrout@"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4,
+ ((char *)sg_virt(req->assoc) - sizeof(struct iphdr)),
+ sizeof(struct iphdr) + req->assoclen +
+@@ -2263,7 +875,7 @@
+ ctx->authsize + 36, 1);
+ if (!err && edesc->sec4_sg_bytes) {
+ struct scatterlist *sg = sg_last(req->src, edesc->src_nents);
+- print_hex_dump(KERN_ERR, "sglastout@"__stringify(__LINE__)": ",
++ print_hex_dump(KERN_ERR, "sglastout@"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(sg),
+ sg->length + ctx->authsize + 16, 1);
+ }
+@@ -2289,14 +901,17 @@
+ edesc = (struct ablkcipher_edesc *)((char *)desc -
+ offsetof(struct ablkcipher_edesc, hw_desc));
+
+- if (err)
+- caam_jr_strstatus(jrdev, err);
++ if (err) {
++ char tmp[CAAM_ERROR_STR_MAX];
++
++ dev_err(jrdev, "%08x: %s\n", err, caam_jr_strstatus(tmp, err));
++ }
+
+ #ifdef DEBUG
+- print_hex_dump(KERN_ERR, "dstiv @"__stringify(__LINE__)": ",
++ print_hex_dump(KERN_ERR, "dstiv @"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, req->info,
+ edesc->src_nents > 1 ? 100 : ivsize, 1);
+- print_hex_dump(KERN_ERR, "dst @"__stringify(__LINE__)": ",
++ print_hex_dump(KERN_ERR, "dst @"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->src),
+ edesc->dst_nents > 1 ? 100 : req->nbytes, 1);
+ #endif
+@@ -2321,14 +936,17 @@
+
+ edesc = (struct ablkcipher_edesc *)((char *)desc -
+ offsetof(struct ablkcipher_edesc, hw_desc));
+- if (err)
+- caam_jr_strstatus(jrdev, err);
++ if (err) {
++ char tmp[CAAM_ERROR_STR_MAX];
++
++ dev_err(jrdev, "%08x: %s\n", err, caam_jr_strstatus(tmp, err));
++ }
+
+ #ifdef DEBUG
+- print_hex_dump(KERN_ERR, "dstiv @"__stringify(__LINE__)": ",
++ print_hex_dump(KERN_ERR, "dstiv @"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, req->info,
+ ivsize, 1);
+- print_hex_dump(KERN_ERR, "dst @"__stringify(__LINE__)": ",
++ print_hex_dump(KERN_ERR, "dst @"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->src),
+ edesc->dst_nents > 1 ? 100 : req->nbytes, 1);
+ #endif
+@@ -2355,38 +973,29 @@
+ u32 out_options = 0, in_options;
+ dma_addr_t dst_dma, src_dma;
+ int len, sec4_sg_index = 0;
+- bool is_gcm = false;
+
+ #ifdef DEBUG
+ debug("assoclen %d cryptlen %d authsize %d\n",
+ req->assoclen, req->cryptlen, authsize);
+- print_hex_dump(KERN_ERR, "assoc @"__stringify(__LINE__)": ",
++ print_hex_dump(KERN_ERR, "assoc @"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->assoc),
+ req->assoclen , 1);
+- print_hex_dump(KERN_ERR, "presciv@"__stringify(__LINE__)": ",
++ print_hex_dump(KERN_ERR, "presciv@"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, req->iv,
+ edesc->src_nents ? 100 : ivsize, 1);
+- print_hex_dump(KERN_ERR, "src @"__stringify(__LINE__)": ",
++ print_hex_dump(KERN_ERR, "src @"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->src),
+ edesc->src_nents ? 100 : req->cryptlen, 1);
+- print_hex_dump(KERN_ERR, "shrdesc@"__stringify(__LINE__)": ",
++ print_hex_dump(KERN_ERR, "shrdesc@"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, sh_desc,
+ desc_bytes(sh_desc), 1);
+ #endif
+
+- if (((ctx->class1_alg_type & OP_ALG_ALGSEL_MASK) ==
+- OP_ALG_ALGSEL_AES) &&
+- ((ctx->class1_alg_type & OP_ALG_AAI_MASK) == OP_ALG_AAI_GCM))
+- is_gcm = true;
+-
+ len = desc_len(sh_desc);
+ init_job_desc_shared(desc, ptr, len, HDR_SHARE_DEFER | HDR_REVERSE);
+
+ if (all_contig) {
+- if (is_gcm)
+- src_dma = edesc->iv_dma;
+- else
+- src_dma = sg_dma_address(req->assoc);
++ src_dma = sg_dma_address(req->assoc);
+ in_options = 0;
+ } else {
+ src_dma = edesc->sec4_sg_dma;
+@@ -2394,9 +1003,12 @@
+ (edesc->src_nents ? : 1);
+ in_options = LDST_SGF;
+ }
+-
+- append_seq_in_ptr(desc, src_dma, req->assoclen + ivsize + req->cryptlen,
+- in_options);
++ if (encrypt)
++ append_seq_in_ptr(desc, src_dma, req->assoclen + ivsize +
++ req->cryptlen - authsize, in_options);
++ else
++ append_seq_in_ptr(desc, src_dma, req->assoclen + ivsize +
++ req->cryptlen, in_options);
+
+ if (likely(req->src == req->dst)) {
+ if (all_contig) {
+@@ -2417,8 +1029,7 @@
+ }
+ }
+ if (encrypt)
+- append_seq_out_ptr(desc, dst_dma, req->cryptlen + authsize,
+- out_options);
++ append_seq_out_ptr(desc, dst_dma, req->cryptlen, out_options);
+ else
+ append_seq_out_ptr(desc, dst_dma, req->cryptlen - authsize,
+ out_options);
+@@ -2440,53 +1051,43 @@
+ u32 out_options = 0, in_options;
+ dma_addr_t dst_dma, src_dma;
+ int len, sec4_sg_index = 0;
+- bool is_gcm = false;
+
+ #ifdef DEBUG
+ debug("assoclen %d cryptlen %d authsize %d\n",
+ req->assoclen, req->cryptlen, authsize);
+- print_hex_dump(KERN_ERR, "assoc @"__stringify(__LINE__)": ",
++ print_hex_dump(KERN_ERR, "assoc @"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->assoc),
+ req->assoclen , 1);
+- print_hex_dump(KERN_ERR, "presciv@"__stringify(__LINE__)": ",
++ print_hex_dump(KERN_ERR, "presciv@"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, req->iv, ivsize, 1);
+- print_hex_dump(KERN_ERR, "src @"__stringify(__LINE__)": ",
++ print_hex_dump(KERN_ERR, "src @"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->src),
+ edesc->src_nents > 1 ? 100 : req->cryptlen, 1);
+- print_hex_dump(KERN_ERR, "shrdesc@"__stringify(__LINE__)": ",
++ print_hex_dump(KERN_ERR, "shrdesc@"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, sh_desc,
+ desc_bytes(sh_desc), 1);
+ #endif
+
+- if (((ctx->class1_alg_type & OP_ALG_ALGSEL_MASK) ==
+- OP_ALG_ALGSEL_AES) &&
+- ((ctx->class1_alg_type & OP_ALG_AAI_MASK) == OP_ALG_AAI_GCM))
+- is_gcm = true;
+-
+ len = desc_len(sh_desc);
+ init_job_desc_shared(desc, ptr, len, HDR_SHARE_DEFER | HDR_REVERSE);
+
+ if (contig & GIV_SRC_CONTIG) {
+- if (is_gcm)
+- src_dma = edesc->iv_dma;
+- else
+- src_dma = sg_dma_address(req->assoc);
++ src_dma = sg_dma_address(req->assoc);
+ in_options = 0;
+ } else {
+ src_dma = edesc->sec4_sg_dma;
+ sec4_sg_index += edesc->assoc_nents + 1 + edesc->src_nents;
+ in_options = LDST_SGF;
+ }
+- append_seq_in_ptr(desc, src_dma, req->assoclen + ivsize + req->cryptlen,
+- in_options);
++ append_seq_in_ptr(desc, src_dma, req->assoclen + ivsize +
++ req->cryptlen - authsize, in_options);
+
+ if (contig & GIV_DST_CONTIG) {
+ dst_dma = edesc->iv_dma;
+ } else {
+ if (likely(req->src == req->dst)) {
+ dst_dma = src_dma + sizeof(struct sec4_sg_entry) *
+- (edesc->assoc_nents +
+- (is_gcm ? 1 + edesc->src_nents : 0));
++ edesc->assoc_nents;
+ out_options = LDST_SGF;
+ } else {
+ dst_dma = edesc->sec4_sg_dma +
+@@ -2496,8 +1097,7 @@
+ }
+ }
+
+- append_seq_out_ptr(desc, dst_dma, ivsize + req->cryptlen + authsize,
+- out_options);
++ append_seq_out_ptr(desc, dst_dma, ivsize + req->cryptlen, out_options);
+ }
+
+ /*
+@@ -2516,10 +1116,10 @@
+ int len, sec4_sg_index = 0;
+
+ #ifdef DEBUG
+- print_hex_dump(KERN_ERR, "presciv@"__stringify(__LINE__)": ",
++ print_hex_dump(KERN_ERR, "presciv@"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, req->info,
+ ivsize, 1);
+- print_hex_dump(KERN_ERR, "src @"__stringify(__LINE__)": ",
++ print_hex_dump(KERN_ERR, "src @"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->src),
+ edesc->src_nents ? 100 : req->nbytes, 1);
+ #endif
+@@ -2532,7 +1132,7 @@
+ in_options = 0;
+ } else {
+ src_dma = edesc->sec4_sg_dma;
+- sec4_sg_index += edesc->src_nents + 1;
++ sec4_sg_index += (iv_contig ? 0 : 1) + edesc->src_nents;
+ in_options = LDST_SGF;
+ }
+ append_seq_in_ptr(desc, src_dma, req->nbytes + ivsize, in_options);
+@@ -2558,59 +1158,10 @@
+ }
+
+ /*
+- * Fill in ablkcipher givencrypt job descriptor
+- */
+-static void init_ablkcipher_giv_job(u32 *sh_desc, dma_addr_t ptr,
+- struct ablkcipher_edesc *edesc,
+- struct ablkcipher_request *req,
+- bool iv_contig)
+-{
+- struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req);
+- int ivsize = crypto_ablkcipher_ivsize(ablkcipher);
+- u32 *desc = edesc->hw_desc;
+- u32 out_options, in_options;
+- dma_addr_t dst_dma, src_dma;
+- int len, sec4_sg_index = 0;
+-
+-#ifdef DEBUG
+- print_hex_dump(KERN_ERR, "presciv@" __stringify(__LINE__) ": ",
+- DUMP_PREFIX_ADDRESS, 16, 4, req->info,
+- ivsize, 1);
+- print_hex_dump(KERN_ERR, "src @" __stringify(__LINE__) ": ",
+- DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->src),
+- edesc->src_nents ? 100 : req->nbytes, 1);
+-#endif
+-
+- len = desc_len(sh_desc);
+- init_job_desc_shared(desc, ptr, len, HDR_SHARE_DEFER | HDR_REVERSE);
+-
+- if (!edesc->src_nents) {
+- src_dma = sg_dma_address(req->src);
+- in_options = 0;
+- } else {
+- src_dma = edesc->sec4_sg_dma;
+- sec4_sg_index += edesc->src_nents;
+- in_options = LDST_SGF;
+- }
+- append_seq_in_ptr(desc, src_dma, req->nbytes, in_options);
+-
+- if (iv_contig) {
+- dst_dma = edesc->iv_dma;
+- out_options = 0;
+- } else {
+- dst_dma = edesc->sec4_sg_dma +
+- sec4_sg_index * sizeof(struct sec4_sg_entry);
+- out_options = LDST_SGF;
+- }
+- append_seq_out_ptr(desc, dst_dma, req->nbytes + ivsize, out_options);
+-}
+-
+-/*
+ * allocate and map the aead extended descriptor
+ */
+ static struct aead_edesc *aead_edesc_alloc(struct aead_request *req,
+- int desc_bytes, bool *all_contig_ptr,
+- bool encrypt)
++ int desc_bytes, bool *all_contig_ptr)
+ {
+ struct crypto_aead *aead = crypto_aead_reqtfm(req);
+ struct caam_ctx *ctx = crypto_aead_ctx(aead);
+@@ -2625,26 +1176,15 @@
+ bool assoc_chained = false, src_chained = false, dst_chained = false;
+ int ivsize = crypto_aead_ivsize(aead);
+ int sec4_sg_index, sec4_sg_len = 0, sec4_sg_bytes;
+- unsigned int authsize = ctx->authsize;
+- bool is_gcm = false;
+
+ assoc_nents = sg_count(req->assoc, req->assoclen, &assoc_chained);
++ src_nents = sg_count(req->src, req->cryptlen, &src_chained);
+
+- if (unlikely(req->dst != req->src)) {
+- src_nents = sg_count(req->src, req->cryptlen, &src_chained);
+- dst_nents = sg_count(req->dst,
+- req->cryptlen +
+- (encrypt ? authsize : (-authsize)),
+- &dst_chained);
+- } else {
+- src_nents = sg_count(req->src,
+- req->cryptlen +
+- (encrypt ? authsize : 0),
+- &src_chained);
+- }
++ if (unlikely(req->dst != req->src))
++ dst_nents = sg_count(req->dst, req->cryptlen, &dst_chained);
+
+ sgc = dma_map_sg_chained(jrdev, req->assoc, assoc_nents ? : 1,
+- DMA_TO_DEVICE, assoc_chained);
++ DMA_BIDIRECTIONAL, assoc_chained);
+ if (likely(req->src == req->dst)) {
+ sgc = dma_map_sg_chained(jrdev, req->src, src_nents ? : 1,
+ DMA_BIDIRECTIONAL, src_chained);
+@@ -2655,43 +1195,23 @@
+ DMA_FROM_DEVICE, dst_chained);
+ }
+
++ /* Check if data are contiguous */
+ iv_dma = dma_map_single(jrdev, req->iv, ivsize, DMA_TO_DEVICE);
+- if (dma_mapping_error(jrdev, iv_dma)) {
+- dev_err(jrdev, "unable to map IV\n");
+- return ERR_PTR(-ENOMEM);
+- }
+-
+- if (((ctx->class1_alg_type & OP_ALG_ALGSEL_MASK) ==
+- OP_ALG_ALGSEL_AES) &&
+- ((ctx->class1_alg_type & OP_ALG_AAI_MASK) == OP_ALG_AAI_GCM))
+- is_gcm = true;
+-
+- /*
+- * Check if data are contiguous.
+- * GCM expected input sequence: IV, AAD, text
+- * All other - expected input sequence: AAD, IV, text
+- */
+- if (is_gcm)
+- all_contig = (!assoc_nents &&
+- iv_dma + ivsize == sg_dma_address(req->assoc) &&
+- !src_nents && sg_dma_address(req->assoc) +
+- req->assoclen == sg_dma_address(req->src));
+- else
+- all_contig = (!assoc_nents && sg_dma_address(req->assoc) +
+- req->assoclen == iv_dma && !src_nents &&
+- iv_dma + ivsize == sg_dma_address(req->src));
+- if (!all_contig) {
++ if (assoc_nents || sg_dma_address(req->assoc) + req->assoclen !=
++ iv_dma || src_nents || iv_dma + ivsize !=
++ sg_dma_address(req->src)) {
++ all_contig = false;
+ assoc_nents = assoc_nents ? : 1;
+ src_nents = src_nents ? : 1;
+ sec4_sg_len = assoc_nents + 1 + src_nents;
+ }
+-
+ sec4_sg_len += dst_nents;
+
+ sec4_sg_bytes = sec4_sg_len * sizeof(struct sec4_sg_entry);
++ dma_sync_single_for_device(jrdev, iv_dma, ivsize, DMA_TO_DEVICE);
+
+ /* allocate space for base edesc and hw desc commands, link tables */
+- edesc = kmalloc(sizeof(struct aead_edesc) + desc_bytes +
++ edesc = kzalloc(sizeof(struct aead_edesc) + desc_bytes +
+ sec4_sg_bytes, GFP_DMA | flags);
+ if (!edesc) {
+ dev_err(jrdev, "could not allocate extended descriptor\n");
+@@ -2708,46 +1228,32 @@
+ edesc->sec4_sg_bytes = sec4_sg_bytes;
+ edesc->sec4_sg = (void *)edesc + sizeof(struct aead_edesc) +
+ desc_bytes;
++ edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg,
++ sec4_sg_bytes, DMA_TO_DEVICE);
+ *all_contig_ptr = all_contig;
+
+ sec4_sg_index = 0;
+ if (!all_contig) {
+- if (!is_gcm) {
+- sg_to_sec4_sg(req->assoc,
+- assoc_nents,
+- edesc->sec4_sg +
+- sec4_sg_index, 0);
+- sec4_sg_index += assoc_nents;
+- }
+-
++ sg_to_sec4_sg(req->assoc,
++ (assoc_nents ? : 1),
++ edesc->sec4_sg +
++ sec4_sg_index, 0);
++ sec4_sg_index += assoc_nents ? : 1;
+ dma_to_sec4_sg_one(edesc->sec4_sg + sec4_sg_index,
+ iv_dma, ivsize, 0);
+ sec4_sg_index += 1;
+-
+- if (is_gcm) {
+- sg_to_sec4_sg(req->assoc,
+- assoc_nents,
+- edesc->sec4_sg +
+- sec4_sg_index, 0);
+- sec4_sg_index += assoc_nents;
+- }
+-
+ sg_to_sec4_sg_last(req->src,
+- src_nents,
++ (src_nents ? : 1),
+ edesc->sec4_sg +
+ sec4_sg_index, 0);
+- sec4_sg_index += src_nents;
++ sec4_sg_index += src_nents ? : 1;
+ }
+ if (dst_nents) {
+ sg_to_sec4_sg_last(req->dst, dst_nents,
+ edesc->sec4_sg + sec4_sg_index, 0);
+ }
+- edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg,
+- sec4_sg_bytes, DMA_TO_DEVICE);
+- if (dma_mapping_error(jrdev, edesc->sec4_sg_dma)) {
+- dev_err(jrdev, "unable to map S/G table\n");
+- return ERR_PTR(-ENOMEM);
+- }
++ dma_sync_single_for_device(jrdev, edesc->sec4_sg_dma, sec4_sg_bytes,
++ DMA_TO_DEVICE);
+
+ return edesc;
+ }
+@@ -2762,9 +1268,11 @@
+ u32 *desc;
+ int ret = 0;
+
++ req->cryptlen += ctx->authsize;
++
+ /* allocate extended descriptor */
+ edesc = aead_edesc_alloc(req, DESC_JOB_IO_LEN *
+- CAAM_CMD_SZ, &all_contig, true);
++ CAAM_CMD_SZ, &all_contig);
+ if (IS_ERR(edesc))
+ return PTR_ERR(edesc);
+
+@@ -2772,7 +1280,7 @@
+ init_aead_job(ctx->sh_desc_enc, ctx->sh_desc_enc_dma, edesc, req,
+ all_contig, true);
+ #ifdef DEBUG
+- print_hex_dump(KERN_ERR, "aead jobdesc@"__stringify(__LINE__)": ",
++ print_hex_dump(KERN_ERR, "aead jobdesc@"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, edesc->hw_desc,
+ desc_bytes(edesc->hw_desc), 1);
+ #endif
+@@ -2801,12 +1309,12 @@
+
+ /* allocate extended descriptor */
+ edesc = aead_edesc_alloc(req, DESC_JOB_IO_LEN *
+- CAAM_CMD_SZ, &all_contig, false);
++ CAAM_CMD_SZ, &all_contig);
+ if (IS_ERR(edesc))
+ return PTR_ERR(edesc);
+
+ #ifdef DEBUG
+- print_hex_dump(KERN_ERR, "dec src@"__stringify(__LINE__)": ",
++ print_hex_dump(KERN_ERR, "dec src@"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->src),
+ req->cryptlen, 1);
+ #endif
+@@ -2815,7 +1323,7 @@
+ init_aead_job(ctx->sh_desc_dec,
+ ctx->sh_desc_dec_dma, edesc, req, all_contig, false);
+ #ifdef DEBUG
+- print_hex_dump(KERN_ERR, "aead jobdesc@"__stringify(__LINE__)": ",
++ print_hex_dump(KERN_ERR, "aead jobdesc@"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, edesc->hw_desc,
+ desc_bytes(edesc->hw_desc), 1);
+ #endif
+@@ -2853,17 +1361,15 @@
+ int ivsize = crypto_aead_ivsize(aead);
+ bool assoc_chained = false, src_chained = false, dst_chained = false;
+ int sec4_sg_index, sec4_sg_len = 0, sec4_sg_bytes;
+- bool is_gcm = false;
+
+ assoc_nents = sg_count(req->assoc, req->assoclen, &assoc_chained);
+ src_nents = sg_count(req->src, req->cryptlen, &src_chained);
+
+ if (unlikely(req->dst != req->src))
+- dst_nents = sg_count(req->dst, req->cryptlen + ctx->authsize,
+- &dst_chained);
++ dst_nents = sg_count(req->dst, req->cryptlen, &dst_chained);
+
+ sgc = dma_map_sg_chained(jrdev, req->assoc, assoc_nents ? : 1,
+- DMA_TO_DEVICE, assoc_chained);
++ DMA_BIDIRECTIONAL, assoc_chained);
+ if (likely(req->src == req->dst)) {
+ sgc = dma_map_sg_chained(jrdev, req->src, src_nents ? : 1,
+ DMA_BIDIRECTIONAL, src_chained);
+@@ -2874,64 +1380,32 @@
+ DMA_FROM_DEVICE, dst_chained);
+ }
+
++ /* Check if data are contiguous */
+ iv_dma = dma_map_single(jrdev, greq->giv, ivsize, DMA_TO_DEVICE);
+- if (dma_mapping_error(jrdev, iv_dma)) {
+- dev_err(jrdev, "unable to map IV\n");
+- return ERR_PTR(-ENOMEM);
+- }
+-
+- if (((ctx->class1_alg_type & OP_ALG_ALGSEL_MASK) ==
+- OP_ALG_ALGSEL_AES) &&
+- ((ctx->class1_alg_type & OP_ALG_AAI_MASK) == OP_ALG_AAI_GCM))
+- is_gcm = true;
+-
+- /*
+- * Check if data are contiguous.
+- * GCM expected input sequence: IV, AAD, text
+- * All other - expected input sequence: AAD, IV, text
+- */
+-
+- if (is_gcm) {
+- if (assoc_nents || iv_dma + ivsize !=
+- sg_dma_address(req->assoc) || src_nents ||
+- sg_dma_address(req->assoc) + req->assoclen !=
+- sg_dma_address(req->src))
+- contig &= ~GIV_SRC_CONTIG;
+- } else {
+- if (assoc_nents ||
+- sg_dma_address(req->assoc) + req->assoclen != iv_dma ||
+- src_nents || iv_dma + ivsize != sg_dma_address(req->src))
+- contig &= ~GIV_SRC_CONTIG;
+- }
+-
++ if (assoc_nents || sg_dma_address(req->assoc) + req->assoclen !=
++ iv_dma || src_nents || iv_dma + ivsize != sg_dma_address(req->src))
++ contig &= ~GIV_SRC_CONTIG;
+ if (dst_nents || iv_dma + ivsize != sg_dma_address(req->dst))
+ contig &= ~GIV_DST_CONTIG;
+-
++ if (unlikely(req->src != req->dst)) {
++ dst_nents = dst_nents ? : 1;
++ sec4_sg_len += 1;
++ }
+ if (!(contig & GIV_SRC_CONTIG)) {
+ assoc_nents = assoc_nents ? : 1;
+ src_nents = src_nents ? : 1;
+ sec4_sg_len += assoc_nents + 1 + src_nents;
+- if (req->src == req->dst &&
+- (src_nents || iv_dma + ivsize != sg_dma_address(req->src)))
+- contig &= ~GIV_DST_CONTIG;
+- }
+-
+- /*
+- * Add new sg entries for GCM output sequence.
+- * Expected output sequence: IV, encrypted text.
+- */
+- if (is_gcm && req->src == req->dst && !(contig & GIV_DST_CONTIG))
+- sec4_sg_len += 1 + src_nents;
+-
+- if (unlikely(req->src != req->dst)) {
+- dst_nents = dst_nents ? : 1;
+- sec4_sg_len += 1 + dst_nents;
++ if (likely(req->src == req->dst))
++ contig &= ~GIV_DST_CONTIG;
+ }
++ sec4_sg_len += dst_nents;
+
+ sec4_sg_bytes = sec4_sg_len * sizeof(struct sec4_sg_entry);
+
++ dma_sync_single_for_device(jrdev, iv_dma, ivsize, DMA_TO_DEVICE);
++
+ /* allocate space for base edesc and hw desc commands, link tables */
+- edesc = kmalloc(sizeof(struct aead_edesc) + desc_bytes +
++ edesc = kzalloc(sizeof(struct aead_edesc) + desc_bytes +
+ sec4_sg_bytes, GFP_DMA | flags);
+ if (!edesc) {
+ dev_err(jrdev, "could not allocate extended descriptor\n");
+@@ -2948,40 +1422,24 @@
+ edesc->sec4_sg_bytes = sec4_sg_bytes;
+ edesc->sec4_sg = (void *)edesc + sizeof(struct aead_edesc) +
+ desc_bytes;
++ edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg,
++ sec4_sg_bytes, DMA_TO_DEVICE);
+ *contig_ptr = contig;
+
+ sec4_sg_index = 0;
+ if (!(contig & GIV_SRC_CONTIG)) {
+- if (!is_gcm) {
+- sg_to_sec4_sg(req->assoc, assoc_nents,
+- edesc->sec4_sg + sec4_sg_index, 0);
+- sec4_sg_index += assoc_nents;
+- }
+-
++ sg_to_sec4_sg(req->assoc, assoc_nents,
++ edesc->sec4_sg +
++ sec4_sg_index, 0);
++ sec4_sg_index += assoc_nents;
+ dma_to_sec4_sg_one(edesc->sec4_sg + sec4_sg_index,
+ iv_dma, ivsize, 0);
+ sec4_sg_index += 1;
+-
+- if (is_gcm) {
+- sg_to_sec4_sg(req->assoc, assoc_nents,
+- edesc->sec4_sg + sec4_sg_index, 0);
+- sec4_sg_index += assoc_nents;
+- }
+-
+ sg_to_sec4_sg_last(req->src, src_nents,
+ edesc->sec4_sg +
+ sec4_sg_index, 0);
+ sec4_sg_index += src_nents;
+ }
+-
+- if (is_gcm && req->src == req->dst && !(contig & GIV_DST_CONTIG)) {
+- dma_to_sec4_sg_one(edesc->sec4_sg + sec4_sg_index,
+- iv_dma, ivsize, 0);
+- sec4_sg_index += 1;
+- sg_to_sec4_sg_last(req->src, src_nents,
+- edesc->sec4_sg + sec4_sg_index, 0);
+- }
+-
+ if (unlikely(req->src != req->dst && !(contig & GIV_DST_CONTIG))) {
+ dma_to_sec4_sg_one(edesc->sec4_sg + sec4_sg_index,
+ iv_dma, ivsize, 0);
+@@ -2989,12 +1447,8 @@
+ sg_to_sec4_sg_last(req->dst, dst_nents,
+ edesc->sec4_sg + sec4_sg_index, 0);
+ }
+- edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg,
+- sec4_sg_bytes, DMA_TO_DEVICE);
+- if (dma_mapping_error(jrdev, edesc->sec4_sg_dma)) {
+- dev_err(jrdev, "unable to map S/G table\n");
+- return ERR_PTR(-ENOMEM);
+- }
++ dma_sync_single_for_device(jrdev, edesc->sec4_sg_dma, sec4_sg_bytes,
++ DMA_TO_DEVICE);
+
+ return edesc;
+ }
+@@ -3010,6 +1464,8 @@
+ u32 *desc;
+ int ret = 0;
+
++ req->cryptlen += ctx->authsize;
++
+ /* allocate extended descriptor */
+ edesc = aead_giv_edesc_alloc(areq, DESC_JOB_IO_LEN *
+ CAAM_CMD_SZ, &contig);
+@@ -3018,7 +1474,7 @@
+ return PTR_ERR(edesc);
+
+ #ifdef DEBUG
+- print_hex_dump(KERN_ERR, "giv src@"__stringify(__LINE__)": ",
++ print_hex_dump(KERN_ERR, "giv src@"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->src),
+ req->cryptlen, 1);
+ #endif
+@@ -3027,7 +1483,7 @@
+ init_aead_giv_job(ctx->sh_desc_givenc,
+ ctx->sh_desc_givenc_dma, edesc, req, contig);
+ #ifdef DEBUG
+- print_hex_dump(KERN_ERR, "aead jobdesc@"__stringify(__LINE__)": ",
++ print_hex_dump(KERN_ERR, "aead jobdesc@"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, edesc->hw_desc,
+ desc_bytes(edesc->hw_desc), 1);
+ #endif
+@@ -3044,11 +1500,6 @@
+ return ret;
+ }
+
+-static int aead_null_givencrypt(struct aead_givcrypt_request *areq)
+-{
+- return aead_encrypt(&areq->areq);
+-}
+-
+ /*
+ * allocate and map the ablkcipher extended descriptor for ablkcipher
+ */
+@@ -3086,16 +1537,12 @@
+ DMA_FROM_DEVICE, dst_chained);
+ }
+
+- iv_dma = dma_map_single(jrdev, req->info, ivsize, DMA_TO_DEVICE);
+- if (dma_mapping_error(jrdev, iv_dma)) {
+- dev_err(jrdev, "unable to map IV\n");
+- return ERR_PTR(-ENOMEM);
+- }
+-
+ /*
+ * Check if iv can be contiguous with source and destination.
+ * If so, include it. If not, create scatterlist.
+ */
++ iv_dma = dma_map_single(jrdev, req->info, ivsize, DMA_TO_DEVICE);
++ dma_sync_single_for_device(jrdev, iv_dma, ivsize, DMA_TO_DEVICE);
+ if (!src_nents && iv_dma + ivsize == sg_dma_address(req->src))
+ iv_contig = true;
+ else
+@@ -3104,7 +1551,7 @@
+ sizeof(struct sec4_sg_entry);
+
+ /* allocate space for base edesc and hw desc commands, link tables */
+- edesc = kmalloc(sizeof(struct ablkcipher_edesc) + desc_bytes +
++ edesc = kzalloc(sizeof(struct ablkcipher_edesc) + desc_bytes +
+ sec4_sg_bytes, GFP_DMA | flags);
+ if (!edesc) {
+ dev_err(jrdev, "could not allocate extended descriptor\n");
+@@ -3134,15 +1581,13 @@
+
+ edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg,
+ sec4_sg_bytes, DMA_TO_DEVICE);
+- if (dma_mapping_error(jrdev, edesc->sec4_sg_dma)) {
+- dev_err(jrdev, "unable to map S/G table\n");
+- return ERR_PTR(-ENOMEM);
+- }
+-
+ edesc->iv_dma = iv_dma;
+
++ dma_sync_single_for_device(jrdev, edesc->sec4_sg_dma, sec4_sg_bytes,
++ DMA_TO_DEVICE);
++
+ #ifdef DEBUG
+- print_hex_dump(KERN_ERR, "ablkcipher sec4_sg@"__stringify(__LINE__)": ",
++ print_hex_dump(KERN_ERR, "ablkcipher sec4_sg@"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, edesc->sec4_sg,
+ sec4_sg_bytes, 1);
+ #endif
+@@ -3171,7 +1616,7 @@
+ init_ablkcipher_job(ctx->sh_desc_enc,
+ ctx->sh_desc_enc_dma, edesc, req, iv_contig);
+ #ifdef DEBUG
+- print_hex_dump(KERN_ERR, "ablkcipher jobdesc@"__stringify(__LINE__)": ",
++ print_hex_dump(KERN_ERR, "ablkcipher jobdesc@"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, edesc->hw_desc,
+ desc_bytes(edesc->hw_desc), 1);
+ #endif
+@@ -3209,7 +1654,7 @@
+ ctx->sh_desc_dec_dma, edesc, req, iv_contig);
+ desc = edesc->hw_desc;
+ #ifdef DEBUG
+- print_hex_dump(KERN_ERR, "ablkcipher jobdesc@"__stringify(__LINE__)": ",
++ print_hex_dump(KERN_ERR, "ablkcipher jobdesc@"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, edesc->hw_desc,
+ desc_bytes(edesc->hw_desc), 1);
+ #endif
+@@ -3225,291 +1670,28 @@
+ return ret;
+ }
+
+-/*
+- * allocate and map the ablkcipher extended descriptor
+- * for ablkcipher givencrypt
+- */
+-static struct ablkcipher_edesc *ablkcipher_giv_edesc_alloc(
+- struct skcipher_givcrypt_request *greq,
+- int desc_bytes,
+- bool *iv_contig_out)
+-{
+- struct ablkcipher_request *req = &greq->creq;
+- struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req);
+- struct caam_ctx *ctx = crypto_ablkcipher_ctx(ablkcipher);
+- struct device *jrdev = ctx->jrdev;
+- gfp_t flags = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG |
+- CRYPTO_TFM_REQ_MAY_SLEEP)) ?
+- GFP_KERNEL : GFP_ATOMIC;
+- int src_nents, dst_nents = 0, sec4_sg_bytes;
+- struct ablkcipher_edesc *edesc;
+- dma_addr_t iv_dma = 0;
+- bool iv_contig = false;
+- int sgc;
+- int ivsize = crypto_ablkcipher_ivsize(ablkcipher);
+- bool src_chained = false, dst_chained = false;
+- int sec4_sg_index;
+-
+- src_nents = sg_count(req->src, req->nbytes, &src_chained);
+-
+- if (unlikely(req->dst != req->src))
+- dst_nents = sg_count(req->dst, req->nbytes, &dst_chained);
+-
+- if (likely(req->src == req->dst)) {
+- sgc = dma_map_sg_chained(jrdev, req->src, src_nents ? : 1,
+- DMA_BIDIRECTIONAL, src_chained);
+- } else {
+- sgc = dma_map_sg_chained(jrdev, req->src, src_nents ? : 1,
+- DMA_TO_DEVICE, src_chained);
+- sgc = dma_map_sg_chained(jrdev, req->dst, dst_nents ? : 1,
+- DMA_FROM_DEVICE, dst_chained);
+- }
+-
+- /*
+- * Check if iv can be contiguous with source and destination.
+- * If so, include it. If not, create scatterlist.
+- */
+- iv_dma = dma_map_single(jrdev, greq->giv, ivsize, DMA_TO_DEVICE);
+- if (dma_mapping_error(jrdev, iv_dma)) {
+- dev_err(jrdev, "unable to map IV\n");
+- return ERR_PTR(-ENOMEM);
+- }
+-
+- if (!dst_nents && iv_dma + ivsize == sg_dma_address(req->dst))
+- iv_contig = true;
+- else
+- dst_nents = dst_nents ? : 1;
+- sec4_sg_bytes = ((iv_contig ? 0 : 1) + src_nents + dst_nents) *
+- sizeof(struct sec4_sg_entry);
+-
+- /* allocate space for base edesc and hw desc commands, link tables */
+- edesc = kmalloc(sizeof(*edesc) + desc_bytes +
+- sec4_sg_bytes, GFP_DMA | flags);
+- if (!edesc) {
+- dev_err(jrdev, "could not allocate extended descriptor\n");
+- return ERR_PTR(-ENOMEM);
+- }
+-
+- edesc->src_nents = src_nents;
+- edesc->src_chained = src_chained;
+- edesc->dst_nents = dst_nents;
+- edesc->dst_chained = dst_chained;
+- edesc->sec4_sg_bytes = sec4_sg_bytes;
+- edesc->sec4_sg = (void *)edesc + sizeof(struct ablkcipher_edesc) +
+- desc_bytes;
+-
+- sec4_sg_index = 0;
+- if (src_nents) {
+- sg_to_sec4_sg_last(req->src, src_nents, edesc->sec4_sg, 0);
+- sec4_sg_index += src_nents;
+- }
+-
+- if (!iv_contig) {
+- dma_to_sec4_sg_one(edesc->sec4_sg + sec4_sg_index,
+- iv_dma, ivsize, 0);
+- sec4_sg_index += 1;
+- sg_to_sec4_sg_last(req->dst, dst_nents,
+- edesc->sec4_sg + sec4_sg_index, 0);
+- }
+-
+- edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg,
+- sec4_sg_bytes, DMA_TO_DEVICE);
+- if (dma_mapping_error(jrdev, edesc->sec4_sg_dma)) {
+- dev_err(jrdev, "unable to map S/G table\n");
+- return ERR_PTR(-ENOMEM);
+- }
+- edesc->iv_dma = iv_dma;
+-
+-#ifdef DEBUG
+- print_hex_dump(KERN_ERR,
+- "ablkcipher sec4_sg@" __stringify(__LINE__) ": ",
+- DUMP_PREFIX_ADDRESS, 16, 4, edesc->sec4_sg,
+- sec4_sg_bytes, 1);
+-#endif
+-
+- *iv_contig_out = iv_contig;
+- return edesc;
+-}
+-
+-static int ablkcipher_givencrypt(struct skcipher_givcrypt_request *creq)
+-{
+- struct ablkcipher_request *req = &creq->creq;
+- struct ablkcipher_edesc *edesc;
+- struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req);
+- struct caam_ctx *ctx = crypto_ablkcipher_ctx(ablkcipher);
+- struct device *jrdev = ctx->jrdev;
+- bool iv_contig;
+- u32 *desc;
+- int ret = 0;
+-
+- /* allocate extended descriptor */
+- edesc = ablkcipher_giv_edesc_alloc(creq, DESC_JOB_IO_LEN *
+- CAAM_CMD_SZ, &iv_contig);
+- if (IS_ERR(edesc))
+- return PTR_ERR(edesc);
+-
+- /* Create and submit job descriptor*/
+- init_ablkcipher_giv_job(ctx->sh_desc_givenc, ctx->sh_desc_givenc_dma,
+- edesc, req, iv_contig);
+-#ifdef DEBUG
+- print_hex_dump(KERN_ERR,
+- "ablkcipher jobdesc@" __stringify(__LINE__) ": ",
+- DUMP_PREFIX_ADDRESS, 16, 4, edesc->hw_desc,
+- desc_bytes(edesc->hw_desc), 1);
+-#endif
+- desc = edesc->hw_desc;
+- ret = caam_jr_enqueue(jrdev, desc, ablkcipher_encrypt_done, req);
+-
+- if (!ret) {
+- ret = -EINPROGRESS;
+- } else {
+- ablkcipher_unmap(jrdev, edesc, req);
+- kfree(edesc);
+- }
+-
+- return ret;
+-}
+-
+ #define template_aead template_u.aead
+ #define template_ablkcipher template_u.ablkcipher
+ struct caam_alg_template {
+ char name[CRYPTO_MAX_ALG_NAME];
+- char driver_name[CRYPTO_MAX_ALG_NAME];
+- unsigned int blocksize;
+- u32 type;
+- union {
+- struct ablkcipher_alg ablkcipher;
+- struct aead_alg aead;
+- struct blkcipher_alg blkcipher;
+- struct cipher_alg cipher;
+- struct compress_alg compress;
+- struct rng_alg rng;
+- } template_u;
+- u32 class1_alg_type;
+- u32 class2_alg_type;
+- u32 alg_op;
+-};
+-
+-static struct caam_alg_template driver_algs[] = {
+- /* single-pass ipsec_esp descriptor */
+- {
+- .name = "authenc(hmac(md5),ecb(cipher_null))",
+- .driver_name = "authenc-hmac-md5-ecb-cipher_null-caam",
+- .blocksize = NULL_BLOCK_SIZE,
+- .type = CRYPTO_ALG_TYPE_AEAD,
+- .template_aead = {
+- .setkey = aead_setkey,
+- .setauthsize = aead_setauthsize,
+- .encrypt = aead_encrypt,
+- .decrypt = aead_decrypt,
+- .givencrypt = aead_null_givencrypt,
+- .geniv = "<built-in>",
+- .ivsize = NULL_IV_SIZE,
+- .maxauthsize = MD5_DIGEST_SIZE,
+- },
+- .class1_alg_type = 0,
+- .class2_alg_type = OP_ALG_ALGSEL_MD5 | OP_ALG_AAI_HMAC_PRECOMP,
+- .alg_op = OP_ALG_ALGSEL_MD5 | OP_ALG_AAI_HMAC,
+- },
+- {
+- .name = "authenc(hmac(sha1),ecb(cipher_null))",
+- .driver_name = "authenc-hmac-sha1-ecb-cipher_null-caam",
+- .blocksize = NULL_BLOCK_SIZE,
+- .type = CRYPTO_ALG_TYPE_AEAD,
+- .template_aead = {
+- .setkey = aead_setkey,
+- .setauthsize = aead_setauthsize,
+- .encrypt = aead_encrypt,
+- .decrypt = aead_decrypt,
+- .givencrypt = aead_null_givencrypt,
+- .geniv = "<built-in>",
+- .ivsize = NULL_IV_SIZE,
+- .maxauthsize = SHA1_DIGEST_SIZE,
+- },
+- .class1_alg_type = 0,
+- .class2_alg_type = OP_ALG_ALGSEL_SHA1 | OP_ALG_AAI_HMAC_PRECOMP,
+- .alg_op = OP_ALG_ALGSEL_SHA1 | OP_ALG_AAI_HMAC,
+- },
+- {
+- .name = "authenc(hmac(sha224),ecb(cipher_null))",
+- .driver_name = "authenc-hmac-sha224-ecb-cipher_null-caam",
+- .blocksize = NULL_BLOCK_SIZE,
+- .type = CRYPTO_ALG_TYPE_AEAD,
+- .template_aead = {
+- .setkey = aead_setkey,
+- .setauthsize = aead_setauthsize,
+- .encrypt = aead_encrypt,
+- .decrypt = aead_decrypt,
+- .givencrypt = aead_null_givencrypt,
+- .geniv = "<built-in>",
+- .ivsize = NULL_IV_SIZE,
+- .maxauthsize = SHA224_DIGEST_SIZE,
+- },
+- .class1_alg_type = 0,
+- .class2_alg_type = OP_ALG_ALGSEL_SHA224 |
+- OP_ALG_AAI_HMAC_PRECOMP,
+- .alg_op = OP_ALG_ALGSEL_SHA224 | OP_ALG_AAI_HMAC,
+- },
+- {
+- .name = "authenc(hmac(sha256),ecb(cipher_null))",
+- .driver_name = "authenc-hmac-sha256-ecb-cipher_null-caam",
+- .blocksize = NULL_BLOCK_SIZE,
+- .type = CRYPTO_ALG_TYPE_AEAD,
+- .template_aead = {
+- .setkey = aead_setkey,
+- .setauthsize = aead_setauthsize,
+- .encrypt = aead_encrypt,
+- .decrypt = aead_decrypt,
+- .givencrypt = aead_null_givencrypt,
+- .geniv = "<built-in>",
+- .ivsize = NULL_IV_SIZE,
+- .maxauthsize = SHA256_DIGEST_SIZE,
+- },
+- .class1_alg_type = 0,
+- .class2_alg_type = OP_ALG_ALGSEL_SHA256 |
+- OP_ALG_AAI_HMAC_PRECOMP,
+- .alg_op = OP_ALG_ALGSEL_SHA256 | OP_ALG_AAI_HMAC,
+- },
+- {
+- .name = "authenc(hmac(sha384),ecb(cipher_null))",
+- .driver_name = "authenc-hmac-sha384-ecb-cipher_null-caam",
+- .blocksize = NULL_BLOCK_SIZE,
+- .type = CRYPTO_ALG_TYPE_AEAD,
+- .template_aead = {
+- .setkey = aead_setkey,
+- .setauthsize = aead_setauthsize,
+- .encrypt = aead_encrypt,
+- .decrypt = aead_decrypt,
+- .givencrypt = aead_null_givencrypt,
+- .geniv = "<built-in>",
+- .ivsize = NULL_IV_SIZE,
+- .maxauthsize = SHA384_DIGEST_SIZE,
+- },
+- .class1_alg_type = 0,
+- .class2_alg_type = OP_ALG_ALGSEL_SHA384 |
+- OP_ALG_AAI_HMAC_PRECOMP,
+- .alg_op = OP_ALG_ALGSEL_SHA384 | OP_ALG_AAI_HMAC,
+- },
+- {
+- .name = "authenc(hmac(sha512),ecb(cipher_null))",
+- .driver_name = "authenc-hmac-sha512-ecb-cipher_null-caam",
+- .blocksize = NULL_BLOCK_SIZE,
+- .type = CRYPTO_ALG_TYPE_AEAD,
+- .template_aead = {
+- .setkey = aead_setkey,
+- .setauthsize = aead_setauthsize,
+- .encrypt = aead_encrypt,
+- .decrypt = aead_decrypt,
+- .givencrypt = aead_null_givencrypt,
+- .geniv = "<built-in>",
+- .ivsize = NULL_IV_SIZE,
+- .maxauthsize = SHA512_DIGEST_SIZE,
+- },
+- .class1_alg_type = 0,
+- .class2_alg_type = OP_ALG_ALGSEL_SHA512 |
+- OP_ALG_AAI_HMAC_PRECOMP,
+- .alg_op = OP_ALG_ALGSEL_SHA512 | OP_ALG_AAI_HMAC,
+- },
++ char driver_name[CRYPTO_MAX_ALG_NAME];
++ unsigned int blocksize;
++ u32 type;
++ union {
++ struct ablkcipher_alg ablkcipher;
++ struct aead_alg aead;
++ struct blkcipher_alg blkcipher;
++ struct cipher_alg cipher;
++ struct compress_alg compress;
++ struct rng_alg rng;
++ } template_u;
++ u32 class1_alg_type;
++ u32 class2_alg_type;
++ u32 alg_op;
++};
++
++static struct caam_alg_template driver_algs[] = {
++ /* single-pass ipsec_esp descriptor */
+ {
+ .name = "authenc(hmac(md5),cbc(aes))",
+ .driver_name = "authenc-hmac-md5-cbc-aes-caam",
+@@ -3865,188 +2047,81 @@
+ OP_ALG_AAI_HMAC_PRECOMP,
+ .alg_op = OP_ALG_ALGSEL_SHA512 | OP_ALG_AAI_HMAC,
+ },
++ /* ablkcipher descriptor */
+ {
+- .name = "authenc(hmac(md5),rfc3686(ctr(aes)))",
+- .driver_name = "authenc-hmac-md5-rfc3686-ctr-aes-caam",
+- .blocksize = 1,
+- .type = CRYPTO_ALG_TYPE_AEAD,
+- .template_aead = {
+- .setkey = aead_setkey,
+- .setauthsize = aead_setauthsize,
+- .encrypt = aead_encrypt,
+- .decrypt = aead_decrypt,
+- .givencrypt = aead_givencrypt,
+- .geniv = "<built-in>",
+- .ivsize = CTR_RFC3686_IV_SIZE,
+- .maxauthsize = MD5_DIGEST_SIZE,
+- },
+- .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CTR_MOD128,
+- .class2_alg_type = OP_ALG_ALGSEL_MD5 | OP_ALG_AAI_HMAC_PRECOMP,
+- .alg_op = OP_ALG_ALGSEL_MD5 | OP_ALG_AAI_HMAC,
+- },
+- {
+- .name = "authenc(hmac(sha1),rfc3686(ctr(aes)))",
+- .driver_name = "authenc-hmac-sha1-rfc3686-ctr-aes-caam",
+- .blocksize = 1,
+- .type = CRYPTO_ALG_TYPE_AEAD,
+- .template_aead = {
+- .setkey = aead_setkey,
+- .setauthsize = aead_setauthsize,
+- .encrypt = aead_encrypt,
+- .decrypt = aead_decrypt,
+- .givencrypt = aead_givencrypt,
+- .geniv = "<built-in>",
+- .ivsize = CTR_RFC3686_IV_SIZE,
+- .maxauthsize = SHA1_DIGEST_SIZE,
+- },
+- .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CTR_MOD128,
+- .class2_alg_type = OP_ALG_ALGSEL_SHA1 | OP_ALG_AAI_HMAC_PRECOMP,
+- .alg_op = OP_ALG_ALGSEL_SHA1 | OP_ALG_AAI_HMAC,
+- },
+- {
+- .name = "authenc(hmac(sha224),rfc3686(ctr(aes)))",
+- .driver_name = "authenc-hmac-sha224-rfc3686-ctr-aes-caam",
+- .blocksize = 1,
+- .type = CRYPTO_ALG_TYPE_AEAD,
+- .template_aead = {
+- .setkey = aead_setkey,
+- .setauthsize = aead_setauthsize,
+- .encrypt = aead_encrypt,
+- .decrypt = aead_decrypt,
+- .givencrypt = aead_givencrypt,
+- .geniv = "<built-in>",
+- .ivsize = CTR_RFC3686_IV_SIZE,
+- .maxauthsize = SHA224_DIGEST_SIZE,
++ .name = "ecb(des)",
++ .driver_name = "ecb-des-caam",
++ .blocksize = DES_BLOCK_SIZE,
++ .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
++ .template_ablkcipher = {
++ .setkey = ablkcipher_setkey,
++ .encrypt = ablkcipher_encrypt,
++ .decrypt = ablkcipher_decrypt,
++ .geniv = "eseqiv",
++ .min_keysize = DES_KEY_SIZE,
++ .max_keysize = DES_KEY_SIZE,
++ .ivsize = DES_BLOCK_SIZE,
+ },
+- .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CTR_MOD128,
+- .class2_alg_type = OP_ALG_ALGSEL_SHA224 |
+- OP_ALG_AAI_HMAC_PRECOMP,
+- .alg_op = OP_ALG_ALGSEL_SHA224 | OP_ALG_AAI_HMAC,
++ .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_ECB,
+ },
+ {
+- .name = "authenc(hmac(sha256),rfc3686(ctr(aes)))",
+- .driver_name = "authenc-hmac-sha256-rfc3686-ctr-aes-caam",
+- .blocksize = 1,
+- .type = CRYPTO_ALG_TYPE_AEAD,
+- .template_aead = {
+- .setkey = aead_setkey,
+- .setauthsize = aead_setauthsize,
+- .encrypt = aead_encrypt,
+- .decrypt = aead_decrypt,
+- .givencrypt = aead_givencrypt,
+- .geniv = "<built-in>",
+- .ivsize = CTR_RFC3686_IV_SIZE,
+- .maxauthsize = SHA256_DIGEST_SIZE,
+- },
+- .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CTR_MOD128,
+- .class2_alg_type = OP_ALG_ALGSEL_SHA256 |
+- OP_ALG_AAI_HMAC_PRECOMP,
+- .alg_op = OP_ALG_ALGSEL_SHA256 | OP_ALG_AAI_HMAC,
++ .name = "ecb(arc4)",
++ .driver_name = "ecb-arc4-caam",
++ .blocksize = ARC4_BLOCK_SIZE,
++ .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
++ .template_ablkcipher = {
++ .setkey = ablkcipher_setkey,
++ .encrypt = ablkcipher_encrypt,
++ .decrypt = ablkcipher_decrypt,
++ .geniv = "eseqiv",
++ .min_keysize = ARC4_MIN_KEY_SIZE,
++ .max_keysize = ARC4_MAX_KEY_SIZE,
++ .ivsize = ARC4_BLOCK_SIZE,
++ },
++ .class1_alg_type = OP_ALG_ALGSEL_ARC4 | OP_ALG_AAI_ECB
+ },
+ {
+- .name = "authenc(hmac(sha384),rfc3686(ctr(aes)))",
+- .driver_name = "authenc-hmac-sha384-rfc3686-ctr-aes-caam",
+- .blocksize = 1,
+- .type = CRYPTO_ALG_TYPE_AEAD,
+- .template_aead = {
+- .setkey = aead_setkey,
+- .setauthsize = aead_setauthsize,
+- .encrypt = aead_encrypt,
+- .decrypt = aead_decrypt,
+- .givencrypt = aead_givencrypt,
+- .geniv = "<built-in>",
+- .ivsize = CTR_RFC3686_IV_SIZE,
+- .maxauthsize = SHA384_DIGEST_SIZE,
++ .name = "ecb(aes)",
++ .driver_name = "ecb-aes-caam",
++ .blocksize = AES_BLOCK_SIZE,
++ .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
++ .template_ablkcipher = {
++ .setkey = ablkcipher_setkey,
++ .encrypt = ablkcipher_encrypt,
++ .decrypt = ablkcipher_decrypt,
++ .geniv = "eseqiv",
++ .min_keysize = AES_MIN_KEY_SIZE,
++ .max_keysize = AES_MAX_KEY_SIZE,
++ .ivsize = AES_BLOCK_SIZE,
+ },
+- .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CTR_MOD128,
+- .class2_alg_type = OP_ALG_ALGSEL_SHA384 |
+- OP_ALG_AAI_HMAC_PRECOMP,
+- .alg_op = OP_ALG_ALGSEL_SHA384 | OP_ALG_AAI_HMAC,
++ .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_ECB,
+ },
+ {
+- .name = "authenc(hmac(sha512),rfc3686(ctr(aes)))",
+- .driver_name = "authenc-hmac-sha512-rfc3686-ctr-aes-caam",
+- .blocksize = 1,
+- .type = CRYPTO_ALG_TYPE_AEAD,
+- .template_aead = {
+- .setkey = aead_setkey,
+- .setauthsize = aead_setauthsize,
+- .encrypt = aead_encrypt,
+- .decrypt = aead_decrypt,
+- .givencrypt = aead_givencrypt,
+- .geniv = "<built-in>",
+- .ivsize = CTR_RFC3686_IV_SIZE,
+- .maxauthsize = SHA512_DIGEST_SIZE,
++ .name = "ctr(aes)",
++ .driver_name = "ctr-aes-caam",
++ .blocksize = AES_BLOCK_SIZE,
++ .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
++ .template_ablkcipher = {
++ .setkey = ablkcipher_setkey,
++ .encrypt = ablkcipher_encrypt,
++ .decrypt = ablkcipher_decrypt,
++ .geniv = "eseqiv",
++ .min_keysize = AES_MIN_KEY_SIZE,
++ .max_keysize = AES_MAX_KEY_SIZE,
++ .ivsize = AES_BLOCK_SIZE,
+ },
+ .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CTR_MOD128,
+- .class2_alg_type = OP_ALG_ALGSEL_SHA512 |
+- OP_ALG_AAI_HMAC_PRECOMP,
+- .alg_op = OP_ALG_ALGSEL_SHA512 | OP_ALG_AAI_HMAC,
+- },
+- {
+- .name = "rfc4106(gcm(aes))",
+- .driver_name = "rfc4106-gcm-aes-caam",
+- .blocksize = 1,
+- .type = CRYPTO_ALG_TYPE_AEAD,
+- .template_aead = {
+- .setkey = rfc4106_setkey,
+- .setauthsize = rfc4106_setauthsize,
+- .encrypt = aead_encrypt,
+- .decrypt = aead_decrypt,
+- .givencrypt = aead_givencrypt,
+- .geniv = "<built-in>",
+- .ivsize = 8,
+- .maxauthsize = AES_BLOCK_SIZE,
+- },
+- .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_GCM,
+- },
+- {
+- .name = "rfc4543(gcm(aes))",
+- .driver_name = "rfc4543-gcm-aes-caam",
+- .blocksize = 1,
+- .type = CRYPTO_ALG_TYPE_AEAD,
+- .template_aead = {
+- .setkey = rfc4543_setkey,
+- .setauthsize = rfc4543_setauthsize,
+- .encrypt = aead_encrypt,
+- .decrypt = aead_decrypt,
+- .givencrypt = aead_givencrypt,
+- .geniv = "<built-in>",
+- .ivsize = 8,
+- .maxauthsize = AES_BLOCK_SIZE,
+- },
+- .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_GCM,
+- },
+- /* Galois Counter Mode */
+- {
+- .name = "gcm(aes)",
+- .driver_name = "gcm-aes-caam",
+- .blocksize = 1,
+- .type = CRYPTO_ALG_TYPE_AEAD,
+- .template_aead = {
+- .setkey = gcm_setkey,
+- .setauthsize = gcm_setauthsize,
+- .encrypt = aead_encrypt,
+- .decrypt = aead_decrypt,
+- .givencrypt = NULL,
+- .geniv = "<built-in>",
+- .ivsize = 12,
+- .maxauthsize = AES_BLOCK_SIZE,
+- },
+- .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_GCM,
+ },
+- /* ablkcipher descriptor */
+ {
+ .name = "cbc(aes)",
+ .driver_name = "cbc-aes-caam",
+ .blocksize = AES_BLOCK_SIZE,
+- .type = CRYPTO_ALG_TYPE_GIVCIPHER,
++ .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
+ .template_ablkcipher = {
+ .setkey = ablkcipher_setkey,
+ .encrypt = ablkcipher_encrypt,
+ .decrypt = ablkcipher_decrypt,
+- .givencrypt = ablkcipher_givencrypt,
+- .geniv = "<built-in>",
++ .geniv = "eseqiv",
+ .min_keysize = AES_MIN_KEY_SIZE,
+ .max_keysize = AES_MAX_KEY_SIZE,
+ .ivsize = AES_BLOCK_SIZE,
+@@ -4054,16 +2129,31 @@
+ .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
+ },
+ {
++ .name = "ecb(des3_ede)",
++ .driver_name = "ecb-des3-caam",
++ .blocksize = DES3_EDE_BLOCK_SIZE,
++ .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
++ .template_ablkcipher = {
++ .setkey = ablkcipher_setkey,
++ .encrypt = ablkcipher_encrypt,
++ .decrypt = ablkcipher_decrypt,
++ .geniv = "eseqiv",
++ .min_keysize = DES3_EDE_KEY_SIZE,
++ .max_keysize = DES3_EDE_KEY_SIZE,
++ .ivsize = DES3_EDE_BLOCK_SIZE,
++ },
++ .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_ECB,
++ },
++ {
+ .name = "cbc(des3_ede)",
+ .driver_name = "cbc-3des-caam",
+ .blocksize = DES3_EDE_BLOCK_SIZE,
+- .type = CRYPTO_ALG_TYPE_GIVCIPHER,
++ .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
+ .template_ablkcipher = {
+ .setkey = ablkcipher_setkey,
+ .encrypt = ablkcipher_encrypt,
+ .decrypt = ablkcipher_decrypt,
+- .givencrypt = ablkcipher_givencrypt,
+- .geniv = "<built-in>",
++ .geniv = "eseqiv",
+ .min_keysize = DES3_EDE_KEY_SIZE,
+ .max_keysize = DES3_EDE_KEY_SIZE,
+ .ivsize = DES3_EDE_BLOCK_SIZE,
+@@ -4074,58 +2164,23 @@
+ .name = "cbc(des)",
+ .driver_name = "cbc-des-caam",
+ .blocksize = DES_BLOCK_SIZE,
+- .type = CRYPTO_ALG_TYPE_GIVCIPHER,
++ .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
+ .template_ablkcipher = {
+ .setkey = ablkcipher_setkey,
+ .encrypt = ablkcipher_encrypt,
+ .decrypt = ablkcipher_decrypt,
+- .givencrypt = ablkcipher_givencrypt,
+- .geniv = "<built-in>",
++ .geniv = "eseqiv",
+ .min_keysize = DES_KEY_SIZE,
+ .max_keysize = DES_KEY_SIZE,
+ .ivsize = DES_BLOCK_SIZE,
+ },
+ .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
+- },
+- {
+- .name = "ctr(aes)",
+- .driver_name = "ctr-aes-caam",
+- .blocksize = 1,
+- .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
+- .template_ablkcipher = {
+- .setkey = ablkcipher_setkey,
+- .encrypt = ablkcipher_encrypt,
+- .decrypt = ablkcipher_decrypt,
+- .geniv = "chainiv",
+- .min_keysize = AES_MIN_KEY_SIZE,
+- .max_keysize = AES_MAX_KEY_SIZE,
+- .ivsize = AES_BLOCK_SIZE,
+- },
+- .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CTR_MOD128,
+- },
+- {
+- .name = "rfc3686(ctr(aes))",
+- .driver_name = "rfc3686-ctr-aes-caam",
+- .blocksize = 1,
+- .type = CRYPTO_ALG_TYPE_GIVCIPHER,
+- .template_ablkcipher = {
+- .setkey = ablkcipher_setkey,
+- .encrypt = ablkcipher_encrypt,
+- .decrypt = ablkcipher_decrypt,
+- .givencrypt = ablkcipher_givencrypt,
+- .geniv = "<built-in>",
+- .min_keysize = AES_MIN_KEY_SIZE +
+- CTR_RFC3686_NONCE_SIZE,
+- .max_keysize = AES_MAX_KEY_SIZE +
+- CTR_RFC3686_NONCE_SIZE,
+- .ivsize = CTR_RFC3686_IV_SIZE,
+- },
+- .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CTR_MOD128,
+ }
+ };
+
+ struct caam_crypto_alg {
+ struct list_head entry;
++ struct device *ctrldev;
+ int class1_alg_type;
+ int class2_alg_type;
+ int alg_op;
+@@ -4138,12 +2193,14 @@
+ struct caam_crypto_alg *caam_alg =
+ container_of(alg, struct caam_crypto_alg, crypto_alg);
+ struct caam_ctx *ctx = crypto_tfm_ctx(tfm);
++ struct caam_drv_private *priv = dev_get_drvdata(caam_alg->ctrldev);
++ int tgt_jr = atomic_inc_return(&priv->tfm_count);
+
+- ctx->jrdev = caam_jr_alloc();
+- if (IS_ERR(ctx->jrdev)) {
+- pr_err("Job Ring Device allocation for transform failed\n");
+- return PTR_ERR(ctx->jrdev);
+- }
++ /*
++ * distribute tfms across job rings to ensure in-order
++ * crypto request processing per tfm
++ */
++ ctx->jrdev = priv->algapi_jr[(tgt_jr / 2) % priv->num_jrs_for_algapi];
+
+ /* copy descriptor header template value */
+ ctx->class1_alg_type = OP_TYPE_CLASS1_ALG | caam_alg->class1_alg_type;
+@@ -4170,31 +2227,57 @@
+ dma_unmap_single(ctx->jrdev, ctx->sh_desc_givenc_dma,
+ desc_bytes(ctx->sh_desc_givenc),
+ DMA_TO_DEVICE);
+- if (ctx->key_dma &&
+- !dma_mapping_error(ctx->jrdev, ctx->key_dma))
+- dma_unmap_single(ctx->jrdev, ctx->key_dma,
+- ctx->enckeylen + ctx->split_key_pad_len,
+- DMA_TO_DEVICE);
+-
+- caam_jr_free(ctx->jrdev);
+ }
+
+ static void __exit caam_algapi_exit(void)
+ {
+
++ struct device_node *dev_node;
++ struct platform_device *pdev;
++ struct device *ctrldev;
++ struct caam_drv_private *priv;
+ struct caam_crypto_alg *t_alg, *n;
++ int i, err;
++
++ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
++ if (!dev_node) {
++ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec4.0");
++ if (!dev_node)
++ return;
++ }
++
++ pdev = of_find_device_by_node(dev_node);
++ if (!pdev) {
++ of_node_put(dev_node);
++ return;
++ }
+
+- if (!alg_list.next)
++ ctrldev = &pdev->dev;
++ priv = dev_get_drvdata(ctrldev);
++
++ if (!priv->alg_list.next) {
++ of_node_put(dev_node);
+ return;
++ }
+
+- list_for_each_entry_safe(t_alg, n, &alg_list, entry) {
++ list_for_each_entry_safe(t_alg, n, &priv->alg_list, entry) {
+ crypto_unregister_alg(&t_alg->crypto_alg);
+ list_del(&t_alg->entry);
+ kfree(t_alg);
+ }
++
++ for (i = 0; i < priv->total_jobrs; i++) {
++ err = caam_jr_deregister(priv->algapi_jr[i]);
++ if (err < 0)
++ break;
++ }
++ kfree(priv->algapi_jr);
++
++ of_node_put(dev_node);
+ }
+
+-static struct caam_crypto_alg *caam_alg_alloc(struct caam_alg_template
++static struct caam_crypto_alg *caam_alg_alloc(struct device *ctrldev,
++ struct caam_alg_template
+ *template)
+ {
+ struct caam_crypto_alg *t_alg;
+@@ -4202,7 +2285,7 @@
+
+ t_alg = kzalloc(sizeof(struct caam_crypto_alg), GFP_KERNEL);
+ if (!t_alg) {
+- pr_err("failed to allocate t_alg\n");
++ dev_err(ctrldev, "failed to allocate t_alg\n");
+ return ERR_PTR(-ENOMEM);
+ }
+
+@@ -4218,13 +2301,13 @@
+ alg->cra_blocksize = template->blocksize;
+ alg->cra_alignmask = 0;
+ alg->cra_ctxsize = sizeof(struct caam_ctx);
+- alg->cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_KERN_DRIVER_ONLY |
+- template->type;
++ alg->cra_flags = CRYPTO_ALG_ASYNC | template->type;
++
++#ifdef CRYPTO_ALG_KERN_DRIVER_ONLY
++ alg->cra_flags |= CRYPTO_ALG_KERN_DRIVER_ONLY;
++#endif
++
+ switch (template->type) {
+- case CRYPTO_ALG_TYPE_GIVCIPHER:
+- alg->cra_type = &crypto_givcipher_type;
+- alg->cra_ablkcipher = template->template_ablkcipher;
+- break;
+ case CRYPTO_ALG_TYPE_ABLKCIPHER:
+ alg->cra_type = &crypto_ablkcipher_type;
+ alg->cra_ablkcipher = template->template_ablkcipher;
+@@ -4238,6 +2321,7 @@
+ t_alg->class1_alg_type = template->class1_alg_type;
+ t_alg->class2_alg_type = template->class2_alg_type;
+ t_alg->alg_op = template->alg_op;
++ t_alg->ctrldev = ctrldev;
+
+ return t_alg;
+ }
+@@ -4246,9 +2330,11 @@
+ {
+ struct device_node *dev_node;
+ struct platform_device *pdev;
+- struct device *ctrldev;
+- void *priv;
+- int i = 0, err = 0;
++ struct device *ctrldev, **jrdev;
++ struct caam_drv_private *priv;
++ int i = 0, err = 0, md_limit = 0;
++ int des_inst, aes_inst, md_inst;
++ u64 cha_inst;
+
+ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
+ if (!dev_node) {
+@@ -4265,42 +2351,117 @@
+
+ ctrldev = &pdev->dev;
+ priv = dev_get_drvdata(ctrldev);
+- of_node_put(dev_node);
+
+- /*
+- * If priv is NULL, it's probably because the caam driver wasn't
+- * properly initialized (e.g. RNG4 init failed). Thus, bail out here.
+- */
+- if (!priv)
+- return -ENODEV;
++ INIT_LIST_HEAD(&priv->alg_list);
++
++ jrdev = kmalloc(sizeof(*jrdev) * priv->total_jobrs, GFP_ATOMIC);
++ if (!jrdev) {
++ of_node_put(dev_node);
++ return -ENOMEM;
++ }
+
++ for (i = 0; i < priv->total_jobrs; i++) {
++ err = caam_jr_register(ctrldev, &jrdev[i]);
++ if (err < 0)
++ break;
++ }
++ if (err < 0 && i == 0) {
++ dev_err(ctrldev, "algapi error in job ring registration: %d\n",
++ err);
++ of_node_put(dev_node);
++ kfree(jrdev);
++ return err;
++ }
+
+- INIT_LIST_HEAD(&alg_list);
++ priv->num_jrs_for_algapi = i;
++ priv->algapi_jr = jrdev;
++ atomic_set(&priv->tfm_count, -1);
++
++ /*
++ * register crypto algorithms the device supports
++ * first, detect presence of DES, AES, and MD blocks. If MD present,
++ * determine limit of supported digest size
++ */
++ cha_inst = rd_reg64(&priv->ctrl->perfmon.cha_num);
++ des_inst = (cha_inst & CHA_ID_DES_MASK) >> CHA_ID_DES_SHIFT;
++ aes_inst = (cha_inst & CHA_ID_AES_MASK) >> CHA_ID_AES_SHIFT;
++ md_inst = (cha_inst & CHA_ID_MD_MASK) >> CHA_ID_MD_SHIFT;
++ if (md_inst) {
++ md_limit = SHA512_DIGEST_SIZE;
++ if ((rd_reg64(&priv->ctrl->perfmon.cha_id) & CHA_ID_MD_MASK)
++ == CHA_ID_MD_LP256) /* LP256 limits digest size */
++ md_limit = SHA256_DIGEST_SIZE;
++ }
+
+- /* register crypto algorithms the device supports */
+ for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
+- /* TODO: check if h/w supports alg */
+ struct caam_crypto_alg *t_alg;
++ bool done = false;
++
++authencesn:
++ /*
++ * All registrable algs in this module require a blockcipher
++ * All aead algs require message digests, so check them for
++ * instantiation and size.
++ */
++ if (driver_algs[i].type == CRYPTO_ALG_TYPE_AEAD) {
++ /* If no MD instantiated, or MD too small, skip */
++ if ((!md_inst) ||
++ (driver_algs[i].template_aead.maxauthsize >
++ md_limit))
++ continue;
++ }
++ /* If DES alg, and CHA not instantiated, skip */
++ if ((driver_algs[i].class1_alg_type & OP_ALG_ALGSEL_3DES) ||
++ (driver_algs[i].class1_alg_type & OP_ALG_ALGSEL_DES))
++ if (!des_inst)
++ continue;
++ /* If AES alg, and CHA not instantiated, skip */
++ if (driver_algs[i].class1_alg_type & OP_ALG_ALGSEL_AES)
++ if (!aes_inst)
++ continue;
+
+- t_alg = caam_alg_alloc(&driver_algs[i]);
++ t_alg = caam_alg_alloc(ctrldev, &driver_algs[i]);
+ if (IS_ERR(t_alg)) {
+ err = PTR_ERR(t_alg);
+- pr_warn("%s alg allocation failed\n",
+- driver_algs[i].driver_name);
++ dev_warn(ctrldev, "%s alg allocation failed\n",
++ driver_algs[i].driver_name);
+ continue;
+ }
+
+ err = crypto_register_alg(&t_alg->crypto_alg);
+ if (err) {
+- pr_warn("%s alg registration failed\n",
++ dev_warn(ctrldev, "%s alg registration failed\n",
+ t_alg->crypto_alg.cra_driver_name);
+ kfree(t_alg);
+- } else
+- list_add_tail(&t_alg->entry, &alg_list);
++ } else {
++ list_add_tail(&t_alg->entry, &priv->alg_list);
++ dev_info(ctrldev, "%s\n",
++ t_alg->crypto_alg.cra_driver_name);
++
++ if (driver_algs[i].type == CRYPTO_ALG_TYPE_AEAD &&
++ !memcmp(driver_algs[i].name, "authenc", 7) &&
++ !done) {
++ char *name;
++
++ name = driver_algs[i].name;
++ memmove(name + 10, name + 7, strlen(name) - 7);
++ memcpy(name + 7, "esn", 3);
++
++ name = driver_algs[i].driver_name;
++ memmove(name + 10, name + 7, strlen(name) - 7);
++ memcpy(name + 7, "esn", 3);
++
++ done = true;
++ goto authencesn;
++ }
++ }
+ }
+- if (!list_empty(&alg_list))
+- pr_info("caam algorithms registered in /proc/crypto\n");
+
++ if (!list_empty(&priv->alg_list))
++ dev_info(ctrldev, "%s algorithms registered in /proc/crypto\n",
++ (char *)of_get_property(dev_node, "compatible", NULL));
++
++ of_node_put(dev_node);
+ return err;
+ }
+
+diff -Nur linux-4.1.3/drivers/crypto/caam/caamhash.c linux-xbian-imx6/drivers/crypto/caam/caamhash.c
+--- linux-4.1.3/drivers/crypto/caam/caamhash.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/drivers/crypto/caam/caamhash.c 2015-07-27 23:13:04.209961631 +0200
+@@ -1,7 +1,7 @@
+ /*
+ * caam - Freescale FSL CAAM support for ahash functions of crypto API
+ *
+- * Copyright 2011 Freescale Semiconductor, Inc.
++ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
+ *
+ * Based on caamalg.c crypto API driver.
+ *
+@@ -62,6 +62,7 @@
+ #include "error.h"
+ #include "sg_sw_sec4.h"
+ #include "key_gen.h"
++#include <linux/string.h>
+
+ #define CAAM_CRA_PRIORITY 3000
+
+@@ -72,6 +73,8 @@
+ #define CAAM_MAX_HASH_DIGEST_SIZE SHA512_DIGEST_SIZE
+
+ /* length of descriptors text */
++#define DESC_JOB_IO_LEN (CAAM_CMD_SZ * 5 + CAAM_PTR_SZ * 3)
++
+ #define DESC_AHASH_BASE (4 * CAAM_CMD_SZ)
+ #define DESC_AHASH_UPDATE_LEN (6 * CAAM_CMD_SZ)
+ #define DESC_AHASH_UPDATE_FIRST_LEN (DESC_AHASH_BASE + 4 * CAAM_CMD_SZ)
+@@ -89,14 +92,13 @@
+
+ #ifdef DEBUG
+ /* for print_hex_dumps with line references */
++#define xstr(s) str(s)
++#define str(s) #s
+ #define debug(format, arg...) printk(format, arg)
+ #else
+ #define debug(format, arg...)
+ #endif
+
+-
+-static struct list_head hash_list;
+-
+ /* ahash per-session context */
+ struct caam_hash_ctx {
+ struct device *jrdev;
+@@ -115,6 +117,7 @@
+ u8 key[CAAM_MAX_HASH_KEY_SIZE];
+ dma_addr_t key_dma;
+ int ctx_len;
++ unsigned int key_len;
+ unsigned int split_key_len;
+ unsigned int split_key_pad_len;
+ };
+@@ -137,20 +140,13 @@
+ /* Common job descriptor seq in/out ptr routines */
+
+ /* Map state->caam_ctx, and append seq_out_ptr command that points to it */
+-static inline int map_seq_out_ptr_ctx(u32 *desc, struct device *jrdev,
+- struct caam_hash_state *state,
+- int ctx_len)
++static inline void map_seq_out_ptr_ctx(u32 *desc, struct device *jrdev,
++ struct caam_hash_state *state,
++ int ctx_len)
+ {
+ state->ctx_dma = dma_map_single(jrdev, state->caam_ctx,
+ ctx_len, DMA_FROM_DEVICE);
+- if (dma_mapping_error(jrdev, state->ctx_dma)) {
+- dev_err(jrdev, "unable to map ctx\n");
+- return -ENOMEM;
+- }
+-
+ append_seq_out_ptr(desc, state->ctx_dma, ctx_len, 0);
+-
+- return 0;
+ }
+
+ /* Map req->result, and append seq_out_ptr command that points to it */
+@@ -173,6 +169,7 @@
+ dma_addr_t buf_dma;
+
+ buf_dma = dma_map_single(jrdev, buf, buflen, DMA_TO_DEVICE);
++ dma_sync_single_for_device(jrdev, buf_dma, buflen, DMA_TO_DEVICE);
+ dma_to_sec4_sg_one(sec4_sg, buf_dma, buflen, 0);
+
+ return buf_dma;
+@@ -208,19 +205,17 @@
+ }
+
+ /* Map state->caam_ctx, and add it to link table */
+-static inline int ctx_map_to_sec4_sg(u32 *desc, struct device *jrdev,
+- struct caam_hash_state *state, int ctx_len,
+- struct sec4_sg_entry *sec4_sg, u32 flag)
++static inline void ctx_map_to_sec4_sg(u32 *desc, struct device *jrdev,
++ struct caam_hash_state *state,
++ int ctx_len,
++ struct sec4_sg_entry *sec4_sg,
++ u32 flag)
+ {
+ state->ctx_dma = dma_map_single(jrdev, state->caam_ctx, ctx_len, flag);
+- if (dma_mapping_error(jrdev, state->ctx_dma)) {
+- dev_err(jrdev, "unable to map ctx\n");
+- return -ENOMEM;
+- }
+-
++ if ((flag == DMA_TO_DEVICE) || (flag == DMA_BIDIRECTIONAL))
++ dma_sync_single_for_device(jrdev, state->ctx_dma, ctx_len,
++ flag);
+ dma_to_sec4_sg_one(sec4_sg, state->ctx_dma, ctx_len, 0);
+-
+- return 0;
+ }
+
+ /* Common shared descriptor commands */
+@@ -231,6 +226,13 @@
+ KEY_DEST_MDHA_SPLIT | KEY_ENC);
+ }
+
++static inline void append_key_axcbc(u32 *desc, struct caam_hash_ctx *ctx)
++{
++ append_key_as_imm(desc, ctx->key, ctx->key_len,
++ ctx->key_len, CLASS_1 |
++ KEY_DEST_CLASS_REG);
++}
++
+ /* Append key if it has been set */
+ static inline void init_sh_desc_key_ahash(u32 *desc, struct caam_hash_ctx *ctx)
+ {
+@@ -252,6 +254,25 @@
+ append_cmd(desc, SET_OK_NO_PROP_ERRORS | CMD_LOAD);
+ }
+
++static inline void init_sh_desc_key_axcbc(u32 *desc, struct caam_hash_ctx *ctx)
++{
++ u32 *key_jump_cmd;
++
++ init_sh_desc(desc, HDR_SHARE_SERIAL);
++
++ if (ctx->key_len) {
++ key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
++ JUMP_COND_SHRD);
++
++ append_key_axcbc(desc, ctx);
++
++ set_jump_tgt_here(desc, key_jump_cmd);
++ }
++
++ /* Propagate errors from shared to job descriptor */
++ append_cmd(desc, SET_OK_NO_PROP_ERRORS | CMD_LOAD);
++
++}
+ /*
+ * For ahash read data from seqin following state->caam_ctx,
+ * and write resulting class2 context to seqout, which may be state->caam_ctx
+@@ -271,6 +292,20 @@
+ LDST_SRCDST_BYTE_CONTEXT);
+ }
+
++static inline void axcbc_append_load_str(u32 *desc, int digestsize)
++{
++ /* Calculate remaining bytes to read */
++ append_math_add(desc, VARSEQINLEN, SEQINLEN, REG0, CAAM_CMD_SZ);
++
++ /* Read remaining bytes */
++ append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLD_TYPE_LAST1 |
++ FIFOLD_TYPE_MSG | KEY_VLF);
++
++ /* Store class1 context bytes */
++ append_seq_store(desc, digestsize, LDST_CLASS_1_CCB |
++ LDST_SRCDST_BYTE_CONTEXT);
++}
++
+ /*
+ * For ahash update, final and finup, import context, read and write to seqout
+ */
+@@ -293,6 +328,27 @@
+ ahash_append_load_str(desc, digestsize);
+ }
+
++/*
++ * For ahash update, final and finup, import context, read and write to seqout
++ */
++static inline void axcbc_ctx_data_to_out(u32 *desc, u32 op, u32 state,
++ int digestsize,
++ struct caam_hash_ctx *ctx)
++{
++ init_sh_desc_key_axcbc(desc, ctx);
++
++ /* Import context from software */
++ append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_BYTE_CONTEXT |
++ LDST_CLASS_1_CCB | ctx->ctx_len);
++
++ /* Class 1 operation */
++ append_operation(desc, op | state | OP_ALG_ENCRYPT);
++
++ /*
++ * Load from buf and/or src and write to req->result or state->context
++ */
++ axcbc_append_load_str(desc, digestsize);
++}
+ /* For ahash firsts and digest, read and write to seqout */
+ static inline void ahash_data_to_out(u32 *desc, u32 op, u32 state,
+ int digestsize, struct caam_hash_ctx *ctx)
+@@ -308,6 +364,21 @@
+ ahash_append_load_str(desc, digestsize);
+ }
+
++/* For ahash firsts and digest, read and write to seqout */
++static inline void axcbc_data_to_out(u32 *desc, u32 op, u32 state,
++ int digestsize, struct caam_hash_ctx *ctx)
++{
++ init_sh_desc_key_axcbc(desc, ctx);
++
++ /* Class 1 operation */
++ append_operation(desc, op | state | OP_ALG_ENCRYPT);
++
++ /*
++ * Load from buf and/or src and write to req->result or state->context
++ */
++ axcbc_append_load_str(desc, digestsize);
++}
++
+ static int ahash_set_sh_desc(struct crypto_ahash *ahash)
+ {
+ struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
+@@ -342,8 +413,7 @@
+ return -ENOMEM;
+ }
+ #ifdef DEBUG
+- print_hex_dump(KERN_ERR,
+- "ahash update shdesc@"__stringify(__LINE__)": ",
++ print_hex_dump(KERN_ERR, "ahash update shdesc@"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
+ #endif
+
+@@ -361,10 +431,11 @@
+ return -ENOMEM;
+ }
+ #ifdef DEBUG
+- print_hex_dump(KERN_ERR,
+- "ahash update first shdesc@"__stringify(__LINE__)": ",
++ print_hex_dump(KERN_ERR, "ahash update first shdesc@"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
+ #endif
++ dma_sync_single_for_device(jrdev, ctx->sh_desc_update_first_dma,
++ desc_bytes(desc), DMA_TO_DEVICE);
+
+ /* ahash_final shared descriptor */
+ desc = ctx->sh_desc_fin;
+@@ -379,10 +450,12 @@
+ return -ENOMEM;
+ }
+ #ifdef DEBUG
+- print_hex_dump(KERN_ERR, "ahash final shdesc@"__stringify(__LINE__)": ",
++ print_hex_dump(KERN_ERR, "ahash final shdesc@"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, desc,
+ desc_bytes(desc), 1);
+ #endif
++ dma_sync_single_for_device(jrdev, ctx->sh_desc_fin_dma,
++ desc_bytes(desc), DMA_TO_DEVICE);
+
+ /* ahash_finup shared descriptor */
+ desc = ctx->sh_desc_finup;
+@@ -397,10 +470,12 @@
+ return -ENOMEM;
+ }
+ #ifdef DEBUG
+- print_hex_dump(KERN_ERR, "ahash finup shdesc@"__stringify(__LINE__)": ",
++ print_hex_dump(KERN_ERR, "ahash finup shdesc@"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, desc,
+ desc_bytes(desc), 1);
+ #endif
++ dma_sync_single_for_device(jrdev, ctx->sh_desc_finup_dma,
++ desc_bytes(desc), DMA_TO_DEVICE);
+
+ /* ahash_digest shared descriptor */
+ desc = ctx->sh_desc_digest;
+@@ -416,15 +491,134 @@
+ return -ENOMEM;
+ }
+ #ifdef DEBUG
+- print_hex_dump(KERN_ERR,
+- "ahash digest shdesc@"__stringify(__LINE__)": ",
++ print_hex_dump(KERN_ERR, "ahash digest shdesc@"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, desc,
+ desc_bytes(desc), 1);
+ #endif
++ dma_sync_single_for_device(jrdev, ctx->sh_desc_digest_dma,
++ desc_bytes(desc), DMA_TO_DEVICE);
+
+ return 0;
+ }
+
++static int axcbc_set_sh_desc(struct crypto_ahash *ahash)
++{
++ struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
++ int digestsize = crypto_ahash_digestsize(ahash);
++ struct device *jrdev = ctx->jrdev;
++ u32 have_key = 0;
++ u32 *desc;
++
++ /* ahash_update shared descriptor */
++ desc = ctx->sh_desc_update;
++
++ init_sh_desc(desc, HDR_SHARE_SERIAL);
++
++ /* Import context from software */
++ append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_BYTE_CONTEXT |
++ LDST_CLASS_1_CCB | ctx->ctx_len);
++
++ /* Class 1 operation */
++ append_operation(desc, ctx->alg_type | OP_ALG_AS_UPDATE |
++ OP_ALG_ENCRYPT);
++
++ /* Load data and write to result or context */
++ axcbc_append_load_str(desc, ctx->ctx_len);
++
++ ctx->sh_desc_update_dma = dma_map_single(jrdev, desc, desc_bytes(desc),
++ DMA_TO_DEVICE);
++ if (dma_mapping_error(jrdev, ctx->sh_desc_update_dma)) {
++ dev_err(jrdev, "unable to map shared descriptor\n");
++ return -ENOMEM;
++ }
++#ifdef DEBUG
++ print_hex_dump(KERN_ERR, "ahash update shdesc@"xstr(__LINE__)": ",
++ DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
++#endif
++
++ /* ahash_update_first shared descriptor */
++ desc = ctx->sh_desc_update_first;
++
++ axcbc_data_to_out(desc, have_key | ctx->alg_type, OP_ALG_AS_INIT,
++ ctx->ctx_len, ctx);
++
++ ctx->sh_desc_update_first_dma = dma_map_single(jrdev, desc,
++ desc_bytes(desc),
++ DMA_TO_DEVICE);
++ if (dma_mapping_error(jrdev, ctx->sh_desc_update_first_dma)) {
++ dev_err(jrdev, "unable to map shared descriptor\n");
++ return -ENOMEM;
++ }
++#ifdef DEBUG
++ print_hex_dump(KERN_ERR, "ahash update first shdesc@"xstr(__LINE__)": ",
++ DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
++#endif
++ dma_sync_single_for_device(jrdev, ctx->sh_desc_update_first_dma,
++ desc_bytes(desc), DMA_TO_DEVICE);
++
++ /* ahash_final shared descriptor */
++ desc = ctx->sh_desc_fin;
++
++ axcbc_ctx_data_to_out(desc, have_key | ctx->alg_type,
++ OP_ALG_AS_FINALIZE, digestsize, ctx);
++
++ ctx->sh_desc_fin_dma = dma_map_single(jrdev, desc, desc_bytes(desc),
++ DMA_TO_DEVICE);
++ if (dma_mapping_error(jrdev, ctx->sh_desc_fin_dma)) {
++ dev_err(jrdev, "unable to map shared descriptor\n");
++ return -ENOMEM;
++ }
++#ifdef DEBUG
++ print_hex_dump(KERN_ERR, "ahash final shdesc@"xstr(__LINE__)": ",
++ DUMP_PREFIX_ADDRESS, 16, 4, desc,
++ desc_bytes(desc), 1);
++#endif
++ dma_sync_single_for_device(jrdev, ctx->sh_desc_fin_dma,
++ desc_bytes(desc), DMA_TO_DEVICE);
++
++ /* ahash_finup shared descriptor */
++ desc = ctx->sh_desc_finup;
++
++ axcbc_ctx_data_to_out(desc, have_key | ctx->alg_type,
++ OP_ALG_AS_FINALIZE, digestsize, ctx);
++
++ ctx->sh_desc_finup_dma = dma_map_single(jrdev, desc, desc_bytes(desc),
++ DMA_TO_DEVICE);
++ if (dma_mapping_error(jrdev, ctx->sh_desc_finup_dma)) {
++ dev_err(jrdev, "unable to map shared descriptor\n");
++ return -ENOMEM;
++ }
++#ifdef DEBUG
++ print_hex_dump(KERN_ERR, "ahash finup shdesc@"xstr(__LINE__)": ",
++ DUMP_PREFIX_ADDRESS, 16, 4, desc,
++ desc_bytes(desc), 1);
++#endif
++ dma_sync_single_for_device(jrdev, ctx->sh_desc_finup_dma,
++ desc_bytes(desc), DMA_TO_DEVICE);
++
++ /* ahash_digest shared descriptor */
++ desc = ctx->sh_desc_digest;
++
++ axcbc_data_to_out(desc, have_key | ctx->alg_type, OP_ALG_AS_INITFINAL,
++ digestsize, ctx);
++
++ ctx->sh_desc_digest_dma = dma_map_single(jrdev, desc,
++ desc_bytes(desc),
++ DMA_TO_DEVICE);
++ if (dma_mapping_error(jrdev, ctx->sh_desc_digest_dma)) {
++ dev_err(jrdev, "unable to map shared descriptor\n");
++ return -ENOMEM;
++ }
++#ifdef DEBUG
++ print_hex_dump(KERN_ERR, "ahash digest shdesc@"xstr(__LINE__)": ",
++ DUMP_PREFIX_ADDRESS, 16, 4, desc,
++ desc_bytes(desc), 1);
++#endif
++ dma_sync_single_for_device(jrdev, ctx->sh_desc_digest_dma,
++ desc_bytes(desc), DMA_TO_DEVICE);
++
++ return 0;
++}
+ static int gen_split_hash_key(struct caam_hash_ctx *ctx, const u8 *key_in,
+ u32 keylen)
+ {
+@@ -458,6 +652,8 @@
+ kfree(desc);
+ return -ENOMEM;
+ }
++ dma_sync_single_for_device(jrdev, src_dma, *keylen, DMA_TO_DEVICE);
++
+ dst_dma = dma_map_single(jrdev, (void *)key_out, digestsize,
+ DMA_FROM_DEVICE);
+ if (dma_mapping_error(jrdev, dst_dma)) {
+@@ -478,9 +674,9 @@
+ LDST_SRCDST_BYTE_CONTEXT);
+
+ #ifdef DEBUG
+- print_hex_dump(KERN_ERR, "key_in@"__stringify(__LINE__)": ",
++ print_hex_dump(KERN_ERR, "key_in@"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, key_in, *keylen, 1);
+- print_hex_dump(KERN_ERR, "jobdesc@"__stringify(__LINE__)": ",
++ print_hex_dump(KERN_ERR, "jobdesc@"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
+ #endif
+
+@@ -493,17 +689,17 @@
+ wait_for_completion_interruptible(&result.completion);
+ ret = result.err;
+ #ifdef DEBUG
+- print_hex_dump(KERN_ERR,
+- "digested key@"__stringify(__LINE__)": ",
++ print_hex_dump(KERN_ERR, "digested key@"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, key_in,
+ digestsize, 1);
+ #endif
+ }
++ *keylen = digestsize;
++
+ dma_unmap_single(jrdev, src_dma, *keylen, DMA_TO_DEVICE);
++ dma_sync_single_for_cpu(jrdev, dst_dma, digestsize, DMA_FROM_DEVICE);
+ dma_unmap_single(jrdev, dst_dma, digestsize, DMA_FROM_DEVICE);
+
+- *keylen = digestsize;
+-
+ kfree(desc);
+
+ return ret;
+@@ -545,7 +741,7 @@
+ #ifdef DEBUG
+ printk(KERN_ERR "split_key_len %d split_key_pad_len %d\n",
+ ctx->split_key_len, ctx->split_key_pad_len);
+- print_hex_dump(KERN_ERR, "key in @"__stringify(__LINE__)": ",
++ print_hex_dump(KERN_ERR, "key in @"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
+ #endif
+
+@@ -557,11 +753,14 @@
+ DMA_TO_DEVICE);
+ if (dma_mapping_error(jrdev, ctx->key_dma)) {
+ dev_err(jrdev, "unable to map key i/o memory\n");
+- ret = -ENOMEM;
+- goto map_err;
++ return -ENOMEM;
+ }
++
++ dma_sync_single_for_device(jrdev, ctx->key_dma, ctx->split_key_pad_len,
++ DMA_TO_DEVICE);
++
+ #ifdef DEBUG
+- print_hex_dump(KERN_ERR, "ctx.key@"__stringify(__LINE__)": ",
++ print_hex_dump(KERN_ERR, "ctx.key@"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, ctx->key,
+ ctx->split_key_pad_len, 1);
+ #endif
+@@ -572,7 +771,6 @@
+ DMA_TO_DEVICE);
+ }
+
+-map_err:
+ kfree(hashed_key);
+ return ret;
+ badkey:
+@@ -581,6 +779,25 @@
+ return -EINVAL;
+ }
+
++static int axcbc_setkey(struct crypto_ahash *ahash,
++ const u8 *key, unsigned int keylen)
++{
++ struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
++ int ret = 0;
++
++ ctx->key_len = keylen;
++ memcpy(ctx->key, key, keylen);
++
++#ifdef DEBUG
++ print_hex_dump(KERN_ERR, "ctx.key@"xstr(__LINE__)": ",
++ DUMP_PREFIX_ADDRESS, 16, 4, ctx->key,
++ ctx->key_len, 1);
++#endif
++
++ ret = axcbc_set_sh_desc(ahash);
++
++ return ret;
++}
+ /*
+ * ahash_edesc - s/w-extended ahash descriptor
+ * @dst_dma: physical mapped address of req->result
+@@ -608,8 +825,11 @@
+ if (edesc->src_nents)
+ dma_unmap_sg_chained(dev, req->src, edesc->src_nents,
+ DMA_TO_DEVICE, edesc->chained);
+- if (edesc->dst_dma)
++ if (edesc->dst_dma) {
++ dma_sync_single_for_cpu(dev, edesc->dst_dma, dst_len,
++ DMA_FROM_DEVICE);
+ dma_unmap_single(dev, edesc->dst_dma, dst_len, DMA_FROM_DEVICE);
++ }
+
+ if (edesc->sec4_sg_bytes)
+ dma_unmap_single(dev, edesc->sec4_sg_dma,
+@@ -624,8 +844,12 @@
+ struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
+ struct caam_hash_state *state = ahash_request_ctx(req);
+
+- if (state->ctx_dma)
++ if (state->ctx_dma) {
++ if ((flag == DMA_FROM_DEVICE) || (flag == DMA_BIDIRECTIONAL))
++ dma_sync_single_for_cpu(dev, state->ctx_dma,
++ ctx->ctx_len, flag);
+ dma_unmap_single(dev, state->ctx_dma, ctx->ctx_len, flag);
++ }
+ ahash_unmap(dev, edesc, req, dst_len);
+ }
+
+@@ -645,18 +869,21 @@
+
+ edesc = (struct ahash_edesc *)((char *)desc -
+ offsetof(struct ahash_edesc, hw_desc));
+- if (err)
+- caam_jr_strstatus(jrdev, err);
++ if (err) {
++ char tmp[CAAM_ERROR_STR_MAX];
++
++ dev_err(jrdev, "%08x: %s\n", err, caam_jr_strstatus(tmp, err));
++ }
+
+ ahash_unmap(jrdev, edesc, req, digestsize);
+ kfree(edesc);
+
+ #ifdef DEBUG
+- print_hex_dump(KERN_ERR, "ctx@"__stringify(__LINE__)": ",
++ print_hex_dump(KERN_ERR, "ctx@"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, state->caam_ctx,
+ ctx->ctx_len, 1);
+ if (req->result)
+- print_hex_dump(KERN_ERR, "result@"__stringify(__LINE__)": ",
++ print_hex_dump(KERN_ERR, "result@"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, req->result,
+ digestsize, 1);
+ #endif
+@@ -680,18 +907,21 @@
+
+ edesc = (struct ahash_edesc *)((char *)desc -
+ offsetof(struct ahash_edesc, hw_desc));
+- if (err)
+- caam_jr_strstatus(jrdev, err);
++ if (err) {
++ char tmp[CAAM_ERROR_STR_MAX];
++
++ dev_err(jrdev, "%08x: %s\n", err, caam_jr_strstatus(tmp, err));
++ }
+
+ ahash_unmap_ctx(jrdev, edesc, req, ctx->ctx_len, DMA_BIDIRECTIONAL);
+ kfree(edesc);
+
+ #ifdef DEBUG
+- print_hex_dump(KERN_ERR, "ctx@"__stringify(__LINE__)": ",
++ print_hex_dump(KERN_ERR, "ctx@"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, state->caam_ctx,
+ ctx->ctx_len, 1);
+ if (req->result)
+- print_hex_dump(KERN_ERR, "result@"__stringify(__LINE__)": ",
++ print_hex_dump(KERN_ERR, "result@"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, req->result,
+ digestsize, 1);
+ #endif
+@@ -715,18 +945,21 @@
+
+ edesc = (struct ahash_edesc *)((char *)desc -
+ offsetof(struct ahash_edesc, hw_desc));
+- if (err)
+- caam_jr_strstatus(jrdev, err);
++ if (err) {
++ char tmp[CAAM_ERROR_STR_MAX];
+
+- ahash_unmap_ctx(jrdev, edesc, req, digestsize, DMA_TO_DEVICE);
++ dev_err(jrdev, "%08x: %s\n", err, caam_jr_strstatus(tmp, err));
++ }
++
++ ahash_unmap_ctx(jrdev, edesc, req, digestsize, DMA_FROM_DEVICE);
+ kfree(edesc);
+
+ #ifdef DEBUG
+- print_hex_dump(KERN_ERR, "ctx@"__stringify(__LINE__)": ",
++ print_hex_dump(KERN_ERR, "ctx@"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, state->caam_ctx,
+ ctx->ctx_len, 1);
+ if (req->result)
+- print_hex_dump(KERN_ERR, "result@"__stringify(__LINE__)": ",
++ print_hex_dump(KERN_ERR, "result@"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, req->result,
+ digestsize, 1);
+ #endif
+@@ -750,18 +983,21 @@
+
+ edesc = (struct ahash_edesc *)((char *)desc -
+ offsetof(struct ahash_edesc, hw_desc));
+- if (err)
+- caam_jr_strstatus(jrdev, err);
++ if (err) {
++ char tmp[CAAM_ERROR_STR_MAX];
++
++ dev_err(jrdev, "%08x: %s\n", err, caam_jr_strstatus(tmp, err));
++ }
+
+- ahash_unmap_ctx(jrdev, edesc, req, ctx->ctx_len, DMA_FROM_DEVICE);
++ ahash_unmap_ctx(jrdev, edesc, req, ctx->ctx_len, DMA_TO_DEVICE);
+ kfree(edesc);
+
+ #ifdef DEBUG
+- print_hex_dump(KERN_ERR, "ctx@"__stringify(__LINE__)": ",
++ print_hex_dump(KERN_ERR, "ctx@"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, state->caam_ctx,
+ ctx->ctx_len, 1);
+ if (req->result)
+- print_hex_dump(KERN_ERR, "result@"__stringify(__LINE__)": ",
++ print_hex_dump(KERN_ERR, "result@"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, req->result,
+ digestsize, 1);
+ #endif
+@@ -807,7 +1043,7 @@
+ * allocate space for base edesc and hw desc commands,
+ * link tables
+ */
+- edesc = kmalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN +
++ edesc = kzalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN +
+ sec4_sg_bytes, GFP_DMA | flags);
+ if (!edesc) {
+ dev_err(jrdev,
+@@ -820,11 +1056,12 @@
+ edesc->sec4_sg_bytes = sec4_sg_bytes;
+ edesc->sec4_sg = (void *)edesc + sizeof(struct ahash_edesc) +
+ DESC_JOB_IO_LEN;
++ edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg,
++ sec4_sg_bytes,
++ DMA_TO_DEVICE);
+
+- ret = ctx_map_to_sec4_sg(desc, jrdev, state, ctx->ctx_len,
+- edesc->sec4_sg, DMA_BIDIRECTIONAL);
+- if (ret)
+- return ret;
++ ctx_map_to_sec4_sg(desc, jrdev, state, ctx->ctx_len,
++ edesc->sec4_sg, DMA_BIDIRECTIONAL);
+
+ state->buf_dma = try_buf_map_to_sec4_sg(jrdev,
+ edesc->sec4_sg + 1,
+@@ -851,21 +1088,16 @@
+ init_job_desc_shared(desc, ptr, sh_len, HDR_SHARE_DEFER |
+ HDR_REVERSE);
+
+- edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg,
+- sec4_sg_bytes,
+- DMA_TO_DEVICE);
+- if (dma_mapping_error(jrdev, edesc->sec4_sg_dma)) {
+- dev_err(jrdev, "unable to map S/G table\n");
+- return -ENOMEM;
+- }
+-
+ append_seq_in_ptr(desc, edesc->sec4_sg_dma, ctx->ctx_len +
+ to_hash, LDST_SGF);
+
+ append_seq_out_ptr(desc, state->ctx_dma, ctx->ctx_len, 0);
+
++ dma_sync_single_for_device(jrdev, edesc->sec4_sg_dma,
++ sec4_sg_bytes, DMA_TO_DEVICE);
++
+ #ifdef DEBUG
+- print_hex_dump(KERN_ERR, "jobdesc@"__stringify(__LINE__)": ",
++ print_hex_dump(KERN_ERR, "jobdesc@"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, desc,
+ desc_bytes(desc), 1);
+ #endif
+@@ -885,9 +1117,9 @@
+ *next_buflen = last_buflen;
+ }
+ #ifdef DEBUG
+- print_hex_dump(KERN_ERR, "buf@"__stringify(__LINE__)": ",
++ print_hex_dump(KERN_ERR, "buf@"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, buf, *buflen, 1);
+- print_hex_dump(KERN_ERR, "next buf@"__stringify(__LINE__)": ",
++ print_hex_dump(KERN_ERR, "next buf@"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, next_buf,
+ *next_buflen, 1);
+ #endif
+@@ -918,7 +1150,7 @@
+ sec4_sg_bytes = (1 + (buflen ? 1 : 0)) * sizeof(struct sec4_sg_entry);
+
+ /* allocate space for base edesc and hw desc commands, link tables */
+- edesc = kmalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN +
++ edesc = kzalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN +
+ sec4_sg_bytes, GFP_DMA | flags);
+ if (!edesc) {
+ dev_err(jrdev, "could not allocate extended descriptor\n");
+@@ -932,37 +1164,29 @@
+ edesc->sec4_sg_bytes = sec4_sg_bytes;
+ edesc->sec4_sg = (void *)edesc + sizeof(struct ahash_edesc) +
+ DESC_JOB_IO_LEN;
++ edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg,
++ sec4_sg_bytes, DMA_TO_DEVICE);
+ edesc->src_nents = 0;
+
+- ret = ctx_map_to_sec4_sg(desc, jrdev, state, ctx->ctx_len,
+- edesc->sec4_sg, DMA_TO_DEVICE);
+- if (ret)
+- return ret;
++ ctx_map_to_sec4_sg(desc, jrdev, state, ctx->ctx_len, edesc->sec4_sg,
++ DMA_TO_DEVICE);
+
+ state->buf_dma = try_buf_map_to_sec4_sg(jrdev, edesc->sec4_sg + 1,
+ buf, state->buf_dma, buflen,
+ last_buflen);
+ (edesc->sec4_sg + sec4_sg_bytes - 1)->len |= SEC4_SG_LEN_FIN;
+
+- edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg,
+- sec4_sg_bytes, DMA_TO_DEVICE);
+- if (dma_mapping_error(jrdev, edesc->sec4_sg_dma)) {
+- dev_err(jrdev, "unable to map S/G table\n");
+- return -ENOMEM;
+- }
+-
+ append_seq_in_ptr(desc, edesc->sec4_sg_dma, ctx->ctx_len + buflen,
+ LDST_SGF);
+
+ edesc->dst_dma = map_seq_out_ptr_result(desc, jrdev, req->result,
+ digestsize);
+- if (dma_mapping_error(jrdev, edesc->dst_dma)) {
+- dev_err(jrdev, "unable to map dst\n");
+- return -ENOMEM;
+- }
++
++ dma_sync_single_for_device(jrdev, edesc->sec4_sg_dma, sec4_sg_bytes,
++ DMA_TO_DEVICE);
+
+ #ifdef DEBUG
+- print_hex_dump(KERN_ERR, "jobdesc@"__stringify(__LINE__)": ",
++ print_hex_dump(KERN_ERR, "jobdesc@"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
+ #endif
+
+@@ -1005,7 +1229,7 @@
+ sizeof(struct sec4_sg_entry);
+
+ /* allocate space for base edesc and hw desc commands, link tables */
+- edesc = kmalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN +
++ edesc = kzalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN +
+ sec4_sg_bytes, GFP_DMA | flags);
+ if (!edesc) {
+ dev_err(jrdev, "could not allocate extended descriptor\n");
+@@ -1021,11 +1245,11 @@
+ edesc->sec4_sg_bytes = sec4_sg_bytes;
+ edesc->sec4_sg = (void *)edesc + sizeof(struct ahash_edesc) +
+ DESC_JOB_IO_LEN;
++ edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg,
++ sec4_sg_bytes, DMA_TO_DEVICE);
+
+- ret = ctx_map_to_sec4_sg(desc, jrdev, state, ctx->ctx_len,
+- edesc->sec4_sg, DMA_TO_DEVICE);
+- if (ret)
+- return ret;
++ ctx_map_to_sec4_sg(desc, jrdev, state, ctx->ctx_len, edesc->sec4_sg,
++ DMA_TO_DEVICE);
+
+ state->buf_dma = try_buf_map_to_sec4_sg(jrdev, edesc->sec4_sg + 1,
+ buf, state->buf_dma, buflen,
+@@ -1034,25 +1258,17 @@
+ src_map_to_sec4_sg(jrdev, req->src, src_nents, edesc->sec4_sg +
+ sec4_sg_src_index, chained);
+
+- edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg,
+- sec4_sg_bytes, DMA_TO_DEVICE);
+- if (dma_mapping_error(jrdev, edesc->sec4_sg_dma)) {
+- dev_err(jrdev, "unable to map S/G table\n");
+- return -ENOMEM;
+- }
+-
+ append_seq_in_ptr(desc, edesc->sec4_sg_dma, ctx->ctx_len +
+ buflen + req->nbytes, LDST_SGF);
+
+ edesc->dst_dma = map_seq_out_ptr_result(desc, jrdev, req->result,
+ digestsize);
+- if (dma_mapping_error(jrdev, edesc->dst_dma)) {
+- dev_err(jrdev, "unable to map dst\n");
+- return -ENOMEM;
+- }
++
++ dma_sync_single_for_device(jrdev, edesc->sec4_sg_dma, sec4_sg_bytes,
++ DMA_TO_DEVICE);
+
+ #ifdef DEBUG
+- print_hex_dump(KERN_ERR, "jobdesc@"__stringify(__LINE__)": ",
++ print_hex_dump(KERN_ERR, "jobdesc@"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
+ #endif
+
+@@ -1091,7 +1307,7 @@
+ sec4_sg_bytes = src_nents * sizeof(struct sec4_sg_entry);
+
+ /* allocate space for base edesc and hw desc commands, link tables */
+- edesc = kmalloc(sizeof(struct ahash_edesc) + sec4_sg_bytes +
++ edesc = kzalloc(sizeof(struct ahash_edesc) + sec4_sg_bytes +
+ DESC_JOB_IO_LEN, GFP_DMA | flags);
+ if (!edesc) {
+ dev_err(jrdev, "could not allocate extended descriptor\n");
+@@ -1099,6 +1315,8 @@
+ }
+ edesc->sec4_sg = (void *)edesc + sizeof(struct ahash_edesc) +
+ DESC_JOB_IO_LEN;
++ edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg,
++ sec4_sg_bytes, DMA_TO_DEVICE);
+ edesc->sec4_sg_bytes = sec4_sg_bytes;
+ edesc->src_nents = src_nents;
+ edesc->chained = chained;
+@@ -1109,12 +1327,6 @@
+
+ if (src_nents) {
+ sg_to_sec4_sg_last(req->src, src_nents, edesc->sec4_sg, 0);
+- edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg,
+- sec4_sg_bytes, DMA_TO_DEVICE);
+- if (dma_mapping_error(jrdev, edesc->sec4_sg_dma)) {
+- dev_err(jrdev, "unable to map S/G table\n");
+- return -ENOMEM;
+- }
+ src_dma = edesc->sec4_sg_dma;
+ options = LDST_SGF;
+ } else {
+@@ -1123,15 +1335,14 @@
+ }
+ append_seq_in_ptr(desc, src_dma, req->nbytes, options);
+
++ dma_sync_single_for_device(jrdev, edesc->sec4_sg_dma,
++ edesc->sec4_sg_bytes, DMA_TO_DEVICE);
++
+ edesc->dst_dma = map_seq_out_ptr_result(desc, jrdev, req->result,
+ digestsize);
+- if (dma_mapping_error(jrdev, edesc->dst_dma)) {
+- dev_err(jrdev, "unable to map dst\n");
+- return -ENOMEM;
+- }
+
+ #ifdef DEBUG
+- print_hex_dump(KERN_ERR, "jobdesc@"__stringify(__LINE__)": ",
++ print_hex_dump(KERN_ERR, "jobdesc@"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
+ #endif
+
+@@ -1165,7 +1376,7 @@
+ int sh_len;
+
+ /* allocate space for base edesc and hw desc commands, link tables */
+- edesc = kmalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN,
++ edesc = kzalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN,
+ GFP_DMA | flags);
+ if (!edesc) {
+ dev_err(jrdev, "could not allocate extended descriptor\n");
+@@ -1178,23 +1389,17 @@
+ init_job_desc_shared(desc, ptr, sh_len, HDR_SHARE_DEFER | HDR_REVERSE);
+
+ state->buf_dma = dma_map_single(jrdev, buf, buflen, DMA_TO_DEVICE);
+- if (dma_mapping_error(jrdev, state->buf_dma)) {
+- dev_err(jrdev, "unable to map src\n");
+- return -ENOMEM;
+- }
+
+ append_seq_in_ptr(desc, state->buf_dma, buflen, 0);
+
+ edesc->dst_dma = map_seq_out_ptr_result(desc, jrdev, req->result,
+ digestsize);
+- if (dma_mapping_error(jrdev, edesc->dst_dma)) {
+- dev_err(jrdev, "unable to map dst\n");
+- return -ENOMEM;
+- }
+ edesc->src_nents = 0;
+
++ dma_sync_single_for_device(jrdev, state->buf_dma, buflen,
++ DMA_TO_DEVICE);
+ #ifdef DEBUG
+- print_hex_dump(KERN_ERR, "jobdesc@"__stringify(__LINE__)": ",
++ print_hex_dump(KERN_ERR, "jobdesc@"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
+ #endif
+
+@@ -1245,7 +1450,7 @@
+ * allocate space for base edesc and hw desc commands,
+ * link tables
+ */
+- edesc = kmalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN +
++ edesc = kzalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN +
+ sec4_sg_bytes, GFP_DMA | flags);
+ if (!edesc) {
+ dev_err(jrdev,
+@@ -1258,7 +1463,9 @@
+ edesc->sec4_sg_bytes = sec4_sg_bytes;
+ edesc->sec4_sg = (void *)edesc + sizeof(struct ahash_edesc) +
+ DESC_JOB_IO_LEN;
+- edesc->dst_dma = 0;
++ edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg,
++ sec4_sg_bytes,
++ DMA_TO_DEVICE);
+
+ state->buf_dma = buf_map_to_sec4_sg(jrdev, edesc->sec4_sg,
+ buf, *buflen);
+@@ -1276,22 +1483,14 @@
+ init_job_desc_shared(desc, ptr, sh_len, HDR_SHARE_DEFER |
+ HDR_REVERSE);
+
+- edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg,
+- sec4_sg_bytes,
+- DMA_TO_DEVICE);
+- if (dma_mapping_error(jrdev, edesc->sec4_sg_dma)) {
+- dev_err(jrdev, "unable to map S/G table\n");
+- return -ENOMEM;
+- }
+-
+ append_seq_in_ptr(desc, edesc->sec4_sg_dma, to_hash, LDST_SGF);
+
+- ret = map_seq_out_ptr_ctx(desc, jrdev, state, ctx->ctx_len);
+- if (ret)
+- return ret;
++ map_seq_out_ptr_ctx(desc, jrdev, state, ctx->ctx_len);
+
++ dma_sync_single_for_device(jrdev, edesc->sec4_sg_dma,
++ sec4_sg_bytes, DMA_TO_DEVICE);
+ #ifdef DEBUG
+- print_hex_dump(KERN_ERR, "jobdesc@"__stringify(__LINE__)": ",
++ print_hex_dump(KERN_ERR, "jobdesc@"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, desc,
+ desc_bytes(desc), 1);
+ #endif
+@@ -1314,9 +1513,9 @@
+ *next_buflen = 0;
+ }
+ #ifdef DEBUG
+- print_hex_dump(KERN_ERR, "buf@"__stringify(__LINE__)": ",
++ print_hex_dump(KERN_ERR, "buf@"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, buf, *buflen, 1);
+- print_hex_dump(KERN_ERR, "next buf@"__stringify(__LINE__)": ",
++ print_hex_dump(KERN_ERR, "next buf@"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, next_buf,
+ *next_buflen, 1);
+ #endif
+@@ -1352,7 +1551,7 @@
+ sizeof(struct sec4_sg_entry);
+
+ /* allocate space for base edesc and hw desc commands, link tables */
+- edesc = kmalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN +
++ edesc = kzalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN +
+ sec4_sg_bytes, GFP_DMA | flags);
+ if (!edesc) {
+ dev_err(jrdev, "could not allocate extended descriptor\n");
+@@ -1368,6 +1567,8 @@
+ edesc->sec4_sg_bytes = sec4_sg_bytes;
+ edesc->sec4_sg = (void *)edesc + sizeof(struct ahash_edesc) +
+ DESC_JOB_IO_LEN;
++ edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg,
++ sec4_sg_bytes, DMA_TO_DEVICE);
+
+ state->buf_dma = try_buf_map_to_sec4_sg(jrdev, edesc->sec4_sg, buf,
+ state->buf_dma, buflen,
+@@ -1376,25 +1577,17 @@
+ src_map_to_sec4_sg(jrdev, req->src, src_nents, edesc->sec4_sg + 1,
+ chained);
+
+- edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg,
+- sec4_sg_bytes, DMA_TO_DEVICE);
+- if (dma_mapping_error(jrdev, edesc->sec4_sg_dma)) {
+- dev_err(jrdev, "unable to map S/G table\n");
+- return -ENOMEM;
+- }
+-
+ append_seq_in_ptr(desc, edesc->sec4_sg_dma, buflen +
+ req->nbytes, LDST_SGF);
+
+ edesc->dst_dma = map_seq_out_ptr_result(desc, jrdev, req->result,
+ digestsize);
+- if (dma_mapping_error(jrdev, edesc->dst_dma)) {
+- dev_err(jrdev, "unable to map dst\n");
+- return -ENOMEM;
+- }
++
++ dma_sync_single_for_device(jrdev, edesc->sec4_sg_dma, sec4_sg_bytes,
++ DMA_TO_DEVICE);
+
+ #ifdef DEBUG
+- print_hex_dump(KERN_ERR, "jobdesc@"__stringify(__LINE__)": ",
++ print_hex_dump(KERN_ERR, "jobdesc@"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
+ #endif
+
+@@ -1447,7 +1640,7 @@
+ * allocate space for base edesc and hw desc commands,
+ * link tables
+ */
+- edesc = kmalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN +
++ edesc = kzalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN +
+ sec4_sg_bytes, GFP_DMA | flags);
+ if (!edesc) {
+ dev_err(jrdev,
+@@ -1460,19 +1653,13 @@
+ edesc->sec4_sg_bytes = sec4_sg_bytes;
+ edesc->sec4_sg = (void *)edesc + sizeof(struct ahash_edesc) +
+ DESC_JOB_IO_LEN;
+- edesc->dst_dma = 0;
++ edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg,
++ sec4_sg_bytes,
++ DMA_TO_DEVICE);
+
+ if (src_nents) {
+ sg_to_sec4_sg_last(req->src, src_nents,
+ edesc->sec4_sg, 0);
+- edesc->sec4_sg_dma = dma_map_single(jrdev,
+- edesc->sec4_sg,
+- sec4_sg_bytes,
+- DMA_TO_DEVICE);
+- if (dma_mapping_error(jrdev, edesc->sec4_sg_dma)) {
+- dev_err(jrdev, "unable to map S/G table\n");
+- return -ENOMEM;
+- }
+ src_dma = edesc->sec4_sg_dma;
+ options = LDST_SGF;
+ } else {
+@@ -1491,12 +1678,12 @@
+
+ append_seq_in_ptr(desc, src_dma, to_hash, options);
+
+- ret = map_seq_out_ptr_ctx(desc, jrdev, state, ctx->ctx_len);
+- if (ret)
+- return ret;
++ map_seq_out_ptr_ctx(desc, jrdev, state, ctx->ctx_len);
+
++ dma_sync_single_for_device(jrdev, edesc->sec4_sg_dma,
++ sec4_sg_bytes, DMA_TO_DEVICE);
+ #ifdef DEBUG
+- print_hex_dump(KERN_ERR, "jobdesc@"__stringify(__LINE__)": ",
++ print_hex_dump(KERN_ERR, "jobdesc@"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, desc,
+ desc_bytes(desc), 1);
+ #endif
+@@ -1521,7 +1708,7 @@
+ req->nbytes, 0);
+ }
+ #ifdef DEBUG
+- print_hex_dump(KERN_ERR, "next buf@"__stringify(__LINE__)": ",
++ print_hex_dump(KERN_ERR, "next buf@"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, next_buf,
+ *next_buflen, 1);
+ #endif
+@@ -1735,10 +1922,33 @@
+ .alg_type = OP_ALG_ALGSEL_MD5,
+ .alg_op = OP_ALG_ALGSEL_MD5 | OP_ALG_AAI_HMAC,
+ },
++ {
++ .name = "xcbc(aes)",
++ .driver_name = "xcbc-aes-caam",
++ .hmac_name = "xcbc(aes)",
++ .hmac_driver_name = "xcbc-aes-caam",
++ .blocksize = XCBC_MAC_BLOCK_WORDS * 4,
++ .template_ahash = {
++ .init = ahash_init,
++ .update = ahash_update,
++ .final = ahash_final,
++ .finup = ahash_finup,
++ .digest = ahash_digest,
++ .export = ahash_export,
++ .import = ahash_import,
++ .setkey = axcbc_setkey,
++ .halg = {
++ .digestsize = XCBC_MAC_DIGEST_SIZE,
++ },
++ },
++ .alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_XCBC_MAC,
++ .alg_op = OP_ALG_ALGSEL_AES,
++ },
+ };
+
+ struct caam_hash_alg {
+ struct list_head entry;
++ struct device *ctrldev;
+ int alg_type;
+ int alg_op;
+ struct ahash_alg ahash_alg;
+@@ -1755,6 +1965,7 @@
+ struct caam_hash_alg *caam_hash =
+ container_of(alg, struct caam_hash_alg, ahash_alg);
+ struct caam_hash_ctx *ctx = crypto_tfm_ctx(tfm);
++ struct caam_drv_private *priv = dev_get_drvdata(caam_hash->ctrldev);
+ /* Sizes for MDHA running digests: MD5, SHA1, 224, 256, 384, 512 */
+ static const u8 runninglen[] = { HASH_MSG_LEN + MD5_DIGEST_SIZE,
+ HASH_MSG_LEN + SHA1_DIGEST_SIZE,
+@@ -1762,17 +1973,15 @@
+ HASH_MSG_LEN + SHA256_DIGEST_SIZE,
+ HASH_MSG_LEN + 64,
+ HASH_MSG_LEN + SHA512_DIGEST_SIZE };
++ int tgt_jr = atomic_inc_return(&priv->tfm_count);
+ int ret = 0;
+
+ /*
+- * Get a Job ring from Job Ring driver to ensure in-order
++ * distribute tfms across job rings to ensure in-order
+ * crypto request processing per tfm
+ */
+- ctx->jrdev = caam_jr_alloc();
+- if (IS_ERR(ctx->jrdev)) {
+- pr_err("Job Ring Device allocation for transform failed\n");
+- return PTR_ERR(ctx->jrdev);
+- }
++ ctx->jrdev = priv->jrdev[tgt_jr % priv->total_jobrs];
++
+ /* copy descriptor header template value */
+ ctx->alg_type = OP_TYPE_CLASS2_ALG | caam_hash->alg_type;
+ ctx->alg_op = OP_TYPE_CLASS2_ALG | caam_hash->alg_op;
+@@ -1788,6 +1997,39 @@
+ return ret;
+ }
+
++static int caam_axcbc_cra_init(struct crypto_tfm *tfm)
++{
++ struct crypto_ahash *ahash = __crypto_ahash_cast(tfm);
++ struct crypto_alg *base = tfm->__crt_alg;
++ struct hash_alg_common *halg =
++ container_of(base, struct hash_alg_common, base);
++ struct ahash_alg *alg =
++ container_of(halg, struct ahash_alg, halg);
++ struct caam_hash_alg *caam_hash =
++ container_of(alg, struct caam_hash_alg, ahash_alg);
++ struct caam_hash_ctx *ctx = crypto_tfm_ctx(tfm);
++ struct caam_drv_private *priv = dev_get_drvdata(caam_hash->ctrldev);
++ int tgt_jr = atomic_inc_return(&priv->tfm_count);
++ int ret = 0;
++
++ /*
++ * distribute tfms across job rings to ensure in-order
++ * crypto request processing per tfm
++ */
++ ctx->jrdev = priv->jrdev[tgt_jr % priv->total_jobrs];
++
++ /* copy descriptor header template value */
++ ctx->alg_type = OP_TYPE_CLASS1_ALG | caam_hash->alg_type;
++ ctx->alg_op = OP_TYPE_CLASS1_ALG | caam_hash->alg_op;
++
++ crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
++ sizeof(struct caam_hash_state));
++
++ ret = axcbc_set_sh_desc(ahash);
++
++ return ret;
++}
++
+ static void caam_hash_cra_exit(struct crypto_tfm *tfm)
+ {
+ struct caam_hash_ctx *ctx = crypto_tfm_ctx(tfm);
+@@ -1815,35 +2057,57 @@
+ !dma_mapping_error(ctx->jrdev, ctx->sh_desc_finup_dma))
+ dma_unmap_single(ctx->jrdev, ctx->sh_desc_finup_dma,
+ desc_bytes(ctx->sh_desc_finup), DMA_TO_DEVICE);
+-
+- caam_jr_free(ctx->jrdev);
+ }
+
+ static void __exit caam_algapi_hash_exit(void)
+ {
++ struct device_node *dev_node;
++ struct platform_device *pdev;
++ struct device *ctrldev;
++ struct caam_drv_private *priv;
+ struct caam_hash_alg *t_alg, *n;
+
+- if (!hash_list.next)
++ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
++ if (!dev_node) {
++ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec4.0");
++ if (!dev_node)
++ return;
++ }
++
++ pdev = of_find_device_by_node(dev_node);
++ if (!pdev) {
++ of_node_put(dev_node);
+ return;
++ }
+
+- list_for_each_entry_safe(t_alg, n, &hash_list, entry) {
++ ctrldev = &pdev->dev;
++ priv = dev_get_drvdata(ctrldev);
++
++ if (!priv->hash_list.next) {
++ of_node_put(dev_node);
++ return;
++ }
++
++ list_for_each_entry_safe(t_alg, n, &priv->hash_list, entry) {
+ crypto_unregister_ahash(&t_alg->ahash_alg);
+ list_del(&t_alg->entry);
+ kfree(t_alg);
+ }
++
++ of_node_put(dev_node);
+ }
+
+ static struct caam_hash_alg *
+-caam_hash_alloc(struct caam_hash_template *template,
++caam_hash_alloc(struct device *ctrldev, struct caam_hash_template *template,
+ bool keyed)
+ {
+ struct caam_hash_alg *t_alg;
+ struct ahash_alg *halg;
+ struct crypto_alg *alg;
+
+- t_alg = kzalloc(sizeof(struct caam_hash_alg), GFP_KERNEL);
++ t_alg = kzalloc(sizeof(struct caam_hash_alg), GFP_ATOMIC);
+ if (!t_alg) {
+- pr_err("failed to allocate t_alg\n");
++ dev_err(ctrldev, "failed to allocate t_alg\n");
+ return ERR_PTR(-ENOMEM);
+ }
+
+@@ -1863,7 +2127,11 @@
+ template->driver_name);
+ }
+ alg->cra_module = THIS_MODULE;
+- alg->cra_init = caam_hash_cra_init;
++
++ if (strstr(alg->cra_name, "xcbc") > 0)
++ alg->cra_init = caam_axcbc_cra_init;
++ else
++ alg->cra_init = caam_hash_cra_init;
+ alg->cra_exit = caam_hash_cra_exit;
+ alg->cra_ctxsize = sizeof(struct caam_hash_ctx);
+ alg->cra_priority = CAAM_CRA_PRIORITY;
+@@ -1874,6 +2142,7 @@
+
+ t_alg->alg_type = template->alg_type;
+ t_alg->alg_op = template->alg_op;
++ t_alg->ctrldev = ctrldev;
+
+ return t_alg;
+ }
+@@ -1883,8 +2152,9 @@
+ struct device_node *dev_node;
+ struct platform_device *pdev;
+ struct device *ctrldev;
+- void *priv;
+- int i = 0, err = 0;
++ struct caam_drv_private *priv;
++ int i = 0, err = 0, md_limit = 0, md_inst;
++ u64 cha_inst;
+
+ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
+ if (!dev_node) {
+@@ -1898,60 +2168,68 @@
+ of_node_put(dev_node);
+ return -ENODEV;
+ }
+-
+ ctrldev = &pdev->dev;
+ priv = dev_get_drvdata(ctrldev);
+- of_node_put(dev_node);
+
+- /*
+- * If priv is NULL, it's probably because the caam driver wasn't
+- * properly initialized (e.g. RNG4 init failed). Thus, bail out here.
+- */
+- if (!priv)
+- return -ENODEV;
++ INIT_LIST_HEAD(&priv->hash_list);
+
+- INIT_LIST_HEAD(&hash_list);
++ atomic_set(&priv->tfm_count, -1);
++
++ /* register algorithms the device supports */
++ cha_inst = rd_reg64(&priv->ctrl->perfmon.cha_num);
++ md_inst = (cha_inst & CHA_ID_MD_MASK) >> CHA_ID_MD_SHIFT;
++ if (md_inst) {
++ md_limit = SHA512_DIGEST_SIZE;
++ if ((rd_reg64(&priv->ctrl->perfmon.cha_id) & CHA_ID_MD_MASK)
++ == CHA_ID_MD_LP256) /* LP256 limits digest size */
++ md_limit = SHA256_DIGEST_SIZE;
++ }
+
+- /* register crypto algorithms the device supports */
+ for (i = 0; i < ARRAY_SIZE(driver_hash); i++) {
+- /* TODO: check if h/w supports alg */
+ struct caam_hash_alg *t_alg;
+
++ /* If no MD instantiated, or MD too small, skip */
++ if ((!md_inst) ||
++ (driver_hash[i].template_ahash.halg.digestsize >
++ md_limit))
++ continue;
++
+ /* register hmac version */
+- t_alg = caam_hash_alloc(&driver_hash[i], true);
++ t_alg = caam_hash_alloc(ctrldev, &driver_hash[i], true);
+ if (IS_ERR(t_alg)) {
+ err = PTR_ERR(t_alg);
+- pr_warn("%s alg allocation failed\n",
+- driver_hash[i].driver_name);
++ dev_warn(ctrldev, "%s alg allocation failed\n",
++ driver_hash[i].driver_name);
+ continue;
+ }
+
+ err = crypto_register_ahash(&t_alg->ahash_alg);
+ if (err) {
+- pr_warn("%s alg registration failed\n",
++ dev_warn(ctrldev, "%s alg registration failed\n",
+ t_alg->ahash_alg.halg.base.cra_driver_name);
+ kfree(t_alg);
+ } else
+- list_add_tail(&t_alg->entry, &hash_list);
++ list_add_tail(&t_alg->entry, &priv->hash_list);
+
+ /* register unkeyed version */
+- t_alg = caam_hash_alloc(&driver_hash[i], false);
++ t_alg = caam_hash_alloc(ctrldev, &driver_hash[i], false);
+ if (IS_ERR(t_alg)) {
+ err = PTR_ERR(t_alg);
+- pr_warn("%s alg allocation failed\n",
+- driver_hash[i].driver_name);
++ dev_warn(ctrldev, "%s alg allocation failed\n",
++ driver_hash[i].driver_name);
+ continue;
+ }
+
+ err = crypto_register_ahash(&t_alg->ahash_alg);
+ if (err) {
+- pr_warn("%s alg registration failed\n",
++ dev_warn(ctrldev, "%s alg registration failed\n",
+ t_alg->ahash_alg.halg.base.cra_driver_name);
+ kfree(t_alg);
+ } else
+- list_add_tail(&t_alg->entry, &hash_list);
++ list_add_tail(&t_alg->entry, &priv->hash_list);
+ }
+
++ of_node_put(dev_node);
+ return err;
+ }
+
+diff -Nur linux-4.1.3/drivers/crypto/caam/caam_keyblob.c linux-xbian-imx6/drivers/crypto/caam/caam_keyblob.c
+--- linux-4.1.3/drivers/crypto/caam/caam_keyblob.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/crypto/caam/caam_keyblob.c 2015-07-27 23:13:04.205975852 +0200
+@@ -0,0 +1,687 @@
++/*
++ * Key blob driver based on CAAM hardware
++ *
++ * Copyright (C) 2015 Freescale Semiconductor, Inc.
++ */
++
++#include <linux/of_irq.h>
++#include <linux/of_address.h>
++
++#include "compat.h"
++#include "regs.h"
++#include "jr.h"
++#include "desc.h"
++#include "intern.h"
++#include "sm.h"
++#include "caam_keyblob.h"
++
++#define INITIAL_DESCSZ 16 /* size of tmp buffer for descriptor const. */
++
++/**
++ * struct kb_device - the metadata of the caam key blob device node
++ * @dev: the actual misc device
++ */
++struct kb_device {
++ struct miscdevice misc_dev;
++ struct device *jr_dev;
++};
++
++/*
++ * Pseudo-synchronous ring access functions for carrying out key
++ * encapsulation and decapsulation
++ */
++
++struct sm_key_job_result {
++ int error;
++ struct completion completion;
++};
++
++
++static struct kb_device *kb_dev;
++
++static struct kb_device *kb_device_create(void);
++static int kb_device_destroy(struct kb_device *kb_dev);
++static int kb_open(struct inode *inode, struct file *file);
++static int kb_release(struct inode *inode, struct file *file);
++static void sm_key_job_done(struct device *dev, u32 *desc,
++ u32 err, void *context);
++static int gen_mem_encap(struct device *jr_dev, void __user *secretbuf,
++ int keylen, void __user *kmodbuf, void __user *outbuf);
++static int gen_mem_decap(struct device *jr_dev, void __user *keyblobbuf,
++ int bloblen, void __user *kmodbuf, void __user *outbuf);
++static long kb_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
++static int caam_keyblob_probe(struct platform_device *pdev);
++static int caam_keyblob_remove(struct platform_device *pdev);
++
++static int kb_open(struct inode *inode, struct file *file)
++{
++ struct miscdevice *miscdev = file->private_data;
++ struct kb_device *dev = container_of(miscdev, struct kb_device, misc_dev);
++ struct device *jr_dev;
++
++ if (!dev->jr_dev) {
++ jr_dev = caam_jr_alloc();
++ if (IS_ERR(jr_dev)) {
++ pr_err("Job Ring Device allocation for transform failed\n");
++ return -ENOMEM;
++ }
++ pr_info("Allocate a job ring device\n");
++ dev->jr_dev = jr_dev;
++ }
++ else {
++ pr_err("Already created a job ring device");
++ return -EPERM;
++ }
++
++ return 0;
++}
++
++static int kb_release(struct inode *inode, struct file *file)
++{
++ struct miscdevice *miscdev = file->private_data;
++ struct kb_device *dev = container_of(miscdev, struct kb_device, misc_dev);
++
++ if (dev && dev->jr_dev) {
++ caam_jr_free(dev->jr_dev);
++ pr_info("Free a job ring device\n");
++ dev->jr_dev = NULL;
++ }
++ return 0;
++}
++
++static void sm_key_job_done(struct device *dev, u32 *desc,
++ u32 err, void *context)
++{
++ struct sm_key_job_result *res = context;
++
++ res->error = err; /* save off the error for postprocessing */
++ complete(&res->completion); /* mark us complete */
++}
++
++/*
++ * Construct a blob encapsulation job descriptor
++ *
++ * This function dynamically constructs a blob encapsulation job descriptor
++ * from the following arguments:
++ *
++ * - desc pointer to a pointer to the descriptor generated by this
++ * function. Caller will be responsible to kfree() this
++ * descriptor after execution.
++ * - keymod Physical pointer to a key modifier, which must reside in a
++ * contiguous piece of memory. Modifier will be assumed to be
++ * 8 bytes long for a blob of type SM_SECMEM, or 16 bytes long
++ * for a blob of type SM_GENMEM (see blobtype argument).
++ * - secretbuf Physical pointer to a secret, normally a black or red key,
++ * possibly residing within an accessible secure memory page,
++ * of the secret to be encapsulated to an output blob.
++ * - outbuf Physical pointer to the destination buffer to receive the
++ * encapsulated output. This buffer will need to be 48 bytes
++ * larger than the input because of the added encapsulation data.
++ * The generated descriptor will account for the increase in size,
++ * but the caller must also account for this increase in the
++ * buffer allocator.
++ * - secretsz Size of input secret, in bytes. This is limited to 65536
++ * less the size of blob overhead, since the length embeds into
++ * DECO pointer in/out instructions.
++ * - keycolor Determines if the source data is covered (black key) or
++ * plaintext (red key). RED_KEY or BLACK_KEY are defined in
++ * for this purpose.
++ * - blobtype Determine if encapsulated blob should be a secure memory
++ * blob (SM_SECMEM), with partition data embedded with key
++ * material, or a general memory blob (SM_GENMEM).
++ * - auth If BLACK_KEY source is covered via AES-CCM, specify
++ * KEY_COVER_CCM, else uses AES-ECB (KEY_COVER_ECB).
++ *
++ * Upon completion, desc points to a buffer containing a CAAM job
++ * descriptor which encapsulates data into an externally-storable blob
++ * suitable for use across power cycles.
++ *
++ * This is an example of a black key encapsulation job into a general memory
++ * blob. Notice the 16-byte key modifier in the LOAD instruction. Also note
++ * the output 48 bytes longer than the input:
++ *
++ * [00] B0800008 jobhdr: stidx=0 len=8
++ * [01] 14400010 ld: ccb2-key len=16 offs=0
++ * [02] 08144891 ptr->@0x08144891
++ * [03] F800003A seqoutptr: len=58
++ * [04] 01000000 out_ptr->@0x01000000
++ * [05] F000000A seqinptr: len=10
++ * [06] 09745090 in_ptr->@0x09745090
++ * [07] 870D0004 operation: encap blob reg=memory, black, format=normal
++ *
++ * This is an example of a red key encapsulation job for storing a red key
++ * into a secure memory blob. Note the 8 byte modifier on the 12 byte offset
++ * in the LOAD instruction; this accounts for blob permission storage:
++ *
++ * [00] B0800008 jobhdr: stidx=0 len=8
++ * [01] 14400C08 ld: ccb2-key len=8 offs=12
++ * [02] 087D0784 ptr->@0x087d0784
++ * [03] F8000050 seqoutptr: len=80
++ * [04] 09251BB2 out_ptr->@0x09251bb2
++ * [05] F0000020 seqinptr: len=32
++ * [06] 40000F31 in_ptr->@0x40000f31
++ * [07] 870D0008 operation: encap blob reg=memory, red, sec_mem,
++ * format=normal
++ *
++ * Note: this function only generates 32-bit pointers at present, and should
++ * be refactored using a scheme that allows both 32 and 64 bit addressing
++ */
++
++static int blob_encap_jobdesc(u32 **desc, dma_addr_t keymod,
++ void *secretbuf, dma_addr_t outbuf,
++ u16 secretsz, u8 keycolor, u8 blobtype, u8 auth)
++{
++ u32 *tdesc, tmpdesc[INITIAL_DESCSZ];
++ u16 dsize, idx;
++
++ memset(tmpdesc, 0, INITIAL_DESCSZ * sizeof(u32));
++ idx = 1;
++
++ /*
++ * Key modifier works differently for secure/general memory blobs
++ * This accounts for the permission/protection data encapsulated
++ * within the blob if a secure memory blob is requested
++ */
++ if (blobtype == SM_SECMEM)
++ tmpdesc[idx++] = CMD_LOAD | LDST_CLASS_2_CCB |
++ LDST_SRCDST_BYTE_KEY |
++ ((12 << LDST_OFFSET_SHIFT) & LDST_OFFSET_MASK)
++ | (8 & LDST_LEN_MASK);
++ else /* is general memory blob */
++ tmpdesc[idx++] = CMD_LOAD | LDST_CLASS_2_CCB |
++ LDST_SRCDST_BYTE_KEY | (16 & LDST_LEN_MASK);
++
++ tmpdesc[idx++] = (u32)keymod;
++
++ /*
++ * Encapsulation output must include space for blob key encryption
++ * key and MAC tag
++ */
++ tmpdesc[idx++] = CMD_SEQ_OUT_PTR | (secretsz + BLOB_OVERHEAD);
++ tmpdesc[idx++] = (u32)outbuf;
++
++ /* Input data, should be somewhere in secure memory */
++ tmpdesc[idx++] = CMD_SEQ_IN_PTR | secretsz;
++ tmpdesc[idx++] = (u32)secretbuf;
++
++ /* Set blob encap, then color */
++ tmpdesc[idx] = CMD_OPERATION | OP_TYPE_ENCAP_PROTOCOL | OP_PCLID_BLOB;
++
++ if (blobtype == SM_SECMEM)
++ tmpdesc[idx] |= OP_PCL_BLOB_PTXT_SECMEM;
++
++ if (auth == KEY_COVER_CCM)
++ tmpdesc[idx] |= OP_PCL_BLOB_EKT;
++
++ if (keycolor == BLACK_KEY)
++ tmpdesc[idx] |= OP_PCL_BLOB_BLACK;
++
++ idx++;
++ tmpdesc[0] = CMD_DESC_HDR | HDR_ONE | (idx & HDR_DESCLEN_MASK);
++ dsize = idx * sizeof(u32);
++
++ tdesc = kmalloc(dsize, GFP_KERNEL | GFP_DMA);
++ if (tdesc == NULL)
++ return 0;
++
++ memcpy(tdesc, tmpdesc, dsize);
++ *desc = tdesc;
++ return dsize;
++}
++
++/*
++ * Construct a blob decapsulation job descriptor
++ *
++ * This function dynamically constructs a blob decapsulation job descriptor
++ * from the following arguments:
++ *
++ * - desc pointer to a pointer to the descriptor generated by this
++ * function. Caller will be responsible to kfree() this
++ * descriptor after execution.
++ * - keymod Physical pointer to a key modifier, which must reside in a
++ * contiguous piece of memory. Modifier will be assumed to be
++ * 8 bytes long for a blob of type SM_SECMEM, or 16 bytes long
++ * for a blob of type SM_GENMEM (see blobtype argument).
++ * - blobbuf Physical pointer (into external memory) of the blob to
++ * be decapsulated. Blob must reside in a contiguous memory
++ * segment.
++ * - outbuf Physical pointer of the decapsulated output, possibly into
++ * a location within a secure memory page. Must be contiguous.
++ * - secretsz Size of encapsulated secret in bytes (not the size of the
++ * input blob).
++ * - keycolor Determines if decapsulated content is encrypted (BLACK_KEY)
++ * or left as plaintext (RED_KEY).
++ * - blobtype Determine if encapsulated blob should be a secure memory
++ * blob (SM_SECMEM), with partition data embedded with key
++ * material, or a general memory blob (SM_GENMEM).
++ * - auth If decapsulation path is specified by BLACK_KEY, then if
++ * AES-CCM is requested for key covering use KEY_COVER_CCM, else
++ * use AES-ECB (KEY_COVER_ECB).
++ *
++ * Upon completion, desc points to a buffer containing a CAAM job descriptor
++ * that decapsulates a key blob from external memory into a black (encrypted)
++ * key or red (plaintext) content.
++ *
++ * This is an example of a black key decapsulation job from a general memory
++ * blob. Notice the 16-byte key modifier in the LOAD instruction.
++ *
++ * [00] B0800008 jobhdr: stidx=0 len=8
++ * [01] 14400010 ld: ccb2-key len=16 offs=0
++ * [02] 08A63B7F ptr->@0x08a63b7f
++ * [03] F8000010 seqoutptr: len=16
++ * [04] 01000000 out_ptr->@0x01000000
++ * [05] F000003A seqinptr: len=58
++ * [06] 01000010 in_ptr->@0x01000010
++ * [07] 860D0004 operation: decap blob reg=memory, black, format=normal
++ *
++ * This is an example of a red key decapsulation job for restoring a red key
++ * from a secure memory blob. Note the 8 byte modifier on the 12 byte offset
++ * in the LOAD instruction:
++ *
++ * [00] B0800008 jobhdr: stidx=0 len=8
++ * [01] 14400C08 ld: ccb2-key len=8 offs=12
++ * [02] 01000000 ptr->@0x01000000
++ * [03] F8000020 seqoutptr: len=32
++ * [04] 400000E6 out_ptr->@0x400000e6
++ * [05] F0000050 seqinptr: len=80
++ * [06] 08F0C0EA in_ptr->@0x08f0c0ea
++ * [07] 860D0008 operation: decap blob reg=memory, red, sec_mem,
++ * format=normal
++ *
++ * Note: this function only generates 32-bit pointers at present, and should
++ * be refactored using a scheme that allows both 32 and 64 bit addressing
++ */
++
++static int blob_decap_jobdesc(u32 **desc, dma_addr_t keymod, dma_addr_t blobbuf,
++ u8 *outbuf, u16 secretsz, u8 keycolor,
++ u8 blobtype, u8 auth)
++{
++ u32 *tdesc, tmpdesc[INITIAL_DESCSZ];
++ u16 dsize, idx;
++
++ memset(tmpdesc, 0, INITIAL_DESCSZ * sizeof(u32));
++ idx = 1;
++
++ /* Load key modifier */
++ if (blobtype == SM_SECMEM)
++ tmpdesc[idx++] = CMD_LOAD | LDST_CLASS_2_CCB |
++ LDST_SRCDST_BYTE_KEY |
++ ((12 << LDST_OFFSET_SHIFT) & LDST_OFFSET_MASK)
++ | (8 & LDST_LEN_MASK);
++ else /* is general memory blob */
++ tmpdesc[idx++] = CMD_LOAD | LDST_CLASS_2_CCB |
++ LDST_SRCDST_BYTE_KEY | (16 & LDST_LEN_MASK);
++
++ tmpdesc[idx++] = (u32)keymod;
++
++ /* Compensate BKEK + MAC tag over size of encapsulated secret */
++ tmpdesc[idx++] = CMD_SEQ_IN_PTR | (secretsz + BLOB_OVERHEAD);
++ tmpdesc[idx++] = (u32)blobbuf;
++ tmpdesc[idx++] = CMD_SEQ_OUT_PTR | secretsz;
++ tmpdesc[idx++] = (u32)outbuf;
++
++ /* Decapsulate from secure memory partition to black blob */
++ tmpdesc[idx] = CMD_OPERATION | OP_TYPE_DECAP_PROTOCOL | OP_PCLID_BLOB;
++
++ if (blobtype == SM_SECMEM)
++ tmpdesc[idx] |= OP_PCL_BLOB_PTXT_SECMEM;
++
++ if (auth == KEY_COVER_CCM)
++ tmpdesc[idx] |= OP_PCL_BLOB_EKT;
++
++ if (keycolor == BLACK_KEY)
++ tmpdesc[idx] |= OP_PCL_BLOB_BLACK;
++
++ idx++;
++ tmpdesc[0] = CMD_DESC_HDR | HDR_ONE | (idx & HDR_DESCLEN_MASK);
++ dsize = idx * sizeof(u32);
++
++ tdesc = kmalloc(dsize, GFP_KERNEL | GFP_DMA);
++ if (tdesc == NULL)
++ return 0;
++
++ memcpy(tdesc, tmpdesc, dsize);
++ *desc = tdesc;
++ return dsize;
++}
++
++
++
++static int gen_mem_encap(struct device *jr_dev, void __user *secretbuf,
++ int keylen, void __user *kmodbuf, void __user *outbuf)
++{
++ int retval = 0;
++ u32 dsize;
++ u32 __iomem *encapdesc = NULL;
++ dma_addr_t secret_dma = 0, keymod_dma = 0, outbuf_dma = 0;
++ u8 __iomem *lsecret = NULL, *lkeymod = NULL, *loutbuf = NULL;
++ struct sm_key_job_result testres;
++
++ /* Build/map/flush the scret */
++ lsecret = kmalloc(keylen, GFP_KERNEL | GFP_DMA);
++ if (!lsecret) {
++ dev_err(jr_dev, "%s: can't alloc for key\n", __func__);
++ retval = -ENOMEM;
++ goto out;
++ }
++ if (copy_from_user(lsecret, secretbuf, keylen)) {
++ dev_err(jr_dev, "%s: can't Copy for key\n", __func__);
++ retval = -EFAULT;
++ goto out;
++ }
++ secret_dma = dma_map_single(jr_dev, lsecret, keylen,
++ DMA_TO_DEVICE);
++
++ /* Build/map/flush the key modifier */
++ lkeymod = kmalloc(GENMEM_KEYMOD_LEN, GFP_KERNEL | GFP_DMA);
++ if (!lkeymod) {
++ dev_err(jr_dev, "%s: can't alloc for keymod\n", __func__);
++ retval = -ENOMEM;
++ goto out;
++ }
++ if (copy_from_user(lkeymod, kmodbuf, GENMEM_KEYMOD_LEN)) {
++ dev_err(jr_dev, "%s: can't Copy for keymod\n", __func__);
++ retval = -EFAULT;
++ goto out;
++ }
++ keymod_dma = dma_map_single(jr_dev, lkeymod, GENMEM_KEYMOD_LEN,
++ DMA_TO_DEVICE);
++
++ loutbuf = kmalloc(keylen + BLOB_OVERHEAD, GFP_KERNEL | GFP_DMA);
++ if (!lkeymod) {
++ dev_err(jr_dev, "%s: can't alloc for output\n", __func__);
++ retval = -ENOMEM;
++ goto out;
++ }
++ outbuf_dma = dma_map_single(jr_dev, loutbuf, keylen + BLOB_OVERHEAD,
++ DMA_FROM_DEVICE);
++ dsize = blob_encap_jobdesc(&encapdesc, keymod_dma, (void *)secret_dma, outbuf_dma,
++ keylen, RED_KEY, SM_GENMEM, KEY_COVER_ECB);
++ if (!dsize) {
++ dev_err(jr_dev, "can't alloc an encapsulation descriptor\n");
++ retval = -ENOMEM;
++ goto out;
++ }
++ init_completion(&testres.completion);
++
++ retval = caam_jr_enqueue(jr_dev, encapdesc, sm_key_job_done,
++ &testres);
++ if (!retval) {
++ wait_for_completion_interruptible(&testres.completion);
++ dev_info(jr_dev, "job ring return %d\n", testres.error);
++ if (!testres.error) {
++ dma_sync_single_for_cpu(jr_dev, outbuf_dma, keylen + BLOB_OVERHEAD,
++ DMA_FROM_DEVICE);
++
++ if (copy_to_user(outbuf, loutbuf, keylen + BLOB_OVERHEAD)) {
++ retval = -EFAULT;
++ dev_err(jr_dev, "can't copy for output\n");
++ goto out;
++ }
++ }
++ retval = testres.error;
++ }
++
++out:
++ if (outbuf_dma)
++ dma_unmap_single(jr_dev, outbuf_dma, keylen + BLOB_OVERHEAD,
++ DMA_FROM_DEVICE);
++ if (keymod_dma)
++ dma_unmap_single(jr_dev, keymod_dma, GENMEM_KEYMOD_LEN, DMA_TO_DEVICE);
++ if (secret_dma)
++ dma_unmap_single(jr_dev, secret_dma, keylen, DMA_TO_DEVICE);
++ kfree(encapdesc);
++ kfree(lkeymod);
++ kfree(lsecret);
++ kfree(loutbuf);
++
++ return retval;
++}
++
++static int gen_mem_decap(struct device *jr_dev, void __user *keyblobbuf,
++ int bloblen, void __user *kmodbuf, void __user *outbuf)
++{
++ int retval = 0;
++ int keylen = bloblen - BLOB_OVERHEAD;
++ u32 dsize;
++ dma_addr_t keyblob_dma = 0, keymod_dma = 0, outbuf_dma = 0;
++ u8 __iomem *lkeyblob = NULL, *lkeymod = NULL, *loutbuf = NULL;
++ struct sm_key_job_result testres;
++ u32 __iomem *decapdesc = NULL;
++
++ /* Build/map/flush the scret */
++ lkeyblob = kmalloc(bloblen, GFP_KERNEL | GFP_DMA);
++ if (!lkeyblob) {
++ dev_err(jr_dev, "%s: can't alloc for keylob\n", __func__);
++ retval = -ENOMEM;
++ goto out;
++ }
++ if (copy_from_user(lkeyblob, keyblobbuf, bloblen)) {
++ dev_err(jr_dev, "%s: can't Copy for keyblob\n", __func__);
++ retval = -EFAULT;
++ goto out;
++ }
++ keyblob_dma = dma_map_single(jr_dev, lkeyblob, bloblen,
++ DMA_TO_DEVICE);
++
++ /* Build/map/flush the key modifier */
++ lkeymod = kmalloc(GENMEM_KEYMOD_LEN, GFP_KERNEL | GFP_DMA);
++ if (!lkeymod) {
++ dev_err(jr_dev, "%s: can't alloc for keymod\n", __func__);
++ retval = -ENOMEM;
++ goto out;
++ }
++ if (copy_from_user(lkeymod, kmodbuf, GENMEM_KEYMOD_LEN)) {
++ dev_err(jr_dev, "%s: can't Copy for keymod\n", __func__);
++ retval = -EFAULT;
++ goto out;
++ }
++ keymod_dma = dma_map_single(jr_dev, lkeymod, GENMEM_KEYMOD_LEN,
++ DMA_TO_DEVICE);
++
++ loutbuf = kmalloc(keylen, GFP_KERNEL | GFP_DMA);
++ if (!loutbuf) {
++ dev_err(jr_dev, "%s: can't alloc for outbuf\n", __func__);
++ retval = -ENOMEM;
++ goto out;
++ }
++ outbuf_dma = dma_map_single(jr_dev, loutbuf, keylen,
++ DMA_FROM_DEVICE);
++
++ /* Build the encapsulation job descriptor */
++ dsize = blob_decap_jobdesc(&decapdesc, keymod_dma, keyblob_dma, (u8 *)outbuf_dma,
++ keylen, RED_KEY, SM_GENMEM, KEY_COVER_ECB);
++ if (!dsize) {
++ dev_err(jr_dev, "can't alloc a decapsulation descriptor\n");
++ retval = -ENOMEM;
++ goto out;
++ }
++
++ init_completion(&testres.completion);
++
++ retval = caam_jr_enqueue(jr_dev, decapdesc, sm_key_job_done,
++ &testres);
++ if (!retval) {
++ wait_for_completion_interruptible(&testres.completion);
++ dev_info(jr_dev, "job ring return %d\n", testres.error);
++ if (!testres.error) {
++ dma_sync_single_for_cpu(jr_dev, outbuf_dma, keylen,
++ DMA_FROM_DEVICE);
++
++ if (copy_to_user(outbuf, loutbuf, keylen)) {
++ retval = -EFAULT;
++ goto out;
++ }
++ }
++ retval = testres.error;
++ }
++
++out:
++ if (outbuf_dma)
++ dma_unmap_single(jr_dev, outbuf_dma, keylen,
++ DMA_FROM_DEVICE);
++ if (keymod_dma)
++ dma_unmap_single(jr_dev, keymod_dma, GENMEM_KEYMOD_LEN,
++ DMA_TO_DEVICE);
++ if (keyblob_dma)
++ dma_unmap_single(jr_dev, keyblob_dma, bloblen,
++ DMA_TO_DEVICE);
++ kfree(decapdesc);
++ kfree(lkeymod);
++ kfree(lkeyblob);
++ kfree(loutbuf);
++
++ return retval;
++}
++
++
++static long kb_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
++{
++ int retval = 0;
++ struct caam_kb_data kb_data;
++ struct miscdevice *miscdev = file->private_data;
++ struct kb_device *dev = container_of(miscdev, struct kb_device, misc_dev);
++
++ if (copy_from_user(&kb_data, (void *)arg, sizeof(kb_data))) {
++ retval = -EFAULT;
++ goto err;
++ }
++
++ if (!kb_data.rawkey || !kb_data.keyblob ||
++ (kb_data.rawkey_len + BLOB_OVERHEAD != kb_data.keyblob_len) ||
++ (kb_data.keymod_len != GENMEM_KEYMOD_LEN)) {
++ retval = -EINVAL;
++ goto err;
++ }
++
++ printk(KERN_INFO"%s:rawkey_len %d, keyblob_len %d\n",
++ __func__, kb_data.rawkey_len, kb_data.keyblob_len);
++
++ switch (cmd) {
++ case CAAM_KB_ENCRYPT:
++ {
++ retval = gen_mem_encap(dev->jr_dev, kb_data.rawkey, kb_data.rawkey_len,
++ kb_data.keymod, kb_data.keyblob);
++ break;
++ }
++ case CAAM_KB_DECRYPT:
++ {
++ retval = gen_mem_decap(dev->jr_dev, kb_data.keyblob, kb_data.keyblob_len,
++ kb_data.keymod, kb_data.rawkey);
++ break;
++ }
++ default:
++ return -ENOTTY;
++ }
++
++err:
++ return retval;
++}
++
++static const struct file_operations kb_fops = {
++ .owner = THIS_MODULE,
++ .open = kb_open,
++ .release = kb_release,
++ .unlocked_ioctl = kb_ioctl,
++};
++
++static struct kb_device *kb_device_create(void)
++{
++ struct kb_device *idev;
++ int ret;
++
++ idev = kzalloc(sizeof(struct kb_device), GFP_KERNEL);
++ if (!idev)
++ return ERR_PTR(-ENOMEM);
++
++ idev->misc_dev.minor = MISC_DYNAMIC_MINOR;
++ idev->misc_dev.name = "caam_kb";
++ idev->misc_dev.fops = &kb_fops;
++ idev->misc_dev.parent = NULL;
++ ret = misc_register(&idev->misc_dev);
++ if (ret) {
++ pr_err("ion: failed to register misc device.\n");
++ return ERR_PTR(ret);
++ }
++
++ return idev;
++}
++
++static int kb_device_destroy(struct kb_device *kb_dev)
++{
++ if ((kb_dev) && (kb_dev->jr_dev)) {
++ caam_jr_free(kb_dev->jr_dev);
++ kb_dev->jr_dev = NULL;
++ }
++
++ if (kb_dev)
++ misc_deregister(&kb_dev->misc_dev);
++
++ return 0;
++}
++/*
++ * Probe key blob device
++ */
++static int caam_keyblob_probe(struct platform_device *pdev)
++{
++ int err;
++
++ dev_dbg(&pdev->dev, "%s enter\n", __func__);
++ kb_dev = kb_device_create();
++ if (IS_ERR_OR_NULL(kb_dev)) {
++ err = PTR_ERR(kb_dev);
++ goto err;
++ }
++ return 0;
++err:
++ return err;
++}
++
++/*
++ * Remove key blob device
++ */
++static int caam_keyblob_remove(struct platform_device *pdev)
++{
++ kb_device_destroy(kb_dev);
++ return 0;
++}
++
++static struct of_device_id caam_keyblob_match[] = {
++ {
++ .compatible = "fsl,sec-v4.0-keyblob",
++ },
++ {
++ .compatible = "fsl,sec4.0-keyblob",
++ },
++ {},
++};
++
++MODULE_DEVICE_TABLE(of, caam_keyblob_match);
++
++static struct platform_driver caam_keyblob_driver = {
++ .driver = {
++ .name = "caam_keyblob",
++ .owner = THIS_MODULE,
++ .of_match_table = caam_keyblob_match,
++ },
++ .probe = caam_keyblob_probe,
++ .remove = caam_keyblob_remove,
++};
++
++static int __init keyblob_driver_init(void)
++{
++ return platform_driver_register(&caam_keyblob_driver);
++}
++
++static void __exit keyblob_driver_exit(void)
++{
++ platform_driver_unregister(&caam_keyblob_driver);
++}
++
++module_init(keyblob_driver_init);
++module_exit(keyblob_driver_exit);
++
++
++MODULE_LICENSE("Dual BSD/GPL");
++MODULE_DESCRIPTION("FSL CAAM Secure Memory / Keystore");
++MODULE_AUTHOR("Freescale Semiconductor - NMSG/MAD");
+diff -Nur linux-4.1.3/drivers/crypto/caam/caam_keyblob.h linux-xbian-imx6/drivers/crypto/caam/caam_keyblob.h
+--- linux-4.1.3/drivers/crypto/caam/caam_keyblob.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/crypto/caam/caam_keyblob.h 2015-07-27 23:13:04.205975852 +0200
+@@ -0,0 +1,45 @@
++/*
++ * CAAM public-level include definitions for the key blob
++ *
++ * Copyright (C) 2015 Freescale Semiconductor, Inc.
++ */
++
++#ifndef CAAM_KEYBLOB_H
++#define CAAM_KEYBLOB_H
++
++
++#include <linux/ioctl.h>
++#include <linux/types.h>
++
++struct caam_kb_data {
++ char *rawkey;
++ size_t rawkey_len;
++ char *keyblob;
++ size_t keyblob_len;
++ char *keymod;
++ size_t keymod_len;
++};
++
++
++#define CAAM_KB_MAGIC 'I'
++
++/**
++ * DOC: CAAM_KB_ENCRYPT - generate a key blob from raw key
++ *
++ * Takes an caam_kb_data struct and returns it with the key blob
++ */
++#define CAAM_KB_ENCRYPT _IOWR(CAAM_KB_MAGIC, 0, \
++ struct caam_kb_data)
++
++/**
++ * DOC: CAAM_KB_DECRYPT - get keys from a key blob
++ *
++ * Takes an caam_kb_data struct and returns it with the raw key.
++ */
++#define CAAM_KB_DECRYPT _IOWR(CAAM_KB_MAGIC, 1, struct caam_kb_data)
++
++#ifndef GENMEM_KEYMOD_LEN
++#define GENMEM_KEYMOD_LEN 16
++#endif
++
++#endif /* CAAM_KEYBLOB_H */
+diff -Nur linux-4.1.3/drivers/crypto/caam/caamrng.c linux-xbian-imx6/drivers/crypto/caam/caamrng.c
+--- linux-4.1.3/drivers/crypto/caam/caamrng.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/drivers/crypto/caam/caamrng.c 2015-07-27 23:13:04.209961631 +0200
+@@ -1,7 +1,7 @@
+ /*
+ * caam - Freescale FSL CAAM support for hw_random
+ *
+- * Copyright 2011 Freescale Semiconductor, Inc.
++ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
+ *
+ * Based on caamalg.c crypto API driver.
+ *
+@@ -80,9 +80,12 @@
+
+ static inline void rng_unmap_buf(struct device *jrdev, struct buf_data *bd)
+ {
+- if (bd->addr)
++ if (bd->addr) {
++ dma_sync_single_for_cpu(jrdev, bd->addr, RN_BUF_SIZE,
++ DMA_FROM_DEVICE);
+ dma_unmap_single(jrdev, bd->addr, RN_BUF_SIZE,
+ DMA_FROM_DEVICE);
++ }
+ }
+
+ static inline void rng_unmap_ctx(struct caam_rng_ctx *ctx)
+@@ -103,11 +106,18 @@
+ bd = (struct buf_data *)((char *)desc -
+ offsetof(struct buf_data, hw_desc));
+
+- if (err)
+- caam_jr_strstatus(jrdev, err);
++ if (err) {
++ char tmp[CAAM_ERROR_STR_MAX];
++
++ dev_err(jrdev, "%08x: %s\n", err, caam_jr_strstatus(tmp, err));
++ }
+
+ atomic_set(&bd->empty, BUF_NOT_EMPTY);
+ complete(&bd->filled);
++
++ /* Buffer refilled, invalidate cache */
++ dma_sync_single_for_cpu(jrdev, bd->addr, RN_BUF_SIZE, DMA_FROM_DEVICE);
++
+ #ifdef DEBUG
+ print_hex_dump(KERN_ERR, "rng refreshed buf@: ",
+ DUMP_PREFIX_ADDRESS, 16, 4, bd->buf, RN_BUF_SIZE, 1);
+@@ -185,7 +195,7 @@
+ max - copied_idx, false);
+ }
+
+-static inline int rng_create_sh_desc(struct caam_rng_ctx *ctx)
++static inline void rng_create_sh_desc(struct caam_rng_ctx *ctx)
+ {
+ struct device *jrdev = ctx->jrdev;
+ u32 *desc = ctx->sh_desc;
+@@ -203,18 +213,16 @@
+
+ ctx->sh_desc_dma = dma_map_single(jrdev, desc, desc_bytes(desc),
+ DMA_TO_DEVICE);
+- if (dma_mapping_error(jrdev, ctx->sh_desc_dma)) {
+- dev_err(jrdev, "unable to map shared descriptor\n");
+- return -ENOMEM;
+- }
++ dma_sync_single_for_device(jrdev, ctx->sh_desc_dma, desc_bytes(desc),
++ DMA_TO_DEVICE);
++
+ #ifdef DEBUG
+ print_hex_dump(KERN_ERR, "rng shdesc@: ", DUMP_PREFIX_ADDRESS, 16, 4,
+ desc, desc_bytes(desc), 1);
+ #endif
+- return 0;
+ }
+
+-static inline int rng_create_job_desc(struct caam_rng_ctx *ctx, int buf_id)
++static inline void rng_create_job_desc(struct caam_rng_ctx *ctx, int buf_id)
+ {
+ struct device *jrdev = ctx->jrdev;
+ struct buf_data *bd = &ctx->bufs[buf_id];
+@@ -225,17 +233,12 @@
+ HDR_REVERSE);
+
+ bd->addr = dma_map_single(jrdev, bd->buf, RN_BUF_SIZE, DMA_FROM_DEVICE);
+- if (dma_mapping_error(jrdev, bd->addr)) {
+- dev_err(jrdev, "unable to map dst\n");
+- return -ENOMEM;
+- }
+
+ append_seq_out_ptr_intlen(desc, bd->addr, RN_BUF_SIZE, 0);
+ #ifdef DEBUG
+ print_hex_dump(KERN_ERR, "rng job desc@: ", DUMP_PREFIX_ADDRESS, 16, 4,
+ desc, desc_bytes(desc), 1);
+ #endif
+- return 0;
+ }
+
+ static void caam_cleanup(struct hwrng *rng)
+@@ -252,44 +255,67 @@
+ rng_unmap_ctx(rng_ctx);
+ }
+
+-static int caam_init_buf(struct caam_rng_ctx *ctx, int buf_id)
++#ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_TEST
++static inline void test_len(struct hwrng *rng, size_t len, bool wait)
+ {
+- struct buf_data *bd = &ctx->bufs[buf_id];
+- int err;
++ u8 *buf;
++ int real_len;
+
+- err = rng_create_job_desc(ctx, buf_id);
+- if (err)
+- return err;
++ buf = kzalloc(sizeof(u8) * len, GFP_KERNEL);
++ real_len = rng->read(rng, buf, len, wait);
++ if (real_len == 0 && wait)
++ pr_err("WAITING FAILED\n");
++ pr_info("wanted %d bytes, got %d\n", len, real_len);
++ print_hex_dump(KERN_INFO, "random bytes@: ", DUMP_PREFIX_ADDRESS,
++ 16, 4, buf, real_len, 1);
++ kfree(buf);
++}
+
+- atomic_set(&bd->empty, BUF_EMPTY);
+- submit_job(ctx, buf_id == ctx->current_buf);
+- wait_for_completion(&bd->filled);
++static inline void test_mode_once(struct hwrng *rng, bool wait)
++{
++#define TEST_CHUNK (RN_BUF_SIZE / 4)
+
+- return 0;
++ test_len(rng, TEST_CHUNK, wait);
++ test_len(rng, RN_BUF_SIZE * 2, wait);
++ test_len(rng, RN_BUF_SIZE * 2 - TEST_CHUNK, wait);
+ }
+
+-static int caam_init_rng(struct caam_rng_ctx *ctx, struct device *jrdev)
++static inline void test_mode(struct hwrng *rng, bool wait)
+ {
+- int err;
+-
+- ctx->jrdev = jrdev;
++#define TEST_PASS 1
++ int i;
+
+- err = rng_create_sh_desc(ctx);
+- if (err)
+- return err;
++ for (i = 0; i < TEST_PASS; i++)
++ test_mode_once(rng, wait);
++}
+
+- ctx->current_buf = 0;
+- ctx->cur_buf_idx = 0;
++static void self_test(struct hwrng *rng)
++{
++ pr_info("testing without waiting\n");
++ test_mode(rng, false);
++ pr_info("testing with waiting\n");
++ test_mode(rng, true);
++}
++#endif
+
+- err = caam_init_buf(ctx, 0);
+- if (err)
+- return err;
++static void caam_init_buf(struct caam_rng_ctx *ctx, int buf_id)
++{
++ struct buf_data *bd = &ctx->bufs[buf_id];
+
+- err = caam_init_buf(ctx, 1);
+- if (err)
+- return err;
++ rng_create_job_desc(ctx, buf_id);
++ atomic_set(&bd->empty, BUF_EMPTY);
++ submit_job(ctx, buf_id == ctx->current_buf);
++ wait_for_completion(&bd->filled);
++}
+
+- return 0;
++static void caam_init_rng(struct caam_rng_ctx *ctx, struct device *jrdev)
++{
++ ctx->jrdev = jrdev;
++ rng_create_sh_desc(ctx);
++ ctx->current_buf = 0;
++ ctx->cur_buf_idx = 0;
++ caam_init_buf(ctx, 0);
++ caam_init_buf(ctx, 1);
+ }
+
+ static struct hwrng caam_rng = {
+@@ -300,19 +326,15 @@
+
+ static void __exit caam_rng_exit(void)
+ {
+- caam_jr_free(rng_ctx->jrdev);
+ hwrng_unregister(&caam_rng);
+- kfree(rng_ctx);
+ }
+
+ static int __init caam_rng_init(void)
+ {
+- struct device *dev;
+ struct device_node *dev_node;
+ struct platform_device *pdev;
+ struct device *ctrldev;
+- void *priv;
+- int err;
++ struct caam_drv_private *priv;
+
+ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
+ if (!dev_node) {
+@@ -322,35 +344,26 @@
+ }
+
+ pdev = of_find_device_by_node(dev_node);
+- if (!pdev) {
+- of_node_put(dev_node);
++ if (!pdev)
+ return -ENODEV;
+- }
+
+ ctrldev = &pdev->dev;
+ priv = dev_get_drvdata(ctrldev);
+ of_node_put(dev_node);
+
+- /*
+- * If priv is NULL, it's probably because the caam driver wasn't
+- * properly initialized (e.g. RNG4 init failed). Thus, bail out here.
+- */
+- if (!priv)
++ /* Check RNG present in hardware before registration */
++ if (!(rd_reg64(&priv->ctrl->perfmon.cha_num) & CHA_ID_RNG_MASK))
+ return -ENODEV;
+
+- dev = caam_jr_alloc();
+- if (IS_ERR(dev)) {
+- pr_err("Job Ring Device allocation for transform failed\n");
+- return PTR_ERR(dev);
+- }
+- rng_ctx = kmalloc(sizeof(struct caam_rng_ctx), GFP_DMA);
+- if (!rng_ctx)
+- return -ENOMEM;
+- err = caam_init_rng(rng_ctx, dev);
+- if (err)
+- return err;
++ rng_ctx = kmalloc(sizeof(struct caam_rng_ctx), GFP_KERNEL | GFP_DMA);
++
++ caam_init_rng(rng_ctx, priv->jrdev[0]);
++
++#ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_TEST
++ self_test(&caam_rng);
++#endif
+
+- dev_info(dev, "registering rng-caam\n");
++ dev_info(priv->jrdev[0], "registering rng-caam\n");
+ return hwrng_register(&caam_rng);
+ }
+
+diff -Nur linux-4.1.3/drivers/crypto/caam/compat.h linux-xbian-imx6/drivers/crypto/caam/compat.h
+--- linux-4.1.3/drivers/crypto/caam/compat.h 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/drivers/crypto/caam/compat.h 2015-07-27 23:13:04.209961631 +0200
+@@ -14,6 +14,8 @@
+ #include <linux/hash.h>
+ #include <linux/hw_random.h>
+ #include <linux/of_platform.h>
++#include <linux/of_address.h>
++#include <linux/of_irq.h>
+ #include <linux/dma-mapping.h>
+ #include <linux/io.h>
+ #include <linux/spinlock.h>
+@@ -23,12 +25,15 @@
+ #include <linux/types.h>
+ #include <linux/debugfs.h>
+ #include <linux/circ_buf.h>
++#include <crypto/scatterwalk.h>
++
++#ifdef CONFIG_ARM /* needs the clock control subsystem */
++#include <linux/clk.h>
++#endif
+ #include <net/xfrm.h>
+
+ #include <crypto/algapi.h>
+-#include <crypto/null.h>
+ #include <crypto/aes.h>
+-#include <crypto/ctr.h>
+ #include <crypto/des.h>
+ #include <crypto/sha.h>
+ #include <crypto/md5.h>
+diff -Nur linux-4.1.3/drivers/crypto/caam/ctrl.c linux-xbian-imx6/drivers/crypto/caam/ctrl.c
+--- linux-4.1.3/drivers/crypto/caam/ctrl.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/drivers/crypto/caam/ctrl.c 2015-07-27 23:13:04.209961631 +0200
+@@ -1,405 +1,260 @@
+-/* * CAAM control-plane driver backend
++/*
++ * CAAM control-plane driver backend
+ * Controller-level driver, kernel property detection, initialization
+ *
+- * Copyright 2008-2012 Freescale Semiconductor, Inc.
++ * Copyright (C) 2008-2013 Freescale Semiconductor, Inc.
+ */
+
+-#include <linux/device.h>
+-#include <linux/of_address.h>
+-#include <linux/of_irq.h>
+-
+ #include "compat.h"
+ #include "regs.h"
+ #include "intern.h"
+ #include "jr.h"
+ #include "desc_constr.h"
+ #include "error.h"
++#include "ctrl.h"
++#include "sm.h"
++#include <linux/device.h>
+
+-/*
+- * Descriptor to instantiate RNG State Handle 0 in normal mode and
+- * load the JDKEK, TDKEK and TDSK registers
+- */
+-static void build_instantiation_desc(u32 *desc, int handle, int do_sk)
+-{
+- u32 *jump_cmd, op_flags;
+-
+- init_job_desc(desc, 0);
+-
+- op_flags = OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
+- (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INIT;
+-
+- /* INIT RNG in non-test mode */
+- append_operation(desc, op_flags);
+-
+- if (!handle && do_sk) {
+- /*
+- * For SH0, Secure Keys must be generated as well
+- */
++/* Used to capture the array of job rings */
++struct device **caam_jr_dev;
+
+- /* wait for done */
+- jump_cmd = append_jump(desc, JUMP_CLASS_CLASS1);
+- set_jump_tgt_here(desc, jump_cmd);
++static int caam_remove(struct platform_device *pdev)
++{
++ struct device *ctrldev;
++ struct caam_drv_private *ctrlpriv;
++ struct caam_drv_private_jr *jrpriv;
++ struct caam_full __iomem *topregs;
++ int ring, ret = 0;
+
+- /*
+- * load 1 to clear written reg:
+- * resets the done interrrupt and returns the RNG to idle.
+- */
+- append_load_imm_u32(desc, 1, LDST_SRCDST_WORD_CLRW);
++ ctrldev = &pdev->dev;
++ ctrlpriv = dev_get_drvdata(ctrldev);
++ topregs = (struct caam_full __iomem *)ctrlpriv->ctrl;
+
+- /* Initialize State Handle */
+- append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
+- OP_ALG_AAI_RNG4_SK);
++ /* shut down JobRs */
++ for (ring = 0; ring < ctrlpriv->total_jobrs; ring++) {
++ ret |= caam_jr_shutdown(ctrlpriv->jrdev[ring]);
++ jrpriv = dev_get_drvdata(ctrlpriv->jrdev[ring]);
++ irq_dispose_mapping(jrpriv->irq);
+ }
+
+- append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT);
+-}
++ /* Shut down debug views */
++#ifdef CONFIG_DEBUG_FS
++ debugfs_remove_recursive(ctrlpriv->dfs_root);
++#endif
+
+-/* Descriptor for deinstantiation of State Handle 0 of the RNG block. */
+-static void build_deinstantiation_desc(u32 *desc, int handle)
+-{
+- init_job_desc(desc, 0);
++ /* Unmap controller region */
++ iounmap(&topregs->ctrl);
+
+- /* Uninstantiate State Handle 0 */
+- append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
+- (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INITFINAL);
++#ifdef CONFIG_ARM
++ /* shut clocks off before finalizing shutdown */
++ clk_disable(ctrlpriv->caam_ipg);
++ clk_disable(ctrlpriv->caam_mem);
++ clk_disable(ctrlpriv->caam_aclk);
++#endif
++
++ kfree(ctrlpriv->jrdev);
++ kfree(ctrlpriv);
+
+- append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT);
++ return ret;
+ }
+
+ /*
+- * run_descriptor_deco0 - runs a descriptor on DECO0, under direct control of
+- * the software (no JR/QI used).
+- * @ctrldev - pointer to device
+- * @status - descriptor status, after being run
+- *
+- * Return: - 0 if no error occurred
+- * - -ENODEV if the DECO couldn't be acquired
+- * - -EAGAIN if an error occurred while executing the descriptor
++ * Descriptor to instantiate RNG State Handle 0 in normal mode and
++ * load the JDKEK, TDKEK and TDSK registers
+ */
+-static inline int run_descriptor_deco0(struct device *ctrldev, u32 *desc,
+- u32 *status)
++static void build_instantiation_desc(u32 *desc)
+ {
+- struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
+- struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl;
+- struct caam_deco __iomem *deco = ctrlpriv->deco;
+- unsigned int timeout = 100000;
+- u32 deco_dbg_reg, flags;
+- int i;
+-
++ u32 *jump_cmd;
+
+- if (ctrlpriv->virt_en == 1) {
+- setbits32(&ctrl->deco_rsr, DECORSR_JR0);
+-
+- while (!(rd_reg32(&ctrl->deco_rsr) & DECORSR_VALID) &&
+- --timeout)
+- cpu_relax();
+-
+- timeout = 100000;
+- }
+-
+- setbits32(&ctrl->deco_rq, DECORR_RQD0ENABLE);
+-
+- while (!(rd_reg32(&ctrl->deco_rq) & DECORR_DEN0) &&
+- --timeout)
+- cpu_relax();
++ init_job_desc(desc, 0);
+
+- if (!timeout) {
+- dev_err(ctrldev, "failed to acquire DECO 0\n");
+- clrbits32(&ctrl->deco_rq, DECORR_RQD0ENABLE);
+- return -ENODEV;
+- }
++ /* INIT RNG in non-test mode */
++ append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
++ OP_ALG_AS_INIT);
+
+- for (i = 0; i < desc_len(desc); i++)
+- wr_reg32(&deco->descbuf[i], *(desc + i));
++ /* wait for done */
++ jump_cmd = append_jump(desc, JUMP_CLASS_CLASS1);
++ set_jump_tgt_here(desc, jump_cmd);
+
+- flags = DECO_JQCR_WHL;
+ /*
+- * If the descriptor length is longer than 4 words, then the
+- * FOUR bit in JRCTRL register must be set.
++ * load 1 to clear written reg:
++ * resets the done interrupt and returns the RNG to idle.
+ */
+- if (desc_len(desc) >= 4)
+- flags |= DECO_JQCR_FOUR;
++ append_load_imm_u32(desc, 1, LDST_SRCDST_WORD_CLRW);
+
+- /* Instruct the DECO to execute it */
+- wr_reg32(&deco->jr_ctl_hi, flags);
+-
+- timeout = 10000000;
+- do {
+- deco_dbg_reg = rd_reg32(&deco->desc_dbg);
+- /*
+- * If an error occured in the descriptor, then
+- * the DECO status field will be set to 0x0D
+- */
+- if ((deco_dbg_reg & DESC_DBG_DECO_STAT_MASK) ==
+- DESC_DBG_DECO_STAT_HOST_ERR)
+- break;
+- cpu_relax();
+- } while ((deco_dbg_reg & DESC_DBG_DECO_STAT_VALID) && --timeout);
+-
+- *status = rd_reg32(&deco->op_status_hi) &
+- DECO_OP_STATUS_HI_ERR_MASK;
+-
+- if (ctrlpriv->virt_en == 1)
+- clrbits32(&ctrl->deco_rsr, DECORSR_JR0);
+-
+- /* Mark the DECO as free */
+- clrbits32(&ctrl->deco_rq, DECORR_RQD0ENABLE);
+-
+- if (!timeout)
+- return -EAGAIN;
+-
+- return 0;
+ }
+
+-/*
+- * instantiate_rng - builds and executes a descriptor on DECO0,
+- * which initializes the RNG block.
+- * @ctrldev - pointer to device
+- * @state_handle_mask - bitmask containing the instantiation status
+- * for the RNG4 state handles which exist in
+- * the RNG4 block: 1 if it's been instantiated
+- * by an external entry, 0 otherwise.
+- * @gen_sk - generate data to be loaded into the JDKEK, TDKEK and TDSK;
+- * Caution: this can be done only once; if the keys need to be
+- * regenerated, a POR is required
+- *
+- * Return: - 0 if no error occurred
+- * - -ENOMEM if there isn't enough memory to allocate the descriptor
+- * - -ENODEV if DECO0 couldn't be acquired
+- * - -EAGAIN if an error occurred when executing the descriptor
+- * f.i. there was a RNG hardware error due to not "good enough"
+- * entropy being aquired.
+- */
+-static int instantiate_rng(struct device *ctrldev, int state_handle_mask,
+- int gen_sk)
++static void generate_secure_keys_desc(u32 *desc)
+ {
+- struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
+- struct caam_ctrl __iomem *ctrl;
+- u32 *desc, status, rdsta_val;
+- int ret = 0, sh_idx;
+-
+- ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
+- desc = kmalloc(CAAM_CMD_SZ * 7, GFP_KERNEL);
+- if (!desc)
+- return -ENOMEM;
++ /* generate secure keys (non-test) */
++ append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
++ OP_ALG_RNG4_SK);
++}
+
+- for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
+- /*
+- * If the corresponding bit is set, this state handle
+- * was initialized by somebody else, so it's left alone.
+- */
+- if ((1 << sh_idx) & state_handle_mask)
+- continue;
++struct instantiate_result {
++ struct completion completion;
++ int err;
++};
+
+- /* Create the descriptor for instantiating RNG State Handle */
+- build_instantiation_desc(desc, sh_idx, gen_sk);
++static void rng4_init_done(struct device *dev, u32 *desc, u32 err,
++ void *context)
++{
++ struct instantiate_result *instantiation = context;
+
+- /* Try to run it through DECO0 */
+- ret = run_descriptor_deco0(ctrldev, desc, &status);
++ if (err) {
++ char tmp[CAAM_ERROR_STR_MAX];
+
+- /*
+- * If ret is not 0, or descriptor status is not 0, then
+- * something went wrong. No need to try the next state
+- * handle (if available), bail out here.
+- * Also, if for some reason, the State Handle didn't get
+- * instantiated although the descriptor has finished
+- * without any error (HW optimizations for later
+- * CAAM eras), then try again.
+- */
+- rdsta_val = rd_reg32(&ctrl->r4tst[0].rdsta) & RDSTA_IFMASK;
+- if (status || !(rdsta_val & (1 << sh_idx)))
+- ret = -EAGAIN;
+- if (ret)
+- break;
+- dev_info(ctrldev, "Instantiated RNG4 SH%d\n", sh_idx);
+- /* Clear the contents before recreating the descriptor */
+- memset(desc, 0x00, CAAM_CMD_SZ * 7);
++ dev_err(dev, "%08x: %s\n", err, caam_jr_strstatus(tmp, err));
+ }
+
+- kfree(desc);
+-
+- return ret;
++ instantiation->err = err;
++ complete(&instantiation->completion);
+ }
+
+-/*
+- * deinstantiate_rng - builds and executes a descriptor on DECO0,
+- * which deinitializes the RNG block.
+- * @ctrldev - pointer to device
+- * @state_handle_mask - bitmask containing the instantiation status
+- * for the RNG4 state handles which exist in
+- * the RNG4 block: 1 if it's been instantiated
+- *
+- * Return: - 0 if no error occurred
+- * - -ENOMEM if there isn't enough memory to allocate the descriptor
+- * - -ENODEV if DECO0 couldn't be acquired
+- * - -EAGAIN if an error occurred when executing the descriptor
+- */
+-static int deinstantiate_rng(struct device *ctrldev, int state_handle_mask)
++static int instantiate_rng(struct device *jrdev, u32 keys_generated)
+ {
+- u32 *desc, status;
+- int sh_idx, ret = 0;
++ struct instantiate_result instantiation;
+
+- desc = kmalloc(CAAM_CMD_SZ * 3, GFP_KERNEL);
+- if (!desc)
++ dma_addr_t desc_dma;
++ u32 *desc;
++ int ret;
++
++ desc = kmalloc(CAAM_CMD_SZ * 6, GFP_KERNEL | GFP_DMA);
++ if (!desc) {
++ dev_err(jrdev, "cannot allocate RNG init descriptor memory\n");
+ return -ENOMEM;
+-
+- for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
+- /*
+- * If the corresponding bit is set, then it means the state
+- * handle was initialized by us, and thus it needs to be
+- * deintialized as well
+- */
+- if ((1 << sh_idx) & state_handle_mask) {
+- /*
+- * Create the descriptor for deinstantating this state
+- * handle
+- */
+- build_deinstantiation_desc(desc, sh_idx);
+-
+- /* Try to run it through DECO0 */
+- ret = run_descriptor_deco0(ctrldev, desc, &status);
+-
+- if (ret || status) {
+- dev_err(ctrldev,
+- "Failed to deinstantiate RNG4 SH%d\n",
+- sh_idx);
+- break;
+- }
+- dev_info(ctrldev, "Deinstantiated RNG4 SH%d\n", sh_idx);
+- }
+ }
+
+- kfree(desc);
+-
+- return ret;
+-}
++ build_instantiation_desc(desc);
+
+-static int caam_remove(struct platform_device *pdev)
+-{
+- struct device *ctrldev;
+- struct caam_drv_private *ctrlpriv;
+- struct caam_ctrl __iomem *ctrl;
+- int ring, ret = 0;
+-
+- ctrldev = &pdev->dev;
+- ctrlpriv = dev_get_drvdata(ctrldev);
+- ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
+-
+- /* Remove platform devices for JobRs */
+- for (ring = 0; ring < ctrlpriv->total_jobrs; ring++) {
+- if (ctrlpriv->jrpdev[ring])
+- of_device_unregister(ctrlpriv->jrpdev[ring]);
++ /* If keys have not been generated, add op code to generate key. */
++ if (!keys_generated)
++ generate_secure_keys_desc(desc);
++
++ desc_dma = dma_map_single(jrdev, desc, desc_bytes(desc), DMA_TO_DEVICE);
++ dma_sync_single_for_device(jrdev, desc_dma, desc_bytes(desc),
++ DMA_TO_DEVICE);
++ init_completion(&instantiation.completion);
++ ret = caam_jr_enqueue(jrdev, desc, rng4_init_done, &instantiation);
++ if (!ret) {
++ wait_for_completion_interruptible(&instantiation.completion);
++ ret = instantiation.err;
++ if (ret)
++ dev_err(jrdev, "unable to instantiate RNG\n");
+ }
+
+- /* De-initialize RNG state handles initialized by this driver. */
+- if (ctrlpriv->rng4_sh_init)
+- deinstantiate_rng(ctrldev, ctrlpriv->rng4_sh_init);
+-
+- /* Shut down debug views */
+-#ifdef CONFIG_DEBUG_FS
+- debugfs_remove_recursive(ctrlpriv->dfs_root);
+-#endif
++ dma_unmap_single(jrdev, desc_dma, desc_bytes(desc), DMA_TO_DEVICE);
+
+- /* Unmap controller region */
+- iounmap(&ctrl);
++ kfree(desc);
+
+ return ret;
+ }
+
+ /*
+- * kick_trng - sets the various parameters for enabling the initialization
+- * of the RNG4 block in CAAM
+- * @pdev - pointer to the platform device
+- * @ent_delay - Defines the length (in system clocks) of each entropy sample.
++ * By default, the TRNG runs for 200 clocks per sample;
++ * 1600 clocks per sample generates better entropy.
+ */
+-static void kick_trng(struct platform_device *pdev, int ent_delay)
++static void kick_trng(struct platform_device *pdev)
+ {
+ struct device *ctrldev = &pdev->dev;
+ struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
+- struct caam_ctrl __iomem *ctrl;
++ struct caam_full __iomem *topregs;
+ struct rng4tst __iomem *r4tst;
+ u32 val;
+
+- ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
+- r4tst = &ctrl->r4tst[0];
++ topregs = (struct caam_full __iomem *)ctrlpriv->ctrl;
++ r4tst = &topregs->ctrl.r4tst[0];
+
++ val = rd_reg32(&r4tst->rtmctl);
+ /* put RNG4 into program mode */
+ setbits32(&r4tst->rtmctl, RTMCTL_PRGM);
+-
+- /*
+- * Performance-wise, it does not make sense to
+- * set the delay to a value that is lower
+- * than the last one that worked (i.e. the state handles
+- * were instantiated properly. Thus, instead of wasting
+- * time trying to set the values controlling the sample
+- * frequency, the function simply returns.
+- */
+- val = (rd_reg32(&r4tst->rtsdctl) & RTSDCTL_ENT_DLY_MASK)
+- >> RTSDCTL_ENT_DLY_SHIFT;
+- if (ent_delay <= val) {
+- /* put RNG4 into run mode */
+- clrbits32(&r4tst->rtmctl, RTMCTL_PRGM);
+- return;
+- }
+-
++ /* Set clocks per sample to the default, and divider to zero */
+ val = rd_reg32(&r4tst->rtsdctl);
+ val = (val & ~RTSDCTL_ENT_DLY_MASK) |
+- (ent_delay << RTSDCTL_ENT_DLY_SHIFT);
++ (RNG4_ENT_CLOCKS_SAMPLE << RTSDCTL_ENT_DLY_SHIFT);
+ wr_reg32(&r4tst->rtsdctl, val);
+- /* min. freq. count, equal to 1/4 of the entropy sample length */
+- wr_reg32(&r4tst->rtfrqmin, ent_delay >> 2);
+- /* disable maximum frequency count */
+- wr_reg32(&r4tst->rtfrqmax, RTFRQMAX_DISABLE);
+- /* read the control register */
+- val = rd_reg32(&r4tst->rtmctl);
+- /*
+- * select raw sampling in both entropy shifter
+- * and statistical checker
+- */
+- setbits32(&val, RTMCTL_SAMP_MODE_RAW_ES_SC);
++ /* min. freq. count */
++ wr_reg32(&r4tst->rtfrqmin, RNG4_ENT_CLOCKS_SAMPLE / 4);
++ /* max. freq. count */
++ wr_reg32(&r4tst->rtfrqmax, RNG4_ENT_CLOCKS_SAMPLE * 8);
+ /* put RNG4 into run mode */
+- clrbits32(&val, RTMCTL_PRGM);
+- /* write back the control register */
+- wr_reg32(&r4tst->rtmctl, val);
++ clrbits32(&r4tst->rtmctl, RTMCTL_PRGM);
+ }
+
+ /**
+ * caam_get_era() - Return the ERA of the SEC on SoC, based
+- * on "sec-era" propery in the DTS. This property is updated by u-boot.
++ * on the SEC_VID register.
++ * Returns the ERA number (1..4) or -ENOTSUPP if the ERA is unknown.
++ * @caam_id - the value of the SEC_VID register
+ **/
+-int caam_get_era(void)
++int caam_get_era(u64 caam_id)
+ {
+- struct device_node *caam_node;
+- for_each_compatible_node(caam_node, NULL, "fsl,sec-v4.0") {
+- const uint32_t *prop = (uint32_t *)of_get_property(caam_node,
+- "fsl,sec-era",
+- NULL);
+- return prop ? *prop : -ENOTSUPP;
+- }
++ struct sec_vid *sec_vid = (struct sec_vid *)&caam_id;
++ static const struct {
++ u16 ip_id;
++ u8 maj_rev;
++ u8 era;
++ } caam_eras[] = {
++ {0x0A10, 1, 1},
++ {0x0A10, 2, 2},
++ {0x0A12, 1, 3},
++ {0x0A14, 1, 3},
++ {0x0A14, 2, 4},
++ {0x0A16, 1, 4},
++ {0x0A11, 1, 4},
++ {0x0A10, 3, 4},
++ {0x0A18, 1, 4},
++ {0x0A11, 2, 5},
++ {0x0A12, 2, 5},
++ {0x0A13, 1, 5},
++ {0x0A1C, 1, 5},
++ {0x0A12, 4, 6},
++ {0x0A13, 2, 6},
++ {0x0A16, 2, 6},
++ {0x0A18, 2, 6},
++ {0x0A1A, 1, 6},
++ {0x0A1C, 2, 6},
++ {0x0A17, 1, 6}
++ };
++ int i;
++
++ for (i = 0; i < ARRAY_SIZE(caam_eras); i++)
++ if (caam_eras[i].ip_id == sec_vid->ip_id &&
++ caam_eras[i].maj_rev == sec_vid->maj_rev)
++ return caam_eras[i].era;
+
+ return -ENOTSUPP;
+ }
+ EXPORT_SYMBOL(caam_get_era);
+
++/*
++ * Return a job ring device. This is available so outside
++ * entities can gain direct access to the job ring. For now,
++ * this function returns the first job ring (at index 0).
++ */
++struct device *caam_get_jrdev(void)
++{
++ return caam_jr_dev[0];
++}
++EXPORT_SYMBOL(caam_get_jrdev);
++
++
+ /* Probe routine for CAAM top (controller) level */
+ static int caam_probe(struct platform_device *pdev)
+ {
+- int ret, ring, rspec, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN;
++ int ret, ring, rspec;
+ u64 caam_id;
+ struct device *dev;
+ struct device_node *nprop, *np;
+ struct caam_ctrl __iomem *ctrl;
++ struct caam_full __iomem *topregs;
++ struct snvs_full __iomem *snvsregs;
+ struct caam_drv_private *ctrlpriv;
+ #ifdef CONFIG_DEBUG_FS
+ struct caam_perfmon *perfmon;
+ #endif
+- u32 scfgr, comp_params;
+- u32 cha_vid_ls;
+- int pg_size;
+- int BLOCK_OFFSET = 0;
+
+- ctrlpriv = devm_kzalloc(&pdev->dev, sizeof(struct caam_drv_private),
+- GFP_KERNEL);
++ ctrlpriv = kzalloc(sizeof(struct caam_drv_private), GFP_KERNEL);
+ if (!ctrlpriv)
+ return -ENOMEM;
+
+@@ -415,71 +270,128 @@
+ dev_err(dev, "caam: of_iomap() failed\n");
+ return -ENOMEM;
+ }
+- /* Finding the page size for using the CTPR_MS register */
+- comp_params = rd_reg32(&ctrl->perfmon.comp_parms_ms);
+- pg_size = (comp_params & CTPR_MS_PG_SZ_MASK) >> CTPR_MS_PG_SZ_SHIFT;
+-
+- /* Allocating the BLOCK_OFFSET based on the supported page size on
+- * the platform
+- */
+- if (pg_size == 0)
+- BLOCK_OFFSET = PG_SIZE_4K;
+- else
+- BLOCK_OFFSET = PG_SIZE_64K;
+-
+ ctrlpriv->ctrl = (struct caam_ctrl __force *)ctrl;
+- ctrlpriv->assure = (struct caam_assurance __force *)
+- ((uint8_t *)ctrl +
+- BLOCK_OFFSET * ASSURE_BLOCK_NUMBER
+- );
+- ctrlpriv->deco = (struct caam_deco __force *)
+- ((uint8_t *)ctrl +
+- BLOCK_OFFSET * DECO_BLOCK_NUMBER
+- );
++
++ /* topregs used to derive pointers to CAAM sub-blocks only */
++ topregs = (struct caam_full __iomem *)ctrl;
+
+ /* Get the IRQ of the controller (for security violations only) */
+- ctrlpriv->secvio_irq = irq_of_parse_and_map(nprop, 0);
++ ctrlpriv->secvio_irq = of_irq_to_resource(nprop, 0, NULL);
++
++ /* Get SNVS register Page */
++ np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-caam-snvs");
++
++ if (!np)
++ return -ENODEV;
++
++ snvsregs = of_iomap(np, 0);
++ ctrlpriv->snvs = snvsregs;
++ /* Get CAAM-SM node and of_iomap() and save */
++ np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-caam-sm");
++
++ if (!np)
++ return -ENODEV;
++
++ ctrlpriv->sm_base = of_iomap(np, 0);
++ ctrlpriv->sm_size = 0x3fff;
++
++/*
++ * ARM targets tend to have clock control subsystems that can
++ * enable/disable clocking to our device. Turn clocking on to proceed
++ */
++#ifdef CONFIG_ARM
++ ctrlpriv->caam_ipg = devm_clk_get(&ctrlpriv->pdev->dev, "caam_ipg");
++ if (IS_ERR(ctrlpriv->caam_ipg)) {
++ ret = PTR_ERR(ctrlpriv->caam_ipg);
++ dev_err(&ctrlpriv->pdev->dev,
++ "can't identify CAAM ipg clk: %d\n", ret);
++ return -ENODEV;
++ }
++ ctrlpriv->caam_mem = devm_clk_get(&ctrlpriv->pdev->dev, "caam_mem");
++ if (IS_ERR(ctrlpriv->caam_mem)) {
++ ret = PTR_ERR(ctrlpriv->caam_mem);
++ dev_err(&ctrlpriv->pdev->dev,
++ "can't identify CAAM secure mem clk: %d\n", ret);
++ return -ENODEV;
++ }
++ ctrlpriv->caam_aclk = devm_clk_get(&ctrlpriv->pdev->dev, "caam_aclk");
++ if (IS_ERR(ctrlpriv->caam_aclk)) {
++ ret = PTR_ERR(ctrlpriv->caam_aclk);
++ dev_err(&ctrlpriv->pdev->dev,
++ "can't identify CAAM aclk clk: %d\n", ret);
++ return -ENODEV;
++ }
++
++ ret = clk_prepare(ctrlpriv->caam_ipg);
++ if (ret < 0) {
++ dev_err(&pdev->dev, "can't prepare CAAM ipg clock: %d\n", ret);
++ return -ENODEV;
++ }
++ ret = clk_prepare(ctrlpriv->caam_mem);
++ if (ret < 0) {
++ dev_err(&pdev->dev, "can't prepare CAAM secure mem clock: %d\n", ret);
++ return -ENODEV;
++ }
++ ret = clk_prepare(ctrlpriv->caam_aclk);
++ if (ret < 0) {
++ dev_err(&pdev->dev, "can't prepare CAAM aclk clock: %d\n", ret);
++ return -ENODEV;
++ }
++
++ ret = clk_enable(ctrlpriv->caam_ipg);
++ if (ret < 0) {
++ dev_err(&pdev->dev, "can't enable CAAM ipg clock: %d\n", ret);
++ return -ENODEV;
++ }
++ ret = clk_enable(ctrlpriv->caam_mem);
++ if (ret < 0) {
++ dev_err(&pdev->dev, "can't enable CAAM secure mem clock: %d\n", ret);
++ return -ENODEV;
++ }
++ ret = clk_enable(ctrlpriv->caam_aclk);
++ if (ret < 0) {
++ dev_err(&pdev->dev, "can't enable CAAM aclk clock: %d\n", ret);
++ return -ENODEV;
++ }
++
++ pr_debug("%s caam_ipg clock:%d\n", __func__,
++ (int)clk_get_rate(ctrlpriv->caam_ipg));
++ pr_debug("%s caam_mem clock:%d\n", __func__,
++ (int)clk_get_rate(ctrlpriv->caam_mem));
++ pr_debug("%s caam_aclk clock:%d\n", __func__,
++ (int)clk_get_rate(ctrlpriv->caam_aclk));
++#endif
+
+ /*
+ * Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel,
+ * long pointers in master configuration register
+ */
+- setbits32(&ctrl->mcr, MCFGR_WDENABLE |
++ setbits32(&topregs->ctrl.mcr, MCFGR_WDENABLE |
+ (sizeof(dma_addr_t) == sizeof(u64) ? MCFGR_LONG_PTR : 0));
+
++#ifdef CONFIG_ARCH_MX6
+ /*
+- * Read the Compile Time paramters and SCFGR to determine
+- * if Virtualization is enabled for this platform
++ * ERRATA: mx6 devices have an issue wherein AXI bus transactions
++ * may not occur in the correct order. This isn't a problem running
++ * single descriptors, but can be if running multiple concurrent
++ * descriptors. Reworking the driver to throttle to single requests
++ * is impractical, thus the workaround is to limit the AXI pipeline
++ * to a depth of 1 (from it's default of 4) to preclude this situation
++ * from occurring.
+ */
+- scfgr = rd_reg32(&ctrl->scfgr);
+-
+- ctrlpriv->virt_en = 0;
+- if (comp_params & CTPR_MS_VIRT_EN_INCL) {
+- /* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or
+- * VIRT_EN_INCL = 1 & VIRT_EN_POR = 0 & SCFGR_VIRT_EN = 1
+- */
+- if ((comp_params & CTPR_MS_VIRT_EN_POR) ||
+- (!(comp_params & CTPR_MS_VIRT_EN_POR) &&
+- (scfgr & SCFGR_VIRT_EN)))
+- ctrlpriv->virt_en = 1;
+- } else {
+- /* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */
+- if (comp_params & CTPR_MS_VIRT_EN_POR)
+- ctrlpriv->virt_en = 1;
+- }
+-
+- if (ctrlpriv->virt_en == 1)
+- setbits32(&ctrl->jrstart, JRSTART_JR0_START |
+- JRSTART_JR1_START | JRSTART_JR2_START |
+- JRSTART_JR3_START);
++ wr_reg32(&topregs->ctrl.mcr,
++ (rd_reg32(&topregs->ctrl.mcr) & ~(MCFGR_AXIPIPE_MASK)) |
++ ((1 << MCFGR_AXIPIPE_SHIFT) & MCFGR_AXIPIPE_MASK));
++#endif
+
++ /* Set DMA masks according to platform ranging */
+ if (sizeof(dma_addr_t) == sizeof(u64))
+- if (of_device_is_compatible(nprop, "fsl,sec-v5.0"))
+- dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40));
++ if (of_device_is_compatible(nprop, "fsl,sec-v4.0"))
++ dma_set_mask(dev, DMA_BIT_MASK(40));
+ else
+- dma_set_mask_and_coherent(dev, DMA_BIT_MASK(36));
++ dma_set_mask(dev, DMA_BIT_MASK(36));
+ else
+- dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
++ dma_set_mask(dev, DMA_BIT_MASK(32));
+
+ /*
+ * Detect and enable JobRs
+@@ -487,51 +399,65 @@
+ * for all, then go probe each one.
+ */
+ rspec = 0;
+- for_each_available_child_of_node(nprop, np)
+- if (of_device_is_compatible(np, "fsl,sec-v4.0-job-ring") ||
+- of_device_is_compatible(np, "fsl,sec4.0-job-ring"))
++ for_each_compatible_node(np, NULL, "fsl,sec-v4.0-job-ring")
++ rspec++;
++ if (!rspec) {
++ /* for backward compatible with device trees */
++ for_each_compatible_node(np, NULL, "fsl,sec4.0-job-ring")
+ rspec++;
++ }
+
+- ctrlpriv->jrpdev = devm_kzalloc(&pdev->dev,
+- sizeof(struct platform_device *) * rspec,
+- GFP_KERNEL);
+- if (ctrlpriv->jrpdev == NULL) {
+- iounmap(&ctrl);
++ ctrlpriv->jrdev = kzalloc(sizeof(struct device *) * rspec, GFP_KERNEL);
++ if (ctrlpriv->jrdev == NULL) {
++ iounmap(&topregs->ctrl);
+ return -ENOMEM;
+ }
+
+ ring = 0;
+ ctrlpriv->total_jobrs = 0;
+- for_each_available_child_of_node(nprop, np)
+- if (of_device_is_compatible(np, "fsl,sec-v4.0-job-ring") ||
+- of_device_is_compatible(np, "fsl,sec4.0-job-ring")) {
+- ctrlpriv->jrpdev[ring] =
+- of_platform_device_create(np, NULL, dev);
+- if (!ctrlpriv->jrpdev[ring]) {
+- pr_warn("JR%d Platform device creation error\n",
+- ring);
+- continue;
++ for_each_compatible_node(np, NULL, "fsl,sec-v4.0-job-ring") {
++ ret = caam_jr_probe(pdev, np, ring);
++ if (ret < 0) {
++ /*
++ * Job ring not found, error out. At some
++ * point, we should enhance job ring handling
++ * to allow for non-consecutive job rings to
++ * be found.
++ */
++ pr_err("fsl,sec-v4.0-job-ring not found ");
++ pr_err("(ring %d)\n", ring);
++ return ret;
++ }
++ ctrlpriv->total_jobrs++;
++ ring++;
++ }
++
++ if (!ring) {
++ for_each_compatible_node(np, NULL, "fsl,sec4.0-job-ring") {
++ ret = caam_jr_probe(pdev, np, ring);
++ if (ret < 0) {
++ /*
++ * Job ring not found, error out. At some
++ * point, we should enhance job ring handling
++ * to allow for non-consecutive job rings to
++ * be found.
++ */
++ pr_err("fsl,sec4.0-job-ring not found ");
++ pr_err("(ring %d)\n", ring);
++ return ret;
+ }
+- ctrlpriv->jr[ring] = (struct caam_job_ring __force *)
+- ((uint8_t *)ctrl +
+- (ring + JR_BLOCK_NUMBER) *
+- BLOCK_OFFSET
+- );
+ ctrlpriv->total_jobrs++;
+ ring++;
++ }
+ }
+
+ /* Check to see if QI present. If so, enable */
+- ctrlpriv->qi_present =
+- !!(rd_reg32(&ctrl->perfmon.comp_parms_ms) &
+- CTPR_MS_QI_MASK);
++ ctrlpriv->qi_present = !!(rd_reg64(&topregs->ctrl.perfmon.comp_parms) &
++ CTPR_QI_MASK);
+ if (ctrlpriv->qi_present) {
+- ctrlpriv->qi = (struct caam_queue_if __force *)
+- ((uint8_t *)ctrl +
+- BLOCK_OFFSET * QI_BLOCK_NUMBER
+- );
++ ctrlpriv->qi = (struct caam_queue_if __force *)&topregs->qi;
+ /* This is all that's required to physically enable QI */
+- wr_reg32(&ctrlpriv->qi->qi_control_lo, QICTL_DQEN);
++ wr_reg32(&topregs->qi.qi_control_lo, QICTL_DQEN);
+ }
+
+ /* If no QI and no rings specified, quit and go home */
+@@ -541,81 +467,53 @@
+ return -ENOMEM;
+ }
+
+- cha_vid_ls = rd_reg32(&ctrl->perfmon.cha_id_ls);
+-
+ /*
+- * If SEC has RNG version >= 4 and RNG state handle has not been
+- * already instantiated, do RNG instantiation
++ * RNG4 based SECs (v5+ | >= i.MX6) need special initialization prior
++ * to executing any descriptors. If there's a problem with init,
++ * remove other subsystems and return; internal padding functions
++ * cannot run without an RNG. This procedure assumes a single RNG4
++ * instance.
+ */
+- if ((cha_vid_ls & CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT >= 4) {
+- ctrlpriv->rng4_sh_init =
+- rd_reg32(&ctrl->r4tst[0].rdsta);
++ if ((rd_reg64(&topregs->ctrl.perfmon.cha_id) & CHA_ID_RNG_MASK)
++ == CHA_ID_RNG_4) {
++ struct rng4tst __iomem *r4tst;
++ u32 rdsta, rng_if, rng_skvn;
++
+ /*
+- * If the secure keys (TDKEK, JDKEK, TDSK), were already
+- * generated, signal this to the function that is instantiating
+- * the state handles. An error would occur if RNG4 attempts
+- * to regenerate these keys before the next POR.
++ * Check to see if the RNG has already been instantiated.
++ * If either the state 0 or 1 instantiated flags are set,
++ * then don't continue on and try to instantiate the RNG
++ * again.
+ */
+- gen_sk = ctrlpriv->rng4_sh_init & RDSTA_SKVN ? 0 : 1;
+- ctrlpriv->rng4_sh_init &= RDSTA_IFMASK;
+- do {
+- int inst_handles =
+- rd_reg32(&ctrl->r4tst[0].rdsta) &
+- RDSTA_IFMASK;
+- /*
+- * If either SH were instantiated by somebody else
+- * (e.g. u-boot) then it is assumed that the entropy
+- * parameters are properly set and thus the function
+- * setting these (kick_trng(...)) is skipped.
+- * Also, if a handle was instantiated, do not change
+- * the TRNG parameters.
+- */
+- if (!(ctrlpriv->rng4_sh_init || inst_handles)) {
+- dev_info(dev,
+- "Entropy delay = %u\n",
+- ent_delay);
+- kick_trng(pdev, ent_delay);
+- ent_delay += 400;
++ r4tst = &topregs->ctrl.r4tst[0];
++ rdsta = rd_reg32(&r4tst->rdsta); /* Read RDSTA register */
++
++ /* Check IF bit for non-deterministic instantiation */
++ rng_if = rdsta & RDSTA_IF;
++
++ /* Check SKVN bit for non-deterministic key generation */
++ rng_skvn = rdsta & RDSTA_SKVN;
++ if (!rng_if) {
++ kick_trng(pdev);
++ ret = instantiate_rng(ctrlpriv->jrdev[0], rng_skvn);
++ if (ret) {
++ caam_remove(pdev);
++ return -ENODEV;
+ }
+- /*
+- * if instantiate_rng(...) fails, the loop will rerun
+- * and the kick_trng(...) function will modfiy the
+- * upper and lower limits of the entropy sampling
+- * interval, leading to a sucessful initialization of
+- * the RNG.
+- */
+- ret = instantiate_rng(dev, inst_handles,
+- gen_sk);
+- if (ret == -EAGAIN)
+- /*
+- * if here, the loop will rerun,
+- * so don't hog the CPU
+- */
+- cpu_relax();
+- } while ((ret == -EAGAIN) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
+- if (ret) {
+- dev_err(dev, "failed to instantiate RNG");
+- caam_remove(pdev);
+- return ret;
++ ctrlpriv->rng_inst++;
+ }
+- /*
+- * Set handles init'ed by this module as the complement of the
+- * already initialized ones
+- */
+- ctrlpriv->rng4_sh_init = ~ctrlpriv->rng4_sh_init & RDSTA_IFMASK;
+-
+- /* Enable RDB bit so that RNG works faster */
+- setbits32(&ctrl->scfgr, SCFGR_RDBENABLE);
+ }
+
+ /* NOTE: RTIC detection ought to go here, around Si time */
+
+- caam_id = (u64)rd_reg32(&ctrl->perfmon.caam_id_ms) << 32 |
+- (u64)rd_reg32(&ctrl->perfmon.caam_id_ls);
++ /* Initialize queue allocator lock */
++ spin_lock_init(&ctrlpriv->jr_alloc_lock);
++
++ caam_id = rd_reg64(&topregs->ctrl.perfmon.caam_id);
+
+ /* Report "alive" for developer to see */
+ dev_info(dev, "device ID = 0x%016llx (Era %d)\n", caam_id,
+- caam_get_era());
++ caam_get_era(caam_id));
+ dev_info(dev, "job rings = %d, qi = %d\n",
+ ctrlpriv->total_jobrs, ctrlpriv->qi_present);
+
+@@ -627,7 +525,7 @@
+ */
+ perfmon = (struct caam_perfmon __force *)&ctrl->perfmon;
+
+- ctrlpriv->dfs_root = debugfs_create_dir(dev_name(dev), NULL);
++ ctrlpriv->dfs_root = debugfs_create_dir("caam", NULL);
+ ctrlpriv->ctl = debugfs_create_dir("ctl", ctrlpriv->dfs_root);
+
+ /* Controller-level - performance monitor counters */
+@@ -716,6 +614,7 @@
+ static struct platform_driver caam_driver = {
+ .driver = {
+ .name = "caam",
++ .owner = THIS_MODULE,
+ .of_match_table = caam_match,
+ },
+ .probe = caam_probe,
+diff -Nur linux-4.1.3/drivers/crypto/caam/ctrl.h linux-xbian-imx6/drivers/crypto/caam/ctrl.h
+--- linux-4.1.3/drivers/crypto/caam/ctrl.h 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/drivers/crypto/caam/ctrl.h 2015-07-27 23:13:04.209961631 +0200
+@@ -8,6 +8,6 @@
+ #define CTRL_H
+
+ /* Prototypes for backend-level services exposed to APIs */
+-int caam_get_era(void);
++int caam_get_era(u64 caam_id);
+
+ #endif /* CTRL_H */
+diff -Nur linux-4.1.3/drivers/crypto/caam/desc_constr.h linux-xbian-imx6/drivers/crypto/caam/desc_constr.h
+--- linux-4.1.3/drivers/crypto/caam/desc_constr.h 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/drivers/crypto/caam/desc_constr.h 2015-07-27 23:13:04.209961631 +0200
+@@ -10,7 +10,6 @@
+ #define CAAM_CMD_SZ sizeof(u32)
+ #define CAAM_PTR_SZ sizeof(dma_addr_t)
+ #define CAAM_DESC_BYTES_MAX (CAAM_CMD_SZ * MAX_CAAM_DESCSIZE)
+-#define DESC_JOB_IO_LEN (CAAM_CMD_SZ * 5 + CAAM_PTR_SZ * 3)
+
+ #ifdef DEBUG
+ #define PRINT_POS do { printk(KERN_DEBUG "%02d: %s\n", desc_len(desc),\
+@@ -111,26 +110,6 @@
+ (*desc)++;
+ }
+
+-#define append_u32 append_cmd
+-
+-static inline void append_u64(u32 *desc, u64 data)
+-{
+- u32 *offset = desc_end(desc);
+-
+- *offset = upper_32_bits(data);
+- *(++offset) = lower_32_bits(data);
+-
+- (*desc) += 2;
+-}
+-
+-/* Write command without affecting header, and return pointer to next word */
+-static inline u32 *write_cmd(u32 *desc, u32 command)
+-{
+- *desc = command;
+-
+- return desc + 1;
+-}
+-
+ static inline void append_cmd_ptr(u32 *desc, dma_addr_t ptr, int len,
+ u32 command)
+ {
+@@ -143,8 +122,7 @@
+ unsigned int len, u32 command)
+ {
+ append_cmd(desc, command);
+- if (!(command & (SQIN_RTO | SQIN_PRE)))
+- append_ptr(desc, ptr);
++ append_ptr(desc, ptr);
+ append_cmd(desc, len);
+ }
+
+@@ -155,29 +133,21 @@
+ append_data(desc, data, len);
+ }
+
+-#define APPEND_CMD_RET(cmd, op) \
+-static inline u32 *append_##cmd(u32 *desc, u32 options) \
+-{ \
+- u32 *cmd = desc_end(desc); \
+- PRINT_POS; \
+- append_cmd(desc, CMD_##op | options); \
+- return cmd; \
++static inline u32 *append_jump(u32 *desc, u32 options)
++{
++ u32 *cmd = desc_end(desc);
++
++ PRINT_POS;
++ append_cmd(desc, CMD_JUMP | options);
++
++ return cmd;
+ }
+-APPEND_CMD_RET(jump, JUMP)
+-APPEND_CMD_RET(move, MOVE)
+
+ static inline void set_jump_tgt_here(u32 *desc, u32 *jump_cmd)
+ {
+ *jump_cmd = *jump_cmd | (desc_len(desc) - (jump_cmd - desc));
+ }
+
+-static inline void set_move_tgt_here(u32 *desc, u32 *move_cmd)
+-{
+- *move_cmd &= ~MOVE_OFFSET_MASK;
+- *move_cmd = *move_cmd | ((desc_len(desc) << (MOVE_OFFSET_SHIFT + 2)) &
+- MOVE_OFFSET_MASK);
+-}
+-
+ #define APPEND_CMD(cmd, op) \
+ static inline void append_##cmd(u32 *desc, u32 options) \
+ { \
+@@ -185,6 +155,7 @@
+ append_cmd(desc, CMD_##op | options); \
+ }
+ APPEND_CMD(operation, OPERATION)
++APPEND_CMD(move, MOVE)
+
+ #define APPEND_CMD_LEN(cmd, op) \
+ static inline void append_##cmd(u32 *desc, unsigned int len, u32 options) \
+@@ -192,8 +163,6 @@
+ PRINT_POS; \
+ append_cmd(desc, CMD_##op | len | options); \
+ }
+-
+-APPEND_CMD_LEN(seq_load, SEQ_LOAD)
+ APPEND_CMD_LEN(seq_store, SEQ_STORE)
+ APPEND_CMD_LEN(seq_fifo_load, SEQ_FIFO_LOAD)
+ APPEND_CMD_LEN(seq_fifo_store, SEQ_FIFO_STORE)
+@@ -207,36 +176,17 @@
+ }
+ APPEND_CMD_PTR(key, KEY)
+ APPEND_CMD_PTR(load, LOAD)
++APPEND_CMD_PTR(store, STORE)
+ APPEND_CMD_PTR(fifo_load, FIFO_LOAD)
+ APPEND_CMD_PTR(fifo_store, FIFO_STORE)
+
+-static inline void append_store(u32 *desc, dma_addr_t ptr, unsigned int len,
+- u32 options)
+-{
+- u32 cmd_src;
+-
+- cmd_src = options & LDST_SRCDST_MASK;
+-
+- append_cmd(desc, CMD_STORE | options | len);
+-
+- /* The following options do not require pointer */
+- if (!(cmd_src == LDST_SRCDST_WORD_DESCBUF_SHARED ||
+- cmd_src == LDST_SRCDST_WORD_DESCBUF_JOB ||
+- cmd_src == LDST_SRCDST_WORD_DESCBUF_JOB_WE ||
+- cmd_src == LDST_SRCDST_WORD_DESCBUF_SHARED_WE))
+- append_ptr(desc, ptr);
+-}
+-
+ #define APPEND_SEQ_PTR_INTLEN(cmd, op) \
+ static inline void append_seq_##cmd##_ptr_intlen(u32 *desc, dma_addr_t ptr, \
+ unsigned int len, \
+ u32 options) \
+ { \
+ PRINT_POS; \
+- if (options & (SQIN_RTO | SQIN_PRE)) \
+- append_cmd(desc, CMD_SEQ_##op##_PTR | len | options); \
+- else \
+- append_cmd_ptr(desc, ptr, len, CMD_SEQ_##op##_PTR | options); \
++ append_cmd_ptr(desc, ptr, len, CMD_SEQ_##op##_PTR | options); \
+ }
+ APPEND_SEQ_PTR_INTLEN(in, IN)
+ APPEND_SEQ_PTR_INTLEN(out, OUT)
+@@ -309,7 +259,7 @@
+ */
+ #define APPEND_MATH(op, desc, dest, src_0, src_1, len) \
+ append_cmd(desc, CMD_MATH | MATH_FUN_##op | MATH_DEST_##dest | \
+- MATH_SRC0_##src_0 | MATH_SRC1_##src_1 | (u32)len);
++ MATH_SRC0_##src_0 | MATH_SRC1_##src_1 | (u32) (len & MATH_LEN_MASK));
+
+ #define append_math_add(desc, dest, src0, src1, len) \
+ APPEND_MATH(ADD, desc, dest, src0, src1, len)
+@@ -329,15 +279,13 @@
+ APPEND_MATH(LSHIFT, desc, dest, src0, src1, len)
+ #define append_math_rshift(desc, dest, src0, src1, len) \
+ APPEND_MATH(RSHIFT, desc, dest, src0, src1, len)
+-#define append_math_ldshift(desc, dest, src0, src1, len) \
+- APPEND_MATH(SHLD, desc, dest, src0, src1, len)
+
+ /* Exactly one source is IMM. Data is passed in as u32 value */
+ #define APPEND_MATH_IMM_u32(op, desc, dest, src_0, src_1, data) \
+ do { \
+ APPEND_MATH(op, desc, dest, src_0, src_1, CAAM_CMD_SZ); \
+ append_cmd(desc, data); \
+-} while (0)
++} while (0);
+
+ #define append_math_add_imm_u32(desc, dest, src0, src1, data) \
+ APPEND_MATH_IMM_u32(ADD, desc, dest, src0, src1, data)
+@@ -357,34 +305,3 @@
+ APPEND_MATH_IMM_u32(LSHIFT, desc, dest, src0, src1, data)
+ #define append_math_rshift_imm_u32(desc, dest, src0, src1, data) \
+ APPEND_MATH_IMM_u32(RSHIFT, desc, dest, src0, src1, data)
+-
+-/* Exactly one source is IMM. Data is passed in as u64 value */
+-#define APPEND_MATH_IMM_u64(op, desc, dest, src_0, src_1, data) \
+-do { \
+- u32 upper = (data >> 16) >> 16; \
+- APPEND_MATH(op, desc, dest, src_0, src_1, CAAM_CMD_SZ * 2 | \
+- (upper ? 0 : MATH_IFB)); \
+- if (upper) \
+- append_u64(desc, data); \
+- else \
+- append_u32(desc, data); \
+-} while (0)
+-
+-#define append_math_add_imm_u64(desc, dest, src0, src1, data) \
+- APPEND_MATH_IMM_u64(ADD, desc, dest, src0, src1, data)
+-#define append_math_sub_imm_u64(desc, dest, src0, src1, data) \
+- APPEND_MATH_IMM_u64(SUB, desc, dest, src0, src1, data)
+-#define append_math_add_c_imm_u64(desc, dest, src0, src1, data) \
+- APPEND_MATH_IMM_u64(ADDC, desc, dest, src0, src1, data)
+-#define append_math_sub_b_imm_u64(desc, dest, src0, src1, data) \
+- APPEND_MATH_IMM_u64(SUBB, desc, dest, src0, src1, data)
+-#define append_math_and_imm_u64(desc, dest, src0, src1, data) \
+- APPEND_MATH_IMM_u64(AND, desc, dest, src0, src1, data)
+-#define append_math_or_imm_u64(desc, dest, src0, src1, data) \
+- APPEND_MATH_IMM_u64(OR, desc, dest, src0, src1, data)
+-#define append_math_xor_imm_u64(desc, dest, src0, src1, data) \
+- APPEND_MATH_IMM_u64(XOR, desc, dest, src0, src1, data)
+-#define append_math_lshift_imm_u64(desc, dest, src0, src1, data) \
+- APPEND_MATH_IMM_u64(LSHIFT, desc, dest, src0, src1, data)
+-#define append_math_rshift_imm_u64(desc, dest, src0, src1, data) \
+- APPEND_MATH_IMM_u64(RSHIFT, desc, dest, src0, src1, data)
+diff -Nur linux-4.1.3/drivers/crypto/caam/desc.h linux-xbian-imx6/drivers/crypto/caam/desc.h
+--- linux-4.1.3/drivers/crypto/caam/desc.h 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/drivers/crypto/caam/desc.h 2015-07-27 23:13:04.209961631 +0200
+@@ -2,19 +2,35 @@
+ * CAAM descriptor composition header
+ * Definitions to support CAAM descriptor instruction generation
+ *
+- * Copyright 2008-2011 Freescale Semiconductor, Inc.
++ * Copyright (C) 2008-2013 Freescale Semiconductor, Inc.
+ */
+
+ #ifndef DESC_H
+ #define DESC_H
+
++/*
++ * 16-byte hardware scatter/gather table
++ * An 8-byte table exists in the hardware spec, but has never been
++ * implemented to date. The 8/16 option is selected at RTL-compile-time.
++ * and this selection is visible in the Compile Time Parameters Register
++ */
++
++#define SEC4_SG_LEN_EXT 0x80000000 /* Entry points to table */
++#define SEC4_SG_LEN_FIN 0x40000000 /* Last ent in table */
++#define SEC4_SG_BPID_MASK 0x000000ff
++#define SEC4_SG_BPID_SHIFT 16
++#define SEC4_SG_LEN_MASK 0x3fffffff /* Excludes EXT and FINAL */
++#define SEC4_SG_OFFS_MASK 0x00001fff
++
+ struct sec4_sg_entry {
++#ifdef CONFIG_64BIT
+ u64 ptr;
+-#define SEC4_SG_LEN_FIN 0x40000000
+-#define SEC4_SG_LEN_EXT 0x80000000
++#else
++ u32 reserved;
++ u32 ptr;
++#endif
+ u32 len;
+- u8 reserved;
+- u8 buf_pool_id;
++ u16 buf_pool_id;
+ u16 offset;
+ };
+
+@@ -231,12 +247,7 @@
+ #define LDST_SRCDST_WORD_PKHA_B_SZ (0x11 << LDST_SRCDST_SHIFT)
+ #define LDST_SRCDST_WORD_PKHA_N_SZ (0x12 << LDST_SRCDST_SHIFT)
+ #define LDST_SRCDST_WORD_PKHA_E_SZ (0x13 << LDST_SRCDST_SHIFT)
+-#define LDST_SRCDST_WORD_CLASS_CTX (0x20 << LDST_SRCDST_SHIFT)
+ #define LDST_SRCDST_WORD_DESCBUF (0x40 << LDST_SRCDST_SHIFT)
+-#define LDST_SRCDST_WORD_DESCBUF_JOB (0x41 << LDST_SRCDST_SHIFT)
+-#define LDST_SRCDST_WORD_DESCBUF_SHARED (0x42 << LDST_SRCDST_SHIFT)
+-#define LDST_SRCDST_WORD_DESCBUF_JOB_WE (0x45 << LDST_SRCDST_SHIFT)
+-#define LDST_SRCDST_WORD_DESCBUF_SHARED_WE (0x46 << LDST_SRCDST_SHIFT)
+ #define LDST_SRCDST_WORD_INFO_FIFO (0x7a << LDST_SRCDST_SHIFT)
+
+ /* Offset in source/destination */
+@@ -321,6 +332,7 @@
+ /* Continue - Not the last FIFO store to come */
+ #define FIFOST_CONT_SHIFT 23
+ #define FIFOST_CONT_MASK (1 << FIFOST_CONT_SHIFT)
++#define FIFOST_CONT_MASK (1 << FIFOST_CONT_SHIFT)
+
+ /*
+ * Extended Length - use 32-bit extended length that
+@@ -370,7 +382,6 @@
+ #define FIFOLD_TYPE_LAST2FLUSH1 (0x05 << FIFOLD_TYPE_SHIFT)
+ #define FIFOLD_TYPE_LASTBOTH (0x06 << FIFOLD_TYPE_SHIFT)
+ #define FIFOLD_TYPE_LASTBOTHFL (0x07 << FIFOLD_TYPE_SHIFT)
+-#define FIFOLD_TYPE_NOINFOFIFO (0x0F << FIFOLD_TYPE_SHIFT)
+
+ #define FIFOLDST_LEN_MASK 0xffff
+ #define FIFOLDST_EXT_LEN_MASK 0xffffffff
+@@ -1092,6 +1103,23 @@
+ #define OP_PCL_PKPROT_ECC 0x0002
+ #define OP_PCL_PKPROT_F2M 0x0001
+
++/* Blob protocol protinfo bits */
++#define OP_PCL_BLOB_TK 0x0200
++#define OP_PCL_BLOB_EKT 0x0100
++
++#define OP_PCL_BLOB_K2KR_MEM 0x0000
++#define OP_PCL_BLOB_K2KR_C1KR 0x0010
++#define OP_PCL_BLOB_K2KR_C2KR 0x0030
++#define OP_PCL_BLOB_K2KR_AFHAS 0x0050
++#define OP_PCL_BLOB_K2KR_C2KR_SPLIT 0x0070
++
++#define OP_PCL_BLOB_PTXT_SECMEM 0x0008
++#define OP_PCL_BLOB_BLACK 0x0004
++
++#define OP_PCL_BLOB_FMT_NORMAL 0x0000
++#define OP_PCL_BLOB_FMT_MSTR 0x0002
++#define OP_PCL_BLOB_FMT_TEST 0x0003
++
+ /* For non-protocol/alg-only op commands */
+ #define OP_ALG_TYPE_SHIFT 24
+ #define OP_ALG_TYPE_MASK (0x7 << OP_ALG_TYPE_SHIFT)
+@@ -1154,15 +1182,8 @@
+
+ /* randomizer AAI set */
+ #define OP_ALG_AAI_RNG (0x00 << OP_ALG_AAI_SHIFT)
+-#define OP_ALG_AAI_RNG_NZB (0x10 << OP_ALG_AAI_SHIFT)
+-#define OP_ALG_AAI_RNG_OBP (0x20 << OP_ALG_AAI_SHIFT)
+-
+-/* RNG4 AAI set */
+-#define OP_ALG_AAI_RNG4_SH_0 (0x00 << OP_ALG_AAI_SHIFT)
+-#define OP_ALG_AAI_RNG4_SH_1 (0x01 << OP_ALG_AAI_SHIFT)
+-#define OP_ALG_AAI_RNG4_PS (0x40 << OP_ALG_AAI_SHIFT)
+-#define OP_ALG_AAI_RNG4_AI (0x80 << OP_ALG_AAI_SHIFT)
+-#define OP_ALG_AAI_RNG4_SK (0x100 << OP_ALG_AAI_SHIFT)
++#define OP_ALG_AAI_RNG_NOZERO (0x10 << OP_ALG_AAI_SHIFT)
++#define OP_ALG_AAI_RNG_ODD (0x20 << OP_ALG_AAI_SHIFT)
+
+ /* hmac/smac AAI set */
+ #define OP_ALG_AAI_HASH (0x00 << OP_ALG_AAI_SHIFT)
+@@ -1184,6 +1205,12 @@
+ #define OP_ALG_AAI_GSM (0x10 << OP_ALG_AAI_SHIFT)
+ #define OP_ALG_AAI_EDGE (0x20 << OP_ALG_AAI_SHIFT)
+
++/* RNG4 set */
++#define OP_ALG_RNG4_SHIFT 4
++#define OP_ALG_RNG4_MASK (0x1f3 << OP_ALG_RNG4_SHIFT)
++
++#define OP_ALG_RNG4_SK (0x100 << OP_ALG_RNG4_SHIFT)
++
+ #define OP_ALG_AS_SHIFT 2
+ #define OP_ALG_AS_MASK (0x3 << OP_ALG_AS_SHIFT)
+ #define OP_ALG_AS_UPDATE (0 << OP_ALG_AS_SHIFT)
+@@ -1300,10 +1327,10 @@
+ #define SQOUT_SGF 0x01000000
+
+ /* Appends to a previous pointer */
+-#define SQOUT_PRE SQIN_PRE
++#define SQOUT_PRE 0x00800000
+
+ /* Restore sequence with pointer/length */
+-#define SQOUT_RTO SQIN_RTO
++#define SQOUT_RTO 0x00200000
+
+ /* Use extended length following pointer */
+ #define SQOUT_EXT 0x00400000
+@@ -1365,7 +1392,6 @@
+ #define MOVE_DEST_MATH3 (0x07 << MOVE_DEST_SHIFT)
+ #define MOVE_DEST_CLASS1INFIFO (0x08 << MOVE_DEST_SHIFT)
+ #define MOVE_DEST_CLASS2INFIFO (0x09 << MOVE_DEST_SHIFT)
+-#define MOVE_DEST_INFIFO_NOINFO (0x0a << MOVE_DEST_SHIFT)
+ #define MOVE_DEST_PK_A (0x0c << MOVE_DEST_SHIFT)
+ #define MOVE_DEST_CLASS1KEY (0x0d << MOVE_DEST_SHIFT)
+ #define MOVE_DEST_CLASS2KEY (0x0e << MOVE_DEST_SHIFT)
+@@ -1418,7 +1444,6 @@
+ #define MATH_SRC0_REG2 (0x02 << MATH_SRC0_SHIFT)
+ #define MATH_SRC0_REG3 (0x03 << MATH_SRC0_SHIFT)
+ #define MATH_SRC0_IMM (0x04 << MATH_SRC0_SHIFT)
+-#define MATH_SRC0_DPOVRD (0x07 << MATH_SRC0_SHIFT)
+ #define MATH_SRC0_SEQINLEN (0x08 << MATH_SRC0_SHIFT)
+ #define MATH_SRC0_SEQOUTLEN (0x09 << MATH_SRC0_SHIFT)
+ #define MATH_SRC0_VARSEQINLEN (0x0a << MATH_SRC0_SHIFT)
+@@ -1433,7 +1458,6 @@
+ #define MATH_SRC1_REG2 (0x02 << MATH_SRC1_SHIFT)
+ #define MATH_SRC1_REG3 (0x03 << MATH_SRC1_SHIFT)
+ #define MATH_SRC1_IMM (0x04 << MATH_SRC1_SHIFT)
+-#define MATH_SRC1_DPOVRD (0x07 << MATH_SRC0_SHIFT)
+ #define MATH_SRC1_INFIFO (0x0a << MATH_SRC1_SHIFT)
+ #define MATH_SRC1_OUTFIFO (0x0b << MATH_SRC1_SHIFT)
+ #define MATH_SRC1_ONE (0x0c << MATH_SRC1_SHIFT)
+@@ -1609,13 +1633,28 @@
+ #define NFIFOENTRY_PLEN_SHIFT 0
+ #define NFIFOENTRY_PLEN_MASK (0xFF << NFIFOENTRY_PLEN_SHIFT)
+
+-/* Append Load Immediate Command */
+-#define FD_CMD_APPEND_LOAD_IMMEDIATE 0x80000000
++/*
++ * PDB internal definitions
++ */
++
++/* IPSec ESP CBC Encap/Decap Options */
++#define PDBOPTS_ESPCBC_ARSNONE 0x00 /* no antireplay window */
++#define PDBOPTS_ESPCBC_ARS32 0x40 /* 32-entry antireplay window */
++#define PDBOPTS_ESPCBC_ARS64 0xc0 /* 64-entry antireplay window */
++#define PDBOPTS_ESPCBC_IVSRC 0x20 /* IV comes from internal random gen */
++#define PDBOPTS_ESPCBC_ESN 0x10 /* extended sequence included */
++#define PDBOPTS_ESPCBC_OUTFMT 0x08 /* output only decapsulation (decap) */
++#define PDBOPTS_ESPCBC_IPHDRSRC 0x08 /* IP header comes from PDB (encap) */
++#define PDBOPTS_ESPCBC_INCIPHDR 0x04 /* Prepend IP header to output frame */
++#define PDBOPTS_ESPCBC_IPVSN 0x02 /* process IPv6 header */
++#define PDBOPTS_ESPCBC_TUNNEL 0x01 /* tunnel mode next-header byte */
++
++#define ARC4_BLOCK_SIZE 1
++#define ARC4_MAX_KEY_SIZE 256
++#define ARC4_MIN_KEY_SIZE 1
+
+-/* Set SEQ LIODN equal to the Non-SEQ LIODN for the job */
+-#define FD_CMD_SET_SEQ_LIODN_EQUAL_NONSEQ_LIODN 0x40000000
++#define XCBC_MAC_DIGEST_SIZE 16
++#define XCBC_MAC_BLOCK_WORDS 16
+
+-/* Frame Descriptor Command for Replacement Job Descriptor */
+-#define FD_CMD_REPLACE_JOB_DESC 0x20000000
+
+ #endif /* DESC_H */
+diff -Nur linux-4.1.3/drivers/crypto/caam/error.c linux-xbian-imx6/drivers/crypto/caam/error.c
+--- linux-4.1.3/drivers/crypto/caam/error.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/drivers/crypto/caam/error.c 2015-07-27 23:13:04.213947410 +0200
+@@ -11,243 +11,264 @@
+ #include "jr.h"
+ #include "error.h"
+
+-static const struct {
+- u8 value;
+- const char *error_text;
+-} desc_error_list[] = {
+- { 0x00, "No error." },
+- { 0x01, "SGT Length Error. The descriptor is trying to read more data than is contained in the SGT table." },
+- { 0x02, "SGT Null Entry Error." },
+- { 0x03, "Job Ring Control Error. There is a bad value in the Job Ring Control register." },
+- { 0x04, "Invalid Descriptor Command. The Descriptor Command field is invalid." },
+- { 0x05, "Reserved." },
+- { 0x06, "Invalid KEY Command" },
+- { 0x07, "Invalid LOAD Command" },
+- { 0x08, "Invalid STORE Command" },
+- { 0x09, "Invalid OPERATION Command" },
+- { 0x0A, "Invalid FIFO LOAD Command" },
+- { 0x0B, "Invalid FIFO STORE Command" },
+- { 0x0C, "Invalid MOVE/MOVE_LEN Command" },
+- { 0x0D, "Invalid JUMP Command. A nonlocal JUMP Command is invalid because the target is not a Job Header Command, or the jump is from a Trusted Descriptor to a Job Descriptor, or because the target Descriptor contains a Shared Descriptor." },
+- { 0x0E, "Invalid MATH Command" },
+- { 0x0F, "Invalid SIGNATURE Command" },
+- { 0x10, "Invalid Sequence Command. A SEQ IN PTR OR SEQ OUT PTR Command is invalid or a SEQ KEY, SEQ LOAD, SEQ FIFO LOAD, or SEQ FIFO STORE decremented the input or output sequence length below 0. This error may result if a built-in PROTOCOL Command has encountered a malformed PDU." },
+- { 0x11, "Skip data type invalid. The type must be 0xE or 0xF."},
+- { 0x12, "Shared Descriptor Header Error" },
+- { 0x13, "Header Error. Invalid length or parity, or certain other problems." },
+- { 0x14, "Burster Error. Burster has gotten to an illegal state" },
+- { 0x15, "Context Register Length Error. The descriptor is trying to read or write past the end of the Context Register. A SEQ LOAD or SEQ STORE with the VLF bit set was executed with too large a length in the variable length register (VSOL for SEQ STORE or VSIL for SEQ LOAD)." },
+- { 0x16, "DMA Error" },
+- { 0x17, "Reserved." },
+- { 0x1A, "Job failed due to JR reset" },
+- { 0x1B, "Job failed due to Fail Mode" },
+- { 0x1C, "DECO Watchdog timer timeout error" },
+- { 0x1D, "DECO tried to copy a key from another DECO but the other DECO's Key Registers were locked" },
+- { 0x1E, "DECO attempted to copy data from a DECO that had an unmasked Descriptor error" },
+- { 0x1F, "LIODN error. DECO was trying to share from itself or from another DECO but the two Non-SEQ LIODN values didn't match or the 'shared from' DECO's Descriptor required that the SEQ LIODNs be the same and they aren't." },
+- { 0x20, "DECO has completed a reset initiated via the DRR register" },
+- { 0x21, "Nonce error. When using EKT (CCM) key encryption option in the FIFO STORE Command, the Nonce counter reached its maximum value and this encryption mode can no longer be used." },
+- { 0x22, "Meta data is too large (> 511 bytes) for TLS decap (input frame; block ciphers) and IPsec decap (output frame, when doing the next header byte update) and DCRC (output frame)." },
+- { 0x23, "Read Input Frame error" },
+- { 0x24, "JDKEK, TDKEK or TDSK not loaded error" },
+- { 0x80, "DNR (do not run) error" },
+- { 0x81, "undefined protocol command" },
+- { 0x82, "invalid setting in PDB" },
+- { 0x83, "Anti-replay LATE error" },
+- { 0x84, "Anti-replay REPLAY error" },
+- { 0x85, "Sequence number overflow" },
+- { 0x86, "Sigver invalid signature" },
+- { 0x87, "DSA Sign Illegal test descriptor" },
+- { 0x88, "Protocol Format Error - A protocol has seen an error in the format of data received. When running RSA, this means that formatting with random padding was used, and did not follow the form: 0x00, 0x02, 8-to-N bytes of non-zero pad, 0x00, F data." },
+- { 0x89, "Protocol Size Error - A protocol has seen an error in size. When running RSA, pdb size N < (size of F) when no formatting is used; or pdb size N < (F + 11) when formatting is used." },
+- { 0xC1, "Blob Command error: Undefined mode" },
+- { 0xC2, "Blob Command error: Secure Memory Blob mode error" },
+- { 0xC4, "Blob Command error: Black Blob key or input size error" },
+- { 0xC5, "Blob Command error: Invalid key destination" },
+- { 0xC8, "Blob Command error: Trusted/Secure mode error" },
+- { 0xF0, "IPsec TTL or hop limit field either came in as 0, or was decremented to 0" },
+- { 0xF1, "3GPP HFN matches or exceeds the Threshold" },
+-};
+-
+-static const char * const cha_id_list[] = {
+- "",
+- "AES",
+- "DES",
+- "ARC4",
+- "MDHA",
+- "RNG",
+- "SNOW f8",
+- "Kasumi f8/9",
+- "PKHA",
+- "CRCA",
+- "SNOW f9",
+- "ZUCE",
+- "ZUCA",
+-};
+-
+-static const char * const err_id_list[] = {
+- "No error.",
+- "Mode error.",
+- "Data size error.",
+- "Key size error.",
+- "PKHA A memory size error.",
+- "PKHA B memory size error.",
+- "Data arrived out of sequence error.",
+- "PKHA divide-by-zero error.",
+- "PKHA modulus even error.",
+- "DES key parity error.",
+- "ICV check failed.",
+- "Hardware error.",
+- "Unsupported CCM AAD size.",
+- "Class 1 CHA is not reset",
+- "Invalid CHA combination was selected",
+- "Invalid CHA selected.",
+-};
+-
+-static const char * const rng_err_id_list[] = {
+- "",
+- "",
+- "",
+- "Instantiate",
+- "Not instantiated",
+- "Test instantiate",
+- "Prediction resistance",
+- "Prediction resistance and test request",
+- "Uninstantiate",
+- "Secure key generation",
+-};
++#define SPRINTFCAT(str, format, param, max_alloc) \
++{ \
++ char *tmp; \
++ \
++ tmp = kmalloc(sizeof(format) + max_alloc, GFP_ATOMIC); \
++ if (likely(tmp)) { \
++ sprintf(tmp, format, param); \
++ strcat(str, tmp); \
++ kfree(tmp); \
++ } else { \
++ strcat(str, "kmalloc failure in SPRINTFCAT"); \
++ } \
++}
+
+-static void report_ccb_status(struct device *jrdev, const u32 status,
+- const char *error)
++static void report_jump_idx(u32 status, char *outstr)
+ {
+- u8 cha_id = (status & JRSTA_CCBERR_CHAID_MASK) >>
+- JRSTA_CCBERR_CHAID_SHIFT;
+- u8 err_id = status & JRSTA_CCBERR_ERRID_MASK;
+ u8 idx = (status & JRSTA_DECOERR_INDEX_MASK) >>
+ JRSTA_DECOERR_INDEX_SHIFT;
+- char *idx_str;
+- const char *cha_str = "unidentified cha_id value 0x";
+- char cha_err_code[3] = { 0 };
+- const char *err_str = "unidentified err_id value 0x";
+- char err_err_code[3] = { 0 };
+
+ if (status & JRSTA_DECOERR_JUMP)
+- idx_str = "jump tgt desc idx";
++ strcat(outstr, "jump tgt desc idx ");
+ else
+- idx_str = "desc idx";
++ strcat(outstr, "desc idx ");
+
+- if (cha_id < ARRAY_SIZE(cha_id_list))
+- cha_str = cha_id_list[cha_id];
+- else
+- snprintf(cha_err_code, sizeof(cha_err_code), "%02x", cha_id);
++ SPRINTFCAT(outstr, "%d: ", idx, sizeof("255"));
++}
++
++static void report_ccb_status(u32 status, char *outstr)
++{
++ static const char * const cha_id_list[] = {
++ "",
++ "AES",
++ "DES",
++ "ARC4",
++ "MDHA",
++ "RNG",
++ "SNOW f8",
++ "Kasumi f8/9",
++ "PKHA",
++ "CRCA",
++ "SNOW f9",
++ "ZUCE",
++ "ZUCA",
++ };
++ static const char * const err_id_list[] = {
++ "No error.",
++ "Mode error.",
++ "Data size error.",
++ "Key size error.",
++ "PKHA A memory size error.",
++ "PKHA B memory size error.",
++ "Data arrived out of sequence error.",
++ "PKHA divide-by-zero error.",
++ "PKHA modulus even error.",
++ "DES key parity error.",
++ "ICV check failed.",
++ "Hardware error.",
++ "Unsupported CCM AAD size.",
++ "Class 1 CHA is not reset",
++ "Invalid CHA combination was selected",
++ "Invalid CHA selected.",
++ };
++ static const char * const rng_err_id_list[] = {
++ "",
++ "",
++ "",
++ "Instantiate",
++ "Not instantiated",
++ "Test instantiate",
++ "Prediction resistance",
++ "Prediction resistance and test request",
++ "Uninstantiate",
++ "Secure key generation",
++ };
++ u8 cha_id = (status & JRSTA_CCBERR_CHAID_MASK) >>
++ JRSTA_CCBERR_CHAID_SHIFT;
++ u8 err_id = status & JRSTA_CCBERR_ERRID_MASK;
++
++ report_jump_idx(status, outstr);
++
++ if (cha_id < ARRAY_SIZE(cha_id_list)) {
++ SPRINTFCAT(outstr, "%s: ", cha_id_list[cha_id],
++ strlen(cha_id_list[cha_id]));
++ } else {
++ SPRINTFCAT(outstr, "unidentified cha_id value 0x%02x: ",
++ cha_id, sizeof("ff"));
++ }
+
+ if ((cha_id << JRSTA_CCBERR_CHAID_SHIFT) == JRSTA_CCBERR_CHAID_RNG &&
+ err_id < ARRAY_SIZE(rng_err_id_list) &&
+ strlen(rng_err_id_list[err_id])) {
+ /* RNG-only error */
+- err_str = rng_err_id_list[err_id];
+- } else if (err_id < ARRAY_SIZE(err_id_list))
+- err_str = err_id_list[err_id];
+- else
+- snprintf(err_err_code, sizeof(err_err_code), "%02x", err_id);
+-
+- /*
+- * CCB ICV check failures are part of normal operation life;
+- * we leave the upper layers to do what they want with them.
+- */
+- if (err_id != JRSTA_CCBERR_ERRID_ICVCHK)
+- dev_err(jrdev, "%08x: %s: %s %d: %s%s: %s%s\n",
+- status, error, idx_str, idx,
+- cha_str, cha_err_code,
+- err_str, err_err_code);
++ SPRINTFCAT(outstr, "%s", rng_err_id_list[err_id],
++ strlen(rng_err_id_list[err_id]));
++ } else if (err_id < ARRAY_SIZE(err_id_list)) {
++ SPRINTFCAT(outstr, "%s", err_id_list[err_id],
++ strlen(err_id_list[err_id]));
++ } else {
++ SPRINTFCAT(outstr, "unidentified err_id value 0x%02x",
++ err_id, sizeof("ff"));
++ }
+ }
+
+-static void report_jump_status(struct device *jrdev, const u32 status,
+- const char *error)
++static void report_jump_status(u32 status, char *outstr)
+ {
+- dev_err(jrdev, "%08x: %s: %s() not implemented\n",
+- status, error, __func__);
++ SPRINTFCAT(outstr, "%s() not implemented", __func__, sizeof(__func__));
+ }
+
+-static void report_deco_status(struct device *jrdev, const u32 status,
+- const char *error)
++static void report_deco_status(u32 status, char *outstr)
+ {
+- u8 err_id = status & JRSTA_DECOERR_ERROR_MASK;
+- u8 idx = (status & JRSTA_DECOERR_INDEX_MASK) >>
+- JRSTA_DECOERR_INDEX_SHIFT;
+- char *idx_str;
+- const char *err_str = "unidentified error value 0x";
+- char err_err_code[3] = { 0 };
++ static const struct {
++ u8 value;
++ char *error_text;
++ } desc_error_list[] = {
++ { 0x00, "No error." },
++ { 0x01, "SGT Length Error. The descriptor is trying to read "
++ "more data than is contained in the SGT table." },
++ { 0x02, "SGT Null Entry Error." },
++ { 0x03, "Job Ring Control Error. There is a bad value in the "
++ "Job Ring Control register." },
++ { 0x04, "Invalid Descriptor Command. The Descriptor Command "
++ "field is invalid." },
++ { 0x05, "Reserved." },
++ { 0x06, "Invalid KEY Command" },
++ { 0x07, "Invalid LOAD Command" },
++ { 0x08, "Invalid STORE Command" },
++ { 0x09, "Invalid OPERATION Command" },
++ { 0x0A, "Invalid FIFO LOAD Command" },
++ { 0x0B, "Invalid FIFO STORE Command" },
++ { 0x0C, "Invalid MOVE/MOVE_LEN Command" },
++ { 0x0D, "Invalid JUMP Command. A nonlocal JUMP Command is "
++ "invalid because the target is not a Job Header "
++ "Command, or the jump is from a Trusted Descriptor to "
++ "a Job Descriptor, or because the target Descriptor "
++ "contains a Shared Descriptor." },
++ { 0x0E, "Invalid MATH Command" },
++ { 0x0F, "Invalid SIGNATURE Command" },
++ { 0x10, "Invalid Sequence Command. A SEQ IN PTR OR SEQ OUT PTR "
++ "Command is invalid or a SEQ KEY, SEQ LOAD, SEQ FIFO "
++ "LOAD, or SEQ FIFO STORE decremented the input or "
++ "output sequence length below 0. This error may result "
++ "if a built-in PROTOCOL Command has encountered a "
++ "malformed PDU." },
++ { 0x11, "Skip data type invalid. The type must be 0xE or 0xF."},
++ { 0x12, "Shared Descriptor Header Error" },
++ { 0x13, "Header Error. Invalid length or parity, or certain "
++ "other problems." },
++ { 0x14, "Burster Error. Burster has gotten to an illegal "
++ "state" },
++ { 0x15, "Context Register Length Error. The descriptor is "
++ "trying to read or write past the end of the Context "
++ "Register. A SEQ LOAD or SEQ STORE with the VLF bit "
++ "set was executed with too large a length in the "
++ "variable length register (VSOL for SEQ STORE or VSIL "
++ "for SEQ LOAD)." },
++ { 0x16, "DMA Error" },
++ { 0x17, "Reserved." },
++ { 0x1A, "Job failed due to JR reset" },
++ { 0x1B, "Job failed due to Fail Mode" },
++ { 0x1C, "DECO Watchdog timer timeout error" },
++ { 0x1D, "DECO tried to copy a key from another DECO but the "
++ "other DECO's Key Registers were locked" },
++ { 0x1E, "DECO attempted to copy data from a DECO that had an "
++ "unmasked Descriptor error" },
++ { 0x1F, "LIODN error. DECO was trying to share from itself or "
++ "from another DECO but the two Non-SEQ LIODN values "
++ "didn't match or the 'shared from' DECO's Descriptor "
++ "required that the SEQ LIODNs be the same and they "
++ "aren't." },
++ { 0x20, "DECO has completed a reset initiated via the DRR "
++ "register" },
++ { 0x21, "Nonce error. When using EKT (CCM) key encryption "
++ "option in the FIFO STORE Command, the Nonce counter "
++ "reached its maximum value and this encryption mode "
++ "can no longer be used." },
++ { 0x22, "Meta data is too large (> 511 bytes) for TLS decap "
++ "(input frame; block ciphers) and IPsec decap (output "
++ "frame, when doing the next header byte update) and "
++ "DCRC (output frame)." },
++ { 0x23, "Read Input Frame error" },
++ { 0x24, "JDKEK, TDKEK or TDSK not loaded error" },
++ { 0x80, "DNR (do not run) error" },
++ { 0x81, "undefined protocol command" },
++ { 0x82, "invalid setting in PDB" },
++ { 0x83, "Anti-replay LATE error" },
++ { 0x84, "Anti-replay REPLAY error" },
++ { 0x85, "Sequence number overflow" },
++ { 0x86, "Sigver invalid signature" },
++ { 0x87, "DSA Sign Illegal test descriptor" },
++ { 0x88, "Protocol Format Error - A protocol has seen an error "
++ "in the format of data received. When running RSA, "
++ "this means that formatting with random padding was "
++ "used, and did not follow the form: 0x00, 0x02, 8-to-N "
++ "bytes of non-zero pad, 0x00, F data." },
++ { 0x89, "Protocol Size Error - A protocol has seen an error in "
++ "size. When running RSA, pdb size N < (size of F) when "
++ "no formatting is used; or pdb size N < (F + 11) when "
++ "formatting is used." },
++ { 0xC1, "Blob Command error: Undefined mode" },
++ { 0xC2, "Blob Command error: Secure Memory Blob mode error" },
++ { 0xC4, "Blob Command error: Black Blob key or input size "
++ "error" },
++ { 0xC5, "Blob Command error: Invalid key destination" },
++ { 0xC8, "Blob Command error: Trusted/Secure mode error" },
++ { 0xF0, "IPsec TTL or hop limit field either came in as 0, "
++ "or was decremented to 0" },
++ { 0xF1, "3GPP HFN matches or exceeds the Threshold" },
++ };
++ u8 desc_error = status & JRSTA_DECOERR_ERROR_MASK;
+ int i;
+
+- if (status & JRSTA_DECOERR_JUMP)
+- idx_str = "jump tgt desc idx";
+- else
+- idx_str = "desc idx";
++ report_jump_idx(status, outstr);
+
+ for (i = 0; i < ARRAY_SIZE(desc_error_list); i++)
+- if (desc_error_list[i].value == err_id)
++ if (desc_error_list[i].value == desc_error)
+ break;
+
+- if (i != ARRAY_SIZE(desc_error_list) && desc_error_list[i].error_text)
+- err_str = desc_error_list[i].error_text;
+- else
+- snprintf(err_err_code, sizeof(err_err_code), "%02x", err_id);
+-
+- dev_err(jrdev, "%08x: %s: %s %d: %s%s\n",
+- status, error, idx_str, idx, err_str, err_err_code);
++ if (i != ARRAY_SIZE(desc_error_list) && desc_error_list[i].error_text) {
++ SPRINTFCAT(outstr, "%s", desc_error_list[i].error_text,
++ strlen(desc_error_list[i].error_text));
++ } else {
++ SPRINTFCAT(outstr, "unidentified error value 0x%02x",
++ desc_error, sizeof("ff"));
++ }
+ }
+
+-static void report_jr_status(struct device *jrdev, const u32 status,
+- const char *error)
++static void report_jr_status(u32 status, char *outstr)
+ {
+- dev_err(jrdev, "%08x: %s: %s() not implemented\n",
+- status, error, __func__);
++ SPRINTFCAT(outstr, "%s() not implemented", __func__, sizeof(__func__));
+ }
+
+-static void report_cond_code_status(struct device *jrdev, const u32 status,
+- const char *error)
++static void report_cond_code_status(u32 status, char *outstr)
+ {
+- dev_err(jrdev, "%08x: %s: %s() not implemented\n",
+- status, error, __func__);
++ SPRINTFCAT(outstr, "%s() not implemented", __func__, sizeof(__func__));
+ }
+
+-void caam_jr_strstatus(struct device *jrdev, u32 status)
++char *caam_jr_strstatus(char *outstr, u32 status)
+ {
+ static const struct stat_src {
+- void (*report_ssed)(struct device *jrdev, const u32 status,
+- const char *error);
+- const char *error;
+- } status_src[16] = {
++ void (*report_ssed)(u32 status, char *outstr);
++ char *error;
++ } status_src[] = {
+ { NULL, "No error" },
+ { NULL, NULL },
+ { report_ccb_status, "CCB" },
+ { report_jump_status, "Jump" },
+ { report_deco_status, "DECO" },
+- { NULL, "Queue Manager Interface" },
++ { NULL, NULL },
+ { report_jr_status, "Job Ring" },
+ { report_cond_code_status, "Condition Code" },
+- { NULL, NULL },
+- { NULL, NULL },
+- { NULL, NULL },
+- { NULL, NULL },
+- { NULL, NULL },
+- { NULL, NULL },
+- { NULL, NULL },
+- { NULL, NULL },
+ };
+ u32 ssrc = status >> JRSTA_SSRC_SHIFT;
+- const char *error = status_src[ssrc].error;
+
+- /*
+- * If there is an error handling function, call it to report the error.
+- * Otherwise print the error source name.
+- */
++ sprintf(outstr, "%s: ", status_src[ssrc].error);
++
+ if (status_src[ssrc].report_ssed)
+- status_src[ssrc].report_ssed(jrdev, status, error);
+- else if (error)
+- dev_err(jrdev, "%d: %s\n", ssrc, error);
+- else
+- dev_err(jrdev, "%d: unknown error source\n", ssrc);
++ status_src[ssrc].report_ssed(status, outstr);
++
++ return outstr;
+ }
+ EXPORT_SYMBOL(caam_jr_strstatus);
+diff -Nur linux-4.1.3/drivers/crypto/caam/error.h linux-xbian-imx6/drivers/crypto/caam/error.h
+--- linux-4.1.3/drivers/crypto/caam/error.h 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/drivers/crypto/caam/error.h 2015-07-27 23:13:04.213947410 +0200
+@@ -7,5 +7,5 @@
+ #ifndef CAAM_ERROR_H
+ #define CAAM_ERROR_H
+ #define CAAM_ERROR_STR_MAX 302
+-void caam_jr_strstatus(struct device *jrdev, u32 status);
++extern char *caam_jr_strstatus(char *outstr, u32 status);
+ #endif /* CAAM_ERROR_H */
+diff -Nur linux-4.1.3/drivers/crypto/caam/intern.h linux-xbian-imx6/drivers/crypto/caam/intern.h
+--- linux-4.1.3/drivers/crypto/caam/intern.h 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/drivers/crypto/caam/intern.h 2015-07-27 23:13:04.213947410 +0200
+@@ -2,13 +2,19 @@
+ * CAAM/SEC 4.x driver backend
+ * Private/internal definitions between modules
+ *
+- * Copyright 2008-2011 Freescale Semiconductor, Inc.
++ * Copyright (C) 2008-2013 Freescale Semiconductor, Inc.
+ *
+ */
+
+ #ifndef INTERN_H
+ #define INTERN_H
+
++#define JOBR_UNASSIGNED 0
++#define JOBR_ASSIGNED 1
++
++/* Default clock/sample settings for an RNG4 entropy source */
++#define RNG4_ENT_CLOCKS_SAMPLE 1600
++
+ /* Currently comes from Kconfig param as a ^2 (driver-required) */
+ #define JOBR_DEPTH (1 << CONFIG_CRYPTO_DEV_FSL_CAAM_RINGSIZE)
+
+@@ -37,15 +43,13 @@
+
+ /* Private sub-storage for a single JobR */
+ struct caam_drv_private_jr {
+- struct list_head list_node; /* Job Ring device list */
+- struct device *dev;
++ struct device *parentdev; /* points back to controller dev */
++ struct platform_device *jr_pdev;/* points to platform device for JR */
+ int ridx;
+ struct caam_job_ring __iomem *rregs; /* JobR's register space */
+ struct tasklet_struct irqtask;
+ int irq; /* One per queue */
+-
+- /* Number of scatterlist crypt transforms active on the JobR */
+- atomic_t tfm_count ____cacheline_aligned;
++ int assign; /* busy/free */
+
+ /* Job ring info */
+ int ringsize; /* Size of rings (assume input = output) */
+@@ -66,15 +70,20 @@
+ struct caam_drv_private {
+
+ struct device *dev;
+- struct platform_device **jrpdev; /* Alloc'ed array per sub-device */
++ struct device *smdev;
++ struct device *secviodev;
++ struct device **jrdev; /* Alloc'ed array per sub-device */
++ spinlock_t jr_alloc_lock;
+ struct platform_device *pdev;
+
+ /* Physical-presence section */
+- struct caam_ctrl __iomem *ctrl; /* controller region */
+- struct caam_deco __iomem *deco; /* DECO/CCB views */
+- struct caam_assurance __iomem *assure;
+- struct caam_queue_if __iomem *qi; /* QI control region */
+- struct caam_job_ring __iomem *jr[4]; /* JobR's register space */
++ struct caam_ctrl *ctrl; /* controller region */
++ struct caam_deco **deco; /* DECO/CCB views */
++ struct caam_assurance *ac;
++ struct caam_queue_if *qi; /* QI control region */
++ struct snvs_full __iomem *snvs; /* SNVS HP+LP register space */
++ dma_addr_t __iomem *sm_base; /* Secure memory storage base */
++ u32 sm_size;
+
+ /*
+ * Detected geometry block. Filled in from device tree if powerpc,
+@@ -83,14 +92,22 @@
+ u8 total_jobrs; /* Total Job Rings in device */
+ u8 qi_present; /* Nonzero if QI present in device */
+ int secvio_irq; /* Security violation interrupt number */
+- int virt_en; /* Virtualization enabled in CAAM */
+-
+-#define RNG4_MAX_HANDLES 2
+- /* RNG4 block */
+- u32 rng4_sh_init; /* This bitmap shows which of the State
+- Handles of the RNG4 block are initialized
+- by this driver */
++ int rng_inst; /* Total instantiated RNGs */
+
++ /* which jr allocated to scatterlist crypto */
++ atomic_t tfm_count ____cacheline_aligned;
++ int num_jrs_for_algapi;
++ struct device **algapi_jr;
++ /* list of registered crypto algorithms (mk generic context handle?) */
++ struct list_head alg_list;
++ /* list of registered hash algorithms (mk generic context handle?) */
++ struct list_head hash_list;
++
++#ifdef CONFIG_ARM
++ struct clk *caam_ipg;
++ struct clk *caam_mem;
++ struct clk *caam_aclk;
++#endif
+ /*
+ * debugfs entries for developer view into driver/device
+ * variables at runtime.
+diff -Nur linux-4.1.3/drivers/crypto/caam/jr.c linux-xbian-imx6/drivers/crypto/caam/jr.c
+--- linux-4.1.3/drivers/crypto/caam/jr.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/drivers/crypto/caam/jr.c 2015-07-27 23:13:04.213947410 +0200
+@@ -2,125 +2,15 @@
+ * CAAM/SEC 4.x transport/backend driver
+ * JobR backend functionality
+ *
+- * Copyright 2008-2012 Freescale Semiconductor, Inc.
++ * Copyright (C) 2008-2013 Freescale Semiconductor, Inc.
+ */
+
+-#include <linux/of_irq.h>
+-#include <linux/of_address.h>
+-
+ #include "compat.h"
+ #include "regs.h"
+ #include "jr.h"
+ #include "desc.h"
+ #include "intern.h"
+
+-struct jr_driver_data {
+- /* List of Physical JobR's with the Driver */
+- struct list_head jr_list;
+- spinlock_t jr_alloc_lock; /* jr_list lock */
+-} ____cacheline_aligned;
+-
+-static struct jr_driver_data driver_data;
+-
+-static int caam_reset_hw_jr(struct device *dev)
+-{
+- struct caam_drv_private_jr *jrp = dev_get_drvdata(dev);
+- unsigned int timeout = 100000;
+-
+- /*
+- * mask interrupts since we are going to poll
+- * for reset completion status
+- */
+- setbits32(&jrp->rregs->rconfig_lo, JRCFG_IMSK);
+-
+- /* initiate flush (required prior to reset) */
+- wr_reg32(&jrp->rregs->jrcommand, JRCR_RESET);
+- while (((rd_reg32(&jrp->rregs->jrintstatus) & JRINT_ERR_HALT_MASK) ==
+- JRINT_ERR_HALT_INPROGRESS) && --timeout)
+- cpu_relax();
+-
+- if ((rd_reg32(&jrp->rregs->jrintstatus) & JRINT_ERR_HALT_MASK) !=
+- JRINT_ERR_HALT_COMPLETE || timeout == 0) {
+- dev_err(dev, "failed to flush job ring %d\n", jrp->ridx);
+- return -EIO;
+- }
+-
+- /* initiate reset */
+- timeout = 100000;
+- wr_reg32(&jrp->rregs->jrcommand, JRCR_RESET);
+- while ((rd_reg32(&jrp->rregs->jrcommand) & JRCR_RESET) && --timeout)
+- cpu_relax();
+-
+- if (timeout == 0) {
+- dev_err(dev, "failed to reset job ring %d\n", jrp->ridx);
+- return -EIO;
+- }
+-
+- /* unmask interrupts */
+- clrbits32(&jrp->rregs->rconfig_lo, JRCFG_IMSK);
+-
+- return 0;
+-}
+-
+-/*
+- * Shutdown JobR independent of platform property code
+- */
+-int caam_jr_shutdown(struct device *dev)
+-{
+- struct caam_drv_private_jr *jrp = dev_get_drvdata(dev);
+- dma_addr_t inpbusaddr, outbusaddr;
+- int ret;
+-
+- ret = caam_reset_hw_jr(dev);
+-
+- tasklet_kill(&jrp->irqtask);
+-
+- /* Release interrupt */
+- free_irq(jrp->irq, dev);
+-
+- /* Free rings */
+- inpbusaddr = rd_reg64(&jrp->rregs->inpring_base);
+- outbusaddr = rd_reg64(&jrp->rregs->outring_base);
+- dma_free_coherent(dev, sizeof(dma_addr_t) * JOBR_DEPTH,
+- jrp->inpring, inpbusaddr);
+- dma_free_coherent(dev, sizeof(struct jr_outentry) * JOBR_DEPTH,
+- jrp->outring, outbusaddr);
+- kfree(jrp->entinfo);
+-
+- return ret;
+-}
+-
+-static int caam_jr_remove(struct platform_device *pdev)
+-{
+- int ret;
+- struct device *jrdev;
+- struct caam_drv_private_jr *jrpriv;
+-
+- jrdev = &pdev->dev;
+- jrpriv = dev_get_drvdata(jrdev);
+-
+- /*
+- * Return EBUSY if job ring already allocated.
+- */
+- if (atomic_read(&jrpriv->tfm_count)) {
+- dev_err(jrdev, "Device is busy\n");
+- return -EBUSY;
+- }
+-
+- /* Remove the node from Physical JobR list maintained by driver */
+- spin_lock(&driver_data.jr_alloc_lock);
+- list_del(&jrpriv->list_node);
+- spin_unlock(&driver_data.jr_alloc_lock);
+-
+- /* Release ring */
+- ret = caam_jr_shutdown(jrdev);
+- if (ret)
+- dev_err(jrdev, "Failed to shut down job ring\n");
+- irq_dispose_mapping(jrpriv->irq);
+-
+- return ret;
+-}
+-
+ /* Main per-ring interrupt handler */
+ static irqreturn_t caam_jr_interrupt(int irq, void *st_dev)
+ {
+@@ -168,6 +58,9 @@
+ void (*usercall)(struct device *dev, u32 *desc, u32 status, void *arg);
+ u32 *userdesc, userstatus;
+ void *userarg;
++ dma_addr_t outbusaddr;
++
++ outbusaddr = rd_reg64(&jrp->rregs->outring_base);
+
+ while (rd_reg32(&jrp->rregs->outring_used)) {
+
+@@ -177,10 +70,15 @@
+
+ sw_idx = tail = jrp->tail;
+ hw_idx = jrp->out_ring_read_index;
++ dma_sync_single_for_cpu(dev, outbusaddr,
++ sizeof(struct jr_outentry) * JOBR_DEPTH,
++ DMA_FROM_DEVICE);
+
+ for (i = 0; CIRC_CNT(head, tail + i, JOBR_DEPTH) >= 1; i++) {
+ sw_idx = (tail + i) & (JOBR_DEPTH - 1);
+
++ smp_read_barrier_depends();
++
+ if (jrp->outring[hw_idx].desc ==
+ jrp->entinfo[sw_idx].desc_addr_dma)
+ break; /* found */
+@@ -202,6 +100,8 @@
+ userdesc = jrp->entinfo[sw_idx].desc_addr_virt;
+ userstatus = jrp->outring[hw_idx].jrstatus;
+
++ smp_mb();
++
+ /* set done */
+ wr_reg32(&jrp->rregs->outring_rmvd, 1);
+
+@@ -216,6 +116,7 @@
+ if (sw_idx == tail) {
+ do {
+ tail = (tail + 1) & (JOBR_DEPTH - 1);
++ smp_read_barrier_depends();
+ } while (CIRC_CNT(head, tail, JOBR_DEPTH) >= 1 &&
+ jrp->entinfo[tail].desc_addr_dma == 0);
+
+@@ -233,57 +134,70 @@
+ }
+
+ /**
+- * caam_jr_alloc() - Alloc a job ring for someone to use as needed.
+- *
+- * returns : pointer to the newly allocated physical
+- * JobR dev can be written to if successful.
++ * caam_jr_register() - Alloc a ring for someone to use as needed. Returns
++ * an ordinal of the rings allocated, else returns -ENODEV if no rings
++ * are available.
++ * @ctrldev: points to the controller level dev (parent) that
++ * owns rings available for use.
++ * @dev: points to where a pointer to the newly allocated queue's
++ * dev can be written to if successful.
+ **/
+-struct device *caam_jr_alloc(void)
++int caam_jr_register(struct device *ctrldev, struct device **rdev)
+ {
+- struct caam_drv_private_jr *jrpriv, *min_jrpriv = NULL;
+- struct device *dev = NULL;
+- int min_tfm_cnt = INT_MAX;
+- int tfm_cnt;
+-
+- spin_lock(&driver_data.jr_alloc_lock);
+-
+- if (list_empty(&driver_data.jr_list)) {
+- spin_unlock(&driver_data.jr_alloc_lock);
+- return ERR_PTR(-ENODEV);
+- }
+-
+- list_for_each_entry(jrpriv, &driver_data.jr_list, list_node) {
+- tfm_cnt = atomic_read(&jrpriv->tfm_count);
+- if (tfm_cnt < min_tfm_cnt) {
+- min_tfm_cnt = tfm_cnt;
+- min_jrpriv = jrpriv;
++ struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
++ struct caam_drv_private_jr *jrpriv = NULL;
++ int ring;
++
++ /* Lock, if free ring - assign, unlock */
++ spin_lock(&ctrlpriv->jr_alloc_lock);
++ for (ring = 0; ring < ctrlpriv->total_jobrs; ring++) {
++ jrpriv = dev_get_drvdata(ctrlpriv->jrdev[ring]);
++ if (jrpriv->assign == JOBR_UNASSIGNED) {
++ jrpriv->assign = JOBR_ASSIGNED;
++ *rdev = ctrlpriv->jrdev[ring];
++ spin_unlock(&ctrlpriv->jr_alloc_lock);
++ return ring;
+ }
+- if (!min_tfm_cnt)
+- break;
+ }
+
+- if (min_jrpriv) {
+- atomic_inc(&min_jrpriv->tfm_count);
+- dev = min_jrpriv->dev;
+- }
+- spin_unlock(&driver_data.jr_alloc_lock);
++ /* If assigned, write dev where caller needs it */
++ spin_unlock(&ctrlpriv->jr_alloc_lock);
++ *rdev = NULL;
+
+- return dev;
++ return -ENODEV;
+ }
+-EXPORT_SYMBOL(caam_jr_alloc);
++EXPORT_SYMBOL(caam_jr_register);
+
+ /**
+- * caam_jr_free() - Free the Job Ring
+- * @rdev - points to the dev that identifies the Job ring to
+- * be released.
++ * caam_jr_deregister() - Deregister an API and release the queue.
++ * Returns 0 if OK, -EBUSY if queue still contains pending entries
++ * or unprocessed results at the time of the call
++ * @dev - points to the dev that identifies the queue to
++ * be released.
+ **/
+-void caam_jr_free(struct device *rdev)
++int caam_jr_deregister(struct device *rdev)
+ {
+ struct caam_drv_private_jr *jrpriv = dev_get_drvdata(rdev);
++ struct caam_drv_private *ctrlpriv;
++
++ /* Get the owning controller's private space */
++ ctrlpriv = dev_get_drvdata(jrpriv->parentdev);
++
++ /*
++ * Make sure ring empty before release
++ */
++ if (rd_reg32(&jrpriv->rregs->outring_used) ||
++ (rd_reg32(&jrpriv->rregs->inpring_avail) != JOBR_DEPTH))
++ return -EBUSY;
+
+- atomic_dec(&jrpriv->tfm_count);
++ /* Release ring */
++ spin_lock(&ctrlpriv->jr_alloc_lock);
++ jrpriv->assign = JOBR_UNASSIGNED;
++ spin_unlock(&ctrlpriv->jr_alloc_lock);
++
++ return 0;
+ }
+-EXPORT_SYMBOL(caam_jr_free);
++EXPORT_SYMBOL(caam_jr_deregister);
+
+ /**
+ * caam_jr_enqueue() - Enqueue a job descriptor head. Returns 0 if OK,
+@@ -321,7 +235,7 @@
+ struct caam_drv_private_jr *jrp = dev_get_drvdata(dev);
+ struct caam_jrentry_info *head_entry;
+ int head, tail, desc_size;
+- dma_addr_t desc_dma;
++ dma_addr_t desc_dma, inpbusaddr;
+
+ desc_size = (*desc & HDR_JD_LENGTH_MASK) * sizeof(u32);
+ desc_dma = dma_map_single(dev, desc, desc_size, DMA_TO_DEVICE);
+@@ -330,6 +244,13 @@
+ return -EIO;
+ }
+
++ dma_sync_single_for_device(dev, desc_dma, desc_size, DMA_TO_DEVICE);
++
++ inpbusaddr = rd_reg64(&jrp->rregs->inpring_base);
++ dma_sync_single_for_device(dev, inpbusaddr,
++ sizeof(dma_addr_t) * JOBR_DEPTH,
++ DMA_TO_DEVICE);
++
+ spin_lock_bh(&jrp->inplock);
+
+ head = jrp->head;
+@@ -351,12 +272,18 @@
+
+ jrp->inpring[jrp->inp_ring_write_index] = desc_dma;
+
++ dma_sync_single_for_device(dev, inpbusaddr,
++ sizeof(dma_addr_t) * JOBR_DEPTH,
++ DMA_TO_DEVICE);
++
+ smp_wmb();
+
+ jrp->inp_ring_write_index = (jrp->inp_ring_write_index + 1) &
+ (JOBR_DEPTH - 1);
+ jrp->head = (head + 1) & (JOBR_DEPTH - 1);
+
++ wmb();
++
+ wr_reg32(&jrp->rregs->inpring_jobadd, 1);
+
+ spin_unlock_bh(&jrp->inplock);
+@@ -365,6 +292,46 @@
+ }
+ EXPORT_SYMBOL(caam_jr_enqueue);
+
++static int caam_reset_hw_jr(struct device *dev)
++{
++ struct caam_drv_private_jr *jrp = dev_get_drvdata(dev);
++ unsigned int timeout = 100000;
++
++ /*
++ * mask interrupts since we are going to poll
++ * for reset completion status
++ */
++ setbits32(&jrp->rregs->rconfig_lo, JRCFG_IMSK);
++
++ /* initiate flush (required prior to reset) */
++ wr_reg32(&jrp->rregs->jrcommand, JRCR_RESET);
++ while (((rd_reg32(&jrp->rregs->jrintstatus) & JRINT_ERR_HALT_MASK) ==
++ JRINT_ERR_HALT_INPROGRESS) && --timeout)
++ cpu_relax();
++
++ if ((rd_reg32(&jrp->rregs->jrintstatus) & JRINT_ERR_HALT_MASK) !=
++ JRINT_ERR_HALT_COMPLETE || timeout == 0) {
++ dev_err(dev, "failed to flush job ring %d\n", jrp->ridx);
++ return -EIO;
++ }
++
++ /* initiate reset */
++ timeout = 100000;
++ wr_reg32(&jrp->rregs->jrcommand, JRCR_RESET);
++ while ((rd_reg32(&jrp->rregs->jrcommand) & JRCR_RESET) && --timeout)
++ cpu_relax();
++
++ if (timeout == 0) {
++ dev_err(dev, "failed to reset job ring %d\n", jrp->ridx);
++ return -EIO;
++ }
++
++ /* unmask interrupts */
++ clrbits32(&jrp->rregs->rconfig_lo, JRCFG_IMSK);
++
++ return 0;
++}
++
+ /*
+ * Init JobR independent of platform property detection
+ */
+@@ -380,32 +347,34 @@
+
+ /* Connect job ring interrupt handler. */
+ error = request_irq(jrp->irq, caam_jr_interrupt, IRQF_SHARED,
+- dev_name(dev), dev);
++ "caam-jobr", dev);
+ if (error) {
+ dev_err(dev, "can't connect JobR %d interrupt (%d)\n",
+ jrp->ridx, jrp->irq);
+- goto out_kill_deq;
++ irq_dispose_mapping(jrp->irq);
++ jrp->irq = 0;
++ return -EINVAL;
+ }
+
+ error = caam_reset_hw_jr(dev);
+ if (error)
+- goto out_free_irq;
++ return error;
+
+- error = -ENOMEM;
+ jrp->inpring = dma_alloc_coherent(dev, sizeof(dma_addr_t) * JOBR_DEPTH,
+ &inpbusaddr, GFP_KERNEL);
+- if (!jrp->inpring)
+- goto out_free_irq;
+
+ jrp->outring = dma_alloc_coherent(dev, sizeof(struct jr_outentry) *
+ JOBR_DEPTH, &outbusaddr, GFP_KERNEL);
+- if (!jrp->outring)
+- goto out_free_inpring;
+
+ jrp->entinfo = kzalloc(sizeof(struct caam_jrentry_info) * JOBR_DEPTH,
+ GFP_KERNEL);
+- if (!jrp->entinfo)
+- goto out_free_outring;
++
++ if ((jrp->inpring == NULL) || (jrp->outring == NULL) ||
++ (jrp->entinfo == NULL)) {
++ dev_err(dev, "can't allocate job rings for %d\n",
++ jrp->ridx);
++ return -ENOMEM;
++ }
+
+ for (i = 0; i < JOBR_DEPTH; i++)
+ jrp->entinfo[i].desc_addr_dma = !0;
+@@ -431,120 +400,123 @@
+ (JOBR_INTC_COUNT_THLD << JRCFG_ICDCT_SHIFT) |
+ (JOBR_INTC_TIME_THLD << JRCFG_ICTT_SHIFT));
+
++ jrp->assign = JOBR_UNASSIGNED;
+ return 0;
++}
+
+-out_free_outring:
+- dma_free_coherent(dev, sizeof(struct jr_outentry) * JOBR_DEPTH,
+- jrp->outring, outbusaddr);
+-out_free_inpring:
++/*
++ * Shutdown JobR independent of platform property code
++ */
++int caam_jr_shutdown(struct device *dev)
++{
++ struct caam_drv_private_jr *jrp = dev_get_drvdata(dev);
++ dma_addr_t inpbusaddr, outbusaddr;
++ int ret;
++
++ ret = caam_reset_hw_jr(dev);
++
++ tasklet_kill(&jrp->irqtask);
++
++ /* Release interrupt */
++ free_irq(jrp->irq, dev);
++
++ /* Free rings */
++ inpbusaddr = rd_reg64(&jrp->rregs->inpring_base);
++ outbusaddr = rd_reg64(&jrp->rregs->outring_base);
+ dma_free_coherent(dev, sizeof(dma_addr_t) * JOBR_DEPTH,
+ jrp->inpring, inpbusaddr);
+- dev_err(dev, "can't allocate job rings for %d\n", jrp->ridx);
+-out_free_irq:
+- free_irq(jrp->irq, dev);
+-out_kill_deq:
+- tasklet_kill(&jrp->irqtask);
+- return error;
+-}
++ dma_free_coherent(dev, sizeof(struct jr_outentry) * JOBR_DEPTH,
++ jrp->outring, outbusaddr);
++ kfree(jrp->entinfo);
++ of_device_unregister(jrp->jr_pdev);
+
++ return ret;
++}
+
+ /*
+- * Probe routine for each detected JobR subsystem.
++ * Probe routine for each detected JobR subsystem. It assumes that
++ * property detection was picked up externally.
+ */
+-static int caam_jr_probe(struct platform_device *pdev)
++int caam_jr_probe(struct platform_device *pdev, struct device_node *np,
++ int ring)
+ {
+- struct device *jrdev;
+- struct device_node *nprop;
+- struct caam_job_ring __iomem *ctrl;
++ struct device *ctrldev, *jrdev;
++ struct platform_device *jr_pdev;
++ struct caam_drv_private *ctrlpriv;
+ struct caam_drv_private_jr *jrpriv;
+- static int total_jobrs;
++ const __be32 *jroffset_addr;
++ u32 jroffset;
+ int error;
+
+- jrdev = &pdev->dev;
+- jrpriv = devm_kmalloc(jrdev, sizeof(struct caam_drv_private_jr),
+- GFP_KERNEL);
+- if (!jrpriv)
++ ctrldev = &pdev->dev;
++ ctrlpriv = dev_get_drvdata(ctrldev);
++
++ jrpriv = kmalloc(sizeof(struct caam_drv_private_jr),
++ GFP_KERNEL);
++ if (jrpriv == NULL) {
++ dev_err(ctrldev, "can't alloc private mem for job ring %d\n",
++ ring);
+ return -ENOMEM;
++ }
++ jrpriv->parentdev = ctrldev; /* point back to parent */
++ jrpriv->ridx = ring; /* save ring identity relative to detection */
+
+- dev_set_drvdata(jrdev, jrpriv);
++ /*
++ * Derive a pointer to the detected JobRs regs
++ * Driver has already iomapped the entire space, we just
++ * need to add in the offset to this JobR. Don't know if I
++ * like this long-term, but it'll run
++ */
++ jroffset_addr = of_get_property(np, "reg", NULL);
+
+- /* save ring identity relative to detection */
+- jrpriv->ridx = total_jobrs++;
++ if (jroffset_addr == NULL) {
++ kfree(jrpriv);
++ return -EINVAL;
++ }
+
+- nprop = pdev->dev.of_node;
+- /* Get configuration properties from device tree */
+- /* First, get register page */
+- ctrl = of_iomap(nprop, 0);
+- if (!ctrl) {
+- dev_err(jrdev, "of_iomap() failed\n");
+- return -ENOMEM;
++ /*
++ * Fix the endianness of this value read from the device
++ * tree if running on ARM.
++ */
++ jroffset = be32_to_cpup(jroffset_addr);
++
++ jrpriv->rregs = (struct caam_job_ring __iomem *)((void *)ctrlpriv->ctrl
++ + jroffset);
++
++ /* Build a local dev for each detected queue */
++ jr_pdev = of_platform_device_create(np, NULL, ctrldev);
++ if (jr_pdev == NULL) {
++ kfree(jrpriv);
++ return -EINVAL;
+ }
+
+- jrpriv->rregs = (struct caam_job_ring __force *)ctrl;
++ jrpriv->jr_pdev = jr_pdev;
++ jrdev = &jr_pdev->dev;
++ dev_set_drvdata(jrdev, jrpriv);
++ ctrlpriv->jrdev[ring] = jrdev;
+
+ if (sizeof(dma_addr_t) == sizeof(u64))
+- if (of_device_is_compatible(nprop, "fsl,sec-v5.0-job-ring"))
+- dma_set_mask_and_coherent(jrdev, DMA_BIT_MASK(40));
++ if (of_device_is_compatible(np, "fsl,sec-v4.0-job-ring"))
++ dma_set_mask(jrdev, DMA_BIT_MASK(40));
+ else
+- dma_set_mask_and_coherent(jrdev, DMA_BIT_MASK(36));
++ dma_set_mask(jrdev, DMA_BIT_MASK(36));
+ else
+- dma_set_mask_and_coherent(jrdev, DMA_BIT_MASK(32));
++ dma_set_mask(jrdev, DMA_BIT_MASK(32));
+
+ /* Identify the interrupt */
+- jrpriv->irq = irq_of_parse_and_map(nprop, 0);
++ jrpriv->irq = of_irq_to_resource(np, 0, NULL);
++ if (jrpriv->irq <= 0) {
++ kfree(jrpriv);
++ return -EINVAL;
++ }
+
+ /* Now do the platform independent part */
+ error = caam_jr_init(jrdev); /* now turn on hardware */
+ if (error) {
+- irq_dispose_mapping(jrpriv->irq);
++ of_device_unregister(jr_pdev);
++ kfree(jrpriv);
+ return error;
+ }
+
+- jrpriv->dev = jrdev;
+- spin_lock(&driver_data.jr_alloc_lock);
+- list_add_tail(&jrpriv->list_node, &driver_data.jr_list);
+- spin_unlock(&driver_data.jr_alloc_lock);
+-
+- atomic_set(&jrpriv->tfm_count, 0);
+-
+- return 0;
+-}
+-
+-static struct of_device_id caam_jr_match[] = {
+- {
+- .compatible = "fsl,sec-v4.0-job-ring",
+- },
+- {
+- .compatible = "fsl,sec4.0-job-ring",
+- },
+- {},
+-};
+-MODULE_DEVICE_TABLE(of, caam_jr_match);
+-
+-static struct platform_driver caam_jr_driver = {
+- .driver = {
+- .name = "caam_jr",
+- .of_match_table = caam_jr_match,
+- },
+- .probe = caam_jr_probe,
+- .remove = caam_jr_remove,
+-};
+-
+-static int __init jr_driver_init(void)
+-{
+- spin_lock_init(&driver_data.jr_alloc_lock);
+- INIT_LIST_HEAD(&driver_data.jr_list);
+- return platform_driver_register(&caam_jr_driver);
+-}
+-
+-static void __exit jr_driver_exit(void)
+-{
+- platform_driver_unregister(&caam_jr_driver);
++ return error;
+ }
+-
+-module_init(jr_driver_init);
+-module_exit(jr_driver_exit);
+-
+-MODULE_LICENSE("GPL");
+-MODULE_DESCRIPTION("FSL CAAM JR request backend");
+-MODULE_AUTHOR("Freescale Semiconductor - NMG/STC");
+diff -Nur linux-4.1.3/drivers/crypto/caam/jr.h linux-xbian-imx6/drivers/crypto/caam/jr.h
+--- linux-4.1.3/drivers/crypto/caam/jr.h 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/drivers/crypto/caam/jr.h 2015-07-27 23:13:04.213947410 +0200
+@@ -1,18 +1,22 @@
+ /*
+ * CAAM public-level include definitions for the JobR backend
+ *
+- * Copyright 2008-2011 Freescale Semiconductor, Inc.
++ * Copyright (C) 2008-2013 Freescale Semiconductor, Inc.
+ */
+
+ #ifndef JR_H
+ #define JR_H
+
+ /* Prototypes for backend-level services exposed to APIs */
+-struct device *caam_jr_alloc(void);
+-void caam_jr_free(struct device *rdev);
++int caam_jr_register(struct device *ctrldev, struct device **rdev);
++int caam_jr_deregister(struct device *rdev);
+ int caam_jr_enqueue(struct device *dev, u32 *desc,
+ void (*cbk)(struct device *dev, u32 *desc, u32 status,
+ void *areq),
+ void *areq);
+
++extern int caam_jr_probe(struct platform_device *pdev, struct device_node *np,
++ int ring);
++extern int caam_jr_shutdown(struct device *dev);
++extern struct device *caam_get_jrdev(void);
+ #endif /* JR_H */
+diff -Nur linux-4.1.3/drivers/crypto/caam/Kconfig linux-xbian-imx6/drivers/crypto/caam/Kconfig
+--- linux-4.1.3/drivers/crypto/caam/Kconfig 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/drivers/crypto/caam/Kconfig 2015-07-27 23:13:04.205975852 +0200
+@@ -1,32 +1,19 @@
+ config CRYPTO_DEV_FSL_CAAM
+ tristate "Freescale CAAM-Multicore driver backend"
+- depends on FSL_SOC
++ depends on FSL_SOC || ARCH_MXC
+ help
+ Enables the driver module for Freescale's Cryptographic Accelerator
+ and Assurance Module (CAAM), also known as the SEC version 4 (SEC4).
+- This module creates job ring devices, and configures h/w
++ This module adds a job ring operation interface, and configures h/w
+ to operate as a DPAA component automatically, depending
+ on h/w feature availability.
+
+ To compile this driver as a module, choose M here: the module
+ will be called caam.
+
+-config CRYPTO_DEV_FSL_CAAM_JR
+- tristate "Freescale CAAM Job Ring driver backend"
+- depends on CRYPTO_DEV_FSL_CAAM
+- default y
+- help
+- Enables the driver module for Job Rings which are part of
+- Freescale's Cryptographic Accelerator
+- and Assurance Module (CAAM). This module adds a job ring operation
+- interface.
+-
+- To compile this driver as a module, choose M here: the module
+- will be called caam_jr.
+-
+ config CRYPTO_DEV_FSL_CAAM_RINGSIZE
+ int "Job Ring size"
+- depends on CRYPTO_DEV_FSL_CAAM_JR
++ depends on CRYPTO_DEV_FSL_CAAM
+ range 2 9
+ default "9"
+ help
+@@ -44,7 +31,7 @@
+
+ config CRYPTO_DEV_FSL_CAAM_INTC
+ bool "Job Ring interrupt coalescing"
+- depends on CRYPTO_DEV_FSL_CAAM_JR
++ depends on CRYPTO_DEV_FSL_CAAM
+ default n
+ help
+ Enable the Job Ring's interrupt coalescing feature.
+@@ -75,7 +62,7 @@
+
+ config CRYPTO_DEV_FSL_CAAM_CRYPTO_API
+ tristate "Register algorithm implementations with the Crypto API"
+- depends on CRYPTO_DEV_FSL_CAAM && CRYPTO_DEV_FSL_CAAM_JR
++ depends on CRYPTO_DEV_FSL_CAAM
+ default y
+ select CRYPTO_ALGAPI
+ select CRYPTO_AUTHENC
+@@ -89,7 +76,7 @@
+
+ config CRYPTO_DEV_FSL_CAAM_AHASH_API
+ tristate "Register hash algorithm implementations with Crypto API"
+- depends on CRYPTO_DEV_FSL_CAAM && CRYPTO_DEV_FSL_CAAM_JR
++ depends on CRYPTO_DEV_FSL_CAAM
+ default y
+ select CRYPTO_HASH
+ help
+@@ -101,7 +88,7 @@
+
+ config CRYPTO_DEV_FSL_CAAM_RNG_API
+ tristate "Register caam device for hwrng API"
+- depends on CRYPTO_DEV_FSL_CAAM && CRYPTO_DEV_FSL_CAAM_JR
++ depends on CRYPTO_DEV_FSL_CAAM
+ default y
+ select CRYPTO_RNG
+ select HW_RANDOM
+@@ -112,6 +99,54 @@
+ To compile this as a module, choose M here: the module
+ will be called caamrng.
+
++config CRYPTO_DEV_FSL_CAAM_RNG_TEST
++ boolean "Test caam rng"
++ depends on CRYPTO_DEV_FSL_CAAM_RNG_API
++ default n
++ help
++ Selecting this will enable self-test for caam rng.
++
++config CRYPTO_DEV_FSL_CAAM_SM
++ tristate "CAAM Secure Memory / Keystore API (EXPERIMENTAL)"
++ default n
++ help
++ Enables use of a prototype kernel-level Keystore API with CAAM
++ Secure Memory for insertion/extraction of bus-protected secrets.
++
++config CRYPTO_DEV_FSL_CAAM_SM_SLOTSIZE
++ int "Size of each keystore slot in Secure Memory"
++ depends on CRYPTO_DEV_FSL_CAAM_SM
++ range 5 9
++ default 7
++ help
++ Select size of allocation units to divide Secure Memory pages into
++ (the size of a "slot" as referenced inside the API code).
++ Established as powers of two.
++ Examples:
++ 5 => 32 bytes
++ 6 => 64 bytes
++ 7 => 128 bytes
++ 8 => 256 bytes
++ 9 => 512 bytes
++
++config CRYPTO_DEV_FSL_CAAM_SM_TEST
++ tristate "CAAM Secure Memory - Keystore Test/Example (EXPERIMENTAL)"
++ depends on CRYPTO_DEV_FSL_CAAM_SM
++ default n
++ help
++ Example thread to exercise the Keystore API and to verify that
++ stored and recovered secrets can be used for general purpose
++ encryption/decryption.
++
++config CRYPTO_DEV_FSL_CAAM_SECVIO
++ tristate "CAAM/SNVS Security Violation Handler (EXPERIMENTAL)"
++ depends on CRYPTO_DEV_FSL_CAAM
++ default n
++ help
++ Enables installation of an interrupt handler with registrable
++ handler functions which can be specified to act on the consequences
++ of a security violation.
++
+ config CRYPTO_DEV_FSL_CAAM_DEBUG
+ bool "Enable debug output in CAAM driver"
+ depends on CRYPTO_DEV_FSL_CAAM
+@@ -119,3 +154,19 @@
+ help
+ Selecting this will enable printing of various debug
+ information in the CAAM driver.
++
++config CRYPTO_DEV_FSL_CAAM_KEYBLOB
++ tristate "Freescale CAAM memory keyblob driver backend"
++ depends on CRYPTO_DEV_FSL_CAAM
++ depends on CRYPTO_DEV_FSL_CAAM_JR
++ default y
++ help
++ Enables the driver module for Key Blob which are part of
++ Freescale's Cryptographic Accelerator
++ and Assurance Module (CAAM). This module adds a key blob operation
++ interface.
++
++ To compile this driver as a module, choose M here: the module
++ will be called caam_keyblob.
++
++
+diff -Nur linux-4.1.3/drivers/crypto/caam/key_gen.c linux-xbian-imx6/drivers/crypto/caam/key_gen.c
+--- linux-4.1.3/drivers/crypto/caam/key_gen.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/drivers/crypto/caam/key_gen.c 2015-07-27 23:13:04.213947410 +0200
+@@ -1,7 +1,7 @@
+ /*
+ * CAAM/SEC 4.x functions for handling key-generation jobs
+ *
+- * Copyright 2008-2011 Freescale Semiconductor, Inc.
++ * Copyright (C) 2008-2013 Freescale Semiconductor, Inc.
+ *
+ */
+ #include "compat.h"
+@@ -19,8 +19,11 @@
+ dev_err(dev, "%s %d: err 0x%x\n", __func__, __LINE__, err);
+ #endif
+
+- if (err)
+- caam_jr_strstatus(dev, err);
++ if (err) {
++ char tmp[CAAM_ERROR_STR_MAX];
++
++ dev_err(dev, "%08x: %s\n", err, caam_jr_strstatus(tmp, err));
++ }
+
+ res->err = err;
+
+@@ -48,29 +51,24 @@
+ u32 *desc;
+ struct split_key_result result;
+ dma_addr_t dma_addr_in, dma_addr_out;
+- int ret = -ENOMEM;
++ int ret = 0;
+
+ desc = kmalloc(CAAM_CMD_SZ * 6 + CAAM_PTR_SZ * 2, GFP_KERNEL | GFP_DMA);
+ if (!desc) {
+ dev_err(jrdev, "unable to allocate key input memory\n");
+- return ret;
++ return -ENOMEM;
+ }
+
++ init_job_desc(desc, 0);
++
+ dma_addr_in = dma_map_single(jrdev, (void *)key_in, keylen,
+ DMA_TO_DEVICE);
+ if (dma_mapping_error(jrdev, dma_addr_in)) {
+ dev_err(jrdev, "unable to map key input memory\n");
+- goto out_free;
++ kfree(desc);
++ return -ENOMEM;
+ }
+-
+- dma_addr_out = dma_map_single(jrdev, key_out, split_key_pad_len,
+- DMA_FROM_DEVICE);
+- if (dma_mapping_error(jrdev, dma_addr_out)) {
+- dev_err(jrdev, "unable to map key output memory\n");
+- goto out_unmap_in;
+- }
+-
+- init_job_desc(desc, 0);
++ dma_sync_single_for_device(jrdev, dma_addr_in, keylen, DMA_TO_DEVICE);
+ append_key(desc, dma_addr_in, keylen, CLASS_2 | KEY_DEST_CLASS_REG);
+
+ /* Sets MDHA up into an HMAC-INIT */
+@@ -91,9 +89,9 @@
+ LDST_CLASS_2_CCB | FIFOST_TYPE_SPLIT_KEK);
+
+ #ifdef DEBUG
+- print_hex_dump(KERN_ERR, "ctx.key@"__stringify(__LINE__)": ",
++ print_hex_dump(KERN_ERR, "ctx.key@"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, key_in, keylen, 1);
+- print_hex_dump(KERN_ERR, "jobdesc@"__stringify(__LINE__)": ",
++ print_hex_dump(KERN_ERR, "jobdesc@"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
+ #endif
+
+@@ -106,12 +104,13 @@
+ wait_for_completion_interruptible(&result.completion);
+ ret = result.err;
+ #ifdef DEBUG
+- print_hex_dump(KERN_ERR, "ctx.key@"__stringify(__LINE__)": ",
++ print_hex_dump(KERN_ERR, "ctx.key@"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, key_out,
+ split_key_pad_len, 1);
+ #endif
+ }
+-
++ dma_sync_single_for_cpu(jrdev, dma_addr_out, split_key_pad_len,
++ DMA_FROM_DEVICE);
+ dma_unmap_single(jrdev, dma_addr_out, split_key_pad_len,
+ DMA_FROM_DEVICE);
+ out_unmap_in:
+diff -Nur linux-4.1.3/drivers/crypto/caam/Makefile linux-xbian-imx6/drivers/crypto/caam/Makefile
+--- linux-4.1.3/drivers/crypto/caam/Makefile 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/drivers/crypto/caam/Makefile 2015-07-27 23:13:04.205975852 +0200
+@@ -1,15 +1,14 @@
+ #
+ # Makefile for the CAAM backend and dependent components
+ #
+-ifeq ($(CONFIG_CRYPTO_DEV_FSL_CAAM_DEBUG), y)
+- EXTRA_CFLAGS := -DDEBUG
+-endif
+
+ obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM) += caam.o
+-obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_JR) += caam_jr.o
+ obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API) += caamalg.o
+ obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API) += caamhash.o
+ obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API) += caamrng.o
++obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_SM) += sm_store.o
++obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST) += sm_test.o
++obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO) += secvio.o
++obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_KEYBLOB) += caam_keyblob.o
+
+-caam-objs := ctrl.o
+-caam_jr-objs := jr.o key_gen.o error.o
++caam-objs := ctrl.o jr.o error.o key_gen.o
+diff -Nur linux-4.1.3/drivers/crypto/caam/pdb.h linux-xbian-imx6/drivers/crypto/caam/pdb.h
+--- linux-4.1.3/drivers/crypto/caam/pdb.h 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/drivers/crypto/caam/pdb.h 2015-07-27 23:13:04.213947410 +0200
+@@ -44,7 +44,6 @@
+ #define PDBOPTS_ESP_IPHDRSRC 0x08 /* IP header comes from PDB (encap) */
+ #define PDBOPTS_ESP_INCIPHDR 0x04 /* Prepend IP header to output frame */
+ #define PDBOPTS_ESP_IPVSN 0x02 /* process IPv6 header */
+-#define PDBOPTS_ESP_AOFL 0x04 /* adjust out frame len (decap, SEC>=5.3)*/
+ #define PDBOPTS_ESP_TUNNEL 0x01 /* tunnel mode next-header byte */
+ #define PDBOPTS_ESP_IPV6 0x02 /* ip header version is V6 */
+ #define PDBOPTS_ESP_DIFFSERV 0x40 /* copy TOS/TC from inner iphdr */
+diff -Nur linux-4.1.3/drivers/crypto/caam/regs.h linux-xbian-imx6/drivers/crypto/caam/regs.h
+--- linux-4.1.3/drivers/crypto/caam/regs.h 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/drivers/crypto/caam/regs.h 2015-07-27 23:13:04.213947410 +0200
+@@ -1,7 +1,7 @@
+ /*
+ * CAAM hardware register-level view
+ *
+- * Copyright 2008-2011 Freescale Semiconductor, Inc.
++ * Copyright (C) 2008-2013 Freescale Semiconductor, Inc.
+ */
+
+ #ifndef REGS_H
+@@ -74,17 +74,22 @@
+ #endif
+ #else
+ #ifdef __LITTLE_ENDIAN
+-#define wr_reg32(reg, data) __raw_writel(data, reg)
+-#define rd_reg32(reg) __raw_readl(reg)
++#define wr_reg32(reg, data) writel(data, reg)
++#define rd_reg32(reg) readl(reg)
+ #ifdef CONFIG_64BIT
+-#define wr_reg64(reg, data) __raw_writeq(data, reg)
+-#define rd_reg64(reg) __raw_readq(reg)
++#define wr_reg64(reg, data) writeq(data, reg)
++#define rd_reg64(reg) readq(reg)
+ #endif
+ #endif
+ #endif
+
++#ifdef CONFIG_ARM
++/* These are common macros for Power, put here for ARMs */
++#define setbits32(_addr, _v) writel((readl(_addr) | (_v)), (_addr))
++#define clrbits32(_addr, _v) writel((readl(_addr) & ~(_v)), (_addr))
++#endif
++
+ #ifndef CONFIG_64BIT
+-#ifdef __BIG_ENDIAN
+ static inline void wr_reg64(u64 __iomem *reg, u64 data)
+ {
+ wr_reg32((u32 __iomem *)reg, (data & 0xffffffff00000000ull) >> 32);
+@@ -96,21 +101,6 @@
+ return (((u64)rd_reg32((u32 __iomem *)reg)) << 32) |
+ ((u64)rd_reg32((u32 __iomem *)reg + 1));
+ }
+-#else
+-#ifdef __LITTLE_ENDIAN
+-static inline void wr_reg64(u64 __iomem *reg, u64 data)
+-{
+- wr_reg32((u32 __iomem *)reg + 1, (data & 0xffffffff00000000ull) >> 32);
+- wr_reg32((u32 __iomem *)reg, data & 0x00000000ffffffffull);
+-}
+-
+-static inline u64 rd_reg64(u64 __iomem *reg)
+-{
+- return (((u64)rd_reg32((u32 __iomem *)reg + 1)) << 32) |
+- ((u64)rd_reg32((u32 __iomem *)reg));
+-}
+-#endif
+-#endif
+ #endif
+
+ /*
+@@ -123,6 +113,98 @@
+ } __packed;
+
+ /*
++ * CHA version ID / instantiation bitfields
++ * Defined for use within cha_id in perfmon
++ * Note that the same shift/mask selectors can be used to pull out number
++ * of instantiated blocks within cha_num in perfmon, the locations are
++ * the same.
++ */
++
++/* Job Ring */
++#define CHA_ID_JR_SHIFT 60
++#define CHA_ID_JR_MASK (0xfull << CHA_ID_JR_SHIFT)
++
++/* DEscriptor COntroller */
++#define CHA_ID_DECO_SHIFT 56
++#define CHA_ID_DECO_MASK (0xfull << CHA_ID_DECO_SHIFT)
++#define CHA_NUM_DECONUM_SHIFT 56 /* legacy definition */
++#define CHA_NUM_DECONUM_MASK (0xfull << CHA_NUM_DECONUM_SHIFT)
++
++/* ZUC-Authentication */
++#define CHA_ID_ZA_SHIFT 44
++#define CHA_ID_ZA_MASK (0xfull << CHA_ID_ZA_SHIFT)
++
++/* ZUC-Encryption */
++#define CHA_ID_ZE_SHIFT 40
++#define CHA_ID_ZE_MASK (0xfull << CHA_ID_ZE_SHIFT)
++
++/* SNOW f9 */
++#define CHA_ID_SNW9_SHIFT 36
++#define CHA_ID_SNW9_MASK (0xfull << CHA_ID_SNW9_SHIFT)
++
++/* CRC */
++#define CHA_ID_CRC_SHIFT 32
++#define CHA_ID_CRC_MASK (0xfull << CHA_ID_CRC_SHIFT)
++
++/* Public Key */
++#define CHA_ID_PK_SHIFT 28
++#define CHA_ID_PK_MASK (0xfull << CHA_ID_PK_SHIFT)
++
++/* Kasumi */
++#define CHA_ID_KAS_SHIFT 24
++#define CHA_ID_KAS_MASK (0xfull << CHA_ID_KAS_SHIFT)
++
++/* SNOW f8 */
++#define CHA_ID_SNW8_SHIFT 20
++#define CHA_ID_SNW8_MASK (0xfull << CHA_ID_SNW8_SHIFT)
++
++/*
++ * Random Generator
++ * RNG4 = FIPS-verification-compliant, requires init kickstart for use
++ */
++#define CHA_ID_RNG_SHIFT 16
++#define CHA_ID_RNG_MASK (0xfull << CHA_ID_RNG_SHIFT)
++#define CHA_ID_RNG_A (0x1ull << CHA_ID_RNG_SHIFT)
++#define CHA_ID_RNG_B (0x2ull << CHA_ID_RNG_SHIFT)
++#define CHA_ID_RNG_C (0x3ull << CHA_ID_RNG_SHIFT)
++#define CHA_ID_RNG_4 (0x4ull << CHA_ID_RNG_SHIFT)
++
++/*
++ * Message Digest
++ * LP256 = Low Power (MD5/SHA1/SHA224/SHA256 + HMAC)
++ * LP512 = Low Power (LP256 + SHA384/SHA512)
++ * HP = High Power (LP512 + SMAC)
++ */
++#define CHA_ID_MD_SHIFT 12
++#define CHA_ID_MD_MASK (0xfull << CHA_ID_MD_SHIFT)
++#define CHA_ID_MD_LP256 (0x0ull << CHA_ID_MD_SHIFT)
++#define CHA_ID_MD_LP512 (0x1ull << CHA_ID_MD_SHIFT)
++#define CHA_ID_MD_HP (0x2ull << CHA_ID_MD_SHIFT)
++
++/* ARC4 Streamcipher */
++#define CHA_ID_ARC4_SHIFT 8
++#define CHA_ID_ARC4_MASK (0xfull << CHA_ID_ARC4_SHIFT)
++#define CHA_ID_ARC4_LP (0x0ull << CHA_ID_ARC4_SHIFT)
++#define CHA_ID_ARC4_HP (0x1ull << CHA_ID_ARC4_SHIFT)
++
++/* DES Blockcipher Accelerator */
++#define CHA_ID_DES_SHIFT 4
++#define CHA_ID_DES_MASK (0xfull << CHA_ID_DES_SHIFT)
++
++/*
++ * AES Blockcipher + Combo Mode Accelerator
++ * LP = Low Power (includes ECB/CBC/CFB128/OFB/CTR/CCM/CMAC/XCBC-MAC)
++ * HP = High Power (LP + CBCXCBC/CTRXCBC/XTS/GCM)
++ * DIFFPWR = ORed in if differential-power-analysis resistance implemented
++ */
++#define CHA_ID_AES_SHIFT 0
++#define CHA_ID_AES_MASK (0xfull << CHA_ID_AES_SHIFT)
++#define CHA_ID_AES_LP (0x3ull << CHA_ID_AES_SHIFT)
++#define CHA_ID_AES_HP (0x4ull << CHA_ID_AES_SHIFT)
++#define CHA_ID_AES_DIFFPWR (0x1ull << CHA_ID_AES_SHIFT)
++
++
++/*
+ * caam_perfmon - Performance Monitor/Secure Memory Status/
+ * CAAM Global Status/Component Version IDs
+ *
+@@ -130,45 +212,8 @@
+ */
+
+ /* Number of DECOs */
+-#define CHA_NUM_MS_DECONUM_SHIFT 24
+-#define CHA_NUM_MS_DECONUM_MASK (0xfull << CHA_NUM_MS_DECONUM_SHIFT)
+-
+-/* CHA Version IDs */
+-#define CHA_ID_LS_AES_SHIFT 0
+-#define CHA_ID_LS_AES_MASK (0xfull << CHA_ID_LS_AES_SHIFT)
+-
+-#define CHA_ID_LS_DES_SHIFT 4
+-#define CHA_ID_LS_DES_MASK (0xfull << CHA_ID_LS_DES_SHIFT)
+-
+-#define CHA_ID_LS_ARC4_SHIFT 8
+-#define CHA_ID_LS_ARC4_MASK (0xfull << CHA_ID_LS_ARC4_SHIFT)
+-
+-#define CHA_ID_LS_MD_SHIFT 12
+-#define CHA_ID_LS_MD_MASK (0xfull << CHA_ID_LS_MD_SHIFT)
+-
+-#define CHA_ID_LS_RNG_SHIFT 16
+-#define CHA_ID_LS_RNG_MASK (0xfull << CHA_ID_LS_RNG_SHIFT)
+-
+-#define CHA_ID_LS_SNW8_SHIFT 20
+-#define CHA_ID_LS_SNW8_MASK (0xfull << CHA_ID_LS_SNW8_SHIFT)
+-
+-#define CHA_ID_LS_KAS_SHIFT 24
+-#define CHA_ID_LS_KAS_MASK (0xfull << CHA_ID_LS_KAS_SHIFT)
+-
+-#define CHA_ID_LS_PK_SHIFT 28
+-#define CHA_ID_LS_PK_MASK (0xfull << CHA_ID_LS_PK_SHIFT)
+-
+-#define CHA_ID_MS_CRC_SHIFT 0
+-#define CHA_ID_MS_CRC_MASK (0xfull << CHA_ID_MS_CRC_SHIFT)
+-
+-#define CHA_ID_MS_SNW9_SHIFT 4
+-#define CHA_ID_MS_SNW9_MASK (0xfull << CHA_ID_MS_SNW9_SHIFT)
+-
+-#define CHA_ID_MS_DECO_SHIFT 24
+-#define CHA_ID_MS_DECO_MASK (0xfull << CHA_ID_MS_DECO_SHIFT)
+-
+-#define CHA_ID_MS_JR_SHIFT 28
+-#define CHA_ID_MS_JR_MASK (0xfull << CHA_ID_MS_JR_SHIFT)
++#define CHA_NUM_DECONUM_SHIFT 56
++#define CHA_NUM_DECONUM_MASK (0xfull << CHA_NUM_DECONUM_SHIFT)
+
+ struct sec_vid {
+ u16 ip_id;
+@@ -176,6 +221,10 @@
+ u8 min_rev;
+ };
+
++#define SEC_VID_IPID_SHIFT 16
++#define SEC_VID_MAJ_SHIFT 8
++#define SEC_VID_MAJ_MASK 0xFF00
++
+ struct caam_perfmon {
+ /* Performance Monitor Registers f00-f9f */
+ u64 req_dequeued; /* PC_REQ_DEQ - Dequeued Requests */
+@@ -188,36 +237,89 @@
+ u64 rsvd[13];
+
+ /* CAAM Hardware Instantiation Parameters fa0-fbf */
+- u32 cha_rev_ms; /* CRNR - CHA Rev No. Most significant half*/
+- u32 cha_rev_ls; /* CRNR - CHA Rev No. Least significant half*/
+-#define CTPR_MS_QI_SHIFT 25
+-#define CTPR_MS_QI_MASK (0x1ull << CTPR_MS_QI_SHIFT)
+-#define CTPR_MS_VIRT_EN_INCL 0x00000001
+-#define CTPR_MS_VIRT_EN_POR 0x00000002
+-#define CTPR_MS_PG_SZ_MASK 0x10
+-#define CTPR_MS_PG_SZ_SHIFT 4
+- u32 comp_parms_ms; /* CTPR - Compile Parameters Register */
+- u32 comp_parms_ls; /* CTPR - Compile Parameters Register */
+- u64 rsvd1[2];
++ u64 cha_rev; /* CRNR - CHA Revision Number */
++#define CTPR_QI_SHIFT 57
++#define CTPR_QI_MASK (0x1ull << CTPR_QI_SHIFT)
++ u64 comp_parms; /* CTPR - Compile Parameters Register */
++
++ /* Secure Memory State Visibility */
++ u32 rsvd1;
++ u32 smstatus; /* Secure memory status */
++ u32 rsvd2;
++ u32 smpartown; /* Secure memory partition owner */
+
+ /* CAAM Global Status fc0-fdf */
+ u64 faultaddr; /* FAR - Fault Address */
+ u32 faultliodn; /* FALR - Fault Address LIODN */
+ u32 faultdetail; /* FADR - Fault Addr Detail */
+- u32 rsvd2;
++ u32 rsvd3;
+ u32 status; /* CSTA - CAAM Status */
+- u64 rsvd3;
++ u32 smpart; /* Secure Memory Partition Parameters */
++ u32 smvid; /* Secure Memory Version ID */
+
+ /* Component Instantiation Parameters fe0-fff */
+ u32 rtic_id; /* RVID - RTIC Version ID */
+ u32 ccb_id; /* CCBVID - CCB Version ID */
+- u32 cha_id_ms; /* CHAVID - CHA Version ID Most Significant*/
+- u32 cha_id_ls; /* CHAVID - CHA Version ID Least Significant*/
+- u32 cha_num_ms; /* CHANUM - CHA Number Most Significant */
+- u32 cha_num_ls; /* CHANUM - CHA Number Least Significant*/
+- u32 caam_id_ms; /* CAAMVID - CAAM Version ID MS */
+- u32 caam_id_ls; /* CAAMVID - CAAM Version ID LS */
+-};
++ u64 cha_id; /* CHAVID - CHA Version ID */
++ u64 cha_num; /* CHANUM - CHA Number */
++ u64 caam_id; /* CAAMVID - CAAM Version ID */
++};
++
++#define SMSTATUS_PART_SHIFT 28
++#define SMSTATUS_PART_MASK (0xf << SMSTATUS_PART_SHIFT)
++#define SMSTATUS_PAGE_SHIFT 16
++#define SMSTATUS_PAGE_MASK (0x7ff << SMSTATUS_PAGE_SHIFT)
++#define SMSTATUS_MID_SHIFT 8
++#define SMSTATUS_MID_MASK (0x3f << SMSTATUS_MID_SHIFT)
++#define SMSTATUS_ACCERR_SHIFT 4
++#define SMSTATUS_ACCERR_MASK (0xf << SMSTATUS_ACCERR_SHIFT)
++#define SMSTATUS_ACCERR_NONE 0
++#define SMSTATUS_ACCERR_ALLOC 1 /* Page not allocated */
++#define SMSTATUS_ACCESS_ID 2 /* Not granted by ID */
++#define SMSTATUS_ACCESS_WRITE 3 /* Writes not allowed */
++#define SMSTATUS_ACCESS_READ 4 /* Reads not allowed */
++#define SMSTATUS_ACCESS_NONKEY 6 /* Non-key reads not allowed */
++#define SMSTATUS_ACCESS_BLOB 9 /* Blob access not allowed */
++#define SMSTATUS_ACCESS_DESCB 10 /* Descriptor Blob access spans pages */
++#define SMSTATUS_ACCESS_NON_SM 11 /* Outside Secure Memory range */
++#define SMSTATUS_ACCESS_XPAGE 12 /* Access crosses pages */
++#define SMSTATUS_ACCESS_INITPG 13 /* Page still initializing */
++#define SMSTATUS_STATE_SHIFT 0
++#define SMSTATUS_STATE_MASK (0xf << SMSTATUS_STATE_SHIFT)
++#define SMSTATUS_STATE_RESET 0
++#define SMSTATUS_STATE_INIT 1
++#define SMSTATUS_STATE_NORMAL 2
++#define SMSTATUS_STATE_FAIL 3
++
++/* up to 15 rings, 2 bits shifted by ring number */
++#define SMPARTOWN_RING_SHIFT 2
++#define SMPARTOWN_RING_MASK 3
++#define SMPARTOWN_AVAILABLE 0
++#define SMPARTOWN_NOEXIST 1
++#define SMPARTOWN_UNAVAILABLE 2
++#define SMPARTOWN_OURS 3
++
++/* Maximum number of pages possible */
++#define SMPART_MAX_NUMPG_SHIFT 16
++#define SMPART_MAX_NUMPG_MASK (0x3f << SMPART_MAX_NUMPG_SHIFT)
++
++/* Maximum partition number */
++#define SMPART_MAX_PNUM_SHIFT 12
++#define SMPART_MAX_PNUM_MASK (0xf << SMPART_MAX_PNUM_SHIFT)
++
++/* Highest possible page number */
++#define SMPART_MAX_PG_SHIFT 0
++#define SMPART_MAX_PG_MASK (0x3f << SMPART_MAX_PG_SHIFT)
++
++/* Max size of a page */
++#define SMVID_PG_SIZE_SHIFT 16
++#define SMVID_PG_SIZE_MASK (0x7 << SMVID_PG_SIZE_SHIFT)
++
++/* Major/Minor Version ID */
++#define SMVID_MAJ_VERS_SHIFT 8
++#define SMVID_MAJ_VERS (0xf << SMVID_MAJ_VERS_SHIFT)
++#define SMVID_MIN_VERS_SHIFT 0
++#define SMVID_MIN_VERS (0xf << SMVID_MIN_VERS_SHIFT)
+
+ /* LIODN programming for DMA configuration */
+ #define MSTRID_LOCK_LIODN 0x80000000
+@@ -270,17 +372,7 @@
+
+ /* RNG4 TRNG test registers */
+ struct rng4tst {
+-#define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode */
+-#define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_SC 0 /* use von Neumann data in
+- both entropy shifter and
+- statistical checker */
+-#define RTMCTL_SAMP_MODE_RAW_ES_SC 1 /* use raw data in both
+- entropy shifter and
+- statistical checker */
+-#define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_RAW_SC 2 /* use von Neumann data in
+- entropy shifter, raw data
+- in statistical checker */
+-#define RTMCTL_SAMP_MODE_INVALID 3 /* invalid combination */
++#define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode */
+ u32 rtmctl; /* misc. control register */
+ u32 rtscmisc; /* statistical check misc. register */
+ u32 rtpkrrng; /* poker range register */
+@@ -290,26 +382,22 @@
+ };
+ #define RTSDCTL_ENT_DLY_SHIFT 16
+ #define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT)
+-#define RTSDCTL_ENT_DLY_MIN 3200
+-#define RTSDCTL_ENT_DLY_MAX 12800
+ u32 rtsdctl; /* seed control register */
+ union {
+ u32 rtsblim; /* PRGM=1: sparse bit limit register */
+ u32 rttotsam; /* PRGM=0: total samples register */
+ };
+ u32 rtfrqmin; /* frequency count min. limit register */
+-#define RTFRQMAX_DISABLE (1 << 20)
+ union {
+ u32 rtfrqmax; /* PRGM=1: freq. count max. limit register */
+ u32 rtfrqcnt; /* PRGM=0: freq. count register */
+ };
+ u32 rsvd1[40];
+-#define RDSTA_SKVT 0x80000000
+-#define RDSTA_SKVN 0x40000000
+-#define RDSTA_IF0 0x00000001
+-#define RDSTA_IF1 0x00000002
+-#define RDSTA_IFMASK (RDSTA_IF1 | RDSTA_IF0)
+- u32 rdsta;
++#define RDSTA_IF 0x00000003 /* state handle instantiated flags 0 and 1 */
++#define RDSTA_SKVN 0x40000000 /* Secure Key Valid Non-Test mode */
++#define RDSTA_SKVT 0x80000000 /* Secure Key Valid Test. non-test mode */
++#define RDSTA_TF 0x00000300 /* State handle instantiated Test-mode */
++ u32 rdsta; /* DRNG status register */
+ u32 rsvd2[15];
+ };
+
+@@ -340,12 +428,9 @@
+ /* Bus Access Configuration Section 010-11f */
+ /* Read/Writable */
+ struct masterid jr_mid[4]; /* JRxLIODNR - JobR LIODN setup */
+- u32 rsvd3[11];
+- u32 jrstart; /* JRSTART - Job Ring Start Register */
++ u32 rsvd3[12];
+ struct masterid rtic_mid[4]; /* RTICxLIODNR - RTIC LIODN setup */
+- u32 rsvd4[5];
+- u32 deco_rsr; /* DECORSR - Deco Request Source */
+- u32 rsvd11;
++ u32 rsvd4[7];
+ u32 deco_rq; /* DECORR - DECO Request */
+ struct partid deco_mid[5]; /* DECOxLIODNR - 1 per DECO */
+ u32 rsvd5[22];
+@@ -386,11 +471,6 @@
+ #define MCFGR_DMA_RESET 0x10000000
+ #define MCFGR_LONG_PTR 0x00010000 /* Use >32-bit desc addressing */
+ #define SCFGR_RDBENABLE 0x00000400
+-#define SCFGR_VIRT_EN 0x00008000
+-#define DECORR_RQD0ENABLE 0x00000001 /* Enable DECO0 for direct access */
+-#define DECORSR_JR0 0x00000001 /* JR to supply TZ, SDID, ICID */
+-#define DECORSR_VALID 0x80000000
+-#define DECORR_DEN0 0x00010000 /* DECO0 available for access*/
+
+ /* AXI read cache control */
+ #define MCFGR_ARCACHE_SHIFT 12
+@@ -407,12 +487,6 @@
+ #define MCFGR_AXIPRI 0x00000008 /* Assert AXI priority sideband */
+ #define MCFGR_BURST_64 0x00000001 /* Max burst size */
+
+-/* JRSTART register offsets */
+-#define JRSTART_JR0_START 0x00000001 /* Start Job ring 0 */
+-#define JRSTART_JR1_START 0x00000002 /* Start Job ring 1 */
+-#define JRSTART_JR2_START 0x00000004 /* Start Job ring 2 */
+-#define JRSTART_JR3_START 0x00000008 /* Start Job ring 3 */
+-
+ /*
+ * caam_job_ring - direct job ring setup
+ * 1-4 possible per instantiation, base + 1000/2000/3000/4000
+@@ -455,7 +529,18 @@
+ u32 rsvd11;
+ u32 jrcommand; /* JRCRx - JobR command */
+
+- u32 rsvd12[932];
++ u32 rsvd12[33];
++
++ /* Secure Memory Configuration - if you have it */
++ u32 sm_cmd; /* SMCJRx - Secure memory command */
++ u32 rsvd13;
++ u32 sm_status; /* SMCSJRx - Secure memory status */
++ u32 rsvd14;
++ u32 sm_perm; /* SMAPJRx - Secure memory access perms */
++ u32 sm_group2; /* SMAP2JRx - Secure memory access group 2 */
++ u32 sm_group1; /* SMAP1JRx - Secure memory access group 1 */
++
++ u32 rsvd15[891];
+
+ /* Performance Monitor f00-fff */
+ struct caam_perfmon perfmon;
+@@ -578,6 +663,62 @@
+
+ #define JRCR_RESET 0x01
+
++/* secure memory command */
++#define SMC_PAGE_SHIFT 16
++#define SMC_PAGE_MASK (0xffff << SMC_PAGE_SHIFT)
++#define SMC_PART_SHIFT 8
++#define SMC_PART_MASK (0x0f << SMC_PART_SHIFT)
++#define SMC_CMD_SHIFT 0
++#define SMC_CMD_MASK (0x0f << SMC_CMD_SHIFT)
++
++#define SMC_CMD_ALLOC_PAGE 0x01 /* allocate page to this partition */
++#define SMC_CMD_DEALLOC_PAGE 0x02 /* deallocate page from partition */
++#define SMC_CMD_DEALLOC_PART 0x03 /* deallocate partition */
++#define SMC_CMD_PAGE_INQUIRY 0x05 /* find partition associate with page */
++
++/* secure memory (command) status */
++#define SMCS_PAGE_SHIFT 16
++#define SMCS_PAGE_MASK (0x0fff << SMCS_PAGE_SHIFT)
++#define SMCS_CMDERR_SHIFT 14
++#define SMCS_CMDERR_MASK (3 << SMCS_CMDERR_SHIFT)
++#define SMCS_ALCERR_SHIFT 12
++#define SMCS_ALCERR_MASK (3 << SMCS_ALCERR_SHIFT)
++#define SMCS_PGOWN_SHIFT 6
++#define SMCS_PGWON_MASK (3 << SMCS_PGOWN_SHIFT)
++#define SMCS_PART_SHIFT 0
++#define SMCS_PART_MASK (0xf << SMCS_PART_SHIFT)
++
++#define SMCS_CMDERR_NONE 0
++#define SMCS_CMDERR_INCOMP 1 /* Command not yet complete */
++#define SMCS_CMDERR_SECFAIL 2 /* Security failure occurred */
++#define SMCS_CMDERR_OVERFLOW 3 /* Command overflow */
++
++#define SMCS_ALCERR_NONE 0
++#define SMCS_ALCERR_PSPERR 1 /* Partion marked PSP (dealloc only) */
++#define SMCS_ALCERR_PAGEAVAIL 2 /* Page not available */
++#define SMCS_ALCERR_PARTOWN 3 /* Partition ownership error */
++
++#define SMCS_PGOWN_AVAIL 0 /* Page is available */
++#define SMCS_PGOWN_NOEXIST 1 /* Page initializing or nonexistent */
++#define SMCS_PGOWN_NOOWN 2 /* Page owned by another processor */
++#define SMCS_PGOWN_OWNED 3 /* Page belongs to this processor */
++
++/* secure memory access permissions */
++#define SMCS_PERM_KEYMOD_SHIFT 16
++#define SMCA_PERM_KEYMOD_MASK (0xff << SMCS_PERM_KEYMOD_SHIFT)
++#define SMCA_PERM_CSP_ZERO 0x8000 /* Zero when deallocated or released */
++#define SMCA_PERM_PSP_LOCK 0x4000 /* Part./pages can't be deallocated */
++#define SMCA_PERM_PERM_LOCK 0x2000 /* Lock permissions */
++#define SMCA_PERM_GRP_LOCK 0x1000 /* Lock access groups */
++#define SMCA_PERM_RINGID_SHIFT 10
++#define SMCA_PERM_RINGID_MASK (3 << SMCA_PERM_RINGID_SHIFT)
++#define SMCA_PERM_G2_BLOB 0x0080 /* Group 2 blob import/export */
++#define SMCA_PERM_G2_WRITE 0x0020 /* Group 2 write */
++#define SMCA_PERM_G2_READ 0x0010 /* Group 2 read */
++#define SMCA_PERM_G1_BLOB 0x0008 /* Group 1... */
++#define SMCA_PERM_G1_WRITE 0x0002
++#define SMCA_PERM_G1_READ 0x0001
++
+ /*
+ * caam_assurance - Assurance Controller View
+ * base + 0x6000 padded out to 0x1000
+@@ -746,7 +887,6 @@
+ u32 jr_ctl_hi; /* CxJRR - JobR Control Register @800 */
+ u32 jr_ctl_lo;
+ u64 jr_descaddr; /* CxDADR - JobR Descriptor Address */
+-#define DECO_OP_STATUS_HI_ERR_MASK 0xF00000FF
+ u32 op_status_hi; /* DxOPSTA - DECO Operation Status */
+ u32 op_status_lo;
+ u32 rsvd24[2];
+@@ -760,21 +900,36 @@
+ struct deco_sg_table sctr_tbl[4]; /* DxSTR - Scatter Tables */
+ u32 rsvd29[48];
+ u32 descbuf[64]; /* DxDESB - Descriptor buffer */
+- u32 rscvd30[193];
+-#define DESC_DBG_DECO_STAT_HOST_ERR 0x00D00000
+-#define DESC_DBG_DECO_STAT_VALID 0x80000000
+-#define DESC_DBG_DECO_STAT_MASK 0x00F00000
+- u32 desc_dbg; /* DxDDR - DECO Debug Register */
+- u32 rsvd31[126];
+-};
+-
+-#define DECO_JQCR_WHL 0x20000000
+-#define DECO_JQCR_FOUR 0x10000000
+-
+-#define JR_BLOCK_NUMBER 1
+-#define ASSURE_BLOCK_NUMBER 6
+-#define QI_BLOCK_NUMBER 7
+-#define DECO_BLOCK_NUMBER 8
+-#define PG_SIZE_4K 0x1000
+-#define PG_SIZE_64K 0x10000
++ u32 rsvd30[320];
++};
++
++/*
++ * Current top-level view of memory map is:
++ *
++ * 0x0000 - 0x0fff - CAAM Top-Level Control
++ * 0x1000 - 0x1fff - Job Ring 0
++ * 0x2000 - 0x2fff - Job Ring 1
++ * 0x3000 - 0x3fff - Job Ring 2
++ * 0x4000 - 0x4fff - Job Ring 3
++ * 0x5000 - 0x5fff - (unused)
++ * 0x6000 - 0x6fff - Assurance Controller
++ * 0x7000 - 0x7fff - Queue Interface
++ * 0x8000 - 0x8fff - DECO-CCB 0
++ * 0x9000 - 0x9fff - DECO-CCB 1
++ * 0xa000 - 0xafff - DECO-CCB 2
++ * 0xb000 - 0xbfff - DECO-CCB 3
++ * 0xc000 - 0xcfff - DECO-CCB 4
++ *
++ * caam_full describes the full register view of CAAM if useful,
++ * although many configurations may choose to implement parts of
++ * the register map separately, in differing privilege regions
++ */
++struct caam_full {
++ struct caam_ctrl __iomem ctrl;
++ struct caam_job_ring jr[4];
++ u64 rsvd[512];
++ struct caam_assurance assure;
++ struct caam_queue_if qi;
++};
++
+ #endif /* REGS_H */
+diff -Nur linux-4.1.3/drivers/crypto/caam/secvio.c linux-xbian-imx6/drivers/crypto/caam/secvio.c
+--- linux-4.1.3/drivers/crypto/caam/secvio.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/crypto/caam/secvio.c 2015-07-27 23:13:04.213947410 +0200
+@@ -0,0 +1,290 @@
++
++/*
++ * SNVS Security Violation Handler
++ * Copyright (C) 2012-2015 Freescale Semiconductor, Inc., All Rights Reserved
++ */
++
++#include "compat.h"
++#include "intern.h"
++#include "secvio.h"
++#include "regs.h"
++
++/*
++ * These names are associated with each violation handler.
++ * The source names were taken from MX6, and are based on recommendations
++ * for most common SoCs.
++ */
++static const u8 *violation_src_name[] = {
++ "CAAM Internal Security Violation",
++ "JTAG Alarm",
++ "Watchdog",
++ "(reserved)",
++ "External Boot",
++ "External Tamper Detect",
++};
++
++/* These names help describe security monitor state for the console */
++static const u8 *snvs_ssm_state_name[] = {
++ "init",
++ "hard fail",
++ "(undef:2)",
++ "soft fail",
++ "(undef:4)",
++ "(undef:5)",
++ "(undef:6)",
++ "(undef:7)",
++ "transition",
++ "check",
++ "(undef:10)",
++ "non-secure",
++ "(undef:12)",
++ "trusted",
++ "(undef:14)",
++ "secure",
++};
++
++/* Top-level security violation interrupt */
++static irqreturn_t snvs_secvio_interrupt(int irq, void *snvsdev)
++{
++ struct device *dev = snvsdev;
++ struct snvs_secvio_drv_private *svpriv = dev_get_drvdata(dev);
++
++ /* Check the HP secvio status register */
++ svpriv->irqcause = rd_reg32(&svpriv->svregs->hp.secvio_status) &
++ HP_SECVIOST_SECVIOMASK;
++
++ if (!svpriv->irqcause)
++ return IRQ_NONE;
++
++ /* Now ACK cause */
++ setbits32(&svpriv->svregs->hp.secvio_status, svpriv->irqcause);
++
++ /* And run deferred service */
++ preempt_disable();
++ tasklet_schedule(&svpriv->irqtask[smp_processor_id()]);
++ preempt_enable();
++
++ return IRQ_HANDLED;
++}
++
++/* Deferred service handler. Tasklet arg is simply the SNVS dev */
++static void snvs_secvio_dispatch(unsigned long indev)
++{
++ struct device *dev = (struct device *)indev;
++ struct snvs_secvio_drv_private *svpriv = dev_get_drvdata(dev);
++ unsigned long flags;
++ int i;
++
++
++ /* Look through stored causes, call each handler if exists */
++ for (i = 0; i < MAX_SECVIO_SOURCES; i++)
++ if (svpriv->irqcause & (1 << i)) {
++ spin_lock_irqsave(&svpriv->svlock, flags);
++ svpriv->intsrc[i].handler(dev, i,
++ svpriv->intsrc[i].ext);
++ spin_unlock_irqrestore(&svpriv->svlock, flags);
++ };
++
++ /* Re-enable now-serviced interrupts */
++ setbits32(&svpriv->svregs->hp.secvio_intcfg, svpriv->irqcause);
++}
++
++/*
++ * Default cause handler, used in lieu of an application-defined handler.
++ * All it does at this time is print a console message. It could force a halt.
++ */
++static void snvs_secvio_default(struct device *dev, u32 cause, void *ext)
++{
++ struct snvs_secvio_drv_private *svpriv = dev_get_drvdata(dev);
++
++ dev_err(dev, "Unhandled Security Violation Interrupt %d = %s\n",
++ cause, svpriv->intsrc[cause].intname);
++}
++
++/*
++ * Install an application-defined handler for a specified cause
++ * Arguments:
++ * - dev points to SNVS-owning device
++ * - cause interrupt source cause
++ * - handler application-defined handler, gets called with dev
++ * source cause, and locally-defined handler argument
++ * - cause_description points to a string to override the default cause
++ * name, this can be used as an alternate for error
++ * messages and such. If left NULL, the default
++ * description string is used.
++ * - ext pointer to any extra data needed by the handler.
++ */
++int snvs_secvio_install_handler(struct device *dev, enum secvio_cause cause,
++ void (*handler)(struct device *dev, u32 cause,
++ void *ext),
++ u8 *cause_description, void *ext)
++{
++ unsigned long flags;
++ struct snvs_secvio_drv_private *svpriv;
++
++ svpriv = dev_get_drvdata(dev);
++
++ if ((handler == NULL) || (cause > SECVIO_CAUSE_SOURCE_5))
++ return -EINVAL;
++
++ spin_lock_irqsave(&svpriv->svlock, flags);
++ svpriv->intsrc[cause].handler = handler;
++ if (cause_description != NULL)
++ svpriv->intsrc[cause].intname = cause_description;
++ if (ext != NULL)
++ svpriv->intsrc[cause].ext = ext;
++ spin_unlock_irqrestore(&svpriv->svlock, flags);
++
++ return 0;
++}
++EXPORT_SYMBOL(snvs_secvio_install_handler);
++
++/*
++ * Remove an application-defined handler for a specified cause (and, by
++ * implication, restore the "default".
++ * Arguments:
++ * - dev points to SNVS-owning device
++ * - cause interrupt source cause
++ */
++int snvs_secvio_remove_handler(struct device *dev, enum secvio_cause cause)
++{
++ unsigned long flags;
++ struct snvs_secvio_drv_private *svpriv;
++
++ svpriv = dev_get_drvdata(dev);
++
++ if (cause > SECVIO_CAUSE_SOURCE_5)
++ return -EINVAL;
++
++ spin_lock_irqsave(&svpriv->svlock, flags);
++ svpriv->intsrc[cause].intname = violation_src_name[cause];
++ svpriv->intsrc[cause].handler = snvs_secvio_default;
++ svpriv->intsrc[cause].ext = NULL;
++ spin_unlock_irqrestore(&svpriv->svlock, flags);
++ return 0;
++}
++EXPORT_SYMBOL(snvs_secvio_remove_handler);
++
++static int snvs_secvio_remove(struct platform_device *pdev)
++{
++ struct device *svdev;
++ struct snvs_secvio_drv_private *svpriv;
++ int i;
++
++ svdev = &pdev->dev;
++ svpriv = dev_get_drvdata(svdev);
++
++ /* Set all sources to nonfatal */
++ wr_reg32(&svpriv->svregs->hp.secvio_intcfg, 0);
++
++ /* Remove tasklets and release interrupt */
++ for_each_possible_cpu(i)
++ tasklet_kill(&svpriv->irqtask[i]);
++
++ free_irq(svpriv->irq, svdev);
++ iounmap(svpriv->svregs);
++ kfree(svpriv);
++
++ return 0;
++}
++
++static int snvs_secvio_probe(struct platform_device *pdev)
++{
++ struct device *svdev;
++ struct snvs_secvio_drv_private *svpriv;
++ struct device_node *np, *npirq;
++ struct snvs_full __iomem *snvsregs;
++ int i, error;
++ u32 hpstate;
++
++ svpriv = kzalloc(sizeof(struct snvs_secvio_drv_private), GFP_KERNEL);
++ if (!svpriv)
++ return -ENOMEM;
++
++ svdev = &pdev->dev;
++ dev_set_drvdata(svdev, svpriv);
++ svpriv->pdev = pdev;
++ np = pdev->dev.of_node;
++
++ npirq = of_find_compatible_node(NULL, NULL, "fsl,imx6q-caam-secvio");
++ if (!npirq) {
++ dev_err(svdev, "can't identify secvio interrupt\n");
++ kfree(svpriv);
++ return -EINVAL;
++ }
++ svpriv->irq = irq_of_parse_and_map(npirq, 0);
++ if (svpriv->irq <= 0) {
++ kfree(svpriv);
++ return -EINVAL;
++ }
++
++ snvsregs = of_iomap(np, 0);
++ if (!snvsregs) {
++ dev_err(svdev, "register mapping failed\n");
++ return -ENOMEM;
++ }
++ svpriv->svregs = (struct snvs_full __force *)snvsregs;
++
++ /* Device data set up. Now init interrupt source descriptions */
++ for (i = 0; i < MAX_SECVIO_SOURCES; i++) {
++ svpriv->intsrc[i].intname = violation_src_name[i];
++ svpriv->intsrc[i].handler = snvs_secvio_default;
++ }
++ /* Connect main handler */
++ for_each_possible_cpu(i)
++ tasklet_init(&svpriv->irqtask[i], snvs_secvio_dispatch,
++ (unsigned long)svdev);
++
++ error = request_irq(svpriv->irq, snvs_secvio_interrupt,
++ IRQF_SHARED, "snvs-secvio", svdev);
++ if (error) {
++ dev_err(svdev, "can't connect secvio interrupt\n");
++ irq_dispose_mapping(svpriv->irq);
++ svpriv->irq = 0;
++ iounmap(svpriv->svregs);
++ kfree(svpriv);
++ return -EINVAL;
++ }
++
++ /*
++ * Configure all sources as fatal violations except LP section,
++ * source #5 (typically used as an external tamper detect), and
++ * source #3 (typically unused). Whenever the transition to
++ * secure mode has occurred, these will now be "fatal" violations
++ */
++ wr_reg32(&svpriv->svregs->hp.secvio_intcfg,
++ HP_SECVIO_INTEN_SRC4 | HP_SECVIO_INTEN_SRC2 |
++ HP_SECVIO_INTEN_SRC1 | HP_SECVIO_INTEN_SRC0);
++
++ hpstate = (rd_reg32(&svpriv->svregs->hp.status) &
++ HP_STATUS_SSM_ST_MASK) >> HP_STATUS_SSM_ST_SHIFT;
++ dev_info(svdev, "violation handlers armed - %s state\n",
++ snvs_ssm_state_name[hpstate]);
++
++ return 0;
++}
++
++static struct of_device_id snvs_secvio_match[] = {
++ {
++ .compatible = "fsl,imx6q-caam-snvs",
++ },
++ {},
++};
++MODULE_DEVICE_TABLE(of, snvs_secvio_match);
++
++static struct platform_driver snvs_secvio_driver = {
++ .driver = {
++ .name = "snvs-secvio",
++ .owner = THIS_MODULE,
++ .of_match_table = snvs_secvio_match,
++ },
++ .probe = snvs_secvio_probe,
++ .remove = snvs_secvio_remove,
++};
++
++module_platform_driver(snvs_secvio_driver);
++
++MODULE_LICENSE("Dual BSD/GPL");
++MODULE_DESCRIPTION("FSL SNVS Security Violation Handler");
++MODULE_AUTHOR("Freescale Semiconductor - MCU");
++
+diff -Nur linux-4.1.3/drivers/crypto/caam/secvio.h linux-xbian-imx6/drivers/crypto/caam/secvio.h
+--- linux-4.1.3/drivers/crypto/caam/secvio.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/crypto/caam/secvio.h 2015-07-27 23:13:04.213947410 +0200
+@@ -0,0 +1,66 @@
++
++/*
++ * CAAM Security Violation Handler
++ * Copyright (C) 2012-2014 Freescale Semiconductor, Inc., All Rights Reserved
++ */
++
++#ifndef SECVIO_H
++#define SECVIO_H
++
++#include "snvsregs.h"
++
++
++/*
++ * Defines the published interfaces to install/remove application-specified
++ * handlers for catching violations
++ */
++
++#define MAX_SECVIO_SOURCES 6
++
++/* these are the untranslated causes */
++enum secvio_cause {
++ SECVIO_CAUSE_SOURCE_0,
++ SECVIO_CAUSE_SOURCE_1,
++ SECVIO_CAUSE_SOURCE_2,
++ SECVIO_CAUSE_SOURCE_3,
++ SECVIO_CAUSE_SOURCE_4,
++ SECVIO_CAUSE_SOURCE_5
++};
++
++/* These are common "recommended" cause definitions for most devices */
++#define SECVIO_CAUSE_CAAM_VIOLATION SECVIO_CAUSE_SOURCE_0
++#define SECVIO_CAUSE_JTAG_ALARM SECVIO_CAUSE_SOURCE_1
++#define SECVIO_CAUSE_WATCHDOG SECVIO_CAUSE_SOURCE_2
++#define SECVIO_CAUSE_EXTERNAL_BOOT SECVIO_CAUSE_SOURCE_4
++#define SECVIO_CAUSE_TAMPER_DETECT SECVIO_CAUSE_SOURCE_5
++
++int snvs_secvio_install_handler(struct device *dev, enum secvio_cause cause,
++ void (*handler)(struct device *dev, u32 cause,
++ void *ext),
++ u8 *cause_description, void *ext);
++int snvs_secvio_remove_handler(struct device *dev, enum secvio_cause cause);
++
++/*
++ * Private data definitions for the secvio "driver"
++ */
++
++struct secvio_int_src {
++ const u8 *intname; /* Points to a descriptive name for source */
++ void *ext; /* Extended data to pass to the handler */
++ void (*handler)(struct device *dev, u32 cause, void *ext);
++};
++
++struct snvs_secvio_drv_private {
++ struct platform_device *pdev;
++ spinlock_t svlock ____cacheline_aligned;
++ struct tasklet_struct irqtask[NR_CPUS];
++ struct snvs_full __iomem *svregs; /* both HP and LP domains */
++ int irq;
++ u32 irqcause; /* stashed cause of violation interrupt */
++
++ /* Registered handlers for each violation */
++ struct secvio_int_src intsrc[MAX_SECVIO_SOURCES];
++
++};
++
++#endif /* SECVIO_H */
+diff -Nur linux-4.1.3/drivers/crypto/caam/sg_sw_sec4.h linux-xbian-imx6/drivers/crypto/caam/sg_sw_sec4.h
+--- linux-4.1.3/drivers/crypto/caam/sg_sw_sec4.h 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/drivers/crypto/caam/sg_sw_sec4.h 2015-07-27 23:13:04.213947410 +0200
+@@ -1,7 +1,7 @@
+ /*
+ * CAAM/SEC 4.x functions for using scatterlists in caam driver
+ *
+- * Copyright 2008-2011 Freescale Semiconductor, Inc.
++ * Copyright (C) 2008-2013 Freescale Semiconductor, Inc.
+ *
+ */
+
+@@ -91,13 +91,22 @@
+ {
+ if (unlikely(chained)) {
+ int i;
++ struct scatterlist *tsg = sg;
++
++ /* We use a local copy of the sg pointer to avoid moving the
++ * head of the list pointed to by sg as we wall the list.
++ */
+ for (i = 0; i < nents; i++) {
+- dma_map_sg(dev, sg, 1, dir);
+- sg = sg_next(sg);
++ dma_map_sg(dev, tsg, 1, dir);
++ tsg = sg_next(tsg);
+ }
+ } else {
+ dma_map_sg(dev, sg, nents, dir);
+ }
++
++ if ((dir == DMA_TO_DEVICE) || (dir == DMA_BIDIRECTIONAL))
++ dma_sync_sg_for_device(dev, sg, nents, dir);
++
+ return nents;
+ }
+
+@@ -105,6 +114,9 @@
+ unsigned int nents, enum dma_data_direction dir,
+ bool chained)
+ {
++ if ((dir == DMA_FROM_DEVICE) || (dir == DMA_BIDIRECTIONAL))
++ dma_sync_sg_for_cpu(dev, sg, nents, dir);
++
+ if (unlikely(chained)) {
+ int i;
+ for (i = 0; i < nents; i++) {
+@@ -116,3 +128,41 @@
+ }
+ return nents;
+ }
++
++/* Copy from len bytes of sg to dest, starting from beginning */
++static inline void sg_copy(u8 *dest, struct scatterlist *sg, unsigned int len)
++{
++ struct scatterlist *current_sg = sg;
++ int cpy_index = 0, next_cpy_index = current_sg->length;
++
++ while (next_cpy_index < len) {
++ memcpy(dest + cpy_index, (u8 *) sg_virt(current_sg),
++ current_sg->length);
++ current_sg = sg_next(current_sg);
++ cpy_index = next_cpy_index;
++ next_cpy_index += current_sg->length;
++ }
++ if (cpy_index < len)
++ memcpy(dest + cpy_index, (u8 *) sg_virt(current_sg),
++ len - cpy_index);
++}
++
++/* Copy sg data, from to_skip to end, to dest */
++static inline void sg_copy_part(u8 *dest, struct scatterlist *sg,
++ int to_skip, unsigned int end)
++{
++ struct scatterlist *current_sg = sg;
++ int sg_index, cpy_index;
++
++ sg_index = current_sg->length;
++ while (sg_index <= to_skip) {
++ current_sg = sg_next(current_sg);
++ sg_index += current_sg->length;
++ }
++ cpy_index = sg_index - to_skip;
++ memcpy(dest, (u8 *) sg_virt(current_sg) +
++ current_sg->length - cpy_index, cpy_index);
++ current_sg = sg_next(current_sg);
++ if (end - sg_index)
++ sg_copy(dest + cpy_index, current_sg, end - sg_index);
++}
+diff -Nur linux-4.1.3/drivers/crypto/caam/sm.h linux-xbian-imx6/drivers/crypto/caam/sm.h
+--- linux-4.1.3/drivers/crypto/caam/sm.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/crypto/caam/sm.h 2015-07-27 23:13:04.213947410 +0200
+@@ -0,0 +1,88 @@
++
++/*
++ * CAAM Secure Memory/Keywrap API Definitions
++ * Copyright (C) 2008-2013 Freescale Semiconductor, Inc.
++ */
++
++#ifndef SM_H
++#define SM_H
++
++
++/* Storage access permissions */
++#define SM_PERM_READ 0x01
++#define SM_PERM_WRITE 0x02
++#define SM_PERM_BLOB 0x03
++
++
++/* Keystore maintenance functions */
++void sm_init_keystore(struct device *dev);
++u32 sm_detect_keystore_units(struct device *dev);
++int sm_establish_keystore(struct device *dev, u32 unit);
++void sm_release_keystore(struct device *dev, u32 unit);
++void caam_sm_shutdown(struct platform_device *pdev);
++int caam_sm_example_init(struct platform_device *pdev);
++
++/* Keystore accessor functions */
++extern int sm_keystore_slot_alloc(struct device *dev, u32 unit, u32 size,
++ u32 *slot);
++extern int sm_keystore_slot_dealloc(struct device *dev, u32 unit, u32 slot);
++extern int sm_keystore_slot_load(struct device *dev, u32 unit, u32 slot,
++ const u8 *key_data, u32 key_length);
++extern int sm_keystore_slot_read(struct device *dev, u32 unit, u32 slot,
++ u32 key_length, u8 *key_data);
++extern int sm_keystore_slot_encapsulate(struct device *dev, u32 unit,
++ u32 inslot, u32 outslot, u16 secretlen,
++ u8 *keymod, u16 keymodlen);
++extern int sm_keystore_slot_decapsulate(struct device *dev, u32 unit,
++ u32 inslot, u32 outslot, u16 secretlen,
++ u8 *keymod, u16 keymodlen);
++
++/* Data structure to hold per-slot information */
++struct keystore_data_slot_info {
++ u8 allocated; /* Track slot assignments */
++ u32 key_length; /* Size of the key */
++};
++
++/* Data structure to hold keystore information */
++struct keystore_data {
++ void *base_address; /* Base of the Secure Partition */
++ u32 slot_count; /* Number of slots in the keystore */
++ struct keystore_data_slot_info *slot; /* Per-slot information */
++};
++
++/* store the detected attributes of a secure memory page */
++struct sm_page_descriptor {
++ u16 phys_pagenum; /* may be discontiguous */
++ u16 own_part; /* Owning partition */
++ void *pg_base; /* Calculated virtual address */
++ struct keystore_data *ksdata;
++};
++
++struct caam_drv_private_sm {
++ struct device *parentdev; /* this ends up as the controller */
++ struct device *smringdev; /* ring that owns this instance */
++ spinlock_t kslock ____cacheline_aligned;
++
++ /* Default parameters for geometry */
++ u32 max_pages; /* maximum pages this instance can support */
++ u32 top_partition; /* highest partition number in this instance */
++ u32 top_page; /* highest page number in this instance */
++ u32 page_size; /* page size */
++ u32 slot_size; /* selected size of each storage block */
++
++ /* Partition/Page Allocation Map */
++ u32 localpages; /* Number of pages we can access */
++ struct sm_page_descriptor *pagedesc; /* Allocated per-page */
++
++ /* Installed handlers for keystore access */
++ int (*data_init)(struct device *dev, u32 unit);
++ void (*data_cleanup)(struct device *dev, u32 unit);
++ int (*slot_alloc)(struct device *dev, u32 unit, u32 size, u32 *slot);
++ int (*slot_dealloc)(struct device *dev, u32 unit, u32 slot);
++ void *(*slot_get_address)(struct device *dev, u32 unit, u32 handle);
++ u32 (*slot_get_base)(struct device *dev, u32 unit, u32 handle);
++ u32 (*slot_get_offset)(struct device *dev, u32 unit, u32 handle);
++ u32 (*slot_get_slot_size)(struct device *dev, u32 unit, u32 handle);
++};
++
++#endif /* SM_H */
+diff -Nur linux-4.1.3/drivers/crypto/caam/sm_store.c linux-xbian-imx6/drivers/crypto/caam/sm_store.c
+--- linux-4.1.3/drivers/crypto/caam/sm_store.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/crypto/caam/sm_store.c 2015-07-27 23:13:04.213947410 +0200
+@@ -0,0 +1,896 @@
++
++/*
++ * CAAM Secure Memory Storage Interface
++ * Copyright (C) 2008-2013 Freescale Semiconductor, Inc.
++ *
++ * Loosely based on the SHW Keystore API for SCC/SCC2
++ * Experimental implementation and NOT intended for upstream use. Expect
++ * this interface to be amended significantly in the future once it becomes
++ * integrated into live applications.
++ *
++ * Known issues:
++ *
++ * - Executes one instance of an secure memory "driver". This is tied to the
++ * fact that job rings can't run as standalone instances in the present
++ * configuration.
++ *
++ * - It does not expose a userspace interface. The value of a userspace
++ * interface for access to secrets is a point for further architectural
++ * discussion.
++ *
++ * - Partition/permission management is not part of this interface. It
++ * depends on some level of "knowledge" agreed upon between bootloader,
++ * provisioning applications, and OS-hosted software (which uses this
++ * driver).
++ *
++ * - No means of identifying the location or purpose of secrets managed by
++ * this interface exists; "slot location" and format of a given secret
++ * needs to be agreed upon between bootloader, provisioner, and OS-hosted
++ * application.
++ */
++
++#include "compat.h"
++#include "regs.h"
++#include "jr.h"
++#include "desc.h"
++#include "intern.h"
++#include "error.h"
++#include "sm.h"
++
++#ifdef SM_DEBUG_CONT
++void sm_show_page(struct device *dev, struct sm_page_descriptor *pgdesc)
++{
++ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev);
++ u32 i, *smdata;
++
++ dev_info(dev, "physical page %d content at 0x%08x\n",
++ pgdesc->phys_pagenum, pgdesc->pg_base);
++ smdata = pgdesc->pg_base;
++ for (i = 0; i < (smpriv->page_size / sizeof(u32)); i += 4)
++ dev_info(dev, "[0x%08x] 0x%08x 0x%08x 0x%08x 0x%08x\n",
++ (u32)&smdata[i], smdata[i], smdata[i+1], smdata[i+2],
++ smdata[i+3]);
++}
++#endif
++
++/*
++ * Construct a secure memory blob encapsulation job descriptor
++ *
++ * - desc pointer to hold new (to be allocated) pointer to the generated
++ * descriptor for later use. Calling thread can kfree the
++ * descriptor after execution.
++ * - keymod Physical pointer to key modifier (contiguous piece).
++ * - keymodsz Size of key modifier in bytes (should normally be 8).
++ * - secretbuf Physical pointer (within an accessible secure memory page)
++ * of the secret to be encapsulated.
++ * - outbuf Physical pointer (within an accessible secure memory page)
++ * of the encapsulated output. This will be larger than the
++ * input secret because of the added encapsulation data.
++ * - secretsz Size of input secret, in bytes.
++ * - auth If nonzero, use AES-CCM for encapsulation, else use ECB
++ *
++ * Note: this uses 32-bit pointers at present
++ */
++#define INITIAL_DESCSZ 16 /* size of tmp buffer for descriptor const. */
++static int blob_encap_desc(u32 **desc, dma_addr_t keymod, u16 keymodsz,
++ dma_addr_t secretbuf, dma_addr_t outbuf,
++ u16 secretsz, bool auth)
++{
++ u32 *tdesc, tmpdesc[INITIAL_DESCSZ];
++ u16 dsize, idx;
++
++ memset(tmpdesc, 0, INITIAL_DESCSZ * sizeof(u32));
++ idx = 1;
++
++ /* Load key modifier */
++ tmpdesc[idx++] = CMD_LOAD | LDST_CLASS_2_CCB | LDST_SRCDST_BYTE_KEY |
++ ((12 << LDST_OFFSET_SHIFT) & LDST_OFFSET_MASK) |
++ (keymodsz & LDST_LEN_MASK);
++
++ tmpdesc[idx++] = (u32)keymod;
++
++ /* Encapsulate to secure memory */
++ tmpdesc[idx++] = CMD_SEQ_IN_PTR | secretsz;
++ tmpdesc[idx++] = (u32)secretbuf;
++
++ /* Add space for BKEK and MAC tag */
++ tmpdesc[idx++] = CMD_SEQ_IN_PTR | (secretsz + (32 + 16));
++
++ tmpdesc[idx++] = (u32)outbuf;
++ tmpdesc[idx] = CMD_OPERATION | OP_TYPE_ENCAP_PROTOCOL | OP_PCLID_BLOB |
++ OP_PCL_BLOB_PTXT_SECMEM;
++ if (auth)
++ tmpdesc[idx] |= OP_PCL_BLOB_EKT;
++
++ idx++;
++ tmpdesc[0] = CMD_DESC_HDR | HDR_ONE | (idx & HDR_DESCLEN_MASK);
++ dsize = idx * sizeof(u32);
++
++ tdesc = kmalloc(dsize, GFP_KERNEL | GFP_DMA);
++ if (tdesc == NULL)
++ return 0;
++
++ memcpy(tdesc, tmpdesc, dsize);
++ *desc = tdesc;
++ return dsize;
++}
++
++/*
++ * Construct a secure memory blob decapsulation job descriptor
++ *
++ * - desc pointer to hold new (to be allocated) pointer to the generated
++ * descriptor for later use. Calling thread can kfree the
++ * descriptor after execution.
++ * - keymod Physical pointer to key modifier (contiguous piece).
++ * - keymodsz Size of key modifier in bytes (should normally be 16).
++ * - blobbuf Physical pointer (within an accessible secure memory page)
++ * of the blob to be decapsulated.
++ * - outbuf Physical pointer (within an accessible secure memory page)
++ * of the decapsulated output.
++ * - secretsz Size of input blob, in bytes.
++ * - auth If nonzero, assume AES-CCM for decapsulation, else use ECB
++ *
++ * Note: this uses 32-bit pointers at present
++ */
++static int blob_decap_desc(u32 **desc, dma_addr_t keymod, u16 keymodsz,
++ dma_addr_t blobbuf, dma_addr_t outbuf,
++ u16 blobsz, bool auth)
++{
++ u32 *tdesc, tmpdesc[INITIAL_DESCSZ];
++ u16 dsize, idx;
++
++ memset(tmpdesc, 0, INITIAL_DESCSZ * sizeof(u32));
++ idx = 1;
++
++ /* Load key modifier */
++ tmpdesc[idx++] = CMD_LOAD | LDST_CLASS_2_CCB | LDST_SRCDST_BYTE_KEY |
++ ((12 << LDST_OFFSET_SHIFT) & LDST_OFFSET_MASK) |
++ (keymodsz & LDST_LEN_MASK);
++
++ tmpdesc[idx++] = (u32)keymod;
++
++ /* Compensate BKEK + MAC tag */
++ tmpdesc[idx++] = CMD_SEQ_IN_PTR | (blobsz + 32 + 16);
++
++ tmpdesc[idx++] = (u32)blobbuf;
++ tmpdesc[idx++] = CMD_SEQ_OUT_PTR | blobsz;
++ tmpdesc[idx++] = (u32)outbuf;
++
++ /* Decapsulate from secure memory partition to black blob */
++ tmpdesc[idx] = CMD_OPERATION | OP_TYPE_DECAP_PROTOCOL | OP_PCLID_BLOB |
++ OP_PCL_BLOB_PTXT_SECMEM | OP_PCL_BLOB_BLACK;
++ if (auth)
++ tmpdesc[idx] |= OP_PCL_BLOB_EKT;
++
++ idx++;
++ tmpdesc[0] = CMD_DESC_HDR | HDR_ONE | (idx & HDR_DESCLEN_MASK);
++ dsize = idx * sizeof(u32);
++
++ tdesc = kmalloc(dsize, GFP_KERNEL | GFP_DMA);
++ if (tdesc == NULL)
++ return 0;
++
++ memcpy(tdesc, tmpdesc, dsize);
++ *desc = tdesc;
++ return dsize;
++}
++
++/*
++ * Pseudo-synchronous ring access functions for carrying out key
++ * encapsulation and decapsulation
++ */
++
++struct sm_key_job_result {
++ int error;
++ struct completion completion;
++};
++
++void sm_key_job_done(struct device *dev, u32 *desc, u32 err, void *context)
++{
++ struct sm_key_job_result *res = context;
++
++ res->error = err; /* save off the error for postprocessing */
++ complete(&res->completion); /* mark us complete */
++}
++
++static int sm_key_job(struct device *ksdev, u32 *jobdesc)
++{
++ struct sm_key_job_result testres;
++ struct caam_drv_private_sm *kspriv;
++ int rtn = 0;
++
++ kspriv = dev_get_drvdata(ksdev);
++
++ init_completion(&testres.completion);
++
++ rtn = caam_jr_enqueue(kspriv->smringdev, jobdesc, sm_key_job_done,
++ &testres);
++ if (!rtn) {
++ wait_for_completion_interruptible(&testres.completion);
++ rtn = testres.error;
++ }
++ return rtn;
++}
++
++/*
++ * Following section establishes the default methods for keystore access
++ * They are NOT intended for use external to this module
++ *
++ * In the present version, these are the only means for the higher-level
++ * interface to deal with the mechanics of accessing the phyiscal keystore
++ */
++
++
++int slot_alloc(struct device *dev, u32 unit, u32 size, u32 *slot)
++{
++ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev);
++ struct keystore_data *ksdata = smpriv->pagedesc[unit].ksdata;
++ u32 i;
++#ifdef SM_DEBUG
++ dev_info(dev, "slot_alloc(): requesting slot for %d bytes\n", size);
++#endif
++
++ if (size > smpriv->slot_size)
++ return -EKEYREJECTED;
++
++ for (i = 0; i < ksdata->slot_count; i++) {
++ if (ksdata->slot[i].allocated == 0) {
++ ksdata->slot[i].allocated = 1;
++ (*slot) = i;
++#ifdef SM_DEBUG
++ dev_info(dev, "slot_alloc(): new slot %d allocated\n",
++ *slot);
++#endif
++ return 0;
++ }
++ }
++
++ return -ENOSPC;
++}
++EXPORT_SYMBOL(slot_alloc);
++
++int slot_dealloc(struct device *dev, u32 unit, u32 slot)
++{
++ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev);
++ struct keystore_data *ksdata = smpriv->pagedesc[unit].ksdata;
++ u8 __iomem *slotdata;
++
++#ifdef SM_DEBUG
++ dev_info(dev, "slot_dealloc(): releasing slot %d\n", slot);
++#endif
++ if (slot >= ksdata->slot_count)
++ return -EINVAL;
++ slotdata = ksdata->base_address + slot * smpriv->slot_size;
++
++ if (ksdata->slot[slot].allocated == 1) {
++ /* Forcibly overwrite the data from the keystore */
++ memset(ksdata->base_address + slot * smpriv->slot_size, 0,
++ smpriv->slot_size);
++
++ ksdata->slot[slot].allocated = 0;
++#ifdef SM_DEBUG
++ dev_info(dev, "slot_dealloc(): slot %d released\n", slot);
++#endif
++ return 0;
++ }
++
++ return -EINVAL;
++}
++EXPORT_SYMBOL(slot_dealloc);
++
++void *slot_get_address(struct device *dev, u32 unit, u32 slot)
++{
++ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev);
++ struct keystore_data *ksdata = smpriv->pagedesc[unit].ksdata;
++
++ if (slot >= ksdata->slot_count)
++ return NULL;
++
++#ifdef SM_DEBUG
++ dev_info(dev, "slot_get_address(): slot %d is 0x%08x\n", slot,
++ (u32)ksdata->base_address + slot * smpriv->slot_size);
++#endif
++
++ return ksdata->base_address + slot * smpriv->slot_size;
++}
++
++u32 slot_get_base(struct device *dev, u32 unit, u32 slot)
++{
++ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev);
++ struct keystore_data *ksdata = smpriv->pagedesc[unit].ksdata;
++
++ /*
++ * There could potentially be more than one secure partition object
++ * associated with this keystore. For now, there is just one.
++ */
++
++ (void)slot;
++
++#ifdef SM_DEBUG
++ dev_info(dev, "slot_get_base(): slot %d = 0x%08x\n",
++ slot, (u32)ksdata->base_address);
++#endif
++
++ return (u32)(ksdata->base_address);
++}
++
++u32 slot_get_offset(struct device *dev, u32 unit, u32 slot)
++{
++ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev);
++ struct keystore_data *ksdata = smpriv->pagedesc[unit].ksdata;
++
++ if (slot >= ksdata->slot_count)
++ return -EINVAL;
++
++#ifdef SM_DEBUG
++ dev_info(dev, "slot_get_offset(): slot %d = %d\n", slot,
++ slot * smpriv->slot_size);
++#endif
++
++ return slot * smpriv->slot_size;
++}
++
++u32 slot_get_slot_size(struct device *dev, u32 unit, u32 slot)
++{
++ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev);
++
++
++#ifdef SM_DEBUG
++ dev_info(dev, "slot_get_slot_size(): slot %d = %d\n", slot,
++ smpriv->slot_size);
++#endif
++ /* All slots are the same size in the default implementation */
++ return smpriv->slot_size;
++}
++
++
++
++int kso_init_data(struct device *dev, u32 unit)
++{
++ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev);
++ int retval = -EINVAL;
++ struct keystore_data *keystore_data = NULL;
++ u32 slot_count;
++ u32 keystore_data_size;
++
++ /*
++ * Calculate the required size of the keystore data structure, based
++ * on the number of keys that can fit in the partition.
++ */
++ slot_count = smpriv->page_size / smpriv->slot_size;
++#ifdef SM_DEBUG
++ dev_info(dev, "kso_init_data: %d slots initializing\n", slot_count);
++#endif
++
++ keystore_data_size = sizeof(struct keystore_data) +
++ slot_count *
++ sizeof(struct keystore_data_slot_info);
++
++ keystore_data = kzalloc(keystore_data_size, GFP_KERNEL);
++
++ if (keystore_data == NULL) {
++ retval = -ENOSPC;
++ goto out;
++ }
++
++#ifdef SM_DEBUG
++ dev_info(dev, "kso_init_data: keystore data size = %d\n",
++ keystore_data_size);
++#endif
++
++ /*
++ * Place the slot information structure directly after the keystore data
++ * structure.
++ */
++ keystore_data->slot = (struct keystore_data_slot_info *)
++ (keystore_data + 1);
++ keystore_data->slot_count = slot_count;
++
++ smpriv->pagedesc[unit].ksdata = keystore_data;
++ smpriv->pagedesc[unit].ksdata->base_address =
++ smpriv->pagedesc[unit].pg_base;
++
++ retval = 0;
++
++out:
++ if (retval != 0)
++ if (keystore_data != NULL)
++ kfree(keystore_data);
++
++
++ return retval;
++}
++
++void kso_cleanup_data(struct device *dev, u32 unit)
++{
++ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev);
++ struct keystore_data *keystore_data = NULL;
++
++ if (smpriv->pagedesc[unit].ksdata != NULL)
++ keystore_data = smpriv->pagedesc[unit].ksdata;
++
++ /* Release the allocated keystore management data */
++ kfree(smpriv->pagedesc[unit].ksdata);
++
++ return;
++}
++
++
++
++/*
++ * Keystore management section
++ */
++
++void sm_init_keystore(struct device *dev)
++{
++ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev);
++
++ smpriv->data_init = kso_init_data;
++ smpriv->data_cleanup = kso_cleanup_data;
++ smpriv->slot_alloc = slot_alloc;
++ smpriv->slot_dealloc = slot_dealloc;
++ smpriv->slot_get_address = slot_get_address;
++ smpriv->slot_get_base = slot_get_base;
++ smpriv->slot_get_offset = slot_get_offset;
++ smpriv->slot_get_slot_size = slot_get_slot_size;
++#ifdef SM_DEBUG
++ dev_info(dev, "sm_init_keystore(): handlers installed\n");
++#endif
++}
++EXPORT_SYMBOL(sm_init_keystore);
++
++/* Return available pages/units */
++u32 sm_detect_keystore_units(struct device *dev)
++{
++ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev);
++
++ return smpriv->localpages;
++}
++EXPORT_SYMBOL(sm_detect_keystore_units);
++
++/*
++ * Do any keystore specific initializations
++ */
++int sm_establish_keystore(struct device *dev, u32 unit)
++{
++ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev);
++
++#ifdef SM_DEBUG
++ dev_info(dev, "sm_establish_keystore(): unit %d initializing\n", unit);
++#endif
++
++ if (smpriv->data_init == NULL)
++ return -EINVAL;
++
++ /* Call the data_init function for any user setup */
++ return smpriv->data_init(dev, unit);
++}
++EXPORT_SYMBOL(sm_establish_keystore);
++
++void sm_release_keystore(struct device *dev, u32 unit)
++{
++ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev);
++
++#ifdef SM_DEBUG
++ dev_info(dev, "sm_establish_keystore(): unit %d releasing\n", unit);
++#endif
++ if ((smpriv != NULL) && (smpriv->data_cleanup != NULL))
++ smpriv->data_cleanup(dev, unit);
++
++ return;
++}
++EXPORT_SYMBOL(sm_release_keystore);
++
++/*
++ * Subsequent interfacce (sm_keystore_*) forms the accessor interfacce to
++ * the keystore
++ */
++int sm_keystore_slot_alloc(struct device *dev, u32 unit, u32 size, u32 *slot)
++{
++ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev);
++ int retval = -EINVAL;
++
++ spin_lock(&smpriv->kslock);
++
++ if ((smpriv->slot_alloc == NULL) ||
++ (smpriv->pagedesc[unit].ksdata == NULL))
++ goto out;
++
++ retval = smpriv->slot_alloc(dev, unit, size, slot);
++
++out:
++ spin_unlock(&smpriv->kslock);
++ return retval;
++}
++EXPORT_SYMBOL(sm_keystore_slot_alloc);
++
++int sm_keystore_slot_dealloc(struct device *dev, u32 unit, u32 slot)
++{
++ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev);
++ int retval = -EINVAL;
++
++ spin_lock(&smpriv->kslock);
++
++ if ((smpriv->slot_alloc == NULL) ||
++ (smpriv->pagedesc[unit].ksdata == NULL))
++ goto out;
++
++ retval = smpriv->slot_dealloc(dev, unit, slot);
++out:
++ spin_unlock(&smpriv->kslock);
++ return retval;
++}
++EXPORT_SYMBOL(sm_keystore_slot_dealloc);
++
++int sm_keystore_slot_load(struct device *dev, u32 unit, u32 slot,
++ const u8 *key_data, u32 key_length)
++{
++ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev);
++ int retval = -EINVAL;
++ u32 slot_size;
++ u32 i;
++ u8 __iomem *slot_location;
++
++ spin_lock(&smpriv->kslock);
++
++ slot_size = smpriv->slot_get_slot_size(dev, unit, slot);
++
++ if (key_length > slot_size) {
++ retval = -EFBIG;
++ goto out;
++ }
++
++ slot_location = smpriv->slot_get_address(dev, unit, slot);
++
++ for (i = 0; i < key_length; i++)
++ slot_location[i] = key_data[i];
++
++ retval = 0;
++
++out:
++ spin_unlock(&smpriv->kslock);
++ return retval;
++}
++EXPORT_SYMBOL(sm_keystore_slot_load);
++
++int sm_keystore_slot_read(struct device *dev, u32 unit, u32 slot,
++ u32 key_length, u8 *key_data)
++{
++ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev);
++ int retval = -EINVAL;
++ u8 __iomem *slot_addr;
++ u32 slot_size;
++
++ spin_lock(&smpriv->kslock);
++
++ slot_addr = smpriv->slot_get_address(dev, unit, slot);
++ slot_size = smpriv->slot_get_slot_size(dev, unit, slot);
++
++ if (key_length > slot_size) {
++ retval = -EKEYREJECTED;
++ goto out;
++ }
++
++ memcpy(key_data, slot_addr, key_length);
++ retval = 0;
++
++out:
++ spin_unlock(&smpriv->kslock);
++ return retval;
++}
++EXPORT_SYMBOL(sm_keystore_slot_read);
++
++int sm_keystore_slot_encapsulate(struct device *dev, u32 unit, u32 inslot,
++ u32 outslot, u16 secretlen, u8 *keymod,
++ u16 keymodlen)
++{
++ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev);
++ int retval = 0;
++ u32 slot_length, dsize, jstat;
++ u32 __iomem *encapdesc = NULL;
++ u8 __iomem *lkeymod, *inpslotaddr, *outslotaddr;
++ dma_addr_t keymod_dma;
++
++ /* Ensure that the full blob will fit in the key slot */
++ slot_length = smpriv->slot_get_slot_size(dev, unit, outslot);
++ if ((secretlen + 48) > slot_length)
++ goto out;
++
++ /* Get the base addresses of both keystore slots */
++ inpslotaddr = (u8 *)smpriv->slot_get_address(dev, unit, inslot);
++ outslotaddr = (u8 *)smpriv->slot_get_address(dev, unit, outslot);
++
++ /* Build the key modifier */
++ lkeymod = kmalloc(keymodlen, GFP_KERNEL | GFP_DMA);
++ memcpy(lkeymod, keymod, keymodlen);
++ keymod_dma = dma_map_single(dev, lkeymod, keymodlen, DMA_TO_DEVICE);
++ dma_sync_single_for_device(dev, keymod_dma, keymodlen, DMA_TO_DEVICE);
++
++ /* Build the encapsulation job descriptor */
++ dsize = blob_encap_desc(&encapdesc, keymod_dma, keymodlen,
++ __pa(inpslotaddr), __pa(outslotaddr),
++ secretlen, 0);
++ if (!dsize) {
++ dev_err(dev, "can't alloc an encap descriptor\n");
++ retval = -ENOMEM;
++ goto out;
++ }
++ jstat = sm_key_job(dev, encapdesc);
++
++ dma_unmap_single(dev, keymod_dma, keymodlen, DMA_TO_DEVICE);
++ kfree(encapdesc);
++
++out:
++ return retval;
++
++}
++EXPORT_SYMBOL(sm_keystore_slot_encapsulate);
++
++int sm_keystore_slot_decapsulate(struct device *dev, u32 unit, u32 inslot,
++ u32 outslot, u16 secretlen, u8 *keymod,
++ u16 keymodlen)
++{
++ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev);
++ int retval = 0;
++ u32 slot_length, dsize, jstat;
++ u32 __iomem *decapdesc = NULL;
++ u8 __iomem *lkeymod, *inpslotaddr, *outslotaddr;
++ dma_addr_t keymod_dma;
++
++ /* Ensure that the decap data will fit in the key slot */
++ slot_length = smpriv->slot_get_slot_size(dev, unit, outslot);
++ if (secretlen > slot_length)
++ goto out;
++
++ /* Get the base addresses of both keystore slots */
++ inpslotaddr = (u8 *)smpriv->slot_get_address(dev, unit, inslot);
++ outslotaddr = (u8 *)smpriv->slot_get_address(dev, unit, outslot);
++
++ /* Build the key modifier */
++ lkeymod = kmalloc(keymodlen, GFP_KERNEL | GFP_DMA);
++ memcpy(lkeymod, keymod, keymodlen);
++ keymod_dma = dma_map_single(dev, lkeymod, keymodlen, DMA_TO_DEVICE);
++ dma_sync_single_for_device(dev, keymod_dma, keymodlen, DMA_TO_DEVICE);
++
++ /* Build the decapsulation job descriptor */
++ dsize = blob_decap_desc(&decapdesc, keymod_dma, keymodlen,
++ __pa(inpslotaddr), __pa(outslotaddr),
++ secretlen, 0);
++ if (!dsize) {
++ dev_err(dev, "can't alloc a decap descriptor\n");
++ retval = -ENOMEM;
++ goto out;
++ }
++ jstat = sm_key_job(dev, decapdesc);
++
++ dma_unmap_single(dev, keymod_dma, keymodlen, DMA_TO_DEVICE);
++ kfree(decapdesc);
++
++out:
++ return retval;
++
++}
++EXPORT_SYMBOL(sm_keystore_slot_decapsulate);
++
++
++/*
++ * Initialization/shutdown subsystem
++ * Assumes statically-invoked startup/shutdown from the controller driver
++ * for the present time, to be reworked when a device tree becomes
++ * available. This code will not modularize in present form.
++ *
++ * Also, simply uses ring 0 for execution at the present
++ */
++
++int caam_sm_startup(struct platform_device *pdev)
++{
++ struct device *ctrldev, *smdev;
++ struct caam_drv_private *ctrlpriv;
++ struct caam_drv_private_sm *smpriv;
++ struct caam_drv_private_jr *jrpriv; /* need this for reg page */
++ struct platform_device *sm_pdev;
++ struct sm_page_descriptor *lpagedesc;
++ u32 page, pgstat, lpagect, detectedpage;
++
++ struct device_node *np;
++ ctrldev = &pdev->dev;
++ ctrlpriv = dev_get_drvdata(ctrldev);
++
++ /*
++ * Set up the private block for secure memory
++ * Only one instance is possible
++ */
++ smpriv = kzalloc(sizeof(struct caam_drv_private_sm), GFP_KERNEL);
++ if (smpriv == NULL) {
++ dev_err(ctrldev, "can't alloc private mem for secure memory\n");
++ return -ENOMEM;
++ }
++ smpriv->parentdev = ctrldev; /* copy of parent dev is handy */
++
++ /* Create the dev */
++#ifdef CONFIG_OF
++ np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-caam-sm");
++ sm_pdev = of_platform_device_create(np, "caam_sm", ctrldev);
++#else
++ sm_pdev = platform_device_register_data(ctrldev, "caam_sm", 0,
++ smpriv,
++ sizeof(struct caam_drv_private_sm));
++#endif
++ if (sm_pdev == NULL) {
++ kfree(smpriv);
++ return -EINVAL;
++ }
++ smdev = &sm_pdev->dev;
++ dev_set_drvdata(smdev, smpriv);
++ ctrlpriv->smdev = smdev;
++
++ /*
++ * Collect configuration limit data for reference
++ * This batch comes from the partition data/vid registers in perfmon
++ */
++ smpriv->max_pages = ((rd_reg32(&ctrlpriv->ctrl->perfmon.smpart)
++ & SMPART_MAX_NUMPG_MASK) >>
++ SMPART_MAX_NUMPG_SHIFT) + 1;
++ smpriv->top_partition = ((rd_reg32(&ctrlpriv->ctrl->perfmon.smpart)
++ & SMPART_MAX_PNUM_MASK) >>
++ SMPART_MAX_PNUM_SHIFT) + 1;
++ smpriv->top_page = ((rd_reg32(&ctrlpriv->ctrl->perfmon.smpart)
++ & SMPART_MAX_PG_MASK) >> SMPART_MAX_PG_SHIFT) + 1;
++ smpriv->page_size = 1024 << ((rd_reg32(&ctrlpriv->ctrl->perfmon.smvid)
++ & SMVID_PG_SIZE_MASK) >> SMVID_PG_SIZE_SHIFT);
++ smpriv->slot_size = 1 << CONFIG_CRYPTO_DEV_FSL_CAAM_SM_SLOTSIZE;
++
++#ifdef SM_DEBUG
++ dev_info(smdev, "max pages = %d, top partition = %d\n",
++ smpriv->max_pages, smpriv->top_partition);
++ dev_info(smdev, "top page = %d, page size = %d (total = %d)\n",
++ smpriv->top_page, smpriv->page_size,
++ smpriv->top_page * smpriv->page_size);
++ dev_info(smdev, "selected slot size = %d\n", smpriv->slot_size);
++#endif
++
++ /*
++ * Now probe for partitions/pages to which we have access. Note that
++ * these have likely been set up by a bootloader or platform
++ * provisioning application, so we have to assume that we "inherit"
++ * a configuration and work within the constraints of what it might be.
++ *
++ * Assume use of the zeroth ring in the present iteration (until
++ * we can divorce the controller and ring drivers, and then assign
++ * an SM instance to any ring instance).
++ */
++ smpriv->smringdev = ctrlpriv->jrdev[0];
++ jrpriv = dev_get_drvdata(smpriv->smringdev);
++ lpagect = 0;
++ lpagedesc = kzalloc(sizeof(struct sm_page_descriptor)
++ * smpriv->max_pages, GFP_KERNEL);
++ if (lpagedesc == NULL) {
++ kfree(smpriv);
++ return -ENOMEM;
++ }
++
++ for (page = 0; page < smpriv->max_pages; page++) {
++ wr_reg32(&jrpriv->rregs->sm_cmd,
++ ((page << SMC_PAGE_SHIFT) & SMC_PAGE_MASK) |
++ (SMC_CMD_PAGE_INQUIRY & SMC_CMD_MASK));
++ pgstat = rd_reg32(&jrpriv->rregs->sm_status);
++ if (((pgstat & SMCS_PGWON_MASK) >> SMCS_PGOWN_SHIFT)
++ == SMCS_PGOWN_OWNED) { /* our page? */
++ lpagedesc[page].phys_pagenum =
++ (pgstat & SMCS_PAGE_MASK) >> SMCS_PAGE_SHIFT;
++ lpagedesc[page].own_part =
++ (pgstat & SMCS_PART_SHIFT) >> SMCS_PART_MASK;
++ lpagedesc[page].pg_base = ctrlpriv->sm_base +
++ ((smpriv->page_size * page) / sizeof(u32));
++ lpagect++;
++#ifdef SM_DEBUG
++ dev_info(smdev,
++ "physical page %d, owning partition = %d\n",
++ lpagedesc[page].phys_pagenum,
++ lpagedesc[page].own_part);
++#endif
++ }
++ }
++
++ smpriv->pagedesc = kzalloc(sizeof(struct sm_page_descriptor) * lpagect,
++ GFP_KERNEL);
++ if (smpriv->pagedesc == NULL) {
++ kfree(lpagedesc);
++ kfree(smpriv);
++ return -ENOMEM;
++ }
++ smpriv->localpages = lpagect;
++
++ detectedpage = 0;
++ for (page = 0; page < smpriv->max_pages; page++) {
++ if (lpagedesc[page].pg_base != NULL) { /* e.g. live entry */
++ memcpy(&smpriv->pagedesc[detectedpage],
++ &lpagedesc[page],
++ sizeof(struct sm_page_descriptor));
++#ifdef SM_DEBUG_CONT
++ sm_show_page(smdev, &smpriv->pagedesc[detectedpage]);
++#endif
++ detectedpage++;
++ }
++ }
++
++ kfree(lpagedesc);
++
++ sm_init_keystore(smdev);
++
++ return 0;
++}
++
++void caam_sm_shutdown(struct platform_device *pdev)
++{
++ struct device *ctrldev, *smdev;
++ struct caam_drv_private *priv;
++ struct caam_drv_private_sm *smpriv;
++
++ ctrldev = &pdev->dev;
++ priv = dev_get_drvdata(ctrldev);
++ smdev = priv->smdev;
++ smpriv = dev_get_drvdata(smdev);
++
++ kfree(smpriv->pagedesc);
++ kfree(smpriv);
++}
++EXPORT_SYMBOL(caam_sm_shutdown);
++#ifdef CONFIG_OF
++static void __exit caam_sm_exit(void)
++{
++ struct device_node *dev_node;
++ struct platform_device *pdev;
++
++ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
++ if (!dev_node) {
++ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec4.0");
++ if (!dev_node)
++ return;
++ }
++
++ pdev = of_find_device_by_node(dev_node);
++ if (!pdev)
++ return;
++
++ of_node_put(dev_node);
++
++ caam_sm_shutdown(pdev);
++
++ return;
++}
++
++static int __init caam_sm_init(void)
++{
++ struct device_node *dev_node;
++ struct platform_device *pdev;
++
++ /*
++ * Do of_find_compatible_node() then of_find_device_by_node()
++ * once a functional device tree is available
++ */
++ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
++ if (!dev_node) {
++ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec4.0");
++ if (!dev_node)
++ return -ENODEV;
++ }
++
++ pdev = of_find_device_by_node(dev_node);
++ if (!pdev)
++ return -ENODEV;
++
++ of_node_get(dev_node);
++
++ caam_sm_startup(pdev);
++
++ return 0;
++}
++
++module_init(caam_sm_init);
++module_exit(caam_sm_exit);
++
++MODULE_LICENSE("Dual BSD/GPL");
++MODULE_DESCRIPTION("FSL CAAM Secure Memory / Keystore");
++MODULE_AUTHOR("Freescale Semiconductor - NMSG/MAD");
++#endif
+diff -Nur linux-4.1.3/drivers/crypto/caam/sm_test.c linux-xbian-imx6/drivers/crypto/caam/sm_test.c
+--- linux-4.1.3/drivers/crypto/caam/sm_test.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/crypto/caam/sm_test.c 2015-07-27 23:13:04.213947410 +0200
+@@ -0,0 +1,844 @@
++/*
++ * Secure Memory / Keystore Exemplification Module
++ * Copyright (C) 2013 Freescale Semiconductor, Inc. All Rights Reserved
++ *
++ * Serves as a functional example, and as a self-contained unit test for
++ * the functionality contained in sm_store.c.
++ *
++ * The example function, caam_sm_example_init(), runs a thread that:
++ *
++ * - initializes a set of fixed keys
++ * - stores one copy in clear buffers
++ * - stores them again in secure memory
++ * - extracts stored keys back out for use
++ * - intializes 3 data buffers for a test:
++ * (1) containing cleartext
++ * (2) to hold ciphertext encrypted with an extracted black key
++ * (3) to hold extracted cleartext decrypted with an equivalent clear key
++ *
++ * The function then builds simple job descriptors that reference the key
++ * material and buffers as initialized, and executes an encryption job
++ * with a black key, and a decryption job using a the same key held in the
++ * clear. The output of the decryption job is compared to the original
++ * cleartext; if they don't compare correctly, one can assume a key problem
++ * exists, where the function will exit with an error.
++ *
++ * This module can use a substantial amount of refactoring, which may occur
++ * after the API gets some mileage. Furthermore, expect this module to
++ * eventually disappear once the API is integrated into "real" software.
++ */
++
++#include "compat.h"
++#include "intern.h"
++#include "desc.h"
++#include "error.h"
++#include "jr.h"
++#include "sm.h"
++
++static u8 skeymod[] = {
++ 0x0f, 0x0e, 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08,
++ 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00
++};
++static u8 symkey[] = {
++ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
++ 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
++ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
++ 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f
++};
++
++static u8 symdata[] = {
++ 0x00, 0x01, 0x02, 0x03, 0x04, 0x0f, 0x06, 0x07,
++ 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
++ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
++ 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f,
++ 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
++ 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
++ 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
++ 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
++ 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
++ 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
++ 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
++ 0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
++ 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
++ 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
++ 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
++ 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f,
++ 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
++ 0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f,
++ 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97,
++ 0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f,
++ 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7,
++ 0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf,
++ 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7,
++ 0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf,
++ 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7,
++ 0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf,
++ 0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7,
++ 0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf,
++ 0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7,
++ 0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef,
++ 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7,
++ 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff
++};
++
++static int mk_job_desc(u32 *desc, dma_addr_t key, u16 keysz, dma_addr_t indata,
++ dma_addr_t outdata, u16 sz, u32 cipherdir, u32 keymode)
++{
++ desc[1] = CMD_KEY | CLASS_1 | (keysz & KEY_LENGTH_MASK) | keymode;
++ desc[2] = (u32)key;
++ desc[3] = CMD_OPERATION | OP_TYPE_CLASS1_ALG | OP_ALG_AAI_ECB |
++ cipherdir;
++ desc[4] = CMD_FIFO_LOAD | FIFOLD_CLASS_CLASS1 |
++ FIFOLD_TYPE_MSG | FIFOLD_TYPE_LAST1 | sz;
++ desc[5] = (u32)indata;
++ desc[6] = CMD_FIFO_STORE | FIFOST_TYPE_MESSAGE_DATA | sz;
++ desc[7] = (u32)outdata;
++
++ desc[0] = CMD_DESC_HDR | HDR_ONE | (8 & HDR_DESCLEN_MASK);
++ return 8 * sizeof(u32);
++}
++
++struct exec_test_result {
++ int error;
++ struct completion completion;
++};
++
++void exec_test_done(struct device *dev, u32 *desc, u32 err, void *context)
++{
++ struct exec_test_result *res = context;
++
++ if (err) {
++ char tmp[CAAM_ERROR_STR_MAX];
++ dev_err(dev, "%08x: %s\n", err, caam_jr_strstatus(tmp, err));
++ }
++
++ res->error = err;
++ complete(&res->completion);
++}
++
++static int exec_test_job(struct device *ksdev, u32 *jobdesc)
++{
++ struct exec_test_result testres;
++ struct caam_drv_private_sm *kspriv;
++ int rtn = 0;
++
++ kspriv = dev_get_drvdata(ksdev);
++
++ init_completion(&testres.completion);
++
++ rtn = caam_jr_enqueue(kspriv->smringdev, jobdesc, exec_test_done,
++ &testres);
++ if (!rtn) {
++ wait_for_completion_interruptible(&testres.completion);
++ rtn = testres.error;
++ }
++ return rtn;
++}
++
++
++int caam_sm_example_init(struct platform_device *pdev)
++{
++ struct device *ctrldev, *ksdev;
++ struct caam_drv_private *ctrlpriv;
++ struct caam_drv_private_sm *kspriv;
++ u32 unit, units, jdescsz;
++ int stat, jstat, rtnval = 0;
++ u8 __iomem *syminp, *symint, *symout = NULL;
++ dma_addr_t syminp_dma, symint_dma, symout_dma;
++ u8 __iomem *black_key_des, *black_key_aes128;
++ u8 __iomem *black_key_aes256;
++ dma_addr_t black_key_des_dma, black_key_aes128_dma;
++ dma_addr_t black_key_aes256_dma;
++ u8 __iomem *clear_key_des, *clear_key_aes128, *clear_key_aes256;
++ dma_addr_t clear_key_des_dma, clear_key_aes128_dma;
++ dma_addr_t clear_key_aes256_dma;
++ u32 __iomem *jdesc;
++ u32 keyslot_des, keyslot_aes128, keyslot_aes256 = 0;
++
++ jdesc = NULL;
++ black_key_des = black_key_aes128 = black_key_aes256 = NULL;
++ clear_key_des = clear_key_aes128 = clear_key_aes256 = NULL;
++
++ /* We can lose this cruft once we can get a pdev by name */
++ ctrldev = &pdev->dev;
++ ctrlpriv = dev_get_drvdata(ctrldev);
++ ksdev = ctrlpriv->smdev;
++ kspriv = dev_get_drvdata(ksdev);
++ if (kspriv == NULL)
++ return -ENODEV;
++
++ /* Now that we have the dev for the single SM instance, connect */
++#ifdef SM_TEST_DETAIL
++ dev_info(ksdev, "caam_sm_test_init() running\n");
++#endif
++ /* Probe to see what keystores are available to us */
++ units = sm_detect_keystore_units(ksdev);
++ if (!units)
++ dev_err(ksdev, "caam_sm_test: no keystore units available\n");
++
++ /*
++ * MX6 bootloader stores some stuff in unit 0, so let's
++ * use 1 or above
++ */
++ if (units < 2) {
++ dev_err(ksdev, "caam_sm_test: insufficient keystore units\n");
++ return -ENODEV;
++ }
++ unit = 1;
++
++#ifdef SM_TEST_DETAIL
++ dev_info(ksdev, "caam_sm_test: %d keystore units available\n", units);
++#endif
++
++ /* Initialize/Establish Keystore */
++ sm_establish_keystore(ksdev, unit); /* Initalize store in #1 */
++
++ /*
++ * Top of main test thread
++ */
++
++ /* Allocate test data blocks (input, intermediate, output) */
++ syminp = kmalloc(256, GFP_KERNEL | GFP_DMA);
++ symint = kmalloc(256, GFP_KERNEL | GFP_DMA);
++ symout = kmalloc(256, GFP_KERNEL | GFP_DMA);
++ if ((syminp == NULL) || (symint == NULL) || (symout == NULL)) {
++ rtnval = -ENOMEM;
++ dev_err(ksdev, "caam_sm_test: can't get test data buffers\n");
++ goto freemem;
++ }
++
++ /* Allocate storage for 3 black keys: encapsulated 8, 16, 32 */
++ black_key_des = kmalloc(16, GFP_KERNEL | GFP_DMA); /* padded to 16... */
++ black_key_aes128 = kmalloc(16, GFP_KERNEL | GFP_DMA);
++ black_key_aes256 = kmalloc(16, GFP_KERNEL | GFP_DMA);
++ if ((black_key_des == NULL) || (black_key_aes128 == NULL) ||
++ (black_key_aes256 == NULL)) {
++ rtnval = -ENOMEM;
++ dev_err(ksdev, "caam_sm_test: can't black key buffers\n");
++ goto freemem;
++ }
++
++ clear_key_des = kmalloc(8, GFP_KERNEL | GFP_DMA);
++ clear_key_aes128 = kmalloc(16, GFP_KERNEL | GFP_DMA);
++ clear_key_aes256 = kmalloc(32, GFP_KERNEL | GFP_DMA);
++ if ((clear_key_des == NULL) || (clear_key_aes128 == NULL) ||
++ (clear_key_aes256 == NULL)) {
++ rtnval = -ENOMEM;
++ dev_err(ksdev, "caam_sm_test: can't get clear key buffers\n");
++ goto freemem;
++ }
++
++ /* Allocate storage for job descriptor */
++ jdesc = kmalloc(8 * sizeof(u32), GFP_KERNEL | GFP_DMA);
++ if (jdesc == NULL) {
++ rtnval = -ENOMEM;
++ dev_err(ksdev, "caam_sm_test: can't get descriptor buffers\n");
++ goto freemem;
++ }
++
++#ifdef SM_TEST_DETAIL
++ dev_info(ksdev, "caam_sm_test: all buffers allocated\n");
++#endif
++
++ /* Load up input data block, clear outputs */
++ memcpy(syminp, symdata, 256);
++ memset(symint, 0, 256);
++ memset(symout, 0, 256);
++#ifdef SM_TEST_DETAIL
++ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \
++ "0x%02x 0x%02x 0x%02x 0x%02x\n",
++ syminp[0], syminp[1], syminp[2], syminp[3],
++ syminp[4], syminp[5], syminp[6], syminp[7]);
++ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \
++ "0x%02x 0x%02x 0x%02x 0x%02x\n",
++ symint[0], symint[1], symint[2], symint[3],
++ symint[4], symint[5], symint[6], symint[7]);
++ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \
++ "0x%02x 0x%02x 0x%02x 0x%02x\n",
++ symout[0], symout[1], symout[2], symout[3],
++ symout[4], symout[5], symout[6], symout[7]);
++
++ dev_info(ksdev, "caam_sm_test: data buffers initialized\n");
++#endif
++
++ /* Load up clear keys */
++ memcpy(clear_key_des, symkey, 8);
++ memcpy(clear_key_aes128, symkey, 16);
++ memcpy(clear_key_aes256, symkey, 32);
++
++#ifdef SM_TEST_DETAIL
++ dev_info(ksdev, "caam_sm_test: all clear keys loaded\n");
++#endif
++
++ /*
++ * Place clear keys in keystore.
++ * All the interesting stuff happens here.
++ */
++ /* 8 bit DES key */
++ stat = sm_keystore_slot_alloc(ksdev, unit, 8, &keyslot_des);
++ if (stat)
++ goto freemem;
++#ifdef SM_TEST_DETAIL
++ dev_info(ksdev, "caam_sm_test: 8 byte key slot in %d\n", keyslot_des);
++#endif
++ stat = sm_keystore_slot_load(ksdev, unit, keyslot_des, clear_key_des,
++ 8);
++ if (stat) {
++#ifdef SM_TEST_DETAIL
++ dev_info(ksdev, "caam_sm_test: can't load 8 byte key in %d\n",
++ keyslot_des);
++#endif
++ sm_keystore_slot_dealloc(ksdev, unit, keyslot_des);
++ goto freemem;
++ }
++
++ /* 16 bit AES key */
++ stat = sm_keystore_slot_alloc(ksdev, unit, 16, &keyslot_aes128);
++ if (stat) {
++ sm_keystore_slot_dealloc(ksdev, unit, keyslot_des);
++ goto freemem;
++ }
++#ifdef SM_TEST_DETAIL
++ dev_info(ksdev, "caam_sm_test: 16 byte key slot in %d\n",
++ keyslot_aes128);
++#endif
++ stat = sm_keystore_slot_load(ksdev, unit, keyslot_aes128,
++ clear_key_aes128, 16);
++ if (stat) {
++#ifdef SM_TEST_DETAIL
++ dev_info(ksdev, "caam_sm_test: can't load 16 byte key in %d\n",
++ keyslot_aes128);
++#endif
++ sm_keystore_slot_dealloc(ksdev, unit, keyslot_aes128);
++ sm_keystore_slot_dealloc(ksdev, unit, keyslot_des);
++ goto freemem;
++ }
++
++ /* 32 bit AES key */
++ stat = sm_keystore_slot_alloc(ksdev, unit, 32, &keyslot_aes256);
++ if (stat) {
++ sm_keystore_slot_dealloc(ksdev, unit, keyslot_aes128);
++ sm_keystore_slot_dealloc(ksdev, unit, keyslot_des);
++ goto freemem;
++ }
++#ifdef SM_TEST_DETAIL
++ dev_info(ksdev, "caam_sm_test: 32 byte key slot in %d\n",
++ keyslot_aes256);
++#endif
++ stat = sm_keystore_slot_load(ksdev, unit, keyslot_aes256,
++ clear_key_aes256, 32);
++ if (stat) {
++#ifdef SM_TEST_DETAIL
++ dev_info(ksdev, "caam_sm_test: can't load 32 byte key in %d\n",
++ keyslot_aes128);
++#endif
++ sm_keystore_slot_dealloc(ksdev, unit, keyslot_aes256);
++ sm_keystore_slot_dealloc(ksdev, unit, keyslot_aes128);
++ sm_keystore_slot_dealloc(ksdev, unit, keyslot_des);
++ goto freemem;
++ }
++
++ /* Encapsulate all keys as SM blobs */
++ stat = sm_keystore_slot_encapsulate(ksdev, unit, keyslot_des,
++ keyslot_des, 8, skeymod, 8);
++ if (stat) {
++ dev_info(ksdev, "caam_sm_test: can't encapsulate DES key\n");
++ goto freekeys;
++ }
++
++ stat = sm_keystore_slot_encapsulate(ksdev, unit, keyslot_aes128,
++ keyslot_aes128, 16, skeymod, 8);
++ if (stat) {
++ dev_info(ksdev, "caam_sm_test: can't encapsulate AES128 key\n");
++ goto freekeys;
++ }
++
++ stat = sm_keystore_slot_encapsulate(ksdev, unit, keyslot_aes256,
++ keyslot_aes256, 32, skeymod, 8);
++ if (stat) {
++ dev_info(ksdev, "caam_sm_test: can't encapsulate AES256 key\n");
++ goto freekeys;
++ }
++
++ /* Now decapsulate as black key blobs */
++ stat = sm_keystore_slot_decapsulate(ksdev, unit, keyslot_des,
++ keyslot_des, 8, skeymod, 8);
++ if (stat) {
++ dev_info(ksdev, "caam_sm_test: can't decapsulate DES key\n");
++ goto freekeys;
++ }
++
++ stat = sm_keystore_slot_decapsulate(ksdev, unit, keyslot_aes128,
++ keyslot_aes128, 16, skeymod, 8);
++ if (stat) {
++ dev_info(ksdev, "caam_sm_test: can't decapsulate AES128 key\n");
++ goto freekeys;
++ }
++
++ stat = sm_keystore_slot_decapsulate(ksdev, unit, keyslot_aes256,
++ keyslot_aes256, 32, skeymod, 8);
++ if (stat) {
++ dev_info(ksdev, "caam_sm_test: can't decapsulate AES128 key\n");
++ goto freekeys;
++ }
++
++ /* Extract 8/16/32 byte black keys */
++ sm_keystore_slot_read(ksdev, unit, keyslot_des, 8, black_key_des);
++ sm_keystore_slot_read(ksdev, unit, keyslot_aes128, 16,
++ black_key_aes128);
++ sm_keystore_slot_read(ksdev, unit, keyslot_aes256, 32,
++ black_key_aes256);
++
++#ifdef SM_TEST_DETAIL
++ dev_info(ksdev, "caam_sm_test: all black keys extracted\n");
++#endif
++
++ /* DES encrypt using 8 byte black key */
++ black_key_des_dma = dma_map_single(ksdev, black_key_des, 8,
++ DMA_TO_DEVICE);
++ dma_sync_single_for_device(ksdev, black_key_des_dma, 8, DMA_TO_DEVICE);
++ syminp_dma = dma_map_single(ksdev, syminp, 256, DMA_TO_DEVICE);
++ dma_sync_single_for_device(ksdev, syminp_dma, 256, DMA_TO_DEVICE);
++ symint_dma = dma_map_single(ksdev, symint, 256, DMA_FROM_DEVICE);
++
++ jdescsz = mk_job_desc(jdesc, black_key_des_dma, 8, syminp_dma,
++ symint_dma, 256,
++ OP_ALG_ENCRYPT | OP_ALG_ALGSEL_DES, 0);
++
++#ifdef SM_TEST_DETAIL
++ dev_info(ksdev, "jobdesc:\n");
++ dev_info(ksdev, "0x%08x\n", jdesc[0]);
++ dev_info(ksdev, "0x%08x\n", jdesc[1]);
++ dev_info(ksdev, "0x%08x\n", jdesc[2]);
++ dev_info(ksdev, "0x%08x\n", jdesc[3]);
++ dev_info(ksdev, "0x%08x\n", jdesc[4]);
++ dev_info(ksdev, "0x%08x\n", jdesc[5]);
++ dev_info(ksdev, "0x%08x\n", jdesc[6]);
++ dev_info(ksdev, "0x%08x\n", jdesc[7]);
++#endif
++
++ jstat = exec_test_job(ksdev, jdesc);
++
++ dma_sync_single_for_cpu(ksdev, symint_dma, 256, DMA_FROM_DEVICE);
++ dma_unmap_single(ksdev, symint_dma, 256, DMA_FROM_DEVICE);
++ dma_unmap_single(ksdev, syminp_dma, 256, DMA_TO_DEVICE);
++ dma_unmap_single(ksdev, black_key_des_dma, 8, DMA_TO_DEVICE);
++
++#ifdef SM_TEST_DETAIL
++ dev_info(ksdev, "input block:\n");
++ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \
++ "0x%02x 0x%02x 0x%02x 0x%02x\n",
++ syminp[0], syminp[1], syminp[2], syminp[3],
++ syminp[4], syminp[5], syminp[6], syminp[7]);
++ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \
++ "0x%02x 0x%02x 0x%02x 0x%02x\n",
++ syminp[8], syminp[9], syminp[10], syminp[11],
++ syminp[12], syminp[13], syminp[14], syminp[15]);
++ dev_info(ksdev, "intermediate block:\n");
++ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \
++ "0x%02x 0x%02x 0x%02x 0x%02x\n",
++ symint[0], symint[1], symint[2], symint[3],
++ symint[4], symint[5], symint[6], symint[7]);
++ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \
++ "0x%02x 0x%02x 0x%02x 0x%02x\n",
++ symint[8], symint[9], symint[10], symint[11],
++ symint[12], symint[13], symint[14], symint[15]);
++ dev_info(ksdev, "caam_sm_test: encrypt cycle with 8 byte key\n");
++#endif
++
++ /* DES decrypt using 8 byte clear key */
++ clear_key_des_dma = dma_map_single(ksdev, clear_key_des, 8,
++ DMA_TO_DEVICE);
++ dma_sync_single_for_device(ksdev, clear_key_des_dma, 8, DMA_TO_DEVICE);
++ symint_dma = dma_map_single(ksdev, symint, 256, DMA_TO_DEVICE);
++ dma_sync_single_for_device(ksdev, symint_dma, 256, DMA_TO_DEVICE);
++ symout_dma = dma_map_single(ksdev, symout, 256, DMA_FROM_DEVICE);
++
++ jdescsz = mk_job_desc(jdesc, clear_key_des_dma, 8, symint_dma,
++ symout_dma, 256,
++ OP_ALG_DECRYPT | OP_ALG_ALGSEL_DES, 0);
++
++#ifdef SM_TEST_DETAIL
++ dev_info(ksdev, "jobdesc:\n");
++ dev_info(ksdev, "0x%08x\n", jdesc[0]);
++ dev_info(ksdev, "0x%08x\n", jdesc[1]);
++ dev_info(ksdev, "0x%08x\n", jdesc[2]);
++ dev_info(ksdev, "0x%08x\n", jdesc[3]);
++ dev_info(ksdev, "0x%08x\n", jdesc[4]);
++ dev_info(ksdev, "0x%08x\n", jdesc[5]);
++ dev_info(ksdev, "0x%08x\n", jdesc[6]);
++ dev_info(ksdev, "0x%08x\n", jdesc[7]);
++#endif
++
++ jstat = exec_test_job(ksdev, jdesc);
++
++ dma_sync_single_for_cpu(ksdev, symout_dma, 256, DMA_FROM_DEVICE);
++ dma_unmap_single(ksdev, symout_dma, 256, DMA_FROM_DEVICE);
++ dma_unmap_single(ksdev, symint_dma, 256, DMA_TO_DEVICE);
++ dma_unmap_single(ksdev, clear_key_des_dma, 8, DMA_TO_DEVICE);
++
++#ifdef SM_TEST_DETAIL
++ dev_info(ksdev, "intermediate block:\n");
++ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \
++ "0x%02x 0x%02x 0x%02x 0x%02x\n",
++ symint[0], symint[1], symint[2], symint[3],
++ symint[4], symint[5], symint[6], symint[7]);
++ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \
++ "0x%02x 0x%02x 0x%02x 0x%02x\n",
++ symint[8], symint[9], symint[10], symint[11],
++ symint[12], symint[13], symint[14], symint[15]);
++ dev_info(ksdev, "decrypted block:\n");
++ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \
++ "0x%02x 0x%02x 0x%02x 0x%02x\n",
++ symout[0], symout[1], symout[2], symout[3],
++ symout[4], symout[5], symout[6], symout[7]);
++ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \
++ "0x%02x 0x%02x 0x%02x 0x%02x\n",
++ symout[8], symout[9], symout[10], symout[11],
++ symout[12], symout[13], symout[14], symout[15]);
++ dev_info(ksdev, "caam_sm_test: decrypt cycle with 8 byte key\n");
++#endif
++
++ /* Check result */
++ if (memcmp(symout, syminp, 256)) {
++ dev_info(ksdev, "caam_sm_test: 8-byte key test mismatch\n");
++ rtnval = -1;
++ goto freekeys;
++ } else
++ dev_info(ksdev, "caam_sm_test: 8-byte key test match OK\n");
++
++ /* AES-128 encrypt using 16 byte black key */
++ black_key_aes128_dma = dma_map_single(ksdev, black_key_aes128, 16,
++ DMA_TO_DEVICE);
++ dma_sync_single_for_device(ksdev, black_key_aes128_dma, 16,
++ DMA_TO_DEVICE);
++ syminp_dma = dma_map_single(ksdev, syminp, 256, DMA_TO_DEVICE);
++ dma_sync_single_for_device(ksdev, syminp_dma, 256, DMA_TO_DEVICE);
++ symint_dma = dma_map_single(ksdev, symint, 256, DMA_FROM_DEVICE);
++
++ jdescsz = mk_job_desc(jdesc, black_key_aes128_dma, 16, syminp_dma,
++ symint_dma, 256,
++ OP_ALG_ENCRYPT | OP_ALG_ALGSEL_AES, 0);
++
++#ifdef SM_TEST_DETAIL
++ dev_info(ksdev, "jobdesc:\n");
++ dev_info(ksdev, "0x%08x\n", jdesc[0]);
++ dev_info(ksdev, "0x%08x\n", jdesc[1]);
++ dev_info(ksdev, "0x%08x\n", jdesc[2]);
++ dev_info(ksdev, "0x%08x\n", jdesc[3]);
++ dev_info(ksdev, "0x%08x\n", jdesc[4]);
++ dev_info(ksdev, "0x%08x\n", jdesc[5]);
++ dev_info(ksdev, "0x%08x\n", jdesc[6]);
++ dev_info(ksdev, "0x%08x\n", jdesc[7]);
++#endif
++
++ jstat = exec_test_job(ksdev, jdesc);
++
++ dma_sync_single_for_cpu(ksdev, symint_dma, 256, DMA_FROM_DEVICE);
++ dma_unmap_single(ksdev, symint_dma, 256, DMA_FROM_DEVICE);
++ dma_unmap_single(ksdev, syminp_dma, 256, DMA_TO_DEVICE);
++ dma_unmap_single(ksdev, black_key_aes128_dma, 16, DMA_TO_DEVICE);
++
++#ifdef SM_TEST_DETAIL
++ dev_info(ksdev, "input block:\n");
++ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \
++ "0x%02x 0x%02x 0x%02x 0x%02x\n",
++ syminp[0], syminp[1], syminp[2], syminp[3],
++ syminp[4], syminp[5], syminp[6], syminp[7]);
++ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \
++ "0x%02x 0x%02x 0x%02x 0x%02x\n",
++ syminp[8], syminp[9], syminp[10], syminp[11],
++ syminp[12], syminp[13], syminp[14], syminp[15]);
++ dev_info(ksdev, "intermediate block:\n");
++ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \
++ "0x%02x 0x%02x 0x%02x 0x%02x\n",
++ symint[0], symint[1], symint[2], symint[3],
++ symint[4], symint[5], symint[6], symint[7]);
++ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \
++ "0x%02x 0x%02x 0x%02x 0x%02x\n",
++ symint[8], symint[9], symint[10], symint[11],
++ symint[12], symint[13], symint[14], symint[15]);
++ dev_info(ksdev, "caam_sm_test: encrypt cycle with 16 byte key\n");
++#endif
++
++ /* AES-128 decrypt using 16 byte clear key */
++ clear_key_aes128_dma = dma_map_single(ksdev, clear_key_aes128, 16,
++ DMA_TO_DEVICE);
++ dma_sync_single_for_device(ksdev, clear_key_aes128_dma, 16,
++ DMA_TO_DEVICE);
++ symint_dma = dma_map_single(ksdev, symint, 256, DMA_TO_DEVICE);
++ dma_sync_single_for_device(ksdev, symint_dma, 256, DMA_TO_DEVICE);
++ symout_dma = dma_map_single(ksdev, symout, 256, DMA_FROM_DEVICE);
++
++ jdescsz = mk_job_desc(jdesc, clear_key_aes128_dma, 16, symint_dma,
++ symout_dma, 256,
++ OP_ALG_DECRYPT | OP_ALG_ALGSEL_AES, 0);
++
++#ifdef SM_TEST_DETAIL
++ dev_info(ksdev, "jobdesc:\n");
++ dev_info(ksdev, "0x%08x\n", jdesc[0]);
++ dev_info(ksdev, "0x%08x\n", jdesc[1]);
++ dev_info(ksdev, "0x%08x\n", jdesc[2]);
++ dev_info(ksdev, "0x%08x\n", jdesc[3]);
++ dev_info(ksdev, "0x%08x\n", jdesc[4]);
++ dev_info(ksdev, "0x%08x\n", jdesc[5]);
++ dev_info(ksdev, "0x%08x\n", jdesc[6]);
++ dev_info(ksdev, "0x%08x\n", jdesc[7]);
++#endif
++ jstat = exec_test_job(ksdev, jdesc);
++
++ dma_sync_single_for_cpu(ksdev, symout_dma, 256, DMA_FROM_DEVICE);
++ dma_unmap_single(ksdev, symout_dma, 256, DMA_FROM_DEVICE);
++ dma_unmap_single(ksdev, symint_dma, 256, DMA_TO_DEVICE);
++ dma_unmap_single(ksdev, clear_key_aes128_dma, 16, DMA_TO_DEVICE);
++
++#ifdef SM_TEST_DETAIL
++ dev_info(ksdev, "intermediate block:\n");
++ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \
++ "0x%02x 0x%02x 0x%02x 0x%02x\n",
++ symint[0], symint[1], symint[2], symint[3],
++ symint[4], symint[5], symint[6], symint[7]);
++ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \
++ "0x%02x 0x%02x 0x%02x 0x%02x\n",
++ symint[8], symint[9], symint[10], symint[11],
++ symint[12], symint[13], symint[14], symint[15]);
++ dev_info(ksdev, "decrypted block:\n");
++ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \
++ "0x%02x 0x%02x 0x%02x 0x%02x\n",
++ symout[0], symout[1], symout[2], symout[3],
++ symout[4], symout[5], symout[6], symout[7]);
++ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \
++ "0x%02x 0x%02x 0x%02x 0x%02x\n",
++ symout[8], symout[9], symout[10], symout[11],
++ symout[12], symout[13], symout[14], symout[15]);
++ dev_info(ksdev, "caam_sm_test: decrypt cycle with 16 byte key\n");
++#endif
++
++ /* Check result */
++ if (memcmp(symout, syminp, 256)) {
++ dev_info(ksdev, "caam_sm_test: 16-byte key test mismatch\n");
++ rtnval = -1;
++ goto freekeys;
++ } else
++ dev_info(ksdev, "caam_sm_test: 16-byte key test match OK\n");
++
++ /* AES-256 encrypt using 32 byte black key */
++ black_key_aes256_dma = dma_map_single(ksdev, black_key_aes256, 32,
++ DMA_TO_DEVICE);
++ dma_sync_single_for_device(ksdev, black_key_aes256_dma, 32,
++ DMA_TO_DEVICE);
++ syminp_dma = dma_map_single(ksdev, syminp, 256, DMA_TO_DEVICE);
++ dma_sync_single_for_device(ksdev, syminp_dma, 256, DMA_TO_DEVICE);
++ symint_dma = dma_map_single(ksdev, symint, 256, DMA_FROM_DEVICE);
++
++ jdescsz = mk_job_desc(jdesc, black_key_aes256_dma, 32, syminp_dma,
++ symint_dma, 256,
++ OP_ALG_ENCRYPT | OP_ALG_ALGSEL_AES, 0);
++
++#ifdef SM_TEST_DETAIL
++ dev_info(ksdev, "jobdesc:\n");
++ dev_info(ksdev, "0x%08x\n", jdesc[0]);
++ dev_info(ksdev, "0x%08x\n", jdesc[1]);
++ dev_info(ksdev, "0x%08x\n", jdesc[2]);
++ dev_info(ksdev, "0x%08x\n", jdesc[3]);
++ dev_info(ksdev, "0x%08x\n", jdesc[4]);
++ dev_info(ksdev, "0x%08x\n", jdesc[5]);
++ dev_info(ksdev, "0x%08x\n", jdesc[6]);
++ dev_info(ksdev, "0x%08x\n", jdesc[7]);
++#endif
++
++ jstat = exec_test_job(ksdev, jdesc);
++
++ dma_sync_single_for_cpu(ksdev, symint_dma, 256, DMA_FROM_DEVICE);
++ dma_unmap_single(ksdev, symint_dma, 256, DMA_FROM_DEVICE);
++ dma_unmap_single(ksdev, syminp_dma, 256, DMA_TO_DEVICE);
++ dma_unmap_single(ksdev, black_key_aes256_dma, 32, DMA_TO_DEVICE);
++
++#ifdef SM_TEST_DETAIL
++ dev_info(ksdev, "input block:\n");
++ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \
++ "0x%02x 0x%02x 0x%02x 0x%02x\n",
++ syminp[0], syminp[1], syminp[2], syminp[3],
++ syminp[4], syminp[5], syminp[6], syminp[7]);
++ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \
++ "0x%02x 0x%02x 0x%02x 0x%02x\n",
++ syminp[8], syminp[9], syminp[10], syminp[11],
++ syminp[12], syminp[13], syminp[14], syminp[15]);
++ dev_info(ksdev, "intermediate block:\n");
++ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \
++ "0x%02x 0x%02x 0x%02x 0x%02x\n",
++ symint[0], symint[1], symint[2], symint[3],
++ symint[4], symint[5], symint[6], symint[7]);
++ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \
++ "0x%02x 0x%02x 0x%02x 0x%02x\n",
++ symint[8], symint[9], symint[10], symint[11],
++ symint[12], symint[13], symint[14], symint[15]);
++ dev_info(ksdev, "caam_sm_test: encrypt cycle with 32 byte key\n");
++#endif
++
++ /* AES-256 decrypt using 32-byte black key */
++ clear_key_aes256_dma = dma_map_single(ksdev, clear_key_aes256, 32,
++ DMA_TO_DEVICE);
++ dma_sync_single_for_device(ksdev, clear_key_aes256_dma, 32,
++ DMA_TO_DEVICE);
++ symint_dma = dma_map_single(ksdev, symint, 256, DMA_TO_DEVICE);
++ dma_sync_single_for_device(ksdev, symint_dma, 256, DMA_TO_DEVICE);
++ symout_dma = dma_map_single(ksdev, symout, 256, DMA_FROM_DEVICE);
++
++ jdescsz = mk_job_desc(jdesc, clear_key_aes256_dma, 32, symint_dma,
++ symout_dma, 256,
++ OP_ALG_DECRYPT | OP_ALG_ALGSEL_AES, 0);
++
++#ifdef SM_TEST_DETAIL
++ dev_info(ksdev, "jobdesc:\n");
++ dev_info(ksdev, "0x%08x\n", jdesc[0]);
++ dev_info(ksdev, "0x%08x\n", jdesc[1]);
++ dev_info(ksdev, "0x%08x\n", jdesc[2]);
++ dev_info(ksdev, "0x%08x\n", jdesc[3]);
++ dev_info(ksdev, "0x%08x\n", jdesc[4]);
++ dev_info(ksdev, "0x%08x\n", jdesc[5]);
++ dev_info(ksdev, "0x%08x\n", jdesc[6]);
++ dev_info(ksdev, "0x%08x\n", jdesc[7]);
++#endif
++
++ jstat = exec_test_job(ksdev, jdesc);
++
++ dma_sync_single_for_cpu(ksdev, symout_dma, 256, DMA_FROM_DEVICE);
++ dma_unmap_single(ksdev, symout_dma, 256, DMA_FROM_DEVICE);
++ dma_unmap_single(ksdev, symint_dma, 256, DMA_TO_DEVICE);
++ dma_unmap_single(ksdev, clear_key_aes256_dma, 32, DMA_TO_DEVICE);
++
++#ifdef SM_TEST_DETAIL
++ dev_info(ksdev, "intermediate block:\n");
++ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \
++ "0x%02x 0x%02x 0x%02x 0x%02x\n",
++ symint[0], symint[1], symint[2], symint[3],
++ symint[4], symint[5], symint[6], symint[7]);
++ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \
++ "0x%02x 0x%02x 0x%02x 0x%02x\n",
++ symint[8], symint[9], symint[10], symint[11],
++ symint[12], symint[13], symint[14], symint[15]);
++ dev_info(ksdev, "decrypted block:\n");
++ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \
++ "0x%02x 0x%02x 0x%02x 0x%02x\n",
++ symout[0], symout[1], symout[2], symout[3],
++ symout[4], symout[5], symout[6], symout[7]);
++ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \
++ "0x%02x 0x%02x 0x%02x 0x%02x\n",
++ symout[8], symout[9], symout[10], symout[11],
++ symout[12], symout[13], symout[14], symout[15]);
++ dev_info(ksdev, "caam_sm_test: decrypt cycle with 32 byte key\n");
++#endif
++
++ /* Check result */
++ if (memcmp(symout, syminp, 256)) {
++ dev_info(ksdev, "caam_sm_test: 32-byte key test mismatch\n");
++ rtnval = -1;
++ goto freekeys;
++ } else
++ dev_info(ksdev, "caam_sm_test: 32-byte key test match OK\n");
++
++
++ /* Remove 8/16/32 byte keys from keystore */
++freekeys:
++ stat = sm_keystore_slot_dealloc(ksdev, unit, keyslot_des);
++ if (stat)
++ dev_info(ksdev, "caam_sm_test: can't release slot %d\n",
++ keyslot_des);
++
++ stat = sm_keystore_slot_dealloc(ksdev, unit, keyslot_aes128);
++ if (stat)
++ dev_info(ksdev, "caam_sm_test: can't release slot %d\n",
++ keyslot_aes128);
++
++ stat = sm_keystore_slot_dealloc(ksdev, unit, keyslot_aes256);
++ if (stat)
++ dev_info(ksdev, "caam_sm_test: can't release slot %d\n",
++ keyslot_aes256);
++
++
++ /* Free resources */
++freemem:
++#ifdef SM_TEST_DETAIL
++ dev_info(ksdev, "caam_sm_test: cleaning up\n");
++#endif
++ kfree(syminp);
++ kfree(symint);
++ kfree(symout);
++ kfree(clear_key_des);
++ kfree(clear_key_aes128);
++ kfree(clear_key_aes256);
++ kfree(black_key_des);
++ kfree(black_key_aes128);
++ kfree(black_key_aes256);
++ kfree(jdesc);
++
++ /* Disconnect from keystore and leave */
++ sm_release_keystore(ksdev, unit);
++
++ return rtnval;
++}
++EXPORT_SYMBOL(caam_sm_example_init);
++
++void caam_sm_example_shutdown(void)
++{
++ /* unused in present version */
++ struct device_node *dev_node;
++ struct platform_device *pdev;
++
++ /*
++ * Do of_find_compatible_node() then of_find_device_by_node()
++ * once a functional device tree is available
++ */
++ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
++ if (!dev_node) {
++ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec4.0");
++ if (!dev_node)
++ return;
++ }
++
++ pdev = of_find_device_by_node(dev_node);
++ if (!pdev)
++ return;
++
++ of_node_get(dev_node);
++
++}
++
++static int __init caam_sm_test_init(void)
++{
++ struct device_node *dev_node;
++ struct platform_device *pdev;
++
++ /*
++ * Do of_find_compatible_node() then of_find_device_by_node()
++ * once a functional device tree is available
++ */
++ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
++ if (!dev_node) {
++ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec4.0");
++ if (!dev_node)
++ return -ENODEV;
++ }
++
++ pdev = of_find_device_by_node(dev_node);
++ if (!pdev)
++ return -ENODEV;
++
++ of_node_put(dev_node);
++
++ caam_sm_example_init(pdev);
++
++ return 0;
++}
++
++
++/* Module-based initialization needs to wait for dev tree */
++#ifdef CONFIG_OF
++module_init(caam_sm_test_init);
++module_exit(caam_sm_example_shutdown);
++
++MODULE_LICENSE("Dual BSD/GPL");
++MODULE_DESCRIPTION("FSL CAAM Keystore Usage Example");
++MODULE_AUTHOR("Freescale Semiconductor - NMSG/MAD");
++#endif
+diff -Nur linux-4.1.3/drivers/crypto/caam/snvsregs.h linux-xbian-imx6/drivers/crypto/caam/snvsregs.h
+--- linux-4.1.3/drivers/crypto/caam/snvsregs.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/crypto/caam/snvsregs.h 2015-07-27 23:13:04.213947410 +0200
+@@ -0,0 +1,237 @@
++/*
++ * SNVS hardware register-level view
++ *
++ * Copyright (C) 2012-2014 Freescale Semiconductor, Inc., All Rights Reserved
++ */
++
++#ifndef SNVSREGS_H
++#define SNVSREGS_H
++
++#include <linux/types.h>
++#include <linux/io.h>
++
++/*
++ * SNVS High Power Domain
++ * Includes security violations, HA counter, RTC, alarm
++ */
++struct snvs_hp {
++ u32 lock; /* HPLR - HP Lock */
++ u32 cmd; /* HPCOMR - HP Command */
++ u32 ctl; /* HPCR - HP Control */
++ u32 secvio_intcfg; /* HPSICR - Security Violation Int Config */
++ u32 secvio_ctl; /* HPSVCR - Security Violation Control */
++ u32 status; /* HPSR - HP Status */
++ u32 secvio_status; /* HPSVSR - Security Violation Status */
++ u32 ha_counteriv; /* High Assurance Counter IV */
++ u32 ha_counter; /* High Assurance Counter */
++ u32 rtc_msb; /* Real Time Clock/Counter MSB */
++ u32 rtc_lsb; /* Real Time Counter LSB */
++ u32 time_alarm_msb; /* Time Alarm MSB */
++ u32 time_alarm_lsb; /* Time Alarm LSB */
++};
++
++#define HP_LOCK_HAC_LCK 0x00040000
++#define HP_LOCK_HPSICR_LCK 0x00020000
++#define HP_LOCK_HPSVCR_LCK 0x00010000
++#define HP_LOCK_MKEYSEL_LCK 0x00000200
++#define HP_LOCK_TAMPCFG_LCK 0x00000100
++#define HP_LOCK_TAMPFLT_LCK 0x00000080
++#define HP_LOCK_SECVIO_LCK 0x00000040
++#define HP_LOCK_GENP_LCK 0x00000020
++#define HP_LOCK_MONOCTR_LCK 0x00000010
++#define HP_LOCK_CALIB_LCK 0x00000008
++#define HP_LOCK_SRTC_LCK 0x00000004
++#define HP_LOCK_ZMK_RD_LCK 0x00000002
++#define HP_LOCK_ZMK_WT_LCK 0x00000001
++
++#define HP_CMD_NONPRIV_AXS 0x80000000
++#define HP_CMD_HAC_STOP 0x00080000
++#define HP_CMD_HAC_CLEAR 0x00040000
++#define HP_CMD_HAC_LOAD 0x00020000
++#define HP_CMD_HAC_CFG_EN 0x00010000
++#define HP_CMD_SNVS_MSTR_KEY 0x00002000
++#define HP_CMD_PROG_ZMK 0x00001000
++#define HP_CMD_SW_LPSV 0x00000400
++#define HP_CMD_SW_FSV 0x00000200
++#define HP_CMD_SW_SV 0x00000100
++#define HP_CMD_LP_SWR_DIS 0x00000020
++#define HP_CMD_LP_SWR 0x00000010
++#define HP_CMD_SSM_SFNS_DIS 0x00000004
++#define HP_CMD_SSM_ST_DIS 0x00000002
++#define HP_CMD_SMM_ST 0x00000001
++
++#define HP_CTL_TIME_SYNC 0x00010000
++#define HP_CTL_CAL_VAL_SHIFT 10
++#define HP_CTL_CAL_VAL_MASK (0x1f << HP_CTL_CALIB_SHIFT)
++#define HP_CTL_CALIB_EN 0x00000100
++#define HP_CTL_PI_FREQ_SHIFT 4
++#define HP_CTL_PI_FREQ_MASK (0xf << HP_CTL_PI_FREQ_SHIFT)
++#define HP_CTL_PI_EN 0x00000008
++#define HP_CTL_TIMEALARM_EN 0x00000002
++#define HP_CTL_RTC_EN 0x00000001
++
++#define HP_SECVIO_INTEN_EN 0x10000000
++#define HP_SECVIO_INTEN_SRC5 0x00000020
++#define HP_SECVIO_INTEN_SRC4 0x00000010
++#define HP_SECVIO_INTEN_SRC3 0x00000008
++#define HP_SECVIO_INTEN_SRC2 0x00000004
++#define HP_SECVIO_INTEN_SRC1 0x00000002
++#define HP_SECVIO_INTEN_SRC0 0x00000001
++#define HP_SECVIO_INTEN_ALL 0x8000003f
++
++#define HP_SECVIO_ICTL_CFG_SHIFT 30
++#define HP_SECVIO_ICTL_CFG_MASK (0x3 << HP_SECVIO_ICTL_CFG_SHIFT)
++#define HP_SECVIO_ICTL_CFG5_SHIFT 5
++#define HP_SECVIO_ICTL_CFG5_MASK (0x3 << HP_SECVIO_ICTL_CFG5_SHIFT)
++#define HP_SECVIO_ICTL_CFG_DISABLE 0
++#define HP_SECVIO_ICTL_CFG_NONFATAL 1
++#define HP_SECVIO_ICTL_CFG_FATAL 2
++#define HP_SECVIO_ICTL_CFG4_FATAL 0x00000010
++#define HP_SECVIO_ICTL_CFG3_FATAL 0x00000008
++#define HP_SECVIO_ICTL_CFG2_FATAL 0x00000004
++#define HP_SECVIO_ICTL_CFG1_FATAL 0x00000002
++#define HP_SECVIO_ICTL_CFG0_FATAL 0x00000001
++
++#define HP_STATUS_ZMK_ZERO 0x80000000
++#define HP_STATUS_OTPMK_ZERO 0x08000000
++#define HP_STATUS_OTPMK_SYN_SHIFT 16
++#define HP_STATUS_OTPMK_SYN_MASK (0x1ff << HP_STATUS_OTPMK_SYN_SHIFT)
++#define HP_STATUS_SSM_ST_SHIFT 8
++#define HP_STATUS_SSM_ST_MASK (0xf << HP_STATUS_SSM_ST_SHIFT)
++#define HP_STATUS_SSM_ST_INIT 0
++#define HP_STATUS_SSM_ST_HARDFAIL 1
++#define HP_STATUS_SSM_ST_SOFTFAIL 3
++#define HP_STATUS_SSM_ST_INITINT 8
++#define HP_STATUS_SSM_ST_CHECK 9
++#define HP_STATUS_SSM_ST_NONSECURE 11
++#define HP_STATUS_SSM_ST_TRUSTED 13
++#define HP_STATUS_SSM_ST_SECURE 15
++
++#define HP_SECVIOST_ZMK_ECC_FAIL 0x08000000 /* write to clear */
++#define HP_SECVIOST_ZMK_SYN_SHIFT 16
++#define HP_SECVIOST_ZMK_SYN_MASK (0x1ff << HP_SECVIOST_ZMK_SYN_SHIFT)
++#define HP_SECVIOST_SECVIO5 0x00000020
++#define HP_SECVIOST_SECVIO4 0x00000010
++#define HP_SECVIOST_SECVIO3 0x00000008
++#define HP_SECVIOST_SECVIO2 0x00000004
++#define HP_SECVIOST_SECVIO1 0x00000002
++#define HP_SECVIOST_SECVIO0 0x00000001
++#define HP_SECVIOST_SECVIOMASK 0x0000003f
++
++/*
++ * SNVS Low Power Domain
++ * Includes glitch detector, SRTC, alarm, monotonic counter, ZMK
++ */
++struct snvs_lp {
++ u32 lock;
++ u32 ctl;
++ u32 mstr_key_ctl; /* Master Key Control */
++ u32 secvio_ctl; /* Security Violation Control */
++ u32 tamper_filt_cfg; /* Tamper Glitch Filters Configuration */
++ u32 tamper_det_cfg; /* Tamper Detectors Configuration */
++ u32 status;
++ u32 srtc_msb; /* Secure Real Time Clock/Counter MSB */
++ u32 srtc_lsb; /* Secure Real Time Clock/Counter LSB */
++ u32 time_alarm; /* Time Alarm */
++ u32 smc_msb; /* Secure Monotonic Counter MSB */
++ u32 smc_lsb; /* Secure Monotonic Counter LSB */
++ u32 pwr_glitch_det; /* Power Glitch Detector */
++ u32 gen_purpose;
++ u32 zmk[8]; /* Zeroizable Master Key */
++};
++
++#define LP_LOCK_MKEYSEL_LCK 0x00000200
++#define LP_LOCK_TAMPDET_LCK 0x00000100
++#define LP_LOCK_TAMPFLT_LCK 0x00000080
++#define LP_LOCK_SECVIO_LCK 0x00000040
++#define LP_LOCK_GENP_LCK 0x00000020
++#define LP_LOCK_MONOCTR_LCK 0x00000010
++#define LP_LOCK_CALIB_LCK 0x00000008
++#define LP_LOCK_SRTC_LCK 0x00000004
++#define LP_LOCK_ZMK_RD_LCK 0x00000002
++#define LP_LOCK_ZMK_WT_LCK 0x00000001
++
++#define LP_CTL_CAL_VAL_SHIFT 10
++#define LP_CTL_CAL_VAL_MASK (0x1f << LP_CTL_CAL_VAL_SHIFT)
++#define LP_CTL_CALIB_EN 0x00000100
++#define LP_CTL_SRTC_INVAL_EN 0x00000010
++#define LP_CTL_WAKE_INT_EN 0x00000008
++#define LP_CTL_MONOCTR_EN 0x00000004
++#define LP_CTL_TIMEALARM_EN 0x00000002
++#define LP_CTL_SRTC_EN 0x00000001
++
++#define LP_MKEYCTL_ZMKECC_SHIFT 8
++#define LP_MKEYCTL_ZMKECC_MASK (0xff << LP_MKEYCTL_ZMKECC_SHIFT)
++#define LP_MKEYCTL_ZMKECC_EN 0x00000010
++#define LP_MKEYCTL_ZMKECC_VAL 0x00000008
++#define LP_MKEYCTL_ZMKECC_PROG 0x00000004
++#define LP_MKEYCTL_MKSEL_SHIFT 0
++#define LP_MKEYCTL_MKSEL_MASK (3 << LP_MKEYCTL_MKSEL_SHIFT)
++#define LP_MKEYCTL_MK_OTP 0
++#define LP_MKEYCTL_MK_ZMK 2
++#define LP_MKEYCTL_MK_COMB 3
++
++#define LP_SECVIO_CTL_SRC5 0x20
++#define LP_SECVIO_CTL_SRC4 0x10
++#define LP_SECVIO_CTL_SRC3 0x08
++#define LP_SECVIO_CTL_SRC2 0x04
++#define LP_SECVIO_CTL_SRC1 0x02
++#define LP_SECVIO_CTL_SRC0 0x01
++
++#define LP_TAMPFILT_EXT2_EN 0x80000000
++#define LP_TAMPFILT_EXT2_SHIFT 24
++#define LP_TAMPFILT_EXT2_MASK (0x1f << LP_TAMPFILT_EXT2_SHIFT)
++#define LP_TAMPFILT_EXT1_EN 0x00800000
++#define LP_TAMPFILT_EXT1_SHIFT 16
++#define LP_TAMPFILT_EXT1_MASK (0x1f << LP_TAMPFILT_EXT1_SHIFT)
++#define LP_TAMPFILT_WM_EN 0x00000080
++#define LP_TAMPFILT_WM_SHIFT 0
++#define LP_TAMPFILT_WM_MASK (0x1f << LP_TAMPFILT_WM_SHIFT)
++
++#define LP_TAMPDET_OSC_BPS 0x10000000
++#define LP_TAMPDET_VRC_SHIFT 24
++#define LP_TAMPDET_VRC_MASK (3 << LP_TAMPFILT_VRC_SHIFT)
++#define LP_TAMPDET_HTDC_SHIFT 20
++#define LP_TAMPDET_HTDC_MASK (3 << LP_TAMPFILT_HTDC_SHIFT)
++#define LP_TAMPDET_LTDC_SHIFT 16
++#define LP_TAMPDET_LTDC_MASK (3 << LP_TAMPFILT_LTDC_SHIFT)
++#define LP_TAMPDET_POR_OBS 0x00008000
++#define LP_TAMPDET_PFD_OBS 0x00004000
++#define LP_TAMPDET_ET2_EN 0x00000400
++#define LP_TAMPDET_ET1_EN 0x00000200
++#define LP_TAMPDET_WMT2_EN 0x00000100
++#define LP_TAMPDET_WMT1_EN 0x00000080
++#define LP_TAMPDET_VT_EN 0x00000040
++#define LP_TAMPDET_TT_EN 0x00000020
++#define LP_TAMPDET_CT_EN 0x00000010
++#define LP_TAMPDET_MCR_EN 0x00000004
++#define LP_TAMPDET_SRTCR_EN 0x00000002
++
++#define LP_STATUS_SECURE
++#define LP_STATUS_NONSECURE
++#define LP_STATUS_SCANEXIT 0x00100000 /* all write 1 clear here on */
++#define LP_STATUS_EXT_SECVIO 0x00010000
++#define LP_STATUS_ET2 0x00000400
++#define LP_STATUS_ET1 0x00000200
++#define LP_STATUS_WMT2 0x00000100
++#define LP_STATUS_WMT1 0x00000080
++#define LP_STATUS_VTD 0x00000040
++#define LP_STATUS_TTD 0x00000020
++#define LP_STATUS_CTD 0x00000010
++#define LP_STATUS_PGD 0x00000008
++#define LP_STATUS_MCR 0x00000004
++#define LP_STATUS_SRTCR 0x00000002
++#define LP_STATUS_LPTA 0x00000001
++
++/* Full SNVS register page, including version/options */
++struct snvs_full {
++ struct snvs_hp hp;
++ struct snvs_lp lp;
++ u32 rsvd[731]; /* deadspace 0x08c-0xbf7 */
++
++ /* Version / Revision / Option ID space - end of register page */
++ u32 vid; /* 0xbf8 HP Version ID (VID 1) */
++ u32 opt_rev; /* 0xbfc HP Options / Revision (VID 2) */
++};
++
++#endif /* SNVSREGS_H */
+diff -Nur linux-4.1.3/drivers/dma/imx-sdma.c linux-xbian-imx6/drivers/dma/imx-sdma.c
+--- linux-4.1.3/drivers/dma/imx-sdma.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/drivers/dma/imx-sdma.c 2015-07-27 23:13:04.285691435 +0200
+@@ -29,6 +29,7 @@
+ #include <linux/semaphore.h>
+ #include <linux/spinlock.h>
+ #include <linux/device.h>
++#include <linux/genalloc.h>
+ #include <linux/dma-mapping.h>
+ #include <linux/firmware.h>
+ #include <linux/slab.h>
+@@ -232,6 +233,14 @@
+
+ struct sdma_engine;
+
++enum sdma_mode {
++ SDMA_MODE_INVALID = 0,
++ SDMA_MODE_LOOP,
++ SDMA_MODE_NORMAL,
++ SDMA_MODE_P2P,
++ SDMA_MODE_NO_BD,
++};
++
+ /**
+ * struct sdma_channel - housekeeping for a SDMA channel
+ *
+@@ -244,6 +253,7 @@
+ * @word_size peripheral access size
+ * @buf_tail ID of the buffer that was processed
+ * @num_bd max NUM_BD. number of descriptors currently handling
++ * @bd_iram flag indicating the memory location of buffer descriptor
+ */
+ struct sdma_channel {
+ struct sdma_engine *sdma;
+@@ -258,12 +268,16 @@
+ unsigned int period_len;
+ struct sdma_buffer_descriptor *bd;
+ dma_addr_t bd_phys;
++ bool bd_iram;
+ unsigned int pc_from_device, pc_to_device;
+- unsigned long flags;
+- dma_addr_t per_address;
++ unsigned int device_to_device;
++ unsigned int other_script;
++ enum sdma_mode mode;
++ dma_addr_t per_address, per_address2;
+ unsigned long event_mask[2];
+ unsigned long watermark_level;
+ u32 shp_addr, per_addr;
++ u32 data_addr1, data_addr2;
+ struct dma_chan chan;
+ spinlock_t lock;
+ struct dma_async_tx_descriptor desc;
+@@ -271,11 +285,8 @@
+ unsigned int chn_count;
+ unsigned int chn_real_count;
+ struct tasklet_struct tasklet;
+- struct imx_dma_data data;
+ };
+
+-#define IMX_DMA_SG_LOOP BIT(0)
+-
+ #define MAX_DMA_CHANNELS 32
+ #define MXC_SDMA_DEFAULT_PRIORITY 1
+ #define MXC_SDMA_MIN_PRIORITY 1
+@@ -327,6 +338,7 @@
+ spinlock_t channel_0_lock;
+ u32 script_number;
+ struct sdma_script_start_addrs *script_addrs;
++ struct gen_pool *iram_pool;
+ const struct sdma_driver_data *drvdata;
+ };
+
+@@ -546,12 +558,14 @@
+ dma_addr_t buf_phys;
+ int ret;
+ unsigned long flags;
++ bool use_iram = true;
+
+- buf_virt = dma_alloc_coherent(NULL,
+- size,
+- &buf_phys, GFP_KERNEL);
++ buf_virt = gen_pool_dma_alloc(sdma->iram_pool, size, &buf_phys);
+ if (!buf_virt) {
+- return -ENOMEM;
++ use_iram = false;
++ buf_virt = dma_alloc_coherent(NULL, size, &buf_phys, GFP_KERNEL);
++ if (!buf_virt)
++ return -ENOMEM;
+ }
+
+ spin_lock_irqsave(&sdma->channel_0_lock, flags);
+@@ -568,7 +582,10 @@
+
+ spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
+
+- dma_free_coherent(NULL, size, buf_virt, buf_phys);
++ if (use_iram)
++ gen_pool_free(sdma->iram_pool, (unsigned long)buf_virt, size);
++ else
++ dma_free_coherent(NULL, size, buf_virt, buf_phys);
+
+ return ret;
+ }
+@@ -654,14 +671,31 @@
+ sdmac->desc.callback(sdmac->desc.callback_param);
+ }
+
++static void sdma_handle_other_intr(struct sdma_channel *sdmac)
++{
++ if (sdmac->desc.callback)
++ sdmac->desc.callback(sdmac->desc.callback_param);
++}
++
+ static void sdma_tasklet(unsigned long data)
+ {
+ struct sdma_channel *sdmac = (struct sdma_channel *) data;
++ struct sdma_engine *sdma = sdmac->sdma;
+
+- if (sdmac->flags & IMX_DMA_SG_LOOP)
++ switch (sdmac->mode) {
++ case SDMA_MODE_LOOP:
+ sdma_handle_channel_loop(sdmac);
+- else
++ break;
++ case SDMA_MODE_NORMAL:
+ mxc_sdma_handle_channel_normal(sdmac);
++ break;
++ case SDMA_MODE_NO_BD:
++ sdma_handle_other_intr(sdmac);
++ break;
++ default:
++ dev_err(sdma->dev, "invalid SDMA MODE!\n");
++ break;
++ }
+ }
+
+ static irqreturn_t sdma_int_handler(int irq, void *dev_id)
+@@ -678,7 +712,7 @@
+ int channel = fls(stat) - 1;
+ struct sdma_channel *sdmac = &sdma->channel[channel];
+
+- if (sdmac->flags & IMX_DMA_SG_LOOP)
++ if (sdmac->mode & SDMA_MODE_LOOP)
+ sdma_update_channel_loop(sdmac);
+
+ tasklet_schedule(&sdmac->tasklet);
+@@ -702,9 +736,12 @@
+ * two peripherals or memory-to-memory transfers
+ */
+ int per_2_per = 0, emi_2_emi = 0;
++ int other = 0;
+
+ sdmac->pc_from_device = 0;
+ sdmac->pc_to_device = 0;
++ sdmac->device_to_device = 0;
++ sdmac->other_script = 0;
+
+ switch (peripheral_type) {
+ case IMX_DMATYPE_MEMORY:
+@@ -733,7 +770,6 @@
+ case IMX_DMATYPE_CSPI:
+ case IMX_DMATYPE_EXT:
+ case IMX_DMATYPE_SSI:
+- case IMX_DMATYPE_SAI:
+ per_2_emi = sdma->script_addrs->app_2_mcu_addr;
+ emi_2_per = sdma->script_addrs->mcu_2_app_addr;
+ break;
+@@ -751,11 +787,6 @@
+ emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
+ break;
+ case IMX_DMATYPE_ASRC:
+- per_2_emi = sdma->script_addrs->asrc_2_mcu_addr;
+- emi_2_per = sdma->script_addrs->asrc_2_mcu_addr;
+- per_2_per = sdma->script_addrs->per_2_per_addr;
+- break;
+- case IMX_DMATYPE_ASRC_SP:
+ per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
+ emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
+ per_2_per = sdma->script_addrs->per_2_per_addr;
+@@ -774,12 +805,17 @@
+ case IMX_DMATYPE_IPU_MEMORY:
+ emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr;
+ break;
++ case IMX_DMATYPE_HDMI:
++ other = sdma->script_addrs->hdmi_dma_addr;
++ break;
+ default:
+ break;
+ }
+
+ sdmac->pc_from_device = per_2_emi;
+ sdmac->pc_to_device = emi_2_per;
++ sdmac->device_to_device = per_2_per;
++ sdmac->other_script = other;
+ }
+
+ static int sdma_load_context(struct sdma_channel *sdmac)
+@@ -792,11 +828,14 @@
+ int ret;
+ unsigned long flags;
+
+- if (sdmac->direction == DMA_DEV_TO_MEM) {
++ if (sdmac->direction == DMA_DEV_TO_MEM)
+ load_address = sdmac->pc_from_device;
+- } else {
++ else if (sdmac->direction == DMA_DEV_TO_DEV)
++ load_address = sdmac->device_to_device;
++ else if (sdmac->direction == DMA_MEM_TO_DEV)
+ load_address = sdmac->pc_to_device;
+- }
++ else
++ load_address = sdmac->other_script;
+
+ if (load_address < 0)
+ return load_address;
+@@ -816,11 +855,16 @@
+ /* Send by context the event mask,base address for peripheral
+ * and watermark level
+ */
+- context->gReg[0] = sdmac->event_mask[1];
+- context->gReg[1] = sdmac->event_mask[0];
+- context->gReg[2] = sdmac->per_addr;
+- context->gReg[6] = sdmac->shp_addr;
+- context->gReg[7] = sdmac->watermark_level;
++ if (sdmac->peripheral_type == IMX_DMATYPE_HDMI) {
++ context->gReg[4] = sdmac->data_addr1;
++ context->gReg[6] = sdmac->data_addr2;
++ } else {
++ context->gReg[0] = sdmac->event_mask[1];
++ context->gReg[1] = sdmac->event_mask[0];
++ context->gReg[2] = sdmac->per_addr;
++ context->gReg[6] = sdmac->shp_addr;
++ context->gReg[7] = sdmac->watermark_level;
++ }
+
+ bd0->mode.command = C0_SETDM;
+ bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
+@@ -854,6 +898,7 @@
+ static int sdma_config_channel(struct dma_chan *chan)
+ {
+ struct sdma_channel *sdmac = to_sdma_chan(chan);
++ struct imx_dma_data *data = sdmac->chan.private;
+ int ret;
+
+ sdma_disable_channel(chan);
+@@ -862,12 +907,19 @@
+ sdmac->event_mask[1] = 0;
+ sdmac->shp_addr = 0;
+ sdmac->per_addr = 0;
++ sdmac->data_addr1 = 0;
++ sdmac->data_addr2 = 0;
+
+- if (sdmac->event_id0) {
++ if (sdmac->event_id0 >= 0) {
+ if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events)
+ return -EINVAL;
+ sdma_event_enable(sdmac, sdmac->event_id0);
+ }
++ if (sdmac->event_id1) {
++ if (sdmac->event_id1 >= sdmac->sdma->drvdata->num_events)
++ return -EINVAL;
++ sdma_event_enable(sdmac, sdmac->event_id1);
++ }
+
+ switch (sdmac->peripheral_type) {
+ case IMX_DMATYPE_DSP:
+@@ -887,19 +939,75 @@
+ (sdmac->peripheral_type != IMX_DMATYPE_DSP)) {
+ /* Handle multiple event channels differently */
+ if (sdmac->event_id1) {
+- sdmac->event_mask[1] = BIT(sdmac->event_id1 % 32);
+- if (sdmac->event_id1 > 31)
+- __set_bit(31, &sdmac->watermark_level);
+- sdmac->event_mask[0] = BIT(sdmac->event_id0 % 32);
+- if (sdmac->event_id0 > 31)
+- __set_bit(30, &sdmac->watermark_level);
++ if (sdmac->event_id0 > 31) {
++ sdmac->event_mask[0] |= 0;
++ __set_bit(28, &sdmac->watermark_level);
++ sdmac->event_mask[1] |=
++ BIT(sdmac->event_id0 % 32);
++ } else {
++ sdmac->event_mask[1] |= 0;
++ sdmac->event_mask[0] |=
++ BIT(sdmac->event_id0 % 32);
++ }
++ if (sdmac->event_id1 > 31) {
++ sdmac->event_mask[0] |= 0;
++ __set_bit(29, &sdmac->watermark_level);
++ sdmac->event_mask[1] |=
++ BIT(sdmac->event_id1 % 32);
++ } else {
++ sdmac->event_mask[1] |= 0;
++ sdmac->event_mask[0] |=
++ BIT(sdmac->event_id1 % 32);
++ }
++ /* BIT 11:
++ * 1 : Source on SPBA
++ * 0 : Source on AIPS
++ */
++ __set_bit(11, &sdmac->watermark_level);
++ /* BIT 12:
++ * 1 : Destination on SPBA
++ * 0 : Destination on AIPS
++ */
++ __set_bit(12, &sdmac->watermark_level);
++ __set_bit(31, &sdmac->watermark_level);
++ /* BIT 31:
++ * 1 : Amount of samples to be transferred is
++ * unknown and script will keep on transferring
++ * samples as long as both events are detected
++ * and script must be manually stopped by the
++ * application.
++ * 0 : The amount of samples to be is equal to
++ * the count field of mode word
++ * */
++ __set_bit(25, &sdmac->watermark_level);
++ __clear_bit(24, &sdmac->watermark_level);
+ } else {
+- __set_bit(sdmac->event_id0, sdmac->event_mask);
++ if (sdmac->event_id0 > 31) {
++ sdmac->event_mask[0] = 0;
++ sdmac->event_mask[1] |=
++ BIT(sdmac->event_id0 % 32);
++ } else {
++ sdmac->event_mask[0] |=
++ BIT(sdmac->event_id0 % 32);
++ sdmac->event_mask[1] = 0;
++ }
+ }
+ /* Watermark Level */
+ sdmac->watermark_level |= sdmac->watermark_level;
+ /* Address */
+- sdmac->shp_addr = sdmac->per_address;
++ if (sdmac->direction == DMA_DEV_TO_DEV) {
++ sdmac->shp_addr = sdmac->per_address2;
++ sdmac->per_addr = sdmac->per_address;
++ } else if (sdmac->direction == DMA_TRANS_NONE) {
++ if (sdmac->peripheral_type != IMX_DMATYPE_HDMI ||
++ !data->data_addr1 || !data->data_addr2)
++ return -EINVAL;
++ sdmac->data_addr1 = *(u32 *)data->data_addr1;
++ sdmac->data_addr2 = *(u32 *)data->data_addr2;
++ sdmac->watermark_level = 0;
++ } else {
++ sdmac->shp_addr = sdmac->per_address;
++ }
+ } else {
+ sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */
+ }
+@@ -931,13 +1039,19 @@
+ int channel = sdmac->channel;
+ int ret = -EBUSY;
+
+- sdmac->bd = dma_zalloc_coherent(NULL, PAGE_SIZE, &sdmac->bd_phys,
+- GFP_KERNEL);
++ sdmac->bd_iram = true;
++ sdmac->bd = gen_pool_dma_alloc(sdma->iram_pool, PAGE_SIZE, &sdmac->bd_phys);
+ if (!sdmac->bd) {
+- ret = -ENOMEM;
+- goto out;
++ sdmac->bd_iram = false;
++ sdmac->bd = dma_alloc_coherent(NULL, PAGE_SIZE, &sdmac->bd_phys, GFP_KERNEL);
++ if (!sdmac->bd) {
++ ret = -ENOMEM;
++ goto out;
++ }
+ }
+
++ memset(sdmac->bd, 0, PAGE_SIZE);
++
+ sdma->channel_control[channel].base_bd_ptr = sdmac->bd_phys;
+ sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
+
+@@ -987,6 +1101,7 @@
+
+ sdmac->peripheral_type = data->peripheral_type;
+ sdmac->event_id0 = data->dma_request;
++ sdmac->event_id1 = data->dma_request2;
+
+ clk_enable(sdmac->sdma->clk_ipg);
+ clk_enable(sdmac->sdma->clk_ahb);
+@@ -1004,6 +1119,9 @@
+ /* txd.flags will be overwritten in prep funcs */
+ sdmac->desc.flags = DMA_CTRL_ACK;
+
++ /* Set SDMA channel mode to unvalid to avoid misconfig */
++ sdmac->mode = SDMA_MODE_INVALID;
++
+ return 0;
+ }
+
+@@ -1014,7 +1132,7 @@
+
+ sdma_disable_channel(chan);
+
+- if (sdmac->event_id0)
++ if (sdmac->event_id0 >= 0)
+ sdma_event_disable(sdmac, sdmac->event_id0);
+ if (sdmac->event_id1)
+ sdma_event_disable(sdmac, sdmac->event_id1);
+@@ -1024,7 +1142,10 @@
+
+ sdma_set_channel_priority(sdmac, 0);
+
+- dma_free_coherent(NULL, PAGE_SIZE, sdmac->bd, sdmac->bd_phys);
++ if (sdmac->bd_iram)
++ gen_pool_free(sdma->iram_pool, (unsigned long)sdmac->bd, PAGE_SIZE);
++ else
++ dma_free_coherent(NULL, PAGE_SIZE, sdmac->bd, sdmac->bd_phys);
+
+ clk_disable(sdma->clk_ipg);
+ clk_disable(sdma->clk_ahb);
+@@ -1045,7 +1166,7 @@
+ return NULL;
+ sdmac->status = DMA_IN_PROGRESS;
+
+- sdmac->flags = 0;
++ sdmac->mode = SDMA_MODE_NORMAL;
+
+ sdmac->buf_tail = 0;
+
+@@ -1134,13 +1255,13 @@
+ static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic(
+ struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
+ size_t period_len, enum dma_transfer_direction direction,
+- unsigned long flags)
++ unsigned long flags, void *context)
+ {
+ struct sdma_channel *sdmac = to_sdma_chan(chan);
+ struct sdma_engine *sdma = sdmac->sdma;
+- int num_periods = buf_len / period_len;
+ int channel = sdmac->channel;
+ int ret, i = 0, buf = 0;
++ int num_periods;
+
+ dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel);
+
+@@ -1152,12 +1273,33 @@
+ sdmac->buf_tail = 0;
+ sdmac->period_len = period_len;
+
+- sdmac->flags |= IMX_DMA_SG_LOOP;
+ sdmac->direction = direction;
++
++ switch (sdmac->direction) {
++ case DMA_DEV_TO_DEV:
++ sdmac->mode = SDMA_MODE_P2P;
++ break;
++ case DMA_TRANS_NONE:
++ sdmac->mode = SDMA_MODE_NO_BD;
++ break;
++ case DMA_MEM_TO_DEV:
++ case DMA_DEV_TO_MEM:
++ sdmac->mode = SDMA_MODE_LOOP;
++ break;
++ default:
++ dev_err(sdma->dev, "invalid SDMA direction %d\n", direction);
++ return NULL;
++ }
++
+ ret = sdma_load_context(sdmac);
+ if (ret)
+ goto err_out;
+
++ if (period_len)
++ num_periods = buf_len / period_len;
++ else
++ return &sdmac->desc;
++
+ if (num_periods > NUM_BD) {
+ dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
+ channel, num_periods, NUM_BD);
+@@ -1216,7 +1358,16 @@
+ {
+ struct sdma_channel *sdmac = to_sdma_chan(chan);
+
+- if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
++ if (dmaengine_cfg->direction == DMA_DEV_TO_DEV) {
++ sdmac->per_address = dmaengine_cfg->src_addr;
++ sdmac->per_address2 = dmaengine_cfg->dst_addr;
++ sdmac->watermark_level = 0;
++ sdmac->watermark_level |=
++ dmaengine_cfg->src_maxburst;
++ sdmac->watermark_level |=
++ dmaengine_cfg->dst_maxburst << 16;
++ sdmac->word_size = dmaengine_cfg->dst_addr_width;
++ } else if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
+ sdmac->per_address = dmaengine_cfg->src_addr;
+ sdmac->watermark_level = dmaengine_cfg->src_maxburst *
+ dmaengine_cfg->src_addr_width;
+@@ -1238,7 +1389,7 @@
+ struct sdma_channel *sdmac = to_sdma_chan(chan);
+ u32 residue;
+
+- if (sdmac->flags & IMX_DMA_SG_LOOP)
++ if (sdmac->mode & SDMA_MODE_LOOP)
+ residue = (sdmac->num_bd - sdmac->buf_tail) * sdmac->period_len;
+ else
+ residue = sdmac->chn_count - sdmac->chn_real_count;
+@@ -1286,8 +1437,7 @@
+ unsigned short *ram_code;
+
+ if (!fw) {
+- dev_info(sdma->dev, "external firmware not found, using ROM firmware\n");
+- /* In this case we just use the ROM firmware. */
++ dev_err(sdma->dev, "firmware not found\n");
+ return;
+ }
+
+@@ -1302,7 +1452,10 @@
+ goto err_firmware;
+ switch (header->version_major) {
+ case 1:
+- sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1;
++ if (header->version_minor > 0)
++ sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2;
++ else
++ sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1;
+ break;
+ case 2:
+ sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2;
+@@ -1337,7 +1490,7 @@
+ release_firmware(fw);
+ }
+
+-static int sdma_get_firmware(struct sdma_engine *sdma,
++static int __init sdma_get_firmware(struct sdma_engine *sdma,
+ const char *fw_name)
+ {
+ int ret;
+@@ -1349,9 +1502,9 @@
+ return ret;
+ }
+
+-static int sdma_init(struct sdma_engine *sdma)
++static int __init sdma_init(struct sdma_engine *sdma)
+ {
+- int i, ret;
++ int i, ret, ccbsize;
+ dma_addr_t ccb_phys;
+
+ clk_enable(sdma->clk_ipg);
+@@ -1360,14 +1513,17 @@
+ /* Be sure SDMA has not started yet */
+ writel_relaxed(0, sdma->regs + SDMA_H_C0PTR);
+
+- sdma->channel_control = dma_alloc_coherent(NULL,
+- MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) +
+- sizeof(struct sdma_context_data),
+- &ccb_phys, GFP_KERNEL);
++ ccbsize = MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control)
++ + sizeof(struct sdma_context_data);
+
++ sdma->channel_control = gen_pool_dma_alloc(sdma->iram_pool, ccbsize, &ccb_phys);
+ if (!sdma->channel_control) {
+- ret = -ENOMEM;
+- goto err_dma_alloc;
++ sdma->channel_control = dma_alloc_coherent(NULL, ccbsize,
++ &ccb_phys, GFP_KERNEL);
++ if (!sdma->channel_control) {
++ ret = -ENOMEM;
++ goto err_dma_alloc;
++ }
+ }
+
+ sdma->context = (void *)sdma->channel_control +
+@@ -1419,14 +1575,12 @@
+
+ static bool sdma_filter_fn(struct dma_chan *chan, void *fn_param)
+ {
+- struct sdma_channel *sdmac = to_sdma_chan(chan);
+ struct imx_dma_data *data = fn_param;
+
+ if (!imx_dma_is_general_purpose(chan))
+ return false;
+
+- sdmac->data = *data;
+- chan->private = &sdmac->data;
++ chan->private = data;
+
+ return true;
+ }
+@@ -1444,11 +1598,12 @@
+ data.dma_request = dma_spec->args[0];
+ data.peripheral_type = dma_spec->args[1];
+ data.priority = dma_spec->args[2];
++ data.dma_request2 = 0;
+
+ return dma_request_channel(mask, sdma_filter_fn, &data);
+ }
+
+-static int sdma_probe(struct platform_device *pdev)
++static int __init sdma_probe(struct platform_device *pdev)
+ {
+ const struct of_device_id *of_id =
+ of_match_device(sdma_dt_ids, &pdev->dev);
+@@ -1547,6 +1702,11 @@
+ &sdma->dma_device.channels);
+ }
+
++ if (np)
++ sdma->iram_pool = of_get_named_gen_pool(np, "iram", 0);
++ if (!sdma->iram_pool)
++ dev_warn(&pdev->dev, "no iram assigned, using external mem\n");
++
+ ret = sdma_init(sdma);
+ if (ret)
+ goto err_init;
+@@ -1583,7 +1743,7 @@
+ sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources;
+ sdma->dma_device.device_tx_status = sdma_tx_status;
+ sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg;
+- sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic;
++ sdma->dma_device.device_prep_dma_cyclic = (void*)sdma_prep_dma_cyclic;
+ sdma->dma_device.device_config = sdma_config;
+ sdma->dma_device.device_terminate_all = sdma_disable_channel;
+ sdma->dma_device.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
+@@ -1594,8 +1754,6 @@
+ sdma->dma_device.dev->dma_parms = &sdma->dma_parms;
+ dma_set_max_seg_size(sdma->dma_device.dev, 65535);
+
+- platform_set_drvdata(pdev, sdma);
+-
+ ret = dma_async_device_register(&sdma->dma_device);
+ if (ret) {
+ dev_err(&pdev->dev, "unable to register\n");
+@@ -1647,10 +1805,13 @@
+ },
+ .id_table = sdma_devtypes,
+ .remove = sdma_remove,
+- .probe = sdma_probe,
+ };
+
+-module_platform_driver(sdma_driver);
++static int __init sdma_module_init(void)
++{
++ return platform_driver_probe(&sdma_driver, sdma_probe);
++}
++module_init(sdma_module_init);
+
+ MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
+ MODULE_DESCRIPTION("i.MX SDMA driver");
+diff -Nur linux-4.1.3/drivers/gpu/drm/Kconfig linux-xbian-imx6/drivers/gpu/drm/Kconfig
+--- linux-4.1.3/drivers/gpu/drm/Kconfig 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/drivers/gpu/drm/Kconfig 2015-07-27 23:13:04.353449682 +0200
+@@ -217,3 +217,5 @@
+ source "drivers/gpu/drm/amd/amdkfd/Kconfig"
+
+ source "drivers/gpu/drm/imx/Kconfig"
++
++source "drivers/gpu/drm/vivante/Kconfig"
+diff -Nur linux-4.1.3/drivers/gpu/drm/Makefile linux-xbian-imx6/drivers/gpu/drm/Makefile
+--- linux-4.1.3/drivers/gpu/drm/Makefile 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/drivers/gpu/drm/Makefile 2015-07-27 23:13:04.353449682 +0200
+@@ -67,6 +67,7 @@
+ obj-$(CONFIG_DRM_TEGRA) += tegra/
+ obj-$(CONFIG_DRM_STI) += sti/
+ obj-$(CONFIG_DRM_IMX) += imx/
++obj-$(CONFIG_DRM_VIVANTE) += vivante/
+ obj-y += i2c/
+ obj-y += panel/
+ obj-y += bridge/
+diff -Nur linux-4.1.3/drivers/gpu/drm/vivante/Kconfig linux-xbian-imx6/drivers/gpu/drm/vivante/Kconfig
+--- linux-4.1.3/drivers/gpu/drm/vivante/Kconfig 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/gpu/drm/vivante/Kconfig 2015-07-27 23:13:04.744056042 +0200
+@@ -0,0 +1,6 @@
++config DRM_VIVANTE
++ tristate "Vivante GCCore"
++ depends on DRM
++ help
++ Choose this option if you have a Vivante graphics card.
++ If M is selected, the module will be called vivante.
+diff -Nur linux-4.1.3/drivers/gpu/drm/vivante/Makefile linux-xbian-imx6/drivers/gpu/drm/vivante/Makefile
+--- linux-4.1.3/drivers/gpu/drm/vivante/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/gpu/drm/vivante/Makefile 2015-07-27 23:13:04.744056042 +0200
+@@ -0,0 +1,29 @@
++##############################################################################
++#
++# Copyright (C) 2005 - 2013 by Vivante Corp.
++#
++# This program is free software; you can redistribute it and/or modify
++# it under the terms of the GNU General Public License as published by
++# the Free Software Foundation; either version 2 of the license, or
++# (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not write to the Free Software
++# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++#
++##############################################################################
++
++
++#
++# Makefile for the drm device driver. This driver provides support for the
++# Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
++
++ccflags-y := -Iinclude/drm
++vivante-y := vivante_drv.o
++
++obj-$(CONFIG_DRM_VIVANTE) += vivante.o
+diff -Nur linux-4.1.3/drivers/gpu/drm/vivante/vivante_drv.c linux-xbian-imx6/drivers/gpu/drm/vivante/vivante_drv.c
+--- linux-4.1.3/drivers/gpu/drm/vivante/vivante_drv.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/gpu/drm/vivante/vivante_drv.c 2015-07-27 23:13:04.744056042 +0200
+@@ -0,0 +1,112 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++/* vivante_drv.c -- vivante driver -*- linux-c -*-
++ *
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice (including the next
++ * paragraph) shall be included in all copies or substantial portions of the
++ * Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
++ * DEALINGS IN THE SOFTWARE.
++ *
++ * Authors:
++ * Rickard E. (Rik) Faith <faith@valinux.com>
++ * Daryll Strauss <daryll@valinux.com>
++ * Gareth Hughes <gareth@valinux.com>
++ */
++
++#include <linux/version.h>
++#include <linux/module.h>
++
++#include "drmP.h"
++#include "vivante_drv.h"
++
++#include "drm_pciids.h"
++
++static char platformdevicename[] = "Vivante GCCore";
++static struct platform_device *pplatformdev;
++
++static const struct file_operations viv_driver_fops = {
++ .owner = THIS_MODULE,
++ .open = drm_open,
++ .release = drm_release,
++ .unlocked_ioctl = drm_ioctl,
++ .mmap = drm_legacy_mmap,
++ .poll = drm_poll,
++ .llseek = noop_llseek,
++};
++
++static struct drm_driver driver = {
++// .driver_features = DRIVER_RENDER,
++ .fops = &viv_driver_fops,
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 18, 0)
++ .set_busid = drm_platform_set_busid,
++#endif
++ .name = DRIVER_NAME,
++ .desc = DRIVER_DESC,
++ .date = DRIVER_DATE,
++ .major = DRIVER_MAJOR,
++ .minor = DRIVER_MINOR,
++ .patchlevel = DRIVER_PATCHLEVEL,
++};
++
++static int __init vivante_init(void)
++{
++ int retcode;
++
++ pplatformdev = platform_device_register_simple(platformdevicename,
++ -1, NULL, 0);
++ if (pplatformdev == NULL)
++ printk(KERN_ERR"Platform device is null\n");
++
++ retcode = drm_platform_init(&driver, pplatformdev);
++
++ return retcode;
++}
++
++static void __exit vivante_exit(void)
++{
++ if (pplatformdev) {
++ platform_device_unregister(pplatformdev);
++ pplatformdev = NULL;
++ }
++}
++
++module_init(vivante_init);
++module_exit(vivante_exit);
++
++MODULE_AUTHOR(DRIVER_AUTHOR);
++MODULE_DESCRIPTION(DRIVER_DESC);
++MODULE_LICENSE("GPL and additional rights");
+diff -Nur linux-4.1.3/drivers/gpu/drm/vivante/vivante_drv.h linux-xbian-imx6/drivers/gpu/drm/vivante/vivante_drv.h
+--- linux-4.1.3/drivers/gpu/drm/vivante/vivante_drv.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/gpu/drm/vivante/vivante_drv.h 2015-07-27 23:13:04.744056042 +0200
+@@ -0,0 +1,69 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++/* vivante_drv.h -- Vivante DRM template customization -*- linux-c -*-
++ * Created: Wed Feb 14 12:32:32 2012 by John Zhao
++ */
++/*
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice (including the next
++ * paragraph) shall be included in all copies or substantial portions of the
++ * Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors:
++ * Gareth Hughes <gareth@valinux.com>
++ */
++
++#ifndef __VIVANTE_DRV_H__
++#define __VIVANTE_DRV_H__
++
++/* General customization:
++ */
++
++#include <drm/drm_legacy.h>
++#include <drm/drm_mm.h>
++
++#define DRIVER_AUTHOR "Vivante Inc."
++
++#define DRIVER_NAME "vivante"
++#define DRIVER_DESC "Vivante GCCore"
++#define DRIVER_DATE "20120216"
++
++#define DRIVER_MAJOR 1
++#define DRIVER_MINOR 0
++#define DRIVER_PATCHLEVEL 0
++
++#endif
+diff -Nur linux-4.1.3/drivers/Kconfig linux-xbian-imx6/drivers/Kconfig
+--- linux-4.1.3/drivers/Kconfig 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/drivers/Kconfig 2015-07-27 23:13:03.699781896 +0200
+@@ -182,4 +182,6 @@
+
+ source "drivers/android/Kconfig"
+
++source "drivers/mxc/Kconfig"
++
+ endmenu
+diff -Nur linux-4.1.3/drivers/Makefile linux-xbian-imx6/drivers/Makefile
+--- linux-4.1.3/drivers/Makefile 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/drivers/Makefile 2015-07-27 23:13:03.699781896 +0200
+@@ -165,3 +165,4 @@
+ obj-$(CONFIG_THUNDERBOLT) += thunderbolt/
+ obj-$(CONFIG_CORESIGHT) += hwtracing/coresight/
+ obj-$(CONFIG_ANDROID) += android/
++obj-y += mxc/
+diff -Nur linux-4.1.3/drivers/mfd/Kconfig linux-xbian-imx6/drivers/mfd/Kconfig
+--- linux-4.1.3/drivers/mfd/Kconfig 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/drivers/mfd/Kconfig 2015-07-27 23:13:06.023491162 +0200
+@@ -207,6 +207,13 @@
+ Additional drivers must be enabled in order to use the specific
+ features of the device.
+
++config MFD_MXC_HDMI
++ tristate "Freescale HDMI Core"
++ select MFD_CORE
++ help
++ This is the core driver for the Freescale i.MX6 on-chip HDMI.
++ This MFD driver connects with the video and audio drivers for HDMI.
++
+ config MFD_DLN2
+ tristate "Diolan DLN2 support"
+ select MFD_CORE
+diff -Nur linux-4.1.3/drivers/mfd/Makefile linux-xbian-imx6/drivers/mfd/Makefile
+--- linux-4.1.3/drivers/mfd/Makefile 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/drivers/mfd/Makefile 2015-07-27 23:13:06.023491162 +0200
+@@ -185,3 +185,4 @@
+ intel-soc-pmic-objs := intel_soc_pmic_core.o intel_soc_pmic_crc.o
+ obj-$(CONFIG_INTEL_SOC_PMIC) += intel-soc-pmic.o
+ obj-$(CONFIG_MFD_MT6397) += mt6397-core.o
++obj-$(CONFIG_MFD_MXC_HDMI) += mxc-hdmi-core.o
+diff -Nur linux-4.1.3/drivers/mfd/mxc-hdmi-core.c linux-xbian-imx6/drivers/mfd/mxc-hdmi-core.c
+--- linux-4.1.3/drivers/mfd/mxc-hdmi-core.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mfd/mxc-hdmi-core.c 2015-07-27 23:13:06.051391618 +0200
+@@ -0,0 +1,723 @@
++/*
++ * Copyright (C) 2011-2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ */
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/slab.h>
++#include <linux/device.h>
++#include <linux/err.h>
++#include <linux/io.h>
++#include <linux/clk.h>
++#include <linux/spinlock.h>
++#include <linux/irq.h>
++#include <linux/interrupt.h>
++
++#include <linux/platform_device.h>
++#include <linux/regulator/machine.h>
++#include <asm/mach-types.h>
++
++#include <video/mxc_hdmi.h>
++#include <linux/ipu-v3.h>
++#include <video/mxc_edid.h>
++#include "../mxc/ipu3/ipu_prv.h"
++#include <linux/mfd/mxc-hdmi-core.h>
++#include <linux/of_device.h>
++#include <linux/mod_devicetable.h>
++
++struct mxc_hdmi_data {
++ struct platform_device *pdev;
++ unsigned long __iomem *reg_base;
++ unsigned long reg_phys_base;
++ struct device *dev;
++};
++
++static void __iomem *hdmi_base;
++static struct clk *isfr_clk;
++static struct clk *iahb_clk;
++static spinlock_t irq_spinlock;
++static spinlock_t edid_spinlock;
++static unsigned int sample_rate;
++static unsigned long pixel_clk_rate;
++static struct clk *pixel_clk;
++static int hdmi_ratio;
++int mxc_hdmi_ipu_id;
++int mxc_hdmi_disp_id;
++static int hdmi_core_edid_status;
++static struct mxc_edid_cfg hdmi_core_edid_cfg;
++static int hdmi_core_init;
++static unsigned int hdmi_dma_running;
++static struct snd_pcm_substream *hdmi_audio_stream_playback;
++static unsigned int hdmi_cable_state;
++static unsigned int hdmi_blank_state;
++static unsigned int hdmi_abort_state;
++static spinlock_t hdmi_audio_lock, hdmi_blank_state_lock, hdmi_cable_state_lock;
++
++void hdmi_set_dvi_mode(unsigned int state)
++{
++ if (state) {
++ mxc_hdmi_abort_stream();
++ hdmi_cec_stop_device();
++ } else {
++ hdmi_cec_start_device();
++ }
++}
++EXPORT_SYMBOL(hdmi_set_dvi_mode);
++
++unsigned int hdmi_set_cable_state(unsigned int state)
++{
++ unsigned long flags;
++ struct snd_pcm_substream *substream = hdmi_audio_stream_playback;
++
++ spin_lock_irqsave(&hdmi_cable_state_lock, flags);
++ hdmi_cable_state = state;
++ spin_unlock_irqrestore(&hdmi_cable_state_lock, flags);
++
++ if (check_hdmi_state() && substream && hdmi_abort_state) {
++ hdmi_abort_state = 0;
++ substream->ops->trigger(substream, SNDRV_PCM_TRIGGER_START);
++ }
++ return 0;
++}
++EXPORT_SYMBOL(hdmi_set_cable_state);
++
++unsigned int hdmi_set_blank_state(unsigned int state)
++{
++ unsigned long flags;
++ struct snd_pcm_substream *substream = hdmi_audio_stream_playback;
++
++ spin_lock_irqsave(&hdmi_blank_state_lock, flags);
++ hdmi_blank_state = state;
++ spin_unlock_irqrestore(&hdmi_blank_state_lock, flags);
++
++ if (check_hdmi_state() && substream && hdmi_abort_state) {
++ hdmi_abort_state = 0;
++ substream->ops->trigger(substream, SNDRV_PCM_TRIGGER_START);
++ }
++ return 0;
++}
++EXPORT_SYMBOL(hdmi_set_blank_state);
++
++static void hdmi_audio_abort_stream(struct snd_pcm_substream *substream)
++{
++ unsigned long flags;
++
++ snd_pcm_stream_lock_irqsave(substream, flags);
++
++ if (snd_pcm_running(substream)) {
++ hdmi_abort_state = 1;
++ substream->ops->trigger(substream, SNDRV_PCM_TRIGGER_STOP);
++ }
++
++ snd_pcm_stream_unlock_irqrestore(substream, flags);
++}
++
++int mxc_hdmi_abort_stream(void)
++{
++ unsigned long flags;
++ spin_lock_irqsave(&hdmi_audio_lock, flags);
++ if (hdmi_audio_stream_playback)
++ hdmi_audio_abort_stream(hdmi_audio_stream_playback);
++ spin_unlock_irqrestore(&hdmi_audio_lock, flags);
++
++ return 0;
++}
++EXPORT_SYMBOL(mxc_hdmi_abort_stream);
++
++int check_hdmi_state(void)
++{
++ unsigned long flags1, flags2;
++ unsigned int ret;
++
++ spin_lock_irqsave(&hdmi_cable_state_lock, flags1);
++ spin_lock_irqsave(&hdmi_blank_state_lock, flags2);
++
++ ret = hdmi_cable_state && hdmi_blank_state;
++
++ spin_unlock_irqrestore(&hdmi_blank_state_lock, flags2);
++ spin_unlock_irqrestore(&hdmi_cable_state_lock, flags1);
++
++ return ret;
++}
++EXPORT_SYMBOL(check_hdmi_state);
++
++int mxc_hdmi_register_audio(struct snd_pcm_substream *substream)
++{
++ unsigned long flags, flags1;
++ int ret = 0;
++
++ snd_pcm_stream_lock_irqsave(substream, flags);
++
++ if (substream && check_hdmi_state()) {
++ spin_lock_irqsave(&hdmi_audio_lock, flags1);
++ if (hdmi_audio_stream_playback) {
++ pr_err("%s unconsist hdmi auido stream!\n", __func__);
++ ret = -EINVAL;
++ }
++ hdmi_audio_stream_playback = substream;
++ hdmi_abort_state = 0;
++ spin_unlock_irqrestore(&hdmi_audio_lock, flags1);
++ } else
++ ret = -EINVAL;
++
++ snd_pcm_stream_unlock_irqrestore(substream, flags);
++
++ return ret;
++}
++EXPORT_SYMBOL(mxc_hdmi_register_audio);
++
++void mxc_hdmi_unregister_audio(struct snd_pcm_substream *substream)
++{
++ unsigned long flags;
++
++ spin_lock_irqsave(&hdmi_audio_lock, flags);
++ hdmi_audio_stream_playback = NULL;
++ hdmi_abort_state = 0;
++ spin_unlock_irqrestore(&hdmi_audio_lock, flags);
++}
++EXPORT_SYMBOL(mxc_hdmi_unregister_audio);
++
++u8 hdmi_readb(unsigned int reg)
++{
++ u8 value;
++
++ value = __raw_readb(hdmi_base + reg);
++
++ return value;
++}
++EXPORT_SYMBOL(hdmi_readb);
++
++#ifdef DEBUG
++static bool overflow_lo;
++static bool overflow_hi;
++
++bool hdmi_check_overflow(void)
++{
++ u8 val, lo, hi;
++
++ val = hdmi_readb(HDMI_IH_FC_STAT2);
++ lo = (val & HDMI_IH_FC_STAT2_LOW_PRIORITY_OVERFLOW) != 0;
++ hi = (val & HDMI_IH_FC_STAT2_HIGH_PRIORITY_OVERFLOW) != 0;
++
++ if ((lo != overflow_lo) || (hi != overflow_hi)) {
++ pr_debug("%s LowPriority=%d HighPriority=%d <=======================\n",
++ __func__, lo, hi);
++ overflow_lo = lo;
++ overflow_hi = hi;
++ return true;
++ }
++ return false;
++}
++#else
++bool hdmi_check_overflow(void)
++{
++ return false;
++}
++#endif
++EXPORT_SYMBOL(hdmi_check_overflow);
++
++void hdmi_writeb(u8 value, unsigned int reg)
++{
++ hdmi_check_overflow();
++ __raw_writeb(value, hdmi_base + reg);
++ hdmi_check_overflow();
++}
++EXPORT_SYMBOL(hdmi_writeb);
++
++void hdmi_mask_writeb(u8 data, unsigned int reg, u8 shift, u8 mask)
++{
++ u8 value = hdmi_readb(reg) & ~mask;
++ value |= (data << shift) & mask;
++ hdmi_writeb(value, reg);
++}
++EXPORT_SYMBOL(hdmi_mask_writeb);
++
++unsigned int hdmi_read4(unsigned int reg)
++{
++ /* read a four byte address from registers */
++ return (hdmi_readb(reg + 3) << 24) |
++ (hdmi_readb(reg + 2) << 16) |
++ (hdmi_readb(reg + 1) << 8) |
++ hdmi_readb(reg);
++}
++EXPORT_SYMBOL(hdmi_read4);
++
++void hdmi_write4(unsigned int value, unsigned int reg)
++{
++ /* write a four byte address to hdmi regs */
++ hdmi_writeb(value & 0xff, reg);
++ hdmi_writeb((value >> 8) & 0xff, reg + 1);
++ hdmi_writeb((value >> 16) & 0xff, reg + 2);
++ hdmi_writeb((value >> 24) & 0xff, reg + 3);
++}
++EXPORT_SYMBOL(hdmi_write4);
++
++static void initialize_hdmi_ih_mutes(void)
++{
++ u8 ih_mute;
++
++ /*
++ * Boot up defaults are:
++ * HDMI_IH_MUTE = 0x03 (disabled)
++ * HDMI_IH_MUTE_* = 0x00 (enabled)
++ */
++
++ /* Disable top level interrupt bits in HDMI block */
++ ih_mute = hdmi_readb(HDMI_IH_MUTE) |
++ HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
++ HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
++
++ hdmi_writeb(ih_mute, HDMI_IH_MUTE);
++
++ /* by default mask all interrupts */
++ hdmi_writeb(0xff, HDMI_VP_MASK);
++ hdmi_writeb(0xff, HDMI_FC_MASK0);
++ hdmi_writeb(0xff, HDMI_FC_MASK1);
++ hdmi_writeb(0xff, HDMI_FC_MASK2);
++ hdmi_writeb(0xff, HDMI_PHY_MASK0);
++ hdmi_writeb(0xff, HDMI_PHY_I2CM_INT_ADDR);
++ hdmi_writeb(0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
++ hdmi_writeb(0xff, HDMI_AUD_INT);
++ hdmi_writeb(0xff, HDMI_AUD_SPDIFINT);
++ hdmi_writeb(0xff, HDMI_AUD_HBR_MASK);
++ hdmi_writeb(0xff, HDMI_GP_MASK);
++ hdmi_writeb(0xff, HDMI_A_APIINTMSK);
++ hdmi_writeb(0xff, HDMI_CEC_MASK);
++ hdmi_writeb(0xff, HDMI_I2CM_INT);
++ hdmi_writeb(0xff, HDMI_I2CM_CTLINT);
++
++ /* Disable interrupts in the IH_MUTE_* registers */
++ hdmi_writeb(0xff, HDMI_IH_MUTE_FC_STAT0);
++ hdmi_writeb(0xff, HDMI_IH_MUTE_FC_STAT1);
++ hdmi_writeb(0xff, HDMI_IH_MUTE_FC_STAT2);
++ hdmi_writeb(0xff, HDMI_IH_MUTE_AS_STAT0);
++ hdmi_writeb(0xff, HDMI_IH_MUTE_PHY_STAT0);
++ hdmi_writeb(0xff, HDMI_IH_MUTE_I2CM_STAT0);
++ hdmi_writeb(0xff, HDMI_IH_MUTE_CEC_STAT0);
++ hdmi_writeb(0xff, HDMI_IH_MUTE_VP_STAT0);
++ hdmi_writeb(0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
++ hdmi_writeb(0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
++
++ /* Enable top level interrupt bits in HDMI block */
++ ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
++ HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
++ hdmi_writeb(ih_mute, HDMI_IH_MUTE);
++}
++
++static void hdmi_set_clock_regenerator_n(unsigned int value)
++{
++ u8 val;
++
++ if (!hdmi_dma_running) {
++ hdmi_writeb(value & 0xff, HDMI_AUD_N1);
++ hdmi_writeb(0, HDMI_AUD_N2);
++ hdmi_writeb(0, HDMI_AUD_N3);
++ }
++
++ hdmi_writeb(value & 0xff, HDMI_AUD_N1);
++ hdmi_writeb((value >> 8) & 0xff, HDMI_AUD_N2);
++ hdmi_writeb((value >> 16) & 0x0f, HDMI_AUD_N3);
++
++ /* nshift factor = 0 */
++ val = hdmi_readb(HDMI_AUD_CTS3);
++ val &= ~HDMI_AUD_CTS3_N_SHIFT_MASK;
++ hdmi_writeb(val, HDMI_AUD_CTS3);
++}
++
++static void hdmi_set_clock_regenerator_cts(unsigned int cts)
++{
++ u8 val;
++
++ if (!hdmi_dma_running) {
++ hdmi_writeb(cts & 0xff, HDMI_AUD_CTS1);
++ hdmi_writeb(0, HDMI_AUD_CTS2);
++ hdmi_writeb(0, HDMI_AUD_CTS3);
++ }
++
++ /* Must be set/cleared first */
++ val = hdmi_readb(HDMI_AUD_CTS3);
++ val &= ~HDMI_AUD_CTS3_CTS_MANUAL;
++ hdmi_writeb(val, HDMI_AUD_CTS3);
++
++ hdmi_writeb(cts & 0xff, HDMI_AUD_CTS1);
++ hdmi_writeb((cts >> 8) & 0xff, HDMI_AUD_CTS2);
++ hdmi_writeb(((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
++ HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
++}
++
++struct imx6_hdmi_acr {
++ int FREQ;
++ int N;
++ int CTS;
++};
++
++struct imx6_hdmi_acr_def {
++ int CLK;
++ struct imx6_hdmi_acr imx6_data[3];
++};
++
++static const struct imx6_hdmi_acr_def imx6_hdmi_conv[] = {
++ /* 32kHz 44.1kHz 48kHz */
++ /* Clock N CTS N CTS N CTS */
++ { 2517/*5*/, { { 32000, 4096, 25175 }, { 44100, 28224, 125875 }, { 48000, 6144, 25175 } } }, /* 25,20/1.001 MHz */
++ { 2520/*0*/, { { 32000, 4096, 25200 }, { 44100, 6272, 28000 }, { 48000, 6144, 25200 } } }, /* 25.20 MHz */
++ { 2700/*0*/, { { 32000, 4096, 27000 }, { 44100, 6272, 30000 }, { 48000, 6144, 27000 } } }, /* 27.00 MHz */
++ { 2702/*7*/, { { 32000, 4096, 27027 }, { 44100, 6272, 30030 }, { 48000, 6144, 27027 } } }, /* 27.00*1.001 MHz */
++ { 5400/*0*/, { { 32000, 4096, 54000 }, { 44100, 6272, 60000 }, { 48000, 6144, 54000 } } }, /* 54.00 MHz */
++ { 5405/*4*/, { { 32000, 4096, 54054 }, { 44100, 6272, 60060 }, { 48000, 6144, 54054 } } }, /* 54.00*1.001 MHz */
++ { 7417/*6*/, { { 32000, 4096, 74176 }, { 44100, 5733, 75335 }, { 48000, 6144, 74176 } } }, /* 74.25/1.001 MHz */
++ { 7425/*0*/, { { 32000, 4096, 74250 }, { 44100, 6272, 82500 }, { 48000, 6144, 74250 } } }, /* 74.25 MHz */
++ {14836/*2*/, { { 32000, 4096, 148352 }, { 44100, 5733, 150670 }, { 48000, 6144, 148352 } } }, /* 148.50/1.001 MHz */
++ {14850/*0*/, { { 32000, 4096, 148500 }, { 44100, 6272, 165000 }, { 48000, 6144, 148500 } } }, /* 148.50 MHz */
++ { 0, { { 32000, 4096, 0 }, { 44100, 6272, 0 }, { 48000, 6144, 0 } } } /* Other */
++};
++
++static void hdmi_compute_cts_n(unsigned int freq, unsigned long pixel_clk,
++ unsigned int *n, unsigned int *cts)
++{
++ unsigned int clk = pixel_clk / 10000;
++ unsigned int frq = freq;
++ int i, j;
++
++ *n = 1;
++ switch (frq) {
++ case 88200:
++ frq = 44100;
++ *n = 2;
++ break;
++ case 96000:
++ frq = 48000;
++ *n = 2;
++ break;
++ case 176400:
++ frq = 44100;
++ *n = 4;
++ break;
++ case 192000:
++ frq = 48000;
++ *n = 4;
++ break;
++ default:
++ break;
++ }
++
++ for (i = 0; i < ARRAY_SIZE(imx6_hdmi_conv); i++) {
++ if (imx6_hdmi_conv[i].CLK == clk || imx6_hdmi_conv[i].CLK == 0) {
++ for (j = 0; j < 3; j++) {
++ if (imx6_hdmi_conv[i].imx6_data[j].FREQ == frq) {
++ *n *= imx6_hdmi_conv[i].imx6_data[j].N;
++ *cts = imx6_hdmi_conv[i].imx6_data[j].CTS;
++ return;
++ }
++ }
++ }
++ }
++}
++
++static void hdmi_set_clk_regenerator(void)
++{
++ unsigned int clk_n, clk_cts = 0;
++
++ hdmi_compute_cts_n(sample_rate, pixel_clk_rate, &clk_n, &clk_cts);
++
++ if (clk_cts == 0) {
++ clk_n = (128 * sample_rate) / 1000;
++ clk_cts = (clk_n / 128) * pixel_clk_rate;
++ clk_cts += (clk_n % 128) * pixel_clk_rate / 128;
++ clk_cts /= (sample_rate / 10);
++ pr_debug("%s: pixel clock not supported - fallback calculation: %d, N=%d, cts: %d\n",
++ __func__, (int)pixel_clk_rate, clk_n, clk_cts);
++ }
++// if (ratio != 100)
++// clk_cts = (clk_cts * ratio) / 100;
++
++ pr_debug("%s: samplerate=%d ratio=%d pixelclk=%d N=%d cts=%d\n",
++ __func__, sample_rate, hdmi_ratio, (int)pixel_clk_rate,
++ clk_n, clk_cts);
++
++ hdmi_set_clock_regenerator_cts(clk_cts);
++ hdmi_set_clock_regenerator_n(clk_n);
++}
++
++static int hdmi_core_get_of_property(struct platform_device *pdev)
++{
++ struct device_node *np = pdev->dev.of_node;
++ int err;
++ int ipu_id, disp_id;
++
++ err = of_property_read_u32(np, "ipu_id", &ipu_id);
++ if (err) {
++ dev_dbg(&pdev->dev, "get of property ipu_id fail\n");
++ return err;
++ }
++ err = of_property_read_u32(np, "disp_id", &disp_id);
++ if (err) {
++ dev_dbg(&pdev->dev, "get of property disp_id fail\n");
++ return err;
++ }
++
++ mxc_hdmi_ipu_id = ipu_id;
++ mxc_hdmi_disp_id = disp_id;
++
++ return err;
++}
++
++/* Need to run this before phy is enabled the first time to prevent
++ * overflow condition in HDMI_IH_FC_STAT2 */
++void hdmi_init_clk_regenerator(void)
++{
++ if (pixel_clk_rate == 0) {
++ pixel_clk_rate = 74250000;
++ hdmi_set_clk_regenerator();
++ }
++}
++EXPORT_SYMBOL(hdmi_init_clk_regenerator);
++
++void hdmi_clk_regenerator_update_pixel_clock(u32 pixclock)
++{
++
++ /* Translate pixel clock in ps (pico seconds) to Hz */
++ pixel_clk_rate = PICOS2KHZ(pixclock) * 1000UL;
++ hdmi_set_clk_regenerator();
++}
++EXPORT_SYMBOL(hdmi_clk_regenerator_update_pixel_clock);
++
++void hdmi_set_dma_mode(unsigned int dma_running)
++{
++ hdmi_dma_running = dma_running;
++ hdmi_set_clk_regenerator();
++}
++EXPORT_SYMBOL(hdmi_set_dma_mode);
++
++void hdmi_set_sample_rate(unsigned int rate)
++{
++ sample_rate = rate;
++}
++EXPORT_SYMBOL(hdmi_set_sample_rate);
++
++void hdmi_set_edid_cfg(int edid_status, struct mxc_edid_cfg *cfg)
++{
++ unsigned long flags;
++
++ spin_lock_irqsave(&edid_spinlock, flags);
++ hdmi_core_edid_status = edid_status;
++ memcpy(&hdmi_core_edid_cfg, cfg, sizeof(struct mxc_edid_cfg));
++ spin_unlock_irqrestore(&edid_spinlock, flags);
++}
++EXPORT_SYMBOL(hdmi_set_edid_cfg);
++
++int hdmi_get_edid_cfg(struct mxc_edid_cfg *cfg)
++{
++ unsigned long flags;
++
++ spin_lock_irqsave(&edid_spinlock, flags);
++ memcpy(cfg, &hdmi_core_edid_cfg, sizeof(struct mxc_edid_cfg));
++ spin_unlock_irqrestore(&edid_spinlock, flags);
++
++ return hdmi_core_edid_status;
++}
++EXPORT_SYMBOL(hdmi_get_edid_cfg);
++
++void hdmi_set_registered(int registered)
++{
++ hdmi_core_init = registered;
++}
++EXPORT_SYMBOL(hdmi_set_registered);
++
++int hdmi_get_registered(void)
++{
++ return hdmi_core_init;
++}
++EXPORT_SYMBOL(hdmi_get_registered);
++
++static int mxc_hdmi_core_probe(struct platform_device *pdev)
++{
++ struct mxc_hdmi_data *hdmi_data;
++ struct resource *res;
++ unsigned long flags;
++ int ret = 0;
++
++#ifdef DEBUG
++ overflow_lo = false;
++ overflow_hi = false;
++#endif
++
++ hdmi_core_init = 0;
++ hdmi_dma_running = 0;
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (!res)
++ return -ENOENT;
++
++ ret = hdmi_core_get_of_property(pdev);
++ if (ret < 0) {
++ dev_err(&pdev->dev, "get hdmi of property fail\n");
++ return -ENOENT;
++ }
++
++ hdmi_data = devm_kzalloc(&pdev->dev, sizeof(struct mxc_hdmi_data), GFP_KERNEL);
++ if (!hdmi_data) {
++ dev_err(&pdev->dev, "Couldn't allocate mxc hdmi mfd device\n");
++ return -ENOMEM;
++ }
++ hdmi_data->pdev = pdev;
++
++ pixel_clk = NULL;
++ sample_rate = 48000;
++ pixel_clk_rate = 0;
++ hdmi_ratio = 100;
++
++ spin_lock_init(&irq_spinlock);
++ spin_lock_init(&edid_spinlock);
++
++
++ spin_lock_init(&hdmi_cable_state_lock);
++ spin_lock_init(&hdmi_blank_state_lock);
++ spin_lock_init(&hdmi_audio_lock);
++
++ spin_lock_irqsave(&hdmi_cable_state_lock, flags);
++ hdmi_cable_state = 0;
++ spin_unlock_irqrestore(&hdmi_cable_state_lock, flags);
++
++ spin_lock_irqsave(&hdmi_blank_state_lock, flags);
++ hdmi_blank_state = 0;
++ spin_unlock_irqrestore(&hdmi_blank_state_lock, flags);
++
++ spin_lock_irqsave(&hdmi_audio_lock, flags);
++ hdmi_audio_stream_playback = NULL;
++ hdmi_abort_state = 0;
++ spin_unlock_irqrestore(&hdmi_audio_lock, flags);
++
++ isfr_clk = clk_get(&hdmi_data->pdev->dev, "hdmi_isfr");
++ if (IS_ERR(isfr_clk)) {
++ ret = PTR_ERR(isfr_clk);
++ dev_err(&hdmi_data->pdev->dev,
++ "Unable to get HDMI isfr clk: %d\n", ret);
++ goto eclkg;
++ }
++
++ ret = clk_prepare_enable(isfr_clk);
++ if (ret < 0) {
++ dev_err(&pdev->dev, "Cannot enable HDMI clock: %d\n", ret);
++ goto eclke;
++ }
++
++ pr_debug("%s isfr_clk:%d\n", __func__,
++ (int)clk_get_rate(isfr_clk));
++
++ iahb_clk = clk_get(&hdmi_data->pdev->dev, "hdmi_iahb");
++ if (IS_ERR(iahb_clk)) {
++ ret = PTR_ERR(iahb_clk);
++ dev_err(&hdmi_data->pdev->dev,
++ "Unable to get HDMI iahb clk: %d\n", ret);
++ goto eclkg2;
++ }
++
++ ret = clk_prepare_enable(iahb_clk);
++ if (ret < 0) {
++ dev_err(&pdev->dev, "Cannot enable HDMI clock: %d\n", ret);
++ goto eclke2;
++ }
++
++ hdmi_data->reg_phys_base = res->start;
++ if (!request_mem_region(res->start, resource_size(res),
++ dev_name(&pdev->dev))) {
++ dev_err(&pdev->dev, "request_mem_region failed\n");
++ ret = -EBUSY;
++ goto emem;
++ }
++
++ hdmi_data->reg_base = ioremap(res->start, resource_size(res));
++ if (!hdmi_data->reg_base) {
++ dev_err(&pdev->dev, "ioremap failed\n");
++ ret = -ENOMEM;
++ goto eirq;
++ }
++ hdmi_base = hdmi_data->reg_base;
++
++ pr_debug("\n%s hdmi hw base = 0x%08x\n\n", __func__, (int)res->start);
++
++ initialize_hdmi_ih_mutes();
++
++ /* Disable HDMI clocks until video/audio sub-drivers are initialized */
++ clk_disable_unprepare(isfr_clk);
++ clk_disable_unprepare(iahb_clk);
++
++ /* Replace platform data coming in with a local struct */
++ platform_set_drvdata(pdev, hdmi_data);
++
++ return ret;
++
++eirq:
++ release_mem_region(res->start, resource_size(res));
++emem:
++ clk_disable_unprepare(iahb_clk);
++eclke2:
++ clk_put(iahb_clk);
++eclkg2:
++ clk_disable_unprepare(isfr_clk);
++eclke:
++ clk_put(isfr_clk);
++eclkg:
++ return ret;
++}
++
++
++static int __exit mxc_hdmi_core_remove(struct platform_device *pdev)
++{
++ struct mxc_hdmi_data *hdmi_data = platform_get_drvdata(pdev);
++ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++
++ iounmap(hdmi_data->reg_base);
++ release_mem_region(res->start, resource_size(res));
++
++ return 0;
++}
++
++static const struct of_device_id imx_hdmi_dt_ids[] = {
++ { .compatible = "fsl,imx6q-hdmi-core", },
++ { .compatible = "fsl,imx6dl-hdmi-core", },
++ { /* sentinel */ }
++};
++
++static struct platform_driver mxc_hdmi_core_driver = {
++ .driver = {
++ .name = "mxc_hdmi_core",
++ .of_match_table = imx_hdmi_dt_ids,
++ .owner = THIS_MODULE,
++ },
++ .remove = __exit_p(mxc_hdmi_core_remove),
++};
++
++static int __init mxc_hdmi_core_init(void)
++{
++ return platform_driver_probe(&mxc_hdmi_core_driver,
++ mxc_hdmi_core_probe);
++}
++
++static void __exit mxc_hdmi_core_exit(void)
++{
++ platform_driver_unregister(&mxc_hdmi_core_driver);
++}
++
++subsys_initcall(mxc_hdmi_core_init);
++module_exit(mxc_hdmi_core_exit);
++
++MODULE_DESCRIPTION("Core driver for Freescale i.Mx on-chip HDMI");
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_LICENSE("GPL");
+diff -Nur linux-4.1.3/drivers/misc/sram.c linux-xbian-imx6/drivers/misc/sram.c
+--- linux-4.1.3/drivers/misc/sram.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/drivers/misc/sram.c 2015-07-27 23:13:06.095235186 +0200
+@@ -17,6 +17,7 @@
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
++#define DEBUG
+
+ #include <linux/kernel.h>
+ #include <linux/init.h>
+diff -Nur linux-4.1.3/drivers/mmc/core/core.c linux-xbian-imx6/drivers/mmc/core/core.c
+--- linux-4.1.3/drivers/mmc/core/core.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/drivers/mmc/core/core.c 2015-07-27 23:13:06.115164084 +0200
+@@ -13,11 +13,13 @@
+ #include <linux/module.h>
+ #include <linux/init.h>
+ #include <linux/interrupt.h>
++#include <linux/clk.h>
+ #include <linux/completion.h>
+ #include <linux/device.h>
+ #include <linux/delay.h>
+ #include <linux/pagemap.h>
+ #include <linux/err.h>
++#include <linux/gpio/consumer.h>
+ #include <linux/leds.h>
+ #include <linux/scatterlist.h>
+ #include <linux/log2.h>
+@@ -1601,6 +1603,43 @@
+ mmc_host_clk_release(host);
+ }
+
++static void mmc_card_power_up(struct mmc_host *host)
++{
++ int i;
++ struct gpio_desc **gds = host->card_reset_gpios;
++
++ for (i = 0; i < ARRAY_SIZE(host->card_reset_gpios); i++) {
++ if (gds[i]) {
++ dev_dbg(host->parent, "Asserting reset line %d", i);
++ gpiod_set_value(gds[i], 1);
++ }
++ }
++
++ if (host->card_regulator) {
++ dev_dbg(host->parent, "Enabling external regulator");
++ if (regulator_enable(host->card_regulator))
++ dev_err(host->parent, "Failed to enable external regulator");
++ }
++
++ if (host->card_clk) {
++ dev_dbg(host->parent, "Enabling external clock");
++ clk_prepare_enable(host->card_clk);
++ }
++
++ /* 2ms delay to let clocks and power settle */
++ mmc_delay(20);
++
++ for (i = 0; i < ARRAY_SIZE(host->card_reset_gpios); i++) {
++ if (gds[i]) {
++ dev_dbg(host->parent, "Deasserting reset line %d", i);
++ gpiod_set_value(gds[i], 0);
++ }
++ }
++
++ /* 2ms delay to after reset release */
++ mmc_delay(20);
++}
++
+ /*
+ * Apply power to the MMC stack. This is a two-stage process.
+ * First, we enable power to the card without the clock running.
+@@ -1661,6 +1700,9 @@
+ if (host->ios.power_mode == MMC_POWER_OFF)
+ return;
+
++ /* Power up the card/module first, if needed */
++ mmc_card_power_up(host);
++
+ mmc_host_clk_hold(host);
+
+ mmc_pwrseq_power_off(host);
+@@ -1686,7 +1728,7 @@
+ {
+ mmc_power_off(host);
+ /* Wait at least 1 ms according to SD spec */
+- mmc_delay(1);
++ mmc_delay(3);
+ mmc_power_up(host, ocr);
+ }
+
+diff -Nur linux-4.1.3/drivers/mmc/core/host.c linux-xbian-imx6/drivers/mmc/core/host.c
+--- linux-4.1.3/drivers/mmc/core/host.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/drivers/mmc/core/host.c 2015-07-27 23:13:06.115164084 +0200
+@@ -12,14 +12,18 @@
+ * MMC host class device management
+ */
+
++#include <linux/kernel.h>
++#include <linux/clk.h>
+ #include <linux/device.h>
+ #include <linux/err.h>
++#include <linux/gpio/consumer.h>
+ #include <linux/idr.h>
+ #include <linux/of.h>
+ #include <linux/of_gpio.h>
+ #include <linux/pagemap.h>
+ #include <linux/export.h>
+ #include <linux/leds.h>
++#include <linux/regulator/consumer.h>
+ #include <linux/slab.h>
+ #include <linux/suspend.h>
+
+@@ -454,6 +458,66 @@
+
+ EXPORT_SYMBOL(mmc_of_parse);
+
++static int mmc_of_parse_child(struct mmc_host *host)
++{
++ struct device_node *np;
++ struct clk *clk;
++ int i;
++
++ if (!host->parent || !host->parent->of_node)
++ return 0;
++
++ np = host->parent->of_node;
++
++ host->card_regulator = regulator_get(host->parent, "card-external-vcc");
++ if (IS_ERR(host->card_regulator)) {
++ if (PTR_ERR(host->card_regulator) == -EPROBE_DEFER)
++ return PTR_ERR(host->card_regulator);
++ host->card_regulator = NULL;
++ }
++
++ /* Parse card power/reset/clock control */
++ if (of_find_property(np, "card-reset-gpios", NULL)) {
++ struct gpio_desc *gpd;
++ int level = 0;
++
++ /*
++ * If the regulator is enabled, then we can hold the
++ * card in reset with an active high resets. Otherwise,
++ * hold the resets low.
++ */
++ if (host->card_regulator && regulator_is_enabled(host->card_regulator))
++ level = 1;
++
++ for (i = 0; i < ARRAY_SIZE(host->card_reset_gpios); i++) {
++ gpd = devm_gpiod_get_index(host->parent, "card-reset", i);
++ if (IS_ERR(gpd)) {
++ if (PTR_ERR(gpd) == -EPROBE_DEFER)
++ return PTR_ERR(gpd);
++ break;
++ }
++ gpiod_direction_output(gpd, gpiod_is_active_low(gpd) | level);
++ host->card_reset_gpios[i] = gpd;
++ }
++
++ gpd = devm_gpiod_get_index(host->parent, "card-reset", ARRAY_SIZE(host->card_reset_gpios));
++ if (!IS_ERR(gpd)) {
++ dev_warn(host->parent, "More reset gpios than we can handle");
++ gpiod_put(gpd);
++ }
++ }
++
++ clk = of_clk_get_by_name(np, "card_ext_clock");
++ if (IS_ERR(clk)) {
++ if (PTR_ERR(clk) == -EPROBE_DEFER)
++ return PTR_ERR(clk);
++ clk = NULL;
++ }
++ host->card_clk = clk;
++
++ return 0;
++}
++
+ /**
+ * mmc_alloc_host - initialise the per-host structure.
+ * @extra: sizeof private data structure
+@@ -533,6 +597,10 @@
+ {
+ int err;
+
++ err = mmc_of_parse_child(host);
++ if (err)
++ return err;
++
+ WARN_ON((host->caps & MMC_CAP_SDIO_IRQ) &&
+ !host->ops->enable_sdio_irq);
+
+diff -Nur linux-4.1.3/drivers/mmc/core/mmc_ops.c linux-xbian-imx6/drivers/mmc/core/mmc_ops.c
+--- linux-4.1.3/drivers/mmc/core/mmc_ops.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/drivers/mmc/core/mmc_ops.c 2015-07-27 23:13:06.115164084 +0200
+@@ -513,6 +513,12 @@
+ return 0;
+
+ /*
++ * WORKAROUND: for Sandisk eMMC cards, it might need certain delay
++ * before sending CMD13 after CMD6
++ */
++ mdelay(1);
++
++ /*
+ * CRC errors shall only be ignored in cases were CMD13 is used to poll
+ * to detect busy completion.
+ */
+diff -Nur linux-4.1.3/drivers/mmc/core/sd.c linux-xbian-imx6/drivers/mmc/core/sd.c
+--- linux-4.1.3/drivers/mmc/core/sd.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/drivers/mmc/core/sd.c 2015-07-27 23:13:06.119149862 +0200
+@@ -521,6 +521,13 @@
+ else {
+ mmc_set_timing(card->host, timing);
+ mmc_set_clock(card->host, card->sw_caps.uhs_max_dtr);
++
++ /*
++ * FIXME: Sandisk SD3.0 cards DDR50 mode requires such
++ * delay to get stable, without this delay we may encounter
++ * CRC errors after switch to DDR50 mode
++ */
++ mmc_delay(100);
+ }
+
+ return 0;
+diff -Nur linux-4.1.3/drivers/mmc/host/sdhci-esdhc-imx.c linux-xbian-imx6/drivers/mmc/host/sdhci-esdhc-imx.c
+--- linux-4.1.3/drivers/mmc/host/sdhci-esdhc-imx.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/drivers/mmc/host/sdhci-esdhc-imx.c 2015-07-27 23:13:06.131107202 +0200
+@@ -65,6 +65,8 @@
+ /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
+ #define ESDHC_TUNING_START_TAP 0x1
+
++#define ESDHC_TUNING_BLOCK_PATTERN_LEN 64
++
+ /* pinctrl state */
+ #define ESDHC_PINCTRL_STATE_100MHZ "state_100mhz"
+ #define ESDHC_PINCTRL_STATE_200MHZ "state_200mhz"
+@@ -112,6 +114,12 @@
+ #define ESDHC_FLAG_STD_TUNING BIT(5)
+ /* The IP has SDHCI_CAPABILITIES_1 register */
+ #define ESDHC_FLAG_HAVE_CAP1 BIT(6)
++/*
++ * The IP has errata ERR004536
++ * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow,
++ * when reading data from the card
++ */
++#define ESDHC_FLAG_ERR004536 BIT(7)
+
+ struct esdhc_soc_data {
+ u32 flags;
+@@ -445,6 +453,10 @@
+ if (val & SDHCI_CTRL_EXEC_TUNING) {
+ v |= ESDHC_MIX_CTRL_EXE_TUNE;
+ m |= ESDHC_MIX_CTRL_FBCLK_SEL;
++ writel(readl(host->ioaddr + ESDHC_TUNING_CTRL) |
++ ESDHC_STD_TUNING_EN |
++ ESDHC_TUNING_START_TAP,
++ host->ioaddr + ESDHC_TUNING_CTRL);
+ } else {
+ v &= ~ESDHC_MIX_CTRL_EXE_TUNE;
+ }
+@@ -700,6 +712,56 @@
+ val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS));
+ }
+
++static void esdhc_request_done(struct mmc_request *mrq)
++{
++ complete(&mrq->completion);
++}
++
++static int esdhc_send_tuning_cmd(struct sdhci_host *host, u32 opcode,
++ struct scatterlist *sg)
++{
++ struct mmc_command cmd = {0};
++ struct mmc_request mrq = {NULL};
++ struct mmc_data data = {0};
++
++ cmd.opcode = opcode;
++ cmd.arg = 0;
++ cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
++
++ data.blksz = ESDHC_TUNING_BLOCK_PATTERN_LEN;
++ data.blocks = 1;
++ data.flags = MMC_DATA_READ;
++ data.sg = sg;
++ data.sg_len = 1;
++
++ mrq.cmd = &cmd;
++ mrq.cmd->mrq = &mrq;
++ mrq.data = &data;
++ mrq.data->mrq = &mrq;
++ mrq.cmd->data = mrq.data;
++
++ mrq.done = esdhc_request_done;
++ init_completion(&(mrq.completion));
++
++ disable_irq(host->irq);
++ spin_lock(&host->lock);
++ host->mrq = &mrq;
++
++ sdhci_send_command(host, mrq.cmd);
++
++ spin_unlock(&host->lock);
++ enable_irq(host->irq);
++
++ wait_for_completion(&mrq.completion);
++
++ if (cmd.error)
++ return cmd.error;
++ if (data.error)
++ return data.error;
++
++ return 0;
++}
++
+ static void esdhc_post_tuning(struct sdhci_host *host)
+ {
+ u32 reg;
+@@ -711,13 +773,21 @@
+
+ static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode)
+ {
++ struct scatterlist sg;
++ char *tuning_pattern;
+ int min, max, avg, ret;
+
++ tuning_pattern = kmalloc(ESDHC_TUNING_BLOCK_PATTERN_LEN, GFP_KERNEL);
++ if (!tuning_pattern)
++ return -ENOMEM;
++
++ sg_init_one(&sg, tuning_pattern, ESDHC_TUNING_BLOCK_PATTERN_LEN);
++
+ /* find the mininum delay first which can pass tuning */
+ min = ESDHC_TUNE_CTRL_MIN;
+ while (min < ESDHC_TUNE_CTRL_MAX) {
+ esdhc_prepare_tuning(host, min);
+- if (!mmc_send_tuning(host->mmc))
++ if (!esdhc_send_tuning_cmd(host, opcode, &sg))
+ break;
+ min += ESDHC_TUNE_CTRL_STEP;
+ }
+@@ -726,7 +796,7 @@
+ max = min + ESDHC_TUNE_CTRL_STEP;
+ while (max < ESDHC_TUNE_CTRL_MAX) {
+ esdhc_prepare_tuning(host, max);
+- if (mmc_send_tuning(host->mmc)) {
++ if (esdhc_send_tuning_cmd(host, opcode, &sg)) {
+ max -= ESDHC_TUNE_CTRL_STEP;
+ break;
+ }
+@@ -736,9 +806,11 @@
+ /* use average delay to get the best timing */
+ avg = (min + max) / 2;
+ esdhc_prepare_tuning(host, avg);
+- ret = mmc_send_tuning(host->mmc);
++ ret = esdhc_send_tuning_cmd(host, opcode, &sg);
+ esdhc_post_tuning(host);
+
++ kfree(tuning_pattern);
++
+ dev_dbg(mmc_dev(host->mmc), "tunning %s at 0x%x ret %d\n",
+ ret ? "failed" : "passed", avg, ret);
+
+@@ -901,6 +973,9 @@
+ if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line))
+ boarddata->delay_line = 0;
+
++ if (of_find_property(np, "keep-power-in-suspend", NULL))
++ host->mmc->pm_caps |= MMC_PM_KEEP_POWER;
++
+ mmc_of_parse_voltage(np, &host->ocr_mask);
+
+ return 0;
+@@ -997,10 +1072,8 @@
+ sdhci_esdhc_ops.platform_execute_tuning =
+ esdhc_executing_tuning;
+
+- if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING)
+- writel(readl(host->ioaddr + ESDHC_TUNING_CTRL) |
+- ESDHC_STD_TUNING_EN | ESDHC_TUNING_START_TAP,
+- host->ioaddr + ESDHC_TUNING_CTRL);
++ if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536)
++ host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
+
+ boarddata = &imx_data->boarddata;
+ if (sdhci_esdhc_imx_probe_dt(pdev, host, boarddata) < 0) {
+diff -Nur linux-4.1.3/drivers/mxc/asrc/Kconfig linux-xbian-imx6/drivers/mxc/asrc/Kconfig
+--- linux-4.1.3/drivers/mxc/asrc/Kconfig 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/asrc/Kconfig 2015-07-27 23:13:06.166979215 +0200
+@@ -0,0 +1,14 @@
++#
++# ASRC configuration
++#
++
++menu "MXC Asynchronous Sample Rate Converter support"
++
++config MXC_ASRC
++ tristate "ASRC support"
++ depends on SOC_IMX35 || SOC_IMX53 || SOC_IMX6
++# select SND_SOC_FSL_ASRC
++ ---help---
++ Say Y to get the ASRC service.
++
++endmenu
+diff -Nur linux-4.1.3/drivers/mxc/asrc/Makefile linux-xbian-imx6/drivers/mxc/asrc/Makefile
+--- linux-4.1.3/drivers/mxc/asrc/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/asrc/Makefile 2015-07-27 23:13:06.166979215 +0200
+@@ -0,0 +1,4 @@
++#
++# Makefile for the kernel Asynchronous Sample Rate Converter driver
++#
++obj-$(CONFIG_MXC_ASRC) += mxc_asrc.o
+diff -Nur linux-4.1.3/drivers/mxc/asrc/mxc_asrc.c linux-xbian-imx6/drivers/mxc/asrc/mxc_asrc.c
+--- linux-4.1.3/drivers/mxc/asrc/mxc_asrc.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/asrc/mxc_asrc.c 2015-07-27 23:13:06.166979215 +0200
+@@ -0,0 +1,2045 @@
++/*
++ * Freescale Asynchronous Sample Rate Converter (ASRC) driver
++ *
++ * Copyright 2008-2014 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This file is licensed under the terms of the GNU General Public License
++ * version 2. This program is licensed "as is" without any warranty of any
++ * kind, whether express or implied.
++ */
++
++#include <linux/clk.h>
++#include <linux/slab.h>
++#include <linux/delay.h>
++#include <linux/sched.h>
++#include <linux/regmap.h>
++#include <linux/module.h>
++#include <linux/proc_fs.h>
++#include <linux/pagemap.h>
++#include <linux/interrupt.h>
++#include <linux/miscdevice.h>
++#include <linux/dma-mapping.h>
++#include <linux/of_platform.h>
++#include <linux/platform_data/dma-imx.h>
++
++#include <linux/mxc_asrc.h>
++
++#define ASRC_PROC_PATH "driver/asrc"
++
++#define ASRC_RATIO_DECIMAL_DEPTH 26
++
++#define pair_err(fmt, ...) \
++ dev_err(asrc->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__)
++
++#define pair_dbg(fmt, ...) \
++ dev_dbg(asrc->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__)
++
++DEFINE_SPINLOCK(data_lock);
++DEFINE_SPINLOCK(pair_lock);
++
++/* Sample rates are aligned with that defined in pcm.h file */
++static const unsigned char asrc_process_table[][8][2] = {
++ /* 32kHz 44.1kHz 48kHz 64kHz 88.2kHz 96kHz 176kHz 192kHz */
++ {{0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, /* 5512Hz */
++ {{0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, /* 8kHz */
++ {{0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, /* 11025Hz */
++ {{0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, /* 16kHz */
++ {{0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, /* 22050Hz */
++ {{0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0},}, /* 32kHz */
++ {{0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0},}, /* 44.1kHz */
++ {{0, 2}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0},}, /* 48kHz */
++ {{1, 2}, {0, 2}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0},}, /* 64kHz */
++ {{1, 2}, {1, 2}, {1, 2}, {1, 1}, {1, 1}, {1, 1}, {1, 1}, {1, 1},}, /* 88.2kHz */
++ {{1, 2}, {1, 2}, {1, 2}, {1, 1}, {1, 1}, {1, 1}, {1, 1}, {1, 1},}, /* 96kHz */
++ {{2, 2}, {2, 2}, {2, 2}, {2, 1}, {2, 1}, {2, 1}, {2, 1}, {2, 1},}, /* 176kHz */
++ {{2, 2}, {2, 2}, {2, 2}, {2, 1}, {2, 1}, {2, 1}, {2, 1}, {2, 1},}, /* 192kHz */
++};
++
++static struct asrc_data *asrc;
++
++/*
++ * The following tables map the relationship between asrc_inclk/asrc_outclk in
++ * mxc_asrc.h and the registers of ASRCSR
++ */
++static unsigned char input_clk_map_v1[] = {
++ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf,
++};
++
++static unsigned char output_clk_map_v1[] = {
++ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf,
++};
++
++/* V2 uses the same map for input and output */
++static unsigned char input_clk_map_v2[] = {
++/* 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf */
++ 0x0, 0x1, 0x2, 0x7, 0x4, 0x5, 0x6, 0x3, 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0xe, 0xd,
++};
++
++static unsigned char output_clk_map_v2[] = {
++/* 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf */
++ 0x8, 0x9, 0xa, 0x7, 0xc, 0x5, 0x6, 0xb, 0x0, 0x1, 0x2, 0x3, 0x4, 0xf, 0xe, 0xd,
++};
++
++static unsigned char *input_clk_map, *output_clk_map;
++
++enum mxc_asrc_type {
++ IMX35_ASRC,
++ IMX53_ASRC,
++};
++
++static const struct platform_device_id mxc_asrc_devtype[] = {
++ {
++ .name = "imx35-asrc",
++ .driver_data = IMX35_ASRC,
++ }, {
++ .name = "imx53-asrc",
++ .driver_data = IMX53_ASRC,
++ }, {
++ /* sentinel */
++ }
++};
++MODULE_DEVICE_TABLE(platform, mxc_asrc_devtype);
++
++static const struct of_device_id fsl_asrc_ids[] = {
++ {
++ .compatible = "fsl,imx35-asrc",
++ .data = &mxc_asrc_devtype[IMX35_ASRC],
++ }, {
++ .compatible = "fsl,imx53-asrc",
++ .data = &mxc_asrc_devtype[IMX53_ASRC],
++ }, {
++ /* sentinel */
++ }
++};
++MODULE_DEVICE_TABLE(of, fsl_asrc_ids);
++
++
++#ifdef DEBUG
++u32 asrc_reg[] = {
++ REG_ASRCTR,
++ REG_ASRIER,
++ REG_ASRCNCR,
++ REG_ASRCFG,
++ REG_ASRCSR,
++ REG_ASRCDR1,
++ REG_ASRCDR2,
++ REG_ASRSTR,
++ REG_ASRRA,
++ REG_ASRRB,
++ REG_ASRRC,
++ REG_ASRPM1,
++ REG_ASRPM2,
++ REG_ASRPM3,
++ REG_ASRPM4,
++ REG_ASRPM5,
++ REG_ASRTFR1,
++ REG_ASRCCR,
++ REG_ASRIDRHA,
++ REG_ASRIDRLA,
++ REG_ASRIDRHB,
++ REG_ASRIDRLB,
++ REG_ASRIDRHC,
++ REG_ASRIDRLC,
++ REG_ASR76K,
++ REG_ASR56K,
++ REG_ASRMCRA,
++ REG_ASRFSTA,
++ REG_ASRMCRB,
++ REG_ASRFSTB,
++ REG_ASRMCRC,
++ REG_ASRFSTC,
++ REG_ASRMCR1A,
++ REG_ASRMCR1B,
++ REG_ASRMCR1C,
++};
++
++static void dump_regs(void)
++{
++ u32 reg, val;
++ int i;
++
++ for (i = 0; i < ARRAY_SIZE(asrc_reg); i++) {
++ reg = asrc_reg[i];
++ regmap_read(asrc->regmap, reg, &val);
++ dev_dbg(asrc->dev, "REG addr=0x%x val=0x%x\n", reg, val);
++ }
++}
++#else
++static void dump_regs(void) {}
++#endif
++
++/* Only used for Ideal Ratio mode */
++static int asrc_set_clock_ratio(enum asrc_pair_index index,
++ int inrate, int outrate)
++{
++ unsigned long val = 0;
++ int integ, i;
++
++ if (outrate == 0) {
++ dev_err(asrc->dev, "wrong output sample rate: %d\n", outrate);
++ return -EINVAL;
++ }
++
++ /* Formula: r = (1 << ASRC_RATIO_DECIMAL_DEPTH) / outrate * inrate; */
++ for (integ = 0; inrate >= outrate; integ++)
++ inrate -= outrate;
++
++ val |= (integ << ASRC_RATIO_DECIMAL_DEPTH);
++
++ for (i = 1; i <= ASRC_RATIO_DECIMAL_DEPTH; i++) {
++ if ((inrate * 2) >= outrate) {
++ val |= (1 << (ASRC_RATIO_DECIMAL_DEPTH - i));
++ inrate = inrate * 2 - outrate;
++ } else
++ inrate = inrate << 1;
++
++ if (inrate == 0)
++ break;
++ }
++
++ regmap_write(asrc->regmap, REG_ASRIDRL(index), val);
++ regmap_write(asrc->regmap, REG_ASRIDRH(index), (val >> 24));
++
++ return 0;
++}
++
++/* Corresponding to asrc_process_table */
++static int supported_input_rate[] = {
++ 5512, 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000, 88200,
++ 96000, 176400, 192000,
++};
++
++static int supported_output_rate[] = {
++ 32000, 44100, 48000, 64000, 88200, 96000, 176400, 192000,
++};
++
++static int asrc_set_process_configuration(enum asrc_pair_index index,
++ int inrate, int outrate)
++{
++ int in, out;
++
++ for (in = 0; in < ARRAY_SIZE(supported_input_rate); in++) {
++ if (inrate == supported_input_rate[in])
++ break;
++ }
++
++ if (in == ARRAY_SIZE(supported_input_rate)) {
++ dev_err(asrc->dev, "unsupported input sample rate: %d\n", in);
++ return -EINVAL;
++ }
++
++ for (out = 0; out < ARRAY_SIZE(supported_output_rate); out++) {
++ if (outrate == supported_output_rate[out])
++ break;
++ }
++
++ if (out == ARRAY_SIZE(supported_output_rate)) {
++ dev_err(asrc->dev, "unsupported output sample rate: %d\n", out);
++ return -EINVAL;
++ }
++
++ regmap_update_bits(asrc->regmap, REG_ASRCFG,
++ ASRCFG_PREMODx_MASK(index) | ASRCFG_POSTMODx_MASK(index),
++ ASRCFG_PREMOD(index, asrc_process_table[in][out][0]) |
++ ASRCFG_POSTMOD(index, asrc_process_table[in][out][1]));
++
++ return 0;
++}
++
++static int asrc_get_asrck_clock_divider(int samplerate)
++{
++ unsigned int prescaler, divider, ratio, ra, i;
++ unsigned long bitclk;
++
++ if (samplerate == 0) {
++ dev_err(asrc->dev, "invalid sample rate: %d\n", samplerate);
++ return -EINVAL;
++ }
++
++ bitclk = clk_get_rate(asrc->asrck_clk);
++
++ ra = bitclk / samplerate;
++ ratio = ra;
++
++ /* Calculate the prescaler */
++ for (i = 0; ratio > 8; i++)
++ ratio >>= 1;
++
++ prescaler = i;
++
++ /* Calculate the divider */
++ divider = i ? (((ra + (1 << (i - 1)) - 1) >> i) - 1) : (ra - 1);
++
++ /* The totally divider is (2 ^ prescaler) * divider */
++ return (divider << ASRCDRx_AxCPx_WIDTH) + prescaler;
++}
++
++int asrc_req_pair(int chn_num, enum asrc_pair_index *index)
++{
++ int imax = 0, busy = 0, i, ret = 0;
++ unsigned long lock_flags;
++ struct asrc_pair *pair;
++
++ spin_lock_irqsave(&data_lock, lock_flags);
++
++ for (i = ASRC_PAIR_A; i < ASRC_PAIR_MAX_NUM; i++) {
++ pair = &asrc->asrc_pair[i];
++ if (chn_num > pair->chn_max) {
++ imax++;
++ continue;
++ } else if (pair->active) {
++ busy++;
++ continue;
++ }
++ /* Save the current qualified pair */
++ *index = i;
++
++ /* Check if this pair is a perfect one */
++ if (chn_num == pair->chn_max)
++ break;
++ }
++
++ if (imax == ASRC_PAIR_MAX_NUM) {
++ dev_err(asrc->dev, "no pair could afford required channel number\n");
++ ret = -EINVAL;
++ } else if (busy == ASRC_PAIR_MAX_NUM) {
++ dev_err(asrc->dev, "all pairs are busy now\n");
++ ret = -EBUSY;
++ } else if (busy + imax >= ASRC_PAIR_MAX_NUM) {
++ dev_err(asrc->dev, "all affordable pairs are busy now\n");
++ ret = -EBUSY;
++ } else {
++ pair = &asrc->asrc_pair[*index];
++ pair->chn_num = chn_num;
++ pair->active = 1;
++ }
++
++ spin_unlock_irqrestore(&data_lock, lock_flags);
++
++ if (!ret) {
++ clk_prepare_enable(asrc->mem_clk);
++ clk_prepare_enable(asrc->ipg_clk);
++ clk_prepare_enable(asrc->asrck_clk);
++ clk_prepare_enable(asrc->dma_clk);
++ }
++
++ return ret;
++}
++EXPORT_SYMBOL(asrc_req_pair);
++
++void asrc_release_pair(enum asrc_pair_index index)
++{
++ struct asrc_pair *pair = &asrc->asrc_pair[index];
++ unsigned long lock_flags;
++
++ spin_lock_irqsave(&data_lock, lock_flags);
++
++ pair->active = 0;
++ pair->overload_error = 0;
++
++ spin_unlock_irqrestore(&data_lock, lock_flags);
++
++ /* Disable PAIR */
++ regmap_update_bits(asrc->regmap, REG_ASRCTR, ASRCTR_ASRCEx_MASK(index), 0);
++}
++EXPORT_SYMBOL(asrc_release_pair);
++
++int asrc_config_pair(struct asrc_config *config)
++{
++ u32 inrate = config->input_sample_rate, indiv;
++ u32 outrate = config->output_sample_rate, outdiv;
++ int ret, channels, index = config->pair;
++ unsigned long lock_flags;
++
++ /* Set the channel number */
++ spin_lock_irqsave(&data_lock, lock_flags);
++ asrc->asrc_pair[index].chn_num = config->channel_num;
++ spin_unlock_irqrestore(&data_lock, lock_flags);
++
++ if (asrc->channel_bits > 3)
++ channels = config->channel_num;
++ else
++ channels = (config->channel_num + 1) / 2;
++
++ /* Update channel number of current pair */
++ regmap_update_bits(asrc->regmap, REG_ASRCNCR,
++ ASRCNCR_ANCx_MASK(index, asrc->channel_bits),
++ ASRCNCR_ANCx_set(index, channels, asrc->channel_bits));
++
++ /* Set the clock source */
++ regmap_update_bits(asrc->regmap, REG_ASRCSR,
++ ASRCSR_AICSx_MASK(index) | ASRCSR_AOCSx_MASK(index),
++ ASRCSR_AICS(index, input_clk_map[config->inclk]) |
++ ASRCSR_AOCS(index, output_clk_map[config->outclk]));
++
++ /* Default setting: Automatic selection for processing mode */
++ regmap_update_bits(asrc->regmap, REG_ASRCTR,
++ ASRCTR_ATSx_MASK(index), ASRCTR_ATS(index));
++ regmap_update_bits(asrc->regmap, REG_ASRCTR, ASRCTR_USRx_MASK(index), 0);
++
++ /* Default Input Clock Divider Setting */
++ switch (config->inclk & ASRCSR_AxCSx_MASK) {
++ case INCLK_SPDIF_RX:
++ indiv = ASRC_PRESCALER_SPDIF_RX;
++ break;
++ case INCLK_SPDIF_TX:
++ indiv = ASRC_PRESCALER_SPDIF_TX;
++ break;
++ case INCLK_ASRCK1_CLK:
++ indiv = asrc_get_asrck_clock_divider(inrate);
++ break;
++ default:
++ switch (config->input_word_width) {
++ case ASRC_WIDTH_16_BIT:
++ indiv = ASRC_PRESCALER_I2S_16BIT;
++ break;
++ case ASRC_WIDTH_24_BIT:
++ indiv = ASRC_PRESCALER_I2S_24BIT;
++ break;
++ default:
++ pair_err("unsupported input word width %d\n",
++ config->input_word_width);
++ return -EINVAL;
++ }
++ break;
++ }
++
++ /* Default Output Clock Divider Setting */
++ switch (config->outclk & ASRCSR_AxCSx_MASK) {
++ case OUTCLK_SPDIF_RX:
++ outdiv = ASRC_PRESCALER_SPDIF_RX;
++ break;
++ case OUTCLK_SPDIF_TX:
++ outdiv = ASRC_PRESCALER_SPDIF_TX;
++ break;
++ case OUTCLK_ASRCK1_CLK:
++ if ((config->inclk & ASRCSR_AxCSx_MASK) == INCLK_NONE)
++ outdiv = ASRC_PRESCALER_IDEAL_RATIO;
++ else
++ outdiv = asrc_get_asrck_clock_divider(outrate);
++ break;
++ default:
++ switch (config->output_word_width) {
++ case ASRC_WIDTH_16_BIT:
++ outdiv = ASRC_PRESCALER_I2S_16BIT;
++ break;
++ case ASRC_WIDTH_24_BIT:
++ outdiv = ASRC_PRESCALER_I2S_24BIT;
++ break;
++ default:
++ pair_err("unsupported output word width %d\n",
++ config->input_word_width);
++ return -EINVAL;
++ }
++ break;
++ }
++
++ /* indiv and outdiv'd include prescaler's value, so add its MASK too */
++ regmap_update_bits(asrc->regmap, REG_ASRCDR(index),
++ ASRCDRx_AOCPx_MASK(index) | ASRCDRx_AICPx_MASK(index) |
++ ASRCDRx_AOCDx_MASK(index) | ASRCDRx_AICDx_MASK(index),
++ ASRCDRx_AOCP(index, outdiv) | ASRCDRx_AICP(index, indiv));
++
++ /* Check whether ideal ratio is a must */
++ switch (config->inclk & ASRCSR_AxCSx_MASK) {
++ case INCLK_NONE:
++ /* Clear ASTSx bit to use ideal ratio */
++ regmap_update_bits(asrc->regmap, REG_ASRCTR,
++ ASRCTR_ATSx_MASK(index), 0);
++
++ regmap_update_bits(asrc->regmap, REG_ASRCTR,
++ ASRCTR_IDRx_MASK(index) | ASRCTR_USRx_MASK(index),
++ ASRCTR_IDR(index) | ASRCTR_USR(index));
++
++ ret = asrc_set_clock_ratio(index, inrate, outrate);
++ if (ret)
++ return ret;
++
++ ret = asrc_set_process_configuration(index, inrate, outrate);
++ if (ret)
++ return ret;
++
++ break;
++ case INCLK_ASRCK1_CLK:
++ /* This case and default are both remained for v1 */
++ if (inrate == 44100 || inrate == 88200) {
++ pair_err("unsupported sample rate %d by selected clock\n",
++ inrate);
++ return -EINVAL;
++ }
++ break;
++ default:
++ if ((config->outclk & ASRCSR_AxCSx_MASK) != OUTCLK_ASRCK1_CLK)
++ break;
++
++ if (outrate == 44100 || outrate == 88200) {
++ pair_err("unsupported sample rate %d by selected clock\n",
++ outrate);
++ return -EINVAL;
++ }
++ break;
++ }
++
++ /* Config input and output wordwidth */
++ if (config->output_word_width == ASRC_WIDTH_8_BIT) {
++ pair_err("unsupported wordwidth for output: 8bit\n");
++ pair_err("output only support: 16bit or 24bit\n");
++ return -EINVAL;
++ }
++
++ regmap_update_bits(asrc->regmap, REG_ASRMCR1(index),
++ ASRMCR1x_OW16_MASK | ASRMCR1x_IWD_MASK,
++ ASRMCR1x_OW16(config->output_word_width) |
++ ASRMCR1x_IWD(config->input_word_width));
++
++ /* Enable BUFFER STALL */
++ regmap_update_bits(asrc->regmap, REG_ASRMCR(index),
++ ASRMCRx_BUFSTALLx_MASK, ASRMCRx_BUFSTALLx);
++
++ /* Set Threshold for input and output FIFO */
++ return asrc_set_watermark(index, ASRC_INPUTFIFO_THRESHOLD,
++ ASRC_INPUTFIFO_THRESHOLD);
++}
++EXPORT_SYMBOL(asrc_config_pair);
++
++int asrc_set_watermark(enum asrc_pair_index index, u32 in_wm, u32 out_wm)
++{
++ if (in_wm > ASRC_FIFO_THRESHOLD_MAX || out_wm > ASRC_FIFO_THRESHOLD_MAX) {
++ pair_err("invalid watermark!\n");
++ return -EINVAL;
++ }
++
++ return regmap_update_bits(asrc->regmap, REG_ASRMCR(index),
++ ASRMCRx_EXTTHRSHx_MASK | ASRMCRx_INFIFO_THRESHOLD_MASK |
++ ASRMCRx_OUTFIFO_THRESHOLD_MASK,
++ ASRMCRx_EXTTHRSHx | ASRMCRx_INFIFO_THRESHOLD(in_wm) |
++ ASRMCRx_OUTFIFO_THRESHOLD(out_wm));
++}
++EXPORT_SYMBOL(asrc_set_watermark);
++
++void asrc_start_conv(enum asrc_pair_index index)
++{
++ int reg, retry, channels, i;
++
++ regmap_update_bits(asrc->regmap, REG_ASRCTR,
++ ASRCTR_ASRCEx_MASK(index), ASRCTR_ASRCE(index));
++
++ /* Wait for status of initialization */
++ for (retry = 10, reg = 0; !reg && retry; --retry) {
++ udelay(5);
++ regmap_read(asrc->regmap, REG_ASRCFG, &reg);
++ reg &= ASRCFG_INIRQx_MASK(index);
++ }
++
++ /* Set the input fifo to ASRC STALL level */
++ regmap_read(asrc->regmap, REG_ASRCNCR, &reg);
++ channels = ASRCNCR_ANCx_get(index, reg, asrc->channel_bits);
++ for (i = 0; i < channels * 4; i++)
++ regmap_write(asrc->regmap, REG_ASRDI(index), 0);
++
++ /* Overload Interrupt Enable */
++ regmap_write(asrc->regmap, REG_ASRIER, ASRIER_AOLIE);
++}
++EXPORT_SYMBOL(asrc_start_conv);
++
++void asrc_stop_conv(enum asrc_pair_index index)
++{
++ regmap_update_bits(asrc->regmap, REG_ASRCTR, ASRCTR_ASRCEx_MASK(index), 0);
++}
++EXPORT_SYMBOL(asrc_stop_conv);
++
++void asrc_finish_conv(enum asrc_pair_index index)
++{
++ clk_disable_unprepare(asrc->dma_clk);
++ clk_disable_unprepare(asrc->asrck_clk);
++ clk_disable_unprepare(asrc->ipg_clk);
++ clk_disable_unprepare(asrc->mem_clk);
++}
++EXPORT_SYMBOL(asrc_finish_conv);
++
++#define SET_OVERLOAD_ERR(index, err, msg) \
++ do { \
++ asrc->asrc_pair[index].overload_error |= err; \
++ pair_dbg(msg); \
++ } while (0)
++
++static irqreturn_t asrc_isr(int irq, void *dev_id)
++{
++ enum asrc_pair_index index;
++ u32 status;
++
++ regmap_read(asrc->regmap, REG_ASRSTR, &status);
++
++ for (index = ASRC_PAIR_A; index < ASRC_PAIR_MAX_NUM; index++) {
++ if (asrc->asrc_pair[index].active == 0)
++ continue;
++ if (status & ASRSTR_ATQOL)
++ SET_OVERLOAD_ERR(index, ASRC_TASK_Q_OVERLOAD,
++ "Task Queue FIFO overload");
++ if (status & ASRSTR_AOOL(index))
++ SET_OVERLOAD_ERR(index, ASRC_OUTPUT_TASK_OVERLOAD,
++ "Output Task Overload");
++ if (status & ASRSTR_AIOL(index))
++ SET_OVERLOAD_ERR(index, ASRC_INPUT_TASK_OVERLOAD,
++ "Input Task Overload");
++ if (status & ASRSTR_AODO(index))
++ SET_OVERLOAD_ERR(index, ASRC_OUTPUT_BUFFER_OVERFLOW,
++ "Output Data Buffer has overflowed");
++ if (status & ASRSTR_AIDU(index))
++ SET_OVERLOAD_ERR(index, ASRC_INPUT_BUFFER_UNDERRUN,
++ "Input Data Buffer has underflowed");
++ }
++
++ /* Clean overload error */
++ regmap_write(asrc->regmap, REG_ASRSTR, ASRSTR_AOLE);
++
++ return IRQ_HANDLED;
++}
++
++void asrc_get_status(struct asrc_status_flags *flags)
++{
++ enum asrc_pair_index index = flags->index;
++ unsigned long lock_flags;
++
++ spin_lock_irqsave(&data_lock, lock_flags);
++
++ flags->overload_error = asrc->asrc_pair[index].overload_error;
++
++ spin_unlock_irqrestore(&data_lock, lock_flags);
++}
++EXPORT_SYMBOL(asrc_get_status);
++
++u32 asrc_get_per_addr(enum asrc_pair_index index, bool in)
++{
++ return asrc->paddr + (in ? REG_ASRDI(index) : REG_ASRDO(index));
++}
++EXPORT_SYMBOL(asrc_get_per_addr);
++
++static int mxc_init_asrc(void)
++{
++ /* Halt ASRC internal FP when input FIFO needs data for pair A, B, C */
++ regmap_write(asrc->regmap, REG_ASRCTR, ASRCTR_ASRCEN);
++
++ /* Disable interrupt by default */
++ regmap_write(asrc->regmap, REG_ASRIER, 0x0);
++
++ /* Default 2: 6: 2 channel assignment */
++ regmap_update_bits(asrc->regmap, REG_ASRCNCR,
++ ASRCNCR_ANCx_MASK(ASRC_PAIR_A, asrc->channel_bits),
++ ASRCNCR_ANCx_set(ASRC_PAIR_A, 2, asrc->channel_bits));
++ regmap_update_bits(asrc->regmap, REG_ASRCNCR,
++ ASRCNCR_ANCx_MASK(ASRC_PAIR_B, asrc->channel_bits),
++ ASRCNCR_ANCx_set(ASRC_PAIR_B, 6, asrc->channel_bits));
++ regmap_update_bits(asrc->regmap, REG_ASRCNCR,
++ ASRCNCR_ANCx_MASK(ASRC_PAIR_C, asrc->channel_bits),
++ ASRCNCR_ANCx_set(ASRC_PAIR_C, 2, asrc->channel_bits));
++
++ /* Parameter Registers recommended settings */
++ regmap_write(asrc->regmap, REG_ASRPM1, 0x7fffff);
++ regmap_write(asrc->regmap, REG_ASRPM2, 0x255555);
++ regmap_write(asrc->regmap, REG_ASRPM3, 0xff7280);
++ regmap_write(asrc->regmap, REG_ASRPM4, 0xff7280);
++ regmap_write(asrc->regmap, REG_ASRPM5, 0xff7280);
++
++ /* Base address for task queue FIFO. Set to 0x7C */
++ regmap_update_bits(asrc->regmap, REG_ASRTFR1,
++ ASRTFR1_TF_BASE_MASK, ASRTFR1_TF_BASE(0xfc));
++
++ /* Set the processing clock for 76KHz, 133M */
++ regmap_write(asrc->regmap, REG_ASR76K, 0x06D6);
++
++ /* Set the processing clock for 56KHz, 133M */
++ return regmap_write(asrc->regmap, REG_ASR56K, 0x0947);
++}
++
++#define ASRC_xPUT_DMA_CALLBACK(in) \
++ ((in) ? asrc_input_dma_callback : asrc_output_dma_callback)
++
++static void asrc_input_dma_callback(void *data)
++{
++ struct asrc_pair_params *params = (struct asrc_pair_params *)data;
++
++ complete(&params->input_complete);
++}
++
++static void asrc_output_dma_callback(void *data)
++{
++ struct asrc_pair_params *params = (struct asrc_pair_params *)data;
++
++ complete(&params->output_complete);
++}
++
++static unsigned int asrc_get_output_FIFO_size(enum asrc_pair_index index)
++{
++ u32 val;
++
++ regmap_read(asrc->regmap, REG_ASRFST(index), &val);
++
++ val &= ASRFSTx_OUTPUT_FIFO_MASK;
++
++ return val >> ASRFSTx_OUTPUT_FIFO_SHIFT;
++}
++
++static u32 asrc_read_one_from_output_FIFO(enum asrc_pair_index index)
++{
++ u32 val;
++
++ regmap_read(asrc->regmap, REG_ASRDO(index), &val);
++
++ return val;
++}
++
++static void asrc_read_output_FIFO(struct asrc_pair_params *params)
++{
++ u32 *reg24 = params->output_last_period.dma_vaddr;
++ u16 *reg16 = params->output_last_period.dma_vaddr;
++ enum asrc_pair_index index = params->index;
++ u32 i, j, reg, size, t_size;
++ bool bit24 = false;
++
++ if (params->output_word_width == ASRC_WIDTH_24_BIT)
++ bit24 = true;
++
++ t_size = 0;
++ do {
++ size = asrc_get_output_FIFO_size(index);
++ for (i = 0; i < size; i++) {
++ for (j = 0; j < params->channel_nums; j++) {
++ reg = asrc_read_one_from_output_FIFO(index);
++ if (bit24) {
++ *(reg24) = reg;
++ reg24++;
++ } else {
++ *(reg16) = (u16)reg;
++ reg16++;
++ }
++ }
++ }
++ t_size += size;
++ } while (size);
++
++ if (t_size > params->last_period_sample)
++ t_size = params->last_period_sample;
++
++ params->output_last_period.length = t_size * params->channel_nums * 2;
++ if (bit24)
++ params->output_last_period.length *= 2;
++}
++
++static void mxc_free_dma_buf(struct asrc_pair_params *params)
++{
++ if (params->input_dma_total.dma_vaddr != NULL) {
++ kfree(params->input_dma_total.dma_vaddr);
++ params->input_dma_total.dma_vaddr = NULL;
++ }
++
++ if (params->output_dma_total.dma_vaddr != NULL) {
++ kfree(params->output_dma_total.dma_vaddr);
++ params->output_dma_total.dma_vaddr = NULL;
++ }
++
++ if (params->output_last_period.dma_vaddr) {
++ dma_free_coherent(asrc->dev, 1024 * params->last_period_sample,
++ params->output_last_period.dma_vaddr,
++ params->output_last_period.dma_paddr);
++ params->output_last_period.dma_vaddr = NULL;
++ }
++}
++
++static int mxc_allocate_dma_buf(struct asrc_pair_params *params)
++{
++ struct dma_block *input_a, *output_a, *last_period;
++ enum asrc_pair_index index = params->index;
++
++ input_a = &params->input_dma_total;
++ output_a = &params->output_dma_total;
++ last_period = &params->output_last_period;
++
++ input_a->dma_vaddr = kzalloc(input_a->length, GFP_KERNEL);
++ if (!input_a->dma_vaddr) {
++ pair_err("failed to allocate input dma buffer\n");
++ goto exit;
++ }
++ input_a->dma_paddr = virt_to_dma(NULL, input_a->dma_vaddr);
++
++ output_a->dma_vaddr = kzalloc(output_a->length, GFP_KERNEL);
++ if (!output_a->dma_vaddr) {
++ pair_err("failed to allocate output dma buffer\n");
++ goto exit;
++ }
++ output_a->dma_paddr = virt_to_dma(NULL, output_a->dma_vaddr);
++
++ last_period->dma_vaddr = dma_zalloc_coherent(asrc->dev,
++ 1024 * params->last_period_sample,
++ &last_period->dma_paddr, GFP_KERNEL);
++ if (!last_period->dma_vaddr) {
++ pair_err("failed to allocate last period buffer\n");
++ goto exit;
++ }
++
++ return 0;
++
++exit:
++ mxc_free_dma_buf(params);
++
++ return -ENOBUFS;
++}
++
++static struct dma_chan *imx_asrc_get_dma_channel(enum asrc_pair_index index, bool in)
++{
++ char name[4];
++
++ sprintf(name, "%cx%c", in ? 'r' : 't', index + 'a');
++
++ return dma_request_slave_channel(asrc->dev, name);
++}
++
++static int imx_asrc_dma_config(struct asrc_pair_params *params,
++ struct dma_chan *chan, u32 dma_addr,
++ void *buf_addr, u32 buf_len, bool in,
++ enum asrc_word_width word_width)
++{
++ enum asrc_pair_index index = params->index;
++ struct dma_async_tx_descriptor *desc;
++ struct dma_slave_config slave_config;
++ enum dma_slave_buswidth buswidth;
++ struct scatterlist *sg;
++ unsigned int sg_nent, i;
++ int ret;
++
++ if (in) {
++ sg = params->input_sg;
++ sg_nent = params->input_sg_nodes;
++ desc = params->desc_in;
++ } else {
++ sg = params->output_sg;
++ sg_nent = params->output_sg_nodes;
++ desc = params->desc_out;
++ }
++
++ switch (word_width) {
++ case ASRC_WIDTH_16_BIT:
++ buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
++ break;
++ case ASRC_WIDTH_24_BIT:
++ buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
++ break;
++ default:
++ pair_err("invalid word width\n");
++ return -EINVAL;
++ }
++
++// slave_config.dma_request0 = 0;
++// slave_config.dma_request1 = 0;
++
++ if (in) {
++ slave_config.direction = DMA_MEM_TO_DEV;
++ slave_config.dst_addr = dma_addr;
++ slave_config.dst_addr_width = buswidth;
++ slave_config.dst_maxburst =
++ params->input_wm * params->channel_nums;
++ } else {
++ slave_config.direction = DMA_DEV_TO_MEM;
++ slave_config.src_addr = dma_addr;
++ slave_config.src_addr_width = buswidth;
++ slave_config.src_maxburst =
++ params->output_wm * params->channel_nums;
++ }
++ ret = dmaengine_slave_config(chan, &slave_config);
++ if (ret) {
++ pair_err("failed to config dmaengine for %sput task: %d\n",
++ in ? "in" : "out", ret);
++ return -EINVAL;
++ }
++
++ sg_init_table(sg, sg_nent);
++ switch (sg_nent) {
++ case 1:
++ sg_init_one(sg, buf_addr, buf_len);
++ break;
++ case 2:
++ case 3:
++ case 4:
++ for (i = 0; i < (sg_nent - 1); i++)
++ sg_set_buf(&sg[i], buf_addr + i * ASRC_MAX_BUFFER_SIZE,
++ ASRC_MAX_BUFFER_SIZE);
++
++ sg_set_buf(&sg[i], buf_addr + i * ASRC_MAX_BUFFER_SIZE,
++ buf_len - ASRC_MAX_BUFFER_SIZE * i);
++ break;
++ default:
++ pair_err("invalid input DMA nodes number: %d\n", sg_nent);
++ return -EINVAL;
++ }
++
++ ret = dma_map_sg(NULL, sg, sg_nent, slave_config.direction);
++ if (ret != sg_nent) {
++ pair_err("failed to map dma sg for %sput task\n",
++ in ? "in" : "out");
++ return -EINVAL;
++ }
++
++ desc = dmaengine_prep_slave_sg(chan, sg, sg_nent,
++ slave_config.direction, DMA_PREP_INTERRUPT);
++ if (!desc) {
++ pair_err("failed to prepare slave sg for %sput task\n",
++ in ? "in" : "out");
++ return -EINVAL;
++ }
++
++ if (in) {
++ params->desc_in = desc;
++ params->desc_in->callback = asrc_input_dma_callback;
++ } else {
++ params->desc_out = desc;
++ params->desc_out->callback = asrc_output_dma_callback;
++ }
++
++ desc->callback = ASRC_xPUT_DMA_CALLBACK(in);
++ desc->callback_param = params;
++
++ return 0;
++}
++
++static int mxc_asrc_prepare_io_buffer(struct asrc_pair_params *params,
++ struct asrc_convert_buffer *pbuf, bool in)
++{
++ enum asrc_pair_index index = params->index;
++ struct dma_chan *dma_channel;
++ enum asrc_word_width width;
++ unsigned int *dma_len, *sg_nodes, buf_len, wm;
++ void __user *buf_vaddr;
++ void *dma_vaddr;
++ u32 word_size, fifo_addr;
++
++ if (in) {
++ dma_channel = params->input_dma_channel;
++ dma_vaddr = params->input_dma_total.dma_vaddr;
++ dma_len = &params->input_dma_total.length;
++ width = params->input_word_width;
++ sg_nodes = &params->input_sg_nodes;
++ wm = params->input_wm;
++ buf_vaddr = (void __user *)pbuf->input_buffer_vaddr;
++ buf_len = pbuf->input_buffer_length;
++ } else {
++ dma_channel = params->output_dma_channel;
++ dma_vaddr = params->output_dma_total.dma_vaddr;
++ dma_len = &params->output_dma_total.length;
++ width = params->output_word_width;
++ sg_nodes = &params->output_sg_nodes;
++ wm = params->last_period_sample;
++ buf_vaddr = (void __user *)pbuf->output_buffer_vaddr;
++ buf_len = pbuf->output_buffer_length;
++ }
++
++ switch (width) {
++ case ASRC_WIDTH_24_BIT:
++ word_size = 4;
++ break;
++ case ASRC_WIDTH_16_BIT:
++ case ASRC_WIDTH_8_BIT:
++ word_size = 2;
++ break;
++ default:
++ pair_err("invalid %sput word size!\n", in ? "in" : "out");
++ return -EINVAL;
++ }
++
++ if (buf_len < word_size * params->channel_nums * wm) {
++ pair_err("%sput buffer size[%d] is too small!\n",
++ in ? "in" : "out", buf_len);
++ return -EINVAL;
++ }
++
++ /* Copy origin data into input buffer */
++ if (in && copy_from_user(dma_vaddr, buf_vaddr, buf_len))
++ return -EFAULT;
++
++ *dma_len = buf_len;
++ if (!in)
++ *dma_len -= wm * word_size * params->channel_nums;
++
++ *sg_nodes = *dma_len / ASRC_MAX_BUFFER_SIZE + 1;
++
++ fifo_addr = asrc_get_per_addr(params->index, in);
++
++ return imx_asrc_dma_config(params, dma_channel, fifo_addr, dma_vaddr,
++ *dma_len, in, width);
++}
++
++static int mxc_asrc_prepare_buffer(struct asrc_pair_params *params,
++ struct asrc_convert_buffer *pbuf)
++{
++ enum asrc_pair_index index = params->index;
++ int ret;
++
++ ret = mxc_asrc_prepare_io_buffer(params, pbuf, true);
++ if (ret) {
++ pair_err("failed to prepare input buffer: %d\n", ret);
++ return ret;
++ }
++
++ ret = mxc_asrc_prepare_io_buffer(params, pbuf, false);
++ if (ret) {
++ pair_err("failed to prepare output buffer: %d\n", ret);
++ return ret;
++ }
++
++ return 0;
++}
++
++int mxc_asrc_process_buffer_pre(struct completion *complete,
++ enum asrc_pair_index index, bool in)
++{
++ if (!wait_for_completion_interruptible_timeout(complete, 10 * HZ)) {
++ pair_err("%sput dma task timeout\n", in ? "in" : "out");
++ return -ETIME;
++ } else if (signal_pending(current)) {
++ pair_err("%sput task forcibly aborted\n", in ? "in" : "out");
++ return -EBUSY;
++ }
++
++ init_completion(complete);
++
++ return 0;
++}
++
++#define mxc_asrc_dma_umap(params) \
++ do { \
++ dma_unmap_sg(NULL, params->input_sg, params->input_sg_nodes, \
++ DMA_MEM_TO_DEV); \
++ dma_unmap_sg(NULL, params->output_sg, params->output_sg_nodes, \
++ DMA_DEV_TO_MEM); \
++ } while (0)
++
++int mxc_asrc_process_buffer(struct asrc_pair_params *params,
++ struct asrc_convert_buffer *pbuf)
++{
++ enum asrc_pair_index index = params->index;
++ unsigned long lock_flags;
++ int ret;
++
++ /* Check input task first */
++ ret = mxc_asrc_process_buffer_pre(&params->input_complete, index, false);
++ if (ret) {
++ mxc_asrc_dma_umap(params);
++ return ret;
++ }
++
++ /* ...then output task*/
++ ret = mxc_asrc_process_buffer_pre(&params->output_complete, index, true);
++ if (ret) {
++ mxc_asrc_dma_umap(params);
++ return ret;
++ }
++
++ mxc_asrc_dma_umap(params);
++
++ pbuf->input_buffer_length = params->input_dma_total.length;
++ pbuf->output_buffer_length = params->output_dma_total.length;
++
++ spin_lock_irqsave(&pair_lock, lock_flags);
++ if (!params->pair_hold) {
++ spin_unlock_irqrestore(&pair_lock, lock_flags);
++ return -EFAULT;
++ }
++ spin_unlock_irqrestore(&pair_lock, lock_flags);
++
++ asrc_read_output_FIFO(params);
++
++ if (copy_to_user((void __user *)pbuf->output_buffer_vaddr,
++ params->output_dma_total.dma_vaddr,
++ params->output_dma_total.length))
++ return -EFAULT;
++
++ pbuf->output_buffer_length += params->output_last_period.length;
++
++ if (copy_to_user((void __user *)pbuf->output_buffer_vaddr +
++ params->output_dma_total.length,
++ params->output_last_period.dma_vaddr,
++ params->output_last_period.length))
++ return -EFAULT;
++
++ return 0;
++}
++
++#ifdef ASRC_POLLING_WITHOUT_DMA
++static void asrc_write_one_to_input_FIFO(enum asrc_pair_index index, u32 val)
++{
++ regmap_write(asrc->regmap, REG_ASRDI(index), val);
++}
++
++/* THIS FUNCTION ONLY EXISTS FOR DEBUGGING AND ONLY SUPPORTS TWO CHANNELS */
++static void asrc_polling_debug(struct asrc_pair_params *params)
++{
++ enum asrc_pair_index index = params->index;
++ u32 *in24 = params->input_dma_total.dma_vaddr;
++ u32 dma_len = params->input_dma_total.length / (params->channel_nums * 4);
++ u32 size, i, j, t_size, reg;
++ u32 *reg24 = params->output_dma_total.dma_vaddr;
++
++ t_size = 0;
++
++ for (i = 0; i < dma_len; ) {
++ for (j = 0; j < 2; j++) {
++ asrc_write_one_to_input_FIFO(index, *in24);
++ in24++;
++ asrc_write_one_to_input_FIFO(index, *in24);
++ in24++;
++ i++;
++ }
++ udelay(50);
++ udelay(50 * params->output_sample_rate / params->input_sample_rate);
++
++ size = asrc_get_output_FIFO_size(index);
++ for (j = 0; j < size; j++) {
++ reg = asrc_read_one_from_output_FIFO(index);
++ *(reg24) = reg;
++ reg24++;
++ reg = asrc_read_one_from_output_FIFO(index);
++ *(reg24) = reg;
++ reg24++;
++ }
++ t_size += size;
++ }
++
++ mdelay(1);
++ size = asrc_get_output_FIFO_size(index);
++ for (j = 0; j < size; j++) {
++ reg = asrc_read_one_from_output_FIFO(index);
++ *(reg24) = reg;
++ reg24++;
++ reg = asrc_read_one_from_output_FIFO(index);
++ *(reg24) = reg;
++ reg24++;
++ }
++ t_size += size;
++
++ params->output_dma_total.length = t_size * params->channel_nums * 4;
++ params->output_last_period.length = 0;
++
++ complete(&params->input_complete);
++}
++#else
++static void mxc_asrc_submit_dma(struct asrc_pair_params *params)
++{
++ enum asrc_pair_index index = params->index;
++ u32 size = asrc_get_output_FIFO_size(params->index);
++ int i, j;
++
++ /* Read all data in OUTPUT FIFO */
++ while (size) {
++ for (j = 0; j < size; j++)
++ for (i = 0; i < params->channel_nums; i++)
++ asrc_read_one_from_output_FIFO(index);
++ /* Fetch the data every 100us */
++ udelay(100);
++
++ size = asrc_get_output_FIFO_size(index);
++ }
++
++ /* Submit dma request */
++ dmaengine_submit(params->desc_in);
++ dma_async_issue_pending(params->desc_in->chan);
++
++ dmaengine_submit(params->desc_out);
++ dma_async_issue_pending(params->desc_out->chan);
++
++ /*
++ * Clear dma request during the stall state of ASRC:
++ * During STALL state, the remaining in input fifo would never be
++ * smaller than the input threshold while the output fifo would not
++ * be bigger than output one. Thus the dma request would be cleared.
++ */
++ asrc_set_watermark(index, ASRC_FIFO_THRESHOLD_MIN, ASRC_FIFO_THRESHOLD_MAX);
++
++ /* Update the real input threshold to raise dma request */
++ asrc_set_watermark(index, params->input_wm, params->output_wm);
++}
++#endif
++
++static long asrc_ioctl_req_pair(struct asrc_pair_params *params,
++ void __user *user)
++{
++ unsigned long lock_flags;
++ struct asrc_req req;
++ long ret;
++
++ ret = copy_from_user(&req, user, sizeof(req));
++ if (ret) {
++ dev_err(asrc->dev, "failed to get req from user space: %ld\n", ret);
++ return ret;
++ }
++
++ ret = asrc_req_pair(req.chn_num, &req.index);
++ if (ret) {
++ dev_err(asrc->dev, "failed to request pair: %ld\n", ret);
++ return ret;
++ }
++
++ spin_lock_irqsave(&pair_lock, lock_flags);
++ params->pair_hold = 1;
++ spin_unlock_irqrestore(&pair_lock, lock_flags);
++ params->index = req.index;
++ params->channel_nums = req.chn_num;
++
++ ret = copy_to_user(user, &req, sizeof(req));
++ if (ret) {
++ dev_err(asrc->dev, "failed to send req to user space: %ld\n", ret);
++ return ret;
++ }
++
++ return 0;
++}
++
++static long asrc_ioctl_config_pair(struct asrc_pair_params *params,
++ void __user *user)
++{
++ struct asrc_config config;
++ enum asrc_pair_index index;
++ long ret;
++
++ ret = copy_from_user(&config, user, sizeof(config));
++ if (ret) {
++ dev_err(asrc->dev, "failed to get config from user space: %ld\n", ret);
++ return ret;
++ }
++
++ index = config.pair;
++
++ ret = asrc_config_pair(&config);
++ if (ret) {
++ pair_err("failed to config pair: %ld\n", ret);
++ return ret;
++ }
++
++ params->input_wm = 4;
++ params->output_wm = 2;
++
++ ret = asrc_set_watermark(index, params->input_wm, params->output_wm);
++ if (ret)
++ return ret;
++
++ params->output_buffer_size = config.dma_buffer_size;
++ params->input_buffer_size = config.dma_buffer_size;
++ if (config.buffer_num > ASRC_DMA_BUFFER_NUM)
++ params->buffer_num = ASRC_DMA_BUFFER_NUM;
++ else
++ params->buffer_num = config.buffer_num;
++
++ params->input_dma_total.length = ASRC_DMA_BUFFER_SIZE;
++ params->output_dma_total.length = ASRC_DMA_BUFFER_SIZE;
++
++ params->input_word_width = config.input_word_width;
++ params->output_word_width = config.output_word_width;
++
++ params->input_sample_rate = config.input_sample_rate;
++ params->output_sample_rate = config.output_sample_rate;
++
++ if (params->output_sample_rate > params->input_sample_rate)
++ params->last_period_sample = ASRC_OUTPUT_LAST_SAMPLE_DEFAULT_MAX;
++ else
++ params->last_period_sample = ASRC_OUTPUT_LAST_SAMPLE_DEFAULT;
++
++
++ ret = mxc_allocate_dma_buf(params);
++ if (ret) {
++ pair_err("failed to allocate dma buffer: %ld\n", ret);
++ return ret;
++ }
++
++ /* Request DMA channel for both input and output */
++ params->input_dma_channel = imx_asrc_get_dma_channel(index, true);
++ if (params->input_dma_channel == NULL) {
++ pair_err("failed to request input task dma channel\n");
++ return -EBUSY;
++ }
++
++ params->output_dma_channel = imx_asrc_get_dma_channel(index, false);
++ if (params->output_dma_channel == NULL) {
++ pair_err("failed to request output task dma channel\n");
++ return -EBUSY;
++ }
++
++ ret = copy_to_user(user, &config, sizeof(config));
++ if (ret) {
++ pair_err("failed to send config to user space: %ld\n", ret);
++ return ret;
++ }
++
++ return 0;
++}
++
++static long asrc_ioctl_release_pair(struct asrc_pair_params *params,
++ void __user *user)
++{
++ enum asrc_pair_index index;
++ unsigned long lock_flags;
++ long ret;
++
++ ret = copy_from_user(&index, user, sizeof(index));
++ if (ret) {
++ dev_err(asrc->dev, "failed to get index from user space: %ld\n", ret);
++ return ret;
++ }
++
++ /* index might be not valid due to some application failure. */
++ if (index < 0)
++ return -EINVAL;
++
++ params->asrc_active = 0;
++
++ spin_lock_irqsave(&pair_lock, lock_flags);
++ params->pair_hold = 0;
++ spin_unlock_irqrestore(&pair_lock, lock_flags);
++
++ if (params->input_dma_channel)
++ dma_release_channel(params->input_dma_channel);
++ if (params->output_dma_channel)
++ dma_release_channel(params->output_dma_channel);
++ mxc_free_dma_buf(params);
++ asrc_release_pair(index);
++ asrc_finish_conv(index);
++
++ return 0;
++}
++
++static long asrc_ioctl_convert(struct asrc_pair_params *params,
++ void __user *user)
++{
++ enum asrc_pair_index index = params->index;
++ struct asrc_convert_buffer buf;
++ long ret;
++
++ ret = copy_from_user(&buf, user, sizeof(buf));
++ if (ret) {
++ pair_err("failed to get buf from user space: %ld\n", ret);
++ return ret;
++ }
++
++ ret = mxc_asrc_prepare_buffer(params, &buf);
++ if (ret) {
++ pair_err("failed to prepare buffer: %ld\n", ret);
++ return ret;
++ }
++
++#ifdef ASRC_POLLING_WITHOUT_DMA
++ asrc_polling_debug(params);
++#else
++ mxc_asrc_submit_dma(params);
++#endif
++
++ ret = mxc_asrc_process_buffer(params, &buf);
++ if (ret) {
++ pair_err("failed to process buffer: %ld\n", ret);
++ return ret;
++ }
++
++ ret = copy_to_user(user, &buf, sizeof(buf));
++ if (ret) {
++ pair_err("failed to send buf to user space: %ld\n", ret);
++ return ret;
++ }
++
++ return 0;
++}
++
++static long asrc_ioctl_start_conv(struct asrc_pair_params *params,
++ void __user *user)
++{
++ enum asrc_pair_index index;
++ long ret;
++
++ ret = copy_from_user(&index, user, sizeof(index));
++ if (ret) {
++ dev_err(asrc->dev, "failed to get index from user space: %ld\n", ret);
++ return ret;
++ }
++
++ params->asrc_active = 1;
++ asrc_start_conv(index);
++
++ return 0;
++}
++
++static long asrc_ioctl_stop_conv(struct asrc_pair_params *params,
++ void __user *user)
++{
++ enum asrc_pair_index index;
++ long ret;
++
++ ret = copy_from_user(&index, user, sizeof(index));
++ if (ret) {
++ dev_err(asrc->dev, "failed to get index from user space: %ld\n", ret);
++ return ret;
++ }
++
++ dmaengine_terminate_all(params->input_dma_channel);
++ dmaengine_terminate_all(params->output_dma_channel);
++
++ asrc_stop_conv(index);
++ params->asrc_active = 0;
++
++ return 0;
++}
++
++static long asrc_ioctl_status(struct asrc_pair_params *params,
++ void __user *user)
++{
++ enum asrc_pair_index index = params->index;
++ struct asrc_status_flags flags;
++ long ret;
++
++ ret = copy_from_user(&flags, user, sizeof(flags));
++ if (ret) {
++ pair_err("failed to get flags from user space: %ld\n", ret);
++ return ret;
++ }
++
++ asrc_get_status(&flags);
++
++ ret = copy_to_user(user, &flags, sizeof(flags));
++ if (ret) {
++ pair_err("failed to send flags to user space: %ld\n", ret);
++ return ret;
++ }
++
++ return 0;
++}
++
++static long asrc_ioctl_flush(struct asrc_pair_params *params,
++ void __user *user)
++{
++ enum asrc_pair_index index = params->index;
++ init_completion(&params->input_complete);
++ init_completion(&params->output_complete);
++
++ /* Release DMA and request again */
++ dma_release_channel(params->input_dma_channel);
++ dma_release_channel(params->output_dma_channel);
++
++ params->input_dma_channel = imx_asrc_get_dma_channel(index, true);
++ if (params->input_dma_channel == NULL) {
++ pair_err("failed to request input task dma channel\n");
++ return -EBUSY;
++ }
++
++ params->output_dma_channel = imx_asrc_get_dma_channel(index, false);
++ if (params->output_dma_channel == NULL) {
++ pair_err("failed to request output task dma channel\n");
++ return -EBUSY;
++ }
++
++ return 0;
++}
++
++static long asrc_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
++{
++ struct asrc_pair_params *params = file->private_data;
++ void __user *user = (void __user *)arg;
++ long ret = 0;
++
++ switch (cmd) {
++ case ASRC_REQ_PAIR:
++ ret = asrc_ioctl_req_pair(params, user);
++ break;
++ case ASRC_CONFIG_PAIR:
++ ret = asrc_ioctl_config_pair(params, user);
++ break;
++ case ASRC_RELEASE_PAIR:
++ ret = asrc_ioctl_release_pair(params, user);
++ break;
++ case ASRC_CONVERT:
++ ret = asrc_ioctl_convert(params, user);
++ break;
++ case ASRC_START_CONV:
++ ret = asrc_ioctl_start_conv(params, user);
++ dump_regs();
++ break;
++ case ASRC_STOP_CONV:
++ ret = asrc_ioctl_stop_conv(params, user);
++ break;
++ case ASRC_STATUS:
++ ret = asrc_ioctl_status(params, user);
++ break;
++ case ASRC_FLUSH:
++ ret = asrc_ioctl_flush(params, user);
++ break;
++ default:
++ dev_err(asrc->dev, "invalid ioctl cmd!\n");
++ break;
++ }
++
++ return ret;
++}
++
++static int mxc_asrc_open(struct inode *inode, struct file *file)
++{
++ struct asrc_pair_params *params;
++ unsigned long lock_flags;
++ int i = 0, ret = 0;
++
++ ret = signal_pending(current);
++ if (ret) {
++ dev_err(asrc->dev, "current process has a signal pending\n");
++ return ret;
++ }
++
++ params = kzalloc(sizeof(struct asrc_pair_params), GFP_KERNEL);
++ if (params == NULL) {
++ dev_err(asrc->dev, "failed to allocate pair_params\n");
++ return -ENOBUFS;
++ }
++
++ file->private_data = params;
++
++ while (asrc->params[i])
++ i++;
++
++ if (i >= ASRC_PAIR_MAX_NUM) {
++ dev_err(asrc->dev, "All pairs are being occupied\n");
++ return -EBUSY;
++ }
++
++ init_completion(&params->input_complete);
++ init_completion(&params->output_complete);
++
++ spin_lock_irqsave(&pair_lock, lock_flags);
++ asrc->params[i] = params;
++ spin_unlock_irqrestore(&pair_lock, lock_flags);
++
++ return ret;
++}
++
++static int mxc_asrc_close(struct inode *inode, struct file *file)
++{
++ struct asrc_pair_params *params;
++ unsigned long lock_flags;
++ int i;
++
++ params = file->private_data;
++
++ spin_lock_irqsave(&pair_lock, lock_flags);
++ for (i = 0; i < ASRC_PAIR_MAX_NUM; i++)
++ if (asrc->params[i] == params)
++ asrc->params[i] = NULL;
++ spin_unlock_irqrestore(&pair_lock, lock_flags);
++
++ if (!params)
++ return 0;
++
++ if (params->asrc_active) {
++ params->asrc_active = 0;
++
++ dmaengine_terminate_all(params->input_dma_channel);
++ dmaengine_terminate_all(params->output_dma_channel);
++
++ asrc_stop_conv(params->index);
++
++ complete(&params->input_complete);
++ complete(&params->output_complete);
++ }
++
++ spin_lock_irqsave(&pair_lock, lock_flags);
++ if (params->pair_hold) {
++ params->pair_hold = 0;
++ spin_unlock_irqrestore(&pair_lock, lock_flags);
++
++ if (params->input_dma_channel)
++ dma_release_channel(params->input_dma_channel);
++ if (params->output_dma_channel)
++ dma_release_channel(params->output_dma_channel);
++
++ mxc_free_dma_buf(params);
++
++ asrc_release_pair(params->index);
++ asrc_finish_conv(params->index);
++ } else {
++ spin_unlock_irqrestore(&pair_lock, lock_flags);
++ }
++
++ spin_lock_irqsave(&pair_lock, lock_flags);
++ kfree(params);
++ spin_unlock_irqrestore(&pair_lock, lock_flags);
++ file->private_data = NULL;
++
++ return 0;
++}
++
++static int mxc_asrc_mmap(struct file *file, struct vm_area_struct *vma)
++{
++ unsigned long size = vma->vm_end - vma->vm_start;
++ int ret;
++
++ vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
++
++ ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
++ size, vma->vm_page_prot);
++ if (ret) {
++ dev_err(asrc->dev, "failed to memory map!\n");
++ return ret;
++ }
++
++ vma->vm_flags &= ~VM_IO;
++
++ return ret;
++}
++
++static const struct file_operations asrc_fops = {
++ .owner = THIS_MODULE,
++ .unlocked_ioctl = asrc_ioctl,
++ .mmap = mxc_asrc_mmap,
++ .open = mxc_asrc_open,
++ .release = mxc_asrc_close,
++};
++
++static struct miscdevice asrc_miscdev = {
++ .name = "mxc_asrc",
++ .fops = &asrc_fops,
++ .minor = MISC_DYNAMIC_MINOR,
++};
++
++static int asrc_read_proc_attr(struct file *file, char __user *buf,
++ size_t count, loff_t *off)
++{
++ char tmpbuf[80];
++ int len = 0;
++ u32 reg;
++
++ if (*off)
++ return 0;
++
++ regmap_read(asrc->regmap, REG_ASRCNCR, &reg);
++
++ len += sprintf(tmpbuf, "ANCA: %d\nANCB: %d\nANCC: %d\n",
++ ASRCNCR_ANCx_get(ASRC_PAIR_A, reg, asrc->channel_bits),
++ ASRCNCR_ANCx_get(ASRC_PAIR_B, reg, asrc->channel_bits),
++ ASRCNCR_ANCx_get(ASRC_PAIR_C, reg, asrc->channel_bits));
++
++ if (len > count)
++ return 0;
++
++ if (copy_to_user(buf, &tmpbuf, len))
++ return -EFAULT;
++
++ *off += len;
++
++ return len;
++}
++
++#define ASRC_MAX_PROC_BUFFER_SIZE 63
++
++static int asrc_write_proc_attr(struct file *file, const char __user *buffer,
++ size_t count, loff_t *data)
++{
++ char buf[ASRC_MAX_PROC_BUFFER_SIZE];
++ int na, nb, nc;
++ int total;
++
++ if (count > ASRC_MAX_PROC_BUFFER_SIZE) {
++ dev_err(asrc->dev, "proc write: the input string was too long\n");
++ return -EINVAL;
++ }
++
++ if (copy_from_user(buf, buffer, count)) {
++ dev_err(asrc->dev, "proc write: failed to copy buffer from user\n");
++ return -EFAULT;
++ }
++
++ sscanf(buf, "ANCA: %d\nANCB: %d\nANCC: %d", &na, &nb, &nc);
++
++ total = asrc->channel_bits > 3 ? 10 : 5;
++
++ if (na + nb + nc > total) {
++ dev_err(asrc->dev, "don't surpass %d for total\n", total);
++ return -EINVAL;
++ } else if (asrc->channel_bits < 4 &&
++ (na % 2 != 0 || nb % 2 != 0 || nc % 2 != 0)) {
++ dev_err(asrc->dev, "please set an even number for each pair\n");
++ return -EINVAL;
++ } else if (na < 0 || nb < 0 || nc < 0) {
++ dev_err(asrc->dev, "please set an positive number for each pair\n");
++ return -EINVAL;
++ }
++
++
++ asrc->asrc_pair[ASRC_PAIR_A].chn_max = na;
++ asrc->asrc_pair[ASRC_PAIR_B].chn_max = nb;
++ asrc->asrc_pair[ASRC_PAIR_C].chn_max = nc;
++
++ /* Update channel number settings */
++ regmap_update_bits(asrc->regmap, REG_ASRCNCR,
++ ASRCNCR_ANCx_MASK(ASRC_PAIR_A, asrc->channel_bits),
++ ASRCNCR_ANCx_set(ASRC_PAIR_A, na, asrc->channel_bits));
++ regmap_update_bits(asrc->regmap, REG_ASRCNCR,
++ ASRCNCR_ANCx_MASK(ASRC_PAIR_B, asrc->channel_bits),
++ ASRCNCR_ANCx_set(ASRC_PAIR_B, nb, asrc->channel_bits));
++ regmap_update_bits(asrc->regmap, REG_ASRCNCR,
++ ASRCNCR_ANCx_MASK(ASRC_PAIR_C, asrc->channel_bits),
++ ASRCNCR_ANCx_set(ASRC_PAIR_C, nc, asrc->channel_bits));
++
++ return count;
++}
++
++static const struct file_operations asrc_proc_fops = {
++ .read = asrc_read_proc_attr,
++ .write = asrc_write_proc_attr,
++};
++
++static void asrc_proc_create(void)
++{
++ struct proc_dir_entry *proc_attr;
++
++ asrc->proc_asrc = proc_mkdir(ASRC_PROC_PATH, NULL);
++ if (!asrc->proc_asrc) {
++ dev_err(asrc->dev, "failed to create proc entry %s\n", ASRC_PROC_PATH);
++ return;
++ }
++
++ proc_attr = proc_create("ChSettings", S_IFREG | S_IRUGO | S_IWUSR,
++ asrc->proc_asrc, &asrc_proc_fops);
++ if (!proc_attr) {
++ remove_proc_entry(ASRC_PROC_PATH, NULL);
++ dev_err(asrc->dev, "failed to create proc attribute entry\n");
++ }
++}
++
++static void asrc_proc_remove(void)
++{
++ remove_proc_entry("ChSettings", asrc->proc_asrc);
++ remove_proc_entry(ASRC_PROC_PATH, NULL);
++}
++
++
++static bool asrc_readable_reg(struct device *dev, unsigned int reg)
++{
++ switch (reg) {
++ case REG_ASRCTR:
++ case REG_ASRIER:
++ case REG_ASRCNCR:
++ case REG_ASRCFG:
++ case REG_ASRCSR:
++ case REG_ASRCDR1:
++ case REG_ASRCDR2:
++ case REG_ASRSTR:
++ case REG_ASRPM1:
++ case REG_ASRPM2:
++ case REG_ASRPM3:
++ case REG_ASRPM4:
++ case REG_ASRPM5:
++ case REG_ASRTFR1:
++ case REG_ASRCCR:
++ case REG_ASRDOA:
++ case REG_ASRDOB:
++ case REG_ASRDOC:
++ case REG_ASRIDRHA:
++ case REG_ASRIDRLA:
++ case REG_ASRIDRHB:
++ case REG_ASRIDRLB:
++ case REG_ASRIDRHC:
++ case REG_ASRIDRLC:
++ case REG_ASR76K:
++ case REG_ASR56K:
++ case REG_ASRMCRA:
++ case REG_ASRFSTA:
++ case REG_ASRMCRB:
++ case REG_ASRFSTB:
++ case REG_ASRMCRC:
++ case REG_ASRFSTC:
++ case REG_ASRMCR1A:
++ case REG_ASRMCR1B:
++ case REG_ASRMCR1C:
++ return true;
++ default:
++ return false;
++ }
++}
++
++static bool asrc_volatile_reg(struct device *dev, unsigned int reg)
++{
++ switch (reg) {
++ case REG_ASRSTR:
++ case REG_ASRDIA:
++ case REG_ASRDIB:
++ case REG_ASRDIC:
++ case REG_ASRDOA:
++ case REG_ASRDOB:
++ case REG_ASRDOC:
++ case REG_ASRFSTA:
++ case REG_ASRFSTB:
++ case REG_ASRFSTC:
++ case REG_ASRCFG:
++ return true;
++ default:
++ return false;
++ }
++}
++
++static bool asrc_writeable_reg(struct device *dev, unsigned int reg)
++{
++ switch (reg) {
++ case REG_ASRCTR:
++ case REG_ASRIER:
++ case REG_ASRCNCR:
++ case REG_ASRCFG:
++ case REG_ASRCSR:
++ case REG_ASRCDR1:
++ case REG_ASRCDR2:
++ case REG_ASRSTR:
++ case REG_ASRPM1:
++ case REG_ASRPM2:
++ case REG_ASRPM3:
++ case REG_ASRPM4:
++ case REG_ASRPM5:
++ case REG_ASRTFR1:
++ case REG_ASRCCR:
++ case REG_ASRDIA:
++ case REG_ASRDIB:
++ case REG_ASRDIC:
++ case REG_ASRIDRHA:
++ case REG_ASRIDRLA:
++ case REG_ASRIDRHB:
++ case REG_ASRIDRLB:
++ case REG_ASRIDRHC:
++ case REG_ASRIDRLC:
++ case REG_ASR76K:
++ case REG_ASR56K:
++ case REG_ASRMCRA:
++ case REG_ASRMCRB:
++ case REG_ASRMCRC:
++ case REG_ASRMCR1A:
++ case REG_ASRMCR1B:
++ case REG_ASRMCR1C:
++ return true;
++ default:
++ return false;
++ }
++}
++
++static struct regmap_config asrc_regmap_config = {
++ .reg_bits = 32,
++ .reg_stride = 4,
++ .val_bits = 32,
++
++ .max_register = REG_ASRMCR1C,
++ .readable_reg = asrc_readable_reg,
++ .volatile_reg = asrc_volatile_reg,
++ .writeable_reg = asrc_writeable_reg,
++ .cache_type = REGCACHE_RBTREE,
++};
++
++static int mxc_asrc_probe(struct platform_device *pdev)
++{
++ const struct of_device_id *of_id = of_match_device(fsl_asrc_ids, &pdev->dev);
++ struct device_node *np = pdev->dev.of_node;
++ enum mxc_asrc_type devtype;
++ struct resource *res;
++ void __iomem *regs;
++ int ret;
++
++ /* Check if the device is existed */
++ if (!np)
++ return -ENODEV;
++
++ asrc = devm_kzalloc(&pdev->dev, sizeof(struct asrc_data), GFP_KERNEL);
++ if (!asrc)
++ return -ENOMEM;
++
++ if (of_id) {
++ const struct platform_device_id *id_entry = of_id->data;
++ devtype = id_entry->driver_data;
++ } else {
++ devtype = pdev->id_entry->driver_data;
++ }
++
++ asrc->dev = &pdev->dev;
++ asrc->dev->coherent_dma_mask = DMA_BIT_MASK(32);
++
++ asrc->asrc_pair[ASRC_PAIR_A].chn_max = 2;
++ asrc->asrc_pair[ASRC_PAIR_B].chn_max = 6;
++ asrc->asrc_pair[ASRC_PAIR_C].chn_max = 2;
++ asrc->asrc_pair[ASRC_PAIR_A].overload_error = 0;
++ asrc->asrc_pair[ASRC_PAIR_B].overload_error = 0;
++ asrc->asrc_pair[ASRC_PAIR_C].overload_error = 0;
++
++ /* Map the address */
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (IS_ERR(res)) {
++ dev_err(&pdev->dev, "could not determine device resources\n");
++ return PTR_ERR(res);
++ }
++
++ regs = devm_ioremap_resource(&pdev->dev, res);
++ if (IS_ERR(regs)) {
++ dev_err(&pdev->dev, "could not map device resources\n");
++ return PTR_ERR(regs);
++ }
++ asrc->paddr = res->start;
++
++ /* Register regmap and let it prepare core clock */
++ asrc->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
++ "mem", regs, &asrc_regmap_config);
++ if (IS_ERR(asrc->regmap)) {
++ dev_err(&pdev->dev, "regmap init failed\n");
++ return PTR_ERR(asrc->regmap);
++ }
++
++ asrc->irq = platform_get_irq(pdev, 0);
++ if (asrc->irq == NO_IRQ) {
++ dev_err(&pdev->dev, "no irq for node %s\n", np->full_name);
++ return asrc->irq;
++ }
++
++ ret = devm_request_irq(&pdev->dev, asrc->irq, asrc_isr, 0, np->name, NULL);
++ if (ret) {
++ dev_err(&pdev->dev, "could not claim irq %u: %d\n", asrc->irq, ret);
++ return ret;
++ }
++
++ asrc->mem_clk = devm_clk_get(&pdev->dev, "mem");
++ if (IS_ERR(asrc->mem_clk)) {
++ dev_err(&pdev->dev, "failed to get mem clock\n");
++ return PTR_ERR(asrc->ipg_clk);
++ }
++
++ asrc->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
++ if (IS_ERR(asrc->ipg_clk)) {
++ dev_err(&pdev->dev, "failed to get ipg clock\n");
++ return PTR_ERR(asrc->ipg_clk);
++ }
++
++ asrc->asrck_clk = devm_clk_get(&pdev->dev, "asrck");
++ if (IS_ERR(asrc->asrck_clk)) {
++ dev_err(&pdev->dev, "failed to get asrck clock\n");
++ return PTR_ERR(asrc->asrck_clk);
++ }
++
++ asrc->dma_clk = devm_clk_get(&pdev->dev, "dma");
++ if (IS_ERR(asrc->dma_clk)) {
++ dev_err(&pdev->dev, "failed to get dma script clock\n");
++ return PTR_ERR(asrc->dma_clk);
++ }
++
++ switch (devtype) {
++ case IMX35_ASRC:
++ asrc->channel_bits = 3;
++ input_clk_map = input_clk_map_v1;
++ output_clk_map = output_clk_map_v1;
++ break;
++ case IMX53_ASRC:
++ asrc->channel_bits = 4;
++ input_clk_map = input_clk_map_v2;
++ output_clk_map = output_clk_map_v2;
++ break;
++ default:
++ dev_err(&pdev->dev, "unsupported device type\n");
++ return -EINVAL;
++ }
++
++ ret = misc_register(&asrc_miscdev);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to register char device %d\n", ret);
++ return ret;
++ }
++
++ asrc_proc_create();
++
++ ret = mxc_init_asrc();
++ if (ret) {
++ dev_err(&pdev->dev, "failed to init asrc %d\n", ret);
++ goto err_misc;
++ }
++
++ dev_info(&pdev->dev, "mxc_asrc registered\n");
++
++ return ret;
++
++err_misc:
++ misc_deregister(&asrc_miscdev);
++
++ return ret;
++}
++
++static int mxc_asrc_remove(struct platform_device *pdev)
++{
++ asrc_proc_remove();
++ misc_deregister(&asrc_miscdev);
++
++ return 0;
++}
++
++#if CONFIG_PM_SLEEP
++static int mxc_asrc_suspend(struct device *dev)
++{
++ struct asrc_pair_params *params;
++ unsigned long lock_flags;
++ int i;
++
++ for (i = 0; i < ASRC_PAIR_MAX_NUM; i++) {
++ spin_lock_irqsave(&pair_lock, lock_flags);
++
++ params = asrc->params[i];
++ if (!params || !params->pair_hold) {
++ spin_unlock_irqrestore(&pair_lock, lock_flags);
++ continue;
++ }
++
++ if (!completion_done(&params->input_complete)) {
++ if (params->input_dma_channel)
++ dmaengine_terminate_all(params->input_dma_channel);
++ asrc_input_dma_callback((void *)params);
++ }
++ if (!completion_done(&params->output_complete)) {
++ if (params->output_dma_channel)
++ dmaengine_terminate_all(params->output_dma_channel);
++ asrc_output_dma_callback((void *)params);
++ }
++
++ spin_unlock_irqrestore(&pair_lock, lock_flags);
++ }
++
++ regcache_cache_only(asrc->regmap, true);
++ regcache_mark_dirty(asrc->regmap);
++
++ return 0;
++}
++
++static int mxc_asrc_resume(struct device *dev)
++{
++ u32 asrctr;
++
++ /* Stop all pairs provisionally */
++ regmap_read(asrc->regmap, REG_ASRCTR, &asrctr);
++ regmap_update_bits(asrc->regmap, REG_ASRCTR, ASRCTR_ASRCEx_ALL_MASK, 0);
++
++ regcache_cache_only(asrc->regmap, false);
++ regcache_sync(asrc->regmap);
++
++ /* Restart enabled pairs */
++ regmap_update_bits(asrc->regmap, REG_ASRCTR,
++ ASRCTR_ASRCEx_ALL_MASK, asrctr);
++
++ return 0;
++}
++#endif /* CONFIG_PM_SLEEP */
++
++static const struct dev_pm_ops mxc_asrc_pm_ops = {
++ SET_SYSTEM_SLEEP_PM_OPS(mxc_asrc_suspend, mxc_asrc_resume)
++};
++
++static struct platform_driver mxc_asrc_driver = {
++ .driver = {
++ .name = "mxc_asrc",
++ .of_match_table = fsl_asrc_ids,
++ .pm = &mxc_asrc_pm_ops,
++ },
++ .probe = mxc_asrc_probe,
++ .remove = mxc_asrc_remove,
++};
++
++module_platform_driver(mxc_asrc_driver);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("Asynchronous Sample Rate Converter");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:mxc_asrc");
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/arch/GC350/hal/kernel/gc_hal_kernel_hardware_command_vg.c linux-xbian-imx6/drivers/mxc/gpu-viv/arch/GC350/hal/kernel/gc_hal_kernel_hardware_command_vg.c
+--- linux-4.1.3/drivers/mxc/gpu-viv/arch/GC350/hal/kernel/gc_hal_kernel_hardware_command_vg.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/arch/GC350/hal/kernel/gc_hal_kernel_hardware_command_vg.c 2015-07-27 23:13:06.166979215 +0200
+@@ -0,0 +1,932 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal.h"
++#include "gc_hal_kernel.h"
++
++#if gcdENABLE_VG
++
++#include "gc_hal_kernel_hardware_command_vg.h"
++
++#define _GC_OBJ_ZONE gcvZONE_COMMAND
++
++/******************************************************************************\
++****************************** gckVGCOMMAND API code *****************************
++\******************************************************************************/
++
++/*******************************************************************************
++**
++** gckVGCOMMAND_InitializeInfo
++**
++** Initialize architecture dependent command buffer information.
++**
++** INPUT:
++**
++** gckVGCOMMAND Command
++** Pointer to the Command object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckVGCOMMAND_InitializeInfo(
++ IN gckVGCOMMAND Command
++ )
++{
++ gceSTATUS status;
++ gcmkHEADER_ARG("Command=0x%x", Command);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ do
++ {
++ /* Reset interrupts. */
++ Command->info.feBufferInt = -1;
++ Command->info.tsOverflowInt = -1;
++
++ /* Set command buffer attributes. */
++ Command->info.addressAlignment = 64;
++ Command->info.commandAlignment = 8;
++
++ /* Determine command alignment address mask. */
++ Command->info.addressMask = ((((gctUINT32) (Command->info.addressAlignment - 1)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0))) | (((gctUINT32) ((gctUINT32) (0 ) & ((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0)));
++
++ /* Query the number of bytes needed by the STATE command. */
++ gcmkERR_BREAK(gckVGCOMMAND_StateCommand(
++ Command, 0x0, gcvNULL, (gctUINT32)~0, 0,
++ &Command->info.stateCommandSize
++ ));
++
++ /* Query the number of bytes needed by the RESTART command. */
++ gcmkERR_BREAK(gckVGCOMMAND_RestartCommand(
++ Command, gcvNULL, (gctUINT32)~0, 0,
++ &Command->info.restartCommandSize
++ ));
++
++ /* Query the number of bytes needed by the FETCH command. */
++ gcmkERR_BREAK(gckVGCOMMAND_FetchCommand(
++ Command, gcvNULL, (gctUINT32)~0, 0,
++ &Command->info.fetchCommandSize
++ ));
++
++ /* Query the number of bytes needed by the CALL command. */
++ gcmkERR_BREAK(gckVGCOMMAND_CallCommand(
++ Command, gcvNULL, (gctUINT32)~0, 0,
++ &Command->info.callCommandSize
++ ));
++
++ /* Query the number of bytes needed by the RETURN command. */
++ gcmkERR_BREAK(gckVGCOMMAND_ReturnCommand(
++ Command, gcvNULL,
++ &Command->info.returnCommandSize
++ ));
++
++ /* Query the number of bytes needed by the EVENT command. */
++ gcmkERR_BREAK(gckVGCOMMAND_EventCommand(
++ Command, gcvNULL, gcvBLOCK_PIXEL, -1,
++ &Command->info.eventCommandSize
++ ));
++
++ /* Query the number of bytes needed by the END command. */
++ gcmkERR_BREAK(gckVGCOMMAND_EndCommand(
++ Command, gcvNULL, -1,
++ &Command->info.endCommandSize
++ ));
++
++ /* Determine the tail reserve size. */
++ Command->info.staticTailSize = gcmMAX(
++ Command->info.fetchCommandSize,
++ gcmMAX(
++ Command->info.returnCommandSize,
++ Command->info.endCommandSize
++ )
++ );
++
++ /* Determine the maximum tail size. */
++ Command->info.dynamicTailSize
++ = Command->info.staticTailSize
++ + Command->info.eventCommandSize * gcvBLOCK_COUNT;
++ }
++ while (gcvFALSE);
++
++ gcmkFOOTER();
++ /* Return status. */
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckVGCOMMAND_StateCommand
++**
++** Append a STATE command at the specified location in the command buffer.
++**
++** INPUT:
++**
++** gckVGCOMMAND Command
++** Pointer to an gckVGCOMMAND object.
++**
++** gctUINT32 Pipe
++** Harwdare destination pipe.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command buffer to append
++** STATE command at or gcvNULL to query the size of the command.
++**
++** gctUINT32 Address
++** Starting register address of the state buffer.
++** If 'Logical' is gcvNULL, this argument is ignored.
++**
++** gctUINT32 Count
++** Number of states in state buffer.
++** If 'Logical' is gcvNULL, this argument is ignored.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the STATE command.
++** If 'Logical' is gcvNULL, the value from this argument is ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** for the STATE command. If 'Bytes' is gcvNULL, nothing is returned.
++*/
++gceSTATUS
++gckVGCOMMAND_StateCommand(
++ IN gckVGCOMMAND Command,
++ IN gctUINT32 Pipe,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Address,
++ IN gctSIZE_T Count,
++ IN OUT gctSIZE_T * Bytes
++ )
++{
++ gcmkHEADER_ARG("Command=0x%x Pipe=0x%x Logical=0x%x Address=0x%x Count=0x%x Bytes = 0x%x",
++ Command, Pipe, Logical, Address, Count, Bytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ if (Command->fe20)
++ {
++ if (Logical != gcvNULL)
++ {
++ gctUINT32_PTR buffer;
++
++ /* Cast the buffer pointer. */
++ buffer = (gctUINT32_PTR) Logical;
++
++ /* Append STATE. */
++ buffer[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28))) | (((gctUINT32) (0x3 & ((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 11:0) - (0 ? 11:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:0) - (0 ? 11:0) + 1))))))) << (0 ? 11:0))) | (((gctUINT32) ((gctUINT32) (Address) & ((gctUINT32) ((((1 ? 11:0) - (0 ? 11:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:0) - (0 ? 11:0) + 1))))))) << (0 ? 11:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 27:16) - (0 ? 27:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:16) - (0 ? 27:16) + 1))))))) << (0 ? 27:16))) | (((gctUINT32) ((gctUINT32) (Count) & ((gctUINT32) ((((1 ? 27:16) - (0 ? 27:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:16) - (0 ? 27:16) + 1))))))) << (0 ? 27:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 13:12) - (0 ? 13:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 13:12) - (0 ? 13:12) + 1))))))) << (0 ? 13:12))) | (((gctUINT32) ((gctUINT32) (Pipe) & ((gctUINT32) ((((1 ? 13:12) - (0 ? 13:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 13:12) - (0 ? 13:12) + 1))))))) << (0 ? 13:12)));
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the STATE command. */
++ *Bytes = 4 * (Count + 1);
++ }
++ }
++ else
++ {
++ if (Logical != gcvNULL)
++ {
++ gctUINT32_PTR buffer;
++
++ /* Cast the buffer pointer. */
++ buffer = (gctUINT32_PTR) Logical;
++
++ /* Append LOAD_STATE. */
++ buffer[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (Count) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (Address) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the STATE command. */
++ *Bytes = 4 * (Count + 1);
++ }
++ }
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGCOMMAND_RestartCommand
++**
++** Form a RESTART command at the specified location in the command buffer.
++**
++** INPUT:
++**
++** gckVGCOMMAND Command
++** Pointer to an gckVGCOMMAND object.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command buffer to append
++** RESTART command at or gcvNULL to query the size of the command.
++**
++** gctUINT32 FetchAddress
++** The address of another command buffer to be executed by this RESTART
++** command. If 'Logical' is gcvNULL, this argument is ignored.
++**
++** gctUINT FetchCount
++** The number of 64-bit data quantities in another command buffer to
++** be executed by this RESTART command. If 'Logical' is gcvNULL, this
++** argument is ignored.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the RESTART command.
++** If 'Logical' is gcvNULL, the value from this argument is ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** for the RESTART command. If 'Bytes' is gcvNULL, nothing is returned.
++*/
++gceSTATUS
++gckVGCOMMAND_RestartCommand(
++ IN gckVGCOMMAND Command,
++ IN gctPOINTER Logical,
++ IN gctUINT32 FetchAddress,
++ IN gctUINT FetchCount,
++ IN OUT gctSIZE_T * Bytes
++ )
++{
++ gcmkHEADER_ARG("Command=0x%x Logical=0x%x FetchAddress=0x%x FetchCount=0x%x Bytes = 0x%x",
++ Command, Logical, FetchAddress, FetchCount, Bytes);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ if (Command->fe20)
++ {
++ if (Logical != gcvNULL)
++ {
++ gctUINT32_PTR buffer;
++ gctUINT32 beginEndMark;
++
++ /* Cast the buffer pointer. */
++ buffer = (gctUINT32_PTR) Logical;
++
++ /* Determine Begin/End flag. */
++ beginEndMark = (FetchCount > 0)
++ ? ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 24:24) - (0 ? 24:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 24:24) - (0 ? 24:24) + 1))))))) << (0 ? 24:24))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 24:24) - (0 ? 24:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 24:24) - (0 ? 24:24) + 1))))))) << (0 ? 24:24)))
++ : ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 24:24) - (0 ? 24:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 24:24) - (0 ? 24:24) + 1))))))) << (0 ? 24:24))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 24:24) - (0 ? 24:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 24:24) - (0 ? 24:24) + 1))))))) << (0 ? 24:24)));
++
++ /* Append RESTART. */
++ buffer[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28))) | (((gctUINT32) (0x9 & ((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 20:0) - (0 ? 20:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:0) - (0 ? 20:0) + 1))))))) << (0 ? 20:0))) | (((gctUINT32) ((gctUINT32) (FetchCount) & ((gctUINT32) ((((1 ? 20:0) - (0 ? 20:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:0) - (0 ? 20:0) + 1))))))) << (0 ? 20:0)))
++ | beginEndMark;
++
++ buffer[1]
++ = FetchAddress;
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the RESTART command. */
++ *Bytes = 8;
++ }
++ }
++ else
++ {
++ gcmkFOOTER_NO();
++ return gcvSTATUS_NOT_SUPPORTED;
++ }
++
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGCOMMAND_FetchCommand
++**
++** Form a FETCH command at the specified location in the command buffer.
++**
++** INPUT:
++**
++** gckVGCOMMAND Command
++** Pointer to an gckVGCOMMAND object.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command buffer to append
++** FETCH command at or gcvNULL to query the size of the command.
++**
++** gctUINT32 FetchAddress
++** The address of another command buffer to be executed by this FETCH
++** command. If 'Logical' is gcvNULL, this argument is ignored.
++**
++** gctUINT FetchCount
++** The number of 64-bit data quantities in another command buffer to
++** be executed by this FETCH command. If 'Logical' is gcvNULL, this
++** argument is ignored.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the FETCH command.
++** If 'Logical' is gcvNULL, the value from this argument is ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** for the FETCH command. If 'Bytes' is gcvNULL, nothing is returned.
++*/
++gceSTATUS
++gckVGCOMMAND_FetchCommand(
++ IN gckVGCOMMAND Command,
++ IN gctPOINTER Logical,
++ IN gctUINT32 FetchAddress,
++ IN gctUINT FetchCount,
++ IN OUT gctSIZE_T * Bytes
++ )
++{
++ gcmkHEADER_ARG("Command=0x%x Logical=0x%x FetchAddress=0x%x FetchCount=0x%x Bytes = 0x%x",
++ Command, Logical, FetchAddress, FetchCount, Bytes);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ if (Command->fe20)
++ {
++ if (Logical != gcvNULL)
++ {
++ gctUINT32_PTR buffer;
++
++ /* Cast the buffer pointer. */
++ buffer = (gctUINT32_PTR) Logical;
++
++ /* Append FETCH. */
++ buffer[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28))) | (((gctUINT32) (0x5 & ((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 20:0) - (0 ? 20:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:0) - (0 ? 20:0) + 1))))))) << (0 ? 20:0))) | (((gctUINT32) ((gctUINT32) (FetchCount) & ((gctUINT32) ((((1 ? 20:0) - (0 ? 20:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:0) - (0 ? 20:0) + 1))))))) << (0 ? 20:0)));
++
++ buffer[1]
++ = gcmkFIXADDRESS(FetchAddress);
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the FETCH command. */
++ *Bytes = 8;
++ }
++ }
++ else
++ {
++ if (Logical != gcvNULL)
++ {
++ gctUINT32_PTR buffer;
++
++ /* Cast the buffer pointer. */
++ buffer = (gctUINT32_PTR) Logical;
++
++ /* Append LINK. */
++ buffer[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x08 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (FetchCount) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ buffer[1]
++ = gcmkFIXADDRESS(FetchAddress);
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the LINK command. */
++ *Bytes = 8;
++ }
++ }
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGCOMMAND_CallCommand
++**
++** Append a CALL command at the specified location in the command buffer.
++**
++** INPUT:
++**
++** gckVGCOMMAND Command
++** Pointer to an gckVGCOMMAND object.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command buffer to append
++** CALL command at or gcvNULL to query the size of the command.
++**
++** gctUINT32 FetchAddress
++** The address of another command buffer to be executed by this CALL
++** command. If 'Logical' is gcvNULL, this argument is ignored.
++**
++** gctUINT FetchCount
++** The number of 64-bit data quantities in another command buffer to
++** be executed by this CALL command. If 'Logical' is gcvNULL, this
++** argument is ignored.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the CALL command.
++** If 'Logical' is gcvNULL, the value from this argument is ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** for the CALL command. If 'Bytes' is gcvNULL, nothing is returned.
++*/
++gceSTATUS
++gckVGCOMMAND_CallCommand(
++ IN gckVGCOMMAND Command,
++ IN gctPOINTER Logical,
++ IN gctUINT32 FetchAddress,
++ IN gctUINT FetchCount,
++ IN OUT gctSIZE_T * Bytes
++ )
++{
++ gcmkHEADER_ARG("Command=0x%x Logical=0x%x FetchAddress=0x%x FetchCount=0x%x Bytes = 0x%x",
++ Command, Logical, FetchAddress, FetchCount, Bytes);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ if (Command->fe20)
++ {
++ if (Logical != gcvNULL)
++ {
++ gctUINT32_PTR buffer;
++
++ /* Cast the buffer pointer. */
++ buffer = (gctUINT32_PTR) Logical;
++
++ /* Append CALL. */
++ buffer[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28))) | (((gctUINT32) (0x6 & ((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 20:0) - (0 ? 20:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:0) - (0 ? 20:0) + 1))))))) << (0 ? 20:0))) | (((gctUINT32) ((gctUINT32) (FetchCount) & ((gctUINT32) ((((1 ? 20:0) - (0 ? 20:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:0) - (0 ? 20:0) + 1))))))) << (0 ? 20:0)));
++
++ buffer[1]
++ = gcmkFIXADDRESS(FetchAddress);
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the CALL command. */
++ *Bytes = 8;
++ }
++ }
++ else
++ {
++ gcmkFOOTER_NO();
++ return gcvSTATUS_NOT_SUPPORTED;
++ }
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGCOMMAND_ReturnCommand
++**
++** Append a RETURN command at the specified location in the command buffer.
++**
++** INPUT:
++**
++** gckVGCOMMAND Command
++** Pointer to an gckVGCOMMAND object.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command buffer to append
++** RETURN command at or gcvNULL to query the size of the command.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the RETURN command.
++** If 'Logical' is gcvNULL, the value from this argument is ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** for the RETURN command. If 'Bytes' is gcvNULL, nothing is returned.
++*/
++gceSTATUS
++gckVGCOMMAND_ReturnCommand(
++ IN gckVGCOMMAND Command,
++ IN gctPOINTER Logical,
++ IN OUT gctSIZE_T * Bytes
++ )
++{
++ gcmkHEADER_ARG("Command=0x%x Logical=0x%x Bytes = 0x%x",
++ Command, Logical, Bytes);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ if (Command->fe20)
++ {
++ if (Logical != gcvNULL)
++ {
++ gctUINT32_PTR buffer;
++
++ /* Cast the buffer pointer. */
++ buffer = (gctUINT32_PTR) Logical;
++
++ /* Append RETURN. */
++ buffer[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28))) | (((gctUINT32) (0x7 & ((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28)));
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the RETURN command. */
++ *Bytes = 8;
++ }
++ }
++ else
++ {
++ gcmkFOOTER_NO();
++ return gcvSTATUS_NOT_SUPPORTED;
++ }
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGCOMMAND_EventCommand
++**
++** Form an EVENT command at the specified location in the command buffer.
++**
++** INPUT:
++**
++** gckVGCOMMAND Command
++** Pointer to the Command object.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command buffer to append
++** EVENT command at or gcvNULL to query the size of the command.
++**
++** gctINT32 InterruptId
++** The ID of the interrupt to generate.
++** If 'Logical' is gcvNULL, this argument is ignored.
++**
++** gceBLOCK Block
++** Block that will generate the interrupt.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the EVENT command.
++** If 'Logical' is gcvNULL, the value from this argument is ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** for the END command. If 'Bytes' is gcvNULL, nothing is returned.
++*/
++gceSTATUS
++gckVGCOMMAND_EventCommand(
++ IN gckVGCOMMAND Command,
++ IN gctPOINTER Logical,
++ IN gceBLOCK Block,
++ IN gctINT32 InterruptId,
++ IN OUT gctSIZE_T * Bytes
++ )
++{
++ gcmkHEADER_ARG("Command=0x%x Logical=0x%x Block=0x%x InterruptId=0x%x Bytes = 0x%x",
++ Command, Logical, Block, InterruptId, Bytes);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ if (Command->fe20)
++ {
++ typedef struct _gcsEVENTSTATES
++ {
++ /* Chips before VG21 use these values. */
++ gctUINT eventFromFE;
++ gctUINT eventFromPE;
++
++ /* VG21 chips and later use SOURCE field. */
++ gctUINT eventSource;
++ }
++ gcsEVENTSTATES;
++
++ static gcsEVENTSTATES states[] =
++ {
++ /* gcvBLOCK_COMMAND */
++ {
++ (gctUINT)~0,
++ (gctUINT)~0,
++ (gctUINT)~0
++ },
++
++ /* gcvBLOCK_TESSELLATOR */
++ {
++ 0x0,
++ 0x1,
++ 0x10
++ },
++
++ /* gcvBLOCK_TESSELLATOR2 */
++ {
++ 0x0,
++ 0x1,
++ 0x12
++ },
++
++ /* gcvBLOCK_TESSELLATOR3 */
++ {
++ 0x0,
++ 0x1,
++ 0x14
++ },
++
++ /* gcvBLOCK_RASTER */
++ {
++ 0x0,
++ 0x1,
++ 0x07,
++ },
++
++ /* gcvBLOCK_VG */
++ {
++ 0x0,
++ 0x1,
++ 0x0F
++ },
++
++ /* gcvBLOCK_VG2 */
++ {
++ 0x0,
++ 0x1,
++ 0x11
++ },
++
++ /* gcvBLOCK_VG3 */
++ {
++ 0x0,
++ 0x1,
++ 0x13
++ },
++
++ /* gcvBLOCK_PIXEL */
++ {
++ 0x0,
++ 0x1,
++ 0x07
++ },
++ };
++
++ /* Verify block ID. */
++ gcmkVERIFY_ARGUMENT(gcmIS_VALID_INDEX(Block, states));
++
++ if (Logical != gcvNULL)
++ {
++ gctUINT32_PTR buffer;
++
++ /* Verify the event ID. */
++ gcmkVERIFY_ARGUMENT(InterruptId >= 0);
++ gcmkVERIFY_ARGUMENT(InterruptId <= ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))));
++
++ /* Cast the buffer pointer. */
++ buffer = (gctUINT32_PTR) Logical;
++
++ /* Append EVENT. */
++ buffer[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28))) | (((gctUINT32) (0x3 & ((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 11:0) - (0 ? 11:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:0) - (0 ? 11:0) + 1))))))) << (0 ? 11:0))) | (((gctUINT32) ((gctUINT32) (0x0E01) & ((gctUINT32) ((((1 ? 11:0) - (0 ? 11:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:0) - (0 ? 11:0) + 1))))))) << (0 ? 11:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 27:16) - (0 ? 27:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:16) - (0 ? 27:16) + 1))))))) << (0 ? 27:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 27:16) - (0 ? 27:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:16) - (0 ? 27:16) + 1))))))) << (0 ? 27:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 13:12) - (0 ? 13:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 13:12) - (0 ? 13:12) + 1))))))) << (0 ? 13:12))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 13:12) - (0 ? 13:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 13:12) - (0 ? 13:12) + 1))))))) << (0 ? 13:12)));
++
++ /* Determine chip version. */
++ if (Command->vg21)
++ {
++ /* Get the event source for the block. */
++ gctUINT eventSource = states[Block].eventSource;
++
++ /* Supported? */
++ if (eventSource == ~0)
++ {
++ gcmkFOOTER_NO();
++ return gcvSTATUS_NOT_SUPPORTED;
++ }
++
++ buffer[1]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) ((gctUINT32) (InterruptId) & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) ((gctUINT32) (eventSource) & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++ }
++ else
++ {
++ /* Get the event source for the block. */
++ gctUINT eventFromFE = states[Block].eventFromFE;
++ gctUINT eventFromPE = states[Block].eventFromPE;
++
++ /* Supported? */
++ if (eventFromFE == ~0)
++ {
++ gcmkFOOTER_NO();
++ return gcvSTATUS_NOT_SUPPORTED;
++ }
++
++ buffer[1]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) ((gctUINT32) (InterruptId) & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))) | (((gctUINT32) ((gctUINT32) (eventFromFE) & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6))) | (((gctUINT32) ((gctUINT32) (eventFromPE) & ((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6)));
++ }
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Make sure the events are directly supported for the block. */
++ if (states[Block].eventSource == ~0)
++ {
++ gcmkFOOTER_NO();
++ return gcvSTATUS_NOT_SUPPORTED;
++ }
++
++ /* Return number of bytes required by the END command. */
++ *Bytes = 8;
++ }
++ }
++ else
++ {
++ if (Logical != gcvNULL)
++ {
++ gctUINT32_PTR buffer;
++
++ /* Verify the event ID. */
++ gcmkVERIFY_ARGUMENT(InterruptId >= 0);
++ gcmkVERIFY_ARGUMENT(InterruptId <= ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))));
++
++ /* Cast the buffer pointer. */
++ buffer = (gctUINT32_PTR) Logical;
++
++ /* Append EVENT. */
++ buffer[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E01) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ /* Determine event source. */
++ if (Block == gcvBLOCK_COMMAND)
++ {
++ buffer[1]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) ((gctUINT32) (InterruptId) & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5)));
++ }
++ else
++ {
++ buffer[1]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) ((gctUINT32) (InterruptId) & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6)));
++ }
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the EVENT and END commands. */
++ *Bytes = 8;
++ }
++ }
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGCOMMAND_EndCommand
++**
++** Form an END command at the specified location in the command buffer.
++**
++** INPUT:
++**
++** gckVGCOMMAND Command
++** Pointer to the Command object.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command buffer to append
++** END command at or gcvNULL to query the size of the command.
++**
++** gctINT32 InterruptId
++** The ID of the interrupt to generate.
++** If 'Logical' is gcvNULL, this argument will be ignored.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the END command.
++** If 'Logical' is gcvNULL, the value from this argument is ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** for the END command. If 'Bytes' is gcvNULL, nothing is returned.
++*/
++gceSTATUS
++gckVGCOMMAND_EndCommand(
++ IN gckVGCOMMAND Command,
++ IN gctPOINTER Logical,
++ IN gctINT32 InterruptId,
++ IN OUT gctSIZE_T * Bytes
++ )
++{
++ gcmkHEADER_ARG("Command=0x%x Logical=0x%x InterruptId=0x%x Bytes = 0x%x",
++ Command, Logical, InterruptId, Bytes);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ if (Command->fe20)
++ {
++ if (Logical != gcvNULL)
++ {
++ gctUINT32_PTR buffer;
++
++ /* Verify the event ID. */
++ gcmkVERIFY_ARGUMENT(InterruptId >= 0);
++
++ /* Cast the buffer pointer. */
++ buffer = (gctUINT32_PTR) Logical;
++
++ /* Append END. */
++ buffer[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) ((gctUINT32) (InterruptId) & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)));
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the END command. */
++ *Bytes = 8;
++ }
++ }
++ else
++ {
++ if (Logical != gcvNULL)
++ {
++ gctUINT32_PTR memory;
++
++ /* Verify the event ID. */
++ gcmkVERIFY_ARGUMENT(InterruptId >= 0);
++
++ /* Cast the buffer pointer. */
++ memory = (gctUINT32_PTR) Logical;
++
++ /* Append EVENT. */
++ memory[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E01) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ memory[1]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) ((gctUINT32) (InterruptId) & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6)));
++
++ /* Append END. */
++ memory[2]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x02 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the EVENT and END commands. */
++ *Bytes = 16;
++ }
++ }
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++#endif /* gcdENABLE_VG */
++
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/arch/GC350/hal/kernel/gc_hal_kernel_hardware_command_vg.h linux-xbian-imx6/drivers/mxc/gpu-viv/arch/GC350/hal/kernel/gc_hal_kernel_hardware_command_vg.h
+--- linux-4.1.3/drivers/mxc/gpu-viv/arch/GC350/hal/kernel/gc_hal_kernel_hardware_command_vg.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/arch/GC350/hal/kernel/gc_hal_kernel_hardware_command_vg.h 2015-07-27 23:13:06.166979215 +0200
+@@ -0,0 +1,319 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_kernel_hardware_command_vg_h_
++#define __gc_hal_kernel_hardware_command_vg_h_
++
++/******************************************************************************\
++******************* Task and Interrupt Management Structures. ******************
++\******************************************************************************/
++
++/* Task storage header. */
++typedef struct _gcsTASK_STORAGE * gcsTASK_STORAGE_PTR;
++typedef struct _gcsTASK_STORAGE
++{
++ /* Next allocated storage buffer. */
++ gcsTASK_STORAGE_PTR next;
++}
++gcsTASK_STORAGE;
++
++/* Task container header. */
++typedef struct _gcsTASK_CONTAINER * gcsTASK_CONTAINER_PTR;
++typedef struct _gcsTASK_CONTAINER
++{
++ /* The number of tasks left to be processed in the container. */
++ gctINT referenceCount;
++
++ /* Size of the buffer. */
++ gctUINT size;
++
++ /* Link to the previous and the next allocated containers. */
++ gcsTASK_CONTAINER_PTR allocPrev;
++ gcsTASK_CONTAINER_PTR allocNext;
++
++ /* Link to the previous and the next containers in the free list. */
++ gcsTASK_CONTAINER_PTR freePrev;
++ gcsTASK_CONTAINER_PTR freeNext;
++}
++gcsTASK_CONTAINER;
++
++/* Kernel space task master table entry. */
++typedef struct _gcsBLOCK_TASK_ENTRY * gcsBLOCK_TASK_ENTRY_PTR;
++typedef struct _gcsBLOCK_TASK_ENTRY
++{
++ /* Pointer to the current task container for the block. */
++ gcsTASK_CONTAINER_PTR container;
++
++ /* Pointer to the current task data within the container. */
++ gcsTASK_HEADER_PTR task;
++
++ /* Pointer to the last link task within the container. */
++ gcsTASK_LINK_PTR link;
++
++ /* Number of interrupts allocated for this block. */
++ gctUINT interruptCount;
++
++ /* The index of the current interrupt. */
++ gctUINT interruptIndex;
++
++ /* Interrupt semaphore. */
++ gctSEMAPHORE interruptSemaphore;
++
++ /* Interrupt value array. */
++ gctINT32 interruptArray[32];
++}
++gcsBLOCK_TASK_ENTRY;
++
++
++/******************************************************************************\
++********************* Command Queue Management Structures. *********************
++\******************************************************************************/
++
++/* Command queue kernel element pointer. */
++typedef struct _gcsKERNEL_CMDQUEUE * gcsKERNEL_CMDQUEUE_PTR;
++
++/* Command queue object handler function type. */
++typedef gceSTATUS (* gctOBJECT_HANDLER) (
++ gckVGKERNEL Kernel,
++ gcsKERNEL_CMDQUEUE_PTR Entry
++ );
++
++/* Command queue kernel element. */
++typedef struct _gcsKERNEL_CMDQUEUE
++{
++ /* The number of buffers in the queue. */
++ gcsCMDBUFFER_PTR commandBuffer;
++
++ /* Pointer to the object handler function. */
++ gctOBJECT_HANDLER handler;
++}
++gcsKERNEL_CMDQUEUE;
++
++/* Command queue header. */
++typedef struct _gcsKERNEL_QUEUE_HEADER * gcsKERNEL_QUEUE_HEADER_PTR;
++typedef struct _gcsKERNEL_QUEUE_HEADER
++{
++ /* The size of the buffer in bytes. */
++ gctUINT size;
++
++ /* The number of pending entries to be processed. */
++ volatile gctUINT pending;
++
++ /* The current command queue entry. */
++ gcsKERNEL_CMDQUEUE_PTR currentEntry;
++
++ /* Next buffer. */
++ gcsKERNEL_QUEUE_HEADER_PTR next;
++}
++gcsKERNEL_QUEUE_HEADER;
++
++
++/******************************************************************************\
++******************************* gckVGCOMMAND Object *******************************
++\******************************************************************************/
++
++/* gckVGCOMMAND object. */
++struct _gckVGCOMMAND
++{
++ /***************************************************************************
++ ** Object data and pointers.
++ */
++
++ gcsOBJECT object;
++ gckVGKERNEL kernel;
++ gckOS os;
++ gckVGHARDWARE hardware;
++
++ /* Features. */
++ gctBOOL fe20;
++ gctBOOL vg20;
++ gctBOOL vg21;
++
++
++ /***************************************************************************
++ ** Enable command queue dumping.
++ */
++
++ gctBOOL enableDumping;
++
++
++ /***************************************************************************
++ ** Bus Error interrupt.
++ */
++
++ gctINT32 busErrorInt;
++
++
++ /***************************************************************************
++ ** Command buffer information.
++ */
++
++ gcsCOMMAND_BUFFER_INFO info;
++
++
++ /***************************************************************************
++ ** Synchronization objects.
++ */
++
++ gctPOINTER queueMutex;
++ gctPOINTER taskMutex;
++ gctPOINTER commitMutex;
++
++
++ /***************************************************************************
++ ** Task management.
++ */
++
++ /* The head of the storage buffer linked list. */
++ gcsTASK_STORAGE_PTR taskStorage;
++
++ /* Allocation size. */
++ gctUINT taskStorageGranularity;
++ gctUINT taskStorageUsable;
++
++ /* The free container list. */
++ gcsTASK_CONTAINER_PTR taskFreeHead;
++ gcsTASK_CONTAINER_PTR taskFreeTail;
++
++ /* Task table */
++ gcsBLOCK_TASK_ENTRY taskTable[gcvBLOCK_COUNT];
++
++
++ /***************************************************************************
++ ** Command queue.
++ */
++
++ /* Pointer to the allocated queue memory. */
++ gcsKERNEL_QUEUE_HEADER_PTR queue;
++
++ /* Pointer to the current available queue from which new queue entries
++ will be allocated. */
++ gcsKERNEL_QUEUE_HEADER_PTR queueHead;
++
++ /* If different from queueHead, points to the command queue which is
++ currently being executed by the hardware. */
++ gcsKERNEL_QUEUE_HEADER_PTR queueTail;
++
++ /* Points to the queue to merge the tail with when the tail is processed. */
++ gcsKERNEL_QUEUE_HEADER_PTR mergeQueue;
++
++ /* Queue overflow counter. */
++ gctUINT queueOverflow;
++
++
++ /***************************************************************************
++ ** Context.
++ */
++
++ /* Context counter used for unique ID. */
++ gctUINT64 contextCounter;
++
++ /* Current context ID. */
++ gctUINT64 currentContext;
++
++ /* Command queue power semaphore. */
++ gctPOINTER powerSemaphore;
++ gctINT32 powerStallInt;
++ gcsCMDBUFFER_PTR powerStallBuffer;
++ gctSIGNAL powerStallSignal;
++
++};
++
++/******************************************************************************\
++************************ gckVGCOMMAND Object Internal API. ***********************
++\******************************************************************************/
++
++/* Initialize architecture dependent command buffer information. */
++gceSTATUS
++gckVGCOMMAND_InitializeInfo(
++ IN gckVGCOMMAND Command
++ );
++
++/* Form a STATE command at the specified location in the command buffer. */
++gceSTATUS
++gckVGCOMMAND_StateCommand(
++ IN gckVGCOMMAND Command,
++ IN gctUINT32 Pipe,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Address,
++ IN gctSIZE_T Count,
++ IN OUT gctSIZE_T * Bytes
++ );
++
++/* Form a RESTART command at the specified location in the command buffer. */
++gceSTATUS
++gckVGCOMMAND_RestartCommand(
++ IN gckVGCOMMAND Command,
++ IN gctPOINTER Logical,
++ IN gctUINT32 FetchAddress,
++ IN gctUINT FetchCount,
++ IN OUT gctSIZE_T * Bytes
++ );
++
++/* Form a FETCH command at the specified location in the command buffer. */
++gceSTATUS
++gckVGCOMMAND_FetchCommand(
++ IN gckVGCOMMAND Command,
++ IN gctPOINTER Logical,
++ IN gctUINT32 FetchAddress,
++ IN gctUINT FetchCount,
++ IN OUT gctSIZE_T * Bytes
++ );
++
++/* Form a CALL command at the specified location in the command buffer. */
++gceSTATUS
++gckVGCOMMAND_CallCommand(
++ IN gckVGCOMMAND Command,
++ IN gctPOINTER Logical,
++ IN gctUINT32 FetchAddress,
++ IN gctUINT FetchCount,
++ IN OUT gctSIZE_T * Bytes
++ );
++
++/* Form a RETURN command at the specified location in the command buffer. */
++gceSTATUS
++gckVGCOMMAND_ReturnCommand(
++ IN gckVGCOMMAND Command,
++ IN gctPOINTER Logical,
++ IN OUT gctSIZE_T * Bytes
++ );
++
++/* Form an EVENT command at the specified location in the command buffer. */
++gceSTATUS
++gckVGCOMMAND_EventCommand(
++ IN gckVGCOMMAND Command,
++ IN gctPOINTER Logical,
++ IN gceBLOCK Block,
++ IN gctINT32 InterruptId,
++ IN OUT gctSIZE_T * Bytes
++ );
++
++/* Form an END command at the specified location in the command buffer. */
++gceSTATUS
++gckVGCOMMAND_EndCommand(
++ IN gckVGCOMMAND Command,
++ IN gctPOINTER Logical,
++ IN gctINT32 InterruptId,
++ IN OUT gctSIZE_T * Bytes
++ );
++
++#endif /* __gc_hal_kernel_hardware_command_h_ */
++
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/arch/GC350/hal/kernel/gc_hal_kernel_hardware_vg.c linux-xbian-imx6/drivers/mxc/gpu-viv/arch/GC350/hal/kernel/gc_hal_kernel_hardware_vg.c
+--- linux-4.1.3/drivers/mxc/gpu-viv/arch/GC350/hal/kernel/gc_hal_kernel_hardware_vg.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/arch/GC350/hal/kernel/gc_hal_kernel_hardware_vg.c 2015-07-27 23:13:06.166979215 +0200
+@@ -0,0 +1,2114 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal.h"
++#include "gc_hal_kernel.h"
++#include "gc_hal_kernel_hardware_command_vg.h"
++
++#if gcdENABLE_VG
++
++#define _GC_OBJ_ZONE gcvZONE_HARDWARE
++
++typedef enum
++{
++ gcvPOWER_FLAG_INITIALIZE = 1 << 0,
++ gcvPOWER_FLAG_STALL = 1 << 1,
++ gcvPOWER_FLAG_STOP = 1 << 2,
++ gcvPOWER_FLAG_START = 1 << 3,
++ gcvPOWER_FLAG_RELEASE = 1 << 4,
++ gcvPOWER_FLAG_DELAY = 1 << 5,
++ gcvPOWER_FLAG_SAVE = 1 << 6,
++ gcvPOWER_FLAG_ACQUIRE = 1 << 7,
++ gcvPOWER_FLAG_POWER_OFF = 1 << 8,
++ gcvPOWER_FLAG_CLOCK_OFF = 1 << 9,
++ gcvPOWER_FLAG_CLOCK_ON = 1 << 10,
++ gcvPOWER_FLAG_NOP = 1 << 11,
++}
++gcePOWER_FLAGS;
++
++/******************************************************************************\
++********************************* Support Code *********************************
++\******************************************************************************/
++static gceSTATUS
++_ResetGPU(
++ IN gckOS Os
++ )
++{
++ gctUINT32 control, idle;
++ gceSTATUS status;
++
++ /* Read register. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Os,
++ gcvCORE_VG,
++ 0x00000,
++ &control));
++
++ for (;;)
++ {
++ /* Disable clock gating. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ gcvCORE_VG,
++ 0x00104,
++ 0x00000000));
++
++ /* Wait for clock being stable. */
++ gcmkONERROR(gckOS_Delay(Os, 1));
++
++ /* Isolate the GPU. */
++ control = ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19)));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ gcvCORE_VG,
++ 0x00000,
++ control));
++
++ /* Set soft reset. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ gcvCORE_VG,
++ 0x00000,
++ ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12)))));
++
++ /* Wait for reset. */
++ gcmkONERROR(gckOS_Delay(Os, 1));
++
++ /* Reset soft reset bit. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ gcvCORE_VG,
++ 0x00000,
++ ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12)))));
++
++ /* Reset GPU isolation. */
++ control = ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19)));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ gcvCORE_VG,
++ 0x00000,
++ control));
++
++ /* Read idle register. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Os,
++ gcvCORE_VG,
++ 0x00004,
++ &idle));
++
++ if ((((((gctUINT32) (idle)) >> (0 ? 0:0)) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1)))))) ) == 0)
++ {
++ continue;
++ }
++
++ /* Read reset register. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Os,
++ gcvCORE_VG,
++ 0x00000,
++ &control));
++
++ if (((((((gctUINT32) (control)) >> (0 ? 16:16)) & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1)))))) ) == 0)
++ || ((((((gctUINT32) (control)) >> (0 ? 17:17)) & ((gctUINT32) ((((1 ? 17:17) - (0 ? 17:17) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 17:17) - (0 ? 17:17) + 1)))))) ) == 0)
++ )
++ {
++ continue;
++ }
++
++ /* GPU is idle. */
++ break;
++ }
++
++ /* Success. */
++ return gcvSTATUS_OK;
++
++OnError:
++
++ /* Return the error. */
++ return status;
++}
++
++
++static gceSTATUS
++_IdentifyHardware(
++ IN gckOS Os,
++ OUT gceCHIPMODEL * ChipModel,
++ OUT gctUINT32 * ChipRevision,
++ OUT gctUINT32 * ChipFeatures,
++ OUT gctUINT32 * ChipMinorFeatures,
++ OUT gctUINT32 * ChipMinorFeatures2
++ )
++{
++ gceSTATUS status;
++ gctUINT32 chipIdentity;
++
++ do
++ {
++ /* Read chip identity register. */
++ gcmkERR_BREAK(gckOS_ReadRegisterEx(Os, gcvCORE_VG, 0x00018, &chipIdentity));
++
++ /* Special case for older graphic cores. */
++ if (((((gctUINT32) (chipIdentity)) >> (0 ? 31:24) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1)))))) == (0x01 & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))))
++ {
++ *ChipModel = gcv500;
++ *ChipRevision = (((((gctUINT32) (chipIdentity)) >> (0 ? 15:12)) & ((gctUINT32) ((((1 ? 15:12) - (0 ? 15:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:12) - (0 ? 15:12) + 1)))))) );
++ }
++
++ else
++ {
++ /* Read chip identity register. */
++ gcmkERR_BREAK(gckOS_ReadRegisterEx(Os, gcvCORE_VG,
++ 0x00020,
++ (gctUINT32 *) ChipModel));
++
++ /* Read CHIP_REV register. */
++ gcmkERR_BREAK(gckOS_ReadRegisterEx(Os, gcvCORE_VG,
++ 0x00024,
++ ChipRevision));
++ }
++
++ /* Read chip feature register. */
++ gcmkERR_BREAK(gckOS_ReadRegisterEx(
++ Os, gcvCORE_VG, 0x0001C, ChipFeatures
++ ));
++
++ /* Read chip minor feature register. */
++ gcmkERR_BREAK(gckOS_ReadRegisterEx(
++ Os, gcvCORE_VG, 0x00034, ChipMinorFeatures
++ ));
++
++ /* Read chip minor feature register #2. */
++ gcmkERR_BREAK(gckOS_ReadRegisterEx(
++ Os, gcvCORE_VG, 0x00074, ChipMinorFeatures2
++ ));
++
++ gcmkTRACE(
++ gcvLEVEL_VERBOSE,
++ "ChipModel=0x%08X\n"
++ "ChipRevision=0x%08X\n"
++ "ChipFeatures=0x%08X\n"
++ "ChipMinorFeatures=0x%08X\n"
++ "ChipMinorFeatures2=0x%08X\n",
++ *ChipModel,
++ *ChipRevision,
++ *ChipFeatures,
++ *ChipMinorFeatures,
++ *ChipMinorFeatures2
++ );
++
++ /* Success. */
++ return gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ /* Return the status. */
++ return status;
++}
++
++#if gcdPOWEROFF_TIMEOUT
++void
++_VGPowerTimerFunction(
++ gctPOINTER Data
++ )
++{
++ gckVGHARDWARE hardware = (gckVGHARDWARE)Data;
++ gcmkVERIFY_OK(
++ gckVGHARDWARE_SetPowerManagementState(hardware, gcvPOWER_OFF_TIMEOUT));
++}
++#endif
++
++/******************************************************************************\
++****************************** gckVGHARDWARE API code *****************************
++\******************************************************************************/
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_Construct
++**
++** Construct a new gckVGHARDWARE object.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an initialized gckOS object.
++**
++** OUTPUT:
++**
++** gckVGHARDWARE * Hardware
++** Pointer to a variable that will hold the pointer to the gckVGHARDWARE
++** object.
++*/
++gceSTATUS
++gckVGHARDWARE_Construct(
++ IN gckOS Os,
++ OUT gckVGHARDWARE * Hardware
++ )
++{
++ gckVGHARDWARE hardware = gcvNULL;
++ gceSTATUS status;
++ gceCHIPMODEL chipModel;
++ gctUINT32 chipRevision;
++ gctUINT32 chipFeatures;
++ gctUINT32 chipMinorFeatures;
++ gctUINT32 chipMinorFeatures2;
++
++ gcmkHEADER_ARG("Os=0x%x Hardware=0x%x ", Os, Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Hardware != gcvNULL);
++
++ do
++ {
++ gcmkERR_BREAK(gckOS_SetGPUPower(Os, gcvCORE_VG, gcvTRUE, gcvTRUE));
++
++ status = _ResetGPU(Os);
++
++ if (status != gcvSTATUS_OK)
++ {
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "_ResetGPU failed: status=%d\n", status);
++ }
++
++ /* Identify the hardware. */
++ gcmkERR_BREAK(_IdentifyHardware(Os,
++ &chipModel, &chipRevision,
++ &chipFeatures, &chipMinorFeatures, &chipMinorFeatures2
++ ));
++
++ /* Allocate the gckVGHARDWARE object. */
++ gcmkERR_BREAK(gckOS_Allocate(Os,
++ gcmSIZEOF(struct _gckVGHARDWARE), (gctPOINTER *) &hardware
++ ));
++
++ /* Initialize the gckVGHARDWARE object. */
++ hardware->object.type = gcvOBJ_HARDWARE;
++ hardware->os = Os;
++
++ /* Set chip identity. */
++ hardware->chipModel = chipModel;
++ hardware->chipRevision = chipRevision;
++ hardware->chipFeatures = chipFeatures;
++ hardware->chipMinorFeatures = chipMinorFeatures;
++ hardware->chipMinorFeatures2 = chipMinorFeatures2;
++
++ hardware->powerMutex = gcvNULL;
++ hardware->chipPowerState = gcvPOWER_ON;
++ hardware->chipPowerStateGlobal = gcvPOWER_ON;
++ hardware->clockState = gcvTRUE;
++ hardware->powerState = gcvTRUE;
++
++#if gcdPOWEROFF_TIMEOUT
++ hardware->powerOffTime = 0;
++ hardware->powerOffTimeout = gcdPOWEROFF_TIMEOUT;
++
++ gcmkVERIFY_OK(gckOS_CreateTimer(Os,
++ _VGPowerTimerFunction,
++ (gctPOINTER)hardware,
++ &hardware->powerOffTimer));
++#endif
++
++ /* Determine whether FE 2.0 is present. */
++ hardware->fe20 = ((((gctUINT32) (hardware->chipFeatures)) >> (0 ? 28:28) & ((gctUINT32) ((((1 ? 28:28) - (0 ? 28:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 28:28) - (0 ? 28:28) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 28:28) - (0 ? 28:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 28:28) - (0 ? 28:28) + 1)))))));
++
++ /* Determine whether VG 2.0 is present. */
++ hardware->vg20 = ((((gctUINT32) (hardware->chipMinorFeatures)) >> (0 ? 13:13) & ((gctUINT32) ((((1 ? 13:13) - (0 ? 13:13) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 13:13) - (0 ? 13:13) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 13:13) - (0 ? 13:13) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 13:13) - (0 ? 13:13) + 1)))))));
++
++ /* Determine whether VG 2.1 is present. */
++ hardware->vg21 = ((((gctUINT32) (hardware->chipMinorFeatures)) >> (0 ? 18:18) & ((gctUINT32) ((((1 ? 18:18) - (0 ? 18:18) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 18:18) - (0 ? 18:18) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 18:18) - (0 ? 18:18) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 18:18) - (0 ? 18:18) + 1)))))));
++
++ /* Set default event mask. */
++ hardware->eventMask = 0xFFFFFFFF;
++
++ gcmkERR_BREAK(gckOS_AtomConstruct(Os, &hardware->pageTableDirty));
++
++ /* Set fast clear to auto. */
++ gcmkVERIFY_OK(gckVGHARDWARE_SetFastClear(hardware, -1));
++
++ gcmkERR_BREAK(gckOS_CreateMutex(Os, &hardware->powerMutex));
++
++ /* Enable power management by default. */
++ hardware->powerManagement = gcvTRUE;
++
++ /* Return pointer to the gckVGHARDWARE object. */
++ *Hardware = hardware;
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++#if gcdPOWEROFF_TIMEOUT
++ if (hardware->powerOffTimer != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_StopTimer(Os, hardware->powerOffTimer));
++ gcmkVERIFY_OK(gckOS_DestroyTimer(Os, hardware->powerOffTimer));
++ }
++#endif
++
++ if (hardware->pageTableDirty != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_AtomDestroy(Os, hardware->pageTableDirty));
++ }
++
++ if (hardware != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_Free(Os, hardware));
++ }
++
++ gcmkVERIFY_OK(gckOS_SetGPUPower(Os, gcvCORE_VG, gcvFALSE, gcvFALSE));
++
++ gcmkFOOTER();
++ /* Return the status. */
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_Destroy
++**
++** Destroy an gckVGHARDWARE object.
++**
++** INPUT:
++**
++** gckVGHARDWARE Hardware
++** Pointer to the gckVGHARDWARE object that needs to be destroyed.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckVGHARDWARE_Destroy(
++ IN gckVGHARDWARE Hardware
++ )
++{
++ gceSTATUS status;
++ gcmkHEADER_ARG("Hardware=0x%x ", Hardware);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Mark the object as unknown. */
++ Hardware->object.type = gcvOBJ_UNKNOWN;
++
++ if (Hardware->powerMutex != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_DeleteMutex(
++ Hardware->os, Hardware->powerMutex));
++ }
++
++#if gcdPOWEROFF_TIMEOUT
++ gcmkVERIFY_OK(gckOS_StopTimer(Hardware->os, Hardware->powerOffTimer));
++ gcmkVERIFY_OK(gckOS_DestroyTimer(Hardware->os, Hardware->powerOffTimer));
++#endif
++
++ if (Hardware->pageTableDirty != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_AtomDestroy(Hardware->os, Hardware->pageTableDirty));
++ }
++
++ /* Free the object. */
++ status = gckOS_Free(Hardware->os, Hardware);
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_QueryMemory
++**
++** Query the amount of memory available on the hardware.
++**
++** INPUT:
++**
++** gckVGHARDWARE Hardware
++** Pointer to the gckVGHARDWARE object.
++**
++** OUTPUT:
++**
++** gctSIZE_T * InternalSize
++** Pointer to a variable that will hold the size of the internal video
++** memory in bytes. If 'InternalSize' is gcvNULL, no information of the
++** internal memory will be returned.
++**
++** gctUINT32 * InternalBaseAddress
++** Pointer to a variable that will hold the hardware's base address for
++** the internal video memory. This pointer cannot be gcvNULL if
++** 'InternalSize' is also non-gcvNULL.
++**
++** gctUINT32 * InternalAlignment
++** Pointer to a variable that will hold the hardware's base address for
++** the internal video memory. This pointer cannot be gcvNULL if
++** 'InternalSize' is also non-gcvNULL.
++**
++** gctSIZE_T * ExternalSize
++** Pointer to a variable that will hold the size of the external video
++** memory in bytes. If 'ExternalSize' is gcvNULL, no information of the
++** external memory will be returned.
++**
++** gctUINT32 * ExternalBaseAddress
++** Pointer to a variable that will hold the hardware's base address for
++** the external video memory. This pointer cannot be gcvNULL if
++** 'ExternalSize' is also non-gcvNULL.
++**
++** gctUINT32 * ExternalAlignment
++** Pointer to a variable that will hold the hardware's base address for
++** the external video memory. This pointer cannot be gcvNULL if
++** 'ExternalSize' is also non-gcvNULL.
++**
++** gctUINT32 * HorizontalTileSize
++** Number of horizontal pixels per tile. If 'HorizontalTileSize' is
++** gcvNULL, no horizontal pixel per tile will be returned.
++**
++** gctUINT32 * VerticalTileSize
++** Number of vertical pixels per tile. If 'VerticalTileSize' is
++** gcvNULL, no vertical pixel per tile will be returned.
++*/
++gceSTATUS
++gckVGHARDWARE_QueryMemory(
++ IN gckVGHARDWARE Hardware,
++ OUT gctSIZE_T * InternalSize,
++ OUT gctUINT32 * InternalBaseAddress,
++ OUT gctUINT32 * InternalAlignment,
++ OUT gctSIZE_T * ExternalSize,
++ OUT gctUINT32 * ExternalBaseAddress,
++ OUT gctUINT32 * ExternalAlignment,
++ OUT gctUINT32 * HorizontalTileSize,
++ OUT gctUINT32 * VerticalTileSize
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x InternalSize=0x%x InternalBaseAddress=0x%x InternalAlignment=0x%x"
++ "ExternalSize=0x%x ExternalBaseAddress=0x%x ExternalAlignment=0x%x HorizontalTileSize=0x%x VerticalTileSize=0x%x",
++ Hardware, InternalSize, InternalBaseAddress, InternalAlignment,
++ ExternalSize, ExternalBaseAddress, ExternalAlignment, HorizontalTileSize, VerticalTileSize);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ if (InternalSize != gcvNULL)
++ {
++ /* No internal memory. */
++ *InternalSize = 0;
++ }
++
++ if (ExternalSize != gcvNULL)
++ {
++ /* No external memory. */
++ *ExternalSize = 0;
++ }
++
++ if (HorizontalTileSize != gcvNULL)
++ {
++ /* 4x4 tiles. */
++ *HorizontalTileSize = 4;
++ }
++
++ if (VerticalTileSize != gcvNULL)
++ {
++ /* 4x4 tiles. */
++ *VerticalTileSize = 4;
++ }
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_QueryChipIdentity
++**
++** Query the identity of the hardware.
++**
++** INPUT:
++**
++** gckVGHARDWARE Hardware
++** Pointer to the gckVGHARDWARE object.
++**
++** OUTPUT:
++**
++** gceCHIPMODEL * ChipModel
++** If 'ChipModel' is not gcvNULL, the variable it points to will
++** receive the model of the chip.
++**
++** gctUINT32 * ChipRevision
++** If 'ChipRevision' is not gcvNULL, the variable it points to will
++** receive the revision of the chip.
++**
++** gctUINT32 * ChipFeatures
++** If 'ChipFeatures' is not gcvNULL, the variable it points to will
++** receive the feature set of the chip.
++**
++** gctUINT32 * ChipMinorFeatures
++** If 'ChipMinorFeatures' is not gcvNULL, the variable it points to
++** will receive the minor feature set of the chip.
++**
++** gctUINT32 * ChipMinorFeatures2
++** If 'ChipMinorFeatures2' is not gcvNULL, the variable it points to
++** will receive the minor feature set of the chip.
++**
++*/
++gceSTATUS
++gckVGHARDWARE_QueryChipIdentity(
++ IN gckVGHARDWARE Hardware,
++ OUT gceCHIPMODEL * ChipModel,
++ OUT gctUINT32 * ChipRevision,
++ OUT gctUINT32* ChipFeatures,
++ OUT gctUINT32* ChipMinorFeatures,
++ OUT gctUINT32* ChipMinorFeatures2
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x ChipModel=0x%x ChipRevision=0x%x ChipFeatures = 0x%x ChipMinorFeatures = 0x%x ChipMinorFeatures2 = 0x%x",
++ Hardware, ChipModel, ChipRevision, ChipFeatures, ChipMinorFeatures, ChipMinorFeatures2);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Return chip model. */
++ if (ChipModel != gcvNULL)
++ {
++ *ChipModel = Hardware->chipModel;
++ }
++
++ /* Return revision number. */
++ if (ChipRevision != gcvNULL)
++ {
++ *ChipRevision = Hardware->chipRevision;
++ }
++
++ /* Return feature set. */
++ if (ChipFeatures != gcvNULL)
++ {
++ gctUINT32 features = Hardware->chipFeatures;
++
++ if ((((((gctUINT32) (features)) >> (0 ? 0:0)) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1)))))) ))
++ {
++ features = ((((gctUINT32) (features)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (Hardware->allowFastClear) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)));
++ }
++
++ /* Mark 2D pipe as available for GC500.0 since it did not have this *\
++ \* bit. */
++ if ((Hardware->chipModel == gcv500)
++ && (Hardware->chipRevision == 0)
++ )
++ {
++ features = ((((gctUINT32) (features)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9)));
++ }
++
++ /* Mark 2D pipe as available for GC300 since it did not have this *\
++ \* bit. */
++ if (Hardware->chipModel == gcv300)
++ {
++ features = ((((gctUINT32) (features)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9)));
++ }
++
++ *ChipFeatures = features;
++ }
++
++ /* Return minor feature set. */
++ if (ChipMinorFeatures != gcvNULL)
++ {
++ *ChipMinorFeatures = Hardware->chipMinorFeatures;
++ }
++
++ /* Return minor feature set #2. */
++ if (ChipMinorFeatures2 != gcvNULL)
++ {
++ *ChipMinorFeatures2 = Hardware->chipMinorFeatures2;
++ }
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_ConvertFormat
++**
++** Convert an API format to hardware parameters.
++**
++** INPUT:
++**
++** gckVGHARDWARE Hardware
++** Pointer to the gckVGHARDWARE object.
++**
++** gceSURF_FORMAT Format
++** API format to convert.
++**
++** OUTPUT:
++**
++** gctUINT32 * BitsPerPixel
++** Pointer to a variable that will hold the number of bits per pixel.
++**
++** gctUINT32 * BytesPerTile
++** Pointer to a variable that will hold the number of bytes per tile.
++*/
++gceSTATUS
++gckVGHARDWARE_ConvertFormat(
++ IN gckVGHARDWARE Hardware,
++ IN gceSURF_FORMAT Format,
++ OUT gctUINT32 * BitsPerPixel,
++ OUT gctUINT32 * BytesPerTile
++ )
++{
++ gctUINT32 bitsPerPixel;
++ gctUINT32 bytesPerTile;
++
++ gcmkHEADER_ARG("Hardware=0x%x Format=0x%x BitsPerPixel=0x%x BytesPerTile = 0x%x",
++ Hardware, Format, BitsPerPixel, BytesPerTile);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Dispatch on format. */
++ switch (Format)
++ {
++ case gcvSURF_A1:
++ case gcvSURF_L1:
++ /* 1-bpp format. */
++ bitsPerPixel = 1;
++ bytesPerTile = (1 * 4 * 4) / 8;
++ break;
++
++ case gcvSURF_A4:
++ /* 4-bpp format. */
++ bitsPerPixel = 4;
++ bytesPerTile = (4 * 4 * 4) / 8;
++ break;
++
++ case gcvSURF_INDEX8:
++ case gcvSURF_A8:
++ case gcvSURF_L8:
++ /* 8-bpp format. */
++ bitsPerPixel = 8;
++ bytesPerTile = (8 * 4 * 4) / 8;
++ break;
++
++ case gcvSURF_YV12:
++ /* 12-bpp planar YUV formats. */
++ bitsPerPixel = 12;
++ bytesPerTile = (12 * 4 * 4) / 8;
++ break;
++
++ case gcvSURF_NV12:
++ /* 12-bpp planar YUV formats. */
++ bitsPerPixel = 12;
++ bytesPerTile = (12 * 4 * 4) / 8;
++ break;
++
++ /* 4444 variations. */
++ case gcvSURF_X4R4G4B4:
++ case gcvSURF_A4R4G4B4:
++ case gcvSURF_R4G4B4X4:
++ case gcvSURF_R4G4B4A4:
++ case gcvSURF_B4G4R4X4:
++ case gcvSURF_B4G4R4A4:
++ case gcvSURF_X4B4G4R4:
++ case gcvSURF_A4B4G4R4:
++
++ /* 1555 variations. */
++ case gcvSURF_X1R5G5B5:
++ case gcvSURF_A1R5G5B5:
++ case gcvSURF_R5G5B5X1:
++ case gcvSURF_R5G5B5A1:
++ case gcvSURF_X1B5G5R5:
++ case gcvSURF_A1B5G5R5:
++ case gcvSURF_B5G5R5X1:
++ case gcvSURF_B5G5R5A1:
++
++ /* 565 variations. */
++ case gcvSURF_R5G6B5:
++ case gcvSURF_B5G6R5:
++
++ case gcvSURF_A8L8:
++ case gcvSURF_YUY2:
++ case gcvSURF_UYVY:
++ case gcvSURF_D16:
++ /* 16-bpp format. */
++ bitsPerPixel = 16;
++ bytesPerTile = (16 * 4 * 4) / 8;
++ break;
++
++ case gcvSURF_X8R8G8B8:
++ case gcvSURF_A8R8G8B8:
++ case gcvSURF_X8B8G8R8:
++ case gcvSURF_A8B8G8R8:
++ case gcvSURF_R8G8B8X8:
++ case gcvSURF_R8G8B8A8:
++ case gcvSURF_B8G8R8X8:
++ case gcvSURF_B8G8R8A8:
++ case gcvSURF_D32:
++ /* 32-bpp format. */
++ bitsPerPixel = 32;
++ bytesPerTile = (32 * 4 * 4) / 8;
++ break;
++
++ case gcvSURF_D24S8:
++ /* 24-bpp format. */
++ bitsPerPixel = 32;
++ bytesPerTile = (32 * 4 * 4) / 8;
++ break;
++
++ case gcvSURF_DXT1:
++ case gcvSURF_ETC1:
++ bitsPerPixel = 4;
++ bytesPerTile = (4 * 4 * 4) / 8;
++ break;
++
++ case gcvSURF_DXT2:
++ case gcvSURF_DXT3:
++ case gcvSURF_DXT4:
++ case gcvSURF_DXT5:
++ bitsPerPixel = 8;
++ bytesPerTile = (8 * 4 * 4) / 8;
++ break;
++
++ default:
++ /* Invalid format. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_INVALID_ARGUMENT;
++ }
++
++ /* Set the result. */
++ if (BitsPerPixel != gcvNULL)
++ {
++ * BitsPerPixel = bitsPerPixel;
++ }
++
++ if (BytesPerTile != gcvNULL)
++ {
++ * BytesPerTile = bytesPerTile;
++ }
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_SplitMemory
++**
++** Split a hardware specific memory address into a pool and offset.
++**
++** INPUT:
++**
++** gckVGHARDWARE Hardware
++** Pointer to the gckVGHARDWARE object.
++**
++** gctUINT32 Address
++** Address in hardware specific format.
++**
++** OUTPUT:
++**
++** gcePOOL * Pool
++** Pointer to a variable that will hold the pool type for the address.
++**
++** gctUINT32 * Offset
++** Pointer to a variable that will hold the offset for the address.
++*/
++gceSTATUS
++gckVGHARDWARE_SplitMemory(
++ IN gckVGHARDWARE Hardware,
++ IN gctUINT32 Address,
++ OUT gcePOOL * Pool,
++ OUT gctUINT32 * Offset
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x Address=0x%x Pool=0x%x Offset = 0x%x",
++ Hardware, Address, Pool, Offset);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(Pool != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Offset != gcvNULL);
++
++ /* Dispatch on memory type. */
++ switch ((((((gctUINT32) (Address)) >> (0 ? 1:0)) & ((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1)))))) ))
++ {
++ case 0x0:
++ /* System memory. */
++ *Pool = gcvPOOL_SYSTEM;
++ break;
++
++ case 0x2:
++ /* Virtual memory. */
++ *Pool = gcvPOOL_VIRTUAL;
++ break;
++
++ default:
++ /* Invalid memory type. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_INVALID_ARGUMENT;
++ }
++
++ /* Return offset of address. */
++ *Offset = ((((gctUINT32) (Address)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0)));
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_Execute
++**
++** Kickstart the hardware's command processor with an initialized command
++** buffer.
++**
++** INPUT:
++**
++** gckVGHARDWARE Hardware
++** Pointer to the gckVGHARDWARE object.
++**
++** gctUINT32 Address
++** Address of the command buffer.
++**
++** gctSIZE_T Count
++** Number of command-sized data units to be executed.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckVGHARDWARE_Execute(
++ IN gckVGHARDWARE Hardware,
++ IN gctUINT32 Address,
++ IN gctSIZE_T Count
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Hardware=0x%x Address=0x%x Count=0x%x",
++ Hardware, Address, Count);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ do
++ {
++ /* Enable all events. */
++ gcmkERR_BREAK(gckOS_WriteRegisterEx(
++ Hardware->os,
++ gcvCORE_VG,
++ 0x00014,
++ Hardware->eventMask
++ ));
++
++ if (Hardware->fe20)
++ {
++ /* Write address register. */
++ gcmkERR_BREAK(gckOS_WriteRegisterEx(
++ Hardware->os,
++ gcvCORE_VG,
++ 0x00500,
++ gcmkFIXADDRESS(Address)
++ ));
++
++ /* Write control register. */
++ gcmkERR_BREAK(gckOS_WriteRegisterEx(
++ Hardware->os,
++ gcvCORE_VG,
++ 0x00504,
++ Count
++ ));
++ }
++ else
++ {
++ /* Write address register. */
++ gcmkERR_BREAK(gckOS_WriteRegisterEx(
++ Hardware->os,
++ gcvCORE_VG,
++ 0x00654,
++ gcmkFIXADDRESS(Address)
++ ));
++
++ /* Write control register. */
++ gcmkERR_BREAK(gckOS_WriteRegisterEx(
++ Hardware->os,
++ gcvCORE_VG,
++ 0x00658,
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) << (0 ? 16:16))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) << (0 ? 16:16))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (Count) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ ));
++ }
++
++ /* Success. */
++ gcmkFOOTER();
++ return gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++
++ gcmkFOOTER();
++ /* Return the status. */
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_AlignToTile
++**
++** Align the specified width and height to tile boundaries.
++**
++** INPUT:
++**
++** gckVGHARDWARE Hardware
++** Pointer to an gckVGHARDWARE object.
++**
++** gceSURF_TYPE Type
++** Type of alignment.
++**
++** gctUINT32 * Width
++** Pointer to the width to be aligned. If 'Width' is gcvNULL, no width
++** will be aligned.
++**
++** gctUINT32 * Height
++** Pointer to the height to be aligned. If 'Height' is gcvNULL, no height
++** will be aligned.
++**
++** OUTPUT:
++**
++** gctUINT32 * Width
++** Pointer to a variable that will receive the aligned width.
++**
++** gctUINT32 * Height
++** Pointer to a variable that will receive the aligned height.
++*/
++gceSTATUS
++gckVGHARDWARE_AlignToTile(
++ IN gckVGHARDWARE Hardware,
++ IN gceSURF_TYPE Type,
++ IN OUT gctUINT32 * Width,
++ IN OUT gctUINT32 * Height
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x Type=0x%x Width=0x%x Height=0x%x",
++ Hardware, Type, Width, Height);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ if (Width != gcvNULL)
++ {
++ /* Align the width. */
++ *Width = gcmALIGN(*Width, (Type == gcvSURF_TEXTURE) ? 4 : 16);
++ }
++
++ if (Height != gcvNULL)
++ {
++ /* Special case for VG images. */
++ if ((*Height == 0) && (Type == gcvSURF_IMAGE))
++ {
++ *Height = 4;
++ }
++ else
++ {
++ /* Align the height. */
++ *Height = gcmALIGN(*Height, 4);
++ }
++ }
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_ConvertLogical
++**
++** Convert a logical system address into a hardware specific address.
++**
++** INPUT:
++**
++** gckVGHARDWARE Hardware
++** Pointer to an gckVGHARDWARE object.
++**
++** gctPOINTER Logical
++** Logical address to convert.
++**
++** gctUINT32* Address
++** Return hardware specific address.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckVGHARDWARE_ConvertLogical(
++ IN gckVGHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ OUT gctUINT32 * Address
++ )
++{
++ gctUINT32 address;
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x Address=0x%x",
++ Hardware, Logical, Address);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Address != gcvNULL);
++
++ do
++ {
++ /* Convert logical address into a physical address. */
++ gcmkERR_BREAK(gckOS_GetPhysicalAddress(
++ Hardware->os, Logical, &address
++ ));
++
++ /* Return hardware specific address. */
++ *Address = ((((gctUINT32) (address)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0)));
++
++ /* Success. */
++ gcmkFOOTER();
++ return gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ gcmkFOOTER();
++ /* Return the status. */
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_QuerySystemMemory
++**
++** Query the command buffer alignment and number of reserved bytes.
++**
++** INPUT:
++**
++** gckVGHARDWARE Harwdare
++** Pointer to an gckVGHARDWARE object.
++**
++** OUTPUT:
++**
++** gctSIZE_T * SystemSize
++** Pointer to a variable that receives the maximum size of the system
++** memory.
++**
++** gctUINT32 * SystemBaseAddress
++** Poinetr to a variable that receives the base address for system
++** memory.
++*/
++gceSTATUS gckVGHARDWARE_QuerySystemMemory(
++ IN gckVGHARDWARE Hardware,
++ OUT gctSIZE_T * SystemSize,
++ OUT gctUINT32 * SystemBaseAddress
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x SystemSize=0x%x SystemBaseAddress=0x%x",
++ Hardware, SystemSize, SystemBaseAddress);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ if (SystemSize != gcvNULL)
++ {
++ /* Maximum system memory can be 2GB. */
++ *SystemSize = (gctSIZE_T)(1 << 31);
++ }
++
++ if (SystemBaseAddress != gcvNULL)
++ {
++ /* Set system memory base address. */
++ *SystemBaseAddress = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0)));
++ }
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_SetMMU
++**
++** Set the page table base address.
++**
++** INPUT:
++**
++** gckVGHARDWARE Harwdare
++** Pointer to an gckVGHARDWARE object.
++**
++** gctPOINTER Logical
++** Logical address of the page table.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS gckVGHARDWARE_SetMMU(
++ IN gckVGHARDWARE Hardware,
++ IN gctPOINTER Logical
++ )
++{
++ gceSTATUS status;
++ gctUINT32 address = 0;
++
++ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x",
++ Hardware, Logical);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++
++ do
++ {
++ /* Convert the logical address into an hardware address. */
++ gcmkERR_BREAK(gckVGHARDWARE_ConvertLogical(Hardware, Logical, &address) );
++
++ /* Write the AQMemoryFePageTable register. */
++ gcmkERR_BREAK(gckOS_WriteRegisterEx(Hardware->os, gcvCORE_VG,
++ 0x00400,
++ gcmkFIXADDRESS(address)) );
++
++ /* Write the AQMemoryTxPageTable register. */
++ gcmkERR_BREAK(gckOS_WriteRegisterEx(Hardware->os, gcvCORE_VG,
++ 0x00404,
++ gcmkFIXADDRESS(address)) );
++
++ /* Write the AQMemoryPePageTable register. */
++ gcmkERR_BREAK(gckOS_WriteRegisterEx(Hardware->os, gcvCORE_VG,
++ 0x00408,
++ gcmkFIXADDRESS(address)) );
++
++ /* Write the AQMemoryPezPageTable register. */
++ gcmkERR_BREAK(gckOS_WriteRegisterEx(Hardware->os, gcvCORE_VG,
++ 0x0040C,
++ gcmkFIXADDRESS(address)) );
++
++ /* Write the AQMemoryRaPageTable register. */
++ gcmkERR_BREAK(gckOS_WriteRegisterEx(Hardware->os, gcvCORE_VG,
++ 0x00410,
++ gcmkFIXADDRESS(address)) );
++ }
++ while (gcvFALSE);
++
++ gcmkFOOTER();
++ /* Return the status. */
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_FlushMMU
++**
++** Flush the page table.
++**
++** INPUT:
++**
++** gckVGHARDWARE Harwdare
++** Pointer to an gckVGHARDWARE object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS gckVGHARDWARE_FlushMMU(
++ IN gckVGHARDWARE Hardware
++ )
++{
++ gceSTATUS status;
++ gckVGCOMMAND command;
++
++ gcmkHEADER_ARG("Hardware=0x%x ", Hardware);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ do
++ {
++ gcsCMDBUFFER_PTR commandBuffer;
++ gctUINT32_PTR buffer;
++
++ /* Create a shortcut to the command buffer object. */
++ command = Hardware->kernel->command;
++
++ /* Allocate command buffer space. */
++ gcmkERR_BREAK(gckVGCOMMAND_Allocate(
++ command, 8, &commandBuffer, (gctPOINTER *) &buffer
++ ));
++
++ buffer[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E04) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ buffer[1]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4)));
++ }
++ while(gcvFALSE);
++
++ gcmkFOOTER();
++ /* Return the status. */
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_BuildVirtualAddress
++**
++** Build a virtual address.
++**
++** INPUT:
++**
++** gckVGHARDWARE Harwdare
++** Pointer to an gckVGHARDWARE object.
++**
++** gctUINT32 Index
++** Index into page table.
++**
++** gctUINT32 Offset
++** Offset into page.
++**
++** OUTPUT:
++**
++** gctUINT32 * Address
++** Pointer to a variable receiving te hardware address.
++*/
++gceSTATUS gckVGHARDWARE_BuildVirtualAddress(
++ IN gckVGHARDWARE Hardware,
++ IN gctUINT32 Index,
++ IN gctUINT32 Offset,
++ OUT gctUINT32 * Address
++ )
++{
++ gctUINT32 address;
++
++ gcmkHEADER_ARG("Hardware=0x%x Index=0x%x Offset=0x%x Address=0x%x",
++ Hardware, Index, Offset, Address);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(Address != gcvNULL);
++
++ /* Build virtual address. */
++ address = (Index << 12) | Offset;
++
++ /* Set virtual type. */
++ address = ((((gctUINT32) (address)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0))) | (((gctUINT32) (0x2 & ((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0)));
++
++ /* Set the result. */
++ *Address = address;
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckVGHARDWARE_GetIdle(
++ IN gckVGHARDWARE Hardware,
++ OUT gctUINT32 * Data
++ )
++{
++ gceSTATUS status;
++ gcmkHEADER_ARG("Hardware=0x%x Data=0x%x", Hardware, Data);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(Data != gcvNULL);
++
++ /* Read register and return. */
++ status = gckOS_ReadRegisterEx(Hardware->os, gcvCORE_VG, 0x00004, Data);
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckVGHARDWARE_SetFastClear(
++ IN gckVGHARDWARE Hardware,
++ IN gctINT Enable
++ )
++{
++ gctUINT32 debug;
++ gceSTATUS status;
++
++ if (!(((((gctUINT32) (Hardware->chipFeatures)) >> (0 ? 0:0)) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1)))))) ))
++ {
++ return gcvSTATUS_OK;
++ }
++
++ do
++ {
++ if (Enable == -1)
++ {
++ Enable = (Hardware->chipModel > gcv500) ||
++ ((Hardware->chipModel == gcv500) && (Hardware->chipRevision >= 3));
++ }
++
++ gcmkERR_BREAK(gckOS_ReadRegisterEx(Hardware->os, gcvCORE_VG,
++ 0x00414,
++ &debug));
++
++ debug = ((((gctUINT32) (debug)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 20:20) - (0 ? 20:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:20) - (0 ? 20:20) + 1))))))) << (0 ? 20:20))) | (((gctUINT32) ((gctUINT32) (Enable == 0) & ((gctUINT32) ((((1 ? 20:20) - (0 ? 20:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:20) - (0 ? 20:20) + 1))))))) << (0 ? 20:20)));
++
++#ifdef AQ_MEMORY_DEBUG_DISABLE_Z_COMPRESSION
++ debug = ((((gctUINT32) (debug)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? AQ_MEMORY_DEBUG_DISABLE_Z_COMPRESSION) - (0 ? AQ_MEMORY_DEBUG_DISABLE_Z_COMPRESSION) + 1) == 32) ? ~0 : (~(~0 << ((1 ? AQ_MEMORY_DEBUG_DISABLE_Z_COMPRESSION) - (0 ? AQ_MEMORY_DEBUG_DISABLE_Z_COMPRESSION) + 1))))))) << (0 ? AQ_MEMORY_DEBUG_DISABLE_Z_COMPRESSION))) | (((gctUINT32) ((gctUINT32) (Enable == 0) & ((gctUINT32) ((((1 ? AQ_MEMORY_DEBUG_DISABLE_Z_COMPRESSION) - (0 ? AQ_MEMORY_DEBUG_DISABLE_Z_COMPRESSION) + 1) == 32) ? ~0 : (~(~0 << ((1 ? AQ_MEMORY_DEBUG_DISABLE_Z_COMPRESSION) - (0 ? AQ_MEMORY_DEBUG_DISABLE_Z_COMPRESSION) + 1))))))) << (0 ? AQ_MEMORY_DEBUG_DISABLE_Z_COMPRESSION)));
++#endif
++
++ gcmkERR_BREAK(gckOS_WriteRegisterEx(Hardware->os, gcvCORE_VG,
++ 0x00414,
++ debug));
++
++ Hardware->allowFastClear = Enable;
++
++ status = gcvFALSE;
++ }
++ while (gcvFALSE);
++
++ return status;
++}
++
++gceSTATUS
++gckVGHARDWARE_ReadInterrupt(
++ IN gckVGHARDWARE Hardware,
++ OUT gctUINT32_PTR IDs
++ )
++{
++ gceSTATUS status;
++ gcmkHEADER_ARG("Hardware=0x%x IDs=0x%x", Hardware, IDs);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(IDs != gcvNULL);
++
++ /* Read AQIntrAcknowledge register. */
++ status = gckOS_ReadRegisterEx(Hardware->os, gcvCORE_VG,
++ 0x00010,
++ IDs);
++ gcmkFOOTER();
++ return status;
++}
++
++static gceSTATUS _CommandStall(
++ gckVGHARDWARE Hardware)
++{
++ gceSTATUS status;
++ gckVGCOMMAND command;
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ do
++ {
++ gctUINT32_PTR buffer;
++ command = Hardware->kernel->command;
++
++ /* Allocate command buffer space. */
++ gcmkERR_BREAK(gckVGCOMMAND_Allocate(
++ command, 8, &command->powerStallBuffer,
++ (gctPOINTER *) &buffer
++ ));
++
++ gcmkERR_BREAK(gckVGCOMMAND_EventCommand(
++ command, buffer, gcvBLOCK_PIXEL,
++ command->powerStallInt, gcvNULL));
++
++ gcmkERR_BREAK(gckVGCOMMAND_Execute(
++ command,
++ command->powerStallBuffer
++ ));
++
++ /* Wait the signal. */
++ gcmkERR_BREAK(gckOS_WaitSignal(
++ command->os,
++ command->powerStallSignal,
++ gcdGPU_TIMEOUT));
++
++
++ }
++ while(gcvFALSE);
++
++ gcmkFOOTER();
++ /* Return the status. */
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_SetPowerManagementState
++**
++** Set GPU to a specified power state.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** gceCHIPPOWERSTATE State
++** Power State.
++**
++*/
++gceSTATUS
++gckVGHARDWARE_SetPowerManagementState(
++ IN gckVGHARDWARE Hardware,
++ IN gceCHIPPOWERSTATE State
++ )
++{
++ gceSTATUS status;
++ gckVGCOMMAND command = gcvNULL;
++ gckOS os;
++ gctUINT flag/*, clock*/;
++
++ gctBOOL acquired = gcvFALSE;
++ gctBOOL stall = gcvTRUE;
++ gctBOOL commitMutex = gcvFALSE;
++ gctBOOL mutexAcquired = gcvFALSE;
++
++#if gcdPOWEROFF_TIMEOUT
++ gctBOOL timeout = gcvFALSE;
++ gctBOOL isAfter = gcvFALSE;
++ gctUINT32 currentTime;
++#endif
++
++ gctBOOL broadcast = gcvFALSE;
++ gctUINT32 process, thread;
++ gctBOOL global = gcvFALSE;
++
++#if gcdENABLE_PROFILING
++ gctUINT64 time, freq, mutexTime, onTime, stallTime, stopTime, delayTime,
++ initTime, offTime, startTime, totalTime;
++#endif
++
++ /* State transition flags. */
++ static const gctUINT flags[4][4] =
++ {
++ /* gcvPOWER_ON */
++ { /* ON */ 0,
++ /* OFF */ gcvPOWER_FLAG_ACQUIRE |
++ gcvPOWER_FLAG_STALL |
++ gcvPOWER_FLAG_STOP |
++ gcvPOWER_FLAG_POWER_OFF |
++ gcvPOWER_FLAG_CLOCK_OFF,
++ /* IDLE */ gcvPOWER_FLAG_NOP,
++ /* SUSPEND */ gcvPOWER_FLAG_ACQUIRE |
++ gcvPOWER_FLAG_STALL |
++ gcvPOWER_FLAG_STOP |
++ gcvPOWER_FLAG_CLOCK_OFF,
++ },
++
++ /* gcvPOWER_OFF */
++ { /* ON */ gcvPOWER_FLAG_INITIALIZE |
++ gcvPOWER_FLAG_START |
++ gcvPOWER_FLAG_RELEASE |
++ gcvPOWER_FLAG_DELAY,
++ /* OFF */ 0,
++ /* IDLE */ gcvPOWER_FLAG_INITIALIZE |
++ gcvPOWER_FLAG_START |
++ gcvPOWER_FLAG_RELEASE |
++ gcvPOWER_FLAG_DELAY,
++ /* SUSPEND */ gcvPOWER_FLAG_INITIALIZE |
++ gcvPOWER_FLAG_CLOCK_OFF,
++ },
++
++ /* gcvPOWER_IDLE */
++ { /* ON */ gcvPOWER_FLAG_NOP,
++ /* OFF */ gcvPOWER_FLAG_ACQUIRE |
++ gcvPOWER_FLAG_STOP |
++ gcvPOWER_FLAG_POWER_OFF |
++ gcvPOWER_FLAG_CLOCK_OFF,
++ /* IDLE */ 0,
++ /* SUSPEND */ gcvPOWER_FLAG_ACQUIRE |
++ gcvPOWER_FLAG_STOP |
++ gcvPOWER_FLAG_CLOCK_OFF,
++ },
++
++ /* gcvPOWER_SUSPEND */
++ { /* ON */ gcvPOWER_FLAG_START |
++ gcvPOWER_FLAG_RELEASE |
++ gcvPOWER_FLAG_DELAY |
++ gcvPOWER_FLAG_CLOCK_ON,
++ /* OFF */ gcvPOWER_FLAG_SAVE |
++ gcvPOWER_FLAG_POWER_OFF |
++ gcvPOWER_FLAG_CLOCK_OFF,
++ /* IDLE */ gcvPOWER_FLAG_START |
++ gcvPOWER_FLAG_DELAY |
++ gcvPOWER_FLAG_RELEASE |
++ gcvPOWER_FLAG_CLOCK_ON,
++ /* SUSPEND */ 0,
++ },
++ };
++
++ gcmkHEADER_ARG("Hardware=0x%x State=%d", Hardware, State);
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Switching to power state %d",
++ State);
++#endif
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Get the gckOS object pointer. */
++ os = Hardware->os;
++ gcmkVERIFY_OBJECT(os, gcvOBJ_OS);
++
++ /* Get the gckCOMMAND object pointer. */
++ gcmkVERIFY_OBJECT(Hardware->kernel, gcvOBJ_KERNEL);
++ command = Hardware->kernel->command;
++ gcmkVERIFY_OBJECT(command, gcvOBJ_COMMAND);
++
++ if (Hardware->powerManagement == gcvFALSE)
++ {
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++
++ /* Start profiler. */
++ gcmkPROFILE_INIT(freq, time);
++
++ /* Convert the broadcast power state. */
++ switch (State)
++ {
++ case gcvPOWER_SUSPEND_ATPOWERON:
++ /* Convert to SUSPEND and don't wait for STALL. */
++ State = gcvPOWER_SUSPEND;
++ stall = gcvFALSE;
++ break;
++
++ case gcvPOWER_OFF_ATPOWERON:
++ /* Convert to OFF and don't wait for STALL. */
++ State = gcvPOWER_OFF;
++ stall = gcvFALSE;
++ break;
++
++ case gcvPOWER_IDLE_BROADCAST:
++ /* Convert to IDLE and note we are inside broadcast. */
++ State = gcvPOWER_IDLE;
++ broadcast = gcvTRUE;
++ break;
++
++ case gcvPOWER_SUSPEND_BROADCAST:
++ /* Convert to SUSPEND and note we are inside broadcast. */
++ State = gcvPOWER_SUSPEND;
++ broadcast = gcvTRUE;
++ break;
++
++ case gcvPOWER_OFF_BROADCAST:
++ /* Convert to OFF and note we are inside broadcast. */
++ State = gcvPOWER_OFF;
++ broadcast = gcvTRUE;
++ break;
++
++ case gcvPOWER_OFF_RECOVERY:
++ /* Convert to OFF and note we are inside recovery. */
++ State = gcvPOWER_OFF;
++ stall = gcvFALSE;
++ broadcast = gcvTRUE;
++ break;
++
++ case gcvPOWER_ON_AUTO:
++ /* Convert to ON and note we are inside recovery. */
++ State = gcvPOWER_ON;
++ break;
++
++ case gcvPOWER_ON:
++ case gcvPOWER_IDLE:
++ case gcvPOWER_SUSPEND:
++ case gcvPOWER_OFF:
++ /* Mark as global power management. */
++ global = gcvTRUE;
++ break;
++
++#if gcdPOWEROFF_TIMEOUT
++ case gcvPOWER_OFF_TIMEOUT:
++ /* Convert to OFF and note we are inside broadcast. */
++ State = gcvPOWER_OFF;
++ broadcast = gcvTRUE;
++ /* Check time out */
++ timeout = gcvTRUE;
++ break;
++#endif
++
++ default:
++ break;
++ }
++
++ /* Get current process and thread IDs. */
++ gcmkONERROR(gckOS_GetProcessID(&process));
++ gcmkONERROR(gckOS_GetThreadID(&thread));
++
++ /* Acquire the power mutex. */
++ if (broadcast)
++ {
++ /* Try to acquire the power mutex. */
++ status = gckOS_AcquireMutex(os, Hardware->powerMutex, 0);
++
++ if (status == gcvSTATUS_TIMEOUT)
++ {
++ /* Check if we already own this mutex. */
++ if ((Hardware->powerProcess == process)
++ && (Hardware->powerThread == thread)
++ )
++ {
++ /* Bail out on recursive power management. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++ else if (State == gcvPOWER_IDLE)
++ {
++ /* gcvPOWER_IDLE_BROADCAST is from IST,
++ ** so waiting here will cause deadlock,
++ ** if lock holder call gckCOMMAND_Stall() */
++ gcmkONERROR(gcvSTATUS_INVALID_REQUEST);
++ }
++ else
++ {
++ /* Acquire the power mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(os,
++ Hardware->powerMutex,
++ gcvINFINITE));
++ }
++ }
++ }
++ else
++ {
++ /* Acquire the power mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(os, Hardware->powerMutex, gcvINFINITE));
++ }
++
++ /* Get time until mtuex acquired. */
++ gcmkPROFILE_QUERY(time, mutexTime);
++
++ Hardware->powerProcess = process;
++ Hardware->powerThread = thread;
++ mutexAcquired = gcvTRUE;
++
++ /* Grab control flags and clock. */
++ flag = flags[Hardware->chipPowerState][State];
++ /*clock = clocks[State];*/
++
++#if gcdPOWEROFF_TIMEOUT
++ if (timeout)
++ {
++ gcmkONERROR(gckOS_GetTicks(&currentTime));
++
++ gcmkONERROR(
++ gckOS_TicksAfter(Hardware->powerOffTime, currentTime, &isAfter));
++
++ /* powerOffTime is pushed forward, give up.*/
++ if (isAfter
++ /* Expect a transition start from IDLE. */
++ || (Hardware->chipPowerState == gcvPOWER_ON)
++ || (Hardware->chipPowerState == gcvPOWER_OFF)
++ )
++ {
++ /* Release the power mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(os, Hardware->powerMutex));
++
++ /* No need to do anything. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++ }
++#endif
++
++ if (flag == 0)
++ {
++ /* Release the power mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(os, Hardware->powerMutex));
++
++ /* No need to do anything. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++
++ /* internal power control */
++ if (!global)
++ {
++ if (Hardware->chipPowerStateGlobal == gcvPOWER_OFF)
++ {
++ /* Release the power mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(os, Hardware->powerMutex));
++
++ /* No need to do anything. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++ }
++ else
++ {
++ if (flag & gcvPOWER_FLAG_ACQUIRE)
++ {
++ /* Acquire the power management semaphore. */
++ gcmkONERROR(gckOS_AcquireSemaphore(os, command->powerSemaphore));
++ acquired = gcvTRUE;
++
++ /* avoid acquiring again. */
++ flag &= ~gcvPOWER_FLAG_ACQUIRE;
++ }
++ }
++
++ if (flag & (gcvPOWER_FLAG_INITIALIZE | gcvPOWER_FLAG_CLOCK_ON))
++ {
++ /* Turn on the power. */
++ gcmkONERROR(gckOS_SetGPUPower(os, gcvCORE_VG, gcvTRUE, gcvTRUE));
++
++ /* Mark clock and power as enabled. */
++ Hardware->clockState = gcvTRUE;
++ Hardware->powerState = gcvTRUE;
++ }
++
++ /* Get time until powered on. */
++ gcmkPROFILE_QUERY(time, onTime);
++
++ if ((flag & gcvPOWER_FLAG_STALL) && stall)
++ {
++ /* Acquire the mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(
++ command->os,
++ command->commitMutex,
++ gcvINFINITE
++ ));
++
++ commitMutex = gcvTRUE;
++
++ gcmkONERROR(_CommandStall(Hardware));
++ }
++
++ /* Get time until stalled. */
++ gcmkPROFILE_QUERY(time, stallTime);
++
++ if (flag & gcvPOWER_FLAG_ACQUIRE)
++ {
++ /* Acquire the power management semaphore. */
++ gcmkONERROR(gckOS_AcquireSemaphore(os, command->powerSemaphore));
++
++ acquired = gcvTRUE;
++ }
++
++ if (flag & gcvPOWER_FLAG_STOP)
++ {
++ }
++
++ /* Get time until stopped. */
++ gcmkPROFILE_QUERY(time, stopTime);
++
++ /* Only process this when hardware is enabled. */
++ if (Hardware->clockState && Hardware->powerState)
++ {
++ }
++
++ if (flag & gcvPOWER_FLAG_DELAY)
++ {
++ /* Wait for the specified amount of time to settle coming back from
++ ** power-off or suspend state. */
++ gcmkONERROR(gckOS_Delay(os, gcdPOWER_CONTROL_DELAY));
++ }
++
++ /* Get time until delayed. */
++ gcmkPROFILE_QUERY(time, delayTime);
++
++ if (flag & gcvPOWER_FLAG_INITIALIZE)
++ {
++ gcmkONERROR(gckVGHARDWARE_SetMMU(Hardware, Hardware->kernel->mmu->pageTableLogical));
++
++ /* Force the command queue to reload the next context. */
++ command->currentContext = 0;
++ }
++
++ /* Get time until initialized. */
++ gcmkPROFILE_QUERY(time, initTime);
++
++ if (flag & (gcvPOWER_FLAG_POWER_OFF | gcvPOWER_FLAG_CLOCK_OFF))
++ {
++ /* Turn off the GPU power. */
++ gcmkONERROR(
++ gckOS_SetGPUPower(os,
++ gcvCORE_VG,
++ (flag & gcvPOWER_FLAG_CLOCK_OFF) ? gcvFALSE
++ : gcvTRUE,
++ (flag & gcvPOWER_FLAG_POWER_OFF) ? gcvFALSE
++ : gcvTRUE));
++
++ /* Save current hardware power and clock states. */
++ Hardware->clockState = (flag & gcvPOWER_FLAG_CLOCK_OFF) ? gcvFALSE
++ : gcvTRUE;
++ Hardware->powerState = (flag & gcvPOWER_FLAG_POWER_OFF) ? gcvFALSE
++ : gcvTRUE;
++ }
++
++ /* Get time until off. */
++ gcmkPROFILE_QUERY(time, offTime);
++
++ if (flag & gcvPOWER_FLAG_START)
++ {
++ }
++
++ /* Get time until started. */
++ gcmkPROFILE_QUERY(time, startTime);
++
++ if (flag & gcvPOWER_FLAG_RELEASE)
++ {
++ /* Release the power management semaphore. */
++ gcmkONERROR(gckOS_ReleaseSemaphore(os, command->powerSemaphore));
++ acquired = gcvFALSE;
++ }
++
++ /* Save the new power state. */
++ Hardware->chipPowerState = State;
++
++ if (global)
++ {
++ /* Save the new power state. */
++ Hardware->chipPowerStateGlobal = State;
++ }
++
++ if (commitMutex)
++ {
++ /* Acquire the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(
++ command->os,
++ command->commitMutex
++ ));
++ }
++
++#if gcdPOWEROFF_TIMEOUT
++ /* Reset power off time */
++ gcmkONERROR(gckOS_GetTicks(&currentTime));
++
++ Hardware->powerOffTime = currentTime + Hardware->powerOffTimeout;
++
++ if (State == gcvPOWER_IDLE)
++ {
++ /* Start a timer to power off GPU when GPU enters IDLE or SUSPEND. */
++ gcmkVERIFY_OK(gckOS_StartTimer(os,
++ Hardware->powerOffTimer,
++ Hardware->powerOffTimeout));
++ }
++ else
++ {
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, "Cancel powerOfftimer");
++
++ /* Cancel running timer when GPU enters ON or OFF. */
++ gcmkVERIFY_OK(gckOS_StopTimer(os, Hardware->powerOffTimer));
++ }
++#endif
++
++ /* Release the power mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(os, Hardware->powerMutex));
++
++ /* Get total time. */
++ gcmkPROFILE_QUERY(time, totalTime);
++#if gcdENABLE_PROFILING
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "PROF(%llu): mutex:%llu on:%llu stall:%llu stop:%llu",
++ freq, mutexTime, onTime, stallTime, stopTime);
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ " delay:%llu init:%llu off:%llu start:%llu total:%llu",
++ delayTime, initTime, offTime, startTime, totalTime);
++#endif
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++
++ if (acquired)
++ {
++ /* Release semaphore. */
++ gcmkVERIFY_OK(gckOS_ReleaseSemaphore(Hardware->os,
++ command->powerSemaphore));
++ }
++
++ if (mutexAcquired)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Hardware->os, Hardware->powerMutex));
++ }
++
++ if (commitMutex)
++ {
++ /* Acquire the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(
++ command->os,
++ command->commitMutex
++ ));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_QueryPowerManagementState
++**
++** Get GPU power state.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** gceCHIPPOWERSTATE* State
++** Power State.
++**
++*/
++gceSTATUS
++gckVGHARDWARE_QueryPowerManagementState(
++ IN gckVGHARDWARE Hardware,
++ OUT gceCHIPPOWERSTATE* State
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(State != gcvNULL);
++
++ /* Return the statue. */
++ *State = Hardware->chipPowerState;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*State=%d", *State);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_SetPowerManagement
++**
++** Configure GPU power management function.
++** Only used in driver initialization stage.
++**
++** INPUT:
++**
++** gckVGHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** gctBOOL PowerManagement
++** Power Mangement State.
++**
++*/
++gceSTATUS
++gckVGHARDWARE_SetPowerManagement(
++ IN gckVGHARDWARE Hardware,
++ IN gctBOOL PowerManagement
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ Hardware->powerManagement = PowerManagement;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckVGHARDWARE_SetPowerOffTimeout(
++ IN gckVGHARDWARE Hardware,
++ IN gctUINT32 Timeout
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x Timeout=%d", Hardware, Timeout);
++
++#if gcdPOWEROFF_TIMEOUT
++ Hardware->powerOffTimeout = Timeout;
++#endif
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++
++gceSTATUS
++gckVGHARDWARE_QueryPowerOffTimeout(
++ IN gckVGHARDWARE Hardware,
++ OUT gctUINT32* Timeout
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++#if gcdPOWEROFF_TIMEOUT
++ *Timeout = Hardware->powerOffTimeout;
++#endif
++
++ gcmkFOOTER_ARG("*Timeout=%d", *Timeout);
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckVGHARDWARE_QueryIdle(
++ IN gckVGHARDWARE Hardware,
++ OUT gctBOOL_PTR IsIdle
++ )
++{
++ gceSTATUS status;
++ gctUINT32 idle;
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(IsIdle != gcvNULL);
++
++ /* We are idle when the power is not ON. */
++ if (Hardware->chipPowerState != gcvPOWER_ON)
++ {
++ *IsIdle = gcvTRUE;
++ }
++
++ else
++ {
++ /* Read idle register. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os, gcvCORE_VG, 0x00004, &idle));
++
++ /* Pipe must be idle. */
++ if (((((((gctUINT32) (idle)) >> (0 ? 0:0)) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1)))))) ) != 1)
++ || ((((((gctUINT32) (idle)) >> (0 ? 8:8)) & ((gctUINT32) ((((1 ? 8:8) - (0 ? 8:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:8) - (0 ? 8:8) + 1)))))) ) != 1)
++ || ((((((gctUINT32) (idle)) >> (0 ? 9:9)) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1)))))) ) != 1)
++ || ((((((gctUINT32) (idle)) >> (0 ? 10:10)) & ((gctUINT32) ((((1 ? 10:10) - (0 ? 10:10) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 10:10) - (0 ? 10:10) + 1)))))) ) != 1)
++ || ((((((gctUINT32) (idle)) >> (0 ? 11:11)) & ((gctUINT32) ((((1 ? 11:11) - (0 ? 11:11) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:11) - (0 ? 11:11) + 1)))))) ) != 1)
++ )
++ {
++ /* Something is busy. */
++ *IsIdle = gcvFALSE;
++ }
++
++ else
++ {
++ *IsIdle = gcvTRUE;
++ }
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++#endif /* gcdENABLE_VG */
++
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/arch/GC350/hal/kernel/gc_hal_kernel_hardware_vg.h linux-xbian-imx6/drivers/mxc/gpu-viv/arch/GC350/hal/kernel/gc_hal_kernel_hardware_vg.h
+--- linux-4.1.3/drivers/mxc/gpu-viv/arch/GC350/hal/kernel/gc_hal_kernel_hardware_vg.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/arch/GC350/hal/kernel/gc_hal_kernel_hardware_vg.h 2015-07-27 23:13:06.166979215 +0200
+@@ -0,0 +1,75 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_kernel_hardware_vg_h_
++#define __gc_hal_kernel_hardware_vg_h_
++
++/* gckHARDWARE object. */
++struct _gckVGHARDWARE
++{
++ /* Object. */
++ gcsOBJECT object;
++
++ /* Pointer to gckKERNEL object. */
++ gckVGKERNEL kernel;
++
++ /* Pointer to gckOS object. */
++ gckOS os;
++
++ /* Chip characteristics. */
++ gceCHIPMODEL chipModel;
++ gctUINT32 chipRevision;
++ gctUINT32 chipFeatures;
++ gctUINT32 chipMinorFeatures;
++ gctUINT32 chipMinorFeatures2;
++ gctBOOL allowFastClear;
++
++ /* Features. */
++ gctBOOL fe20;
++ gctBOOL vg20;
++ gctBOOL vg21;
++
++ /* Event mask. */
++ gctUINT32 eventMask;
++
++ gctBOOL clockState;
++ gctBOOL powerState;
++ gctPOINTER powerMutex;
++ gctUINT32 powerProcess;
++ gctUINT32 powerThread;
++ gceCHIPPOWERSTATE chipPowerState;
++ gceCHIPPOWERSTATE chipPowerStateGlobal;
++ gctISRMANAGERFUNC startIsr;
++ gctISRMANAGERFUNC stopIsr;
++ gctPOINTER isrContext;
++ gctPOINTER pageTableDirty;
++
++#if gcdPOWEROFF_TIMEOUT
++ gctUINT32 powerOffTime;
++ gctUINT32 powerOffTimeout;
++ gctPOINTER powerOffTimer;
++#endif
++
++ gctBOOL powerManagement;
++};
++
++#endif /* __gc_hal_kernel_hardware_h_ */
++
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/arch/XAQ2/hal/kernel/gc_hal_kernel_context.c linux-xbian-imx6/drivers/mxc/gpu-viv/arch/XAQ2/hal/kernel/gc_hal_kernel_context.c
+--- linux-4.1.3/drivers/mxc/gpu-viv/arch/XAQ2/hal/kernel/gc_hal_kernel_context.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/arch/XAQ2/hal/kernel/gc_hal_kernel_context.c 2015-07-27 23:13:06.170964992 +0200
+@@ -0,0 +1,1735 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal.h"
++#include "gc_hal_kernel.h"
++#include "gc_hal_kernel_context.h"
++#include "gc_hal_kernel_buffer.h"
++
++/******************************************************************************\
++******************************** Debugging Macro *******************************
++\******************************************************************************/
++
++/* Zone used for header/footer. */
++#define _GC_OBJ_ZONE gcvZONE_HARDWARE
++
++
++/******************************************************************************\
++************************** Context State Buffer Helpers ************************
++\******************************************************************************/
++
++#define _STATE(reg) \
++ _State(\
++ Context, index, \
++ reg ## _Address >> 2, \
++ reg ## _ResetValue, \
++ reg ## _Count, \
++ gcvFALSE, gcvFALSE \
++ )
++
++#define _STATE_COUNT(reg, count) \
++ _State(\
++ Context, index, \
++ reg ## _Address >> 2, \
++ reg ## _ResetValue, \
++ count, \
++ gcvFALSE, gcvFALSE \
++ )
++
++#define _STATE_COUNT_OFFSET(reg, offset, count) \
++ _State(\
++ Context, index, \
++ (reg ## _Address >> 2) + offset, \
++ reg ## _ResetValue, \
++ count, \
++ gcvFALSE, gcvFALSE \
++ )
++
++#define _STATE_MIRROR_COUNT(reg, mirror, count) \
++ _StateMirror(\
++ Context, \
++ reg ## _Address >> 2, \
++ count, \
++ mirror ## _Address >> 2 \
++ )
++
++#define _STATE_HINT(reg) \
++ _State(\
++ Context, index, \
++ reg ## _Address >> 2, \
++ reg ## _ResetValue, \
++ reg ## _Count, \
++ gcvFALSE, gcvTRUE \
++ )
++
++#define _STATE_HINT_BLOCK(reg, block, count) \
++ _State(\
++ Context, index, \
++ (reg ## _Address >> 2) + (block << reg ## _BLK), \
++ reg ## _ResetValue, \
++ count, \
++ gcvFALSE, gcvTRUE \
++ )
++
++#define _STATE_X(reg) \
++ _State(\
++ Context, index, \
++ reg ## _Address >> 2, \
++ reg ## _ResetValue, \
++ reg ## _Count, \
++ gcvTRUE, gcvFALSE \
++ )
++
++#define _CLOSE_RANGE() \
++ _TerminateStateBlock(Context, index)
++
++#define _ENABLE(reg, field) \
++ do \
++ { \
++ if (gcmVERIFYFIELDVALUE(data, reg, MASK_ ## field, ENABLED)) \
++ { \
++ enable |= gcmFIELDMASK(reg, field); \
++ } \
++ } \
++ while (gcvFALSE)
++
++#define _BLOCK_COUNT(reg) \
++ ((reg ## _Count) >> (reg ## _BLK))
++
++
++/******************************************************************************\
++*********************** Support Functions and Definitions **********************
++\******************************************************************************/
++
++#define gcdSTATE_MASK \
++ (((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x03 | 0xC0FFEE & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))))
++
++#if !defined(VIVANTE_NO_3D)
++static gctSIZE_T
++_TerminateStateBlock(
++ IN gckCONTEXT Context,
++ IN gctSIZE_T Index
++ )
++{
++ gctUINT32_PTR buffer;
++ gctSIZE_T align;
++
++ /* Determine if we need alignment. */
++ align = (Index & 1) ? 1 : 0;
++
++ /* Address correct index. */
++ buffer = (Context->buffer == gcvNULL)
++ ? gcvNULL
++ : Context->buffer->logical;
++
++ /* Flush the current state block; make sure no pairing with the states
++ to follow happens. */
++ if (align && (buffer != gcvNULL))
++ {
++ buffer[Index] = 0xDEADDEAD;
++ }
++
++ /* Reset last address. */
++ Context->lastAddress = ~0U;
++
++ /* Return alignment requirement. */
++ return align;
++}
++#endif
++
++
++static gctSIZE_T
++_FlushPipe(
++ IN gckCONTEXT Context,
++ IN gctSIZE_T Index,
++ IN gcePIPE_SELECT Pipe
++ )
++{
++ if (Context->buffer != gcvNULL)
++ {
++ gctUINT32_PTR buffer;
++
++ /* Address correct index. */
++ buffer = Context->buffer->logical + Index;
++
++ /* Flush the current pipe. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E03) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ *buffer++
++ = (Pipe == gcvPIPE_2D)
++ ? ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3)))
++ : ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4)));
++
++ /* Semaphore from FE to PE. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /* Stall from FE to PE. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++
++ *buffer
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++ }
++
++ /* Flushing 3D pipe takes 6 slots. */
++ return 6;
++}
++
++#if !defined(VIVANTE_NO_3D)
++static gctSIZE_T
++_SemaphoreStall(
++ IN gckCONTEXT Context,
++ IN gctSIZE_T Index
++ )
++{
++ if (Context->buffer != gcvNULL)
++ {
++ gctUINT32_PTR buffer;
++
++ /* Address correct index. */
++ buffer = Context->buffer->logical + Index;
++
++ /* Semaphore from FE to PE. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /* Stall from FE to PE. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++
++ *buffer
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++ }
++
++ /* Semaphore/stall takes 4 slots. */
++ return 4;
++}
++#endif
++
++static gctSIZE_T
++_SwitchPipe(
++ IN gckCONTEXT Context,
++ IN gctSIZE_T Index,
++ IN gcePIPE_SELECT Pipe
++ )
++{
++ if (Context->buffer != gcvNULL)
++ {
++ gctUINT32_PTR buffer;
++
++ /* Address correct index. */
++ buffer = Context->buffer->logical + Index;
++
++ /* LoadState(AQPipeSelect, 1), pipe. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E00) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ *buffer
++ = (Pipe == gcvPIPE_2D)
++ ? 0x1
++ : 0x0;
++ }
++
++ return 2;
++}
++
++#if !defined(VIVANTE_NO_3D)
++static gctSIZE_T
++_State(
++ IN gckCONTEXT Context,
++ IN gctSIZE_T Index,
++ IN gctUINT32 Address,
++ IN gctUINT32 Value,
++ IN gctSIZE_T Size,
++ IN gctBOOL FixedPoint,
++ IN gctBOOL Hinted
++ )
++{
++ gctUINT32_PTR buffer;
++ gctSIZE_T align, i;
++
++ /* Determine if we need alignment. */
++ align = (Index & 1) ? 1 : 0;
++
++ /* Address correct index. */
++ buffer = (Context->buffer == gcvNULL)
++ ? gcvNULL
++ : Context->buffer->logical;
++
++ if ((buffer == gcvNULL) && (Address + Size > Context->stateCount))
++ {
++ /* Determine maximum state. */
++ Context->stateCount = Address + Size;
++ }
++
++ /* Do we need a new entry? */
++ if ((Address != Context->lastAddress) || (FixedPoint != Context->lastFixed))
++ {
++ if (buffer != gcvNULL)
++ {
++ if (align)
++ {
++ /* Add filler. */
++ buffer[Index++] = 0xDEADDEAD;
++ }
++
++ /* LoadState(Address, Count). */
++ gcmkASSERT((Index & 1) == 0);
++
++ if (FixedPoint)
++ {
++ buffer[Index]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 26:26) - (0 ? 26:26) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 26:26) - (0 ? 26:26) + 1))))))) << (0 ? 26:26))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 26:26) - (0 ? 26:26) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 26:26) - (0 ? 26:26) + 1))))))) << (0 ? 26:26)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (Size) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (Address) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++ }
++ else
++ {
++ buffer[Index]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 26:26) - (0 ? 26:26) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 26:26) - (0 ? 26:26) + 1))))))) << (0 ? 26:26))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 26:26) - (0 ? 26:26) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 26:26) - (0 ? 26:26) + 1))))))) << (0 ? 26:26)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (Size) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (Address) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++ }
++
++ /* Walk all the states. */
++ for (i = 0; i < Size; i += 1)
++ {
++ /* Set state to uninitialized value. */
++ buffer[Index + 1 + i] = Value;
++
++ /* Set index in state mapping table. */
++ Context->map[Address + i].index = Index + 1 + i;
++
++#if gcdSECURE_USER
++ /* Save hint. */
++ if (Context->hint != gcvNULL)
++ {
++ Context->hint[Address + i] = Hinted;
++ }
++#endif
++ }
++ }
++
++ /* Save information for this LoadState. */
++ Context->lastIndex = Index;
++ Context->lastAddress = Address + Size;
++ Context->lastSize = Size;
++ Context->lastFixed = FixedPoint;
++
++ /* Return size for load state. */
++ return align + 1 + Size;
++ }
++
++ /* Append this state to the previous one. */
++ if (buffer != gcvNULL)
++ {
++ /* Update last load state. */
++ buffer[Context->lastIndex] =
++ ((((gctUINT32) (buffer[Context->lastIndex])) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (Context->lastSize + Size) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ /* Walk all the states. */
++ for (i = 0; i < Size; i += 1)
++ {
++ /* Set state to uninitialized value. */
++ buffer[Index + i] = Value;
++
++ /* Set index in state mapping table. */
++ Context->map[Address + i].index = Index + i;
++
++#if gcdSECURE_USER
++ /* Save hint. */
++ if (Context->hint != gcvNULL)
++ {
++ Context->hint[Address + i] = Hinted;
++ }
++#endif
++ }
++ }
++
++ /* Update last address and size. */
++ Context->lastAddress += Size;
++ Context->lastSize += Size;
++
++ /* Return number of slots required. */
++ return Size;
++}
++
++static gctSIZE_T
++_StateMirror(
++ IN gckCONTEXT Context,
++ IN gctUINT32 Address,
++ IN gctSIZE_T Size,
++ IN gctUINT32 AddressMirror
++ )
++{
++ gctSIZE_T i;
++
++ /* Process when buffer is set. */
++ if (Context->buffer != gcvNULL)
++ {
++ /* Walk all states. */
++ for (i = 0; i < Size; i++)
++ {
++ /* Copy the mapping address. */
++ Context->map[Address + i].index =
++ Context->map[AddressMirror + i].index;
++ }
++ }
++
++ /* Return the number of required maps. */
++ return Size;
++}
++#endif
++
++static gceSTATUS
++_InitializeContextBuffer(
++ IN gckCONTEXT Context
++ )
++{
++ gctUINT32_PTR buffer;
++ gctSIZE_T index;
++
++#if !defined(VIVANTE_NO_3D)
++ gctUINT i;
++ gctUINT vertexUniforms, fragmentUniforms;
++ gctUINT fe2vsCount;
++ gctBOOL halti0;
++#endif
++
++ /* Reset the buffer index. */
++ index = 0;
++
++ /* Reset the last state address. */
++ Context->lastAddress = ~0U;
++
++ /* Get the buffer pointer. */
++ buffer = (Context->buffer == gcvNULL)
++ ? gcvNULL
++ : Context->buffer->logical;
++
++
++ /**************************************************************************/
++ /* Build 2D states. *******************************************************/
++
++
++#if !defined(VIVANTE_NO_3D)
++ /**************************************************************************/
++ /* Build 3D states. *******************************************************/
++ halti0 = (((((gctUINT32) (Context->hardware->identity.chipMinorFeatures1)) >> (0 ? 23:23)) & ((gctUINT32) ((((1 ? 23:23) - (0 ? 23:23) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:23) - (0 ? 23:23) + 1)))))) );
++
++ /* Query shader support. */
++ gcmkVERIFY_OK(gckHARDWARE_QueryShaderCaps(
++ Context->hardware, &vertexUniforms, &fragmentUniforms, gcvNULL));
++
++ /* Store the 3D entry index. */
++ Context->entryOffset3D = index * gcmSIZEOF(gctUINT32);
++
++ /* Flush 2D pipe. */
++ index += _FlushPipe(Context, index, gcvPIPE_2D);
++
++ /* Switch to 3D pipe. */
++ index += _SwitchPipe(Context, index, gcvPIPE_3D);
++
++ /* Current context pointer. */
++#if gcdDEBUG
++ index += _State(Context, index, 0x03850 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++#endif
++
++ index += _FlushPipe(Context, index, gcvPIPE_3D);
++
++ /* Global states. */
++ index += _State(Context, index, 0x03814 >> 2, 0x00000001, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x03818 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0381C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x03820 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x03828 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0382C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x03834 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x03838 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0384C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++
++ /* Front End states. */
++ fe2vsCount = 12;
++ if ((((((gctUINT32) (Context->hardware->identity.chipMinorFeatures1)) >> (0 ? 23:23)) & ((gctUINT32) ((((1 ? 23:23) - (0 ? 23:23) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:23) - (0 ? 23:23) + 1)))))) ))
++ {
++ fe2vsCount = 16;
++ }
++ index += _State(Context, index, 0x00600 >> 2, 0x00000000, fe2vsCount, gcvFALSE, gcvFALSE);
++ index += _CLOSE_RANGE();
++
++ index += _State(Context, index, 0x00644 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x00648 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0064C >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x00650 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00680 >> 2, 0x00000000, 8, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x006A0 >> 2, 0x00000000, 8, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00670 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00678 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0067C >> 2, 0xFFFFFFFF, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x006C0 >> 2, 0x00000000, 16, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00700 >> 2, 0x00000000, 16, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00740 >> 2, 0x00000000, 16, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00780 >> 2, 0x3F800000, 16, gcvFALSE, gcvFALSE);
++
++ /* Vertex Shader states. */
++ index += _State(Context, index, 0x00800 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00804 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00808 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0080C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00810 >> 2, 0x00000000, 4, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00820 >> 2, 0x00000000, 4, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00830 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00838 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ if (Context->hardware->identity.instructionCount <= 256)
++ {
++ index += _State(Context, index, 0x04000 >> 2, 0x00000000, 1024, gcvFALSE, gcvFALSE);
++ }
++
++ index += _CLOSE_RANGE();
++ index += _State(Context, index, 0x05000 >> 2, 0x00000000, vertexUniforms * 4, gcvFALSE, gcvFALSE);
++
++ /* Primitive Assembly states. */
++ index += _State(Context, index, 0x00A00 >> 2, 0x00000000, 1, gcvTRUE, gcvFALSE);
++ index += _State(Context, index, 0x00A04 >> 2, 0x00000000, 1, gcvTRUE, gcvFALSE);
++ index += _State(Context, index, 0x00A08 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00A0C >> 2, 0x00000000, 1, gcvTRUE, gcvFALSE);
++ index += _State(Context, index, 0x00A10 >> 2, 0x00000000, 1, gcvTRUE, gcvFALSE);
++ index += _State(Context, index, 0x00A14 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00A18 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00A1C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00A28 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00A2C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00A30 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00A40 >> 2, 0x00000000, 10, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00A34 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00A38 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00A3C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00A80 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00A84 >> 2, 0x00000000, 1, gcvTRUE, gcvFALSE);
++ index += _State(Context, index, 0x00A8C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++
++ /* Setup states. */
++ index += _State(Context, index, 0x00C00 >> 2, 0x00000000, 1, gcvTRUE, gcvFALSE);
++ index += _State(Context, index, 0x00C04 >> 2, 0x00000000, 1, gcvTRUE, gcvFALSE);
++ index += _State(Context, index, 0x00C08 >> 2, 0x45000000, 1, gcvTRUE, gcvFALSE);
++ index += _State(Context, index, 0x00C0C >> 2, 0x45000000, 1, gcvTRUE, gcvFALSE);
++ index += _State(Context, index, 0x00C10 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00C14 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00C18 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00C1C >> 2, 0x42000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00C20 >> 2, 0x00000000, 1, gcvTRUE, gcvFALSE);
++ index += _State(Context, index, 0x00C24 >> 2, 0x00000000, 1, gcvTRUE, gcvFALSE);
++
++ /* Raster states. */
++ index += _State(Context, index, 0x00E00 >> 2, 0x00000001, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00E10 >> 2, 0x00000000, 4, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00E04 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00E40 >> 2, 0x00000000, 16, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00E08 >> 2, 0x00000031, 1, gcvFALSE, gcvFALSE);
++
++ /* Pixel Shader states. */
++ index += _State(Context, index, 0x01000 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01004 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01008 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0100C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01010 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01018 >> 2, 0x01000000, 1, gcvFALSE, gcvFALSE);
++ if (Context->hardware->identity.instructionCount <= 256)
++ {
++ index += _State(Context, index, 0x06000 >> 2, 0x00000000, 1024, gcvFALSE, gcvFALSE);
++ }
++
++ index += _CLOSE_RANGE();
++ index += _State(Context, index, 0x07000 >> 2, 0x00000000, fragmentUniforms * 4, gcvFALSE, gcvFALSE);
++
++ /* Texture states. */
++ index += _State(Context, index, 0x02000 >> 2, 0x00000000, 12, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x02040 >> 2, 0x00000000, 12, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x02080 >> 2, 0x00000000, 12, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x020C0 >> 2, 0x00000000, 12, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x02100 >> 2, 0x00000000, 12, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x02140 >> 2, 0x00000000, 12, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x02180 >> 2, 0x00000000, 12, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x021C0 >> 2, 0x00321000, 12, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x02200 >> 2, 0x00000000, 12, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x02240 >> 2, 0x00000000, 12, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, (0x02400 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x02440 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x02480 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x024C0 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x02500 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x02540 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x02580 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x025C0 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x02600 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x02640 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x02680 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x026C0 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x02700 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x02740 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _CLOSE_RANGE();
++
++ if ((((((gctUINT32) (Context->hardware->identity.chipMinorFeatures2)) >> (0 ? 11:11)) & ((gctUINT32) ((((1 ? 11:11) - (0 ? 11:11) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:11) - (0 ? 11:11) + 1)))))) ))
++ {
++ gctUINT texBlockCount;
++
++ /* New texture block. */
++ index += _State(Context, index, 0x10000 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x10080 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x10100 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x10180 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x10200 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x10280 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE);
++ for (i = 0; i < 256 / 16; i += 1)
++ {
++ index += _State(Context, index, (0x02C00 >> 2) + i * 16, 0x00000000, 14, gcvFALSE, gcvFALSE);
++ }
++ index += _State(Context, index, 0x10300 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x10380 >> 2, 0x00321000, 32, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x10400 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x10480 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE);
++
++ if ((((((gctUINT32) (Context->hardware->identity.chipMinorFeatures2)) >> (0 ? 15:15)) & ((gctUINT32) ((((1 ? 15:15) - (0 ? 15:15) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:15) - (0 ? 15:15) + 1)))))) ))
++ {
++ index += _State(Context, index, 0x12000 >> 2, 0x00000000, 256, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x12400 >> 2, 0x00000000, 256, gcvFALSE, gcvFALSE);
++ }
++
++ if ((Context->hardware->identity.chipModel == gcv2000)
++ && (Context->hardware->identity.chipRevision == 0x5108))
++ {
++ texBlockCount = 12;
++ }
++ else
++ {
++ texBlockCount = ((512) >> (4));
++ }
++ for (i = 0; i < texBlockCount; i += 1)
++ {
++ index += _State(Context, index, (0x10800 >> 2) + (i << 4), 0x00000000, 14, gcvFALSE, gcvTRUE);
++ }
++ }
++
++ /* YUV. */
++ index += _State(Context, index, 0x01678 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0167C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01680 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x01684 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01688 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x0168C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01690 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x01694 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01698 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x0169C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _CLOSE_RANGE();
++
++ /* Thread walker states. */
++ index += _State(Context, index, 0x00900 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00904 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00908 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0090C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00910 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00914 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00918 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0091C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00924 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _CLOSE_RANGE();
++
++ if (Context->hardware->identity.instructionCount > 1024)
++ {
++ /* New Shader instruction memory. */
++ index += _State(Context, index, 0x0085C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0101C >> 2, 0x00000100, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00860 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _CLOSE_RANGE();
++
++ for (i = 0;
++ i < Context->hardware->identity.instructionCount << 2;
++ i += 256 << 2
++ )
++ {
++ index += _State(Context, index, (0x20000 >> 2) + i, 0x00000000, 256 << 2, gcvFALSE, gcvFALSE);
++ index += _CLOSE_RANGE();
++ }
++ }
++ else if (Context->hardware->identity.instructionCount > 256)
++ {
++ /* New Shader instruction memory. */
++ index += _State(Context, index, 0x0085C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0101C >> 2, 0x00000100, 1, gcvFALSE, gcvFALSE);
++ index += _CLOSE_RANGE();
++
++ /* VX instruction memory. */
++ for (i = 0;
++ i < Context->hardware->identity.instructionCount << 2;
++ i += 256 << 2
++ )
++ {
++ index += _State(Context, index, (0x0C000 >> 2) + i, 0x00000000, 256 << 2, gcvFALSE, gcvFALSE);
++ index += _CLOSE_RANGE();
++ }
++
++ _StateMirror(Context, 0x08000 >> 2, Context->hardware->identity.instructionCount << 2 , 0x0C000 >> 2);
++ }
++
++ /* Store the index of the "XD" entry. */
++ Context->entryOffsetXDFrom3D = index * gcmSIZEOF(gctUINT32);
++
++
++ /* Pixel Engine states. */
++ index += _State(Context, index, 0x01400 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01404 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01408 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0140C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01414 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01418 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0141C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01420 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01424 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01428 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0142C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01434 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01454 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01458 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x0145C >> 2, 0x00000010, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x014A0 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x014A8 >> 2, 0xFFFFFFFF, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x014AC >> 2, 0xFFFFFFFF, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x014B0 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x014B4 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x014A4 >> 2, 0x000E400C, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01580 >> 2, 0x00000000, 3, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x014B8 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++
++ /* Composition states. */
++ index += _State(Context, index, 0x03008 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++
++ if (Context->hardware->identity.pixelPipes == 1)
++ {
++ index += _State(Context, index, 0x01460 >> 2, 0x00000000, 8, gcvFALSE, gcvTRUE);
++
++ index += _State(Context, index, 0x01430 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x01410 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ }
++ else
++ {
++ index += _State(Context, index, (0x01460 >> 2) + (0 << 3), 0x00000000, Context->hardware->identity.pixelPipes, gcvFALSE, gcvTRUE);
++
++ for (i = 0; i < 2; i++)
++ {
++ index += _State(Context, index, (0x01500 >> 2) + (i << 3), 0x00000000, Context->hardware->identity.pixelPipes, gcvFALSE, gcvTRUE);
++ }
++ }
++
++ if (Context->hardware->identity.pixelPipes > 1 || halti0)
++ {
++ index += _State(Context, index, (0x01480 >> 2) + (0 << 3), 0x00000000, Context->hardware->identity.pixelPipes, gcvFALSE, gcvTRUE);
++ }
++
++ /* Resolve states. */
++ index += _State(Context, index, 0x01604 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01608 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x0160C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01610 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x01614 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01620 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01630 >> 2, 0x00000000, 2, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01640 >> 2, 0x00000000, 4, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0163C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x016A0 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x016B4 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _CLOSE_RANGE();
++
++ if (Context->hardware->identity.pixelPipes > 1)
++ {
++ index += _State(Context, index, (0x016C0 >> 2) + (0 << 3), 0x00000000, Context->hardware->identity.pixelPipes, gcvFALSE, gcvTRUE);
++
++ index += _State(Context, index, (0x016E0 >> 2) + (0 << 3), 0x00000000, Context->hardware->identity.pixelPipes, gcvFALSE, gcvTRUE);
++
++ index += _State(Context, index, 0x01700 >> 2, 0x00000000, Context->hardware->identity.pixelPipes, gcvFALSE, gcvFALSE);
++ }
++
++ /* Tile status. */
++ index += _State(Context, index, 0x01654 >> 2, 0x00200000, 1, gcvFALSE, gcvFALSE);
++
++ index += _CLOSE_RANGE();
++ index += _State(Context, index, 0x01658 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x0165C >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x01660 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01664 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x01668 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x0166C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01670 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01674 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x016A4 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x016AC >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x016A8 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01720 >> 2, 0x00000000, 8, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01740 >> 2, 0x00000000, 8, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x01760 >> 2, 0x00000000, 8, gcvFALSE, gcvFALSE);
++ index += _CLOSE_RANGE();
++
++ /* Semaphore/stall. */
++ index += _SemaphoreStall(Context, index);
++#endif
++
++ /**************************************************************************/
++ /* Link to another address. ***********************************************/
++
++ Context->linkIndex3D = index;
++
++ if (buffer != gcvNULL)
++ {
++ buffer[index + 0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x08 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ buffer[index + 1]
++ = 0;
++ }
++
++ index += 2;
++
++ /* Store the end of the context buffer. */
++ Context->bufferSize = index * gcmSIZEOF(gctUINT32);
++
++
++ /**************************************************************************/
++ /* Pipe switch for the case where neither 2D nor 3D are used. *************/
++
++ /* Store the 3D entry index. */
++ Context->entryOffsetXDFrom2D = index * gcmSIZEOF(gctUINT32);
++
++ /* Flush 2D pipe. */
++ index += _FlushPipe(Context, index, gcvPIPE_2D);
++
++ /* Switch to 3D pipe. */
++ index += _SwitchPipe(Context, index, gcvPIPE_3D);
++
++ /* Store the location of the link. */
++ Context->linkIndexXD = index;
++
++ if (buffer != gcvNULL)
++ {
++ buffer[index + 0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x08 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ buffer[index + 1]
++ = 0;
++ }
++
++ index += 2;
++
++
++ /**************************************************************************/
++ /* Save size for buffer. **************************************************/
++
++ Context->totalSize = index * gcmSIZEOF(gctUINT32);
++
++
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++static gceSTATUS
++_DestroyContext(
++ IN gckCONTEXT Context
++ )
++{
++ gceSTATUS status = gcvSTATUS_OK;
++
++ if (Context != gcvNULL)
++ {
++ gcsCONTEXT_PTR bufferHead;
++
++ /* Free context buffers. */
++ for (bufferHead = Context->buffer; Context->buffer != gcvNULL;)
++ {
++ /* Get a shortcut to the current buffer. */
++ gcsCONTEXT_PTR buffer = Context->buffer;
++
++ /* Get the next buffer. */
++ gcsCONTEXT_PTR next = buffer->next;
++
++ /* Last item? */
++ if (next == bufferHead)
++ {
++ next = gcvNULL;
++ }
++
++ /* Destroy the signal. */
++ if (buffer->signal != gcvNULL)
++ {
++ gcmkONERROR(gckOS_DestroySignal(
++ Context->os, buffer->signal
++ ));
++
++ buffer->signal = gcvNULL;
++ }
++
++ /* Free state delta map. */
++ if (buffer->logical != gcvNULL)
++ {
++#if gcdVIRTUAL_COMMAND_BUFFER
++ gcmkONERROR(gckEVENT_DestroyVirtualCommandBuffer(
++ Context->hardware->kernel->eventObj,
++ Context->totalSize,
++ buffer->physical,
++ buffer->logical,
++ gcvKERNEL_PIXEL
++ ));
++
++#else
++ gcmkONERROR(gckEVENT_FreeContiguousMemory(
++ Context->hardware->kernel->eventObj,
++ Context->totalSize,
++ buffer->physical,
++ buffer->logical,
++ gcvKERNEL_PIXEL
++ ));
++#endif
++
++ buffer->logical = gcvNULL;
++ }
++
++ /* Free context buffer. */
++ gcmkONERROR(gcmkOS_SAFE_FREE(Context->os, buffer));
++
++ /* Remove from the list. */
++ Context->buffer = next;
++ }
++
++#if gcdSECURE_USER
++ /* Free the hint array. */
++ if (Context->hint != gcvNULL)
++ {
++ gcmkONERROR(gcmkOS_SAFE_FREE(Context->os, Context->hint));
++ }
++#endif
++ /* Free record array copy. */
++ if (Context->recordArray != gcvNULL)
++ {
++ gcmkONERROR(gcmkOS_SAFE_FREE(Context->os, Context->recordArray));
++ }
++
++ /* Free the state mapping. */
++ if (Context->map != gcvNULL)
++ {
++ gcmkONERROR(gcmkOS_SAFE_FREE(Context->os, Context->map));
++ }
++
++ /* Mark the gckCONTEXT object as unknown. */
++ Context->object.type = gcvOBJ_UNKNOWN;
++
++ /* Free the gckCONTEXT object. */
++ gcmkONERROR(gcmkOS_SAFE_FREE(Context->os, Context));
++ }
++
++OnError:
++ return status;
++}
++
++
++/******************************************************************************\
++**************************** Context Management API ****************************
++\******************************************************************************/
++
++/******************************************************************************\
++**
++** gckCONTEXT_Construct
++**
++** Construct a new gckCONTEXT object.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to gckOS object.
++**
++** gctUINT32 ProcessID
++** Current process ID.
++**
++** gckHARDWARE Hardware
++** Pointer to gckHARDWARE object.
++**
++** OUTPUT:
++**
++** gckCONTEXT * Context
++** Pointer to a variable thet will receive the gckCONTEXT object
++** pointer.
++*/
++gceSTATUS
++gckCONTEXT_Construct(
++ IN gckOS Os,
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 ProcessID,
++ OUT gckCONTEXT * Context
++ )
++{
++ gceSTATUS status;
++ gckCONTEXT context = gcvNULL;
++ gctSIZE_T allocationSize;
++ gctUINT i;
++ gctPOINTER pointer = gcvNULL;
++
++ gcmkHEADER_ARG("Os=0x%08X Hardware=0x%08X", Os, Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Context != gcvNULL);
++
++
++ /**************************************************************************/
++ /* Allocate and initialize basic fields of gckCONTEXT. ********************/
++
++ /* The context object size. */
++ allocationSize = gcmSIZEOF(struct _gckCONTEXT);
++
++ /* Allocate the object. */
++ gcmkONERROR(gckOS_Allocate(
++ Os, allocationSize, &pointer
++ ));
++
++ context = pointer;
++
++ /* Reset the entire object. */
++ gcmkONERROR(gckOS_ZeroMemory(context, allocationSize));
++
++ /* Initialize the gckCONTEXT object. */
++ context->object.type = gcvOBJ_CONTEXT;
++ context->os = Os;
++ context->hardware = Hardware;
++
++
++#if defined(VIVANTE_NO_3D)
++ context->entryPipe = gcvPIPE_2D;
++ context->exitPipe = gcvPIPE_2D;
++#elif gcdCMD_NO_2D_CONTEXT
++ context->entryPipe = gcvPIPE_3D;
++ context->exitPipe = gcvPIPE_3D;
++#else
++ context->entryPipe
++ = (((((gctUINT32) (context->hardware->identity.chipFeatures)) >> (0 ? 9:9)) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1)))))) )
++ ? gcvPIPE_2D
++ : gcvPIPE_3D;
++ context->exitPipe = gcvPIPE_3D;
++#endif
++
++ /* Get the command buffer requirements. */
++ gcmkONERROR(gckHARDWARE_QueryCommandBuffer(
++ Hardware,
++ &context->alignment,
++ &context->reservedHead,
++ &context->reservedTail
++ ));
++
++ /* Mark the context as dirty to force loading of the entire state table
++ the first time. */
++ context->dirty = gcvTRUE;
++
++
++ /**************************************************************************/
++ /* Get the size of the context buffer. ************************************/
++
++ gcmkONERROR(_InitializeContextBuffer(context));
++
++
++ /**************************************************************************/
++ /* Compute the size of the record array. **********************************/
++
++ context->recordArraySize
++ = gcmSIZEOF(gcsSTATE_DELTA_RECORD) * context->stateCount;
++
++
++ if (context->stateCount > 0)
++ {
++ /**************************************************************************/
++ /* Allocate and reset the state mapping table. ****************************/
++
++ /* Allocate the state mapping table. */
++ gcmkONERROR(gckOS_Allocate(
++ Os,
++ gcmSIZEOF(gcsSTATE_MAP) * context->stateCount,
++ &pointer
++ ));
++
++ context->map = pointer;
++
++ /* Zero the state mapping table. */
++ gcmkONERROR(gckOS_ZeroMemory(
++ context->map, gcmSIZEOF(gcsSTATE_MAP) * context->stateCount
++ ));
++
++
++ /**************************************************************************/
++ /* Allocate the hint array. ***********************************************/
++
++#if gcdSECURE_USER
++ /* Allocate hints. */
++ gcmkONERROR(gckOS_Allocate(
++ Os,
++ gcmSIZEOF(gctBOOL) * context->stateCount,
++ &pointer
++ ));
++
++ context->hint = pointer;
++#endif
++ }
++
++ /**************************************************************************/
++ /* Allocate the context and state delta buffers. **************************/
++
++ for (i = 0; i < gcdCONTEXT_BUFFER_COUNT; i += 1)
++ {
++ /* Allocate a context buffer. */
++ gcsCONTEXT_PTR buffer;
++
++ /* Allocate the context buffer structure. */
++ gcmkONERROR(gckOS_Allocate(
++ Os,
++ gcmSIZEOF(gcsCONTEXT),
++ &pointer
++ ));
++
++ buffer = pointer;
++
++ /* Reset the context buffer structure. */
++ gcmkVERIFY_OK(gckOS_ZeroMemory(
++ buffer, gcmSIZEOF(gcsCONTEXT)
++ ));
++
++ /* Append to the list. */
++ if (context->buffer == gcvNULL)
++ {
++ buffer->next = buffer;
++ context->buffer = buffer;
++ }
++ else
++ {
++ buffer->next = context->buffer->next;
++ context->buffer->next = buffer;
++ }
++
++ /* Set the number of delta in the order of creation. */
++#if gcmIS_DEBUG(gcdDEBUG_CODE)
++ buffer->num = i;
++#endif
++
++ /* Create the busy signal. */
++ gcmkONERROR(gckOS_CreateSignal(
++ Os, gcvFALSE, &buffer->signal
++ ));
++
++ /* Set the signal, buffer is currently not busy. */
++ gcmkONERROR(gckOS_Signal(
++ Os, buffer->signal, gcvTRUE
++ ));
++
++ /* Create a new physical context buffer. */
++#if gcdVIRTUAL_COMMAND_BUFFER
++ gcmkONERROR(gckKERNEL_AllocateVirtualCommandBuffer(
++ context->hardware->kernel,
++ gcvFALSE,
++ &context->totalSize,
++ &buffer->physical,
++ &pointer
++ ));
++
++#else
++ gcmkONERROR(gckOS_AllocateContiguous(
++ Os,
++ gcvFALSE,
++ &context->totalSize,
++ &buffer->physical,
++ &pointer
++ ));
++#endif
++
++ buffer->logical = pointer;
++
++ /* Set gckEVENT object pointer. */
++ buffer->eventObj = Hardware->kernel->eventObj;
++
++ /* Set the pointers to the LINK commands. */
++ if (context->linkIndex2D != 0)
++ {
++ buffer->link2D = &buffer->logical[context->linkIndex2D];
++ }
++
++ if (context->linkIndex3D != 0)
++ {
++ buffer->link3D = &buffer->logical[context->linkIndex3D];
++ }
++
++ if (context->linkIndexXD != 0)
++ {
++ gctPOINTER xdLink;
++ gctUINT8_PTR xdEntryLogical;
++ gctSIZE_T xdEntrySize;
++ gctSIZE_T linkBytes;
++
++ /* Determine LINK parameters. */
++ xdLink
++ = &buffer->logical[context->linkIndexXD];
++
++ xdEntryLogical
++ = (gctUINT8_PTR) buffer->logical
++ + context->entryOffsetXDFrom3D;
++
++ xdEntrySize
++ = context->bufferSize
++ - context->entryOffsetXDFrom3D;
++
++ /* Query LINK size. */
++ gcmkONERROR(gckHARDWARE_Link(
++ Hardware, gcvNULL, gcvNULL, 0, &linkBytes
++ ));
++
++ /* Generate a LINK. */
++ gcmkONERROR(gckHARDWARE_Link(
++ Hardware,
++ xdLink,
++ xdEntryLogical,
++ xdEntrySize,
++ &linkBytes
++ ));
++ }
++ }
++
++
++ /**************************************************************************/
++ /* Initialize the context buffers. ****************************************/
++
++ /* Initialize the current context buffer. */
++ gcmkONERROR(_InitializeContextBuffer(context));
++
++ /* Make all created contexts equal. */
++ {
++ gcsCONTEXT_PTR currContext, tempContext;
++
++ /* Set the current context buffer. */
++ currContext = context->buffer;
++
++ /* Get the next context buffer. */
++ tempContext = currContext->next;
++
++ /* Loop through all buffers. */
++ while (tempContext != currContext)
++ {
++ if (tempContext == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_NOT_FOUND);
++ }
++
++ /* Copy the current context. */
++ gckOS_MemCopy(
++ tempContext->logical,
++ currContext->logical,
++ context->totalSize
++ );
++
++ /* Get the next context buffer. */
++ tempContext = tempContext->next;
++ }
++ }
++
++ /* Return pointer to the gckCONTEXT object. */
++ *Context = context;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Context=0x%08X", *Context);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Roll back on error. */
++ gcmkVERIFY_OK(_DestroyContext(context));
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/******************************************************************************\
++**
++** gckCONTEXT_Destroy
++**
++** Destroy a gckCONTEXT object.
++**
++** INPUT:
++**
++** gckCONTEXT Context
++** Pointer to an gckCONTEXT object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckCONTEXT_Destroy(
++ IN gckCONTEXT Context
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Context=0x%08X", Context);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Context, gcvOBJ_CONTEXT);
++
++ /* Destroy the context and all related objects. */
++ status = _DestroyContext(Context);
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return status;
++}
++
++/******************************************************************************\
++**
++** gckCONTEXT_Update
++**
++** Merge all pending state delta buffers into the current context buffer.
++**
++** INPUT:
++**
++** gckCONTEXT Context
++** Pointer to an gckCONTEXT object.
++**
++** gctUINT32 ProcessID
++** Current process ID.
++**
++** gcsSTATE_DELTA_PTR StateDelta
++** Pointer to the state delta.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckCONTEXT_Update(
++ IN gckCONTEXT Context,
++ IN gctUINT32 ProcessID,
++ IN gcsSTATE_DELTA_PTR StateDelta
++ )
++{
++#ifndef VIVANTE_NO_3D
++ gceSTATUS status = gcvSTATUS_OK;
++ gcsSTATE_DELTA _stateDelta;
++ gckKERNEL kernel;
++ gcsCONTEXT_PTR buffer;
++ gcsSTATE_MAP_PTR map;
++ gctBOOL needCopy = gcvFALSE;
++ gcsSTATE_DELTA_PTR nDelta;
++ gcsSTATE_DELTA_PTR uDelta = gcvNULL;
++ gcsSTATE_DELTA_PTR kDelta = gcvNULL;
++ gcsSTATE_DELTA_RECORD_PTR record;
++ gcsSTATE_DELTA_RECORD_PTR recordArray = gcvNULL;
++ gctUINT elementCount;
++ gctUINT address;
++ gctUINT32 mask;
++ gctUINT32 data;
++ gctUINT index;
++ gctUINT i, j;
++
++#if gcdSECURE_USER
++ gcskSECURE_CACHE_PTR cache;
++#endif
++
++ gcmkHEADER_ARG(
++ "Context=0x%08X ProcessID=%d StateDelta=0x%08X",
++ Context, ProcessID, StateDelta
++ );
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Context, gcvOBJ_CONTEXT);
++
++ /* Get a shortcut to the kernel object. */
++ kernel = Context->hardware->kernel;
++
++ /* Check wehther we need to copy the structures or not. */
++ gcmkONERROR(gckOS_QueryNeedCopy(Context->os, ProcessID, &needCopy));
++
++ /* Allocate the copy buffer for the user record array. */
++ if (needCopy && (Context->recordArray == gcvNULL))
++ {
++ /* Allocate the buffer. */
++ gcmkONERROR(gckOS_Allocate(
++ Context->os,
++ Context->recordArraySize,
++ (gctPOINTER *) &Context->recordArray
++ ));
++ }
++
++ /* Get the current context buffer. */
++ buffer = Context->buffer;
++
++ /* Wait until the context buffer becomes available; this will
++ also reset the signal and mark the buffer as busy. */
++ gcmkONERROR(gckOS_WaitSignal(
++ Context->os, buffer->signal, gcvINFINITE
++ ));
++
++#if gcdSECURE_USER
++ /* Get the cache form the database. */
++ gcmkONERROR(gckKERNEL_GetProcessDBCache(kernel, ProcessID, &cache));
++#endif
++
++#if gcmIS_DEBUG(gcdDEBUG_CODE) && 1 && !defined(VIVANTE_NO_3D)
++ /* Update current context token. */
++ buffer->logical[Context->map[0x0E14].index]
++ = gcmPTR2INT(Context);
++#endif
++
++ /* Are there any pending deltas? */
++ if (buffer->deltaCount != 0)
++ {
++ /* Get the state map. */
++ map = Context->map;
++
++ /* Get the first delta item. */
++ uDelta = buffer->delta;
++
++ /* Reset the vertex stream count. */
++ elementCount = 0;
++
++ /* Merge all pending deltas. */
++ for (i = 0; i < buffer->deltaCount; i += 1)
++ {
++ /* Get access to the state delta. */
++ gcmkONERROR(gckKERNEL_OpenUserData(
++ kernel, needCopy,
++ &_stateDelta,
++ uDelta, gcmSIZEOF(gcsSTATE_DELTA),
++ (gctPOINTER *) &kDelta
++ ));
++
++ /* Get access to the state records. */
++ gcmkONERROR(gckKERNEL_OpenUserData(
++ kernel, needCopy,
++ Context->recordArray,
++ gcmUINT64_TO_PTR(kDelta->recordArray), Context->recordArraySize,
++ (gctPOINTER *) &recordArray
++ ));
++
++ /* Merge all pending states. */
++ for (j = 0; j < kDelta->recordCount; j += 1)
++ {
++ if (j >= Context->stateCount)
++ {
++ break;
++ }
++
++ /* Get the current state record. */
++ record = &recordArray[j];
++
++ /* Get the state address. */
++ address = record->address;
++
++ /* Make sure the state is a part of the mapping table. */
++ if (address >= Context->stateCount)
++ {
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): State 0x%04X is not mapped.\n",
++ __FUNCTION__, __LINE__,
++ address
++ );
++
++ continue;
++ }
++
++ /* Get the state index. */
++ index = map[address].index;
++
++ /* Skip the state if not mapped. */
++ if (index == 0)
++ {
++#if gcdDEBUG
++ if ((address != 0x0594)
++ && (address != 0x0E00)
++ && (address != 0x0E03)
++ )
++ {
++#endif
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): State 0x%04X is not mapped.\n",
++ __FUNCTION__, __LINE__,
++ address
++ );
++#if gcdDEBUG
++ }
++#endif
++ continue;
++ }
++
++ /* Get the data mask. */
++ mask = record->mask;
++
++ /* Masked states that are being completly reset or regular states. */
++ if ((mask == 0) || (mask == ~0U))
++ {
++ /* Get the new data value. */
++ data = record->data;
++
++ /* Process special states. */
++ if (address == 0x0595)
++ {
++ /* Force auto-disable to be disabled. */
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5)));
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4)));
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 13:13) - (0 ? 13:13) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 13:13) - (0 ? 13:13) + 1))))))) << (0 ? 13:13))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 13:13) - (0 ? 13:13) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 13:13) - (0 ? 13:13) + 1))))))) << (0 ? 13:13)));
++ }
++
++#if gcdSECURE_USER
++ /* Do we need to convert the logical address? */
++ if (Context->hint[address])
++ {
++ /* Map handle into physical address. */
++ gcmkONERROR(gckKERNEL_MapLogicalToPhysical(
++ kernel, cache, (gctPOINTER) &data
++ ));
++ }
++#endif
++
++ /* Set new data. */
++ buffer->logical[index] = data;
++ }
++
++ /* Masked states that are being set partially. */
++ else
++ {
++ buffer->logical[index]
++ = (~mask & buffer->logical[index])
++ | (mask & record->data);
++ }
++ }
++
++ /* Get the element count. */
++ if (kDelta->elementCount != 0)
++ {
++ elementCount = kDelta->elementCount;
++ }
++
++ /* Dereference delta. */
++ kDelta->refCount -= 1;
++ gcmkASSERT(kDelta->refCount >= 0);
++
++ /* Get the next state delta. */
++ nDelta = gcmUINT64_TO_PTR(kDelta->next);
++
++ /* Get access to the state records. */
++ gcmkONERROR(gckKERNEL_CloseUserData(
++ kernel, needCopy,
++ gcvFALSE,
++ gcmUINT64_TO_PTR(kDelta->recordArray), Context->recordArraySize,
++ (gctPOINTER *) &recordArray
++ ));
++
++ /* Close access to the current state delta. */
++ gcmkONERROR(gckKERNEL_CloseUserData(
++ kernel, needCopy,
++ gcvTRUE,
++ uDelta, gcmSIZEOF(gcsSTATE_DELTA),
++ (gctPOINTER *) &kDelta
++ ));
++
++ /* Update the user delta pointer. */
++ uDelta = nDelta;
++ }
++
++ /* Hardware disables all input streams when the stream 0 is programmed,
++ it then reenables those streams that were explicitely programmed by
++ the software. Because of this we cannot program the entire array of
++ values, otherwise we'll get all streams reenabled, but rather program
++ only those that are actully needed by the software. */
++ if (elementCount != 0)
++ {
++ gctUINT base;
++ gctUINT nopCount;
++ gctUINT32_PTR nop;
++ gctUINT fe2vsCount = 12;
++
++ if ((((((gctUINT32) (Context->hardware->identity.chipMinorFeatures1)) >> (0 ? 23:23)) & ((gctUINT32) ((((1 ? 23:23) - (0 ? 23:23) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:23) - (0 ? 23:23) + 1)))))) ))
++ {
++ fe2vsCount = 16;
++ }
++
++ /* Determine the base index of the vertex stream array. */
++ base = map[0x0180].index;
++
++ /* Set the proper state count. */
++ buffer->logical[base - 1]
++ = ((((gctUINT32) (buffer->logical[base - 1])) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (elementCount ) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ /* Determine the number of NOP commands. */
++ nopCount
++ = (fe2vsCount / 2)
++ - (elementCount / 2);
++
++ /* Determine the location of the first NOP. */
++ nop = &buffer->logical[base + (elementCount | 1)];
++
++ /* Fill the unused space with NOPs. */
++ for (i = 0; i < nopCount; i += 1)
++ {
++ if (nop >= buffer->logical + Context->totalSize)
++ {
++ break;
++ }
++
++ /* Generate a NOP command. */
++ *nop = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x03 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++
++ /* Advance. */
++ nop += 2;
++ }
++ }
++
++ /* Reset pending deltas. */
++ buffer->deltaCount = 0;
++ buffer->delta = gcvNULL;
++ }
++
++ /* Set state delta user pointer. */
++ uDelta = StateDelta;
++
++ /* Get access to the state delta. */
++ gcmkONERROR(gckKERNEL_OpenUserData(
++ kernel, needCopy,
++ &_stateDelta,
++ uDelta, gcmSIZEOF(gcsSTATE_DELTA),
++ (gctPOINTER *) &kDelta
++ ));
++
++ /* State delta cannot be attached to anything yet. */
++ if (kDelta->refCount != 0)
++ {
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): kDelta->refCount = %d (has to be 0).\n",
++ __FUNCTION__, __LINE__,
++ kDelta->refCount
++ );
++ }
++
++ /* Attach to all contexts. */
++ buffer = Context->buffer;
++
++ do
++ {
++ /* Attach to the context if nothing is attached yet. If a delta
++ is allready attached, all we need to do is to increment
++ the number of deltas in the context. */
++ if (buffer->delta == gcvNULL)
++ {
++ buffer->delta = uDelta;
++ }
++
++ /* Update reference count. */
++ kDelta->refCount += 1;
++
++ /* Update counters. */
++ buffer->deltaCount += 1;
++
++ /* Get the next context buffer. */
++ buffer = buffer->next;
++
++ if (buffer == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_NOT_FOUND);
++ }
++ }
++ while (Context->buffer != buffer);
++
++ /* Close access to the current state delta. */
++ gcmkONERROR(gckKERNEL_CloseUserData(
++ kernel, needCopy,
++ gcvTRUE,
++ uDelta, gcmSIZEOF(gcsSTATE_DELTA),
++ (gctPOINTER *) &kDelta
++ ));
++
++ /* Schedule an event to mark the context buffer as available. */
++ gcmkONERROR(gckEVENT_Signal(
++ buffer->eventObj, buffer->signal, gcvKERNEL_PIXEL
++ ));
++
++ /* Advance to the next context buffer. */
++ Context->buffer = buffer->next;
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Get access to the state records. */
++ if (kDelta != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckKERNEL_CloseUserData(
++ kernel, needCopy,
++ gcvFALSE,
++ gcmUINT64_TO_PTR(kDelta->recordArray), Context->recordArraySize,
++ (gctPOINTER *) &recordArray
++ ));
++ }
++
++ /* Close access to the current state delta. */
++ gcmkVERIFY_OK(gckKERNEL_CloseUserData(
++ kernel, needCopy,
++ gcvTRUE,
++ uDelta, gcmSIZEOF(gcsSTATE_DELTA),
++ (gctPOINTER *) &kDelta
++ ));
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++#else
++ return gcvSTATUS_OK;
++#endif
++}
++
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/arch/XAQ2/hal/kernel/gc_hal_kernel_context.h linux-xbian-imx6/drivers/mxc/gpu-viv/arch/XAQ2/hal/kernel/gc_hal_kernel_context.h
+--- linux-4.1.3/drivers/mxc/gpu-viv/arch/XAQ2/hal/kernel/gc_hal_kernel_context.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/arch/XAQ2/hal/kernel/gc_hal_kernel_context.h 2015-07-27 23:13:06.170964992 +0200
+@@ -0,0 +1,157 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_kernel_context_h_
++#define __gc_hal_kernel_context_h_
++
++#include "gc_hal_kernel_buffer.h"
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/* Maps state locations within the context buffer. */
++typedef struct _gcsSTATE_MAP * gcsSTATE_MAP_PTR;
++typedef struct _gcsSTATE_MAP
++{
++ /* Index of the state in the context buffer. */
++ gctUINT index;
++
++ /* State mask. */
++ gctUINT32 mask;
++}
++gcsSTATE_MAP;
++
++/* Context buffer. */
++typedef struct _gcsCONTEXT * gcsCONTEXT_PTR;
++typedef struct _gcsCONTEXT
++{
++ /* For debugging: the number of context buffer in the order of creation. */
++#if gcmIS_DEBUG(gcdDEBUG_CODE)
++ gctUINT num;
++#endif
++
++ /* Pointer to gckEVENT object. */
++ gckEVENT eventObj;
++
++ /* Context busy signal. */
++ gctSIGNAL signal;
++
++ /* Physical address of the context buffer. */
++ gctPHYS_ADDR physical;
++
++ /* Logical address of the context buffer. */
++ gctUINT32_PTR logical;
++
++ /* Pointer to the LINK commands. */
++ gctPOINTER link2D;
++ gctPOINTER link3D;
++
++ /* The number of pending state deltas. */
++ gctUINT deltaCount;
++
++ /* Pointer to the first delta to be applied. */
++ gcsSTATE_DELTA_PTR delta;
++
++ /* Next context buffer. */
++ gcsCONTEXT_PTR next;
++}
++gcsCONTEXT;
++
++/* gckCONTEXT structure that hold the current context. */
++struct _gckCONTEXT
++{
++ /* Object. */
++ gcsOBJECT object;
++
++ /* Pointer to gckOS object. */
++ gckOS os;
++
++ /* Pointer to gckHARDWARE object. */
++ gckHARDWARE hardware;
++
++ /* Command buffer alignment. */
++ gctSIZE_T alignment;
++ gctSIZE_T reservedHead;
++ gctSIZE_T reservedTail;
++
++ /* Context buffer metrics. */
++ gctSIZE_T stateCount;
++ gctSIZE_T totalSize;
++ gctSIZE_T bufferSize;
++ gctUINT32 linkIndex2D;
++ gctUINT32 linkIndex3D;
++ gctUINT32 linkIndexXD;
++ gctUINT32 entryOffset3D;
++ gctUINT32 entryOffsetXDFrom2D;
++ gctUINT32 entryOffsetXDFrom3D;
++
++ /* Dirty flags. */
++ gctBOOL dirty;
++ gctBOOL dirty2D;
++ gctBOOL dirty3D;
++ gcsCONTEXT_PTR dirtyBuffer;
++
++ /* State mapping. */
++ gcsSTATE_MAP_PTR map;
++
++ /* List of context buffers. */
++ gcsCONTEXT_PTR buffer;
++
++ /* A copy of the user record array. */
++ gctUINT recordArraySize;
++ gcsSTATE_DELTA_RECORD_PTR recordArray;
++
++ /* Requested pipe select for context. */
++ gcePIPE_SELECT entryPipe;
++ gcePIPE_SELECT exitPipe;
++
++ /* Variables used for building state buffer. */
++ gctUINT32 lastAddress;
++ gctSIZE_T lastSize;
++ gctUINT32 lastIndex;
++ gctBOOL lastFixed;
++
++ /* Hint array. */
++#if gcdSECURE_USER
++ gctBOOL_PTR hint;
++#endif
++
++#if VIVANTE_PROFILER_CONTEXT
++ gcsPROFILER_COUNTERS latestProfiler;
++ gcsPROFILER_COUNTERS histroyProfiler;
++ gctUINT32 prevVSInstCount;
++ gctUINT32 prevVSBranchInstCount;
++ gctUINT32 prevVSTexInstCount;
++ gctUINT32 prevVSVertexCount;
++ gctUINT32 prevPSInstCount;
++ gctUINT32 prevPSBranchInstCount;
++ gctUINT32 prevPSTexInstCount;
++ gctUINT32 prevPSPixelCount;
++#endif
++};
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __gc_hal_kernel_context_h_ */
++
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/arch/XAQ2/hal/kernel/gc_hal_kernel_hardware.c linux-xbian-imx6/drivers/mxc/gpu-viv/arch/XAQ2/hal/kernel/gc_hal_kernel_hardware.c
+--- linux-4.1.3/drivers/mxc/gpu-viv/arch/XAQ2/hal/kernel/gc_hal_kernel_hardware.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/arch/XAQ2/hal/kernel/gc_hal_kernel_hardware.c 2015-07-27 23:13:06.170964992 +0200
+@@ -0,0 +1,7280 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal.h"
++#include "gc_hal_kernel.h"
++#if VIVANTE_PROFILER_CONTEXT
++#include "gc_hal_kernel_context.h"
++#endif
++
++#define _GC_OBJ_ZONE gcvZONE_HARDWARE
++
++typedef struct _gcsiDEBUG_REGISTERS * gcsiDEBUG_REGISTERS_PTR;
++typedef struct _gcsiDEBUG_REGISTERS
++{
++ gctSTRING module;
++ gctUINT index;
++ gctUINT shift;
++ gctUINT data;
++ gctUINT count;
++ gctUINT32 signature;
++}
++gcsiDEBUG_REGISTERS;
++
++extern int gpu3DMinClock;
++/******************************************************************************\
++********************************* Support Code *********************************
++\******************************************************************************/
++static gceSTATUS
++_ResetGPU(
++ IN gckHARDWARE Hardware,
++ IN gckOS Os,
++ IN gceCORE Core
++ );
++
++static gceSTATUS
++_IdentifyHardware(
++ IN gckOS Os,
++ IN gceCORE Core,
++ OUT gcsHAL_QUERY_CHIP_IDENTITY_PTR Identity
++ )
++{
++ gceSTATUS status;
++
++ gctUINT32 chipIdentity;
++
++ gctUINT32 streamCount = 0;
++ gctUINT32 registerMax = 0;
++ gctUINT32 threadCount = 0;
++ gctUINT32 shaderCoreCount = 0;
++ gctUINT32 vertexCacheSize = 0;
++ gctUINT32 vertexOutputBufferSize = 0;
++ gctUINT32 pixelPipes = 0;
++ gctUINT32 instructionCount = 0;
++ gctUINT32 numConstants = 0;
++ gctUINT32 bufferSize = 0;
++ gctUINT32 varyingsCount = 0;
++ gctBOOL useHZ;
++
++ gcmkHEADER_ARG("Os=0x%x", Os);
++
++ /***************************************************************************
++ ** Get chip ID and revision.
++ */
++
++ /* Read chip identity register. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x00018,
++ &chipIdentity));
++
++ /* Special case for older graphic cores. */
++ if (((((gctUINT32) (chipIdentity)) >> (0 ? 31:24) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1)))))) == (0x01 & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))))
++ {
++ Identity->chipModel = gcv500;
++ Identity->chipRevision = (((((gctUINT32) (chipIdentity)) >> (0 ? 15:12)) & ((gctUINT32) ((((1 ? 15:12) - (0 ? 15:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:12) - (0 ? 15:12) + 1)))))) );
++ }
++
++ else
++ {
++ /* Read chip identity register. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x00020,
++ (gctUINT32_PTR) &Identity->chipModel));
++
++ /* !!!! HACK ALERT !!!! */
++ /* Because people change device IDs without letting software know
++ ** about it - here is the hack to make it all look the same. Only
++ ** for GC400 family. Next time - TELL ME!!! */
++ if (((Identity->chipModel & 0xFF00) == 0x0400)
++ && (Identity->chipModel != 0x0420))
++ {
++ Identity->chipModel = (gceCHIPMODEL) (Identity->chipModel & 0x0400);
++ }
++
++ /* Read CHIP_REV register. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x00024,
++ &Identity->chipRevision));
++
++ if ((Identity->chipModel == gcv300)
++ && (Identity->chipRevision == 0x2201)
++ )
++ {
++ gctUINT32 chipDate;
++ gctUINT32 chipTime;
++
++ /* Read date and time registers. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x00028,
++ &chipDate));
++
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x0002C,
++ &chipTime));
++
++ if ((chipDate == 0x20080814) && (chipTime == 0x12051100))
++ {
++ /* This IP has an ECO; put the correct revision in it. */
++ Identity->chipRevision = 0x1051;
++ }
++ }
++ }
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Identity: chipModel=%X",
++ Identity->chipModel);
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Identity: chipRevision=%X",
++ Identity->chipRevision);
++
++
++ /***************************************************************************
++ ** Get chip features.
++ */
++
++ /* Read chip feature register. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x0001C,
++ &Identity->chipFeatures));
++
++#ifndef VIVANTE_NO_3D
++ /* Disable fast clear on GC700. */
++ if (Identity->chipModel == gcv700)
++ {
++ Identity->chipFeatures
++ = ((((gctUINT32) (Identity->chipFeatures)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)));
++ }
++#endif
++
++ if (((Identity->chipModel == gcv500) && (Identity->chipRevision < 2))
++ || ((Identity->chipModel == gcv300) && (Identity->chipRevision < 0x2000))
++ )
++ {
++ /* GC500 rev 1.x and GC300 rev < 2.0 doesn't have these registers. */
++ Identity->chipMinorFeatures = 0;
++ Identity->chipMinorFeatures1 = 0;
++ Identity->chipMinorFeatures2 = 0;
++ Identity->chipMinorFeatures3 = 0;
++ Identity->chipMinorFeatures4 = 0;
++ }
++ else
++ {
++ /* Read chip minor feature register #0. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x00034,
++ &Identity->chipMinorFeatures));
++
++ if (((((gctUINT32) (Identity->chipMinorFeatures)) >> (0 ? 21:21) & ((gctUINT32) ((((1 ? 21:21) - (0 ? 21:21) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 21:21) - (0 ? 21:21) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 21:21) - (0 ? 21:21) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 21:21) - (0 ? 21:21) + 1)))))))
++ )
++ {
++ /* Read chip minor featuress register #1. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x00074,
++ &Identity->chipMinorFeatures1));
++
++ /* Read chip minor featuress register #2. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x00084,
++ &Identity->chipMinorFeatures2));
++
++ /*Identity->chipMinorFeatures2 &= ~(0x1 << 3);*/
++
++ /* Read chip minor featuress register #1. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x00088,
++ &Identity->chipMinorFeatures3));
++
++ /*The BG2 chip has no compression supertiled, and the bit of GCMinorFeature3BugFixes15 is n/a*/
++ if(Identity->chipModel == gcv1000 && Identity->chipRevision == 0x5036)
++ {
++ Identity->chipMinorFeatures3
++ = ((((gctUINT32) (Identity->chipMinorFeatures3)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5)));
++ Identity->chipMinorFeatures3
++ = ((((gctUINT32) (Identity->chipMinorFeatures3)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 27:27) - (0 ? 27:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:27) - (0 ? 27:27) + 1))))))) << (0 ? 27:27))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 27:27) - (0 ? 27:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:27) - (0 ? 27:27) + 1))))))) << (0 ? 27:27)));
++ }
++
++ /* Read chip minor featuress register #4. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x00094,
++ &Identity->chipMinorFeatures4));
++ }
++ else
++ {
++ /* Chip doesn't has minor features register #1 or 2 or 3 or 4. */
++ Identity->chipMinorFeatures1 = 0;
++ Identity->chipMinorFeatures2 = 0;
++ Identity->chipMinorFeatures3 = 0;
++ Identity->chipMinorFeatures4 = 0;
++ }
++ }
++
++ /* Get the Supertile layout in the hardware. */
++ if (((((gctUINT32) (Identity->chipMinorFeatures3)) >> (0 ? 26:26) & ((gctUINT32) ((((1 ? 26:26) - (0 ? 26:26) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 26:26) - (0 ? 26:26) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 26:26) - (0 ? 26:26) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 26:26) - (0 ? 26:26) + 1)))))))
++ || ((((gctUINT32) (Identity->chipMinorFeatures3)) >> (0 ? 8:8) & ((gctUINT32) ((((1 ? 8:8) - (0 ? 8:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:8) - (0 ? 8:8) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 8:8) - (0 ? 8:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:8) - (0 ? 8:8) + 1))))))))
++ {
++ Identity->superTileMode = 2;
++ }
++ else if (((((gctUINT32) (Identity->chipMinorFeatures)) >> (0 ? 27:27) & ((gctUINT32) ((((1 ? 27:27) - (0 ? 27:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:27) - (0 ? 27:27) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 27:27) - (0 ? 27:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:27) - (0 ? 27:27) + 1))))))))
++ {
++ Identity->superTileMode = 1;
++ }
++ else
++ {
++ Identity->superTileMode = 0;
++ }
++
++ /* Exception for GC1000, revision 5035 & GC800, revision 4612 */
++ if (((Identity->chipModel == gcv1000) && ((Identity->chipRevision == 0x5035)
++ || (Identity->chipRevision == 0x5036)
++ || (Identity->chipRevision == 0x5037)))
++ || ((Identity->chipModel == gcv800) && (Identity->chipRevision == 0x4612))
++ || ((Identity->chipModel == gcv860) && (Identity->chipRevision == 0x4647)))
++ {
++ Identity->superTileMode = 1;
++ }
++
++ if (Identity->chipModel == gcv4000 && Identity->chipRevision == 0x5245)
++ {
++ useHZ = ((((gctUINT32) (Identity->chipMinorFeatures3)) >> (0 ? 26:26) & ((gctUINT32) ((((1 ? 26:26) - (0 ? 26:26) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 26:26) - (0 ? 26:26) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 26:26) - (0 ? 26:26) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 26:26) - (0 ? 26:26) + 1)))))))
++ || ((((gctUINT32) (Identity->chipMinorFeatures3)) >> (0 ? 8:8) & ((gctUINT32) ((((1 ? 8:8) - (0 ? 8:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:8) - (0 ? 8:8) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 8:8) - (0 ? 8:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:8) - (0 ? 8:8) + 1)))))));
++ }
++ else
++ {
++ useHZ = gcvFALSE;
++ }
++
++ if (useHZ)
++ {
++ /* Disable EZ. */
++ Identity->chipFeatures
++ = ((((gctUINT32) (Identity->chipFeatures)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) << (0 ? 16:16))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) << (0 ? 16:16)));
++ }
++
++ /* Disable HZ when EZ is present for older chips. */
++ else if (!((((gctUINT32) (Identity->chipFeatures)) >> (0 ? 16:16) & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))))
++ {
++ /* Disable HIERARCHICAL_Z. */
++ Identity->chipMinorFeatures
++ = ((((gctUINT32) (Identity->chipMinorFeatures)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 27:27) - (0 ? 27:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:27) - (0 ? 27:27) + 1))))))) << (0 ? 27:27))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 27:27) - (0 ? 27:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:27) - (0 ? 27:27) + 1))))))) << (0 ? 27:27)));
++ }
++
++ /* Disable rectangle primitive when chip is gc880_5_1_0_rc6*/
++ if ((Identity->chipModel == gcv880) && (Identity->chipRevision == 0x5106))
++ {
++ /* Disable rectangle primitive. */
++ Identity->chipMinorFeatures2
++ = ((((gctUINT32) (Identity->chipMinorFeatures2)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5)));
++ }
++
++ if ((Identity->chipModel == gcv800) && (Identity->chipRevision == 0x4605))
++ {
++ /* Correct feature bit: RTL does not have such feature. */
++ Identity->chipFeatures
++ = ((((gctUINT32) (Identity->chipFeatures)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:31) - (0 ? 31:31) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:31) - (0 ? 31:31) + 1))))))) << (0 ? 31:31))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 31:31) - (0 ? 31:31) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:31) - (0 ? 31:31) + 1))))))) << (0 ? 31:31)));
++ }
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Identity: chipFeatures=0x%08X",
++ Identity->chipFeatures);
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Identity: chipMinorFeatures=0x%08X",
++ Identity->chipMinorFeatures);
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Identity: chipMinorFeatures1=0x%08X",
++ Identity->chipMinorFeatures1);
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Identity: chipMinorFeatures2=0x%08X",
++ Identity->chipMinorFeatures2);
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Identity: chipMinorFeatures3=0x%08X",
++ Identity->chipMinorFeatures3);
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Identity: chipMinorFeatures4=0x%08X",
++ Identity->chipMinorFeatures4);
++
++ /***************************************************************************
++ ** Get chip specs.
++ */
++
++ if (((((gctUINT32) (Identity->chipMinorFeatures)) >> (0 ? 21:21) & ((gctUINT32) ((((1 ? 21:21) - (0 ? 21:21) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 21:21) - (0 ? 21:21) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 21:21) - (0 ? 21:21) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 21:21) - (0 ? 21:21) + 1))))))))
++ {
++ gctUINT32 specs, specs2, specs3;
++
++ /* Read gcChipSpecs register. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x00048,
++ &specs));
++
++ /* Extract the fields. */
++ streamCount = (((((gctUINT32) (specs)) >> (0 ? 3:0)) & ((gctUINT32) ((((1 ? 3:0) - (0 ? 3:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:0) - (0 ? 3:0) + 1)))))) );
++ registerMax = (((((gctUINT32) (specs)) >> (0 ? 7:4)) & ((gctUINT32) ((((1 ? 7:4) - (0 ? 7:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:4) - (0 ? 7:4) + 1)))))) );
++ threadCount = (((((gctUINT32) (specs)) >> (0 ? 11:8)) & ((gctUINT32) ((((1 ? 11:8) - (0 ? 11:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:8) - (0 ? 11:8) + 1)))))) );
++ shaderCoreCount = (((((gctUINT32) (specs)) >> (0 ? 24:20)) & ((gctUINT32) ((((1 ? 24:20) - (0 ? 24:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 24:20) - (0 ? 24:20) + 1)))))) );
++ vertexCacheSize = (((((gctUINT32) (specs)) >> (0 ? 16:12)) & ((gctUINT32) ((((1 ? 16:12) - (0 ? 16:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:12) - (0 ? 16:12) + 1)))))) );
++ vertexOutputBufferSize = (((((gctUINT32) (specs)) >> (0 ? 31:28)) & ((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1)))))) );
++ pixelPipes = (((((gctUINT32) (specs)) >> (0 ? 27:25)) & ((gctUINT32) ((((1 ? 27:25) - (0 ? 27:25) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:25) - (0 ? 27:25) + 1)))))) );
++
++ /* Read gcChipSpecs2 register. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x00080,
++ &specs2));
++
++ instructionCount = (((((gctUINT32) (specs2)) >> (0 ? 15:8)) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1)))))) );
++ numConstants = (((((gctUINT32) (specs2)) >> (0 ? 31:16)) & ((gctUINT32) ((((1 ? 31:16) - (0 ? 31:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:16) - (0 ? 31:16) + 1)))))) );
++ bufferSize = (((((gctUINT32) (specs2)) >> (0 ? 7:0)) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1)))))) );
++
++ /* Read gcChipSpecs3 register. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x0008C,
++ &specs3));
++
++ varyingsCount = (((((gctUINT32) (specs3)) >> (0 ? 8:4)) & ((gctUINT32) ((((1 ? 8:4) - (0 ? 8:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:4) - (0 ? 8:4) + 1)))))) );
++ }
++
++ /* Get the number of pixel pipes. */
++ Identity->pixelPipes = gcmMAX(pixelPipes, 1);
++
++ /* Get the stream count. */
++ Identity->streamCount = (streamCount != 0)
++ ? streamCount
++ : (Identity->chipModel >= gcv1000) ? 4 : 1;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Specs: streamCount=%u%s",
++ Identity->streamCount,
++ (streamCount == 0) ? " (default)" : "");
++
++ /* Get the vertex output buffer size. */
++ Identity->vertexOutputBufferSize = (vertexOutputBufferSize != 0)
++ ? 1 << vertexOutputBufferSize
++ : (Identity->chipModel == gcv400)
++ ? (Identity->chipRevision < 0x4000) ? 512
++ : (Identity->chipRevision < 0x4200) ? 256
++ : 128
++ : (Identity->chipModel == gcv530)
++ ? (Identity->chipRevision < 0x4200) ? 512
++ : 128
++ : 512;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Specs: vertexOutputBufferSize=%u%s",
++ Identity->vertexOutputBufferSize,
++ (vertexOutputBufferSize == 0) ? " (default)" : "");
++
++ /* Get the maximum number of threads. */
++ Identity->threadCount = (threadCount != 0)
++ ? 1 << threadCount
++ : (Identity->chipModel == gcv400) ? 64
++ : (Identity->chipModel == gcv500) ? 128
++ : (Identity->chipModel == gcv530) ? 128
++ : 256;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Specs: threadCount=%u%s",
++ Identity->threadCount,
++ (threadCount == 0) ? " (default)" : "");
++
++ /* Get the number of shader cores. */
++ Identity->shaderCoreCount = (shaderCoreCount != 0)
++ ? shaderCoreCount
++ : (Identity->chipModel >= gcv1000) ? 2
++ : 1;
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Specs: shaderCoreCount=%u%s",
++ Identity->shaderCoreCount,
++ (shaderCoreCount == 0) ? " (default)" : "");
++
++ /* Get the vertex cache size. */
++ Identity->vertexCacheSize = (vertexCacheSize != 0)
++ ? vertexCacheSize
++ : 8;
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Specs: vertexCacheSize=%u%s",
++ Identity->vertexCacheSize,
++ (vertexCacheSize == 0) ? " (default)" : "");
++
++ /* Get the maximum number of temporary registers. */
++ Identity->registerMax = (registerMax != 0)
++ /* Maximum of registerMax/4 registers are accessible to 1 shader */
++ ? 1 << registerMax
++ : (Identity->chipModel == gcv400) ? 32
++ : 64;
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Specs: registerMax=%u%s",
++ Identity->registerMax,
++ (registerMax == 0) ? " (default)" : "");
++
++ /* Get the instruction count. */
++ Identity->instructionCount = (instructionCount == 0) ? 256
++ : (instructionCount == 1) ? 1024
++ : (instructionCount == 2) ? 2048
++ : (instructionCount == 0xFF) ? 512
++ : 256;
++
++ if (Identity->instructionCount == 256)
++ {
++ if ((Identity->chipModel == gcv2000 && Identity->chipRevision == 0x5108)
++ || Identity->chipModel == gcv880)
++ {
++ Identity->instructionCount = 512;
++ }
++ }
++
++ if (((((gctUINT32) (Identity->chipMinorFeatures3)) >> (0 ? 3:3) & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))))
++ {
++ Identity->instructionCount = 512;
++ }
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Specs: instructionCount=%u%s",
++ Identity->instructionCount,
++ (instructionCount == 0) ? " (default)" : "");
++
++ /* Get the number of constants. */
++ Identity->numConstants = (numConstants == 0) ? 168 : numConstants;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Specs: numConstants=%u%s",
++ Identity->numConstants,
++ (numConstants == 0) ? " (default)" : "");
++
++ /* Get the buffer size. */
++ Identity->bufferSize = bufferSize;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Specs: bufferSize=%u%s",
++ Identity->bufferSize,
++ (bufferSize == 0) ? " (default)" : "");
++
++
++ if (varyingsCount != 0)
++ {
++ /* Bug 4480. */
++ /*Identity->varyingsCount = varyingsCount;*/
++ Identity->varyingsCount = 12;
++ }
++ else if (((((gctUINT32) (Identity->chipMinorFeatures1)) >> (0 ? 23:23) & ((gctUINT32) ((((1 ? 23:23) - (0 ? 23:23) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:23) - (0 ? 23:23) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 23:23) - (0 ? 23:23) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:23) - (0 ? 23:23) + 1))))))))
++ {
++ Identity->varyingsCount = 12;
++ }
++ else
++ {
++ Identity->varyingsCount = 8;
++ }
++
++ /* For some cores, it consumes two varying for position, so the max varying vectors should minus one. */
++ if ((Identity->chipModel == gcv4000 && Identity->chipRevision == 0x5222) ||
++ (Identity->chipModel == gcv4000 && Identity->chipRevision == 0x5208) ||
++ ((Identity->chipModel == gcv2100 || Identity->chipModel == gcv2000) && Identity->chipRevision == 0x5108) ||
++ (Identity->chipModel == gcv880 && (Identity->chipRevision == 0x5107 || Identity->chipRevision == 0x5106)))
++ {
++ Identity->varyingsCount -= 1;
++ }
++
++ Identity->chip2DControl = 0;
++ if (Identity->chipModel == gcv320)
++ {
++ gctUINT32 data;
++
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os,
++ Core,
++ 0x0002C,
++ &data));
++
++ if ((data != 33956864) &&
++ ((Identity->chipRevision == 0x5007) ||
++ (Identity->chipRevision == 0x5220)))
++ {
++ Identity->chip2DControl |= 0xFF &
++ (Identity->chipRevision == 0x5220 ? 8 :
++ (Identity->chipRevision == 0x5007 ? 12 : 0));
++ }
++
++ if (Identity->chipRevision == 0x5007)
++ {
++ /* Disable splitting rectangle. */
++ Identity->chip2DControl |= 0x100;
++
++ /* Enable 2D Flush. */
++ Identity->chip2DControl |= 0x200;
++ }
++ }
++
++ /* Success. */
++ gcmkFOOTER();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++#if gcdPOWEROFF_TIMEOUT
++void
++_PowerTimerFunction(
++ gctPOINTER Data
++ )
++{
++ gckHARDWARE hardware = (gckHARDWARE)Data;
++ gcmkVERIFY_OK(
++ gckHARDWARE_SetPowerManagementState(hardware, gcvPOWER_OFF_TIMEOUT));
++}
++#endif
++
++static gceSTATUS
++_VerifyDMA(
++ IN gckOS Os,
++ IN gceCORE Core,
++ gctUINT32_PTR Address1,
++ gctUINT32_PTR Address2,
++ gctUINT32_PTR State1,
++ gctUINT32_PTR State2
++ )
++{
++ gceSTATUS status;
++ gctUINT32 i;
++
++ gcmkONERROR(gckOS_ReadRegisterEx(Os, Core, 0x660, State1));
++ gcmkONERROR(gckOS_ReadRegisterEx(Os, Core, 0x664, Address1));
++
++ for (i = 0; i < 500; i += 1)
++ {
++ gcmkONERROR(gckOS_ReadRegisterEx(Os, Core, 0x660, State2));
++ gcmkONERROR(gckOS_ReadRegisterEx(Os, Core, 0x664, Address2));
++
++ if (*Address1 != *Address2)
++ {
++ break;
++ }
++
++ if (*State1 != *State2)
++ {
++ break;
++ }
++ }
++
++OnError:
++ return status;
++}
++
++static gceSTATUS
++_DumpDebugRegisters(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gcsiDEBUG_REGISTERS_PTR Descriptor
++ )
++{
++ gceSTATUS status = gcvSTATUS_OK;
++ gctUINT32 select;
++ gctUINT32 data = 0;
++ gctUINT i;
++
++ gcmkHEADER_ARG("Os=0x%X Descriptor=0x%X", Os, Descriptor);
++
++ gcmkPRINT_N(4, " %s debug registers:\n", Descriptor->module);
++
++ for (i = 0; i < Descriptor->count; i += 1)
++ {
++ select = i << Descriptor->shift;
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Os, Core, Descriptor->index, select));
++#if gcdFPGA_BUILD
++ gcmkONERROR(gckOS_Delay(Os, 1000));
++#endif
++ gcmkONERROR(gckOS_ReadRegisterEx(Os, Core, Descriptor->data, &data));
++
++ gcmkPRINT_N(12, " [0x%02X] 0x%08X\n", i, data);
++ }
++
++ select = 0xF << Descriptor->shift;
++
++ for (i = 0; i < 500; i += 1)
++ {
++ gcmkONERROR(gckOS_WriteRegisterEx(Os, Core, Descriptor->index, select));
++#if gcdFPGA_BUILD
++ gcmkONERROR(gckOS_Delay(Os, 1000));
++#endif
++ gcmkONERROR(gckOS_ReadRegisterEx(Os, Core, Descriptor->data, &data));
++
++ if (data == Descriptor->signature)
++ {
++ break;
++ }
++ }
++
++ if (i == 500)
++ {
++ gcmkPRINT_N(4, " failed to obtain the signature (read 0x%08X).\n", data);
++ }
++ else
++ {
++ gcmkPRINT_N(8, " signature = 0x%08X (%d read attempt(s))\n", data, i + 1);
++ }
++
++OnError:
++ /* Return the error. */
++ gcmkFOOTER();
++ return status;
++}
++
++static gceSTATUS
++_IsGPUPresent(
++ IN gckHARDWARE Hardware
++ )
++{
++ gceSTATUS status;
++ gcsHAL_QUERY_CHIP_IDENTITY identity;
++ gctUINT32 control;
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ &control));
++
++ control = ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1)));
++ control = ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ control));
++
++ /* Identify the hardware. */
++ gcmkONERROR(_IdentifyHardware(Hardware->os,
++ Hardware->core,
++ &identity));
++
++ /* Check if these are the same values as saved before. */
++ if ((Hardware->identity.chipModel != identity.chipModel)
++ || (Hardware->identity.chipRevision != identity.chipRevision)
++ || (Hardware->identity.chipFeatures != identity.chipFeatures)
++ || (Hardware->identity.chipMinorFeatures != identity.chipMinorFeatures)
++ || (Hardware->identity.chipMinorFeatures1 != identity.chipMinorFeatures1)
++ || (Hardware->identity.chipMinorFeatures2 != identity.chipMinorFeatures2)
++ )
++ {
++ gcmkPRINT("[galcore]: GPU is not present.");
++ gcmkONERROR(gcvSTATUS_GPU_NOT_RESPONDING);
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the error. */
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++_FlushCache(
++ gckHARDWARE Hardware,
++ gckCOMMAND Command
++ )
++{
++ gceSTATUS status;
++ gctSIZE_T bytes, requested;
++ gctPOINTER buffer;
++
++ /* Get the size of the flush command. */
++ gcmkONERROR(gckHARDWARE_Flush(Hardware,
++ gcvFLUSH_ALL,
++ gcvNULL,
++ &requested));
++
++ /* Reserve space in the command queue. */
++ gcmkONERROR(gckCOMMAND_Reserve(Command,
++ requested,
++ &buffer,
++ &bytes));
++
++ /* Append a flush. */
++ gcmkONERROR(gckHARDWARE_Flush(
++ Hardware, gcvFLUSH_ALL, buffer, &bytes
++ ));
++
++ /* Execute the command queue. */
++ gcmkONERROR(gckCOMMAND_Execute(Command, requested));
++
++ return gcvSTATUS_OK;
++
++OnError:
++ return status;
++}
++
++/******************************************************************************\
++****************************** gckHARDWARE API code *****************************
++\******************************************************************************/
++
++/*******************************************************************************
++**
++** gckHARDWARE_Construct
++**
++** Construct a new gckHARDWARE object.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an initialized gckOS object.
++**
++** gceCORE Core
++** Specified core.
++**
++** OUTPUT:
++**
++** gckHARDWARE * Hardware
++** Pointer to a variable that will hold the pointer to the gckHARDWARE
++** object.
++*/
++gceSTATUS
++gckHARDWARE_Construct(
++ IN gckOS Os,
++ IN gceCORE Core,
++ OUT gckHARDWARE * Hardware
++ )
++{
++ gceSTATUS status;
++ gckHARDWARE hardware = gcvNULL;
++ gctUINT16 data = 0xff00;
++ gctUINT32 axi_ot;
++ gctPOINTER pointer = gcvNULL;
++
++ gcmkHEADER_ARG("Os=0x%x", Os);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Hardware != gcvNULL);
++
++ /* Enable the GPU. */
++ gcmkONERROR(gckOS_SetGPUPower(Os, Core, gcvTRUE, gcvTRUE));
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ Core,
++ 0x00000,
++ 0x00000900));
++
++ /* Allocate the gckHARDWARE object. */
++ gcmkONERROR(gckOS_Allocate(Os,
++ gcmSIZEOF(struct _gckHARDWARE),
++ &pointer));
++
++ hardware = (gckHARDWARE) pointer;
++
++ /* Initialize the gckHARDWARE object. */
++ hardware->object.type = gcvOBJ_HARDWARE;
++ hardware->os = Os;
++ hardware->core = Core;
++
++ /* Identify the hardware. */
++ gcmkONERROR(_IdentifyHardware(Os, Core, &hardware->identity));
++
++ /* Determine the hardware type */
++ switch (hardware->identity.chipModel)
++ {
++ case gcv350:
++ case gcv355:
++ hardware->type = gcvHARDWARE_VG;
++ break;
++
++ case gcv300:
++ case gcv320:
++ case gcv420:
++ hardware->type = gcvHARDWARE_2D;
++ /*set outstanding limit*/
++ gcmkONERROR(gckOS_ReadRegisterEx(Os, Core, 0x00414, &axi_ot));
++ axi_ot = (axi_ot & (~0xFF)) | 0x10;
++ gcmkONERROR(gckOS_WriteRegisterEx(Os, Core, 0x00414, axi_ot));
++ break;
++
++ default:
++ hardware->type = gcvHARDWARE_3D;
++ if(hardware->identity.chipModel == gcv880)
++ {
++ /*set outstanding limit*/
++ gcmkONERROR(gckOS_ReadRegisterEx(Os, Core, 0x00414, &axi_ot));
++ axi_ot = (axi_ot & (~0xFF)) | 0x10;
++ gcmkONERROR(gckOS_WriteRegisterEx(Os, Core, 0x00414, axi_ot));
++ }
++
++ if ((((((gctUINT32) (hardware->identity.chipFeatures)) >> (0 ? 9:9)) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1)))))) ))
++ {
++ hardware->type = (gceHARDWARE_TYPE) (hardware->type | gcvHARDWARE_2D);
++ }
++ }
++
++ hardware->powerBaseAddress
++ = ((hardware->identity.chipModel == gcv300)
++ && (hardware->identity.chipRevision < 0x2000))
++ ? 0x0100
++ : 0x0000;
++
++ /* _ResetGPU need powerBaseAddress. */
++ status = _ResetGPU(hardware, Os, Core);
++
++ if (status != gcvSTATUS_OK)
++ {
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "_ResetGPU failed: status=%d\n", status);
++ }
++
++ hardware->powerMutex = gcvNULL;
++
++ hardware->mmuVersion
++ = (((((gctUINT32) (hardware->identity.chipMinorFeatures1)) >> (0 ? 28:28)) & ((gctUINT32) ((((1 ? 28:28) - (0 ? 28:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 28:28) - (0 ? 28:28) + 1)))))) );
++
++ /* Determine whether bug fixes #1 are present. */
++ hardware->extraEventStates = ((((gctUINT32) (hardware->identity.chipMinorFeatures1)) >> (0 ? 3:3) & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1)))))) == (0x0 & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1)))))));
++
++ /* Check if big endian */
++ hardware->bigEndian = (*(gctUINT8 *)&data == 0xff);
++
++ /* Initialize the fast clear. */
++ gcmkONERROR(gckHARDWARE_SetFastClear(hardware, -1, -1));
++
++#if !gcdENABLE_128B_MERGE
++
++ if (((((gctUINT32) (hardware->identity.chipMinorFeatures2)) >> (0 ? 21:21) & ((gctUINT32) ((((1 ? 21:21) - (0 ? 21:21) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 21:21) - (0 ? 21:21) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 21:21) - (0 ? 21:21) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 21:21) - (0 ? 21:21) + 1))))))))
++ {
++ /* 128B merge is turned on by default. Disable it. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Os, Core, 0x00558, 0));
++ }
++
++#endif
++
++ /* Set power state to ON. */
++ hardware->chipPowerState = gcvPOWER_ON;
++ hardware->clockState = gcvTRUE;
++ hardware->powerState = gcvTRUE;
++ hardware->lastWaitLink = ~0U;
++ hardware->globalSemaphore = gcvNULL;
++#if gcdENABLE_FSCALE_VAL_ADJUST
++ hardware->powerOnFscaleVal = 64;
++#endif
++
++ gcmkONERROR(gckOS_CreateMutex(Os, &hardware->powerMutex));
++ gcmkONERROR(gckOS_CreateSemaphore(Os, &hardware->globalSemaphore));
++ hardware->startIsr = gcvNULL;
++ hardware->stopIsr = gcvNULL;
++
++#if gcdPOWEROFF_TIMEOUT
++ hardware->powerOffTimeout = gcdPOWEROFF_TIMEOUT;
++
++ gcmkVERIFY_OK(gckOS_CreateTimer(Os,
++ _PowerTimerFunction,
++ (gctPOINTER)hardware,
++ &hardware->powerOffTimer));
++#endif
++
++ gcmkONERROR(gckOS_AtomConstruct(Os, &hardware->pageTableDirty));
++
++#if gcdLINK_QUEUE_SIZE
++ hardware->linkQueue.front = 0;
++ hardware->linkQueue.rear = 0;
++ hardware->linkQueue.count = 0;
++#endif
++
++ /* Enable power management by default. */
++ hardware->powerManagement = gcvTRUE;
++
++ /* Disable profiler by default */
++ hardware->gpuProfiler = gcvFALSE;
++
++ /* Return pointer to the gckHARDWARE object. */
++ *Hardware = hardware;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Hardware=0x%x", *Hardware);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Roll back. */
++ if (hardware != gcvNULL)
++ {
++ /* Turn off the power. */
++ gcmkVERIFY_OK(gckOS_SetGPUPower(Os, Core, gcvFALSE, gcvFALSE));
++
++ if (hardware->globalSemaphore != gcvNULL)
++ {
++ /* Destroy the global semaphore. */
++ gcmkVERIFY_OK(gckOS_DestroySemaphore(Os,
++ hardware->globalSemaphore));
++ }
++
++ if (hardware->powerMutex != gcvNULL)
++ {
++ /* Destroy the power mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Os, hardware->powerMutex));
++ }
++
++#if gcdPOWEROFF_TIMEOUT
++ if (hardware->powerOffTimer != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_StopTimer(Os, hardware->powerOffTimer));
++ gcmkVERIFY_OK(gckOS_DestroyTimer(Os, hardware->powerOffTimer));
++ }
++#endif
++
++ if (hardware->pageTableDirty != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_AtomDestroy(Os, hardware->pageTableDirty));
++ }
++
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Os, hardware));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_Destroy
++**
++** Destroy an gckHARDWARE object.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to the gckHARDWARE object that needs to be destroyed.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckHARDWARE_Destroy(
++ IN gckHARDWARE Hardware
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Destroy the power semaphore. */
++ gcmkVERIFY_OK(gckOS_DestroySemaphore(Hardware->os,
++ Hardware->globalSemaphore));
++
++ /* Destroy the power mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Hardware->os, Hardware->powerMutex));
++
++#if gcdPOWEROFF_TIMEOUT
++ gcmkVERIFY_OK(gckOS_StopTimer(Hardware->os, Hardware->powerOffTimer));
++ gcmkVERIFY_OK(gckOS_DestroyTimer(Hardware->os, Hardware->powerOffTimer));
++#endif
++
++ gcmkVERIFY_OK(gckOS_AtomDestroy(Hardware->os, Hardware->pageTableDirty));
++
++ /* Mark the object as unknown. */
++ Hardware->object.type = gcvOBJ_UNKNOWN;
++
++ /* Free the object. */
++ gcmkONERROR(gcmkOS_SAFE_FREE(Hardware->os, Hardware));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_GetType
++**
++** Get the hardware type.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** OUTPUT:
++**
++** gceHARDWARE_TYPE * Type
++** Pointer to a variable that receives the type of hardware object.
++*/
++gceSTATUS
++gckHARDWARE_GetType(
++ IN gckHARDWARE Hardware,
++ OUT gceHARDWARE_TYPE * Type
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++ gcmkVERIFY_ARGUMENT(Type != gcvNULL);
++
++ *Type = Hardware->type;
++
++ gcmkFOOTER_ARG("*Type=%d", *Type);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_InitializeHardware
++**
++** Initialize the hardware.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to the gckHARDWARE object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckHARDWARE_InitializeHardware(
++ IN gckHARDWARE Hardware
++ )
++{
++ gceSTATUS status;
++ gctUINT32 baseAddress;
++ gctUINT32 chipRev;
++ gctUINT32 control;
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Read the chip revision register. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00024,
++ &chipRev));
++
++ if (chipRev != Hardware->identity.chipRevision)
++ {
++ /* Chip is not there! */
++ gcmkONERROR(gcvSTATUS_CONTEXT_LOSSED);
++ }
++
++ /* Disable isolate GPU bit. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ ((((gctUINT32) (0x00000900)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19)))));
++
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ &control));
++
++ /* Enable debug register. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 11:11) - (0 ? 11:11) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:11) - (0 ? 11:11) + 1))))))) << (0 ? 11:11))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 11:11) - (0 ? 11:11) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:11) - (0 ? 11:11) + 1))))))) << (0 ? 11:11)))));
++
++ /* Reset memory counters. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0003C,
++ ~0U));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0003C,
++ 0));
++
++ /* Get the system's physical base address. */
++ gcmkONERROR(gckOS_GetBaseAddress(Hardware->os, &baseAddress));
++
++ /* Program the base addesses. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0041C,
++ baseAddress));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00418,
++ baseAddress));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00428,
++ baseAddress));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00420,
++ baseAddress));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00424,
++ baseAddress));
++
++#if !VIVANTE_PROFILER
++ {
++ gctUINT32 data;
++
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress +
++ 0x00100,
++ &data));
++
++ /* Enable clock gating. */
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)));
++
++ if ((Hardware->identity.chipRevision == 0x4301)
++ || (Hardware->identity.chipRevision == 0x4302)
++ )
++ {
++ /* Disable stall module level clock gating for 4.3.0.1 and 4.3.0.2
++ ** revisions. */
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1)));
++ }
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress
++ + 0x00100,
++ data));
++
++#ifndef VIVANTE_NO_3D
++ /* Disable PE clock gating on revs < 5.0 when HZ is present without a
++ ** bug fix. */
++ if ((Hardware->identity.chipRevision < 0x5000)
++ && ((((gctUINT32) (Hardware->identity.chipMinorFeatures1)) >> (0 ? 9:9) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1)))))) == (0x0 & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1)))))))
++ && ((((gctUINT32) (Hardware->identity.chipMinorFeatures)) >> (0 ? 27:27) & ((gctUINT32) ((((1 ? 27:27) - (0 ? 27:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:27) - (0 ? 27:27) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 27:27) - (0 ? 27:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:27) - (0 ? 27:27) + 1)))))))
++ )
++ {
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress
++ + 0x00104,
++ &data));
++
++ /* Disable PE clock gating. */
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2)));
++
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress
++ + 0x00104,
++ data));
++ }
++
++#endif
++ }
++#endif
++
++ /* Special workaround for this core
++ ** Make sure pulse eater kicks in only when SH is idle */
++ if (Hardware->identity.chipModel == gcv4000 &&
++ Hardware->identity.chipRevision == 0x5208)
++ {
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0010C,
++ ((((gctUINT32) (0x01590880)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:23) - (0 ? 23:23) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:23) - (0 ? 23:23) + 1))))))) << (0 ? 23:23))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 23:23) - (0 ? 23:23) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:23) - (0 ? 23:23) + 1))))))) << (0 ? 23:23)))));
++ }
++
++ if ((gckHARDWARE_IsFeatureAvailable(Hardware, gcvFEATURE_HALTI2) == gcvFALSE)
++ || (gckHARDWARE_IsFeatureAvailable(Hardware, gcvFEATURE_HALTI2) && (Hardware->identity.chipRevision < 0x5422))
++ )
++ {
++ gctUINT32 data;
++
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress
++ + 0x00104,
++ &data));
++
++
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:15) - (0 ? 15:15) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:15) - (0 ? 15:15) + 1))))))) << (0 ? 15:15))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 15:15) - (0 ? 15:15) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:15) - (0 ? 15:15) + 1))))))) << (0 ? 15:15)));
++
++
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress
++ + 0x00104,
++ data));
++ }
++
++ /* Special workaround for this core
++ ** Make sure FE and TX are on different buses */
++ if ((Hardware->identity.chipModel == gcv2000)
++ && (Hardware->identity.chipRevision == 0x5108))
++ {
++ gctUINT32 data;
++
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00480,
++ &data));
++
++ /* Set FE bus to one, TX bus to zero */
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3)));
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1))))))) << (0 ? 7:7))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1))))))) << (0 ? 7:7)));
++
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00480,
++ data));
++ }
++
++ /* Test if MMU is initialized. */
++ if ((Hardware->kernel != gcvNULL)
++ && (Hardware->kernel->mmu != gcvNULL)
++ )
++ {
++ /* Reset MMU. */
++ if (Hardware->mmuVersion == 0)
++ {
++ gcmkONERROR(
++ gckHARDWARE_SetMMU(Hardware,
++ Hardware->kernel->mmu->pageTableLogical));
++ }
++ }
++
++ if (Hardware->identity.chipModel >= gcv400
++ && Hardware->identity.chipModel != gcv420
++ && (((((gctUINT32) (Hardware->identity.chipMinorFeatures3)) >> (0 ? 15:15) & ((gctUINT32) ((((1 ? 15:15) - (0 ? 15:15) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:15) - (0 ? 15:15) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 15:15) - (0 ? 15:15) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:15) - (0 ? 15:15) + 1))))))) != gcvTRUE)
++ )
++ {
++ gctUINT32 data;
++
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress
++ + 0x00104,
++ &data));
++
++ /* Disable PA clock gating. */
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4)));
++
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress
++ + 0x00104,
++ data));
++ }
++
++#if gcdHZ_L2_DISALBE
++ /* Disable HZ-L2. */
++ if (((((gctUINT32) (Hardware->identity.chipMinorFeatures3)) >> (0 ? 26:26) & ((gctUINT32) ((((1 ? 26:26) - (0 ? 26:26) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 26:26) - (0 ? 26:26) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 26:26) - (0 ? 26:26) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 26:26) - (0 ? 26:26) + 1))))))) == gcvTRUE ||
++ ((((gctUINT32) (Hardware->identity.chipMinorFeatures3)) >> (0 ? 8:8) & ((gctUINT32) ((((1 ? 8:8) - (0 ? 8:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:8) - (0 ? 8:8) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 8:8) - (0 ? 8:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:8) - (0 ? 8:8) + 1))))))) == gcvTRUE)
++ {
++ gctUINT32 data;
++
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00414,
++ &data));
++
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12)));
++
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00414,
++ data));
++ }
++#endif
++
++ /* Limit 2D outstanding request. */
++ if(Hardware->identity.chipModel == gcv880)
++ {
++ gctUINT32 axi_ot;
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00414, &axi_ot));
++ axi_ot = (axi_ot & (~0xFF)) | 0x10;
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00414, axi_ot));
++ }
++
++ if (Hardware->identity.chip2DControl & 0xFF)
++ {
++ gctUINT32 data;
++
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00414,
++ &data));
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (Hardware->identity.chip2DControl & 0xFF) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0)));
++
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00414,
++ data));
++ }
++
++ /* Update GPU AXI cache atttribute. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00008,
++ 0x00002200));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the error. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_QueryMemory
++**
++** Query the amount of memory available on the hardware.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to the gckHARDWARE object.
++**
++** OUTPUT:
++**
++** gctSIZE_T * InternalSize
++** Pointer to a variable that will hold the size of the internal video
++** memory in bytes. If 'InternalSize' is gcvNULL, no information of the
++** internal memory will be returned.
++**
++** gctUINT32 * InternalBaseAddress
++** Pointer to a variable that will hold the hardware's base address for
++** the internal video memory. This pointer cannot be gcvNULL if
++** 'InternalSize' is also non-gcvNULL.
++**
++** gctUINT32 * InternalAlignment
++** Pointer to a variable that will hold the hardware's base address for
++** the internal video memory. This pointer cannot be gcvNULL if
++** 'InternalSize' is also non-gcvNULL.
++**
++** gctSIZE_T * ExternalSize
++** Pointer to a variable that will hold the size of the external video
++** memory in bytes. If 'ExternalSize' is gcvNULL, no information of the
++** external memory will be returned.
++**
++** gctUINT32 * ExternalBaseAddress
++** Pointer to a variable that will hold the hardware's base address for
++** the external video memory. This pointer cannot be gcvNULL if
++** 'ExternalSize' is also non-gcvNULL.
++**
++** gctUINT32 * ExternalAlignment
++** Pointer to a variable that will hold the hardware's base address for
++** the external video memory. This pointer cannot be gcvNULL if
++** 'ExternalSize' is also non-gcvNULL.
++**
++** gctUINT32 * HorizontalTileSize
++** Number of horizontal pixels per tile. If 'HorizontalTileSize' is
++** gcvNULL, no horizontal pixel per tile will be returned.
++**
++** gctUINT32 * VerticalTileSize
++** Number of vertical pixels per tile. If 'VerticalTileSize' is
++** gcvNULL, no vertical pixel per tile will be returned.
++*/
++gceSTATUS
++gckHARDWARE_QueryMemory(
++ IN gckHARDWARE Hardware,
++ OUT gctSIZE_T * InternalSize,
++ OUT gctUINT32 * InternalBaseAddress,
++ OUT gctUINT32 * InternalAlignment,
++ OUT gctSIZE_T * ExternalSize,
++ OUT gctUINT32 * ExternalBaseAddress,
++ OUT gctUINT32 * ExternalAlignment,
++ OUT gctUINT32 * HorizontalTileSize,
++ OUT gctUINT32 * VerticalTileSize
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ if (InternalSize != gcvNULL)
++ {
++ /* No internal memory. */
++ *InternalSize = 0;
++ }
++
++ if (ExternalSize != gcvNULL)
++ {
++ /* No external memory. */
++ *ExternalSize = 0;
++ }
++
++ if (HorizontalTileSize != gcvNULL)
++ {
++ /* 4x4 tiles. */
++ *HorizontalTileSize = 4;
++ }
++
++ if (VerticalTileSize != gcvNULL)
++ {
++ /* 4x4 tiles. */
++ *VerticalTileSize = 4;
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*InternalSize=%lu *InternalBaseAddress=0x%08x "
++ "*InternalAlignment=0x%08x *ExternalSize=%lu "
++ "*ExternalBaseAddress=0x%08x *ExtenalAlignment=0x%08x "
++ "*HorizontalTileSize=%u *VerticalTileSize=%u",
++ gcmOPT_VALUE(InternalSize),
++ gcmOPT_VALUE(InternalBaseAddress),
++ gcmOPT_VALUE(InternalAlignment),
++ gcmOPT_VALUE(ExternalSize),
++ gcmOPT_VALUE(ExternalBaseAddress),
++ gcmOPT_VALUE(ExternalAlignment),
++ gcmOPT_VALUE(HorizontalTileSize),
++ gcmOPT_VALUE(VerticalTileSize));
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_QueryChipIdentity
++**
++** Query the identity of the hardware.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to the gckHARDWARE object.
++**
++** OUTPUT:
++**
++** gcsHAL_QUERY_CHIP_IDENTITY_PTR Identity
++** Pointer to the identity structure.
++**
++*/
++gceSTATUS
++gckHARDWARE_QueryChipIdentity(
++ IN gckHARDWARE Hardware,
++ OUT gcsHAL_QUERY_CHIP_IDENTITY_PTR Identity
++ )
++{
++ gctUINT32 features;
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(Identity != gcvNULL);
++
++ /* Return chip model and revision. */
++ Identity->chipModel = Hardware->identity.chipModel;
++ Identity->chipRevision = Hardware->identity.chipRevision;
++
++ /* Return feature set. */
++ features = Hardware->identity.chipFeatures;
++
++ if ((((((gctUINT32) (features)) >> (0 ? 0:0)) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1)))))) ))
++ {
++ /* Override fast clear by command line. */
++ features = ((((gctUINT32) (features)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (Hardware->allowFastClear) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)));
++ }
++
++ if ((((((gctUINT32) (features)) >> (0 ? 5:5)) & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1)))))) ))
++ {
++ /* Override compression by command line. */
++ features = ((((gctUINT32) (features)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))) | (((gctUINT32) ((gctUINT32) (Hardware->allowCompression) & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5)));
++ }
++
++ /* Mark 2D pipe as available for GC500.0 through GC500.2 and GC300,
++ ** since they did not have this bit. */
++ if (((Hardware->identity.chipModel == gcv500) && (Hardware->identity.chipRevision <= 2))
++ || (Hardware->identity.chipModel == gcv300)
++ )
++ {
++ features = ((((gctUINT32) (features)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9)));
++ }
++
++ Identity->chipFeatures = features;
++
++ /* Return minor features. */
++ Identity->chipMinorFeatures = Hardware->identity.chipMinorFeatures;
++ Identity->chipMinorFeatures1 = Hardware->identity.chipMinorFeatures1;
++ Identity->chipMinorFeatures2 = Hardware->identity.chipMinorFeatures2;
++ Identity->chipMinorFeatures3 = Hardware->identity.chipMinorFeatures3;
++ Identity->chipMinorFeatures4 = Hardware->identity.chipMinorFeatures4;
++
++ /* Return chip specs. */
++ Identity->streamCount = Hardware->identity.streamCount;
++ Identity->registerMax = Hardware->identity.registerMax;
++ Identity->threadCount = Hardware->identity.threadCount;
++ Identity->shaderCoreCount = Hardware->identity.shaderCoreCount;
++ Identity->vertexCacheSize = Hardware->identity.vertexCacheSize;
++ Identity->vertexOutputBufferSize = Hardware->identity.vertexOutputBufferSize;
++ Identity->pixelPipes = Hardware->identity.pixelPipes;
++ Identity->instructionCount = Hardware->identity.instructionCount;
++ Identity->numConstants = Hardware->identity.numConstants;
++ Identity->bufferSize = Hardware->identity.bufferSize;
++ Identity->varyingsCount = Hardware->identity.varyingsCount;
++ Identity->superTileMode = Hardware->identity.superTileMode;
++ Identity->chip2DControl = Hardware->identity.chip2DControl;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_SplitMemory
++**
++** Split a hardware specific memory address into a pool and offset.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to the gckHARDWARE object.
++**
++** gctUINT32 Address
++** Address in hardware specific format.
++**
++** OUTPUT:
++**
++** gcePOOL * Pool
++** Pointer to a variable that will hold the pool type for the address.
++**
++** gctUINT32 * Offset
++** Pointer to a variable that will hold the offset for the address.
++*/
++gceSTATUS
++gckHARDWARE_SplitMemory(
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 Address,
++ OUT gcePOOL * Pool,
++ OUT gctUINT32 * Offset
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x Addres=0x%08x", Hardware, Address);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(Pool != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Offset != gcvNULL);
++
++ if (Hardware->mmuVersion == 0)
++ {
++ /* Dispatch on memory type. */
++ switch ((((((gctUINT32) (Address)) >> (0 ? 31:31)) & ((gctUINT32) ((((1 ? 31:31) - (0 ? 31:31) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:31) - (0 ? 31:31) + 1)))))) ))
++ {
++ case 0x0:
++ /* System memory. */
++ *Pool = gcvPOOL_SYSTEM;
++ break;
++
++ case 0x1:
++ /* Virtual memory. */
++ *Pool = gcvPOOL_VIRTUAL;
++ break;
++
++ default:
++ /* Invalid memory type. */
++ gcmkFOOTER_ARG("status=%d", gcvSTATUS_INVALID_ARGUMENT);
++ return gcvSTATUS_INVALID_ARGUMENT;
++ }
++
++ /* Return offset of address. */
++ *Offset = (((((gctUINT32) (Address)) >> (0 ? 30:0)) & ((gctUINT32) ((((1 ? 30:0) - (0 ? 30:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 30:0) - (0 ? 30:0) + 1)))))) );
++ }
++ else
++ {
++ *Pool = gcvPOOL_SYSTEM;
++ *Offset = Address;
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Pool=%d *Offset=0x%08x", *Pool, *Offset);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_Execute
++**
++** Kickstart the hardware's command processor with an initialized command
++** buffer.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to the gckHARDWARE object.
++**
++** gctPOINTER Logical
++** Logical address of command buffer.
++**
++** gctSIZE_T Bytes
++** Number of bytes for the prefetch unit (until after the first LINK).
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckHARDWARE_Execute(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++#ifdef __QNXNTO__
++ IN gctPOINTER Physical,
++ IN gctBOOL PhysicalAddresses,
++#endif
++ IN gctSIZE_T Bytes
++ )
++{
++ gceSTATUS status;
++ gctUINT32 address = 0, control;
++
++ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x Bytes=%lu",
++ Hardware, Logical, Bytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++
++#ifdef __QNXNTO__
++ if (PhysicalAddresses && (Hardware->mmuVersion == 0))
++ {
++ /* Convert physical into hardware specific address. */
++ gcmkONERROR(
++ gckHARDWARE_ConvertPhysical(Hardware, Physical, &address));
++ }
++ else
++ {
++#endif
++ /* Convert logical into hardware specific address. */
++ gcmkONERROR(
++ gckHARDWARE_ConvertLogical(Hardware, Logical, &address));
++#ifdef __QNXNTO__
++ }
++#endif
++
++ /* Enable all events. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00014, ~0U));
++
++ /* Write address register. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00654, address));
++
++ /* Build control register. */
++ control = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) << (0 ? 16:16))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) << (0 ? 16:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) ((Bytes + 7) >> 3) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ /* Set big endian */
++ if (Hardware->bigEndian)
++ {
++ control |= ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 21:20) - (0 ? 21:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 21:20) - (0 ? 21:20) + 1))))))) << (0 ? 21:20))) | (((gctUINT32) (0x2 & ((gctUINT32) ((((1 ? 21:20) - (0 ? 21:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 21:20) - (0 ? 21:20) + 1))))))) << (0 ? 21:20)));
++ }
++
++ /* Write control register. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00658, control));
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Started command buffer @ 0x%08x",
++ address);
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_WaitLink
++**
++** Append a WAIT/LINK command sequence at the specified location in the command
++** queue.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to an gckHARDWARE object.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command queue to append
++** WAIT/LINK command sequence at or gcvNULL just to query the size of the
++** WAIT/LINK command sequence.
++**
++** gctUINT32 Offset
++** Offset into command buffer required for alignment.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the WAIT/LINK command
++** sequence. If 'Logical' is gcvNULL, this argument will be ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** by the WAIT/LINK command sequence. If 'Bytes' is gcvNULL, nothing will
++** be returned.
++**
++** gctUINT32 * WaitOffset
++** Pointer to a variable that will receive the offset of the WAIT command
++** from the specified logcial pointer.
++** If 'WaitOffset' is gcvNULL nothing will be returned.
++**
++** gctSIZE_T * WaitSize
++** Pointer to a variable that will receive the number of bytes used by
++** the WAIT command. If 'LinkSize' is gcvNULL nothing will be returned.
++*/
++gceSTATUS
++gckHARDWARE_WaitLink(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Offset,
++ IN OUT gctSIZE_T * Bytes,
++ OUT gctUINT32 * WaitOffset,
++ OUT gctSIZE_T * WaitSize
++ )
++{
++ static const gctUINT waitCount = 200;
++
++ gceSTATUS status;
++ gctUINT32 address;
++ gctUINT32_PTR logical;
++ gctSIZE_T bytes;
++
++ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x Offset=0x%08x *Bytes=%lu",
++ Hardware, Logical, Offset, gcmOPT_VALUE(Bytes));
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT((Logical != gcvNULL) || (Bytes != gcvNULL));
++
++ /* Compute number of bytes required. */
++#if gcd6000_SUPPORT
++ bytes = gcmALIGN(Offset + 96, 8) - Offset;
++#else
++ bytes = gcmALIGN(Offset + 16, 8) - Offset;
++#endif
++
++ /* Cast the input pointer. */
++ logical = (gctUINT32_PTR) Logical;
++
++ if (logical != gcvNULL)
++ {
++ /* Not enough space? */
++ if (*Bytes < bytes)
++ {
++ /* Command queue too small. */
++ gcmkONERROR(gcvSTATUS_BUFFER_TOO_SMALL);
++ }
++
++ /* Convert logical into hardware specific address. */
++ gcmkONERROR(gckHARDWARE_ConvertLogical(Hardware, logical, &address));
++
++ /* Store the WAIT/LINK address. */
++ Hardware->lastWaitLink = address;
++
++ /* Append WAIT(count). */
++ logical[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (waitCount) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++#if gcd6000_SUPPORT
++ /* Send FE-PE sempahore token. */
++ logical[2]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ logical[3]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /* Send FE-PE stall token. */
++ logical[4]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++
++ logical[5]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /*************************************************************/
++ /* Enable chip ID 0. */
++ logical[6] =
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x0D & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | (1 << 0);
++
++ /* Send semaphore from FE to ChipID 1. */
++ logical[8] =
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ logical[9] =
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x0F & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 27:24) - (0 ? 27:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:24) - (0 ? 27:24) + 1))))))) << (0 ? 27:24))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 27:24) - (0 ? 27:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:24) - (0 ? 27:24) + 1))))))) << (0 ? 27:24)));
++
++ /* Send semaphore from FE to ChipID 1. */
++ logical[10] =
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++
++ logical[11] =
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x0F & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 27:24) - (0 ? 27:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:24) - (0 ? 27:24) + 1))))))) << (0 ? 27:24))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 27:24) - (0 ? 27:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:24) - (0 ? 27:24) + 1))))))) << (0 ? 27:24)));
++
++ /*************************************************************/
++ /* Enable chip ID 1. */
++ logical[12] =
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x0D & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | (1 << 1);
++
++ /* Send semaphore from FE to ChipID 1. */
++ logical[14] =
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ logical[15] =
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x0F & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 27:24) - (0 ? 27:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:24) - (0 ? 27:24) + 1))))))) << (0 ? 27:24))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 27:24) - (0 ? 27:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:24) - (0 ? 27:24) + 1))))))) << (0 ? 27:24)));
++
++ /* Wait for semaphore from ChipID 0. */
++ logical[16] =
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++
++ logical[17] =
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x0F & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 27:24) - (0 ? 27:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:24) - (0 ? 27:24) + 1))))))) << (0 ? 27:24))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 27:24) - (0 ? 27:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:24) - (0 ? 27:24) + 1))))))) << (0 ? 27:24)));
++
++ /*************************************************************/
++ /* Enable all chips. */
++ logical[18] =
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x0D & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | (0xFFFF);
++
++ /* LoadState(AQFlush, 1), flush. */
++ logical[20]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E03) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ logical[21]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6)));
++
++ /* Append LINK(2, address). */
++ logical[22]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x08 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (bytes >> 3) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ logical[23] = address;
++#else
++ /* Append LINK(2, address). */
++ logical[2]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x08 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (bytes >> 3) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ logical[3] = address;
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "0x%08x: WAIT %u", address, waitCount
++ );
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "0x%08x: LINK 0x%08x, #%lu",
++ address + 8, address, bytes
++ );
++#endif
++
++ if (WaitOffset != gcvNULL)
++ {
++ /* Return the offset pointer to WAIT command. */
++ *WaitOffset = 0;
++ }
++
++ if (WaitSize != gcvNULL)
++ {
++ /* Return number of bytes used by the WAIT command. */
++ *WaitSize = 8;
++ }
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the WAIT/LINK command
++ ** sequence. */
++ *Bytes = bytes;
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Bytes=%lu *WaitOffset=0x%x *WaitSize=%lu",
++ gcmOPT_VALUE(Bytes), gcmOPT_VALUE(WaitOffset),
++ gcmOPT_VALUE(WaitSize));
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_End
++**
++** Append an END command at the specified location in the command queue.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to an gckHARDWARE object.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command queue to append
++** END command at or gcvNULL just to query the size of the END command.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the END command. If
++** 'Logical' is gcvNULL, this argument will be ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** for the END command. If 'Bytes' is gcvNULL, nothing will be returned.
++*/
++gceSTATUS
++gckHARDWARE_End(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN OUT gctSIZE_T * Bytes
++ )
++{
++ gctUINT32_PTR logical = (gctUINT32_PTR) Logical;
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x *Bytes=%lu",
++ Hardware, Logical, gcmOPT_VALUE(Bytes));
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT((Logical == gcvNULL) || (Bytes != gcvNULL));
++
++ if (Logical != gcvNULL)
++ {
++ if (*Bytes < 8)
++ {
++ /* Command queue too small. */
++ gcmkONERROR(gcvSTATUS_BUFFER_TOO_SMALL);
++ }
++
++ /* Append END. */
++ logical[0] =
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x02 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, "0x%x: END", Logical);
++
++ /* Make sure the CPU writes out the data to memory. */
++ gcmkONERROR(
++ gckOS_MemoryBarrier(Hardware->os, Logical));
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the END command. */
++ *Bytes = 8;
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Bytes=%lu", gcmOPT_VALUE(Bytes));
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_Nop
++**
++** Append a NOP command at the specified location in the command queue.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to an gckHARDWARE object.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command queue to append
++** NOP command at or gcvNULL just to query the size of the NOP command.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the NOP command. If
++** 'Logical' is gcvNULL, this argument will be ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** for the NOP command. If 'Bytes' is gcvNULL, nothing will be returned.
++*/
++gceSTATUS
++gckHARDWARE_Nop(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN OUT gctSIZE_T * Bytes
++ )
++{
++ gctUINT32_PTR logical = (gctUINT32_PTR) Logical;
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x *Bytes=%lu",
++ Hardware, Logical, gcmOPT_VALUE(Bytes));
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT((Logical == gcvNULL) || (Bytes != gcvNULL));
++
++ if (Logical != gcvNULL)
++ {
++ if (*Bytes < 8)
++ {
++ /* Command queue too small. */
++ gcmkONERROR(gcvSTATUS_BUFFER_TOO_SMALL);
++ }
++
++ /* Append NOP. */
++ logical[0] = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x03 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, "0x%x: NOP", Logical);
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the NOP command. */
++ *Bytes = 8;
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Bytes=%lu", gcmOPT_VALUE(Bytes));
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_Wait
++**
++** Append a WAIT command at the specified location in the command queue.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to an gckHARDWARE object.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command queue to append
++** WAIT command at or gcvNULL just to query the size of the WAIT command.
++**
++** gctUINT32 Count
++** Number of cycles to wait.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the WAIT command. If
++** 'Logical' is gcvNULL, this argument will be ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** for the NOP command. If 'Bytes' is gcvNULL, nothing will be returned.
++*/
++gceSTATUS
++gckHARDWARE_Wait(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Count,
++ IN OUT gctSIZE_T * Bytes
++ )
++{
++ gceSTATUS status;
++ gctUINT32_PTR logical;
++
++ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x Count=%u *Bytes=%lu",
++ Hardware, Logical, Count, gcmOPT_VALUE(Bytes));
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT((Logical == gcvNULL) || (Bytes != gcvNULL));
++
++ /* Cast the input pointer. */
++ logical = (gctUINT32_PTR) Logical;
++
++ if (Logical != gcvNULL)
++ {
++ if (*Bytes < 8)
++ {
++ /* Command queue too small. */
++ gcmkONERROR(gcvSTATUS_BUFFER_TOO_SMALL);
++ }
++
++ /* Append WAIT. */
++ logical[0] = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (Count) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++ {
++ gctUINT32 address;
++
++ /* Convert logical into hardware specific address. */
++ gcmkONERROR(gckHARDWARE_ConvertLogical(
++ Hardware, logical, &address
++ ));
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "0x%08x: WAIT %u", address, Count
++ );
++ }
++#endif
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the WAIT command. */
++ *Bytes = 8;
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Bytes=%lu", gcmOPT_VALUE(Bytes));
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_Event
++**
++** Append an EVENT command at the specified location in the command queue.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to an gckHARDWARE object.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command queue to append
++** the EVENT command at or gcvNULL just to query the size of the EVENT
++** command.
++**
++** gctUINT8 Event
++** Event ID to program.
++**
++** gceKERNEL_WHERE FromWhere
++** Location of the pipe to send the event.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the EVENT command. If
++** 'Logical' is gcvNULL, this argument will be ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** for the EVENT command. If 'Bytes' is gcvNULL, nothing will be
++** returned.
++*/
++gceSTATUS
++gckHARDWARE_Event(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN gctUINT8 Event,
++ IN gceKERNEL_WHERE FromWhere,
++ IN OUT gctSIZE_T * Bytes
++ )
++{
++ gctUINT size;
++ gctUINT32 destination = 0;
++ gctUINT32_PTR logical = (gctUINT32_PTR) Logical;
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x Event=%u FromWhere=%d *Bytes=%lu",
++ Hardware, Logical, Event, FromWhere, gcmOPT_VALUE(Bytes));
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT((Logical == gcvNULL) || (Bytes != gcvNULL));
++ gcmkVERIFY_ARGUMENT(Event < 32);
++
++ /* Determine the size of the command. */
++
++ size = (Hardware->extraEventStates && (FromWhere == gcvKERNEL_PIXEL))
++ ? gcmALIGN(8 + (1 + 5) * 4, 8) /* EVENT + 5 STATES */
++ : 8;
++
++ if (Logical != gcvNULL)
++ {
++ if (*Bytes < size)
++ {
++ /* Command queue too small. */
++ gcmkONERROR(gcvSTATUS_BUFFER_TOO_SMALL);
++ }
++
++ switch (FromWhere)
++ {
++ case gcvKERNEL_COMMAND:
++ /* From command processor. */
++ destination = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5)));
++ break;
++
++ case gcvKERNEL_PIXEL:
++ /* From pixel engine. */
++ destination = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6)));
++ break;
++
++ default:
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ /* Append EVENT(Event, destiantion). */
++ logical[0] = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E01) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ logical[1] = ((((gctUINT32) (destination)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) ((gctUINT32) (Event) & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)));
++
++ /* Make sure the event ID gets written out before GPU can access it. */
++ gcmkONERROR(
++ gckOS_MemoryBarrier(Hardware->os, logical + 1));
++
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++ {
++ gctUINT32 phys;
++ gckOS_GetPhysicalAddress(Hardware->os, Logical, &phys);
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "0x%08x: EVENT %d", phys, Event);
++ }
++#endif
++
++ /* Append the extra states. These are needed for the chips that do not
++ ** support back-to-back events due to the async interface. The extra
++ ** states add the necessary delay to ensure that event IDs do not
++ ** collide. */
++ if (size > 8)
++ {
++ logical[2] = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0100) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (5) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++ logical[3] = 0;
++ logical[4] = 0;
++ logical[5] = 0;
++ logical[6] = 0;
++ logical[7] = 0;
++ }
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the EVENT command. */
++ *Bytes = size;
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Bytes=%lu", gcmOPT_VALUE(Bytes));
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_PipeSelect
++**
++** Append a PIPESELECT command at the specified location in the command queue.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to an gckHARDWARE object.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command queue to append
++** the PIPESELECT command at or gcvNULL just to query the size of the
++** PIPESELECT command.
++**
++** gcePIPE_SELECT Pipe
++** Pipe value to select.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the PIPESELECT command.
++** If 'Logical' is gcvNULL, this argument will be ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** for the PIPESELECT command. If 'Bytes' is gcvNULL, nothing will be
++** returned.
++*/
++gceSTATUS
++gckHARDWARE_PipeSelect(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN gcePIPE_SELECT Pipe,
++ IN OUT gctSIZE_T * Bytes
++ )
++{
++ gctUINT32_PTR logical = (gctUINT32_PTR) Logical;
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x Pipe=%d *Bytes=%lu",
++ Hardware, Logical, Pipe, gcmOPT_VALUE(Bytes));
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT((Logical == gcvNULL) || (Bytes != gcvNULL));
++
++ /* Append a PipeSelect. */
++ if (Logical != gcvNULL)
++ {
++ gctUINT32 flush, stall;
++
++ if (*Bytes < 32)
++ {
++ /* Command queue too small. */
++ gcmkONERROR(gcvSTATUS_BUFFER_TOO_SMALL);
++ }
++
++ flush = (Pipe == gcvPIPE_2D)
++ ? ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)))
++ : ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3)));
++
++ stall = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /* LoadState(AQFlush, 1), flush. */
++ logical[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E03) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ logical[1]
++ = flush;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "0x%x: FLUSH 0x%x", logical, flush);
++
++ /* LoadState(AQSempahore, 1), stall. */
++ logical[2]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ logical[3]
++ = stall;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "0x%x: SEMAPHORE 0x%x", logical + 2, stall);
++
++ /* Stall, stall. */
++ logical[4] = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++ logical[5] = stall;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "0x%x: STALL 0x%x", logical + 4, stall);
++
++ /* LoadState(AQPipeSelect, 1), pipe. */
++ logical[6]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E00) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ logical[7] = (Pipe == gcvPIPE_2D)
++ ? 0x1
++ : 0x0;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "0x%x: PIPE %d", logical + 6, Pipe);
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the PIPESELECT command. */
++ *Bytes = 32;
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Bytes=%lu", gcmOPT_VALUE(Bytes));
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_Link
++**
++** Append a LINK command at the specified location in the command queue.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to an gckHARDWARE object.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command queue to append
++** the LINK command at or gcvNULL just to query the size of the LINK
++** command.
++**
++** gctPOINTER FetchAddress
++** Logical address of destination of LINK.
++**
++** gctSIZE_T FetchSize
++** Number of bytes in destination of LINK.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the LINK command. If
++** 'Logical' is gcvNULL, this argument will be ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** for the LINK command. If 'Bytes' is gcvNULL, nothing will be returned.
++*/
++gceSTATUS
++gckHARDWARE_Link(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN gctPOINTER FetchAddress,
++ IN gctSIZE_T FetchSize,
++ IN OUT gctSIZE_T * Bytes
++ )
++{
++ gceSTATUS status;
++ gctSIZE_T bytes;
++ gctUINT32 address;
++ gctUINT32 link;
++ gctUINT32_PTR logical = (gctUINT32_PTR) Logical;
++
++ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x FetchAddress=0x%x FetchSize=%lu "
++ "*Bytes=%lu",
++ Hardware, Logical, FetchAddress, FetchSize,
++ gcmOPT_VALUE(Bytes));
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT((Logical == gcvNULL) || (Bytes != gcvNULL));
++
++ if (Logical != gcvNULL)
++ {
++ if (*Bytes < 8)
++ {
++ /* Command queue too small. */
++ gcmkONERROR(gcvSTATUS_BUFFER_TOO_SMALL);
++ }
++
++ /* Convert logical address to hardware address. */
++ gcmkONERROR(
++ gckHARDWARE_ConvertLogical(Hardware, FetchAddress, &address));
++
++ gcmkONERROR(
++ gckOS_WriteMemory(Hardware->os, logical + 1, address));
++
++ /* Make sure the address got written before the LINK command. */
++ gcmkONERROR(
++ gckOS_MemoryBarrier(Hardware->os, logical + 1));
++
++ /* Compute number of 64-byte aligned bytes to fetch. */
++ bytes = gcmALIGN(address + FetchSize, 8) - address;
++
++ /* Append LINK(bytes / 8), FetchAddress. */
++ link = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x08 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (bytes >> 3) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ gcmkONERROR(
++ gckOS_WriteMemory(Hardware->os, logical, link));
++
++ /* Memory barrier. */
++ gcmkONERROR(
++ gckOS_MemoryBarrier(Hardware->os, logical));
++
++#if gcdLINK_QUEUE_SIZE && gcdVIRTUAL_COMMAND_BUFFER
++ if (address >= 0x80000000)
++ {
++ gckLINKQUEUE_Enqueue(&Hardware->linkQueue, address, address + bytes);
++ }
++#endif
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the LINK command. */
++ *Bytes = 8;
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Bytes=%lu", gcmOPT_VALUE(Bytes));
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_UpdateQueueTail
++**
++** Update the tail of the command queue.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to an gckHARDWARE object.
++**
++** gctPOINTER Logical
++** Logical address of the start of the command queue.
++**
++** gctUINT32 Offset
++** Offset into the command queue of the tail (last command).
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckHARDWARE_UpdateQueueTail(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Offset
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x Offset=0x%08x",
++ Hardware, Logical, Offset);
++
++ /* Verify the hardware. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Force a barrier. */
++ gcmkONERROR(
++ gckOS_MemoryBarrier(Hardware->os, Logical));
++
++ /* Notify gckKERNEL object of change. */
++ gcmkONERROR(
++ gckKERNEL_Notify(Hardware->kernel,
++ gcvNOTIFY_COMMAND_QUEUE,
++ gcvFALSE));
++
++ if (status == gcvSTATUS_CHIP_NOT_READY)
++ {
++ gcmkONERROR(gcvSTATUS_GPU_NOT_RESPONDING);
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_ConvertLogical
++**
++** Convert a logical system address into a hardware specific address.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to an gckHARDWARE object.
++**
++** gctPOINTER Logical
++** Logical address to convert.
++**
++** gctUINT32* Address
++** Return hardware specific address.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckHARDWARE_ConvertLogical(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ OUT gctUINT32 * Address
++ )
++{
++ gctUINT32 address;
++ gceSTATUS status;
++ gctUINT32 baseAddress;
++
++ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x", Hardware, Logical);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Address != gcvNULL);
++
++#if gcdVIRTUAL_COMMAND_BUFFER
++ status = gckKERNEL_GetGPUAddress(Hardware->kernel, Logical, Address);
++
++ if (status == gcvSTATUS_INVALID_ADDRESS)
++#endif
++ {
++ /* Convert logical address into a physical address. */
++ gcmkONERROR(
++ gckOS_GetPhysicalAddress(Hardware->os, Logical, &address));
++
++ /* For old MMU, get GPU address according to baseAddress. */
++ if (Hardware->mmuVersion == 0)
++ {
++ gcmkONERROR(gckOS_GetBaseAddress(Hardware->os, &baseAddress));
++
++ /* Subtract base address to get a GPU address. */
++ gcmkASSERT(address >= baseAddress);
++ address -= baseAddress;
++ }
++
++ /* Return hardware specific address. */
++ *Address = (Hardware->mmuVersion == 0)
++ ? ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:31) - (0 ? 31:31) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:31) - (0 ? 31:31) + 1))))))) << (0 ? 31:31))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 31:31) - (0 ? 31:31) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:31) - (0 ? 31:31) + 1))))))) << (0 ? 31:31)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 30:0) - (0 ? 30:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 30:0) - (0 ? 30:0) + 1))))))) << (0 ? 30:0))) | (((gctUINT32) ((gctUINT32) (address) & ((gctUINT32) ((((1 ? 30:0) - (0 ? 30:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 30:0) - (0 ? 30:0) + 1))))))) << (0 ? 30:0)))
++ : address;
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Address=0x%08x", *Address);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_ConvertPhysical
++**
++** Convert a physical address into a hardware specific address.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to an gckHARDWARE object.
++**
++** gctPHYS_ADDR Physical
++** Physical address to convert.
++**
++** gctUINT32* Address
++** Return hardware specific address.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckHARDWARE_ConvertPhysical(
++ IN gckHARDWARE Hardware,
++ IN gctPHYS_ADDR Physical,
++ OUT gctUINT32 * Address
++ )
++{
++ gctUINT32 address;
++ gctUINT32 baseAddress;
++
++ gcmkHEADER_ARG("Hardware=0x%x Physical=0x%x", Hardware, Physical);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(Physical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Address != gcvNULL);
++
++ address = gcmPTR2INT(Physical);
++
++ /* For old MMU, get GPU address according to baseAddress. */
++ if (Hardware->mmuVersion == 0)
++ {
++ gcmkVERIFY_OK(gckOS_GetBaseAddress(Hardware->os, &baseAddress));
++
++ /* Subtract base address to get a GPU address. */
++ gcmkASSERT(address >= baseAddress);
++ address -= baseAddress;
++ }
++
++ /* Return hardware specific address. */
++ *Address = (Hardware->mmuVersion == 0)
++ ? ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:31) - (0 ? 31:31) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:31) - (0 ? 31:31) + 1))))))) << (0 ? 31:31))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 31:31) - (0 ? 31:31) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:31) - (0 ? 31:31) + 1))))))) << (0 ? 31:31)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 30:0) - (0 ? 30:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 30:0) - (0 ? 30:0) + 1))))))) << (0 ? 30:0))) | (((gctUINT32) ((gctUINT32) (address) & ((gctUINT32) ((((1 ? 30:0) - (0 ? 30:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 30:0) - (0 ? 30:0) + 1))))))) << (0 ? 30:0)))
++ : address;
++
++ /* Return the status. */
++ gcmkFOOTER_ARG("*Address=0x%08x", *Address);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_Interrupt
++**
++** Process an interrupt.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to an gckHARDWARE object.
++**
++** gctBOOL InterruptValid
++** If gcvTRUE, this function will read the interrupt acknowledge
++** register, stores the data, and return whether or not the interrupt
++** is ours or not. If gcvFALSE, this functions will read the interrupt
++** acknowledge register and combine it with any stored value to handle
++** the event notifications.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckHARDWARE_Interrupt(
++ IN gckHARDWARE Hardware,
++ IN gctBOOL InterruptValid
++ )
++{
++ gckEVENT eventObj;
++ gctUINT32 data;
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Hardware=0x%x InterruptValid=%d", Hardware, InterruptValid);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Extract gckEVENT object. */
++ eventObj = Hardware->kernel->eventObj;
++ gcmkVERIFY_OBJECT(eventObj, gcvOBJ_EVENT);
++
++ if (InterruptValid)
++ {
++ /* Read AQIntrAcknowledge register. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00010,
++ &data));
++
++ if (data == 0)
++ {
++ /* Not our interrupt. */
++ status = gcvSTATUS_NOT_OUR_INTERRUPT;
++ }
++ else
++ {
++ /* Inform gckEVENT of the interrupt. */
++ status = gckEVENT_Interrupt(eventObj, data);
++ }
++ }
++ else
++ {
++ /* Handle events. */
++ status = gckEVENT_Notify(eventObj, 0);
++ }
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_QueryCommandBuffer
++**
++** Query the command buffer alignment and number of reserved bytes.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Alignment
++** Pointer to a variable receiving the alignment for each command.
++**
++** gctSIZE_T * ReservedHead
++** Pointer to a variable receiving the number of reserved bytes at the
++** head of each command buffer.
++**
++** gctSIZE_T * ReservedTail
++** Pointer to a variable receiving the number of bytes reserved at the
++** tail of each command buffer.
++*/
++gceSTATUS
++gckHARDWARE_QueryCommandBuffer(
++ IN gckHARDWARE Hardware,
++ OUT gctSIZE_T * Alignment,
++ OUT gctSIZE_T * ReservedHead,
++ OUT gctSIZE_T * ReservedTail
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ if (Alignment != gcvNULL)
++ {
++ /* Align every 8 bytes. */
++ *Alignment = 8;
++ }
++
++ if (ReservedHead != gcvNULL)
++ {
++ /* Reserve space for SelectPipe(). */
++ *ReservedHead = 32;
++ }
++
++ if (ReservedTail != gcvNULL)
++ {
++ /* Reserve space for Link(). */
++ *ReservedTail = 8;
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Alignment=%lu *ReservedHead=%lu *ReservedTail=%lu",
++ gcmOPT_VALUE(Alignment), gcmOPT_VALUE(ReservedHead),
++ gcmOPT_VALUE(ReservedTail));
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_QuerySystemMemory
++**
++** Query the command buffer alignment and number of reserved bytes.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** OUTPUT:
++**
++** gctSIZE_T * SystemSize
++** Pointer to a variable that receives the maximum size of the system
++** memory.
++**
++** gctUINT32 * SystemBaseAddress
++** Poinetr to a variable that receives the base address for system
++** memory.
++*/
++gceSTATUS
++gckHARDWARE_QuerySystemMemory(
++ IN gckHARDWARE Hardware,
++ OUT gctSIZE_T * SystemSize,
++ OUT gctUINT32 * SystemBaseAddress
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ if (SystemSize != gcvNULL)
++ {
++ /* Maximum system memory can be 2GB. */
++ *SystemSize = 1U << 31;
++ }
++
++ if (SystemBaseAddress != gcvNULL)
++ {
++ /* Set system memory base address. */
++ *SystemBaseAddress = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:31) - (0 ? 31:31) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:31) - (0 ? 31:31) + 1))))))) << (0 ? 31:31))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 31:31) - (0 ? 31:31) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:31) - (0 ? 31:31) + 1))))))) << (0 ? 31:31)));
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*SystemSize=%lu *SystemBaseAddress=%lu",
++ gcmOPT_VALUE(SystemSize), gcmOPT_VALUE(SystemBaseAddress));
++ return gcvSTATUS_OK;
++}
++
++#ifndef VIVANTE_NO_3D
++/*******************************************************************************
++**
++** gckHARDWARE_QueryShaderCaps
++**
++** Query the shader capabilities.
++**
++** INPUT:
++**
++** Nothing.
++**
++** OUTPUT:
++**
++** gctUINT * VertexUniforms
++** Pointer to a variable receiving the number of uniforms in the vertex
++** shader.
++**
++** gctUINT * FragmentUniforms
++** Pointer to a variable receiving the number of uniforms in the
++** fragment shader.
++**
++** gctUINT * Varyings
++** Pointer to a variable receiving the maimum number of varyings.
++*/
++gceSTATUS
++gckHARDWARE_QueryShaderCaps(
++ IN gckHARDWARE Hardware,
++ OUT gctUINT * VertexUniforms,
++ OUT gctUINT * FragmentUniforms,
++ OUT gctUINT * Varyings
++ )
++{
++ gctUINT32 vsConstMax;
++ gctUINT32 psConstMax;
++
++ gcmkHEADER_ARG("Hardware=0x%x VertexUniforms=0x%x "
++ "FragmentUniforms=0x%x Varyings=0x%x",
++ Hardware, VertexUniforms,
++ FragmentUniforms, Varyings);
++
++ if ((Hardware->identity.chipModel == gcv2000)
++ && (Hardware->identity.chipRevision == 0x5118))
++ {
++ vsConstMax = 256;
++ psConstMax = 64;
++ }
++ else if (Hardware->identity.numConstants > 256)
++ {
++ vsConstMax = 256;
++ psConstMax = 256;
++ }
++ else if (Hardware->identity.numConstants == 256)
++ {
++ vsConstMax = 256;
++ psConstMax = 256;
++ }
++ else
++ {
++ vsConstMax = 168;
++ psConstMax = 64;
++ }
++
++ if (VertexUniforms != gcvNULL)
++ {
++ *VertexUniforms = vsConstMax;
++ }
++
++ if (FragmentUniforms != gcvNULL)
++ {
++ *FragmentUniforms = psConstMax;
++ }
++
++ if (Varyings != gcvNULL)
++ {
++ /* Return the shader varyings count. */
++ *Varyings = Hardware->identity.varyingsCount;
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++#endif
++
++/*******************************************************************************
++**
++** gckHARDWARE_SetMMU
++**
++** Set the page table base address.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** gctPOINTER Logical
++** Logical address of the page table.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckHARDWARE_SetMMU(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical
++ )
++{
++ gceSTATUS status;
++ gctUINT32 address = 0;
++ gctUINT32 baseAddress;
++
++ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x", Hardware, Logical);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++
++ /* Convert the logical address into an hardware address. */
++ gcmkONERROR(
++ gckHARDWARE_ConvertLogical(Hardware, Logical, &address));
++
++ /* Also get the base address - we need a real physical address. */
++ gcmkONERROR(
++ gckOS_GetBaseAddress(Hardware->os, &baseAddress));
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Setting page table to 0x%08X",
++ address + baseAddress);
++
++ /* Write the AQMemoryFePageTable register. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00400,
++ address + baseAddress));
++
++ /* Write the AQMemoryRaPageTable register. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00410,
++ address + baseAddress));
++
++ /* Write the AQMemoryTxPageTable register. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00404,
++ address + baseAddress));
++
++
++ /* Write the AQMemoryPePageTable register. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00408,
++ address + baseAddress));
++
++ /* Write the AQMemoryPezPageTable register. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0040C,
++ address + baseAddress));
++
++ /* Return the status. */
++ gcmkFOOTER_NO();
++ return status;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_FlushMMU
++**
++** Flush the page table.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckHARDWARE_FlushMMU(
++ IN gckHARDWARE Hardware
++ )
++{
++ gceSTATUS status;
++ gckCOMMAND command;
++ gctUINT32_PTR buffer;
++ gctSIZE_T bufferSize;
++ gctBOOL commitEntered = gcvFALSE;
++ gctPOINTER pointer = gcvNULL;
++ gctUINT32 flushSize;
++ gctUINT32 count;
++ gctUINT32 physical;
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Verify the gckCOMMAND object pointer. */
++ command = Hardware->kernel->command;
++
++ /* Acquire the command queue. */
++ gcmkONERROR(gckCOMMAND_EnterCommit(command, gcvFALSE));
++ commitEntered = gcvTRUE;
++
++ /* Flush the memory controller. */
++ if (Hardware->mmuVersion == 0)
++ {
++ gcmkONERROR(gckCOMMAND_Reserve(
++ command, 8, &pointer, &bufferSize
++ ));
++
++ buffer = (gctUINT32_PTR) pointer;
++
++ buffer[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E04) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ buffer[1]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4)));
++
++ gcmkONERROR(gckCOMMAND_Execute(command, 8));
++ }
++ else
++ {
++ flushSize = 16 * 4;
++
++ gcmkONERROR(gckCOMMAND_Reserve(
++ command, flushSize, &pointer, &bufferSize
++ ));
++
++ buffer = (gctUINT32_PTR) pointer;
++
++ count = (bufferSize - flushSize + 7) >> 3;
++
++ gcmkONERROR(gckOS_GetPhysicalAddress(command->os, buffer, &physical));
++
++ /* Flush cache. */
++ buffer[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E03) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ buffer[1]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6)));
++
++ /* Arm the PE-FE Semaphore. */
++ buffer[2]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ buffer[3]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /* STALL FE until PE is done flushing. */
++ buffer[4]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++
++ buffer[5]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /* LINK to next slot to flush FE FIFO. */
++ buffer[6]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x08 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (4) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ buffer[7]
++ = physical + 8 * gcmSIZEOF(gctUINT32);
++
++ /* Flush MMU cache. */
++ buffer[8]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0061) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ buffer[9]
++ = (((((gctUINT32) (~0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) & ((((gctUINT32) (~0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1))))))) << (0 ? 7:7))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1))))))) << (0 ? 7:7))));
++
++ /* Arm the PE-FE Semaphore. */
++ buffer[10]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ buffer[11]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /* STALL FE until PE is done flushing. */
++ buffer[12]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++
++ buffer[13]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /* LINK to next slot to flush FE FIFO. */
++ buffer[14]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x08 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (count) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ buffer[15]
++ = physical + flushSize;
++
++ gcmkONERROR(gckCOMMAND_Execute(command, flushSize));
++ }
++
++ /* Release the command queue. */
++ gcmkONERROR(gckCOMMAND_ExitCommit(command, gcvFALSE));
++ commitEntered = gcvFALSE;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (commitEntered)
++ {
++ /* Release the command queue mutex. */
++ gcmkVERIFY_OK(gckCOMMAND_ExitCommit(Hardware->kernel->command,
++ gcvFALSE));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_SetMMUv2
++**
++** Set the page table base address.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckHARDWARE_SetMMUv2(
++ IN gckHARDWARE Hardware,
++ IN gctBOOL Enable,
++ IN gctPOINTER MtlbAddress,
++ IN gceMMU_MODE Mode,
++ IN gctPOINTER SafeAddress,
++ IN gctBOOL FromPower
++ )
++{
++ gceSTATUS status;
++ gctUINT32 config, address;
++ gckCOMMAND command;
++ gctUINT32_PTR buffer;
++ gctSIZE_T bufferSize;
++ gctBOOL commitEntered = gcvFALSE;
++ gctPOINTER pointer = gcvNULL;
++ gctBOOL acquired = gcvFALSE;
++ gctBOOL config2D;
++ gctSIZE_T configSize;
++
++ gcmkHEADER_ARG("Hardware=0x%x Enable=%d", Hardware, Enable);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ config2D = gckHARDWARE_IsFeatureAvailable(Hardware, gcvFEATURE_PIPE_3D)
++ && gckHARDWARE_IsFeatureAvailable(Hardware, gcvFEATURE_PIPE_2D);
++
++ configSize = 4 * 4;
++
++ if (config2D)
++ {
++ configSize +=
++ /* Pipe Select. */
++ 4 * 4
++ /* Configure MMU States. */
++ + 4 * 4;
++ }
++
++ /* Convert logical address into physical address. */
++ gcmkONERROR(
++ gckOS_GetPhysicalAddress(Hardware->os, MtlbAddress, &config));
++
++ gcmkONERROR(
++ gckOS_GetPhysicalAddress(Hardware->os, SafeAddress, &address));
++
++ if (address & 0x3F)
++ {
++ gcmkONERROR(gcvSTATUS_NOT_ALIGNED);
++ }
++
++ switch (Mode)
++ {
++ case gcvMMU_MODE_1K:
++ if (config & 0x3FF)
++ {
++ gcmkONERROR(gcvSTATUS_NOT_ALIGNED);
++ }
++
++ config |= ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)));
++
++ break;
++
++ case gcvMMU_MODE_4K:
++ if (config & 0xFFF)
++ {
++ gcmkONERROR(gcvSTATUS_NOT_ALIGNED);
++ }
++
++ config |= ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)));
++
++ break;
++
++ default:
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ /* Verify the gckCOMMAND object pointer. */
++ command = Hardware->kernel->command;
++
++ /* Acquire the command queue. */
++ gcmkONERROR(gckCOMMAND_EnterCommit(command, FromPower));
++ commitEntered = gcvTRUE;
++
++ gcmkONERROR(gckCOMMAND_Reserve(
++ command, configSize, &pointer, &bufferSize
++ ));
++
++ buffer = pointer;
++
++ buffer[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0061) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ buffer[1] = config;
++
++ buffer[2]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0060) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ buffer[3] = address;
++
++ if (config2D)
++ {
++ /* LoadState(AQPipeSelect, 1), pipe. */
++ buffer[4]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E00) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ buffer[5] = 0x1;
++
++ buffer[6]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0061) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ buffer[7] = config;
++
++ buffer[8]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0060) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ buffer[9] = address;
++
++ /* LoadState(AQPipeSelect, 1), pipe. */
++ buffer[10]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E00) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ buffer[11] = 0x0;
++ }
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Setup MMU: config=%08x, Safe Address=%08x\n.", config, address);
++
++ gcmkONERROR(gckCOMMAND_Execute(command, configSize));
++
++ if (FromPower == gcvFALSE)
++ {
++ /* Acquire global semaphore to suspend power management until MMU
++ ** is enabled. And acquired it before gckCOMMAND_ExitCommit to
++ ** make sure GPU keeps ON. */
++ gcmkONERROR(
++ gckOS_AcquireSemaphore(Hardware->os, Hardware->globalSemaphore));
++
++ acquired = gcvTRUE;
++ }
++
++ /* Release the command queue. */
++ gcmkONERROR(gckCOMMAND_ExitCommit(command, FromPower));
++ commitEntered = gcvFALSE;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "call gckCOMMAND_Stall to make sure the config is done.\n ");
++
++ gcmkONERROR(gckCOMMAND_Stall(command, FromPower));
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Enable MMU through GCREG_MMU_CONTROL.");
++
++ /* Enable MMU. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0018C,
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (Enable) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)))));
++
++ if (FromPower == gcvFALSE)
++ {
++ /* Relase global semaphore. */
++ gcmkVERIFY_OK(
++ gckOS_ReleaseSemaphore(Hardware->os, Hardware->globalSemaphore));
++
++ acquired = gcvFALSE;
++ }
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "call gckCOMMAND_Stall to check MMU available.\n");
++
++ gcmkONERROR(gckCOMMAND_Stall(command, FromPower));
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "The MMU is available.\n");
++
++ /* Return the status. */
++ gcmkFOOTER_NO();
++ return status;
++
++OnError:
++ if (commitEntered)
++ {
++ /* Release the command queue mutex. */
++ gcmkVERIFY_OK(gckCOMMAND_ExitCommit(Hardware->kernel->command,
++ FromPower));
++ }
++
++ if (acquired)
++ {
++ gcmkVERIFY_OK(
++ gckOS_ReleaseSemaphore(Hardware->os, Hardware->globalSemaphore));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_BuildVirtualAddress
++**
++** Build a virtual address.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** gctUINT32 Index
++** Index into page table.
++**
++** gctUINT32 Offset
++** Offset into page.
++**
++** OUTPUT:
++**
++** gctUINT32 * Address
++** Pointer to a variable receiving te hardware address.
++*/
++gceSTATUS
++gckHARDWARE_BuildVirtualAddress(
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 Index,
++ IN gctUINT32 Offset,
++ OUT gctUINT32 * Address
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x Index=%u Offset=%u", Hardware, Index, Offset);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(Address != gcvNULL);
++
++ /* Build virtual address. */
++ *Address = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:31) - (0 ? 31:31) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:31) - (0 ? 31:31) + 1))))))) << (0 ? 31:31))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 31:31) - (0 ? 31:31) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:31) - (0 ? 31:31) + 1))))))) << (0 ? 31:31)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 30:0) - (0 ? 30:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 30:0) - (0 ? 30:0) + 1))))))) << (0 ? 30:0))) | (((gctUINT32) ((gctUINT32) (Offset | (Index << 12)) & ((gctUINT32) ((((1 ? 30:0) - (0 ? 30:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 30:0) - (0 ? 30:0) + 1))))))) << (0 ? 30:0)));
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Address=0x%08x", *Address);
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckHARDWARE_GetIdle(
++ IN gckHARDWARE Hardware,
++ IN gctBOOL Wait,
++ OUT gctUINT32 * Data
++ )
++{
++ gceSTATUS status;
++ gctUINT32 idle = 0;
++ gctINT retry, poll, pollCount;
++
++ gcmkHEADER_ARG("Hardware=0x%x Wait=%d", Hardware, Wait);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(Data != gcvNULL);
++
++
++ /* If we have to wait, try 100 polls per millisecond. */
++ pollCount = Wait ? 100 : 1;
++
++ /* At most, try for 1 second. */
++ for (retry = 0; retry < 1000; ++retry)
++ {
++ /* If we have to wait, try 100 polls per millisecond. */
++ for (poll = pollCount; poll > 0; --poll)
++ {
++ /* Read register. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00004, &idle));
++
++ /* See if we have to wait for FE idle. */
++ if ((((((gctUINT32) (idle)) >> (0 ? 0:0)) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1)))))) ))
++ {
++ /* FE is idle. */
++ break;
++ }
++ }
++
++ /* Check if we need to wait for FE and FE is busy. */
++ if (Wait && !(((((gctUINT32) (idle)) >> (0 ? 0:0)) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1)))))) ))
++ {
++ /* Wait a little. */
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "%s: Waiting for idle: 0x%08X",
++ __FUNCTION__, idle);
++
++ gcmkVERIFY_OK(gckOS_Delay(Hardware->os, 1));
++ }
++ else
++ {
++ break;
++ }
++ }
++
++ /* Return idle to caller. */
++ *Data = idle;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Data=0x%08x", *Data);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/* Flush the caches. */
++gceSTATUS
++gckHARDWARE_Flush(
++ IN gckHARDWARE Hardware,
++ IN gceKERNEL_FLUSH Flush,
++ IN gctPOINTER Logical,
++ IN OUT gctSIZE_T * Bytes
++ )
++{
++ gctUINT32 pipe;
++ gctUINT32 flush = 0;
++ gctUINT32_PTR logical = (gctUINT32_PTR) Logical;
++ gceSTATUS status;
++ gctBOOL fcFlushStall;
++ gctUINT32 reserveBytes = 8;
++
++ gcmkHEADER_ARG("Hardware=0x%x Flush=0x%x Logical=0x%x *Bytes=%lu",
++ Hardware, Flush, Logical, gcmOPT_VALUE(Bytes));
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Get current pipe. */
++ pipe = Hardware->kernel->command->pipeSelect;
++
++ fcFlushStall
++ = ((((gctUINT32) (Hardware->identity.chipMinorFeatures1)) >> (0 ? 31:31) & ((gctUINT32) ((((1 ? 31:31) - (0 ? 31:31) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:31) - (0 ? 31:31) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 31:31) - (0 ? 31:31) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:31) - (0 ? 31:31) + 1)))))))
++ && (Flush == gcvFLUSH_ALL)
++ ;
++
++ if (fcFlushStall)
++ {
++ reserveBytes += 8;
++ }
++
++ /* Flush 3D color cache. */
++ if ((Flush & gcvFLUSH_COLOR) && (pipe == 0x0))
++ {
++ flush |= ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1)));
++ }
++
++ /* Flush 3D depth cache. */
++ if ((Flush & gcvFLUSH_DEPTH) && (pipe == 0x0))
++ {
++ flush |= ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)));
++ }
++
++ /* Flush 3D texture cache. */
++ if ((Flush & gcvFLUSH_TEXTURE) && (pipe == 0x0))
++ {
++ flush |= ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2)));
++ flush |= ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4)));
++ }
++
++ /* Flush 2D cache. */
++ if ((Flush & gcvFLUSH_2D) && (pipe == 0x1))
++ {
++ flush |= ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3)));
++ }
++
++ /* See if there is a valid flush. */
++ if (flush == 0)
++ {
++ if (Bytes != gcvNULL)
++ {
++ /* No bytes required. */
++ *Bytes = 0;
++ }
++ }
++
++ else
++ {
++ /* Copy to command queue. */
++ if (Logical != gcvNULL)
++ {
++ if (*Bytes < reserveBytes)
++ {
++ /* Command queue too small. */
++ gcmkONERROR(gcvSTATUS_BUFFER_TOO_SMALL);
++ }
++
++ /* Append LOAD_STATE to AQFlush. */
++ logical[0] = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E03) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ logical[1] = flush;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "0x%x: FLUSH 0x%x", logical, flush);
++
++ if (fcFlushStall)
++ {
++ logical[2] = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0594) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ logical[3] = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)));
++
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "0x%x: FLUSH 0x%x", logical + 3, logical[3]);
++ }
++
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* bytes required. */
++ *Bytes = reserveBytes;
++ }
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Bytes=%lu", gcmOPT_VALUE(Bytes));
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckHARDWARE_SetFastClear(
++ IN gckHARDWARE Hardware,
++ IN gctINT Enable,
++ IN gctINT Compression
++ )
++{
++#ifndef VIVANTE_NO_3D
++ gctUINT32 debug;
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Hardware=0x%x Enable=%d Compression=%d",
++ Hardware, Enable, Compression);
++
++ /* Only process if fast clear is available. */
++ if ((((((gctUINT32) (Hardware->identity.chipFeatures)) >> (0 ? 0:0)) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1)))))) ))
++ {
++ if (Enable == -1)
++ {
++ /* Determine automatic value for fast clear. */
++ Enable = ((Hardware->identity.chipModel != gcv500)
++ || (Hardware->identity.chipRevision >= 3)
++ ) ? 1 : 0;
++ }
++
++ if (Compression == -1)
++ {
++ /* Determine automatic value for compression. */
++ Compression = Enable
++ & (((((gctUINT32) (Hardware->identity.chipFeatures)) >> (0 ? 5:5)) & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1)))))) );
++ }
++
++ /* Read AQMemoryDebug register. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00414, &debug));
++
++ /* Set fast clear bypass. */
++ debug = ((((gctUINT32) (debug)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 20:20) - (0 ? 20:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:20) - (0 ? 20:20) + 1))))))) << (0 ? 20:20))) | (((gctUINT32) ((gctUINT32) (Enable == 0) & ((gctUINT32) ((((1 ? 20:20) - (0 ? 20:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:20) - (0 ? 20:20) + 1))))))) << (0 ? 20:20)));
++
++ if (
++ ((((gctUINT32) (Hardware->identity.chipMinorFeatures2)) >> (0 ? 27:27) & ((gctUINT32) ((((1 ? 27:27) - (0 ? 27:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:27) - (0 ? 27:27) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 27:27) - (0 ? 27:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:27) - (0 ? 27:27) + 1))))))) ||
++ (Hardware->identity.chipModel >= gcv4000))
++ {
++ /* Set compression bypass. */
++ debug = ((((gctUINT32) (debug)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 21:21) - (0 ? 21:21) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 21:21) - (0 ? 21:21) + 1))))))) << (0 ? 21:21))) | (((gctUINT32) ((gctUINT32) (Compression == 0) & ((gctUINT32) ((((1 ? 21:21) - (0 ? 21:21) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 21:21) - (0 ? 21:21) + 1))))))) << (0 ? 21:21)));
++ }
++
++ /* Write back AQMemoryDebug register. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00414,
++ debug));
++
++ /* Store fast clear and comprersison flags. */
++ Hardware->allowFastClear = Enable;
++ Hardware->allowCompression = Compression;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "FastClear=%d Compression=%d", Enable, Compression);
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++#else
++ return gcvSTATUS_OK;
++#endif
++}
++
++typedef enum
++{
++ gcvPOWER_FLAG_INITIALIZE = 1 << 0,
++ gcvPOWER_FLAG_STALL = 1 << 1,
++ gcvPOWER_FLAG_STOP = 1 << 2,
++ gcvPOWER_FLAG_START = 1 << 3,
++ gcvPOWER_FLAG_RELEASE = 1 << 4,
++ gcvPOWER_FLAG_DELAY = 1 << 5,
++ gcvPOWER_FLAG_SAVE = 1 << 6,
++ gcvPOWER_FLAG_ACQUIRE = 1 << 7,
++ gcvPOWER_FLAG_POWER_OFF = 1 << 8,
++ gcvPOWER_FLAG_CLOCK_OFF = 1 << 9,
++ gcvPOWER_FLAG_CLOCK_ON = 1 << 10,
++}
++gcePOWER_FLAGS;
++
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++static gctCONST_STRING
++_PowerEnum(gceCHIPPOWERSTATE State)
++{
++ const gctCONST_STRING states[] =
++ {
++ gcmSTRING(gcvPOWER_ON),
++ gcmSTRING(gcvPOWER_OFF),
++ gcmSTRING(gcvPOWER_IDLE),
++ gcmSTRING(gcvPOWER_SUSPEND),
++ gcmSTRING(gcvPOWER_SUSPEND_ATPOWERON),
++ gcmSTRING(gcvPOWER_OFF_ATPOWERON),
++ gcmSTRING(gcvPOWER_IDLE_BROADCAST),
++ gcmSTRING(gcvPOWER_SUSPEND_BROADCAST),
++ gcmSTRING(gcvPOWER_OFF_BROADCAST),
++ gcmSTRING(gcvPOWER_OFF_RECOVERY),
++ gcmSTRING(gcvPOWER_ON_AUTO)
++ };
++
++ if ((State >= gcvPOWER_ON) && (State <= gcvPOWER_ON_AUTO))
++ {
++ return states[State - gcvPOWER_ON];
++ }
++
++ return "unknown";
++}
++#endif
++
++/*******************************************************************************
++**
++** gckHARDWARE_SetPowerManagementState
++**
++** Set GPU to a specified power state.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** gceCHIPPOWERSTATE State
++** Power State.
++**
++*/
++gceSTATUS
++gckHARDWARE_SetPowerManagementState(
++ IN gckHARDWARE Hardware,
++ IN gceCHIPPOWERSTATE State
++ )
++{
++ gceSTATUS status;
++ gckCOMMAND command = gcvNULL;
++ gckOS os;
++ gctUINT flag, clock;
++ gctPOINTER buffer;
++ gctSIZE_T bytes, requested;
++ gctBOOL acquired = gcvFALSE;
++ gctBOOL mutexAcquired = gcvFALSE;
++ gctBOOL stall = gcvTRUE;
++ gctBOOL broadcast = gcvFALSE;
++#if gcdPOWEROFF_TIMEOUT
++ gctBOOL timeout = gcvFALSE;
++ gctBOOL isAfter = gcvFALSE;
++ gctUINT32 currentTime;
++#endif
++ gctUINT32 process, thread;
++ gctBOOL commitEntered = gcvFALSE;
++ gctBOOL commandStarted = gcvFALSE;
++ gctBOOL isrStarted = gcvFALSE;
++
++#if gcdENABLE_PROFILING
++ gctUINT64 time, freq, mutexTime, onTime, stallTime, stopTime, delayTime,
++ initTime, offTime, startTime, totalTime;
++#endif
++ gctBOOL global = gcvFALSE;
++ gctBOOL globalAcquired = gcvFALSE;
++ gctBOOL configMmu = gcvFALSE;
++
++ /* State transition flags. */
++ static const gctUINT flags[4][4] =
++ {
++ /* gcvPOWER_ON */
++ { /* ON */ 0,
++ /* OFF */ gcvPOWER_FLAG_ACQUIRE |
++ gcvPOWER_FLAG_STALL |
++ gcvPOWER_FLAG_STOP |
++ gcvPOWER_FLAG_POWER_OFF |
++ gcvPOWER_FLAG_CLOCK_OFF,
++ /* IDLE */ gcvPOWER_FLAG_ACQUIRE |
++ gcvPOWER_FLAG_STALL,
++ /* SUSPEND */ gcvPOWER_FLAG_ACQUIRE |
++ gcvPOWER_FLAG_STALL |
++ gcvPOWER_FLAG_STOP |
++ gcvPOWER_FLAG_CLOCK_OFF,
++ },
++
++ /* gcvPOWER_OFF */
++ { /* ON */ gcvPOWER_FLAG_INITIALIZE |
++ gcvPOWER_FLAG_START |
++ gcvPOWER_FLAG_RELEASE |
++ gcvPOWER_FLAG_DELAY,
++ /* OFF */ 0,
++ /* IDLE */ gcvPOWER_FLAG_INITIALIZE |
++ gcvPOWER_FLAG_START |
++ gcvPOWER_FLAG_DELAY,
++ /* SUSPEND */ gcvPOWER_FLAG_INITIALIZE |
++ gcvPOWER_FLAG_CLOCK_OFF,
++ },
++
++ /* gcvPOWER_IDLE */
++ { /* ON */ gcvPOWER_FLAG_RELEASE,
++ /* OFF */ gcvPOWER_FLAG_STOP |
++ gcvPOWER_FLAG_POWER_OFF |
++ gcvPOWER_FLAG_CLOCK_OFF,
++ /* IDLE */ 0,
++ /* SUSPEND */ gcvPOWER_FLAG_STOP |
++ gcvPOWER_FLAG_CLOCK_OFF,
++ },
++
++ /* gcvPOWER_SUSPEND */
++ { /* ON */ gcvPOWER_FLAG_START |
++ gcvPOWER_FLAG_RELEASE |
++ gcvPOWER_FLAG_DELAY |
++ gcvPOWER_FLAG_CLOCK_ON,
++ /* OFF */ gcvPOWER_FLAG_SAVE |
++ gcvPOWER_FLAG_POWER_OFF |
++ gcvPOWER_FLAG_CLOCK_OFF,
++ /* IDLE */ gcvPOWER_FLAG_START |
++ gcvPOWER_FLAG_DELAY |
++ gcvPOWER_FLAG_CLOCK_ON,
++ /* SUSPEND */ 0,
++ },
++ };
++
++ /* Clocks. */
++ static const gctUINT clocks[4] =
++ {
++ /* gcvPOWER_ON */
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) | (((gctUINT32) ((gctUINT32) (64) & ((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))),
++
++ /* gcvPOWER_OFF */
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))),
++
++ /* gcvPOWER_IDLE */
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))),
++
++ /* gcvPOWER_SUSPEND */
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))),
++ };
++
++ gcmkHEADER_ARG("Hardware=0x%x State=%d", Hardware, State);
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Switching to power state %d(%s)",
++ State, _PowerEnum(State));
++#endif
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Get the gckOS object pointer. */
++ os = Hardware->os;
++ gcmkVERIFY_OBJECT(os, gcvOBJ_OS);
++
++ /* Get the gckCOMMAND object pointer. */
++ gcmkVERIFY_OBJECT(Hardware->kernel, gcvOBJ_KERNEL);
++ command = Hardware->kernel->command;
++ gcmkVERIFY_OBJECT(command, gcvOBJ_COMMAND);
++
++ if (Hardware->powerManagement == gcvFALSE)
++ {
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++
++ /* Start profiler. */
++ gcmkPROFILE_INIT(freq, time);
++
++ /* Convert the broadcast power state. */
++ switch (State)
++ {
++ case gcvPOWER_SUSPEND_ATPOWERON:
++ /* Convert to SUSPEND and don't wait for STALL. */
++ State = gcvPOWER_SUSPEND;
++ stall = gcvFALSE;
++ break;
++
++ case gcvPOWER_OFF_ATPOWERON:
++ /* Convert to OFF and don't wait for STALL. */
++ State = gcvPOWER_OFF;
++ stall = gcvFALSE;
++ break;
++
++ case gcvPOWER_IDLE_BROADCAST:
++ /* Convert to IDLE and note we are inside broadcast. */
++ State = gcvPOWER_IDLE;
++ broadcast = gcvTRUE;
++ break;
++
++ case gcvPOWER_SUSPEND_BROADCAST:
++ /* Convert to SUSPEND and note we are inside broadcast. */
++ State = gcvPOWER_SUSPEND;
++ broadcast = gcvTRUE;
++ break;
++
++ case gcvPOWER_OFF_BROADCAST:
++ /* Convert to OFF and note we are inside broadcast. */
++ State = gcvPOWER_OFF;
++ broadcast = gcvTRUE;
++ break;
++
++ case gcvPOWER_OFF_RECOVERY:
++ /* Convert to OFF and note we are inside recovery. */
++ State = gcvPOWER_OFF;
++ stall = gcvFALSE;
++ broadcast = gcvTRUE;
++ break;
++
++ case gcvPOWER_ON_AUTO:
++ /* Convert to ON and note we are inside recovery. */
++ State = gcvPOWER_ON;
++ break;
++
++ case gcvPOWER_ON:
++ case gcvPOWER_IDLE:
++ case gcvPOWER_SUSPEND:
++ case gcvPOWER_OFF:
++ /* Mark as global power management. */
++ global = gcvTRUE;
++ break;
++
++#if gcdPOWEROFF_TIMEOUT
++ case gcvPOWER_OFF_TIMEOUT:
++ /* Convert to OFF and note we are inside broadcast. */
++ State = gcvPOWER_OFF;
++ broadcast = gcvTRUE;
++ /* Check time out */
++ timeout = gcvTRUE;
++ break;
++#endif
++
++ default:
++ break;
++ }
++
++ /* Get current process and thread IDs. */
++ gcmkONERROR(gckOS_GetProcessID(&process));
++ gcmkONERROR(gckOS_GetThreadID(&thread));
++
++ /* Before we grab locks see if this is actually a needed change */
++ if (State == Hardware->chipPowerState)
++ return gcvSTATUS_OK;
++
++ if (broadcast)
++ {
++ /* Try to acquire the power mutex. */
++ status = gckOS_AcquireMutex(os, Hardware->powerMutex, 0);
++
++ if (status == gcvSTATUS_TIMEOUT)
++ {
++ /* Check if we already own this mutex. */
++ if ((Hardware->powerProcess == process)
++ && (Hardware->powerThread == thread)
++ )
++ {
++ /* Bail out on recursive power management. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++ else if (State == gcvPOWER_IDLE || State == gcvPOWER_SUSPEND)
++ {
++ /* Called from IST,
++ ** so waiting here will cause deadlock,
++ ** if lock holder call gckCOMMAND_Stall() */
++ gcmkONERROR(gcvSTATUS_INVALID_REQUEST);
++ }
++#if gcdPOWEROFF_TIMEOUT
++ else if(State == gcvPOWER_OFF && timeout == gcvTRUE)
++ {
++ /*
++ ** try to aqcuire the mutex with more milliseconds,
++ ** flush_delayed_work should be running with timeout,
++ ** so waiting here will cause deadlock */
++ status = gckOS_AcquireMutex(os, Hardware->powerMutex, gcdPOWEROFF_TIMEOUT);
++
++ if (status == gcvSTATUS_TIMEOUT)
++ {
++ gckOS_Print("GPU Timer deadlock, exit by timeout!!!!\n");
++
++ gcmkONERROR(gcvSTATUS_INVALID_REQUEST);
++ }
++ }
++#endif
++ else
++ {
++ /* Acquire the power mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(os,
++ Hardware->powerMutex,
++ gcvINFINITE));
++ }
++ }
++ }
++ else
++ {
++ /* Acquire the power mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(os, Hardware->powerMutex, gcvINFINITE));
++ }
++
++ /* Get time until mtuex acquired. */
++ gcmkPROFILE_QUERY(time, mutexTime);
++
++ Hardware->powerProcess = process;
++ Hardware->powerThread = thread;
++ mutexAcquired = gcvTRUE;
++
++ /* Grab control flags and clock. */
++ flag = flags[Hardware->chipPowerState][State];
++ clock = clocks[State];
++
++#if gcdENABLE_FSCALE_VAL_ADJUST
++ if (State == gcvPOWER_ON)
++ {
++ clock = ((((gctUINT32) (clock)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) | (((gctUINT32) ((gctUINT32) (Hardware->powerOnFscaleVal) & ((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2)));
++ }
++#endif
++
++ if (State == gcvPOWER_SUSPEND && Hardware->chipPowerState == gcvPOWER_OFF && broadcast)
++ {
++#if gcdPOWER_SUSNPEND_WHEN_IDLE
++ /* Do nothing */
++
++ /* Release the power mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(os, Hardware->powerMutex));
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++#else
++ /* Clock should be on when switch power from off to suspend */
++ clock = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) ;
++#endif
++ }
++
++#if gcdPOWEROFF_TIMEOUT
++ if (timeout)
++ {
++ gcmkONERROR(gckOS_GetTicks(&currentTime));
++
++ gcmkONERROR(
++ gckOS_TicksAfter(Hardware->powerOffTime, currentTime, &isAfter));
++
++ /* powerOffTime is pushed forward, give up.*/
++ if (isAfter
++ /* Expect a transition start from IDLE or SUSPEND. */
++ || (Hardware->chipPowerState == gcvPOWER_ON)
++ || (Hardware->chipPowerState == gcvPOWER_OFF)
++ )
++ {
++ /* Release the power mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(os, Hardware->powerMutex));
++
++ /* No need to do anything. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Power Off GPU[%d] at %u [supposed to be at %u]",
++ Hardware->core, currentTime, Hardware->powerOffTime);
++ }
++
++ if (State == gcvPOWER_ON || State == gcvPOWER_OFF)
++ {
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, "Cancel powerOfftimer");
++
++ /* Cancel running timer when GPU enters ON or OFF. */
++ gcmkVERIFY_OK(gckOS_StopTimer(os, Hardware->powerOffTimer));
++ }
++#endif
++
++ if (flag == 0)
++ {
++ /* Release the power mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(os, Hardware->powerMutex));
++
++ /* No need to do anything. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++
++ /* If this is an internal power management, we have to check if we can grab
++ ** the global power semaphore. If we cannot, we have to wait until the
++ ** external world changes power management. */
++ if (!global)
++ {
++ /* Try to acquire the global semaphore. */
++ status = gckOS_TryAcquireSemaphore(os, Hardware->globalSemaphore);
++ if (status == gcvSTATUS_TIMEOUT)
++ {
++ if (State == gcvPOWER_IDLE || State == gcvPOWER_SUSPEND)
++ {
++ /* Called from thread routine which should NEVER sleep.*/
++ gcmkONERROR(gcvSTATUS_INVALID_REQUEST);
++ }
++
++ /* Release the power mutex. */
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Releasing the power mutex.");
++ gcmkONERROR(gckOS_ReleaseMutex(os, Hardware->powerMutex));
++ mutexAcquired = gcvFALSE;
++
++ /* Wait for the semaphore. */
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Waiting for global semaphore.");
++ gcmkONERROR(gckOS_AcquireSemaphore(os, Hardware->globalSemaphore));
++ globalAcquired = gcvTRUE;
++
++ /* Acquire the power mutex. */
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Reacquiring the power mutex.");
++ gcmkONERROR(gckOS_AcquireMutex(os,
++ Hardware->powerMutex,
++ gcvINFINITE));
++ mutexAcquired = gcvTRUE;
++
++ /* chipPowerState may be changed by external world during the time
++ ** we give up powerMutex, so updating flag now is necessary. */
++ flag = flags[Hardware->chipPowerState][State];
++
++ if (flag == 0)
++ {
++ gcmkONERROR(gckOS_ReleaseSemaphore(os, Hardware->globalSemaphore));
++ globalAcquired = gcvFALSE;
++
++ gcmkONERROR(gckOS_ReleaseMutex(os, Hardware->powerMutex));
++ mutexAcquired = gcvFALSE;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++ }
++ else
++ {
++ /* Error. */
++ gcmkONERROR(status);
++ }
++
++ /* Release the global semaphore again. */
++ gcmkONERROR(gckOS_ReleaseSemaphore(os, Hardware->globalSemaphore));
++ globalAcquired = gcvFALSE;
++ }
++ else
++ {
++ if (State == gcvPOWER_OFF || State == gcvPOWER_SUSPEND || State == gcvPOWER_IDLE)
++ {
++ /* Acquire the global semaphore if it has not been acquired. */
++ status = gckOS_TryAcquireSemaphore(os, Hardware->globalSemaphore);
++ if (status == gcvSTATUS_OK)
++ {
++ globalAcquired = gcvTRUE;
++ }
++ else if (status != gcvSTATUS_TIMEOUT)
++ {
++ /* Other errors. */
++ gcmkONERROR(status);
++ }
++ /* Ignore gcvSTATUS_TIMEOUT and leave globalAcquired as gcvFALSE.
++ ** gcvSTATUS_TIMEOUT means global semaphore has already
++ ** been acquired before this operation, so even if we fail,
++ ** we should not release it in our error handling. It should be
++ ** released by the next successful global gcvPOWER_ON. */
++ }
++
++ /* Global power management can't be aborted, so sync with
++ ** proceeding last commit. */
++ if (flag & gcvPOWER_FLAG_ACQUIRE)
++ {
++ /* Acquire the power management semaphore. */
++ gcmkONERROR(gckOS_AcquireSemaphore(os, command->powerSemaphore));
++ acquired = gcvTRUE;
++
++ /* avoid acquiring again. */
++ flag &= ~gcvPOWER_FLAG_ACQUIRE;
++ }
++ }
++
++ if (flag & (gcvPOWER_FLAG_INITIALIZE | gcvPOWER_FLAG_CLOCK_ON))
++ {
++ /* Turn on the power. */
++ gcmkONERROR(gckOS_SetGPUPower(os, Hardware->core, gcvTRUE, gcvTRUE));
++
++ /* Mark clock and power as enabled. */
++ Hardware->clockState = gcvTRUE;
++ Hardware->powerState = gcvTRUE;
++
++ for (;;)
++ {
++ /* Check if GPU is present and awake. */
++ status = _IsGPUPresent(Hardware);
++
++ /* Check if the GPU is not responding. */
++ if (status == gcvSTATUS_GPU_NOT_RESPONDING)
++ {
++ /* Turn off the power and clock. */
++ gcmkONERROR(gckOS_SetGPUPower(os, Hardware->core, gcvFALSE, gcvFALSE));
++
++ Hardware->clockState = gcvFALSE;
++ Hardware->powerState = gcvFALSE;
++
++ /* Wait a little. */
++ gckOS_Delay(os, 1);
++
++ /* Turn on the power and clock. */
++ gcmkONERROR(gckOS_SetGPUPower(os, Hardware->core, gcvTRUE, gcvTRUE));
++
++ Hardware->clockState = gcvTRUE;
++ Hardware->powerState = gcvTRUE;
++
++ /* We need to initialize the hardware and start the command
++ * processor. */
++ flag |= gcvPOWER_FLAG_INITIALIZE | gcvPOWER_FLAG_START;
++ }
++ else
++ {
++ /* Test for error. */
++ gcmkONERROR(status);
++
++ /* Break out of loop. */
++ break;
++ }
++ }
++ }
++
++ /* Get time until powered on. */
++ gcmkPROFILE_QUERY(time, onTime);
++
++ if ((flag & gcvPOWER_FLAG_STALL) && stall)
++ {
++ gctBOOL idle;
++ gctINT32 atomValue;
++
++ /* For global operation, all pending commits have already been
++ ** blocked by globalSemaphore or powerSemaphore.*/
++ if (!global)
++ {
++ /* Check commit atom. */
++ gcmkONERROR(gckOS_AtomGet(os, command->atomCommit, &atomValue));
++
++ if (atomValue > 0)
++ {
++ /* Commits are pending - abort power management. */
++ status = broadcast ? gcvSTATUS_CHIP_NOT_READY
++ : gcvSTATUS_MORE_DATA;
++ goto OnError;
++ }
++ }
++
++ if (broadcast)
++ {
++ /* Check for idle. */
++ gcmkONERROR(gckHARDWARE_QueryIdle(Hardware, &idle));
++
++ if (!idle)
++ {
++ status = gcvSTATUS_CHIP_NOT_READY;
++ goto OnError;
++ }
++ }
++
++ else
++ {
++ /* Acquire the command queue. */
++ gcmkONERROR(gckCOMMAND_EnterCommit(command, gcvTRUE));
++ commitEntered = gcvTRUE;
++
++ /* Get the size of the flush command. */
++ gcmkONERROR(gckHARDWARE_Flush(Hardware,
++ gcvFLUSH_ALL,
++ gcvNULL,
++ &requested));
++
++ /* Reserve space in the command queue. */
++ gcmkONERROR(gckCOMMAND_Reserve(command,
++ requested,
++ &buffer,
++ &bytes));
++
++ /* Append a flush. */
++ gcmkONERROR(gckHARDWARE_Flush(
++ Hardware, gcvFLUSH_ALL, buffer, &bytes
++ ));
++
++ /* Execute the command queue. */
++ gcmkONERROR(gckCOMMAND_Execute(command, requested));
++
++ /* Release the command queue. */
++ gcmkONERROR(gckCOMMAND_ExitCommit(command, gcvTRUE));
++ commitEntered = gcvFALSE;
++
++ /* Wait to finish all commands. */
++ gcmkONERROR(gckCOMMAND_Stall(command, gcvTRUE));
++ }
++ }
++
++ /* Get time until stalled. */
++ gcmkPROFILE_QUERY(time, stallTime);
++
++ if (flag & gcvPOWER_FLAG_ACQUIRE)
++ {
++ /* Acquire the power management semaphore. */
++ gcmkONERROR(gckOS_AcquireSemaphore(os, command->powerSemaphore));
++ acquired = gcvTRUE;
++ }
++
++ if (flag & gcvPOWER_FLAG_STOP)
++ {
++ /* Stop the command parser. */
++ gcmkONERROR(gckCOMMAND_Stop(command, gcvFALSE));
++
++ /* Stop the Isr. */
++ if (Hardware->stopIsr)
++ {
++ gcmkONERROR(Hardware->stopIsr(Hardware->isrContext, Hardware->core));
++ }
++ }
++
++ /* Flush Cache before Power Off. */
++ if (flag & gcvPOWER_FLAG_POWER_OFF)
++ {
++ if (Hardware->clockState == gcvFALSE)
++ {
++ /* Turn off the GPU power. */
++ gcmkONERROR(
++ gckOS_SetGPUPower(os,
++ Hardware->core,
++ gcvTRUE,
++ gcvTRUE));
++
++ Hardware->clockState = gcvTRUE;
++
++ if (gckHARDWARE_IsFeatureAvailable(Hardware, gcvFEATURE_DYNAMIC_FREQUENCY_SCALING) != gcvTRUE)
++ {
++ /* Write the clock control register. */
++ gcmkONERROR(gckOS_WriteRegisterEx(os,
++ Hardware->core,
++ 0x00000,
++ clocks[0]));
++
++ /* Done loading the frequency scaler. */
++ gcmkONERROR(gckOS_WriteRegisterEx(os,
++ Hardware->core,
++ 0x00000,
++ ((((gctUINT32) (clocks[0])) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9)))));
++ }
++ }
++
++ gcmkONERROR(gckCOMMAND_Start(command));
++
++ gcmkONERROR(_FlushCache(Hardware, command));
++
++ gckOS_Delay(gcvNULL, 1);
++
++ /* Stop the command parser. */
++ gcmkONERROR(gckCOMMAND_Stop(command, gcvFALSE));
++
++ flag |= gcvPOWER_FLAG_CLOCK_OFF;
++ }
++
++ /* Get time until stopped. */
++ gcmkPROFILE_QUERY(time, stopTime);
++
++ /* Only process this when hardware is enabled. */
++ if (Hardware->clockState && Hardware->powerState
++ /* Don't touch clock control if dynamic frequency scaling is available. */
++ && gckHARDWARE_IsFeatureAvailable(Hardware, gcvFEATURE_DYNAMIC_FREQUENCY_SCALING) != gcvTRUE
++ )
++ {
++ if (flag & (gcvPOWER_FLAG_POWER_OFF | gcvPOWER_FLAG_CLOCK_OFF))
++ {
++ if (Hardware->identity.chipModel == gcv4000
++ && Hardware->identity.chipRevision == 0x5208)
++ {
++ clock &= ~2U;
++ }
++ }
++
++ /* Write the clock control register. */
++ gcmkONERROR(gckOS_WriteRegisterEx(os,
++ Hardware->core,
++ 0x00000,
++ clock));
++
++ /* Done loading the frequency scaler. */
++ gcmkONERROR(gckOS_WriteRegisterEx(os,
++ Hardware->core,
++ 0x00000,
++ ((((gctUINT32) (clock)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9)))));
++ }
++
++ if (flag & gcvPOWER_FLAG_DELAY)
++ {
++ /* Wait for the specified amount of time to settle coming back from
++ ** power-off or suspend state. */
++ gcmkONERROR(gckOS_Delay(os, gcdPOWER_CONTROL_DELAY));
++ }
++
++ /* Get time until delayed. */
++ gcmkPROFILE_QUERY(time, delayTime);
++
++ if (flag & gcvPOWER_FLAG_INITIALIZE)
++ {
++ /* Initialize hardware. */
++ gcmkONERROR(gckHARDWARE_InitializeHardware(Hardware));
++
++ gcmkONERROR(gckHARDWARE_SetFastClear(Hardware,
++ Hardware->allowFastClear,
++ Hardware->allowCompression));
++
++ /* Force the command queue to reload the next context. */
++ command->currContext = gcvNULL;
++
++ /* Need to config mmu after command start. */
++ configMmu = gcvTRUE;
++ }
++
++ /* Get time until initialized. */
++ gcmkPROFILE_QUERY(time, initTime);
++
++ if (flag & (gcvPOWER_FLAG_POWER_OFF | gcvPOWER_FLAG_CLOCK_OFF))
++ {
++ /* Turn off the GPU power. */
++ gcmkONERROR(
++ gckOS_SetGPUPower(os,
++ Hardware->core,
++ (flag & gcvPOWER_FLAG_CLOCK_OFF) ? gcvFALSE
++ : gcvTRUE,
++ (flag & gcvPOWER_FLAG_POWER_OFF) ? gcvFALSE
++ : gcvTRUE));
++
++ /* Save current hardware power and clock states. */
++ Hardware->clockState = (flag & gcvPOWER_FLAG_CLOCK_OFF) ? gcvFALSE
++ : gcvTRUE;
++ Hardware->powerState = (flag & gcvPOWER_FLAG_POWER_OFF) ? gcvFALSE
++ : gcvTRUE;
++ }
++
++ /* Get time until off. */
++ gcmkPROFILE_QUERY(time, offTime);
++
++ if (flag & gcvPOWER_FLAG_START)
++ {
++ /* Start the command processor. */
++ gcmkONERROR(gckCOMMAND_Start(command));
++ commandStarted = gcvTRUE;
++
++ if (Hardware->startIsr)
++ {
++ /* Start the Isr. */
++ gcmkONERROR(Hardware->startIsr(Hardware->isrContext, Hardware->core));
++ isrStarted = gcvTRUE;
++ }
++
++ /* Set NEW MMU. */
++ if (Hardware->mmuVersion != 0 && configMmu)
++ {
++ gcmkONERROR(
++ gckHARDWARE_SetMMUv2(
++ Hardware,
++ gcvTRUE,
++ Hardware->kernel->mmu->mtlbLogical,
++ gcvMMU_MODE_4K,
++ (gctUINT8_PTR)Hardware->kernel->mmu->mtlbLogical + gcdMMU_MTLB_SIZE,
++ gcvTRUE
++ ));
++ }
++ }
++
++ /* Get time until started. */
++ gcmkPROFILE_QUERY(time, startTime);
++
++ if (flag & gcvPOWER_FLAG_RELEASE)
++ {
++ /* Release the power management semaphore. */
++ gcmkONERROR(gckOS_ReleaseSemaphore(os, command->powerSemaphore));
++ acquired = gcvFALSE;
++
++ if (global)
++ {
++ /* Verify global semaphore has been acquired already before
++ ** we release it.
++ ** If it was acquired, gckOS_TryAcquireSemaphore will return
++ ** gcvSTATUS_TIMEOUT and we release it. Otherwise, global
++ ** semaphore will be acquried now, but it still is released
++ ** immediately. */
++ status = gckOS_TryAcquireSemaphore(os, Hardware->globalSemaphore);
++ if (status != gcvSTATUS_TIMEOUT)
++ {
++ gcmkONERROR(status);
++ }
++
++ /* Release the global semaphore. */
++ gcmkONERROR(gckOS_ReleaseSemaphore(os, Hardware->globalSemaphore));
++ globalAcquired = gcvFALSE;
++ }
++ }
++
++ /* Save the new power state. */
++ Hardware->chipPowerState = State;
++
++#if gcdDVFS
++ if (State == gcvPOWER_ON && Hardware->kernel->dvfs)
++ {
++ gckDVFS_Start(Hardware->kernel->dvfs);
++ }
++#endif
++
++#if gcdPOWEROFF_TIMEOUT
++ if (State == gcvPOWER_IDLE || State == gcvPOWER_SUSPEND)
++ {
++ gcmkONERROR(gckOS_GetTicks(&currentTime));
++
++ Hardware->powerOffTime = currentTime + Hardware->powerOffTimeout;
++ /* Start a timer to power off GPU when GPU enters IDLE or SUSPEND. */
++ gcmkVERIFY_OK(gckOS_StartTimer(os,
++ Hardware->powerOffTimer,
++ Hardware->powerOffTimeout));
++ }
++#endif
++
++ /* Release the power mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(os, Hardware->powerMutex));
++
++ /* Get total time. */
++ gcmkPROFILE_QUERY(time, totalTime);
++#if gcdENABLE_PROFILING
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "PROF(%llu): mutex:%llu on:%llu stall:%llu stop:%llu",
++ freq, mutexTime, onTime, stallTime, stopTime);
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ " delay:%llu init:%llu off:%llu start:%llu total:%llu",
++ delayTime, initTime, offTime, startTime, totalTime);
++#endif
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (commandStarted)
++ {
++ gcmkVERIFY_OK(gckCOMMAND_Stop(command, gcvFALSE));
++ }
++
++ if (isrStarted)
++ {
++ gcmkVERIFY_OK(Hardware->stopIsr(Hardware->isrContext, Hardware->core));
++ }
++
++ if (commitEntered)
++ {
++ /* Release the command queue mutex. */
++ gcmkVERIFY_OK(gckCOMMAND_ExitCommit(command, gcvTRUE));
++ }
++
++ if (acquired)
++ {
++ /* Release semaphore. */
++ gcmkVERIFY_OK(gckOS_ReleaseSemaphore(Hardware->os,
++ command->powerSemaphore));
++ }
++
++ if (globalAcquired)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseSemaphore(Hardware->os,
++ Hardware->globalSemaphore));
++ }
++
++ if (mutexAcquired)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Hardware->os, Hardware->powerMutex));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_QueryPowerManagementState
++**
++** Get GPU power state.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** gceCHIPPOWERSTATE* State
++** Power State.
++**
++*/
++gceSTATUS
++gckHARDWARE_QueryPowerManagementState(
++ IN gckHARDWARE Hardware,
++ OUT gceCHIPPOWERSTATE* State
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(State != gcvNULL);
++
++ /* Return the statue. */
++ *State = Hardware->chipPowerState;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*State=%d", *State);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_SetPowerManagement
++**
++** Configure GPU power management function.
++** Only used in driver initialization stage.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** gctBOOL PowerManagement
++** Power Mangement State.
++**
++*/
++gceSTATUS
++gckHARDWARE_SetPowerManagement(
++ IN gckHARDWARE Hardware,
++ IN gctBOOL PowerManagement
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ Hardware->powerManagement = PowerManagement;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_SetGpuProfiler
++**
++** Configure GPU profiler function.
++** Only used in driver initialization stage.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** gctBOOL GpuProfiler
++** GOU Profiler State.
++**
++*/
++gceSTATUS
++gckHARDWARE_SetGpuProfiler(
++ IN gckHARDWARE Hardware,
++ IN gctBOOL GpuProfiler
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ Hardware->gpuProfiler = GpuProfiler;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++#if gcdENABLE_FSCALE_VAL_ADJUST
++gceSTATUS
++gckHARDWARE_SetFscaleValue(
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 FscaleValue
++ )
++{
++ gceSTATUS status;
++ gctUINT32 clock;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Hardware=0x%x FscaleValue=%d", Hardware, FscaleValue);
++
++ gcmkVERIFY_ARGUMENT(FscaleValue > 0 && FscaleValue <= 64);
++
++ gcmkONERROR(
++ gckOS_AcquireMutex(Hardware->os, Hardware->powerMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ Hardware->powerOnFscaleVal = FscaleValue;
++
++ if (Hardware->chipPowerState == gcvPOWER_ON)
++ {
++ gctUINT32 data;
++
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress
++ + 0x00104,
++ &data));
++
++ /* Disable all clock gating. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress
++ + 0x00104,
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1))))))) << (0 ? 7:7))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1))))))) << (0 ? 7:7)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 8:8) - (0 ? 8:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:8) - (0 ? 8:8) + 1))))))) << (0 ? 8:8))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 8:8) - (0 ? 8:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:8) - (0 ? 8:8) + 1))))))) << (0 ? 8:8)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 11:11) - (0 ? 11:11) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:11) - (0 ? 11:11) + 1))))))) << (0 ? 11:11))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 11:11) - (0 ? 11:11) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:11) - (0 ? 11:11) + 1))))))) << (0 ? 11:11)))));
++
++ clock = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) | (((gctUINT32) ((gctUINT32) (FscaleValue) & ((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9)));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ clock));
++
++ /* Done loading the frequency scaler. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ ((((gctUINT32) (clock)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9)))));
++
++ /* Restore all clock gating. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress
++ + 0x00104,
++ data));
++ }
++
++ gcmkVERIFY(gckOS_ReleaseMutex(Hardware->os, Hardware->powerMutex));
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ gcmkVERIFY(gckOS_ReleaseMutex(Hardware->os, Hardware->powerMutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckHARDWARE_GetFscaleValue(
++ IN gckHARDWARE Hardware,
++ IN gctUINT * FscaleValue,
++ IN gctUINT * MinFscaleValue,
++ IN gctUINT * MaxFscaleValue
++ )
++{
++ *FscaleValue = Hardware->powerOnFscaleVal;
++ if ((gpu3DMinClock > 0) && (gpu3DMinClock <= 64) && (Hardware->core == gcvCORE_MAJOR))
++ *MinFscaleValue = gpu3DMinClock;
++ else
++ *MinFscaleValue = 1;
++ *MaxFscaleValue = 64;
++
++ return gcvSTATUS_OK;
++}
++
++#endif
++
++#if gcdPOWEROFF_TIMEOUT
++gceSTATUS
++gckHARDWARE_SetPowerOffTimeout(
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 Timeout
++)
++{
++ gcmkHEADER_ARG("Hardware=0x%x Timeout=%d", Hardware, Timeout);
++
++ Hardware->powerOffTimeout = Timeout;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++
++gceSTATUS
++gckHARDWARE_QueryPowerOffTimeout(
++ IN gckHARDWARE Hardware,
++ OUT gctUINT32* Timeout
++)
++{
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ *Timeout = Hardware->powerOffTimeout;
++
++ gcmkFOOTER_ARG("*Timeout=%d", *Timeout);
++ return gcvSTATUS_OK;
++}
++#endif
++
++gceSTATUS
++gckHARDWARE_QueryIdle(
++ IN gckHARDWARE Hardware,
++ OUT gctBOOL_PTR IsIdle
++ )
++{
++ gceSTATUS status;
++ gctUINT32 idle, address;
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(IsIdle != gcvNULL);
++
++ /* We are idle when the power is not ON. */
++ if (Hardware->chipPowerState != gcvPOWER_ON)
++ {
++ *IsIdle = gcvTRUE;
++ }
++
++ else
++ {
++ /* Read idle register. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00004, &idle));
++
++ /* Pipe must be idle. */
++ if (((((((gctUINT32) (idle)) >> (0 ? 1:1)) & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1)))))) ) != 1)
++ || ((((((gctUINT32) (idle)) >> (0 ? 3:3)) & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1)))))) ) != 1)
++ || ((((((gctUINT32) (idle)) >> (0 ? 4:4)) & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1)))))) ) != 1)
++ || ((((((gctUINT32) (idle)) >> (0 ? 5:5)) & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1)))))) ) != 1)
++ || ((((((gctUINT32) (idle)) >> (0 ? 6:6)) & ((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1)))))) ) != 1)
++ || ((((((gctUINT32) (idle)) >> (0 ? 7:7)) & ((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1)))))) ) != 1)
++ || ((((((gctUINT32) (idle)) >> (0 ? 2:2)) & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1)))))) ) != 1)
++ )
++ {
++ /* Something is busy. */
++ *IsIdle = gcvFALSE;
++ }
++
++ else
++ {
++ /* Read the current FE address. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00664,
++ &address));
++
++ /* Test if address is inside the last WAIT/LINK sequence. */
++ if ((address >= Hardware->lastWaitLink)
++ && (address <= Hardware->lastWaitLink + 16)
++ )
++ {
++ /* FE is in last WAIT/LINK and the pipe is idle. */
++ *IsIdle = gcvTRUE;
++ }
++ else
++ {
++ /* FE is not in WAIT/LINK yet. */
++ *IsIdle = gcvFALSE;
++ }
++ }
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++** Handy macros that will help in reading those debug registers.
++*/
++
++#define gcmkREAD_DEBUG_REGISTER(control, block, index, data) \
++ gcmkONERROR(\
++ gckOS_WriteRegisterEx(Hardware->os, \
++ Hardware->core, \
++ GC_DEBUG_CONTROL##control##_Address, \
++ gcmSETFIELD(0, \
++ GC_DEBUG_CONTROL##control, \
++ block, \
++ index))); \
++ gcmkONERROR(\
++ gckOS_ReadRegisterEx(Hardware->os, \
++ Hardware->core, \
++ GC_DEBUG_SIGNALS_##block##_Address, \
++ &profiler->data))
++
++#define gcmkREAD_DEBUG_REGISTER_N(control, block, index, data) \
++ gcmkONERROR(\
++ gckOS_WriteRegisterEx(Hardware->os, \
++ Hardware->core, \
++ GC_DEBUG_CONTROL##control##_Address, \
++ gcmSETFIELD(0, \
++ GC_DEBUG_CONTROL##control, \
++ block, \
++ index))); \
++ gcmkONERROR(\
++ gckOS_ReadRegisterEx(Hardware->os, \
++ Hardware->core, \
++ GC_DEBUG_SIGNALS_##block##_Address, \
++ &data))
++
++#define gcmkRESET_DEBUG_REGISTER(control, block) \
++ gcmkONERROR(\
++ gckOS_WriteRegisterEx(Hardware->os, \
++ Hardware->core, \
++ GC_DEBUG_CONTROL##control##_Address, \
++ gcmSETFIELD(0, \
++ GC_DEBUG_CONTROL##control, \
++ block, \
++ 15))); \
++ gcmkONERROR(\
++ gckOS_WriteRegisterEx(Hardware->os, \
++ Hardware->core, \
++ GC_DEBUG_CONTROL##control##_Address, \
++ gcmSETFIELD(0, \
++ GC_DEBUG_CONTROL##control, \
++ block, \
++ 0)))
++
++/*******************************************************************************
++**
++** gckHARDWARE_ProfileEngine2D
++**
++** Read the profile registers available in the 2D engine and sets them in the
++** profile. The function will also reset the pixelsRendered counter every time.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to an gckHARDWARE object.
++**
++** OPTIONAL gcs2D_PROFILE_PTR Profile
++** Pointer to a gcs2D_Profile structure.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckHARDWARE_ProfileEngine2D(
++ IN gckHARDWARE Hardware,
++ OPTIONAL gcs2D_PROFILE_PTR Profile
++ )
++{
++ gceSTATUS status;
++ gcs2D_PROFILE_PTR profiler = Profile;
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ if (Profile != gcvNULL)
++ {
++ /* Read the cycle count. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00438,
++ &Profile->cycleCount));
++
++ /* Read pixels rendered by 2D engine. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (11) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00454, &profiler->pixelsRendered));
++
++ /* Reset counter. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))
++));
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++#if VIVANTE_PROFILER
++gceSTATUS
++gckHARDWARE_QueryProfileRegisters(
++ IN gckHARDWARE Hardware,
++ IN gctBOOL Reset,
++ OUT gcsPROFILER_COUNTERS * Counters
++ )
++{
++ gceSTATUS status;
++ gcsPROFILER_COUNTERS * profiler = Counters;
++ gctUINT i, clock;
++ gctUINT32 colorKilled, colorDrawn, depthKilled, depthDrawn;
++ gctUINT32 totalRead, totalWrite;
++
++ gcmkHEADER_ARG("Hardware=0x%x Counters=0x%x", Hardware, Counters);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Read the counters. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00438,
++ &profiler->gpuCyclesCounter));
++
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00078,
++ &profiler->gpuTotalCyclesCounter));
++
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0007C,
++ &profiler->gpuIdleCyclesCounter));
++
++
++ /* Read clock control register. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ &clock));
++
++ profiler->gpuTotalRead64BytesPerFrame = 0;
++ profiler->gpuTotalWrite64BytesPerFrame = 0;
++ profiler->pe_pixel_count_killed_by_color_pipe = 0;
++ profiler->pe_pixel_count_killed_by_depth_pipe = 0;
++ profiler->pe_pixel_count_drawn_by_color_pipe = 0;
++ profiler->pe_pixel_count_drawn_by_depth_pipe = 0;
++
++ /* Walk through all avaiable pixel pipes. */
++ for (i = 0; i < Hardware->identity.pixelPipes; ++i)
++ {
++ /* Select proper pipe. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ ((((gctUINT32) (clock)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:20) - (0 ? 23:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:20) - (0 ? 23:20) + 1))))))) << (0 ? 23:20))) | (((gctUINT32) ((gctUINT32) (i) & ((gctUINT32) ((((1 ? 23:20) - (0 ? 23:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:20) - (0 ? 23:20) + 1))))))) << (0 ? 23:20)))));
++
++ /* BW */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00040,
++ &totalRead));
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00044,
++ &totalWrite));
++
++ profiler->gpuTotalRead64BytesPerFrame += totalRead;
++ profiler->gpuTotalWrite64BytesPerFrame += totalWrite;
++
++ /* PE */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))));gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00454, &colorKilled));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))));gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00454, &depthKilled));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (2) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))));gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00454, &colorDrawn));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (3) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))));gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00454, &depthDrawn));
++
++ profiler->pe_pixel_count_killed_by_color_pipe += colorKilled;
++ profiler->pe_pixel_count_killed_by_depth_pipe += depthKilled;
++ profiler->pe_pixel_count_drawn_by_color_pipe += colorDrawn;
++ profiler->pe_pixel_count_drawn_by_depth_pipe += depthDrawn;
++ }
++
++ /* Reset clock control register. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ clock));
++
++ if(Reset){
++ /* Reset counters. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x0003C, 1));
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x0003C, 0));
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00438, 0));
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00078, 0));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))
++));
++ }
++
++ /* SH */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (7) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->ps_inst_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (8) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->rendered_pixel_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (9) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->vs_inst_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (10) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->rendered_vertice_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (11) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->vtx_branch_inst_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (12) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->vtx_texld_inst_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (13) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->pxl_branch_inst_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (14) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->pxl_texld_inst_counter));
++ if(Reset){ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24)))
++));}
++
++ /* PA */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (3) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_input_vtx_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (4) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_input_prim_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (5) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_output_prim_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (6) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_depth_clipped_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (7) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_trivial_rejected_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (8) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_culled_counter));
++ if(Reset){ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0)))
++));}
++
++ /* SE */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00464, &profiler->se_culled_triangle_count));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00464, &profiler->se_culled_lines_count));
++ if(Reset){ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8)))
++));}
++
++ /* RA */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_valid_pixel_count));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_total_quad_count));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (2) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_valid_quad_count_after_early_z));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (3) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_total_primitive_count));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (9) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_pipe_cache_miss_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (10) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_prefetch_cache_miss_counter));
++ if(Reset){ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))
++));}
++
++ /* TX */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_total_bilinear_requests));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_total_trilinear_requests));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (2) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_total_discarded_texture_requests));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (3) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_total_texture_requests));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (5) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_mem_read_count));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (6) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_mem_read_in_8B_count));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (7) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_cache_miss_count));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (8) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_cache_hit_texel_count));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (9) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_cache_miss_texel_count));
++ if(Reset){ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24)))
++));}
++
++ /* MC */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00468, &profiler->mc_total_read_req_8B_from_pipeline));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (2) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00468, &profiler->mc_total_read_req_8B_from_IP));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (3) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00468, &profiler->mc_total_write_req_8B_from_pipeline));
++ if(Reset){ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0)))
++));}
++
++ /* HI */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0046C, &profiler->hi_axi_cycles_read_request_stalled));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0046C, &profiler->hi_axi_cycles_write_request_stalled));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (2) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0046C, &profiler->hi_axi_cycles_write_data_stalled));
++ if(Reset){ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8)))
++));}
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++#endif
++
++#if VIVANTE_PROFILER_CONTEXT
++#define gcmkUPDATE_PROFILE_DATA(data) \
++ profilerHistroy->data += profiler->data
++
++gceSTATUS
++gckHARDWARE_QueryContextProfile(
++ IN gckHARDWARE Hardware,
++ IN gctBOOL Reset,
++ IN gckCONTEXT Context,
++ OUT gcsPROFILER_COUNTERS * Counters
++ )
++{
++ gceSTATUS status;
++ gckCOMMAND command = Hardware->kernel->command;
++ gcsPROFILER_COUNTERS * profiler = Counters;
++
++ gcmkHEADER_ARG("Hardware=0x%x Counters=0x%x", Hardware, Counters);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Acquire the context sequnence mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(
++ command->os, command->mutexContextSeq, gcvINFINITE
++ ));
++
++ /* Read the counters. */
++ gcmkVERIFY_OK(gckOS_MemCopy(
++ profiler, &Context->histroyProfiler, gcmSIZEOF(gcsPROFILER_COUNTERS)
++ ));
++
++ if (Reset)
++ {
++ /* Reset counters. */
++ gcmkVERIFY_OK(gckOS_ZeroMemory(
++ &Context->histroyProfiler, gcmSIZEOF(gcsPROFILER_COUNTERS)
++ ));
++ }
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(
++ command->os, command->mutexContextSeq
++ ));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++
++gceSTATUS
++gckHARDWARE_UpdateContextProfile(
++ IN gckHARDWARE Hardware,
++ IN gckCONTEXT Context
++ )
++{
++ gceSTATUS status;
++ gcsPROFILER_COUNTERS * profiler = &Context->latestProfiler;
++ gcsPROFILER_COUNTERS * profilerHistroy = &Context->histroyProfiler;
++ gctUINT i, clock;
++ gctUINT32 colorKilled, colorDrawn, depthKilled, depthDrawn;
++ gctUINT32 totalRead, totalWrite;
++ gceCHIPMODEL chipModel;
++ gctUINT32 chipRevision;
++ gctUINT32 temp;
++ gctBOOL needResetShader = gcvFALSE;
++
++ gcmkHEADER_ARG("Hardware=0x%x Context=0x%x", Hardware, Context);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_OBJECT(Context, gcvOBJ_CONTEXT);
++
++ chipModel = Hardware->identity.chipModel;
++ chipRevision = Hardware->identity.chipRevision;
++ if (chipModel == gcv2000 || (chipModel == gcv2100 && chipRevision == 0x5118))
++ {
++ needResetShader = gcvTRUE;
++ }
++
++ /* Read the counters. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00438,
++ &profiler->gpuCyclesCounter));
++ gcmkUPDATE_PROFILE_DATA(gpuCyclesCounter);
++
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00078,
++ &profiler->gpuTotalCyclesCounter));
++ gcmkUPDATE_PROFILE_DATA(gpuTotalCyclesCounter);
++
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0007C,
++ &profiler->gpuIdleCyclesCounter));
++ gcmkUPDATE_PROFILE_DATA(gpuIdleCyclesCounter);
++
++ /* Read clock control register. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ &clock));
++
++ profiler->gpuTotalRead64BytesPerFrame = 0;
++ profiler->gpuTotalWrite64BytesPerFrame = 0;
++ profiler->pe_pixel_count_killed_by_color_pipe = 0;
++ profiler->pe_pixel_count_killed_by_depth_pipe = 0;
++ profiler->pe_pixel_count_drawn_by_color_pipe = 0;
++ profiler->pe_pixel_count_drawn_by_depth_pipe = 0;
++
++ /* Walk through all avaiable pixel pipes. */
++ for (i = 0; i < Hardware->identity.pixelPipes; ++i)
++ {
++ /* Select proper pipe. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ ((((gctUINT32) (clock)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:20) - (0 ? 23:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:20) - (0 ? 23:20) + 1))))))) << (0 ? 23:20))) | (((gctUINT32) ((gctUINT32) (i) & ((gctUINT32) ((((1 ? 23:20) - (0 ? 23:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:20) - (0 ? 23:20) + 1))))))) << (0 ? 23:20)))));
++
++ /* BW */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00040,
++ &totalRead));
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00044,
++ &totalWrite));
++
++ profiler->gpuTotalRead64BytesPerFrame += totalRead;
++ profiler->gpuTotalWrite64BytesPerFrame += totalWrite;
++ gcmkUPDATE_PROFILE_DATA(gpuTotalRead64BytesPerFrame);
++ gcmkUPDATE_PROFILE_DATA(gpuTotalWrite64BytesPerFrame);
++
++ /* PE */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))));gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00454, &colorKilled));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))));gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00454, &depthKilled));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (2) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))));gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00454, &colorDrawn));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (3) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))));gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00454, &depthDrawn));
++
++ profiler->pe_pixel_count_killed_by_color_pipe += colorKilled;
++ profiler->pe_pixel_count_killed_by_depth_pipe += depthKilled;
++ profiler->pe_pixel_count_drawn_by_color_pipe += colorDrawn;
++ profiler->pe_pixel_count_drawn_by_depth_pipe += depthDrawn;
++ gcmkUPDATE_PROFILE_DATA(pe_pixel_count_killed_by_color_pipe);
++ gcmkUPDATE_PROFILE_DATA(pe_pixel_count_killed_by_depth_pipe);
++ gcmkUPDATE_PROFILE_DATA(pe_pixel_count_drawn_by_color_pipe);
++ gcmkUPDATE_PROFILE_DATA(pe_pixel_count_drawn_by_depth_pipe);
++ }
++
++ /* Reset clock control register. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ clock));
++
++
++
++
++ /* Reset counters. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x0003C, 1));
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x0003C, 0));
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00438, 0));
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00078, 0));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))
++));
++
++ /* SH */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (7) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->ps_inst_counter));
++ if (needResetShader)
++ {
++ temp = profiler->ps_inst_counter;
++ profiler->ps_inst_counter -= Context->prevPSInstCount;
++ Context->prevPSInstCount = temp;
++ }
++ gcmkUPDATE_PROFILE_DATA(ps_inst_counter);
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (8) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->rendered_pixel_counter));
++ if (needResetShader)
++ {
++ temp = profiler->rendered_pixel_counter;
++ profiler->rendered_pixel_counter -= Context->prevPSPixelCount;
++ Context->prevPSPixelCount = temp;
++ }
++ gcmkUPDATE_PROFILE_DATA(rendered_pixel_counter);
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (9) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->vs_inst_counter));
++ if (needResetShader)
++ {
++ temp = profiler->vs_inst_counter;
++ profiler->vs_inst_counter -= Context->prevVSInstCount;
++ Context->prevVSInstCount = temp;
++ }
++ gcmkUPDATE_PROFILE_DATA(vs_inst_counter);
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (10) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->rendered_vertice_counter));
++ if (needResetShader)
++ {
++ temp = profiler->rendered_vertice_counter;
++ profiler->rendered_vertice_counter -= Context->prevVSVertexCount;
++ Context->prevVSVertexCount = temp;
++ }
++ gcmkUPDATE_PROFILE_DATA(rendered_vertice_counter);
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (11) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->vtx_branch_inst_counter));
++ if (needResetShader)
++ {
++ temp = profiler->vtx_branch_inst_counter;
++ profiler->vtx_branch_inst_counter -= Context->prevVSBranchInstCount;
++ Context->prevVSBranchInstCount = temp;
++ }
++ gcmkUPDATE_PROFILE_DATA(vtx_branch_inst_counter);
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (12) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->vtx_texld_inst_counter));
++ if (needResetShader)
++ {
++ temp = profiler->vtx_texld_inst_counter;
++ profiler->vtx_texld_inst_counter -= Context->prevVSTexInstCount;
++ Context->prevVSTexInstCount = temp;
++ }
++ gcmkUPDATE_PROFILE_DATA(vtx_texld_inst_counter);
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (13) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->pxl_branch_inst_counter));
++ if (needResetShader)
++ {
++ temp = profiler->pxl_branch_inst_counter;
++ profiler->pxl_branch_inst_counter -= Context->prevPSBranchInstCount;
++ Context->prevPSBranchInstCount = temp;
++ }
++ gcmkUPDATE_PROFILE_DATA(pxl_branch_inst_counter);
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (14) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->pxl_texld_inst_counter));
++ if (needResetShader)
++ {
++ temp = profiler->pxl_texld_inst_counter;
++ profiler->pxl_texld_inst_counter -= Context->prevPSTexInstCount;
++ Context->prevPSTexInstCount = temp;
++ }
++ gcmkUPDATE_PROFILE_DATA(pxl_texld_inst_counter);
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24)))
++));
++
++ /* PA */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (3) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_input_vtx_counter));
++ gcmkUPDATE_PROFILE_DATA(pa_input_vtx_counter);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (4) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_input_prim_counter));
++ gcmkUPDATE_PROFILE_DATA(pa_input_prim_counter);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (5) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_output_prim_counter));
++ gcmkUPDATE_PROFILE_DATA(pa_output_prim_counter);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (6) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_depth_clipped_counter));
++ gcmkUPDATE_PROFILE_DATA(pa_depth_clipped_counter);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (7) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_trivial_rejected_counter));
++ gcmkUPDATE_PROFILE_DATA(pa_trivial_rejected_counter);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (8) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_culled_counter));
++ gcmkUPDATE_PROFILE_DATA(pa_culled_counter);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0)))
++));
++
++ /* SE */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00464, &profiler->se_culled_triangle_count));
++ gcmkUPDATE_PROFILE_DATA(se_culled_triangle_count);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00464, &profiler->se_culled_lines_count));
++ gcmkUPDATE_PROFILE_DATA(se_culled_lines_count);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8)))
++));
++
++ /* RA */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_valid_pixel_count));
++ gcmkUPDATE_PROFILE_DATA(ra_valid_pixel_count);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_total_quad_count));
++ gcmkUPDATE_PROFILE_DATA(ra_total_quad_count);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (2) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_valid_quad_count_after_early_z));
++ gcmkUPDATE_PROFILE_DATA(ra_valid_quad_count_after_early_z);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (3) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_total_primitive_count));
++ gcmkUPDATE_PROFILE_DATA(ra_total_primitive_count);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (9) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_pipe_cache_miss_counter));
++ gcmkUPDATE_PROFILE_DATA(ra_pipe_cache_miss_counter);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (10) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_prefetch_cache_miss_counter));
++ gcmkUPDATE_PROFILE_DATA(ra_prefetch_cache_miss_counter);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))
++));
++
++ /* TX */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_total_bilinear_requests));
++ gcmkUPDATE_PROFILE_DATA(tx_total_bilinear_requests);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_total_trilinear_requests));
++ gcmkUPDATE_PROFILE_DATA(tx_total_trilinear_requests);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (2) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_total_discarded_texture_requests));
++ gcmkUPDATE_PROFILE_DATA(tx_total_discarded_texture_requests);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (3) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_total_texture_requests));
++ gcmkUPDATE_PROFILE_DATA(tx_total_texture_requests);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (5) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_mem_read_count));
++ gcmkUPDATE_PROFILE_DATA(tx_mem_read_count);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (6) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_mem_read_in_8B_count));
++ gcmkUPDATE_PROFILE_DATA(tx_mem_read_in_8B_count);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (7) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_cache_miss_count));
++ gcmkUPDATE_PROFILE_DATA(tx_cache_miss_count);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (8) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_cache_hit_texel_count));
++ gcmkUPDATE_PROFILE_DATA(tx_cache_hit_texel_count);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (9) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_cache_miss_texel_count));
++ gcmkUPDATE_PROFILE_DATA(tx_cache_miss_texel_count);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24)))
++));
++
++ /* MC */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00468, &profiler->mc_total_read_req_8B_from_pipeline));
++ gcmkUPDATE_PROFILE_DATA(mc_total_read_req_8B_from_pipeline);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (2) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00468, &profiler->mc_total_read_req_8B_from_IP));
++ gcmkUPDATE_PROFILE_DATA(mc_total_read_req_8B_from_IP);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (3) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00468, &profiler->mc_total_write_req_8B_from_pipeline));
++ gcmkUPDATE_PROFILE_DATA(mc_total_write_req_8B_from_pipeline);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0)))
++));
++
++ /* HI */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0046C, &profiler->hi_axi_cycles_read_request_stalled));
++ gcmkUPDATE_PROFILE_DATA(hi_axi_cycles_read_request_stalled);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0046C, &profiler->hi_axi_cycles_write_request_stalled));
++ gcmkUPDATE_PROFILE_DATA(hi_axi_cycles_write_request_stalled);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (2) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0046C, &profiler->hi_axi_cycles_write_data_stalled));
++ gcmkUPDATE_PROFILE_DATA(hi_axi_cycles_write_data_stalled);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8)))
++));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++#endif
++
++static gceSTATUS
++_ResetGPU(
++ IN gckHARDWARE Hardware,
++ IN gckOS Os,
++ IN gceCORE Core
++ )
++{
++ gctUINT32 control, idle;
++ gceSTATUS status;
++
++ for (;;)
++ {
++ /* Disable clock gating. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ Core,
++ Hardware->powerBaseAddress +
++ 0x00104,
++ 0x00000000));
++
++ control = ((((gctUINT32) (0x01590880)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 17:17) - (0 ? 17:17) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 17:17) - (0 ? 17:17) + 1))))))) << (0 ? 17:17))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 17:17) - (0 ? 17:17) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 17:17) - (0 ? 17:17) + 1))))))) << (0 ? 17:17)));
++
++ /* Disable pulse-eater. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ Core,
++ 0x0010C,
++ control));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ Core,
++ 0x0010C,
++ ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)))));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ Core,
++ 0x0010C,
++ control));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ Core,
++ 0x00000,
++ ((((gctUINT32) (0x00000900)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9)))));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ Core,
++ 0x00000,
++ 0x00000900));
++
++ /* Wait for clock being stable. */
++ gcmkONERROR(gckOS_Delay(Os, 1));
++
++ /* Isolate the GPU. */
++ control = ((((gctUINT32) (0x00000900)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19)));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ Core,
++ 0x00000,
++ control));
++
++ /* Set soft reset. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ Core,
++ 0x00000,
++ ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12)))));
++
++ /* Wait for reset. */
++ gcmkONERROR(gckOS_Delay(Os, 1));
++
++ /* Reset soft reset bit. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ Core,
++ 0x00000,
++ ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12)))));
++
++ /* Reset GPU isolation. */
++ control = ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19)));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ Core,
++ 0x00000,
++ control));
++
++ /* Read idle register. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Os,
++ Core,
++ 0x00004,
++ &idle));
++
++ if ((((((gctUINT32) (idle)) >> (0 ? 0:0)) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1)))))) ) == 0)
++ {
++ continue;
++ }
++
++ /* Read reset register. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Os,
++ Core,
++ 0x00000,
++ &control));
++
++ if (((((((gctUINT32) (control)) >> (0 ? 16:16)) & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1)))))) ) == 0)
++ || ((((((gctUINT32) (control)) >> (0 ? 17:17)) & ((gctUINT32) ((((1 ? 17:17) - (0 ? 17:17) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 17:17) - (0 ? 17:17) + 1)))))) ) == 0)
++ )
++ {
++ continue;
++ }
++
++ /* GPU is idle. */
++ break;
++ }
++
++ /* Success. */
++ return gcvSTATUS_OK;
++
++OnError:
++
++ /* Return the error. */
++ return status;
++}
++
++gceSTATUS
++gckHARDWARE_Reset(
++ IN gckHARDWARE Hardware
++ )
++{
++ gceSTATUS status;
++ gckCOMMAND command;
++ gctBOOL acquired = gcvFALSE;
++ gctBOOL mutexAcquired = gcvFALSE;
++ gctUINT32 process, thread;
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_OBJECT(Hardware->kernel, gcvOBJ_KERNEL);
++ command = Hardware->kernel->command;
++ gcmkVERIFY_OBJECT(command, gcvOBJ_COMMAND);
++
++ if (Hardware->identity.chipRevision < 0x4600)
++ {
++ /* Not supported - we need the isolation bit. */
++ gcmkONERROR(gcvSTATUS_NOT_SUPPORTED);
++ }
++
++ status = gckOS_AcquireMutex(Hardware->os, Hardware->powerMutex, 0);
++ if (status == gcvSTATUS_TIMEOUT)
++ {
++ gcmkONERROR(gckOS_GetProcessID(&process));
++ gcmkONERROR(gckOS_GetThreadID(&thread));
++
++ if ((Hardware->powerProcess == process)
++ && (Hardware->powerThread == thread))
++ {
++ /* No way to recovery from a error in power management. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++ }
++ else
++ {
++ mutexAcquired = gcvTRUE;
++ }
++
++ if (Hardware->chipPowerState == gcvPOWER_ON)
++ {
++ /* Acquire the power management semaphore. */
++ gcmkONERROR(
++ gckOS_AcquireSemaphore(Hardware->os, command->powerSemaphore));
++ acquired = gcvTRUE;
++ }
++
++ if ((Hardware->chipPowerState == gcvPOWER_ON)
++ || (Hardware->chipPowerState == gcvPOWER_IDLE)
++ )
++ {
++ /* Stop the command processor. */
++ gcmkONERROR(gckCOMMAND_Stop(command, gcvTRUE));
++ }
++
++ /* Stop isr, we will start it again when power on GPU. */
++ if (Hardware->stopIsr)
++ {
++ gcmkONERROR(Hardware->stopIsr(Hardware->isrContext, Hardware->core));
++ }
++
++ /* Hardware reset. */
++ status = gckOS_ResetGPU(Hardware->os, Hardware->core);
++
++ if (gcmIS_ERROR(status))
++ {
++ /* Soft reset. */
++ gcmkONERROR(_ResetGPU(Hardware, Hardware->os, Hardware->core));
++ }
++
++ /* Force an OFF to ON power switch. */
++ Hardware->chipPowerState = gcvPOWER_OFF;
++
++ gcmkONERROR(gckOS_ReleaseMutex(Hardware->os, Hardware->powerMutex));
++ mutexAcquired = gcvFALSE;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ /* Release the power management semaphore. */
++ gcmkVERIFY_OK(
++ gckOS_ReleaseSemaphore(Hardware->os, command->powerSemaphore));
++ }
++
++ if (mutexAcquired)
++ {
++ gckOS_ReleaseMutex(Hardware->os, Hardware->powerMutex);
++ }
++
++ /* Return the error. */
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckHARDWARE_GetBaseAddress(
++ IN gckHARDWARE Hardware,
++ OUT gctUINT32_PTR BaseAddress
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(BaseAddress != gcvNULL);
++
++ /* Test if we have a new Memory Controller. */
++ if (((((gctUINT32) (Hardware->identity.chipMinorFeatures)) >> (0 ? 22:22) & ((gctUINT32) ((((1 ? 22:22) - (0 ? 22:22) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 22:22) - (0 ? 22:22) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 22:22) - (0 ? 22:22) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 22:22) - (0 ? 22:22) + 1))))))))
++ {
++ /* No base address required. */
++ *BaseAddress = 0;
++ }
++ else
++ {
++ /* Get the base address from the OS. */
++ gcmkONERROR(gckOS_GetBaseAddress(Hardware->os, BaseAddress));
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*BaseAddress=0x%08x", *BaseAddress);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckHARDWARE_NeedBaseAddress(
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 State,
++ OUT gctBOOL_PTR NeedBase
++ )
++{
++ gctBOOL need = gcvFALSE;
++
++ gcmkHEADER_ARG("Hardware=0x%x State=0x%08x", Hardware, State);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(NeedBase != gcvNULL);
++
++ /* Make sure this is a load state. */
++ if (((((gctUINT32) (State)) >> (0 ? 31:27) & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1)))))) == (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))))
++ {
++#ifndef VIVANTE_NO_3D
++ /* Get the state address. */
++ switch ((((((gctUINT32) (State)) >> (0 ? 15:0)) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1)))))) ))
++ {
++ case 0x0596:
++ case 0x0597:
++ case 0x0599:
++ case 0x059A:
++ case 0x05A9:
++ /* These states need a TRUE physical address. */
++ need = gcvTRUE;
++ break;
++ }
++#else
++ /* 2D addresses don't need a base address. */
++#endif
++ }
++
++ /* Return the flag. */
++ *NeedBase = need;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*NeedBase=%d", *NeedBase);
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckHARDWARE_SetIsrManager(
++ IN gckHARDWARE Hardware,
++ IN gctISRMANAGERFUNC StartIsr,
++ IN gctISRMANAGERFUNC StopIsr,
++ IN gctPOINTER Context
++ )
++{
++ gceSTATUS status = gcvSTATUS_OK;
++
++ gcmkHEADER_ARG("Hardware=0x%x, StartIsr=0x%x, StopIsr=0x%x, Context=0x%x",
++ Hardware, StartIsr, StopIsr, Context);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ if (StartIsr == gcvNULL ||
++ StopIsr == gcvNULL ||
++ Context == gcvNULL)
++ {
++ status = gcvSTATUS_INVALID_ARGUMENT;
++
++ gcmkFOOTER();
++ return status;
++ }
++
++ Hardware->startIsr = StartIsr;
++ Hardware->stopIsr = StopIsr;
++ Hardware->isrContext = Context;
++
++ /* Success. */
++ gcmkFOOTER();
++
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_Compose
++**
++** Start a composition.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to the gckHARDWARE object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckHARDWARE_Compose(
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 ProcessID,
++ IN gctPHYS_ADDR Physical,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Offset,
++ IN gctSIZE_T Size,
++ IN gctUINT8 EventID
++ )
++{
++#ifndef VIVANTE_NO_3D
++ gceSTATUS status;
++ gctUINT32_PTR triggerState;
++
++ gcmkHEADER_ARG("Hardware=0x%x Physical=0x%x Logical=0x%x"
++ " Offset=%d Size=%d EventID=%d",
++ Hardware, Physical, Logical, Offset, Size, EventID);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(((Size + 8) & 63) == 0);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++
++ /* Program the trigger state. */
++ triggerState = (gctUINT32_PTR) ((gctUINT8_PTR) Logical + Offset + Size);
++ triggerState[0] = 0x0C03;
++ triggerState[1]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:4) - (0 ? 5:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:4) - (0 ? 5:4) + 1))))))) << (0 ? 5:4))) | (((gctUINT32) (0x3 & ((gctUINT32) ((((1 ? 5:4) - (0 ? 5:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:4) - (0 ? 5:4) + 1))))))) << (0 ? 5:4)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 8:8) - (0 ? 8:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:8) - (0 ? 8:8) + 1))))))) << (0 ? 8:8))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 8:8) - (0 ? 8:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:8) - (0 ? 8:8) + 1))))))) << (0 ? 8:8)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 24:24) - (0 ? 24:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 24:24) - (0 ? 24:24) + 1))))))) << (0 ? 24:24))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 24:24) - (0 ? 24:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 24:24) - (0 ? 24:24) + 1))))))) << (0 ? 24:24)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 20:16) - (0 ? 20:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:16) - (0 ? 20:16) + 1))))))) << (0 ? 20:16))) | (((gctUINT32) ((gctUINT32) (EventID) & ((gctUINT32) ((((1 ? 20:16) - (0 ? 20:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:16) - (0 ? 20:16) + 1))))))) << (0 ? 20:16)))
++ ;
++
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ /* Flush the cache for the wait/link. */
++ gcmkONERROR(gckOS_CacheClean(
++ Hardware->os, ProcessID, gcvNULL,
++ Physical, Logical, Offset + Size
++ ));
++#endif
++
++ /* Start composition. */
++ gcmkONERROR(gckOS_WriteRegisterEx(
++ Hardware->os, Hardware->core, 0x00554,
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0))) | (((gctUINT32) (0x3 & ((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0)))
++ ));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++#else
++ /* Return the status. */
++ return gcvSTATUS_NOT_SUPPORTED;
++#endif
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_IsFeatureAvailable
++**
++** Verifies whether the specified feature is available in hardware.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to an gckHARDWARE object.
++**
++** gceFEATURE Feature
++** Feature to be verified.
++*/
++gceSTATUS
++gckHARDWARE_IsFeatureAvailable(
++ IN gckHARDWARE Hardware,
++ IN gceFEATURE Feature
++ )
++{
++ gctBOOL available;
++
++ gcmkHEADER_ARG("Hardware=0x%x Feature=%d", Hardware, Feature);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Only features needed by common kernel logic added here. */
++ switch (Feature)
++ {
++ case gcvFEATURE_END_EVENT:
++ /*available = gcmVERIFYFIELDVALUE(Hardware->identity.chipMinorFeatures2,
++ GC_MINOR_FEATURES2, END_EVENT, AVAILABLE
++ );*/
++ available = gcvFALSE;
++ break;
++ case gcvFEATURE_MC20:
++ available = ((((gctUINT32) (Hardware->identity.chipMinorFeatures)) >> (0 ? 22:22) & ((gctUINT32) ((((1 ? 22:22) - (0 ? 22:22) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 22:22) - (0 ? 22:22) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 22:22) - (0 ? 22:22) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 22:22) - (0 ? 22:22) + 1)))))));
++ break;
++ case gcvFEATURE_DYNAMIC_FREQUENCY_SCALING:
++ /* This feature doesn't apply for 2D cores. */
++ available = ((((gctUINT32) (Hardware->identity.chipMinorFeatures2)) >> (0 ? 14:14) & ((gctUINT32) ((((1 ? 14:14) - (0 ? 14:14) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 14:14) - (0 ? 14:14) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 14:14) - (0 ? 14:14) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 14:14) - (0 ? 14:14) + 1)))))))
++ && ((((gctUINT32) (Hardware->identity.chipFeatures)) >> (0 ? 2:2) & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1)))))));
++ break;
++
++ case gcvFEATURE_PIPE_2D:
++ available = ((((gctUINT32) (Hardware->identity.chipFeatures)) >> (0 ? 9:9) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1)))))));
++ break;
++
++ case gcvFEATURE_PIPE_3D:
++#ifndef VIVANTE_NO_3D
++ available = ((((gctUINT32) (Hardware->identity.chipFeatures)) >> (0 ? 2:2) & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1)))))));
++#else
++ available = gcvFALSE;
++#endif
++ break;
++
++ case gcvFEATURE_HALTI2:
++ available = ((((gctUINT32) (Hardware->identity.chipMinorFeatures4)) >> (0 ? 16:16) & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1)))))));
++ break;
++
++ default:
++ gcmkFATAL("Invalid feature has been requested.");
++ available = gcvFALSE;
++ }
++
++ /* Return result. */
++ gcmkFOOTER_ARG("%d", available ? gcvSTATUS_TRUE : gcvSTATUS_OK);
++ return available ? gcvSTATUS_TRUE : gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_DumpMMUException
++**
++** Dump the MMU debug info on an MMU exception.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckHARDWARE_DumpMMUException(
++ IN gckHARDWARE Hardware
++ )
++{
++#if !gcdPOWER_SUSNPEND_WHEN_IDLE && !gcdPOWEROFF_TIMEOUT
++ gctUINT32 mmu, mmuStatus, address, i;
++#if gcdDEBUG
++ gctUINT32 mtlb, stlb, offset;
++#endif
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ gcmkPRINT("GPU[%d](ChipModel=0x%x ChipRevision=0x%x):\n",
++ Hardware->core,
++ Hardware->identity.chipModel,
++ Hardware->identity.chipRevision);
++
++ gcmkPRINT("**************************\n");
++ gcmkPRINT("*** MMU ERROR DUMP ***\n");
++ gcmkPRINT("**************************\n");
++
++ gcmkVERIFY_OK(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00188,
++ &mmuStatus));
++
++ gcmkPRINT(" MMU status = 0x%08X\n", mmuStatus);
++
++ for (i = 0; i < 4; i += 1)
++ {
++ mmu = mmuStatus & 0xF;
++ mmuStatus >>= 4;
++
++ if (mmu == 0)
++ {
++ continue;
++ }
++
++ switch (mmu)
++ {
++ case 1:
++ gcmkPRINT(" MMU%d: slave not present\n", i);
++ break;
++
++ case 2:
++ gcmkPRINT(" MMU%d: page not present\n", i);
++ break;
++
++ case 3:
++ gcmkPRINT(" MMU%d: write violation\n", i);
++ break;
++
++ default:
++ gcmkPRINT(" MMU%d: unknown state\n", i);
++ }
++
++ gcmkVERIFY_OK(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00190 + i * 4,
++ &address));
++
++ mtlb = (address & gcdMMU_MTLB_MASK) >> gcdMMU_MTLB_SHIFT;
++ stlb = (address & gcdMMU_STLB_4K_MASK) >> gcdMMU_STLB_4K_SHIFT;
++ offset = address & gcdMMU_OFFSET_4K_MASK;
++
++ gcmkPRINT(" MMU%d: exception address = 0x%08X\n", i, address);
++
++ gcmkPRINT(" MTLB entry = %d\n", mtlb);
++
++ gcmkPRINT(" STLB entry = %d\n", stlb);
++
++ gcmkPRINT(" Offset = 0x%08X (%d)\n", offset, offset);
++
++ gckMMU_DumpPageTableEntry(Hardware->kernel->mmu, address);
++
++ }
++
++ gcmkFOOTER_NO();
++#else
++ /* If clock could be off automatically, we can't read mmu debug
++ ** register here; build driver with gcdPOWER_SUSPEND_WHEN_IDLE = 0
++ ** and gcdPOWEROFF_TIMEOUT = 0 to make it safe to read mmu register. */
++ gcmkPRINT("[galcore] %s(%d): MMU Exception!", __FUNCTION__, __LINE__);
++#endif
++
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_DumpGPUState
++**
++** Dump the GPU debug registers.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckHARDWARE_DumpGPUState(
++ IN gckHARDWARE Hardware
++ )
++{
++ static gctCONST_STRING _cmdState[] =
++ {
++ "PAR_IDLE_ST", "PAR_DEC_ST", "PAR_ADR0_ST", "PAR_LOAD0_ST",
++ "PAR_ADR1_ST", "PAR_LOAD1_ST", "PAR_3DADR_ST", "PAR_3DCMD_ST",
++ "PAR_3DCNTL_ST", "PAR_3DIDXCNTL_ST", "PAR_INITREQDMA_ST",
++ "PAR_DRAWIDX_ST", "PAR_DRAW_ST", "PAR_2DRECT0_ST", "PAR_2DRECT1_ST",
++ "PAR_2DDATA0_ST", "PAR_2DDATA1_ST", "PAR_WAITFIFO_ST", "PAR_WAIT_ST",
++ "PAR_LINK_ST", "PAR_END_ST", "PAR_STALL_ST"
++ };
++
++ static gctCONST_STRING _cmdDmaState[] =
++ {
++ "CMD_IDLE_ST", "CMD_START_ST", "CMD_REQ_ST", "CMD_END_ST"
++ };
++
++ static gctCONST_STRING _cmdFetState[] =
++ {
++ "FET_IDLE_ST", "FET_RAMVALID_ST", "FET_VALID_ST"
++ };
++
++ static gctCONST_STRING _reqDmaState[] =
++ {
++ "REQ_IDLE_ST", "REQ_WAITIDX_ST", "REQ_CAL_ST"
++ };
++
++ static gctCONST_STRING _calState[] =
++ {
++ "CAL_IDLE_ST", "CAL_LDADR_ST", "CAL_IDXCALC_ST"
++ };
++
++ static gctCONST_STRING _veReqState[] =
++ {
++ "VER_IDLE_ST", "VER_CKCACHE_ST", "VER_MISS_ST"
++ };
++
++ static gcsiDEBUG_REGISTERS _dbgRegs[] =
++ {
++ { "RA", 0x474, 16, 0x448, 16, 0x12344321 },
++ { "TX", 0x474, 24, 0x44C, 16, 0x12211221 },
++ { "FE", 0x470, 0, 0x450, 16, 0xBABEF00D },
++ { "PE", 0x470, 16, 0x454, 16, 0xBABEF00D },
++ { "DE", 0x470, 8, 0x458, 16, 0xBABEF00D },
++ { "SH", 0x470, 24, 0x45C, 16, 0xDEADBEEF },
++ { "PA", 0x474, 0, 0x460, 16, 0x0000AAAA },
++ { "SE", 0x474, 8, 0x464, 16, 0x5E5E5E5E },
++ { "MC", 0x478, 0, 0x468, 16, 0x12345678 },
++ { "HI", 0x478, 8, 0x46C, 16, 0xAAAAAAAA }
++ };
++
++ static gctUINT32 _otherRegs[] =
++ {
++ 0x040, 0x044, 0x04C, 0x050, 0x054, 0x058, 0x05C, 0x060,
++ 0x43c, 0x440, 0x444, 0x414,
++ };
++
++ gceSTATUS status;
++ gckKERNEL kernel;
++ gctUINT32 idle, axi;
++ gctUINT32 dmaAddress1, dmaAddress2;
++ gctUINT32 dmaState1, dmaState2;
++ gctUINT32 dmaLow, dmaHigh;
++ gctUINT32 cmdState, cmdDmaState, cmdFetState;
++ gctUINT32 dmaReqState, calState, veReqState;
++ gctUINT i;
++ gctUINT pipe, pixelPipes;
++ gctUINT32 control, oldControl;
++ gckOS os = Hardware->os;
++ gceCORE core = Hardware->core;
++
++ gcmkHEADER_ARG("Hardware=0x%X", Hardware);
++
++ kernel = Hardware->kernel;
++
++ gcmkPRINT_N(12, "GPU[%d](ChipModel=0x%x ChipRevision=0x%x):\n",
++ core,
++ Hardware->identity.chipModel,
++ Hardware->identity.chipRevision);
++
++ pixelPipes = Hardware->identity.pixelPipes
++ ? Hardware->identity.pixelPipes
++ : 1;
++
++ /* Reset register values. */
++ idle = axi =
++ dmaState1 = dmaState2 =
++ dmaAddress1 = dmaAddress2 =
++ dmaLow = dmaHigh = 0;
++
++ /* Verify whether DMA is running. */
++ gcmkONERROR(_VerifyDMA(
++ os, core, &dmaAddress1, &dmaAddress2, &dmaState1, &dmaState2
++ ));
++
++ cmdState = dmaState2 & 0x1F;
++ cmdDmaState = (dmaState2 >> 8) & 0x03;
++ cmdFetState = (dmaState2 >> 10) & 0x03;
++ dmaReqState = (dmaState2 >> 12) & 0x03;
++ calState = (dmaState2 >> 14) & 0x03;
++ veReqState = (dmaState2 >> 16) & 0x03;
++
++ gcmkONERROR(gckOS_ReadRegisterEx(os, core, 0x004, &idle));
++ gcmkONERROR(gckOS_ReadRegisterEx(os, core, 0x00C, &axi));
++ gcmkONERROR(gckOS_ReadRegisterEx(os, core, 0x668, &dmaLow));
++ gcmkONERROR(gckOS_ReadRegisterEx(os, core, 0x66C, &dmaHigh));
++
++ gcmkPRINT_N(0, "**************************\n");
++ gcmkPRINT_N(0, "*** GPU STATE DUMP ***\n");
++ gcmkPRINT_N(0, "**************************\n");
++
++ gcmkPRINT_N(4, " axi = 0x%08X\n", axi);
++
++ gcmkPRINT_N(4, " idle = 0x%08X\n", idle);
++ if ((idle & 0x00000001) == 0) gcmkPRINT_N(0, " FE not idle\n");
++ if ((idle & 0x00000002) == 0) gcmkPRINT_N(0, " DE not idle\n");
++ if ((idle & 0x00000004) == 0) gcmkPRINT_N(0, " PE not idle\n");
++ if ((idle & 0x00000008) == 0) gcmkPRINT_N(0, " SH not idle\n");
++ if ((idle & 0x00000010) == 0) gcmkPRINT_N(0, " PA not idle\n");
++ if ((idle & 0x00000020) == 0) gcmkPRINT_N(0, " SE not idle\n");
++ if ((idle & 0x00000040) == 0) gcmkPRINT_N(0, " RA not idle\n");
++ if ((idle & 0x00000080) == 0) gcmkPRINT_N(0, " TX not idle\n");
++ if ((idle & 0x00000100) == 0) gcmkPRINT_N(0, " VG not idle\n");
++ if ((idle & 0x00000200) == 0) gcmkPRINT_N(0, " IM not idle\n");
++ if ((idle & 0x00000400) == 0) gcmkPRINT_N(0, " FP not idle\n");
++ if ((idle & 0x00000800) == 0) gcmkPRINT_N(0, " TS not idle\n");
++ if ((idle & 0x80000000) != 0) gcmkPRINT_N(0, " AXI low power mode\n");
++
++ if (
++ (dmaAddress1 == dmaAddress2)
++ && (dmaState1 == dmaState2)
++ )
++ {
++ gcmkPRINT_N(0, " DMA appears to be stuck at this address:\n");
++ gcmkPRINT_N(4, " 0x%08X\n", dmaAddress1);
++ }
++ else
++ {
++ if (dmaAddress1 == dmaAddress2)
++ {
++ gcmkPRINT_N(0, " DMA address is constant, but state is changing:\n");
++ gcmkPRINT_N(4, " 0x%08X\n", dmaState1);
++ gcmkPRINT_N(4, " 0x%08X\n", dmaState2);
++ }
++ else
++ {
++ gcmkPRINT_N(0, " DMA is running; known addresses are:\n");
++ gcmkPRINT_N(4, " 0x%08X\n", dmaAddress1);
++ gcmkPRINT_N(4, " 0x%08X\n", dmaAddress2);
++ }
++ }
++ gcmkPRINT_N(4, " dmaLow = 0x%08X\n", dmaLow);
++ gcmkPRINT_N(4, " dmaHigh = 0x%08X\n", dmaHigh);
++ gcmkPRINT_N(4, " dmaState = 0x%08X\n", dmaState2);
++ gcmkPRINT_N(8, " command state = %d (%s)\n", cmdState, _cmdState [cmdState]);
++ gcmkPRINT_N(8, " command DMA state = %d (%s)\n", cmdDmaState, _cmdDmaState[cmdDmaState]);
++ gcmkPRINT_N(8, " command fetch state = %d (%s)\n", cmdFetState, _cmdFetState[cmdFetState]);
++ gcmkPRINT_N(8, " DMA request state = %d (%s)\n", dmaReqState, _reqDmaState[dmaReqState]);
++ gcmkPRINT_N(8, " cal state = %d (%s)\n", calState, _calState [calState]);
++ gcmkPRINT_N(8, " VE request state = %d (%s)\n", veReqState, _veReqState [veReqState]);
++
++ /* Record control. */
++ gckOS_ReadRegisterEx(os, core, 0x0, &oldControl);
++
++ for (pipe = 0; pipe < pixelPipes; pipe++)
++ {
++ gcmkPRINT_N(4, " Debug registers of pipe[%d]:\n", pipe);
++
++ /* Switch pipe. */
++ gckOS_ReadRegisterEx(os, core, 0x0, &control);
++ control &= ~(0xF << 20);
++ control |= (pipe << 20);
++ gckOS_WriteRegisterEx(os, core, 0x0, control);
++
++ for (i = 0; i < gcmCOUNTOF(_dbgRegs); i += 1)
++ {
++ gcmkONERROR(_DumpDebugRegisters(os, core, &_dbgRegs[i]));
++ }
++
++ gcmkPRINT_N(0, " Other Registers:\n");
++ for (i = 0; i < gcmCOUNTOF(_otherRegs); i += 1)
++ {
++ gctUINT32 read;
++ gcmkONERROR(gckOS_ReadRegisterEx(os, core, _otherRegs[i], &read));
++ gcmkPRINT_N(12, " [0x%04X] 0x%08X\n", _otherRegs[i], read);
++ }
++ }
++
++ if (kernel->hardware->identity.chipFeatures & (1 << 4))
++ {
++ gctUINT32 read0, read1, write;
++
++ read0 = read1 = write = 0;
++
++ gcmkONERROR(gckOS_ReadRegisterEx(os, core, 0x43C, &read0));
++ gcmkONERROR(gckOS_ReadRegisterEx(os, core, 0x440, &read1));
++ gcmkONERROR(gckOS_ReadRegisterEx(os, core, 0x444, &write));
++
++ gcmkPRINT_N(4, " read0 = 0x%08X\n", read0);
++ gcmkPRINT_N(4, " read1 = 0x%08X\n", read1);
++ gcmkPRINT_N(4, " write = 0x%08X\n", write);
++ }
++
++ /* Restore control. */
++ gckOS_WriteRegisterEx(os, core, 0x0, oldControl);
++
++ /* dump stack. */
++ gckOS_DumpCallStack(os);
++
++OnError:
++
++ /* Return the error. */
++ gcmkFOOTER();
++ return status;
++}
++
++
++#if gcdFRAME_DB
++static gceSTATUS
++gckHARDWARE_ReadPerformanceRegister(
++ IN gckHARDWARE Hardware,
++ IN gctUINT PerformanceAddress,
++ IN gctUINT IndexAddress,
++ IN gctUINT IndexShift,
++ IN gctUINT Index,
++ OUT gctUINT32_PTR Value
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Hardware=0x%x PerformanceAddress=0x%x IndexAddress=0x%x "
++ "IndexShift=%u Index=%u",
++ Hardware, PerformanceAddress, IndexAddress, IndexShift,
++ Index);
++
++ /* Write the index. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ IndexAddress,
++ Index << IndexShift));
++
++ /* Read the register. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ PerformanceAddress,
++ Value));
++
++ /* Test for reset. */
++ if (Index == 15)
++ {
++ /* Index another register to get out of reset. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, IndexAddress, 0));
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Value=0x%x", *Value);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckHARDWARE_GetFrameInfo(
++ IN gckHARDWARE Hardware,
++ OUT gcsHAL_FRAME_INFO * FrameInfo
++ )
++{
++ gceSTATUS status;
++ gctUINT i, clock;
++ gcsHAL_FRAME_INFO info;
++#if gcdFRAME_DB_RESET
++ gctUINT reset;
++#endif
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Get profile tick. */
++ gcmkONERROR(gckOS_GetProfileTick(&info.ticks));
++
++ /* Read SH counters and reset them. */
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x0045C,
++ 0x00470,
++ 24,
++ 4,
++ &info.shaderCycles));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x0045C,
++ 0x00470,
++ 24,
++ 9,
++ &info.vsInstructionCount));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x0045C,
++ 0x00470,
++ 24,
++ 12,
++ &info.vsTextureCount));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x0045C,
++ 0x00470,
++ 24,
++ 7,
++ &info.psInstructionCount));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x0045C,
++ 0x00470,
++ 24,
++ 14,
++ &info.psTextureCount));
++#if gcdFRAME_DB_RESET
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x0045C,
++ 0x00470,
++ 24,
++ 15,
++ &reset));
++#endif
++
++ /* Read PA counters and reset them. */
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00460,
++ 0x00474,
++ 0,
++ 3,
++ &info.vertexCount));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00460,
++ 0x00474,
++ 0,
++ 4,
++ &info.primitiveCount));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00460,
++ 0x00474,
++ 0,
++ 7,
++ &info.rejectedPrimitives));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00460,
++ 0x00474,
++ 0,
++ 8,
++ &info.culledPrimitives));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00460,
++ 0x00474,
++ 0,
++ 6,
++ &info.clippedPrimitives));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00460,
++ 0x00474,
++ 0,
++ 5,
++ &info.outPrimitives));
++#if gcdFRAME_DB_RESET
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00460,
++ 0x00474,
++ 0,
++ 15,
++ &reset));
++#endif
++
++ /* Read RA counters and reset them. */
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00448,
++ 0x00474,
++ 16,
++ 3,
++ &info.inPrimitives));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00448,
++ 0x00474,
++ 16,
++ 11,
++ &info.culledQuadCount));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00448,
++ 0x00474,
++ 16,
++ 1,
++ &info.totalQuadCount));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00448,
++ 0x00474,
++ 16,
++ 2,
++ &info.quadCount));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00448,
++ 0x00474,
++ 16,
++ 0,
++ &info.totalPixelCount));
++#if gcdFRAME_DB_RESET
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00448,
++ 0x00474,
++ 16,
++ 15,
++ &reset));
++#endif
++
++ /* Read TX counters and reset them. */
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x0044C,
++ 0x00474,
++ 24,
++ 0,
++ &info.bilinearRequests));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x0044C,
++ 0x00474,
++ 24,
++ 1,
++ &info.trilinearRequests));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x0044C,
++ 0x00474,
++ 24,
++ 8,
++ &info.txHitCount));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x0044C,
++ 0x00474,
++ 24,
++ 9,
++ &info.txMissCount));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x0044C,
++ 0x00474,
++ 24,
++ 6,
++ &info.txBytes8));
++#if gcdFRAME_DB_RESET
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x0044C,
++ 0x00474,
++ 24,
++ 15,
++ &reset));
++#endif
++
++ /* Read clock control register. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ &clock));
++
++ /* Walk through all avaiable pixel pipes. */
++ for (i = 0; i < Hardware->identity.pixelPipes; ++i)
++ {
++ /* Select proper pipe. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ ((((gctUINT32) (clock)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:20) - (0 ? 23:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:20) - (0 ? 23:20) + 1))))))) << (0 ? 23:20))) | (((gctUINT32) ((gctUINT32) (i) & ((gctUINT32) ((((1 ? 23:20) - (0 ? 23:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:20) - (0 ? 23:20) + 1))))))) << (0 ? 23:20)))));
++
++ /* Read cycle registers. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00078,
++ &info.cycles[i]));
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0007C,
++ &info.idleCycles[i]));
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00438,
++ &info.mcCycles[i]));
++
++ /* Read bandwidth registers. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0005C,
++ &info.readRequests[i]));
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00040,
++ &info.readBytes8[i]));
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00050,
++ &info.writeRequests[i]));
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00044,
++ &info.writeBytes8[i]));
++
++ /* Read PE counters. */
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00454,
++ 0x00470,
++ 16,
++ 0,
++ &info.colorKilled[i]));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00454,
++ 0x00470,
++ 16,
++ 2,
++ &info.colorDrawn[i]));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00454,
++ 0x00470,
++ 16,
++ 1,
++ &info.depthKilled[i]));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00454,
++ 0x00470,
++ 16,
++ 3,
++ &info.depthDrawn[i]));
++ }
++
++ /* Zero out remaning reserved counters. */
++ for (; i < 8; ++i)
++ {
++ info.readBytes8[i] = 0;
++ info.writeBytes8[i] = 0;
++ info.cycles[i] = 0;
++ info.idleCycles[i] = 0;
++ info.mcCycles[i] = 0;
++ info.readRequests[i] = 0;
++ info.writeRequests[i] = 0;
++ info.colorKilled[i] = 0;
++ info.colorDrawn[i] = 0;
++ info.depthKilled[i] = 0;
++ info.depthDrawn[i] = 0;
++ }
++
++ /* Reset clock control register. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ clock));
++
++ /* Reset cycle and bandwidth counters. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0003C,
++ 1));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0003C,
++ 0));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00078,
++ 0));
++
++#if gcdFRAME_DB_RESET
++ /* Reset PE counters. */
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00454,
++ 0x00470,
++ 16,
++ 15,
++ &reset));
++#endif
++
++ /* Copy to user. */
++ gcmkONERROR(gckOS_CopyToUserData(Hardware->os,
++ &info,
++ FrameInfo,
++ gcmSIZEOF(info)));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++#endif
++
++#if gcdDVFS
++#define READ_FROM_EATER1 0
++
++gceSTATUS
++gckHARDWARE_QueryLoad(
++ IN gckHARDWARE Hardware,
++ OUT gctUINT32 * Load
++ )
++{
++ gctUINT32 debug1;
++ gceSTATUS status;
++ gcmkHEADER_ARG("Hardware=0x%X", Hardware);
++
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(Load != gcvNULL);
++
++ gckOS_AcquireMutex(Hardware->os, Hardware->powerMutex, gcvINFINITE);
++
++ if (Hardware->chipPowerState == gcvPOWER_ON)
++ {
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00110,
++ Load));
++#if READ_FROM_EATER1
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00134,
++ Load));
++#endif
++
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00114,
++ &debug1));
++
++ /* Patch result of 0x110 with result of 0x114. */
++ if ((debug1 & 0xFF) == 1)
++ {
++ *Load &= ~0xFF;
++ *Load |= 1;
++ }
++
++ if (((debug1 & 0xFF00) >> 8) == 1)
++ {
++ *Load &= ~(0xFF << 8);
++ *Load |= 1 << 8;
++ }
++
++ if (((debug1 & 0xFF0000) >> 16) == 1)
++ {
++ *Load &= ~(0xFF << 16);
++ *Load |= 1 << 16;
++ }
++
++ if (((debug1 & 0xFF000000) >> 24) == 1)
++ {
++ *Load &= ~(0xFF << 24);
++ *Load |= 1 << 24;
++ }
++ }
++ else
++ {
++ status = gcvSTATUS_INVALID_REQUEST;
++ }
++
++OnError:
++
++ gckOS_ReleaseMutex(Hardware->os, Hardware->powerMutex);
++
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckHARDWARE_SetDVFSPeroid(
++ IN gckHARDWARE Hardware,
++ OUT gctUINT32 Frequency
++ )
++{
++ gceSTATUS status;
++ gctUINT32 period;
++ gctUINT32 eater;
++
++#if READ_FROM_EATER1
++ gctUINT32 period1;
++ gctUINT32 eater1;
++#endif
++
++ gcmkHEADER_ARG("Hardware=0x%X Frequency=%d", Hardware, Frequency);
++
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ period = 0;
++
++ while((64 << period) < (gcdDVFS_ANAYLSE_WINDOW * Frequency * 1000) )
++ {
++ period++;
++ }
++
++#if READ_FROM_EATER1
++ /*
++ * Peroid = F * 1000 * 1000 / (60 * 16 * 1024);
++ */
++ period1 = Frequency * 6250 / 6114;
++#endif
++
++ gckOS_AcquireMutex(Hardware->os, Hardware->powerMutex, gcvINFINITE);
++
++ if (Hardware->chipPowerState == gcvPOWER_ON)
++ {
++ /* Get current configure. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0010C,
++ &eater));
++
++ /* Change peroid. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0010C,
++ ((((gctUINT32) (eater)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (period) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8)))));
++
++#if READ_FROM_EATER1
++ /* Config eater1. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00130,
++ &eater1));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00130,
++ ((((gctUINT32) (eater1)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:16) - (0 ? 31:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:16) - (0 ? 31:16) + 1))))))) << (0 ? 31:16))) | (((gctUINT32) ((gctUINT32) (period1) & ((gctUINT32) ((((1 ? 31:16) - (0 ? 31:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:16) - (0 ? 31:16) + 1))))))) << (0 ? 31:16)))));
++#endif
++ }
++ else
++ {
++ status = gcvSTATUS_INVALID_REQUEST;
++ }
++
++OnError:
++ gckOS_ReleaseMutex(Hardware->os, Hardware->powerMutex);
++
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckHARDWARE_InitDVFS(
++ IN gckHARDWARE Hardware
++ )
++{
++ gceSTATUS status;
++ gctUINT32 data;
++
++ gcmkHEADER_ARG("Hardware=0x%X", Hardware);
++
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0010C,
++ &data));
++
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) << (0 ? 16:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) << (0 ? 16:16)));
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 18:18) - (0 ? 18:18) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 18:18) - (0 ? 18:18) + 1))))))) << (0 ? 18:18))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 18:18) - (0 ? 18:18) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 18:18) - (0 ? 18:18) + 1))))))) << (0 ? 18:18)));
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19)));
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 20:20) - (0 ? 20:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:20) - (0 ? 20:20) + 1))))))) << (0 ? 20:20))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 20:20) - (0 ? 20:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:20) - (0 ? 20:20) + 1))))))) << (0 ? 20:20)));
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:23) - (0 ? 23:23) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:23) - (0 ? 23:23) + 1))))))) << (0 ? 23:23))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 23:23) - (0 ? 23:23) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:23) - (0 ? 23:23) + 1))))))) << (0 ? 23:23)));
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 22:22) - (0 ? 22:22) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 22:22) - (0 ? 22:22) + 1))))))) << (0 ? 22:22))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 22:22) - (0 ? 22:22) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 22:22) - (0 ? 22:22) + 1))))))) << (0 ? 22:22)));
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "DVFS Configure=0x%X",
++ data);
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0010C,
++ data));
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++#endif
++
++
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/arch/XAQ2/hal/kernel/gc_hal_kernel_hardware.h linux-xbian-imx6/drivers/mxc/gpu-viv/arch/XAQ2/hal/kernel/gc_hal_kernel_hardware.h
+--- linux-4.1.3/drivers/mxc/gpu-viv/arch/XAQ2/hal/kernel/gc_hal_kernel_hardware.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/arch/XAQ2/hal/kernel/gc_hal_kernel_hardware.h 2015-07-27 23:13:06.170964992 +0200
+@@ -0,0 +1,136 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_kernel_hardware_h_
++#define __gc_hal_kernel_hardware_h_
++
++#if gcdENABLE_VG
++#include "gc_hal_kernel_hardware_vg.h"
++#endif
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/* gckHARDWARE object. */
++struct _gckHARDWARE
++{
++ /* Object. */
++ gcsOBJECT object;
++
++ /* Pointer to gctKERNEL object. */
++ gckKERNEL kernel;
++
++ /* Pointer to gctOS object. */
++ gckOS os;
++
++ /* Core */
++ gceCORE core;
++
++ /* Chip characteristics. */
++ gcsHAL_QUERY_CHIP_IDENTITY identity;
++ gctBOOL allowFastClear;
++ gctBOOL allowCompression;
++ gctUINT32 powerBaseAddress;
++ gctBOOL extraEventStates;
++
++ /* Big endian */
++ gctBOOL bigEndian;
++
++ /* Chip status */
++ gctPOINTER powerMutex;
++ gctUINT32 powerProcess;
++ gctUINT32 powerThread;
++ gceCHIPPOWERSTATE chipPowerState;
++ gctUINT32 lastWaitLink;
++ gctBOOL clockState;
++ gctBOOL powerState;
++ gctPOINTER globalSemaphore;
++
++ gctISRMANAGERFUNC startIsr;
++ gctISRMANAGERFUNC stopIsr;
++ gctPOINTER isrContext;
++
++ gctUINT32 mmuVersion;
++
++ /* Type */
++ gceHARDWARE_TYPE type;
++
++#if gcdPOWEROFF_TIMEOUT
++ gctUINT32 powerOffTime;
++ gctUINT32 powerOffTimeout;
++ gctPOINTER powerOffTimer;
++#endif
++
++ gctPOINTER pageTableDirty;
++
++#if gcdENABLE_FSCALE_VAL_ADJUST
++ /* FSCALE_VAL when gcvPOWER_ON. */
++ gctUINT32 powerOnFscaleVal;
++#endif
++
++#if gcdLINK_QUEUE_SIZE
++ struct _gckLINKQUEUE linkQueue;
++#endif
++
++ gctBOOL powerManagement;
++ gctBOOL gpuProfiler;
++};
++
++gceSTATUS
++gckHARDWARE_GetBaseAddress(
++ IN gckHARDWARE Hardware,
++ OUT gctUINT32_PTR BaseAddress
++ );
++
++gceSTATUS
++gckHARDWARE_NeedBaseAddress(
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 State,
++ OUT gctBOOL_PTR NeedBase
++ );
++
++gceSTATUS
++gckHARDWARE_GetFrameInfo(
++ IN gckHARDWARE Hardware,
++ OUT gcsHAL_FRAME_INFO * FrameInfo
++ );
++
++gceSTATUS
++gckHARDWARE_SetFscaleValue(
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 FscaleValue
++ );
++
++gceSTATUS
++gckHARDWARE_GetFscaleValue(
++ IN gckHARDWARE Hardware,
++ IN gctUINT * FscaleValue,
++ IN gctUINT * MinFscaleValue,
++ IN gctUINT * MaxFscaleValue
++ );
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __gc_hal_kernel_hardware_h_ */
++
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/config linux-xbian-imx6/drivers/mxc/gpu-viv/config
+--- linux-4.1.3/drivers/mxc/gpu-viv/config 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/config 2015-07-27 23:13:06.170964992 +0200
+@@ -0,0 +1,38 @@
++##############################################################################
++#
++# Copyright (C) 2005 - 2013 by Vivante Corp.
++#
++# This program is free software; you can redistribute it and/or modify
++# it under the terms of the GNU General Public License as published by
++# the Free Software Foundation; either version 2 of the license, or
++# (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not write to the Free Software
++# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++#
++##############################################################################
++
++
++ARCH_TYPE ?= arm
++SDK_DIR ?= $(AQROOT)/build/sdk
++USE_3D_VG ?= 1
++FORCE_ALL_VIDEO_MEMORY_CACHED ?= 0
++NONPAGED_MEMORY_CACHEABLE ?= 0
++NONPAGED_MEMORY_BUFFERABLE ?= 1
++CACHE_FUNCTION_UNIMPLEMENTED ?= 0
++VIVANTE_ENABLE_VG ?= 1
++NO_USER_DIRECT_ACCESS_FROM_KERNEL ?= 1
++VIVANTE_NO_3D ?= 0
++ENABLE_OUTER_CACHE_PATCH ?= 1
++USE_BANK_ALIGNMENT ?= 1
++BANK_BIT_START ?= 13
++BANK_BIT_END ?= 15
++BANK_CHANNEL_BIT ?= 12
++ENABLE_GPU_CLOCK_BY_DRIVER = 1
++
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/arch/gc_hal_kernel_context.c linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/arch/gc_hal_kernel_context.c
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/arch/gc_hal_kernel_context.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/arch/gc_hal_kernel_context.c 2015-07-27 23:13:06.186908111 +0200
+@@ -0,0 +1,2317 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal.h"
++#include "gc_hal_kernel.h"
++#include "gc_hal_kernel_context.h"
++#include "gc_hal_kernel_buffer.h"
++
++/******************************************************************************\
++******************************** Debugging Macro *******************************
++\******************************************************************************/
++
++/* Zone used for header/footer. */
++#define _GC_OBJ_ZONE gcvZONE_HARDWARE
++
++
++/******************************************************************************\
++************************** Context State Buffer Helpers ************************
++\******************************************************************************/
++
++#define _STATE(reg) \
++ _State(\
++ Context, index, \
++ reg ## _Address >> 2, \
++ reg ## _ResetValue, \
++ reg ## _Count, \
++ gcvFALSE, gcvFALSE \
++ )
++
++#define _STATE_COUNT(reg, count) \
++ _State(\
++ Context, index, \
++ reg ## _Address >> 2, \
++ reg ## _ResetValue, \
++ count, \
++ gcvFALSE, gcvFALSE \
++ )
++
++#define _STATE_COUNT_OFFSET(reg, offset, count) \
++ _State(\
++ Context, index, \
++ (reg ## _Address >> 2) + offset, \
++ reg ## _ResetValue, \
++ count, \
++ gcvFALSE, gcvFALSE \
++ )
++
++#define _STATE_MIRROR_COUNT(reg, mirror, count) \
++ _StateMirror(\
++ Context, \
++ reg ## _Address >> 2, \
++ count, \
++ mirror ## _Address >> 2 \
++ )
++
++#define _STATE_HINT(reg) \
++ _State(\
++ Context, index, \
++ reg ## _Address >> 2, \
++ reg ## _ResetValue, \
++ reg ## _Count, \
++ gcvFALSE, gcvTRUE \
++ )
++
++#define _STATE_HINT_BLOCK(reg, block, count) \
++ _State(\
++ Context, index, \
++ (reg ## _Address >> 2) + (block << reg ## _BLK), \
++ reg ## _ResetValue, \
++ count, \
++ gcvFALSE, gcvTRUE \
++ )
++
++#define _STATE_COUNT_OFFSET_HINT(reg, offset, count) \
++ _State(\
++ Context, index, \
++ (reg ## _Address >> 2) + offset, \
++ reg ## _ResetValue, \
++ count, \
++ gcvFALSE, gcvTRUE \
++ )
++
++#define _STATE_X(reg) \
++ _State(\
++ Context, index, \
++ reg ## _Address >> 2, \
++ reg ## _ResetValue, \
++ reg ## _Count, \
++ gcvTRUE, gcvFALSE \
++ )
++
++#define _STATE_INIT_VALUE(reg, value) \
++ _State(\
++ Context, index, \
++ reg ## _Address >> 2, \
++ value, \
++ reg ## _Count, \
++ gcvFALSE, gcvFALSE \
++ )
++
++#define _CLOSE_RANGE() \
++ _TerminateStateBlock(Context, index)
++
++#define _ENABLE(reg, field) \
++ do \
++ { \
++ if (gcmVERIFYFIELDVALUE(data, reg, MASK_ ## field, ENABLED)) \
++ { \
++ enable |= gcmFIELDMASK(reg, field); \
++ } \
++ } \
++ while (gcvFALSE)
++
++#define _BLOCK_COUNT(reg) \
++ ((reg ## _Count) >> (reg ## _BLK))
++
++
++/******************************************************************************\
++*********************** Support Functions and Definitions **********************
++\******************************************************************************/
++
++#define gcdSTATE_MASK \
++ (((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x03 | 0xC0FFEE & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))))
++
++#if gcdENABLE_3D
++static gctUINT32
++_TerminateStateBlock(
++ IN gckCONTEXT Context,
++ IN gctUINT32 Index
++ )
++{
++ gctUINT32_PTR buffer;
++ gctUINT32 align;
++
++ /* Determine if we need alignment. */
++ align = (Index & 1) ? 1 : 0;
++
++ /* Address correct index. */
++ buffer = (Context->buffer == gcvNULL)
++ ? gcvNULL
++ : Context->buffer->logical;
++
++ /* Flush the current state block; make sure no pairing with the states
++ to follow happens. */
++ if (align && (buffer != gcvNULL))
++ {
++ buffer[Index] = 0xDEADDEAD;
++ }
++
++ /* Reset last address. */
++ Context->lastAddress = ~0U;
++
++ /* Return alignment requirement. */
++ return align;
++}
++#endif
++
++
++#if (gcdENABLE_3D || gcdENABLE_2D)
++static gctUINT32
++_FlushPipe(
++ IN gckCONTEXT Context,
++ IN gctUINT32 Index,
++ IN gcePIPE_SELECT Pipe
++ )
++{
++ gctBOOL fcFlushStall;
++ gctUINT32 flushSlots;
++ gctBOOL iCacheInvalidate;
++
++ fcFlushStall
++ = gckHARDWARE_IsFeatureAvailable(Context->hardware, gcvFEATURE_FC_FLUSH_STALL);
++
++ iCacheInvalidate
++ = ((((gctUINT32) (Context->hardware->identity.chipMinorFeatures3)) >> (0 ? 3:3) & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1)))))));
++
++ flushSlots = 6;
++
++ if (fcFlushStall)
++ {
++ /* Flush tile status cache. */
++ flushSlots += 6;
++ }
++
++ if (iCacheInvalidate)
++ {
++ flushSlots += 12;
++ }
++
++ if (Context->buffer != gcvNULL)
++ {
++ gctUINT32_PTR buffer;
++
++ /* Address correct index. */
++ buffer = Context->buffer->logical + Index;
++
++ /* Flush the current pipe. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E03) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ *buffer++
++ = (Pipe == gcvPIPE_2D)
++ ? ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3)))
++ : ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5)));
++
++ /* Semaphore from FE to PE. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /* Stall from FE to PE. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ if (fcFlushStall)
++ {
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0594) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)));
++
++ /* Semaphore from FE to PE. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /* Stall from FE to PE. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++ }
++
++ if (iCacheInvalidate)
++ {
++ /* Invalidate I$ after pipe is stalled */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0218) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x021A) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0218) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x021A) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5)));
++
++ /* Semaphore from FE to PE. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /* Stall from FE to PE. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++ }
++ }
++
++ /* Number of slots taken by flushing pipe. */
++ return flushSlots;
++}
++#endif
++
++#if gcdENABLE_3D
++static gctUINT32
++_SemaphoreStall(
++ IN gckCONTEXT Context,
++ IN gctUINT32 Index
++ )
++{
++ if (Context->buffer != gcvNULL)
++ {
++ gctUINT32_PTR buffer;
++
++ /* Address correct index. */
++ buffer = Context->buffer->logical + Index;
++
++ /* Semaphore from FE to PE. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /* Stall from FE to PE. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++
++ *buffer
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++ }
++
++ /* Semaphore/stall takes 4 slots. */
++ return 4;
++}
++#endif
++
++#if (gcdENABLE_3D || gcdENABLE_2D)
++static gctUINT32
++_SwitchPipe(
++ IN gckCONTEXT Context,
++ IN gctUINT32 Index,
++ IN gcePIPE_SELECT Pipe
++ )
++{
++ gctUINT32 slots = 6;
++
++ if (Context->buffer != gcvNULL)
++ {
++ gctUINT32_PTR buffer;
++
++ /* Address correct index. */
++ buffer = Context->buffer->logical + Index;
++
++ /* LoadState(AQPipeSelect, 1), pipe. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E00) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ *buffer++
++ = (Pipe == gcvPIPE_2D)
++ ? 0x1
++ : 0x0;
++
++ /* Semaphore from FE to PE. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /* Stall from FE to PE. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++ }
++
++ Context->pipeSelectBytes = slots * gcmSIZEOF(gctUINT32);
++
++ return slots;
++}
++#endif
++
++#if gcdENABLE_3D
++static gctUINT32
++_State(
++ IN gckCONTEXT Context,
++ IN gctUINT32 Index,
++ IN gctUINT32 Address,
++ IN gctUINT32 Value,
++ IN gctUINT32 Size,
++ IN gctBOOL FixedPoint,
++ IN gctBOOL Hinted
++ )
++{
++ gctUINT32_PTR buffer;
++ gctUINT32 align;
++ gctUINT32 i;
++
++ /* Determine if we need alignment. */
++ align = (Index & 1) ? 1 : 0;
++
++ /* Address correct index. */
++ buffer = (Context->buffer == gcvNULL)
++ ? gcvNULL
++ : Context->buffer->logical;
++
++ if ((buffer == gcvNULL) && (Address + Size > Context->stateCount))
++ {
++ /* Determine maximum state. */
++ Context->stateCount = Address + Size;
++ }
++
++ /* Do we need a new entry? */
++ if ((Address != Context->lastAddress) || (FixedPoint != Context->lastFixed))
++ {
++ if (buffer != gcvNULL)
++ {
++ if (align)
++ {
++ /* Add filler. */
++ buffer[Index++] = 0xDEADDEAD;
++ }
++
++ /* LoadState(Address, Count). */
++ gcmkASSERT((Index & 1) == 0);
++
++ if (FixedPoint)
++ {
++ buffer[Index]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 26:26) - (0 ? 26:26) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 26:26) - (0 ? 26:26) + 1))))))) << (0 ? 26:26))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 26:26) - (0 ? 26:26) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 26:26) - (0 ? 26:26) + 1))))))) << (0 ? 26:26)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (Size) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (Address) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++ }
++ else
++ {
++ buffer[Index]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 26:26) - (0 ? 26:26) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 26:26) - (0 ? 26:26) + 1))))))) << (0 ? 26:26))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 26:26) - (0 ? 26:26) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 26:26) - (0 ? 26:26) + 1))))))) << (0 ? 26:26)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (Size) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (Address) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++ }
++
++ /* Walk all the states. */
++ for (i = 0; i < (gctUINT32)Size; i += 1)
++ {
++ /* Set state to uninitialized value. */
++ buffer[Index + 1 + i] = Value;
++
++ /* Set index in state mapping table. */
++ Context->map[Address + i].index = (gctUINT)Index + 1 + i;
++
++#if gcdSECURE_USER
++ /* Save hint. */
++ if (Context->hint != gcvNULL)
++ {
++ Context->hint[Address + i] = Hinted;
++ }
++#endif
++ }
++ }
++
++ /* Save information for this LoadState. */
++ Context->lastIndex = (gctUINT)Index;
++ Context->lastAddress = Address + (gctUINT32)Size;
++ Context->lastSize = Size;
++ Context->lastFixed = FixedPoint;
++
++ /* Return size for load state. */
++ return align + 1 + Size;
++ }
++
++ /* Append this state to the previous one. */
++ if (buffer != gcvNULL)
++ {
++ /* Update last load state. */
++ buffer[Context->lastIndex] =
++ ((((gctUINT32) (buffer[Context->lastIndex])) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (Context->lastSize + Size) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ /* Walk all the states. */
++ for (i = 0; i < (gctUINT32)Size; i += 1)
++ {
++ /* Set state to uninitialized value. */
++ buffer[Index + i] = Value;
++
++ /* Set index in state mapping table. */
++ Context->map[Address + i].index = (gctUINT)Index + i;
++
++#if gcdSECURE_USER
++ /* Save hint. */
++ if (Context->hint != gcvNULL)
++ {
++ Context->hint[Address + i] = Hinted;
++ }
++#endif
++ }
++ }
++
++ /* Update last address and size. */
++ Context->lastAddress += (gctUINT32)Size;
++ Context->lastSize += Size;
++
++ /* Return number of slots required. */
++ return Size;
++}
++
++static gctUINT32
++_StateMirror(
++ IN gckCONTEXT Context,
++ IN gctUINT32 Address,
++ IN gctUINT32 Size,
++ IN gctUINT32 AddressMirror
++ )
++{
++ gctUINT32 i;
++
++ /* Process when buffer is set. */
++ if (Context->buffer != gcvNULL)
++ {
++ /* Walk all states. */
++ for (i = 0; i < Size; i++)
++ {
++ /* Copy the mapping address. */
++ Context->map[Address + i].index =
++ Context->map[AddressMirror + i].index;
++ }
++ }
++
++ /* Return the number of required maps. */
++ return Size;
++}
++#endif
++
++#if (gcdENABLE_3D || gcdENABLE_2D)
++static gceSTATUS
++_InitializeContextBuffer(
++ IN gckCONTEXT Context
++ )
++{
++ gctUINT32_PTR buffer;
++ gctUINT32 index;
++
++#if gcdENABLE_3D
++ gctBOOL halti0, halti1, halti2, halti3;
++ gctUINT i;
++ gctUINT vertexUniforms, fragmentUniforms, vsConstBase, psConstBase, constMax;
++ gctBOOL unifiedUniform;
++ gctUINT fe2vsCount;
++#endif
++
++ /* Reset the buffer index. */
++ index = 0;
++
++ /* Reset the last state address. */
++ Context->lastAddress = ~0U;
++
++ /* Get the buffer pointer. */
++ buffer = (Context->buffer == gcvNULL)
++ ? gcvNULL
++ : Context->buffer->logical;
++
++
++ /**************************************************************************/
++ /* Build 2D states. *******************************************************/
++
++
++#if gcdENABLE_3D
++ /**************************************************************************/
++ /* Build 3D states. *******************************************************/
++
++ halti0 = (((((gctUINT32) (Context->hardware->identity.chipMinorFeatures1)) >> (0 ? 23:23)) & ((gctUINT32) ((((1 ? 23:23) - (0 ? 23:23) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:23) - (0 ? 23:23) + 1)))))) );
++ halti1 = (((((gctUINT32) (Context->hardware->identity.chipMinorFeatures2)) >> (0 ? 11:11)) & ((gctUINT32) ((((1 ? 11:11) - (0 ? 11:11) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:11) - (0 ? 11:11) + 1)))))) );
++ halti2 = (((((gctUINT32) (Context->hardware->identity.chipMinorFeatures4)) >> (0 ? 16:16)) & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1)))))) );
++ halti3 = (((((gctUINT32) (Context->hardware->identity.chipMinorFeatures5)) >> (0 ? 9:9)) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1)))))) );
++
++ /* Query how many uniforms can support for non-unified uniform mode. */
++ {if (Context->hardware->identity.numConstants > 256){ unifiedUniform = gcvTRUE; vsConstBase = 0xC000; psConstBase = 0xC000; constMax = Context->hardware->identity.numConstants; vertexUniforms = 256; fragmentUniforms = constMax - vertexUniforms;}else if (Context->hardware->identity.numConstants == 256){ if (Context->hardware->identity.chipModel == gcv2000 && Context->hardware->identity.chipRevision == 0x5118) { unifiedUniform = gcvFALSE; vsConstBase = 0x1400; psConstBase = 0x1C00; vertexUniforms = 256; fragmentUniforms = 64; constMax = 320; } else { unifiedUniform = gcvFALSE; vsConstBase = 0x1400; psConstBase = 0x1C00; vertexUniforms = 256; fragmentUniforms = 256; constMax = 512; }}else{ unifiedUniform = gcvFALSE; vsConstBase = 0x1400; psConstBase = 0x1C00; vertexUniforms = 168; fragmentUniforms = 64; constMax = 232;}};
++
++#if !gcdENABLE_UNIFIED_CONSTANT
++ if (Context->hardware->identity.numConstants > 256)
++ {
++ unifiedUniform = gcvTRUE;
++ }
++ else
++ {
++ unifiedUniform = gcvFALSE;
++ }
++#endif
++
++ /* Store the 3D entry index. */
++ Context->entryOffset3D = (gctUINT)index * gcmSIZEOF(gctUINT32);
++
++ /* Switch to 3D pipe. */
++ index += _SwitchPipe(Context, index, gcvPIPE_3D);
++
++ /* Current context pointer. */
++#if gcdDEBUG
++ index += _State(Context, index, 0x03850 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++#endif
++
++ index += _FlushPipe(Context, index, gcvPIPE_3D);
++
++ /* Global states. */
++ index += _State(Context, index, 0x03814 >> 2, 0x00000001, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x03818 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0381C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x03820 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x03828 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0382C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x03834 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x03838 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x03854 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0384C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++
++ /* Front End states. */
++ fe2vsCount = 12;
++ if (halti0)
++ {
++ fe2vsCount = 16;
++ }
++ index += _State(Context, index, 0x00600 >> 2, 0x00000000, fe2vsCount, gcvFALSE, gcvFALSE);
++ index += _CLOSE_RANGE();
++
++ index += _State(Context, index, 0x00644 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x00648 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0064C >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x00650 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00680 >> 2, 0x00000000, 8, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x006A0 >> 2, 0x00000000, 8, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00674 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00670 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00678 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0067C >> 2, 0xFFFFFFFF, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x006C0 >> 2, 0x00000000, 16, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00700 >> 2, 0x00000000, 16, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00740 >> 2, 0x00000000, 16, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00780 >> 2, 0x3F800000, 16, gcvFALSE, gcvFALSE);
++
++ if (halti2)
++ {
++ index += _State(Context, index, 0x14600 >> 2, 0x00000000, 16, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14640 >> 2, 0x00000000, 16, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14680 >> 2, 0x00000000, 16, gcvFALSE, gcvFALSE);
++ }
++
++ /* This register is programed by all chips, which program all DECODE_SELECT as VS
++ ** except SAMPLER_DECODE_SELECT.
++ */
++ index += _State(Context, index, 0x00860 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++
++ if (((((gctUINT32) (Context->hardware->identity.chipMinorFeatures3)) >> (0 ? 3:3) & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))))
++ {
++ /* I-Cache states. */
++ index += _State(Context, index, 0x00868 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0086C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0304C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01028 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _CLOSE_RANGE();
++
++ if (halti3)
++ {
++ index += _State(Context, index, 0x00890 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x0104C >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _CLOSE_RANGE();
++ }
++ }
++
++ /* Vertex Shader states. */
++ index += _State(Context, index, 0x00804 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00808 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0080C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00810 >> 2, 0x00000000, 4, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00820 >> 2, 0x00000000, 4, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00830 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++
++ index += _CLOSE_RANGE();
++
++ /* Primitive Assembly states. */
++ index += _State(Context, index, 0x00A00 >> 2, 0x00000000, 1, gcvTRUE, gcvFALSE);
++ index += _State(Context, index, 0x00A04 >> 2, 0x00000000, 1, gcvTRUE, gcvFALSE);
++ index += _State(Context, index, 0x00A08 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00A0C >> 2, 0x00000000, 1, gcvTRUE, gcvFALSE);
++ index += _State(Context, index, 0x00A10 >> 2, 0x00000000, 1, gcvTRUE, gcvFALSE);
++ index += _State(Context, index, 0x00A14 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00A18 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00A1C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00A28 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00A2C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00A30 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00A40 >> 2, 0x00000000, Context->hardware->identity.varyingsCount, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00A34 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00A38 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00A3C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00A80 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00A84 >> 2, 0x00000000, 1, gcvTRUE, gcvFALSE);
++ index += _State(Context, index, 0x00A8C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00A88 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++
++#if gcdMULTI_GPU
++ index += _State(Context, index, 0x03A00 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x03A04 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x03A08 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++#endif
++ /* Setup states. */
++ index += _State(Context, index, 0x00C00 >> 2, 0x00000000, 1, gcvTRUE, gcvFALSE);
++ index += _State(Context, index, 0x00C04 >> 2, 0x00000000, 1, gcvTRUE, gcvFALSE);
++ index += _State(Context, index, 0x00C08 >> 2, 0x45000000, 1, gcvTRUE, gcvFALSE);
++ index += _State(Context, index, 0x00C0C >> 2, 0x45000000, 1, gcvTRUE, gcvFALSE);
++ index += _State(Context, index, 0x00C10 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00C14 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00C18 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00C1C >> 2, 0x42000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00C20 >> 2, 0x00000000, 1, gcvTRUE, gcvFALSE);
++ index += _State(Context, index, 0x00C24 >> 2, 0x00000000, 1, gcvTRUE, gcvFALSE);
++
++ /* Raster states. */
++ index += _State(Context, index, 0x00E00 >> 2, 0x00000001, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00E10 >> 2, 0x00000000, 4, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00E04 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00E40 >> 2, 0x00000000, 16, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00E08 >> 2, 0x00000031, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00E24 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00E20 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++
++ if (halti2)
++ {
++ index += _State(Context, index, 0x00E0C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ }
++
++ /* Pixel Shader states. */
++ index += _State(Context, index, 0x01004 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01008 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0100C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01010 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01030 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++
++ index += _CLOSE_RANGE();
++
++ /* Texture states. */
++ index += _State(Context, index, 0x02000 >> 2, 0x00000000, 12, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x02040 >> 2, 0x00000000, 12, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x02080 >> 2, 0x00000000, 12, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x020C0 >> 2, 0x00000000, 12, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x02100 >> 2, 0x00000000, 12, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x02140 >> 2, 0x00000000, 12, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x02180 >> 2, 0x00000000, 12, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x021C0 >> 2, 0x00321000, 12, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x02200 >> 2, 0x00000000, 12, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x02240 >> 2, 0x00000000, 12, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, (0x02400 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x02440 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x02480 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x024C0 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x02500 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x02540 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x02580 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x025C0 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x02600 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x02640 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x02680 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x026C0 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x02700 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x02740 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _CLOSE_RANGE();
++
++ if ((((((gctUINT32) (Context->hardware->identity.chipMinorFeatures1)) >> (0 ? 22:22)) & ((gctUINT32) ((((1 ? 22:22) - (0 ? 22:22) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 22:22) - (0 ? 22:22) + 1)))))) ))
++ {
++ /*
++ * Linear stride LODn will overwrite LOD0 on GC880,GC2000.
++ * And only LOD0 is valid for this register.
++ */
++ gctUINT count = halti1 ? 14 : 1;
++
++ for (i = 0; i < 12; i += 1)
++ {
++ index += _State(Context, index, (0x02C00 >> 2) + i * 16, 0x00000000, count, gcvFALSE, gcvFALSE);
++ }
++ }
++
++ if (halti1)
++ {
++ gctUINT texBlockCount;
++ gctUINT gcregTXLogSizeResetValue;
++
++ /* Enable the integer filter pipe for all texture samplers
++ so that the floating point filter clock will shut off until
++ we start using the floating point filter.
++ */
++ gcregTXLogSizeResetValue = ((((gctUINT32) (0x00000000)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 29:29) - (0 ? 29:29) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 29:29) - (0 ? 29:29) + 1))))))) << (0 ? 29:29))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 29:29) - (0 ? 29:29) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 29:29) - (0 ? 29:29) + 1))))))) << (0 ? 29:29)));
++
++ /* New texture block. */
++ index += _State(Context, index, 0x10000 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x10080 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x10100 >> 2, gcregTXLogSizeResetValue, 32, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x10180 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x10200 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x10280 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x10300 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x10380 >> 2, 0x00321000, 32, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x10400 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x10480 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE);
++
++ if ((((((gctUINT32) (Context->hardware->identity.chipMinorFeatures2)) >> (0 ? 15:15)) & ((gctUINT32) ((((1 ? 15:15) - (0 ? 15:15) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:15) - (0 ? 15:15) + 1)))))) ))
++ {
++ index += _State(Context, index, 0x12000 >> 2, 0x00000000, 256, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x12400 >> 2, 0x00000000, 256, gcvFALSE, gcvFALSE);
++ }
++
++ texBlockCount = ((512) >> (4));
++
++ for (i = 0; i < texBlockCount; i += 1)
++ {
++ index += _State(Context, index, (0x10800 >> 2) + (i << 4), 0x00000000, 14, gcvFALSE, gcvTRUE);
++ }
++ }
++
++ if (halti2)
++ {
++ index += _State(Context, index, 0x10700 >> 2, 0x00000F00, 32, gcvFALSE, gcvFALSE);
++ }
++
++ if (halti3)
++ {
++ index += _State(Context, index, 0x10780 >> 2, 0x00030000, 32, gcvFALSE, gcvFALSE);
++ }
++
++ /* ASTC */
++ if ((((((gctUINT32) (Context->hardware->identity.chipMinorFeatures4)) >> (0 ? 13:13)) & ((gctUINT32) ((((1 ? 13:13) - (0 ? 13:13) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 13:13) - (0 ? 13:13) + 1)))))) ))
++ {
++ index += _State(Context, index, 0x10500 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x10580 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x10600 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x10680 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE);
++ }
++
++ /* YUV. */
++ index += _State(Context, index, 0x01678 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0167C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01680 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x01684 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01688 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x0168C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01690 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x01694 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01698 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x0169C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _CLOSE_RANGE();
++
++ /* Thread walker states. */
++ index += _State(Context, index, 0x00900 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00904 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00908 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0090C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00910 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00914 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00918 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0091C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00924 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++
++ if (((((gctUINT32) (Context->hardware->identity.chipMinorFeatures3)) >> (0 ? 21:21) & ((gctUINT32) ((((1 ? 21:21) - (0 ? 21:21) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 21:21) - (0 ? 21:21) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 21:21) - (0 ? 21:21) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 21:21) - (0 ? 21:21) + 1))))))))
++ {
++ index += _State(Context, index, 0x00940 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00944 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00948 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0094C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00950 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00954 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ }
++
++ index += _CLOSE_RANGE();
++
++ if (!halti3)
++ {
++ if (Context->hardware->identity.instructionCount > 1024)
++ {
++ /* New Shader instruction PC registers. */
++ index += _State(Context, index, 0x0085C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0101C >> 2, 0x00000100, 1, gcvFALSE, gcvFALSE);
++ index += _CLOSE_RANGE();
++
++ for (i = 0;
++ i < Context->hardware->identity.instructionCount << 2;
++ i += 256 << 2
++ )
++ {
++ index += _State(Context, index, (0x20000 >> 2) + i, 0x00000000, 256 << 2, gcvFALSE, gcvFALSE);
++ index += _CLOSE_RANGE();
++ }
++ }
++ else if (Context->hardware->identity.instructionCount > 256)
++ {
++ /* New Shader instruction PC registers. */
++ index += _State(Context, index, 0x0085C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0101C >> 2, 0x00000100, 1, gcvFALSE, gcvFALSE);
++ index += _CLOSE_RANGE();
++
++ /* VX instruction memory. */
++ for (i = 0;
++ i < Context->hardware->identity.instructionCount << 2;
++ i += 256 << 2
++ )
++ {
++ index += _State(Context, index, (0x0C000 >> 2) + i, 0x00000000, 256 << 2, gcvFALSE, gcvFALSE);
++ index += _CLOSE_RANGE();
++ }
++
++ _StateMirror(Context, 0x08000 >> 2, Context->hardware->identity.instructionCount << 2 , 0x0C000 >> 2);
++ }
++ else /* if (Context->hardware->identity.instructionCount <= 256) */
++ {
++ /* old shader instruction PC registers */
++ index += _State(Context, index, 0x00800 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00838 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _CLOSE_RANGE();
++
++ index += _State(Context, index, 0x01000 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01018 >> 2, 0x01000000, 1, gcvFALSE, gcvFALSE);
++ index += _CLOSE_RANGE();
++
++ index += _State(Context, index, 0x04000 >> 2, 0x00000000, 1024, gcvFALSE, gcvFALSE);
++ index += _CLOSE_RANGE();
++ index += _State(Context, index, 0x06000 >> 2, 0x00000000, 1024, gcvFALSE, gcvFALSE);
++ index += _CLOSE_RANGE();
++ }
++ }
++ /* I cache use the new instruction PC registers */
++ else
++ {
++ /* New Shader instruction PC registers. */
++ index += _State(Context, index, 0x0085C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0101C >> 2, 0x00000100, 1, gcvFALSE, gcvFALSE);
++ index += _CLOSE_RANGE();
++ }
++
++ if (unifiedUniform)
++ {
++ gctINT numConstants = Context->hardware->identity.numConstants;
++
++ index += _State(Context, index, 0x01024 >> 2, 0x00000100, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00864 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _CLOSE_RANGE();
++
++ for (i = 0;
++ numConstants > 0;
++ i += 256 << 2,
++ numConstants -= 256
++ )
++ {
++ if (numConstants >= 256)
++ {
++ index += _State(Context, index, (0x30000 >> 2) + i, 0x00000000, 256 << 2, gcvFALSE, gcvFALSE);
++ }
++ else
++ {
++ index += _State(Context, index, (0x30000 >> 2) + i, 0x00000000, numConstants << 2, gcvFALSE, gcvFALSE);
++ }
++ index += _CLOSE_RANGE();
++ }
++ }
++#if gcdENABLE_UNIFIED_CONSTANT
++ else
++#endif
++ {
++ index += _State(Context, index, 0x05000 >> 2, 0x00000000, vertexUniforms * 4, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x07000 >> 2, 0x00000000, fragmentUniforms * 4, gcvFALSE, gcvFALSE);
++ }
++
++ /* Store the index of the "XD" entry. */
++ Context->entryOffsetXDFrom3D = (gctUINT)index * gcmSIZEOF(gctUINT32);
++
++
++ /* Pixel Engine states. */
++ index += _State(Context, index, 0x01400 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01404 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01408 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0140C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01414 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01418 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0141C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01420 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01424 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01428 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0142C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01434 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01454 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01458 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x0145C >> 2, 0x00000010, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x014A0 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x014A8 >> 2, 0xFFFFFFFF, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x014AC >> 2, 0xFFFFFFFF, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x014B0 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x014B4 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x014A4 >> 2, 0x000E400C, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01580 >> 2, 0x00000000, 3, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x014B8 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++
++ /* Composition states. */
++ index += _State(Context, index, 0x03008 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++
++ if (Context->hardware->identity.pixelPipes == 1)
++ {
++ index += _State(Context, index, 0x01460 >> 2, 0x00000000, 8, gcvFALSE, gcvTRUE);
++
++ index += _State(Context, index, 0x01430 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x01410 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ }
++ else
++ {
++ index += _State(Context, index, (0x01460 >> 2) + (0 << 3), 0x00000000, Context->hardware->identity.pixelPipes, gcvFALSE, gcvTRUE);
++ }
++
++ if (Context->hardware->identity.pixelPipes > 1 || halti0)
++ {
++ index += _State(Context, index, (0x01480 >> 2) + (0 << 3), 0x00000000, Context->hardware->identity.pixelPipes, gcvFALSE, gcvTRUE);
++ }
++
++ for (i = 0; i < 3; i++)
++ {
++ index += _State(Context, index, (0x01500 >> 2) + (i << 3), 0x00000000, Context->hardware->identity.pixelPipes, gcvFALSE, gcvTRUE);
++ }
++
++ if (halti2)
++ {
++ for (i = 0; i < 7; i++)
++ {
++ index += _State(Context, index, (0x14800 >> 2) + (i << 3), 0x00000000, Context->hardware->identity.pixelPipes, gcvFALSE, gcvTRUE);
++ }
++ index += _State(Context, index, 0x14900 >> 2, 0x00000000, 7, gcvFALSE, gcvFALSE);
++ }
++
++
++ if (halti3)
++ {
++ index += _State(Context, index, 0x014BC >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ }
++
++ /* Resolve states. */
++ index += _State(Context, index, 0x01604 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01608 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x0160C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01610 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x01614 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01620 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01630 >> 2, 0x00000000, 2, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01640 >> 2, 0x00000000, 4, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0163C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x016A0 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x016B4 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _CLOSE_RANGE();
++
++ if ((Context->hardware->identity.pixelPipes > 1) || halti1)
++ {
++ index += _State(Context, index, (0x016C0 >> 2) + (0 << 3), 0x00000000, Context->hardware->identity.pixelPipes, gcvFALSE, gcvTRUE);
++
++ index += _State(Context, index, (0x016E0 >> 2) + (0 << 3), 0x00000000, Context->hardware->identity.pixelPipes, gcvFALSE, gcvTRUE);
++
++ index += _State(Context, index, 0x01700 >> 2, 0x00000000, Context->hardware->identity.pixelPipes, gcvFALSE, gcvFALSE);
++ }
++
++#if gcd3DBLIT
++ index += _State(Context, index, (0x14000 >> 2) + (0 << 1), 0x00000000, 2, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x14008 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x1400C >> 2, 0x0001C800, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14010 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x14014 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, (0x14018 >> 2) + (0 << 1), 0x00000000, 2, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x14020 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x14024 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14028 >> 2, 0x0001C800, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x1402C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14030 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14034 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14038 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x1403C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14040 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14044 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14048 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x1404C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14050 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14058 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x1405C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14054 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14100 >> 2, 0x00000000, 64, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14200 >> 2, 0x00000000, 64, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14064 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14068 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++
++ index += _State(Context, index, 0x1406C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14070 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14074 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14078 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x1407C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14080 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14084 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14088 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x1408C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14090 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++
++ index += _State(Context, index, 0x14094 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14098 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++#endif
++
++ /* Tile status. */
++ index += _State(Context, index, 0x01654 >> 2, 0x00200000, 1, gcvFALSE, gcvFALSE);
++
++ index += _CLOSE_RANGE();
++ index += _State(Context, index, 0x01658 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x0165C >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x01660 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01664 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x01668 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x0166C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01670 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01674 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x016A4 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x016AC >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x016A8 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01720 >> 2, 0x00000000, 8, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01740 >> 2, 0x00000000, 8, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x01760 >> 2, 0x00000000, 8, gcvFALSE, gcvFALSE);
++
++
++ if (halti2)
++ {
++ index += _State(Context, index, 0x01780 >> 2, 0x00000000, 8, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x016BC >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, (0x017A0 >> 2) + 1, 0x00000000, 7, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, (0x017C0 >> 2) + 1, 0x00000000, 7, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x017E0 >> 2) + 1, 0x00000000, 7, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x01A00 >> 2) + 1, 0x00000000, 7, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, (0x01A20 >> 2) + 1, 0x00000000, 7, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, (0x01A40 >> 2) + 1, 0x00000000, 7, gcvFALSE, gcvFALSE);
++ }
++
++ index += _CLOSE_RANGE();
++
++ if(((((gctUINT32) (Context->hardware->identity.chipMinorFeatures4)) >> (0 ? 25:25) & ((gctUINT32) ((((1 ? 25:25) - (0 ? 25:25) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:25) - (0 ? 25:25) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 25:25) - (0 ? 25:25) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:25) - (0 ? 25:25) + 1))))))))
++ {
++ index += _State(Context, index, 0x03860 >> 2, 0x6, 1, gcvFALSE, gcvFALSE);
++ index += _CLOSE_RANGE();
++ }
++
++ if (halti3)
++ {
++ index += _State(Context, index, 0x01A80 >> 2, 0x00000000, 8, gcvFALSE, gcvTRUE);
++ index += _CLOSE_RANGE();
++ }
++
++ /* Semaphore/stall. */
++ index += _SemaphoreStall(Context, index);
++#endif
++
++ /**************************************************************************/
++ /* Link to another address. ***********************************************/
++
++ Context->linkIndex3D = (gctUINT)index;
++
++ if (buffer != gcvNULL)
++ {
++ buffer[index + 0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x08 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ buffer[index + 1]
++ = 0;
++ }
++
++ index += 2;
++
++ /* Store the end of the context buffer. */
++ Context->bufferSize = index * gcmSIZEOF(gctUINT32);
++
++
++ /**************************************************************************/
++ /* Pipe switch for the case where neither 2D nor 3D are used. *************/
++
++ /* Store the 3D entry index. */
++ Context->entryOffsetXDFrom2D = (gctUINT)index * gcmSIZEOF(gctUINT32);
++
++ /* Flush 2D pipe. */
++ index += _FlushPipe(Context, index, gcvPIPE_2D);
++
++ /* Switch to 3D pipe. */
++ index += _SwitchPipe(Context, index, gcvPIPE_3D);
++
++ /* Store the location of the link. */
++ Context->linkIndexXD = (gctUINT)index;
++
++ if (buffer != gcvNULL)
++ {
++ buffer[index + 0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x08 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ buffer[index + 1]
++ = 0;
++ }
++
++ index += 2;
++
++
++ /**************************************************************************/
++ /* Save size for buffer. **************************************************/
++
++ Context->totalSize = index * gcmSIZEOF(gctUINT32);
++
++
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++#endif
++
++static gceSTATUS
++_DestroyContext(
++ IN gckCONTEXT Context
++ )
++{
++ gceSTATUS status = gcvSTATUS_OK;
++
++ if (Context != gcvNULL)
++ {
++ gcsCONTEXT_PTR bufferHead;
++
++ /* Free context buffers. */
++ for (bufferHead = Context->buffer; Context->buffer != gcvNULL;)
++ {
++ /* Get a shortcut to the current buffer. */
++ gcsCONTEXT_PTR buffer = Context->buffer;
++
++ /* Get the next buffer. */
++ gcsCONTEXT_PTR next = buffer->next;
++
++ /* Last item? */
++ if (next == bufferHead)
++ {
++ next = gcvNULL;
++ }
++
++ /* Destroy the signal. */
++ if (buffer->signal != gcvNULL)
++ {
++ gcmkONERROR(gckOS_DestroySignal(
++ Context->os, buffer->signal
++ ));
++
++ buffer->signal = gcvNULL;
++ }
++
++ /* Free state delta map. */
++ if (buffer->logical != gcvNULL)
++ {
++ if (Context->hardware->kernel->virtualCommandBuffer)
++ {
++ gcmkONERROR(gckEVENT_DestroyVirtualCommandBuffer(
++ Context->hardware->kernel->eventObj,
++ Context->totalSize,
++ buffer->physical,
++ buffer->logical,
++ gcvKERNEL_PIXEL
++ ));
++ }
++ else
++ {
++ gcmkONERROR(gckEVENT_FreeContiguousMemory(
++ Context->hardware->kernel->eventObj,
++ Context->totalSize,
++ buffer->physical,
++ buffer->logical,
++ gcvKERNEL_PIXEL
++ ));
++ }
++
++ buffer->logical = gcvNULL;
++ }
++
++ /* Free context buffer. */
++ gcmkONERROR(gcmkOS_SAFE_FREE(Context->os, buffer));
++
++ /* Remove from the list. */
++ Context->buffer = next;
++ }
++
++#if gcdSECURE_USER
++ /* Free the hint array. */
++ if (Context->hint != gcvNULL)
++ {
++ gcmkONERROR(gcmkOS_SAFE_FREE(Context->os, Context->hint));
++ }
++#endif
++ /* Free record array copy. */
++#if REMOVE_DUPLICATED_COPY_FROM_USER
++ if (Context->recordArrayMap != gcvNULL)
++ {
++ gcsRECORD_ARRAY_MAP_PTR map = Context->recordArrayMap;
++
++ do
++ {
++ /* Free record array. */
++ gcmkONERROR(gcmkOS_SAFE_FREE(Context->os, map->kData));
++ map = map->next;
++ }
++ while (map != Context->recordArrayMap);
++
++ gcmkONERROR(gcmkOS_SAFE_FREE(Context->os, Context->recordArrayMap));
++ }
++#else
++ if (Context->recordArray != gcvNULL)
++ {
++ gcmkONERROR(gcmkOS_SAFE_FREE(Context->os, Context->recordArray));
++ }
++#endif
++
++ /* Free the state mapping. */
++ if (Context->map != gcvNULL)
++ {
++ gcmkONERROR(gcmkOS_SAFE_FREE(Context->os, Context->map));
++ }
++
++ /* Mark the gckCONTEXT object as unknown. */
++ Context->object.type = gcvOBJ_UNKNOWN;
++
++ /* Free the gckCONTEXT object. */
++ gcmkONERROR(gcmkOS_SAFE_FREE(Context->os, Context));
++ }
++
++OnError:
++ return status;
++}
++
++
++/******************************************************************************\
++**************************** Context Management API ****************************
++\******************************************************************************/
++
++/******************************************************************************\
++**
++** gckCONTEXT_Construct
++**
++** Construct a new gckCONTEXT object.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to gckOS object.
++**
++** gctUINT32 ProcessID
++** Current process ID.
++**
++** gckHARDWARE Hardware
++** Pointer to gckHARDWARE object.
++**
++** OUTPUT:
++**
++** gckCONTEXT * Context
++** Pointer to a variable thet will receive the gckCONTEXT object
++** pointer.
++*/
++#if (gcdENABLE_3D || gcdENABLE_2D)
++gceSTATUS
++gckCONTEXT_Construct(
++ IN gckOS Os,
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 ProcessID,
++ OUT gckCONTEXT * Context
++ )
++{
++ gceSTATUS status;
++ gckCONTEXT context = gcvNULL;
++ gctUINT32 allocationSize;
++ gctUINT i;
++ gctPOINTER pointer = gcvNULL;
++ gctUINT32 address;
++
++ gcmkHEADER_ARG("Os=0x%08X Hardware=0x%08X", Os, Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Context != gcvNULL);
++
++
++ /**************************************************************************/
++ /* Allocate and initialize basic fields of gckCONTEXT. ********************/
++
++ /* The context object size. */
++ allocationSize = gcmSIZEOF(struct _gckCONTEXT);
++
++ /* Allocate the object. */
++ gcmkONERROR(gckOS_Allocate(
++ Os, allocationSize, &pointer
++ ));
++
++ context = pointer;
++
++ /* Reset the entire object. */
++ gcmkONERROR(gckOS_ZeroMemory(context, allocationSize));
++
++ /* Initialize the gckCONTEXT object. */
++ context->object.type = gcvOBJ_CONTEXT;
++ context->os = Os;
++ context->hardware = Hardware;
++
++
++#if !gcdENABLE_3D
++ context->entryPipe = gcvPIPE_2D;
++ context->exitPipe = gcvPIPE_2D;
++#elif gcdCMD_NO_2D_CONTEXT
++ context->entryPipe = gcvPIPE_3D;
++ context->exitPipe = gcvPIPE_3D;
++#else
++ context->entryPipe
++ = (((((gctUINT32) (context->hardware->identity.chipFeatures)) >> (0 ? 9:9)) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1)))))) )
++ ? gcvPIPE_2D
++ : gcvPIPE_3D;
++ context->exitPipe = gcvPIPE_3D;
++#endif
++
++ /* Get the command buffer requirements. */
++ gcmkONERROR(gckHARDWARE_QueryCommandBuffer(
++ Hardware,
++ &context->alignment,
++ &context->reservedHead,
++ &context->reservedTail
++ ));
++
++ /* Mark the context as dirty to force loading of the entire state table
++ the first time. */
++ context->dirty = gcvTRUE;
++
++
++ /**************************************************************************/
++ /* Get the size of the context buffer. ************************************/
++
++ gcmkONERROR(_InitializeContextBuffer(context));
++
++
++ /**************************************************************************/
++ /* Compute the size of the record array. **********************************/
++
++ context->recordArraySize
++ = gcmSIZEOF(gcsSTATE_DELTA_RECORD) * (gctUINT)context->stateCount;
++
++
++ if (context->stateCount > 0)
++ {
++ /**************************************************************************/
++ /* Allocate and reset the state mapping table. ****************************/
++
++ /* Allocate the state mapping table. */
++ gcmkONERROR(gckOS_Allocate(
++ Os,
++ gcmSIZEOF(gcsSTATE_MAP) * context->stateCount,
++ &pointer
++ ));
++
++ context->map = pointer;
++
++ /* Zero the state mapping table. */
++ gcmkONERROR(gckOS_ZeroMemory(
++ context->map, gcmSIZEOF(gcsSTATE_MAP) * context->stateCount
++ ));
++
++
++ /**************************************************************************/
++ /* Allocate the hint array. ***********************************************/
++
++#if gcdSECURE_USER
++ /* Allocate hints. */
++ gcmkONERROR(gckOS_Allocate(
++ Os,
++ gcmSIZEOF(gctBOOL) * context->stateCount,
++ &pointer
++ ));
++
++ context->hint = pointer;
++#endif
++ }
++
++ /**************************************************************************/
++ /* Allocate the context and state delta buffers. **************************/
++
++ for (i = 0; i < gcdCONTEXT_BUFFER_COUNT; i += 1)
++ {
++ /* Allocate a context buffer. */
++ gcsCONTEXT_PTR buffer;
++
++ gctSIZE_T totalSize = context->totalSize;
++
++ /* Allocate the context buffer structure. */
++ gcmkONERROR(gckOS_Allocate(
++ Os,
++ gcmSIZEOF(gcsCONTEXT),
++ &pointer
++ ));
++
++ buffer = pointer;
++
++ /* Reset the context buffer structure. */
++ gcmkVERIFY_OK(gckOS_ZeroMemory(
++ buffer, gcmSIZEOF(gcsCONTEXT)
++ ));
++
++ /* Append to the list. */
++ if (context->buffer == gcvNULL)
++ {
++ buffer->next = buffer;
++ context->buffer = buffer;
++ }
++ else
++ {
++ buffer->next = context->buffer->next;
++ context->buffer->next = buffer;
++ }
++
++ /* Set the number of delta in the order of creation. */
++#if gcmIS_DEBUG(gcdDEBUG_CODE)
++ buffer->num = i;
++#endif
++
++ /* Create the busy signal. */
++ gcmkONERROR(gckOS_CreateSignal(
++ Os, gcvFALSE, &buffer->signal
++ ));
++
++ /* Set the signal, buffer is currently not busy. */
++ gcmkONERROR(gckOS_Signal(
++ Os, buffer->signal, gcvTRUE
++ ));
++
++ /* Create a new physical context buffer. */
++ if (context->hardware->kernel->virtualCommandBuffer)
++ {
++ gcmkONERROR(gckKERNEL_AllocateVirtualCommandBuffer(
++ context->hardware->kernel,
++ gcvFALSE,
++ &totalSize,
++ &buffer->physical,
++ &pointer
++ ));
++
++ gcmkONERROR(gckKERNEL_GetGPUAddress(
++ context->hardware->kernel,
++ pointer,
++ gcvFALSE,
++ &address
++ ));
++ }
++ else
++ {
++ gcmkONERROR(gckOS_AllocateContiguous(
++ Os,
++ gcvFALSE,
++ &totalSize,
++ &buffer->physical,
++ &pointer
++ ));
++
++ gcmkONERROR(gckHARDWARE_ConvertLogical(
++ context->hardware,
++ pointer,
++ gcvFALSE,
++ &address
++ ));
++ }
++
++ buffer->logical = pointer;
++ buffer->address = address;
++
++ /* Set gckEVENT object pointer. */
++ buffer->eventObj = Hardware->kernel->eventObj;
++
++ /* Set the pointers to the LINK commands. */
++ if (context->linkIndex2D != 0)
++ {
++ buffer->link2D = &buffer->logical[context->linkIndex2D];
++ }
++
++ if (context->linkIndex3D != 0)
++ {
++ buffer->link3D = &buffer->logical[context->linkIndex3D];
++ }
++
++ if (context->linkIndexXD != 0)
++ {
++ gctPOINTER xdLink;
++ gctUINT32 xdEntryAddress;
++ gctUINT32 xdEntrySize;
++ gctUINT32 linkBytes;
++
++ /* Determine LINK parameters. */
++ xdLink
++ = &buffer->logical[context->linkIndexXD];
++
++ xdEntryAddress
++ = buffer->address
++ + context->entryOffsetXDFrom3D;
++
++ xdEntrySize
++ = context->bufferSize
++ - context->entryOffsetXDFrom3D;
++
++ /* Query LINK size. */
++ gcmkONERROR(gckHARDWARE_Link(
++ Hardware, gcvNULL, 0, 0, &linkBytes
++ ));
++
++ /* Generate a LINK. */
++ gcmkONERROR(gckHARDWARE_Link(
++ Hardware,
++ xdLink,
++ xdEntryAddress,
++ xdEntrySize,
++ &linkBytes
++ ));
++ }
++ }
++
++
++ /**************************************************************************/
++ /* Initialize the context buffers. ****************************************/
++
++ /* Initialize the current context buffer. */
++ gcmkONERROR(_InitializeContextBuffer(context));
++
++ /* Make all created contexts equal. */
++ {
++ gcsCONTEXT_PTR currContext, tempContext;
++
++ /* Set the current context buffer. */
++ currContext = context->buffer;
++
++ /* Get the next context buffer. */
++ tempContext = currContext->next;
++
++ /* Loop through all buffers. */
++ while (tempContext != currContext)
++ {
++ if (tempContext == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_NOT_FOUND);
++ }
++
++ /* Copy the current context. */
++ gckOS_MemCopy(
++ tempContext->logical,
++ currContext->logical,
++ context->totalSize
++ );
++
++ /* Get the next context buffer. */
++ tempContext = tempContext->next;
++ }
++ }
++
++ /* Return pointer to the gckCONTEXT object. */
++ *Context = context;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Context=0x%08X", *Context);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Roll back on error. */
++ gcmkVERIFY_OK(_DestroyContext(context));
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++#endif
++
++/******************************************************************************\
++**
++** gckCONTEXT_Destroy
++**
++** Destroy a gckCONTEXT object.
++**
++** INPUT:
++**
++** gckCONTEXT Context
++** Pointer to an gckCONTEXT object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckCONTEXT_Destroy(
++ IN gckCONTEXT Context
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Context=0x%08X", Context);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Context, gcvOBJ_CONTEXT);
++
++ /* Destroy the context and all related objects. */
++ status = _DestroyContext(Context);
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return status;
++}
++
++/******************************************************************************\
++**
++** gckCONTEXT_Update
++**
++** Merge all pending state delta buffers into the current context buffer.
++**
++** INPUT:
++**
++** gckCONTEXT Context
++** Pointer to an gckCONTEXT object.
++**
++** gctUINT32 ProcessID
++** Current process ID.
++**
++** gcsSTATE_DELTA_PTR StateDelta
++** Pointer to the state delta.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckCONTEXT_Update(
++ IN gckCONTEXT Context,
++ IN gctUINT32 ProcessID,
++ IN gcsSTATE_DELTA_PTR StateDelta
++ )
++{
++#if gcdENABLE_3D
++ gceSTATUS status = gcvSTATUS_OK;
++ gcsSTATE_DELTA _stateDelta;
++ gckKERNEL kernel;
++ gcsCONTEXT_PTR buffer;
++ gcsSTATE_MAP_PTR map;
++ gctBOOL needCopy = gcvFALSE;
++ gcsSTATE_DELTA_PTR nDelta;
++ gcsSTATE_DELTA_PTR uDelta = gcvNULL;
++ gcsSTATE_DELTA_PTR kDelta = gcvNULL;
++ gcsSTATE_DELTA_RECORD_PTR record;
++ gcsSTATE_DELTA_RECORD_PTR recordArray = gcvNULL;
++#if REMOVE_DUPLICATED_COPY_FROM_USER
++ gcsRECORD_ARRAY_MAP_PTR recordArrayMap = gcvNULL;
++#endif
++ gctUINT elementCount;
++ gctUINT address;
++ gctUINT32 mask;
++ gctUINT32 data;
++ gctUINT index;
++ gctUINT i, j;
++
++#if gcdSECURE_USER
++ gcskSECURE_CACHE_PTR cache;
++#endif
++
++ gcmkHEADER_ARG(
++ "Context=0x%08X ProcessID=%d StateDelta=0x%08X",
++ Context, ProcessID, StateDelta
++ );
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Context, gcvOBJ_CONTEXT);
++
++ /* Get a shortcut to the kernel object. */
++ kernel = Context->hardware->kernel;
++
++ /* Check wehther we need to copy the structures or not. */
++ gcmkONERROR(gckOS_QueryNeedCopy(Context->os, ProcessID, &needCopy));
++
++ /* Allocate the copy buffer for the user record array. */
++#if REMOVE_DUPLICATED_COPY_FROM_USER
++ if (needCopy && (Context->recordArrayMap == gcvNULL))
++ {
++ /* Allocate enough maps. */
++ gcmkONERROR(gckOS_Allocate(
++ Context->os,
++ gcmSIZEOF(gcsRECORD_ARRAY_MAP_PTR) * gcdCONTEXT_BUFFER_COUNT,
++ (gctPOINTER *) &Context->recordArrayMap
++ ));
++
++ for (i = 0; i < gcdCONTEXT_BUFFER_COUNT; i++)
++ {
++ /* Next mapping id. */
++ gctUINT n = (i + 1) % gcdCONTEXT_BUFFER_COUNT;
++
++ recordArrayMap = &Context->recordArrayMap[i];
++
++ /* Allocate the buffer. */
++ gcmkONERROR(gckOS_Allocate(
++ Context->os,
++ Context->recordArraySize,
++ (gctPOINTER *) &recordArrayMap->kData
++ ));
++
++ /* Initialize fields. */
++ recordArrayMap->key = 0;
++ recordArrayMap->next = &Context->recordArrayMap[n];
++ }
++ }
++#else
++ if (needCopy && (Context->recordArray == gcvNULL))
++ {
++ /* Allocate the buffer. */
++ gcmkONERROR(gckOS_Allocate(
++ Context->os,
++ Context->recordArraySize,
++ (gctPOINTER *) &Context->recordArray
++ ));
++ }
++#endif
++
++ /* Get the current context buffer. */
++ buffer = Context->buffer;
++
++ /* Wait until the context buffer becomes available; this will
++ also reset the signal and mark the buffer as busy. */
++ gcmkONERROR(gckOS_WaitSignal(
++ Context->os, buffer->signal, gcvINFINITE
++ ));
++
++#if gcdSECURE_USER
++ /* Get the cache form the database. */
++ gcmkONERROR(gckKERNEL_GetProcessDBCache(kernel, ProcessID, &cache));
++#endif
++
++#if gcmIS_DEBUG(gcdDEBUG_CODE) && 1 && gcdENABLE_3D
++ /* Update current context token. */
++ buffer->logical[Context->map[0x0E14].index]
++ = (gctUINT32)gcmPTR2INT32(Context);
++#endif
++
++ /* Are there any pending deltas? */
++ if (buffer->deltaCount != 0)
++ {
++ /* Get the state map. */
++ map = Context->map;
++
++ /* Get the first delta item. */
++ uDelta = buffer->delta;
++
++ /* Reset the vertex stream count. */
++ elementCount = 0;
++
++ /* Merge all pending deltas. */
++ for (i = 0; i < buffer->deltaCount; i += 1)
++ {
++ /* Get access to the state delta. */
++ gcmkONERROR(gckKERNEL_OpenUserData(
++ kernel, needCopy,
++ &_stateDelta,
++ uDelta, gcmSIZEOF(gcsSTATE_DELTA),
++ (gctPOINTER *) &kDelta
++ ));
++
++#if REMOVE_DUPLICATED_COPY_FROM_USER
++ if (needCopy)
++ {
++ recordArray = gcvNULL;
++ recordArrayMap = Context->recordArrayMap;
++
++ do
++ {
++ /* Check if recordArray is alreay opened. */
++ if (recordArrayMap->key == kDelta->recordArray)
++ {
++ /* Found. */
++ recordArray = recordArrayMap->kData;
++ break;
++ }
++
++ recordArrayMap = recordArrayMap->next;
++ }
++ while (recordArrayMap != Context->recordArrayMap);
++
++ if (recordArray == gcvNULL)
++ {
++ while (recordArrayMap->key != 0)
++ {
++ /* Found an empty slot. */
++ recordArrayMap = recordArrayMap->next;
++ }
++
++ /* Get access to the state records. */
++ gcmkONERROR(gckOS_CopyFromUserData(
++ kernel->os,
++ recordArrayMap->kData,
++ gcmUINT64_TO_PTR(kDelta->recordArray),
++ Context->recordArraySize
++ ));
++
++ /* Save user pointer as key. */
++ recordArrayMap->key = kDelta->recordArray;
++ recordArray = recordArrayMap->kData;
++ }
++ }
++ else
++ {
++ /* Get access to the state records. */
++ gcmkONERROR(gckOS_MapUserPointer(
++ kernel->os,
++ gcmUINT64_TO_PTR(kDelta->recordArray),
++ Context->recordArraySize,
++ (gctPOINTER *) &recordArray
++ ));
++ }
++#else
++ /* Get access to the state records. */
++ gcmkONERROR(gckKERNEL_OpenUserData(
++ kernel, needCopy,
++ Context->recordArray,
++ gcmUINT64_TO_PTR(kDelta->recordArray), Context->recordArraySize,
++ (gctPOINTER *) &recordArray
++ ));
++#endif
++
++ /* Merge all pending states. */
++ for (j = 0; j < kDelta->recordCount; j += 1)
++ {
++ if (j >= Context->stateCount)
++ {
++ break;
++ }
++
++ /* Get the current state record. */
++ record = &recordArray[j];
++
++ /* Get the state address. */
++ address = record->address;
++
++ /* Make sure the state is a part of the mapping table. */
++ if (address >= Context->stateCount)
++ {
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): State 0x%04X is not mapped.\n",
++ __FUNCTION__, __LINE__,
++ address
++ );
++
++ continue;
++ }
++
++ /* Get the state index. */
++ index = map[address].index;
++
++ /* Skip the state if not mapped. */
++ if (index == 0)
++ {
++ continue;
++ }
++
++ /* Get the data mask. */
++ mask = record->mask;
++
++ /* Masked states that are being completly reset or regular states. */
++ if ((mask == 0) || (mask == ~0U))
++ {
++ /* Get the new data value. */
++ data = record->data;
++
++ /* Process special states. */
++ if (address == 0x0595)
++ {
++ /* Force auto-disable to be disabled. */
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5)));
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4)));
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 13:13) - (0 ? 13:13) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 13:13) - (0 ? 13:13) + 1))))))) << (0 ? 13:13))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 13:13) - (0 ? 13:13) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 13:13) - (0 ? 13:13) + 1))))))) << (0 ? 13:13)));
++ }
++
++#if gcdSECURE_USER
++ /* Do we need to convert the logical address? */
++ if (Context->hint[address])
++ {
++ /* Map handle into physical address. */
++ gcmkONERROR(gckKERNEL_MapLogicalToPhysical(
++ kernel, cache, (gctPOINTER) &data
++ ));
++ }
++#endif
++
++ /* Set new data. */
++ buffer->logical[index] = data;
++ }
++
++ /* Masked states that are being set partially. */
++ else
++ {
++ buffer->logical[index]
++ = (~mask & buffer->logical[index])
++ | (mask & record->data);
++ }
++ }
++
++ /* Get the element count. */
++ if (kDelta->elementCount != 0)
++ {
++ elementCount = kDelta->elementCount;
++ }
++
++ /* Dereference delta. */
++ kDelta->refCount -= 1;
++ gcmkASSERT(kDelta->refCount >= 0);
++
++ /* Get the next state delta. */
++ nDelta = gcmUINT64_TO_PTR(kDelta->next);
++
++#if REMOVE_DUPLICATED_COPY_FROM_USER
++ if (needCopy)
++ {
++ if (kDelta->refCount == 0)
++ {
++ /* No other reference, reset the mapping. */
++ recordArrayMap->key = 0;
++ }
++ }
++ else
++ {
++ /* Close access to the state records. */
++ gcmkONERROR(gckOS_UnmapUserPointer(
++ kernel->os,
++ gcmUINT64_TO_PTR(kDelta->recordArray),
++ Context->recordArraySize,
++ (gctPOINTER *) recordArray
++ ));
++
++ recordArray = gcvNULL;
++ }
++#else
++ /* Get access to the state records. */
++ gcmkONERROR(gckKERNEL_CloseUserData(
++ kernel, needCopy,
++ gcvFALSE,
++ gcmUINT64_TO_PTR(kDelta->recordArray), Context->recordArraySize,
++ (gctPOINTER *) &recordArray
++ ));
++#endif
++
++ /* Close access to the current state delta. */
++ gcmkONERROR(gckKERNEL_CloseUserData(
++ kernel, needCopy,
++ gcvTRUE,
++ uDelta, gcmSIZEOF(gcsSTATE_DELTA),
++ (gctPOINTER *) &kDelta
++ ));
++
++ /* Update the user delta pointer. */
++ uDelta = nDelta;
++ }
++
++ /* Hardware disables all input streams when the stream 0 is programmed,
++ it then reenables those streams that were explicitely programmed by
++ the software. Because of this we cannot program the entire array of
++ values, otherwise we'll get all streams reenabled, but rather program
++ only those that are actully needed by the software. */
++ if (elementCount != 0)
++ {
++ gctUINT base;
++ gctUINT nopCount;
++ gctUINT32_PTR nop;
++ gctUINT fe2vsCount = 12;
++
++ if ((((((gctUINT32) (Context->hardware->identity.chipMinorFeatures1)) >> (0 ? 23:23)) & ((gctUINT32) ((((1 ? 23:23) - (0 ? 23:23) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:23) - (0 ? 23:23) + 1)))))) ))
++ {
++ fe2vsCount = 16;
++ }
++
++ /* Determine the base index of the vertex stream array. */
++ base = map[0x0180].index;
++
++ /* Set the proper state count. */
++ buffer->logical[base - 1]
++ = ((((gctUINT32) (buffer->logical[base - 1])) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (elementCount ) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ /* Determine the number of NOP commands. */
++ nopCount
++ = (fe2vsCount / 2)
++ - (elementCount / 2);
++
++ /* Determine the location of the first NOP. */
++ nop = &buffer->logical[base + (elementCount | 1)];
++
++ /* Fill the unused space with NOPs. */
++ for (i = 0; i < nopCount; i += 1)
++ {
++ if (nop >= buffer->logical + Context->totalSize)
++ {
++ break;
++ }
++
++ /* Generate a NOP command. */
++ *nop = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x03 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++
++ /* Advance. */
++ nop += 2;
++ }
++ }
++
++ /* Reset pending deltas. */
++ buffer->deltaCount = 0;
++ buffer->delta = gcvNULL;
++ }
++
++ /* Set state delta user pointer. */
++ uDelta = StateDelta;
++
++ /* Get access to the state delta. */
++ gcmkONERROR(gckKERNEL_OpenUserData(
++ kernel, needCopy,
++ &_stateDelta,
++ uDelta, gcmSIZEOF(gcsSTATE_DELTA),
++ (gctPOINTER *) &kDelta
++ ));
++
++ /* State delta cannot be attached to anything yet. */
++ if (kDelta->refCount != 0)
++ {
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): kDelta->refCount = %d (has to be 0).\n",
++ __FUNCTION__, __LINE__,
++ kDelta->refCount
++ );
++ }
++
++ /* Attach to all contexts. */
++ buffer = Context->buffer;
++
++ do
++ {
++ /* Attach to the context if nothing is attached yet. If a delta
++ is allready attached, all we need to do is to increment
++ the number of deltas in the context. */
++ if (buffer->delta == gcvNULL)
++ {
++ buffer->delta = uDelta;
++ }
++
++ /* Update reference count. */
++ kDelta->refCount += 1;
++
++ /* Update counters. */
++ buffer->deltaCount += 1;
++
++ /* Get the next context buffer. */
++ buffer = buffer->next;
++
++ if (buffer == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_NOT_FOUND);
++ }
++ }
++ while (Context->buffer != buffer);
++
++ /* Close access to the current state delta. */
++ gcmkONERROR(gckKERNEL_CloseUserData(
++ kernel, needCopy,
++ gcvTRUE,
++ uDelta, gcmSIZEOF(gcsSTATE_DELTA),
++ (gctPOINTER *) &kDelta
++ ));
++
++ /* Schedule an event to mark the context buffer as available. */
++ gcmkONERROR(gckEVENT_Signal(
++ buffer->eventObj, buffer->signal, gcvKERNEL_PIXEL
++ ));
++
++ /* Advance to the next context buffer. */
++ Context->buffer = buffer->next;
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Get access to the state records. */
++ if (kDelta != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckKERNEL_CloseUserData(
++ kernel, needCopy,
++ gcvFALSE,
++ gcmUINT64_TO_PTR(kDelta->recordArray), Context->recordArraySize,
++ (gctPOINTER *) &recordArray
++ ));
++ }
++
++ /* Close access to the current state delta. */
++ gcmkVERIFY_OK(gckKERNEL_CloseUserData(
++ kernel, needCopy,
++ gcvTRUE,
++ uDelta, gcmSIZEOF(gcsSTATE_DELTA),
++ (gctPOINTER *) &kDelta
++ ));
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++#else
++ return gcvSTATUS_OK;
++#endif
++}
++
++gceSTATUS
++gckCONTEXT_MapBuffer(
++ IN gckCONTEXT Context,
++ OUT gctUINT32 *Physicals,
++ OUT gctUINT64 *Logicals,
++ OUT gctUINT32 *Bytes
++ )
++{
++ gceSTATUS status;
++ int i = 0;
++ gctSIZE_T pageCount;
++ gckVIRTUAL_COMMAND_BUFFER_PTR commandBuffer;
++ gckKERNEL kernel = Context->hardware->kernel;
++ gctPOINTER logical;
++ gctPHYS_ADDR physical;
++
++ gcsCONTEXT_PTR buffer;
++
++ gcmkHEADER();
++
++ gcmkVERIFY_OBJECT(Context, gcvOBJ_CONTEXT);
++
++ buffer = Context->buffer;
++
++ for (i = 0; i < gcdCONTEXT_BUFFER_COUNT; i++)
++ {
++ if (kernel->virtualCommandBuffer)
++ {
++ commandBuffer = (gckVIRTUAL_COMMAND_BUFFER_PTR)buffer->physical;
++ physical = commandBuffer->physical;
++
++ gcmkONERROR(gckOS_CreateUserVirtualMapping(
++ kernel->os,
++ physical,
++ Context->totalSize,
++ &logical,
++ &pageCount));
++ }
++ else
++ {
++ physical = buffer->physical;
++
++ gcmkONERROR(gckOS_MapMemory(
++ kernel->os,
++ physical,
++ Context->totalSize,
++ &logical));
++ }
++
++ Physicals[i] = gcmPTR_TO_NAME(physical);
++
++ Logicals[i] = gcmPTR_TO_UINT64(logical);
++
++ buffer = buffer->next;
++ }
++
++ *Bytes = (gctUINT)Context->totalSize;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/arch/gc_hal_kernel_context.h linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/arch/gc_hal_kernel_context.h
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/arch/gc_hal_kernel_context.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/arch/gc_hal_kernel_context.h 2015-07-27 23:13:06.186908111 +0200
+@@ -0,0 +1,183 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_kernel_context_h_
++#define __gc_hal_kernel_context_h_
++
++#include "gc_hal_kernel_buffer.h"
++
++/* Exprimental optimization. */
++#define REMOVE_DUPLICATED_COPY_FROM_USER 1
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/* Maps state locations within the context buffer. */
++typedef struct _gcsSTATE_MAP * gcsSTATE_MAP_PTR;
++typedef struct _gcsSTATE_MAP
++{
++ /* Index of the state in the context buffer. */
++ gctUINT index;
++
++ /* State mask. */
++ gctUINT32 mask;
++}
++gcsSTATE_MAP;
++
++/* Context buffer. */
++typedef struct _gcsCONTEXT * gcsCONTEXT_PTR;
++typedef struct _gcsCONTEXT
++{
++ /* For debugging: the number of context buffer in the order of creation. */
++#if gcmIS_DEBUG(gcdDEBUG_CODE)
++ gctUINT num;
++#endif
++
++ /* Pointer to gckEVENT object. */
++ gckEVENT eventObj;
++
++ /* Context busy signal. */
++ gctSIGNAL signal;
++
++ /* Physical address of the context buffer. */
++ gctPHYS_ADDR physical;
++
++ /* Logical address of the context buffer. */
++ gctUINT32_PTR logical;
++
++ /* Hardware address of the context buffer. */
++ gctUINT32 address;
++
++ /* Pointer to the LINK commands. */
++ gctPOINTER link2D;
++ gctPOINTER link3D;
++
++ /* The number of pending state deltas. */
++ gctUINT deltaCount;
++
++ /* Pointer to the first delta to be applied. */
++ gcsSTATE_DELTA_PTR delta;
++
++ /* Next context buffer. */
++ gcsCONTEXT_PTR next;
++}
++gcsCONTEXT;
++
++typedef struct _gcsRECORD_ARRAY_MAP * gcsRECORD_ARRAY_MAP_PTR;
++struct _gcsRECORD_ARRAY_MAP
++{
++ /* User pointer key. */
++ gctUINT64 key;
++
++ /* Kernel memory buffer. */
++ gcsSTATE_DELTA_RECORD_PTR kData;
++
++ /* Next map. */
++ gcsRECORD_ARRAY_MAP_PTR next;
++
++};
++
++/* gckCONTEXT structure that hold the current context. */
++struct _gckCONTEXT
++{
++ /* Object. */
++ gcsOBJECT object;
++
++ /* Pointer to gckOS object. */
++ gckOS os;
++
++ /* Pointer to gckHARDWARE object. */
++ gckHARDWARE hardware;
++
++ /* Command buffer alignment. */
++ gctUINT32 alignment;
++ gctUINT32 reservedHead;
++ gctUINT32 reservedTail;
++
++ /* Context buffer metrics. */
++ gctSIZE_T stateCount;
++ gctUINT32 totalSize;
++ gctUINT32 bufferSize;
++ gctUINT32 linkIndex2D;
++ gctUINT32 linkIndex3D;
++ gctUINT32 linkIndexXD;
++ gctUINT32 entryOffset3D;
++ gctUINT32 entryOffsetXDFrom2D;
++ gctUINT32 entryOffsetXDFrom3D;
++
++ /* Dirty flags. */
++ gctBOOL dirty;
++ gctBOOL dirty2D;
++ gctBOOL dirty3D;
++ gcsCONTEXT_PTR dirtyBuffer;
++
++ /* State mapping. */
++ gcsSTATE_MAP_PTR map;
++
++ /* List of context buffers. */
++ gcsCONTEXT_PTR buffer;
++
++ /* A copy of the user record array. */
++ gctUINT recordArraySize;
++#if REMOVE_DUPLICATED_COPY_FROM_USER
++ gcsRECORD_ARRAY_MAP_PTR recordArrayMap;
++#else
++ gcsSTATE_DELTA_RECORD_PTR recordArray;
++#endif
++
++ /* Requested pipe select for context. */
++ gcePIPE_SELECT entryPipe;
++ gcePIPE_SELECT exitPipe;
++
++ /* Variables used for building state buffer. */
++ gctUINT32 lastAddress;
++ gctSIZE_T lastSize;
++ gctUINT32 lastIndex;
++ gctBOOL lastFixed;
++
++ gctUINT32 pipeSelectBytes;
++
++ /* Hint array. */
++#if gcdSECURE_USER
++ gctBOOL_PTR hint;
++#endif
++
++#if VIVANTE_PROFILER_CONTEXT
++ gcsPROFILER_COUNTERS latestProfiler;
++ gcsPROFILER_COUNTERS histroyProfiler;
++ gctUINT32 prevVSInstCount;
++ gctUINT32 prevVSBranchInstCount;
++ gctUINT32 prevVSTexInstCount;
++ gctUINT32 prevVSVertexCount;
++ gctUINT32 prevPSInstCount;
++ gctUINT32 prevPSBranchInstCount;
++ gctUINT32 prevPSTexInstCount;
++ gctUINT32 prevPSPixelCount;
++#endif
++};
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __gc_hal_kernel_context_h_ */
++
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/arch/gc_hal_kernel_hardware.c linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/arch/gc_hal_kernel_hardware.c
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/arch/gc_hal_kernel_hardware.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/arch/gc_hal_kernel_hardware.c 2015-07-27 23:13:06.186908111 +0200
+@@ -0,0 +1,8036 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal.h"
++#include "gc_hal_kernel.h"
++#if VIVANTE_PROFILER_CONTEXT
++#include "gc_hal_kernel_context.h"
++#endif
++
++#define gcdDISABLE_FE_L2 1
++
++#define _GC_OBJ_ZONE gcvZONE_HARDWARE
++
++#define gcmSEMAPHORESTALL(buffer) \
++ do \
++ { \
++ /* Arm the PE-FE Semaphore. */ \
++ *buffer++ \
++ = gcmSETFIELDVALUE(0, AQ_COMMAND_LOAD_STATE_COMMAND, OPCODE, LOAD_STATE) \
++ | gcmSETFIELD (0, AQ_COMMAND_LOAD_STATE_COMMAND, COUNT, 1) \
++ | gcmSETFIELD (0, AQ_COMMAND_LOAD_STATE_COMMAND, ADDRESS, 0x0E02); \
++ \
++ *buffer++ \
++ = gcmSETFIELDVALUE(0, AQ_SEMAPHORE, SOURCE, FRONT_END) \
++ | gcmSETFIELDVALUE(0, AQ_SEMAPHORE, DESTINATION, PIXEL_ENGINE);\
++ \
++ /* STALL FE until PE is done flushing. */ \
++ *buffer++ \
++ = gcmSETFIELDVALUE(0, STALL_COMMAND, OPCODE, STALL); \
++ \
++ *buffer++ \
++ = gcmSETFIELDVALUE(0, STALL_STALL, SOURCE, FRONT_END) \
++ | gcmSETFIELDVALUE(0, STALL_STALL, DESTINATION, PIXEL_ENGINE); \
++ } while(0)
++
++typedef struct _gcsiDEBUG_REGISTERS * gcsiDEBUG_REGISTERS_PTR;
++typedef struct _gcsiDEBUG_REGISTERS
++{
++ gctSTRING module;
++ gctUINT index;
++ gctUINT shift;
++ gctUINT data;
++ gctUINT count;
++ gctUINT32 signature;
++}
++gcsiDEBUG_REGISTERS;
++
++/******************************************************************************\
++********************************* Support Code *********************************
++\******************************************************************************/
++static gctBOOL
++_IsHardwareMatch(
++ IN gckHARDWARE Hardware,
++ IN gctINT32 ChipModel,
++ IN gctUINT32 ChipRevision
++ )
++{
++ return ((Hardware->identity.chipModel == ChipModel) &&
++ (Hardware->identity.chipRevision == ChipRevision));
++}
++
++static gceSTATUS
++_ResetGPU(
++ IN gckHARDWARE Hardware,
++ IN gckOS Os,
++ IN gceCORE Core
++ );
++
++static gceSTATUS
++_IdentifyHardware(
++ IN gckOS Os,
++ IN gceCORE Core,
++ OUT gcsHAL_QUERY_CHIP_IDENTITY_PTR Identity
++ )
++{
++ gceSTATUS status;
++
++ gctUINT32 chipIdentity;
++
++ gctUINT32 streamCount = 0;
++ gctUINT32 registerMax = 0;
++ gctUINT32 threadCount = 0;
++ gctUINT32 shaderCoreCount = 0;
++ gctUINT32 vertexCacheSize = 0;
++ gctUINT32 vertexOutputBufferSize = 0;
++ gctUINT32 pixelPipes = 0;
++ gctUINT32 instructionCount = 0;
++ gctUINT32 numConstants = 0;
++ gctUINT32 bufferSize = 0;
++ gctUINT32 varyingsCount = 0;
++#if gcdMULTI_GPU
++ gctUINT32 gpuCoreCount = 0;
++#endif
++
++ gcmkHEADER_ARG("Os=0x%x", Os);
++
++ /***************************************************************************
++ ** Get chip ID and revision.
++ */
++
++ /* Read chip identity register. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x00018,
++ &chipIdentity));
++
++ /* Special case for older graphic cores. */
++ if (((((gctUINT32) (chipIdentity)) >> (0 ? 31:24) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1)))))) == (0x01 & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))))
++ {
++ Identity->chipModel = gcv500;
++ Identity->chipRevision = (((((gctUINT32) (chipIdentity)) >> (0 ? 15:12)) & ((gctUINT32) ((((1 ? 15:12) - (0 ? 15:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:12) - (0 ? 15:12) + 1)))))) );
++ }
++
++ else
++ {
++ /* Read chip identity register. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x00020,
++ (gctUINT32_PTR) &Identity->chipModel));
++
++ if (((Identity->chipModel & 0xFF00) == 0x0400)
++ && (Identity->chipModel != 0x0420)
++ && (Identity->chipModel != 0x0428))
++ {
++ Identity->chipModel = (gceCHIPMODEL) (Identity->chipModel & 0x0400);
++ }
++
++ /* Read CHIP_REV register. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x00024,
++ &Identity->chipRevision));
++
++ if ((Identity->chipModel == gcv300)
++ && (Identity->chipRevision == 0x2201)
++ )
++ {
++ gctUINT32 chipDate;
++ gctUINT32 chipTime;
++
++ /* Read date and time registers. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x00028,
++ &chipDate));
++
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x0002C,
++ &chipTime));
++
++ if ((chipDate == 0x20080814) && (chipTime == 0x12051100))
++ {
++ /* This IP has an ECO; put the correct revision in it. */
++ Identity->chipRevision = 0x1051;
++ }
++ }
++
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x000A8,
++ &Identity->productID));
++ }
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Identity: chipModel=%X",
++ Identity->chipModel);
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Identity: chipRevision=%X",
++ Identity->chipRevision);
++
++
++ /***************************************************************************
++ ** Get chip features.
++ */
++
++ /* Read chip feature register. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x0001C,
++ &Identity->chipFeatures));
++
++#if gcdENABLE_3D
++ /* Disable fast clear on GC700. */
++ if (Identity->chipModel == gcv700)
++ {
++ Identity->chipFeatures
++ = ((((gctUINT32) (Identity->chipFeatures)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)));
++ }
++#endif
++
++ if (((Identity->chipModel == gcv500) && (Identity->chipRevision < 2))
++ || ((Identity->chipModel == gcv300) && (Identity->chipRevision < 0x2000))
++ )
++ {
++ /* GC500 rev 1.x and GC300 rev < 2.0 doesn't have these registers. */
++ Identity->chipMinorFeatures = 0;
++ Identity->chipMinorFeatures1 = 0;
++ Identity->chipMinorFeatures2 = 0;
++ Identity->chipMinorFeatures3 = 0;
++ Identity->chipMinorFeatures4 = 0;
++ Identity->chipMinorFeatures5 = 0;
++ }
++ else
++ {
++ /* Read chip minor feature register #0. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x00034,
++ &Identity->chipMinorFeatures));
++
++ if (((((gctUINT32) (Identity->chipMinorFeatures)) >> (0 ? 21:21) & ((gctUINT32) ((((1 ? 21:21) - (0 ? 21:21) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 21:21) - (0 ? 21:21) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 21:21) - (0 ? 21:21) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 21:21) - (0 ? 21:21) + 1)))))))
++ )
++ {
++ /* Read chip minor featuress register #1. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x00074,
++ &Identity->chipMinorFeatures1));
++
++ /* Read chip minor featuress register #2. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x00084,
++ &Identity->chipMinorFeatures2));
++
++ /*Identity->chipMinorFeatures2 &= ~(0x1 << 3);*/
++
++ /* Read chip minor featuress register #1. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x00088,
++ &Identity->chipMinorFeatures3));
++
++
++ /* Read chip minor featuress register #4. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x00094,
++ &Identity->chipMinorFeatures4));
++
++ /* Read chip minor featuress register #5. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x000A0,
++ &Identity->chipMinorFeatures5));
++ }
++ else
++ {
++ /* Chip doesn't has minor features register #1 or 2 or 3 or 4. */
++ Identity->chipMinorFeatures1 = 0;
++ Identity->chipMinorFeatures2 = 0;
++ Identity->chipMinorFeatures3 = 0;
++ Identity->chipMinorFeatures4 = 0;
++ Identity->chipMinorFeatures5 = 0;
++ }
++ }
++
++ /* Get the Supertile layout in the hardware. */
++ if (((((gctUINT32) (Identity->chipMinorFeatures3)) >> (0 ? 26:26) & ((gctUINT32) ((((1 ? 26:26) - (0 ? 26:26) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 26:26) - (0 ? 26:26) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 26:26) - (0 ? 26:26) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 26:26) - (0 ? 26:26) + 1)))))))
++ || ((((gctUINT32) (Identity->chipMinorFeatures3)) >> (0 ? 8:8) & ((gctUINT32) ((((1 ? 8:8) - (0 ? 8:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:8) - (0 ? 8:8) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 8:8) - (0 ? 8:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:8) - (0 ? 8:8) + 1))))))))
++ {
++ Identity->superTileMode = 2;
++ }
++ else if (((((gctUINT32) (Identity->chipMinorFeatures)) >> (0 ? 27:27) & ((gctUINT32) ((((1 ? 27:27) - (0 ? 27:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:27) - (0 ? 27:27) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 27:27) - (0 ? 27:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:27) - (0 ? 27:27) + 1))))))))
++ {
++ Identity->superTileMode = 1;
++ }
++ else
++ {
++ Identity->superTileMode = 0;
++ }
++
++ /* Exception for GC1000, revision 5035 & GC800, revision 4612 */
++ if (((Identity->chipModel == gcv1000) && ((Identity->chipRevision == 0x5035)
++ || (Identity->chipRevision == 0x5036)
++ || (Identity->chipRevision == 0x5037)
++ || (Identity->chipRevision == 0x5039)
++ || (Identity->chipRevision >= 0x5040)))
++ || ((Identity->chipModel == gcv800) && (Identity->chipRevision == 0x4612))
++ || ((Identity->chipModel == gcv600) && (Identity->chipRevision >= 0x4650))
++ || ((Identity->chipModel == gcv860) && (Identity->chipRevision == 0x4647))
++ || ((Identity->chipModel == gcv400) && (Identity->chipRevision >= 0x4633)))
++ {
++ Identity->superTileMode = 1;
++ }
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Identity: chipFeatures=0x%08X",
++ Identity->chipFeatures);
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Identity: chipMinorFeatures=0x%08X",
++ Identity->chipMinorFeatures);
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Identity: chipMinorFeatures1=0x%08X",
++ Identity->chipMinorFeatures1);
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Identity: chipMinorFeatures2=0x%08X",
++ Identity->chipMinorFeatures2);
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Identity: chipMinorFeatures3=0x%08X",
++ Identity->chipMinorFeatures3);
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Identity: chipMinorFeatures4=0x%08X",
++ Identity->chipMinorFeatures4);
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Identity: chipMinorFeatures5=0x%08X",
++ Identity->chipMinorFeatures5);
++
++ /***************************************************************************
++ ** Get chip specs.
++ */
++
++ if (((((gctUINT32) (Identity->chipMinorFeatures)) >> (0 ? 21:21) & ((gctUINT32) ((((1 ? 21:21) - (0 ? 21:21) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 21:21) - (0 ? 21:21) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 21:21) - (0 ? 21:21) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 21:21) - (0 ? 21:21) + 1))))))))
++ {
++ gctUINT32 specs, specs2, specs3, specs4;
++
++ /* Read gcChipSpecs register. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x00048,
++ &specs));
++
++ /* Extract the fields. */
++ registerMax = (((((gctUINT32) (specs)) >> (0 ? 7:4)) & ((gctUINT32) ((((1 ? 7:4) - (0 ? 7:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:4) - (0 ? 7:4) + 1)))))) );
++ threadCount = (((((gctUINT32) (specs)) >> (0 ? 11:8)) & ((gctUINT32) ((((1 ? 11:8) - (0 ? 11:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:8) - (0 ? 11:8) + 1)))))) );
++ shaderCoreCount = (((((gctUINT32) (specs)) >> (0 ? 24:20)) & ((gctUINT32) ((((1 ? 24:20) - (0 ? 24:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 24:20) - (0 ? 24:20) + 1)))))) );
++ vertexCacheSize = (((((gctUINT32) (specs)) >> (0 ? 16:12)) & ((gctUINT32) ((((1 ? 16:12) - (0 ? 16:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:12) - (0 ? 16:12) + 1)))))) );
++ vertexOutputBufferSize = (((((gctUINT32) (specs)) >> (0 ? 31:28)) & ((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1)))))) );
++ pixelPipes = (((((gctUINT32) (specs)) >> (0 ? 27:25)) & ((gctUINT32) ((((1 ? 27:25) - (0 ? 27:25) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:25) - (0 ? 27:25) + 1)))))) );
++
++ /* Read gcChipSpecs2 register. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x00080,
++ &specs2));
++
++ instructionCount = (((((gctUINT32) (specs2)) >> (0 ? 15:8)) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1)))))) );
++ numConstants = (((((gctUINT32) (specs2)) >> (0 ? 31:16)) & ((gctUINT32) ((((1 ? 31:16) - (0 ? 31:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:16) - (0 ? 31:16) + 1)))))) );
++ bufferSize = (((((gctUINT32) (specs2)) >> (0 ? 7:0)) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1)))))) );
++
++ /* Read gcChipSpecs3 register. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x0008C,
++ &specs3));
++
++ varyingsCount = (((((gctUINT32) (specs3)) >> (0 ? 8:4)) & ((gctUINT32) ((((1 ? 8:4) - (0 ? 8:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:4) - (0 ? 8:4) + 1)))))) );
++#if gcdMULTI_GPU
++ gpuCoreCount = (((((gctUINT32) (specs3)) >> (0 ? 2:0)) & ((gctUINT32) ((((1 ? 2:0) - (0 ? 2:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:0) - (0 ? 2:0) + 1)))))) );
++#endif
++
++ /* Read gcChipSpecs4 register. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x0009C,
++ &specs4));
++
++
++ streamCount = (((((gctUINT32) (specs4)) >> (0 ? 16:12)) & ((gctUINT32) ((((1 ? 16:12) - (0 ? 16:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:12) - (0 ? 16:12) + 1)))))) );
++ if (streamCount == 0)
++ {
++ /* Extract stream count from older register. */
++ streamCount = (((((gctUINT32) (specs)) >> (0 ? 3:0)) & ((gctUINT32) ((((1 ? 3:0) - (0 ? 3:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:0) - (0 ? 3:0) + 1)))))) );
++ }
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Identity: chipSpecs1=0x%08X",
++ specs);
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Identity: chipSpecs2=0x%08X",
++ specs2);
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Identity: chipSpecs3=0x%08X",
++ specs3);
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Identity: chipSpecs4=0x%08X",
++ specs4);
++ }
++
++ /* Get the number of pixel pipes. */
++ Identity->pixelPipes = gcmMAX(pixelPipes, 1);
++
++ /* Get the stream count. */
++ Identity->streamCount = (streamCount != 0)
++ ? streamCount
++ : (Identity->chipModel >= gcv1000) ? 4 : 1;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Specs: streamCount=%u%s",
++ Identity->streamCount,
++ (streamCount == 0) ? " (default)" : "");
++
++ /* Get the vertex output buffer size. */
++ Identity->vertexOutputBufferSize = (vertexOutputBufferSize != 0)
++ ? 1 << vertexOutputBufferSize
++ : (Identity->chipModel == gcv400)
++ ? (Identity->chipRevision < 0x4000) ? 512
++ : (Identity->chipRevision < 0x4200) ? 256
++ : 128
++ : (Identity->chipModel == gcv530)
++ ? (Identity->chipRevision < 0x4200) ? 512
++ : 128
++ : 512;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Specs: vertexOutputBufferSize=%u%s",
++ Identity->vertexOutputBufferSize,
++ (vertexOutputBufferSize == 0) ? " (default)" : "");
++
++ /* Get the maximum number of threads. */
++ Identity->threadCount = (threadCount != 0)
++ ? 1 << threadCount
++ : (Identity->chipModel == gcv400) ? 64
++ : (Identity->chipModel == gcv500) ? 128
++ : (Identity->chipModel == gcv530) ? 128
++ : 256;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Specs: threadCount=%u%s",
++ Identity->threadCount,
++ (threadCount == 0) ? " (default)" : "");
++
++ /* Get the number of shader cores. */
++ Identity->shaderCoreCount = (shaderCoreCount != 0)
++ ? shaderCoreCount
++ : (Identity->chipModel >= gcv1000) ? 2
++ : 1;
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Specs: shaderCoreCount=%u%s",
++ Identity->shaderCoreCount,
++ (shaderCoreCount == 0) ? " (default)" : "");
++
++ /* Get the vertex cache size. */
++ Identity->vertexCacheSize = (vertexCacheSize != 0)
++ ? vertexCacheSize
++ : 8;
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Specs: vertexCacheSize=%u%s",
++ Identity->vertexCacheSize,
++ (vertexCacheSize == 0) ? " (default)" : "");
++
++ /* Get the maximum number of temporary registers. */
++ Identity->registerMax = (registerMax != 0)
++ /* Maximum of registerMax/4 registers are accessible to 1 shader */
++ ? 1 << registerMax
++ : (Identity->chipModel == gcv400) ? 32
++ : 64;
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Specs: registerMax=%u%s",
++ Identity->registerMax,
++ (registerMax == 0) ? " (default)" : "");
++
++ /* Get the instruction count. */
++ Identity->instructionCount = (instructionCount == 0) ? 256
++ : (instructionCount == 1) ? 1024
++ : (instructionCount == 2) ? 2048
++ : (instructionCount == 0xFF) ? 512
++ : 256;
++
++ if (Identity->instructionCount == 256)
++ {
++ if ((Identity->chipModel == gcv2000 && Identity->chipRevision == 0x5108)
++ || Identity->chipModel == gcv880)
++ {
++ Identity->instructionCount = 512;
++ }
++ else if (((((gctUINT32) (Identity->chipMinorFeatures3)) >> (0 ? 3:3) & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))))
++ {
++ Identity->instructionCount = 512;
++ }
++ }
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Specs: instructionCount=%u%s",
++ Identity->instructionCount,
++ (instructionCount == 0) ? " (default)" : "");
++
++ /* Get the number of constants. */
++ Identity->numConstants = (numConstants == 0) ? 168 : numConstants;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Specs: numConstants=%u%s",
++ Identity->numConstants,
++ (numConstants == 0) ? " (default)" : "");
++
++ /* Get the buffer size. */
++ Identity->bufferSize = bufferSize;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Specs: bufferSize=%u%s",
++ Identity->bufferSize,
++ (bufferSize == 0) ? " (default)" : "");
++
++
++ if (varyingsCount != 0)
++ {
++ Identity->varyingsCount = varyingsCount;
++ }
++ else if (((((gctUINT32) (Identity->chipMinorFeatures1)) >> (0 ? 23:23) & ((gctUINT32) ((((1 ? 23:23) - (0 ? 23:23) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:23) - (0 ? 23:23) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 23:23) - (0 ? 23:23) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:23) - (0 ? 23:23) + 1))))))))
++ {
++ Identity->varyingsCount = 12;
++ }
++ else
++ {
++ Identity->varyingsCount = 8;
++ }
++
++ /* For some cores, it consumes two varying for position, so the max varying vectors should minus one. */
++ if ((Identity->chipModel == gcv5000 && Identity->chipRevision == 0x5434) ||
++ (Identity->chipModel == gcv4000 && Identity->chipRevision == 0x5222) ||
++ (Identity->chipModel == gcv4000 && Identity->chipRevision == 0x5208) ||
++ (Identity->chipModel == gcv4000 && Identity->chipRevision == 0x5245) ||
++ (Identity->chipModel == gcv3000 && Identity->chipRevision == 0x5435) ||
++ (Identity->chipModel == gcv2200 && Identity->chipRevision == 0x5244) ||
++ (Identity->chipModel == gcv1500 && Identity->chipRevision == 0x5246) ||
++ ((Identity->chipModel == gcv2100 || Identity->chipModel == gcv2000) && Identity->chipRevision == 0x5108) ||
++ (Identity->chipModel == gcv880 && (Identity->chipRevision == 0x5107 || Identity->chipRevision == 0x5106)))
++ {
++ Identity->varyingsCount -= 1;
++ }
++
++ Identity->chip2DControl = 0;
++ if (Identity->chipModel == gcv320)
++ {
++ gctUINT32 data;
++
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os,
++ Core,
++ 0x0002C,
++ &data));
++
++ if ((data != 33956864) &&
++ ((Identity->chipRevision == 0x5007) ||
++ (Identity->chipRevision == 0x5220)))
++ {
++ Identity->chip2DControl |= 0xFF &
++ (Identity->chipRevision == 0x5220 ? 8 :
++ (Identity->chipRevision == 0x5007 ? 12 : 0));
++ }
++
++ if (Identity->chipRevision == 0x5007)
++ {
++ /* Disable splitting rectangle. */
++ Identity->chip2DControl |= 0x100;
++
++ /* Enable 2D Flush. */
++ Identity->chip2DControl |= 0x200;
++ }
++ }
++
++#if gcdMULTI_GPU
++#if gcdMULTI_GPU > 1
++ Identity->gpuCoreCount = gpuCoreCount + 1;
++#else
++ Identity->gpuCoreCount = 1;
++#endif
++#endif
++
++ /* Success. */
++ gcmkFOOTER();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++#define gcdDEBUG_MODULE_CLOCK_GATING 0
++#define gcdDISABLE_MODULE_CLOCK_GATING 0
++#define gcdDISABLE_FE_CLOCK_GATING 0
++#define gcdDISABLE_PE_CLOCK_GATING 0
++#define gcdDISABLE_SH_CLOCK_GATING 0
++#define gcdDISABLE_PA_CLOCK_GATING 0
++#define gcdDISABLE_SE_CLOCK_GATING 0
++#define gcdDISABLE_RA_CLOCK_GATING 0
++#define gcdDISABLE_RA_EZ_CLOCK_GATING 0
++#define gcdDISABLE_RA_HZ_CLOCK_GATING 0
++#define gcdDISABLE_TX_CLOCK_GATING 0
++
++#if gcdDEBUG_MODULE_CLOCK_GATING
++gceSTATUS
++_ConfigureModuleLevelClockGating(
++ gckHARDWARE Hardware
++ )
++{
++ gctUINT32 data;
++
++ gcmkVERIFY_OK(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress
++ + 0x00104,
++ &data));
++
++#if gcdDISABLE_FE_CLOCK_GATING
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)));
++#endif
++
++#if gcdDISABLE_PE_CLOCK_GATING
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2)));
++#endif
++
++#if gcdDISABLE_SH_CLOCK_GATING
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3)));
++#endif
++
++#if gcdDISABLE_PA_CLOCK_GATING
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4)));
++#endif
++
++#if gcdDISABLE_SE_CLOCK_GATING
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5)));
++#endif
++
++#if gcdDISABLE_RA_CLOCK_GATING
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6)));
++#endif
++
++#if gcdDISABLE_TX_CLOCK_GATING
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1))))))) << (0 ? 7:7))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1))))))) << (0 ? 7:7)));
++#endif
++
++#if gcdDISABLE_RA_EZ_CLOCK_GATING
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) << (0 ? 16:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) << (0 ? 16:16)));
++#endif
++
++#if gcdDISABLE_RA_HZ_CLOCK_GATING
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 17:17) - (0 ? 17:17) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 17:17) - (0 ? 17:17) + 1))))))) << (0 ? 17:17))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 17:17) - (0 ? 17:17) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 17:17) - (0 ? 17:17) + 1))))))) << (0 ? 17:17)));
++#endif
++
++ gcmkVERIFY_OK(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress
++ + 0x00104,
++ data));
++
++#if gcdDISABLE_MODULE_CLOCK_GATING
++ gcmkVERIFY_OK(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress +
++ 0x00100,
++ &data));
++
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)));
++
++
++ gcmkVERIFY_OK(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress
++ + 0x00100,
++ data));
++#endif
++
++ return gcvSTATUS_OK;
++}
++#endif
++
++#if gcdPOWEROFF_TIMEOUT
++void
++_PowerTimerFunction(
++ gctPOINTER Data
++ )
++{
++ gckHARDWARE hardware = (gckHARDWARE)Data;
++ gcmkVERIFY_OK(
++ gckHARDWARE_SetPowerManagementState(hardware, gcvPOWER_OFF_TIMEOUT));
++}
++#endif
++
++static gceSTATUS
++_VerifyDMA(
++ IN gckOS Os,
++ IN gceCORE Core,
++ gctUINT32_PTR Address1,
++ gctUINT32_PTR Address2,
++ gctUINT32_PTR State1,
++ gctUINT32_PTR State2
++ )
++{
++ gceSTATUS status;
++ gctUINT32 i;
++
++ gcmkONERROR(gckOS_ReadRegisterEx(Os, Core, 0x660, State1));
++ gcmkONERROR(gckOS_ReadRegisterEx(Os, Core, 0x664, Address1));
++
++ for (i = 0; i < 500; i += 1)
++ {
++ gcmkONERROR(gckOS_ReadRegisterEx(Os, Core, 0x660, State2));
++ gcmkONERROR(gckOS_ReadRegisterEx(Os, Core, 0x664, Address2));
++
++ if (*Address1 != *Address2)
++ {
++ break;
++ }
++
++ if (*State1 != *State2)
++ {
++ break;
++ }
++ }
++
++OnError:
++ return status;
++}
++
++static gceSTATUS
++_DumpDebugRegisters(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gcsiDEBUG_REGISTERS_PTR Descriptor
++ )
++{
++ gceSTATUS status = gcvSTATUS_OK;
++ gctUINT32 select;
++ gctUINT32 data = 0;
++ gctUINT i;
++
++ gcmkHEADER_ARG("Os=0x%X Descriptor=0x%X", Os, Descriptor);
++
++ gcmkPRINT_N(4, " %s debug registers:\n", Descriptor->module);
++
++ for (i = 0; i < Descriptor->count; i += 1)
++ {
++ select = i << Descriptor->shift;
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Os, Core, Descriptor->index, select));
++#if gcdFPGA_BUILD
++ gcmkONERROR(gckOS_Delay(Os, 1000));
++#endif
++ gcmkONERROR(gckOS_ReadRegisterEx(Os, Core, Descriptor->data, &data));
++
++ gcmkPRINT_N(12, " [0x%02X] 0x%08X\n", i, data);
++ }
++
++ select = 0xF << Descriptor->shift;
++
++ for (i = 0; i < 500; i += 1)
++ {
++ gcmkONERROR(gckOS_WriteRegisterEx(Os, Core, Descriptor->index, select));
++#if gcdFPGA_BUILD
++ gcmkONERROR(gckOS_Delay(Os, 1000));
++#endif
++ gcmkONERROR(gckOS_ReadRegisterEx(Os, Core, Descriptor->data, &data));
++
++ if (data == Descriptor->signature)
++ {
++ break;
++ }
++ }
++
++ if (i == 500)
++ {
++ gcmkPRINT_N(4, " failed to obtain the signature (read 0x%08X).\n", data);
++ }
++ else
++ {
++ gcmkPRINT_N(8, " signature = 0x%08X (%d read attempt(s))\n", data, i + 1);
++ }
++
++OnError:
++ /* Return the error. */
++ gcmkFOOTER();
++ return status;
++}
++
++static gceSTATUS
++_IsGPUPresent(
++ IN gckHARDWARE Hardware
++ )
++{
++ gceSTATUS status;
++ gcsHAL_QUERY_CHIP_IDENTITY identity;
++ gctUINT32 control;
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ &control));
++
++ control = ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1)));
++ control = ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ control));
++
++ /* Identify the hardware. */
++ gcmkONERROR(_IdentifyHardware(Hardware->os,
++ Hardware->core,
++ &identity));
++
++ /* Check if these are the same values as saved before. */
++ if ((Hardware->identity.chipModel != identity.chipModel)
++ || (Hardware->identity.chipRevision != identity.chipRevision)
++ || (Hardware->identity.chipFeatures != identity.chipFeatures)
++ || (Hardware->identity.chipMinorFeatures != identity.chipMinorFeatures)
++ || (Hardware->identity.chipMinorFeatures1 != identity.chipMinorFeatures1)
++ || (Hardware->identity.chipMinorFeatures2 != identity.chipMinorFeatures2)
++ )
++ {
++ gcmkPRINT("[galcore]: GPU is not present.");
++ gcmkONERROR(gcvSTATUS_GPU_NOT_RESPONDING);
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the error. */
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++_FlushCache(
++ gckHARDWARE Hardware,
++ gckCOMMAND Command
++ )
++{
++ gceSTATUS status;
++ gctUINT32 bytes, requested;
++ gctPOINTER buffer;
++
++ /* Get the size of the flush command. */
++ gcmkONERROR(gckHARDWARE_Flush(Hardware,
++ gcvFLUSH_ALL,
++ gcvNULL,
++ &requested));
++
++ /* Reserve space in the command queue. */
++ gcmkONERROR(gckCOMMAND_Reserve(Command,
++ requested,
++ &buffer,
++ &bytes));
++
++ /* Append a flush. */
++ gcmkONERROR(gckHARDWARE_Flush(
++ Hardware, gcvFLUSH_ALL, buffer, &bytes
++ ));
++
++ /* Execute the command queue. */
++ gcmkONERROR(gckCOMMAND_Execute(Command, requested));
++
++ return gcvSTATUS_OK;
++
++OnError:
++ return status;
++}
++
++gctBOOL
++_IsGPUIdle(
++ IN gctUINT32 Idle
++ )
++{
++ return (((((gctUINT32) (Idle)) >> (0 ? 0:0)) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1)))))) )
++ && (((((gctUINT32) (Idle)) >> (0 ? 1:1)) & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1)))))) )
++ && (((((gctUINT32) (Idle)) >> (0 ? 3:3)) & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1)))))) )
++ && (((((gctUINT32) (Idle)) >> (0 ? 4:4)) & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1)))))) )
++ && (((((gctUINT32) (Idle)) >> (0 ? 5:5)) & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1)))))) )
++ && (((((gctUINT32) (Idle)) >> (0 ? 6:6)) & ((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1)))))) )
++ && (((((gctUINT32) (Idle)) >> (0 ? 7:7)) & ((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1)))))) )
++ && (((((gctUINT32) (Idle)) >> (0 ? 2:2)) & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1)))))) )
++ ;
++}
++
++/******************************************************************************\
++****************************** gckHARDWARE API code *****************************
++\******************************************************************************/
++
++/*******************************************************************************
++**
++** gckHARDWARE_Construct
++**
++** Construct a new gckHARDWARE object.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an initialized gckOS object.
++**
++** gceCORE Core
++** Specified core.
++**
++** OUTPUT:
++**
++** gckHARDWARE * Hardware
++** Pointer to a variable that will hold the pointer to the gckHARDWARE
++** object.
++*/
++gceSTATUS
++gckHARDWARE_Construct(
++ IN gckOS Os,
++ IN gceCORE Core,
++ OUT gckHARDWARE * Hardware
++ )
++{
++ gceSTATUS status;
++ gckHARDWARE hardware = gcvNULL;
++ gctUINT16 data = 0xff00;
++ gctPOINTER pointer = gcvNULL;
++#if gcdMULTI_GPU_AFFINITY
++ gctUINT32 control;
++#endif
++
++ gcmkHEADER_ARG("Os=0x%x", Os);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Hardware != gcvNULL);
++
++ /* Enable the GPU. */
++ gcmkONERROR(gckOS_SetGPUPower(Os, Core, gcvTRUE, gcvTRUE));
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ Core,
++ 0x00000,
++ 0x00000900));
++
++ /* Allocate the gckHARDWARE object. */
++ gcmkONERROR(gckOS_Allocate(Os,
++ gcmSIZEOF(struct _gckHARDWARE),
++ &pointer));
++
++ hardware = (gckHARDWARE) pointer;
++
++ /* Initialize the gckHARDWARE object. */
++ hardware->object.type = gcvOBJ_HARDWARE;
++ hardware->os = Os;
++ hardware->core = Core;
++
++ /* Identify the hardware. */
++ gcmkONERROR(_IdentifyHardware(Os, Core, &hardware->identity));
++
++ /* Determine the hardware type */
++ switch (hardware->identity.chipModel)
++ {
++ case gcv350:
++ case gcv355:
++ hardware->type = gcvHARDWARE_VG;
++ break;
++
++ case gcv200:
++ case gcv300:
++ case gcv320:
++ case gcv328:
++ case gcv420:
++ case gcv428:
++ hardware->type = gcvHARDWARE_2D;
++ break;
++
++ default:
++#if gcdMULTI_GPU_AFFINITY
++ hardware->type = (Core == gcvCORE_MAJOR) ? gcvHARDWARE_3D : gcvHARDWARE_OCL;
++#else
++ hardware->type = gcvHARDWARE_3D;
++#endif
++
++ if(hardware->identity.chipModel == gcv880 && hardware->identity.chipRevision == 0x5107)
++ {
++ /*set outstanding limit*/
++ gctUINT32 axi_ot;
++ gcmkONERROR(gckOS_ReadRegisterEx(Os, Core, 0x00414, &axi_ot));
++ axi_ot = (axi_ot & (~0xFF)) | 0x00010;
++ gcmkONERROR(gckOS_WriteRegisterEx(Os, Core, 0x00414, axi_ot));
++ }
++
++
++ if ((((((gctUINT32) (hardware->identity.chipFeatures)) >> (0 ? 9:9)) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1)))))) ))
++ {
++ hardware->type = (gceHARDWARE_TYPE) (hardware->type | gcvHARDWARE_2D);
++ }
++ }
++
++ hardware->powerBaseAddress
++ = ((hardware->identity.chipModel == gcv300)
++ && (hardware->identity.chipRevision < 0x2000))
++ ? 0x0100
++ : 0x0000;
++
++ /* _ResetGPU need powerBaseAddress. */
++ status = _ResetGPU(hardware, Os, Core);
++
++ if (status != gcvSTATUS_OK)
++ {
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "_ResetGPU failed: status=%d\n", status);
++ }
++
++#if gcdMULTI_GPU
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ Core,
++ 0x0055C,
++#if gcdDISABLE_FE_L2
++ 0x00FFFFFF));
++#else
++ 0x00FFFF05));
++#endif
++
++#elif gcdMULTI_GPU_AFFINITY
++ control = ((((gctUINT32) (0x00FF0A05)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 27:27) - (0 ? 27:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:27) - (0 ? 27:27) + 1))))))) << (0 ? 27:27))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 27:27) - (0 ? 27:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:27) - (0 ? 27:27) + 1))))))) << (0 ? 27:27)));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ Core,
++ 0x0055C,
++ control));
++#endif
++
++ hardware->powerMutex = gcvNULL;
++
++ hardware->mmuVersion
++ = (((((gctUINT32) (hardware->identity.chipMinorFeatures1)) >> (0 ? 28:28)) & ((gctUINT32) ((((1 ? 28:28) - (0 ? 28:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 28:28) - (0 ? 28:28) + 1)))))) );
++
++ /* Determine whether bug fixes #1 are present. */
++ hardware->extraEventStates = ((((gctUINT32) (hardware->identity.chipMinorFeatures1)) >> (0 ? 3:3) & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1)))))) == (0x0 & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1)))))));
++
++ /* Check if big endian */
++ hardware->bigEndian = (*(gctUINT8 *)&data == 0xff);
++
++ /* Initialize the fast clear. */
++ gcmkONERROR(gckHARDWARE_SetFastClear(hardware, -1, -1));
++
++#if !gcdENABLE_128B_MERGE
++
++ if (((((gctUINT32) (hardware->identity.chipMinorFeatures2)) >> (0 ? 21:21) & ((gctUINT32) ((((1 ? 21:21) - (0 ? 21:21) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 21:21) - (0 ? 21:21) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 21:21) - (0 ? 21:21) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 21:21) - (0 ? 21:21) + 1))))))))
++ {
++ /* 128B merge is turned on by default. Disable it. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Os, Core, 0x00558, 0));
++ }
++
++#endif
++
++ /* Set power state to ON. */
++ hardware->chipPowerState = gcvPOWER_ON;
++ hardware->clockState = gcvTRUE;
++ hardware->powerState = gcvTRUE;
++ hardware->lastWaitLink = ~0U;
++ hardware->lastEnd = ~0U;
++ hardware->globalSemaphore = gcvNULL;
++#if gcdENABLE_FSCALE_VAL_ADJUST
++ hardware->powerOnFscaleVal = 64;
++#endif
++
++ gcmkONERROR(gckOS_CreateMutex(Os, &hardware->powerMutex));
++ gcmkONERROR(gckOS_CreateSemaphore(Os, &hardware->globalSemaphore));
++ hardware->startIsr = gcvNULL;
++ hardware->stopIsr = gcvNULL;
++
++#if gcdPOWEROFF_TIMEOUT
++ hardware->powerOffTimeout = gcdPOWEROFF_TIMEOUT;
++
++ gcmkVERIFY_OK(gckOS_CreateTimer(Os,
++ _PowerTimerFunction,
++ (gctPOINTER)hardware,
++ &hardware->powerOffTimer));
++#endif
++
++ gcmkONERROR(gckOS_AtomConstruct(Os, &hardware->pageTableDirty));
++ gcmkONERROR(gckOS_AtomConstruct(Os, &hardware->pendingEvent));
++
++#if gcdLINK_QUEUE_SIZE
++ hardware->linkQueue.front = 0;
++ hardware->linkQueue.rear = 0;
++ hardware->linkQueue.count = 0;
++#endif
++
++ /* Enable power management by default. */
++ hardware->powerManagement = gcvTRUE;
++
++ /* Disable profiler by default */
++ hardware->gpuProfiler = gcvFALSE;
++
++#if defined(LINUX) || defined(__QNXNTO__) || defined(UNDERCE)
++ if (hardware->mmuVersion)
++ {
++ hardware->endAfterFlushMmuCache = gcvTRUE;
++ }
++ else
++#endif
++ {
++ hardware->endAfterFlushMmuCache = gcvFALSE;
++ }
++
++ gcmkONERROR(gckOS_QueryOption(Os, "mmu", (gctUINT32_PTR)&hardware->enableMMU));
++
++ hardware->minFscaleValue = 1;
++
++ /* Return pointer to the gckHARDWARE object. */
++ *Hardware = hardware;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Hardware=0x%x", *Hardware);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Roll back. */
++ if (hardware != gcvNULL)
++ {
++ /* Turn off the power. */
++ gcmkVERIFY_OK(gckOS_SetGPUPower(Os, Core, gcvFALSE, gcvFALSE));
++
++ if (hardware->globalSemaphore != gcvNULL)
++ {
++ /* Destroy the global semaphore. */
++ gcmkVERIFY_OK(gckOS_DestroySemaphore(Os,
++ hardware->globalSemaphore));
++ }
++
++ if (hardware->powerMutex != gcvNULL)
++ {
++ /* Destroy the power mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Os, hardware->powerMutex));
++ }
++
++#if gcdPOWEROFF_TIMEOUT
++ if (hardware->powerOffTimer != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_StopTimer(Os, hardware->powerOffTimer));
++ gcmkVERIFY_OK(gckOS_DestroyTimer(Os, hardware->powerOffTimer));
++ }
++#endif
++
++ if (hardware->pageTableDirty != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_AtomDestroy(Os, hardware->pageTableDirty));
++ }
++
++ if (hardware->pendingEvent != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_AtomDestroy(Os, hardware->pendingEvent));
++ }
++
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Os, hardware));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_Destroy
++**
++** Destroy an gckHARDWARE object.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to the gckHARDWARE object that needs to be destroyed.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckHARDWARE_Destroy(
++ IN gckHARDWARE Hardware
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Destroy the power semaphore. */
++ gcmkVERIFY_OK(gckOS_DestroySemaphore(Hardware->os,
++ Hardware->globalSemaphore));
++
++ /* Destroy the power mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Hardware->os, Hardware->powerMutex));
++
++#if gcdPOWEROFF_TIMEOUT
++ gcmkVERIFY_OK(gckOS_StopTimer(Hardware->os, Hardware->powerOffTimer));
++ gcmkVERIFY_OK(gckOS_DestroyTimer(Hardware->os, Hardware->powerOffTimer));
++#endif
++
++ gcmkVERIFY_OK(gckOS_AtomDestroy(Hardware->os, Hardware->pageTableDirty));
++
++ gcmkVERIFY_OK(gckOS_AtomDestroy(Hardware->os, Hardware->pendingEvent));
++
++ gcmkVERIFY_OK(gckOS_FreeNonPagedMemory(
++ Hardware->os,
++ Hardware->functionBytes,
++ Hardware->functionPhysical,
++ Hardware->functionLogical
++ ));
++
++ /* Mark the object as unknown. */
++ Hardware->object.type = gcvOBJ_UNKNOWN;
++
++ /* Free the object. */
++ gcmkONERROR(gcmkOS_SAFE_FREE(Hardware->os, Hardware));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_GetType
++**
++** Get the hardware type.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** OUTPUT:
++**
++** gceHARDWARE_TYPE * Type
++** Pointer to a variable that receives the type of hardware object.
++*/
++gceSTATUS
++gckHARDWARE_GetType(
++ IN gckHARDWARE Hardware,
++ OUT gceHARDWARE_TYPE * Type
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++ gcmkVERIFY_ARGUMENT(Type != gcvNULL);
++
++ *Type = Hardware->type;
++
++ gcmkFOOTER_ARG("*Type=%d", *Type);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_InitializeHardware
++**
++** Initialize the hardware.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to the gckHARDWARE object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckHARDWARE_InitializeHardware(
++ IN gckHARDWARE Hardware
++ )
++{
++ gceSTATUS status;
++ gctUINT32 baseAddress;
++ gctUINT32 chipRev;
++ gctUINT32 control;
++ gctUINT32 data;
++ gctUINT32 regPMC = 0;
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Read the chip revision register. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00024,
++ &chipRev));
++
++ if (chipRev != Hardware->identity.chipRevision)
++ {
++ /* Chip is not there! */
++ gcmkONERROR(gcvSTATUS_CONTEXT_LOSSED);
++ }
++
++ /* Disable isolate GPU bit. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ ((((gctUINT32) (0x00000900)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19)))));
++
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ &control));
++
++ /* Enable debug register. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 11:11) - (0 ? 11:11) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:11) - (0 ? 11:11) + 1))))))) << (0 ? 11:11))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 11:11) - (0 ? 11:11) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:11) - (0 ? 11:11) + 1))))))) << (0 ? 11:11)))));
++
++ /* Reset memory counters. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0003C,
++ ~0U));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0003C,
++ 0));
++
++ /* Get the system's physical base address. */
++ gcmkONERROR(gckOS_GetBaseAddress(Hardware->os, &baseAddress));
++
++ /* Program the base addesses. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0041C,
++ baseAddress));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00418,
++ baseAddress));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00428,
++ baseAddress));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00420,
++ baseAddress));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00424,
++ baseAddress));
++
++ {
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress +
++ 0x00100,
++ &data));
++
++ /* Enable clock gating. */
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)));
++
++ if ((Hardware->identity.chipRevision == 0x4301)
++ || (Hardware->identity.chipRevision == 0x4302)
++ )
++ {
++ /* Disable stall module level clock gating for 4.3.0.1 and 4.3.0.2
++ ** revisions. */
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1)));
++ }
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress
++ + 0x00100,
++ data));
++
++#if gcdENABLE_3D
++ /* Disable PE clock gating on revs < 5.0 when HZ is present without a
++ ** bug fix. */
++ if ((Hardware->identity.chipRevision < 0x5000)
++ && gckHARDWARE_IsFeatureAvailable(Hardware, gcvFEATURE_HZ)
++ && ((((gctUINT32) (Hardware->identity.chipMinorFeatures1)) >> (0 ? 9:9) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1)))))) == (0x0 & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1)))))))
++ )
++ {
++ if (regPMC == 0)
++ {
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress
++ + 0x00104,
++ &regPMC));
++ }
++
++ /* Disable PE clock gating. */
++ regPMC = ((((gctUINT32) (regPMC)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2)));
++ }
++
++#endif
++ }
++
++ if (Hardware->identity.chipModel == gcv4000 &&
++ ((Hardware->identity.chipRevision == 0x5208) || (Hardware->identity.chipRevision == 0x5222)))
++ {
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0010C,
++ ((((gctUINT32) (0x01590880)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:23) - (0 ? 23:23) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:23) - (0 ? 23:23) + 1))))))) << (0 ? 23:23))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 23:23) - (0 ? 23:23) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:23) - (0 ? 23:23) + 1))))))) << (0 ? 23:23)))));
++ }
++
++ if (Hardware->identity.chipModel == gcv1000 &&
++ (Hardware->identity.chipRevision == 0x5039 ||
++ Hardware->identity.chipRevision == 0x5040))
++ {
++ gctUINT32 pulseEater;
++
++ pulseEater = ((((gctUINT32) (0x01590880)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) << (0 ? 16:16))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) << (0 ? 16:16)));
++
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0010C,
++ ((((gctUINT32) (pulseEater)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 17:17) - (0 ? 17:17) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 17:17) - (0 ? 17:17) + 1))))))) << (0 ? 17:17))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 17:17) - (0 ? 17:17) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 17:17) - (0 ? 17:17) + 1))))))) << (0 ? 17:17)))));
++ }
++
++ if ((gckHARDWARE_IsFeatureAvailable(Hardware, gcvFEATURE_HALTI2) == gcvSTATUS_FALSE)
++ || (Hardware->identity.chipRevision < 0x5422)
++ )
++ {
++ if (regPMC == 0)
++ {
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress
++ + 0x00104,
++ &regPMC));
++ }
++
++ regPMC = ((((gctUINT32) (regPMC)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:15) - (0 ? 15:15) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:15) - (0 ? 15:15) + 1))))))) << (0 ? 15:15))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 15:15) - (0 ? 15:15) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:15) - (0 ? 15:15) + 1))))))) << (0 ? 15:15)));
++ }
++
++ if (_IsHardwareMatch(Hardware, gcv2000, 0x5108))
++ {
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00480,
++ &data));
++
++ /* Set FE bus to one, TX bus to zero */
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3)));
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1))))))) << (0 ? 7:7))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1))))))) << (0 ? 7:7)));
++
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00480,
++ data));
++ }
++
++ gcmkONERROR(
++ gckHARDWARE_SetMMU(Hardware,
++ Hardware->kernel->mmu->pageTableLogical));
++
++ if (Hardware->identity.chipModel >= gcv400
++ && Hardware->identity.chipModel != gcv420)
++ {
++ if (regPMC == 0)
++ {
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress
++ + 0x00104,
++ &regPMC));
++ }
++
++ /* Disable PA clock gating. */
++ regPMC = ((((gctUINT32) (regPMC)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4)));
++ }
++
++ /* Limit 2D outstanding request. */
++ if (_IsHardwareMatch(Hardware, gcv880, 0x5107))
++ {
++ gctUINT32 axi_ot;
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00414, &axi_ot));
++ axi_ot = (axi_ot & (~0xFF)) | 0x00010;
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00414, axi_ot));
++ }
++
++ if (Hardware->identity.chip2DControl & 0xFF)
++ {
++ gctUINT32 data;
++
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00414,
++ &data));
++
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (Hardware->identity.chip2DControl & 0xFF) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0)));
++
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00414,
++ data));
++ }
++
++ if (_IsHardwareMatch(Hardware, gcv1000, 0x5035))
++ {
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00414,
++ &data));
++
++ /* Disable HZ-L2. */
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12)));
++
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00414,
++ data));
++ }
++
++ if (_IsHardwareMatch(Hardware, gcv4000, 0x5222))
++ {
++ if (regPMC == 0)
++ {
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress
++ + 0x00104,
++ &regPMC));
++ }
++
++ /* Disable TX clock gating. */
++ regPMC = ((((gctUINT32) (regPMC)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1))))))) << (0 ? 7:7))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1))))))) << (0 ? 7:7)));
++ }
++
++ if (_IsHardwareMatch(Hardware, gcv880, 0x5106))
++ {
++ Hardware->kernel->timeOut = 140 * 1000;
++ }
++
++ if (regPMC == 0)
++ {
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress
++ + 0x00104,
++ &regPMC));
++ }
++
++ /* Disable RA HZ clock gating. */
++ regPMC = ((((gctUINT32) (regPMC)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 17:17) - (0 ? 17:17) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 17:17) - (0 ? 17:17) + 1))))))) << (0 ? 17:17))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 17:17) - (0 ? 17:17) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 17:17) - (0 ? 17:17) + 1))))))) << (0 ? 17:17)));
++
++ /* Disable RA EZ clock gating. */
++ regPMC = ((((gctUINT32) (regPMC)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) << (0 ? 16:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) << (0 ? 16:16)));
++
++ if (regPMC != 0)
++ {
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress
++ + 0x00104,
++ regPMC));
++ }
++
++ if (_IsHardwareMatch(Hardware, gcv2000, 0x5108)
++ || _IsHardwareMatch(Hardware, gcv320, 0x5007)
++ || _IsHardwareMatch(Hardware, gcv880, 0x5106)
++ || _IsHardwareMatch(Hardware, gcv400, 0x4645)
++ )
++ {
++ /* Update GPU AXI cache atttribute. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00008,
++ 0x00002200));
++ }
++
++
++ if ((Hardware->identity.chipRevision > 0x5420)
++ && gckHARDWARE_IsFeatureAvailable(Hardware, gcvFEATURE_PIPE_3D))
++ {
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0010C,
++ &data));
++
++ /* Disable internal DFS. */
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 18:18) - (0 ? 18:18) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 18:18) - (0 ? 18:18) + 1))))))) << (0 ? 18:18))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 18:18) - (0 ? 18:18) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 18:18) - (0 ? 18:18) + 1))))))) << (0 ? 18:18)));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0010C,
++ data));
++ }
++
++#if gcdDEBUG_MODULE_CLOCK_GATING
++ _ConfigureModuleLevelClockGating(Hardware);
++#endif
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the error. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_QueryMemory
++**
++** Query the amount of memory available on the hardware.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to the gckHARDWARE object.
++**
++** OUTPUT:
++**
++** gctSIZE_T * InternalSize
++** Pointer to a variable that will hold the size of the internal video
++** memory in bytes. If 'InternalSize' is gcvNULL, no information of the
++** internal memory will be returned.
++**
++** gctUINT32 * InternalBaseAddress
++** Pointer to a variable that will hold the hardware's base address for
++** the internal video memory. This pointer cannot be gcvNULL if
++** 'InternalSize' is also non-gcvNULL.
++**
++** gctUINT32 * InternalAlignment
++** Pointer to a variable that will hold the hardware's base address for
++** the internal video memory. This pointer cannot be gcvNULL if
++** 'InternalSize' is also non-gcvNULL.
++**
++** gctSIZE_T * ExternalSize
++** Pointer to a variable that will hold the size of the external video
++** memory in bytes. If 'ExternalSize' is gcvNULL, no information of the
++** external memory will be returned.
++**
++** gctUINT32 * ExternalBaseAddress
++** Pointer to a variable that will hold the hardware's base address for
++** the external video memory. This pointer cannot be gcvNULL if
++** 'ExternalSize' is also non-gcvNULL.
++**
++** gctUINT32 * ExternalAlignment
++** Pointer to a variable that will hold the hardware's base address for
++** the external video memory. This pointer cannot be gcvNULL if
++** 'ExternalSize' is also non-gcvNULL.
++**
++** gctUINT32 * HorizontalTileSize
++** Number of horizontal pixels per tile. If 'HorizontalTileSize' is
++** gcvNULL, no horizontal pixel per tile will be returned.
++**
++** gctUINT32 * VerticalTileSize
++** Number of vertical pixels per tile. If 'VerticalTileSize' is
++** gcvNULL, no vertical pixel per tile will be returned.
++*/
++gceSTATUS
++gckHARDWARE_QueryMemory(
++ IN gckHARDWARE Hardware,
++ OUT gctSIZE_T * InternalSize,
++ OUT gctUINT32 * InternalBaseAddress,
++ OUT gctUINT32 * InternalAlignment,
++ OUT gctSIZE_T * ExternalSize,
++ OUT gctUINT32 * ExternalBaseAddress,
++ OUT gctUINT32 * ExternalAlignment,
++ OUT gctUINT32 * HorizontalTileSize,
++ OUT gctUINT32 * VerticalTileSize
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ if (InternalSize != gcvNULL)
++ {
++ /* No internal memory. */
++ *InternalSize = 0;
++ }
++
++ if (ExternalSize != gcvNULL)
++ {
++ /* No external memory. */
++ *ExternalSize = 0;
++ }
++
++ if (HorizontalTileSize != gcvNULL)
++ {
++ /* 4x4 tiles. */
++ *HorizontalTileSize = 4;
++ }
++
++ if (VerticalTileSize != gcvNULL)
++ {
++ /* 4x4 tiles. */
++ *VerticalTileSize = 4;
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*InternalSize=%lu *InternalBaseAddress=0x%08x "
++ "*InternalAlignment=0x%08x *ExternalSize=%lu "
++ "*ExternalBaseAddress=0x%08x *ExtenalAlignment=0x%08x "
++ "*HorizontalTileSize=%u *VerticalTileSize=%u",
++ gcmOPT_VALUE(InternalSize),
++ gcmOPT_VALUE(InternalBaseAddress),
++ gcmOPT_VALUE(InternalAlignment),
++ gcmOPT_VALUE(ExternalSize),
++ gcmOPT_VALUE(ExternalBaseAddress),
++ gcmOPT_VALUE(ExternalAlignment),
++ gcmOPT_VALUE(HorizontalTileSize),
++ gcmOPT_VALUE(VerticalTileSize));
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_QueryChipIdentity
++**
++** Query the identity of the hardware.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to the gckHARDWARE object.
++**
++** OUTPUT:
++**
++** gcsHAL_QUERY_CHIP_IDENTITY_PTR Identity
++** Pointer to the identity structure.
++**
++*/
++gceSTATUS
++gckHARDWARE_QueryChipIdentity(
++ IN gckHARDWARE Hardware,
++ OUT gcsHAL_QUERY_CHIP_IDENTITY_PTR Identity
++ )
++{
++ gctUINT32 features;
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(Identity != gcvNULL);
++
++ /* Return chip model and revision. */
++ Identity->chipModel = Hardware->identity.chipModel;
++ Identity->chipRevision = Hardware->identity.chipRevision;
++
++ /* Return feature set. */
++ features = Hardware->identity.chipFeatures;
++
++ if ((((((gctUINT32) (features)) >> (0 ? 0:0)) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1)))))) ))
++ {
++ /* Override fast clear by command line. */
++ features = ((((gctUINT32) (features)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (Hardware->allowFastClear) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)));
++ }
++
++ if ((((((gctUINT32) (features)) >> (0 ? 5:5)) & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1)))))) ))
++ {
++ /* Override compression by command line. */
++ features = ((((gctUINT32) (features)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))) | (((gctUINT32) ((gctUINT32) (Hardware->allowCompression) & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5)));
++ }
++
++ /* Mark 2D pipe as available for GC500.0 through GC500.2 and GC300,
++ ** since they did not have this bit. */
++ if (((Hardware->identity.chipModel == gcv500) && (Hardware->identity.chipRevision <= 2))
++ || (Hardware->identity.chipModel == gcv300)
++ )
++ {
++ features = ((((gctUINT32) (features)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9)));
++ }
++
++ Identity->chipFeatures = features;
++
++ /* Return minor features. */
++ Identity->chipMinorFeatures = Hardware->identity.chipMinorFeatures;
++ Identity->chipMinorFeatures1 = Hardware->identity.chipMinorFeatures1;
++ Identity->chipMinorFeatures2 = Hardware->identity.chipMinorFeatures2;
++ Identity->chipMinorFeatures3 = Hardware->identity.chipMinorFeatures3;
++ Identity->chipMinorFeatures4 = Hardware->identity.chipMinorFeatures4;
++ Identity->chipMinorFeatures5 = Hardware->identity.chipMinorFeatures5;
++
++ /* Return chip specs. */
++ Identity->streamCount = Hardware->identity.streamCount;
++ Identity->registerMax = Hardware->identity.registerMax;
++ Identity->threadCount = Hardware->identity.threadCount;
++ Identity->shaderCoreCount = Hardware->identity.shaderCoreCount;
++ Identity->vertexCacheSize = Hardware->identity.vertexCacheSize;
++ Identity->vertexOutputBufferSize = Hardware->identity.vertexOutputBufferSize;
++ Identity->pixelPipes = Hardware->identity.pixelPipes;
++ Identity->instructionCount = Hardware->identity.instructionCount;
++ Identity->numConstants = Hardware->identity.numConstants;
++ Identity->bufferSize = Hardware->identity.bufferSize;
++ Identity->varyingsCount = Hardware->identity.varyingsCount;
++ Identity->superTileMode = Hardware->identity.superTileMode;
++#if gcdMULTI_GPU
++ Identity->gpuCoreCount = Hardware->identity.gpuCoreCount;
++#endif
++ Identity->chip2DControl = Hardware->identity.chip2DControl;
++
++ Identity->productID = Hardware->identity.productID;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_SplitMemory
++**
++** Split a hardware specific memory address into a pool and offset.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to the gckHARDWARE object.
++**
++** gctUINT32 Address
++** Address in hardware specific format.
++**
++** OUTPUT:
++**
++** gcePOOL * Pool
++** Pointer to a variable that will hold the pool type for the address.
++**
++** gctUINT32 * Offset
++** Pointer to a variable that will hold the offset for the address.
++*/
++gceSTATUS
++gckHARDWARE_SplitMemory(
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 Address,
++ OUT gcePOOL * Pool,
++ OUT gctUINT32 * Offset
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x Addres=0x%08x", Hardware, Address);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(Pool != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Offset != gcvNULL);
++
++ if (Hardware->mmuVersion == 0)
++ {
++ /* Dispatch on memory type. */
++ switch ((((((gctUINT32) (Address)) >> (0 ? 31:31)) & ((gctUINT32) ((((1 ? 31:31) - (0 ? 31:31) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:31) - (0 ? 31:31) + 1)))))) ))
++ {
++ case 0x0:
++ /* System memory. */
++ *Pool = gcvPOOL_SYSTEM;
++ break;
++
++ case 0x1:
++ /* Virtual memory. */
++ *Pool = gcvPOOL_VIRTUAL;
++ break;
++
++ default:
++ /* Invalid memory type. */
++ gcmkFOOTER_ARG("status=%d", gcvSTATUS_INVALID_ARGUMENT);
++ return gcvSTATUS_INVALID_ARGUMENT;
++ }
++
++ /* Return offset of address. */
++ *Offset = (((((gctUINT32) (Address)) >> (0 ? 30:0)) & ((gctUINT32) ((((1 ? 30:0) - (0 ? 30:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 30:0) - (0 ? 30:0) + 1)))))) );
++ }
++ else
++ {
++ *Pool = gcvPOOL_SYSTEM;
++ *Offset = Address;
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Pool=%d *Offset=0x%08x", *Pool, *Offset);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_Execute
++**
++** Kickstart the hardware's command processor with an initialized command
++** buffer.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to the gckHARDWARE object.
++**
++** gctUINT32 Address
++** Hardware address of command buffer.
++**
++** gctSIZE_T Bytes
++** Number of bytes for the prefetch unit (until after the first LINK).
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckHARDWARE_Execute(
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 Address,
++ IN gctSIZE_T Bytes
++ )
++{
++ gceSTATUS status;
++ gctUINT32 control;
++
++ gcmkHEADER_ARG("Hardware=0x%x Address=0x%x Bytes=%lu",
++ Hardware, Address, Bytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Enable all events. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00014, ~0U));
++
++ /* Write address register. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00654, Address));
++
++ /* Build control register. */
++ control = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) << (0 ? 16:16))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) << (0 ? 16:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) ((Bytes + 7) >> 3) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ /* Set big endian */
++ if (Hardware->bigEndian)
++ {
++ control |= ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 21:20) - (0 ? 21:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 21:20) - (0 ? 21:20) + 1))))))) << (0 ? 21:20))) | (((gctUINT32) (0x2 & ((gctUINT32) ((((1 ? 21:20) - (0 ? 21:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 21:20) - (0 ? 21:20) + 1))))))) << (0 ? 21:20)));
++ }
++
++ /* Write control register. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00658, control));
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Started command buffer @ 0x%08x",
++ Address);
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_WaitLink
++**
++** Append a WAIT/LINK command sequence at the specified location in the command
++** queue.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to an gckHARDWARE object.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command queue to append
++** WAIT/LINK command sequence at or gcvNULL just to query the size of the
++** WAIT/LINK command sequence.
++**
++** gctUINT32 Offset
++** Offset into command buffer required for alignment.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the WAIT/LINK command
++** sequence. If 'Logical' is gcvNULL, this argument will be ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** by the WAIT/LINK command sequence. If 'Bytes' is gcvNULL, nothing will
++** be returned.
++**
++** gctUINT32 * WaitOffset
++** Pointer to a variable that will receive the offset of the WAIT command
++** from the specified logcial pointer.
++** If 'WaitOffset' is gcvNULL nothing will be returned.
++**
++** gctSIZE_T * WaitSize
++** Pointer to a variable that will receive the number of bytes used by
++** the WAIT command. If 'LinkSize' is gcvNULL nothing will be returned.
++*/
++gceSTATUS
++gckHARDWARE_WaitLink(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Offset,
++ IN OUT gctUINT32 * Bytes,
++ OUT gctUINT32 * WaitOffset,
++ OUT gctUINT32 * WaitSize
++ )
++{
++ static const gctUINT waitCount = 200;
++
++ gceSTATUS status;
++ gctUINT32 address;
++ gctUINT32_PTR logical;
++ gctUINT32 bytes;
++
++ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x Offset=0x%08x *Bytes=%lu",
++ Hardware, Logical, Offset, gcmOPT_VALUE(Bytes));
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT((Logical != gcvNULL) || (Bytes != gcvNULL));
++
++#if gcdMULTI_GPU && !gcdDISABLE_FE_L2
++ bytes = gcmALIGN(Offset + 40, 8) - Offset;
++#else
++ /* Compute number of bytes required. */
++ bytes = gcmALIGN(Offset + 16, 8) - Offset;
++#endif
++ /* Cast the input pointer. */
++ logical = (gctUINT32_PTR) Logical;
++
++ if (logical != gcvNULL)
++ {
++ /* Not enough space? */
++ if (*Bytes < bytes)
++ {
++ /* Command queue too small. */
++ gcmkONERROR(gcvSTATUS_BUFFER_TOO_SMALL);
++ }
++
++ /* Convert logical into hardware specific address. */
++ gcmkONERROR(gckHARDWARE_ConvertLogical(Hardware, logical, gcvFALSE, &address));
++
++ /* Store the WAIT/LINK address. */
++ Hardware->lastWaitLink = address;
++
++ /* Append WAIT(count). */
++ logical[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (waitCount) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++#if gcdMULTI_GPU && !gcdDISABLE_FE_L2
++ logical[2] = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x0D & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | gcvCORE_3D_0_MASK;
++
++ logical[3] = 0;
++
++ /* LoadState(AQFlush, 1), flush. */
++ logical[4] = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E03) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ logical[5] = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6)));
++
++ logical[6] = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x0D & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | gcvCORE_3D_ALL_MASK;
++
++ logical[7] = 0;
++
++ /* Append LINK(2, address). */
++ logical[8] = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x08 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (bytes >> 3) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ logical[9] = address;
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "0x%08x: WAIT %u", address, waitCount
++ );
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "0x%x: FLUSH 0x%x", address + 8, logical[3]);
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "0x%08x: LINK 0x%08x, #%lu",
++ address + 16, address, bytes
++ );
++#else
++
++ /* Append LINK(2, address). */
++ logical[2]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x08 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (bytes >> 3) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ logical[3] = address;
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "0x%08x: WAIT %u", address, waitCount
++ );
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "0x%08x: LINK 0x%08x, #%lu",
++ address + 8, address, bytes
++ );
++#endif
++ if (WaitOffset != gcvNULL)
++ {
++ /* Return the offset pointer to WAIT command. */
++ *WaitOffset = 0;
++ }
++
++ if (WaitSize != gcvNULL)
++ {
++ /* Return number of bytes used by the WAIT command. */
++#if gcdMULTI_GPU && !gcdDISABLE_FE_L2
++ *WaitSize = 32;
++#else
++ *WaitSize = 8;
++#endif
++ }
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the WAIT/LINK command
++ ** sequence. */
++ *Bytes = bytes;
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Bytes=%lu *WaitOffset=0x%x *WaitSize=%lu",
++ gcmOPT_VALUE(Bytes), gcmOPT_VALUE(WaitOffset),
++ gcmOPT_VALUE(WaitSize));
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_End
++**
++** Append an END command at the specified location in the command queue.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to an gckHARDWARE object.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command queue to append
++** END command at or gcvNULL just to query the size of the END command.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the END command. If
++** 'Logical' is gcvNULL, this argument will be ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** for the END command. If 'Bytes' is gcvNULL, nothing will be returned.
++*/
++gceSTATUS
++gckHARDWARE_End(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN OUT gctUINT32 * Bytes
++ )
++{
++ gctUINT32_PTR logical = (gctUINT32_PTR) Logical;
++ gctUINT32 address;
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x *Bytes=%lu",
++ Hardware, Logical, gcmOPT_VALUE(Bytes));
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT((Logical == gcvNULL) || (Bytes != gcvNULL));
++
++ if (Logical != gcvNULL)
++ {
++ if (*Bytes < 8)
++ {
++ /* Command queue too small. */
++ gcmkONERROR(gcvSTATUS_BUFFER_TOO_SMALL);
++ }
++
++ /* Append END. */
++ logical[0] =
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x02 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, "0x%x: END", Logical);
++
++ /* Make sure the CPU writes out the data to memory. */
++ gcmkONERROR(
++ gckOS_MemoryBarrier(Hardware->os, Logical));
++
++ gcmkONERROR(gckHARDWARE_ConvertLogical(Hardware, logical, gcvFALSE, &address));
++
++ Hardware->lastEnd = address;
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the END command. */
++ *Bytes = 8;
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Bytes=%lu", gcmOPT_VALUE(Bytes));
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++#if gcdMULTI_GPU
++gceSTATUS
++gckHARDWARE_ChipEnable(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN gceCORE_3D_MASK ChipEnable,
++ IN OUT gctSIZE_T * Bytes
++ )
++{
++ gctUINT32_PTR logical = (gctUINT32_PTR) Logical;
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x ChipEnable=0x%x *Bytes=%lu",
++ Hardware, Logical, ChipEnable, gcmOPT_VALUE(Bytes));
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT((Logical == gcvNULL) || (Bytes != gcvNULL));
++
++ if (Logical != gcvNULL)
++ {
++ if (*Bytes < 8)
++ {
++ /* Command queue too small. */
++ gcmkONERROR(gcvSTATUS_BUFFER_TOO_SMALL);
++ }
++
++ /* Append CHIPENABLE. */
++ logical[0] = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x0D & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ChipEnable;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, "0x%x: CHIPENABLE 0x%x", Logical, ChipEnable);
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the CHIPENABLE command. */
++ *Bytes = 8;
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Bytes=%lu", gcmOPT_VALUE(Bytes));
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++#endif
++
++/*******************************************************************************
++**
++** gckHARDWARE_Nop
++**
++** Append a NOP command at the specified location in the command queue.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to an gckHARDWARE object.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command queue to append
++** NOP command at or gcvNULL just to query the size of the NOP command.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the NOP command. If
++** 'Logical' is gcvNULL, this argument will be ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** for the NOP command. If 'Bytes' is gcvNULL, nothing will be returned.
++*/
++gceSTATUS
++gckHARDWARE_Nop(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN OUT gctSIZE_T * Bytes
++ )
++{
++ gctUINT32_PTR logical = (gctUINT32_PTR) Logical;
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x *Bytes=%lu",
++ Hardware, Logical, gcmOPT_VALUE(Bytes));
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT((Logical == gcvNULL) || (Bytes != gcvNULL));
++
++ if (Logical != gcvNULL)
++ {
++ if (*Bytes < 8)
++ {
++ /* Command queue too small. */
++ gcmkONERROR(gcvSTATUS_BUFFER_TOO_SMALL);
++ }
++
++ /* Append NOP. */
++ logical[0] = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x03 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, "0x%x: NOP", Logical);
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the NOP command. */
++ *Bytes = 8;
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Bytes=%lu", gcmOPT_VALUE(Bytes));
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_Event
++**
++** Append an EVENT command at the specified location in the command queue.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to an gckHARDWARE object.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command queue to append
++** the EVENT command at or gcvNULL just to query the size of the EVENT
++** command.
++**
++** gctUINT8 Event
++** Event ID to program.
++**
++** gceKERNEL_WHERE FromWhere
++** Location of the pipe to send the event.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the EVENT command. If
++** 'Logical' is gcvNULL, this argument will be ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** for the EVENT command. If 'Bytes' is gcvNULL, nothing will be
++** returned.
++*/
++gceSTATUS
++gckHARDWARE_Event(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN gctUINT8 Event,
++ IN gceKERNEL_WHERE FromWhere,
++ IN OUT gctUINT32 * Bytes
++ )
++{
++ gctUINT size;
++ gctUINT32 destination = 0;
++ gctUINT32_PTR logical = (gctUINT32_PTR) Logical;
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x Event=%u FromWhere=%d *Bytes=%lu",
++ Hardware, Logical, Event, FromWhere, gcmOPT_VALUE(Bytes));
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT((Logical == gcvNULL) || (Bytes != gcvNULL));
++ gcmkVERIFY_ARGUMENT(Event < 32);
++
++#if gcdMULTI_GPU
++ if (FromWhere == gcvKERNEL_COMMAND) FromWhere = gcvKERNEL_PIXEL;
++#endif
++
++ /* Determine the size of the command. */
++
++ size = (Hardware->extraEventStates && (FromWhere == gcvKERNEL_PIXEL))
++ ? gcmALIGN(8 + (1 + 5) * 4, 8) /* EVENT + 5 STATES */
++ : 8;
++
++ if (Logical != gcvNULL)
++ {
++ if (*Bytes < size)
++ {
++ /* Command queue too small. */
++ gcmkONERROR(gcvSTATUS_BUFFER_TOO_SMALL);
++ }
++
++ switch (FromWhere)
++ {
++ case gcvKERNEL_COMMAND:
++ /* From command processor. */
++ destination = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5)));
++ break;
++
++ case gcvKERNEL_PIXEL:
++ /* From pixel engine. */
++ destination = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6)));
++ break;
++
++ default:
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ /* Append EVENT(Event, destiantion). */
++ logical[0] = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E01) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ logical[1] = ((((gctUINT32) (destination)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) ((gctUINT32) (Event) & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)));
++
++ /* Make sure the event ID gets written out before GPU can access it. */
++ gcmkONERROR(
++ gckOS_MemoryBarrier(Hardware->os, logical + 1));
++
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++ {
++ gctUINT32 phys;
++ gckOS_GetPhysicalAddress(Hardware->os, Logical, &phys);
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "0x%08x: EVENT %d", phys, Event);
++ }
++#endif
++
++ /* Append the extra states. These are needed for the chips that do not
++ ** support back-to-back events due to the async interface. The extra
++ ** states add the necessary delay to ensure that event IDs do not
++ ** collide. */
++ if (size > 8)
++ {
++ logical[2] = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0100) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (5) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++ logical[3] = 0;
++ logical[4] = 0;
++ logical[5] = 0;
++ logical[6] = 0;
++ logical[7] = 0;
++ }
++
++#if gcdINTERRUPT_STATISTIC
++ if (Event < gcmCOUNTOF(Hardware->kernel->eventObj->queues))
++ {
++ gckOS_AtomSetMask(Hardware->pendingEvent, 1 << Event);
++ }
++#endif
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the EVENT command. */
++ *Bytes = size;
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Bytes=%lu", gcmOPT_VALUE(Bytes));
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_PipeSelect
++**
++** Append a PIPESELECT command at the specified location in the command queue.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to an gckHARDWARE object.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command queue to append
++** the PIPESELECT command at or gcvNULL just to query the size of the
++** PIPESELECT command.
++**
++** gcePIPE_SELECT Pipe
++** Pipe value to select.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the PIPESELECT command.
++** If 'Logical' is gcvNULL, this argument will be ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** for the PIPESELECT command. If 'Bytes' is gcvNULL, nothing will be
++** returned.
++*/
++gceSTATUS
++gckHARDWARE_PipeSelect(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN gcePIPE_SELECT Pipe,
++ IN OUT gctUINT32 * Bytes
++ )
++{
++ gctUINT32_PTR logical = (gctUINT32_PTR) Logical;
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x Pipe=%d *Bytes=%lu",
++ Hardware, Logical, Pipe, gcmOPT_VALUE(Bytes));
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT((Logical == gcvNULL) || (Bytes != gcvNULL));
++
++ /* Append a PipeSelect. */
++ if (Logical != gcvNULL)
++ {
++ gctUINT32 flush, stall;
++
++ if (*Bytes < 32)
++ {
++ /* Command queue too small. */
++ gcmkONERROR(gcvSTATUS_BUFFER_TOO_SMALL);
++ }
++
++ flush = (Pipe == gcvPIPE_2D)
++ ? ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)))
++ : ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3)));
++
++ stall = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /* LoadState(AQFlush, 1), flush. */
++ logical[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E03) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ logical[1]
++ = flush;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "0x%x: FLUSH 0x%x", logical, flush);
++
++ /* LoadState(AQSempahore, 1), stall. */
++ logical[2]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ logical[3]
++ = stall;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "0x%x: SEMAPHORE 0x%x", logical + 2, stall);
++
++ /* Stall, stall. */
++ logical[4] = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++ logical[5] = stall;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "0x%x: STALL 0x%x", logical + 4, stall);
++
++ /* LoadState(AQPipeSelect, 1), pipe. */
++ logical[6]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E00) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ logical[7] = (Pipe == gcvPIPE_2D)
++ ? 0x1
++ : 0x0;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "0x%x: PIPE %d", logical + 6, Pipe);
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the PIPESELECT command. */
++ *Bytes = 32;
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Bytes=%lu", gcmOPT_VALUE(Bytes));
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_Link
++**
++** Append a LINK command at the specified location in the command queue.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to an gckHARDWARE object.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command queue to append
++** the LINK command at or gcvNULL just to query the size of the LINK
++** command.
++**
++** gctUINT32 FetchAddress
++** Hardware address of destination of LINK.
++**
++** gctSIZE_T FetchSize
++** Number of bytes in destination of LINK.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the LINK command. If
++** 'Logical' is gcvNULL, this argument will be ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** for the LINK command. If 'Bytes' is gcvNULL, nothing will be returned.
++*/
++gceSTATUS
++gckHARDWARE_Link(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN gctUINT32 FetchAddress,
++ IN gctUINT32 FetchSize,
++ IN OUT gctUINT32 * Bytes
++ )
++{
++ gceSTATUS status;
++ gctSIZE_T bytes;
++ gctUINT32 link;
++ gctUINT32_PTR logical = (gctUINT32_PTR) Logical;
++
++ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x FetchAddress=0x%x FetchSize=%lu "
++ "*Bytes=%lu",
++ Hardware, Logical, FetchAddress, FetchSize,
++ gcmOPT_VALUE(Bytes));
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT((Logical == gcvNULL) || (Bytes != gcvNULL));
++
++ if (Logical != gcvNULL)
++ {
++ if (*Bytes < 8)
++ {
++ /* Command queue too small. */
++ gcmkONERROR(gcvSTATUS_BUFFER_TOO_SMALL);
++ }
++
++ gcmkONERROR(
++ gckOS_WriteMemory(Hardware->os, logical + 1, FetchAddress));
++
++ /* Make sure the address got written before the LINK command. */
++ gcmkONERROR(
++ gckOS_MemoryBarrier(Hardware->os, logical + 1));
++
++ /* Compute number of 64-byte aligned bytes to fetch. */
++ bytes = gcmALIGN(FetchAddress + FetchSize, 64) - FetchAddress;
++
++ /* Append LINK(bytes / 8), FetchAddress. */
++ link = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x08 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (bytes >> 3) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ gcmkONERROR(
++ gckOS_WriteMemory(Hardware->os, logical, link));
++
++ /* Memory barrier. */
++ gcmkONERROR(
++ gckOS_MemoryBarrier(Hardware->os, logical));
++
++#if gcdLINK_QUEUE_SIZE && !gcdPROCESS_ADDRESS_SPACE
++ if ((Hardware->kernel->virtualCommandBuffer)
++ && (Hardware->kernel->stuckDump > 2)
++ )
++ {
++ gctBOOL in;
++
++ gcmkVERIFY_OK(gckCOMMAND_AddressInKernelCommandBuffer(
++ Hardware->kernel->command, FetchAddress, &in));
++
++ if (in == gcvFALSE)
++ {
++ /* Record user command buffer and context buffer link
++ ** information for stuck dump.
++ **/
++ gckLINKQUEUE_Enqueue(
++ &Hardware->linkQueue, FetchAddress, FetchAddress + (gctUINT)bytes);
++ }
++ }
++#endif
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the LINK command. */
++ *Bytes = 8;
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Bytes=%lu", gcmOPT_VALUE(Bytes));
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_UpdateQueueTail
++**
++** Update the tail of the command queue.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to an gckHARDWARE object.
++**
++** gctPOINTER Logical
++** Logical address of the start of the command queue.
++**
++** gctUINT32 Offset
++** Offset into the command queue of the tail (last command).
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckHARDWARE_UpdateQueueTail(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Offset
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x Offset=0x%08x",
++ Hardware, Logical, Offset);
++
++ /* Verify the hardware. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Force a barrier. */
++ gcmkONERROR(
++ gckOS_MemoryBarrier(Hardware->os, Logical));
++
++ /* Notify gckKERNEL object of change. */
++#if gcdMULTI_GPU
++ gcmkONERROR(
++ gckKERNEL_Notify(Hardware->kernel,
++ 0,
++ gcvNOTIFY_COMMAND_QUEUE,
++ gcvFALSE));
++#else
++ gcmkONERROR(
++ gckKERNEL_Notify(Hardware->kernel,
++ gcvNOTIFY_COMMAND_QUEUE,
++ gcvFALSE));
++#endif
++
++ if (status == gcvSTATUS_CHIP_NOT_READY)
++ {
++ gcmkONERROR(gcvSTATUS_DEVICE);
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_ConvertLogical
++**
++** Convert a logical system address into a hardware specific address.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to an gckHARDWARE object.
++**
++** gctPOINTER Logical
++** Logical address to convert.
++**
++** gctBOOL InUserSpace
++** gcvTRUE if the memory in user space.
++**
++** gctUINT32* Address
++** Return hardware specific address.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckHARDWARE_ConvertLogical(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN gctBOOL InUserSpace,
++ OUT gctUINT32 * Address
++ )
++{
++ gctUINT32 address;
++ gceSTATUS status;
++ gctUINT32 baseAddress;
++
++ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x InUserSpace=%d",
++ Hardware, Logical, InUserSpace);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Address != gcvNULL);
++
++ /* Convert logical address into a physical address. */
++ if (InUserSpace)
++ {
++ gcmkONERROR(gckOS_UserLogicalToPhysical(Hardware->os, Logical, &address));
++ }
++ else
++ {
++ gcmkONERROR(gckOS_GetPhysicalAddress(Hardware->os, Logical, &address));
++ }
++
++ /* For old MMU, get GPU address according to baseAddress. */
++ if (Hardware->mmuVersion == 0)
++ {
++ gcmkONERROR(gckOS_GetBaseAddress(Hardware->os, &baseAddress));
++
++ /* Subtract base address to get a GPU address. */
++ gcmkASSERT(address >= baseAddress);
++ address -= baseAddress;
++ }
++
++ /* Return hardware specific address. */
++ *Address = (Hardware->mmuVersion == 0)
++ ? ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:31) - (0 ? 31:31) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:31) - (0 ? 31:31) + 1))))))) << (0 ? 31:31))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 31:31) - (0 ? 31:31) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:31) - (0 ? 31:31) + 1))))))) << (0 ? 31:31)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 30:0) - (0 ? 30:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 30:0) - (0 ? 30:0) + 1))))))) << (0 ? 30:0))) | (((gctUINT32) ((gctUINT32) (address) & ((gctUINT32) ((((1 ? 30:0) - (0 ? 30:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 30:0) - (0 ? 30:0) + 1))))))) << (0 ? 30:0)))
++ : address;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Address=0x%08x", *Address);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_Interrupt
++**
++** Process an interrupt.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to an gckHARDWARE object.
++**
++** gctBOOL InterruptValid
++** If gcvTRUE, this function will read the interrupt acknowledge
++** register, stores the data, and return whether or not the interrupt
++** is ours or not. If gcvFALSE, this functions will read the interrupt
++** acknowledge register and combine it with any stored value to handle
++** the event notifications.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckHARDWARE_Interrupt(
++ IN gckHARDWARE Hardware,
++#if gcdMULTI_GPU
++ IN gctUINT CoreId,
++#endif
++ IN gctBOOL InterruptValid
++ )
++{
++ gckEVENT eventObj;
++ gctUINT32 data = 0;
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Hardware=0x%x InterruptValid=%d", Hardware, InterruptValid);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Extract gckEVENT object. */
++ eventObj = Hardware->kernel->eventObj;
++ gcmkVERIFY_OBJECT(eventObj, gcvOBJ_EVENT);
++
++ if (InterruptValid)
++ {
++ /* Read AQIntrAcknowledge register. */
++#if gcdMULTI_GPU
++ if (Hardware->core == gcvCORE_MAJOR)
++ {
++ gcmkONERROR(
++ gckOS_ReadRegisterByCoreId(Hardware->os,
++ Hardware->core,
++ CoreId,
++ 0x00010,
++ &data));
++ }
++ else
++ {
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00010,
++ &data));
++ }
++#else
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00010,
++ &data));
++#endif
++
++ if (data == 0)
++ {
++ /* Not our interrupt. */
++ status = gcvSTATUS_NOT_OUR_INTERRUPT;
++ }
++ else
++ {
++
++#if gcdINTERRUPT_STATISTIC
++ gckOS_AtomClearMask(Hardware->pendingEvent, data);
++#endif
++
++ /* Inform gckEVENT of the interrupt. */
++ status = gckEVENT_Interrupt(eventObj,
++#if gcdMULTI_GPU
++ CoreId,
++#endif
++ data);
++ }
++ }
++ else
++ {
++ /* Handle events. */
++ status = gckEVENT_Notify(eventObj, 0);
++ }
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_QueryCommandBuffer
++**
++** Query the command buffer alignment and number of reserved bytes.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Alignment
++** Pointer to a variable receiving the alignment for each command.
++**
++** gctSIZE_T * ReservedHead
++** Pointer to a variable receiving the number of reserved bytes at the
++** head of each command buffer.
++**
++** gctSIZE_T * ReservedTail
++** Pointer to a variable receiving the number of bytes reserved at the
++** tail of each command buffer.
++*/
++gceSTATUS
++gckHARDWARE_QueryCommandBuffer(
++ IN gckHARDWARE Hardware,
++ OUT gctUINT32 * Alignment,
++ OUT gctUINT32 * ReservedHead,
++ OUT gctUINT32 * ReservedTail
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ if (Alignment != gcvNULL)
++ {
++ /* Align every 8 bytes. */
++ *Alignment = 8;
++ }
++
++ if (ReservedHead != gcvNULL)
++ {
++ /* Reserve space for SelectPipe(). */
++ *ReservedHead = 32;
++ }
++
++ if (ReservedTail != gcvNULL)
++ {
++ /* Reserve space for Link(). */
++ *ReservedTail = 8;
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Alignment=%lu *ReservedHead=%lu *ReservedTail=%lu",
++ gcmOPT_VALUE(Alignment), gcmOPT_VALUE(ReservedHead),
++ gcmOPT_VALUE(ReservedTail));
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_QuerySystemMemory
++**
++** Query the command buffer alignment and number of reserved bytes.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** OUTPUT:
++**
++** gctSIZE_T * SystemSize
++** Pointer to a variable that receives the maximum size of the system
++** memory.
++**
++** gctUINT32 * SystemBaseAddress
++** Poinetr to a variable that receives the base address for system
++** memory.
++*/
++gceSTATUS
++gckHARDWARE_QuerySystemMemory(
++ IN gckHARDWARE Hardware,
++ OUT gctSIZE_T * SystemSize,
++ OUT gctUINT32 * SystemBaseAddress
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ if (SystemSize != gcvNULL)
++ {
++ /* Maximum system memory can be 2GB. */
++ *SystemSize = 1U << 31;
++ }
++
++ if (SystemBaseAddress != gcvNULL)
++ {
++ /* Set system memory base address. */
++ *SystemBaseAddress = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:31) - (0 ? 31:31) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:31) - (0 ? 31:31) + 1))))))) << (0 ? 31:31))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 31:31) - (0 ? 31:31) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:31) - (0 ? 31:31) + 1))))))) << (0 ? 31:31)));
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*SystemSize=%lu *SystemBaseAddress=%lu",
++ gcmOPT_VALUE(SystemSize), gcmOPT_VALUE(SystemBaseAddress));
++ return gcvSTATUS_OK;
++}
++
++#if gcdENABLE_3D
++/*******************************************************************************
++**
++** gckHARDWARE_QueryShaderCaps
++**
++** Query the shader capabilities.
++**
++** INPUT:
++**
++** Nothing.
++**
++** OUTPUT:
++**
++** gctUINT * VertexUniforms
++** Pointer to a variable receiving the number of uniforms in the vertex
++** shader.
++**
++** gctUINT * FragmentUniforms
++** Pointer to a variable receiving the number of uniforms in the
++** fragment shader.
++**
++** gctBOOL * UnifiedUnforms
++** Pointer to a variable receiving whether the uniformas are unified.
++*/
++gceSTATUS
++gckHARDWARE_QueryShaderCaps(
++ IN gckHARDWARE Hardware,
++ OUT gctUINT * VertexUniforms,
++ OUT gctUINT * FragmentUniforms,
++ OUT gctBOOL * UnifiedUnforms
++ )
++{
++ gctBOOL unifiedConst;
++ gctUINT32 vsConstMax;
++ gctUINT32 psConstMax;
++ gctUINT32 vsConstBase;
++ gctUINT32 psConstBase;
++ gctUINT32 ConstMax;
++
++ gcmkHEADER_ARG("Hardware=0x%x VertexUniforms=0x%x "
++ "FragmentUniforms=0x%x UnifiedUnforms=0x%x",
++ Hardware, VertexUniforms,
++ FragmentUniforms, UnifiedUnforms);
++
++ {if (Hardware->identity.numConstants > 256){ unifiedConst = gcvTRUE; vsConstBase = 0xC000; psConstBase = 0xC000; ConstMax = Hardware->identity.numConstants; vsConstMax = 256; psConstMax = ConstMax - vsConstMax;}else if (Hardware->identity.numConstants == 256){ if (Hardware->identity.chipModel == gcv2000 && Hardware->identity.chipRevision == 0x5118) { unifiedConst = gcvFALSE; vsConstBase = 0x1400; psConstBase = 0x1C00; vsConstMax = 256; psConstMax = 64; ConstMax = 320; } else { unifiedConst = gcvFALSE; vsConstBase = 0x1400; psConstBase = 0x1C00; vsConstMax = 256; psConstMax = 256; ConstMax = 512; }}else{ unifiedConst = gcvFALSE; vsConstBase = 0x1400; psConstBase = 0x1C00; vsConstMax = 168; psConstMax = 64; ConstMax = 232;}};
++
++ if (VertexUniforms != gcvNULL)
++ {
++ /* Return the vs shader const count. */
++ *VertexUniforms = vsConstMax;
++ }
++
++ if (FragmentUniforms != gcvNULL)
++ {
++ /* Return the ps shader const count. */
++ *FragmentUniforms = psConstMax;
++ }
++
++ if (UnifiedUnforms != gcvNULL)
++ {
++ /* Return whether the uniformas are unified. */
++ *UnifiedUnforms = unifiedConst;
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++#endif
++
++/*******************************************************************************
++**
++** gckHARDWARE_SetMMU
++**
++** Set the page table base address.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** gctPOINTER Logical
++** Logical address of the page table.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckHARDWARE_SetMMU(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical
++ )
++{
++ gceSTATUS status;
++ gctUINT32 address = 0;
++ gctUINT32 idle;
++ gctUINT32 timer = 0, delay = 1;
++
++ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x", Hardware, Logical);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ if (Hardware->mmuVersion == 0)
++ {
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++
++ /* Convert the logical address into physical address. */
++ gcmkONERROR(gckOS_GetPhysicalAddress(Hardware->os, Logical, &address));
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Setting page table to 0x%08X",
++ address);
++
++ /* Write the AQMemoryFePageTable register. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00400,
++ address));
++
++ /* Write the AQMemoryRaPageTable register. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00410,
++ address));
++
++ /* Write the AQMemoryTxPageTable register. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00404,
++ address));
++
++
++ /* Write the AQMemoryPePageTable register. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00408,
++ address));
++
++ /* Write the AQMemoryPezPageTable register. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0040C,
++ address));
++ }
++ else if (Hardware->enableMMU == gcvTRUE)
++ {
++ /* Execute prepared command sequence. */
++ gcmkONERROR(gckHARDWARE_Execute(
++ Hardware,
++ Hardware->functions[gcvHARDWARE_FUNCTION_MMU].address,
++ Hardware->functions[gcvHARDWARE_FUNCTION_MMU].bytes
++ ));
++
++ /* Wait until MMU configure finishes. */
++ do
++ {
++ gckOS_Delay(Hardware->os, delay);
++
++ gcmkONERROR(gckOS_ReadRegisterEx(
++ Hardware->os,
++ Hardware->core,
++ 0x00004,
++ &idle));
++
++ timer += delay;
++ delay *= 2;
++
++#if gcdGPU_TIMEOUT
++ if (timer >= Hardware->kernel->timeOut)
++ {
++ /* Even if hardware is not reset correctly, let software
++ ** continue to avoid software stuck. Software will timeout again
++ ** and try to recover GPU in next timeout.
++ */
++ gcmkONERROR(gcvSTATUS_DEVICE);
++ }
++#endif
++ }
++ while (!(((((gctUINT32) (idle)) >> (0 ? 0:0)) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1)))))) ));
++
++ /* Enable MMU. */
++ gcmkONERROR(gckOS_WriteRegisterEx(
++ Hardware->os,
++ Hardware->core,
++ 0x0018C,
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (gcvTRUE) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)))
++ ));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_FlushMMU
++**
++** Flush the page table.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckHARDWARE_FlushMMU(
++ IN gckHARDWARE Hardware
++ )
++{
++ gceSTATUS status;
++ gckCOMMAND command;
++ gctUINT32_PTR buffer;
++ gctUINT32 bufferSize;
++ gctPOINTER pointer = gcvNULL;
++ gctUINT32 flushSize;
++ gctUINT32 count;
++ gctUINT32 physical;
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Verify the gckCOMMAND object pointer. */
++ command = Hardware->kernel->command;
++
++ /* Flush the memory controller. */
++ if (Hardware->mmuVersion == 0)
++ {
++ gcmkONERROR(gckCOMMAND_Reserve(
++ command, 8, &pointer, &bufferSize
++ ));
++
++ buffer = (gctUINT32_PTR) pointer;
++
++ buffer[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E04) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ buffer[1]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4)));
++
++ gcmkONERROR(gckCOMMAND_Execute(command, 8));
++ }
++ else
++ {
++ flushSize = 16 * 4;
++
++ gcmkONERROR(gckCOMMAND_Reserve(
++ command, flushSize, &pointer, &bufferSize
++ ));
++
++ buffer = (gctUINT32_PTR) pointer;
++
++ count = ((gctUINT)bufferSize - flushSize + 7) >> 3;
++
++ gcmkONERROR(gckOS_GetPhysicalAddress(command->os, buffer, &physical));
++
++ /* Flush cache. */
++ buffer[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E03) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ buffer[1]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6)));
++
++ /* Arm the PE-FE Semaphore. */
++ buffer[2]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ buffer[3]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /* STALL FE until PE is done flushing. */
++ buffer[4]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++
++ buffer[5]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /* LINK to next slot to flush FE FIFO. */
++ buffer[6]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x08 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (4) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ buffer[7]
++ = physical + 8 * gcmSIZEOF(gctUINT32);
++
++ /* Flush MMU cache. */
++ buffer[8]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0061) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ buffer[9]
++ = (((((gctUINT32) (~0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) & ((((gctUINT32) (~0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1))))))) << (0 ? 7:7))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1))))))) << (0 ? 7:7))));
++
++ /* Arm the PE-FE Semaphore. */
++ buffer[10]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ buffer[11]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /* STALL FE until PE is done flushing. */
++ buffer[12]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++
++ buffer[13]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /* LINK to next slot to flush FE FIFO. */
++ buffer[14]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x08 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (count) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ buffer[15]
++ = physical + flushSize;
++
++ gcmkONERROR(gckCOMMAND_Execute(command, flushSize));
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckHARDWARE_SetMMUStates(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER MtlbAddress,
++ IN gceMMU_MODE Mode,
++ IN gctPOINTER SafeAddress,
++ IN gctPOINTER Logical,
++ IN OUT gctUINT32 * Bytes
++ )
++{
++ gceSTATUS status;
++ gctUINT32 config, address;
++ gctUINT32_PTR buffer;
++ gctBOOL ace;
++ gctUINT32 reserveBytes = 16 + 4 * 4;
++
++ gctBOOL config2D;
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(Hardware->mmuVersion != 0);
++
++ ace = gckHARDWARE_IsFeatureAvailable(Hardware, gcvFEATURE_ACE);
++
++ if (ace)
++ {
++ reserveBytes += 8;
++ }
++
++ config2D = gckHARDWARE_IsFeatureAvailable(Hardware, gcvFEATURE_PIPE_3D)
++ && gckHARDWARE_IsFeatureAvailable(Hardware, gcvFEATURE_PIPE_2D);
++
++ if (config2D)
++ {
++ reserveBytes +=
++ /* Pipe Select. */
++ 4 * 4
++ /* Configure MMU States. */
++ + 4 * 4
++ /* Semaphore stall */
++ + 4 * 8;
++ }
++
++ /* Convert logical address into physical address. */
++ gcmkONERROR(
++ gckOS_GetPhysicalAddress(Hardware->os, MtlbAddress, &config));
++
++ gcmkONERROR(
++ gckOS_GetPhysicalAddress(Hardware->os, SafeAddress, &address));
++
++ if (address & 0x3F)
++ {
++ gcmkONERROR(gcvSTATUS_NOT_ALIGNED);
++ }
++
++ switch (Mode)
++ {
++ case gcvMMU_MODE_1K:
++ if (config & 0x3FF)
++ {
++ gcmkONERROR(gcvSTATUS_NOT_ALIGNED);
++ }
++
++ config |= ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)));
++
++ break;
++
++ case gcvMMU_MODE_4K:
++ if (config & 0xFFF)
++ {
++ gcmkONERROR(gcvSTATUS_NOT_ALIGNED);
++ }
++
++ config |= ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)));
++
++ break;
++
++ default:
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ if (Logical != gcvNULL)
++ {
++ buffer = Logical;
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0061) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ *buffer++ = config;
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0060) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ *buffer++ = address;
++
++ if (ace)
++ {
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0068) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ *buffer++ = 0;
++ }
++
++ do{*buffer++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))); *buffer++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))); *buffer++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))); *buffer++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));} while(0);;
++
++ if (config2D)
++ {
++ /* LoadState(AQPipeSelect, 1), pipe. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E00) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ *buffer++ = 0x1;
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0061) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ *buffer++ = config;
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0060) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ *buffer++ = address;
++
++ do{*buffer++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))); *buffer++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))); *buffer++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))); *buffer++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));} while(0);;
++
++ /* LoadState(AQPipeSelect, 1), pipe. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E00) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ *buffer++ = 0x0;
++
++ do{*buffer++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))); *buffer++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))); *buffer++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))); *buffer++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));} while(0);;
++ }
++
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ *Bytes = reserveBytes;
++ }
++
++ /* Return the status. */
++ gcmkFOOTER_NO();
++ return status;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++#if gcdPROCESS_ADDRESS_SPACE
++/*******************************************************************************
++**
++** gckHARDWARE_ConfigMMU
++**
++** Append a MMU Configuration command sequence at the specified location in the command
++** queue. That command sequence consists of mmu configuration, LINK and WAIT/LINK.
++** LINK is fetched and paresed with new mmu configuration.
++**
++** If MMU Configuration is not changed between commit, change last WAIT/LINK to
++** link to ENTRY.
++**
++** -+-----------+-----------+-----------------------------------------
++** | WAIT/LINK | WAIT/LINK |
++** -+-----------+-----------+-----------------------------------------
++** | /|\
++** \|/ |
++** +--------------------+
++** | ENTRY | ... | LINK |
++** +--------------------+
++**
++** If MMU Configuration is changed between commit, change last WAIT/LINK to
++** link to MMU CONFIGURATION command sequence, and there are an EVNET and
++** an END at the end of this command sequence, when interrupt handler
++** receives this event, it will start FE at ENTRY to continue the command
++** buffer execution.
++**
++** -+-----------+-------------------+---------+---------+-----------+--
++** | WAIT/LINK | MMU CONFIGURATION | EVENT | END | WAIT/LINK |
++** -+-----------+-------------------+---------+---------+-----------+--
++** | /|\ /|\
++** +-------------+ |
++** +--------------------+
++** | ENTRY | ... | LINK |
++** +--------------------+
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to an gckHARDWARE object.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command queue to append
++** command sequence at or gcvNULL just to query the size of the
++** command sequence.
++**
++** gctPOINTER MtlbLogical
++** Pointer to the current Master TLB.
++**
++** gctUINT32 Offset
++** Offset into command buffer required for alignment.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the command
++** sequence. If 'Logical' is gcvNULL, this argument will be ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** by the command sequence. If 'Bytes' is gcvNULL, nothing will
++** be returned.
++**
++** gctUINT32 * WaitLinkOffset
++** Pointer to a variable that will receive the offset of the WAIT/LINK command
++** from the specified logcial pointer.
++** If 'WaitLinkOffset' is gcvNULL nothing will be returned.
++**
++** gctSIZE_T * WaitLinkBytes
++** Pointer to a variable that will receive the number of bytes used by
++** the WAIT command.
++** If 'WaitLinkBytes' is gcvNULL nothing will be returned.
++*/
++gceSTATUS
++gckHARDWARE_ConfigMMU(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN gctPOINTER MtlbLogical,
++ IN gctUINT32 Offset,
++ IN OUT gctSIZE_T * Bytes,
++ OUT gctSIZE_T * WaitLinkOffset,
++ OUT gctSIZE_T * WaitLinkBytes
++ )
++{
++ gceSTATUS status;
++ gctSIZE_T bytes, bytesAligned;
++ gctUINT32 config;
++ gctUINT32_PTR buffer = (gctUINT32_PTR) Logical;
++ gctUINT32 physical;
++ gctUINT32 event;
++
++ gcmkHEADER_ARG("Hardware=0x%08X Logical=0x%08x MtlbLogical=0x%08X",
++ Hardware, Logical, MtlbLogical);
++
++ bytes
++ /* Flush cache states. */
++ = 18 * 4
++ /* MMU configuration states. */
++ + 6 * 4
++ /* EVENT. */
++ + 2 * 4
++ /* END. */
++ + 2 * 4
++ /* WAIT/LINK. */
++ + 4 * 4;
++
++ /* Compute number of bytes required. */
++ bytesAligned = gcmALIGN(Offset + bytes, 8) - Offset;
++
++ if (buffer != gcvNULL)
++ {
++ if (MtlbLogical == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ /* Get physical address of this command buffer segment. */
++ gcmkONERROR(gckOS_GetPhysicalAddress(Hardware->os, buffer, &physical));
++
++ /* Get physical address of Master TLB. */
++ gcmkONERROR(gckOS_GetPhysicalAddress(Hardware->os, MtlbLogical, &config));
++
++ config |= ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4)));
++
++ /* Flush cache. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E03) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6)));
++
++ /* Flush tile status cache. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0594) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)));
++
++ /* Arm the PE-FE Semaphore. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /* STALL FE until PE is done flushing. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /* LINK to next slot to flush FE FIFO. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x08 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (4) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ *buffer++
++ = physical + 10 * gcmSIZEOF(gctUINT32);
++
++ /* Configure MMU. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0061) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ *buffer++
++ = (((((gctUINT32) (~0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) & ((((gctUINT32) (~0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1))))))) << (0 ? 7:7))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1))))))) << (0 ? 7:7))));
++
++ /* Arm the PE-FE Semaphore. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /* STALL FE until PE is done flushing. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /* LINK to next slot to flush FE FIFO. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x08 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (5) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ *buffer++
++ = physical + 18 * 4;
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0061) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ *buffer++
++ = config;
++
++ /* Arm the PE-FE Semaphore. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /* STALL FE until PE is done flushing. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /* Event 29. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E01) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ event = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6)));
++ event = ((((gctUINT32) (event)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) ((gctUINT32) (29) & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)));
++
++ *buffer++
++ = event;
++
++ /* Append END. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x02 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ *Bytes = bytesAligned;
++ }
++
++ if (WaitLinkOffset != gcvNULL)
++ {
++ *WaitLinkOffset = bytes - 4 * 4;
++ }
++
++ if (WaitLinkBytes != gcvNULL)
++ {
++#if gcdMULTI_GPU
++ *WaitLinkBytes = 40;
++#else
++ *WaitLinkBytes = 4 * 4;
++#endif
++ }
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++#endif
++
++/*******************************************************************************
++**
++** gckHARDWARE_BuildVirtualAddress
++**
++** Build a virtual address.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** gctUINT32 Index
++** Index into page table.
++**
++** gctUINT32 Offset
++** Offset into page.
++**
++** OUTPUT:
++**
++** gctUINT32 * Address
++** Pointer to a variable receiving te hardware address.
++*/
++gceSTATUS
++gckHARDWARE_BuildVirtualAddress(
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 Index,
++ IN gctUINT32 Offset,
++ OUT gctUINT32 * Address
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x Index=%u Offset=%u", Hardware, Index, Offset);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(Address != gcvNULL);
++
++ /* Build virtual address. */
++ *Address = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:31) - (0 ? 31:31) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:31) - (0 ? 31:31) + 1))))))) << (0 ? 31:31))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 31:31) - (0 ? 31:31) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:31) - (0 ? 31:31) + 1))))))) << (0 ? 31:31)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 30:0) - (0 ? 30:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 30:0) - (0 ? 30:0) + 1))))))) << (0 ? 30:0))) | (((gctUINT32) ((gctUINT32) (Offset | (Index << 12)) & ((gctUINT32) ((((1 ? 30:0) - (0 ? 30:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 30:0) - (0 ? 30:0) + 1))))))) << (0 ? 30:0)));
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Address=0x%08x", *Address);
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckHARDWARE_GetIdle(
++ IN gckHARDWARE Hardware,
++ IN gctBOOL Wait,
++ OUT gctUINT32 * Data
++ )
++{
++ gceSTATUS status;
++ gctUINT32 idle = 0;
++ gctINT retry, poll, pollCount;
++ gctUINT32 address;
++
++ gcmkHEADER_ARG("Hardware=0x%x Wait=%d", Hardware, Wait);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(Data != gcvNULL);
++
++
++ /* If we have to wait, try 100 polls per millisecond. */
++ pollCount = Wait ? 100 : 1;
++
++ /* At most, try for 1 second. */
++ for (retry = 0; retry < 1000; ++retry)
++ {
++ /* If we have to wait, try 100 polls per millisecond. */
++ for (poll = pollCount; poll > 0; --poll)
++ {
++ /* Read register. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00004, &idle));
++
++ /* Read the current FE address. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00664,
++ &address));
++
++
++ /* See if we have to wait for FE idle. */
++ if (_IsGPUIdle(idle)
++ && (address == Hardware->lastEnd + 8)
++ )
++ {
++ /* FE is idle. */
++ break;
++ }
++ }
++
++ /* Check if we need to wait for FE and FE is busy. */
++ if (Wait && !_IsGPUIdle(idle))
++ {
++ /* Wait a little. */
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "%s: Waiting for idle: 0x%08X",
++ __FUNCTION__, idle);
++
++ gcmkVERIFY_OK(gckOS_Delay(Hardware->os, 1));
++ }
++ else
++ {
++ break;
++ }
++ }
++
++ /* Return idle to caller. */
++ *Data = idle;
++
++#if defined(EMULATOR)
++ /* Wait a little while until CModel FE gets END.
++ * END is supposed to be appended by caller.
++ */
++ gckOS_Delay(gcvNULL, 100);
++#endif
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Data=0x%08x", *Data);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/* Flush the caches. */
++gceSTATUS
++gckHARDWARE_Flush(
++ IN gckHARDWARE Hardware,
++ IN gceKERNEL_FLUSH Flush,
++ IN gctPOINTER Logical,
++ IN OUT gctUINT32 * Bytes
++ )
++{
++ gctUINT32 pipe;
++ gctUINT32 flush = 0;
++ gctBOOL flushTileStatus;
++ gctUINT32_PTR logical = (gctUINT32_PTR) Logical;
++ gceSTATUS status;
++ gctUINT32 reserveBytes
++ /* Semaphore/Stall */
++ = 4 * gcmSIZEOF(gctUINT32);
++
++ gcmkHEADER_ARG("Hardware=0x%x Flush=0x%x Logical=0x%x *Bytes=%lu",
++ Hardware, Flush, Logical, gcmOPT_VALUE(Bytes));
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Get current pipe. */
++ pipe = Hardware->kernel->command->pipeSelect;
++
++ /* Flush tile status cache. */
++ flushTileStatus = Flush & gcvFLUSH_TILE_STATUS;
++
++ /* Flush 3D color cache. */
++ if ((Flush & gcvFLUSH_COLOR) && (pipe == 0x0))
++ {
++ flush |= ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1)));
++ }
++
++ /* Flush 3D depth cache. */
++ if ((Flush & gcvFLUSH_DEPTH) && (pipe == 0x0))
++ {
++ flush |= ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)));
++ }
++
++ /* Flush 3D texture cache. */
++ if ((Flush & gcvFLUSH_TEXTURE) && (pipe == 0x0))
++ {
++ flush |= ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2)));
++ }
++
++ /* Flush 2D cache. */
++ if ((Flush & gcvFLUSH_2D) && (pipe == 0x1))
++ {
++ flush |= ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3)));
++ }
++
++#if gcdMULTI_GPU
++ /* Flush L2 cache. */
++ if ((Flush & gcvFLUSH_L2) && (pipe == 0x0))
++ {
++ flush |= ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6)));
++ }
++#endif
++
++ /* Determine reserve bytes. */
++ if (flush)
++ {
++ reserveBytes += 2 * gcmSIZEOF(gctUINT32);
++ }
++
++ if (flushTileStatus)
++ {
++ reserveBytes += 2 * gcmSIZEOF(gctUINT32);
++ }
++
++ /* See if there is a valid flush. */
++ if ((flush == 0) && (flushTileStatus == gcvFALSE))
++ {
++ if (Bytes != gcvNULL)
++ {
++ /* No bytes required. */
++ *Bytes = 0;
++ }
++ }
++
++ else
++ {
++ /* Copy to command queue. */
++ if (Logical != gcvNULL)
++ {
++ if (*Bytes < reserveBytes)
++ {
++ /* Command queue too small. */
++ gcmkONERROR(gcvSTATUS_BUFFER_TOO_SMALL);
++ }
++
++ if (flush)
++ {
++ /* Append LOAD_STATE to AQFlush. */
++ *logical++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E03) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ *logical++
++ = flush;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "0x%x: FLUSH 0x%x", logical - 1, flush);
++ }
++
++ if (flushTileStatus)
++ {
++ *logical++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0594) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ *logical++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)));
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "0x%x: FLUSH TILE STATUS 0x%x", logical - 1, logical[-1]);
++ }
++
++ /* Semaphore. */
++ *logical++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ *logical++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /* Stall. */
++ *logical++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++
++ *logical++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x05 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* bytes required. */
++ *Bytes = reserveBytes;
++ }
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Bytes=%lu", gcmOPT_VALUE(Bytes));
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckHARDWARE_SetFastClear(
++ IN gckHARDWARE Hardware,
++ IN gctINT Enable,
++ IN gctINT Compression
++ )
++{
++#if gcdENABLE_3D
++ gctUINT32 debug;
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Hardware=0x%x Enable=%d Compression=%d",
++ Hardware, Enable, Compression);
++
++ /* Only process if fast clear is available. */
++ if ((((((gctUINT32) (Hardware->identity.chipFeatures)) >> (0 ? 0:0)) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1)))))) ))
++ {
++ if (Enable == -1)
++ {
++ /* Determine automatic value for fast clear. */
++ Enable = ((Hardware->identity.chipModel != gcv500)
++ || (Hardware->identity.chipRevision >= 3)
++ ) ? 1 : 0;
++ }
++
++ if (Compression == -1)
++ {
++ /* Determine automatic value for compression. */
++ Compression = Enable
++ & (((((gctUINT32) (Hardware->identity.chipFeatures)) >> (0 ? 5:5)) & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1)))))) );
++ }
++
++ /* Read AQMemoryDebug register. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00414, &debug));
++
++ /* Set fast clear bypass. */
++ debug = ((((gctUINT32) (debug)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 20:20) - (0 ? 20:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:20) - (0 ? 20:20) + 1))))))) << (0 ? 20:20))) | (((gctUINT32) ((gctUINT32) (Enable == 0) & ((gctUINT32) ((((1 ? 20:20) - (0 ? 20:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:20) - (0 ? 20:20) + 1))))))) << (0 ? 20:20)));
++
++ if (
++ ((((gctUINT32) (Hardware->identity.chipMinorFeatures2)) >> (0 ? 27:27) & ((gctUINT32) ((((1 ? 27:27) - (0 ? 27:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:27) - (0 ? 27:27) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 27:27) - (0 ? 27:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:27) - (0 ? 27:27) + 1))))))) ||
++ (Hardware->identity.chipModel >= gcv4000))
++ {
++ /* Set compression bypass. */
++ debug = ((((gctUINT32) (debug)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 21:21) - (0 ? 21:21) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 21:21) - (0 ? 21:21) + 1))))))) << (0 ? 21:21))) | (((gctUINT32) ((gctUINT32) (Compression == 0) & ((gctUINT32) ((((1 ? 21:21) - (0 ? 21:21) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 21:21) - (0 ? 21:21) + 1))))))) << (0 ? 21:21)));
++ }
++
++ /* Write back AQMemoryDebug register. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00414,
++ debug));
++
++ /* Store fast clear and comprersison flags. */
++ Hardware->allowFastClear = Enable;
++ Hardware->allowCompression = Compression;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "FastClear=%d Compression=%d", Enable, Compression);
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++#else
++ return gcvSTATUS_OK;
++#endif
++}
++
++typedef enum
++{
++ gcvPOWER_FLAG_INITIALIZE = 1 << 0,
++ gcvPOWER_FLAG_STALL = 1 << 1,
++ gcvPOWER_FLAG_STOP = 1 << 2,
++ gcvPOWER_FLAG_START = 1 << 3,
++ gcvPOWER_FLAG_RELEASE = 1 << 4,
++ gcvPOWER_FLAG_DELAY = 1 << 5,
++ gcvPOWER_FLAG_SAVE = 1 << 6,
++ gcvPOWER_FLAG_ACQUIRE = 1 << 7,
++ gcvPOWER_FLAG_POWER_OFF = 1 << 8,
++ gcvPOWER_FLAG_CLOCK_OFF = 1 << 9,
++ gcvPOWER_FLAG_CLOCK_ON = 1 << 10,
++}
++gcePOWER_FLAGS;
++
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++static gctCONST_STRING
++_PowerEnum(gceCHIPPOWERSTATE State)
++{
++ const gctCONST_STRING states[] =
++ {
++ gcmSTRING(gcvPOWER_ON),
++ gcmSTRING(gcvPOWER_OFF),
++ gcmSTRING(gcvPOWER_IDLE),
++ gcmSTRING(gcvPOWER_SUSPEND),
++ gcmSTRING(gcvPOWER_SUSPEND_ATPOWERON),
++ gcmSTRING(gcvPOWER_OFF_ATPOWERON),
++ gcmSTRING(gcvPOWER_IDLE_BROADCAST),
++ gcmSTRING(gcvPOWER_SUSPEND_BROADCAST),
++ gcmSTRING(gcvPOWER_OFF_BROADCAST),
++ gcmSTRING(gcvPOWER_OFF_RECOVERY),
++ gcmSTRING(gcvPOWER_OFF_TIMEOUT),
++ gcmSTRING(gcvPOWER_ON_AUTO)
++ };
++
++ if ((State >= gcvPOWER_ON) && (State <= gcvPOWER_ON_AUTO))
++ {
++ return states[State - gcvPOWER_ON];
++ }
++
++ return "unknown";
++}
++#endif
++
++/*******************************************************************************
++**
++** gckHARDWARE_SetPowerManagementState
++**
++** Set GPU to a specified power state.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** gceCHIPPOWERSTATE State
++** Power State.
++**
++*/
++gceSTATUS
++gckHARDWARE_SetPowerManagementState(
++ IN gckHARDWARE Hardware,
++ IN gceCHIPPOWERSTATE State
++ )
++{
++ gceSTATUS status;
++ gckCOMMAND command = gcvNULL;
++ gckOS os;
++ gctUINT flag, clock;
++ gctPOINTER buffer;
++ gctUINT32 bytes, requested;
++ gctBOOL acquired = gcvFALSE;
++ gctBOOL mutexAcquired = gcvFALSE;
++ gctBOOL stall = gcvTRUE;
++ gctBOOL broadcast = gcvFALSE;
++#if gcdPOWEROFF_TIMEOUT
++ gctBOOL timeout = gcvFALSE;
++ gctBOOL isAfter = gcvFALSE;
++ gctUINT32 currentTime;
++#endif
++ gctUINT32 process, thread;
++ gctBOOL commitEntered = gcvFALSE;
++ gctBOOL commandStarted = gcvFALSE;
++ gctBOOL isrStarted = gcvFALSE;
++
++#if gcdENABLE_PROFILING
++ gctUINT64 time, freq, mutexTime, onTime, stallTime, stopTime, delayTime,
++ initTime, offTime, startTime, totalTime;
++#endif
++ gctBOOL global = gcvFALSE;
++ gctBOOL globalAcquired = gcvFALSE;
++ gctBOOL configMmu = gcvFALSE;
++
++ /* State transition flags. */
++ static const gctUINT flags[4][4] =
++ {
++ /* gcvPOWER_ON */
++ { /* ON */ 0,
++ /* OFF */ gcvPOWER_FLAG_ACQUIRE |
++ gcvPOWER_FLAG_STALL |
++ gcvPOWER_FLAG_STOP |
++ gcvPOWER_FLAG_POWER_OFF |
++ gcvPOWER_FLAG_CLOCK_OFF,
++ /* IDLE */ gcvPOWER_FLAG_ACQUIRE |
++ gcvPOWER_FLAG_STALL,
++ /* SUSPEND */ gcvPOWER_FLAG_ACQUIRE |
++ gcvPOWER_FLAG_STALL |
++ gcvPOWER_FLAG_STOP |
++ gcvPOWER_FLAG_CLOCK_OFF,
++ },
++
++ /* gcvPOWER_OFF */
++ { /* ON */ gcvPOWER_FLAG_INITIALIZE |
++ gcvPOWER_FLAG_START |
++ gcvPOWER_FLAG_RELEASE |
++ gcvPOWER_FLAG_DELAY,
++ /* OFF */ 0,
++ /* IDLE */ gcvPOWER_FLAG_INITIALIZE |
++ gcvPOWER_FLAG_START |
++ gcvPOWER_FLAG_DELAY,
++ /* SUSPEND */ gcvPOWER_FLAG_INITIALIZE |
++ gcvPOWER_FLAG_CLOCK_OFF,
++ },
++
++ /* gcvPOWER_IDLE */
++ { /* ON */ gcvPOWER_FLAG_RELEASE,
++ /* OFF */ gcvPOWER_FLAG_STOP |
++ gcvPOWER_FLAG_POWER_OFF |
++ gcvPOWER_FLAG_CLOCK_OFF,
++ /* IDLE */ 0,
++ /* SUSPEND */ gcvPOWER_FLAG_STOP |
++ gcvPOWER_FLAG_CLOCK_OFF,
++ },
++
++ /* gcvPOWER_SUSPEND */
++ { /* ON */ gcvPOWER_FLAG_START |
++ gcvPOWER_FLAG_RELEASE |
++ gcvPOWER_FLAG_DELAY |
++ gcvPOWER_FLAG_CLOCK_ON,
++ /* OFF */ gcvPOWER_FLAG_SAVE |
++ gcvPOWER_FLAG_POWER_OFF |
++ gcvPOWER_FLAG_CLOCK_OFF,
++ /* IDLE */ gcvPOWER_FLAG_START |
++ gcvPOWER_FLAG_DELAY |
++ gcvPOWER_FLAG_CLOCK_ON,
++ /* SUSPEND */ 0,
++ },
++ };
++
++ /* Clocks. */
++ static const gctUINT clocks[4] =
++ {
++ /* gcvPOWER_ON */
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) | (((gctUINT32) ((gctUINT32) (64) & ((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))),
++
++ /* gcvPOWER_OFF */
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))),
++
++ /* gcvPOWER_IDLE */
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))),
++
++ /* gcvPOWER_SUSPEND */
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))),
++ };
++
++ gcmkHEADER_ARG("Hardware=0x%x State=%d", Hardware, State);
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Switching to power state %d(%s)",
++ State, _PowerEnum(State));
++#endif
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Get the gckOS object pointer. */
++ os = Hardware->os;
++ gcmkVERIFY_OBJECT(os, gcvOBJ_OS);
++
++ /* Get the gckCOMMAND object pointer. */
++ gcmkVERIFY_OBJECT(Hardware->kernel, gcvOBJ_KERNEL);
++ command = Hardware->kernel->command;
++ gcmkVERIFY_OBJECT(command, gcvOBJ_COMMAND);
++
++ /* Start profiler. */
++ gcmkPROFILE_INIT(freq, time);
++
++ /* Convert the broadcast power state. */
++ switch (State)
++ {
++ case gcvPOWER_SUSPEND_ATPOWERON:
++ /* Convert to SUSPEND and don't wait for STALL. */
++ State = gcvPOWER_SUSPEND;
++ stall = gcvFALSE;
++ break;
++
++ case gcvPOWER_OFF_ATPOWERON:
++ /* Convert to OFF and don't wait for STALL. */
++ State = gcvPOWER_OFF;
++ stall = gcvFALSE;
++ break;
++
++ case gcvPOWER_IDLE_BROADCAST:
++ /* Convert to IDLE and note we are inside broadcast. */
++ State = gcvPOWER_IDLE;
++ broadcast = gcvTRUE;
++ break;
++
++ case gcvPOWER_SUSPEND_BROADCAST:
++ /* Convert to SUSPEND and note we are inside broadcast. */
++ State = gcvPOWER_SUSPEND;
++ broadcast = gcvTRUE;
++ break;
++
++ case gcvPOWER_OFF_BROADCAST:
++ /* Convert to OFF and note we are inside broadcast. */
++ State = gcvPOWER_OFF;
++ broadcast = gcvTRUE;
++ break;
++
++ case gcvPOWER_OFF_RECOVERY:
++ /* Convert to OFF and note we are inside recovery. */
++ State = gcvPOWER_OFF;
++ stall = gcvFALSE;
++ broadcast = gcvTRUE;
++ break;
++
++ case gcvPOWER_ON_AUTO:
++ /* Convert to ON and note we are inside recovery. */
++ State = gcvPOWER_ON;
++ break;
++
++ case gcvPOWER_ON:
++ case gcvPOWER_IDLE:
++ case gcvPOWER_SUSPEND:
++ case gcvPOWER_OFF:
++ /* Mark as global power management. */
++ global = gcvTRUE;
++ break;
++
++#if gcdPOWEROFF_TIMEOUT
++ case gcvPOWER_OFF_TIMEOUT:
++ /* Convert to OFF and note we are inside broadcast. */
++ State = gcvPOWER_OFF;
++ broadcast = gcvTRUE;
++ /* Check time out */
++ timeout = gcvTRUE;
++ break;
++#endif
++
++ default:
++ break;
++ }
++
++ if (Hardware->powerManagement == gcvFALSE
++ && State != gcvPOWER_ON
++ )
++ {
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++
++ /* Get current process and thread IDs. */
++ gcmkONERROR(gckOS_GetProcessID(&process));
++ gcmkONERROR(gckOS_GetThreadID(&thread));
++
++ if (broadcast)
++ {
++ /* Try to acquire the power mutex. */
++ status = gckOS_AcquireMutex(os, Hardware->powerMutex, 0);
++
++ if (status == gcvSTATUS_TIMEOUT)
++ {
++ /* Check if we already own this mutex. */
++ if ((Hardware->powerProcess == process)
++ && (Hardware->powerThread == thread)
++ )
++ {
++ /* Bail out on recursive power management. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++ else if (State != gcvPOWER_ON)
++ {
++ /* Called from IST,
++ ** so waiting here will cause deadlock,
++ ** if lock holder call gckCOMMAND_Stall() */
++ status = gcvSTATUS_INVALID_REQUEST;
++ goto OnError;
++ }
++ else
++ {
++ /* Acquire the power mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(os,
++ Hardware->powerMutex,
++ gcvINFINITE));
++ }
++ }
++ }
++ else
++ {
++ /* Acquire the power mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(os, Hardware->powerMutex, gcvINFINITE));
++ }
++
++ /* Get time until mtuex acquired. */
++ gcmkPROFILE_QUERY(time, mutexTime);
++
++ Hardware->powerProcess = process;
++ Hardware->powerThread = thread;
++ mutexAcquired = gcvTRUE;
++
++ /* Grab control flags and clock. */
++ flag = flags[Hardware->chipPowerState][State];
++ clock = clocks[State];
++
++#if gcdENABLE_FSCALE_VAL_ADJUST
++ if (State == gcvPOWER_ON)
++ {
++ clock = ((((gctUINT32) (clock)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) | (((gctUINT32) ((gctUINT32) (Hardware->powerOnFscaleVal) & ((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2)));
++ }
++#endif
++
++ if (State == gcvPOWER_SUSPEND && Hardware->chipPowerState == gcvPOWER_OFF && broadcast)
++ {
++#if gcdPOWER_SUSPEND_WHEN_IDLE
++ /* Do nothing */
++
++ /* Release the power mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(os, Hardware->powerMutex));
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++#else
++ /* Clock should be on when switch power from off to suspend */
++ clock = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) ;
++#endif
++ }
++
++#if gcdPOWEROFF_TIMEOUT
++ if (timeout)
++ {
++ gcmkONERROR(gckOS_GetTicks(&currentTime));
++
++ gcmkONERROR(
++ gckOS_TicksAfter(Hardware->powerOffTime, currentTime, &isAfter));
++
++ /* powerOffTime is pushed forward, give up.*/
++ if (isAfter
++ /* Expect a transition start from IDLE or SUSPEND. */
++ || (Hardware->chipPowerState == gcvPOWER_ON)
++ || (Hardware->chipPowerState == gcvPOWER_OFF)
++ )
++ {
++ /* Release the power mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(os, Hardware->powerMutex));
++
++ /* No need to do anything. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Power Off GPU[%d] at %u [supposed to be at %u]",
++ Hardware->core, currentTime, Hardware->powerOffTime);
++ }
++#endif
++
++ if (flag == 0)
++ {
++ /* Release the power mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(os, Hardware->powerMutex));
++
++ /* No need to do anything. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++
++ /* If this is an internal power management, we have to check if we can grab
++ ** the global power semaphore. If we cannot, we have to wait until the
++ ** external world changes power management. */
++ if (!global)
++ {
++ /* Try to acquire the global semaphore. */
++ status = gckOS_TryAcquireSemaphore(os, Hardware->globalSemaphore);
++ if (status == gcvSTATUS_TIMEOUT)
++ {
++ if (State == gcvPOWER_IDLE || State == gcvPOWER_SUSPEND)
++ {
++ /* Called from thread routine which should NEVER sleep.*/
++ gcmkONERROR(gcvSTATUS_INVALID_REQUEST);
++ }
++
++ /* Release the power mutex. */
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Releasing the power mutex.");
++ gcmkONERROR(gckOS_ReleaseMutex(os, Hardware->powerMutex));
++ mutexAcquired = gcvFALSE;
++
++ /* Wait for the semaphore. */
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Waiting for global semaphore.");
++ gcmkONERROR(gckOS_AcquireSemaphore(os, Hardware->globalSemaphore));
++ globalAcquired = gcvTRUE;
++
++ /* Acquire the power mutex. */
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Reacquiring the power mutex.");
++ gcmkONERROR(gckOS_AcquireMutex(os,
++ Hardware->powerMutex,
++ gcvINFINITE));
++ mutexAcquired = gcvTRUE;
++
++ /* chipPowerState may be changed by external world during the time
++ ** we give up powerMutex, so updating flag now is necessary. */
++ flag = flags[Hardware->chipPowerState][State];
++
++ if (flag == 0)
++ {
++ gcmkONERROR(gckOS_ReleaseSemaphore(os, Hardware->globalSemaphore));
++ globalAcquired = gcvFALSE;
++
++ gcmkONERROR(gckOS_ReleaseMutex(os, Hardware->powerMutex));
++ mutexAcquired = gcvFALSE;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++ }
++ else
++ {
++ /* Error. */
++ gcmkONERROR(status);
++ }
++
++ /* Release the global semaphore again. */
++ gcmkONERROR(gckOS_ReleaseSemaphore(os, Hardware->globalSemaphore));
++ globalAcquired = gcvFALSE;
++ }
++ else
++ {
++ if (State == gcvPOWER_OFF || State == gcvPOWER_SUSPEND || State == gcvPOWER_IDLE)
++ {
++ /* Acquire the global semaphore if it has not been acquired. */
++ status = gckOS_TryAcquireSemaphore(os, Hardware->globalSemaphore);
++ if (status == gcvSTATUS_OK)
++ {
++ globalAcquired = gcvTRUE;
++ }
++ else if (status != gcvSTATUS_TIMEOUT)
++ {
++ /* Other errors. */
++ gcmkONERROR(status);
++ }
++ /* Ignore gcvSTATUS_TIMEOUT and leave globalAcquired as gcvFALSE.
++ ** gcvSTATUS_TIMEOUT means global semaphore has already
++ ** been acquired before this operation, so even if we fail,
++ ** we should not release it in our error handling. It should be
++ ** released by the next successful global gcvPOWER_ON. */
++ }
++
++ /* Global power management can't be aborted, so sync with
++ ** proceeding last commit. */
++ if (flag & gcvPOWER_FLAG_ACQUIRE)
++ {
++ /* Acquire the power management semaphore. */
++ gcmkONERROR(gckOS_AcquireSemaphore(os, command->powerSemaphore));
++ acquired = gcvTRUE;
++
++ /* avoid acquiring again. */
++ flag &= ~gcvPOWER_FLAG_ACQUIRE;
++ }
++ }
++
++ if (flag & (gcvPOWER_FLAG_INITIALIZE | gcvPOWER_FLAG_CLOCK_ON))
++ {
++ /* Turn on the power. */
++ gcmkONERROR(gckOS_SetGPUPower(os, Hardware->core, gcvTRUE, gcvTRUE));
++
++ /* Mark clock and power as enabled. */
++ Hardware->clockState = gcvTRUE;
++ Hardware->powerState = gcvTRUE;
++
++ for (;;)
++ {
++ /* Check if GPU is present and awake. */
++ status = _IsGPUPresent(Hardware);
++
++ /* Check if the GPU is not responding. */
++ if (status == gcvSTATUS_GPU_NOT_RESPONDING)
++ {
++ /* Turn off the power and clock. */
++ gcmkONERROR(gckOS_SetGPUPower(os, Hardware->core, gcvFALSE, gcvFALSE));
++
++ Hardware->clockState = gcvFALSE;
++ Hardware->powerState = gcvFALSE;
++
++ /* Wait a little. */
++ gckOS_Delay(os, 1);
++
++ /* Turn on the power and clock. */
++ gcmkONERROR(gckOS_SetGPUPower(os, Hardware->core, gcvTRUE, gcvTRUE));
++
++ Hardware->clockState = gcvTRUE;
++ Hardware->powerState = gcvTRUE;
++
++ /* We need to initialize the hardware and start the command
++ * processor. */
++ flag |= gcvPOWER_FLAG_INITIALIZE | gcvPOWER_FLAG_START;
++ }
++ else
++ {
++ /* Test for error. */
++ gcmkONERROR(status);
++
++ /* Break out of loop. */
++ break;
++ }
++ }
++ }
++
++ /* Get time until powered on. */
++ gcmkPROFILE_QUERY(time, onTime);
++
++ if ((flag & gcvPOWER_FLAG_STALL) && stall)
++ {
++ gctBOOL idle;
++ gctINT32 atomValue;
++
++ /* For global operation, all pending commits have already been
++ ** blocked by globalSemaphore or powerSemaphore.*/
++ if (!global)
++ {
++ /* Check commit atom. */
++ gcmkONERROR(gckOS_AtomGet(os, command->atomCommit, &atomValue));
++
++ if (atomValue > 0)
++ {
++ /* Commits are pending - abort power management. */
++ status = broadcast ? gcvSTATUS_CHIP_NOT_READY
++ : gcvSTATUS_MORE_DATA;
++ goto OnError;
++ }
++ }
++
++ if (broadcast)
++ {
++ /* Check for idle. */
++ gcmkONERROR(gckHARDWARE_QueryIdle(Hardware, &idle));
++
++ if (!idle)
++ {
++ status = gcvSTATUS_CHIP_NOT_READY;
++ goto OnError;
++ }
++ }
++
++ else
++ {
++ /* Acquire the command queue. */
++ gcmkONERROR(gckCOMMAND_EnterCommit(command, gcvTRUE));
++ commitEntered = gcvTRUE;
++
++ /* Get the size of the flush command. */
++ gcmkONERROR(gckHARDWARE_Flush(Hardware,
++ gcvFLUSH_ALL,
++ gcvNULL,
++ &requested));
++
++ /* Reserve space in the command queue. */
++ gcmkONERROR(gckCOMMAND_Reserve(command,
++ requested,
++ &buffer,
++ &bytes));
++
++ /* Append a flush. */
++ gcmkONERROR(gckHARDWARE_Flush(
++ Hardware, gcvFLUSH_ALL, buffer, &bytes
++ ));
++
++ /* Execute the command queue. */
++ gcmkONERROR(gckCOMMAND_Execute(command, requested));
++
++ /* Release the command queue. */
++ gcmkONERROR(gckCOMMAND_ExitCommit(command, gcvTRUE));
++ commitEntered = gcvFALSE;
++
++ /* Wait to finish all commands. */
++#if gcdMULTI_GPU
++ gcmkONERROR(gckCOMMAND_Stall(command, gcvTRUE, gcvCORE_3D_ALL_MASK));
++#else
++ gcmkONERROR(gckCOMMAND_Stall(command, gcvTRUE));
++#endif
++ }
++ }
++
++ /* Get time until stalled. */
++ gcmkPROFILE_QUERY(time, stallTime);
++
++ if (flag & gcvPOWER_FLAG_ACQUIRE)
++ {
++ /* Acquire the power management semaphore. */
++ gcmkONERROR(gckOS_AcquireSemaphore(os, command->powerSemaphore));
++ acquired = gcvTRUE;
++ }
++
++ if (flag & gcvPOWER_FLAG_STOP)
++ {
++ /* Stop the command parser. */
++ gcmkONERROR(gckCOMMAND_Stop(command, gcvFALSE));
++
++ /* Stop the Isr. */
++ if (Hardware->stopIsr)
++ {
++ gcmkONERROR(Hardware->stopIsr(Hardware->isrContext));
++ }
++ }
++
++ /* Flush Cache before Power Off. */
++ if (flag & gcvPOWER_FLAG_POWER_OFF)
++ {
++ if (Hardware->clockState == gcvFALSE)
++ {
++ /* Turn off the GPU power. */
++ gcmkONERROR(
++ gckOS_SetGPUPower(os,
++ Hardware->core,
++ gcvTRUE,
++ gcvTRUE));
++
++ Hardware->clockState = gcvTRUE;
++
++ if (gckHARDWARE_IsFeatureAvailable(Hardware, gcvFEATURE_DYNAMIC_FREQUENCY_SCALING) != gcvTRUE)
++ {
++ /* Write the clock control register. */
++ gcmkONERROR(gckOS_WriteRegisterEx(os,
++ Hardware->core,
++ 0x00000,
++ clocks[0]));
++
++ /* Done loading the frequency scaler. */
++ gcmkONERROR(gckOS_WriteRegisterEx(os,
++ Hardware->core,
++ 0x00000,
++ ((((gctUINT32) (clocks[0])) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9)))));
++ }
++ }
++
++ gcmkONERROR(gckCOMMAND_Start(command));
++
++ gcmkONERROR(_FlushCache(Hardware, command));
++
++ gckOS_Delay(gcvNULL, 1);
++
++ /* Stop the command parser. */
++ gcmkONERROR(gckCOMMAND_Stop(command, gcvFALSE));
++
++ flag |= gcvPOWER_FLAG_CLOCK_OFF;
++ }
++
++ /* Get time until stopped. */
++ gcmkPROFILE_QUERY(time, stopTime);
++
++ /* Only process this when hardware is enabled. */
++ if (Hardware->clockState && Hardware->powerState
++ /* Don't touch clock control if dynamic frequency scaling is available. */
++ && gckHARDWARE_IsFeatureAvailable(Hardware, gcvFEATURE_DYNAMIC_FREQUENCY_SCALING) != gcvTRUE
++ )
++ {
++ if (flag & (gcvPOWER_FLAG_POWER_OFF | gcvPOWER_FLAG_CLOCK_OFF))
++ {
++ if (Hardware->identity.chipModel == gcv4000
++ && ((Hardware->identity.chipRevision == 0x5208) || (Hardware->identity.chipRevision == 0x5222)))
++ {
++ clock &= ~2U;
++ }
++ }
++
++ /* Write the clock control register. */
++ gcmkONERROR(gckOS_WriteRegisterEx(os,
++ Hardware->core,
++ 0x00000,
++ clock));
++
++ /* Done loading the frequency scaler. */
++ gcmkONERROR(gckOS_WriteRegisterEx(os,
++ Hardware->core,
++ 0x00000,
++ ((((gctUINT32) (clock)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9)))));
++ }
++
++ if (flag & gcvPOWER_FLAG_DELAY)
++ {
++ /* Wait for the specified amount of time to settle coming back from
++ ** power-off or suspend state. */
++ gcmkONERROR(gckOS_Delay(os, gcdPOWER_CONTROL_DELAY));
++ }
++
++ /* Get time until delayed. */
++ gcmkPROFILE_QUERY(time, delayTime);
++
++ if (flag & gcvPOWER_FLAG_INITIALIZE)
++ {
++ /* Initialize hardware. */
++ gcmkONERROR(gckHARDWARE_InitializeHardware(Hardware));
++
++ gcmkONERROR(gckHARDWARE_SetFastClear(Hardware,
++ Hardware->allowFastClear,
++ Hardware->allowCompression));
++
++ /* Force the command queue to reload the next context. */
++ command->currContext = gcvNULL;
++
++ /* Need to config mmu after command start. */
++ configMmu = gcvTRUE;
++ }
++
++ /* Get time until initialized. */
++ gcmkPROFILE_QUERY(time, initTime);
++
++ if (flag & (gcvPOWER_FLAG_POWER_OFF | gcvPOWER_FLAG_CLOCK_OFF))
++ {
++ /* Turn off the GPU power. */
++ gcmkONERROR(
++ gckOS_SetGPUPower(os,
++ Hardware->core,
++ (flag & gcvPOWER_FLAG_CLOCK_OFF) ? gcvFALSE
++ : gcvTRUE,
++ (flag & gcvPOWER_FLAG_POWER_OFF) ? gcvFALSE
++ : gcvTRUE));
++
++ /* Save current hardware power and clock states. */
++ Hardware->clockState = (flag & gcvPOWER_FLAG_CLOCK_OFF) ? gcvFALSE
++ : gcvTRUE;
++ Hardware->powerState = (flag & gcvPOWER_FLAG_POWER_OFF) ? gcvFALSE
++ : gcvTRUE;
++ }
++
++ /* Get time until off. */
++ gcmkPROFILE_QUERY(time, offTime);
++
++ if (flag & gcvPOWER_FLAG_START)
++ {
++ /* Start the command processor. */
++ gcmkONERROR(gckCOMMAND_Start(command));
++ commandStarted = gcvTRUE;
++
++ if (Hardware->startIsr)
++ {
++ /* Start the Isr. */
++ gcmkONERROR(Hardware->startIsr(Hardware->isrContext));
++ isrStarted = gcvTRUE;
++ }
++ }
++
++ /* Get time until started. */
++ gcmkPROFILE_QUERY(time, startTime);
++
++ if (flag & gcvPOWER_FLAG_RELEASE)
++ {
++ /* Release the power management semaphore. */
++ gcmkONERROR(gckOS_ReleaseSemaphore(os, command->powerSemaphore));
++ acquired = gcvFALSE;
++
++ if (global)
++ {
++ /* Verify global semaphore has been acquired already before
++ ** we release it.
++ ** If it was acquired, gckOS_TryAcquireSemaphore will return
++ ** gcvSTATUS_TIMEOUT and we release it. Otherwise, global
++ ** semaphore will be acquried now, but it still is released
++ ** immediately. */
++ status = gckOS_TryAcquireSemaphore(os, Hardware->globalSemaphore);
++ if (status != gcvSTATUS_TIMEOUT)
++ {
++ gcmkONERROR(status);
++ }
++
++ /* Release the global semaphore. */
++ gcmkONERROR(gckOS_ReleaseSemaphore(os, Hardware->globalSemaphore));
++ globalAcquired = gcvFALSE;
++ }
++ }
++
++ /* Save the new power state. */
++ Hardware->chipPowerState = State;
++
++#if gcdDVFS
++ if (State == gcvPOWER_ON && Hardware->kernel->dvfs)
++ {
++ gckDVFS_Start(Hardware->kernel->dvfs);
++ }
++#endif
++
++#if gcdPOWEROFF_TIMEOUT
++ /* Reset power off time */
++ gcmkONERROR(gckOS_GetTicks(&currentTime));
++
++ Hardware->powerOffTime = currentTime + Hardware->powerOffTimeout;
++
++ if (State == gcvPOWER_IDLE || State == gcvPOWER_SUSPEND)
++ {
++ /* Start a timer to power off GPU when GPU enters IDLE or SUSPEND. */
++ gcmkVERIFY_OK(gckOS_StartTimer(os,
++ Hardware->powerOffTimer,
++ Hardware->powerOffTimeout));
++ }
++ else
++ {
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, "Cancel powerOfftimer");
++
++ /* Cancel running timer when GPU enters ON or OFF. */
++ gcmkVERIFY_OK(gckOS_StopTimer(os, Hardware->powerOffTimer));
++ }
++#endif
++
++ /* Release the power mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(os, Hardware->powerMutex));
++
++ /* Get total time. */
++ gcmkPROFILE_QUERY(time, totalTime);
++#if gcdENABLE_PROFILING
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "PROF(%llu): mutex:%llu on:%llu stall:%llu stop:%llu",
++ freq, mutexTime, onTime, stallTime, stopTime);
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ " delay:%llu init:%llu off:%llu start:%llu total:%llu",
++ delayTime, initTime, offTime, startTime, totalTime);
++#endif
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (commandStarted)
++ {
++ gcmkVERIFY_OK(gckCOMMAND_Stop(command, gcvFALSE));
++ }
++
++ if (isrStarted)
++ {
++ gcmkVERIFY_OK(Hardware->stopIsr(Hardware->isrContext));
++ }
++
++ if (commitEntered)
++ {
++ /* Release the command queue mutex. */
++ gcmkVERIFY_OK(gckCOMMAND_ExitCommit(command, gcvTRUE));
++ }
++
++ if (acquired)
++ {
++ /* Release semaphore. */
++ gcmkVERIFY_OK(gckOS_ReleaseSemaphore(Hardware->os,
++ command->powerSemaphore));
++ }
++
++ if (globalAcquired)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseSemaphore(Hardware->os,
++ Hardware->globalSemaphore));
++ }
++
++ if (mutexAcquired)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Hardware->os, Hardware->powerMutex));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_QueryPowerManagementState
++**
++** Get GPU power state.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** gceCHIPPOWERSTATE* State
++** Power State.
++**
++*/
++gceSTATUS
++gckHARDWARE_QueryPowerManagementState(
++ IN gckHARDWARE Hardware,
++ OUT gceCHIPPOWERSTATE* State
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(State != gcvNULL);
++
++ /* Return the statue. */
++ *State = Hardware->chipPowerState;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*State=%d", *State);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_SetPowerManagement
++**
++** Configure GPU power management function.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** gctBOOL PowerManagement
++** Power Mangement State.
++**
++*/
++gceSTATUS
++gckHARDWARE_SetPowerManagement(
++ IN gckHARDWARE Hardware,
++ IN gctBOOL PowerManagement
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ if(!Hardware->powerManagementLock)
++ {
++ gcmkVERIFY_OK(
++ gckOS_AcquireMutex(Hardware->os, Hardware->powerMutex, gcvINFINITE));
++
++ Hardware->powerManagement = PowerManagement;
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Hardware->os, Hardware->powerMutex));
++ }
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_SetPowerManagementLock
++**
++** Disable dynamic GPU power management switch.
++** Only used in driver initialization stage.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** gctBOOL Lock
++** Power Mangement Lock State.
++**
++*/
++gceSTATUS
++gckHARDWARE_SetPowerManagementLock(
++ IN gckHARDWARE Hardware,
++ IN gctBOOL Lock
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ Hardware->powerManagementLock = Lock;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++/*******************************************************************************
++**
++** gckHARDWARE_SetGpuProfiler
++**
++** Configure GPU profiler function.
++** Only used in driver initialization stage.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** gctBOOL GpuProfiler
++** GOU Profiler State.
++**
++*/
++gceSTATUS
++gckHARDWARE_SetGpuProfiler(
++ IN gckHARDWARE Hardware,
++ IN gctBOOL GpuProfiler
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ if (GpuProfiler == gcvTRUE)
++ {
++ gctUINT32 data = 0;
++
++ /* Need to disable clock gating when doing profiling. */
++ gcmkVERIFY_OK(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress +
++ 0x00100,
++ &data));
++
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)));
++
++
++ gcmkVERIFY_OK(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress
++ + 0x00100,
++ data));
++ }
++
++ Hardware->gpuProfiler = GpuProfiler;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++#if gcdENABLE_FSCALE_VAL_ADJUST
++gceSTATUS
++gckHARDWARE_SetFscaleValue(
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 FscaleValue
++ )
++{
++ gceSTATUS status;
++ gctUINT32 clock;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Hardware=0x%x FscaleValue=%d", Hardware, FscaleValue);
++
++ gcmkVERIFY_ARGUMENT(FscaleValue > 0 && FscaleValue <= 64);
++
++ gcmkONERROR(
++ gckOS_AcquireMutex(Hardware->os, Hardware->powerMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ Hardware->powerOnFscaleVal = FscaleValue;
++
++ if (Hardware->chipPowerState == gcvPOWER_ON)
++ {
++ gctUINT32 data;
++
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress
++ + 0x00104,
++ &data));
++
++ /* Disable all clock gating. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress
++ + 0x00104,
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1))))))) << (0 ? 7:7))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1))))))) << (0 ? 7:7)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 8:8) - (0 ? 8:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:8) - (0 ? 8:8) + 1))))))) << (0 ? 8:8))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 8:8) - (0 ? 8:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:8) - (0 ? 8:8) + 1))))))) << (0 ? 8:8)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 11:11) - (0 ? 11:11) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:11) - (0 ? 11:11) + 1))))))) << (0 ? 11:11))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 11:11) - (0 ? 11:11) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:11) - (0 ? 11:11) + 1))))))) << (0 ? 11:11)))));
++
++ clock = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) | (((gctUINT32) ((gctUINT32) (FscaleValue) & ((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9)));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ clock));
++
++ /* Done loading the frequency scaler. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ ((((gctUINT32) (clock)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9)))));
++
++ /* Restore all clock gating. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress
++ + 0x00104,
++ data));
++ }
++
++ gcmkVERIFY(gckOS_ReleaseMutex(Hardware->os, Hardware->powerMutex));
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ gcmkVERIFY(gckOS_ReleaseMutex(Hardware->os, Hardware->powerMutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckHARDWARE_GetFscaleValue(
++ IN gckHARDWARE Hardware,
++ IN gctUINT * FscaleValue,
++ IN gctUINT * MinFscaleValue,
++ IN gctUINT * MaxFscaleValue
++ )
++{
++ *FscaleValue = Hardware->powerOnFscaleVal;
++ *MinFscaleValue = Hardware->minFscaleValue;
++ *MaxFscaleValue = 64;
++
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckHARDWARE_SetMinFscaleValue(
++ IN gckHARDWARE Hardware,
++ IN gctUINT MinFscaleValue
++ )
++{
++ if (MinFscaleValue >= 1 && MinFscaleValue <= 64)
++ {
++ Hardware->minFscaleValue = MinFscaleValue;
++ }
++
++ return gcvSTATUS_OK;
++}
++#endif
++
++#if gcdPOWEROFF_TIMEOUT
++gceSTATUS
++gckHARDWARE_SetPowerOffTimeout(
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 Timeout
++)
++{
++ gcmkHEADER_ARG("Hardware=0x%x Timeout=%d", Hardware, Timeout);
++
++ Hardware->powerOffTimeout = Timeout;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++
++gceSTATUS
++gckHARDWARE_QueryPowerOffTimeout(
++ IN gckHARDWARE Hardware,
++ OUT gctUINT32* Timeout
++)
++{
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ *Timeout = Hardware->powerOffTimeout;
++
++ gcmkFOOTER_ARG("*Timeout=%d", *Timeout);
++ return gcvSTATUS_OK;
++}
++#endif
++
++gceSTATUS
++gckHARDWARE_QueryIdle(
++ IN gckHARDWARE Hardware,
++ OUT gctBOOL_PTR IsIdle
++ )
++{
++ gceSTATUS status;
++ gctUINT32 idle, address;
++ gctBOOL isIdle;
++#if gcdMULTI_GPU > 1
++ gctUINT32 idle3D1 = 0;
++ gctUINT32 address3D1;
++ gctBOOL isIdle3D1 = gcvFALSE;
++#endif
++
++#if gcdINTERRUPT_STATISTIC
++ gctINT32 pendingInterrupt;
++#endif
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(IsIdle != gcvNULL);
++
++ /* We are idle when the power is not ON. */
++ if (Hardware->chipPowerState != gcvPOWER_ON)
++ {
++ isIdle = gcvTRUE;
++#if gcdMULTI_GPU > 1
++ isIdle3D1 = gcvTRUE;
++#endif
++ }
++
++ else
++ {
++ /* Read idle register. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00004, &idle));
++
++#if gcdMULTI_GPU > 1
++ if (Hardware->core == gcvCORE_MAJOR)
++ {
++ gcmkONERROR(
++ gckOS_ReadRegisterByCoreId(Hardware->os,
++ Hardware->core,
++ gcvCORE_3D_1_ID,
++ 0x00004,
++ &idle3D1));
++ }
++#endif
++
++ /* Pipe must be idle. */
++ if (((((((gctUINT32) (idle)) >> (0 ? 1:1)) & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1)))))) ) != 1)
++ || ((((((gctUINT32) (idle)) >> (0 ? 3:3)) & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1)))))) ) != 1)
++ || ((((((gctUINT32) (idle)) >> (0 ? 4:4)) & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1)))))) ) != 1)
++ || ((((((gctUINT32) (idle)) >> (0 ? 5:5)) & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1)))))) ) != 1)
++ || ((((((gctUINT32) (idle)) >> (0 ? 6:6)) & ((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1)))))) ) != 1)
++ || ((((((gctUINT32) (idle)) >> (0 ? 7:7)) & ((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1)))))) ) != 1)
++ || ((((((gctUINT32) (idle)) >> (0 ? 2:2)) & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1)))))) ) != 1)
++ )
++ {
++ /* Something is busy. */
++ isIdle = gcvFALSE;
++ }
++
++ else
++ {
++#if gcdSECURITY
++ isIdle = gcvTRUE;
++ address = 0;
++#else
++ /* Read the current FE address. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00664,
++ &address));
++
++ /* Test if address is inside the last WAIT/LINK sequence. */
++ if ((address >= Hardware->lastWaitLink)
++#if gcdMULTI_GPU
++ && (address <= Hardware->lastWaitLink + 40)
++#else
++ && (address <= Hardware->lastWaitLink + 16)
++#endif
++ )
++ {
++ /* FE is in last WAIT/LINK and the pipe is idle. */
++ isIdle = gcvTRUE;
++ }
++ else
++ {
++ /* FE is not in WAIT/LINK yet. */
++ isIdle = gcvFALSE;
++ }
++#endif
++ }
++
++#if gcdMULTI_GPU > 1
++ if (Hardware->core == gcvCORE_MAJOR)
++ {
++ /* Pipe must be idle. */
++ if (((((((gctUINT32) (idle3D1)) >> (0 ? 1:1)) & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1)))))) ) != 1)
++ || ((((((gctUINT32) (idle3D1)) >> (0 ? 3:3)) & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1)))))) ) != 1)
++ || ((((((gctUINT32) (idle3D1)) >> (0 ? 4:4)) & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1)))))) ) != 1)
++ || ((((((gctUINT32) (idle3D1)) >> (0 ? 5:5)) & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1)))))) ) != 1)
++ || ((((((gctUINT32) (idle3D1)) >> (0 ? 6:6)) & ((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1)))))) ) != 1)
++ || ((((((gctUINT32) (idle3D1)) >> (0 ? 7:7)) & ((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1)))))) ) != 1)
++ || ((((((gctUINT32) (idle3D1)) >> (0 ? 2:2)) & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1)))))) ) != 1)
++ )
++ {
++ /* Something is busy. */
++ isIdle3D1 = gcvFALSE;
++ }
++
++ else
++ {
++ /* Read the current FE address. */
++ gcmkONERROR(gckOS_ReadRegisterByCoreId(Hardware->os,
++ Hardware->core,
++ gcvCORE_3D_1_ID,
++ 0x00664,
++ &address3D1));
++
++ /* Test if address is inside the last WAIT/LINK sequence. */
++ if ((address3D1 >= Hardware->lastWaitLink)
++ && (address3D1 <= Hardware->lastWaitLink + 40)
++ )
++ {
++ /* FE is in last WAIT/LINK and the pipe is idle. */
++ isIdle3D1 = gcvTRUE;
++ }
++ else
++ {
++ /* FE is not in WAIT/LINK yet. */
++ isIdle3D1 = gcvFALSE;
++ }
++ }
++ }
++#endif
++
++ }
++
++#if gcdINTERRUPT_STATISTIC
++ gcmkONERROR(gckOS_AtomGet(
++ Hardware->os,
++ Hardware->kernel->eventObj->interruptCount,
++ &pendingInterrupt
++ ));
++
++ if (pendingInterrupt)
++ {
++ isIdle = gcvFALSE;
++ }
++#endif
++
++#if gcdMULTI_GPU > 1
++ if (Hardware->core == gcvCORE_MAJOR)
++ {
++ *IsIdle = (isIdle & isIdle3D1);
++ }
++ else
++#endif
++ {
++ *IsIdle = isIdle;
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++** Handy macros that will help in reading those debug registers.
++*/
++
++#define gcmkREAD_DEBUG_REGISTER(control, block, index, data) \
++ gcmkONERROR(\
++ gckOS_WriteRegisterEx(Hardware->os, \
++ Hardware->core, \
++ GC_DEBUG_CONTROL##control##_Address, \
++ gcmSETFIELD(0, \
++ GC_DEBUG_CONTROL##control, \
++ block, \
++ index))); \
++ gcmkONERROR(\
++ gckOS_ReadRegisterEx(Hardware->os, \
++ Hardware->core, \
++ GC_DEBUG_SIGNALS_##block##_Address, \
++ &profiler->data))
++
++#define gcmkREAD_DEBUG_REGISTER_N(control, block, index, data) \
++ gcmkONERROR(\
++ gckOS_WriteRegisterEx(Hardware->os, \
++ Hardware->core, \
++ GC_DEBUG_CONTROL##control##_Address, \
++ gcmSETFIELD(0, \
++ GC_DEBUG_CONTROL##control, \
++ block, \
++ index))); \
++ gcmkONERROR(\
++ gckOS_ReadRegisterEx(Hardware->os, \
++ Hardware->core, \
++ GC_DEBUG_SIGNALS_##block##_Address, \
++ &data))
++
++#define gcmkRESET_DEBUG_REGISTER(control, block) \
++ gcmkONERROR(\
++ gckOS_WriteRegisterEx(Hardware->os, \
++ Hardware->core, \
++ GC_DEBUG_CONTROL##control##_Address, \
++ gcmSETFIELD(0, \
++ GC_DEBUG_CONTROL##control, \
++ block, \
++ 15))); \
++ gcmkONERROR(\
++ gckOS_WriteRegisterEx(Hardware->os, \
++ Hardware->core, \
++ GC_DEBUG_CONTROL##control##_Address, \
++ gcmSETFIELD(0, \
++ GC_DEBUG_CONTROL##control, \
++ block, \
++ 0)))
++
++/*******************************************************************************
++**
++** gckHARDWARE_ProfileEngine2D
++**
++** Read the profile registers available in the 2D engine and sets them in the
++** profile. The function will also reset the pixelsRendered counter every time.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to an gckHARDWARE object.
++**
++** OPTIONAL gcs2D_PROFILE_PTR Profile
++** Pointer to a gcs2D_Profile structure.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckHARDWARE_ProfileEngine2D(
++ IN gckHARDWARE Hardware,
++ OPTIONAL gcs2D_PROFILE_PTR Profile
++ )
++{
++ gceSTATUS status;
++ gcs2D_PROFILE_PTR profiler = Profile;
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ if (Profile != gcvNULL)
++ {
++ /* Read the cycle count. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00438,
++ &Profile->cycleCount));
++
++ /* Read pixels rendered by 2D engine. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (11) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00454, &profiler->pixelsRendered));
++
++ /* Reset counter. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))
++));
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++#if VIVANTE_PROFILER
++gceSTATUS
++gckHARDWARE_QueryProfileRegisters(
++ IN gckHARDWARE Hardware,
++ IN gctBOOL Reset,
++ OUT gcsPROFILER_COUNTERS * Counters
++ )
++{
++ gceSTATUS status;
++ gcsPROFILER_COUNTERS * profiler = Counters;
++ gctUINT i, clock;
++ gctUINT32 colorKilled, colorDrawn, depthKilled, depthDrawn;
++ gctUINT32 totalRead, totalWrite;
++
++ gcmkHEADER_ARG("Hardware=0x%x Counters=0x%x", Hardware, Counters);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Read the counters. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00438,
++ &profiler->gpuCyclesCounter));
++
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00078,
++ &profiler->gpuTotalCyclesCounter));
++
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0007C,
++ &profiler->gpuIdleCyclesCounter));
++
++
++ /* Read clock control register. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ &clock));
++
++ profiler->gpuTotalRead64BytesPerFrame = 0;
++ profiler->gpuTotalWrite64BytesPerFrame = 0;
++ profiler->pe_pixel_count_killed_by_color_pipe = 0;
++ profiler->pe_pixel_count_killed_by_depth_pipe = 0;
++ profiler->pe_pixel_count_drawn_by_color_pipe = 0;
++ profiler->pe_pixel_count_drawn_by_depth_pipe = 0;
++
++ /* Walk through all avaiable pixel pipes. */
++ for (i = 0; i < Hardware->identity.pixelPipes; ++i)
++ {
++ /* Select proper pipe. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ ((((gctUINT32) (clock)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:20) - (0 ? 23:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:20) - (0 ? 23:20) + 1))))))) << (0 ? 23:20))) | (((gctUINT32) ((gctUINT32) (i) & ((gctUINT32) ((((1 ? 23:20) - (0 ? 23:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:20) - (0 ? 23:20) + 1))))))) << (0 ? 23:20)))));
++
++ /* BW */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00040,
++ &totalRead));
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00044,
++ &totalWrite));
++
++ profiler->gpuTotalRead64BytesPerFrame += totalRead;
++ profiler->gpuTotalWrite64BytesPerFrame += totalWrite;
++
++ /* PE */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))));gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00454, &colorKilled));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))));gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00454, &depthKilled));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (2) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))));gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00454, &colorDrawn));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (3) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))));gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00454, &depthDrawn));
++
++ profiler->pe_pixel_count_killed_by_color_pipe += colorKilled;
++ profiler->pe_pixel_count_killed_by_depth_pipe += depthKilled;
++ profiler->pe_pixel_count_drawn_by_color_pipe += colorDrawn;
++ profiler->pe_pixel_count_drawn_by_depth_pipe += depthDrawn;
++ }
++
++ /* Reset clock control register. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ clock));
++
++ /* Reset counters. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x0003C, 1));
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x0003C, 0));
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00438, 0));
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00078, 0));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))
++));
++
++ /* SH */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (7) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->ps_inst_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (8) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->rendered_pixel_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (9) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->vs_inst_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (10) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->rendered_vertice_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (11) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->vtx_branch_inst_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (12) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->vtx_texld_inst_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (13) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->pxl_branch_inst_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (14) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->pxl_texld_inst_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24)))
++));
++
++ /* PA */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (3) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_input_vtx_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (4) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_input_prim_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (5) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_output_prim_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (6) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_depth_clipped_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (7) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_trivial_rejected_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (8) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_culled_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0)))
++));
++
++ /* SE */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00464, &profiler->se_culled_triangle_count));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00464, &profiler->se_culled_lines_count));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8)))
++));
++
++ /* RA */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_valid_pixel_count));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_total_quad_count));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (2) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_valid_quad_count_after_early_z));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (3) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_total_primitive_count));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (9) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_pipe_cache_miss_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (10) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_prefetch_cache_miss_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))
++));
++
++ /* TX */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_total_bilinear_requests));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_total_trilinear_requests));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (2) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_total_discarded_texture_requests));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (3) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_total_texture_requests));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (5) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_mem_read_count));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (6) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_mem_read_in_8B_count));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (7) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_cache_miss_count));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (8) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_cache_hit_texel_count));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (9) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_cache_miss_texel_count));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24)))
++));
++
++ /* MC */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00468, &profiler->mc_total_read_req_8B_from_pipeline));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (2) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00468, &profiler->mc_total_read_req_8B_from_IP));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (3) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00468, &profiler->mc_total_write_req_8B_from_pipeline));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0)))
++));
++
++ /* HI */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0046C, &profiler->hi_axi_cycles_read_request_stalled));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0046C, &profiler->hi_axi_cycles_write_request_stalled));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (2) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0046C, &profiler->hi_axi_cycles_write_data_stalled));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8)))
++));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++#endif
++
++
++#if VIVANTE_PROFILER_CONTEXT
++#define gcmkUPDATE_PROFILE_DATA(data) \
++ profilerHistroy->data += profiler->data
++
++gceSTATUS
++gckHARDWARE_QueryContextProfile(
++ IN gckHARDWARE Hardware,
++ IN gctBOOL Reset,
++ IN gckCONTEXT Context,
++ OUT gcsPROFILER_COUNTERS * Counters
++ )
++{
++ gceSTATUS status;
++ gckCOMMAND command = Hardware->kernel->command;
++ gcsPROFILER_COUNTERS * profiler = Counters;
++
++ gcmkHEADER_ARG("Hardware=0x%x Counters=0x%x", Hardware, Counters);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Acquire the context sequnence mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(
++ command->os, command->mutexContextSeq, gcvINFINITE
++ ));
++
++ /* Read the counters. */
++ gcmkVERIFY_OK(gckOS_MemCopy(
++ profiler, &Context->histroyProfiler, gcmSIZEOF(gcsPROFILER_COUNTERS)
++ ));
++
++ /* Reset counters. */
++ gcmkVERIFY_OK(gckOS_ZeroMemory(
++ &Context->histroyProfiler, gcmSIZEOF(gcsPROFILER_COUNTERS)
++ ));
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(
++ command->os, command->mutexContextSeq
++ ));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++static gctUINT32
++CalcDelta(
++ IN gctUINT32 new,
++ IN gctUINT32 old
++ )
++{
++ if (new >= old)
++ {
++ return new - old;
++ }
++ else
++ {
++ return (gctUINT32)((gctUINT64)new + 0x100000000ll - old);
++ }
++}
++
++gceSTATUS
++gckHARDWARE_UpdateContextProfile(
++ IN gckHARDWARE Hardware,
++ IN gckCONTEXT Context
++ )
++{
++ gceSTATUS status;
++ gcsPROFILER_COUNTERS * profiler = &Context->latestProfiler;
++ gcsPROFILER_COUNTERS * profilerHistroy = &Context->histroyProfiler;
++ gctUINT i, clock;
++ gctUINT32 colorKilled = 0, colorDrawn = 0, depthKilled = 0, depthDrawn = 0;
++ gctUINT32 totalRead, totalWrite;
++ gceCHIPMODEL chipModel;
++ gctUINT32 chipRevision;
++ gctUINT32 temp;
++ gctBOOL needResetShader = gcvFALSE;
++
++ gcmkHEADER_ARG("Hardware=0x%x Context=0x%x", Hardware, Context);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_OBJECT(Context, gcvOBJ_CONTEXT);
++
++ chipModel = Hardware->identity.chipModel;
++ chipRevision = Hardware->identity.chipRevision;
++ if (chipModel == gcv2000 || (chipModel == gcv2100 && chipRevision == 0x5118))
++ {
++ needResetShader = gcvTRUE;
++ }
++
++ /* Read the counters. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00438,
++ &profiler->gpuCyclesCounter));
++ gcmkUPDATE_PROFILE_DATA(gpuCyclesCounter);
++
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00078,
++ &profiler->gpuTotalCyclesCounter));
++ gcmkUPDATE_PROFILE_DATA(gpuTotalCyclesCounter);
++
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0007C,
++ &profiler->gpuIdleCyclesCounter));
++ gcmkUPDATE_PROFILE_DATA(gpuIdleCyclesCounter);
++
++ /* Read clock control register. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ &clock));
++
++ profiler->gpuTotalRead64BytesPerFrame = 0;
++ profiler->gpuTotalWrite64BytesPerFrame = 0;
++ profiler->pe_pixel_count_killed_by_color_pipe = 0;
++ profiler->pe_pixel_count_killed_by_depth_pipe = 0;
++ profiler->pe_pixel_count_drawn_by_color_pipe = 0;
++ profiler->pe_pixel_count_drawn_by_depth_pipe = 0;
++
++ /* Walk through all avaiable pixel pipes. */
++ for (i = 0; i < Hardware->identity.pixelPipes; ++i)
++ {
++ /* Select proper pipe. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ ((((gctUINT32) (clock)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:20) - (0 ? 23:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:20) - (0 ? 23:20) + 1))))))) << (0 ? 23:20))) | (((gctUINT32) ((gctUINT32) (i) & ((gctUINT32) ((((1 ? 23:20) - (0 ? 23:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:20) - (0 ? 23:20) + 1))))))) << (0 ? 23:20)))));
++
++ /* BW */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00040,
++ &totalRead));
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00044,
++ &totalWrite));
++
++ profiler->gpuTotalRead64BytesPerFrame += totalRead;
++ profiler->gpuTotalWrite64BytesPerFrame += totalWrite;
++ gcmkUPDATE_PROFILE_DATA(gpuTotalRead64BytesPerFrame);
++ gcmkUPDATE_PROFILE_DATA(gpuTotalWrite64BytesPerFrame);
++
++ /* PE */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))));gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00454, &colorKilled));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))));gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00454, &depthKilled));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (2) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))));gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00454, &colorDrawn));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (3) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))));gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00454, &depthDrawn));
++
++ profiler->pe_pixel_count_killed_by_color_pipe += colorKilled;
++ profiler->pe_pixel_count_killed_by_depth_pipe += depthKilled;
++ profiler->pe_pixel_count_drawn_by_color_pipe += colorDrawn;
++ profiler->pe_pixel_count_drawn_by_depth_pipe += depthDrawn;
++ gcmkUPDATE_PROFILE_DATA(pe_pixel_count_killed_by_color_pipe);
++ gcmkUPDATE_PROFILE_DATA(pe_pixel_count_killed_by_depth_pipe);
++ gcmkUPDATE_PROFILE_DATA(pe_pixel_count_drawn_by_color_pipe);
++ gcmkUPDATE_PROFILE_DATA(pe_pixel_count_drawn_by_depth_pipe);
++ }
++
++ /* Reset clock control register. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ clock));
++
++
++ /* Reset counters. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x0003C, 1));
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x0003C, 0));
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00438, 0));
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00078, 0));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))
++));
++
++ /* SH */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (7) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->ps_inst_counter));
++ if (needResetShader)
++ {
++ temp = profiler->ps_inst_counter;
++ profiler->ps_inst_counter = CalcDelta(temp, Context->prevPSInstCount);
++ Context->prevPSInstCount = temp;
++ }
++ gcmkUPDATE_PROFILE_DATA(ps_inst_counter);
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (8) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->rendered_pixel_counter));
++ if (needResetShader)
++ {
++ temp = profiler->rendered_pixel_counter;
++ profiler->rendered_pixel_counter = CalcDelta(temp, Context->prevPSPixelCount);
++ Context->prevPSPixelCount = temp;
++ }
++ gcmkUPDATE_PROFILE_DATA(rendered_pixel_counter);
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (9) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->vs_inst_counter));
++ if (needResetShader)
++ {
++ temp = profiler->vs_inst_counter;
++ profiler->vs_inst_counter = CalcDelta(temp, Context->prevVSInstCount);
++ Context->prevVSInstCount = temp;
++ }
++ gcmkUPDATE_PROFILE_DATA(vs_inst_counter);
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (10) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->rendered_vertice_counter));
++ if (needResetShader)
++ {
++ temp = profiler->rendered_vertice_counter;
++ profiler->rendered_vertice_counter = CalcDelta(temp, Context->prevVSVertexCount);
++ Context->prevVSVertexCount = temp;
++ }
++ gcmkUPDATE_PROFILE_DATA(rendered_vertice_counter);
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (11) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->vtx_branch_inst_counter));
++ if (needResetShader)
++ {
++ temp = profiler->vtx_branch_inst_counter;
++ profiler->vtx_branch_inst_counter = CalcDelta(temp, Context->prevVSBranchInstCount);
++ Context->prevVSBranchInstCount = temp;
++ }
++ gcmkUPDATE_PROFILE_DATA(vtx_branch_inst_counter);
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (12) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->vtx_texld_inst_counter));
++ if (needResetShader)
++ {
++ temp = profiler->vtx_texld_inst_counter;
++ profiler->vtx_texld_inst_counter = CalcDelta(temp, Context->prevVSTexInstCount);
++ Context->prevVSTexInstCount = temp;
++ }
++ gcmkUPDATE_PROFILE_DATA(vtx_texld_inst_counter);
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (13) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->pxl_branch_inst_counter));
++ if (needResetShader)
++ {
++ temp = profiler->pxl_branch_inst_counter;
++ profiler->pxl_branch_inst_counter = CalcDelta(temp, Context->prevPSBranchInstCount);
++ Context->prevPSBranchInstCount = temp;
++ }
++ gcmkUPDATE_PROFILE_DATA(pxl_branch_inst_counter);
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (14) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->pxl_texld_inst_counter));
++ if (needResetShader)
++ {
++ temp = profiler->pxl_texld_inst_counter;
++ profiler->pxl_texld_inst_counter = CalcDelta(temp, Context->prevPSTexInstCount);
++ Context->prevPSTexInstCount = temp;
++ }
++ gcmkUPDATE_PROFILE_DATA(pxl_texld_inst_counter);
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24)))
++));
++
++ /* PA */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (3) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_input_vtx_counter));
++ gcmkUPDATE_PROFILE_DATA(pa_input_vtx_counter);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (4) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_input_prim_counter));
++ gcmkUPDATE_PROFILE_DATA(pa_input_prim_counter);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (5) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_output_prim_counter));
++ gcmkUPDATE_PROFILE_DATA(pa_output_prim_counter);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (6) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_depth_clipped_counter));
++ gcmkUPDATE_PROFILE_DATA(pa_depth_clipped_counter);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (7) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_trivial_rejected_counter));
++ gcmkUPDATE_PROFILE_DATA(pa_trivial_rejected_counter);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (8) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_culled_counter));
++ gcmkUPDATE_PROFILE_DATA(pa_culled_counter);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0)))
++));
++
++ /* SE */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00464, &profiler->se_culled_triangle_count));
++ gcmkUPDATE_PROFILE_DATA(se_culled_triangle_count);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00464, &profiler->se_culled_lines_count));
++ gcmkUPDATE_PROFILE_DATA(se_culled_lines_count);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8)))
++));
++
++ /* RA */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_valid_pixel_count));
++ gcmkUPDATE_PROFILE_DATA(ra_valid_pixel_count);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_total_quad_count));
++ gcmkUPDATE_PROFILE_DATA(ra_total_quad_count);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (2) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_valid_quad_count_after_early_z));
++ gcmkUPDATE_PROFILE_DATA(ra_valid_quad_count_after_early_z);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (3) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_total_primitive_count));
++ gcmkUPDATE_PROFILE_DATA(ra_total_primitive_count);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (9) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_pipe_cache_miss_counter));
++ gcmkUPDATE_PROFILE_DATA(ra_pipe_cache_miss_counter);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (10) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_prefetch_cache_miss_counter));
++ gcmkUPDATE_PROFILE_DATA(ra_prefetch_cache_miss_counter);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))
++));
++
++ /* TX */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_total_bilinear_requests));
++ gcmkUPDATE_PROFILE_DATA(tx_total_bilinear_requests);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_total_trilinear_requests));
++ gcmkUPDATE_PROFILE_DATA(tx_total_trilinear_requests);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (2) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_total_discarded_texture_requests));
++ gcmkUPDATE_PROFILE_DATA(tx_total_discarded_texture_requests);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (3) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_total_texture_requests));
++ gcmkUPDATE_PROFILE_DATA(tx_total_texture_requests);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (5) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_mem_read_count));
++ gcmkUPDATE_PROFILE_DATA(tx_mem_read_count);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (6) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_mem_read_in_8B_count));
++ gcmkUPDATE_PROFILE_DATA(tx_mem_read_in_8B_count);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (7) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_cache_miss_count));
++ gcmkUPDATE_PROFILE_DATA(tx_cache_miss_count);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (8) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_cache_hit_texel_count));
++ gcmkUPDATE_PROFILE_DATA(tx_cache_hit_texel_count);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (9) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_cache_miss_texel_count));
++ gcmkUPDATE_PROFILE_DATA(tx_cache_miss_texel_count);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24)))
++));
++
++ /* MC */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00468, &profiler->mc_total_read_req_8B_from_pipeline));
++ gcmkUPDATE_PROFILE_DATA(mc_total_read_req_8B_from_pipeline);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (2) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00468, &profiler->mc_total_read_req_8B_from_IP));
++ gcmkUPDATE_PROFILE_DATA(mc_total_read_req_8B_from_IP);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (3) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00468, &profiler->mc_total_write_req_8B_from_pipeline));
++ gcmkUPDATE_PROFILE_DATA(mc_total_write_req_8B_from_pipeline);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0)))
++));
++
++ /* HI */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0046C, &profiler->hi_axi_cycles_read_request_stalled));
++ gcmkUPDATE_PROFILE_DATA(hi_axi_cycles_read_request_stalled);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0046C, &profiler->hi_axi_cycles_write_request_stalled));
++ gcmkUPDATE_PROFILE_DATA(hi_axi_cycles_write_request_stalled);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (2) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0046C, &profiler->hi_axi_cycles_write_data_stalled));
++ gcmkUPDATE_PROFILE_DATA(hi_axi_cycles_write_data_stalled);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8)))
++));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++#endif
++
++
++#if VIVANTE_PROFILER_NEW
++gceSTATUS
++gckHARDWARE_InitProfiler(
++ IN gckHARDWARE Hardware
++ )
++{
++ gceSTATUS status;
++ gctUINT32 control;
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ &control));
++ /* Enable debug register. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 11:11) - (0 ? 11:11) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:11) - (0 ? 11:11) + 1))))))) << (0 ? 11:11))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 11:11) - (0 ? 11:11) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:11) - (0 ? 11:11) + 1))))))) << (0 ? 11:11)))));
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++#endif
++
++static gceSTATUS
++_ResetGPU(
++ IN gckHARDWARE Hardware,
++ IN gckOS Os,
++ IN gceCORE Core
++ )
++{
++ gctUINT32 control, idle;
++ gceSTATUS status;
++
++ for (;;)
++ {
++ /* Disable clock gating. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ Core,
++ Hardware->powerBaseAddress +
++ 0x00104,
++ 0x00000000));
++
++ control = ((((gctUINT32) (0x01590880)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 17:17) - (0 ? 17:17) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 17:17) - (0 ? 17:17) + 1))))))) << (0 ? 17:17))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 17:17) - (0 ? 17:17) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 17:17) - (0 ? 17:17) + 1))))))) << (0 ? 17:17)));
++
++ /* Disable pulse-eater. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ Core,
++ 0x0010C,
++ control));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ Core,
++ 0x0010C,
++ ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)))));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ Core,
++ 0x0010C,
++ control));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ Core,
++ 0x00000,
++ ((((gctUINT32) (0x00000900)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9)))));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ Core,
++ 0x00000,
++ 0x00000900));
++
++ /* Wait for clock being stable. */
++ gcmkONERROR(gckOS_Delay(Os, 1));
++
++ /* Isolate the GPU. */
++ control = ((((gctUINT32) (0x00000900)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19)));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ Core,
++ 0x00000,
++ control));
++
++ /* Set soft reset. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ Core,
++ 0x00000,
++ ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12)))));
++
++ /* Wait for reset. */
++ gcmkONERROR(gckOS_Delay(Os, 1));
++
++ /* Reset soft reset bit. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ Core,
++ 0x00000,
++ ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12)))));
++
++ /* Reset GPU isolation. */
++ control = ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19)));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ Core,
++ 0x00000,
++ control));
++
++ /* Read idle register. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Os,
++ Core,
++ 0x00004,
++ &idle));
++
++ if ((((((gctUINT32) (idle)) >> (0 ? 0:0)) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1)))))) ) == 0)
++ {
++ continue;
++ }
++
++#if gcdMULTI_GPU > 1
++ if (Core == gcvCORE_MAJOR)
++ {
++ /* Read idle register. */
++ gcmkONERROR(gckOS_ReadRegisterByCoreId(Os,
++ Core,
++ gcvCORE_3D_1_ID,
++ 0x00004,
++ &idle));
++
++ if ((((((gctUINT32) (idle)) >> (0 ? 0:0)) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1)))))) ) == 0)
++ {
++ continue;
++ }
++ }
++#endif
++ /* Read reset register. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Os,
++ Core,
++ 0x00000,
++ &control));
++
++ if (((((((gctUINT32) (control)) >> (0 ? 16:16)) & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1)))))) ) == 0)
++ || ((((((gctUINT32) (control)) >> (0 ? 17:17)) & ((gctUINT32) ((((1 ? 17:17) - (0 ? 17:17) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 17:17) - (0 ? 17:17) + 1)))))) ) == 0)
++ )
++ {
++ continue;
++ }
++
++#if gcdMULTI_GPU > 1
++ if (Core == gcvCORE_MAJOR)
++ {
++ /* Read reset register. */
++ gcmkONERROR(gckOS_ReadRegisterByCoreId(Os,
++ Core,
++ gcvCORE_3D_1_ID,
++ 0x00000,
++ &control));
++
++ if (((((((gctUINT32) (control)) >> (0 ? 16:16)) & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1)))))) ) == 0)
++ || ((((((gctUINT32) (control)) >> (0 ? 17:17)) & ((gctUINT32) ((((1 ? 17:17) - (0 ? 17:17) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 17:17) - (0 ? 17:17) + 1)))))) ) == 0)
++ )
++ {
++ continue;
++ }
++ }
++#endif
++ /* GPU is idle. */
++ break;
++ }
++
++ /* Success. */
++ return gcvSTATUS_OK;
++
++OnError:
++
++ /* Return the error. */
++ return status;
++}
++
++gceSTATUS
++gckHARDWARE_Reset(
++ IN gckHARDWARE Hardware
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_OBJECT(Hardware->kernel, gcvOBJ_KERNEL);
++
++ /* Hardware reset. */
++ status = gckOS_ResetGPU(Hardware->os, Hardware->core);
++
++ if (gcmIS_ERROR(status))
++ {
++ if (Hardware->identity.chipRevision < 0x4600)
++ {
++ /* Not supported - we need the isolation bit. */
++ gcmkONERROR(gcvSTATUS_NOT_SUPPORTED);
++ }
++
++ /* Soft reset. */
++ gcmkONERROR(_ResetGPU(Hardware, Hardware->os, Hardware->core));
++ }
++
++ /* Initialize hardware. */
++ gcmkONERROR(gckHARDWARE_InitializeHardware(Hardware));
++
++ /* Jump to address into which GPU should run if it doesn't stuck. */
++ gcmkONERROR(gckHARDWARE_Execute(Hardware, Hardware->kernel->restoreAddress, 16));
++
++ gcmkPRINT("[galcore]: recovery done");
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkPRINT("[galcore]: Hardware not reset successfully, give up");
++
++ /* Return the error. */
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckHARDWARE_GetBaseAddress(
++ IN gckHARDWARE Hardware,
++ OUT gctUINT32_PTR BaseAddress
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(BaseAddress != gcvNULL);
++
++ /* Test if we have a new Memory Controller. */
++ if (((((gctUINT32) (Hardware->identity.chipMinorFeatures)) >> (0 ? 22:22) & ((gctUINT32) ((((1 ? 22:22) - (0 ? 22:22) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 22:22) - (0 ? 22:22) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 22:22) - (0 ? 22:22) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 22:22) - (0 ? 22:22) + 1))))))))
++ {
++ /* No base address required. */
++ *BaseAddress = 0;
++ }
++ else
++ {
++ /* Get the base address from the OS. */
++ gcmkONERROR(gckOS_GetBaseAddress(Hardware->os, BaseAddress));
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*BaseAddress=0x%08x", *BaseAddress);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckHARDWARE_NeedBaseAddress(
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 State,
++ OUT gctBOOL_PTR NeedBase
++ )
++{
++ gctBOOL need = gcvFALSE;
++
++ gcmkHEADER_ARG("Hardware=0x%x State=0x%08x", Hardware, State);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(NeedBase != gcvNULL);
++
++ /* Make sure this is a load state. */
++ if (((((gctUINT32) (State)) >> (0 ? 31:27) & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1)))))) == (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))))
++ {
++#if gcdENABLE_3D
++ /* Get the state address. */
++ switch ((((((gctUINT32) (State)) >> (0 ? 15:0)) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1)))))) ))
++ {
++ case 0x0596:
++ case 0x0597:
++ case 0x0599:
++ case 0x059A:
++ case 0x05A9:
++ /* These states need a TRUE physical address. */
++ need = gcvTRUE;
++ break;
++ }
++#else
++ /* 2D addresses don't need a base address. */
++#endif
++ }
++
++ /* Return the flag. */
++ *NeedBase = need;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*NeedBase=%d", *NeedBase);
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckHARDWARE_SetIsrManager(
++ IN gckHARDWARE Hardware,
++ IN gctISRMANAGERFUNC StartIsr,
++ IN gctISRMANAGERFUNC StopIsr,
++ IN gctPOINTER Context
++ )
++{
++ gceSTATUS status = gcvSTATUS_OK;
++
++ gcmkHEADER_ARG("Hardware=0x%x, StartIsr=0x%x, StopIsr=0x%x, Context=0x%x",
++ Hardware, StartIsr, StopIsr, Context);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ if (StartIsr == gcvNULL ||
++ StopIsr == gcvNULL ||
++ Context == gcvNULL)
++ {
++ status = gcvSTATUS_INVALID_ARGUMENT;
++
++ gcmkFOOTER();
++ return status;
++ }
++
++ Hardware->startIsr = StartIsr;
++ Hardware->stopIsr = StopIsr;
++ Hardware->isrContext = Context;
++
++ /* Success. */
++ gcmkFOOTER();
++
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_Compose
++**
++** Start a composition.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to the gckHARDWARE object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckHARDWARE_Compose(
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 ProcessID,
++ IN gctPHYS_ADDR Physical,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Offset,
++ IN gctSIZE_T Size,
++ IN gctUINT8 EventID
++ )
++{
++#if gcdENABLE_3D
++ gceSTATUS status;
++ gctUINT32_PTR triggerState;
++
++ gcmkHEADER_ARG("Hardware=0x%x Physical=0x%x Logical=0x%x"
++ " Offset=%d Size=%d EventID=%d",
++ Hardware, Physical, Logical, Offset, Size, EventID);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(((Size + 8) & 63) == 0);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++
++ /* Program the trigger state. */
++ triggerState = (gctUINT32_PTR) ((gctUINT8_PTR) Logical + Offset + Size);
++ triggerState[0] = 0x0C03;
++ triggerState[1]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:4) - (0 ? 5:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:4) - (0 ? 5:4) + 1))))))) << (0 ? 5:4))) | (((gctUINT32) (0x3 & ((gctUINT32) ((((1 ? 5:4) - (0 ? 5:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:4) - (0 ? 5:4) + 1))))))) << (0 ? 5:4)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 8:8) - (0 ? 8:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:8) - (0 ? 8:8) + 1))))))) << (0 ? 8:8))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 8:8) - (0 ? 8:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:8) - (0 ? 8:8) + 1))))))) << (0 ? 8:8)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 24:24) - (0 ? 24:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 24:24) - (0 ? 24:24) + 1))))))) << (0 ? 24:24))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 24:24) - (0 ? 24:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 24:24) - (0 ? 24:24) + 1))))))) << (0 ? 24:24)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 20:16) - (0 ? 20:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:16) - (0 ? 20:16) + 1))))))) << (0 ? 20:16))) | (((gctUINT32) ((gctUINT32) (EventID) & ((gctUINT32) ((((1 ? 20:16) - (0 ? 20:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:16) - (0 ? 20:16) + 1))))))) << (0 ? 20:16)))
++ ;
++
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ /* Flush the cache for the wait/link. */
++ gcmkONERROR(gckOS_CacheClean(
++ Hardware->os, ProcessID, gcvNULL,
++ (gctUINT32)Physical, Logical, Offset + Size
++ ));
++#endif
++
++ /* Start composition. */
++ gcmkONERROR(gckOS_WriteRegisterEx(
++ Hardware->os, Hardware->core, 0x00554,
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0))) | (((gctUINT32) (0x3 & ((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0)))
++ ));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++#else
++ /* Return the status. */
++ return gcvSTATUS_NOT_SUPPORTED;
++#endif
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_IsFeatureAvailable
++**
++** Verifies whether the specified feature is available in hardware.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to an gckHARDWARE object.
++**
++** gceFEATURE Feature
++** Feature to be verified.
++*/
++gceSTATUS
++gckHARDWARE_IsFeatureAvailable(
++ IN gckHARDWARE Hardware,
++ IN gceFEATURE Feature
++ )
++{
++ gctBOOL available;
++
++ gcmkHEADER_ARG("Hardware=0x%x Feature=%d", Hardware, Feature);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Only features needed by common kernel logic added here. */
++ switch (Feature)
++ {
++ case gcvFEATURE_END_EVENT:
++ /*available = gcmVERIFYFIELDVALUE(Hardware->identity.chipMinorFeatures2,
++ GC_MINOR_FEATURES2, END_EVENT, AVAILABLE
++ );*/
++ available = gcvFALSE;
++ break;
++
++ case gcvFEATURE_MC20:
++ available = ((((gctUINT32) (Hardware->identity.chipMinorFeatures)) >> (0 ? 22:22) & ((gctUINT32) ((((1 ? 22:22) - (0 ? 22:22) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 22:22) - (0 ? 22:22) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 22:22) - (0 ? 22:22) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 22:22) - (0 ? 22:22) + 1)))))));
++ break;
++
++ case gcvFEATURE_EARLY_Z:
++ available = ((((gctUINT32) (Hardware->identity.chipFeatures)) >> (0 ? 16:16) & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1)))))) == (0x0 & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1)))))));
++ break;
++
++ case gcvFEATURE_HZ:
++ available = ((((gctUINT32) (Hardware->identity.chipMinorFeatures)) >> (0 ? 27:27) & ((gctUINT32) ((((1 ? 27:27) - (0 ? 27:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:27) - (0 ? 27:27) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 27:27) - (0 ? 27:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:27) - (0 ? 27:27) + 1)))))));
++ break;
++
++ case gcvFEATURE_NEW_HZ:
++ available = ((((gctUINT32) (Hardware->identity.chipMinorFeatures3)) >> (0 ? 26:26) & ((gctUINT32) ((((1 ? 26:26) - (0 ? 26:26) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 26:26) - (0 ? 26:26) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 26:26) - (0 ? 26:26) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 26:26) - (0 ? 26:26) + 1)))))));
++ break;
++
++ case gcvFEATURE_FAST_MSAA:
++ available = ((((gctUINT32) (Hardware->identity.chipMinorFeatures3)) >> (0 ? 8:8) & ((gctUINT32) ((((1 ? 8:8) - (0 ? 8:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:8) - (0 ? 8:8) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 8:8) - (0 ? 8:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:8) - (0 ? 8:8) + 1)))))));
++ break;
++
++ case gcvFEATURE_SMALL_MSAA:
++ available = ((((gctUINT32) (Hardware->identity.chipMinorFeatures4)) >> (0 ? 18:18) & ((gctUINT32) ((((1 ? 18:18) - (0 ? 18:18) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 18:18) - (0 ? 18:18) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 18:18) - (0 ? 18:18) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 18:18) - (0 ? 18:18) + 1)))))));
++ break;
++
++ case gcvFEATURE_DYNAMIC_FREQUENCY_SCALING:
++ /* This feature doesn't apply for 2D cores. */
++ available = ((((gctUINT32) (Hardware->identity.chipMinorFeatures2)) >> (0 ? 14:14) & ((gctUINT32) ((((1 ? 14:14) - (0 ? 14:14) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 14:14) - (0 ? 14:14) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 14:14) - (0 ? 14:14) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 14:14) - (0 ? 14:14) + 1)))))))
++ && ((((gctUINT32) (Hardware->identity.chipFeatures)) >> (0 ? 2:2) & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1)))))));
++
++ if (Hardware->identity.chipModel == gcv1000 &&
++ (Hardware->identity.chipRevision == 0x5039 ||
++ Hardware->identity.chipRevision == 0x5040))
++ {
++ available = gcvFALSE;
++ }
++ break;
++
++ case gcvFEATURE_ACE:
++ available = ((((gctUINT32) (Hardware->identity.chipMinorFeatures3)) >> (0 ? 18:18) & ((gctUINT32) ((((1 ? 18:18) - (0 ? 18:18) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 18:18) - (0 ? 18:18) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 18:18) - (0 ? 18:18) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 18:18) - (0 ? 18:18) + 1)))))));
++ break;
++
++ case gcvFEATURE_HALTI2:
++ available = ((((gctUINT32) (Hardware->identity.chipMinorFeatures4)) >> (0 ? 16:16) & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1)))))));
++ break;
++
++ case gcvFEATURE_PIPE_2D:
++ available = ((((gctUINT32) (Hardware->identity.chipFeatures)) >> (0 ? 9:9) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1)))))));
++ break;
++
++ case gcvFEATURE_PIPE_3D:
++#if gcdENABLE_3D
++ available = ((((gctUINT32) (Hardware->identity.chipFeatures)) >> (0 ? 2:2) & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1)))))));
++#else
++ available = gcvFALSE;
++#endif
++ break;
++
++ case gcvFEATURE_FC_FLUSH_STALL:
++ available = ((((gctUINT32) (Hardware->identity.chipMinorFeatures1)) >> (0 ? 31:31) & ((gctUINT32) ((((1 ? 31:31) - (0 ? 31:31) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:31) - (0 ? 31:31) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 31:31) - (0 ? 31:31) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:31) - (0 ? 31:31) + 1)))))));
++ break;
++
++ default:
++ gcmkFATAL("Invalid feature has been requested.");
++ available = gcvFALSE;
++ }
++
++ /* Return result. */
++ gcmkFOOTER_ARG("%d", available ? gcvSTATUS_TRUE : gcvSTATUS_FALSE);
++ return available ? gcvSTATUS_TRUE : gcvSTATUS_FALSE;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_DumpMMUException
++**
++** Dump the MMU debug info on an MMU exception.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckHARDWARE_DumpMMUException(
++ IN gckHARDWARE Hardware
++ )
++{
++ gctUINT32 mmu = 0;
++ gctUINT32 mmuStatus = 0;
++ gctUINT32 address = 0;
++ gctUINT32 i = 0;
++ gctUINT32 mtlb = 0;
++ gctUINT32 stlb = 0;
++ gctUINT32 offset = 0;
++#if gcdPROCESS_ADDRESS_SPACE
++ gcsDATABASE_PTR database;
++#endif
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ gcmkPRINT("GPU[%d](ChipModel=0x%x ChipRevision=0x%x):\n",
++ Hardware->core,
++ Hardware->identity.chipModel,
++ Hardware->identity.chipRevision);
++
++ gcmkPRINT("**************************\n");
++ gcmkPRINT("*** MMU ERROR DUMP ***\n");
++ gcmkPRINT("**************************\n");
++
++ gcmkVERIFY_OK(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00188,
++ &mmuStatus));
++
++ gcmkPRINT(" MMU status = 0x%08X\n", mmuStatus);
++
++ for (i = 0; i < 4; i += 1)
++ {
++ mmu = mmuStatus & 0xF;
++ mmuStatus >>= 4;
++
++ if (mmu == 0)
++ {
++ continue;
++ }
++
++ switch (mmu)
++ {
++ case 1:
++ gcmkPRINT(" MMU%d: slave not present\n", i);
++ break;
++
++ case 2:
++ gcmkPRINT(" MMU%d: page not present\n", i);
++ break;
++
++ case 3:
++ gcmkPRINT(" MMU%d: write violation\n", i);
++ break;
++
++ default:
++ gcmkPRINT(" MMU%d: unknown state\n", i);
++ }
++
++ gcmkVERIFY_OK(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00190 + i * 4,
++ &address));
++
++ mtlb = (address & gcdMMU_MTLB_MASK) >> gcdMMU_MTLB_SHIFT;
++ stlb = (address & gcdMMU_STLB_4K_MASK) >> gcdMMU_STLB_4K_SHIFT;
++ offset = address & gcdMMU_OFFSET_4K_MASK;
++
++ gcmkPRINT(" MMU%d: exception address = 0x%08X\n", i, address);
++
++ gcmkPRINT(" MTLB entry = %d\n", mtlb);
++
++ gcmkPRINT(" STLB entry = %d\n", stlb);
++
++ gcmkPRINT(" Offset = 0x%08X (%d)\n", offset, offset);
++
++ gckMMU_DumpPageTableEntry(Hardware->kernel->mmu, address);
++
++#if gcdPROCESS_ADDRESS_SPACE
++ for (i = 0; i < gcmCOUNTOF(Hardware->kernel->db->db); ++i)
++ {
++ for (database = Hardware->kernel->db->db[i];
++ database != gcvNULL;
++ database = database->next)
++ {
++ gcmkPRINT(" database [%d] :", database->processID);
++ gckMMU_DumpPageTableEntry(database->mmu, address);
++ }
++ }
++#endif
++ }
++
++ gckHARDWARE_DumpGPUState(Hardware);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_DumpGPUState
++**
++** Dump the GPU debug registers.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckHARDWARE_DumpGPUState(
++ IN gckHARDWARE Hardware
++ )
++{
++ static gctCONST_STRING _cmdState[] =
++ {
++ "PAR_IDLE_ST", "PAR_DEC_ST", "PAR_ADR0_ST", "PAR_LOAD0_ST",
++ "PAR_ADR1_ST", "PAR_LOAD1_ST", "PAR_3DADR_ST", "PAR_3DCMD_ST",
++ "PAR_3DCNTL_ST", "PAR_3DIDXCNTL_ST", "PAR_INITREQDMA_ST",
++ "PAR_DRAWIDX_ST", "PAR_DRAW_ST", "PAR_2DRECT0_ST", "PAR_2DRECT1_ST",
++ "PAR_2DDATA0_ST", "PAR_2DDATA1_ST", "PAR_WAITFIFO_ST", "PAR_WAIT_ST",
++ "PAR_LINK_ST", "PAR_END_ST", "PAR_STALL_ST"
++ };
++
++ static gctCONST_STRING _cmdDmaState[] =
++ {
++ "CMD_IDLE_ST", "CMD_START_ST", "CMD_REQ_ST", "CMD_END_ST"
++ };
++
++ static gctCONST_STRING _cmdFetState[] =
++ {
++ "FET_IDLE_ST", "FET_RAMVALID_ST", "FET_VALID_ST"
++ };
++
++ static gctCONST_STRING _reqDmaState[] =
++ {
++ "REQ_IDLE_ST", "REQ_WAITIDX_ST", "REQ_CAL_ST"
++ };
++
++ static gctCONST_STRING _calState[] =
++ {
++ "CAL_IDLE_ST", "CAL_LDADR_ST", "CAL_IDXCALC_ST"
++ };
++
++ static gctCONST_STRING _veReqState[] =
++ {
++ "VER_IDLE_ST", "VER_CKCACHE_ST", "VER_MISS_ST"
++ };
++
++ static gcsiDEBUG_REGISTERS _dbgRegs[] =
++ {
++ { "RA", 0x474, 16, 0x448, 16, 0x12344321 },
++ { "TX", 0x474, 24, 0x44C, 16, 0x12211221 },
++ { "FE", 0x470, 0, 0x450, 16, 0xBABEF00D },
++ { "PE", 0x470, 16, 0x454, 16, 0xBABEF00D },
++ { "DE", 0x470, 8, 0x458, 16, 0xBABEF00D },
++ { "SH", 0x470, 24, 0x45C, 16, 0xDEADBEEF },
++ { "PA", 0x474, 0, 0x460, 16, 0x0000AAAA },
++ { "SE", 0x474, 8, 0x464, 16, 0x5E5E5E5E },
++ { "MC", 0x478, 0, 0x468, 16, 0x12345678 },
++ { "HI", 0x478, 8, 0x46C, 16, 0xAAAAAAAA }
++ };
++
++ static gctUINT32 _otherRegs[] =
++ {
++ 0x040, 0x044, 0x04C, 0x050, 0x054, 0x058, 0x05C, 0x060,
++ 0x43c, 0x440, 0x444, 0x414,
++ };
++
++ gceSTATUS status;
++ gckKERNEL kernel = gcvNULL;
++ gctUINT32 idle = 0, axi = 0;
++ gctUINT32 dmaAddress1 = 0, dmaAddress2 = 0;
++ gctUINT32 dmaState1 = 0, dmaState2 = 0;
++ gctUINT32 dmaLow = 0, dmaHigh = 0;
++ gctUINT32 cmdState = 0, cmdDmaState = 0, cmdFetState = 0;
++ gctUINT32 dmaReqState = 0, calState = 0, veReqState = 0;
++ gctUINT i;
++ gctUINT pipe = 0, pixelPipes = 0;
++ gctUINT32 control = 0, oldControl = 0;
++ gckOS os = Hardware->os;
++ gceCORE core = Hardware->core;
++
++ gcmkHEADER_ARG("Hardware=0x%X", Hardware);
++
++ kernel = Hardware->kernel;
++
++ gcmkPRINT_N(12, "GPU[%d](ChipModel=0x%x ChipRevision=0x%x):\n",
++ core,
++ Hardware->identity.chipModel,
++ Hardware->identity.chipRevision);
++
++ pixelPipes = Hardware->identity.pixelPipes
++ ? Hardware->identity.pixelPipes
++ : 1;
++
++ /* Reset register values. */
++ idle = axi =
++ dmaState1 = dmaState2 =
++ dmaAddress1 = dmaAddress2 =
++ dmaLow = dmaHigh = 0;
++
++ /* Verify whether DMA is running. */
++ gcmkONERROR(_VerifyDMA(
++ os, core, &dmaAddress1, &dmaAddress2, &dmaState1, &dmaState2
++ ));
++
++ cmdState = dmaState2 & 0x1F;
++ cmdDmaState = (dmaState2 >> 8) & 0x03;
++ cmdFetState = (dmaState2 >> 10) & 0x03;
++ dmaReqState = (dmaState2 >> 12) & 0x03;
++ calState = (dmaState2 >> 14) & 0x03;
++ veReqState = (dmaState2 >> 16) & 0x03;
++
++ gcmkONERROR(gckOS_ReadRegisterEx(os, core, 0x004, &idle));
++ gcmkONERROR(gckOS_ReadRegisterEx(os, core, 0x00C, &axi));
++ gcmkONERROR(gckOS_ReadRegisterEx(os, core, 0x668, &dmaLow));
++ gcmkONERROR(gckOS_ReadRegisterEx(os, core, 0x66C, &dmaHigh));
++
++ gcmkPRINT_N(0, "**************************\n");
++ gcmkPRINT_N(0, "*** GPU STATE DUMP ***\n");
++ gcmkPRINT_N(0, "**************************\n");
++
++ gcmkPRINT_N(4, " axi = 0x%08X\n", axi);
++
++ gcmkPRINT_N(4, " idle = 0x%08X\n", idle);
++ if ((idle & 0x00000001) == 0) gcmkPRINT_N(0, " FE not idle\n");
++ if ((idle & 0x00000002) == 0) gcmkPRINT_N(0, " DE not idle\n");
++ if ((idle & 0x00000004) == 0) gcmkPRINT_N(0, " PE not idle\n");
++ if ((idle & 0x00000008) == 0) gcmkPRINT_N(0, " SH not idle\n");
++ if ((idle & 0x00000010) == 0) gcmkPRINT_N(0, " PA not idle\n");
++ if ((idle & 0x00000020) == 0) gcmkPRINT_N(0, " SE not idle\n");
++ if ((idle & 0x00000040) == 0) gcmkPRINT_N(0, " RA not idle\n");
++ if ((idle & 0x00000080) == 0) gcmkPRINT_N(0, " TX not idle\n");
++ if ((idle & 0x00000100) == 0) gcmkPRINT_N(0, " VG not idle\n");
++ if ((idle & 0x00000200) == 0) gcmkPRINT_N(0, " IM not idle\n");
++ if ((idle & 0x00000400) == 0) gcmkPRINT_N(0, " FP not idle\n");
++ if ((idle & 0x00000800) == 0) gcmkPRINT_N(0, " TS not idle\n");
++ if ((idle & 0x80000000) != 0) gcmkPRINT_N(0, " AXI low power mode\n");
++
++ if (
++ (dmaAddress1 == dmaAddress2)
++ && (dmaState1 == dmaState2)
++ )
++ {
++ gcmkPRINT_N(0, " DMA appears to be stuck at this address:\n");
++ gcmkPRINT_N(4, " 0x%08X\n", dmaAddress1);
++ }
++ else
++ {
++ if (dmaAddress1 == dmaAddress2)
++ {
++ gcmkPRINT_N(0, " DMA address is constant, but state is changing:\n");
++ gcmkPRINT_N(4, " 0x%08X\n", dmaState1);
++ gcmkPRINT_N(4, " 0x%08X\n", dmaState2);
++ }
++ else
++ {
++ gcmkPRINT_N(0, " DMA is running; known addresses are:\n");
++ gcmkPRINT_N(4, " 0x%08X\n", dmaAddress1);
++ gcmkPRINT_N(4, " 0x%08X\n", dmaAddress2);
++ }
++ }
++
++ gcmkPRINT_N(4, " dmaLow = 0x%08X\n", dmaLow);
++ gcmkPRINT_N(4, " dmaHigh = 0x%08X\n", dmaHigh);
++ gcmkPRINT_N(4, " dmaState = 0x%08X\n", dmaState2);
++ gcmkPRINT_N(8, " command state = %d (%s)\n", cmdState, _cmdState [cmdState]);
++ gcmkPRINT_N(8, " command DMA state = %d (%s)\n", cmdDmaState, _cmdDmaState[cmdDmaState]);
++ gcmkPRINT_N(8, " command fetch state = %d (%s)\n", cmdFetState, _cmdFetState[cmdFetState]);
++ gcmkPRINT_N(8, " DMA request state = %d (%s)\n", dmaReqState, _reqDmaState[dmaReqState]);
++ gcmkPRINT_N(8, " cal state = %d (%s)\n", calState, _calState [calState]);
++ gcmkPRINT_N(8, " VE request state = %d (%s)\n", veReqState, _veReqState [veReqState]);
++
++ /* Record control. */
++ gckOS_ReadRegisterEx(os, core, 0x0, &oldControl);
++
++ for (pipe = 0; pipe < pixelPipes; pipe++)
++ {
++ gcmkPRINT_N(4, " Debug registers of pipe[%d]:\n", pipe);
++
++ /* Switch pipe. */
++ gcmkONERROR(gckOS_ReadRegisterEx(os, core, 0x0, &control));
++ control &= ~(0xF << 20);
++ control |= (pipe << 20);
++ gcmkONERROR(gckOS_WriteRegisterEx(os, core, 0x0, control));
++
++ for (i = 0; i < gcmCOUNTOF(_dbgRegs); i += 1)
++ {
++ gcmkONERROR(_DumpDebugRegisters(os, core, &_dbgRegs[i]));
++ }
++
++ gcmkPRINT_N(0, " Other Registers:\n");
++ for (i = 0; i < gcmCOUNTOF(_otherRegs); i += 1)
++ {
++ gctUINT32 read;
++ gcmkONERROR(gckOS_ReadRegisterEx(os, core, _otherRegs[i], &read));
++ gcmkPRINT_N(12, " [0x%04X] 0x%08X\n", _otherRegs[i], read);
++ }
++ }
++
++ if (kernel->hardware->identity.chipFeatures & (1 << 4))
++ {
++ gctUINT32 read0, read1, write;
++
++ read0 = read1 = write = 0;
++
++ gcmkONERROR(gckOS_ReadRegisterEx(os, core, 0x43C, &read0));
++ gcmkONERROR(gckOS_ReadRegisterEx(os, core, 0x440, &read1));
++ gcmkONERROR(gckOS_ReadRegisterEx(os, core, 0x444, &write));
++
++ gcmkPRINT_N(4, " read0 = 0x%08X\n", read0);
++ gcmkPRINT_N(4, " read1 = 0x%08X\n", read1);
++ gcmkPRINT_N(4, " write = 0x%08X\n", write);
++ }
++
++ /* Restore control. */
++ gcmkONERROR(gckOS_WriteRegisterEx(os, core, 0x0, oldControl));
++
++ /* dump stack. */
++ gckOS_DumpCallStack(os);
++
++OnError:
++
++ /* Return the error. */
++ gcmkFOOTER();
++ return status;
++}
++
++static gceSTATUS
++gckHARDWARE_ReadPerformanceRegister(
++ IN gckHARDWARE Hardware,
++ IN gctUINT PerformanceAddress,
++ IN gctUINT IndexAddress,
++ IN gctUINT IndexShift,
++ IN gctUINT Index,
++ OUT gctUINT32_PTR Value
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Hardware=0x%x PerformanceAddress=0x%x IndexAddress=0x%x "
++ "IndexShift=%u Index=%u",
++ Hardware, PerformanceAddress, IndexAddress, IndexShift,
++ Index);
++
++ /* Write the index. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ IndexAddress,
++ Index << IndexShift));
++
++ /* Read the register. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ PerformanceAddress,
++ Value));
++
++ /* Test for reset. */
++ if (Index == 15)
++ {
++ /* Index another register to get out of reset. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, IndexAddress, 0));
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Value=0x%x", *Value);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckHARDWARE_GetFrameInfo(
++ IN gckHARDWARE Hardware,
++ OUT gcsHAL_FRAME_INFO * FrameInfo
++ )
++{
++ gceSTATUS status;
++ gctUINT i, clock;
++ gcsHAL_FRAME_INFO info;
++#if gcdFRAME_DB_RESET
++ gctUINT reset;
++#endif
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Get profile tick. */
++ gcmkONERROR(gckOS_GetProfileTick(&info.ticks));
++
++ /* Read SH counters and reset them. */
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x0045C,
++ 0x00470,
++ 24,
++ 4,
++ &info.shaderCycles));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x0045C,
++ 0x00470,
++ 24,
++ 9,
++ &info.vsInstructionCount));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x0045C,
++ 0x00470,
++ 24,
++ 12,
++ &info.vsTextureCount));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x0045C,
++ 0x00470,
++ 24,
++ 7,
++ &info.psInstructionCount));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x0045C,
++ 0x00470,
++ 24,
++ 14,
++ &info.psTextureCount));
++#if gcdFRAME_DB_RESET
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x0045C,
++ 0x00470,
++ 24,
++ 15,
++ &reset));
++#endif
++
++ /* Read PA counters and reset them. */
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00460,
++ 0x00474,
++ 0,
++ 3,
++ &info.vertexCount));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00460,
++ 0x00474,
++ 0,
++ 4,
++ &info.primitiveCount));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00460,
++ 0x00474,
++ 0,
++ 7,
++ &info.rejectedPrimitives));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00460,
++ 0x00474,
++ 0,
++ 8,
++ &info.culledPrimitives));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00460,
++ 0x00474,
++ 0,
++ 6,
++ &info.clippedPrimitives));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00460,
++ 0x00474,
++ 0,
++ 5,
++ &info.outPrimitives));
++#if gcdFRAME_DB_RESET
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00460,
++ 0x00474,
++ 0,
++ 15,
++ &reset));
++#endif
++
++ /* Read RA counters and reset them. */
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00448,
++ 0x00474,
++ 16,
++ 3,
++ &info.inPrimitives));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00448,
++ 0x00474,
++ 16,
++ 11,
++ &info.culledQuadCount));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00448,
++ 0x00474,
++ 16,
++ 1,
++ &info.totalQuadCount));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00448,
++ 0x00474,
++ 16,
++ 2,
++ &info.quadCount));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00448,
++ 0x00474,
++ 16,
++ 0,
++ &info.totalPixelCount));
++#if gcdFRAME_DB_RESET
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00448,
++ 0x00474,
++ 16,
++ 15,
++ &reset));
++#endif
++
++ /* Read TX counters and reset them. */
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x0044C,
++ 0x00474,
++ 24,
++ 0,
++ &info.bilinearRequests));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x0044C,
++ 0x00474,
++ 24,
++ 1,
++ &info.trilinearRequests));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x0044C,
++ 0x00474,
++ 24,
++ 8,
++ &info.txHitCount));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x0044C,
++ 0x00474,
++ 24,
++ 9,
++ &info.txMissCount));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x0044C,
++ 0x00474,
++ 24,
++ 6,
++ &info.txBytes8));
++#if gcdFRAME_DB_RESET
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x0044C,
++ 0x00474,
++ 24,
++ 15,
++ &reset));
++#endif
++
++ /* Read clock control register. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ &clock));
++
++ /* Walk through all avaiable pixel pipes. */
++ for (i = 0; i < Hardware->identity.pixelPipes; ++i)
++ {
++ /* Select proper pipe. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ ((((gctUINT32) (clock)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:20) - (0 ? 23:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:20) - (0 ? 23:20) + 1))))))) << (0 ? 23:20))) | (((gctUINT32) ((gctUINT32) (i) & ((gctUINT32) ((((1 ? 23:20) - (0 ? 23:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:20) - (0 ? 23:20) + 1))))))) << (0 ? 23:20)))));
++
++ /* Read cycle registers. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00078,
++ &info.cycles[i]));
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0007C,
++ &info.idleCycles[i]));
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00438,
++ &info.mcCycles[i]));
++
++ /* Read bandwidth registers. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0005C,
++ &info.readRequests[i]));
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00040,
++ &info.readBytes8[i]));
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00050,
++ &info.writeRequests[i]));
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00044,
++ &info.writeBytes8[i]));
++
++ /* Read PE counters. */
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00454,
++ 0x00470,
++ 16,
++ 0,
++ &info.colorKilled[i]));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00454,
++ 0x00470,
++ 16,
++ 2,
++ &info.colorDrawn[i]));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00454,
++ 0x00470,
++ 16,
++ 1,
++ &info.depthKilled[i]));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00454,
++ 0x00470,
++ 16,
++ 3,
++ &info.depthDrawn[i]));
++ }
++
++ /* Zero out remaning reserved counters. */
++ for (; i < 8; ++i)
++ {
++ info.readBytes8[i] = 0;
++ info.writeBytes8[i] = 0;
++ info.cycles[i] = 0;
++ info.idleCycles[i] = 0;
++ info.mcCycles[i] = 0;
++ info.readRequests[i] = 0;
++ info.writeRequests[i] = 0;
++ info.colorKilled[i] = 0;
++ info.colorDrawn[i] = 0;
++ info.depthKilled[i] = 0;
++ info.depthDrawn[i] = 0;
++ }
++
++ /* Reset clock control register. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ clock));
++
++ /* Reset cycle and bandwidth counters. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0003C,
++ 1));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0003C,
++ 0));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00078,
++ 0));
++
++#if gcdFRAME_DB_RESET
++ /* Reset PE counters. */
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00454,
++ 0x00470,
++ 16,
++ 15,
++ &reset));
++#endif
++
++ /* Copy to user. */
++ gcmkONERROR(gckOS_CopyToUserData(Hardware->os,
++ &info,
++ FrameInfo,
++ gcmSIZEOF(info)));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++#if gcdDVFS
++#define READ_FROM_EATER1 0
++
++gceSTATUS
++gckHARDWARE_QueryLoad(
++ IN gckHARDWARE Hardware,
++ OUT gctUINT32 * Load
++ )
++{
++ gctUINT32 debug1;
++ gceSTATUS status;
++ gcmkHEADER_ARG("Hardware=0x%X", Hardware);
++
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(Load != gcvNULL);
++
++ gckOS_AcquireMutex(Hardware->os, Hardware->powerMutex, gcvINFINITE);
++
++ if (Hardware->chipPowerState == gcvPOWER_ON)
++ {
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00110,
++ Load));
++#if READ_FROM_EATER1
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00134,
++ Load));
++#endif
++
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00114,
++ &debug1));
++
++ /* Patch result of 0x110 with result of 0x114. */
++ if ((debug1 & 0xFF) == 1)
++ {
++ *Load &= ~0xFF;
++ *Load |= 1;
++ }
++
++ if (((debug1 & 0xFF00) >> 8) == 1)
++ {
++ *Load &= ~(0xFF << 8);
++ *Load |= 1 << 8;
++ }
++
++ if (((debug1 & 0xFF0000) >> 16) == 1)
++ {
++ *Load &= ~(0xFF << 16);
++ *Load |= 1 << 16;
++ }
++
++ if (((debug1 & 0xFF000000) >> 24) == 1)
++ {
++ *Load &= ~(0xFF << 24);
++ *Load |= 1 << 24;
++ }
++ }
++ else
++ {
++ status = gcvSTATUS_INVALID_REQUEST;
++ }
++
++OnError:
++
++ gckOS_ReleaseMutex(Hardware->os, Hardware->powerMutex);
++
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckHARDWARE_SetDVFSPeroid(
++ IN gckHARDWARE Hardware,
++ OUT gctUINT32 Frequency
++ )
++{
++ gceSTATUS status;
++ gctUINT32 period;
++ gctUINT32 eater;
++
++#if READ_FROM_EATER1
++ gctUINT32 period1;
++ gctUINT32 eater1;
++#endif
++
++ gcmkHEADER_ARG("Hardware=0x%X Frequency=%d", Hardware, Frequency);
++
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ period = 0;
++
++ while((64 << period) < (gcdDVFS_ANAYLSE_WINDOW * Frequency * 1000) )
++ {
++ period++;
++ }
++
++#if READ_FROM_EATER1
++ /*
++ * Peroid = F * 1000 * 1000 / (60 * 16 * 1024);
++ */
++ period1 = Frequency * 6250 / 6114;
++#endif
++
++ gckOS_AcquireMutex(Hardware->os, Hardware->powerMutex, gcvINFINITE);
++
++ if (Hardware->chipPowerState == gcvPOWER_ON)
++ {
++ /* Get current configure. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0010C,
++ &eater));
++
++ /* Change peroid. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0010C,
++ ((((gctUINT32) (eater)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (period) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8)))));
++
++#if READ_FROM_EATER1
++ /* Config eater1. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00130,
++ &eater1));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00130,
++ ((((gctUINT32) (eater1)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:16) - (0 ? 31:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:16) - (0 ? 31:16) + 1))))))) << (0 ? 31:16))) | (((gctUINT32) ((gctUINT32) (period1) & ((gctUINT32) ((((1 ? 31:16) - (0 ? 31:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:16) - (0 ? 31:16) + 1))))))) << (0 ? 31:16)))));
++#endif
++ }
++ else
++ {
++ status = gcvSTATUS_INVALID_REQUEST;
++ }
++
++OnError:
++ gckOS_ReleaseMutex(Hardware->os, Hardware->powerMutex);
++
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckHARDWARE_InitDVFS(
++ IN gckHARDWARE Hardware
++ )
++{
++ gceSTATUS status;
++ gctUINT32 data;
++
++ gcmkHEADER_ARG("Hardware=0x%X", Hardware);
++
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0010C,
++ &data));
++
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) << (0 ? 16:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) << (0 ? 16:16)));
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 18:18) - (0 ? 18:18) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 18:18) - (0 ? 18:18) + 1))))))) << (0 ? 18:18))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 18:18) - (0 ? 18:18) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 18:18) - (0 ? 18:18) + 1))))))) << (0 ? 18:18)));
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19)));
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 20:20) - (0 ? 20:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:20) - (0 ? 20:20) + 1))))))) << (0 ? 20:20))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 20:20) - (0 ? 20:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:20) - (0 ? 20:20) + 1))))))) << (0 ? 20:20)));
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:23) - (0 ? 23:23) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:23) - (0 ? 23:23) + 1))))))) << (0 ? 23:23))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 23:23) - (0 ? 23:23) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:23) - (0 ? 23:23) + 1))))))) << (0 ? 23:23)));
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 22:22) - (0 ? 22:22) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 22:22) - (0 ? 22:22) + 1))))))) << (0 ? 22:22))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 22:22) - (0 ? 22:22) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 22:22) - (0 ? 22:22) + 1))))))) << (0 ? 22:22)));
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "DVFS Configure=0x%X",
++ data);
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0010C,
++ data));
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++#endif
++
++/*******************************************************************************
++**
++** gckHARDWARE_PrepareFunctions
++**
++** Generate command buffer snippets which will be used by gckHARDWARE, by which
++** gckHARDWARE can manipulate GPU by FE command without using gckCOMMAND to avoid
++** race condition and deadlock.
++**
++** Notice:
++** 1. Each snippet can only be executed when GPU is idle.
++** 2. Execution is triggered by AHB (0x658)
++** 3. Each snippet followed by END so software can sync with GPU by checking GPU
++** idle
++** 4. It is transparent to gckCOMMAND command buffer.
++**
++** Existing Snippets:
++** 1. MMU Configure
++** For new MMU, after GPU is reset, FE execute this command sequence to enble MMU.
++*/
++gceSTATUS
++gckHARDWARE_PrepareFunctions(
++ gckHARDWARE Hardware
++ )
++{
++ gceSTATUS status;
++ gckOS os;
++ gctUINT32 offset = 0;
++ gctUINT32 mmuBytes;
++ gctUINT32 endBytes;
++ gctUINT8_PTR logical;
++
++ gcmkHEADER_ARG("%x", Hardware);
++
++ os = Hardware->os;
++
++ gcmkVERIFY_OK(gckOS_GetPageSize(os, &Hardware->functionBytes));
++
++ /* Allocate a command buffer. */
++ gcmkONERROR(gckOS_AllocateNonPagedMemory(
++ os,
++ gcvFALSE,
++ &Hardware->functionBytes,
++ &Hardware->functionPhysical,
++ &Hardware->functionLogical
++ ));
++
++ gcmkONERROR(gckOS_GetPhysicalAddress(
++ os,
++ Hardware->functionLogical,
++ &Hardware->functionAddress
++ ));
++
++ if (Hardware->mmuVersion > 0)
++ {
++ /* MMU configure command sequence. */
++ logical = (gctUINT8_PTR)Hardware->functionLogical + offset;
++
++ Hardware->functions[gcvHARDWARE_FUNCTION_MMU].address
++ = Hardware->functionAddress + offset;
++
++ gcmkONERROR(gckHARDWARE_SetMMUStates(
++ Hardware,
++ Hardware->kernel->mmu->mtlbLogical,
++ gcvMMU_MODE_4K,
++ (gctUINT8_PTR)Hardware->kernel->mmu->mtlbLogical + gcdMMU_MTLB_SIZE,
++ logical,
++ &mmuBytes
++ ));
++
++ offset += mmuBytes;
++
++ logical = (gctUINT8_PTR)Hardware->functionLogical + offset;
++
++ gcmkONERROR(gckHARDWARE_End(
++ Hardware,
++ gcvNULL,
++ &endBytes
++ ));
++
++ gcmkONERROR(gckHARDWARE_End(
++ Hardware,
++ logical,
++ &endBytes
++ ));
++
++ offset += endBytes;
++
++ Hardware->functions[gcvHARDWARE_FUNCTION_MMU].bytes = mmuBytes + endBytes;
++ }
++
++ gcmkASSERT(offset < Hardware->functionBytes);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/arch/gc_hal_kernel_hardware.h linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/arch/gc_hal_kernel_hardware.h
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/arch/gc_hal_kernel_hardware.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/arch/gc_hal_kernel_hardware.h 2015-07-27 23:13:06.186908111 +0200
+@@ -0,0 +1,160 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_kernel_hardware_h_
++#define __gc_hal_kernel_hardware_h_
++
++#if gcdENABLE_VG
++#include "gc_hal_kernel_hardware_vg.h"
++#endif
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++typedef enum {
++ gcvHARDWARE_FUNCTION_MMU,
++ gcvHARDWARE_FUNCTION_FLUSH,
++
++ gcvHARDWARE_FUNCTION_NUM,
++}
++gceHARDWARE_FUNCTION;
++
++
++typedef struct _gcsHARWARE_FUNCTION
++{
++ /* Entry of the function. */
++ gctUINT32 address;
++
++ /* Bytes of the function. */
++ gctUINT32 bytes;
++}
++gcsHARDWARE_FUNCTION;
++
++/* gckHARDWARE object. */
++struct _gckHARDWARE
++{
++ /* Object. */
++ gcsOBJECT object;
++
++ /* Pointer to gctKERNEL object. */
++ gckKERNEL kernel;
++
++ /* Pointer to gctOS object. */
++ gckOS os;
++
++ /* Core */
++ gceCORE core;
++
++ /* Chip characteristics. */
++ gcsHAL_QUERY_CHIP_IDENTITY identity;
++ gctBOOL allowFastClear;
++ gctBOOL allowCompression;
++ gctUINT32 powerBaseAddress;
++ gctBOOL extraEventStates;
++
++ /* Big endian */
++ gctBOOL bigEndian;
++
++ /* Chip status */
++ gctPOINTER powerMutex;
++ gctUINT32 powerProcess;
++ gctUINT32 powerThread;
++ gceCHIPPOWERSTATE chipPowerState;
++ gctUINT32 lastWaitLink;
++ gctUINT32 lastEnd;
++ gctBOOL clockState;
++ gctBOOL powerState;
++ gctPOINTER globalSemaphore;
++
++ gctISRMANAGERFUNC startIsr;
++ gctISRMANAGERFUNC stopIsr;
++ gctPOINTER isrContext;
++
++ gctUINT32 mmuVersion;
++
++ /* Whether use new MMU. It is meaningless
++ ** for old MMU since old MMU is always enabled.
++ */
++ gctBOOL enableMMU;
++
++ /* Type */
++ gceHARDWARE_TYPE type;
++
++#if gcdPOWEROFF_TIMEOUT
++ gctUINT32 powerOffTime;
++ gctUINT32 powerOffTimeout;
++ gctPOINTER powerOffTimer;
++#endif
++
++#if gcdENABLE_FSCALE_VAL_ADJUST
++ gctUINT32 powerOnFscaleVal;
++#endif
++ gctPOINTER pageTableDirty;
++
++#if gcdLINK_QUEUE_SIZE
++ struct _gckLINKQUEUE linkQueue;
++#endif
++
++ gctBOOL powerManagement;
++ gctBOOL powerManagementLock;
++ gctBOOL gpuProfiler;
++
++ gctBOOL endAfterFlushMmuCache;
++
++ gctUINT32 minFscaleValue;
++
++ gctPOINTER pendingEvent;
++
++ /* Function used by gckHARDWARE. */
++ gctPHYS_ADDR functionPhysical;
++ gctPOINTER functionLogical;
++ gctUINT32 functionAddress;
++ gctSIZE_T functionBytes;
++
++ gcsHARDWARE_FUNCTION functions[gcvHARDWARE_FUNCTION_NUM];
++};
++
++gceSTATUS
++gckHARDWARE_GetBaseAddress(
++ IN gckHARDWARE Hardware,
++ OUT gctUINT32_PTR BaseAddress
++ );
++
++gceSTATUS
++gckHARDWARE_NeedBaseAddress(
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 State,
++ OUT gctBOOL_PTR NeedBase
++ );
++
++gceSTATUS
++gckHARDWARE_GetFrameInfo(
++ IN gckHARDWARE Hardware,
++ OUT gcsHAL_FRAME_INFO * FrameInfo
++ );
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __gc_hal_kernel_hardware_h_ */
++
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/arch/gc_hal_kernel_recorder.c linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/arch/gc_hal_kernel_recorder.c
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/arch/gc_hal_kernel_recorder.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/arch/gc_hal_kernel_recorder.c 2015-07-27 23:13:06.190893891 +0200
+@@ -0,0 +1,679 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal.h"
++#include "gc_hal_kernel.h"
++#include "gc_hal_kernel_context.h"
++
++/*
++ * -----------------------
++ * HARDWARE STATE RECORDER
++ * -----------------------
++ *
++ * State mirror buffer is used to 'mirror' hardware states since hardware
++ * states can't be dumpped. It is a context buffer which stores 'global'
++ * context.
++ *
++ * For each commit, state recorder
++ * 1) Records context buffer (if there is) and command buffers in this commit.
++ * 2) Parse those buffers to estimate the state changed.
++ * 3) Stores result to a mirror buffer.
++ *
++ * == Commit 0 ====================================================================
++ *
++ * Context Buffer 0
++ *
++ * Command Buffer 0
++ *
++ * Mirror Buffer 0 <- Context Buffer 0 + Command Buffer 0
++ *
++ * == Commit 1 ====================================================================
++ *
++ * Command Buffer 1
++ *
++ * Mirror Buffer 1 <- Command buffer 1 + Mirror Buffer 0
++ *
++ * == Commit 2 ====================================================================
++ *
++ * Context Buffer 2 (optional)
++ *
++ * Command Buffer 2
++ *
++ * Mirror Buffer 2 <- Command buffer 2 + Context Buffer 2 + Mirror Buffer 1
++ *
++ * == Commit N ====================================================================
++ *
++ * For Commit N, these buffers are needed to reproduce hardware's behavior in
++ * this commit.
++ *
++ * Mirror Buffer [N - 1] : State Mirror accumlated by past commits,
++ * which is used to restore hardware state.
++ * Context Buffer [N] :
++ * Command Buffer [N] : Command buffer executed by hardware in this commit.
++ *
++ * If sequence of states programming matters, hardware's behavior can't be reproduced,
++ * but the state values stored in mirror buffer are assuring.
++ */
++
++/* Queue size. */
++#define gcdNUM_RECORDS 6
++
++typedef struct _gcsPARSER_HANDLER * gckPARSER_HANDLER;
++
++typedef void
++(*HandlerFunction)(
++ IN gckPARSER_HANDLER Handler,
++ IN gctUINT32 Addr,
++ IN gctUINT32 Data
++ );
++
++typedef struct _gcsPARSER_HANDLER
++{
++ gctUINT32 type;
++ gctUINT32 cmd;
++ gctPOINTER private;
++ HandlerFunction function;
++}
++gcsPARSER_HANDLER;
++
++typedef struct _gcsPARSER * gckPARSER;
++typedef struct _gcsPARSER
++{
++ gctUINT8_PTR currentCmdBufferAddr;
++
++ /* Current command. */
++ gctUINT32 lo;
++ gctUINT32 hi;
++
++ gctUINT8 cmdOpcode;
++ gctUINT16 cmdAddr;
++ gctUINT32 cmdSize;
++ gctUINT32 cmdRectCount;
++ gctUINT8 skip;
++ gctUINT32 skipCount;
++
++ gctBOOL allow;
++
++ /* Callback used by parser to handle a command. */
++ gckPARSER_HANDLER commandHandler;
++}
++gcsPARSER;
++
++typedef struct _gcsMIRROR
++{
++ gctUINT32_PTR logical[gcdNUM_RECORDS];
++ gctUINT32 bytes;
++ gcsSTATE_MAP_PTR map;
++ gctUINT32 stateCount;
++}
++gcsMIRROR;
++
++typedef struct _gcsDELTA
++{
++ gctUINT64 commitStamp;
++ gctUINT32_PTR command;
++ gctUINT32 commandBytes;
++ gctUINT32_PTR context;
++ gctUINT32 contextBytes;
++}
++gcsDELTA;
++
++typedef struct _gcsRECORDER
++{
++ gckOS os;
++ gcsMIRROR mirror;
++ gcsDELTA deltas[gcdNUM_RECORDS];
++
++ /* Index of current record. */
++ gctUINT index;
++
++ /* Number of records. */
++ gctUINT num;
++
++ /* Plugin used by gckPARSER. */
++ gcsPARSER_HANDLER recorderHandler;
++ gckPARSER parser;
++}
++gcsRECORDER;
++
++
++/******************************************************************************\
++***************************** Command Buffer Parser ****************************
++\******************************************************************************/
++
++/*
++** Command buffer parser checks command buffer in FE's view to make sure there
++** is no format error.
++**
++** Parser provide a callback mechnisam, so plug-in can be added to implement
++** other functions.
++*/
++
++static void
++_HandleLoadState(
++ IN OUT gckPARSER Parser
++ )
++{
++ gctUINT i;
++ gctUINT32_PTR data = (gctUINT32_PTR)Parser->currentCmdBufferAddr;
++ gctUINT32 cmdAddr = Parser->cmdAddr;
++
++ if (Parser->commandHandler == gcvNULL
++ || Parser->commandHandler->cmd != 0x01
++ )
++ {
++ /* No handler for this command. */
++ return;
++ }
++
++ for (i = 0; i < Parser->cmdSize; i++)
++ {
++ Parser->commandHandler->function(Parser->commandHandler, cmdAddr, *data);
++
++ /* Advance to next state. */
++ cmdAddr++;
++ data++;
++ }
++}
++
++static void
++_GetCommand(
++ IN OUT gckPARSER Parser
++ )
++{
++ gctUINT32 * buffer = (gctUINT32 *)Parser->currentCmdBufferAddr;
++
++ gctUINT16 cmdRectCount;
++ gctUINT16 cmdDataCount;
++
++ Parser->hi = buffer[0];
++ Parser->lo = buffer[1];
++
++ Parser->cmdOpcode = (((((gctUINT32) (Parser->hi)) >> (0 ? 31:27)) & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1)))))) );
++ Parser->cmdRectCount = 1;
++
++ switch (Parser->cmdOpcode)
++ {
++ case 0x01:
++ /* Extract count. */
++ Parser->cmdSize = (((((gctUINT32) (Parser->hi)) >> (0 ? 25:16)) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1)))))) );
++ if (Parser->cmdSize == 0)
++ {
++ /* 0 means 1024. */
++ Parser->cmdSize = 1024;
++ }
++ Parser->skip = (Parser->cmdSize & 0x1) ? 0 : 1;
++
++ /* Extract address. */
++ Parser->cmdAddr = (((((gctUINT32) (Parser->hi)) >> (0 ? 15:0)) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1)))))) );
++
++ Parser->currentCmdBufferAddr = Parser->currentCmdBufferAddr + 4;
++ Parser->skipCount = Parser->cmdSize + Parser->skip;
++ break;
++
++ case 0x05:
++ Parser->cmdSize = 4;
++ Parser->skipCount = gcmALIGN(Parser->cmdSize, 2);
++ break;
++
++ case 0x06:
++ Parser->cmdSize = 5;
++ Parser->skipCount = gcmALIGN(Parser->cmdSize, 2);
++ break;
++
++ case 0x0C:
++ Parser->cmdSize = 3;
++ Parser->skipCount = gcmALIGN(Parser->cmdSize, 2);
++ break;
++
++ case 0x09:
++ Parser->cmdSize = 2;
++ Parser->cmdAddr = 0x0F16;
++ Parser->skipCount = gcmALIGN(Parser->cmdSize, 2);
++ break;
++
++ case 0x04:
++ Parser->cmdSize = 1;
++ Parser->cmdAddr = 0x0F06;
++
++ cmdRectCount = (((((gctUINT32) (Parser->hi)) >> (0 ? 15:8)) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1)))))) );
++ cmdDataCount = (((((gctUINT32) (Parser->hi)) >> (0 ? 26:16)) & ((gctUINT32) ((((1 ? 26:16) - (0 ? 26:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 26:16) - (0 ? 26:16) + 1)))))) );
++
++ Parser->skipCount = gcmALIGN(Parser->cmdSize, 2)
++ + cmdRectCount * 2
++ + gcmALIGN(cmdDataCount, 2);
++
++ Parser->cmdRectCount = cmdRectCount;
++ break;
++
++ case 0x03:
++ Parser->currentCmdBufferAddr = Parser->currentCmdBufferAddr + 8;
++ Parser->skipCount = 0;
++ break;
++
++ case 0x02:
++ Parser->currentCmdBufferAddr = Parser->currentCmdBufferAddr + 8;
++ Parser->skipCount = 0;
++ break;
++
++ default:
++ /* Unknown command is a risk. */
++ Parser->allow = gcvFALSE;
++ break;
++ }
++}
++
++static void
++_ParseCommand(
++ IN OUT gckPARSER Parser
++ )
++{
++ switch(Parser->cmdOpcode)
++ {
++ case 0x01:
++ _HandleLoadState(Parser);
++ break;
++ case 0x05:
++ case 0x06:
++ case 0x0C:
++ break;
++ case 0x04:
++ break;
++ default:
++ break;
++ }
++
++ /* Advance to next command. */
++ Parser->currentCmdBufferAddr = Parser->currentCmdBufferAddr
++ + (Parser->skipCount << 2);
++}
++
++gceSTATUS
++gckPARSER_Parse(
++ IN gckPARSER Parser,
++ IN gctUINT8_PTR Buffer,
++ IN gctUINT32 Bytes
++ )
++{
++ gckPARSER parser = Parser;
++ gctUINT8_PTR end = (gctUINT8_PTR)Buffer + Bytes;
++
++ /* Initialize parser. */
++ parser->currentCmdBufferAddr = (gctUINT8_PTR)Buffer;
++ parser->skip = 0;
++ parser->allow = gcvTRUE;
++
++ /* Go through command buffer until reaching the end
++ ** or meeting an error. */
++ do
++ {
++ _GetCommand(parser);
++
++ _ParseCommand(parser);
++ }
++ while ((parser->currentCmdBufferAddr < end) && (parser->allow == gcvTRUE));
++
++ if (parser->allow == gcvFALSE)
++ {
++ /* Error detected. */
++ return gcvSTATUS_NOT_SUPPORTED;
++ }
++
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckPARSER_RegisterCommandHandler
++**
++** Register a command handler which will be called when parser get a command.
++**
++*/
++gceSTATUS
++gckPARSER_RegisterCommandHandler(
++ IN gckPARSER Parser,
++ IN gckPARSER_HANDLER Handler
++ )
++{
++ Parser->commandHandler = Handler;
++
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckPARSER_Construct(
++ IN gckOS Os,
++ IN gckPARSER_HANDLER Handler,
++ OUT gckPARSER * Parser
++ )
++{
++ gceSTATUS status;
++ gckPARSER pointer;
++
++ gcmkONERROR(gckOS_Allocate(Os, gcmSIZEOF(gcsPARSER), (gctPOINTER *)&pointer));
++
++ /* Put it here temp, should have a more general plug-in mechnisam. */
++ pointer->commandHandler = Handler;
++
++ *Parser = pointer;
++
++ return gcvSTATUS_OK;
++
++OnError:
++ return status;
++}
++
++void
++gckPARSER_Destroy(
++ IN gckOS Os,
++ IN gckPARSER Parser
++ )
++{
++ gcmkOS_SAFE_FREE(Os, Parser);
++}
++
++/******************************************************************************\
++**************************** Hardware States Recorder **************************
++\******************************************************************************/
++
++static void
++_RecodeState(
++ IN gckPARSER_HANDLER Handler,
++ IN gctUINT32 Addr,
++ IN gctUINT32 Data
++ )
++{
++ gcmkVERIFY_OK(gckRECORDER_UpdateMirror(Handler->private, Addr, Data));
++}
++
++static gctUINT
++_Previous(
++ IN gctUINT Index
++ )
++{
++ if (Index == 0)
++ {
++ return gcdNUM_RECORDS - 1;
++ }
++
++ return Index - 1;
++}
++
++static gctUINT
++_Next(
++ IN gctUINT Index
++ )
++{
++ return (Index + 1) % gcdNUM_RECORDS;
++}
++
++gceSTATUS
++gckRECORDER_Construct(
++ IN gckOS Os,
++ IN gckHARDWARE Hardware,
++ OUT gckRECORDER * Recorder
++ )
++{
++ gceSTATUS status;
++ gckCONTEXT context = gcvNULL;
++ gckRECORDER recorder = gcvNULL;
++ gctUINT32 mapSize;
++ gctUINT i;
++ gctBOOL virtualCommandBuffer = Hardware->kernel->virtualCommandBuffer;
++
++ /* TODO: We only need context buffer and state map, it should be able to get without construct a
++ ** new context.
++ ** Now it is leaked, since we can't free it when command buffer is gone.
++ */
++
++ /* MMU is not ready now. */
++ Hardware->kernel->virtualCommandBuffer = gcvFALSE;
++
++ gcmkONERROR(gckCONTEXT_Construct(Os, Hardware, 0, &context));
++
++ /* Restore. */
++ Hardware->kernel->virtualCommandBuffer = virtualCommandBuffer;
++
++ gcmkONERROR(gckOS_Allocate(Os, gcmSIZEOF(gcsRECORDER), (gctPOINTER *)&recorder));
++
++ gckOS_ZeroMemory(recorder, gcmSIZEOF(gcsRECORDER));
++
++ /* Copy state map. */
++ recorder->mirror.stateCount = context->stateCount;
++
++ mapSize = context->stateCount * gcmSIZEOF(gcsSTATE_MAP);
++
++ gcmkONERROR(gckOS_Allocate(Os, mapSize, (gctPOINTER *)&recorder->mirror.map));
++
++ gckOS_MemCopy(recorder->mirror.map, context->map, mapSize);
++
++ /* Copy context buffer. */
++ recorder->mirror.bytes = context->totalSize;
++
++ for (i = 0; i < gcdNUM_RECORDS; i++)
++ {
++ gcmkONERROR(gckOS_Allocate(Os, context->totalSize, (gctPOINTER *)&recorder->mirror.logical[i]));
++ gckOS_MemCopy(recorder->mirror.logical[i], context->buffer->logical, context->totalSize);
++ }
++
++ for (i = 0; i < gcdNUM_RECORDS; i++)
++ {
++ /* TODO : Optimize size. */
++ gcmkONERROR(gckOS_Allocate(Os, gcdCMD_BUFFER_SIZE, (gctPOINTER *)&recorder->deltas[i].command));
++ gcmkONERROR(gckOS_Allocate(Os, context->totalSize, (gctPOINTER *)&recorder->deltas[i].context));
++ }
++
++ recorder->index = 0;
++ recorder->num = 0;
++
++ /* Initialize Parser plugin. */
++ recorder->recorderHandler.cmd = 0x01;
++ recorder->recorderHandler.private = recorder;
++ recorder->recorderHandler.function = _RecodeState;
++
++ gcmkONERROR(gckPARSER_Construct(Os, &recorder->recorderHandler, &recorder->parser));
++
++ recorder->os = Os;
++
++ *Recorder = recorder;
++
++ return gcvSTATUS_OK;
++
++OnError:
++ if (recorder)
++ {
++ gckRECORDER_Destory(Os, recorder);
++ }
++
++ return status;
++}
++
++gceSTATUS
++gckRECORDER_Destory(
++ IN gckOS Os,
++ IN gckRECORDER Recorder
++ )
++{
++ gctUINT i;
++
++ if (Recorder->mirror.map)
++ {
++ gcmkOS_SAFE_FREE(Os, Recorder->mirror.map);
++ }
++
++ for (i = 0; i < gcdNUM_RECORDS; i++)
++ {
++ if (Recorder->mirror.logical[i])
++ {
++ gcmkOS_SAFE_FREE(Os, Recorder->mirror.logical[i]);
++ }
++ }
++
++ for (i = 0; i < gcdNUM_RECORDS; i++)
++ {
++ if (Recorder->deltas[i].command)
++ {
++ gcmkOS_SAFE_FREE(Os, Recorder->deltas[i].command);
++ }
++
++ if (Recorder->deltas[i].context)
++ {
++ gcmkOS_SAFE_FREE(Os, Recorder->deltas[i].context);
++ }
++ }
++
++ if (Recorder->parser)
++ {
++ gckPARSER_Destroy(Os, Recorder->parser);
++ }
++
++ gcmkOS_SAFE_FREE(Os, Recorder);
++
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckRECORDER_UpdateMirror(
++ IN gckRECORDER Recorder,
++ IN gctUINT32 State,
++ IN gctUINT32 Data
++ )
++{
++ gctUINT32 index;
++ gcsSTATE_MAP_PTR map = Recorder->mirror.map;
++ gctUINT32_PTR buffer = Recorder->mirror.logical[Recorder->index];
++
++ if (State >= Recorder->mirror.stateCount)
++ {
++ /* Ignore them just like HW does. */
++ return gcvSTATUS_OK;
++ }
++
++ index = map[State].index;
++
++ if (index)
++ {
++ buffer[index] = Data;
++ }
++
++ return gcvSTATUS_OK;
++}
++
++void
++gckRECORDER_AdvanceIndex(
++ IN gckRECORDER Recorder,
++ IN gctUINT64 CommitStamp
++ )
++{
++ /* Get next record. */
++ gctUINT next = (Recorder->index + 1) % gcdNUM_RECORDS;
++
++ /* Record stamp of this commit. */
++ Recorder->deltas[Recorder->index].commitStamp = CommitStamp;
++
++ /* Mirror of next record is mirror of this record and delta in next record. */
++ gckOS_MemCopy(Recorder->mirror.logical[next],
++ Recorder->mirror.logical[Recorder->index], Recorder->mirror.bytes);
++
++ /* Advance to next record. */
++ Recorder->index = next;
++
++ Recorder->num = gcmMIN(Recorder->num + 1, gcdNUM_RECORDS - 1);
++
++
++ /* Reset delta. */
++ Recorder->deltas[Recorder->index].commandBytes = 0;
++ Recorder->deltas[Recorder->index].contextBytes = 0;
++}
++
++void
++gckRECORDER_Record(
++ IN gckRECORDER Recorder,
++ IN gctUINT8_PTR CommandBuffer,
++ IN gctUINT32 CommandBytes,
++ IN gctUINT8_PTR ContextBuffer,
++ IN gctUINT32 ContextBytes
++ )
++{
++ gcsDELTA * delta = &Recorder->deltas[Recorder->index];
++
++ if (CommandBytes != 0xFFFFFFFF)
++ {
++ gckPARSER_Parse(Recorder->parser, CommandBuffer, CommandBytes);
++ gckOS_MemCopy(delta->command, CommandBuffer, CommandBytes);
++ delta->commandBytes = CommandBytes;
++ }
++
++ if (ContextBytes != 0xFFFFFFFF)
++ {
++ gckPARSER_Parse(Recorder->parser, ContextBuffer, ContextBytes);
++ gckOS_MemCopy(delta->context, ContextBuffer, ContextBytes);
++ delta->contextBytes = ContextBytes;
++ }
++}
++
++void
++gckRECORDER_Dump(
++ IN gckRECORDER Recorder
++ )
++{
++ gctUINT last = Recorder->index;
++ gctUINT previous;
++ gctUINT i;
++ gcsMIRROR *mirror = &Recorder->mirror;
++ gcsDELTA *delta;
++ gckOS os = Recorder->os;
++
++ for (i = 0; i < Recorder->num; i++)
++ {
++ last = _Previous(last);
++ }
++
++ for (i = 0; i < Recorder->num; i++)
++ {
++ delta = &Recorder->deltas[last];
++
++ /* Dump record */
++ gcmkPRINT("#[commit %llu]", delta->commitStamp);
++
++ if (delta->commitStamp)
++ {
++ previous = _Previous(last);
++
++ gcmkPRINT("#[mirror]");
++ gckOS_DumpBuffer(os, mirror->logical[previous], mirror->bytes, gceDUMP_BUFFER_CONTEXT, gcvTRUE);
++ gcmkPRINT("@[kernel.execute]");
++ }
++
++ if (delta->contextBytes)
++ {
++ gckOS_DumpBuffer(os, delta->context, delta->contextBytes, gceDUMP_BUFFER_CONTEXT, gcvTRUE);
++ gcmkPRINT("@[kernel.execute]");
++ }
++
++ gckOS_DumpBuffer(os, delta->command, delta->commandBytes, gceDUMP_BUFFER_USER, gcvTRUE);
++ gcmkPRINT("@[kernel.execute]");
++
++ last = _Next(last);
++ }
++}
++
++
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/archvg/gc_hal_kernel_hardware_command_vg.c linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/archvg/gc_hal_kernel_hardware_command_vg.c
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/archvg/gc_hal_kernel_hardware_command_vg.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/archvg/gc_hal_kernel_hardware_command_vg.c 2015-07-27 23:13:06.190893891 +0200
+@@ -0,0 +1,932 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal.h"
++#include "gc_hal_kernel.h"
++
++#if gcdENABLE_VG
++
++#include "gc_hal_kernel_hardware_command_vg.h"
++
++#define _GC_OBJ_ZONE gcvZONE_COMMAND
++
++/******************************************************************************\
++****************************** gckVGCOMMAND API code *****************************
++\******************************************************************************/
++
++/*******************************************************************************
++**
++** gckVGCOMMAND_InitializeInfo
++**
++** Initialize architecture dependent command buffer information.
++**
++** INPUT:
++**
++** gckVGCOMMAND Command
++** Pointer to the Command object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckVGCOMMAND_InitializeInfo(
++ IN gckVGCOMMAND Command
++ )
++{
++ gceSTATUS status;
++ gcmkHEADER_ARG("Command=0x%x", Command);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ do
++ {
++ /* Reset interrupts. */
++ Command->info.feBufferInt = -1;
++ Command->info.tsOverflowInt = -1;
++
++ /* Set command buffer attributes. */
++ Command->info.addressAlignment = 64;
++ Command->info.commandAlignment = 8;
++
++ /* Determine command alignment address mask. */
++ Command->info.addressMask = ((((gctUINT32) (Command->info.addressAlignment - 1)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0))) | (((gctUINT32) ((gctUINT32) (0 ) & ((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0)));
++
++ /* Query the number of bytes needed by the STATE command. */
++ gcmkERR_BREAK(gckVGCOMMAND_StateCommand(
++ Command, 0x0, gcvNULL, (gctUINT32)~0, 0,
++ &Command->info.stateCommandSize
++ ));
++
++ /* Query the number of bytes needed by the RESTART command. */
++ gcmkERR_BREAK(gckVGCOMMAND_RestartCommand(
++ Command, gcvNULL, (gctUINT32)~0, 0,
++ &Command->info.restartCommandSize
++ ));
++
++ /* Query the number of bytes needed by the FETCH command. */
++ gcmkERR_BREAK(gckVGCOMMAND_FetchCommand(
++ Command, gcvNULL, (gctUINT32)~0, 0,
++ &Command->info.fetchCommandSize
++ ));
++
++ /* Query the number of bytes needed by the CALL command. */
++ gcmkERR_BREAK(gckVGCOMMAND_CallCommand(
++ Command, gcvNULL, (gctUINT32)~0, 0,
++ &Command->info.callCommandSize
++ ));
++
++ /* Query the number of bytes needed by the RETURN command. */
++ gcmkERR_BREAK(gckVGCOMMAND_ReturnCommand(
++ Command, gcvNULL,
++ &Command->info.returnCommandSize
++ ));
++
++ /* Query the number of bytes needed by the EVENT command. */
++ gcmkERR_BREAK(gckVGCOMMAND_EventCommand(
++ Command, gcvNULL, gcvBLOCK_PIXEL, -1,
++ &Command->info.eventCommandSize
++ ));
++
++ /* Query the number of bytes needed by the END command. */
++ gcmkERR_BREAK(gckVGCOMMAND_EndCommand(
++ Command, gcvNULL, -1,
++ &Command->info.endCommandSize
++ ));
++
++ /* Determine the tail reserve size. */
++ Command->info.staticTailSize = gcmMAX(
++ Command->info.fetchCommandSize,
++ gcmMAX(
++ Command->info.returnCommandSize,
++ Command->info.endCommandSize
++ )
++ );
++
++ /* Determine the maximum tail size. */
++ Command->info.dynamicTailSize
++ = Command->info.staticTailSize
++ + Command->info.eventCommandSize * gcvBLOCK_COUNT;
++ }
++ while (gcvFALSE);
++
++ gcmkFOOTER();
++ /* Return status. */
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckVGCOMMAND_StateCommand
++**
++** Append a STATE command at the specified location in the command buffer.
++**
++** INPUT:
++**
++** gckVGCOMMAND Command
++** Pointer to an gckVGCOMMAND object.
++**
++** gctUINT32 Pipe
++** Harwdare destination pipe.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command buffer to append
++** STATE command at or gcvNULL to query the size of the command.
++**
++** gctUINT32 Address
++** Starting register address of the state buffer.
++** If 'Logical' is gcvNULL, this argument is ignored.
++**
++** gctUINT32 Count
++** Number of states in state buffer.
++** If 'Logical' is gcvNULL, this argument is ignored.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the STATE command.
++** If 'Logical' is gcvNULL, the value from this argument is ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** for the STATE command. If 'Bytes' is gcvNULL, nothing is returned.
++*/
++gceSTATUS
++gckVGCOMMAND_StateCommand(
++ IN gckVGCOMMAND Command,
++ IN gctUINT32 Pipe,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Address,
++ IN gctUINT32 Count,
++ IN OUT gctUINT32 * Bytes
++ )
++{
++ gcmkHEADER_ARG("Command=0x%x Pipe=0x%x Logical=0x%x Address=0x%x Count=0x%x Bytes = 0x%x",
++ Command, Pipe, Logical, Address, Count, Bytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ if (Command->fe20)
++ {
++ if (Logical != gcvNULL)
++ {
++ gctUINT32_PTR buffer;
++
++ /* Cast the buffer pointer. */
++ buffer = (gctUINT32_PTR) Logical;
++
++ /* Append STATE. */
++ buffer[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28))) | (((gctUINT32) (0x3 & ((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 11:0) - (0 ? 11:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:0) - (0 ? 11:0) + 1))))))) << (0 ? 11:0))) | (((gctUINT32) ((gctUINT32) (Address) & ((gctUINT32) ((((1 ? 11:0) - (0 ? 11:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:0) - (0 ? 11:0) + 1))))))) << (0 ? 11:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 27:16) - (0 ? 27:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:16) - (0 ? 27:16) + 1))))))) << (0 ? 27:16))) | (((gctUINT32) ((gctUINT32) (Count) & ((gctUINT32) ((((1 ? 27:16) - (0 ? 27:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:16) - (0 ? 27:16) + 1))))))) << (0 ? 27:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 13:12) - (0 ? 13:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 13:12) - (0 ? 13:12) + 1))))))) << (0 ? 13:12))) | (((gctUINT32) ((gctUINT32) (Pipe) & ((gctUINT32) ((((1 ? 13:12) - (0 ? 13:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 13:12) - (0 ? 13:12) + 1))))))) << (0 ? 13:12)));
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the STATE command. */
++ *Bytes = 4 * (Count + 1);
++ }
++ }
++ else
++ {
++ if (Logical != gcvNULL)
++ {
++ gctUINT32_PTR buffer;
++
++ /* Cast the buffer pointer. */
++ buffer = (gctUINT32_PTR) Logical;
++
++ /* Append LOAD_STATE. */
++ buffer[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (Count) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (Address) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the STATE command. */
++ *Bytes = 4 * (Count + 1);
++ }
++ }
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGCOMMAND_RestartCommand
++**
++** Form a RESTART command at the specified location in the command buffer.
++**
++** INPUT:
++**
++** gckVGCOMMAND Command
++** Pointer to an gckVGCOMMAND object.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command buffer to append
++** RESTART command at or gcvNULL to query the size of the command.
++**
++** gctUINT32 FetchAddress
++** The address of another command buffer to be executed by this RESTART
++** command. If 'Logical' is gcvNULL, this argument is ignored.
++**
++** gctUINT FetchCount
++** The number of 64-bit data quantities in another command buffer to
++** be executed by this RESTART command. If 'Logical' is gcvNULL, this
++** argument is ignored.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the RESTART command.
++** If 'Logical' is gcvNULL, the value from this argument is ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** for the RESTART command. If 'Bytes' is gcvNULL, nothing is returned.
++*/
++gceSTATUS
++gckVGCOMMAND_RestartCommand(
++ IN gckVGCOMMAND Command,
++ IN gctPOINTER Logical,
++ IN gctUINT32 FetchAddress,
++ IN gctUINT FetchCount,
++ IN OUT gctUINT32 * Bytes
++ )
++{
++ gcmkHEADER_ARG("Command=0x%x Logical=0x%x FetchAddress=0x%x FetchCount=0x%x Bytes = 0x%x",
++ Command, Logical, FetchAddress, FetchCount, Bytes);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ if (Command->fe20)
++ {
++ if (Logical != gcvNULL)
++ {
++ gctUINT32_PTR buffer;
++ gctUINT32 beginEndMark;
++
++ /* Cast the buffer pointer. */
++ buffer = (gctUINT32_PTR) Logical;
++
++ /* Determine Begin/End flag. */
++ beginEndMark = (FetchCount > 0)
++ ? ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 24:24) - (0 ? 24:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 24:24) - (0 ? 24:24) + 1))))))) << (0 ? 24:24))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 24:24) - (0 ? 24:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 24:24) - (0 ? 24:24) + 1))))))) << (0 ? 24:24)))
++ : ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 24:24) - (0 ? 24:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 24:24) - (0 ? 24:24) + 1))))))) << (0 ? 24:24))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 24:24) - (0 ? 24:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 24:24) - (0 ? 24:24) + 1))))))) << (0 ? 24:24)));
++
++ /* Append RESTART. */
++ buffer[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28))) | (((gctUINT32) (0x9 & ((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 20:0) - (0 ? 20:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:0) - (0 ? 20:0) + 1))))))) << (0 ? 20:0))) | (((gctUINT32) ((gctUINT32) (FetchCount) & ((gctUINT32) ((((1 ? 20:0) - (0 ? 20:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:0) - (0 ? 20:0) + 1))))))) << (0 ? 20:0)))
++ | beginEndMark;
++
++ buffer[1]
++ = FetchAddress;
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the RESTART command. */
++ *Bytes = 8;
++ }
++ }
++ else
++ {
++ gcmkFOOTER_NO();
++ return gcvSTATUS_NOT_SUPPORTED;
++ }
++
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGCOMMAND_FetchCommand
++**
++** Form a FETCH command at the specified location in the command buffer.
++**
++** INPUT:
++**
++** gckVGCOMMAND Command
++** Pointer to an gckVGCOMMAND object.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command buffer to append
++** FETCH command at or gcvNULL to query the size of the command.
++**
++** gctUINT32 FetchAddress
++** The address of another command buffer to be executed by this FETCH
++** command. If 'Logical' is gcvNULL, this argument is ignored.
++**
++** gctUINT FetchCount
++** The number of 64-bit data quantities in another command buffer to
++** be executed by this FETCH command. If 'Logical' is gcvNULL, this
++** argument is ignored.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the FETCH command.
++** If 'Logical' is gcvNULL, the value from this argument is ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** for the FETCH command. If 'Bytes' is gcvNULL, nothing is returned.
++*/
++gceSTATUS
++gckVGCOMMAND_FetchCommand(
++ IN gckVGCOMMAND Command,
++ IN gctPOINTER Logical,
++ IN gctUINT32 FetchAddress,
++ IN gctUINT FetchCount,
++ IN OUT gctUINT32 * Bytes
++ )
++{
++ gcmkHEADER_ARG("Command=0x%x Logical=0x%x FetchAddress=0x%x FetchCount=0x%x Bytes = 0x%x",
++ Command, Logical, FetchAddress, FetchCount, Bytes);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ if (Command->fe20)
++ {
++ if (Logical != gcvNULL)
++ {
++ gctUINT32_PTR buffer;
++
++ /* Cast the buffer pointer. */
++ buffer = (gctUINT32_PTR) Logical;
++
++ /* Append FETCH. */
++ buffer[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28))) | (((gctUINT32) (0x5 & ((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 20:0) - (0 ? 20:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:0) - (0 ? 20:0) + 1))))))) << (0 ? 20:0))) | (((gctUINT32) ((gctUINT32) (FetchCount) & ((gctUINT32) ((((1 ? 20:0) - (0 ? 20:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:0) - (0 ? 20:0) + 1))))))) << (0 ? 20:0)));
++
++ buffer[1]
++ = gcmkFIXADDRESS(FetchAddress);
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the FETCH command. */
++ *Bytes = 8;
++ }
++ }
++ else
++ {
++ if (Logical != gcvNULL)
++ {
++ gctUINT32_PTR buffer;
++
++ /* Cast the buffer pointer. */
++ buffer = (gctUINT32_PTR) Logical;
++
++ /* Append LINK. */
++ buffer[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x08 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (FetchCount) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ buffer[1]
++ = gcmkFIXADDRESS(FetchAddress);
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the LINK command. */
++ *Bytes = 8;
++ }
++ }
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGCOMMAND_CallCommand
++**
++** Append a CALL command at the specified location in the command buffer.
++**
++** INPUT:
++**
++** gckVGCOMMAND Command
++** Pointer to an gckVGCOMMAND object.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command buffer to append
++** CALL command at or gcvNULL to query the size of the command.
++**
++** gctUINT32 FetchAddress
++** The address of another command buffer to be executed by this CALL
++** command. If 'Logical' is gcvNULL, this argument is ignored.
++**
++** gctUINT FetchCount
++** The number of 64-bit data quantities in another command buffer to
++** be executed by this CALL command. If 'Logical' is gcvNULL, this
++** argument is ignored.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the CALL command.
++** If 'Logical' is gcvNULL, the value from this argument is ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** for the CALL command. If 'Bytes' is gcvNULL, nothing is returned.
++*/
++gceSTATUS
++gckVGCOMMAND_CallCommand(
++ IN gckVGCOMMAND Command,
++ IN gctPOINTER Logical,
++ IN gctUINT32 FetchAddress,
++ IN gctUINT FetchCount,
++ IN OUT gctUINT32 * Bytes
++ )
++{
++ gcmkHEADER_ARG("Command=0x%x Logical=0x%x FetchAddress=0x%x FetchCount=0x%x Bytes = 0x%x",
++ Command, Logical, FetchAddress, FetchCount, Bytes);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ if (Command->fe20)
++ {
++ if (Logical != gcvNULL)
++ {
++ gctUINT32_PTR buffer;
++
++ /* Cast the buffer pointer. */
++ buffer = (gctUINT32_PTR) Logical;
++
++ /* Append CALL. */
++ buffer[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28))) | (((gctUINT32) (0x6 & ((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 20:0) - (0 ? 20:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:0) - (0 ? 20:0) + 1))))))) << (0 ? 20:0))) | (((gctUINT32) ((gctUINT32) (FetchCount) & ((gctUINT32) ((((1 ? 20:0) - (0 ? 20:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:0) - (0 ? 20:0) + 1))))))) << (0 ? 20:0)));
++
++ buffer[1]
++ = gcmkFIXADDRESS(FetchAddress);
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the CALL command. */
++ *Bytes = 8;
++ }
++ }
++ else
++ {
++ gcmkFOOTER_NO();
++ return gcvSTATUS_NOT_SUPPORTED;
++ }
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGCOMMAND_ReturnCommand
++**
++** Append a RETURN command at the specified location in the command buffer.
++**
++** INPUT:
++**
++** gckVGCOMMAND Command
++** Pointer to an gckVGCOMMAND object.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command buffer to append
++** RETURN command at or gcvNULL to query the size of the command.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the RETURN command.
++** If 'Logical' is gcvNULL, the value from this argument is ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** for the RETURN command. If 'Bytes' is gcvNULL, nothing is returned.
++*/
++gceSTATUS
++gckVGCOMMAND_ReturnCommand(
++ IN gckVGCOMMAND Command,
++ IN gctPOINTER Logical,
++ IN OUT gctUINT32 * Bytes
++ )
++{
++ gcmkHEADER_ARG("Command=0x%x Logical=0x%x Bytes = 0x%x",
++ Command, Logical, Bytes);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ if (Command->fe20)
++ {
++ if (Logical != gcvNULL)
++ {
++ gctUINT32_PTR buffer;
++
++ /* Cast the buffer pointer. */
++ buffer = (gctUINT32_PTR) Logical;
++
++ /* Append RETURN. */
++ buffer[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28))) | (((gctUINT32) (0x7 & ((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28)));
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the RETURN command. */
++ *Bytes = 8;
++ }
++ }
++ else
++ {
++ gcmkFOOTER_NO();
++ return gcvSTATUS_NOT_SUPPORTED;
++ }
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGCOMMAND_EventCommand
++**
++** Form an EVENT command at the specified location in the command buffer.
++**
++** INPUT:
++**
++** gckVGCOMMAND Command
++** Pointer to the Command object.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command buffer to append
++** EVENT command at or gcvNULL to query the size of the command.
++**
++** gctINT32 InterruptId
++** The ID of the interrupt to generate.
++** If 'Logical' is gcvNULL, this argument is ignored.
++**
++** gceBLOCK Block
++** Block that will generate the interrupt.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the EVENT command.
++** If 'Logical' is gcvNULL, the value from this argument is ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** for the END command. If 'Bytes' is gcvNULL, nothing is returned.
++*/
++gceSTATUS
++gckVGCOMMAND_EventCommand(
++ IN gckVGCOMMAND Command,
++ IN gctPOINTER Logical,
++ IN gceBLOCK Block,
++ IN gctINT32 InterruptId,
++ IN OUT gctUINT32 * Bytes
++ )
++{
++ gcmkHEADER_ARG("Command=0x%x Logical=0x%x Block=0x%x InterruptId=0x%x Bytes = 0x%x",
++ Command, Logical, Block, InterruptId, Bytes);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ if (Command->fe20)
++ {
++ typedef struct _gcsEVENTSTATES
++ {
++ /* Chips before VG21 use these values. */
++ gctUINT eventFromFE;
++ gctUINT eventFromPE;
++
++ /* VG21 chips and later use SOURCE field. */
++ gctUINT eventSource;
++ }
++ gcsEVENTSTATES;
++
++ static gcsEVENTSTATES states[] =
++ {
++ /* gcvBLOCK_COMMAND */
++ {
++ (gctUINT)~0,
++ (gctUINT)~0,
++ (gctUINT)~0
++ },
++
++ /* gcvBLOCK_TESSELLATOR */
++ {
++ 0x0,
++ 0x1,
++ 0x10
++ },
++
++ /* gcvBLOCK_TESSELLATOR2 */
++ {
++ 0x0,
++ 0x1,
++ 0x12
++ },
++
++ /* gcvBLOCK_TESSELLATOR3 */
++ {
++ 0x0,
++ 0x1,
++ 0x14
++ },
++
++ /* gcvBLOCK_RASTER */
++ {
++ 0x0,
++ 0x1,
++ 0x07,
++ },
++
++ /* gcvBLOCK_VG */
++ {
++ 0x0,
++ 0x1,
++ 0x0F
++ },
++
++ /* gcvBLOCK_VG2 */
++ {
++ 0x0,
++ 0x1,
++ 0x11
++ },
++
++ /* gcvBLOCK_VG3 */
++ {
++ 0x0,
++ 0x1,
++ 0x13
++ },
++
++ /* gcvBLOCK_PIXEL */
++ {
++ 0x0,
++ 0x1,
++ 0x07
++ },
++ };
++
++ /* Verify block ID. */
++ gcmkVERIFY_ARGUMENT(gcmIS_VALID_INDEX(Block, states));
++
++ if (Logical != gcvNULL)
++ {
++ gctUINT32_PTR buffer;
++
++ /* Verify the event ID. */
++ gcmkVERIFY_ARGUMENT(InterruptId >= 0);
++ gcmkVERIFY_ARGUMENT(InterruptId <= ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))));
++
++ /* Cast the buffer pointer. */
++ buffer = (gctUINT32_PTR) Logical;
++
++ /* Append EVENT. */
++ buffer[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28))) | (((gctUINT32) (0x3 & ((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 11:0) - (0 ? 11:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:0) - (0 ? 11:0) + 1))))))) << (0 ? 11:0))) | (((gctUINT32) ((gctUINT32) (0x0E01) & ((gctUINT32) ((((1 ? 11:0) - (0 ? 11:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:0) - (0 ? 11:0) + 1))))))) << (0 ? 11:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 27:16) - (0 ? 27:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:16) - (0 ? 27:16) + 1))))))) << (0 ? 27:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 27:16) - (0 ? 27:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:16) - (0 ? 27:16) + 1))))))) << (0 ? 27:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 13:12) - (0 ? 13:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 13:12) - (0 ? 13:12) + 1))))))) << (0 ? 13:12))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 13:12) - (0 ? 13:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 13:12) - (0 ? 13:12) + 1))))))) << (0 ? 13:12)));
++
++ /* Determine chip version. */
++ if (Command->vg21)
++ {
++ /* Get the event source for the block. */
++ gctUINT eventSource = states[Block].eventSource;
++
++ /* Supported? */
++ if (eventSource == ~0)
++ {
++ gcmkFOOTER_NO();
++ return gcvSTATUS_NOT_SUPPORTED;
++ }
++
++ buffer[1]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) ((gctUINT32) (InterruptId) & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) ((gctUINT32) (eventSource) & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++ }
++ else
++ {
++ /* Get the event source for the block. */
++ gctUINT eventFromFE = states[Block].eventFromFE;
++ gctUINT eventFromPE = states[Block].eventFromPE;
++
++ /* Supported? */
++ if (eventFromFE == ~0)
++ {
++ gcmkFOOTER_NO();
++ return gcvSTATUS_NOT_SUPPORTED;
++ }
++
++ buffer[1]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) ((gctUINT32) (InterruptId) & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))) | (((gctUINT32) ((gctUINT32) (eventFromFE) & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6))) | (((gctUINT32) ((gctUINT32) (eventFromPE) & ((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6)));
++ }
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Make sure the events are directly supported for the block. */
++ if (states[Block].eventSource == ~0)
++ {
++ gcmkFOOTER_NO();
++ return gcvSTATUS_NOT_SUPPORTED;
++ }
++
++ /* Return number of bytes required by the END command. */
++ *Bytes = 8;
++ }
++ }
++ else
++ {
++ if (Logical != gcvNULL)
++ {
++ gctUINT32_PTR buffer;
++
++ /* Verify the event ID. */
++ gcmkVERIFY_ARGUMENT(InterruptId >= 0);
++ gcmkVERIFY_ARGUMENT(InterruptId <= ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))));
++
++ /* Cast the buffer pointer. */
++ buffer = (gctUINT32_PTR) Logical;
++
++ /* Append EVENT. */
++ buffer[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E01) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ /* Determine event source. */
++ if (Block == gcvBLOCK_COMMAND)
++ {
++ buffer[1]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) ((gctUINT32) (InterruptId) & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5)));
++ }
++ else
++ {
++ buffer[1]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) ((gctUINT32) (InterruptId) & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6)));
++ }
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the EVENT and END commands. */
++ *Bytes = 8;
++ }
++ }
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGCOMMAND_EndCommand
++**
++** Form an END command at the specified location in the command buffer.
++**
++** INPUT:
++**
++** gckVGCOMMAND Command
++** Pointer to the Command object.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command buffer to append
++** END command at or gcvNULL to query the size of the command.
++**
++** gctINT32 InterruptId
++** The ID of the interrupt to generate.
++** If 'Logical' is gcvNULL, this argument will be ignored.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the END command.
++** If 'Logical' is gcvNULL, the value from this argument is ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** for the END command. If 'Bytes' is gcvNULL, nothing is returned.
++*/
++gceSTATUS
++gckVGCOMMAND_EndCommand(
++ IN gckVGCOMMAND Command,
++ IN gctPOINTER Logical,
++ IN gctINT32 InterruptId,
++ IN OUT gctUINT32 * Bytes
++ )
++{
++ gcmkHEADER_ARG("Command=0x%x Logical=0x%x InterruptId=0x%x Bytes = 0x%x",
++ Command, Logical, InterruptId, Bytes);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ if (Command->fe20)
++ {
++ if (Logical != gcvNULL)
++ {
++ gctUINT32_PTR buffer;
++
++ /* Verify the event ID. */
++ gcmkVERIFY_ARGUMENT(InterruptId >= 0);
++
++ /* Cast the buffer pointer. */
++ buffer = (gctUINT32_PTR) Logical;
++
++ /* Append END. */
++ buffer[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) ((gctUINT32) (InterruptId) & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)));
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the END command. */
++ *Bytes = 8;
++ }
++ }
++ else
++ {
++ if (Logical != gcvNULL)
++ {
++ gctUINT32_PTR memory;
++
++ /* Verify the event ID. */
++ gcmkVERIFY_ARGUMENT(InterruptId >= 0);
++
++ /* Cast the buffer pointer. */
++ memory = (gctUINT32_PTR) Logical;
++
++ /* Append EVENT. */
++ memory[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E01) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ memory[1]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) ((gctUINT32) (InterruptId) & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6)));
++
++ /* Append END. */
++ memory[2]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x02 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the EVENT and END commands. */
++ *Bytes = 16;
++ }
++ }
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++#endif /* gcdENABLE_VG */
++
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/archvg/gc_hal_kernel_hardware_command_vg.h linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/archvg/gc_hal_kernel_hardware_command_vg.h
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/archvg/gc_hal_kernel_hardware_command_vg.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/archvg/gc_hal_kernel_hardware_command_vg.h 2015-07-27 23:13:06.190893891 +0200
+@@ -0,0 +1,319 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_kernel_hardware_command_vg_h_
++#define __gc_hal_kernel_hardware_command_vg_h_
++
++/******************************************************************************\
++******************* Task and Interrupt Management Structures. ******************
++\******************************************************************************/
++
++/* Task storage header. */
++typedef struct _gcsTASK_STORAGE * gcsTASK_STORAGE_PTR;
++typedef struct _gcsTASK_STORAGE
++{
++ /* Next allocated storage buffer. */
++ gcsTASK_STORAGE_PTR next;
++}
++gcsTASK_STORAGE;
++
++/* Task container header. */
++typedef struct _gcsTASK_CONTAINER * gcsTASK_CONTAINER_PTR;
++typedef struct _gcsTASK_CONTAINER
++{
++ /* The number of tasks left to be processed in the container. */
++ gctINT referenceCount;
++
++ /* Size of the buffer. */
++ gctUINT size;
++
++ /* Link to the previous and the next allocated containers. */
++ gcsTASK_CONTAINER_PTR allocPrev;
++ gcsTASK_CONTAINER_PTR allocNext;
++
++ /* Link to the previous and the next containers in the free list. */
++ gcsTASK_CONTAINER_PTR freePrev;
++ gcsTASK_CONTAINER_PTR freeNext;
++}
++gcsTASK_CONTAINER;
++
++/* Kernel space task master table entry. */
++typedef struct _gcsBLOCK_TASK_ENTRY * gcsBLOCK_TASK_ENTRY_PTR;
++typedef struct _gcsBLOCK_TASK_ENTRY
++{
++ /* Pointer to the current task container for the block. */
++ gcsTASK_CONTAINER_PTR container;
++
++ /* Pointer to the current task data within the container. */
++ gcsTASK_HEADER_PTR task;
++
++ /* Pointer to the last link task within the container. */
++ gcsTASK_LINK_PTR link;
++
++ /* Number of interrupts allocated for this block. */
++ gctUINT interruptCount;
++
++ /* The index of the current interrupt. */
++ gctUINT interruptIndex;
++
++ /* Interrupt semaphore. */
++ gctSEMAPHORE interruptSemaphore;
++
++ /* Interrupt value array. */
++ gctINT32 interruptArray[32];
++}
++gcsBLOCK_TASK_ENTRY;
++
++
++/******************************************************************************\
++********************* Command Queue Management Structures. *********************
++\******************************************************************************/
++
++/* Command queue kernel element pointer. */
++typedef struct _gcsKERNEL_CMDQUEUE * gcsKERNEL_CMDQUEUE_PTR;
++
++/* Command queue object handler function type. */
++typedef gceSTATUS (* gctOBJECT_HANDLER) (
++ gckVGKERNEL Kernel,
++ gcsKERNEL_CMDQUEUE_PTR Entry
++ );
++
++/* Command queue kernel element. */
++typedef struct _gcsKERNEL_CMDQUEUE
++{
++ /* The number of buffers in the queue. */
++ gcsCMDBUFFER_PTR commandBuffer;
++
++ /* Pointer to the object handler function. */
++ gctOBJECT_HANDLER handler;
++}
++gcsKERNEL_CMDQUEUE;
++
++/* Command queue header. */
++typedef struct _gcsKERNEL_QUEUE_HEADER * gcsKERNEL_QUEUE_HEADER_PTR;
++typedef struct _gcsKERNEL_QUEUE_HEADER
++{
++ /* The size of the buffer in bytes. */
++ gctUINT size;
++
++ /* The number of pending entries to be processed. */
++ volatile gctUINT pending;
++
++ /* The current command queue entry. */
++ gcsKERNEL_CMDQUEUE_PTR currentEntry;
++
++ /* Next buffer. */
++ gcsKERNEL_QUEUE_HEADER_PTR next;
++}
++gcsKERNEL_QUEUE_HEADER;
++
++
++/******************************************************************************\
++******************************* gckVGCOMMAND Object *******************************
++\******************************************************************************/
++
++/* gckVGCOMMAND object. */
++struct _gckVGCOMMAND
++{
++ /***************************************************************************
++ ** Object data and pointers.
++ */
++
++ gcsOBJECT object;
++ gckVGKERNEL kernel;
++ gckOS os;
++ gckVGHARDWARE hardware;
++
++ /* Features. */
++ gctBOOL fe20;
++ gctBOOL vg20;
++ gctBOOL vg21;
++
++
++ /***************************************************************************
++ ** Enable command queue dumping.
++ */
++
++ gctBOOL enableDumping;
++
++
++ /***************************************************************************
++ ** Bus Error interrupt.
++ */
++
++ gctINT32 busErrorInt;
++
++
++ /***************************************************************************
++ ** Command buffer information.
++ */
++
++ gcsCOMMAND_BUFFER_INFO info;
++
++
++ /***************************************************************************
++ ** Synchronization objects.
++ */
++
++ gctPOINTER queueMutex;
++ gctPOINTER taskMutex;
++ gctPOINTER commitMutex;
++
++
++ /***************************************************************************
++ ** Task management.
++ */
++
++ /* The head of the storage buffer linked list. */
++ gcsTASK_STORAGE_PTR taskStorage;
++
++ /* Allocation size. */
++ gctUINT taskStorageGranularity;
++ gctUINT taskStorageUsable;
++
++ /* The free container list. */
++ gcsTASK_CONTAINER_PTR taskFreeHead;
++ gcsTASK_CONTAINER_PTR taskFreeTail;
++
++ /* Task table */
++ gcsBLOCK_TASK_ENTRY taskTable[gcvBLOCK_COUNT];
++
++
++ /***************************************************************************
++ ** Command queue.
++ */
++
++ /* Pointer to the allocated queue memory. */
++ gcsKERNEL_QUEUE_HEADER_PTR queue;
++
++ /* Pointer to the current available queue from which new queue entries
++ will be allocated. */
++ gcsKERNEL_QUEUE_HEADER_PTR queueHead;
++
++ /* If different from queueHead, points to the command queue which is
++ currently being executed by the hardware. */
++ gcsKERNEL_QUEUE_HEADER_PTR queueTail;
++
++ /* Points to the queue to merge the tail with when the tail is processed. */
++ gcsKERNEL_QUEUE_HEADER_PTR mergeQueue;
++
++ /* Queue overflow counter. */
++ gctUINT queueOverflow;
++
++
++ /***************************************************************************
++ ** Context.
++ */
++
++ /* Context counter used for unique ID. */
++ gctUINT64 contextCounter;
++
++ /* Current context ID. */
++ gctUINT64 currentContext;
++
++ /* Command queue power semaphore. */
++ gctPOINTER powerSemaphore;
++ gctINT32 powerStallInt;
++ gcsCMDBUFFER_PTR powerStallBuffer;
++ gctSIGNAL powerStallSignal;
++
++};
++
++/******************************************************************************\
++************************ gckVGCOMMAND Object Internal API. ***********************
++\******************************************************************************/
++
++/* Initialize architecture dependent command buffer information. */
++gceSTATUS
++gckVGCOMMAND_InitializeInfo(
++ IN gckVGCOMMAND Command
++ );
++
++/* Form a STATE command at the specified location in the command buffer. */
++gceSTATUS
++gckVGCOMMAND_StateCommand(
++ IN gckVGCOMMAND Command,
++ IN gctUINT32 Pipe,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Address,
++ IN gctUINT32 Count,
++ IN OUT gctUINT32 * Bytes
++ );
++
++/* Form a RESTART command at the specified location in the command buffer. */
++gceSTATUS
++gckVGCOMMAND_RestartCommand(
++ IN gckVGCOMMAND Command,
++ IN gctPOINTER Logical,
++ IN gctUINT32 FetchAddress,
++ IN gctUINT FetchCount,
++ IN OUT gctUINT32 * Bytes
++ );
++
++/* Form a FETCH command at the specified location in the command buffer. */
++gceSTATUS
++gckVGCOMMAND_FetchCommand(
++ IN gckVGCOMMAND Command,
++ IN gctPOINTER Logical,
++ IN gctUINT32 FetchAddress,
++ IN gctUINT FetchCount,
++ IN OUT gctUINT32 * Bytes
++ );
++
++/* Form a CALL command at the specified location in the command buffer. */
++gceSTATUS
++gckVGCOMMAND_CallCommand(
++ IN gckVGCOMMAND Command,
++ IN gctPOINTER Logical,
++ IN gctUINT32 FetchAddress,
++ IN gctUINT FetchCount,
++ IN OUT gctUINT32 * Bytes
++ );
++
++/* Form a RETURN command at the specified location in the command buffer. */
++gceSTATUS
++gckVGCOMMAND_ReturnCommand(
++ IN gckVGCOMMAND Command,
++ IN gctPOINTER Logical,
++ IN OUT gctUINT32 * Bytes
++ );
++
++/* Form an EVENT command at the specified location in the command buffer. */
++gceSTATUS
++gckVGCOMMAND_EventCommand(
++ IN gckVGCOMMAND Command,
++ IN gctPOINTER Logical,
++ IN gceBLOCK Block,
++ IN gctINT32 InterruptId,
++ IN OUT gctUINT32 * Bytes
++ );
++
++/* Form an END command at the specified location in the command buffer. */
++gceSTATUS
++gckVGCOMMAND_EndCommand(
++ IN gckVGCOMMAND Command,
++ IN gctPOINTER Logical,
++ IN gctINT32 InterruptId,
++ IN OUT gctUINT32 * Bytes
++ );
++
++#endif /* __gc_hal_kernel_hardware_command_h_ */
++
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/archvg/gc_hal_kernel_hardware_vg.c linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/archvg/gc_hal_kernel_hardware_vg.c
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/archvg/gc_hal_kernel_hardware_vg.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/archvg/gc_hal_kernel_hardware_vg.c 2015-07-27 23:13:06.190893891 +0200
+@@ -0,0 +1,2119 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal.h"
++#include "gc_hal_kernel.h"
++#include "gc_hal_kernel_hardware_command_vg.h"
++
++#if gcdENABLE_VG
++
++#define _GC_OBJ_ZONE gcvZONE_HARDWARE
++
++typedef enum
++{
++ gcvPOWER_FLAG_INITIALIZE = 1 << 0,
++ gcvPOWER_FLAG_STALL = 1 << 1,
++ gcvPOWER_FLAG_STOP = 1 << 2,
++ gcvPOWER_FLAG_START = 1 << 3,
++ gcvPOWER_FLAG_RELEASE = 1 << 4,
++ gcvPOWER_FLAG_DELAY = 1 << 5,
++ gcvPOWER_FLAG_SAVE = 1 << 6,
++ gcvPOWER_FLAG_ACQUIRE = 1 << 7,
++ gcvPOWER_FLAG_POWER_OFF = 1 << 8,
++ gcvPOWER_FLAG_CLOCK_OFF = 1 << 9,
++ gcvPOWER_FLAG_CLOCK_ON = 1 << 10,
++ gcvPOWER_FLAG_NOP = 1 << 11,
++}
++gcePOWER_FLAGS;
++
++/******************************************************************************\
++********************************* Support Code *********************************
++\******************************************************************************/
++static gceSTATUS
++_ResetGPU(
++ IN gckOS Os
++ )
++{
++ gctUINT32 control, idle;
++ gceSTATUS status;
++
++ /* Read register. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Os,
++ gcvCORE_VG,
++ 0x00000,
++ &control));
++
++ for (;;)
++ {
++ /* Disable clock gating. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ gcvCORE_VG,
++ 0x00104,
++ 0x00000000));
++
++ /* Wait for clock being stable. */
++ gcmkONERROR(gckOS_Delay(Os, 1));
++
++ /* Isolate the GPU. */
++ control = ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19)));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ gcvCORE_VG,
++ 0x00000,
++ control));
++
++ /* Set soft reset. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ gcvCORE_VG,
++ 0x00000,
++ ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12)))));
++
++ /* Wait for reset. */
++ gcmkONERROR(gckOS_Delay(Os, 1));
++
++ /* Reset soft reset bit. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ gcvCORE_VG,
++ 0x00000,
++ ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12)))));
++
++ /* Reset GPU isolation. */
++ control = ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19)));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ gcvCORE_VG,
++ 0x00000,
++ control));
++
++ /* Read idle register. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Os,
++ gcvCORE_VG,
++ 0x00004,
++ &idle));
++
++ if ((((((gctUINT32) (idle)) >> (0 ? 0:0)) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1)))))) ) == 0)
++ {
++ continue;
++ }
++
++ /* Read reset register. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Os,
++ gcvCORE_VG,
++ 0x00000,
++ &control));
++
++ if (((((((gctUINT32) (control)) >> (0 ? 16:16)) & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1)))))) ) == 0)
++ || ((((((gctUINT32) (control)) >> (0 ? 17:17)) & ((gctUINT32) ((((1 ? 17:17) - (0 ? 17:17) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 17:17) - (0 ? 17:17) + 1)))))) ) == 0)
++ )
++ {
++ continue;
++ }
++
++ /* GPU is idle. */
++ break;
++ }
++
++ /* Success. */
++ return gcvSTATUS_OK;
++
++OnError:
++
++ /* Return the error. */
++ return status;
++}
++
++
++static gceSTATUS
++_IdentifyHardware(
++ IN gckOS Os,
++ OUT gceCHIPMODEL * ChipModel,
++ OUT gctUINT32 * ChipRevision,
++ OUT gctUINT32 * ChipFeatures,
++ OUT gctUINT32 * ChipMinorFeatures,
++ OUT gctUINT32 * ChipMinorFeatures2
++ )
++{
++ gceSTATUS status;
++ gctUINT32 chipIdentity;
++
++ do
++ {
++ /* Read chip identity register. */
++ gcmkERR_BREAK(gckOS_ReadRegisterEx(Os, gcvCORE_VG, 0x00018, &chipIdentity));
++
++ /* Special case for older graphic cores. */
++ if (((((gctUINT32) (chipIdentity)) >> (0 ? 31:24) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1)))))) == (0x01 & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))))
++ {
++ *ChipModel = gcv500;
++ *ChipRevision = (((((gctUINT32) (chipIdentity)) >> (0 ? 15:12)) & ((gctUINT32) ((((1 ? 15:12) - (0 ? 15:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:12) - (0 ? 15:12) + 1)))))) );
++ }
++
++ else
++ {
++ /* Read chip identity register. */
++ gcmkERR_BREAK(gckOS_ReadRegisterEx(Os, gcvCORE_VG,
++ 0x00020,
++ (gctUINT32 *) ChipModel));
++
++ /* Read CHIP_REV register. */
++ gcmkERR_BREAK(gckOS_ReadRegisterEx(Os, gcvCORE_VG,
++ 0x00024,
++ ChipRevision));
++ }
++
++ /* Read chip feature register. */
++ gcmkERR_BREAK(gckOS_ReadRegisterEx(
++ Os, gcvCORE_VG, 0x0001C, ChipFeatures
++ ));
++
++ /* Read chip minor feature register. */
++ gcmkERR_BREAK(gckOS_ReadRegisterEx(
++ Os, gcvCORE_VG, 0x00034, ChipMinorFeatures
++ ));
++
++ /* Read chip minor feature register #2. */
++ gcmkERR_BREAK(gckOS_ReadRegisterEx(
++ Os, gcvCORE_VG, 0x00074, ChipMinorFeatures2
++ ));
++
++ gcmkTRACE(
++ gcvLEVEL_VERBOSE,
++ "ChipModel=0x%08X\n"
++ "ChipRevision=0x%08X\n"
++ "ChipFeatures=0x%08X\n"
++ "ChipMinorFeatures=0x%08X\n"
++ "ChipMinorFeatures2=0x%08X\n",
++ *ChipModel,
++ *ChipRevision,
++ *ChipFeatures,
++ *ChipMinorFeatures,
++ *ChipMinorFeatures2
++ );
++
++ /* Success. */
++ return gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ /* Return the status. */
++ return status;
++}
++
++#if gcdPOWEROFF_TIMEOUT
++void
++_VGPowerTimerFunction(
++ gctPOINTER Data
++ )
++{
++ gckVGHARDWARE hardware = (gckVGHARDWARE)Data;
++ gcmkVERIFY_OK(
++ gckVGHARDWARE_SetPowerManagementState(hardware, gcvPOWER_OFF_TIMEOUT));
++}
++#endif
++
++/******************************************************************************\
++****************************** gckVGHARDWARE API code *****************************
++\******************************************************************************/
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_Construct
++**
++** Construct a new gckVGHARDWARE object.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an initialized gckOS object.
++**
++** OUTPUT:
++**
++** gckVGHARDWARE * Hardware
++** Pointer to a variable that will hold the pointer to the gckVGHARDWARE
++** object.
++*/
++gceSTATUS
++gckVGHARDWARE_Construct(
++ IN gckOS Os,
++ OUT gckVGHARDWARE * Hardware
++ )
++{
++ gckVGHARDWARE hardware = gcvNULL;
++ gceSTATUS status;
++ gceCHIPMODEL chipModel;
++ gctUINT32 chipRevision;
++ gctUINT32 chipFeatures;
++ gctUINT32 chipMinorFeatures;
++ gctUINT32 chipMinorFeatures2;
++
++ gcmkHEADER_ARG("Os=0x%x Hardware=0x%x ", Os, Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Hardware != gcvNULL);
++
++ do
++ {
++ gcmkERR_BREAK(gckOS_SetGPUPower(Os, gcvCORE_VG, gcvTRUE, gcvTRUE));
++
++ status = _ResetGPU(Os);
++
++ if (status != gcvSTATUS_OK)
++ {
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "_ResetGPU failed: status=%d\n", status);
++ }
++
++ /* Identify the hardware. */
++ gcmkERR_BREAK(_IdentifyHardware(Os,
++ &chipModel, &chipRevision,
++ &chipFeatures, &chipMinorFeatures, &chipMinorFeatures2
++ ));
++
++ /* Allocate the gckVGHARDWARE object. */
++ gcmkERR_BREAK(gckOS_Allocate(Os,
++ gcmSIZEOF(struct _gckVGHARDWARE), (gctPOINTER *) &hardware
++ ));
++
++ /* Initialize the gckVGHARDWARE object. */
++ hardware->object.type = gcvOBJ_HARDWARE;
++ hardware->os = Os;
++
++ /* Set chip identity. */
++ hardware->chipModel = chipModel;
++ hardware->chipRevision = chipRevision;
++ hardware->chipFeatures = chipFeatures;
++ hardware->chipMinorFeatures = chipMinorFeatures;
++ hardware->chipMinorFeatures2 = chipMinorFeatures2;
++
++ hardware->powerMutex = gcvNULL;
++ hardware->chipPowerState = gcvPOWER_ON;
++ hardware->chipPowerStateGlobal = gcvPOWER_ON;
++ hardware->clockState = gcvTRUE;
++ hardware->powerState = gcvTRUE;
++
++#if gcdPOWEROFF_TIMEOUT
++ hardware->powerOffTime = 0;
++ hardware->powerOffTimeout = gcdPOWEROFF_TIMEOUT;
++
++ gcmkVERIFY_OK(gckOS_CreateTimer(Os,
++ _VGPowerTimerFunction,
++ (gctPOINTER)hardware,
++ &hardware->powerOffTimer));
++#endif
++
++ /* Determine whether FE 2.0 is present. */
++ hardware->fe20 = ((((gctUINT32) (hardware->chipFeatures)) >> (0 ? 28:28) & ((gctUINT32) ((((1 ? 28:28) - (0 ? 28:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 28:28) - (0 ? 28:28) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 28:28) - (0 ? 28:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 28:28) - (0 ? 28:28) + 1)))))));
++
++ /* Determine whether VG 2.0 is present. */
++ hardware->vg20 = ((((gctUINT32) (hardware->chipMinorFeatures)) >> (0 ? 13:13) & ((gctUINT32) ((((1 ? 13:13) - (0 ? 13:13) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 13:13) - (0 ? 13:13) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 13:13) - (0 ? 13:13) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 13:13) - (0 ? 13:13) + 1)))))));
++
++ /* Determine whether VG 2.1 is present. */
++ hardware->vg21 = ((((gctUINT32) (hardware->chipMinorFeatures)) >> (0 ? 18:18) & ((gctUINT32) ((((1 ? 18:18) - (0 ? 18:18) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 18:18) - (0 ? 18:18) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 18:18) - (0 ? 18:18) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 18:18) - (0 ? 18:18) + 1)))))));
++
++ /* Set default event mask. */
++ hardware->eventMask = 0xFFFFFFFF;
++
++ gcmkERR_BREAK(gckOS_AtomConstruct(Os, &hardware->pageTableDirty));
++
++ /* Set fast clear to auto. */
++ gcmkVERIFY_OK(gckVGHARDWARE_SetFastClear(hardware, -1));
++
++ gcmkERR_BREAK(gckOS_CreateMutex(Os, &hardware->powerMutex));
++
++ /* Enable power management by default. */
++ hardware->powerManagement = gcvTRUE;
++
++ /* Return pointer to the gckVGHARDWARE object. */
++ *Hardware = hardware;
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++#if gcdPOWEROFF_TIMEOUT
++ if (hardware->powerOffTimer != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_StopTimer(Os, hardware->powerOffTimer));
++ gcmkVERIFY_OK(gckOS_DestroyTimer(Os, hardware->powerOffTimer));
++ }
++#endif
++
++ gcmkVERIFY_OK(gckOS_SetGPUPower(Os, gcvCORE_VG, gcvFALSE, gcvFALSE));
++
++ if (hardware != gcvNULL && hardware->pageTableDirty != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_AtomDestroy(Os, hardware->pageTableDirty));
++ }
++
++ if (hardware != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_Free(Os, hardware));
++ }
++
++ gcmkFOOTER();
++ /* Return the status. */
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_Destroy
++**
++** Destroy an gckVGHARDWARE object.
++**
++** INPUT:
++**
++** gckVGHARDWARE Hardware
++** Pointer to the gckVGHARDWARE object that needs to be destroyed.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckVGHARDWARE_Destroy(
++ IN gckVGHARDWARE Hardware
++ )
++{
++ gceSTATUS status;
++ gcmkHEADER_ARG("Hardware=0x%x ", Hardware);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Mark the object as unknown. */
++ Hardware->object.type = gcvOBJ_UNKNOWN;
++
++ if (Hardware->powerMutex != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_DeleteMutex(
++ Hardware->os, Hardware->powerMutex));
++ }
++
++#if gcdPOWEROFF_TIMEOUT
++ gcmkVERIFY_OK(gckOS_StopTimer(Hardware->os, Hardware->powerOffTimer));
++ gcmkVERIFY_OK(gckOS_DestroyTimer(Hardware->os, Hardware->powerOffTimer));
++#endif
++
++ if (Hardware->pageTableDirty != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_AtomDestroy(Hardware->os, Hardware->pageTableDirty));
++ }
++
++ /* Free the object. */
++ status = gckOS_Free(Hardware->os, Hardware);
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_QueryMemory
++**
++** Query the amount of memory available on the hardware.
++**
++** INPUT:
++**
++** gckVGHARDWARE Hardware
++** Pointer to the gckVGHARDWARE object.
++**
++** OUTPUT:
++**
++** gctSIZE_T * InternalSize
++** Pointer to a variable that will hold the size of the internal video
++** memory in bytes. If 'InternalSize' is gcvNULL, no information of the
++** internal memory will be returned.
++**
++** gctUINT32 * InternalBaseAddress
++** Pointer to a variable that will hold the hardware's base address for
++** the internal video memory. This pointer cannot be gcvNULL if
++** 'InternalSize' is also non-gcvNULL.
++**
++** gctUINT32 * InternalAlignment
++** Pointer to a variable that will hold the hardware's base address for
++** the internal video memory. This pointer cannot be gcvNULL if
++** 'InternalSize' is also non-gcvNULL.
++**
++** gctSIZE_T * ExternalSize
++** Pointer to a variable that will hold the size of the external video
++** memory in bytes. If 'ExternalSize' is gcvNULL, no information of the
++** external memory will be returned.
++**
++** gctUINT32 * ExternalBaseAddress
++** Pointer to a variable that will hold the hardware's base address for
++** the external video memory. This pointer cannot be gcvNULL if
++** 'ExternalSize' is also non-gcvNULL.
++**
++** gctUINT32 * ExternalAlignment
++** Pointer to a variable that will hold the hardware's base address for
++** the external video memory. This pointer cannot be gcvNULL if
++** 'ExternalSize' is also non-gcvNULL.
++**
++** gctUINT32 * HorizontalTileSize
++** Number of horizontal pixels per tile. If 'HorizontalTileSize' is
++** gcvNULL, no horizontal pixel per tile will be returned.
++**
++** gctUINT32 * VerticalTileSize
++** Number of vertical pixels per tile. If 'VerticalTileSize' is
++** gcvNULL, no vertical pixel per tile will be returned.
++*/
++gceSTATUS
++gckVGHARDWARE_QueryMemory(
++ IN gckVGHARDWARE Hardware,
++ OUT gctSIZE_T * InternalSize,
++ OUT gctUINT32 * InternalBaseAddress,
++ OUT gctUINT32 * InternalAlignment,
++ OUT gctSIZE_T * ExternalSize,
++ OUT gctUINT32 * ExternalBaseAddress,
++ OUT gctUINT32 * ExternalAlignment,
++ OUT gctUINT32 * HorizontalTileSize,
++ OUT gctUINT32 * VerticalTileSize
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x InternalSize=0x%x InternalBaseAddress=0x%x InternalAlignment=0x%x"
++ "ExternalSize=0x%x ExternalBaseAddress=0x%x ExternalAlignment=0x%x HorizontalTileSize=0x%x VerticalTileSize=0x%x",
++ Hardware, InternalSize, InternalBaseAddress, InternalAlignment,
++ ExternalSize, ExternalBaseAddress, ExternalAlignment, HorizontalTileSize, VerticalTileSize);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ if (InternalSize != gcvNULL)
++ {
++ /* No internal memory. */
++ *InternalSize = 0;
++ }
++
++ if (ExternalSize != gcvNULL)
++ {
++ /* No external memory. */
++ *ExternalSize = 0;
++ }
++
++ if (HorizontalTileSize != gcvNULL)
++ {
++ /* 4x4 tiles. */
++ *HorizontalTileSize = 4;
++ }
++
++ if (VerticalTileSize != gcvNULL)
++ {
++ /* 4x4 tiles. */
++ *VerticalTileSize = 4;
++ }
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_QueryChipIdentity
++**
++** Query the identity of the hardware.
++**
++** INPUT:
++**
++** gckVGHARDWARE Hardware
++** Pointer to the gckVGHARDWARE object.
++**
++** OUTPUT:
++**
++** gceCHIPMODEL * ChipModel
++** If 'ChipModel' is not gcvNULL, the variable it points to will
++** receive the model of the chip.
++**
++** gctUINT32 * ChipRevision
++** If 'ChipRevision' is not gcvNULL, the variable it points to will
++** receive the revision of the chip.
++**
++** gctUINT32 * ChipFeatures
++** If 'ChipFeatures' is not gcvNULL, the variable it points to will
++** receive the feature set of the chip.
++**
++** gctUINT32 * ChipMinorFeatures
++** If 'ChipMinorFeatures' is not gcvNULL, the variable it points to
++** will receive the minor feature set of the chip.
++**
++** gctUINT32 * ChipMinorFeatures2
++** If 'ChipMinorFeatures2' is not gcvNULL, the variable it points to
++** will receive the minor feature set of the chip.
++**
++*/
++gceSTATUS
++gckVGHARDWARE_QueryChipIdentity(
++ IN gckVGHARDWARE Hardware,
++ OUT gceCHIPMODEL * ChipModel,
++ OUT gctUINT32 * ChipRevision,
++ OUT gctUINT32* ChipFeatures,
++ OUT gctUINT32* ChipMinorFeatures,
++ OUT gctUINT32* ChipMinorFeatures2
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x ChipModel=0x%x ChipRevision=0x%x ChipFeatures = 0x%x ChipMinorFeatures = 0x%x ChipMinorFeatures2 = 0x%x",
++ Hardware, ChipModel, ChipRevision, ChipFeatures, ChipMinorFeatures, ChipMinorFeatures2);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Return chip model. */
++ if (ChipModel != gcvNULL)
++ {
++ *ChipModel = Hardware->chipModel;
++ }
++
++ /* Return revision number. */
++ if (ChipRevision != gcvNULL)
++ {
++ *ChipRevision = Hardware->chipRevision;
++ }
++
++ /* Return feature set. */
++ if (ChipFeatures != gcvNULL)
++ {
++ gctUINT32 features = Hardware->chipFeatures;
++
++ if ((((((gctUINT32) (features)) >> (0 ? 0:0)) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1)))))) ))
++ {
++ features = ((((gctUINT32) (features)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (Hardware->allowFastClear) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)));
++ }
++
++ /* Mark 2D pipe as available for GC500.0 since it did not have this *\
++ \* bit. */
++ if ((Hardware->chipModel == gcv500)
++ && (Hardware->chipRevision == 0)
++ )
++ {
++ features = ((((gctUINT32) (features)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9)));
++ }
++
++ /* Mark 2D pipe as available for GC300 since it did not have this *\
++ \* bit. */
++ if (Hardware->chipModel == gcv300)
++ {
++ features = ((((gctUINT32) (features)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9)));
++ }
++
++ *ChipFeatures = features;
++ }
++
++ /* Return minor feature set. */
++ if (ChipMinorFeatures != gcvNULL)
++ {
++ *ChipMinorFeatures = Hardware->chipMinorFeatures;
++ }
++
++ /* Return minor feature set #2. */
++ if (ChipMinorFeatures2 != gcvNULL)
++ {
++ *ChipMinorFeatures2 = Hardware->chipMinorFeatures2;
++ }
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_ConvertFormat
++**
++** Convert an API format to hardware parameters.
++**
++** INPUT:
++**
++** gckVGHARDWARE Hardware
++** Pointer to the gckVGHARDWARE object.
++**
++** gceSURF_FORMAT Format
++** API format to convert.
++**
++** OUTPUT:
++**
++** gctUINT32 * BitsPerPixel
++** Pointer to a variable that will hold the number of bits per pixel.
++**
++** gctUINT32 * BytesPerTile
++** Pointer to a variable that will hold the number of bytes per tile.
++*/
++gceSTATUS
++gckVGHARDWARE_ConvertFormat(
++ IN gckVGHARDWARE Hardware,
++ IN gceSURF_FORMAT Format,
++ OUT gctUINT32 * BitsPerPixel,
++ OUT gctUINT32 * BytesPerTile
++ )
++{
++ gctUINT32 bitsPerPixel;
++ gctUINT32 bytesPerTile;
++
++ gcmkHEADER_ARG("Hardware=0x%x Format=0x%x BitsPerPixel=0x%x BytesPerTile = 0x%x",
++ Hardware, Format, BitsPerPixel, BytesPerTile);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Dispatch on format. */
++ switch (Format)
++ {
++ case gcvSURF_A1:
++ case gcvSURF_L1:
++ /* 1-bpp format. */
++ bitsPerPixel = 1;
++ bytesPerTile = (1 * 4 * 4) / 8;
++ break;
++
++ case gcvSURF_A4:
++ /* 4-bpp format. */
++ bitsPerPixel = 4;
++ bytesPerTile = (4 * 4 * 4) / 8;
++ break;
++
++ case gcvSURF_INDEX8:
++ case gcvSURF_A8:
++ case gcvSURF_L8:
++ /* 8-bpp format. */
++ bitsPerPixel = 8;
++ bytesPerTile = (8 * 4 * 4) / 8;
++ break;
++
++ case gcvSURF_YV12:
++ /* 12-bpp planar YUV formats. */
++ bitsPerPixel = 12;
++ bytesPerTile = (12 * 4 * 4) / 8;
++ break;
++
++ case gcvSURF_NV12:
++ /* 12-bpp planar YUV formats. */
++ bitsPerPixel = 12;
++ bytesPerTile = (12 * 4 * 4) / 8;
++ break;
++
++ /* 4444 variations. */
++ case gcvSURF_X4R4G4B4:
++ case gcvSURF_A4R4G4B4:
++ case gcvSURF_R4G4B4X4:
++ case gcvSURF_R4G4B4A4:
++ case gcvSURF_B4G4R4X4:
++ case gcvSURF_B4G4R4A4:
++ case gcvSURF_X4B4G4R4:
++ case gcvSURF_A4B4G4R4:
++
++ /* 1555 variations. */
++ case gcvSURF_X1R5G5B5:
++ case gcvSURF_A1R5G5B5:
++ case gcvSURF_R5G5B5X1:
++ case gcvSURF_R5G5B5A1:
++ case gcvSURF_X1B5G5R5:
++ case gcvSURF_A1B5G5R5:
++ case gcvSURF_B5G5R5X1:
++ case gcvSURF_B5G5R5A1:
++
++ /* 565 variations. */
++ case gcvSURF_R5G6B5:
++ case gcvSURF_B5G6R5:
++
++ case gcvSURF_A8L8:
++ case gcvSURF_YUY2:
++ case gcvSURF_UYVY:
++ case gcvSURF_D16:
++ /* 16-bpp format. */
++ bitsPerPixel = 16;
++ bytesPerTile = (16 * 4 * 4) / 8;
++ break;
++
++ case gcvSURF_X8R8G8B8:
++ case gcvSURF_A8R8G8B8:
++ case gcvSURF_X8B8G8R8:
++ case gcvSURF_A8B8G8R8:
++ case gcvSURF_R8G8B8X8:
++ case gcvSURF_R8G8B8A8:
++ case gcvSURF_B8G8R8X8:
++ case gcvSURF_B8G8R8A8:
++ case gcvSURF_D32:
++ /* 32-bpp format. */
++ bitsPerPixel = 32;
++ bytesPerTile = (32 * 4 * 4) / 8;
++ break;
++
++ case gcvSURF_D24S8:
++ /* 24-bpp format. */
++ bitsPerPixel = 32;
++ bytesPerTile = (32 * 4 * 4) / 8;
++ break;
++
++ case gcvSURF_DXT1:
++ case gcvSURF_ETC1:
++ bitsPerPixel = 4;
++ bytesPerTile = (4 * 4 * 4) / 8;
++ break;
++
++ case gcvSURF_DXT2:
++ case gcvSURF_DXT3:
++ case gcvSURF_DXT4:
++ case gcvSURF_DXT5:
++ bitsPerPixel = 8;
++ bytesPerTile = (8 * 4 * 4) / 8;
++ break;
++
++ default:
++ /* Invalid format. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_INVALID_ARGUMENT;
++ }
++
++ /* Set the result. */
++ if (BitsPerPixel != gcvNULL)
++ {
++ * BitsPerPixel = bitsPerPixel;
++ }
++
++ if (BytesPerTile != gcvNULL)
++ {
++ * BytesPerTile = bytesPerTile;
++ }
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_SplitMemory
++**
++** Split a hardware specific memory address into a pool and offset.
++**
++** INPUT:
++**
++** gckVGHARDWARE Hardware
++** Pointer to the gckVGHARDWARE object.
++**
++** gctUINT32 Address
++** Address in hardware specific format.
++**
++** OUTPUT:
++**
++** gcePOOL * Pool
++** Pointer to a variable that will hold the pool type for the address.
++**
++** gctUINT32 * Offset
++** Pointer to a variable that will hold the offset for the address.
++*/
++gceSTATUS
++gckVGHARDWARE_SplitMemory(
++ IN gckVGHARDWARE Hardware,
++ IN gctUINT32 Address,
++ OUT gcePOOL * Pool,
++ OUT gctUINT32 * Offset
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x Address=0x%x Pool=0x%x Offset = 0x%x",
++ Hardware, Address, Pool, Offset);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(Pool != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Offset != gcvNULL);
++
++ /* Dispatch on memory type. */
++ switch ((((((gctUINT32) (Address)) >> (0 ? 1:0)) & ((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1)))))) ))
++ {
++ case 0x0:
++ /* System memory. */
++ *Pool = gcvPOOL_SYSTEM;
++ break;
++
++ case 0x2:
++ /* Virtual memory. */
++ *Pool = gcvPOOL_VIRTUAL;
++ break;
++
++ default:
++ /* Invalid memory type. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_INVALID_ARGUMENT;
++ }
++
++ /* Return offset of address. */
++ *Offset = ((((gctUINT32) (Address)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0)));
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_Execute
++**
++** Kickstart the hardware's command processor with an initialized command
++** buffer.
++**
++** INPUT:
++**
++** gckVGHARDWARE Hardware
++** Pointer to the gckVGHARDWARE object.
++**
++** gctUINT32 Address
++** Address of the command buffer.
++**
++** gctSIZE_T Count
++** Number of command-sized data units to be executed.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckVGHARDWARE_Execute(
++ IN gckVGHARDWARE Hardware,
++ IN gctUINT32 Address,
++ IN gctUINT32 Count
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Hardware=0x%x Address=0x%x Count=0x%x",
++ Hardware, Address, Count);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ do
++ {
++ /* Enable all events. */
++ gcmkERR_BREAK(gckOS_WriteRegisterEx(
++ Hardware->os,
++ gcvCORE_VG,
++ 0x00014,
++ Hardware->eventMask
++ ));
++
++ if (Hardware->fe20)
++ {
++ /* Write address register. */
++ gcmkERR_BREAK(gckOS_WriteRegisterEx(
++ Hardware->os,
++ gcvCORE_VG,
++ 0x00500,
++ gcmkFIXADDRESS(Address)
++ ));
++
++ /* Write control register. */
++ gcmkERR_BREAK(gckOS_WriteRegisterEx(
++ Hardware->os,
++ gcvCORE_VG,
++ 0x00504,
++ Count
++ ));
++ }
++ else
++ {
++ /* Write address register. */
++ gcmkERR_BREAK(gckOS_WriteRegisterEx(
++ Hardware->os,
++ gcvCORE_VG,
++ 0x00654,
++ gcmkFIXADDRESS(Address)
++ ));
++
++ /* Write control register. */
++ gcmkERR_BREAK(gckOS_WriteRegisterEx(
++ Hardware->os,
++ gcvCORE_VG,
++ 0x00658,
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) << (0 ? 16:16))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) << (0 ? 16:16))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (Count) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ ));
++ }
++
++ /* Success. */
++ gcmkFOOTER();
++ return gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++
++ gcmkFOOTER();
++ /* Return the status. */
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_AlignToTile
++**
++** Align the specified width and height to tile boundaries.
++**
++** INPUT:
++**
++** gckVGHARDWARE Hardware
++** Pointer to an gckVGHARDWARE object.
++**
++** gceSURF_TYPE Type
++** Type of alignment.
++**
++** gctUINT32 * Width
++** Pointer to the width to be aligned. If 'Width' is gcvNULL, no width
++** will be aligned.
++**
++** gctUINT32 * Height
++** Pointer to the height to be aligned. If 'Height' is gcvNULL, no height
++** will be aligned.
++**
++** OUTPUT:
++**
++** gctUINT32 * Width
++** Pointer to a variable that will receive the aligned width.
++**
++** gctUINT32 * Height
++** Pointer to a variable that will receive the aligned height.
++*/
++gceSTATUS
++gckVGHARDWARE_AlignToTile(
++ IN gckVGHARDWARE Hardware,
++ IN gceSURF_TYPE Type,
++ IN OUT gctUINT32 * Width,
++ IN OUT gctUINT32 * Height
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x Type=0x%x Width=0x%x Height=0x%x",
++ Hardware, Type, Width, Height);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ if (Width != gcvNULL)
++ {
++ /* Align the width. */
++ *Width = gcmALIGN(*Width, (Type == gcvSURF_TEXTURE) ? 4 : 16);
++ }
++
++ if (Height != gcvNULL)
++ {
++ /* Special case for VG images. */
++ if ((*Height == 0) && (Type == gcvSURF_IMAGE))
++ {
++ *Height = 4;
++ }
++ else
++ {
++ /* Align the height. */
++ *Height = gcmALIGN(*Height, 4);
++ }
++ }
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_ConvertLogical
++**
++** Convert a logical system address into a hardware specific address.
++**
++** INPUT:
++**
++** gckVGHARDWARE Hardware
++** Pointer to an gckVGHARDWARE object.
++**
++** gctPOINTER Logical
++** Logical address to convert.
++**
++** gctBOOL InUserSpace
++** gcvTRUE if the memory in user space.
++**
++** gctUINT32* Address
++** Return hardware specific address.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckVGHARDWARE_ConvertLogical(
++ IN gckVGHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN gctBOOL InUserSpace,
++ OUT gctUINT32 * Address
++ )
++{
++ gctUINT32 address;
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x InUserSpace=%d Address=0x%x",
++ Hardware, Logical, InUserSpace, Address);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Address != gcvNULL);
++
++ do
++ {
++ /* Convert logical address into a physical address. */
++ if (InUserSpace)
++ {
++ gcmkERR_BREAK(gckOS_UserLogicalToPhysical(
++ Hardware->os, Logical, &address
++ ));
++ }
++ else
++ {
++ gcmkERR_BREAK(gckOS_GetPhysicalAddress(
++ Hardware->os, Logical, &address
++ ));
++ }
++
++ /* Return hardware specific address. */
++ *Address = ((((gctUINT32) (address)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0)));
++
++ /* Success. */
++ gcmkFOOTER();
++ return gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ gcmkFOOTER();
++ /* Return the status. */
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_QuerySystemMemory
++**
++** Query the command buffer alignment and number of reserved bytes.
++**
++** INPUT:
++**
++** gckVGHARDWARE Harwdare
++** Pointer to an gckVGHARDWARE object.
++**
++** OUTPUT:
++**
++** gctSIZE_T * SystemSize
++** Pointer to a variable that receives the maximum size of the system
++** memory.
++**
++** gctUINT32 * SystemBaseAddress
++** Poinetr to a variable that receives the base address for system
++** memory.
++*/
++gceSTATUS gckVGHARDWARE_QuerySystemMemory(
++ IN gckVGHARDWARE Hardware,
++ OUT gctSIZE_T * SystemSize,
++ OUT gctUINT32 * SystemBaseAddress
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x SystemSize=0x%x SystemBaseAddress=0x%x",
++ Hardware, SystemSize, SystemBaseAddress);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ if (SystemSize != gcvNULL)
++ {
++ /* Maximum system memory can be 2GB. */
++ *SystemSize = (gctSIZE_T)(1 << 31);
++ }
++
++ if (SystemBaseAddress != gcvNULL)
++ {
++ /* Set system memory base address. */
++ *SystemBaseAddress = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0)));
++ }
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_SetMMU
++**
++** Set the page table base address.
++**
++** INPUT:
++**
++** gckVGHARDWARE Harwdare
++** Pointer to an gckVGHARDWARE object.
++**
++** gctPOINTER Logical
++** Logical address of the page table.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS gckVGHARDWARE_SetMMU(
++ IN gckVGHARDWARE Hardware,
++ IN gctPOINTER Logical
++ )
++{
++ gceSTATUS status;
++ gctUINT32 address = 0;
++
++ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x",
++ Hardware, Logical);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++
++ do
++ {
++ /* Convert the logical address into an hardware address. */
++ gcmkERR_BREAK(gckVGHARDWARE_ConvertLogical(Hardware, Logical,
++ gcvFALSE, &address));
++
++ /* Write the AQMemoryFePageTable register. */
++ gcmkERR_BREAK(gckOS_WriteRegisterEx(Hardware->os, gcvCORE_VG,
++ 0x00400,
++ gcmkFIXADDRESS(address)));
++
++ /* Write the AQMemoryTxPageTable register. */
++ gcmkERR_BREAK(gckOS_WriteRegisterEx(Hardware->os, gcvCORE_VG,
++ 0x00404,
++ gcmkFIXADDRESS(address)));
++
++ /* Write the AQMemoryPePageTable register. */
++ gcmkERR_BREAK(gckOS_WriteRegisterEx(Hardware->os, gcvCORE_VG,
++ 0x00408,
++ gcmkFIXADDRESS(address)));
++
++ /* Write the AQMemoryPezPageTable register. */
++ gcmkERR_BREAK(gckOS_WriteRegisterEx(Hardware->os, gcvCORE_VG,
++ 0x0040C,
++ gcmkFIXADDRESS(address)));
++
++ /* Write the AQMemoryRaPageTable register. */
++ gcmkERR_BREAK(gckOS_WriteRegisterEx(Hardware->os, gcvCORE_VG,
++ 0x00410,
++ gcmkFIXADDRESS(address)));
++ }
++ while (gcvFALSE);
++
++ gcmkFOOTER();
++ /* Return the status. */
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_FlushMMU
++**
++** Flush the page table.
++**
++** INPUT:
++**
++** gckVGHARDWARE Harwdare
++** Pointer to an gckVGHARDWARE object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS gckVGHARDWARE_FlushMMU(
++ IN gckVGHARDWARE Hardware
++ )
++{
++ gceSTATUS status;
++ gckVGCOMMAND command;
++
++ gcmkHEADER_ARG("Hardware=0x%x ", Hardware);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ do
++ {
++ gcsCMDBUFFER_PTR commandBuffer;
++ gctUINT32_PTR buffer;
++
++ /* Create a shortcut to the command buffer object. */
++ command = Hardware->kernel->command;
++
++ /* Allocate command buffer space. */
++ gcmkERR_BREAK(gckVGCOMMAND_Allocate(
++ command, 8, &commandBuffer, (gctPOINTER *) &buffer
++ ));
++
++ buffer[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E04) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ buffer[1]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4)));
++ }
++ while(gcvFALSE);
++
++ gcmkFOOTER();
++ /* Return the status. */
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_BuildVirtualAddress
++**
++** Build a virtual address.
++**
++** INPUT:
++**
++** gckVGHARDWARE Harwdare
++** Pointer to an gckVGHARDWARE object.
++**
++** gctUINT32 Index
++** Index into page table.
++**
++** gctUINT32 Offset
++** Offset into page.
++**
++** OUTPUT:
++**
++** gctUINT32 * Address
++** Pointer to a variable receiving te hardware address.
++*/
++gceSTATUS gckVGHARDWARE_BuildVirtualAddress(
++ IN gckVGHARDWARE Hardware,
++ IN gctUINT32 Index,
++ IN gctUINT32 Offset,
++ OUT gctUINT32 * Address
++ )
++{
++ gctUINT32 address;
++
++ gcmkHEADER_ARG("Hardware=0x%x Index=0x%x Offset=0x%x Address=0x%x",
++ Hardware, Index, Offset, Address);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(Address != gcvNULL);
++
++ /* Build virtual address. */
++ address = (Index << 12) | Offset;
++
++ /* Set virtual type. */
++ address = ((((gctUINT32) (address)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0))) | (((gctUINT32) (0x2 & ((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0)));
++
++ /* Set the result. */
++ *Address = address;
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckVGHARDWARE_GetIdle(
++ IN gckVGHARDWARE Hardware,
++ OUT gctUINT32 * Data
++ )
++{
++ gceSTATUS status;
++ gcmkHEADER_ARG("Hardware=0x%x Data=0x%x", Hardware, Data);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(Data != gcvNULL);
++
++ /* Read register and return. */
++ status = gckOS_ReadRegisterEx(Hardware->os, gcvCORE_VG, 0x00004, Data);
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckVGHARDWARE_SetFastClear(
++ IN gckVGHARDWARE Hardware,
++ IN gctINT Enable
++ )
++{
++ gctUINT32 debug;
++ gceSTATUS status;
++
++ if (!(((((gctUINT32) (Hardware->chipFeatures)) >> (0 ? 0:0)) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1)))))) ))
++ {
++ return gcvSTATUS_OK;
++ }
++
++ do
++ {
++ if (Enable == -1)
++ {
++ Enable = (Hardware->chipModel > gcv500) ||
++ ((Hardware->chipModel == gcv500) && (Hardware->chipRevision >= 3));
++ }
++
++ gcmkERR_BREAK(gckOS_ReadRegisterEx(Hardware->os, gcvCORE_VG,
++ 0x00414,
++ &debug));
++
++ debug = ((((gctUINT32) (debug)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 20:20) - (0 ? 20:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:20) - (0 ? 20:20) + 1))))))) << (0 ? 20:20))) | (((gctUINT32) ((gctUINT32) (Enable == 0) & ((gctUINT32) ((((1 ? 20:20) - (0 ? 20:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:20) - (0 ? 20:20) + 1))))))) << (0 ? 20:20)));
++
++#ifdef AQ_MEMORY_DEBUG_DISABLE_Z_COMPRESSION
++ debug = ((((gctUINT32) (debug)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? AQ_MEMORY_DEBUG_DISABLE_Z_COMPRESSION) - (0 ? AQ_MEMORY_DEBUG_DISABLE_Z_COMPRESSION) + 1) == 32) ? ~0 : (~(~0 << ((1 ? AQ_MEMORY_DEBUG_DISABLE_Z_COMPRESSION) - (0 ? AQ_MEMORY_DEBUG_DISABLE_Z_COMPRESSION) + 1))))))) << (0 ? AQ_MEMORY_DEBUG_DISABLE_Z_COMPRESSION))) | (((gctUINT32) ((gctUINT32) (Enable == 0) & ((gctUINT32) ((((1 ? AQ_MEMORY_DEBUG_DISABLE_Z_COMPRESSION) - (0 ? AQ_MEMORY_DEBUG_DISABLE_Z_COMPRESSION) + 1) == 32) ? ~0 : (~(~0 << ((1 ? AQ_MEMORY_DEBUG_DISABLE_Z_COMPRESSION) - (0 ? AQ_MEMORY_DEBUG_DISABLE_Z_COMPRESSION) + 1))))))) << (0 ? AQ_MEMORY_DEBUG_DISABLE_Z_COMPRESSION)));
++#endif
++
++ gcmkERR_BREAK(gckOS_WriteRegisterEx(Hardware->os, gcvCORE_VG,
++ 0x00414,
++ debug));
++
++ Hardware->allowFastClear = Enable;
++
++ status = gcvFALSE;
++ }
++ while (gcvFALSE);
++
++ return status;
++}
++
++gceSTATUS
++gckVGHARDWARE_ReadInterrupt(
++ IN gckVGHARDWARE Hardware,
++ OUT gctUINT32_PTR IDs
++ )
++{
++ gceSTATUS status;
++ gcmkHEADER_ARG("Hardware=0x%x IDs=0x%x", Hardware, IDs);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(IDs != gcvNULL);
++
++ /* Read AQIntrAcknowledge register. */
++ status = gckOS_ReadRegisterEx(Hardware->os, gcvCORE_VG,
++ 0x00010,
++ IDs);
++ gcmkFOOTER();
++ return status;
++}
++
++static gceSTATUS _CommandStall(
++ gckVGHARDWARE Hardware)
++{
++ gceSTATUS status;
++ gckVGCOMMAND command;
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ do
++ {
++ gctUINT32_PTR buffer;
++ command = Hardware->kernel->command;
++
++ /* Allocate command buffer space. */
++ gcmkERR_BREAK(gckVGCOMMAND_Allocate(
++ command, 8, &command->powerStallBuffer,
++ (gctPOINTER *) &buffer
++ ));
++
++ gcmkERR_BREAK(gckVGCOMMAND_EventCommand(
++ command, buffer, gcvBLOCK_PIXEL,
++ command->powerStallInt, gcvNULL));
++
++ gcmkERR_BREAK(gckVGCOMMAND_Execute(
++ command,
++ command->powerStallBuffer
++ ));
++
++ /* Wait the signal. */
++ gcmkERR_BREAK(gckOS_WaitSignal(
++ command->os,
++ command->powerStallSignal,
++ command->kernel->kernel->timeOut));
++
++
++ }
++ while(gcvFALSE);
++
++ gcmkFOOTER();
++ /* Return the status. */
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_SetPowerManagementState
++**
++** Set GPU to a specified power state.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** gceCHIPPOWERSTATE State
++** Power State.
++**
++*/
++gceSTATUS
++gckVGHARDWARE_SetPowerManagementState(
++ IN gckVGHARDWARE Hardware,
++ IN gceCHIPPOWERSTATE State
++ )
++{
++ gceSTATUS status;
++ gckVGCOMMAND command = gcvNULL;
++ gckOS os;
++ gctUINT flag/*, clock*/;
++
++ gctBOOL acquired = gcvFALSE;
++ gctBOOL stall = gcvTRUE;
++ gctBOOL commitMutex = gcvFALSE;
++ gctBOOL mutexAcquired = gcvFALSE;
++
++#if gcdPOWEROFF_TIMEOUT
++ gctBOOL timeout = gcvFALSE;
++ gctBOOL isAfter = gcvFALSE;
++ gctUINT32 currentTime;
++#endif
++
++ gctBOOL broadcast = gcvFALSE;
++ gctUINT32 process, thread;
++ gctBOOL global = gcvFALSE;
++
++#if gcdENABLE_PROFILING
++ gctUINT64 time, freq, mutexTime, onTime, stallTime, stopTime, delayTime,
++ initTime, offTime, startTime, totalTime;
++#endif
++
++ /* State transition flags. */
++ static const gctUINT flags[4][4] =
++ {
++ /* gcvPOWER_ON */
++ { /* ON */ 0,
++ /* OFF */ gcvPOWER_FLAG_ACQUIRE |
++ gcvPOWER_FLAG_STALL |
++ gcvPOWER_FLAG_STOP |
++ gcvPOWER_FLAG_POWER_OFF |
++ gcvPOWER_FLAG_CLOCK_OFF,
++ /* IDLE */ gcvPOWER_FLAG_NOP,
++ /* SUSPEND */ gcvPOWER_FLAG_ACQUIRE |
++ gcvPOWER_FLAG_STALL |
++ gcvPOWER_FLAG_STOP |
++ gcvPOWER_FLAG_CLOCK_OFF,
++ },
++
++ /* gcvPOWER_OFF */
++ { /* ON */ gcvPOWER_FLAG_INITIALIZE |
++ gcvPOWER_FLAG_START |
++ gcvPOWER_FLAG_RELEASE |
++ gcvPOWER_FLAG_DELAY,
++ /* OFF */ 0,
++ /* IDLE */ gcvPOWER_FLAG_INITIALIZE |
++ gcvPOWER_FLAG_START |
++ gcvPOWER_FLAG_RELEASE |
++ gcvPOWER_FLAG_DELAY,
++ /* SUSPEND */ gcvPOWER_FLAG_INITIALIZE |
++ gcvPOWER_FLAG_CLOCK_OFF,
++ },
++
++ /* gcvPOWER_IDLE */
++ { /* ON */ gcvPOWER_FLAG_NOP,
++ /* OFF */ gcvPOWER_FLAG_ACQUIRE |
++ gcvPOWER_FLAG_STOP |
++ gcvPOWER_FLAG_POWER_OFF |
++ gcvPOWER_FLAG_CLOCK_OFF,
++ /* IDLE */ 0,
++ /* SUSPEND */ gcvPOWER_FLAG_ACQUIRE |
++ gcvPOWER_FLAG_STOP |
++ gcvPOWER_FLAG_CLOCK_OFF,
++ },
++
++ /* gcvPOWER_SUSPEND */
++ { /* ON */ gcvPOWER_FLAG_START |
++ gcvPOWER_FLAG_RELEASE |
++ gcvPOWER_FLAG_DELAY |
++ gcvPOWER_FLAG_CLOCK_ON,
++ /* OFF */ gcvPOWER_FLAG_SAVE |
++ gcvPOWER_FLAG_POWER_OFF |
++ gcvPOWER_FLAG_CLOCK_OFF,
++ /* IDLE */ gcvPOWER_FLAG_START |
++ gcvPOWER_FLAG_DELAY |
++ gcvPOWER_FLAG_RELEASE |
++ gcvPOWER_FLAG_CLOCK_ON,
++ /* SUSPEND */ 0,
++ },
++ };
++
++ gcmkHEADER_ARG("Hardware=0x%x State=%d", Hardware, State);
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Switching to power state %d",
++ State);
++#endif
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Get the gckOS object pointer. */
++ os = Hardware->os;
++ gcmkVERIFY_OBJECT(os, gcvOBJ_OS);
++
++ /* Get the gckCOMMAND object pointer. */
++ gcmkVERIFY_OBJECT(Hardware->kernel, gcvOBJ_KERNEL);
++ command = Hardware->kernel->command;
++ gcmkVERIFY_OBJECT(command, gcvOBJ_COMMAND);
++
++ if (Hardware->powerManagement == gcvFALSE)
++ {
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++
++ /* Start profiler. */
++ gcmkPROFILE_INIT(freq, time);
++
++ /* Convert the broadcast power state. */
++ switch (State)
++ {
++ case gcvPOWER_SUSPEND_ATPOWERON:
++ /* Convert to SUSPEND and don't wait for STALL. */
++ State = gcvPOWER_SUSPEND;
++ stall = gcvFALSE;
++ break;
++
++ case gcvPOWER_OFF_ATPOWERON:
++ /* Convert to OFF and don't wait for STALL. */
++ State = gcvPOWER_OFF;
++ stall = gcvFALSE;
++ break;
++
++ case gcvPOWER_IDLE_BROADCAST:
++ /* Convert to IDLE and note we are inside broadcast. */
++ State = gcvPOWER_IDLE;
++ broadcast = gcvTRUE;
++ break;
++
++ case gcvPOWER_SUSPEND_BROADCAST:
++ /* Convert to SUSPEND and note we are inside broadcast. */
++ State = gcvPOWER_SUSPEND;
++ broadcast = gcvTRUE;
++ break;
++
++ case gcvPOWER_OFF_BROADCAST:
++ /* Convert to OFF and note we are inside broadcast. */
++ State = gcvPOWER_OFF;
++ broadcast = gcvTRUE;
++ break;
++
++ case gcvPOWER_OFF_RECOVERY:
++ /* Convert to OFF and note we are inside recovery. */
++ State = gcvPOWER_OFF;
++ stall = gcvFALSE;
++ broadcast = gcvTRUE;
++ break;
++
++ case gcvPOWER_ON_AUTO:
++ /* Convert to ON and note we are inside recovery. */
++ State = gcvPOWER_ON;
++ break;
++
++ case gcvPOWER_ON:
++ case gcvPOWER_IDLE:
++ case gcvPOWER_SUSPEND:
++ case gcvPOWER_OFF:
++ /* Mark as global power management. */
++ global = gcvTRUE;
++ break;
++
++#if gcdPOWEROFF_TIMEOUT
++ case gcvPOWER_OFF_TIMEOUT:
++ /* Convert to OFF and note we are inside broadcast. */
++ State = gcvPOWER_OFF;
++ broadcast = gcvTRUE;
++ /* Check time out */
++ timeout = gcvTRUE;
++ break;
++#endif
++
++ default:
++ break;
++ }
++
++ /* Get current process and thread IDs. */
++ gcmkONERROR(gckOS_GetProcessID(&process));
++ gcmkONERROR(gckOS_GetThreadID(&thread));
++
++ /* Acquire the power mutex. */
++ if (broadcast)
++ {
++ /* Try to acquire the power mutex. */
++ status = gckOS_AcquireMutex(os, Hardware->powerMutex, 0);
++
++ if (status == gcvSTATUS_TIMEOUT)
++ {
++ /* Check if we already own this mutex. */
++ if ((Hardware->powerProcess == process)
++ && (Hardware->powerThread == thread)
++ )
++ {
++ /* Bail out on recursive power management. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++ else if (State == gcvPOWER_IDLE)
++ {
++ /* gcvPOWER_IDLE_BROADCAST is from IST,
++ ** so waiting here will cause deadlock,
++ ** if lock holder call gckCOMMAND_Stall() */
++ gcmkONERROR(gcvSTATUS_INVALID_REQUEST);
++ }
++ else
++ {
++ /* Acquire the power mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(os,
++ Hardware->powerMutex,
++ gcvINFINITE));
++ }
++ }
++ }
++ else
++ {
++ /* Acquire the power mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(os, Hardware->powerMutex, gcvINFINITE));
++ }
++
++ /* Get time until mtuex acquired. */
++ gcmkPROFILE_QUERY(time, mutexTime);
++
++ Hardware->powerProcess = process;
++ Hardware->powerThread = thread;
++ mutexAcquired = gcvTRUE;
++
++ /* Grab control flags and clock. */
++ flag = flags[Hardware->chipPowerState][State];
++ /*clock = clocks[State];*/
++
++#if gcdPOWEROFF_TIMEOUT
++ if (timeout)
++ {
++ gcmkONERROR(gckOS_GetTicks(&currentTime));
++
++ gcmkONERROR(
++ gckOS_TicksAfter(Hardware->powerOffTime, currentTime, &isAfter));
++
++ /* powerOffTime is pushed forward, give up.*/
++ if (isAfter
++ /* Expect a transition start from IDLE. */
++ || (Hardware->chipPowerState == gcvPOWER_ON)
++ || (Hardware->chipPowerState == gcvPOWER_OFF)
++ )
++ {
++ /* Release the power mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(os, Hardware->powerMutex));
++
++ /* No need to do anything. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++ }
++#endif
++
++ if (flag == 0)
++ {
++ /* Release the power mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(os, Hardware->powerMutex));
++
++ /* No need to do anything. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++
++ /* internal power control */
++ if (!global)
++ {
++ if (Hardware->chipPowerStateGlobal == gcvPOWER_OFF)
++ {
++ /* Release the power mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(os, Hardware->powerMutex));
++
++ /* No need to do anything. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++ }
++ else
++ {
++ if (flag & gcvPOWER_FLAG_ACQUIRE)
++ {
++ /* Acquire the power management semaphore. */
++ gcmkONERROR(gckOS_AcquireSemaphore(os, command->powerSemaphore));
++ acquired = gcvTRUE;
++
++ /* avoid acquiring again. */
++ flag &= ~gcvPOWER_FLAG_ACQUIRE;
++ }
++ }
++
++ if (flag & (gcvPOWER_FLAG_INITIALIZE | gcvPOWER_FLAG_CLOCK_ON))
++ {
++ /* Turn on the power. */
++ gcmkONERROR(gckOS_SetGPUPower(os, gcvCORE_VG, gcvTRUE, gcvTRUE));
++
++ /* Mark clock and power as enabled. */
++ Hardware->clockState = gcvTRUE;
++ Hardware->powerState = gcvTRUE;
++ }
++
++ /* Get time until powered on. */
++ gcmkPROFILE_QUERY(time, onTime);
++
++ if ((flag & gcvPOWER_FLAG_STALL) && stall)
++ {
++ /* Acquire the mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(
++ command->os,
++ command->commitMutex,
++ gcvINFINITE
++ ));
++
++ commitMutex = gcvTRUE;
++
++ gcmkONERROR(_CommandStall(Hardware));
++ }
++
++ /* Get time until stalled. */
++ gcmkPROFILE_QUERY(time, stallTime);
++
++ if (flag & gcvPOWER_FLAG_ACQUIRE)
++ {
++ /* Acquire the power management semaphore. */
++ gcmkONERROR(gckOS_AcquireSemaphore(os, command->powerSemaphore));
++
++ acquired = gcvTRUE;
++ }
++
++
++ /* Get time until stopped. */
++ gcmkPROFILE_QUERY(time, stopTime);
++
++
++ if (flag & gcvPOWER_FLAG_DELAY)
++ {
++ /* Wait for the specified amount of time to settle coming back from
++ ** power-off or suspend state. */
++ gcmkONERROR(gckOS_Delay(os, gcdPOWER_CONTROL_DELAY));
++ }
++
++ /* Get time until delayed. */
++ gcmkPROFILE_QUERY(time, delayTime);
++
++ if (flag & gcvPOWER_FLAG_INITIALIZE)
++ {
++
++ /* Initialize GPU here, replaced by InitializeHardware later */
++ gcmkONERROR(gckVGHARDWARE_SetMMU(Hardware, Hardware->kernel->mmu->pageTableLogical));
++ gcmkVERIFY_OK(gckVGHARDWARE_SetFastClear(Hardware, -1));
++
++ /* Force the command queue to reload the next context. */
++ command->currentContext = 0;
++ }
++
++ /* Get time until initialized. */
++ gcmkPROFILE_QUERY(time, initTime);
++
++ if (flag & (gcvPOWER_FLAG_POWER_OFF | gcvPOWER_FLAG_CLOCK_OFF))
++ {
++ /* Turn off the GPU power. */
++ gcmkONERROR(
++ gckOS_SetGPUPower(os,
++ gcvCORE_VG,
++ (flag & gcvPOWER_FLAG_CLOCK_OFF) ? gcvFALSE
++ : gcvTRUE,
++ (flag & gcvPOWER_FLAG_POWER_OFF) ? gcvFALSE
++ : gcvTRUE));
++
++ /* Save current hardware power and clock states. */
++ Hardware->clockState = (flag & gcvPOWER_FLAG_CLOCK_OFF) ? gcvFALSE
++ : gcvTRUE;
++ Hardware->powerState = (flag & gcvPOWER_FLAG_POWER_OFF) ? gcvFALSE
++ : gcvTRUE;
++ }
++
++ /* Get time until off. */
++ gcmkPROFILE_QUERY(time, offTime);
++
++
++ /* Get time until started. */
++ gcmkPROFILE_QUERY(time, startTime);
++
++ if (flag & gcvPOWER_FLAG_RELEASE)
++ {
++ /* Release the power management semaphore. */
++ gcmkONERROR(gckOS_ReleaseSemaphore(os, command->powerSemaphore));
++ acquired = gcvFALSE;
++ }
++
++ /* Save the new power state. */
++ Hardware->chipPowerState = State;
++
++ if (global)
++ {
++ /* Save the new power state. */
++ Hardware->chipPowerStateGlobal = State;
++ }
++
++ if (commitMutex)
++ {
++ /* Acquire the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(
++ command->os,
++ command->commitMutex
++ ));
++ }
++
++#if gcdPOWEROFF_TIMEOUT
++ /* Reset power off time */
++ gcmkONERROR(gckOS_GetTicks(&currentTime));
++
++ Hardware->powerOffTime = currentTime + Hardware->powerOffTimeout;
++
++ if (State == gcvPOWER_IDLE)
++ {
++ /* Start a timer to power off GPU when GPU enters IDLE or SUSPEND. */
++ gcmkVERIFY_OK(gckOS_StartTimer(os,
++ Hardware->powerOffTimer,
++ Hardware->powerOffTimeout));
++ }
++ else
++ {
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, "Cancel powerOfftimer");
++
++ /* Cancel running timer when GPU enters ON or OFF. */
++ gcmkVERIFY_OK(gckOS_StopTimer(os, Hardware->powerOffTimer));
++ }
++#endif
++
++ /* Release the power mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(os, Hardware->powerMutex));
++
++ /* Get total time. */
++ gcmkPROFILE_QUERY(time, totalTime);
++#if gcdENABLE_PROFILING
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "PROF(%llu): mutex:%llu on:%llu stall:%llu stop:%llu",
++ freq, mutexTime, onTime, stallTime, stopTime);
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ " delay:%llu init:%llu off:%llu start:%llu total:%llu",
++ delayTime, initTime, offTime, startTime, totalTime);
++#endif
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++
++ if (acquired)
++ {
++ /* Release semaphore. */
++ gcmkVERIFY_OK(gckOS_ReleaseSemaphore(Hardware->os,
++ command->powerSemaphore));
++ }
++
++ if (mutexAcquired)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Hardware->os, Hardware->powerMutex));
++ }
++
++ if (commitMutex)
++ {
++ /* Acquire the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(
++ command->os,
++ command->commitMutex
++ ));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_QueryPowerManagementState
++**
++** Get GPU power state.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** gceCHIPPOWERSTATE* State
++** Power State.
++**
++*/
++gceSTATUS
++gckVGHARDWARE_QueryPowerManagementState(
++ IN gckVGHARDWARE Hardware,
++ OUT gceCHIPPOWERSTATE* State
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(State != gcvNULL);
++
++ /* Return the statue. */
++ *State = Hardware->chipPowerState;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*State=%d", *State);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_SetPowerManagement
++**
++** Configure GPU power management function.
++** Only used in driver initialization stage.
++**
++** INPUT:
++**
++** gckVGHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** gctBOOL PowerManagement
++** Power Mangement State.
++**
++*/
++gceSTATUS
++gckVGHARDWARE_SetPowerManagement(
++ IN gckVGHARDWARE Hardware,
++ IN gctBOOL PowerManagement
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ Hardware->powerManagement = PowerManagement;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++#if gcdPOWEROFF_TIMEOUT
++gceSTATUS
++gckVGHARDWARE_SetPowerOffTimeout(
++ IN gckVGHARDWARE Hardware,
++ IN gctUINT32 Timeout
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x Timeout=%d", Hardware, Timeout);
++
++ Hardware->powerOffTimeout = Timeout;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++
++gceSTATUS
++gckVGHARDWARE_QueryPowerOffTimeout(
++ IN gckVGHARDWARE Hardware,
++ OUT gctUINT32* Timeout
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ *Timeout = Hardware->powerOffTimeout;
++
++ gcmkFOOTER_ARG("*Timeout=%d", *Timeout);
++ return gcvSTATUS_OK;
++}
++#endif
++
++gceSTATUS
++gckVGHARDWARE_QueryIdle(
++ IN gckVGHARDWARE Hardware,
++ OUT gctBOOL_PTR IsIdle
++ )
++{
++ gceSTATUS status;
++ gctUINT32 idle;
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(IsIdle != gcvNULL);
++
++ /* We are idle when the power is not ON. */
++ if (Hardware->chipPowerState != gcvPOWER_ON)
++ {
++ *IsIdle = gcvTRUE;
++ }
++
++ else
++ {
++ /* Read idle register. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os, gcvCORE_VG, 0x00004, &idle));
++
++ /* Pipe must be idle. */
++ if (((((((gctUINT32) (idle)) >> (0 ? 0:0)) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1)))))) ) != 1)
++ || ((((((gctUINT32) (idle)) >> (0 ? 8:8)) & ((gctUINT32) ((((1 ? 8:8) - (0 ? 8:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:8) - (0 ? 8:8) + 1)))))) ) != 1)
++ || ((((((gctUINT32) (idle)) >> (0 ? 9:9)) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1)))))) ) != 1)
++ || ((((((gctUINT32) (idle)) >> (0 ? 10:10)) & ((gctUINT32) ((((1 ? 10:10) - (0 ? 10:10) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 10:10) - (0 ? 10:10) + 1)))))) ) != 1)
++ || ((((((gctUINT32) (idle)) >> (0 ? 11:11)) & ((gctUINT32) ((((1 ? 11:11) - (0 ? 11:11) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:11) - (0 ? 11:11) + 1)))))) ) != 1)
++ )
++ {
++ /* Something is busy. */
++ *IsIdle = gcvFALSE;
++ }
++
++ else
++ {
++ *IsIdle = gcvTRUE;
++ }
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++#endif /* gcdENABLE_VG */
++
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/archvg/gc_hal_kernel_hardware_vg.h linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/archvg/gc_hal_kernel_hardware_vg.h
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/archvg/gc_hal_kernel_hardware_vg.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/archvg/gc_hal_kernel_hardware_vg.h 2015-07-27 23:13:06.190893891 +0200
+@@ -0,0 +1,74 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_kernel_hardware_vg_h_
++#define __gc_hal_kernel_hardware_vg_h_
++
++/* gckHARDWARE object. */
++struct _gckVGHARDWARE
++{
++ /* Object. */
++ gcsOBJECT object;
++
++ /* Pointer to gckKERNEL object. */
++ gckVGKERNEL kernel;
++
++ /* Pointer to gckOS object. */
++ gckOS os;
++
++ /* Chip characteristics. */
++ gceCHIPMODEL chipModel;
++ gctUINT32 chipRevision;
++ gctUINT32 chipFeatures;
++ gctUINT32 chipMinorFeatures;
++ gctUINT32 chipMinorFeatures2;
++ gctBOOL allowFastClear;
++
++ /* Features. */
++ gctBOOL fe20;
++ gctBOOL vg20;
++ gctBOOL vg21;
++
++ /* Event mask. */
++ gctUINT32 eventMask;
++
++ gctBOOL clockState;
++ gctBOOL powerState;
++ gctPOINTER powerMutex;
++ gctUINT32 powerProcess;
++ gctUINT32 powerThread;
++ gceCHIPPOWERSTATE chipPowerState;
++ gceCHIPPOWERSTATE chipPowerStateGlobal;
++ gctISRMANAGERFUNC startIsr;
++ gctISRMANAGERFUNC stopIsr;
++ gctPOINTER isrContext;
++ gctPOINTER pageTableDirty;
++#if gcdPOWEROFF_TIMEOUT
++ gctUINT32 powerOffTime;
++ gctUINT32 powerOffTimeout;
++ gctPOINTER powerOffTimer;
++#endif
++
++ gctBOOL powerManagement;
++};
++
++#endif /* __gc_hal_kernel_hardware_h_ */
++
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel.c linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel.c
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel.c 2015-07-27 23:13:06.190893891 +0200
+@@ -0,0 +1,3976 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_precomp.h"
++
++#define _GC_OBJ_ZONE gcvZONE_KERNEL
++
++/*******************************************************************************
++***** Version Signature *******************************************************/
++
++#define _gcmTXT2STR(t) #t
++#define gcmTXT2STR(t) _gcmTXT2STR(t)
++const char * _VERSION = "\n\0$VERSION$"
++ gcmTXT2STR(gcvVERSION_MAJOR) "."
++ gcmTXT2STR(gcvVERSION_MINOR) "."
++ gcmTXT2STR(gcvVERSION_PATCH) ":"
++ gcmTXT2STR(gcvVERSION_BUILD) "$\n";
++
++/******************************************************************************\
++******************************* gckKERNEL API Code ******************************
++\******************************************************************************/
++
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++#define gcmDEFINE2TEXT(d) #d
++gctCONST_STRING _DispatchText[] =
++{
++ gcmDEFINE2TEXT(gcvHAL_QUERY_VIDEO_MEMORY),
++ gcmDEFINE2TEXT(gcvHAL_QUERY_CHIP_IDENTITY),
++ gcmDEFINE2TEXT(gcvHAL_ALLOCATE_NON_PAGED_MEMORY),
++ gcmDEFINE2TEXT(gcvHAL_FREE_NON_PAGED_MEMORY),
++ gcmDEFINE2TEXT(gcvHAL_ALLOCATE_CONTIGUOUS_MEMORY),
++ gcmDEFINE2TEXT(gcvHAL_FREE_CONTIGUOUS_MEMORY),
++ gcmDEFINE2TEXT(gcvHAL_ALLOCATE_VIDEO_MEMORY),
++ gcmDEFINE2TEXT(gcvHAL_ALLOCATE_LINEAR_VIDEO_MEMORY),
++ gcmDEFINE2TEXT(gcvHAL_FREE_VIDEO_MEMORY),
++ gcmDEFINE2TEXT(gcvHAL_MAP_MEMORY),
++ gcmDEFINE2TEXT(gcvHAL_UNMAP_MEMORY),
++ gcmDEFINE2TEXT(gcvHAL_MAP_USER_MEMORY),
++ gcmDEFINE2TEXT(gcvHAL_UNMAP_USER_MEMORY),
++ gcmDEFINE2TEXT(gcvHAL_LOCK_VIDEO_MEMORY),
++ gcmDEFINE2TEXT(gcvHAL_UNLOCK_VIDEO_MEMORY),
++ gcmDEFINE2TEXT(gcvHAL_EVENT_COMMIT),
++ gcmDEFINE2TEXT(gcvHAL_USER_SIGNAL),
++ gcmDEFINE2TEXT(gcvHAL_SIGNAL),
++ gcmDEFINE2TEXT(gcvHAL_WRITE_DATA),
++ gcmDEFINE2TEXT(gcvHAL_COMMIT),
++ gcmDEFINE2TEXT(gcvHAL_STALL),
++ gcmDEFINE2TEXT(gcvHAL_READ_REGISTER),
++ gcmDEFINE2TEXT(gcvHAL_WRITE_REGISTER),
++ gcmDEFINE2TEXT(gcvHAL_GET_PROFILE_SETTING),
++ gcmDEFINE2TEXT(gcvHAL_SET_PROFILE_SETTING),
++ gcmDEFINE2TEXT(gcvHAL_READ_ALL_PROFILE_REGISTERS),
++#if VIVANTE_PROFILER_PERDRAW
++ gcmDEFINE2TEXT(gcvHAL_READ_PROFILER_REGISTER_SETTING),
++#endif
++ gcmDEFINE2TEXT(gcvHAL_PROFILE_REGISTERS_2D),
++ gcmDEFINE2TEXT(gcvHAL_SET_POWER_MANAGEMENT_STATE),
++ gcmDEFINE2TEXT(gcvHAL_QUERY_POWER_MANAGEMENT_STATE),
++ gcmDEFINE2TEXT(gcvHAL_GET_BASE_ADDRESS),
++ gcmDEFINE2TEXT(gcvHAL_SET_IDLE),
++ gcmDEFINE2TEXT(gcvHAL_QUERY_KERNEL_SETTINGS),
++ gcmDEFINE2TEXT(gcvHAL_RESET),
++ gcmDEFINE2TEXT(gcvHAL_MAP_PHYSICAL),
++ gcmDEFINE2TEXT(gcvHAL_DEBUG),
++ gcmDEFINE2TEXT(gcvHAL_CACHE),
++ gcmDEFINE2TEXT(gcvHAL_TIMESTAMP),
++ gcmDEFINE2TEXT(gcvHAL_DATABASE),
++ gcmDEFINE2TEXT(gcvHAL_VERSION),
++ gcmDEFINE2TEXT(gcvHAL_CHIP_INFO),
++ gcmDEFINE2TEXT(gcvHAL_ATTACH),
++ gcmDEFINE2TEXT(gcvHAL_DETACH)
++};
++#endif
++
++#if gcdENABLE_RECOVERY
++void
++_ResetFinishFunction(
++ gctPOINTER Data
++ )
++{
++ gckKERNEL kernel = (gckKERNEL)Data;
++
++ gckOS_AtomSet(kernel->os, kernel->resetAtom, 0);
++}
++#endif
++
++/*******************************************************************************
++**
++** gckKERNEL_Construct
++**
++** Construct a new gckKERNEL object.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gceCORE Core
++** Specified core.
++**
++** IN gctPOINTER Context
++** Pointer to a driver defined context.
++**
++** IN gckDB SharedDB,
++** Pointer to a shared DB.
++**
++** OUTPUT:
++**
++** gckKERNEL * Kernel
++** Pointer to a variable that will hold the pointer to the gckKERNEL
++** object.
++*/
++
++gceSTATUS
++gckKERNEL_Construct(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctPOINTER Context,
++ IN gckDB SharedDB,
++ OUT gckKERNEL * Kernel
++ )
++{
++ gckKERNEL kernel = gcvNULL;
++ gceSTATUS status;
++ gctSIZE_T i;
++ gctPOINTER pointer = gcvNULL;
++
++ gcmkHEADER_ARG("Os=0x%x Context=0x%x", Os, Context);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Kernel != gcvNULL);
++
++ /* Allocate the gckKERNEL object. */
++ gcmkONERROR(gckOS_Allocate(Os,
++ gcmSIZEOF(struct _gckKERNEL),
++ &pointer));
++
++ kernel = pointer;
++
++ /* Zero the object pointers. */
++ kernel->hardware = gcvNULL;
++ kernel->command = gcvNULL;
++ kernel->eventObj = gcvNULL;
++ kernel->mmu = gcvNULL;
++#if gcdDVFS
++ kernel->dvfs = gcvNULL;
++#endif
++
++ kernel->vidmemMutex = gcvNULL;
++
++ /* Initialize the gckKERNEL object. */
++ kernel->object.type = gcvOBJ_KERNEL;
++ kernel->os = Os;
++ kernel->core = Core;
++
++
++ if (SharedDB == gcvNULL)
++ {
++ gcmkONERROR(gckOS_Allocate(Os,
++ gcmSIZEOF(struct _gckDB),
++ &pointer));
++
++ kernel->db = pointer;
++ kernel->dbCreated = gcvTRUE;
++ kernel->db->freeDatabase = gcvNULL;
++ kernel->db->freeRecord = gcvNULL;
++ kernel->db->dbMutex = gcvNULL;
++ kernel->db->lastDatabase = gcvNULL;
++ kernel->db->idleTime = 0;
++ kernel->db->lastIdle = 0;
++ kernel->db->lastSlowdown = 0;
++
++ for (i = 0; i < gcmCOUNTOF(kernel->db->db); ++i)
++ {
++ kernel->db->db[i] = gcvNULL;
++ }
++
++ /* Construct a database mutex. */
++ gcmkONERROR(gckOS_CreateMutex(Os, &kernel->db->dbMutex));
++
++ /* Construct a id-pointer database. */
++ gcmkONERROR(gckKERNEL_CreateIntegerDatabase(kernel, &kernel->db->pointerDatabase));
++
++ /* Construct a id-pointer database mutex. */
++ gcmkONERROR(gckOS_CreateMutex(Os, &kernel->db->pointerDatabaseMutex));
++ }
++ else
++ {
++ kernel->db = SharedDB;
++ kernel->dbCreated = gcvFALSE;
++ }
++
++ for (i = 0; i < gcmCOUNTOF(kernel->timers); ++i)
++ {
++ kernel->timers[i].startTime = 0;
++ kernel->timers[i].stopTime = 0;
++ }
++
++ kernel->timeOut = gcdGPU_TIMEOUT;
++
++ /* Save context. */
++ kernel->context = Context;
++
++#if gcdVIRTUAL_COMMAND_BUFFER
++ kernel->virtualBufferHead =
++ kernel->virtualBufferTail = gcvNULL;
++
++ gcmkONERROR(
++ gckOS_CreateMutex(Os, (gctPOINTER)&kernel->virtualBufferLock));
++#endif
++
++ /* Construct atom holding number of clients. */
++ kernel->atomClients = gcvNULL;
++ gcmkONERROR(gckOS_AtomConstruct(Os, &kernel->atomClients));
++
++#if gcdENABLE_VG
++ kernel->vg = gcvNULL;
++
++ if (Core == gcvCORE_VG)
++ {
++ /* Construct the gckMMU object. */
++ gcmkONERROR(
++ gckVGKERNEL_Construct(Os, Context, kernel, &kernel->vg));
++ }
++ else
++#endif
++ {
++ /* Construct the gckHARDWARE object. */
++ gcmkONERROR(
++ gckHARDWARE_Construct(Os, kernel->core, &kernel->hardware));
++
++ /* Set pointer to gckKERNEL object in gckHARDWARE object. */
++ kernel->hardware->kernel = kernel;
++
++ /* Initialize the hardware. */
++ gcmkONERROR(
++ gckHARDWARE_InitializeHardware(kernel->hardware));
++
++ /* Construct the gckCOMMAND object. */
++ gcmkONERROR(
++ gckCOMMAND_Construct(kernel, &kernel->command));
++
++ /* Construct the gckEVENT object. */
++ gcmkONERROR(
++ gckEVENT_Construct(kernel, &kernel->eventObj));
++
++ /* Construct the gckMMU object. */
++ gcmkONERROR(
++ gckMMU_Construct(kernel, gcdMMU_SIZE, &kernel->mmu));
++
++#if gcdENABLE_RECOVERY
++ gcmkONERROR(
++ gckOS_AtomConstruct(Os, &kernel->resetAtom));
++
++ gcmkVERIFY_OK(
++ gckOS_CreateTimer(Os,
++ (gctTIMERFUNCTION)_ResetFinishFunction,
++ (gctPOINTER)kernel,
++ &kernel->resetFlagClearTimer));
++ kernel->resetTimeStamp = 0;
++#endif
++
++#if gcdDVFS
++ if (gckHARDWARE_IsFeatureAvailable(kernel->hardware,
++ gcvFEATURE_DYNAMIC_FREQUENCY_SCALING))
++ {
++ gcmkONERROR(gckDVFS_Construct(kernel->hardware, &kernel->dvfs));
++ gcmkONERROR(gckDVFS_Start(kernel->dvfs));
++ }
++#endif
++ }
++
++ spin_lock_init(&kernel->irq_lock);
++
++#if VIVANTE_PROFILER
++ /* Initialize profile setting */
++ kernel->profileEnable = gcvFALSE;
++ kernel->profileCleanRegister = gcvTRUE;
++#endif
++
++#if gcdANDROID_NATIVE_FENCE_SYNC
++ gcmkONERROR(gckOS_CreateSyncTimeline(Os, &kernel->timeline));
++#endif
++
++ /* Construct a video memory mutex. */
++ gcmkONERROR(gckOS_GetVideoMemoryMutex(Os, &kernel->vidmemMutex));
++
++ /* Return pointer to the gckKERNEL object. */
++ *Kernel = kernel;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Kernel=0x%x", *Kernel);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (kernel != gcvNULL)
++ {
++#if gcdENABLE_VG
++ if (Core != gcvCORE_VG)
++#endif
++ {
++ if (kernel->eventObj != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckEVENT_Destroy(kernel->eventObj));
++ }
++
++ if (kernel->command != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckCOMMAND_Destroy(kernel->command));
++ }
++
++ if (kernel->hardware != gcvNULL)
++ {
++ /* Turn off the power. */
++ gcmkVERIFY_OK(gckOS_SetGPUPower(kernel->hardware->os,
++ kernel->hardware->core,
++ gcvFALSE,
++ gcvFALSE));
++ gcmkVERIFY_OK(gckHARDWARE_Destroy(kernel->hardware));
++ }
++ }
++
++ if (kernel->atomClients != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_AtomDestroy(Os, kernel->atomClients));
++ }
++
++#if gcdENABLE_RECOVERY
++ if (kernel->resetAtom != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_AtomDestroy(Os, kernel->resetAtom));
++ }
++
++ if (kernel->resetFlagClearTimer)
++ {
++ gcmkVERIFY_OK(gckOS_StopTimer(Os, kernel->resetFlagClearTimer));
++ gcmkVERIFY_OK(gckOS_DestroyTimer(Os, kernel->resetFlagClearTimer));
++ }
++#endif
++
++ if (kernel->dbCreated && kernel->db != gcvNULL)
++ {
++ if (kernel->db->dbMutex != gcvNULL)
++ {
++ /* Destroy the database mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Os, kernel->db->dbMutex));
++ }
++
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Os, kernel->db));
++ }
++
++#if gcdVIRTUAL_COMMAND_BUFFER
++ if (kernel->virtualBufferLock != gcvNULL)
++ {
++ /* Destroy the virtual command buffer mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Os, kernel->virtualBufferLock));
++ }
++#endif
++
++#if gcdDVFS
++ if (kernel->dvfs)
++ {
++ gcmkVERIFY_OK(gckDVFS_Stop(kernel->dvfs));
++ gcmkVERIFY_OK(gckDVFS_Destroy(kernel->dvfs));
++ }
++#endif
++
++#if gcdANDROID_NATIVE_FENCE_SYNC
++ if (kernel->timeline)
++ {
++ gcmkVERIFY_OK(gckOS_DestroySyncTimeline(Os, kernel->timeline));
++ }
++#endif
++
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Os, kernel));
++ }
++
++ /* Return the error. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_Destroy
++**
++** Destroy an gckKERNEL object.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object to destroy.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckKERNEL_Destroy(
++ IN gckKERNEL Kernel
++ )
++{
++ gctSIZE_T i;
++ gcsDATABASE_PTR database, databaseNext;
++ gcsDATABASE_RECORD_PTR record, recordNext;
++
++ gcmkHEADER_ARG("Kernel=0x%x", Kernel);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++#if QNX_SINGLE_THREADED_DEBUGGING
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Kernel->os, Kernel->debugMutex));
++#endif
++
++ /* Destroy the database. */
++ if (Kernel->dbCreated)
++ {
++ for (i = 0; i < gcmCOUNTOF(Kernel->db->db); ++i)
++ {
++ if (Kernel->db->db[i] != gcvNULL)
++ {
++ gcmkVERIFY_OK(
++ gckKERNEL_DestroyProcessDB(Kernel, Kernel->db->db[i]->processID));
++ }
++ }
++
++ /* Free all databases. */
++ for (database = Kernel->db->freeDatabase;
++ database != gcvNULL;
++ database = databaseNext)
++ {
++ databaseNext = database->next;
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Kernel->os, database));
++ }
++
++ if (Kernel->db->lastDatabase != gcvNULL)
++ {
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Kernel->os, Kernel->db->lastDatabase));
++ }
++
++ /* Free all database records. */
++ for (record = Kernel->db->freeRecord; record != gcvNULL; record = recordNext)
++ {
++ recordNext = record->next;
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Kernel->os, record));
++ }
++
++ /* Destroy the database mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Kernel->os, Kernel->db->dbMutex));
++
++
++ /* Destroy id-pointer database. */
++ gcmkVERIFY_OK(gckKERNEL_DestroyIntegerDatabase(Kernel, Kernel->db->pointerDatabase));
++
++ /* Destroy id-pointer database mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Kernel->os, Kernel->db->pointerDatabaseMutex));
++ }
++
++#if gcdENABLE_VG
++ if (Kernel->vg)
++ {
++ gcmkVERIFY_OK(gckVGKERNEL_Destroy(Kernel->vg));
++ }
++ else
++#endif
++ {
++ /* Destroy the gckMMU object. */
++ gcmkVERIFY_OK(gckMMU_Destroy(Kernel->mmu));
++
++ /* Destroy the gckCOMMNAND object. */
++ gcmkVERIFY_OK(gckCOMMAND_Destroy(Kernel->command));
++
++ /* Destroy the gckEVENT object. */
++ gcmkVERIFY_OK(gckEVENT_Destroy(Kernel->eventObj));
++
++ /* Destroy the gckHARDWARE object. */
++ gcmkVERIFY_OK(gckHARDWARE_Destroy(Kernel->hardware));
++
++#if gcdENABLE_RECOVERY
++ gcmkVERIFY_OK(gckOS_AtomDestroy(Kernel->os, Kernel->resetAtom));
++
++ if (Kernel->resetFlagClearTimer)
++ {
++ gcmkVERIFY_OK(gckOS_StopTimer(Kernel->os, Kernel->resetFlagClearTimer));
++ gcmkVERIFY_OK(gckOS_DestroyTimer(Kernel->os, Kernel->resetFlagClearTimer));
++ }
++#endif
++ }
++
++ /* Detsroy the client atom. */
++ gcmkVERIFY_OK(gckOS_AtomDestroy(Kernel->os, Kernel->atomClients));
++
++#if gcdVIRTUAL_COMMAND_BUFFER
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Kernel->os, Kernel->virtualBufferLock));
++#endif
++
++#if gcdDVFS
++ if (Kernel->dvfs)
++ {
++ gcmkVERIFY_OK(gckDVFS_Stop(Kernel->dvfs));
++ gcmkVERIFY_OK(gckDVFS_Destroy(Kernel->dvfs));
++ }
++#endif
++
++#if gcdANDROID_NATIVE_FENCE_SYNC
++ gcmkVERIFY_OK(gckOS_DestroySyncTimeline(Kernel->os, Kernel->timeline));
++#endif
++
++ /* Mark the gckKERNEL object as unknown. */
++ Kernel->object.type = gcvOBJ_UNKNOWN;
++
++ /* Free the gckKERNEL object. */
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Kernel->os, Kernel));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++#ifdef CONFIG_ANDROID_RESERVED_MEMORY_ACCOUNT
++#include <linux/kernel.h>
++#include <linux/mm.h>
++#include <linux/oom.h>
++#include <linux/sched.h>
++#include <linux/notifier.h>
++
++extern struct task_struct *lowmem_deathpending;
++static unsigned long lowmem_deathpending_timeout;
++
++static int force_contiguous_lowmem_shrink(IN gckKERNEL Kernel)
++{
++ struct task_struct *p;
++ struct task_struct *selected = NULL;
++ int tasksize;
++ int ret = -1;
++ int min_adj = 0;
++ int selected_tasksize = 0;
++ int selected_oom_adj;
++ /*
++ * If we already have a death outstanding, then
++ * bail out right away; indicating to vmscan
++ * that we have nothing further to offer on
++ * this pass.
++ *
++ */
++ if (lowmem_deathpending &&
++ time_before_eq(jiffies, lowmem_deathpending_timeout))
++ return 0;
++ selected_oom_adj = min_adj;
++
++ read_lock(&tasklist_lock);
++ for_each_process(p) {
++ struct mm_struct *mm;
++ struct signal_struct *sig;
++ gcuDATABASE_INFO info;
++ int oom_adj, pid;
++
++ task_lock(p);
++ mm = p->mm;
++ sig = p->signal;
++ pid = p->pid;
++ if (!mm || !sig) {
++ task_unlock(p);
++ continue;
++ }
++ oom_adj = sig->oom_adj;
++ task_unlock(p);
++ if (oom_adj < min_adj) {
++ continue;
++ }
++
++ read_unlock(&tasklist_lock);
++
++ tasksize = 0;
++ if (gckKERNEL_QueryProcessDB(Kernel, pid, gcvFALSE, gcvDB_VIDEO_MEMORY, &info) == gcvSTATUS_OK){
++ tasksize += info.counters.bytes / PAGE_SIZE;
++ }
++ if (gckKERNEL_QueryProcessDB(Kernel, pid, gcvFALSE, gcvDB_CONTIGUOUS, &info) == gcvSTATUS_OK){
++ tasksize += info.counters.bytes / PAGE_SIZE;
++ }
++
++ read_lock(&tasklist_lock);
++
++ if (tasksize <= 0)
++ continue;
++
++ gckOS_Print("<gpu> pid %d (%s), adj %d, size %d \n", p->pid, p->comm, oom_adj, tasksize);
++
++ if (selected) {
++ if (oom_adj < selected_oom_adj)
++ continue;
++ if (oom_adj == selected_oom_adj &&
++ tasksize <= selected_tasksize)
++ continue;
++ }
++ selected = p;
++ selected_tasksize = tasksize;
++ selected_oom_adj = oom_adj;
++ }
++ if (selected) {
++ gckOS_Print("<gpu> send sigkill to %d (%s), adj %d, size %d\n",
++ selected->pid, selected->comm,
++ selected_oom_adj, selected_tasksize);
++ lowmem_deathpending = selected;
++ lowmem_deathpending_timeout = jiffies + HZ;
++ force_sig(SIGKILL, selected);
++ ret = 0;
++ }
++ read_unlock(&tasklist_lock);
++ return ret;
++}
++
++#endif
++
++/*******************************************************************************
++**
++** _AllocateMemory
++**
++** Private function to walk all required memory pools to allocate the requested
++** amount of video memory.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gcsHAL_INTERFACE * Interface
++** Pointer to a gcsHAL_INTERFACE structure that defines the command to
++** be dispatched.
++**
++** OUTPUT:
++**
++** gcsHAL_INTERFACE * Interface
++** Pointer to a gcsHAL_INTERFACE structure that receives any data to be
++** returned.
++*/
++static gceSTATUS
++_AllocateMemory(
++ IN gckKERNEL Kernel,
++ IN OUT gcePOOL * Pool,
++ IN gctSIZE_T Bytes,
++ IN gctSIZE_T Alignment,
++ IN gceSURF_TYPE Type,
++ OUT gcuVIDMEM_NODE_PTR * Node
++ )
++{
++ gcePOOL pool;
++ gceSTATUS status;
++ gckVIDMEM videoMemory;
++ gctINT loopCount;
++ gcuVIDMEM_NODE_PTR node = gcvNULL;
++ gctBOOL tileStatusInVirtual;
++ gctBOOL forceContiguous = gcvFALSE;
++
++ gcmkHEADER_ARG("Kernel=0x%x *Pool=%d Bytes=%lu Alignment=%lu Type=%d",
++ Kernel, *Pool, Bytes, Alignment, Type);
++
++ gcmkVERIFY_ARGUMENT(Pool != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Bytes != 0);
++
++#ifdef CONFIG_ANDROID_RESERVED_MEMORY_ACCOUNT
++_AllocateMemory_Retry:
++#endif
++ /* Get initial pool. */
++ switch (pool = *Pool)
++ {
++ case gcvPOOL_DEFAULT_FORCE_CONTIGUOUS:
++ forceContiguous = gcvTRUE;
++ case gcvPOOL_DEFAULT:
++ case gcvPOOL_LOCAL:
++ pool = gcvPOOL_LOCAL_INTERNAL;
++ loopCount = (gctINT) gcvPOOL_NUMBER_OF_POOLS;
++ break;
++
++ case gcvPOOL_UNIFIED:
++ pool = gcvPOOL_SYSTEM;
++ loopCount = (gctINT) gcvPOOL_NUMBER_OF_POOLS;
++ break;
++
++ case gcvPOOL_CONTIGUOUS:
++ loopCount = (gctINT) gcvPOOL_NUMBER_OF_POOLS;
++ break;
++
++ case gcvPOOL_DEFAULT_FORCE_CONTIGUOUS_CACHEABLE:
++ pool = gcvPOOL_CONTIGUOUS;
++ loopCount = 1;
++ forceContiguous = gcvTRUE;
++ break;
++
++ default:
++ loopCount = 1;
++ break;
++ }
++
++ while (loopCount-- > 0)
++ {
++ if (pool == gcvPOOL_VIRTUAL)
++ {
++ /* Create a gcuVIDMEM_NODE for virtual memory. */
++ gcmkONERROR(
++ gckVIDMEM_ConstructVirtual(Kernel, gcvFALSE, Bytes, &node));
++
++ /* Success. */
++ break;
++ }
++
++ else
++ if (pool == gcvPOOL_CONTIGUOUS)
++ {
++#if gcdCONTIGUOUS_SIZE_LIMIT
++ if (Bytes > gcdCONTIGUOUS_SIZE_LIMIT && forceContiguous == gcvFALSE)
++ {
++ status = gcvSTATUS_OUT_OF_MEMORY;
++ }
++ else
++#endif
++ {
++ /* Create a gcuVIDMEM_NODE from contiguous memory. */
++ status = gckVIDMEM_ConstructVirtual(Kernel, gcvTRUE, Bytes, &node);
++ }
++
++ if (gcmIS_SUCCESS(status) || forceContiguous == gcvTRUE)
++ {
++ /* Memory allocated. */
++ if(node && forceContiguous == gcvTRUE)
++ {
++ gctUINT32 physAddr=0;
++ gctUINT32 baseAddress = 0;
++
++ gcmkONERROR(
++ gckOS_LockPages(Kernel->os,
++ node->Virtual.physical,
++ node->Virtual.bytes,
++ gcvFALSE,
++ &node->Virtual.logical,
++ &node->Virtual.pageCount));
++
++ /* Convert logical address into a physical address. */
++ gcmkONERROR(
++ gckOS_GetPhysicalAddress(Kernel->os,
++ node->Virtual.logical,
++ &physAddr));
++
++ gcmkONERROR(
++ gckOS_UnlockPages(Kernel->os,
++ node->Virtual.physical,
++ node->Virtual.bytes,
++ node->Virtual.logical));
++
++ gcmkONERROR(gckOS_GetBaseAddress(Kernel->os, &baseAddress));
++
++ gcmkASSERT(physAddr >= baseAddress);
++
++ /* Subtract baseAddress to get a GPU address used for programming. */
++ physAddr -= baseAddress;
++
++ if((physAddr & 0x80000000) || ((physAddr + Bytes) & 0x80000000))
++ {
++ gckOS_Print("gpu virtual memory 0x%x cannot be allocated in force contiguous request!\n", physAddr);
++
++ gcmkONERROR(gckVIDMEM_Free(Kernel,node));
++
++ node = gcvNULL;
++ }
++ }
++
++ break;
++ }
++ }
++
++ else
++ {
++ /* Get pointer to gckVIDMEM object for pool. */
++#if gcdUSE_VIDMEM_PER_PID
++ gctUINT32 pid;
++ gckOS_GetProcessID(&pid);
++
++ status = gckKERNEL_GetVideoMemoryPoolPid(Kernel, pool, pid, &videoMemory);
++ if (status == gcvSTATUS_NOT_FOUND)
++ {
++ /* Create VidMem pool for this process. */
++ status = gckKERNEL_CreateVideoMemoryPoolPid(Kernel, pool, pid, &videoMemory);
++ }
++#else
++ status = gckKERNEL_GetVideoMemoryPool(Kernel, pool, &videoMemory);
++#endif
++
++ if (gcmIS_SUCCESS(status))
++ {
++ /* Allocate memory. */
++ status = gckVIDMEM_AllocateLinear(Kernel,
++ videoMemory,
++ Bytes,
++ Alignment,
++ Type,
++ &node);
++
++ if (gcmIS_SUCCESS(status))
++ {
++ /* Memory allocated. */
++ node->VidMem.pool = pool;
++ break;
++ }
++ }
++ }
++
++ if (pool == gcvPOOL_LOCAL_INTERNAL)
++ {
++ /* Advance to external memory. */
++ pool = gcvPOOL_LOCAL_EXTERNAL;
++ }
++
++ else
++ if (pool == gcvPOOL_LOCAL_EXTERNAL)
++ {
++ /* Advance to contiguous system memory. */
++ pool = gcvPOOL_SYSTEM;
++ }
++
++ else
++ if (pool == gcvPOOL_SYSTEM)
++ {
++ /* Advance to contiguous memory. */
++ pool = gcvPOOL_CONTIGUOUS;
++ }
++
++ else
++ if (pool == gcvPOOL_CONTIGUOUS)
++ {
++ tileStatusInVirtual =
++ gckHARDWARE_IsFeatureAvailable(Kernel->hardware,
++ gcvFEATURE_MC20);
++
++ if (Type == gcvSURF_TILE_STATUS && tileStatusInVirtual != gcvTRUE)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ /* Advance to virtual memory. */
++ pool = gcvPOOL_VIRTUAL;
++ }
++
++ else
++ {
++ /* Out of pools. */
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++ }
++
++ if (node == gcvNULL)
++ {
++
++#ifdef CONFIG_ANDROID_RESERVED_MEMORY_ACCOUNT
++ if(forceContiguous == gcvTRUE)
++ {
++ if(force_contiguous_lowmem_shrink(Kernel) == 0)
++ {
++ /* Sleep 1 millisecond. */
++ gckOS_Delay(gcvNULL, 1);
++ goto _AllocateMemory_Retry;
++ }
++ }
++#endif
++ /* Nothing allocated. */
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ /* Return node and pool used for allocation. */
++ *Node = node;
++ *Pool = pool;
++
++ /* Return status. */
++ gcmkFOOTER_ARG("*Pool=%d *Node=0x%x", *Pool, *Node);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_Dispatch
++**
++** Dispatch a command received from the user HAL layer.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gctBOOL FromUser
++** whether the call is from the user space.
++**
++** gcsHAL_INTERFACE * Interface
++** Pointer to a gcsHAL_INTERFACE structure that defines the command to
++** be dispatched.
++**
++** OUTPUT:
++**
++** gcsHAL_INTERFACE * Interface
++** Pointer to a gcsHAL_INTERFACE structure that receives any data to be
++** returned.
++*/
++
++gceSTATUS
++gckKERNEL_Dispatch(
++ IN gckKERNEL Kernel,
++ IN gctBOOL FromUser,
++ IN OUT gcsHAL_INTERFACE * Interface
++ )
++{
++ gceSTATUS status = gcvSTATUS_OK;
++ gctSIZE_T bytes;
++ gcuVIDMEM_NODE_PTR node;
++ gctBOOL locked = gcvFALSE;
++ gctPHYS_ADDR physical = gcvNULL;
++ gctPOINTER logical = gcvNULL;
++ gctPOINTER info = gcvNULL;
++ gckCONTEXT context = gcvNULL;
++ gctUINT32 address;
++ gctUINT32 processID;
++ gckKERNEL kernel = Kernel;
++#if gcdSECURE_USER
++ gcskSECURE_CACHE_PTR cache;
++#endif
++ gctBOOL asynchronous;
++ gctPOINTER paddr = gcvNULL;
++#if !USE_NEW_LINUX_SIGNAL
++ gctSIGNAL signal;
++#endif
++ gceSURF_TYPE type;
++
++ gcmkHEADER_ARG("Kernel=0x%x FromUser=%d Interface=0x%x",
++ Kernel, FromUser, Interface);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(Interface != gcvNULL);
++
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_KERNEL,
++ "Dispatching command %d (%s)",
++ Interface->command, _DispatchText[Interface->command]);
++#endif
++#if QNX_SINGLE_THREADED_DEBUGGING
++ gckOS_AcquireMutex(Kernel->os, Kernel->debugMutex, gcvINFINITE);
++#endif
++
++ /* Get the current process ID. */
++ gcmkONERROR(gckOS_GetProcessID(&processID));
++
++#if gcdSECURE_USER
++ gcmkONERROR(gckKERNEL_GetProcessDBCache(Kernel, processID, &cache));
++#endif
++
++ /* Dispatch on command. */
++ switch (Interface->command)
++ {
++ case gcvHAL_GET_BASE_ADDRESS:
++ /* Get base address. */
++ gcmkONERROR(
++ gckOS_GetBaseAddress(Kernel->os,
++ &Interface->u.GetBaseAddress.baseAddress));
++ break;
++
++ case gcvHAL_QUERY_VIDEO_MEMORY:
++ /* Query video memory size. */
++ gcmkONERROR(gckKERNEL_QueryVideoMemory(Kernel, Interface));
++ break;
++
++ case gcvHAL_QUERY_CHIP_IDENTITY:
++ /* Query chip identity. */
++ gcmkONERROR(
++ gckHARDWARE_QueryChipIdentity(
++ Kernel->hardware,
++ &Interface->u.QueryChipIdentity));
++ break;
++
++ case gcvHAL_MAP_MEMORY:
++ physical = gcmINT2PTR(Interface->u.MapMemory.physical);
++
++ /* Map memory. */
++ gcmkONERROR(
++ gckKERNEL_MapMemory(Kernel,
++ physical,
++ (gctSIZE_T) Interface->u.MapMemory.bytes,
++ &logical));
++
++ Interface->u.MapMemory.logical = gcmPTR_TO_UINT64(logical);
++
++ gcmkVERIFY_OK(
++ gckKERNEL_AddProcessDB(Kernel,
++ processID, gcvDB_MAP_MEMORY,
++ logical,
++ physical,
++ (gctSIZE_T) Interface->u.MapMemory.bytes));
++ break;
++
++ case gcvHAL_UNMAP_MEMORY:
++ physical = gcmINT2PTR(Interface->u.UnmapMemory.physical);
++
++ /* Unmap memory. */
++ gcmkONERROR(
++ gckKERNEL_UnmapMemory(Kernel,
++ physical,
++ (gctSIZE_T) Interface->u.UnmapMemory.bytes,
++ gcmUINT64_TO_PTR(Interface->u.UnmapMemory.logical)));
++ gcmkVERIFY_OK(
++ gckKERNEL_RemoveProcessDB(Kernel,
++ processID, gcvDB_MAP_MEMORY,
++ gcmUINT64_TO_PTR(Interface->u.UnmapMemory.logical)));
++ break;
++
++ case gcvHAL_ALLOCATE_NON_PAGED_MEMORY:
++ bytes = (gctSIZE_T) Interface->u.AllocateNonPagedMemory.bytes;
++
++ /* Allocate non-paged memory. */
++ gcmkONERROR(
++ gckOS_AllocateNonPagedMemory(
++ Kernel->os,
++ FromUser,
++ &bytes,
++ &physical,
++ &logical));
++
++ Interface->u.AllocateNonPagedMemory.bytes = bytes;
++ Interface->u.AllocateNonPagedMemory.logical = gcmPTR_TO_UINT64(logical);
++ Interface->u.AllocateNonPagedMemory.physical = gcmPTR_TO_NAME(physical);
++
++ gcmkVERIFY_OK(
++ gckKERNEL_AddProcessDB(Kernel,
++ processID, gcvDB_NON_PAGED,
++ logical,
++ gcmINT2PTR(Interface->u.AllocateNonPagedMemory.physical),
++ bytes));
++
++ break;
++
++ case gcvHAL_ALLOCATE_VIRTUAL_COMMAND_BUFFER:
++#if gcdVIRTUAL_COMMAND_BUFFER
++ bytes = (gctSIZE_T) Interface->u.AllocateVirtualCommandBuffer.bytes;
++
++ gcmkONERROR(
++ gckKERNEL_AllocateVirtualCommandBuffer(
++ Kernel,
++ FromUser,
++ &bytes,
++ &physical,
++ &logical));
++
++ Interface->u.AllocateVirtualCommandBuffer.bytes = bytes;
++ Interface->u.AllocateVirtualCommandBuffer.logical = gcmPTR_TO_UINT64(logical);
++ Interface->u.AllocateVirtualCommandBuffer.physical = gcmPTR_TO_NAME(physical);
++
++ gcmkVERIFY_OK(
++ gckKERNEL_AddProcessDB(Kernel,
++ processID, gcvDB_COMMAND_BUFFER,
++ logical,
++ gcmINT2PTR(Interface->u.AllocateVirtualCommandBuffer.physical),
++ bytes));
++#else
++ status = gcvSTATUS_NOT_SUPPORTED;
++#endif
++ break;
++
++ case gcvHAL_FREE_NON_PAGED_MEMORY:
++ physical = gcmNAME_TO_PTR(Interface->u.FreeNonPagedMemory.physical);
++
++ /* Unmap user logical out of physical memory first. */
++ gcmkONERROR(gckOS_UnmapUserLogical(Kernel->os,
++ physical,
++ (gctSIZE_T) Interface->u.FreeNonPagedMemory.bytes,
++ gcmUINT64_TO_PTR(Interface->u.FreeNonPagedMemory.logical)));
++
++ /* Free non-paged memory. */
++ gcmkONERROR(
++ gckOS_FreeNonPagedMemory(Kernel->os,
++ (gctSIZE_T) Interface->u.FreeNonPagedMemory.bytes,
++ physical,
++ gcmUINT64_TO_PTR(Interface->u.FreeNonPagedMemory.logical)));
++
++ gcmkVERIFY_OK(
++ gckKERNEL_RemoveProcessDB(Kernel,
++ processID, gcvDB_NON_PAGED,
++ gcmUINT64_TO_PTR(Interface->u.FreeNonPagedMemory.logical)));
++
++#if gcdSECURE_USER
++ gcmkVERIFY_OK(gckKERNEL_FlushTranslationCache(
++ Kernel,
++ cache,
++ gcmUINT64_TO_PTR(Interface->u.FreeNonPagedMemory.logical),
++ Interface->u.FreeNonPagedMemory.bytes));
++#endif
++
++ gcmRELEASE_NAME(Interface->u.FreeNonPagedMemory.physical);
++
++ break;
++
++ case gcvHAL_ALLOCATE_CONTIGUOUS_MEMORY:
++ bytes = (gctSIZE_T) Interface->u.AllocateContiguousMemory.bytes;
++
++ /* Allocate contiguous memory. */
++ gcmkONERROR(gckOS_AllocateContiguous(
++ Kernel->os,
++ FromUser,
++ &bytes,
++ &physical,
++ &logical));
++
++ Interface->u.AllocateContiguousMemory.bytes = bytes;
++ Interface->u.AllocateContiguousMemory.logical = gcmPTR_TO_UINT64(logical);
++ Interface->u.AllocateContiguousMemory.physical = gcmPTR_TO_NAME(physical);
++
++ gcmkONERROR(gckHARDWARE_ConvertLogical(
++ Kernel->hardware,
++ gcmUINT64_TO_PTR(Interface->u.AllocateContiguousMemory.logical),
++ &Interface->u.AllocateContiguousMemory.address));
++
++ gcmkVERIFY_OK(gckKERNEL_AddProcessDB(
++ Kernel,
++ processID, gcvDB_CONTIGUOUS,
++ logical,
++ gcmINT2PTR(Interface->u.AllocateContiguousMemory.physical),
++ bytes));
++
++ break;
++
++ case gcvHAL_FREE_CONTIGUOUS_MEMORY:
++ physical = gcmNAME_TO_PTR(Interface->u.FreeContiguousMemory.physical);
++
++ /* Unmap user logical out of physical memory first. */
++ gcmkONERROR(gckOS_UnmapUserLogical(Kernel->os,
++ physical,
++ (gctSIZE_T) Interface->u.FreeContiguousMemory.bytes,
++ gcmUINT64_TO_PTR(Interface->u.FreeContiguousMemory.logical)));
++
++ /* Free contiguous memory. */
++ gcmkONERROR(
++ gckOS_FreeContiguous(Kernel->os,
++ physical,
++ gcmUINT64_TO_PTR(Interface->u.FreeContiguousMemory.logical),
++ (gctSIZE_T) Interface->u.FreeContiguousMemory.bytes));
++
++ gcmkVERIFY_OK(
++ gckKERNEL_RemoveProcessDB(Kernel,
++ processID, gcvDB_CONTIGUOUS,
++ gcmUINT64_TO_PTR(Interface->u.FreeNonPagedMemory.logical)));
++
++#if gcdSECURE_USER
++ gcmkVERIFY_OK(gckKERNEL_FlushTranslationCache(
++ Kernel,
++ cache,
++ gcmUINT64_TO_PTR(Interface->u.FreeContiguousMemory.logical),
++ Interface->u.FreeContiguousMemory.bytes));
++#endif
++
++ gcmRELEASE_NAME(Interface->u.FreeContiguousMemory.physical);
++
++ break;
++
++ case gcvHAL_ALLOCATE_VIDEO_MEMORY:
++
++ gcmkONERROR(gcvSTATUS_NOT_SUPPORTED);
++
++ break;
++
++ case gcvHAL_ALLOCATE_LINEAR_VIDEO_MEMORY:
++ type = Interface->u.AllocateLinearVideoMemory.type;
++
++ /* Allocate memory. */
++ gcmkONERROR(
++ _AllocateMemory(Kernel,
++ &Interface->u.AllocateLinearVideoMemory.pool,
++ Interface->u.AllocateLinearVideoMemory.bytes,
++ Interface->u.AllocateLinearVideoMemory.alignment,
++ Interface->u.AllocateLinearVideoMemory.type,
++ &node));
++
++ if (node->VidMem.memory->object.type == gcvOBJ_VIDMEM)
++ {
++ bytes = node->VidMem.bytes;
++ node->VidMem.type = type;
++
++ gcmkONERROR(
++ gckKERNEL_AddProcessDB(Kernel,
++ processID, gcvDB_VIDEO_MEMORY_RESERVED,
++ node,
++ gcvNULL,
++ bytes));
++ }
++ else
++ {
++ bytes = node->Virtual.bytes;
++ node->Virtual.type = type;
++
++ if(node->Virtual.contiguous)
++ {
++ gcmkONERROR(
++ gckKERNEL_AddProcessDB(Kernel,
++ processID, gcvDB_VIDEO_MEMORY_CONTIGUOUS,
++ node,
++ gcvNULL,
++ bytes));
++ }
++ else
++ {
++ gcmkONERROR(
++ gckKERNEL_AddProcessDB(Kernel,
++ processID, gcvDB_VIDEO_MEMORY_VIRTUAL,
++ node,
++ gcvNULL,
++ bytes));
++ }
++
++ }
++
++ gcmkONERROR(
++ gckKERNEL_AddProcessDB(Kernel,
++ processID, gcvDB_VIDEO_MEMORY,
++ node,
++ gcvNULL,
++ bytes));
++
++ /* Get the node. */
++ Interface->u.AllocateLinearVideoMemory.node = gcmPTR_TO_UINT64(node);
++ break;
++
++ case gcvHAL_FREE_VIDEO_MEMORY:
++ node = gcmUINT64_TO_PTR(Interface->u.FreeVideoMemory.node);
++#ifdef __QNXNTO__
++ if (node->VidMem.memory->object.type == gcvOBJ_VIDMEM
++ && node->VidMem.logical != gcvNULL)
++ {
++ gcmkONERROR(
++ gckKERNEL_UnmapVideoMemory(Kernel,
++ node->VidMem.logical,
++ processID,
++ node->VidMem.bytes));
++ node->VidMem.logical = gcvNULL;
++ }
++#endif
++ /* Free video memory. */
++ gcmkONERROR(
++ gckVIDMEM_Free(Kernel, node));
++
++ gcmkONERROR(
++ gckKERNEL_RemoveProcessDB(Kernel,
++ processID, gcvDB_VIDEO_MEMORY,
++ node));
++
++ if (node->VidMem.memory->object.type == gcvOBJ_VIDMEM)
++ {
++ gcmkONERROR(
++ gckKERNEL_RemoveProcessDB(Kernel,
++ processID, gcvDB_VIDEO_MEMORY_RESERVED,
++ node));
++ }
++ else if(node->Virtual.contiguous)
++ {
++ gcmkONERROR(
++ gckKERNEL_RemoveProcessDB(Kernel,
++ processID, gcvDB_VIDEO_MEMORY_CONTIGUOUS,
++ node));
++ }
++ else
++ {
++ gcmkONERROR(
++ gckKERNEL_RemoveProcessDB(Kernel,
++ processID, gcvDB_VIDEO_MEMORY_VIRTUAL,
++ node));
++ }
++
++ break;
++
++ case gcvHAL_LOCK_VIDEO_MEMORY:
++ node = gcmUINT64_TO_PTR(Interface->u.LockVideoMemory.node);
++
++ /* Lock video memory. */
++ gcmkONERROR(
++ gckVIDMEM_Lock(Kernel,
++ node,
++ Interface->u.LockVideoMemory.cacheable,
++ &Interface->u.LockVideoMemory.address));
++
++ locked = gcvTRUE;
++
++ if (node->VidMem.memory->object.type == gcvOBJ_VIDMEM)
++ {
++ /* Map video memory address into user space. */
++#ifdef __QNXNTO__
++ if (node->VidMem.logical == gcvNULL)
++ {
++ gcmkONERROR(
++ gckKERNEL_MapVideoMemory(Kernel,
++ FromUser,
++ Interface->u.LockVideoMemory.address,
++ processID,
++ node->VidMem.bytes,
++ &node->VidMem.logical));
++ }
++ gcmkASSERT(node->VidMem.logical != gcvNULL);
++
++ Interface->u.LockVideoMemory.memory = gcmPTR_TO_UINT64(node->VidMem.logical);
++#else
++ gcmkONERROR(
++ gckKERNEL_MapVideoMemory(Kernel,
++ FromUser,
++ Interface->u.LockVideoMemory.address,
++ &logical));
++
++ Interface->u.LockVideoMemory.memory = gcmPTR_TO_UINT64(logical);
++#endif
++ }
++ else
++ {
++ Interface->u.LockVideoMemory.memory = gcmPTR_TO_UINT64(node->Virtual.logical);
++
++ /* Success. */
++ status = gcvSTATUS_OK;
++ }
++
++#if gcdSECURE_USER
++ /* Return logical address as physical address. */
++ Interface->u.LockVideoMemory.address =
++ Interface->u.LockVideoMemory.memory;
++#endif
++ gcmkONERROR(
++ gckKERNEL_AddProcessDB(Kernel,
++ processID, gcvDB_VIDEO_MEMORY_LOCKED,
++ node,
++ gcvNULL,
++ 0));
++
++ break;
++
++ case gcvHAL_UNLOCK_VIDEO_MEMORY:
++ /* Unlock video memory. */
++ node = gcmUINT64_TO_PTR(Interface->u.UnlockVideoMemory.node);
++
++#if gcdSECURE_USER
++ /* Save node information before it disappears. */
++ if (node->VidMem.memory->object.type == gcvOBJ_VIDMEM)
++ {
++ logical = gcvNULL;
++ bytes = 0;
++ }
++ else
++ {
++ logical = node->Virtual.logical;
++ bytes = node->Virtual.bytes;
++ }
++#endif
++
++ /* Unlock video memory. */
++ gcmkONERROR(
++ gckVIDMEM_Unlock(Kernel,
++ node,
++ Interface->u.UnlockVideoMemory.type,
++ &Interface->u.UnlockVideoMemory.asynchroneous));
++
++#if gcdSECURE_USER
++ /* Flush the translation cache for virtual surfaces. */
++ if (logical != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckKERNEL_FlushTranslationCache(Kernel,
++ cache,
++ logical,
++ bytes));
++ }
++#endif
++ if (Interface->u.UnlockVideoMemory.asynchroneous == gcvFALSE)
++ {
++ /* There isn't a event to unlock this node, remove record now */
++ gcmkONERROR(
++ gckKERNEL_RemoveProcessDB(Kernel,
++ processID, gcvDB_VIDEO_MEMORY_LOCKED,
++ node));
++ }
++ break;
++
++ case gcvHAL_EVENT_COMMIT:
++ /* Commit an event queue. */
++ gcmkONERROR(
++ gckEVENT_Commit(Kernel->eventObj,
++ gcmUINT64_TO_PTR(Interface->u.Event.queue)));
++ break;
++
++ case gcvHAL_COMMIT:
++ /* Commit a command and context buffer. */
++ gcmkONERROR(
++ gckCOMMAND_Commit(Kernel->command,
++ Interface->u.Commit.context ?
++ gcmNAME_TO_PTR(Interface->u.Commit.context) : gcvNULL,
++ gcmUINT64_TO_PTR(Interface->u.Commit.commandBuffer),
++ gcmUINT64_TO_PTR(Interface->u.Commit.delta),
++ gcmUINT64_TO_PTR(Interface->u.Commit.queue),
++ processID));
++ break;
++
++ case gcvHAL_STALL:
++ /* Stall the command queue. */
++ gcmkONERROR(gckCOMMAND_Stall(Kernel->command, gcvFALSE));
++ break;
++
++ case gcvHAL_MAP_USER_MEMORY:
++ /* Map user memory to DMA. */
++ gcmkONERROR(
++ gckOS_MapUserMemory(Kernel->os,
++ Kernel->core,
++ gcmUINT64_TO_PTR(Interface->u.MapUserMemory.memory),
++ Interface->u.MapUserMemory.physical,
++ (gctSIZE_T) Interface->u.MapUserMemory.size,
++ &info,
++ &Interface->u.MapUserMemory.address));
++
++ Interface->u.MapUserMemory.info = gcmPTR_TO_NAME(info);
++
++ gcmkVERIFY_OK(
++ gckKERNEL_AddProcessDB(Kernel,
++ processID, gcvDB_MAP_USER_MEMORY,
++ gcmINT2PTR(Interface->u.MapUserMemory.info),
++ gcmUINT64_TO_PTR(Interface->u.MapUserMemory.memory),
++ (gctSIZE_T) Interface->u.MapUserMemory.size));
++ break;
++
++ case gcvHAL_UNMAP_USER_MEMORY:
++ address = Interface->u.UnmapUserMemory.address;
++ info = gcmNAME_TO_PTR(Interface->u.UnmapUserMemory.info);
++
++ /* Unmap user memory. */
++ gcmkONERROR(
++ gckOS_UnmapUserMemory(Kernel->os,
++ Kernel->core,
++ gcmUINT64_TO_PTR(Interface->u.UnmapUserMemory.memory),
++ (gctSIZE_T) Interface->u.UnmapUserMemory.size,
++ info,
++ address));
++
++#if gcdSECURE_USER
++ gcmkVERIFY_OK(gckKERNEL_FlushTranslationCache(
++ Kernel,
++ cache,
++ gcmUINT64_TO_PTR(Interface->u.UnmapUserMemory.memory),
++ Interface->u.UnmapUserMemory.size));
++#endif
++ gcmkVERIFY_OK(
++ gckKERNEL_RemoveProcessDB(Kernel,
++ processID, gcvDB_MAP_USER_MEMORY,
++ gcmINT2PTR(Interface->u.UnmapUserMemory.info)));
++
++ gcmRELEASE_NAME(Interface->u.UnmapUserMemory.info);
++
++ break;
++
++#if !USE_NEW_LINUX_SIGNAL
++ case gcvHAL_USER_SIGNAL:
++ /* Dispatch depends on the user signal subcommands. */
++ switch(Interface->u.UserSignal.command)
++ {
++ case gcvUSER_SIGNAL_CREATE:
++ /* Create a signal used in the user space. */
++ gcmkONERROR(
++ gckOS_CreateUserSignal(Kernel->os,
++ Interface->u.UserSignal.manualReset,
++ &Interface->u.UserSignal.id));
++
++ gcmkVERIFY_OK(
++ gckKERNEL_AddProcessDB(Kernel,
++ processID, gcvDB_SIGNAL,
++ gcmINT2PTR(Interface->u.UserSignal.id),
++ gcvNULL,
++ 0));
++ break;
++
++ case gcvUSER_SIGNAL_DESTROY:
++ /* Destroy the signal. */
++ gcmkONERROR(
++ gckOS_DestroyUserSignal(Kernel->os,
++ Interface->u.UserSignal.id));
++
++ gcmkVERIFY_OK(gckKERNEL_RemoveProcessDB(
++ Kernel,
++ processID, gcvDB_SIGNAL,
++ gcmINT2PTR(Interface->u.UserSignal.id)));
++ break;
++
++ case gcvUSER_SIGNAL_SIGNAL:
++ /* Signal the signal. */
++ gcmkONERROR(
++ gckOS_SignalUserSignal(Kernel->os,
++ Interface->u.UserSignal.id,
++ Interface->u.UserSignal.state));
++ break;
++
++ case gcvUSER_SIGNAL_WAIT:
++#if gcdGPU_TIMEOUT
++ if (Interface->u.UserSignal.wait == gcvINFINITE)
++ {
++ gckHARDWARE hardware;
++ gctUINT32 timer = 0;
++
++ for(;;)
++ {
++ /* Wait on the signal. */
++ status = gckOS_WaitUserSignal(Kernel->os,
++ Interface->u.UserSignal.id,
++ gcdGPU_ADVANCETIMER);
++
++ if (status == gcvSTATUS_TIMEOUT)
++ {
++ gcmkONERROR(
++ gckOS_SignalQueryHardware(Kernel->os,
++ (gctSIGNAL)(gctUINTPTR_T)Interface->u.UserSignal.id,
++ &hardware));
++
++ if (hardware)
++ {
++ /* This signal is bound to a hardware,
++ ** so the timeout is limited by Kernel->timeOut.
++ */
++ timer += gcdGPU_ADVANCETIMER;
++ }
++
++ if (timer >= Kernel->timeOut)
++ {
++ gcmkONERROR(
++ gckOS_Broadcast(Kernel->os,
++ hardware,
++ gcvBROADCAST_GPU_STUCK));
++
++ timer = 0;
++
++ /* If a few process try to reset GPU, only one
++ ** of them can do the real reset, other processes
++ ** still need to wait for this signal is triggered,
++ ** which menas reset is finished.
++ */
++ continue;
++ }
++ }
++ else
++ {
++ /* Bail out on other error. */
++ gcmkONERROR(status);
++
++ /* Wait for signal successfully. */
++ break;
++ }
++ }
++ }
++ else
++#endif
++ {
++ /* Wait on the signal. */
++ status = gckOS_WaitUserSignal(Kernel->os,
++ Interface->u.UserSignal.id,
++ Interface->u.UserSignal.wait);
++ }
++
++ break;
++
++ case gcvUSER_SIGNAL_MAP:
++ gcmkONERROR(
++ gckOS_MapSignal(Kernel->os,
++ (gctSIGNAL)(gctUINTPTR_T)Interface->u.UserSignal.id,
++ (gctHANDLE)(gctUINTPTR_T)processID,
++ &signal));
++
++ gcmkVERIFY_OK(
++ gckKERNEL_AddProcessDB(Kernel,
++ processID, gcvDB_SIGNAL,
++ gcmINT2PTR(Interface->u.UserSignal.id),
++ gcvNULL,
++ 0));
++ break;
++
++ case gcvUSER_SIGNAL_UNMAP:
++ /* Destroy the signal. */
++ gcmkONERROR(
++ gckOS_DestroyUserSignal(Kernel->os,
++ Interface->u.UserSignal.id));
++
++ gcmkVERIFY_OK(gckKERNEL_RemoveProcessDB(
++ Kernel,
++ processID, gcvDB_SIGNAL,
++ gcmINT2PTR(Interface->u.UserSignal.id)));
++ break;
++
++ default:
++ /* Invalid user signal command. */
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++ break;
++#endif
++
++ case gcvHAL_SET_POWER_MANAGEMENT_STATE:
++ /* Set the power management state. */
++ gcmkONERROR(
++ gckHARDWARE_SetPowerManagementState(
++ Kernel->hardware,
++ Interface->u.SetPowerManagement.state));
++ break;
++
++ case gcvHAL_QUERY_POWER_MANAGEMENT_STATE:
++ /* Chip is not idle. */
++ Interface->u.QueryPowerManagement.isIdle = gcvFALSE;
++
++ /* Query the power management state. */
++ gcmkONERROR(gckHARDWARE_QueryPowerManagementState(
++ Kernel->hardware,
++ &Interface->u.QueryPowerManagement.state));
++
++ /* Query the idle state. */
++ gcmkONERROR(
++ gckHARDWARE_QueryIdle(Kernel->hardware,
++ &Interface->u.QueryPowerManagement.isIdle));
++ break;
++
++ case gcvHAL_READ_REGISTER:
++#if gcdREGISTER_ACCESS_FROM_USER
++ {
++ gceCHIPPOWERSTATE power;
++
++ gckOS_AcquireMutex(Kernel->os, Kernel->hardware->powerMutex, gcvINFINITE);
++ gcmkONERROR(gckHARDWARE_QueryPowerManagementState(Kernel->hardware,
++ &power));
++ if (power == gcvPOWER_ON)
++ {
++ /* Read a register. */
++ gcmkONERROR(gckOS_ReadRegisterEx(
++ Kernel->os,
++ Kernel->core,
++ Interface->u.ReadRegisterData.address,
++ &Interface->u.ReadRegisterData.data));
++ }
++ else
++ {
++ /* Chip is in power-state. */
++ Interface->u.ReadRegisterData.data = 0;
++ status = gcvSTATUS_CHIP_NOT_READY;
++ }
++ gcmkONERROR(gckOS_ReleaseMutex(Kernel->os, Kernel->hardware->powerMutex));
++ }
++#else
++ /* No access from user land to read registers. */
++ Interface->u.ReadRegisterData.data = 0;
++ status = gcvSTATUS_NOT_SUPPORTED;
++#endif
++ break;
++
++ case gcvHAL_WRITE_REGISTER:
++#if gcdREGISTER_ACCESS_FROM_USER
++ {
++ gceCHIPPOWERSTATE power;
++
++ gckOS_AcquireMutex(Kernel->os, Kernel->hardware->powerMutex, gcvINFINITE);
++ gcmkONERROR(gckHARDWARE_QueryPowerManagementState(Kernel->hardware,
++ &power));
++ if (power == gcvPOWER_ON)
++ {
++ /* Write a register. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Kernel->os,
++ Kernel->core,
++ Interface->u.WriteRegisterData.address,
++ Interface->u.WriteRegisterData.data));
++ }
++ else
++ {
++ /* Chip is in power-state. */
++ Interface->u.WriteRegisterData.data = 0;
++ status = gcvSTATUS_CHIP_NOT_READY;
++ }
++ gcmkONERROR(gckOS_ReleaseMutex(Kernel->os, Kernel->hardware->powerMutex));
++ }
++#else
++ /* No access from user land to write registers. */
++ status = gcvSTATUS_NOT_SUPPORTED;
++#endif
++ break;
++
++ case gcvHAL_READ_ALL_PROFILE_REGISTERS:
++#if VIVANTE_PROFILER && VIVANTE_PROFILER_CONTEXT
++ /* Read profile data according to the context. */
++ gcmkONERROR(
++ gckHARDWARE_QueryContextProfile(
++ Kernel->hardware,
++ Kernel->profileCleanRegister,
++ gcmNAME_TO_PTR(Interface->u.RegisterProfileData.context),
++ &Interface->u.RegisterProfileData.counters));
++#elif VIVANTE_PROFILER
++ /* Read all 3D profile registers. */
++ gcmkONERROR(
++ gckHARDWARE_QueryProfileRegisters(
++ Kernel->hardware,
++ Kernel->profileCleanRegister,
++ &Interface->u.RegisterProfileData.counters));
++#else
++ status = gcvSTATUS_OK;
++#endif
++ break;
++
++ case gcvHAL_PROFILE_REGISTERS_2D:
++#if VIVANTE_PROFILER
++ /* Read all 2D profile registers. */
++ gcmkONERROR(
++ gckHARDWARE_ProfileEngine2D(
++ Kernel->hardware,
++ gcmUINT64_TO_PTR(Interface->u.RegisterProfileData2D.hwProfile2D)));
++#else
++ status = gcvSTATUS_OK;
++#endif
++ break;
++
++ case gcvHAL_GET_PROFILE_SETTING:
++#if VIVANTE_PROFILER
++ /* Get profile setting */
++ Interface->u.GetProfileSetting.enable = Kernel->profileEnable;
++#endif
++
++ status = gcvSTATUS_OK;
++ break;
++ case gcvHAL_SET_PROFILE_SETTING:
++#if VIVANTE_PROFILER
++ /* Set profile setting */
++ if(Kernel->hardware->gpuProfiler)
++ Kernel->profileEnable = Interface->u.SetProfileSetting.enable;
++ else
++ {
++ status = gcvSTATUS_NOT_SUPPORTED;
++ break;
++ }
++#endif
++
++ status = gcvSTATUS_OK;
++ break;
++
++#if VIVANTE_PROFILER_PERDRAW
++ case gcvHAL_READ_PROFILER_REGISTER_SETTING:
++ #if VIVANTE_PROFILER
++ Kernel->profileCleanRegister = Interface->u.SetProfilerRegisterClear.bclear;
++ #endif
++ status = gcvSTATUS_OK;
++ break;
++#endif
++
++ case gcvHAL_QUERY_KERNEL_SETTINGS:
++ /* Get kernel settings. */
++ gcmkONERROR(
++ gckKERNEL_QuerySettings(Kernel,
++ &Interface->u.QueryKernelSettings.settings));
++ break;
++
++ case gcvHAL_RESET:
++ /* Reset the hardware. */
++ gckKERNEL_Recovery(Kernel);
++ break;
++
++ case gcvHAL_DEBUG:
++ /* Set debug level and zones. */
++ if (Interface->u.Debug.set)
++ {
++ gckOS_SetDebugLevel(Interface->u.Debug.level);
++ gckOS_SetDebugZones(Interface->u.Debug.zones,
++ Interface->u.Debug.enable);
++ }
++
++ if (Interface->u.Debug.message[0] != '\0')
++ {
++ /* Print a message to the debugger. */
++ if (Interface->u.Debug.type == gcvMESSAGE_TEXT)
++ {
++ gckOS_CopyPrint(Interface->u.Debug.message);
++ }
++ else
++ {
++ gckOS_DumpBuffer(Kernel->os,
++ Interface->u.Debug.message,
++ Interface->u.Debug.messageSize,
++ gceDUMP_BUFFER_FROM_USER,
++ gcvTRUE);
++ }
++ }
++ status = gcvSTATUS_OK;
++ break;
++
++ case gcvHAL_DUMP_GPU_STATE:
++ /* Dump GPU state */
++ {
++ gceCHIPPOWERSTATE power;
++ gcmkONERROR(gckHARDWARE_QueryPowerManagementState(Kernel->hardware,
++ &power));
++ if (power == gcvPOWER_ON)
++ {
++ Interface->u.ReadRegisterData.data = 1;
++ gcmkVERIFY_OK(
++ gckHARDWARE_DumpGPUState(Kernel->hardware));
++#if gcdVIRTUAL_COMMAND_BUFFER
++ gcmkVERIFY_OK(
++ gckCOMMAND_DumpExecutingBuffer(Kernel->command));
++#endif
++ }
++ else
++ {
++ Interface->u.ReadRegisterData.data = 0;
++ status = gcvSTATUS_CHIP_NOT_READY;
++ }
++ }
++ break;
++
++ case gcvHAL_DUMP_EVENT:
++ /* Dump GPU event */
++ gcmkVERIFY_OK(gckEVENT_Dump(Kernel->eventObj));
++
++ /* Dump Process DB. */
++ gcmkVERIFY_OK(gckKERNEL_DumpProcessDB(Kernel));
++ break;
++
++ case gcvHAL_CACHE:
++ node = gcmUINT64_TO_PTR(Interface->u.Cache.node);
++ if (node == gcvNULL)
++ {
++ /* FIXME Surface wrap some memory which is not allocated by us,
++ ** So we don't have physical address to handle outer cache, ignore it*/
++ status = gcvSTATUS_OK;
++ break;
++ }
++ else if (node->VidMem.memory->object.type == gcvOBJ_VIDMEM)
++ {
++ /* Video memory has no physical handles. */
++ physical = gcvNULL;
++ }
++ else
++ {
++ /* Grab physical handle. */
++ physical = node->Virtual.physical;
++ }
++
++ logical = gcmUINT64_TO_PTR(Interface->u.Cache.logical);
++ bytes = (gctSIZE_T) Interface->u.Cache.bytes;
++ switch(Interface->u.Cache.operation)
++ {
++ case gcvCACHE_FLUSH:
++ /* Clean and invalidate the cache. */
++ status = gckOS_CacheFlush(Kernel->os,
++ processID,
++ physical,
++ paddr,
++ logical,
++ bytes);
++ break;
++ case gcvCACHE_CLEAN:
++ /* Clean the cache. */
++ status = gckOS_CacheClean(Kernel->os,
++ processID,
++ physical,
++ paddr,
++ logical,
++ bytes);
++ break;
++ case gcvCACHE_INVALIDATE:
++ /* Invalidate the cache. */
++ status = gckOS_CacheInvalidate(Kernel->os,
++ processID,
++ physical,
++ paddr,
++ logical,
++ bytes);
++ break;
++
++ case gcvCACHE_MEMORY_BARRIER:
++ status = gckOS_MemoryBarrier(Kernel->os,
++ logical);
++ break;
++ default:
++ status = gcvSTATUS_INVALID_ARGUMENT;
++ break;
++ }
++ break;
++
++ case gcvHAL_TIMESTAMP:
++ /* Check for invalid timer. */
++ if ((Interface->u.TimeStamp.timer >= gcmCOUNTOF(Kernel->timers))
++ || (Interface->u.TimeStamp.request != 2))
++ {
++ Interface->u.TimeStamp.timeDelta = 0;
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ /* Return timer results and reset timer. */
++ {
++ gcsTIMER_PTR timer = &(Kernel->timers[Interface->u.TimeStamp.timer]);
++ gctUINT64 timeDelta = 0;
++
++ if (timer->stopTime < timer->startTime )
++ {
++ Interface->u.TimeStamp.timeDelta = 0;
++ gcmkONERROR(gcvSTATUS_TIMER_OVERFLOW);
++ }
++
++ timeDelta = timer->stopTime - timer->startTime;
++
++ /* Check truncation overflow. */
++ Interface->u.TimeStamp.timeDelta = (gctINT32) timeDelta;
++ /*bit0~bit30 is available*/
++ if (timeDelta>>31)
++ {
++ Interface->u.TimeStamp.timeDelta = 0;
++ gcmkONERROR(gcvSTATUS_TIMER_OVERFLOW);
++ }
++
++ status = gcvSTATUS_OK;
++ }
++ break;
++
++ case gcvHAL_DATABASE:
++ /* Query video memory. */
++ gcmkONERROR(
++ gckKERNEL_QueryProcessDB(Kernel,
++ Interface->u.Database.processID,
++ !Interface->u.Database.validProcessID,
++ gcvDB_VIDEO_MEMORY,
++ &Interface->u.Database.vidMem));
++
++ /* Query non-paged memory. */
++ gcmkONERROR(
++ gckKERNEL_QueryProcessDB(Kernel,
++ Interface->u.Database.processID,
++ !Interface->u.Database.validProcessID,
++ gcvDB_NON_PAGED,
++ &Interface->u.Database.nonPaged));
++
++ /* Query contiguous memory. */
++ gcmkONERROR(
++ gckKERNEL_QueryProcessDB(Kernel,
++ Interface->u.Database.processID,
++ !Interface->u.Database.validProcessID,
++ gcvDB_CONTIGUOUS,
++ &Interface->u.Database.contiguous));
++
++ /* Query GPU idle time. */
++ gcmkONERROR(
++ gckKERNEL_QueryProcessDB(Kernel,
++ Interface->u.Database.processID,
++ !Interface->u.Database.validProcessID,
++ gcvDB_IDLE,
++ &Interface->u.Database.gpuIdle));
++ break;
++
++ case gcvHAL_VIDMEM_DATABASE:
++ /* Query reserved video memory. */
++ gcmkONERROR(
++ gckKERNEL_QueryProcessDB(Kernel,
++ Interface->u.VidMemDatabase.processID,
++ !Interface->u.VidMemDatabase.validProcessID,
++ gcvDB_VIDEO_MEMORY_RESERVED,
++ &Interface->u.VidMemDatabase.vidMemResv));
++
++ /* Query contiguous video memory. */
++ gcmkONERROR(
++ gckKERNEL_QueryProcessDB(Kernel,
++ Interface->u.VidMemDatabase.processID,
++ !Interface->u.VidMemDatabase.validProcessID,
++ gcvDB_VIDEO_MEMORY_CONTIGUOUS,
++ &Interface->u.VidMemDatabase.vidMemCont));
++
++ /* Query virtual video memory. */
++ gcmkONERROR(
++ gckKERNEL_QueryProcessDB(Kernel,
++ Interface->u.VidMemDatabase.processID,
++ !Interface->u.VidMemDatabase.validProcessID,
++ gcvDB_VIDEO_MEMORY_VIRTUAL,
++ &Interface->u.VidMemDatabase.vidMemVirt));
++
++ break;
++
++ case gcvHAL_VERSION:
++ Interface->u.Version.major = gcvVERSION_MAJOR;
++ Interface->u.Version.minor = gcvVERSION_MINOR;
++ Interface->u.Version.patch = gcvVERSION_PATCH;
++ Interface->u.Version.build = gcvVERSION_BUILD;
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_KERNEL,
++ "KERNEL version %d.%d.%d build %u %s %s",
++ gcvVERSION_MAJOR, gcvVERSION_MINOR, gcvVERSION_PATCH,
++ gcvVERSION_BUILD, gcvVERSION_DATE, gcvVERSION_TIME);
++#endif
++ break;
++
++ case gcvHAL_CHIP_INFO:
++ /* Only if not support multi-core */
++ Interface->u.ChipInfo.count = 1;
++ Interface->u.ChipInfo.types[0] = Kernel->hardware->type;
++ break;
++
++ case gcvHAL_ATTACH:
++ /* Attach user process. */
++ gcmkONERROR(
++ gckCOMMAND_Attach(Kernel->command,
++ &context,
++ &bytes,
++ processID));
++
++ Interface->u.Attach.stateCount = bytes;
++ Interface->u.Attach.context = gcmPTR_TO_NAME(context);
++
++ gcmkVERIFY_OK(
++ gckKERNEL_AddProcessDB(Kernel,
++ processID, gcvDB_CONTEXT,
++ gcmINT2PTR(Interface->u.Attach.context),
++ gcvNULL,
++ 0));
++ break;
++
++ case gcvHAL_DETACH:
++ /* Detach user process. */
++ gcmkONERROR(
++ gckCOMMAND_Detach(Kernel->command,
++ gcmNAME_TO_PTR(Interface->u.Detach.context)));
++
++ gcmkVERIFY_OK(
++ gckKERNEL_RemoveProcessDB(Kernel,
++ processID, gcvDB_CONTEXT,
++ gcmINT2PTR(Interface->u.Detach.context)));
++
++ gcmRELEASE_NAME(Interface->u.Detach.context);
++ break;
++
++ case gcvHAL_COMPOSE:
++ Interface->u.Compose.physical = gcmPTR_TO_UINT64(gcmNAME_TO_PTR(Interface->u.Compose.physical));
++ /* Start composition. */
++ gcmkONERROR(
++ gckEVENT_Compose(Kernel->eventObj,
++ &Interface->u.Compose));
++ break;
++
++ case gcvHAL_SET_TIMEOUT:
++ /* set timeOut value from user */
++ gckKERNEL_SetTimeOut(Kernel, Interface->u.SetTimeOut.timeOut);
++ break;
++
++#if gcdFRAME_DB
++ case gcvHAL_GET_FRAME_INFO:
++ gcmkONERROR(gckHARDWARE_GetFrameInfo(
++ Kernel->hardware,
++ gcmUINT64_TO_PTR(Interface->u.GetFrameInfo.frameInfo)));
++ break;
++#endif
++
++ case gcvHAL_GET_SHARED_INFO:
++ if (Interface->u.GetSharedInfo.data == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++ else
++ {
++ gctUINT32 pid = Interface->u.GetSharedInfo.pid;
++ gctUINT32 dataId = Interface->u.GetSharedInfo.dataId;
++ gctSIZE_T bytes = Interface->u.GetSharedInfo.bytes;
++ gctPOINTER data = Interface->u.GetSharedInfo.data;
++ gcsDATABASE_RECORD record;
++
++ /* Find record. */
++ gcmkONERROR(
++ gckKERNEL_FindProcessDB(Kernel,
++ pid,
++ 0,
++ gcvDB_SHARED_INFO,
++ gcmINT2PTR(dataId),
++ &record));
++
++ /* Check memory size. */
++ if (bytes < record.bytes)
++ {
++ /* Insufficient memory to hold shared data. */
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ /* Copy to user. */
++ status = gckOS_CopyToUserData(Kernel->os,
++ record.physical,
++ data,
++ record.bytes);
++
++ /*
++ * Remove from process db.
++ * Every time when shared info is taken, the record is erased in
++ * kernel side.
++ */
++ gcmkVERIFY_OK(
++ gckKERNEL_RemoveProcessDB(Kernel,
++ pid,
++ gcvDB_SHARED_INFO,
++ gcmINT2PTR(dataId)));
++ /* Free existed data. */
++ gcmkVERIFY_OK(
++ gckOS_FreeMemory(Kernel->os, record.physical));
++ }
++ break;
++
++ case gcvHAL_SET_SHARED_INFO:
++ {
++ gctUINT32 dataId = Interface->u.SetSharedInfo.dataId;
++ gctPOINTER data = Interface->u.SetSharedInfo.data;
++ gctUINT32 bytes = Interface->u.SetSharedInfo.bytes;
++ gctPOINTER memory = gcvNULL;
++ gcsDATABASE_RECORD record;
++
++ if (gcmIS_SUCCESS(gckKERNEL_FindProcessDB(Kernel,
++ processID,
++ 0,
++ gcvDB_SHARED_INFO,
++ gcmINT2PTR(dataId),
++ &record)))
++ {
++ /* Find a record with the same id. */
++ if (bytes != record.bytes)
++ {
++ /* Remove from process db. */
++ gcmkVERIFY_OK(
++ gckKERNEL_RemoveProcessDB(Kernel,
++ processID,
++ gcvDB_SHARED_INFO,
++ gcmINT2PTR(dataId)));
++
++ /* Free existed data. */
++ gcmkVERIFY_OK(
++ gckOS_FreeMemory(Kernel->os, record.physical));
++ }
++ else
++ {
++ /* Re-use allocated memory. */
++ memory = record.physical;
++ }
++ }
++
++ if ((data == gcvNULL) || (bytes == 0))
++ {
++ /* Nothing to record. */
++ break;
++ }
++
++ if (bytes > 1024)
++ {
++ /* Limite data size. */
++ gcmkONERROR(gcvSTATUS_TOO_COMPLEX);
++ }
++
++ if (memory == gcvNULL)
++ {
++ /* Allocate memory for holding shared data. */
++ gcmkONERROR(
++ gckOS_AllocateMemory(Kernel->os, bytes, &memory));
++
++ /* Add to process db. */
++ status = gckKERNEL_AddProcessDB(Kernel,
++ processID,
++ gcvDB_SHARED_INFO,
++ gcmINT2PTR(dataId),
++ memory,
++ bytes);
++
++ if (gcmIS_ERROR(status))
++ {
++ /* Failed to add process db. Free allocated memory. */
++ gcmkVERIFY_OK(gckOS_FreeMemory(Kernel->os, memory));
++ break;
++ }
++ }
++
++ /* Copy shared data to kernel memory. */
++ gcmkONERROR(
++ gckOS_CopyFromUserData(Kernel->os,
++ memory,
++ data,
++ bytes));
++ }
++ break;
++
++ case gcvHAL_SET_FSCALE_VALUE:
++#if gcdENABLE_FSCALE_VAL_ADJUST
++ status = gckHARDWARE_SetFscaleValue(Kernel->hardware,
++ Interface->u.SetFscaleValue.value);
++#else
++ status = gcvSTATUS_NOT_SUPPORTED;
++#endif
++ break;
++ case gcvHAL_GET_FSCALE_VALUE:
++#if gcdENABLE_FSCALE_VAL_ADJUST
++ status = gckHARDWARE_GetFscaleValue(Kernel->hardware,
++ &Interface->u.GetFscaleValue.value,
++ &Interface->u.GetFscaleValue.minValue,
++ &Interface->u.GetFscaleValue.maxValue);
++#else
++ status = gcvSTATUS_NOT_SUPPORTED;
++#endif
++ break;
++
++ case gcvHAL_QUERY_RESET_TIME_STAMP:
++#if gcdENABLE_RECOVERY
++ Interface->u.QueryResetTimeStamp.timeStamp = Kernel->resetTimeStamp;
++#else
++ Interface->u.QueryResetTimeStamp.timeStamp = 0;
++#endif
++ break;
++
++#if gcdANDROID_NATIVE_FENCE_SYNC
++ case gcvHAL_SYNC_POINT:
++ {
++ gctSYNC_POINT syncPoint;
++
++ switch (Interface->u.SyncPoint.command)
++ {
++ case gcvSYNC_POINT_CREATE:
++ gcmkONERROR(gckOS_CreateSyncPoint(Kernel->os, &syncPoint));
++
++ Interface->u.SyncPoint.syncPoint = gcmPTR_TO_UINT64(syncPoint);
++
++ gcmkVERIFY_OK(
++ gckKERNEL_AddProcessDB(Kernel,
++ processID, gcvDB_SYNC_POINT,
++ syncPoint,
++ gcvNULL,
++ 0));
++ break;
++
++ case gcvSYNC_POINT_DESTROY:
++ syncPoint = gcmUINT64_TO_PTR(Interface->u.SyncPoint.syncPoint);
++
++ gcmkONERROR(gckOS_DestroySyncPoint(Kernel->os, syncPoint));
++
++ gcmkVERIFY_OK(
++ gckKERNEL_RemoveProcessDB(Kernel,
++ processID, gcvDB_SYNC_POINT,
++ syncPoint));
++ break;
++
++ default:
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ break;
++ }
++ }
++ break;
++
++ case gcvHAL_CREATE_NATIVE_FENCE:
++ {
++ gctINT fenceFD;
++ gctSYNC_POINT syncPoint =
++ gcmUINT64_TO_PTR(Interface->u.CreateNativeFence.syncPoint);
++
++ gcmkONERROR(
++ gckOS_CreateNativeFence(Kernel->os,
++ Kernel->timeline,
++ syncPoint,
++ &fenceFD));
++
++ Interface->u.CreateNativeFence.fenceFD = fenceFD;
++ }
++ break;
++#endif
++
++ default:
++ /* Invalid command. */
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++OnError:
++ /* Save status. */
++ Interface->status = status;
++
++ if (gcmIS_ERROR(status))
++ {
++ if (locked)
++ {
++ /* Roll back the lock. */
++ gcmkVERIFY_OK(
++ gckVIDMEM_Unlock(Kernel,
++ gcmUINT64_TO_PTR(Interface->u.LockVideoMemory.node),
++ gcvSURF_TYPE_UNKNOWN,
++ &asynchronous));
++
++ if (gcvTRUE == asynchronous)
++ {
++ /* Bottom Half */
++ gcmkVERIFY_OK(
++ gckVIDMEM_Unlock(Kernel,
++ gcmUINT64_TO_PTR(Interface->u.LockVideoMemory.node),
++ gcvSURF_TYPE_UNKNOWN,
++ gcvNULL));
++ }
++ }
++ }
++
++#if QNX_SINGLE_THREADED_DEBUGGING
++ gckOS_ReleaseMutex(Kernel->os, Kernel->debugMutex);
++#endif
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++** gckKERNEL_AttachProcess
++**
++** Attach or detach a process.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gctBOOL Attach
++** gcvTRUE if a new process gets attached or gcFALSE when a process
++** gets detatched.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckKERNEL_AttachProcess(
++ IN gckKERNEL Kernel,
++ IN gctBOOL Attach
++ )
++{
++ gceSTATUS status;
++ gctUINT32 processID;
++
++ gcmkHEADER_ARG("Kernel=0x%x Attach=%d", Kernel, Attach);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++
++ /* Get current process ID. */
++ gcmkONERROR(gckOS_GetProcessID(&processID));
++
++ gcmkONERROR(gckKERNEL_AttachProcessEx(Kernel, Attach, processID));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++** gckKERNEL_AttachProcessEx
++**
++** Attach or detach a process with the given PID. Can be paired with gckKERNEL_AttachProcess
++** provided the programmer is aware of the consequences.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gctBOOL Attach
++** gcvTRUE if a new process gets attached or gcFALSE when a process
++** gets detatched.
++**
++** gctUINT32 PID
++** PID of the process to attach or detach.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckKERNEL_AttachProcessEx(
++ IN gckKERNEL Kernel,
++ IN gctBOOL Attach,
++ IN gctUINT32 PID
++ )
++{
++ gceSTATUS status;
++ gctINT32 old;
++
++ gcmkHEADER_ARG("Kernel=0x%x Attach=%d PID=%d", Kernel, Attach, PID);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++
++ if (Attach)
++ {
++ /* Increment the number of clients attached. */
++ gcmkONERROR(
++ gckOS_AtomIncrement(Kernel->os, Kernel->atomClients, &old));
++
++ if (old == 0)
++ {
++#if gcdENABLE_VG
++ if (Kernel->vg == gcvNULL)
++#endif
++ {
++ gcmkONERROR(gckOS_Broadcast(Kernel->os,
++ Kernel->hardware,
++ gcvBROADCAST_FIRST_PROCESS));
++ }
++ }
++
++ if (Kernel->dbCreated)
++ {
++ /* Create the process database. */
++ gcmkONERROR(gckKERNEL_CreateProcessDB(Kernel, PID));
++ }
++ }
++ else
++ {
++ if (Kernel->dbCreated)
++ {
++ /* Clean up the process database. */
++ gcmkONERROR(gckKERNEL_DestroyProcessDB(Kernel, PID));
++
++ /* Save the last know process ID. */
++ Kernel->db->lastProcessID = PID;
++ }
++
++#if gcdENABLE_VG
++ if (Kernel->vg == gcvNULL)
++#endif
++ {
++ status = gckEVENT_Submit(Kernel->eventObj, gcvTRUE, gcvFALSE);
++
++ if (status == gcvSTATUS_INTERRUPTED && Kernel->eventObj->submitTimer)
++ {
++ gcmkONERROR(gckOS_StartTimer(Kernel->os,
++ Kernel->eventObj->submitTimer,
++ 1));
++ }
++ else
++ {
++ gcmkONERROR(status);
++ }
++ }
++
++ /* Decrement the number of clients attached. */
++ gcmkONERROR(
++ gckOS_AtomDecrement(Kernel->os, Kernel->atomClients, &old));
++
++ if (old == 1)
++ {
++#if gcdENABLE_VG
++ if (Kernel->vg == gcvNULL)
++#endif
++ {
++ /* Last client detached, switch to SUSPEND power state. */
++ gcmkONERROR(gckOS_Broadcast(Kernel->os,
++ Kernel->hardware,
++ gcvBROADCAST_LAST_PROCESS));
++ }
++
++ /* Flush the debug cache. */
++ gcmkDEBUGFLUSH(~0U);
++ }
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++#if gcdSECURE_USER
++gceSTATUS
++gckKERNEL_MapLogicalToPhysical(
++ IN gckKERNEL Kernel,
++ IN gcskSECURE_CACHE_PTR Cache,
++ IN OUT gctPOINTER * Data
++ )
++{
++ gceSTATUS status;
++ static gctBOOL baseAddressValid = gcvFALSE;
++ static gctUINT32 baseAddress;
++ gctBOOL needBase;
++ gcskLOGICAL_CACHE_PTR slot;
++
++ gcmkHEADER_ARG("Kernel=0x%x Cache=0x%x *Data=0x%x",
++ Kernel, Cache, gcmOPT_POINTER(Data));
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++
++ if (!baseAddressValid)
++ {
++ /* Get base address. */
++ gcmkONERROR(gckHARDWARE_GetBaseAddress(Kernel->hardware, &baseAddress));
++
++ baseAddressValid = gcvTRUE;
++ }
++
++ /* Does this state load need a base address? */
++ gcmkONERROR(gckHARDWARE_NeedBaseAddress(Kernel->hardware,
++ ((gctUINT32_PTR) Data)[-1],
++ &needBase));
++
++#if gcdSECURE_CACHE_METHOD == gcdSECURE_CACHE_LRU
++ {
++ gcskLOGICAL_CACHE_PTR next;
++ gctINT i;
++
++ /* Walk all used cache slots. */
++ for (i = 1, slot = Cache->cache[0].next, next = gcvNULL;
++ (i <= gcdSECURE_CACHE_SLOTS) && (slot->logical != gcvNULL);
++ ++i, slot = slot->next
++ )
++ {
++ if (slot->logical == *Data)
++ {
++ /* Bail out. */
++ next = slot;
++ break;
++ }
++ }
++
++ /* See if we had a miss. */
++ if (next == gcvNULL)
++ {
++ /* Use the tail of the cache. */
++ slot = Cache->cache[0].prev;
++
++ /* Initialize the cache line. */
++ slot->logical = *Data;
++
++ /* Map the logical address to a DMA address. */
++ gcmkONERROR(
++ gckOS_GetPhysicalAddress(Kernel->os, *Data, &slot->dma));
++ }
++
++ /* Move slot to head of list. */
++ if (slot != Cache->cache[0].next)
++ {
++ /* Unlink. */
++ slot->prev->next = slot->next;
++ slot->next->prev = slot->prev;
++
++ /* Move to head of chain. */
++ slot->prev = &Cache->cache[0];
++ slot->next = Cache->cache[0].next;
++ slot->prev->next = slot;
++ slot->next->prev = slot;
++ }
++ }
++#elif gcdSECURE_CACHE_METHOD == gcdSECURE_CACHE_LINEAR
++ {
++ gctINT i;
++ gcskLOGICAL_CACHE_PTR next = gcvNULL;
++ gcskLOGICAL_CACHE_PTR oldestSlot = gcvNULL;
++ slot = gcvNULL;
++
++ if (Cache->cacheIndex != gcvNULL)
++ {
++ /* Walk the cache forwards. */
++ for (i = 1, slot = Cache->cacheIndex;
++ (i <= gcdSECURE_CACHE_SLOTS) && (slot->logical != gcvNULL);
++ ++i, slot = slot->next)
++ {
++ if (slot->logical == *Data)
++ {
++ /* Bail out. */
++ next = slot;
++ break;
++ }
++
++ /* Determine age of this slot. */
++ if ((oldestSlot == gcvNULL)
++ || (oldestSlot->stamp > slot->stamp)
++ )
++ {
++ oldestSlot = slot;
++ }
++ }
++
++ if (next == gcvNULL)
++ {
++ /* Walk the cache backwards. */
++ for (slot = Cache->cacheIndex->prev;
++ (i <= gcdSECURE_CACHE_SLOTS) && (slot->logical != gcvNULL);
++ ++i, slot = slot->prev)
++ {
++ if (slot->logical == *Data)
++ {
++ /* Bail out. */
++ next = slot;
++ break;
++ }
++
++ /* Determine age of this slot. */
++ if ((oldestSlot == gcvNULL)
++ || (oldestSlot->stamp > slot->stamp)
++ )
++ {
++ oldestSlot = slot;
++ }
++ }
++ }
++ }
++
++ /* See if we had a miss. */
++ if (next == gcvNULL)
++ {
++ if (Cache->cacheFree != 0)
++ {
++ slot = &Cache->cache[Cache->cacheFree];
++ gcmkASSERT(slot->logical == gcvNULL);
++
++ ++ Cache->cacheFree;
++ if (Cache->cacheFree >= gcmCOUNTOF(Cache->cache))
++ {
++ Cache->cacheFree = 0;
++ }
++ }
++ else
++ {
++ /* Use the oldest cache slot. */
++ gcmkASSERT(oldestSlot != gcvNULL);
++ slot = oldestSlot;
++
++ /* Unlink from the chain. */
++ slot->prev->next = slot->next;
++ slot->next->prev = slot->prev;
++
++ /* Append to the end. */
++ slot->prev = Cache->cache[0].prev;
++ slot->next = &Cache->cache[0];
++ slot->prev->next = slot;
++ slot->next->prev = slot;
++ }
++
++ /* Initialize the cache line. */
++ slot->logical = *Data;
++
++ /* Map the logical address to a DMA address. */
++ gcmkONERROR(
++ gckOS_GetPhysicalAddress(Kernel->os, *Data, &slot->dma));
++ }
++
++ /* Save time stamp. */
++ slot->stamp = ++ Cache->cacheStamp;
++
++ /* Save current slot for next lookup. */
++ Cache->cacheIndex = slot;
++ }
++#elif gcdSECURE_CACHE_METHOD == gcdSECURE_CACHE_HASH
++ {
++ gctINT i;
++ gctUINT32 data = gcmPTR2INT(*Data);
++ gctUINT32 key, index;
++ gcskLOGICAL_CACHE_PTR hash;
++
++ /* Generate a hash key. */
++ key = (data >> 24) + (data >> 16) + (data >> 8) + data;
++ index = key % gcmCOUNTOF(Cache->hash);
++
++ /* Get the hash entry. */
++ hash = &Cache->hash[index];
++
++ for (slot = hash->nextHash, i = 0;
++ (slot != gcvNULL) && (i < gcdSECURE_CACHE_SLOTS);
++ slot = slot->nextHash, ++i
++ )
++ {
++ if (slot->logical == (*Data))
++ {
++ break;
++ }
++ }
++
++ if (slot == gcvNULL)
++ {
++ /* Grab from the tail of the cache. */
++ slot = Cache->cache[0].prev;
++
++ /* Unlink slot from any hash table it is part of. */
++ if (slot->prevHash != gcvNULL)
++ {
++ slot->prevHash->nextHash = slot->nextHash;
++ }
++ if (slot->nextHash != gcvNULL)
++ {
++ slot->nextHash->prevHash = slot->prevHash;
++ }
++
++ /* Initialize the cache line. */
++ slot->logical = *Data;
++
++ /* Map the logical address to a DMA address. */
++ gcmkONERROR(
++ gckOS_GetPhysicalAddress(Kernel->os, *Data, &slot->dma));
++
++ if (hash->nextHash != gcvNULL)
++ {
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_KERNEL,
++ "Hash Collision: logical=0x%x key=0x%08x",
++ *Data, key);
++ }
++
++ /* Insert the slot at the head of the hash list. */
++ slot->nextHash = hash->nextHash;
++ if (slot->nextHash != gcvNULL)
++ {
++ slot->nextHash->prevHash = slot;
++ }
++ slot->prevHash = hash;
++ hash->nextHash = slot;
++ }
++
++ /* Move slot to head of list. */
++ if (slot != Cache->cache[0].next)
++ {
++ /* Unlink. */
++ slot->prev->next = slot->next;
++ slot->next->prev = slot->prev;
++
++ /* Move to head of chain. */
++ slot->prev = &Cache->cache[0];
++ slot->next = Cache->cache[0].next;
++ slot->prev->next = slot;
++ slot->next->prev = slot;
++ }
++ }
++#elif gcdSECURE_CACHE_METHOD == gcdSECURE_CACHE_TABLE
++ {
++ gctUINT32 index = (gcmPTR2INT(*Data) % gcdSECURE_CACHE_SLOTS) + 1;
++
++ /* Get cache slot. */
++ slot = &Cache->cache[index];
++
++ /* Check for cache miss. */
++ if (slot->logical != *Data)
++ {
++ /* Initialize the cache line. */
++ slot->logical = *Data;
++
++ /* Map the logical address to a DMA address. */
++ gcmkONERROR(
++ gckOS_GetPhysicalAddress(Kernel->os, *Data, &slot->dma));
++ }
++ }
++#endif
++
++ /* Return DMA address. */
++ *Data = gcmINT2PTR(slot->dma + (needBase ? baseAddress : 0));
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Data=0x%08x", *Data);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckKERNEL_FlushTranslationCache(
++ IN gckKERNEL Kernel,
++ IN gcskSECURE_CACHE_PTR Cache,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes
++ )
++{
++ gctINT i;
++ gcskLOGICAL_CACHE_PTR slot;
++ gctUINT8_PTR ptr;
++
++ gcmkHEADER_ARG("Kernel=0x%x Cache=0x%x Logical=0x%x Bytes=%lu",
++ Kernel, Cache, Logical, Bytes);
++
++ /* Do we need to flush the entire cache? */
++ if (Logical == gcvNULL)
++ {
++ /* Clear all cache slots. */
++ for (i = 1; i <= gcdSECURE_CACHE_SLOTS; ++i)
++ {
++ Cache->cache[i].logical = gcvNULL;
++
++#if gcdSECURE_CACHE_METHOD == gcdSECURE_CACHE_HASH
++ Cache->cache[i].nextHash = gcvNULL;
++ Cache->cache[i].prevHash = gcvNULL;
++#endif
++}
++
++#if gcdSECURE_CACHE_METHOD == gcdSECURE_CACHE_HASH
++ /* Zero the hash table. */
++ for (i = 0; i < gcmCOUNTOF(Cache->hash); ++i)
++ {
++ Cache->hash[i].nextHash = gcvNULL;
++ }
++#endif
++
++ /* Reset the cache functionality. */
++ Cache->cacheIndex = gcvNULL;
++ Cache->cacheFree = 1;
++ Cache->cacheStamp = 0;
++ }
++
++ else
++ {
++ gctUINT8_PTR low = (gctUINT8_PTR) Logical;
++ gctUINT8_PTR high = low + Bytes;
++
++#if gcdSECURE_CACHE_METHOD == gcdSECURE_CACHE_LRU
++ gcskLOGICAL_CACHE_PTR next;
++
++ /* Walk all used cache slots. */
++ for (i = 1, slot = Cache->cache[0].next;
++ (i <= gcdSECURE_CACHE_SLOTS) && (slot->logical != gcvNULL);
++ ++i, slot = next
++ )
++ {
++ /* Save pointer to next slot. */
++ next = slot->next;
++
++ /* Test if this slot falls within the range to flush. */
++ ptr = (gctUINT8_PTR) slot->logical;
++ if ((ptr >= low) && (ptr < high))
++ {
++ /* Unlink slot. */
++ slot->prev->next = slot->next;
++ slot->next->prev = slot->prev;
++
++ /* Append slot to tail of cache. */
++ slot->prev = Cache->cache[0].prev;
++ slot->next = &Cache->cache[0];
++ slot->prev->next = slot;
++ slot->next->prev = slot;
++
++ /* Mark slot as empty. */
++ slot->logical = gcvNULL;
++ }
++ }
++
++#elif gcdSECURE_CACHE_METHOD == gcdSECURE_CACHE_LINEAR
++ gcskLOGICAL_CACHE_PTR next;
++
++ for (i = 1, slot = Cache->cache[0].next;
++ (i <= gcdSECURE_CACHE_SLOTS) && (slot->logical != gcvNULL);
++ ++i, slot = next)
++ {
++ /* Save pointer to next slot. */
++ next = slot->next;
++
++ /* Test if this slot falls within the range to flush. */
++ ptr = (gctUINT8_PTR) slot->logical;
++ if ((ptr >= low) && (ptr < high))
++ {
++ /* Test if this slot is the current slot. */
++ if (slot == Cache->cacheIndex)
++ {
++ /* Move to next or previous slot. */
++ Cache->cacheIndex = (slot->next->logical != gcvNULL)
++ ? slot->next
++ : (slot->prev->logical != gcvNULL)
++ ? slot->prev
++ : gcvNULL;
++ }
++
++ /* Unlink slot from cache. */
++ slot->prev->next = slot->next;
++ slot->next->prev = slot->prev;
++
++ /* Insert slot to head of cache. */
++ slot->prev = &Cache->cache[0];
++ slot->next = Cache->cache[0].next;
++ slot->prev->next = slot;
++ slot->next->prev = slot;
++
++ /* Mark slot as empty. */
++ slot->logical = gcvNULL;
++ slot->stamp = 0;
++ }
++ }
++
++#elif gcdSECURE_CACHE_METHOD == gcdSECURE_CACHE_HASH
++ gctINT j;
++ gcskLOGICAL_CACHE_PTR hash, next;
++
++ /* Walk all hash tables. */
++ for (i = 0, hash = Cache->hash;
++ i < gcmCOUNTOF(Cache->hash);
++ ++i, ++hash)
++ {
++ /* Walk all slots in the hash. */
++ for (j = 0, slot = hash->nextHash;
++ (j < gcdSECURE_CACHE_SLOTS) && (slot != gcvNULL);
++ ++j, slot = next)
++ {
++ /* Save pointer to next slot. */
++ next = slot->next;
++
++ /* Test if this slot falls within the range to flush. */
++ ptr = (gctUINT8_PTR) slot->logical;
++ if ((ptr >= low) && (ptr < high))
++ {
++ /* Unlink slot from hash table. */
++ if (slot->prevHash == hash)
++ {
++ hash->nextHash = slot->nextHash;
++ }
++ else
++ {
++ slot->prevHash->nextHash = slot->nextHash;
++ }
++
++ if (slot->nextHash != gcvNULL)
++ {
++ slot->nextHash->prevHash = slot->prevHash;
++ }
++
++ /* Unlink slot from cache. */
++ slot->prev->next = slot->next;
++ slot->next->prev = slot->prev;
++
++ /* Append slot to tail of cache. */
++ slot->prev = Cache->cache[0].prev;
++ slot->next = &Cache->cache[0];
++ slot->prev->next = slot;
++ slot->next->prev = slot;
++
++ /* Mark slot as empty. */
++ slot->logical = gcvNULL;
++ slot->prevHash = gcvNULL;
++ slot->nextHash = gcvNULL;
++ }
++ }
++ }
++
++#elif gcdSECURE_CACHE_METHOD == gcdSECURE_CACHE_TABLE
++ gctUINT32 index;
++
++ /* Loop while inside the range. */
++ for (i = 1; (low < high) && (i <= gcdSECURE_CACHE_SLOTS); ++i)
++ {
++ /* Get index into cache for this range. */
++ index = (gcmPTR2INT(low) % gcdSECURE_CACHE_SLOTS) + 1;
++ slot = &Cache->cache[index];
++
++ /* Test if this slot falls within the range to flush. */
++ ptr = (gctUINT8_PTR) slot->logical;
++ if ((ptr >= low) && (ptr < high))
++ {
++ /* Remove entry from cache. */
++ slot->logical = gcvNULL;
++ }
++
++ /* Next block. */
++ low += gcdSECURE_CACHE_SLOTS;
++ }
++#endif
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++#endif
++
++/*******************************************************************************
++**
++** gckKERNEL_Recovery
++**
++** Try to recover the GPU from a fatal error.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckKERNEL_Recovery(
++ IN gckKERNEL Kernel
++ )
++{
++#if gcdENABLE_RECOVERY
++#define gcdEVENT_MASK 0x3FFFFFFF
++ gceSTATUS status;
++ gckEVENT eventObj;
++ gckHARDWARE hardware;
++#if gcdSECURE_USER
++ gctUINT32 processID;
++ gcskSECURE_CACHE_PTR cache;
++#endif
++ gctUINT32 oldValue;
++ gcmkHEADER_ARG("Kernel=0x%x", Kernel);
++
++ /* Validate the arguemnts. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++
++ /* Grab gckEVENT object. */
++ eventObj = Kernel->eventObj;
++ gcmkVERIFY_OBJECT(eventObj, gcvOBJ_EVENT);
++
++ /* Grab gckHARDWARE object. */
++ hardware = Kernel->hardware;
++ gcmkVERIFY_OBJECT(hardware, gcvOBJ_HARDWARE);
++
++#if gcdSECURE_USER
++ /* Flush the secure mapping cache. */
++ gcmkONERROR(gckOS_GetProcessID(&processID));
++ gcmkONERROR(gckKERNEL_GetProcessDBCache(Kernel, processID, &cache));
++ gcmkONERROR(gckKERNEL_FlushTranslationCache(Kernel, cache, gcvNULL, 0));
++#endif
++
++ gcmkONERROR(
++ gckOS_AtomicExchange(Kernel->os, Kernel->resetAtom, 1, &oldValue));
++
++ if (oldValue)
++ {
++ /* Some one else will recovery GPU. */
++ return gcvSTATUS_OK;
++ }
++
++ gcmkPRINT("[galcore]: GPU[%d] hang, automatic recovery.", Kernel->core);
++
++ /* Start a timer to clear reset flag, before timer is expired,
++ ** other recovery request is ignored. */
++ gcmkVERIFY_OK(
++ gckOS_StartTimer(Kernel->os,
++ Kernel->resetFlagClearTimer,
++ gcdGPU_TIMEOUT - 500));
++
++
++ /* Try issuing a soft reset for the GPU. */
++ status = gckHARDWARE_Reset(hardware);
++ if (status == gcvSTATUS_NOT_SUPPORTED)
++ {
++ /* Switch to OFF power. The next submit should return the GPU to ON
++ ** state. */
++ gcmkONERROR(
++ gckHARDWARE_SetPowerManagementState(hardware,
++ gcvPOWER_OFF_RECOVERY));
++ }
++ else
++ {
++ /* Bail out on reset error. */
++ gcmkONERROR(status);
++ }
++
++ /* Handle all outstanding events now. */
++#if gcdSMP
++ gcmkONERROR(gckOS_AtomSet(Kernel->os, eventObj->pending, gcdEVENT_MASK));
++#else
++ eventObj->pending = gcdEVENT_MASK;
++#endif
++ gcmkONERROR(gckEVENT_Notify(eventObj, 1));
++
++ /* Again in case more events got submitted. */
++#if gcdSMP
++ gcmkONERROR(gckOS_AtomSet(Kernel->os, eventObj->pending, gcdEVENT_MASK));
++#else
++ eventObj->pending = gcdEVENT_MASK;
++#endif
++ gcmkONERROR(gckEVENT_Notify(eventObj, 2));
++
++ Kernel->resetTimeStamp++;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++#else
++ return gcvSTATUS_OK;
++#endif
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_OpenUserData
++**
++** Get access to the user data.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gctBOOL NeedCopy
++** The flag indicating whether or not the data should be copied.
++**
++** gctPOINTER StaticStorage
++** Pointer to the kernel storage where the data is to be copied if
++** NeedCopy is gcvTRUE.
++**
++** gctPOINTER UserPointer
++** User pointer to the data.
++**
++** gctSIZE_T Size
++** Size of the data.
++**
++** OUTPUT:
++**
++** gctPOINTER * KernelPointer
++** Pointer to the kernel pointer that will be pointing to the data.
++*/
++gceSTATUS
++gckKERNEL_OpenUserData(
++ IN gckKERNEL Kernel,
++ IN gctBOOL NeedCopy,
++ IN gctPOINTER StaticStorage,
++ IN gctPOINTER UserPointer,
++ IN gctSIZE_T Size,
++ OUT gctPOINTER * KernelPointer
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG(
++ "Kernel=0x%08X NeedCopy=%d StaticStorage=0x%08X "
++ "UserPointer=0x%08X Size=%lu KernelPointer=0x%08X",
++ Kernel, NeedCopy, StaticStorage, UserPointer, Size, KernelPointer
++ );
++
++ /* Validate the arguemnts. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(!NeedCopy || (StaticStorage != gcvNULL));
++ gcmkVERIFY_ARGUMENT(UserPointer != gcvNULL);
++ gcmkVERIFY_ARGUMENT(KernelPointer != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Size > 0);
++
++ if (NeedCopy)
++ {
++ /* Copy the user data to the static storage. */
++ gcmkONERROR(gckOS_CopyFromUserData(
++ Kernel->os, StaticStorage, UserPointer, Size
++ ));
++
++ /* Set the kernel pointer. */
++ * KernelPointer = StaticStorage;
++ }
++ else
++ {
++ gctPOINTER pointer = gcvNULL;
++
++ /* Map the user pointer. */
++ gcmkONERROR(gckOS_MapUserPointer(
++ Kernel->os, UserPointer, Size, &pointer
++ ));
++
++ /* Set the kernel pointer. */
++ * KernelPointer = pointer;
++ }
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_CloseUserData
++**
++** Release resources associated with the user data connection opened by
++** gckKERNEL_OpenUserData.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gctBOOL NeedCopy
++** The flag indicating whether or not the data should be copied.
++**
++** gctBOOL FlushData
++** If gcvTRUE, the data is written back to the user.
++**
++** gctPOINTER UserPointer
++** User pointer to the data.
++**
++** gctSIZE_T Size
++** Size of the data.
++**
++** OUTPUT:
++**
++** gctPOINTER * KernelPointer
++** Kernel pointer to the data.
++*/
++gceSTATUS
++gckKERNEL_CloseUserData(
++ IN gckKERNEL Kernel,
++ IN gctBOOL NeedCopy,
++ IN gctBOOL FlushData,
++ IN gctPOINTER UserPointer,
++ IN gctSIZE_T Size,
++ OUT gctPOINTER * KernelPointer
++ )
++{
++ gceSTATUS status = gcvSTATUS_OK;
++ gctPOINTER pointer;
++
++ gcmkHEADER_ARG(
++ "Kernel=0x%08X NeedCopy=%d FlushData=%d "
++ "UserPointer=0x%08X Size=%lu KernelPointer=0x%08X",
++ Kernel, NeedCopy, FlushData, UserPointer, Size, KernelPointer
++ );
++
++ /* Validate the arguemnts. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(UserPointer != gcvNULL);
++ gcmkVERIFY_ARGUMENT(KernelPointer != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Size > 0);
++
++ /* Get a shortcut to the kernel pointer. */
++ pointer = * KernelPointer;
++
++ if (pointer != gcvNULL)
++ {
++ if (NeedCopy)
++ {
++ if (FlushData)
++ {
++ gcmkONERROR(gckOS_CopyToUserData(
++ Kernel->os, * KernelPointer, UserPointer, Size
++ ));
++ }
++ }
++ else
++ {
++ /* Unmap record from kernel memory. */
++ gcmkONERROR(gckOS_UnmapUserPointer(
++ Kernel->os,
++ UserPointer,
++ Size,
++ * KernelPointer
++ ));
++ }
++
++ /* Reset the kernel pointer. */
++ * KernelPointer = gcvNULL;
++ }
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++void
++gckKERNEL_SetTimeOut(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 timeOut
++ )
++{
++ gcmkHEADER_ARG("Kernel=0x%x timeOut=%d", Kernel, timeOut);
++#if gcdGPU_TIMEOUT
++ Kernel->timeOut = timeOut;
++#endif
++ gcmkFOOTER_NO();
++}
++
++#if gcdVIRTUAL_COMMAND_BUFFER
++gceSTATUS
++gckKERNEL_AllocateVirtualCommandBuffer(
++ IN gckKERNEL Kernel,
++ IN gctBOOL InUserSpace,
++ IN OUT gctSIZE_T * Bytes,
++ OUT gctPHYS_ADDR * Physical,
++ OUT gctPOINTER * Logical
++ )
++{
++ gckOS os = Kernel->os;
++ gceSTATUS status;
++ gctPOINTER logical;
++ gctSIZE_T pageCount;
++ gctSIZE_T bytes = *Bytes;
++ gckVIRTUAL_COMMAND_BUFFER_PTR buffer;
++
++ gcmkHEADER_ARG("Os=0x%X InUserSpace=%d *Bytes=%lu",
++ os, InUserSpace, gcmOPT_VALUE(Bytes));
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Bytes != gcvNULL);
++ gcmkVERIFY_ARGUMENT(*Bytes > 0);
++ gcmkVERIFY_ARGUMENT(Physical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++
++ gcmkONERROR(gckOS_Allocate(os,
++ sizeof(gckVIRTUAL_COMMAND_BUFFER),
++ (gctPOINTER)&buffer));
++
++ gcmkONERROR(gckOS_ZeroMemory(buffer, sizeof(gckVIRTUAL_COMMAND_BUFFER)));
++
++ gcmkONERROR(gckOS_AllocatePagedMemoryEx(os,
++ gcvFALSE,
++ bytes,
++ &buffer->physical));
++
++ if (InUserSpace)
++ {
++ gcmkONERROR(gckOS_LockPages(os,
++ buffer->physical,
++ bytes,
++ gcvFALSE,
++ &logical,
++ &pageCount));
++
++ *Logical =
++ buffer->userLogical = logical;
++ }
++ else
++ {
++ gcmkONERROR(
++ gckOS_CreateKernelVirtualMapping(buffer->physical,
++ &pageCount,
++ &logical));
++ *Logical =
++ buffer->kernelLogical = logical;
++ }
++
++ buffer->pageCount = pageCount;
++ buffer->kernel = Kernel;
++
++ gcmkONERROR(gckOS_GetProcessID(&buffer->pid));
++
++ gcmkONERROR(gckMMU_AllocatePages(Kernel->mmu,
++ pageCount,
++ &buffer->pageTable,
++ &buffer->gpuAddress));
++
++ gcmkONERROR(gckOS_MapPagesEx(os,
++ Kernel->core,
++ buffer->physical,
++ pageCount,
++ buffer->pageTable));
++
++ gcmkONERROR(gckMMU_Flush(Kernel->mmu));
++
++ *Physical = buffer;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_KERNEL,
++ "gpuAddress = %x pageCount = %d kernelLogical = %x userLogical=%x",
++ buffer->gpuAddress, buffer->pageCount,
++ buffer->kernelLogical, buffer->userLogical);
++
++ gcmkVERIFY_OK(gckOS_AcquireMutex(os, Kernel->virtualBufferLock, gcvINFINITE));
++
++ if (Kernel->virtualBufferHead == gcvNULL)
++ {
++ Kernel->virtualBufferHead =
++ Kernel->virtualBufferTail = buffer;
++ }
++ else
++ {
++ buffer->prev = Kernel->virtualBufferTail;
++ Kernel->virtualBufferTail->next = buffer;
++ Kernel->virtualBufferTail = buffer;
++ }
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(os, Kernel->virtualBufferLock));
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (buffer->gpuAddress)
++ {
++ gcmkVERIFY_OK(
++ gckMMU_FreePages(Kernel->mmu, buffer->pageTable, buffer->pageCount));
++ }
++
++ if (buffer->userLogical)
++ {
++ gcmkVERIFY_OK(
++ gckOS_UnlockPages(os, buffer->physical, bytes, buffer->userLogical));
++ }
++
++ if (buffer->kernelLogical)
++ {
++ gcmkVERIFY_OK(
++ gckOS_DestroyKernelVirtualMapping(buffer->kernelLogical));
++ }
++
++ if (buffer->physical)
++ {
++ gcmkVERIFY_OK(gckOS_FreePagedMemory(os, buffer->physical, bytes));
++ }
++
++ gcmkVERIFY_OK(gckOS_Free(os, buffer));
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckKERNEL_DestroyVirtualCommandBuffer(
++ IN gckKERNEL Kernel,
++ IN gctSIZE_T Bytes,
++ IN gctPHYS_ADDR Physical,
++ IN gctPOINTER Logical
++ )
++{
++ gckOS os;
++ gckKERNEL kernel;
++ gckVIRTUAL_COMMAND_BUFFER_PTR buffer = (gckVIRTUAL_COMMAND_BUFFER_PTR)Physical;
++
++ gcmkHEADER();
++ gcmkVERIFY_ARGUMENT(buffer != gcvNULL);
++
++ kernel = buffer->kernel;
++ os = kernel->os;
++
++ if (buffer->userLogical)
++ {
++ gcmkVERIFY_OK(gckOS_UnlockPages(os, buffer->physical, Bytes, Logical));
++ }
++ else
++ {
++ gcmkVERIFY_OK(gckOS_DestroyKernelVirtualMapping(Logical));
++ }
++
++ gcmkVERIFY_OK(
++ gckMMU_FreePages(kernel->mmu, buffer->pageTable, buffer->pageCount));
++
++ gcmkVERIFY_OK(gckOS_FreePagedMemory(os, buffer->physical, Bytes));
++
++ gcmkVERIFY_OK(gckOS_AcquireMutex(os, kernel->virtualBufferLock, gcvINFINITE));
++
++ if (buffer == kernel->virtualBufferHead)
++ {
++ if ((kernel->virtualBufferHead = buffer->next) == gcvNULL)
++ {
++ kernel->virtualBufferTail = gcvNULL;
++ }
++ }
++ else
++ {
++ buffer->prev->next = buffer->next;
++
++ if (buffer == kernel->virtualBufferTail)
++ {
++ kernel->virtualBufferTail = buffer->prev;
++ }
++ else
++ {
++ buffer->next->prev = buffer->prev;
++ }
++ }
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(os, kernel->virtualBufferLock));
++
++ gcmkVERIFY_OK(gckOS_Free(os, buffer));
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckKERNEL_GetGPUAddress(
++ IN gckKERNEL Kernel,
++ IN gctPOINTER Logical,
++ OUT gctUINT32 * Address
++ )
++{
++ gceSTATUS status;
++ gckVIRTUAL_COMMAND_BUFFER_PTR buffer;
++ gctPOINTER start;
++ gctINT pid;
++
++ gcmkHEADER_ARG("Logical = %x", Logical);
++
++ gckOS_GetProcessID(&pid);
++
++ status = gcvSTATUS_INVALID_ADDRESS;
++
++ gcmkVERIFY_OK(gckOS_AcquireMutex(Kernel->os, Kernel->virtualBufferLock, gcvINFINITE));
++
++ /* Walk all command buffer. */
++ for (buffer = Kernel->virtualBufferHead; buffer != gcvNULL; buffer = buffer->next)
++ {
++ if (buffer->userLogical)
++ {
++ start = buffer->userLogical;
++ }
++ else
++ {
++ start = buffer->kernelLogical;
++ }
++
++ if (Logical >= start
++ && (Logical < (start + buffer->pageCount * 4096))
++ && pid == buffer->pid
++ )
++ {
++ * Address = buffer->gpuAddress + (Logical - start);
++ status = gcvSTATUS_OK;
++ break;
++ }
++ }
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, Kernel->virtualBufferLock));
++
++ gcmkFOOTER_NO();
++ return status;
++}
++
++gceSTATUS
++gckKERNEL_QueryGPUAddress(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 GpuAddress,
++ OUT gckVIRTUAL_COMMAND_BUFFER_PTR * Buffer
++ )
++{
++ gckVIRTUAL_COMMAND_BUFFER_PTR buffer;
++ gctUINT32 start;
++ gceSTATUS status = gcvSTATUS_NOT_SUPPORTED;
++
++ gcmkVERIFY_OK(gckOS_AcquireMutex(Kernel->os, Kernel->virtualBufferLock, gcvINFINITE));
++
++ /* Walk all command buffers. */
++ for (buffer = Kernel->virtualBufferHead; buffer != gcvNULL; buffer = buffer->next)
++ {
++ start = (gctUINT32)buffer->gpuAddress;
++
++ if (GpuAddress >= start && GpuAddress < (start + buffer->pageCount * 4096))
++ {
++ /* Find a range matched. */
++ *Buffer = buffer;
++ status = gcvSTATUS_OK;
++ break;
++ }
++ }
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, Kernel->virtualBufferLock));
++
++ return status;
++}
++#endif
++
++#if gcdLINK_QUEUE_SIZE
++static void
++gckLINKQUEUE_Dequeue(
++ IN gckLINKQUEUE LinkQueue
++ )
++{
++ gcmkASSERT(LinkQueue->count == gcdLINK_QUEUE_SIZE);
++
++ LinkQueue->count--;
++ LinkQueue->front = (LinkQueue->front + 1) % gcdLINK_QUEUE_SIZE;
++}
++
++void
++gckLINKQUEUE_Enqueue(
++ IN gckLINKQUEUE LinkQueue,
++ IN gctUINT32 start,
++ IN gctUINT32 end
++ )
++{
++ if (LinkQueue->count == gcdLINK_QUEUE_SIZE)
++ {
++ gckLINKQUEUE_Dequeue(LinkQueue);
++ }
++
++ gcmkASSERT(LinkQueue->count < gcdLINK_QUEUE_SIZE);
++
++ LinkQueue->count++;
++
++ LinkQueue->data[LinkQueue->rear].start = start;
++ LinkQueue->data[LinkQueue->rear].end = end;
++
++ gcmkVERIFY_OK(
++ gckOS_GetProcessID(&LinkQueue->data[LinkQueue->rear].pid));
++
++ LinkQueue->rear = (LinkQueue->rear + 1) % gcdLINK_QUEUE_SIZE;
++}
++
++void
++gckLINKQUEUE_GetData(
++ IN gckLINKQUEUE LinkQueue,
++ IN gctUINT32 Index,
++ OUT gckLINKDATA * Data
++ )
++{
++ gcmkASSERT(Index >= 0 && Index < gcdLINK_QUEUE_SIZE);
++
++ *Data = &LinkQueue->data[(Index + LinkQueue->front) % gcdLINK_QUEUE_SIZE];
++}
++#endif
++
++/******************************************************************************\
++*************************** Pointer - ID translation ***************************
++\******************************************************************************/
++#define gcdID_TABLE_LENGTH 1024
++typedef struct _gcsINTEGERDB * gckINTEGERDB;
++typedef struct _gcsINTEGERDB
++{
++ gckOS os;
++ gctPOINTER* table;
++ gctPOINTER mutex;
++ gctUINT32 tableLen;
++ gctUINT32 currentID;
++ gctUINT32 unused;
++}
++gcsINTEGERDB;
++
++gceSTATUS
++gckKERNEL_CreateIntegerDatabase(
++ IN gckKERNEL Kernel,
++ OUT gctPOINTER * Database
++ )
++{
++ gceSTATUS status;
++ gckINTEGERDB database = gcvNULL;
++
++ gcmkHEADER_ARG("Kernel=0x%08X Datbase=0x%08X", Kernel, Database);
++
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(Database != gcvNULL);
++
++ /* Allocate a database. */
++ gcmkONERROR(gckOS_Allocate(
++ Kernel->os, gcmSIZEOF(gcsINTEGERDB), (gctPOINTER *)&database));
++
++ gckOS_ZeroMemory(database, gcmSIZEOF(gcsINTEGERDB));
++
++ /* Allocate a pointer table. */
++ gcmkONERROR(gckOS_Allocate(
++ Kernel->os, gcmSIZEOF(gctPOINTER) * gcdID_TABLE_LENGTH, (gctPOINTER *)&database->table));
++
++ gckOS_ZeroMemory(database->table, gcmSIZEOF(gctPOINTER) * gcdID_TABLE_LENGTH);
++
++ /* Allocate a database mutex. */
++ gcmkONERROR(gckOS_CreateMutex(Kernel->os, &database->mutex));
++
++ /* Initialize. */
++ database->currentID = 0;
++ database->unused = gcdID_TABLE_LENGTH;
++ database->os = Kernel->os;
++ database->tableLen = gcdID_TABLE_LENGTH;
++
++ *Database = database;
++
++ gcmkFOOTER_ARG("*Database=0x%08X", *Database);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Rollback. */
++ if (database)
++ {
++ if (database->table)
++ {
++ gcmkOS_SAFE_FREE(Kernel->os, database->table);
++ }
++
++ gcmkOS_SAFE_FREE(Kernel->os, database);
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckKERNEL_DestroyIntegerDatabase(
++ IN gckKERNEL Kernel,
++ IN gctPOINTER Database
++ )
++{
++ gckINTEGERDB database = Database;
++
++ gcmkHEADER_ARG("Kernel=0x%08X Datbase=0x%08X", Kernel, Database);
++
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(Database != gcvNULL);
++
++ /* Destroy pointer table. */
++ gcmkOS_SAFE_FREE(Kernel->os, database->table);
++
++ /* Destroy database mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Kernel->os, database->mutex));
++
++ /* Destroy database. */
++ gcmkOS_SAFE_FREE(Kernel->os, database);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckKERNEL_AllocateIntegerId(
++ IN gctPOINTER Database,
++ IN gctPOINTER Pointer,
++ OUT gctUINT32 * Id
++ )
++{
++ gceSTATUS status;
++ gckINTEGERDB database = Database;
++ gctUINT32 i, unused, currentID, tableLen;
++ gctPOINTER * table;
++ gckOS os = database->os;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Database=0x%08X Pointer=0x%08X", Database, Pointer);
++
++ gcmkVERIFY_ARGUMENT(Id != gcvNULL);
++
++ gcmkVERIFY_OK(gckOS_AcquireMutex(os, database->mutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ if (database->unused < 1)
++ {
++ /* Extend table. */
++ gcmkONERROR(
++ gckOS_Allocate(os,
++ gcmSIZEOF(gctPOINTER) * (database->tableLen + gcdID_TABLE_LENGTH),
++ (gctPOINTER *)&table));
++
++ gckOS_ZeroMemory(table + database->tableLen,
++ gcmSIZEOF(gctPOINTER) * gcdID_TABLE_LENGTH);
++
++ /* Copy data from old table. */
++ gckOS_MemCopy(table,
++ database->table,
++ database->tableLen * gcmSIZEOF(gctPOINTER));
++
++ gcmkOS_SAFE_FREE(os, database->table);
++
++ /* Update databse with new allocated table. */
++ database->table = table;
++ database->currentID = database->tableLen;
++ database->tableLen += gcdID_TABLE_LENGTH;
++ database->unused += gcdID_TABLE_LENGTH;
++ }
++
++ table = database->table;
++ currentID = database->currentID;
++ tableLen = database->tableLen;
++ unused = database->unused;
++
++ /* Connect id with pointer. */
++ table[currentID] = Pointer;
++
++ *Id = currentID + 1;
++
++ /* Update the currentID. */
++ if (--unused > 0)
++ {
++ for (i = 0; i < tableLen; i++)
++ {
++ if (++currentID >= tableLen)
++ {
++ /* Wrap to the begin. */
++ currentID = 0;
++ }
++
++ if (table[currentID] == gcvNULL)
++ {
++ break;
++ }
++ }
++ }
++
++ database->table = table;
++ database->currentID = currentID;
++ database->tableLen = tableLen;
++ database->unused = unused;
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(os, database->mutex));
++ acquired = gcvFALSE;
++
++ gcmkFOOTER_ARG("*Id=%d", *Id);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(os, database->mutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckKERNEL_FreeIntegerId(
++ IN gctPOINTER Database,
++ IN gctUINT32 Id
++ )
++{
++ gceSTATUS status;
++ gckINTEGERDB database = Database;
++ gckOS os = database->os;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Database=0x%08X Id=%d", Database, Id);
++
++ gcmkVERIFY_OK(gckOS_AcquireMutex(os, database->mutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ if (!(Id > 0 && Id <= database->tableLen))
++ {
++ gcmkONERROR(gcvSTATUS_NOT_FOUND);
++ }
++
++ Id -= 1;
++
++ database->table[Id] = gcvNULL;
++
++ if (database->unused++ == 0)
++ {
++ database->currentID = Id;
++ }
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(os, database->mutex));
++ acquired = gcvFALSE;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(os, database->mutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckKERNEL_QueryIntegerId(
++ IN gctPOINTER Database,
++ IN gctUINT32 Id,
++ OUT gctPOINTER * Pointer
++ )
++{
++ gceSTATUS status;
++ gckINTEGERDB database = Database;
++ gctPOINTER pointer;
++ gckOS os = database->os;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Database=0x%08X Id=%d", Database, Id);
++ gcmkVERIFY_ARGUMENT(Pointer != gcvNULL);
++
++ gcmkVERIFY_OK(gckOS_AcquireMutex(os, database->mutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ if (!(Id > 0 && Id <= database->tableLen))
++ {
++ gcmkONERROR(gcvSTATUS_NOT_FOUND);
++ }
++
++ Id -= 1;
++
++ pointer = database->table[Id];
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(os, database->mutex));
++ acquired = gcvFALSE;
++
++ if (pointer)
++ {
++ *Pointer = pointer;
++ }
++ else
++ {
++ gcmkONERROR(gcvSTATUS_NOT_FOUND);
++ }
++
++ gcmkFOOTER_ARG("*Pointer=0x%08X", *Pointer);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(os, database->mutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++
++gctUINT32
++gckKERNEL_AllocateNameFromPointer(
++ IN gckKERNEL Kernel,
++ IN gctPOINTER Pointer
++ )
++{
++ gceSTATUS status;
++ gctUINT32 name;
++ gctPOINTER database = Kernel->db->pointerDatabase;
++
++ gcmkHEADER_ARG("Kernel=0x%X Pointer=0x%X", Kernel, Pointer);
++
++ gcmkONERROR(
++ gckKERNEL_AllocateIntegerId(database, Pointer, &name));
++
++ gcmkFOOTER_ARG("name=%d", name);
++ return name;
++
++OnError:
++ gcmkFOOTER();
++ return 0;
++}
++
++gctPOINTER
++gckKERNEL_QueryPointerFromName(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 Name
++ )
++{
++ gceSTATUS status;
++ gctPOINTER pointer = gcvNULL;
++ gctPOINTER database = Kernel->db->pointerDatabase;
++
++ gcmkHEADER_ARG("Kernel=0x%X Name=%d", Kernel, Name);
++
++ /* Lookup in database to get pointer. */
++ gcmkONERROR(gckKERNEL_QueryIntegerId(database, Name, &pointer));
++
++ gcmkFOOTER_ARG("pointer=0x%X", pointer);
++ return pointer;
++
++OnError:
++ gcmkFOOTER();
++ return gcvNULL;
++}
++
++gceSTATUS
++gckKERNEL_DeleteName(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 Name
++ )
++{
++ gctPOINTER database = Kernel->db->pointerDatabase;
++
++ gcmkHEADER_ARG("Kernel=0x%X Name=0x%X", Kernel, Name);
++
++ /* Free name if exists. */
++ gcmkVERIFY_OK(gckKERNEL_FreeIntegerId(database, Name));
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++/*******************************************************************************
++***** Test Code ****************************************************************
++*******************************************************************************/
++
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_command.c linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_command.c
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_command.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_command.c 2015-07-27 23:13:06.190893891 +0200
+@@ -0,0 +1,3042 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_precomp.h"
++#include "gc_hal_kernel_context.h"
++
++#ifdef __QNXNTO__
++#include <sys/slog.h>
++#endif
++
++#define _GC_OBJ_ZONE gcvZONE_COMMAND
++
++/******************************************************************************\
++********************************* Support Code *********************************
++\******************************************************************************/
++
++/*******************************************************************************
++**
++** _NewQueue
++**
++** Allocate a new command queue.
++**
++** INPUT:
++**
++** gckCOMMAND Command
++** Pointer to an gckCOMMAND object.
++**
++** OUTPUT:
++**
++** gckCOMMAND Command
++** gckCOMMAND object has been updated with a new command queue.
++*/
++static gceSTATUS
++_NewQueue(
++ IN OUT gckCOMMAND Command
++ )
++{
++ gceSTATUS status;
++ gctINT currentIndex, newIndex;
++
++ gcmkHEADER_ARG("Command=0x%x", Command);
++
++ /* Switch to the next command buffer. */
++ currentIndex = Command->index;
++ newIndex = (currentIndex + 1) % gcdCOMMAND_QUEUES;
++
++ /* Wait for availability. */
++#if gcdDUMP_COMMAND
++ gcmkPRINT("@[kernel.waitsignal]");
++#endif
++
++ gcmkONERROR(gckOS_WaitSignal(
++ Command->os,
++ Command->queues[newIndex].signal,
++ gcvINFINITE
++ ));
++
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++ if (newIndex < currentIndex)
++ {
++ Command->wrapCount += 1;
++
++ gcmkTRACE_ZONE_N(
++ gcvLEVEL_INFO, gcvZONE_COMMAND,
++ 2 * 4,
++ "%s(%d): queue array wrapped around.\n",
++ __FUNCTION__, __LINE__
++ );
++ }
++
++ gcmkTRACE_ZONE_N(
++ gcvLEVEL_INFO, gcvZONE_COMMAND,
++ 3 * 4,
++ "%s(%d): total queue wrap arounds %d.\n",
++ __FUNCTION__, __LINE__, Command->wrapCount
++ );
++
++ gcmkTRACE_ZONE_N(
++ gcvLEVEL_INFO, gcvZONE_COMMAND,
++ 3 * 4,
++ "%s(%d): switched to queue %d.\n",
++ __FUNCTION__, __LINE__, newIndex
++ );
++#endif
++
++ /* Update gckCOMMAND object with new command queue. */
++ Command->index = newIndex;
++ Command->newQueue = gcvTRUE;
++ Command->logical = Command->queues[newIndex].logical;
++ Command->offset = 0;
++
++ gcmkONERROR(
++ gckOS_GetPhysicalAddress(
++ Command->os,
++ Command->logical,
++ (gctUINT32 *) &Command->physical
++ ));
++
++ if (currentIndex != -1)
++ {
++ /* Mark the command queue as available. */
++ gcmkONERROR(gckEVENT_Signal(
++ Command->kernel->eventObj,
++ Command->queues[currentIndex].signal,
++ gcvKERNEL_COMMAND
++ ));
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("Command->index=%d", Command->index);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++static gceSTATUS
++_IncrementCommitAtom(
++ IN gckCOMMAND Command,
++ IN gctBOOL Increment
++ )
++{
++ gceSTATUS status;
++ gckHARDWARE hardware;
++ gctINT32 atomValue;
++ gctBOOL powerAcquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Command=0x%x", Command);
++
++ /* Extract the gckHARDWARE and gckEVENT objects. */
++ hardware = Command->kernel->hardware;
++ gcmkVERIFY_OBJECT(hardware, gcvOBJ_HARDWARE);
++
++ /* Grab the power mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(
++ Command->os, hardware->powerMutex, gcvINFINITE
++ ));
++ powerAcquired = gcvTRUE;
++
++ /* Increment the commit atom. */
++ if (Increment)
++ {
++ gcmkONERROR(gckOS_AtomIncrement(
++ Command->os, Command->atomCommit, &atomValue
++ ));
++ }
++ else
++ {
++ gcmkONERROR(gckOS_AtomDecrement(
++ Command->os, Command->atomCommit, &atomValue
++ ));
++ }
++
++ /* Release the power mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(
++ Command->os, hardware->powerMutex
++ ));
++ powerAcquired = gcvFALSE;
++
++ /* Success. */
++ gcmkFOOTER();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (powerAcquired)
++ {
++ /* Release the power mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(
++ Command->os, hardware->powerMutex
++ ));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++#if gcdSECURE_USER
++static gceSTATUS
++_ProcessHints(
++ IN gckCOMMAND Command,
++ IN gctUINT32 ProcessID,
++ IN gcoCMDBUF CommandBuffer
++ )
++{
++ gceSTATUS status = gcvSTATUS_OK;
++ gckKERNEL kernel;
++ gctBOOL needCopy = gcvFALSE;
++ gcskSECURE_CACHE_PTR cache;
++ gctUINT8_PTR commandBufferLogical;
++ gctUINT8_PTR hintedData;
++ gctUINT32_PTR hintArray;
++ gctUINT i, hintCount;
++
++ gcmkHEADER_ARG(
++ "Command=0x%08X ProcessID=%d CommandBuffer=0x%08X",
++ Command, ProcessID, CommandBuffer
++ );
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ /* Reset state array pointer. */
++ hintArray = gcvNULL;
++
++ /* Get the kernel object. */
++ kernel = Command->kernel;
++
++ /* Get the cache form the database. */
++ gcmkONERROR(gckKERNEL_GetProcessDBCache(kernel, ProcessID, &cache));
++
++ /* Determine the start of the command buffer. */
++ commandBufferLogical
++ = (gctUINT8_PTR) CommandBuffer->logical
++ + CommandBuffer->startOffset;
++
++ /* Determine the number of records in the state array. */
++ hintCount = CommandBuffer->hintArrayTail - CommandBuffer->hintArray;
++
++ /* Check wehther we need to copy the structures or not. */
++ gcmkONERROR(gckOS_QueryNeedCopy(Command->os, ProcessID, &needCopy));
++
++ /* Get access to the state array. */
++ if (needCopy)
++ {
++ gctUINT copySize;
++
++ if (Command->hintArrayAllocated &&
++ (Command->hintArraySize < CommandBuffer->hintArraySize))
++ {
++ gcmkONERROR(gcmkOS_SAFE_FREE(Command->os, gcmUINT64_TO_PTR(Command->hintArray)));
++ Command->hintArraySize = gcvFALSE;
++ }
++
++ if (!Command->hintArrayAllocated)
++ {
++ gctPOINTER pointer = gcvNULL;
++
++ gcmkONERROR(gckOS_Allocate(
++ Command->os,
++ CommandBuffer->hintArraySize,
++ &pointer
++ ));
++
++ Command->hintArray = gcmPTR_TO_UINT64(pointer);
++ Command->hintArrayAllocated = gcvTRUE;
++ Command->hintArraySize = CommandBuffer->hintArraySize;
++ }
++
++ hintArray = gcmUINT64_TO_PTR(Command->hintArray);
++ copySize = hintCount * gcmSIZEOF(gctUINT32);
++
++ gcmkONERROR(gckOS_CopyFromUserData(
++ Command->os,
++ hintArray,
++ gcmUINT64_TO_PTR(CommandBuffer->hintArray),
++ copySize
++ ));
++ }
++ else
++ {
++ gctPOINTER pointer = gcvNULL;
++
++ gcmkONERROR(gckOS_MapUserPointer(
++ Command->os,
++ gcmUINT64_TO_PTR(CommandBuffer->hintArray),
++ CommandBuffer->hintArraySize,
++ &pointer
++ ));
++
++ hintArray = pointer;
++ }
++
++ /* Scan through the buffer. */
++ for (i = 0; i < hintCount; i += 1)
++ {
++ /* Determine the location of the hinted data. */
++ hintedData = commandBufferLogical + hintArray[i];
++
++ /* Map handle into physical address. */
++ gcmkONERROR(gckKERNEL_MapLogicalToPhysical(
++ kernel, cache, (gctPOINTER) hintedData
++ ));
++ }
++
++OnError:
++ /* Get access to the state array. */
++ if (!needCopy && (hintArray != gcvNULL))
++ {
++ gcmkVERIFY_OK(gckOS_UnmapUserPointer(
++ Command->os,
++ gcmUINT64_TO_PTR(CommandBuffer->hintArray),
++ CommandBuffer->hintArraySize,
++ hintArray
++ ));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++#endif
++
++static gceSTATUS
++_FlushMMU(
++ IN gckCOMMAND Command
++ )
++{
++ gceSTATUS status;
++ gctUINT32 oldValue;
++ gckHARDWARE hardware = Command->kernel->hardware;
++
++ gcmkONERROR(gckOS_AtomicExchange(Command->os,
++ hardware->pageTableDirty,
++ 0,
++ &oldValue));
++
++ if (oldValue)
++ {
++ /* Page Table is upated, flush mmu before commit. */
++ gcmkONERROR(gckHARDWARE_FlushMMU(hardware));
++ }
++
++ return gcvSTATUS_OK;
++OnError:
++ return status;
++}
++
++#if gcdVIRTUAL_COMMAND_BUFFER
++static void
++_DumpBuffer(
++ IN gctPOINTER Buffer,
++ IN gctUINT32 GpuAddress,
++ IN gctSIZE_T Size
++ )
++{
++ gctINT i, line, left;
++ gctUINT32_PTR data = Buffer;
++
++ line = Size / 32;
++ left = Size % 32;
++
++
++ for (i = 0; i < line; i++)
++ {
++ gcmkPRINT("%X : %08X %08X %08X %08X %08X %08X %08X %08X ",
++ GpuAddress, data[0], data[1], data[2], data[3], data[4], data[5], data[6], data[7]);
++ data += 8;
++ GpuAddress += 8 * 4;
++ }
++
++ switch(left)
++ {
++ case 28:
++ gcmkPRINT("%X : %08X %08X %08X %08X %08X %08X %08X ",
++ GpuAddress, data[0], data[1], data[2], data[3], data[4], data[5], data[6]);
++ break;
++ case 24:
++ gcmkPRINT("%X : %08X %08X %08X %08X %08X %08X ",
++ GpuAddress, data[0], data[1], data[2], data[3], data[4], data[5]);
++ break;
++ case 20:
++ gcmkPRINT("%X : %08X %08X %08X %08X %08X ",
++ GpuAddress, data[0], data[1], data[2], data[3], data[4]);
++ break;
++ case 16:
++ gcmkPRINT("%X : %08X %08X %08X %08X ",
++ GpuAddress, data[0], data[1], data[2], data[3]);
++ break;
++ case 12:
++ gcmkPRINT("%X : %08X %08X %08X ",
++ GpuAddress, data[0], data[1], data[2]);
++ break;
++ case 8:
++ gcmkPRINT("%X : %08X %08X ",
++ GpuAddress, data[0], data[1]);
++ break;
++ case 4:
++ gcmkPRINT("%X : %08X ",
++ GpuAddress, data[0]);
++ break;
++ default:
++ break;
++ }
++}
++
++static void
++_DumpKernelCommandBuffer(
++ IN gckCOMMAND Command
++)
++{
++ gctINT i;
++ gctUINT32 physical;
++ gctPOINTER entry;
++
++ for (i = 0; i < gcdCOMMAND_QUEUES; i++)
++ {
++ entry = Command->queues[i].logical;
++
++ gckOS_GetPhysicalAddress(Command->os, entry, &physical);
++
++ gcmkPRINT("Kernel command buffer %d\n", i);
++
++ _DumpBuffer(entry, physical, Command->pageSize);
++ }
++}
++#endif
++
++/******************************************************************************\
++****************************** gckCOMMAND API Code ******************************
++\******************************************************************************/
++
++/*******************************************************************************
++**
++** gckCOMMAND_Construct
++**
++** Construct a new gckCOMMAND object.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** OUTPUT:
++**
++** gckCOMMAND * Command
++** Pointer to a variable that will hold the pointer to the gckCOMMAND
++** object.
++*/
++gceSTATUS
++gckCOMMAND_Construct(
++ IN gckKERNEL Kernel,
++ OUT gckCOMMAND * Command
++ )
++{
++ gckOS os;
++ gckCOMMAND command = gcvNULL;
++ gceSTATUS status;
++ gctINT i;
++ gctPOINTER pointer = gcvNULL;
++
++ gcmkHEADER_ARG("Kernel=0x%x", Kernel);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(Command != gcvNULL);
++
++ /* Extract the gckOS object. */
++ os = Kernel->os;
++
++ /* Allocate the gckCOMMAND structure. */
++ gcmkONERROR(gckOS_Allocate(os, gcmSIZEOF(struct _gckCOMMAND), &pointer));
++ command = pointer;
++
++ /* Reset the entire object. */
++ gcmkONERROR(gckOS_ZeroMemory(command, gcmSIZEOF(struct _gckCOMMAND)));
++
++ /* Initialize the gckCOMMAND object.*/
++ command->object.type = gcvOBJ_COMMAND;
++ command->kernel = Kernel;
++ command->os = os;
++
++ /* Get the command buffer requirements. */
++ gcmkONERROR(gckHARDWARE_QueryCommandBuffer(
++ Kernel->hardware,
++ &command->alignment,
++ &command->reservedHead,
++ &command->reservedTail
++ ));
++
++ /* Create the command queue mutex. */
++ gcmkONERROR(gckOS_CreateMutex(os, &command->mutexQueue));
++
++ /* Create the context switching mutex. */
++ gcmkONERROR(gckOS_CreateMutex(os, &command->mutexContext));
++
++#if VIVANTE_PROFILER_CONTEXT
++ /* Create the context switching mutex. */
++ gcmkONERROR(gckOS_CreateMutex(os, &command->mutexContextSeq));
++#endif
++
++ /* Create the power management semaphore. */
++ gcmkONERROR(gckOS_CreateSemaphore(os, &command->powerSemaphore));
++
++ /* Create the commit atom. */
++ gcmkONERROR(gckOS_AtomConstruct(os, &command->atomCommit));
++
++ /* Get the page size from teh OS. */
++ gcmkONERROR(gckOS_GetPageSize(os, &command->pageSize));
++
++ /* Get process ID. */
++ gcmkONERROR(gckOS_GetProcessID(&command->kernelProcessID));
++
++ /* Set hardware to pipe 0. */
++ command->pipeSelect = gcvPIPE_INVALID;
++
++ /* Pre-allocate the command queues. */
++ for (i = 0; i < gcdCOMMAND_QUEUES; ++i)
++ {
++ gcmkONERROR(gckOS_AllocateNonPagedMemory(
++ os,
++ gcvFALSE,
++ &command->pageSize,
++ &command->queues[i].physical,
++ &command->queues[i].logical
++ ));
++
++ gcmkONERROR(gckOS_CreateSignal(
++ os, gcvFALSE, &command->queues[i].signal
++ ));
++
++ gcmkONERROR(gckOS_Signal(
++ os, command->queues[i].signal, gcvTRUE
++ ));
++ }
++
++ /* No command queue in use yet. */
++ command->index = -1;
++ command->logical = gcvNULL;
++ command->newQueue = gcvFALSE;
++
++ /* Command is not yet running. */
++ command->running = gcvFALSE;
++
++ /* Command queue is idle. */
++ command->idle = gcvTRUE;
++
++ /* Commit stamp is zero. */
++ command->commitStamp = 0;
++
++ /* END event signal not created. */
++ command->endEventSignal = gcvNULL;
++
++ /* Return pointer to the gckCOMMAND object. */
++ *Command = command;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Command=0x%x", *Command);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Roll back. */
++ if (command != gcvNULL)
++ {
++ if (command->atomCommit != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_AtomDestroy(os, command->atomCommit));
++ }
++
++ if (command->powerSemaphore != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_DestroySemaphore(os, command->powerSemaphore));
++ }
++
++ if (command->mutexContext != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_DeleteMutex(os, command->mutexContext));
++ }
++
++#if VIVANTE_PROFILER_CONTEXT
++ if (command->mutexContextSeq != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_DeleteMutex(os, command->mutexContextSeq));
++ }
++#endif
++
++ if (command->mutexQueue != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_DeleteMutex(os, command->mutexQueue));
++ }
++
++ for (i = 0; i < gcdCOMMAND_QUEUES; ++i)
++ {
++ if (command->queues[i].signal != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_DestroySignal(
++ os, command->queues[i].signal
++ ));
++ }
++
++ if (command->queues[i].logical != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_FreeNonPagedMemory(
++ os,
++ command->pageSize,
++ command->queues[i].physical,
++ command->queues[i].logical
++ ));
++ }
++ }
++
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(os, command));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckCOMMAND_Destroy
++**
++** Destroy an gckCOMMAND object.
++**
++** INPUT:
++**
++** gckCOMMAND Command
++** Pointer to an gckCOMMAND object to destroy.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckCOMMAND_Destroy(
++ IN gckCOMMAND Command
++ )
++{
++ gctINT i;
++
++ gcmkHEADER_ARG("Command=0x%x", Command);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ /* Stop the command queue. */
++ gcmkVERIFY_OK(gckCOMMAND_Stop(Command, gcvFALSE));
++
++ for (i = 0; i < gcdCOMMAND_QUEUES; ++i)
++ {
++ gcmkASSERT(Command->queues[i].signal != gcvNULL);
++ gcmkVERIFY_OK(gckOS_DestroySignal(
++ Command->os, Command->queues[i].signal
++ ));
++
++ gcmkASSERT(Command->queues[i].logical != gcvNULL);
++ gcmkVERIFY_OK(gckOS_FreeNonPagedMemory(
++ Command->os,
++ Command->pageSize,
++ Command->queues[i].physical,
++ Command->queues[i].logical
++ ));
++ }
++
++ /* END event signal. */
++ if (Command->endEventSignal != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_DestroySignal(
++ Command->os, Command->endEventSignal
++ ));
++ }
++
++ /* Delete the context switching mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Command->os, Command->mutexContext));
++
++#if VIVANTE_PROFILER_CONTEXT
++ if (Command->mutexContextSeq != gcvNULL)
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Command->os, Command->mutexContextSeq));
++#endif
++
++ /* Delete the command queue mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Command->os, Command->mutexQueue));
++
++ /* Destroy the power management semaphore. */
++ gcmkVERIFY_OK(gckOS_DestroySemaphore(Command->os, Command->powerSemaphore));
++
++ /* Destroy the commit atom. */
++ gcmkVERIFY_OK(gckOS_AtomDestroy(Command->os, Command->atomCommit));
++
++#if gcdSECURE_USER
++ /* Free state array. */
++ if (Command->hintArrayAllocated)
++ {
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Command->os, gcmUINT64_TO_PTR(Command->hintArray)));
++ Command->hintArrayAllocated = gcvFALSE;
++ }
++#endif
++
++ /* Mark object as unknown. */
++ Command->object.type = gcvOBJ_UNKNOWN;
++
++ /* Free the gckCOMMAND object. */
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Command->os, Command));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckCOMMAND_EnterCommit
++**
++** Acquire command queue synchronization objects.
++**
++** INPUT:
++**
++** gckCOMMAND Command
++** Pointer to an gckCOMMAND object to destroy.
++**
++** gctBOOL FromPower
++** Determines whether the call originates from inside the power
++** management or not.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckCOMMAND_EnterCommit(
++ IN gckCOMMAND Command,
++ IN gctBOOL FromPower
++ )
++{
++ gceSTATUS status;
++ gckHARDWARE hardware;
++ gctBOOL atomIncremented = gcvFALSE;
++ gctBOOL semaAcquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Command=0x%x", Command);
++
++ /* Extract the gckHARDWARE and gckEVENT objects. */
++ hardware = Command->kernel->hardware;
++ gcmkVERIFY_OBJECT(hardware, gcvOBJ_HARDWARE);
++
++ if (!FromPower)
++ {
++ /* Increment COMMIT atom to let power management know that a commit is
++ ** in progress. */
++ gcmkONERROR(_IncrementCommitAtom(Command, gcvTRUE));
++ atomIncremented = gcvTRUE;
++
++ /* Notify the system the GPU has a commit. */
++ gcmkONERROR(gckOS_Broadcast(Command->os,
++ hardware,
++ gcvBROADCAST_GPU_COMMIT));
++
++ /* Acquire the power management semaphore. */
++ gcmkONERROR(gckOS_AcquireSemaphore(Command->os,
++ Command->powerSemaphore));
++ semaAcquired = gcvTRUE;
++ }
++
++ /* Grab the conmmand queue mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(Command->os,
++ Command->mutexQueue,
++ gcvINFINITE));
++
++ /* Success. */
++ gcmkFOOTER();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (semaAcquired)
++ {
++ /* Release the power management semaphore. */
++ gcmkVERIFY_OK(gckOS_ReleaseSemaphore(
++ Command->os, Command->powerSemaphore
++ ));
++ }
++
++ if (atomIncremented)
++ {
++ /* Decrement the commit atom. */
++ gcmkVERIFY_OK(_IncrementCommitAtom(
++ Command, gcvFALSE
++ ));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckCOMMAND_ExitCommit
++**
++** Release command queue synchronization objects.
++**
++** INPUT:
++**
++** gckCOMMAND Command
++** Pointer to an gckCOMMAND object to destroy.
++**
++** gctBOOL FromPower
++** Determines whether the call originates from inside the power
++** management or not.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckCOMMAND_ExitCommit(
++ IN gckCOMMAND Command,
++ IN gctBOOL FromPower
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Command=0x%x", Command);
++
++ /* Release the power mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Command->os, Command->mutexQueue));
++
++ if (!FromPower)
++ {
++ /* Release the power management semaphore. */
++ gcmkONERROR(gckOS_ReleaseSemaphore(Command->os,
++ Command->powerSemaphore));
++
++ /* Decrement the commit atom. */
++ gcmkONERROR(_IncrementCommitAtom(Command, gcvFALSE));
++ }
++
++ /* Success. */
++ gcmkFOOTER();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckCOMMAND_Start
++**
++** Start up the command queue.
++**
++** INPUT:
++**
++** gckCOMMAND Command
++** Pointer to an gckCOMMAND object to start.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckCOMMAND_Start(
++ IN gckCOMMAND Command
++ )
++{
++ gceSTATUS status;
++ gckHARDWARE hardware;
++ gctUINT32 waitOffset;
++ gctSIZE_T waitLinkBytes;
++
++ gcmkHEADER_ARG("Command=0x%x", Command);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ if (Command->running)
++ {
++ /* Command queue already running. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++
++ /* Extract the gckHARDWARE object. */
++ hardware = Command->kernel->hardware;
++ gcmkVERIFY_OBJECT(hardware, gcvOBJ_HARDWARE);
++
++ if (Command->logical == gcvNULL)
++ {
++ /* Start at beginning of a new queue. */
++ gcmkONERROR(_NewQueue(Command));
++ }
++
++ /* Start at beginning of page. */
++ Command->offset = 0;
++
++ /* Set abvailable number of bytes for WAIT/LINK command sequence. */
++ waitLinkBytes = Command->pageSize;
++
++ /* Append WAIT/LINK. */
++ gcmkONERROR(gckHARDWARE_WaitLink(
++ hardware,
++ Command->logical,
++ 0,
++ &waitLinkBytes,
++ &waitOffset,
++ &Command->waitSize
++ ));
++
++ Command->waitLogical = (gctUINT8_PTR) Command->logical + waitOffset;
++ Command->waitPhysical = (gctUINT8_PTR) Command->physical + waitOffset;
++
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ /* Flush the cache for the wait/link. */
++ gcmkONERROR(gckOS_CacheClean(
++ Command->os,
++ Command->kernelProcessID,
++ gcvNULL,
++ Command->physical,
++ Command->logical,
++ waitLinkBytes
++ ));
++#endif
++
++ /* Adjust offset. */
++ Command->offset = waitLinkBytes;
++ Command->newQueue = gcvFALSE;
++
++ /* Enable command processor. */
++#ifdef __QNXNTO__
++ gcmkONERROR(gckHARDWARE_Execute(
++ hardware,
++ Command->logical,
++ Command->physical,
++ gcvTRUE,
++ waitLinkBytes
++ ));
++#else
++ gcmkONERROR(gckHARDWARE_Execute(
++ hardware,
++ Command->logical,
++ waitLinkBytes
++ ));
++#endif
++
++ /* Command queue is running. */
++ Command->running = gcvTRUE;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckCOMMAND_Stop
++**
++** Stop the command queue.
++**
++** INPUT:
++**
++** gckCOMMAND Command
++** Pointer to an gckCOMMAND object to stop.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckCOMMAND_Stop(
++ IN gckCOMMAND Command,
++ IN gctBOOL FromRecovery
++ )
++{
++ gckHARDWARE hardware;
++ gceSTATUS status;
++ gctUINT32 idle;
++
++ gcmkHEADER_ARG("Command=0x%x", Command);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ if (!Command->running)
++ {
++ /* Command queue is not running. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++
++ /* Extract the gckHARDWARE object. */
++ hardware = Command->kernel->hardware;
++ gcmkVERIFY_OBJECT(hardware, gcvOBJ_HARDWARE);
++
++ if (gckHARDWARE_IsFeatureAvailable(hardware,
++ gcvFEATURE_END_EVENT) == gcvSTATUS_TRUE)
++ {
++ /* Allocate the signal. */
++ if (Command->endEventSignal == gcvNULL)
++ {
++ gcmkONERROR(gckOS_CreateSignal(Command->os,
++ gcvTRUE,
++ &Command->endEventSignal));
++ }
++
++ /* Append the END EVENT command to trigger the signal. */
++ gcmkONERROR(gckEVENT_Stop(Command->kernel->eventObj,
++ Command->kernelProcessID,
++ Command->waitPhysical,
++ Command->waitLogical,
++ Command->endEventSignal,
++ &Command->waitSize));
++ }
++ else
++ {
++ /* Replace last WAIT with END. */
++ gcmkONERROR(gckHARDWARE_End(
++ hardware, Command->waitLogical, &Command->waitSize
++ ));
++
++ /* Update queue tail pointer. */
++ gcmkONERROR(gckHARDWARE_UpdateQueueTail(Command->kernel->hardware,
++ Command->logical,
++ Command->offset));
++
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ /* Flush the cache for the END. */
++ gcmkONERROR(gckOS_CacheClean(
++ Command->os,
++ Command->kernelProcessID,
++ gcvNULL,
++ Command->waitPhysical,
++ Command->waitLogical,
++ Command->waitSize
++ ));
++#endif
++
++ /* Wait for idle. */
++ gcmkONERROR(gckHARDWARE_GetIdle(hardware, !FromRecovery, &idle));
++ }
++
++ /* Command queue is no longer running. */
++ Command->running = gcvFALSE;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckCOMMAND_Commit
++**
++** Commit a command buffer to the command queue.
++**
++** INPUT:
++**
++** gckCOMMAND Command
++** Pointer to a gckCOMMAND object.
++**
++** gckCONTEXT Context
++** Pointer to a gckCONTEXT object.
++**
++** gcoCMDBUF CommandBuffer
++** Pointer to a gcoCMDBUF object.
++**
++** gcsSTATE_DELTA_PTR StateDelta
++** Pointer to the state delta.
++**
++** gctUINT32 ProcessID
++** Current process ID.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckCOMMAND_Commit(
++ IN gckCOMMAND Command,
++ IN gckCONTEXT Context,
++ IN gcoCMDBUF CommandBuffer,
++ IN gcsSTATE_DELTA_PTR StateDelta,
++ IN gcsQUEUE_PTR EventQueue,
++ IN gctUINT32 ProcessID
++ )
++{
++ gceSTATUS status;
++ gctBOOL commitEntered = gcvFALSE;
++ gctBOOL contextAcquired = gcvFALSE;
++ gckHARDWARE hardware;
++ gctBOOL needCopy = gcvFALSE;
++ gcsQUEUE_PTR eventRecord = gcvNULL;
++ gcsQUEUE _eventRecord;
++ gcsQUEUE_PTR nextEventRecord;
++ gctBOOL commandBufferMapped = gcvFALSE;
++ gcoCMDBUF commandBufferObject = gcvNULL;
++
++#if !gcdNULL_DRIVER
++ gcsCONTEXT_PTR contextBuffer;
++ struct _gcoCMDBUF _commandBufferObject;
++ gctPHYS_ADDR commandBufferPhysical;
++ gctUINT8_PTR commandBufferLogical;
++ gctUINT8_PTR commandBufferLink;
++ gctUINT commandBufferSize;
++ gctSIZE_T nopBytes;
++ gctSIZE_T pipeBytes;
++ gctSIZE_T linkBytes;
++ gctSIZE_T bytes;
++ gctUINT32 offset;
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ gctPHYS_ADDR entryPhysical;
++#endif
++ gctPOINTER entryLogical;
++ gctSIZE_T entryBytes;
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ gctPHYS_ADDR exitPhysical;
++#endif
++ gctPOINTER exitLogical;
++ gctSIZE_T exitBytes;
++ gctPHYS_ADDR waitLinkPhysical;
++ gctPOINTER waitLinkLogical;
++ gctSIZE_T waitLinkBytes;
++ gctPHYS_ADDR waitPhysical;
++ gctPOINTER waitLogical;
++ gctUINT32 waitOffset;
++ gctSIZE_T waitSize;
++
++#if gcdDUMP_COMMAND
++ gctPOINTER contextDumpLogical = gcvNULL;
++ gctSIZE_T contextDumpBytes = 0;
++ gctPOINTER bufferDumpLogical = gcvNULL;
++ gctSIZE_T bufferDumpBytes = 0;
++# endif
++#endif
++
++#if VIVANTE_PROFILER_CONTEXT
++ gctBOOL sequenceAcquired = gcvFALSE;
++#endif
++
++ gctPOINTER pointer = gcvNULL;
++
++ gcmkHEADER_ARG(
++ "Command=0x%x CommandBuffer=0x%x ProcessID=%d",
++ Command, CommandBuffer, ProcessID
++ );
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ if (Command->kernel->core == gcvCORE_2D)
++ {
++ /* There is no context for 2D. */
++ Context = gcvNULL;
++ }
++
++ gcmkONERROR(_FlushMMU(Command));
++
++#if VIVANTE_PROFILER_CONTEXT
++ if((Command->kernel->hardware->gpuProfiler) && (Command->kernel->profileEnable))
++ {
++ /* Acquire the context sequnence mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(
++ Command->os, Command->mutexContextSeq, gcvINFINITE
++ ));
++ sequenceAcquired = gcvTRUE;
++ }
++#endif
++
++ /* Acquire the command queue. */
++ gcmkONERROR(gckCOMMAND_EnterCommit(Command, gcvFALSE));
++ commitEntered = gcvTRUE;
++
++ /* Acquire the context switching mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(
++ Command->os, Command->mutexContext, gcvINFINITE
++ ));
++ contextAcquired = gcvTRUE;
++
++ /* Extract the gckHARDWARE and gckEVENT objects. */
++ hardware = Command->kernel->hardware;
++
++ /* Check wehther we need to copy the structures or not. */
++ gcmkONERROR(gckOS_QueryNeedCopy(Command->os, ProcessID, &needCopy));
++
++#if gcdNULL_DRIVER
++ /* Context switch required? */
++ if ((Context != gcvNULL) && (Command->currContext != Context))
++ {
++ /* Yes, merge in the deltas. */
++ gckCONTEXT_Update(Context, ProcessID, StateDelta);
++
++ /* Update the current context. */
++ Command->currContext = Context;
++ }
++#else
++ if (needCopy)
++ {
++ commandBufferObject = &_commandBufferObject;
++
++ gcmkONERROR(gckOS_CopyFromUserData(
++ Command->os,
++ commandBufferObject,
++ CommandBuffer,
++ gcmSIZEOF(struct _gcoCMDBUF)
++ ));
++
++ gcmkVERIFY_OBJECT(commandBufferObject, gcvOBJ_COMMANDBUFFER);
++ }
++ else
++ {
++ gcmkONERROR(gckOS_MapUserPointer(
++ Command->os,
++ CommandBuffer,
++ gcmSIZEOF(struct _gcoCMDBUF),
++ &pointer
++ ));
++
++ commandBufferObject = pointer;
++
++ gcmkVERIFY_OBJECT(commandBufferObject, gcvOBJ_COMMANDBUFFER);
++ commandBufferMapped = gcvTRUE;
++ }
++
++ /* Query the size of NOP command. */
++ gcmkONERROR(gckHARDWARE_Nop(
++ hardware, gcvNULL, &nopBytes
++ ));
++
++ /* Query the size of pipe select command sequence. */
++ gcmkONERROR(gckHARDWARE_PipeSelect(
++ hardware, gcvNULL, gcvPIPE_3D, &pipeBytes
++ ));
++
++ /* Query the size of LINK command. */
++ gcmkONERROR(gckHARDWARE_Link(
++ hardware, gcvNULL, gcvNULL, 0, &linkBytes
++ ));
++
++ /* Compute the command buffer entry and the size. */
++ commandBufferLogical
++ = (gctUINT8_PTR) gcmUINT64_TO_PTR(commandBufferObject->logical)
++ + commandBufferObject->startOffset;
++
++ gcmkONERROR(gckOS_GetPhysicalAddress(
++ Command->os,
++ commandBufferLogical,
++ (gctUINT32_PTR)&commandBufferPhysical
++ ));
++
++ commandBufferSize
++ = commandBufferObject->offset
++ + Command->reservedTail
++ - commandBufferObject->startOffset;
++
++ /* Get the current offset. */
++ offset = Command->offset;
++
++ /* Compute number of bytes left in current kernel command queue. */
++ bytes = Command->pageSize - offset;
++
++ /* Query the size of WAIT/LINK command sequence. */
++ gcmkONERROR(gckHARDWARE_WaitLink(
++ hardware,
++ gcvNULL,
++ offset,
++ &waitLinkBytes,
++ gcvNULL,
++ gcvNULL
++ ));
++
++ /* Is there enough space in the current command queue? */
++ if (bytes < waitLinkBytes)
++ {
++ /* No, create a new one. */
++ gcmkONERROR(_NewQueue(Command));
++
++ /* Get the new current offset. */
++ offset = Command->offset;
++
++ /* Recompute the number of bytes in the new kernel command queue. */
++ bytes = Command->pageSize - offset;
++ gcmkASSERT(bytes >= waitLinkBytes);
++ }
++
++ /* Compute the location if WAIT/LINK command sequence. */
++ waitLinkPhysical = (gctUINT8_PTR) Command->physical + offset;
++ waitLinkLogical = (gctUINT8_PTR) Command->logical + offset;
++
++ /* Context switch required? */
++ if (Context == gcvNULL)
++ {
++ /* See if we have to switch pipes for the command buffer. */
++ if (commandBufferObject->entryPipe == Command->pipeSelect)
++ {
++ /* Skip pipe switching sequence. */
++ offset = pipeBytes;
++ }
++ else
++ {
++ /* The current hardware and the entry command buffer pipes
++ ** are different, switch to the correct pipe. */
++ gcmkONERROR(gckHARDWARE_PipeSelect(
++ Command->kernel->hardware,
++ commandBufferLogical,
++ commandBufferObject->entryPipe,
++ &pipeBytes
++ ));
++
++ /* Do not skip pipe switching sequence. */
++ offset = 0;
++ }
++
++ /* Compute the entry. */
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ entryPhysical = (gctUINT8_PTR) commandBufferPhysical + offset;
++#endif
++ entryLogical = commandBufferLogical + offset;
++ entryBytes = commandBufferSize - offset;
++ }
++ else if (Command->currContext != Context)
++ {
++ /* Temporary disable context length oprimization. */
++ Context->dirty = gcvTRUE;
++
++ /* Get the current context buffer. */
++ contextBuffer = Context->buffer;
++
++ /* Yes, merge in the deltas. */
++ gcmkONERROR(gckCONTEXT_Update(Context, ProcessID, StateDelta));
++
++ /* Determine context entry and exit points. */
++ if (0)
++ {
++ /* Reset 2D dirty flag. */
++ Context->dirty2D = gcvFALSE;
++
++ if (Context->dirty || commandBufferObject->using3D)
++ {
++ /***************************************************************
++ ** SWITCHING CONTEXT: 2D and 3D are used.
++ */
++
++ /* Reset 3D dirty flag. */
++ Context->dirty3D = gcvFALSE;
++
++ /* Compute the entry. */
++ if (Command->pipeSelect == gcvPIPE_2D)
++ {
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ entryPhysical = (gctUINT8_PTR) contextBuffer->physical + pipeBytes;
++#endif
++ entryLogical = (gctUINT8_PTR) contextBuffer->logical + pipeBytes;
++ entryBytes = Context->bufferSize - pipeBytes;
++ }
++ else
++ {
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ entryPhysical = (gctUINT8_PTR) contextBuffer->physical;
++#endif
++ entryLogical = (gctUINT8_PTR) contextBuffer->logical;
++ entryBytes = Context->bufferSize;
++ }
++
++ /* See if we have to switch pipes between the context
++ and command buffers. */
++ if (commandBufferObject->entryPipe == gcvPIPE_3D)
++ {
++ /* Skip pipe switching sequence. */
++ offset = pipeBytes;
++ }
++ else
++ {
++ /* The current hardware and the initial context pipes are
++ different, switch to the correct pipe. */
++ gcmkONERROR(gckHARDWARE_PipeSelect(
++ Command->kernel->hardware,
++ commandBufferLogical,
++ commandBufferObject->entryPipe,
++ &pipeBytes
++ ));
++
++ /* Do not skip pipe switching sequence. */
++ offset = 0;
++ }
++
++ /* Ensure the NOP between 2D and 3D is in place so that the
++ execution falls through from 2D to 3D. */
++ gcmkONERROR(gckHARDWARE_Nop(
++ hardware,
++ contextBuffer->link2D,
++ &nopBytes
++ ));
++
++ /* Generate a LINK from the context buffer to
++ the command buffer. */
++ gcmkONERROR(gckHARDWARE_Link(
++ hardware,
++ contextBuffer->link3D,
++ commandBufferLogical + offset,
++ commandBufferSize - offset,
++ &linkBytes
++ ));
++
++ /* Mark context as not dirty. */
++ Context->dirty = gcvFALSE;
++ }
++ else
++ {
++ /***************************************************************
++ ** SWITCHING CONTEXT: 2D only command buffer.
++ */
++
++ /* Mark 3D as dirty. */
++ Context->dirty3D = gcvTRUE;
++
++ /* Compute the entry. */
++ if (Command->pipeSelect == gcvPIPE_2D)
++ {
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ entryPhysical = (gctUINT8_PTR) contextBuffer->physical + pipeBytes;
++#endif
++ entryLogical = (gctUINT8_PTR) contextBuffer->logical + pipeBytes;
++ entryBytes = Context->entryOffset3D - pipeBytes;
++ }
++ else
++ {
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ entryPhysical = (gctUINT8_PTR) contextBuffer->physical;
++#endif
++ entryLogical = (gctUINT8_PTR) contextBuffer->logical;
++ entryBytes = Context->entryOffset3D;
++ }
++
++ /* Store the current context buffer. */
++ Context->dirtyBuffer = contextBuffer;
++
++ /* See if we have to switch pipes between the context
++ and command buffers. */
++ if (commandBufferObject->entryPipe == gcvPIPE_2D)
++ {
++ /* Skip pipe switching sequence. */
++ offset = pipeBytes;
++ }
++ else
++ {
++ /* The current hardware and the initial context pipes are
++ different, switch to the correct pipe. */
++ gcmkONERROR(gckHARDWARE_PipeSelect(
++ Command->kernel->hardware,
++ commandBufferLogical,
++ commandBufferObject->entryPipe,
++ &pipeBytes
++ ));
++
++ /* Do not skip pipe switching sequence. */
++ offset = 0;
++ }
++
++ /* 3D is not used, generate a LINK from the end of 2D part of
++ the context buffer to the command buffer. */
++ gcmkONERROR(gckHARDWARE_Link(
++ hardware,
++ contextBuffer->link2D,
++ commandBufferLogical + offset,
++ commandBufferSize - offset,
++ &linkBytes
++ ));
++ }
++ }
++
++ /* Not using 2D. */
++ else
++ {
++ /* Mark 2D as dirty. */
++ Context->dirty2D = gcvTRUE;
++
++ /* Store the current context buffer. */
++ Context->dirtyBuffer = contextBuffer;
++
++ if (Context->dirty || commandBufferObject->using3D)
++ {
++ /***************************************************************
++ ** SWITCHING CONTEXT: 3D only command buffer.
++ */
++
++ /* Reset 3D dirty flag. */
++ Context->dirty3D = gcvFALSE;
++
++ /* Determine context buffer entry offset. */
++ offset = (Command->pipeSelect == gcvPIPE_3D)
++
++ /* Skip pipe switching sequence. */
++ ? Context->entryOffset3D + pipeBytes
++
++ /* Do not skip pipe switching sequence. */
++ : Context->entryOffset3D;
++
++ /* Compute the entry. */
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ entryPhysical = (gctUINT8_PTR) contextBuffer->physical + offset;
++#endif
++ entryLogical = (gctUINT8_PTR) contextBuffer->logical + offset;
++ entryBytes = Context->bufferSize - offset;
++
++ /* See if we have to switch pipes between the context
++ and command buffers. */
++ if (commandBufferObject->entryPipe == gcvPIPE_3D)
++ {
++ /* Skip pipe switching sequence. */
++ offset = pipeBytes;
++ }
++ else
++ {
++ /* The current hardware and the initial context pipes are
++ different, switch to the correct pipe. */
++ gcmkONERROR(gckHARDWARE_PipeSelect(
++ Command->kernel->hardware,
++ commandBufferLogical,
++ commandBufferObject->entryPipe,
++ &pipeBytes
++ ));
++
++ /* Do not skip pipe switching sequence. */
++ offset = 0;
++ }
++
++ /* Generate a LINK from the context buffer to
++ the command buffer. */
++ gcmkONERROR(gckHARDWARE_Link(
++ hardware,
++ contextBuffer->link3D,
++ commandBufferLogical + offset,
++ commandBufferSize - offset,
++ &linkBytes
++ ));
++ }
++ else
++ {
++ /***************************************************************
++ ** SWITCHING CONTEXT: "XD" command buffer - neither 2D nor 3D.
++ */
++
++ /* Mark 3D as dirty. */
++ Context->dirty3D = gcvTRUE;
++
++ /* Compute the entry. */
++ if (Command->pipeSelect == gcvPIPE_3D)
++ {
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ entryPhysical
++ = (gctUINT8_PTR) contextBuffer->physical
++ + Context->entryOffsetXDFrom3D;
++#endif
++ entryLogical
++ = (gctUINT8_PTR) contextBuffer->logical
++ + Context->entryOffsetXDFrom3D;
++
++ entryBytes
++ = Context->bufferSize
++ - Context->entryOffsetXDFrom3D;
++ }
++ else
++ {
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ entryPhysical
++ = (gctUINT8_PTR) contextBuffer->physical
++ + Context->entryOffsetXDFrom2D;
++#endif
++ entryLogical
++ = (gctUINT8_PTR) contextBuffer->logical
++ + Context->entryOffsetXDFrom2D;
++
++ entryBytes
++ = Context->totalSize
++ - Context->entryOffsetXDFrom2D;
++ }
++
++ /* See if we have to switch pipes between the context
++ and command buffers. */
++ if (commandBufferObject->entryPipe == gcvPIPE_3D)
++ {
++ /* Skip pipe switching sequence. */
++ offset = pipeBytes;
++ }
++ else
++ {
++ /* The current hardware and the initial context pipes are
++ different, switch to the correct pipe. */
++ gcmkONERROR(gckHARDWARE_PipeSelect(
++ Command->kernel->hardware,
++ commandBufferLogical,
++ commandBufferObject->entryPipe,
++ &pipeBytes
++ ));
++
++ /* Do not skip pipe switching sequence. */
++ offset = 0;
++ }
++
++ /* Generate a LINK from the context buffer to
++ the command buffer. */
++ gcmkONERROR(gckHARDWARE_Link(
++ hardware,
++ contextBuffer->link3D,
++ commandBufferLogical + offset,
++ commandBufferSize - offset,
++ &linkBytes
++ ));
++ }
++ }
++
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ /* Flush the context buffer cache. */
++ gcmkONERROR(gckOS_CacheClean(
++ Command->os,
++ Command->kernelProcessID,
++ gcvNULL,
++ entryPhysical,
++ entryLogical,
++ entryBytes
++ ));
++#endif
++
++ /* Update the current context. */
++ Command->currContext = Context;
++
++#if gcdDUMP_COMMAND
++ contextDumpLogical = entryLogical;
++ contextDumpBytes = entryBytes;
++#endif
++ }
++
++ /* Same context. */
++ else
++ {
++ /* Determine context entry and exit points. */
++ if (commandBufferObject->using2D && Context->dirty2D)
++ {
++ /* Reset 2D dirty flag. */
++ Context->dirty2D = gcvFALSE;
++
++ /* Get the "dirty" context buffer. */
++ contextBuffer = Context->dirtyBuffer;
++
++ if (commandBufferObject->using3D && Context->dirty3D)
++ {
++ /* Reset 3D dirty flag. */
++ Context->dirty3D = gcvFALSE;
++
++ /* Compute the entry. */
++ if (Command->pipeSelect == gcvPIPE_2D)
++ {
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ entryPhysical = (gctUINT8_PTR) contextBuffer->physical + pipeBytes;
++#endif
++ entryLogical = (gctUINT8_PTR) contextBuffer->logical + pipeBytes;
++ entryBytes = Context->bufferSize - pipeBytes;
++ }
++ else
++ {
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ entryPhysical = (gctUINT8_PTR) contextBuffer->physical;
++#endif
++ entryLogical = (gctUINT8_PTR) contextBuffer->logical;
++ entryBytes = Context->bufferSize;
++ }
++
++ /* See if we have to switch pipes between the context
++ and command buffers. */
++ if (commandBufferObject->entryPipe == gcvPIPE_3D)
++ {
++ /* Skip pipe switching sequence. */
++ offset = pipeBytes;
++ }
++ else
++ {
++ /* The current hardware and the initial context pipes are
++ different, switch to the correct pipe. */
++ gcmkONERROR(gckHARDWARE_PipeSelect(
++ Command->kernel->hardware,
++ commandBufferLogical,
++ commandBufferObject->entryPipe,
++ &pipeBytes
++ ));
++
++ /* Do not skip pipe switching sequence. */
++ offset = 0;
++ }
++
++ /* Ensure the NOP between 2D and 3D is in place so that the
++ execution falls through from 2D to 3D. */
++ gcmkONERROR(gckHARDWARE_Nop(
++ hardware,
++ contextBuffer->link2D,
++ &nopBytes
++ ));
++
++ /* Generate a LINK from the context buffer to
++ the command buffer. */
++ gcmkONERROR(gckHARDWARE_Link(
++ hardware,
++ contextBuffer->link3D,
++ commandBufferLogical + offset,
++ commandBufferSize - offset,
++ &linkBytes
++ ));
++ }
++ else
++ {
++ /* Compute the entry. */
++ if (Command->pipeSelect == gcvPIPE_2D)
++ {
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ entryPhysical = (gctUINT8_PTR) contextBuffer->physical + pipeBytes;
++#endif
++ entryLogical = (gctUINT8_PTR) contextBuffer->logical + pipeBytes;
++ entryBytes = Context->entryOffset3D - pipeBytes;
++ }
++ else
++ {
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ entryPhysical = (gctUINT8_PTR) contextBuffer->physical;
++#endif
++ entryLogical = (gctUINT8_PTR) contextBuffer->logical;
++ entryBytes = Context->entryOffset3D;
++ }
++
++ /* See if we have to switch pipes between the context
++ and command buffers. */
++ if (commandBufferObject->entryPipe == gcvPIPE_2D)
++ {
++ /* Skip pipe switching sequence. */
++ offset = pipeBytes;
++ }
++ else
++ {
++ /* The current hardware and the initial context pipes are
++ different, switch to the correct pipe. */
++ gcmkONERROR(gckHARDWARE_PipeSelect(
++ Command->kernel->hardware,
++ commandBufferLogical,
++ commandBufferObject->entryPipe,
++ &pipeBytes
++ ));
++
++ /* Do not skip pipe switching sequence. */
++ offset = 0;
++ }
++
++ /* 3D is not used, generate a LINK from the end of 2D part of
++ the context buffer to the command buffer. */
++ gcmkONERROR(gckHARDWARE_Link(
++ hardware,
++ contextBuffer->link2D,
++ commandBufferLogical + offset,
++ commandBufferSize - offset,
++ &linkBytes
++ ));
++ }
++ }
++ else
++ {
++ if (commandBufferObject->using3D && Context->dirty3D)
++ {
++ /* Reset 3D dirty flag. */
++ Context->dirty3D = gcvFALSE;
++
++ /* Get the "dirty" context buffer. */
++ contextBuffer = Context->dirtyBuffer;
++
++ /* Determine context buffer entry offset. */
++ offset = (Command->pipeSelect == gcvPIPE_3D)
++
++ /* Skip pipe switching sequence. */
++ ? Context->entryOffset3D + pipeBytes
++
++ /* Do not skip pipe switching sequence. */
++ : Context->entryOffset3D;
++
++ /* Compute the entry. */
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ entryPhysical = (gctUINT8_PTR) contextBuffer->physical + offset;
++#endif
++ entryLogical = (gctUINT8_PTR) contextBuffer->logical + offset;
++ entryBytes = Context->bufferSize - offset;
++
++ /* See if we have to switch pipes between the context
++ and command buffers. */
++ if (commandBufferObject->entryPipe == gcvPIPE_3D)
++ {
++ /* Skip pipe switching sequence. */
++ offset = pipeBytes;
++ }
++ else
++ {
++ /* The current hardware and the initial context pipes are
++ different, switch to the correct pipe. */
++ gcmkONERROR(gckHARDWARE_PipeSelect(
++ Command->kernel->hardware,
++ commandBufferLogical,
++ commandBufferObject->entryPipe,
++ &pipeBytes
++ ));
++
++ /* Do not skip pipe switching sequence. */
++ offset = 0;
++ }
++
++ /* Generate a LINK from the context buffer to
++ the command buffer. */
++ gcmkONERROR(gckHARDWARE_Link(
++ hardware,
++ contextBuffer->link3D,
++ commandBufferLogical + offset,
++ commandBufferSize - offset,
++ &linkBytes
++ ));
++ }
++ else
++ {
++ /* See if we have to switch pipes for the command buffer. */
++ if (commandBufferObject->entryPipe == Command->pipeSelect)
++ {
++ /* Skip pipe switching sequence. */
++ offset = pipeBytes;
++ }
++ else
++ {
++ /* The current hardware and the entry command buffer pipes
++ ** are different, switch to the correct pipe. */
++ gcmkONERROR(gckHARDWARE_PipeSelect(
++ Command->kernel->hardware,
++ commandBufferLogical,
++ commandBufferObject->entryPipe,
++ &pipeBytes
++ ));
++
++ /* Do not skip pipe switching sequence. */
++ offset = 0;
++ }
++
++ /* Compute the entry. */
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ entryPhysical = (gctUINT8_PTR) commandBufferPhysical + offset;
++#endif
++ entryLogical = commandBufferLogical + offset;
++ entryBytes = commandBufferSize - offset;
++ }
++ }
++ }
++
++#if gcdDUMP_COMMAND
++ bufferDumpLogical = commandBufferLogical + offset;
++ bufferDumpBytes = commandBufferSize - offset;
++#endif
++
++#if gcdSECURE_USER
++ /* Process user hints. */
++ gcmkONERROR(_ProcessHints(Command, ProcessID, commandBufferObject));
++#endif
++
++ /* Determine the location to jump to for the command buffer being
++ ** scheduled. */
++ if (Command->newQueue)
++ {
++ /* New command queue, jump to the beginning of it. */
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ exitPhysical = Command->physical;
++#endif
++ exitLogical = Command->logical;
++ exitBytes = Command->offset + waitLinkBytes;
++ }
++ else
++ {
++ /* Still within the preexisting command queue, jump to the new
++ WAIT/LINK command sequence. */
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ exitPhysical = waitLinkPhysical;
++#endif
++ exitLogical = waitLinkLogical;
++ exitBytes = waitLinkBytes;
++ }
++
++ /* Add a new WAIT/LINK command sequence. When the command buffer which is
++ currently being scheduled is fully executed by the GPU, the FE will
++ jump to this WAIT/LINK sequence. */
++ gcmkONERROR(gckHARDWARE_WaitLink(
++ hardware,
++ waitLinkLogical,
++ offset,
++ &waitLinkBytes,
++ &waitOffset,
++ &waitSize
++ ));
++
++ /* Compute the location if WAIT command. */
++ waitPhysical = (gctUINT8_PTR) waitLinkPhysical + waitOffset;
++ waitLogical = (gctUINT8_PTR) waitLinkLogical + waitOffset;
++
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ /* Flush the command queue cache. */
++ gcmkONERROR(gckOS_CacheClean(
++ Command->os,
++ Command->kernelProcessID,
++ gcvNULL,
++ exitPhysical,
++ exitLogical,
++ exitBytes
++ ));
++#endif
++
++ /* Determine the location of the LINK command in the command buffer. */
++ commandBufferLink
++ = (gctUINT8_PTR) gcmUINT64_TO_PTR(commandBufferObject->logical)
++ + commandBufferObject->offset;
++
++ /* Generate a LINK from the end of the command buffer being scheduled
++ back to the kernel command queue. */
++ gcmkONERROR(gckHARDWARE_Link(
++ hardware,
++ commandBufferLink,
++ exitLogical,
++ exitBytes,
++ &linkBytes
++ ));
++
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ /* Flush the command buffer cache. */
++ gcmkONERROR(gckOS_CacheClean(
++ Command->os,
++ ProcessID,
++ gcvNULL,
++ commandBufferPhysical,
++ commandBufferLogical,
++ commandBufferSize
++ ));
++#endif
++
++ /* Generate a LINK from the previous WAIT/LINK command sequence to the
++ entry determined above (either the context or the command buffer).
++ This LINK replaces the WAIT instruction from the previous WAIT/LINK
++ pair, therefore we use WAIT metrics for generation of this LINK.
++ This action will execute the entire sequence. */
++ gcmkONERROR(gckHARDWARE_Link(
++ hardware,
++ Command->waitLogical,
++ entryLogical,
++ entryBytes,
++ &Command->waitSize
++ ));
++
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ /* Flush the cache for the link. */
++ gcmkONERROR(gckOS_CacheClean(
++ Command->os,
++ Command->kernelProcessID,
++ gcvNULL,
++ Command->waitPhysical,
++ Command->waitLogical,
++ Command->waitSize
++ ));
++#endif
++
++ gcmkDUMPCOMMAND(
++ Command->os,
++ Command->waitLogical,
++ Command->waitSize,
++ gceDUMP_BUFFER_LINK,
++ gcvFALSE
++ );
++
++ gcmkDUMPCOMMAND(
++ Command->os,
++ contextDumpLogical,
++ contextDumpBytes,
++ gceDUMP_BUFFER_CONTEXT,
++ gcvFALSE
++ );
++
++ gcmkDUMPCOMMAND(
++ Command->os,
++ bufferDumpLogical,
++ bufferDumpBytes,
++ gceDUMP_BUFFER_USER,
++ gcvFALSE
++ );
++
++ gcmkDUMPCOMMAND(
++ Command->os,
++ waitLinkLogical,
++ waitLinkBytes,
++ gceDUMP_BUFFER_WAITLINK,
++ gcvFALSE
++ );
++
++ /* Update the current pipe. */
++ Command->pipeSelect = commandBufferObject->exitPipe;
++
++ /* Update command queue offset. */
++ Command->offset += waitLinkBytes;
++ Command->newQueue = gcvFALSE;
++
++ /* Update address of last WAIT. */
++ Command->waitPhysical = waitPhysical;
++ Command->waitLogical = waitLogical;
++ Command->waitSize = waitSize;
++
++ /* Update queue tail pointer. */
++ gcmkONERROR(gckHARDWARE_UpdateQueueTail(
++ hardware, Command->logical, Command->offset
++ ));
++
++#if gcdDUMP_COMMAND
++ gcmkPRINT("@[kernel.commit]");
++#endif
++#endif /* gcdNULL_DRIVER */
++
++ /* Release the context switching mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Command->os, Command->mutexContext));
++ contextAcquired = gcvFALSE;
++
++ /* Release the command queue. */
++ gcmkONERROR(gckCOMMAND_ExitCommit(Command, gcvFALSE));
++ commitEntered = gcvFALSE;
++
++#if VIVANTE_PROFILER_CONTEXT
++ if(sequenceAcquired)
++ {
++ gcmkONERROR(gckCOMMAND_Stall(Command, gcvTRUE));
++ if (Command->currContext)
++ {
++ gcmkONERROR(gckHARDWARE_UpdateContextProfile(
++ hardware,
++ Command->currContext));
++ }
++
++ /* Release the context switching mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Command->os, Command->mutexContextSeq));
++ sequenceAcquired = gcvFALSE;
++ }
++#endif
++
++ /* Loop while there are records in the queue. */
++ while (EventQueue != gcvNULL)
++ {
++ if (needCopy)
++ {
++ /* Point to stack record. */
++ eventRecord = &_eventRecord;
++
++ /* Copy the data from the client. */
++ gcmkONERROR(gckOS_CopyFromUserData(
++ Command->os, eventRecord, EventQueue, gcmSIZEOF(gcsQUEUE)
++ ));
++ }
++ else
++ {
++ /* Map record into kernel memory. */
++ gcmkONERROR(gckOS_MapUserPointer(Command->os,
++ EventQueue,
++ gcmSIZEOF(gcsQUEUE),
++ &pointer));
++
++ eventRecord = pointer;
++ }
++
++ /* Append event record to event queue. */
++ gcmkONERROR(gckEVENT_AddList(
++ Command->kernel->eventObj, &eventRecord->iface, gcvKERNEL_PIXEL, gcvTRUE, gcvFALSE
++ ));
++
++ /* Next record in the queue. */
++ nextEventRecord = gcmUINT64_TO_PTR(eventRecord->next);
++
++ if (!needCopy)
++ {
++ /* Unmap record from kernel memory. */
++ gcmkONERROR(gckOS_UnmapUserPointer(
++ Command->os, EventQueue, gcmSIZEOF(gcsQUEUE), (gctPOINTER *) eventRecord
++ ));
++
++ eventRecord = gcvNULL;
++ }
++
++ EventQueue = nextEventRecord;
++ }
++
++ if (Command->kernel->eventObj->queueHead == gcvNULL
++ && Command->kernel->hardware->powerManagement == gcvTRUE
++ )
++ {
++ /* Commit done event by which work thread knows all jobs done. */
++ gcmkVERIFY_OK(
++ gckEVENT_CommitDone(Command->kernel->eventObj, gcvKERNEL_PIXEL));
++ }
++
++ /* Submit events. */
++ status = gckEVENT_Submit(Command->kernel->eventObj, gcvTRUE, gcvFALSE);
++
++ if (status == gcvSTATUS_INTERRUPTED)
++ {
++ gcmkTRACE(
++ gcvLEVEL_INFO,
++ "%s(%d): Intterupted in gckEVENT_Submit",
++ __FUNCTION__, __LINE__
++ );
++ status = gcvSTATUS_OK;
++ }
++ else
++ {
++ gcmkONERROR(status);
++ }
++
++ /* Unmap the command buffer pointer. */
++ if (commandBufferMapped)
++ {
++ gcmkONERROR(gckOS_UnmapUserPointer(
++ Command->os,
++ CommandBuffer,
++ gcmSIZEOF(struct _gcoCMDBUF),
++ commandBufferObject
++ ));
++
++ commandBufferMapped = gcvFALSE;
++ }
++
++ /* Return status. */
++ gcmkFOOTER();
++ return gcvSTATUS_OK;
++
++OnError:
++ if ((eventRecord != gcvNULL) && !needCopy)
++ {
++ /* Roll back. */
++ gcmkVERIFY_OK(gckOS_UnmapUserPointer(
++ Command->os,
++ EventQueue,
++ gcmSIZEOF(gcsQUEUE),
++ (gctPOINTER *) eventRecord
++ ));
++ }
++
++ if (contextAcquired)
++ {
++ /* Release the context switching mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Command->os, Command->mutexContext));
++ }
++
++ if (commitEntered)
++ {
++ /* Release the command queue mutex. */
++ gcmkVERIFY_OK(gckCOMMAND_ExitCommit(Command, gcvFALSE));
++ }
++
++#if VIVANTE_PROFILER_CONTEXT
++ if (sequenceAcquired)
++ {
++ /* Release the context sequence mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Command->os, Command->mutexContextSeq));
++ }
++#endif
++
++ /* Unmap the command buffer pointer. */
++ if (commandBufferMapped)
++ {
++ gcmkVERIFY_OK(gckOS_UnmapUserPointer(
++ Command->os,
++ CommandBuffer,
++ gcmSIZEOF(struct _gcoCMDBUF),
++ commandBufferObject
++ ));
++ }
++
++ /* Return status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckCOMMAND_Reserve
++**
++** Reserve space in the command queue. Also acquire the command queue mutex.
++**
++** INPUT:
++**
++** gckCOMMAND Command
++** Pointer to an gckCOMMAND object.
++**
++** gctSIZE_T RequestedBytes
++** Number of bytes previously reserved.
++**
++** OUTPUT:
++**
++** gctPOINTER * Buffer
++** Pointer to a variable that will receive the address of the reserved
++** space.
++**
++** gctSIZE_T * BufferSize
++** Pointer to a variable that will receive the number of bytes
++** available in the command queue.
++*/
++gceSTATUS
++gckCOMMAND_Reserve(
++ IN gckCOMMAND Command,
++ IN gctSIZE_T RequestedBytes,
++ OUT gctPOINTER * Buffer,
++ OUT gctSIZE_T * BufferSize
++ )
++{
++ gceSTATUS status;
++ gctSIZE_T bytes;
++ gctSIZE_T requiredBytes;
++ gctUINT32 requestedAligned;
++
++ gcmkHEADER_ARG("Command=0x%x RequestedBytes=%lu", Command, RequestedBytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ /* Compute aligned number of reuested bytes. */
++ requestedAligned = gcmALIGN(RequestedBytes, Command->alignment);
++
++ /* Another WAIT/LINK command sequence will have to be appended after
++ the requested area being reserved. Compute the number of bytes
++ required for WAIT/LINK at the location after the reserved area. */
++ gcmkONERROR(gckHARDWARE_WaitLink(
++ Command->kernel->hardware,
++ gcvNULL,
++ Command->offset + requestedAligned,
++ &requiredBytes,
++ gcvNULL,
++ gcvNULL
++ ));
++
++ /* Compute total number of bytes required. */
++ requiredBytes += requestedAligned;
++
++ /* Compute number of bytes available in command queue. */
++ bytes = Command->pageSize - Command->offset;
++
++ /* Is there enough space in the current command queue? */
++ if (bytes < requiredBytes)
++ {
++ /* Create a new command queue. */
++ gcmkONERROR(_NewQueue(Command));
++
++ /* Recompute the number of bytes in the new kernel command queue. */
++ bytes = Command->pageSize - Command->offset;
++
++ /* Still not enough space? */
++ if (bytes < requiredBytes)
++ {
++ /* Rare case, not enough room in command queue. */
++ gcmkONERROR(gcvSTATUS_BUFFER_TOO_SMALL);
++ }
++ }
++
++ /* Return pointer to empty slot command queue. */
++ *Buffer = (gctUINT8 *) Command->logical + Command->offset;
++
++ /* Return number of bytes left in command queue. */
++ *BufferSize = bytes;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Buffer=0x%x *BufferSize=%lu", *Buffer, *BufferSize);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckCOMMAND_Execute
++**
++** Execute a previously reserved command queue by appending a WAIT/LINK command
++** sequence after it and modifying the last WAIT into a LINK command. The
++** command FIFO mutex will be released whether this function succeeds or not.
++**
++** INPUT:
++**
++** gckCOMMAND Command
++** Pointer to an gckCOMMAND object.
++**
++** gctSIZE_T RequestedBytes
++** Number of bytes previously reserved.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckCOMMAND_Execute(
++ IN gckCOMMAND Command,
++ IN gctSIZE_T RequestedBytes
++ )
++{
++ gceSTATUS status;
++
++ gctPHYS_ADDR waitLinkPhysical;
++ gctUINT8_PTR waitLinkLogical;
++ gctUINT32 waitLinkOffset;
++ gctSIZE_T waitLinkBytes;
++
++ gctPHYS_ADDR waitPhysical;
++ gctPOINTER waitLogical;
++ gctUINT32 waitOffset;
++ gctSIZE_T waitBytes;
++
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ gctPHYS_ADDR execPhysical;
++#endif
++ gctPOINTER execLogical;
++ gctSIZE_T execBytes;
++
++ gcmkHEADER_ARG("Command=0x%x RequestedBytes=%lu", Command, RequestedBytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ /* Compute offset for WAIT/LINK. */
++ waitLinkOffset = Command->offset + RequestedBytes;
++
++ /* Compute number of bytes left in command queue. */
++ waitLinkBytes = Command->pageSize - waitLinkOffset;
++
++ /* Compute the location if WAIT/LINK command sequence. */
++ waitLinkPhysical = (gctUINT8_PTR) Command->physical + waitLinkOffset;
++ waitLinkLogical = (gctUINT8_PTR) Command->logical + waitLinkOffset;
++
++ /* Append WAIT/LINK in command queue. */
++ gcmkONERROR(gckHARDWARE_WaitLink(
++ Command->kernel->hardware,
++ waitLinkLogical,
++ waitLinkOffset,
++ &waitLinkBytes,
++ &waitOffset,
++ &waitBytes
++ ));
++
++ /* Compute the location if WAIT command. */
++ waitPhysical = (gctUINT8_PTR) waitLinkPhysical + waitOffset;
++ waitLogical = waitLinkLogical + waitOffset;
++
++ /* Determine the location to jump to for the command buffer being
++ ** scheduled. */
++ if (Command->newQueue)
++ {
++ /* New command queue, jump to the beginning of it. */
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ execPhysical = Command->physical;
++#endif
++ execLogical = Command->logical;
++ execBytes = waitLinkOffset + waitLinkBytes;
++ }
++ else
++ {
++ /* Still within the preexisting command queue, jump directly to the
++ reserved area. */
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ execPhysical = (gctUINT8 *) Command->physical + Command->offset;
++#endif
++ execLogical = (gctUINT8 *) Command->logical + Command->offset;
++ execBytes = RequestedBytes + waitLinkBytes;
++ }
++
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ /* Flush the cache. */
++ gcmkONERROR(gckOS_CacheClean(
++ Command->os,
++ Command->kernelProcessID,
++ gcvNULL,
++ execPhysical,
++ execLogical,
++ execBytes
++ ));
++#endif
++
++ /* Convert the last WAIT into a LINK. */
++ gcmkONERROR(gckHARDWARE_Link(
++ Command->kernel->hardware,
++ Command->waitLogical,
++ execLogical,
++ execBytes,
++ &Command->waitSize
++ ));
++
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ /* Flush the cache. */
++ gcmkONERROR(gckOS_CacheClean(
++ Command->os,
++ Command->kernelProcessID,
++ gcvNULL,
++ Command->waitPhysical,
++ Command->waitLogical,
++ Command->waitSize
++ ));
++#endif
++
++ gcmkDUMPCOMMAND(
++ Command->os,
++ Command->waitLogical,
++ Command->waitSize,
++ gceDUMP_BUFFER_LINK,
++ gcvFALSE
++ );
++
++ gcmkDUMPCOMMAND(
++ Command->os,
++ execLogical,
++ execBytes,
++ gceDUMP_BUFFER_KERNEL,
++ gcvFALSE
++ );
++
++ /* Update the pointer to the last WAIT. */
++ Command->waitPhysical = waitPhysical;
++ Command->waitLogical = waitLogical;
++ Command->waitSize = waitBytes;
++
++ /* Update the command queue. */
++ Command->offset += RequestedBytes + waitLinkBytes;
++ Command->newQueue = gcvFALSE;
++
++ /* Update queue tail pointer. */
++ gcmkONERROR(gckHARDWARE_UpdateQueueTail(
++ Command->kernel->hardware, Command->logical, Command->offset
++ ));
++
++#if gcdDUMP_COMMAND
++ gcmkPRINT("@[kernel.execute]");
++#endif
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckCOMMAND_Stall
++**
++** The calling thread will be suspended until the command queue has been
++** completed.
++**
++** INPUT:
++**
++** gckCOMMAND Command
++** Pointer to an gckCOMMAND object.
++**
++** gctBOOL FromPower
++** Determines whether the call originates from inside the power
++** management or not.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckCOMMAND_Stall(
++ IN gckCOMMAND Command,
++ IN gctBOOL FromPower
++ )
++{
++#if gcdNULL_DRIVER
++ /* Do nothing with infinite hardware. */
++ return gcvSTATUS_OK;
++#else
++ gckOS os;
++ gckHARDWARE hardware;
++ gckEVENT eventObject;
++ gceSTATUS status;
++ gctSIGNAL signal = gcvNULL;
++ gctUINT timer = 0;
++
++ gcmkHEADER_ARG("Command=0x%x", Command);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ /* Extract the gckOS object pointer. */
++ os = Command->os;
++ gcmkVERIFY_OBJECT(os, gcvOBJ_OS);
++
++ /* Extract the gckHARDWARE object pointer. */
++ hardware = Command->kernel->hardware;
++ gcmkVERIFY_OBJECT(hardware, gcvOBJ_HARDWARE);
++
++ /* Extract the gckEVENT object pointer. */
++ eventObject = Command->kernel->eventObj;
++ gcmkVERIFY_OBJECT(eventObject, gcvOBJ_EVENT);
++
++ /* Allocate the signal. */
++ gcmkONERROR(gckOS_CreateSignal(os, gcvTRUE, &signal));
++
++ /* Append the EVENT command to trigger the signal. */
++ gcmkONERROR(gckEVENT_Signal(eventObject, signal, gcvKERNEL_PIXEL));
++
++ /* Submit the event queue. */
++ gcmkONERROR(gckEVENT_Submit(eventObject, gcvTRUE, FromPower));
++
++#if gcdDUMP_COMMAND
++ gcmkPRINT("@[kernel.stall]");
++#endif
++
++ if (status == gcvSTATUS_CHIP_NOT_READY)
++ {
++ /* Error. */
++ goto OnError;
++ }
++
++ do
++ {
++ /* Wait for the signal. */
++ status = gckOS_WaitSignal(os, signal, gcdGPU_ADVANCETIMER);
++
++ if (status == gcvSTATUS_TIMEOUT)
++ {
++#if gcmIS_DEBUG(gcdDEBUG_CODE)
++ gctUINT32 idle;
++
++ /* Read idle register. */
++ gcmkVERIFY_OK(gckHARDWARE_GetIdle(
++ hardware, gcvFALSE, &idle
++ ));
++
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): idle=%08x",
++ __FUNCTION__, __LINE__, idle
++ );
++
++ gcmkONERROR(gckOS_MemoryBarrier(os, gcvNULL));
++
++#ifdef __QNXNTO__
++ gctUINT32 reg_cmdbuf_fetch;
++ gctUINT32 reg_intr;
++
++ gcmkVERIFY_OK(gckOS_ReadRegisterEx(
++ Command->kernel->hardware->os, Command->kernel->core, 0x0664, &reg_cmdbuf_fetch
++ ));
++
++ if (idle == 0x7FFFFFFE)
++ {
++ /*
++ * GPU is idle so there should not be pending interrupts.
++ * Just double check.
++ *
++ * Note that reading interrupt register clears it.
++ * That's why we don't read it in all cases.
++ */
++ gcmkVERIFY_OK(gckOS_ReadRegisterEx(
++ Command->kernel->hardware->os, Command->kernel->core, 0x10, &reg_intr
++ ));
++
++ slogf(
++ _SLOG_SETCODE(1, 0),
++ _SLOG_CRITICAL,
++ "GALcore: Stall timeout (idle = 0x%X, command buffer fetch = 0x%X, interrupt = 0x%X)",
++ idle, reg_cmdbuf_fetch, reg_intr
++ );
++ }
++ else
++ {
++ slogf(
++ _SLOG_SETCODE(1, 0),
++ _SLOG_CRITICAL,
++ "GALcore: Stall timeout (idle = 0x%X, command buffer fetch = 0x%X)",
++ idle, reg_cmdbuf_fetch
++ );
++ }
++#endif
++#endif
++ /* Advance timer. */
++ timer += gcdGPU_ADVANCETIMER;
++ }
++ else if (status == gcvSTATUS_INTERRUPTED)
++ {
++ gcmkONERROR(gcvSTATUS_INTERRUPTED);
++ }
++
++ }
++ while (gcmIS_ERROR(status)
++#if gcdGPU_TIMEOUT
++ && (timer < Command->kernel->timeOut)
++#endif
++ );
++
++ /* Bail out on timeout. */
++ if (gcmIS_ERROR(status))
++ {
++ /* Broadcast the stuck GPU. */
++ gcmkONERROR(gckOS_Broadcast(
++ os, hardware, gcvBROADCAST_GPU_STUCK
++ ));
++ }
++
++ /* Delete the signal. */
++ gcmkVERIFY_OK(gckOS_DestroySignal(os, signal));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (signal != gcvNULL)
++ {
++ /* Free the signal. */
++ gcmkVERIFY_OK(gckOS_DestroySignal(os, signal));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++#endif
++}
++
++/*******************************************************************************
++**
++** gckCOMMAND_Attach
++**
++** Attach user process.
++**
++** INPUT:
++**
++** gckCOMMAND Command
++** Pointer to a gckCOMMAND object.
++**
++** gctUINT32 ProcessID
++** Current process ID.
++**
++** OUTPUT:
++**
++** gckCONTEXT * Context
++** Pointer to a variable that will receive a pointer to a new
++** gckCONTEXT object.
++**
++** gctSIZE_T * StateCount
++** Pointer to a variable that will receive the number of states
++** in the context buffer.
++*/
++gceSTATUS
++gckCOMMAND_Attach(
++ IN gckCOMMAND Command,
++ OUT gckCONTEXT * Context,
++ OUT gctSIZE_T * StateCount,
++ IN gctUINT32 ProcessID
++ )
++{
++ gceSTATUS status;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Command=0x%x", Command);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ /* Acquire the context switching mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(
++ Command->os, Command->mutexContext, gcvINFINITE
++ ));
++ acquired = gcvTRUE;
++
++ /* Construct a gckCONTEXT object. */
++ gcmkONERROR(gckCONTEXT_Construct(
++ Command->os,
++ Command->kernel->hardware,
++ ProcessID,
++ Context
++ ));
++
++ /* Return the number of states in the context. */
++ * StateCount = (* Context)->stateCount;
++
++ /* Release the context switching mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Command->os, Command->mutexContext));
++ acquired = gcvFALSE;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Context=0x%x", *Context);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Release mutex. */
++ if (acquired)
++ {
++ /* Release the context switching mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Command->os, Command->mutexContext));
++ acquired = gcvFALSE;
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckCOMMAND_Detach
++**
++** Detach user process.
++**
++** INPUT:
++**
++** gckCOMMAND Command
++** Pointer to a gckCOMMAND object.
++**
++** gckCONTEXT Context
++** Pointer to a gckCONTEXT object to be destroyed.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckCOMMAND_Detach(
++ IN gckCOMMAND Command,
++ IN gckCONTEXT Context
++ )
++{
++ gceSTATUS status;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Command=0x%x Context=0x%x", Command, Context);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ /* Acquire the context switching mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(
++ Command->os, Command->mutexContext, gcvINFINITE
++ ));
++ acquired = gcvTRUE;
++
++ /* Construct a gckCONTEXT object. */
++ gcmkONERROR(gckCONTEXT_Destroy(Context));
++
++ if (Command->currContext == Context)
++ {
++ /* Detach from gckCOMMAND object if the destoryed context is current context. */
++ Command->currContext = gcvNULL;
++ }
++
++ /* Release the context switching mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Command->os, Command->mutexContext));
++ acquired = gcvFALSE;
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Release mutex. */
++ if (acquired)
++ {
++ /* Release the context switching mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Command->os, Command->mutexContext));
++ acquired = gcvFALSE;
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++#if gcdVIRTUAL_COMMAND_BUFFER
++/*******************************************************************************
++**
++** gckCOMMAND_DumpExecutingBuffer
++**
++** Dump the command buffer which GPU is executing.
++**
++** INPUT:
++**
++** gckCOMMAND Command
++** Pointer to a gckCOMMAND object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckCOMMAND_DumpExecutingBuffer(
++ IN gckCOMMAND Command
++ )
++{
++ gceSTATUS status;
++ gckVIRTUAL_COMMAND_BUFFER_PTR buffer;
++ gctUINT32 gpuAddress;
++ gctSIZE_T pageCount;
++ gctPOINTER entry;
++ gckOS os = Command->os;
++ gckKERNEL kernel = Command->kernel;
++#if gcdLINK_QUEUE_SIZE
++ gctINT pid;
++ gctINT i, rear;
++ gctUINT32 start, end;
++ gctUINT32 dumpFront, dumpRear;
++ gckLINKQUEUE queue = &kernel->hardware->linkQueue;
++ gckLINKQUEUE queueMirror;
++ gctUINT32 bytes;
++ gckLINKDATA linkData;
++#endif
++
++ gcmkPRINT("**************************\n");
++ gcmkPRINT("**** COMMAND BUF DUMP ****\n");
++ gcmkPRINT("**************************\n");
++
++ gcmkVERIFY_OK(gckOS_ReadRegisterEx(os, kernel->core, 0x664, &gpuAddress));
++
++ gcmkPRINT("DMA Address 0x%08X", gpuAddress);
++
++#if gcdLINK_QUEUE_SIZE
++ /* Duplicate queue because it will be changed.*/
++ gcmkONERROR(gckOS_AllocateMemory(os,
++ sizeof(struct _gckLINKQUEUE),
++ (gctPOINTER *)&queueMirror));
++
++ gcmkONERROR(gckOS_MemCopy(queueMirror,
++ queue,
++ sizeof(struct _gckLINKQUEUE)));
++
++ /* If kernel command buffer link to a context buffer, then link to a user command
++ ** buffer, the second link will be in queue first, so we must fix this.
++ ** In Queue: C1 U1 U2 C2 U3 U4 U5 C3
++ ** Real: C1 X1 U1 C2 U2 U3 U4 C3 U5
++ ** Command buffer X1 which is after C1 is out of queue, so C1 is meaningless.
++ */
++ for (i = 0; i < gcdLINK_QUEUE_SIZE; i++)
++ {
++ gckLINKQUEUE_GetData(queueMirror, i, &linkData);
++
++ status = gckKERNEL_QueryGPUAddress(kernel, linkData->start, &buffer);
++
++ if (gcmIS_ERROR(status))
++ {
++ /* Can't find it in virtual command buffer list, ignore it. */
++ continue;
++ }
++
++ if (buffer->kernelLogical)
++ {
++ /* It is a context buffer. */
++ if (i == 0)
++ {
++ /* The real command buffer is out, so clear this slot. */
++ linkData->start = 0;
++ linkData->end = 0;
++ linkData->pid = 0;
++ }
++ else
++ {
++ /* switch context buffer and command buffer. */
++ struct _gckLINKDATA tmp = *linkData;
++ gckLINKDATA linkDataPrevious;
++
++ gckLINKQUEUE_GetData(queueMirror, i - 1, &linkDataPrevious);
++ *linkData = *linkDataPrevious;
++ *linkDataPrevious = tmp;
++ }
++ }
++ }
++
++ /* Clear search result. */
++ dumpFront = dumpRear = gcvINFINITE;
++
++ gcmkPRINT("Link Stack:");
++
++ /* Search stuck address in link queue from rear. */
++ rear = gcdLINK_QUEUE_SIZE - 1;
++ for (i = 0; i < gcdLINK_QUEUE_SIZE; i++)
++ {
++ gckLINKQUEUE_GetData(queueMirror, rear, &linkData);
++
++ start = linkData->start;
++ end = linkData->end;
++ pid = linkData->pid;
++
++ if (gpuAddress >= start && gpuAddress < end)
++ {
++ /* Find latest matched command buffer. */
++ gcmkPRINT(" %d, [%08X - %08X]", pid, start, end);
++
++ /* Initiliaze dump information. */
++ dumpFront = dumpRear = rear;
++ }
++
++ /* Advance to previous one. */
++ rear--;
++
++ if (dumpFront != gcvINFINITE)
++ {
++ break;
++ }
++ }
++
++ if (dumpFront == gcvINFINITE)
++ {
++ /* Can't find matched record in link queue, dump kernel command buffer. */
++ _DumpKernelCommandBuffer(Command);
++
++ /* Free local copy. */
++ gcmkOS_SAFE_FREE(os, queueMirror);
++ return gcvSTATUS_OK;
++ }
++
++ /* Search the last context buffer linked. */
++ while (rear >= 0)
++ {
++ gckLINKQUEUE_GetData(queueMirror, rear, &linkData);
++
++ gcmkPRINT(" %d, [%08X - %08X]",
++ linkData->pid,
++ linkData->start,
++ linkData->end);
++
++ status = gckKERNEL_QueryGPUAddress(kernel, linkData->start, &buffer);
++
++ if (gcmIS_SUCCESS(status) && buffer->kernelLogical)
++ {
++ /* Find a context buffer. */
++ dumpFront = rear;
++ break;
++ }
++
++ rear--;
++ }
++
++ /* Dump from last context buffer to last command buffer where hang happens. */
++ for (i = dumpFront; i <= dumpRear; i++)
++ {
++ gckLINKQUEUE_GetData(queueMirror, i, &linkData);
++
++ /* Get gpu address of this command buffer. */
++ gpuAddress = linkData->start;
++ bytes = linkData->end - gpuAddress;
++
++ /* Get the whole buffer. */
++ status = gckKERNEL_QueryGPUAddress(kernel, gpuAddress, &buffer);
++
++ if (gcmIS_ERROR(status))
++ {
++ gcmkPRINT("Buffer [%08X - %08X] is lost",
++ linkData->start,
++ linkData->end);
++ continue;
++ }
++
++ /* Get kernel logical for dump. */
++ if (buffer->kernelLogical)
++ {
++ /* Get kernel logical directly if it is a context buffer. */
++ entry = buffer->kernelLogical;
++ gcmkPRINT("Context Buffer:");
++ }
++ else
++ {
++ /* Make it accessiable by kernel if it is a user command buffer. */
++ gcmkVERIFY_OK(
++ gckOS_CreateKernelVirtualMapping(buffer->physical,
++ &pageCount,
++ &entry));
++ gcmkPRINT("User Command Buffer:");
++ }
++
++ /* Dump from the entry. */
++ _DumpBuffer(entry + (gpuAddress - buffer->gpuAddress), gpuAddress, bytes);
++
++ /* Release kernel logical address if neccessary. */
++ if (!buffer->kernelLogical)
++ {
++ gcmkVERIFY_OK(gckOS_DestroyKernelVirtualMapping(entry));
++ }
++ }
++
++ /* Free local copy. */
++ gcmkOS_SAFE_FREE(os, queueMirror);
++ return gcvSTATUS_OK;
++OnError:
++ return status;
++#else
++ /* Without link queue information, we don't know the entry of last command
++ ** buffer, just dump the page where GPU stuck. */
++ status = gckKERNEL_QueryGPUAddress(kernel, gpuAddress, &buffer);
++
++ if (gcmIS_SUCCESS(status))
++ {
++ gcmkVERIFY_OK(
++ gckOS_CreateKernelVirtualMapping(buffer->physical, &pageCount, &entry));
++
++ if (entry)
++ {
++ gctUINT32 offset = gpuAddress - buffer->gpuAddress;
++ gctPOINTER entryDump = entry;
++
++ /* Dump one pages. */
++ gctUINT32 bytes = 4096;
++
++ /* Align to page. */
++ offset &= 0xfffff000;
++
++ /* Kernel address of page where stall point stay. */
++ entryDump += offset;
++
++ /* Align to page. */
++ gpuAddress &= 0xfffff000;
++
++ gcmkPRINT("User Command Buffer:\n");
++ _DumpBuffer(entryDump, gpuAddress, bytes);
++ }
++
++ gcmkVERIFY_OK(
++ gckOS_DestroyKernelVirtualMapping(entry));
++ }
++ else
++ {
++ _DumpKernelCommandBuffer(Command);
++ }
++
++ return gcvSTATUS_OK;
++#endif
++}
++#endif
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_command_vg.c linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_command_vg.c
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_command_vg.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_command_vg.c 2015-07-27 23:13:06.190893891 +0200
+@@ -0,0 +1,3678 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_precomp.h"
++
++#if gcdENABLE_VG
++
++#include "gc_hal_kernel_hardware_command_vg.h"
++
++#define _GC_OBJ_ZONE gcvZONE_COMMAND
++
++/******************************************************************************\
++*********************************** Debugging **********************************
++\******************************************************************************/
++
++#define gcvDISABLE_TIMEOUT 1
++#define gcvDUMP_COMMAND_BUFFER 0
++#define gcvDUMP_COMMAND_LINES 0
++
++
++#if gcvDEBUG || defined(EMULATOR) || gcvDISABLE_TIMEOUT
++# define gcvQUEUE_TIMEOUT ~0
++#else
++# define gcvQUEUE_TIMEOUT 10
++#endif
++
++
++/******************************************************************************\
++********************************** Definitions *********************************
++\******************************************************************************/
++
++/* Minimum buffer size. */
++#define gcvMINUMUM_BUFFER \
++ gcmSIZEOF(gcsKERNEL_QUEUE_HEADER) + \
++ gcmSIZEOF(gcsKERNEL_CMDQUEUE) * 2
++
++#define gcmDECLARE_INTERRUPT_HANDLER(Block, Number) \
++ static gceSTATUS \
++ _EventHandler_##Block##_##Number( \
++ IN gckVGKERNEL Kernel \
++ )
++
++#define gcmDEFINE_INTERRUPT_HANDLER(Block, Number) \
++ gcmDECLARE_INTERRUPT_HANDLER(Block, Number) \
++ { \
++ return _EventHandler_Block( \
++ Kernel, \
++ &Kernel->command->taskTable[gcvBLOCK_##Block], \
++ gcvFALSE \
++ ); \
++ }
++
++#define gcmDEFINE_INTERRUPT_HANDLER_ENTRY(Block, Number) \
++ { gcvBLOCK_##Block, _EventHandler_##Block##_##Number }
++
++/* Block interrupt handling table entry. */
++typedef struct _gcsBLOCK_INTERRUPT_HANDLER * gcsBLOCK_INTERRUPT_HANDLER_PTR;
++typedef struct _gcsBLOCK_INTERRUPT_HANDLER
++{
++ gceBLOCK block;
++ gctINTERRUPT_HANDLER handler;
++}
++gcsBLOCK_INTERRUPT_HANDLER;
++
++/* Queue control functions. */
++typedef struct _gcsQUEUE_UPDATE_CONTROL * gcsQUEUE_UPDATE_CONTROL_PTR;
++typedef struct _gcsQUEUE_UPDATE_CONTROL
++{
++ gctOBJECT_HANDLER execute;
++ gctOBJECT_HANDLER update;
++ gctOBJECT_HANDLER lastExecute;
++ gctOBJECT_HANDLER lastUpdate;
++}
++gcsQUEUE_UPDATE_CONTROL;
++
++
++/******************************************************************************\
++********************************* Support Code *********************************
++\******************************************************************************/
++static gceSTATUS
++_FlushMMU(
++ IN gckVGCOMMAND Command
++ )
++{
++ gceSTATUS status;
++ gctUINT32 oldValue;
++ gckVGHARDWARE hardware = Command->hardware;
++
++ gcmkONERROR(gckOS_AtomicExchange(Command->os,
++ hardware->pageTableDirty,
++ 0,
++ &oldValue));
++
++ if (oldValue)
++ {
++ /* Page Table is upated, flush mmu before commit. */
++ gcmkONERROR(gckVGHARDWARE_FlushMMU(hardware));
++ }
++
++ return gcvSTATUS_OK;
++OnError:
++ return status;
++}
++
++static gceSTATUS
++_WaitForIdle(
++ IN gckVGCOMMAND Command,
++ IN gcsKERNEL_QUEUE_HEADER_PTR Queue
++ )
++{
++ gceSTATUS status = gcvSTATUS_OK;
++ gctUINT32 idle;
++ gctUINT timeout = 0;
++
++ /* Loop while not idle. */
++ while (Queue->pending)
++ {
++ /* Did we reach the timeout limit? */
++ if (timeout == gcvQUEUE_TIMEOUT)
++ {
++ /* Hardware is probably dead... */
++ return gcvSTATUS_TIMEOUT;
++ }
++
++ /* Sleep for 100ms. */
++ gcmkERR_BREAK(gckOS_Delay(Command->os, 100));
++
++ /* Not the first loop? */
++ if (timeout > 0)
++ {
++ /* Read IDLE register. */
++ gcmkVERIFY_OK(gckVGHARDWARE_GetIdle(Command->hardware, &idle));
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_COMMAND,
++ "%s: timeout, IDLE=%08X\n",
++ __FUNCTION__, idle
++ );
++ }
++
++ /* Increment the timeout counter. */
++ timeout += 1;
++ }
++
++ /* Return status. */
++ return status;
++}
++
++static gctINT32
++_GetNextInterrupt(
++ IN gckVGCOMMAND Command,
++ IN gceBLOCK Block
++ )
++{
++ gctUINT index;
++ gcsBLOCK_TASK_ENTRY_PTR entry;
++ gctINT32 interrupt;
++
++ /* Get the block entry. */
++ entry = &Command->taskTable[Block];
++
++ /* Make sure we have initialized interrupts. */
++ gcmkASSERT(entry->interruptCount > 0);
++
++ /* Decrement the interrupt usage semaphore. */
++ gcmkVERIFY_OK(gckOS_DecrementSemaphore(
++ Command->os, entry->interruptSemaphore
++ ));
++
++ /* Get the value index. */
++ index = entry->interruptIndex;
++
++ /* Get the interrupt value. */
++ interrupt = entry->interruptArray[index];
++
++ /* Must be a valid value. */
++ gcmkASSERT((interrupt >= 0) && (interrupt <= 31));
++
++ /* Advance the index to the next value. */
++ index += 1;
++
++ /* Set the new index. */
++ entry->interruptIndex = (index == entry->interruptCount)
++ ? 0
++ : index;
++
++ /* Return interrupt value. */
++ return interrupt;
++}
++
++
++/******************************************************************************\
++***************************** Task Storage Management **************************
++\******************************************************************************/
++
++/* Minimum task buffer size. */
++#define gcvMIN_TASK_BUFFER \
++( \
++ gcmSIZEOF(gcsTASK_CONTAINER) + 128 \
++)
++
++/* Free list terminator. */
++#define gcvFREE_TASK_TERMINATOR \
++( \
++ (gcsTASK_CONTAINER_PTR) gcmINT2PTR(~0) \
++)
++
++
++/*----------------------------------------------------------------------------*/
++/*------------------- Allocated Task Buffer List Management ------------------*/
++
++static void
++_InsertTaskBuffer(
++ IN gcsTASK_CONTAINER_PTR AddAfter,
++ IN gcsTASK_CONTAINER_PTR Buffer
++ )
++{
++ gcsTASK_CONTAINER_PTR addBefore;
++
++ /* Cannot add before the first buffer. */
++ gcmkASSERT(AddAfter != gcvNULL);
++
++ /* Create a shortcut to the next buffer. */
++ addBefore = AddAfter->allocNext;
++
++ /* Initialize the links. */
++ Buffer->allocPrev = AddAfter;
++ Buffer->allocNext = addBefore;
++
++ /* Link to the previous buffer. */
++ AddAfter->allocNext = Buffer;
++
++ /* Link to the next buffer. */
++ if (addBefore != gcvNULL)
++ {
++ addBefore->allocPrev = Buffer;
++ }
++}
++
++static void
++_RemoveTaskBuffer(
++ IN gcsTASK_CONTAINER_PTR Buffer
++ )
++{
++ gcsTASK_CONTAINER_PTR prev;
++ gcsTASK_CONTAINER_PTR next;
++
++ /* Cannot remove the first buffer. */
++ gcmkASSERT(Buffer->allocPrev != gcvNULL);
++
++ /* Create shortcuts to the previous and next buffers. */
++ prev = Buffer->allocPrev;
++ next = Buffer->allocNext;
++
++ /* Tail buffer? */
++ if (next == gcvNULL)
++ {
++ /* Remove from the list. */
++ prev->allocNext = gcvNULL;
++ }
++
++ /* Buffer from the middle. */
++ else
++ {
++ prev->allocNext = next;
++ next->allocPrev = prev;
++ }
++}
++
++
++/*----------------------------------------------------------------------------*/
++/*--------------------- Free Task Buffer List Management ---------------------*/
++
++static void
++_AppendToFreeList(
++ IN gckVGCOMMAND Command,
++ IN gcsTASK_CONTAINER_PTR Buffer
++ )
++{
++ /* Cannot be a part of the free list already. */
++ gcmkASSERT(Buffer->freePrev == gcvNULL);
++ gcmkASSERT(Buffer->freeNext == gcvNULL);
++
++ /* First buffer to add? */
++ if (Command->taskFreeHead == gcvNULL)
++ {
++ /* Terminate the links. */
++ Buffer->freePrev = gcvFREE_TASK_TERMINATOR;
++ Buffer->freeNext = gcvFREE_TASK_TERMINATOR;
++
++ /* Initialize the list pointer. */
++ Command->taskFreeHead = Command->taskFreeTail = Buffer;
++ }
++
++ /* Not the first, add after the tail. */
++ else
++ {
++ /* Initialize the new tail buffer. */
++ Buffer->freePrev = Command->taskFreeTail;
++ Buffer->freeNext = gcvFREE_TASK_TERMINATOR;
++
++ /* Add after the tail. */
++ Command->taskFreeTail->freeNext = Buffer;
++ Command->taskFreeTail = Buffer;
++ }
++}
++
++static void
++_RemoveFromFreeList(
++ IN gckVGCOMMAND Command,
++ IN gcsTASK_CONTAINER_PTR Buffer
++ )
++{
++ /* Has to be a part of the free list. */
++ gcmkASSERT(Buffer->freePrev != gcvNULL);
++ gcmkASSERT(Buffer->freeNext != gcvNULL);
++
++ /* Head buffer? */
++ if (Buffer->freePrev == gcvFREE_TASK_TERMINATOR)
++ {
++ /* Tail buffer as well? */
++ if (Buffer->freeNext == gcvFREE_TASK_TERMINATOR)
++ {
++ /* Reset the list pointer. */
++ Command->taskFreeHead = Command->taskFreeTail = gcvNULL;
++ }
++
++ /* No, just the head. */
++ else
++ {
++ /* Update the head. */
++ Command->taskFreeHead = Buffer->freeNext;
++
++ /* Terminate the next buffer. */
++ Command->taskFreeHead->freePrev = gcvFREE_TASK_TERMINATOR;
++ }
++ }
++
++ /* Not the head. */
++ else
++ {
++ /* Tail buffer? */
++ if (Buffer->freeNext == gcvFREE_TASK_TERMINATOR)
++ {
++ /* Update the tail. */
++ Command->taskFreeTail = Buffer->freePrev;
++
++ /* Terminate the previous buffer. */
++ Command->taskFreeTail->freeNext = gcvFREE_TASK_TERMINATOR;
++ }
++
++ /* A buffer in the middle. */
++ else
++ {
++ /* Remove the buffer from the list. */
++ Buffer->freePrev->freeNext = Buffer->freeNext;
++ Buffer->freeNext->freePrev = Buffer->freePrev;
++ }
++ }
++
++ /* Reset free list pointers. */
++ Buffer->freePrev = gcvNULL;
++ Buffer->freeNext = gcvNULL;
++}
++
++
++/*----------------------------------------------------------------------------*/
++/*-------------------------- Task Buffer Allocation --------------------------*/
++
++static void
++_SplitTaskBuffer(
++ IN gckVGCOMMAND Command,
++ IN gcsTASK_CONTAINER_PTR Buffer,
++ IN gctUINT Size
++ )
++{
++ /* Determine the size of the new buffer. */
++ gctINT splitBufferSize = Buffer->size - Size;
++ gcmkASSERT(splitBufferSize >= 0);
++
++ /* Is the split buffer big enough to become a separate buffer? */
++ if (splitBufferSize >= gcvMIN_TASK_BUFFER)
++ {
++ /* Place the new path data. */
++ gcsTASK_CONTAINER_PTR splitBuffer = (gcsTASK_CONTAINER_PTR)
++ (
++ (gctUINT8_PTR) Buffer + Size
++ );
++
++ /* Set the trimmed buffer size. */
++ Buffer->size = Size;
++
++ /* Initialize the split buffer. */
++ splitBuffer->referenceCount = 0;
++ splitBuffer->size = splitBufferSize;
++ splitBuffer->freePrev = gcvNULL;
++ splitBuffer->freeNext = gcvNULL;
++
++ /* Link in. */
++ _InsertTaskBuffer(Buffer, splitBuffer);
++ _AppendToFreeList(Command, splitBuffer);
++ }
++}
++
++static gceSTATUS
++_AllocateTaskContainer(
++ IN gckVGCOMMAND Command,
++ IN gctUINT Size,
++ OUT gcsTASK_CONTAINER_PTR * Buffer
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Command=0x%x Size=0x%x, Buffer ==0x%x", Command, Size, Buffer);
++
++ /* Verify arguments. */
++ gcmkVERIFY_ARGUMENT(Buffer != gcvNULL);
++
++ do
++ {
++ gcsTASK_STORAGE_PTR storage;
++ gcsTASK_CONTAINER_PTR buffer;
++
++ /* Adjust the size. */
++ Size += gcmSIZEOF(gcsTASK_CONTAINER);
++
++ /* Adjust the allocation size if not big enough. */
++ if (Size > Command->taskStorageUsable)
++ {
++ Command->taskStorageGranularity
++ = gcmALIGN(Size + gcmSIZEOF(gcsTASK_STORAGE), 1024);
++
++ Command->taskStorageUsable
++ = Command->taskStorageGranularity - gcmSIZEOF(gcsTASK_STORAGE);
++ }
++
++ /* Is there a free buffer available? */
++ else if (Command->taskFreeHead != gcvNULL)
++ {
++ /* Set the initial free buffer. */
++ gcsTASK_CONTAINER_PTR buffer = Command->taskFreeHead;
++
++ do
++ {
++ /* Is the buffer big enough? */
++ if (buffer->size >= Size)
++ {
++ /* Remove the buffer from the free list. */
++ _RemoveFromFreeList(Command, buffer);
++
++ /* Split the buffer. */
++ _SplitTaskBuffer(Command, buffer, Size);
++
++ /* Set the result. */
++ * Buffer = buffer;
++
++ gcmkFOOTER_ARG("*Buffer=0x%x",*Buffer);
++ /* Success. */
++ return gcvSTATUS_OK;
++ }
++
++ /* Get the next free buffer. */
++ buffer = buffer->freeNext;
++ }
++ while (buffer != gcvFREE_TASK_TERMINATOR);
++ }
++
++ /* Allocate a container. */
++ gcmkERR_BREAK(gckOS_Allocate(
++ Command->os,
++ Command->taskStorageGranularity,
++ (gctPOINTER *) &storage
++ ));
++
++ /* Link in the storage buffer. */
++ storage->next = Command->taskStorage;
++ Command->taskStorage = storage;
++
++ /* Place the task buffer. */
++ buffer = (gcsTASK_CONTAINER_PTR) (storage + 1);
++
++ /* Determine the size of the buffer. */
++ buffer->size
++ = Command->taskStorageGranularity
++ - gcmSIZEOF(gcsTASK_STORAGE);
++
++ /* Initialize the task buffer. */
++ buffer->referenceCount = 0;
++ buffer->allocPrev = gcvNULL;
++ buffer->allocNext = gcvNULL;
++ buffer->freePrev = gcvNULL;
++ buffer->freeNext = gcvNULL;
++
++ /* Split the buffer. */
++ _SplitTaskBuffer(Command, buffer, Size);
++
++ /* Set the result. */
++ * Buffer = buffer;
++
++ gcmkFOOTER_ARG("*Buffer=0x%x",*Buffer);
++ /* Success. */
++ return gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ gcmkFOOTER();
++ /* Return status. */
++ return status;
++}
++
++static void
++_FreeTaskContainer(
++ IN gckVGCOMMAND Command,
++ IN gcsTASK_CONTAINER_PTR Buffer
++ )
++{
++ gcsTASK_CONTAINER_PTR prev;
++ gcsTASK_CONTAINER_PTR next;
++ gcsTASK_CONTAINER_PTR merged;
++
++ gctSIZE_T mergedSize;
++
++ /* Verify arguments. */
++ gcmkASSERT(Buffer != gcvNULL);
++ gcmkASSERT(Buffer->freePrev == gcvNULL);
++ gcmkASSERT(Buffer->freeNext == gcvNULL);
++
++ /* Get shortcuts to the previous and next path data buffers. */
++ prev = Buffer->allocPrev;
++ next = Buffer->allocNext;
++
++ /* Is the previous path data buffer already free? */
++ if (prev && prev->freeNext)
++ {
++ /* The previous path data buffer is the one that remains. */
++ merged = prev;
++
++ /* Is the next path data buffer already free? */
++ if (next && next->freeNext)
++ {
++ /* Merge all three path data buffers into the previous. */
++ mergedSize = prev->size + Buffer->size + next->size;
++
++ /* Remove the next path data buffer. */
++ _RemoveFromFreeList(Command, next);
++ _RemoveTaskBuffer(next);
++ }
++ else
++ {
++ /* Merge the current path data buffer into the previous. */
++ mergedSize = prev->size + Buffer->size;
++ }
++
++ /* Delete the current path data buffer. */
++ _RemoveTaskBuffer(Buffer);
++
++ /* Set new size. */
++ merged->size = mergedSize;
++ }
++ else
++ {
++ /* The current path data buffer is the one that remains. */
++ merged = Buffer;
++
++ /* Is the next buffer already free? */
++ if (next && next->freeNext)
++ {
++ /* Merge the next into the current. */
++ mergedSize = Buffer->size + next->size;
++
++ /* Remove the next buffer. */
++ _RemoveFromFreeList(Command, next);
++ _RemoveTaskBuffer(next);
++
++ /* Set new size. */
++ merged->size = mergedSize;
++ }
++
++ /* Add the current buffer into the free list. */
++ _AppendToFreeList(Command, merged);
++ }
++}
++
++gceSTATUS
++_RemoveRecordFromProcesDB(
++ IN gckVGCOMMAND Command,
++ IN gcsTASK_HEADER_PTR Task
++ )
++{
++ gcsTASK_PTR task = (gcsTASK_PTR)((gctUINT8_PTR)Task - sizeof(gcsTASK));
++ gcsTASK_FREE_VIDEO_MEMORY_PTR freeVideoMemory;
++ gcsTASK_UNLOCK_VIDEO_MEMORY_PTR unlockVideoMemory;
++ gctINT pid;
++ gctUINT32 size;
++
++ /* Get the total size of all tasks. */
++ size = task->size;
++
++ gcmkVERIFY_OK(gckOS_GetProcessID((gctUINT32_PTR)&pid));
++
++ do
++ {
++ switch (Task->id)
++ {
++ case gcvTASK_FREE_VIDEO_MEMORY:
++ freeVideoMemory = (gcsTASK_FREE_VIDEO_MEMORY_PTR)Task;
++
++ /* Remove record from process db. */
++ gcmkVERIFY_OK(gckKERNEL_RemoveProcessDB(
++ Command->kernel->kernel,
++ pid,
++ gcvDB_VIDEO_MEMORY,
++ gcmUINT64_TO_PTR(freeVideoMemory->node)));
++
++ /* Advance to next task. */
++ size -= sizeof(gcsTASK_FREE_VIDEO_MEMORY);
++ Task = (gcsTASK_HEADER_PTR)(freeVideoMemory + 1);
++
++ break;
++ case gcvTASK_UNLOCK_VIDEO_MEMORY:
++ unlockVideoMemory = (gcsTASK_UNLOCK_VIDEO_MEMORY_PTR)Task;
++
++ /* Remove record from process db. */
++ gcmkVERIFY_OK(gckKERNEL_RemoveProcessDB(
++ Command->kernel->kernel,
++ pid,
++ gcvDB_VIDEO_MEMORY_LOCKED,
++ gcmUINT64_TO_PTR(unlockVideoMemory->node)));
++
++ /* Advance to next task. */
++ size -= sizeof(gcsTASK_UNLOCK_VIDEO_MEMORY);
++ Task = (gcsTASK_HEADER_PTR)(unlockVideoMemory + 1);
++
++ break;
++ default:
++ /* Skip the whole task. */
++ size = 0;
++ break;
++ }
++ }
++ while(size);
++
++ return gcvSTATUS_OK;
++}
++
++/******************************************************************************\
++********************************* Task Scheduling ******************************
++\******************************************************************************/
++
++static gceSTATUS
++_ScheduleTasks(
++ IN gckVGCOMMAND Command,
++ IN gcsTASK_MASTER_TABLE_PTR TaskTable,
++ IN gctUINT8_PTR PreviousEnd
++ )
++{
++ gceSTATUS status;
++
++ do
++ {
++ gctINT block;
++ gcsTASK_CONTAINER_PTR container;
++ gcsTASK_MASTER_ENTRY_PTR userTaskEntry;
++ gcsBLOCK_TASK_ENTRY_PTR kernelTaskEntry;
++ gcsTASK_PTR userTask;
++ gctUINT8_PTR kernelTask;
++ gctINT32 interrupt;
++ gctUINT8_PTR eventCommand;
++
++ /* Nothing to schedule? */
++ if (TaskTable->size == 0)
++ {
++ status = gcvSTATUS_OK;
++ break;
++ }
++
++ /* Acquire the mutex. */
++ gcmkERR_BREAK(gckOS_AcquireMutex(
++ Command->os,
++ Command->taskMutex,
++ gcvINFINITE
++ ));
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ "%s(%d)\n",
++ __FUNCTION__, __LINE__
++ );
++
++ do
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ " number of tasks scheduled = %d\n"
++ " size of event data in bytes = %d\n",
++ TaskTable->count,
++ TaskTable->size
++ );
++
++ /* Allocate task buffer. */
++ gcmkERR_BREAK(_AllocateTaskContainer(
++ Command,
++ TaskTable->size,
++ &container
++ ));
++
++ /* Determine the task data pointer. */
++ kernelTask = (gctUINT8_PTR) (container + 1);
++
++ /* Initialize the reference count. */
++ container->referenceCount = TaskTable->count;
++
++ /* Process tasks. */
++ for (block = gcvBLOCK_COUNT - 1; block >= 0; block -= 1)
++ {
++ /* Get the current user table entry. */
++ userTaskEntry = &TaskTable->table[block];
++
++ /* Are there tasks scheduled? */
++ if (userTaskEntry->head == gcvNULL)
++ {
++ /* No, skip to the next block. */
++ continue;
++ }
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ " processing tasks for block %d\n",
++ block
++ );
++
++ /* Get the current kernel table entry. */
++ kernelTaskEntry = &Command->taskTable[block];
++
++ /* Are there tasks for the current block scheduled? */
++ if (kernelTaskEntry->container == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ " first task container for the block added\n",
++ block
++ );
++
++ /* Nothing yet, set the container buffer pointer. */
++ kernelTaskEntry->container = container;
++ kernelTaskEntry->task = (gcsTASK_HEADER_PTR) kernelTask;
++ }
++
++ /* Yes, append to the end. */
++ else
++ {
++ kernelTaskEntry->link->cotainer = container;
++ kernelTaskEntry->link->task = (gcsTASK_HEADER_PTR) kernelTask;
++ }
++
++ /* Set initial task. */
++ userTask = userTaskEntry->head;
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ " copying user tasks over to the kernel\n"
++ );
++
++ /* Copy tasks. */
++ do
++ {
++ gcsTASK_HEADER_PTR taskHeader = (gcsTASK_HEADER_PTR) (userTask + 1);
++
++ gcmkVERIFY_OK(_RemoveRecordFromProcesDB(Command, taskHeader));
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ " task ID = %d, size = %d\n",
++ ((gcsTASK_HEADER_PTR) (userTask + 1))->id,
++ userTask->size
++ );
++
++#ifdef __QNXNTO__
++ if (taskHeader->id == gcvTASK_SIGNAL)
++ {
++ ((gcsTASK_SIGNAL_PTR)taskHeader)->coid = TaskTable->coid;
++ ((gcsTASK_SIGNAL_PTR)taskHeader)->rcvid = TaskTable->rcvid;
++ }
++#endif /* __QNXNTO__ */
++ /* Copy the task data. */
++ gcmkVERIFY_OK(gckOS_MemCopy(
++ kernelTask, taskHeader, userTask->size
++ ));
++
++ /* Advance to the next task. */
++ kernelTask += userTask->size;
++ userTask = userTask->next;
++ }
++ while (userTask != gcvNULL);
++
++ /* Update link pointer in the header. */
++ kernelTaskEntry->link = (gcsTASK_LINK_PTR) kernelTask;
++
++ /* Initialize link task. */
++ kernelTaskEntry->link->id = gcvTASK_LINK;
++ kernelTaskEntry->link->cotainer = gcvNULL;
++ kernelTaskEntry->link->task = gcvNULL;
++
++ /* Advance the task data pointer. */
++ kernelTask += gcmSIZEOF(gcsTASK_LINK);
++ }
++ }
++ while (gcvFALSE);
++
++ /* Release the mutex. */
++ gcmkERR_BREAK(gckOS_ReleaseMutex(
++ Command->os,
++ Command->taskMutex
++ ));
++
++ /* Assign interrupts to the blocks. */
++ eventCommand = PreviousEnd;
++
++ for (block = gcvBLOCK_COUNT - 1; block >= 0; block -= 1)
++ {
++ /* Get the current user table entry. */
++ userTaskEntry = &TaskTable->table[block];
++
++ /* Are there tasks scheduled? */
++ if (userTaskEntry->head == gcvNULL)
++ {
++ /* No, skip to the next block. */
++ continue;
++ }
++
++ /* Get the interrupt number. */
++ interrupt = _GetNextInterrupt(Command, block);
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ "%s(%d): block = %d interrupt = %d\n",
++ __FUNCTION__, __LINE__,
++ block, interrupt
++ );
++
++ /* Determine the command position. */
++ eventCommand -= Command->info.eventCommandSize;
++
++ /* Append an EVENT command. */
++ gcmkERR_BREAK(gckVGCOMMAND_EventCommand(
++ Command, eventCommand, block, interrupt, gcvNULL
++ ));
++ }
++ }
++ while (gcvFALSE);
++
++ /* Return status. */
++ return status;
++}
++
++
++/******************************************************************************\
++******************************** Memory Management *****************************
++\******************************************************************************/
++
++static gceSTATUS
++_HardwareToKernel(
++ IN gckOS Os,
++ IN gcuVIDMEM_NODE_PTR Node,
++ IN gctUINT32 Address,
++ OUT gctPOINTER * KernelPointer
++ )
++{
++ gceSTATUS status;
++ gckVIDMEM memory;
++ gctUINT32 offset;
++#if gcdDYNAMIC_MAP_RESERVED_MEMORY
++ gctUINT32 nodePhysical;
++#endif
++ status = gcvSTATUS_OK;
++ /* Assume a non-virtual node and get the pool manager object. */
++ memory = Node->VidMem.memory;
++
++#if gcdDYNAMIC_MAP_RESERVED_MEMORY
++ nodePhysical = memory->baseAddress
++ + Node->VidMem.offset
++ + Node->VidMem.alignment;
++
++ if (Node->VidMem.kernelVirtual == gcvNULL)
++ {
++ status = gckOS_MapPhysical(Os,
++ nodePhysical,
++ Node->VidMem.bytes,
++ (gctPOINTER *)&Node->VidMem.kernelVirtual);
++
++ if (gcmkIS_ERROR(status))
++ {
++ return status;
++ }
++ }
++
++ offset = Address - nodePhysical;
++ *KernelPointer = (gctPOINTER)((gctUINT8_PTR)Node->VidMem.kernelVirtual + offset);
++#else
++ /* Determine the header offset within the pool it is allocated in. */
++ offset = Address - memory->baseAddress;
++
++ /* Translate the offset into the kernel side pointer. */
++ status = gckOS_GetKernelLogicalEx(
++ Os,
++ gcvCORE_VG,
++ offset,
++ KernelPointer
++ );
++#endif
++
++ /* Return status. */
++ return status;
++}
++
++static gceSTATUS
++_ConvertUserCommandBufferPointer(
++ IN gckVGCOMMAND Command,
++ IN gcsCMDBUFFER_PTR UserCommandBuffer,
++ OUT gcsCMDBUFFER_PTR * KernelCommandBuffer
++ )
++{
++ gceSTATUS status, last;
++ gcsCMDBUFFER_PTR mappedUserCommandBuffer = gcvNULL;
++
++ do
++ {
++ gctUINT32 headerAddress;
++
++ /* Map the command buffer structure into the kernel space. */
++ gcmkERR_BREAK(gckOS_MapUserPointer(
++ Command->os,
++ UserCommandBuffer,
++ gcmSIZEOF(gcsCMDBUFFER),
++ (gctPOINTER *) &mappedUserCommandBuffer
++ ));
++
++ /* Determine the address of the header. */
++ headerAddress
++ = mappedUserCommandBuffer->address
++ - mappedUserCommandBuffer->bufferOffset;
++
++ /* Translate the logical address to the kernel space. */
++ gcmkERR_BREAK(_HardwareToKernel(
++ Command->os,
++ gcmUINT64_TO_PTR(mappedUserCommandBuffer->node),
++ headerAddress,
++ (gctPOINTER *) KernelCommandBuffer
++ ));
++ }
++ while (gcvFALSE);
++
++ /* Unmap the user command buffer. */
++ if (mappedUserCommandBuffer != gcvNULL)
++ {
++ gcmkCHECK_STATUS(gckOS_UnmapUserPointer(
++ Command->os,
++ UserCommandBuffer,
++ gcmSIZEOF(gcsCMDBUFFER),
++ mappedUserCommandBuffer
++ ));
++ }
++
++ /* Return status. */
++ return status;
++}
++
++static gceSTATUS
++_AllocateLinear(
++ IN gckVGCOMMAND Command,
++ IN gctUINT Size,
++ IN gctUINT Alignment,
++ OUT gcuVIDMEM_NODE_PTR * Node,
++ OUT gctUINT32 * Address,
++ OUT gctPOINTER * Logical
++ )
++{
++ gceSTATUS status, last;
++ gcuVIDMEM_NODE_PTR node = gcvNULL;
++ gctUINT32 address = (gctUINT32)~0;
++
++ do
++ {
++ gcePOOL pool;
++ gctPOINTER logical;
++
++ /* Allocate from the system pool. */
++ pool = gcvPOOL_SYSTEM;
++
++ /* Allocate memory. */
++ gcmkERR_BREAK(gckKERNEL_AllocateLinearMemory(
++ Command->kernel->kernel, &pool,
++ Size, Alignment,
++ gcvSURF_TYPE_UNKNOWN,
++ &node
++ ));
++
++ /* Do not accept virtual pools for now because we don't handle the
++ kernel pointer translation at the moment. */
++ if (pool == gcvPOOL_VIRTUAL)
++ {
++ status = gcvSTATUS_OUT_OF_MEMORY;
++ break;
++ }
++
++ /* Lock the command buffer. */
++ gcmkERR_BREAK(gckVIDMEM_Lock(
++ Command->kernel->kernel,
++ node,
++ gcvFALSE,
++ &address
++ ));
++
++ /* Translate the logical address to the kernel space. */
++ gcmkERR_BREAK(_HardwareToKernel(
++ Command->os,
++ node,
++ address,
++ &logical
++ ));
++
++ /* Set return values. */
++ * Node = node;
++ * Address = address;
++ * Logical = logical;
++
++ /* Success. */
++ return gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ /* Roll back. */
++ if (node != gcvNULL)
++ {
++ /* Unlock the command buffer. */
++ if (address != ~0)
++ {
++ gcmkCHECK_STATUS(gckVIDMEM_Unlock(
++ Command->kernel->kernel, node, gcvSURF_TYPE_UNKNOWN, gcvNULL
++ ));
++ }
++
++ /* Free the command buffer. */
++ gcmkCHECK_STATUS(gckVIDMEM_Free(
++ Command->kernel->kernel,
++ node
++ ));
++ }
++
++ /* Return status. */
++ return status;
++}
++
++static gceSTATUS
++_FreeLinear(
++ IN gckVGKERNEL Kernel,
++ IN gcuVIDMEM_NODE_PTR Node
++ )
++{
++ gceSTATUS status;
++
++ do
++ {
++ /* Unlock the linear buffer. */
++ gcmkERR_BREAK(gckVIDMEM_Unlock(Kernel->kernel, Node, gcvSURF_TYPE_UNKNOWN, gcvNULL));
++
++ /* Free the linear buffer. */
++ gcmkERR_BREAK(gckVIDMEM_Free(Kernel->kernel, Node));
++ }
++ while (gcvFALSE);
++
++ /* Return status. */
++ return status;
++}
++
++gceSTATUS
++_AllocateCommandBuffer(
++ IN gckVGCOMMAND Command,
++ IN gctSIZE_T Size,
++ OUT gcsCMDBUFFER_PTR * CommandBuffer
++ )
++{
++ gceSTATUS status, last;
++ gcuVIDMEM_NODE_PTR node = gcvNULL;
++
++ do
++ {
++ gctUINT alignedHeaderSize;
++ gctUINT requestedSize;
++ gctUINT allocationSize;
++ gctUINT32 address = 0;
++ gcsCMDBUFFER_PTR commandBuffer;
++ gctUINT8_PTR endCommand;
++
++ /* Determine the aligned header size. */
++ alignedHeaderSize
++ = gcmALIGN(gcmSIZEOF(gcsCMDBUFFER), Command->info.addressAlignment);
++
++ /* Align the requested size. */
++ requestedSize
++ = gcmALIGN(Size, Command->info.commandAlignment);
++
++ /* Determine the size of the buffer to allocate. */
++ allocationSize
++ = alignedHeaderSize
++ + requestedSize
++ + Command->info.staticTailSize;
++
++ /* Allocate the command buffer. */
++ gcmkERR_BREAK(_AllocateLinear(
++ Command,
++ allocationSize,
++ Command->info.addressAlignment,
++ &node,
++ &address,
++ (gctPOINTER *) &commandBuffer
++ ));
++
++ /* Initialize the structure. */
++ commandBuffer->completion = gcvVACANT_BUFFER;
++ commandBuffer->node = gcmPTR_TO_UINT64(node);
++ commandBuffer->address = address + alignedHeaderSize;
++ commandBuffer->bufferOffset = alignedHeaderSize;
++ commandBuffer->size = requestedSize;
++ commandBuffer->offset = requestedSize;
++ commandBuffer->nextAllocated = gcvNULL;
++ commandBuffer->nextSubBuffer = gcvNULL;
++
++ /* Determine the data count. */
++ commandBuffer->dataCount
++ = (requestedSize + Command->info.staticTailSize)
++ / Command->info.commandAlignment;
++
++ /* Determine the location of the END command. */
++ endCommand
++ = (gctUINT8_PTR) commandBuffer
++ + alignedHeaderSize
++ + requestedSize;
++
++ /* Append an END command. */
++ gcmkERR_BREAK(gckVGCOMMAND_EndCommand(
++ Command,
++ endCommand,
++ Command->info.feBufferInt,
++ gcvNULL
++ ));
++
++ /* Set the return pointer. */
++ * CommandBuffer = commandBuffer;
++
++ /* Success. */
++ return gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ /* Roll back. */
++ if (node != gcvNULL)
++ {
++ /* Free the command buffer. */
++ gcmkCHECK_STATUS(_FreeLinear(Command->kernel, node));
++ }
++
++ /* Return status. */
++ return status;
++}
++
++static gceSTATUS
++_FreeCommandBuffer(
++ IN gckVGKERNEL Kernel,
++ IN gcsCMDBUFFER_PTR CommandBuffer
++ )
++{
++ gceSTATUS status;
++
++ /* Free the buffer. */
++ status = _FreeLinear(Kernel, gcmUINT64_TO_PTR(CommandBuffer->node));
++
++ /* Return status. */
++ return status;
++}
++
++
++/******************************************************************************\
++****************************** TS Overflow Handler *****************************
++\******************************************************************************/
++
++static gceSTATUS
++_EventHandler_TSOverflow(
++ IN gckVGKERNEL Kernel
++ )
++{
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): **** TS OVERFLOW ENCOUNTERED ****\n",
++ __FUNCTION__, __LINE__
++ );
++
++ return gcvSTATUS_OK;
++}
++
++
++/******************************************************************************\
++****************************** Bus Error Handler *******************************
++\******************************************************************************/
++
++static gceSTATUS
++_EventHandler_BusError(
++ IN gckVGKERNEL Kernel
++ )
++{
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): **** BUS ERROR ENCOUNTERED ****\n",
++ __FUNCTION__, __LINE__
++ );
++
++ return gcvSTATUS_OK;
++}
++
++/******************************************************************************\
++****************************** Power Stall Handler *******************************
++\******************************************************************************/
++
++static gceSTATUS
++_EventHandler_PowerStall(
++ IN gckVGKERNEL Kernel
++ )
++{
++ /* Signal. */
++ return gckOS_Signal(
++ Kernel->os,
++ Kernel->command->powerStallSignal,
++ gcvTRUE);
++}
++
++/******************************************************************************\
++******************************** Task Routines *********************************
++\******************************************************************************/
++
++typedef gceSTATUS (* gctTASKROUTINE) (
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ );
++
++static gceSTATUS
++_TaskLink(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ );
++
++static gceSTATUS
++_TaskCluster(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ );
++
++static gceSTATUS
++_TaskIncrement(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ );
++
++static gceSTATUS
++_TaskDecrement(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ );
++
++static gceSTATUS
++_TaskSignal(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ );
++
++static gceSTATUS
++_TaskLockdown(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ );
++
++static gceSTATUS
++_TaskUnlockVideoMemory(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ );
++
++static gceSTATUS
++_TaskFreeVideoMemory(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ );
++
++static gceSTATUS
++_TaskFreeContiguousMemory(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ );
++
++static gceSTATUS
++_TaskUnmapUserMemory(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ );
++
++static gctTASKROUTINE _taskRoutine[] =
++{
++ _TaskLink, /* gcvTASK_LINK */
++ _TaskCluster, /* gcvTASK_CLUSTER */
++ _TaskIncrement, /* gcvTASK_INCREMENT */
++ _TaskDecrement, /* gcvTASK_DECREMENT */
++ _TaskSignal, /* gcvTASK_SIGNAL */
++ _TaskLockdown, /* gcvTASK_LOCKDOWN */
++ _TaskUnlockVideoMemory, /* gcvTASK_UNLOCK_VIDEO_MEMORY */
++ _TaskFreeVideoMemory, /* gcvTASK_FREE_VIDEO_MEMORY */
++ _TaskFreeContiguousMemory, /* gcvTASK_FREE_CONTIGUOUS_MEMORY */
++ _TaskUnmapUserMemory, /* gcvTASK_UNMAP_USER_MEMORY */
++};
++
++static gceSTATUS
++_TaskLink(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ )
++{
++ /* Cast the task pointer. */
++ gcsTASK_LINK_PTR task = (gcsTASK_LINK_PTR) TaskHeader->task;
++
++ /* Save the pointer to the container. */
++ gcsTASK_CONTAINER_PTR container = TaskHeader->container;
++
++ /* No more tasks in the list? */
++ if (task->task == gcvNULL)
++ {
++ /* Reset the entry. */
++ TaskHeader->container = gcvNULL;
++ TaskHeader->task = gcvNULL;
++ TaskHeader->link = gcvNULL;
++ }
++ else
++ {
++ /* Update the entry. */
++ TaskHeader->container = task->cotainer;
++ TaskHeader->task = task->task;
++ }
++
++ /* Decrement the task buffer reference. */
++ gcmkASSERT(container->referenceCount >= 0);
++ if (container->referenceCount == 0)
++ {
++ /* Free the container. */
++ _FreeTaskContainer(Command, container);
++ }
++
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++static gceSTATUS
++_TaskCluster(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ )
++{
++ gceSTATUS status = gcvSTATUS_OK;
++
++ /* Cast the task pointer. */
++ gcsTASK_CLUSTER_PTR cluster = (gcsTASK_CLUSTER_PTR) TaskHeader->task;
++
++ /* Get the number of tasks. */
++ gctUINT taskCount = cluster->taskCount;
++
++ /* Advance to the next task. */
++ TaskHeader->task = (gcsTASK_HEADER_PTR) (cluster + 1);
++
++ /* Perform all tasks in the cluster. */
++ while (taskCount)
++ {
++ /* Perform the current task. */
++ gcmkERR_BREAK(_taskRoutine[TaskHeader->task->id](
++ Command,
++ TaskHeader
++ ));
++
++ /* Update the task count. */
++ taskCount -= 1;
++ }
++
++ /* Return status. */
++ return status;
++}
++
++static gceSTATUS
++_TaskIncrement(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ )
++{
++ gceSTATUS status;
++
++ do
++ {
++ /* Cast the task pointer. */
++ gcsTASK_INCREMENT_PTR task = (gcsTASK_INCREMENT_PTR) TaskHeader->task;
++
++ /* Convert physical into logical address. */
++ gctUINT32_PTR logical;
++ gcmkERR_BREAK(gckOS_MapPhysical(
++ Command->os,
++ task->address,
++ gcmSIZEOF(gctUINT32),
++ (gctPOINTER *) &logical
++ ));
++
++ /* Increment data. */
++ (* logical) += 1;
++
++ /* Unmap the physical memory. */
++ gcmkERR_BREAK(gckOS_UnmapPhysical(
++ Command->os,
++ logical,
++ gcmSIZEOF(gctUINT32)
++ ));
++
++ /* Update the reference counter. */
++ TaskHeader->container->referenceCount -= 1;
++
++ /* Update the task pointer. */
++ TaskHeader->task = (gcsTASK_HEADER_PTR) (task + 1);
++ }
++ while (gcvFALSE);
++
++ /* Return status. */
++ return status;
++}
++
++static gceSTATUS
++_TaskDecrement(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ )
++{
++ gceSTATUS status;
++
++ do
++ {
++ /* Cast the task pointer. */
++ gcsTASK_DECREMENT_PTR task = (gcsTASK_DECREMENT_PTR) TaskHeader->task;
++
++ /* Convert physical into logical address. */
++ gctUINT32_PTR logical;
++ gcmkERR_BREAK(gckOS_MapPhysical(
++ Command->os,
++ task->address,
++ gcmSIZEOF(gctUINT32),
++ (gctPOINTER *) &logical
++ ));
++
++ /* Decrement data. */
++ (* logical) -= 1;
++
++ /* Unmap the physical memory. */
++ gcmkERR_BREAK(gckOS_UnmapPhysical(
++ Command->os,
++ logical,
++ gcmSIZEOF(gctUINT32)
++ ));
++
++ /* Update the reference counter. */
++ TaskHeader->container->referenceCount -= 1;
++
++ /* Update the task pointer. */
++ TaskHeader->task = (gcsTASK_HEADER_PTR) (task + 1);
++ }
++ while (gcvFALSE);
++
++ /* Return status. */
++ return status;
++}
++
++static gceSTATUS
++_TaskSignal(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ )
++{
++ gceSTATUS status;
++
++ do
++ {
++ /* Cast the task pointer. */
++ gcsTASK_SIGNAL_PTR task = (gcsTASK_SIGNAL_PTR) TaskHeader->task;
++
++
++ /* Map the signal into kernel space. */
++#ifdef __QNXNTO__
++ gcmkERR_BREAK(gckOS_UserSignal(
++ Command->os, task->signal, task->rcvid, task->coid
++ ));
++#else
++ gcmkERR_BREAK(gckOS_UserSignal(
++ Command->os, task->signal, task->process
++ ));
++#endif /* __QNXNTO__ */
++
++ /* Update the reference counter. */
++ TaskHeader->container->referenceCount -= 1;
++
++ /* Update the task pointer. */
++ TaskHeader->task = (gcsTASK_HEADER_PTR) (task + 1);
++ }
++ while (gcvFALSE);
++
++ /* Return status. */
++ return status;
++}
++
++static gceSTATUS
++_TaskLockdown(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ )
++{
++ gceSTATUS status;
++ gctUINT32_PTR userCounter = gcvNULL;
++ gctUINT32_PTR kernelCounter = gcvNULL;
++ gctSIGNAL signal = gcvNULL;
++
++ do
++ {
++ /* Cast the task pointer. */
++ gcsTASK_LOCKDOWN_PTR task = (gcsTASK_LOCKDOWN_PTR) TaskHeader->task;
++
++ /* Convert physical addresses into logical. */
++ gcmkERR_BREAK(gckOS_MapPhysical(
++ Command->os,
++ task->userCounter,
++ gcmSIZEOF(gctUINT32),
++ (gctPOINTER *) &userCounter
++ ));
++
++ gcmkERR_BREAK(gckOS_MapPhysical(
++ Command->os,
++ task->kernelCounter,
++ gcmSIZEOF(gctUINT32),
++ (gctPOINTER *) &kernelCounter
++ ));
++
++ /* Update the kernel counter. */
++ (* kernelCounter) += 1;
++
++ /* Are the counters equal? */
++ if ((* userCounter) == (* kernelCounter))
++ {
++ /* Map the signal into kernel space. */
++ gcmkERR_BREAK(gckOS_MapSignal(
++ Command->os, task->signal, task->process, &signal
++ ));
++
++ if (signal == gcvNULL)
++ {
++ /* Signal. */
++ gcmkERR_BREAK(gckOS_Signal(
++ Command->os, task->signal, gcvTRUE
++ ));
++ }
++ else
++ {
++ /* Signal. */
++ gcmkERR_BREAK(gckOS_Signal(
++ Command->os, signal, gcvTRUE
++ ));
++ }
++ }
++
++ /* Update the reference counter. */
++ TaskHeader->container->referenceCount -= 1;
++
++ /* Update the task pointer. */
++ TaskHeader->task = (gcsTASK_HEADER_PTR) (task + 1);
++ }
++ while (gcvFALSE);
++
++ /* Destroy the mapped signal. */
++ if (signal != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_DestroySignal(
++ Command->os, signal
++ ));
++ }
++
++ /* Unmap the physical memory. */
++ if (kernelCounter != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_UnmapPhysical(
++ Command->os,
++ kernelCounter,
++ gcmSIZEOF(gctUINT32)
++ ));
++ }
++
++ if (userCounter != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_UnmapPhysical(
++ Command->os,
++ userCounter,
++ gcmSIZEOF(gctUINT32)
++ ));
++ }
++
++ /* Return status. */
++ return status;
++}
++
++static gceSTATUS
++_TaskUnlockVideoMemory(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ )
++{
++ gceSTATUS status;
++
++ do
++ {
++ /* Cast the task pointer. */
++ gcsTASK_UNLOCK_VIDEO_MEMORY_PTR task
++ = (gcsTASK_UNLOCK_VIDEO_MEMORY_PTR) TaskHeader->task;
++
++ /* Unlock video memory. */
++ gcmkERR_BREAK(gckVIDMEM_Unlock(
++ Command->kernel->kernel,
++ gcmUINT64_TO_PTR(task->node),
++ gcvSURF_TYPE_UNKNOWN,
++ gcvNULL));
++
++ /* Update the reference counter. */
++ TaskHeader->container->referenceCount -= 1;
++
++ /* Update the task pointer. */
++ TaskHeader->task = (gcsTASK_HEADER_PTR) (task + 1);
++ }
++ while (gcvFALSE);
++
++ /* Return status. */
++ return status;
++}
++
++static gceSTATUS
++_TaskFreeVideoMemory(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ )
++{
++ gceSTATUS status;
++
++ do
++ {
++ /* Cast the task pointer. */
++ gcsTASK_FREE_VIDEO_MEMORY_PTR task
++ = (gcsTASK_FREE_VIDEO_MEMORY_PTR) TaskHeader->task;
++
++ /* Free video memory. */
++ gcmkERR_BREAK(gckVIDMEM_Free(Command->kernel->kernel, gcmUINT64_TO_PTR(task->node)));
++
++ /* Update the reference counter. */
++ TaskHeader->container->referenceCount -= 1;
++
++ /* Update the task pointer. */
++ TaskHeader->task = (gcsTASK_HEADER_PTR) (task + 1);
++ }
++ while (gcvFALSE);
++
++ /* Return status. */
++ return status;
++}
++
++static gceSTATUS
++_TaskFreeContiguousMemory(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ )
++{
++ gceSTATUS status;
++
++ do
++ {
++ /* Cast the task pointer. */
++ gcsTASK_FREE_CONTIGUOUS_MEMORY_PTR task
++ = (gcsTASK_FREE_CONTIGUOUS_MEMORY_PTR) TaskHeader->task;
++
++ /* Free contiguous memory. */
++ gcmkERR_BREAK(gckOS_FreeContiguous(
++ Command->os, task->physical, task->logical, task->bytes
++ ));
++
++ /* Update the reference counter. */
++ TaskHeader->container->referenceCount -= 1;
++
++ /* Update the task pointer. */
++ TaskHeader->task = (gcsTASK_HEADER_PTR) (task + 1);
++ }
++ while (gcvFALSE);
++
++ /* Return status. */
++ return status;
++}
++
++static gceSTATUS
++_TaskUnmapUserMemory(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ )
++{
++ gceSTATUS status;
++
++ do
++ {
++ /* Cast the task pointer. */
++ gcsTASK_UNMAP_USER_MEMORY_PTR task
++ = (gcsTASK_UNMAP_USER_MEMORY_PTR) TaskHeader->task;
++
++ /* Unmap the user memory. */
++ gcmkERR_BREAK(gckOS_UnmapUserMemory(
++ Command->os, gcvCORE_VG, task->memory, task->size, task->info, task->address
++ ));
++
++ /* Update the reference counter. */
++ TaskHeader->container->referenceCount -= 1;
++
++ /* Update the task pointer. */
++ TaskHeader->task = (gcsTASK_HEADER_PTR) (task + 1);
++ }
++ while (gcvFALSE);
++
++ /* Return status. */
++ return status;
++}
++
++/******************************************************************************\
++************ Hardware Block Interrupt Handlers For Scheduled Events ************
++\******************************************************************************/
++
++static gceSTATUS
++_EventHandler_Block(
++ IN gckVGKERNEL Kernel,
++ IN gcsBLOCK_TASK_ENTRY_PTR TaskHeader,
++ IN gctBOOL ProcessAll
++ )
++{
++ gceSTATUS status, last;
++
++ gcmkHEADER_ARG("Kernel=0x%x TaskHeader=0x%x ProcessAll=0x%x", Kernel, TaskHeader, ProcessAll);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++
++ do
++ {
++ gckVGCOMMAND command;
++
++ /* Get the command buffer object. */
++ command = Kernel->command;
++
++ /* Increment the interrupt usage semaphore. */
++ gcmkERR_BREAK(gckOS_IncrementSemaphore(
++ command->os, TaskHeader->interruptSemaphore
++ ));
++
++ /* Acquire the mutex. */
++ gcmkERR_BREAK(gckOS_AcquireMutex(
++ command->os,
++ command->taskMutex,
++ gcvINFINITE
++ ));
++
++ /* Verify inputs. */
++ gcmkASSERT(TaskHeader != gcvNULL);
++ gcmkASSERT(TaskHeader->container != gcvNULL);
++ gcmkASSERT(TaskHeader->task != gcvNULL);
++ gcmkASSERT(TaskHeader->link != gcvNULL);
++
++ /* Process tasks. */
++ do
++ {
++ /* Process the current task. */
++ gcmkERR_BREAK(_taskRoutine[TaskHeader->task->id](
++ command,
++ TaskHeader
++ ));
++
++ /* Is the next task is LINK? */
++ if (TaskHeader->task->id == gcvTASK_LINK)
++ {
++ gcmkERR_BREAK(_taskRoutine[TaskHeader->task->id](
++ command,
++ TaskHeader
++ ));
++
++ /* Done. */
++ break;
++ }
++ }
++ while (ProcessAll);
++
++ /* Release the mutex. */
++ gcmkCHECK_STATUS(gckOS_ReleaseMutex(
++ command->os,
++ command->taskMutex
++ ));
++ }
++ while (gcvFALSE);
++
++ gcmkFOOTER();
++ /* Return status. */
++ return status;
++}
++
++gcmDECLARE_INTERRUPT_HANDLER(COMMAND, 0)
++{
++ gceSTATUS status, last;
++
++ gcmkHEADER_ARG("Kernel=0x%x ", Kernel);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++
++
++ do
++ {
++ gckVGCOMMAND command;
++ gcsKERNEL_QUEUE_HEADER_PTR mergeQueue;
++ gcsKERNEL_QUEUE_HEADER_PTR queueTail;
++ gcsKERNEL_CMDQUEUE_PTR entry;
++ gctUINT entryCount;
++
++ /* Get the command buffer object. */
++ command = Kernel->command;
++
++ /* Acquire the mutex. */
++ gcmkERR_BREAK(gckOS_AcquireMutex(
++ command->os,
++ command->queueMutex,
++ gcvINFINITE
++ ));
++
++ /* Get the current queue. */
++ queueTail = command->queueTail;
++
++ /* Get the current queue entry. */
++ entry = queueTail->currentEntry;
++
++ /* Get the number of entries in the queue. */
++ entryCount = queueTail->pending;
++
++ /* Process all entries. */
++ while (gcvTRUE)
++ {
++ /* Call post-execution function. */
++ status = entry->handler(Kernel, entry);
++
++ /* Failed? */
++ if (gcmkIS_ERROR(status))
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR,
++ gcvZONE_COMMAND,
++ "[%s] line %d: post action failed.\n",
++ __FUNCTION__, __LINE__
++ );
++ }
++
++ /* Executed the next buffer? */
++ if (status == gcvSTATUS_EXECUTED)
++ {
++ /* Update the queue. */
++ queueTail->pending = entryCount;
++ queueTail->currentEntry = entry;
++
++ /* Success. */
++ status = gcvSTATUS_OK;
++
++ /* Break out of the loop. */
++ break;
++ }
++
++ /* Advance to the next entry. */
++ entry += 1;
++ entryCount -= 1;
++
++ /* Last entry? */
++ if (entryCount == 0)
++ {
++ /* Reset the queue to idle. */
++ queueTail->pending = 0;
++
++ /* Get a shortcut to the queue to merge with. */
++ mergeQueue = command->mergeQueue;
++
++ /* Merge the queues if necessary. */
++ if (mergeQueue != queueTail)
++ {
++ gcmkASSERT(mergeQueue < queueTail);
++ gcmkASSERT(mergeQueue->next == queueTail);
++
++ mergeQueue->size
++ += gcmSIZEOF(gcsKERNEL_QUEUE_HEADER)
++ + queueTail->size;
++
++ mergeQueue->next = queueTail->next;
++ }
++
++ /* Advance to the next queue. */
++ queueTail = queueTail->next;
++
++ /* Did it wrap around? */
++ if (command->queue == queueTail)
++ {
++ /* Reset merge queue. */
++ command->mergeQueue = queueTail;
++ }
++
++ /* Set new queue. */
++ command->queueTail = queueTail;
++
++ /* Is the next queue scheduled? */
++ if (queueTail->pending > 0)
++ {
++ gcsCMDBUFFER_PTR commandBuffer;
++
++ /* The first entry must be a command buffer. */
++ commandBuffer = queueTail->currentEntry->commandBuffer;
++
++ /* Start the command processor. */
++ status = gckVGHARDWARE_Execute(
++ command->hardware,
++ commandBuffer->address,
++ commandBuffer->dataCount
++ );
++
++ /* Failed? */
++ if (gcmkIS_ERROR(status))
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR,
++ gcvZONE_COMMAND,
++ "[%s] line %d: failed to start the next queue.\n",
++ __FUNCTION__, __LINE__
++ );
++ }
++ }
++ else
++ {
++ status = gckVGHARDWARE_SetPowerManagementState(
++ Kernel->command->hardware, gcvPOWER_IDLE_BROADCAST
++ );
++ }
++
++ /* Break out of the loop. */
++ break;
++ }
++ }
++
++ /* Release the mutex. */
++ gcmkCHECK_STATUS(gckOS_ReleaseMutex(
++ command->os,
++ command->queueMutex
++ ));
++ }
++ while (gcvFALSE);
++
++
++ gcmkFOOTER();
++ /* Return status. */
++ return status;
++}
++
++/* Define standard block interrupt handlers. */
++gcmDEFINE_INTERRUPT_HANDLER(TESSELLATOR, 0)
++gcmDEFINE_INTERRUPT_HANDLER(VG, 0)
++gcmDEFINE_INTERRUPT_HANDLER(PIXEL, 0)
++gcmDEFINE_INTERRUPT_HANDLER(PIXEL, 1)
++gcmDEFINE_INTERRUPT_HANDLER(PIXEL, 2)
++gcmDEFINE_INTERRUPT_HANDLER(PIXEL, 3)
++gcmDEFINE_INTERRUPT_HANDLER(PIXEL, 4)
++gcmDEFINE_INTERRUPT_HANDLER(PIXEL, 5)
++gcmDEFINE_INTERRUPT_HANDLER(PIXEL, 6)
++gcmDEFINE_INTERRUPT_HANDLER(PIXEL, 7)
++gcmDEFINE_INTERRUPT_HANDLER(PIXEL, 8)
++gcmDEFINE_INTERRUPT_HANDLER(PIXEL, 9)
++
++/* The entries in the array are arranged by event priority. */
++static gcsBLOCK_INTERRUPT_HANDLER _blockHandlers[] =
++{
++ gcmDEFINE_INTERRUPT_HANDLER_ENTRY(TESSELLATOR, 0),
++ gcmDEFINE_INTERRUPT_HANDLER_ENTRY(VG, 0),
++ gcmDEFINE_INTERRUPT_HANDLER_ENTRY(PIXEL, 0),
++ gcmDEFINE_INTERRUPT_HANDLER_ENTRY(PIXEL, 1),
++ gcmDEFINE_INTERRUPT_HANDLER_ENTRY(PIXEL, 2),
++ gcmDEFINE_INTERRUPT_HANDLER_ENTRY(PIXEL, 3),
++ gcmDEFINE_INTERRUPT_HANDLER_ENTRY(PIXEL, 4),
++ gcmDEFINE_INTERRUPT_HANDLER_ENTRY(PIXEL, 5),
++ gcmDEFINE_INTERRUPT_HANDLER_ENTRY(PIXEL, 6),
++ gcmDEFINE_INTERRUPT_HANDLER_ENTRY(PIXEL, 7),
++ gcmDEFINE_INTERRUPT_HANDLER_ENTRY(PIXEL, 8),
++ gcmDEFINE_INTERRUPT_HANDLER_ENTRY(PIXEL, 9),
++ gcmDEFINE_INTERRUPT_HANDLER_ENTRY(COMMAND, 0),
++};
++
++
++/******************************************************************************\
++************************* Static Command Buffer Handlers ***********************
++\******************************************************************************/
++
++static gceSTATUS
++_UpdateStaticCommandBuffer(
++ IN gckVGKERNEL Kernel,
++ IN gcsKERNEL_CMDQUEUE_PTR Entry
++ )
++{
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ "%s(%d)\n",
++ __FUNCTION__, __LINE__
++ );
++
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++static gceSTATUS
++_ExecuteStaticCommandBuffer(
++ IN gckVGKERNEL Kernel,
++ IN gcsKERNEL_CMDQUEUE_PTR Entry
++ )
++{
++ gceSTATUS status;
++
++ do
++ {
++ gcsCMDBUFFER_PTR commandBuffer;
++
++ /* Cast the command buffer header. */
++ commandBuffer = Entry->commandBuffer;
++
++ /* Set to update the command buffer next time. */
++ Entry->handler = _UpdateStaticCommandBuffer;
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ "%s(%d): executing next buffer @ 0x%08X, data count = %d\n",
++ __FUNCTION__, __LINE__,
++ commandBuffer->address,
++ commandBuffer->dataCount
++ );
++
++ /* Start the command processor. */
++ gcmkERR_BREAK(gckVGHARDWARE_Execute(
++ Kernel->hardware,
++ commandBuffer->address,
++ commandBuffer->dataCount
++ ));
++
++ /* Success. */
++ return gcvSTATUS_EXECUTED;
++ }
++ while (gcvFALSE);
++
++ /* Return status. */
++ return status;
++}
++
++static gceSTATUS
++_UpdateLastStaticCommandBuffer(
++ IN gckVGKERNEL Kernel,
++ IN gcsKERNEL_CMDQUEUE_PTR Entry
++ )
++{
++#if gcvDEBUG || gcdFORCE_MESSAGES
++ /* Get the command buffer header. */
++ gcsCMDBUFFER_PTR commandBuffer = Entry->commandBuffer;
++
++ /* Validate the command buffer. */
++ gcmkASSERT(commandBuffer->completion != gcvNULL);
++ gcmkASSERT(commandBuffer->completion != gcvVACANT_BUFFER);
++
++#endif
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ "%s(%d): processing all tasks scheduled for FE.\n",
++ __FUNCTION__, __LINE__
++ );
++
++ /* Perform scheduled tasks. */
++ return _EventHandler_Block(
++ Kernel,
++ &Kernel->command->taskTable[gcvBLOCK_COMMAND],
++ gcvTRUE
++ );
++}
++
++static gceSTATUS
++_ExecuteLastStaticCommandBuffer(
++ IN gckVGKERNEL Kernel,
++ IN gcsKERNEL_CMDQUEUE_PTR Entry
++ )
++{
++ gceSTATUS status;
++
++ do
++ {
++ /* Cast the command buffer header. */
++ gcsCMDBUFFER_PTR commandBuffer = Entry->commandBuffer;
++
++ /* Set to update the command buffer next time. */
++ Entry->handler = _UpdateLastStaticCommandBuffer;
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ "%s(%d): executing next buffer @ 0x%08X, data count = %d\n",
++ __FUNCTION__, __LINE__,
++ commandBuffer->address,
++ commandBuffer->dataCount
++ );
++
++ /* Start the command processor. */
++ gcmkERR_BREAK(gckVGHARDWARE_Execute(
++ Kernel->hardware,
++ commandBuffer->address,
++ commandBuffer->dataCount
++ ));
++
++ /* Success. */
++ return gcvSTATUS_EXECUTED;
++ }
++ while (gcvFALSE);
++
++ /* Return status. */
++ return status;
++}
++
++
++/******************************************************************************\
++************************* Dynamic Command Buffer Handlers **********************
++\******************************************************************************/
++
++static gceSTATUS
++_UpdateDynamicCommandBuffer(
++ IN gckVGKERNEL Kernel,
++ IN gcsKERNEL_CMDQUEUE_PTR Entry
++ )
++{
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ "%s(%d)\n",
++ __FUNCTION__, __LINE__
++ );
++
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++static gceSTATUS
++_ExecuteDynamicCommandBuffer(
++ IN gckVGKERNEL Kernel,
++ IN gcsKERNEL_CMDQUEUE_PTR Entry
++ )
++{
++ gceSTATUS status;
++
++ do
++ {
++ /* Cast the command buffer header. */
++ gcsCMDBUFFER_PTR commandBuffer = Entry->commandBuffer;
++
++ /* Set to update the command buffer next time. */
++ Entry->handler = _UpdateDynamicCommandBuffer;
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ "%s(%d): executing next buffer @ 0x%08X, data count = %d\n",
++ __FUNCTION__, __LINE__,
++ commandBuffer->address,
++ commandBuffer->dataCount
++ );
++
++ /* Start the command processor. */
++ gcmkERR_BREAK(gckVGHARDWARE_Execute(
++ Kernel->hardware,
++ commandBuffer->address,
++ commandBuffer->dataCount
++ ));
++
++ /* Success. */
++ return gcvSTATUS_EXECUTED;
++ }
++ while (gcvFALSE);
++
++ /* Return status. */
++ return status;
++}
++
++static gceSTATUS
++_UpdateLastDynamicCommandBuffer(
++ IN gckVGKERNEL Kernel,
++ IN gcsKERNEL_CMDQUEUE_PTR Entry
++ )
++{
++#if gcvDEBUG || gcdFORCE_MESSAGES
++ /* Get the command buffer header. */
++ gcsCMDBUFFER_PTR commandBuffer = Entry->commandBuffer;
++
++ /* Validate the command buffer. */
++ gcmkASSERT(commandBuffer->completion != gcvNULL);
++ gcmkASSERT(commandBuffer->completion != gcvVACANT_BUFFER);
++
++#endif
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ "%s(%d): processing all tasks scheduled for FE.\n",
++ __FUNCTION__, __LINE__
++ );
++
++ /* Perform scheduled tasks. */
++ return _EventHandler_Block(
++ Kernel,
++ &Kernel->command->taskTable[gcvBLOCK_COMMAND],
++ gcvTRUE
++ );
++}
++
++static gceSTATUS
++_ExecuteLastDynamicCommandBuffer(
++ IN gckVGKERNEL Kernel,
++ IN gcsKERNEL_CMDQUEUE_PTR Entry
++ )
++{
++ gceSTATUS status;
++
++ do
++ {
++ /* Cast the command buffer header. */
++ gcsCMDBUFFER_PTR commandBuffer = Entry->commandBuffer;
++
++ /* Set to update the command buffer next time. */
++ Entry->handler = _UpdateLastDynamicCommandBuffer;
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ "%s(%d): executing next buffer @ 0x%08X, data count = %d\n",
++ __FUNCTION__, __LINE__,
++ commandBuffer->address,
++ commandBuffer->dataCount
++ );
++
++ /* Start the command processor. */
++ gcmkERR_BREAK(gckVGHARDWARE_Execute(
++ Kernel->hardware,
++ commandBuffer->address,
++ commandBuffer->dataCount
++ ));
++
++ /* Success. */
++ return gcvSTATUS_EXECUTED;
++ }
++ while (gcvFALSE);
++
++ /* Return status. */
++ return status;
++}
++
++
++/******************************************************************************\
++********************************* Other Handlers *******************************
++\******************************************************************************/
++
++static gceSTATUS
++_FreeKernelCommandBuffer(
++ IN gckVGKERNEL Kernel,
++ IN gcsKERNEL_CMDQUEUE_PTR Entry
++ )
++{
++ gceSTATUS status;
++
++ /* Free the command buffer. */
++ status = _FreeCommandBuffer(Kernel, Entry->commandBuffer);
++
++ /* Return status. */
++ return status;
++}
++
++
++/******************************************************************************\
++******************************* Queue Management *******************************
++\******************************************************************************/
++
++#if gcvDUMP_COMMAND_BUFFER
++static void
++_DumpCommandQueue(
++ IN gckVGCOMMAND Command,
++ IN gcsKERNEL_QUEUE_HEADER_PTR QueueHeader,
++ IN gctUINT EntryCount
++ )
++{
++ gcsKERNEL_CMDQUEUE_PTR entry;
++ gctUINT queueIndex;
++
++#if defined(gcvCOMMAND_BUFFER_NAME)
++ static gctUINT arrayCount = 0;
++#endif
++
++ /* Is dumpinng enabled? */
++ if (!Commad->enableDumping)
++ {
++ return;
++ }
++
++#if !defined(gcvCOMMAND_BUFFER_NAME)
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_COMMAND,
++ "COMMAND QUEUE DUMP: %d entries\n", EntryCount
++ );
++#endif
++
++ /* Get the pointer to the first entry. */
++ entry = QueueHeader->currentEntry;
++
++ /* Iterate through the queue. */
++ for (queueIndex = 0; queueIndex < EntryCount; queueIndex += 1)
++ {
++ gcsCMDBUFFER_PTR buffer;
++ gctUINT bufferCount;
++ gctUINT bufferIndex;
++ gctUINT i, count;
++ gctUINT size;
++ gctUINT32_PTR data;
++
++#if gcvDUMP_COMMAND_LINES
++ gctUINT lineNumber;
++#endif
++
++#if !defined(gcvCOMMAND_BUFFER_NAME)
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_COMMAND,
++ "ENTRY %d\n", queueIndex
++ );
++#endif
++
++ /* Reset the count. */
++ bufferCount = 0;
++
++ /* Set the initial buffer. */
++ buffer = entry->commandBuffer;
++
++ /* Loop through all subbuffers. */
++ while (buffer)
++ {
++ /* Update the count. */
++ bufferCount += 1;
++
++ /* Advance to the next subbuffer. */
++ buffer = buffer->nextSubBuffer;
++ }
++
++#if !defined(gcvCOMMAND_BUFFER_NAME)
++ if (bufferCount > 1)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO,
++ gcvZONE_COMMAND,
++ " COMMAND BUFFER SET: %d buffers.\n",
++ bufferCount
++ );
++ }
++#endif
++
++ /* Reset the buffer index. */
++ bufferIndex = 0;
++
++ /* Set the initial buffer. */
++ buffer = entry->commandBuffer;
++
++ /* Loop through all subbuffers. */
++ while (buffer)
++ {
++ /* Determine the size of the buffer. */
++ size = buffer->dataCount * Command->info.commandAlignment;
++
++#if !defined(gcvCOMMAND_BUFFER_NAME)
++ /* A single buffer? */
++ if (bufferCount == 1)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO,
++ gcvZONE_COMMAND,
++ " COMMAND BUFFER: count=%d (0x%X), size=%d bytes @ %08X.\n",
++ buffer->dataCount,
++ buffer->dataCount,
++ size,
++ buffer->address
++ );
++ }
++ else
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO,
++ gcvZONE_COMMAND,
++ " COMMAND BUFFER %d: count=%d (0x%X), size=%d bytes @ %08X\n",
++ bufferIndex,
++ buffer->dataCount,
++ buffer->dataCount,
++ size,
++ buffer->address
++ );
++ }
++#endif
++
++ /* Determine the number of double words to print. */
++ count = size / 4;
++
++ /* Determine the buffer location. */
++ data = (gctUINT32_PTR)
++ (
++ (gctUINT8_PTR) buffer + buffer->bufferOffset
++ );
++
++#if defined(gcvCOMMAND_BUFFER_NAME)
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO,
++ gcvZONE_COMMAND,
++ "unsigned int _" gcvCOMMAND_BUFFER_NAME "_%d[] =\n",
++ arrayCount
++ );
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO,
++ gcvZONE_COMMAND,
++ "{\n"
++ );
++
++ arrayCount += 1;
++#endif
++
++#if gcvDUMP_COMMAND_LINES
++ /* Reset the line number. */
++ lineNumber = 0;
++#endif
++
++#if defined(gcvCOMMAND_BUFFER_NAME)
++ count -= 2;
++#endif
++
++ for (i = 0; i < count; i += 1)
++ {
++ if ((i % 8) == 0)
++ {
++#if defined(gcvCOMMAND_BUFFER_NAME)
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_COMMAND, "\t");
++#else
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_COMMAND, " ");
++#endif
++ }
++
++#if gcvDUMP_COMMAND_LINES
++ if (lineNumber == gcvDUMP_COMMAND_LINES)
++ {
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_COMMAND, " . . . . . . . . .\n");
++ break;
++ }
++#endif
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_COMMAND, "0x%08X", data[i]);
++
++ if (i + 1 == count)
++ {
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_COMMAND, "\n");
++
++#if gcvDUMP_COMMAND_LINES
++ lineNumber += 1;
++#endif
++ }
++ else
++ {
++ if (((i + 1) % 8) == 0)
++ {
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_COMMAND, ",\n");
++
++#if gcvDUMP_COMMAND_LINES
++ lineNumber += 1;
++#endif
++ }
++ else
++ {
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_COMMAND, ", ");
++ }
++ }
++ }
++
++#if defined(gcvCOMMAND_BUFFER_NAME)
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO,
++ gcvZONE_COMMAND,
++ "};\n\n"
++ );
++#endif
++
++ /* Advance to the next subbuffer. */
++ buffer = buffer->nextSubBuffer;
++ bufferIndex += 1;
++ }
++
++ /* Advance to the next entry. */
++ entry += 1;
++ }
++}
++#endif
++
++static gceSTATUS
++_LockCurrentQueue(
++ IN gckVGCOMMAND Command,
++ OUT gcsKERNEL_CMDQUEUE_PTR * Entries,
++ OUT gctUINT_PTR EntryCount
++ )
++{
++ gceSTATUS status;
++
++ do
++ {
++ gcsKERNEL_QUEUE_HEADER_PTR queueHead;
++
++ /* Get a shortcut to the head of the queue. */
++ queueHead = Command->queueHead;
++
++ /* Is the head buffer still being worked on? */
++ if (queueHead->pending)
++ {
++ /* Increment overflow count. */
++ Command->queueOverflow += 1;
++
++ /* Wait until the head becomes idle. */
++ gcmkERR_BREAK(_WaitForIdle(Command, queueHead));
++ }
++
++ /* Acquire the mutex. */
++ gcmkERR_BREAK(gckOS_AcquireMutex(
++ Command->os,
++ Command->queueMutex,
++ gcvINFINITE
++ ));
++
++ /* Determine the first queue entry. */
++ queueHead->currentEntry = (gcsKERNEL_CMDQUEUE_PTR)
++ (
++ (gctUINT8_PTR) queueHead + gcmSIZEOF(gcsKERNEL_QUEUE_HEADER)
++ );
++
++ /* Set the pointer to the first entry. */
++ * Entries = queueHead->currentEntry;
++
++ /* Determine the number of available entries. */
++ * EntryCount = queueHead->size / gcmSIZEOF(gcsKERNEL_CMDQUEUE);
++
++ /* Success. */
++ return gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ /* Return status. */
++ return status;
++}
++
++static gceSTATUS
++_UnlockCurrentQueue(
++ IN gckVGCOMMAND Command,
++ IN gctUINT EntryCount
++ )
++{
++ gceSTATUS status;
++
++ do
++ {
++#if !gcdENABLE_INFINITE_SPEED_HW
++ gcsKERNEL_QUEUE_HEADER_PTR queueTail;
++ gcsKERNEL_QUEUE_HEADER_PTR queueHead;
++ gcsKERNEL_QUEUE_HEADER_PTR queueNext;
++ gctUINT queueSize;
++ gctUINT newSize;
++ gctUINT unusedSize;
++
++ /* Get shortcut to the head and to the tail of the queue. */
++ queueTail = Command->queueTail;
++ queueHead = Command->queueHead;
++
++ /* Dump the command buffer. */
++#if gcvDUMP_COMMAND_BUFFER
++ _DumpCommandQueue(Command, queueHead, EntryCount);
++#endif
++
++ /* Get a shortcut to the current queue size. */
++ queueSize = queueHead->size;
++
++ /* Determine the new queue size. */
++ newSize = EntryCount * gcmSIZEOF(gcsKERNEL_CMDQUEUE);
++ gcmkASSERT(newSize <= queueSize);
++
++ /* Determine the size of the unused area. */
++ unusedSize = queueSize - newSize;
++
++ /* Is the unused area big enough to become a buffer? */
++ if (unusedSize >= gcvMINUMUM_BUFFER)
++ {
++ gcsKERNEL_QUEUE_HEADER_PTR nextHead;
++
++ /* Place the new header. */
++ nextHead = (gcsKERNEL_QUEUE_HEADER_PTR)
++ (
++ (gctUINT8_PTR) queueHead
++ + gcmSIZEOF(gcsKERNEL_QUEUE_HEADER)
++ + newSize
++ );
++
++ /* Initialize the buffer. */
++ nextHead->size = unusedSize - gcmSIZEOF(gcsKERNEL_QUEUE_HEADER);
++ nextHead->pending = 0;
++
++ /* Link the buffer in. */
++ nextHead->next = queueHead->next;
++ queueHead->next = nextHead;
++ queueNext = nextHead;
++
++ /* Update the size of the current buffer. */
++ queueHead->size = newSize;
++ }
++
++ /* Not big enough. */
++ else
++ {
++ /* Determine the next queue. */
++ queueNext = queueHead->next;
++ }
++
++ /* Mark the buffer as busy. */
++ queueHead->pending = EntryCount;
++
++ /* Advance to the next buffer. */
++ Command->queueHead = queueNext;
++
++ /* Start the command processor if the queue was empty. */
++ if (queueTail == queueHead)
++ {
++ gcsCMDBUFFER_PTR commandBuffer;
++
++ /* The first entry must be a command buffer. */
++ commandBuffer = queueTail->currentEntry->commandBuffer;
++
++ /* Start the command processor. */
++ gcmkERR_BREAK(gckVGHARDWARE_Execute(
++ Command->hardware,
++ commandBuffer->address,
++ commandBuffer->dataCount
++ ));
++ }
++
++ /* The queue was not empty. */
++ else
++ {
++ /* Advance the merge buffer if needed. */
++ if (queueHead == Command->mergeQueue)
++ {
++ Command->mergeQueue = queueNext;
++ }
++ }
++#endif
++
++ /* Release the mutex. */
++ gcmkERR_BREAK(gckOS_ReleaseMutex(
++ Command->os,
++ Command->queueMutex
++ ));
++
++ /* Success. */
++ return gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ /* Return status. */
++ return status;
++}
++
++
++
++/******************************************************************************\
++****************************** gckVGCOMMAND API Code *****************************
++\******************************************************************************/
++gceSTATUS
++gckVGCOMMAND_Construct(
++ IN gckVGKERNEL Kernel,
++ IN gctUINT TaskGranularity,
++ IN gctUINT QueueSize,
++ OUT gckVGCOMMAND * Command
++ )
++{
++ gceSTATUS status, last;
++ gckVGCOMMAND command = gcvNULL;
++ gcsKERNEL_QUEUE_HEADER_PTR queue;
++ gctUINT i, j;
++
++ gcmkHEADER_ARG("Kernel=0x%x TaskGranularity=0x%x QueueSize=0x%x Command=0x%x",
++ Kernel, TaskGranularity, QueueSize, Command);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(QueueSize >= gcvMINUMUM_BUFFER);
++ gcmkVERIFY_ARGUMENT(Command != gcvNULL);
++
++ do
++ {
++ /***********************************************************************
++ ** Generic object initialization.
++ */
++
++ /* Allocate the gckVGCOMMAND structure. */
++ gcmkERR_BREAK(gckOS_Allocate(
++ Kernel->os,
++ gcmSIZEOF(struct _gckVGCOMMAND),
++ (gctPOINTER *) &command
++ ));
++
++ /* Initialize the object. */
++ command->object.type = gcvOBJ_COMMAND;
++
++ /* Set the object pointers. */
++ command->kernel = Kernel;
++ command->os = Kernel->os;
++ command->hardware = Kernel->hardware;
++
++ /* Reset pointers. */
++ command->queue = gcvNULL;
++ command->queueMutex = gcvNULL;
++ command->taskMutex = gcvNULL;
++ command->commitMutex = gcvNULL;
++
++ command->powerStallBuffer = gcvNULL;
++ command->powerStallSignal = gcvNULL;
++ command->powerSemaphore = gcvNULL;
++
++ /* Reset context states. */
++ command->contextCounter = 0;
++ command->currentContext = 0;
++
++ /* Enable command buffer dumping. */
++ command->enableDumping = gcvTRUE;
++
++ /* Set features. */
++ command->fe20 = Kernel->hardware->fe20;
++ command->vg20 = Kernel->hardware->vg20;
++ command->vg21 = Kernel->hardware->vg21;
++
++ /* Reset task table .*/
++ gcmkVERIFY_OK(gckOS_ZeroMemory(
++ command->taskTable, gcmSIZEOF(command->taskTable)
++ ));
++
++ /* Query command buffer attributes. */
++ gcmkERR_BREAK(gckVGCOMMAND_InitializeInfo(command));
++
++ /* Create the control mutexes. */
++ gcmkERR_BREAK(gckOS_CreateMutex(Kernel->os, &command->queueMutex));
++ gcmkERR_BREAK(gckOS_CreateMutex(Kernel->os, &command->taskMutex));
++ gcmkERR_BREAK(gckOS_CreateMutex(Kernel->os, &command->commitMutex));
++
++ /* Create the power management semaphore. */
++ gcmkERR_BREAK(gckOS_CreateSemaphore(Kernel->os,
++ &command->powerSemaphore));
++
++ gcmkERR_BREAK(gckOS_CreateSignal(Kernel->os,
++ gcvFALSE, &command->powerStallSignal));
++
++ /***********************************************************************
++ ** Command queue initialization.
++ */
++
++ /* Allocate the command queue. */
++ gcmkERR_BREAK(gckOS_Allocate(
++ Kernel->os,
++ QueueSize,
++ (gctPOINTER *) &command->queue
++ ));
++
++ /* Initialize the command queue. */
++ queue = command->queue;
++
++ queue->size = QueueSize - gcmSIZEOF(gcsKERNEL_QUEUE_HEADER);
++ queue->pending = 0;
++ queue->next = queue;
++
++ command->queueHead =
++ command->queueTail =
++ command->mergeQueue = command->queue;
++
++ command->queueOverflow = 0;
++
++
++ /***********************************************************************
++ ** Enable TS overflow interrupt.
++ */
++
++ command->info.tsOverflowInt = 0;
++ gcmkERR_BREAK(gckVGINTERRUPT_Enable(
++ Kernel->interrupt,
++ &command->info.tsOverflowInt,
++ _EventHandler_TSOverflow
++ ));
++
++ /* Mask out the interrupt. */
++ Kernel->hardware->eventMask &= ~(1 << command->info.tsOverflowInt);
++
++
++ /***********************************************************************
++ ** Enable Bus Error interrupt.
++ */
++
++ /* Hardwired to bit 31. */
++ command->busErrorInt = 31;
++
++ /* Enable the interrupt. */
++ gcmkERR_BREAK(gckVGINTERRUPT_Enable(
++ Kernel->interrupt,
++ &command->busErrorInt,
++ _EventHandler_BusError
++ ));
++
++
++ command->powerStallInt = 30;
++ /* Enable the interrupt. */
++ gcmkERR_BREAK(gckVGINTERRUPT_Enable(
++ Kernel->interrupt,
++ &command->powerStallInt,
++ _EventHandler_PowerStall
++ ));
++
++ /***********************************************************************
++ ** Task management initialization.
++ */
++
++ command->taskStorage = gcvNULL;
++ command->taskStorageGranularity = TaskGranularity;
++ command->taskStorageUsable = TaskGranularity - gcmSIZEOF(gcsTASK_STORAGE);
++
++ command->taskFreeHead = gcvNULL;
++ command->taskFreeTail = gcvNULL;
++
++ /* Enable block handlers. */
++ for (i = 0; i < gcmCOUNTOF(_blockHandlers); i += 1)
++ {
++ /* Get the target hardware block. */
++ gceBLOCK block = _blockHandlers[i].block;
++
++ /* Get the interrupt array entry. */
++ gcsBLOCK_TASK_ENTRY_PTR entry = &command->taskTable[block];
++
++ /* Determine the interrupt value index. */
++ gctUINT index = entry->interruptCount;
++
++ /* Create the block semaphore. */
++ if (entry->interruptSemaphore == gcvNULL)
++ {
++ gcmkERR_BREAK(gckOS_CreateSemaphoreVG(
++ command->os, &entry->interruptSemaphore
++ ));
++ }
++
++ /* Enable auto-detection. */
++ entry->interruptArray[index] = -1;
++
++ /* Enable interrupt for the block. */
++ gcmkERR_BREAK(gckVGINTERRUPT_Enable(
++ Kernel->interrupt,
++ &entry->interruptArray[index],
++ _blockHandlers[i].handler
++ ));
++
++ /* Update the number of registered interrupts. */
++ entry->interruptCount += 1;
++
++ /* Inrement the semaphore to allow the usage of the registered
++ interrupt. */
++ gcmkERR_BREAK(gckOS_IncrementSemaphore(
++ command->os, entry->interruptSemaphore
++ ));
++
++ }
++
++ /* Error? */
++ if (gcmkIS_ERROR(status))
++ {
++ break;
++ }
++
++ /* Get the FE interrupt. */
++ command->info.feBufferInt
++ = command->taskTable[gcvBLOCK_COMMAND].interruptArray[0];
++
++ /* Return gckVGCOMMAND object pointer. */
++ *Command = command;
++
++ gcmkFOOTER_ARG("*Command=0x%x",*Command);
++ /* Success. */
++ return gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ /* Roll back. */
++ if (command != gcvNULL)
++ {
++ /* Disable block handlers. */
++ for (i = 0; i < gcvBLOCK_COUNT; i += 1)
++ {
++ /* Get the task table entry. */
++ gcsBLOCK_TASK_ENTRY_PTR entry = &command->taskTable[i];
++
++ /* Destroy the semaphore. */
++ if (entry->interruptSemaphore != gcvNULL)
++ {
++ gcmkCHECK_STATUS(gckOS_DestroySemaphore(
++ command->os, entry->interruptSemaphore
++ ));
++ }
++
++ /* Disable all enabled interrupts. */
++ for (j = 0; j < entry->interruptCount; j += 1)
++ {
++ /* Must be a valid value. */
++ gcmkASSERT(entry->interruptArray[j] >= 0);
++ gcmkASSERT(entry->interruptArray[j] <= 31);
++
++ /* Disable the interrupt. */
++ gcmkCHECK_STATUS(gckVGINTERRUPT_Disable(
++ Kernel->interrupt,
++ entry->interruptArray[j]
++ ));
++ }
++ }
++
++ /* Disable the bus error interrupt. */
++ gcmkCHECK_STATUS(gckVGINTERRUPT_Disable(
++ Kernel->interrupt,
++ command->busErrorInt
++ ));
++
++ /* Disable TS overflow interrupt. */
++ if (command->info.tsOverflowInt != -1)
++ {
++ gcmkCHECK_STATUS(gckVGINTERRUPT_Disable(
++ Kernel->interrupt,
++ command->info.tsOverflowInt
++ ));
++ }
++
++ /* Delete the commit mutex. */
++ if (command->commitMutex != gcvNULL)
++ {
++ gcmkCHECK_STATUS(gckOS_DeleteMutex(
++ Kernel->os, command->commitMutex
++ ));
++ }
++
++ /* Delete the command queue mutex. */
++ if (command->taskMutex != gcvNULL)
++ {
++ gcmkCHECK_STATUS(gckOS_DeleteMutex(
++ Kernel->os, command->taskMutex
++ ));
++ }
++
++ /* Delete the command queue mutex. */
++ if (command->queueMutex != gcvNULL)
++ {
++ gcmkCHECK_STATUS(gckOS_DeleteMutex(
++ Kernel->os, command->queueMutex
++ ));
++ }
++
++ /* Delete the command queue. */
++ if (command->queue != gcvNULL)
++ {
++ gcmkCHECK_STATUS(gckOS_Free(
++ Kernel->os, command->queue
++ ));
++ }
++
++ if (command->powerSemaphore != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_DestroySemaphore(
++ Kernel->os, command->powerSemaphore));
++ }
++
++ if (command->powerStallSignal != gcvNULL)
++ {
++ /* Create the power management semaphore. */
++ gcmkVERIFY_OK(gckOS_DestroySignal(
++ Kernel->os,
++ command->powerStallSignal));
++ }
++
++ /* Free the gckVGCOMMAND structure. */
++ gcmkCHECK_STATUS(gckOS_Free(
++ Kernel->os, command
++ ));
++ }
++
++ gcmkFOOTER();
++ /* Return the error. */
++ return status;
++}
++
++gceSTATUS
++gckVGCOMMAND_Destroy(
++ OUT gckVGCOMMAND Command
++ )
++{
++ gceSTATUS status = gcvSTATUS_OK;
++
++ gcmkHEADER_ARG("Command=0x%x", Command);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ do
++ {
++ gctUINT i;
++ gcsTASK_STORAGE_PTR nextStorage;
++
++ if (Command->queueHead != gcvNULL)
++ {
++ /* Wait until the head becomes idle. */
++ gcmkERR_BREAK(_WaitForIdle(Command, Command->queueHead));
++ }
++
++ /* Disable block handlers. */
++ for (i = 0; i < gcvBLOCK_COUNT; i += 1)
++ {
++ /* Get the interrupt array entry. */
++ gcsBLOCK_TASK_ENTRY_PTR entry = &Command->taskTable[i];
++
++ /* Determine the index of the last interrupt in the array. */
++ gctINT index = entry->interruptCount - 1;
++
++ /* Destroy the semaphore. */
++ if (entry->interruptSemaphore != gcvNULL)
++ {
++ gcmkERR_BREAK(gckOS_DestroySemaphore(
++ Command->os, entry->interruptSemaphore
++ ));
++ }
++
++ /* Disable all enabled interrupts. */
++ while (index >= 0)
++ {
++ /* Must be a valid value. */
++ gcmkASSERT(entry->interruptArray[index] >= 0);
++ gcmkASSERT(entry->interruptArray[index] <= 31);
++
++ /* Disable the interrupt. */
++ gcmkERR_BREAK(gckVGINTERRUPT_Disable(
++ Command->kernel->interrupt,
++ entry->interruptArray[index]
++ ));
++
++ /* Update to the next interrupt. */
++ index -= 1;
++ entry->interruptCount -= 1;
++ }
++
++ /* Error? */
++ if (gcmkIS_ERROR(status))
++ {
++ break;
++ }
++ }
++
++ /* Error? */
++ if (gcmkIS_ERROR(status))
++ {
++ break;
++ }
++
++ /* Disable the bus error interrupt. */
++ gcmkERR_BREAK(gckVGINTERRUPT_Disable(
++ Command->kernel->interrupt,
++ Command->busErrorInt
++ ));
++
++ /* Disable TS overflow interrupt. */
++ if (Command->info.tsOverflowInt != -1)
++ {
++ gcmkERR_BREAK(gckVGINTERRUPT_Disable(
++ Command->kernel->interrupt,
++ Command->info.tsOverflowInt
++ ));
++
++ Command->info.tsOverflowInt = -1;
++ }
++
++ /* Delete the commit mutex. */
++ if (Command->commitMutex != gcvNULL)
++ {
++ gcmkERR_BREAK(gckOS_DeleteMutex(
++ Command->os, Command->commitMutex
++ ));
++
++ Command->commitMutex = gcvNULL;
++ }
++
++ /* Delete the command queue mutex. */
++ if (Command->taskMutex != gcvNULL)
++ {
++ gcmkERR_BREAK(gckOS_DeleteMutex(
++ Command->os, Command->taskMutex
++ ));
++
++ Command->taskMutex = gcvNULL;
++ }
++
++ /* Delete the command queue mutex. */
++ if (Command->queueMutex != gcvNULL)
++ {
++ gcmkERR_BREAK(gckOS_DeleteMutex(
++ Command->os, Command->queueMutex
++ ));
++
++ Command->queueMutex = gcvNULL;
++ }
++
++ if (Command->powerSemaphore != gcvNULL)
++ {
++ /* Destroy the power management semaphore. */
++ gcmkERR_BREAK(gckOS_DestroySemaphore(
++ Command->os, Command->powerSemaphore));
++ }
++
++ if (Command->powerStallSignal != gcvNULL)
++ {
++ /* Create the power management semaphore. */
++ gcmkERR_BREAK(gckOS_DestroySignal(
++ Command->os,
++ Command->powerStallSignal));
++ }
++
++ if (Command->queue != gcvNULL)
++ {
++ /* Delete the command queue. */
++ gcmkERR_BREAK(gckOS_Free(
++ Command->os, Command->queue
++ ));
++ }
++
++ /* Destroy all allocated buffers. */
++ while (Command->taskStorage)
++ {
++ /* Copy the buffer pointer. */
++ nextStorage = Command->taskStorage->next;
++
++ /* Free the current container. */
++ gcmkERR_BREAK(gckOS_Free(
++ Command->os, Command->taskStorage
++ ));
++
++ /* Advance to the next one. */
++ Command->taskStorage = nextStorage;
++ }
++
++ /* Error? */
++ if (gcmkIS_ERROR(status))
++ {
++ break;
++ }
++
++ /* Mark the object as unknown. */
++ Command->object.type = gcvOBJ_UNKNOWN;
++
++ /* Free the gckVGCOMMAND structure. */
++ gcmkERR_BREAK(gckOS_Free(Command->os, Command));
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ /* Restore the object type if failed. */
++ Command->object.type = gcvOBJ_COMMAND;
++
++ gcmkFOOTER();
++ /* Return the error. */
++ return status;
++}
++
++gceSTATUS
++gckVGCOMMAND_QueryCommandBuffer(
++ IN gckVGCOMMAND Command,
++ OUT gcsCOMMAND_BUFFER_INFO_PTR Information
++ )
++{
++ gcmkHEADER_ARG("Command=0x%x Information=0x%x", Command, Information);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++ gcmkVERIFY_ARGUMENT(Information != gcvNULL);
++
++ /* Copy the information. */
++ gcmkVERIFY_OK(gckOS_MemCopy(
++ Information, &Command->info, sizeof(gcsCOMMAND_BUFFER_INFO)
++ ));
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckVGCOMMAND_Allocate(
++ IN gckVGCOMMAND Command,
++ IN gctSIZE_T Size,
++ OUT gcsCMDBUFFER_PTR * CommandBuffer,
++ OUT gctPOINTER * Data
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Command=0x%x Size=0x%x CommandBuffer=0x%x Data=0x%x",
++ Command, Size, CommandBuffer, Data);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++ gcmkVERIFY_ARGUMENT(Data != gcvNULL);
++
++ do
++ {
++ /* Allocate the buffer. */
++ gcmkERR_BREAK(_AllocateCommandBuffer(Command, Size, CommandBuffer));
++
++ /* Determine the data pointer. */
++ * Data = (gctUINT8_PTR) (*CommandBuffer) + (* CommandBuffer)->bufferOffset;
++ }
++ while (gcvFALSE);
++
++ gcmkFOOTER();
++ /* Return status. */
++ return status;
++}
++
++gceSTATUS
++gckVGCOMMAND_Free(
++ IN gckVGCOMMAND Command,
++ IN gcsCMDBUFFER_PTR CommandBuffer
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Command=0x%x CommandBuffer=0x%x",
++ Command, CommandBuffer);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++ gcmkVERIFY_ARGUMENT(CommandBuffer != gcvNULL);
++
++ /* Free command buffer. */
++ status = _FreeCommandBuffer(Command->kernel, CommandBuffer);
++
++ gcmkFOOTER();
++ /* Return status. */
++ return status;
++}
++
++gceSTATUS
++gckVGCOMMAND_Execute(
++ IN gckVGCOMMAND Command,
++ IN gcsCMDBUFFER_PTR CommandBuffer
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Command=0x%x CommandBuffer=0x%x",
++ Command, CommandBuffer);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++ gcmkVERIFY_ARGUMENT(CommandBuffer != gcvNULL);
++
++ do
++ {
++ gctUINT queueLength;
++ gcsKERNEL_CMDQUEUE_PTR kernelEntry;
++
++ /* Lock the current queue. */
++ gcmkERR_BREAK(_LockCurrentQueue(
++ Command, &kernelEntry, &queueLength
++ ));
++
++ /* Set the buffer. */
++ kernelEntry->commandBuffer = CommandBuffer;
++ kernelEntry->handler = _FreeKernelCommandBuffer;
++
++ /* Lock the current queue. */
++ gcmkERR_BREAK(_UnlockCurrentQueue(
++ Command, 1
++ ));
++ }
++ while (gcvFALSE);
++
++ gcmkFOOTER();
++ /* Return status. */
++ return status;
++}
++
++gceSTATUS
++gckVGCOMMAND_Commit(
++ IN gckVGCOMMAND Command,
++ IN gcsVGCONTEXT_PTR Context,
++ IN gcsVGCMDQUEUE_PTR Queue,
++ IN gctUINT EntryCount,
++ IN gcsTASK_MASTER_TABLE_PTR TaskTable
++ )
++{
++ /*
++ The first buffer is executed through a direct gckVGHARDWARE_Execute call,
++ therefore only an update is needed after the execution is over. All
++ consequent buffers need to be executed upon the first update call from
++ the FE interrupt handler.
++ */
++
++ static gcsQUEUE_UPDATE_CONTROL _dynamicBuffer[] =
++ {
++ {
++ _UpdateDynamicCommandBuffer,
++ _UpdateDynamicCommandBuffer,
++ _UpdateLastDynamicCommandBuffer,
++ _UpdateLastDynamicCommandBuffer
++ },
++ {
++ _ExecuteDynamicCommandBuffer,
++ _UpdateDynamicCommandBuffer,
++ _ExecuteLastDynamicCommandBuffer,
++ _UpdateLastDynamicCommandBuffer
++ }
++ };
++
++ static gcsQUEUE_UPDATE_CONTROL _staticBuffer[] =
++ {
++ {
++ _UpdateStaticCommandBuffer,
++ _UpdateStaticCommandBuffer,
++ _UpdateLastStaticCommandBuffer,
++ _UpdateLastStaticCommandBuffer
++ },
++ {
++ _ExecuteStaticCommandBuffer,
++ _UpdateStaticCommandBuffer,
++ _ExecuteLastStaticCommandBuffer,
++ _UpdateLastStaticCommandBuffer
++ }
++ };
++
++ gceSTATUS status, last;
++
++ gcmkHEADER_ARG("Command=0x%x Context=0x%x Queue=0x%x EntryCount=0x%x TaskTable=0x%x",
++ Command, Context, Queue, EntryCount, TaskTable);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++ gcmkVERIFY_ARGUMENT(Context != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Queue != gcvNULL);
++ gcmkVERIFY_ARGUMENT(EntryCount > 1);
++
++#ifdef __QNXNTO__
++ TaskTable->coid = Context->coid;
++ TaskTable->rcvid = Context->rcvid;
++#endif /* __QNXNTO__ */
++
++ do
++ {
++ gctBOOL haveFETasks;
++ gctUINT queueSize;
++ gcsVGCMDQUEUE_PTR mappedQueue;
++ gcsVGCMDQUEUE_PTR userEntry;
++ gcsKERNEL_CMDQUEUE_PTR kernelEntry;
++ gcsQUEUE_UPDATE_CONTROL_PTR queueControl;
++ gctUINT currentLength;
++ gctUINT queueLength;
++ gctUINT entriesQueued;
++ gctUINT8_PTR previousEnd;
++ gctBOOL previousDynamic;
++ gctBOOL previousExecuted;
++ gctUINT controlIndex;
++
++ gcmkERR_BREAK(gckVGHARDWARE_SetPowerManagementState(
++ Command->hardware, gcvPOWER_ON_AUTO
++ ));
++
++ /* Acquire the power semaphore. */
++ gcmkERR_BREAK(gckOS_AcquireSemaphore(
++ Command->os, Command->powerSemaphore
++ ));
++
++ /* Acquire the mutex. */
++ status = gckOS_AcquireMutex(
++ Command->os,
++ Command->commitMutex,
++ gcvINFINITE
++ );
++
++ if (gcmIS_ERROR(status))
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseSemaphore(
++ Command->os, Command->powerSemaphore));
++ break;
++ }
++
++ do
++ {
++ gcmkERR_BREAK(_FlushMMU(Command));
++
++ /* Assign a context ID if not yet assigned. */
++ if (Context->id == 0)
++ {
++ /* Assign the next context number. */
++ Context->id = ++ Command->contextCounter;
++
++ /* See if we overflowed. */
++ if (Command->contextCounter == 0)
++ {
++ /* We actually did overflow, wow... */
++ status = gcvSTATUS_OUT_OF_RESOURCES;
++ break;
++ }
++ }
++
++ /* The first entry in the queue is always the context buffer.
++ Verify whether the user context is the same as the current
++ context and if that's the case, skip the first entry. */
++ if (Context->id == Command->currentContext)
++ {
++ /* Same context as before, skip the first entry. */
++ EntryCount -= 1;
++ Queue += 1;
++
++ /* Set the signal to avoid user waiting. */
++#ifdef __QNXNTO__
++ gcmkERR_BREAK(gckOS_UserSignal(
++ Command->os, Context->signal, Context->rcvid, Context->coid
++ ));
++#else
++ gcmkERR_BREAK(gckOS_UserSignal(
++ Command->os, Context->signal, Context->process
++ ));
++
++#endif /* __QNXNTO__ */
++
++ }
++ else
++ {
++ /* Different user context - keep the first entry.
++ Set the user context as the current one. */
++ Command->currentContext = Context->id;
++ }
++
++ /* Reset pointers. */
++ queueControl = gcvNULL;
++ previousEnd = gcvNULL;
++
++ /* Determine whether there are FE tasks to be performed. */
++ haveFETasks = (TaskTable->table[gcvBLOCK_COMMAND].head != gcvNULL);
++
++ /* Determine the size of the queue. */
++ queueSize = EntryCount * gcmSIZEOF(gcsVGCMDQUEUE);
++
++ /* Map the command queue into the kernel space. */
++ gcmkERR_BREAK(gckOS_MapUserPointer(
++ Command->os,
++ Queue,
++ queueSize,
++ (gctPOINTER *) &mappedQueue
++ ));
++
++ /* Set the first entry. */
++ userEntry = mappedQueue;
++
++ /* Process the command queue. */
++ while (EntryCount)
++ {
++ /* Lock the current queue. */
++ gcmkERR_BREAK(_LockCurrentQueue(
++ Command, &kernelEntry, &queueLength
++ ));
++
++ /* Determine the number of entries to process. */
++ currentLength = (queueLength < EntryCount)
++ ? queueLength
++ : EntryCount;
++
++ /* Update the number of the entries left to process. */
++ EntryCount -= currentLength;
++
++ /* Reset previous flags. */
++ previousDynamic = gcvFALSE;
++ previousExecuted = gcvFALSE;
++
++ /* Set the initial control index. */
++ controlIndex = 0;
++
++ /* Process entries. */
++ for (entriesQueued = 0; entriesQueued < currentLength; entriesQueued += 1)
++ {
++ /* Get the kernel pointer to the command buffer header. */
++ gcsCMDBUFFER_PTR commandBuffer = gcvNULL;
++ gcmkERR_BREAK(_ConvertUserCommandBufferPointer(
++ Command,
++ userEntry->commandBuffer,
++ &commandBuffer
++ ));
++
++ /* Is it a dynamic command buffer? */
++ if (userEntry->dynamic)
++ {
++ /* Select dynamic buffer control functions. */
++ queueControl = &_dynamicBuffer[controlIndex];
++ }
++
++ /* No, a static command buffer. */
++ else
++ {
++ /* Select static buffer control functions. */
++ queueControl = &_staticBuffer[controlIndex];
++ }
++
++ /* Set the command buffer pointer to the entry. */
++ kernelEntry->commandBuffer = commandBuffer;
++
++ /* If the previous entry was a dynamic command buffer,
++ link it to the current. */
++ if (previousDynamic)
++ {
++ gcmkERR_BREAK(gckVGCOMMAND_FetchCommand(
++ Command,
++ previousEnd,
++ commandBuffer->address,
++ commandBuffer->dataCount,
++ gcvNULL
++ ));
++
++ /* The buffer will be auto-executed, only need to
++ update it after it has been executed. */
++ kernelEntry->handler = queueControl->update;
++
++ /* The buffer is only being updated. */
++ previousExecuted = gcvFALSE;
++ }
++ else
++ {
++ /* Set the buffer up for execution. */
++ kernelEntry->handler = queueControl->execute;
++
++ /* The buffer is being updated. */
++ previousExecuted = gcvTRUE;
++ }
++
++ /* The current buffer's END command becomes the last END. */
++ previousEnd
++ = ((gctUINT8_PTR) commandBuffer)
++ + commandBuffer->bufferOffset
++ + commandBuffer->dataCount * Command->info.commandAlignment
++ - Command->info.staticTailSize;
++
++ /* Update the last entry info. */
++ previousDynamic = userEntry->dynamic;
++
++ /* Advance entries. */
++ userEntry += 1;
++ kernelEntry += 1;
++
++ /* Update the control index. */
++ controlIndex = 1;
++ }
++
++ /* If the previous entry was a dynamic command buffer,
++ terminate it with an END. */
++ if (previousDynamic)
++ {
++ gcmkERR_BREAK(gckVGCOMMAND_EndCommand(
++ Command,
++ previousEnd,
++ Command->info.feBufferInt,
++ gcvNULL
++ ));
++ }
++
++ /* Last buffer? */
++ if (EntryCount == 0)
++ {
++ /* Modify the last command buffer's routines to handle
++ tasks if any.*/
++ if (haveFETasks)
++ {
++ if (previousExecuted)
++ {
++ kernelEntry[-1].handler = queueControl->lastExecute;
++ }
++ else
++ {
++ kernelEntry[-1].handler = queueControl->lastUpdate;
++ }
++ }
++
++ /* Release the mutex. */
++ gcmkERR_BREAK(gckOS_ReleaseMutex(
++ Command->os,
++ Command->queueMutex
++ ));
++ /* Schedule tasks. */
++ gcmkERR_BREAK(_ScheduleTasks(Command, TaskTable, previousEnd));
++
++ /* Acquire the mutex. */
++ gcmkERR_BREAK(gckOS_AcquireMutex(
++ Command->os,
++ Command->queueMutex,
++ gcvINFINITE
++ ));
++ }
++
++ /* Unkock and schedule the current queue for execution. */
++ gcmkERR_BREAK(_UnlockCurrentQueue(
++ Command, currentLength
++ ));
++ }
++
++
++ /* Unmap the user command buffer. */
++ gcmkERR_BREAK(gckOS_UnmapUserPointer(
++ Command->os,
++ Queue,
++ queueSize,
++ mappedQueue
++ ));
++ }
++ while (gcvFALSE);
++
++ /* Release the mutex. */
++ gcmkCHECK_STATUS(gckOS_ReleaseMutex(
++ Command->os,
++ Command->commitMutex
++ ));
++
++ gcmkVERIFY_OK(gckOS_ReleaseSemaphore(
++ Command->os, Command->powerSemaphore));
++ }
++ while (gcvFALSE);
++
++ gcmkFOOTER();
++ /* Return status. */
++ return status;
++}
++
++#endif /* gcdENABLE_VG */
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_db.c linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_db.c
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_db.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_db.c 2015-07-27 23:13:06.190893891 +0200
+@@ -0,0 +1,1618 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_precomp.h"
++
++#define _GC_OBJ_ZONE gcvZONE_DATABASE
++
++/*******************************************************************************
++***** Private fuctions ********************************************************/
++
++#define _GetSlot(database, x) \
++ (gctUINT32)(((gcmPTR_TO_UINT64(x) >> 7) % gcmCOUNTOF(database->list)))
++
++/*******************************************************************************
++** gckKERNEL_NewDatabase
++**
++** Create a new database structure and insert it to the head of the hash list.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to a gckKERNEL object.
++**
++** gctUINT32 ProcessID
++** ProcessID that identifies the database.
++**
++** OUTPUT:
++**
++** gcsDATABASE_PTR * Database
++** Pointer to a variable receiving the database structure pointer on
++** success.
++*/
++static gceSTATUS
++gckKERNEL_NewDatabase(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ OUT gcsDATABASE_PTR * Database
++ )
++{
++ gceSTATUS status;
++ gcsDATABASE_PTR database;
++ gctBOOL acquired = gcvFALSE;
++ gctSIZE_T slot;
++ gcsDATABASE_PTR existingDatabase;
++
++ gcmkHEADER_ARG("Kernel=0x%x ProcessID=%d", Kernel, ProcessID);
++
++ /* Acquire the database mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(Kernel->os, Kernel->db->dbMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Compute the hash for the database. */
++ slot = ProcessID % gcmCOUNTOF(Kernel->db->db);
++
++ /* Walk the hash list. */
++ for (existingDatabase = Kernel->db->db[slot];
++ existingDatabase != gcvNULL;
++ existingDatabase = existingDatabase->next)
++ {
++ if (existingDatabase->processID == ProcessID)
++ {
++ /* One process can't be added twice. */
++ gcmkONERROR(gcvSTATUS_NOT_SUPPORTED);
++ }
++ }
++
++ if (Kernel->db->freeDatabase != gcvNULL)
++ {
++ /* Allocate a database from the free list. */
++ database = Kernel->db->freeDatabase;
++ Kernel->db->freeDatabase = database->next;
++ }
++ else
++ {
++ gctPOINTER pointer = gcvNULL;
++
++ /* Allocate a new database from the heap. */
++ gcmkONERROR(gckOS_Allocate(Kernel->os,
++ gcmSIZEOF(gcsDATABASE),
++ &pointer));
++
++ database = pointer;
++ }
++
++ /* Insert the database into the hash. */
++ database->next = Kernel->db->db[slot];
++ Kernel->db->db[slot] = database;
++
++ /* Save the hash slot. */
++ database->slot = slot;
++
++ /* Release the database mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex));
++
++ /* Return the database. */
++ *Database = database;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Database=0x%x", *Database);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ /* Release the database mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++** gckKERNEL_FindDatabase
++**
++** Find a database identified by a process ID and move it to the head of the
++** hash list.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to a gckKERNEL object.
++**
++** gctUINT32 ProcessID
++** ProcessID that identifies the database.
++**
++** gctBOOL LastProcessID
++** gcvTRUE if searching for the last known process ID. gcvFALSE if
++** we need to search for the process ID specified by the ProcessID
++** argument.
++**
++** OUTPUT:
++**
++** gcsDATABASE_PTR * Database
++** Pointer to a variable receiving the database structure pointer on
++** success.
++*/
++static gceSTATUS
++gckKERNEL_FindDatabase(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ IN gctBOOL LastProcessID,
++ OUT gcsDATABASE_PTR * Database
++ )
++{
++ gceSTATUS status;
++ gcsDATABASE_PTR database, previous;
++ gctSIZE_T slot;
++
++ gcmkHEADER_ARG("Kernel=0x%x ProcessID=%d LastProcessID=%d",
++ Kernel, ProcessID, LastProcessID);
++
++ /* Compute the hash for the database. */
++ slot = ProcessID % gcmCOUNTOF(Kernel->db->db);
++
++ /* Check whether we are getting the last known database. */
++ if (LastProcessID)
++ {
++ /* Use last database. */
++ database = Kernel->db->lastDatabase;
++
++ if (database == gcvNULL)
++ {
++ /* Database not found. */
++ gcmkONERROR(gcvSTATUS_INVALID_DATA);
++ }
++ }
++ else
++ {
++ /* Walk the hash list. */
++ for (previous = gcvNULL, database = Kernel->db->db[slot];
++ database != gcvNULL;
++ database = database->next)
++ {
++ if (database->processID == ProcessID)
++ {
++ /* Found it! */
++ break;
++ }
++
++ previous = database;
++ }
++
++ if (database == gcvNULL)
++ {
++ /* Database not found. */
++ gcmkONERROR(gcvSTATUS_INVALID_DATA);
++ }
++
++ if (previous != gcvNULL)
++ {
++ /* Move database to the head of the hash list. */
++ previous->next = database->next;
++ database->next = Kernel->db->db[slot];
++ Kernel->db->db[slot] = database;
++ }
++ }
++
++ /* Return the database. */
++ *Database = database;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Database=0x%x", *Database);
++ return gcvSTATUS_OK;
++
++OnError:
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++** gckKERNEL_DeleteDatabase
++**
++** Remove a database from the hash list and delete its structure.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to a gckKERNEL object.
++**
++** gcsDATABASE_PTR Database
++** Pointer to the database structure to remove.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++static gceSTATUS
++gckKERNEL_DeleteDatabase(
++ IN gckKERNEL Kernel,
++ IN gcsDATABASE_PTR Database
++ )
++{
++ gceSTATUS status;
++ gcsDATABASE_PTR database;
++
++ gcmkHEADER_ARG("Kernel=0x%x Database=0x%x", Kernel, Database);
++
++ /* Check slot value. */
++ gcmkVERIFY_ARGUMENT(Database->slot < gcmCOUNTOF(Kernel->db->db));
++
++ if (Database->slot < gcmCOUNTOF(Kernel->db->db))
++ {
++ /* Check if database if the head of the hash list. */
++ if (Kernel->db->db[Database->slot] == Database)
++ {
++ /* Remove the database from the hash list. */
++ Kernel->db->db[Database->slot] = Database->next;
++ }
++ else
++ {
++ /* Walk the has list to find the database. */
++ for (database = Kernel->db->db[Database->slot];
++ database != gcvNULL;
++ database = database->next
++ )
++ {
++ /* Check if the next list entry is this database. */
++ if (database->next == Database)
++ {
++ /* Remove the database from the hash list. */
++ database->next = Database->next;
++ break;
++ }
++ }
++
++ if (database == gcvNULL)
++ {
++ /* Ouch! Something got corrupted. */
++ gcmkONERROR(gcvSTATUS_INVALID_DATA);
++ }
++ }
++ }
++
++ if (Kernel->db->lastDatabase != gcvNULL)
++ {
++ /* Insert database to the free list. */
++ Kernel->db->lastDatabase->next = Kernel->db->freeDatabase;
++ Kernel->db->freeDatabase = Kernel->db->lastDatabase;
++ }
++
++ /* Keep database as the last database. */
++ Kernel->db->lastDatabase = Database;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++** gckKERNEL_NewRecord
++**
++** Create a new database record structure and insert it to the head of the
++** database.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to a gckKERNEL object.
++**
++** gcsDATABASE_PTR Database
++** Pointer to a database structure.
++**
++** OUTPUT:
++**
++** gcsDATABASE_RECORD_PTR * Record
++** Pointer to a variable receiving the database record structure
++** pointer on success.
++*/
++static gceSTATUS
++gckKERNEL_NewRecord(
++ IN gckKERNEL Kernel,
++ IN gcsDATABASE_PTR Database,
++ IN gctUINT32 Slot,
++ OUT gcsDATABASE_RECORD_PTR * Record
++ )
++{
++ gceSTATUS status;
++ gcsDATABASE_RECORD_PTR record = gcvNULL;
++
++ gcmkHEADER_ARG("Kernel=0x%x Database=0x%x", Kernel, Database);
++
++ if (Kernel->db->freeRecord != gcvNULL)
++ {
++ /* Allocate the record from the free list. */
++ record = Kernel->db->freeRecord;
++ Kernel->db->freeRecord = record->next;
++ }
++ else
++ {
++ gctPOINTER pointer = gcvNULL;
++
++ /* Allocate the record from the heap. */
++ gcmkONERROR(gckOS_Allocate(Kernel->os,
++ gcmSIZEOF(gcsDATABASE_RECORD),
++ &pointer));
++
++ record = pointer;
++ }
++
++ /* Insert the record in the database. */
++ record->next = Database->list[Slot];
++ Database->list[Slot] = record;
++
++ /* Return the record. */
++ *Record = record;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Record=0x%x", *Record);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (record != gcvNULL)
++ {
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Kernel->os, record));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++** gckKERNEL_DeleteRecord
++**
++** Remove a database record from the database and delete its structure.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to a gckKERNEL object.
++**
++** gcsDATABASE_PTR Database
++** Pointer to a database structure.
++**
++** gceDATABASE_TYPE Type
++** Type of the record to remove.
++**
++** gctPOINTER Data
++** Data of the record to remove.
++**
++** OUTPUT:
++**
++** gctSIZE_T_PTR Bytes
++** Pointer to a variable that receives the size of the record deleted.
++** Can be gcvNULL if the size is not required.
++*/
++static gceSTATUS
++gckKERNEL_DeleteRecord(
++ IN gckKERNEL Kernel,
++ IN gcsDATABASE_PTR Database,
++ IN gceDATABASE_TYPE Type,
++ IN gctPOINTER Data,
++ OUT gctSIZE_T_PTR Bytes OPTIONAL
++ )
++{
++ gceSTATUS status;
++ gcsDATABASE_RECORD_PTR record, previous;
++ gctUINT32 slot = _GetSlot(Database, Data);
++
++ gcmkHEADER_ARG("Kernel=0x%x Database=0x%x Type=%d Data=0x%x",
++ Kernel, Database, Type, Data);
++
++ /* Scan the database for this record. */
++ for (record = Database->list[slot], previous = gcvNULL;
++ record != gcvNULL;
++ record = record->next
++ )
++ {
++ if ((record->type == Type)
++ && (record->data == Data)
++ )
++ {
++ /* Found it! */
++ break;
++ }
++
++ previous = record;
++ }
++
++ if (record == gcvNULL)
++ {
++ /* Ouch! This record is not found? */
++ gcmkONERROR(gcvSTATUS_INVALID_DATA);
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return size of record. */
++ *Bytes = record->bytes;
++ }
++
++ /* Remove record from database. */
++ if (previous == gcvNULL)
++ {
++ Database->list[slot] = record->next;
++ }
++ else
++ {
++ previous->next = record->next;
++ }
++
++ /* Insert record in free list. */
++ record->next = Kernel->db->freeRecord;
++ Kernel->db->freeRecord = record;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Bytes=%lu", gcmOPT_VALUE(Bytes));
++ return gcvSTATUS_OK;
++
++OnError:
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++** gckKERNEL_FindRecord
++**
++** Find a database record from the database.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to a gckKERNEL object.
++**
++** gcsDATABASE_PTR Database
++** Pointer to a database structure.
++**
++** gceDATABASE_TYPE Type
++** Type of the record to remove.
++**
++** gctPOINTER Data
++** Data of the record to remove.
++**
++** OUTPUT:
++**
++** gctSIZE_T_PTR Bytes
++** Pointer to a variable that receives the size of the record deleted.
++** Can be gcvNULL if the size is not required.
++*/
++static gceSTATUS
++gckKERNEL_FindRecord(
++ IN gckKERNEL Kernel,
++ IN gcsDATABASE_PTR Database,
++ IN gceDATABASE_TYPE Type,
++ IN gctPOINTER Data,
++ OUT gcsDATABASE_RECORD_PTR Record
++ )
++{
++ gceSTATUS status;
++ gcsDATABASE_RECORD_PTR record;
++ gctUINT32 slot = _GetSlot(Database, Data);
++
++ gcmkHEADER_ARG("Kernel=0x%x Database=0x%x Type=%d Data=0x%x",
++ Kernel, Database, Type, Data);
++
++ /* Scan the database for this record. */
++ for (record = Database->list[slot];
++ record != gcvNULL;
++ record = record->next
++ )
++ {
++ if ((record->type == Type)
++ && (record->data == Data)
++ )
++ {
++ /* Found it! */
++ break;
++ }
++ }
++
++ if (record == gcvNULL)
++ {
++ /* Ouch! This record is not found? */
++ gcmkONERROR(gcvSTATUS_INVALID_DATA);
++ }
++
++ if (Record != gcvNULL)
++ {
++ /* Return information of record. */
++ gcmkONERROR(
++ gckOS_MemCopy(Record, record, sizeof(gcsDATABASE_RECORD)));
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("Record=0x%x", Record);
++ return gcvSTATUS_OK;
++
++OnError:
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++
++/*******************************************************************************
++***** Public API **************************************************************/
++
++/*******************************************************************************
++** gckKERNEL_CreateProcessDB
++**
++** Create a new process database.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to a gckKERNEL object.
++**
++** gctUINT32 ProcessID
++** Process ID used to identify the database.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckKERNEL_CreateProcessDB(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID
++ )
++{
++ gceSTATUS status;
++ gcsDATABASE_PTR database = gcvNULL;
++ gctUINT32 i;
++
++ gcmkHEADER_ARG("Kernel=0x%x ProcessID=%d", Kernel, ProcessID);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++
++ /* Create a new database. */
++ gcmkONERROR(gckKERNEL_NewDatabase(Kernel, ProcessID, &database));
++
++ /* Initialize the database. */
++ database->processID = ProcessID;
++ database->vidMem.bytes = 0;
++ database->vidMem.maxBytes = 0;
++ database->vidMem.totalBytes = 0;
++ database->nonPaged.bytes = 0;
++ database->nonPaged.maxBytes = 0;
++ database->nonPaged.totalBytes = 0;
++ database->contiguous.bytes = 0;
++ database->contiguous.maxBytes = 0;
++ database->contiguous.totalBytes = 0;
++ database->mapMemory.bytes = 0;
++ database->mapMemory.maxBytes = 0;
++ database->mapMemory.totalBytes = 0;
++ database->mapUserMemory.bytes = 0;
++ database->mapUserMemory.maxBytes = 0;
++ database->mapUserMemory.totalBytes = 0;
++ database->vidMemResv.bytes = 0;
++ database->vidMemResv.maxBytes = 0;
++ database->vidMemResv.totalBytes = 0;
++ database->vidMemCont.bytes = 0;
++ database->vidMemCont.maxBytes = 0;
++ database->vidMemCont.totalBytes = 0;
++ database->vidMemVirt.bytes = 0;
++ database->vidMemVirt.maxBytes = 0;
++ database->vidMemVirt.totalBytes = 0;
++
++ for (i = 0; i < gcmCOUNTOF(database->list); i++)
++ {
++ database->list[i] = gcvNULL;
++ }
++
++#if gcdSECURE_USER
++ {
++ gctINT slot;
++ gcskSECURE_CACHE * cache = &database->cache;
++
++ /* Setup the linked list of cache nodes. */
++ for (slot = 1; slot <= gcdSECURE_CACHE_SLOTS; ++slot)
++ {
++ cache->cache[slot].logical = gcvNULL;
++
++#if gcdSECURE_CACHE_METHOD != gcdSECURE_CACHE_TABLE
++ cache->cache[slot].prev = &cache->cache[slot - 1];
++ cache->cache[slot].next = &cache->cache[slot + 1];
++# endif
++#if gcdSECURE_CACHE_METHOD == gcdSECURE_CACHE_HASH
++ cache->cache[slot].nextHash = gcvNULL;
++ cache->cache[slot].prevHash = gcvNULL;
++# endif
++ }
++
++#if gcdSECURE_CACHE_METHOD != gcdSECURE_CACHE_TABLE
++ /* Setup the head and tail of the cache. */
++ cache->cache[0].next = &cache->cache[1];
++ cache->cache[0].prev = &cache->cache[gcdSECURE_CACHE_SLOTS];
++ cache->cache[0].logical = gcvNULL;
++
++ /* Fix up the head and tail pointers. */
++ cache->cache[0].next->prev = &cache->cache[0];
++ cache->cache[0].prev->next = &cache->cache[0];
++# endif
++
++#if gcdSECURE_CACHE_METHOD == gcdSECURE_CACHE_HASH
++ /* Zero out the hash table. */
++ for (slot = 0; slot < gcmCOUNTOF(cache->hash); ++slot)
++ {
++ cache->hash[slot].logical = gcvNULL;
++ cache->hash[slot].nextHash = gcvNULL;
++ }
++# endif
++
++ /* Initialize cache index. */
++ cache->cacheIndex = gcvNULL;
++ cache->cacheFree = 1;
++ cache->cacheStamp = 0;
++ }
++#endif
++
++ /* Reset idle timer. */
++ Kernel->db->lastIdle = 0;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++** gckKERNEL_AddProcessDB
++**
++** Add a record to a process database.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to a gckKERNEL object.
++**
++** gctUINT32 ProcessID
++** Process ID used to identify the database.
++**
++** gceDATABASE_TYPE TYPE
++** Type of the record to add.
++**
++** gctPOINTER Pointer
++** Data of the record to add.
++**
++** gctPHYS_ADDR Physical
++** Physical address of the record to add.
++**
++** gctSIZE_T Size
++** Size of the record to add.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckKERNEL_AddProcessDB(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ IN gceDATABASE_TYPE Type,
++ IN gctPOINTER Pointer,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Size
++ )
++{
++ gceSTATUS status;
++ gcsDATABASE_PTR database;
++ gcsDATABASE_RECORD_PTR record = gcvNULL;
++ gcsDATABASE_COUNTERS * count;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Kernel=0x%x ProcessID=%d Type=%d Pointer=0x%x "
++ "Physical=0x%x Size=%lu",
++ Kernel, ProcessID, Type, Pointer, Physical, Size);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++
++ /* Acquire the database mutex. */
++ gcmkONERROR(
++ gckOS_AcquireMutex(Kernel->os, Kernel->db->dbMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Special case the idle record. */
++ if (Type == gcvDB_IDLE)
++ {
++ gctUINT64 time;
++
++ /* Get the current profile time. */
++ gcmkONERROR(gckOS_GetProfileTick(&time));
++
++ if ((ProcessID == 0) && (Kernel->db->lastIdle != 0))
++ {
++ /* Out of idle, adjust time it was idle. */
++ Kernel->db->idleTime += time - Kernel->db->lastIdle;
++ Kernel->db->lastIdle = 0;
++ }
++ else if (ProcessID == 1)
++ {
++ /* Save current idle time. */
++ Kernel->db->lastIdle = time;
++ }
++
++#if gcdDYNAMIC_SPEED
++ {
++ /* Test for first call. */
++ if (Kernel->db->lastSlowdown == 0)
++ {
++ /* Save milliseconds. */
++ Kernel->db->lastSlowdown = time;
++ Kernel->db->lastSlowdownIdle = Kernel->db->idleTime;
++ }
++ else
++ {
++ /* Compute ellapsed time in milliseconds. */
++ gctUINT delta = gckOS_ProfileToMS(time - Kernel->db->lastSlowdown);
++
++ /* Test for end of period. */
++ if (delta >= gcdDYNAMIC_SPEED)
++ {
++ /* Compute number of idle milliseconds. */
++ gctUINT idle = gckOS_ProfileToMS(
++ Kernel->db->idleTime - Kernel->db->lastSlowdownIdle);
++
++ /* Broadcast to slow down the GPU. */
++ gcmkONERROR(gckOS_BroadcastCalibrateSpeed(Kernel->os,
++ Kernel->hardware,
++ idle,
++ delta));
++
++ /* Save current time. */
++ Kernel->db->lastSlowdown = time;
++ Kernel->db->lastSlowdownIdle = Kernel->db->idleTime;
++ }
++ }
++ }
++#endif
++ /* Release the database mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++
++ /* Verify the arguments. */
++ gcmkVERIFY_ARGUMENT(Pointer != gcvNULL);
++
++
++ /* Find the database. */
++ gcmkONERROR(gckKERNEL_FindDatabase(Kernel, ProcessID, gcvFALSE, &database));
++
++ /* Create a new record in the database. */
++ gcmkONERROR(gckKERNEL_NewRecord(Kernel, database, _GetSlot(database, Pointer), &record));
++
++ /* Initialize the record. */
++ record->kernel = Kernel;
++ record->type = Type;
++ record->data = Pointer;
++ record->physical = Physical;
++ record->bytes = Size;
++
++ /* Get pointer to counters. */
++ switch (Type)
++ {
++ case gcvDB_VIDEO_MEMORY:
++ count = &database->vidMem;
++ break;
++
++ case gcvDB_NON_PAGED:
++ count = &database->nonPaged;
++ break;
++
++ case gcvDB_CONTIGUOUS:
++ count = &database->contiguous;
++ break;
++
++ case gcvDB_MAP_MEMORY:
++ count = &database->mapMemory;
++ break;
++
++ case gcvDB_MAP_USER_MEMORY:
++ count = &database->mapUserMemory;
++ break;
++
++ case gcvDB_VIDEO_MEMORY_RESERVED:
++ count = &database->vidMemResv;
++ break;
++
++ case gcvDB_VIDEO_MEMORY_CONTIGUOUS:
++ count = &database->vidMemCont;
++ break;
++
++ case gcvDB_VIDEO_MEMORY_VIRTUAL:
++ count = &database->vidMemVirt;
++ break;
++
++ default:
++ count = gcvNULL;
++ break;
++ }
++
++ if (count != gcvNULL)
++ {
++ /* Adjust counters. */
++ count->totalBytes += Size;
++ count->bytes += Size;
++
++ if (count->bytes > count->maxBytes)
++ {
++ count->maxBytes = count->bytes;
++ }
++ }
++
++ /* Release the database mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ /* Release the database mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++** gckKERNEL_RemoveProcessDB
++**
++** Remove a record from a process database.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to a gckKERNEL object.
++**
++** gctUINT32 ProcessID
++** Process ID used to identify the database.
++**
++** gceDATABASE_TYPE TYPE
++** Type of the record to remove.
++**
++** gctPOINTER Pointer
++** Data of the record to remove.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckKERNEL_RemoveProcessDB(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ IN gceDATABASE_TYPE Type,
++ IN gctPOINTER Pointer
++ )
++{
++ gceSTATUS status;
++ gcsDATABASE_PTR database;
++ gctSIZE_T bytes = 0;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Kernel=0x%x ProcessID=%d Type=%d Pointer=0x%x",
++ Kernel, ProcessID, Type, Pointer);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(Pointer != gcvNULL);
++
++ /* Acquire the database mutex. */
++ gcmkONERROR(
++ gckOS_AcquireMutex(Kernel->os, Kernel->db->dbMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Find the database. */
++ gcmkONERROR(gckKERNEL_FindDatabase(Kernel, ProcessID, gcvFALSE, &database));
++
++ /* Delete the record. */
++ gcmkONERROR(
++ gckKERNEL_DeleteRecord(Kernel, database, Type, Pointer, &bytes));
++
++ /* Update counters. */
++ switch (Type)
++ {
++ case gcvDB_VIDEO_MEMORY:
++ database->vidMem.bytes -= bytes;
++ break;
++
++ case gcvDB_NON_PAGED:
++ database->nonPaged.bytes -= bytes;
++ break;
++
++ case gcvDB_CONTIGUOUS:
++ database->contiguous.bytes -= bytes;
++ break;
++
++ case gcvDB_MAP_MEMORY:
++ database->mapMemory.bytes -= bytes;
++ break;
++
++ case gcvDB_MAP_USER_MEMORY:
++ database->mapUserMemory.bytes -= bytes;
++ break;
++
++ case gcvDB_VIDEO_MEMORY_RESERVED:
++ database->vidMemResv.bytes -= bytes;
++ break;
++
++ case gcvDB_VIDEO_MEMORY_CONTIGUOUS:
++ database->vidMemCont.bytes -= bytes;
++ break;
++
++ case gcvDB_VIDEO_MEMORY_VIRTUAL:
++ database->vidMemVirt.bytes -= bytes;
++ break;
++
++ default:
++ break;
++ }
++
++ /* Release the database mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ /* Release the database mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++** gckKERNEL_FindProcessDB
++**
++** Find a record from a process database.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to a gckKERNEL object.
++**
++** gctUINT32 ProcessID
++** Process ID used to identify the database.
++**
++** gceDATABASE_TYPE TYPE
++** Type of the record to remove.
++**
++** gctPOINTER Pointer
++** Data of the record to remove.
++**
++** OUTPUT:
++**
++** gcsDATABASE_RECORD_PTR Record
++** Copy of record.
++*/
++gceSTATUS
++gckKERNEL_FindProcessDB(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ IN gctUINT32 ThreadID,
++ IN gceDATABASE_TYPE Type,
++ IN gctPOINTER Pointer,
++ OUT gcsDATABASE_RECORD_PTR Record
++ )
++{
++ gceSTATUS status;
++ gcsDATABASE_PTR database;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Kernel=0x%x ProcessID=%d Type=%d Pointer=0x%x",
++ Kernel, ProcessID, ThreadID, Type, Pointer);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(Pointer != gcvNULL);
++
++ /* Acquire the database mutex. */
++ gcmkONERROR(
++ gckOS_AcquireMutex(Kernel->os, Kernel->db->dbMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Find the database. */
++ gcmkONERROR(gckKERNEL_FindDatabase(Kernel, ProcessID, gcvFALSE, &database));
++
++ /* Find the record. */
++ gcmkONERROR(
++ gckKERNEL_FindRecord(Kernel, database, Type, Pointer, Record));
++
++ /* Release the database mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ /* Release the database mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++** gckKERNEL_DestroyProcessDB
++**
++** Destroy a process database. If the database contains any records, the data
++** inside those records will be deleted as well. This aids in the cleanup if
++** a process has died unexpectedly or has memory leaks.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to a gckKERNEL object.
++**
++** gctUINT32 ProcessID
++** Process ID used to identify the database.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckKERNEL_DestroyProcessDB(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID
++ )
++{
++ gceSTATUS status;
++ gcsDATABASE_PTR database;
++ gcsDATABASE_RECORD_PTR record, next;
++ gctBOOL asynchronous;
++ gctPHYS_ADDR physical;
++ gcuVIDMEM_NODE_PTR node;
++ gckKERNEL kernel = Kernel;
++ gctUINT32 i;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Kernel=0x%x ProcessID=%d", Kernel, ProcessID);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++
++ /* Acquire the database mutex. */
++ gcmkONERROR(
++ gckOS_AcquireMutex(Kernel->os, Kernel->db->dbMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Find the database. */
++ gcmkONERROR(gckKERNEL_FindDatabase(Kernel, ProcessID, gcvFALSE, &database));
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_DATABASE,
++ "DB(%d): VidMem: total=%lu max=%lu",
++ ProcessID, database->vidMem.totalBytes,
++ database->vidMem.maxBytes);
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_DATABASE,
++ "DB(%d): NonPaged: total=%lu max=%lu",
++ ProcessID, database->nonPaged.totalBytes,
++ database->nonPaged.maxBytes);
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_DATABASE,
++ "DB(%d): Contiguous: total=%lu max=%lu",
++ ProcessID, database->contiguous.totalBytes,
++ database->contiguous.maxBytes);
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_DATABASE,
++ "DB(%d): Idle time=%llu",
++ ProcessID, Kernel->db->idleTime);
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_DATABASE,
++ "DB(%d): Map: total=%lu max=%lu",
++ ProcessID, database->mapMemory.totalBytes,
++ database->mapMemory.maxBytes);
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_DATABASE,
++ "DB(%d): Map: total=%lu max=%lu",
++ ProcessID, database->mapUserMemory.totalBytes,
++ database->mapUserMemory.maxBytes);
++
++ if (database->list != gcvNULL)
++ {
++ gcmkTRACE_ZONE(gcvLEVEL_WARNING, gcvZONE_DATABASE,
++ "Process %d has entries in its database:",
++ ProcessID);
++ }
++
++ for(i = 0; i < gcmCOUNTOF(database->list); i++)
++ {
++
++ /* Walk all records. */
++ for (record = database->list[i]; record != gcvNULL; record = next)
++ {
++ /* Next next record. */
++ next = record->next;
++
++ gcmkONERROR(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex));
++ acquired = gcvFALSE;
++
++ /* Dispatch on record type. */
++ switch (record->type)
++ {
++ case gcvDB_VIDEO_MEMORY:
++ /* Free the video memory. */
++ status = gckVIDMEM_Free(Kernel, gcmUINT64_TO_PTR(record->data));
++
++ gcmkTRACE_ZONE(gcvLEVEL_WARNING, gcvZONE_DATABASE,
++ "DB: VIDEO_MEMORY 0x%x (status=%d)",
++ record->data, status);
++ break;
++
++ case gcvDB_NON_PAGED:
++ physical = gcmNAME_TO_PTR(record->physical);
++ /* Unmap user logical memory first. */
++ status = gckOS_UnmapUserLogical(Kernel->os,
++ physical,
++ record->bytes,
++ record->data);
++
++ /* Free the non paged memory. */
++ status = gckOS_FreeNonPagedMemory(Kernel->os,
++ record->bytes,
++ physical,
++ record->data);
++ gcmRELEASE_NAME(record->physical);
++
++ gcmkTRACE_ZONE(gcvLEVEL_WARNING, gcvZONE_DATABASE,
++ "DB: NON_PAGED 0x%x, bytes=%lu (status=%d)",
++ record->data, record->bytes, status);
++ break;
++
++#if gcdVIRTUAL_COMMAND_BUFFER
++ case gcvDB_COMMAND_BUFFER:
++ /* Free the command buffer. */
++ status = gckEVENT_DestroyVirtualCommandBuffer(record->kernel->eventObj,
++ record->bytes,
++ gcmNAME_TO_PTR(record->physical),
++ record->data,
++ gcvKERNEL_PIXEL);
++ gcmRELEASE_NAME(record->physical);
++
++ gcmkTRACE_ZONE(gcvLEVEL_WARNING, gcvZONE_DATABASE,
++ "DB: COMMAND_BUFFER 0x%x, bytes=%lu (status=%d)",
++ record->data, record->bytes, status);
++ break;
++#endif
++
++ case gcvDB_CONTIGUOUS:
++ physical = gcmNAME_TO_PTR(record->physical);
++ /* Unmap user logical memory first. */
++ status = gckOS_UnmapUserLogical(Kernel->os,
++ physical,
++ record->bytes,
++ record->data);
++
++ /* Free the contiguous memory. */
++ status = gckEVENT_FreeContiguousMemory(Kernel->eventObj,
++ record->bytes,
++ physical,
++ record->data,
++ gcvKERNEL_PIXEL);
++ gcmRELEASE_NAME(record->physical);
++
++ gcmkTRACE_ZONE(gcvLEVEL_WARNING, gcvZONE_DATABASE,
++ "DB: CONTIGUOUS 0x%x bytes=%lu (status=%d)",
++ record->data, record->bytes, status);
++ break;
++
++ case gcvDB_SIGNAL:
++#if USE_NEW_LINUX_SIGNAL
++ status = gcvSTATUS_NOT_SUPPORTED;
++#else
++ /* Free the user signal. */
++ status = gckOS_DestroyUserSignal(Kernel->os,
++ gcmPTR2INT(record->data));
++#endif /* USE_NEW_LINUX_SIGNAL */
++
++ gcmkTRACE_ZONE(gcvLEVEL_WARNING, gcvZONE_DATABASE,
++ "DB: SIGNAL %d (status=%d)",
++ (gctINT)(gctUINTPTR_T)record->data, status);
++ break;
++
++ case gcvDB_VIDEO_MEMORY_LOCKED:
++ node = gcmUINT64_TO_PTR(record->data);
++ /* Unlock what we still locked */
++ status = gckVIDMEM_Unlock(record->kernel,
++ node,
++ gcvSURF_TYPE_UNKNOWN,
++ &asynchronous);
++
++ if (gcmIS_SUCCESS(status) && (gcvTRUE == asynchronous))
++ {
++ /* TODO: we maybe need to schedule a event here */
++ status = gckVIDMEM_Unlock(record->kernel,
++ node,
++ gcvSURF_TYPE_UNKNOWN,
++ gcvNULL);
++ }
++
++ gcmkTRACE_ZONE(gcvLEVEL_WARNING, gcvZONE_DATABASE,
++ "DB: VIDEO_MEMORY_LOCKED 0x%x (status=%d)",
++ node, status);
++ break;
++
++ case gcvDB_CONTEXT:
++ /* TODO: Free the context */
++ status = gckCOMMAND_Detach(Kernel->command, gcmNAME_TO_PTR(record->data));
++ gcmRELEASE_NAME(record->data);
++
++ gcmkTRACE_ZONE(gcvLEVEL_WARNING, gcvZONE_DATABASE,
++ "DB: CONTEXT 0x%x (status=%d)",
++ record->data, status);
++ break;
++
++ case gcvDB_MAP_MEMORY:
++ /* Unmap memory. */
++ status = gckKERNEL_UnmapMemory(Kernel,
++ record->physical,
++ record->bytes,
++ record->data);
++
++ gcmkTRACE_ZONE(gcvLEVEL_WARNING, gcvZONE_DATABASE,
++ "DB: MAP MEMORY %d (status=%d)",
++ gcmPTR2INT(record->data), status);
++ break;
++
++ case gcvDB_MAP_USER_MEMORY:
++ /* TODO: Unmap user memory. */
++ status = gckOS_UnmapUserMemory(Kernel->os,
++ Kernel->core,
++ record->physical,
++ record->bytes,
++ gcmNAME_TO_PTR(record->data),
++ 0);
++ gcmRELEASE_NAME(record->data);
++
++ gcmkTRACE_ZONE(gcvLEVEL_WARNING, gcvZONE_DATABASE,
++ "DB: MAP USER MEMORY %d (status=%d)",
++ gcmPTR2INT(record->data), status);
++ break;
++
++ case gcvDB_SHARED_INFO:
++ status = gckOS_FreeMemory(Kernel->os, record->physical);
++ break;
++
++#if gcdANDROID_NATIVE_FENCE_SYNC
++ case gcvDB_SYNC_POINT:
++ /* Free the user signal. */
++ status = gckOS_DestroySyncPoint(Kernel->os,
++ (gctSYNC_POINT) record->data);
++
++ gcmkTRACE_ZONE(gcvLEVEL_WARNING, gcvZONE_DATABASE,
++ "DB: SYNC POINT %d (status=%d)",
++ (gctINT)(gctUINTPTR_T)record->data, status);
++ break;
++#endif
++
++ case gcvDB_VIDEO_MEMORY_RESERVED:
++ case gcvDB_VIDEO_MEMORY_CONTIGUOUS:
++ case gcvDB_VIDEO_MEMORY_VIRTUAL:
++ break;//Nothing to do
++
++ default:
++ gcmkTRACE_ZONE(gcvLEVEL_ERROR, gcvZONE_DATABASE,
++ "DB: Correcupted record=0x%08x type=%d",
++ record, record->type);
++ break;
++ }
++
++ gcmkONERROR(
++ gckOS_AcquireMutex(Kernel->os, Kernel->db->dbMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Delete the record. */
++ gcmkONERROR(gckKERNEL_DeleteRecord(Kernel,
++ database,
++ record->type,
++ record->data,
++ gcvNULL));
++ }
++
++ }
++
++ /* Delete the database. */
++ gcmkONERROR(gckKERNEL_DeleteDatabase(Kernel, database));
++
++ /* Release the database mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ /* Release the database mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++** gckKERNEL_QueryProcessDB
++**
++** Query a process database for the current usage of a particular record type.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to a gckKERNEL object.
++**
++** gctUINT32 ProcessID
++** Process ID used to identify the database.
++**
++** gctBOOL LastProcessID
++** gcvTRUE if searching for the last known process ID. gcvFALSE if
++** we need to search for the process ID specified by the ProcessID
++** argument.
++**
++** gceDATABASE_TYPE Type
++** Type of the record to query.
++**
++** OUTPUT:
++**
++** gcuDATABASE_INFO * Info
++** Pointer to a variable that receives the requested information.
++*/
++gceSTATUS
++gckKERNEL_QueryProcessDB(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ IN gctBOOL LastProcessID,
++ IN gceDATABASE_TYPE Type,
++ OUT gcuDATABASE_INFO * Info
++ )
++{
++ gceSTATUS status;
++ gcsDATABASE_PTR database;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Kernel=0x%x ProcessID=%d Type=%d Info=0x%x",
++ Kernel, ProcessID, Type, Info);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(Info != gcvNULL);
++
++ /* Acquire the database mutex. */
++ gcmkONERROR(
++ gckOS_AcquireMutex(Kernel->os, Kernel->db->dbMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Find the database. */
++ gcmkONERROR(
++ gckKERNEL_FindDatabase(Kernel, ProcessID, LastProcessID, &database));
++
++ /* Get pointer to counters. */
++ switch (Type)
++ {
++ case gcvDB_VIDEO_MEMORY:
++ gckOS_MemCopy(&Info->counters,
++ &database->vidMem,
++ gcmSIZEOF(database->vidMem));
++ break;
++
++ case gcvDB_NON_PAGED:
++ gckOS_MemCopy(&Info->counters,
++ &database->nonPaged,
++ gcmSIZEOF(database->vidMem));
++ break;
++
++ case gcvDB_CONTIGUOUS:
++ gckOS_MemCopy(&Info->counters,
++ &database->contiguous,
++ gcmSIZEOF(database->vidMem));
++ break;
++
++ case gcvDB_IDLE:
++ Info->time = Kernel->db->idleTime;
++ Kernel->db->idleTime = 0;
++ break;
++
++ case gcvDB_MAP_MEMORY:
++ gckOS_MemCopy(&Info->counters,
++ &database->mapMemory,
++ gcmSIZEOF(database->mapMemory));
++ break;
++
++ case gcvDB_MAP_USER_MEMORY:
++ gckOS_MemCopy(&Info->counters,
++ &database->mapUserMemory,
++ gcmSIZEOF(database->mapUserMemory));
++ break;
++
++ case gcvDB_VIDEO_MEMORY_RESERVED:
++ gckOS_MemCopy(&Info->counters,
++ &database->vidMemResv,
++ gcmSIZEOF(database->vidMemResv));
++ break;
++
++ case gcvDB_VIDEO_MEMORY_CONTIGUOUS:
++ gckOS_MemCopy(&Info->counters,
++ &database->vidMemCont,
++ gcmSIZEOF(database->vidMemCont));
++ break;
++
++ case gcvDB_VIDEO_MEMORY_VIRTUAL:
++ gckOS_MemCopy(&Info->counters,
++ &database->vidMemVirt,
++ gcmSIZEOF(database->vidMemVirt));
++ break;
++
++ default:
++ break;
++ }
++
++ /* Release the database mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ /* Release the database mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++#if gcdSECURE_USER
++/*******************************************************************************
++** gckKERNEL_GetProcessDBCache
++**
++** Get teh secure cache from a process database.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to a gckKERNEL object.
++**
++** gctUINT32 ProcessID
++** Process ID used to identify the database.
++**
++** OUTPUT:
++**
++** gcskSECURE_CACHE_PTR * Cache
++** Pointer to a variable that receives the secure cache pointer.
++*/
++gceSTATUS
++gckKERNEL_GetProcessDBCache(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ OUT gcskSECURE_CACHE_PTR * Cache
++ )
++{
++ gceSTATUS status;
++ gcsDATABASE_PTR database;
++
++ gcmkHEADER_ARG("Kernel=0x%x ProcessID=%d", Kernel, ProcessID);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(Cache != gcvNULL);
++
++ /* Find the database. */
++ gcmkONERROR(gckKERNEL_FindDatabase(Kernel, ProcessID, gcvFALSE, &database));
++
++ /* Return the pointer to the cache. */
++ *Cache = &database->cache;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Cache=0x%x", *Cache);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++#endif
++
++gceSTATUS
++gckKERNEL_DumpProcessDB(
++ IN gckKERNEL Kernel
++ )
++{
++ gcsDATABASE_PTR database;
++ gctINT i, pid;
++ gctUINT8 name[24];
++
++ gcmkHEADER_ARG("Kernel=0x%x", Kernel);
++
++ /* Acquire the database mutex. */
++ gcmkVERIFY_OK(
++ gckOS_AcquireMutex(Kernel->os, Kernel->db->dbMutex, gcvINFINITE));
++
++ gcmkPRINT("**************************\n");
++ gcmkPRINT("*** PROCESS DB DUMP ***\n");
++ gcmkPRINT("**************************\n");
++
++ gcmkPRINT_N(8, "%-8s%s\n", "PID", "NAME");
++ /* Walk the databases. */
++ for (i = 0; i < gcmCOUNTOF(Kernel->db->db); ++i)
++ {
++ for (database = Kernel->db->db[i];
++ database != gcvNULL;
++ database = database->next)
++ {
++ pid = database->processID;
++
++ gcmkVERIFY_OK(gckOS_ZeroMemory(name, gcmSIZEOF(name)));
++
++ gcmkVERIFY_OK(gckOS_GetProcessNameByPid(pid, gcmSIZEOF(name), name));
++
++ gcmkPRINT_N(8, "%-8d%s\n", pid, name);
++ }
++ }
++
++ /* Release the database mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_debug.c linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_debug.c
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_debug.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_debug.c 2015-07-27 23:13:06.190893891 +0200
+@@ -0,0 +1,2559 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_precomp.h"
++#include <gc_hal_kernel_debug.h>
++
++/******************************************************************************\
++******************************** Debug Variables *******************************
++\******************************************************************************/
++
++static gceSTATUS _lastError = gcvSTATUS_OK;
++static gctUINT32 _debugLevel = gcvLEVEL_ERROR;
++/*
++_debugZones config value
++Please Reference define in gc_hal_base.h
++*/
++static gctUINT32 _debugZones = gcvZONE_NONE;
++
++/******************************************************************************\
++********************************* Debug Switches *******************************
++\******************************************************************************/
++
++/*
++ gcdBUFFERED_OUTPUT
++
++ When set to non-zero, all output is collected into a buffer with the
++ specified size. Once the buffer gets full, the debug buffer will be
++ printed to the console. gcdBUFFERED_SIZE determines the size of the buffer.
++*/
++#define gcdBUFFERED_OUTPUT 0
++
++/*
++ gcdBUFFERED_SIZE
++
++ When set to non-zero, all output is collected into a buffer with the
++ specified size. Once the buffer gets full, the debug buffer will be
++ printed to the console.
++*/
++#define gcdBUFFERED_SIZE (1024 * 1024 * 2)
++
++/*
++ gcdDMA_BUFFER_COUNT
++
++ If greater then zero, the debugger will attempt to find the command buffer
++ where DMA is currently executing and then print this buffer and
++ (gcdDMA_BUFFER_COUNT - 1) buffers before the current one. If set to zero
++ or the current buffer is not found, all buffers are printed.
++*/
++#define gcdDMA_BUFFER_COUNT 0
++
++/*
++ gcdTHREAD_BUFFERS
++
++ When greater then one, will accumulate messages from the specified number
++ of threads in separate output buffers.
++*/
++#define gcdTHREAD_BUFFERS 1
++
++/*
++ gcdENABLE_OVERFLOW
++
++ When set to non-zero, and the output buffer gets full, instead of being
++ printed, it will be allowed to overflow removing the oldest messages.
++*/
++#define gcdENABLE_OVERFLOW 1
++
++/*
++ gcdSHOW_LINE_NUMBER
++
++ When enabledm each print statement will be preceeded with the current
++ line number.
++*/
++#define gcdSHOW_LINE_NUMBER 0
++
++/*
++ gcdSHOW_PROCESS_ID
++
++ When enabledm each print statement will be preceeded with the current
++ process ID.
++*/
++#define gcdSHOW_PROCESS_ID 0
++
++/*
++ gcdSHOW_THREAD_ID
++
++ When enabledm each print statement will be preceeded with the current
++ thread ID.
++*/
++#define gcdSHOW_THREAD_ID 0
++
++/*
++ gcdSHOW_TIME
++
++ When enabled each print statement will be preceeded with the current
++ high-resolution time.
++*/
++#define gcdSHOW_TIME 0
++
++
++/******************************************************************************\
++****************************** Miscellaneous Macros ****************************
++\******************************************************************************/
++
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++# define gcmDBGASSERT(Expression, Format, Value) \
++ if (!(Expression)) \
++ { \
++ _DirectPrint( \
++ "*** gcmDBGASSERT ***************************\n" \
++ " function : %s\n" \
++ " line : %d\n" \
++ " expression : " #Expression "\n" \
++ " actual value : " Format "\n", \
++ __FUNCTION__, __LINE__, Value \
++ ); \
++ }
++#else
++# define gcmDBGASSERT(Expression, Format, Value)
++#endif
++
++#define gcmPTRALIGNMENT(Pointer, Alignemnt) \
++( \
++ gcmALIGN(gcmPTR2INT(Pointer), Alignemnt) - gcmPTR2INT(Pointer) \
++)
++
++#if gcdALIGNBYSIZE
++# define gcmISALIGNED(Offset, Alignment) \
++ (((Offset) & ((Alignment) - 1)) == 0)
++
++# define gcmkALIGNPTR(Type, Pointer, Alignment) \
++ Pointer = (Type) gcmINT2PTR(gcmALIGN(gcmPTR2INT(Pointer), Alignment))
++#else
++# define gcmISALIGNED(Offset, Alignment) \
++ gcvTRUE
++
++# define gcmkALIGNPTR(Type, Pointer, Alignment)
++#endif
++
++#define gcmALIGNSIZE(Offset, Size) \
++ ((Size - Offset) + Size)
++
++#define gcdHAVEPREFIX \
++( \
++ gcdSHOW_TIME \
++ || gcdSHOW_LINE_NUMBER \
++ || gcdSHOW_PROCESS_ID \
++ || gcdSHOW_THREAD_ID \
++)
++
++#if gcdHAVEPREFIX
++
++# define gcdOFFSET 0
++
++#if gcdSHOW_TIME
++#if gcmISALIGNED(gcdOFFSET, 8)
++# define gcdTIMESIZE gcmSIZEOF(gctUINT64)
++# elif gcdOFFSET == 4
++# define gcdTIMESIZE gcmALIGNSIZE(4, gcmSIZEOF(gctUINT64))
++# else
++# error "Unexpected offset value."
++# endif
++# undef gcdOFFSET
++# define gcdOFFSET 8
++#if !defined(gcdPREFIX_LEADER)
++# define gcdPREFIX_LEADER gcmSIZEOF(gctUINT64)
++# define gcdTIMEFORMAT "0x%016llX"
++# else
++# define gcdTIMEFORMAT ", 0x%016llX"
++# endif
++# else
++# define gcdTIMESIZE 0
++# define gcdTIMEFORMAT
++# endif
++
++#if gcdSHOW_LINE_NUMBER
++#if gcmISALIGNED(gcdOFFSET, 8)
++# define gcdNUMSIZE gcmSIZEOF(gctUINT64)
++# elif gcdOFFSET == 4
++# define gcdNUMSIZE gcmALIGNSIZE(4, gcmSIZEOF(gctUINT64))
++# else
++# error "Unexpected offset value."
++# endif
++# undef gcdOFFSET
++# define gcdOFFSET 8
++#if !defined(gcdPREFIX_LEADER)
++# define gcdPREFIX_LEADER gcmSIZEOF(gctUINT64)
++# define gcdNUMFORMAT "%8llu"
++# else
++# define gcdNUMFORMAT ", %8llu"
++# endif
++# else
++# define gcdNUMSIZE 0
++# define gcdNUMFORMAT
++# endif
++
++#if gcdSHOW_PROCESS_ID
++#if gcmISALIGNED(gcdOFFSET, 4)
++# define gcdPIDSIZE gcmSIZEOF(gctUINT32)
++# else
++# error "Unexpected offset value."
++# endif
++# undef gcdOFFSET
++# define gcdOFFSET 4
++#if !defined(gcdPREFIX_LEADER)
++# define gcdPREFIX_LEADER gcmSIZEOF(gctUINT32)
++# define gcdPIDFORMAT "pid=%5d"
++# else
++# define gcdPIDFORMAT ", pid=%5d"
++# endif
++# else
++# define gcdPIDSIZE 0
++# define gcdPIDFORMAT
++# endif
++
++#if gcdSHOW_THREAD_ID
++#if gcmISALIGNED(gcdOFFSET, 4)
++# define gcdTIDSIZE gcmSIZEOF(gctUINT32)
++# else
++# error "Unexpected offset value."
++# endif
++# undef gcdOFFSET
++# define gcdOFFSET 4
++#if !defined(gcdPREFIX_LEADER)
++# define gcdPREFIX_LEADER gcmSIZEOF(gctUINT32)
++# define gcdTIDFORMAT "tid=%5d"
++# else
++# define gcdTIDFORMAT ", tid=%5d"
++# endif
++# else
++# define gcdTIDSIZE 0
++# define gcdTIDFORMAT
++# endif
++
++# define gcdPREFIX_SIZE \
++ ( \
++ gcdTIMESIZE \
++ + gcdNUMSIZE \
++ + gcdPIDSIZE \
++ + gcdTIDSIZE \
++ )
++
++ static const char * _prefixFormat =
++ "["
++ gcdTIMEFORMAT
++ gcdNUMFORMAT
++ gcdPIDFORMAT
++ gcdTIDFORMAT
++ "] ";
++
++#else
++
++# define gcdPREFIX_LEADER gcmSIZEOF(gctUINT32)
++# define gcdPREFIX_SIZE 0
++
++#endif
++
++/* Assumed largest variable argument leader size. */
++#define gcdVARARG_LEADER gcmSIZEOF(gctUINT64)
++
++/* Alignnments. */
++#if gcdALIGNBYSIZE
++# define gcdPREFIX_ALIGNMENT gcdPREFIX_LEADER
++# define gcdVARARG_ALIGNMENT gcdVARARG_LEADER
++#else
++# define gcdPREFIX_ALIGNMENT 0
++# define gcdVARARG_ALIGNMENT 0
++#endif
++
++#if gcdBUFFERED_OUTPUT
++# define gcdOUTPUTPREFIX _AppendPrefix
++# define gcdOUTPUTSTRING _AppendString
++# define gcdOUTPUTCOPY _AppendCopy
++# define gcdOUTPUTBUFFER _AppendBuffer
++#else
++# define gcdOUTPUTPREFIX _PrintPrefix
++# define gcdOUTPUTSTRING _PrintString
++# define gcdOUTPUTCOPY _PrintString
++# define gcdOUTPUTBUFFER _PrintBuffer
++#endif
++
++/******************************************************************************\
++****************************** Private Structures ******************************
++\******************************************************************************/
++
++typedef enum _gceBUFITEM
++{
++ gceBUFITEM_NONE,
++ gcvBUFITEM_PREFIX,
++ gcvBUFITEM_STRING,
++ gcvBUFITEM_COPY,
++ gcvBUFITEM_BUFFER
++}
++gceBUFITEM;
++
++/* Common item head/buffer terminator. */
++typedef struct _gcsBUFITEM_HEAD * gcsBUFITEM_HEAD_PTR;
++typedef struct _gcsBUFITEM_HEAD
++{
++ gceBUFITEM type;
++}
++gcsBUFITEM_HEAD;
++
++/* String prefix (for ex. [ 1,tid=0x019A]) */
++typedef struct _gcsBUFITEM_PREFIX * gcsBUFITEM_PREFIX_PTR;
++typedef struct _gcsBUFITEM_PREFIX
++{
++ gceBUFITEM type;
++#if gcdHAVEPREFIX
++ gctPOINTER prefixData;
++#endif
++}
++gcsBUFITEM_PREFIX;
++
++/* Buffered string. */
++typedef struct _gcsBUFITEM_STRING * gcsBUFITEM_STRING_PTR;
++typedef struct _gcsBUFITEM_STRING
++{
++ gceBUFITEM type;
++ gctINT indent;
++ gctCONST_STRING message;
++ gctPOINTER messageData;
++ gctUINT messageDataSize;
++}
++gcsBUFITEM_STRING;
++
++/* Buffered string (copy of the string is included with the record). */
++typedef struct _gcsBUFITEM_COPY * gcsBUFITEM_COPY_PTR;
++typedef struct _gcsBUFITEM_COPY
++{
++ gceBUFITEM type;
++ gctINT indent;
++ gctPOINTER messageData;
++ gctUINT messageDataSize;
++}
++gcsBUFITEM_COPY;
++
++/* Memory buffer. */
++typedef struct _gcsBUFITEM_BUFFER * gcsBUFITEM_BUFFER_PTR;
++typedef struct _gcsBUFITEM_BUFFER
++{
++ gceBUFITEM type;
++ gctINT indent;
++ gceDUMP_BUFFER bufferType;
++
++#if gcdDMA_BUFFER_COUNT && (gcdTHREAD_BUFFERS == 1)
++ gctUINT32 dmaAddress;
++#endif
++
++ gctUINT dataSize;
++ gctUINT32 address;
++#if gcdHAVEPREFIX
++ gctPOINTER prefixData;
++#endif
++}
++gcsBUFITEM_BUFFER;
++
++typedef struct _gcsBUFFERED_OUTPUT * gcsBUFFERED_OUTPUT_PTR;
++typedef struct _gcsBUFFERED_OUTPUT
++{
++#if gcdTHREAD_BUFFERS > 1
++ gctUINT32 threadID;
++#endif
++
++#if gcdSHOW_LINE_NUMBER
++ gctUINT64 lineNumber;
++#endif
++
++ gctINT indent;
++
++#if gcdBUFFERED_OUTPUT
++ gctINT start;
++ gctINT index;
++ gctINT count;
++ gctUINT8 buffer[gcdBUFFERED_SIZE];
++#endif
++
++ gcsBUFFERED_OUTPUT_PTR prev;
++ gcsBUFFERED_OUTPUT_PTR next;
++}
++gcsBUFFERED_OUTPUT;
++
++typedef gctUINT (* gcfPRINTSTRING) (
++ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer,
++ IN gcsBUFITEM_HEAD_PTR Item
++ );
++
++typedef gctINT (* gcfGETITEMSIZE) (
++ IN gcsBUFITEM_HEAD_PTR Item
++ );
++
++/******************************************************************************\
++******************************* Private Variables ******************************
++\******************************************************************************/
++
++static gcsBUFFERED_OUTPUT _outputBuffer[gcdTHREAD_BUFFERS];
++static gcsBUFFERED_OUTPUT_PTR _outputBufferHead = gcvNULL;
++static gcsBUFFERED_OUTPUT_PTR _outputBufferTail = gcvNULL;
++
++/******************************************************************************\
++****************************** Item Size Functions *****************************
++\******************************************************************************/
++
++#if gcdBUFFERED_OUTPUT
++static gctINT
++_GetTerminatorItemSize(
++ IN gcsBUFITEM_HEAD_PTR Item
++ )
++{
++ return gcmSIZEOF(gcsBUFITEM_HEAD);
++}
++
++static gctINT
++_GetPrefixItemSize(
++ IN gcsBUFITEM_HEAD_PTR Item
++ )
++{
++#if gcdHAVEPREFIX
++ gcsBUFITEM_PREFIX_PTR item = (gcsBUFITEM_PREFIX_PTR) Item;
++ gctUINT vlen = ((gctUINT8_PTR) item->prefixData) - ((gctUINT8_PTR) item);
++ return vlen + gcdPREFIX_SIZE;
++#else
++ return gcmSIZEOF(gcsBUFITEM_PREFIX);
++#endif
++}
++
++static gctINT
++_GetStringItemSize(
++ IN gcsBUFITEM_HEAD_PTR Item
++ )
++{
++ gcsBUFITEM_STRING_PTR item = (gcsBUFITEM_STRING_PTR) Item;
++ gctUINT vlen = ((gctUINT8_PTR) item->messageData) - ((gctUINT8_PTR) item);
++ return vlen + item->messageDataSize;
++}
++
++static gctINT
++_GetCopyItemSize(
++ IN gcsBUFITEM_HEAD_PTR Item
++ )
++{
++ gcsBUFITEM_COPY_PTR item = (gcsBUFITEM_COPY_PTR) Item;
++ gctUINT vlen = ((gctUINT8_PTR) item->messageData) - ((gctUINT8_PTR) item);
++ return vlen + item->messageDataSize;
++}
++
++static gctINT
++_GetBufferItemSize(
++ IN gcsBUFITEM_HEAD_PTR Item
++ )
++{
++#if gcdHAVEPREFIX
++ gcsBUFITEM_BUFFER_PTR item = (gcsBUFITEM_BUFFER_PTR) Item;
++ gctUINT vlen = ((gctUINT8_PTR) item->prefixData) - ((gctUINT8_PTR) item);
++ return vlen + gcdPREFIX_SIZE + item->dataSize;
++#else
++ gcsBUFITEM_BUFFER_PTR item = (gcsBUFITEM_BUFFER_PTR) Item;
++ return gcmSIZEOF(gcsBUFITEM_BUFFER) + item->dataSize;
++#endif
++}
++
++static gcfGETITEMSIZE _itemSize[] =
++{
++ _GetTerminatorItemSize,
++ _GetPrefixItemSize,
++ _GetStringItemSize,
++ _GetCopyItemSize,
++ _GetBufferItemSize
++};
++#endif
++
++/******************************************************************************\
++******************************* Printing Functions *****************************
++\******************************************************************************/
++
++#if gcdDEBUG || gcdBUFFERED_OUTPUT
++static void
++_DirectPrint(
++ gctCONST_STRING Message,
++ ...
++ )
++{
++ gctINT len;
++ char buffer[768];
++ gctARGUMENTS arguments;
++
++ gcmkARGUMENTS_START(arguments, Message);
++ len = gcmkVSPRINTF(buffer, gcmSIZEOF(buffer), Message, arguments);
++ gcmkARGUMENTS_END(arguments);
++
++ buffer[len] = '\0';
++ gcmkOUTPUT_STRING(buffer);
++}
++#endif
++
++static int
++_AppendIndent(
++ IN gctINT Indent,
++ IN char * Buffer,
++ IN int BufferSize
++ )
++{
++ gctINT i;
++
++ gctINT len = 0;
++ gctINT indent = Indent % 40;
++
++ for (i = 0; i < indent; i += 1)
++ {
++ Buffer[len++] = ' ';
++ }
++
++ if (indent != Indent)
++ {
++ len += gcmkSPRINTF(
++ Buffer + len, BufferSize - len, " <%d> ", Indent
++ );
++
++ Buffer[len] = '\0';
++ }
++
++ return len;
++}
++
++#if gcdHAVEPREFIX
++static void
++_PrintPrefix(
++ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer,
++ IN gctPOINTER Data
++ )
++{
++ char buffer[768];
++ gctINT len;
++
++ /* Format the string. */
++ len = gcmkVSPRINTF(buffer, gcmSIZEOF(buffer), _prefixFormat, Data);
++ buffer[len] = '\0';
++
++ /* Print the string. */
++ gcmkOUTPUT_STRING(buffer);
++}
++#endif
++
++static void
++_PrintString(
++ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer,
++ IN gctINT Indent,
++ IN gctCONST_STRING Message,
++ IN gctUINT ArgumentSize,
++ IN gctPOINTER Data
++ )
++{
++ char buffer[768];
++ gctINT len;
++
++ /* Append the indent string. */
++ len = _AppendIndent(Indent, buffer, gcmSIZEOF(buffer));
++
++ /* Format the string. */
++ len += gcmkVSPRINTF(buffer + len, gcmSIZEOF(buffer) - len, Message, Data);
++ buffer[len] = '\0';
++
++ /* Add end-of-line if missing. */
++ if (buffer[len - 1] != '\n')
++ {
++ buffer[len++] = '\n';
++ buffer[len] = '\0';
++ }
++
++ /* Print the string. */
++ gcmkOUTPUT_STRING(buffer);
++}
++
++static void
++_PrintBuffer(
++ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer,
++ IN gctINT Indent,
++ IN gctPOINTER PrefixData,
++ IN gctPOINTER Data,
++ IN gctUINT Address,
++ IN gctUINT DataSize,
++ IN gceDUMP_BUFFER Type,
++ IN gctUINT32 DmaAddress
++ )
++{
++ static gctCONST_STRING _titleString[] =
++ {
++ "CONTEXT BUFFER",
++ "USER COMMAND BUFFER",
++ "KERNEL COMMAND BUFFER",
++ "LINK BUFFER",
++ "WAIT LINK BUFFER",
++ ""
++ };
++
++ static const gctINT COLUMN_COUNT = 8;
++
++ gctUINT i, count, column, address;
++ gctUINT32_PTR data;
++ gctCHAR buffer[768];
++ gctUINT indent, len;
++ gctBOOL command;
++
++ /* Append space for the prefix. */
++#if gcdHAVEPREFIX
++ indent = gcmkVSPRINTF(buffer, gcmSIZEOF(buffer), _prefixFormat, PrefixData);
++ buffer[indent] = '\0';
++#else
++ indent = 0;
++#endif
++
++ /* Append the indent string. */
++ indent += _AppendIndent(
++ Indent, buffer + indent, gcmSIZEOF(buffer) - indent
++ );
++
++ switch (Type)
++ {
++ case gceDUMP_BUFFER_CONTEXT:
++ case gceDUMP_BUFFER_USER:
++ case gceDUMP_BUFFER_KERNEL:
++ case gceDUMP_BUFFER_LINK:
++ case gceDUMP_BUFFER_WAITLINK:
++ /* Form and print the title string. */
++ gcmkSPRINTF2(
++ buffer + indent, gcmSIZEOF(buffer) - indent,
++ "%s%s\n", _titleString[Type],
++ ((DmaAddress >= Address) && (DmaAddress < Address + DataSize))
++ ? " (CURRENT)" : ""
++ );
++
++ gcmkOUTPUT_STRING(buffer);
++
++ /* Terminate the string. */
++ buffer[indent] = '\0';
++
++ /* This is a command buffer. */
++ command = gcvTRUE;
++ break;
++
++ case gceDUMP_BUFFER_FROM_USER:
++ /* This is not a command buffer. */
++ command = gcvFALSE;
++
++ /* No title. */
++ break;
++
++ default:
++ gcmDBGASSERT(gcvFALSE, "%s", "invalid buffer type");
++
++ /* This is not a command buffer. */
++ command = gcvFALSE;
++ }
++
++ /* Overwrite the prefix with spaces. */
++ for (i = 0; i < indent; i += 1)
++ {
++ buffer[i] = ' ';
++ }
++
++ /* Form and print the opening string. */
++ if (command)
++ {
++ gcmkSPRINTF2(
++ buffer + indent, gcmSIZEOF(buffer) - indent,
++ "@[kernel.command %08X %08X\n", Address, DataSize
++ );
++
++ gcmkOUTPUT_STRING(buffer);
++
++ /* Terminate the string. */
++ buffer[indent] = '\0';
++ }
++
++ /* Get initial address. */
++ address = Address;
++
++ /* Cast the data pointer. */
++ data = (gctUINT32_PTR) Data;
++
++ /* Compute the number of double words. */
++ count = DataSize / gcmSIZEOF(gctUINT32);
++
++ /* Print the buffer. */
++ for (i = 0, len = indent, column = 0; i < count; i += 1)
++ {
++ /* Append the address. */
++ if (column == 0)
++ {
++ len += gcmkSPRINTF(
++ buffer + len, gcmSIZEOF(buffer) - len, "0x%08X:", address
++ );
++ }
++
++ /* Append the data value. */
++ len += gcmkSPRINTF2(
++ buffer + len, gcmSIZEOF(buffer) - len, "%c%08X",
++ (address == DmaAddress)? '>' : ' ', data[i]
++ );
++
++ buffer[len] = '\0';
++
++ /* Update the address. */
++ address += gcmSIZEOF(gctUINT32);
++
++ /* Advance column count. */
++ column += 1;
++
++ /* End of line? */
++ if ((column % COLUMN_COUNT) == 0)
++ {
++ /* Append EOL. */
++ gcmkSTRCAT(buffer + len, gcmSIZEOF(buffer) - len, "\n");
++
++ /* Print the string. */
++ gcmkOUTPUT_STRING(buffer);
++
++ /* Reset. */
++ len = indent;
++ column = 0;
++ }
++ }
++
++ /* Print the last partial string. */
++ if (column != 0)
++ {
++ /* Append EOL. */
++ gcmkSTRCAT(buffer + len, gcmSIZEOF(buffer) - len, "\n");
++
++ /* Print the string. */
++ gcmkOUTPUT_STRING(buffer);
++ }
++
++ /* Form and print the opening string. */
++ if (command)
++ {
++ buffer[indent] = '\0';
++ gcmkSTRCAT(buffer, gcmSIZEOF(buffer), "] -- command\n");
++ gcmkOUTPUT_STRING(buffer);
++ }
++}
++
++#if gcdBUFFERED_OUTPUT
++static gctUINT
++_PrintNone(
++ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer,
++ IN gcsBUFITEM_HEAD_PTR Item
++ )
++{
++ /* Return the size of the node. */
++ return gcmSIZEOF(gcsBUFITEM_HEAD);
++}
++
++static gctUINT
++_PrintPrefixWrapper(
++ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer,
++ IN gcsBUFITEM_HEAD_PTR Item
++ )
++{
++#if gcdHAVEPREFIX
++ gcsBUFITEM_PREFIX_PTR item;
++ gctUINT vlen;
++
++ /* Get access to the data. */
++ item = (gcsBUFITEM_PREFIX_PTR) Item;
++
++ /* Print the message. */
++ _PrintPrefix(OutputBuffer, item->prefixData);
++
++ /* Compute the size of the variable portion of the structure. */
++ vlen = ((gctUINT8_PTR) item->prefixData) - ((gctUINT8_PTR) item);
++
++ /* Return the size of the node. */
++ return vlen + gcdPREFIX_SIZE;
++#else
++ return gcmSIZEOF(gcsBUFITEM_PREFIX);
++#endif
++}
++
++static gctUINT
++_PrintStringWrapper(
++ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer,
++ IN gcsBUFITEM_HEAD_PTR Item
++ )
++{
++ gcsBUFITEM_STRING_PTR item;
++ gctUINT vlen;
++
++ /* Get access to the data. */
++ item = (gcsBUFITEM_STRING_PTR) Item;
++
++ /* Print the message. */
++ _PrintString(
++ OutputBuffer,
++ item->indent, item->message, item->messageDataSize, item->messageData
++ );
++
++ /* Compute the size of the variable portion of the structure. */
++ vlen = ((gctUINT8_PTR) item->messageData) - ((gctUINT8_PTR) item);
++
++ /* Return the size of the node. */
++ return vlen + item->messageDataSize;
++}
++
++static gctUINT
++_PrintCopyWrapper(
++ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer,
++ IN gcsBUFITEM_HEAD_PTR Item
++ )
++{
++ gcsBUFITEM_COPY_PTR item;
++ gctCONST_STRING message;
++ gctUINT vlen;
++
++ /* Get access to the data. */
++ item = (gcsBUFITEM_COPY_PTR) Item;
++
++ /* Determine the string pointer. */
++ message = (gctCONST_STRING) (item + 1);
++
++ /* Print the message. */
++ _PrintString(
++ OutputBuffer,
++ item->indent, message, item->messageDataSize, item->messageData
++ );
++
++ /* Compute the size of the variable portion of the structure. */
++ vlen = ((gctUINT8_PTR) item->messageData) - ((gctUINT8_PTR) item);
++
++ /* Return the size of the node. */
++ return vlen + item->messageDataSize;
++}
++
++static gctUINT
++_PrintBufferWrapper(
++ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer,
++ IN gcsBUFITEM_HEAD_PTR Item
++ )
++{
++#if gcdHAVEPREFIX
++ gctUINT32 dmaAddress;
++ gcsBUFITEM_BUFFER_PTR item;
++ gctPOINTER data;
++ gctUINT vlen;
++
++ /* Get access to the data. */
++ item = (gcsBUFITEM_BUFFER_PTR) Item;
++
++#if gcdDMA_BUFFER_COUNT && (gcdTHREAD_BUFFERS == 1)
++ dmaAddress = item->dmaAddress;
++#else
++ dmaAddress = 0xFFFFFFFF;
++#endif
++
++ if (dmaAddress != 0)
++ {
++ /* Compute the data address. */
++ data = ((gctUINT8_PTR) item->prefixData) + gcdPREFIX_SIZE;
++
++ /* Print buffer. */
++ _PrintBuffer(
++ OutputBuffer,
++ item->indent, item->prefixData,
++ data, item->address, item->dataSize,
++ item->bufferType, dmaAddress
++ );
++ }
++
++ /* Compute the size of the variable portion of the structure. */
++ vlen = ((gctUINT8_PTR) item->prefixData) - ((gctUINT8_PTR) item);
++
++ /* Return the size of the node. */
++ return vlen + gcdPREFIX_SIZE + item->dataSize;
++#else
++ gctUINT32 dmaAddress;
++ gcsBUFITEM_BUFFER_PTR item;
++
++ /* Get access to the data. */
++ item = (gcsBUFITEM_BUFFER_PTR) Item;
++
++#if gcdDMA_BUFFER_COUNT && (gcdTHREAD_BUFFERS == 1)
++ dmaAddress = item->dmaAddress;
++#else
++ dmaAddress = 0xFFFFFFFF;
++#endif
++
++ if (dmaAddress != 0)
++ {
++ /* Print buffer. */
++ _PrintBuffer(
++ OutputBuffer,
++ item->indent, gcvNULL,
++ item + 1, item->address, item->dataSize,
++ item->bufferType, dmaAddress
++ );
++ }
++
++ /* Return the size of the node. */
++ return gcmSIZEOF(gcsBUFITEM_BUFFER) + item->dataSize;
++#endif
++}
++
++static gcfPRINTSTRING _printArray[] =
++{
++ _PrintNone,
++ _PrintPrefixWrapper,
++ _PrintStringWrapper,
++ _PrintCopyWrapper,
++ _PrintBufferWrapper
++};
++#endif
++
++/******************************************************************************\
++******************************* Private Functions ******************************
++\******************************************************************************/
++
++#if gcdBUFFERED_OUTPUT
++
++#if gcdDMA_BUFFER_COUNT && (gcdTHREAD_BUFFERS == 1)
++static gcsBUFITEM_BUFFER_PTR
++_FindCurrentDMABuffer(
++ gctUINT32 DmaAddress
++ )
++{
++ gctINT i, skip;
++ gcsBUFITEM_HEAD_PTR item;
++ gcsBUFITEM_BUFFER_PTR dmaCurrent;
++
++ /* Reset the current buffer. */
++ dmaCurrent = gcvNULL;
++
++ /* Get the first stored item. */
++ item = (gcsBUFITEM_HEAD_PTR) &_outputBufferHead->buffer[_outputBufferHead->start];
++
++ /* Run through all items. */
++ for (i = 0; i < _outputBufferHead->count; i += 1)
++ {
++ /* Buffer item? */
++ if (item->type == gcvBUFITEM_BUFFER)
++ {
++ gcsBUFITEM_BUFFER_PTR buffer = (gcsBUFITEM_BUFFER_PTR) item;
++
++ if ((DmaAddress >= buffer->address) &&
++ (DmaAddress < buffer->address + buffer->dataSize))
++ {
++ dmaCurrent = buffer;
++ }
++ }
++
++ /* Get the item size and skip it. */
++ skip = (* _itemSize[item->type]) (item);
++ item = (gcsBUFITEM_HEAD_PTR) ((gctUINT8_PTR) item + skip);
++
++ /* End of the buffer? Wrap around. */
++ if (item->type == gceBUFITEM_NONE)
++ {
++ item = (gcsBUFITEM_HEAD_PTR) _outputBufferHead->buffer;
++ }
++ }
++
++ /* Return result. */
++ return dmaCurrent;
++}
++
++static void
++_EnableAllDMABuffers(
++ void
++ )
++{
++ gctINT i, skip;
++ gcsBUFITEM_HEAD_PTR item;
++
++ /* Get the first stored item. */
++ item = (gcsBUFITEM_HEAD_PTR) &_outputBufferHead->buffer[_outputBufferHead->start];
++
++ /* Run through all items. */
++ for (i = 0; i < _outputBufferHead->count; i += 1)
++ {
++ /* Buffer item? */
++ if (item->type == gcvBUFITEM_BUFFER)
++ {
++ gcsBUFITEM_BUFFER_PTR buffer = (gcsBUFITEM_BUFFER_PTR) item;
++
++ /* Enable the buffer. */
++ buffer->dmaAddress = ~0U;
++ }
++
++ /* Get the item size and skip it. */
++ skip = (* _itemSize[item->type]) (item);
++ item = (gcsBUFITEM_HEAD_PTR) ((gctUINT8_PTR) item + skip);
++
++ /* End of the buffer? Wrap around. */
++ if (item->type == gceBUFITEM_NONE)
++ {
++ item = (gcsBUFITEM_HEAD_PTR) _outputBufferHead->buffer;
++ }
++ }
++}
++
++static void
++_EnableDMABuffers(
++ gctUINT32 DmaAddress,
++ gcsBUFITEM_BUFFER_PTR CurrentDMABuffer
++ )
++{
++ gctINT i, skip, index;
++ gcsBUFITEM_HEAD_PTR item;
++ gcsBUFITEM_BUFFER_PTR buffers[gcdDMA_BUFFER_COUNT];
++
++ /* Reset buffer pointers. */
++ gckOS_ZeroMemory(buffers, gcmSIZEOF(buffers));
++
++ /* Set the current buffer index. */
++ index = -1;
++
++ /* Get the first stored item. */
++ item = (gcsBUFITEM_HEAD_PTR) &_outputBufferHead->buffer[_outputBufferHead->start];
++
++ /* Run through all items until the current DMA buffer is found. */
++ for (i = 0; i < _outputBufferHead->count; i += 1)
++ {
++ /* Buffer item? */
++ if (item->type == gcvBUFITEM_BUFFER)
++ {
++ /* Advance the index. */
++ index = (index + 1) % gcdDMA_BUFFER_COUNT;
++
++ /* Add to the buffer array. */
++ buffers[index] = (gcsBUFITEM_BUFFER_PTR) item;
++
++ /* Stop if this is the current DMA buffer. */
++ if ((gcsBUFITEM_BUFFER_PTR) item == CurrentDMABuffer)
++ {
++ break;
++ }
++ }
++
++ /* Get the item size and skip it. */
++ skip = (* _itemSize[item->type]) (item);
++ item = (gcsBUFITEM_HEAD_PTR) ((gctUINT8_PTR) item + skip);
++
++ /* End of the buffer? Wrap around. */
++ if (item->type == gceBUFITEM_NONE)
++ {
++ item = (gcsBUFITEM_HEAD_PTR) _outputBufferHead->buffer;
++ }
++ }
++
++ /* Enable the found buffers. */
++ gcmDBGASSERT(index != -1, "%d", index);
++
++ for (i = 0; i < gcdDMA_BUFFER_COUNT; i += 1)
++ {
++ if (buffers[index] == gcvNULL)
++ {
++ break;
++ }
++
++ buffers[index]->dmaAddress = DmaAddress;
++
++ index -= 1;
++
++ if (index == -1)
++ {
++ index = gcdDMA_BUFFER_COUNT - 1;
++ }
++ }
++}
++#endif
++
++static void
++_Flush(
++ gctUINT32 DmaAddress
++ )
++{
++ gctINT i, skip;
++ gcsBUFITEM_HEAD_PTR item;
++
++ gcsBUFFERED_OUTPUT_PTR outputBuffer = _outputBufferHead;
++
++#if gcdDMA_BUFFER_COUNT && (gcdTHREAD_BUFFERS == 1)
++ if ((outputBuffer != gcvNULL) && (outputBuffer->count != 0))
++ {
++ /* Find the current DMA buffer. */
++ gcsBUFITEM_BUFFER_PTR dmaCurrent = _FindCurrentDMABuffer(DmaAddress);
++
++ /* Was the current buffer found? */
++ if (dmaCurrent == gcvNULL)
++ {
++ /* No, print all buffers. */
++ _EnableAllDMABuffers();
++ }
++ else
++ {
++ /* Yes, enable only specified number of buffers. */
++ _EnableDMABuffers(DmaAddress, dmaCurrent);
++ }
++ }
++#endif
++
++ while (outputBuffer != gcvNULL)
++ {
++ if (outputBuffer->count != 0)
++ {
++ _DirectPrint("********************************************************************************\n");
++ _DirectPrint("FLUSHING DEBUG OUTPUT BUFFER (%d elements).\n", outputBuffer->count);
++ _DirectPrint("********************************************************************************\n");
++
++ item = (gcsBUFITEM_HEAD_PTR) &outputBuffer->buffer[outputBuffer->start];
++
++ for (i = 0; i < outputBuffer->count; i += 1)
++ {
++ skip = (* _printArray[item->type]) (outputBuffer, item);
++
++ item = (gcsBUFITEM_HEAD_PTR) ((gctUINT8_PTR) item + skip);
++
++ if (item->type == gceBUFITEM_NONE)
++ {
++ item = (gcsBUFITEM_HEAD_PTR) outputBuffer->buffer;
++ }
++ }
++
++ outputBuffer->start = 0;
++ outputBuffer->index = 0;
++ outputBuffer->count = 0;
++ }
++
++ outputBuffer = outputBuffer->next;
++ }
++}
++
++static gcsBUFITEM_HEAD_PTR
++_AllocateItem(
++ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer,
++ IN gctINT Size
++ )
++{
++ gctINT skip;
++ gcsBUFITEM_HEAD_PTR item, next;
++
++#if gcdENABLE_OVERFLOW
++ if (
++ (OutputBuffer->index + Size >= gcdBUFFERED_SIZE - gcmSIZEOF(gcsBUFITEM_HEAD))
++ ||
++ (
++ (OutputBuffer->index < OutputBuffer->start) &&
++ (OutputBuffer->index + Size >= OutputBuffer->start)
++ )
++ )
++ {
++ if (OutputBuffer->index + Size >= gcdBUFFERED_SIZE - gcmSIZEOF(gcsBUFITEM_HEAD))
++ {
++ if (OutputBuffer->index < OutputBuffer->start)
++ {
++ item = (gcsBUFITEM_HEAD_PTR) &OutputBuffer->buffer[OutputBuffer->start];
++
++ while (item->type != gceBUFITEM_NONE)
++ {
++ skip = (* _itemSize[item->type]) (item);
++
++ OutputBuffer->start += skip;
++ OutputBuffer->count -= 1;
++
++ item->type = gceBUFITEM_NONE;
++ item = (gcsBUFITEM_HEAD_PTR) ((gctUINT8_PTR) item + skip);
++ }
++
++ OutputBuffer->start = 0;
++ }
++
++ OutputBuffer->index = 0;
++ }
++
++ item = (gcsBUFITEM_HEAD_PTR) &OutputBuffer->buffer[OutputBuffer->start];
++
++ while (OutputBuffer->start - OutputBuffer->index <= Size)
++ {
++ skip = (* _itemSize[item->type]) (item);
++
++ OutputBuffer->start += skip;
++ OutputBuffer->count -= 1;
++
++ item->type = gceBUFITEM_NONE;
++ item = (gcsBUFITEM_HEAD_PTR) ((gctUINT8_PTR) item + skip);
++
++ if (item->type == gceBUFITEM_NONE)
++ {
++ OutputBuffer->start = 0;
++ break;
++ }
++ }
++ }
++#else
++ if (OutputBuffer->index + Size > gcdBUFFERED_SIZE - gcmSIZEOF(gcsBUFITEM_HEAD))
++ {
++ _DirectPrint("\nMessage buffer full; forcing message flush.\n\n");
++ _Flush(~0U);
++ }
++#endif
++
++ item = (gcsBUFITEM_HEAD_PTR) &OutputBuffer->buffer[OutputBuffer->index];
++
++ OutputBuffer->index += Size;
++ OutputBuffer->count += 1;
++
++ next = (gcsBUFITEM_HEAD_PTR) ((gctUINT8_PTR) item + Size);
++ next->type = gceBUFITEM_NONE;
++
++ return item;
++}
++
++#if gcdALIGNBYSIZE
++static void
++_FreeExtraSpace(
++ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer,
++ IN gctPOINTER Item,
++ IN gctINT ItemSize,
++ IN gctINT FreeSize
++ )
++{
++ gcsBUFITEM_HEAD_PTR next;
++
++ OutputBuffer->index -= FreeSize;
++
++ next = (gcsBUFITEM_HEAD_PTR) ((gctUINT8_PTR) Item + ItemSize);
++ next->type = gceBUFITEM_NONE;
++}
++#endif
++
++#if gcdHAVEPREFIX
++static void
++_AppendPrefix(
++ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer,
++ IN gctPOINTER Data
++ )
++{
++ gctUINT8_PTR prefixData;
++ gcsBUFITEM_PREFIX_PTR item;
++ gctINT allocSize;
++
++#if gcdALIGNBYSIZE
++ gctUINT alignment;
++ gctINT size, freeSize;
++#endif
++
++ gcmDBGASSERT(Data != gcvNULL, "%p", Data);
++
++ /* Determine the maximum item size. */
++ allocSize
++ = gcmSIZEOF(gcsBUFITEM_PREFIX)
++ + gcdPREFIX_SIZE
++ + gcdPREFIX_ALIGNMENT;
++
++ /* Allocate prefix item. */
++ item = (gcsBUFITEM_PREFIX_PTR) _AllocateItem(OutputBuffer, allocSize);
++
++ /* Compute the initial prefix data pointer. */
++ prefixData = (gctUINT8_PTR) (item + 1);
++
++ /* Align the data pointer as necessary. */
++#if gcdALIGNBYSIZE
++ alignment = gcmPTRALIGNMENT(prefixData, gcdPREFIX_ALIGNMENT);
++ prefixData += alignment;
++#endif
++
++ /* Set item data. */
++ item->type = gcvBUFITEM_PREFIX;
++ item->prefixData = prefixData;
++
++ /* Copy argument value. */
++ memcpy(prefixData, Data, gcdPREFIX_SIZE);
++
++#if gcdALIGNBYSIZE
++ /* Compute the actual node size. */
++ size = gcmSIZEOF(gcsBUFITEM_PREFIX) + gcdPREFIX_SIZE + alignment;
++
++ /* Free extra memory if any. */
++ freeSize = allocSize - size;
++ if (freeSize != 0)
++ {
++ _FreeExtraSpace(OutputBuffer, item, size, freeSize);
++ }
++#endif
++}
++#endif
++
++static void
++_AppendString(
++ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer,
++ IN gctINT Indent,
++ IN gctCONST_STRING Message,
++ IN gctUINT ArgumentSize,
++ IN gctPOINTER Data
++ )
++{
++ gctUINT8_PTR messageData;
++ gcsBUFITEM_STRING_PTR item;
++ gctINT allocSize;
++
++#if gcdALIGNBYSIZE
++ gctUINT alignment;
++ gctINT size, freeSize;
++#endif
++
++ /* Determine the maximum item size. */
++ allocSize
++ = gcmSIZEOF(gcsBUFITEM_STRING)
++ + ArgumentSize
++ + gcdVARARG_ALIGNMENT;
++
++ /* Allocate prefix item. */
++ item = (gcsBUFITEM_STRING_PTR) _AllocateItem(OutputBuffer, allocSize);
++
++ /* Compute the initial message data pointer. */
++ messageData = (gctUINT8_PTR) (item + 1);
++
++ /* Align the data pointer as necessary. */
++#if gcdALIGNBYSIZE
++ alignment = gcmPTRALIGNMENT(messageData, gcdVARARG_ALIGNMENT);
++ messageData += alignment;
++#endif
++
++ /* Set item data. */
++ item->type = gcvBUFITEM_STRING;
++ item->indent = Indent;
++ item->message = Message;
++ item->messageData = messageData;
++ item->messageDataSize = ArgumentSize;
++
++ /* Copy argument value. */
++ if (ArgumentSize != 0)
++ {
++ memcpy(messageData, Data, ArgumentSize);
++ }
++
++#if gcdALIGNBYSIZE
++ /* Compute the actual node size. */
++ size = gcmSIZEOF(gcsBUFITEM_STRING) + ArgumentSize + alignment;
++
++ /* Free extra memory if any. */
++ freeSize = allocSize - size;
++ if (freeSize != 0)
++ {
++ _FreeExtraSpace(OutputBuffer, item, size, freeSize);
++ }
++#endif
++}
++
++static void
++_AppendCopy(
++ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer,
++ IN gctINT Indent,
++ IN gctCONST_STRING Message,
++ IN gctUINT ArgumentSize,
++ IN gctPOINTER Data
++ )
++{
++ gctUINT8_PTR messageData;
++ gcsBUFITEM_COPY_PTR item;
++ gctINT allocSize;
++ gctINT messageLength;
++ gctCONST_STRING message;
++
++#if gcdALIGNBYSIZE
++ gctUINT alignment;
++ gctINT size, freeSize;
++#endif
++
++ /* Get the length of the string. */
++ messageLength = strlen(Message) + 1;
++
++ /* Determine the maximum item size. */
++ allocSize
++ = gcmSIZEOF(gcsBUFITEM_COPY)
++ + messageLength
++ + ArgumentSize
++ + gcdVARARG_ALIGNMENT;
++
++ /* Allocate prefix item. */
++ item = (gcsBUFITEM_COPY_PTR) _AllocateItem(OutputBuffer, allocSize);
++
++ /* Determine the message placement. */
++ message = (gctCONST_STRING) (item + 1);
++
++ /* Compute the initial message data pointer. */
++ messageData = (gctUINT8_PTR) message + messageLength;
++
++ /* Align the data pointer as necessary. */
++#if gcdALIGNBYSIZE
++ if (ArgumentSize == 0)
++ {
++ alignment = 0;
++ }
++ else
++ {
++ alignment = gcmPTRALIGNMENT(messageData, gcdVARARG_ALIGNMENT);
++ messageData += alignment;
++ }
++#endif
++
++ /* Set item data. */
++ item->type = gcvBUFITEM_COPY;
++ item->indent = Indent;
++ item->messageData = messageData;
++ item->messageDataSize = ArgumentSize;
++
++ /* Copy the message. */
++ memcpy((gctPOINTER) message, Message, messageLength);
++
++ /* Copy argument value. */
++ if (ArgumentSize != 0)
++ {
++ memcpy(messageData, Data, ArgumentSize);
++ }
++
++#if gcdALIGNBYSIZE
++ /* Compute the actual node size. */
++ size
++ = gcmSIZEOF(gcsBUFITEM_COPY)
++ + messageLength
++ + ArgumentSize
++ + alignment;
++
++ /* Free extra memory if any. */
++ freeSize = allocSize - size;
++ if (freeSize != 0)
++ {
++ _FreeExtraSpace(OutputBuffer, item, size, freeSize);
++ }
++#endif
++}
++
++static void
++_AppendBuffer(
++ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer,
++ IN gctINT Indent,
++ IN gctPOINTER PrefixData,
++ IN gctPOINTER Data,
++ IN gctUINT Address,
++ IN gctUINT DataSize,
++ IN gceDUMP_BUFFER Type,
++ IN gctUINT32 DmaAddress
++ )
++{
++#if gcdHAVEPREFIX
++ gctUINT8_PTR prefixData;
++ gcsBUFITEM_BUFFER_PTR item;
++ gctINT allocSize;
++ gctPOINTER data;
++
++#if gcdALIGNBYSIZE
++ gctUINT alignment;
++ gctINT size, freeSize;
++#endif
++
++ gcmDBGASSERT(DataSize != 0, "%d", DataSize);
++ gcmDBGASSERT(Data != gcvNULL, "%p", Data);
++
++ /* Determine the maximum item size. */
++ allocSize
++ = gcmSIZEOF(gcsBUFITEM_BUFFER)
++ + gcdPREFIX_SIZE
++ + gcdPREFIX_ALIGNMENT
++ + DataSize;
++
++ /* Allocate prefix item. */
++ item = (gcsBUFITEM_BUFFER_PTR) _AllocateItem(OutputBuffer, allocSize);
++
++ /* Compute the initial prefix data pointer. */
++ prefixData = (gctUINT8_PTR) (item + 1);
++
++#if gcdALIGNBYSIZE
++ /* Align the data pointer as necessary. */
++ alignment = gcmPTRALIGNMENT(prefixData, gcdPREFIX_ALIGNMENT);
++ prefixData += alignment;
++#endif
++
++ /* Set item data. */
++ item->type = gcvBUFITEM_BUFFER;
++ item->indent = Indent;
++ item->bufferType = Type;
++ item->dataSize = DataSize;
++ item->address = Address;
++ item->prefixData = prefixData;
++
++#if gcdDMA_BUFFER_COUNT && (gcdTHREAD_BUFFERS == 1)
++ item->dmaAddress = DmaAddress;
++#endif
++
++ /* Copy prefix data. */
++ memcpy(prefixData, PrefixData, gcdPREFIX_SIZE);
++
++ /* Compute the data pointer. */
++ data = prefixData + gcdPREFIX_SIZE;
++
++ /* Copy argument value. */
++ memcpy(data, Data, DataSize);
++
++#if gcdALIGNBYSIZE
++ /* Compute the actual node size. */
++ size
++ = gcmSIZEOF(gcsBUFITEM_BUFFER)
++ + gcdPREFIX_SIZE
++ + alignment
++ + DataSize;
++
++ /* Free extra memory if any. */
++ freeSize = allocSize - size;
++ if (freeSize != 0)
++ {
++ _FreeExtraSpace(OutputBuffer, item, size, freeSize);
++ }
++#endif
++#else
++ gcsBUFITEM_BUFFER_PTR item;
++ gctINT size;
++
++ gcmDBGASSERT(DataSize != 0, "%d", DataSize);
++ gcmDBGASSERT(Data != gcvNULL, "%p", Data);
++
++ /* Determine the maximum item size. */
++ size = gcmSIZEOF(gcsBUFITEM_BUFFER) + DataSize;
++
++ /* Allocate prefix item. */
++ item = (gcsBUFITEM_BUFFER_PTR) _AllocateItem(OutputBuffer, size);
++
++ /* Set item data. */
++ item->type = gcvBUFITEM_BUFFER;
++ item->indent = Indent;
++ item->dataSize = DataSize;
++ item->address = Address;
++
++ /* Copy argument value. */
++ memcpy(item + 1, Data, DataSize);
++#endif
++}
++#endif
++
++static gcmINLINE void
++_InitBuffers(
++ void
++ )
++{
++ int i;
++
++ if (_outputBufferHead == gcvNULL)
++ {
++ for (i = 0; i < gcdTHREAD_BUFFERS; i += 1)
++ {
++ if (_outputBufferTail == gcvNULL)
++ {
++ _outputBufferHead = &_outputBuffer[i];
++ }
++ else
++ {
++ _outputBufferTail->next = &_outputBuffer[i];
++ }
++
++#if gcdTHREAD_BUFFERS > 1
++ _outputBuffer[i].threadID = ~0U;
++#endif
++
++ _outputBuffer[i].prev = _outputBufferTail;
++ _outputBuffer[i].next = gcvNULL;
++
++ _outputBufferTail = &_outputBuffer[i];
++ }
++ }
++}
++
++static gcmINLINE gcsBUFFERED_OUTPUT_PTR
++_GetOutputBuffer(
++ void
++ )
++{
++ gcsBUFFERED_OUTPUT_PTR outputBuffer;
++
++#if gcdTHREAD_BUFFERS > 1
++ /* Get the current thread ID. */
++ gctUINT32 ThreadID = gcmkGETTHREADID();
++
++ /* Locate the output buffer for the thread. */
++ outputBuffer = _outputBufferHead;
++
++ while (outputBuffer != gcvNULL)
++ {
++ if (outputBuffer->threadID == ThreadID)
++ {
++ break;
++ }
++
++ outputBuffer = outputBuffer->next;
++ }
++
++ /* No matching buffer found? */
++ if (outputBuffer == gcvNULL)
++ {
++ /* Get the tail for the buffer. */
++ outputBuffer = _outputBufferTail;
++
++ /* Move it to the head. */
++ _outputBufferTail = _outputBufferTail->prev;
++ _outputBufferTail->next = gcvNULL;
++
++ outputBuffer->prev = gcvNULL;
++ outputBuffer->next = _outputBufferHead;
++
++ _outputBufferHead->prev = outputBuffer;
++ _outputBufferHead = outputBuffer;
++
++ /* Reset the buffer. */
++ outputBuffer->threadID = ThreadID;
++#if gcdBUFFERED_OUTPUT
++ outputBuffer->start = 0;
++ outputBuffer->index = 0;
++ outputBuffer->count = 0;
++#endif
++#if gcdSHOW_LINE_NUMBER
++ outputBuffer->lineNumber = 0;
++#endif
++ }
++#else
++ outputBuffer = _outputBufferHead;
++#endif
++
++ return outputBuffer;
++}
++
++static gcmINLINE int _GetArgumentSize(
++ IN gctCONST_STRING Message
++ )
++{
++ int i, count;
++
++ gcmDBGASSERT(Message != gcvNULL, "%p", Message);
++
++ for (i = 0, count = 0; Message[i]; i += 1)
++ {
++ if (Message[i] == '%')
++ {
++ count += 1;
++ }
++ }
++
++ return count * gcmSIZEOF(gctUINT32);
++}
++
++#if gcdHAVEPREFIX
++static void
++_InitPrefixData(
++ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer,
++ IN gctPOINTER Data
++ )
++{
++ gctUINT8_PTR data = (gctUINT8_PTR) Data;
++
++#if gcdSHOW_TIME
++ {
++ gctUINT64 time;
++ gckOS_GetProfileTick(&time);
++ gcmkALIGNPTR(gctUINT8_PTR, data, gcmSIZEOF(gctUINT64));
++ * ((gctUINT64_PTR) data) = time;
++ data += gcmSIZEOF(gctUINT64);
++ }
++#endif
++
++#if gcdSHOW_LINE_NUMBER
++ {
++ gcmkALIGNPTR(gctUINT8_PTR, data, gcmSIZEOF(gctUINT64));
++ * ((gctUINT64_PTR) data) = OutputBuffer->lineNumber;
++ data += gcmSIZEOF(gctUINT64);
++ }
++#endif
++
++#if gcdSHOW_PROCESS_ID
++ {
++ gcmkALIGNPTR(gctUINT8_PTR, data, gcmSIZEOF(gctUINT32));
++ * ((gctUINT32_PTR) data) = gcmkGETPROCESSID();
++ data += gcmSIZEOF(gctUINT32);
++ }
++#endif
++
++#if gcdSHOW_THREAD_ID
++ {
++ gcmkALIGNPTR(gctUINT8_PTR, data, gcmSIZEOF(gctUINT32));
++ * ((gctUINT32_PTR) data) = gcmkGETTHREADID();
++ }
++#endif
++}
++#endif
++
++static void
++_Print(
++ IN gctUINT ArgumentSize,
++ IN gctBOOL CopyMessage,
++ IN gctCONST_STRING Message,
++ IN gctARGUMENTS Arguments
++ )
++{
++ gcsBUFFERED_OUTPUT_PTR outputBuffer;
++ gcmkDECLARE_LOCK(lockHandle);
++
++ gcmkLOCKSECTION(lockHandle);
++
++ /* Initialize output buffer list. */
++ _InitBuffers();
++
++ /* Locate the proper output buffer. */
++ outputBuffer = _GetOutputBuffer();
++
++ /* Update the line number. */
++#if gcdSHOW_LINE_NUMBER
++ outputBuffer->lineNumber += 1;
++#endif
++
++ /* Print prefix. */
++#if gcdHAVEPREFIX
++ {
++ gctUINT8_PTR alignedPrefixData;
++ gctUINT8 prefixData[gcdPREFIX_SIZE + gcdPREFIX_ALIGNMENT];
++
++ /* Compute aligned pointer. */
++ alignedPrefixData = prefixData;
++ gcmkALIGNPTR(gctUINT8_PTR, alignedPrefixData, gcdPREFIX_ALIGNMENT);
++
++ /* Initialize the prefix data. */
++ _InitPrefixData(outputBuffer, alignedPrefixData);
++
++ /* Print the prefix. */
++ gcdOUTPUTPREFIX(outputBuffer, alignedPrefixData);
++ }
++#endif
++
++ /* Form the indent string. */
++ if (strncmp(Message, "--", 2) == 0)
++ {
++ outputBuffer->indent -= 2;
++ }
++
++ /* Print the message. */
++ if (CopyMessage)
++ {
++ gcdOUTPUTCOPY(
++ outputBuffer, outputBuffer->indent,
++ Message, ArgumentSize, * (gctPOINTER *) &Arguments
++ );
++ }
++ else
++ {
++ gcdOUTPUTSTRING(
++ outputBuffer, outputBuffer->indent,
++ Message, ArgumentSize, * (gctPOINTER *) &Arguments
++ );
++ }
++
++ /* Check increasing indent. */
++ if (strncmp(Message, "++", 2) == 0)
++ {
++ outputBuffer->indent += 2;
++ }
++
++ gcmkUNLOCKSECTION(lockHandle);
++}
++
++
++/******************************************************************************\
++********************************* Debug Macros *********************************
++\******************************************************************************/
++
++#ifdef __QNXNTO__
++
++extern volatile unsigned g_nQnxInIsrs;
++
++#define gcmDEBUGPRINT(ArgumentSize, CopyMessage, Message) \
++{ \
++ if (atomic_add_value(&g_nQnxInIsrs, 1) == 0) \
++ { \
++ gctARGUMENTS __arguments__; \
++ gcmkARGUMENTS_START(__arguments__, Message); \
++ _Print(ArgumentSize, CopyMessage, Message, __arguments__); \
++ gcmkARGUMENTS_END(__arguments__); \
++ } \
++ atomic_sub(&g_nQnxInIsrs, 1); \
++}
++
++#else
++
++#define gcmDEBUGPRINT(ArgumentSize, CopyMessage, Message) \
++{ \
++ gctARGUMENTS __arguments__; \
++ gcmkARGUMENTS_START(__arguments__, Message); \
++ _Print(ArgumentSize, CopyMessage, Message, __arguments__); \
++ gcmkARGUMENTS_END(__arguments__); \
++}
++
++#endif
++
++/******************************************************************************\
++********************************** Debug Code **********************************
++\******************************************************************************/
++
++/*******************************************************************************
++**
++** gckOS_Print
++**
++** Send a message to the debugger.
++**
++** INPUT:
++**
++** gctCONST_STRING Message
++** Pointer to message.
++**
++** ...
++** Optional arguments.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++void
++gckOS_Print(
++ IN gctCONST_STRING Message,
++ ...
++ )
++{
++ gcmDEBUGPRINT(_GetArgumentSize(Message), gcvFALSE, Message);
++}
++
++/*******************************************************************************
++**
++** gckOS_PrintN
++**
++** Send a message to the debugger.
++**
++** INPUT:
++**
++** gctUINT ArgumentSize
++** The size of the optional arguments in bytes.
++**
++** gctCONST_STRING Message
++** Pointer to message.
++**
++** ...
++** Optional arguments.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++void
++gckOS_PrintN(
++ IN gctUINT ArgumentSize,
++ IN gctCONST_STRING Message,
++ ...
++ )
++{
++ gcmDEBUGPRINT(ArgumentSize, gcvFALSE, Message);
++}
++
++/*******************************************************************************
++**
++** gckOS_CopyPrint
++**
++** Send a message to the debugger. If in buffered output mode, the entire
++** message will be copied into the buffer instead of using the pointer to
++** the string.
++**
++** INPUT:
++**
++** gctCONST_STRING Message
++** Pointer to message.
++**
++** ...
++** Optional arguments.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++void
++gckOS_CopyPrint(
++ IN gctCONST_STRING Message,
++ ...
++ )
++{
++ gcmDEBUGPRINT(_GetArgumentSize(Message), gcvTRUE, Message);
++}
++
++/*******************************************************************************
++**
++** gckOS_DumpBuffer
++**
++** Print the contents of the specified buffer.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to gckOS object.
++**
++** gctPOINTER Buffer
++** Pointer to the buffer to print.
++**
++** gctUINT Size
++** Size of the buffer.
++**
++** gceDUMP_BUFFER Type
++** Buffer type.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++void
++gckOS_DumpBuffer(
++ IN gckOS Os,
++ IN gctPOINTER Buffer,
++ IN gctUINT Size,
++ IN gceDUMP_BUFFER Type,
++ IN gctBOOL CopyMessage
++ )
++{
++ gctUINT32 address;
++ gcsBUFFERED_OUTPUT_PTR outputBuffer;
++ static gctBOOL userLocked;
++ gctCHAR *buffer = (gctCHAR*)Buffer;
++
++ gcmkDECLARE_LOCK(lockHandle);
++
++ /* Request lock when not coming from user,
++ or coming from user and not yet locked
++ and message is starting with @[. */
++ if (Type == gceDUMP_BUFFER_FROM_USER)
++ {
++ if ((Size > 2)
++ && (buffer[0] == '@')
++ && (buffer[1] == '['))
++ {
++ /* Beginning of a user dump. */
++ gcmkLOCKSECTION(lockHandle);
++ userLocked = gcvTRUE;
++ }
++ /* Else, let it pass through. */
++ }
++ else
++ {
++ gcmkLOCKSECTION(lockHandle);
++ userLocked = gcvFALSE;
++ }
++
++ if (Buffer != gcvNULL)
++ {
++ /* Initialize output buffer list. */
++ _InitBuffers();
++
++ /* Locate the proper output buffer. */
++ outputBuffer = _GetOutputBuffer();
++
++ /* Update the line number. */
++#if gcdSHOW_LINE_NUMBER
++ outputBuffer->lineNumber += 1;
++#endif
++
++ /* Get the physical address of the buffer. */
++ if (Type != gceDUMP_BUFFER_FROM_USER)
++ {
++ gcmkVERIFY_OK(gckOS_GetPhysicalAddress(Os, Buffer, &address));
++ }
++ else
++ {
++ address = 0;
++ }
++
++#if gcdHAVEPREFIX
++ {
++ gctUINT8_PTR alignedPrefixData;
++ gctUINT8 prefixData[gcdPREFIX_SIZE + gcdPREFIX_ALIGNMENT];
++
++ /* Compute aligned pointer. */
++ alignedPrefixData = prefixData;
++ gcmkALIGNPTR(gctUINT8_PTR, alignedPrefixData, gcdPREFIX_ALIGNMENT);
++
++ /* Initialize the prefix data. */
++ _InitPrefixData(outputBuffer, alignedPrefixData);
++
++ /* Print/schedule the buffer. */
++ gcdOUTPUTBUFFER(
++ outputBuffer, outputBuffer->indent,
++ alignedPrefixData, Buffer, address, Size, Type, 0
++ );
++ }
++#else
++ /* Print/schedule the buffer. */
++ if (Type == gceDUMP_BUFFER_FROM_USER)
++ {
++ gcdOUTPUTSTRING(
++ outputBuffer, outputBuffer->indent,
++ Buffer, 0, gcvNULL
++ );
++ }
++ else
++ {
++ gcdOUTPUTBUFFER(
++ outputBuffer, outputBuffer->indent,
++ gcvNULL, Buffer, address, Size, Type, 0
++ );
++ }
++#endif
++ }
++
++ /* Unlock when not coming from user,
++ or coming from user and not yet locked. */
++ if (userLocked)
++ {
++ if ((Size > 4)
++ && (buffer[0] == ']')
++ && (buffer[1] == ' ')
++ && (buffer[2] == '-')
++ && (buffer[3] == '-'))
++ {
++ /* End of a user dump. */
++ gcmkUNLOCKSECTION(lockHandle);
++ userLocked = gcvFALSE;
++ }
++ /* Else, let it pass through, don't unlock. */
++ }
++ else
++ {
++ gcmkUNLOCKSECTION(lockHandle);
++ }
++}
++
++/*******************************************************************************
++**
++** gckOS_DebugTrace
++**
++** Send a leveled message to the debugger.
++**
++** INPUT:
++**
++** gctUINT32 Level
++** Debug level of message.
++**
++** gctCONST_STRING Message
++** Pointer to message.
++**
++** ...
++** Optional arguments.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++void
++gckOS_DebugTrace(
++ IN gctUINT32 Level,
++ IN gctCONST_STRING Message,
++ ...
++ )
++{
++ if (Level > _debugLevel)
++ {
++ return;
++ }
++
++ gcmDEBUGPRINT(_GetArgumentSize(Message), gcvFALSE, Message);
++}
++
++/*******************************************************************************
++**
++** gckOS_DebugTraceN
++**
++** Send a leveled message to the debugger.
++**
++** INPUT:
++**
++** gctUINT32 Level
++** Debug level of message.
++**
++** gctUINT ArgumentSize
++** The size of the optional arguments in bytes.
++**
++** gctCONST_STRING Message
++** Pointer to message.
++**
++** ...
++** Optional arguments.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++void
++gckOS_DebugTraceN(
++ IN gctUINT32 Level,
++ IN gctUINT ArgumentSize,
++ IN gctCONST_STRING Message,
++ ...
++ )
++{
++ if (Level > _debugLevel)
++ {
++ return;
++ }
++
++ gcmDEBUGPRINT(ArgumentSize, gcvFALSE, Message);
++}
++
++/*******************************************************************************
++**
++** gckOS_DebugTraceZone
++**
++** Send a leveled and zoned message to the debugger.
++**
++** INPUT:
++**
++** gctUINT32 Level
++** Debug level for message.
++**
++** gctUINT32 Zone
++** Debug zone for message.
++**
++** gctCONST_STRING Message
++** Pointer to message.
++**
++** ...
++** Optional arguments.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++void
++gckOS_DebugTraceZone(
++ IN gctUINT32 Level,
++ IN gctUINT32 Zone,
++ IN gctCONST_STRING Message,
++ ...
++ )
++{
++ if ((Level > _debugLevel) || !(Zone & _debugZones))
++ {
++ return;
++ }
++
++ gcmDEBUGPRINT(_GetArgumentSize(Message), gcvFALSE, Message);
++}
++
++/*******************************************************************************
++**
++** gckOS_DebugTraceZoneN
++**
++** Send a leveled and zoned message to the debugger.
++**
++** INPUT:
++**
++** gctUINT32 Level
++** Debug level for message.
++**
++** gctUINT32 Zone
++** Debug zone for message.
++**
++** gctUINT ArgumentSize
++** The size of the optional arguments in bytes.
++**
++** gctCONST_STRING Message
++** Pointer to message.
++**
++** ...
++** Optional arguments.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++void
++gckOS_DebugTraceZoneN(
++ IN gctUINT32 Level,
++ IN gctUINT32 Zone,
++ IN gctUINT ArgumentSize,
++ IN gctCONST_STRING Message,
++ ...
++ )
++{
++ if ((Level > _debugLevel) || !(Zone & _debugZones))
++ {
++ return;
++ }
++
++ gcmDEBUGPRINT(ArgumentSize, gcvFALSE, Message);
++}
++
++/*******************************************************************************
++**
++** gckOS_DebugBreak
++**
++** Break into the debugger.
++**
++** INPUT:
++**
++** Nothing.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++void
++gckOS_DebugBreak(
++ void
++ )
++{
++ gckOS_DebugTrace(gcvLEVEL_ERROR, "%s(%d)", __FUNCTION__, __LINE__);
++}
++
++/*******************************************************************************
++**
++** gckOS_DebugFatal
++**
++** Send a message to the debugger and break into the debugger.
++**
++** INPUT:
++**
++** gctCONST_STRING Message
++** Pointer to message.
++**
++** ...
++** Optional arguments.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++void
++gckOS_DebugFatal(
++ IN gctCONST_STRING Message,
++ ...
++ )
++{
++ gcmkPRINT_VERSION();
++ gcmDEBUGPRINT(_GetArgumentSize(Message), gcvFALSE, Message);
++
++ /* Break into the debugger. */
++ gckOS_DebugBreak();
++}
++
++/*******************************************************************************
++**
++** gckOS_SetDebugLevel
++**
++** Set the debug level.
++**
++** INPUT:
++**
++** gctUINT32 Level
++** New debug level.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++void
++gckOS_SetDebugLevel(
++ IN gctUINT32 Level
++ )
++{
++ _debugLevel = Level;
++}
++
++/*******************************************************************************
++**
++** gckOS_SetDebugZone
++**
++** Set the debug zone.
++**
++** INPUT:
++**
++** gctUINT32 Zone
++** New debug zone.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++void
++gckOS_SetDebugZone(
++ IN gctUINT32 Zone
++ )
++{
++ _debugZones = Zone;
++}
++
++/*******************************************************************************
++**
++** gckOS_SetDebugLevelZone
++**
++** Set the debug level and zone.
++**
++** INPUT:
++**
++** gctUINT32 Level
++** New debug level.
++**
++** gctUINT32 Zone
++** New debug zone.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++void
++gckOS_SetDebugLevelZone(
++ IN gctUINT32 Level,
++ IN gctUINT32 Zone
++ )
++{
++ _debugLevel = Level;
++ _debugZones = Zone;
++}
++
++/*******************************************************************************
++**
++** gckOS_SetDebugZones
++**
++** Enable or disable debug zones.
++**
++** INPUT:
++**
++** gctUINT32 Zones
++** Debug zones to enable or disable.
++**
++** gctBOOL Enable
++** Set to gcvTRUE to enable the zones (or the Zones with the current
++** zones) or gcvFALSE to disable the specified Zones.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++void
++gckOS_SetDebugZones(
++ IN gctUINT32 Zones,
++ IN gctBOOL Enable
++ )
++{
++ if (Enable)
++ {
++ /* Enable the zones. */
++ _debugZones |= Zones;
++ }
++ else
++ {
++ /* Disable the zones. */
++ _debugZones &= ~Zones;
++ }
++}
++
++/*******************************************************************************
++**
++** gckOS_Verify
++**
++** Called to verify the result of a function call.
++**
++** INPUT:
++**
++** gceSTATUS Status
++** Function call result.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++void
++gckOS_Verify(
++ IN gceSTATUS status
++ )
++{
++ _lastError = status;
++}
++
++/*******************************************************************************
++**
++** gckOS_DebugFlush
++**
++** Force messages to be flushed out.
++**
++** INPUT:
++**
++** gctCONST_STRING CallerName
++** Name of the caller function.
++**
++** gctUINT LineNumber
++** Line number of the caller.
++**
++** gctUINT32 DmaAddress
++** The current DMA address or ~0U to ignore.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++void
++gckOS_DebugFlush(
++ gctCONST_STRING CallerName,
++ gctUINT LineNumber,
++ gctUINT32 DmaAddress
++ )
++{
++#if gcdBUFFERED_OUTPUT
++ _DirectPrint("\nFlush requested by %s(%d).\n\n", CallerName, LineNumber);
++ _Flush(DmaAddress);
++#endif
++}
++gctCONST_STRING
++gckOS_DebugStatus2Name(
++ gceSTATUS status
++ )
++{
++ switch (status)
++ {
++ case gcvSTATUS_OK:
++ return "gcvSTATUS_OK";
++ case gcvSTATUS_TRUE:
++ return "gcvSTATUS_TRUE";
++ case gcvSTATUS_NO_MORE_DATA:
++ return "gcvSTATUS_NO_MORE_DATA";
++ case gcvSTATUS_CACHED:
++ return "gcvSTATUS_CACHED";
++ case gcvSTATUS_MIPMAP_TOO_LARGE:
++ return "gcvSTATUS_MIPMAP_TOO_LARGE";
++ case gcvSTATUS_NAME_NOT_FOUND:
++ return "gcvSTATUS_NAME_NOT_FOUND";
++ case gcvSTATUS_NOT_OUR_INTERRUPT:
++ return "gcvSTATUS_NOT_OUR_INTERRUPT";
++ case gcvSTATUS_MISMATCH:
++ return "gcvSTATUS_MISMATCH";
++ case gcvSTATUS_MIPMAP_TOO_SMALL:
++ return "gcvSTATUS_MIPMAP_TOO_SMALL";
++ case gcvSTATUS_LARGER:
++ return "gcvSTATUS_LARGER";
++ case gcvSTATUS_SMALLER:
++ return "gcvSTATUS_SMALLER";
++ case gcvSTATUS_CHIP_NOT_READY:
++ return "gcvSTATUS_CHIP_NOT_READY";
++ case gcvSTATUS_NEED_CONVERSION:
++ return "gcvSTATUS_NEED_CONVERSION";
++ case gcvSTATUS_SKIP:
++ return "gcvSTATUS_SKIP";
++ case gcvSTATUS_DATA_TOO_LARGE:
++ return "gcvSTATUS_DATA_TOO_LARGE";
++ case gcvSTATUS_INVALID_CONFIG:
++ return "gcvSTATUS_INVALID_CONFIG";
++ case gcvSTATUS_CHANGED:
++ return "gcvSTATUS_CHANGED";
++ case gcvSTATUS_NOT_SUPPORT_DITHER:
++ return "gcvSTATUS_NOT_SUPPORT_DITHER";
++
++ case gcvSTATUS_INVALID_ARGUMENT:
++ return "gcvSTATUS_INVALID_ARGUMENT";
++ case gcvSTATUS_INVALID_OBJECT:
++ return "gcvSTATUS_INVALID_OBJECT";
++ case gcvSTATUS_OUT_OF_MEMORY:
++ return "gcvSTATUS_OUT_OF_MEMORY";
++ case gcvSTATUS_MEMORY_LOCKED:
++ return "gcvSTATUS_MEMORY_LOCKED";
++ case gcvSTATUS_MEMORY_UNLOCKED:
++ return "gcvSTATUS_MEMORY_UNLOCKED";
++ case gcvSTATUS_HEAP_CORRUPTED:
++ return "gcvSTATUS_HEAP_CORRUPTED";
++ case gcvSTATUS_GENERIC_IO:
++ return "gcvSTATUS_GENERIC_IO";
++ case gcvSTATUS_INVALID_ADDRESS:
++ return "gcvSTATUS_INVALID_ADDRESS";
++ case gcvSTATUS_CONTEXT_LOSSED:
++ return "gcvSTATUS_CONTEXT_LOSSED";
++ case gcvSTATUS_TOO_COMPLEX:
++ return "gcvSTATUS_TOO_COMPLEX";
++ case gcvSTATUS_BUFFER_TOO_SMALL:
++ return "gcvSTATUS_BUFFER_TOO_SMALL";
++ case gcvSTATUS_INTERFACE_ERROR:
++ return "gcvSTATUS_INTERFACE_ERROR";
++ case gcvSTATUS_NOT_SUPPORTED:
++ return "gcvSTATUS_NOT_SUPPORTED";
++ case gcvSTATUS_MORE_DATA:
++ return "gcvSTATUS_MORE_DATA";
++ case gcvSTATUS_TIMEOUT:
++ return "gcvSTATUS_TIMEOUT";
++ case gcvSTATUS_OUT_OF_RESOURCES:
++ return "gcvSTATUS_OUT_OF_RESOURCES";
++ case gcvSTATUS_INVALID_DATA:
++ return "gcvSTATUS_INVALID_DATA";
++ case gcvSTATUS_INVALID_MIPMAP:
++ return "gcvSTATUS_INVALID_MIPMAP";
++ case gcvSTATUS_NOT_FOUND:
++ return "gcvSTATUS_NOT_FOUND";
++ case gcvSTATUS_NOT_ALIGNED:
++ return "gcvSTATUS_NOT_ALIGNED";
++ case gcvSTATUS_INVALID_REQUEST:
++ return "gcvSTATUS_INVALID_REQUEST";
++ case gcvSTATUS_GPU_NOT_RESPONDING:
++ return "gcvSTATUS_GPU_NOT_RESPONDING";
++ case gcvSTATUS_TIMER_OVERFLOW:
++ return "gcvSTATUS_TIMER_OVERFLOW";
++ case gcvSTATUS_VERSION_MISMATCH:
++ return "gcvSTATUS_VERSION_MISMATCH";
++ case gcvSTATUS_LOCKED:
++ return "gcvSTATUS_LOCKED";
++
++ /* Linker errors. */
++ case gcvSTATUS_GLOBAL_TYPE_MISMATCH:
++ return "gcvSTATUS_GLOBAL_TYPE_MISMATCH";
++ case gcvSTATUS_TOO_MANY_ATTRIBUTES:
++ return "gcvSTATUS_TOO_MANY_ATTRIBUTES";
++ case gcvSTATUS_TOO_MANY_UNIFORMS:
++ return "gcvSTATUS_TOO_MANY_UNIFORMS";
++ case gcvSTATUS_TOO_MANY_VARYINGS:
++ return "gcvSTATUS_TOO_MANY_VARYINGS";
++ case gcvSTATUS_UNDECLARED_VARYING:
++ return "gcvSTATUS_UNDECLARED_VARYING";
++ case gcvSTATUS_VARYING_TYPE_MISMATCH:
++ return "gcvSTATUS_VARYING_TYPE_MISMATCH";
++ case gcvSTATUS_MISSING_MAIN:
++ return "gcvSTATUS_MISSING_MAIN";
++ case gcvSTATUS_NAME_MISMATCH:
++ return "gcvSTATUS_NAME_MISMATCH";
++ case gcvSTATUS_INVALID_INDEX:
++ return "gcvSTATUS_INVALID_INDEX";
++ default:
++ return "nil";
++ }
++}
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_event.c linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_event.c
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_event.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_event.c 2015-07-27 23:13:06.194879670 +0200
+@@ -0,0 +1,2898 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_precomp.h"
++#include "gc_hal_kernel_buffer.h"
++
++#ifdef __QNXNTO__
++#include <atomic.h>
++#include "gc_hal_kernel_qnx.h"
++#endif
++
++#define _GC_OBJ_ZONE gcvZONE_EVENT
++
++#define gcdEVENT_ALLOCATION_COUNT (4096 / gcmSIZEOF(gcsHAL_INTERFACE))
++#define gcdEVENT_MIN_THRESHOLD 4
++
++/******************************************************************************\
++********************************* Support Code *********************************
++\******************************************************************************/
++
++static gceSTATUS
++gckEVENT_AllocateQueue(
++ IN gckEVENT Event,
++ OUT gcsEVENT_QUEUE_PTR * Queue
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Event=0x%x", Event);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++ gcmkVERIFY_ARGUMENT(Queue != gcvNULL);
++
++ /* Do we have free queues? */
++ if (Event->freeList == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++ /* Move one free queue from the free list. */
++ * Queue = Event->freeList;
++ Event->freeList = Event->freeList->next;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Queue=0x%x", gcmOPT_POINTER(Queue));
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++static gceSTATUS
++gckEVENT_FreeQueue(
++ IN gckEVENT Event,
++ OUT gcsEVENT_QUEUE_PTR Queue
++ )
++{
++ gceSTATUS status = gcvSTATUS_OK;
++
++ gcmkHEADER_ARG("Event=0x%x", Event);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++ gcmkVERIFY_ARGUMENT(Queue != gcvNULL);
++
++ /* Move one free queue from the free list. */
++ Queue->next = Event->freeList;
++ Event->freeList = Queue;
++
++ /* Success. */
++ gcmkFOOTER();
++ return status;
++}
++
++static gceSTATUS
++gckEVENT_FreeRecord(
++ IN gckEVENT Event,
++ IN gcsEVENT_PTR Record
++ )
++{
++ gceSTATUS status;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Event=0x%x Record=0x%x", Event, Record);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++ gcmkVERIFY_ARGUMENT(Record != gcvNULL);
++
++ /* Acquire the mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(Event->os,
++ Event->freeEventMutex,
++ gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Push the record on the free list. */
++ Record->next = Event->freeEventList;
++ Event->freeEventList = Record;
++ Event->freeEventCount += 1;
++
++ /* Release the mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Event->os, Event->freeEventMutex));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Roll back. */
++ if (acquired)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Event->os, Event->freeEventMutex));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return gcvSTATUS_OK;
++}
++
++static gceSTATUS
++gckEVENT_IsEmpty(
++ IN gckEVENT Event,
++ OUT gctBOOL_PTR IsEmpty
++ )
++{
++ gceSTATUS status;
++ gctSIZE_T i;
++
++ gcmkHEADER_ARG("Event=0x%x", Event);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++ gcmkVERIFY_ARGUMENT(IsEmpty != gcvNULL);
++
++ /* Assume the event queue is empty. */
++ *IsEmpty = gcvTRUE;
++
++ /* Try acquiring the mutex. */
++ status = gckOS_AcquireMutex(Event->os, Event->eventQueueMutex, 0);
++ if (status == gcvSTATUS_TIMEOUT)
++ {
++ /* Timeout - queue is no longer empty. */
++ *IsEmpty = gcvFALSE;
++ }
++ else
++ {
++ /* Bail out on error. */
++ gcmkONERROR(status);
++
++ /* Walk the event queue. */
++ for (i = 0; i < gcmCOUNTOF(Event->queues); ++i)
++ {
++ /* Check whether this event is in use. */
++ if (Event->queues[i].head != gcvNULL)
++ {
++ /* The event is in use, hence the queue is not empty. */
++ *IsEmpty = gcvFALSE;
++ break;
++ }
++ }
++
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Event->os, Event->eventQueueMutex));
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*IsEmpty=%d", gcmOPT_VALUE(IsEmpty));
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++static gceSTATUS
++_TryToIdleGPU(
++ IN gckEVENT Event
++)
++{
++ gceSTATUS status;
++ gctBOOL empty = gcvFALSE, idle = gcvFALSE;
++ gctBOOL powerLocked = gcvFALSE;
++ gckHARDWARE hardware;
++
++ gcmkHEADER_ARG("Event=0x%x", Event);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++
++ /* Grab gckHARDWARE object. */
++ hardware = Event->kernel->hardware;
++ gcmkVERIFY_OBJECT(hardware, gcvOBJ_HARDWARE);
++
++ /* Check whether the event queue is empty. */
++ gcmkONERROR(gckEVENT_IsEmpty(Event, &empty));
++
++ if (empty)
++ {
++ status = gckOS_AcquireMutex(hardware->os, hardware->powerMutex, 0);
++ if (status == gcvSTATUS_TIMEOUT)
++ {
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++
++ powerLocked = gcvTRUE;
++
++ /* Query whether the hardware is idle. */
++ gcmkONERROR(gckHARDWARE_QueryIdle(Event->kernel->hardware, &idle));
++
++ gcmkONERROR(gckOS_ReleaseMutex(hardware->os, hardware->powerMutex));
++ powerLocked = gcvFALSE;
++
++ if (idle)
++ {
++ /* Inform the system of idle GPU. */
++ gcmkONERROR(gckOS_Broadcast(Event->os,
++ Event->kernel->hardware,
++ gcvBROADCAST_GPU_IDLE));
++ }
++ }
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (powerLocked)
++ {
++ gcmkONERROR(gckOS_ReleaseMutex(hardware->os, hardware->powerMutex));
++ powerLocked = gcvFALSE;
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++static gceSTATUS
++__RemoveRecordFromProcessDB(
++ IN gckEVENT Event,
++ IN gcsEVENT_PTR Record
++ )
++{
++ gcmkHEADER_ARG("Event=0x%x Record=0x%x", Event, Record);
++ gcmkVERIFY_ARGUMENT(Record != gcvNULL);
++
++ while (Record != gcvNULL)
++ {
++ if (Record->info.command == gcvHAL_SIGNAL)
++ {
++ /* TODO: Find a better place to bind signal to hardware.*/
++ gcmkVERIFY_OK(gckOS_SignalSetHardware(Event->os,
++ gcmUINT64_TO_PTR(Record->info.u.Signal.signal),
++ Event->kernel->hardware));
++ }
++
++ if (Record->fromKernel)
++ {
++ /* No need to check db if event is from kernel. */
++ Record = Record->next;
++ continue;
++ }
++
++ switch (Record->info.command)
++ {
++ case gcvHAL_FREE_NON_PAGED_MEMORY:
++ gcmkVERIFY_OK(gckKERNEL_RemoveProcessDB(
++ Event->kernel,
++ Record->processID,
++ gcvDB_NON_PAGED,
++ gcmUINT64_TO_PTR(Record->info.u.FreeNonPagedMemory.logical)));
++ break;
++
++ case gcvHAL_FREE_CONTIGUOUS_MEMORY:
++ gcmkVERIFY_OK(gckKERNEL_RemoveProcessDB(
++ Event->kernel,
++ Record->processID,
++ gcvDB_CONTIGUOUS,
++ gcmUINT64_TO_PTR(Record->info.u.FreeContiguousMemory.logical)));
++ break;
++
++ case gcvHAL_FREE_VIDEO_MEMORY:
++ gcmkVERIFY_OK(gckKERNEL_RemoveProcessDB(
++ Event->kernel,
++ Record->processID,
++ gcvDB_VIDEO_MEMORY,
++ gcmUINT64_TO_PTR(Record->info.u.FreeVideoMemory.node)));
++
++ {
++ gcuVIDMEM_NODE_PTR node = (gcuVIDMEM_NODE_PTR)(gcmUINT64_TO_PTR(Record->info.u.FreeVideoMemory.node));
++
++ if (node->VidMem.memory->object.type == gcvOBJ_VIDMEM)
++ {
++ gcmkVERIFY_OK(gckKERNEL_RemoveProcessDB(Event->kernel,
++ Record->processID,
++ gcvDB_VIDEO_MEMORY_RESERVED,
++ node));
++ }
++ else if(node->Virtual.contiguous)
++ {
++ gcmkVERIFY_OK(gckKERNEL_RemoveProcessDB(Event->kernel,
++ Record->processID,
++ gcvDB_VIDEO_MEMORY_CONTIGUOUS,
++ node));
++ }
++ else
++ {
++ gcmkVERIFY_OK(gckKERNEL_RemoveProcessDB(Event->kernel,
++ Record->processID,
++ gcvDB_VIDEO_MEMORY_VIRTUAL,
++ node));
++ }
++ }
++
++ break;
++
++ case gcvHAL_UNLOCK_VIDEO_MEMORY:
++ gcmkVERIFY_OK(gckKERNEL_RemoveProcessDB(
++ Event->kernel,
++ Record->processID,
++ gcvDB_VIDEO_MEMORY_LOCKED,
++ gcmUINT64_TO_PTR(Record->info.u.UnlockVideoMemory.node)));
++ break;
++
++ case gcvHAL_UNMAP_USER_MEMORY:
++ gcmkVERIFY_OK(gckKERNEL_RemoveProcessDB(
++ Event->kernel,
++ Record->processID,
++ gcvDB_MAP_USER_MEMORY,
++ gcmINT2PTR(Record->info.u.UnmapUserMemory.info)));
++ break;
++
++ case gcvHAL_FREE_VIRTUAL_COMMAND_BUFFER:
++ gcmkVERIFY_OK(gckKERNEL_RemoveProcessDB(
++ Event->kernel,
++ Record->processID,
++ gcvDB_COMMAND_BUFFER,
++ gcmUINT64_TO_PTR(Record->info.u.FreeVirtualCommandBuffer.logical)));
++ break;
++
++ default:
++ break;
++ }
++
++ Record = Record->next;
++ }
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++void
++_SubmitTimerFunction(
++ gctPOINTER Data
++ )
++{
++ gckEVENT event = (gckEVENT)Data;
++ gcmkVERIFY_OK(gckEVENT_Submit(event, gcvTRUE, gcvFALSE));
++}
++
++/******************************************************************************\
++******************************* gckEVENT API Code *******************************
++\******************************************************************************/
++
++/*******************************************************************************
++**
++** gckEVENT_Construct
++**
++** Construct a new gckEVENT object.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** OUTPUT:
++**
++** gckEVENT * Event
++** Pointer to a variable that receives the gckEVENT object pointer.
++*/
++gceSTATUS
++gckEVENT_Construct(
++ IN gckKERNEL Kernel,
++ OUT gckEVENT * Event
++ )
++{
++ gckOS os;
++ gceSTATUS status;
++ gckEVENT eventObj = gcvNULL;
++ int i;
++ gcsEVENT_PTR record;
++ gctPOINTER pointer = gcvNULL;
++
++ gcmkHEADER_ARG("Kernel=0x%x", Kernel);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(Event != gcvNULL);
++
++ /* Extract the pointer to the gckOS object. */
++ os = Kernel->os;
++ gcmkVERIFY_OBJECT(os, gcvOBJ_OS);
++
++ /* Allocate the gckEVENT object. */
++ gcmkONERROR(gckOS_Allocate(os, gcmSIZEOF(struct _gckEVENT), &pointer));
++
++ eventObj = pointer;
++
++ /* Reset the object. */
++ gcmkVERIFY_OK(gckOS_ZeroMemory(eventObj, gcmSIZEOF(struct _gckEVENT)));
++
++ /* Initialize the gckEVENT object. */
++ eventObj->object.type = gcvOBJ_EVENT;
++ eventObj->kernel = Kernel;
++ eventObj->os = os;
++
++ /* Create the mutexes. */
++ gcmkONERROR(gckOS_CreateMutex(os, &eventObj->eventQueueMutex));
++ gcmkONERROR(gckOS_CreateMutex(os, &eventObj->freeEventMutex));
++ gcmkONERROR(gckOS_CreateMutex(os, &eventObj->eventListMutex));
++
++ /* Create a bunch of event reccords. */
++ for (i = 0; i < gcdEVENT_ALLOCATION_COUNT; i += 1)
++ {
++ /* Allocate an event record. */
++ gcmkONERROR(gckOS_Allocate(os, gcmSIZEOF(gcsEVENT), &pointer));
++
++ record = pointer;
++
++ /* Push it on the free list. */
++ record->next = eventObj->freeEventList;
++ eventObj->freeEventList = record;
++ eventObj->freeEventCount += 1;
++ }
++
++ /* Initialize the free list of event queues. */
++ for (i = 0; i < gcdREPO_LIST_COUNT; i += 1)
++ {
++ eventObj->repoList[i].next = eventObj->freeList;
++ eventObj->freeList = &eventObj->repoList[i];
++ }
++
++ /* Construct the atom. */
++ gcmkONERROR(gckOS_AtomConstruct(os, &eventObj->freeAtom));
++ gcmkONERROR(gckOS_AtomSet(os,
++ eventObj->freeAtom,
++ gcmCOUNTOF(eventObj->queues)));
++
++#if gcdSMP
++ gcmkONERROR(gckOS_AtomConstruct(os, &eventObj->pending));
++#endif
++
++ gcmkVERIFY_OK(gckOS_CreateTimer(os,
++ _SubmitTimerFunction,
++ (gctPOINTER)eventObj,
++ &eventObj->submitTimer));
++
++ /* Return pointer to the gckEVENT object. */
++ *Event = eventObj;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Event=0x%x", *Event);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Roll back. */
++ if (eventObj != gcvNULL)
++ {
++ if (eventObj->eventQueueMutex != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_DeleteMutex(os, eventObj->eventQueueMutex));
++ }
++
++ if (eventObj->freeEventMutex != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_DeleteMutex(os, eventObj->freeEventMutex));
++ }
++
++ if (eventObj->eventListMutex != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_DeleteMutex(os, eventObj->eventListMutex));
++ }
++
++ while (eventObj->freeEventList != gcvNULL)
++ {
++ record = eventObj->freeEventList;
++ eventObj->freeEventList = record->next;
++
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(os, record));
++ }
++
++ if (eventObj->freeAtom != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_AtomDestroy(os, eventObj->freeAtom));
++ }
++
++#if gcdSMP
++ if (eventObj->pending != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_AtomDestroy(os, eventObj->pending));
++ }
++#endif
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(os, eventObj));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckEVENT_Destroy
++**
++** Destroy an gckEVENT object.
++**
++** INPUT:
++**
++** gckEVENT Event
++** Pointer to an gckEVENT object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckEVENT_Destroy(
++ IN gckEVENT Event
++ )
++{
++ gcsEVENT_PTR record;
++ gcsEVENT_QUEUE_PTR queue;
++
++ gcmkHEADER_ARG("Event=0x%x", Event);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++
++ if (Event->submitTimer != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_StopTimer(Event->os, Event->submitTimer));
++ gcmkVERIFY_OK(gckOS_DestroyTimer(Event->os, Event->submitTimer));
++ }
++
++ /* Delete the queue mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Event->os, Event->eventQueueMutex));
++
++ /* Free all free events. */
++ while (Event->freeEventList != gcvNULL)
++ {
++ record = Event->freeEventList;
++ Event->freeEventList = record->next;
++
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Event->os, record));
++ }
++
++ /* Delete the free mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Event->os, Event->freeEventMutex));
++
++ /* Free all pending queues. */
++ while (Event->queueHead != gcvNULL)
++ {
++ /* Get the current queue. */
++ queue = Event->queueHead;
++
++ /* Free all pending events. */
++ while (queue->head != gcvNULL)
++ {
++ record = queue->head;
++ queue->head = record->next;
++
++ gcmkTRACE_ZONE_N(
++ gcvLEVEL_WARNING, gcvZONE_EVENT,
++ gcmSIZEOF(record) + gcmSIZEOF(queue->source),
++ "Event record 0x%x is still pending for %d.",
++ record, queue->source
++ );
++
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Event->os, record));
++ }
++
++ /* Remove the top queue from the list. */
++ if (Event->queueHead == Event->queueTail)
++ {
++ Event->queueHead =
++ Event->queueTail = gcvNULL;
++ }
++ else
++ {
++ Event->queueHead = Event->queueHead->next;
++ }
++
++ /* Free the queue. */
++ gcmkVERIFY_OK(gckEVENT_FreeQueue(Event, queue));
++ }
++
++ /* Delete the list mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Event->os, Event->eventListMutex));
++
++ /* Delete the atom. */
++ gcmkVERIFY_OK(gckOS_AtomDestroy(Event->os, Event->freeAtom));
++
++#if gcdSMP
++ gcmkVERIFY_OK(gckOS_AtomDestroy(Event->os, Event->pending));
++#endif
++
++ /* Mark the gckEVENT object as unknown. */
++ Event->object.type = gcvOBJ_UNKNOWN;
++
++ /* Free the gckEVENT object. */
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Event->os, Event));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckEVENT_GetEvent
++**
++** Reserve the next available hardware event.
++**
++** INPUT:
++**
++** gckEVENT Event
++** Pointer to an gckEVENT object.
++**
++** gctBOOL Wait
++** Set to gcvTRUE to force the function to wait if no events are
++** immediately available.
++**
++** gceKERNEL_WHERE Source
++** Source of the event.
++**
++** OUTPUT:
++**
++** gctUINT8 * EventID
++** Reserved event ID.
++*/
++static gceSTATUS
++gckEVENT_GetEvent(
++ IN gckEVENT Event,
++ IN gctBOOL Wait,
++ OUT gctUINT8 * EventID,
++ IN gcsEVENT_PTR Head,
++ IN gceKERNEL_WHERE Source
++ )
++{
++ gctINT i, id;
++ gceSTATUS status;
++ gctBOOL acquired = gcvFALSE;
++ gctINT32 free;
++
++#if gcdGPU_TIMEOUT
++ gctUINT32 timer = 0;
++#endif
++
++ gcmkHEADER_ARG("Event=0x%x Head=%p Source=%d", Event, Head, Source);
++
++ while (gcvTRUE)
++ {
++ /* Grab the queue mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(Event->os,
++ Event->eventQueueMutex,
++ gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Walk through all events. */
++ id = Event->lastID;
++ for (i = 0; i < gcmCOUNTOF(Event->queues); ++i)
++ {
++ gctINT nextID = gckMATH_ModuloInt((id + 1),
++ gcmCOUNTOF(Event->queues));
++
++ if (Event->queues[id].head == gcvNULL)
++ {
++ *EventID = (gctUINT8) id;
++
++ Event->lastID = (gctUINT8) nextID;
++
++ /* Save time stamp of event. */
++ Event->queues[id].stamp = ++(Event->stamp);
++ Event->queues[id].head = Head;
++ Event->queues[id].source = Source;
++
++ gcmkONERROR(gckOS_AtomDecrement(Event->os,
++ Event->freeAtom,
++ &free));
++#if gcdDYNAMIC_SPEED
++ if (free <= gcdDYNAMIC_EVENT_THRESHOLD)
++ {
++ gcmkONERROR(gckOS_BroadcastHurry(
++ Event->os,
++ Event->kernel->hardware,
++ gcdDYNAMIC_EVENT_THRESHOLD - free));
++ }
++#endif
++
++ /* Release the queue mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Event->os,
++ Event->eventQueueMutex));
++
++ /* Success. */
++ gcmkTRACE_ZONE_N(
++ gcvLEVEL_INFO, gcvZONE_EVENT,
++ gcmSIZEOF(id),
++ "Using id=%d",
++ id
++ );
++
++ gcmkFOOTER_ARG("*EventID=%u", *EventID);
++ return gcvSTATUS_OK;
++ }
++
++ id = nextID;
++ }
++
++#if gcdDYNAMIC_SPEED
++ /* No free events, speed up the GPU right now! */
++ gcmkONERROR(gckOS_BroadcastHurry(Event->os,
++ Event->kernel->hardware,
++ gcdDYNAMIC_EVENT_THRESHOLD));
++#endif
++
++ /* Release the queue mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Event->os, Event->eventQueueMutex));
++ acquired = gcvFALSE;
++
++ /* Fail if wait is not requested. */
++ if (!Wait)
++ {
++ /* Out of resources. */
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++ /* Delay a while. */
++ gcmkONERROR(gckOS_Delay(Event->os, 1));
++
++#if gcdGPU_TIMEOUT
++ /* Increment the wait timer. */
++ timer += 1;
++
++ if (timer == Event->kernel->timeOut)
++ {
++ /* Try to call any outstanding events. */
++ gcmkONERROR(gckHARDWARE_Interrupt(Event->kernel->hardware,
++ gcvTRUE));
++ }
++ else if (timer > Event->kernel->timeOut)
++ {
++ gcmkTRACE_N(
++ gcvLEVEL_ERROR,
++ gcmSIZEOF(gctCONST_STRING) + gcmSIZEOF(gctINT),
++ "%s(%d): no available events\n",
++ __FUNCTION__, __LINE__
++ );
++
++ /* Bail out. */
++ gcmkONERROR(gcvSTATUS_GPU_NOT_RESPONDING);
++ }
++#endif
++ }
++
++OnError:
++ if (acquired)
++ {
++ /* Release the queue mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Event->os, Event->eventQueueMutex));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckEVENT_AllocateRecord
++**
++** Allocate a record for the new event.
++**
++** INPUT:
++**
++** gckEVENT Event
++** Pointer to an gckEVENT object.
++**
++** gctBOOL AllocateAllowed
++** State for allocation if out of free events.
++**
++** OUTPUT:
++**
++** gcsEVENT_PTR * Record
++** Allocated event record.
++*/
++gceSTATUS
++gckEVENT_AllocateRecord(
++ IN gckEVENT Event,
++ IN gctBOOL AllocateAllowed,
++ OUT gcsEVENT_PTR * Record
++ )
++{
++ gceSTATUS status;
++ gctBOOL acquired = gcvFALSE;
++ gctINT i;
++ gcsEVENT_PTR record;
++ gctPOINTER pointer = gcvNULL;
++
++ gcmkHEADER_ARG("Event=0x%x AllocateAllowed=%d", Event, AllocateAllowed);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++ gcmkVERIFY_ARGUMENT(Record != gcvNULL);
++
++ /* Acquire the mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(Event->os, Event->freeEventMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Test if we are below the allocation threshold. */
++ if ( (AllocateAllowed && (Event->freeEventCount < gcdEVENT_MIN_THRESHOLD)) ||
++ (Event->freeEventCount == 0) )
++ {
++ /* Allocate a bunch of records. */
++ for (i = 0; i < gcdEVENT_ALLOCATION_COUNT; i += 1)
++ {
++ /* Allocate an event record. */
++ gcmkONERROR(gckOS_Allocate(Event->os,
++ gcmSIZEOF(gcsEVENT),
++ &pointer));
++
++ record = pointer;
++
++ /* Push it on the free list. */
++ record->next = Event->freeEventList;
++ Event->freeEventList = record;
++ Event->freeEventCount += 1;
++ }
++ }
++
++ *Record = Event->freeEventList;
++ Event->freeEventList = Event->freeEventList->next;
++ Event->freeEventCount -= 1;
++
++ /* Release the mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Event->os, Event->freeEventMutex));
++ acquired = gcvFALSE;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Record=0x%x", gcmOPT_POINTER(Record));
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Roll back. */
++ if (acquired)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Event->os, Event->freeEventMutex));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckEVENT_AddList
++**
++** Add a new event to the list of events.
++**
++** INPUT:
++**
++** gckEVENT Event
++** Pointer to an gckEVENT object.
++**
++** gcsHAL_INTERFACE_PTR Interface
++** Pointer to the interface for the event to be added.
++**
++** gceKERNEL_WHERE FromWhere
++** Place in the pipe where the event needs to be generated.
++**
++** gctBOOL AllocateAllowed
++** State for allocation if out of free events.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckEVENT_AddList(
++ IN gckEVENT Event,
++ IN gcsHAL_INTERFACE_PTR Interface,
++ IN gceKERNEL_WHERE FromWhere,
++ IN gctBOOL AllocateAllowed,
++ IN gctBOOL FromKernel
++ )
++{
++ gceSTATUS status;
++ gctBOOL acquired = gcvFALSE;
++ gcsEVENT_PTR record = gcvNULL;
++ gcsEVENT_QUEUE_PTR queue;
++ gckKERNEL kernel = Event->kernel;
++
++ gcmkHEADER_ARG("Event=0x%x Interface=0x%x",
++ Event, Interface);
++
++ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, _GC_OBJ_ZONE,
++ "FromWhere=%d AllocateAllowed=%d",
++ FromWhere, AllocateAllowed);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++ gcmkVERIFY_ARGUMENT(Interface != gcvNULL);
++
++ /* Verify the event command. */
++ gcmkASSERT
++ ( (Interface->command == gcvHAL_FREE_NON_PAGED_MEMORY)
++ || (Interface->command == gcvHAL_FREE_CONTIGUOUS_MEMORY)
++ || (Interface->command == gcvHAL_FREE_VIDEO_MEMORY)
++ || (Interface->command == gcvHAL_WRITE_DATA)
++ || (Interface->command == gcvHAL_UNLOCK_VIDEO_MEMORY)
++ || (Interface->command == gcvHAL_SIGNAL)
++ || (Interface->command == gcvHAL_UNMAP_USER_MEMORY)
++ || (Interface->command == gcvHAL_TIMESTAMP)
++ || (Interface->command == gcvHAL_COMMIT_DONE)
++ || (Interface->command == gcvHAL_FREE_VIRTUAL_COMMAND_BUFFER)
++ || (Interface->command == gcvHAL_SYNC_POINT)
++ );
++
++ /* Validate the source. */
++ if ((FromWhere != gcvKERNEL_COMMAND) && (FromWhere != gcvKERNEL_PIXEL))
++ {
++ /* Invalid argument. */
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ /* Allocate a free record. */
++ gcmkONERROR(gckEVENT_AllocateRecord(Event, AllocateAllowed, &record));
++
++ /* Termninate the record. */
++ record->next = gcvNULL;
++
++ /* Record the committer. */
++ record->fromKernel = FromKernel;
++
++ /* Copy the event interface into the record. */
++ gckOS_MemCopy(&record->info, Interface, gcmSIZEOF(record->info));
++
++ /* Get process ID. */
++ gcmkONERROR(gckOS_GetProcessID(&record->processID));
++
++#ifdef __QNXNTO__
++ record->kernel = Event->kernel;
++#endif
++
++ gcmkONERROR(__RemoveRecordFromProcessDB(Event, record));
++
++ /* Acquire the mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(Event->os, Event->eventListMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Do we need to allocate a new queue? */
++ if ((Event->queueTail == gcvNULL) || (Event->queueTail->source < FromWhere))
++ {
++ /* Allocate a new queue. */
++ gcmkONERROR(gckEVENT_AllocateQueue(Event, &queue));
++
++ /* Initialize the queue. */
++ queue->source = FromWhere;
++ queue->head = gcvNULL;
++ queue->next = gcvNULL;
++
++ /* Attach it to the list of allocated queues. */
++ if (Event->queueTail == gcvNULL)
++ {
++ Event->queueHead =
++ Event->queueTail = queue;
++ }
++ else
++ {
++ Event->queueTail->next = queue;
++ Event->queueTail = queue;
++ }
++ }
++ else
++ {
++ queue = Event->queueTail;
++ }
++
++ /* Attach the record to the queue. */
++ if (queue->head == gcvNULL)
++ {
++ queue->head = record;
++ queue->tail = record;
++ }
++ else
++ {
++ queue->tail->next = record;
++ queue->tail = record;
++ }
++
++ /* Unmap user space logical address.
++ * Linux kernel does not support unmap the memory of other process any more since 3.5.
++ * Let's unmap memory of self process before submit the event to gpu.
++ * */
++ switch(Interface->command)
++ {
++ case gcvHAL_FREE_NON_PAGED_MEMORY:
++ gcmkONERROR(gckOS_UnmapUserLogical(
++ Event->os,
++ gcmNAME_TO_PTR(Interface->u.FreeNonPagedMemory.physical),
++ (gctSIZE_T) Interface->u.FreeNonPagedMemory.bytes,
++ gcmUINT64_TO_PTR(Interface->u.FreeNonPagedMemory.logical)));
++ break;
++ case gcvHAL_FREE_CONTIGUOUS_MEMORY:
++ gcmkONERROR(gckOS_UnmapUserLogical(
++ Event->os,
++ gcmNAME_TO_PTR(Interface->u.FreeContiguousMemory.physical),
++ (gctSIZE_T) Interface->u.FreeContiguousMemory.bytes,
++ gcmUINT64_TO_PTR(Interface->u.FreeContiguousMemory.logical)));
++ break;
++ default:
++ break;
++ }
++
++
++ /* Release the mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Event->os, Event->eventListMutex));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Roll back. */
++ if (acquired)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Event->os, Event->eventListMutex));
++ }
++
++ if (record != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckEVENT_FreeRecord(Event, record));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckEVENT_Unlock
++**
++** Schedule an event to unlock virtual memory.
++**
++** INPUT:
++**
++** gckEVENT Event
++** Pointer to an gckEVENT object.
++**
++** gceKERNEL_WHERE FromWhere
++** Place in the pipe where the event needs to be generated.
++**
++** gcuVIDMEM_NODE_PTR Node
++** Pointer to a gcuVIDMEM_NODE union that specifies the virtual memory
++** to unlock.
++**
++** gceSURF_TYPE Type
++** Type of surface to unlock.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckEVENT_Unlock(
++ IN gckEVENT Event,
++ IN gceKERNEL_WHERE FromWhere,
++ IN gcuVIDMEM_NODE_PTR Node,
++ IN gceSURF_TYPE Type
++ )
++{
++ gceSTATUS status;
++ gcsHAL_INTERFACE iface;
++
++ gcmkHEADER_ARG("Event=0x%x FromWhere=%d Node=0x%x Type=%d",
++ Event, FromWhere, Node, Type);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++ gcmkVERIFY_ARGUMENT(Node != gcvNULL);
++
++ /* Mark the event as an unlock. */
++ iface.command = gcvHAL_UNLOCK_VIDEO_MEMORY;
++ iface.u.UnlockVideoMemory.node = gcmPTR_TO_UINT64(Node);
++ iface.u.UnlockVideoMemory.type = Type;
++ iface.u.UnlockVideoMemory.asynchroneous = 0;
++
++ /* Append it to the queue. */
++ gcmkONERROR(gckEVENT_AddList(Event, &iface, FromWhere, gcvFALSE, gcvTRUE));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckEVENT_FreeVideoMemory
++**
++** Schedule an event to free video memory.
++**
++** INPUT:
++**
++** gckEVENT Event
++** Pointer to an gckEVENT object.
++**
++** gcuVIDMEM_NODE_PTR VideoMemory
++** Pointer to a gcuVIDMEM_NODE object to free.
++**
++** gceKERNEL_WHERE FromWhere
++** Place in the pipe where the event needs to be generated.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckEVENT_FreeVideoMemory(
++ IN gckEVENT Event,
++ IN gcuVIDMEM_NODE_PTR VideoMemory,
++ IN gceKERNEL_WHERE FromWhere
++ )
++{
++ gceSTATUS status;
++ gcsHAL_INTERFACE iface;
++
++ gcmkHEADER_ARG("Event=0x%x VideoMemory=0x%x FromWhere=%d",
++ Event, VideoMemory, FromWhere);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++ gcmkVERIFY_ARGUMENT(VideoMemory != gcvNULL);
++
++ /* Create an event. */
++ iface.command = gcvHAL_FREE_VIDEO_MEMORY;
++ iface.u.FreeVideoMemory.node = gcmPTR_TO_UINT64(VideoMemory);
++
++ /* Append it to the queue. */
++ gcmkONERROR(gckEVENT_AddList(Event, &iface, FromWhere, gcvFALSE, gcvTRUE));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckEVENT_FreeNonPagedMemory
++**
++** Schedule an event to free non-paged memory.
++**
++** INPUT:
++**
++** gckEVENT Event
++** Pointer to an gckEVENT object.
++**
++** gctSIZE_T Bytes
++** Number of bytes of non-paged memory to free.
++**
++** gctPHYS_ADDR Physical
++** Physical address of non-paged memory to free.
++**
++** gctPOINTER Logical
++** Logical address of non-paged memory to free.
++**
++** gceKERNEL_WHERE FromWhere
++** Place in the pipe where the event needs to be generated.
++*/
++gceSTATUS
++gckEVENT_FreeNonPagedMemory(
++ IN gckEVENT Event,
++ IN gctSIZE_T Bytes,
++ IN gctPHYS_ADDR Physical,
++ IN gctPOINTER Logical,
++ IN gceKERNEL_WHERE FromWhere
++ )
++{
++ gceSTATUS status;
++ gcsHAL_INTERFACE iface;
++ gckKERNEL kernel = Event->kernel;
++
++ gcmkHEADER_ARG("Event=0x%x Bytes=%lu Physical=0x%x Logical=0x%x "
++ "FromWhere=%d",
++ Event, Bytes, Physical, Logical, FromWhere);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++ gcmkVERIFY_ARGUMENT(Physical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++
++ /* Create an event. */
++ iface.command = gcvHAL_FREE_NON_PAGED_MEMORY;
++ iface.u.FreeNonPagedMemory.bytes = Bytes;
++ iface.u.FreeNonPagedMemory.physical = gcmPTR_TO_NAME(Physical);
++ iface.u.FreeNonPagedMemory.logical = gcmPTR_TO_UINT64(Logical);
++
++ /* Append it to the queue. */
++ gcmkONERROR(gckEVENT_AddList(Event, &iface, FromWhere, gcvFALSE, gcvTRUE));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckEVENT_DestroyVirtualCommandBuffer(
++ IN gckEVENT Event,
++ IN gctSIZE_T Bytes,
++ IN gctPHYS_ADDR Physical,
++ IN gctPOINTER Logical,
++ IN gceKERNEL_WHERE FromWhere
++ )
++{
++ gceSTATUS status;
++ gcsHAL_INTERFACE iface;
++ gckKERNEL kernel = Event->kernel;
++
++ gcmkHEADER_ARG("Event=0x%x Bytes=%lu Physical=0x%x Logical=0x%x "
++ "FromWhere=%d",
++ Event, Bytes, Physical, Logical, FromWhere);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++ gcmkVERIFY_ARGUMENT(Physical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++
++ /* Create an event. */
++ iface.command = gcvHAL_FREE_VIRTUAL_COMMAND_BUFFER;
++ iface.u.FreeVirtualCommandBuffer.bytes = Bytes;
++ iface.u.FreeVirtualCommandBuffer.physical = gcmPTR_TO_NAME(Physical);
++ iface.u.FreeVirtualCommandBuffer.logical = gcmPTR_TO_UINT64(Logical);
++
++ /* Append it to the queue. */
++ gcmkONERROR(gckEVENT_AddList(Event, &iface, FromWhere, gcvFALSE, gcvTRUE));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckEVENT_FreeContigiuousMemory
++**
++** Schedule an event to free contiguous memory.
++**
++** INPUT:
++**
++** gckEVENT Event
++** Pointer to an gckEVENT object.
++**
++** gctSIZE_T Bytes
++** Number of bytes of contiguous memory to free.
++**
++** gctPHYS_ADDR Physical
++** Physical address of contiguous memory to free.
++**
++** gctPOINTER Logical
++** Logical address of contiguous memory to free.
++**
++** gceKERNEL_WHERE FromWhere
++** Place in the pipe where the event needs to be generated.
++*/
++gceSTATUS
++gckEVENT_FreeContiguousMemory(
++ IN gckEVENT Event,
++ IN gctSIZE_T Bytes,
++ IN gctPHYS_ADDR Physical,
++ IN gctPOINTER Logical,
++ IN gceKERNEL_WHERE FromWhere
++ )
++{
++ gceSTATUS status;
++ gcsHAL_INTERFACE iface;
++ gckKERNEL kernel = Event->kernel;
++
++ gcmkHEADER_ARG("Event=0x%x Bytes=%lu Physical=0x%x Logical=0x%x "
++ "FromWhere=%d",
++ Event, Bytes, Physical, Logical, FromWhere);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++ gcmkVERIFY_ARGUMENT(Physical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++
++ /* Create an event. */
++ iface.command = gcvHAL_FREE_CONTIGUOUS_MEMORY;
++ iface.u.FreeContiguousMemory.bytes = Bytes;
++ iface.u.FreeContiguousMemory.physical = gcmPTR_TO_NAME(Physical);
++ iface.u.FreeContiguousMemory.logical = gcmPTR_TO_UINT64(Logical);
++
++ /* Append it to the queue. */
++ gcmkONERROR(gckEVENT_AddList(Event, &iface, FromWhere, gcvFALSE, gcvTRUE));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckEVENT_Signal
++**
++** Schedule an event to trigger a signal.
++**
++** INPUT:
++**
++** gckEVENT Event
++** Pointer to an gckEVENT object.
++**
++** gctSIGNAL Signal
++** Pointer to the signal to trigger.
++**
++** gceKERNEL_WHERE FromWhere
++** Place in the pipe where the event needs to be generated.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckEVENT_Signal(
++ IN gckEVENT Event,
++ IN gctSIGNAL Signal,
++ IN gceKERNEL_WHERE FromWhere
++ )
++{
++ gceSTATUS status;
++ gcsHAL_INTERFACE iface;
++
++ gcmkHEADER_ARG("Event=0x%x Signal=0x%x FromWhere=%d",
++ Event, Signal, FromWhere);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++ gcmkVERIFY_ARGUMENT(Signal != gcvNULL);
++
++ /* Mark the event as a signal. */
++ iface.command = gcvHAL_SIGNAL;
++ iface.u.Signal.signal = gcmPTR_TO_UINT64(Signal);
++#ifdef __QNXNTO__
++ iface.u.Signal.coid = 0;
++ iface.u.Signal.rcvid = 0;
++#endif
++ iface.u.Signal.auxSignal = 0;
++ iface.u.Signal.process = 0;
++
++ /* Append it to the queue. */
++ gcmkONERROR(gckEVENT_AddList(Event, &iface, FromWhere, gcvFALSE, gcvTRUE));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckEVENT_CommitDone
++**
++** Schedule an event to wake up work thread when commit is done by GPU.
++**
++** INPUT:
++**
++** gckEVENT Event
++** Pointer to an gckEVENT object.
++**
++** gceKERNEL_WHERE FromWhere
++** Place in the pipe where the event needs to be generated.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckEVENT_CommitDone(
++ IN gckEVENT Event,
++ IN gceKERNEL_WHERE FromWhere
++ )
++{
++ gceSTATUS status;
++ gcsHAL_INTERFACE iface;
++
++ gcmkHEADER_ARG("Event=0x%x FromWhere=%d", Event, FromWhere);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++
++ iface.command = gcvHAL_COMMIT_DONE;
++
++ /* Append it to the queue. */
++ gcmkONERROR(gckEVENT_AddList(Event, &iface, FromWhere, gcvFALSE, gcvTRUE));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++/*******************************************************************************
++**
++** gckEVENT_Submit
++**
++** Submit the current event queue to the GPU.
++**
++** INPUT:
++**
++** gckEVENT Event
++** Pointer to an gckEVENT object.
++**
++** gctBOOL Wait
++** Submit requires one vacant event; if Wait is set to not zero,
++** and there are no vacant events at this time, the function will
++** wait until an event becomes vacant so that submission of the
++** queue is successful.
++**
++** gctBOOL FromPower
++** Determines whether the call originates from inside the power
++** management or not.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckEVENT_Submit(
++ IN gckEVENT Event,
++ IN gctBOOL Wait,
++ IN gctBOOL FromPower
++ )
++{
++ gceSTATUS status;
++ gctUINT8 id = 0xFF;
++ gcsEVENT_QUEUE_PTR queue;
++ gctBOOL acquired = gcvFALSE;
++ gckCOMMAND command = gcvNULL;
++ gctBOOL commitEntered = gcvFALSE;
++#if !gcdNULL_DRIVER
++ gctSIZE_T bytes;
++ gctPOINTER buffer;
++#endif
++
++ gcmkHEADER_ARG("Event=0x%x Wait=%d", Event, Wait);
++
++ /* Get gckCOMMAND object. */
++ command = Event->kernel->command;
++
++ /* Are there event queues? */
++ if (Event->queueHead != gcvNULL)
++ {
++ /* Acquire the command queue. */
++ gcmkONERROR(gckCOMMAND_EnterCommit(command, FromPower));
++ commitEntered = gcvTRUE;
++
++ /* Process all queues. */
++ while (Event->queueHead != gcvNULL)
++ {
++ /* Acquire the list mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(Event->os,
++ Event->eventListMutex,
++ gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Get the current queue. */
++ queue = Event->queueHead;
++
++ /* Allocate an event ID. */
++ gcmkONERROR(gckEVENT_GetEvent(Event, Wait, &id, queue->head, queue->source));
++
++ /* Copy event list to event ID queue. */
++ Event->queues[id].head = queue->head;
++
++ /* Remove the top queue from the list. */
++ if (Event->queueHead == Event->queueTail)
++ {
++ Event->queueHead = gcvNULL;
++ Event->queueTail = gcvNULL;
++ }
++ else
++ {
++ Event->queueHead = Event->queueHead->next;
++ }
++
++ /* Free the queue. */
++ gcmkONERROR(gckEVENT_FreeQueue(Event, queue));
++
++ /* Release the list mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Event->os, Event->eventListMutex));
++ acquired = gcvFALSE;
++
++#if gcdNULL_DRIVER
++ /* Notify immediately on infinite hardware. */
++ gcmkONERROR(gckEVENT_Interrupt(Event, 1 << id));
++
++ gcmkONERROR(gckEVENT_Notify(Event, 0));
++#else
++ /* Get the size of the hardware event. */
++ gcmkONERROR(gckHARDWARE_Event(Event->kernel->hardware,
++ gcvNULL,
++ id,
++ Event->queues[id].source,
++ &bytes));
++
++ /* Reserve space in the command queue. */
++ gcmkONERROR(gckCOMMAND_Reserve(command,
++ bytes,
++ &buffer,
++ &bytes));
++
++ /* Set the hardware event in the command queue. */
++ gcmkONERROR(gckHARDWARE_Event(Event->kernel->hardware,
++ buffer,
++ id,
++ Event->queues[id].source,
++ &bytes));
++
++ /* Execute the hardware event. */
++ gcmkONERROR(gckCOMMAND_Execute(command, bytes));
++#endif
++ }
++
++ /* Release the command queue. */
++ gcmkONERROR(gckCOMMAND_ExitCommit(command, FromPower));
++ commitEntered = gcvFALSE;
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (commitEntered)
++ {
++ /* Release the command queue mutex. */
++ gcmkVERIFY_OK(gckCOMMAND_ExitCommit(command, FromPower));
++ }
++
++ if (acquired)
++ {
++ /* Need to unroll the mutex acquire. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Event->os, Event->eventListMutex));
++ }
++
++ if (id != 0xFF)
++ {
++ /* Need to unroll the event allocation. */
++ Event->queues[id].head = gcvNULL;
++ }
++
++ if (status == gcvSTATUS_GPU_NOT_RESPONDING)
++ {
++ /* Broadcast GPU stuck. */
++ status = gckOS_Broadcast(Event->os,
++ Event->kernel->hardware,
++ gcvBROADCAST_GPU_STUCK);
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckEVENT_Commit
++**
++** Commit an event queue from the user.
++**
++** INPUT:
++**
++** gckEVENT Event
++** Pointer to an gckEVENT object.
++**
++** gcsQUEUE_PTR Queue
++** User event queue.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckEVENT_Commit(
++ IN gckEVENT Event,
++ IN gcsQUEUE_PTR Queue
++ )
++{
++ gceSTATUS status;
++ gcsQUEUE_PTR record = gcvNULL, next;
++ gctUINT32 processID;
++ gctBOOL needCopy = gcvFALSE;
++
++ gcmkHEADER_ARG("Event=0x%x Queue=0x%x", Event, Queue);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++
++ /* Get the current process ID. */
++ gcmkONERROR(gckOS_GetProcessID(&processID));
++
++ /* Query if we need to copy the client data. */
++ gcmkONERROR(gckOS_QueryNeedCopy(Event->os, processID, &needCopy));
++
++ /* Loop while there are records in the queue. */
++ while (Queue != gcvNULL)
++ {
++ gcsQUEUE queue;
++
++ if (needCopy)
++ {
++ /* Point to stack record. */
++ record = &queue;
++
++ /* Copy the data from the client. */
++ gcmkONERROR(gckOS_CopyFromUserData(Event->os,
++ record,
++ Queue,
++ gcmSIZEOF(gcsQUEUE)));
++ }
++ else
++ {
++ gctPOINTER pointer = gcvNULL;
++
++ /* Map record into kernel memory. */
++ gcmkONERROR(gckOS_MapUserPointer(Event->os,
++ Queue,
++ gcmSIZEOF(gcsQUEUE),
++ &pointer));
++
++ record = pointer;
++ }
++
++ /* Append event record to event queue. */
++ gcmkONERROR(
++ gckEVENT_AddList(Event, &record->iface, gcvKERNEL_PIXEL, gcvTRUE, gcvFALSE));
++
++ /* Next record in the queue. */
++ next = gcmUINT64_TO_PTR(record->next);
++
++ if (!needCopy)
++ {
++ /* Unmap record from kernel memory. */
++ gcmkONERROR(
++ gckOS_UnmapUserPointer(Event->os,
++ Queue,
++ gcmSIZEOF(gcsQUEUE),
++ (gctPOINTER *) record));
++ record = gcvNULL;
++ }
++
++ Queue = next;
++ }
++
++ /* Submit the event list. */
++ gcmkONERROR(gckEVENT_Submit(Event, gcvTRUE, gcvFALSE));
++
++ /* Success */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if ((record != gcvNULL) && !needCopy)
++ {
++ /* Roll back. */
++ gcmkVERIFY_OK(gckOS_UnmapUserPointer(Event->os,
++ Queue,
++ gcmSIZEOF(gcsQUEUE),
++ (gctPOINTER *) record));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckEVENT_Compose
++**
++** Schedule a composition event and start a composition.
++**
++** INPUT:
++**
++** gckEVENT Event
++** Pointer to an gckEVENT object.
++**
++** gcsHAL_COMPOSE_PTR Info
++** Pointer to the composition structure.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckEVENT_Compose(
++ IN gckEVENT Event,
++ IN gcsHAL_COMPOSE_PTR Info
++ )
++{
++ gceSTATUS status;
++ gcsEVENT_PTR headRecord;
++ gcsEVENT_PTR tailRecord;
++ gcsEVENT_PTR tempRecord;
++ gctUINT8 id = 0xFF;
++ gctUINT32 processID;
++
++ gcmkHEADER_ARG("Event=0x%x Info=0x%x", Event, Info);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++ gcmkVERIFY_ARGUMENT(Info != gcvNULL);
++
++ /* Get process ID. */
++ gcmkONERROR(gckOS_GetProcessID(&processID));
++
++ /* Allocate a record. */
++ gcmkONERROR(gckEVENT_AllocateRecord(Event, gcvTRUE, &tempRecord));
++ headRecord = tailRecord = tempRecord;
++
++ /* Initialize the record. */
++ tempRecord->info.command = gcvHAL_SIGNAL;
++ tempRecord->info.u.Signal.process = Info->process;
++#ifdef __QNXNTO__
++ tempRecord->info.u.Signal.coid = Info->coid;
++ tempRecord->info.u.Signal.rcvid = Info->rcvid;
++#endif
++ tempRecord->info.u.Signal.signal = Info->signal;
++ tempRecord->info.u.Signal.auxSignal = 0;
++ tempRecord->next = gcvNULL;
++ tempRecord->processID = processID;
++
++ /* Allocate another record for user signal #1. */
++ if (gcmUINT64_TO_PTR(Info->userSignal1) != gcvNULL)
++ {
++ /* Allocate a record. */
++ gcmkONERROR(gckEVENT_AllocateRecord(Event, gcvTRUE, &tempRecord));
++ tailRecord->next = tempRecord;
++ tailRecord = tempRecord;
++
++ /* Initialize the record. */
++ tempRecord->info.command = gcvHAL_SIGNAL;
++ tempRecord->info.u.Signal.process = Info->userProcess;
++#ifdef __QNXNTO__
++ tempRecord->info.u.Signal.coid = Info->coid;
++ tempRecord->info.u.Signal.rcvid = Info->rcvid;
++#endif
++ tempRecord->info.u.Signal.signal = Info->userSignal1;
++ tempRecord->info.u.Signal.auxSignal = 0;
++ tempRecord->next = gcvNULL;
++ tempRecord->processID = processID;
++ }
++
++ /* Allocate another record for user signal #2. */
++ if (gcmUINT64_TO_PTR(Info->userSignal2) != gcvNULL)
++ {
++ /* Allocate a record. */
++ gcmkONERROR(gckEVENT_AllocateRecord(Event, gcvTRUE, &tempRecord));
++ tailRecord->next = tempRecord;
++ tailRecord = tempRecord;
++
++ /* Initialize the record. */
++ tempRecord->info.command = gcvHAL_SIGNAL;
++ tempRecord->info.u.Signal.process = Info->userProcess;
++#ifdef __QNXNTO__
++ tempRecord->info.u.Signal.coid = Info->coid;
++ tempRecord->info.u.Signal.rcvid = Info->rcvid;
++#endif
++ tempRecord->info.u.Signal.signal = Info->userSignal2;
++ tempRecord->info.u.Signal.auxSignal = 0;
++ tempRecord->next = gcvNULL;
++ tempRecord->processID = processID;
++ }
++
++ /* Allocate an event ID. */
++ gcmkONERROR(gckEVENT_GetEvent(Event, gcvTRUE, &id, headRecord, gcvKERNEL_PIXEL));
++
++ /* Start composition. */
++ gcmkONERROR(gckHARDWARE_Compose(
++ Event->kernel->hardware, processID,
++ gcmUINT64_TO_PTR(Info->physical), gcmUINT64_TO_PTR(Info->logical), Info->offset, Info->size, id
++ ));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckEVENT_Interrupt
++**
++** Called by the interrupt service routine to store the triggered interrupt
++** mask to be later processed by gckEVENT_Notify.
++**
++** INPUT:
++**
++** gckEVENT Event
++** Pointer to an gckEVENT object.
++**
++** gctUINT32 Data
++** Mask for the 32 interrupts.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckEVENT_Interrupt(
++ IN gckEVENT Event,
++ IN gctUINT32 Data
++ )
++{
++ unsigned long flags;
++ gcmkHEADER_ARG("Event=0x%x Data=0x%x", Event, Data);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++
++ /* Combine current interrupt status with pending flags. */
++ spin_lock_irqsave(&Event->kernel->irq_lock, flags);
++#if gcdSMP
++ gckOS_AtomSetMask(Event->pending, Data);
++#elif defined(__QNXNTO__)
++ atomic_set(&Event->pending, Data);
++#else
++ Event->pending |= Data;
++#endif
++ spin_unlock_irqrestore(&Event->kernel->irq_lock, flags);
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckEVENT_Notify
++**
++** Process all triggered interrupts.
++**
++** INPUT:
++**
++** gckEVENT Event
++** Pointer to an gckEVENT object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckEVENT_Notify(
++ IN gckEVENT Event,
++ IN gctUINT32 IDs
++ )
++{
++ gceSTATUS status = gcvSTATUS_OK;
++ gctINT i;
++ gcsEVENT_QUEUE * queue;
++ gctUINT mask = 0;
++ gctBOOL acquired = gcvFALSE;
++ gcuVIDMEM_NODE_PTR node;
++ gctPOINTER info;
++ gctSIGNAL signal;
++ gctUINT pending;
++ gckKERNEL kernel = Event->kernel;
++#if !gcdSMP
++ gctBOOL suspended = gcvFALSE;
++#endif
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++ gctINT eventNumber = 0;
++#endif
++ gctINT32 free;
++#if gcdSECURE_USER
++ gcskSECURE_CACHE_PTR cache;
++#endif
++ unsigned long flags;
++
++ gcmkHEADER_ARG("Event=0x%x IDs=0x%x", Event, IDs);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++
++ gcmDEBUG_ONLY(
++ if (IDs != 0)
++ {
++ for (i = 0; i < gcmCOUNTOF(Event->queues); ++i)
++ {
++ if (Event->queues[i].head != gcvNULL)
++ {
++ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_EVENT,
++ "Queue(%d): stamp=%llu source=%d",
++ i,
++ Event->queues[i].stamp,
++ Event->queues[i].source);
++ }
++ }
++ }
++ );
++
++ for (;;)
++ {
++ gcsEVENT_PTR record;
++
++ spin_lock_irqsave(&Event->kernel->irq_lock, flags);
++#if gcdSMP
++ /* Get current interrupts. */
++ gckOS_AtomGet(Event->os, Event->pending, (gctINT32_PTR)&pending);
++#else
++ /* Get current interrupts. */
++ pending = Event->pending;
++#endif
++ spin_unlock_irqrestore(&Event->kernel->irq_lock, flags);
++
++ if (pending & 0x80000000)
++ {
++ //gckOS_Print("!!!!!!!!!!!!! AXI BUS ERROR !!!!!!!!!!!!!\n");
++ gcmkTRACE_ZONE(gcvLEVEL_ERROR, gcvZONE_EVENT, "AXI BUS ERROR");
++ pending &= 0x7FFFFFFF;
++ }
++
++ if (pending & 0x40000000)
++ {
++ gckHARDWARE_DumpMMUException(Event->kernel->hardware);
++
++ pending &= 0x3FFFFFFF;
++ }
++
++ gcmkTRACE_ZONE_N(
++ gcvLEVEL_INFO, gcvZONE_EVENT,
++ gcmSIZEOF(pending),
++ "Pending interrupts 0x%x",
++ pending
++ );
++
++ if (pending == 0)
++ {
++ /* No more pending interrupts - done. */
++ break;
++ }
++
++ queue = gcvNULL;
++
++ /* Grab the mutex queue. */
++ gcmkONERROR(gckOS_AcquireMutex(Event->os,
++ Event->eventQueueMutex,
++ gcvINFINITE));
++ acquired = gcvTRUE;
++
++ gcmDEBUG_ONLY(
++ if (IDs == 0)
++ {
++ for (i = 0; i < gcmCOUNTOF(Event->queues); ++i)
++ {
++ if (Event->queues[i].head != gcvNULL)
++ {
++ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_EVENT,
++ "Queue(%d): stamp=%llu source=%d",
++ i,
++ Event->queues[i].stamp,
++ Event->queues[i].source);
++ }
++ }
++ }
++ );
++
++ /* Find the oldest pending interrupt. */
++ for (i = 0; i < gcmCOUNTOF(Event->queues); ++i)
++ {
++ if ((Event->queues[i].head != gcvNULL)
++ && (pending & (1 << i))
++ )
++ {
++ if ((queue == gcvNULL)
++ || (Event->queues[i].stamp < queue->stamp)
++ )
++ {
++ queue = &Event->queues[i];
++ mask = 1 << i;
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++ eventNumber = i;
++#endif
++ }
++ }
++ }
++
++ if (queue == gcvNULL)
++ {
++ gcmkTRACE_ZONE_N(
++ gcvLEVEL_ERROR, gcvZONE_EVENT,
++ gcmSIZEOF(pending),
++ "Interrupts 0x%x are not pending.",
++ pending
++ );
++
++ /* Release the mutex queue. */
++ gcmkONERROR(gckOS_ReleaseMutex(Event->os, Event->eventQueueMutex));
++ acquired = gcvFALSE;
++
++ spin_lock_irqsave(&Event->kernel->irq_lock, flags);
++#if gcdSMP
++ /* Mark pending interrupts as handled. */
++ gckOS_AtomClearMask(Event->pending, pending);
++#elif defined(__QNXNTO__)
++ /* Mark pending interrupts as handled. */
++ atomic_clr((gctUINT32_PTR)&Event->pending, pending);
++#else
++ /* Mark pending interrupts as handled. */
++ Event->pending &= ~pending;
++#endif
++ spin_unlock_irqrestore(&Event->kernel->irq_lock, flags);
++ break;
++ }
++
++ /* Check whether there is a missed interrupt. */
++ for (i = 0; i < gcmCOUNTOF(Event->queues); ++i)
++ {
++ if ((Event->queues[i].head != gcvNULL)
++ && (Event->queues[i].stamp < queue->stamp)
++ && (Event->queues[i].source <= queue->source)
++ )
++ {
++ gcmkTRACE_N(
++ gcvLEVEL_ERROR,
++ gcmSIZEOF(i) + gcmSIZEOF(Event->queues[i].stamp),
++ "Event %d lost (stamp %llu)",
++ i, Event->queues[i].stamp
++ );
++
++ /* Use this event instead. */
++ queue = &Event->queues[i];
++ mask = 0;
++ }
++ }
++
++ if (mask != 0)
++ {
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++ gcmkTRACE_ZONE_N(
++ gcvLEVEL_INFO, gcvZONE_EVENT,
++ gcmSIZEOF(eventNumber),
++ "Processing interrupt %d",
++ eventNumber
++ );
++#endif
++ }
++
++ spin_lock_irqsave(&Event->kernel->irq_lock, flags);
++#if gcdSMP
++ /* Mark pending interrupt as handled. */
++ gckOS_AtomClearMask(Event->pending, mask);
++#elif defined(__QNXNTO__)
++ /* Mark pending interrupt as handled. */
++ atomic_clr(&Event->pending, mask);
++#else
++ /* Mark pending interrupt as handled. */
++ Event->pending &= ~mask;
++#endif
++ spin_unlock_irqrestore(&Event->kernel->irq_lock, flags);
++
++ /* We are in the notify loop. */
++ Event->inNotify = gcvTRUE;
++
++ /* We are in the notify loop. */
++ Event->inNotify = gcvTRUE;
++
++ /* Grab the event head. */
++ record = queue->head;
++
++ /* Now quickly clear its event list. */
++ queue->head = gcvNULL;
++
++ /* Release the mutex queue. */
++ gcmkONERROR(gckOS_ReleaseMutex(Event->os, Event->eventQueueMutex));
++ acquired = gcvFALSE;
++
++ /* Increase the number of free events. */
++ gcmkONERROR(gckOS_AtomIncrement(Event->os, Event->freeAtom, &free));
++
++ /* Walk all events for this interrupt. */
++ while (record != gcvNULL)
++ {
++ gcsEVENT_PTR recordNext;
++#ifndef __QNXNTO__
++ gctPOINTER logical;
++#endif
++#if gcdSECURE_USER
++ gctSIZE_T bytes;
++#endif
++
++ /* Grab next record. */
++ recordNext = record->next;
++
++#ifdef __QNXNTO__
++ /* Assign record->processID as the pid for this galcore thread.
++ * Used in OS calls like gckOS_UnlockMemory() which do not take a pid.
++ */
++ drv_thread_specific_key_assign(record->processID, 0, Event->kernel->core);
++#endif
++
++#if gcdSECURE_USER
++ /* Get the cache that belongs to this process. */
++ gcmkONERROR(gckKERNEL_GetProcessDBCache(Event->kernel,
++ record->processID,
++ &cache));
++#endif
++
++ gcmkTRACE_ZONE_N(
++ gcvLEVEL_INFO, gcvZONE_EVENT,
++ gcmSIZEOF(record->info.command),
++ "Processing event type: %d",
++ record->info.command
++ );
++
++ switch (record->info.command)
++ {
++ case gcvHAL_FREE_NON_PAGED_MEMORY:
++ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_EVENT,
++ "gcvHAL_FREE_NON_PAGED_MEMORY: 0x%x",
++ gcmNAME_TO_PTR(record->info.u.FreeNonPagedMemory.physical));
++
++ /* Free non-paged memory. */
++ status = gckOS_FreeNonPagedMemory(
++ Event->os,
++ (gctSIZE_T) record->info.u.FreeNonPagedMemory.bytes,
++ gcmNAME_TO_PTR(record->info.u.FreeNonPagedMemory.physical),
++ gcmUINT64_TO_PTR(record->info.u.FreeNonPagedMemory.logical));
++
++ if (gcmIS_SUCCESS(status))
++ {
++#if gcdSECURE_USER
++ gcmkVERIFY_OK(gckKERNEL_FlushTranslationCache(
++ Event->kernel,
++ cache,
++ gcmUINT64_TO_PTR(record->record.u.FreeNonPagedMemory.logical),
++ (gctSIZE_T) record->record.u.FreeNonPagedMemory.bytes));
++#endif
++ }
++ gcmRELEASE_NAME(record->info.u.FreeNonPagedMemory.physical);
++ break;
++
++ case gcvHAL_FREE_CONTIGUOUS_MEMORY:
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_EVENT,
++ "gcvHAL_FREE_CONTIGUOUS_MEMORY: 0x%x",
++ gcmNAME_TO_PTR(record->info.u.FreeContiguousMemory.physical));
++
++ /* Unmap the user memory. */
++ status = gckOS_FreeContiguous(
++ Event->os,
++ gcmNAME_TO_PTR(record->info.u.FreeContiguousMemory.physical),
++ gcmUINT64_TO_PTR(record->info.u.FreeContiguousMemory.logical),
++ (gctSIZE_T) record->info.u.FreeContiguousMemory.bytes);
++
++ if (gcmIS_SUCCESS(status))
++ {
++#if gcdSECURE_USER
++ gcmkVERIFY_OK(gckKERNEL_FlushTranslationCache(
++ Event->kernel,
++ cache,
++ gcmUINT64_TO_PTR(record->record.u.FreeContiguousMemory.logical),
++ (gctSIZE_T) record->record.u.FreeContiguousMemory.bytes));
++#endif
++ }
++ gcmRELEASE_NAME(record->info.u.FreeContiguousMemory.physical);
++ break;
++
++ case gcvHAL_FREE_VIDEO_MEMORY:
++ node = gcmUINT64_TO_PTR(record->info.u.FreeVideoMemory.node);
++ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_EVENT,
++ "gcvHAL_FREE_VIDEO_MEMORY: 0x%x",
++ node);
++#ifdef __QNXNTO__
++#if gcdUSE_VIDMEM_PER_PID
++ /* Check if the VidMem object still exists. */
++ if (gckKERNEL_GetVideoMemoryPoolPid(record->kernel,
++ gcvPOOL_SYSTEM,
++ record->processID,
++ gcvNULL) == gcvSTATUS_NOT_FOUND)
++ {
++ /*printf("Vidmem not found for process:%d\n", queue->processID);*/
++ status = gcvSTATUS_OK;
++ break;
++ }
++#else
++ if ((node->VidMem.memory->object.type == gcvOBJ_VIDMEM)
++ && (node->VidMem.logical != gcvNULL)
++ )
++ {
++ gcmkERR_BREAK(
++ gckKERNEL_UnmapVideoMemory(record->kernel,
++ node->VidMem.logical,
++ record->processID,
++ node->VidMem.bytes));
++ node->VidMem.logical = gcvNULL;
++ }
++#endif
++#endif
++
++ /* Free video memory. */
++ status =
++ gckVIDMEM_Free(Event->kernel, node);
++
++ break;
++
++ case gcvHAL_WRITE_DATA:
++#ifndef __QNXNTO__
++ /* Convert physical into logical address. */
++ gcmkERR_BREAK(
++ gckOS_MapPhysical(Event->os,
++ record->info.u.WriteData.address,
++ gcmSIZEOF(gctUINT32),
++ &logical));
++
++ /* Write data. */
++ gcmkERR_BREAK(
++ gckOS_WriteMemory(Event->os,
++ logical,
++ record->info.u.WriteData.data));
++
++ /* Unmap the physical memory. */
++ gcmkERR_BREAK(
++ gckOS_UnmapPhysical(Event->os,
++ logical,
++ gcmSIZEOF(gctUINT32)));
++#else
++ /* Write data. */
++ gcmkERR_BREAK(
++ gckOS_WriteMemory(Event->os,
++ (gctPOINTER)
++ record->info.u.WriteData.address,
++ record->info.u.WriteData.data));
++#endif
++ break;
++
++ case gcvHAL_UNLOCK_VIDEO_MEMORY:
++ node = gcmUINT64_TO_PTR(record->info.u.UnlockVideoMemory.node);
++
++ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_EVENT,
++ "gcvHAL_UNLOCK_VIDEO_MEMORY: 0x%x",
++ node);
++
++ /* Save node information before it disappears. */
++#if gcdSECURE_USER
++ if (node->VidMem.memory->object.type == gcvOBJ_VIDMEM)
++ {
++ logical = gcvNULL;
++ bytes = 0;
++ }
++ else
++ {
++ logical = node->Virtual.logical;
++ bytes = node->Virtual.bytes;
++ }
++#endif
++
++ /* Unlock. */
++ status = gckVIDMEM_Unlock(
++ Event->kernel,
++ node,
++ record->info.u.UnlockVideoMemory.type,
++ gcvNULL);
++
++#if gcdSECURE_USER
++ if (gcmIS_SUCCESS(status) && (logical != gcvNULL))
++ {
++ gcmkVERIFY_OK(gckKERNEL_FlushTranslationCache(
++ Event->kernel,
++ cache,
++ logical,
++ bytes));
++ }
++#endif
++ break;
++
++ case gcvHAL_SIGNAL:
++ signal = gcmUINT64_TO_PTR(record->info.u.Signal.signal);
++ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_EVENT,
++ "gcvHAL_SIGNAL: 0x%x",
++ signal);
++
++#ifdef __QNXNTO__
++ if ((record->info.u.Signal.coid == 0)
++ && (record->info.u.Signal.rcvid == 0)
++ )
++ {
++ /* Kernel signal. */
++ gcmkERR_BREAK(
++ gckOS_Signal(Event->os,
++ signal,
++ gcvTRUE));
++ }
++ else
++ {
++ /* User signal. */
++ gcmkERR_BREAK(
++ gckOS_UserSignal(Event->os,
++ signal,
++ record->info.u.Signal.rcvid,
++ record->info.u.Signal.coid));
++ }
++#else
++ /* Set signal. */
++ if (gcmUINT64_TO_PTR(record->info.u.Signal.process) == gcvNULL)
++ {
++ /* Kernel signal. */
++ gcmkERR_BREAK(
++ gckOS_Signal(Event->os,
++ signal,
++ gcvTRUE));
++ }
++ else
++ {
++ /* User signal. */
++ gcmkERR_BREAK(
++ gckOS_UserSignal(Event->os,
++ signal,
++ gcmUINT64_TO_PTR(record->info.u.Signal.process)));
++ }
++
++ gcmkASSERT(record->info.u.Signal.auxSignal == 0);
++#endif
++ break;
++
++ case gcvHAL_UNMAP_USER_MEMORY:
++ info = gcmNAME_TO_PTR(record->info.u.UnmapUserMemory.info);
++ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_EVENT,
++ "gcvHAL_UNMAP_USER_MEMORY: 0x%x",
++ info);
++
++ /* Unmap the user memory. */
++ status = gckOS_UnmapUserMemory(
++ Event->os,
++ Event->kernel->core,
++ gcmUINT64_TO_PTR(record->info.u.UnmapUserMemory.memory),
++ (gctSIZE_T) record->info.u.UnmapUserMemory.size,
++ info,
++ record->info.u.UnmapUserMemory.address);
++
++#if gcdSECURE_USER
++ if (gcmIS_SUCCESS(status))
++ {
++ gcmkVERIFY_OK(gckKERNEL_FlushTranslationCache(
++ Event->kernel,
++ cache,
++ gcmUINT64_TO_PTR(record->info.u.UnmapUserMemory.memory),
++ (gctSIZE_T) record->info.u.UnmapUserMemory.size));
++ }
++#endif
++ gcmRELEASE_NAME(record->info.u.UnmapUserMemory.info);
++ break;
++
++ case gcvHAL_TIMESTAMP:
++ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_EVENT,
++ "gcvHAL_TIMESTAMP: %d %d",
++ record->info.u.TimeStamp.timer,
++ record->info.u.TimeStamp.request);
++
++ /* Process the timestamp. */
++ switch (record->info.u.TimeStamp.request)
++ {
++ case 0:
++ status = gckOS_GetTime(&Event->kernel->timers[
++ record->info.u.TimeStamp.timer].
++ stopTime);
++ break;
++
++ case 1:
++ status = gckOS_GetTime(&Event->kernel->timers[
++ record->info.u.TimeStamp.timer].
++ startTime);
++ break;
++
++ default:
++ gcmkTRACE_ZONE_N(
++ gcvLEVEL_ERROR, gcvZONE_EVENT,
++ gcmSIZEOF(record->info.u.TimeStamp.request),
++ "Invalid timestamp request: %d",
++ record->info.u.TimeStamp.request
++ );
++
++ status = gcvSTATUS_INVALID_ARGUMENT;
++ break;
++ }
++ break;
++
++#if gcdVIRTUAL_COMMAND_BUFFER
++ case gcvHAL_FREE_VIRTUAL_COMMAND_BUFFER:
++ gcmkVERIFY_OK(
++ gckKERNEL_DestroyVirtualCommandBuffer(Event->kernel,
++ (gctSIZE_T) record->info.u.FreeVirtualCommandBuffer.bytes,
++ gcmNAME_TO_PTR(record->info.u.FreeVirtualCommandBuffer.physical),
++ gcmUINT64_TO_PTR(record->info.u.FreeVirtualCommandBuffer.logical)
++ ));
++ gcmRELEASE_NAME(record->info.u.FreeVirtualCommandBuffer.physical);
++ break;
++#endif
++
++#if gcdANDROID_NATIVE_FENCE_SYNC
++ case gcvHAL_SYNC_POINT:
++ {
++ gctSYNC_POINT syncPoint;
++
++ syncPoint = gcmUINT64_TO_PTR(record->info.u.SyncPoint.syncPoint);
++ status = gckOS_SignalSyncPoint(Event->os, syncPoint);
++ }
++ break;
++#endif
++
++ case gcvHAL_COMMIT_DONE:
++ break;
++
++ default:
++ /* Invalid argument. */
++ gcmkTRACE_ZONE_N(
++ gcvLEVEL_ERROR, gcvZONE_EVENT,
++ gcmSIZEOF(record->info.command),
++ "Unknown event type: %d",
++ record->info.command
++ );
++
++ status = gcvSTATUS_INVALID_ARGUMENT;
++ break;
++ }
++
++ /* Make sure there are no errors generated. */
++ if (gcmIS_ERROR(status))
++ {
++ gcmkTRACE_ZONE_N(
++ gcvLEVEL_WARNING, gcvZONE_EVENT,
++ gcmSIZEOF(status),
++ "Event produced status: %d(%s)",
++ status, gckOS_DebugStatus2Name(status));
++ }
++
++ /* Free the event. */
++ gcmkVERIFY_OK(gckEVENT_FreeRecord(Event, record));
++
++ /* Advance to next record. */
++ record = recordNext;
++ }
++
++ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_EVENT,
++ "Handled interrupt 0x%x", mask);
++ }
++
++ if (IDs == 0)
++ {
++ gcmkONERROR(_TryToIdleGPU(Event));
++ }
++
++ /* We are out the notify loop. */
++ Event->inNotify = gcvFALSE;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ /* Release mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Event->os, Event->eventQueueMutex));
++ }
++
++#if !gcdSMP
++ if (suspended)
++ {
++ /* Resume interrupts. */
++ gcmkVERIFY_OK(gckOS_ResumeInterruptEx(Event->os, Event->kernel->core));
++ }
++#endif
++
++ /* We are out the notify loop. */
++ Event->inNotify = gcvFALSE;
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++** gckEVENT_FreeProcess
++**
++** Free all events owned by a particular process ID.
++**
++** INPUT:
++**
++** gckEVENT Event
++** Pointer to an gckEVENT object.
++**
++** gctUINT32 ProcessID
++** Process ID of the process to be freed up.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckEVENT_FreeProcess(
++ IN gckEVENT Event,
++ IN gctUINT32 ProcessID
++ )
++{
++ gctSIZE_T i;
++ gctBOOL acquired = gcvFALSE;
++ gcsEVENT_PTR record, next;
++ gceSTATUS status;
++ gcsEVENT_PTR deleteHead, deleteTail;
++
++ gcmkHEADER_ARG("Event=0x%x ProcessID=%d", Event, ProcessID);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++
++ /* Walk through all queues. */
++ for (i = 0; i < gcmCOUNTOF(Event->queues); ++i)
++ {
++ if (Event->queues[i].head != gcvNULL)
++ {
++ /* Grab the event queue mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(Event->os,
++ Event->eventQueueMutex,
++ gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Grab the mutex head. */
++ record = Event->queues[i].head;
++ Event->queues[i].head = gcvNULL;
++ Event->queues[i].tail = gcvNULL;
++ deleteHead = gcvNULL;
++ deleteTail = gcvNULL;
++
++ while (record != gcvNULL)
++ {
++ next = record->next;
++ if (record->processID == ProcessID)
++ {
++ if (deleteHead == gcvNULL)
++ {
++ deleteHead = record;
++ }
++ else
++ {
++ deleteTail->next = record;
++ }
++
++ deleteTail = record;
++ }
++ else
++ {
++ if (Event->queues[i].head == gcvNULL)
++ {
++ Event->queues[i].head = record;
++ }
++ else
++ {
++ Event->queues[i].tail->next = record;
++ }
++
++ Event->queues[i].tail = record;
++ }
++
++ record->next = gcvNULL;
++ record = next;
++ }
++
++ /* Release the mutex queue. */
++ gcmkONERROR(gckOS_ReleaseMutex(Event->os, Event->eventQueueMutex));
++ acquired = gcvFALSE;
++
++ /* Loop through the entire list of events. */
++ for (record = deleteHead; record != gcvNULL; record = next)
++ {
++ /* Get the next event record. */
++ next = record->next;
++
++ /* Free the event record. */
++ gcmkONERROR(gckEVENT_FreeRecord(Event, record));
++ }
++ }
++ }
++
++ gcmkONERROR(_TryToIdleGPU(Event));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Release the event queue mutex. */
++ if (acquired)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Event->os, Event->eventQueueMutex));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++** gckEVENT_Stop
++**
++** Stop the hardware using the End event mechanism.
++**
++** INPUT:
++**
++** gckEVENT Event
++** Pointer to an gckEVENT object.
++**
++** gctUINT32 ProcessID
++** Process ID Logical belongs.
++**
++** gctPHYS_ADDR Handle
++** Physical address handle. If gcvNULL it is video memory.
++**
++** gctPOINTER Logical
++** Logical address to flush.
++**
++** gctSIGNAL Signal
++** Pointer to the signal to trigger.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckEVENT_Stop(
++ IN gckEVENT Event,
++ IN gctUINT32 ProcessID,
++ IN gctPHYS_ADDR Handle,
++ IN gctPOINTER Logical,
++ IN gctSIGNAL Signal,
++ IN OUT gctSIZE_T * waitSize
++ )
++{
++ gceSTATUS status;
++ /* gctSIZE_T waitSize;*/
++ gcsEVENT_PTR record;
++ gctUINT8 id = 0xFF;
++
++ gcmkHEADER_ARG("Event=0x%x ProcessID=%u Handle=0x%x Logical=0x%x "
++ "Signal=0x%x",
++ Event, ProcessID, Handle, Logical, Signal);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++
++ /* Submit the current event queue. */
++ gcmkONERROR(gckEVENT_Submit(Event, gcvTRUE, gcvFALSE));
++
++ /* Allocate a record. */
++ gcmkONERROR(gckEVENT_AllocateRecord(Event, gcvTRUE, &record));
++
++ /* Initialize the record. */
++ record->next = gcvNULL;
++ record->processID = ProcessID;
++ record->info.command = gcvHAL_SIGNAL;
++ record->info.u.Signal.signal = gcmPTR_TO_UINT64(Signal);
++#ifdef __QNXNTO__
++ record->info.u.Signal.coid = 0;
++ record->info.u.Signal.rcvid = 0;
++#endif
++ record->info.u.Signal.auxSignal = 0;
++ record->info.u.Signal.process = 0;
++
++
++ gcmkONERROR(gckEVENT_GetEvent(Event, gcvTRUE, &id, record, gcvKERNEL_PIXEL));
++
++ /* Replace last WAIT with END. */
++ gcmkONERROR(gckHARDWARE_End(
++ Event->kernel->hardware, Logical, waitSize
++ ));
++
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ /* Flush the cache for the END. */
++ gcmkONERROR(gckOS_CacheClean(
++ Event->os,
++ ProcessID,
++ gcvNULL,
++ Handle,
++ Logical,
++ *waitSize
++ ));
++#endif
++
++ /* Wait for the signal. */
++ gcmkONERROR(gckOS_WaitSignal(Event->os, Signal, gcvINFINITE));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++static void
++_PrintRecord(
++ gcsEVENT_PTR record
++ )
++{
++ switch (record->info.command)
++ {
++ case gcvHAL_FREE_NON_PAGED_MEMORY:
++ gcmkPRINT(" gcvHAL_FREE_NON_PAGED_MEMORY");
++ break;
++
++ case gcvHAL_FREE_CONTIGUOUS_MEMORY:
++ gcmkPRINT(" gcvHAL_FREE_CONTIGUOUS_MEMORY");
++ break;
++
++ case gcvHAL_FREE_VIDEO_MEMORY:
++ gcmkPRINT(" gcvHAL_FREE_VIDEO_MEMORY");
++ break;
++
++ case gcvHAL_WRITE_DATA:
++ gcmkPRINT(" gcvHAL_WRITE_DATA");
++ break;
++
++ case gcvHAL_UNLOCK_VIDEO_MEMORY:
++ gcmkPRINT(" gcvHAL_UNLOCK_VIDEO_MEMORY");
++ break;
++
++ case gcvHAL_SIGNAL:
++ gcmkPRINT(" gcvHAL_SIGNAL process=%d signal=0x%x",
++ record->info.u.Signal.process,
++ record->info.u.Signal.signal);
++ break;
++
++ case gcvHAL_UNMAP_USER_MEMORY:
++ gcmkPRINT(" gcvHAL_UNMAP_USER_MEMORY");
++ break;
++
++ case gcvHAL_TIMESTAMP:
++ gcmkPRINT(" gcvHAL_TIMESTAMP");
++ break;
++
++ case gcvHAL_COMMIT_DONE:
++ gcmkPRINT(" gcvHAL_COMMIT_DONE");
++ break;
++
++ case gcvHAL_FREE_VIRTUAL_COMMAND_BUFFER:
++ gcmkPRINT(" gcvHAL_FREE_VIRTUAL_COMMAND_BUFFER logical=0x%08x",
++ record->info.u.FreeVirtualCommandBuffer.logical);
++ break;
++
++ default:
++ gcmkPRINT(" Illegal Event %d", record->info.command);
++ break;
++ }
++}
++
++/*******************************************************************************
++** gckEVENT_Dump
++**
++** Dump record in event queue when stuck happens.
++** No protection for the event queue.
++**/
++gceSTATUS
++gckEVENT_Dump(
++ IN gckEVENT Event
++ )
++{
++ gcsEVENT_QUEUE_PTR queueHead = Event->queueHead;
++ gcsEVENT_QUEUE_PTR queue;
++ gcsEVENT_PTR record = gcvNULL;
++ gctINT i;
++
++ gcmkHEADER_ARG("Event=0x%x", Event);
++
++ gcmkPRINT("**************************\n");
++ gcmkPRINT("*** EVENT STATE DUMP ***\n");
++ gcmkPRINT("**************************\n");
++
++
++ gcmkPRINT(" Unsumbitted Event:");
++ while(queueHead)
++ {
++ queue = queueHead;
++ record = queueHead->head;
++
++ gcmkPRINT(" [%x]:", queue);
++ while(record)
++ {
++ _PrintRecord(record);
++ record = record->next;
++ }
++
++ if (queueHead == Event->queueTail)
++ {
++ queueHead = gcvNULL;
++ }
++ else
++ {
++ queueHead = queueHead->next;
++ }
++ }
++
++ gcmkPRINT(" Untriggered Event:");
++ for (i = 0; i < 30; i++)
++ {
++ queue = &Event->queues[i];
++ record = queue->head;
++
++ gcmkPRINT(" [%d]:", i);
++ while(record)
++ {
++ _PrintRecord(record);
++ record = record->next;
++ }
++ }
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS gckEVENT_WaitEmpty(gckEVENT Event)
++{
++ gctBOOL isEmpty;
++
++ while (Event->inNotify || (gcmIS_SUCCESS(gckEVENT_IsEmpty(Event, &isEmpty)) && !isEmpty)) ;
++
++ return gcvSTATUS_OK;
++}
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel.h linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel.h
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel.h 2015-07-27 23:13:06.190893891 +0200
+@@ -0,0 +1,1007 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_kernel_h_
++#define __gc_hal_kernel_h_
++
++#include <linux/spinlock.h>
++
++#include "gc_hal.h"
++#include "gc_hal_kernel_hardware.h"
++#include "gc_hal_driver.h"
++
++#if gcdENABLE_VG
++#include "gc_hal_kernel_vg.h"
++#endif
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++
++/*******************************************************************************
++***** New MMU Defination *******************************************************/
++#define gcdMMU_MTLB_SHIFT 22
++#define gcdMMU_STLB_4K_SHIFT 12
++#define gcdMMU_STLB_64K_SHIFT 16
++
++#define gcdMMU_MTLB_BITS (32 - gcdMMU_MTLB_SHIFT)
++#define gcdMMU_PAGE_4K_BITS gcdMMU_STLB_4K_SHIFT
++#define gcdMMU_STLB_4K_BITS (32 - gcdMMU_MTLB_BITS - gcdMMU_PAGE_4K_BITS)
++#define gcdMMU_PAGE_64K_BITS gcdMMU_STLB_64K_SHIFT
++#define gcdMMU_STLB_64K_BITS (32 - gcdMMU_MTLB_BITS - gcdMMU_PAGE_64K_BITS)
++
++#define gcdMMU_MTLB_ENTRY_NUM (1 << gcdMMU_MTLB_BITS)
++#define gcdMMU_MTLB_SIZE (gcdMMU_MTLB_ENTRY_NUM << 2)
++#define gcdMMU_STLB_4K_ENTRY_NUM (1 << gcdMMU_STLB_4K_BITS)
++#define gcdMMU_STLB_4K_SIZE (gcdMMU_STLB_4K_ENTRY_NUM << 2)
++#define gcdMMU_PAGE_4K_SIZE (1 << gcdMMU_STLB_4K_SHIFT)
++#define gcdMMU_STLB_64K_ENTRY_NUM (1 << gcdMMU_STLB_64K_BITS)
++#define gcdMMU_STLB_64K_SIZE (gcdMMU_STLB_64K_ENTRY_NUM << 2)
++#define gcdMMU_PAGE_64K_SIZE (1 << gcdMMU_STLB_64K_SHIFT)
++
++#define gcdMMU_MTLB_MASK (~((1U << gcdMMU_MTLB_SHIFT)-1))
++#define gcdMMU_STLB_4K_MASK ((~0U << gcdMMU_STLB_4K_SHIFT) ^ gcdMMU_MTLB_MASK)
++#define gcdMMU_PAGE_4K_MASK (gcdMMU_PAGE_4K_SIZE - 1)
++#define gcdMMU_STLB_64K_MASK ((~((1U << gcdMMU_STLB_64K_SHIFT)-1)) ^ gcdMMU_MTLB_MASK)
++#define gcdMMU_PAGE_64K_MASK (gcdMMU_PAGE_64K_SIZE - 1)
++
++/* Page offset definitions. */
++#define gcdMMU_OFFSET_4K_BITS (32 - gcdMMU_MTLB_BITS - gcdMMU_STLB_4K_BITS)
++#define gcdMMU_OFFSET_4K_MASK ((1U << gcdMMU_OFFSET_4K_BITS) - 1)
++#define gcdMMU_OFFSET_16K_BITS (32 - gcdMMU_MTLB_BITS - gcdMMU_STLB_16K_BITS)
++#define gcdMMU_OFFSET_16K_MASK ((1U << gcdMMU_OFFSET_16K_BITS) - 1)
++
++/*******************************************************************************
++***** Process Secure Cache ****************************************************/
++
++#define gcdSECURE_CACHE_LRU 1
++#define gcdSECURE_CACHE_LINEAR 2
++#define gcdSECURE_CACHE_HASH 3
++#define gcdSECURE_CACHE_TABLE 4
++
++typedef struct _gcskLOGICAL_CACHE * gcskLOGICAL_CACHE_PTR;
++typedef struct _gcskLOGICAL_CACHE gcskLOGICAL_CACHE;
++struct _gcskLOGICAL_CACHE
++{
++ /* Logical address. */
++ gctPOINTER logical;
++
++ /* DMAable address. */
++ gctUINT32 dma;
++
++#if gcdSECURE_CACHE_METHOD == gcdSECURE_CACHE_HASH
++ /* Pointer to the previous and next hash tables. */
++ gcskLOGICAL_CACHE_PTR nextHash;
++ gcskLOGICAL_CACHE_PTR prevHash;
++#endif
++
++#if gcdSECURE_CACHE_METHOD != gcdSECURE_CACHE_TABLE
++ /* Pointer to the previous and next slot. */
++ gcskLOGICAL_CACHE_PTR next;
++ gcskLOGICAL_CACHE_PTR prev;
++#endif
++
++#if gcdSECURE_CACHE_METHOD == gcdSECURE_CACHE_LINEAR
++ /* Time stamp. */
++ gctUINT64 stamp;
++#endif
++};
++
++typedef struct _gcskSECURE_CACHE * gcskSECURE_CACHE_PTR;
++typedef struct _gcskSECURE_CACHE
++{
++ /* Cache memory. */
++ gcskLOGICAL_CACHE cache[1 + gcdSECURE_CACHE_SLOTS];
++
++ /* Last known index for LINEAR mode. */
++ gcskLOGICAL_CACHE_PTR cacheIndex;
++
++ /* Current free slot for LINEAR mode. */
++ gctUINT32 cacheFree;
++
++ /* Time stamp for LINEAR mode. */
++ gctUINT64 cacheStamp;
++
++#if gcdSECURE_CACHE_METHOD == gcdSECURE_CACHE_HASH
++ /* Hash table for HASH mode. */
++ gcskLOGICAL_CACHE hash[256];
++#endif
++}
++gcskSECURE_CACHE;
++
++/*******************************************************************************
++***** Process Database Management *********************************************/
++
++typedef enum _gceDATABASE_TYPE
++{
++ gcvDB_VIDEO_MEMORY = 1, /* Video memory created. */
++ gcvDB_COMMAND_BUFFER, /* Command Buffer. */
++ gcvDB_NON_PAGED, /* Non paged memory. */
++ gcvDB_CONTIGUOUS, /* Contiguous memory. */
++ gcvDB_SIGNAL, /* Signal. */
++ gcvDB_VIDEO_MEMORY_LOCKED, /* Video memory locked. */
++ gcvDB_CONTEXT, /* Context */
++ gcvDB_IDLE, /* GPU idle. */
++ gcvDB_MAP_MEMORY, /* Map memory */
++ gcvDB_SHARED_INFO, /* Private data */
++ gcvDB_MAP_USER_MEMORY, /* Map user memory */
++ gcvDB_SYNC_POINT, /* Sync point. */
++ gcvDB_VIDEO_MEMORY_RESERVED, /* Reserved video memory */
++ gcvDB_VIDEO_MEMORY_CONTIGUOUS, /* Contiguous video memory */
++ gcvDB_VIDEO_MEMORY_VIRTUAL, /* Virtual video memory */
++}
++gceDATABASE_TYPE;
++
++typedef struct _gcsDATABASE_RECORD * gcsDATABASE_RECORD_PTR;
++typedef struct _gcsDATABASE_RECORD
++{
++ /* Pointer to kernel. */
++ gckKERNEL kernel;
++
++ /* Pointer to next database record. */
++ gcsDATABASE_RECORD_PTR next;
++
++ /* Type of record. */
++ gceDATABASE_TYPE type;
++
++ /* Data for record. */
++ gctPOINTER data;
++ gctPHYS_ADDR physical;
++ gctSIZE_T bytes;
++}
++gcsDATABASE_RECORD;
++
++typedef struct _gcsDATABASE * gcsDATABASE_PTR;
++typedef struct _gcsDATABASE
++{
++ /* Pointer to next entry is hash list. */
++ gcsDATABASE_PTR next;
++ gctSIZE_T slot;
++
++ /* Process ID. */
++ gctUINT32 processID;
++
++ /* Sizes to query. */
++ gcsDATABASE_COUNTERS vidMem;
++ gcsDATABASE_COUNTERS nonPaged;
++ gcsDATABASE_COUNTERS contiguous;
++ gcsDATABASE_COUNTERS mapUserMemory;
++ gcsDATABASE_COUNTERS mapMemory;
++ gcsDATABASE_COUNTERS vidMemResv;
++ gcsDATABASE_COUNTERS vidMemCont;
++ gcsDATABASE_COUNTERS vidMemVirt;
++
++ /* Idle time management. */
++ gctUINT64 lastIdle;
++ gctUINT64 idle;
++
++ /* Pointer to database. */
++ gcsDATABASE_RECORD_PTR list[48];
++
++#if gcdSECURE_USER
++ /* Secure cache. */
++ gcskSECURE_CACHE cache;
++#endif
++
++ gctPOINTER handleDatabase;
++ gctPOINTER handleDatabaseMutex;
++}
++gcsDATABASE;
++
++/* Create a process database that will contain all its allocations. */
++gceSTATUS
++gckKERNEL_CreateProcessDB(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID
++ );
++
++/* Add a record to the process database. */
++gceSTATUS
++gckKERNEL_AddProcessDB(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ IN gceDATABASE_TYPE Type,
++ IN gctPOINTER Pointer,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Size
++ );
++
++/* Remove a record to the process database. */
++gceSTATUS
++gckKERNEL_RemoveProcessDB(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ IN gceDATABASE_TYPE Type,
++ IN gctPOINTER Pointer
++ );
++
++/* Destroy the process database. */
++gceSTATUS
++gckKERNEL_DestroyProcessDB(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID
++ );
++
++/* Find a record to the process database. */
++gceSTATUS
++gckKERNEL_FindProcessDB(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ IN gctUINT32 ThreadID,
++ IN gceDATABASE_TYPE Type,
++ IN gctPOINTER Pointer,
++ OUT gcsDATABASE_RECORD_PTR Record
++ );
++
++/* Query the process database. */
++gceSTATUS
++gckKERNEL_QueryProcessDB(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ IN gctBOOL LastProcessID,
++ IN gceDATABASE_TYPE Type,
++ OUT gcuDATABASE_INFO * Info
++ );
++
++/* Dump the process database. */
++gceSTATUS
++gckKERNEL_DumpProcessDB(
++ IN gckKERNEL Kernel
++ );
++
++/* ID database */
++gceSTATUS
++gckKERNEL_CreateIntegerDatabase(
++ IN gckKERNEL Kernel,
++ OUT gctPOINTER * Database
++ );
++
++gceSTATUS
++gckKERNEL_DestroyIntegerDatabase(
++ IN gckKERNEL Kernel,
++ IN gctPOINTER Database
++ );
++
++gceSTATUS
++gckKERNEL_AllocateIntegerId(
++ IN gctPOINTER Database,
++ IN gctPOINTER Pointer,
++ OUT gctUINT32 * Id
++ );
++
++gceSTATUS
++gckKERNEL_FreeIntegerId(
++ IN gctPOINTER Database,
++ IN gctUINT32 Id
++ );
++
++gceSTATUS
++gckKERNEL_QueryIntegerId(
++ IN gctPOINTER Database,
++ IN gctUINT32 Id,
++ OUT gctPOINTER * Pointer
++ );
++
++gctUINT32
++gckKERNEL_AllocateNameFromPointer(
++ IN gckKERNEL Kernel,
++ IN gctPOINTER Pointer
++ );
++
++gctPOINTER
++gckKERNEL_QueryPointerFromName(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 Name
++ );
++
++gceSTATUS
++gckKERNEL_DeleteName(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 Name
++ );
++
++#if gcdSECURE_USER
++/* Get secure cache from the process database. */
++gceSTATUS
++gckKERNEL_GetProcessDBCache(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ OUT gcskSECURE_CACHE_PTR * Cache
++ );
++#endif
++
++/*******************************************************************************
++********* Timer Management ****************************************************/
++typedef struct _gcsTIMER * gcsTIMER_PTR;
++typedef struct _gcsTIMER
++{
++ /* Start and Stop time holders. */
++ gctUINT64 startTime;
++ gctUINT64 stopTime;
++}
++gcsTIMER;
++
++/******************************************************************************\
++********************************** Structures **********************************
++\******************************************************************************/
++
++/* gckDB object. */
++struct _gckDB
++{
++ /* Database management. */
++ gcsDATABASE_PTR db[16];
++ gctPOINTER dbMutex;
++ gcsDATABASE_PTR freeDatabase;
++ gcsDATABASE_RECORD_PTR freeRecord;
++ gcsDATABASE_PTR lastDatabase;
++ gctUINT32 lastProcessID;
++ gctUINT64 lastIdle;
++ gctUINT64 idleTime;
++ gctUINT64 lastSlowdown;
++ gctUINT64 lastSlowdownIdle;
++ /* ID - Pointer database*/
++ gctPOINTER pointerDatabase;
++ gctPOINTER pointerDatabaseMutex;
++};
++
++#if gcdVIRTUAL_COMMAND_BUFFER
++typedef struct _gckVIRTUAL_COMMAND_BUFFER * gckVIRTUAL_COMMAND_BUFFER_PTR;
++typedef struct _gckVIRTUAL_COMMAND_BUFFER
++{
++ gctPHYS_ADDR physical;
++ gctPOINTER userLogical;
++ gctPOINTER kernelLogical;
++ gctSIZE_T pageCount;
++ gctPOINTER pageTable;
++ gctUINT32 gpuAddress;
++ gctUINT pid;
++ gckVIRTUAL_COMMAND_BUFFER_PTR next;
++ gckVIRTUAL_COMMAND_BUFFER_PTR prev;
++ gckKERNEL kernel;
++}
++gckVIRTUAL_COMMAND_BUFFER;
++#endif
++
++/* gckKERNEL object. */
++struct _gckKERNEL
++{
++ /* Object. */
++ gcsOBJECT object;
++
++ /* Pointer to gckOS object. */
++ gckOS os;
++
++ /* Core */
++ gceCORE core;
++
++ /* Pointer to gckHARDWARE object. */
++ gckHARDWARE hardware;
++
++ /* Pointer to gckCOMMAND object. */
++ gckCOMMAND command;
++
++ /* Pointer to gckEVENT object. */
++ gckEVENT eventObj;
++
++ /* Pointer to context. */
++ gctPOINTER context;
++
++ /* Pointer to gckMMU object. */
++ gckMMU mmu;
++
++ /* Arom holding number of clients. */
++ gctPOINTER atomClients;
++
++#if VIVANTE_PROFILER
++ /* Enable profiling */
++ gctBOOL profileEnable;
++
++ /* Clear profile register or not*/
++ gctBOOL profileCleanRegister;
++
++#endif
++
++#ifdef QNX_SINGLE_THREADED_DEBUGGING
++ gctPOINTER debugMutex;
++#endif
++
++ /* Database management. */
++ gckDB db;
++ gctBOOL dbCreated;
++
++#if gcdENABLE_RECOVERY
++ gctPOINTER resetFlagClearTimer;
++ gctPOINTER resetAtom;
++ gctUINT64 resetTimeStamp;
++#endif
++
++ /* Pointer to gckEVENT object. */
++ gcsTIMER timers[8];
++ gctUINT32 timeOut;
++
++#if gcdENABLE_VG
++ gckVGKERNEL vg;
++#endif
++
++#if gcdVIRTUAL_COMMAND_BUFFER
++ gckVIRTUAL_COMMAND_BUFFER_PTR virtualBufferHead;
++ gckVIRTUAL_COMMAND_BUFFER_PTR virtualBufferTail;
++ gctPOINTER virtualBufferLock;
++#endif
++
++#if gcdDVFS
++ gckDVFS dvfs;
++#endif
++
++#if gcdANDROID_NATIVE_FENCE_SYNC
++ gctHANDLE timeline;
++#endif
++
++ spinlock_t irq_lock;
++
++ gctPOINTER vidmemMutex;
++};
++
++struct _FrequencyHistory
++{
++ gctUINT32 frequency;
++ gctUINT32 count;
++};
++
++/* gckDVFS object. */
++struct _gckDVFS
++{
++ gckOS os;
++ gckHARDWARE hardware;
++ gctPOINTER timer;
++ gctUINT32 pollingTime;
++ gctBOOL stop;
++ gctUINT32 totalConfig;
++ gctUINT32 loads[8];
++ gctUINT8 currentScale;
++ struct _FrequencyHistory frequencyHistory[16];
++};
++
++/* gckCOMMAND object. */
++struct _gckCOMMAND
++{
++ /* Object. */
++ gcsOBJECT object;
++
++ /* Pointer to required object. */
++ gckKERNEL kernel;
++ gckOS os;
++
++ /* Number of bytes per page. */
++ gctSIZE_T pageSize;
++
++ /* Current pipe select. */
++ gcePIPE_SELECT pipeSelect;
++
++ /* Command queue running flag. */
++ gctBOOL running;
++
++ /* Idle flag and commit stamp. */
++ gctBOOL idle;
++ gctUINT64 commitStamp;
++
++ /* Command queue mutex. */
++ gctPOINTER mutexQueue;
++
++ /* Context switching mutex. */
++ gctPOINTER mutexContext;
++
++#if VIVANTE_PROFILER_CONTEXT
++ /* Context sequence mutex. */
++ gctPOINTER mutexContextSeq;
++#endif
++
++ /* Command queue power semaphore. */
++ gctPOINTER powerSemaphore;
++
++ /* Current command queue. */
++ struct _gcskCOMMAND_QUEUE
++ {
++ gctSIGNAL signal;
++ gctPHYS_ADDR physical;
++ gctPOINTER logical;
++ }
++ queues[gcdCOMMAND_QUEUES];
++
++ gctPHYS_ADDR physical;
++ gctPOINTER logical;
++ gctUINT32 offset;
++ gctINT index;
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++ gctUINT wrapCount;
++#endif
++
++ /* The command queue is new. */
++ gctBOOL newQueue;
++
++ /* Context management. */
++ gckCONTEXT currContext;
++
++ /* Pointer to last WAIT command. */
++ gctPHYS_ADDR waitPhysical;
++ gctPOINTER waitLogical;
++ gctSIZE_T waitSize;
++
++ /* Command buffer alignment. */
++ gctSIZE_T alignment;
++ gctSIZE_T reservedHead;
++ gctSIZE_T reservedTail;
++
++ /* Commit counter. */
++ gctPOINTER atomCommit;
++
++ /* Kernel process ID. */
++ gctUINT32 kernelProcessID;
++
++ /* End Event signal. */
++ gctSIGNAL endEventSignal;
++
++#if gcdSECURE_USER
++ /* Hint array copy buffer. */
++ gctBOOL hintArrayAllocated;
++ gctUINT hintArraySize;
++ gctUINT32_PTR hintArray;
++#endif
++};
++
++typedef struct _gcsEVENT * gcsEVENT_PTR;
++
++/* Structure holding one event to be processed. */
++typedef struct _gcsEVENT
++{
++ /* Pointer to next event in queue. */
++ gcsEVENT_PTR next;
++
++ /* Event information. */
++ gcsHAL_INTERFACE info;
++
++ /* Process ID owning the event. */
++ gctUINT32 processID;
++
++#ifdef __QNXNTO__
++ /* Kernel. */
++ gckKERNEL kernel;
++#endif
++
++ gctBOOL fromKernel;
++}
++gcsEVENT;
++
++/* Structure holding a list of events to be processed by an interrupt. */
++typedef struct _gcsEVENT_QUEUE * gcsEVENT_QUEUE_PTR;
++typedef struct _gcsEVENT_QUEUE
++{
++ /* Time stamp. */
++ gctUINT64 stamp;
++
++ /* Source of the event. */
++ gceKERNEL_WHERE source;
++
++ /* Pointer to head of event queue. */
++ gcsEVENT_PTR head;
++
++ /* Pointer to tail of event queue. */
++ gcsEVENT_PTR tail;
++
++ /* Next list of events. */
++ gcsEVENT_QUEUE_PTR next;
++}
++gcsEVENT_QUEUE;
++
++/*
++ gcdREPO_LIST_COUNT defines the maximum number of event queues with different
++ hardware module sources that may coexist at the same time. Only two sources
++ are supported - gcvKERNEL_COMMAND and gcvKERNEL_PIXEL. gcvKERNEL_COMMAND
++ source is used only for managing the kernel command queue and is only issued
++ when the current command queue gets full. Since we commit event queues every
++ time we commit command buffers, in the worst case we can have up to three
++ pending event queues:
++ - gcvKERNEL_PIXEL
++ - gcvKERNEL_COMMAND (queue overflow)
++ - gcvKERNEL_PIXEL
++*/
++#define gcdREPO_LIST_COUNT 3
++
++/* gckEVENT object. */
++struct _gckEVENT
++{
++ /* The object. */
++ gcsOBJECT object;
++
++ /* Pointer to required objects. */
++ gckOS os;
++ gckKERNEL kernel;
++
++ /* Time stamp. */
++ gctUINT64 stamp;
++ gctUINT64 lastCommitStamp;
++
++ /* Queue mutex. */
++ gctPOINTER eventQueueMutex;
++
++ /* Array of event queues. */
++ gcsEVENT_QUEUE queues[30];
++ gctUINT8 lastID;
++ gctPOINTER freeAtom;
++
++ /* Pending events. */
++#if gcdSMP
++ gctPOINTER pending;
++#else
++ volatile gctUINT pending;
++#endif
++
++ /* List of free event structures and its mutex. */
++ gcsEVENT_PTR freeEventList;
++ gctSIZE_T freeEventCount;
++ gctPOINTER freeEventMutex;
++
++ /* Event queues. */
++ gcsEVENT_QUEUE_PTR queueHead;
++ gcsEVENT_QUEUE_PTR queueTail;
++ gcsEVENT_QUEUE_PTR freeList;
++ gcsEVENT_QUEUE repoList[gcdREPO_LIST_COUNT];
++ gctPOINTER eventListMutex;
++
++ gctPOINTER submitTimer;
++
++ volatile gctBOOL inNotify;
++};
++
++/* Free all events belonging to a process. */
++gceSTATUS
++gckEVENT_FreeProcess(
++ IN gckEVENT Event,
++ IN gctUINT32 ProcessID
++ );
++
++gceSTATUS
++gckEVENT_Stop(
++ IN gckEVENT Event,
++ IN gctUINT32 ProcessID,
++ IN gctPHYS_ADDR Handle,
++ IN gctPOINTER Logical,
++ IN gctSIGNAL Signal,
++ IN OUT gctSIZE_T * waitSize
++ );
++
++gceSTATUS
++gckEVENT_WaitEmpty(
++ IN gckEVENT Event
++ );
++
++/* gcuVIDMEM_NODE structure. */
++typedef union _gcuVIDMEM_NODE
++{
++ /* Allocated from gckVIDMEM. */
++ struct _gcsVIDMEM_NODE_VIDMEM
++ {
++ /* Owner of this node. */
++ gckVIDMEM memory;
++
++ /* Dual-linked list of nodes. */
++ gcuVIDMEM_NODE_PTR next;
++ gcuVIDMEM_NODE_PTR prev;
++
++ /* Dual linked list of free nodes. */
++ gcuVIDMEM_NODE_PTR nextFree;
++ gcuVIDMEM_NODE_PTR prevFree;
++
++ /* Information for this node. */
++ gctUINT32 offset;
++ gctSIZE_T bytes;
++ gctUINT32 alignment;
++
++#ifdef __QNXNTO__
++ /* Client/server vaddr (mapped using mmap_join). */
++ gctPOINTER logical;
++#endif
++
++ /* Locked counter. */
++ gctINT32 locked;
++
++ /* Memory pool. */
++ gcePOOL pool;
++ gctUINT32 physical;
++
++ /* Process ID owning this memory. */
++ gctUINT32 processID;
++
++ /* Prevent compositor from freeing until client unlocks. */
++ gctBOOL freePending;
++
++ /* */
++ gcsVIDMEM_NODE_SHARED_INFO sharedInfo;
++
++#if gcdDYNAMIC_MAP_RESERVED_MEMORY && gcdENABLE_VG
++ gctPOINTER kernelVirtual;
++#endif
++
++ /* Surface type. */
++ gceSURF_TYPE type;
++ }
++ VidMem;
++
++ /* Allocated from gckOS. */
++ struct _gcsVIDMEM_NODE_VIRTUAL
++ {
++ /* Pointer to gckKERNEL object. */
++ gckKERNEL kernel;
++
++ /* Information for this node. */
++ /* Contiguously allocated? */
++ gctBOOL contiguous;
++ /* mdl record pointer... a kmalloc address. Process agnostic. */
++ gctPHYS_ADDR physical;
++ gctSIZE_T bytes;
++ /* do_mmap_pgoff address... mapped per-process. */
++ gctPOINTER logical;
++
++ /* Page table information. */
++ /* Used only when node is not contiguous */
++ gctSIZE_T pageCount;
++
++ /* Used only when node is not contiguous */
++ gctPOINTER pageTables[gcdMAX_GPU_COUNT];
++ /* Pointer to gckKERNEL object who lock this. */
++ gckKERNEL lockKernels[gcdMAX_GPU_COUNT];
++ /* Actual physical address */
++ gctUINT32 addresses[gcdMAX_GPU_COUNT];
++
++ /* Locked counter. */
++ gctINT32 lockeds[gcdMAX_GPU_COUNT];
++
++#ifdef __QNXNTO__
++ /* Single linked list of nodes. */
++ gcuVIDMEM_NODE_PTR next;
++
++ /* Unlock pending flag. */
++ gctBOOL unlockPendings[gcdMAX_GPU_COUNT];
++
++ /* Free pending flag. */
++ gctBOOL freePending;
++#endif
++
++ /* Process ID owning this memory. */
++ gctUINT32 processID;
++
++ /* Owner process sets freed to true
++ * when it trys to free a locked
++ * node */
++ gctBOOL freed;
++
++ /* */
++ gcsVIDMEM_NODE_SHARED_INFO sharedInfo;
++
++ /* Surface type. */
++ gceSURF_TYPE type;
++ }
++ Virtual;
++}
++gcuVIDMEM_NODE;
++
++/* gckVIDMEM object. */
++struct _gckVIDMEM
++{
++ /* Object. */
++ gcsOBJECT object;
++
++ /* Pointer to gckOS object. */
++ gckOS os;
++
++ /* Information for this video memory heap. */
++ gctUINT32 baseAddress;
++ gctSIZE_T bytes;
++ gctSIZE_T freeBytes;
++
++ /* Mapping for each type of surface. */
++ gctINT mapping[gcvSURF_NUM_TYPES];
++
++ /* Sentinel nodes for up to 8 banks. */
++ gcuVIDMEM_NODE sentinel[8];
++
++ /* Allocation threshold. */
++ gctSIZE_T threshold;
++
++#if gcdUSE_VIDMEM_PER_PID
++ /* The Pid this VidMem belongs to. */
++ gctUINT32 pid;
++
++ struct _gckVIDMEM* next;
++#endif
++};
++
++/* gckMMU object. */
++struct _gckMMU
++{
++ /* The object. */
++ gcsOBJECT object;
++
++ /* Pointer to gckOS object. */
++ gckOS os;
++
++ /* Pointer to gckHARDWARE object. */
++ gckHARDWARE hardware;
++
++ /* The page table mutex. */
++ gctPOINTER pageTableMutex;
++
++ /* Page table information. */
++ gctSIZE_T pageTableSize;
++ gctPHYS_ADDR pageTablePhysical;
++ gctUINT32_PTR pageTableLogical;
++ gctUINT32 pageTableEntries;
++
++ /* Master TLB information. */
++ gctSIZE_T mtlbSize;
++ gctPHYS_ADDR mtlbPhysical;
++ gctUINT32_PTR mtlbLogical;
++ gctUINT32 mtlbEntries;
++
++ /* Free entries. */
++ gctUINT32 heapList;
++ gctBOOL freeNodes;
++
++ gctPOINTER staticSTLB;
++ gctBOOL enabled;
++
++ gctUINT32 dynamicMappingStart;
++
++#ifdef __QNXNTO__
++ /* Single linked list of all allocated nodes. */
++ gctPOINTER nodeMutex;
++ gcuVIDMEM_NODE_PTR nodeList;
++#endif
++};
++
++#if gcdVIRTUAL_COMMAND_BUFFER
++gceSTATUS
++gckOS_CreateKernelVirtualMapping(
++ IN gctPHYS_ADDR Physical,
++ OUT gctSIZE_T * PageCount,
++ OUT gctPOINTER * Logical
++ );
++
++gceSTATUS
++gckOS_DestroyKernelVirtualMapping(
++ IN gctPOINTER Logical
++ );
++
++gceSTATUS
++gckKERNEL_AllocateVirtualCommandBuffer(
++ IN gckKERNEL Kernel,
++ IN gctBOOL InUserSpace,
++ IN OUT gctSIZE_T * Bytes,
++ OUT gctPHYS_ADDR * Physical,
++ OUT gctPOINTER * Logical
++ );
++
++gceSTATUS
++gckKERNEL_DestroyVirtualCommandBuffer(
++ IN gckKERNEL Kernel,
++ IN gctSIZE_T Bytes,
++ IN gctPHYS_ADDR Physical,
++ IN gctPOINTER Logical
++ );
++
++gceSTATUS
++gckKERNEL_GetGPUAddress(
++ IN gckKERNEL Kernel,
++ IN gctPOINTER Logical,
++ OUT gctUINT32 * Address
++ );
++
++gceSTATUS
++gckKERNEL_QueryGPUAddress(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 GpuAddress,
++ OUT gckVIRTUAL_COMMAND_BUFFER_PTR * Buffer
++ );
++#endif
++
++gceSTATUS
++gckKERNEL_AttachProcess(
++ IN gckKERNEL Kernel,
++ IN gctBOOL Attach
++ );
++
++gceSTATUS
++gckKERNEL_AttachProcessEx(
++ IN gckKERNEL Kernel,
++ IN gctBOOL Attach,
++ IN gctUINT32 PID
++ );
++
++#if gcdSECURE_USER
++gceSTATUS
++gckKERNEL_MapLogicalToPhysical(
++ IN gckKERNEL Kernel,
++ IN gcskSECURE_CACHE_PTR Cache,
++ IN OUT gctPOINTER * Data
++ );
++
++gceSTATUS
++gckKERNEL_FlushTranslationCache(
++ IN gckKERNEL Kernel,
++ IN gcskSECURE_CACHE_PTR Cache,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes
++ );
++#endif
++
++gceSTATUS
++gckHARDWARE_QueryIdle(
++ IN gckHARDWARE Hardware,
++ OUT gctBOOL_PTR IsIdle
++ );
++
++/******************************************************************************\
++******************************* gckCONTEXT Object *******************************
++\******************************************************************************/
++
++gceSTATUS
++gckCONTEXT_Construct(
++ IN gckOS Os,
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 ProcessID,
++ OUT gckCONTEXT * Context
++ );
++
++gceSTATUS
++gckCONTEXT_Destroy(
++ IN gckCONTEXT Context
++ );
++
++gceSTATUS
++gckCONTEXT_Update(
++ IN gckCONTEXT Context,
++ IN gctUINT32 ProcessID,
++ IN gcsSTATE_DELTA_PTR StateDelta
++ );
++
++#if gcdLINK_QUEUE_SIZE
++void
++gckLINKQUEUE_Enqueue(
++ IN gckLINKQUEUE LinkQueue,
++ IN gctUINT32 start,
++ IN gctUINT32 end
++ );
++
++void
++gckLINKQUEUE_GetData(
++ IN gckLINKQUEUE LinkQueue,
++ IN gctUINT32 Index,
++ OUT gckLINKDATA * Data
++ );
++#endif
++
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __gc_hal_kernel_h_ */
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_heap.c linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_heap.c
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_heap.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_heap.c 2015-07-27 23:13:06.194879670 +0200
+@@ -0,0 +1,859 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++/**
++** @file
++** gckHEAP object for kernel HAL layer. The heap implemented here is an arena-
++** based memory allocation. An arena-based memory heap allocates data quickly
++** from specified arenas and reduces memory fragmentation.
++**
++*/
++#include "gc_hal_kernel_precomp.h"
++
++#define _GC_OBJ_ZONE gcvZONE_HEAP
++
++/*******************************************************************************
++***** Structures ***************************************************************
++*******************************************************************************/
++
++#define gcdIN_USE ((gcskNODE_PTR) ~0)
++
++typedef struct _gcskNODE * gcskNODE_PTR;
++typedef struct _gcskNODE
++{
++ /* Number of byets in node. */
++ gctSIZE_T bytes;
++
++ /* Pointer to next free node, or gcvNULL to mark the node as freed, or
++ ** gcdIN_USE to mark the node as used. */
++ gcskNODE_PTR next;
++
++#if gcmIS_DEBUG(gcdDEBUG_CODE)
++ /* Time stamp of allocation. */
++ gctUINT64 timeStamp;
++#endif
++}
++gcskNODE;
++
++typedef struct _gcskHEAP * gcskHEAP_PTR;
++typedef struct _gcskHEAP
++{
++ /* Linked list. */
++ gcskHEAP_PTR next;
++ gcskHEAP_PTR prev;
++
++ /* Heap size. */
++ gctSIZE_T size;
++
++ /* Free list. */
++ gcskNODE_PTR freeList;
++}
++gcskHEAP;
++
++struct _gckHEAP
++{
++ /* Object. */
++ gcsOBJECT object;
++
++ /* Pointer to a gckOS object. */
++ gckOS os;
++
++ /* Locking mutex. */
++ gctPOINTER mutex;
++
++ /* Allocation parameters. */
++ gctSIZE_T allocationSize;
++
++ /* Heap list. */
++ gcskHEAP_PTR heap;
++#if gcmIS_DEBUG(gcdDEBUG_CODE)
++ gctUINT64 timeStamp;
++#endif
++
++#if VIVANTE_PROFILER || gcmIS_DEBUG(gcdDEBUG_CODE)
++ /* Profile information. */
++ gctUINT32 allocCount;
++ gctUINT64 allocBytes;
++ gctUINT64 allocBytesMax;
++ gctUINT64 allocBytesTotal;
++ gctUINT32 heapCount;
++ gctUINT32 heapCountMax;
++ gctUINT64 heapMemory;
++ gctUINT64 heapMemoryMax;
++#endif
++};
++
++/*******************************************************************************
++***** Static Support Functions *************************************************
++*******************************************************************************/
++
++#if gcmIS_DEBUG(gcdDEBUG_CODE)
++static gctSIZE_T
++_DumpHeap(
++ IN gcskHEAP_PTR Heap
++ )
++{
++ gctPOINTER p;
++ gctSIZE_T leaked = 0;
++
++ /* Start at first node. */
++ for (p = Heap + 1;;)
++ {
++ /* Convert the pointer. */
++ gcskNODE_PTR node = (gcskNODE_PTR) p;
++
++ /* Check if this is a used node. */
++ if (node->next == gcdIN_USE)
++ {
++ /* Print the leaking node. */
++ gcmkTRACE_ZONE(gcvLEVEL_WARNING, gcvZONE_HEAP,
++ "Detected leaking: node=0x%x bytes=%lu timeStamp=%llu "
++ "(%08X %c%c%c%c)",
++ node, node->bytes, node->timeStamp,
++ ((gctUINT32_PTR) (node + 1))[0],
++ gcmPRINTABLE(((gctUINT8_PTR) (node + 1))[0]),
++ gcmPRINTABLE(((gctUINT8_PTR) (node + 1))[1]),
++ gcmPRINTABLE(((gctUINT8_PTR) (node + 1))[2]),
++ gcmPRINTABLE(((gctUINT8_PTR) (node + 1))[3]));
++
++ /* Add leaking byte count. */
++ leaked += node->bytes;
++ }
++
++ /* Test for end of heap. */
++ if (node->bytes == 0)
++ {
++ break;
++ }
++
++ else
++ {
++ /* Move to next node. */
++ p = (gctUINT8_PTR) node + node->bytes;
++ }
++ }
++
++ /* Return the number of leaked bytes. */
++ return leaked;
++}
++#endif
++
++static gceSTATUS
++_CompactKernelHeap(
++ IN gckHEAP Heap
++ )
++{
++ gcskHEAP_PTR heap, next;
++ gctPOINTER p;
++ gcskHEAP_PTR freeList = gcvNULL;
++
++ gcmkHEADER_ARG("Heap=0x%x", Heap);
++
++ /* Walk all the heaps. */
++ for (heap = Heap->heap; heap != gcvNULL; heap = next)
++ {
++ gcskNODE_PTR lastFree = gcvNULL;
++
++ /* Zero out the free list. */
++ heap->freeList = gcvNULL;
++
++ /* Start at the first node. */
++ for (p = (gctUINT8_PTR) (heap + 1);;)
++ {
++ /* Convert the pointer. */
++ gcskNODE_PTR node = (gcskNODE_PTR) p;
++
++ gcmkASSERT(p <= (gctPOINTER) ((gctUINT8_PTR) (heap + 1) + heap->size));
++
++ /* Test if this node not used. */
++ if (node->next != gcdIN_USE)
++ {
++ /* Test if this is the end of the heap. */
++ if (node->bytes == 0)
++ {
++ break;
++ }
++
++ /* Test of this is the first free node. */
++ else if (lastFree == gcvNULL)
++ {
++ /* Initialzie the free list. */
++ heap->freeList = node;
++ lastFree = node;
++ }
++
++ else
++ {
++ /* Test if this free node is contiguous with the previous
++ ** free node. */
++ if ((gctUINT8_PTR) lastFree + lastFree->bytes == p)
++ {
++ /* Just increase the size of the previous free node. */
++ lastFree->bytes += node->bytes;
++ }
++ else
++ {
++ /* Add to linked list. */
++ lastFree->next = node;
++ lastFree = node;
++ }
++ }
++ }
++
++ /* Move to next node. */
++ p = (gctUINT8_PTR) node + node->bytes;
++ }
++
++ /* Mark the end of the chain. */
++ if (lastFree != gcvNULL)
++ {
++ lastFree->next = gcvNULL;
++ }
++
++ /* Get next heap. */
++ next = heap->next;
++
++ /* Check if the entire heap is free. */
++ if ((heap->freeList != gcvNULL)
++ && (heap->freeList->bytes == heap->size - gcmSIZEOF(gcskNODE))
++ )
++ {
++ /* Remove the heap from the linked list. */
++ if (heap->prev == gcvNULL)
++ {
++ Heap->heap = next;
++ }
++ else
++ {
++ heap->prev->next = next;
++ }
++
++ if (heap->next != gcvNULL)
++ {
++ heap->next->prev = heap->prev;
++ }
++
++#if VIVANTE_PROFILER || gcmIS_DEBUG(gcdDEBUG_CODE)
++ /* Update profiling. */
++ Heap->heapCount -= 1;
++ Heap->heapMemory -= heap->size + gcmSIZEOF(gcskHEAP);
++#endif
++
++ /* Add this heap to the list of heaps that need to be freed. */
++ heap->next = freeList;
++ freeList = heap;
++ }
++ }
++
++ if (freeList != gcvNULL)
++ {
++ /* Release the mutex, remove any chance for a dead lock. */
++ gcmkVERIFY_OK(
++ gckOS_ReleaseMutex(Heap->os, Heap->mutex));
++
++ /* Free all heaps in the free list. */
++ for (heap = freeList; heap != gcvNULL; heap = next)
++ {
++ /* Get pointer to the next heap. */
++ next = heap->next;
++
++ /* Free the heap. */
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HEAP,
++ "Freeing heap 0x%x (%lu bytes)",
++ heap, heap->size + gcmSIZEOF(gcskHEAP));
++ gcmkVERIFY_OK(gckOS_FreeMemory(Heap->os, heap));
++ }
++
++ /* Acquire the mutex again. */
++ gcmkVERIFY_OK(
++ gckOS_AcquireMutex(Heap->os, Heap->mutex, gcvINFINITE));
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++***** gckHEAP API Code *********************************************************
++*******************************************************************************/
++
++/*******************************************************************************
++**
++** gckHEAP_Construct
++**
++** Construct a new gckHEAP object.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gctSIZE_T AllocationSize
++** Minimum size per arena.
++**
++** OUTPUT:
++**
++** gckHEAP * Heap
++** Pointer to a variable that will hold the pointer to the gckHEAP
++** object.
++*/
++gceSTATUS
++gckHEAP_Construct(
++ IN gckOS Os,
++ IN gctSIZE_T AllocationSize,
++ OUT gckHEAP * Heap
++ )
++{
++ gceSTATUS status;
++ gckHEAP heap = gcvNULL;
++ gctPOINTER pointer = gcvNULL;
++
++ gcmkHEADER_ARG("Os=0x%x AllocationSize=%lu", Os, AllocationSize);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Heap != gcvNULL);
++
++ /* Allocate the gckHEAP object. */
++ gcmkONERROR(gckOS_AllocateMemory(Os,
++ gcmSIZEOF(struct _gckHEAP),
++ &pointer));
++
++ heap = pointer;
++
++ /* Initialize the gckHEAP object. */
++ heap->object.type = gcvOBJ_HEAP;
++ heap->os = Os;
++ heap->allocationSize = AllocationSize;
++ heap->heap = gcvNULL;
++#if gcmIS_DEBUG(gcdDEBUG_CODE)
++ heap->timeStamp = 0;
++#endif
++
++#if VIVANTE_PROFILER || gcmIS_DEBUG(gcdDEBUG_CODE)
++ /* Zero the counters. */
++ heap->allocCount = 0;
++ heap->allocBytes = 0;
++ heap->allocBytesMax = 0;
++ heap->allocBytesTotal = 0;
++ heap->heapCount = 0;
++ heap->heapCountMax = 0;
++ heap->heapMemory = 0;
++ heap->heapMemoryMax = 0;
++#endif
++
++ /* Create the mutex. */
++ gcmkONERROR(gckOS_CreateMutex(Os, &heap->mutex));
++
++ /* Return the pointer to the gckHEAP object. */
++ *Heap = heap;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Heap=0x%x", *Heap);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Roll back. */
++ if (heap != gcvNULL)
++ {
++ /* Free the heap structure. */
++ gcmkVERIFY_OK(gckOS_FreeMemory(Os, heap));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHEAP_Destroy
++**
++** Destroy a gckHEAP object.
++**
++** INPUT:
++**
++** gckHEAP Heap
++** Pointer to a gckHEAP object to destroy.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckHEAP_Destroy(
++ IN gckHEAP Heap
++ )
++{
++ gcskHEAP_PTR heap;
++#if gcmIS_DEBUG(gcdDEBUG_CODE)
++ gctSIZE_T leaked = 0;
++#endif
++
++ gcmkHEADER_ARG("Heap=0x%x", Heap);
++
++ for (heap = Heap->heap; heap != gcvNULL; heap = Heap->heap)
++ {
++ /* Unlink heap from linked list. */
++ Heap->heap = heap->next;
++
++#if gcmIS_DEBUG(gcdDEBUG_CODE)
++ /* Check for leaked memory. */
++ leaked += _DumpHeap(heap);
++#endif
++
++ /* Free the heap. */
++ gcmkVERIFY_OK(gckOS_FreeMemory(Heap->os, heap));
++ }
++
++ /* Free the mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Heap->os, Heap->mutex));
++
++ /* Free the heap structure. */
++ gcmkVERIFY_OK(gckOS_FreeMemory(Heap->os, Heap));
++
++ /* Success. */
++#if gcmIS_DEBUG(gcdDEBUG_CODE)
++ gcmkFOOTER_ARG("leaked=%lu", leaked);
++#else
++ gcmkFOOTER_NO();
++#endif
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckHEAP_Allocate
++**
++** Allocate data from the heap.
++**
++** INPUT:
++**
++** gckHEAP Heap
++** Pointer to a gckHEAP object.
++**
++** IN gctSIZE_T Bytes
++** Number of byte to allocate.
++**
++** OUTPUT:
++**
++** gctPOINTER * Memory
++** Pointer to a variable that will hold the address of the allocated
++** memory.
++*/
++gceSTATUS
++gckHEAP_Allocate(
++ IN gckHEAP Heap,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Memory
++ )
++{
++ gctBOOL acquired = gcvFALSE;
++ gcskHEAP_PTR heap;
++ gceSTATUS status;
++ gctSIZE_T bytes;
++ gcskNODE_PTR node, used, prevFree = gcvNULL;
++ gctPOINTER memory = gcvNULL;
++
++ gcmkHEADER_ARG("Heap=0x%x Bytes=%lu", Heap, Bytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Heap, gcvOBJ_HEAP);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++ gcmkVERIFY_ARGUMENT(Memory != gcvNULL);
++
++ /* Determine number of bytes required for a node. */
++ bytes = gcmALIGN(Bytes + gcmSIZEOF(gcskNODE), 8);
++
++ /* Acquire the mutex. */
++ gcmkONERROR(
++ gckOS_AcquireMutex(Heap->os, Heap->mutex, gcvINFINITE));
++
++ acquired = gcvTRUE;
++
++ /* Check if this allocation is bigger than the default allocation size. */
++ if (bytes > Heap->allocationSize - gcmSIZEOF(gcskHEAP) - gcmSIZEOF(gcskNODE))
++ {
++ /* Adjust allocation size. */
++ Heap->allocationSize = bytes * 2;
++ }
++
++ else if (Heap->heap != gcvNULL)
++ {
++ gctINT i;
++
++ /* 2 retries, since we might need to compact. */
++ for (i = 0; i < 2; ++i)
++ {
++ /* Walk all the heaps. */
++ for (heap = Heap->heap; heap != gcvNULL; heap = heap->next)
++ {
++ /* Check if this heap has enough bytes to hold the request. */
++ if (bytes <= heap->size - gcmSIZEOF(gcskNODE))
++ {
++ prevFree = gcvNULL;
++
++ /* Walk the chain of free nodes. */
++ for (node = heap->freeList;
++ node != gcvNULL;
++ node = node->next
++ )
++ {
++ gcmkASSERT(node->next != gcdIN_USE);
++
++ /* Check if this free node has enough bytes. */
++ if (node->bytes >= bytes)
++ {
++ /* Use the node. */
++ goto UseNode;
++ }
++
++ /* Save current free node for linked list management. */
++ prevFree = node;
++ }
++ }
++ }
++
++ if (i == 0)
++ {
++ /* Compact the heap. */
++ gcmkVERIFY_OK(_CompactKernelHeap(Heap));
++
++#if gcmIS_DEBUG(gcdDEBUG_CODE)
++ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_HEAP,
++ "===== KERNEL HEAP =====");
++ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_HEAP,
++ "Number of allocations : %12u",
++ Heap->allocCount);
++ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_HEAP,
++ "Number of bytes allocated : %12llu",
++ Heap->allocBytes);
++ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_HEAP,
++ "Maximum allocation size : %12llu",
++ Heap->allocBytesMax);
++ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_HEAP,
++ "Total number of bytes allocated : %12llu",
++ Heap->allocBytesTotal);
++ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_HEAP,
++ "Number of heaps : %12u",
++ Heap->heapCount);
++ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_HEAP,
++ "Heap memory in bytes : %12llu",
++ Heap->heapMemory);
++ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_HEAP,
++ "Maximum number of heaps : %12u",
++ Heap->heapCountMax);
++ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_HEAP,
++ "Maximum heap memory in bytes : %12llu",
++ Heap->heapMemoryMax);
++#endif
++ }
++ }
++ }
++
++ /* Release the mutex. */
++ gcmkONERROR(
++ gckOS_ReleaseMutex(Heap->os, Heap->mutex));
++
++ acquired = gcvFALSE;
++
++ /* Allocate a new heap. */
++ gcmkONERROR(
++ gckOS_AllocateMemory(Heap->os,
++ Heap->allocationSize,
++ &memory));
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HEAP,
++ "Allocated heap 0x%x (%lu bytes)",
++ memory, Heap->allocationSize);
++
++ /* Acquire the mutex. */
++ gcmkONERROR(
++ gckOS_AcquireMutex(Heap->os, Heap->mutex, gcvINFINITE));
++
++ acquired = gcvTRUE;
++
++ /* Use the allocated memory as the heap. */
++ heap = (gcskHEAP_PTR) memory;
++
++ /* Insert this heap to the head of the chain. */
++ heap->next = Heap->heap;
++ heap->prev = gcvNULL;
++ heap->size = Heap->allocationSize - gcmSIZEOF(gcskHEAP);
++
++ if (heap->next != gcvNULL)
++ {
++ heap->next->prev = heap;
++ }
++ Heap->heap = heap;
++
++ /* Mark the end of the heap. */
++ node = (gcskNODE_PTR) ( (gctUINT8_PTR) heap
++ + Heap->allocationSize
++ - gcmSIZEOF(gcskNODE)
++ );
++ node->bytes = 0;
++ node->next = gcvNULL;
++
++ /* Create a free list. */
++ node = (gcskNODE_PTR) (heap + 1);
++ heap->freeList = node;
++
++ /* Initialize the free list. */
++ node->bytes = heap->size - gcmSIZEOF(gcskNODE);
++ node->next = gcvNULL;
++
++ /* No previous free. */
++ prevFree = gcvNULL;
++
++#if VIVANTE_PROFILER || gcmIS_DEBUG(gcdDEBUG_CODE)
++ /* Update profiling. */
++ Heap->heapCount += 1;
++ Heap->heapMemory += Heap->allocationSize;
++
++ if (Heap->heapCount > Heap->heapCountMax)
++ {
++ Heap->heapCountMax = Heap->heapCount;
++ }
++ if (Heap->heapMemory > Heap->heapMemoryMax)
++ {
++ Heap->heapMemoryMax = Heap->heapMemory;
++ }
++#endif
++
++UseNode:
++ /* Verify some stuff. */
++ gcmkASSERT(heap != gcvNULL);
++ gcmkASSERT(node != gcvNULL);
++ gcmkASSERT(node->bytes >= bytes);
++
++ if (heap->prev != gcvNULL)
++ {
++ /* Unlink the heap from the linked list. */
++ heap->prev->next = heap->next;
++ if (heap->next != gcvNULL)
++ {
++ heap->next->prev = heap->prev;
++ }
++
++ /* Move the heap to the front of the list. */
++ heap->next = Heap->heap;
++ heap->prev = gcvNULL;
++ Heap->heap = heap;
++ heap->next->prev = heap;
++ }
++
++ /* Check if there is enough free space left after usage for another free
++ ** node. */
++ if (node->bytes - bytes >= gcmSIZEOF(gcskNODE))
++ {
++ /* Allocated used space from the back of the free list. */
++ used = (gcskNODE_PTR) ((gctUINT8_PTR) node + node->bytes - bytes);
++
++ /* Adjust the number of free bytes. */
++ node->bytes -= bytes;
++ gcmkASSERT(node->bytes >= gcmSIZEOF(gcskNODE));
++ }
++ else
++ {
++ /* Remove this free list from the chain. */
++ if (prevFree == gcvNULL)
++ {
++ heap->freeList = node->next;
++ }
++ else
++ {
++ prevFree->next = node->next;
++ }
++
++ /* Consume the entire free node. */
++ used = (gcskNODE_PTR) node;
++ bytes = node->bytes;
++ }
++
++ /* Mark node as used. */
++ used->bytes = bytes;
++ used->next = gcdIN_USE;
++#if gcmIS_DEBUG(gcdDEBUG_CODE)
++ used->timeStamp = ++Heap->timeStamp;
++#endif
++
++#if VIVANTE_PROFILER || gcmIS_DEBUG(gcdDEBUG_CODE)
++ /* Update profile counters. */
++ Heap->allocCount += 1;
++ Heap->allocBytes += bytes;
++ Heap->allocBytesMax = gcmMAX(Heap->allocBytes, Heap->allocBytesMax);
++ Heap->allocBytesTotal += bytes;
++#endif
++
++ /* Release the mutex. */
++ gcmkVERIFY_OK(
++ gckOS_ReleaseMutex(Heap->os, Heap->mutex));
++
++ /* Return pointer to memory. */
++ *Memory = used + 1;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Memory=0x%x", *Memory);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ /* Release the mutex. */
++ gcmkVERIFY_OK(
++ gckOS_ReleaseMutex(Heap->os, Heap->mutex));
++ }
++
++ if (memory != gcvNULL)
++ {
++ /* Free the heap memory. */
++ gckOS_FreeMemory(Heap->os, memory);
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHEAP_Free
++**
++** Free allocated memory from the heap.
++**
++** INPUT:
++**
++** gckHEAP Heap
++** Pointer to a gckHEAP object.
++**
++** IN gctPOINTER Memory
++** Pointer to memory to free.
++**
++** OUTPUT:
++**
++** NOTHING.
++*/
++gceSTATUS
++gckHEAP_Free(
++ IN gckHEAP Heap,
++ IN gctPOINTER Memory
++ )
++{
++ gcskNODE_PTR node;
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Heap=0x%x Memory=0x%x", Heap, Memory);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Heap, gcvOBJ_HEAP);
++ gcmkVERIFY_ARGUMENT(Memory != gcvNULL);
++
++ /* Acquire the mutex. */
++ gcmkONERROR(
++ gckOS_AcquireMutex(Heap->os, Heap->mutex, gcvINFINITE));
++
++ /* Pointer to structure. */
++ node = (gcskNODE_PTR) Memory - 1;
++
++ /* Mark the node as freed. */
++ node->next = gcvNULL;
++
++#if VIVANTE_PROFILER || gcmIS_DEBUG(gcdDEBUG_CODE)
++ /* Update profile counters. */
++ Heap->allocBytes -= node->bytes;
++#endif
++
++ /* Release the mutex. */
++ gcmkVERIFY_OK(
++ gckOS_ReleaseMutex(Heap->os, Heap->mutex));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++#if VIVANTE_PROFILER
++gceSTATUS
++gckHEAP_ProfileStart(
++ IN gckHEAP Heap
++ )
++{
++ gcmkHEADER_ARG("Heap=0x%x", Heap);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Heap, gcvOBJ_HEAP);
++
++ /* Zero the counters. */
++ Heap->allocCount = 0;
++ Heap->allocBytes = 0;
++ Heap->allocBytesMax = 0;
++ Heap->allocBytesTotal = 0;
++ Heap->heapCount = 0;
++ Heap->heapCountMax = 0;
++ Heap->heapMemory = 0;
++ Heap->heapMemoryMax = 0;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckHEAP_ProfileEnd(
++ IN gckHEAP Heap,
++ IN gctCONST_STRING Title
++ )
++{
++ gcmkHEADER_ARG("Heap=0x%x Title=0x%x", Heap, Title);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Heap, gcvOBJ_HEAP);
++ gcmkVERIFY_ARGUMENT(Title != gcvNULL);
++
++ gcmkPRINT("");
++ gcmkPRINT("=====[ HEAP - %s ]=====", Title);
++ gcmkPRINT("Number of allocations : %12u", Heap->allocCount);
++ gcmkPRINT("Number of bytes allocated : %12llu", Heap->allocBytes);
++ gcmkPRINT("Maximum allocation size : %12llu", Heap->allocBytesMax);
++ gcmkPRINT("Total number of bytes allocated : %12llu", Heap->allocBytesTotal);
++ gcmkPRINT("Number of heaps : %12u", Heap->heapCount);
++ gcmkPRINT("Heap memory in bytes : %12llu", Heap->heapMemory);
++ gcmkPRINT("Maximum number of heaps : %12u", Heap->heapCountMax);
++ gcmkPRINT("Maximum heap memory in bytes : %12llu", Heap->heapMemoryMax);
++ gcmkPRINT("==============================================");
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++#endif /* VIVANTE_PROFILER */
++
++/*******************************************************************************
++***** Test Code ****************************************************************
++*******************************************************************************/
++
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_interrupt_vg.c linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_interrupt_vg.c
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_interrupt_vg.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_interrupt_vg.c 2015-07-27 23:13:06.194879670 +0200
+@@ -0,0 +1,877 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_precomp.h"
++
++#if gcdENABLE_VG
++
++/******************************************************************************\
++*********************** Support Functions and Definitions **********************
++\******************************************************************************/
++
++/* Interruot statistics will be accumulated if not zero. */
++#define gcmENABLE_INTERRUPT_STATISTICS 0
++
++#define _GC_OBJ_ZONE gcvZONE_INTERRUPT
++
++/* Object structure. */
++struct _gckVGINTERRUPT
++{
++ /* Object. */
++ gcsOBJECT object;
++
++ /* gckVGKERNEL pointer. */
++ gckVGKERNEL kernel;
++
++ /* gckOS pointer. */
++ gckOS os;
++
++ /* Interrupt handlers. */
++ gctINTERRUPT_HANDLER handlers[32];
++
++ /* Main interrupt handler thread. */
++ gctTHREAD handler;
++ gctBOOL terminate;
++
++ /* Interrupt FIFO. */
++ gctSEMAPHORE fifoValid;
++ gctUINT32 fifo[256];
++ gctUINT fifoItems;
++ gctUINT8 head;
++ gctUINT8 tail;
++
++ /* Interrupt statistics. */
++#if gcmENABLE_INTERRUPT_STATISTICS
++ gctUINT maxFifoItems;
++ gctUINT fifoOverflow;
++ gctUINT maxSimultaneous;
++ gctUINT multipleCount;
++#endif
++};
++
++
++/*******************************************************************************
++**
++** _ProcessInterrupt
++**
++** The interrupt processor.
++**
++** INPUT:
++**
++** ThreadParameter
++** Pointer to the gckVGINTERRUPT object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++#if gcmENABLE_INTERRUPT_STATISTICS
++static void
++_ProcessInterrupt(
++ gckVGINTERRUPT Interrupt,
++ gctUINT_PTR TriggeredCount
++ )
++#else
++static void
++_ProcessInterrupt(
++ gckVGINTERRUPT Interrupt
++ )
++#endif
++{
++ gceSTATUS status;
++ gctUINT32 triggered;
++ gctUINT i;
++
++ /* Advance to the next entry. */
++ Interrupt->tail += 1;
++ Interrupt->fifoItems -= 1;
++
++ /* Get the interrupt value. */
++ triggered = Interrupt->fifo[Interrupt->tail];
++ gcmkASSERT(triggered != 0);
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ "%s: triggered=0x%08X\n",
++ __FUNCTION__,
++ triggered
++ );
++
++ /* Walk through all possible interrupts. */
++ for (i = 0; i < gcmSIZEOF(Interrupt->handlers); i += 1)
++ {
++ /* Test if interrupt happened. */
++ if ((triggered & 1) == 1)
++ {
++#if gcmENABLE_INTERRUPT_STATISTICS
++ if (TriggeredCount != gcvNULL)
++ {
++ (* TriggeredCount) += 1;
++ }
++#endif
++
++ /* Make sure we have valid handler. */
++ if (Interrupt->handlers[i] == gcvNULL)
++ {
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s: Interrupt %d isn't registered.\n",
++ __FUNCTION__, i
++ );
++ }
++ else
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ "%s: interrupt=%d\n",
++ __FUNCTION__,
++ i
++ );
++
++ /* Call the handler. */
++ status = Interrupt->handlers[i] (Interrupt->kernel);
++
++ if (gcmkIS_ERROR(status))
++ {
++ /* Failed to signal the semaphore. */
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s: Error %d incrementing the semaphore #%d.\n",
++ __FUNCTION__, status, i
++ );
++ }
++ }
++ }
++
++ /* Next interrupt. */
++ triggered >>= 1;
++
++ /* No more interrupts to handle? */
++ if (triggered == 0)
++ {
++ break;
++ }
++ }
++}
++
++
++/*******************************************************************************
++**
++** _MainInterruptHandler
++**
++** The main interrupt thread serves the interrupt FIFO and calls registered
++** handlers for the interrupts that occured. The handlers are called in the
++** sequence interrupts occured with the exception when multiple interrupts
++** occured at the same time. In that case the handler calls are "sorted" by
++** the interrupt number therefore giving the interrupts with lower numbers
++** higher priority.
++**
++** INPUT:
++**
++** ThreadParameter
++** Pointer to the gckVGINTERRUPT object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++static gctTHREADFUNCRESULT gctTHREADFUNCTYPE
++_MainInterruptHandler(
++ gctTHREADFUNCPARAMETER ThreadParameter
++ )
++{
++ gceSTATUS status;
++ gckVGINTERRUPT interrupt;
++
++#if gcmENABLE_INTERRUPT_STATISTICS
++ gctUINT count;
++#endif
++
++ /* Cast the object. */
++ interrupt = (gckVGINTERRUPT) ThreadParameter;
++
++ /* Enter the loop. */
++ while (gcvTRUE)
++ {
++ /* Wait for an interrupt. */
++ status = gckOS_DecrementSemaphore(interrupt->os, interrupt->fifoValid);
++
++ /* Error? */
++ if (gcmkIS_ERROR(status))
++ {
++ break;
++ }
++
++ /* System termination request? */
++ if (status == gcvSTATUS_TERMINATE)
++ {
++ break;
++ }
++
++ /* Driver is shutting down? */
++ if (interrupt->terminate)
++ {
++ break;
++ }
++
++#if gcmENABLE_INTERRUPT_STATISTICS
++ /* Reset triggered count. */
++ count = 0;
++
++ /* Process the interrupt. */
++ _ProcessInterrupt(interrupt, &count);
++
++ /* Update conters. */
++ if (count > interrupt->maxSimultaneous)
++ {
++ interrupt->maxSimultaneous = count;
++ }
++
++ if (count > 1)
++ {
++ interrupt->multipleCount += 1;
++ }
++#else
++ /* Process the interrupt. */
++ _ProcessInterrupt(interrupt);
++#endif
++ }
++
++ return 0;
++}
++
++
++/*******************************************************************************
++**
++** _StartInterruptHandler / _StopInterruptHandler
++**
++** Main interrupt handler routine control.
++**
++** INPUT:
++**
++** ThreadParameter
++** Pointer to the gckVGINTERRUPT object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++static gceSTATUS
++_StartInterruptHandler(
++ gckVGINTERRUPT Interrupt
++ )
++{
++ gceSTATUS status, last;
++
++ do
++ {
++ /* Objects must not be already created. */
++ gcmkASSERT(Interrupt->fifoValid == gcvNULL);
++ gcmkASSERT(Interrupt->handler == gcvNULL);
++
++ /* Reset the termination request. */
++ Interrupt->terminate = gcvFALSE;
++
++#if !gcdENABLE_INFINITE_SPEED_HW
++ /* Construct the fifo semaphore. */
++ gcmkERR_BREAK(gckOS_CreateSemaphoreVG(
++ Interrupt->os, &Interrupt->fifoValid
++ ));
++
++ /* Start the interrupt handler thread. */
++ gcmkERR_BREAK(gckOS_StartThread(
++ Interrupt->os,
++ _MainInterruptHandler,
++ Interrupt,
++ &Interrupt->handler
++ ));
++#endif
++
++ /* Success. */
++ return gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ /* Roll back. */
++ if (Interrupt->fifoValid != gcvNULL)
++ {
++ gcmkCHECK_STATUS(gckOS_DestroySemaphore(
++ Interrupt->os, Interrupt->fifoValid
++ ));
++
++ Interrupt->fifoValid = gcvNULL;
++ }
++
++ /* Return the status. */
++ return status;
++}
++
++static gceSTATUS
++_StopInterruptHandler(
++ gckVGINTERRUPT Interrupt
++ )
++{
++ gceSTATUS status;
++
++ do
++ {
++ /* Does the thread exist? */
++ if (Interrupt->handler == gcvNULL)
++ {
++ /* The semaphore must be NULL as well. */
++ gcmkASSERT(Interrupt->fifoValid == gcvNULL);
++
++ /* Success. */
++ status = gcvSTATUS_OK;
++ break;
++ }
++
++ /* The semaphore must exist as well. */
++ gcmkASSERT(Interrupt->fifoValid != gcvNULL);
++
++ /* Set the termination request. */
++ Interrupt->terminate = gcvTRUE;
++
++ /* Unlock the thread. */
++ gcmkERR_BREAK(gckOS_IncrementSemaphore(
++ Interrupt->os, Interrupt->fifoValid
++ ));
++
++ /* Wait until the thread quits. */
++ gcmkERR_BREAK(gckOS_StopThread(
++ Interrupt->os,
++ Interrupt->handler
++ ));
++
++ /* Destroy the semaphore. */
++ gcmkERR_BREAK(gckOS_DestroySemaphore(
++ Interrupt->os, Interrupt->fifoValid
++ ));
++
++ /* Reset handles. */
++ Interrupt->handler = gcvNULL;
++ Interrupt->fifoValid = gcvNULL;
++ }
++ while (gcvFALSE);
++
++ /* Return the status. */
++ return status;
++}
++
++
++/******************************************************************************\
++***************************** Interrupt Object API *****************************
++\******************************************************************************/
++
++/*******************************************************************************
++**
++** gckVGINTERRUPT_Construct
++**
++** Construct an interrupt object.
++**
++** INPUT:
++**
++** Kernel
++** Pointer to the gckVGKERNEL object.
++**
++** OUTPUT:
++**
++** Interrupt
++** Pointer to the new gckVGINTERRUPT object.
++*/
++
++gceSTATUS
++gckVGINTERRUPT_Construct(
++ IN gckVGKERNEL Kernel,
++ OUT gckVGINTERRUPT * Interrupt
++ )
++{
++ gceSTATUS status;
++ gckVGINTERRUPT interrupt = gcvNULL;
++
++ gcmkHEADER_ARG("Kernel=0x%x Interrupt=0x%x", Kernel, Interrupt);
++
++ /* Verify argeuments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(Interrupt != gcvNULL);
++
++ do
++ {
++ /* Allocate the gckVGINTERRUPT structure. */
++ gcmkERR_BREAK(gckOS_Allocate(
++ Kernel->os,
++ gcmSIZEOF(struct _gckVGINTERRUPT),
++ (gctPOINTER *) &interrupt
++ ));
++
++ /* Reset the object data. */
++ gcmkVERIFY_OK(gckOS_ZeroMemory(
++ interrupt, gcmSIZEOF(struct _gckVGINTERRUPT)
++ ));
++
++ /* Initialize the object. */
++ interrupt->object.type = gcvOBJ_INTERRUPT;
++
++ /* Initialize the object pointers. */
++ interrupt->kernel = Kernel;
++ interrupt->os = Kernel->os;
++
++ /* Initialize the current FIFO position. */
++ interrupt->head = (gctUINT8)~0;
++ interrupt->tail = (gctUINT8)~0;
++
++ /* Start the thread. */
++ gcmkERR_BREAK(_StartInterruptHandler(interrupt));
++
++ /* Return interrupt object. */
++ *Interrupt = interrupt;
++
++ gcmkFOOTER_ARG("*Interrup=0x%x", *Interrupt);
++ /* Success. */
++ return gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ /* Roll back. */
++ if (interrupt != gcvNULL)
++ {
++ /* Free the gckVGINTERRUPT structure. */
++ gcmkVERIFY_OK(gckOS_Free(interrupt->os, interrupt));
++ }
++
++ gcmkFOOTER();
++
++ /* Return the status. */
++ return status;
++}
++
++
++/*******************************************************************************
++**
++** gckVGINTERRUPT_Destroy
++**
++** Destroy an interrupt object.
++**
++** INPUT:
++**
++** Interrupt
++** Pointer to the gckVGINTERRUPT object to destroy.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++gceSTATUS
++gckVGINTERRUPT_Destroy(
++ IN gckVGINTERRUPT Interrupt
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Interrupt=0x%x", Interrupt);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Interrupt, gcvOBJ_INTERRUPT);
++
++ do
++ {
++ /* Stop the interrupt thread. */
++ gcmkERR_BREAK(_StopInterruptHandler(Interrupt));
++
++ /* Mark the object as unknown. */
++ Interrupt->object.type = gcvOBJ_UNKNOWN;
++
++ /* Free the gckVGINTERRUPT structure. */
++ gcmkERR_BREAK(gckOS_Free(Interrupt->os, Interrupt));
++ }
++ while (gcvFALSE);
++
++ gcmkFOOTER();
++
++ /* Return the status. */
++ return status;
++}
++
++
++/*******************************************************************************
++**
++** gckVGINTERRUPT_DumpState
++**
++** Print the current state of the interrupt manager.
++**
++** INPUT:
++**
++** Interrupt
++** Pointer to a gckVGINTERRUPT object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++#if gcvDEBUG
++gceSTATUS
++gckVGINTERRUPT_DumpState(
++ IN gckVGINTERRUPT Interrupt
++ )
++{
++ gcmkHEADER_ARG("Interrupt=0x%x", Interrupt);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Interrupt, gcvOBJ_INTERRUPT);
++
++ /* Print the header. */
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ "%s: INTERRUPT OBJECT STATUS\n",
++ __FUNCTION__
++ );
++
++ /* Print statistics. */
++#if gcmENABLE_INTERRUPT_STATISTICS
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ " Maximum number of FIFO items accumulated at a single time: %d\n",
++ Interrupt->maxFifoItems
++ );
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ " Interrupt FIFO overflow happened times: %d\n",
++ Interrupt->fifoOverflow
++ );
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ " Maximum number of interrupts simultaneously generated: %d\n",
++ Interrupt->maxSimultaneous
++ );
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ " Number of times when there were multiple interrupts generated: %d\n",
++ Interrupt->multipleCount
++ );
++#endif
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ " The current number of entries in the FIFO: %d\n",
++ Interrupt->fifoItems
++ );
++
++ /* Print the FIFO contents. */
++ if (Interrupt->fifoItems != 0)
++ {
++ gctUINT8 index;
++ gctUINT8 last;
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ " FIFO current contents:\n"
++ );
++
++ /* Get the current pointers. */
++ index = Interrupt->tail;
++ last = Interrupt->head;
++
++ while (index != last)
++ {
++ /* Advance to the next entry. */
++ index += 1;
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ " %d: 0x%08X\n",
++ index, Interrupt->fifo[index]
++ );
++ }
++ }
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++#endif
++
++
++/*******************************************************************************
++**
++** gckVGINTERRUPT_Enable
++**
++** Enable the specified interrupt.
++**
++** INPUT:
++**
++** Interrupt
++** Pointer to a gckVGINTERRUPT object.
++**
++** Id
++** Pointer to the variable that holds the interrupt number to be
++** registered in range 0..31.
++** If the value is less then 0, gckVGINTERRUPT_Enable will attempt
++** to find an unused interrupt. If such interrupt is found, the number
++** will be assigned to the variable if the functuion call succeedes.
++**
++** Handler
++** Pointer to the handler to register for the interrupt.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++gceSTATUS
++gckVGINTERRUPT_Enable(
++ IN gckVGINTERRUPT Interrupt,
++ IN OUT gctINT32_PTR Id,
++ IN gctINTERRUPT_HANDLER Handler
++ )
++{
++ gceSTATUS status;
++ gctINT32 i;
++
++ gcmkHEADER_ARG("Interrupt=0x%x Id=0x%x Handler=0x%x", Interrupt, Id, Handler);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Interrupt, gcvOBJ_INTERRUPT);
++ gcmkVERIFY_ARGUMENT(Id != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Handler != gcvNULL);
++
++ do
++ {
++ /* See if we need to allocate an ID. */
++ if (*Id < 0)
++ {
++ /* Find the first unused interrupt handler. */
++ for (i = 0; i < gcmCOUNTOF(Interrupt->handlers); ++i)
++ {
++ if (Interrupt->handlers[i] == gcvNULL)
++ {
++ break;
++ }
++ }
++
++ /* No unused innterrupts? */
++ if (i == gcmCOUNTOF(Interrupt->handlers))
++ {
++ status = gcvSTATUS_OUT_OF_RESOURCES;
++ break;
++ }
++
++ /* Update the interrupt ID. */
++ *Id = i;
++ }
++
++ /* Make sure the ID is in range. */
++ else if (*Id >= gcmCOUNTOF(Interrupt->handlers))
++ {
++ status = gcvSTATUS_INVALID_ARGUMENT;
++ break;
++ }
++
++ /* Set interrupt handler. */
++ Interrupt->handlers[*Id] = Handler;
++
++ /* Success. */
++ status = gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ gcmkFOOTER();
++ /* Return the status. */
++ return status;
++}
++
++
++/*******************************************************************************
++**
++** gckVGINTERRUPT_Disable
++**
++** Disable the specified interrupt.
++**
++** INPUT:
++**
++** Interrupt
++** Pointer to a gckVGINTERRUPT object.
++**
++** Id
++** Interrupt number to be disabled in range 0..31.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++gceSTATUS
++gckVGINTERRUPT_Disable(
++ IN gckVGINTERRUPT Interrupt,
++ IN gctINT32 Id
++ )
++{
++ gcmkHEADER_ARG("Interrupt=0x%x Id=0x%x", Interrupt, Id);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Interrupt, gcvOBJ_INTERRUPT);
++ gcmkVERIFY_ARGUMENT((Id >= 0) && (Id < gcmCOUNTOF(Interrupt->handlers)));
++
++ /* Reset interrupt handler. */
++ Interrupt->handlers[Id] = gcvNULL;
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++
++/*******************************************************************************
++**
++** gckVGINTERRUPT_Enque
++**
++** Read the interrupt status register and put the value in the interrupt FIFO.
++**
++** INPUT:
++**
++** Interrupt
++** Pointer to a gckVGINTERRUPT object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++#ifndef __QNXNTO__
++gceSTATUS
++gckVGINTERRUPT_Enque(
++ IN gckVGINTERRUPT Interrupt
++ )
++#else
++gceSTATUS
++gckVGINTERRUPT_Enque(
++ IN gckVGINTERRUPT Interrupt,
++ OUT gckOS *Os,
++ OUT gctSEMAPHORE *Semaphore
++ )
++#endif
++{
++ gceSTATUS status;
++ gctUINT32 triggered;
++
++ gcmkHEADER_ARG("Interrupt=0x%x", Interrupt);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Interrupt, gcvOBJ_INTERRUPT);
++
++#ifdef __QNXNTO__
++ *Os = gcvNULL;
++ *Semaphore = gcvNULL;
++#endif
++
++ do
++ {
++ /* Read interrupt status register. */
++ gcmkERR_BREAK(gckVGHARDWARE_ReadInterrupt(
++ Interrupt->kernel->hardware, &triggered
++ ));
++
++ /* Mask out TS overflow interrupt */
++ triggered &= 0xfffffffe;
++
++ /* No interrupts to process? */
++ if (triggered == 0)
++ {
++ status = gcvSTATUS_NOT_OUR_INTERRUPT;
++ break;
++ }
++
++ /* FIFO overflow? */
++ if (Interrupt->fifoItems == gcmCOUNTOF(Interrupt->fifo))
++ {
++#if gcmENABLE_INTERRUPT_STATISTICS
++ Interrupt->fifoOverflow += 1;
++#endif
++
++ /* OR the interrupt with the last value in the FIFO. */
++ Interrupt->fifo[Interrupt->head] |= triggered;
++
++ /* Success (kind of). */
++ status = gcvSTATUS_OK;
++ }
++ else
++ {
++ /* Advance to the next entry. */
++ Interrupt->head += 1;
++ Interrupt->fifoItems += 1;
++
++#if gcmENABLE_INTERRUPT_STATISTICS
++ if (Interrupt->fifoItems > Interrupt->maxFifoItems)
++ {
++ Interrupt->maxFifoItems = Interrupt->fifoItems;
++ }
++#endif
++
++ /* Set the new value. */
++ Interrupt->fifo[Interrupt->head] = triggered;
++
++#ifndef __QNXNTO__
++ /* Increment the FIFO semaphore. */
++ gcmkERR_BREAK(gckOS_IncrementSemaphore(
++ Interrupt->os, Interrupt->fifoValid
++ ));
++#else
++ *Os = Interrupt->os;
++ *Semaphore = Interrupt->fifoValid;
++#endif
++
++ /* Windows kills our threads prematurely when the application
++ exists. Verify here that the thread is still alive. */
++ status = gckOS_VerifyThread(Interrupt->os, Interrupt->handler);
++
++ /* Has the thread been prematurely terminated? */
++ if (status != gcvSTATUS_OK)
++ {
++ /* Process all accumulated interrupts. */
++ while (Interrupt->head != Interrupt->tail)
++ {
++#if gcmENABLE_INTERRUPT_STATISTICS
++ /* Process the interrupt. */
++ _ProcessInterrupt(Interrupt, gcvNULL);
++#else
++ /* Process the interrupt. */
++ _ProcessInterrupt(Interrupt);
++#endif
++ }
++
++ /* Set success. */
++ status = gcvSTATUS_OK;
++ }
++ }
++ }
++ while (gcvFALSE);
++
++ gcmkFOOTER();
++ /* Return status. */
++ return status;
++}
++
++#endif /* gcdENABLE_VG */
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_mmu.c linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_mmu.c
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_mmu.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_mmu.c 2015-07-27 23:13:06.194879670 +0200
+@@ -0,0 +1,1982 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_precomp.h"
++
++#define _GC_OBJ_ZONE gcvZONE_MMU
++
++typedef enum _gceMMU_TYPE
++{
++ gcvMMU_USED = (0 << 4),
++ gcvMMU_SINGLE = (1 << 4),
++ gcvMMU_FREE = (2 << 4),
++}
++gceMMU_TYPE;
++
++#define gcmENTRY_TYPE(x) (x & 0xF0)
++
++#define gcdMMU_TABLE_DUMP 0
++
++#define gcdUSE_MMU_EXCEPTION 0
++
++/*
++ gcdMMU_CLEAR_VALUE
++
++ The clear value for the entry of the old MMU.
++*/
++#ifndef gcdMMU_CLEAR_VALUE
++# define gcdMMU_CLEAR_VALUE 0x00000ABC
++#endif
++
++/* VIV: Start GPU address for gcvSURF_VERTEX. */
++#define gcdVERTEX_START (128 << 10)
++
++typedef struct _gcsMMU_STLB *gcsMMU_STLB_PTR;
++
++typedef struct _gcsMMU_STLB
++{
++ gctPHYS_ADDR physical;
++ gctUINT32_PTR logical;
++ gctSIZE_T size;
++ gctUINT32 physBase;
++ gctSIZE_T pageCount;
++ gctUINT32 mtlbIndex;
++ gctUINT32 mtlbEntryNum;
++ gcsMMU_STLB_PTR next;
++} gcsMMU_STLB;
++
++#if gcdSHARED_PAGETABLE
++typedef struct _gcsSharedPageTable * gcsSharedPageTable_PTR;
++typedef struct _gcsSharedPageTable
++{
++ /* Shared gckMMU object. */
++ gckMMU mmu;
++
++ /* Hardwares which use this shared pagetable. */
++ gckHARDWARE hardwares[gcdMAX_GPU_COUNT];
++
++ /* Number of cores use this shared pagetable. */
++ gctUINT32 reference;
++}
++gcsSharedPageTable;
++
++static gcsSharedPageTable_PTR sharedPageTable = gcvNULL;
++#endif
++
++#if gcdMIRROR_PAGETABLE
++typedef struct _gcsMirrorPageTable * gcsMirrorPageTable_PTR;
++typedef struct _gcsMirrorPageTable
++{
++ /* gckMMU objects. */
++ gckMMU mmus[gcdMAX_GPU_COUNT];
++
++ /* Hardwares which use this shared pagetable. */
++ gckHARDWARE hardwares[gcdMAX_GPU_COUNT];
++
++ /* Number of cores use this shared pagetable. */
++ gctUINT32 reference;
++}
++gcsMirrorPageTable;
++
++static gcsMirrorPageTable_PTR mirrorPageTable = gcvNULL;
++static gctPOINTER mirrorPageTableMutex = gcvNULL;
++#endif
++
++typedef struct _gcsDynamicSpaceNode * gcsDynamicSpaceNode_PTR;
++typedef struct _gcsDynamicSpaceNode
++{
++ gctUINT32 start;
++ gctINT32 entries;
++}
++gcsDynamicSpaceNode;
++
++static void
++_WritePageEntry(
++ IN gctUINT32_PTR PageEntry,
++ IN gctUINT32 EntryValue
++ )
++{
++ static gctUINT16 data = 0xff00;
++
++ if (*(gctUINT8 *)&data == 0xff)
++ {
++ *PageEntry = gcmSWAB32(EntryValue);
++ }
++ else
++ {
++ *PageEntry = EntryValue;
++ }
++}
++
++static gctUINT32
++_ReadPageEntry(
++ IN gctUINT32_PTR PageEntry
++ )
++{
++ static gctUINT16 data = 0xff00;
++ gctUINT32 entryValue;
++
++ if (*(gctUINT8 *)&data == 0xff)
++ {
++ entryValue = *PageEntry;
++ return gcmSWAB32(entryValue);
++ }
++ else
++ {
++ return *PageEntry;
++ }
++}
++
++static gceSTATUS
++_FillPageTable(
++ IN gctUINT32_PTR PageTable,
++ IN gctUINT32 PageCount,
++ IN gctUINT32 EntryValue
++)
++{
++ gctUINT i;
++
++ for (i = 0; i < PageCount; i++)
++ {
++ _WritePageEntry(PageTable + i, EntryValue);
++ }
++
++ return gcvSTATUS_OK;
++}
++
++static gceSTATUS
++_Link(
++ IN gckMMU Mmu,
++ IN gctUINT32 Index,
++ IN gctUINT32 Next
++ )
++{
++ if (Index >= Mmu->pageTableEntries)
++ {
++ /* Just move heap pointer. */
++ Mmu->heapList = Next;
++ }
++ else
++ {
++ /* Address page table. */
++ gctUINT32_PTR pageTable = Mmu->pageTableLogical;
++
++ /* Dispatch on node type. */
++ switch (gcmENTRY_TYPE(_ReadPageEntry(&pageTable[Index])))
++ {
++ case gcvMMU_SINGLE:
++ /* Set single index. */
++ _WritePageEntry(&pageTable[Index], (Next << 8) | gcvMMU_SINGLE);
++ break;
++
++ case gcvMMU_FREE:
++ /* Set index. */
++ _WritePageEntry(&pageTable[Index + 1], Next);
++ break;
++
++ default:
++ gcmkFATAL("MMU table correcupted at index %u!", Index);
++ return gcvSTATUS_HEAP_CORRUPTED;
++ }
++ }
++
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++static gceSTATUS
++_AddFree(
++ IN gckMMU Mmu,
++ IN gctUINT32 Index,
++ IN gctUINT32 Node,
++ IN gctUINT32 Count
++ )
++{
++ gctUINT32_PTR pageTable = Mmu->pageTableLogical;
++
++ if (Count == 1)
++ {
++ /* Initialize a single page node. */
++ _WritePageEntry(pageTable + Node, (~((1U<<8)-1)) | gcvMMU_SINGLE);
++ }
++ else
++ {
++ /* Initialize the node. */
++ _WritePageEntry(pageTable + Node + 0, (Count << 8) | gcvMMU_FREE);
++ _WritePageEntry(pageTable + Node + 1, ~0U);
++ }
++
++ /* Append the node. */
++ return _Link(Mmu, Index, Node);
++}
++
++static gceSTATUS
++_Collect(
++ IN gckMMU Mmu
++ )
++{
++ gctUINT32_PTR pageTable = Mmu->pageTableLogical;
++ gceSTATUS status;
++ gctUINT32 i, previous, start = 0, count = 0;
++
++ previous = Mmu->heapList = ~0U;
++ Mmu->freeNodes = gcvFALSE;
++
++ /* Walk the entire page table. */
++ for (i = 0; i < Mmu->pageTableEntries; ++i)
++ {
++ /* Dispatch based on type of page. */
++ switch (gcmENTRY_TYPE(_ReadPageEntry(&pageTable[i])))
++ {
++ case gcvMMU_USED:
++ /* Used page, so close any open node. */
++ if (count > 0)
++ {
++ /* Add the node. */
++ gcmkONERROR(_AddFree(Mmu, previous, start, count));
++
++ /* Reset the node. */
++ previous = start;
++ count = 0;
++ }
++ break;
++
++ case gcvMMU_SINGLE:
++ /* Single free node. */
++ if (count++ == 0)
++ {
++ /* Start a new node. */
++ start = i;
++ }
++ break;
++
++ case gcvMMU_FREE:
++ /* A free node. */
++ if (count == 0)
++ {
++ /* Start a new node. */
++ start = i;
++ }
++
++ /* Advance the count. */
++ count += _ReadPageEntry(&pageTable[i]) >> 8;
++
++ /* Advance the index into the page table. */
++ i += (_ReadPageEntry(&pageTable[i]) >> 8) - 1;
++ break;
++
++ default:
++ gcmkFATAL("MMU page table correcupted at index %u!", i);
++ return gcvSTATUS_HEAP_CORRUPTED;
++ }
++ }
++
++ /* See if we have an open node left. */
++ if (count > 0)
++ {
++ /* Add the node to the list. */
++ gcmkONERROR(_AddFree(Mmu, previous, start, count));
++ }
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_MMU,
++ "Performed a garbage collection of the MMU heap.");
++
++ /* Success. */
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the staus. */
++ return status;
++}
++
++static gctUINT32
++_SetPage(gctUINT32 PageAddress)
++{
++ return PageAddress
++ /* writable */
++ | (1 << 2)
++ /* Ignore exception */
++ | (0 << 1)
++ /* Present */
++ | (1 << 0);
++}
++
++static gceSTATUS
++_FillFlatMapping(
++ IN gckMMU Mmu,
++ IN gctUINT32 PhysBase,
++ OUT gctSIZE_T Size
++ )
++{
++ gceSTATUS status;
++ gctBOOL mutex = gcvFALSE;
++ gcsMMU_STLB_PTR head = gcvNULL, pre = gcvNULL;
++ gctUINT32 start = PhysBase & (~gcdMMU_PAGE_64K_MASK);
++ gctUINT32 end = (PhysBase + Size - 1) & (~gcdMMU_PAGE_64K_MASK);
++ gctUINT32 mStart = start >> gcdMMU_MTLB_SHIFT;
++ gctUINT32 mEnd = end >> gcdMMU_MTLB_SHIFT;
++ gctUINT32 sStart = (start & gcdMMU_STLB_64K_MASK) >> gcdMMU_STLB_64K_SHIFT;
++ gctUINT32 sEnd = (end & gcdMMU_STLB_64K_MASK) >> gcdMMU_STLB_64K_SHIFT;
++
++ /* Grab the mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(Mmu->os, Mmu->pageTableMutex, gcvINFINITE));
++ mutex = gcvTRUE;
++
++ while (mStart <= mEnd)
++ {
++ gcmkASSERT(mStart < gcdMMU_MTLB_ENTRY_NUM);
++ if (*(Mmu->mtlbLogical + mStart) == 0)
++ {
++ gcsMMU_STLB_PTR stlb;
++ gctPOINTER pointer = gcvNULL;
++ gctUINT32 last = (mStart == mEnd) ? sEnd : (gcdMMU_STLB_64K_ENTRY_NUM - 1);
++
++ gcmkONERROR(gckOS_Allocate(Mmu->os, sizeof(struct _gcsMMU_STLB), &pointer));
++ stlb = pointer;
++
++ stlb->mtlbEntryNum = 0;
++ stlb->next = gcvNULL;
++ stlb->physical = gcvNULL;
++ stlb->logical = gcvNULL;
++ stlb->size = gcdMMU_STLB_64K_SIZE;
++ stlb->pageCount = 0;
++
++ if (pre == gcvNULL)
++ {
++ pre = head = stlb;
++ }
++ else
++ {
++ gcmkASSERT(pre->next == gcvNULL);
++ pre->next = stlb;
++ pre = stlb;
++ }
++
++ gcmkONERROR(
++ gckOS_AllocateContiguous(Mmu->os,
++ gcvFALSE,
++ &stlb->size,
++ &stlb->physical,
++ (gctPOINTER)&stlb->logical));
++
++ gcmkONERROR(gckOS_ZeroMemory(stlb->logical, stlb->size));
++
++ gcmkONERROR(gckOS_GetPhysicalAddress(
++ Mmu->os,
++ stlb->logical,
++ &stlb->physBase));
++
++ if (stlb->physBase & (gcdMMU_STLB_64K_SIZE - 1))
++ {
++ gcmkONERROR(gcvSTATUS_NOT_ALIGNED);
++ }
++
++ _WritePageEntry(Mmu->mtlbLogical + mStart,
++ stlb->physBase
++ /* 64KB page size */
++ | (1 << 2)
++ /* Ignore exception */
++ | (0 << 1)
++ /* Present */
++ | (1 << 0)
++ );
++#if gcdMMU_TABLE_DUMP
++ gckOS_Print("%s(%d): insert MTLB[%d]: %08x\n",
++ __FUNCTION__, __LINE__,
++ mStart,
++ _ReadPageEntry(Mmu->mtlbLogical + mStart));
++#endif
++
++ stlb->mtlbIndex = mStart;
++ stlb->mtlbEntryNum = 1;
++#if gcdMMU_TABLE_DUMP
++ gckOS_Print("%s(%d): STLB: logical:%08x -> physical:%08x\n",
++ __FUNCTION__, __LINE__,
++ stlb->logical,
++ stlb->physBase);
++#endif
++
++ while (sStart <= last)
++ {
++ gcmkASSERT(!(start & gcdMMU_PAGE_64K_MASK));
++ _WritePageEntry(stlb->logical + sStart, _SetPage(start));
++#if gcdMMU_TABLE_DUMP
++ gckOS_Print("%s(%d): insert STLB[%d]: %08x\n",
++ __FUNCTION__, __LINE__,
++ sStart,
++ _ReadPageEntry(stlb->logical + sStart));
++#endif
++ /* next page. */
++ start += gcdMMU_PAGE_64K_SIZE;
++ sStart++;
++ stlb->pageCount++;
++ }
++
++ sStart = 0;
++ ++mStart;
++ }
++ else
++ {
++ gcmkONERROR(gcvSTATUS_INVALID_REQUEST);
++ }
++ }
++
++ /* Insert the stlb into staticSTLB. */
++ if (Mmu->staticSTLB == gcvNULL)
++ {
++ Mmu->staticSTLB = head;
++ }
++ else
++ {
++ gcmkASSERT(pre == gcvNULL);
++ gcmkASSERT(pre->next == gcvNULL);
++ pre->next = Mmu->staticSTLB;
++ Mmu->staticSTLB = head;
++ }
++
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Mmu->os, Mmu->pageTableMutex));
++
++ return gcvSTATUS_OK;
++
++OnError:
++
++ /* Roll back. */
++ while (head != gcvNULL)
++ {
++ pre = head;
++ head = head->next;
++
++ if (pre->physical != gcvNULL)
++ {
++ gcmkVERIFY_OK(
++ gckOS_FreeContiguous(Mmu->os,
++ pre->physical,
++ pre->logical,
++ pre->size));
++ }
++
++ if (pre->mtlbEntryNum != 0)
++ {
++ gcmkASSERT(pre->mtlbEntryNum == 1);
++ _WritePageEntry(Mmu->mtlbLogical + pre->mtlbIndex, 0);
++ }
++
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Mmu->os, pre));
++ }
++
++ if (mutex)
++ {
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Mmu->os, Mmu->pageTableMutex));
++ }
++
++ return status;
++}
++
++static gceSTATUS
++_FindDynamicSpace(
++ IN gckMMU Mmu,
++ OUT gcsDynamicSpaceNode_PTR *Array,
++ OUT gctINT * Size
++ )
++{
++ gceSTATUS status = gcvSTATUS_OK;
++ gctPOINTER pointer = gcvNULL;
++ gcsDynamicSpaceNode_PTR array = gcvNULL;
++ gctINT size = 0;
++ gctINT i = 0, nodeStart = -1, nodeEntries = 0;
++
++ /* Allocate memory for the array. */
++ gcmkONERROR(gckOS_Allocate(Mmu->os,
++ gcmSIZEOF(*array) * (gcdMMU_MTLB_ENTRY_NUM / 2),
++ &pointer));
++
++ array = (gcsDynamicSpaceNode_PTR)pointer;
++
++ /* Loop all the entries. */
++ while (i < gcdMMU_MTLB_ENTRY_NUM)
++ {
++ if (!Mmu->mtlbLogical[i])
++ {
++ if (nodeStart < 0)
++ {
++ /* This is the first entry of the dynamic space. */
++ nodeStart = i;
++ nodeEntries = 1;
++ }
++ else
++ {
++ /* Other entries of the dynamic space. */
++ nodeEntries++;
++ }
++ }
++ else if (nodeStart >= 0)
++ {
++ /* Save the previous node. */
++ array[size].start = nodeStart;
++ array[size].entries = nodeEntries;
++ size++;
++
++ /* Reset the start. */
++ nodeStart = -1;
++ nodeEntries = 0;
++ }
++
++ i++;
++ }
++
++ /* Save the previous node. */
++ if (nodeStart >= 0)
++ {
++ array[size].start = nodeStart;
++ array[size].entries = nodeEntries;
++ size++;
++ }
++
++#if gcdMMU_TABLE_DUMP
++ for (i = 0; i < size; i++)
++ {
++ gckOS_Print("%s(%d): [%d]: start=%d, entries=%d.\n",
++ __FUNCTION__, __LINE__,
++ i,
++ array[i].start,
++ array[i].entries);
++ }
++#endif
++
++ *Array = array;
++ *Size = size;
++
++ return gcvSTATUS_OK;
++
++OnError:
++ if (pointer != gcvNULL)
++ {
++ gckOS_Free(Mmu->os, pointer);
++ }
++
++ return status;
++}
++
++static gceSTATUS
++_SetupDynamicSpace(
++ IN gckMMU Mmu
++ )
++{
++ gceSTATUS status;
++ gcsDynamicSpaceNode_PTR nodeArray = gcvNULL;
++ gctINT i, nodeArraySize = 0;
++ gctUINT32 physical;
++ gctINT numEntries = 0;
++ gctUINT32_PTR pageTable;
++ gctBOOL acquired = gcvFALSE;
++
++ /* Find all the dynamic address space. */
++ gcmkONERROR(_FindDynamicSpace(Mmu, &nodeArray, &nodeArraySize));
++
++ /* TODO: We only use the largest one for now. */
++ for (i = 0; i < nodeArraySize; i++)
++ {
++ if (nodeArray[i].entries > numEntries)
++ {
++ Mmu->dynamicMappingStart = nodeArray[i].start;
++ numEntries = nodeArray[i].entries;
++ }
++ }
++
++ gckOS_Free(Mmu->os, (gctPOINTER)nodeArray);
++
++ Mmu->pageTableSize = numEntries * 4096;
++
++ Mmu->pageTableEntries = Mmu->pageTableSize / gcmSIZEOF(gctUINT32);
++
++ /* Construct Slave TLB. */
++ gcmkONERROR(gckOS_AllocateContiguous(Mmu->os,
++ gcvFALSE,
++ &Mmu->pageTableSize,
++ &Mmu->pageTablePhysical,
++ (gctPOINTER)&Mmu->pageTableLogical));
++
++#if gcdUSE_MMU_EXCEPTION
++ gcmkONERROR(_FillPageTable(Mmu->pageTableLogical,
++ Mmu->pageTableEntries,
++ /* Enable exception */
++ 1 << 1));
++#else
++ /* Invalidate all entries. */
++ gcmkONERROR(gckOS_ZeroMemory(Mmu->pageTableLogical,
++ Mmu->pageTableSize));
++#endif
++
++ /* Initilization. */
++ pageTable = Mmu->pageTableLogical;
++ _WritePageEntry(pageTable, (Mmu->pageTableEntries << 8) | gcvMMU_FREE);
++ _WritePageEntry(pageTable + 1, ~0U);
++ Mmu->heapList = 0;
++ Mmu->freeNodes = gcvFALSE;
++
++ gcmkONERROR(gckOS_GetPhysicalAddress(Mmu->os,
++ Mmu->pageTableLogical,
++ &physical));
++
++ /* Grab the mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(Mmu->os, Mmu->pageTableMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Map to Master TLB. */
++ for (i = (gctINT)Mmu->dynamicMappingStart;
++ i < (gctINT)Mmu->dynamicMappingStart + numEntries;
++ i++)
++ {
++ _WritePageEntry(Mmu->mtlbLogical + i,
++ physical
++ /* 4KB page size */
++ | (0 << 2)
++ /* Ignore exception */
++ | (0 << 1)
++ /* Present */
++ | (1 << 0)
++ );
++#if gcdMMU_TABLE_DUMP
++ gckOS_Print("%s(%d): insert MTLB[%d]: %08x\n",
++ __FUNCTION__, __LINE__,
++ i,
++ _ReadPageEntry(Mmu->mtlbLogical + i));
++#endif
++ physical += gcdMMU_STLB_4K_SIZE;
++ }
++
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Mmu->os, Mmu->pageTableMutex));
++
++ return gcvSTATUS_OK;
++
++OnError:
++ if (Mmu->pageTableLogical)
++ {
++ /* Free the page table. */
++ gcmkVERIFY_OK(
++ gckOS_FreeContiguous(Mmu->os,
++ Mmu->pageTablePhysical,
++ (gctPOINTER) Mmu->pageTableLogical,
++ Mmu->pageTableSize));
++ }
++
++ if (acquired)
++ {
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Mmu->os, Mmu->pageTableMutex));
++ }
++
++ return status;
++}
++
++/*******************************************************************************
++**
++** _Construct
++**
++** Construct a new gckMMU object.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gctSIZE_T MmuSize
++** Number of bytes for the page table.
++**
++** OUTPUT:
++**
++** gckMMU * Mmu
++** Pointer to a variable that receives the gckMMU object pointer.
++*/
++gceSTATUS
++_Construct(
++ IN gckKERNEL Kernel,
++ IN gctSIZE_T MmuSize,
++ OUT gckMMU * Mmu
++ )
++{
++ gckOS os;
++ gckHARDWARE hardware;
++ gceSTATUS status;
++ gckMMU mmu = gcvNULL;
++ gctUINT32_PTR pageTable;
++ gctPOINTER pointer = gcvNULL;
++
++ gcmkHEADER_ARG("Kernel=0x%x MmuSize=%lu", Kernel, MmuSize);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(MmuSize > 0);
++ gcmkVERIFY_ARGUMENT(Mmu != gcvNULL);
++
++ /* Extract the gckOS object pointer. */
++ os = Kernel->os;
++ gcmkVERIFY_OBJECT(os, gcvOBJ_OS);
++
++ /* Extract the gckHARDWARE object pointer. */
++ hardware = Kernel->hardware;
++ gcmkVERIFY_OBJECT(hardware, gcvOBJ_HARDWARE);
++
++ /* Allocate memory for the gckMMU object. */
++ gcmkONERROR(gckOS_Allocate(os, sizeof(struct _gckMMU), &pointer));
++
++ mmu = pointer;
++
++ /* Initialize the gckMMU object. */
++ mmu->object.type = gcvOBJ_MMU;
++ mmu->os = os;
++ mmu->hardware = hardware;
++ mmu->pageTableMutex = gcvNULL;
++ mmu->pageTableLogical = gcvNULL;
++ mmu->mtlbLogical = gcvNULL;
++ mmu->staticSTLB = gcvNULL;
++ mmu->enabled = gcvFALSE;
++#ifdef __QNXNTO__
++ mmu->nodeList = gcvNULL;
++ mmu->nodeMutex = gcvNULL;
++#endif
++
++ /* Create the page table mutex. */
++ gcmkONERROR(gckOS_CreateMutex(os, &mmu->pageTableMutex));
++
++#ifdef __QNXNTO__
++ /* Create the node list mutex. */
++ gcmkONERROR(gckOS_CreateMutex(os, &mmu->nodeMutex));
++#endif
++
++ if (hardware->mmuVersion == 0)
++ {
++ mmu->pageTableSize = MmuSize;
++
++ gcmkONERROR(
++ gckOS_AllocateContiguous(os,
++ gcvFALSE,
++ &mmu->pageTableSize,
++ &mmu->pageTablePhysical,
++ &pointer));
++
++ mmu->pageTableLogical = pointer;
++
++ /* Compute number of entries in page table. */
++ mmu->pageTableEntries = mmu->pageTableSize / sizeof(gctUINT32);
++
++ /* Mark all pages as free. */
++ pageTable = mmu->pageTableLogical;
++
++#if gcdMMU_CLEAR_VALUE
++ _FillPageTable(pageTable, mmu->pageTableEntries, gcdMMU_CLEAR_VALUE);
++#endif
++
++ _WritePageEntry(pageTable, (mmu->pageTableEntries << 8) | gcvMMU_FREE);
++ _WritePageEntry(pageTable + 1, ~0U);
++ mmu->heapList = 0;
++ mmu->freeNodes = gcvFALSE;
++
++ /* Set page table address. */
++ gcmkONERROR(
++ gckHARDWARE_SetMMU(hardware, (gctPOINTER) mmu->pageTableLogical));
++ }
++ else
++ {
++ /* Allocate the 4K mode MTLB table. */
++ mmu->mtlbSize = gcdMMU_MTLB_SIZE + 64;
++
++ gcmkONERROR(
++ gckOS_AllocateContiguous(os,
++ gcvFALSE,
++ &mmu->mtlbSize,
++ &mmu->mtlbPhysical,
++ &pointer));
++
++ mmu->mtlbLogical = pointer;
++
++ /* Invalid all the entries. */
++ gcmkONERROR(
++ gckOS_ZeroMemory(pointer, mmu->mtlbSize));
++ }
++
++ /* Return the gckMMU object pointer. */
++ *Mmu = mmu;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Mmu=0x%x", *Mmu);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Roll back. */
++ if (mmu != gcvNULL)
++ {
++ if (mmu->pageTableLogical != gcvNULL)
++ {
++ /* Free the page table. */
++ gcmkVERIFY_OK(
++ gckOS_FreeContiguous(os,
++ mmu->pageTablePhysical,
++ (gctPOINTER) mmu->pageTableLogical,
++ mmu->pageTableSize));
++
++ }
++
++ if (mmu->mtlbLogical != gcvNULL)
++ {
++ gcmkVERIFY_OK(
++ gckOS_FreeContiguous(os,
++ mmu->mtlbPhysical,
++ (gctPOINTER) mmu->mtlbLogical,
++ mmu->mtlbSize));
++ }
++
++ if (mmu->pageTableMutex != gcvNULL)
++ {
++ /* Delete the mutex. */
++ gcmkVERIFY_OK(
++ gckOS_DeleteMutex(os, mmu->pageTableMutex));
++ }
++
++#ifdef __QNXNTO__
++ if (mmu->nodeMutex != gcvNULL)
++ {
++ /* Delete the mutex. */
++ gcmkVERIFY_OK(
++ gckOS_DeleteMutex(os, mmu->nodeMutex));
++ }
++#endif
++
++ /* Mark the gckMMU object as unknown. */
++ mmu->object.type = gcvOBJ_UNKNOWN;
++
++ /* Free the allocates memory. */
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(os, mmu));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** _Destroy
++**
++** Destroy a gckMMU object.
++**
++** INPUT:
++**
++** gckMMU Mmu
++** Pointer to an gckMMU object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++_Destroy(
++ IN gckMMU Mmu
++ )
++{
++#ifdef __QNXNTO__
++ gcuVIDMEM_NODE_PTR node, next;
++#endif
++
++ gcmkHEADER_ARG("Mmu=0x%x", Mmu);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Mmu, gcvOBJ_MMU);
++
++#ifdef __QNXNTO__
++ /* Free all associated virtual memory. */
++ for (node = Mmu->nodeList; node != gcvNULL; node = next)
++ {
++ next = node->Virtual.next;
++ gcmkVERIFY_OK(gckVIDMEM_Free(node));
++ }
++#endif
++
++ while (Mmu->staticSTLB != gcvNULL)
++ {
++ gcsMMU_STLB_PTR pre = Mmu->staticSTLB;
++ Mmu->staticSTLB = pre->next;
++
++ if (pre->physical != gcvNULL)
++ {
++ gcmkVERIFY_OK(
++ gckOS_FreeContiguous(Mmu->os,
++ pre->physical,
++ pre->logical,
++ pre->size));
++ }
++
++ if (pre->mtlbEntryNum != 0)
++ {
++ gcmkASSERT(pre->mtlbEntryNum == 1);
++ _WritePageEntry(Mmu->mtlbLogical + pre->mtlbIndex, 0);
++#if gcdMMU_TABLE_DUMP
++ gckOS_Print("%s(%d): clean MTLB[%d]\n",
++ __FUNCTION__, __LINE__,
++ pre->mtlbIndex);
++#endif
++ }
++
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Mmu->os, pre));
++ }
++
++ if (Mmu->hardware->mmuVersion != 0)
++ {
++ gcmkVERIFY_OK(
++ gckOS_FreeContiguous(Mmu->os,
++ Mmu->mtlbPhysical,
++ (gctPOINTER) Mmu->mtlbLogical,
++ Mmu->mtlbSize));
++ }
++
++ /* Free the page table. */
++ gcmkVERIFY_OK(
++ gckOS_FreeContiguous(Mmu->os,
++ Mmu->pageTablePhysical,
++ (gctPOINTER) Mmu->pageTableLogical,
++ Mmu->pageTableSize));
++
++#ifdef __QNXNTO__
++ /* Delete the node list mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Mmu->os, Mmu->nodeMutex));
++#endif
++
++ /* Delete the page table mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Mmu->os, Mmu->pageTableMutex));
++
++ /* Mark the gckMMU object as unknown. */
++ Mmu->object.type = gcvOBJ_UNKNOWN;
++
++ /* Free the gckMMU object. */
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Mmu->os, Mmu));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++** _AdjstIndex
++**
++** Adjust the index from which we search for a usable node to make sure
++** index allocated is greater than Start.
++*/
++gceSTATUS
++_AdjustIndex(
++ IN gckMMU Mmu,
++ IN gctUINT32 Index,
++ IN gctUINT32 PageCount,
++ IN gctUINT32 Start,
++ OUT gctUINT32 * IndexAdjusted
++ )
++{
++ gceSTATUS status;
++ gctUINT32 index = Index;
++ gctUINT32_PTR map = Mmu->pageTableLogical;
++
++ gcmkHEADER();
++
++ for (; index < Mmu->pageTableEntries;)
++ {
++ gctUINT32 result = 0;
++ gctUINT32 nodeSize = 0;
++
++ if (index >= Start)
++ {
++ break;
++ }
++
++ switch (gcmENTRY_TYPE(map[index]))
++ {
++ case gcvMMU_SINGLE:
++ nodeSize = 1;
++ break;
++
++ case gcvMMU_FREE:
++ nodeSize = map[index] >> 8;
++ break;
++
++ default:
++ gcmkFATAL("MMU table correcupted at index %u!", index);
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++ if (nodeSize > PageCount)
++ {
++ result = index + (nodeSize - PageCount);
++
++ if (result >= Start)
++ {
++ break;
++ }
++ }
++
++ switch (gcmENTRY_TYPE(map[index]))
++ {
++ case gcvMMU_SINGLE:
++ index = map[index] >> 8;
++ break;
++
++ case gcvMMU_FREE:
++ index = map[index + 1];
++ break;
++
++ default:
++ gcmkFATAL("MMU table correcupted at index %u!", index);
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++ }
++
++ *IndexAdjusted = index;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckMMU_Construct(
++ IN gckKERNEL Kernel,
++ IN gctSIZE_T MmuSize,
++ OUT gckMMU * Mmu
++ )
++{
++#if gcdSHARED_PAGETABLE
++ gceSTATUS status;
++ gctPOINTER pointer;
++
++ gcmkHEADER_ARG("Kernel=0x%08x", Kernel);
++
++ if (sharedPageTable == gcvNULL)
++ {
++ gcmkONERROR(
++ gckOS_Allocate(Kernel->os,
++ sizeof(struct _gcsSharedPageTable),
++ &pointer));
++ sharedPageTable = pointer;
++
++ gcmkONERROR(
++ gckOS_ZeroMemory(sharedPageTable,
++ sizeof(struct _gcsSharedPageTable)));
++
++ gcmkONERROR(_Construct(Kernel, MmuSize, &sharedPageTable->mmu));
++ }
++ else if (Kernel->hardware->mmuVersion == 0)
++ {
++ /* Set page table address. */
++ gcmkONERROR(
++ gckHARDWARE_SetMMU(Kernel->hardware, (gctPOINTER) sharedPageTable->mmu->pageTableLogical));
++ }
++
++ *Mmu = sharedPageTable->mmu;
++
++ sharedPageTable->hardwares[sharedPageTable->reference] = Kernel->hardware;
++
++ sharedPageTable->reference++;
++
++ gcmkFOOTER_ARG("sharedPageTable->reference=%lu", sharedPageTable->reference);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (sharedPageTable)
++ {
++ if (sharedPageTable->mmu)
++ {
++ gcmkVERIFY_OK(gckMMU_Destroy(sharedPageTable->mmu));
++ }
++
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Kernel->os, sharedPageTable));
++ }
++
++ gcmkFOOTER();
++ return status;
++#elif gcdMIRROR_PAGETABLE
++ gceSTATUS status;
++ gctPOINTER pointer;
++
++ gcmkHEADER_ARG("Kernel=0x%08x", Kernel);
++
++ if (mirrorPageTable == gcvNULL)
++ {
++ gcmkONERROR(
++ gckOS_Allocate(Kernel->os,
++ sizeof(struct _gcsMirrorPageTable),
++ &pointer));
++ mirrorPageTable = pointer;
++
++ gcmkONERROR(
++ gckOS_ZeroMemory(mirrorPageTable,
++ sizeof(struct _gcsMirrorPageTable)));
++
++ gcmkONERROR(
++ gckOS_CreateMutex(Kernel->os, &mirrorPageTableMutex));
++ }
++
++ gcmkONERROR(_Construct(Kernel, MmuSize, Mmu));
++
++ mirrorPageTable->mmus[mirrorPageTable->reference] = *Mmu;
++
++ mirrorPageTable->hardwares[mirrorPageTable->reference] = Kernel->hardware;
++
++ mirrorPageTable->reference++;
++
++ gcmkFOOTER_ARG("mirrorPageTable->reference=%lu", mirrorPageTable->reference);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (mirrorPageTable && mirrorPageTable->reference == 0)
++ {
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Kernel->os, mirrorPageTable));
++ }
++
++ gcmkFOOTER();
++ return status;
++#else
++ return _Construct(Kernel, MmuSize, Mmu);
++#endif
++}
++
++gceSTATUS
++gckMMU_Destroy(
++ IN gckMMU Mmu
++ )
++{
++#if gcdSHARED_PAGETABLE
++ sharedPageTable->reference--;
++
++ if (sharedPageTable->reference == 0)
++ {
++ if (sharedPageTable->mmu)
++ {
++ gcmkVERIFY_OK(_Destroy(Mmu));
++ }
++
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Mmu->os, sharedPageTable));
++ }
++
++ return gcvSTATUS_OK;
++#elif gcdMIRROR_PAGETABLE
++ mirrorPageTable->reference--;
++
++ if (mirrorPageTable->reference == 0)
++ {
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Mmu->os, mirrorPageTable));
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Mmu->os, mirrorPageTableMutex));
++ }
++
++ return _Destroy(Mmu);
++#else
++ return _Destroy(Mmu);
++#endif
++}
++
++/*******************************************************************************
++**
++** gckMMU_AllocatePages
++**
++** Allocate pages inside the page table.
++**
++** INPUT:
++**
++** gckMMU Mmu
++** Pointer to an gckMMU object.
++**
++** gctSIZE_T PageCount
++** Number of pages to allocate.
++**
++** OUTPUT:
++**
++** gctPOINTER * PageTable
++** Pointer to a variable that receives the base address of the page
++** table.
++**
++** gctUINT32 * Address
++** Pointer to a variable that receives the hardware specific address.
++*/
++gceSTATUS
++_AllocatePages(
++ IN gckMMU Mmu,
++ IN gctSIZE_T PageCount,
++ IN gceSURF_TYPE Type,
++ OUT gctPOINTER * PageTable,
++ OUT gctUINT32 * Address
++ )
++{
++ gceSTATUS status;
++ gctBOOL mutex = gcvFALSE;
++ gctUINT32 index = 0, previous = ~0U, left;
++ gctUINT32_PTR pageTable;
++ gctBOOL gotIt;
++ gctUINT32 address;
++
++ gcmkHEADER_ARG("Mmu=0x%x PageCount=%lu", Mmu, PageCount);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Mmu, gcvOBJ_MMU);
++ gcmkVERIFY_ARGUMENT(PageCount > 0);
++ gcmkVERIFY_ARGUMENT(PageTable != gcvNULL);
++
++ if (PageCount > Mmu->pageTableEntries)
++ {
++ gcmkPRINT("[galcore]: %s(%d): Run out of free page entry.",
++ __FUNCTION__, __LINE__);
++
++ /* Not enough pages avaiable. */
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++ /* Grab the mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(Mmu->os, Mmu->pageTableMutex, gcvINFINITE));
++ mutex = gcvTRUE;
++
++ /* Cast pointer to page table. */
++ for (pageTable = Mmu->pageTableLogical, gotIt = gcvFALSE; !gotIt;)
++ {
++ index = Mmu->heapList;
++
++ if ((Mmu->hardware->mmuVersion == 0) && (Type == gcvSURF_VERTEX))
++ {
++ gcmkONERROR(_AdjustIndex(
++ Mmu,
++ index,
++ PageCount,
++ gcdVERTEX_START / gcmSIZEOF(gctUINT32),
++ &index
++ ));
++ }
++
++ /* Walk the heap list. */
++ for (; !gotIt && (index < Mmu->pageTableEntries);)
++ {
++ /* Check the node type. */
++ switch (gcmENTRY_TYPE(_ReadPageEntry(&pageTable[index])))
++ {
++ case gcvMMU_SINGLE:
++ /* Single odes are valid if we only need 1 page. */
++ if (PageCount == 1)
++ {
++ gotIt = gcvTRUE;
++ }
++ else
++ {
++ /* Move to next node. */
++ previous = index;
++ index = _ReadPageEntry(&pageTable[index]) >> 8;
++ }
++ break;
++
++ case gcvMMU_FREE:
++ /* Test if the node has enough space. */
++ if (PageCount <= (_ReadPageEntry(&pageTable[index]) >> 8))
++ {
++ gotIt = gcvTRUE;
++ }
++ else
++ {
++ /* Move to next node. */
++ previous = index;
++ index = _ReadPageEntry(&pageTable[index + 1]);
++ }
++ break;
++
++ default:
++ gcmkFATAL("MMU table correcupted at index %u!", index);
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++ }
++
++ /* Test if we are out of memory. */
++ if (index >= Mmu->pageTableEntries)
++ {
++ if (Mmu->freeNodes)
++ {
++ /* Time to move out the trash! */
++ gcmkONERROR(_Collect(Mmu));
++ }
++ else
++ {
++ gcmkPRINT("[galcore]: %s(%d): Run out of free page entry.",
++ __FUNCTION__, __LINE__);
++
++ /* Out of resources. */
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++ }
++ }
++
++ switch (gcmENTRY_TYPE(_ReadPageEntry(&pageTable[index])))
++ {
++ case gcvMMU_SINGLE:
++ /* Unlink single node from free list. */
++ gcmkONERROR(
++ _Link(Mmu, previous, _ReadPageEntry(&pageTable[index]) >> 8));
++ break;
++
++ case gcvMMU_FREE:
++ /* Check how many pages will be left. */
++ left = (_ReadPageEntry(&pageTable[index]) >> 8) - PageCount;
++ switch (left)
++ {
++ case 0:
++ /* The entire node is consumed, just unlink it. */
++ gcmkONERROR(
++ _Link(Mmu, previous, _ReadPageEntry(&pageTable[index + 1])));
++ break;
++
++ case 1:
++ /* One page will remain. Convert the node to a single node and
++ ** advance the index. */
++ _WritePageEntry(&pageTable[index], (_ReadPageEntry(&pageTable[index + 1]) << 8) | gcvMMU_SINGLE);
++ index ++;
++ break;
++
++ default:
++ /* Enough pages remain for a new node. However, we will just adjust
++ ** the size of the current node and advance the index. */
++ _WritePageEntry(&pageTable[index], (left << 8) | gcvMMU_FREE);
++ index += left;
++ break;
++ }
++ break;
++ }
++
++ /* Mark node as used. */
++ gcmkONERROR(_FillPageTable(&pageTable[index], PageCount, gcvMMU_USED));
++
++ /* Return pointer to page table. */
++ *PageTable = &pageTable[index];
++
++ /* Build virtual address. */
++ if (Mmu->hardware->mmuVersion == 0)
++ {
++ gcmkONERROR(
++ gckHARDWARE_BuildVirtualAddress(Mmu->hardware, index, 0, &address));
++ }
++ else
++ {
++ gctUINT32 masterOffset = index / gcdMMU_STLB_4K_ENTRY_NUM
++ + Mmu->dynamicMappingStart;
++ gctUINT32 slaveOffset = index % gcdMMU_STLB_4K_ENTRY_NUM;
++
++ address = (masterOffset << gcdMMU_MTLB_SHIFT)
++ | (slaveOffset << gcdMMU_STLB_4K_SHIFT);
++ }
++
++ if (Address != gcvNULL)
++ {
++ *Address = address;
++ }
++
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Mmu->os, Mmu->pageTableMutex));
++
++ /* Success. */
++ gcmkFOOTER_ARG("*PageTable=0x%x *Address=%08x",
++ *PageTable, gcmOPT_VALUE(Address));
++ return gcvSTATUS_OK;
++
++OnError:
++
++ if (mutex)
++ {
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Mmu->os, Mmu->pageTableMutex));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckMMU_FreePages
++**
++** Free pages inside the page table.
++**
++** INPUT:
++**
++** gckMMU Mmu
++** Pointer to an gckMMU object.
++**
++** gctPOINTER PageTable
++** Base address of the page table to free.
++**
++** gctSIZE_T PageCount
++** Number of pages to free.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++_FreePages(
++ IN gckMMU Mmu,
++ IN gctPOINTER PageTable,
++ IN gctSIZE_T PageCount
++ )
++{
++ gctUINT32_PTR pageTable;
++ gceSTATUS status;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Mmu=0x%x PageTable=0x%x PageCount=%lu",
++ Mmu, PageTable, PageCount);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Mmu, gcvOBJ_MMU);
++ gcmkVERIFY_ARGUMENT(PageTable != gcvNULL);
++ gcmkVERIFY_ARGUMENT(PageCount > 0);
++
++ /* Convert the pointer. */
++ pageTable = (gctUINT32_PTR) PageTable;
++
++ gcmkONERROR(gckOS_AcquireMutex(Mmu->os, Mmu->pageTableMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++#if gcdMMU_CLEAR_VALUE
++ if (Mmu->hardware->mmuVersion == 0)
++ {
++ _FillPageTable(pageTable, PageCount, gcdMMU_CLEAR_VALUE);
++ }
++#endif
++
++ if (PageCount == 1)
++ {
++ /* Single page node. */
++ _WritePageEntry(pageTable,
++ (~((1U<<8)-1)) | gcvMMU_SINGLE
++#if gcdUSE_MMU_EXCEPTION
++ /* Enable exception */
++ | 1 << 1
++#endif
++ );
++ }
++ else
++ {
++ /* Mark the node as free. */
++ _WritePageEntry(pageTable,
++ (PageCount << 8) | gcvMMU_FREE
++#if gcdUSE_MMU_EXCEPTION
++ /* Enable exception */
++ | 1 << 1
++#endif
++ );
++ _WritePageEntry(pageTable + 1, ~0U);
++
++#if gcdUSE_MMU_EXCEPTION
++ /* Enable exception */
++ gcmkVERIFY_OK(_FillPageTable(pageTable + 2, PageCount - 2, 1 << 1));
++#endif
++ }
++
++ /* We have free nodes. */
++ Mmu->freeNodes = gcvTRUE;
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Mmu->os, Mmu->pageTableMutex));
++ acquired = gcvFALSE;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Mmu->os, Mmu->pageTableMutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckMMU_AllocatePages(
++ IN gckMMU Mmu,
++ IN gctSIZE_T PageCount,
++ OUT gctPOINTER * PageTable,
++ OUT gctUINT32 * Address
++ )
++{
++ return gckMMU_AllocatePagesEx(
++ Mmu, PageCount, gcvSURF_UNKNOWN, PageTable, Address);
++}
++
++gceSTATUS
++gckMMU_AllocatePagesEx(
++ IN gckMMU Mmu,
++ IN gctSIZE_T PageCount,
++ IN gceSURF_TYPE Type,
++ OUT gctPOINTER * PageTable,
++ OUT gctUINT32 * Address
++ )
++{
++#if gcdMIRROR_PAGETABLE
++ gceSTATUS status;
++ gctPOINTER pageTable;
++ gctUINT32 address;
++ gctINT i;
++ gckMMU mmu;
++ gctBOOL acquired = gcvFALSE;
++ gctBOOL allocated = gcvFALSE;
++
++ gckOS_AcquireMutex(Mmu->os, mirrorPageTableMutex, gcvINFINITE);
++ acquired = gcvTRUE;
++
++ /* Allocate page table for current MMU. */
++ for (i = 0; i < (gctINT)mirrorPageTable->reference; i++)
++ {
++ if (Mmu == mirrorPageTable->mmus[i])
++ {
++ gcmkONERROR(_AllocatePages(Mmu, PageCount, Type, PageTable, Address));
++ allocated = gcvTRUE;
++ }
++ }
++
++ /* Allocate page table for other MMUs. */
++ for (i = 0; i < (gctINT)mirrorPageTable->reference; i++)
++ {
++ mmu = mirrorPageTable->mmus[i];
++
++ if (Mmu != mmu)
++ {
++ gcmkONERROR(_AllocatePages(mmu, PageCount, Type, &pageTable, &address));
++ gcmkASSERT(address == *Address);
++ }
++ }
++
++ gckOS_ReleaseMutex(Mmu->os, mirrorPageTableMutex);
++ acquired = gcvFALSE;
++
++ return gcvSTATUS_OK;
++OnError:
++
++ if (allocated)
++ {
++ /* Page tables for multiple GPU always keep the same. So it is impossible
++ * the fist one allocates successfully but others fail.
++ */
++ gcmkASSERT(0);
++ }
++
++ if (acquired)
++ {
++ gckOS_ReleaseMutex(Mmu->os, mirrorPageTableMutex);
++ }
++
++ return status;
++#else
++ return _AllocatePages(Mmu, PageCount, Type, PageTable, Address);
++#endif
++}
++
++gceSTATUS
++gckMMU_FreePages(
++ IN gckMMU Mmu,
++ IN gctPOINTER PageTable,
++ IN gctSIZE_T PageCount
++ )
++{
++#if gcdMIRROR_PAGETABLE
++ gctINT i;
++ gctUINT32 offset;
++ gckMMU mmu;
++
++ gckOS_AcquireMutex(Mmu->os, mirrorPageTableMutex, gcvINFINITE);
++
++ gcmkVERIFY_OK(_FreePages(Mmu, PageTable, PageCount));
++
++ offset = (gctUINT32)PageTable - (gctUINT32)Mmu->pageTableLogical;
++
++ for (i = 0; i < (gctINT)mirrorPageTable->reference; i++)
++ {
++ mmu = mirrorPageTable->mmus[i];
++
++ if (mmu != Mmu)
++ {
++ gcmkVERIFY_OK(_FreePages(mmu, mmu->pageTableLogical + offset/4, PageCount));
++ }
++ }
++
++ gckOS_ReleaseMutex(Mmu->os, mirrorPageTableMutex);
++
++ return gcvSTATUS_OK;
++#else
++ return _FreePages(Mmu, PageTable, PageCount);
++#endif
++}
++
++gceSTATUS
++gckMMU_Enable(
++ IN gckMMU Mmu,
++ IN gctUINT32 PhysBaseAddr,
++ IN gctUINT32 PhysSize
++ )
++{
++ gceSTATUS status;
++#if gcdSHARED_PAGETABLE
++ gckHARDWARE hardware;
++ gctINT i;
++#endif
++
++ gcmkHEADER_ARG("Mmu=0x%x", Mmu);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Mmu, gcvOBJ_MMU);
++
++#if gcdSHARED_PAGETABLE
++ if (Mmu->enabled)
++ {
++ gcmkFOOTER_ARG("Status=%d", gcvSTATUS_SKIP);
++ return gcvSTATUS_SKIP;
++ }
++#endif
++
++ if (Mmu->hardware->mmuVersion == 0)
++ {
++ /* Success. */
++ gcmkFOOTER_ARG("Status=%d", gcvSTATUS_SKIP);
++ return gcvSTATUS_SKIP;
++ }
++ else
++ {
++ if (PhysSize != 0)
++ {
++ gcmkONERROR(_FillFlatMapping(
++ Mmu,
++ PhysBaseAddr,
++ PhysSize
++ ));
++ }
++
++ gcmkONERROR(_SetupDynamicSpace(Mmu));
++
++#if gcdSHARED_PAGETABLE
++ for(i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ hardware = sharedPageTable->hardwares[i];
++ if (hardware != gcvNULL)
++ {
++ gcmkONERROR(
++ gckHARDWARE_SetMMUv2(
++ hardware,
++ gcvTRUE,
++ Mmu->mtlbLogical,
++ gcvMMU_MODE_4K,
++ (gctUINT8_PTR)Mmu->mtlbLogical + gcdMMU_MTLB_SIZE,
++ gcvFALSE
++ ));
++ }
++ }
++#else
++ gcmkONERROR(
++ gckHARDWARE_SetMMUv2(
++ Mmu->hardware,
++ gcvTRUE,
++ Mmu->mtlbLogical,
++ gcvMMU_MODE_4K,
++ (gctUINT8_PTR)Mmu->mtlbLogical + gcdMMU_MTLB_SIZE,
++ gcvFALSE
++ ));
++#endif
++
++ Mmu->enabled = gcvTRUE;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckMMU_SetPage(
++ IN gckMMU Mmu,
++ IN gctUINT32 PageAddress,
++ IN gctUINT32 *PageEntry
++ )
++{
++#if gcdMIRROR_PAGETABLE
++ gctUINT32_PTR pageEntry;
++ gctINT i;
++ gckMMU mmu;
++ gctUINT32 offset = (gctUINT32)PageEntry - (gctUINT32)Mmu->pageTableLogical;
++#endif
++
++ gctUINT32 data;
++ gcmkHEADER_ARG("Mmu=0x%x", Mmu);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Mmu, gcvOBJ_MMU);
++ gcmkVERIFY_ARGUMENT(PageEntry != gcvNULL);
++ gcmkVERIFY_ARGUMENT(!(PageAddress & 0xFFF));
++
++ if (Mmu->hardware->mmuVersion == 0)
++ {
++ data = PageAddress;
++ }
++ else
++ {
++ data = _SetPage(PageAddress);
++ }
++
++ _WritePageEntry(PageEntry, data);
++
++#if gcdMIRROR_PAGETABLE
++ for (i = 0; i < (gctINT)mirrorPageTable->reference; i++)
++ {
++ mmu = mirrorPageTable->mmus[i];
++
++ if (mmu != Mmu)
++ {
++ pageEntry = mmu->pageTableLogical + offset / 4;
++
++ if (mmu->hardware->mmuVersion == 0)
++ {
++ _WritePageEntry(pageEntry, PageAddress);
++ }
++ else
++ {
++ _WritePageEntry(pageEntry, _SetPage(PageAddress));
++ }
++ }
++
++ }
++#endif
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++#ifdef __QNXNTO__
++gceSTATUS
++gckMMU_InsertNode(
++ IN gckMMU Mmu,
++ IN gcuVIDMEM_NODE_PTR Node)
++{
++ gceSTATUS status;
++ gctBOOL mutex = gcvFALSE;
++
++ gcmkHEADER_ARG("Mmu=0x%x Node=0x%x", Mmu, Node);
++
++ gcmkVERIFY_OBJECT(Mmu, gcvOBJ_MMU);
++
++ gcmkONERROR(gckOS_AcquireMutex(Mmu->os, Mmu->nodeMutex, gcvINFINITE));
++ mutex = gcvTRUE;
++
++ Node->Virtual.next = Mmu->nodeList;
++ Mmu->nodeList = Node;
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Mmu->os, Mmu->nodeMutex));
++
++ gcmkFOOTER();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (mutex)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Mmu->os, Mmu->nodeMutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckMMU_RemoveNode(
++ IN gckMMU Mmu,
++ IN gcuVIDMEM_NODE_PTR Node)
++{
++ gceSTATUS status;
++ gctBOOL mutex = gcvFALSE;
++ gcuVIDMEM_NODE_PTR *iter;
++
++ gcmkHEADER_ARG("Mmu=0x%x Node=0x%x", Mmu, Node);
++
++ gcmkVERIFY_OBJECT(Mmu, gcvOBJ_MMU);
++
++ gcmkONERROR(gckOS_AcquireMutex(Mmu->os, Mmu->nodeMutex, gcvINFINITE));
++ mutex = gcvTRUE;
++
++ for (iter = &Mmu->nodeList; *iter; iter = &(*iter)->Virtual.next)
++ {
++ if (*iter == Node)
++ {
++ *iter = Node->Virtual.next;
++ break;
++ }
++ }
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Mmu->os, Mmu->nodeMutex));
++
++ gcmkFOOTER();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (mutex)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Mmu->os, Mmu->nodeMutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckMMU_FreeHandleMemory(
++ IN gckKERNEL Kernel,
++ IN gckMMU Mmu,
++ IN gctUINT32 Pid
++ )
++{
++ gceSTATUS status;
++ gctBOOL acquired = gcvFALSE;
++ gcuVIDMEM_NODE_PTR curr, next;
++
++ gcmkHEADER_ARG("Kernel=0x%x, Mmu=0x%x Pid=%u", Kernel, Mmu, Pid);
++
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_OBJECT(Mmu, gcvOBJ_MMU);
++
++ gcmkONERROR(gckOS_AcquireMutex(Mmu->os, Mmu->nodeMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ for (curr = Mmu->nodeList; curr != gcvNULL; curr = next)
++ {
++ next = curr->Virtual.next;
++
++ if (curr->Virtual.processID == Pid)
++ {
++ while (curr->Virtual.unlockPendings[Kernel->core] == 0 && curr->Virtual.lockeds[Kernel->core] > 0)
++ {
++ gcmkONERROR(gckVIDMEM_Unlock(Kernel, curr, gcvSURF_TYPE_UNKNOWN, gcvNULL));
++ }
++
++ gcmkVERIFY_OK(gckVIDMEM_Free(curr));
++ }
++ }
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Mmu->os, Mmu->nodeMutex));
++
++ gcmkFOOTER();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Mmu->os, Mmu->nodeMutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++#endif
++
++gceSTATUS
++gckMMU_Flush(
++ IN gckMMU Mmu
++ )
++{
++ gckHARDWARE hardware;
++#if gcdSHARED_PAGETABLE
++ gctINT i;
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++#if gcdENABLE_VG
++ if (i == gcvCORE_VG)
++ {
++ continue;
++ }
++#endif
++ hardware = sharedPageTable->hardwares[i];
++ if (hardware)
++ {
++ /* Notify cores who use this page table. */
++ gcmkVERIFY_OK(
++ gckOS_AtomSet(hardware->os, hardware->pageTableDirty, 1));
++ }
++ }
++#elif gcdMIRROR_PAGETABLE
++ gctINT i;
++ for (i = 0; i < mirrorPageTable->reference; i++)
++ {
++ hardware = mirrorPageTable->hardwares[i];
++
++ /* Notify cores who use this page table. */
++ gcmkVERIFY_OK(
++ gckOS_AtomSet(hardware->os, hardware->pageTableDirty, 1));
++ }
++#else
++ hardware = Mmu->hardware;
++ gcmkVERIFY_OK(
++ gckOS_AtomSet(hardware->os, hardware->pageTableDirty, 1));
++#endif
++
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckMMU_DumpPageTableEntry(
++ IN gckMMU Mmu,
++ IN gctUINT32 Address
++ )
++{
++ gctUINT32_PTR pageTable;
++ gctUINT32 index;
++ gctUINT32 mtlb, stlb;
++
++ gcmkHEADER_ARG("Mmu=0x%08X Address=0x%08X", Mmu, Address);
++ gcmkVERIFY_OBJECT(Mmu, gcvOBJ_MMU);
++
++ gcmkASSERT(Mmu->hardware->mmuVersion > 0);
++
++ mtlb = (Address & gcdMMU_MTLB_MASK) >> gcdMMU_MTLB_SHIFT;
++ stlb = (Address & gcdMMU_STLB_4K_MASK) >> gcdMMU_STLB_4K_SHIFT;
++
++ if (Address >= 0x80000000)
++ {
++ pageTable = Mmu->pageTableLogical;
++
++ index = (mtlb - Mmu->dynamicMappingStart)
++ * gcdMMU_STLB_4K_ENTRY_NUM
++ + stlb;
++
++ gcmkPRINT(" Page table entry = 0x%08X", _ReadPageEntry(pageTable + index));
++ }
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/******************************************************************************
++****************************** T E S T C O D E ******************************
++******************************************************************************/
++
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_mmu_vg.c linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_mmu_vg.c
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_mmu_vg.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_mmu_vg.c 2015-07-27 23:13:06.194879670 +0200
+@@ -0,0 +1,522 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_precomp.h"
++
++#if gcdENABLE_VG
++
++#define _GC_OBJ_ZONE gcvZONE_MMU
++
++/*******************************************************************************
++**
++** gckVGMMU_Construct
++**
++** Construct a new gckVGMMU object.
++**
++** INPUT:
++**
++** gckVGKERNEL Kernel
++** Pointer to an gckVGKERNEL object.
++**
++** gctSIZE_T MmuSize
++** Number of bytes for the page table.
++**
++** OUTPUT:
++**
++** gckVGMMU * Mmu
++** Pointer to a variable that receives the gckVGMMU object pointer.
++*/
++gceSTATUS gckVGMMU_Construct(
++ IN gckVGKERNEL Kernel,
++ IN gctSIZE_T MmuSize,
++ OUT gckVGMMU * Mmu
++ )
++{
++ gckOS os;
++ gckVGHARDWARE hardware;
++ gceSTATUS status;
++ gckVGMMU mmu;
++ gctUINT32 * pageTable;
++ gctUINT32 i;
++
++ gcmkHEADER_ARG("Kernel=0x%x MmuSize=0x%x Mmu=0x%x", Kernel, MmuSize, Mmu);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(MmuSize > 0);
++ gcmkVERIFY_ARGUMENT(Mmu != gcvNULL);
++
++ /* Extract the gckOS object pointer. */
++ os = Kernel->os;
++ gcmkVERIFY_OBJECT(os, gcvOBJ_OS);
++
++ /* Extract the gckVGHARDWARE object pointer. */
++ hardware = Kernel->hardware;
++ gcmkVERIFY_OBJECT(hardware, gcvOBJ_HARDWARE);
++
++ /* Allocate memory for the gckVGMMU object. */
++ status = gckOS_Allocate(os, sizeof(struct _gckVGMMU), (gctPOINTER *) &mmu);
++
++ if (status < 0)
++ {
++ /* Error. */
++ gcmkFATAL(
++ "%s(%d): could not allocate gckVGMMU object.",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkFOOTER();
++ return status;
++ }
++
++ /* Initialize the gckVGMMU object. */
++ mmu->object.type = gcvOBJ_MMU;
++ mmu->os = os;
++ mmu->hardware = hardware;
++
++ /* Create the mutex. */
++ status = gckOS_CreateMutex(os, &mmu->mutex);
++
++ if (status < 0)
++ {
++ /* Roll back. */
++ mmu->object.type = gcvOBJ_UNKNOWN;
++ gcmkVERIFY_OK(gckOS_Free(os, mmu));
++
++ gcmkFOOTER();
++ /* Error. */
++ return status;
++ }
++
++ /* Allocate the page table. */
++ mmu->pageTableSize = MmuSize;
++ status = gckOS_AllocateContiguous(os,
++ gcvFALSE,
++ &mmu->pageTableSize,
++ &mmu->pageTablePhysical,
++ &mmu->pageTableLogical);
++
++ if (status < 0)
++ {
++ /* Roll back. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(os, mmu->mutex));
++
++ mmu->object.type = gcvOBJ_UNKNOWN;
++ gcmkVERIFY_OK(gckOS_Free(os, mmu));
++
++ /* Error. */
++ gcmkFATAL(
++ "%s(%d): could not allocate page table.",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkFOOTER();
++ return status;
++ }
++
++ /* Compute number of entries in page table. */
++ mmu->entryCount = mmu->pageTableSize / sizeof(gctUINT32);
++ mmu->entry = 0;
++
++ /* Mark the entire page table as available. */
++ pageTable = (gctUINT32 *) mmu->pageTableLogical;
++ for (i = 0; i < mmu->entryCount; i++)
++ {
++ pageTable[i] = (gctUINT32)~0;
++ }
++
++ /* Set page table address. */
++ status = gckVGHARDWARE_SetMMU(hardware, mmu->pageTableLogical);
++
++ if (status < 0)
++ {
++ /* Free the page table. */
++ gcmkVERIFY_OK(gckOS_FreeContiguous(mmu->os,
++ mmu->pageTablePhysical,
++ mmu->pageTableLogical,
++ mmu->pageTableSize));
++
++ /* Roll back. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(os, mmu->mutex));
++
++ mmu->object.type = gcvOBJ_UNKNOWN;
++ gcmkVERIFY_OK(gckOS_Free(os, mmu));
++
++ /* Error. */
++ gcmkFATAL(
++ "%s(%d): could not program page table.",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkFOOTER();
++ return status;
++ }
++
++ /* Return the gckVGMMU object pointer. */
++ *Mmu = mmu;
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_MMU,
++ "%s(%d): %u entries at %p.(0x%08X)\n",
++ __FUNCTION__, __LINE__,
++ mmu->entryCount,
++ mmu->pageTableLogical,
++ mmu->pageTablePhysical
++ );
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGMMU_Destroy
++**
++** Destroy a nAQMMU object.
++**
++** INPUT:
++**
++** gckVGMMU Mmu
++** Pointer to an gckVGMMU object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS gckVGMMU_Destroy(
++ IN gckVGMMU Mmu
++ )
++{
++ gcmkHEADER_ARG("Mmu=0x%x", Mmu);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Mmu, gcvOBJ_MMU);
++
++ /* Free the page table. */
++ gcmkVERIFY_OK(gckOS_FreeContiguous(Mmu->os,
++ Mmu->pageTablePhysical,
++ Mmu->pageTableLogical,
++ Mmu->pageTableSize));
++
++ /* Roll back. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Mmu->os, Mmu->mutex));
++
++ /* Mark the gckVGMMU object as unknown. */
++ Mmu->object.type = gcvOBJ_UNKNOWN;
++
++ /* Free the gckVGMMU object. */
++ gcmkVERIFY_OK(gckOS_Free(Mmu->os, Mmu));
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGMMU_AllocatePages
++**
++** Allocate pages inside the page table.
++**
++** INPUT:
++**
++** gckVGMMU Mmu
++** Pointer to an gckVGMMU object.
++**
++** gctSIZE_T PageCount
++** Number of pages to allocate.
++**
++** OUTPUT:
++**
++** gctPOINTER * PageTable
++** Pointer to a variable that receives the base address of the page
++** table.
++**
++** gctUINT32 * Address
++** Pointer to a variable that receives the hardware specific address.
++*/
++gceSTATUS gckVGMMU_AllocatePages(
++ IN gckVGMMU Mmu,
++ IN gctSIZE_T PageCount,
++ OUT gctPOINTER * PageTable,
++ OUT gctUINT32 * Address
++ )
++{
++ gceSTATUS status;
++ gctUINT32 tail, index, i;
++ gctUINT32 * table;
++ gctBOOL allocated = gcvFALSE;
++
++ gcmkHEADER_ARG("Mmu=0x%x PageCount=0x%x PageTable=0x%x Address=0x%x",
++ Mmu, PageCount, PageTable, Address);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Mmu, gcvOBJ_MMU);
++ gcmkVERIFY_ARGUMENT(PageCount > 0);
++ gcmkVERIFY_ARGUMENT(PageTable != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Address != gcvNULL);
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_MMU,
++ "%s(%d): %u pages.\n",
++ __FUNCTION__, __LINE__,
++ PageCount
++ );
++
++ if (PageCount > Mmu->entryCount)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_MMU,
++ "%s(%d): page table too small for %u pages.\n",
++ __FUNCTION__, __LINE__,
++ PageCount
++ );
++
++ gcmkFOOTER_NO();
++ /* Not enough pages avaiable. */
++ return gcvSTATUS_OUT_OF_RESOURCES;
++ }
++
++ /* Grab the mutex. */
++ status = gckOS_AcquireMutex(Mmu->os, Mmu->mutex, gcvINFINITE);
++
++ if (status < 0)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_MMU,
++ "%s(%d): could not acquire mutex.\n"
++ ,__FUNCTION__, __LINE__
++ );
++
++ gcmkFOOTER();
++ /* Error. */
++ return status;
++ }
++
++ /* Compute the tail for this allocation. */
++ tail = Mmu->entryCount - PageCount;
++
++ /* Walk all entries until we find enough slots. */
++ for (index = Mmu->entry; index <= tail;)
++ {
++ /* Access page table. */
++ table = (gctUINT32 *) Mmu->pageTableLogical + index;
++
++ /* See if all slots are available. */
++ for (i = 0; i < PageCount; i++, table++)
++ {
++ if (*table != ~0)
++ {
++ /* Start from next slot. */
++ index += i + 1;
++ break;
++ }
++ }
++
++ if (i == PageCount)
++ {
++ /* Bail out if we have enough page entries. */
++ allocated = gcvTRUE;
++ break;
++ }
++ }
++
++ if (!allocated)
++ {
++ if (status >= 0)
++ {
++ /* Walk all entries until we find enough slots. */
++ for (index = 0; index <= tail;)
++ {
++ /* Access page table. */
++ table = (gctUINT32 *) Mmu->pageTableLogical + index;
++
++ /* See if all slots are available. */
++ for (i = 0; i < PageCount; i++, table++)
++ {
++ if (*table != ~0)
++ {
++ /* Start from next slot. */
++ index += i + 1;
++ break;
++ }
++ }
++
++ if (i == PageCount)
++ {
++ /* Bail out if we have enough page entries. */
++ allocated = gcvTRUE;
++ break;
++ }
++ }
++ }
++ }
++
++ if (!allocated && (status >= 0))
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_MMU,
++ "%s(%d): not enough free pages for %u pages.\n",
++ __FUNCTION__, __LINE__,
++ PageCount
++ );
++
++ /* Not enough empty slots available. */
++ status = gcvSTATUS_OUT_OF_RESOURCES;
++ }
++
++ if (status >= 0)
++ {
++ /* Build virtual address. */
++ status = gckVGHARDWARE_BuildVirtualAddress(Mmu->hardware,
++ index,
++ 0,
++ Address);
++
++ if (status >= 0)
++ {
++ /* Update current entry into page table. */
++ Mmu->entry = index + PageCount;
++
++ /* Return pointer to page table. */
++ *PageTable = (gctUINT32 *) Mmu->pageTableLogical + index;
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_MMU,
++ "%s(%d): allocated %u pages at index %u (0x%08X) @ %p.\n",
++ __FUNCTION__, __LINE__,
++ PageCount,
++ index,
++ *Address,
++ *PageTable
++ );
++ }
++ }
++
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Mmu->os, Mmu->mutex));
++ gcmkFOOTER();
++
++ /* Return status. */
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckVGMMU_FreePages
++**
++** Free pages inside the page table.
++**
++** INPUT:
++**
++** gckVGMMU Mmu
++** Pointer to an gckVGMMU object.
++**
++** gctPOINTER PageTable
++** Base address of the page table to free.
++**
++** gctSIZE_T PageCount
++** Number of pages to free.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS gckVGMMU_FreePages(
++ IN gckVGMMU Mmu,
++ IN gctPOINTER PageTable,
++ IN gctSIZE_T PageCount
++ )
++{
++ gctUINT32 * table;
++
++ gcmkHEADER_ARG("Mmu=0x%x PageTable=0x%x PageCount=0x%x",
++ Mmu, PageTable, PageCount);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Mmu, gcvOBJ_MMU);
++ gcmkVERIFY_ARGUMENT(PageTable != gcvNULL);
++ gcmkVERIFY_ARGUMENT(PageCount > 0);
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_MMU,
++ "%s(%d): freeing %u pages at index %u @ %p.\n",
++ __FUNCTION__, __LINE__,
++ PageCount,
++ ((gctUINT32 *) PageTable - (gctUINT32 *) Mmu->pageTableLogical),
++ PageTable
++ );
++
++ /* Convert pointer. */
++ table = (gctUINT32 *) PageTable;
++
++ /* Mark the page table entries as available. */
++ while (PageCount-- > 0)
++ {
++ *table++ = (gctUINT32)~0;
++ }
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckVGMMU_SetPage(
++ IN gckVGMMU Mmu,
++ IN gctUINT32 PageAddress,
++ IN gctUINT32 *PageEntry
++ )
++{
++ gcmkHEADER_ARG("Mmu=0x%x", Mmu);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Mmu, gcvOBJ_MMU);
++ gcmkVERIFY_ARGUMENT(PageEntry != gcvNULL);
++ gcmkVERIFY_ARGUMENT(!(PageAddress & 0xFFF));
++
++ *PageEntry = PageAddress;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckVGMMU_Flush(
++ IN gckVGMMU Mmu
++ )
++{
++ gckVGHARDWARE hardware;
++
++ gcmkHEADER_ARG("Mmu=0x%x", Mmu);
++
++ hardware = Mmu->hardware;
++ gcmkVERIFY_OK(
++ gckOS_AtomSet(hardware->os, hardware->pageTableDirty, 1));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++#endif /* gcdENABLE_VG */
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_power.c linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_power.c
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_power.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_power.c 2015-07-27 23:13:06.194879670 +0200
+@@ -0,0 +1,347 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_precomp.h"
++
++#define _GC_OBJ_ZONE gcvZONE_POWER
++
++/******************************************************************************\
++************************ Dynamic Voltage Frequency Setting *********************
++\******************************************************************************/
++#if gcdDVFS
++static gctUINT32
++_GetLoadHistory(
++ IN gckDVFS Dvfs,
++ IN gctUINT32 Select,
++ IN gctUINT32 Index
++)
++{
++ return Dvfs->loads[Index];
++}
++
++static void
++_IncreaseScale(
++ IN gckDVFS Dvfs,
++ IN gctUINT32 Load,
++ OUT gctUINT8 *Scale
++ )
++{
++ if (Dvfs->currentScale < 32)
++ {
++ *Scale = Dvfs->currentScale + 8;
++ }
++ else
++ {
++ *Scale = Dvfs->currentScale + 8;
++ *Scale = gcmMIN(64, *Scale);
++ }
++}
++
++static void
++_RecordFrequencyHistory(
++ gckDVFS Dvfs,
++ gctUINT32 Frequency
++ )
++{
++ gctUINT32 i = 0;
++
++ struct _FrequencyHistory *history = Dvfs->frequencyHistory;
++
++ for (i = 0; i < 16; i++)
++ {
++ if (history->frequency == Frequency)
++ {
++ break;
++ }
++
++ if (history->frequency == 0)
++ {
++ history->frequency = Frequency;
++ break;
++ }
++
++ history++;
++ }
++
++ if (i < 16)
++ {
++ history->count++;
++ }
++}
++
++static gctUINT32
++_GetFrequencyHistory(
++ gckDVFS Dvfs,
++ gctUINT32 Frequency
++ )
++{
++ gctUINT32 i = 0;
++
++ struct _FrequencyHistory * history = Dvfs->frequencyHistory;
++
++ for (i = 0; i < 16; i++)
++ {
++ if (history->frequency == Frequency)
++ {
++ break;
++ }
++
++ history++;
++ }
++
++ if (i < 16)
++ {
++ return history->count;
++ }
++
++ return 0;
++}
++
++static void
++_Policy(
++ IN gckDVFS Dvfs,
++ IN gctUINT32 Load,
++ OUT gctUINT8 *Scale
++ )
++{
++ gctUINT8 load[4], nextLoad;
++ gctUINT8 scale;
++
++ /* Last 4 history. */
++ load[0] = (Load & 0xFF);
++ load[1] = (Load & 0xFF00) >> 8;
++ load[2] = (Load & 0xFF0000) >> 16;
++ load[3] = (Load & 0xFF000000) >> 24;
++
++ /* Determine target scale. */
++ if (load[0] > 54)
++ {
++ _IncreaseScale(Dvfs, Load, &scale);
++ }
++ else
++ {
++ nextLoad = (load[0] + load[1] + load[2] + load[3])/4;
++
++ scale = Dvfs->currentScale * (nextLoad) / 54;
++
++ scale = gcmMAX(1, scale);
++ scale = gcmMIN(64, scale);
++ }
++
++ Dvfs->totalConfig++;
++
++ Dvfs->loads[(load[0]-1)/8]++;
++
++ *Scale = scale;
++
++
++ if (Dvfs->totalConfig % 100 == 0)
++ {
++ gcmkPRINT("=======================================================");
++ gcmkPRINT("GPU Load: %-8d %-8d %-8d %-8d %-8d %-8d %-8d %-8d",
++ 8, 16, 24, 32, 40, 48, 56, 64);
++ gcmkPRINT(" %-8d %-8d %-8d %-8d %-8d %-8d %-8d %-8d",
++ _GetLoadHistory(Dvfs,2, 0),
++ _GetLoadHistory(Dvfs,2, 1),
++ _GetLoadHistory(Dvfs,2, 2),
++ _GetLoadHistory(Dvfs,2, 3),
++ _GetLoadHistory(Dvfs,2, 4),
++ _GetLoadHistory(Dvfs,2, 5),
++ _GetLoadHistory(Dvfs,2, 6),
++ _GetLoadHistory(Dvfs,2, 7)
++ );
++
++ gcmkPRINT("Frequency(MHz) %-8d %-8d %-8d %-8d %-8d",
++ 58, 120, 240, 360, 480);
++ gcmkPRINT(" %-8d %-8d %-8d %-8d %-8d",
++ _GetFrequencyHistory(Dvfs, 58),
++ _GetFrequencyHistory(Dvfs,120),
++ _GetFrequencyHistory(Dvfs,240),
++ _GetFrequencyHistory(Dvfs,360),
++ _GetFrequencyHistory(Dvfs,480)
++ );
++ }
++}
++
++static void
++_TimerFunction(
++ gctPOINTER Data
++ )
++{
++ gceSTATUS status;
++ gckDVFS dvfs = (gckDVFS) Data;
++ gckHARDWARE hardware = dvfs->hardware;
++ gctUINT32 value;
++ gctUINT32 frequency;
++ gctUINT8 scale;
++ gctUINT32 t1, t2, consumed;
++
++ gckOS_GetTicks(&t1);
++
++ gcmkONERROR(gckHARDWARE_QueryLoad(hardware, &value));
++
++ /* determine target sacle. */
++ _Policy(dvfs, value, &scale);
++
++ /* Set frequency and voltage. */
++ gcmkONERROR(gckOS_SetGPUFrequency(hardware->os, hardware->core, scale));
++
++ /* Query real frequency. */
++ gcmkONERROR(
++ gckOS_QueryGPUFrequency(hardware->os,
++ hardware->core,
++ &frequency,
++ &dvfs->currentScale));
++
++ _RecordFrequencyHistory(dvfs, frequency);
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_POWER,
++ "Current frequency = %d",
++ frequency);
++
++ /* Set period. */
++ gcmkONERROR(gckHARDWARE_SetDVFSPeroid(hardware, frequency));
++
++OnError:
++ /* Determine next querying time. */
++ gckOS_GetTicks(&t2);
++
++ consumed = gcmMIN(((long)t2 - (long)t1), 5);
++
++ if (dvfs->stop == gcvFALSE)
++ {
++ gcmkVERIFY_OK(gckOS_StartTimer(hardware->os,
++ dvfs->timer,
++ dvfs->pollingTime - consumed));
++ }
++
++ return;
++}
++
++gceSTATUS
++gckDVFS_Construct(
++ IN gckHARDWARE Hardware,
++ OUT gckDVFS * Dvfs
++ )
++{
++ gceSTATUS status;
++ gctPOINTER pointer;
++ gckDVFS dvfs = gcvNULL;
++ gckOS os = Hardware->os;
++
++ gcmkHEADER_ARG("Hardware=0x%X", Hardware);
++
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(Dvfs != gcvNULL);
++
++ /* Allocate a gckDVFS manager. */
++ gcmkONERROR(gckOS_Allocate(os, gcmSIZEOF(struct _gckDVFS), &pointer));
++
++ gckOS_ZeroMemory(pointer, gcmSIZEOF(struct _gckDVFS));
++
++ dvfs = pointer;
++
++ /* Initialization. */
++ dvfs->hardware = Hardware;
++ dvfs->pollingTime = gcdDVFS_POLLING_TIME;
++ dvfs->os = Hardware->os;
++ dvfs->currentScale = 64;
++
++ /* Create a polling timer. */
++ gcmkONERROR(gckOS_CreateTimer(os, _TimerFunction, pointer, &dvfs->timer));
++
++ /* Initialize frequency and voltage adjustment helper. */
++ gcmkONERROR(gckOS_PrepareGPUFrequency(os, Hardware->core));
++
++ /* Return result. */
++ *Dvfs = dvfs;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Roll back. */
++ if (dvfs)
++ {
++ if (dvfs->timer)
++ {
++ gcmkVERIFY_OK(gckOS_DestroyTimer(os, dvfs->timer));
++ }
++
++ gcmkOS_SAFE_FREE(os, dvfs);
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckDVFS_Destroy(
++ IN gckDVFS Dvfs
++ )
++{
++ gcmkHEADER_ARG("Dvfs=0x%X", Dvfs);
++ gcmkVERIFY_ARGUMENT(Dvfs != gcvNULL);
++
++ /* Deinitialize helper fuunction. */
++ gcmkVERIFY_OK(gckOS_FinishGPUFrequency(Dvfs->os, Dvfs->hardware->core));
++
++ /* DestroyTimer. */
++ gcmkVERIFY_OK(gckOS_DestroyTimer(Dvfs->os, Dvfs->timer));
++
++ gcmkOS_SAFE_FREE(Dvfs->os, Dvfs);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckDVFS_Start(
++ IN gckDVFS Dvfs
++ )
++{
++ gcmkHEADER_ARG("Dvfs=0x%X", Dvfs);
++ gcmkVERIFY_ARGUMENT(Dvfs != gcvNULL);
++
++ gckHARDWARE_InitDVFS(Dvfs->hardware);
++
++ Dvfs->stop = gcvFALSE;
++
++ gckOS_StartTimer(Dvfs->os, Dvfs->timer, Dvfs->pollingTime);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckDVFS_Stop(
++ IN gckDVFS Dvfs
++ )
++{
++ gcmkHEADER_ARG("Dvfs=0x%X", Dvfs);
++ gcmkVERIFY_ARGUMENT(Dvfs != gcvNULL);
++
++ Dvfs->stop = gcvTRUE;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++#endif
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_precomp.h linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_precomp.h
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_precomp.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_precomp.h 2015-07-27 23:13:06.194879670 +0200
+@@ -0,0 +1,29 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_kernel_precomp_h_
++#define __gc_hal_kernel_precomp_h_
++
++#include "gc_hal.h"
++#include "gc_hal_driver.h"
++#include "gc_hal_kernel.h"
++
++#endif /* __gc_hal_kernel_precomp_h_ */
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_security.c linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_security.c
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_security.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_security.c 2015-07-27 23:13:06.194879670 +0200
+@@ -0,0 +1,239 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_precomp.h"
++
++
++
++
++#define _GC_OBJ_ZONE gcvZONE_KERNEL
++
++#if gcdSECURITY
++
++/*
++** Open a security service channel.
++*/
++gceSTATUS
++gckKERNEL_SecurityOpen(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 GPU,
++ OUT gctUINT32 *Channel
++ )
++{
++ gceSTATUS status;
++
++ gcmkONERROR(gckOS_OpenSecurityChannel(Kernel->os, Kernel->core, Channel));
++ gcmkONERROR(gckOS_InitSecurityChannel(*Channel));
++
++ return gcvSTATUS_OK;
++
++OnError:
++ return status;
++}
++
++/*
++** Close a security service channel
++*/
++gceSTATUS
++gckKERNEL_SecurityClose(
++ IN gctUINT32 Channel
++ )
++{
++ return gcvSTATUS_OK;
++}
++
++/*
++** Security service interface.
++*/
++gceSTATUS
++gckKERNEL_SecurityCallService(
++ IN gctUINT32 Channel,
++ IN OUT gcsTA_INTERFACE * Interface
++)
++{
++ gceSTATUS status;
++ gcmkHEADER();
++
++ gcmkVERIFY_ARGUMENT(Interface != gcvNULL);
++
++ gckOS_CallSecurityService(Channel, Interface);
++
++ status = Interface->result;
++
++ gcmkONERROR(status);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckKERNEL_SecurityStartCommand(
++ IN gckKERNEL Kernel
++ )
++{
++ gceSTATUS status;
++ gcsTA_INTERFACE iface;
++
++ gcmkHEADER();
++
++ iface.command = KERNEL_START_COMMAND;
++ iface.u.StartCommand.gpu = Kernel->core;
++
++ gcmkONERROR(gckKERNEL_SecurityCallService(Kernel->securityChannel, &iface));
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckKERNEL_SecurityAllocateSecurityMemory(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 Bytes,
++ OUT gctUINT32 * Handle
++ )
++{
++ gceSTATUS status;
++ gcsTA_INTERFACE iface;
++
++ gcmkHEADER();
++
++ iface.command = KERNEL_ALLOCATE_SECRUE_MEMORY;
++ iface.u.AllocateSecurityMemory.bytes = Bytes;
++
++ gcmkONERROR(gckKERNEL_SecurityCallService(Kernel->securityChannel, &iface));
++
++ *Handle = iface.u.AllocateSecurityMemory.memory_handle;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckKERNEL_SecurityExecute(
++ IN gckKERNEL Kernel,
++ IN gctPOINTER Buffer,
++ IN gctUINT32 Bytes
++ )
++{
++ gceSTATUS status;
++ gcsTA_INTERFACE iface;
++
++ gcmkHEADER();
++
++ iface.command = KERNEL_EXECUTE;
++ iface.u.Execute.command_buffer = (gctUINT32 *)Buffer;
++ iface.u.Execute.gpu = Kernel->core;
++ iface.u.Execute.command_buffer_length = Bytes;
++
++#if defined(LINUX)
++ gcmkONERROR(gckOS_GetPhysicalAddress(Kernel->os, Buffer,
++ (gctUINT32 *)&iface.u.Execute.command_buffer));
++#endif
++
++ gcmkONERROR(gckKERNEL_SecurityCallService(Kernel->securityChannel, &iface));
++
++ /* Update queue tail pointer. */
++ gcmkONERROR(gckHARDWARE_UpdateQueueTail(
++ Kernel->hardware, 0, 0
++ ));
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckKERNEL_SecurityMapMemory(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 *PhysicalArray,
++ IN gctUINT32 PageCount,
++ OUT gctUINT32 * GPUAddress
++ )
++{
++ gceSTATUS status;
++ gcsTA_INTERFACE iface;
++
++ gcmkHEADER();
++
++ iface.command = KERNEL_MAP_MEMORY;
++
++#if defined(LINUX)
++ gcmkONERROR(gckOS_GetPhysicalAddress(Kernel->os, PhysicalArray,
++ (gctUINT32 *)&iface.u.MapMemory.physicals));
++#endif
++
++ iface.u.MapMemory.pageCount = PageCount;
++
++ gcmkONERROR(gckKERNEL_SecurityCallService(Kernel->securityChannel, &iface));
++
++ *GPUAddress = iface.u.MapMemory.gpuAddress;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckKERNEL_SecurityUnmapMemory(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 GPUAddress,
++ IN gctUINT32 PageCount
++ )
++{
++ gceSTATUS status;
++ gcsTA_INTERFACE iface;
++
++ gcmkHEADER();
++
++ iface.command = KERNEL_UNMAP_MEMORY;
++
++ iface.u.UnmapMemory.gpuAddress = GPUAddress;
++ iface.u.UnmapMemory.pageCount = PageCount;
++
++ gcmkONERROR(gckKERNEL_SecurityCallService(Kernel->securityChannel, &iface));
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++#endif
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_vg.c linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_vg.c
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_vg.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_vg.c 2015-07-27 23:13:06.194879670 +0200
+@@ -0,0 +1,896 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_precomp.h"
++
++#if gcdENABLE_VG
++
++#define ENABLE_VG_TRY_VIRTUAL_MEMORY 0
++
++#define _GC_OBJ_ZONE gcvZONE_VG
++
++/******************************************************************************\
++******************************* gckKERNEL API Code ******************************
++\******************************************************************************/
++
++/*******************************************************************************
++**
++** gckKERNEL_Construct
++**
++** Construct a new gckKERNEL object.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** IN gctPOINTER Context
++** Pointer to a driver defined context.
++**
++** OUTPUT:
++**
++** gckKERNEL * Kernel
++** Pointer to a variable that will hold the pointer to the gckKERNEL
++** object.
++*/
++gceSTATUS gckVGKERNEL_Construct(
++ IN gckOS Os,
++ IN gctPOINTER Context,
++ IN gckKERNEL inKernel,
++ OUT gckVGKERNEL * Kernel
++ )
++{
++ gceSTATUS status;
++ gckVGKERNEL kernel = gcvNULL;
++
++ gcmkHEADER_ARG("Os=0x%x Context=0x%x", Os, Context);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Kernel != gcvNULL);
++
++ do
++ {
++ /* Allocate the gckKERNEL object. */
++ gcmkERR_BREAK(gckOS_Allocate(
++ Os,
++ sizeof(struct _gckVGKERNEL),
++ (gctPOINTER *) &kernel
++ ));
++
++ /* Initialize the gckKERNEL object. */
++ kernel->object.type = gcvOBJ_KERNEL;
++ kernel->os = Os;
++ kernel->context = Context;
++ kernel->hardware = gcvNULL;
++ kernel->interrupt = gcvNULL;
++ kernel->command = gcvNULL;
++ kernel->mmu = gcvNULL;
++ kernel->kernel = inKernel;
++
++ /* Construct the gckVGHARDWARE object. */
++ gcmkERR_BREAK(gckVGHARDWARE_Construct(
++ Os, &kernel->hardware
++ ));
++
++ /* Set pointer to gckKERNEL object in gckVGHARDWARE object. */
++ kernel->hardware->kernel = kernel;
++
++ /* Construct the gckVGINTERRUPT object. */
++ gcmkERR_BREAK(gckVGINTERRUPT_Construct(
++ kernel, &kernel->interrupt
++ ));
++
++ /* Construct the gckVGCOMMAND object. */
++ gcmkERR_BREAK(gckVGCOMMAND_Construct(
++ kernel, gcmKB2BYTES(8), gcmKB2BYTES(2), &kernel->command
++ ));
++
++ /* Construct the gckVGMMU object. */
++ gcmkERR_BREAK(gckVGMMU_Construct(
++ kernel, gcmKB2BYTES(32), &kernel->mmu
++ ));
++
++ /* Return pointer to the gckKERNEL object. */
++ *Kernel = kernel;
++
++ gcmkFOOTER_ARG("*Kernel=0x%x", *Kernel);
++ /* Success. */
++ return gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ /* Roll back. */
++ if (kernel != gcvNULL)
++ {
++ if (kernel->mmu != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckVGMMU_Destroy(kernel->mmu));
++ }
++
++ if (kernel->command != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckVGCOMMAND_Destroy(kernel->command));
++ }
++
++ if (kernel->interrupt != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckVGINTERRUPT_Destroy(kernel->interrupt));
++ }
++
++ if (kernel->hardware != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckVGHARDWARE_Destroy(kernel->hardware));
++ }
++
++ gcmkVERIFY_OK(gckOS_Free(Os, kernel));
++ }
++
++ gcmkFOOTER();
++ /* Return status. */
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_Destroy
++**
++** Destroy an gckKERNEL object.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object to destroy.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS gckVGKERNEL_Destroy(
++ IN gckVGKERNEL Kernel
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Kernel=0x%x", Kernel);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++
++ do
++ {
++ /* Destroy the gckVGMMU object. */
++ if (Kernel->mmu != gcvNULL)
++ {
++ gcmkERR_BREAK(gckVGMMU_Destroy(Kernel->mmu));
++ Kernel->mmu = gcvNULL;
++ }
++
++ /* Destroy the gckVGCOMMAND object. */
++ if (Kernel->command != gcvNULL)
++ {
++ gcmkERR_BREAK(gckVGCOMMAND_Destroy(Kernel->command));
++ Kernel->command = gcvNULL;
++ }
++
++ /* Destroy the gckVGINTERRUPT object. */
++ if (Kernel->interrupt != gcvNULL)
++ {
++ gcmkERR_BREAK(gckVGINTERRUPT_Destroy(Kernel->interrupt));
++ Kernel->interrupt = gcvNULL;
++ }
++
++ /* Destroy the gckVGHARDWARE object. */
++ if (Kernel->hardware != gcvNULL)
++ {
++ gcmkERR_BREAK(gckVGHARDWARE_Destroy(Kernel->hardware));
++ Kernel->hardware = gcvNULL;
++ }
++
++ /* Mark the gckKERNEL object as unknown. */
++ Kernel->object.type = gcvOBJ_UNKNOWN;
++
++ /* Free the gckKERNEL object. */
++ gcmkERR_BREAK(gckOS_Free(Kernel->os, Kernel));
++ }
++ while (gcvFALSE);
++
++ gcmkFOOTER();
++
++ /* Return status. */
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_AllocateLinearMemory
++**
++** Function walks all required memory pools and allocates the requested
++** amount of video memory.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gcePOOL * Pool
++** Pointer the desired memory pool.
++**
++** gctSIZE_T Bytes
++** Number of bytes to allocate.
++**
++** gctSIZE_T Alignment
++** Required buffer alignment.
++**
++** gceSURF_TYPE Type
++** Surface type.
++**
++** OUTPUT:
++**
++** gcePOOL * Pool
++** Pointer to the actual pool where the memory was allocated.
++**
++** gcuVIDMEM_NODE_PTR * Node
++** Allocated node.
++*/
++gceSTATUS
++gckKERNEL_AllocateLinearMemory(
++ IN gckKERNEL Kernel,
++ IN OUT gcePOOL * Pool,
++ IN gctSIZE_T Bytes,
++ IN gctSIZE_T Alignment,
++ IN gceSURF_TYPE Type,
++ OUT gcuVIDMEM_NODE_PTR * Node
++ )
++{
++ gcePOOL pool;
++ gceSTATUS status;
++ gckVIDMEM videoMemory;
++
++ /* Get initial pool. */
++ switch (pool = *Pool)
++ {
++ case gcvPOOL_DEFAULT:
++ case gcvPOOL_LOCAL:
++ pool = gcvPOOL_LOCAL_INTERNAL;
++ break;
++
++ case gcvPOOL_UNIFIED:
++ pool = gcvPOOL_SYSTEM;
++ break;
++
++ default:
++ break;
++ }
++
++ do
++ {
++ /* Verify the number of bytes to allocate. */
++ if (Bytes == 0)
++ {
++ status = gcvSTATUS_INVALID_ARGUMENT;
++ break;
++ }
++
++ if (pool == gcvPOOL_VIRTUAL)
++ {
++ /* Create a gcuVIDMEM_NODE for virtual memory. */
++ gcmkERR_BREAK(gckVIDMEM_ConstructVirtual(Kernel, gcvFALSE, Bytes, Node));
++
++ /* Success. */
++ break;
++ }
++
++ else
++ {
++ /* Get pointer to gckVIDMEM object for pool. */
++ status = gckKERNEL_GetVideoMemoryPool(Kernel, pool, &videoMemory);
++
++ if (status == gcvSTATUS_OK)
++ {
++ if(*Pool == gcvPOOL_SYSTEM)
++ Type |= gcvSURF_VG;
++ /* Allocate memory. */
++ status = gckVIDMEM_AllocateLinear(Kernel,
++ videoMemory,
++ Bytes,
++ Alignment,
++ Type,
++ Node);
++
++ if (status == gcvSTATUS_OK)
++ {
++ /* Memory allocated. */
++ break;
++ }
++ }
++ }
++
++ if (pool == gcvPOOL_LOCAL_INTERNAL)
++ {
++ /* Advance to external memory. */
++ pool = gcvPOOL_LOCAL_EXTERNAL;
++ }
++ else if (pool == gcvPOOL_LOCAL_EXTERNAL)
++ {
++ /* Advance to contiguous system memory. */
++ pool = gcvPOOL_SYSTEM;
++ }
++ else if (pool == gcvPOOL_SYSTEM)
++ {
++ /* Advance to virtual memory. */
++#if ENABLE_VG_TRY_VIRTUAL_MEMORY
++ pool = gcvPOOL_VIRTUAL;
++#else
++ /*VG non-contiguous memory support is not ready yet, disable it temporary*/
++ status = gcvSTATUS_OUT_OF_MEMORY;
++ break;
++#endif
++ }
++ else
++ {
++ /* Out of pools. */
++ status = gcvSTATUS_OUT_OF_MEMORY;
++ break;
++ }
++ }
++ /* Loop only for multiple selection pools. */
++ while ((*Pool == gcvPOOL_DEFAULT)
++ || (*Pool == gcvPOOL_LOCAL)
++ || (*Pool == gcvPOOL_UNIFIED)
++ );
++
++ if (gcmIS_SUCCESS(status))
++ {
++ /* Return pool used for allocation. */
++ *Pool = pool;
++ }
++
++ /* Return status. */
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_Dispatch
++**
++** Dispatch a command received from the user HAL layer.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gcsHAL_INTERFACE * Interface
++** Pointer to a gcsHAL_INTERFACE structure that defines the command to
++** be dispatched.
++**
++** OUTPUT:
++**
++** gcsHAL_INTERFACE * Interface
++** Pointer to a gcsHAL_INTERFACE structure that receives any data to be
++** returned.
++*/
++gceSTATUS gckVGKERNEL_Dispatch(
++ IN gckKERNEL Kernel,
++ IN gctBOOL FromUser,
++ IN OUT gcsHAL_INTERFACE * Interface
++ )
++{
++ gceSTATUS status;
++ gcsHAL_INTERFACE * kernelInterface = Interface;
++ gcuVIDMEM_NODE_PTR node;
++ gctUINT32 processID;
++ gckKERNEL kernel = Kernel;
++ gctPOINTER info = gcvNULL;
++ gctPHYS_ADDR physical = gcvNULL;
++ gctPOINTER logical = gcvNULL;
++ gctSIZE_T bytes = 0;
++
++ gcmkHEADER_ARG("Kernel=0x%x Interface=0x%x ", Kernel, Interface);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(Interface != gcvNULL);
++
++ gcmkONERROR(gckOS_GetProcessID(&processID));
++
++ /* Dispatch on command. */
++ switch (Interface->command)
++ {
++ case gcvHAL_QUERY_VIDEO_MEMORY:
++ /* Query video memory size. */
++ gcmkERR_BREAK(gckKERNEL_QueryVideoMemory(
++ Kernel, kernelInterface
++ ));
++ break;
++
++ case gcvHAL_QUERY_CHIP_IDENTITY:
++ /* Query chip identity. */
++ gcmkERR_BREAK(gckVGHARDWARE_QueryChipIdentity(
++ Kernel->vg->hardware,
++ &kernelInterface->u.QueryChipIdentity.chipModel,
++ &kernelInterface->u.QueryChipIdentity.chipRevision,
++ &kernelInterface->u.QueryChipIdentity.chipFeatures,
++ &kernelInterface->u.QueryChipIdentity.chipMinorFeatures,
++ &kernelInterface->u.QueryChipIdentity.chipMinorFeatures2
++ ));
++ break;
++
++ case gcvHAL_QUERY_COMMAND_BUFFER:
++ /* Query command buffer information. */
++ gcmkERR_BREAK(gckKERNEL_QueryCommandBuffer(
++ Kernel,
++ &kernelInterface->u.QueryCommandBuffer.information
++ ));
++ break;
++ case gcvHAL_ALLOCATE_NON_PAGED_MEMORY:
++ bytes = (gctSIZE_T) kernelInterface->u.AllocateNonPagedMemory.bytes;
++ /* Allocate non-paged memory. */
++ gcmkERR_BREAK(gckOS_AllocateContiguous(
++ Kernel->os,
++ gcvTRUE,
++ &bytes,
++ &physical,
++ &logical
++ ));
++
++ kernelInterface->u.AllocateNonPagedMemory.bytes = bytes;
++ kernelInterface->u.AllocateNonPagedMemory.logical = gcmPTR_TO_UINT64(logical);
++ kernelInterface->u.AllocateNonPagedMemory.physical = gcmPTR_TO_NAME(physical);
++ break;
++
++ case gcvHAL_FREE_NON_PAGED_MEMORY:
++ physical = gcmNAME_TO_PTR(kernelInterface->u.AllocateNonPagedMemory.physical);
++
++ /* Unmap user logical out of physical memory first. */
++ gcmkERR_BREAK(gckOS_UnmapUserLogical(
++ Kernel->os,
++ physical,
++ (gctSIZE_T) kernelInterface->u.AllocateNonPagedMemory.bytes,
++ gcmUINT64_TO_PTR(kernelInterface->u.AllocateNonPagedMemory.logical)
++ ));
++
++ /* Free non-paged memory. */
++ gcmkERR_BREAK(gckOS_FreeNonPagedMemory(
++ Kernel->os,
++ (gctSIZE_T) kernelInterface->u.AllocateNonPagedMemory.bytes,
++ physical,
++ gcmUINT64_TO_PTR(kernelInterface->u.AllocateNonPagedMemory.logical)
++ ));
++
++ gcmRELEASE_NAME(kernelInterface->u.AllocateNonPagedMemory.physical);
++ break;
++
++ case gcvHAL_ALLOCATE_CONTIGUOUS_MEMORY:
++ bytes = (gctSIZE_T) kernelInterface->u.AllocateNonPagedMemory.bytes;
++ /* Allocate contiguous memory. */
++ gcmkERR_BREAK(gckOS_AllocateContiguous(
++ Kernel->os,
++ gcvTRUE,
++ &bytes,
++ &physical,
++ &logical
++ ));
++
++ kernelInterface->u.AllocateNonPagedMemory.bytes = bytes;
++ kernelInterface->u.AllocateNonPagedMemory.logical = gcmPTR_TO_UINT64(logical);
++ kernelInterface->u.AllocateNonPagedMemory.physical = gcmPTR_TO_NAME(physical);
++ break;
++
++ case gcvHAL_FREE_CONTIGUOUS_MEMORY:
++ physical = gcmNAME_TO_PTR(kernelInterface->u.AllocateNonPagedMemory.physical);
++ /* Unmap user logical out of physical memory first. */
++ gcmkERR_BREAK(gckOS_UnmapUserLogical(
++ Kernel->os,
++ physical,
++ (gctSIZE_T) kernelInterface->u.AllocateNonPagedMemory.bytes,
++ gcmUINT64_TO_PTR(kernelInterface->u.AllocateNonPagedMemory.logical)
++ ));
++
++ /* Free contiguous memory. */
++ gcmkERR_BREAK(gckOS_FreeContiguous(
++ Kernel->os,
++ physical,
++ gcmUINT64_TO_PTR(kernelInterface->u.AllocateNonPagedMemory.logical),
++ (gctSIZE_T) kernelInterface->u.AllocateNonPagedMemory.bytes
++ ));
++
++ gcmRELEASE_NAME(kernelInterface->u.AllocateNonPagedMemory.physical);
++ break;
++
++ case gcvHAL_ALLOCATE_VIDEO_MEMORY:
++ {
++ gctSIZE_T bytes;
++ gctUINT32 bitsPerPixel;
++ gctUINT32 bits;
++
++ /* Align width and height to tiles. */
++ gcmkERR_BREAK(gckVGHARDWARE_AlignToTile(
++ Kernel->vg->hardware,
++ kernelInterface->u.AllocateVideoMemory.type,
++ &kernelInterface->u.AllocateVideoMemory.width,
++ &kernelInterface->u.AllocateVideoMemory.height
++ ));
++
++ /* Convert format into bytes per pixel and bytes per tile. */
++ gcmkERR_BREAK(gckVGHARDWARE_ConvertFormat(
++ Kernel->vg->hardware,
++ kernelInterface->u.AllocateVideoMemory.format,
++ &bitsPerPixel,
++ gcvNULL
++ ));
++
++ /* Compute number of bits for the allocation. */
++ bits
++ = kernelInterface->u.AllocateVideoMemory.width
++ * kernelInterface->u.AllocateVideoMemory.height
++ * kernelInterface->u.AllocateVideoMemory.depth
++ * bitsPerPixel;
++
++ /* Compute number of bytes for the allocation. */
++ bytes = gcmALIGN(bits, 8) / 8;
++
++ /* Allocate memory. */
++ gcmkERR_BREAK(gckKERNEL_AllocateLinearMemory(
++ Kernel,
++ &kernelInterface->u.AllocateVideoMemory.pool,
++ bytes,
++ 64,
++ kernelInterface->u.AllocateVideoMemory.type,
++ &node
++ ));
++
++ kernelInterface->u.AllocateVideoMemory.node = gcmPTR_TO_UINT64(node);
++ }
++ break;
++
++ case gcvHAL_ALLOCATE_LINEAR_VIDEO_MEMORY:
++ /* Allocate memory. */
++ gcmkERR_BREAK(gckKERNEL_AllocateLinearMemory(
++ Kernel,
++ &kernelInterface->u.AllocateLinearVideoMemory.pool,
++ kernelInterface->u.AllocateLinearVideoMemory.bytes,
++ kernelInterface->u.AllocateLinearVideoMemory.alignment,
++ kernelInterface->u.AllocateLinearVideoMemory.type,
++ &node
++ ));
++
++ gcmkERR_BREAK(gckKERNEL_AddProcessDB(Kernel,
++ processID, gcvDB_VIDEO_MEMORY,
++ node,
++ gcvNULL,
++ kernelInterface->u.AllocateLinearVideoMemory.bytes
++ ));
++
++ kernelInterface->u.AllocateLinearVideoMemory.node = gcmPTR_TO_UINT64(node);
++ break;
++
++ case gcvHAL_FREE_VIDEO_MEMORY:
++ node = gcmUINT64_TO_PTR(Interface->u.FreeVideoMemory.node);
++#ifdef __QNXNTO__
++ /* Unmap the video memory */
++
++ if ((node->VidMem.memory->object.type == gcvOBJ_VIDMEM) &&
++ (node->VidMem.logical != gcvNULL))
++ {
++ gckKERNEL_UnmapVideoMemory(Kernel,
++ node->VidMem.logical,
++ processID,
++ node->VidMem.bytes);
++ node->VidMem.logical = gcvNULL;
++ }
++#endif /* __QNXNTO__ */
++
++ /* Free video memory. */
++ gcmkERR_BREAK(gckVIDMEM_Free(Kernel,
++ node
++ ));
++
++ gcmkERR_BREAK(gckKERNEL_RemoveProcessDB(
++ Kernel,
++ processID, gcvDB_VIDEO_MEMORY,
++ node
++ ));
++
++ break;
++
++ case gcvHAL_MAP_MEMORY:
++ /* Map memory. */
++ gcmkERR_BREAK(gckKERNEL_MapMemory(
++ Kernel,
++ gcmINT2PTR(kernelInterface->u.MapMemory.physical),
++ (gctSIZE_T) kernelInterface->u.MapMemory.bytes,
++ &logical
++ ));
++ kernelInterface->u.MapMemory.logical = gcmPTR_TO_UINT64(logical);
++ break;
++
++ case gcvHAL_UNMAP_MEMORY:
++ /* Unmap memory. */
++ gcmkERR_BREAK(gckKERNEL_UnmapMemory(
++ Kernel,
++ gcmINT2PTR(kernelInterface->u.MapMemory.physical),
++ (gctSIZE_T) kernelInterface->u.MapMemory.bytes,
++ gcmUINT64_TO_PTR(kernelInterface->u.MapMemory.logical)
++ ));
++ break;
++
++ case gcvHAL_MAP_USER_MEMORY:
++ /* Map user memory to DMA. */
++ gcmkERR_BREAK(gckOS_MapUserMemory(
++ Kernel->os,
++ gcvCORE_VG,
++ gcmUINT64_TO_PTR(kernelInterface->u.MapUserMemory.memory),
++ kernelInterface->u.MapUserMemory.physical,
++ (gctSIZE_T) kernelInterface->u.MapUserMemory.size,
++ &info,
++ &kernelInterface->u.MapUserMemory.address
++ ));
++
++ kernelInterface->u.MapUserMemory.info = gcmPTR_TO_NAME(info);
++ break;
++
++ case gcvHAL_UNMAP_USER_MEMORY:
++ /* Unmap user memory. */
++ gcmkERR_BREAK(gckOS_UnmapUserMemory(
++ Kernel->os,
++ gcvCORE_VG,
++ gcmUINT64_TO_PTR(kernelInterface->u.UnmapUserMemory.memory),
++ (gctSIZE_T) kernelInterface->u.UnmapUserMemory.size,
++ gcmNAME_TO_PTR(kernelInterface->u.UnmapUserMemory.info),
++ kernelInterface->u.UnmapUserMemory.address
++ ));
++ gcmRELEASE_NAME(kernelInterface->u.UnmapUserMemory.info);
++ break;
++ case gcvHAL_LOCK_VIDEO_MEMORY:
++ node = gcmUINT64_TO_PTR(Interface->u.LockVideoMemory.node);
++
++ /* Lock video memory. */
++ gcmkERR_BREAK(
++ gckVIDMEM_Lock(Kernel,
++ node,
++ gcvFALSE,
++ &Interface->u.LockVideoMemory.address));
++
++ if (node->VidMem.memory->object.type == gcvOBJ_VIDMEM)
++ {
++ /* Map video memory address into user space. */
++#ifdef __QNXNTO__
++ if (node->VidMem.logical == gcvNULL)
++ {
++ gcmkONERROR(
++ gckKERNEL_MapVideoMemory(Kernel,
++ FromUser,
++ Interface->u.LockVideoMemory.address,
++ processID,
++ node->VidMem.bytes,
++ &node->VidMem.logical));
++ }
++
++ Interface->u.LockVideoMemory.memory = gcmPTR_TO_UINT64(node->VidMem.logical);
++#else
++ gcmkERR_BREAK(
++ gckKERNEL_MapVideoMemoryEx(Kernel,
++ gcvCORE_VG,
++ FromUser,
++ Interface->u.LockVideoMemory.address,
++ &logical));
++ Interface->u.LockVideoMemory.memory = gcmPTR_TO_UINT64(logical);
++#endif
++ }
++ else
++ {
++ Interface->u.LockVideoMemory.memory = gcmPTR_TO_UINT64(node->Virtual.logical);
++
++ /* Success. */
++ status = gcvSTATUS_OK;
++ }
++
++#if gcdSECURE_USER
++ /* Return logical address as physical address. */
++ Interface->u.LockVideoMemory.address =
++ (gctUINT32)(Interface->u.LockVideoMemory.memory);
++#endif
++ gcmkERR_BREAK(
++ gckKERNEL_AddProcessDB(Kernel,
++ processID, gcvDB_VIDEO_MEMORY_LOCKED,
++ node,
++ gcvNULL,
++ 0));
++ break;
++
++ case gcvHAL_UNLOCK_VIDEO_MEMORY:
++ /* Unlock video memory. */
++ node = gcmUINT64_TO_PTR(Interface->u.UnlockVideoMemory.node);
++
++#if gcdSECURE_USER
++ /* Save node information before it disappears. */
++ if (node->VidMem.memory->object.type == gcvOBJ_VIDMEM)
++ {
++ logical = gcvNULL;
++ bytes = 0;
++ }
++ else
++ {
++ logical = node->Virtual.logical;
++ bytes = node->Virtual.bytes;
++ }
++#endif
++
++ /* Unlock video memory. */
++ gcmkERR_BREAK(
++ gckVIDMEM_Unlock(Kernel,
++ node,
++ Interface->u.UnlockVideoMemory.type,
++ &Interface->u.UnlockVideoMemory.asynchroneous));
++
++#if gcdSECURE_USER
++ /* Flush the translation cache for virtual surfaces. */
++ if (logical != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckKERNEL_FlushTranslationCache(Kernel,
++ cache,
++ logical,
++ bytes));
++ }
++#endif
++
++ if (Interface->u.UnlockVideoMemory.asynchroneous == gcvFALSE)
++ {
++ /* There isn't a event to unlock this node, remove record now */
++ gcmkERR_BREAK(
++ gckKERNEL_RemoveProcessDB(Kernel,
++ processID, gcvDB_VIDEO_MEMORY_LOCKED,
++ node));
++ }
++
++ break;
++ case gcvHAL_USER_SIGNAL:
++#if !USE_NEW_LINUX_SIGNAL
++ /* Dispatch depends on the user signal subcommands. */
++ switch(Interface->u.UserSignal.command)
++ {
++ case gcvUSER_SIGNAL_CREATE:
++ /* Create a signal used in the user space. */
++ gcmkERR_BREAK(
++ gckOS_CreateUserSignal(Kernel->os,
++ Interface->u.UserSignal.manualReset,
++ &Interface->u.UserSignal.id));
++
++ gcmkVERIFY_OK(
++ gckKERNEL_AddProcessDB(Kernel,
++ processID, gcvDB_SIGNAL,
++ gcmINT2PTR(Interface->u.UserSignal.id),
++ gcvNULL,
++ 0));
++ break;
++
++ case gcvUSER_SIGNAL_DESTROY:
++ /* Destroy the signal. */
++ gcmkERR_BREAK(
++ gckOS_DestroyUserSignal(Kernel->os,
++ Interface->u.UserSignal.id));
++
++ gcmkVERIFY_OK(gckKERNEL_RemoveProcessDB(
++ Kernel,
++ processID, gcvDB_SIGNAL,
++ gcmINT2PTR(Interface->u.UserSignal.id)));
++ break;
++
++ case gcvUSER_SIGNAL_SIGNAL:
++ /* Signal the signal. */
++ gcmkERR_BREAK(
++ gckOS_SignalUserSignal(Kernel->os,
++ Interface->u.UserSignal.id,
++ Interface->u.UserSignal.state));
++ break;
++
++ case gcvUSER_SIGNAL_WAIT:
++ /* Wait on the signal. */
++ status = gckOS_WaitUserSignal(Kernel->os,
++ Interface->u.UserSignal.id,
++ Interface->u.UserSignal.wait);
++ break;
++
++ default:
++ /* Invalid user signal command. */
++ gcmkERR_BREAK(gcvSTATUS_INVALID_ARGUMENT);
++ }
++#endif
++ break;
++
++ case gcvHAL_COMMIT:
++ /* Commit a command and context buffer. */
++ gcmkERR_BREAK(gckVGCOMMAND_Commit(
++ Kernel->vg->command,
++ gcmUINT64_TO_PTR(kernelInterface->u.VGCommit.context),
++ gcmUINT64_TO_PTR(kernelInterface->u.VGCommit.queue),
++ kernelInterface->u.VGCommit.entryCount,
++ gcmUINT64_TO_PTR(kernelInterface->u.VGCommit.taskTable)
++ ));
++ break;
++ case gcvHAL_VERSION:
++ kernelInterface->u.Version.major = gcvVERSION_MAJOR;
++ kernelInterface->u.Version.minor = gcvVERSION_MINOR;
++ kernelInterface->u.Version.patch = gcvVERSION_PATCH;
++ kernelInterface->u.Version.build = gcvVERSION_BUILD;
++ status = gcvSTATUS_OK;
++ break;
++
++ case gcvHAL_GET_BASE_ADDRESS:
++ /* Get base address. */
++ gcmkERR_BREAK(
++ gckOS_GetBaseAddress(Kernel->os,
++ &kernelInterface->u.GetBaseAddress.baseAddress));
++ break;
++ default:
++ /* Invalid command. */
++ status = gcvSTATUS_INVALID_ARGUMENT;
++ }
++
++OnError:
++ /* Save status. */
++ kernelInterface->status = status;
++
++ gcmkFOOTER();
++
++ /* Return the status. */
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_QueryCommandBuffer
++**
++** Query command buffer attributes.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckVGHARDWARE object.
++**
++** OUTPUT:
++**
++** gcsCOMMAND_BUFFER_INFO_PTR Information
++** Pointer to the information structure to receive buffer attributes.
++*/
++gceSTATUS
++gckKERNEL_QueryCommandBuffer(
++ IN gckKERNEL Kernel,
++ OUT gcsCOMMAND_BUFFER_INFO_PTR Information
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Kernel=0x%x *Pool=0x%x",
++ Kernel, Information);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++
++ /* Get the information. */
++ status = gckVGCOMMAND_QueryCommandBuffer(Kernel->vg->command, Information);
++
++ gcmkFOOTER();
++ /* Return status. */
++ return status;
++}
++
++#endif /* gcdENABLE_VG */
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_vg.h linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_vg.h
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_vg.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_vg.h 2015-07-27 23:13:06.194879670 +0200
+@@ -0,0 +1,85 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_kernel_vg_h_
++#define __gc_hal_kernel_vg_h_
++
++#include "gc_hal.h"
++#include "gc_hal_driver.h"
++#include "gc_hal_kernel_hardware.h"
++
++/******************************************************************************\
++********************************** Structures **********************************
++\******************************************************************************/
++
++/* gckKERNEL object. */
++struct _gckVGKERNEL
++{
++ /* Object. */
++ gcsOBJECT object;
++
++ /* Pointer to gckOS object. */
++ gckOS os;
++
++ /* Pointer to gckHARDWARE object. */
++ gckVGHARDWARE hardware;
++
++ /* Pointer to gckINTERRUPT object. */
++ gckVGINTERRUPT interrupt;
++
++ /* Pointer to gckCOMMAND object. */
++ gckVGCOMMAND command;
++
++ /* Pointer to context. */
++ gctPOINTER context;
++
++ /* Pointer to gckMMU object. */
++ gckVGMMU mmu;
++
++ gckKERNEL kernel;
++};
++
++/* gckMMU object. */
++struct _gckVGMMU
++{
++ /* The object. */
++ gcsOBJECT object;
++
++ /* Pointer to gckOS object. */
++ gckOS os;
++
++ /* Pointer to gckHARDWARE object. */
++ gckVGHARDWARE hardware;
++
++ /* The page table mutex. */
++ gctPOINTER mutex;
++
++ /* Page table information. */
++ gctSIZE_T pageTableSize;
++ gctPHYS_ADDR pageTablePhysical;
++ gctPOINTER pageTableLogical;
++
++ /* Allocation index. */
++ gctUINT32 entryCount;
++ gctUINT32 entry;
++};
++
++#endif /* __gc_hal_kernel_h_ */
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_video_memory.c linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_video_memory.c
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_video_memory.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_video_memory.c 2015-07-27 23:13:06.194879670 +0200
+@@ -0,0 +1,2229 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_precomp.h"
++
++#define _GC_OBJ_ZONE gcvZONE_VIDMEM
++
++/******************************************************************************\
++******************************* Private Functions ******************************
++\******************************************************************************/
++
++/*******************************************************************************
++**
++** _Split
++**
++** Split a node on the required byte boundary.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gcuVIDMEM_NODE_PTR Node
++** Pointer to the node to split.
++**
++** gctSIZE_T Bytes
++** Number of bytes to keep in the node.
++**
++** OUTPUT:
++**
++** Nothing.
++**
++** RETURNS:
++**
++** gctBOOL
++** gcvTRUE if the node was split successfully, or gcvFALSE if there is an
++** error.
++**
++*/
++static gctBOOL
++_Split(
++ IN gckOS Os,
++ IN gcuVIDMEM_NODE_PTR Node,
++ IN gctSIZE_T Bytes
++ )
++{
++ gcuVIDMEM_NODE_PTR node;
++ gctPOINTER pointer = gcvNULL;
++
++ /* Make sure the byte boundary makes sense. */
++ if ((Bytes <= 0) || (Bytes > Node->VidMem.bytes))
++ {
++ return gcvFALSE;
++ }
++
++ /* Allocate a new gcuVIDMEM_NODE object. */
++ if (gcmIS_ERROR(gckOS_Allocate(Os,
++ gcmSIZEOF(gcuVIDMEM_NODE),
++ &pointer)))
++ {
++ /* Error. */
++ return gcvFALSE;
++ }
++
++ node = pointer;
++
++ /* Initialize gcuVIDMEM_NODE structure. */
++ node->VidMem.offset = Node->VidMem.offset + Bytes;
++ node->VidMem.bytes = Node->VidMem.bytes - Bytes;
++ node->VidMem.alignment = 0;
++ node->VidMem.locked = 0;
++ node->VidMem.memory = Node->VidMem.memory;
++ node->VidMem.pool = Node->VidMem.pool;
++ node->VidMem.physical = Node->VidMem.physical;
++#ifdef __QNXNTO__
++#if gcdUSE_VIDMEM_PER_PID
++ gcmkASSERT(Node->VidMem.physical != 0);
++ gcmkASSERT(Node->VidMem.logical != gcvNULL);
++ node->VidMem.processID = Node->VidMem.processID;
++ node->VidMem.physical = Node->VidMem.physical + Bytes;
++ node->VidMem.logical = Node->VidMem.logical + Bytes;
++#else
++ node->VidMem.processID = 0;
++ node->VidMem.logical = gcvNULL;
++#endif
++#endif
++
++ /* Insert node behind specified node. */
++ node->VidMem.next = Node->VidMem.next;
++ node->VidMem.prev = Node;
++ Node->VidMem.next = node->VidMem.next->VidMem.prev = node;
++
++ /* Insert free node behind specified node. */
++ node->VidMem.nextFree = Node->VidMem.nextFree;
++ node->VidMem.prevFree = Node;
++ Node->VidMem.nextFree = node->VidMem.nextFree->VidMem.prevFree = node;
++
++ /* Adjust size of specified node. */
++ Node->VidMem.bytes = Bytes;
++
++ /* Success. */
++ return gcvTRUE;
++}
++
++/*******************************************************************************
++**
++** _Merge
++**
++** Merge two adjacent nodes together.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gcuVIDMEM_NODE_PTR Node
++** Pointer to the first of the two nodes to merge.
++**
++** OUTPUT:
++**
++** Nothing.
++**
++*/
++static gceSTATUS
++_Merge(
++ IN gckOS Os,
++ IN gcuVIDMEM_NODE_PTR Node
++ )
++{
++ gcuVIDMEM_NODE_PTR node;
++ gceSTATUS status;
++
++ /* Save pointer to next node. */
++ node = Node->VidMem.next;
++#if gcdUSE_VIDMEM_PER_PID
++ /* Check if the nodes are adjacent physically. */
++ if ( ((Node->VidMem.physical + Node->VidMem.bytes) != node->VidMem.physical) ||
++ ((Node->VidMem.logical + Node->VidMem.bytes) != node->VidMem.logical) )
++ {
++ /* Can't merge. */
++ return gcvSTATUS_OK;
++ }
++#else
++
++ /* This is a good time to make sure the heap is not corrupted. */
++ if (Node->VidMem.offset + Node->VidMem.bytes != node->VidMem.offset)
++ {
++ /* Corrupted heap. */
++ gcmkASSERT(
++ Node->VidMem.offset + Node->VidMem.bytes == node->VidMem.offset);
++ return gcvSTATUS_HEAP_CORRUPTED;
++ }
++#endif
++
++ /* Adjust byte count. */
++ Node->VidMem.bytes += node->VidMem.bytes;
++
++ /* Unlink next node from linked list. */
++ Node->VidMem.next = node->VidMem.next;
++ Node->VidMem.nextFree = node->VidMem.nextFree;
++
++ Node->VidMem.next->VidMem.prev =
++ Node->VidMem.nextFree->VidMem.prevFree = Node;
++
++ /* Free next node. */
++ status = gcmkOS_SAFE_FREE(Os, node);
++ return status;
++}
++
++/******************************************************************************\
++******************************* gckVIDMEM API Code ******************************
++\******************************************************************************/
++
++/*******************************************************************************
++**
++** gckVIDMEM_ConstructVirtual
++**
++** Construct a new gcuVIDMEM_NODE union for virtual memory.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gctSIZE_T Bytes
++** Number of byte to allocate.
++**
++** OUTPUT:
++**
++** gcuVIDMEM_NODE_PTR * Node
++** Pointer to a variable that receives the gcuVIDMEM_NODE union pointer.
++*/
++gceSTATUS
++gckVIDMEM_ConstructVirtual(
++ IN gckKERNEL Kernel,
++ IN gctBOOL Contiguous,
++ IN gctSIZE_T Bytes,
++ OUT gcuVIDMEM_NODE_PTR * Node
++ )
++{
++ gckOS os;
++ gceSTATUS status;
++ gcuVIDMEM_NODE_PTR node = gcvNULL;
++ gctPOINTER pointer = gcvNULL;
++ gctINT i;
++
++ gcmkHEADER_ARG("Kernel=0x%x Contiguous=%d Bytes=%lu", Kernel, Contiguous, Bytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++ gcmkVERIFY_ARGUMENT(Node != gcvNULL);
++
++ /* Extract the gckOS object pointer. */
++ os = Kernel->os;
++ gcmkVERIFY_OBJECT(os, gcvOBJ_OS);
++
++ /* Allocate an gcuVIDMEM_NODE union. */
++ gcmkONERROR(gckOS_Allocate(os, gcmSIZEOF(gcuVIDMEM_NODE), &pointer));
++
++ node = pointer;
++
++ /* Initialize gcuVIDMEM_NODE union for virtual memory. */
++ node->Virtual.kernel = Kernel;
++ node->Virtual.contiguous = Contiguous;
++ node->Virtual.logical = gcvNULL;
++
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ node->Virtual.lockeds[i] = 0;
++ node->Virtual.pageTables[i] = gcvNULL;
++ node->Virtual.lockKernels[i] = gcvNULL;
++ }
++
++ gcmkONERROR(gckOS_GetProcessID(&node->Virtual.processID));
++
++#ifdef __QNXNTO__
++ node->Virtual.next = gcvNULL;
++ node->Virtual.freePending = gcvFALSE;
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ node->Virtual.unlockPendings[i] = gcvFALSE;
++ }
++#endif
++
++ node->Virtual.freed = gcvFALSE;
++
++ gcmkONERROR(gckOS_ZeroMemory(&node->Virtual.sharedInfo, gcmSIZEOF(gcsVIDMEM_NODE_SHARED_INFO)));
++
++ /* Allocate the virtual memory. */
++ gcmkONERROR(
++ gckOS_AllocatePagedMemoryEx(os,
++ node->Virtual.contiguous,
++ node->Virtual.bytes = Bytes,
++ &node->Virtual.physical));
++
++#ifdef __QNXNTO__
++ /* Register. */
++#if gcdENABLE_VG
++ if (Kernel->core != gcvCORE_VG)
++#endif
++ {
++ gckMMU_InsertNode(Kernel->mmu, node);
++ }
++#endif
++
++ /* Return pointer to the gcuVIDMEM_NODE union. */
++ *Node = node;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM,
++ "Created virtual node 0x%x for %u bytes @ 0x%x",
++ node, Bytes, node->Virtual.physical);
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Node=0x%x", *Node);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Roll back. */
++ if (node != gcvNULL)
++ {
++ /* Free the structure. */
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(os, node));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckVIDMEM_DestroyVirtual
++**
++** Destroy an gcuVIDMEM_NODE union for virtual memory.
++**
++** INPUT:
++**
++** gcuVIDMEM_NODE_PTR Node
++** Pointer to a gcuVIDMEM_NODE union.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckVIDMEM_DestroyVirtual(
++ IN gcuVIDMEM_NODE_PTR Node
++ )
++{
++ gckOS os;
++ gctINT i;
++
++ gcmkHEADER_ARG("Node=0x%x", Node);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Node->Virtual.kernel, gcvOBJ_KERNEL);
++
++ /* Extact the gckOS object pointer. */
++ os = Node->Virtual.kernel->os;
++ gcmkVERIFY_OBJECT(os, gcvOBJ_OS);
++
++#ifdef __QNXNTO__
++ /* Unregister. */
++#if gcdENABLE_VG
++ if (Node->Virtual.kernel->core != gcvCORE_VG)
++#endif
++ {
++ gcmkVERIFY_OK(
++ gckMMU_RemoveNode(Node->Virtual.kernel->mmu, Node));
++ }
++#endif
++
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ if (Node->Virtual.pageTables[i] != gcvNULL)
++ {
++#if gcdENABLE_VG
++ if (i == gcvCORE_VG)
++ {
++ /* Free the pages. */
++ gcmkVERIFY_OK(gckVGMMU_FreePages(Node->Virtual.lockKernels[i]->vg->mmu,
++ Node->Virtual.pageTables[i],
++ Node->Virtual.pageCount));
++ }
++ else
++#endif
++ {
++ /* Free the pages. */
++ gcmkVERIFY_OK(gckMMU_FreePages(Node->Virtual.lockKernels[i]->mmu,
++ Node->Virtual.pageTables[i],
++ Node->Virtual.pageCount));
++ }
++ }
++ }
++
++ /* Delete the gcuVIDMEM_NODE union. */
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(os, Node));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVIDMEM_Construct
++**
++** Construct a new gckVIDMEM object.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctUINT32 BaseAddress
++** Base address for the video memory heap.
++**
++** gctSIZE_T Bytes
++** Number of bytes in the video memory heap.
++**
++** gctSIZE_T Threshold
++** Minimum number of bytes beyond am allocation before the node is
++** split. Can be used as a minimum alignment requirement.
++**
++** gctSIZE_T BankSize
++** Number of bytes per physical memory bank. Used by bank
++** optimization.
++**
++** OUTPUT:
++**
++** gckVIDMEM * Memory
++** Pointer to a variable that will hold the pointer to the gckVIDMEM
++** object.
++*/
++gceSTATUS
++gckVIDMEM_Construct(
++ IN gckOS Os,
++ IN gctUINT32 BaseAddress,
++ IN gctSIZE_T Bytes,
++ IN gctSIZE_T Threshold,
++ IN gctSIZE_T BankSize,
++ OUT gckVIDMEM * Memory
++ )
++{
++ gckVIDMEM memory = gcvNULL;
++ gceSTATUS status;
++ gcuVIDMEM_NODE_PTR node;
++ gctINT i, banks = 0;
++ gctPOINTER pointer = gcvNULL;
++
++ gcmkHEADER_ARG("Os=0x%x BaseAddress=%08x Bytes=%lu Threshold=%lu "
++ "BankSize=%lu",
++ Os, BaseAddress, Bytes, Threshold, BankSize);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++ gcmkVERIFY_ARGUMENT(Memory != gcvNULL);
++
++ /* Allocate the gckVIDMEM object. */
++ gcmkONERROR(gckOS_Allocate(Os, gcmSIZEOF(struct _gckVIDMEM), &pointer));
++
++ memory = pointer;
++
++ /* Initialize the gckVIDMEM object. */
++ memory->object.type = gcvOBJ_VIDMEM;
++ memory->os = Os;
++
++ /* Set video memory heap information. */
++ memory->baseAddress = BaseAddress;
++ memory->bytes = Bytes;
++ memory->freeBytes = Bytes;
++ memory->threshold = Threshold;
++#if gcdUSE_VIDMEM_PER_PID
++ gcmkONERROR(gckOS_GetProcessID(&memory->pid));
++#endif
++
++ BaseAddress = 0;
++
++ /* Walk all possible banks. */
++ for (i = 0; i < gcmCOUNTOF(memory->sentinel); ++i)
++ {
++ gctSIZE_T bytes;
++
++ if (BankSize == 0)
++ {
++ /* Use all bytes for the first bank. */
++ bytes = Bytes;
++ }
++ else
++ {
++ /* Compute number of bytes for this bank. */
++ bytes = gcmALIGN(BaseAddress + 1, BankSize) - BaseAddress;
++
++ if (bytes > Bytes)
++ {
++ /* Make sure we don't exceed the total number of bytes. */
++ bytes = Bytes;
++ }
++ }
++
++ if (bytes == 0)
++ {
++ /* Mark heap is not used. */
++ memory->sentinel[i].VidMem.next =
++ memory->sentinel[i].VidMem.prev =
++ memory->sentinel[i].VidMem.nextFree =
++ memory->sentinel[i].VidMem.prevFree = gcvNULL;
++ continue;
++ }
++
++ /* Allocate one gcuVIDMEM_NODE union. */
++ gcmkONERROR(gckOS_Allocate(Os, gcmSIZEOF(gcuVIDMEM_NODE), &pointer));
++
++ node = pointer;
++
++ /* Initialize gcuVIDMEM_NODE union. */
++ node->VidMem.memory = memory;
++
++ node->VidMem.next =
++ node->VidMem.prev =
++ node->VidMem.nextFree =
++ node->VidMem.prevFree = &memory->sentinel[i];
++
++ node->VidMem.offset = BaseAddress;
++ node->VidMem.bytes = bytes;
++ node->VidMem.alignment = 0;
++ node->VidMem.physical = 0;
++ node->VidMem.pool = gcvPOOL_UNKNOWN;
++
++ node->VidMem.locked = 0;
++
++#if gcdDYNAMIC_MAP_RESERVED_MEMORY && gcdENABLE_VG
++ node->VidMem.kernelVirtual = gcvNULL;
++#endif
++
++ gcmkONERROR(gckOS_ZeroMemory(&node->VidMem.sharedInfo, gcmSIZEOF(gcsVIDMEM_NODE_SHARED_INFO)));
++
++#ifdef __QNXNTO__
++#if gcdUSE_VIDMEM_PER_PID
++ node->VidMem.processID = memory->pid;
++ node->VidMem.physical = memory->baseAddress + BaseAddress;
++ gcmkONERROR(gckOS_GetLogicalAddressProcess(Os,
++ node->VidMem.processID,
++ node->VidMem.physical,
++ &node->VidMem.logical));
++#else
++ node->VidMem.processID = 0;
++ node->VidMem.logical = gcvNULL;
++#endif
++#endif
++
++ /* Initialize the linked list of nodes. */
++ memory->sentinel[i].VidMem.next =
++ memory->sentinel[i].VidMem.prev =
++ memory->sentinel[i].VidMem.nextFree =
++ memory->sentinel[i].VidMem.prevFree = node;
++
++ /* Mark sentinel. */
++ memory->sentinel[i].VidMem.bytes = 0;
++
++ /* Adjust address for next bank. */
++ BaseAddress += bytes;
++ Bytes -= bytes;
++ banks ++;
++ }
++
++ /* Assign all the bank mappings. */
++ memory->mapping[gcvSURF_RENDER_TARGET] = banks - 1;
++ memory->mapping[gcvSURF_BITMAP] = banks - 1;
++ if (banks > 1) --banks;
++ memory->mapping[gcvSURF_DEPTH] = banks - 1;
++ memory->mapping[gcvSURF_HIERARCHICAL_DEPTH] = banks - 1;
++ if (banks > 1) --banks;
++ memory->mapping[gcvSURF_TEXTURE] = banks - 1;
++ if (banks > 1) --banks;
++ memory->mapping[gcvSURF_VERTEX] = banks - 1;
++ if (banks > 1) --banks;
++ memory->mapping[gcvSURF_INDEX] = banks - 1;
++ if (banks > 1) --banks;
++ memory->mapping[gcvSURF_TILE_STATUS] = banks - 1;
++ if (banks > 1) --banks;
++ memory->mapping[gcvSURF_TYPE_UNKNOWN] = 0;
++
++#if gcdENABLE_VG
++ memory->mapping[gcvSURF_IMAGE] = 0;
++ memory->mapping[gcvSURF_MASK] = 0;
++ memory->mapping[gcvSURF_SCISSOR] = 0;
++#endif
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM,
++ "[GALCORE] INDEX: bank %d",
++ memory->mapping[gcvSURF_INDEX]);
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM,
++ "[GALCORE] VERTEX: bank %d",
++ memory->mapping[gcvSURF_VERTEX]);
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM,
++ "[GALCORE] TEXTURE: bank %d",
++ memory->mapping[gcvSURF_TEXTURE]);
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM,
++ "[GALCORE] RENDER_TARGET: bank %d",
++ memory->mapping[gcvSURF_RENDER_TARGET]);
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM,
++ "[GALCORE] DEPTH: bank %d",
++ memory->mapping[gcvSURF_DEPTH]);
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM,
++ "[GALCORE] TILE_STATUS: bank %d",
++ memory->mapping[gcvSURF_TILE_STATUS]);
++
++ /* Return pointer to the gckVIDMEM object. */
++ *Memory = memory;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Memory=0x%x", *Memory);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Roll back. */
++ if (memory != gcvNULL)
++ {
++ for (i = 0; i < banks; ++i)
++ {
++ /* Free the heap. */
++ gcmkASSERT(memory->sentinel[i].VidMem.next != gcvNULL);
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Os, memory->sentinel[i].VidMem.next));
++ }
++
++ /* Free the object. */
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Os, memory));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckVIDMEM_Destroy
++**
++** Destroy an gckVIDMEM object.
++**
++** INPUT:
++**
++** gckVIDMEM Memory
++** Pointer to an gckVIDMEM object to destroy.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckVIDMEM_Destroy(
++ IN gckVIDMEM Memory
++ )
++{
++ gcuVIDMEM_NODE_PTR node, next;
++ gctINT i;
++
++ gcmkHEADER_ARG("Memory=0x%x", Memory);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Memory, gcvOBJ_VIDMEM);
++
++ /* Walk all sentinels. */
++ for (i = 0; i < gcmCOUNTOF(Memory->sentinel); ++i)
++ {
++ /* Bail out of the heap is not used. */
++ if (Memory->sentinel[i].VidMem.next == gcvNULL)
++ {
++ break;
++ }
++
++ /* Walk all the nodes until we reach the sentinel. */
++ for (node = Memory->sentinel[i].VidMem.next;
++ node->VidMem.bytes != 0;
++ node = next)
++ {
++ /* Save pointer to the next node. */
++ next = node->VidMem.next;
++
++ /* Free the node. */
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Memory->os, node));
++ }
++ }
++
++ /* Mark the object as unknown. */
++ Memory->object.type = gcvOBJ_UNKNOWN;
++
++ /* Free the gckVIDMEM object. */
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Memory->os, Memory));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVIDMEM_Allocate
++**
++** Allocate rectangular memory from the gckVIDMEM object.
++**
++** INPUT:
++**
++** gckVIDMEM Memory
++** Pointer to an gckVIDMEM object.
++**
++** gctUINT Width
++** Width of rectangle to allocate. Make sure the width is properly
++** aligned.
++**
++** gctUINT Height
++** Height of rectangle to allocate. Make sure the height is properly
++** aligned.
++**
++** gctUINT Depth
++** Depth of rectangle to allocate. This equals to the number of
++** rectangles to allocate contiguously (i.e., for cubic maps and volume
++** textures).
++**
++** gctUINT BytesPerPixel
++** Number of bytes per pixel.
++**
++** gctUINT32 Alignment
++** Byte alignment for allocation.
++**
++** gceSURF_TYPE Type
++** Type of surface to allocate (use by bank optimization).
++**
++** OUTPUT:
++**
++** gcuVIDMEM_NODE_PTR * Node
++** Pointer to a variable that will hold the allocated memory node.
++*/
++gceSTATUS
++gckVIDMEM_Allocate(
++ IN gckKERNEL Kernel,
++ IN gckVIDMEM Memory,
++ IN gctUINT Width,
++ IN gctUINT Height,
++ IN gctUINT Depth,
++ IN gctUINT BytesPerPixel,
++ IN gctUINT32 Alignment,
++ IN gceSURF_TYPE Type,
++ OUT gcuVIDMEM_NODE_PTR * Node
++ )
++{
++ gctSIZE_T bytes;
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Memory=0x%x Width=%u Height=%u Depth=%u BytesPerPixel=%u "
++ "Alignment=%u Type=%d",
++ Memory, Width, Height, Depth, BytesPerPixel, Alignment,
++ Type);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Memory, gcvOBJ_VIDMEM);
++ gcmkVERIFY_ARGUMENT(Width > 0);
++ gcmkVERIFY_ARGUMENT(Height > 0);
++ gcmkVERIFY_ARGUMENT(Depth > 0);
++ gcmkVERIFY_ARGUMENT(BytesPerPixel > 0);
++ gcmkVERIFY_ARGUMENT(Node != gcvNULL);
++
++ /* Compute linear size. */
++ bytes = Width * Height * Depth * BytesPerPixel;
++
++ /* Allocate through linear function. */
++ gcmkONERROR(
++ gckVIDMEM_AllocateLinear(Kernel, Memory, bytes, Alignment, Type, Node));
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Node=0x%x", *Node);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++#if gcdENABLE_BANK_ALIGNMENT
++
++#if !gcdBANK_BIT_START
++#error gcdBANK_BIT_START not defined.
++#endif
++
++#if !gcdBANK_BIT_END
++#error gcdBANK_BIT_END not defined.
++#endif
++/*******************************************************************************
++** _GetSurfaceBankAlignment
++**
++** Return the required offset alignment required to the make BaseAddress
++** aligned properly.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to gcoOS object.
++**
++** gceSURF_TYPE Type
++** Type of allocation.
++**
++** gctUINT32 BaseAddress
++** Base address of current video memory node.
++**
++** OUTPUT:
++**
++** gctUINT32_PTR AlignmentOffset
++** Pointer to a variable that will hold the number of bytes to skip in
++** the current video memory node in order to make the alignment bank
++** aligned.
++*/
++static gceSTATUS
++_GetSurfaceBankAlignment(
++ IN gceSURF_TYPE Type,
++ IN gctUINT32 BaseAddress,
++ OUT gctUINT32_PTR AlignmentOffset
++ )
++{
++ gctUINT32 bank;
++ /* To retrieve the bank. */
++ static const gctUINT32 bankMask = (0xFFFFFFFF << gcdBANK_BIT_START)
++ ^ (0xFFFFFFFF << (gcdBANK_BIT_END + 1));
++
++ /* To retrieve the bank and all the lower bytes. */
++ static const gctUINT32 byteMask = ~(0xFFFFFFFF << (gcdBANK_BIT_END + 1));
++
++ gcmkHEADER_ARG("Type=%d BaseAddress=0x%x ", Type, BaseAddress);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_ARGUMENT(AlignmentOffset != gcvNULL);
++
++ switch (Type)
++ {
++ case gcvSURF_RENDER_TARGET:
++ bank = (BaseAddress & bankMask) >> (gcdBANK_BIT_START);
++
++ /* Align to the first bank. */
++ *AlignmentOffset = (bank == 0) ?
++ 0 :
++ ((1 << (gcdBANK_BIT_END + 1)) + 0) - (BaseAddress & byteMask);
++ break;
++
++ case gcvSURF_DEPTH:
++ bank = (BaseAddress & bankMask) >> (gcdBANK_BIT_START);
++
++ /* Align to the third bank. */
++ *AlignmentOffset = (bank == 2) ?
++ 0 :
++ ((1 << (gcdBANK_BIT_END + 1)) + (2 << gcdBANK_BIT_START)) - (BaseAddress & byteMask);
++
++ /* Add a channel offset at the channel bit. */
++ *AlignmentOffset += (1 << gcdBANK_CHANNEL_BIT);
++ break;
++
++ default:
++ /* no alignment needed. */
++ *AlignmentOffset = 0;
++ }
++
++ /* Return the status. */
++ gcmkFOOTER_ARG("*AlignmentOffset=%u", *AlignmentOffset);
++ return gcvSTATUS_OK;
++}
++#endif
++
++static gcuVIDMEM_NODE_PTR
++_FindNode(
++ IN gckVIDMEM Memory,
++ IN gctINT Bank,
++ IN gctSIZE_T Bytes,
++ IN gceSURF_TYPE Type,
++ IN OUT gctUINT32_PTR Alignment
++ )
++{
++ gcuVIDMEM_NODE_PTR node;
++ gctUINT32 alignment;
++
++#if gcdENABLE_BANK_ALIGNMENT
++ gctUINT32 bankAlignment;
++ gceSTATUS status;
++#endif
++
++ if (Memory->sentinel[Bank].VidMem.nextFree == gcvNULL)
++ {
++ /* No free nodes left. */
++ return gcvNULL;
++ }
++
++#if gcdENABLE_BANK_ALIGNMENT
++ /* Walk all free nodes until we have one that is big enough or we have
++ ** reached the sentinel. */
++ for (node = Memory->sentinel[Bank].VidMem.nextFree;
++ node->VidMem.bytes != 0;
++ node = node->VidMem.nextFree)
++ {
++ gcmkONERROR(_GetSurfaceBankAlignment(
++ Type,
++ node->VidMem.memory->baseAddress + node->VidMem.offset,
++ &bankAlignment));
++
++ bankAlignment = gcmALIGN(bankAlignment, *Alignment);
++
++ /* Compute number of bytes to skip for alignment. */
++ alignment = (*Alignment == 0)
++ ? 0
++ : (*Alignment - (node->VidMem.offset % *Alignment));
++
++ if (alignment == *Alignment)
++ {
++ /* Node is already aligned. */
++ alignment = 0;
++ }
++
++ if (node->VidMem.bytes >= Bytes + alignment + bankAlignment)
++ {
++ /* This node is big enough. */
++ *Alignment = alignment + bankAlignment;
++ return node;
++ }
++ }
++#endif
++
++ /* Walk all free nodes until we have one that is big enough or we have
++ reached the sentinel. */
++ for (node = Memory->sentinel[Bank].VidMem.nextFree;
++ node->VidMem.bytes != 0;
++ node = node->VidMem.nextFree)
++ {
++
++ gctINT modulo = gckMATH_ModuloInt(node->VidMem.offset, *Alignment);
++
++ /* Compute number of bytes to skip for alignment. */
++ alignment = (*Alignment == 0) ? 0 : (*Alignment - modulo);
++
++ if (alignment == *Alignment)
++ {
++ /* Node is already aligned. */
++ alignment = 0;
++ }
++
++ if (node->VidMem.bytes >= Bytes + alignment)
++ {
++ /* This node is big enough. */
++ *Alignment = alignment;
++ return node;
++ }
++ }
++
++#if gcdENABLE_BANK_ALIGNMENT
++OnError:
++#endif
++ /* Not enough memory. */
++ return gcvNULL;
++}
++
++/*******************************************************************************
++**
++** gckVIDMEM_AllocateLinear
++**
++** Allocate linear memory from the gckVIDMEM object.
++**
++** INPUT:
++**
++** gckVIDMEM Memory
++** Pointer to an gckVIDMEM object.
++**
++** gctSIZE_T Bytes
++** Number of bytes to allocate.
++**
++** gctUINT32 Alignment
++** Byte alignment for allocation.
++**
++** gceSURF_TYPE Type
++** Type of surface to allocate (use by bank optimization).
++**
++** OUTPUT:
++**
++** gcuVIDMEM_NODE_PTR * Node
++** Pointer to a variable that will hold the allocated memory node.
++*/
++gceSTATUS
++gckVIDMEM_AllocateLinear(
++ IN gckKERNEL Kernel,
++ IN gckVIDMEM Memory,
++ IN gctSIZE_T Bytes,
++ IN gctUINT32 Alignment,
++ IN gceSURF_TYPE Type,
++ OUT gcuVIDMEM_NODE_PTR * Node
++ )
++{
++ gceSTATUS status;
++ gcuVIDMEM_NODE_PTR node;
++ gctUINT32 alignment;
++ gctINT bank, i;
++ gctBOOL acquired = gcvFALSE;
++#if gcdSMALL_BLOCK_SIZE
++ gctBOOL force_allocate = (Type == gcvSURF_TILE_STATUS) || (Type & gcvSURF_VG);
++#endif
++
++ gcmkHEADER_ARG("Memory=0x%x Bytes=%lu Alignment=%u Type=%d",
++ Memory, Bytes, Alignment, Type);
++
++ Type &= ~gcvSURF_VG;
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Memory, gcvOBJ_VIDMEM);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++ gcmkVERIFY_ARGUMENT(Node != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Type < gcvSURF_NUM_TYPES);
++
++ /* Acquire the mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(Memory->os, Kernel->vidmemMutex, gcvINFINITE));
++
++ acquired = gcvTRUE;
++#if !gcdUSE_VIDMEM_PER_PID
++
++ if (Bytes > Memory->freeBytes)
++ {
++ /* Not enough memory. */
++ status = gcvSTATUS_OUT_OF_MEMORY;
++ goto OnError;
++ }
++#endif
++
++#if gcdSMALL_BLOCK_SIZE
++ if ((!force_allocate) && (Memory->freeBytes < (Memory->bytes/gcdRATIO_FOR_SMALL_MEMORY))
++ && (Bytes >= gcdSMALL_BLOCK_SIZE)
++ )
++ {
++ /* The left memory is for small memory.*/
++ status = gcvSTATUS_OUT_OF_MEMORY;
++ goto OnError;
++ }
++#endif
++
++ /* Find the default bank for this surface type. */
++ gcmkASSERT((gctINT) Type < gcmCOUNTOF(Memory->mapping));
++ bank = Memory->mapping[Type];
++ alignment = Alignment;
++
++#if gcdUSE_VIDMEM_PER_PID
++ if (Bytes <= Memory->freeBytes)
++ {
++#endif
++ /* Find a free node in the default bank. */
++ node = _FindNode(Memory, bank, Bytes, Type, &alignment);
++
++ /* Out of memory? */
++ if (node == gcvNULL)
++ {
++ /* Walk all lower banks. */
++ for (i = bank - 1; i >= 0; --i)
++ {
++ /* Find a free node inside the current bank. */
++ node = _FindNode(Memory, i, Bytes, Type, &alignment);
++ if (node != gcvNULL)
++ {
++ break;
++ }
++ }
++ }
++
++ if (node == gcvNULL)
++ {
++ /* Walk all upper banks. */
++ for (i = bank + 1; i < gcmCOUNTOF(Memory->sentinel); ++i)
++ {
++ if (Memory->sentinel[i].VidMem.nextFree == gcvNULL)
++ {
++ /* Abort when we reach unused banks. */
++ break;
++ }
++
++ /* Find a free node inside the current bank. */
++ node = _FindNode(Memory, i, Bytes, Type, &alignment);
++ if (node != gcvNULL)
++ {
++ break;
++ }
++ }
++ }
++#if gcdUSE_VIDMEM_PER_PID
++ }
++#endif
++
++ if (node == gcvNULL)
++ {
++ /* Out of memory. */
++#if gcdUSE_VIDMEM_PER_PID
++ /* Allocate more memory from shared pool. */
++ gctSIZE_T bytes;
++ gctPHYS_ADDR physical_temp;
++ gctUINT32 physical;
++ gctPOINTER logical;
++
++ bytes = gcmALIGN(Bytes, gcdUSE_VIDMEM_PER_PID_SIZE);
++
++ gcmkONERROR(gckOS_AllocateContiguous(Memory->os,
++ gcvTRUE,
++ &bytes,
++ &physical_temp,
++ &logical));
++
++ /* physical address is returned as 0 for user space. workaround. */
++ if (physical_temp == gcvNULL)
++ {
++ gcmkONERROR(gckOS_GetPhysicalAddress(Memory->os, logical, &physical));
++ }
++
++ /* Allocate one gcuVIDMEM_NODE union. */
++ gcmkONERROR(
++ gckOS_Allocate(Memory->os,
++ gcmSIZEOF(gcuVIDMEM_NODE),
++ (gctPOINTER *) &node));
++
++ /* Initialize gcuVIDMEM_NODE union. */
++ node->VidMem.memory = Memory;
++
++ node->VidMem.offset = 0;
++ node->VidMem.bytes = bytes;
++ node->VidMem.alignment = 0;
++ node->VidMem.physical = physical;
++ node->VidMem.pool = gcvPOOL_UNKNOWN;
++
++ node->VidMem.locked = 0;
++
++#ifdef __QNXNTO__
++ gcmkONERROR(gckOS_GetProcessID(&node->VidMem.processID));
++ node->VidMem.logical = logical;
++ gcmkASSERT(logical != gcvNULL);
++#endif
++
++ /* Insert node behind sentinel node. */
++ node->VidMem.next = Memory->sentinel[bank].VidMem.next;
++ node->VidMem.prev = &Memory->sentinel[bank];
++ Memory->sentinel[bank].VidMem.next = node->VidMem.next->VidMem.prev = node;
++
++ /* Insert free node behind sentinel node. */
++ node->VidMem.nextFree = Memory->sentinel[bank].VidMem.nextFree;
++ node->VidMem.prevFree = &Memory->sentinel[bank];
++ Memory->sentinel[bank].VidMem.nextFree = node->VidMem.nextFree->VidMem.prevFree = node;
++
++ Memory->freeBytes += bytes;
++#else
++ status = gcvSTATUS_OUT_OF_MEMORY;
++ goto OnError;
++#endif
++ }
++
++ /* Do we have an alignment? */
++ if (alignment > 0)
++ {
++ /* Split the node so it is aligned. */
++ if (_Split(Memory->os, node, alignment))
++ {
++ /* Successful split, move to aligned node. */
++ node = node->VidMem.next;
++
++ /* Remove alignment. */
++ alignment = 0;
++ }
++ }
++
++ /* Do we have enough memory after the allocation to split it? */
++ if (node->VidMem.bytes - Bytes > Memory->threshold)
++ {
++ /* Adjust the node size. */
++ _Split(Memory->os, node, Bytes);
++ }
++
++ /* Remove the node from the free list. */
++ node->VidMem.prevFree->VidMem.nextFree = node->VidMem.nextFree;
++ node->VidMem.nextFree->VidMem.prevFree = node->VidMem.prevFree;
++ node->VidMem.nextFree =
++ node->VidMem.prevFree = gcvNULL;
++
++ /* Fill in the information. */
++ node->VidMem.alignment = alignment;
++ node->VidMem.memory = Memory;
++#ifdef __QNXNTO__
++#if !gcdUSE_VIDMEM_PER_PID
++ node->VidMem.logical = gcvNULL;
++ gcmkONERROR(gckOS_GetProcessID(&node->VidMem.processID));
++#else
++ gcmkASSERT(node->VidMem.logical != gcvNULL);
++#endif
++#endif
++
++ /* Adjust the number of free bytes. */
++ Memory->freeBytes -= node->VidMem.bytes;
++
++ node->VidMem.freePending = gcvFALSE;
++
++#if gcdDYNAMIC_MAP_RESERVED_MEMORY && gcdENABLE_VG
++ node->VidMem.kernelVirtual = gcvNULL;
++#endif
++
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Memory->os, Kernel->vidmemMutex));
++
++ /* Return the pointer to the node. */
++ *Node = node;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM,
++ "Allocated %u bytes @ 0x%x [0x%08X]",
++ node->VidMem.bytes, node, node->VidMem.offset);
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Node=0x%x", *Node);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Memory->os, Kernel->vidmemMutex));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckVIDMEM_Free
++**
++** Free an allocated video memory node.
++**
++** INPUT:
++**
++** gcuVIDMEM_NODE_PTR Node
++** Pointer to a gcuVIDMEM_NODE object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckVIDMEM_Free(
++ IN gckKERNEL Kernel,
++ IN gcuVIDMEM_NODE_PTR Node
++ )
++{
++ gceSTATUS status;
++ gckKERNEL kernel = gcvNULL;
++ gckVIDMEM memory = gcvNULL;
++ gcuVIDMEM_NODE_PTR node;
++ gckOS os = gcvNULL;
++ gctBOOL acquired = gcvFALSE;
++ gctINT32 i, totalLocked;
++
++ gcmkHEADER_ARG("Node=0x%x", Node);
++
++ /* Acquire the mutex. */
++ gcmkONERROR(
++ gckOS_AcquireMutex(Kernel->os, Kernel->vidmemMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Verify the arguments. */
++ if ((Node == gcvNULL)
++ || (Node->VidMem.memory == gcvNULL)
++ )
++ {
++ /* Invalid object. */
++ gcmkONERROR(gcvSTATUS_INVALID_OBJECT);
++ }
++
++ /**************************** Video Memory ********************************/
++
++ if (Node->VidMem.memory->object.type == gcvOBJ_VIDMEM)
++ {
++ if (Node->VidMem.locked > 0)
++ {
++ /* Client still has a lock, defer free op 'till when lock reaches 0. */
++ Node->VidMem.freePending = gcvTRUE;
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, Kernel->vidmemMutex));
++ acquired = gcvFALSE;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM,
++ "Node 0x%x is locked (%d)... deferring free.",
++ Node, Node->VidMem.locked);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++
++ /* Extract pointer to gckVIDMEM object owning the node. */
++ memory = Node->VidMem.memory;
++
++#ifdef __QNXNTO__
++#if !gcdUSE_VIDMEM_PER_PID
++ /* Reset. */
++ Node->VidMem.processID = 0;
++ Node->VidMem.logical = gcvNULL;
++#endif
++
++ /* Don't try to re-free an already freed node. */
++ if ((Node->VidMem.nextFree == gcvNULL)
++ && (Node->VidMem.prevFree == gcvNULL)
++ )
++#endif
++ {
++#if gcdDYNAMIC_MAP_RESERVED_MEMORY && gcdENABLE_VG
++ if (Node->VidMem.kernelVirtual)
++ {
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM,
++ "%s(%d) Unmap %x from kernel space.",
++ __FUNCTION__, __LINE__,
++ Node->VidMem.kernelVirtual);
++
++ gcmkVERIFY_OK(
++ gckOS_UnmapPhysical(memory->os,
++ Node->VidMem.kernelVirtual,
++ Node->VidMem.bytes));
++
++ Node->VidMem.kernelVirtual = gcvNULL;
++ }
++#endif
++
++ /* Check if Node is already freed. */
++ if (Node->VidMem.nextFree)
++ {
++ /* Node is alread freed. */
++ gcmkONERROR(gcvSTATUS_INVALID_DATA);
++ }
++
++ /* Update the number of free bytes. */
++ memory->freeBytes += Node->VidMem.bytes;
++
++ /* Find the next free node. */
++ for (node = Node->VidMem.next;
++ node != gcvNULL && node->VidMem.nextFree == gcvNULL;
++ node = node->VidMem.next) ;
++
++ /* Insert this node in the free list. */
++ Node->VidMem.nextFree = node;
++ Node->VidMem.prevFree = node->VidMem.prevFree;
++
++ Node->VidMem.prevFree->VidMem.nextFree =
++ node->VidMem.prevFree = Node;
++
++ /* Is the next node a free node and not the sentinel? */
++ if ((Node->VidMem.next == Node->VidMem.nextFree)
++ && (Node->VidMem.next->VidMem.bytes != 0)
++ )
++ {
++ /* Merge this node with the next node. */
++ gcmkONERROR(_Merge(memory->os, node = Node));
++ gcmkASSERT(node->VidMem.nextFree != node);
++ gcmkASSERT(node->VidMem.prevFree != node);
++ }
++
++ /* Is the previous node a free node and not the sentinel? */
++ if ((Node->VidMem.prev == Node->VidMem.prevFree)
++ && (Node->VidMem.prev->VidMem.bytes != 0)
++ )
++ {
++ /* Merge this node with the previous node. */
++ gcmkONERROR(_Merge(memory->os, node = Node->VidMem.prev));
++ gcmkASSERT(node->VidMem.nextFree != node);
++ gcmkASSERT(node->VidMem.prevFree != node);
++ }
++ }
++
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, Kernel->vidmemMutex));
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM,
++ "Node 0x%x is freed.",
++ Node);
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++
++ /*************************** Virtual Memory *******************************/
++
++ /* Get gckKERNEL object. */
++ kernel = Node->Virtual.kernel;
++
++ /* Verify the gckKERNEL object pointer. */
++ gcmkVERIFY_OBJECT(kernel, gcvOBJ_KERNEL);
++
++ /* Get the gckOS object pointer. */
++ os = kernel->os;
++ gcmkVERIFY_OBJECT(os, gcvOBJ_OS);
++
++ for (i = 0, totalLocked = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ totalLocked += Node->Virtual.lockeds[i];
++ }
++
++ if (totalLocked > 0)
++ {
++ gcmkTRACE_ZONE(gcvLEVEL_ERROR, gcvZONE_VIDMEM,
++ "gckVIDMEM_Free: Virtual node 0x%x is locked (%d)",
++ Node, totalLocked);
++
++ /* Set Flag */
++ Node->Virtual.freed = gcvTRUE;
++ }
++ else
++ {
++ /* Free the virtual memory. */
++ gcmkVERIFY_OK(gckOS_FreePagedMemory(kernel->os,
++ Node->Virtual.physical,
++ Node->Virtual.bytes));
++
++ /* Destroy the gcuVIDMEM_NODE union. */
++ gcmkVERIFY_OK(gckVIDMEM_DestroyVirtual(Node));
++ }
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, Kernel->vidmemMutex));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, Kernel->vidmemMutex));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++
++#ifdef __QNXNTO__
++/*******************************************************************************
++**
++** gcoVIDMEM_FreeHandleMemory
++**
++** Free all allocated video memory nodes for a handle.
++**
++** INPUT:
++**
++** gcoVIDMEM Memory
++** Pointer to an gcoVIDMEM object..
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckVIDMEM_FreeHandleMemory(
++ IN gckKERNEL Kernel,
++ IN gckVIDMEM Memory,
++ IN gctUINT32 Pid
++ )
++{
++ gceSTATUS status;
++ gctBOOL mutex = gcvFALSE;
++ gcuVIDMEM_NODE_PTR node;
++ gctINT i;
++ gctUINT32 nodeCount = 0, byteCount = 0;
++ gctBOOL again;
++
++ gcmkHEADER_ARG("Kernel=0x%x, Memory=0x%x Pid=0x%u", Kernel, Memory, Pid);
++
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_OBJECT(Memory, gcvOBJ_VIDMEM);
++
++ gcmkONERROR(gckOS_AcquireMutex(Memory->os, Memory->mutex, gcvINFINITE));
++ mutex = gcvTRUE;
++
++ /* Walk all sentinels. */
++ for (i = 0; i < gcmCOUNTOF(Memory->sentinel); ++i)
++ {
++ /* Bail out of the heap if it is not used. */
++ if (Memory->sentinel[i].VidMem.next == gcvNULL)
++ {
++ break;
++ }
++
++ do
++ {
++ again = gcvFALSE;
++
++ /* Walk all the nodes until we reach the sentinel. */
++ for (node = Memory->sentinel[i].VidMem.next;
++ node->VidMem.bytes != 0;
++ node = node->VidMem.next)
++ {
++ /* Free the node if it was allocated by Handle. */
++ if (node->VidMem.processID == Pid)
++ {
++ /* Unlock video memory. */
++ while (node->VidMem.locked > 0)
++ {
++ gckVIDMEM_Unlock(Kernel, node, gcvSURF_TYPE_UNKNOWN, gcvNULL);
++ }
++
++ nodeCount++;
++ byteCount += node->VidMem.bytes;
++
++ /* Free video memory. */
++ gcmkVERIFY_OK(gckVIDMEM_Free(node));
++
++ /*
++ * Freeing may cause a merge which will invalidate our iteration.
++ * Don't be clever, just restart.
++ */
++ again = gcvTRUE;
++
++ break;
++ }
++#if gcdUSE_VIDMEM_PER_PID
++ else
++ {
++ gcmkASSERT(node->VidMem.processID == Pid);
++ }
++#endif
++ }
++ }
++ while (again);
++ }
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Memory->os, Memory->mutex));
++ gcmkFOOTER();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (mutex)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Memory->os, Memory->mutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++#endif
++
++/*******************************************************************************
++**
++** _NeedVirtualMapping
++**
++** Whether setup GPU page table for video node.
++**
++** INPUT:
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gcuVIDMEM_NODE_PTR Node
++** Pointer to a gcuVIDMEM_NODE union.
++**
++** gceCORE Core
++** Id of current GPU.
++**
++** OUTPUT:
++** gctBOOL * NeedMapping
++** A pointer hold the result whether Node should be mapping.
++*/
++static gceSTATUS
++_NeedVirtualMapping(
++ IN gckKERNEL Kernel,
++ IN gceCORE Core,
++ IN gcuVIDMEM_NODE_PTR Node,
++ OUT gctBOOL * NeedMapping
++)
++{
++ gceSTATUS status;
++ gctUINT32 phys;
++ gctUINT32 end;
++ gcePOOL pool;
++ gctUINT32 offset;
++ gctUINT32 baseAddress;
++
++ gcmkHEADER_ARG("Node=0x%X", Node);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_ARGUMENT(Kernel != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Node != gcvNULL);
++ gcmkVERIFY_ARGUMENT(NeedMapping != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Core < gcdMAX_GPU_COUNT);
++
++ if (Node->Virtual.contiguous)
++ {
++#if gcdENABLE_VG
++ if (Core == gcvCORE_VG)
++ {
++ *NeedMapping = gcvFALSE;
++ }
++ else
++#endif
++ {
++ /* Convert logical address into a physical address. */
++ gcmkONERROR(
++ gckOS_GetPhysicalAddress(Kernel->os, Node->Virtual.logical, &phys));
++
++ gcmkONERROR(gckOS_GetBaseAddress(Kernel->os, &baseAddress));
++
++ gcmkASSERT(phys >= baseAddress);
++
++ /* Subtract baseAddress to get a GPU address used for programming. */
++ phys -= baseAddress;
++
++ /* If part of region is belong to gcvPOOL_VIRTUAL,
++ ** whole region has to be mapped. */
++ end = phys + Node->Virtual.bytes - 1;
++
++ gcmkONERROR(gckHARDWARE_SplitMemory(
++ Kernel->hardware, end, &pool, &offset
++ ));
++
++ *NeedMapping = (pool == gcvPOOL_VIRTUAL);
++ }
++ }
++ else
++ {
++ *NeedMapping = gcvTRUE;
++ }
++
++ gcmkFOOTER_ARG("*NeedMapping=%d", *NeedMapping);
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckVIDMEM_Lock
++**
++** Lock a video memory node and return its hardware specific address.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gcuVIDMEM_NODE_PTR Node
++** Pointer to a gcuVIDMEM_NODE union.
++**
++** OUTPUT:
++**
++** gctUINT32 * Address
++** Pointer to a variable that will hold the hardware specific address.
++*/
++gceSTATUS
++gckVIDMEM_Lock(
++ IN gckKERNEL Kernel,
++ IN gcuVIDMEM_NODE_PTR Node,
++ IN gctBOOL Cacheable,
++ OUT gctUINT32 * Address
++ )
++{
++ gceSTATUS status;
++ gctBOOL acquired = gcvFALSE;
++ gctBOOL locked = gcvFALSE;
++ gckOS os = gcvNULL;
++ gctBOOL needMapping;
++ gctUINT32 baseAddress;
++
++ gcmkHEADER_ARG("Node=0x%x", Node);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_ARGUMENT(Address != gcvNULL);
++
++ /* Grab the mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(Kernel->os, Kernel->vidmemMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ if ((Node == gcvNULL)
++ || (Node->VidMem.memory == gcvNULL)
++ )
++ {
++ /* Invalid object. */
++ gcmkONERROR(gcvSTATUS_INVALID_OBJECT);
++ }
++
++ /**************************** Video Memory ********************************/
++
++ if (Node->VidMem.memory->object.type == gcvOBJ_VIDMEM)
++ {
++ if (Cacheable == gcvTRUE)
++ {
++ gcmkONERROR(gcvSTATUS_INVALID_REQUEST);
++ }
++
++ /* Increment the lock count. */
++ Node->VidMem.locked ++;
++
++ /* Return the physical address of the node. */
++#if !gcdUSE_VIDMEM_PER_PID
++ *Address = Node->VidMem.memory->baseAddress
++ + Node->VidMem.offset
++ + Node->VidMem.alignment;
++#else
++ *Address = Node->VidMem.physical;
++#endif
++
++ /* Get hardware specific address. */
++#if gcdENABLE_VG
++ if (Kernel->vg == gcvNULL)
++#endif
++ {
++ if (Kernel->hardware->mmuVersion == 0)
++ {
++ /* Convert physical to GPU address for old mmu. */
++ gcmkONERROR(gckOS_GetBaseAddress(Kernel->os, &baseAddress));
++ gcmkASSERT(*Address > baseAddress);
++ *Address -= baseAddress;
++ }
++ }
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM,
++ "Locked node 0x%x (%d) @ 0x%08X",
++ Node,
++ Node->VidMem.locked,
++ *Address);
++ }
++
++ /*************************** Virtual Memory *******************************/
++
++ else
++ {
++ /* Verify the gckKERNEL object pointer. */
++ gcmkVERIFY_OBJECT(Node->Virtual.kernel, gcvOBJ_KERNEL);
++
++ /* Extract the gckOS object pointer. */
++ os = Node->Virtual.kernel->os;
++ gcmkVERIFY_OBJECT(os, gcvOBJ_OS);
++
++#if gcdPAGED_MEMORY_CACHEABLE
++ /* Force video memory cacheable. */
++ Cacheable = gcvTRUE;
++#endif
++
++ gcmkONERROR(
++ gckOS_LockPages(os,
++ Node->Virtual.physical,
++ Node->Virtual.bytes,
++ Cacheable,
++ &Node->Virtual.logical,
++ &Node->Virtual.pageCount));
++
++ /* Increment the lock count. */
++ if (Node->Virtual.lockeds[Kernel->core] ++ == 0)
++ {
++ /* Is this node pending for a final unlock? */
++#ifdef __QNXNTO__
++ if (!Node->Virtual.contiguous && Node->Virtual.unlockPendings[Kernel->core])
++ {
++ /* Make sure we have a page table. */
++ gcmkASSERT(Node->Virtual.pageTables[Kernel->core] != gcvNULL);
++
++ /* Remove pending unlock. */
++ Node->Virtual.unlockPendings[Kernel->core] = gcvFALSE;
++ }
++
++ /* First lock - create a page table. */
++ gcmkASSERT(Node->Virtual.pageTables[Kernel->core] == gcvNULL);
++
++ /* Make sure we mark our node as not flushed. */
++ Node->Virtual.unlockPendings[Kernel->core] = gcvFALSE;
++#endif
++
++ locked = gcvTRUE;
++
++ gcmkONERROR(_NeedVirtualMapping(Kernel, Kernel->core, Node, &needMapping));
++
++ if (needMapping == gcvFALSE)
++ {
++ /* Get hardware specific address. */
++#if gcdENABLE_VG
++ if (Kernel->vg != gcvNULL)
++ {
++ gcmkONERROR(gckVGHARDWARE_ConvertLogical(Kernel->vg->hardware,
++ Node->Virtual.logical,
++ &Node->Virtual.addresses[Kernel->core]));
++ }
++ else
++#endif
++ {
++ gcmkONERROR(gckHARDWARE_ConvertLogical(Kernel->hardware,
++ Node->Virtual.logical,
++ &Node->Virtual.addresses[Kernel->core]));
++ }
++ }
++ else
++ {
++#if gcdENABLE_VG
++ if (Kernel->vg != gcvNULL)
++ {
++ /* Allocate pages inside the MMU. */
++ gcmkONERROR(
++ gckVGMMU_AllocatePages(Kernel->vg->mmu,
++ Node->Virtual.pageCount,
++ &Node->Virtual.pageTables[Kernel->core],
++ &Node->Virtual.addresses[Kernel->core]));
++ }
++ else
++#endif
++ {
++ /* Allocate pages inside the MMU. */
++ gcmkONERROR(
++ gckMMU_AllocatePagesEx(Kernel->mmu,
++ Node->Virtual.pageCount,
++ Node->Virtual.type,
++ &Node->Virtual.pageTables[Kernel->core],
++ &Node->Virtual.addresses[Kernel->core]));
++ }
++
++ Node->Virtual.lockKernels[Kernel->core] = Kernel;
++
++ /* Map the pages. */
++#ifdef __QNXNTO__
++ gcmkONERROR(
++ gckOS_MapPagesEx(os,
++ Kernel->core,
++ Node->Virtual.physical,
++ Node->Virtual.logical,
++ Node->Virtual.pageCount,
++ Node->Virtual.pageTables[Kernel->core]));
++#else
++ gcmkONERROR(
++ gckOS_MapPagesEx(os,
++ Kernel->core,
++ Node->Virtual.physical,
++ Node->Virtual.pageCount,
++ Node->Virtual.pageTables[Kernel->core]));
++#endif
++
++#if gcdENABLE_VG
++ if (Kernel->core == gcvCORE_VG)
++ {
++ gcmkONERROR(gckVGMMU_Flush(Kernel->vg->mmu));
++ }
++ else
++#endif
++ {
++ gcmkONERROR(gckMMU_Flush(Kernel->mmu));
++ }
++ }
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM,
++ "Mapped virtual node 0x%x to 0x%08X",
++ Node,
++ Node->Virtual.addresses[Kernel->core]);
++ }
++
++ /* Return hardware address. */
++ *Address = Node->Virtual.addresses[Kernel->core];
++ }
++
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, Kernel->vidmemMutex));
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Address=%08x", *Address);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (locked)
++ {
++ if (Node->Virtual.pageTables[Kernel->core] != gcvNULL)
++ {
++#if gcdENABLE_VG
++ if (Kernel->vg != gcvNULL)
++ {
++ /* Free the pages from the MMU. */
++ gcmkVERIFY_OK(
++ gckVGMMU_FreePages(Kernel->vg->mmu,
++ Node->Virtual.pageTables[Kernel->core],
++ Node->Virtual.pageCount));
++ }
++ else
++#endif
++ {
++ /* Free the pages from the MMU. */
++ gcmkVERIFY_OK(
++ gckMMU_FreePages(Kernel->mmu,
++ Node->Virtual.pageTables[Kernel->core],
++ Node->Virtual.pageCount));
++ }
++ Node->Virtual.pageTables[Kernel->core] = gcvNULL;
++ Node->Virtual.lockKernels[Kernel->core] = gcvNULL;
++ }
++
++ /* Unlock the pages. */
++ gcmkVERIFY_OK(
++ gckOS_UnlockPages(os,
++ Node->Virtual.physical,
++ Node->Virtual.bytes,
++ Node->Virtual.logical
++ ));
++
++ Node->Virtual.lockeds[Kernel->core]--;
++ }
++
++ if (acquired)
++ {
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, Kernel->vidmemMutex));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckVIDMEM_Unlock
++**
++** Unlock a video memory node.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gcuVIDMEM_NODE_PTR Node
++** Pointer to a locked gcuVIDMEM_NODE union.
++**
++** gceSURF_TYPE Type
++** Type of surface to unlock.
++**
++** gctBOOL * Asynchroneous
++** Pointer to a variable specifying whether the surface should be
++** unlocked asynchroneously or not.
++**
++** OUTPUT:
++**
++** gctBOOL * Asynchroneous
++** Pointer to a variable receiving the number of bytes used in the
++** command buffer specified by 'Commands'. If gcvNULL, there is no
++** command buffer.
++*/
++gceSTATUS
++gckVIDMEM_Unlock(
++ IN gckKERNEL Kernel,
++ IN gcuVIDMEM_NODE_PTR Node,
++ IN gceSURF_TYPE Type,
++ IN OUT gctBOOL * Asynchroneous
++ )
++{
++ gceSTATUS status;
++ gckHARDWARE hardware;
++ gctPOINTER buffer;
++ gctSIZE_T requested, bufferSize;
++ gckCOMMAND command = gcvNULL;
++ gceKERNEL_FLUSH flush;
++ gckOS os = gcvNULL;
++ gctBOOL acquired = gcvFALSE;
++ gctBOOL commitEntered = gcvFALSE;
++ gctINT32 i, totalLocked;
++
++ gcmkHEADER_ARG("Node=0x%x Type=%d *Asynchroneous=%d",
++ Node, Type, gcmOPT_VALUE(Asynchroneous));
++
++ /* Grab the mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(Kernel->os, Kernel->vidmemMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++
++ /* Verify the arguments. */
++ if ((Node == gcvNULL)
++ || (Node->VidMem.memory == gcvNULL)
++ )
++ {
++ /* Invalid object. */
++ gcmkONERROR(gcvSTATUS_INVALID_OBJECT);
++ }
++
++ /**************************** Video Memory ********************************/
++
++ if (Node->VidMem.memory->object.type == gcvOBJ_VIDMEM)
++ {
++ if (Node->VidMem.locked <= 0)
++ {
++ /* The surface was not locked. */
++ status = gcvSTATUS_MEMORY_UNLOCKED;
++ goto OnError;
++ }
++
++ /* Decrement the lock count. */
++ Node->VidMem.locked --;
++
++ if (Asynchroneous != gcvNULL)
++ {
++ /* No need for any events. */
++ *Asynchroneous = gcvFALSE;
++ }
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM,
++ "Unlocked node 0x%x (%d)",
++ Node,
++ Node->VidMem.locked);
++
++#ifdef __QNXNTO__
++ /* Unmap the video memory */
++ if ((Node->VidMem.locked == 0) && (Node->VidMem.logical != gcvNULL))
++ {
++ if (Kernel->core == gcvCORE_VG)
++ {
++ gckKERNEL_UnmapVideoMemory(Kernel,
++ Node->VidMem.logical,
++ Node->VidMem.processID,
++ Node->VidMem.bytes);
++ Node->VidMem.logical = gcvNULL;
++ }
++ }
++#endif /* __QNXNTO__ */
++
++ if (Node->VidMem.freePending && (Node->VidMem.locked == 0))
++ {
++ /* Client has unlocked node previously attempted to be freed by compositor. Free now. */
++ Node->VidMem.freePending = gcvFALSE;
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM,
++ "Deferred-freeing Node 0x%x.",
++ Node);
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, Kernel->vidmemMutex));
++ acquired = gcvFALSE;
++
++ gcmkONERROR(gckVIDMEM_Free(Kernel, Node));
++ }
++ }
++
++ /*************************** Virtual Memory *******************************/
++
++ else
++ {
++ /* Verify the gckHARDWARE object pointer. */
++ hardware = Kernel->hardware;
++ gcmkVERIFY_OBJECT(hardware, gcvOBJ_HARDWARE);
++
++ /* Verify the gckCOMMAND object pointer. */
++ command = Kernel->command;
++ gcmkVERIFY_OBJECT(command, gcvOBJ_COMMAND);
++
++ /* Get the gckOS object pointer. */
++ os = Kernel->os;
++ gcmkVERIFY_OBJECT(os, gcvOBJ_OS);
++
++ if (Asynchroneous == gcvNULL)
++ {
++ if (Node->Virtual.lockeds[Kernel->core] == 0)
++ {
++ status = gcvSTATUS_MEMORY_UNLOCKED;
++ goto OnError;
++ }
++
++ /* Decrement lock count. */
++ -- Node->Virtual.lockeds[Kernel->core];
++
++ /* See if we can unlock the resources. */
++ if (Node->Virtual.lockeds[Kernel->core] == 0)
++ {
++ /* Free the page table. */
++ if (Node->Virtual.pageTables[Kernel->core] != gcvNULL)
++ {
++#if gcdENABLE_VG
++ if (Kernel->vg != gcvNULL)
++ {
++ gcmkONERROR(
++ gckVGMMU_FreePages(Kernel->vg->mmu,
++ Node->Virtual.pageTables[Kernel->core],
++ Node->Virtual.pageCount));
++ }
++ else
++#endif
++ {
++ gcmkONERROR(
++ gckMMU_FreePages(Kernel->mmu,
++ Node->Virtual.pageTables[Kernel->core],
++ Node->Virtual.pageCount));
++ }
++ /* Mark page table as freed. */
++ Node->Virtual.pageTables[Kernel->core] = gcvNULL;
++ Node->Virtual.lockKernels[Kernel->core] = gcvNULL;
++ }
++
++#ifdef __QNXNTO__
++ /* Mark node as unlocked. */
++ Node->Virtual.unlockPendings[Kernel->core] = gcvFALSE;
++#endif
++ }
++
++ for (i = 0, totalLocked = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ totalLocked += Node->Virtual.lockeds[i];
++ }
++
++ if (totalLocked == 0)
++ {
++ /* Owner have already freed this node
++ ** and we are the last one to unlock, do
++ ** real free */
++ if (Node->Virtual.freed)
++ {
++ /* Free the virtual memory. */
++ gcmkVERIFY_OK(gckOS_FreePagedMemory(Kernel->os,
++ Node->Virtual.physical,
++ Node->Virtual.bytes));
++
++ /* Destroy the gcuVIDMEM_NODE union. */
++ gcmkVERIFY_OK(gckVIDMEM_DestroyVirtual(Node));
++
++ /* Release mutex before node is destroyed */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, Kernel->vidmemMutex));
++
++ acquired = gcvFALSE;
++
++ /* Node has been destroyed, so we should not touch it any more */
++ gcmkFOOTER();
++ return gcvSTATUS_OK;
++ }
++ }
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM,
++ "Unmapped virtual node 0x%x from 0x%08X",
++ Node, Node->Virtual.addresses[Kernel->core]);
++
++ }
++
++ else
++ {
++ /* If we need to unlock a node from virtual memory we have to be
++ ** very carefull. If the node is still inside the caches we
++ ** might get a bus error later if the cache line needs to be
++ ** replaced. So - we have to flush the caches before we do
++ ** anything. */
++
++ /* gckCommand_EnterCommit() can't be called in interrupt handler because
++ ** of a dead lock situation:
++ ** process call Command_Commit(), and acquire Command->mutexQueue in
++ ** gckCOMMAND_EnterCommit(). Then it will wait for a signal which depends
++ ** on interrupt handler to generate, if interrupt handler enter
++ ** gckCommand_EnterCommit(), process will never get the signal. */
++
++ /* So, flush cache when we still in process context, and then ask caller to
++ ** schedule a event. */
++
++ gcmkONERROR(
++ gckOS_UnlockPages(os,
++ Node->Virtual.physical,
++ Node->Virtual.bytes,
++ Node->Virtual.logical));
++
++ if (!Node->Virtual.contiguous
++ && (Node->Virtual.lockeds[Kernel->core] == 1)
++#if gcdENABLE_VG
++ && (Kernel->vg == gcvNULL)
++#endif
++ )
++ {
++ if (Type == gcvSURF_BITMAP)
++ {
++ /* Flush 2D cache. */
++ flush = gcvFLUSH_2D;
++ }
++ else if (Type == gcvSURF_RENDER_TARGET)
++ {
++ /* Flush color cache. */
++ flush = gcvFLUSH_COLOR;
++ }
++ else if (Type == gcvSURF_DEPTH)
++ {
++ /* Flush depth cache. */
++ flush = gcvFLUSH_DEPTH;
++ }
++ else
++ {
++ /* No flush required. */
++ flush = (gceKERNEL_FLUSH) 0;
++ }
++ if(hardware)
++ {
++ gcmkONERROR(
++ gckHARDWARE_Flush(hardware, flush, gcvNULL, &requested));
++
++ if (requested != 0)
++ {
++ /* Acquire the command queue. */
++ gcmkONERROR(gckCOMMAND_EnterCommit(command, gcvFALSE));
++ commitEntered = gcvTRUE;
++
++ gcmkONERROR(gckCOMMAND_Reserve(
++ command, requested, &buffer, &bufferSize
++ ));
++
++ gcmkONERROR(gckHARDWARE_Flush(
++ hardware, flush, buffer, &bufferSize
++ ));
++
++ /* Mark node as pending. */
++#ifdef __QNXNTO__
++ Node->Virtual.unlockPendings[Kernel->core] = gcvTRUE;
++#endif
++
++ gcmkONERROR(gckCOMMAND_Execute(command, requested));
++
++ /* Release the command queue. */
++ gcmkONERROR(gckCOMMAND_ExitCommit(command, gcvFALSE));
++ commitEntered = gcvFALSE;
++ }
++ }
++ else
++ {
++ gckOS_Print("Hardware already is freed.\n");
++ }
++ }
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM,
++ "Scheduled unlock for virtual node 0x%x",
++ Node);
++
++ /* Schedule the surface to be unlocked. */
++ *Asynchroneous = gcvTRUE;
++ }
++ }
++
++ if (acquired)
++ {
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, Kernel->vidmemMutex));
++ acquired = gcvFALSE;
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Asynchroneous=%d", gcmOPT_VALUE(Asynchroneous));
++ return gcvSTATUS_OK;
++
++OnError:
++ if (commitEntered)
++ {
++ /* Release the command queue mutex. */
++ gcmkVERIFY_OK(gckCOMMAND_ExitCommit(command, gcvFALSE));
++ }
++
++ if (acquired)
++ {
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, Kernel->vidmemMutex));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_base.h linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_base.h
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_base.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_base.h 2015-07-27 23:13:06.210822785 +0200
+@@ -0,0 +1,3896 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_base_h_
++#define __gc_hal_base_h_
++
++#include "gc_hal_enum.h"
++#include "gc_hal_types.h"
++
++#include "gc_hal_dump.h"
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/******************************************************************************\
++****************************** Object Declarations *****************************
++\******************************************************************************/
++
++typedef struct _gckOS * gckOS;
++typedef struct _gcoHAL * gcoHAL;
++typedef struct _gcoOS * gcoOS;
++typedef struct _gco2D * gco2D;
++
++#ifndef VIVANTE_NO_3D
++typedef struct _gco3D * gco3D;
++#endif
++
++typedef struct _gcoSURF * gcoSURF;
++typedef struct _gcsSURF_INFO * gcsSURF_INFO_PTR;
++typedef struct _gcsSURF_NODE * gcsSURF_NODE_PTR;
++typedef struct _gcsSURF_FORMAT_INFO * gcsSURF_FORMAT_INFO_PTR;
++typedef struct _gcsPOINT * gcsPOINT_PTR;
++typedef struct _gcsSIZE * gcsSIZE_PTR;
++typedef struct _gcsRECT * gcsRECT_PTR;
++typedef struct _gcsBOUNDARY * gcsBOUNDARY_PTR;
++typedef struct _gcoDUMP * gcoDUMP;
++typedef struct _gcoHARDWARE * gcoHARDWARE;
++typedef union _gcuVIDMEM_NODE * gcuVIDMEM_NODE_PTR;
++
++typedef struct gcsATOM * gcsATOM_PTR;
++
++#if gcdENABLE_VG
++typedef struct _gcoVG * gcoVG;
++typedef struct _gcsCOMPLETION_SIGNAL * gcsCOMPLETION_SIGNAL_PTR;
++typedef struct _gcsCONTEXT_MAP * gcsCONTEXT_MAP_PTR;
++#else
++typedef void * gcoVG;
++#endif
++
++#if gcdSYNC
++typedef struct _gcoFENCE * gcoFENCE;
++typedef struct _gcsSYNC_CONTEXT * gcsSYNC_CONTEXT_PTR;
++#endif
++
++typedef struct _gcoOS_SymbolsList gcoOS_SymbolsList;
++
++/******************************************************************************\
++******************************* Process local storage *************************
++\******************************************************************************/
++typedef struct _gcsPLS * gcsPLS_PTR;
++
++typedef void (* gctPLS_DESTRUCTOR) (
++ gcsPLS_PTR
++ );
++
++typedef struct _gcsPLS
++{
++ /* Global objects. */
++ gcoOS os;
++ gcoHAL hal;
++
++ /* Internal memory pool. */
++ gctSIZE_T internalSize;
++ gctPHYS_ADDR internalPhysical;
++ gctPOINTER internalLogical;
++
++ /* External memory pool. */
++ gctSIZE_T externalSize;
++ gctPHYS_ADDR externalPhysical;
++ gctPOINTER externalLogical;
++
++ /* Contiguous memory pool. */
++ gctSIZE_T contiguousSize;
++ gctPHYS_ADDR contiguousPhysical;
++ gctPOINTER contiguousLogical;
++
++ /* EGL-specific process-wide objects. */
++ gctPOINTER eglDisplayInfo;
++ gctPOINTER eglSurfaceInfo;
++ gceSURF_FORMAT eglConfigFormat;
++
++ /* PorcessID of the constrcutor process */
++ gctUINT32 processID;
++#if gcdFORCE_GAL_LOAD_TWICE
++ /* ThreadID of the constrcutor process. */
++ gctSIZE_T threadID;
++ /* Flag for calling module destructor. */
++ gctBOOL exiting;
++#endif
++
++ /* Reference count for destructor. */
++ gcsATOM_PTR reference;
++ gctBOOL bKFS;
++#if gcdUSE_NPOT_PATCH
++ gctBOOL bNeedSupportNP2Texture;
++#endif
++
++ /* Destructor for eglDisplayInfo. */
++ gctPLS_DESTRUCTOR destructor;
++}
++gcsPLS;
++
++extern gcsPLS gcPLS;
++
++/******************************************************************************\
++******************************* Thread local storage *************************
++\******************************************************************************/
++
++typedef struct _gcsTLS * gcsTLS_PTR;
++
++typedef void (* gctTLS_DESTRUCTOR) (
++ gcsTLS_PTR
++ );
++
++typedef struct _gcsTLS
++{
++ gceHARDWARE_TYPE currentType;
++ gcoHARDWARE hardware;
++ /* Only for separated 3D and 2D */
++ gcoHARDWARE hardware2D;
++#if gcdENABLE_VG
++ gcoVGHARDWARE vg;
++ gcoVG engineVG;
++#endif /* gcdENABLE_VG */
++ gctPOINTER context;
++ gctTLS_DESTRUCTOR destructor;
++ gctBOOL ProcessExiting;
++
++#ifndef VIVANTE_NO_3D
++ gco3D engine3D;
++#endif
++#if gcdSYNC
++ gctBOOL fenceEnable;
++#endif
++ gco2D engine2D;
++ gctBOOL copied;
++
++#if gcdFORCE_GAL_LOAD_TWICE
++ /* libGAL.so handle */
++ gctHANDLE handle;
++#endif
++}
++gcsTLS;
++
++/******************************************************************************\
++********************************* Enumerations *********************************
++\******************************************************************************/
++
++typedef enum _gcePLS_VALUE
++{
++ gcePLS_VALUE_EGL_DISPLAY_INFO,
++ gcePLS_VALUE_EGL_SURFACE_INFO,
++ gcePLS_VALUE_EGL_CONFIG_FORMAT_INFO,
++ gcePLS_VALUE_EGL_DESTRUCTOR_INFO,
++}
++gcePLS_VALUE;
++
++/* Video memory pool type. */
++typedef enum _gcePOOL
++{
++ gcvPOOL_UNKNOWN = 0,
++ gcvPOOL_DEFAULT,
++ gcvPOOL_LOCAL,
++ gcvPOOL_LOCAL_INTERNAL,
++ gcvPOOL_LOCAL_EXTERNAL,
++ gcvPOOL_UNIFIED,
++ gcvPOOL_SYSTEM,
++ gcvPOOL_VIRTUAL,
++ gcvPOOL_USER,
++ gcvPOOL_CONTIGUOUS,
++ gcvPOOL_DEFAULT_FORCE_CONTIGUOUS,
++ gcvPOOL_DEFAULT_FORCE_CONTIGUOUS_CACHEABLE,
++
++ gcvPOOL_NUMBER_OF_POOLS
++}
++gcePOOL;
++
++#ifndef VIVANTE_NO_3D
++/* Blending functions. */
++typedef enum _gceBLEND_FUNCTION
++{
++ gcvBLEND_ZERO,
++ gcvBLEND_ONE,
++ gcvBLEND_SOURCE_COLOR,
++ gcvBLEND_INV_SOURCE_COLOR,
++ gcvBLEND_SOURCE_ALPHA,
++ gcvBLEND_INV_SOURCE_ALPHA,
++ gcvBLEND_TARGET_COLOR,
++ gcvBLEND_INV_TARGET_COLOR,
++ gcvBLEND_TARGET_ALPHA,
++ gcvBLEND_INV_TARGET_ALPHA,
++ gcvBLEND_SOURCE_ALPHA_SATURATE,
++ gcvBLEND_CONST_COLOR,
++ gcvBLEND_INV_CONST_COLOR,
++ gcvBLEND_CONST_ALPHA,
++ gcvBLEND_INV_CONST_ALPHA,
++}
++gceBLEND_FUNCTION;
++
++/* Blending modes. */
++typedef enum _gceBLEND_MODE
++{
++ gcvBLEND_ADD,
++ gcvBLEND_SUBTRACT,
++ gcvBLEND_REVERSE_SUBTRACT,
++ gcvBLEND_MIN,
++ gcvBLEND_MAX,
++}
++gceBLEND_MODE;
++
++/* API flags. */
++typedef enum _gceAPI
++{
++ gcvAPI_D3D = 0x1,
++ gcvAPI_OPENGL = 0x2,
++ gcvAPI_OPENVG = 0x3,
++ gcvAPI_OPENCL = 0x4,
++}
++gceAPI;
++
++/* Depth modes. */
++typedef enum _gceDEPTH_MODE
++{
++ gcvDEPTH_NONE,
++ gcvDEPTH_Z,
++ gcvDEPTH_W,
++}
++gceDEPTH_MODE;
++#endif /* VIVANTE_NO_3D */
++
++typedef enum _gceWHERE
++{
++ gcvWHERE_COMMAND,
++ gcvWHERE_RASTER,
++ gcvWHERE_PIXEL,
++}
++gceWHERE;
++
++typedef enum _gceHOW
++{
++ gcvHOW_SEMAPHORE = 0x1,
++ gcvHOW_STALL = 0x2,
++ gcvHOW_SEMAPHORE_STALL = 0x3,
++}
++gceHOW;
++
++typedef enum _gceSignalHandlerType
++{
++ gcvHANDLE_SIGFPE_WHEN_SIGNAL_CODE_IS_0 = 0x1,
++}
++gceSignalHandlerType;
++
++
++#if gcdENABLE_VG
++/* gcsHAL_Limits*/
++typedef struct _gcsHAL_LIMITS
++{
++ /* chip info */
++ gceCHIPMODEL chipModel;
++ gctUINT32 chipRevision;
++ gctUINT32 featureCount;
++ gctUINT32 *chipFeatures;
++
++ /* target caps */
++ gctUINT32 maxWidth;
++ gctUINT32 maxHeight;
++ gctUINT32 multiTargetCount;
++ gctUINT32 maxSamples;
++
++}gcsHAL_LIMITS;
++#endif
++
++/******************************************************************************\
++*********** Generic Memory Allocation Optimization Using Containers ************
++\******************************************************************************/
++
++/* Generic container definition. */
++typedef struct _gcsCONTAINER_LINK * gcsCONTAINER_LINK_PTR;
++typedef struct _gcsCONTAINER_LINK
++{
++ /* Points to the next container. */
++ gcsCONTAINER_LINK_PTR next;
++}
++gcsCONTAINER_LINK;
++
++typedef struct _gcsCONTAINER_RECORD * gcsCONTAINER_RECORD_PTR;
++typedef struct _gcsCONTAINER_RECORD
++{
++ gcsCONTAINER_RECORD_PTR prev;
++ gcsCONTAINER_RECORD_PTR next;
++}
++gcsCONTAINER_RECORD;
++
++typedef struct _gcsCONTAINER * gcsCONTAINER_PTR;
++typedef struct _gcsCONTAINER
++{
++ gctUINT containerSize;
++ gctUINT recordSize;
++ gctUINT recordCount;
++ gcsCONTAINER_LINK_PTR containers;
++ gcsCONTAINER_RECORD freeList;
++ gcsCONTAINER_RECORD allocList;
++}
++gcsCONTAINER;
++
++gceSTATUS
++gcsCONTAINER_Construct(
++ IN gcsCONTAINER_PTR Container,
++ gctUINT RecordsPerContainer,
++ gctUINT RecordSize
++ );
++
++gceSTATUS
++gcsCONTAINER_Destroy(
++ IN gcsCONTAINER_PTR Container
++ );
++
++gceSTATUS
++gcsCONTAINER_AllocateRecord(
++ IN gcsCONTAINER_PTR Container,
++ OUT gctPOINTER * Record
++ );
++
++gceSTATUS
++gcsCONTAINER_FreeRecord(
++ IN gcsCONTAINER_PTR Container,
++ IN gctPOINTER Record
++ );
++
++gceSTATUS
++gcsCONTAINER_FreeAll(
++ IN gcsCONTAINER_PTR Container
++ );
++
++/******************************************************************************\
++********************************* gcoHAL Object *********************************
++\******************************************************************************/
++
++/* Construct a new gcoHAL object. */
++gceSTATUS
++gcoHAL_Construct(
++ IN gctPOINTER Context,
++ IN gcoOS Os,
++ OUT gcoHAL * Hal
++ );
++
++/* Destroy an gcoHAL object. */
++gceSTATUS
++gcoHAL_Destroy(
++ IN gcoHAL Hal
++ );
++
++/* Get pointer to gco2D object. */
++gceSTATUS
++gcoHAL_Get2DEngine(
++ IN gcoHAL Hal,
++ OUT gco2D * Engine
++ );
++
++gceSTATUS
++gcoHAL_SetFscaleValue(
++ IN gctUINT FscaleValue
++ );
++
++gceSTATUS
++gcoHAL_GetFscaleValue(
++ OUT gctUINT * FscaleValue,
++ OUT gctUINT * MinFscaleValue,
++ OUT gctUINT * MaxFscaleValue
++ );
++
++gceSTATUS
++gcoHAL_SetBltNP2Texture(
++ gctBOOL enable
++ );
++
++#ifndef VIVANTE_NO_3D
++/* Get pointer to gco3D object. */
++gceSTATUS
++gcoHAL_Get3DEngine(
++ IN gcoHAL Hal,
++ OUT gco3D * Engine
++ );
++
++gceSTATUS
++gcoHAL_Query3DEngine(
++ IN gcoHAL Hal,
++ OUT gco3D * Engine
++ );
++
++gceSTATUS
++gcoHAL_Set3DEngine(
++ IN gcoHAL Hal,
++ IN gco3D Engine
++ );
++
++gceSTATUS
++gcoHAL_Get3DHardware(
++ IN gcoHAL Hal,
++ OUT gcoHARDWARE * Hardware
++ );
++
++gceSTATUS
++gcoHAL_Set3DHardware(
++ IN gcoHAL Hal,
++ IN gcoHARDWARE Hardware
++ );
++
++
++#endif /* VIVANTE_NO_3D */
++
++/* Verify whether the specified feature is available in hardware. */
++gceSTATUS
++gcoHAL_IsFeatureAvailable(
++ IN gcoHAL Hal,
++ IN gceFEATURE Feature
++ );
++
++/* Query the identity of the hardware. */
++gceSTATUS
++gcoHAL_QueryChipIdentity(
++ IN gcoHAL Hal,
++ OUT gceCHIPMODEL* ChipModel,
++ OUT gctUINT32* ChipRevision,
++ OUT gctUINT32* ChipFeatures,
++ OUT gctUINT32* ChipMinorFeatures
++ );
++
++/* Query the minor features of the hardware. */
++gceSTATUS gcoHAL_QueryChipMinorFeatures(
++ IN gcoHAL Hal,
++ OUT gctUINT32* NumFeatures,
++ OUT gctUINT32* ChipMinorFeatures
++ );
++
++/* Query the amount of video memory. */
++gceSTATUS
++gcoHAL_QueryVideoMemory(
++ IN gcoHAL Hal,
++ OUT gctPHYS_ADDR * InternalAddress,
++ OUT gctSIZE_T * InternalSize,
++ OUT gctPHYS_ADDR * ExternalAddress,
++ OUT gctSIZE_T * ExternalSize,
++ OUT gctPHYS_ADDR * ContiguousAddress,
++ OUT gctSIZE_T * ContiguousSize
++ );
++
++/* Map video memory. */
++gceSTATUS
++gcoHAL_MapMemory(
++ IN gcoHAL Hal,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T NumberOfBytes,
++ OUT gctPOINTER * Logical
++ );
++
++/* Unmap video memory. */
++gceSTATUS
++gcoHAL_UnmapMemory(
++ IN gcoHAL Hal,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T NumberOfBytes,
++ IN gctPOINTER Logical
++ );
++
++/* Schedule an unmap of a buffer mapped through its physical address. */
++gceSTATUS
++gcoHAL_ScheduleUnmapMemory(
++ IN gcoHAL Hal,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T NumberOfBytes,
++ IN gctPOINTER Logical
++ );
++
++/* Map user memory. */
++gceSTATUS
++gcoHAL_MapUserMemory(
++ IN gctPOINTER Logical,
++ IN gctUINT32 Physical,
++ IN gctSIZE_T Size,
++ OUT gctPOINTER * Info,
++ OUT gctUINT32_PTR GPUAddress
++ );
++
++/* Unmap user memory. */
++gceSTATUS
++gcoHAL_UnmapUserMemory(
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Size,
++ IN gctPOINTER Info,
++ IN gctUINT32 GPUAddress
++ );
++
++/* Schedule an unmap of a user buffer using event mechanism. */
++gceSTATUS
++gcoHAL_ScheduleUnmapUserMemory(
++ IN gcoHAL Hal,
++ IN gctPOINTER Info,
++ IN gctSIZE_T Size,
++ IN gctUINT32 Address,
++ IN gctPOINTER Memory
++ );
++
++/* Commit the current command buffer. */
++gceSTATUS
++gcoHAL_Commit(
++ IN gcoHAL Hal,
++ IN gctBOOL Stall
++ );
++
++/* Query the tile capabilities. */
++gceSTATUS
++gcoHAL_QueryTiled(
++ IN gcoHAL Hal,
++ OUT gctINT32 * TileWidth2D,
++ OUT gctINT32 * TileHeight2D,
++ OUT gctINT32 * TileWidth3D,
++ OUT gctINT32 * TileHeight3D
++ );
++
++gceSTATUS
++gcoHAL_Compact(
++ IN gcoHAL Hal
++ );
++
++#if VIVANTE_PROFILER
++gceSTATUS
++gcoHAL_ProfileStart(
++ IN gcoHAL Hal
++ );
++
++gceSTATUS
++gcoHAL_ProfileEnd(
++ IN gcoHAL Hal,
++ IN gctCONST_STRING Title
++ );
++#endif
++
++/* Power Management */
++gceSTATUS
++gcoHAL_SetPowerManagementState(
++ IN gcoHAL Hal,
++ IN gceCHIPPOWERSTATE State
++ );
++
++gceSTATUS
++gcoHAL_QueryPowerManagementState(
++ IN gcoHAL Hal,
++ OUT gceCHIPPOWERSTATE *State
++ );
++
++/* Set the filter type for filter blit. */
++gceSTATUS
++gcoHAL_SetFilterType(
++ IN gcoHAL Hal,
++ IN gceFILTER_TYPE FilterType
++ );
++
++gceSTATUS
++gcoHAL_GetDump(
++ IN gcoHAL Hal,
++ OUT gcoDUMP * Dump
++ );
++
++/* Call the kernel HAL layer. */
++gceSTATUS
++gcoHAL_Call(
++ IN gcoHAL Hal,
++ IN OUT gcsHAL_INTERFACE_PTR Interface
++ );
++
++gceSTATUS
++gcoHAL_GetPatchID(
++ IN gcoHAL Hal,
++ OUT gcePATCH_ID * PatchID
++ );
++
++/* Schedule an event. */
++gceSTATUS
++gcoHAL_ScheduleEvent(
++ IN gcoHAL Hal,
++ IN OUT gcsHAL_INTERFACE_PTR Interface
++ );
++
++/* Destroy a surface. */
++gceSTATUS
++gcoHAL_DestroySurface(
++ IN gcoHAL Hal,
++ IN gcoSURF Surface
++ );
++
++/* Request a start/stop timestamp. */
++gceSTATUS
++gcoHAL_SetTimer(
++ IN gcoHAL Hal,
++ IN gctUINT32 Index,
++ IN gctBOOL Start
++ );
++
++/* Get Time delta from a Timer in microseconds. */
++gceSTATUS
++gcoHAL_GetTimerTime(
++ IN gcoHAL Hal,
++ IN gctUINT32 Timer,
++ OUT gctINT32_PTR TimeDelta
++ );
++
++/* set timeout value. */
++gceSTATUS
++gcoHAL_SetTimeOut(
++ IN gcoHAL Hal,
++ IN gctUINT32 timeOut
++ );
++
++gceSTATUS
++gcoHAL_SetHardwareType(
++ IN gcoHAL Hal,
++ IN gceHARDWARE_TYPE HardwardType
++ );
++
++gceSTATUS
++gcoHAL_GetHardwareType(
++ IN gcoHAL Hal,
++ OUT gceHARDWARE_TYPE * HardwardType
++ );
++
++gceSTATUS
++gcoHAL_QueryChipCount(
++ IN gcoHAL Hal,
++ OUT gctINT32 * Count
++ );
++
++gceSTATUS
++gcoHAL_QuerySeparated3D2D(
++ IN gcoHAL Hal
++ );
++
++gceSTATUS
++gcoHAL_QuerySpecialHint(
++ IN gceSPECIAL_HINT Hint
++ );
++
++gceSTATUS
++gcoHAL_SetSpecialHintData(
++ IN gcoHARDWARE Hardware
++ );
++
++/* Get pointer to gcoVG object. */
++gceSTATUS
++gcoHAL_GetVGEngine(
++ IN gcoHAL Hal,
++ OUT gcoVG * Engine
++ );
++
++#if gcdENABLE_VG
++gceSTATUS
++gcoHAL_QueryChipLimits(
++ IN gcoHAL Hal,
++ IN gctINT32 Chip,
++ OUT gcsHAL_LIMITS *Limits);
++
++gceSTATUS
++gcoHAL_QueryChipFeature(
++ IN gcoHAL Hal,
++ IN gctINT32 Chip,
++ IN gceFEATURE Feature);
++
++#endif
++/******************************************************************************\
++********************************** gcoOS Object *********************************
++\******************************************************************************/
++
++/* Get PLS value for given key */
++gctPOINTER
++gcoOS_GetPLSValue(
++ IN gcePLS_VALUE key
++ );
++
++/* Set PLS value of a given key */
++void
++gcoOS_SetPLSValue(
++ IN gcePLS_VALUE key,
++ OUT gctPOINTER value
++ );
++
++/* Get access to the thread local storage. */
++gceSTATUS
++gcoOS_GetTLS(
++ OUT gcsTLS_PTR * TLS
++ );
++
++ /* Copy the TLS from a source thread. */
++ gceSTATUS gcoOS_CopyTLS(IN gcsTLS_PTR Source);
++
++/* Destroy the objects associated with the current thread. */
++void
++gcoOS_FreeThreadData(
++ IN gctBOOL ProcessExiting
++ );
++
++/* Construct a new gcoOS object. */
++gceSTATUS
++gcoOS_Construct(
++ IN gctPOINTER Context,
++ OUT gcoOS * Os
++ );
++
++/* Destroy an gcoOS object. */
++gceSTATUS
++gcoOS_Destroy(
++ IN gcoOS Os
++ );
++
++/* Get the base address for the physical memory. */
++gceSTATUS
++gcoOS_GetBaseAddress(
++ IN gcoOS Os,
++ OUT gctUINT32_PTR BaseAddress
++ );
++
++/* Allocate memory from the heap. */
++gceSTATUS
++gcoOS_Allocate(
++ IN gcoOS Os,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Memory
++ );
++
++/* Get allocated memory size. */
++gceSTATUS
++gcoOS_GetMemorySize(
++ IN gcoOS Os,
++ IN gctPOINTER Memory,
++ OUT gctSIZE_T_PTR MemorySize
++ );
++
++/* Free allocated memory. */
++gceSTATUS
++gcoOS_Free(
++ IN gcoOS Os,
++ IN gctPOINTER Memory
++ );
++
++/* Allocate memory. */
++gceSTATUS
++gcoOS_AllocateMemory(
++ IN gcoOS Os,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Memory
++ );
++
++/* Free memory. */
++gceSTATUS
++gcoOS_FreeMemory(
++ IN gcoOS Os,
++ IN gctPOINTER Memory
++ );
++
++/* Allocate contiguous memory. */
++gceSTATUS
++gcoOS_AllocateContiguous(
++ IN gcoOS Os,
++ IN gctBOOL InUserSpace,
++ IN OUT gctSIZE_T * Bytes,
++ OUT gctPHYS_ADDR * Physical,
++ OUT gctPOINTER * Logical
++ );
++
++/* Free contiguous memory. */
++gceSTATUS
++gcoOS_FreeContiguous(
++ IN gcoOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes
++ );
++
++/* Allocate video memory. */
++gceSTATUS
++gcoOS_AllocateVideoMemory(
++ IN gcoOS Os,
++ IN gctBOOL InUserSpace,
++ IN gctBOOL InCacheable,
++ IN OUT gctSIZE_T * Bytes,
++ OUT gctUINT32 * Physical,
++ OUT gctPOINTER * Logical,
++ OUT gctPOINTER * Handle
++ );
++
++/* Free video memory. */
++gceSTATUS
++gcoOS_FreeVideoMemory(
++ IN gcoOS Os,
++ IN gctPOINTER Handle
++ );
++
++gceSTATUS
++gcoSURF_GetBankOffsetBytes(
++ IN gcoSURF Surfce,
++ IN gceSURF_TYPE Type,
++ IN gctUINT32 Stride,
++ IN gctUINT32_PTR Bytes
++ );
++
++/* Map user memory. */
++gceSTATUS
++gcoOS_MapUserMemory(
++ IN gcoOS Os,
++ IN gctPOINTER Memory,
++ IN gctSIZE_T Size,
++ OUT gctPOINTER * Info,
++ OUT gctUINT32_PTR Address
++ );
++
++/* Map user memory. */
++gceSTATUS
++gcoOS_MapUserMemoryEx(
++ IN gcoOS Os,
++ IN gctPOINTER Memory,
++ IN gctUINT32 Physical,
++ IN gctSIZE_T Size,
++ OUT gctPOINTER * Info,
++ OUT gctUINT32_PTR Address
++ );
++
++/* Unmap user memory. */
++gceSTATUS
++gcoOS_UnmapUserMemory(
++ IN gcoOS Os,
++ IN gctPOINTER Memory,
++ IN gctSIZE_T Size,
++ IN gctPOINTER Info,
++ IN gctUINT32 Address
++ );
++
++/* Device I/O Control call to the kernel HAL layer. */
++gceSTATUS
++gcoOS_DeviceControl(
++ IN gcoOS Os,
++ IN gctUINT32 IoControlCode,
++ IN gctPOINTER InputBuffer,
++ IN gctSIZE_T InputBufferSize,
++ IN gctPOINTER OutputBuffer,
++ IN gctSIZE_T OutputBufferSize
++ );
++
++/* Allocate non paged memory. */
++gceSTATUS
++gcoOS_AllocateNonPagedMemory(
++ IN gcoOS Os,
++ IN gctBOOL InUserSpace,
++ IN OUT gctSIZE_T * Bytes,
++ OUT gctPHYS_ADDR * Physical,
++ OUT gctPOINTER * Logical
++ );
++
++/* Free non paged memory. */
++gceSTATUS
++gcoOS_FreeNonPagedMemory(
++ IN gcoOS Os,
++ IN gctSIZE_T Bytes,
++ IN gctPHYS_ADDR Physical,
++ IN gctPOINTER Logical
++ );
++
++#define gcmOS_SAFE_FREE(os, mem) \
++ gcoOS_Free(os, mem); \
++ mem = gcvNULL
++
++#define gcmkOS_SAFE_FREE(os, mem) \
++ gckOS_Free(os, mem); \
++ mem = gcvNULL
++
++typedef enum _gceFILE_MODE
++{
++ gcvFILE_CREATE = 0,
++ gcvFILE_APPEND,
++ gcvFILE_READ,
++ gcvFILE_CREATETEXT,
++ gcvFILE_APPENDTEXT,
++ gcvFILE_READTEXT,
++}
++gceFILE_MODE;
++
++/* Open a file. */
++gceSTATUS
++gcoOS_Open(
++ IN gcoOS Os,
++ IN gctCONST_STRING FileName,
++ IN gceFILE_MODE Mode,
++ OUT gctFILE * File
++ );
++
++/* Close a file. */
++gceSTATUS
++gcoOS_Close(
++ IN gcoOS Os,
++ IN gctFILE File
++ );
++
++/* Read data from a file. */
++gceSTATUS
++gcoOS_Read(
++ IN gcoOS Os,
++ IN gctFILE File,
++ IN gctSIZE_T ByteCount,
++ IN gctPOINTER Data,
++ OUT gctSIZE_T * ByteRead
++ );
++
++/* Write data to a file. */
++gceSTATUS
++gcoOS_Write(
++ IN gcoOS Os,
++ IN gctFILE File,
++ IN gctSIZE_T ByteCount,
++ IN gctCONST_POINTER Data
++ );
++
++/* Flush data to a file. */
++gceSTATUS
++gcoOS_Flush(
++ IN gcoOS Os,
++ IN gctFILE File
++ );
++
++/* Close a file descriptor. */
++gceSTATUS
++gcoOS_CloseFD(
++ IN gcoOS Os,
++ IN gctINT FD
++ );
++
++/* Dup file descriptor to another. */
++gceSTATUS
++gcoOS_DupFD(
++ IN gcoOS Os,
++ IN gctINT FD,
++ OUT gctINT * FD2
++ );
++
++/* Create an endpoint for communication. */
++gceSTATUS
++gcoOS_Socket(
++ IN gcoOS Os,
++ IN gctINT Domain,
++ IN gctINT Type,
++ IN gctINT Protocol,
++ OUT gctINT *SockFd
++ );
++
++/* Close a socket. */
++gceSTATUS
++gcoOS_CloseSocket(
++ IN gcoOS Os,
++ IN gctINT SockFd
++ );
++
++/* Initiate a connection on a socket. */
++gceSTATUS
++gcoOS_Connect(
++ IN gcoOS Os,
++ IN gctINT SockFd,
++ IN gctCONST_POINTER HostName,
++ IN gctUINT Port);
++
++/* Shut down part of connection on a socket. */
++gceSTATUS
++gcoOS_Shutdown(
++ IN gcoOS Os,
++ IN gctINT SockFd,
++ IN gctINT How
++ );
++
++/* Send a message on a socket. */
++gceSTATUS
++gcoOS_Send(
++ IN gcoOS Os,
++ IN gctINT SockFd,
++ IN gctSIZE_T ByteCount,
++ IN gctCONST_POINTER Data,
++ IN gctINT Flags
++ );
++
++/* Initiate a connection on a socket. */
++gceSTATUS
++gcoOS_WaitForSend(
++ IN gcoOS Os,
++ IN gctINT SockFd,
++ IN gctINT Seconds,
++ IN gctINT MicroSeconds);
++
++/* Get environment variable value. */
++gceSTATUS
++gcoOS_GetEnv(
++ IN gcoOS Os,
++ IN gctCONST_STRING VarName,
++ OUT gctSTRING * Value
++ );
++
++/* Set environment variable value. */
++gceSTATUS
++gcoOS_SetEnv(
++ IN gcoOS Os,
++ IN gctCONST_STRING VarName,
++ IN gctSTRING Value
++ );
++
++/* Get current working directory. */
++gceSTATUS
++gcoOS_GetCwd(
++ IN gcoOS Os,
++ IN gctINT SizeInBytes,
++ OUT gctSTRING Buffer
++ );
++
++/* Get file status info. */
++gceSTATUS
++gcoOS_Stat(
++ IN gcoOS Os,
++ IN gctCONST_STRING FileName,
++ OUT gctPOINTER Buffer
++ );
++
++typedef enum _gceFILE_WHENCE
++{
++ gcvFILE_SEEK_SET,
++ gcvFILE_SEEK_CUR,
++ gcvFILE_SEEK_END
++}
++gceFILE_WHENCE;
++
++/* Set the current position of a file. */
++gceSTATUS
++gcoOS_Seek(
++ IN gcoOS Os,
++ IN gctFILE File,
++ IN gctUINT32 Offset,
++ IN gceFILE_WHENCE Whence
++ );
++
++/* Set the current position of a file. */
++gceSTATUS
++gcoOS_SetPos(
++ IN gcoOS Os,
++ IN gctFILE File,
++ IN gctUINT32 Position
++ );
++
++/* Get the current position of a file. */
++gceSTATUS
++gcoOS_GetPos(
++ IN gcoOS Os,
++ IN gctFILE File,
++ OUT gctUINT32 * Position
++ );
++
++/* Same as strstr. */
++gceSTATUS
++gcoOS_StrStr(
++ IN gctCONST_STRING String,
++ IN gctCONST_STRING SubString,
++ OUT gctSTRING * Output
++ );
++
++/* Find the last occurance of a character inside a string. */
++gceSTATUS
++gcoOS_StrFindReverse(
++ IN gctCONST_STRING String,
++ IN gctINT8 Character,
++ OUT gctSTRING * Output
++ );
++
++gceSTATUS
++gcoOS_StrDup(
++ IN gcoOS Os,
++ IN gctCONST_STRING String,
++ OUT gctSTRING * Target
++ );
++
++/* Copy a string. */
++gceSTATUS
++gcoOS_StrCopySafe(
++ IN gctSTRING Destination,
++ IN gctSIZE_T DestinationSize,
++ IN gctCONST_STRING Source
++ );
++
++/* Append a string. */
++gceSTATUS
++gcoOS_StrCatSafe(
++ IN gctSTRING Destination,
++ IN gctSIZE_T DestinationSize,
++ IN gctCONST_STRING Source
++ );
++
++/* Compare two strings. */
++gceSTATUS
++gcoOS_StrCmp(
++ IN gctCONST_STRING String1,
++ IN gctCONST_STRING String2
++ );
++
++/* Compare characters of two strings. */
++gceSTATUS
++gcoOS_StrNCmp(
++ IN gctCONST_STRING String1,
++ IN gctCONST_STRING String2,
++ IN gctSIZE_T Count
++ );
++
++/* Convert string to float. */
++gceSTATUS
++gcoOS_StrToFloat(
++ IN gctCONST_STRING String,
++ OUT gctFLOAT * Float
++ );
++
++/* Convert hex string to integer. */
++gceSTATUS
++gcoOS_HexStrToInt(
++ IN gctCONST_STRING String,
++ OUT gctINT * Int
++ );
++
++/* Convert hex string to float. */
++gceSTATUS
++gcoOS_HexStrToFloat(
++ IN gctCONST_STRING String,
++ OUT gctFLOAT * Float
++ );
++
++/* Convert string to integer. */
++gceSTATUS
++gcoOS_StrToInt(
++ IN gctCONST_STRING String,
++ OUT gctINT * Int
++ );
++
++gceSTATUS
++gcoOS_MemCmp(
++ IN gctCONST_POINTER Memory1,
++ IN gctCONST_POINTER Memory2,
++ IN gctSIZE_T Bytes
++ );
++
++gceSTATUS
++gcoOS_PrintStrSafe(
++ OUT gctSTRING String,
++ IN gctSIZE_T StringSize,
++ IN OUT gctUINT * Offset,
++ IN gctCONST_STRING Format,
++ ...
++ );
++
++gceSTATUS
++gcoOS_LoadLibrary(
++ IN gcoOS Os,
++ IN gctCONST_STRING Library,
++ OUT gctHANDLE * Handle
++ );
++
++gceSTATUS
++gcoOS_FreeLibrary(
++ IN gcoOS Os,
++ IN gctHANDLE Handle
++ );
++
++gceSTATUS
++gcoOS_GetProcAddress(
++ IN gcoOS Os,
++ IN gctHANDLE Handle,
++ IN gctCONST_STRING Name,
++ OUT gctPOINTER * Function
++ );
++
++gceSTATUS
++gcoOS_Compact(
++ IN gcoOS Os
++ );
++
++gceSTATUS
++gcoOS_AddSignalHandler (
++ IN gceSignalHandlerType SignalHandlerType
++ );
++
++#if VIVANTE_PROFILER
++gceSTATUS
++gcoOS_ProfileStart(
++ IN gcoOS Os
++ );
++
++gceSTATUS
++gcoOS_ProfileEnd(
++ IN gcoOS Os,
++ IN gctCONST_STRING Title
++ );
++
++gceSTATUS
++gcoOS_SetProfileSetting(
++ IN gcoOS Os,
++ IN gctBOOL Enable,
++ IN gctCONST_STRING FileName
++ );
++#endif
++
++gctBOOL
++gcoOS_IsNeededSupportNP2Texture(
++ IN gctCHAR* ProcName
++ );
++
++/* Query the video memory. */
++gceSTATUS
++gcoOS_QueryVideoMemory(
++ IN gcoOS Os,
++ OUT gctPHYS_ADDR * InternalAddress,
++ OUT gctSIZE_T * InternalSize,
++ OUT gctPHYS_ADDR * ExternalAddress,
++ OUT gctSIZE_T * ExternalSize,
++ OUT gctPHYS_ADDR * ContiguousAddress,
++ OUT gctSIZE_T * ContiguousSize
++ );
++
++/* Detect if the process is the executable specified. */
++gceSTATUS
++gcoOS_DetectProcessByNamePid(
++ IN gctCONST_STRING Name,
++ IN gctHANDLE Pid
++ );
++
++/* Detect if the current process is the executable specified. */
++gceSTATUS
++gcoOS_DetectProcessByName(
++ IN gctCONST_STRING Name
++ );
++
++gceSTATUS
++gcoOS_DetectProcessByEncryptedName(
++ IN gctCONST_STRING Name
++ );
++
++#if defined(ANDROID)
++gceSTATUS
++gcoOS_DetectProgrameByEncryptedSymbols(
++ IN gcoOS_SymbolsList Symbols
++ );
++#endif
++
++/*----------------------------------------------------------------------------*/
++/*----- Atoms ----------------------------------------------------------------*/
++
++/* Construct an atom. */
++gceSTATUS
++gcoOS_AtomConstruct(
++ IN gcoOS Os,
++ OUT gcsATOM_PTR * Atom
++ );
++
++/* Destroy an atom. */
++gceSTATUS
++gcoOS_AtomDestroy(
++ IN gcoOS Os,
++ IN gcsATOM_PTR Atom
++ );
++
++/* Increment an atom. */
++gceSTATUS
++gcoOS_AtomIncrement(
++ IN gcoOS Os,
++ IN gcsATOM_PTR Atom,
++ OUT gctINT32_PTR OldValue
++ );
++
++/* Decrement an atom. */
++gceSTATUS
++gcoOS_AtomDecrement(
++ IN gcoOS Os,
++ IN gcsATOM_PTR Atom,
++ OUT gctINT32_PTR OldValue
++ );
++
++gctHANDLE
++gcoOS_GetCurrentProcessID(
++ void
++ );
++
++gctHANDLE
++gcoOS_GetCurrentThreadID(
++ void
++ );
++
++/*----------------------------------------------------------------------------*/
++/*----- Time -----------------------------------------------------------------*/
++
++/* Get the number of milliseconds since the system started. */
++gctUINT32
++gcoOS_GetTicks(
++ void
++ );
++
++/* Get time in microseconds. */
++gceSTATUS
++gcoOS_GetTime(
++ gctUINT64_PTR Time
++ );
++
++/* Get CPU usage in microseconds. */
++gceSTATUS
++gcoOS_GetCPUTime(
++ gctUINT64_PTR CPUTime
++ );
++
++/* Get memory usage. */
++gceSTATUS
++gcoOS_GetMemoryUsage(
++ gctUINT32_PTR MaxRSS,
++ gctUINT32_PTR IxRSS,
++ gctUINT32_PTR IdRSS,
++ gctUINT32_PTR IsRSS
++ );
++
++/* Delay a number of microseconds. */
++gceSTATUS
++gcoOS_Delay(
++ IN gcoOS Os,
++ IN gctUINT32 Delay
++ );
++
++/*----------------------------------------------------------------------------*/
++/*----- Threads --------------------------------------------------------------*/
++
++#ifdef _WIN32
++/* Cannot include windows.h here becuase "near" and "far"
++ * which are used in gcsDEPTH_INFO, are defined to nothing in WinDef.h.
++ * So, use the real value of DWORD and WINAPI, instead.
++ * DWORD is unsigned long, and WINAPI is __stdcall.
++ * If these two are change in WinDef.h, the following two typdefs
++ * need to be changed, too.
++ */
++typedef unsigned long gctTHREAD_RETURN;
++typedef unsigned long (__stdcall * gcTHREAD_ROUTINE)(void * Argument);
++#else
++typedef void * gctTHREAD_RETURN;
++typedef void * (* gcTHREAD_ROUTINE)(void *);
++#endif
++
++/* Create a new thread. */
++gceSTATUS
++gcoOS_CreateThread(
++ IN gcoOS Os,
++ IN gcTHREAD_ROUTINE Worker,
++ IN gctPOINTER Argument,
++ OUT gctPOINTER * Thread
++ );
++
++/* Close a thread. */
++gceSTATUS
++gcoOS_CloseThread(
++ IN gcoOS Os,
++ IN gctPOINTER Thread
++ );
++
++/*----------------------------------------------------------------------------*/
++/*----- Mutexes --------------------------------------------------------------*/
++
++/* Create a new mutex. */
++gceSTATUS
++gcoOS_CreateMutex(
++ IN gcoOS Os,
++ OUT gctPOINTER * Mutex
++ );
++
++/* Delete a mutex. */
++gceSTATUS
++gcoOS_DeleteMutex(
++ IN gcoOS Os,
++ IN gctPOINTER Mutex
++ );
++
++/* Acquire a mutex. */
++gceSTATUS
++gcoOS_AcquireMutex(
++ IN gcoOS Os,
++ IN gctPOINTER Mutex,
++ IN gctUINT32 Timeout
++ );
++
++/* Release a mutex. */
++gceSTATUS
++gcoOS_ReleaseMutex(
++ IN gcoOS Os,
++ IN gctPOINTER Mutex
++ );
++
++/*----------------------------------------------------------------------------*/
++/*----- Signals --------------------------------------------------------------*/
++
++/* Create a signal. */
++gceSTATUS
++gcoOS_CreateSignal(
++ IN gcoOS Os,
++ IN gctBOOL ManualReset,
++ OUT gctSIGNAL * Signal
++ );
++
++/* Destroy a signal. */
++gceSTATUS
++gcoOS_DestroySignal(
++ IN gcoOS Os,
++ IN gctSIGNAL Signal
++ );
++
++/* Signal a signal. */
++gceSTATUS
++gcoOS_Signal(
++ IN gcoOS Os,
++ IN gctSIGNAL Signal,
++ IN gctBOOL State
++ );
++
++/* Wait for a signal. */
++gceSTATUS
++gcoOS_WaitSignal(
++ IN gcoOS Os,
++ IN gctSIGNAL Signal,
++ IN gctUINT32 Wait
++ );
++
++/* Map a signal from another process */
++gceSTATUS
++gcoOS_MapSignal(
++ IN gctSIGNAL RemoteSignal,
++ OUT gctSIGNAL * LocalSignal
++ );
++
++/* Unmap a signal mapped from another process */
++gceSTATUS
++gcoOS_UnmapSignal(
++ IN gctSIGNAL Signal
++ );
++
++/*----------------------------------------------------------------------------*/
++/*----- Android Native Fence -------------------------------------------------*/
++
++/* Create sync point. */
++gceSTATUS
++gcoOS_CreateSyncPoint(
++ IN gcoOS Os,
++ OUT gctSYNC_POINT * SyncPoint
++ );
++
++/* Destroy sync point. */
++gceSTATUS
++gcoOS_DestroySyncPoint(
++ IN gcoOS Os,
++ IN gctSYNC_POINT SyncPoint
++ );
++
++/* Create native fence. */
++gceSTATUS
++gcoOS_CreateNativeFence(
++ IN gcoOS Os,
++ IN gctSYNC_POINT SyncPoint,
++ OUT gctINT * FenceFD
++ );
++
++/* Wait on native fence. */
++gceSTATUS
++gcoOS_WaitNativeFence(
++ IN gcoOS Os,
++ IN gctINT FenceFD,
++ IN gctUINT32 Timeout
++ );
++
++/*----------------------------------------------------------------------------*/
++/*----- Memory Access and Cache ----------------------------------------------*/
++
++/* Write a register. */
++gceSTATUS
++gcoOS_WriteRegister(
++ IN gcoOS Os,
++ IN gctUINT32 Address,
++ IN gctUINT32 Data
++ );
++
++/* Read a register. */
++gceSTATUS
++gcoOS_ReadRegister(
++ IN gcoOS Os,
++ IN gctUINT32 Address,
++ OUT gctUINT32 * Data
++ );
++
++gceSTATUS
++gcoOS_CacheClean(
++ IN gcoOS Os,
++ IN gctUINT64 Node,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes
++ );
++
++gceSTATUS
++gcoOS_CacheFlush(
++ IN gcoOS Os,
++ IN gctUINT64 Node,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes
++ );
++
++gceSTATUS
++gcoOS_CacheInvalidate(
++ IN gcoOS Os,
++ IN gctUINT64 Node,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes
++ );
++
++gceSTATUS
++gcoOS_MemoryBarrier(
++ IN gcoOS Os,
++ IN gctPOINTER Logical
++ );
++
++
++/*----------------------------------------------------------------------------*/
++/*----- Profile --------------------------------------------------------------*/
++
++gceSTATUS
++gckOS_GetProfileTick(
++ OUT gctUINT64_PTR Tick
++ );
++
++gceSTATUS
++gckOS_QueryProfileTickRate(
++ OUT gctUINT64_PTR TickRate
++ );
++
++gctUINT32
++gckOS_ProfileToMS(
++ IN gctUINT64 Ticks
++ );
++
++gceSTATUS
++gcoOS_GetProfileTick(
++ OUT gctUINT64_PTR Tick
++ );
++
++gceSTATUS
++gcoOS_QueryProfileTickRate(
++ OUT gctUINT64_PTR TickRate
++ );
++
++#define _gcmPROFILE_INIT(prefix, freq, start) \
++ do { \
++ prefix ## OS_QueryProfileTickRate(&(freq)); \
++ prefix ## OS_GetProfileTick(&(start)); \
++ } while (gcvFALSE)
++
++#define _gcmPROFILE_QUERY(prefix, start, ticks) \
++ do { \
++ prefix ## OS_GetProfileTick(&(ticks)); \
++ (ticks) = ((ticks) > (start)) ? ((ticks) - (start)) \
++ : (~0ull - (start) + (ticks) + 1); \
++ } while (gcvFALSE)
++
++#if gcdENABLE_PROFILING
++# define gcmkPROFILE_INIT(freq, start) _gcmPROFILE_INIT(gck, freq, start)
++# define gcmkPROFILE_QUERY(start, ticks) _gcmPROFILE_QUERY(gck, start, ticks)
++# define gcmPROFILE_INIT(freq, start) _gcmPROFILE_INIT(gco, freq, start)
++# define gcmPROFILE_QUERY(start, ticks) _gcmPROFILE_QUERY(gco, start, ticks)
++# define gcmPROFILE_ONLY(x) x
++# define gcmPROFILE_ELSE(x) do { } while (gcvFALSE)
++# define gcmPROFILE_DECLARE_ONLY(x) x
++# define gcmPROFILE_DECLARE_ELSE(x) typedef x
++#else
++# define gcmkPROFILE_INIT(start, freq) do { } while (gcvFALSE)
++# define gcmkPROFILE_QUERY(start, ticks) do { } while (gcvFALSE)
++# define gcmPROFILE_INIT(start, freq) do { } while (gcvFALSE)
++# define gcmPROFILE_QUERY(start, ticks) do { } while (gcvFALSE)
++# define gcmPROFILE_ONLY(x) do { } while (gcvFALSE)
++# define gcmPROFILE_ELSE(x) x
++# define gcmPROFILE_DECLARE_ONLY(x) do { } while (gcvFALSE)
++# define gcmPROFILE_DECLARE_ELSE(x) x
++#endif
++
++/*******************************************************************************
++** gcoMATH object
++*/
++
++#define gcdPI 3.14159265358979323846f
++
++/* Kernel. */
++gctINT
++gckMATH_ModuloInt(
++ IN gctINT X,
++ IN gctINT Y
++ );
++
++/* User. */
++gctUINT32
++gcoMATH_Log2in5dot5(
++ IN gctINT X
++ );
++
++
++gctFLOAT
++gcoMATH_UIntAsFloat(
++ IN gctUINT32 X
++ );
++
++gctUINT32
++gcoMATH_FloatAsUInt(
++ IN gctFLOAT X
++ );
++
++gctBOOL
++gcoMATH_CompareEqualF(
++ IN gctFLOAT X,
++ IN gctFLOAT Y
++ );
++
++gctUINT16
++gcoMATH_UInt8AsFloat16(
++ IN gctUINT8 X
++ );
++
++/******************************************************************************\
++**************************** Coordinate Structures *****************************
++\******************************************************************************/
++
++typedef struct _gcsPOINT
++{
++ gctINT32 x;
++ gctINT32 y;
++}
++gcsPOINT;
++
++typedef struct _gcsSIZE
++{
++ gctINT32 width;
++ gctINT32 height;
++}
++gcsSIZE;
++
++typedef struct _gcsRECT
++{
++ gctINT32 left;
++ gctINT32 top;
++ gctINT32 right;
++ gctINT32 bottom;
++}
++gcsRECT;
++
++typedef union _gcsPIXEL
++{
++ struct
++ {
++ gctFLOAT r, g, b, a;
++ gctFLOAT d, s;
++ } pf;
++
++ struct
++ {
++ gctINT32 r, g, b, a;
++ gctINT32 d, s;
++ } pi;
++
++ struct
++ {
++ gctUINT32 r, g, b, a;
++ gctUINT32 d, s;
++ } pui;
++
++} gcsPIXEL;
++
++
++/******************************************************************************\
++********************************* gcoSURF Object ********************************
++\******************************************************************************/
++
++/*----------------------------------------------------------------------------*/
++/*------------------------------- gcoSURF Common ------------------------------*/
++
++/* Color format classes. */
++typedef enum _gceFORMAT_CLASS
++{
++ gcvFORMAT_CLASS_RGBA = 4500,
++ gcvFORMAT_CLASS_YUV,
++ gcvFORMAT_CLASS_INDEX,
++ gcvFORMAT_CLASS_LUMINANCE,
++ gcvFORMAT_CLASS_BUMP,
++ gcvFORMAT_CLASS_DEPTH,
++}
++gceFORMAT_CLASS;
++
++/* Special enums for width field in gcsFORMAT_COMPONENT. */
++typedef enum _gceCOMPONENT_CONTROL
++{
++ gcvCOMPONENT_NOTPRESENT = 0x00,
++ gcvCOMPONENT_DONTCARE = 0x80,
++ gcvCOMPONENT_WIDTHMASK = 0x7F,
++ gcvCOMPONENT_ODD = 0x80
++}
++gceCOMPONENT_CONTROL;
++
++/* Color format component parameters. */
++typedef struct _gcsFORMAT_COMPONENT
++{
++ gctUINT8 start;
++ gctUINT8 width;
++}
++gcsFORMAT_COMPONENT;
++
++/* RGBA color format class. */
++typedef struct _gcsFORMAT_CLASS_TYPE_RGBA
++{
++ gcsFORMAT_COMPONENT alpha;
++ gcsFORMAT_COMPONENT red;
++ gcsFORMAT_COMPONENT green;
++ gcsFORMAT_COMPONENT blue;
++}
++gcsFORMAT_CLASS_TYPE_RGBA;
++
++/* YUV color format class. */
++typedef struct _gcsFORMAT_CLASS_TYPE_YUV
++{
++ gcsFORMAT_COMPONENT y;
++ gcsFORMAT_COMPONENT u;
++ gcsFORMAT_COMPONENT v;
++}
++gcsFORMAT_CLASS_TYPE_YUV;
++
++/* Index color format class. */
++typedef struct _gcsFORMAT_CLASS_TYPE_INDEX
++{
++ gcsFORMAT_COMPONENT value;
++}
++gcsFORMAT_CLASS_TYPE_INDEX;
++
++/* Luminance color format class. */
++typedef struct _gcsFORMAT_CLASS_TYPE_LUMINANCE
++{
++ gcsFORMAT_COMPONENT alpha;
++ gcsFORMAT_COMPONENT value;
++}
++gcsFORMAT_CLASS_TYPE_LUMINANCE;
++
++/* Bump map color format class. */
++typedef struct _gcsFORMAT_CLASS_TYPE_BUMP
++{
++ gcsFORMAT_COMPONENT alpha;
++ gcsFORMAT_COMPONENT l;
++ gcsFORMAT_COMPONENT v;
++ gcsFORMAT_COMPONENT u;
++ gcsFORMAT_COMPONENT q;
++ gcsFORMAT_COMPONENT w;
++}
++gcsFORMAT_CLASS_TYPE_BUMP;
++
++/* Depth and stencil format class. */
++typedef struct _gcsFORMAT_CLASS_TYPE_DEPTH
++{
++ gcsFORMAT_COMPONENT depth;
++ gcsFORMAT_COMPONENT stencil;
++}
++gcsFORMAT_CLASS_TYPE_DEPTH;
++
++/* Format parameters. */
++typedef struct _gcsSURF_FORMAT_INFO
++{
++ /* Format code and class. */
++ gceSURF_FORMAT format;
++ gceFORMAT_CLASS fmtClass;
++
++ /* The size of one pixel in bits. */
++ gctUINT8 bitsPerPixel;
++
++ /* Component swizzle. */
++ gceSURF_SWIZZLE swizzle;
++
++ /* Some formats have two neighbour pixels interleaved together. */
++ /* To describe such format, set the flag to 1 and add another */
++ /* like this one describing the odd pixel format. */
++ gctUINT8 interleaved;
++
++ /* Format components. */
++ union
++ {
++ gcsFORMAT_CLASS_TYPE_BUMP bump;
++ gcsFORMAT_CLASS_TYPE_RGBA rgba;
++ gcsFORMAT_CLASS_TYPE_YUV yuv;
++ gcsFORMAT_CLASS_TYPE_LUMINANCE lum;
++ gcsFORMAT_CLASS_TYPE_INDEX index;
++ gcsFORMAT_CLASS_TYPE_DEPTH depth;
++ } u;
++}
++gcsSURF_FORMAT_INFO;
++
++/* Frame buffer information. */
++typedef struct _gcsSURF_FRAMEBUFFER
++{
++ gctPOINTER logical;
++ gctUINT width, height;
++ gctINT stride;
++ gceSURF_FORMAT format;
++}
++gcsSURF_FRAMEBUFFER;
++
++typedef struct _gcsVIDMEM_NODE_SHARED_INFO
++{
++ gctBOOL tileStatusDisabled;
++ gcsPOINT SrcOrigin;
++ gcsPOINT DestOrigin;
++ gcsSIZE RectSize;
++ gctUINT32 clearValue;
++}
++gcsVIDMEM_NODE_SHARED_INFO;
++
++/* Generic pixel component descriptors. */
++extern gcsFORMAT_COMPONENT gcvPIXEL_COMP_XXX8;
++extern gcsFORMAT_COMPONENT gcvPIXEL_COMP_XX8X;
++extern gcsFORMAT_COMPONENT gcvPIXEL_COMP_X8XX;
++extern gcsFORMAT_COMPONENT gcvPIXEL_COMP_8XXX;
++
++typedef enum _gceORIENTATION
++{
++ gcvORIENTATION_TOP_BOTTOM,
++ gcvORIENTATION_BOTTOM_TOP,
++}
++gceORIENTATION;
++
++
++/* Construct a new gcoSURF object. */
++gceSTATUS
++gcoSURF_Construct(
++ IN gcoHAL Hal,
++ IN gctUINT Width,
++ IN gctUINT Height,
++ IN gctUINT Depth,
++ IN gceSURF_TYPE Type,
++ IN gceSURF_FORMAT Format,
++ IN gcePOOL Pool,
++ OUT gcoSURF * Surface
++ );
++
++/* Destroy an gcoSURF object. */
++gceSTATUS
++gcoSURF_Destroy(
++ IN gcoSURF Surface
++ );
++
++/* Map user-allocated surface. */
++gceSTATUS
++gcoSURF_MapUserSurface(
++ IN gcoSURF Surface,
++ IN gctUINT Alignment,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Physical
++ );
++
++/* Query vid mem node info. */
++gceSTATUS
++gcoSURF_QueryVidMemNode(
++ IN gcoSURF Surface,
++ OUT gctUINT64 * Node,
++ OUT gcePOOL * Pool,
++ OUT gctUINT_PTR Bytes
++ );
++
++/* Set the color type of the surface. */
++gceSTATUS
++gcoSURF_SetColorType(
++ IN gcoSURF Surface,
++ IN gceSURF_COLOR_TYPE ColorType
++ );
++
++/* Get the color type of the surface. */
++gceSTATUS
++gcoSURF_GetColorType(
++ IN gcoSURF Surface,
++ OUT gceSURF_COLOR_TYPE *ColorType
++ );
++
++/* Set the surface ration angle. */
++gceSTATUS
++gcoSURF_SetRotation(
++ IN gcoSURF Surface,
++ IN gceSURF_ROTATION Rotation
++ );
++
++gceSTATUS
++gcoSURF_SetPreRotation(
++ IN gcoSURF Surface,
++ IN gceSURF_ROTATION Rotation
++ );
++
++gceSTATUS
++gcoSURF_GetPreRotation(
++ IN gcoSURF Surface,
++ IN gceSURF_ROTATION *Rotation
++ );
++
++gceSTATUS
++gcoSURF_IsValid(
++ IN gcoSURF Surface
++ );
++
++#ifndef VIVANTE_NO_3D
++/* Verify and return the state of the tile status mechanism. */
++gceSTATUS
++gcoSURF_IsTileStatusSupported(
++ IN gcoSURF Surface
++ );
++
++/* Process tile status for the specified surface. */
++gceSTATUS
++gcoSURF_SetTileStatus(
++ IN gcoSURF Surface
++ );
++
++/* Enable tile status for the specified surface. */
++gceSTATUS
++gcoSURF_EnableTileStatus(
++ IN gcoSURF Surface
++ );
++
++/* Disable tile status for the specified surface. */
++gceSTATUS
++gcoSURF_DisableTileStatus(
++ IN gcoSURF Surface,
++ IN gctBOOL Decompress
++ );
++
++gceSTATUS
++gcoSURF_AlignResolveRect(
++ IN gcoSURF Surf,
++ IN gcsPOINT_PTR RectOrigin,
++ IN gcsPOINT_PTR RectSize,
++ OUT gcsPOINT_PTR AlignedOrigin,
++ OUT gcsPOINT_PTR AlignedSize
++ );
++#endif /* VIVANTE_NO_3D */
++
++/* Get surface size. */
++gceSTATUS
++gcoSURF_GetSize(
++ IN gcoSURF Surface,
++ OUT gctUINT * Width,
++ OUT gctUINT * Height,
++ OUT gctUINT * Depth
++ );
++
++/* Get surface aligned sizes. */
++gceSTATUS
++gcoSURF_GetAlignedSize(
++ IN gcoSURF Surface,
++ OUT gctUINT * Width,
++ OUT gctUINT * Height,
++ OUT gctINT * Stride
++ );
++
++/* Get alignments. */
++gceSTATUS
++gcoSURF_GetAlignment(
++ IN gceSURF_TYPE Type,
++ IN gceSURF_FORMAT Format,
++ OUT gctUINT * AddressAlignment,
++ OUT gctUINT * XAlignment,
++ OUT gctUINT * YAlignment
++ );
++
++/* Get surface type and format. */
++gceSTATUS
++gcoSURF_GetFormat(
++ IN gcoSURF Surface,
++ OUT gceSURF_TYPE * Type,
++ OUT gceSURF_FORMAT * Format
++ );
++
++/* Get surface tiling. */
++gceSTATUS
++gcoSURF_GetTiling(
++ IN gcoSURF Surface,
++ OUT gceTILING * Tiling
++ );
++
++/* Lock the surface. */
++gceSTATUS
++gcoSURF_Lock(
++ IN gcoSURF Surface,
++ IN OUT gctUINT32 * Address,
++ IN OUT gctPOINTER * Memory
++ );
++
++/* Unlock the surface. */
++gceSTATUS
++gcoSURF_Unlock(
++ IN gcoSURF Surface,
++ IN gctPOINTER Memory
++ );
++
++/* Return pixel format parameters. */
++gceSTATUS
++gcoSURF_QueryFormat(
++ IN gceSURF_FORMAT Format,
++ OUT gcsSURF_FORMAT_INFO_PTR * Info
++ );
++
++/* Compute the color pixel mask. */
++gceSTATUS
++gcoSURF_ComputeColorMask(
++ IN gcsSURF_FORMAT_INFO_PTR Format,
++ OUT gctUINT32_PTR ColorMask
++ );
++
++/* Flush the surface. */
++gceSTATUS
++gcoSURF_Flush(
++ IN gcoSURF Surface
++ );
++
++/* Fill surface from it's tile status buffer. */
++gceSTATUS
++gcoSURF_FillFromTile(
++ IN gcoSURF Surface
++ );
++
++/* Check if surface needs a filler. */
++gceSTATUS gcoSURF_NeedFiller(IN gcoSURF Surface);
++
++/* Fill surface with a value. */
++gceSTATUS
++gcoSURF_Fill(
++ IN gcoSURF Surface,
++ IN gcsPOINT_PTR Origin,
++ IN gcsSIZE_PTR Size,
++ IN gctUINT32 Value,
++ IN gctUINT32 Mask
++ );
++
++/* Alpha blend two surfaces together. */
++gceSTATUS
++gcoSURF_Blend(
++ IN gcoSURF SrcSurface,
++ IN gcoSURF DestSurface,
++ IN gcsPOINT_PTR SrcOrig,
++ IN gcsPOINT_PTR DestOrigin,
++ IN gcsSIZE_PTR Size,
++ IN gceSURF_BLEND_MODE Mode
++ );
++
++/* Create a new gcoSURF wrapper object. */
++gceSTATUS
++gcoSURF_ConstructWrapper(
++ IN gcoHAL Hal,
++ OUT gcoSURF * Surface
++ );
++
++/* Set the underlying buffer for the surface wrapper. */
++gceSTATUS
++gcoSURF_SetBuffer(
++ IN gcoSURF Surface,
++ IN gceSURF_TYPE Type,
++ IN gceSURF_FORMAT Format,
++ IN gctUINT Stride,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Physical
++ );
++
++/* Set the underlying video buffer for the surface wrapper. */
++gceSTATUS
++gcoSURF_SetVideoBuffer(
++ IN gcoSURF Surface,
++ IN gceSURF_TYPE Type,
++ IN gceSURF_FORMAT Format,
++ IN gctUINT Width,
++ IN gctUINT Height,
++ IN gctUINT Stride,
++ IN gctPOINTER *LogicalPlane1,
++ IN gctUINT32 *PhysicalPlane1
++ );
++
++/* Set the size of the surface in pixels and map the underlying buffer. */
++gceSTATUS
++gcoSURF_SetWindow(
++ IN gcoSURF Surface,
++ IN gctUINT X,
++ IN gctUINT Y,
++ IN gctUINT Width,
++ IN gctUINT Height
++ );
++
++/* Set width/height alignment of the surface directly and calculate stride/size. This is only for dri backend now. Please be careful before use. */
++gceSTATUS
++gcoSURF_SetAlignment(
++ IN gcoSURF Surface,
++ IN gctUINT Width,
++ IN gctUINT Height
++ );
++
++/* Increase reference count of the surface. */
++gceSTATUS
++gcoSURF_ReferenceSurface(
++ IN gcoSURF Surface
++ );
++
++/* Get surface reference count. */
++gceSTATUS
++gcoSURF_QueryReferenceCount(
++ IN gcoSURF Surface,
++ OUT gctINT32 * ReferenceCount
++ );
++
++/* Set surface orientation. */
++gceSTATUS
++gcoSURF_SetOrientation(
++ IN gcoSURF Surface,
++ IN gceORIENTATION Orientation
++ );
++
++/* Query surface orientation. */
++gceSTATUS
++gcoSURF_QueryOrientation(
++ IN gcoSURF Surface,
++ OUT gceORIENTATION * Orientation
++ );
++
++gceSTATUS
++gcoSURF_SetOffset(
++ IN gcoSURF Surface,
++ IN gctUINT Offset
++ );
++
++gceSTATUS
++gcoSURF_GetOffset(
++ IN gcoSURF Surface,
++ OUT gctUINT *Offset
++ );
++
++gceSTATUS
++gcoSURF_NODE_Cache(
++ IN gcsSURF_NODE_PTR Node,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes,
++ IN gceCACHEOPERATION Operation
++ );
++
++/* Perform CPU cache operation on surface */
++gceSTATUS
++gcoSURF_CPUCacheOperation(
++ IN gcoSURF Surface,
++ IN gceCACHEOPERATION Operation
++ );
++
++
++gceSTATUS
++gcoSURF_SetLinearResolveAddress(
++ IN gcoSURF Surface,
++ IN gctUINT32 Address,
++ IN gctPOINTER Memory
++ );
++
++ gceSTATUS
++ gcoSURF_Swap(IN gcoSURF Surface1, IN gcoSURF Surface2);
++
++/******************************************************************************\
++********************************* gcoDUMP Object ********************************
++\******************************************************************************/
++
++/* Construct a new gcoDUMP object. */
++gceSTATUS
++gcoDUMP_Construct(
++ IN gcoOS Os,
++ IN gcoHAL Hal,
++ OUT gcoDUMP * Dump
++ );
++
++/* Destroy a gcoDUMP object. */
++gceSTATUS
++gcoDUMP_Destroy(
++ IN gcoDUMP Dump
++ );
++
++/* Enable/disable dumping. */
++gceSTATUS
++gcoDUMP_Control(
++ IN gcoDUMP Dump,
++ IN gctSTRING FileName
++ );
++
++gceSTATUS
++gcoDUMP_IsEnabled(
++ IN gcoDUMP Dump,
++ OUT gctBOOL * Enabled
++ );
++
++/* Add surface. */
++gceSTATUS
++gcoDUMP_AddSurface(
++ IN gcoDUMP Dump,
++ IN gctINT32 Width,
++ IN gctINT32 Height,
++ IN gceSURF_FORMAT PixelFormat,
++ IN gctUINT32 Address,
++ IN gctSIZE_T ByteCount
++ );
++
++/* Mark the beginning of a frame. */
++gceSTATUS
++gcoDUMP_FrameBegin(
++ IN gcoDUMP Dump
++ );
++
++/* Mark the end of a frame. */
++gceSTATUS
++gcoDUMP_FrameEnd(
++ IN gcoDUMP Dump
++ );
++
++/* Dump data. */
++gceSTATUS
++gcoDUMP_DumpData(
++ IN gcoDUMP Dump,
++ IN gceDUMP_TAG Type,
++ IN gctUINT32 Address,
++ IN gctSIZE_T ByteCount,
++ IN gctCONST_POINTER Data
++ );
++
++/* Delete an address. */
++gceSTATUS
++gcoDUMP_Delete(
++ IN gcoDUMP Dump,
++ IN gctUINT32 Address
++ );
++
++/* Enable dump or not. */
++gceSTATUS
++gcoDUMP_SetDumpFlag(
++ IN gctBOOL DumpState
++ );
++
++/******************************************************************************\
++******************************* gcsRECT Structure ******************************
++\******************************************************************************/
++
++/* Initialize rectangle structure. */
++gceSTATUS
++gcsRECT_Set(
++ OUT gcsRECT_PTR Rect,
++ IN gctINT32 Left,
++ IN gctINT32 Top,
++ IN gctINT32 Right,
++ IN gctINT32 Bottom
++ );
++
++/* Return the width of the rectangle. */
++gceSTATUS
++gcsRECT_Width(
++ IN gcsRECT_PTR Rect,
++ OUT gctINT32 * Width
++ );
++
++/* Return the height of the rectangle. */
++gceSTATUS
++gcsRECT_Height(
++ IN gcsRECT_PTR Rect,
++ OUT gctINT32 * Height
++ );
++
++/* Ensure that top left corner is to the left and above the right bottom. */
++gceSTATUS
++gcsRECT_Normalize(
++ IN OUT gcsRECT_PTR Rect
++ );
++
++/* Compare two rectangles. */
++gceSTATUS
++gcsRECT_IsEqual(
++ IN gcsRECT_PTR Rect1,
++ IN gcsRECT_PTR Rect2,
++ OUT gctBOOL * Equal
++ );
++
++/* Compare the sizes of two rectangles. */
++gceSTATUS
++gcsRECT_IsOfEqualSize(
++ IN gcsRECT_PTR Rect1,
++ IN gcsRECT_PTR Rect2,
++ OUT gctBOOL * EqualSize
++ );
++
++gceSTATUS
++gcsRECT_RelativeRotation(
++ IN gceSURF_ROTATION Orientation,
++ IN OUT gceSURF_ROTATION *Relation);
++
++gceSTATUS
++
++gcsRECT_Rotate(
++
++ IN OUT gcsRECT_PTR Rect,
++
++ IN gceSURF_ROTATION Rotation,
++
++ IN gceSURF_ROTATION toRotation,
++
++ IN gctINT32 SurfaceWidth,
++
++ IN gctINT32 SurfaceHeight
++
++ );
++
++/******************************************************************************\
++**************************** gcsBOUNDARY Structure *****************************
++\******************************************************************************/
++
++typedef struct _gcsBOUNDARY
++{
++ gctINT x;
++ gctINT y;
++ gctINT width;
++ gctINT height;
++}
++gcsBOUNDARY;
++
++/******************************************************************************\
++********************************* gcoHEAP Object ********************************
++\******************************************************************************/
++
++typedef struct _gcoHEAP * gcoHEAP;
++
++/* Construct a new gcoHEAP object. */
++gceSTATUS
++gcoHEAP_Construct(
++ IN gcoOS Os,
++ IN gctSIZE_T AllocationSize,
++ OUT gcoHEAP * Heap
++ );
++
++/* Destroy an gcoHEAP object. */
++gceSTATUS
++gcoHEAP_Destroy(
++ IN gcoHEAP Heap
++ );
++
++/* Allocate memory. */
++gceSTATUS
++gcoHEAP_Allocate(
++ IN gcoHEAP Heap,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Node
++ );
++
++gceSTATUS
++gcoHEAP_GetMemorySize(
++ IN gcoHEAP Heap,
++ IN gctPOINTER Memory,
++ OUT gctSIZE_T_PTR MemorySize
++ );
++
++/* Free memory. */
++gceSTATUS
++gcoHEAP_Free(
++ IN gcoHEAP Heap,
++ IN gctPOINTER Node
++ );
++
++#if (VIVANTE_PROFILER || gcdDEBUG)
++/* Profile the heap. */
++gceSTATUS
++gcoHEAP_ProfileStart(
++ IN gcoHEAP Heap
++ );
++
++gceSTATUS
++gcoHEAP_ProfileEnd(
++ IN gcoHEAP Heap,
++ IN gctCONST_STRING Title
++ );
++#endif
++
++
++/******************************************************************************\
++******************************* Debugging Macros *******************************
++\******************************************************************************/
++
++void
++gcoOS_SetDebugLevel(
++ IN gctUINT32 Level
++ );
++
++void
++gcoOS_GetDebugLevel(
++ OUT gctUINT32_PTR DebugLevel
++ );
++
++void
++gcoOS_SetDebugZone(
++ IN gctUINT32 Zone
++ );
++
++void
++gcoOS_GetDebugZone(
++ IN gctUINT32 Zone,
++ OUT gctUINT32_PTR DebugZone
++ );
++
++void
++gcoOS_SetDebugLevelZone(
++ IN gctUINT32 Level,
++ IN gctUINT32 Zone
++ );
++
++void
++gcoOS_SetDebugZones(
++ IN gctUINT32 Zones,
++ IN gctBOOL Enable
++ );
++
++void
++gcoOS_SetDebugFile(
++ IN gctCONST_STRING FileName
++ );
++
++gctFILE
++gcoOS_ReplaceDebugFile(
++ IN gctFILE fp
++ );
++
++/*******************************************************************************
++**
++** gcmFATAL
++**
++** Print a message to the debugger and execute a break point.
++**
++** ARGUMENTS:
++**
++** message Message.
++** ... Optional arguments.
++*/
++
++void
++gckOS_DebugFatal(
++ IN gctCONST_STRING Message,
++ ...
++ );
++
++void
++gcoOS_DebugFatal(
++ IN gctCONST_STRING Message,
++ ...
++ );
++
++#if gcmIS_DEBUG(gcdDEBUG_FATAL)
++# define gcmFATAL gcoOS_DebugFatal
++# define gcmkFATAL gckOS_DebugFatal
++#elif gcdHAS_ELLIPSES
++# define gcmFATAL(...)
++# define gcmkFATAL(...)
++#else
++ gcmINLINE static void
++ __dummy_fatal(
++ IN gctCONST_STRING Message,
++ ...
++ )
++ {
++ }
++# define gcmFATAL __dummy_fatal
++# define gcmkFATAL __dummy_fatal
++#endif
++
++#define gcmENUM2TEXT(e) case e: return #e
++
++/*******************************************************************************
++**
++** gcmTRACE
++**
++** Print a message to the debugfer if the correct level has been set. In
++** retail mode this macro does nothing.
++**
++** ARGUMENTS:
++**
++** level Level of message.
++** message Message.
++** ... Optional arguments.
++*/
++#define gcvLEVEL_NONE -1
++#define gcvLEVEL_ERROR 0
++#define gcvLEVEL_WARNING 1
++#define gcvLEVEL_INFO 2
++#define gcvLEVEL_VERBOSE 3
++
++void
++gckOS_DebugTrace(
++ IN gctUINT32 Level,
++ IN gctCONST_STRING Message,
++ ...
++ );
++
++void
++gckOS_DebugTraceN(
++ IN gctUINT32 Level,
++ IN gctUINT ArgumentSize,
++ IN gctCONST_STRING Message,
++ ...
++ );
++
++void
++gcoOS_DebugTrace(
++ IN gctUINT32 Level,
++ IN gctCONST_STRING Message,
++ ...
++ );
++
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++# define gcmTRACE gcoOS_DebugTrace
++# define gcmkTRACE gckOS_DebugTrace
++# define gcmkTRACE_N gckOS_DebugTraceN
++#elif gcdHAS_ELLIPSES
++# define gcmTRACE(...)
++# define gcmkTRACE(...)
++# define gcmkTRACE_N(...)
++#else
++ gcmINLINE static void
++ __dummy_trace(
++ IN gctUINT32 Level,
++ IN gctCONST_STRING Message,
++ ...
++ )
++ {
++ }
++
++ gcmINLINE static void
++ __dummy_trace_n(
++ IN gctUINT32 Level,
++ IN gctUINT ArgumentSize,
++ IN gctCONST_STRING Message,
++ ...
++ )
++ {
++ }
++
++# define gcmTRACE __dummy_trace
++# define gcmkTRACE __dummy_trace
++# define gcmkTRACE_N __dummy_trace_n
++#endif
++
++/* Zones common for kernel and user. */
++#define gcvZONE_OS (1 << 0)
++#define gcvZONE_HARDWARE (1 << 1)
++#define gcvZONE_HEAP (1 << 2)
++#define gcvZONE_SIGNAL (1 << 27)
++
++/* Kernel zones. */
++#define gcvZONE_KERNEL (1 << 3)
++#define gcvZONE_VIDMEM (1 << 4)
++#define gcvZONE_COMMAND (1 << 5)
++#define gcvZONE_DRIVER (1 << 6)
++#define gcvZONE_CMODEL (1 << 7)
++#define gcvZONE_MMU (1 << 8)
++#define gcvZONE_EVENT (1 << 9)
++#define gcvZONE_DEVICE (1 << 10)
++#define gcvZONE_DATABASE (1 << 11)
++#define gcvZONE_INTERRUPT (1 << 12)
++#define gcvZONE_POWER (1 << 13)
++
++/* User zones. */
++#define gcvZONE_HAL (1 << 3)
++#define gcvZONE_BUFFER (1 << 4)
++#define gcvZONE_CONTEXT (1 << 5)
++#define gcvZONE_SURFACE (1 << 6)
++#define gcvZONE_INDEX (1 << 7)
++#define gcvZONE_STREAM (1 << 8)
++#define gcvZONE_TEXTURE (1 << 9)
++#define gcvZONE_2D (1 << 10)
++#define gcvZONE_3D (1 << 11)
++#define gcvZONE_COMPILER (1 << 12)
++#define gcvZONE_MEMORY (1 << 13)
++#define gcvZONE_STATE (1 << 14)
++#define gcvZONE_AUX (1 << 15)
++#define gcvZONE_VERTEX (1 << 16)
++#define gcvZONE_CL (1 << 17)
++#define gcvZONE_COMPOSITION (1 << 17)
++#define gcvZONE_VG (1 << 18)
++#define gcvZONE_IMAGE (1 << 19)
++#define gcvZONE_UTILITY (1 << 20)
++#define gcvZONE_PARAMETERS (1 << 21)
++
++/* API definitions. */
++#define gcvZONE_API_HAL (1 << 28)
++#define gcvZONE_API_EGL (2 << 28)
++#define gcvZONE_API_ES11 (3 << 28)
++#define gcvZONE_API_ES20 (4 << 28)
++#define gcvZONE_API_VG11 (5 << 28)
++#define gcvZONE_API_GL (6 << 28)
++#define gcvZONE_API_DFB (7 << 28)
++#define gcvZONE_API_GDI (8 << 28)
++#define gcvZONE_API_D3D (9 << 28)
++#define gcvZONE_API_ES30 (10 << 28)
++
++
++#define gcmZONE_GET_API(zone) ((zone) >> 28)
++/*Set gcdZONE_MASE like 0x0 | gcvZONE_API_EGL
++will enable print EGL module debug info*/
++#define gcdZONE_MASK 0x0FFFFFFF
++
++/* Handy zones. */
++#define gcvZONE_NONE 0
++#define gcvZONE_ALL 0x0FFFFFFF
++
++/*Dump API depth set 1 for API, 2 for API and API behavior*/
++#define gcvDUMP_API_DEPTH 1
++
++/*******************************************************************************
++**
++** gcmTRACE_ZONE
++**
++** Print a message to the debugger if the correct level and zone has been
++** set. In retail mode this macro does nothing.
++**
++** ARGUMENTS:
++**
++** Level Level of message.
++** Zone Zone of message.
++** Message Message.
++** ... Optional arguments.
++*/
++
++void
++gckOS_DebugTraceZone(
++ IN gctUINT32 Level,
++ IN gctUINT32 Zone,
++ IN gctCONST_STRING Message,
++ ...
++ );
++
++void
++gckOS_DebugTraceZoneN(
++ IN gctUINT32 Level,
++ IN gctUINT32 Zone,
++ IN gctUINT ArgumentSize,
++ IN gctCONST_STRING Message,
++ ...
++ );
++
++void
++gcoOS_DebugTraceZone(
++ IN gctUINT32 Level,
++ IN gctUINT32 Zone,
++ IN gctCONST_STRING Message,
++ ...
++ );
++
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++# define gcmTRACE_ZONE gcoOS_DebugTraceZone
++# define gcmkTRACE_ZONE gckOS_DebugTraceZone
++# define gcmkTRACE_ZONE_N gckOS_DebugTraceZoneN
++#elif gcdHAS_ELLIPSES
++# define gcmTRACE_ZONE(...)
++# define gcmkTRACE_ZONE(...)
++# define gcmkTRACE_ZONE_N(...)
++#else
++ gcmINLINE static void
++ __dummy_trace_zone(
++ IN gctUINT32 Level,
++ IN gctUINT32 Zone,
++ IN gctCONST_STRING Message,
++ ...
++ )
++ {
++ }
++
++ gcmINLINE static void
++ __dummy_trace_zone_n(
++ IN gctUINT32 Level,
++ IN gctUINT32 Zone,
++ IN gctUINT ArgumentSize,
++ IN gctCONST_STRING Message,
++ ...
++ )
++ {
++ }
++
++# define gcmTRACE_ZONE __dummy_trace_zone
++# define gcmkTRACE_ZONE __dummy_trace_zone
++# define gcmkTRACE_ZONE_N __dummy_trace_zone_n
++#endif
++
++/*******************************************************************************
++**
++** gcmDEBUG_ONLY
++**
++** Execute a statement or function only in DEBUG mode.
++**
++** ARGUMENTS:
++**
++** f Statement or function to execute.
++*/
++#if gcmIS_DEBUG(gcdDEBUG_CODE)
++# define gcmDEBUG_ONLY(f) f
++#else
++# define gcmDEBUG_ONLY(f)
++#endif
++
++/*******************************************************************************
++**
++** gcmSTACK_PUSH
++** gcmSTACK_POP
++** gcmSTACK_DUMP
++**
++** Push or pop a function with entry arguments on the trace stack.
++**
++** ARGUMENTS:
++**
++** Function Name of function.
++** Line Line number.
++** Text Optional text.
++** ... Optional arguments for text.
++*/
++#if gcmIS_DEBUG(gcdDEBUG_STACK)
++ void
++ gcoOS_StackPush(
++ IN gctCONST_STRING Function,
++ IN gctINT Line,
++ IN gctCONST_STRING Text,
++ ...
++ );
++ void
++ gcoOS_StackPop(
++ IN gctCONST_STRING Function
++ );
++ void
++ gcoOS_StackDump(
++ void
++ );
++# define gcmSTACK_PUSH gcoOS_StackPush
++# define gcmSTACK_POP gcoOS_StackPop
++# define gcmSTACK_DUMP gcoOS_StackDump
++#elif gcdHAS_ELLIPSES
++# define gcmSTACK_PUSH(...) do { } while (0)
++# define gcmSTACK_POP(Function) do { } while (0)
++# define gcmSTACK_DUMP() do { } while (0)
++#else
++ gcmINLINE static void
++ __dummy_stack_push(
++ IN gctCONST_STRING Function,
++ IN gctINT Line,
++ IN gctCONST_STRING Text, ...
++ )
++ {
++ }
++# define gcmSTACK_PUSH __dummy_stack_push
++# define gcmSTACK_POP(Function) do { } while (0)
++# define gcmSTACK_DUMP() do { } while (0)
++#endif
++
++/******************************************************************************\
++******************************** Logging Macros ********************************
++\******************************************************************************/
++
++#define gcdHEADER_LEVEL gcvLEVEL_VERBOSE
++
++
++#if gcdENABLE_PROFILING
++void
++gcoOS_ProfileDB(
++ IN gctCONST_STRING Function,
++ IN OUT gctBOOL_PTR Initialized
++ );
++
++#define gcmHEADER() \
++ static gctBOOL __profile__initialized__ = gcvFALSE; \
++ gcmSTACK_PUSH(__FUNCTION__, __LINE__, gcvNULL, gcvNULL); \
++ gcoOS_ProfileDB(__FUNCTION__, &__profile__initialized__)
++#define gcmHEADER_ARG(...) \
++ static gctBOOL __profile__initialized__ = gcvFALSE; \
++ gcmSTACK_PUSH(__FUNCTION__, __LINE__, Text, __VA_ARGS__); \
++ gcoOS_ProfileDB(__FUNCTION__, &__profile__initialized__)
++#define gcmFOOTER() \
++ gcmSTACK_POP(__FUNCTION__); \
++ gcoOS_ProfileDB(__FUNCTION__, gcvNULL)
++#define gcmFOOTER_NO() \
++ gcmSTACK_POP(__FUNCTION__); \
++ gcoOS_ProfileDB(__FUNCTION__, gcvNULL)
++#define gcmFOOTER_ARG(...) \
++ gcmSTACK_POP(__FUNCTION__); \
++ gcoOS_ProfileDB(__FUNCTION__, gcvNULL)
++#define gcmFOOTER_KILL() \
++ gcmSTACK_POP(__FUNCTION__); \
++ gcoOS_ProfileDB(gcvNULL, gcvNULL)
++
++#else /* gcdENABLE_PROFILING */
++
++#if gcdHAS_ELLIPSES
++#define gcmHEADER() \
++ gctINT8 __user__ = 1; \
++ gctINT8_PTR __user_ptr__ = &__user__; \
++ gcmSTACK_PUSH(__FUNCTION__, __LINE__, gcvNULL, gcvNULL); \
++ gcmTRACE_ZONE(gcdHEADER_LEVEL, _GC_OBJ_ZONE, \
++ "++%s(%d)", __FUNCTION__, __LINE__)
++#else
++ gcmINLINE static void
++ __dummy_header(void)
++ {
++ }
++# define gcmHEADER __dummy_header
++#endif
++
++#if gcdHAS_ELLIPSES
++# define gcmHEADER_ARG(Text, ...) \
++ gctINT8 __user__ = 1; \
++ gctINT8_PTR __user_ptr__ = &__user__; \
++ gcmSTACK_PUSH(__FUNCTION__, __LINE__, Text, __VA_ARGS__); \
++ gcmTRACE_ZONE(gcdHEADER_LEVEL, _GC_OBJ_ZONE, \
++ "++%s(%d): " Text, __FUNCTION__, __LINE__, __VA_ARGS__)
++#else
++ gcmINLINE static void
++ __dummy_header_arg(
++ IN gctCONST_STRING Text,
++ ...
++ )
++ {
++ }
++# define gcmHEADER_ARG __dummy_header_arg
++#endif
++
++#if gcdHAS_ELLIPSES
++# define gcmFOOTER() \
++ gcmSTACK_POP(__FUNCTION__); \
++ gcmPROFILE_ONLY(gcmTRACE_ZONE(gcdHEADER_LEVEL, _GC_OBJ_ZONE, \
++ "--%s(%d) [%llu,%llu]: status=%d(%s)", \
++ __FUNCTION__, __LINE__, \
++ __ticks__, __total__, \
++ status, gcoOS_DebugStatus2Name(status))); \
++ gcmPROFILE_ELSE(gcmTRACE_ZONE(gcdHEADER_LEVEL, _GC_OBJ_ZONE, \
++ "--%s(%d): status=%d(%s)", \
++ __FUNCTION__, __LINE__, \
++ status, gcoOS_DebugStatus2Name(status))); \
++ *__user_ptr__ -= 1
++#else
++ gcmINLINE static void
++ __dummy_footer(void)
++ {
++ }
++# define gcmFOOTER __dummy_footer
++#endif
++
++#if gcdHAS_ELLIPSES
++#define gcmFOOTER_NO() \
++ gcmSTACK_POP(__FUNCTION__); \
++ gcmTRACE_ZONE(gcdHEADER_LEVEL, _GC_OBJ_ZONE, \
++ "--%s(%d)", __FUNCTION__, __LINE__); \
++ *__user_ptr__ -= 1
++#else
++ gcmINLINE static void
++ __dummy_footer_no(void)
++ {
++ }
++# define gcmFOOTER_NO __dummy_footer_no
++#endif
++
++#if gcdHAS_ELLIPSES
++#define gcmFOOTER_KILL() \
++ gcmSTACK_POP(__FUNCTION__); \
++ gcmTRACE_ZONE(gcdHEADER_LEVEL, _GC_OBJ_ZONE, \
++ "--%s(%d)", __FUNCTION__, __LINE__); \
++ *__user_ptr__ -= 1
++#else
++ gcmINLINE static void
++ __dummy_footer_kill(void)
++ {
++ }
++# define gcmFOOTER_KILL __dummy_footer_kill
++#endif
++
++#if gcdHAS_ELLIPSES
++# define gcmFOOTER_ARG(Text, ...) \
++ gcmSTACK_POP(__FUNCTION__); \
++ gcmTRACE_ZONE(gcdHEADER_LEVEL, _GC_OBJ_ZONE, \
++ "--%s(%d): " Text, __FUNCTION__, __LINE__, __VA_ARGS__); \
++ *__user_ptr__ -= 1
++#else
++ gcmINLINE static void
++ __dummy_footer_arg(
++ IN gctCONST_STRING Text,
++ ...
++ )
++ {
++ }
++# define gcmFOOTER_ARG __dummy_footer_arg
++#endif
++
++#endif /* gcdENABLE_PROFILING */
++
++#if gcdHAS_ELLIPSES
++#define gcmkHEADER() \
++ gctINT8 __kernel__ = 1; \
++ gctINT8_PTR __kernel_ptr__ = &__kernel__; \
++ gcmkTRACE_ZONE(gcdHEADER_LEVEL, _GC_OBJ_ZONE, \
++ "++%s(%d)", __FUNCTION__, __LINE__)
++#else
++ gcmINLINE static void
++ __dummy_kheader(void)
++ {
++ }
++# define gcmkHEADER __dummy_kheader
++#endif
++
++#if gcdHAS_ELLIPSES
++# define gcmkHEADER_ARG(Text, ...) \
++ gctINT8 __kernel__ = 1; \
++ gctINT8_PTR __kernel_ptr__ = &__kernel__; \
++ gcmkTRACE_ZONE(gcdHEADER_LEVEL, _GC_OBJ_ZONE, \
++ "++%s(%d): " Text, __FUNCTION__, __LINE__, __VA_ARGS__)
++#else
++ gcmINLINE static void
++ __dummy_kheader_arg(
++ IN gctCONST_STRING Text,
++ ...
++ )
++ {
++ }
++# define gcmkHEADER_ARG __dummy_kheader_arg
++#endif
++
++#if gcdHAS_ELLIPSES
++#define gcmkFOOTER() \
++ gcmkTRACE_ZONE(gcdHEADER_LEVEL, _GC_OBJ_ZONE, \
++ "--%s(%d): status=%d(%s)", \
++ __FUNCTION__, __LINE__, status, gckOS_DebugStatus2Name(status)); \
++ *__kernel_ptr__ -= 1
++#else
++ gcmINLINE static void
++ __dummy_kfooter(void)
++ {
++ }
++# define gcmkFOOTER __dummy_kfooter
++#endif
++
++#if gcdHAS_ELLIPSES
++#define gcmkFOOTER_NO() \
++ gcmkTRACE_ZONE(gcdHEADER_LEVEL, _GC_OBJ_ZONE, \
++ "--%s(%d)", __FUNCTION__, __LINE__); \
++ *__kernel_ptr__ -= 1
++#else
++ gcmINLINE static void
++ __dummy_kfooter_no(void)
++ {
++ }
++# define gcmkFOOTER_NO __dummy_kfooter_no
++#endif
++
++#if gcdHAS_ELLIPSES
++# define gcmkFOOTER_ARG(Text, ...) \
++ gcmkTRACE_ZONE(gcdHEADER_LEVEL, _GC_OBJ_ZONE, \
++ "--%s(%d): " Text, \
++ __FUNCTION__, __LINE__, __VA_ARGS__); \
++ *__kernel_ptr__ -= 1
++#else
++ gcmINLINE static void
++ __dummy_kfooter_arg(
++ IN gctCONST_STRING Text,
++ ...
++ )
++ {
++ }
++# define gcmkFOOTER_ARG __dummy_kfooter_arg
++#endif
++
++#define gcmOPT_VALUE(ptr) (((ptr) == gcvNULL) ? 0 : *(ptr))
++#define gcmOPT_VALUE_INDEX(ptr, index) (((ptr) == gcvNULL) ? 0 : ptr[index])
++#define gcmOPT_POINTER(ptr) (((ptr) == gcvNULL) ? gcvNULL : *(ptr))
++#define gcmOPT_STRING(ptr) (((ptr) == gcvNULL) ? "(nil)" : (ptr))
++
++void
++gckOS_Print(
++ IN gctCONST_STRING Message,
++ ...
++ );
++
++void
++gckOS_PrintN(
++ IN gctUINT ArgumentSize,
++ IN gctCONST_STRING Message,
++ ...
++ );
++
++void
++gckOS_CopyPrint(
++ IN gctCONST_STRING Message,
++ ...
++ );
++
++void
++gcoOS_Print(
++ IN gctCONST_STRING Message,
++ ...
++ );
++
++#define gcmPRINT gcoOS_Print
++#define gcmkPRINT gckOS_Print
++#define gcmkPRINT_N gckOS_PrintN
++
++#if gcdPRINT_VERSION
++# define gcmPRINT_VERSION() do { \
++ _gcmPRINT_VERSION(gcm); \
++ gcmSTACK_DUMP(); \
++ } while (0)
++# define gcmkPRINT_VERSION() _gcmPRINT_VERSION(gcmk)
++# define _gcmPRINT_VERSION(prefix) \
++ prefix##TRACE(gcvLEVEL_ERROR, \
++ "Vivante HAL version %d.%d.%d build %d %s %s", \
++ gcvVERSION_MAJOR, gcvVERSION_MINOR, gcvVERSION_PATCH, \
++ gcvVERSION_BUILD, gcvVERSION_DATE, gcvVERSION_TIME )
++#else
++# define gcmPRINT_VERSION() do { gcmSTACK_DUMP(); } while (gcvFALSE)
++# define gcmkPRINT_VERSION() do { } while (gcvFALSE)
++#endif
++
++typedef enum _gceDUMP_BUFFER
++{
++ gceDUMP_BUFFER_CONTEXT,
++ gceDUMP_BUFFER_USER,
++ gceDUMP_BUFFER_KERNEL,
++ gceDUMP_BUFFER_LINK,
++ gceDUMP_BUFFER_WAITLINK,
++ gceDUMP_BUFFER_FROM_USER,
++}
++gceDUMP_BUFFER;
++
++void
++gckOS_DumpBuffer(
++ IN gckOS Os,
++ IN gctPOINTER Buffer,
++ IN gctUINT Size,
++ IN gceDUMP_BUFFER Type,
++ IN gctBOOL CopyMessage
++ );
++
++#define gcmkDUMPBUFFER gckOS_DumpBuffer
++
++#if gcdDUMP_COMMAND
++# define gcmkDUMPCOMMAND(Os, Buffer, Size, Type, CopyMessage) \
++ gcmkDUMPBUFFER(Os, Buffer, Size, Type, CopyMessage)
++#else
++# define gcmkDUMPCOMMAND(Os, Buffer, Size, Type, CopyMessage)
++#endif
++
++#if gcmIS_DEBUG(gcdDEBUG_CODE)
++
++void
++gckOS_DebugFlush(
++ gctCONST_STRING CallerName,
++ gctUINT LineNumber,
++ gctUINT32 DmaAddress
++ );
++
++# define gcmkDEBUGFLUSH(DmaAddress) \
++ gckOS_DebugFlush(__FUNCTION__, __LINE__, DmaAddress)
++#else
++# define gcmkDEBUGFLUSH(DmaAddress)
++#endif
++
++/*******************************************************************************
++**
++** gcmDUMP_FRAMERATE
++**
++** Print average frame rate
++**
++*/
++#if gcdDUMP_FRAMERATE
++ gceSTATUS
++ gcfDumpFrameRate(
++ void
++ );
++# define gcmDUMP_FRAMERATE gcfDumpFrameRate
++#elif gcdHAS_ELLIPSES
++# define gcmDUMP_FRAMERATE(...)
++#else
++ gcmINLINE static void
++ __dummy_dump_frame_rate(
++ void
++ )
++ {
++ }
++# define gcmDUMP_FRAMERATE __dummy_dump_frame_rate
++#endif
++
++
++/*******************************************************************************
++**
++** gcmDUMP
++**
++** Print a dump message.
++**
++** ARGUMENTS:
++**
++** gctSTRING Message.
++**
++** ... Optional arguments.
++*/
++#if gcdDUMP
++ gceSTATUS
++ gcfDump(
++ IN gcoOS Os,
++ IN gctCONST_STRING String,
++ ...
++ );
++# define gcmDUMP gcfDump
++#elif gcdHAS_ELLIPSES
++# define gcmDUMP(...)
++#else
++ gcmINLINE static void
++ __dummy_dump(
++ IN gcoOS Os,
++ IN gctCONST_STRING Message,
++ ...
++ )
++ {
++ }
++# define gcmDUMP __dummy_dump
++#endif
++
++/*******************************************************************************
++**
++** gcmDUMP_DATA
++**
++** Add data to the dump.
++**
++** ARGUMENTS:
++**
++** gctSTRING Tag
++** Tag for dump.
++**
++** gctPOINTER Logical
++** Logical address of buffer.
++**
++** gctSIZE_T Bytes
++** Number of bytes.
++*/
++
++#if gcdDUMP || gcdDUMP_COMMAND
++ gceSTATUS
++ gcfDumpData(
++ IN gcoOS Os,
++ IN gctSTRING Tag,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes
++ );
++# define gcmDUMP_DATA gcfDumpData
++#elif gcdHAS_ELLIPSES
++# define gcmDUMP_DATA(...)
++#else
++ gcmINLINE static void
++ __dummy_dump_data(
++ IN gcoOS Os,
++ IN gctSTRING Tag,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes
++ )
++ {
++ }
++# define gcmDUMP_DATA __dummy_dump_data
++#endif
++
++/*******************************************************************************
++**
++** gcmDUMP_BUFFER
++**
++** Print a buffer to the dump.
++**
++** ARGUMENTS:
++**
++** gctSTRING Tag
++** Tag for dump.
++**
++** gctUINT32 Physical
++** Physical address of buffer.
++**
++** gctPOINTER Logical
++** Logical address of buffer.
++**
++** gctUINT32 Offset
++** Offset into buffer.
++**
++** gctSIZE_T Bytes
++** Number of bytes.
++*/
++
++#if gcdDUMP || gcdDUMP_COMMAND
++gceSTATUS
++gcfDumpBuffer(
++ IN gcoOS Os,
++ IN gctSTRING Tag,
++ IN gctUINT32 Physical,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Offset,
++ IN gctSIZE_T Bytes
++ );
++# define gcmDUMP_BUFFER gcfDumpBuffer
++#elif gcdHAS_ELLIPSES
++# define gcmDUMP_BUFFER(...)
++#else
++ gcmINLINE static void
++ __dummy_dump_buffer(
++ IN gcoOS Os,
++ IN gctSTRING Tag,
++ IN gctUINT32 Physical,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Offset,
++ IN gctSIZE_T Bytes
++ )
++ {
++ }
++# define gcmDUMP_BUFFER __dummy_dump_buffer
++#endif
++
++/*******************************************************************************
++**
++** gcmDUMP_API
++**
++** Print a dump message for a high level API prefixed by the function name.
++**
++** ARGUMENTS:
++**
++** gctSTRING Message.
++**
++** ... Optional arguments.
++*/
++gceSTATUS gcfDumpApi(IN gctCONST_STRING String, ...);
++#if gcdDUMP_API
++# define gcmDUMP_API gcfDumpApi
++#elif gcdHAS_ELLIPSES
++# define gcmDUMP_API(...)
++#else
++ gcmINLINE static void
++ __dummy_dump_api(
++ IN gctCONST_STRING Message,
++ ...
++ )
++ {
++ }
++# define gcmDUMP_API __dummy_dump_api
++#endif
++
++/*******************************************************************************
++**
++** gcmDUMP_API_ARRAY
++**
++** Print an array of data.
++**
++** ARGUMENTS:
++**
++** gctUINT32_PTR Pointer to array.
++** gctUINT32 Size.
++*/
++gceSTATUS gcfDumpArray(IN gctCONST_POINTER Data, IN gctUINT32 Size);
++#if gcdDUMP_API
++# define gcmDUMP_API_ARRAY gcfDumpArray
++#elif gcdHAS_ELLIPSES
++# define gcmDUMP_API_ARRAY(...)
++#else
++ gcmINLINE static void
++ __dummy_dump_api_array(
++ IN gctCONST_POINTER Data,
++ IN gctUINT32 Size
++ )
++ {
++ }
++# define gcmDUMP_API_ARRAY __dummy_dump_api_array
++#endif
++
++/*******************************************************************************
++**
++** gcmDUMP_API_ARRAY_TOKEN
++**
++** Print an array of data terminated by a token.
++**
++** ARGUMENTS:
++**
++** gctUINT32_PTR Pointer to array.
++** gctUINT32 Termination.
++*/
++gceSTATUS gcfDumpArrayToken(IN gctCONST_POINTER Data, IN gctUINT32 Termination);
++#if gcdDUMP_API
++# define gcmDUMP_API_ARRAY_TOKEN gcfDumpArrayToken
++#elif gcdHAS_ELLIPSES
++# define gcmDUMP_API_ARRAY_TOKEN(...)
++#else
++ gcmINLINE static void
++ __dummy_dump_api_array_token(
++ IN gctCONST_POINTER Data,
++ IN gctUINT32 Termination
++ )
++ {
++ }
++# define gcmDUMP_API_ARRAY_TOKEN __dummy_dump_api_array_token
++#endif
++
++/*******************************************************************************
++**
++** gcmDUMP_API_DATA
++**
++** Print an array of bytes.
++**
++** ARGUMENTS:
++**
++** gctCONST_POINTER Pointer to array.
++** gctSIZE_T Size.
++*/
++gceSTATUS gcfDumpApiData(IN gctCONST_POINTER Data, IN gctSIZE_T Size);
++#if gcdDUMP_API
++# define gcmDUMP_API_DATA gcfDumpApiData
++#elif gcdHAS_ELLIPSES
++# define gcmDUMP_API_DATA(...)
++#else
++ gcmINLINE static void
++ __dummy_dump_api_data(
++ IN gctCONST_POINTER Data,
++ IN gctSIZE_T Size
++ )
++ {
++ }
++# define gcmDUMP_API_DATA __dummy_dump_api_data
++#endif
++
++/*******************************************************************************
++**
++** gcmTRACE_RELEASE
++**
++** Print a message to the shader debugger.
++**
++** ARGUMENTS:
++**
++** message Message.
++** ... Optional arguments.
++*/
++
++#define gcmTRACE_RELEASE gcoOS_DebugShaderTrace
++
++void
++gcoOS_DebugShaderTrace(
++ IN gctCONST_STRING Message,
++ ...
++ );
++
++void
++gcoOS_SetDebugShaderFiles(
++ IN gctCONST_STRING VSFileName,
++ IN gctCONST_STRING FSFileName
++ );
++
++void
++gcoOS_SetDebugShaderFileType(
++ IN gctUINT32 ShaderType
++ );
++
++void
++gcoOS_EnableDebugBuffer(
++ IN gctBOOL Enable
++ );
++
++/*******************************************************************************
++**
++** gcmBREAK
++**
++** Break into the debugger. In retail mode this macro does nothing.
++**
++** ARGUMENTS:
++**
++** None.
++*/
++
++void
++gcoOS_DebugBreak(
++ void
++ );
++
++void
++gckOS_DebugBreak(
++ void
++ );
++
++#if gcmIS_DEBUG(gcdDEBUG_BREAK)
++# define gcmBREAK gcoOS_DebugBreak
++# define gcmkBREAK gckOS_DebugBreak
++#else
++# define gcmBREAK()
++# define gcmkBREAK()
++#endif
++
++/*******************************************************************************
++**
++** gcmASSERT
++**
++** Evaluate an expression and break into the debugger if the expression
++** evaluates to false. In retail mode this macro does nothing.
++**
++** ARGUMENTS:
++**
++** exp Expression to evaluate.
++*/
++#if gcmIS_DEBUG(gcdDEBUG_ASSERT)
++# define _gcmASSERT(prefix, exp) \
++ do \
++ { \
++ if (!(exp)) \
++ { \
++ prefix##TRACE(gcvLEVEL_ERROR, \
++ #prefix "ASSERT at %s(%d)", \
++ __FUNCTION__, __LINE__); \
++ prefix##TRACE(gcvLEVEL_ERROR, \
++ "(%s)", #exp); \
++ prefix##BREAK(); \
++ } \
++ } \
++ while (gcvFALSE)
++# define gcmASSERT(exp) _gcmASSERT(gcm, exp)
++# define gcmkASSERT(exp) _gcmASSERT(gcmk, exp)
++#else
++# define gcmASSERT(exp)
++# define gcmkASSERT(exp)
++#endif
++
++/*******************************************************************************
++**
++** gcmVERIFY
++**
++** Verify if an expression returns true. If the expression does not
++** evaluates to true, an assertion will happen in debug mode.
++**
++** ARGUMENTS:
++**
++** exp Expression to evaluate.
++*/
++#if gcmIS_DEBUG(gcdDEBUG_ASSERT)
++# define gcmVERIFY(exp) gcmASSERT(exp)
++# define gcmkVERIFY(exp) gcmkASSERT(exp)
++#else
++# define gcmVERIFY(exp) exp
++# define gcmkVERIFY(exp) exp
++#endif
++
++/*******************************************************************************
++**
++** gcmVERIFY_OK
++**
++** Verify a fucntion returns gcvSTATUS_OK. If the function does not return
++** gcvSTATUS_OK, an assertion will happen in debug mode.
++**
++** ARGUMENTS:
++**
++** func Function to evaluate.
++*/
++
++void
++gcoOS_Verify(
++ IN gceSTATUS status
++ );
++
++void
++gckOS_Verify(
++ IN gceSTATUS status
++ );
++
++#if gcmIS_DEBUG(gcdDEBUG_ASSERT)
++# define gcmVERIFY_OK(func) \
++ do \
++ { \
++ gceSTATUS verifyStatus = func; \
++ gcoOS_Verify(verifyStatus); \
++ if (verifyStatus != gcvSTATUS_OK) \
++ { \
++ gcmTRACE( \
++ gcvLEVEL_ERROR, \
++ "gcmVERIFY_OK(%d): function returned %d", \
++ __LINE__, verifyStatus \
++ ); \
++ } \
++ gcmASSERT(verifyStatus == gcvSTATUS_OK); \
++ } \
++ while (gcvFALSE)
++# define gcmkVERIFY_OK(func) \
++ do \
++ { \
++ gceSTATUS verifyStatus = func; \
++ if (verifyStatus != gcvSTATUS_OK) \
++ { \
++ gcmkTRACE( \
++ gcvLEVEL_ERROR, \
++ "gcmkVERIFY_OK(%d): function returned %d", \
++ __LINE__, verifyStatus \
++ ); \
++ } \
++ gckOS_Verify(verifyStatus); \
++ gcmkASSERT(verifyStatus == gcvSTATUS_OK); \
++ } \
++ while (gcvFALSE)
++#else
++# define gcmVERIFY_OK(func) func
++# define gcmkVERIFY_OK(func) func
++#endif
++
++gctCONST_STRING
++gcoOS_DebugStatus2Name(
++ gceSTATUS status
++ );
++
++gctCONST_STRING
++gckOS_DebugStatus2Name(
++ gceSTATUS status
++ );
++
++/*******************************************************************************
++**
++** gcmERR_BREAK
++**
++** Executes a break statement on error.
++**
++** ASSUMPTIONS:
++**
++** 'status' variable of gceSTATUS type must be defined.
++**
++** ARGUMENTS:
++**
++** func Function to evaluate.
++*/
++#define _gcmERR_BREAK(prefix, func) \
++ status = func; \
++ if (gcmIS_ERROR(status)) \
++ { \
++ prefix##PRINT_VERSION(); \
++ prefix##TRACE(gcvLEVEL_ERROR, \
++ #prefix "ERR_BREAK: status=%d(%s) @ %s(%d)", \
++ status, gcoOS_DebugStatus2Name(status), __FUNCTION__, __LINE__); \
++ break; \
++ } \
++ do { } while (gcvFALSE)
++#define _gcmkERR_BREAK(prefix, func) \
++ status = func; \
++ if (gcmIS_ERROR(status)) \
++ { \
++ prefix##PRINT_VERSION(); \
++ prefix##TRACE(gcvLEVEL_ERROR, \
++ #prefix "ERR_BREAK: status=%d(%s) @ %s(%d)", \
++ status, gckOS_DebugStatus2Name(status), __FUNCTION__, __LINE__); \
++ break; \
++ } \
++ do { } while (gcvFALSE)
++#define gcmERR_BREAK(func) _gcmERR_BREAK(gcm, func)
++#define gcmkERR_BREAK(func) _gcmkERR_BREAK(gcmk, func)
++
++/*******************************************************************************
++**
++** gcmERR_RETURN
++**
++** Executes a return on error.
++**
++** ASSUMPTIONS:
++**
++** 'status' variable of gceSTATUS type must be defined.
++**
++** ARGUMENTS:
++**
++** func Function to evaluate.
++*/
++#define _gcmERR_RETURN(prefix, func) \
++ status = func; \
++ if (gcmIS_ERROR(status)) \
++ { \
++ prefix##PRINT_VERSION(); \
++ prefix##TRACE(gcvLEVEL_ERROR, \
++ #prefix "ERR_RETURN: status=%d(%s) @ %s(%d)", \
++ status, gcoOS_DebugStatus2Name(status), __FUNCTION__, __LINE__); \
++ prefix##FOOTER(); \
++ return status; \
++ } \
++ do { } while (gcvFALSE)
++#define _gcmkERR_RETURN(prefix, func) \
++ status = func; \
++ if (gcmIS_ERROR(status)) \
++ { \
++ prefix##PRINT_VERSION(); \
++ prefix##TRACE(gcvLEVEL_ERROR, \
++ #prefix "ERR_RETURN: status=%d(%s) @ %s(%d)", \
++ status, gckOS_DebugStatus2Name(status), __FUNCTION__, __LINE__); \
++ prefix##FOOTER(); \
++ return status; \
++ } \
++ do { } while (gcvFALSE)
++#define gcmERR_RETURN(func) _gcmERR_RETURN(gcm, func)
++#define gcmkERR_RETURN(func) _gcmkERR_RETURN(gcmk, func)
++
++
++/*******************************************************************************
++**
++** gcmONERROR
++**
++** Jump to the error handler in case there is an error.
++**
++** ASSUMPTIONS:
++**
++** 'status' variable of gceSTATUS type must be defined.
++**
++** ARGUMENTS:
++**
++** func Function to evaluate.
++*/
++#define _gcmONERROR(prefix, func) \
++ do \
++ { \
++ status = func; \
++ if (gcmIS_ERROR(status)) \
++ { \
++ prefix##PRINT_VERSION(); \
++ prefix##TRACE(gcvLEVEL_ERROR, \
++ #prefix "ONERROR: status=%d(%s) @ %s(%d)", \
++ status, gcoOS_DebugStatus2Name(status), __FUNCTION__, __LINE__); \
++ goto OnError; \
++ } \
++ } \
++ while (gcvFALSE)
++#define _gcmkONERROR(prefix, func) \
++ do \
++ { \
++ status = func; \
++ if (gcmIS_ERROR(status)) \
++ { \
++ prefix##PRINT_VERSION(); \
++ prefix##TRACE(gcvLEVEL_ERROR, \
++ #prefix "ONERROR: status=%d(%s) @ %s(%d)", \
++ status, gckOS_DebugStatus2Name(status), __FUNCTION__, __LINE__); \
++ goto OnError; \
++ } \
++ } \
++ while (gcvFALSE)
++#define gcmONERROR(func) _gcmONERROR(gcm, func)
++#define gcmkONERROR(func) _gcmkONERROR(gcmk, func)
++
++/*******************************************************************************
++**
++** gcmVERIFY_LOCK
++**
++** Verifies whether the surface is locked.
++**
++** ARGUMENTS:
++**
++** surfaceInfo Pointer to the surface iniformational structure.
++*/
++#define gcmVERIFY_LOCK(surfaceInfo) \
++ if (!surfaceInfo->node.valid) \
++ { \
++ gcmONERROR(gcvSTATUS_MEMORY_UNLOCKED); \
++ } \
++
++/*******************************************************************************
++**
++** gcmVERIFY_NODE_LOCK
++**
++** Verifies whether the surface node is locked.
++**
++** ARGUMENTS:
++**
++** surfaceInfo Pointer to the surface iniformational structure.
++*/
++#define gcmVERIFY_NODE_LOCK(surfaceNode) \
++ if (!(surfaceNode)->valid) \
++ { \
++ status = gcvSTATUS_MEMORY_UNLOCKED; \
++ break; \
++ } \
++ do { } while (gcvFALSE)
++
++/*******************************************************************************
++**
++** gcmBADOBJECT_BREAK
++**
++** Executes a break statement on bad object.
++**
++** ARGUMENTS:
++**
++** obj Object to test.
++** t Expected type of the object.
++*/
++#define gcmBADOBJECT_BREAK(obj, t) \
++ if ((obj == gcvNULL) \
++ || (((gcsOBJECT *)(obj))->type != t) \
++ ) \
++ { \
++ status = gcvSTATUS_INVALID_OBJECT; \
++ break; \
++ } \
++ do { } while (gcvFALSE)
++
++/*******************************************************************************
++**
++** gcmCHECK_STATUS
++**
++** Executes a break statement on error.
++**
++** ASSUMPTIONS:
++**
++** 'status' variable of gceSTATUS type must be defined.
++**
++** ARGUMENTS:
++**
++** func Function to evaluate.
++*/
++#define _gcmCHECK_STATUS(prefix, func) \
++ do \
++ { \
++ last = func; \
++ if (gcmIS_ERROR(last)) \
++ { \
++ prefix##TRACE(gcvLEVEL_ERROR, \
++ #prefix "CHECK_STATUS: status=%d(%s) @ %s(%d)", \
++ last, gcoOS_DebugStatus2Name(last), __FUNCTION__, __LINE__); \
++ status = last; \
++ } \
++ } \
++ while (gcvFALSE)
++#define _gcmkCHECK_STATUS(prefix, func) \
++ do \
++ { \
++ last = func; \
++ if (gcmIS_ERROR(last)) \
++ { \
++ prefix##TRACE(gcvLEVEL_ERROR, \
++ #prefix "CHECK_STATUS: status=%d(%s) @ %s(%d)", \
++ last, gckOS_DebugStatus2Name(last), __FUNCTION__, __LINE__); \
++ status = last; \
++ } \
++ } \
++ while (gcvFALSE)
++#define gcmCHECK_STATUS(func) _gcmCHECK_STATUS(gcm, func)
++#define gcmkCHECK_STATUS(func) _gcmkCHECK_STATUS(gcmk, func)
++
++/*******************************************************************************
++**
++** gcmVERIFY_ARGUMENT
++**
++** Assert if an argument does not apply to the specified expression. If
++** the argument evaluates to false, gcvSTATUS_INVALID_ARGUMENT will be
++** returned from the current function. In retail mode this macro does
++** nothing.
++**
++** ARGUMENTS:
++**
++** arg Argument to evaluate.
++*/
++# define _gcmVERIFY_ARGUMENT(prefix, arg) \
++ do \
++ { \
++ if (!(arg)) \
++ { \
++ prefix##TRACE(gcvLEVEL_ERROR, #prefix "VERIFY_ARGUMENT failed:"); \
++ prefix##ASSERT(arg); \
++ prefix##FOOTER_ARG("status=%d", gcvSTATUS_INVALID_ARGUMENT); \
++ return gcvSTATUS_INVALID_ARGUMENT; \
++ } \
++ } \
++ while (gcvFALSE)
++# define gcmVERIFY_ARGUMENT(arg) _gcmVERIFY_ARGUMENT(gcm, arg)
++# define gcmkVERIFY_ARGUMENT(arg) _gcmVERIFY_ARGUMENT(gcmk, arg)
++
++/*******************************************************************************
++**
++** gcmDEBUG_VERIFY_ARGUMENT
++**
++** Works just like gcmVERIFY_ARGUMENT, but is only valid in debug mode.
++** Use this to verify arguments inside non-public API functions.
++*/
++#if gcdDEBUG
++# define gcmDEBUG_VERIFY_ARGUMENT(arg) _gcmVERIFY_ARGUMENT(gcm, arg)
++# define gcmkDEBUG_VERIFY_ARGUMENT(arg) _gcmkVERIFY_ARGUMENT(gcm, arg)
++#else
++# define gcmDEBUG_VERIFY_ARGUMENT(arg)
++# define gcmkDEBUG_VERIFY_ARGUMENT(arg)
++#endif
++
++/*******************************************************************************
++**
++** gcmVERIFY_ARGUMENT_RETURN
++**
++** Assert if an argument does not apply to the specified expression. If
++** the argument evaluates to false, gcvSTATUS_INVALID_ARGUMENT will be
++** returned from the current function. In retail mode this macro does
++** nothing.
++**
++** ARGUMENTS:
++**
++** arg Argument to evaluate.
++*/
++# define _gcmVERIFY_ARGUMENT_RETURN(prefix, arg, value) \
++ do \
++ { \
++ if (!(arg)) \
++ { \
++ prefix##TRACE(gcvLEVEL_ERROR, \
++ #prefix "gcmVERIFY_ARGUMENT_RETURN failed:"); \
++ prefix##ASSERT(arg); \
++ prefix##FOOTER_ARG("value=%d", value); \
++ return value; \
++ } \
++ } \
++ while (gcvFALSE)
++# define gcmVERIFY_ARGUMENT_RETURN(arg, value) \
++ _gcmVERIFY_ARGUMENT_RETURN(gcm, arg, value)
++# define gcmkVERIFY_ARGUMENT_RETURN(arg, value) \
++ _gcmVERIFY_ARGUMENT_RETURN(gcmk, arg, value)
++
++#define MAX_LOOP_COUNT 0x7FFFFFFF
++
++/******************************************************************************\
++****************************** User Debug Option ******************************
++\******************************************************************************/
++
++/* User option. */
++typedef enum _gceDEBUG_MSG
++{
++ gcvDEBUG_MSG_NONE,
++ gcvDEBUG_MSG_ERROR,
++ gcvDEBUG_MSG_WARNING
++}
++gceDEBUG_MSG;
++
++typedef struct _gcsUSER_DEBUG_OPTION
++{
++ gceDEBUG_MSG debugMsg;
++}
++gcsUSER_DEBUG_OPTION;
++
++gcsUSER_DEBUG_OPTION *
++gcGetUserDebugOption(
++ void
++ );
++
++struct _gcoOS_SymbolsList
++{
++ gcePATCH_ID patchId;
++ const char * symList[10];
++};
++
++#if gcdHAS_ELLIPSES
++#define gcmUSER_DEBUG_MSG(level, ...) \
++ do \
++ { \
++ if (level <= gcGetUserDebugOption()->debugMsg) \
++ { \
++ gcoOS_Print(__VA_ARGS__); \
++ } \
++ } while (gcvFALSE)
++
++#define gcmUSER_DEBUG_ERROR_MSG(...) gcmUSER_DEBUG_MSG(gcvDEBUG_MSG_ERROR, "Error: " __VA_ARGS__)
++#define gcmUSER_DEBUG_WARNING_MSG(...) gcmUSER_DEBUG_MSG(gcvDEBUG_MSG_WARNING, "Warring: " __VA_ARGS__)
++#else
++#define gcmUSER_DEBUG_MSG
++#define gcmUSER_DEBUG_ERROR_MSG
++#define gcmUSER_DEBUG_WARNING_MSG
++#endif
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __gc_hal_base_h_ */
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_compiler.h linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_compiler.h
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_compiler.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_compiler.h 2015-07-27 23:13:06.210822785 +0200
+@@ -0,0 +1,4356 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++/*
++** Include file the defines the front- and back-end compilers, as well as the
++** objects they use.
++*/
++
++#ifndef __gc_hal_compiler_h_
++#define __gc_hal_compiler_h_
++
++#ifndef VIVANTE_NO_3D
++#include "gc_hal_types.h"
++#include "gc_hal_engine.h"
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++#ifndef GC_ENABLE_LOADTIME_OPT
++#define GC_ENABLE_LOADTIME_OPT 1
++#endif
++
++#define TEMP_OPT_CONSTANT_TEXLD_COORD 0
++
++#define TEMP_SHADER_PATCH 1
++
++#define TEMP_INLINE_ALL_EXPANSION 1
++/******************************* IR VERSION ******************/
++#define gcdSL_IR_VERSION gcmCC('\0','\0','\0','\1')
++
++/******************************************************************************\
++|******************************* SHADER LANGUAGE ******************************|
++\******************************************************************************/
++
++ /* allocator/deallocator function pointer */
++typedef gceSTATUS (*gctAllocatorFunc)(
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Memory
++ );
++
++typedef gceSTATUS (*gctDeallocatorFunc)(
++ IN gctPOINTER Memory
++ );
++
++typedef gctBOOL (*compareFunc) (
++ IN void * data,
++ IN void * key
++ );
++
++typedef struct _gcsListNode gcsListNode;
++struct _gcsListNode
++{
++ gcsListNode * next;
++ void * data;
++};
++
++typedef struct _gcsAllocator
++{
++ gctAllocatorFunc allocate;
++ gctDeallocatorFunc deallocate;
++} gcsAllocator;
++
++/* simple map structure */
++typedef struct _SimpleMap SimpleMap;
++struct _SimpleMap
++{
++ gctUINT32 key;
++ gctUINT32 val;
++ SimpleMap *next;
++ gcsAllocator *allocator;
++
++};
++
++/* SimpleMap Operations */
++/* return -1 if not found, otherwise return the mapped value */
++gctUINT32
++gcSimpleMap_Find(
++ IN SimpleMap *Map,
++ IN gctUINT32 Key
++ );
++
++gceSTATUS
++gcSimpleMap_Destory(
++ IN SimpleMap * Map,
++ IN gcsAllocator * Allocator
++ );
++
++/* Add a pair <Key, Val> to the Map head, the user should be aware that the
++ * map pointer is always changed when adding a new node :
++ *
++ * gcSimpleMap_AddNode(&theMap, key, val, allocator);
++ *
++ */
++gceSTATUS
++gcSimpleMap_AddNode(
++ IN SimpleMap ** Map,
++ IN gctUINT32 Key,
++ IN gctUINT32 Val,
++ IN gcsAllocator * Allocator
++ );
++
++/* gcsList data structure and related operations */
++typedef struct _gcsList
++{
++ gcsListNode *head;
++ gcsListNode *tail;
++ gctINT count;
++ gcsAllocator *allocator;
++} gcsList;
++
++/* List operations */
++void
++gcList_Init(
++ IN gcsList *list,
++ IN gcsAllocator *allocator
++ );
++
++gceSTATUS
++gcList_CreateNode(
++ IN void * Data,
++ IN gctAllocatorFunc Allocator,
++ OUT gcsListNode ** ListNode
++ );
++
++gceSTATUS
++gcList_Clean(
++ IN gcsList * List,
++ IN gctBOOL FreeData
++ );
++
++gcsListNode *
++gcList_FindNode(
++ IN gcsList * List,
++ IN void * Key,
++ IN compareFunc compare
++ );
++
++gceSTATUS
++gcList_AddNode(
++ IN gcsList * List,
++ IN void * Data
++ );
++
++gceSTATUS
++gcList_RemoveNode(
++ IN gcsList * List,
++ IN gcsListNode * Node
++ );
++
++/* link list structure for code list */
++typedef gcsList gcsCodeList;
++typedef gcsCodeList * gctCodeList;
++typedef gcsListNode gcsCodeListNode;
++
++/* Possible shader language opcodes. */
++typedef enum _gcSL_OPCODE
++{
++ gcSL_NOP, /* 0x00 */
++ gcSL_MOV, /* 0x01 */
++ gcSL_SAT, /* 0x02 */
++ gcSL_DP3, /* 0x03 */
++ gcSL_DP4, /* 0x04 */
++ gcSL_ABS, /* 0x05 */
++ gcSL_JMP, /* 0x06 */
++ gcSL_ADD, /* 0x07 */
++ gcSL_MUL, /* 0x08 */
++ gcSL_RCP, /* 0x09 */
++ gcSL_SUB, /* 0x0A */
++ gcSL_KILL, /* 0x0B */
++ gcSL_TEXLD, /* 0x0C */
++ gcSL_CALL, /* 0x0D */
++ gcSL_RET, /* 0x0E */
++ gcSL_NORM, /* 0x0F */
++ gcSL_MAX, /* 0x10 */
++ gcSL_MIN, /* 0x11 */
++ gcSL_POW, /* 0x12 */
++ gcSL_RSQ, /* 0x13 */
++ gcSL_LOG, /* 0x14 */
++ gcSL_FRAC, /* 0x15 */
++ gcSL_FLOOR, /* 0x16 */
++ gcSL_CEIL, /* 0x17 */
++ gcSL_CROSS, /* 0x18 */
++ gcSL_TEXLDP, /* 0x19 */
++ gcSL_TEXBIAS, /* 0x1A */
++ gcSL_TEXGRAD, /* 0x1B */
++ gcSL_TEXLOD, /* 0x1C */
++ gcSL_SIN, /* 0x1D */
++ gcSL_COS, /* 0x1E */
++ gcSL_TAN, /* 0x1F */
++ gcSL_EXP, /* 0x20 */
++ gcSL_SIGN, /* 0x21 */
++ gcSL_STEP, /* 0x22 */
++ gcSL_SQRT, /* 0x23 */
++ gcSL_ACOS, /* 0x24 */
++ gcSL_ASIN, /* 0x25 */
++ gcSL_ATAN, /* 0x26 */
++ gcSL_SET, /* 0x27 */
++ gcSL_DSX, /* 0x28 */
++ gcSL_DSY, /* 0x29 */
++ gcSL_FWIDTH, /* 0x2A */
++ gcSL_DIV, /* 0x2B */
++ gcSL_MOD, /* 0x2C */
++ gcSL_AND_BITWISE, /* 0x2D */
++ gcSL_OR_BITWISE, /* 0x2E */
++ gcSL_XOR_BITWISE, /* 0x2F */
++ gcSL_NOT_BITWISE, /* 0x30 */
++ gcSL_LSHIFT, /* 0x31 */
++ gcSL_RSHIFT, /* 0x32 */
++ gcSL_ROTATE, /* 0x33 */
++ gcSL_BITSEL, /* 0x34 */
++ gcSL_LEADZERO, /* 0x35 */
++ gcSL_LOAD, /* 0x36 */
++ gcSL_STORE, /* 0x37 */
++ gcSL_BARRIER, /* 0x38 */
++ gcSL_STORE1, /* 0x39 */
++ gcSL_ATOMADD, /* 0x3A */
++ gcSL_ATOMSUB, /* 0x3B */
++ gcSL_ATOMXCHG, /* 0x3C */
++ gcSL_ATOMCMPXCHG, /* 0x3D */
++ gcSL_ATOMMIN, /* 0x3E */
++ gcSL_ATOMMAX, /* 0x3F */
++ gcSL_ATOMOR, /* 0x40 */
++ gcSL_ATOMAND, /* 0x41 */
++ gcSL_ATOMXOR, /* 0x42 */
++ /*gcSL_UNUSED, 0x43 */
++ /*gcSL_UNUSED, 0x44 */
++ /*gcSL_UNUSED, 0x45 */
++ /*gcSL_UNUSED, 0x46 */
++ /*gcSL_UNUSED, 0x47 */
++ /*gcSL_UNUSED, 0x48 */
++ /*gcSL_UNUSED, 0x49 */
++ /*gcSL_UNUSED, 0x4A */
++ /*gcSL_UNUSED, 0x4B */
++ /*gcSL_UNUSED, 0x4C */
++ /*gcSL_UNUSED, 0x4D */
++ /*gcSL_UNUSED, 0x4E */
++ /*gcSL_UNUSED, 0x4F */
++ /*gcSL_UNUSED, 0x50 */
++ /*gcSL_UNUSED, 0x51 */
++ /*gcSL_UNUSED, 0x52 */
++ gcSL_ADDLO = 0x53, /* 0x53 */ /* Float only. */
++ gcSL_MULLO, /* 0x54 */ /* Float only. */
++ gcSL_CONV, /* 0x55 */
++ gcSL_GETEXP, /* 0x56 */
++ gcSL_GETMANT, /* 0x57 */
++ gcSL_MULHI, /* 0x58 */ /* Integer only. */
++ gcSL_CMP, /* 0x59 */
++ gcSL_I2F, /* 0x5A */
++ gcSL_F2I, /* 0x5B */
++ gcSL_ADDSAT, /* 0x5C */ /* Integer only. */
++ gcSL_SUBSAT, /* 0x5D */ /* Integer only. */
++ gcSL_MULSAT, /* 0x5E */ /* Integer only. */
++ gcSL_DP2, /* 0x5F */
++ gcSL_MAXOPCODE
++}
++gcSL_OPCODE;
++
++typedef enum _gcSL_FORMAT
++{
++ gcSL_FLOAT = 0, /* 0 */
++ gcSL_INTEGER = 1, /* 1 */
++ gcSL_INT32 = 1, /* 1 */
++ gcSL_BOOLEAN = 2, /* 2 */
++ gcSL_UINT32 = 3, /* 3 */
++ gcSL_INT8, /* 4 */
++ gcSL_UINT8, /* 5 */
++ gcSL_INT16, /* 6 */
++ gcSL_UINT16, /* 7 */
++ gcSL_INT64, /* 8 */ /* Reserved for future enhancement. */
++ gcSL_UINT64, /* 9 */ /* Reserved for future enhancement. */
++ gcSL_INT128, /* 10 */ /* Reserved for future enhancement. */
++ gcSL_UINT128, /* 11 */ /* Reserved for future enhancement. */
++ gcSL_FLOAT16, /* 12 */
++ gcSL_FLOAT64, /* 13 */ /* Reserved for future enhancement. */
++ gcSL_FLOAT128, /* 14 */ /* Reserved for future enhancement. */
++}
++gcSL_FORMAT;
++
++/* Destination write enable bits. */
++typedef enum _gcSL_ENABLE
++{
++ gcSL_ENABLE_NONE = 0x0, /* none is enabled, error/uninitialized state */
++ gcSL_ENABLE_X = 0x1,
++ gcSL_ENABLE_Y = 0x2,
++ gcSL_ENABLE_Z = 0x4,
++ gcSL_ENABLE_W = 0x8,
++ /* Combinations. */
++ gcSL_ENABLE_XY = gcSL_ENABLE_X | gcSL_ENABLE_Y,
++ gcSL_ENABLE_XYZ = gcSL_ENABLE_X | gcSL_ENABLE_Y | gcSL_ENABLE_Z,
++ gcSL_ENABLE_XYZW = gcSL_ENABLE_X | gcSL_ENABLE_Y | gcSL_ENABLE_Z | gcSL_ENABLE_W,
++ gcSL_ENABLE_XYW = gcSL_ENABLE_X | gcSL_ENABLE_Y | gcSL_ENABLE_W,
++ gcSL_ENABLE_XZ = gcSL_ENABLE_X | gcSL_ENABLE_Z,
++ gcSL_ENABLE_XZW = gcSL_ENABLE_X | gcSL_ENABLE_Z | gcSL_ENABLE_W,
++ gcSL_ENABLE_XW = gcSL_ENABLE_X | gcSL_ENABLE_W,
++ gcSL_ENABLE_YZ = gcSL_ENABLE_Y | gcSL_ENABLE_Z,
++ gcSL_ENABLE_YZW = gcSL_ENABLE_Y | gcSL_ENABLE_Z | gcSL_ENABLE_W,
++ gcSL_ENABLE_YW = gcSL_ENABLE_Y | gcSL_ENABLE_W,
++ gcSL_ENABLE_ZW = gcSL_ENABLE_Z | gcSL_ENABLE_W,
++}
++gcSL_ENABLE;
++
++/* Possible indices. */
++typedef enum _gcSL_INDEXED
++{
++ gcSL_NOT_INDEXED, /* 0 */
++ gcSL_INDEXED_X, /* 1 */
++ gcSL_INDEXED_Y, /* 2 */
++ gcSL_INDEXED_Z, /* 3 */
++ gcSL_INDEXED_W, /* 4 */
++}
++gcSL_INDEXED;
++
++/* Opcode conditions. */
++typedef enum _gcSL_CONDITION
++{
++ gcSL_ALWAYS, /* 0x0 */
++ gcSL_NOT_EQUAL, /* 0x1 */
++ gcSL_LESS_OR_EQUAL, /* 0x2 */
++ gcSL_LESS, /* 0x3 */
++ gcSL_EQUAL, /* 0x4 */
++ gcSL_GREATER, /* 0x5 */
++ gcSL_GREATER_OR_EQUAL, /* 0x6 */
++ gcSL_AND, /* 0x7 */
++ gcSL_OR, /* 0x8 */
++ gcSL_XOR, /* 0x9 */
++ gcSL_NOT_ZERO, /* 0xA */
++}
++gcSL_CONDITION;
++
++/* Possible source operand types. */
++typedef enum _gcSL_TYPE
++{
++ gcSL_NONE, /* 0x0 */
++ gcSL_TEMP, /* 0x1 */
++ gcSL_ATTRIBUTE, /* 0x2 */
++ gcSL_UNIFORM, /* 0x3 */
++ gcSL_SAMPLER, /* 0x4 */
++ gcSL_CONSTANT, /* 0x5 */
++ gcSL_OUTPUT, /* 0x6 */
++ gcSL_PHYSICAL, /* 0x7 */
++}
++gcSL_TYPE;
++
++/* Swizzle generator macro. */
++#define gcmSWIZZLE(Component1, Component2, Component3, Component4) \
++( \
++ (gcSL_SWIZZLE_ ## Component1 << 0) | \
++ (gcSL_SWIZZLE_ ## Component2 << 2) | \
++ (gcSL_SWIZZLE_ ## Component3 << 4) | \
++ (gcSL_SWIZZLE_ ## Component4 << 6) \
++)
++
++#define gcmExtractSwizzle(Swizzle, Index) \
++ ((gcSL_SWIZZLE) ((((Swizzle) >> (Index * 2)) & 0x3)))
++
++#define gcmComposeSwizzle(SwizzleX, SwizzleY, SwizzleZ, SwizzleW) \
++( \
++ ((SwizzleX) << 0) | \
++ ((SwizzleY) << 2) | \
++ ((SwizzleZ) << 4) | \
++ ((SwizzleW) << 6) \
++)
++
++/* Possible swizzle values. */
++typedef enum _gcSL_SWIZZLE
++{
++ gcSL_SWIZZLE_X, /* 0x0 */
++ gcSL_SWIZZLE_Y, /* 0x1 */
++ gcSL_SWIZZLE_Z, /* 0x2 */
++ gcSL_SWIZZLE_W, /* 0x3 */
++ /* Combinations. */
++ gcSL_SWIZZLE_XXXX = gcmSWIZZLE(X, X, X, X),
++ gcSL_SWIZZLE_YYYY = gcmSWIZZLE(Y, Y, Y, Y),
++ gcSL_SWIZZLE_ZZZZ = gcmSWIZZLE(Z, Z, Z, Z),
++ gcSL_SWIZZLE_WWWW = gcmSWIZZLE(W, W, W, W),
++ gcSL_SWIZZLE_XYYY = gcmSWIZZLE(X, Y, Y, Y),
++ gcSL_SWIZZLE_XZZZ = gcmSWIZZLE(X, Z, Z, Z),
++ gcSL_SWIZZLE_XWWW = gcmSWIZZLE(X, W, W, W),
++ gcSL_SWIZZLE_YZZZ = gcmSWIZZLE(Y, Z, Z, Z),
++ gcSL_SWIZZLE_YWWW = gcmSWIZZLE(Y, W, W, W),
++ gcSL_SWIZZLE_ZWWW = gcmSWIZZLE(Z, W, W, W),
++ gcSL_SWIZZLE_XYZZ = gcmSWIZZLE(X, Y, Z, Z),
++ gcSL_SWIZZLE_XYWW = gcmSWIZZLE(X, Y, W, W),
++ gcSL_SWIZZLE_XZWW = gcmSWIZZLE(X, Z, W, W),
++ gcSL_SWIZZLE_YZWW = gcmSWIZZLE(Y, Z, W, W),
++ gcSL_SWIZZLE_XXYZ = gcmSWIZZLE(X, X, Y, Z),
++ gcSL_SWIZZLE_XYZW = gcmSWIZZLE(X, Y, Z, W),
++ gcSL_SWIZZLE_XYXY = gcmSWIZZLE(X, Y, X, Y),
++ gcSL_SWIZZLE_YYZZ = gcmSWIZZLE(Y, Y, Z, Z),
++ gcSL_SWIZZLE_YYWW = gcmSWIZZLE(Y, Y, W, W),
++ gcSL_SWIZZLE_ZZZW = gcmSWIZZLE(Z, Z, Z, W),
++ gcSL_SWIZZLE_XZZW = gcmSWIZZLE(X, Z, Z, W),
++ gcSL_SWIZZLE_YYZW = gcmSWIZZLE(Y, Y, Z, W),
++
++ gcSL_SWIZZLE_INVALID = 0x7FFFFFFF
++}
++gcSL_SWIZZLE;
++
++typedef enum _gcSL_COMPONENT
++{
++ gcSL_COMPONENT_X, /* 0x0 */
++ gcSL_COMPONENT_Y, /* 0x1 */
++ gcSL_COMPONENT_Z, /* 0x2 */
++ gcSL_COMPONENT_W, /* 0x3 */
++ gcSL_COMPONENT_COUNT /* 0x4 */
++} gcSL_COMPONENT;
++
++#define gcmIsComponentEnabled(Enable, Component) (((Enable) & (1 << (Component))) != 0)
++
++/******************************************************************************\
++|*********************************** SHADERS **********************************|
++\******************************************************************************/
++
++/* Shader types. */
++typedef enum _gcSHADER_KIND {
++ gcSHADER_TYPE_UNKNOWN = 0,
++ gcSHADER_TYPE_VERTEX,
++ gcSHADER_TYPE_FRAGMENT,
++ gcSHADER_TYPE_CL,
++ gcSHADER_TYPE_PRECOMPILED,
++ gcSHADER_KIND_COUNT
++} gcSHADER_KIND;
++
++typedef enum _gcGL_DRIVER_VERSION {
++ gcGL_DRIVER_ES11, /* OpenGL ES 1.1 */
++ gcGL_DRIVER_ES20, /* OpenGL ES 2.0 */
++ gcGL_DRIVER_ES30 /* OpenGL ES 3.0 */
++} gcGL_DRIVER_VERSION;
++
++/* gcSHADER objects. */
++typedef struct _gcSHADER * gcSHADER;
++typedef struct _gcATTRIBUTE * gcATTRIBUTE;
++typedef struct _gcUNIFORM * gcUNIFORM;
++typedef struct _gcOUTPUT * gcOUTPUT;
++typedef struct _gcsFUNCTION * gcFUNCTION;
++typedef struct _gcsKERNEL_FUNCTION * gcKERNEL_FUNCTION;
++typedef struct _gcsHINT * gcsHINT_PTR;
++typedef struct _gcSHADER_PROFILER * gcSHADER_PROFILER;
++typedef struct _gcVARIABLE * gcVARIABLE;
++typedef struct _gcSHADER_LIST * gcSHADER_LIST;
++
++struct _gcsHINT
++{
++ /* Numbr of data transfers for Vertex Shader output. */
++ gctUINT32 vsOutputCount;
++
++ /* Flag whether the VS has point size or not. */
++ gctBOOL vsHasPointSize;
++
++#if gcdUSE_WCLIP_PATCH
++ /* Flag whether the VS gl_position.z depends on gl_position.w
++ it's a hint for wclipping */
++ gctBOOL vsPositionZDependsOnW;
++#endif
++
++ gctBOOL clipW;
++
++ /* Flag whether or not the shader has a KILL instruction. */
++ gctBOOL hasKill;
++
++ /* Element count. */
++ gctUINT32 elementCount;
++
++ /* Component count. */
++ gctUINT32 componentCount;
++
++ /* Number of data transfers for Fragment Shader input. */
++ gctUINT32 fsInputCount;
++
++ /* Maximum number of temporary registers used in FS. */
++ gctUINT32 fsMaxTemp;
++
++ /* Maximum number of temporary registers used in VS. */
++ gctUINT32 vsMaxTemp;
++
++ /* Balance minimum. */
++ gctUINT32 balanceMin;
++
++ /* Balance maximum. */
++ gctUINT32 balanceMax;
++
++ /* Auto-shift balancing. */
++ gctBOOL autoShift;
++
++ /* Flag whether the PS outputs the depth value or not. */
++ gctBOOL psHasFragDepthOut;
++
++ /* Flag whether the ThreadWalker is in PS. */
++ gctBOOL threadWalkerInPS;
++
++ /* HW reg number for position of VS */
++ gctUINT32 hwRegNoOfSIVPos;
++
++#if gcdALPHA_KILL_IN_SHADER
++ /* States to set when alpha kill is enabled. */
++ gctUINT32 killStateAddress;
++ gctUINT32 alphaKillStateValue;
++ gctUINT32 colorKillStateValue;
++
++ /* Shader instructiuon. */
++ gctUINT32 killInstructionAddress;
++ gctUINT32 alphaKillInstruction[3];
++ gctUINT32 colorKillInstruction[3];
++#endif
++
++#if TEMP_SHADER_PATCH
++ gctUINT32 pachedShaderIdentifier;
++#endif
++
++#if gcdUSE_WCLIP_PATCH
++ /* Strict WClip match. */
++ gctBOOL strictWClipMatch;
++#endif
++};
++
++#if TEMP_SHADER_PATCH
++#define INVALID_SHADER_IDENTIFIER 0xFFFFFFFF
++#endif
++
++/* gcSHADER_TYPE enumeration. */
++typedef enum _gcSHADER_TYPE
++{
++ gcSHADER_FLOAT_X1 = 0, /* 0x00 */
++ gcSHADER_FLOAT_X2, /* 0x01 */
++ gcSHADER_FLOAT_X3, /* 0x02 */
++ gcSHADER_FLOAT_X4, /* 0x03 */
++ gcSHADER_FLOAT_2X2, /* 0x04 */
++ gcSHADER_FLOAT_3X3, /* 0x05 */
++ gcSHADER_FLOAT_4X4, /* 0x06 */
++ gcSHADER_BOOLEAN_X1, /* 0x07 */
++ gcSHADER_BOOLEAN_X2, /* 0x08 */
++ gcSHADER_BOOLEAN_X3, /* 0x09 */
++ gcSHADER_BOOLEAN_X4, /* 0x0A */
++ gcSHADER_INTEGER_X1, /* 0x0B */
++ gcSHADER_INTEGER_X2, /* 0x0C */
++ gcSHADER_INTEGER_X3, /* 0x0D */
++ gcSHADER_INTEGER_X4, /* 0x0E */
++ gcSHADER_SAMPLER_1D, /* 0x0F */
++ gcSHADER_SAMPLER_2D, /* 0x10 */
++ gcSHADER_SAMPLER_3D, /* 0x11 */
++ gcSHADER_SAMPLER_CUBIC, /* 0x12 */
++ gcSHADER_FIXED_X1, /* 0x13 */
++ gcSHADER_FIXED_X2, /* 0x14 */
++ gcSHADER_FIXED_X3, /* 0x15 */
++ gcSHADER_FIXED_X4, /* 0x16 */
++ gcSHADER_IMAGE_2D, /* 0x17 */ /* For OCL. */
++ gcSHADER_IMAGE_3D, /* 0x18 */ /* For OCL. */
++ gcSHADER_SAMPLER, /* 0x19 */ /* For OCL. */
++ gcSHADER_FLOAT_2X3, /* 0x1A */
++ gcSHADER_FLOAT_2X4, /* 0x1B */
++ gcSHADER_FLOAT_3X2, /* 0x1C */
++ gcSHADER_FLOAT_3X4, /* 0x1D */
++ gcSHADER_FLOAT_4X2, /* 0x1E */
++ gcSHADER_FLOAT_4X3, /* 0x1F */
++ gcSHADER_ISAMPLER_2D, /* 0x20 */
++ gcSHADER_ISAMPLER_3D, /* 0x21 */
++ gcSHADER_ISAMPLER_CUBIC, /* 0x22 */
++ gcSHADER_USAMPLER_2D, /* 0x23 */
++ gcSHADER_USAMPLER_3D, /* 0x24 */
++ gcSHADER_USAMPLER_CUBIC, /* 0x25 */
++ gcSHADER_SAMPLER_EXTERNAL_OES, /* 0x26 */
++
++ gcSHADER_UINT_X1, /* 0x27 */
++ gcSHADER_UINT_X2, /* 0x28 */
++ gcSHADER_UINT_X3, /* 0x29 */
++ gcSHADER_UINT_X4, /* 0x2A */
++
++ gcSHADER_UNKONWN_TYPE, /* do not add type after this */
++ gcSHADER_TYPE_COUNT /* must to change gcvShaderTypeInfo at the
++ * same time if you add any new type! */}
++gcSHADER_TYPE;
++
++typedef enum _gcSHADER_TYPE_KIND
++{
++ gceTK_UNKOWN,
++ gceTK_FLOAT,
++ gceTK_INT,
++ gceTK_UINT,
++ gceTK_BOOL,
++ gceTK_FIXED,
++ gceTK_SAMPLER,
++ gceTK_IMAGE,
++ gceTK_OTHER
++} gcSHADER_TYPE_KIND;
++
++typedef struct _gcSHADER_TYPEINFO
++{
++ gcSHADER_TYPE type; /* e.g. gcSHADER_FLOAT_2X4 */
++ gctINT components; /* e.g. 4 components */
++ gctINT rows; /* e.g. 2 rows */
++ gcSHADER_TYPE componentType; /* e.g. gcSHADER_FLOAT_X4 */
++ gcSHADER_TYPE_KIND kind; /* e.g. gceTK_FLOAT */
++ gctCONST_STRING name; /* e.g. "FLOAT_2X4" */
++} gcSHADER_TYPEINFO;
++
++extern gcSHADER_TYPEINFO gcvShaderTypeInfo[];
++
++#define gcmType_Comonents(Type) (gcvShaderTypeInfo[Type].components)
++#define gcmType_Rows(Type) (gcvShaderTypeInfo[Type].rows)
++#define gcmType_ComonentType(Type) (gcvShaderTypeInfo[Type].componentType)
++#define gcmType_Kind(Type) (gcvShaderTypeInfo[Type].kind)
++#define gcmType_Name(Type) (gcvShaderTypeInfo[Type].name)
++
++#define gcmType_isMatrix(type) (gcmType_Rows(type) > 1)
++
++typedef enum _gcSHADER_VAR_CATEGORY
++{
++ gcSHADER_VAR_CATEGORY_NORMAL = 0, /* primitive type and its array */
++ gcSHADER_VAR_CATEGORY_STRUCT = 1 /* structure */
++}
++gcSHADER_VAR_CATEGORY;
++
++typedef enum _gceTYPE_QUALIFIER
++{
++ gcvTYPE_QUALIFIER_NONE = 0x0, /* unqualified */
++ gcvTYPE_QUALIFIER_VOLATILE = 0x1, /* volatile */
++}gceTYPE_QUALIFIER;
++
++typedef gctUINT16 gctTYPE_QUALIFIER;
++
++#if GC_ENABLE_LOADTIME_OPT
++typedef struct _gcSHADER_TYPE_INFO
++{
++ gcSHADER_TYPE type; /* eg. gcSHADER_FLOAT_2X3 is the type */
++ gctCONST_STRING name; /* the name of the type: "gcSHADER_FLOAT_2X3" */
++ gcSHADER_TYPE baseType; /* its base type is gcSHADER_FLOAT_2 */
++ gctINT components; /* it has 2 components */
++ gctINT rows; /* and 3 rows */
++ gctINT size; /* the size in byte */
++} gcSHADER_TYPE_INFO;
++
++extern gcSHADER_TYPE_INFO shader_type_info[];
++
++enum gceLTCDumpOption {
++ gceLTC_DUMP_UNIFORM = 0x0001,
++ gceLTC_DUMP_EVALUATION = 0x0002,
++ gceLTC_DUMP_EXPESSION = 0x0004,
++ gceLTC_DUMP_COLLECTING = 0x0008,
++};
++
++gctBOOL gcDumpOption(gctINT Opt);
++
++#endif /* GC_ENABLE_LOADTIME_OPT */
++
++#define IS_MATRIX_TYPE(type) \
++ (((type >= gcSHADER_FLOAT_2X2) && (type <= gcSHADER_FLOAT_4X4)) || \
++ ((type >= gcSHADER_FLOAT_2X3) && (type <= gcSHADER_FLOAT_4X3)))
++
++/* gcSHADER_PRECISION enumeration. */
++typedef enum _gcSHADER_PRECISION
++{
++ gcSHADER_PRECISION_DEFAULT, /* 0x00 */
++ gcSHADER_PRECISION_HIGH, /* 0x01 */
++ gcSHADER_PRECISION_MEDIUM, /* 0x02 */
++ gcSHADER_PRECISION_LOW, /* 0x03 */
++}
++gcSHADER_PRECISION;
++
++/* Shader flags. */
++typedef enum _gceSHADER_FLAGS
++{
++ gcvSHADER_NO_OPTIMIZATION = 0x00,
++ gcvSHADER_DEAD_CODE = 0x01,
++ gcvSHADER_RESOURCE_USAGE = 0x02,
++ gcvSHADER_OPTIMIZER = 0x04,
++ gcvSHADER_USE_GL_Z = 0x08,
++ /*
++ The GC family of GPU cores model GC860 and under require the Z
++ to be from 0 <= z <= w.
++ However, OpenGL specifies the Z to be from -w <= z <= w. So we
++ have to a conversion here:
++
++ z = (z + w) / 2.
++
++ So here we append two instructions to the vertex shader.
++ */
++ gcvSHADER_USE_GL_POSITION = 0x10,
++ gcvSHADER_USE_GL_FACE = 0x20,
++ gcvSHADER_USE_GL_POINT_COORD = 0x40,
++ gcvSHADER_LOADTIME_OPTIMIZER = 0x80,
++#if gcdALPHA_KILL_IN_SHADER
++ gcvSHADER_USE_ALPHA_KILL = 0x100,
++#endif
++
++#if gcdPRE_ROTATION && (ANDROID_SDK_VERSION >= 14)
++ gcvSHADER_VS_PRE_ROTATION = 0x200,
++#endif
++
++#if TEMP_INLINE_ALL_EXPANSION
++ gcvSHADER_INLINE_ALL_EXPANSION = 0x400,
++#endif
++}
++gceSHADER_FLAGS;
++
++gceSTATUS
++gcSHADER_CheckClipW(
++ IN gctCONST_STRING VertexSource,
++ IN gctCONST_STRING FragmentSource,
++ OUT gctBOOL * clipW);
++
++/*******************************************************************************
++** gcSHADER_GetUniformVectorCount
++**
++** Get the number of vectors used by uniforms for this shader.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Count
++** Pointer to a variable receiving the number of vectors.
++*/
++gceSTATUS
++gcSHADER_GetUniformVectorCount(
++ IN gcSHADER Shader,
++ OUT gctSIZE_T * Count
++ );
++
++/*******************************************************************************
++** gcOptimizer Data Structures
++*******************************************************************************/
++typedef enum _gceSHADER_OPTIMIZATION
++{
++ /* No optimization. */
++ gcvOPTIMIZATION_NONE,
++
++ /* Flow graph construction. */
++ gcvOPTIMIZATION_CONSTRUCTION = 1 << 0,
++
++ /* Dead code elimination. */
++ gcvOPTIMIZATION_DEAD_CODE = 1 << 1,
++
++ /* Redundant move instruction elimination. */
++ gcvOPTIMIZATION_REDUNDANT_MOVE = 1 << 2,
++
++ /* Inline expansion. */
++ gcvOPTIMIZATION_INLINE_EXPANSION = 1 << 3,
++
++ /* Constant propagation. */
++ gcvOPTIMIZATION_CONSTANT_PROPAGATION = 1 << 4,
++
++ /* Redundant bounds/checking elimination. */
++ gcvOPTIMIZATION_REDUNDANT_CHECKING = 1 << 5,
++
++ /* Loop invariant movement. */
++ gcvOPTIMIZATION_LOOP_INVARIANT = 1 << 6,
++
++ /* Induction variable removal. */
++ gcvOPTIMIZATION_INDUCTION_VARIABLE = 1 << 7,
++
++ /* Common subexpression elimination. */
++ gcvOPTIMIZATION_COMMON_SUBEXPRESSION = 1 << 8,
++
++ /* Control flow/banch optimization. */
++ gcvOPTIMIZATION_CONTROL_FLOW = 1 << 9,
++
++ /* Vector component operation merge. */
++ gcvOPTIMIZATION_VECTOR_INSTRUCTION_MERGE = 1 << 10,
++
++ /* Algebra simplificaton. */
++ gcvOPTIMIZATION_ALGEBRAIC_SIMPLIFICATION = 1 << 11,
++
++ /* Pattern matching and replacing. */
++ gcvOPTIMIZATION_PATTERN_MATCHING = 1 << 12,
++
++ /* Interprocedural constant propagation. */
++ gcvOPTIMIZATION_IP_CONSTANT_PROPAGATION = 1 << 13,
++
++ /* Interprecedural register optimization. */
++ gcvOPTIMIZATION_IP_REGISTRATION = 1 << 14,
++
++ /* Optimization option number. */
++ gcvOPTIMIZATION_OPTION_NUMBER = 1 << 15,
++
++ /* Loadtime constant. */
++ gcvOPTIMIZATION_LOADTIME_CONSTANT = 1 << 16,
++
++ /* MAD instruction optimization. */
++ gcvOPTIMIZATION_MAD_INSTRUCTION = 1 << 17,
++
++ /* Special optimization for LOAD SW workaround. */
++ gcvOPTIMIZATION_LOAD_SW_WORKAROUND = 1 << 18,
++
++ /* move code into conditional block if possile */
++ gcvOPTIMIZATION_CONDITIONALIZE = 1 << 19,
++
++ /* expriemental: power optimization mode
++ 1. add extra dummy texld to tune performance
++ 2. insert NOP after high power instrucitons
++ 3. split high power vec3/vec4 instruciton to vec2/vec1 operation
++ 4. ...
++ */
++ gcvOPTIMIZATION_POWER_OPTIMIZATION = 1 << 20,
++
++ /* optimize varying packing */
++ gcvOPTIMIZATION_VARYINGPACKING = 1 << 22,
++
++#if TEMP_INLINE_ALL_EXPANSION
++ gcvOPTIMIZATION_INLINE_ALL_EXPANSION = 1 << 23,
++#endif
++
++ /* Full optimization. */
++ /* Note that gcvOPTIMIZATION_LOAD_SW_WORKAROUND is off. */
++ gcvOPTIMIZATION_FULL = 0x7FFFFFFF &
++ ~gcvOPTIMIZATION_LOAD_SW_WORKAROUND &
++ ~gcvOPTIMIZATION_INLINE_ALL_EXPANSION &
++ ~gcvOPTIMIZATION_POWER_OPTIMIZATION,
++
++ /* Optimization Unit Test flag. */
++ gcvOPTIMIZATION_UNIT_TEST = 1 << 31
++}
++gceSHADER_OPTIMIZATION;
++
++typedef enum _gceOPTIMIZATION_VaryingPaking
++{
++ gcvOPTIMIZATION_VARYINGPACKING_NONE = 0,
++ gcvOPTIMIZATION_VARYINGPACKING_NOSPLIT,
++ gcvOPTIMIZATION_VARYINGPACKING_SPLIT
++} gceOPTIMIZATION_VaryingPaking;
++
++typedef struct _gcOPTIMIZER_OPTION
++{
++ gceSHADER_OPTIMIZATION optFlags;
++
++ /* debug & dump options:
++
++ VC_OPTION=-DUMP:SRC:OPT|:OPTV|:CG|:CGV:|ALL|ALLV
++
++ SRC: dump shader source code
++ OPT: dump incoming and final IR
++ OPTV: dump result IR in each optimization phase
++ CG: dump generated machine code
++ CGV: dump BE tree and optimization detail
++
++ ALL = SRC|OPT|CG
++ ALLV = SRC|OPT|OPTV|CG|CGV
++ */
++ gctBOOL dumpShaderSource; /* dump shader source code */
++ gctBOOL dumpOptimizer; /* dump incoming and final IR */
++ gctBOOL dumpOptimizerVerbose; /* dump result IR in each optimization phase */
++ gctBOOL dumpBEGenertedCode; /* dump generated machine code */
++ gctBOOL dumpBEVerbose; /* dump BE tree and optimization detail */
++ gctBOOL dumpBEFinalIR; /* dump BE final IR */
++
++ /* Code generation */
++
++ /* Varying Packing:
++
++ VC_OPTION=-PACKVARYING:[0-2]|:T[-]m[,n]|:LshaderIdx,min,max
++
++ 0: turn off varying packing
++ 1: pack varyings, donot split any varying
++ 2: pack varyings, may split to make fully packed output
++
++ Tm: only packing shader pair which vertex shader id is m
++ Tm,n: only packing shader pair which vertex shader id
++ is in range of [m, n]
++ T-m: do not packing shader pair which vertex shader id is m
++ T-m,n: do not packing shader pair which vertex shader id
++ is in range of [m, n]
++
++ LshaderIdx,min,max : set load balance (min, max) for shaderIdx
++ if shaderIdx is -1, all shaders are impacted
++ newMin = origMin * (min/100.);
++ newMax = origMax * (max/100.);
++ */
++ gceOPTIMIZATION_VaryingPaking packVarying;
++ gctINT _triageStart;
++ gctINT _triageEnd;
++ gctINT _loadBalanceShaderIdx;
++ gctINT _loadBalanceMin;
++ gctINT _loadBalanceMax;
++
++ /* Do not generate immdeiate
++
++ VC_OPTION=-NOIMM
++
++ Force generate immediate even the machine model don't support it,
++ for testing purpose only
++
++ VC_OPTION=-FORCEIMM
++ */
++ gctBOOL noImmediate;
++ gctBOOL forceImmediate;
++
++ /* Power reduction mode options */
++ gctBOOL needPowerOptimization;
++
++ /* Patch TEXLD instruction by adding dummy texld
++ (can be used to tune GPU power usage):
++ for every TEXLD we seen, add n dummy TEXLD
++
++ it can be enabled by environment variable:
++
++ VC_OPTION=-PATCH_TEXLD:M:N
++
++ (for each M texld, add N dummy texld)
++ */
++ gctINT patchEveryTEXLDs;
++ gctINT patchDummyTEXLDs;
++
++ /* Insert NOP after high power consumption instructions
++
++ VC_OPTION="-INSERTNOP:MUL:MULLO:DP3:DP4:SEENTEXLD"
++ */
++ gctBOOL insertNOP;
++ gctBOOL insertNOPAfterMUL;
++ gctBOOL insertNOPAfterMULLO;
++ gctBOOL insertNOPAfterDP3;
++ gctBOOL insertNOPAfterDP4;
++ gctBOOL insertNOPOnlyWhenTexldSeen;
++
++ /* split MAD to MUL and ADD:
++
++ VC_OPTION=-SPLITMAD
++ */
++ gctBOOL splitMAD;
++
++ /* Convert vect3/vec4 operations to multiple vec2/vec1 operations
++
++ VC_OPTION=-SPLITVEC:MUL:MULLO:DP3:DP4
++ */
++ gctBOOL splitVec;
++ gctBOOL splitVec4MUL;
++ gctBOOL splitVec4MULLO;
++ gctBOOL splitVec4DP3;
++ gctBOOL splitVec4DP4;
++
++ /* turn/off features:
++
++ VC_OPTION=-F:n,[0|1]
++ Note: n must be decimal number
++ */
++ gctUINT featureBits;
++
++ /* inline level (default 2 at O1):
++
++ VC_OPTION=-INLINELEVEL:[0-3]
++ 0: no inline
++ 1: only inline the function only called once or small function
++ 2: inline functions be called less than 5 times or medium size function
++ 3: inline everything possible
++ */
++ gctUINT inlineLevel;
++} gcOPTIMIZER_OPTION;
++
++extern gcOPTIMIZER_OPTION theOptimizerOption;
++#define gcmGetOptimizerOption() gcGetOptimizerOption()
++
++#define gcmOPT_DUMP_SHADER_SRC() \
++ (gcmGetOptimizerOption()->dumpShaderSource != 0)
++#define gcmOPT_DUMP_OPTIMIZER() \
++ (gcmGetOptimizerOption()->dumpOptimizer != 0 || \
++ gcmOPT_DUMP_OPTIMIZER_VERBOSE() )
++#define gcmOPT_DUMP_OPTIMIZER_VERBOSE() \
++ (gcmGetOptimizerOption()->dumpOptimizerVerbose != 0)
++#define gcmOPT_DUMP_CODEGEN() \
++ (gcmGetOptimizerOption()->dumpBEGenertedCode != 0 || \
++ gcmOPT_DUMP_CODEGEN_VERBOSE() )
++#define gcmOPT_DUMP_CODEGEN_VERBOSE() \
++ (gcmGetOptimizerOption()->dumpBEVerbose != 0)
++#define gcmOPT_DUMP_FINAL_IR() \
++ (gcmGetOptimizerOption()->dumpBEFinalIR != 0)
++
++#define gcmOPT_SET_DUMP_SHADER_SRC(v) \
++ gcmGetOptimizerOption()->dumpShaderSource = (v)
++
++#define gcmOPT_PATCH_TEXLD() (gcmGetOptimizerOption()->patchDummyTEXLDs != 0)
++#define gcmOPT_INSERT_NOP() (gcmGetOptimizerOption()->insertNOP == gcvTRUE)
++#define gcmOPT_SPLITMAD() (gcmGetOptimizerOption()->splitMAD == gcvTRUE)
++#define gcmOPT_SPLITVEC() (gcmGetOptimizerOption()->splitVec == gcvTRUE)
++
++#define gcmOPT_NOIMMEDIATE() (gcmGetOptimizerOption()->noImmediate == gcvTRUE)
++#define gcmOPT_FORCEIMMEDIATE() (gcmGetOptimizerOption()->forceImmediate == gcvTRUE)
++
++#define gcmOPT_PACKVARYING() (gcmGetOptimizerOption()->packVarying)
++#define gcmOPT_PACKVARYING_triageStart() (gcmGetOptimizerOption()->_triageStart)
++#define gcmOPT_PACKVARYING_triageEnd() (gcmGetOptimizerOption()->_triageEnd)
++
++#define gcmOPT_INLINELEVEL() (gcmGetOptimizerOption()->inlineLevel)
++
++/* Setters */
++#define gcmOPT_SetPatchTexld(m,n) (gcmGetOptimizerOption()->patchEveryTEXLDs = (m),\
++ gcmGetOptimizerOption()->patchDummyTEXLDs = (n))
++#define gcmOPT_SetSplitVecMUL() (gcmGetOptimizerOption()->splitVec = gcvTRUE, \
++ gcmGetOptimizerOption()->splitVec4MUL = gcvTRUE)
++#define gcmOPT_SetSplitVecMULLO() (gcmGetOptimizerOption()->splitVec = gcvTRUE, \
++ gcmGetOptimizerOption()->splitVec4MULLO = gcvTRUE)
++#define gcmOPT_SetSplitVecDP3() (gcmGetOptimizerOption()->splitVec = gcvTRUE, \
++ gcmGetOptimizerOption()->splitVec4DP3 = gcvTRUE)
++#define gcmOPT_SetSplitVecDP4() (gcmGetOptimizerOption()->splitVec = gcvTRUE, \
++ gcmGetOptimizerOption()->splitVec4DP4 = gcvTRUE)
++
++#define gcmOPT_SetPackVarying(v) (gcmGetOptimizerOption()->packVarying = v)
++
++#define FB_LIVERANGE_FIX1 0x0001
++
++
++#define PredefinedDummySamplerId 8
++
++/* Function argument qualifier */
++typedef enum _gceINPUT_OUTPUT
++{
++ gcvFUNCTION_INPUT,
++ gcvFUNCTION_OUTPUT,
++ gcvFUNCTION_INOUT
++}
++gceINPUT_OUTPUT;
++
++/* Kernel function property flags. */
++typedef enum _gcePROPERTY_FLAGS
++{
++ gcvPROPERTY_REQD_WORK_GRP_SIZE = 0x01
++}
++gceKERNEL_FUNCTION_PROPERTY_FLAGS;
++
++/* Uniform flags. */
++typedef enum _gceUNIFORM_FLAGS
++{
++ gcvUNIFORM_KERNEL_ARG = 0x01,
++ gcvUNIFORM_KERNEL_ARG_LOCAL = 0x02,
++ gcvUNIFORM_KERNEL_ARG_SAMPLER = 0x04,
++ gcvUNIFORM_LOCAL_ADDRESS_SPACE = 0x08,
++ gcvUNIFORM_PRIVATE_ADDRESS_SPACE = 0x10,
++ gcvUNIFORM_CONSTANT_ADDRESS_SPACE = 0x20,
++ gcvUNIFORM_GLOBAL_SIZE = 0x40,
++ gcvUNIFORM_LOCAL_SIZE = 0x80,
++ gcvUNIFORM_NUM_GROUPS = 0x100,
++ gcvUNIFORM_GLOBAL_OFFSET = 0x200,
++ gcvUNIFORM_WORK_DIM = 0x400,
++ gcvUNIFORM_KERNEL_ARG_CONSTANT = 0x800,
++ gcvUNIFORM_KERNEL_ARG_LOCAL_MEM_SIZE = 0x1000,
++ gcvUNIFORM_KERNEL_ARG_PRIVATE = 0x2000,
++ gcvUNIFORM_LOADTIME_CONSTANT = 0x4000,
++ gcvUNIFORM_IS_ARRAY = 0x8000,
++}
++gceUNIFORM_FLAGS;
++
++#define gcdUNIFORM_KERNEL_ARG_MASK (gcvUNIFORM_KERNEL_ARG | \
++ gcvUNIFORM_KERNEL_ARG_LOCAL | \
++ gcvUNIFORM_KERNEL_ARG_SAMPLER | \
++ gcvUNIFORM_KERNEL_ARG_PRIVATE | \
++ gcvUNIFORM_KERNEL_ARG_CONSTANT)
++
++typedef enum _gceVARIABLE_UPDATE_FLAGS
++{
++ gcvVARIABLE_UPDATE_NOUPDATE = 0,
++ gcvVARIABLE_UPDATE_TEMPREG,
++ gcvVARIABLE_UPDATE_TYPE_QUALIFIER,
++}gceVARIABLE_UPDATE_FLAGS;
++
++typedef struct _gcMACHINE_INST
++{
++ gctUINT state0;
++ gctUINT state1;
++ gctUINT state2;
++ gctUINT state3;
++}gcMACHINE_INST, *gcMACHINE_INST_PTR;
++
++typedef struct _gcMACHINECODE
++{
++ gcMACHINE_INST_PTR pCode; /* machine code */
++ gctUINT instCount; /* 128-bit count */
++ gctUINT maxConstRegNo;
++ gctUINT maxTempRegNo;
++ gctUINT endPCOfMainRoutine;
++}gcMACHINECODE, *gcMACHINECODE_PTR;
++
++typedef enum NP2_ADDRESS_MODE
++{
++ NP2_ADDRESS_MODE_CLAMP = 0,
++ NP2_ADDRESS_MODE_REPEAT = 1,
++ NP2_ADDRESS_MODE_MIRROR = 2
++}NP2_ADDRESS_MODE;
++
++typedef struct _gcNPOT_PATCH_PARAM
++{
++ gctINT samplerSlot;
++ NP2_ADDRESS_MODE addressMode[3];
++ gctINT texDimension; /* 2 or 3 */
++}gcNPOT_PATCH_PARAM, *gcNPOT_PATCH_PARAM_PTR;
++
++typedef struct _gcZBIAS_PATCH_PARAM
++{
++ /* Driver uses this to program uniform that designating zbias */
++ gctINT uniformAddr;
++ gctINT channel;
++}gcZBIAS_PATCH_PARAM, *gcZBIAS_PATCH_PARAM_PTR;
++
++void
++gcGetOptionFromEnv(
++ IN OUT gcOPTIMIZER_OPTION * Option
++ );
++
++void
++gcSetOptimizerOption(
++ IN gceSHADER_FLAGS Flags
++ );
++
++gcOPTIMIZER_OPTION *
++gcGetOptimizerOption();
++
++/*******************************************************************************
++** gcSHADER_SetCompilerVersion
++**
++** Set the compiler version of a gcSHADER object.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to gcSHADER object
++**
++** gctINT *Version
++** Pointer to a two word version
++*/
++gceSTATUS
++gcSHADER_SetCompilerVersion(
++ IN gcSHADER Shader,
++ IN gctUINT32 *Version
++ );
++
++/*******************************************************************************
++** gcSHADER_GetCompilerVersion
++**
++** Get the compiler version of a gcSHADER object.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** OUTPUT:
++**
++** gctUINT32_PTR *CompilerVersion.
++** Pointer to holder of returned compilerVersion pointer
++*/
++gceSTATUS
++gcSHADER_GetCompilerVersion(
++ IN gcSHADER Shader,
++ OUT gctUINT32_PTR *CompilerVersion
++ );
++
++/*******************************************************************************
++** gcSHADER_GetType
++**
++** Get the gcSHADER object's type.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** OUTPUT:
++**
++** gctINT *Type.
++** Pointer to return shader type.
++*/
++gceSTATUS
++gcSHADER_GetType(
++ IN gcSHADER Shader,
++ OUT gctINT *Type
++ );
++
++gctUINT
++gcSHADER_NextId();
++/*******************************************************************************
++** gcSHADER_Construct
++********************************************************************************
++**
++** Construct a new gcSHADER object.
++**
++** INPUT:
++**
++** gcoOS Hal
++** Pointer to an gcoHAL object.
++**
++** gctINT ShaderType
++** Type of gcSHADER object to cerate. 'ShaderType' can be one of the
++** following:
++**
++** gcSHADER_TYPE_VERTEX Vertex shader.
++** gcSHADER_TYPE_FRAGMENT Fragment shader.
++**
++** OUTPUT:
++**
++** gcSHADER * Shader
++** Pointer to a variable receiving the gcSHADER object pointer.
++*/
++gceSTATUS
++gcSHADER_Construct(
++ IN gcoHAL Hal,
++ IN gctINT ShaderType,
++ OUT gcSHADER * Shader
++ );
++
++/*******************************************************************************
++** gcSHADER_Destroy
++********************************************************************************
++**
++** Destroy a gcSHADER object.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gcSHADER_Destroy(
++ IN gcSHADER Shader
++ );
++
++/*******************************************************************************
++** gcSHADER_Copy
++********************************************************************************
++**
++** Copy a gcSHADER object.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gcSHADER Source
++** Pointer to a gcSHADER object that will be copied.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gcSHADER_Copy(
++ IN gcSHADER Shader,
++ IN gcSHADER Source
++ );
++
++/*******************************************************************************
++** gcSHADER_LoadHeader
++**
++** Load a gcSHADER object from a binary buffer. The binary buffer is layed out
++** as follows:
++** // Six word header
++** // Signature, must be 'S','H','D','R'.
++** gctINT8 signature[4];
++** gctUINT32 binFileVersion;
++** gctUINT32 compilerVersion[2];
++** gctUINT32 gcSLVersion;
++** gctUINT32 binarySize;
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++** Shader type will be returned if type in shader object is not gcSHADER_TYPE_PRECOMPILED
++**
++** gctPOINTER Buffer
++** Pointer to a binary buffer containing the shader data to load.
++**
++** gctSIZE_T BufferSize
++** Number of bytes inside the binary buffer pointed to by 'Buffer'.
++**
++** OUTPUT:
++** nothing
++**
++*/
++gceSTATUS
++gcSHADER_LoadHeader(
++ IN gcSHADER Shader,
++ IN gctPOINTER Buffer,
++ IN gctSIZE_T BufferSize,
++ OUT gctUINT32 * ShaderVersion
++ );
++
++/*******************************************************************************
++** gcSHADER_LoadKernel
++**
++** Load a kernel function given by name into gcSHADER object
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gctSTRING KernelName
++** Pointer to a kernel function name
++**
++** OUTPUT:
++** nothing
++**
++*/
++gceSTATUS
++gcSHADER_LoadKernel(
++ IN gcSHADER Shader,
++ IN gctSTRING KernelName
++ );
++
++/*******************************************************************************
++** gcSHADER_Load
++********************************************************************************
++**
++** Load a gcSHADER object from a binary buffer.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gctPOINTER Buffer
++** Pointer to a binary buffer containg the shader data to load.
++**
++** gctSIZE_T BufferSize
++** Number of bytes inside the binary buffer pointed to by 'Buffer'.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gcSHADER_Load(
++ IN gcSHADER Shader,
++ IN gctPOINTER Buffer,
++ IN gctSIZE_T BufferSize
++ );
++
++/*******************************************************************************
++** gcSHADER_Save
++********************************************************************************
++**
++** Save a gcSHADER object to a binary buffer.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gctPOINTER Buffer
++** Pointer to a binary buffer to be used as storage for the gcSHADER
++** object. If 'Buffer' is gcvNULL, the gcSHADER object will not be saved,
++** but the number of bytes required to hold the binary output for the
++** gcSHADER object will be returned.
++**
++** gctSIZE_T * BufferSize
++** Pointer to a variable holding the number of bytes allocated in
++** 'Buffer'. Only valid if 'Buffer' is not gcvNULL.
++**
++** OUTPUT:
++**
++** gctSIZE_T * BufferSize
++** Pointer to a variable receiving the number of bytes required to hold
++** the binary form of the gcSHADER object.
++*/
++gceSTATUS
++gcSHADER_Save(
++ IN gcSHADER Shader,
++ IN gctPOINTER Buffer,
++ IN OUT gctSIZE_T * BufferSize
++ );
++
++/*******************************************************************************
++** gcSHADER_LoadEx
++********************************************************************************
++**
++** Load a gcSHADER object from a binary buffer.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gctPOINTER Buffer
++** Pointer to a binary buffer containg the shader data to load.
++**
++** gctSIZE_T BufferSize
++** Number of bytes inside the binary buffer pointed to by 'Buffer'.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gcSHADER_LoadEx(
++ IN gcSHADER Shader,
++ IN gctPOINTER Buffer,
++ IN gctSIZE_T BufferSize
++ );
++
++/*******************************************************************************
++** gcSHADER_SaveEx
++********************************************************************************
++**
++** Save a gcSHADER object to a binary buffer.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gctPOINTER Buffer
++** Pointer to a binary buffer to be used as storage for the gcSHADER
++** object. If 'Buffer' is gcvNULL, the gcSHADER object will not be saved,
++** but the number of bytes required to hold the binary output for the
++** gcSHADER object will be returned.
++**
++** gctSIZE_T * BufferSize
++** Pointer to a variable holding the number of bytes allocated in
++** 'Buffer'. Only valid if 'Buffer' is not gcvNULL.
++**
++** OUTPUT:
++**
++** gctSIZE_T * BufferSize
++** Pointer to a variable receiving the number of bytes required to hold
++** the binary form of the gcSHADER object.
++*/
++gceSTATUS
++gcSHADER_SaveEx(
++ IN gcSHADER Shader,
++ IN gctPOINTER Buffer,
++ IN OUT gctSIZE_T * BufferSize
++ );
++
++/*******************************************************************************
++** gcSHADER_ReallocateAttributes
++**
++** Reallocate an array of pointers to gcATTRIBUTE objects.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gctSIZE_T Count
++** Array count to reallocate. 'Count' must be at least 1.
++*/
++gceSTATUS
++gcSHADER_ReallocateAttributes(
++ IN gcSHADER Shader,
++ IN gctSIZE_T Count
++ );
++
++/*******************************************************************************
++** gcSHADER_AddAttribute
++********************************************************************************
++**
++** Add an attribute to a gcSHADER object.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gctCONST_STRING Name
++** Name of the attribute to add.
++**
++** gcSHADER_TYPE Type
++** Type of the attribute to add.
++**
++** gctSIZE_T Length
++** Array length of the attribute to add. 'Length' must be at least 1.
++**
++** gctBOOL IsTexture
++** gcvTRUE if the attribute is used as a texture coordinate, gcvFALSE if not.
++**
++** OUTPUT:
++**
++** gcATTRIBUTE * Attribute
++** Pointer to a variable receiving the gcATTRIBUTE object pointer.
++*/
++gceSTATUS
++gcSHADER_AddAttribute(
++ IN gcSHADER Shader,
++ IN gctCONST_STRING Name,
++ IN gcSHADER_TYPE Type,
++ IN gctSIZE_T Length,
++ IN gctBOOL IsTexture,
++ OUT gcATTRIBUTE * Attribute
++ );
++
++/*******************************************************************************
++** gcSHADER_GetAttributeCount
++********************************************************************************
++**
++** Get the number of attributes for this shader.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Count
++** Pointer to a variable receiving the number of attributes.
++*/
++gceSTATUS
++gcSHADER_GetAttributeCount(
++ IN gcSHADER Shader,
++ OUT gctSIZE_T * Count
++ );
++
++/*******************************************************************************
++** gcSHADER_GetAttribute
++********************************************************************************
++**
++** Get the gcATTRIBUTE object poniter for an indexed attribute for this shader.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gctUINT Index
++** Index of the attribute to retrieve.
++**
++** OUTPUT:
++**
++** gcATTRIBUTE * Attribute
++** Pointer to a variable receiving the gcATTRIBUTE object pointer.
++*/
++gceSTATUS
++gcSHADER_GetAttribute(
++ IN gcSHADER Shader,
++ IN gctUINT Index,
++ OUT gcATTRIBUTE * Attribute
++ );
++
++/*******************************************************************************
++** gcSHADER_ReallocateUniforms
++**
++** Reallocate an array of pointers to gcUNIFORM objects.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gctSIZE_T Count
++** Array count to reallocate. 'Count' must be at least 1.
++*/
++gceSTATUS
++gcSHADER_ReallocateUniforms(
++ IN gcSHADER Shader,
++ IN gctSIZE_T Count
++ );
++
++/*******************************************************************************
++** gcSHADER_AddUniform
++********************************************************************************
++**
++** Add an uniform to a gcSHADER object.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gctCONST_STRING Name
++** Name of the uniform to add.
++**
++** gcSHADER_TYPE Type
++** Type of the uniform to add.
++**
++** gctSIZE_T Length
++** Array length of the uniform to add. 'Length' must be at least 1.
++**
++** OUTPUT:
++**
++** gcUNIFORM * Uniform
++** Pointer to a variable receiving the gcUNIFORM object pointer.
++*/
++gceSTATUS
++gcSHADER_AddUniform(
++ IN gcSHADER Shader,
++ IN gctCONST_STRING Name,
++ IN gcSHADER_TYPE Type,
++ IN gctSIZE_T Length,
++ OUT gcUNIFORM * Uniform
++ );
++
++/*******************************************************************************
++** gcSHADER_AddPreRotationUniform
++********************************************************************************
++**
++** Add an uniform to a gcSHADER object.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gctCONST_STRING Name
++** Name of the uniform to add.
++**
++** gcSHADER_TYPE Type
++** Type of the uniform to add.
++**
++** gctSIZE_T Length
++** Array length of the uniform to add. 'Length' must be at least 1.
++**
++** gctINT col
++** Which uniform.
++**
++** OUTPUT:
++**
++** gcUNIFORM * Uniform
++** Pointer to a variable receiving the gcUNIFORM object pointer.
++*/
++gceSTATUS
++gcSHADER_AddPreRotationUniform(
++ IN gcSHADER Shader,
++ IN gctCONST_STRING Name,
++ IN gcSHADER_TYPE Type,
++ IN gctSIZE_T Length,
++ IN gctINT col,
++ OUT gcUNIFORM * Uniform
++ );
++
++/*******************************************************************************
++** gcSHADER_AddUniformEx
++********************************************************************************
++**
++** Add an uniform to a gcSHADER object.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gctCONST_STRING Name
++** Name of the uniform to add.
++**
++** gcSHADER_TYPE Type
++** Type of the uniform to add.
++**
++** gcSHADER_PRECISION precision
++** Precision of the uniform to add.
++**
++** gctSIZE_T Length
++** Array length of the uniform to add. 'Length' must be at least 1.
++**
++** OUTPUT:
++**
++** gcUNIFORM * Uniform
++** Pointer to a variable receiving the gcUNIFORM object pointer.
++*/
++gceSTATUS
++gcSHADER_AddUniformEx(
++ IN gcSHADER Shader,
++ IN gctCONST_STRING Name,
++ IN gcSHADER_TYPE Type,
++ IN gcSHADER_PRECISION precision,
++ IN gctSIZE_T Length,
++ OUT gcUNIFORM * Uniform
++ );
++
++/*******************************************************************************
++** gcSHADER_AddUniformEx1
++********************************************************************************
++**
++** Add an uniform to a gcSHADER object.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gctCONST_STRING Name
++** Name of the uniform to add.
++**
++** gcSHADER_TYPE Type
++** Type of the uniform to add.
++**
++** gcSHADER_PRECISION precision
++** Precision of the uniform to add.
++**
++** gctSIZE_T Length
++** Array length of the uniform to add. 'Length' must be at least 1.
++**
++** gcSHADER_VAR_CATEGORY varCategory
++** Variable category, normal or struct.
++**
++** gctUINT16 numStructureElement
++** If struct, its element number.
++**
++** gctINT16 parent
++** If struct, parent index in gcSHADER.variables.
++**
++** gctINT16 prevSibling
++** If struct, previous sibling index in gcSHADER.variables.
++**
++** OUTPUT:
++**
++** gcUNIFORM * Uniform
++** Pointer to a variable receiving the gcUNIFORM object pointer.
++**
++** gctINT16* ThisUniformIndex
++** Returned value about uniform index in gcSHADER.
++*/
++gceSTATUS
++gcSHADER_AddUniformEx1(
++ IN gcSHADER Shader,
++ IN gctCONST_STRING Name,
++ IN gcSHADER_TYPE Type,
++ IN gcSHADER_PRECISION precision,
++ IN gctSIZE_T Length,
++ IN gctINT IsArray,
++ IN gcSHADER_VAR_CATEGORY varCategory,
++ IN gctUINT16 numStructureElement,
++ IN gctINT16 parent,
++ IN gctINT16 prevSibling,
++ OUT gctINT16* ThisUniformIndex,
++ OUT gcUNIFORM * Uniform
++ );
++
++/*******************************************************************************
++** gcSHADER_GetUniformCount
++********************************************************************************
++**
++** Get the number of uniforms for this shader.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Count
++** Pointer to a variable receiving the number of uniforms.
++*/
++gceSTATUS
++gcSHADER_GetUniformCount(
++ IN gcSHADER Shader,
++ OUT gctSIZE_T * Count
++ );
++
++/*******************************************************************************
++** gcSHADER_GetPreRotationUniform
++********************************************************************************
++**
++** Get the preRotate Uniform.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** OUTPUT:
++**
++** gcUNIFORM ** pUniform
++** Pointer to a preRotation uniforms array.
++*/
++gceSTATUS
++gcSHADER_GetPreRotationUniform(
++ IN gcSHADER Shader,
++ OUT gcUNIFORM ** pUniform
++ );
++
++/*******************************************************************************
++** gcSHADER_GetUniform
++********************************************************************************
++**
++** Get the gcUNIFORM object pointer for an indexed uniform for this shader.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gctUINT Index
++** Index of the uniform to retrieve.
++**
++** OUTPUT:
++**
++** gcUNIFORM * Uniform
++** Pointer to a variable receiving the gcUNIFORM object pointer.
++*/
++gceSTATUS
++gcSHADER_GetUniform(
++ IN gcSHADER Shader,
++ IN gctUINT Index,
++ OUT gcUNIFORM * Uniform
++ );
++
++
++/*******************************************************************************
++** gcSHADER_GetUniformIndexingRange
++********************************************************************************
++**
++** Get the gcUNIFORM object pointer for an indexed uniform for this shader.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gctINT uniformIndex
++** Index of the start uniform.
++**
++** gctINT offset
++** Offset to indexing.
++**
++** OUTPUT:
++**
++** gctINT * LastUniformIndex
++** Pointer to index of last uniform in indexing range.
++**
++** gctINT * OffsetUniformIndex
++** Pointer to index of uniform that indexing at offset.
++**
++** gctINT * DeviationInOffsetUniform
++** Pointer to offset in uniform picked up.
++*/
++gceSTATUS
++gcSHADER_GetUniformIndexingRange(
++ IN gcSHADER Shader,
++ IN gctINT uniformIndex,
++ IN gctINT offset,
++ OUT gctINT * LastUniformIndex,
++ OUT gctINT * OffsetUniformIndex,
++ OUT gctINT * DeviationInOffsetUniform
++ );
++
++/*******************************************************************************
++** gcSHADER_GetKernelFucntion
++**
++** Get the gcKERNEL_FUNCTION object pointer for an indexed kernel function for this shader.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gctUINT Index
++** Index of kernel function to retreive the name for.
++**
++** OUTPUT:
++**
++** gcKERNEL_FUNCTION * KernelFunction
++** Pointer to a variable receiving the gcKERNEL_FUNCTION object pointer.
++*/
++gceSTATUS
++gcSHADER_GetKernelFunction(
++ IN gcSHADER Shader,
++ IN gctUINT Index,
++ OUT gcKERNEL_FUNCTION * KernelFunction
++ );
++
++gceSTATUS
++gcSHADER_GetKernelFunctionByName(
++ IN gcSHADER Shader,
++ IN gctSTRING KernelName,
++ OUT gcKERNEL_FUNCTION * KernelFunction
++ );
++/*******************************************************************************
++** gcSHADER_GetKernelFunctionCount
++**
++** Get the number of kernel functions for this shader.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Count
++** Pointer to a variable receiving the number of kernel functions.
++*/
++gceSTATUS
++gcSHADER_GetKernelFunctionCount(
++ IN gcSHADER Shader,
++ OUT gctSIZE_T * Count
++ );
++
++/*******************************************************************************
++** gcSHADER_ReallocateOutputs
++**
++** Reallocate an array of pointers to gcOUTPUT objects.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gctSIZE_T Count
++** Array count to reallocate. 'Count' must be at least 1.
++*/
++gceSTATUS
++gcSHADER_ReallocateOutputs(
++ IN gcSHADER Shader,
++ IN gctSIZE_T Count
++ );
++
++/*******************************************************************************
++** gcSHADER_AddOutput
++********************************************************************************
++**
++** Add an output to a gcSHADER object.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gctCONST_STRING Name
++** Name of the output to add.
++**
++** gcSHADER_TYPE Type
++** Type of the output to add.
++**
++** gctSIZE_T Length
++** Array length of the output to add. 'Length' must be at least 1.
++**
++** gctUINT16 TempRegister
++** Temporary register index that holds the output value.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gcSHADER_AddOutput(
++ IN gcSHADER Shader,
++ IN gctCONST_STRING Name,
++ IN gcSHADER_TYPE Type,
++ IN gctSIZE_T Length,
++ IN gctUINT16 TempRegister
++ );
++
++gceSTATUS
++gcSHADER_AddOutputIndexed(
++ IN gcSHADER Shader,
++ IN gctCONST_STRING Name,
++ IN gctSIZE_T Index,
++ IN gctUINT16 TempIndex
++ );
++
++/*******************************************************************************
++** gcSHADER_GetOutputCount
++********************************************************************************
++**
++** Get the number of outputs for this shader.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Count
++** Pointer to a variable receiving the number of outputs.
++*/
++gceSTATUS
++gcSHADER_GetOutputCount(
++ IN gcSHADER Shader,
++ OUT gctSIZE_T * Count
++ );
++
++/*******************************************************************************
++** gcSHADER_GetOutput
++********************************************************************************
++**
++** Get the gcOUTPUT object pointer for an indexed output for this shader.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gctUINT Index
++** Index of output to retrieve.
++**
++** OUTPUT:
++**
++** gcOUTPUT * Output
++** Pointer to a variable receiving the gcOUTPUT object pointer.
++*/
++gceSTATUS
++gcSHADER_GetOutput(
++ IN gcSHADER Shader,
++ IN gctUINT Index,
++ OUT gcOUTPUT * Output
++ );
++
++
++/*******************************************************************************
++** gcSHADER_GetOutputByName
++********************************************************************************
++**
++** Get the gcOUTPUT object pointer for this shader by output name.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gctSTRING name
++** Name of output to retrieve.
++**
++** gctSIZE_T nameLength
++** Length of name to retrieve
++**
++** OUTPUT:
++**
++** gcOUTPUT * Output
++** Pointer to a variable receiving the gcOUTPUT object pointer.
++*/
++gceSTATUS
++gcSHADER_GetOutputByName(
++ IN gcSHADER Shader,
++ IN gctSTRING name,
++ IN gctSIZE_T nameLength,
++ OUT gcOUTPUT * Output
++ );
++
++/*******************************************************************************
++** gcSHADER_ReallocateVariables
++**
++** Reallocate an array of pointers to gcVARIABLE objects.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gctSIZE_T Count
++** Array count to reallocate. 'Count' must be at least 1.
++*/
++gceSTATUS
++gcSHADER_ReallocateVariables(
++ IN gcSHADER Shader,
++ IN gctSIZE_T Count
++ );
++
++/*******************************************************************************
++** gcSHADER_AddVariable
++********************************************************************************
++**
++** Add a variable to a gcSHADER object.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gctCONST_STRING Name
++** Name of the variable to add.
++**
++** gcSHADER_TYPE Type
++** Type of the variable to add.
++**
++** gctSIZE_T Length
++** Array length of the variable to add. 'Length' must be at least 1.
++**
++** gctUINT16 TempRegister
++** Temporary register index that holds the variable value.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gcSHADER_AddVariable(
++ IN gcSHADER Shader,
++ IN gctCONST_STRING Name,
++ IN gcSHADER_TYPE Type,
++ IN gctSIZE_T Length,
++ IN gctUINT16 TempRegister
++ );
++
++
++/*******************************************************************************
++** gcSHADER_AddVariableEx
++********************************************************************************
++**
++** Add a variable to a gcSHADER object.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gctCONST_STRING Name
++** Name of the variable to add.
++**
++** gcSHADER_TYPE Type
++** Type of the variable to add.
++**
++** gctSIZE_T Length
++** Array length of the variable to add. 'Length' must be at least 1.
++**
++** gctUINT16 TempRegister
++** Temporary register index that holds the variable value.
++**
++** gcSHADER_VAR_CATEGORY varCategory
++** Variable category, normal or struct.
++**
++** gctUINT16 numStructureElement
++** If struct, its element number.
++**
++** gctINT16 parent
++** If struct, parent index in gcSHADER.variables.
++**
++** gctINT16 prevSibling
++** If struct, previous sibling index in gcSHADER.variables.
++**
++** OUTPUT:
++**
++** gctINT16* ThisVarIndex
++** Returned value about variable index in gcSHADER.
++*/
++gceSTATUS
++gcSHADER_AddVariableEx(
++ IN gcSHADER Shader,
++ IN gctCONST_STRING Name,
++ IN gcSHADER_TYPE Type,
++ IN gctSIZE_T Length,
++ IN gctUINT16 TempRegister,
++ IN gcSHADER_VAR_CATEGORY varCategory,
++ IN gctUINT16 numStructureElement,
++ IN gctINT16 parent,
++ IN gctINT16 prevSibling,
++ OUT gctINT16* ThisVarIndex
++ );
++
++/*******************************************************************************
++** gcSHADER_UpdateVariable
++********************************************************************************
++**
++** Update a variable to a gcSHADER object.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gctUINT Index
++** Index of variable to retrieve.
++**
++** gceVARIABLE_UPDATE_FLAGS flag
++** Flag which property of variable will be updated.
++**
++** gctUINT newValue
++** New value to update.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gcSHADER_UpdateVariable(
++ IN gcSHADER Shader,
++ IN gctUINT Index,
++ IN gceVARIABLE_UPDATE_FLAGS flag,
++ IN gctUINT newValue
++ );
++
++/*******************************************************************************
++** gcSHADER_GetVariableCount
++********************************************************************************
++**
++** Get the number of variables for this shader.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Count
++** Pointer to a variable receiving the number of variables.
++*/
++gceSTATUS
++gcSHADER_GetVariableCount(
++ IN gcSHADER Shader,
++ OUT gctSIZE_T * Count
++ );
++
++/*******************************************************************************
++** gcSHADER_GetVariable
++********************************************************************************
++**
++** Get the gcVARIABLE object pointer for an indexed variable for this shader.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gctUINT Index
++** Index of variable to retrieve.
++**
++** OUTPUT:
++**
++** gcVARIABLE * Variable
++** Pointer to a variable receiving the gcVARIABLE object pointer.
++*/
++gceSTATUS
++gcSHADER_GetVariable(
++ IN gcSHADER Shader,
++ IN gctUINT Index,
++ OUT gcVARIABLE * Variable
++ );
++
++/*******************************************************************************
++** gcSHADER_GetVariableIndexingRange
++********************************************************************************
++**
++** Get the gcVARIABLE indexing range.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gcVARIABLE variable
++** Start variable.
++**
++** gctBOOL whole
++** Indicate whether maximum indexing range is queried
++**
++** OUTPUT:
++**
++** gctUINT *Start
++** Pointer to range start (temp register index).
++**
++** gctUINT *End
++** Pointer to range end (temp register index).
++*/
++gceSTATUS
++gcSHADER_GetVariableIndexingRange(
++ IN gcSHADER Shader,
++ IN gcVARIABLE variable,
++ IN gctBOOL whole,
++ OUT gctUINT *Start,
++ OUT gctUINT *End
++ );
++
++/*******************************************************************************
++** gcSHADER_AddOpcode
++********************************************************************************
++**
++** Add an opcode to a gcSHADER object.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gcSL_OPCODE Opcode
++** Opcode to add.
++**
++** gctUINT16 TempRegister
++** Temporary register index that acts as the target of the opcode.
++**
++** gctUINT8 Enable
++** Write enable bits for the temporary register that acts as the target
++** of the opcode.
++**
++** gcSL_FORMAT Format
++** Format of the temporary register.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gcSHADER_AddOpcode(
++ IN gcSHADER Shader,
++ IN gcSL_OPCODE Opcode,
++ IN gctUINT16 TempRegister,
++ IN gctUINT8 Enable,
++ IN gcSL_FORMAT Format
++ );
++
++gceSTATUS
++gcSHADER_AddOpcode2(
++ IN gcSHADER Shader,
++ IN gcSL_OPCODE Opcode,
++ IN gcSL_CONDITION Condition,
++ IN gctUINT16 TempRegister,
++ IN gctUINT8 Enable,
++ IN gcSL_FORMAT Format
++ );
++
++/*******************************************************************************
++** gcSHADER_AddOpcodeIndexed
++********************************************************************************
++**
++** Add an opcode to a gcSHADER object that writes to an dynamically indexed
++** target.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gcSL_OPCODE Opcode
++** Opcode to add.
++**
++** gctUINT16 TempRegister
++** Temporary register index that acts as the target of the opcode.
++**
++** gctUINT8 Enable
++** Write enable bits for the temporary register that acts as the
++** target of the opcode.
++**
++** gcSL_INDEXED Mode
++** Location of the dynamic index inside the temporary register. Valid
++** values can be:
++**
++** gcSL_INDEXED_X - Use x component of the temporary register.
++** gcSL_INDEXED_Y - Use y component of the temporary register.
++** gcSL_INDEXED_Z - Use z component of the temporary register.
++** gcSL_INDEXED_W - Use w component of the temporary register.
++**
++** gctUINT16 IndexRegister
++** Temporary register index that holds the dynamic index.
++**
++** gcSL_FORMAT Format
++** Format of the temporary register.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gcSHADER_AddOpcodeIndexed(
++ IN gcSHADER Shader,
++ IN gcSL_OPCODE Opcode,
++ IN gctUINT16 TempRegister,
++ IN gctUINT8 Enable,
++ IN gcSL_INDEXED Mode,
++ IN gctUINT16 IndexRegister,
++ IN gcSL_FORMAT Format
++ );
++
++/*******************************************************************************
++** gcSHADER_AddOpcodeConditionIndexed
++**
++** Add an opcode to a gcSHADER object that writes to an dynamically indexed
++** target.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gcSL_OPCODE Opcode
++** Opcode to add.
++**
++** gcSL_CONDITION Condition
++** Condition to check.
++**
++** gctUINT16 TempRegister
++** Temporary register index that acts as the target of the opcode.
++**
++** gctUINT8 Enable
++** Write enable bits for the temporary register that acts as the
++** target of the opcode.
++**
++** gcSL_INDEXED Indexed
++** Location of the dynamic index inside the temporary register. Valid
++** values can be:
++**
++** gcSL_INDEXED_X - Use x component of the temporary register.
++** gcSL_INDEXED_Y - Use y component of the temporary register.
++** gcSL_INDEXED_Z - Use z component of the temporary register.
++** gcSL_INDEXED_W - Use w component of the temporary register.
++**
++** gctUINT16 IndexRegister
++** Temporary register index that holds the dynamic index.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gcSHADER_AddOpcodeConditionIndexed(
++ IN gcSHADER Shader,
++ IN gcSL_OPCODE Opcode,
++ IN gcSL_CONDITION Condition,
++ IN gctUINT16 TempRegister,
++ IN gctUINT8 Enable,
++ IN gcSL_INDEXED Indexed,
++ IN gctUINT16 IndexRegister,
++ IN gcSL_FORMAT Format
++ );
++
++/*******************************************************************************
++** gcSHADER_AddOpcodeConditional
++********************************************************************************
++**
++** Add an conditional opcode to a gcSHADER object.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gcSL_OPCODE Opcode
++** Opcode to add.
++**
++** gcSL_CONDITION Condition
++** Condition that needs to evaluate to gcvTRUE in order for the opcode to
++** execute.
++**
++** gctUINT Label
++** Target label if 'Condition' evaluates to gcvTRUE.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gcSHADER_AddOpcodeConditional(
++ IN gcSHADER Shader,
++ IN gcSL_OPCODE Opcode,
++ IN gcSL_CONDITION Condition,
++ IN gctUINT Label
++ );
++
++/*******************************************************************************
++** gcSHADER_AddOpcodeConditionalFormatted
++**
++** Add an conditional jump or call opcode to a gcSHADER object.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gcSL_OPCODE Opcode
++** Opcode to add.
++**
++** gcSL_CONDITION Condition
++** Condition that needs to evaluate to gcvTRUE in order for the opcode to
++** execute.
++**
++** gcSL_FORMAT Format
++** Format of conditional operands
++**
++** gctUINT Label
++** Target label if 'Condition' evaluates to gcvTRUE.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gcSHADER_AddOpcodeConditionalFormatted(
++ IN gcSHADER Shader,
++ IN gcSL_OPCODE Opcode,
++ IN gcSL_CONDITION Condition,
++ IN gcSL_FORMAT Format,
++ IN gctUINT Label
++ );
++
++/*******************************************************************************
++** gcSHADER_AddOpcodeConditionalFormattedEnable
++**
++** Add an conditional jump or call opcode to a gcSHADER object.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gcSL_OPCODE Opcode
++** Opcode to add.
++**
++** gcSL_CONDITION Condition
++** Condition that needs to evaluate to gcvTRUE in order for the opcode to
++** execute.
++**
++** gcSL_FORMAT Format
++** Format of conditional operands
++**
++** gctUINT8 Enable
++** Write enable value for the target of the opcode.
++**
++** gctUINT Label
++** Target label if 'Condition' evaluates to gcvTRUE.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gcSHADER_AddOpcodeConditionalFormattedEnable(
++ IN gcSHADER Shader,
++ IN gcSL_OPCODE Opcode,
++ IN gcSL_CONDITION Condition,
++ IN gcSL_FORMAT Format,
++ IN gctUINT8 Enable,
++ IN gctUINT Label
++ );
++
++/*******************************************************************************
++** gcSHADER_AddLabel
++********************************************************************************
++**
++** Define a label at the current instruction of a gcSHADER object.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gctUINT Label
++** Label to define.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gcSHADER_AddLabel(
++ IN gcSHADER Shader,
++ IN gctUINT Label
++ );
++
++/*******************************************************************************
++** gcSHADER_AddSource
++********************************************************************************
++**
++** Add a source operand to a gcSHADER object.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gcSL_TYPE Type
++** Type of the source operand.
++**
++** gctUINT16 SourceIndex
++** Index of the source operand.
++**
++** gctUINT8 Swizzle
++** x, y, z, and w swizzle values packed into one 8-bit value.
++**
++** gcSL_FORMAT Format
++** Format of the source operand.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gcSHADER_AddSource(
++ IN gcSHADER Shader,
++ IN gcSL_TYPE Type,
++ IN gctUINT16 SourceIndex,
++ IN gctUINT8 Swizzle,
++ IN gcSL_FORMAT Format
++ );
++
++/*******************************************************************************
++** gcSHADER_AddSourceIndexed
++********************************************************************************
++**
++** Add a dynamically indexed source operand to a gcSHADER object.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gcSL_TYPE Type
++** Type of the source operand.
++**
++** gctUINT16 SourceIndex
++** Index of the source operand.
++**
++** gctUINT8 Swizzle
++** x, y, z, and w swizzle values packed into one 8-bit value.
++**
++** gcSL_INDEXED Mode
++** Addressing mode for the index.
++**
++** gctUINT16 IndexRegister
++** Temporary register index that holds the dynamic index.
++**
++** gcSL_FORMAT Format
++** Format of the source operand.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gcSHADER_AddSourceIndexed(
++ IN gcSHADER Shader,
++ IN gcSL_TYPE Type,
++ IN gctUINT16 SourceIndex,
++ IN gctUINT8 Swizzle,
++ IN gcSL_INDEXED Mode,
++ IN gctUINT16 IndexRegister,
++ IN gcSL_FORMAT Format
++ );
++
++/*******************************************************************************
++** gcSHADER_AddSourceAttribute
++********************************************************************************
++**
++** Add an attribute as a source operand to a gcSHADER object.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gcATTRIBUTE Attribute
++** Pointer to a gcATTRIBUTE object.
++**
++** gctUINT8 Swizzle
++** x, y, z, and w swizzle values packed into one 8-bit value.
++**
++** gctINT Index
++** Static index into the attribute in case the attribute is a matrix
++** or array.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gcSHADER_AddSourceAttribute(
++ IN gcSHADER Shader,
++ IN gcATTRIBUTE Attribute,
++ IN gctUINT8 Swizzle,
++ IN gctINT Index
++ );
++
++/*******************************************************************************
++** gcSHADER_AddSourceAttributeIndexed
++********************************************************************************
++**
++** Add an indexed attribute as a source operand to a gcSHADER object.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gcATTRIBUTE Attribute
++** Pointer to a gcATTRIBUTE object.
++**
++** gctUINT8 Swizzle
++** x, y, z, and w swizzle values packed into one 8-bit value.
++**
++** gctINT Index
++** Static index into the attribute in case the attribute is a matrix
++** or array.
++**
++** gcSL_INDEXED Mode
++** Addressing mode of the dynamic index.
++**
++** gctUINT16 IndexRegister
++** Temporary register index that holds the dynamic index.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gcSHADER_AddSourceAttributeIndexed(
++ IN gcSHADER Shader,
++ IN gcATTRIBUTE Attribute,
++ IN gctUINT8 Swizzle,
++ IN gctINT Index,
++ IN gcSL_INDEXED Mode,
++ IN gctUINT16 IndexRegister
++ );
++
++/*******************************************************************************
++** gcSHADER_AddSourceUniform
++********************************************************************************
++**
++** Add a uniform as a source operand to a gcSHADER object.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gcUNIFORM Uniform
++** Pointer to a gcUNIFORM object.
++**
++** gctUINT8 Swizzle
++** x, y, z, and w swizzle values packed into one 8-bit value.
++**
++** gctINT Index
++** Static index into the uniform in case the uniform is a matrix or
++** array.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gcSHADER_AddSourceUniform(
++ IN gcSHADER Shader,
++ IN gcUNIFORM Uniform,
++ IN gctUINT8 Swizzle,
++ IN gctINT Index
++ );
++
++/*******************************************************************************
++** gcSHADER_AddSourceUniformIndexed
++********************************************************************************
++**
++** Add an indexed uniform as a source operand to a gcSHADER object.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gcUNIFORM Uniform
++** Pointer to a gcUNIFORM object.
++**
++** gctUINT8 Swizzle
++** x, y, z, and w swizzle values packed into one 8-bit value.
++**
++** gctINT Index
++** Static index into the uniform in case the uniform is a matrix or
++** array.
++**
++** gcSL_INDEXED Mode
++** Addressing mode of the dynamic index.
++**
++** gctUINT16 IndexRegister
++** Temporary register index that holds the dynamic index.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gcSHADER_AddSourceUniformIndexed(
++ IN gcSHADER Shader,
++ IN gcUNIFORM Uniform,
++ IN gctUINT8 Swizzle,
++ IN gctINT Index,
++ IN gcSL_INDEXED Mode,
++ IN gctUINT16 IndexRegister
++ );
++
++gceSTATUS
++gcSHADER_AddSourceSamplerIndexed(
++ IN gcSHADER Shader,
++ IN gctUINT8 Swizzle,
++ IN gcSL_INDEXED Mode,
++ IN gctUINT16 IndexRegister
++ );
++
++gceSTATUS
++gcSHADER_AddSourceAttributeFormatted(
++ IN gcSHADER Shader,
++ IN gcATTRIBUTE Attribute,
++ IN gctUINT8 Swizzle,
++ IN gctINT Index,
++ IN gcSL_FORMAT Format
++ );
++
++gceSTATUS
++gcSHADER_AddSourceAttributeIndexedFormatted(
++ IN gcSHADER Shader,
++ IN gcATTRIBUTE Attribute,
++ IN gctUINT8 Swizzle,
++ IN gctINT Index,
++ IN gcSL_INDEXED Mode,
++ IN gctUINT16 IndexRegister,
++ IN gcSL_FORMAT Format
++ );
++
++gceSTATUS
++gcSHADER_AddSourceUniformFormatted(
++ IN gcSHADER Shader,
++ IN gcUNIFORM Uniform,
++ IN gctUINT8 Swizzle,
++ IN gctINT Index,
++ IN gcSL_FORMAT Format
++ );
++
++gceSTATUS
++gcSHADER_AddSourceUniformIndexedFormatted(
++ IN gcSHADER Shader,
++ IN gcUNIFORM Uniform,
++ IN gctUINT8 Swizzle,
++ IN gctINT Index,
++ IN gcSL_INDEXED Mode,
++ IN gctUINT16 IndexRegister,
++ IN gcSL_FORMAT Format
++ );
++
++gceSTATUS
++gcSHADER_AddSourceSamplerIndexedFormatted(
++ IN gcSHADER Shader,
++ IN gctUINT8 Swizzle,
++ IN gcSL_INDEXED Mode,
++ IN gctUINT16 IndexRegister,
++ IN gcSL_FORMAT Format
++ );
++
++/*******************************************************************************
++** gcSHADER_AddSourceConstant
++********************************************************************************
++**
++** Add a constant floating point value as a source operand to a gcSHADER
++** object.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gctFLOAT Constant
++** Floating point constant.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gcSHADER_AddSourceConstant(
++ IN gcSHADER Shader,
++ IN gctFLOAT Constant
++ );
++
++/*******************************************************************************
++** gcSHADER_AddSourceConstantFormatted
++********************************************************************************
++**
++** Add a constant value as a source operand to a gcSHADER
++** object.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** void * Constant
++** Pointer to constant.
++**
++** gcSL_FORMAT Format
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gcSHADER_AddSourceConstantFormatted(
++ IN gcSHADER Shader,
++ IN void *Constant,
++ IN gcSL_FORMAT Format
++ );
++
++/*******************************************************************************
++** gcSHADER_Pack
++********************************************************************************
++**
++** Pack a dynamically created gcSHADER object by trimming the allocated arrays
++** and resolving all the labeling.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gcSHADER_Pack(
++ IN gcSHADER Shader
++ );
++
++/*******************************************************************************
++** gcSHADER_SetOptimizationOption
++********************************************************************************
++**
++** Set optimization option of a gcSHADER object.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gctUINT OptimizationOption
++** Optimization option. Can be one of the following:
++**
++** 0 - No optimization.
++** 1 - Full optimization.
++** Other value - For optimizer testing.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gcSHADER_SetOptimizationOption(
++ IN gcSHADER Shader,
++ IN gctUINT OptimizationOption
++ );
++
++/*******************************************************************************
++** gcSHADER_ReallocateFunctions
++**
++** Reallocate an array of pointers to gcFUNCTION objects.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gctSIZE_T Count
++** Array count to reallocate. 'Count' must be at least 1.
++*/
++gceSTATUS
++gcSHADER_ReallocateFunctions(
++ IN gcSHADER Shader,
++ IN gctSIZE_T Count
++ );
++
++gceSTATUS
++gcSHADER_AddFunction(
++ IN gcSHADER Shader,
++ IN gctCONST_STRING Name,
++ OUT gcFUNCTION * Function
++ );
++
++gceSTATUS
++gcSHADER_ReallocateKernelFunctions(
++ IN gcSHADER Shader,
++ IN gctSIZE_T Count
++ );
++
++gceSTATUS
++gcSHADER_AddKernelFunction(
++ IN gcSHADER Shader,
++ IN gctCONST_STRING Name,
++ OUT gcKERNEL_FUNCTION * KernelFunction
++ );
++
++gceSTATUS
++gcSHADER_BeginFunction(
++ IN gcSHADER Shader,
++ IN gcFUNCTION Function
++ );
++
++gceSTATUS
++gcSHADER_EndFunction(
++ IN gcSHADER Shader,
++ IN gcFUNCTION Function
++ );
++
++gceSTATUS
++gcSHADER_BeginKernelFunction(
++ IN gcSHADER Shader,
++ IN gcKERNEL_FUNCTION KernelFunction
++ );
++
++gceSTATUS
++gcSHADER_EndKernelFunction(
++ IN gcSHADER Shader,
++ IN gcKERNEL_FUNCTION KernelFunction,
++ IN gctSIZE_T LocalMemorySize
++ );
++
++gceSTATUS
++gcSHADER_SetMaxKernelFunctionArgs(
++ IN gcSHADER Shader,
++ IN gctUINT32 MaxKernelFunctionArgs
++ );
++
++/*******************************************************************************
++** gcSHADER_SetConstantMemorySize
++**
++** Set the constant memory address space size of a gcSHADER object.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gctSIZE_T ConstantMemorySize
++** Constant memory size in bytes
++**
++** gctCHAR *ConstantMemoryBuffer
++** Constant memory buffer
++*/
++gceSTATUS
++gcSHADER_SetConstantMemorySize(
++ IN gcSHADER Shader,
++ IN gctSIZE_T ConstantMemorySize,
++ IN gctCHAR * ConstantMemoryBuffer
++ );
++
++/*******************************************************************************
++** gcSHADER_GetConstantMemorySize
++**
++** Set the constant memory address space size of a gcSHADER object.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** OUTPUT:
++**
++** gctSIZE_T * ConstantMemorySize
++** Pointer to a variable receiving constant memory size in bytes
++**
++** gctCHAR **ConstantMemoryBuffer.
++** Pointer to a variable for returned shader constant memory buffer.
++*/
++gceSTATUS
++gcSHADER_GetConstantMemorySize(
++ IN gcSHADER Shader,
++ OUT gctSIZE_T * ConstantMemorySize,
++ OUT gctCHAR ** ConstantMemoryBuffer
++ );
++
++/*******************************************************************************
++** gcSHADER_SetPrivateMemorySize
++**
++** Set the private memory address space size of a gcSHADER object.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gctSIZE_T PrivateMemorySize
++** Private memory size in bytes
++*/
++gceSTATUS
++gcSHADER_SetPrivateMemorySize(
++ IN gcSHADER Shader,
++ IN gctSIZE_T PrivateMemorySize
++ );
++
++/*******************************************************************************
++** gcSHADER_GetPrivateMemorySize
++**
++** Set the private memory address space size of a gcSHADER object.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** OUTPUT:
++**
++** gctSIZE_T * PrivateMemorySize
++** Pointer to a variable receiving private memory size in bytes
++*/
++gceSTATUS
++gcSHADER_GetPrivateMemorySize(
++ IN gcSHADER Shader,
++ OUT gctSIZE_T * PrivateMemorySize
++ );
++
++/*******************************************************************************
++** gcSHADER_SetLocalMemorySize
++**
++** Set the local memory address space size of a gcSHADER object.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gctSIZE_T LocalMemorySize
++** Local memory size in bytes
++*/
++gceSTATUS
++gcSHADER_SetLocalMemorySize(
++ IN gcSHADER Shader,
++ IN gctSIZE_T LocalMemorySize
++ );
++
++/*******************************************************************************
++** gcSHADER_GetLocalMemorySize
++**
++** Set the local memory address space size of a gcSHADER object.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** OUTPUT:
++**
++** gctSIZE_T * LocalMemorySize
++** Pointer to a variable receiving lcoal memory size in bytes
++*/
++gceSTATUS
++gcSHADER_GetLocalMemorySize(
++ IN gcSHADER Shader,
++ OUT gctSIZE_T * LocalMemorySize
++ );
++
++
++/*******************************************************************************
++** gcSHADER_CheckValidity
++**
++** Check validity for a gcSHADER object.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++*/
++gceSTATUS
++gcSHADER_CheckValidity(
++ IN gcSHADER Shader
++ );
++
++#if gcdUSE_WCLIP_PATCH
++gceSTATUS
++gcATTRIBUTE_IsPosition(
++ IN gcATTRIBUTE Attribute,
++ OUT gctBOOL * IsPosition
++ );
++#endif
++
++/*******************************************************************************
++** gcATTRIBUTE_GetType
++********************************************************************************
++**
++** Get the type and array length of a gcATTRIBUTE object.
++**
++** INPUT:
++**
++** gcATTRIBUTE Attribute
++** Pointer to a gcATTRIBUTE object.
++**
++** OUTPUT:
++**
++** gcSHADER_TYPE * Type
++** Pointer to a variable receiving the type of the attribute. 'Type'
++** can be gcvNULL, in which case no type will be returned.
++**
++** gctSIZE_T * ArrayLength
++** Pointer to a variable receiving the length of the array if the
++** attribute was declared as an array. If the attribute was not
++** declared as an array, the array length will be 1. 'ArrayLength' can
++** be gcvNULL, in which case no array length will be returned.
++*/
++gceSTATUS
++gcATTRIBUTE_GetType(
++ IN gcATTRIBUTE Attribute,
++ OUT gcSHADER_TYPE * Type,
++ OUT gctSIZE_T * ArrayLength
++ );
++
++/*******************************************************************************
++** gcATTRIBUTE_GetName
++********************************************************************************
++**
++** Get the name of a gcATTRIBUTE object.
++**
++** INPUT:
++**
++** gcATTRIBUTE Attribute
++** Pointer to a gcATTRIBUTE object.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Length
++** Pointer to a variable receiving the length of the attribute name.
++** 'Length' can be gcvNULL, in which case no length will be returned.
++**
++** gctCONST_STRING * Name
++** Pointer to a variable receiving the pointer to the attribute name.
++** 'Name' can be gcvNULL, in which case no name will be returned.
++*/
++gceSTATUS
++gcATTRIBUTE_GetName(
++ IN gcATTRIBUTE Attribute,
++ OUT gctSIZE_T * Length,
++ OUT gctCONST_STRING * Name
++ );
++
++/*******************************************************************************
++** gcATTRIBUTE_IsEnabled
++********************************************************************************
++**
++** Query the enabled state of a gcATTRIBUTE object.
++**
++** INPUT:
++**
++** gcATTRIBUTE Attribute
++** Pointer to a gcATTRIBUTE object.
++**
++** OUTPUT:
++**
++** gctBOOL * Enabled
++** Pointer to a variable receiving the enabled state of the attribute.
++*/
++gceSTATUS
++gcATTRIBUTE_IsEnabled(
++ IN gcATTRIBUTE Attribute,
++ OUT gctBOOL * Enabled
++ );
++
++gceSTATUS
++gcATTRIBUTE_GetIndex(
++ IN gcATTRIBUTE Attribute,
++ OUT gctUINT16 * Index
++ );
++
++/*******************************************************************************
++** gcUNIFORM_GetType
++********************************************************************************
++**
++** Get the type and array length of a gcUNIFORM object.
++**
++** INPUT:
++**
++** gcUNIFORM Uniform
++** Pointer to a gcUNIFORM object.
++**
++** OUTPUT:
++**
++** gcSHADER_TYPE * Type
++** Pointer to a variable receiving the type of the uniform. 'Type' can
++** be gcvNULL, in which case no type will be returned.
++**
++** gctSIZE_T * ArrayLength
++** Pointer to a variable receiving the length of the array if the
++** uniform was declared as an array. If the uniform was not declared
++** as an array, the array length will be 1. 'ArrayLength' can be gcvNULL,
++** in which case no array length will be returned.
++*/
++gceSTATUS
++gcUNIFORM_GetType(
++ IN gcUNIFORM Uniform,
++ OUT gcSHADER_TYPE * Type,
++ OUT gctSIZE_T * ArrayLength
++ );
++
++/*******************************************************************************
++** gcUNIFORM_GetTypeEx
++********************************************************************************
++**
++** Get the type and array length of a gcUNIFORM object.
++**
++** INPUT:
++**
++** gcUNIFORM Uniform
++** Pointer to a gcUNIFORM object.
++**
++** OUTPUT:
++**
++** gcSHADER_TYPE * Type
++** Pointer to a variable receiving the type of the uniform. 'Type' can
++** be gcvNULL, in which case no type will be returned.
++**
++** gcSHADER_PRECISION * Precision
++** Pointer to a variable receiving the precision of the uniform. 'Precision' can
++** be gcvNULL, in which case no type will be returned.
++**
++** gctSIZE_T * ArrayLength
++** Pointer to a variable receiving the length of the array if the
++** uniform was declared as an array. If the uniform was not declared
++** as an array, the array length will be 1. 'ArrayLength' can be gcvNULL,
++** in which case no array length will be returned.
++*/
++gceSTATUS
++gcUNIFORM_GetTypeEx(
++ IN gcUNIFORM Uniform,
++ OUT gcSHADER_TYPE * Type,
++ OUT gcSHADER_PRECISION * Precision,
++ OUT gctSIZE_T * ArrayLength
++ );
++
++/*******************************************************************************
++** gcUNIFORM_GetFlags
++********************************************************************************
++**
++** Get the flags of a gcUNIFORM object.
++**
++** INPUT:
++**
++** gcUNIFORM Uniform
++** Pointer to a gcUNIFORM object.
++**
++** OUTPUT:
++**
++** gceUNIFORM_FLAGS * Flags
++** Pointer to a variable receiving the flags of the uniform.
++**
++*/
++gceSTATUS
++gcUNIFORM_GetFlags(
++ IN gcUNIFORM Uniform,
++ OUT gceUNIFORM_FLAGS * Flags
++ );
++
++/*******************************************************************************
++** gcUNIFORM_SetFlags
++********************************************************************************
++**
++** Set the flags of a gcUNIFORM object.
++**
++** INPUT:
++**
++** gcUNIFORM Uniform
++** Pointer to a gcUNIFORM object.
++**
++** gceUNIFORM_FLAGS Flags
++** Flags of the uniform to be set.
++**
++** OUTPUT:
++** Nothing.
++**
++*/
++gceSTATUS
++gcUNIFORM_SetFlags(
++ IN gcUNIFORM Uniform,
++ IN gceUNIFORM_FLAGS Flags
++ );
++
++/*******************************************************************************
++** gcUNIFORM_GetName
++********************************************************************************
++**
++** Get the name of a gcUNIFORM object.
++**
++** INPUT:
++**
++** gcUNIFORM Uniform
++** Pointer to a gcUNIFORM object.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Length
++** Pointer to a variable receiving the length of the uniform name.
++** 'Length' can be gcvNULL, in which case no length will be returned.
++**
++** gctCONST_STRING * Name
++** Pointer to a variable receiving the pointer to the uniform name.
++** 'Name' can be gcvNULL, in which case no name will be returned.
++*/
++gceSTATUS
++gcUNIFORM_GetName(
++ IN gcUNIFORM Uniform,
++ OUT gctSIZE_T * Length,
++ OUT gctCONST_STRING * Name
++ );
++
++/*******************************************************************************
++** gcUNIFORM_GetSampler
++********************************************************************************
++**
++** Get the physical sampler number for a sampler gcUNIFORM object.
++**
++** INPUT:
++**
++** gcUNIFORM Uniform
++** Pointer to a gcUNIFORM object.
++**
++** OUTPUT:
++**
++** gctUINT32 * Sampler
++** Pointer to a variable receiving the physical sampler.
++*/
++gceSTATUS
++gcUNIFORM_GetSampler(
++ IN gcUNIFORM Uniform,
++ OUT gctUINT32 * Sampler
++ );
++
++gceSTATUS
++gcUNIFORM_GetIndex(
++ IN gcUNIFORM Uniform,
++ OUT gctUINT16 * Index
++ );
++
++/*******************************************************************************
++** gcUNIFORM_GetFormat
++**
++** Get the type and array length of a gcUNIFORM object.
++**
++** INPUT:
++**
++** gcUNIFORM Uniform
++** Pointer to a gcUNIFORM object.
++**
++** OUTPUT:
++**
++** gcSL_FORMAT * Format
++** Pointer to a variable receiving the format of element of the uniform.
++** 'Type' can be gcvNULL, in which case no type will be returned.
++**
++** gctBOOL * IsPointer
++** Pointer to a variable receiving the state wheter the uniform is a pointer.
++** 'IsPointer' can be gcvNULL, in which case no array length will be returned.
++*/
++gceSTATUS
++gcUNIFORM_GetFormat(
++ IN gcUNIFORM Uniform,
++ OUT gcSL_FORMAT * Format,
++ OUT gctBOOL * IsPointer
++ );
++
++/*******************************************************************************
++** gcUNIFORM_SetFormat
++**
++** Set the format and isPointer of a uniform.
++**
++** INPUT:
++**
++** gcUNIFORM Uniform
++** Pointer to a gcUNIFORM object.
++**
++** gcSL_FORMAT Format
++** Format of element of the uniform shaderType.
++**
++** gctBOOL IsPointer
++** Wheter the uniform is a pointer.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gcUNIFORM_SetFormat(
++ IN gcUNIFORM Uniform,
++ IN gcSL_FORMAT Format,
++ IN gctBOOL IsPointer
++ );
++
++/*******************************************************************************
++** gcUNIFORM_SetValue
++********************************************************************************
++**
++** Set the value of a uniform in integer.
++**
++** INPUT:
++**
++** gcUNIFORM Uniform
++** Pointer to a gcUNIFORM object.
++**
++** gctSIZE_T Count
++** Number of entries to program if the uniform has been declared as an
++** array.
++**
++** const gctINT * Value
++** Pointer to a buffer holding the integer values for the uniform.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gcUNIFORM_SetValue(
++ IN gcUNIFORM Uniform,
++ IN gctSIZE_T Count,
++ IN const gctINT * Value
++ );
++
++/*******************************************************************************
++** gcUNIFORM_SetValueX
++********************************************************************************
++**
++** Set the value of a uniform in fixed point.
++**
++** INPUT:
++**
++** gcUNIFORM Uniform
++** Pointer to a gcUNIFORM object.
++**
++** gctSIZE_T Count
++** Number of entries to program if the uniform has been declared as an
++** array.
++**
++** const gctFIXED_POINT * Value
++** Pointer to a buffer holding the fixed point values for the uniform.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gcUNIFORM_SetValueX(
++ IN gcUNIFORM Uniform,
++ IN gctSIZE_T Count,
++ IN gctFIXED_POINT * Value
++ );
++
++/*******************************************************************************
++** gcUNIFORM_SetValueF
++********************************************************************************
++**
++** Set the value of a uniform in floating point.
++**
++** INPUT:
++**
++** gcUNIFORM Uniform
++** Pointer to a gcUNIFORM object.
++**
++** gctSIZE_T Count
++** Number of entries to program if the uniform has been declared as an
++** array.
++**
++** const gctFLOAT * Value
++** Pointer to a buffer holding the floating point values for the
++** uniform.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gcUNIFORM_SetValueF(
++ IN gcUNIFORM Uniform,
++ IN gctSIZE_T Count,
++ IN const gctFLOAT * Value
++ );
++
++/*******************************************************************************
++** gcUNIFORM_ProgramF
++**
++** Set the value of a uniform in floating point.
++**
++** INPUT:
++**
++** gctUINT32 Address
++** Address of Uniform.
++**
++** gctSIZE_T Row/Col
++**
++** const gctFLOAT * Value
++** Pointer to a buffer holding the floating point values for the
++** uniform.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gcUNIFORM_ProgramF(
++ IN gctUINT32 Address,
++ IN gctSIZE_T Row,
++ IN gctSIZE_T Col,
++ IN const gctFLOAT * Value
++ );
++
++/*******************************************************************************
++** gcUNIFORM_GetModelViewProjMatrix
++********************************************************************************
++**
++** Get the value of uniform modelViewProjMatrix ID if present.
++**
++** INPUT:
++**
++** gcUNIFORM Uniform
++** Pointer to a gcUNIFORM object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gctUINT
++gcUNIFORM_GetModelViewProjMatrix(
++ IN gcUNIFORM Uniform
++ );
++
++/*******************************************************************************
++** gcOUTPUT_GetType
++********************************************************************************
++**
++** Get the type and array length of a gcOUTPUT object.
++**
++** INPUT:
++**
++** gcOUTPUT Output
++** Pointer to a gcOUTPUT object.
++**
++** OUTPUT:
++**
++** gcSHADER_TYPE * Type
++** Pointer to a variable receiving the type of the output. 'Type' can
++** be gcvNULL, in which case no type will be returned.
++**
++** gctSIZE_T * ArrayLength
++** Pointer to a variable receiving the length of the array if the
++** output was declared as an array. If the output was not declared
++** as an array, the array length will be 1. 'ArrayLength' can be gcvNULL,
++** in which case no array length will be returned.
++*/
++gceSTATUS
++gcOUTPUT_GetType(
++ IN gcOUTPUT Output,
++ OUT gcSHADER_TYPE * Type,
++ OUT gctSIZE_T * ArrayLength
++ );
++
++/*******************************************************************************
++** gcOUTPUT_GetIndex
++********************************************************************************
++**
++** Get the index of a gcOUTPUT object.
++**
++** INPUT:
++**
++** gcOUTPUT Output
++** Pointer to a gcOUTPUT object.
++**
++** OUTPUT:
++**
++** gctUINT * Index
++** Pointer to a variable receiving the temporary register index of the
++** output. 'Index' can be gcvNULL,. in which case no index will be
++** returned.
++*/
++gceSTATUS
++gcOUTPUT_GetIndex(
++ IN gcOUTPUT Output,
++ OUT gctUINT * Index
++ );
++
++/*******************************************************************************
++** gcOUTPUT_GetName
++********************************************************************************
++**
++** Get the name of a gcOUTPUT object.
++**
++** INPUT:
++**
++** gcOUTPUT Output
++** Pointer to a gcOUTPUT object.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Length
++** Pointer to a variable receiving the length of the output name.
++** 'Length' can be gcvNULL, in which case no length will be returned.
++**
++** gctCONST_STRING * Name
++** Pointer to a variable receiving the pointer to the output name.
++** 'Name' can be gcvNULL, in which case no name will be returned.
++*/
++gceSTATUS
++gcOUTPUT_GetName(
++ IN gcOUTPUT Output,
++ OUT gctSIZE_T * Length,
++ OUT gctCONST_STRING * Name
++ );
++
++/*******************************************************************************
++*********************************************************** F U N C T I O N S **
++*******************************************************************************/
++
++/*******************************************************************************
++** gcFUNCTION_ReallocateArguments
++**
++** Reallocate an array of gcsFUNCTION_ARGUMENT objects.
++**
++** INPUT:
++**
++** gcFUNCTION Function
++** Pointer to a gcFUNCTION object.
++**
++** gctSIZE_T Count
++** Array count to reallocate. 'Count' must be at least 1.
++*/
++gceSTATUS
++gcFUNCTION_ReallocateArguments(
++ IN gcFUNCTION Function,
++ IN gctSIZE_T Count
++ );
++
++gceSTATUS
++gcFUNCTION_AddArgument(
++ IN gcFUNCTION Function,
++ IN gctUINT16 TempIndex,
++ IN gctUINT8 Enable,
++ IN gctUINT8 Qualifier
++ );
++
++gceSTATUS
++gcFUNCTION_GetArgument(
++ IN gcFUNCTION Function,
++ IN gctUINT16 Index,
++ OUT gctUINT16_PTR Temp,
++ OUT gctUINT8_PTR Enable,
++ OUT gctUINT8_PTR Swizzle
++ );
++
++gceSTATUS
++gcFUNCTION_GetLabel(
++ IN gcFUNCTION Function,
++ OUT gctUINT_PTR Label
++ );
++
++/*******************************************************************************
++************************* K E R N E L P R O P E R T Y F U N C T I O N S **
++*******************************************************************************/
++/*******************************************************************************/
++gceSTATUS
++gcKERNEL_FUNCTION_AddKernelFunctionProperties(
++ IN gcKERNEL_FUNCTION KernelFunction,
++ IN gctINT propertyType,
++ IN gctSIZE_T propertySize,
++ IN gctINT * values
++ );
++
++gceSTATUS
++gcKERNEL_FUNCTION_GetPropertyCount(
++ IN gcKERNEL_FUNCTION KernelFunction,
++ OUT gctSIZE_T * Count
++ );
++
++gceSTATUS
++gcKERNEL_FUNCTION_GetProperty(
++ IN gcKERNEL_FUNCTION KernelFunction,
++ IN gctUINT Index,
++ OUT gctSIZE_T * propertySize,
++ OUT gctINT * propertyType,
++ OUT gctINT * propertyValues
++ );
++
++
++/*******************************************************************************
++*******************************I M A G E S A M P L E R F U N C T I O N S **
++*******************************************************************************/
++/*******************************************************************************
++** gcKERNEL_FUNCTION_ReallocateImageSamplers
++**
++** Reallocate an array of pointers to image sampler pair.
++**
++** INPUT:
++**
++** gcKERNEL_FUNCTION KernelFunction
++** Pointer to a gcKERNEL_FUNCTION object.
++**
++** gctSIZE_T Count
++** Array count to reallocate. 'Count' must be at least 1.
++*/
++gceSTATUS
++gcKERNEL_FUNCTION_ReallocateImageSamplers(
++ IN gcKERNEL_FUNCTION KernelFunction,
++ IN gctSIZE_T Count
++ );
++
++gceSTATUS
++gcKERNEL_FUNCTION_AddImageSampler(
++ IN gcKERNEL_FUNCTION KernelFunction,
++ IN gctUINT8 ImageNum,
++ IN gctBOOL IsConstantSamplerType,
++ IN gctUINT32 SamplerType
++ );
++
++gceSTATUS
++gcKERNEL_FUNCTION_GetImageSamplerCount(
++ IN gcKERNEL_FUNCTION KernelFunction,
++ OUT gctSIZE_T * Count
++ );
++
++gceSTATUS
++gcKERNEL_FUNCTION_GetImageSampler(
++ IN gcKERNEL_FUNCTION KernelFunction,
++ IN gctUINT Index,
++ OUT gctUINT8 *ImageNum,
++ OUT gctBOOL *IsConstantSamplerType,
++ OUT gctUINT32 *SamplerType
++ );
++
++/*******************************************************************************
++*********************************************K E R N E L F U N C T I O N S **
++*******************************************************************************/
++
++/*******************************************************************************
++** gcKERNEL_FUNCTION_ReallocateArguments
++**
++** Reallocate an array of gcsFUNCTION_ARGUMENT objects.
++**
++** INPUT:
++**
++** gcKERNEL_FUNCTION Function
++** Pointer to a gcKERNEL_FUNCTION object.
++**
++** gctSIZE_T Count
++** Array count to reallocate. 'Count' must be at least 1.
++*/
++gceSTATUS
++gcKERNEL_FUNCTION_ReallocateArguments(
++ IN gcKERNEL_FUNCTION Function,
++ IN gctSIZE_T Count
++ );
++
++gceSTATUS
++gcKERNEL_FUNCTION_AddArgument(
++ IN gcKERNEL_FUNCTION Function,
++ IN gctUINT16 TempIndex,
++ IN gctUINT8 Enable,
++ IN gctUINT8 Qualifier
++ );
++
++gceSTATUS
++gcKERNEL_FUNCTION_GetArgument(
++ IN gcKERNEL_FUNCTION Function,
++ IN gctUINT16 Index,
++ OUT gctUINT16_PTR Temp,
++ OUT gctUINT8_PTR Enable,
++ OUT gctUINT8_PTR Swizzle
++ );
++
++gceSTATUS
++gcKERNEL_FUNCTION_GetLabel(
++ IN gcKERNEL_FUNCTION Function,
++ OUT gctUINT_PTR Label
++ );
++
++gceSTATUS
++gcKERNEL_FUNCTION_GetName(
++ IN gcKERNEL_FUNCTION KernelFunction,
++ OUT gctSIZE_T * Length,
++ OUT gctCONST_STRING * Name
++ );
++
++gceSTATUS
++gcKERNEL_FUNCTION_ReallocateUniformArguments(
++ IN gcKERNEL_FUNCTION KernelFunction,
++ IN gctSIZE_T Count
++ );
++
++gceSTATUS
++gcKERNEL_FUNCTION_AddUniformArgument(
++ IN gcKERNEL_FUNCTION KernelFunction,
++ IN gctCONST_STRING Name,
++ IN gcSHADER_TYPE Type,
++ IN gctSIZE_T Length,
++ OUT gcUNIFORM * UniformArgument
++ );
++
++gceSTATUS
++gcKERNEL_FUNCTION_GetUniformArgumentCount(
++ IN gcKERNEL_FUNCTION KernelFunction,
++ OUT gctSIZE_T * Count
++ );
++
++gceSTATUS
++gcKERNEL_FUNCTION_GetUniformArgument(
++ IN gcKERNEL_FUNCTION KernelFunction,
++ IN gctUINT Index,
++ OUT gcUNIFORM * UniformArgument
++ );
++
++gceSTATUS
++gcKERNEL_FUNCTION_SetCodeEnd(
++ IN gcKERNEL_FUNCTION KernelFunction
++ );
++
++/*******************************************************************************
++** gcCompileShader
++********************************************************************************
++**
++** Compile a shader.
++**
++** INPUT:
++**
++** gcoOS Hal
++** Pointer to an gcoHAL object.
++**
++** gctINT ShaderType
++** Shader type to compile. Can be one of the following values:
++**
++** gcSHADER_TYPE_VERTEX
++** Compile a vertex shader.
++**
++** gcSHADER_TYPE_FRAGMENT
++** Compile a fragment shader.
++**
++** gctSIZE_T SourceSize
++** Size of the source buffer in bytes.
++**
++** gctCONST_STRING Source
++** Pointer to the buffer containing the shader source code.
++**
++** OUTPUT:
++**
++** gcSHADER * Binary
++** Pointer to a variable receiving the pointer to a gcSHADER object
++** containg the compiled shader code.
++**
++** gctSTRING * Log
++** Pointer to a variable receiving a string pointer containging the
++** compile log.
++*/
++gceSTATUS
++gcCompileShader(
++ IN gcoHAL Hal,
++ IN gctINT ShaderType,
++ IN gctSIZE_T SourceSize,
++ IN gctCONST_STRING Source,
++ OUT gcSHADER * Binary,
++ OUT gctSTRING * Log
++ );
++
++/*******************************************************************************
++** gcOptimizeShader
++********************************************************************************
++**
++** Optimize a shader.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object holding information about the compiled
++** shader.
++**
++** gctFILE LogFile
++** Pointer to an open FILE object.
++*/
++gceSTATUS
++gcOptimizeShader(
++ IN gcSHADER Shader,
++ IN gctFILE LogFile
++ );
++
++/*******************************************************************************
++** gcLinkShaders
++********************************************************************************
++**
++** Link two shaders and generate a harwdare specific state buffer by compiling
++** the compiler generated code through the resource allocator and code
++** generator.
++**
++** INPUT:
++**
++** gcSHADER VertexShader
++** Pointer to a gcSHADER object holding information about the compiled
++** vertex shader.
++**
++** gcSHADER FragmentShader
++** Pointer to a gcSHADER object holding information about the compiled
++** fragment shader.
++**
++** gceSHADER_FLAGS Flags
++** Compiler flags. Can be any of the following:
++**
++** gcvSHADER_DEAD_CODE - Dead code elimination.
++** gcvSHADER_RESOURCE_USAGE - Resource usage optimizaion.
++** gcvSHADER_OPTIMIZER - Full optimization.
++** gcvSHADER_USE_GL_Z - Use OpenGL ES Z coordinate.
++** gcvSHADER_USE_GL_POSITION - Use OpenGL ES gl_Position.
++** gcvSHADER_USE_GL_FACE - Use OpenGL ES gl_FaceForward.
++**
++** OUTPUT:
++**
++** gctSIZE_T * StateBufferSize
++** Pointer to a variable receicing the number of bytes in the buffer
++** returned in 'StateBuffer'.
++**
++** gctPOINTER * StateBuffer
++** Pointer to a variable receiving a buffer pointer that contains the
++** states required to download the shaders into the hardware.
++**
++** gcsHINT_PTR * Hints
++** Pointer to a variable receiving a gcsHINT structure pointer that
++** contains information required when loading the shader states.
++*/
++gceSTATUS
++gcLinkShaders(
++ IN gcSHADER VertexShader,
++ IN gcSHADER FragmentShader,
++ IN gceSHADER_FLAGS Flags,
++ OUT gctSIZE_T * StateBufferSize,
++ OUT gctPOINTER * StateBuffer,
++ OUT gcsHINT_PTR * Hints,
++ OUT gcMACHINECODE_PTR *ppVsMachineCode,
++ OUT gcMACHINECODE_PTR *ppFsMachineCode
++ );
++
++/*******************************************************************************
++** gcLoadShaders
++********************************************************************************
++**
++** Load a pre-compiled and pre-linked shader program into the hardware.
++**
++** INPUT:
++**
++** gcoHAL Hal
++** Pointer to a gcoHAL object.
++**
++** gctSIZE_T StateBufferSize
++** The number of bytes in the 'StateBuffer'.
++**
++** gctPOINTER StateBuffer
++** Pointer to the states that make up the shader program.
++**
++** gcsHINT_PTR Hints
++** Pointer to a gcsHINT structure that contains information required
++** when loading the shader states.
++*/
++gceSTATUS
++gcLoadShaders(
++ IN gcoHAL Hal,
++ IN gctSIZE_T StateBufferSize,
++ IN gctPOINTER StateBuffer,
++ IN gcsHINT_PTR Hints
++ );
++
++gceSTATUS
++gcRecompileShaders(
++ IN gcoHAL Hal,
++ IN gcMACHINECODE_PTR pVsMachineCode,
++ IN gcMACHINECODE_PTR pPsMachineCode,
++ /*Recompile variables*/
++ IN OUT gctPOINTER *ppRecompileStateBuffer,
++ IN OUT gctSIZE_T *pRecompileStateBufferSize,
++ IN OUT gcsHINT_PTR *ppRecompileHints,
++ /* natvie state*/
++ IN gctPOINTER pNativeStateBuffer,
++ IN gctSIZE_T nativeStateBufferSize,
++ IN gcsHINT_PTR pNativeHints,
++ /* npt info */
++ IN gctUINT32 Samplers,
++ IN gctUINT32 *SamplerWrapS,
++ IN gctUINT32 *SamplerWrapT
++ );
++
++gceSTATUS
++gcRecompileDepthBias(
++ IN gcoHAL Hal,
++ IN gcMACHINECODE_PTR pVsMachineCode,
++ /*Recompile variables*/
++ IN OUT gctPOINTER *ppRecompileStateBuffer,
++ IN OUT gctSIZE_T *pRecompileStateBufferSize,
++ IN OUT gcsHINT_PTR *ppRecompileHints,
++ /* natvie state*/
++ IN gctPOINTER pNativeStateBuffer,
++ IN gctSIZE_T nativeStateBufferSize,
++ IN gcsHINT_PTR pNativeHints,
++ OUT gctINT * uniformAddr,
++ OUT gctINT * uniformChannel
++ );
++
++/*******************************************************************************
++** gcSaveProgram
++********************************************************************************
++**
++** Save pre-compiled shaders and pre-linked programs to a binary file.
++**
++** INPUT:
++**
++** gcSHADER VertexShader
++** Pointer to vertex shader object.
++**
++** gcSHADER FragmentShader
++** Pointer to fragment shader object.
++**
++** gctSIZE_T ProgramBufferSize
++** Number of bytes in 'ProgramBuffer'.
++**
++** gctPOINTER ProgramBuffer
++** Pointer to buffer containing the program states.
++**
++** gcsHINT_PTR Hints
++** Pointer to HINTS structure for program states.
++**
++** OUTPUT:
++**
++** gctPOINTER * Binary
++** Pointer to a variable receiving the binary data to be saved.
++**
++** gctSIZE_T * BinarySize
++** Pointer to a variable receiving the number of bytes inside 'Binary'.
++*/
++gceSTATUS
++gcSaveProgram(
++ IN gcSHADER VertexShader,
++ IN gcSHADER FragmentShader,
++ IN gctSIZE_T ProgramBufferSize,
++ IN gctPOINTER ProgramBuffer,
++ IN gcsHINT_PTR Hints,
++ OUT gctPOINTER * Binary,
++ OUT gctSIZE_T * BinarySize
++ );
++
++/*******************************************************************************
++** gcLoadProgram
++********************************************************************************
++**
++** Load pre-compiled shaders and pre-linked programs from a binary file.
++**
++** INPUT:
++**
++** gctPOINTER Binary
++** Pointer to the binary data loaded.
++**
++** gctSIZE_T BinarySize
++** Number of bytes in 'Binary'.
++**
++** OUTPUT:
++**
++** gcSHADER VertexShader
++** Pointer to a vertex shader object.
++**
++** gcSHADER FragmentShader
++** Pointer to a fragment shader object.
++**
++** gctSIZE_T * ProgramBufferSize
++** Pointer to a variable receicing the number of bytes in the buffer
++** returned in 'ProgramBuffer'.
++**
++** gctPOINTER * ProgramBuffer
++** Pointer to a variable receiving a buffer pointer that contains the
++** states required to download the shaders into the hardware.
++**
++** gcsHINT_PTR * Hints
++** Pointer to a variable receiving a gcsHINT structure pointer that
++** contains information required when loading the shader states.
++*/
++gceSTATUS
++gcLoadProgram(
++ IN gctPOINTER Binary,
++ IN gctSIZE_T BinarySize,
++ OUT gcSHADER VertexShader,
++ OUT gcSHADER FragmentShader,
++ OUT gctSIZE_T * ProgramBufferSize,
++ OUT gctPOINTER * ProgramBuffer,
++ OUT gcsHINT_PTR * Hints
++ );
++
++/*******************************************************************************
++** gcCompileKernel
++********************************************************************************
++**
++** Compile a OpenCL kernel shader.
++**
++** INPUT:
++**
++** gcoOS Hal
++** Pointer to an gcoHAL object.
++**
++** gctSIZE_T SourceSize
++** Size of the source buffer in bytes.
++**
++** gctCONST_STRING Source
++** Pointer to the buffer containing the shader source code.
++**
++** OUTPUT:
++**
++** gcSHADER * Binary
++** Pointer to a variable receiving the pointer to a gcSHADER object
++** containg the compiled shader code.
++**
++** gctSTRING * Log
++** Pointer to a variable receiving a string pointer containging the
++** compile log.
++*/
++gceSTATUS
++gcCompileKernel(
++ IN gcoHAL Hal,
++ IN gctSIZE_T SourceSize,
++ IN gctCONST_STRING Source,
++ IN gctCONST_STRING Options,
++ OUT gcSHADER * Binary,
++ OUT gctSTRING * Log
++ );
++
++/*******************************************************************************
++** gcLinkKernel
++********************************************************************************
++**
++** Link OpenCL kernel and generate a harwdare specific state buffer by compiling
++** the compiler generated code through the resource allocator and code
++** generator.
++**
++** INPUT:
++**
++** gcSHADER Kernel
++** Pointer to a gcSHADER object holding information about the compiled
++** OpenCL kernel.
++**
++** gceSHADER_FLAGS Flags
++** Compiler flags. Can be any of the following:
++**
++** gcvSHADER_DEAD_CODE - Dead code elimination.
++** gcvSHADER_RESOURCE_USAGE - Resource usage optimizaion.
++** gcvSHADER_OPTIMIZER - Full optimization.
++** gcvSHADER_USE_GL_Z - Use OpenGL ES Z coordinate.
++** gcvSHADER_USE_GL_POSITION - Use OpenGL ES gl_Position.
++** gcvSHADER_USE_GL_FACE - Use OpenGL ES gl_FaceForward.
++**
++** OUTPUT:
++**
++** gctSIZE_T * StateBufferSize
++** Pointer to a variable receiving the number of bytes in the buffer
++** returned in 'StateBuffer'.
++**
++** gctPOINTER * StateBuffer
++** Pointer to a variable receiving a buffer pointer that contains the
++** states required to download the shaders into the hardware.
++**
++** gcsHINT_PTR * Hints
++** Pointer to a variable receiving a gcsHINT structure pointer that
++** contains information required when loading the shader states.
++*/
++gceSTATUS
++gcLinkKernel(
++ IN gcSHADER Kernel,
++ IN gceSHADER_FLAGS Flags,
++ OUT gctSIZE_T * StateBufferSize,
++ OUT gctPOINTER * StateBuffer,
++ OUT gcsHINT_PTR * Hints
++ );
++
++/*******************************************************************************
++** gcLoadKernel
++********************************************************************************
++**
++** Load a pre-compiled and pre-linked kernel program into the hardware.
++**
++** INPUT:
++**
++** gctSIZE_T StateBufferSize
++** The number of bytes in the 'StateBuffer'.
++**
++** gctPOINTER StateBuffer
++** Pointer to the states that make up the shader program.
++**
++** gcsHINT_PTR Hints
++** Pointer to a gcsHINT structure that contains information required
++** when loading the shader states.
++*/
++gceSTATUS
++gcLoadKernel(
++ IN gctSIZE_T StateBufferSize,
++ IN gctPOINTER StateBuffer,
++ IN gcsHINT_PTR Hints
++ );
++
++gceSTATUS
++gcInvokeThreadWalker(
++ IN gcsTHREAD_WALKER_INFO_PTR Info
++ );
++
++void
++gcTYPE_GetTypeInfo(
++ IN gcSHADER_TYPE Type,
++ OUT gctINT * Components,
++ OUT gctINT * Rows,
++ OUT gctCONST_STRING * Name
++ );
++
++gctBOOL
++gcOPT_doVaryingPackingForShader(
++ IN gcSHADER Shader
++ );
++
++gceSTATUS
++gcSHADER_PatchNPOTForMachineCode(
++ IN gcSHADER_KIND shaderType,
++ IN gcMACHINECODE_PTR pMachineCode,
++ IN gcNPOT_PATCH_PARAM_PTR pPatchParam,
++ IN gctUINT countOfPatchParam,
++ IN gctUINT hwSupportedInstCount,
++ OUT gctPOINTER* ppCmdBuffer,
++ OUT gctUINT32* pByteSizeOfCmdBuffer,
++ IN OUT gcsHINT_PTR pHints /* User needs copy original hints to this one, then passed this one in */
++ );
++
++gceSTATUS
++gcSHADER_PatchZBiasForMachineCodeVS(
++ IN gcMACHINECODE_PTR pMachineCode,
++ IN OUT gcZBIAS_PATCH_PARAM_PTR pPatchParam,
++ IN gctUINT hwSupportedInstCount,
++ OUT gctPOINTER* ppCmdBuffer,
++ OUT gctUINT32* pByteSizeOfCmdBuffer,
++ IN OUT gcsHINT_PTR pHints /* User needs copy original hints to this one, then passed this one in */
++ );
++
++gceSTATUS
++gcSHADER_InsertList(
++ IN gcSHADER Shader,
++ IN gcSHADER_LIST * Root,
++ IN gctINT Index,
++ IN gctINT Data0,
++ IN gctINT Data1
++ );
++
++gceSTATUS
++gcSHADER_UpdateList(
++ IN gcSHADER Shader,
++ IN gcSHADER_LIST Root,
++ IN gctINT Index,
++ IN gctINT NewIndex
++ );
++
++gceSTATUS
++gcSHADER_DeleteList(
++ IN gcSHADER Shader,
++ IN gcSHADER_LIST * Root,
++ IN gctINT Index
++ );
++
++gceSTATUS
++gcSHADER_FindList(
++ IN gcSHADER Shader,
++ IN gcSHADER_LIST Root,
++ IN gctINT Index,
++ IN gcSHADER_LIST * List
++ );
++
++gceSTATUS
++gcSHADER_InsertWClipList(
++ IN gcSHADER Shader,
++ IN gctINT Index,
++ IN gctINT Data0,
++ IN gctINT Data1
++ );
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* VIVANTE_NO_3D */
++#endif /* __gc_hal_compiler_h_ */
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_driver.h linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_driver.h
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_driver.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_driver.h 2015-07-27 23:13:06.210822785 +0200
+@@ -0,0 +1,1051 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_driver_h_
++#define __gc_hal_driver_h_
++
++#include "gc_hal_enum.h"
++#include "gc_hal_types.h"
++
++#if gcdENABLE_VG
++#include "gc_hal_driver_vg.h"
++#endif
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/******************************************************************************\
++******************************* I/O Control Codes ******************************
++\******************************************************************************/
++
++#define gcvHAL_CLASS "galcore"
++#define IOCTL_GCHAL_INTERFACE 30000
++#define IOCTL_GCHAL_KERNEL_INTERFACE 30001
++#define IOCTL_GCHAL_TERMINATE 30002
++
++/******************************************************************************\
++********************************* Command Codes ********************************
++\******************************************************************************/
++
++typedef enum _gceHAL_COMMAND_CODES
++{
++ /* Generic query. */
++ gcvHAL_QUERY_VIDEO_MEMORY,
++ gcvHAL_QUERY_CHIP_IDENTITY,
++
++ /* Contiguous memory. */
++ gcvHAL_ALLOCATE_NON_PAGED_MEMORY,
++ gcvHAL_FREE_NON_PAGED_MEMORY,
++ gcvHAL_ALLOCATE_CONTIGUOUS_MEMORY,
++ gcvHAL_FREE_CONTIGUOUS_MEMORY,
++
++ /* Video memory allocation. */
++ gcvHAL_ALLOCATE_VIDEO_MEMORY, /* Enforced alignment. */
++ gcvHAL_ALLOCATE_LINEAR_VIDEO_MEMORY, /* No alignment. */
++ gcvHAL_FREE_VIDEO_MEMORY,
++
++ /* Physical-to-logical mapping. */
++ gcvHAL_MAP_MEMORY,
++ gcvHAL_UNMAP_MEMORY,
++
++ /* Logical-to-physical mapping. */
++ gcvHAL_MAP_USER_MEMORY,
++ gcvHAL_UNMAP_USER_MEMORY,
++
++ /* Surface lock/unlock. */
++ gcvHAL_LOCK_VIDEO_MEMORY,
++ gcvHAL_UNLOCK_VIDEO_MEMORY,
++
++ /* Event queue. */
++ gcvHAL_EVENT_COMMIT,
++
++ gcvHAL_USER_SIGNAL,
++ gcvHAL_SIGNAL,
++ gcvHAL_WRITE_DATA,
++
++ gcvHAL_COMMIT,
++ gcvHAL_STALL,
++
++ gcvHAL_READ_REGISTER,
++ gcvHAL_WRITE_REGISTER,
++
++ gcvHAL_GET_PROFILE_SETTING,
++ gcvHAL_SET_PROFILE_SETTING,
++
++ gcvHAL_READ_ALL_PROFILE_REGISTERS,
++ gcvHAL_PROFILE_REGISTERS_2D,
++#if VIVANTE_PROFILER_PERDRAW
++ gcvHAL_READ_PROFILER_REGISTER_SETTING,
++#endif
++
++ /* Power management. */
++ gcvHAL_SET_POWER_MANAGEMENT_STATE,
++ gcvHAL_QUERY_POWER_MANAGEMENT_STATE,
++
++ gcvHAL_GET_BASE_ADDRESS,
++
++ gcvHAL_SET_IDLE, /* reserved */
++
++ /* Queries. */
++ gcvHAL_QUERY_KERNEL_SETTINGS,
++
++ /* Reset. */
++ gcvHAL_RESET,
++
++ /* Map physical address into handle. */
++ gcvHAL_MAP_PHYSICAL,
++
++ /* Debugger stuff. */
++ gcvHAL_DEBUG,
++
++ /* Cache stuff. */
++ gcvHAL_CACHE,
++
++ /* TimeStamp */
++ gcvHAL_TIMESTAMP,
++
++ /* Database. */
++ gcvHAL_DATABASE,
++
++ /* Version. */
++ gcvHAL_VERSION,
++
++ /* Chip info */
++ gcvHAL_CHIP_INFO,
++
++ /* Process attaching/detaching. */
++ gcvHAL_ATTACH,
++ gcvHAL_DETACH,
++
++ /* Composition. */
++ gcvHAL_COMPOSE,
++
++ /* Set timeOut value */
++ gcvHAL_SET_TIMEOUT,
++
++ /* Frame database. */
++ gcvHAL_GET_FRAME_INFO,
++
++ /* Shared info for each process */
++ gcvHAL_GET_SHARED_INFO,
++ gcvHAL_SET_SHARED_INFO,
++ gcvHAL_QUERY_COMMAND_BUFFER,
++
++ gcvHAL_COMMIT_DONE,
++
++ /* GPU and event dump */
++ gcvHAL_DUMP_GPU_STATE,
++ gcvHAL_DUMP_EVENT,
++
++ /* Virtual command buffer. */
++ gcvHAL_ALLOCATE_VIRTUAL_COMMAND_BUFFER,
++ gcvHAL_FREE_VIRTUAL_COMMAND_BUFFER,
++
++ /* FSCALE_VAL. */
++ gcvHAL_SET_FSCALE_VALUE,
++ gcvHAL_GET_FSCALE_VALUE,
++
++ /* Reset time stamp. */
++ gcvHAL_QUERY_RESET_TIME_STAMP,
++
++ /* Sync point operations. */
++ gcvHAL_SYNC_POINT,
++
++ /* Create native fence and return its fd. */
++ gcvHAL_CREATE_NATIVE_FENCE,
++
++ /* Video memory database */
++ gcvHAL_VIDMEM_DATABASE,
++}
++gceHAL_COMMAND_CODES;
++
++/******************************************************************************\
++****************************** Interface Structure *****************************
++\******************************************************************************/
++
++#define gcdMAX_PROFILE_FILE_NAME 128
++
++/* Kernel settings. */
++typedef struct _gcsKERNEL_SETTINGS
++{
++ /* Used RealTime signal between kernel and user. */
++ gctINT signal;
++}
++gcsKERNEL_SETTINGS;
++
++
++/* gcvHAL_QUERY_CHIP_IDENTITY */
++typedef struct _gcsHAL_QUERY_CHIP_IDENTITY * gcsHAL_QUERY_CHIP_IDENTITY_PTR;
++typedef struct _gcsHAL_QUERY_CHIP_IDENTITY
++{
++
++ /* Chip model. */
++ gceCHIPMODEL chipModel;
++
++ /* Revision value.*/
++ gctUINT32 chipRevision;
++
++ /* Supported feature fields. */
++ gctUINT32 chipFeatures;
++
++ /* Supported minor feature fields. */
++ gctUINT32 chipMinorFeatures;
++
++ /* Supported minor feature 1 fields. */
++ gctUINT32 chipMinorFeatures1;
++
++ /* Supported minor feature 2 fields. */
++ gctUINT32 chipMinorFeatures2;
++
++ /* Supported minor feature 3 fields. */
++ gctUINT32 chipMinorFeatures3;
++
++ /* Supported minor feature 4 fields. */
++ gctUINT32 chipMinorFeatures4;
++
++ /* Number of streams supported. */
++ gctUINT32 streamCount;
++
++ /* Total number of temporary registers per thread. */
++ gctUINT32 registerMax;
++
++ /* Maximum number of threads. */
++ gctUINT32 threadCount;
++
++ /* Number of shader cores. */
++ gctUINT32 shaderCoreCount;
++
++ /* Size of the vertex cache. */
++ gctUINT32 vertexCacheSize;
++
++ /* Number of entries in the vertex output buffer. */
++ gctUINT32 vertexOutputBufferSize;
++
++ /* Number of pixel pipes. */
++ gctUINT32 pixelPipes;
++
++ /* Number of instructions. */
++ gctUINT32 instructionCount;
++
++ /* Number of constants. */
++ gctUINT32 numConstants;
++
++ /* Buffer size */
++ gctUINT32 bufferSize;
++
++ /* Number of varyings */
++ gctUINT32 varyingsCount;
++
++ /* Supertile layout style in hardware */
++ gctUINT32 superTileMode;
++
++ /* Special control bits for 2D chip. */
++ gctUINT32 chip2DControl;
++}
++gcsHAL_QUERY_CHIP_IDENTITY;
++
++/* gcvHAL_COMPOSE. */
++typedef struct _gcsHAL_COMPOSE * gcsHAL_COMPOSE_PTR;
++typedef struct _gcsHAL_COMPOSE
++{
++ /* Composition state buffer. */
++ gctUINT64 physical;
++ gctUINT64 logical;
++ gctUINT offset;
++ gctUINT size;
++
++ /* Composition end signal. */
++ gctUINT64 process;
++ gctUINT64 signal;
++
++ /* User signals. */
++ gctUINT64 userProcess;
++ gctUINT64 userSignal1;
++ gctUINT64 userSignal2;
++
++#if defined(__QNXNTO__)
++ /* Client pulse side-channel connection ID. */
++ gctINT32 coid;
++
++ /* Set by server. */
++ gctINT32 rcvid;
++#endif
++}
++gcsHAL_COMPOSE;
++
++
++typedef struct _gcsHAL_INTERFACE
++{
++ /* Command code. */
++ gceHAL_COMMAND_CODES command;
++
++ /* Hardware type. */
++ gceHARDWARE_TYPE hardwareType;
++
++ /* Status value. */
++ gceSTATUS status;
++
++ /* Handle to this interface channel. */
++ gctUINT64 handle;
++
++ /* Pid of the client. */
++ gctUINT32 pid;
++
++ /* Union of command structures. */
++ union _u
++ {
++ /* gcvHAL_GET_BASE_ADDRESS */
++ struct _gcsHAL_GET_BASE_ADDRESS
++ {
++ /* Physical memory address of internal memory. */
++ OUT gctUINT32 baseAddress;
++ }
++ GetBaseAddress;
++
++ /* gcvHAL_QUERY_VIDEO_MEMORY */
++ struct _gcsHAL_QUERY_VIDEO_MEMORY
++ {
++ /* Physical memory address of internal memory. Just a name. */
++ OUT gctUINT32 internalPhysical;
++
++ /* Size in bytes of internal memory. */
++ OUT gctUINT64 internalSize;
++
++ /* Physical memory address of external memory. Just a name. */
++ OUT gctUINT32 externalPhysical;
++
++ /* Size in bytes of external memory.*/
++ OUT gctUINT64 externalSize;
++
++ /* Physical memory address of contiguous memory. Just a name. */
++ OUT gctUINT32 contiguousPhysical;
++
++ /* Size in bytes of contiguous memory.*/
++ OUT gctUINT64 contiguousSize;
++ }
++ QueryVideoMemory;
++
++ /* gcvHAL_QUERY_CHIP_IDENTITY */
++ gcsHAL_QUERY_CHIP_IDENTITY QueryChipIdentity;
++
++ /* gcvHAL_MAP_MEMORY */
++ struct _gcsHAL_MAP_MEMORY
++ {
++ /* Physical memory address to map. Just a name on Linux/Qnx. */
++ IN gctUINT32 physical;
++
++ /* Number of bytes in physical memory to map. */
++ IN gctUINT64 bytes;
++
++ /* Address of mapped memory. */
++ OUT gctUINT64 logical;
++ }
++ MapMemory;
++
++ /* gcvHAL_UNMAP_MEMORY */
++ struct _gcsHAL_UNMAP_MEMORY
++ {
++ /* Physical memory address to unmap. Just a name on Linux/Qnx. */
++ IN gctUINT32 physical;
++
++ /* Number of bytes in physical memory to unmap. */
++ IN gctUINT64 bytes;
++
++ /* Address of mapped memory to unmap. */
++ IN gctUINT64 logical;
++ }
++ UnmapMemory;
++
++ /* gcvHAL_ALLOCATE_LINEAR_VIDEO_MEMORY */
++ struct _gcsHAL_ALLOCATE_LINEAR_VIDEO_MEMORY
++ {
++ /* Number of bytes to allocate. */
++ IN OUT gctUINT bytes;
++
++ /* Buffer alignment. */
++ IN gctUINT alignment;
++
++ /* Type of allocation. */
++ IN gceSURF_TYPE type;
++
++ /* Memory pool to allocate from. */
++ IN OUT gcePOOL pool;
++
++ /* Allocated video memory in gcuVIDMEM_NODE. */
++ OUT gctUINT64 node;
++ }
++ AllocateLinearVideoMemory;
++
++ /* gcvHAL_ALLOCATE_VIDEO_MEMORY */
++ struct _gcsHAL_ALLOCATE_VIDEO_MEMORY
++ {
++ /* Width of rectangle to allocate. */
++ IN OUT gctUINT width;
++
++ /* Height of rectangle to allocate. */
++ IN OUT gctUINT height;
++
++ /* Depth of rectangle to allocate. */
++ IN gctUINT depth;
++
++ /* Format rectangle to allocate in gceSURF_FORMAT. */
++ IN gceSURF_FORMAT format;
++
++ /* Type of allocation. */
++ IN gceSURF_TYPE type;
++
++ /* Memory pool to allocate from. */
++ IN OUT gcePOOL pool;
++
++ /* Allocated video memory in gcuVIDMEM_NODE. */
++ OUT gctUINT64 node;
++ }
++ AllocateVideoMemory;
++
++ /* gcvHAL_FREE_VIDEO_MEMORY */
++ struct _gcsHAL_FREE_VIDEO_MEMORY
++ {
++ /* Allocated video memory in gcuVIDMEM_NODE. */
++ IN gctUINT64 node;
++
++#ifdef __QNXNTO__
++/* TODO: This is part of the unlock - why is it here? */
++ /* Mapped logical address to unmap in user space. */
++ OUT gctUINT64 memory;
++
++ /* Number of bytes to allocated. */
++ OUT gctUINT64 bytes;
++#endif
++ }
++ FreeVideoMemory;
++
++ /* gcvHAL_LOCK_VIDEO_MEMORY */
++ struct _gcsHAL_LOCK_VIDEO_MEMORY
++ {
++ /* Allocated video memory gcuVIDMEM_NODE gcuVIDMEM_NODE. */
++ IN gctUINT64 node;
++
++ /* Cache configuration. */
++ /* Only gcvPOOL_CONTIGUOUS and gcvPOOL_VIRUTAL
++ ** can be configured */
++ IN gctBOOL cacheable;
++
++ /* Hardware specific address. */
++ OUT gctUINT32 address;
++
++ /* Mapped logical address. */
++ OUT gctUINT64 memory;
++ }
++ LockVideoMemory;
++
++ /* gcvHAL_UNLOCK_VIDEO_MEMORY */
++ struct _gcsHAL_UNLOCK_VIDEO_MEMORY
++ {
++ /* Allocated video memory in gcuVIDMEM_NODE. */
++ IN gctUINT64 node;
++
++ /* Type of surface. */
++ IN gceSURF_TYPE type;
++
++ /* Flag to unlock surface asynchroneously. */
++ IN OUT gctBOOL asynchroneous;
++ }
++ UnlockVideoMemory;
++
++ /* gcvHAL_ALLOCATE_NON_PAGED_MEMORY */
++ struct _gcsHAL_ALLOCATE_NON_PAGED_MEMORY
++ {
++ /* Number of bytes to allocate. */
++ IN OUT gctUINT64 bytes;
++
++ /* Physical address of allocation. Just a name. */
++ OUT gctUINT32 physical;
++
++ /* Logical address of allocation. */
++ OUT gctUINT64 logical;
++ }
++ AllocateNonPagedMemory;
++
++ /* gcvHAL_FREE_NON_PAGED_MEMORY */
++ struct _gcsHAL_FREE_NON_PAGED_MEMORY
++ {
++ /* Number of bytes allocated. */
++ IN gctUINT64 bytes;
++
++ /* Physical address of allocation. Just a name. */
++ IN gctUINT32 physical;
++
++ /* Logical address of allocation. */
++ IN gctUINT64 logical;
++ }
++ FreeNonPagedMemory;
++
++ /* gcvHAL_ALLOCATE_NON_PAGED_MEMORY */
++ struct _gcsHAL_ALLOCATE_VIRTUAL_COMMAND_BUFFER
++ {
++ /* Number of bytes to allocate. */
++ IN OUT gctUINT64 bytes;
++
++ /* Physical address of allocation. Just a name. */
++ OUT gctUINT32 physical;
++
++ /* Logical address of allocation. */
++ OUT gctUINT64 logical;
++ }
++ AllocateVirtualCommandBuffer;
++
++ /* gcvHAL_FREE_NON_PAGED_MEMORY */
++ struct _gcsHAL_FREE_VIRTUAL_COMMAND_BUFFER
++ {
++ /* Number of bytes allocated. */
++ IN gctUINT64 bytes;
++
++ /* Physical address of allocation. Just a name. */
++ IN gctUINT32 physical;
++
++ /* Logical address of allocation. */
++ IN gctUINT64 logical;
++ }
++ FreeVirtualCommandBuffer;
++
++ /* gcvHAL_EVENT_COMMIT. */
++ struct _gcsHAL_EVENT_COMMIT
++ {
++ /* Event queue in gcsQUEUE. */
++ IN gctUINT64 queue;
++ }
++ Event;
++
++ /* gcvHAL_COMMIT */
++ struct _gcsHAL_COMMIT
++ {
++ /* Context buffer object gckCONTEXT. */
++ IN gctUINT64 context;
++
++ /* Command buffer gcoCMDBUF. */
++ IN gctUINT64 commandBuffer;
++
++ /* State delta buffer in gcsSTATE_DELTA. */
++ gctUINT64 delta;
++
++ /* Event queue in gcsQUEUE. */
++ IN gctUINT64 queue;
++ }
++ Commit;
++
++ /* gcvHAL_MAP_USER_MEMORY */
++ struct _gcsHAL_MAP_USER_MEMORY
++ {
++ /* Base address of user memory to map. */
++ IN gctUINT64 memory;
++
++ /* Physical address of user memory to map. */
++ IN gctUINT32 physical;
++
++ /* Size of user memory in bytes to map. */
++ IN gctUINT64 size;
++
++ /* Info record required by gcvHAL_UNMAP_USER_MEMORY. Just a name. */
++ OUT gctUINT32 info;
++
++ /* Physical address of mapped memory. */
++ OUT gctUINT32 address;
++ }
++ MapUserMemory;
++
++ /* gcvHAL_UNMAP_USER_MEMORY */
++ struct _gcsHAL_UNMAP_USER_MEMORY
++ {
++ /* Base address of user memory to unmap. */
++ IN gctUINT64 memory;
++
++ /* Size of user memory in bytes to unmap. */
++ IN gctUINT64 size;
++
++ /* Info record returned by gcvHAL_MAP_USER_MEMORY. Just a name. */
++ IN gctUINT32 info;
++
++ /* Physical address of mapped memory as returned by
++ gcvHAL_MAP_USER_MEMORY. */
++ IN gctUINT32 address;
++ }
++ UnmapUserMemory;
++#if !USE_NEW_LINUX_SIGNAL
++ /* gcsHAL_USER_SIGNAL */
++ struct _gcsHAL_USER_SIGNAL
++ {
++ /* Command. */
++ gceUSER_SIGNAL_COMMAND_CODES command;
++
++ /* Signal ID. */
++ IN OUT gctINT id;
++
++ /* Reset mode. */
++ IN gctBOOL manualReset;
++
++ /* Wait timedout. */
++ IN gctUINT32 wait;
++
++ /* State. */
++ IN gctBOOL state;
++ }
++ UserSignal;
++#endif
++
++ /* gcvHAL_SIGNAL. */
++ struct _gcsHAL_SIGNAL
++ {
++ /* Signal handle to signal gctSIGNAL. */
++ IN gctUINT64 signal;
++
++ /* Reserved gctSIGNAL. */
++ IN gctUINT64 auxSignal;
++
++ /* Process owning the signal gctHANDLE. */
++ IN gctUINT64 process;
++
++#if defined(__QNXNTO__)
++ /* Client pulse side-channel connection ID. Set by client in gcoOS_CreateSignal. */
++ IN gctINT32 coid;
++
++ /* Set by server. */
++ IN gctINT32 rcvid;
++#endif
++ /* Event generated from where of pipeline */
++ IN gceKERNEL_WHERE fromWhere;
++ }
++ Signal;
++
++ /* gcvHAL_WRITE_DATA. */
++ struct _gcsHAL_WRITE_DATA
++ {
++ /* Address to write data to. */
++ IN gctUINT32 address;
++
++ /* Data to write. */
++ IN gctUINT32 data;
++ }
++ WriteData;
++
++ /* gcvHAL_ALLOCATE_CONTIGUOUS_MEMORY */
++ struct _gcsHAL_ALLOCATE_CONTIGUOUS_MEMORY
++ {
++ /* Number of bytes to allocate. */
++ IN OUT gctUINT64 bytes;
++
++ /* Hardware address of allocation. */
++ OUT gctUINT32 address;
++
++ /* Physical address of allocation. Just a name. */
++ OUT gctUINT32 physical;
++
++ /* Logical address of allocation. */
++ OUT gctUINT64 logical;
++ }
++ AllocateContiguousMemory;
++
++ /* gcvHAL_FREE_CONTIGUOUS_MEMORY */
++ struct _gcsHAL_FREE_CONTIGUOUS_MEMORY
++ {
++ /* Number of bytes allocated. */
++ IN gctUINT64 bytes;
++
++ /* Physical address of allocation. Just a name. */
++ IN gctUINT32 physical;
++
++ /* Logical address of allocation. */
++ IN gctUINT64 logical;
++ }
++ FreeContiguousMemory;
++
++ /* gcvHAL_READ_REGISTER */
++ struct _gcsHAL_READ_REGISTER
++ {
++ /* Logical address of memory to write data to. */
++ IN gctUINT32 address;
++
++ /* Data read. */
++ OUT gctUINT32 data;
++ }
++ ReadRegisterData;
++
++ /* gcvHAL_WRITE_REGISTER */
++ struct _gcsHAL_WRITE_REGISTER
++ {
++ /* Logical address of memory to write data to. */
++ IN gctUINT32 address;
++
++ /* Data read. */
++ IN gctUINT32 data;
++ }
++ WriteRegisterData;
++
++#if VIVANTE_PROFILER
++ /* gcvHAL_GET_PROFILE_SETTING */
++ struct _gcsHAL_GET_PROFILE_SETTING
++ {
++ /* Enable profiling */
++ OUT gctBOOL enable;
++
++ /* The profile file name */
++ OUT gctCHAR fileName[gcdMAX_PROFILE_FILE_NAME];
++ }
++ GetProfileSetting;
++
++ /* gcvHAL_SET_PROFILE_SETTING */
++ struct _gcsHAL_SET_PROFILE_SETTING
++ {
++ /* Enable profiling */
++ IN gctBOOL enable;
++
++ /* The profile file name */
++ IN gctCHAR fileName[gcdMAX_PROFILE_FILE_NAME];
++ }
++ SetProfileSetting;
++
++#if VIVANTE_PROFILER_PERDRAW
++ /* gcvHAL_READ_PROFILER_REGISTER_SETTING */
++ struct _gcsHAL_READ_PROFILER_REGISTER_SETTING
++ {
++ /*Should Clear Register*/
++ IN gctBOOL bclear;
++ }
++ SetProfilerRegisterClear;
++#endif
++
++ /* gcvHAL_READ_ALL_PROFILE_REGISTERS */
++ struct _gcsHAL_READ_ALL_PROFILE_REGISTERS
++ {
++#if VIVANTE_PROFILER_CONTEXT
++ /* Context buffer object gckCONTEXT. Just a name. */
++ IN gctUINT32 context;
++#endif
++ /* Data read. */
++ OUT gcsPROFILER_COUNTERS counters;
++ }
++ RegisterProfileData;
++
++ /* gcvHAL_PROFILE_REGISTERS_2D */
++ struct _gcsHAL_PROFILE_REGISTERS_2D
++ {
++ /* Data read in gcs2D_PROFILE. */
++ OUT gctUINT64 hwProfile2D;
++ }
++ RegisterProfileData2D;
++#endif
++ /* Power management. */
++ /* gcvHAL_SET_POWER_MANAGEMENT_STATE */
++ struct _gcsHAL_SET_POWER_MANAGEMENT
++ {
++ /* Data read. */
++ IN gceCHIPPOWERSTATE state;
++ }
++ SetPowerManagement;
++
++ /* gcvHAL_QUERY_POWER_MANAGEMENT_STATE */
++ struct _gcsHAL_QUERY_POWER_MANAGEMENT
++ {
++ /* Data read. */
++ OUT gceCHIPPOWERSTATE state;
++
++ /* Idle query. */
++ OUT gctBOOL isIdle;
++ }
++ QueryPowerManagement;
++
++ /* gcvHAL_QUERY_KERNEL_SETTINGS */
++ struct _gcsHAL_QUERY_KERNEL_SETTINGS
++ {
++ /* Settings.*/
++ OUT gcsKERNEL_SETTINGS settings;
++ }
++ QueryKernelSettings;
++
++ /* gcvHAL_MAP_PHYSICAL */
++ struct _gcsHAL_MAP_PHYSICAL
++ {
++ /* gcvTRUE to map, gcvFALSE to unmap. */
++ IN gctBOOL map;
++
++ /* Physical address. */
++ IN OUT gctUINT64 physical;
++ }
++ MapPhysical;
++
++ /* gcvHAL_DEBUG */
++ struct _gcsHAL_DEBUG
++ {
++ /* If gcvTRUE, set the debug information. */
++ IN gctBOOL set;
++ IN gctUINT32 level;
++ IN gctUINT32 zones;
++ IN gctBOOL enable;
++
++ IN gceDEBUG_MESSAGE_TYPE type;
++ IN gctUINT32 messageSize;
++
++ /* Message to print if not empty. */
++ IN gctCHAR message[80];
++ }
++ Debug;
++
++ /* gcvHAL_CACHE */
++ struct _gcsHAL_CACHE
++ {
++ IN gceCACHEOPERATION operation;
++ /* gctHANDLE */
++ IN gctUINT64 process;
++ IN gctUINT64 logical;
++ IN gctUINT64 bytes;
++ /* gcuVIDMEM_NODE_PTR */
++ IN gctUINT64 node;
++ }
++ Cache;
++
++ /* gcvHAL_TIMESTAMP */
++ struct _gcsHAL_TIMESTAMP
++ {
++ /* Timer select. */
++ IN gctUINT32 timer;
++
++ /* Timer request type (0-stop, 1-start, 2-send delta). */
++ IN gctUINT32 request;
++
++ /* Result of delta time in microseconds. */
++ OUT gctINT32 timeDelta;
++ }
++ TimeStamp;
++
++ /* gcvHAL_DATABASE */
++ struct _gcsHAL_DATABASE
++ {
++ /* Set to gcvTRUE if you want to query a particular process ID.
++ ** Set to gcvFALSE to query the last detached process. */
++ IN gctBOOL validProcessID;
++
++ /* Process ID to query. */
++ IN gctUINT32 processID;
++
++ /* Information. */
++ OUT gcuDATABASE_INFO vidMem;
++ OUT gcuDATABASE_INFO nonPaged;
++ OUT gcuDATABASE_INFO contiguous;
++ OUT gcuDATABASE_INFO gpuIdle;
++ }
++ Database;
++
++ /* gcvHAL_VIDMEM_DATABASE */
++ struct _gcsHAL_VIDMEM_DATABASE
++ {
++ /* Set to gcvTRUE if you want to query a particular process ID.
++ ** Set to gcvFALSE to query the last detached process. */
++ IN gctBOOL validProcessID;
++
++ /* Process ID to query. */
++ IN gctUINT32 processID;
++
++ /* Information. */
++ OUT gcuDATABASE_INFO vidMemResv;
++ OUT gcuDATABASE_INFO vidMemCont;
++ OUT gcuDATABASE_INFO vidMemVirt;
++ }
++ VidMemDatabase;
++
++ /* gcvHAL_VERSION */
++ struct _gcsHAL_VERSION
++ {
++ /* Major version: N.n.n. */
++ OUT gctINT32 major;
++
++ /* Minor version: n.N.n. */
++ OUT gctINT32 minor;
++
++ /* Patch version: n.n.N. */
++ OUT gctINT32 patch;
++
++ /* Build version. */
++ OUT gctUINT32 build;
++ }
++ Version;
++
++ /* gcvHAL_CHIP_INFO */
++ struct _gcsHAL_CHIP_INFO
++ {
++ /* Chip count. */
++ OUT gctINT32 count;
++
++ /* Chip types. */
++ OUT gceHARDWARE_TYPE types[gcdCHIP_COUNT];
++ }
++ ChipInfo;
++
++ /* gcvHAL_ATTACH */
++ struct _gcsHAL_ATTACH
++ {
++ /* Context buffer object gckCONTEXT. Just a name. */
++ OUT gctUINT32 context;
++
++ /* Number of states in the buffer. */
++ OUT gctUINT64 stateCount;
++ }
++ Attach;
++
++ /* gcvHAL_DETACH */
++ struct _gcsHAL_DETACH
++ {
++ /* Context buffer object gckCONTEXT. Just a name. */
++ IN gctUINT32 context;
++ }
++ Detach;
++
++ /* gcvHAL_COMPOSE. */
++ gcsHAL_COMPOSE Compose;
++
++ /* gcvHAL_GET_FRAME_INFO. */
++ struct _gcsHAL_GET_FRAME_INFO
++ {
++ /* gcsHAL_FRAME_INFO* */
++ OUT gctUINT64 frameInfo;
++ }
++ GetFrameInfo;
++
++ /* gcvHAL_SET_TIME_OUT. */
++ struct _gcsHAL_SET_TIMEOUT
++ {
++ gctUINT32 timeOut;
++ }
++ SetTimeOut;
++
++#if gcdENABLE_VG
++ /* gcvHAL_COMMIT */
++ struct _gcsHAL_VGCOMMIT
++ {
++ /* Context buffer in gcsVGCONTEXT. */
++ IN gctUINT64 context;
++
++ /* Command queue in gcsVGCMDQUEUE. */
++ IN gctUINT64 queue;
++
++ /* Number of entries in the queue. */
++ IN gctUINT entryCount;
++
++ /* Task table in gcsTASK_MASTER_TABLE. */
++ IN gctUINT64 taskTable;
++ }
++ VGCommit;
++
++ /* gcvHAL_QUERY_COMMAND_BUFFER */
++ struct _gcsHAL_QUERY_COMMAND_BUFFER
++ {
++ /* Command buffer attributes. */
++ OUT gcsCOMMAND_BUFFER_INFO information;
++ }
++ QueryCommandBuffer;
++
++#endif
++
++ struct _gcsHAL_GET_SHARED_INFO
++ {
++ /* Process id. */
++ IN gctUINT32 pid;
++
++ /* Data id. */
++ IN gctUINT32 dataId;
++
++ /* Data size. */
++ IN gctSIZE_T bytes;
++
++ /* Pointer to save the shared data. */
++ OUT gctPOINTER data;
++ }
++ GetSharedInfo;
++
++ struct _gcsHAL_SET_SHARED_INFO
++ {
++ /* Data id. */
++ IN gctUINT32 dataId;
++
++ /* Data to be shared. */
++ IN gctPOINTER data;
++
++ /* Data size. */
++ IN gctSIZE_T bytes;
++ }
++ SetSharedInfo;
++
++ struct _gcsHAL_SET_FSCALE_VALUE
++ {
++ IN gctUINT value;
++ }
++ SetFscaleValue;
++
++ struct _gcsHAL_GET_FSCALE_VALUE
++ {
++ OUT gctUINT value;
++ OUT gctUINT minValue;
++ OUT gctUINT maxValue;
++ }
++ GetFscaleValue;
++
++ struct _gcsHAL_QUERY_RESET_TIME_STAMP
++ {
++ OUT gctUINT64 timeStamp;
++ }
++ QueryResetTimeStamp;
++
++ struct _gcsHAL_SYNC_POINT
++ {
++ /* Command. */
++ gceSYNC_POINT_COMMAND_CODES command;
++
++ /* Sync point. */
++ IN OUT gctUINT64 syncPoint;
++
++ /* From where. */
++ IN gceKERNEL_WHERE fromWhere;
++
++ /* Signaled state. */
++ OUT gctBOOL state;
++ }
++ SyncPoint;
++
++ struct _gcsHAL_CREATE_NATIVE_FENCE
++ {
++ /* Signal id to dup. */
++ IN gctUINT64 syncPoint;
++
++ /* Native fence file descriptor. */
++ OUT gctINT fenceFD;
++
++ }
++ CreateNativeFence;
++ }
++ u;
++}
++gcsHAL_INTERFACE;
++
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __gc_hal_driver_h_ */
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_driver_vg.h linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_driver_vg.h
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_driver_vg.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_driver_vg.h 2015-07-27 23:13:06.210822785 +0200
+@@ -0,0 +1,270 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_driver_vg_h_
++#define __gc_hal_driver_vg_h_
++
++
++
++#include "gc_hal_types.h"
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/******************************************************************************\
++******************************* I/O Control Codes ******************************
++\******************************************************************************/
++
++#define gcvHAL_CLASS "galcore"
++#define IOCTL_GCHAL_INTERFACE 30000
++
++/******************************************************************************\
++********************************* Command Codes ********************************
++\******************************************************************************/
++
++/******************************************************************************\
++********************* Command buffer information structure. ********************
++\******************************************************************************/
++
++typedef struct _gcsCOMMAND_BUFFER_INFO * gcsCOMMAND_BUFFER_INFO_PTR;
++typedef struct _gcsCOMMAND_BUFFER_INFO
++{
++ /* FE command buffer interrupt ID. */
++ gctINT32 feBufferInt;
++
++ /* TS overflow interrupt ID. */
++ gctINT32 tsOverflowInt;
++
++ /* Alignment and mask for the buffer address. */
++ gctUINT addressMask;
++ gctSIZE_T addressAlignment;
++
++ /* Alignment for each command. */
++ gctSIZE_T commandAlignment;
++
++ /* Number of bytes required by the STATE command. */
++ gctSIZE_T stateCommandSize;
++
++ /* Number of bytes required by the RESTART command. */
++ gctSIZE_T restartCommandSize;
++
++ /* Number of bytes required by the FETCH command. */
++ gctSIZE_T fetchCommandSize;
++
++ /* Number of bytes required by the CALL command. */
++ gctSIZE_T callCommandSize;
++
++ /* Number of bytes required by the RETURN command. */
++ gctSIZE_T returnCommandSize;
++
++ /* Number of bytes required by the EVENT command. */
++ gctSIZE_T eventCommandSize;
++
++ /* Number of bytes required by the END command. */
++ gctSIZE_T endCommandSize;
++
++ /* Number of bytes reserved at the tail of a static command buffer. */
++ gctSIZE_T staticTailSize;
++
++ /* Number of bytes reserved at the tail of a dynamic command buffer. */
++ gctSIZE_T dynamicTailSize;
++}
++gcsCOMMAND_BUFFER_INFO;
++
++/******************************************************************************\
++******************************** Task Structures *******************************
++\******************************************************************************/
++
++typedef enum _gceTASK
++{
++ gcvTASK_LINK,
++ gcvTASK_CLUSTER,
++ gcvTASK_INCREMENT,
++ gcvTASK_DECREMENT,
++ gcvTASK_SIGNAL,
++ gcvTASK_LOCKDOWN,
++ gcvTASK_UNLOCK_VIDEO_MEMORY,
++ gcvTASK_FREE_VIDEO_MEMORY,
++ gcvTASK_FREE_CONTIGUOUS_MEMORY,
++ gcvTASK_UNMAP_USER_MEMORY
++}
++gceTASK;
++
++typedef struct _gcsTASK_HEADER * gcsTASK_HEADER_PTR;
++typedef struct _gcsTASK_HEADER
++{
++ /* Task ID. */
++ IN gceTASK id;
++}
++gcsTASK_HEADER;
++
++typedef struct _gcsTASK_LINK * gcsTASK_LINK_PTR;
++typedef struct _gcsTASK_LINK
++{
++ /* Task ID (gcvTASK_LINK). */
++ IN gceTASK id;
++
++ /* Pointer to the next task container. */
++ IN gctPOINTER cotainer;
++
++ /* Pointer to the next task from the next task container. */
++ IN gcsTASK_HEADER_PTR task;
++}
++gcsTASK_LINK;
++
++typedef struct _gcsTASK_CLUSTER * gcsTASK_CLUSTER_PTR;
++typedef struct _gcsTASK_CLUSTER
++{
++ /* Task ID (gcvTASK_CLUSTER). */
++ IN gceTASK id;
++
++ /* Number of tasks in the cluster. */
++ IN gctUINT taskCount;
++}
++gcsTASK_CLUSTER;
++
++typedef struct _gcsTASK_INCREMENT * gcsTASK_INCREMENT_PTR;
++typedef struct _gcsTASK_INCREMENT
++{
++ /* Task ID (gcvTASK_INCREMENT). */
++ IN gceTASK id;
++
++ /* Address of the variable to increment. */
++ IN gctUINT32 address;
++}
++gcsTASK_INCREMENT;
++
++typedef struct _gcsTASK_DECREMENT * gcsTASK_DECREMENT_PTR;
++typedef struct _gcsTASK_DECREMENT
++{
++ /* Task ID (gcvTASK_DECREMENT). */
++ IN gceTASK id;
++
++ /* Address of the variable to decrement. */
++ IN gctUINT32 address;
++}
++gcsTASK_DECREMENT;
++
++typedef struct _gcsTASK_SIGNAL * gcsTASK_SIGNAL_PTR;
++typedef struct _gcsTASK_SIGNAL
++{
++ /* Task ID (gcvTASK_SIGNAL). */
++ IN gceTASK id;
++
++ /* Process owning the signal. */
++ IN gctHANDLE process;
++
++ /* Signal handle to signal. */
++ IN gctSIGNAL signal;
++
++#if defined(__QNXNTO__)
++ IN gctINT32 coid;
++ IN gctINT32 rcvid;
++#endif
++}
++gcsTASK_SIGNAL;
++
++typedef struct _gcsTASK_LOCKDOWN * gcsTASK_LOCKDOWN_PTR;
++typedef struct _gcsTASK_LOCKDOWN
++{
++ /* Task ID (gcvTASK_LOCKDOWN). */
++ IN gceTASK id;
++
++ /* Address of the user space counter. */
++ IN gctUINT32 userCounter;
++
++ /* Address of the kernel space counter. */
++ IN gctUINT32 kernelCounter;
++
++ /* Process owning the signal. */
++ IN gctHANDLE process;
++
++ /* Signal handle to signal. */
++ IN gctSIGNAL signal;
++}
++gcsTASK_LOCKDOWN;
++
++typedef struct _gcsTASK_UNLOCK_VIDEO_MEMORY * gcsTASK_UNLOCK_VIDEO_MEMORY_PTR;
++typedef struct _gcsTASK_UNLOCK_VIDEO_MEMORY
++{
++ /* Task ID (gcvTASK_UNLOCK_VIDEO_MEMORY). */
++ IN gceTASK id;
++
++ /* Allocated video memory. */
++ IN gctUINT64 node;
++}
++gcsTASK_UNLOCK_VIDEO_MEMORY;
++
++typedef struct _gcsTASK_FREE_VIDEO_MEMORY * gcsTASK_FREE_VIDEO_MEMORY_PTR;
++typedef struct _gcsTASK_FREE_VIDEO_MEMORY
++{
++ /* Task ID (gcvTASK_FREE_VIDEO_MEMORY). */
++ IN gceTASK id;
++
++ /* Allocated video memory. */
++ IN gctUINT64 node;
++}
++gcsTASK_FREE_VIDEO_MEMORY;
++
++typedef struct _gcsTASK_FREE_CONTIGUOUS_MEMORY * gcsTASK_FREE_CONTIGUOUS_MEMORY_PTR;
++typedef struct _gcsTASK_FREE_CONTIGUOUS_MEMORY
++{
++ /* Task ID (gcvTASK_FREE_CONTIGUOUS_MEMORY). */
++ IN gceTASK id;
++
++ /* Number of bytes allocated. */
++ IN gctSIZE_T bytes;
++
++ /* Physical address of allocation. */
++ IN gctPHYS_ADDR physical;
++
++ /* Logical address of allocation. */
++ IN gctPOINTER logical;
++}
++gcsTASK_FREE_CONTIGUOUS_MEMORY;
++
++typedef struct _gcsTASK_UNMAP_USER_MEMORY * gcsTASK_UNMAP_USER_MEMORY_PTR;
++typedef struct _gcsTASK_UNMAP_USER_MEMORY
++{
++ /* Task ID (gcvTASK_UNMAP_USER_MEMORY). */
++ IN gceTASK id;
++
++ /* Base address of user memory to unmap. */
++ IN gctPOINTER memory;
++
++ /* Size of user memory in bytes to unmap. */
++ IN gctSIZE_T size;
++
++ /* Info record returned by gcvHAL_MAP_USER_MEMORY. */
++ IN gctPOINTER info;
++
++ /* Physical address of mapped memory as returned by
++ gcvHAL_MAP_USER_MEMORY. */
++ IN gctUINT32 address;
++}
++gcsTASK_UNMAP_USER_MEMORY;
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __gc_hal_driver_h_ */
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_dump.h linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_dump.h
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_dump.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_dump.h 2015-07-27 23:13:06.210822785 +0200
+@@ -0,0 +1,88 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_dump_h_
++#define __gc_hal_dump_h_
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/*
++** FILE LAYOUT:
++**
++** gcsDUMP_FILE structure
++**
++** gcsDUMP_DATA frame
++** gcsDUMP_DATA or gcDUMP_DATA_SIZE records rendingring the frame
++** gctUINT8 data[length]
++*/
++
++#define gcvDUMP_FILE_SIGNATURE gcmCC('g','c','D','B')
++
++typedef struct _gcsDUMP_FILE
++{
++ gctUINT32 signature; /* File signature */
++ gctSIZE_T length; /* Length of file */
++ gctUINT32 frames; /* Number of frames in file */
++}
++gcsDUMP_FILE;
++
++typedef enum _gceDUMP_TAG
++{
++ gcvTAG_SURFACE = gcmCC('s','u','r','f'),
++ gcvTAG_FRAME = gcmCC('f','r','m',' '),
++ gcvTAG_COMMAND = gcmCC('c','m','d',' '),
++ gcvTAG_INDEX = gcmCC('i','n','d','x'),
++ gcvTAG_STREAM = gcmCC('s','t','r','m'),
++ gcvTAG_TEXTURE = gcmCC('t','e','x','t'),
++ gcvTAG_RENDER_TARGET = gcmCC('r','n','d','r'),
++ gcvTAG_DEPTH = gcmCC('z','b','u','f'),
++ gcvTAG_RESOLVE = gcmCC('r','s','l','v'),
++ gcvTAG_DELETE = gcmCC('d','e','l',' '),
++}
++gceDUMP_TAG;
++
++typedef struct _gcsDUMP_SURFACE
++{
++ gceDUMP_TAG type; /* Type of record. */
++ gctUINT32 address; /* Address of the surface. */
++ gctINT16 width; /* Width of surface. */
++ gctINT16 height; /* Height of surface. */
++ gceSURF_FORMAT format; /* Surface pixel format. */
++ gctSIZE_T length; /* Number of bytes inside the surface. */
++}
++gcsDUMP_SURFACE;
++
++typedef struct _gcsDUMP_DATA
++{
++ gceDUMP_TAG type; /* Type of record. */
++ gctSIZE_T length; /* Number of bytes of data. */
++ gctUINT32 address; /* Address for the data. */
++}
++gcsDUMP_DATA;
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __gc_hal_dump_h_ */
++
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_eglplatform.h linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_eglplatform.h
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_eglplatform.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_eglplatform.h 2015-07-27 23:13:06.210822785 +0200
+@@ -0,0 +1,627 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++#ifndef __gc_hal_eglplatform_h_
++#define __gc_hal_eglplatform_h_
++
++/* Include VDK types. */
++#include "gc_hal_types.h"
++#include "gc_hal_base.h"
++#include "gc_hal_eglplatform_type.h"
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++
++#if defined(_WIN32) || defined(__VC32__) && !defined(__CYGWIN__) && !defined(__SCITECH_SNAP__)
++/* Win32 and Windows CE platforms. */
++#include <windows.h>
++typedef HDC HALNativeDisplayType;
++typedef HWND HALNativeWindowType;
++typedef HBITMAP HALNativePixmapType;
++
++typedef struct __BITFIELDINFO{
++ BITMAPINFO bmi;
++ RGBQUAD bmiColors[2];
++} BITFIELDINFO;
++
++#elif defined(LINUX) && defined(EGL_API_DFB) && !defined(__APPLE__)
++#include <directfb.h>
++typedef struct _DFBDisplay * HALNativeDisplayType;
++typedef struct _DFBWindow * HALNativeWindowType;
++typedef struct _DFBPixmap * HALNativePixmapType;
++
++#elif defined(LINUX) && defined(EGL_API_FB) && !defined(__APPLE__)
++
++#if defined(EGL_API_WL)
++/* Wayland platform. */
++#include "wayland-server.h"
++#include <wayland-egl.h>
++
++#define WL_EGL_NUM_BACKBUFFERS 3
++
++typedef struct _gcsWL_VIV_BUFFER
++{
++ struct wl_resource *wl_buffer;
++ gcoSURF surface;
++ gctINT32 width, height;
++} gcsWL_VIV_BUFFER;
++
++typedef struct _gcsWL_EGL_DISPLAY
++{
++ struct wl_display* wl_display;
++ struct wl_viv* wl_viv;
++ struct wl_registry *registry;
++ struct wl_event_queue *wl_queue;
++} gcsWL_EGL_DISPLAY;
++
++typedef struct _gcsWL_EGL_BUFFER_INFO
++{
++ gctINT32 width;
++ gctINT32 height;
++ gctINT32 stride;
++ gceSURF_FORMAT format;
++ gcuVIDMEM_NODE_PTR node;
++ gcePOOL pool;
++ gctUINT bytes;
++ gcoSURF surface;
++ gcoSURF attached_surface;
++ gctINT32 invalidate;
++ gctBOOL locked;
++} gcsWL_EGL_BUFFER_INFO;
++
++typedef struct _gcsWL_EGL_BUFFER
++{
++ struct wl_buffer* wl_buffer;
++ gcsWL_EGL_BUFFER_INFO info;
++} gcsWL_EGL_BUFFER;
++
++typedef struct _gcsWL_EGL_WINDOW_INFO
++{
++ gctINT32 dx;
++ gctINT32 dy;
++ gctUINT width;
++ gctUINT height;
++ gctINT32 attached_width;
++ gctINT32 attached_height;
++ gceSURF_FORMAT format;
++ gctUINT bpp;
++} gcsWL_EGL_WINDOW_INFO;
++
++struct wl_egl_window
++{
++ gcsWL_EGL_DISPLAY* display;
++ gcsWL_EGL_BUFFER backbuffers[WL_EGL_NUM_BACKBUFFERS];
++ gcsWL_EGL_WINDOW_INFO info;
++ gctUINT current;
++ struct wl_surface* surface;
++ struct wl_callback* frame_callback;
++};
++
++typedef void* HALNativeDisplayType;
++typedef void* HALNativeWindowType;
++typedef void* HALNativePixmapType;
++#else
++/* Linux platform for FBDEV. */
++typedef struct _FBDisplay * HALNativeDisplayType;
++typedef struct _FBWindow * HALNativeWindowType;
++typedef struct _FBPixmap * HALNativePixmapType;
++#endif
++#elif defined(__ANDROID__) || defined(ANDROID)
++
++struct egl_native_pixmap_t;
++
++#if ANDROID_SDK_VERSION >= 9
++ #include <android/native_window.h>
++
++ typedef struct ANativeWindow* HALNativeWindowType;
++ typedef struct egl_native_pixmap_t* HALNativePixmapType;
++ typedef void* HALNativeDisplayType;
++#else
++ struct android_native_window_t;
++ typedef struct android_native_window_t* HALNativeWindowType;
++ typedef struct egl_native_pixmap_t * HALNativePixmapType;
++ typedef void* HALNativeDisplayType;
++#endif
++
++#elif defined(LINUX) || defined(__APPLE__)
++/* X11 platform. */
++#include <X11/Xlib.h>
++#include <X11/Xutil.h>
++
++typedef Display * HALNativeDisplayType;
++typedef Window HALNativeWindowType;
++
++#ifdef CUSTOM_PIXMAP
++typedef void * HALNativePixmapType;
++#else
++typedef Pixmap HALNativePixmapType;
++#endif /* CUSTOM_PIXMAP */
++
++/* Rename some badly named X defines. */
++#ifdef Status
++# define XStatus int
++# undef Status
++#endif
++#ifdef Always
++# define XAlways 2
++# undef Always
++#endif
++#ifdef CurrentTime
++# undef CurrentTime
++# define XCurrentTime 0
++#endif
++
++#elif defined(__QNXNTO__)
++#include <screen/screen.h>
++
++/* VOID */
++typedef int HALNativeDisplayType;
++typedef screen_window_t HALNativeWindowType;
++typedef screen_pixmap_t HALNativePixmapType;
++
++#else
++
++#error "Platform not recognized"
++
++/* VOID */
++typedef void * HALNativeDisplayType;
++typedef void * HALNativeWindowType;
++typedef void * HALNativePixmapType;
++
++#endif
++
++/* define DUMMY according to the system */
++#if defined(EGL_API_WL)
++# define WL_DUMMY (31415926)
++# define EGL_DUMMY WL_DUMMY
++#elif defined(__ANDROID__) || defined(ANDROID)
++# define ANDROID_DUMMY (31415926)
++# define EGL_DUMMY ANDROID_DUMMY
++#else
++# define EGL_DUMMY (31415926)
++#endif
++
++/*******************************************************************************
++** Display. ********************************************************************
++*/
++
++gceSTATUS
++gcoOS_GetDisplay(
++ OUT HALNativeDisplayType * Display,
++ IN gctPOINTER Context
++ );
++
++gceSTATUS
++gcoOS_GetDisplayByIndex(
++ IN gctINT DisplayIndex,
++ OUT HALNativeDisplayType * Display,
++ IN gctPOINTER Context
++ );
++
++gceSTATUS
++gcoOS_GetDisplayInfo(
++ IN HALNativeDisplayType Display,
++ OUT gctINT * Width,
++ OUT gctINT * Height,
++ OUT gctSIZE_T * Physical,
++ OUT gctINT * Stride,
++ OUT gctINT * BitsPerPixel
++ );
++
++
++
++gceSTATUS
++gcoOS_GetDisplayInfoEx(
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window,
++ IN gctUINT DisplayInfoSize,
++ OUT halDISPLAY_INFO * DisplayInfo
++ );
++
++gceSTATUS
++gcoOS_GetNextDisplayInfoExByIndex(
++ IN gctINT Index,
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window,
++ IN gctUINT DisplayInfoSize,
++ OUT halDISPLAY_INFO * DisplayInfo
++ );
++
++gceSTATUS
++gcoOS_GetDisplayVirtual(
++ IN HALNativeDisplayType Display,
++ OUT gctINT * Width,
++ OUT gctINT * Height
++ );
++
++gceSTATUS
++gcoOS_GetDisplayBackbuffer(
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window,
++ OUT gctPOINTER * context,
++ OUT gcoSURF * surface,
++ OUT gctUINT * Offset,
++ OUT gctINT * X,
++ OUT gctINT * Y
++ );
++
++gceSTATUS
++gcoOS_SetDisplayVirtual(
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window,
++ IN gctUINT Offset,
++ IN gctINT X,
++ IN gctINT Y
++ );
++
++gceSTATUS
++gcoOS_SetDisplayVirtualEx(
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window,
++ IN gctPOINTER Context,
++ IN gcoSURF Surface,
++ IN gctUINT Offset,
++ IN gctINT X,
++ IN gctINT Y
++ );
++
++gceSTATUS
++gcoOS_SetSwapInterval(
++ IN HALNativeDisplayType Display,
++ IN gctINT Interval
++);
++
++gceSTATUS
++gcoOS_GetSwapInterval(
++ IN HALNativeDisplayType Display,
++ IN gctINT_PTR Min,
++ IN gctINT_PTR Max
++);
++
++gceSTATUS
++gcoOS_DisplayBufferRegions(
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window,
++ IN gctINT NumRects,
++ IN gctINT_PTR Rects
++ );
++
++gceSTATUS
++gcoOS_DestroyDisplay(
++ IN HALNativeDisplayType Display
++ );
++
++gceSTATUS
++gcoOS_InitLocalDisplayInfo(
++ IN HALNativeDisplayType Display,
++ IN OUT gctPOINTER * localDisplay
++ );
++
++gceSTATUS
++gcoOS_DeinitLocalDisplayInfo(
++ IN HALNativeDisplayType Display,
++ IN OUT gctPOINTER * localDisplay
++ );
++
++gceSTATUS
++gcoOS_GetDisplayInfoEx2(
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window,
++ IN gctPOINTER localDisplay,
++ IN gctUINT DisplayInfoSize,
++ OUT halDISPLAY_INFO * DisplayInfo
++ );
++
++gceSTATUS
++gcoOS_GetDisplayBackbufferEx(
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window,
++ IN gctPOINTER localDisplay,
++ OUT gctPOINTER * context,
++ OUT gcoSURF * surface,
++ OUT gctUINT * Offset,
++ OUT gctINT * X,
++ OUT gctINT * Y
++ );
++
++gceSTATUS
++gcoOS_IsValidDisplay(
++ IN HALNativeDisplayType Display
++ );
++
++gceSTATUS
++gcoOS_GetNativeVisualId(
++ IN HALNativeDisplayType Display,
++ OUT gctINT* nativeVisualId
++ );
++
++gctBOOL
++gcoOS_SynchronousFlip(
++ IN HALNativeDisplayType Display
++ );
++
++/*******************************************************************************
++** Windows. ********************************************************************
++*/
++
++gceSTATUS
++gcoOS_CreateWindow(
++ IN HALNativeDisplayType Display,
++ IN gctINT X,
++ IN gctINT Y,
++ IN gctINT Width,
++ IN gctINT Height,
++ OUT HALNativeWindowType * Window
++ );
++
++gceSTATUS
++gcoOS_GetWindowInfo(
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window,
++ OUT gctINT * X,
++ OUT gctINT * Y,
++ OUT gctINT * Width,
++ OUT gctINT * Height,
++ OUT gctINT * BitsPerPixel,
++ OUT gctUINT * Offset
++ );
++
++gceSTATUS
++gcoOS_DestroyWindow(
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window
++ );
++
++gceSTATUS
++gcoOS_DrawImage(
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window,
++ IN gctINT Left,
++ IN gctINT Top,
++ IN gctINT Right,
++ IN gctINT Bottom,
++ IN gctINT Width,
++ IN gctINT Height,
++ IN gctINT BitsPerPixel,
++ IN gctPOINTER Bits
++ );
++
++gceSTATUS
++gcoOS_GetImage(
++ IN HALNativeWindowType Window,
++ IN gctINT Left,
++ IN gctINT Top,
++ IN gctINT Right,
++ IN gctINT Bottom,
++ OUT gctINT * BitsPerPixel,
++ OUT gctPOINTER * Bits
++ );
++
++gceSTATUS
++gcoOS_GetWindowInfoEx(
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window,
++ OUT gctINT * X,
++ OUT gctINT * Y,
++ OUT gctINT * Width,
++ OUT gctINT * Height,
++ OUT gctINT * BitsPerPixel,
++ OUT gctUINT * Offset,
++ OUT gceSURF_FORMAT * Format
++ );
++
++gceSTATUS
++gcoOS_DrawImageEx(
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window,
++ IN gctINT Left,
++ IN gctINT Top,
++ IN gctINT Right,
++ IN gctINT Bottom,
++ IN gctINT Width,
++ IN gctINT Height,
++ IN gctINT BitsPerPixel,
++ IN gctPOINTER Bits,
++ IN gceSURF_FORMAT Format
++ );
++
++/*******************************************************************************
++** Pixmaps. ********************************************************************
++*/
++
++gceSTATUS
++gcoOS_CreatePixmap(
++ IN HALNativeDisplayType Display,
++ IN gctINT Width,
++ IN gctINT Height,
++ IN gctINT BitsPerPixel,
++ OUT HALNativePixmapType * Pixmap
++ );
++
++gceSTATUS
++gcoOS_GetPixmapInfo(
++ IN HALNativeDisplayType Display,
++ IN HALNativePixmapType Pixmap,
++ OUT gctINT * Width,
++ OUT gctINT * Height,
++ OUT gctINT * BitsPerPixel,
++ OUT gctINT * Stride,
++ OUT gctPOINTER * Bits
++ );
++
++gceSTATUS
++gcoOS_DrawPixmap(
++ IN HALNativeDisplayType Display,
++ IN HALNativePixmapType Pixmap,
++ IN gctINT Left,
++ IN gctINT Top,
++ IN gctINT Right,
++ IN gctINT Bottom,
++ IN gctINT Width,
++ IN gctINT Height,
++ IN gctINT BitsPerPixel,
++ IN gctPOINTER Bits
++ );
++
++gceSTATUS
++gcoOS_DestroyPixmap(
++ IN HALNativeDisplayType Display,
++ IN HALNativePixmapType Pixmap
++ );
++
++gceSTATUS
++gcoOS_GetPixmapInfoEx(
++ IN HALNativeDisplayType Display,
++ IN HALNativePixmapType Pixmap,
++ OUT gctINT * Width,
++ OUT gctINT * Height,
++ OUT gctINT * BitsPerPixel,
++ OUT gctINT * Stride,
++ OUT gctPOINTER * Bits,
++ OUT gceSURF_FORMAT * Format
++ );
++
++gceSTATUS
++gcoOS_CopyPixmapBits(
++ IN HALNativeDisplayType Display,
++ IN HALNativePixmapType Pixmap,
++ IN gctUINT DstWidth,
++ IN gctUINT DstHeight,
++ IN gctINT DstStride,
++ IN gceSURF_FORMAT DstFormat,
++ OUT gctPOINTER DstBits
++ );
++
++/*******************************************************************************
++** OS relative. ****************************************************************
++*/
++gceSTATUS
++gcoOS_LoadEGLLibrary(
++ OUT gctHANDLE * Handle
++ );
++
++gceSTATUS
++gcoOS_FreeEGLLibrary(
++ IN gctHANDLE Handle
++ );
++
++gceSTATUS
++gcoOS_ShowWindow(
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window
++ );
++
++gceSTATUS
++gcoOS_HideWindow(
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window
++ );
++
++gceSTATUS
++gcoOS_SetWindowTitle(
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window,
++ IN gctCONST_STRING Title
++ );
++
++gceSTATUS
++gcoOS_CapturePointer(
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window
++ );
++
++gceSTATUS
++gcoOS_GetEvent(
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window,
++ OUT halEvent * Event
++ );
++
++gceSTATUS
++gcoOS_CreateClientBuffer(
++ IN gctINT Width,
++ IN gctINT Height,
++ IN gctINT Format,
++ IN gctINT Type,
++ OUT gctPOINTER * ClientBuffer
++ );
++
++gceSTATUS
++gcoOS_GetClientBufferInfo(
++ IN gctPOINTER ClientBuffer,
++ OUT gctINT * Width,
++ OUT gctINT * Height,
++ OUT gctINT * Stride,
++ OUT gctPOINTER * Bits
++ );
++
++gceSTATUS
++gcoOS_DestroyClientBuffer(
++ IN gctPOINTER ClientBuffer
++ );
++
++gceSTATUS
++gcoOS_DestroyContext(
++ IN gctPOINTER Display,
++ IN gctPOINTER Context
++ );
++
++gceSTATUS
++gcoOS_CreateContext(
++ IN gctPOINTER LocalDisplay,
++ IN gctPOINTER Context
++ );
++
++gceSTATUS
++gcoOS_MakeCurrent(
++ IN gctPOINTER LocalDisplay,
++ IN HALNativeWindowType DrawDrawable,
++ IN HALNativeWindowType ReadDrawable,
++ IN gctPOINTER Context,
++ IN gcoSURF ResolveTarget
++ );
++
++gceSTATUS
++gcoOS_CreateDrawable(
++ IN gctPOINTER LocalDisplay,
++ IN HALNativeWindowType Drawable
++ );
++
++gceSTATUS
++gcoOS_DestroyDrawable(
++ IN gctPOINTER LocalDisplay,
++ IN HALNativeWindowType Drawable
++ );
++gceSTATUS
++gcoOS_SwapBuffers(
++ IN gctPOINTER LocalDisplay,
++ IN HALNativeWindowType Drawable,
++ IN gcoSURF RenderTarget,
++ IN gcoSURF ResolveTarget,
++ IN gctPOINTER ResolveBits,
++ OUT gctUINT *Width,
++ OUT gctUINT *Height
++ );
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __gc_hal_eglplatform_h_ */
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_eglplatform_type.h linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_eglplatform_type.h
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_eglplatform_type.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_eglplatform_type.h 2015-07-27 23:13:06.210822785 +0200
+@@ -0,0 +1,286 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_eglplatform_type_h_
++#define __gc_hal_eglplatform_type_h_
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/*******************************************************************************
++** Events. *********************************************************************
++*/
++
++typedef enum _halEventType
++{
++ /* Keyboard event. */
++ HAL_KEYBOARD,
++
++ /* Mouse move event. */
++ HAL_POINTER,
++
++ /* Mouse button event. */
++ HAL_BUTTON,
++
++ /* Application close event. */
++ HAL_CLOSE,
++
++ /* Application window has been updated. */
++ HAL_WINDOW_UPDATE
++}
++halEventType;
++
++/* Scancodes for keyboard. */
++typedef enum _halKeys
++{
++ HAL_UNKNOWN = -1,
++
++ HAL_BACKSPACE = 0x08,
++ HAL_TAB,
++ HAL_ENTER = 0x0D,
++ HAL_ESCAPE = 0x1B,
++
++ HAL_SPACE = 0x20,
++ HAL_SINGLEQUOTE = 0x27,
++ HAL_PAD_ASTERISK = 0x2A,
++ HAL_COMMA = 0x2C,
++ HAL_HYPHEN,
++ HAL_PERIOD,
++ HAL_SLASH,
++ HAL_0,
++ HAL_1,
++ HAL_2,
++ HAL_3,
++ HAL_4,
++ HAL_5,
++ HAL_6,
++ HAL_7,
++ HAL_8,
++ HAL_9,
++ HAL_SEMICOLON = 0x3B,
++ HAL_EQUAL = 0x3D,
++ HAL_A = 0x41,
++ HAL_B,
++ HAL_C,
++ HAL_D,
++ HAL_E,
++ HAL_F,
++ HAL_G,
++ HAL_H,
++ HAL_I,
++ HAL_J,
++ HAL_K,
++ HAL_L,
++ HAL_M,
++ HAL_N,
++ HAL_O,
++ HAL_P,
++ HAL_Q,
++ HAL_R,
++ HAL_S,
++ HAL_T,
++ HAL_U,
++ HAL_V,
++ HAL_W,
++ HAL_X,
++ HAL_Y,
++ HAL_Z,
++ HAL_LBRACKET,
++ HAL_BACKSLASH,
++ HAL_RBRACKET,
++ HAL_BACKQUOTE = 0x60,
++
++ HAL_F1 = 0x80,
++ HAL_F2,
++ HAL_F3,
++ HAL_F4,
++ HAL_F5,
++ HAL_F6,
++ HAL_F7,
++ HAL_F8,
++ HAL_F9,
++ HAL_F10,
++ HAL_F11,
++ HAL_F12,
++
++ HAL_LCTRL,
++ HAL_RCTRL,
++ HAL_LSHIFT,
++ HAL_RSHIFT,
++ HAL_LALT,
++ HAL_RALT,
++ HAL_CAPSLOCK,
++ HAL_NUMLOCK,
++ HAL_SCROLLLOCK,
++ HAL_PAD_0,
++ HAL_PAD_1,
++ HAL_PAD_2,
++ HAL_PAD_3,
++ HAL_PAD_4,
++ HAL_PAD_5,
++ HAL_PAD_6,
++ HAL_PAD_7,
++ HAL_PAD_8,
++ HAL_PAD_9,
++ HAL_PAD_HYPHEN,
++ HAL_PAD_PLUS,
++ HAL_PAD_SLASH,
++ HAL_PAD_PERIOD,
++ HAL_PAD_ENTER,
++ HAL_SYSRQ,
++ HAL_PRNTSCRN,
++ HAL_BREAK,
++ HAL_UP,
++ HAL_LEFT,
++ HAL_RIGHT,
++ HAL_DOWN,
++ HAL_HOME,
++ HAL_END,
++ HAL_PGUP,
++ HAL_PGDN,
++ HAL_INSERT,
++ HAL_DELETE,
++ HAL_LWINDOW,
++ HAL_RWINDOW,
++ HAL_MENU,
++ HAL_POWER,
++ HAL_SLEEP,
++ HAL_WAKE
++}
++halKeys;
++
++/* Structure that defined keyboard mapping. */
++typedef struct _halKeyMap
++{
++ /* Normal key. */
++ halKeys normal;
++
++ /* Extended key. */
++ halKeys extended;
++}
++halKeyMap;
++
++/* Event structure. */
++typedef struct _halEvent
++{
++ /* Event type. */
++ halEventType type;
++
++ /* Event data union. */
++ union _halEventData
++ {
++ /* Event data for keyboard. */
++ struct _halKeyboard
++ {
++ /* Scancode. */
++ halKeys scancode;
++
++ /* ASCII characte of the key pressed. */
++ char key;
++
++ /* Flag whether the key was pressed (1) or released (0). */
++ char pressed;
++ }
++ keyboard;
++
++ /* Event data for pointer. */
++ struct _halPointer
++ {
++ /* Current pointer coordinate. */
++ int x;
++ int y;
++ }
++ pointer;
++
++ /* Event data for mouse buttons. */
++ struct _halButton
++ {
++ /* Left button state. */
++ int left;
++
++ /* Middle button state. */
++ int middle;
++
++ /* Right button state. */
++ int right;
++
++ /* Current pointer coordinate. */
++ int x;
++ int y;
++ }
++ button;
++ }
++ data;
++}
++halEvent;
++
++/* VFK_DISPLAY_INFO structure defining information returned by
++ vdkGetDisplayInfoEx. */
++typedef struct _halDISPLAY_INFO
++{
++ /* The size of the display in pixels. */
++ int width;
++ int height;
++
++ /* The stride of the dispay. -1 is returned if the stride is not known
++ ** for the specified display.*/
++ int stride;
++
++ /* The color depth of the display in bits per pixel. */
++ int bitsPerPixel;
++
++ /* The logical pointer to the display memory buffer. NULL is returned
++ ** if the pointer is not known for the specified display. */
++ void * logical;
++
++ /* The physical address of the display memory buffer. ~0 is returned
++ ** if the address is not known for the specified display. */
++ unsigned long physical;
++
++ int wrapFB; /* true if compositor, false otherwise. */
++
++#ifndef __QNXNTO__
++ /* 355_FB_MULTI_BUFFER */
++ int multiBuffer;
++ int backBufferY;
++#endif
++
++ /* The color info of the display. */
++ unsigned int alphaLength;
++ unsigned int alphaOffset;
++ unsigned int redLength;
++ unsigned int redOffset;
++ unsigned int greenLength;
++ unsigned int greenOffset;
++ unsigned int blueLength;
++ unsigned int blueOffset;
++
++ /* Display flip support. */
++ int flip;
++}
++halDISPLAY_INFO;
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __gc_hal_eglplatform_type_h_ */
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_engine.h linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_engine.h
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_engine.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_engine.h 2015-07-27 23:13:06.214808565 +0200
+@@ -0,0 +1,2053 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_engine_h_
++#define __gc_hal_engine_h_
++
++#ifndef VIVANTE_NO_3D
++#include "gc_hal_types.h"
++#include "gc_hal_enum.h"
++
++#if gcdENABLE_VG
++#include "gc_hal_engine_vg.h"
++#endif
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/******************************************************************************\
++****************************** Object Declarations *****************************
++\******************************************************************************/
++
++typedef struct _gcoSTREAM * gcoSTREAM;
++typedef struct _gcoVERTEX * gcoVERTEX;
++typedef struct _gcoTEXTURE * gcoTEXTURE;
++typedef struct _gcoINDEX * gcoINDEX;
++typedef struct _gcsVERTEX_ATTRIBUTES * gcsVERTEX_ATTRIBUTES_PTR;
++typedef struct _gcoVERTEXARRAY * gcoVERTEXARRAY;
++
++#define gcdATTRIBUTE_COUNT 16
++
++/******************************************************************************\
++********************************* Enumerations *********************************
++\******************************************************************************/
++
++/* Shading format. */
++typedef enum _gceSHADING
++{
++ gcvSHADING_SMOOTH,
++ gcvSHADING_FLAT_D3D,
++ gcvSHADING_FLAT_OPENGL,
++}
++gceSHADING;
++
++/* Culling modes. */
++typedef enum _gceCULL
++{
++ gcvCULL_NONE,
++ gcvCULL_CCW,
++ gcvCULL_CW,
++}
++gceCULL;
++
++/* Fill modes. */
++typedef enum _gceFILL
++{
++ gcvFILL_POINT,
++ gcvFILL_WIRE_FRAME,
++ gcvFILL_SOLID,
++}
++gceFILL;
++
++/* Compare modes. */
++typedef enum _gceCOMPARE
++{
++ gcvCOMPARE_NEVER,
++ gcvCOMPARE_NOT_EQUAL,
++ gcvCOMPARE_LESS,
++ gcvCOMPARE_LESS_OR_EQUAL,
++ gcvCOMPARE_EQUAL,
++ gcvCOMPARE_GREATER,
++ gcvCOMPARE_GREATER_OR_EQUAL,
++ gcvCOMPARE_ALWAYS,
++ gcvCOMPARE_INVALID = -1
++}
++gceCOMPARE;
++
++/* Stencil modes. */
++typedef enum _gceSTENCIL_MODE
++{
++ gcvSTENCIL_NONE,
++ gcvSTENCIL_SINGLE_SIDED,
++ gcvSTENCIL_DOUBLE_SIDED,
++}
++gceSTENCIL_MODE;
++
++/* Stencil operations. */
++typedef enum _gceSTENCIL_OPERATION
++{
++ gcvSTENCIL_KEEP,
++ gcvSTENCIL_REPLACE,
++ gcvSTENCIL_ZERO,
++ gcvSTENCIL_INVERT,
++ gcvSTENCIL_INCREMENT,
++ gcvSTENCIL_DECREMENT,
++ gcvSTENCIL_INCREMENT_SATURATE,
++ gcvSTENCIL_DECREMENT_SATURATE,
++ gcvSTENCIL_OPERATION_INVALID = -1
++}
++gceSTENCIL_OPERATION;
++
++/* Stencil selection. */
++typedef enum _gceSTENCIL_WHERE
++{
++ gcvSTENCIL_FRONT,
++ gcvSTENCIL_BACK,
++}
++gceSTENCIL_WHERE;
++
++/* Texture addressing selection. */
++typedef enum _gceTEXTURE_WHICH
++{
++ gcvTEXTURE_S,
++ gcvTEXTURE_T,
++ gcvTEXTURE_R,
++}
++gceTEXTURE_WHICH;
++
++/* Texture addressing modes. */
++typedef enum _gceTEXTURE_ADDRESSING
++{
++ gcvTEXTURE_WRAP,
++ gcvTEXTURE_CLAMP,
++ gcvTEXTURE_BORDER,
++ gcvTEXTURE_MIRROR,
++ gcvTEXTURE_MIRROR_ONCE,
++}
++gceTEXTURE_ADDRESSING;
++
++/* Texture filters. */
++typedef enum _gceTEXTURE_FILTER
++{
++ gcvTEXTURE_NONE,
++ gcvTEXTURE_POINT,
++ gcvTEXTURE_LINEAR,
++ gcvTEXTURE_ANISOTROPIC,
++}
++gceTEXTURE_FILTER;
++
++/* Primitive types. */
++typedef enum _gcePRIMITIVE
++{
++ gcvPRIMITIVE_POINT_LIST,
++ gcvPRIMITIVE_LINE_LIST,
++ gcvPRIMITIVE_LINE_STRIP,
++ gcvPRIMITIVE_LINE_LOOP,
++ gcvPRIMITIVE_TRIANGLE_LIST,
++ gcvPRIMITIVE_TRIANGLE_STRIP,
++ gcvPRIMITIVE_TRIANGLE_FAN,
++ gcvPRIMITIVE_RECTANGLE,
++}
++gcePRIMITIVE;
++
++/* Index types. */
++typedef enum _gceINDEX_TYPE
++{
++ gcvINDEX_8,
++ gcvINDEX_16,
++ gcvINDEX_32,
++}
++gceINDEX_TYPE;
++
++/******************************************************************************\
++********************************* gcoHAL Object *********************************
++\******************************************************************************/
++
++/* Query the target capabilities. */
++gceSTATUS
++gcoHAL_QueryTargetCaps(
++ IN gcoHAL Hal,
++ OUT gctUINT * MaxWidth,
++ OUT gctUINT * MaxHeight,
++ OUT gctUINT * MultiTargetCount,
++ OUT gctUINT * MaxSamples
++ );
++
++gceSTATUS
++gcoHAL_SetDepthOnly(
++ IN gcoHAL Hal,
++ IN gctBOOL Enable
++ );
++
++gceSTATUS
++gcoHAL_QueryShaderCaps(
++ IN gcoHAL Hal,
++ OUT gctUINT * VertexUniforms,
++ OUT gctUINT * FragmentUniforms,
++ OUT gctUINT * Varyings
++ );
++
++gceSTATUS
++gcoHAL_QueryTextureCaps(
++ IN gcoHAL Hal,
++ OUT gctUINT * MaxWidth,
++ OUT gctUINT * MaxHeight,
++ OUT gctUINT * MaxDepth,
++ OUT gctBOOL * Cubic,
++ OUT gctBOOL * NonPowerOfTwo,
++ OUT gctUINT * VertexSamplers,
++ OUT gctUINT * PixelSamplers
++ );
++
++gceSTATUS
++gcoHAL_QueryTextureMaxAniso(
++ IN gcoHAL Hal,
++ OUT gctUINT * MaxAnisoValue
++ );
++
++gceSTATUS
++gcoHAL_QueryStreamCaps(
++ IN gcoHAL Hal,
++ OUT gctUINT32 * MaxAttributes,
++ OUT gctUINT32 * MaxStreamSize,
++ OUT gctUINT32 * NumberOfStreams,
++ OUT gctUINT32 * Alignment
++ );
++
++/******************************************************************************\
++********************************* gcoSURF Object ********************************
++\******************************************************************************/
++
++/*----------------------------------------------------------------------------*/
++/*--------------------------------- gcoSURF 3D --------------------------------*/
++
++/* Copy surface. */
++gceSTATUS
++gcoSURF_Copy(
++ IN gcoSURF Surface,
++ IN gcoSURF Source
++ );
++
++/* Clear surface. */
++gceSTATUS
++gcoSURF_Clear(
++ IN gcoSURF Surface,
++ IN gctUINT Flags
++ );
++
++/* Set number of samples for a gcoSURF object. */
++gceSTATUS
++gcoSURF_SetSamples(
++ IN gcoSURF Surface,
++ IN gctUINT Samples
++ );
++
++/* Get the number of samples per pixel. */
++gceSTATUS
++gcoSURF_GetSamples(
++ IN gcoSURF Surface,
++ OUT gctUINT_PTR Samples
++ );
++
++/* Clear rectangular surface. */
++gceSTATUS
++gcoSURF_ClearRect(
++ IN gcoSURF Surface,
++ IN gctINT Left,
++ IN gctINT Top,
++ IN gctINT Right,
++ IN gctINT Bottom,
++ IN gctUINT Flags
++ );
++
++/* TO BE REMOVED */
++ gceSTATUS
++ depr_gcoSURF_Resolve(
++ IN gcoSURF SrcSurface,
++ IN gcoSURF DestSurface,
++ IN gctUINT32 DestAddress,
++ IN gctPOINTER DestBits,
++ IN gctINT DestStride,
++ IN gceSURF_TYPE DestType,
++ IN gceSURF_FORMAT DestFormat,
++ IN gctUINT DestWidth,
++ IN gctUINT DestHeight
++ );
++
++ gceSTATUS
++ depr_gcoSURF_ResolveRect(
++ IN gcoSURF SrcSurface,
++ IN gcoSURF DestSurface,
++ IN gctUINT32 DestAddress,
++ IN gctPOINTER DestBits,
++ IN gctINT DestStride,
++ IN gceSURF_TYPE DestType,
++ IN gceSURF_FORMAT DestFormat,
++ IN gctUINT DestWidth,
++ IN gctUINT DestHeight,
++ IN gcsPOINT_PTR SrcOrigin,
++ IN gcsPOINT_PTR DestOrigin,
++ IN gcsPOINT_PTR RectSize
++ );
++
++/* Resample surface. */
++gceSTATUS
++gcoSURF_Resample(
++ IN gcoSURF SrcSurface,
++ IN gcoSURF DestSurface
++ );
++
++/* Resolve surface. */
++gceSTATUS
++gcoSURF_Resolve(
++ IN gcoSURF SrcSurface,
++ IN gcoSURF DestSurface
++ );
++
++gceSTATUS
++gcoSURF_IsHWResolveable(
++ IN gcoSURF SrcSurface,
++ IN gcoSURF DestSurface,
++ IN gcsPOINT_PTR SrcOrigin,
++ IN gcsPOINT_PTR DestOrigin,
++ IN gcsPOINT_PTR RectSize
++ );
++
++/* Resolve rectangular area of a surface. */
++gceSTATUS
++gcoSURF_ResolveRect(
++ IN gcoSURF SrcSurface,
++ IN gcoSURF DestSurface,
++ IN gcsPOINT_PTR SrcOrigin,
++ IN gcsPOINT_PTR DestOrigin,
++ IN gcsPOINT_PTR RectSize
++ );
++
++/* Set surface resolvability. */
++gceSTATUS
++gcoSURF_SetResolvability(
++ IN gcoSURF Surface,
++ IN gctBOOL Resolvable
++ );
++
++gceSTATUS
++gcoSURF_IsRenderable(
++ IN gcoSURF Surface
++ );
++
++gceSTATUS
++gcoSURF_IsFormatRenderableAsRT(
++ IN gcoSURF Surface
++ );
++
++#if gcdSYNC
++gceSTATUS
++gcoSURF_GetFence(
++ IN gcoSURF Surface
++ );
++gceSTATUS
++gcoSURF_WaitFence(
++ IN gcoSURF Surface
++ );
++
++gceSTATUS
++gcoSTREAM_GetFence(
++ IN gcoSTREAM stream
++ );
++
++gceSTATUS
++gcoSTREAM_WaitFence(
++ IN gcoSTREAM stream
++ );
++
++gceSTATUS
++gcoINDEX_GetFence(
++ IN gcoINDEX index
++ );
++
++gceSTATUS
++gcoINDEX_WaitFence(
++ IN gcoINDEX index
++ );
++#endif
++
++/******************************************************************************\
++******************************** gcoINDEX Object *******************************
++\******************************************************************************/
++
++/* Construct a new gcoINDEX object. */
++gceSTATUS
++gcoINDEX_Construct(
++ IN gcoHAL Hal,
++ OUT gcoINDEX * Index
++ );
++
++/* Destroy a gcoINDEX object. */
++gceSTATUS
++gcoINDEX_Destroy(
++ IN gcoINDEX Index
++ );
++
++/* Lock index in memory. */
++gceSTATUS
++gcoINDEX_Lock(
++ IN gcoINDEX Index,
++ OUT gctUINT32 * Address,
++ OUT gctPOINTER * Memory
++ );
++
++/* Unlock index that was previously locked with gcoINDEX_Lock. */
++gceSTATUS
++gcoINDEX_Unlock(
++ IN gcoINDEX Index
++ );
++
++/* Upload index data into the memory. */
++gceSTATUS
++gcoINDEX_Load(
++ IN gcoINDEX Index,
++ IN gceINDEX_TYPE IndexType,
++ IN gctUINT32 IndexCount,
++ IN gctPOINTER IndexBuffer
++ );
++
++/* Bind an index object to the hardware. */
++gceSTATUS
++gcoINDEX_Bind(
++ IN gcoINDEX Index,
++ IN gceINDEX_TYPE Type
++ );
++
++/* Bind an index object to the hardware. */
++gceSTATUS
++gcoINDEX_BindOffset(
++ IN gcoINDEX Index,
++ IN gceINDEX_TYPE Type,
++ IN gctUINT32 Offset
++ );
++
++/* Free existing index buffer. */
++gceSTATUS
++gcoINDEX_Free(
++ IN gcoINDEX Index
++ );
++
++/* Upload data into an index buffer. */
++gceSTATUS
++gcoINDEX_Upload(
++ IN gcoINDEX Index,
++ IN gctCONST_POINTER Buffer,
++ IN gctSIZE_T Bytes
++ );
++
++/* Upload data into an index buffer starting at an offset. */
++gceSTATUS
++gcoINDEX_UploadOffset(
++ IN gcoINDEX Index,
++ IN gctUINT32 Offset,
++ IN gctCONST_POINTER Buffer,
++ IN gctSIZE_T Bytes
++ );
++
++/*Merge index2 to index1 from 0, index2 must subset of inex1*/
++gceSTATUS
++gcoINDEX_Merge(
++ IN gcoINDEX Index1,
++ IN gcoINDEX Index2
++ );
++
++/*check if index buffer is enough for this draw*/
++gctBOOL
++gcoINDEX_CheckRange(
++ IN gcoINDEX Index,
++ IN gceINDEX_TYPE Type,
++ IN gctINT Count,
++ IN gctUINT32 Indices
++ );
++
++/* Query the index capabilities. */
++gceSTATUS
++gcoINDEX_QueryCaps(
++ OUT gctBOOL * Index8,
++ OUT gctBOOL * Index16,
++ OUT gctBOOL * Index32,
++ OUT gctUINT * MaxIndex
++ );
++
++/* Determine the index range in the current index buffer. */
++gceSTATUS
++gcoINDEX_GetIndexRange(
++ IN gcoINDEX Index,
++ IN gceINDEX_TYPE Type,
++ IN gctUINT32 Offset,
++ IN gctUINT32 Count,
++ OUT gctUINT32 * MinimumIndex,
++ OUT gctUINT32 * MaximumIndex
++ );
++
++/* Dynamic buffer management. */
++gceSTATUS
++gcoINDEX_SetDynamic(
++ IN gcoINDEX Index,
++ IN gctSIZE_T Bytes,
++ IN gctUINT Buffers
++ );
++
++gceSTATUS
++gcoINDEX_UploadDynamic(
++ IN gcoINDEX Index,
++ IN gctCONST_POINTER Data,
++ IN gctSIZE_T Bytes
++ );
++
++/******************************************************************************\
++********************************** gco3D Object *********************************
++\******************************************************************************/
++
++/* Clear flags. */
++typedef enum _gceCLEAR
++{
++ gcvCLEAR_COLOR = 0x1,
++ gcvCLEAR_DEPTH = 0x2,
++ gcvCLEAR_STENCIL = 0x4,
++ gcvCLEAR_HZ = 0x8,
++ gcvCLEAR_HAS_VAA = 0x10,
++}
++gceCLEAR;
++
++/* Blending targets. */
++typedef enum _gceBLEND_UNIT
++{
++ gcvBLEND_SOURCE,
++ gcvBLEND_TARGET,
++}
++gceBLEND_UNIT;
++
++/* Construct a new gco3D object. */
++gceSTATUS
++gco3D_Construct(
++ IN gcoHAL Hal,
++ OUT gco3D * Engine
++ );
++
++/* Destroy an gco3D object. */
++gceSTATUS
++gco3D_Destroy(
++ IN gco3D Engine
++ );
++
++/* Set 3D API type. */
++gceSTATUS
++gco3D_SetAPI(
++ IN gco3D Engine,
++ IN gceAPI ApiType
++ );
++
++/* Set render target. */
++gceSTATUS
++gco3D_SetTarget(
++ IN gco3D Engine,
++ IN gcoSURF Surface
++ );
++
++/* Unset render target. */
++gceSTATUS
++gco3D_UnsetTarget(
++ IN gco3D Engine,
++ IN gcoSURF Surface
++ );
++
++/* Set depth buffer. */
++gceSTATUS
++gco3D_SetDepth(
++ IN gco3D Engine,
++ IN gcoSURF Surface
++ );
++
++/* Unset depth buffer. */
++gceSTATUS
++gco3D_UnsetDepth(
++ IN gco3D Engine,
++ IN gcoSURF Surface
++ );
++
++/* Set viewport. */
++gceSTATUS
++gco3D_SetViewport(
++ IN gco3D Engine,
++ IN gctINT32 Left,
++ IN gctINT32 Top,
++ IN gctINT32 Right,
++ IN gctINT32 Bottom
++ );
++
++/* Set scissors. */
++gceSTATUS
++gco3D_SetScissors(
++ IN gco3D Engine,
++ IN gctINT32 Left,
++ IN gctINT32 Top,
++ IN gctINT32 Right,
++ IN gctINT32 Bottom
++ );
++
++/* Set clear color. */
++gceSTATUS
++gco3D_SetClearColor(
++ IN gco3D Engine,
++ IN gctUINT8 Red,
++ IN gctUINT8 Green,
++ IN gctUINT8 Blue,
++ IN gctUINT8 Alpha
++ );
++
++/* Set fixed point clear color. */
++gceSTATUS
++gco3D_SetClearColorX(
++ IN gco3D Engine,
++ IN gctFIXED_POINT Red,
++ IN gctFIXED_POINT Green,
++ IN gctFIXED_POINT Blue,
++ IN gctFIXED_POINT Alpha
++ );
++
++/* Set floating point clear color. */
++gceSTATUS
++gco3D_SetClearColorF(
++ IN gco3D Engine,
++ IN gctFLOAT Red,
++ IN gctFLOAT Green,
++ IN gctFLOAT Blue,
++ IN gctFLOAT Alpha
++ );
++
++/* Set fixed point clear depth. */
++gceSTATUS
++gco3D_SetClearDepthX(
++ IN gco3D Engine,
++ IN gctFIXED_POINT Depth
++ );
++
++/* Set floating point clear depth. */
++gceSTATUS
++gco3D_SetClearDepthF(
++ IN gco3D Engine,
++ IN gctFLOAT Depth
++ );
++
++/* Set clear stencil. */
++gceSTATUS
++gco3D_SetClearStencil(
++ IN gco3D Engine,
++ IN gctUINT32 Stencil
++ );
++
++/* Clear a Rect sub-surface. */
++gceSTATUS
++gco3D_ClearRect(
++ IN gco3D Engine,
++ IN gctUINT32 Address,
++ IN gctPOINTER Memory,
++ IN gctUINT32 Stride,
++ IN gceSURF_FORMAT Format,
++ IN gctINT32 Left,
++ IN gctINT32 Top,
++ IN gctINT32 Right,
++ IN gctINT32 Bottom,
++ IN gctUINT32 Width,
++ IN gctUINT32 Height,
++ IN gctUINT32 Flags
++ );
++
++/* Clear surface. */
++gceSTATUS
++gco3D_Clear(
++ IN gco3D Engine,
++ IN gctUINT32 Address,
++ IN gctUINT32 Stride,
++ IN gceSURF_FORMAT Format,
++ IN gctUINT32 Width,
++ IN gctUINT32 Height,
++ IN gctUINT32 Flags
++ );
++
++
++/* Clear tile status. */
++gceSTATUS
++gco3D_ClearTileStatus(
++ IN gco3D Engine,
++ IN gcsSURF_INFO_PTR Surface,
++ IN gctUINT32 TileStatusAddress,
++ IN gctUINT32 Flags
++ );
++
++/* Set shading mode. */
++gceSTATUS
++gco3D_SetShading(
++ IN gco3D Engine,
++ IN gceSHADING Shading
++ );
++
++/* Set blending mode. */
++gceSTATUS
++gco3D_EnableBlending(
++ IN gco3D Engine,
++ IN gctBOOL Enable
++ );
++
++/* Set blending function. */
++gceSTATUS
++gco3D_SetBlendFunction(
++ IN gco3D Engine,
++ IN gceBLEND_UNIT Unit,
++ IN gceBLEND_FUNCTION FunctionRGB,
++ IN gceBLEND_FUNCTION FunctionAlpha
++ );
++
++/* Set blending mode. */
++gceSTATUS
++gco3D_SetBlendMode(
++ IN gco3D Engine,
++ IN gceBLEND_MODE ModeRGB,
++ IN gceBLEND_MODE ModeAlpha
++ );
++
++/* Set blending color. */
++gceSTATUS
++gco3D_SetBlendColor(
++ IN gco3D Engine,
++ IN gctUINT Red,
++ IN gctUINT Green,
++ IN gctUINT Blue,
++ IN gctUINT Alpha
++ );
++
++/* Set fixed point blending color. */
++gceSTATUS
++gco3D_SetBlendColorX(
++ IN gco3D Engine,
++ IN gctFIXED_POINT Red,
++ IN gctFIXED_POINT Green,
++ IN gctFIXED_POINT Blue,
++ IN gctFIXED_POINT Alpha
++ );
++
++/* Set floating point blending color. */
++gceSTATUS
++gco3D_SetBlendColorF(
++ IN gco3D Engine,
++ IN gctFLOAT Red,
++ IN gctFLOAT Green,
++ IN gctFLOAT Blue,
++ IN gctFLOAT Alpha
++ );
++
++/* Set culling mode. */
++gceSTATUS
++gco3D_SetCulling(
++ IN gco3D Engine,
++ IN gceCULL Mode
++ );
++
++/* Enable point size */
++gceSTATUS
++gco3D_SetPointSizeEnable(
++ IN gco3D Engine,
++ IN gctBOOL Enable
++ );
++
++/* Set point sprite */
++gceSTATUS
++gco3D_SetPointSprite(
++ IN gco3D Engine,
++ IN gctBOOL Enable
++ );
++
++/* Set fill mode. */
++gceSTATUS
++gco3D_SetFill(
++ IN gco3D Engine,
++ IN gceFILL Mode
++ );
++
++/* Set depth compare mode. */
++gceSTATUS
++gco3D_SetDepthCompare(
++ IN gco3D Engine,
++ IN gceCOMPARE Compare
++ );
++
++/* Enable depth writing. */
++gceSTATUS
++gco3D_EnableDepthWrite(
++ IN gco3D Engine,
++ IN gctBOOL Enable
++ );
++
++/* Set depth mode. */
++gceSTATUS
++gco3D_SetDepthMode(
++ IN gco3D Engine,
++ IN gceDEPTH_MODE Mode
++ );
++
++/* Set depth range. */
++gceSTATUS
++gco3D_SetDepthRangeX(
++ IN gco3D Engine,
++ IN gceDEPTH_MODE Mode,
++ IN gctFIXED_POINT Near,
++ IN gctFIXED_POINT Far
++ );
++
++/* Set depth range. */
++gceSTATUS
++gco3D_SetDepthRangeF(
++ IN gco3D Engine,
++ IN gceDEPTH_MODE Mode,
++ IN gctFLOAT Near,
++ IN gctFLOAT Far
++ );
++
++/* Set last pixel enable */
++gceSTATUS
++gco3D_SetLastPixelEnable(
++ IN gco3D Engine,
++ IN gctBOOL Enable
++ );
++
++/* Set depth Bias and Scale */
++gceSTATUS
++gco3D_SetDepthScaleBiasX(
++ IN gco3D Engine,
++ IN gctFIXED_POINT DepthScale,
++ IN gctFIXED_POINT DepthBias
++ );
++
++gceSTATUS
++gco3D_SetDepthScaleBiasF(
++ IN gco3D Engine,
++ IN gctFLOAT DepthScale,
++ IN gctFLOAT DepthBias
++ );
++
++/* Set depth near and far clipping plane. */
++gceSTATUS
++gco3D_SetDepthPlaneF(
++ IN gco3D Engine,
++ IN gctFLOAT Near,
++ IN gctFLOAT Far
++ );
++
++/* Enable or disable dithering. */
++gceSTATUS
++gco3D_EnableDither(
++ IN gco3D Engine,
++ IN gctBOOL Enable
++ );
++
++/* Set color write enable bits. */
++gceSTATUS
++gco3D_SetColorWrite(
++ IN gco3D Engine,
++ IN gctUINT8 Enable
++ );
++
++/* Enable or disable early depth. */
++gceSTATUS
++gco3D_SetEarlyDepth(
++ IN gco3D Engine,
++ IN gctBOOL Enable
++ );
++
++/* Enable or disable all early depth operations. */
++gceSTATUS
++gco3D_SetAllEarlyDepthModes(
++ IN gco3D Engine,
++ IN gctBOOL Disable
++ );
++
++/* Switch dynamic early mode */
++gceSTATUS
++gco3D_SwitchDynamicEarlyDepthMode(
++ IN gco3D Engine
++ );
++
++/* Set dynamic early mode */
++gceSTATUS
++gco3D_DisableDynamicEarlyDepthMode(
++ IN gco3D Engine,
++ IN gctBOOL Disable
++ );
++
++/* Enable or disable depth-only mode. */
++gceSTATUS
++gco3D_SetDepthOnly(
++ IN gco3D Engine,
++ IN gctBOOL Enable
++ );
++
++typedef struct _gcsSTENCIL_INFO * gcsSTENCIL_INFO_PTR;
++typedef struct _gcsSTENCIL_INFO
++{
++ gceSTENCIL_MODE mode;
++
++ gctUINT8 maskFront;
++ gctUINT8 maskBack;
++ gctUINT8 writeMaskFront;
++ gctUINT8 writeMaskBack;
++
++ gctUINT8 referenceFront;
++
++ gceCOMPARE compareFront;
++ gceSTENCIL_OPERATION passFront;
++ gceSTENCIL_OPERATION failFront;
++ gceSTENCIL_OPERATION depthFailFront;
++
++ gctUINT8 referenceBack;
++ gceCOMPARE compareBack;
++ gceSTENCIL_OPERATION passBack;
++ gceSTENCIL_OPERATION failBack;
++ gceSTENCIL_OPERATION depthFailBack;
++}
++gcsSTENCIL_INFO;
++
++/* Set stencil mode. */
++gceSTATUS
++gco3D_SetStencilMode(
++ IN gco3D Engine,
++ IN gceSTENCIL_MODE Mode
++ );
++
++/* Set stencil mask. */
++gceSTATUS
++gco3D_SetStencilMask(
++ IN gco3D Engine,
++ IN gctUINT8 Mask
++ );
++
++/* Set stencil back mask. */
++gceSTATUS
++gco3D_SetStencilMaskBack(
++ IN gco3D Engine,
++ IN gctUINT8 Mask
++ );
++
++/* Set stencil write mask. */
++gceSTATUS
++gco3D_SetStencilWriteMask(
++ IN gco3D Engine,
++ IN gctUINT8 Mask
++ );
++
++/* Set stencil back write mask. */
++gceSTATUS
++gco3D_SetStencilWriteMaskBack(
++ IN gco3D Engine,
++ IN gctUINT8 Mask
++ );
++
++/* Set stencil reference. */
++gceSTATUS
++gco3D_SetStencilReference(
++ IN gco3D Engine,
++ IN gctUINT8 Reference,
++ IN gctBOOL Front
++ );
++
++/* Set stencil compare. */
++gceSTATUS
++gco3D_SetStencilCompare(
++ IN gco3D Engine,
++ IN gceSTENCIL_WHERE Where,
++ IN gceCOMPARE Compare
++ );
++
++/* Set stencil operation on pass. */
++gceSTATUS
++gco3D_SetStencilPass(
++ IN gco3D Engine,
++ IN gceSTENCIL_WHERE Where,
++ IN gceSTENCIL_OPERATION Operation
++ );
++
++/* Set stencil operation on fail. */
++gceSTATUS
++gco3D_SetStencilFail(
++ IN gco3D Engine,
++ IN gceSTENCIL_WHERE Where,
++ IN gceSTENCIL_OPERATION Operation
++ );
++
++/* Set stencil operation on depth fail. */
++gceSTATUS
++gco3D_SetStencilDepthFail(
++ IN gco3D Engine,
++ IN gceSTENCIL_WHERE Where,
++ IN gceSTENCIL_OPERATION Operation
++ );
++
++/* Set all stencil states in one blow. */
++gceSTATUS
++gco3D_SetStencilAll(
++ IN gco3D Engine,
++ IN gcsSTENCIL_INFO_PTR Info
++ );
++
++typedef struct _gcsALPHA_INFO * gcsALPHA_INFO_PTR;
++typedef struct _gcsALPHA_INFO
++{
++ /* Alpha test states. */
++ gctBOOL test;
++ gceCOMPARE compare;
++ gctUINT8 reference;
++ gctFLOAT floatReference;
++
++ /* Alpha blending states. */
++ gctBOOL blend;
++
++ gceBLEND_FUNCTION srcFuncColor;
++ gceBLEND_FUNCTION srcFuncAlpha;
++ gceBLEND_FUNCTION trgFuncColor;
++ gceBLEND_FUNCTION trgFuncAlpha;
++
++ gceBLEND_MODE modeColor;
++ gceBLEND_MODE modeAlpha;
++
++ gctUINT32 color;
++}
++gcsALPHA_INFO;
++
++/* Enable or disable alpha test. */
++gceSTATUS
++gco3D_SetAlphaTest(
++ IN gco3D Engine,
++ IN gctBOOL Enable
++ );
++
++/* Set alpha test compare. */
++gceSTATUS
++gco3D_SetAlphaCompare(
++ IN gco3D Engine,
++ IN gceCOMPARE Compare
++ );
++
++/* Set alpha test reference in unsigned integer. */
++gceSTATUS
++gco3D_SetAlphaReference(
++ IN gco3D Engine,
++ IN gctUINT8 Reference,
++ IN gctFLOAT FloatReference
++ );
++
++/* Set alpha test reference in fixed point. */
++gceSTATUS
++gco3D_SetAlphaReferenceX(
++ IN gco3D Engine,
++ IN gctFIXED_POINT Reference
++ );
++
++/* Set alpha test reference in floating point. */
++gceSTATUS
++gco3D_SetAlphaReferenceF(
++ IN gco3D Engine,
++ IN gctFLOAT Reference
++ );
++
++/* Enable/Disable anti-alias line. */
++gceSTATUS
++gco3D_SetAntiAliasLine(
++ IN gco3D Engine,
++ IN gctBOOL Enable
++ );
++
++/* Set texture slot for anti-alias line. */
++gceSTATUS
++gco3D_SetAALineTexSlot(
++ IN gco3D Engine,
++ IN gctUINT TexSlot
++ );
++
++/* Set anti-alias line width scale. */
++gceSTATUS
++gco3D_SetAALineWidth(
++ IN gco3D Engine,
++ IN gctFLOAT Width
++ );
++
++/* Draw a number of primitives. */
++gceSTATUS
++gco3D_DrawPrimitives(
++ IN gco3D Engine,
++ IN gcePRIMITIVE Type,
++ IN gctINT StartVertex,
++ IN gctSIZE_T PrimitiveCount
++ );
++
++gceSTATUS
++gco3D_DrawPrimitivesCount(
++ IN gco3D Engine,
++ IN gcePRIMITIVE Type,
++ IN gctINT* StartVertex,
++ IN gctSIZE_T* VertexCount,
++ IN gctSIZE_T PrimitiveCount
++ );
++
++
++/* Draw a number of primitives using offsets. */
++gceSTATUS
++gco3D_DrawPrimitivesOffset(
++ IN gco3D Engine,
++ IN gcePRIMITIVE Type,
++ IN gctINT32 StartOffset,
++ IN gctSIZE_T PrimitiveCount
++ );
++
++/* Draw a number of indexed primitives. */
++gceSTATUS
++gco3D_DrawIndexedPrimitives(
++ IN gco3D Engine,
++ IN gcePRIMITIVE Type,
++ IN gctINT BaseVertex,
++ IN gctINT StartIndex,
++ IN gctSIZE_T PrimitiveCount
++ );
++
++/* Draw a number of indexed primitives using offsets. */
++gceSTATUS
++gco3D_DrawIndexedPrimitivesOffset(
++ IN gco3D Engine,
++ IN gcePRIMITIVE Type,
++ IN gctINT32 BaseOffset,
++ IN gctINT32 StartOffset,
++ IN gctSIZE_T PrimitiveCount
++ );
++
++/* Enable or disable anti-aliasing. */
++gceSTATUS
++gco3D_SetAntiAlias(
++ IN gco3D Engine,
++ IN gctBOOL Enable
++ );
++
++/* Write data into the command buffer. */
++gceSTATUS
++gco3D_WriteBuffer(
++ IN gco3D Engine,
++ IN gctCONST_POINTER Data,
++ IN gctSIZE_T Bytes,
++ IN gctBOOL Aligned
++ );
++
++/* Send sempahore and stall until sempahore is signalled. */
++gceSTATUS
++gco3D_Semaphore(
++ IN gco3D Engine,
++ IN gceWHERE From,
++ IN gceWHERE To,
++ IN gceHOW How);
++
++/* Set the subpixels center. */
++gceSTATUS
++gco3D_SetCentroids(
++ IN gco3D Engine,
++ IN gctUINT32 Index,
++ IN gctPOINTER Centroids
++ );
++
++gceSTATUS
++gco3D_SetLogicOp(
++ IN gco3D Engine,
++ IN gctUINT8 Rop
++ );
++
++/* OCL thread walker information. */
++typedef struct _gcsTHREAD_WALKER_INFO * gcsTHREAD_WALKER_INFO_PTR;
++typedef struct _gcsTHREAD_WALKER_INFO
++{
++ gctUINT32 dimensions;
++ gctUINT32 traverseOrder;
++ gctUINT32 enableSwathX;
++ gctUINT32 enableSwathY;
++ gctUINT32 enableSwathZ;
++ gctUINT32 swathSizeX;
++ gctUINT32 swathSizeY;
++ gctUINT32 swathSizeZ;
++ gctUINT32 valueOrder;
++
++ gctUINT32 globalSizeX;
++ gctUINT32 globalOffsetX;
++ gctUINT32 globalSizeY;
++ gctUINT32 globalOffsetY;
++ gctUINT32 globalSizeZ;
++ gctUINT32 globalOffsetZ;
++
++ gctUINT32 workGroupSizeX;
++ gctUINT32 workGroupCountX;
++ gctUINT32 workGroupSizeY;
++ gctUINT32 workGroupCountY;
++ gctUINT32 workGroupSizeZ;
++ gctUINT32 workGroupCountZ;
++
++ gctUINT32 threadAllocation;
++}
++gcsTHREAD_WALKER_INFO;
++
++/* Start OCL thread walker. */
++gceSTATUS
++gco3D_InvokeThreadWalker(
++ IN gco3D Engine,
++ IN gcsTHREAD_WALKER_INFO_PTR Info
++ );
++
++/* Set w clip and w plane limit value. */
++gceSTATUS
++gco3D_SetWClipEnable(
++ IN gco3D Engine,
++ IN gctBOOL Enable
++ );
++
++gceSTATUS
++gco3D_GetWClipEnable(
++ IN gco3D Engine,
++ OUT gctBOOL * Enable
++ );
++
++gceSTATUS
++gco3D_SetWPlaneLimitF(
++ IN gco3D Engine,
++ IN gctFLOAT Value
++ );
++
++gceSTATUS
++gco3D_SetWPlaneLimitX(
++ IN gco3D Engine,
++ IN gctFIXED_POINT Value
++ );
++
++
++gceSTATUS
++gco3D_SetWPlaneLimit(
++ IN gco3D Engine,
++ IN gctFLOAT Value
++ );
++
++/*----------------------------------------------------------------------------*/
++/*-------------------------- gco3D Fragment Processor ------------------------*/
++
++/* Set the fragment processor configuration. */
++gceSTATUS
++gco3D_SetFragmentConfiguration(
++ IN gco3D Engine,
++ IN gctBOOL ColorFromStream,
++ IN gctBOOL EnableFog,
++ IN gctBOOL EnableSmoothPoint,
++ IN gctUINT32 ClipPlanes
++ );
++
++/* Enable/disable texture stage operation. */
++gceSTATUS
++gco3D_EnableTextureStage(
++ IN gco3D Engine,
++ IN gctINT Stage,
++ IN gctBOOL Enable
++ );
++
++/* Program the channel enable masks for the color texture function. */
++gceSTATUS
++gco3D_SetTextureColorMask(
++ IN gco3D Engine,
++ IN gctINT Stage,
++ IN gctBOOL ColorEnabled,
++ IN gctBOOL AlphaEnabled
++ );
++
++/* Program the channel enable masks for the alpha texture function. */
++gceSTATUS
++gco3D_SetTextureAlphaMask(
++ IN gco3D Engine,
++ IN gctINT Stage,
++ IN gctBOOL ColorEnabled,
++ IN gctBOOL AlphaEnabled
++ );
++
++/* Program the constant fragment color. */
++gceSTATUS
++gco3D_SetFragmentColorX(
++ IN gco3D Engine,
++ IN gctFIXED_POINT Red,
++ IN gctFIXED_POINT Green,
++ IN gctFIXED_POINT Blue,
++ IN gctFIXED_POINT Alpha
++ );
++
++gceSTATUS
++gco3D_SetFragmentColorF(
++ IN gco3D Engine,
++ IN gctFLOAT Red,
++ IN gctFLOAT Green,
++ IN gctFLOAT Blue,
++ IN gctFLOAT Alpha
++ );
++
++/* Program the constant fog color. */
++gceSTATUS
++gco3D_SetFogColorX(
++ IN gco3D Engine,
++ IN gctFIXED_POINT Red,
++ IN gctFIXED_POINT Green,
++ IN gctFIXED_POINT Blue,
++ IN gctFIXED_POINT Alpha
++ );
++
++gceSTATUS
++gco3D_SetFogColorF(
++ IN gco3D Engine,
++ IN gctFLOAT Red,
++ IN gctFLOAT Green,
++ IN gctFLOAT Blue,
++ IN gctFLOAT Alpha
++ );
++
++/* Program the constant texture color. */
++gceSTATUS
++gco3D_SetTetxureColorX(
++ IN gco3D Engine,
++ IN gctINT Stage,
++ IN gctFIXED_POINT Red,
++ IN gctFIXED_POINT Green,
++ IN gctFIXED_POINT Blue,
++ IN gctFIXED_POINT Alpha
++ );
++
++gceSTATUS
++gco3D_SetTetxureColorF(
++ IN gco3D Engine,
++ IN gctINT Stage,
++ IN gctFLOAT Red,
++ IN gctFLOAT Green,
++ IN gctFLOAT Blue,
++ IN gctFLOAT Alpha
++ );
++
++/* Configure color texture function. */
++gceSTATUS
++gco3D_SetColorTextureFunction(
++ IN gco3D Engine,
++ IN gctINT Stage,
++ IN gceTEXTURE_FUNCTION Function,
++ IN gceTEXTURE_SOURCE Source0,
++ IN gceTEXTURE_CHANNEL Channel0,
++ IN gceTEXTURE_SOURCE Source1,
++ IN gceTEXTURE_CHANNEL Channel1,
++ IN gceTEXTURE_SOURCE Source2,
++ IN gceTEXTURE_CHANNEL Channel2,
++ IN gctINT Scale
++ );
++
++/* Configure alpha texture function. */
++gceSTATUS
++gco3D_SetAlphaTextureFunction(
++ IN gco3D Engine,
++ IN gctINT Stage,
++ IN gceTEXTURE_FUNCTION Function,
++ IN gceTEXTURE_SOURCE Source0,
++ IN gceTEXTURE_CHANNEL Channel0,
++ IN gceTEXTURE_SOURCE Source1,
++ IN gceTEXTURE_CHANNEL Channel1,
++ IN gceTEXTURE_SOURCE Source2,
++ IN gceTEXTURE_CHANNEL Channel2,
++ IN gctINT Scale
++ );
++
++/* Invoke OCL thread walker. */
++gceSTATUS
++gcoHARDWARE_InvokeThreadWalker(
++ IN gcsTHREAD_WALKER_INFO_PTR Info
++ );
++
++/******************************************************************************\
++******************************* gcoTEXTURE Object *******************************
++\******************************************************************************/
++
++/* Cube faces. */
++typedef enum _gceTEXTURE_FACE
++{
++ gcvFACE_NONE,
++ gcvFACE_POSITIVE_X,
++ gcvFACE_NEGATIVE_X,
++ gcvFACE_POSITIVE_Y,
++ gcvFACE_NEGATIVE_Y,
++ gcvFACE_POSITIVE_Z,
++ gcvFACE_NEGATIVE_Z,
++}
++gceTEXTURE_FACE;
++
++#if gcdFORCE_MIPMAP
++typedef enum
++{
++ gcvForceMipDisabled = 0,
++ gcvForceMipEnable = 1,
++ gcvForceMipGenerated = 2,
++ gcvForceMipNever = 3,
++}gceFORCE_MIPMAP;
++#endif
++
++typedef struct _gcsTEXTURE
++{
++ /* Addressing modes. */
++ gceTEXTURE_ADDRESSING s;
++ gceTEXTURE_ADDRESSING t;
++ gceTEXTURE_ADDRESSING r;
++
++ /* Border color. */
++ gctUINT8 border[4];
++
++ /* Filters. */
++ gceTEXTURE_FILTER minFilter;
++ gceTEXTURE_FILTER magFilter;
++ gceTEXTURE_FILTER mipFilter;
++ gctUINT anisoFilter;
++ gctBOOL forceTopLevel;
++ gctBOOL autoMipmap;
++#if gcdFORCE_MIPMAP
++ gceFORCE_MIPMAP forceMipmap;
++#endif
++ /* Level of detail. */
++ gctFIXED_POINT lodBias;
++ gctFIXED_POINT lodMin;
++ gctFIXED_POINT lodMax;
++}
++gcsTEXTURE, * gcsTEXTURE_PTR;
++
++/* Construct a new gcoTEXTURE object. */
++gceSTATUS
++gcoTEXTURE_Construct(
++ IN gcoHAL Hal,
++ OUT gcoTEXTURE * Texture
++ );
++
++/* Construct a new sized gcoTEXTURE object. */
++gceSTATUS
++gcoTEXTURE_ConstructSized(
++ IN gcoHAL Hal,
++ IN gceSURF_FORMAT Format,
++ IN gctUINT Width,
++ IN gctUINT Height,
++ IN gctUINT Depth,
++ IN gctUINT Faces,
++ IN gctUINT MipMapCount,
++ IN gcePOOL Pool,
++ OUT gcoTEXTURE * Texture
++ );
++
++/* Destroy an gcoTEXTURE object. */
++gceSTATUS
++gcoTEXTURE_Destroy(
++ IN gcoTEXTURE Texture
++ );
++#if gcdFORCE_MIPMAP
++gceSTATUS
++gcoTEXTURE_DestroyForceMipmap(
++ IN gcoTEXTURE Texture
++ );
++
++gceSTATUS
++gcoTEXTURE_GetMipLevels(
++ IN gcoTEXTURE Texture,
++ OUT gctINT * levels
++ );
++#endif
++/* Replace a mipmap in gcoTEXTURE object. */
++gceSTATUS
++gcoTEXTURE_ReplaceMipMap(
++ IN gcoTEXTURE Texture,
++ IN gctUINT Level,
++ IN gctUINT Width,
++ IN gctUINT Height,
++ IN gctINT imageFormat,
++ IN gceSURF_FORMAT Format,
++ IN gctUINT Depth,
++ IN gctUINT Faces,
++ IN gcePOOL Pool
++ );
++
++/* Upload data to an gcoTEXTURE object. */
++gceSTATUS
++gcoTEXTURE_Upload(
++ IN gcoTEXTURE Texture,
++ IN gceTEXTURE_FACE Face,
++ IN gctUINT Width,
++ IN gctUINT Height,
++ IN gctUINT Slice,
++ IN gctCONST_POINTER Memory,
++ IN gctINT Stride,
++ IN gceSURF_FORMAT Format
++ );
++
++/* Upload data to an gcoTEXTURE object. */
++gceSTATUS
++gcoTEXTURE_UploadSub(
++ IN gcoTEXTURE Texture,
++ IN gctUINT MipMap,
++ IN gceTEXTURE_FACE Face,
++ IN gctUINT X,
++ IN gctUINT Y,
++ IN gctUINT Width,
++ IN gctUINT Height,
++ IN gctUINT Slice,
++ IN gctCONST_POINTER Memory,
++ IN gctINT Stride,
++ IN gceSURF_FORMAT Format
++ );
++
++/* Upload YUV data to an gcoTEXTURE object. */
++gceSTATUS
++gcoTEXTURE_UploadYUV(
++ IN gcoTEXTURE Texture,
++ IN gceTEXTURE_FACE Face,
++ IN gctUINT Width,
++ IN gctUINT Height,
++ IN gctUINT Slice,
++ IN gctPOINTER Memory[3],
++ IN gctINT Stride[3],
++ IN gceSURF_FORMAT Format
++ );
++
++/* Upload compressed data to an gcoTEXTURE object. */
++gceSTATUS
++gcoTEXTURE_UploadCompressed(
++ IN gcoTEXTURE Texture,
++ IN gceTEXTURE_FACE Face,
++ IN gctUINT Width,
++ IN gctUINT Height,
++ IN gctUINT Slice,
++ IN gctCONST_POINTER Memory,
++ IN gctSIZE_T Bytes
++ );
++
++/* Upload compressed sub data to an gcoTEXTURE object. */
++gceSTATUS
++gcoTEXTURE_UploadCompressedSub(
++ IN gcoTEXTURE Texture,
++ IN gctUINT MipMap,
++ IN gceTEXTURE_FACE Face,
++ IN gctUINT XOffset,
++ IN gctUINT YOffset,
++ IN gctUINT Width,
++ IN gctUINT Height,
++ IN gctUINT Slice,
++ IN gctCONST_POINTER Memory,
++ IN gctSIZE_T Size
++ );
++
++/* GetImageFormat of texture. */
++gceSTATUS
++gcoTEXTURE_GetImageFormat(
++ IN gcoTEXTURE Texture,
++ IN gctUINT MipMap,
++ OUT gctINT * ImageFormat
++ );
++
++/* Get gcoSURF object for a mipmap level. */
++gceSTATUS
++gcoTEXTURE_GetMipMap(
++ IN gcoTEXTURE Texture,
++ IN gctUINT MipMap,
++ OUT gcoSURF * Surface
++ );
++
++/* Get gcoSURF object for a mipmap level and face offset. */
++gceSTATUS
++gcoTEXTURE_GetMipMapFace(
++ IN gcoTEXTURE Texture,
++ IN gctUINT MipMap,
++ IN gceTEXTURE_FACE Face,
++ OUT gcoSURF * Surface,
++ OUT gctUINT32_PTR Offset
++ );
++
++gceSTATUS
++gcoTEXTURE_AddMipMap(
++ IN gcoTEXTURE Texture,
++ IN gctINT Level,
++ IN gctINT imageFormat,
++ IN gceSURF_FORMAT Format,
++ IN gctUINT Width,
++ IN gctUINT Height,
++ IN gctUINT Depth,
++ IN gctUINT Faces,
++ IN gcePOOL Pool,
++ OUT gcoSURF * Surface
++ );
++
++gceSTATUS
++gcoTEXTURE_AddMipMapFromClient(
++ IN gcoTEXTURE Texture,
++ IN gctINT Level,
++ IN gcoSURF Surface
++ );
++
++gceSTATUS
++gcoTEXTURE_AddMipMapFromSurface(
++ IN gcoTEXTURE Texture,
++ IN gctINT Level,
++ IN gcoSURF Surface
++ );
++
++gceSTATUS
++gcoTEXTURE_SetMaxLevel(
++ IN gcoTEXTURE Texture,
++ IN gctUINT Levels
++ );
++
++gceSTATUS
++gcoTEXTURE_SetEndianHint(
++ IN gcoTEXTURE Texture,
++ IN gceENDIAN_HINT EndianHint
++ );
++
++gceSTATUS
++gcoTEXTURE_Disable(
++ IN gcoHAL Hal,
++ IN gctINT Sampler
++ );
++
++gceSTATUS
++gcoTEXTURE_Flush(
++ IN gcoTEXTURE Texture
++ );
++
++gceSTATUS
++gcoTEXTURE_QueryCaps(
++ IN gcoHAL Hal,
++ OUT gctUINT * MaxWidth,
++ OUT gctUINT * MaxHeight,
++ OUT gctUINT * MaxDepth,
++ OUT gctBOOL * Cubic,
++ OUT gctBOOL * NonPowerOfTwo,
++ OUT gctUINT * VertexSamplers,
++ OUT gctUINT * PixelSamplers
++ );
++
++gceSTATUS
++gcoTEXTURE_GetTiling(
++ IN gcoTEXTURE Texture,
++ IN gctINT preferLevel,
++ OUT gceTILING * Tiling
++ );
++
++gceSTATUS
++gcoTEXTURE_GetClosestFormat(
++ IN gcoHAL Hal,
++ IN gceSURF_FORMAT InFormat,
++ OUT gceSURF_FORMAT* OutFormat
++ );
++
++gceSTATUS
++gcoTEXTURE_RenderIntoMipMap(
++ IN gcoTEXTURE Texture,
++ IN gctINT Level
++ );
++
++gceSTATUS
++gcoTEXTURE_IsRenderable(
++ IN gcoTEXTURE Texture,
++ IN gctUINT Level
++ );
++
++gceSTATUS
++gcoTEXTURE_IsRenderableEx(
++ IN gcoTEXTURE Texture,
++ IN gctUINT Level
++ );
++
++gceSTATUS
++gcoTEXTURE_IsComplete(
++ IN gcoTEXTURE Texture,
++ IN gctINT MaxLevel
++ );
++
++gceSTATUS
++gcoTEXTURE_BindTexture(
++ IN gcoTEXTURE Texture,
++ IN gctINT Target,
++ IN gctINT Sampler,
++ IN gcsTEXTURE_PTR Info
++ );
++
++/******************************************************************************\
++******************************* gcoSTREAM Object ******************************
++\******************************************************************************/
++
++typedef enum _gceVERTEX_FORMAT
++{
++ gcvVERTEX_BYTE,
++ gcvVERTEX_UNSIGNED_BYTE,
++ gcvVERTEX_SHORT,
++ gcvVERTEX_UNSIGNED_SHORT,
++ gcvVERTEX_INT,
++ gcvVERTEX_UNSIGNED_INT,
++ gcvVERTEX_FIXED,
++ gcvVERTEX_HALF,
++ gcvVERTEX_FLOAT,
++ gcvVERTEX_UNSIGNED_INT_10_10_10_2,
++ gcvVERTEX_INT_10_10_10_2,
++}
++gceVERTEX_FORMAT;
++
++gceSTATUS
++gcoSTREAM_Construct(
++ IN gcoHAL Hal,
++ OUT gcoSTREAM * Stream
++ );
++
++gceSTATUS
++gcoSTREAM_Destroy(
++ IN gcoSTREAM Stream
++ );
++
++gceSTATUS
++gcoSTREAM_Upload(
++ IN gcoSTREAM Stream,
++ IN gctCONST_POINTER Buffer,
++ IN gctUINT32 Offset,
++ IN gctSIZE_T Bytes,
++ IN gctBOOL Dynamic
++ );
++
++gceSTATUS
++gcoSTREAM_SetStride(
++ IN gcoSTREAM Stream,
++ IN gctUINT32 Stride
++ );
++
++gceSTATUS
++gcoSTREAM_Lock(
++ IN gcoSTREAM Stream,
++ OUT gctPOINTER * Logical,
++ OUT gctUINT32 * Physical
++ );
++
++gceSTATUS
++gcoSTREAM_Unlock(
++ IN gcoSTREAM Stream
++ );
++
++gceSTATUS
++gcoSTREAM_Reserve(
++ IN gcoSTREAM Stream,
++ IN gctSIZE_T Bytes
++ );
++
++gceSTATUS
++gcoSTREAM_Flush(
++ IN gcoSTREAM Stream
++ );
++
++/* Dynamic buffer API. */
++gceSTATUS
++gcoSTREAM_SetDynamic(
++ IN gcoSTREAM Stream,
++ IN gctSIZE_T Bytes,
++ IN gctUINT Buffers
++ );
++
++typedef struct _gcsSTREAM_INFO
++{
++ gctUINT index;
++ gceVERTEX_FORMAT format;
++ gctBOOL normalized;
++ gctUINT components;
++ gctSIZE_T size;
++ gctCONST_POINTER data;
++ gctUINT stride;
++}
++gcsSTREAM_INFO, * gcsSTREAM_INFO_PTR;
++
++gceSTATUS
++gcoSTREAM_UploadDynamic(
++ IN gcoSTREAM Stream,
++ IN gctUINT VertexCount,
++ IN gctUINT InfoCount,
++ IN gcsSTREAM_INFO_PTR Info,
++ IN gcoVERTEX Vertex
++ );
++
++gceSTATUS
++gcoSTREAM_CPUCacheOperation(
++ IN gcoSTREAM Stream,
++ IN gceCACHEOPERATION Operation
++ );
++
++/******************************************************************************\
++******************************** gcoVERTEX Object ******************************
++\******************************************************************************/
++
++typedef struct _gcsVERTEX_ATTRIBUTES
++{
++ gceVERTEX_FORMAT format;
++ gctBOOL normalized;
++ gctUINT32 components;
++ gctSIZE_T size;
++ gctUINT32 stream;
++ gctUINT32 offset;
++ gctUINT32 stride;
++}
++gcsVERTEX_ATTRIBUTES;
++
++gceSTATUS
++gcoVERTEX_Construct(
++ IN gcoHAL Hal,
++ OUT gcoVERTEX * Vertex
++ );
++
++gceSTATUS
++gcoVERTEX_Destroy(
++ IN gcoVERTEX Vertex
++ );
++
++gceSTATUS
++gcoVERTEX_Reset(
++ IN gcoVERTEX Vertex
++ );
++
++gceSTATUS
++gcoVERTEX_EnableAttribute(
++ IN gcoVERTEX Vertex,
++ IN gctUINT32 Index,
++ IN gceVERTEX_FORMAT Format,
++ IN gctBOOL Normalized,
++ IN gctUINT32 Components,
++ IN gcoSTREAM Stream,
++ IN gctUINT32 Offset,
++ IN gctUINT32 Stride
++ );
++
++gceSTATUS
++gcoVERTEX_DisableAttribute(
++ IN gcoVERTEX Vertex,
++ IN gctUINT32 Index
++ );
++
++gceSTATUS
++gcoVERTEX_Bind(
++ IN gcoVERTEX Vertex
++ );
++
++/*******************************************************************************
++***** gcoVERTEXARRAY Object ***************************************************/
++
++typedef struct _gcsVERTEXARRAY
++{
++ /* Enabled. */
++ gctBOOL enable;
++
++ /* Number of components. */
++ gctINT size;
++
++ /* Attribute format. */
++ gceVERTEX_FORMAT format;
++
++ /* Flag whether the attribute is normalized or not. */
++ gctBOOL normalized;
++
++ /* Stride of the component. */
++ gctUINT stride;
++
++ /* Pointer to the attribute data. */
++ gctCONST_POINTER pointer;
++
++ /* Stream object owning the attribute data. */
++ gcoSTREAM stream;
++
++ /* Generic values for attribute. */
++ gctFLOAT genericValue[4];
++
++ /* Generic size for attribute. */
++ gctINT genericSize;
++
++ /* Vertex shader linkage. */
++ gctUINT linkage;
++
++#if gcdUSE_WCLIP_PATCH
++ gctBOOL isPosition;
++#endif
++}
++gcsVERTEXARRAY,
++* gcsVERTEXARRAY_PTR;
++
++gceSTATUS
++gcoVERTEXARRAY_Construct(
++ IN gcoHAL Hal,
++ OUT gcoVERTEXARRAY * Vertex
++ );
++
++gceSTATUS
++gcoVERTEXARRAY_Destroy(
++ IN gcoVERTEXARRAY Vertex
++ );
++
++gceSTATUS
++gcoVERTEXARRAY_Bind(
++ IN gcoVERTEXARRAY Vertex,
++ IN gctUINT32 EnableBits,
++ IN gcsVERTEXARRAY_PTR VertexArray,
++ IN gctUINT First,
++ IN gctSIZE_T Count,
++ IN gceINDEX_TYPE IndexType,
++ IN gcoINDEX IndexObject,
++ IN gctPOINTER IndexMemory,
++ IN OUT gcePRIMITIVE * PrimitiveType,
++#if gcdUSE_WCLIP_PATCH
++ IN OUT gctUINT * PrimitiveCount,
++ IN OUT gctFLOAT * wLimitRms,
++ IN OUT gctBOOL * wLimitDirty
++#else
++ IN OUT gctUINT * PrimitiveCount
++#endif
++ );
++
++gctUINT
++gcoVERTEXARRAY_GetMaxStream(
++ IN gcoVERTEXARRAY Vertex
++);
++
++gceSTATUS
++gcoVERTEXARRAY_SetMaxStream(
++ IN gcoVERTEXARRAY Vertex,
++ gctUINT maxStreams
++);
++/*******************************************************************************
++***** Composition *************************************************************/
++
++typedef enum _gceCOMPOSITION
++{
++ gcvCOMPOSE_CLEAR = 1,
++ gcvCOMPOSE_BLUR,
++ gcvCOMPOSE_DIM,
++ gcvCOMPOSE_LAYER
++}
++gceCOMPOSITION;
++
++typedef struct _gcsCOMPOSITION * gcsCOMPOSITION_PTR;
++typedef struct _gcsCOMPOSITION
++{
++ /* Structure size. */
++ gctUINT structSize;
++
++ /* Composition operation. */
++ gceCOMPOSITION operation;
++
++ /* Layer to be composed. */
++ gcoSURF layer;
++
++ /* Source and target coordinates. */
++ gcsRECT srcRect;
++ gcsRECT trgRect;
++
++ /* Target rectangle */
++ gcsPOINT v0;
++ gcsPOINT v1;
++ gcsPOINT v2;
++
++ /* Blending parameters. */
++ gctBOOL enableBlending;
++ gctBOOL premultiplied;
++ gctUINT8 alphaValue;
++
++ /* Clear color. */
++ gctFLOAT r;
++ gctFLOAT g;
++ gctFLOAT b;
++ gctFLOAT a;
++}
++gcsCOMPOSITION;
++
++gceSTATUS
++gco3D_ProbeComposition(
++ gctBOOL ResetIfEmpty
++ );
++
++gceSTATUS
++gco3D_CompositionBegin(
++ void
++ );
++
++gceSTATUS
++gco3D_ComposeLayer(
++ IN gcsCOMPOSITION_PTR Layer
++ );
++
++gceSTATUS
++gco3D_CompositionSignals(
++ IN gctHANDLE Process,
++ IN gctSIGNAL Signal1,
++ IN gctSIGNAL Signal2
++ );
++
++gceSTATUS
++gco3D_CompositionEnd(
++ IN gcoSURF Target,
++ IN gctBOOL Synchronous
++ );
++
++/* Frame Database */
++gceSTATUS
++gcoHAL_AddFrameDB(
++ void
++ );
++
++gceSTATUS
++gcoHAL_DumpFrameDB(
++ gctCONST_STRING Filename OPTIONAL
++ );
++
++gceSTATUS
++gcoHAL_GetSharedInfo(
++ IN gctUINT32 Pid,
++ IN gctUINT32 DataId,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER Data
++ );
++
++gceSTATUS
++gcoHAL_SetSharedInfo(
++ IN gctUINT32 DataId,
++ IN gctPOINTER Data,
++ IN gctSIZE_T Bytes
++ );
++
++#if VIVANTE_PROFILER_CONTEXT
++gceSTATUS
++gcoHARDWARE_GetContext(
++ IN gcoHARDWARE Hardware,
++ OUT gctUINT32 * Context
++ );
++#endif
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* VIVANTE_NO_3D */
++#endif /* __gc_hal_engine_h_ */
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_engine_vg.h linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_engine_vg.h
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_engine_vg.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_engine_vg.h 2015-07-27 23:13:06.214808565 +0200
+@@ -0,0 +1,904 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_engine_vg_h_
++#define __gc_hal_engine_vg_h_
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++#include "gc_hal_types.h"
++
++/******************************************************************************\
++******************************** VG Enumerations *******************************
++\******************************************************************************/
++
++/**
++** @ingroup gcoVG
++**
++** @brief Tiling mode for painting and imagig.
++**
++** This enumeration defines the tiling modes supported by the HAL. This is
++** in fact a one-to-one mapping of the OpenVG 1.1 tile modes.
++*/
++typedef enum _gceTILE_MODE
++{
++ gcvTILE_FILL,
++ gcvTILE_PAD,
++ gcvTILE_REPEAT,
++ gcvTILE_REFLECT
++}
++gceTILE_MODE;
++
++/******************************************************************************/
++/** @ingroup gcoVG
++**
++** @brief The different paint modes.
++**
++** This enumeration lists the available paint modes.
++*/
++typedef enum _gcePAINT_TYPE
++{
++ /** Solid color. */
++ gcvPAINT_MODE_SOLID,
++
++ /** Linear gradient. */
++ gcvPAINT_MODE_LINEAR,
++
++ /** Radial gradient. */
++ gcvPAINT_MODE_RADIAL,
++
++ /** Pattern. */
++ gcvPAINT_MODE_PATTERN,
++
++ /** Mode count. */
++ gcvPAINT_MODE_COUNT
++}
++gcePAINT_TYPE;
++
++/**
++** @ingroup gcoVG
++**
++** @brief Types of path data supported by HAL.
++**
++** This enumeration defines the types of path data supported by the HAL.
++** This is in fact a one-to-one mapping of the OpenVG 1.1 path types.
++*/
++typedef enum _gcePATHTYPE
++{
++ gcePATHTYPE_UNKNOWN = -1,
++ gcePATHTYPE_INT8,
++ gcePATHTYPE_INT16,
++ gcePATHTYPE_INT32,
++ gcePATHTYPE_FLOAT
++}
++gcePATHTYPE;
++
++/**
++** @ingroup gcoVG
++**
++** @brief Supported path segment commands.
++**
++** This enumeration defines the path segment commands supported by the HAL.
++*/
++typedef enum _gceVGCMD
++{
++ gcvVGCMD_END, /* 0: GCCMD_TS_OPCODE_END */
++ gcvVGCMD_CLOSE, /* 1: GCCMD_TS_OPCODE_CLOSE */
++ gcvVGCMD_MOVE, /* 2: GCCMD_TS_OPCODE_MOVE */
++ gcvVGCMD_MOVE_REL, /* 3: GCCMD_TS_OPCODE_MOVE_REL */
++ gcvVGCMD_LINE, /* 4: GCCMD_TS_OPCODE_LINE */
++ gcvVGCMD_LINE_REL, /* 5: GCCMD_TS_OPCODE_LINE_REL */
++ gcvVGCMD_QUAD, /* 6: GCCMD_TS_OPCODE_QUADRATIC */
++ gcvVGCMD_QUAD_REL, /* 7: GCCMD_TS_OPCODE_QUADRATIC_REL */
++ gcvVGCMD_CUBIC, /* 8: GCCMD_TS_OPCODE_CUBIC */
++ gcvVGCMD_CUBIC_REL, /* 9: GCCMD_TS_OPCODE_CUBIC_REL */
++ gcvVGCMD_BREAK, /* 10: GCCMD_TS_OPCODE_BREAK */
++ gcvVGCMD_HLINE, /* 11: ******* R E S E R V E D *******/
++ gcvVGCMD_HLINE_REL, /* 12: ******* R E S E R V E D *******/
++ gcvVGCMD_VLINE, /* 13: ******* R E S E R V E D *******/
++ gcvVGCMD_VLINE_REL, /* 14: ******* R E S E R V E D *******/
++ gcvVGCMD_SQUAD, /* 15: ******* R E S E R V E D *******/
++ gcvVGCMD_SQUAD_REL, /* 16: ******* R E S E R V E D *******/
++ gcvVGCMD_SCUBIC, /* 17: ******* R E S E R V E D *******/
++ gcvVGCMD_SCUBIC_REL, /* 18: ******* R E S E R V E D *******/
++ gcvVGCMD_SCCWARC, /* 19: ******* R E S E R V E D *******/
++ gcvVGCMD_SCCWARC_REL, /* 20: ******* R E S E R V E D *******/
++ gcvVGCMD_SCWARC, /* 21: ******* R E S E R V E D *******/
++ gcvVGCMD_SCWARC_REL, /* 22: ******* R E S E R V E D *******/
++ gcvVGCMD_LCCWARC, /* 23: ******* R E S E R V E D *******/
++ gcvVGCMD_LCCWARC_REL, /* 24: ******* R E S E R V E D *******/
++ gcvVGCMD_LCWARC, /* 25: ******* R E S E R V E D *******/
++ gcvVGCMD_LCWARC_REL, /* 26: ******* R E S E R V E D *******/
++
++ /* The width of the command recognized by the hardware on bits. */
++ gcvVGCMD_WIDTH = 5,
++
++ /* Hardware command mask. */
++ gcvVGCMD_MASK = (1 << gcvVGCMD_WIDTH) - 1,
++
++ /* Command modifiers. */
++ gcvVGCMD_H_MOD = 1 << gcvVGCMD_WIDTH, /* = 32 */
++ gcvVGCMD_V_MOD = 2 << gcvVGCMD_WIDTH, /* = 64 */
++ gcvVGCMD_S_MOD = 3 << gcvVGCMD_WIDTH, /* = 96 */
++ gcvVGCMD_ARC_MOD = 4 << gcvVGCMD_WIDTH, /* = 128 */
++
++ /* Emulated LINE commands. */
++ gcvVGCMD_HLINE_EMUL = gcvVGCMD_H_MOD | gcvVGCMD_LINE, /* = 36 */
++ gcvVGCMD_HLINE_EMUL_REL = gcvVGCMD_H_MOD | gcvVGCMD_LINE_REL, /* = 37 */
++ gcvVGCMD_VLINE_EMUL = gcvVGCMD_V_MOD | gcvVGCMD_LINE, /* = 68 */
++ gcvVGCMD_VLINE_EMUL_REL = gcvVGCMD_V_MOD | gcvVGCMD_LINE_REL, /* = 69 */
++
++ /* Emulated SMOOTH commands. */
++ gcvVGCMD_SQUAD_EMUL = gcvVGCMD_S_MOD | gcvVGCMD_QUAD, /* = 102 */
++ gcvVGCMD_SQUAD_EMUL_REL = gcvVGCMD_S_MOD | gcvVGCMD_QUAD_REL, /* = 103 */
++ gcvVGCMD_SCUBIC_EMUL = gcvVGCMD_S_MOD | gcvVGCMD_CUBIC, /* = 104 */
++ gcvVGCMD_SCUBIC_EMUL_REL = gcvVGCMD_S_MOD | gcvVGCMD_CUBIC_REL, /* = 105 */
++
++ /* Emulation ARC commands. */
++ gcvVGCMD_ARC_LINE = gcvVGCMD_ARC_MOD | gcvVGCMD_LINE, /* = 132 */
++ gcvVGCMD_ARC_LINE_REL = gcvVGCMD_ARC_MOD | gcvVGCMD_LINE_REL, /* = 133 */
++ gcvVGCMD_ARC_QUAD = gcvVGCMD_ARC_MOD | gcvVGCMD_QUAD, /* = 134 */
++ gcvVGCMD_ARC_QUAD_REL = gcvVGCMD_ARC_MOD | gcvVGCMD_QUAD_REL /* = 135 */
++}
++gceVGCMD;
++typedef enum _gceVGCMD * gceVGCMD_PTR;
++
++/**
++** @ingroup gcoVG
++**
++** @brief Blending modes supported by the HAL.
++**
++** This enumeration defines the blending modes supported by the HAL. This is
++** in fact a one-to-one mapping of the OpenVG 1.1 blending modes.
++*/
++typedef enum _gceVG_BLEND
++{
++ gcvVG_BLEND_SRC,
++ gcvVG_BLEND_SRC_OVER,
++ gcvVG_BLEND_DST_OVER,
++ gcvVG_BLEND_SRC_IN,
++ gcvVG_BLEND_DST_IN,
++ gcvVG_BLEND_MULTIPLY,
++ gcvVG_BLEND_SCREEN,
++ gcvVG_BLEND_DARKEN,
++ gcvVG_BLEND_LIGHTEN,
++ gcvVG_BLEND_ADDITIVE,
++ gcvVG_BLEND_SUBTRACT,
++ gcvVG_BLEND_FILTER
++}
++gceVG_BLEND;
++
++/**
++** @ingroup gcoVG
++**
++** @brief Image modes supported by the HAL.
++**
++** This enumeration defines the image modes supported by the HAL. This is
++** in fact a one-to-one mapping of the OpenVG 1.1 image modes with the addition
++** of NO IMAGE.
++*/
++typedef enum _gceVG_IMAGE
++{
++ gcvVG_IMAGE_NONE,
++ gcvVG_IMAGE_NORMAL,
++ gcvVG_IMAGE_MULTIPLY,
++ gcvVG_IMAGE_STENCIL,
++ gcvVG_IMAGE_FILTER
++}
++gceVG_IMAGE;
++
++/**
++** @ingroup gcoVG
++**
++** @brief Filter mode patterns and imaging.
++**
++** This enumeration defines the filter modes supported by the HAL.
++*/
++typedef enum _gceIMAGE_FILTER
++{
++ gcvFILTER_POINT,
++ gcvFILTER_LINEAR,
++ gcvFILTER_BI_LINEAR
++}
++gceIMAGE_FILTER;
++
++/**
++** @ingroup gcoVG
++**
++** @brief Primitive modes supported by the HAL.
++**
++** This enumeration defines the primitive modes supported by the HAL.
++*/
++typedef enum _gceVG_PRIMITIVE
++{
++ gcvVG_SCANLINE,
++ gcvVG_RECTANGLE,
++ gcvVG_TESSELLATED,
++ gcvVG_TESSELLATED_TILED
++}
++gceVG_PRIMITIVE;
++
++/**
++** @ingroup gcoVG
++**
++** @brief Rendering quality modes supported by the HAL.
++**
++** This enumeration defines the rendering quality modes supported by the HAL.
++*/
++typedef enum _gceRENDER_QUALITY
++{
++ gcvVG_NONANTIALIASED,
++ gcvVG_2X2_MSAA,
++ gcvVG_2X4_MSAA,
++ gcvVG_4X4_MSAA
++}
++gceRENDER_QUALITY;
++
++/**
++** @ingroup gcoVG
++**
++** @brief Fill rules supported by the HAL.
++**
++** This enumeration defines the fill rules supported by the HAL.
++*/
++typedef enum _gceFILL_RULE
++{
++ gcvVG_EVEN_ODD,
++ gcvVG_NON_ZERO
++}
++gceFILL_RULE;
++
++/**
++** @ingroup gcoVG
++**
++** @brief Cap styles supported by the HAL.
++**
++** This enumeration defines the cap styles supported by the HAL.
++*/
++typedef enum _gceCAP_STYLE
++{
++ gcvCAP_BUTT,
++ gcvCAP_ROUND,
++ gcvCAP_SQUARE
++}
++gceCAP_STYLE;
++
++/**
++** @ingroup gcoVG
++**
++** @brief Join styles supported by the HAL.
++**
++** This enumeration defines the join styles supported by the HAL.
++*/
++typedef enum _gceJOIN_STYLE
++{
++ gcvJOIN_MITER,
++ gcvJOIN_ROUND,
++ gcvJOIN_BEVEL
++}
++gceJOIN_STYLE;
++
++/**
++** @ingroup gcoVG
++**
++** @brief Channel mask values.
++**
++** This enumeration defines the values for channel mask used in image
++** filtering.
++*/
++
++/* Base values for channel mask definitions. */
++#define gcvCHANNEL_X (0)
++#define gcvCHANNEL_R (1 << 0)
++#define gcvCHANNEL_G (1 << 1)
++#define gcvCHANNEL_B (1 << 2)
++#define gcvCHANNEL_A (1 << 3)
++
++typedef enum _gceCHANNEL
++{
++ gcvCHANNEL_XXXX = (gcvCHANNEL_X | gcvCHANNEL_X | gcvCHANNEL_X | gcvCHANNEL_X),
++ gcvCHANNEL_XXXA = (gcvCHANNEL_X | gcvCHANNEL_X | gcvCHANNEL_X | gcvCHANNEL_A),
++ gcvCHANNEL_XXBX = (gcvCHANNEL_X | gcvCHANNEL_X | gcvCHANNEL_B | gcvCHANNEL_X),
++ gcvCHANNEL_XXBA = (gcvCHANNEL_X | gcvCHANNEL_X | gcvCHANNEL_B | gcvCHANNEL_A),
++
++ gcvCHANNEL_XGXX = (gcvCHANNEL_X | gcvCHANNEL_G | gcvCHANNEL_X | gcvCHANNEL_X),
++ gcvCHANNEL_XGXA = (gcvCHANNEL_X | gcvCHANNEL_G | gcvCHANNEL_X | gcvCHANNEL_A),
++ gcvCHANNEL_XGBX = (gcvCHANNEL_X | gcvCHANNEL_G | gcvCHANNEL_B | gcvCHANNEL_X),
++ gcvCHANNEL_XGBA = (gcvCHANNEL_X | gcvCHANNEL_G | gcvCHANNEL_B | gcvCHANNEL_A),
++
++ gcvCHANNEL_RXXX = (gcvCHANNEL_R | gcvCHANNEL_X | gcvCHANNEL_X | gcvCHANNEL_X),
++ gcvCHANNEL_RXXA = (gcvCHANNEL_R | gcvCHANNEL_X | gcvCHANNEL_X | gcvCHANNEL_A),
++ gcvCHANNEL_RXBX = (gcvCHANNEL_R | gcvCHANNEL_X | gcvCHANNEL_B | gcvCHANNEL_X),
++ gcvCHANNEL_RXBA = (gcvCHANNEL_R | gcvCHANNEL_X | gcvCHANNEL_B | gcvCHANNEL_A),
++
++ gcvCHANNEL_RGXX = (gcvCHANNEL_R | gcvCHANNEL_G | gcvCHANNEL_X | gcvCHANNEL_X),
++ gcvCHANNEL_RGXA = (gcvCHANNEL_R | gcvCHANNEL_G | gcvCHANNEL_X | gcvCHANNEL_A),
++ gcvCHANNEL_RGBX = (gcvCHANNEL_R | gcvCHANNEL_G | gcvCHANNEL_B | gcvCHANNEL_X),
++ gcvCHANNEL_RGBA = (gcvCHANNEL_R | gcvCHANNEL_G | gcvCHANNEL_B | gcvCHANNEL_A),
++}
++gceCHANNEL;
++
++/******************************************************************************\
++******************************** VG Structures *******************************
++\******************************************************************************/
++
++/**
++** @ingroup gcoVG
++**
++** @brief Definition of the color ramp used by the gradient paints.
++**
++** The gcsCOLOR_RAMP structure defines the layout of one single color inside
++** a color ramp which is used by gradient paints.
++*/
++typedef struct _gcsCOLOR_RAMP
++{
++ /** Value for the color stop. */
++ gctFLOAT stop;
++
++ /** Red color channel value for the color stop. */
++ gctFLOAT red;
++
++ /** Green color channel value for the color stop. */
++ gctFLOAT green;
++
++ /** Blue color channel value for the color stop. */
++ gctFLOAT blue;
++
++ /** Alpha color channel value for the color stop. */
++ gctFLOAT alpha;
++}
++gcsCOLOR_RAMP, * gcsCOLOR_RAMP_PTR;
++
++/**
++** @ingroup gcoVG
++**
++** @brief Definition of the color ramp used by the gradient paints in fixed form.
++**
++** The gcsCOLOR_RAMP structure defines the layout of one single color inside
++** a color ramp which is used by gradient paints.
++*/
++typedef struct _gcsFIXED_COLOR_RAMP
++{
++ /** Value for the color stop. */
++ gctFIXED_POINT stop;
++
++ /** Red color channel value for the color stop. */
++ gctFIXED_POINT red;
++
++ /** Green color channel value for the color stop. */
++ gctFIXED_POINT green;
++
++ /** Blue color channel value for the color stop. */
++ gctFIXED_POINT blue;
++
++ /** Alpha color channel value for the color stop. */
++ gctFIXED_POINT alpha;
++}
++gcsFIXED_COLOR_RAMP, * gcsFIXED_COLOR_RAMP_PTR;
++
++
++/**
++** @ingroup gcoVG
++**
++** @brief Rectangle structure used by the gcoVG object.
++**
++** This structure defines the layout of a rectangle. Make sure width and
++** height are larger than 0.
++*/
++typedef struct _gcsVG_RECT * gcsVG_RECT_PTR;
++typedef struct _gcsVG_RECT
++{
++ /** Left location of the rectangle. */
++ gctINT x;
++
++ /** Top location of the rectangle. */
++ gctINT y;
++
++ /** Width of the rectangle. */
++ gctINT width;
++
++ /** Height of the rectangle. */
++ gctINT height;
++}
++gcsVG_RECT;
++
++/**
++** @ingroup gcoVG
++**
++** @brief Path command buffer attribute structure.
++**
++** The gcsPATH_BUFFER_INFO structure contains the specifics about
++** the layout of the path data command buffer.
++*/
++typedef struct _gcsPATH_BUFFER_INFO * gcsPATH_BUFFER_INFO_PTR;
++typedef struct _gcsPATH_BUFFER_INFO
++{
++ gctUINT reservedForHead;
++ gctUINT reservedForTail;
++}
++gcsPATH_BUFFER_INFO;
++
++/**
++** @ingroup gcoVG
++**
++** @brief Definition of the path data container structure.
++**
++** The gcsPATH structure defines the layout of the path data container.
++*/
++typedef struct _gcsPATH_DATA * gcsPATH_DATA_PTR;
++typedef struct _gcsPATH_DATA
++{
++ /* Data container in command buffer format. */
++ gcsCMDBUFFER data;
++
++ /* Path data type. */
++ gcePATHTYPE dataType;
++}
++gcsPATH_DATA;
++
++
++/******************************************************************************\
++********************************* gcoHAL Object ********************************
++\******************************************************************************/
++
++/* Query path data storage attributes. */
++gceSTATUS
++gcoHAL_QueryPathStorage(
++ IN gcoHAL Hal,
++ OUT gcsPATH_BUFFER_INFO_PTR Information
++ );
++
++/* Associate a completion signal with the command buffer. */
++gceSTATUS
++gcoHAL_AssociateCompletion(
++ IN gcoHAL Hal,
++ IN gcsPATH_DATA_PTR PathData
++ );
++
++/* Release the current command buffer completion signal. */
++gceSTATUS
++gcoHAL_DeassociateCompletion(
++ IN gcoHAL Hal,
++ IN gcsPATH_DATA_PTR PathData
++ );
++
++/* Verify whether the command buffer is still in use. */
++gceSTATUS
++gcoHAL_CheckCompletion(
++ IN gcoHAL Hal,
++ IN gcsPATH_DATA_PTR PathData
++ );
++
++/* Wait until the command buffer is no longer in use. */
++gceSTATUS
++gcoHAL_WaitCompletion(
++ IN gcoHAL Hal,
++ IN gcsPATH_DATA_PTR PathData
++ );
++
++/* Flush the pixel cache. */
++gceSTATUS
++gcoHAL_Flush(
++ IN gcoHAL Hal
++ );
++
++/* Split a harwdare address into pool and offset. */
++gceSTATUS
++gcoHAL_SplitAddress(
++ IN gcoHAL Hal,
++ IN gctUINT32 Address,
++ OUT gcePOOL * Pool,
++ OUT gctUINT32 * Offset
++ );
++
++/* Combine pool and offset into a harwdare address. */
++gceSTATUS
++gcoHAL_CombineAddress(
++ IN gcoHAL Hal,
++ IN gcePOOL Pool,
++ IN gctUINT32 Offset,
++ OUT gctUINT32 * Address
++ );
++
++/* Schedule to free linear video memory allocated. */
++gceSTATUS
++gcoHAL_ScheduleVideoMemory(
++ IN gcoHAL Hal,
++ IN gctUINT64 Node
++ );
++
++/* Free linear video memory allocated with gcoHAL_AllocateLinearVideoMemory. */
++gceSTATUS
++gcoHAL_FreeVideoMemory(
++ IN gcoHAL Hal,
++ IN gctUINT64 Node
++ );
++
++/* Query command buffer attributes. */
++gceSTATUS
++gcoHAL_QueryCommandBuffer(
++ IN gcoHAL Hal,
++ OUT gcsCOMMAND_BUFFER_INFO_PTR Information
++ );
++/* Allocate and lock linear video memory. */
++gceSTATUS
++gcoHAL_AllocateLinearVideoMemory(
++ IN gcoHAL Hal,
++ IN gctUINT Size,
++ IN gctUINT Alignment,
++ IN gcePOOL Pool,
++ OUT gctUINT64 * Node,
++ OUT gctUINT32 * Address,
++ OUT gctPOINTER * Memory
++ );
++
++/* Align the specified size accordingly to the hardware requirements. */
++gceSTATUS
++gcoHAL_GetAlignedSurfaceSize(
++ IN gcoHAL Hal,
++ IN gceSURF_TYPE Type,
++ IN OUT gctUINT32_PTR Width,
++ IN OUT gctUINT32_PTR Height
++ );
++
++gceSTATUS
++gcoHAL_ReserveTask(
++ IN gcoHAL Hal,
++ IN gceBLOCK Block,
++ IN gctUINT TaskCount,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Memory
++ );
++/******************************************************************************\
++********************************** gcoVG Object ********************************
++\******************************************************************************/
++
++/** @defgroup gcoVG gcoVG
++**
++** The gcoVG object abstracts the VG hardware pipe.
++*/
++
++gctBOOL
++gcoVG_IsMaskSupported(
++ IN gceSURF_FORMAT Format
++ );
++
++gctBOOL
++gcoVG_IsTargetSupported(
++ IN gceSURF_FORMAT Format
++ );
++
++gctBOOL
++gcoVG_IsImageSupported(
++ IN gceSURF_FORMAT Format
++ );
++
++gctUINT8 gcoVG_PackColorComponent(
++ gctFLOAT Value
++ );
++
++gceSTATUS
++gcoVG_Construct(
++ IN gcoHAL Hal,
++ OUT gcoVG * Vg
++ );
++
++gceSTATUS
++gcoVG_Destroy(
++ IN gcoVG Vg
++ );
++
++gceSTATUS
++gcoVG_SetTarget(
++ IN gcoVG Vg,
++ IN gcoSURF Target
++ );
++
++gceSTATUS
++gcoVG_UnsetTarget(
++ IN gcoVG Vg,
++ IN gcoSURF Surface
++ );
++
++gceSTATUS
++gcoVG_SetUserToSurface(
++ IN gcoVG Vg,
++ IN gctFLOAT UserToSurface[9]
++ );
++
++gceSTATUS
++gcoVG_SetSurfaceToImage(
++ IN gcoVG Vg,
++ IN gctFLOAT SurfaceToImage[9]
++ );
++
++gceSTATUS
++gcoVG_EnableMask(
++ IN gcoVG Vg,
++ IN gctBOOL Enable
++ );
++
++gceSTATUS
++gcoVG_SetMask(
++ IN gcoVG Vg,
++ IN gcoSURF Mask
++ );
++
++gceSTATUS
++gcoVG_UnsetMask(
++ IN gcoVG Vg,
++ IN gcoSURF Surface
++ );
++
++gceSTATUS
++gcoVG_FlushMask(
++ IN gcoVG Vg
++ );
++
++gceSTATUS
++gcoVG_EnableScissor(
++ IN gcoVG Vg,
++ IN gctBOOL Enable
++ );
++
++gceSTATUS
++gcoVG_SetScissor(
++ IN gcoVG Vg,
++ IN gctSIZE_T RectangleCount,
++ IN gcsVG_RECT_PTR Rectangles
++ );
++
++gceSTATUS
++gcoVG_EnableColorTransform(
++ IN gcoVG Vg,
++ IN gctBOOL Enable
++ );
++
++gceSTATUS
++gcoVG_SetColorTransform(
++ IN gcoVG Vg,
++ IN gctFLOAT ColorTransform[8]
++ );
++
++gceSTATUS
++gcoVG_SetTileFillColor(
++ IN gcoVG Vg,
++ IN gctFLOAT Red,
++ IN gctFLOAT Green,
++ IN gctFLOAT Blue,
++ IN gctFLOAT Alpha
++ );
++
++gceSTATUS
++gcoVG_SetSolidPaint(
++ IN gcoVG Vg,
++ IN gctUINT8 Red,
++ IN gctUINT8 Green,
++ IN gctUINT8 Blue,
++ IN gctUINT8 Alpha
++ );
++
++gceSTATUS
++gcoVG_SetLinearPaint(
++ IN gcoVG Vg,
++ IN gctFLOAT Constant,
++ IN gctFLOAT StepX,
++ IN gctFLOAT StepY
++ );
++
++gceSTATUS
++gcoVG_SetRadialPaint(
++ IN gcoVG Vg,
++ IN gctFLOAT LinConstant,
++ IN gctFLOAT LinStepX,
++ IN gctFLOAT LinStepY,
++ IN gctFLOAT RadConstant,
++ IN gctFLOAT RadStepX,
++ IN gctFLOAT RadStepY,
++ IN gctFLOAT RadStepXX,
++ IN gctFLOAT RadStepYY,
++ IN gctFLOAT RadStepXY
++ );
++
++gceSTATUS
++gcoVG_SetPatternPaint(
++ IN gcoVG Vg,
++ IN gctFLOAT UConstant,
++ IN gctFLOAT UStepX,
++ IN gctFLOAT UStepY,
++ IN gctFLOAT VConstant,
++ IN gctFLOAT VStepX,
++ IN gctFLOAT VStepY,
++ IN gctBOOL Linear
++ );
++
++gceSTATUS
++gcoVG_SetColorRamp(
++ IN gcoVG Vg,
++ IN gcoSURF ColorRamp,
++ IN gceTILE_MODE ColorRampSpreadMode
++ );
++
++gceSTATUS
++gcoVG_SetPattern(
++ IN gcoVG Vg,
++ IN gcoSURF Pattern,
++ IN gceTILE_MODE TileMode,
++ IN gceIMAGE_FILTER Filter
++ );
++
++gceSTATUS
++gcoVG_SetImageMode(
++ IN gcoVG Vg,
++ IN gceVG_IMAGE Mode
++ );
++
++gceSTATUS
++gcoVG_SetBlendMode(
++ IN gcoVG Vg,
++ IN gceVG_BLEND Mode
++ );
++
++gceSTATUS
++gcoVG_SetRenderingQuality(
++ IN gcoVG Vg,
++ IN gceRENDER_QUALITY Quality
++ );
++
++gceSTATUS
++gcoVG_SetFillRule(
++ IN gcoVG Vg,
++ IN gceFILL_RULE FillRule
++ );
++
++gceSTATUS
++gcoVG_FinalizePath(
++ IN gcoVG Vg,
++ IN gcsPATH_DATA_PTR PathData
++ );
++
++gceSTATUS
++gcoVG_Clear(
++ IN gcoVG Vg,
++ IN gctINT X,
++ IN gctINT Y,
++ IN gctINT Width,
++ IN gctINT Height
++ );
++
++gceSTATUS
++gcoVG_DrawPath(
++ IN gcoVG Vg,
++ IN gcsPATH_DATA_PTR PathData,
++ IN gctFLOAT Scale,
++ IN gctFLOAT Bias,
++ IN gctBOOL SoftwareTesselation
++ );
++
++gceSTATUS
++gcoVG_DrawImage(
++ IN gcoVG Vg,
++ IN gcoSURF Source,
++ IN gcsPOINT_PTR SourceOrigin,
++ IN gcsPOINT_PTR TargetOrigin,
++ IN gcsSIZE_PTR SourceSize,
++ IN gctINT SourceX,
++ IN gctINT SourceY,
++ IN gctINT TargetX,
++ IN gctINT TargetY,
++ IN gctINT Width,
++ IN gctINT Height,
++ IN gctBOOL Mask
++ );
++
++gceSTATUS
++gcoVG_TesselateImage(
++ IN gcoVG Vg,
++ IN gcoSURF Image,
++ IN gcsVG_RECT_PTR Rectangle,
++ IN gceIMAGE_FILTER Filter,
++ IN gctBOOL Mask,
++ IN gctBOOL SoftwareTesselation
++ );
++
++gceSTATUS
++gcoVG_Blit(
++ IN gcoVG Vg,
++ IN gcoSURF Source,
++ IN gcoSURF Target,
++ IN gcsVG_RECT_PTR SrcRect,
++ IN gcsVG_RECT_PTR TrgRect,
++ IN gceIMAGE_FILTER Filter,
++ IN gceVG_BLEND Mode
++ );
++
++gceSTATUS
++gcoVG_ColorMatrix(
++ IN gcoVG Vg,
++ IN gcoSURF Source,
++ IN gcoSURF Target,
++ IN const gctFLOAT * Matrix,
++ IN gceCHANNEL ColorChannels,
++ IN gctBOOL FilterLinear,
++ IN gctBOOL FilterPremultiplied,
++ IN gcsPOINT_PTR SourceOrigin,
++ IN gcsPOINT_PTR TargetOrigin,
++ IN gctINT Width,
++ IN gctINT Height
++ );
++
++gceSTATUS
++gcoVG_SeparableConvolve(
++ IN gcoVG Vg,
++ IN gcoSURF Source,
++ IN gcoSURF Target,
++ IN gctINT KernelWidth,
++ IN gctINT KernelHeight,
++ IN gctINT ShiftX,
++ IN gctINT ShiftY,
++ IN const gctINT16 * KernelX,
++ IN const gctINT16 * KernelY,
++ IN gctFLOAT Scale,
++ IN gctFLOAT Bias,
++ IN gceTILE_MODE TilingMode,
++ IN gctFLOAT_PTR FillColor,
++ IN gceCHANNEL ColorChannels,
++ IN gctBOOL FilterLinear,
++ IN gctBOOL FilterPremultiplied,
++ IN gcsPOINT_PTR SourceOrigin,
++ IN gcsPOINT_PTR TargetOrigin,
++ IN gcsSIZE_PTR SourceSize,
++ IN gctINT Width,
++ IN gctINT Height
++ );
++
++gceSTATUS
++gcoVG_GaussianBlur(
++ IN gcoVG Vg,
++ IN gcoSURF Source,
++ IN gcoSURF Target,
++ IN gctFLOAT StdDeviationX,
++ IN gctFLOAT StdDeviationY,
++ IN gceTILE_MODE TilingMode,
++ IN gctFLOAT_PTR FillColor,
++ IN gceCHANNEL ColorChannels,
++ IN gctBOOL FilterLinear,
++ IN gctBOOL FilterPremultiplied,
++ IN gcsPOINT_PTR SourceOrigin,
++ IN gcsPOINT_PTR TargetOrigin,
++ IN gcsSIZE_PTR SourceSize,
++ IN gctINT Width,
++ IN gctINT Height
++ );
++
++gceSTATUS
++gcoVG_EnableDither(
++ IN gcoVG Vg,
++ IN gctBOOL Enable
++ );
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __gc_hal_vg_h_ */
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_enum.h linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_enum.h
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_enum.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_enum.h 2015-07-27 23:13:06.214808565 +0200
+@@ -0,0 +1,965 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_enum_h_
++#define __gc_hal_enum_h_
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/* Chip models. */
++typedef enum _gceCHIPMODEL
++{
++ gcv300 = 0x0300,
++ gcv320 = 0x0320,
++ gcv350 = 0x0350,
++ gcv355 = 0x0355,
++ gcv400 = 0x0400,
++ gcv410 = 0x0410,
++ gcv420 = 0x0420,
++ gcv450 = 0x0450,
++ gcv500 = 0x0500,
++ gcv530 = 0x0530,
++ gcv600 = 0x0600,
++ gcv700 = 0x0700,
++ gcv800 = 0x0800,
++ gcv860 = 0x0860,
++ gcv880 = 0x0880,
++ gcv1000 = 0x1000,
++ gcv2000 = 0x2000,
++ gcv2100 = 0x2100,
++ gcv4000 = 0x4000,
++}
++gceCHIPMODEL;
++
++/* Chip features. */
++typedef enum _gceFEATURE
++{
++ gcvFEATURE_PIPE_2D = 0,
++ gcvFEATURE_PIPE_3D,
++ gcvFEATURE_PIPE_VG,
++ gcvFEATURE_DC,
++ gcvFEATURE_HIGH_DYNAMIC_RANGE,
++ gcvFEATURE_MODULE_CG,
++ gcvFEATURE_MIN_AREA,
++ gcvFEATURE_BUFFER_INTERLEAVING,
++ gcvFEATURE_BYTE_WRITE_2D,
++ gcvFEATURE_ENDIANNESS_CONFIG,
++ gcvFEATURE_DUAL_RETURN_BUS,
++ gcvFEATURE_DEBUG_MODE,
++ gcvFEATURE_YUY2_RENDER_TARGET,
++ gcvFEATURE_FRAGMENT_PROCESSOR,
++ gcvFEATURE_2DPE20,
++ gcvFEATURE_FAST_CLEAR,
++ gcvFEATURE_YUV420_TILER,
++ gcvFEATURE_YUY2_AVERAGING,
++ gcvFEATURE_FLIP_Y,
++ gcvFEATURE_EARLY_Z,
++ gcvFEATURE_Z_COMPRESSION,
++ gcvFEATURE_MSAA,
++ gcvFEATURE_SPECIAL_ANTI_ALIASING,
++ gcvFEATURE_SPECIAL_MSAA_LOD,
++ gcvFEATURE_422_TEXTURE_COMPRESSION,
++ gcvFEATURE_DXT_TEXTURE_COMPRESSION,
++ gcvFEATURE_ETC1_TEXTURE_COMPRESSION,
++ gcvFEATURE_CORRECT_TEXTURE_CONVERTER,
++ gcvFEATURE_TEXTURE_8K,
++ gcvFEATURE_SCALER,
++ gcvFEATURE_YUV420_SCALER,
++ gcvFEATURE_SHADER_HAS_W,
++ gcvFEATURE_SHADER_HAS_SIGN,
++ gcvFEATURE_SHADER_HAS_FLOOR,
++ gcvFEATURE_SHADER_HAS_CEIL,
++ gcvFEATURE_SHADER_HAS_SQRT,
++ gcvFEATURE_SHADER_HAS_TRIG,
++ gcvFEATURE_VAA,
++ gcvFEATURE_HZ,
++ gcvFEATURE_CORRECT_STENCIL,
++ gcvFEATURE_VG20,
++ gcvFEATURE_VG_FILTER,
++ gcvFEATURE_VG21,
++ gcvFEATURE_VG_DOUBLE_BUFFER,
++ gcvFEATURE_MC20,
++ gcvFEATURE_SUPER_TILED,
++ gcvFEATURE_2D_FILTERBLIT_PLUS_ALPHABLEND,
++ gcvFEATURE_2D_DITHER,
++ gcvFEATURE_2D_A8_TARGET,
++ gcvFEATURE_2D_FILTERBLIT_FULLROTATION,
++ gcvFEATURE_2D_BITBLIT_FULLROTATION,
++ gcvFEATURE_WIDE_LINE,
++ gcvFEATURE_FC_FLUSH_STALL,
++ gcvFEATURE_FULL_DIRECTFB,
++ gcvFEATURE_HALF_FLOAT_PIPE,
++ gcvFEATURE_LINE_LOOP,
++ gcvFEATURE_2D_YUV_BLIT,
++ gcvFEATURE_2D_TILING,
++ gcvFEATURE_NON_POWER_OF_TWO,
++ gcvFEATURE_3D_TEXTURE,
++ gcvFEATURE_TEXTURE_ARRAY,
++ gcvFEATURE_TILE_FILLER,
++ gcvFEATURE_LOGIC_OP,
++ gcvFEATURE_COMPOSITION,
++ gcvFEATURE_MIXED_STREAMS,
++ gcvFEATURE_2D_MULTI_SOURCE_BLT,
++ gcvFEATURE_END_EVENT,
++ gcvFEATURE_VERTEX_10_10_10_2,
++ gcvFEATURE_TEXTURE_10_10_10_2,
++ gcvFEATURE_TEXTURE_ANISOTROPIC_FILTERING,
++ gcvFEATURE_TEXTURE_FLOAT_HALF_FLOAT,
++ gcvFEATURE_2D_ROTATION_STALL_FIX,
++ gcvFEATURE_2D_MULTI_SOURCE_BLT_EX,
++ gcvFEATURE_BUG_FIXES10,
++ gcvFEATURE_2D_MINOR_TILING,
++ /* Supertiled compressed textures are supported. */
++ gcvFEATURE_TEX_COMPRRESSION_SUPERTILED,
++ gcvFEATURE_FAST_MSAA,
++ gcvFEATURE_BUG_FIXED_INDEXED_TRIANGLE_STRIP,
++ gcvFEATURE_TEXTURE_TILED_READ,
++ gcvFEATURE_DEPTH_BIAS_FIX,
++ gcvFEATURE_RECT_PRIMITIVE,
++ gcvFEATURE_BUG_FIXES11,
++ gcvFEATURE_SUPERTILED_TEXTURE,
++ gcvFEATURE_2D_NO_COLORBRUSH_INDEX8,
++ gcvFEATURE_RS_YUV_TARGET,
++ gcvFEATURE_2D_FC_SOURCE,
++ gcvFEATURE_PE_DITHER_FIX,
++ gcvFEATURE_2D_YUV_SEPARATE_STRIDE,
++ gcvFEATURE_FRUSTUM_CLIP_FIX,
++ gcvFEATURE_TEXTURE_LINEAR,
++ gcvFEATURE_TEXTURE_YUV_ASSEMBLER,
++ gcvFEATURE_SHADER_HAS_INSTRUCTION_CACHE,
++ gcvFEATURE_DYNAMIC_FREQUENCY_SCALING,
++ gcvFEATURE_BUGFIX15,
++ gcvFEATURE_2D_GAMMA,
++ gcvFEATURE_2D_COLOR_SPACE_CONVERSION,
++ gcvFEATURE_2D_SUPER_TILE_VERSION,
++ gcvFEATURE_2D_MIRROR_EXTENSION,
++ gcvFEATURE_2D_SUPER_TILE_V1,
++ gcvFEATURE_2D_SUPER_TILE_V2,
++ gcvFEATURE_2D_SUPER_TILE_V3,
++ gcvFEATURE_2D_MULTI_SOURCE_BLT_EX2,
++ gcvFEATURE_ELEMENT_INDEX_UINT,
++ gcvFEATURE_2D_COMPRESSION,
++ gcvFEATURE_2D_OPF_YUV_OUTPUT,
++ gcvFEATURE_2D_MULTI_SRC_BLT_TO_UNIFIED_DST_RECT,
++ gcvFEATURE_2D_YUV_MODE,
++ gcvFEATURE_DECOMPRESS_Z16,
++ gcvFEATURE_LINEAR_RENDER_TARGET,
++ gcvFEATURE_BUG_FIXES8,
++ gcvFEATURE_HALTI2,
++ gcvFEATURE_MMU,
++}
++gceFEATURE;
++
++/* Chip Power Status. */
++typedef enum _gceCHIPPOWERSTATE
++{
++ gcvPOWER_ON = 0,
++ gcvPOWER_OFF,
++ gcvPOWER_IDLE,
++ gcvPOWER_SUSPEND,
++ gcvPOWER_SUSPEND_ATPOWERON,
++ gcvPOWER_OFF_ATPOWERON,
++ gcvPOWER_IDLE_BROADCAST,
++ gcvPOWER_SUSPEND_BROADCAST,
++ gcvPOWER_OFF_BROADCAST,
++ gcvPOWER_OFF_RECOVERY,
++ gcvPOWER_OFF_TIMEOUT,
++ gcvPOWER_ON_AUTO
++}
++gceCHIPPOWERSTATE;
++
++/* CPU cache operations */
++typedef enum _gceCACHEOPERATION
++{
++ gcvCACHE_CLEAN = 0x01,
++ gcvCACHE_INVALIDATE = 0x02,
++ gcvCACHE_FLUSH = gcvCACHE_CLEAN | gcvCACHE_INVALIDATE,
++ gcvCACHE_MEMORY_BARRIER = 0x04
++}
++gceCACHEOPERATION;
++
++/* Surface types. */
++typedef enum _gceSURF_TYPE
++{
++ gcvSURF_TYPE_UNKNOWN = 0,
++ gcvSURF_INDEX,
++ gcvSURF_VERTEX,
++ gcvSURF_TEXTURE,
++ gcvSURF_RENDER_TARGET,
++ gcvSURF_DEPTH,
++ gcvSURF_BITMAP,
++ gcvSURF_TILE_STATUS,
++ gcvSURF_IMAGE,
++ gcvSURF_MASK,
++ gcvSURF_SCISSOR,
++ gcvSURF_HIERARCHICAL_DEPTH,
++ gcvSURF_NUM_TYPES, /* Make sure this is the last one! */
++
++ /* Combinations. */
++ gcvSURF_NO_TILE_STATUS = 0x100,
++ gcvSURF_NO_VIDMEM = 0x200, /* Used to allocate surfaces with no underlying vidmem node.
++ In Android, vidmem node is allocated by another process. */
++ gcvSURF_CACHEABLE = 0x400, /* Used to allocate a cacheable surface */
++ gcvSURF_FLIP = 0x800, /* The Resolve Target the will been flip resolve from RT */
++ gcvSURF_TILE_STATUS_DIRTY = 0x1000, /* Init tile status to all dirty */
++
++ gcvSURF_LINEAR = 0x2000,
++ gcvSURF_VG = 0x4000,
++
++ gcvSURF_TEXTURE_LINEAR = gcvSURF_TEXTURE
++ | gcvSURF_LINEAR,
++
++ gcvSURF_RENDER_TARGET_NO_TILE_STATUS = gcvSURF_RENDER_TARGET
++ | gcvSURF_NO_TILE_STATUS,
++
++ gcvSURF_RENDER_TARGET_TS_DIRTY = gcvSURF_RENDER_TARGET
++ | gcvSURF_TILE_STATUS_DIRTY,
++
++ gcvSURF_DEPTH_NO_TILE_STATUS = gcvSURF_DEPTH
++ | gcvSURF_NO_TILE_STATUS,
++
++ gcvSURF_DEPTH_TS_DIRTY = gcvSURF_DEPTH
++ | gcvSURF_TILE_STATUS_DIRTY,
++
++ /* Supported surface types with no vidmem node. */
++ gcvSURF_BITMAP_NO_VIDMEM = gcvSURF_BITMAP
++ | gcvSURF_NO_VIDMEM,
++
++ gcvSURF_TEXTURE_NO_VIDMEM = gcvSURF_TEXTURE
++ | gcvSURF_NO_VIDMEM,
++
++ /* Cacheable surface types with no vidmem node. */
++ gcvSURF_CACHEABLE_BITMAP_NO_VIDMEM = gcvSURF_BITMAP_NO_VIDMEM
++ | gcvSURF_CACHEABLE,
++
++ gcvSURF_CACHEABLE_BITMAP = gcvSURF_BITMAP
++ | gcvSURF_CACHEABLE,
++
++ gcvSURF_FLIP_BITMAP = gcvSURF_BITMAP
++ | gcvSURF_FLIP,
++}
++gceSURF_TYPE;
++
++typedef enum _gceSURF_USAGE
++{
++ gcvSURF_USAGE_UNKNOWN,
++ gcvSURF_USAGE_RESOLVE_AFTER_CPU,
++ gcvSURF_USAGE_RESOLVE_AFTER_3D
++}
++gceSURF_USAGE;
++
++typedef enum _gceSURF_COLOR_TYPE
++{
++ gcvSURF_COLOR_UNKNOWN = 0,
++ gcvSURF_COLOR_LINEAR = 0x01,
++ gcvSURF_COLOR_ALPHA_PRE = 0x02,
++}
++gceSURF_COLOR_TYPE;
++
++/* Rotation. */
++typedef enum _gceSURF_ROTATION
++{
++ gcvSURF_0_DEGREE = 0,
++ gcvSURF_90_DEGREE,
++ gcvSURF_180_DEGREE,
++ gcvSURF_270_DEGREE,
++ gcvSURF_FLIP_X,
++ gcvSURF_FLIP_Y,
++
++ gcvSURF_POST_FLIP_X = 0x40000000,
++ gcvSURF_POST_FLIP_Y = 0x80000000,
++}
++gceSURF_ROTATION;
++
++typedef enum _gceMIPMAP_IMAGE_FORMAT
++{
++ gcvUNKNOWN_MIPMAP_IMAGE_FORMAT = -2
++}
++gceMIPMAP_IMAGE_FORMAT;
++
++
++/* Surface formats. */
++typedef enum _gceSURF_FORMAT
++{
++ /* Unknown format. */
++ gcvSURF_UNKNOWN = 0,
++
++ /* Palettized formats. */
++ gcvSURF_INDEX1 = 100,
++ gcvSURF_INDEX4,
++ gcvSURF_INDEX8,
++
++ /* RGB formats. */
++ gcvSURF_A2R2G2B2 = 200,
++ gcvSURF_R3G3B2,
++ gcvSURF_A8R3G3B2,
++ gcvSURF_X4R4G4B4,
++ gcvSURF_A4R4G4B4,
++ gcvSURF_R4G4B4A4,
++ gcvSURF_X1R5G5B5,
++ gcvSURF_A1R5G5B5,
++ gcvSURF_R5G5B5A1,
++ gcvSURF_R5G6B5,
++ gcvSURF_R8G8B8,
++ gcvSURF_X8R8G8B8,
++ gcvSURF_A8R8G8B8,
++ gcvSURF_R8G8B8A8,
++ gcvSURF_G8R8G8B8,
++ gcvSURF_R8G8B8G8,
++ gcvSURF_X2R10G10B10,
++ gcvSURF_A2R10G10B10,
++ gcvSURF_X12R12G12B12,
++ gcvSURF_A12R12G12B12,
++ gcvSURF_X16R16G16B16,
++ gcvSURF_A16R16G16B16,
++ gcvSURF_A32R32G32B32,
++ gcvSURF_R8G8B8X8,
++ gcvSURF_R5G5B5X1,
++ gcvSURF_R4G4B4X4,
++
++ /* BGR formats. */
++ gcvSURF_A4B4G4R4 = 300,
++ gcvSURF_A1B5G5R5,
++ gcvSURF_B5G6R5,
++ gcvSURF_B8G8R8,
++ gcvSURF_B16G16R16,
++ gcvSURF_X8B8G8R8,
++ gcvSURF_A8B8G8R8,
++ gcvSURF_A2B10G10R10,
++ gcvSURF_X16B16G16R16,
++ gcvSURF_A16B16G16R16,
++ gcvSURF_B32G32R32,
++ gcvSURF_X32B32G32R32,
++ gcvSURF_A32B32G32R32,
++ gcvSURF_B4G4R4A4,
++ gcvSURF_B5G5R5A1,
++ gcvSURF_B8G8R8X8,
++ gcvSURF_B8G8R8A8,
++ gcvSURF_X4B4G4R4,
++ gcvSURF_X1B5G5R5,
++ gcvSURF_B4G4R4X4,
++ gcvSURF_B5G5R5X1,
++ gcvSURF_X2B10G10R10,
++
++ /* Compressed formats. */
++ gcvSURF_DXT1 = 400,
++ gcvSURF_DXT2,
++ gcvSURF_DXT3,
++ gcvSURF_DXT4,
++ gcvSURF_DXT5,
++ gcvSURF_CXV8U8,
++ gcvSURF_ETC1,
++ gcvSURF_R11_EAC,
++ gcvSURF_SIGNED_R11_EAC,
++ gcvSURF_RG11_EAC,
++ gcvSURF_SIGNED_RG11_EAC,
++ gcvSURF_RGB8_ETC2,
++ gcvSURF_SRGB8_ETC2,
++ gcvSURF_RGB8_PUNCHTHROUGH_ALPHA1_ETC2,
++ gcvSURF_SRGB8_PUNCHTHROUGH_ALPHA1_ETC2,
++ gcvSURF_RGBA8_ETC2_EAC,
++ gcvSURF_SRGB8_ALPHA8_ETC2_EAC,
++
++ /* YUV formats. */
++ gcvSURF_YUY2 = 500,
++ gcvSURF_UYVY,
++ gcvSURF_YV12,
++ gcvSURF_I420,
++ gcvSURF_NV12,
++ gcvSURF_NV21,
++ gcvSURF_NV16,
++ gcvSURF_NV61,
++ gcvSURF_YVYU,
++ gcvSURF_VYUY,
++
++ /* Depth formats. */
++ gcvSURF_D16 = 600,
++ gcvSURF_D24S8,
++ gcvSURF_D32,
++ gcvSURF_D24X8,
++
++ /* Alpha formats. */
++ gcvSURF_A4 = 700,
++ gcvSURF_A8,
++ gcvSURF_A12,
++ gcvSURF_A16,
++ gcvSURF_A32,
++ gcvSURF_A1,
++
++ /* Luminance formats. */
++ gcvSURF_L4 = 800,
++ gcvSURF_L8,
++ gcvSURF_L12,
++ gcvSURF_L16,
++ gcvSURF_L32,
++ gcvSURF_L1,
++
++ /* Alpha/Luminance formats. */
++ gcvSURF_A4L4 = 900,
++ gcvSURF_A2L6,
++ gcvSURF_A8L8,
++ gcvSURF_A4L12,
++ gcvSURF_A12L12,
++ gcvSURF_A16L16,
++
++ /* Bump formats. */
++ gcvSURF_L6V5U5 = 1000,
++ gcvSURF_V8U8,
++ gcvSURF_X8L8V8U8,
++ gcvSURF_Q8W8V8U8,
++ gcvSURF_A2W10V10U10,
++ gcvSURF_V16U16,
++ gcvSURF_Q16W16V16U16,
++
++ /* R/RG/RA formats. */
++ gcvSURF_R8 = 1100,
++ gcvSURF_X8R8,
++ gcvSURF_G8R8,
++ gcvSURF_X8G8R8,
++ gcvSURF_A8R8,
++ gcvSURF_R16,
++ gcvSURF_X16R16,
++ gcvSURF_G16R16,
++ gcvSURF_X16G16R16,
++ gcvSURF_A16R16,
++ gcvSURF_R32,
++ gcvSURF_X32R32,
++ gcvSURF_G32R32,
++ gcvSURF_X32G32R32,
++ gcvSURF_A32R32,
++ gcvSURF_RG16,
++
++ /* Floating point formats. */
++ gcvSURF_R16F = 1200,
++ gcvSURF_X16R16F,
++ gcvSURF_G16R16F,
++ gcvSURF_X16G16R16F,
++ gcvSURF_B16G16R16F,
++ gcvSURF_X16B16G16R16F,
++ gcvSURF_A16B16G16R16F,
++ gcvSURF_R32F,
++ gcvSURF_X32R32F,
++ gcvSURF_G32R32F,
++ gcvSURF_X32G32R32F,
++ gcvSURF_B32G32R32F,
++ gcvSURF_X32B32G32R32F,
++ gcvSURF_A32B32G32R32F,
++ gcvSURF_A16F,
++ gcvSURF_L16F,
++ gcvSURF_A16L16F,
++ gcvSURF_A16R16F,
++ gcvSURF_A32F,
++ gcvSURF_L32F,
++ gcvSURF_A32L32F,
++ gcvSURF_A32R32F,
++
++}
++gceSURF_FORMAT;
++
++/* Pixel swizzle modes. */
++typedef enum _gceSURF_SWIZZLE
++{
++ gcvSURF_NOSWIZZLE = 0,
++ gcvSURF_ARGB,
++ gcvSURF_ABGR,
++ gcvSURF_RGBA,
++ gcvSURF_BGRA
++}
++gceSURF_SWIZZLE;
++
++/* Transparency modes. */
++typedef enum _gceSURF_TRANSPARENCY
++{
++ /* Valid only for PE 1.0 */
++ gcvSURF_OPAQUE = 0,
++ gcvSURF_SOURCE_MATCH,
++ gcvSURF_SOURCE_MASK,
++ gcvSURF_PATTERN_MASK,
++}
++gceSURF_TRANSPARENCY;
++
++/* Surface Alignment. */
++typedef enum _gceSURF_ALIGNMENT
++{
++ gcvSURF_FOUR = 0,
++ gcvSURF_SIXTEEN,
++ gcvSURF_SUPER_TILED,
++ gcvSURF_SPLIT_TILED,
++ gcvSURF_SPLIT_SUPER_TILED,
++}
++gceSURF_ALIGNMENT;
++
++
++/* Surface Addressing. */
++typedef enum _gceSURF_ADDRESSING
++{
++ gcvSURF_NO_STRIDE_TILED = 0,
++ gcvSURF_NO_STRIDE_LINEAR,
++ gcvSURF_STRIDE_TILED,
++ gcvSURF_STRIDE_LINEAR
++}
++gceSURF_ADDRESSING;
++
++/* Transparency modes. */
++typedef enum _gce2D_TRANSPARENCY
++{
++ /* Valid only for PE 2.0 */
++ gcv2D_OPAQUE = 0,
++ gcv2D_KEYED,
++ gcv2D_MASKED
++}
++gce2D_TRANSPARENCY;
++
++/* Mono packing modes. */
++typedef enum _gceSURF_MONOPACK
++{
++ gcvSURF_PACKED8 = 0,
++ gcvSURF_PACKED16,
++ gcvSURF_PACKED32,
++ gcvSURF_UNPACKED,
++}
++gceSURF_MONOPACK;
++
++/* Blending modes. */
++typedef enum _gceSURF_BLEND_MODE
++{
++ /* Porter-Duff blending modes. */
++ /* Fsrc Fdst */
++ gcvBLEND_CLEAR = 0, /* 0 0 */
++ gcvBLEND_SRC, /* 1 0 */
++ gcvBLEND_DST, /* 0 1 */
++ gcvBLEND_SRC_OVER_DST, /* 1 1 - Asrc */
++ gcvBLEND_DST_OVER_SRC, /* 1 - Adst 1 */
++ gcvBLEND_SRC_IN_DST, /* Adst 0 */
++ gcvBLEND_DST_IN_SRC, /* 0 Asrc */
++ gcvBLEND_SRC_OUT_DST, /* 1 - Adst 0 */
++ gcvBLEND_DST_OUT_SRC, /* 0 1 - Asrc */
++ gcvBLEND_SRC_ATOP_DST, /* Adst 1 - Asrc */
++ gcvBLEND_DST_ATOP_SRC, /* 1 - Adst Asrc */
++ gcvBLEND_SRC_XOR_DST, /* 1 - Adst 1 - Asrc */
++
++ /* Special blending modes. */
++ gcvBLEND_SET, /* DST = 1 */
++ gcvBLEND_SUB /* DST = DST * (1 - SRC) */
++}
++gceSURF_BLEND_MODE;
++
++/* Per-pixel alpha modes. */
++typedef enum _gceSURF_PIXEL_ALPHA_MODE
++{
++ gcvSURF_PIXEL_ALPHA_STRAIGHT = 0,
++ gcvSURF_PIXEL_ALPHA_INVERSED
++}
++gceSURF_PIXEL_ALPHA_MODE;
++
++/* Global alpha modes. */
++typedef enum _gceSURF_GLOBAL_ALPHA_MODE
++{
++ gcvSURF_GLOBAL_ALPHA_OFF = 0,
++ gcvSURF_GLOBAL_ALPHA_ON,
++ gcvSURF_GLOBAL_ALPHA_SCALE
++}
++gceSURF_GLOBAL_ALPHA_MODE;
++
++/* Color component modes for alpha blending. */
++typedef enum _gceSURF_PIXEL_COLOR_MODE
++{
++ gcvSURF_COLOR_STRAIGHT = 0,
++ gcvSURF_COLOR_MULTIPLY
++}
++gceSURF_PIXEL_COLOR_MODE;
++
++/* Color component modes for alpha blending. */
++typedef enum _gce2D_PIXEL_COLOR_MULTIPLY_MODE
++{
++ gcv2D_COLOR_MULTIPLY_DISABLE = 0,
++ gcv2D_COLOR_MULTIPLY_ENABLE
++}
++gce2D_PIXEL_COLOR_MULTIPLY_MODE;
++
++/* Color component modes for alpha blending. */
++typedef enum _gce2D_GLOBAL_COLOR_MULTIPLY_MODE
++{
++ gcv2D_GLOBAL_COLOR_MULTIPLY_DISABLE = 0,
++ gcv2D_GLOBAL_COLOR_MULTIPLY_ALPHA,
++ gcv2D_GLOBAL_COLOR_MULTIPLY_COLOR
++}
++gce2D_GLOBAL_COLOR_MULTIPLY_MODE;
++
++/* Alpha blending factor modes. */
++typedef enum _gceSURF_BLEND_FACTOR_MODE
++{
++ gcvSURF_BLEND_ZERO = 0,
++ gcvSURF_BLEND_ONE,
++ gcvSURF_BLEND_STRAIGHT,
++ gcvSURF_BLEND_INVERSED,
++ gcvSURF_BLEND_COLOR,
++ gcvSURF_BLEND_COLOR_INVERSED,
++ gcvSURF_BLEND_SRC_ALPHA_SATURATED,
++ gcvSURF_BLEND_STRAIGHT_NO_CROSS,
++ gcvSURF_BLEND_INVERSED_NO_CROSS,
++ gcvSURF_BLEND_COLOR_NO_CROSS,
++ gcvSURF_BLEND_COLOR_INVERSED_NO_CROSS,
++ gcvSURF_BLEND_SRC_ALPHA_SATURATED_CROSS
++}
++gceSURF_BLEND_FACTOR_MODE;
++
++/* Alpha blending porter duff rules. */
++typedef enum _gce2D_PORTER_DUFF_RULE
++{
++ gcvPD_CLEAR = 0,
++ gcvPD_SRC,
++ gcvPD_SRC_OVER,
++ gcvPD_DST_OVER,
++ gcvPD_SRC_IN,
++ gcvPD_DST_IN,
++ gcvPD_SRC_OUT,
++ gcvPD_DST_OUT,
++ gcvPD_SRC_ATOP,
++ gcvPD_DST_ATOP,
++ gcvPD_ADD,
++ gcvPD_XOR,
++ gcvPD_DST
++}
++gce2D_PORTER_DUFF_RULE;
++
++/* Alpha blending factor modes. */
++typedef enum _gce2D_YUV_COLOR_MODE
++{
++ gcv2D_YUV_601= 0,
++ gcv2D_YUV_709,
++ gcv2D_YUV_USER_DEFINED,
++ gcv2D_YUV_USER_DEFINED_CLAMP,
++
++ /* Default setting is for src. gcv2D_YUV_DST
++ can be ORed to set dst.
++ */
++ gcv2D_YUV_DST = 0x80000000,
++}
++gce2D_YUV_COLOR_MODE;
++
++typedef enum _gce2D_COMMAND
++{
++ gcv2D_CLEAR = 0,
++ gcv2D_LINE,
++ gcv2D_BLT,
++ gcv2D_STRETCH,
++ gcv2D_HOR_FILTER,
++ gcv2D_VER_FILTER,
++ gcv2D_MULTI_SOURCE_BLT,
++}
++gce2D_COMMAND;
++
++typedef enum _gce2D_TILE_STATUS_CONFIG
++{
++ gcv2D_TSC_DISABLE = 0,
++ gcv2D_TSC_ENABLE = 0x00000001,
++ gcv2D_TSC_COMPRESSED = 0x00000002,
++ gcv2D_TSC_DOWN_SAMPLER = 0x00000004,
++ gcv2D_TSC_2D_COMPRESSED = 0x00000008,
++}
++gce2D_TILE_STATUS_CONFIG;
++
++typedef enum _gce2D_QUERY
++{
++ gcv2D_QUERY_RGB_ADDRESS_MIN_ALIGN = 0,
++ gcv2D_QUERY_RGB_STRIDE_MIN_ALIGN,
++ gcv2D_QUERY_YUV_ADDRESS_MIN_ALIGN,
++ gcv2D_QUERY_YUV_STRIDE_MIN_ALIGN,
++}
++gce2D_QUERY;
++
++typedef enum _gce2D_SUPER_TILE_VERSION
++{
++ gcv2D_SUPER_TILE_VERSION_V1 = 1,
++ gcv2D_SUPER_TILE_VERSION_V2 = 2,
++ gcv2D_SUPER_TILE_VERSION_V3 = 3,
++}
++gce2D_SUPER_TILE_VERSION;
++
++typedef enum _gce2D_STATE
++{
++ gcv2D_STATE_SPECIAL_FILTER_MIRROR_MODE = 1,
++ gcv2D_STATE_SUPER_TILE_VERSION,
++ gcv2D_STATE_EN_GAMMA,
++ gcv2D_STATE_DE_GAMMA,
++ gcv2D_STATE_MULTI_SRC_BLIT_UNIFIED_DST_RECT,
++ gcv2D_STATE_XRGB_ENABLE,
++
++ gcv2D_STATE_ARRAY_EN_GAMMA = 0x10001,
++ gcv2D_STATE_ARRAY_DE_GAMMA,
++ gcv2D_STATE_ARRAY_CSC_YUV_TO_RGB,
++ gcv2D_STATE_ARRAY_CSC_RGB_TO_YUV,
++}
++gce2D_STATE;
++
++#ifndef VIVANTE_NO_3D
++/* Texture functions. */
++typedef enum _gceTEXTURE_FUNCTION
++{
++ gcvTEXTURE_DUMMY = 0,
++ gcvTEXTURE_REPLACE = 0,
++ gcvTEXTURE_MODULATE,
++ gcvTEXTURE_ADD,
++ gcvTEXTURE_ADD_SIGNED,
++ gcvTEXTURE_INTERPOLATE,
++ gcvTEXTURE_SUBTRACT,
++ gcvTEXTURE_DOT3
++}
++gceTEXTURE_FUNCTION;
++
++/* Texture sources. */
++typedef enum _gceTEXTURE_SOURCE
++{
++ gcvCOLOR_FROM_TEXTURE = 0,
++ gcvCOLOR_FROM_CONSTANT_COLOR,
++ gcvCOLOR_FROM_PRIMARY_COLOR,
++ gcvCOLOR_FROM_PREVIOUS_COLOR
++}
++gceTEXTURE_SOURCE;
++
++/* Texture source channels. */
++typedef enum _gceTEXTURE_CHANNEL
++{
++ gcvFROM_COLOR = 0,
++ gcvFROM_ONE_MINUS_COLOR,
++ gcvFROM_ALPHA,
++ gcvFROM_ONE_MINUS_ALPHA
++}
++gceTEXTURE_CHANNEL;
++#endif /* VIVANTE_NO_3D */
++
++/* Filter types. */
++typedef enum _gceFILTER_TYPE
++{
++ gcvFILTER_SYNC = 0,
++ gcvFILTER_BLUR,
++ gcvFILTER_USER
++}
++gceFILTER_TYPE;
++
++/* Filter pass types. */
++typedef enum _gceFILTER_PASS_TYPE
++{
++ gcvFILTER_HOR_PASS = 0,
++ gcvFILTER_VER_PASS
++}
++gceFILTER_PASS_TYPE;
++
++/* Endian hints. */
++typedef enum _gceENDIAN_HINT
++{
++ gcvENDIAN_NO_SWAP = 0,
++ gcvENDIAN_SWAP_WORD,
++ gcvENDIAN_SWAP_DWORD
++}
++gceENDIAN_HINT;
++
++/* Tiling modes. */
++typedef enum _gceTILING
++{
++ gcvLINEAR = 0,
++ gcvTILED,
++ gcvSUPERTILED,
++ gcvMULTI_TILED,
++ gcvMULTI_SUPERTILED,
++ gcvMINORTILED,
++}
++gceTILING;
++
++/* 2D pattern type. */
++typedef enum _gce2D_PATTERN
++{
++ gcv2D_PATTERN_SOLID = 0,
++ gcv2D_PATTERN_MONO,
++ gcv2D_PATTERN_COLOR,
++ gcv2D_PATTERN_INVALID
++}
++gce2D_PATTERN;
++
++/* 2D source type. */
++typedef enum _gce2D_SOURCE
++{
++ gcv2D_SOURCE_MASKED = 0,
++ gcv2D_SOURCE_MONO,
++ gcv2D_SOURCE_COLOR,
++ gcv2D_SOURCE_INVALID
++}
++gce2D_SOURCE;
++
++/* Pipes. */
++typedef enum _gcePIPE_SELECT
++{
++ gcvPIPE_INVALID = ~0,
++ gcvPIPE_3D = 0,
++ gcvPIPE_2D
++}
++gcePIPE_SELECT;
++
++/* Hardware type. */
++typedef enum _gceHARDWARE_TYPE
++{
++ gcvHARDWARE_INVALID = 0x00,
++ gcvHARDWARE_3D = 0x01,
++ gcvHARDWARE_2D = 0x02,
++ gcvHARDWARE_VG = 0x04,
++
++ gcvHARDWARE_3D2D = gcvHARDWARE_3D | gcvHARDWARE_2D
++}
++gceHARDWARE_TYPE;
++
++#define gcdCHIP_COUNT 3
++
++typedef enum _gceMMU_MODE
++{
++ gcvMMU_MODE_1K,
++ gcvMMU_MODE_4K,
++} gceMMU_MODE;
++
++/* User signal command codes. */
++typedef enum _gceUSER_SIGNAL_COMMAND_CODES
++{
++ gcvUSER_SIGNAL_CREATE,
++ gcvUSER_SIGNAL_DESTROY,
++ gcvUSER_SIGNAL_SIGNAL,
++ gcvUSER_SIGNAL_WAIT,
++ gcvUSER_SIGNAL_MAP,
++ gcvUSER_SIGNAL_UNMAP,
++}
++gceUSER_SIGNAL_COMMAND_CODES;
++
++/* Sync point command codes. */
++typedef enum _gceSYNC_POINT_COMMAND_CODES
++{
++ gcvSYNC_POINT_CREATE,
++ gcvSYNC_POINT_DESTROY,
++ gcvSYNC_POINT_SIGNAL,
++}
++gceSYNC_POINT_COMMAND_CODES;
++
++/* Event locations. */
++typedef enum _gceKERNEL_WHERE
++{
++ gcvKERNEL_COMMAND,
++ gcvKERNEL_VERTEX,
++ gcvKERNEL_TRIANGLE,
++ gcvKERNEL_TEXTURE,
++ gcvKERNEL_PIXEL,
++}
++gceKERNEL_WHERE;
++
++#if gcdENABLE_VG
++/* Hardware blocks. */
++typedef enum _gceBLOCK
++{
++ gcvBLOCK_COMMAND,
++ gcvBLOCK_TESSELLATOR,
++ gcvBLOCK_TESSELLATOR2,
++ gcvBLOCK_TESSELLATOR3,
++ gcvBLOCK_RASTER,
++ gcvBLOCK_VG,
++ gcvBLOCK_VG2,
++ gcvBLOCK_VG3,
++ gcvBLOCK_PIXEL,
++
++ /* Number of defined blocks. */
++ gcvBLOCK_COUNT
++}
++gceBLOCK;
++#endif
++
++/* gcdDUMP message type. */
++typedef enum _gceDEBUG_MESSAGE_TYPE
++{
++ gcvMESSAGE_TEXT,
++ gcvMESSAGE_DUMP
++}
++gceDEBUG_MESSAGE_TYPE;
++
++typedef enum _gceSPECIAL_HINT
++{
++ gceSPECIAL_HINT0,
++ gceSPECIAL_HINT1,
++ gceSPECIAL_HINT2,
++ gceSPECIAL_HINT3,
++ /* For disable dynamic stream/index */
++ gceSPECIAL_HINT4
++}
++gceSPECIAL_HINT;
++
++typedef enum _gceMACHINECODE
++{
++ gcvMACHINECODE_HOVERJET0 = 0x0,
++ gcvMACHINECODE_HOVERJET1 ,
++
++ gcvMACHINECODE_TAIJI0 ,
++ gcvMACHINECODE_TAIJI1 ,
++ gcvMACHINECODE_TAIJI2 ,
++
++ gcvMACHINECODE_ANTUTU0 ,
++
++ gcvMACHINECODE_GLB27_RELEASE_0,
++ gcvMACHINECODE_GLB27_RELEASE_1,
++
++ gcvMACHINECODE_WAVESCAPE0 ,
++ gcvMACHINECODE_WAVESCAPE1 ,
++
++ gcvMACHINECODE_NENAMARKV2_4_0 ,
++ gcvMACHINECODE_NENAMARKV2_4_1 ,
++
++ gcvMACHINECODE_GLB25_RELEASE_0,
++ gcvMACHINECODE_GLB25_RELEASE_1,
++ gcvMACHINECODE_GLB25_RELEASE_2,
++}
++gceMACHINECODE;
++
++
++/******************************************************************************\
++****************************** Object Declarations *****************************
++\******************************************************************************/
++
++typedef struct _gckCONTEXT * gckCONTEXT;
++typedef struct _gcoCMDBUF * gcoCMDBUF;
++typedef struct _gcsSTATE_DELTA * gcsSTATE_DELTA_PTR;
++typedef struct _gcsQUEUE * gcsQUEUE_PTR;
++typedef struct _gcoQUEUE * gcoQUEUE;
++typedef struct _gcsHAL_INTERFACE * gcsHAL_INTERFACE_PTR;
++typedef struct _gcs2D_PROFILE * gcs2D_PROFILE_PTR;
++
++#if gcdENABLE_VG
++typedef struct _gcoVGHARDWARE * gcoVGHARDWARE;
++typedef struct _gcoVGBUFFER * gcoVGBUFFER;
++typedef struct _gckVGHARDWARE * gckVGHARDWARE;
++typedef struct _gcsVGCONTEXT * gcsVGCONTEXT_PTR;
++typedef struct _gcsVGCONTEXT_MAP * gcsVGCONTEXT_MAP_PTR;
++typedef struct _gcsVGCMDQUEUE * gcsVGCMDQUEUE_PTR;
++typedef struct _gcsTASK_MASTER_TABLE * gcsTASK_MASTER_TABLE_PTR;
++typedef struct _gckVGKERNEL * gckVGKERNEL;
++typedef void * gctTHREAD;
++#endif
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __gc_hal_enum_h_ */
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal.h linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal.h
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal.h 2015-07-27 23:13:06.194879670 +0200
+@@ -0,0 +1,2671 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_h_
++#define __gc_hal_h_
++
++#include "gc_hal_rename.h"
++#include "gc_hal_types.h"
++#include "gc_hal_enum.h"
++#include "gc_hal_base.h"
++#include "gc_hal_profiler.h"
++#include "gc_hal_driver.h"
++#ifndef VIVANTE_NO_3D
++#include "gc_hal_statistics.h"
++#endif
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/******************************************************************************\
++******************************* Alignment Macros *******************************
++\******************************************************************************/
++
++#define gcmALIGN(n, align) \
++( \
++ ((n) + ((align) - 1)) & ~((align) - 1) \
++)
++
++#define gcmALIGN_BASE(n, align) \
++( \
++ ((n) & ~((align) - 1)) \
++)
++
++/******************************************************************************\
++***************************** Element Count Macro *****************************
++\******************************************************************************/
++
++#define gcmSIZEOF(a) \
++( \
++ (gctSIZE_T) (sizeof(a)) \
++)
++
++#define gcmCOUNTOF(a) \
++( \
++ sizeof(a) / sizeof(a[0]) \
++)
++
++/******************************************************************************\
++********************************* Cast Macro **********************************
++\******************************************************************************/
++#define gcmNAME_TO_PTR(na) \
++ gckKERNEL_QueryPointerFromName(kernel, gcmALL_TO_UINT32(na))
++
++#define gcmPTR_TO_NAME(ptr) \
++ gckKERNEL_AllocateNameFromPointer(kernel, ptr)
++
++#define gcmRELEASE_NAME(na) \
++ gckKERNEL_DeleteName(kernel, gcmALL_TO_UINT32(na))
++
++#ifdef __LP64__
++
++#define gcmALL_TO_UINT32(t) \
++( \
++ (gctUINT32) (gctUINTPTR_T) (t)\
++)
++
++#define gcmPTR_TO_UINT64(p) \
++( \
++ (gctUINT64) (p)\
++)
++
++#define gcmUINT64_TO_PTR(u) \
++( \
++ (gctPOINTER) (u)\
++)
++
++#else /* 32 bit */
++
++#define gcmALL_TO_UINT32(t) \
++( \
++ (gctUINT32) (t)\
++)
++
++#define gcmPTR_TO_UINT64(p) \
++( \
++ (gctUINT64) (gctUINTPTR_T) (p)\
++)
++
++#define gcmUINT64_TO_PTR(u) \
++( \
++ (gctPOINTER) (gctUINTPTR_T) (u)\
++)
++
++#endif
++
++#define gcmUINT64_TO_TYPE(u, t) \
++( \
++ (t) (gctUINTPTR_T) (u)\
++)
++
++/******************************************************************************\
++******************************** Useful Macro *********************************
++\******************************************************************************/
++
++#define gcvINVALID_ADDRESS ~0U
++
++#define gcmGET_PRE_ROTATION(rotate) \
++ ((rotate) & (~(gcvSURF_POST_FLIP_X | gcvSURF_POST_FLIP_Y)))
++
++#define gcmGET_POST_ROTATION(rotate) \
++ ((rotate) & (gcvSURF_POST_FLIP_X | gcvSURF_POST_FLIP_Y))
++
++/******************************************************************************\
++******************************** gcsOBJECT Object *******************************
++\******************************************************************************/
++
++/* Type of objects. */
++typedef enum _gceOBJECT_TYPE
++{
++ gcvOBJ_UNKNOWN = 0,
++ gcvOBJ_2D = gcmCC('2','D',' ',' '),
++ gcvOBJ_3D = gcmCC('3','D',' ',' '),
++ gcvOBJ_ATTRIBUTE = gcmCC('A','T','T','R'),
++ gcvOBJ_BRUSHCACHE = gcmCC('B','R','U','$'),
++ gcvOBJ_BRUSHNODE = gcmCC('B','R','U','n'),
++ gcvOBJ_BRUSH = gcmCC('B','R','U','o'),
++ gcvOBJ_BUFFER = gcmCC('B','U','F','R'),
++ gcvOBJ_COMMAND = gcmCC('C','M','D',' '),
++ gcvOBJ_COMMANDBUFFER = gcmCC('C','M','D','B'),
++ gcvOBJ_CONTEXT = gcmCC('C','T','X','T'),
++ gcvOBJ_DEVICE = gcmCC('D','E','V',' '),
++ gcvOBJ_DUMP = gcmCC('D','U','M','P'),
++ gcvOBJ_EVENT = gcmCC('E','V','N','T'),
++ gcvOBJ_FUNCTION = gcmCC('F','U','N','C'),
++ gcvOBJ_HAL = gcmCC('H','A','L',' '),
++ gcvOBJ_HARDWARE = gcmCC('H','A','R','D'),
++ gcvOBJ_HEAP = gcmCC('H','E','A','P'),
++ gcvOBJ_INDEX = gcmCC('I','N','D','X'),
++ gcvOBJ_INTERRUPT = gcmCC('I','N','T','R'),
++ gcvOBJ_KERNEL = gcmCC('K','E','R','N'),
++ gcvOBJ_KERNEL_FUNCTION = gcmCC('K','F','C','N'),
++ gcvOBJ_MEMORYBUFFER = gcmCC('M','E','M','B'),
++ gcvOBJ_MMU = gcmCC('M','M','U',' '),
++ gcvOBJ_OS = gcmCC('O','S',' ',' '),
++ gcvOBJ_OUTPUT = gcmCC('O','U','T','P'),
++ gcvOBJ_PAINT = gcmCC('P','N','T',' '),
++ gcvOBJ_PATH = gcmCC('P','A','T','H'),
++ gcvOBJ_QUEUE = gcmCC('Q','U','E',' '),
++ gcvOBJ_SAMPLER = gcmCC('S','A','M','P'),
++ gcvOBJ_SHADER = gcmCC('S','H','D','R'),
++ gcvOBJ_STREAM = gcmCC('S','T','R','M'),
++ gcvOBJ_SURF = gcmCC('S','U','R','F'),
++ gcvOBJ_TEXTURE = gcmCC('T','X','T','R'),
++ gcvOBJ_UNIFORM = gcmCC('U','N','I','F'),
++ gcvOBJ_VARIABLE = gcmCC('V','A','R','I'),
++ gcvOBJ_VERTEX = gcmCC('V','R','T','X'),
++ gcvOBJ_VIDMEM = gcmCC('V','M','E','M'),
++ gcvOBJ_VG = gcmCC('V','G',' ',' '),
++}
++gceOBJECT_TYPE;
++
++/* gcsOBJECT object defintinon. */
++typedef struct _gcsOBJECT
++{
++ /* Type of an object. */
++ gceOBJECT_TYPE type;
++}
++gcsOBJECT;
++
++typedef struct _gckHARDWARE * gckHARDWARE;
++
++/* CORE flags. */
++typedef enum _gceCORE
++{
++ gcvCORE_MAJOR = 0x0,
++ gcvCORE_2D = 0x1,
++ gcvCORE_VG = 0x2
++}
++gceCORE;
++
++#define gcdMAX_GPU_COUNT 3
++
++/*******************************************************************************
++**
++** gcmVERIFY_OBJECT
++**
++** Assert if an object is invalid or is not of the specified type. If the
++** object is invalid or not of the specified type, gcvSTATUS_INVALID_OBJECT
++** will be returned from the current function. In retail mode this macro
++** does nothing.
++**
++** ARGUMENTS:
++**
++** obj Object to test.
++** t Expected type of the object.
++*/
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++#define _gcmVERIFY_OBJECT(prefix, obj, t) \
++ if ((obj) == gcvNULL) \
++ { \
++ prefix##TRACE(gcvLEVEL_ERROR, \
++ #prefix "VERIFY_OBJECT failed: NULL"); \
++ prefix##TRACE(gcvLEVEL_ERROR, " expected: %c%c%c%c", \
++ gcmCC_PRINT(t)); \
++ prefix##ASSERT((obj) != gcvNULL); \
++ prefix##FOOTER_ARG("status=%d", gcvSTATUS_INVALID_OBJECT); \
++ return gcvSTATUS_INVALID_OBJECT; \
++ } \
++ else if (((gcsOBJECT*) (obj))->type != t) \
++ { \
++ prefix##TRACE(gcvLEVEL_ERROR, \
++ #prefix "VERIFY_OBJECT failed: %c%c%c%c", \
++ gcmCC_PRINT(((gcsOBJECT*) (obj))->type)); \
++ prefix##TRACE(gcvLEVEL_ERROR, " expected: %c%c%c%c", \
++ gcmCC_PRINT(t)); \
++ prefix##ASSERT(((gcsOBJECT*)(obj))->type == t); \
++ prefix##FOOTER_ARG("status=%d", gcvSTATUS_INVALID_OBJECT); \
++ return gcvSTATUS_INVALID_OBJECT; \
++ }
++
++# define gcmVERIFY_OBJECT(obj, t) _gcmVERIFY_OBJECT(gcm, obj, t)
++# define gcmkVERIFY_OBJECT(obj, t) _gcmVERIFY_OBJECT(gcmk, obj, t)
++#else
++# define gcmVERIFY_OBJECT(obj, t) do {} while (gcvFALSE)
++# define gcmkVERIFY_OBJECT(obj, t) do {} while (gcvFALSE)
++#endif
++
++/******************************************************************************/
++/*VERIFY_OBJECT if special return expected*/
++/******************************************************************************/
++#ifndef EGL_API_ANDROID
++# define _gcmVERIFY_OBJECT_RETURN(prefix, obj, t, retVal) \
++ do \
++ { \
++ if ((obj) == gcvNULL) \
++ { \
++ prefix##PRINT_VERSION(); \
++ prefix##TRACE(gcvLEVEL_ERROR, \
++ #prefix "VERIFY_OBJECT_RETURN failed: NULL"); \
++ prefix##TRACE(gcvLEVEL_ERROR, " expected: %c%c%c%c", \
++ gcmCC_PRINT(t)); \
++ prefix##ASSERT((obj) != gcvNULL); \
++ prefix##FOOTER_ARG("retVal=%d", retVal); \
++ return retVal; \
++ } \
++ else if (((gcsOBJECT*) (obj))->type != t) \
++ { \
++ prefix##PRINT_VERSION(); \
++ prefix##TRACE(gcvLEVEL_ERROR, \
++ #prefix "VERIFY_OBJECT_RETURN failed: %c%c%c%c", \
++ gcmCC_PRINT(((gcsOBJECT*) (obj))->type)); \
++ prefix##TRACE(gcvLEVEL_ERROR, " expected: %c%c%c%c", \
++ gcmCC_PRINT(t)); \
++ prefix##ASSERT(((gcsOBJECT*)(obj))->type == t); \
++ prefix##FOOTER_ARG("retVal=%d", retVal); \
++ return retVal; \
++ } \
++ } \
++ while (gcvFALSE)
++# define gcmVERIFY_OBJECT_RETURN(obj, t, retVal) \
++ _gcmVERIFY_OBJECT_RETURN(gcm, obj, t, retVal)
++# define gcmkVERIFY_OBJECT_RETURN(obj, t, retVal) \
++ _gcmVERIFY_OBJECT_RETURN(gcmk, obj, t, retVal)
++#else
++# define gcmVERIFY_OBJECT_RETURN(obj, t) do {} while (gcvFALSE)
++# define gcmVERIFY_OBJECT_RETURN(obj, t) do {} while (gcvFALSE)
++#endif
++
++/******************************************************************************\
++********************************** gckOS Object *********************************
++\******************************************************************************/
++
++/* Construct a new gckOS object. */
++gceSTATUS
++gckOS_Construct(
++ IN gctPOINTER Context,
++ OUT gckOS * Os
++ );
++
++/* Destroy an gckOS object. */
++gceSTATUS
++gckOS_Destroy(
++ IN gckOS Os
++ );
++
++/* Query the video memory. */
++gceSTATUS
++gckOS_QueryVideoMemory(
++ IN gckOS Os,
++ OUT gctPHYS_ADDR * InternalAddress,
++ OUT gctSIZE_T * InternalSize,
++ OUT gctPHYS_ADDR * ExternalAddress,
++ OUT gctSIZE_T * ExternalSize,
++ OUT gctPHYS_ADDR * ContiguousAddress,
++ OUT gctSIZE_T * ContiguousSize
++ );
++
++/* Allocate memory from the heap. */
++gceSTATUS
++gckOS_Allocate(
++ IN gckOS Os,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Memory
++ );
++
++/* Free allocated memory. */
++gceSTATUS
++gckOS_Free(
++ IN gckOS Os,
++ IN gctPOINTER Memory
++ );
++
++/* Wrapper for allocation memory.. */
++gceSTATUS
++gckOS_AllocateMemory(
++ IN gckOS Os,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Memory
++ );
++
++/* Wrapper for freeing memory. */
++gceSTATUS
++gckOS_FreeMemory(
++ IN gckOS Os,
++ IN gctPOINTER Memory
++ );
++
++/* Allocate paged memory. */
++gceSTATUS
++gckOS_AllocatePagedMemory(
++ IN gckOS Os,
++ IN gctSIZE_T Bytes,
++ OUT gctPHYS_ADDR * Physical
++ );
++
++/* Allocate paged memory. */
++gceSTATUS
++gckOS_AllocatePagedMemoryEx(
++ IN gckOS Os,
++ IN gctBOOL Contiguous,
++ IN gctSIZE_T Bytes,
++ OUT gctPHYS_ADDR * Physical
++ );
++
++/* Lock pages. */
++gceSTATUS
++gckOS_LockPages(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ IN gctBOOL Cacheable,
++ OUT gctPOINTER * Logical,
++ OUT gctSIZE_T * PageCount
++ );
++
++/* Map pages. */
++gceSTATUS
++gckOS_MapPages(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++#ifdef __QNXNTO__
++ IN gctPOINTER Logical,
++#endif
++ IN gctSIZE_T PageCount,
++ IN gctPOINTER PageTable
++ );
++
++/* Map pages. */
++gceSTATUS
++gckOS_MapPagesEx(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctPHYS_ADDR Physical,
++#ifdef __QNXNTO__
++ IN gctPOINTER Logical,
++#endif
++ IN gctSIZE_T PageCount,
++ IN gctPOINTER PageTable
++ );
++
++/* Unlock pages. */
++gceSTATUS
++gckOS_UnlockPages(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ IN gctPOINTER Logical
++ );
++
++/* Free paged memory. */
++gceSTATUS
++gckOS_FreePagedMemory(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes
++ );
++
++/* Allocate non-paged memory. */
++gceSTATUS
++gckOS_AllocateNonPagedMemory(
++ IN gckOS Os,
++ IN gctBOOL InUserSpace,
++ IN OUT gctSIZE_T * Bytes,
++ OUT gctPHYS_ADDR * Physical,
++ OUT gctPOINTER * Logical
++ );
++
++/* Free non-paged memory. */
++gceSTATUS
++gckOS_FreeNonPagedMemory(
++ IN gckOS Os,
++ IN gctSIZE_T Bytes,
++ IN gctPHYS_ADDR Physical,
++ IN gctPOINTER Logical
++ );
++
++/* Allocate contiguous memory. */
++gceSTATUS
++gckOS_AllocateContiguous(
++ IN gckOS Os,
++ IN gctBOOL InUserSpace,
++ IN OUT gctSIZE_T * Bytes,
++ OUT gctPHYS_ADDR * Physical,
++ OUT gctPOINTER * Logical
++ );
++
++/* Free contiguous memory. */
++gceSTATUS
++gckOS_FreeContiguous(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes
++ );
++
++/* Get the number fo bytes per page. */
++gceSTATUS
++gckOS_GetPageSize(
++ IN gckOS Os,
++ OUT gctSIZE_T * PageSize
++ );
++
++/* Get the physical address of a corresponding logical address. */
++gceSTATUS
++gckOS_GetPhysicalAddress(
++ IN gckOS Os,
++ IN gctPOINTER Logical,
++ OUT gctUINT32 * Address
++ );
++
++/* Get the physical address of a corresponding logical address. */
++gceSTATUS
++gckOS_GetPhysicalAddressProcess(
++ IN gckOS Os,
++ IN gctPOINTER Logical,
++ IN gctUINT32 ProcessID,
++ OUT gctUINT32 * Address
++ );
++
++/* Map physical memory. */
++gceSTATUS
++gckOS_MapPhysical(
++ IN gckOS Os,
++ IN gctUINT32 Physical,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Logical
++ );
++
++/* Unmap previously mapped physical memory. */
++gceSTATUS
++gckOS_UnmapPhysical(
++ IN gckOS Os,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes
++ );
++
++/* Read data from a hardware register. */
++gceSTATUS
++gckOS_ReadRegister(
++ IN gckOS Os,
++ IN gctUINT32 Address,
++ OUT gctUINT32 * Data
++ );
++
++/* Read data from a hardware register. */
++gceSTATUS
++gckOS_ReadRegisterEx(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctUINT32 Address,
++ OUT gctUINT32 * Data
++ );
++
++/* Write data to a hardware register. */
++gceSTATUS
++gckOS_WriteRegister(
++ IN gckOS Os,
++ IN gctUINT32 Address,
++ IN gctUINT32 Data
++ );
++
++/* Write data to a hardware register. */
++gceSTATUS
++gckOS_WriteRegisterEx(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctUINT32 Address,
++ IN gctUINT32 Data
++ );
++
++/* Write data to a 32-bit memory location. */
++gceSTATUS
++gckOS_WriteMemory(
++ IN gckOS Os,
++ IN gctPOINTER Address,
++ IN gctUINT32 Data
++ );
++
++/* Map physical memory into the process space. */
++gceSTATUS
++gckOS_MapMemory(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Logical
++ );
++
++/* Unmap physical memory from the specified process space. */
++gceSTATUS
++gckOS_UnmapMemoryEx(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ IN gctPOINTER Logical,
++ IN gctUINT32 PID
++ );
++
++/* Unmap physical memory from the process space. */
++gceSTATUS
++gckOS_UnmapMemory(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ IN gctPOINTER Logical
++ );
++
++/* Unmap user logical memory out of physical memory.
++ * This function is only supported in Linux currently.
++ */
++gceSTATUS
++gckOS_UnmapUserLogical(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ IN gctPOINTER Logical
++ );
++
++/* Create a new mutex. */
++gceSTATUS
++gckOS_CreateMutex(
++ IN gckOS Os,
++ OUT gctPOINTER * Mutex
++ );
++
++/* Delete a mutex. */
++gceSTATUS
++gckOS_DeleteMutex(
++ IN gckOS Os,
++ IN gctPOINTER Mutex
++ );
++
++/* Acquire a mutex. */
++gceSTATUS
++gckOS_AcquireMutex(
++ IN gckOS Os,
++ IN gctPOINTER Mutex,
++ IN gctUINT32 Timeout
++ );
++
++/* Release a mutex. */
++gceSTATUS
++gckOS_ReleaseMutex(
++ IN gckOS Os,
++ IN gctPOINTER Mutex
++ );
++
++/* Atomically exchange a pair of 32-bit values. */
++gceSTATUS
++gckOS_AtomicExchange(
++ IN gckOS Os,
++ IN OUT gctUINT32_PTR Target,
++ IN gctUINT32 NewValue,
++ OUT gctUINT32_PTR OldValue
++ );
++
++/* Atomically exchange a pair of pointers. */
++gceSTATUS
++gckOS_AtomicExchangePtr(
++ IN gckOS Os,
++ IN OUT gctPOINTER * Target,
++ IN gctPOINTER NewValue,
++ OUT gctPOINTER * OldValue
++ );
++
++#if gcdSMP
++gceSTATUS
++gckOS_AtomSetMask(
++ IN gctPOINTER Atom,
++ IN gctUINT32 Mask
++ );
++
++gceSTATUS
++gckOS_AtomClearMask(
++ IN gctPOINTER Atom,
++ IN gctUINT32 Mask
++ );
++#endif
++
++gceSTATUS
++gckOS_DumpCallStack(
++ IN gckOS Os
++ );
++
++gceSTATUS
++gckOS_GetProcessNameByPid(
++ IN gctINT Pid,
++ IN gctSIZE_T Length,
++ OUT gctUINT8_PTR String
++ );
++
++
++
++/*******************************************************************************
++**
++** gckOS_AtomConstruct
++**
++** Create an atom.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** OUTPUT:
++**
++** gctPOINTER * Atom
++** Pointer to a variable receiving the constructed atom.
++*/
++gceSTATUS
++gckOS_AtomConstruct(
++ IN gckOS Os,
++ OUT gctPOINTER * Atom
++ );
++
++/*******************************************************************************
++**
++** gckOS_AtomDestroy
++**
++** Destroy an atom.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gctPOINTER Atom
++** Pointer to the atom to destroy.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_AtomDestroy(
++ IN gckOS Os,
++ OUT gctPOINTER Atom
++ );
++
++/*******************************************************************************
++**
++** gckOS_AtomGet
++**
++** Get the 32-bit value protected by an atom.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gctPOINTER Atom
++** Pointer to the atom.
++**
++** OUTPUT:
++**
++** gctINT32_PTR Value
++** Pointer to a variable the receives the value of the atom.
++*/
++gceSTATUS
++gckOS_AtomGet(
++ IN gckOS Os,
++ IN gctPOINTER Atom,
++ OUT gctINT32_PTR Value
++ );
++
++/*******************************************************************************
++**
++** gckOS_AtomSet
++**
++** Set the 32-bit value protected by an atom.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gctPOINTER Atom
++** Pointer to the atom.
++**
++** gctINT32 Value
++** The value of the atom.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_AtomSet(
++ IN gckOS Os,
++ IN gctPOINTER Atom,
++ IN gctINT32 Value
++ );
++
++/*******************************************************************************
++**
++** gckOS_AtomIncrement
++**
++** Atomically increment the 32-bit integer value inside an atom.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gctPOINTER Atom
++** Pointer to the atom.
++**
++** OUTPUT:
++**
++** gctINT32_PTR Value
++** Pointer to a variable the receives the original value of the atom.
++*/
++gceSTATUS
++gckOS_AtomIncrement(
++ IN gckOS Os,
++ IN gctPOINTER Atom,
++ OUT gctINT32_PTR Value
++ );
++
++/*******************************************************************************
++**
++** gckOS_AtomDecrement
++**
++** Atomically decrement the 32-bit integer value inside an atom.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gctPOINTER Atom
++** Pointer to the atom.
++**
++** OUTPUT:
++**
++** gctINT32_PTR Value
++** Pointer to a variable the receives the original value of the atom.
++*/
++gceSTATUS
++gckOS_AtomDecrement(
++ IN gckOS Os,
++ IN gctPOINTER Atom,
++ OUT gctINT32_PTR Value
++ );
++
++/* Delay a number of microseconds. */
++gceSTATUS
++gckOS_Delay(
++ IN gckOS Os,
++ IN gctUINT32 Delay
++ );
++
++/* Get time in milliseconds. */
++gceSTATUS
++gckOS_GetTicks(
++ OUT gctUINT32_PTR Time
++ );
++
++/* Compare time value. */
++gceSTATUS
++gckOS_TicksAfter(
++ IN gctUINT32 Time1,
++ IN gctUINT32 Time2,
++ OUT gctBOOL_PTR IsAfter
++ );
++
++/* Get time in microseconds. */
++gceSTATUS
++gckOS_GetTime(
++ OUT gctUINT64_PTR Time
++ );
++
++/* Memory barrier. */
++gceSTATUS
++gckOS_MemoryBarrier(
++ IN gckOS Os,
++ IN gctPOINTER Address
++ );
++
++/* Map user pointer. */
++gceSTATUS
++gckOS_MapUserPointer(
++ IN gckOS Os,
++ IN gctPOINTER Pointer,
++ IN gctSIZE_T Size,
++ OUT gctPOINTER * KernelPointer
++ );
++
++/* Unmap user pointer. */
++gceSTATUS
++gckOS_UnmapUserPointer(
++ IN gckOS Os,
++ IN gctPOINTER Pointer,
++ IN gctSIZE_T Size,
++ IN gctPOINTER KernelPointer
++ );
++
++/*******************************************************************************
++**
++** gckOS_QueryNeedCopy
++**
++** Query whether the memory can be accessed or mapped directly or it has to be
++** copied.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctUINT32 ProcessID
++** Process ID of the current process.
++**
++** OUTPUT:
++**
++** gctBOOL_PTR NeedCopy
++** Pointer to a boolean receiving gcvTRUE if the memory needs a copy or
++** gcvFALSE if the memory can be accessed or mapped dircetly.
++*/
++gceSTATUS
++gckOS_QueryNeedCopy(
++ IN gckOS Os,
++ IN gctUINT32 ProcessID,
++ OUT gctBOOL_PTR NeedCopy
++ );
++
++/*******************************************************************************
++**
++** gckOS_CopyFromUserData
++**
++** Copy data from user to kernel memory.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPOINTER KernelPointer
++** Pointer to kernel memory.
++**
++** gctPOINTER Pointer
++** Pointer to user memory.
++**
++** gctSIZE_T Size
++** Number of bytes to copy.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_CopyFromUserData(
++ IN gckOS Os,
++ IN gctPOINTER KernelPointer,
++ IN gctPOINTER Pointer,
++ IN gctSIZE_T Size
++ );
++
++/*******************************************************************************
++**
++** gckOS_CopyToUserData
++**
++** Copy data from kernel to user memory.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPOINTER KernelPointer
++** Pointer to kernel memory.
++**
++** gctPOINTER Pointer
++** Pointer to user memory.
++**
++** gctSIZE_T Size
++** Number of bytes to copy.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_CopyToUserData(
++ IN gckOS Os,
++ IN gctPOINTER KernelPointer,
++ IN gctPOINTER Pointer,
++ IN gctSIZE_T Size
++ );
++
++#ifdef __QNXNTO__
++/* Map user physical address. */
++gceSTATUS
++gckOS_MapUserPhysical(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Phys,
++ OUT gctPOINTER * KernelPointer
++ );
++#endif
++
++gceSTATUS
++gckOS_SuspendInterrupt(
++ IN gckOS Os
++ );
++
++gceSTATUS
++gckOS_SuspendInterruptEx(
++ IN gckOS Os,
++ IN gceCORE Core
++ );
++
++gceSTATUS
++gckOS_ResumeInterrupt(
++ IN gckOS Os
++ );
++
++gceSTATUS
++gckOS_ResumeInterruptEx(
++ IN gckOS Os,
++ IN gceCORE Core
++ );
++
++/* Get the base address for the physical memory. */
++gceSTATUS
++gckOS_GetBaseAddress(
++ IN gckOS Os,
++ OUT gctUINT32_PTR BaseAddress
++ );
++
++/* Perform a memory copy. */
++gceSTATUS
++gckOS_MemCopy(
++ IN gctPOINTER Destination,
++ IN gctCONST_POINTER Source,
++ IN gctSIZE_T Bytes
++ );
++
++/* Zero memory. */
++gceSTATUS
++gckOS_ZeroMemory(
++ IN gctPOINTER Memory,
++ IN gctSIZE_T Bytes
++ );
++
++/* Device I/O control to the kernel HAL layer. */
++gceSTATUS
++gckOS_DeviceControl(
++ IN gckOS Os,
++ IN gctBOOL FromUser,
++ IN gctUINT32 IoControlCode,
++ IN gctPOINTER InputBuffer,
++ IN gctSIZE_T InputBufferSize,
++ OUT gctPOINTER OutputBuffer,
++ IN gctSIZE_T OutputBufferSize
++ );
++
++/*******************************************************************************
++**
++** gckOS_GetProcessID
++**
++** Get current process ID.
++**
++** INPUT:
++**
++** Nothing.
++**
++** OUTPUT:
++**
++** gctUINT32_PTR ProcessID
++** Pointer to the variable that receives the process ID.
++*/
++gceSTATUS
++gckOS_GetProcessID(
++ OUT gctUINT32_PTR ProcessID
++ );
++
++gceSTATUS
++gckOS_GetCurrentProcessID(
++ OUT gctUINT32_PTR ProcessID
++ );
++
++/*******************************************************************************
++**
++** gckOS_GetThreadID
++**
++** Get current thread ID.
++**
++** INPUT:
++**
++** Nothing.
++**
++** OUTPUT:
++**
++** gctUINT32_PTR ThreadID
++** Pointer to the variable that receives the thread ID.
++*/
++gceSTATUS
++gckOS_GetThreadID(
++ OUT gctUINT32_PTR ThreadID
++ );
++
++/******************************************************************************\
++********************************** Signal Object *********************************
++\******************************************************************************/
++
++/* Create a signal. */
++gceSTATUS
++gckOS_CreateSignal(
++ IN gckOS Os,
++ IN gctBOOL ManualReset,
++ OUT gctSIGNAL * Signal
++ );
++
++/* Destroy a signal. */
++gceSTATUS
++gckOS_DestroySignal(
++ IN gckOS Os,
++ IN gctSIGNAL Signal
++ );
++
++/* Signal a signal. */
++gceSTATUS
++gckOS_Signal(
++ IN gckOS Os,
++ IN gctSIGNAL Signal,
++ IN gctBOOL State
++ );
++
++/* Wait for a signal. */
++gceSTATUS
++gckOS_WaitSignal(
++ IN gckOS Os,
++ IN gctSIGNAL Signal,
++ IN gctUINT32 Wait
++ );
++
++/* Map a user signal to the kernel space. */
++gceSTATUS
++gckOS_MapSignal(
++ IN gckOS Os,
++ IN gctSIGNAL Signal,
++ IN gctHANDLE Process,
++ OUT gctSIGNAL * MappedSignal
++ );
++
++/* Unmap a user signal */
++gceSTATUS
++gckOS_UnmapSignal(
++ IN gckOS Os,
++ IN gctSIGNAL Signal
++ );
++
++/* Map user memory. */
++gceSTATUS
++gckOS_MapUserMemory(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctPOINTER Memory,
++ IN gctUINT32 Physical,
++ IN gctSIZE_T Size,
++ OUT gctPOINTER * Info,
++ OUT gctUINT32_PTR Address
++ );
++
++/* Unmap user memory. */
++gceSTATUS
++gckOS_UnmapUserMemory(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctPOINTER Memory,
++ IN gctSIZE_T Size,
++ IN gctPOINTER Info,
++ IN gctUINT32 Address
++ );
++
++/******************************************************************************\
++************************** Android Native Fence Sync ***************************
++\******************************************************************************/
++gceSTATUS
++gckOS_CreateSyncTimeline(
++ IN gckOS Os,
++ OUT gctHANDLE * Timeline
++ );
++
++gceSTATUS
++gckOS_DestroySyncTimeline(
++ IN gckOS Os,
++ IN gctHANDLE Timeline
++ );
++
++gceSTATUS
++gckOS_CreateSyncPoint(
++ IN gckOS Os,
++ OUT gctSYNC_POINT * SyncPoint
++ );
++
++gceSTATUS
++gckOS_ReferenceSyncPoint(
++ IN gckOS Os,
++ IN gctSYNC_POINT SyncPoint
++ );
++
++gceSTATUS
++gckOS_DestroySyncPoint(
++ IN gckOS Os,
++ IN gctSYNC_POINT SyncPoint
++ );
++
++gceSTATUS
++gckOS_SignalSyncPoint(
++ IN gckOS Os,
++ IN gctSYNC_POINT SyncPoint
++ );
++
++gceSTATUS
++gckOS_QuerySyncPoint(
++ IN gckOS Os,
++ IN gctSYNC_POINT SyncPoint,
++ OUT gctBOOL_PTR State
++ );
++
++gceSTATUS
++gckOS_CreateNativeFence(
++ IN gckOS Os,
++ IN gctHANDLE Timeline,
++ IN gctSYNC_POINT SyncPoint,
++ OUT gctINT * FenceFD
++ );
++
++#if !USE_NEW_LINUX_SIGNAL
++/* Create signal to be used in the user space. */
++gceSTATUS
++gckOS_CreateUserSignal(
++ IN gckOS Os,
++ IN gctBOOL ManualReset,
++ OUT gctINT * SignalID
++ );
++
++/* Destroy signal used in the user space. */
++gceSTATUS
++gckOS_DestroyUserSignal(
++ IN gckOS Os,
++ IN gctINT SignalID
++ );
++
++/* Wait for signal used in the user space. */
++gceSTATUS
++gckOS_WaitUserSignal(
++ IN gckOS Os,
++ IN gctINT SignalID,
++ IN gctUINT32 Wait
++ );
++
++/* Signal a signal used in the user space. */
++gceSTATUS
++gckOS_SignalUserSignal(
++ IN gckOS Os,
++ IN gctINT SignalID,
++ IN gctBOOL State
++ );
++#endif /* USE_NEW_LINUX_SIGNAL */
++
++/* Set a signal owned by a process. */
++#if defined(__QNXNTO__)
++gceSTATUS
++gckOS_UserSignal(
++ IN gckOS Os,
++ IN gctSIGNAL Signal,
++ IN gctINT Recvid,
++ IN gctINT Coid
++ );
++#else
++gceSTATUS
++gckOS_UserSignal(
++ IN gckOS Os,
++ IN gctSIGNAL Signal,
++ IN gctHANDLE Process
++ );
++#endif
++
++/******************************************************************************\
++** Cache Support
++*/
++
++gceSTATUS
++gckOS_CacheClean(
++ gckOS Os,
++ gctUINT32 ProcessID,
++ gctPHYS_ADDR Handle,
++ gctPOINTER Physical,
++ gctPOINTER Logical,
++ gctSIZE_T Bytes
++ );
++
++gceSTATUS
++gckOS_CacheFlush(
++ gckOS Os,
++ gctUINT32 ProcessID,
++ gctPHYS_ADDR Handle,
++ gctPOINTER Physical,
++ gctPOINTER Logical,
++ gctSIZE_T Bytes
++ );
++
++gceSTATUS
++gckOS_CacheInvalidate(
++ gckOS Os,
++ gctUINT32 ProcessID,
++ gctPHYS_ADDR Handle,
++ gctPOINTER Physical,
++ gctPOINTER Logical,
++ gctSIZE_T Bytes
++ );
++
++/******************************************************************************\
++** Debug Support
++*/
++
++void
++gckOS_SetDebugLevel(
++ IN gctUINT32 Level
++ );
++
++void
++gckOS_SetDebugZone(
++ IN gctUINT32 Zone
++ );
++
++void
++gckOS_SetDebugLevelZone(
++ IN gctUINT32 Level,
++ IN gctUINT32 Zone
++ );
++
++void
++gckOS_SetDebugZones(
++ IN gctUINT32 Zones,
++ IN gctBOOL Enable
++ );
++
++void
++gckOS_SetDebugFile(
++ IN gctCONST_STRING FileName
++ );
++
++/*******************************************************************************
++** Broadcast interface.
++*/
++
++typedef enum _gceBROADCAST
++{
++ /* GPU might be idle. */
++ gcvBROADCAST_GPU_IDLE,
++
++ /* A commit is going to happen. */
++ gcvBROADCAST_GPU_COMMIT,
++
++ /* GPU seems to be stuck. */
++ gcvBROADCAST_GPU_STUCK,
++
++ /* First process gets attached. */
++ gcvBROADCAST_FIRST_PROCESS,
++
++ /* Last process gets detached. */
++ gcvBROADCAST_LAST_PROCESS,
++
++ /* AXI bus error. */
++ gcvBROADCAST_AXI_BUS_ERROR,
++}
++gceBROADCAST;
++
++gceSTATUS
++gckOS_Broadcast(
++ IN gckOS Os,
++ IN gckHARDWARE Hardware,
++ IN gceBROADCAST Reason
++ );
++
++gceSTATUS
++gckOS_BroadcastHurry(
++ IN gckOS Os,
++ IN gckHARDWARE Hardware,
++ IN gctUINT Urgency
++ );
++
++gceSTATUS
++gckOS_BroadcastCalibrateSpeed(
++ IN gckOS Os,
++ IN gckHARDWARE Hardware,
++ IN gctUINT Idle,
++ IN gctUINT Time
++ );
++
++/*******************************************************************************
++**
++** gckOS_SetGPUPower
++**
++** Set the power of the GPU on or off.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.ß
++**
++** gckCORE Core
++** GPU whose power is set.
++**
++** gctBOOL Clock
++** gcvTRUE to turn on the clock, or gcvFALSE to turn off the clock.
++**
++** gctBOOL Power
++** gcvTRUE to turn on the power, or gcvFALSE to turn off the power.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_SetGPUPower(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctBOOL Clock,
++ IN gctBOOL Power
++ );
++
++gceSTATUS
++gckOS_ResetGPU(
++ IN gckOS Os,
++ IN gceCORE Core
++ );
++
++gceSTATUS
++gckOS_PrepareGPUFrequency(
++ IN gckOS Os,
++ IN gceCORE Core
++ );
++
++gceSTATUS
++gckOS_FinishGPUFrequency(
++ IN gckOS Os,
++ IN gceCORE Core
++ );
++
++gceSTATUS
++gckOS_QueryGPUFrequency(
++ IN gckOS Os,
++ IN gceCORE Core,
++ OUT gctUINT32 * Frequency,
++ OUT gctUINT8 * Scale
++ );
++
++gceSTATUS
++gckOS_SetGPUFrequency(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctUINT8 Scale
++ );
++
++/*******************************************************************************
++** Semaphores.
++*/
++
++/* Create a new semaphore. */
++gceSTATUS
++gckOS_CreateSemaphore(
++ IN gckOS Os,
++ OUT gctPOINTER * Semaphore
++ );
++
++#if gcdENABLE_VG
++gceSTATUS
++gckOS_CreateSemaphoreVG(
++ IN gckOS Os,
++ OUT gctPOINTER * Semaphore
++ );
++#endif
++
++/* Delete a semahore. */
++gceSTATUS
++gckOS_DestroySemaphore(
++ IN gckOS Os,
++ IN gctPOINTER Semaphore
++ );
++
++/* Acquire a semahore. */
++gceSTATUS
++gckOS_AcquireSemaphore(
++ IN gckOS Os,
++ IN gctPOINTER Semaphore
++ );
++
++/* Try to acquire a semahore. */
++gceSTATUS
++gckOS_TryAcquireSemaphore(
++ IN gckOS Os,
++ IN gctPOINTER Semaphore
++ );
++
++/* Release a semahore. */
++gceSTATUS
++gckOS_ReleaseSemaphore(
++ IN gckOS Os,
++ IN gctPOINTER Semaphore
++ );
++
++/*******************************************************************************
++** Timer API.
++*/
++
++typedef void (*gctTIMERFUNCTION)(gctPOINTER);
++
++/* Create a timer. */
++gceSTATUS
++gckOS_CreateTimer(
++ IN gckOS Os,
++ IN gctTIMERFUNCTION Function,
++ IN gctPOINTER Data,
++ OUT gctPOINTER * Timer
++ );
++
++/* Destory a timer. */
++gceSTATUS
++gckOS_DestroyTimer(
++ IN gckOS Os,
++ IN gctPOINTER Timer
++ );
++
++/* Start a timer. */
++gceSTATUS
++gckOS_StartTimer(
++ IN gckOS Os,
++ IN gctPOINTER Timer,
++ IN gctUINT32 Delay
++ );
++
++/* Stop a timer. */
++gceSTATUS
++gckOS_StopTimer(
++ IN gckOS Os,
++ IN gctPOINTER Timer
++ );
++
++/* Get the global video memory mutex. */
++gceSTATUS
++gckOS_GetVideoMemoryMutex(
++ IN gckOS Os,
++ OUT gctPOINTER *Mutex
++ );
++
++/******************************************************************************\
++********************************* gckHEAP Object ********************************
++\******************************************************************************/
++
++typedef struct _gckHEAP * gckHEAP;
++
++/* Construct a new gckHEAP object. */
++gceSTATUS
++gckHEAP_Construct(
++ IN gckOS Os,
++ IN gctSIZE_T AllocationSize,
++ OUT gckHEAP * Heap
++ );
++
++/* Destroy an gckHEAP object. */
++gceSTATUS
++gckHEAP_Destroy(
++ IN gckHEAP Heap
++ );
++
++/* Allocate memory. */
++gceSTATUS
++gckHEAP_Allocate(
++ IN gckHEAP Heap,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Node
++ );
++
++/* Free memory. */
++gceSTATUS
++gckHEAP_Free(
++ IN gckHEAP Heap,
++ IN gctPOINTER Node
++ );
++
++/* Profile the heap. */
++gceSTATUS
++gckHEAP_ProfileStart(
++ IN gckHEAP Heap
++ );
++
++gceSTATUS
++gckHEAP_ProfileEnd(
++ IN gckHEAP Heap,
++ IN gctCONST_STRING Title
++ );
++
++
++/******************************************************************************\
++******************************** gckVIDMEM Object ******************************
++\******************************************************************************/
++
++typedef struct _gckVIDMEM * gckVIDMEM;
++typedef struct _gckKERNEL * gckKERNEL;
++typedef struct _gckDB * gckDB;
++typedef struct _gckDVFS * gckDVFS;
++
++/* Construct a new gckVIDMEM object. */
++gceSTATUS
++gckVIDMEM_Construct(
++ IN gckOS Os,
++ IN gctUINT32 BaseAddress,
++ IN gctSIZE_T Bytes,
++ IN gctSIZE_T Threshold,
++ IN gctSIZE_T Banking,
++ OUT gckVIDMEM * Memory
++ );
++
++/* Destroy an gckVDIMEM object. */
++gceSTATUS
++gckVIDMEM_Destroy(
++ IN gckVIDMEM Memory
++ );
++
++/* Allocate rectangular memory. */
++gceSTATUS
++gckVIDMEM_Allocate(
++ IN gckKERNEL Kernel,
++ IN gckVIDMEM Memory,
++ IN gctUINT Width,
++ IN gctUINT Height,
++ IN gctUINT Depth,
++ IN gctUINT BytesPerPixel,
++ IN gctUINT32 Alignment,
++ IN gceSURF_TYPE Type,
++ OUT gcuVIDMEM_NODE_PTR * Node
++ );
++
++/* Allocate linear memory. */
++gceSTATUS
++gckVIDMEM_AllocateLinear(
++ IN gckKERNEL Kernel,
++ IN gckVIDMEM Memory,
++ IN gctSIZE_T Bytes,
++ IN gctUINT32 Alignment,
++ IN gceSURF_TYPE Type,
++ OUT gcuVIDMEM_NODE_PTR * Node
++ );
++
++/* Free memory. */
++gceSTATUS
++gckVIDMEM_Free(
++ IN gckKERNEL Kernel,
++ IN gcuVIDMEM_NODE_PTR Node
++ );
++
++/* Lock memory. */
++gceSTATUS
++gckVIDMEM_Lock(
++ IN gckKERNEL Kernel,
++ IN gcuVIDMEM_NODE_PTR Node,
++ IN gctBOOL Cacheable,
++ OUT gctUINT32 * Address
++ );
++
++/* Unlock memory. */
++gceSTATUS
++gckVIDMEM_Unlock(
++ IN gckKERNEL Kernel,
++ IN gcuVIDMEM_NODE_PTR Node,
++ IN gceSURF_TYPE Type,
++ IN OUT gctBOOL * Asynchroneous
++ );
++
++/* Construct a gcuVIDMEM_NODE union for virtual memory. */
++gceSTATUS
++gckVIDMEM_ConstructVirtual(
++ IN gckKERNEL Kernel,
++ IN gctBOOL Contiguous,
++ IN gctSIZE_T Bytes,
++ OUT gcuVIDMEM_NODE_PTR * Node
++ );
++
++/* Destroy a gcuVIDMEM_NODE union for virtual memory. */
++gceSTATUS
++gckVIDMEM_DestroyVirtual(
++ IN gcuVIDMEM_NODE_PTR Node
++ );
++
++/******************************************************************************\
++******************************** gckKERNEL Object ******************************
++\******************************************************************************/
++
++struct _gcsHAL_INTERFACE;
++
++/* Notifications. */
++typedef enum _gceNOTIFY
++{
++ gcvNOTIFY_INTERRUPT,
++ gcvNOTIFY_COMMAND_QUEUE,
++}
++gceNOTIFY;
++
++/* Flush flags. */
++typedef enum _gceKERNEL_FLUSH
++{
++ gcvFLUSH_COLOR = 0x01,
++ gcvFLUSH_DEPTH = 0x02,
++ gcvFLUSH_TEXTURE = 0x04,
++ gcvFLUSH_2D = 0x08,
++ gcvFLUSH_ALL = gcvFLUSH_COLOR
++ | gcvFLUSH_DEPTH
++ | gcvFLUSH_TEXTURE
++ | gcvFLUSH_2D,
++}
++gceKERNEL_FLUSH;
++
++/* Construct a new gckKERNEL object. */
++gceSTATUS
++gckKERNEL_Construct(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctPOINTER Context,
++ IN gckDB SharedDB,
++ OUT gckKERNEL * Kernel
++ );
++
++/* Destroy an gckKERNEL object. */
++gceSTATUS
++gckKERNEL_Destroy(
++ IN gckKERNEL Kernel
++ );
++
++/* Dispatch a user-level command. */
++gceSTATUS
++gckKERNEL_Dispatch(
++ IN gckKERNEL Kernel,
++ IN gctBOOL FromUser,
++ IN OUT struct _gcsHAL_INTERFACE * Interface
++ );
++
++/* Query the video memory. */
++gceSTATUS
++gckKERNEL_QueryVideoMemory(
++ IN gckKERNEL Kernel,
++ OUT struct _gcsHAL_INTERFACE * Interface
++ );
++
++/* Lookup the gckVIDMEM object for a pool. */
++gceSTATUS
++gckKERNEL_GetVideoMemoryPool(
++ IN gckKERNEL Kernel,
++ IN gcePOOL Pool,
++ OUT gckVIDMEM * VideoMemory
++ );
++
++#if gcdUSE_VIDMEM_PER_PID
++gceSTATUS
++gckKERNEL_GetVideoMemoryPoolPid(
++ IN gckKERNEL Kernel,
++ IN gcePOOL Pool,
++ IN gctUINT32 Pid,
++ OUT gckVIDMEM * VideoMemory
++ );
++
++gceSTATUS
++gckKERNEL_CreateVideoMemoryPoolPid(
++ IN gckKERNEL Kernel,
++ IN gcePOOL Pool,
++ IN gctUINT32 Pid,
++ OUT gckVIDMEM * VideoMemory
++ );
++
++gceSTATUS
++gckKERNEL_RemoveVideoMemoryPoolPid(
++ IN gckKERNEL Kernel,
++ IN gckVIDMEM VideoMemory
++ );
++#endif
++
++/* Map video memory. */
++gceSTATUS
++gckKERNEL_MapVideoMemory(
++ IN gckKERNEL Kernel,
++ IN gctBOOL InUserSpace,
++ IN gctUINT32 Address,
++#ifdef __QNXNTO__
++ IN gctUINT32 Pid,
++ IN gctUINT32 Bytes,
++#endif
++ OUT gctPOINTER * Logical
++ );
++
++/* Map video memory. */
++gceSTATUS
++gckKERNEL_MapVideoMemoryEx(
++ IN gckKERNEL Kernel,
++ IN gceCORE Core,
++ IN gctBOOL InUserSpace,
++ IN gctUINT32 Address,
++#ifdef __QNXNTO__
++ IN gctUINT32 Pid,
++ IN gctUINT32 Bytes,
++#endif
++ OUT gctPOINTER * Logical
++ );
++
++#ifdef __QNXNTO__
++/* Unmap video memory. */
++gceSTATUS
++gckKERNEL_UnmapVideoMemory(
++ IN gckKERNEL Kernel,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Pid,
++ IN gctUINT32 Bytes
++ );
++#endif
++
++/* Map memory. */
++gceSTATUS
++gckKERNEL_MapMemory(
++ IN gckKERNEL Kernel,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Logical
++ );
++
++/* Unmap memory. */
++gceSTATUS
++gckKERNEL_UnmapMemory(
++ IN gckKERNEL Kernel,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ IN gctPOINTER Logical
++ );
++
++/* Notification of events. */
++gceSTATUS
++gckKERNEL_Notify(
++ IN gckKERNEL Kernel,
++ IN gceNOTIFY Notifcation,
++ IN gctBOOL Data
++ );
++
++gceSTATUS
++gckKERNEL_QuerySettings(
++ IN gckKERNEL Kernel,
++ OUT gcsKERNEL_SETTINGS * Settings
++ );
++
++/*******************************************************************************
++**
++** gckKERNEL_Recovery
++**
++** Try to recover the GPU from a fatal error.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckKERNEL_Recovery(
++ IN gckKERNEL Kernel
++ );
++
++/* Set the value of timeout on HW operation. */
++void
++gckKERNEL_SetTimeOut(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 timeOut
++ );
++
++/* Get access to the user data. */
++gceSTATUS
++gckKERNEL_OpenUserData(
++ IN gckKERNEL Kernel,
++ IN gctBOOL NeedCopy,
++ IN gctPOINTER StaticStorage,
++ IN gctPOINTER UserPointer,
++ IN gctSIZE_T Size,
++ OUT gctPOINTER * KernelPointer
++ );
++
++/* Release resources associated with the user data connection. */
++gceSTATUS
++gckKERNEL_CloseUserData(
++ IN gckKERNEL Kernel,
++ IN gctBOOL NeedCopy,
++ IN gctBOOL FlushData,
++ IN gctPOINTER UserPointer,
++ IN gctSIZE_T Size,
++ OUT gctPOINTER * KernelPointer
++ );
++
++gceSTATUS
++gckDVFS_Construct(
++ IN gckHARDWARE Hardware,
++ OUT gckDVFS * Frequency
++ );
++
++gceSTATUS
++gckDVFS_Destroy(
++ IN gckDVFS Dvfs
++ );
++
++gceSTATUS
++gckDVFS_Start(
++ IN gckDVFS Dvfs
++ );
++
++gceSTATUS
++gckDVFS_Stop(
++ IN gckDVFS Dvfs
++ );
++
++/******************************************************************************\
++******************************* gckHARDWARE Object *****************************
++\******************************************************************************/
++
++/* Construct a new gckHARDWARE object. */
++gceSTATUS
++gckHARDWARE_Construct(
++ IN gckOS Os,
++ IN gceCORE Core,
++ OUT gckHARDWARE * Hardware
++ );
++
++/* Destroy an gckHARDWARE object. */
++gceSTATUS
++gckHARDWARE_Destroy(
++ IN gckHARDWARE Hardware
++ );
++
++/* Get hardware type. */
++gceSTATUS
++gckHARDWARE_GetType(
++ IN gckHARDWARE Hardware,
++ OUT gceHARDWARE_TYPE * Type
++ );
++
++/* Query system memory requirements. */
++gceSTATUS
++gckHARDWARE_QuerySystemMemory(
++ IN gckHARDWARE Hardware,
++ OUT gctSIZE_T * SystemSize,
++ OUT gctUINT32 * SystemBaseAddress
++ );
++
++/* Build virtual address. */
++gceSTATUS
++gckHARDWARE_BuildVirtualAddress(
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 Index,
++ IN gctUINT32 Offset,
++ OUT gctUINT32 * Address
++ );
++
++/* Query command buffer requirements. */
++gceSTATUS
++gckHARDWARE_QueryCommandBuffer(
++ IN gckHARDWARE Hardware,
++ OUT gctSIZE_T * Alignment,
++ OUT gctSIZE_T * ReservedHead,
++ OUT gctSIZE_T * ReservedTail
++ );
++
++/* Add a WAIT/LINK pair in the command queue. */
++gceSTATUS
++gckHARDWARE_WaitLink(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Offset,
++ IN OUT gctSIZE_T * Bytes,
++ OUT gctUINT32 * WaitOffset,
++ OUT gctSIZE_T * WaitBytes
++ );
++
++/* Kickstart the command processor. */
++gceSTATUS
++gckHARDWARE_Execute(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++#ifdef __QNXNTO__
++ IN gctPOINTER Physical,
++ IN gctBOOL PhysicalAddresses,
++#endif
++ IN gctSIZE_T Bytes
++ );
++
++/* Add an END command in the command queue. */
++gceSTATUS
++gckHARDWARE_End(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN OUT gctSIZE_T * Bytes
++ );
++
++/* Add a NOP command in the command queue. */
++gceSTATUS
++gckHARDWARE_Nop(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN OUT gctSIZE_T * Bytes
++ );
++
++/* Add a WAIT command in the command queue. */
++gceSTATUS
++gckHARDWARE_Wait(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Count,
++ IN OUT gctSIZE_T * Bytes
++ );
++
++/* Add a PIPESELECT command in the command queue. */
++gceSTATUS
++gckHARDWARE_PipeSelect(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN gcePIPE_SELECT Pipe,
++ IN OUT gctSIZE_T * Bytes
++ );
++
++/* Add a LINK command in the command queue. */
++gceSTATUS
++gckHARDWARE_Link(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN gctPOINTER FetchAddress,
++ IN gctSIZE_T FetchSize,
++ IN OUT gctSIZE_T * Bytes
++ );
++
++/* Add an EVENT command in the command queue. */
++gceSTATUS
++gckHARDWARE_Event(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN gctUINT8 Event,
++ IN gceKERNEL_WHERE FromWhere,
++ IN OUT gctSIZE_T * Bytes
++ );
++
++/* Query the available memory. */
++gceSTATUS
++gckHARDWARE_QueryMemory(
++ IN gckHARDWARE Hardware,
++ OUT gctSIZE_T * InternalSize,
++ OUT gctUINT32 * InternalBaseAddress,
++ OUT gctUINT32 * InternalAlignment,
++ OUT gctSIZE_T * ExternalSize,
++ OUT gctUINT32 * ExternalBaseAddress,
++ OUT gctUINT32 * ExternalAlignment,
++ OUT gctUINT32 * HorizontalTileSize,
++ OUT gctUINT32 * VerticalTileSize
++ );
++
++/* Query the identity of the hardware. */
++gceSTATUS
++gckHARDWARE_QueryChipIdentity(
++ IN gckHARDWARE Hardware,
++ OUT gcsHAL_QUERY_CHIP_IDENTITY_PTR Identity
++ );
++
++/* Query the shader support. */
++gceSTATUS
++gckHARDWARE_QueryShaderCaps(
++ IN gckHARDWARE Hardware,
++ OUT gctUINT * VertexUniforms,
++ OUT gctUINT * FragmentUniforms,
++ OUT gctUINT * Varyings
++ );
++
++/* Split a harwdare specific address into API stuff. */
++gceSTATUS
++gckHARDWARE_SplitMemory(
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 Address,
++ OUT gcePOOL * Pool,
++ OUT gctUINT32 * Offset
++ );
++
++/* Update command queue tail pointer. */
++gceSTATUS
++gckHARDWARE_UpdateQueueTail(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Offset
++ );
++
++/* Convert logical address to hardware specific address. */
++gceSTATUS
++gckHARDWARE_ConvertLogical(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ OUT gctUINT32 * Address
++ );
++
++#ifdef __QNXNTO__
++/* Convert physical address to hardware specific address. */
++gceSTATUS
++gckHARDWARE_ConvertPhysical(
++ IN gckHARDWARE Hardware,
++ IN gctPHYS_ADDR Physical,
++ OUT gctUINT32 * Address
++ );
++#endif
++
++/* Interrupt manager. */
++gceSTATUS
++gckHARDWARE_Interrupt(
++ IN gckHARDWARE Hardware,
++ IN gctBOOL InterruptValid
++ );
++
++/* Program MMU. */
++gceSTATUS
++gckHARDWARE_SetMMU(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical
++ );
++
++/* Flush the MMU. */
++gceSTATUS
++gckHARDWARE_FlushMMU(
++ IN gckHARDWARE Hardware
++ );
++
++/* Set the page table base address. */
++gceSTATUS
++gckHARDWARE_SetMMUv2(
++ IN gckHARDWARE Hardware,
++ IN gctBOOL Enable,
++ IN gctPOINTER MtlbAddress,
++ IN gceMMU_MODE Mode,
++ IN gctPOINTER SafeAddress,
++ IN gctBOOL FromPower
++ );
++
++/* Get idle register. */
++gceSTATUS
++gckHARDWARE_GetIdle(
++ IN gckHARDWARE Hardware,
++ IN gctBOOL Wait,
++ OUT gctUINT32 * Data
++ );
++
++/* Flush the caches. */
++gceSTATUS
++gckHARDWARE_Flush(
++ IN gckHARDWARE Hardware,
++ IN gceKERNEL_FLUSH Flush,
++ IN gctPOINTER Logical,
++ IN OUT gctSIZE_T * Bytes
++ );
++
++/* Enable/disable fast clear. */
++gceSTATUS
++gckHARDWARE_SetFastClear(
++ IN gckHARDWARE Hardware,
++ IN gctINT Enable,
++ IN gctINT Compression
++ );
++
++gceSTATUS
++gckHARDWARE_ReadInterrupt(
++ IN gckHARDWARE Hardware,
++ OUT gctUINT32_PTR IDs
++ );
++
++/* Power management. */
++gceSTATUS
++gckHARDWARE_SetPowerManagementState(
++ IN gckHARDWARE Hardware,
++ IN gceCHIPPOWERSTATE State
++ );
++
++gceSTATUS
++gckHARDWARE_QueryPowerManagementState(
++ IN gckHARDWARE Hardware,
++ OUT gceCHIPPOWERSTATE* State
++ );
++
++gceSTATUS
++gckHARDWARE_SetPowerManagement(
++ IN gckHARDWARE Hardware,
++ IN gctBOOL PowerManagement
++ );
++
++gceSTATUS
++gckHARDWARE_SetGpuProfiler(
++ IN gckHARDWARE Hardware,
++ IN gctBOOL GpuProfiler
++ );
++
++#if gcdENABLE_FSCALE_VAL_ADJUST
++gceSTATUS
++gckHARDWARE_SetFscaleValue(
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 FscaleValue
++ );
++
++gceSTATUS
++gckHARDWARE_GetFscaleValue(
++ IN gckHARDWARE Hardware,
++ IN gctUINT * FscaleValue,
++ IN gctUINT * MinFscaleValue,
++ IN gctUINT * MaxFscaleValue
++ );
++#endif
++
++#if gcdPOWEROFF_TIMEOUT
++gceSTATUS
++gckHARDWARE_SetPowerOffTimeout(
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 Timeout
++);
++
++gceSTATUS
++gckHARDWARE_QueryPowerOffTimeout(
++ IN gckHARDWARE Hardware,
++ OUT gctUINT32* Timeout
++);
++#endif
++
++/* Profile 2D Engine. */
++gceSTATUS
++gckHARDWARE_ProfileEngine2D(
++ IN gckHARDWARE Hardware,
++ OUT gcs2D_PROFILE_PTR Profile
++ );
++
++gceSTATUS
++gckHARDWARE_InitializeHardware(
++ IN gckHARDWARE Hardware
++ );
++
++gceSTATUS
++gckHARDWARE_Reset(
++ IN gckHARDWARE Hardware
++ );
++
++typedef gceSTATUS (*gctISRMANAGERFUNC)(gctPOINTER Context, gceCORE Core);
++
++gceSTATUS
++gckHARDWARE_SetIsrManager(
++ IN gckHARDWARE Hardware,
++ IN gctISRMANAGERFUNC StartIsr,
++ IN gctISRMANAGERFUNC StopIsr,
++ IN gctPOINTER Context
++ );
++
++/* Start a composition. */
++gceSTATUS
++gckHARDWARE_Compose(
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 ProcessID,
++ IN gctPHYS_ADDR Physical,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Offset,
++ IN gctSIZE_T Size,
++ IN gctUINT8 EventID
++ );
++
++/* Check for Hardware features. */
++gceSTATUS
++gckHARDWARE_IsFeatureAvailable(
++ IN gckHARDWARE Hardware,
++ IN gceFEATURE Feature
++ );
++
++gceSTATUS
++gckHARDWARE_DumpMMUException(
++ IN gckHARDWARE Hardware
++ );
++
++gceSTATUS
++gckHARDWARE_DumpGPUState(
++ IN gckHARDWARE Hardware
++ );
++
++gceSTATUS
++gckHARDWARE_InitDVFS(
++ IN gckHARDWARE Hardware
++ );
++
++gceSTATUS
++gckHARDWARE_QueryLoad(
++ IN gckHARDWARE Hardware,
++ OUT gctUINT32 * Load
++ );
++
++gceSTATUS
++gckHARDWARE_SetDVFSPeroid(
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 Frequency
++ );
++
++#if !gcdENABLE_VG
++/******************************************************************************\
++***************************** gckINTERRUPT Object ******************************
++\******************************************************************************/
++
++typedef struct _gckINTERRUPT * gckINTERRUPT;
++
++typedef gceSTATUS (* gctINTERRUPT_HANDLER)(
++ IN gckKERNEL Kernel
++ );
++
++gceSTATUS
++gckINTERRUPT_Construct(
++ IN gckKERNEL Kernel,
++ OUT gckINTERRUPT * Interrupt
++ );
++
++gceSTATUS
++gckINTERRUPT_Destroy(
++ IN gckINTERRUPT Interrupt
++ );
++
++gceSTATUS
++gckINTERRUPT_SetHandler(
++ IN gckINTERRUPT Interrupt,
++ IN OUT gctINT32_PTR Id,
++ IN gctINTERRUPT_HANDLER Handler
++ );
++
++gceSTATUS
++gckINTERRUPT_Notify(
++ IN gckINTERRUPT Interrupt,
++ IN gctBOOL Valid
++ );
++#endif
++/******************************************************************************\
++******************************** gckEVENT Object *******************************
++\******************************************************************************/
++
++typedef struct _gckEVENT * gckEVENT;
++
++/* Construct a new gckEVENT object. */
++gceSTATUS
++gckEVENT_Construct(
++ IN gckKERNEL Kernel,
++ OUT gckEVENT * Event
++ );
++
++/* Destroy an gckEVENT object. */
++gceSTATUS
++gckEVENT_Destroy(
++ IN gckEVENT Event
++ );
++
++/* Add a new event to the list of events. */
++gceSTATUS
++gckEVENT_AddList(
++ IN gckEVENT Event,
++ IN gcsHAL_INTERFACE_PTR Interface,
++ IN gceKERNEL_WHERE FromWhere,
++ IN gctBOOL AllocateAllowed,
++ IN gctBOOL FromKernel
++ );
++
++/* Schedule a FreeNonPagedMemory event. */
++gceSTATUS
++gckEVENT_FreeNonPagedMemory(
++ IN gckEVENT Event,
++ IN gctSIZE_T Bytes,
++ IN gctPHYS_ADDR Physical,
++ IN gctPOINTER Logical,
++ IN gceKERNEL_WHERE FromWhere
++ );
++
++/* Schedule a FreeContiguousMemory event. */
++gceSTATUS
++gckEVENT_FreeContiguousMemory(
++ IN gckEVENT Event,
++ IN gctSIZE_T Bytes,
++ IN gctPHYS_ADDR Physical,
++ IN gctPOINTER Logical,
++ IN gceKERNEL_WHERE FromWhere
++ );
++
++/* Schedule a FreeVideoMemory event. */
++gceSTATUS
++gckEVENT_FreeVideoMemory(
++ IN gckEVENT Event,
++ IN gcuVIDMEM_NODE_PTR VideoMemory,
++ IN gceKERNEL_WHERE FromWhere
++ );
++
++/* Schedule a signal event. */
++gceSTATUS
++gckEVENT_Signal(
++ IN gckEVENT Event,
++ IN gctSIGNAL Signal,
++ IN gceKERNEL_WHERE FromWhere
++ );
++
++/* Schedule an Unlock event. */
++gceSTATUS
++gckEVENT_Unlock(
++ IN gckEVENT Event,
++ IN gceKERNEL_WHERE FromWhere,
++ IN gcuVIDMEM_NODE_PTR Node,
++ IN gceSURF_TYPE Type
++ );
++
++gceSTATUS
++gckEVENT_CommitDone(
++ IN gckEVENT Event,
++ IN gceKERNEL_WHERE FromWhere
++ );
++
++#if gcdVIRTUAL_COMMAND_BUFFER
++/* Schedule a FreeVirtualCommandBuffer event. */
++gceSTATUS
++gckEVENT_DestroyVirtualCommandBuffer(
++ IN gckEVENT Event,
++ IN gctSIZE_T Bytes,
++ IN gctPHYS_ADDR Physical,
++ IN gctPOINTER Logical,
++ IN gceKERNEL_WHERE FromWhere
++ );
++#endif
++
++gceSTATUS
++gckEVENT_Submit(
++ IN gckEVENT Event,
++ IN gctBOOL Wait,
++ IN gctBOOL FromPower
++ );
++
++/* Commit an event queue. */
++gceSTATUS
++gckEVENT_Commit(
++ IN gckEVENT Event,
++ IN gcsQUEUE_PTR Queue
++ );
++
++/* Schedule a composition event. */
++gceSTATUS
++gckEVENT_Compose(
++ IN gckEVENT Event,
++ IN gcsHAL_COMPOSE_PTR Info
++ );
++
++/* Event callback routine. */
++gceSTATUS
++gckEVENT_Notify(
++ IN gckEVENT Event,
++ IN gctUINT32 IDs
++ );
++
++/* Event callback routine. */
++gceSTATUS
++gckEVENT_Interrupt(
++ IN gckEVENT Event,
++ IN gctUINT32 IDs
++ );
++
++gceSTATUS
++gckEVENT_Dump(
++ IN gckEVENT Event
++ );
++/******************************************************************************\
++******************************* gckCOMMAND Object ******************************
++\******************************************************************************/
++
++typedef struct _gckCOMMAND * gckCOMMAND;
++
++/* Construct a new gckCOMMAND object. */
++gceSTATUS
++gckCOMMAND_Construct(
++ IN gckKERNEL Kernel,
++ OUT gckCOMMAND * Command
++ );
++
++/* Destroy an gckCOMMAND object. */
++gceSTATUS
++gckCOMMAND_Destroy(
++ IN gckCOMMAND Command
++ );
++
++/* Acquire command queue synchronization objects. */
++gceSTATUS
++gckCOMMAND_EnterCommit(
++ IN gckCOMMAND Command,
++ IN gctBOOL FromPower
++ );
++
++/* Release command queue synchronization objects. */
++gceSTATUS
++gckCOMMAND_ExitCommit(
++ IN gckCOMMAND Command,
++ IN gctBOOL FromPower
++ );
++
++/* Start the command queue. */
++gceSTATUS
++gckCOMMAND_Start(
++ IN gckCOMMAND Command
++ );
++
++/* Stop the command queue. */
++gceSTATUS
++gckCOMMAND_Stop(
++ IN gckCOMMAND Command,
++ IN gctBOOL FromRecovery
++ );
++
++/* Commit a buffer to the command queue. */
++gceSTATUS
++gckCOMMAND_Commit(
++ IN gckCOMMAND Command,
++ IN gckCONTEXT Context,
++ IN gcoCMDBUF CommandBuffer,
++ IN gcsSTATE_DELTA_PTR StateDelta,
++ IN gcsQUEUE_PTR EventQueue,
++ IN gctUINT32 ProcessID
++ );
++
++/* Reserve space in the command buffer. */
++gceSTATUS
++gckCOMMAND_Reserve(
++ IN gckCOMMAND Command,
++ IN gctSIZE_T RequestedBytes,
++ OUT gctPOINTER * Buffer,
++ OUT gctSIZE_T * BufferSize
++ );
++
++/* Execute reserved space in the command buffer. */
++gceSTATUS
++gckCOMMAND_Execute(
++ IN gckCOMMAND Command,
++ IN gctSIZE_T RequstedBytes
++ );
++
++/* Stall the command queue. */
++gceSTATUS
++gckCOMMAND_Stall(
++ IN gckCOMMAND Command,
++ IN gctBOOL FromPower
++ );
++
++/* Attach user process. */
++gceSTATUS
++gckCOMMAND_Attach(
++ IN gckCOMMAND Command,
++ OUT gckCONTEXT * Context,
++ OUT gctSIZE_T * StateCount,
++ IN gctUINT32 ProcessID
++ );
++
++/* Detach user process. */
++gceSTATUS
++gckCOMMAND_Detach(
++ IN gckCOMMAND Command,
++ IN gckCONTEXT Context
++ );
++
++#if gcdVIRTUAL_COMMAND_BUFFER
++gceSTATUS
++gckCOMMAND_DumpExecutingBuffer(
++ IN gckCOMMAND Command
++ );
++#endif
++
++/******************************************************************************\
++********************************* gckMMU Object ********************************
++\******************************************************************************/
++
++typedef struct _gckMMU * gckMMU;
++
++/* Construct a new gckMMU object. */
++gceSTATUS
++gckMMU_Construct(
++ IN gckKERNEL Kernel,
++ IN gctSIZE_T MmuSize,
++ OUT gckMMU * Mmu
++ );
++
++/* Destroy an gckMMU object. */
++gceSTATUS
++gckMMU_Destroy(
++ IN gckMMU Mmu
++ );
++
++/* Enable the MMU. */
++gceSTATUS
++gckMMU_Enable(
++ IN gckMMU Mmu,
++ IN gctUINT32 PhysBaseAddr,
++ IN gctUINT32 PhysSize
++ );
++
++/* Allocate pages inside the MMU. */
++gceSTATUS
++gckMMU_AllocatePages(
++ IN gckMMU Mmu,
++ IN gctSIZE_T PageCount,
++ OUT gctPOINTER * PageTable,
++ OUT gctUINT32 * Address
++ );
++
++gceSTATUS
++gckMMU_AllocatePagesEx(
++ IN gckMMU Mmu,
++ IN gctSIZE_T PageCount,
++ IN gceSURF_TYPE Type,
++ OUT gctPOINTER * PageTable,
++ OUT gctUINT32 * Address
++ );
++
++/* Remove a page table from the MMU. */
++gceSTATUS
++gckMMU_FreePages(
++ IN gckMMU Mmu,
++ IN gctPOINTER PageTable,
++ IN gctSIZE_T PageCount
++ );
++
++/* Set the MMU page with info. */
++gceSTATUS
++gckMMU_SetPage(
++ IN gckMMU Mmu,
++ IN gctUINT32 PageAddress,
++ IN gctUINT32 *PageEntry
++ );
++
++#ifdef __QNXNTO__
++gceSTATUS
++gckMMU_InsertNode(
++ IN gckMMU Mmu,
++ IN gcuVIDMEM_NODE_PTR Node);
++
++gceSTATUS
++gckMMU_RemoveNode(
++ IN gckMMU Mmu,
++ IN gcuVIDMEM_NODE_PTR Node);
++#endif
++
++#ifdef __QNXNTO__
++gceSTATUS
++gckMMU_FreeHandleMemory(
++ IN gckKERNEL Kernel,
++ IN gckMMU Mmu,
++ IN gctUINT32 Pid
++ );
++#endif
++
++gceSTATUS
++gckMMU_Flush(
++ IN gckMMU Mmu
++ );
++
++gceSTATUS
++gckMMU_DumpPageTableEntry(
++ IN gckMMU Mmu,
++ IN gctUINT32 Address
++ );
++
++
++#if VIVANTE_PROFILER
++gceSTATUS
++gckHARDWARE_QueryProfileRegisters(
++ IN gckHARDWARE Hardware,
++ IN gctBOOL Clear,
++ OUT gcsPROFILER_COUNTERS * Counters
++ );
++#endif
++
++#if VIVANTE_PROFILER_CONTEXT
++gceSTATUS
++gckHARDWARE_QueryContextProfile(
++ IN gckHARDWARE Hardware,
++ IN gctBOOL Clear,
++ IN gckCONTEXT Context,
++ OUT gcsPROFILER_COUNTERS * Counters
++ );
++
++gceSTATUS
++gckHARDWARE_UpdateContextProfile(
++ IN gckHARDWARE Hardware,
++ IN gckCONTEXT Context
++ );
++#endif
++
++gceSTATUS
++gckOS_SignalQueryHardware(
++ IN gckOS Os,
++ IN gctSIGNAL Signal,
++ OUT gckHARDWARE * Hardware
++ );
++
++gceSTATUS
++gckOS_SignalSetHardware(
++ IN gckOS Os,
++ IN gctSIGNAL Signal,
++ gckHARDWARE Hardware
++ );
++
++#ifdef __cplusplus
++}
++#endif
++
++#if gcdENABLE_VG
++#include "gc_hal_vg.h"
++#endif
++
++#endif /* __gc_hal_h_ */
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_kernel_buffer.h linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_kernel_buffer.h
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_kernel_buffer.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_kernel_buffer.h 2015-07-27 23:13:06.214808565 +0200
+@@ -0,0 +1,185 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_kernel_buffer_h_
++#define __gc_hal_kernel_buffer_h_
++
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/******************************************************************************\
++************************ Command Buffer and Event Objects **********************
++\******************************************************************************/
++
++/* The number of context buffers per user. */
++#define gcdCONTEXT_BUFFER_COUNT 2
++
++/* State delta record. */
++typedef struct _gcsSTATE_DELTA_RECORD * gcsSTATE_DELTA_RECORD_PTR;
++typedef struct _gcsSTATE_DELTA_RECORD
++{
++ /* State address. */
++ gctUINT address;
++
++ /* State mask. */
++ gctUINT32 mask;
++
++ /* State data. */
++ gctUINT32 data;
++}
++gcsSTATE_DELTA_RECORD;
++
++/* State delta. */
++typedef struct _gcsSTATE_DELTA
++{
++ /* For debugging: the number of delta in the order of creation. */
++#if gcmIS_DEBUG(gcdDEBUG_CODE)
++ gctUINT num;
++#endif
++
++ /* Main state delta ID. Every time state delta structure gets reinitialized,
++ main ID is incremented. If main state ID overflows, all map entry IDs get
++ reinitialized to make sure there is no potential erroneous match after
++ the overflow.*/
++ gctUINT id;
++
++ /* The number of contexts pending modification by the delta. */
++ gctINT refCount;
++
++ /* Vertex element count for the delta buffer. */
++ gctUINT elementCount;
++
++ /* Number of states currently stored in the record array. */
++ gctUINT recordCount;
++
++ /* Record array; holds all modified states in gcsSTATE_DELTA_RECORD. */
++ gctUINT64 recordArray;
++
++ /* Map entry ID is used for map entry validation. If map entry ID does not
++ match the main state delta ID, the entry and the corresponding state are
++ considered not in use. */
++ gctUINT64 mapEntryID;
++ gctUINT mapEntryIDSize;
++
++ /* If the map entry ID matches the main state delta ID, index points to
++ the state record in the record array. */
++ gctUINT64 mapEntryIndex;
++
++ /* Previous and next state deltas in gcsSTATE_DELTA. */
++ gctUINT64 prev;
++ gctUINT64 next;
++}
++gcsSTATE_DELTA;
++
++/* Command buffer object. */
++struct _gcoCMDBUF
++{
++ /* The object. */
++ gcsOBJECT object;
++
++ /* Command buffer entry and exit pipes. */
++ gcePIPE_SELECT entryPipe;
++ gcePIPE_SELECT exitPipe;
++
++ /* Feature usage flags. */
++ gctBOOL using2D;
++ gctBOOL using3D;
++ gctBOOL usingFilterBlit;
++ gctBOOL usingPalette;
++
++ /* Physical address of command buffer. Just a name. */
++ gctUINT32 physical;
++
++ /* Logical address of command buffer. */
++ gctUINT64 logical;
++
++ /* Number of bytes in command buffer. */
++ gctUINT bytes;
++
++ /* Start offset into the command buffer. */
++ gctUINT startOffset;
++
++ /* Current offset into the command buffer. */
++ gctUINT offset;
++
++ /* Number of free bytes in command buffer. */
++ gctUINT free;
++
++ /* Location of the last reserved area. */
++ gctUINT64 lastReserve;
++ gctUINT lastOffset;
++
++#if gcdSECURE_USER
++ /* Hint array for the current command buffer. */
++ gctUINT hintArraySize;
++ gctUINT64 hintArray;
++ gctUINT64 hintArrayTail;
++#endif
++
++#if gcmIS_DEBUG(gcdDEBUG_CODE)
++ /* Last load state command location and hardware address. */
++ gctUINT64 lastLoadStatePtr;
++ gctUINT32 lastLoadStateAddress;
++ gctUINT32 lastLoadStateCount;
++#endif
++};
++
++typedef struct _gcsQUEUE
++{
++ /* Pointer to next gcsQUEUE structure in gcsQUEUE. */
++ gctUINT64 next;
++
++ /* Event information. */
++ gcsHAL_INTERFACE iface;
++}
++gcsQUEUE;
++
++/* Event queue. */
++struct _gcoQUEUE
++{
++ /* The object. */
++ gcsOBJECT object;
++
++ /* Pointer to current event queue. */
++ gcsQUEUE_PTR head;
++ gcsQUEUE_PTR tail;
++
++#ifdef __QNXNTO__
++ /* Buffer for records. */
++ gcsQUEUE_PTR records;
++ gctUINT32 freeBytes;
++ gctUINT32 offset;
++#else
++ /* List of free records. */
++ gcsQUEUE_PTR freeList;
++#endif
++ #define gcdIN_QUEUE_RECORD_LIMIT 16
++ /* Number of records currently in queue */
++ gctUINT32 recordCount;
++};
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __gc_hal_kernel_buffer_h_ */
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_mem.h linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_mem.h
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_mem.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_mem.h 2015-07-27 23:13:06.214808565 +0200
+@@ -0,0 +1,530 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++/*
++** Include file for the local memory management.
++*/
++
++#ifndef __gc_hal_mem_h_
++#define __gc_hal_mem_h_
++#ifndef VIVANTE_NO_3D
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/*******************************************************************************
++** Usage:
++
++ The macros to declare MemPool type and functions are
++ gcmMEM_DeclareFSMemPool (Type, TypeName, Prefix)
++ gcmMEM_DeclareVSMemPool (Type, TypeName, Prefix)
++ gcmMEM_DeclareAFSMemPool(Type, TypeName, Prefix)
++
++ The data structures for MemPool are
++ typedef struct _gcsMEM_FS_MEM_POOL * gcsMEM_FS_MEM_POOL;
++ typedef struct _gcsMEM_VS_MEM_POOL * gcsMEM_VS_MEM_POOL;
++ typedef struct _gcsMEM_AFS_MEM_POOL * gcsMEM_AFS_MEM_POOL;
++
++ The MemPool constructor and destructor functions are
++ gcfMEM_InitFSMemPool(gcsMEM_FS_MEM_POOL *, gcoOS, gctUINT, gctUINT);
++ gcfMEM_FreeFSMemPool(gcsMEM_FS_MEM_POOL *);
++ gcfMEM_InitVSMemPool(gcsMEM_VS_MEM_POOL *, gcoOS, gctUINT, gctBOOL);
++ gcfMEM_FreeVSMemPool(gcsMEM_VS_MEM_POOL *);
++ gcfMEM_InitAFSMemPool(gcsMEM_AFS_MEM_POOL *, gcoOS, gctUINT);
++ gcfMEM_FreeAFSMemPool(gcsMEM_AFS_MEM_POOL *);
++
++ FS: for Fixed-Size data structures
++ VS: for Variable-size data structures
++ AFS: for Array of Fixed-Size data structures
++
++
++ // Example 1: For a fixed-size data structure, struct gcsNode.
++ // It is used locally in a file, so the functions are static without prefix.
++ // At top level, declear allocate and free functions.
++ // The first argument is the data type.
++ // The second armument is the short name used in the fuctions.
++ gcmMEM_DeclareFSMemPool(struct gcsNode, Node, );
++
++ // The previous macro creates two inline functions,
++ // _AllocateNode and _FreeNode.
++
++ // In function or struct
++ gcsMEM_FS_MEM_POOL nodeMemPool;
++
++ // In function,
++ struct gcsNode * node;
++ gceSTATUS status;
++
++ // Before using the memory pool, initialize it.
++ // The second argument is the gcoOS object.
++ // The third argument is the number of data structures to allocate for each chunk.
++ status = gcfMEM_InitFSMemPool(&nodeMemPool, os, 100, sizeof(struct gcsNode));
++ ...
++
++ // Allocate a node.
++ status = _AllocateNode(nodeMemPool, &node);
++ ...
++ // Free a node.
++ _FreeNode(nodeMemPool, node);
++
++ // After using the memory pool, free it.
++ gcfMEM_FreeFSMemPool(&nodeMemPool);
++
++
++ // Example 2: For array of fixed-size data structures, struct gcsNode.
++ // It is used in several files, so the functions are extern with prefix.
++ // At top level, declear allocate and free functions.
++ // The first argument is the data type, and the second one is the short name
++ // used in the fuctions.
++ gcmMEM_DeclareAFSMemPool(struct gcsNode, NodeArray, gcfOpt);
++
++ // The previous macro creates two inline functions,
++ // gcfOpt_AllocateNodeArray and gcfOpt_FreeNodeArray.
++
++ // In function or struct
++ gcsMEM_AFS_MEM_POOL nodeArrayMemPool;
++
++ // In function,
++ struct gcsNode * nodeArray;
++ gceSTATUS status;
++
++ // Before using the array memory pool, initialize it.
++ // The second argument is the gcoOS object, the third is the number of data
++ // structures to allocate for each chunk.
++ status = gcfMEM_InitAFSMemPool(&nodeArrayMemPool, os, sizeof(struct gcsNode));
++ ...
++
++ // Allocate a node array of size 100.
++ status = gcfOpt_AllocateNodeArray(nodeArrayMemPool, &nodeArray, 100);
++ ...
++ // Free a node array.
++ gcfOpt_FreeNodeArray(&nodeArrayMemPool, nodeArray);
++
++ // After using the array memory pool, free it.
++ gcfMEM_FreeAFSMemPool(&nodeArrayMemPool);
++
++*******************************************************************************/
++
++/*******************************************************************************
++** To switch back to use gcoOS_Allocate and gcoOS_Free, add
++** #define USE_LOCAL_MEMORY_POOL 0
++** before including this file.
++*******************************************************************************/
++#ifndef USE_LOCAL_MEMORY_POOL
++/*
++ USE_LOCAL_MEMORY_POOL
++
++ This define enables the local memory management to improve performance.
++*/
++#define USE_LOCAL_MEMORY_POOL 1
++#endif
++
++/*******************************************************************************
++** Memory Pool Data Structures
++*******************************************************************************/
++#if USE_LOCAL_MEMORY_POOL
++ typedef struct _gcsMEM_FS_MEM_POOL * gcsMEM_FS_MEM_POOL;
++ typedef struct _gcsMEM_VS_MEM_POOL * gcsMEM_VS_MEM_POOL;
++ typedef struct _gcsMEM_AFS_MEM_POOL * gcsMEM_AFS_MEM_POOL;
++#else
++ typedef gcoOS gcsMEM_FS_MEM_POOL;
++ typedef gcoOS gcsMEM_VS_MEM_POOL;
++ typedef gcoOS gcsMEM_AFS_MEM_POOL;
++#endif
++
++/*******************************************************************************
++** Memory Pool Macros
++*******************************************************************************/
++#if USE_LOCAL_MEMORY_POOL
++#define gcmMEM_DeclareFSMemPool(Type, TypeName, Prefix) \
++gceSTATUS \
++Prefix##_Allocate##TypeName( \
++ gcsMEM_FS_MEM_POOL MemPool, \
++ Type ** Pointer \
++ ) \
++{ \
++ return(gcfMEM_FSMemPoolGetANode(MemPool, (gctPOINTER *) Pointer)); \
++} \
++ \
++gceSTATUS \
++Prefix##_CAllocate##TypeName( \
++ gcsMEM_FS_MEM_POOL MemPool, \
++ Type ** Pointer \
++ ) \
++{ \
++ gceSTATUS status; \
++ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x", MemPool, Pointer); \
++ gcmERR_RETURN(gcfMEM_FSMemPoolGetANode(MemPool, (gctPOINTER *) Pointer)); \
++ gcoOS_ZeroMemory(*(gctPOINTER *) Pointer, gcmSIZEOF(Type)); \
++ gcmFOOTER(); \
++ return gcvSTATUS_OK; \
++} \
++ \
++gceSTATUS \
++Prefix##_Free##TypeName( \
++ gcsMEM_FS_MEM_POOL MemPool, \
++ Type * Pointer \
++ ) \
++{ \
++ gceSTATUS status; \
++ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x", MemPool, Pointer); \
++ status = gcfMEM_FSMemPoolFreeANode(MemPool, (gctPOINTER) Pointer); \
++ gcmFOOTER(); \
++ return status; \
++} \
++ \
++gceSTATUS \
++Prefix##_Free##TypeName##List( \
++ gcsMEM_FS_MEM_POOL MemPool, \
++ Type * FirstPointer, \
++ Type * LastPointer \
++ ) \
++{ \
++ gceSTATUS status; \
++ gcmHEADER_ARG("MemPool=0x%x FirstPointer=0x%x LastPointer=0x%x", MemPool, FirstPointer, LastPointer); \
++ status = gcfMEM_FSMemPoolFreeAList(MemPool, (gctPOINTER) FirstPointer, (gctPOINTER) LastPointer); \
++ gcmFOOTER(); \
++ return status; \
++}
++
++#define gcmMEM_DeclareVSMemPool(Type, TypeName, Prefix) \
++gceSTATUS \
++Prefix##_Allocate##TypeName( \
++ gcsMEM_FS_MEM_POOL MemPool, \
++ Type ** Pointer, \
++ gctUINT Size \
++ ) \
++{ \
++ gceSTATUS status;\
++ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x Size=%u", MemPool, Pointer, Size); \
++ status = gcfMEM_VSMemPoolGetANode(MemPool, Size, (gctPOINTER *) Pointer); \
++ gcmFOOTER(); \
++ return status; \
++} \
++ \
++gceSTATUS \
++ Prefix##_CAllocate##TypeName( \
++ gcsMEM_FS_MEM_POOL MemPool, \
++ Type ** Pointer, \
++ gctUINT Size \
++ ) \
++{ \
++ gceSTATUS status; \
++ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x Size=%u", MemPool, Pointer, Size); \
++ gcmERR_RETURN(gcfMEM_VSMemPoolGetANode(MemPool, Size, (gctPOINTER *) Pointer)); \
++ gcoOS_ZeroMemory(*(gctPOINTER *) Pointer, size); \
++ gcmFOOTER(); \
++ return gcvSTATUS_OK; \
++} \
++ \
++gceSTATUS \
++Prefix##_Free##TypeName( \
++ gcsMEM_FS_MEM_POOL MemPool, \
++ Type * Pointer \
++ ) \
++{ \
++ gceSTATUS status; \
++ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x", MemPool, Pinter); \
++ status = gcfMEM_VSMemPoolFreeANode(MemPool, (gctPOINTER) Pointer); \
++ gcmFOOTER(); \
++ return status; \
++}
++
++#define gcmMEM_DeclareAFSMemPool(Type, TypeName, Prefix) \
++gceSTATUS \
++Prefix##_Allocate##TypeName( \
++ gcsMEM_AFS_MEM_POOL MemPool, \
++ Type ** Pointer, \
++ gctUINT Count \
++ ) \
++{ \
++ gceSTATUS status; \
++ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x Count=%u", MemPool, Pointer, Count); \
++ status = gcfMEM_AFSMemPoolGetANode(MemPool, Count, (gctPOINTER *) Pointer); \
++ gcmFOOTER(); \
++ return status; \
++} \
++ \
++gceSTATUS \
++Prefix##_CAllocate##TypeName( \
++ gcsMEM_AFS_MEM_POOL MemPool, \
++ Type ** Pointer, \
++ gctUINT Count \
++ ) \
++{ \
++ gceSTATUS status; \
++ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x Count=%u", MemPool, Pointer, Count); \
++ gcmERR_RETURN(gcfMEM_AFSMemPoolGetANode(MemPool, Count, (gctPOINTER *) Pointer)); \
++ gcoOS_ZeroMemory(*(gctPOINTER *) Pointer, Count * gcmSIZEOF(Type)); \
++ gcmFOOTER(); \
++ return gcvSTATUS_OK; \
++} \
++ \
++gceSTATUS \
++Prefix##_Free##TypeName( \
++ gcsMEM_AFS_MEM_POOL MemPool, \
++ Type * Pointer \
++ ) \
++{ \
++ gceSTATUS status; \
++ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x", MemPool, Pointer); \
++ status = gcfMEM_AFSMemPoolFreeANode(MemPool, (gctPOINTER) Pointer); \
++ gcmFOOTER(); \
++ return status; \
++}
++
++#else
++
++#define gcmMEM_DeclareFSMemPool(Type, TypeName, Prefix) \
++gceSTATUS \
++Prefix##_Allocate##TypeName( \
++ gcsMEM_FS_MEM_POOL MemPool, \
++ Type ** Pointer \
++ ) \
++{ \
++ gceSTATUS status; \
++ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x", MemPool, Pointer); \
++ status = gcoOS_Allocate(MemPool, \
++ gcmSIZEOF(Type), \
++ (gctPOINTER *) Pointer); \
++ gcmFOOTER(); \
++ return status; \
++} \
++ \
++gceSTATUS \
++Prefix##_CAllocate##TypeName( \
++ gcsMEM_FS_MEM_POOL MemPool, \
++ Type ** Pointer \
++ ) \
++{ \
++ gceSTATUS status; \
++ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x", MemPool, Pointer); \
++ gcmERR_RETURN(gcoOS_Allocate(MemPool, \
++ gcmSIZEOF(Type), \
++ (gctPOINTER *) Pointer)); \
++ gcoOS_ZeroMemory(*(gctPOINTER *) Pointer, gcmSIZEOF(Type)); \
++ gcmFOOTER(); \
++ return gcvSTATUS_OK; \
++} \
++ \
++gceSTATUS \
++Prefix##_Free##TypeName( \
++ gcsMEM_FS_MEM_POOL MemPool, \
++ Type * Pointer \
++ ) \
++{ \
++ gceSTATUS status; \
++ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x", MemPool, Pointer); \
++ status = gcmOS_SAFE_FREE(MemPool, Pointer); \
++ gcmFOOTER(); \
++ return status; \
++}
++
++#define gcmMEM_DeclareVSMemPool(Type, TypeName, Prefix) \
++gceSTATUS \
++Prefix##_Allocate##TypeName( \
++ gcsMEM_VS_MEM_POOL MemPool, \
++ Type ** Pointer, \
++ gctUINT Size \
++ ) \
++{ \
++ gceSTATUS status; \
++ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x Size=%u", MemPool, Pointer, Size); \
++ status = gcoOS_Allocate(MemPool, \
++ Size, \
++ (gctPOINTER *) Pointer); \
++ gcmFOOTER(); \
++ return status; \
++} \
++ \
++gceSTATUS \
++Prefix##_CAllocate##TypeName( \
++ gcsMEM_VS_MEM_POOL MemPool, \
++ Type ** Pointer, \
++ gctUINT Size \
++ ) \
++{ \
++ gceSTATUS status; \
++ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x Size=%u", MemPool, Pointer, Size); \
++ gcmERR_RETURN(gcoOS_Allocate(MemPool, \
++ Size, \
++ (gctPOINTER *) Pointer)); \
++ gcoOS_ZeroMemory(*(gctPOINTER *) Pointer, Size); \
++ gcmFOOTER(); \
++ return gcvSTATUS_OK; \
++} \
++ \
++gceSTATUS \
++Prefix##_Free##TypeName( \
++ gcsMEM_VS_MEM_POOL MemPool, \
++ Type * Pointer \
++ ) \
++{ \
++ gceSTATUS status; \
++ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x", MemPool, Pointer); \
++ status = gcmOS_SAFE_FREE(MemPool, Pointer); \
++ gcmFOOTER(); \
++ return status; \
++}
++
++#define gcmMEM_DeclareAFSMemPool(Type, TypeName, Prefix) \
++gceSTATUS \
++Prefix##_Allocate##TypeName( \
++ gcsMEM_AFS_MEM_POOL MemPool, \
++ Type ** Pointer, \
++ gctUINT Count \
++ ) \
++{ \
++ gceSTATUS status; \
++ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x Count=%u", MemPool, Pointer, Count); \
++ status = gcoOS_Allocate(MemPool, \
++ Count * gcmSIZEOF(Type), \
++ (gctPOINTER *) Pointer); \
++ gcmFOOTER(); \
++ return status; \
++} \
++ \
++gceSTATUS \
++Prefix##_CAllocate##TypeName( \
++ gcsMEM_AFS_MEM_POOL MemPool, \
++ Type ** Pointer, \
++ gctUINT Count \
++ ) \
++{ \
++ gceSTATUS status; \
++ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x Count=%u", MemPool, Pointer, Count); \
++ gcmERR_RETURN(gcoOS_Allocate(MemPool, \
++ Count * gcmSIZEOF(Type), \
++ (gctPOINTER *) Pointer)); \
++ gcoOS_ZeroMemory(*(gctPOINTER *) Pointer, Count * gcmSIZEOF(Type)); \
++ gcmFOOTER(); \
++ return gcvSTATUS_OK; \
++} \
++ \
++gceSTATUS \
++Prefix##_Free##TypeName( \
++ gcsMEM_AFS_MEM_POOL MemPool, \
++ Type * Pointer \
++ ) \
++{ \
++ gceSTATUS status; \
++ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x", MemPool, Pointer); \
++ status = gcmOS_SAFE_FREE(MemPool, Pointer); \
++ gcmFOOTER(); \
++ return status; \
++}
++#endif
++
++/*******************************************************************************
++** Memory Pool Data Functions
++*******************************************************************************/
++gceSTATUS
++gcfMEM_InitFSMemPool(
++ IN gcsMEM_FS_MEM_POOL * MemPool,
++ IN gcoOS OS,
++ IN gctUINT NodeCount,
++ IN gctUINT NodeSize
++ );
++
++gceSTATUS
++gcfMEM_FreeFSMemPool(
++ IN gcsMEM_FS_MEM_POOL * MemPool
++ );
++
++gceSTATUS
++gcfMEM_FSMemPoolGetANode(
++ IN gcsMEM_FS_MEM_POOL MemPool,
++ OUT gctPOINTER * Node
++ );
++
++gceSTATUS
++gcfMEM_FSMemPoolFreeANode(
++ IN gcsMEM_FS_MEM_POOL MemPool,
++ IN gctPOINTER Node
++ );
++
++gceSTATUS
++gcfMEM_FSMemPoolFreeAList(
++ IN gcsMEM_FS_MEM_POOL MemPool,
++ IN gctPOINTER FirstNode,
++ IN gctPOINTER LastNode
++ );
++
++gceSTATUS
++gcfMEM_InitVSMemPool(
++ IN gcsMEM_VS_MEM_POOL * MemPool,
++ IN gcoOS OS,
++ IN gctUINT BlockSize,
++ IN gctBOOL RecycleFreeNode
++ );
++
++gceSTATUS
++gcfMEM_FreeVSMemPool(
++ IN gcsMEM_VS_MEM_POOL * MemPool
++ );
++
++gceSTATUS
++gcfMEM_VSMemPoolGetANode(
++ IN gcsMEM_VS_MEM_POOL MemPool,
++ IN gctUINT Size,
++ IN gctUINT Alignment,
++ OUT gctPOINTER * Node
++ );
++
++gceSTATUS
++gcfMEM_VSMemPoolFreeANode(
++ IN gcsMEM_VS_MEM_POOL MemPool,
++ IN gctPOINTER Node
++ );
++
++gceSTATUS
++gcfMEM_InitAFSMemPool(
++ IN gcsMEM_AFS_MEM_POOL *MemPool,
++ IN gcoOS OS,
++ IN gctUINT NodeCount,
++ IN gctUINT NodeSize
++ );
++
++gceSTATUS
++gcfMEM_FreeAFSMemPool(
++ IN gcsMEM_AFS_MEM_POOL *MemPool
++ );
++
++gceSTATUS
++gcfMEM_AFSMemPoolGetANode(
++ IN gcsMEM_AFS_MEM_POOL MemPool,
++ IN gctUINT Count,
++ OUT gctPOINTER * Node
++ );
++
++gceSTATUS
++gcfMEM_AFSMemPoolFreeANode(
++ IN gcsMEM_AFS_MEM_POOL MemPool,
++ IN gctPOINTER Node
++ );
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* VIVANTE_NO_3D */
++#endif /* __gc_hal_mem_h_ */
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_options.h linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_options.h
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_options.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_options.h 2015-07-27 23:13:06.214808565 +0200
+@@ -0,0 +1,947 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_options_h_
++#define __gc_hal_options_h_
++
++/*
++ gcdPRINT_VERSION
++
++ Print HAL version.
++*/
++#ifndef gcdPRINT_VERSION
++# define gcdPRINT_VERSION 0
++#endif
++
++/*
++ USE_NEW_LINUX_SIGNAL
++
++ This define enables the Linux kernel signaling between kernel and user.
++*/
++#ifndef USE_NEW_LINUX_SIGNAL
++# define USE_NEW_LINUX_SIGNAL 0
++#endif
++
++/*
++ VIVANTE_PROFILER
++
++ This define enables the profiler.
++*/
++#ifndef VIVANTE_PROFILER
++# define VIVANTE_PROFILER 1
++#endif
++
++#ifndef VIVANTE_PROFILER_PERDRAW
++# define VIVANTE_PROFILER_PERDRAW 0
++#endif
++
++/*
++ VIVANTE_PROFILER_CONTEXT
++
++ This define enables the profiler according to each hw context.
++*/
++#ifndef VIVANTE_PROFILER_CONTEXT
++# define VIVANTE_PROFILER_CONTEXT 1
++#endif
++
++/*
++ gcdUSE_VG
++
++ Enable VG HAL layer (only for GC350).
++*/
++#ifndef gcdUSE_VG
++# define gcdUSE_VG 0
++#endif
++
++/*
++ USE_SW_FB
++
++ Set to 1 if the frame buffer memory cannot be accessed by the GPU.
++*/
++#ifndef USE_SW_FB
++# define USE_SW_FB 0
++#endif
++
++/*
++ USE_SUPER_SAMPLING
++
++ This define enables super-sampling support.
++*/
++#define USE_SUPER_SAMPLING 0
++
++/*
++ PROFILE_HAL_COUNTERS
++
++ This define enables HAL counter profiling support. HW and SHADER
++ counter profiling depends on this.
++*/
++#ifndef PROFILE_HAL_COUNTERS
++# define PROFILE_HAL_COUNTERS 1
++#endif
++
++/*
++ PROFILE_HW_COUNTERS
++
++ This define enables HW counter profiling support.
++*/
++#ifndef PROFILE_HW_COUNTERS
++# define PROFILE_HW_COUNTERS 1
++#endif
++
++/*
++ PROFILE_SHADER_COUNTERS
++
++ This define enables SHADER counter profiling support.
++*/
++#ifndef PROFILE_SHADER_COUNTERS
++# define PROFILE_SHADER_COUNTERS 1
++#endif
++
++/*
++ COMMAND_PROCESSOR_VERSION
++
++ The version of the command buffer and task manager.
++*/
++#define COMMAND_PROCESSOR_VERSION 1
++
++/*
++ gcdDUMP_KEY
++
++ Set this to a string that appears in 'cat /proc/<pid>/cmdline'. E.g. 'camera'.
++ HAL will create dumps for the processes matching this key.
++*/
++#ifndef gcdDUMP_KEY
++# define gcdDUMP_KEY "process"
++#endif
++
++/*
++ gcdDUMP_PATH
++
++ The dump file location. Some processes cannot write to the sdcard.
++ Try apps' data dir, e.g. /data/data/com.android.launcher
++*/
++#ifndef gcdDUMP_PATH
++#if defined(ANDROID)
++# define gcdDUMP_PATH "/mnt/sdcard/"
++#else
++# define gcdDUMP_PATH "./"
++#endif
++#endif
++
++/*
++ gcdDUMP
++
++ When set to 1, a dump of all states and memory uploads, as well as other
++ hardware related execution will be printed to the debug console. This
++ data can be used for playing back applications.
++*/
++#ifndef gcdDUMP
++# define gcdDUMP 0
++#endif
++
++/*
++ gcdDUMP_API
++
++ When set to 1, a high level dump of the EGL and GL/VG APs's are
++ captured.
++*/
++#ifndef gcdDUMP_API
++# define gcdDUMP_API 0
++#endif
++
++/*
++ gcdDUMP_FRAMERATE
++ When set to a value other than zero, averaqe frame rate will be dumped.
++ The value set is the starting frame that the average will be calculated.
++ This is needed because sometimes first few frames are too slow to be included
++ in the average. Frame count starts from 1.
++*/
++#ifndef gcdDUMP_FRAMERATE
++# define gcdDUMP_FRAMERATE 0
++#endif
++
++/*
++ gcdVIRTUAL_COMMAND_BUFFER
++ When set to 1, user command buffer and context buffer will be allocated
++ from gcvPOOL_VIRTUAL.
++*/
++#ifndef gcdVIRTUAL_COMMAND_BUFFER
++# define gcdVIRTUAL_COMMAND_BUFFER 0
++#endif
++
++/*
++ gcdENABLE_FSCALE_VAL_ADJUST
++ When non-zero, FSCALE_VAL when gcvPOWER_ON can be adjusted externally.
++ */
++#ifndef gcdENABLE_FSCALE_VAL_ADJUST
++# define gcdENABLE_FSCALE_VAL_ADJUST 1
++#endif
++
++/*
++ gcdDUMP_IN_KERNEL
++
++ When set to 1, all dumps will happen in the kernel. This is handy if
++ you want the kernel to dump its command buffers as well and the data
++ needs to be in sync.
++*/
++#ifndef gcdDUMP_IN_KERNEL
++# define gcdDUMP_IN_KERNEL 0
++#endif
++
++/*
++ gcdDUMP_COMMAND
++
++ When set to non-zero, the command queue will dump all incoming command
++ and context buffers as well as all other modifications to the command
++ queue.
++*/
++#ifndef gcdDUMP_COMMAND
++# define gcdDUMP_COMMAND 0
++#endif
++
++/*
++ gcdDUMP_FRAME_TGA
++
++ When set to a value other than 0, a dump of the frame specified by the value,
++ will be done into frame.tga. Frame count starts from 1.
++ */
++#ifndef gcdDUMP_FRAME_TGA
++#define gcdDUMP_FRAME_TGA 0
++#endif
++/*
++ gcdNULL_DRIVER
++
++ Set to 1 for infinite speed hardware.
++ Set to 2 for bypassing the HAL.
++ Set to 3 for bypassing the drivers.
++*/
++#ifndef gcdNULL_DRIVER
++# define gcdNULL_DRIVER 0
++#endif
++
++/*
++ gcdENABLE_TIMEOUT_DETECTION
++
++ Enable timeout detection.
++*/
++#ifndef gcdENABLE_TIMEOUT_DETECTION
++# define gcdENABLE_TIMEOUT_DETECTION 0
++#endif
++
++/*
++ gcdCMD_BUFFER_SIZE
++
++ Number of bytes in a command buffer.
++*/
++#ifndef gcdCMD_BUFFER_SIZE
++# define gcdCMD_BUFFER_SIZE (128 << 10)
++#endif
++
++/*
++ gcdCMD_BUFFERS
++
++ Number of command buffers to use per client.
++*/
++#ifndef gcdCMD_BUFFERS
++# define gcdCMD_BUFFERS 2
++#endif
++
++/*
++ gcdMAX_CMD_BUFFERS
++
++ Maximum number of command buffers to use per client.
++*/
++#ifndef gcdMAX_CMD_BUFFERS
++# define gcdMAX_CMD_BUFFERS 8
++#endif
++
++/*
++ gcdCOMMAND_QUEUES
++
++ Number of command queues in the kernel.
++*/
++#ifndef gcdCOMMAND_QUEUES
++# define gcdCOMMAND_QUEUES 2
++#endif
++
++/*
++ gcdPOWER_CONTROL_DELAY
++
++ The delay in milliseconds required to wait until the GPU has woke up
++ from a suspend or power-down state. This is system dependent because
++ the bus clock also needs to stabalize.
++*/
++#ifndef gcdPOWER_CONTROL_DELAY
++# define gcdPOWER_CONTROL_DELAY 0
++#endif
++
++/*
++ gcdMIRROR_PAGETABLE
++
++ Enable it when GPUs with old MMU and new MMU exist at same SoC. It makes
++ each GPU use same virtual address to access same physical memory.
++*/
++#ifndef gcdMIRROR_PAGETABLE
++# define gcdMIRROR_PAGETABLE 0
++#endif
++
++/*
++ gcdMMU_SIZE
++
++ Size of the MMU page table in bytes. Each 4 bytes can hold 4kB worth of
++ virtual data.
++*/
++#ifndef gcdMMU_SIZE
++#if gcdMIRROR_PAGETABLE
++# define gcdMMU_SIZE 0x200000
++#else
++# define gcdMMU_SIZE (2048 << 10)
++#endif
++#endif
++
++/*
++ gcdSECURE_USER
++
++ Use logical addresses instead of physical addresses in user land. In
++ this case a hint table is created for both command buffers and context
++ buffers, and that hint table will be used to patch up those buffers in
++ the kernel when they are ready to submit.
++*/
++#ifndef gcdSECURE_USER
++# define gcdSECURE_USER 0
++#endif
++
++/*
++ gcdSECURE_CACHE_SLOTS
++
++ Number of slots in the logical to DMA address cache table. Each time a
++ logical address needs to be translated into a DMA address for the GPU,
++ this cache will be walked. The replacement scheme is LRU.
++*/
++#ifndef gcdSECURE_CACHE_SLOTS
++# define gcdSECURE_CACHE_SLOTS 1024
++#endif
++
++/*
++ gcdSECURE_CACHE_METHOD
++
++ Replacement scheme used for Secure Cache. The following options are
++ available:
++
++ gcdSECURE_CACHE_LRU
++ A standard LRU cache.
++
++ gcdSECURE_CACHE_LINEAR
++ A linear walker with the idea that an application will always
++ render the scene in a similar way, so the next entry in the
++ cache should be a hit most of the time.
++
++ gcdSECURE_CACHE_HASH
++ A 256-entry hash table.
++
++ gcdSECURE_CACHE_TABLE
++ A simple cache but with potential of a lot of cache replacement.
++*/
++#ifndef gcdSECURE_CACHE_METHOD
++# define gcdSECURE_CACHE_METHOD gcdSECURE_CACHE_HASH
++#endif
++
++/*
++ gcdREGISTER_ACCESS_FROM_USER
++
++ Set to 1 to allow IOCTL calls to get through from user land. This
++ should only be in debug or development drops.
++*/
++#ifndef gcdREGISTER_ACCESS_FROM_USER
++# define gcdREGISTER_ACCESS_FROM_USER 1
++#endif
++
++/*
++ gcdUSER_HEAP_ALLOCATOR
++
++ Set to 1 to enable user mode heap allocator for fast memory allocation
++ and destroying. Otherwise, memory allocation/destroying in user mode
++ will be directly managed by system. Only for linux for now.
++*/
++#ifndef gcdUSER_HEAP_ALLOCATOR
++# define gcdUSER_HEAP_ALLOCATOR 1
++#endif
++
++/*
++ gcdHEAP_SIZE
++
++ Set the allocation size for the internal heaps. Each time a heap is
++ full, a new heap will be allocated with this minmimum amount of bytes.
++ The bigger this size, the fewer heaps there are to allocate, the better
++ the performance. However, heaps won't be freed until they are
++ completely free, so there might be some more memory waste if the size is
++ too big.
++*/
++#ifndef gcdHEAP_SIZE
++# define gcdHEAP_SIZE (64 << 10)
++#endif
++
++/*
++ gcdPOWER_SUSNPEND_WHEN_IDLE
++
++ Set to 1 to make GPU enter gcvPOWER_SUSPEND when idle detected,
++ otherwise GPU will enter gcvPOWER_IDLE.
++*/
++#ifndef gcdPOWER_SUSNPEND_WHEN_IDLE
++# define gcdPOWER_SUSNPEND_WHEN_IDLE 1
++#endif
++
++/*
++ gcdFPGA_BUILD
++
++ This define enables work arounds for FPGA images.
++*/
++#ifndef gcdFPGA_BUILD
++# define gcdFPGA_BUILD 0
++#endif
++
++/*
++ gcdGPU_TIMEOUT
++
++ This define specified the number of milliseconds the system will wait
++ before it broadcasts the GPU is stuck. In other words, it will define
++ the timeout of any operation that needs to wait for the GPU.
++
++ If the value is 0, no timeout will be checked for.
++*/
++#ifndef gcdGPU_TIMEOUT
++#if gcdFPGA_BUILD
++# define gcdGPU_TIMEOUT 0
++# else
++# define gcdGPU_TIMEOUT 20000
++# endif
++#endif
++
++/*
++ gcdGPU_ADVANCETIMER
++
++ it is advance timer.
++*/
++#ifndef gcdGPU_ADVANCETIMER
++# define gcdGPU_ADVANCETIMER 250
++#endif
++
++/*
++ gcdSTATIC_LINK
++
++ This define disalbes static linking;
++*/
++#ifndef gcdSTATIC_LINK
++# define gcdSTATIC_LINK 0
++#endif
++
++/*
++ gcdUSE_NEW_HEAP
++
++ Setting this define to 1 enables new heap.
++*/
++#ifndef gcdUSE_NEW_HEAP
++# define gcdUSE_NEW_HEAP 0
++#endif
++
++/*
++ gcdCMD_NO_2D_CONTEXT
++
++ This define enables no-context 2D command buffer.
++*/
++#ifndef gcdCMD_NO_2D_CONTEXT
++# define gcdCMD_NO_2D_CONTEXT 1
++#endif
++
++/*
++ gcdENABLE_BANK_ALIGNMENT
++
++ When enabled, video memory is allocated bank aligned. The vendor can modify
++ _GetSurfaceBankAlignment() and gcoSURF_GetBankOffsetBytes() to define how
++ different types of allocations are bank and channel aligned.
++ When disabled (default), no bank alignment is done.
++*/
++#ifndef gcdENABLE_BANK_ALIGNMENT
++# define gcdENABLE_BANK_ALIGNMENT 0
++#endif
++
++/*
++ gcdBANK_BIT_START
++
++ Specifies the start bit of the bank (inclusive).
++*/
++#ifndef gcdBANK_BIT_START
++# define gcdBANK_BIT_START 12
++#endif
++
++/*
++ gcdBANK_BIT_END
++
++ Specifies the end bit of the bank (inclusive).
++*/
++#ifndef gcdBANK_BIT_END
++# define gcdBANK_BIT_END 14
++#endif
++
++/*
++ gcdBANK_CHANNEL_BIT
++
++ When set, video memory when allocated bank aligned is allocated such that
++ render and depth buffer addresses alternate on the channel bit specified.
++ This option has an effect only when gcdENABLE_BANK_ALIGNMENT is enabled.
++ When disabled (default), no alteration is done.
++*/
++#ifndef gcdBANK_CHANNEL_BIT
++# define gcdBANK_CHANNEL_BIT 7
++#endif
++
++/*
++ gcdDYNAMIC_SPEED
++
++ When non-zero, it informs the kernel driver to use the speed throttling
++ broadcasting functions to inform the system the GPU should be spet up or
++ slowed down. It will send a broadcast for slowdown each "interval"
++ specified by this define in milliseconds
++ (gckOS_BroadcastCalibrateSpeed).
++*/
++#ifndef gcdDYNAMIC_SPEED
++# define gcdDYNAMIC_SPEED 2000
++#endif
++
++/*
++ gcdDYNAMIC_EVENT_THRESHOLD
++
++ When non-zero, it specifies the maximum number of available events at
++ which the kernel driver will issue a broadcast to speed up the GPU
++ (gckOS_BroadcastHurry).
++*/
++#ifndef gcdDYNAMIC_EVENT_THRESHOLD
++# define gcdDYNAMIC_EVENT_THRESHOLD 5
++#endif
++
++/*
++ gcdENABLE_PROFILING
++
++ Enable profiling macros.
++*/
++#ifndef gcdENABLE_PROFILING
++# define gcdENABLE_PROFILING 0
++#endif
++
++/*
++ gcdENABLE_128B_MERGE
++
++ Enable 128B merge for the BUS control.
++*/
++#ifndef gcdENABLE_128B_MERGE
++# define gcdENABLE_128B_MERGE 0
++#endif
++
++/*
++ gcdFRAME_DB
++
++ When non-zero, it specified the number of frames inside the frame
++ database. The frame DB will collect per-frame timestamps and hardware
++ counters.
++*/
++#ifndef gcdFRAME_DB
++# define gcdFRAME_DB 0
++# define gcdFRAME_DB_RESET 0
++# define gcdFRAME_DB_NAME "/var/log/frameDB.log"
++#endif
++
++/*
++ gcdENABLE_VG
++ enable the 2D openVG
++*/
++
++#ifndef gcdENABLE_VG
++# define gcdENABLE_VG 0
++#endif
++
++/*
++ gcdDYNAMIC_MAP_RESERVED_MEMORY
++
++ When gcvPOOL_SYSTEM is constructed from RESERVED memory,
++ driver can map the whole reserved memory to kernel space
++ at the beginning, or just map a piece of memory when need
++ to access.
++
++ Notice:
++ - It's only for the 2D openVG. For other cores, there is
++ _NO_ need to map reserved memory to kernel.
++ - It's meaningless when memory is allocated by
++ gckOS_AllocateContiguous, in that case, memory is always
++ mapped by system when allocated.
++*/
++#ifndef gcdDYNAMIC_MAP_RESERVED_MEMORY
++# define gcdDYNAMIC_MAP_RESERVED_MEMORY 1
++#endif
++
++/*
++ gcdPAGED_MEMORY_CACHEABLE
++
++ When non-zero, paged memory will be cacheable.
++
++ Normally, driver will detemines whether a video memory
++ is cacheable or not. When cacheable is not neccessary,
++ it will be writecombine.
++
++ This option is only for those SOC which can't enable
++ writecombine without enabling cacheable.
++*/
++
++#ifndef gcdPAGED_MEMORY_CACHEABLE
++# define gcdPAGED_MEMORY_CACHEABLE 0
++#endif
++
++/*
++ gcdNONPAGED_MEMORY_CACHEABLE
++
++ When non-zero, non paged memory will be cacheable.
++*/
++
++#ifndef gcdNONPAGED_MEMORY_CACHEABLE
++# define gcdNONPAGED_MEMORY_CACHEABLE 0
++#endif
++
++/*
++ gcdNONPAGED_MEMORY_BUFFERABLE
++
++ When non-zero, non paged memory will be bufferable.
++ gcdNONPAGED_MEMORY_BUFFERABLE and gcdNONPAGED_MEMORY_CACHEABLE
++ can't be set 1 at same time
++*/
++
++#ifndef gcdNONPAGED_MEMORY_BUFFERABLE
++# define gcdNONPAGED_MEMORY_BUFFERABLE 1
++#endif
++
++/*
++ gcdENABLE_INFINITE_SPEED_HW
++ enable the Infinte HW , this is for 2D openVG
++*/
++
++#ifndef gcdENABLE_INFINITE_SPEED_HW
++# define gcdENABLE_INFINITE_SPEED_HW 0
++#endif
++
++/*
++ gcdENABLE_TS_DOUBLE_BUFFER
++ enable the TS double buffer, this is for 2D openVG
++*/
++
++#ifndef gcdENABLE_TS_DOUBLE_BUFFER
++# define gcdENABLE_TS_DOUBLE_BUFFER 1
++#endif
++
++/*
++ gcd6000_SUPPORT
++
++ Temporary define to enable/disable 6000 support.
++ */
++#ifndef gcd6000_SUPPORT
++# define gcd6000_SUPPORT 0
++#endif
++
++/*
++ gcdPOWEROFF_TIMEOUT
++
++ When non-zero, GPU will power off automatically from
++ idle state, and gcdPOWEROFF_TIMEOUT is also the default
++ timeout in milliseconds.
++ */
++
++#ifndef gcdPOWEROFF_TIMEOUT
++# define gcdPOWEROFF_TIMEOUT 300
++#endif
++
++/*
++ gcdUSE_VIDMEM_PER_PID
++*/
++#ifndef gcdUSE_VIDMEM_PER_PID
++# define gcdUSE_VIDMEM_PER_PID 0
++#endif
++
++/*
++ QNX_SINGLE_THREADED_DEBUGGING
++*/
++#ifndef QNX_SINGLE_THREADED_DEBUGGING
++# define QNX_SINGLE_THREADED_DEBUGGING 0
++#endif
++
++/*
++ gcdENABLE_RECOVERY
++
++ This define enables the recovery code.
++*/
++#ifndef gcdENABLE_RECOVERY
++# define gcdENABLE_RECOVERY 0
++#endif
++
++/*
++ gcdRENDER_THREADS
++
++ Number of render threads. Make it zero, and there will be no render
++ threads.
++*/
++#ifndef gcdRENDER_THREADS
++# define gcdRENDER_THREADS 0
++#endif
++
++/*
++ gcdSMP
++
++ This define enables SMP support.
++
++ Currently, it only works on Linux/Android,
++ Kbuild will config it according to whether
++ CONFIG_SMP is set.
++
++*/
++#ifndef gcdSMP
++# define gcdSMP 0
++#endif
++
++/*
++ gcdSUPPORT_SWAP_RECTANGLE
++
++ Support swap with a specific rectangle.
++
++ Set the rectangle with eglSetSwapRectangleANDROID api.
++*/
++#ifndef gcdSUPPORT_SWAP_RECTANGLE
++# define gcdSUPPORT_SWAP_RECTANGLE 0
++#endif
++
++/*
++ gcdGPU_LINEAR_BUFFER_ENABLED
++
++ Use linear buffer for GPU apps so HWC can do 2D composition.
++*/
++#ifndef gcdGPU_LINEAR_BUFFER_ENABLED
++# define gcdGPU_LINEAR_BUFFER_ENABLED 1
++#endif
++
++/*
++ gcdENABLE_RENDER_INTO_WINDOW
++
++ Enable Render-Into-Window (ie, No-Resolve) feature on android.
++ NOTE that even if enabled, it still depends on hardware feature and
++ android application behavior. When hardware feature or application
++ behavior can not support render into window mode, it will fail back
++ to normal mode.
++ When Render-Into-Window is finally used, window back buffer of android
++ applications will be allocated matching render target tiling format.
++ Otherwise buffer tiling is decided by the above option
++ 'gcdGPU_LINEAR_BUFFER_ENABLED'.
++*/
++#ifndef gcdENABLE_RENDER_INTO_WINDOW
++# define gcdENABLE_RENDER_INTO_WINDOW 1
++#endif
++
++/*
++ gcdSHARED_RESOLVE_BUFFER_ENABLED
++
++ Use shared resolve buffer for all app buffers.
++*/
++#ifndef gcdSHARED_RESOLVE_BUFFER_ENABLED
++# define gcdSHARED_RESOLVE_BUFFER_ENABLED 0
++#endif
++
++/*
++ gcdUSE_TRIANGLE_STRIP_PATCH
++ */
++#ifndef gcdUSE_TRIANGLE_STRIP_PATCH
++# define gcdUSE_TRIANGLE_STRIP_PATCH 1
++#endif
++
++/*
++ gcdENABLE_OUTER_CACHE_PATCH
++
++ Enable the outer cache patch.
++*/
++#ifndef gcdENABLE_OUTER_CACHE_PATCH
++# define gcdENABLE_OUTER_CACHE_PATCH 0
++#endif
++
++#ifndef gcdANDROID_UNALIGNED_LINEAR_COMPOSITION_ADJUST
++# ifdef ANDROID
++# define gcdANDROID_UNALIGNED_LINEAR_COMPOSITION_ADJUST 1
++# else
++# define gcdANDROID_UNALIGNED_LINEAR_COMPOSITION_ADJUST 0
++# endif
++#endif
++
++#ifndef gcdENABLE_PE_DITHER_FIX
++# define gcdENABLE_PE_DITHER_FIX 1
++#endif
++
++#ifndef gcdSHARED_PAGETABLE
++# define gcdSHARED_PAGETABLE 1
++#endif
++#ifndef gcdUSE_PVR
++# define gcdUSE_PVR 1
++#endif
++
++/*
++ gcdSMALL_BLOCK_SIZE
++
++ When non-zero, a part of VIDMEM will be reserved for requests
++ whose requesting size is less than gcdSMALL_BLOCK_SIZE.
++
++ For Linux, it's the size of a page. If this requeset fallbacks
++ to gcvPOOL_CONTIGUOUS or gcvPOOL_VIRTUAL, memory will be wasted
++ because they allocate a page at least.
++ */
++#ifndef gcdSMALL_BLOCK_SIZE
++# define gcdSMALL_BLOCK_SIZE 4096
++# define gcdRATIO_FOR_SMALL_MEMORY 32
++#endif
++
++/*
++ gcdCONTIGUOUS_SIZE_LIMIT
++ When non-zero, size of video node from gcvPOOL_CONTIGUOUS is
++ limited by gcdCONTIGUOUS_SIZE_LIMIT.
++ */
++#ifndef gcdCONTIGUOUS_SIZE_LIMIT
++# define gcdCONTIGUOUS_SIZE_LIMIT 0
++#endif
++
++#ifndef gcdDISALBE_EARLY_EARLY_Z
++# define gcdDISALBE_EARLY_EARLY_Z 1
++#endif
++
++#ifndef gcdSHADER_SRC_BY_MACHINECODE
++# define gcdSHADER_SRC_BY_MACHINECODE 1
++#endif
++
++/*
++ gcdLINK_QUEUE_SIZE
++
++ When non-zero, driver maintains a queue to record information of
++ latest lined context buffer and command buffer. Data in this queue
++ is be used to debug.
++*/
++#ifndef gcdLINK_QUEUE_SIZE
++# define gcdLINK_QUEUE_SIZE 0
++#endif
++
++/* gcdALPHA_KILL_IN_SHADER
++ *
++ * Enable alpha kill inside the shader. This will be set automatically by the
++ * HAL if certain states match a criteria.
++ */
++#ifndef gcdALPHA_KILL_IN_SHADER
++# define gcdALPHA_KILL_IN_SHADER 1
++#endif
++
++/* gcdHIGH_PRECISION_DELAY_ENABLE
++ *
++ * Enable high precision schedule delay with 1ms unit. otherwise schedule delay up to 10ms.
++ * Browser app performance will have obvious drop without this enablement
++ */
++#ifndef gcdHIGH_PRECISION_DELAY_ENABLE
++# define gcdHIGH_PRECISION_DELAY_ENABLE 1
++#endif
++
++#ifndef gcdUSE_WCLIP_PATCH
++# define gcdUSE_WCLIP_PATCH 1
++#endif
++
++#ifndef gcdHZ_L2_DISALBE
++# define gcdHZ_L2_DISALBE 1
++#endif
++
++#ifndef gcdBUGFIX15_DISABLE
++# define gcdBUGFIX15_DISABLE 1
++#endif
++
++#ifndef gcdDISABLE_HZ_FAST_CLEAR
++# define gcdDISABLE_HZ_FAST_CLEAR 1
++#endif
++
++#ifndef gcdUSE_NPOT_PATCH
++#define gcdUSE_NPOT_PATCH 1
++#endif
++
++#ifndef gcdSYNC
++# define gcdSYNC 1
++#endif
++
++#ifndef gcdENABLE_SPECIAL_HINT3
++# define gcdENABLE_SPECIAL_HINT3 1
++#endif
++
++#if defined(ANDROID)
++#ifndef gcdPRE_ROTATION
++# define gcdPRE_ROTATION 1
++#endif
++#endif
++
++/*
++ gcdDVFS
++
++ When non-zero, software will make use of dynamic voltage and
++ frequency feature.
++ */
++#ifndef gcdDVFS
++# define gcdDVFS 1
++# define gcdDVFS_ANAYLSE_WINDOW 4
++# define gcdDVFS_POLLING_TIME (gcdDVFS_ANAYLSE_WINDOW * 4)
++#endif
++
++/*
++ gcdANDROID_NATIVE_FENCE_SYNC
++
++ Enable android native fence sync. It is introduced since jellybean-4.2.
++ Depends on linux kernel option: CONFIG_SYNC.
++
++ 0: Disabled
++ 1: Build framework for native fence sync feature, and EGL extension
++ 2: Enable async swap buffers for client
++ * Native fence sync for client 'queueBuffer' in EGL, which is
++ 'acquireFenceFd' for layer in compositor side.
++ 3. Enable async hwcomposer composition.
++ * 'releaseFenceFd' for layer in compositor side, which is native
++ fence sync when client 'dequeueBuffer'
++ * Native fence sync for compositor 'queueBuffer' in EGL, which is
++ 'acquireFenceFd' for framebuffer target for DC
++ */
++#ifndef gcdANDROID_NATIVE_FENCE_SYNC
++# define gcdANDROID_NATIVE_FENCE_SYNC 0
++#endif
++
++#ifndef gcdFORCE_MIPMAP
++# define gcdFORCE_MIPMAP 1
++#endif
++
++/*
++ gcdFORCE_GAL_LOAD_TWICE
++
++ When non-zero, each thread except the main one will load libGAL.so twice to avoid potential segmetantion fault when app using dlopen/dlclose.
++ If threads exit arbitrarily, libGAL.so may not unload until the process quit.
++ */
++#ifndef gcdFORCE_GAL_LOAD_TWICE
++# define gcdFORCE_GAL_LOAD_TWICE 0
++#endif
++
++#endif /* __gc_hal_options_h_ */
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_profiler.h linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_profiler.h
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_profiler.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_profiler.h 2015-07-27 23:13:06.214808565 +0200
+@@ -0,0 +1,584 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_profiler_h_
++#define __gc_hal_profiler_h_
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++#define GLVERTEX_OBJECT 10
++#define GLVERTEX_OBJECT_BYTES 11
++
++#define GLINDEX_OBJECT 20
++#define GLINDEX_OBJECT_BYTES 21
++
++#define GLTEXTURE_OBJECT 30
++#define GLTEXTURE_OBJECT_BYTES 31
++
++#if VIVANTE_PROFILER
++#define gcmPROFILE_GC(Enum, Value) gcoPROFILER_Count(gcvNULL, Enum, Value)
++#else
++#define gcmPROFILE_GC(Enum, Value) do { } while (gcvFALSE)
++#endif
++
++#ifndef gcdNEW_PROFILER_FILE
++#define gcdNEW_PROFILER_FILE 1
++#endif
++
++#define ES11_CALLS 151
++#define ES11_DRAWCALLS (ES11_CALLS + 1)
++#define ES11_STATECHANGECALLS (ES11_DRAWCALLS + 1)
++#define ES11_POINTCOUNT (ES11_STATECHANGECALLS + 1)
++#define ES11_LINECOUNT (ES11_POINTCOUNT + 1)
++#define ES11_TRIANGLECOUNT (ES11_LINECOUNT + 1)
++
++#define ES20_CALLS 159
++#define ES20_DRAWCALLS (ES20_CALLS + 1)
++#define ES20_STATECHANGECALLS (ES20_DRAWCALLS + 1)
++#define ES20_POINTCOUNT (ES20_STATECHANGECALLS + 1)
++#define ES20_LINECOUNT (ES20_POINTCOUNT + 1)
++#define ES20_TRIANGLECOUNT (ES20_LINECOUNT + 1)
++
++#define VG11_CALLS 88
++#define VG11_DRAWCALLS (VG11_CALLS + 1)
++#define VG11_STATECHANGECALLS (VG11_DRAWCALLS + 1)
++#define VG11_FILLCOUNT (VG11_STATECHANGECALLS + 1)
++#define VG11_STROKECOUNT (VG11_FILLCOUNT + 1)
++/* End of Driver API ID Definitions. */
++
++/* HAL & MISC IDs. */
++#define HAL_VERTBUFNEWBYTEALLOC 1
++#define HAL_VERTBUFTOTALBYTEALLOC (HAL_VERTBUFNEWBYTEALLOC + 1)
++#define HAL_VERTBUFNEWOBJALLOC (HAL_VERTBUFTOTALBYTEALLOC + 1)
++#define HAL_VERTBUFTOTALOBJALLOC (HAL_VERTBUFNEWOBJALLOC + 1)
++#define HAL_INDBUFNEWBYTEALLOC (HAL_VERTBUFTOTALOBJALLOC + 1)
++#define HAL_INDBUFTOTALBYTEALLOC (HAL_INDBUFNEWBYTEALLOC + 1)
++#define HAL_INDBUFNEWOBJALLOC (HAL_INDBUFTOTALBYTEALLOC + 1)
++#define HAL_INDBUFTOTALOBJALLOC (HAL_INDBUFNEWOBJALLOC + 1)
++#define HAL_TEXBUFNEWBYTEALLOC (HAL_INDBUFTOTALOBJALLOC + 1)
++#define HAL_TEXBUFTOTALBYTEALLOC (HAL_TEXBUFNEWBYTEALLOC + 1)
++#define HAL_TEXBUFNEWOBJALLOC (HAL_TEXBUFTOTALBYTEALLOC + 1)
++#define HAL_TEXBUFTOTALOBJALLOC (HAL_TEXBUFNEWOBJALLOC + 1)
++
++#define GPU_CYCLES 1
++#define GPU_READ64BYTE (GPU_CYCLES + 1)
++#define GPU_WRITE64BYTE (GPU_READ64BYTE + 1)
++#define GPU_TOTALCYCLES (GPU_WRITE64BYTE + 1)
++#define GPU_IDLECYCLES (GPU_TOTALCYCLES + 1)
++
++#define VS_INSTCOUNT 1
++#define VS_BRANCHINSTCOUNT (VS_INSTCOUNT + 1)
++#define VS_TEXLDINSTCOUNT (VS_BRANCHINSTCOUNT + 1)
++#define VS_RENDEREDVERTCOUNT (VS_TEXLDINSTCOUNT + 1)
++#define VS_SOURCE (VS_RENDEREDVERTCOUNT + 1)
++
++#define PS_INSTCOUNT 1
++#define PS_BRANCHINSTCOUNT (PS_INSTCOUNT + 1)
++#define PS_TEXLDINSTCOUNT (PS_BRANCHINSTCOUNT + 1)
++#define PS_RENDEREDPIXCOUNT (PS_TEXLDINSTCOUNT + 1)
++#define PS_SOURCE (PS_RENDEREDPIXCOUNT + 1)
++
++#define PA_INVERTCOUNT 1
++#define PA_INPRIMCOUNT (PA_INVERTCOUNT + 1)
++#define PA_OUTPRIMCOUNT (PA_INPRIMCOUNT + 1)
++#define PA_DEPTHCLIPCOUNT (PA_OUTPRIMCOUNT + 1)
++#define PA_TRIVIALREJCOUNT (PA_DEPTHCLIPCOUNT + 1)
++#define PA_CULLCOUNT (PA_TRIVIALREJCOUNT + 1)
++
++#define SE_TRIANGLECOUNT 1
++#define SE_LINECOUNT (SE_TRIANGLECOUNT + 1)
++
++#define RA_VALIDPIXCOUNT 1
++#define RA_TOTALQUADCOUNT (RA_VALIDPIXCOUNT + 1)
++#define RA_VALIDQUADCOUNTEZ (RA_TOTALQUADCOUNT + 1)
++#define RA_TOTALPRIMCOUNT (RA_VALIDQUADCOUNTEZ + 1)
++#define RA_PIPECACHEMISSCOUNT (RA_TOTALPRIMCOUNT + 1)
++#define RA_PREFCACHEMISSCOUNT (RA_PIPECACHEMISSCOUNT + 1)
++#define RA_EEZCULLCOUNT (RA_PREFCACHEMISSCOUNT + 1)
++
++#define TX_TOTBILINEARREQ 1
++#define TX_TOTTRILINEARREQ (TX_TOTBILINEARREQ + 1)
++#define TX_TOTDISCARDTEXREQ (TX_TOTTRILINEARREQ + 1)
++#define TX_TOTTEXREQ (TX_TOTDISCARDTEXREQ + 1)
++#define TX_MEMREADCOUNT (TX_TOTTEXREQ + 1)
++#define TX_MEMREADIN8BCOUNT (TX_MEMREADCOUNT + 1)
++#define TX_CACHEMISSCOUNT (TX_MEMREADIN8BCOUNT + 1)
++#define TX_CACHEHITTEXELCOUNT (TX_CACHEMISSCOUNT + 1)
++#define TX_CACHEMISSTEXELCOUNT (TX_CACHEHITTEXELCOUNT + 1)
++
++#define PE_KILLEDBYCOLOR 1
++#define PE_KILLEDBYDEPTH (PE_KILLEDBYCOLOR + 1)
++#define PE_DRAWNBYCOLOR (PE_KILLEDBYDEPTH + 1)
++#define PE_DRAWNBYDEPTH (PE_DRAWNBYCOLOR + 1)
++
++#define MC_READREQ8BPIPE 1
++#define MC_READREQ8BIP (MC_READREQ8BPIPE + 1)
++#define MC_WRITEREQ8BPIPE (MC_READREQ8BIP + 1)
++
++#define AXI_READREQSTALLED 1
++#define AXI_WRITEREQSTALLED (AXI_READREQSTALLED + 1)
++#define AXI_WRITEDATASTALLED (AXI_WRITEREQSTALLED + 1)
++
++#define PVS_INSTRCOUNT 1
++#define PVS_ALUINSTRCOUNT (PVS_INSTRCOUNT + 1)
++#define PVS_TEXINSTRCOUNT (PVS_ALUINSTRCOUNT + 1)
++#define PVS_ATTRIBCOUNT (PVS_TEXINSTRCOUNT + 1)
++#define PVS_UNIFORMCOUNT (PVS_ATTRIBCOUNT + 1)
++#define PVS_FUNCTIONCOUNT (PVS_UNIFORMCOUNT + 1)
++#define PVS_SOURCE (PVS_FUNCTIONCOUNT + 1)
++
++#define PPS_INSTRCOUNT 1
++#define PPS_ALUINSTRCOUNT (PPS_INSTRCOUNT + 1)
++#define PPS_TEXINSTRCOUNT (PPS_ALUINSTRCOUNT + 1)
++#define PPS_ATTRIBCOUNT (PPS_TEXINSTRCOUNT + 1)
++#define PPS_UNIFORMCOUNT (PPS_ATTRIBCOUNT + 1)
++#define PPS_FUNCTIONCOUNT (PPS_UNIFORMCOUNT + 1)
++#define PPS_SOURCE (PPS_FUNCTIONCOUNT + 1)
++/* End of MISC Counter IDs. */
++
++#ifdef gcdNEW_PROFILER_FILE
++
++/* Category Constants. */
++#define VPHEADER 0x010000
++#define VPG_INFO 0x020000
++#define VPG_TIME 0x030000
++#define VPG_MEM 0x040000
++#define VPG_ES11 0x050000
++#define VPG_ES20 0x060000
++#define VPG_VG11 0x070000
++#define VPG_HAL 0x080000
++#define VPG_HW 0x090000
++#define VPG_GPU 0x0a0000
++#define VPG_VS 0x0b0000
++#define VPG_PS 0x0c0000
++#define VPG_PA 0x0d0000
++#define VPG_SETUP 0x0e0000
++#define VPG_RA 0x0f0000
++#define VPG_TX 0x100000
++#define VPG_PE 0x110000
++#define VPG_MC 0x120000
++#define VPG_AXI 0x130000
++#define VPG_PROG 0x140000
++#define VPG_PVS 0x150000
++#define VPG_PPS 0x160000
++#define VPG_ES11_TIME 0x170000
++#define VPG_ES20_TIME 0x180000
++#define VPG_FRAME 0x190000
++#define VPG_ES11_DRAW 0x200000
++#define VPG_ES20_DRAW 0x210000
++#define VPG_END 0xff0000
++
++/* Info. */
++#define VPC_INFOCOMPANY (VPG_INFO + 1)
++#define VPC_INFOVERSION (VPC_INFOCOMPANY + 1)
++#define VPC_INFORENDERER (VPC_INFOVERSION + 1)
++#define VPC_INFOREVISION (VPC_INFORENDERER + 1)
++#define VPC_INFODRIVER (VPC_INFOREVISION + 1)
++#define VPC_INFODRIVERMODE (VPC_INFODRIVER + 1)
++#define VPC_INFOSCREENSIZE (VPC_INFODRIVERMODE + 1)
++
++/* Counter Constants. */
++#define VPC_ELAPSETIME (VPG_TIME + 1)
++#define VPC_CPUTIME (VPC_ELAPSETIME + 1)
++
++#define VPC_MEMMAXRES (VPG_MEM + 1)
++#define VPC_MEMSHARED (VPC_MEMMAXRES + 1)
++#define VPC_MEMUNSHAREDDATA (VPC_MEMSHARED + 1)
++#define VPC_MEMUNSHAREDSTACK (VPC_MEMUNSHAREDDATA + 1)
++
++/* OpenGL ES11 Statics Counter IDs. */
++#define VPC_ES11CALLS (VPG_ES11 + ES11_CALLS)
++#define VPC_ES11DRAWCALLS (VPG_ES11 + ES11_DRAWCALLS)
++#define VPC_ES11STATECHANGECALLS (VPG_ES11 + ES11_STATECHANGECALLS)
++#define VPC_ES11POINTCOUNT (VPG_ES11 + ES11_POINTCOUNT)
++#define VPC_ES11LINECOUNT (VPG_ES11 + ES11_LINECOUNT)
++#define VPC_ES11TRIANGLECOUNT (VPG_ES11 + ES11_TRIANGLECOUNT)
++
++/* OpenGL ES20 Statistics Counter IDs. */
++#define VPC_ES20CALLS (VPG_ES20 + ES20_CALLS)
++#define VPC_ES20DRAWCALLS (VPG_ES20 + ES20_DRAWCALLS)
++#define VPC_ES20STATECHANGECALLS (VPG_ES20 + ES20_STATECHANGECALLS)
++#define VPC_ES20POINTCOUNT (VPG_ES20 + ES20_POINTCOUNT)
++#define VPC_ES20LINECOUNT (VPG_ES20 + ES20_LINECOUNT)
++#define VPC_ES20TRIANGLECOUNT (VPG_ES20 + ES20_TRIANGLECOUNT)
++
++/* OpenVG Statistics Counter IDs. */
++#define VPC_VG11CALLS (VPG_VG11 + VG11_CALLS)
++#define VPC_VG11DRAWCALLS (VPG_VG11 + VG11_DRAWCALLS)
++#define VPC_VG11STATECHANGECALLS (VPG_VG11 + VG11_STATECHANGECALLS)
++#define VPC_VG11FILLCOUNT (VPG_VG11 + VG11_FILLCOUNT)
++#define VPC_VG11STROKECOUNT (VPG_VG11 + VG11_STROKECOUNT)
++
++/* HAL Counters. */
++#define VPC_HALVERTBUFNEWBYTEALLOC (VPG_HAL + HAL_VERTBUFNEWBYTEALLOC)
++#define VPC_HALVERTBUFTOTALBYTEALLOC (VPG_HAL + HAL_VERTBUFTOTALBYTEALLOC)
++#define VPC_HALVERTBUFNEWOBJALLOC (VPG_HAL + HAL_VERTBUFNEWOBJALLOC)
++#define VPC_HALVERTBUFTOTALOBJALLOC (VPG_HAL + HAL_VERTBUFTOTALOBJALLOC)
++#define VPC_HALINDBUFNEWBYTEALLOC (VPG_HAL + HAL_INDBUFNEWBYTEALLOC)
++#define VPC_HALINDBUFTOTALBYTEALLOC (VPG_HAL + HAL_INDBUFTOTALBYTEALLOC)
++#define VPC_HALINDBUFNEWOBJALLOC (VPG_HAL + HAL_INDBUFNEWOBJALLOC)
++#define VPC_HALINDBUFTOTALOBJALLOC (VPG_HAL + HAL_INDBUFTOTALOBJALLOC)
++#define VPC_HALTEXBUFNEWBYTEALLOC (VPG_HAL + HAL_TEXBUFNEWBYTEALLOC)
++#define VPC_HALTEXBUFTOTALBYTEALLOC (VPG_HAL + HAL_TEXBUFTOTALBYTEALLOC)
++#define VPC_HALTEXBUFNEWOBJALLOC (VPG_HAL + HAL_TEXBUFNEWOBJALLOC)
++#define VPC_HALTEXBUFTOTALOBJALLOC (VPG_HAL + HAL_TEXBUFTOTALOBJALLOC)
++
++/* HW: GPU Counters. */
++#define VPC_GPUCYCLES (VPG_GPU + GPU_CYCLES)
++#define VPC_GPUREAD64BYTE (VPG_GPU + GPU_READ64BYTE)
++#define VPC_GPUWRITE64BYTE (VPG_GPU + GPU_WRITE64BYTE)
++#define VPC_GPUTOTALCYCLES (VPG_GPU + GPU_TOTALCYCLES)
++#define VPC_GPUIDLECYCLES (VPG_GPU + GPU_IDLECYCLES)
++
++/* HW: Shader Counters. */
++#define VPC_VSINSTCOUNT (VPG_VS + VS_INSTCOUNT)
++#define VPC_VSBRANCHINSTCOUNT (VPG_VS + VS_BRANCHINSTCOUNT)
++#define VPC_VSTEXLDINSTCOUNT (VPG_VS + VS_TEXLDINSTCOUNT)
++#define VPC_VSRENDEREDVERTCOUNT (VPG_VS + VS_RENDEREDVERTCOUNT)
++/* HW: PS Count. */
++#define VPC_PSINSTCOUNT (VPG_PS + PS_INSTCOUNT)
++#define VPC_PSBRANCHINSTCOUNT (VPG_PS + PS_BRANCHINSTCOUNT)
++#define VPC_PSTEXLDINSTCOUNT (VPG_PS + PS_TEXLDINSTCOUNT)
++#define VPC_PSRENDEREDPIXCOUNT (VPG_PS + PS_RENDEREDPIXCOUNT)
++
++
++/* HW: PA Counters. */
++#define VPC_PAINVERTCOUNT (VPG_PA + PA_INVERTCOUNT)
++#define VPC_PAINPRIMCOUNT (VPG_PA + PA_INPRIMCOUNT)
++#define VPC_PAOUTPRIMCOUNT (VPG_PA + PA_OUTPRIMCOUNT)
++#define VPC_PADEPTHCLIPCOUNT (VPG_PA + PA_DEPTHCLIPCOUNT)
++#define VPC_PATRIVIALREJCOUNT (VPG_PA + PA_TRIVIALREJCOUNT)
++#define VPC_PACULLCOUNT (VPG_PA + PA_CULLCOUNT)
++
++/* HW: Setup Counters. */
++#define VPC_SETRIANGLECOUNT (VPG_SETUP + SE_TRIANGLECOUNT)
++#define VPC_SELINECOUNT (VPG_SETUP + SE_LINECOUNT)
++
++/* HW: RA Counters. */
++#define VPC_RAVALIDPIXCOUNT (VPG_RA + RA_VALIDPIXCOUNT)
++#define VPC_RATOTALQUADCOUNT (VPG_RA + RA_TOTALQUADCOUNT)
++#define VPC_RAVALIDQUADCOUNTEZ (VPG_RA + RA_VALIDQUADCOUNTEZ)
++#define VPC_RATOTALPRIMCOUNT (VPG_RA + RA_TOTALPRIMCOUNT)
++#define VPC_RAPIPECACHEMISSCOUNT (VPG_RA + RA_PIPECACHEMISSCOUNT)
++#define VPC_RAPREFCACHEMISSCOUNT (VPG_RA + RA_PREFCACHEMISSCOUNT)
++#define VPC_RAEEZCULLCOUNT (VPG_RA + RA_EEZCULLCOUNT)
++
++/* HW: TEX Counters. */
++#define VPC_TXTOTBILINEARREQ (VPG_TX + TX_TOTBILINEARREQ)
++#define VPC_TXTOTTRILINEARREQ (VPG_TX + TX_TOTTRILINEARREQ)
++#define VPC_TXTOTDISCARDTEXREQ (VPG_TX + TX_TOTDISCARDTEXREQ)
++#define VPC_TXTOTTEXREQ (VPG_TX + TX_TOTTEXREQ)
++#define VPC_TXMEMREADCOUNT (VPG_TX + TX_MEMREADCOUNT)
++#define VPC_TXMEMREADIN8BCOUNT (VPG_TX + TX_MEMREADIN8BCOUNT)
++#define VPC_TXCACHEMISSCOUNT (VPG_TX + TX_CACHEMISSCOUNT)
++#define VPC_TXCACHEHITTEXELCOUNT (VPG_TX + TX_CACHEHITTEXELCOUNT)
++#define VPC_TXCACHEMISSTEXELCOUNT (VPG_TX + TX_CACHEMISSTEXELCOUNT)
++
++/* HW: PE Counters. */
++#define VPC_PEKILLEDBYCOLOR (VPG_PE + PE_KILLEDBYCOLOR)
++#define VPC_PEKILLEDBYDEPTH (VPG_PE + PE_KILLEDBYDEPTH)
++#define VPC_PEDRAWNBYCOLOR (VPG_PE + PE_DRAWNBYCOLOR)
++#define VPC_PEDRAWNBYDEPTH (VPG_PE + PE_DRAWNBYDEPTH)
++
++/* HW: MC Counters. */
++#define VPC_MCREADREQ8BPIPE (VPG_MC + MC_READREQ8BPIPE)
++#define VPC_MCREADREQ8BIP (VPG_MC + MC_READREQ8BIP)
++#define VPC_MCWRITEREQ8BPIPE (VPG_MC + MC_WRITEREQ8BPIPE)
++
++/* HW: AXI Counters. */
++#define VPC_AXIREADREQSTALLED (VPG_AXI + AXI_READREQSTALLED)
++#define VPC_AXIWRITEREQSTALLED (VPG_AXI + AXI_WRITEREQSTALLED)
++#define VPC_AXIWRITEDATASTALLED (VPG_AXI + AXI_WRITEDATASTALLED)
++
++/* PROGRAM: Shader program counters. */
++#define VPC_PVSINSTRCOUNT (VPG_PVS + PVS_INSTRCOUNT)
++#define VPC_PVSALUINSTRCOUNT (VPG_PVS + PVS_ALUINSTRCOUNT)
++#define VPC_PVSTEXINSTRCOUNT (VPG_PVS + PVS_TEXINSTRCOUNT)
++#define VPC_PVSATTRIBCOUNT (VPG_PVS + PVS_ATTRIBCOUNT)
++#define VPC_PVSUNIFORMCOUNT (VPG_PVS + PVS_UNIFORMCOUNT)
++#define VPC_PVSFUNCTIONCOUNT (VPG_PVS + PVS_FUNCTIONCOUNT)
++#define VPC_PVSSOURCE (VPG_PVS + PVS_SOURCE)
++
++#define VPC_PPSINSTRCOUNT (VPG_PPS + PPS_INSTRCOUNT)
++#define VPC_PPSALUINSTRCOUNT (VPG_PPS + PPS_ALUINSTRCOUNT)
++#define VPC_PPSTEXINSTRCOUNT (VPG_PPS + PPS_TEXINSTRCOUNT)
++#define VPC_PPSATTRIBCOUNT (VPG_PPS + PPS_ATTRIBCOUNT)
++#define VPC_PPSUNIFORMCOUNT (VPG_PPS + PPS_UNIFORMCOUNT)
++#define VPC_PPSFUNCTIONCOUNT (VPG_PPS + PPS_FUNCTIONCOUNT)
++#define VPC_PPSSOURCE (VPG_PPS + PPS_SOURCE)
++
++#define VPC_PROGRAMHANDLE (VPG_PROG + 1)
++
++#define VPG_ES20_DRAW_NO (VPG_ES20_DRAW + 1)
++#define VPG_ES11_DRAW_NO (VPG_ES11_DRAW + 1)
++
++#define VPG_FRAME_USEVBO (VPG_FRAME + 1)
++
++#endif
++
++
++/* HW profile information. */
++typedef struct _gcsPROFILER_COUNTERS
++{
++ /* HW static counters. */
++ gctUINT32 gpuClock;
++ gctUINT32 axiClock;
++ gctUINT32 shaderClock;
++
++ /* HW vairable counters. */
++ gctUINT32 gpuClockStart;
++ gctUINT32 gpuClockEnd;
++
++ /* HW vairable counters. */
++ gctUINT32 gpuCyclesCounter;
++ gctUINT32 gpuTotalCyclesCounter;
++ gctUINT32 gpuIdleCyclesCounter;
++ gctUINT32 gpuTotalRead64BytesPerFrame;
++ gctUINT32 gpuTotalWrite64BytesPerFrame;
++
++ /* PE */
++ gctUINT32 pe_pixel_count_killed_by_color_pipe;
++ gctUINT32 pe_pixel_count_killed_by_depth_pipe;
++ gctUINT32 pe_pixel_count_drawn_by_color_pipe;
++ gctUINT32 pe_pixel_count_drawn_by_depth_pipe;
++
++ /* SH */
++ gctUINT32 ps_inst_counter;
++ gctUINT32 rendered_pixel_counter;
++ gctUINT32 vs_inst_counter;
++ gctUINT32 rendered_vertice_counter;
++ gctUINT32 vtx_branch_inst_counter;
++ gctUINT32 vtx_texld_inst_counter;
++ gctUINT32 pxl_branch_inst_counter;
++ gctUINT32 pxl_texld_inst_counter;
++
++ /* PA */
++ gctUINT32 pa_input_vtx_counter;
++ gctUINT32 pa_input_prim_counter;
++ gctUINT32 pa_output_prim_counter;
++ gctUINT32 pa_depth_clipped_counter;
++ gctUINT32 pa_trivial_rejected_counter;
++ gctUINT32 pa_culled_counter;
++
++ /* SE */
++ gctUINT32 se_culled_triangle_count;
++ gctUINT32 se_culled_lines_count;
++
++ /* RA */
++ gctUINT32 ra_valid_pixel_count;
++ gctUINT32 ra_total_quad_count;
++ gctUINT32 ra_valid_quad_count_after_early_z;
++ gctUINT32 ra_total_primitive_count;
++ gctUINT32 ra_pipe_cache_miss_counter;
++ gctUINT32 ra_prefetch_cache_miss_counter;
++ gctUINT32 ra_eez_culled_counter;
++
++ /* TX */
++ gctUINT32 tx_total_bilinear_requests;
++ gctUINT32 tx_total_trilinear_requests;
++ gctUINT32 tx_total_discarded_texture_requests;
++ gctUINT32 tx_total_texture_requests;
++ gctUINT32 tx_mem_read_count;
++ gctUINT32 tx_mem_read_in_8B_count;
++ gctUINT32 tx_cache_miss_count;
++ gctUINT32 tx_cache_hit_texel_count;
++ gctUINT32 tx_cache_miss_texel_count;
++
++ /* MC */
++ gctUINT32 mc_total_read_req_8B_from_pipeline;
++ gctUINT32 mc_total_read_req_8B_from_IP;
++ gctUINT32 mc_total_write_req_8B_from_pipeline;
++
++ /* HI */
++ gctUINT32 hi_axi_cycles_read_request_stalled;
++ gctUINT32 hi_axi_cycles_write_request_stalled;
++ gctUINT32 hi_axi_cycles_write_data_stalled;
++}
++gcsPROFILER_COUNTERS;
++
++/* HAL profile information. */
++typedef struct _gcsPROFILER
++{
++ gctUINT32 enable;
++ gctBOOL enableHal;
++ gctBOOL enableHW;
++ gctBOOL enableSH;
++ gctBOOL isSyncMode;
++
++ gctBOOL useSocket;
++ gctINT sockFd;
++
++ gctFILE file;
++
++ /* Aggregate Information */
++
++ /* Clock Info */
++ gctUINT64 frameStart;
++ gctUINT64 frameEnd;
++
++ /* Current frame information */
++ gctUINT32 frameNumber;
++ gctUINT64 frameStartTimeusec;
++ gctUINT64 frameEndTimeusec;
++ gctUINT64 frameStartCPUTimeusec;
++ gctUINT64 frameEndCPUTimeusec;
++
++#if PROFILE_HAL_COUNTERS
++ gctUINT32 vertexBufferTotalBytesAlloc;
++ gctUINT32 vertexBufferNewBytesAlloc;
++ int vertexBufferTotalObjectsAlloc;
++ int vertexBufferNewObjectsAlloc;
++
++ gctUINT32 indexBufferTotalBytesAlloc;
++ gctUINT32 indexBufferNewBytesAlloc;
++ int indexBufferTotalObjectsAlloc;
++ int indexBufferNewObjectsAlloc;
++
++ gctUINT32 textureBufferTotalBytesAlloc;
++ gctUINT32 textureBufferNewBytesAlloc;
++ int textureBufferTotalObjectsAlloc;
++ int textureBufferNewObjectsAlloc;
++
++ gctUINT32 numCommits;
++ gctUINT32 drawPointCount;
++ gctUINT32 drawLineCount;
++ gctUINT32 drawTriangleCount;
++ gctUINT32 drawVertexCount;
++ gctUINT32 redundantStateChangeCalls;
++#endif
++
++ gctUINT32 prevVSInstCount;
++ gctUINT32 prevVSBranchInstCount;
++ gctUINT32 prevVSTexInstCount;
++ gctUINT32 prevVSVertexCount;
++ gctUINT32 prevPSInstCount;
++ gctUINT32 prevPSBranchInstCount;
++ gctUINT32 prevPSTexInstCount;
++ gctUINT32 prevPSPixelCount;
++
++ char* psSource;
++ char* vsSource;
++
++}
++gcsPROFILER;
++
++/* Memory profile information. */
++struct _gcsMemProfile
++{
++ /* Memory Usage */
++ gctUINT32 videoMemUsed;
++ gctUINT32 systemMemUsed;
++ gctUINT32 commitBufferSize;
++ gctUINT32 contextBufferCopyBytes;
++};
++
++/* Shader profile information. */
++struct _gcsSHADER_PROFILER
++{
++ gctUINT32 shaderLength;
++ gctUINT32 shaderALUCycles;
++ gctUINT32 shaderTexLoadCycles;
++ gctUINT32 shaderTempRegCount;
++ gctUINT32 shaderSamplerRegCount;
++ gctUINT32 shaderInputRegCount;
++ gctUINT32 shaderOutputRegCount;
++};
++
++/* Initialize the gcsProfiler. */
++gceSTATUS
++gcoPROFILER_Initialize(
++ IN gcoHAL Hal
++ );
++
++/* Destroy the gcProfiler. */
++gceSTATUS
++gcoPROFILER_Destroy(
++ IN gcoHAL Hal
++ );
++
++/* Write data to profiler. */
++gceSTATUS
++gcoPROFILER_Write(
++ IN gcoHAL Hal,
++ IN gctSIZE_T ByteCount,
++ IN gctCONST_POINTER Data
++ );
++
++/* Flush data out. */
++gceSTATUS
++gcoPROFILER_Flush(
++ IN gcoHAL Hal
++ );
++
++/* Call to signal end of frame. */
++gceSTATUS
++gcoPROFILER_EndFrame(
++ IN gcoHAL Hal
++ );
++
++/* Call to signal end of draw. */
++gceSTATUS
++gcoPROFILER_EndDraw(
++ IN gcoHAL Hal,
++ IN gctBOOL FirstDraw
++ );
++
++/* Increase profile counter Enum by Value. */
++gceSTATUS
++gcoPROFILER_Count(
++ IN gcoHAL Hal,
++ IN gctUINT32 Enum,
++ IN gctINT Value
++ );
++
++gceSTATUS
++gcoPROFILER_ShaderSourceFS(
++ IN gcoHAL Hal,
++ IN char* source
++ );
++
++gceSTATUS
++gcoPROFILER_ShaderSourceVS(
++ IN gcoHAL Hal,
++ IN char* source
++ );
++
++/* Profile input vertex shader. */
++gceSTATUS
++gcoPROFILER_ShaderVS(
++ IN gcoHAL Hal,
++ IN gctPOINTER Vs
++ );
++
++/* Profile input fragment shader. */
++gceSTATUS
++gcoPROFILER_ShaderFS(
++ IN gcoHAL Hal,
++ IN gctPOINTER Fs
++ );
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __gc_hal_profiler_h_ */
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_raster.h linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_raster.h
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_raster.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_raster.h 2015-07-27 23:13:06.218794344 +0200
+@@ -0,0 +1,1010 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_raster_h_
++#define __gc_hal_raster_h_
++
++#include "gc_hal_enum.h"
++#include "gc_hal_types.h"
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/******************************************************************************\
++****************************** Object Declarations *****************************
++\******************************************************************************/
++
++typedef struct _gcoBRUSH * gcoBRUSH;
++typedef struct _gcoBRUSH_CACHE * gcoBRUSH_CACHE;
++
++/******************************************************************************\
++******************************** gcoBRUSH Object *******************************
++\******************************************************************************/
++
++/* Create a new solid color gcoBRUSH object. */
++gceSTATUS
++gcoBRUSH_ConstructSingleColor(
++ IN gcoHAL Hal,
++ IN gctUINT32 ColorConvert,
++ IN gctUINT32 Color,
++ IN gctUINT64 Mask,
++ gcoBRUSH * Brush
++ );
++
++/* Create a new monochrome gcoBRUSH object. */
++gceSTATUS
++gcoBRUSH_ConstructMonochrome(
++ IN gcoHAL Hal,
++ IN gctUINT32 OriginX,
++ IN gctUINT32 OriginY,
++ IN gctUINT32 ColorConvert,
++ IN gctUINT32 FgColor,
++ IN gctUINT32 BgColor,
++ IN gctUINT64 Bits,
++ IN gctUINT64 Mask,
++ gcoBRUSH * Brush
++ );
++
++/* Create a color gcoBRUSH object. */
++gceSTATUS
++gcoBRUSH_ConstructColor(
++ IN gcoHAL Hal,
++ IN gctUINT32 OriginX,
++ IN gctUINT32 OriginY,
++ IN gctPOINTER Address,
++ IN gceSURF_FORMAT Format,
++ IN gctUINT64 Mask,
++ gcoBRUSH * Brush
++ );
++
++/* Destroy an gcoBRUSH object. */
++gceSTATUS
++gcoBRUSH_Destroy(
++ IN gcoBRUSH Brush
++ );
++
++/******************************************************************************\
++******************************** gcoSURF Object *******************************
++\******************************************************************************/
++
++/* Set cipping rectangle. */
++gceSTATUS
++gcoSURF_SetClipping(
++ IN gcoSURF Surface
++ );
++
++/* Clear one or more rectangular areas. */
++gceSTATUS
++gcoSURF_Clear2D(
++ IN gcoSURF DestSurface,
++ IN gctUINT32 RectCount,
++ IN gcsRECT_PTR DestRect,
++ IN gctUINT32 LoColor,
++ IN gctUINT32 HiColor
++ );
++
++/* Draw one or more Bresenham lines. */
++gceSTATUS
++gcoSURF_Line(
++ IN gcoSURF Surface,
++ IN gctUINT32 LineCount,
++ IN gcsRECT_PTR Position,
++ IN gcoBRUSH Brush,
++ IN gctUINT8 FgRop,
++ IN gctUINT8 BgRop
++ );
++
++/* Generic rectangular blit. */
++gceSTATUS
++gcoSURF_Blit(
++ IN OPTIONAL gcoSURF SrcSurface,
++ IN gcoSURF DestSurface,
++ IN gctUINT32 RectCount,
++ IN OPTIONAL gcsRECT_PTR SrcRect,
++ IN gcsRECT_PTR DestRect,
++ IN OPTIONAL gcoBRUSH Brush,
++ IN gctUINT8 FgRop,
++ IN gctUINT8 BgRop,
++ IN OPTIONAL gceSURF_TRANSPARENCY Transparency,
++ IN OPTIONAL gctUINT32 TransparencyColor,
++ IN OPTIONAL gctPOINTER Mask,
++ IN OPTIONAL gceSURF_MONOPACK MaskPack
++ );
++
++/* Monochrome blit. */
++gceSTATUS
++gcoSURF_MonoBlit(
++ IN gcoSURF DestSurface,
++ IN gctPOINTER Source,
++ IN gceSURF_MONOPACK SourcePack,
++ IN gcsPOINT_PTR SourceSize,
++ IN gcsPOINT_PTR SourceOrigin,
++ IN gcsRECT_PTR DestRect,
++ IN OPTIONAL gcoBRUSH Brush,
++ IN gctUINT8 FgRop,
++ IN gctUINT8 BgRop,
++ IN gctBOOL ColorConvert,
++ IN gctUINT8 MonoTransparency,
++ IN gceSURF_TRANSPARENCY Transparency,
++ IN gctUINT32 FgColor,
++ IN gctUINT32 BgColor
++ );
++
++/* Filter blit. */
++gceSTATUS
++gcoSURF_FilterBlit(
++ IN gcoSURF SrcSurface,
++ IN gcoSURF DestSurface,
++ IN gcsRECT_PTR SrcRect,
++ IN gcsRECT_PTR DestRect,
++ IN gcsRECT_PTR DestSubRect
++ );
++
++/* Enable alpha blending engine in the hardware and disengage the ROP engine. */
++gceSTATUS
++gcoSURF_EnableAlphaBlend(
++ IN gcoSURF Surface,
++ IN gctUINT8 SrcGlobalAlphaValue,
++ IN gctUINT8 DstGlobalAlphaValue,
++ IN gceSURF_PIXEL_ALPHA_MODE SrcAlphaMode,
++ IN gceSURF_PIXEL_ALPHA_MODE DstAlphaMode,
++ IN gceSURF_GLOBAL_ALPHA_MODE SrcGlobalAlphaMode,
++ IN gceSURF_GLOBAL_ALPHA_MODE DstGlobalAlphaMode,
++ IN gceSURF_BLEND_FACTOR_MODE SrcFactorMode,
++ IN gceSURF_BLEND_FACTOR_MODE DstFactorMode,
++ IN gceSURF_PIXEL_COLOR_MODE SrcColorMode,
++ IN gceSURF_PIXEL_COLOR_MODE DstColorMode
++ );
++
++/* Disable alpha blending engine in the hardware and engage the ROP engine. */
++gceSTATUS
++gcoSURF_DisableAlphaBlend(
++ IN gcoSURF Surface
++ );
++
++/* Copy a rectangular area with format conversion. */
++gceSTATUS
++gcoSURF_CopyPixels(
++ IN gcoSURF Source,
++ IN gcoSURF Target,
++ IN gctINT SourceX,
++ IN gctINT SourceY,
++ IN gctINT TargetX,
++ IN gctINT TargetY,
++ IN gctINT Width,
++ IN gctINT Height
++ );
++
++/* Read surface pixel. */
++gceSTATUS
++gcoSURF_ReadPixel(
++ IN gcoSURF Surface,
++ IN gctPOINTER Memory,
++ IN gctINT X,
++ IN gctINT Y,
++ IN gceSURF_FORMAT Format,
++ OUT gctPOINTER PixelValue
++ );
++
++/* Write surface pixel. */
++gceSTATUS
++gcoSURF_WritePixel(
++ IN gcoSURF Surface,
++ IN gctPOINTER Memory,
++ IN gctINT X,
++ IN gctINT Y,
++ IN gceSURF_FORMAT Format,
++ IN gctPOINTER PixelValue
++ );
++
++gceSTATUS
++gcoSURF_SetDither(
++ IN gcoSURF Surface,
++ IN gctBOOL Dither
++ );
++/******************************************************************************\
++********************************** gco2D Object *********************************
++\******************************************************************************/
++
++/* Construct a new gco2D object. */
++gceSTATUS
++gco2D_Construct(
++ IN gcoHAL Hal,
++ OUT gco2D * Hardware
++ );
++
++/* Destroy an gco2D object. */
++gceSTATUS
++gco2D_Destroy(
++ IN gco2D Hardware
++ );
++
++/* Sets the maximum number of brushes in the brush cache. */
++gceSTATUS
++gco2D_SetBrushLimit(
++ IN gco2D Hardware,
++ IN gctUINT MaxCount
++ );
++
++/* Flush the brush. */
++gceSTATUS
++gco2D_FlushBrush(
++ IN gco2D Engine,
++ IN gcoBRUSH Brush,
++ IN gceSURF_FORMAT Format
++ );
++
++/* Program the specified solid color brush. */
++gceSTATUS
++gco2D_LoadSolidBrush(
++ IN gco2D Engine,
++ IN gceSURF_FORMAT Format,
++ IN gctUINT32 ColorConvert,
++ IN gctUINT32 Color,
++ IN gctUINT64 Mask
++ );
++
++gceSTATUS
++gco2D_LoadMonochromeBrush(
++ IN gco2D Engine,
++ IN gctUINT32 OriginX,
++ IN gctUINT32 OriginY,
++ IN gctUINT32 ColorConvert,
++ IN gctUINT32 FgColor,
++ IN gctUINT32 BgColor,
++ IN gctUINT64 Bits,
++ IN gctUINT64 Mask
++ );
++
++gceSTATUS
++gco2D_LoadColorBrush(
++ IN gco2D Engine,
++ IN gctUINT32 OriginX,
++ IN gctUINT32 OriginY,
++ IN gctUINT32 Address,
++ IN gceSURF_FORMAT Format,
++ IN gctUINT64 Mask
++ );
++
++/* Configure monochrome source. */
++gceSTATUS
++gco2D_SetMonochromeSource(
++ IN gco2D Engine,
++ IN gctBOOL ColorConvert,
++ IN gctUINT8 MonoTransparency,
++ IN gceSURF_MONOPACK DataPack,
++ IN gctBOOL CoordRelative,
++ IN gceSURF_TRANSPARENCY Transparency,
++ IN gctUINT32 FgColor,
++ IN gctUINT32 BgColor
++ );
++
++/* Configure color source. */
++gceSTATUS
++gco2D_SetColorSource(
++ IN gco2D Engine,
++ IN gctUINT32 Address,
++ IN gctUINT32 Stride,
++ IN gceSURF_FORMAT Format,
++ IN gceSURF_ROTATION Rotation,
++ IN gctUINT32 SurfaceWidth,
++ IN gctBOOL CoordRelative,
++ IN gceSURF_TRANSPARENCY Transparency,
++ IN gctUINT32 TransparencyColor
++ );
++
++/* Configure color source extension for full rotation. */
++gceSTATUS
++gco2D_SetColorSourceEx(
++ IN gco2D Engine,
++ IN gctUINT32 Address,
++ IN gctUINT32 Stride,
++ IN gceSURF_FORMAT Format,
++ IN gceSURF_ROTATION Rotation,
++ IN gctUINT32 SurfaceWidth,
++ IN gctUINT32 SurfaceHeight,
++ IN gctBOOL CoordRelative,
++ IN gceSURF_TRANSPARENCY Transparency,
++ IN gctUINT32 TransparencyColor
++ );
++
++/* Configure color source. */
++gceSTATUS
++gco2D_SetColorSourceAdvanced(
++ IN gco2D Engine,
++ IN gctUINT32 Address,
++ IN gctUINT32 Stride,
++ IN gceSURF_FORMAT Format,
++ IN gceSURF_ROTATION Rotation,
++ IN gctUINT32 SurfaceWidth,
++ IN gctUINT32 SurfaceHeight,
++ IN gctBOOL CoordRelative
++ );
++
++gceSTATUS
++gco2D_SetColorSourceN(
++ IN gco2D Engine,
++ IN gctUINT32 Address,
++ IN gctUINT32 Stride,
++ IN gceSURF_FORMAT Format,
++ IN gceSURF_ROTATION Rotation,
++ IN gctUINT32 SurfaceWidth,
++ IN gctUINT32 SurfaceHeight,
++ IN gctUINT32 SurfaceNumber
++ );
++
++/* Configure masked color source. */
++gceSTATUS
++gco2D_SetMaskedSource(
++ IN gco2D Engine,
++ IN gctUINT32 Address,
++ IN gctUINT32 Stride,
++ IN gceSURF_FORMAT Format,
++ IN gctBOOL CoordRelative,
++ IN gceSURF_MONOPACK MaskPack
++ );
++
++/* Configure masked color source extension for full rotation. */
++gceSTATUS
++gco2D_SetMaskedSourceEx(
++ IN gco2D Engine,
++ IN gctUINT32 Address,
++ IN gctUINT32 Stride,
++ IN gceSURF_FORMAT Format,
++ IN gctBOOL CoordRelative,
++ IN gceSURF_MONOPACK MaskPack,
++ IN gceSURF_ROTATION Rotation,
++ IN gctUINT32 SurfaceWidth,
++ IN gctUINT32 SurfaceHeight
++ );
++
++/* Setup the source rectangle. */
++gceSTATUS
++gco2D_SetSource(
++ IN gco2D Engine,
++ IN gcsRECT_PTR SrcRect
++ );
++
++/* Set clipping rectangle. */
++gceSTATUS
++gco2D_SetClipping(
++ IN gco2D Engine,
++ IN gcsRECT_PTR Rect
++ );
++
++/* Configure destination. */
++gceSTATUS
++gco2D_SetTarget(
++ IN gco2D Engine,
++ IN gctUINT32 Address,
++ IN gctUINT32 Stride,
++ IN gceSURF_ROTATION Rotation,
++ IN gctUINT32 SurfaceWidth
++ );
++
++/* Configure destination extension for full rotation. */
++gceSTATUS
++gco2D_SetTargetEx(
++ IN gco2D Engine,
++ IN gctUINT32 Address,
++ IN gctUINT32 Stride,
++ IN gceSURF_ROTATION Rotation,
++ IN gctUINT32 SurfaceWidth,
++ IN gctUINT32 SurfaceHeight
++ );
++
++/* Calculate and program the stretch factors. */
++gceSTATUS
++gco2D_CalcStretchFactor(
++ IN gco2D Engine,
++ IN gctINT32 SrcSize,
++ IN gctINT32 DestSize,
++ OUT gctUINT32_PTR Factor
++ );
++
++gceSTATUS
++gco2D_SetStretchFactors(
++ IN gco2D Engine,
++ IN gctUINT32 HorFactor,
++ IN gctUINT32 VerFactor
++ );
++
++/* Calculate and program the stretch factors based on the rectangles. */
++gceSTATUS
++gco2D_SetStretchRectFactors(
++ IN gco2D Engine,
++ IN gcsRECT_PTR SrcRect,
++ IN gcsRECT_PTR DestRect
++ );
++
++/* Create a new solid color gcoBRUSH object. */
++gceSTATUS
++gco2D_ConstructSingleColorBrush(
++ IN gco2D Engine,
++ IN gctUINT32 ColorConvert,
++ IN gctUINT32 Color,
++ IN gctUINT64 Mask,
++ gcoBRUSH * Brush
++ );
++
++/* Create a new monochrome gcoBRUSH object. */
++gceSTATUS
++gco2D_ConstructMonochromeBrush(
++ IN gco2D Engine,
++ IN gctUINT32 OriginX,
++ IN gctUINT32 OriginY,
++ IN gctUINT32 ColorConvert,
++ IN gctUINT32 FgColor,
++ IN gctUINT32 BgColor,
++ IN gctUINT64 Bits,
++ IN gctUINT64 Mask,
++ gcoBRUSH * Brush
++ );
++
++/* Create a color gcoBRUSH object. */
++gceSTATUS
++gco2D_ConstructColorBrush(
++ IN gco2D Engine,
++ IN gctUINT32 OriginX,
++ IN gctUINT32 OriginY,
++ IN gctPOINTER Address,
++ IN gceSURF_FORMAT Format,
++ IN gctUINT64 Mask,
++ gcoBRUSH * Brush
++ );
++
++/* Clear one or more rectangular areas. */
++gceSTATUS
++gco2D_Clear(
++ IN gco2D Engine,
++ IN gctUINT32 RectCount,
++ IN gcsRECT_PTR Rect,
++ IN gctUINT32 Color32,
++ IN gctUINT8 FgRop,
++ IN gctUINT8 BgRop,
++ IN gceSURF_FORMAT DestFormat
++ );
++
++/* Draw one or more Bresenham lines. */
++gceSTATUS
++gco2D_Line(
++ IN gco2D Engine,
++ IN gctUINT32 LineCount,
++ IN gcsRECT_PTR Position,
++ IN gcoBRUSH Brush,
++ IN gctUINT8 FgRop,
++ IN gctUINT8 BgRop,
++ IN gceSURF_FORMAT DestFormat
++ );
++
++/* Draw one or more Bresenham lines based on the 32-bit color. */
++gceSTATUS
++gco2D_ColorLine(
++ IN gco2D Engine,
++ IN gctUINT32 LineCount,
++ IN gcsRECT_PTR Position,
++ IN gctUINT32 Color32,
++ IN gctUINT8 FgRop,
++ IN gctUINT8 BgRop,
++ IN gceSURF_FORMAT DestFormat
++ );
++
++/* Generic blit. */
++gceSTATUS
++gco2D_Blit(
++ IN gco2D Engine,
++ IN gctUINT32 RectCount,
++ IN gcsRECT_PTR Rect,
++ IN gctUINT8 FgRop,
++ IN gctUINT8 BgRop,
++ IN gceSURF_FORMAT DestFormat
++ );
++
++gceSTATUS
++gco2D_Blend(
++ IN gco2D Engine,
++ IN gctUINT32 SrcCount,
++ IN gctUINT32 RectCount,
++ IN gcsRECT_PTR Rect,
++ IN gctUINT8 FgRop,
++ IN gctUINT8 BgRop,
++ IN gceSURF_FORMAT DestFormat
++ );
++
++/* Batch blit. */
++gceSTATUS
++gco2D_BatchBlit(
++ IN gco2D Engine,
++ IN gctUINT32 RectCount,
++ IN gcsRECT_PTR SrcRect,
++ IN gcsRECT_PTR DestRect,
++ IN gctUINT8 FgRop,
++ IN gctUINT8 BgRop,
++ IN gceSURF_FORMAT DestFormat
++ );
++
++/* Stretch blit. */
++gceSTATUS
++gco2D_StretchBlit(
++ IN gco2D Engine,
++ IN gctUINT32 RectCount,
++ IN gcsRECT_PTR Rect,
++ IN gctUINT8 FgRop,
++ IN gctUINT8 BgRop,
++ IN gceSURF_FORMAT DestFormat
++ );
++
++/* Monochrome blit. */
++gceSTATUS
++gco2D_MonoBlit(
++ IN gco2D Engine,
++ IN gctPOINTER StreamBits,
++ IN gcsPOINT_PTR StreamSize,
++ IN gcsRECT_PTR StreamRect,
++ IN gceSURF_MONOPACK SrcStreamPack,
++ IN gceSURF_MONOPACK DestStreamPack,
++ IN gcsRECT_PTR DestRect,
++ IN gctUINT32 FgRop,
++ IN gctUINT32 BgRop,
++ IN gceSURF_FORMAT DestFormat
++ );
++
++gceSTATUS
++gco2D_MonoBlitEx(
++ IN gco2D Engine,
++ IN gctPOINTER StreamBits,
++ IN gctINT32 StreamStride,
++ IN gctINT32 StreamWidth,
++ IN gctINT32 StreamHeight,
++ IN gctINT32 StreamX,
++ IN gctINT32 StreamY,
++ IN gctUINT32 FgColor,
++ IN gctUINT32 BgColor,
++ IN gcsRECT_PTR SrcRect,
++ IN gcsRECT_PTR DstRect,
++ IN gctUINT8 FgRop,
++ IN gctUINT8 BgRop
++ );
++
++/* Set kernel size. */
++gceSTATUS
++gco2D_SetKernelSize(
++ IN gco2D Engine,
++ IN gctUINT8 HorKernelSize,
++ IN gctUINT8 VerKernelSize
++ );
++
++/* Set filter type. */
++gceSTATUS
++gco2D_SetFilterType(
++ IN gco2D Engine,
++ IN gceFILTER_TYPE FilterType
++ );
++
++/* Set the filter kernel by user. */
++gceSTATUS
++gco2D_SetUserFilterKernel(
++ IN gco2D Engine,
++ IN gceFILTER_PASS_TYPE PassType,
++ IN gctUINT16_PTR KernelArray
++ );
++
++/* Select the pass(es) to be done for user defined filter. */
++gceSTATUS
++gco2D_EnableUserFilterPasses(
++ IN gco2D Engine,
++ IN gctBOOL HorPass,
++ IN gctBOOL VerPass
++ );
++
++/* Frees the temporary buffer allocated by filter blit operation. */
++gceSTATUS
++gco2D_FreeFilterBuffer(
++ IN gco2D Engine
++ );
++
++/* Filter blit. */
++gceSTATUS
++gco2D_FilterBlit(
++ IN gco2D Engine,
++ IN gctUINT32 SrcAddress,
++ IN gctUINT SrcStride,
++ IN gctUINT32 SrcUAddress,
++ IN gctUINT SrcUStride,
++ IN gctUINT32 SrcVAddress,
++ IN gctUINT SrcVStride,
++ IN gceSURF_FORMAT SrcFormat,
++ IN gceSURF_ROTATION SrcRotation,
++ IN gctUINT32 SrcSurfaceWidth,
++ IN gcsRECT_PTR SrcRect,
++ IN gctUINT32 DestAddress,
++ IN gctUINT DestStride,
++ IN gceSURF_FORMAT DestFormat,
++ IN gceSURF_ROTATION DestRotation,
++ IN gctUINT32 DestSurfaceWidth,
++ IN gcsRECT_PTR DestRect,
++ IN gcsRECT_PTR DestSubRect
++ );
++
++/* Filter blit extension for full rotation. */
++gceSTATUS
++gco2D_FilterBlitEx(
++ IN gco2D Engine,
++ IN gctUINT32 SrcAddress,
++ IN gctUINT SrcStride,
++ IN gctUINT32 SrcUAddress,
++ IN gctUINT SrcUStride,
++ IN gctUINT32 SrcVAddress,
++ IN gctUINT SrcVStride,
++ IN gceSURF_FORMAT SrcFormat,
++ IN gceSURF_ROTATION SrcRotation,
++ IN gctUINT32 SrcSurfaceWidth,
++ IN gctUINT32 SrcSurfaceHeight,
++ IN gcsRECT_PTR SrcRect,
++ IN gctUINT32 DestAddress,
++ IN gctUINT DestStride,
++ IN gceSURF_FORMAT DestFormat,
++ IN gceSURF_ROTATION DestRotation,
++ IN gctUINT32 DestSurfaceWidth,
++ IN gctUINT32 DestSurfaceHeight,
++ IN gcsRECT_PTR DestRect,
++ IN gcsRECT_PTR DestSubRect
++ );
++
++gceSTATUS
++gco2D_FilterBlitEx2(
++ IN gco2D Engine,
++ IN gctUINT32_PTR SrcAddresses,
++ IN gctUINT32 SrcAddressNum,
++ IN gctUINT32_PTR SrcStrides,
++ IN gctUINT32 SrcStrideNum,
++ IN gceTILING SrcTiling,
++ IN gceSURF_FORMAT SrcFormat,
++ IN gceSURF_ROTATION SrcRotation,
++ IN gctUINT32 SrcSurfaceWidth,
++ IN gctUINT32 SrcSurfaceHeight,
++ IN gcsRECT_PTR SrcRect,
++ IN gctUINT32_PTR DestAddresses,
++ IN gctUINT32 DestAddressNum,
++ IN gctUINT32_PTR DestStrides,
++ IN gctUINT32 DestStrideNum,
++ IN gceTILING DestTiling,
++ IN gceSURF_FORMAT DestFormat,
++ IN gceSURF_ROTATION DestRotation,
++ IN gctUINT32 DestSurfaceWidth,
++ IN gctUINT32 DestSurfaceHeight,
++ IN gcsRECT_PTR DestRect,
++ IN gcsRECT_PTR DestSubRect
++ );
++
++/* Enable alpha blending engine in the hardware and disengage the ROP engine. */
++gceSTATUS
++gco2D_EnableAlphaBlend(
++ IN gco2D Engine,
++ IN gctUINT8 SrcGlobalAlphaValue,
++ IN gctUINT8 DstGlobalAlphaValue,
++ IN gceSURF_PIXEL_ALPHA_MODE SrcAlphaMode,
++ IN gceSURF_PIXEL_ALPHA_MODE DstAlphaMode,
++ IN gceSURF_GLOBAL_ALPHA_MODE SrcGlobalAlphaMode,
++ IN gceSURF_GLOBAL_ALPHA_MODE DstGlobalAlphaMode,
++ IN gceSURF_BLEND_FACTOR_MODE SrcFactorMode,
++ IN gceSURF_BLEND_FACTOR_MODE DstFactorMode,
++ IN gceSURF_PIXEL_COLOR_MODE SrcColorMode,
++ IN gceSURF_PIXEL_COLOR_MODE DstColorMode
++ );
++
++/* Enable alpha blending engine in the hardware. */
++gceSTATUS
++gco2D_EnableAlphaBlendAdvanced(
++ IN gco2D Engine,
++ IN gceSURF_PIXEL_ALPHA_MODE SrcAlphaMode,
++ IN gceSURF_PIXEL_ALPHA_MODE DstAlphaMode,
++ IN gceSURF_GLOBAL_ALPHA_MODE SrcGlobalAlphaMode,
++ IN gceSURF_GLOBAL_ALPHA_MODE DstGlobalAlphaMode,
++ IN gceSURF_BLEND_FACTOR_MODE SrcFactorMode,
++ IN gceSURF_BLEND_FACTOR_MODE DstFactorMode
++ );
++
++/* Enable alpha blending engine with Porter Duff rule. */
++gceSTATUS
++gco2D_SetPorterDuffBlending(
++ IN gco2D Engine,
++ IN gce2D_PORTER_DUFF_RULE Rule
++ );
++
++/* Disable alpha blending engine in the hardware and engage the ROP engine. */
++gceSTATUS
++gco2D_DisableAlphaBlend(
++ IN gco2D Engine
++ );
++
++/* Retrieve the maximum number of 32-bit data chunks for a single DE command. */
++gctUINT32
++gco2D_GetMaximumDataCount(
++ void
++ );
++
++/* Retrieve the maximum number of rectangles, that can be passed in a single DE command. */
++gctUINT32
++gco2D_GetMaximumRectCount(
++ void
++ );
++
++/* Returns the pixel alignment of the surface. */
++gceSTATUS
++gco2D_GetPixelAlignment(
++ gceSURF_FORMAT Format,
++ gcsPOINT_PTR Alignment
++ );
++
++/* Retrieve monochrome stream pack size. */
++gceSTATUS
++gco2D_GetPackSize(
++ IN gceSURF_MONOPACK StreamPack,
++ OUT gctUINT32 * PackWidth,
++ OUT gctUINT32 * PackHeight
++ );
++
++/* Flush the 2D pipeline. */
++gceSTATUS
++gco2D_Flush(
++ IN gco2D Engine
++ );
++
++/* Load 256-entry color table for INDEX8 source surfaces. */
++gceSTATUS
++gco2D_LoadPalette(
++ IN gco2D Engine,
++ IN gctUINT FirstIndex,
++ IN gctUINT IndexCount,
++ IN gctPOINTER ColorTable,
++ IN gctBOOL ColorConvert
++ );
++
++/* Enable/disable 2D BitBlt mirrorring. */
++gceSTATUS
++gco2D_SetBitBlitMirror(
++ IN gco2D Engine,
++ IN gctBOOL HorizontalMirror,
++ IN gctBOOL VerticalMirror
++ );
++
++/*
++ * Set the transparency for source, destination and pattern.
++ * It also enable or disable the DFB color key mode.
++ */
++gceSTATUS
++gco2D_SetTransparencyAdvancedEx(
++ IN gco2D Engine,
++ IN gce2D_TRANSPARENCY SrcTransparency,
++ IN gce2D_TRANSPARENCY DstTransparency,
++ IN gce2D_TRANSPARENCY PatTransparency,
++ IN gctBOOL EnableDFBColorKeyMode
++ );
++
++/* Set the transparency for source, destination and pattern. */
++gceSTATUS
++gco2D_SetTransparencyAdvanced(
++ IN gco2D Engine,
++ IN gce2D_TRANSPARENCY SrcTransparency,
++ IN gce2D_TRANSPARENCY DstTransparency,
++ IN gce2D_TRANSPARENCY PatTransparency
++ );
++
++/* Set the source color key. */
++gceSTATUS
++gco2D_SetSourceColorKeyAdvanced(
++ IN gco2D Engine,
++ IN gctUINT32 ColorKey
++ );
++
++/* Set the source color key range. */
++gceSTATUS
++gco2D_SetSourceColorKeyRangeAdvanced(
++ IN gco2D Engine,
++ IN gctUINT32 ColorKeyLow,
++ IN gctUINT32 ColorKeyHigh
++ );
++
++/* Set the target color key. */
++gceSTATUS
++gco2D_SetTargetColorKeyAdvanced(
++ IN gco2D Engine,
++ IN gctUINT32 ColorKey
++ );
++
++/* Set the target color key range. */
++gceSTATUS
++gco2D_SetTargetColorKeyRangeAdvanced(
++ IN gco2D Engine,
++ IN gctUINT32 ColorKeyLow,
++ IN gctUINT32 ColorKeyHigh
++ );
++
++/* Set the YUV color space mode. */
++gceSTATUS
++gco2D_SetYUVColorMode(
++ IN gco2D Engine,
++ IN gce2D_YUV_COLOR_MODE Mode
++ );
++
++/* Setup the source global color value in ARGB8 format. */
++gceSTATUS gco2D_SetSourceGlobalColorAdvanced(
++ IN gco2D Engine,
++ IN gctUINT32 Color32
++ );
++
++/* Setup the target global color value in ARGB8 format. */
++gceSTATUS gco2D_SetTargetGlobalColorAdvanced(
++ IN gco2D Engine,
++ IN gctUINT32 Color32
++ );
++
++/* Setup the source and target pixel multiply modes. */
++gceSTATUS
++gco2D_SetPixelMultiplyModeAdvanced(
++ IN gco2D Engine,
++ IN gce2D_PIXEL_COLOR_MULTIPLY_MODE SrcPremultiplySrcAlpha,
++ IN gce2D_PIXEL_COLOR_MULTIPLY_MODE DstPremultiplyDstAlpha,
++ IN gce2D_GLOBAL_COLOR_MULTIPLY_MODE SrcPremultiplyGlobalMode,
++ IN gce2D_PIXEL_COLOR_MULTIPLY_MODE DstDemultiplyDstAlpha
++ );
++
++/* Set the GPU clock cycles after which the idle engine will keep auto-flushing. */
++gceSTATUS
++gco2D_SetAutoFlushCycles(
++ IN gco2D Engine,
++ IN gctUINT32 Cycles
++ );
++
++#if VIVANTE_PROFILER
++/* Read the profile registers available in the 2D engine and sets them in the profile.
++ The function will also reset the pixelsRendered counter every time.
++*/
++gceSTATUS
++gco2D_ProfileEngine(
++ IN gco2D Engine,
++ OPTIONAL gcs2D_PROFILE_PTR Profile
++ );
++#endif
++
++/* Enable or disable 2D dithering. */
++gceSTATUS
++gco2D_EnableDither(
++ IN gco2D Engine,
++ IN gctBOOL Enable
++ );
++
++gceSTATUS
++gco2D_SetGenericSource(
++ IN gco2D Engine,
++ IN gctUINT32_PTR Addresses,
++ IN gctUINT32 AddressNum,
++ IN gctUINT32_PTR Strides,
++ IN gctUINT32 StrideNum,
++ IN gceTILING Tiling,
++ IN gceSURF_FORMAT Format,
++ IN gceSURF_ROTATION Rotation,
++ IN gctUINT32 SurfaceWidth,
++ IN gctUINT32 SurfaceHeight
++);
++
++gceSTATUS
++gco2D_SetGenericTarget(
++ IN gco2D Engine,
++ IN gctUINT32_PTR Addresses,
++ IN gctUINT32 AddressNum,
++ IN gctUINT32_PTR Strides,
++ IN gctUINT32 StrideNum,
++ IN gceTILING Tiling,
++ IN gceSURF_FORMAT Format,
++ IN gceSURF_ROTATION Rotation,
++ IN gctUINT32 SurfaceWidth,
++ IN gctUINT32 SurfaceHeight
++);
++
++gceSTATUS
++gco2D_SetCurrentSourceIndex(
++ IN gco2D Engine,
++ IN gctUINT32 SrcIndex
++ );
++
++gceSTATUS
++gco2D_MultiSourceBlit(
++ IN gco2D Engine,
++ IN gctUINT32 SourceMask,
++ IN gcsRECT_PTR DestRect,
++ IN gctUINT32 RectCount
++ );
++
++gceSTATUS
++gco2D_SetROP(
++ IN gco2D Engine,
++ IN gctUINT8 FgRop,
++ IN gctUINT8 BgRop
++ );
++
++gceSTATUS
++gco2D_SetGdiStretchMode(
++ IN gco2D Engine,
++ IN gctBOOL Enable
++ );
++
++gceSTATUS
++gco2D_SetSourceTileStatus(
++ IN gco2D Engine,
++ IN gce2D_TILE_STATUS_CONFIG TSControl,
++ IN gceSURF_FORMAT CompressedFormat,
++ IN gctUINT32 ClearValue,
++ IN gctUINT32 GpuAddress
++ );
++
++gceSTATUS
++gco2D_SetTargetTileStatus(
++ IN gco2D Engine,
++ IN gce2D_TILE_STATUS_CONFIG TileStatusConfig,
++ IN gceSURF_FORMAT CompressedFormat,
++ IN gctUINT32 ClearValue,
++ IN gctUINT32 GpuAddress
++ );
++
++gceSTATUS
++gco2D_QueryU32(
++ IN gco2D Engine,
++ IN gce2D_QUERY Item,
++ OUT gctUINT32_PTR Value
++ );
++
++gceSTATUS
++gco2D_SetStateU32(
++ IN gco2D Engine,
++ IN gce2D_STATE State,
++ IN gctUINT32 Value
++ );
++
++gceSTATUS
++gco2D_SetStateArrayI32(
++ IN gco2D Engine,
++ IN gce2D_STATE State,
++ IN gctINT32_PTR Array,
++ IN gctINT32 ArraySize
++ );
++
++gceSTATUS
++gco2D_SetStateArrayU32(
++ IN gco2D Engine,
++ IN gce2D_STATE State,
++ IN gctUINT32_PTR Array,
++ IN gctINT32 ArraySize
++ );
++
++gceSTATUS
++gco2D_SetTargetRect(
++ IN gco2D Engine,
++ IN gcsRECT_PTR Rect
++ );
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __gc_hal_raster_h_ */
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_rename.h linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_rename.h
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_rename.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_rename.h 2015-07-27 23:13:06.218794344 +0200
+@@ -0,0 +1,248 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_rename_h_
++#define __gc_hal_rename_h_
++
++
++#if defined(_HAL2D_APPENDIX)
++
++#define _HAL2D_RENAME_2(api, appendix) api ## appendix
++#define _HAL2D_RENAME_1(api, appendix) _HAL2D_RENAME_2(api, appendix)
++#define gcmHAL2D(api) _HAL2D_RENAME_1(api, _HAL2D_APPENDIX)
++
++
++#define gckOS_Construct gcmHAL2D(gckOS_Construct)
++#define gckOS_Destroy gcmHAL2D(gckOS_Destroy)
++#define gckOS_QueryVideoMemory gcmHAL2D(gckOS_QueryVideoMemory)
++#define gckOS_Allocate gcmHAL2D(gckOS_Allocate)
++#define gckOS_Free gcmHAL2D(gckOS_Free)
++#define gckOS_AllocateMemory gcmHAL2D(gckOS_AllocateMemory)
++#define gckOS_FreeMemory gcmHAL2D(gckOS_FreeMemory)
++#define gckOS_AllocatePagedMemory gcmHAL2D(gckOS_AllocatePagedMemory)
++#define gckOS_AllocatePagedMemoryEx gcmHAL2D(gckOS_AllocatePagedMemoryEx)
++#define gckOS_LockPages gcmHAL2D(gckOS_LockPages)
++#define gckOS_MapPages gcmHAL2D(gckOS_MapPages)
++#define gckOS_UnlockPages gcmHAL2D(gckOS_UnlockPages)
++#define gckOS_FreePagedMemory gcmHAL2D(gckOS_FreePagedMemory)
++#define gckOS_AllocateNonPagedMemory gcmHAL2D(gckOS_AllocateNonPagedMemory)
++#define gckOS_FreeNonPagedMemory gcmHAL2D(gckOS_FreeNonPagedMemory)
++#define gckOS_AllocateContiguous gcmHAL2D(gckOS_AllocateContiguous)
++#define gckOS_FreeContiguous gcmHAL2D(gckOS_FreeContiguous)
++#define gckOS_GetPageSize gcmHAL2D(gckOS_GetPageSize)
++#define gckOS_GetPhysicalAddress gcmHAL2D(gckOS_GetPhysicalAddress)
++#define gckOS_GetPhysicalAddressProcess gcmHAL2D(gckOS_GetPhysicalAddressProcess)
++#define gckOS_MapPhysical gcmHAL2D(gckOS_MapPhysical)
++#define gckOS_UnmapPhysical gcmHAL2D(gckOS_UnmapPhysical)
++#define gckOS_ReadRegister gcmHAL2D(gckOS_ReadRegister)
++#define gckOS_WriteRegister gcmHAL2D(gckOS_WriteRegister)
++#define gckOS_WriteMemory gcmHAL2D(gckOS_WriteMemory)
++#define gckOS_MapMemory gcmHAL2D(gckOS_MapMemory)
++#define gckOS_UnmapMemory gcmHAL2D(gckOS_UnmapMemory)
++#define gckOS_UnmapMemoryEx gcmHAL2D(gckOS_UnmapMemoryEx)
++#define gckOS_CreateMutex gcmHAL2D(gckOS_CreateMutex)
++#define gckOS_DeleteMutex gcmHAL2D(gckOS_DeleteMutex)
++#define gckOS_AcquireMutex gcmHAL2D(gckOS_AcquireMutex)
++#define gckOS_ReleaseMutex gcmHAL2D(gckOS_ReleaseMutex)
++#define gckOS_AtomicExchange gcmHAL2D(gckOS_AtomicExchange)
++#define gckOS_AtomicExchangePtr gcmHAL2D(gckOS_AtomicExchangePtr)
++#define gckOS_AtomConstruct gcmHAL2D(gckOS_AtomConstruct)
++#define gckOS_AtomDestroy gcmHAL2D(gckOS_AtomDestroy)
++#define gckOS_AtomGet gcmHAL2D(gckOS_AtomGet)
++#define gckOS_AtomIncrement gcmHAL2D(gckOS_AtomIncrement)
++#define gckOS_AtomDecrement gcmHAL2D(gckOS_AtomDecrement)
++#define gckOS_Delay gcmHAL2D(gckOS_Delay)
++#define gckOS_GetTime gcmHAL2D(gckOS_GetTime)
++#define gckOS_MemoryBarrier gcmHAL2D(gckOS_MemoryBarrier)
++#define gckOS_MapUserPointer gcmHAL2D(gckOS_MapUserPointer)
++#define gckOS_UnmapUserPointer gcmHAL2D(gckOS_UnmapUserPointer)
++#define gckOS_QueryNeedCopy gcmHAL2D(gckOS_QueryNeedCopy)
++#define gckOS_CopyFromUserData gcmHAL2D(gckOS_CopyFromUserData)
++#define gckOS_CopyToUserData gcmHAL2D(gckOS_CopyToUserData)
++#define gckOS_MapUserPhysical gcmHAL2D(gckOS_MapUserPhysical)
++#define gckOS_SuspendInterrupt gcmHAL2D(gckOS_SuspendInterrupt)
++#define gckOS_ResumeInterrupt gcmHAL2D(gckOS_ResumeInterrupt)
++#define gckOS_GetBaseAddress gcmHAL2D(gckOS_GetBaseAddress)
++#define gckOS_MemCopy gcmHAL2D(gckOS_MemCopy)
++#define gckOS_ZeroMemory gcmHAL2D(gckOS_ZeroMemory)
++#define gckOS_DeviceControl gcmHAL2D(gckOS_DeviceControl)
++#define gckOS_GetProcessID gcmHAL2D(gckOS_GetProcessID)
++#define gckOS_GetThreadID gcmHAL2D(gckOS_GetThreadID)
++#define gckOS_CreateSignal gcmHAL2D(gckOS_CreateSignal)
++#define gckOS_DestroySignal gcmHAL2D(gckOS_DestroySignal)
++#define gckOS_Signal gcmHAL2D(gckOS_Signal)
++#define gckOS_WaitSignal gcmHAL2D(gckOS_WaitSignal)
++#define gckOS_MapSignal gcmHAL2D(gckOS_MapSignal)
++#define gckOS_MapUserMemory gcmHAL2D(gckOS_MapUserMemory)
++#define gckOS_UnmapUserMemory gcmHAL2D(gckOS_UnmapUserMemory)
++#define gckOS_CreateUserSignal gcmHAL2D(gckOS_CreateUserSignal)
++#define gckOS_DestroyUserSignal gcmHAL2D(gckOS_DestroyUserSignal)
++#define gckOS_WaitUserSignal gcmHAL2D(gckOS_WaitUserSignal)
++#define gckOS_SignalUserSignal gcmHAL2D(gckOS_SignalUserSignal)
++#define gckOS_UserSignal gcmHAL2D(gckOS_UserSignal)
++#define gckOS_UserSignal gcmHAL2D(gckOS_UserSignal)
++#define gckOS_CacheClean gcmHAL2D(gckOS_CacheClean)
++#define gckOS_CacheFlush gcmHAL2D(gckOS_CacheFlush)
++#define gckOS_SetDebugLevel gcmHAL2D(gckOS_SetDebugLevel)
++#define gckOS_SetDebugZone gcmHAL2D(gckOS_SetDebugZone)
++#define gckOS_SetDebugLevelZone gcmHAL2D(gckOS_SetDebugLevelZone)
++#define gckOS_SetDebugZones gcmHAL2D(gckOS_SetDebugZones)
++#define gckOS_SetDebugFile gcmHAL2D(gckOS_SetDebugFile)
++#define gckOS_Broadcast gcmHAL2D(gckOS_Broadcast)
++#define gckOS_SetGPUPower gcmHAL2D(gckOS_SetGPUPower)
++#define gckOS_CreateSemaphore gcmHAL2D(gckOS_CreateSemaphore)
++#define gckOS_DestroySemaphore gcmHAL2D(gckOS_DestroySemaphore)
++#define gckOS_AcquireSemaphore gcmHAL2D(gckOS_AcquireSemaphore)
++#define gckOS_ReleaseSemaphore gcmHAL2D(gckOS_ReleaseSemaphore)
++#define gckHEAP_Construct gcmHAL2D(gckHEAP_Construct)
++#define gckHEAP_Destroy gcmHAL2D(gckHEAP_Destroy)
++#define gckHEAP_Allocate gcmHAL2D(gckHEAP_Allocate)
++#define gckHEAP_Free gcmHAL2D(gckHEAP_Free)
++#define gckHEAP_ProfileStart gcmHAL2D(gckHEAP_ProfileStart)
++#define gckHEAP_ProfileEnd gcmHAL2D(gckHEAP_ProfileEnd)
++#define gckHEAP_Test gcmHAL2D(gckHEAP_Test)
++#define gckVIDMEM_Construct gcmHAL2D(gckVIDMEM_Construct)
++#define gckVIDMEM_Destroy gcmHAL2D(gckVIDMEM_Destroy)
++#define gckVIDMEM_Allocate gcmHAL2D(gckVIDMEM_Allocate)
++#define gckVIDMEM_AllocateLinear gcmHAL2D(gckVIDMEM_AllocateLinear)
++#define gckVIDMEM_Free gcmHAL2D(gckVIDMEM_Free)
++#define gckVIDMEM_Lock gcmHAL2D(gckVIDMEM_Lock)
++#define gckVIDMEM_Unlock gcmHAL2D(gckVIDMEM_Unlock)
++#define gckVIDMEM_ConstructVirtual gcmHAL2D(gckVIDMEM_ConstructVirtual)
++#define gckVIDMEM_DestroyVirtual gcmHAL2D(gckVIDMEM_DestroyVirtual)
++#define gckKERNEL_Construct gcmHAL2D(gckKERNEL_Construct)
++#define gckKERNEL_Destroy gcmHAL2D(gckKERNEL_Destroy)
++#define gckKERNEL_Dispatch gcmHAL2D(gckKERNEL_Dispatch)
++#define gckKERNEL_QueryVideoMemory gcmHAL2D(gckKERNEL_QueryVideoMemory)
++#define gckKERNEL_GetVideoMemoryPool gcmHAL2D(gckKERNEL_GetVideoMemoryPool)
++#define gckKERNEL_MapVideoMemory gcmHAL2D(gckKERNEL_MapVideoMemory)
++#define gckKERNEL_UnmapVideoMemory gcmHAL2D(gckKERNEL_UnmapVideoMemory)
++#define gckKERNEL_MapMemory gcmHAL2D(gckKERNEL_MapMemory)
++#define gckKERNEL_UnmapMemory gcmHAL2D(gckKERNEL_UnmapMemory)
++#define gckKERNEL_Notify gcmHAL2D(gckKERNEL_Notify)
++#define gckKERNEL_QuerySettings gcmHAL2D(gckKERNEL_QuerySettings)
++#define gckKERNEL_Recovery gcmHAL2D(gckKERNEL_Recovery)
++#define gckKERNEL_OpenUserData gcmHAL2D(gckKERNEL_OpenUserData)
++#define gckKERNEL_CloseUserData gcmHAL2D(gckKERNEL_CloseUserData)
++#define gckHARDWARE_Construct gcmHAL2D(gckHARDWARE_Construct)
++#define gckHARDWARE_Destroy gcmHAL2D(gckHARDWARE_Destroy)
++#define gckHARDWARE_QuerySystemMemory gcmHAL2D(gckHARDWARE_QuerySystemMemory)
++#define gckHARDWARE_BuildVirtualAddress gcmHAL2D(gckHARDWARE_BuildVirtualAddress)
++#define gckHARDWARE_QueryCommandBuffer gcmHAL2D(gckHARDWARE_QueryCommandBuffer)
++#define gckHARDWARE_WaitLink gcmHAL2D(gckHARDWARE_WaitLink)
++#define gckHARDWARE_Execute gcmHAL2D(gckHARDWARE_Execute)
++#define gckHARDWARE_End gcmHAL2D(gckHARDWARE_End)
++#define gckHARDWARE_Nop gcmHAL2D(gckHARDWARE_Nop)
++#define gckHARDWARE_Wait gcmHAL2D(gckHARDWARE_Wait)
++#define gckHARDWARE_PipeSelect gcmHAL2D(gckHARDWARE_PipeSelect)
++#define gckHARDWARE_Link gcmHAL2D(gckHARDWARE_Link)
++#define gckHARDWARE_Event gcmHAL2D(gckHARDWARE_Event)
++#define gckHARDWARE_QueryMemory gcmHAL2D(gckHARDWARE_QueryMemory)
++#define gckHARDWARE_QueryChipIdentity gcmHAL2D(gckHARDWARE_QueryChipIdentity)
++#define gckHARDWARE_QueryChipSpecs gcmHAL2D(gckHARDWARE_QueryChipSpecs)
++#define gckHARDWARE_QueryShaderCaps gcmHAL2D(gckHARDWARE_QueryShaderCaps)
++#define gckHARDWARE_ConvertFormat gcmHAL2D(gckHARDWARE_ConvertFormat)
++#define gckHARDWARE_SplitMemory gcmHAL2D(gckHARDWARE_SplitMemory)
++#define gckHARDWARE_AlignToTile gcmHAL2D(gckHARDWARE_AlignToTile)
++#define gckHARDWARE_UpdateQueueTail gcmHAL2D(gckHARDWARE_UpdateQueueTail)
++#define gckHARDWARE_ConvertLogical gcmHAL2D(gckHARDWARE_ConvertLogical)
++#define gckHARDWARE_ConvertPhysical gcmHAL2D(gckHARDWARE_ConvertPhysical)
++#define gckHARDWARE_Interrupt gcmHAL2D(gckHARDWARE_Interrupt)
++#define gckHARDWARE_SetMMU gcmHAL2D(gckHARDWARE_SetMMU)
++#define gckHARDWARE_FlushMMU gcmHAL2D(gckHARDWARE_FlushMMU)
++#define gckHARDWARE_GetIdle gcmHAL2D(gckHARDWARE_GetIdle)
++#define gckHARDWARE_Flush gcmHAL2D(gckHARDWARE_Flush)
++#define gckHARDWARE_SetFastClear gcmHAL2D(gckHARDWARE_SetFastClear)
++#define gckHARDWARE_ReadInterrupt gcmHAL2D(gckHARDWARE_ReadInterrupt)
++#define gckHARDWARE_SetPowerManagementState gcmHAL2D(gckHARDWARE_SetPowerManagementState)
++#define gckHARDWARE_QueryPowerManagementState gcmHAL2D(gckHARDWARE_QueryPowerManagementState)
++#define gckHARDWARE_ProfileEngine2D gcmHAL2D(gckHARDWARE_ProfileEngine2D)
++#define gckHARDWARE_InitializeHardware gcmHAL2D(gckHARDWARE_InitializeHardware)
++#define gckHARDWARE_Reset gcmHAL2D(gckHARDWARE_Reset)
++#define gckINTERRUPT_Construct gcmHAL2D(gckINTERRUPT_Construct)
++#define gckINTERRUPT_Destroy gcmHAL2D(gckINTERRUPT_Destroy)
++#define gckINTERRUPT_SetHandler gcmHAL2D(gckINTERRUPT_SetHandler)
++#define gckINTERRUPT_Notify gcmHAL2D(gckINTERRUPT_Notify)
++#define gckEVENT_Construct gcmHAL2D(gckEVENT_Construct)
++#define gckEVENT_Destroy gcmHAL2D(gckEVENT_Destroy)
++#define gckEVENT_AddList gcmHAL2D(gckEVENT_AddList)
++#define gckEVENT_FreeNonPagedMemory gcmHAL2D(gckEVENT_FreeNonPagedMemory)
++#define gckEVENT_FreeContiguousMemory gcmHAL2D(gckEVENT_FreeContiguousMemory)
++#define gckEVENT_FreeVideoMemory gcmHAL2D(gckEVENT_FreeVideoMemory)
++#define gckEVENT_Signal gcmHAL2D(gckEVENT_Signal)
++#define gckEVENT_Unlock gcmHAL2D(gckEVENT_Unlock)
++#define gckEVENT_Submit gcmHAL2D(gckEVENT_Submit)
++#define gckEVENT_Commit gcmHAL2D(gckEVENT_Commit)
++#define gckEVENT_Notify gcmHAL2D(gckEVENT_Notify)
++#define gckEVENT_Interrupt gcmHAL2D(gckEVENT_Interrupt)
++#define gckCOMMAND_Construct gcmHAL2D(gckCOMMAND_Construct)
++#define gckCOMMAND_Destroy gcmHAL2D(gckCOMMAND_Destroy)
++#define gckCOMMAND_EnterCommit gcmHAL2D(gckCOMMAND_EnterCommit)
++#define gckCOMMAND_ExitCommit gcmHAL2D(gckCOMMAND_ExitCommit)
++#define gckCOMMAND_Start gcmHAL2D(gckCOMMAND_Start)
++#define gckCOMMAND_Stop gcmHAL2D(gckCOMMAND_Stop)
++#define gckCOMMAND_Commit gcmHAL2D(gckCOMMAND_Commit)
++#define gckCOMMAND_Reserve gcmHAL2D(gckCOMMAND_Reserve)
++#define gckCOMMAND_Execute gcmHAL2D(gckCOMMAND_Execute)
++#define gckCOMMAND_Stall gcmHAL2D(gckCOMMAND_Stall)
++#define gckCOMMAND_Attach gcmHAL2D(gckCOMMAND_Attach)
++#define gckCOMMAND_Detach gcmHAL2D(gckCOMMAND_Detach)
++#define gckMMU_Construct gcmHAL2D(gckMMU_Construct)
++#define gckMMU_Destroy gcmHAL2D(gckMMU_Destroy)
++#define gckMMU_AllocatePages gcmHAL2D(gckMMU_AllocatePages)
++#define gckMMU_FreePages gcmHAL2D(gckMMU_FreePages)
++#define gckMMU_InsertNode gcmHAL2D(gckMMU_InsertNode)
++#define gckMMU_RemoveNode gcmHAL2D(gckMMU_RemoveNode)
++#define gckMMU_FreeHandleMemory gcmHAL2D(gckMMU_FreeHandleMemory)
++#define gckMMU_Test gcmHAL2D(gckMMU_Test)
++#define gckHARDWARE_QueryProfileRegisters gcmHAL2D(gckHARDWARE_QueryProfileRegisters)
++
++
++#define FindMdlMap gcmHAL2D(FindMdlMap)
++#define OnProcessExit gcmHAL2D(OnProcessExit)
++
++#define gckGALDEVICE_Destroy gcmHAL2D(gckGALDEVICE_Destroy)
++#define gckOS_Print gcmHAL2D(gckOS_Print)
++#define gckGALDEVICE_FreeMemory gcmHAL2D(gckGALDEVICE_FreeMemory)
++#define gckGALDEVICE_AllocateMemory gcmHAL2D(gckGALDEVICE_AllocateMemory)
++#define gckOS_DebugBreak gcmHAL2D(gckOS_DebugBreak)
++#define gckGALDEVICE_Release_ISR gcmHAL2D(gckGALDEVICE_Release_ISR)
++#define gckOS_Verify gcmHAL2D(gckOS_Verify)
++#define gckCOMMAND_Release gcmHAL2D(gckCOMMAND_Release)
++#define gckGALDEVICE_Stop gcmHAL2D(gckGALDEVICE_Stop)
++#define gckGALDEVICE_Construct gcmHAL2D(gckGALDEVICE_Construct)
++#define gckOS_DebugFatal gcmHAL2D(gckOS_DebugFatal)
++#define gckOS_DebugTrace gcmHAL2D(gckOS_DebugTrace)
++#define gckHARDWARE_GetBaseAddress gcmHAL2D(gckHARDWARE_GetBaseAddress)
++#define gckGALDEVICE_Setup_ISR gcmHAL2D(gckGALDEVICE_Setup_ISR)
++#define gckKERNEL_AttachProcess gcmHAL2D(gckKERNEL_AttachProcess)
++#define gckKERNEL_AttachProcessEx gcmHAL2D(gckKERNEL_AttachProcessEx)
++#define gckGALDEVICE_Start_Thread gcmHAL2D(gckGALDEVICE_Start_Thread)
++#define gckHARDWARE_QueryIdle gcmHAL2D(gckHARDWARE_QueryIdle)
++#define gckGALDEVICE_Start gcmHAL2D(gckGALDEVICE_Start)
++#define gckOS_GetKernelLogical gcmHAL2D(gckOS_GetKernelLogical)
++#define gckOS_DebugTraceZone gcmHAL2D(gckOS_DebugTraceZone)
++#define gckGALDEVICE_Stop_Thread gcmHAL2D(gckGALDEVICE_Stop_Thread)
++#define gckHARDWARE_NeedBaseAddress gcmHAL2D(gckHARDWARE_NeedBaseAddress)
++
++#endif
++
++#endif /* __gc_hal_rename_h_ */
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_security_interface.h linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_security_interface.h
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_security_interface.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_security_interface.h 2015-07-27 23:13:06.218794344 +0200
+@@ -0,0 +1,137 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef _GC_HAL_SECURITY_INTERFACE_H_
++#define _GC_HAL_SECURITY_INTERFACE_H_
++/*!
++ @brief Command codes between kernel module and TrustZone
++ @discussion
++ Critical services must be done in TrustZone to avoid sensitive content leak. Most of kernel module is kept in non-Secure os to minimize
++ code in TrustZone.
++ */
++typedef enum kernel_packet_command {
++ KERNEL_START_COMMAND,
++ KERNEL_SUBMIT,
++ KERNEL_MAP_MEMORY, /* */
++ KERNEL_UNMAP_MEMORY,
++ KERNEL_ALLOCATE_SECRUE_MEMORY, /*! Security memory management. */
++ KERNEL_FREE_SECURE_MEMORY,
++ KERNEL_EXECUTE, /* Execute a command buffer. */
++} kernel_packet_command_t;
++
++/*!
++ @brief gckCOMMAND Object requests TrustZone to start FE.
++ @discussion
++ DMA enabled register can only be written in TrustZone to avoid GPU from jumping to a hacked code.
++ Kernel module need use these command to ask TrustZone start command parser.
++ */
++struct kernel_start_command {
++ kernel_packet_command_t command; /*! The command (always needs to be the first entry in a structure). */
++ gctUINT8 gpu; /*! Which GPU. */
++};
++
++/*!
++ @brief gckCOMMAND Object requests TrustZone to submit command buffer.
++ @discussion
++ Code in trustzone will check content of command buffer after copying command buffer to TrustZone.
++ */
++struct kernel_submit {
++ kernel_packet_command_t command; /*! The command (always needs to be the first entry in a structure). */
++ gctUINT8 gpu; /*! Which GPU. */
++ gctUINT8 kernel_command; /*! Whether it is a kernel command. */
++ gctUINT32 command_buffer_handle; /*! Handle to command buffer. */
++ gctUINT32 offset; /* Offset in command buffer. */
++ gctUINT32 * command_buffer; /*! Content of command buffer need to be submit. */
++ gctUINT32 command_buffer_length; /*! Length of command buffer. */
++};
++
++
++/*!
++ @brief gckVIDMEM Object requests TrustZone to allocate security memory.
++ @discussion
++ Allocate a buffer from security GPU memory.
++ */
++struct kernel_allocate_security_memory {
++ kernel_packet_command_t command; /*! The command (always needs to be the first entry in a structure). */
++ gctUINT32 bytes; /*! Requested bytes. */
++ gctUINT32 memory_handle; /*! Handle of allocated memory. */
++};
++
++/*!
++ @brief gckVIDMEM Object requests TrustZone to allocate security memory.
++ @discussion
++ Free a video memory buffer from security GPU memory.
++ */
++struct kernel_free_security_memory {
++ kernel_packet_command_t command; /*! The command (always needs to be the first entry in a structure). */
++ gctUINT32 memory_handle; /*! Handle of allocated memory. */
++};
++
++struct kernel_execute {
++ kernel_packet_command_t command; /*! The command (always needs to be the first entry in a structure). */
++ gctUINT8 gpu; /*! Which GPU. */
++ gctUINT8 kernel_command; /*! Whether it is a kernel command. */
++ gctUINT32 * command_buffer; /*! Content of command buffer need to be submit. */
++ gctUINT32 command_buffer_length; /*! Length of command buffer. */
++};
++
++typedef struct kernel_map_scatter_gather {
++ gctUINT32 bytes;
++ gctUINT32 physical;
++ struct kernel_map_scatter_gather *next;
++}
++kernel_map_scatter_gather_t;
++
++struct kernel_map_memory {
++ kernel_packet_command_t command;
++ kernel_map_scatter_gather_t *scatter;
++ gctUINT32 *physicals;
++ gctUINT32 pageCount;
++ gctUINT32 gpuAddress;
++};
++
++struct kernel_unmap_memory {
++ gctUINT32 gpuAddress;
++ gctUINT32 pageCount;
++};
++
++typedef struct _gcsTA_INTERFACE {
++ kernel_packet_command_t command;
++ union {
++ struct kernel_submit Submit;
++ struct kernel_start_command StartCommand;
++ struct kernel_allocate_security_memory AllocateSecurityMemory;
++ struct kernel_execute Execute;
++ struct kernel_map_memory MapMemory;
++ struct kernel_unmap_memory UnmapMemory;
++ } u;
++ gceSTATUS result;
++} gcsTA_INTERFACE;
++
++enum {
++ gcvTA_COMMAND_INIT,
++ gcvTA_COMMAND_DISPATCH,
++
++ gcvTA_CALLBACK_ALLOC_SECURE_MEM,
++ gcvTA_CALLBACK_FREE_SECURE_MEM,
++};
++
++#endif
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_statistics.h linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_statistics.h
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_statistics.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_statistics.h 2015-07-27 23:13:06.218794344 +0200
+@@ -0,0 +1,115 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_statistics_h_
++#define __gc_hal_statistics_h_
++
++
++#define VIV_STAT_ENABLE_STATISTICS 0
++
++/* Toal number of frames for which the frame time is accounted. We have storage
++ to keep frame times for last this many frames.
++*/
++#define VIV_STAT_FRAME_BUFFER_SIZE 30
++
++/*
++ Total number of frames sampled for a mode. This means
++
++ # of frames for HZ Current : VIV_STAT_EARLY_Z_SAMPLE_FRAMES
++ # of frames for HZ Switched : VIV_STAT_EARLY_Z_SAMPLE_FRAMES
++ +
++ --------------------------------------------------------
++ : (2 * VIV_STAT_EARLY_Z_SAMPLE_FRAMES) frames needed
++
++ IMPORTANT: This total must be smaller than VIV_STAT_FRAME_BUFFER_SIZE
++*/
++#define VIV_STAT_EARLY_Z_SAMPLE_FRAMES 7
++#define VIV_STAT_EARLY_Z_LATENCY_FRAMES 2
++
++/* Multiplication factor for previous Hz off mode. Make it more than 1.0 to advertise HZ on.*/
++#define VIV_STAT_EARLY_Z_FACTOR (1.05f)
++
++/* Defines the statistical data keys monitored by the statistics module */
++typedef enum _gceSTATISTICS
++{
++ gcvFRAME_FPS = 1,
++}
++gceSTATISTICS;
++
++/* HAL statistics information. */
++typedef struct _gcsSTATISTICS_EARLYZ
++{
++ gctUINT switchBackCount;
++ gctUINT nextCheckPoint;
++ gctBOOL disabled;
++}
++gcsSTATISTICS_EARLYZ;
++
++
++/* Defines the statistical data keys monitored by the statistics module */
++typedef enum _gceSTATISTICS_Call
++{
++ gcvSTAT_ES11_GLDRAWELEMENTS = 1,
++}
++gceSTATISTICS_Call;
++
++
++/* HAL statistics information. */
++typedef struct _gcsSTATISTICS
++{
++ gctUINT64 frameTime[VIV_STAT_FRAME_BUFFER_SIZE];
++ gctUINT64 previousFrameTime;
++ gctUINT frame;
++ gcsSTATISTICS_EARLYZ earlyZ;
++ gctUINT ES11_drawElementsCount;
++ gctBOOL applyRTestVAFix;
++}
++gcsSTATISTICS;
++
++
++/* Add a frame based data into current statistics. */
++void
++gcfSTATISTICS_AddData(
++ IN gceSTATISTICS Key,
++ IN gctUINT Value
++ );
++
++/* Marks the frame end and triggers statistical calculations and decisions.*/
++void
++gcfSTATISTICS_MarkFrameEnd (
++ void
++ );
++
++/* Sets whether the dynmaic HZ is disabled or not .*/
++void
++gcfSTATISTICS_DisableDynamicEarlyZ (
++ IN gctBOOL Disabled
++ );
++
++/* Checks whether or not glDrawArray function call will be discarded */
++gctBOOL
++gcfSTATISTICS_DiscardCall(
++ gceSTATISTICS_Call Function
++ );
++
++
++#endif /*__gc_hal_statistics_h_ */
++
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_types.h linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_types.h
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_types.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_types.h 2015-07-27 23:13:06.218794344 +0200
+@@ -0,0 +1,1088 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++#ifndef __gc_hal_types_h_
++#define __gc_hal_types_h_
++
++#include "gc_hal_version.h"
++#include "gc_hal_options.h"
++
++#ifdef _WIN32
++#pragma warning(disable:4127) /* Conditional expression is constant (do { }
++ ** while(0)). */
++#pragma warning(disable:4100) /* Unreferenced formal parameter. */
++#pragma warning(disable:4204) /* Non-constant aggregate initializer (C99). */
++#pragma warning(disable:4131) /* Uses old-style declarator (for Bison and
++ ** Flex generated files). */
++#pragma warning(disable:4206) /* Translation unit is empty. */
++#endif
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/******************************************************************************\
++** Platform macros.
++*/
++
++#if defined(__GNUC__)
++# define gcdHAS_ELLIPSES 1 /* GCC always has it. */
++#elif defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 199901L)
++# define gcdHAS_ELLIPSES 1 /* C99 has it. */
++#elif defined(_MSC_VER) && (_MSC_VER >= 1500)
++# define gcdHAS_ELLIPSES 1 /* MSVC 2007+ has it. */
++#elif defined(UNDER_CE)
++#if UNDER_CE >= 600
++# define gcdHAS_ELLIPSES 1
++# else
++# define gcdHAS_ELLIPSES 0
++# endif
++#else
++# error "gcdHAS_ELLIPSES: Platform could not be determined"
++#endif
++
++/******************************************************************************\
++************************************ Keyword ***********************************
++\******************************************************************************/
++
++#if (defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 199901L))
++# define gcmINLINE inline /* C99 keyword. */
++#elif defined(__GNUC__)
++# define gcmINLINE __inline__ /* GNU keyword. */
++#elif defined(_MSC_VER) || defined(UNDER_CE)
++# define gcmINLINE __inline /* Internal keyword. */
++#else
++# error "gcmINLINE: Platform could not be determined"
++#endif
++
++/* Possible debug flags. */
++#define gcdDEBUG_NONE 0
++#define gcdDEBUG_ALL (1 << 0)
++#define gcdDEBUG_FATAL (1 << 1)
++#define gcdDEBUG_TRACE (1 << 2)
++#define gcdDEBUG_BREAK (1 << 3)
++#define gcdDEBUG_ASSERT (1 << 4)
++#define gcdDEBUG_CODE (1 << 5)
++#define gcdDEBUG_STACK (1 << 6)
++
++#define gcmIS_DEBUG(flag) ( gcdDEBUG & (flag | gcdDEBUG_ALL) )
++
++#ifndef gcdDEBUG
++#if (defined(DBG) && DBG) || defined(DEBUG) || defined(_DEBUG)
++# define gcdDEBUG gcdDEBUG_ALL
++# else
++# define gcdDEBUG gcdDEBUG_NONE
++# endif
++#endif
++
++#ifdef _USRDLL
++#ifdef _MSC_VER
++#ifdef HAL_EXPORTS
++# define HALAPI __declspec(dllexport)
++# else
++# define HALAPI __declspec(dllimport)
++# endif
++# define HALDECL __cdecl
++# else
++#ifdef HAL_EXPORTS
++# define HALAPI
++# else
++# define HALAPI extern
++# endif
++# endif
++#else
++# define HALAPI
++# define HALDECL
++#endif
++
++/******************************************************************************\
++********************************** Common Types ********************************
++\******************************************************************************/
++
++#define gcvFALSE 0
++#define gcvTRUE 1
++
++#define gcvINFINITE ((gctUINT32) ~0U)
++
++#define gcvINVALID_HANDLE ((gctHANDLE) ~0U)
++
++typedef int gctBOOL;
++typedef gctBOOL * gctBOOL_PTR;
++
++typedef int gctINT;
++typedef long gctLONG;
++typedef signed char gctINT8;
++typedef signed short gctINT16;
++typedef signed int gctINT32;
++typedef signed long long gctINT64;
++
++typedef gctINT * gctINT_PTR;
++typedef gctINT8 * gctINT8_PTR;
++typedef gctINT16 * gctINT16_PTR;
++typedef gctINT32 * gctINT32_PTR;
++typedef gctINT64 * gctINT64_PTR;
++
++typedef unsigned int gctUINT;
++typedef unsigned char gctUINT8;
++typedef unsigned short gctUINT16;
++typedef unsigned int gctUINT32;
++typedef unsigned long long gctUINT64;
++typedef unsigned long gctUINTPTR_T;
++
++typedef gctUINT * gctUINT_PTR;
++typedef gctUINT8 * gctUINT8_PTR;
++typedef gctUINT16 * gctUINT16_PTR;
++typedef gctUINT32 * gctUINT32_PTR;
++typedef gctUINT64 * gctUINT64_PTR;
++
++typedef unsigned long gctSIZE_T;
++typedef gctSIZE_T * gctSIZE_T_PTR;
++
++#ifdef __cplusplus
++# define gcvNULL 0
++#else
++# define gcvNULL ((void *) 0)
++#endif
++
++typedef float gctFLOAT;
++typedef signed int gctFIXED_POINT;
++typedef float * gctFLOAT_PTR;
++
++typedef void * gctPHYS_ADDR;
++typedef void * gctHANDLE;
++typedef void * gctFILE;
++typedef void * gctSIGNAL;
++typedef void * gctWINDOW;
++typedef void * gctIMAGE;
++typedef void * gctSYNC_POINT;
++
++typedef void * gctSEMAPHORE;
++
++typedef void * gctPOINTER;
++typedef const void * gctCONST_POINTER;
++
++typedef char gctCHAR;
++typedef char * gctSTRING;
++typedef const char * gctCONST_STRING;
++
++typedef struct _gcsCOUNT_STRING
++{
++ gctSIZE_T Length;
++ gctCONST_STRING String;
++}
++gcsCOUNT_STRING;
++
++typedef union _gcuFLOAT_UINT32
++{
++ gctFLOAT f;
++ gctUINT32 u;
++}
++gcuFLOAT_UINT32;
++
++/* Fixed point constants. */
++#define gcvZERO_X ((gctFIXED_POINT) 0x00000000)
++#define gcvHALF_X ((gctFIXED_POINT) 0x00008000)
++#define gcvONE_X ((gctFIXED_POINT) 0x00010000)
++#define gcvNEGONE_X ((gctFIXED_POINT) 0xFFFF0000)
++#define gcvTWO_X ((gctFIXED_POINT) 0x00020000)
++
++/* Stringizing macro. */
++#define gcmSTRING(Value) #Value
++
++/******************************************************************************\
++******************************* Fixed Point Math *******************************
++\******************************************************************************/
++
++#define gcmXMultiply(x1, x2) gcoMATH_MultiplyFixed(x1, x2)
++#define gcmXDivide(x1, x2) gcoMATH_DivideFixed(x1, x2)
++#define gcmXMultiplyDivide(x1, x2, x3) gcoMATH_MultiplyDivideFixed(x1, x2, x3)
++
++/* 2D Engine profile. */
++typedef struct _gcs2D_PROFILE
++{
++ /* Cycle count.
++ 32bit counter incremented every 2D clock cycle.
++ Wraps back to 0 when the counter overflows.
++ */
++ gctUINT32 cycleCount;
++
++ /* Pixels rendered by the 2D engine.
++ Resets to 0 every time it is read. */
++ gctUINT32 pixelsRendered;
++}
++gcs2D_PROFILE;
++
++/* Macro to combine four characters into a Charcater Code. */
++#define gcmCC(c1, c2, c3, c4) \
++( \
++ (char) (c1) \
++ | \
++ ((char) (c2) << 8) \
++ | \
++ ((char) (c3) << 16) \
++ | \
++ ((char) (c4) << 24) \
++)
++
++#define gcmPRINTABLE(c) ((((c) >= ' ') && ((c) <= '}')) ? ((c) != '%' ? (c) : ' ') : ' ')
++
++#define gcmCC_PRINT(cc) \
++ gcmPRINTABLE((char) ( (cc) & 0xFF)), \
++ gcmPRINTABLE((char) (((cc) >> 8) & 0xFF)), \
++ gcmPRINTABLE((char) (((cc) >> 16) & 0xFF)), \
++ gcmPRINTABLE((char) (((cc) >> 24) & 0xFF))
++
++/******************************************************************************\
++****************************** Function Parameters *****************************
++\******************************************************************************/
++
++#define IN
++#define OUT
++#define OPTIONAL
++
++/******************************************************************************\
++********************************* Status Codes *********************************
++\******************************************************************************/
++
++typedef enum _gceSTATUS
++{
++ gcvSTATUS_OK = 0,
++ gcvSTATUS_FALSE = 0,
++ gcvSTATUS_TRUE = 1,
++ gcvSTATUS_NO_MORE_DATA = 2,
++ gcvSTATUS_CACHED = 3,
++ gcvSTATUS_MIPMAP_TOO_LARGE = 4,
++ gcvSTATUS_NAME_NOT_FOUND = 5,
++ gcvSTATUS_NOT_OUR_INTERRUPT = 6,
++ gcvSTATUS_MISMATCH = 7,
++ gcvSTATUS_MIPMAP_TOO_SMALL = 8,
++ gcvSTATUS_LARGER = 9,
++ gcvSTATUS_SMALLER = 10,
++ gcvSTATUS_CHIP_NOT_READY = 11,
++ gcvSTATUS_NEED_CONVERSION = 12,
++ gcvSTATUS_SKIP = 13,
++ gcvSTATUS_DATA_TOO_LARGE = 14,
++ gcvSTATUS_INVALID_CONFIG = 15,
++ gcvSTATUS_CHANGED = 16,
++ gcvSTATUS_NOT_SUPPORT_DITHER = 17,
++ gcvSTATUS_EXECUTED = 18,
++ gcvSTATUS_TERMINATE = 19,
++
++ gcvSTATUS_CONVERT_TO_SINGLE_STREAM = 20,
++
++ gcvSTATUS_INVALID_ARGUMENT = -1,
++ gcvSTATUS_INVALID_OBJECT = -2,
++ gcvSTATUS_OUT_OF_MEMORY = -3,
++ gcvSTATUS_MEMORY_LOCKED = -4,
++ gcvSTATUS_MEMORY_UNLOCKED = -5,
++ gcvSTATUS_HEAP_CORRUPTED = -6,
++ gcvSTATUS_GENERIC_IO = -7,
++ gcvSTATUS_INVALID_ADDRESS = -8,
++ gcvSTATUS_CONTEXT_LOSSED = -9,
++ gcvSTATUS_TOO_COMPLEX = -10,
++ gcvSTATUS_BUFFER_TOO_SMALL = -11,
++ gcvSTATUS_INTERFACE_ERROR = -12,
++ gcvSTATUS_NOT_SUPPORTED = -13,
++ gcvSTATUS_MORE_DATA = -14,
++ gcvSTATUS_TIMEOUT = -15,
++ gcvSTATUS_OUT_OF_RESOURCES = -16,
++ gcvSTATUS_INVALID_DATA = -17,
++ gcvSTATUS_INVALID_MIPMAP = -18,
++ gcvSTATUS_NOT_FOUND = -19,
++ gcvSTATUS_NOT_ALIGNED = -20,
++ gcvSTATUS_INVALID_REQUEST = -21,
++ gcvSTATUS_GPU_NOT_RESPONDING = -22,
++ gcvSTATUS_TIMER_OVERFLOW = -23,
++ gcvSTATUS_VERSION_MISMATCH = -24,
++ gcvSTATUS_LOCKED = -25,
++ gcvSTATUS_INTERRUPTED = -26,
++ gcvSTATUS_DEVICE = -27,
++ gcvSTATUS_NOT_MULTI_PIPE_ALIGNED = -28,
++
++ /* Linker errors. */
++ gcvSTATUS_GLOBAL_TYPE_MISMATCH = -1000,
++ gcvSTATUS_TOO_MANY_ATTRIBUTES = -1001,
++ gcvSTATUS_TOO_MANY_UNIFORMS = -1002,
++ gcvSTATUS_TOO_MANY_VARYINGS = -1003,
++ gcvSTATUS_UNDECLARED_VARYING = -1004,
++ gcvSTATUS_VARYING_TYPE_MISMATCH = -1005,
++ gcvSTATUS_MISSING_MAIN = -1006,
++ gcvSTATUS_NAME_MISMATCH = -1007,
++ gcvSTATUS_INVALID_INDEX = -1008,
++ gcvSTATUS_UNIFORM_TYPE_MISMATCH = -1009,
++
++ /* Compiler errors. */
++ gcvSTATUS_COMPILER_FE_PREPROCESSOR_ERROR = -2000,
++ gcvSTATUS_COMPILER_FE_PARSER_ERROR = -2001,
++}
++gceSTATUS;
++
++/******************************************************************************\
++********************************* Status Macros ********************************
++\******************************************************************************/
++
++#define gcmIS_ERROR(status) (status < 0)
++#define gcmNO_ERROR(status) (status >= 0)
++#define gcmIS_SUCCESS(status) (status == gcvSTATUS_OK)
++
++/******************************************************************************\
++********************************* Field Macros *********************************
++\******************************************************************************/
++
++#define __gcmSTART(reg_field) \
++ (0 ? reg_field)
++
++#define __gcmEND(reg_field) \
++ (1 ? reg_field)
++
++#define __gcmGETSIZE(reg_field) \
++ (__gcmEND(reg_field) - __gcmSTART(reg_field) + 1)
++
++#define __gcmALIGN(data, reg_field) \
++ (((gctUINT32) (data)) << __gcmSTART(reg_field))
++
++#define __gcmMASK(reg_field) \
++ ((gctUINT32) ((__gcmGETSIZE(reg_field) == 32) \
++ ? ~0 \
++ : (~(~0 << __gcmGETSIZE(reg_field)))))
++
++/*******************************************************************************
++**
++** gcmFIELDMASK
++**
++** Get aligned field mask.
++**
++** ARGUMENTS:
++**
++** reg Name of register.
++** field Name of field within register.
++*/
++#define gcmFIELDMASK(reg, field) \
++( \
++ __gcmALIGN(__gcmMASK(reg##_##field), reg##_##field) \
++)
++
++/*******************************************************************************
++**
++** gcmGETFIELD
++**
++** Extract the value of a field from specified data.
++**
++** ARGUMENTS:
++**
++** data Data value.
++** reg Name of register.
++** field Name of field within register.
++*/
++#define gcmGETFIELD(data, reg, field) \
++( \
++ ((((gctUINT32) (data)) >> __gcmSTART(reg##_##field)) \
++ & __gcmMASK(reg##_##field)) \
++)
++
++/*******************************************************************************
++**
++** gcmSETFIELD
++**
++** Set the value of a field within specified data.
++**
++** ARGUMENTS:
++**
++** data Data value.
++** reg Name of register.
++** field Name of field within register.
++** value Value for field.
++*/
++#define gcmSETFIELD(data, reg, field, value) \
++( \
++ (((gctUINT32) (data)) \
++ & ~__gcmALIGN(__gcmMASK(reg##_##field), reg##_##field)) \
++ | __gcmALIGN((gctUINT32) (value) \
++ & __gcmMASK(reg##_##field), reg##_##field) \
++)
++
++/*******************************************************************************
++**
++** gcmSETFIELDVALUE
++**
++** Set the value of a field within specified data with a
++** predefined value.
++**
++** ARGUMENTS:
++**
++** data Data value.
++** reg Name of register.
++** field Name of field within register.
++** value Name of the value within the field.
++*/
++#define gcmSETFIELDVALUE(data, reg, field, value) \
++( \
++ (((gctUINT32) (data)) \
++ & ~__gcmALIGN(__gcmMASK(reg##_##field), reg##_##field)) \
++ | __gcmALIGN(reg##_##field##_##value \
++ & __gcmMASK(reg##_##field), reg##_##field) \
++)
++
++/*******************************************************************************
++**
++** gcmGETMASKEDFIELDMASK
++**
++** Determine field mask of a masked field.
++**
++** ARGUMENTS:
++**
++** reg Name of register.
++** field Name of field within register.
++*/
++#define gcmGETMASKEDFIELDMASK(reg, field) \
++( \
++ gcmSETFIELD(0, reg, field, ~0) | \
++ gcmSETFIELD(0, reg, MASK_ ## field, ~0) \
++)
++
++/*******************************************************************************
++**
++** gcmSETMASKEDFIELD
++**
++** Set the value of a masked field with specified data.
++**
++** ARGUMENTS:
++**
++** reg Name of register.
++** field Name of field within register.
++** value Value for field.
++*/
++#define gcmSETMASKEDFIELD(reg, field, value) \
++( \
++ gcmSETFIELD (~0, reg, field, value) & \
++ gcmSETFIELDVALUE(~0, reg, MASK_ ## field, ENABLED) \
++)
++
++/*******************************************************************************
++**
++** gcmSETMASKEDFIELDVALUE
++**
++** Set the value of a masked field with specified data.
++**
++** ARGUMENTS:
++**
++** reg Name of register.
++** field Name of field within register.
++** value Value for field.
++*/
++#define gcmSETMASKEDFIELDVALUE(reg, field, value) \
++( \
++ gcmSETFIELDVALUE(~0, reg, field, value) & \
++ gcmSETFIELDVALUE(~0, reg, MASK_ ## field, ENABLED) \
++)
++
++/*******************************************************************************
++**
++** gcmVERIFYFIELDVALUE
++**
++** Verify if the value of a field within specified data equals a
++** predefined value.
++**
++** ARGUMENTS:
++**
++** data Data value.
++** reg Name of register.
++** field Name of field within register.
++** value Name of the value within the field.
++*/
++#define gcmVERIFYFIELDVALUE(data, reg, field, value) \
++( \
++ (((gctUINT32) (data)) >> __gcmSTART(reg##_##field) & \
++ __gcmMASK(reg##_##field)) \
++ == \
++ (reg##_##field##_##value & __gcmMASK(reg##_##field)) \
++)
++
++/*******************************************************************************
++** Bit field macros.
++*/
++
++#define __gcmSTARTBIT(Field) \
++ ( 1 ? Field )
++
++#define __gcmBITSIZE(Field) \
++ ( 0 ? Field )
++
++#define __gcmBITMASK(Field) \
++( \
++ (1 << __gcmBITSIZE(Field)) - 1 \
++)
++
++#define gcmGETBITS(Value, Type, Field) \
++( \
++ ( ((Type) (Value)) >> __gcmSTARTBIT(Field) ) \
++ & \
++ __gcmBITMASK(Field) \
++)
++
++#define gcmSETBITS(Value, Type, Field, NewValue) \
++( \
++ ( ((Type) (Value)) \
++ & ~(__gcmBITMASK(Field) << __gcmSTARTBIT(Field)) \
++ ) \
++ | \
++ ( ( ((Type) (NewValue)) \
++ & __gcmBITMASK(Field) \
++ ) << __gcmSTARTBIT(Field) \
++ ) \
++)
++
++/*******************************************************************************
++**
++** gcmISINREGRANGE
++**
++** Verify whether the specified address is in the register range.
++**
++** ARGUMENTS:
++**
++** Address Address to be verified.
++** Name Name of a register.
++*/
++
++#define gcmISINREGRANGE(Address, Name) \
++( \
++ ((Address & (~0U << Name ## _LSB)) == (Name ## _Address >> 2)) \
++)
++
++/*******************************************************************************
++**
++** A set of macros to aid state loading.
++**
++** ARGUMENTS:
++**
++** CommandBuffer Pointer to a gcoCMDBUF object.
++** StateDelta Pointer to a gcsSTATE_DELTA state delta structure.
++** Memory Destination memory pointer of gctUINT32_PTR type.
++** PartOfContext Whether or not the state is a part of the context.
++** FixedPoint Whether or not the state is of the fixed point format.
++** Count Number of consecutive states to be loaded.
++** Address State address.
++** Data Data to be set to the state.
++*/
++
++/*----------------------------------------------------------------------------*/
++
++#if gcmIS_DEBUG(gcdDEBUG_CODE)
++
++# define gcmSTORELOADSTATE(CommandBuffer, Memory, Address, Count) \
++ CommandBuffer->lastLoadStatePtr = gcmPTR_TO_UINT64(Memory); \
++ CommandBuffer->lastLoadStateAddress = Address; \
++ CommandBuffer->lastLoadStateCount = Count
++
++# define gcmVERIFYLOADSTATE(CommandBuffer, Memory, Address) \
++ gcmASSERT( \
++ (gctUINT) (Memory - gcmUINT64_TO_TYPE(CommandBuffer->lastLoadStatePtr, gctUINT32_PTR) - 1) \
++ == \
++ (gctUINT) (Address - CommandBuffer->lastLoadStateAddress) \
++ ); \
++ \
++ gcmASSERT(CommandBuffer->lastLoadStateCount > 0); \
++ \
++ CommandBuffer->lastLoadStateCount -= 1
++
++# define gcmVERIFYLOADSTATEDONE(CommandBuffer) \
++ gcmASSERT(CommandBuffer->lastLoadStateCount == 0)
++
++#else
++
++# define gcmSTORELOADSTATE(CommandBuffer, Memory, Address, Count)
++# define gcmVERIFYLOADSTATE(CommandBuffer, Memory, Address)
++# define gcmVERIFYLOADSTATEDONE(CommandBuffer)
++
++#endif
++
++#if gcdSECURE_USER
++
++# define gcmDEFINESECUREUSER() \
++ gctUINT __secure_user_offset__; \
++ gctUINT32_PTR __secure_user_hintArray__;
++
++# define gcmBEGINSECUREUSER() \
++ __secure_user_offset__ = reserve->lastOffset; \
++ \
++ __secure_user_hintArray__ = gcmUINT64_TO_PTR(reserve->hintArrayTail)
++
++# define gcmENDSECUREUSER() \
++ reserve->hintArrayTail = gcmPTR_TO_UINT64(__secure_user_hintArray__)
++
++# define gcmSKIPSECUREUSER() \
++ __secure_user_offset__ += gcmSIZEOF(gctUINT32)
++
++# define gcmUPDATESECUREUSER() \
++ *__secure_user_hintArray__ = __secure_user_offset__; \
++ \
++ __secure_user_offset__ += gcmSIZEOF(gctUINT32); \
++ __secure_user_hintArray__ += 1
++
++#else
++
++# define gcmDEFINESECUREUSER()
++# define gcmBEGINSECUREUSER()
++# define gcmENDSECUREUSER()
++# define gcmSKIPSECUREUSER()
++# define gcmUPDATESECUREUSER()
++
++#endif
++
++/*----------------------------------------------------------------------------*/
++
++#if gcdDUMP
++# define gcmDUMPSTATEDATA(StateDelta, FixedPoint, Address, Data) \
++ if (FixedPoint) \
++ { \
++ gcmDUMP(gcvNULL, "@[state.x 0x%04X 0x%08X]", \
++ Address, Data \
++ ); \
++ } \
++ else \
++ { \
++ gcmDUMP(gcvNULL, "@[state 0x%04X 0x%08X]", \
++ Address, Data \
++ ); \
++ }
++#else
++# define gcmDUMPSTATEDATA(StateDelta, FixedPoint, Address, Data)
++#endif
++
++/*----------------------------------------------------------------------------*/
++
++#define gcmDEFINESTATEBUFFER(CommandBuffer, StateDelta, Memory, ReserveSize) \
++ gcmDEFINESECUREUSER() \
++ gctSIZE_T ReserveSize; \
++ gcoCMDBUF CommandBuffer; \
++ gctUINT32_PTR Memory; \
++ gcsSTATE_DELTA_PTR StateDelta
++
++#define gcmBEGINSTATEBUFFER(Hardware, CommandBuffer, StateDelta, Memory, ReserveSize) \
++{ \
++ gcmONERROR(gcoBUFFER_Reserve( \
++ Hardware->buffer, ReserveSize, gcvTRUE, &CommandBuffer \
++ )); \
++ \
++ Memory = gcmUINT64_TO_PTR(CommandBuffer->lastReserve); \
++ \
++ StateDelta = Hardware->delta; \
++ \
++ gcmBEGINSECUREUSER(); \
++}
++
++#define gcmENDSTATEBUFFER(CommandBuffer, Memory, ReserveSize) \
++{ \
++ gcmENDSECUREUSER(); \
++ \
++ gcmASSERT( \
++ gcmUINT64_TO_TYPE(CommandBuffer->lastReserve, gctUINT8_PTR) + ReserveSize \
++ == \
++ (gctUINT8_PTR) Memory \
++ ); \
++}
++
++/*----------------------------------------------------------------------------*/
++
++#define gcmBEGINSTATEBATCH(CommandBuffer, Memory, FixedPoint, Address, Count) \
++{ \
++ gcmASSERT(((Memory - gcmUINT64_TO_TYPE(CommandBuffer->lastReserve, gctUINT32_PTR)) & 1) == 0); \
++ gcmASSERT((gctUINT32)Count <= 1024); \
++ \
++ gcmVERIFYLOADSTATEDONE(CommandBuffer); \
++ \
++ gcmSTORELOADSTATE(CommandBuffer, Memory, Address, Count); \
++ \
++ *Memory++ \
++ = gcmSETFIELDVALUE(0, AQ_COMMAND_LOAD_STATE_COMMAND, OPCODE, LOAD_STATE) \
++ | gcmSETFIELD (0, AQ_COMMAND_LOAD_STATE_COMMAND, FLOAT, FixedPoint) \
++ | gcmSETFIELD (0, AQ_COMMAND_LOAD_STATE_COMMAND, COUNT, Count) \
++ | gcmSETFIELD (0, AQ_COMMAND_LOAD_STATE_COMMAND, ADDRESS, Address); \
++ \
++ gcmSKIPSECUREUSER(); \
++}
++
++#define gcmENDSTATEBATCH(CommandBuffer, Memory) \
++{ \
++ gcmVERIFYLOADSTATEDONE(CommandBuffer); \
++ \
++ gcmASSERT(((Memory - gcmUINT64_TO_TYPE(CommandBuffer->lastReserve, gctUINT32_PTR)) & 1) == 0); \
++}
++
++/*----------------------------------------------------------------------------*/
++
++#define gcmSETSTATEDATA(StateDelta, CommandBuffer, Memory, FixedPoint, \
++ Address, Data) \
++{ \
++ gctUINT32 __temp_data32__; \
++ \
++ gcmVERIFYLOADSTATE(CommandBuffer, Memory, Address); \
++ \
++ __temp_data32__ = Data; \
++ \
++ *Memory++ = __temp_data32__; \
++ \
++ gcoHARDWARE_UpdateDelta( \
++ StateDelta, FixedPoint, Address, 0, __temp_data32__ \
++ ); \
++ \
++ gcmDUMPSTATEDATA(StateDelta, FixedPoint, Address, __temp_data32__); \
++ \
++ gcmUPDATESECUREUSER(); \
++}
++
++#define gcmSETCTRLSTATE(StateDelta, CommandBuffer, Memory, Address, Data) \
++{ \
++ gctUINT32 __temp_data32__; \
++ \
++ gcmVERIFYLOADSTATE(CommandBuffer, Memory, Address); \
++ \
++ __temp_data32__ = Data; \
++ \
++ *Memory++ = __temp_data32__; \
++ \
++ gcmDUMPSTATEDATA(StateDelta, gcvFALSE, Address, __temp_data32__); \
++ \
++ gcmSKIPSECUREUSER(); \
++}
++
++#define gcmSETFILLER(CommandBuffer, Memory) \
++{ \
++ gcmVERIFYLOADSTATEDONE(CommandBuffer); \
++ \
++ Memory += 1; \
++ \
++ gcmSKIPSECUREUSER(); \
++}
++
++/*----------------------------------------------------------------------------*/
++
++#define gcmSETSINGLESTATE(StateDelta, CommandBuffer, Memory, FixedPoint, \
++ Address, Data) \
++{ \
++ gcmBEGINSTATEBATCH(CommandBuffer, Memory, FixedPoint, Address, 1); \
++ gcmSETSTATEDATA(StateDelta, CommandBuffer, Memory, FixedPoint, \
++ Address, Data); \
++ gcmENDSTATEBATCH(CommandBuffer, Memory); \
++}
++
++#define gcmSETSINGLECTRLSTATE(StateDelta, CommandBuffer, Memory, FixedPoint, \
++ Address, Data) \
++{ \
++ gcmBEGINSTATEBATCH(CommandBuffer, Memory, FixedPoint, Address, 1); \
++ gcmSETCTRLSTATE(StateDelta, CommandBuffer, Memory, Address, Data); \
++ gcmENDSTATEBATCH(CommandBuffer, Memory); \
++}
++
++
++/*******************************************************************************
++**
++** gcmSETSTARTDECOMMAND
++**
++** Form a START_DE command.
++**
++** ARGUMENTS:
++**
++** Memory Destination memory pointer of gctUINT32_PTR type.
++** Count Number of the rectangles.
++*/
++
++#define gcmSETSTARTDECOMMAND(Memory, Count) \
++{ \
++ *Memory++ \
++ = gcmSETFIELDVALUE(0, AQ_COMMAND_START_DE_COMMAND, OPCODE, START_DE) \
++ | gcmSETFIELD (0, AQ_COMMAND_START_DE_COMMAND, COUNT, Count) \
++ | gcmSETFIELD (0, AQ_COMMAND_START_DE_COMMAND, DATA_COUNT, 0); \
++ \
++ *Memory++ = 0xDEADDEED; \
++}
++
++/******************************************************************************\
++******************************** Ceiling Macro ********************************
++\******************************************************************************/
++#define gcmCEIL(x) ((x - (gctUINT32)x) == 0 ? (gctUINT32)x : (gctUINT32)x + 1)
++
++/******************************************************************************\
++******************************** Min/Max Macros ********************************
++\******************************************************************************/
++
++#define gcmMIN(x, y) (((x) <= (y)) ? (x) : (y))
++#define gcmMAX(x, y) (((x) >= (y)) ? (x) : (y))
++#define gcmCLAMP(x, min, max) (((x) < (min)) ? (min) : \
++ ((x) > (max)) ? (max) : (x))
++#define gcmABS(x) (((x) < 0) ? -(x) : (x))
++#define gcmNEG(x) (((x) < 0) ? (x) : -(x))
++
++/*******************************************************************************
++**
++** gcmPTR2INT
++**
++** Convert a pointer to an integer value.
++**
++** ARGUMENTS:
++**
++** p Pointer value.
++*/
++#if defined(_WIN32) || (defined(__LP64__) && __LP64__)
++# define gcmPTR2INT(p) \
++ ( \
++ (gctUINT32) (gctUINT64) (p) \
++ )
++#else
++# define gcmPTR2INT(p) \
++ ( \
++ (gctUINT32) (p) \
++ )
++#endif
++
++/*******************************************************************************
++**
++** gcmINT2PTR
++**
++** Convert an integer value into a pointer.
++**
++** ARGUMENTS:
++**
++** v Integer value.
++*/
++#ifdef __LP64__
++# define gcmINT2PTR(i) \
++ ( \
++ (gctPOINTER) (gctINT64) (i) \
++ )
++#else
++# define gcmINT2PTR(i) \
++ ( \
++ (gctPOINTER) (i) \
++ )
++#endif
++
++/*******************************************************************************
++**
++** gcmOFFSETOF
++**
++** Compute the byte offset of a field inside a structure.
++**
++** ARGUMENTS:
++**
++** s Structure name.
++** field Field name.
++*/
++#define gcmOFFSETOF(s, field) \
++( \
++ gcmPTR2INT(& (((struct s *) 0)->field)) \
++)
++
++#define gcmSWAB32(x) ((gctUINT32)( \
++ (((gctUINT32)(x) & (gctUINT32)0x000000FFUL) << 24) | \
++ (((gctUINT32)(x) & (gctUINT32)0x0000FF00UL) << 8) | \
++ (((gctUINT32)(x) & (gctUINT32)0x00FF0000UL) >> 8) | \
++ (((gctUINT32)(x) & (gctUINT32)0xFF000000UL) >> 24)))
++
++/*******************************************************************************
++***** Database ****************************************************************/
++
++typedef struct _gcsDATABASE_COUNTERS
++{
++ /* Number of currently allocated bytes. */
++ gctUINT64 bytes;
++
++ /* Maximum number of bytes allocated (memory footprint). */
++ gctUINT64 maxBytes;
++
++ /* Total number of bytes allocated. */
++ gctUINT64 totalBytes;
++}
++gcsDATABASE_COUNTERS;
++
++typedef struct _gcuDATABASE_INFO
++{
++ /* Counters. */
++ gcsDATABASE_COUNTERS counters;
++
++ /* Time value. */
++ gctUINT64 time;
++}
++gcuDATABASE_INFO;
++
++/*******************************************************************************
++***** Frame database **********************************************************/
++
++/* gcsHAL_FRAME_INFO */
++typedef struct _gcsHAL_FRAME_INFO
++{
++ /* Current timer tick. */
++ OUT gctUINT64 ticks;
++
++ /* Bandwidth counters. */
++ OUT gctUINT readBytes8[8];
++ OUT gctUINT writeBytes8[8];
++
++ /* Counters. */
++ OUT gctUINT cycles[8];
++ OUT gctUINT idleCycles[8];
++ OUT gctUINT mcCycles[8];
++ OUT gctUINT readRequests[8];
++ OUT gctUINT writeRequests[8];
++
++ /* FE counters. */
++ OUT gctUINT drawCount;
++ OUT gctUINT vertexOutCount;
++ OUT gctUINT vertexMissCount;
++
++ /* 3D counters. */
++ OUT gctUINT vertexCount;
++ OUT gctUINT primitiveCount;
++ OUT gctUINT rejectedPrimitives;
++ OUT gctUINT culledPrimitives;
++ OUT gctUINT clippedPrimitives;
++ OUT gctUINT droppedPrimitives;
++ OUT gctUINT frustumClippedPrimitives;
++ OUT gctUINT outPrimitives;
++ OUT gctUINT inPrimitives;
++ OUT gctUINT culledQuadCount;
++ OUT gctUINT totalQuadCount;
++ OUT gctUINT quadCount;
++ OUT gctUINT totalPixelCount;
++
++ /* PE counters. */
++ OUT gctUINT colorKilled[8];
++ OUT gctUINT colorDrawn[8];
++ OUT gctUINT depthKilled[8];
++ OUT gctUINT depthDrawn[8];
++
++ /* Shader counters. */
++ OUT gctUINT shaderCycles;
++ OUT gctUINT vsInstructionCount;
++ OUT gctUINT vsTextureCount;
++ OUT gctUINT vsBranchCount;
++ OUT gctUINT vsVertices;
++ OUT gctUINT psInstructionCount;
++ OUT gctUINT psTextureCount;
++ OUT gctUINT psBranchCount;
++ OUT gctUINT psPixels;
++
++ /* Texture counters. */
++ OUT gctUINT bilinearRequests;
++ OUT gctUINT trilinearRequests;
++ OUT gctUINT txBytes8[2];
++ OUT gctUINT txHitCount;
++ OUT gctUINT txMissCount;
++}
++gcsHAL_FRAME_INFO;
++
++typedef enum _gcePATCH_ID
++{
++ gcePATCH_UNKNOWN = 0xFFFFFFFF,
++
++ /* Benchmark list*/
++ gcePATCH_GLB11 = 0x0,
++ gcePATCH_GLB21,
++ gcePATCH_GLB25,
++ gcePATCH_GLB27,
++
++ gcePATCH_BM21,
++ gcePATCH_MM,
++ gcePATCH_MM06,
++ gcePATCH_MM07,
++ gcePATCH_QUADRANT,
++ gcePATCH_ANTUTU,
++ gcePATCH_SMARTBENCH,
++ gcePATCH_JPCT,
++ gcePATCH_NENAMARK,
++ gcePATCH_NENAMARK2,
++ gcePATCH_NEOCORE,
++ gcePATCH_GLB,
++ gcePATCH_GB,
++ gcePATCH_RTESTVA,
++ gcePATCH_BMX,
++ gcePATCH_BMGUI,
++
++ /* Game list */
++ gcePATCH_NBA2013,
++ gcePATCH_BARDTALE,
++ gcePATCH_BUSPARKING3D,
++ gcePATCH_FISHBOODLE,
++ gcePATCH_SUBWAYSURFER,
++ gcePATCH_HIGHWAYDRIVER,
++ gcePATCH_PREMIUM,
++ gcePATCH_RACEILLEGAL,
++ gcePATCH_BLABLA,
++ gcePATCH_MEGARUN,
++ gcePATCH_GALAXYONFIRE2,
++ gcePATCH_GLOFTR3HM,
++ gcePATCH_GLOFTSXHM,
++ gcePATCH_GLOFTF3HM,
++ gcePATCH_GLOFTGANG,
++ gcePATCH_XRUNNER,
++ gcePATCH_WP,
++ gcePATCH_DEVIL,
++ gcePATCH_HOLYARCH,
++ gcePATCH_MUSE,
++ gcePATCH_SG,
++ gcePATCH_SIEGECRAFT,
++ gcePATCH_CARCHALLENGE,
++ gcePATCH_HEROESCALL,
++ gcePATCH_MONOPOLY,
++ gcePATCH_CTGL20,
++ gcePATCH_FIREFOX,
++ gcePATCH_CHORME,
++ gcePATCH_DUOKANTV,
++ gcePATCH_TESTAPP,
++ gcePATCH_GOOGLEEARTH,
++ gcePATCH_SF4,
++ gcePATCH_SPEEDRACE,
++ gcePATCH_AIRNAVY,
++ gcePATCH_F18NEW,
++ gcePATCH_F18,
++ gcePATCH_WISTONESG,
++ gcvPATCH_VECUNIT_RED,
++ gcvPATCH_NAMESGAS,
++ gcvPATCH_AFTERBURNER,
++ gcvPATCH_UIMARK,
++ /* Count enum*/
++ gcePATCH_COUNT,
++}
++gcePATCH_ID;
++
++#if gcdLINK_QUEUE_SIZE
++typedef struct _gckLINKDATA * gckLINKDATA;
++struct _gckLINKDATA
++{
++ gctUINT32 start;
++ gctUINT32 end;
++ gctINT pid;
++};
++
++typedef struct _gckLINKQUEUE * gckLINKQUEUE;
++struct _gckLINKQUEUE
++{
++ struct _gckLINKDATA data[gcdLINK_QUEUE_SIZE];
++ gctUINT32 rear;
++ gctUINT32 front;
++ gctUINT32 count;
++};
++#endif
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __gc_hal_types_h_ */
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_version.h linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_version.h
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_version.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_version.h 2015-07-27 23:13:06.218794344 +0200
+@@ -0,0 +1,37 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_version_h_
++#define __gc_hal_version_h_
++
++#define gcvVERSION_MAJOR 4
++
++#define gcvVERSION_MINOR 6
++
++#define gcvVERSION_PATCH 9
++
++#define gcvVERSION_BUILD 9754
++
++#define gcvVERSION_DATE __DATE__
++
++#define gcvVERSION_TIME __TIME__
++
++#endif /* __gc_hal_version_h_ */
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_vg.h linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_vg.h
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_vg.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_vg.h 2015-07-27 23:13:06.218794344 +0200
+@@ -0,0 +1,913 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_vg_h_
++#define __gc_hal_vg_h_
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++
++#include "gc_hal_rename.h"
++#include "gc_hal_types.h"
++#include "gc_hal_enum.h"
++#include "gc_hal_base.h"
++
++#if gcdENABLE_VG
++
++/* Thread routine type. */
++#if defined(LINUX)
++ typedef gctINT gctTHREADFUNCRESULT;
++ typedef gctPOINTER gctTHREADFUNCPARAMETER;
++# define gctTHREADFUNCTYPE
++#elif defined(WIN32)
++ typedef gctUINT gctTHREADFUNCRESULT;
++ typedef gctPOINTER gctTHREADFUNCPARAMETER;
++# define gctTHREADFUNCTYPE __stdcall
++#elif defined(__QNXNTO__)
++ typedef void * gctTHREADFUNCRESULT;
++ typedef gctPOINTER gctTHREADFUNCPARAMETER;
++# define gctTHREADFUNCTYPE
++#endif
++
++typedef gctTHREADFUNCRESULT (gctTHREADFUNCTYPE * gctTHREADFUNC) (
++ gctTHREADFUNCPARAMETER ThreadParameter
++ );
++
++
++#if defined(gcvDEBUG)
++# undef gcvDEBUG
++#endif
++
++#define gcdFORCE_DEBUG 0
++#define gcdFORCE_MESSAGES 0
++
++
++#if DBG || defined(DEBUG) || defined(_DEBUG) || gcdFORCE_DEBUG
++# define gcvDEBUG 1
++#else
++# define gcvDEBUG 0
++#endif
++
++#define _gcmERROR_RETURN(prefix, func) \
++ status = func; \
++ if (gcmIS_ERROR(status)) \
++ { \
++ prefix##PRINT_VERSION(); \
++ prefix##TRACE(gcvLEVEL_ERROR, \
++ #prefix "ERR_RETURN: status=%d(%s) @ %s(%d)", \
++ status, gcoOS_DebugStatus2Name(status), __FUNCTION__, __LINE__); \
++ return status; \
++ } \
++ do { } while (gcvFALSE)
++
++#define gcmERROR_RETURN(func) _gcmERROR_RETURN(gcm, func)
++
++#define gcmLOG_LOCATION()
++
++#define gcmkIS_ERROR(status) (status < 0)
++
++#define gcmALIGNDOWN(n, align) \
++( \
++ (n) & ~((align) - 1) \
++)
++
++#define gcmIS_VALID_INDEX(Index, Array) \
++ (((gctUINT) (Index)) < gcmCOUNTOF(Array))
++
++
++#define gcmIS_NAN(x) \
++( \
++ ((* (gctUINT32_PTR) &(x)) & 0x7FFFFFFF) == 0x7FFFFFFF \
++)
++
++#define gcmLERP(v1, v2, w) \
++ ((v1) * (w) + (v2) * (1.0f - (w)))
++
++#define gcmINTERSECT(Start1, Start2, Length) \
++ (gcmABS((Start1) - (Start2)) < (Length))
++
++/*******************************************************************************
++**
++** gcmERR_GOTO
++**
++** Prints a message and terminates the current loop on error.
++**
++** ASSUMPTIONS:
++**
++** 'status' variable of gceSTATUS type must be defined.
++**
++** ARGUMENTS:
++**
++** Function
++** Function to evaluate.
++*/
++
++#define gcmERR_GOTO(Function) \
++ status = Function; \
++ if (gcmIS_ERROR(status)) \
++ { \
++ gcmTRACE( \
++ gcvLEVEL_ERROR, \
++ "gcmERR_GOTO: status=%d @ line=%d in function %s.\n", \
++ status, __LINE__, __FUNCTION__ \
++ ); \
++ goto ErrorHandler; \
++ }
++
++#if gcvDEBUG || gcdFORCE_MESSAGES
++# define gcmVERIFY_BOOLEAN(Expression) \
++ gcmASSERT( \
++ ( (Expression) == gcvFALSE ) || \
++ ( (Expression) == gcvTRUE ) \
++ )
++#else
++# define gcmVERIFY_BOOLEAN(Expression)
++#endif
++
++/*******************************************************************************
++**
++** gcmVERIFYFIELDFIT
++**
++** Verify whether the value fits in the field.
++**
++** ARGUMENTS:
++**
++** data Data value.
++** reg Name of register.
++** field Name of field within register.
++** value Value for field.
++*/
++#define gcmVERIFYFIELDFIT(reg, field, value) \
++ gcmASSERT( \
++ (value) <= gcmFIELDMAX(reg, field) \
++ )
++/*******************************************************************************
++**
++** gcmFIELDMAX
++**
++** Get field maximum value.
++**
++** ARGUMENTS:
++**
++** reg Name of register.
++** field Name of field within register.
++*/
++#define gcmFIELDMAX(reg, field) \
++( \
++ (gctUINT32) \
++ ( \
++ (__gcmGETSIZE(reg##_##field) == 32) \
++ ? ~0 \
++ : (~(~0 << __gcmGETSIZE(reg##_##field))) \
++ ) \
++)
++
++
++/* ANSI C does not have the 'f' functions, define replacements here. */
++#define gcmSINF(x) ((gctFLOAT) sin(x))
++#define gcmCOSF(x) ((gctFLOAT) cos(x))
++#define gcmASINF(x) ((gctFLOAT) asin(x))
++#define gcmACOSF(x) ((gctFLOAT) acos(x))
++#define gcmSQRTF(x) ((gctFLOAT) sqrt(x))
++#define gcmFABSF(x) ((gctFLOAT) fabs(x))
++#define gcmFMODF(x, y) ((gctFLOAT) fmod((x), (y)))
++#define gcmCEILF(x) ((gctFLOAT) ceil(x))
++#define gcmFLOORF(x) ((gctFLOAT) floor(x))
++
++
++
++/* Fixed point constants. */
++#define gcvZERO_X ((gctFIXED_POINT) 0x00000000)
++#define gcvHALF_X ((gctFIXED_POINT) 0x00008000)
++#define gcvONE_X ((gctFIXED_POINT) 0x00010000)
++#define gcvNEGONE_X ((gctFIXED_POINT) 0xFFFF0000)
++#define gcvTWO_X ((gctFIXED_POINT) 0x00020000)
++
++/* Integer constants. */
++#define gcvMAX_POS_INT ((gctINT) 0x7FFFFFFF)
++#define gcvMAX_NEG_INT ((gctINT) 0x80000000)
++
++/* Float constants. */
++#define gcvMAX_POS_FLOAT ((gctFLOAT) 3.4028235e+038)
++#define gcvMAX_NEG_FLOAT ((gctFLOAT) -3.4028235e+038)
++
++/******************************************************************************\
++***************************** Miscellaneous Macro ******************************
++\******************************************************************************/
++
++#define gcmKB2BYTES(Kilobyte) \
++( \
++ (Kilobyte) << 10 \
++)
++
++#define gcmMB2BYTES(Megabyte) \
++( \
++ (Megabyte) << 20 \
++)
++
++#define gcmMAT(Matrix, Row, Column) \
++( \
++ (Matrix) [(Row) * 3 + (Column)] \
++)
++
++#define gcmMAKE2CHAR(Char1, Char2) \
++( \
++ ((gctUINT16) (gctUINT8) (Char1) << 0) | \
++ ((gctUINT16) (gctUINT8) (Char2) << 8) \
++)
++
++#define gcmMAKE4CHAR(Char1, Char2, Char3, Char4) \
++( \
++ ((gctUINT32)(gctUINT8) (Char1) << 0) | \
++ ((gctUINT32)(gctUINT8) (Char2) << 8) | \
++ ((gctUINT32)(gctUINT8) (Char3) << 16) | \
++ ((gctUINT32)(gctUINT8) (Char4) << 24) \
++)
++
++/* some platforms need to fix the physical address for HW to access*/
++#define gcmFIXADDRESS(address) \
++(\
++ (address)\
++)
++
++#define gcmkFIXADDRESS(address) \
++(\
++ (address)\
++)
++
++/******************************************************************************\
++****************************** Kernel Debug Macro ******************************
++\******************************************************************************/
++
++/* Set signal to signaled state for specified process. */
++gceSTATUS
++gckOS_SetSignal(
++ IN gckOS Os,
++ IN gctHANDLE Process,
++ IN gctSIGNAL Signal
++ );
++
++/* Return the kernel logical pointer for the given physical one. */
++gceSTATUS
++gckOS_GetKernelLogical(
++ IN gckOS Os,
++ IN gctUINT32 Address,
++ OUT gctPOINTER * KernelPointer
++ );
++
++/* Return the kernel logical pointer for the given physical one. */
++gceSTATUS
++gckOS_GetKernelLogicalEx(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctUINT32 Address,
++ OUT gctPOINTER * KernelPointer
++ );
++
++/*----------------------------------------------------------------------------*/
++/*----------------------------- Semaphore Object -----------------------------*/
++
++/* Increment the value of a semaphore. */
++gceSTATUS
++gckOS_IncrementSemaphore(
++ IN gckOS Os,
++ IN gctSEMAPHORE Semaphore
++ );
++
++/* Decrement the value of a semaphore (waiting might occur). */
++gceSTATUS
++gckOS_DecrementSemaphore(
++ IN gckOS Os,
++ IN gctSEMAPHORE Semaphore
++ );
++
++
++/*----------------------------------------------------------------------------*/
++/*------------------------------- Thread Object ------------------------------*/
++
++/* Start a thread. */
++gceSTATUS
++gckOS_StartThread(
++ IN gckOS Os,
++ IN gctTHREADFUNC ThreadFunction,
++ IN gctPOINTER ThreadParameter,
++ OUT gctTHREAD * Thread
++ );
++
++/* Stop a thread. */
++gceSTATUS
++gckOS_StopThread(
++ IN gckOS Os,
++ IN gctTHREAD Thread
++ );
++
++/* Verify whether the thread is still running. */
++gceSTATUS
++gckOS_VerifyThread(
++ IN gckOS Os,
++ IN gctTHREAD Thread
++ );
++
++
++/* Construct a new gckVGKERNEL object. */
++gceSTATUS
++gckVGKERNEL_Construct(
++ IN gckOS Os,
++ IN gctPOINTER Context,
++ IN gckKERNEL inKernel,
++ OUT gckVGKERNEL * Kernel
++ );
++
++/* Destroy an gckVGKERNEL object. */
++gceSTATUS
++gckVGKERNEL_Destroy(
++ IN gckVGKERNEL Kernel
++ );
++
++/* Allocate linear video memory. */
++gceSTATUS
++gckKERNEL_AllocateLinearMemory(
++ IN gckKERNEL Kernel,
++ IN OUT gcePOOL * Pool,
++ IN gctSIZE_T Bytes,
++ IN gctSIZE_T Alignment,
++ IN gceSURF_TYPE Type,
++ OUT gcuVIDMEM_NODE_PTR * Node
++ );
++
++/* Unmap memory. */
++gceSTATUS
++gckKERNEL_UnmapMemory(
++ IN gckKERNEL Kernel,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ IN gctPOINTER Logical
++ );
++
++/* Dispatch a user-level command. */
++gceSTATUS
++gckVGKERNEL_Dispatch(
++ IN gckKERNEL Kernel,
++ IN gctBOOL FromUser,
++ IN OUT struct _gcsHAL_INTERFACE * Interface
++ );
++
++/* Query command buffer requirements. */
++gceSTATUS
++gckKERNEL_QueryCommandBuffer(
++ IN gckKERNEL Kernel,
++ OUT gcsCOMMAND_BUFFER_INFO_PTR Information
++ );
++
++#if gcdDYNAMIC_MAP_RESERVED_MEMORY
++gceSTATUS
++gckOS_MapReservedMemoryToKernel(
++ IN gckOS Os,
++ IN gctUINT32 Physical,
++ IN gctINT Bytes,
++ IN OUT gctPOINTER *Virtual
++ );
++
++gceSTATUS
++gckOS_UnmapReservedMemoryFromKernel(
++ IN gctPOINTER Virtual
++ );
++#endif
++
++/******************************************************************************\
++******************************* gckVGHARDWARE Object ******************************
++\******************************************************************************/
++
++/* Construct a new gckVGHARDWARE object. */
++gceSTATUS
++gckVGHARDWARE_Construct(
++ IN gckOS Os,
++ OUT gckVGHARDWARE * Hardware
++ );
++
++/* Destroy an gckVGHARDWARE object. */
++gceSTATUS
++gckVGHARDWARE_Destroy(
++ IN gckVGHARDWARE Hardware
++ );
++
++/* Query system memory requirements. */
++gceSTATUS
++gckVGHARDWARE_QuerySystemMemory(
++ IN gckVGHARDWARE Hardware,
++ OUT gctSIZE_T * SystemSize,
++ OUT gctUINT32 * SystemBaseAddress
++ );
++
++/* Build virtual address. */
++gceSTATUS
++gckVGHARDWARE_BuildVirtualAddress(
++ IN gckVGHARDWARE Hardware,
++ IN gctUINT32 Index,
++ IN gctUINT32 Offset,
++ OUT gctUINT32 * Address
++ );
++
++/* Kickstart the command processor. */
++gceSTATUS
++gckVGHARDWARE_Execute(
++ IN gckVGHARDWARE Hardware,
++ IN gctUINT32 Address,
++ IN gctSIZE_T Count
++ );
++
++/* Query the available memory. */
++gceSTATUS
++gckVGHARDWARE_QueryMemory(
++ IN gckVGHARDWARE Hardware,
++ OUT gctSIZE_T * InternalSize,
++ OUT gctUINT32 * InternalBaseAddress,
++ OUT gctUINT32 * InternalAlignment,
++ OUT gctSIZE_T * ExternalSize,
++ OUT gctUINT32 * ExternalBaseAddress,
++ OUT gctUINT32 * ExternalAlignment,
++ OUT gctUINT32 * HorizontalTileSize,
++ OUT gctUINT32 * VerticalTileSize
++ );
++
++/* Query the identity of the hardware. */
++gceSTATUS
++gckVGHARDWARE_QueryChipIdentity(
++ IN gckVGHARDWARE Hardware,
++ OUT gceCHIPMODEL* ChipModel,
++ OUT gctUINT32* ChipRevision,
++ OUT gctUINT32* ChipFeatures,
++ OUT gctUINT32* ChipMinorFeatures,
++ OUT gctUINT32* ChipMinorFeatures1
++ );
++
++/* Convert an API format. */
++gceSTATUS
++gckVGHARDWARE_ConvertFormat(
++ IN gckVGHARDWARE Hardware,
++ IN gceSURF_FORMAT Format,
++ OUT gctUINT32 * BitsPerPixel,
++ OUT gctUINT32 * BytesPerTile
++ );
++
++/* Split a harwdare specific address into API stuff. */
++gceSTATUS
++gckVGHARDWARE_SplitMemory(
++ IN gckVGHARDWARE Hardware,
++ IN gctUINT32 Address,
++ OUT gcePOOL * Pool,
++ OUT gctUINT32 * Offset
++ );
++
++/* Align size to tile boundary. */
++gceSTATUS
++gckVGHARDWARE_AlignToTile(
++ IN gckVGHARDWARE Hardware,
++ IN gceSURF_TYPE Type,
++ IN OUT gctUINT32_PTR Width,
++ IN OUT gctUINT32_PTR Height
++ );
++
++/* Convert logical address to hardware specific address. */
++gceSTATUS
++gckVGHARDWARE_ConvertLogical(
++ IN gckVGHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ OUT gctUINT32 * Address
++ );
++
++/* Program MMU. */
++gceSTATUS
++gckVGHARDWARE_SetMMU(
++ IN gckVGHARDWARE Hardware,
++ IN gctPOINTER Logical
++ );
++
++/* Flush the MMU. */
++gceSTATUS
++gckVGHARDWARE_FlushMMU(
++ IN gckVGHARDWARE Hardware
++ );
++
++/* Get idle register. */
++gceSTATUS
++gckVGHARDWARE_GetIdle(
++ IN gckVGHARDWARE Hardware,
++ OUT gctUINT32 * Data
++ );
++
++/* Flush the caches. */
++gceSTATUS
++gckVGHARDWARE_Flush(
++ IN gckVGHARDWARE Hardware,
++ IN gceKERNEL_FLUSH Flush,
++ IN gctPOINTER Logical,
++ IN OUT gctSIZE_T * Bytes
++ );
++
++/* Enable/disable fast clear. */
++gceSTATUS
++gckVGHARDWARE_SetFastClear(
++ IN gckVGHARDWARE Hardware,
++ IN gctINT Enable
++ );
++
++gceSTATUS
++gckVGHARDWARE_ReadInterrupt(
++ IN gckVGHARDWARE Hardware,
++ OUT gctUINT32_PTR IDs
++ );
++
++/* Power management. */
++gceSTATUS
++gckVGHARDWARE_SetPowerManagementState(
++ IN gckVGHARDWARE Hardware,
++ IN gceCHIPPOWERSTATE State
++ );
++
++gceSTATUS
++gckVGHARDWARE_QueryPowerManagementState(
++ IN gckVGHARDWARE Hardware,
++ OUT gceCHIPPOWERSTATE* State
++ );
++
++gceSTATUS
++gckVGHARDWARE_SetPowerManagement(
++ IN gckVGHARDWARE Hardware,
++ IN gctBOOL PowerManagement
++ );
++
++gceSTATUS
++gckVGHARDWARE_SetPowerOffTimeout(
++ IN gckVGHARDWARE Hardware,
++ IN gctUINT32 Timeout
++ );
++
++gceSTATUS
++gckVGHARDWARE_QueryPowerOffTimeout(
++ IN gckVGHARDWARE Hardware,
++ OUT gctUINT32* Timeout
++ );
++
++gceSTATUS
++gckVGHARDWARE_QueryIdle(
++ IN gckVGHARDWARE Hardware,
++ OUT gctBOOL_PTR IsIdle
++ );
++/******************************************************************************\
++*************************** Command Buffer Structures **************************
++\******************************************************************************/
++
++/* Vacant command buffer marker. */
++#define gcvVACANT_BUFFER ((gcsCOMPLETION_SIGNAL_PTR) (1))
++
++/* Command buffer header. */
++typedef struct _gcsCMDBUFFER * gcsCMDBUFFER_PTR;
++typedef struct _gcsCMDBUFFER
++{
++ /* Pointer to the completion signal. */
++ gcsCOMPLETION_SIGNAL_PTR completion;
++
++ /* The user sets this to the node of the container buffer whitin which
++ this particular command buffer resides. The kernel sets this to the
++ node of the internally allocated buffer. */
++ gctUINT64 node;
++
++ /* Command buffer hardware address. */
++ gctUINT32 address;
++
++ /* The offset of the buffer from the beginning of the header. */
++ gctUINT32 bufferOffset;
++
++ /* Size of the area allocated for the data portion of this particular
++ command buffer (headers and tail reserves are excluded). */
++ gctSIZE_T size;
++
++ /* Offset into the buffer [0..size]; reflects exactly how much data has
++ been put into the command buffer. */
++ gctUINT offset;
++
++ /* The number of command units in the buffer for the hardware to
++ execute. */
++ gctSIZE_T dataCount;
++
++ /* MANAGED BY : user HAL (gcoBUFFER object).
++ USED BY : user HAL (gcoBUFFER object).
++ Points to the immediate next allocated command buffer. */
++ gcsCMDBUFFER_PTR nextAllocated;
++
++ /* MANAGED BY : user layers (HAL and drivers).
++ USED BY : kernel HAL (gcoBUFFER object).
++ Points to the next subbuffer if any. A family of subbuffers are chained
++ together and are meant to be executed inseparably as a unit. Meaning
++ that context switching cannot occur while a chain of subbuffers is being
++ executed. */
++ gcsCMDBUFFER_PTR nextSubBuffer;
++}
++gcsCMDBUFFER;
++
++/* Command queue element. */
++typedef struct _gcsVGCMDQUEUE
++{
++ /* Pointer to the command buffer header. */
++ gcsCMDBUFFER_PTR commandBuffer;
++
++ /* Dynamic vs. static command buffer state. */
++ gctBOOL dynamic;
++}
++gcsVGCMDQUEUE;
++
++/* Context map entry. */
++typedef struct _gcsVGCONTEXT_MAP
++{
++ /* State index. */
++ gctUINT32 index;
++
++ /* New state value. */
++ gctUINT32 data;
++
++ /* Points to the next entry in the mod list. */
++ gcsVGCONTEXT_MAP_PTR next;
++}
++gcsVGCONTEXT_MAP;
++
++/* gcsVGCONTEXT structure that holds the current context. */
++typedef struct _gcsVGCONTEXT
++{
++ /* Context ID. */
++ gctUINT64 id;
++
++ /* State caching ebable flag. */
++ gctBOOL stateCachingEnabled;
++
++ /* Current pipe. */
++ gctUINT32 currentPipe;
++
++ /* State map/mod buffer. */
++ gctSIZE_T mapFirst;
++ gctSIZE_T mapLast;
++#ifdef __QNXNTO__
++ gctSIZE_T mapContainerSize;
++#endif
++ gcsVGCONTEXT_MAP_PTR mapContainer;
++ gcsVGCONTEXT_MAP_PTR mapPrev;
++ gcsVGCONTEXT_MAP_PTR mapCurr;
++ gcsVGCONTEXT_MAP_PTR firstPrevMap;
++ gcsVGCONTEXT_MAP_PTR firstCurrMap;
++
++ /* Main context buffer. */
++ gcsCMDBUFFER_PTR header;
++ gctUINT32_PTR buffer;
++
++ /* Completion signal. */
++ gctHANDLE process;
++ gctSIGNAL signal;
++
++#if defined(__QNXNTO__)
++ gctINT32 coid;
++ gctINT32 rcvid;
++#endif
++}
++gcsVGCONTEXT;
++
++/* User space task header. */
++typedef struct _gcsTASK * gcsTASK_PTR;
++typedef struct _gcsTASK
++{
++ /* Pointer to the next task for the same interrupt in user space. */
++ gcsTASK_PTR next;
++
++ /* Size of the task data that immediately follows the structure. */
++ gctUINT size;
++
++ /* Task data starts here. */
++ /* ... */
++}
++gcsTASK;
++
++/* User space task master table entry. */
++typedef struct _gcsTASK_MASTER_ENTRY * gcsTASK_MASTER_ENTRY_PTR;
++typedef struct _gcsTASK_MASTER_ENTRY
++{
++ /* Pointers to the head and to the tail of the task chain. */
++ gcsTASK_PTR head;
++ gcsTASK_PTR tail;
++}
++gcsTASK_MASTER_ENTRY;
++
++/* User space task master table entry. */
++typedef struct _gcsTASK_MASTER_TABLE
++{
++ /* Table with one entry per block. */
++ gcsTASK_MASTER_ENTRY table[gcvBLOCK_COUNT];
++
++ /* The total number of tasks sckeduled. */
++ gctUINT count;
++
++ /* The total size of event data in bytes. */
++ gctUINT size;
++
++#if defined(__QNXNTO__)
++ gctINT32 coid;
++ gctINT32 rcvid;
++#endif
++}
++gcsTASK_MASTER_TABLE;
++
++/******************************************************************************\
++***************************** gckVGINTERRUPT Object ******************************
++\******************************************************************************/
++
++typedef struct _gckVGINTERRUPT * gckVGINTERRUPT;
++
++typedef gceSTATUS (* gctINTERRUPT_HANDLER)(
++ IN gckVGKERNEL Kernel
++ );
++
++gceSTATUS
++gckVGINTERRUPT_Construct(
++ IN gckVGKERNEL Kernel,
++ OUT gckVGINTERRUPT * Interrupt
++ );
++
++gceSTATUS
++gckVGINTERRUPT_Destroy(
++ IN gckVGINTERRUPT Interrupt
++ );
++
++gceSTATUS
++gckVGINTERRUPT_Enable(
++ IN gckVGINTERRUPT Interrupt,
++ IN OUT gctINT32_PTR Id,
++ IN gctINTERRUPT_HANDLER Handler
++ );
++
++gceSTATUS
++gckVGINTERRUPT_Disable(
++ IN gckVGINTERRUPT Interrupt,
++ IN gctINT32 Id
++ );
++
++#ifndef __QNXNTO__
++
++gceSTATUS
++gckVGINTERRUPT_Enque(
++ IN gckVGINTERRUPT Interrupt
++ );
++
++#else
++
++gceSTATUS
++gckVGINTERRUPT_Enque(
++ IN gckVGINTERRUPT Interrupt,
++ OUT gckOS *Os,
++ OUT gctSEMAPHORE *Semaphore
++ );
++
++#endif
++
++gceSTATUS
++gckVGINTERRUPT_DumpState(
++ IN gckVGINTERRUPT Interrupt
++ );
++
++
++/******************************************************************************\
++******************************* gckVGCOMMAND Object *******************************
++\******************************************************************************/
++
++typedef struct _gckVGCOMMAND * gckVGCOMMAND;
++
++/* Construct a new gckVGCOMMAND object. */
++gceSTATUS
++gckVGCOMMAND_Construct(
++ IN gckVGKERNEL Kernel,
++ IN gctUINT TaskGranularity,
++ IN gctUINT QueueSize,
++ OUT gckVGCOMMAND * Command
++ );
++
++/* Destroy an gckVGCOMMAND object. */
++gceSTATUS
++gckVGCOMMAND_Destroy(
++ IN gckVGCOMMAND Command
++ );
++
++/* Query command buffer attributes. */
++gceSTATUS
++gckVGCOMMAND_QueryCommandBuffer(
++ IN gckVGCOMMAND Command,
++ OUT gcsCOMMAND_BUFFER_INFO_PTR Information
++ );
++
++/* Allocate a command queue. */
++gceSTATUS
++gckVGCOMMAND_Allocate(
++ IN gckVGCOMMAND Command,
++ IN gctSIZE_T Size,
++ OUT gcsCMDBUFFER_PTR * CommandBuffer,
++ OUT gctPOINTER * Data
++ );
++
++/* Release memory held by the command queue. */
++gceSTATUS
++gckVGCOMMAND_Free(
++ IN gckVGCOMMAND Command,
++ IN gcsCMDBUFFER_PTR CommandBuffer
++ );
++
++/* Schedule the command queue for execution. */
++gceSTATUS
++gckVGCOMMAND_Execute(
++ IN gckVGCOMMAND Command,
++ IN gcsCMDBUFFER_PTR CommandBuffer
++ );
++
++/* Commit a buffer to the command queue. */
++gceSTATUS
++gckVGCOMMAND_Commit(
++ IN gckVGCOMMAND Command,
++ IN gcsVGCONTEXT_PTR Context,
++ IN gcsVGCMDQUEUE_PTR Queue,
++ IN gctUINT EntryCount,
++ IN gcsTASK_MASTER_TABLE_PTR TaskTable
++ );
++
++/******************************************************************************\
++********************************* gckVGMMU Object ********************************
++\******************************************************************************/
++
++typedef struct _gckVGMMU * gckVGMMU;
++
++/* Construct a new gckVGMMU object. */
++gceSTATUS
++gckVGMMU_Construct(
++ IN gckVGKERNEL Kernel,
++ IN gctSIZE_T MmuSize,
++ OUT gckVGMMU * Mmu
++ );
++
++/* Destroy an gckVGMMU object. */
++gceSTATUS
++gckVGMMU_Destroy(
++ IN gckVGMMU Mmu
++ );
++
++/* Allocate pages inside the MMU. */
++gceSTATUS
++gckVGMMU_AllocatePages(
++ IN gckVGMMU Mmu,
++ IN gctSIZE_T PageCount,
++ OUT gctPOINTER * PageTable,
++ OUT gctUINT32 * Address
++ );
++
++/* Remove a page table from the MMU. */
++gceSTATUS
++gckVGMMU_FreePages(
++ IN gckVGMMU Mmu,
++ IN gctPOINTER PageTable,
++ IN gctSIZE_T PageCount
++ );
++
++/* Set the MMU page with info. */
++gceSTATUS
++gckVGMMU_SetPage(
++ IN gckVGMMU Mmu,
++ IN gctUINT32 PageAddress,
++ IN gctUINT32 *PageEntry
++ );
++
++/* Flush MMU */
++gceSTATUS
++gckVGMMU_Flush(
++ IN gckVGMMU Mmu
++ );
++
++#endif /* gcdENABLE_VG */
++
++#ifdef __cplusplus
++} /* extern "C" */
++#endif
++
++#endif /* __gc_hal_h_ */
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/os/linux/kernel/allocator/default/gc_hal_kernel_allocator_array.h linux-xbian-imx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/allocator/default/gc_hal_kernel_allocator_array.h
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/os/linux/kernel/allocator/default/gc_hal_kernel_allocator_array.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/allocator/default/gc_hal_kernel_allocator_array.h 2015-07-27 23:13:06.218794344 +0200
+@@ -0,0 +1,34 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++extern gceSTATUS
++_DefaultAlloctorInit(
++ IN gckOS Os,
++ OUT gckALLOCATOR * Allocator
++ );
++
++gcsALLOCATOR_DESC allocatorArray[] =
++{
++ /* Default allocator. */
++ gcmkDEFINE_ALLOCATOR_DESC("default", _DefaultAlloctorInit),
++};
++
++
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/os/linux/kernel/allocator/freescale/gc_hal_kernel_allocator_array.h linux-xbian-imx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/allocator/freescale/gc_hal_kernel_allocator_array.h
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/os/linux/kernel/allocator/freescale/gc_hal_kernel_allocator_array.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/allocator/freescale/gc_hal_kernel_allocator_array.h 2015-07-27 23:13:06.218794344 +0200
+@@ -0,0 +1,45 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++extern gceSTATUS
++_DefaultAlloctorInit(
++ IN gckOS Os,
++ OUT gckALLOCATOR * Allocator
++ );
++
++#if LINUX_CMA_FSL
++gceSTATUS
++_CMAFSLAlloctorInit(
++ IN gckOS Os,
++ OUT gckALLOCATOR * Allocator
++ );
++#endif
++
++gcsALLOCATOR_DESC allocatorArray[] =
++{
++#if LINUX_CMA_FSL
++ gcmkDEFINE_ALLOCATOR_DESC("cmafsl", _CMAFSLAlloctorInit),
++#endif
++ /* Default allocator. */
++ gcmkDEFINE_ALLOCATOR_DESC("default", _DefaultAlloctorInit),
++};
++
++
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/os/linux/kernel/allocator/freescale/gc_hal_kernel_allocator_cma.c linux-xbian-imx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/allocator/freescale/gc_hal_kernel_allocator_cma.c
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/os/linux/kernel/allocator/freescale/gc_hal_kernel_allocator_cma.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/allocator/freescale/gc_hal_kernel_allocator_cma.c 2015-07-27 23:13:06.218794344 +0200
+@@ -0,0 +1,412 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_linux.h"
++#include "gc_hal_kernel_allocator.h"
++
++#include <linux/pagemap.h>
++#include <linux/seq_file.h>
++#include <linux/mman.h>
++#include <asm/atomic.h>
++#include <linux/dma-mapping.h>
++#include <linux/slab.h>
++#include <linux/dma-mapping.h>
++
++#define _GC_OBJ_ZONE gcvZONE_OS
++
++typedef struct _gcsCMA_PRIV * gcsCMA_PRIV_PTR;
++typedef struct _gcsCMA_PRIV {
++ gctUINT32 cmasize;
++}
++gcsCMA_PRIV;
++
++struct mdl_cma_priv {
++ gctPOINTER kvaddr;
++ dma_addr_t physical;
++};
++
++int gc_cma_usage_show(struct seq_file* m, void* data)
++{
++ gcsINFO_NODE *node = m->private;
++ gckALLOCATOR Allocator = node->device;
++ gcsCMA_PRIV_PTR priv = Allocator->privateData;
++
++ seq_printf(m, "cma: %u bytes\n", priv->cmasize);
++
++ return 0;
++}
++
++static gcsINFO InfoList[] =
++{
++ {"cmausage", gc_cma_usage_show},
++};
++
++static void
++_DefaultAllocatorDebugfsInit(
++ IN gckALLOCATOR Allocator,
++ IN gckDEBUGFS_DIR Root
++ )
++{
++ gcmkVERIFY_OK(
++ gckDEBUGFS_DIR_Init(&Allocator->debugfsDir, Root->root, "cma"));
++
++ gcmkVERIFY_OK(gckDEBUGFS_DIR_CreateFiles(
++ &Allocator->debugfsDir,
++ InfoList,
++ gcmCOUNTOF(InfoList),
++ Allocator
++ ));
++}
++
++static void
++_DefaultAllocatorDebugfsCleanup(
++ IN gckALLOCATOR Allocator
++ )
++{
++ gcmkVERIFY_OK(gckDEBUGFS_DIR_RemoveFiles(
++ &Allocator->debugfsDir,
++ InfoList,
++ gcmCOUNTOF(InfoList)
++ ));
++
++ gckDEBUGFS_DIR_Deinit(&Allocator->debugfsDir);
++}
++
++static gceSTATUS
++_CMAFSLAlloc(
++ IN gckALLOCATOR Allocator,
++ INOUT PLINUX_MDL Mdl,
++ IN gctSIZE_T NumPages,
++ IN gctUINT32 Flags
++ )
++{
++ gceSTATUS status;
++ gcsCMA_PRIV_PTR priv = (gcsCMA_PRIV_PTR)Allocator->privateData;
++
++ struct mdl_cma_priv *mdl_priv=gcvNULL;
++ gckOS os = Allocator->os;
++
++ gcmkHEADER_ARG("Mdl=%p NumPages=%d", Mdl, NumPages);
++
++ gcmkONERROR(gckOS_Allocate(os, sizeof(struct mdl_cma_priv), (gctPOINTER *)&mdl_priv));
++ mdl_priv->kvaddr = gcvNULL;
++
++ mdl_priv->kvaddr = dma_alloc_writecombine(gcvNULL,
++ NumPages * PAGE_SIZE,
++ &mdl_priv->physical,
++ GFP_KERNEL | gcdNOWARN);
++
++ if (mdl_priv->kvaddr == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ Mdl->priv = mdl_priv;
++ priv->cmasize += NumPages * PAGE_SIZE;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if(mdl_priv)
++ gckOS_Free(os, mdl_priv);
++ gcmkFOOTER();
++ return status;
++}
++
++static void
++_CMAFSLFree(
++ IN gckALLOCATOR Allocator,
++ IN OUT PLINUX_MDL Mdl
++ )
++{
++ gckOS os = Allocator->os;
++ struct mdl_cma_priv *mdl_priv=(struct mdl_cma_priv *)Mdl->priv;
++ gcsCMA_PRIV_PTR priv = (gcsCMA_PRIV_PTR)Allocator->privateData;
++ dma_free_writecombine(gcvNULL,
++ Mdl->numPages * PAGE_SIZE,
++ mdl_priv->kvaddr,
++ mdl_priv->physical);
++ gckOS_Free(os, mdl_priv);
++ priv->cmasize -= Mdl->numPages * PAGE_SIZE;
++}
++
++gctINT
++_CMAFSLMapUser(
++ gckALLOCATOR Allocator,
++ PLINUX_MDL Mdl,
++ PLINUX_MDL_MAP MdlMap,
++ gctBOOL Cacheable
++ )
++{
++
++ PLINUX_MDL mdl = Mdl;
++ PLINUX_MDL_MAP mdlMap = MdlMap;
++ struct mdl_cma_priv *mdl_priv=(struct mdl_cma_priv *)Mdl->priv;
++
++ gcmkHEADER_ARG("Allocator=%p Mdl=%p MdlMap=%p gctBOOL=%d", Allocator, Mdl, MdlMap, Cacheable);
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0)
++ mdlMap->vmaAddr = (gctSTRING)vm_mmap(gcvNULL,
++ 0L,
++ mdl->numPages * PAGE_SIZE,
++ PROT_READ | PROT_WRITE,
++ MAP_SHARED,
++ 0);
++#else
++ down_write(&current->mm->mmap_sem);
++
++ mdlMap->vmaAddr = (gctSTRING)do_mmap_pgoff(gcvNULL,
++ 0L,
++ mdl->numPages * PAGE_SIZE,
++ PROT_READ | PROT_WRITE,
++ MAP_SHARED,
++ 0);
++
++ up_write(&current->mm->mmap_sem);
++#endif
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): vmaAddr->0x%X for phys_addr->0x%X",
++ __FUNCTION__, __LINE__,
++ (gctUINT32)(gctUINTPTR_T)mdlMap->vmaAddr,
++ (gctUINT32)(gctUINTPTR_T)mdl
++ );
++
++ if (IS_ERR(mdlMap->vmaAddr))
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): do_mmap_pgoff error",
++ __FUNCTION__, __LINE__
++ );
++
++ mdlMap->vmaAddr = gcvNULL;
++
++ gcmkFOOTER_ARG("*status=%d", gcvSTATUS_OUT_OF_MEMORY);
++ return gcvSTATUS_OUT_OF_MEMORY;
++ }
++
++ down_write(&current->mm->mmap_sem);
++
++ mdlMap->vma = find_vma(current->mm, (unsigned long)mdlMap->vmaAddr);
++
++ if (mdlMap->vma == gcvNULL)
++ {
++ up_write(&current->mm->mmap_sem);
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): find_vma error",
++ __FUNCTION__, __LINE__
++ );
++
++ mdlMap->vmaAddr = gcvNULL;
++
++ gcmkFOOTER_ARG("*status=%d", gcvSTATUS_OUT_OF_RESOURCES);
++ return gcvSTATUS_OUT_OF_RESOURCES;
++ }
++
++ /* Now map all the vmalloc pages to this user address. */
++ if (mdl->contiguous)
++ {
++ /* map kernel memory to user space.. */
++ if (dma_mmap_writecombine(gcvNULL,
++ mdlMap->vma,
++ mdl_priv->kvaddr,
++ mdl_priv->physical,
++ mdl->numPages * PAGE_SIZE) < 0)
++ {
++ up_write(&current->mm->mmap_sem);
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_WARNING, gcvZONE_OS,
++ "%s(%d): dma_mmap_attrs error",
++ __FUNCTION__, __LINE__
++ );
++
++ mdlMap->vmaAddr = gcvNULL;
++
++ gcmkFOOTER_ARG("*status=%d", gcvSTATUS_OUT_OF_MEMORY);
++ return gcvSTATUS_OUT_OF_MEMORY;
++ }
++ }
++ else
++ {
++ gckOS_Print("incorrect mdl:conti%d\n",mdl->contiguous);
++ }
++
++ up_write(&current->mm->mmap_sem);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++void
++_CMAUnmapUser(
++ IN gckALLOCATOR Allocator,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Size
++ )
++{
++ if (unlikely(current->mm == gcvNULL))
++ {
++ /* Do nothing if process is exiting. */
++ return;
++ }
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,4,0)
++ if (vm_munmap((unsigned long)Logical, Size) < 0)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_WARNING, gcvZONE_OS,
++ "%s(%d): vm_munmap failed",
++ __FUNCTION__, __LINE__
++ );
++ }
++#else
++ down_write(&current->mm->mmap_sem);
++ if (do_munmap(current->mm, (unsigned long)Logical, Size) < 0)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_WARNING, gcvZONE_OS,
++ "%s(%d): do_munmap failed",
++ __FUNCTION__, __LINE__
++ );
++ }
++ up_write(&current->mm->mmap_sem);
++#endif
++}
++
++gceSTATUS
++_CMAMapKernel(
++ IN gckALLOCATOR Allocator,
++ IN PLINUX_MDL Mdl,
++ OUT gctPOINTER *Logical
++ )
++{
++ struct mdl_cma_priv *mdl_priv=(struct mdl_cma_priv *)Mdl->priv;
++ *Logical =mdl_priv->kvaddr;
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++_CMAUnmapKernel(
++ IN gckALLOCATOR Allocator,
++ IN PLINUX_MDL Mdl,
++ IN gctPOINTER Logical
++ )
++{
++ return gcvSTATUS_OK;
++}
++
++extern gceSTATUS
++_DefaultLogicalToPhysical(
++ IN gckALLOCATOR Allocator,
++ IN PLINUX_MDL Mdl,
++ IN gctPOINTER Logical,
++ IN gctUINT32 ProcessID,
++ OUT gctUINT32_PTR Physical
++ );
++
++extern gceSTATUS
++_DefaultCache(
++ IN gckALLOCATOR Allocator,
++ IN PLINUX_MDL Mdl,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Physical,
++ IN gctUINT32 Bytes,
++ IN gceCACHEOPERATION Operation
++ );
++
++gceSTATUS
++_CMAPhysical(
++ IN gckALLOCATOR Allocator,
++ IN PLINUX_MDL Mdl,
++ IN gctUINT32 Offset,
++ OUT gctUINT32_PTR Physical
++ )
++{
++ struct mdl_cma_priv *mdl_priv=(struct mdl_cma_priv *)Mdl->priv;
++ gcmkASSERT(!Offset);
++ *Physical = mdl_priv->physical;
++
++ return gcvSTATUS_OK;
++}
++
++
++extern void
++_DefaultAllocatorDestructor(
++ IN void* PrivateData
++ );
++
++/* Default allocator operations. */
++gcsALLOCATOR_OPERATIONS CMAFSLAllocatorOperations = {
++ .Alloc = _CMAFSLAlloc,
++ .Free = _CMAFSLFree,
++ .MapUser = _CMAFSLMapUser,
++ .UnmapUser = _CMAUnmapUser,
++ .MapKernel = _CMAMapKernel,
++ .UnmapKernel = _CMAUnmapKernel,
++ .LogicalToPhysical = _DefaultLogicalToPhysical,
++ .Cache = _DefaultCache,
++ .Physical = _CMAPhysical,
++};
++
++/* Default allocator entry. */
++gceSTATUS
++_CMAFSLAlloctorInit(
++ IN gckOS Os,
++ OUT gckALLOCATOR * Allocator
++ )
++{
++ gceSTATUS status;
++ gckALLOCATOR allocator;
++ gcsCMA_PRIV_PTR priv = gcvNULL;
++
++ gcmkONERROR(
++ gckALLOCATOR_Construct(Os, &CMAFSLAllocatorOperations, &allocator));
++
++ priv = kzalloc(gcmSIZEOF(gcsCMA_PRIV), GFP_KERNEL | gcdNOWARN);
++
++ if (!priv)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ /* Register private data. */
++ allocator->privateData = priv;
++ allocator->privateDataDestructor = _DefaultAllocatorDestructor;
++
++ allocator->debugfsInit = _DefaultAllocatorDebugfsInit;
++ allocator->debugfsCleanup = _DefaultAllocatorDebugfsCleanup;
++
++ allocator->capability = gcvALLOC_FLAG_CONTIGUOUS;
++
++ *Allocator = allocator;
++
++ return gcvSTATUS_OK;
++
++OnError:
++ return status;
++}
++
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_allocator.c linux-xbian-imx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_allocator.c
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_allocator.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_allocator.c 2015-07-27 23:13:06.222780123 +0200
+@@ -0,0 +1,938 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_linux.h"
++#include "gc_hal_kernel_allocator.h"
++#include <linux/pagemap.h>
++#include <linux/seq_file.h>
++#include <linux/mman.h>
++#include <asm/atomic.h>
++#include <linux/dma-mapping.h>
++#include <linux/slab.h>
++
++#include "gc_hal_kernel_allocator_array.h"
++#include "gc_hal_kernel_platform.h"
++
++#define _GC_OBJ_ZONE gcvZONE_OS
++
++typedef struct _gcsDEFAULT_PRIV * gcsDEFAULT_PRIV_PTR;
++typedef struct _gcsDEFAULT_PRIV {
++ gctUINT32 low;
++ gctUINT32 high;
++}
++gcsDEFAULT_PRIV;
++
++/******************************************************************************\
++************************** Default Allocator Debugfs ***************************
++\******************************************************************************/
++
++int gc_usage_show(struct seq_file* m, void* data)
++{
++ gcsINFO_NODE *node = m->private;
++ gckALLOCATOR Allocator = node->device;
++ gcsDEFAULT_PRIV_PTR priv = Allocator->privateData;
++
++ seq_printf(m, "low: %u bytes\n", priv->low);
++ seq_printf(m, "high: %u bytes\n", priv->high);
++
++ return 0;
++}
++
++static gcsINFO InfoList[] =
++{
++ {"lowHighUsage", gc_usage_show},
++};
++
++static void
++_DefaultAllocatorDebugfsInit(
++ IN gckALLOCATOR Allocator,
++ IN gckDEBUGFS_DIR Root
++ )
++{
++ gcmkVERIFY_OK(
++ gckDEBUGFS_DIR_Init(&Allocator->debugfsDir, Root->root, "default"));
++
++ gcmkVERIFY_OK(gckDEBUGFS_DIR_CreateFiles(
++ &Allocator->debugfsDir,
++ InfoList,
++ gcmCOUNTOF(InfoList),
++ Allocator
++ ));
++}
++
++static void
++_DefaultAllocatorDebugfsCleanup(
++ IN gckALLOCATOR Allocator
++ )
++{
++ gcmkVERIFY_OK(gckDEBUGFS_DIR_RemoveFiles(
++ &Allocator->debugfsDir,
++ InfoList,
++ gcmCOUNTOF(InfoList)
++ ));
++
++ gckDEBUGFS_DIR_Deinit(&Allocator->debugfsDir);
++}
++
++
++static void
++_NonContiguousFree(
++ IN struct page ** Pages,
++ IN gctUINT32 NumPages
++ )
++{
++ gctINT i;
++
++ gcmkHEADER_ARG("Pages=0x%X, NumPages=%d", Pages, NumPages);
++
++ gcmkASSERT(Pages != gcvNULL);
++
++ for (i = 0; i < NumPages; i++)
++ {
++ __free_page(Pages[i]);
++ }
++
++ if (is_vmalloc_addr(Pages))
++ {
++ vfree(Pages);
++ }
++ else
++ {
++ kfree(Pages);
++ }
++
++ gcmkFOOTER_NO();
++}
++
++static struct page **
++_NonContiguousAlloc(
++ IN gctUINT32 NumPages
++ )
++{
++ struct page ** pages;
++ struct page *p;
++ gctINT i, size;
++
++ gcmkHEADER_ARG("NumPages=%lu", NumPages);
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 32)
++ if (NumPages > totalram_pages)
++#else
++ if (NumPages > num_physpages)
++#endif
++ {
++ gcmkFOOTER_NO();
++ return gcvNULL;
++ }
++
++ size = NumPages * sizeof(struct page *);
++
++ pages = kmalloc(size, GFP_KERNEL | gcdNOWARN);
++
++ if (!pages)
++ {
++ pages = vmalloc(size);
++
++ if (!pages)
++ {
++ gcmkFOOTER_NO();
++ return gcvNULL;
++ }
++ }
++
++ for (i = 0; i < NumPages; i++)
++ {
++ p = alloc_page(GFP_KERNEL | __GFP_HIGHMEM | gcdNOWARN);
++
++ if (!p)
++ {
++ _NonContiguousFree(pages, i);
++ gcmkFOOTER_NO();
++ return gcvNULL;
++ }
++
++ pages[i] = p;
++ }
++
++ gcmkFOOTER_ARG("pages=0x%X", pages);
++ return pages;
++}
++
++gctSTRING
++_CreateKernelVirtualMapping(
++ IN PLINUX_MDL Mdl
++ )
++{
++ gctSTRING addr = 0;
++ gctINT numPages = Mdl->numPages;
++
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ if (Mdl->contiguous)
++ {
++ addr = page_address(Mdl->u.contiguousPages);
++ }
++ else
++ {
++ addr = vmap(Mdl->u.nonContiguousPages,
++ numPages,
++ 0,
++ PAGE_KERNEL);
++
++ /* Trigger a page fault. */
++ memset(addr, 0, numPages * PAGE_SIZE);
++ }
++#else
++ struct page ** pages;
++ gctBOOL free = gcvFALSE;
++ gctINT i;
++
++ if (Mdl->contiguous)
++ {
++ pages = kmalloc(sizeof(struct page *) * numPages, GFP_KERNEL | gcdNOWARN);
++
++ if (!pages)
++ {
++ return gcvNULL;
++ }
++
++ for (i = 0; i < numPages; i++)
++ {
++ pages[i] = nth_page(Mdl->u.contiguousPages, i);
++ }
++
++ free = gcvTRUE;
++ }
++ else
++ {
++ pages = Mdl->u.nonContiguousPages;
++ }
++
++ /* ioremap() can't work on system memory since 2.6.38. */
++ addr = vmap(pages, numPages, 0, gcmkNONPAGED_MEMROY_PROT(PAGE_KERNEL));
++
++ if (free)
++ {
++ kfree(pages);
++ }
++
++#endif
++
++ return addr;
++}
++
++void
++_DestoryKernelVirtualMapping(
++ IN gctSTRING Addr
++ )
++{
++#if !gcdNONPAGED_MEMORY_CACHEABLE
++ vunmap(Addr);
++#endif
++}
++
++void
++_UnmapUserLogical(
++ IN gctPOINTER Logical,
++ IN gctUINT32 Size
++)
++{
++ if (unlikely(current->mm == gcvNULL))
++ {
++ /* Do nothing if process is exiting. */
++ return;
++ }
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,5,0)
++ if (vm_munmap((unsigned long)Logical, Size) < 0)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_WARNING, gcvZONE_OS,
++ "%s(%d): vm_munmap failed",
++ __FUNCTION__, __LINE__
++ );
++ }
++#else
++ down_write(&current->mm->mmap_sem);
++ if (do_munmap(current->mm, (unsigned long)Logical, Size) < 0)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_WARNING, gcvZONE_OS,
++ "%s(%d): do_munmap failed",
++ __FUNCTION__, __LINE__
++ );
++ }
++ up_write(&current->mm->mmap_sem);
++#endif
++}
++
++/***************************************************************************\
++************************ Default Allocator **********************************
++\***************************************************************************/
++#define C_MAX_PAGENUM (50*1024)
++static gceSTATUS
++_DefaultAlloc(
++ IN gckALLOCATOR Allocator,
++ INOUT PLINUX_MDL Mdl,
++ IN gctSIZE_T NumPages,
++ IN gctUINT32 Flags
++ )
++{
++ gceSTATUS status;
++ gctUINT32 order;
++ gctSIZE_T bytes;
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)
++ gctPOINTER addr = gcvNULL;
++#endif
++ gctUINT32 numPages;
++ gctUINT i = 0;
++ gctBOOL contiguous = Flags & gcvALLOC_FLAG_CONTIGUOUS;
++ struct sysinfo temsysinfo;
++ gcsDEFAULT_PRIV_PTR priv = (gcsDEFAULT_PRIV_PTR)Allocator->privateData;
++
++ gcmkHEADER_ARG("Mdl=%p NumPages=%d", Mdl, NumPages);
++
++ numPages = NumPages;
++ bytes = NumPages * PAGE_SIZE;
++ order = get_order(bytes);
++
++ si_meminfo(&temsysinfo);
++
++ if (Flags & gcvALLOC_FLAG_MEMLIMIT)
++ {
++ if ( (temsysinfo.freeram < NumPages) || ((temsysinfo.freeram-NumPages) < C_MAX_PAGENUM) )
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++ }
++
++ if (contiguous)
++ {
++ if (order >= MAX_ORDER)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)
++ addr =
++ alloc_pages_exact(bytes, GFP_KERNEL | gcdNOWARN | __GFP_NORETRY);
++
++ Mdl->u.contiguousPages = addr
++ ? virt_to_page(addr)
++ : gcvNULL;
++
++ Mdl->exact = gcvTRUE;
++#else
++ Mdl->u.contiguousPages =
++ alloc_pages(GFP_KERNEL | gcdNOWARN | __GFP_NORETRY, order);
++#endif
++
++ if (Mdl->u.contiguousPages == gcvNULL)
++ {
++ Mdl->u.contiguousPages =
++ alloc_pages(GFP_KERNEL | __GFP_HIGHMEM | gcdNOWARN, order);
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)
++ Mdl->exact = gcvFALSE;
++#endif
++ }
++ }
++ else
++ {
++ Mdl->u.nonContiguousPages = _NonContiguousAlloc(numPages);
++ }
++
++ if (Mdl->u.contiguousPages == gcvNULL && Mdl->u.nonContiguousPages == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ for (i = 0; i < numPages; i++)
++ {
++ struct page *page;
++
++ if (contiguous)
++ {
++ page = nth_page(Mdl->u.contiguousPages, i);
++ }
++ else
++ {
++ page = _NonContiguousToPage(Mdl->u.nonContiguousPages, i);
++ }
++
++ SetPageReserved(page);
++
++ if (!PageHighMem(page) && page_to_phys(page))
++ {
++ gcmkVERIFY_OK(
++ gckOS_CacheFlush(Allocator->os, _GetProcessID(), gcvNULL,
++ page_to_phys(page),
++ page_address(page),
++ PAGE_SIZE));
++
++ priv->low += PAGE_SIZE;
++ }
++ else
++ {
++ flush_dcache_page(page);
++
++#if !gcdCACHE_FUNCTION_UNIMPLEMENTED && defined(CONFIG_OUTER_CACHE) && gcdENABLE_OUTER_CACHE_PATCH
++ if (page_to_phys(page))
++ {
++ _HandleOuterCache(
++ Allocator->os,
++ page_to_phys(page),
++ gcvNULL,
++ PAGE_SIZE,
++ gcvCACHE_FLUSH
++ );
++ }
++#endif
++
++ priv->high += PAGE_SIZE;
++ }
++ }
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++static void
++_DefaultFree(
++ IN gckALLOCATOR Allocator,
++ IN OUT PLINUX_MDL Mdl
++ )
++{
++ gctINT i;
++ struct page * page;
++ gcsDEFAULT_PRIV_PTR priv = (gcsDEFAULT_PRIV_PTR)Allocator->privateData;
++
++ for (i = 0; i < Mdl->numPages; i++)
++ {
++ if (Mdl->contiguous)
++ {
++ page = nth_page(Mdl->u.contiguousPages, i);
++ }
++ else
++ {
++ page = _NonContiguousToPage(Mdl->u.nonContiguousPages, i);
++ }
++
++ ClearPageReserved(page);
++
++ if (PageHighMem(page))
++ {
++ priv->high -= PAGE_SIZE;
++ }
++ else
++ {
++ priv->low -= PAGE_SIZE;
++ }
++ }
++
++ if (Mdl->contiguous)
++ {
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)
++ if (Mdl->exact == gcvTRUE)
++ {
++ free_pages_exact(page_address(Mdl->u.contiguousPages), Mdl->numPages * PAGE_SIZE);
++ }
++ else
++#endif
++ {
++ __free_pages(Mdl->u.contiguousPages, get_order(Mdl->numPages * PAGE_SIZE));
++ }
++ }
++ else
++ {
++ _NonContiguousFree(Mdl->u.nonContiguousPages, Mdl->numPages);
++ }
++}
++
++gctINT
++_DefaultMapUser(
++ gckALLOCATOR Allocator,
++ PLINUX_MDL Mdl,
++ PLINUX_MDL_MAP MdlMap,
++ gctBOOL Cacheable
++ )
++{
++
++ gctSTRING addr;
++ unsigned long start;
++ unsigned long pfn;
++ gctINT i;
++ gckOS os = Allocator->os;
++ gcsPLATFORM * platform = os->device->platform;
++
++ PLINUX_MDL mdl = Mdl;
++ PLINUX_MDL_MAP mdlMap = MdlMap;
++
++ gcmkHEADER_ARG("Allocator=%p Mdl=%p MdlMap=%p gctBOOL=%d", Allocator, Mdl, MdlMap, Cacheable);
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0)
++ mdlMap->vmaAddr = (gctSTRING)vm_mmap(gcvNULL,
++ 0L,
++ mdl->numPages * PAGE_SIZE,
++ PROT_READ | PROT_WRITE,
++ MAP_SHARED,
++ 0);
++#else
++ down_write(&current->mm->mmap_sem);
++
++ mdlMap->vmaAddr = (gctSTRING)do_mmap_pgoff(gcvNULL,
++ 0L,
++ mdl->numPages * PAGE_SIZE,
++ PROT_READ | PROT_WRITE,
++ MAP_SHARED,
++ 0);
++
++ up_write(&current->mm->mmap_sem);
++#endif
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): vmaAddr->0x%X for phys_addr->0x%X",
++ __FUNCTION__, __LINE__,
++ (gctUINT32)(gctUINTPTR_T)mdlMap->vmaAddr,
++ (gctUINT32)(gctUINTPTR_T)mdl
++ );
++
++ if (IS_ERR(mdlMap->vmaAddr))
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): do_mmap_pgoff error",
++ __FUNCTION__, __LINE__
++ );
++
++ mdlMap->vmaAddr = gcvNULL;
++
++ gcmkFOOTER_ARG("*status=%d", gcvSTATUS_OUT_OF_MEMORY);
++ return gcvSTATUS_OUT_OF_MEMORY;
++ }
++
++ down_write(&current->mm->mmap_sem);
++
++ mdlMap->vma = find_vma(current->mm, (unsigned long)mdlMap->vmaAddr);
++
++ if (mdlMap->vma == gcvNULL)
++ {
++ up_write(&current->mm->mmap_sem);
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): find_vma error",
++ __FUNCTION__, __LINE__
++ );
++
++ mdlMap->vmaAddr = gcvNULL;
++
++ gcmkFOOTER_ARG("*status=%d", gcvSTATUS_OUT_OF_RESOURCES);
++ return gcvSTATUS_OUT_OF_RESOURCES;
++ }
++
++ mdlMap->vma->vm_flags |= gcdVM_FLAGS;
++
++ if (Cacheable == gcvFALSE)
++ {
++ /* Make this mapping non-cached. */
++ mdlMap->vma->vm_page_prot = gcmkPAGED_MEMROY_PROT(mdlMap->vma->vm_page_prot);
++ }
++
++ if (platform && platform->ops->adjustProt)
++ {
++ platform->ops->adjustProt(mdlMap->vma);
++ }
++
++ addr = mdl->addr;
++
++ /* Now map all the vmalloc pages to this user address. */
++ if (mdl->contiguous)
++ {
++ /* map kernel memory to user space.. */
++ if (remap_pfn_range(mdlMap->vma,
++ mdlMap->vma->vm_start,
++ page_to_pfn(mdl->u.contiguousPages),
++ mdlMap->vma->vm_end - mdlMap->vma->vm_start,
++ mdlMap->vma->vm_page_prot) < 0)
++ {
++ up_write(&current->mm->mmap_sem);
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): unable to mmap ret",
++ __FUNCTION__, __LINE__
++ );
++
++ mdlMap->vmaAddr = gcvNULL;
++
++ gcmkFOOTER_ARG("*status=%d", gcvSTATUS_OUT_OF_MEMORY);
++ return gcvSTATUS_OUT_OF_MEMORY;
++ }
++ }
++ else
++ {
++ start = mdlMap->vma->vm_start;
++
++ for (i = 0; i < mdl->numPages; i++)
++ {
++ pfn = _NonContiguousToPfn(mdl->u.nonContiguousPages, i);
++
++ if (remap_pfn_range(mdlMap->vma,
++ start,
++ pfn,
++ PAGE_SIZE,
++ mdlMap->vma->vm_page_prot) < 0)
++ {
++ up_write(&current->mm->mmap_sem);
++
++ mdlMap->vmaAddr = gcvNULL;
++
++ gcmkFOOTER_ARG("*status=%d", gcvSTATUS_OUT_OF_MEMORY);
++ return gcvSTATUS_OUT_OF_MEMORY;
++ }
++
++ start += PAGE_SIZE;
++ addr += PAGE_SIZE;
++ }
++ }
++
++ up_write(&current->mm->mmap_sem);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++void
++_DefaultUnmapUser(
++ IN gckALLOCATOR Allocator,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Size
++ )
++{
++ _UnmapUserLogical(Logical, Size);
++}
++
++gceSTATUS
++_DefaultMapKernel(
++ IN gckALLOCATOR Allocator,
++ IN PLINUX_MDL Mdl,
++ OUT gctPOINTER *Logical
++ )
++{
++ *Logical = _CreateKernelVirtualMapping(Mdl);
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++_DefaultUnmapKernel(
++ IN gckALLOCATOR Allocator,
++ IN PLINUX_MDL Mdl,
++ IN gctPOINTER Logical
++ )
++{
++ _DestoryKernelVirtualMapping(Logical);
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++_DefaultLogicalToPhysical(
++ IN gckALLOCATOR Allocator,
++ IN PLINUX_MDL Mdl,
++ IN gctPOINTER Logical,
++ IN gctUINT32 ProcessID,
++ OUT gctUINT32_PTR Physical
++ )
++{
++ return _ConvertLogical2Physical(
++ Allocator->os, Logical, ProcessID, Mdl, Physical);
++}
++
++gceSTATUS
++_DefaultCache(
++ IN gckALLOCATOR Allocator,
++ IN PLINUX_MDL Mdl,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Physical,
++ IN gctUINT32 Bytes,
++ IN gceCACHEOPERATION Operation
++ )
++{
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++_DefaultPhysical(
++ IN gckALLOCATOR Allocator,
++ IN PLINUX_MDL Mdl,
++ IN gctUINT32 Offset,
++ OUT gctUINT32_PTR Physical
++ )
++{
++ gcmkASSERT(Mdl->pagedMem && !Mdl->contiguous);
++ *Physical = _NonContiguousToPhys(Mdl->u.nonContiguousPages, Offset);
++
++ return gcvSTATUS_OK;
++}
++
++void
++_DefaultAllocatorDestructor(
++ IN void* PrivateData
++ )
++{
++ kfree(PrivateData);
++}
++
++/* Default allocator operations. */
++gcsALLOCATOR_OPERATIONS DefaultAllocatorOperations = {
++ .Alloc = _DefaultAlloc,
++ .Free = _DefaultFree,
++ .MapUser = _DefaultMapUser,
++ .UnmapUser = _DefaultUnmapUser,
++ .MapKernel = _DefaultMapKernel,
++ .UnmapKernel = _DefaultUnmapKernel,
++ .LogicalToPhysical = _DefaultLogicalToPhysical,
++ .Cache = _DefaultCache,
++ .Physical = _DefaultPhysical,
++};
++
++/* Default allocator entry. */
++gceSTATUS
++_DefaultAlloctorInit(
++ IN gckOS Os,
++ OUT gckALLOCATOR * Allocator
++ )
++{
++ gceSTATUS status;
++ gckALLOCATOR allocator;
++ gcsDEFAULT_PRIV_PTR priv = gcvNULL;
++
++ gcmkONERROR(
++ gckALLOCATOR_Construct(Os, &DefaultAllocatorOperations, &allocator));
++
++ priv = kzalloc(gcmSIZEOF(gcsDEFAULT_PRIV), GFP_KERNEL | gcdNOWARN);
++
++ if (!priv)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ /* Register private data. */
++ allocator->privateData = priv;
++ allocator->privateDataDestructor = _DefaultAllocatorDestructor;
++
++ allocator->debugfsInit = _DefaultAllocatorDebugfsInit;
++ allocator->debugfsCleanup = _DefaultAllocatorDebugfsCleanup;
++
++ *Allocator = allocator;
++
++ return gcvSTATUS_OK;
++
++OnError:
++ return status;
++}
++
++/***************************************************************************\
++************************ Allocator helper ***********************************
++\***************************************************************************/
++
++gceSTATUS
++gckALLOCATOR_Construct(
++ IN gckOS Os,
++ IN gcsALLOCATOR_OPERATIONS * Operations,
++ OUT gckALLOCATOR * Allocator
++ )
++{
++ gceSTATUS status;
++ gckALLOCATOR allocator;
++
++ gcmkHEADER_ARG("Os=%p, Operations=%p, Allocator=%p",
++ Os, Operations, Allocator);
++
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Allocator != gcvNULL);
++ gcmkVERIFY_ARGUMENT
++ ( Operations
++ && Operations->Alloc
++ && Operations->Free
++ && Operations->MapUser
++ && Operations->UnmapUser
++ && Operations->MapKernel
++ && Operations->UnmapKernel
++ && Operations->LogicalToPhysical
++ && Operations->Cache
++ && Operations->Physical
++ );
++
++ gcmkONERROR(
++ gckOS_Allocate(Os, gcmSIZEOF(gcsALLOCATOR), (gctPOINTER *)&allocator));
++
++ gckOS_ZeroMemory(allocator, gcmSIZEOF(gcsALLOCATOR));
++
++ /* Record os. */
++ allocator->os = Os;
++
++ /* Set operations. */
++ allocator->ops = Operations;
++
++ allocator->capability = gcvALLOC_FLAG_CONTIGUOUS
++ | gcvALLOC_FLAG_NON_CONTIGUOUS
++ | gcvALLOC_FLAG_CACHEABLE
++ | gcvALLOC_FLAG_MEMLIMIT;
++ ;
++
++ *Allocator = allocator;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++/******************************************************************************\
++******************************** Debugfs Support *******************************
++\******************************************************************************/
++
++static gceSTATUS
++_AllocatorDebugfsInit(
++ IN gckOS Os
++ )
++{
++ gceSTATUS status;
++ gckGALDEVICE device = Os->device;
++
++ gckDEBUGFS_DIR dir = &Os->allocatorDebugfsDir;
++
++ gcmkONERROR(gckDEBUGFS_DIR_Init(dir, device->debugfsDir.root, "allocators"));
++
++ return gcvSTATUS_OK;
++
++OnError:
++ return status;
++}
++
++static void
++_AllocatorDebugfsCleanup(
++ IN gckOS Os
++ )
++{
++ gckDEBUGFS_DIR dir = &Os->allocatorDebugfsDir;
++
++ gckDEBUGFS_DIR_Deinit(dir);
++}
++
++/***************************************************************************\
++************************ Allocator management *******************************
++\***************************************************************************/
++
++gceSTATUS
++gckOS_ImportAllocators(
++ gckOS Os
++ )
++{
++ gceSTATUS status;
++ gctUINT i;
++ gckALLOCATOR allocator;
++
++ _AllocatorDebugfsInit(Os);
++
++ INIT_LIST_HEAD(&Os->allocatorList);
++
++ for (i = 0; i < gcmCOUNTOF(allocatorArray); i++)
++ {
++ if (allocatorArray[i].construct)
++ {
++ /* Construct allocator. */
++ status = allocatorArray[i].construct(Os, &allocator);
++
++ if (gcmIS_ERROR(status))
++ {
++ gcmkPRINT("["DEVICE_NAME"]: Can't construct allocator(%s)",
++ allocatorArray[i].name);
++
++ continue;
++ }
++
++ allocator->name = allocatorArray[i].name;
++
++ if (allocator->debugfsInit)
++ {
++ /* Init allocator's debugfs. */
++ allocator->debugfsInit(allocator, &Os->allocatorDebugfsDir);
++ }
++
++ list_add_tail(&allocator->head, &Os->allocatorList);
++ }
++ }
++
++#if gcdDEBUG
++ list_for_each_entry(allocator, &Os->allocatorList, head)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_WARNING, gcvZONE_OS,
++ "%s(%d) Allocator: %s",
++ __FUNCTION__, __LINE__,
++ allocator->name
++ );
++ }
++#endif
++
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckOS_FreeAllocators(
++ gckOS Os
++ )
++{
++ gckALLOCATOR allocator;
++ gckALLOCATOR temp;
++
++ list_for_each_entry_safe(allocator, temp, &Os->allocatorList, head)
++ {
++ list_del(&allocator->head);
++
++ if (allocator->debugfsCleanup)
++ {
++ /* Clean up allocator's debugfs. */
++ allocator->debugfsCleanup(allocator);
++ }
++
++ /* Free private data. */
++ if (allocator->privateDataDestructor && allocator->privateData)
++ {
++ allocator->privateDataDestructor(allocator->privateData);
++ }
++
++ gckOS_Free(Os, allocator);
++ }
++
++ _AllocatorDebugfsCleanup(Os);
++
++ return gcvSTATUS_OK;
++}
++
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_allocator.h linux-xbian-imx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_allocator.h
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_allocator.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_allocator.h 2015-07-27 23:13:06.222780123 +0200
+@@ -0,0 +1,400 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_kernel_allocator_h_
++#define __gc_hal_kernel_allocator_h_
++
++#include "gc_hal_kernel_linux.h"
++
++typedef struct _gcsALLOCATOR * gckALLOCATOR;
++
++typedef struct _gcsALLOCATOR_OPERATIONS
++{
++ /**************************************************************************
++ **
++ ** Alloc
++ **
++ ** Allocte memory, request size is page aligned.
++ **
++ ** INPUT:
++ **
++ ** gckALLOCATOR Allocator
++ ** Pointer to an gckALLOCATOER object.
++ **
++ ** PLINUX_Mdl
++ ** Pointer to Mdl whichs stores information
++ ** about allocated memory.
++ **
++ ** gctSIZE_T NumPages
++ ** Number of pages need to allocate.
++ **
++ ** gctUINT32 Flag
++ ** Allocation option.
++ **
++ ** OUTPUT:
++ **
++ ** Nothing.
++ **
++ */
++ gceSTATUS
++ (*Alloc)(
++ IN gckALLOCATOR Allocator,
++ IN PLINUX_MDL Mdl,
++ IN gctSIZE_T NumPages,
++ IN gctUINT32 Flag
++ );
++
++ /**************************************************************************
++ **
++ ** Free
++ **
++ ** Free memory.
++ **
++ ** INPUT:
++ **
++ ** gckALLOCATOR Allocator
++ ** Pointer to an gckALLOCATOER object.
++ **
++ ** PLINUX_MDL Mdl
++ ** Mdl which stores information.
++ **
++ ** OUTPUT:
++ **
++ ** Nothing.
++ **
++ */
++ void
++ (*Free)(
++ IN gckALLOCATOR Allocator,
++ IN PLINUX_MDL Mdl
++ );
++
++ /**************************************************************************
++ **
++ ** MapUser
++ **
++ ** Map memory to user space.
++ **
++ ** INPUT:
++ ** gckALLOCATOR Allocator
++ ** Pointer to an gckALLOCATOER object.
++ **
++ ** PLINUX_MDL Mdl
++ ** Pointer to a Mdl.
++ **
++ ** PLINUX_MDL_MAP MdlMap
++ ** Pointer to a MdlMap, mapped address is stored
++ ** in MdlMap->vmaAddr
++ **
++ ** gctBOOL Cacheable
++ ** Whether this mapping is cacheable.
++ **
++ ** OUTPUT:
++ **
++ ** Nothing.
++ **
++ */
++ gctINT
++ (*MapUser)(
++ IN gckALLOCATOR Allocator,
++ IN PLINUX_MDL Mdl,
++ IN PLINUX_MDL_MAP MdlMap,
++ IN gctBOOL Cacheable
++ );
++
++ /**************************************************************************
++ **
++ ** UnmapUser
++ **
++ ** Unmap address from user address space.
++ **
++ ** INPUT:
++ ** gckALLOCATOR Allocator
++ ** Pointer to an gckALLOCATOER object.
++ **
++ ** gctPOINTER Logical
++ ** Address to be unmap
++ **
++ ** gctUINT32 Size
++ ** Size of address space
++ **
++ ** OUTPUT:
++ **
++ ** Nothing.
++ **
++ */
++ void
++ (*UnmapUser)(
++ IN gckALLOCATOR Allocator,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Size
++ );
++
++ /**************************************************************************
++ **
++ ** MapKernel
++ **
++ ** Map memory to kernel space.
++ **
++ ** INPUT:
++ ** gckALLOCATOR Allocator
++ ** Pointer to an gckALLOCATOER object.
++ **
++ ** PLINUX_MDL Mdl
++ ** Pointer to a Mdl object.
++ **
++ ** OUTPUT:
++ ** gctPOINTER * Logical
++ ** Mapped kernel address.
++ */
++ gceSTATUS
++ (*MapKernel)(
++ IN gckALLOCATOR Allocator,
++ IN PLINUX_MDL Mdl,
++ OUT gctPOINTER *Logical
++ );
++
++ /**************************************************************************
++ **
++ ** UnmapKernel
++ **
++ ** Unmap memory from kernel space.
++ **
++ ** INPUT:
++ ** gckALLOCATOR Allocator
++ ** Pointer to an gckALLOCATOER object.
++ **
++ ** PLINUX_MDL Mdl
++ ** Pointer to a Mdl object.
++ **
++ ** gctPOINTER Logical
++ ** Mapped kernel address.
++ **
++ ** OUTPUT:
++ **
++ ** Nothing.
++ **
++ */
++ gceSTATUS
++ (*UnmapKernel)(
++ IN gckALLOCATOR Allocator,
++ IN PLINUX_MDL Mdl,
++ IN gctPOINTER Logical
++ );
++
++ /**************************************************************************
++ **
++ ** LogicalToPhysical
++ **
++ ** Get physical address from logical address, logical
++ ** address could be user virtual address or kernel
++ ** virtual address.
++ **
++ ** INPUT:
++ ** gckALLOCATOR Allocator
++ ** Pointer to an gckALLOCATOER object.
++ **
++ ** PLINUX_MDL Mdl
++ ** Pointer to a Mdl object.
++ **
++ ** gctPOINTER Logical
++ ** Mapped kernel address.
++ **
++ ** gctUINT32 ProcessID
++ ** pid of current process.
++ ** OUTPUT:
++ **
++ ** gctUINT32_PTR Physical
++ ** Physical address.
++ **
++ */
++ gceSTATUS
++ (*LogicalToPhysical)(
++ IN gckALLOCATOR Allocator,
++ IN PLINUX_MDL Mdl,
++ IN gctPOINTER Logical,
++ IN gctUINT32 ProcessID,
++ OUT gctUINT32_PTR Physical
++ );
++
++ /**************************************************************************
++ **
++ ** Cache
++ **
++ ** Maintain cache coherency.
++ **
++ ** INPUT:
++ ** gckALLOCATOR Allocator
++ ** Pointer to an gckALLOCATOER object.
++ **
++ ** PLINUX_MDL Mdl
++ ** Pointer to a Mdl object.
++ **
++ ** gctPOINTER Logical
++ ** Logical address, could be user address or kernel address
++ **
++ ** gctUINT32_PTR Physical
++ ** Physical address.
++ **
++ ** gctUINT32 Bytes
++ ** Size of memory region.
++ **
++ ** gceCACHEOPERATION Opertaion
++ ** Cache operation.
++ **
++ ** OUTPUT:
++ **
++ ** Nothing.
++ **
++ */
++ gceSTATUS (*Cache)(
++ IN gckALLOCATOR Allocator,
++ IN PLINUX_MDL Mdl,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Physical,
++ IN gctUINT32 Bytes,
++ IN gceCACHEOPERATION Operation
++ );
++
++ /**************************************************************************
++ **
++ ** Physical
++ **
++ ** Get physical address from a offset in memory region.
++ **
++ ** INPUT:
++ ** gckALLOCATOR Allocator
++ ** Pointer to an gckALLOCATOER object.
++ **
++ ** PLINUX_MDL Mdl
++ ** Pointer to a Mdl object.
++ **
++ ** gctUINT32 Offset
++ ** Offset in this memory region.
++ **
++ ** OUTPUT:
++ ** gctUINT32_PTR Physical
++ ** Physical address.
++ **
++ */
++ gceSTATUS (*Physical)(
++ IN gckALLOCATOR Allocator,
++ IN PLINUX_MDL Mdl,
++ IN gctUINT32 Offset,
++ OUT gctUINT32_PTR Physical
++ );
++}
++gcsALLOCATOR_OPERATIONS;
++
++typedef struct _gcsALLOCATOR
++{
++ /* Pointer to gckOS Object. */
++ gckOS os;
++
++ /* Name. */
++ gctSTRING name;
++
++ /* Operations. */
++ gcsALLOCATOR_OPERATIONS* ops;
++
++ /* Capability of this allocator. */
++ gctUINT32 capability;
++
++ struct list_head head;
++
++ /* Debugfs entry of this allocator. */
++ gcsDEBUGFS_DIR debugfsDir;
++
++ /* Init allocator debugfs. */
++ void (*debugfsInit)(gckALLOCATOR, gckDEBUGFS_DIR);
++
++ /* Cleanup allocator debugfs. */
++ void (*debugfsCleanup)(gckALLOCATOR);
++
++ /* Private data used by customer allocator. */
++ void * privateData;
++
++ /* Private data destructor. */
++ void (*privateDataDestructor)(void *);
++}
++gcsALLOCATOR;
++
++typedef struct _gcsALLOCATOR_DESC
++{
++ /* Name of a allocator. */
++ char * name;
++
++ /* Entry function to construct a allocator. */
++ gceSTATUS (*construct)(gckOS, gckALLOCATOR *);
++}
++gcsALLOCATOR_DESC;
++
++/*
++* Helpers
++*/
++
++/* Fill a gcsALLOCATOR_DESC structure. */
++#define gcmkDEFINE_ALLOCATOR_DESC(Name, Construct) \
++ { \
++ .name = Name, \
++ .construct = Construct, \
++ }
++
++/* Construct a allocator. */
++gceSTATUS
++gckALLOCATOR_Construct(
++ IN gckOS Os,
++ IN gcsALLOCATOR_OPERATIONS * Operations,
++ OUT gckALLOCATOR * Allocator
++ );
++
++/*
++ How to implement customer allocator
++
++ Build in customer alloctor
++
++ It is recommanded that customer allocator is implmented in independent
++ source file(s) which is specified by CUSOMTER_ALLOCATOR_OBJS in Kbuld.
++
++ Register gcsALLOCATOR
++
++ For each customer specified allocator, a desciption entry must be added
++ to allocatorArray defined in gc_hal_kernel_allocator_array.h.
++
++ An entry in allocatorArray is a gcsALLOCATOR_DESC structure which describes
++ name and constructor of a gckALLOCATOR object.
++
++
++ Implement gcsALLOCATOR_DESC.init()
++
++ In gcsALLOCATOR_DESC.init(), gckALLOCATOR_Construct should be called
++ to create a gckALLOCATOR object, customer specified private data can
++ be put in gcsALLOCATOR.privateData.
++
++
++ Implement gcsALLOCATOR_OPERATIONS
++
++ When call gckALLOCATOR_Construct to create a gckALLOCATOR object, a
++ gcsALLOCATOR_OPERATIONS structure must be provided whose all members
++ implemented.
++
++*/
++#endif
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_debugfs.c linux-xbian-imx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_debugfs.c
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_debugfs.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_debugfs.c 2015-07-27 23:13:06.222780123 +0200
+@@ -0,0 +1,795 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifdef MODULE
++#include <linux/module.h>
++#endif
++#include <linux/init.h>
++#include <linux/debugfs.h>
++#include <linux/slab.h>
++#ifdef MODVERSIONS
++#include <linux/modversions.h>
++#endif
++#include <linux/stddef.h>
++#include <linux/sched.h>
++#include <linux/kernel.h>
++#include <linux/timer.h>
++#include <linux/delay.h>
++#include <linux/errno.h>
++#include <linux/mutex.h>
++#include <linux/vmalloc.h>
++#include <linux/types.h>
++#include <linux/fs.h>
++#include <linux/poll.h>
++#include <asm/uaccess.h>
++#include <linux/completion.h>
++#include "gc_hal_kernel_linux.h"
++
++/*
++ Prequsite:
++
++ 1) Debugfs feature must be enabled in the kernel.
++ 1.a) You can enable this, in the compilation of the uImage, all you have to do is, In the "make menuconfig" part,
++ you have to enable the debugfs in the kernel hacking part of the menu.
++
++ HOW TO USE:
++ 1) insert the driver with the following option logFileSize, Ex: insmod galcore.ko ...... logFileSize=10240
++ This gives a circular buffer of 10 MB
++
++ 2)Usually after inserting the driver, the debug file system is mounted under /sys/kernel/debug/
++
++ 2.a)If the debugfs is not mounted, you must do "mount -t debugfs none /sys/kernel/debug"
++
++ 3) To read what is being printed in the debugfs file system:
++ Ex : cat /sys/kernel/debug/gpu/galcore_trace
++
++ 4)To write into the debug file system from user side :
++ Ex: echo "hello" > cat /sys/kernel/debug/gpu/galcore_trace
++
++ 5)To write into debugfs from kernel side, Use the function called gckDebugFileSystemPrint
++
++
++ USECASE Kernel Dump:
++
++ 1) Go to /hal/inc/gc_hal_options.h, and enable the following flags:
++ - # define gcdDUMP 1
++ - # define gcdDUMP_IN_KERNEL 1
++ - # define gcdDUMP_COMMAND 1
++
++ 2) Go to /hal/kernel/gc_hal_kernel_command.c and disable the following flag
++ -#define gcdSIMPLE_COMMAND_DUMP 0
++
++ 3) Compile the driver
++ 4) insmod it with the logFileSize option
++ 5) Run an application
++ 6) You can get the dump by cat /sys/kernel/debug/gpu/galcore_trace
++
++ */
++
++/**/
++typedef va_list gctDBGARGS ;
++#define gcmkARGS_START(argument, pointer) va_start(argument, pointer)
++#define gcmkARGS_END(argument) va_end(argument)
++
++#define gcmkDBGFSPRINT(ArgumentSize, Message) \
++ { \
++ gctDBGARGS __arguments__; \
++ gcmkARGS_START(__arguments__, Message); \
++ _DebugFSPrint(ArgumentSize, Message, __arguments__);\
++ gcmkARGS_END(__arguments__); \
++ }
++
++/*Debug File System Node Struct*/
++struct _gcsDebugFileSystemNode
++{
++ /*wait queues for read and write operations*/
++#if defined(DECLARE_WAIT_QUEUE_HEAD)
++ wait_queue_head_t read_q , write_q ;
++#else
++ struct wait_queue *read_q , *write_q ;
++#endif
++ struct dentry *parent ; /*parent directory*/
++ struct dentry *filen ; /*filename*/
++ struct semaphore sem ; /* mutual exclusion semaphore */
++ char *data ; /* The circular buffer data */
++ int size ; /* Size of the buffer pointed to by 'data' */
++ int refcount ; /* Files that have this buffer open */
++ int read_point ; /* Offset in circ. buffer of oldest data */
++ int write_point ; /* Offset in circ. buffer of newest data */
++ int offset ; /* Byte number of read_point in the stream */
++ struct _gcsDebugFileSystemNode *next ;
++} ;
++
++/* amount of data in the queue */
++#define gcmkNODE_QLEN(node) ( (node)->write_point >= (node)->read_point ? \
++ (node)->write_point - (node)->read_point : \
++ (node)->size - (node)->read_point + (node)->write_point)
++
++/* byte number of the last byte in the queue */
++#define gcmkNODE_FIRST_EMPTY_BYTE(node) ((node)->offset + gcmkNODE_QLEN(node))
++
++/*Synchronization primitives*/
++#define gcmkNODE_READQ(node) (&((node)->read_q))
++#define gcmkNODE_WRITEQ(node) (&((node)->write_q))
++#define gcmkNODE_SEM(node) (&((node)->sem))
++
++/*Utilities*/
++#define gcmkMIN(x, y) ((x) < (y) ? (x) : y)
++
++/*Debug File System Struct*/
++typedef struct _gcsDebugFileSystem
++{
++ gcsDebugFileSystemNode* linkedlist ;
++ gcsDebugFileSystemNode* currentNode ;
++ int isInited ;
++} gcsDebugFileSystem ;
++
++
++/*debug file system*/
++static gcsDebugFileSystem gc_dbgfs ;
++
++
++
++/*******************************************************************************
++ **
++ ** READ & WRITE FUNCTIONS (START)
++ **
++ *******************************************************************************/
++
++/*******************************************************************************
++ **
++ ** _ReadFromNode
++ **
++ ** 1) reading bytes out of a circular buffer with wraparound.
++ ** 2)returns caddr_t, pointer to data read, which the caller must free.
++ ** 3) length is (a pointer to) the number of bytes to be read, which will be set by this function to
++ ** be the number of bytes actually returned
++ **
++ *******************************************************************************/
++static caddr_t
++_ReadFromNode (
++ gcsDebugFileSystemNode* Node ,
++ size_t *Length ,
++ loff_t *Offset
++ )
++{
++ caddr_t retval ;
++ int bytes_copied = 0 , n , start_point , remaining ;
++
++ /* is the user trying to read data that has already scrolled off? */
++ if ( *Offset < Node->offset )
++ {
++ *Offset = Node->offset ;
++ }
++
++ /* is the user trying to read past EOF? */
++ if ( *Offset >= gcmkNODE_FIRST_EMPTY_BYTE ( Node ) )
++ {
++ return NULL ;
++ }
++
++ /* find the smaller of the total bytes we have available and what
++ * the user is asking for */
++
++ *Length = gcmkMIN ( *Length , gcmkNODE_FIRST_EMPTY_BYTE ( Node ) - *Offset ) ;
++
++ remaining = * Length ;
++
++ /* figure out where to start based on user's Offset */
++ start_point = Node->read_point + ( *Offset - Node->offset ) ;
++
++ start_point = start_point % Node->size ;
++
++ /* allocate memory to return */
++ if ( ( retval = kmalloc ( sizeof (char ) * remaining , GFP_KERNEL ) ) == NULL )
++ return NULL ;
++
++ /* copy the (possibly noncontiguous) data to our buffer */
++ while ( remaining )
++ {
++ n = gcmkMIN ( remaining , Node->size - start_point ) ;
++ memcpy ( retval + bytes_copied , Node->data + start_point , n ) ;
++ bytes_copied += n ;
++ remaining -= n ;
++ start_point = ( start_point + n ) % Node->size ;
++ }
++
++ /* advance user's file pointer */
++ *Offset += * Length ;
++
++ return retval ;
++}
++
++/*******************************************************************************
++ **
++ ** _WriteToNode
++ **
++ ** 1) writes to a circular buffer with wraparound.
++ ** 2)in case of an overflow, it overwrites the oldest unread data.
++ **
++ *********************************************************************************/
++static void
++_WriteToNode (
++ gcsDebugFileSystemNode* Node ,
++ caddr_t Buf ,
++ int Length
++ )
++{
++ int bytes_copied = 0 ;
++ int overflow = 0 ;
++ int n ;
++
++ if ( Length + gcmkNODE_QLEN ( Node ) >= ( Node->size - 1 ) )
++ {
++ overflow = 1 ;
++
++ /* in case of overflow, figure out where the new buffer will
++ * begin. we start by figuring out where the current buffer ENDS:
++ * node->parent->offset + gcmkNODE_QLEN. we then advance the end-offset
++ * by the Length of the current write, and work backwards to
++ * figure out what the oldest unoverwritten data will be (i.e.,
++ * size of the buffer). */
++ Node->offset = Node->offset + gcmkNODE_QLEN ( Node ) + Length
++ - Node->size + 1 ;
++ }
++
++ while ( Length )
++ {
++ /* how many contiguous bytes are available from the write point to
++ * the end of the circular buffer? */
++ n = gcmkMIN ( Length , Node->size - Node->write_point ) ;
++ memcpy ( Node->data + Node->write_point , Buf + bytes_copied , n ) ;
++ bytes_copied += n ;
++ Length -= n ;
++ Node->write_point = ( Node->write_point + n ) % Node->size ;
++ }
++
++ /* if there is an overflow, reset the read point to read whatever is
++ * the oldest data that we have, that has not yet been
++ * overwritten. */
++ if ( overflow )
++ {
++ Node->read_point = ( Node->write_point + 1 ) % Node->size ;
++ }
++}
++
++
++/*******************************************************************************
++ **
++ ** PRINTING UTILITY (START)
++ **
++ *******************************************************************************/
++
++/*******************************************************************************
++ **
++ ** _GetArgumentSize
++ **
++ **
++ *******************************************************************************/
++static gctINT
++_GetArgumentSize (
++ IN gctCONST_STRING Message
++ )
++{
++ gctINT i , count ;
++
++ for ( i = 0 , count = 0 ; Message[i] ; i += 1 )
++ {
++ if ( Message[i] == '%' )
++ {
++ count += 1 ;
++ }
++ }
++ return count * sizeof (unsigned int ) ;
++}
++
++/*******************************************************************************
++ **
++ ** _AppendString
++ **
++ **
++ *******************************************************************************/
++static ssize_t
++_AppendString (
++ IN gcsDebugFileSystemNode* Node ,
++ IN gctCONST_STRING String ,
++ IN int Length
++ )
++{
++ caddr_t message = NULL ;
++ int n ;
++
++ /* if the message is longer than the buffer, just take the beginning
++ * of it, in hopes that the reader (if any) will have time to read
++ * before we wrap around and obliterate it */
++ n = gcmkMIN ( Length , Node->size - 1 ) ;
++
++ /* make sure we have the memory for it */
++ if ( ( message = kmalloc ( n , GFP_KERNEL ) ) == NULL )
++ return - ENOMEM ;
++
++ /* copy into our temp buffer */
++ memcpy ( message , String , n ) ;
++
++ /* now copy it into the circular buffer and free our temp copy */
++ _WriteToNode ( Node , message , n ) ;
++ kfree ( message ) ;
++ return n ;
++}
++
++/*******************************************************************************
++ **
++ ** _DebugFSPrint
++ **
++ **
++ *******************************************************************************/
++static void
++_DebugFSPrint (
++ IN unsigned int ArgumentSize ,
++ IN const char* Message ,
++ IN gctDBGARGS Arguments
++
++ )
++{
++ char buffer[MAX_LINE_SIZE] ;
++ int len ;
++ down ( gcmkNODE_SEM ( gc_dbgfs.currentNode ) ) ;
++ len = vsnprintf ( buffer , sizeof (buffer ) , Message , *( va_list * ) & Arguments ) ;
++ buffer[len] = '\0' ;
++
++ /* Add end-of-line if missing. */
++ if ( buffer[len - 1] != '\n' )
++ {
++ buffer[len ++] = '\n' ;
++ buffer[len] = '\0' ;
++ }
++ _AppendString ( gc_dbgfs.currentNode , buffer , len ) ;
++ up ( gcmkNODE_SEM ( gc_dbgfs.currentNode ) ) ;
++ wake_up_interruptible ( gcmkNODE_READQ ( gc_dbgfs.currentNode ) ) ; /* blocked in read*/
++}
++
++/*******************************************************************************
++ **
++ ** LINUX SYSTEM FUNCTIONS (START)
++ **
++ *******************************************************************************/
++
++/*******************************************************************************
++ **
++ ** find the vivlog structure associated with an inode.
++ ** returns a pointer to the structure if found, NULL if not found
++ **
++ *******************************************************************************/
++static gcsDebugFileSystemNode*
++_GetNodeInfo (
++ IN struct inode *Inode
++ )
++{
++ gcsDebugFileSystemNode* node ;
++
++ if ( Inode == NULL )
++ return NULL ;
++
++ for ( node = gc_dbgfs.linkedlist ; node != NULL ; node = node->next )
++ if ( node->filen->d_inode->i_ino == Inode->i_ino )
++ return node ;
++
++ return NULL ;
++}
++
++/*******************************************************************************
++ **
++ ** _DebugFSRead
++ **
++ *******************************************************************************/
++static ssize_t
++_DebugFSRead (
++ struct file *file ,
++ char __user * buffer ,
++ size_t length ,
++ loff_t * offset
++ )
++{
++ int retval ;
++ caddr_t data_to_return ;
++ gcsDebugFileSystemNode* node ;
++ /* get the metadata about this emlog */
++ if ( ( node = _GetNodeInfo ( file->f_path.dentry->d_inode ) ) == NULL )
++ {
++ printk ( "debugfs_read: record not found\n" ) ;
++ return - EIO ;
++ }
++
++ if ( down_interruptible ( gcmkNODE_SEM ( node ) ) )
++ {
++ return - ERESTARTSYS ;
++ }
++
++ /* wait until there's data available (unless we do nonblocking reads) */
++ while ( *offset >= gcmkNODE_FIRST_EMPTY_BYTE ( node ) )
++ {
++ up ( gcmkNODE_SEM ( node ) ) ;
++ if ( file->f_flags & O_NONBLOCK )
++ {
++ return - EAGAIN ;
++ }
++ if ( wait_event_interruptible ( ( *( gcmkNODE_READQ ( node ) ) ) , ( *offset < gcmkNODE_FIRST_EMPTY_BYTE ( node ) ) ) )
++ {
++ return - ERESTARTSYS ; /* signal: tell the fs layer to handle it */
++ }
++ /* otherwise loop, but first reacquire the lock */
++ if ( down_interruptible ( gcmkNODE_SEM ( node ) ) )
++ {
++ return - ERESTARTSYS ;
++ }
++ }
++ data_to_return = _ReadFromNode ( node , &length , offset ) ;
++ if ( data_to_return == NULL )
++ {
++ retval = 0 ;
++ goto unlock ;
++ }
++ if ( copy_to_user ( buffer , data_to_return , length ) > 0 )
++ {
++ retval = - EFAULT ;
++ }
++ else
++ {
++ retval = length ;
++ }
++ kfree ( data_to_return ) ;
++unlock:
++ up ( gcmkNODE_SEM ( node ) ) ;
++ wake_up_interruptible ( gcmkNODE_WRITEQ ( node ) ) ;
++ return retval ;
++}
++
++/*******************************************************************************
++ **
++ **_DebugFSWrite
++ **
++ *******************************************************************************/
++static ssize_t
++_DebugFSWrite (
++ struct file *file ,
++ const char __user * buffer ,
++ size_t length ,
++ loff_t * offset
++ )
++{
++ caddr_t message = NULL ;
++ int n ;
++ gcsDebugFileSystemNode*node ;
++
++ /* get the metadata about this log */
++ if ( ( node = _GetNodeInfo ( file->f_path.dentry->d_inode ) ) == NULL )
++ {
++ return - EIO ;
++ }
++
++ if ( down_interruptible ( gcmkNODE_SEM ( node ) ) )
++ {
++ return - ERESTARTSYS ;
++ }
++
++ /* if the message is longer than the buffer, just take the beginning
++ * of it, in hopes that the reader (if any) will have time to read
++ * before we wrap around and obliterate it */
++ n = gcmkMIN ( length , node->size - 1 ) ;
++
++ /* make sure we have the memory for it */
++ if ( ( message = kmalloc ( n , GFP_KERNEL ) ) == NULL )
++ {
++ up ( gcmkNODE_SEM ( node ) ) ;
++ return - ENOMEM ;
++ }
++
++ /* copy into our temp buffer */
++ if ( copy_from_user ( message , buffer , n ) > 0 )
++ {
++ up ( gcmkNODE_SEM ( node ) ) ;
++ kfree ( message ) ;
++ return - EFAULT ;
++ }
++
++ /* now copy it into the circular buffer and free our temp copy */
++ _WriteToNode ( node , message , n ) ;
++
++ kfree ( message ) ;
++ up ( gcmkNODE_SEM ( node ) ) ;
++
++ /* wake up any readers that might be waiting for the data. we call
++ * schedule in the vague hope that a reader will run before the
++ * writer's next write, to avoid losing data. */
++ wake_up_interruptible ( gcmkNODE_READQ ( node ) ) ;
++
++ return n ;
++}
++
++/*******************************************************************************
++ **
++ ** File Operations Table
++ **
++ *******************************************************************************/
++static const struct file_operations debugfs_operations = {
++ .owner = THIS_MODULE ,
++ .read = _DebugFSRead ,
++ .write = _DebugFSWrite ,
++} ;
++
++/*******************************************************************************
++ **
++ ** INTERFACE FUNCTIONS (START)
++ **
++ *******************************************************************************/
++
++/*******************************************************************************
++ **
++ ** gckDebugFileSystemIsEnabled
++ **
++ **
++ ** INPUT:
++ **
++ ** OUTPUT:
++ **
++ *******************************************************************************/
++
++
++gctINT
++gckDebugFileSystemIsEnabled ( void )
++{
++ return gc_dbgfs.isInited ;
++}
++/*******************************************************************************
++ **
++ ** gckDebugFileSystemInitialize
++ **
++ **
++ ** INPUT:
++ **
++ ** OUTPUT:
++ **
++ *******************************************************************************/
++
++gctINT
++gckDebugFileSystemInitialize ( void )
++{
++ if ( ! gc_dbgfs.isInited )
++ {
++ gc_dbgfs.linkedlist = gcvNULL ;
++ gc_dbgfs.currentNode = gcvNULL ;
++ gc_dbgfs.isInited = 1 ;
++ }
++ return gc_dbgfs.isInited ;
++}
++/*******************************************************************************
++ **
++ ** gckDebugFileSystemTerminate
++ **
++ **
++ ** INPUT:
++ **
++ ** OUTPUT:
++ **
++ *******************************************************************************/
++
++gctINT
++gckDebugFileSystemTerminate ( void )
++{
++ gcsDebugFileSystemNode * next = gcvNULL ;
++ gcsDebugFileSystemNode * temp = gcvNULL ;
++ if ( gc_dbgfs.isInited )
++ {
++ temp = gc_dbgfs.linkedlist ;
++ while ( temp != gcvNULL )
++ {
++ next = temp->next ;
++ gckDebugFileSystemFreeNode ( temp ) ;
++ kfree ( temp ) ;
++ temp = next ;
++ }
++ gc_dbgfs.isInited = 0 ;
++ }
++ return 0 ;
++}
++
++
++/*******************************************************************************
++ **
++ ** gckDebugFileSystemCreateNode
++ **
++ **
++ ** INPUT:
++ **
++ ** OUTPUT:
++ **
++ ** gckDebugFileSystemFreeNode * Device
++ ** Pointer to a variable receiving the gcsDebugFileSystemNode object pointer on
++ ** success.
++ *********************************************************************************/
++
++gctINT
++gckDebugFileSystemCreateNode (
++ IN gctINT SizeInKB ,
++ IN gctCONST_STRING ParentName ,
++ IN gctCONST_STRING NodeName ,
++ OUT gcsDebugFileSystemNode **Node
++ )
++{
++ gcsDebugFileSystemNode*node ;
++ /* allocate space for our metadata and initialize it */
++ if ( ( node = kmalloc ( sizeof (gcsDebugFileSystemNode ) , GFP_KERNEL ) ) == NULL )
++ goto struct_malloc_failed ;
++
++ /*Zero it out*/
++ memset ( node , 0 , sizeof (gcsDebugFileSystemNode ) ) ;
++
++ /*Init the sync primitives*/
++#if defined(DECLARE_WAIT_QUEUE_HEAD)
++ init_waitqueue_head ( gcmkNODE_READQ ( node ) ) ;
++#else
++ init_waitqueue ( gcmkNODE_READQ ( node ) ) ;
++#endif
++
++#if defined(DECLARE_WAIT_QUEUE_HEAD)
++ init_waitqueue_head ( gcmkNODE_WRITEQ ( node ) ) ;
++#else
++ init_waitqueue ( gcmkNODE_WRITEQ ( node ) ) ;
++#endif
++ sema_init ( gcmkNODE_SEM ( node ) , 1 ) ;
++ /*End the sync primitives*/
++
++
++ /* figure out how much of a buffer this should be and allocate the buffer */
++ node->size = 1024 * SizeInKB ;
++ if ( ( node->data = ( char * ) vmalloc ( sizeof (char ) * node->size ) ) == NULL )
++ goto data_malloc_failed ;
++
++ /*creating the debug file system*/
++ node->parent = debugfs_create_dir ( ParentName , NULL ) ;
++
++ /*creating the file*/
++ node->filen = debugfs_create_file ( NodeName , S_IRUGO | S_IWUSR , node->parent , NULL ,
++ &debugfs_operations ) ;
++
++ /* add it to our linked list */
++ node->next = gc_dbgfs.linkedlist ;
++ gc_dbgfs.linkedlist = node ;
++
++ /* pass the struct back */
++ *Node = node ;
++ return 0 ;
++
++ vfree ( node->data ) ;
++data_malloc_failed:
++ kfree ( node ) ;
++struct_malloc_failed:
++ return - ENOMEM ;
++}
++
++/*******************************************************************************
++ **
++ ** gckDebugFileSystemFreeNode
++ **
++ **
++ ** INPUT:
++ **
++ ** OUTPUT:
++ **
++ *******************************************************************************/
++void
++gckDebugFileSystemFreeNode (
++ IN gcsDebugFileSystemNode * Node
++ )
++{
++
++ gcsDebugFileSystemNode **ptr ;
++
++ if ( Node == NULL )
++ {
++ printk ( "null passed to free_vinfo\n" ) ;
++ return ;
++ }
++
++ down ( gcmkNODE_SEM ( Node ) ) ;
++ /*free data*/
++ vfree ( Node->data ) ;
++
++ /*Close Debug fs*/
++ if ( Node->filen )
++ {
++ debugfs_remove ( Node->filen ) ;
++ }
++ if ( Node->parent )
++ {
++ debugfs_remove ( Node->parent ) ;
++ }
++
++ /* now delete the node from the linked list */
++ ptr = & ( gc_dbgfs.linkedlist ) ;
++ while ( *ptr != Node )
++ {
++ if ( ! *ptr )
++ {
++ printk ( "corrupt info list!\n" ) ;
++ break ;
++ }
++ else
++ ptr = & ( ( **ptr ).next ) ;
++ }
++ *ptr = Node->next ;
++ up ( gcmkNODE_SEM ( Node ) ) ;
++}
++
++/*******************************************************************************
++ **
++ ** gckDebugFileSystemSetCurrentNode
++ **
++ **
++ ** INPUT:
++ **
++ ** OUTPUT:
++ **
++ *******************************************************************************/
++void
++gckDebugFileSystemSetCurrentNode (
++ IN gcsDebugFileSystemNode * Node
++ )
++{
++ gc_dbgfs.currentNode = Node ;
++}
++
++/*******************************************************************************
++ **
++ ** gckDebugFileSystemGetCurrentNode
++ **
++ **
++ ** INPUT:
++ **
++ ** OUTPUT:
++ **
++ *******************************************************************************/
++void
++gckDebugFileSystemGetCurrentNode (
++ OUT gcsDebugFileSystemNode ** Node
++ )
++{
++ *Node = gc_dbgfs.currentNode ;
++}
++
++/*******************************************************************************
++ **
++ ** gckDebugFileSystemPrint
++ **
++ **
++ ** INPUT:
++ **
++ ** OUTPUT:
++ **
++ *******************************************************************************/
++void
++gckDebugFileSystemPrint (
++ IN gctCONST_STRING Message ,
++ ...
++ )
++{
++ gcmkDBGFSPRINT ( _GetArgumentSize ( Message ) , Message ) ;
++}
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_debugfs.h linux-xbian-imx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_debugfs.h
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_debugfs.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_debugfs.h 2015-07-27 23:13:06.222780123 +0200
+@@ -0,0 +1,84 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include <stdarg.h>
++
++#ifndef __gc_hal_kernel_debugfs_h_
++#define __gc_hal_kernel_debugfs_h_
++
++ #define MAX_LINE_SIZE 768 /* Max bytes for a line of debug info */
++
++
++ typedef struct _gcsDebugFileSystemNode gcsDebugFileSystemNode ;
++
++
++/*******************************************************************************
++ **
++ ** System Related
++ **
++ *******************************************************************************/
++
++gctINT gckDebugFileSystemIsEnabled(void);
++
++gctINT gckDebugFileSystemInitialize(void);
++
++gctINT gckDebugFileSystemTerminate(void);
++
++
++/*******************************************************************************
++ **
++ ** Node Related
++ **
++ *******************************************************************************/
++
++gctINT gckDebugFileSystemCreateNode(
++ IN gctINT SizeInKB,
++ IN gctCONST_STRING ParentName ,
++ IN gctCONST_STRING NodeName,
++ OUT gcsDebugFileSystemNode **Node
++ );
++
++
++void gckDebugFileSystemFreeNode(
++ IN gcsDebugFileSystemNode * Node
++ );
++
++
++
++void gckDebugFileSystemSetCurrentNode(
++ IN gcsDebugFileSystemNode * Node
++ );
++
++
++
++void gckDebugFileSystemGetCurrentNode(
++ OUT gcsDebugFileSystemNode ** Node
++ );
++
++
++void gckDebugFileSystemPrint(
++ IN gctCONST_STRING Message,
++ ...
++ );
++
++#endif
++
++
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_debug.h linux-xbian-imx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_debug.h
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_debug.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_debug.h 2015-07-27 23:13:06.222780123 +0200
+@@ -0,0 +1,102 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_kernel_debug_h_
++#define __gc_hal_kernel_debug_h_
++
++#include <gc_hal_kernel_linux.h>
++#include <linux/spinlock.h>
++#include <linux/time.h>
++#include <stdarg.h>
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/******************************************************************************\
++****************************** OS-dependent Macros *****************************
++\******************************************************************************/
++
++typedef va_list gctARGUMENTS;
++
++#define gcmkARGUMENTS_START(Arguments, Pointer) \
++ va_start(Arguments, Pointer)
++
++#define gcmkARGUMENTS_END(Arguments) \
++ va_end(Arguments)
++
++#define gcmkDECLARE_LOCK(__spinLock__) \
++ static DEFINE_SPINLOCK(__spinLock__);
++
++#define gcmkLOCKSECTION(__spinLock__) \
++ spin_lock(&__spinLock__)
++
++#define gcmkUNLOCKSECTION(__spinLock__) \
++ spin_unlock(&__spinLock__)
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)
++# define gcmkGETPROCESSID() \
++ task_tgid_vnr(current)
++#else
++# define gcmkGETPROCESSID() \
++ current->tgid
++#endif
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)
++# define gcmkGETTHREADID() \
++ task_pid_vnr(current)
++#else
++# define gcmkGETTHREADID() \
++ current->pid
++#endif
++
++#define gcmkOUTPUT_STRING(String) \
++ if(gckDebugFileSystemIsEnabled()) \
++ gckDebugFileSystemPrint(String);\
++ else\
++ printk(String); \
++ touch_softlockup_watchdog()
++
++
++#define gcmkSPRINTF(Destination, Size, Message, Value) \
++ snprintf(Destination, Size, Message, Value)
++
++#define gcmkSPRINTF2(Destination, Size, Message, Value1, Value2) \
++ snprintf(Destination, Size, Message, Value1, Value2)
++
++#define gcmkSPRINTF3(Destination, Size, Message, Value1, Value2, Value3) \
++ snprintf(Destination, Size, Message, Value1, Value2, Value3)
++
++#define gcmkVSPRINTF(Destination, Size, Message, Arguments) \
++ vsnprintf(Destination, Size, Message, *(va_list *) &Arguments)
++
++#define gcmkSTRCAT(Destination, Size, String) \
++ strncat(Destination, String, Size)
++
++/* If not zero, forces data alignment in the variable argument list
++ by its individual size. */
++#define gcdALIGNBYSIZE 1
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __gc_hal_kernel_debug_h_ */
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_device.c linux-xbian-imx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_device.c
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_device.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_device.c 2015-07-27 23:13:06.222780123 +0200
+@@ -0,0 +1,1676 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_linux.h"
++#include <linux/pagemap.h>
++#include <linux/seq_file.h>
++#include <linux/mm.h>
++#include <linux/mman.h>
++#include <linux/slab.h>
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,10,0)
++#include <mach/hardware.h>
++#endif
++#include <linux/pm_runtime.h>
++
++#define _GC_OBJ_ZONE gcvZONE_DEVICE
++
++#define DEBUG_FILE "galcore_trace"
++#define PARENT_FILE "gpu"
++
++
++#ifdef FLAREON
++ static struct dove_gpio_irq_handler gc500_handle;
++#endif
++
++#define gcmIS_CORE_PRESENT(Device, Core) (Device->irqLines[Core] > 0)
++
++/******************************************************************************\
++*************************** Memory Allocation Wrappers *************************
++\******************************************************************************/
++
++static gceSTATUS
++_AllocateMemory(
++ IN gckGALDEVICE Device,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER *Logical,
++ OUT gctPHYS_ADDR *Physical,
++ OUT gctUINT32 *PhysAddr
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Device=0x%x Bytes=%lu", Device, Bytes);
++
++ gcmkVERIFY_ARGUMENT(Device != NULL);
++ gcmkVERIFY_ARGUMENT(Logical != NULL);
++ gcmkVERIFY_ARGUMENT(Physical != NULL);
++ gcmkVERIFY_ARGUMENT(PhysAddr != NULL);
++
++ gcmkONERROR(gckOS_AllocateContiguous(
++ Device->os, gcvFALSE, &Bytes, Physical, Logical
++ ));
++
++ *PhysAddr = ((PLINUX_MDL)*Physical)->dmaHandle - Device->baseAddress;
++
++ /* Success. */
++ gcmkFOOTER_ARG(
++ "*Logical=0x%x *Physical=0x%x *PhysAddr=0x%08x",
++ *Logical, *Physical, *PhysAddr
++ );
++
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++static gceSTATUS
++_FreeMemory(
++ IN gckGALDEVICE Device,
++ IN gctPOINTER Logical,
++ IN gctPHYS_ADDR Physical)
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Device=0x%x Logical=0x%x Physical=0x%x",
++ Device, Logical, Physical);
++
++ gcmkVERIFY_ARGUMENT(Device != NULL);
++
++ status = gckOS_FreeContiguous(
++ Device->os, Physical, Logical,
++ ((PLINUX_MDL) Physical)->numPages * PAGE_SIZE
++ );
++
++ gcmkFOOTER();
++ return status;
++}
++
++
++
++/******************************************************************************\
++******************************* Interrupt Handler ******************************
++\******************************************************************************/
++static irqreturn_t isrRoutine(int irq, void *ctxt)
++{
++ gceSTATUS status;
++ gckGALDEVICE device;
++
++ device = (gckGALDEVICE) ctxt;
++
++ /* Call kernel interrupt notification. */
++ status = gckKERNEL_Notify(device->kernels[gcvCORE_MAJOR], gcvNOTIFY_INTERRUPT, gcvTRUE);
++
++ if (gcmIS_SUCCESS(status))
++ {
++ device->dataReadys[gcvCORE_MAJOR] = gcvTRUE;
++
++ up(&device->semas[gcvCORE_MAJOR]);
++
++ return IRQ_HANDLED;
++ }
++
++ return IRQ_NONE;
++}
++
++static int threadRoutine(void *ctxt)
++{
++ gckGALDEVICE device = (gckGALDEVICE) ctxt;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_DRIVER,
++ "Starting isr Thread with extension=%p",
++ device);
++
++ for (;;)
++ {
++ static int down;
++
++ down = down_interruptible(&device->semas[gcvCORE_MAJOR]);
++ if (down); /*To make gcc 4.6 happye*/
++ device->dataReadys[gcvCORE_MAJOR] = gcvFALSE;
++
++ if (device->killThread == gcvTRUE)
++ {
++ /* The daemon exits. */
++ while (!kthread_should_stop())
++ {
++ gckOS_Delay(device->os, 1);
++ }
++
++ return 0;
++ }
++
++ gckKERNEL_Notify(device->kernels[gcvCORE_MAJOR], gcvNOTIFY_INTERRUPT, gcvFALSE);
++ }
++}
++
++static irqreturn_t isrRoutine2D(int irq, void *ctxt)
++{
++ gceSTATUS status;
++ gckGALDEVICE device;
++
++ device = (gckGALDEVICE) ctxt;
++
++ /* Call kernel interrupt notification. */
++ status = gckKERNEL_Notify(device->kernels[gcvCORE_2D], gcvNOTIFY_INTERRUPT, gcvTRUE);
++
++ if (gcmIS_SUCCESS(status))
++ {
++ device->dataReadys[gcvCORE_2D] = gcvTRUE;
++
++ up(&device->semas[gcvCORE_2D]);
++
++ return IRQ_HANDLED;
++ }
++
++ return IRQ_NONE;
++}
++
++static int threadRoutine2D(void *ctxt)
++{
++ gckGALDEVICE device = (gckGALDEVICE) ctxt;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_DRIVER,
++ "Starting isr Thread with extension=%p",
++ device);
++
++ for (;;)
++ {
++ static int down;
++
++ down = down_interruptible(&device->semas[gcvCORE_2D]);
++ if (down); /*To make gcc 4.6 happye*/
++ device->dataReadys[gcvCORE_2D] = gcvFALSE;
++
++ if (device->killThread == gcvTRUE)
++ {
++ /* The daemon exits. */
++ while (!kthread_should_stop())
++ {
++ gckOS_Delay(device->os, 1);
++ }
++
++ return 0;
++ }
++
++ gckKERNEL_Notify(device->kernels[gcvCORE_2D], gcvNOTIFY_INTERRUPT, gcvFALSE);
++ }
++}
++
++static irqreturn_t isrRoutineVG(int irq, void *ctxt)
++{
++#if gcdENABLE_VG
++ gceSTATUS status;
++ gckGALDEVICE device;
++
++ device = (gckGALDEVICE) ctxt;
++
++ /* Serve the interrupt. */
++ status = gckVGINTERRUPT_Enque(device->kernels[gcvCORE_VG]->vg->interrupt);
++
++ /* Determine the return value. */
++ return (status == gcvSTATUS_NOT_OUR_INTERRUPT)
++ ? IRQ_RETVAL(0)
++ : IRQ_RETVAL(1);
++#else
++ return IRQ_NONE;
++#endif
++}
++
++static int threadRoutineVG(void *ctxt)
++{
++ gckGALDEVICE device = (gckGALDEVICE) ctxt;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_DRIVER,
++ "Starting isr Thread with extension=%p",
++ device);
++
++ for (;;)
++ {
++ static int down;
++
++ down = down_interruptible(&device->semas[gcvCORE_VG]);
++ if (down); /*To make gcc 4.6 happye*/
++ device->dataReadys[gcvCORE_VG] = gcvFALSE;
++
++ if (device->killThread == gcvTRUE)
++ {
++ /* The daemon exits. */
++ while (!kthread_should_stop())
++ {
++ gckOS_Delay(device->os, 1);
++ }
++
++ return 0;
++ }
++
++ gckKERNEL_Notify(device->kernels[gcvCORE_VG], gcvNOTIFY_INTERRUPT, gcvFALSE);
++ }
++}
++
++/******************************************************************************\
++******************************* gckGALDEVICE Code ******************************
++\******************************************************************************/
++
++/*******************************************************************************
++**
++** gckGALDEVICE_Construct
++**
++** Constructor.
++**
++** INPUT:
++**
++** OUTPUT:
++**
++** gckGALDEVICE * Device
++** Pointer to a variable receiving the gckGALDEVICE object pointer on
++** success.
++*/
++gceSTATUS
++gckGALDEVICE_Construct(
++ IN gctINT IrqLine,
++ IN gctUINT32 RegisterMemBase,
++ IN gctSIZE_T RegisterMemSize,
++ IN gctINT IrqLine2D,
++ IN gctUINT32 RegisterMemBase2D,
++ IN gctSIZE_T RegisterMemSize2D,
++ IN gctINT IrqLineVG,
++ IN gctUINT32 RegisterMemBaseVG,
++ IN gctSIZE_T RegisterMemSizeVG,
++ IN gctUINT32 ContiguousBase,
++ IN gctSIZE_T ContiguousSize,
++ IN gctSIZE_T BankSize,
++ IN gctINT FastClear,
++ IN gctINT Compression,
++ IN gctUINT32 PhysBaseAddr,
++ IN gctUINT32 PhysSize,
++ IN gctINT Signal,
++ IN gctUINT LogFileSize,
++ IN struct device *pdev,
++ IN gctINT PowerManagement,
++ IN gctINT GpuProfiler,
++ OUT gckGALDEVICE *Device
++ )
++{
++ gctUINT32 internalBaseAddress = 0, internalAlignment = 0;
++ gctUINT32 externalBaseAddress = 0, externalAlignment = 0;
++ gctUINT32 horizontalTileSize, verticalTileSize;
++ struct resource* mem_region;
++ gctUINT32 physAddr;
++ gctUINT32 physical;
++ gckGALDEVICE device;
++ gceSTATUS status;
++ gctINT32 i;
++ gceHARDWARE_TYPE type;
++ gckDB sharedDB = gcvNULL;
++ gckKERNEL kernel = gcvNULL;
++
++ gcmkHEADER_ARG("IrqLine=%d RegisterMemBase=0x%08x RegisterMemSize=%u "
++ "IrqLine2D=%d RegisterMemBase2D=0x%08x RegisterMemSize2D=%u "
++ "IrqLineVG=%d RegisterMemBaseVG=0x%08x RegisterMemSizeVG=%u "
++ "ContiguousBase=0x%08x ContiguousSize=%lu BankSize=%lu "
++ "FastClear=%d Compression=%d PhysBaseAddr=0x%x PhysSize=%d Signal=%d",
++ IrqLine, RegisterMemBase, RegisterMemSize,
++ IrqLine2D, RegisterMemBase2D, RegisterMemSize2D,
++ IrqLineVG, RegisterMemBaseVG, RegisterMemSizeVG,
++ ContiguousBase, ContiguousSize, BankSize, FastClear, Compression,
++ PhysBaseAddr, PhysSize, Signal);
++
++ /* Allocate device structure. */
++ device = kmalloc(sizeof(struct _gckGALDEVICE), GFP_KERNEL);
++
++ if (!device)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ memset(device, 0, sizeof(struct _gckGALDEVICE));
++
++ device->dbgnode = gcvNULL;
++ if(LogFileSize != 0)
++ {
++ if(gckDebugFileSystemCreateNode(LogFileSize,PARENT_FILE,DEBUG_FILE,&(device->dbgnode)) != 0)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Failed to create the debug file system %s/%s \n",
++ __FUNCTION__, __LINE__,
++ PARENT_FILE, DEBUG_FILE
++ );
++ }
++ else
++ {
++ /*Everything is OK*/
++ gckDebugFileSystemSetCurrentNode(device->dbgnode);
++ }
++ }
++#ifdef CONFIG_PM
++ /*Init runtime pm for gpu*/
++ pm_runtime_enable(pdev);
++ device->pmdev = pdev;
++#endif
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,5,0)
++ /*get gpu regulator*/
++ device->gpu_regulator = regulator_get(pdev, "cpu_vddgpu");
++#elif LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
++ device->gpu_regulator = devm_regulator_get(pdev, "pu");
++#endif
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,5,0) || LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
++ if (IS_ERR(device->gpu_regulator)) {
++ gcmkTRACE_ZONE(gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Failed to get gpu regulator %s/%s \n",
++ __FUNCTION__, __LINE__,
++ PARENT_FILE, DEBUG_FILE);
++ gcmkONERROR(gcvSTATUS_NOT_FOUND);
++ }
++#endif
++ /*Initialize the clock structure*/
++ if (IrqLine != -1) {
++ device->clk_3d_core = clk_get(pdev, "gpu3d_clk");
++ if (!IS_ERR(device->clk_3d_core)) {
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,5,0)
++ if (cpu_is_mx6q()) {
++ device->clk_3d_shader = clk_get(pdev, "gpu3d_shader_clk");
++ if (IS_ERR(device->clk_3d_shader)) {
++ IrqLine = -1;
++ clk_put(device->clk_3d_core);
++ device->clk_3d_core = NULL;
++ device->clk_3d_shader = NULL;
++ gckOS_Print("galcore: clk_get gpu3d_shader_clk failed, disable 3d!\n");
++ }
++ }
++#else
++ device->clk_3d_axi = clk_get(pdev, "gpu3d_axi_clk");
++ device->clk_3d_shader = clk_get(pdev, "gpu3d_shader_clk");
++ if (IS_ERR(device->clk_3d_shader)) {
++ IrqLine = -1;
++ clk_put(device->clk_3d_core);
++ device->clk_3d_core = NULL;
++ device->clk_3d_shader = NULL;
++ gckOS_Print("galcore: clk_get gpu3d_shader_clk failed, disable 3d!\n");
++ }
++#endif
++ } else {
++ IrqLine = -1;
++ device->clk_3d_core = NULL;
++ gckOS_Print("galcore: clk_get gpu3d_clk failed, disable 3d!\n");
++ }
++ }
++ if ((IrqLine2D != -1) || (IrqLineVG != -1)) {
++ device->clk_2d_core = clk_get(pdev, "gpu2d_clk");
++ if (IS_ERR(device->clk_2d_core)) {
++ IrqLine2D = -1;
++ IrqLineVG = -1;
++ device->clk_2d_core = NULL;
++ gckOS_Print("galcore: clk_get 2d core clock failed, disable 2d/vg!\n");
++ } else {
++ if (IrqLine2D != -1) {
++ device->clk_2d_axi = clk_get(pdev, "gpu2d_axi_clk");
++ if (IS_ERR(device->clk_2d_axi)) {
++ device->clk_2d_axi = NULL;
++ IrqLine2D = -1;
++ gckOS_Print("galcore: clk_get 2d axi clock failed, disable 2d\n");
++ }
++ }
++ if (IrqLineVG != -1) {
++ device->clk_vg_axi = clk_get(pdev, "openvg_axi_clk");
++ if (IS_ERR(device->clk_vg_axi)) {
++ IrqLineVG = -1;
++ device->clk_vg_axi = NULL;
++ gckOS_Print("galcore: clk_get vg clock failed, disable vg!\n");
++ }
++ }
++ }
++ }
++
++ if (IrqLine != -1)
++ {
++ device->requestedRegisterMemBases[gcvCORE_MAJOR] = RegisterMemBase;
++ device->requestedRegisterMemSizes[gcvCORE_MAJOR] = RegisterMemSize;
++ }
++
++ if (IrqLine2D != -1)
++ {
++ device->requestedRegisterMemBases[gcvCORE_2D] = RegisterMemBase2D;
++ device->requestedRegisterMemSizes[gcvCORE_2D] = RegisterMemSize2D;
++ }
++
++ if (IrqLineVG != -1)
++ {
++ device->requestedRegisterMemBases[gcvCORE_VG] = RegisterMemBaseVG;
++ device->requestedRegisterMemSizes[gcvCORE_VG] = RegisterMemSizeVG;
++ }
++
++ device->requestedContiguousBase = 0;
++ device->requestedContiguousSize = 0;
++
++
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ physical = device->requestedRegisterMemBases[i];
++
++ /* Set up register memory region. */
++ if (physical != 0)
++ {
++ mem_region = request_mem_region(
++ physical, device->requestedRegisterMemSizes[i], "galcore register region"
++ );
++
++ if (mem_region == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Failed to claim %lu bytes @ 0x%08X\n",
++ __FUNCTION__, __LINE__,
++ physical, device->requestedRegisterMemSizes[i]
++ );
++
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++ device->registerBases[i] = (gctPOINTER) ioremap_nocache(
++ physical, device->requestedRegisterMemSizes[i]);
++
++ if (device->registerBases[i] == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Unable to map %ld bytes @ 0x%08X\n",
++ __FUNCTION__, __LINE__,
++ physical, device->requestedRegisterMemSizes[i]
++ );
++
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++ physical += device->requestedRegisterMemSizes[i];
++ }
++ else
++ {
++ device->registerBases[i] = gcvNULL;
++ }
++ }
++
++ /* Set the base address */
++ device->baseAddress = PhysBaseAddr;
++
++ /* Construct the gckOS object. */
++ gcmkONERROR(gckOS_Construct(device, &device->os));
++
++ if (IrqLine != -1)
++ {
++ /* Construct the gckKERNEL object. */
++ gcmkONERROR(gckKERNEL_Construct(
++ device->os, gcvCORE_MAJOR, device,
++ gcvNULL, &device->kernels[gcvCORE_MAJOR]));
++
++ sharedDB = device->kernels[gcvCORE_MAJOR]->db;
++
++ /* Initialize core mapping */
++ for (i = 0; i < 8; i++)
++ {
++ device->coreMapping[i] = gcvCORE_MAJOR;
++ }
++
++ /* Setup the ISR manager. */
++ gcmkONERROR(gckHARDWARE_SetIsrManager(
++ device->kernels[gcvCORE_MAJOR]->hardware,
++ (gctISRMANAGERFUNC) gckGALDEVICE_Enable_ISR,
++ (gctISRMANAGERFUNC) gckGALDEVICE_Disable_ISR,
++ device
++ ));
++
++ gcmkONERROR(gckHARDWARE_SetFastClear(
++ device->kernels[gcvCORE_MAJOR]->hardware, FastClear, Compression
++ ));
++
++ gcmkONERROR(gckHARDWARE_SetPowerManagement(
++ device->kernels[gcvCORE_MAJOR]->hardware, PowerManagement
++ ));
++
++ gcmkONERROR(gckHARDWARE_SetGpuProfiler(
++ device->kernels[gcvCORE_MAJOR]->hardware, GpuProfiler
++ ));
++
++#if COMMAND_PROCESSOR_VERSION == 1
++ /* Start the command queue. */
++ gcmkONERROR(gckCOMMAND_Start(device->kernels[gcvCORE_MAJOR]->command));
++#endif
++ }
++ else
++ {
++ device->kernels[gcvCORE_MAJOR] = gcvNULL;
++ }
++
++ if (IrqLine2D != -1)
++ {
++ gcmkONERROR(gckKERNEL_Construct(
++ device->os, gcvCORE_2D, device,
++ sharedDB, &device->kernels[gcvCORE_2D]));
++
++ if (sharedDB == gcvNULL) sharedDB = device->kernels[gcvCORE_2D]->db;
++
++ /* Verify the hardware type */
++ gcmkONERROR(gckHARDWARE_GetType(device->kernels[gcvCORE_2D]->hardware, &type));
++
++ if (type != gcvHARDWARE_2D)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Unexpected hardware type: %d\n",
++ __FUNCTION__, __LINE__,
++ type
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ /* Initialize core mapping */
++ if (device->kernels[gcvCORE_MAJOR] == gcvNULL)
++ {
++ for (i = 0; i < 8; i++)
++ {
++ device->coreMapping[i] = gcvCORE_2D;
++ }
++ }
++ else
++ {
++ device->coreMapping[gcvHARDWARE_2D] = gcvCORE_2D;
++ }
++
++ /* Setup the ISR manager. */
++ gcmkONERROR(gckHARDWARE_SetIsrManager(
++ device->kernels[gcvCORE_2D]->hardware,
++ (gctISRMANAGERFUNC) gckGALDEVICE_Enable_ISR,
++ (gctISRMANAGERFUNC) gckGALDEVICE_Disable_ISR,
++ device
++ ));
++
++ gcmkONERROR(gckHARDWARE_SetPowerManagement(
++ device->kernels[gcvCORE_2D]->hardware, PowerManagement
++ ));
++
++
++#if COMMAND_PROCESSOR_VERSION == 1
++ /* Start the command queue. */
++ gcmkONERROR(gckCOMMAND_Start(device->kernels[gcvCORE_2D]->command));
++#endif
++ }
++ else
++ {
++ device->kernels[gcvCORE_2D] = gcvNULL;
++ }
++
++ if (IrqLineVG != -1)
++ {
++#if gcdENABLE_VG
++ gcmkONERROR(gckKERNEL_Construct(
++ device->os, gcvCORE_VG, device,
++ sharedDB, &device->kernels[gcvCORE_VG]));
++ /* Initialize core mapping */
++ if (device->kernels[gcvCORE_MAJOR] == gcvNULL
++ && device->kernels[gcvCORE_2D] == gcvNULL
++ )
++ {
++ for (i = 0; i < 8; i++)
++ {
++ device->coreMapping[i] = gcvCORE_VG;
++ }
++ }
++ else
++ {
++ device->coreMapping[gcvHARDWARE_VG] = gcvCORE_VG;
++ }
++
++
++ gcmkONERROR(gckVGHARDWARE_SetPowerManagement(
++ device->kernels[gcvCORE_VG]->vg->hardware,
++ PowerManagement
++ ));
++
++#endif
++ }
++ else
++ {
++ device->kernels[gcvCORE_VG] = gcvNULL;
++ }
++
++ /* Initialize the ISR. */
++ device->irqLines[gcvCORE_MAJOR] = IrqLine;
++ device->irqLines[gcvCORE_2D] = IrqLine2D;
++ device->irqLines[gcvCORE_VG] = IrqLineVG;
++
++ /* Initialize the kernel thread semaphores. */
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ if (device->irqLines[i] != -1) sema_init(&device->semas[i], 0);
++ }
++
++ device->signal = Signal;
++
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ if (device->kernels[i] != gcvNULL) break;
++ }
++
++ if (i == gcdMAX_GPU_COUNT)
++ {
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++#if gcdENABLE_VG
++ if (i == gcvCORE_VG)
++ {
++ /* Query the ceiling of the system memory. */
++ gcmkONERROR(gckVGHARDWARE_QuerySystemMemory(
++ device->kernels[i]->vg->hardware,
++ &device->systemMemorySize,
++ &device->systemMemoryBaseAddress
++ ));
++ /* query the amount of video memory */
++ gcmkONERROR(gckVGHARDWARE_QueryMemory(
++ device->kernels[i]->vg->hardware,
++ &device->internalSize, &internalBaseAddress, &internalAlignment,
++ &device->externalSize, &externalBaseAddress, &externalAlignment,
++ &horizontalTileSize, &verticalTileSize
++ ));
++ }
++ else
++#endif
++ {
++ /* Query the ceiling of the system memory. */
++ gcmkONERROR(gckHARDWARE_QuerySystemMemory(
++ device->kernels[i]->hardware,
++ &device->systemMemorySize,
++ &device->systemMemoryBaseAddress
++ ));
++
++ /* query the amount of video memory */
++ gcmkONERROR(gckHARDWARE_QueryMemory(
++ device->kernels[i]->hardware,
++ &device->internalSize, &internalBaseAddress, &internalAlignment,
++ &device->externalSize, &externalBaseAddress, &externalAlignment,
++ &horizontalTileSize, &verticalTileSize
++ ));
++ }
++
++
++ /* Grab the first availiable kernel */
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ if (device->irqLines[i] != -1)
++ {
++ kernel = device->kernels[i];
++ break;
++ }
++ }
++
++ /* Set up the internal memory region. */
++ if (device->internalSize > 0)
++ {
++ status = gckVIDMEM_Construct(
++ device->os,
++ internalBaseAddress, device->internalSize, internalAlignment,
++ 0, &device->internalVidMem
++ );
++
++ if (gcmIS_ERROR(status))
++ {
++ /* Error, disable internal heap. */
++ device->internalSize = 0;
++ }
++ else
++ {
++ /* Map internal memory. */
++ device->internalLogical
++ = (gctPOINTER) ioremap_nocache(physical, device->internalSize);
++
++ if (device->internalLogical == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++ device->internalPhysical = (gctPHYS_ADDR)(gctUINTPTR_T) physical;
++ device->internalPhysicalName = gcmPTR_TO_NAME(device->internalPhysical);
++ physical += device->internalSize;
++ }
++ }
++
++ if (device->externalSize > 0)
++ {
++ /* create the external memory heap */
++ status = gckVIDMEM_Construct(
++ device->os,
++ externalBaseAddress, device->externalSize, externalAlignment,
++ 0, &device->externalVidMem
++ );
++
++ if (gcmIS_ERROR(status))
++ {
++ /* Error, disable internal heap. */
++ device->externalSize = 0;
++ }
++ else
++ {
++ /* Map external memory. */
++ device->externalLogical
++ = (gctPOINTER) ioremap_nocache(physical, device->externalSize);
++
++ if (device->externalLogical == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++ device->externalPhysical = (gctPHYS_ADDR)(gctUINTPTR_T) physical;
++ device->externalPhysicalName = gcmPTR_TO_NAME(device->externalPhysical);
++ physical += device->externalSize;
++ }
++ }
++
++ /* set up the contiguous memory */
++ device->contiguousSize = ContiguousSize;
++
++ if (ContiguousSize > 0)
++ {
++ if (ContiguousBase == 0)
++ {
++ while (device->contiguousSize > 0)
++ {
++ /* Allocate contiguous memory. */
++ status = _AllocateMemory(
++ device,
++ device->contiguousSize,
++ &device->contiguousBase,
++ &device->contiguousPhysical,
++ &physAddr
++ );
++
++ if (gcmIS_SUCCESS(status))
++ {
++ device->contiguousPhysicalName = gcmPTR_TO_NAME(device->contiguousPhysical);
++ status = gckVIDMEM_Construct(
++ device->os,
++ physAddr | device->systemMemoryBaseAddress,
++ device->contiguousSize,
++ 64,
++ BankSize,
++ &device->contiguousVidMem
++ );
++
++ if (gcmIS_SUCCESS(status))
++ {
++ break;
++ }
++
++ gcmkONERROR(_FreeMemory(
++ device,
++ device->contiguousBase,
++ device->contiguousPhysical
++ ));
++
++ gcmRELEASE_NAME(device->contiguousPhysicalName);
++ device->contiguousBase = gcvNULL;
++ device->contiguousPhysical = gcvNULL;
++ }
++
++ if (device->contiguousSize <= (4 << 20))
++ {
++ device->contiguousSize = 0;
++ }
++ else
++ {
++ device->contiguousSize -= (4 << 20);
++ }
++ }
++ }
++ else
++ {
++ /* Create the contiguous memory heap. */
++ status = gckVIDMEM_Construct(
++ device->os,
++ ContiguousBase | device->systemMemoryBaseAddress,
++ ContiguousSize,
++ 64, BankSize,
++ &device->contiguousVidMem
++ );
++
++ if (gcmIS_ERROR(status))
++ {
++ /* Error, disable contiguous memory pool. */
++ device->contiguousVidMem = gcvNULL;
++ device->contiguousSize = 0;
++ }
++ else
++ {
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,10,0)
++ mem_region = request_mem_region(
++ ContiguousBase, ContiguousSize, "galcore managed memory"
++ );
++
++ if (mem_region == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Failed to claim %ld bytes @ 0x%08X\n",
++ __FUNCTION__, __LINE__,
++ ContiguousSize, ContiguousBase
++ );
++
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++#endif
++
++ device->requestedContiguousBase = ContiguousBase;
++ device->requestedContiguousSize = ContiguousSize;
++
++#if !gcdDYNAMIC_MAP_RESERVED_MEMORY && gcdENABLE_VG
++ if (gcmIS_CORE_PRESENT(device, gcvCORE_VG))
++ {
++ device->contiguousBase
++#if gcdPAGED_MEMORY_CACHEABLE
++ = (gctPOINTER) ioremap_cached(ContiguousBase, ContiguousSize);
++#else
++ = (gctPOINTER) ioremap_nocache(ContiguousBase, ContiguousSize);
++#endif
++ if (device->contiguousBase == gcvNULL)
++ {
++ device->contiguousVidMem = gcvNULL;
++ device->contiguousSize = 0;
++
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++ }
++#endif
++
++ device->contiguousPhysical = gcvNULL;
++ device->contiguousPhysicalName = 0;
++ device->contiguousSize = ContiguousSize;
++ device->contiguousMapped = gcvTRUE;
++ }
++ }
++ }
++
++ /* Return pointer to the device. */
++ * Device = device;
++
++ gcmkFOOTER_ARG("*Device=0x%x", * Device);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Roll back. */
++ gcmkVERIFY_OK(gckGALDEVICE_Destroy(device));
++
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckGALDEVICE_Destroy
++**
++** Class destructor.
++**
++** INPUT:
++**
++** Nothing.
++**
++** OUTPUT:
++**
++** Nothing.
++**
++** RETURNS:
++**
++** Nothing.
++*/
++gceSTATUS
++gckGALDEVICE_Destroy(
++ gckGALDEVICE Device)
++{
++ gctINT i;
++ gceSTATUS status = gcvSTATUS_OK;
++ gckKERNEL kernel = gcvNULL;
++
++ gcmkHEADER_ARG("Device=0x%x", Device);
++
++ if (Device != gcvNULL)
++ {
++ /* Grab the first availiable kernel */
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ if (Device->irqLines[i] != -1)
++ {
++ kernel = Device->kernels[i];
++ break;
++ }
++ }
++ if (Device->internalPhysicalName != 0)
++ {
++ gcmRELEASE_NAME(Device->internalPhysicalName);
++ Device->internalPhysicalName = 0;
++ }
++ if (Device->externalPhysicalName != 0)
++ {
++ gcmRELEASE_NAME(Device->externalPhysicalName);
++ Device->externalPhysicalName = 0;
++ }
++ if (Device->contiguousPhysicalName != 0)
++ {
++ gcmRELEASE_NAME(Device->contiguousPhysicalName);
++ Device->contiguousPhysicalName = 0;
++ }
++
++
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ if (Device->kernels[i] != gcvNULL)
++ {
++ /* Destroy the gckKERNEL object. */
++ gcmkVERIFY_OK(gckKERNEL_Destroy(Device->kernels[i]));
++ Device->kernels[i] = gcvNULL;
++ }
++ }
++
++ {
++ if (Device->internalLogical != gcvNULL)
++ {
++ /* Unmap the internal memory. */
++ iounmap(Device->internalLogical);
++ Device->internalLogical = gcvNULL;
++ }
++
++ if (Device->internalVidMem != gcvNULL)
++ {
++ /* Destroy the internal heap. */
++ gcmkVERIFY_OK(gckVIDMEM_Destroy(Device->internalVidMem));
++ Device->internalVidMem = gcvNULL;
++ }
++ }
++
++ {
++ if (Device->externalLogical != gcvNULL)
++ {
++ /* Unmap the external memory. */
++ iounmap(Device->externalLogical);
++ Device->externalLogical = gcvNULL;
++ }
++
++ if (Device->externalVidMem != gcvNULL)
++ {
++ /* destroy the external heap */
++ gcmkVERIFY_OK(gckVIDMEM_Destroy(Device->externalVidMem));
++ Device->externalVidMem = gcvNULL;
++ }
++ }
++
++ {
++ if (Device->contiguousBase != gcvNULL)
++ {
++ if (Device->contiguousMapped)
++ {
++#if !gcdDYNAMIC_MAP_RESERVED_MEMORY && gcdENABLE_VG
++ if (Device->contiguousBase)
++ {
++ /* Unmap the contiguous memory. */
++ iounmap(Device->contiguousBase);
++ }
++#endif
++ }
++ else
++ {
++ gcmkONERROR(_FreeMemory(
++ Device,
++ Device->contiguousBase,
++ Device->contiguousPhysical
++ ));
++ }
++
++ Device->contiguousBase = gcvNULL;
++ Device->contiguousPhysical = gcvNULL;
++ }
++
++ if (Device->requestedContiguousBase != 0)
++ {
++ release_mem_region(Device->requestedContiguousBase, Device->requestedContiguousSize);
++ Device->requestedContiguousBase = 0;
++ Device->requestedContiguousSize = 0;
++ }
++
++ if (Device->contiguousVidMem != gcvNULL)
++ {
++ /* Destroy the contiguous heap. */
++ gcmkVERIFY_OK(gckVIDMEM_Destroy(Device->contiguousVidMem));
++ Device->contiguousVidMem = gcvNULL;
++ }
++ }
++
++ {
++ if(gckDebugFileSystemIsEnabled())
++ {
++ gckDebugFileSystemFreeNode(Device->dbgnode);
++ kfree(Device->dbgnode);
++ Device->dbgnode = gcvNULL;
++ }
++ }
++
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ if (Device->registerBases[i] != gcvNULL)
++ {
++ /* Unmap register memory. */
++ iounmap(Device->registerBases[i]);
++ if (Device->requestedRegisterMemBases[i] != 0)
++ {
++ release_mem_region(Device->requestedRegisterMemBases[i], Device->requestedRegisterMemSizes[i]);
++ }
++
++ Device->registerBases[i] = gcvNULL;
++ Device->requestedRegisterMemBases[i] = 0;
++ Device->requestedRegisterMemSizes[i] = 0;
++ }
++ }
++
++ /*Disable clock*/
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,5,0)
++ if (Device->clk_3d_axi) {
++ clk_put(Device->clk_3d_axi);
++ Device->clk_3d_axi = NULL;
++ }
++#endif
++ if (Device->clk_3d_core) {
++ clk_put(Device->clk_3d_core);
++ Device->clk_3d_core = NULL;
++ }
++ if (Device->clk_3d_shader) {
++ clk_put(Device->clk_3d_shader);
++ Device->clk_3d_shader = NULL;
++ }
++ if (Device->clk_2d_core) {
++ clk_put(Device->clk_2d_core);
++ Device->clk_2d_core = NULL;
++ }
++ if (Device->clk_2d_axi) {
++ clk_put(Device->clk_2d_axi);
++ Device->clk_2d_axi = NULL;
++ }
++ if (Device->clk_vg_axi) {
++ clk_put(Device->clk_vg_axi);
++ Device->clk_vg_axi = NULL;
++ }
++
++#ifdef CONFIG_PM
++ if(Device->pmdev)
++ pm_runtime_disable(Device->pmdev);
++#endif
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,5,0)
++ if (Device->gpu_regulator) {
++ regulator_put(Device->gpu_regulator);
++ Device->gpu_regulator = NULL;
++ }
++#endif
++
++ /* Destroy the gckOS object. */
++ if (Device->os != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_Destroy(Device->os));
++ Device->os = gcvNULL;
++ }
++
++ /* Free the device. */
++ kfree(Device);
++ }
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckGALDEVICE_Setup_ISR
++**
++** Start the ISR routine.
++**
++** INPUT:
++**
++** gckGALDEVICE Device
++** Pointer to an gckGALDEVICE object.
++**
++** OUTPUT:
++**
++** Nothing.
++**
++** RETURNS:
++**
++** gcvSTATUS_OK
++** Setup successfully.
++** gcvSTATUS_GENERIC_IO
++** Setup failed.
++*/
++gceSTATUS
++gckGALDEVICE_Setup_ISR(
++ IN gckGALDEVICE Device,
++ IN gceCORE Core
++ )
++{
++ gceSTATUS status;
++ gctINT ret = -1;
++
++ gcmkHEADER_ARG("Device=0x%x Core=%d", Device, Core);
++
++ gcmkVERIFY_ARGUMENT(Device != NULL);
++
++ if (Device->irqLines[Core] < 0)
++ {
++ gcmkONERROR(gcvSTATUS_GENERIC_IO);
++ }
++
++ /* Hook up the isr based on the irq line. */
++#ifdef FLAREON
++ gc500_handle.dev_name = "galcore interrupt service";
++ gc500_handle.dev_id = Device;
++ switch (Core) {
++ case gcvCORE_MAJOR:
++ gc500_handle.handler = isrRoutine;
++ break;
++ case gcvCORE_2D:
++ gc500_handle.handler = isrRoutine2D;
++ break;
++ case gcvCORE_VG:
++ gc500_handle.handler = isrRoutineVG;
++ break;
++ default:
++ break;
++ }
++ gc500_handle.intr_gen = GPIO_INTR_LEVEL_TRIGGER;
++ gc500_handle.intr_trig = GPIO_TRIG_HIGH_LEVEL;
++
++ ret = dove_gpio_request(
++ DOVE_GPIO0_7, &gc500_handle
++ );
++#else
++ switch (Core) {
++ case gcvCORE_MAJOR:
++ ret = request_irq(
++ Device->irqLines[Core], isrRoutine, 0x0/*IRQF_DISABLED*/,
++ "galcore interrupt service", Device
++ );
++ break;
++ case gcvCORE_2D:
++ ret = request_irq(
++ Device->irqLines[Core], isrRoutine2D, 0x0/*IRQF_DISABLED*/,
++ "galcore 2D interrupt service", Device
++ );
++ break;
++ case gcvCORE_VG:
++ ret = request_irq(
++ Device->irqLines[Core], isrRoutineVG, 0x0/*IRQF_DISABLED*/,
++ "galcore VG interrupt service", Device
++ );
++ break;
++ default:
++ break;
++ }
++#endif
++
++ if (ret != 0)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Could not register irq line %d (error=%d)\n",
++ __FUNCTION__, __LINE__,
++ Device->irqLines[Core], ret
++ );
++
++ gcmkONERROR(gcvSTATUS_GENERIC_IO);
++ }
++
++ Device->isrEnabled[Core] = 1;
++
++ /* Mark ISR as initialized. */
++ Device->isrInitializeds[Core] = gcvTRUE;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckGALDEVICE_Enable_ISR(
++ IN gckGALDEVICE Device,
++ IN gceCORE Core
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Device=0x%x Core=%d", Device, Core);
++
++ gcmkVERIFY_ARGUMENT(Device != NULL);
++
++ if (Device->irqLines[Core] < 0)
++ {
++ gcmkONERROR(gcvSTATUS_GENERIC_IO);
++ }
++
++ spin_lock(&Device->kernels[Core]->irq_lock);
++ if (Device->isrEnabled[Core] == 0)
++ {
++ enable_irq(Device->irqLines[Core]);
++ /* Mark ISR as initialized. */
++ Device->isrEnabled[Core] = gcvTRUE;
++ }
++ Device->isrEnabled[Core]++;
++ spin_unlock(&Device->kernels[Core]->irq_lock);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckGALDEVICE_Release_ISR
++**
++** Release the irq line.
++**
++** INPUT:
++**
++** gckGALDEVICE Device
++** Pointer to an gckGALDEVICE object.
++**
++** OUTPUT:
++**
++** Nothing.
++**
++** RETURNS:
++**
++** Nothing.
++*/
++gceSTATUS
++gckGALDEVICE_Release_ISR(
++ IN gckGALDEVICE Device,
++ IN gceCORE Core
++ )
++{
++ gcmkHEADER_ARG("Device=0x%x Core=%d", Device, Core);
++
++ gcmkVERIFY_ARGUMENT(Device != NULL);
++
++ /* release the irq */
++ if (Device->isrInitializeds[Core])
++ {
++#ifdef FLAREON
++ dove_gpio_free(DOVE_GPIO0_7, "galcore interrupt service");
++#else
++ free_irq(Device->irqLines[Core], Device);
++#endif
++
++ Device->isrInitializeds[Core] = gcvFALSE;
++ }
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckGALDEVICE_Disable_ISR(
++ IN gckGALDEVICE Device,
++ IN gceCORE Core
++ )
++{
++ gcmkHEADER_ARG("Device=0x%x Core=%d", Device, Core);
++
++ gcmkVERIFY_ARGUMENT(Device != NULL);
++
++ /* disable the irq */
++ spin_lock(&Device->kernels[Core]->irq_lock);
++ if (Device->isrEnabled[Core] > 0)
++ {
++ Device->isrEnabled[Core]--;
++ if (Device->isrEnabled[Core] == 0)
++ disable_irq(Device->irqLines[Core]);
++ }
++ spin_unlock(&Device->kernels[Core]->irq_lock);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckGALDEVICE_Start_Threads
++**
++** Start the daemon threads.
++**
++** INPUT:
++**
++** gckGALDEVICE Device
++** Pointer to an gckGALDEVICE object.
++**
++** OUTPUT:
++**
++** Nothing.
++**
++** RETURNS:
++**
++** gcvSTATUS_OK
++** Start successfully.
++** gcvSTATUS_GENERIC_IO
++** Start failed.
++*/
++gceSTATUS
++gckGALDEVICE_Start_Threads(
++ IN gckGALDEVICE Device
++ )
++{
++ gceSTATUS status;
++ struct task_struct * task;
++
++ gcmkHEADER_ARG("Device=0x%x", Device);
++
++ gcmkVERIFY_ARGUMENT(Device != NULL);
++
++ if (Device->kernels[gcvCORE_MAJOR] != gcvNULL)
++ {
++ /* Start the kernel thread. */
++ task = kthread_run(threadRoutine, Device, "galcore daemon thread");
++
++ if (IS_ERR(task))
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Could not start the kernel thread.\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_GENERIC_IO);
++ }
++
++ Device->threadCtxts[gcvCORE_MAJOR] = task;
++ Device->threadInitializeds[gcvCORE_MAJOR] = gcvTRUE;
++ }
++
++ if (Device->kernels[gcvCORE_2D] != gcvNULL)
++ {
++ /* Start the kernel thread. */
++ task = kthread_run(threadRoutine2D, Device, "galcore daemon thread for 2D");
++
++ if (IS_ERR(task))
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Could not start the kernel thread.\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_GENERIC_IO);
++ }
++
++ Device->threadCtxts[gcvCORE_2D] = task;
++ Device->threadInitializeds[gcvCORE_2D] = gcvTRUE;
++ }
++ else
++ {
++ Device->threadInitializeds[gcvCORE_2D] = gcvFALSE;
++ }
++
++ if (Device->kernels[gcvCORE_VG] != gcvNULL)
++ {
++ /* Start the kernel thread. */
++ task = kthread_run(threadRoutineVG, Device, "galcore daemon thread for VG");
++
++ if (IS_ERR(task))
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Could not start the kernel thread.\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_GENERIC_IO);
++ }
++
++ Device->threadCtxts[gcvCORE_VG] = task;
++ Device->threadInitializeds[gcvCORE_VG] = gcvTRUE;
++ }
++ else
++ {
++ Device->threadInitializeds[gcvCORE_VG] = gcvFALSE;
++ }
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckGALDEVICE_Stop_Threads
++**
++** Stop the gal device, including the following actions: stop the daemon
++** thread, release the irq.
++**
++** INPUT:
++**
++** gckGALDEVICE Device
++** Pointer to an gckGALDEVICE object.
++**
++** OUTPUT:
++**
++** Nothing.
++**
++** RETURNS:
++**
++** Nothing.
++*/
++gceSTATUS
++gckGALDEVICE_Stop_Threads(
++ gckGALDEVICE Device
++ )
++{
++ gctINT i;
++
++ gcmkHEADER_ARG("Device=0x%x", Device);
++
++ gcmkVERIFY_ARGUMENT(Device != NULL);
++
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ /* Stop the kernel threads. */
++ if (Device->threadInitializeds[i])
++ {
++ Device->killThread = gcvTRUE;
++ up(&Device->semas[i]);
++
++ kthread_stop(Device->threadCtxts[i]);
++ Device->threadCtxts[i] = gcvNULL;
++ Device->threadInitializeds[i] = gcvFALSE;
++ }
++ }
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckGALDEVICE_Start
++**
++** Start the gal device, including the following actions: setup the isr routine
++** and start the daemoni thread.
++**
++** INPUT:
++**
++** gckGALDEVICE Device
++** Pointer to an gckGALDEVICE object.
++**
++** OUTPUT:
++**
++** Nothing.
++**
++** RETURNS:
++**
++** gcvSTATUS_OK
++** Start successfully.
++*/
++gceSTATUS
++gckGALDEVICE_Start(
++ IN gckGALDEVICE Device
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Device=0x%x", Device);
++
++ /* Start the kernel thread. */
++ gcmkONERROR(gckGALDEVICE_Start_Threads(Device));
++
++ if (Device->kernels[gcvCORE_MAJOR] != gcvNULL)
++ {
++ /* Setup the ISR routine. */
++ gcmkONERROR(gckGALDEVICE_Setup_ISR(Device, gcvCORE_MAJOR));
++
++ /* Switch to SUSPEND power state. */
++ gcmkONERROR(gckHARDWARE_SetPowerManagementState(
++ Device->kernels[gcvCORE_MAJOR]->hardware, gcvPOWER_OFF_BROADCAST
++ ));
++ }
++
++ if (Device->kernels[gcvCORE_2D] != gcvNULL)
++ {
++ /* Setup the ISR routine. */
++ gcmkONERROR(gckGALDEVICE_Setup_ISR(Device, gcvCORE_2D));
++
++ /* Switch to SUSPEND power state. */
++ gcmkONERROR(gckHARDWARE_SetPowerManagementState(
++ Device->kernels[gcvCORE_2D]->hardware, gcvPOWER_OFF_BROADCAST
++ ));
++ }
++
++ if (Device->kernels[gcvCORE_VG] != gcvNULL)
++ {
++ /* Setup the ISR routine. */
++ gcmkONERROR(gckGALDEVICE_Setup_ISR(Device, gcvCORE_VG));
++
++ /* Switch to SUSPEND power state. */
++ gcmkONERROR(gckVGHARDWARE_SetPowerManagementState(
++ Device->kernels[gcvCORE_VG]->vg->hardware, gcvPOWER_OFF_BROADCAST
++ ));
++ }
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckGALDEVICE_Stop
++**
++** Stop the gal device, including the following actions: stop the daemon
++** thread, release the irq.
++**
++** INPUT:
++**
++** gckGALDEVICE Device
++** Pointer to an gckGALDEVICE object.
++**
++** OUTPUT:
++**
++** Nothing.
++**
++** RETURNS:
++**
++** Nothing.
++*/
++gceSTATUS
++gckGALDEVICE_Stop(
++ gckGALDEVICE Device
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Device=0x%x", Device);
++
++ gcmkVERIFY_ARGUMENT(Device != NULL);
++
++ if (Device->kernels[gcvCORE_MAJOR] != gcvNULL)
++ {
++ /* Switch to OFF power state. */
++ gcmkONERROR(gckHARDWARE_SetPowerManagementState(
++ Device->kernels[gcvCORE_MAJOR]->hardware, gcvPOWER_OFF
++ ));
++
++ /* Remove the ISR routine. */
++ gcmkONERROR(gckGALDEVICE_Release_ISR(Device, gcvCORE_MAJOR));
++ }
++
++ if (Device->kernels[gcvCORE_2D] != gcvNULL)
++ {
++ /* Setup the ISR routine. */
++ gcmkONERROR(gckGALDEVICE_Release_ISR(Device, gcvCORE_2D));
++
++ /* Switch to OFF power state. */
++ gcmkONERROR(gckHARDWARE_SetPowerManagementState(
++ Device->kernels[gcvCORE_2D]->hardware, gcvPOWER_OFF
++ ));
++ }
++
++ if (Device->kernels[gcvCORE_VG] != gcvNULL)
++ {
++ /* Setup the ISR routine. */
++ gcmkONERROR(gckGALDEVICE_Release_ISR(Device, gcvCORE_VG));
++
++#if gcdENABLE_VG
++ /* Switch to OFF power state. */
++ gcmkONERROR(gckVGHARDWARE_SetPowerManagementState(
++ Device->kernels[gcvCORE_VG]->vg->hardware, gcvPOWER_OFF
++ ));
++#endif
++ }
++
++ /* Stop the kernel thread. */
++ gcmkONERROR(gckGALDEVICE_Stop_Threads(Device));
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_device.h linux-xbian-imx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_device.h
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_device.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_device.h 2015-07-27 23:13:06.222780123 +0200
+@@ -0,0 +1,192 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_kernel_device_h_
++#define __gc_hal_kernel_device_h_
++
++/******************************************************************************\
++******************************* gckGALDEVICE Structure *******************************
++\******************************************************************************/
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
++struct contiguous_mem_pool {
++ struct dma_attrs attrs;
++ dma_addr_t phys;
++ void *virt;
++ size_t size;
++};
++#endif
++
++typedef struct _gckGALDEVICE
++{
++ /* Objects. */
++ gckOS os;
++ gckKERNEL kernels[gcdMAX_GPU_COUNT];
++
++ /* Attributes. */
++ gctSIZE_T internalSize;
++ gctPHYS_ADDR internalPhysical;
++ gctUINT32 internalPhysicalName;
++ gctPOINTER internalLogical;
++ gckVIDMEM internalVidMem;
++ gctSIZE_T externalSize;
++ gctPHYS_ADDR externalPhysical;
++ gctUINT32 externalPhysicalName;
++ gctPOINTER externalLogical;
++ gckVIDMEM externalVidMem;
++ gckVIDMEM contiguousVidMem;
++ gctPOINTER contiguousBase;
++ gctPHYS_ADDR contiguousPhysical;
++ gctUINT32 contiguousPhysicalName;
++ gctSIZE_T contiguousSize;
++ gctBOOL contiguousMapped;
++ gctPOINTER contiguousMappedUser;
++ gctSIZE_T systemMemorySize;
++ gctUINT32 systemMemoryBaseAddress;
++ gctPOINTER registerBases[gcdMAX_GPU_COUNT];
++ gctSIZE_T registerSizes[gcdMAX_GPU_COUNT];
++ gctUINT32 baseAddress;
++ gctUINT32 requestedRegisterMemBases[gcdMAX_GPU_COUNT];
++ gctSIZE_T requestedRegisterMemSizes[gcdMAX_GPU_COUNT];
++ gctUINT32 requestedContiguousBase;
++ gctSIZE_T requestedContiguousSize;
++
++ /* IRQ management. */
++ gctINT irqLines[gcdMAX_GPU_COUNT];
++ gctBOOL isrInitializeds[gcdMAX_GPU_COUNT];
++ gctINT isrEnabled[gcdMAX_GPU_COUNT];
++ gctBOOL dataReadys[gcdMAX_GPU_COUNT];
++
++ /* Thread management. */
++ struct task_struct *threadCtxts[gcdMAX_GPU_COUNT];
++ struct semaphore semas[gcdMAX_GPU_COUNT];
++ gctBOOL threadInitializeds[gcdMAX_GPU_COUNT];
++ gctBOOL killThread;
++
++ /* Signal management. */
++ gctINT signal;
++
++ /* Core mapping */
++ gceCORE coreMapping[8];
++
++ /* States before suspend. */
++ gceCHIPPOWERSTATE statesStored[gcdMAX_GPU_COUNT];
++
++ /*Device Debug File System Entry in Kernel*/
++ struct _gcsDebugFileSystemNode * dbgnode;
++
++ /* Clock management.*/
++ struct clk *clk_3d_core;
++ struct clk *clk_3d_shader;
++ struct clk *clk_3d_axi;
++ struct clk *clk_2d_core;
++ struct clk *clk_2d_axi;
++ struct clk *clk_vg_axi;
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,5,0) || LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
++ /*Power management.*/
++ struct regulator *gpu_regulator;
++#endif
++ /*Run time pm*/
++ struct device *pmdev;
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
++ struct contiguous_mem_pool *pool;
++ struct reset_control *rstc[gcdMAX_GPU_COUNT];
++#endif
++}
++* gckGALDEVICE;
++
++typedef struct _gcsHAL_PRIVATE_DATA
++{
++ gckGALDEVICE device;
++ gctPOINTER mappedMemory;
++ gctPOINTER contiguousLogical;
++ /* The process opening the device may not be the same as the one that closes it. */
++ gctUINT32 pidOpen;
++}
++gcsHAL_PRIVATE_DATA, * gcsHAL_PRIVATE_DATA_PTR;
++
++gceSTATUS gckGALDEVICE_Enable_ISR(
++ IN gckGALDEVICE Device,
++ IN gceCORE Core
++ );
++
++gceSTATUS gckGALDEVICE_Disable_ISR(
++ IN gckGALDEVICE Device,
++ IN gceCORE Core
++ );
++
++gceSTATUS gckGALDEVICE_Setup_ISR(
++ IN gckGALDEVICE Device,
++ IN gceCORE Core
++ );
++
++gceSTATUS gckGALDEVICE_Release_ISR(
++ IN gckGALDEVICE Device,
++ IN gceCORE Core
++ );
++
++gceSTATUS gckGALDEVICE_Start_Threads(
++ IN gckGALDEVICE Device
++ );
++
++gceSTATUS gckGALDEVICE_Stop_Threads(
++ gckGALDEVICE Device
++ );
++
++gceSTATUS gckGALDEVICE_Start(
++ IN gckGALDEVICE Device
++ );
++
++gceSTATUS gckGALDEVICE_Stop(
++ gckGALDEVICE Device
++ );
++
++gceSTATUS gckGALDEVICE_Construct(
++ IN gctINT IrqLine,
++ IN gctUINT32 RegisterMemBase,
++ IN gctSIZE_T RegisterMemSize,
++ IN gctINT IrqLine2D,
++ IN gctUINT32 RegisterMemBase2D,
++ IN gctSIZE_T RegisterMemSize2D,
++ IN gctINT IrqLineVG,
++ IN gctUINT32 RegisterMemBaseVG,
++ IN gctSIZE_T RegisterMemSizeVG,
++ IN gctUINT32 ContiguousBase,
++ IN gctSIZE_T ContiguousSize,
++ IN gctSIZE_T BankSize,
++ IN gctINT FastClear,
++ IN gctINT Compression,
++ IN gctUINT32 PhysBaseAddr,
++ IN gctUINT32 PhysSize,
++ IN gctINT Signal,
++ IN gctUINT LogFileSize,
++ IN struct device *pdev,
++ IN gctINT PowerManagement,
++ IN gctINT GpuProfiler,
++ OUT gckGALDEVICE *Device
++ );
++
++gceSTATUS gckGALDEVICE_Destroy(
++ IN gckGALDEVICE Device
++ );
++
++#endif /* __gc_hal_kernel_device_h_ */
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_driver.c linux-xbian-imx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_driver.c
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_driver.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_driver.c 2015-07-27 23:13:06.222780123 +0200
+@@ -0,0 +1,1476 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++* Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++#include <linux/device.h>
++#include <linux/slab.h>
++#include <linux/notifier.h>
++#include "gc_hal_kernel_linux.h"
++#include "gc_hal_driver.h"
++
++#if USE_PLATFORM_DRIVER
++# include <linux/platform_device.h>
++#endif
++
++#ifdef CONFIG_PXA_DVFM
++# include <mach/dvfm.h>
++# include <mach/pxa3xx_dvfm.h>
++#endif
++
++
++#ifdef CONFIG_ANDROID_RESERVED_MEMORY_ACCOUNT
++# include <linux/resmem_account.h>
++# include <linux/kernel.h>
++# include <linux/mm.h>
++# include <linux/oom.h>
++# include <linux/sched.h>
++# include <linux/notifier.h>
++
++struct task_struct *lowmem_deathpending;
++
++static int
++task_notify_func(struct notifier_block *self, unsigned long val, void *data);
++
++static struct notifier_block task_nb = {
++ .notifier_call = task_notify_func,
++};
++
++static int
++task_notify_func(struct notifier_block *self, unsigned long val, void *data)
++{
++ struct task_struct *task = data;
++
++ if (task == lowmem_deathpending)
++ lowmem_deathpending = NULL;
++
++ return NOTIFY_OK;
++}
++#endif
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,5,0)
++#include <mach/viv_gpu.h>
++#else
++#include <linux/pm_runtime.h>
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 10, 0)
++#include <mach/busfreq.h>
++#else
++#include <linux/busfreq-imx6.h>
++#include <linux/reset.h>
++#endif
++#endif
++/* Zone used for header/footer. */
++#define _GC_OBJ_ZONE gcvZONE_DRIVER
++
++#if gcdENABLE_FSCALE_VAL_ADJUST
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
++#include <linux/device_cooling.h>
++#define REG_THERMAL_NOTIFIER(a) register_devfreq_cooling_notifier(a);
++#define UNREG_THERMAL_NOTIFIER(a) unregister_devfreq_cooling_notifier(a);
++#else
++extern int register_thermal_notifier(struct notifier_block *nb);
++extern int unregister_thermal_notifier(struct notifier_block *nb);
++#define REG_THERMAL_NOTIFIER(a) register_thermal_notifier(a);
++#define UNREG_THERMAL_NOTIFIER(a) unregister_thermal_notifier(a);
++#endif
++#endif
++
++MODULE_DESCRIPTION("Vivante Graphics Driver");
++MODULE_LICENSE("GPL");
++
++static struct class* gpuClass;
++
++static gckGALDEVICE galDevice;
++
++static uint major = 199;
++module_param(major, uint, 0644);
++
++static int irqLine = -1;
++module_param(irqLine, int, 0644);
++
++static ulong registerMemBase = 0x80000000;
++module_param(registerMemBase, ulong, 0644);
++
++static ulong registerMemSize = 2 << 10;
++module_param(registerMemSize, ulong, 0644);
++
++static int irqLine2D = -1;
++module_param(irqLine2D, int, 0644);
++
++static ulong registerMemBase2D = 0x00000000;
++module_param(registerMemBase2D, ulong, 0644);
++
++static ulong registerMemSize2D = 2 << 10;
++module_param(registerMemSize2D, ulong, 0644);
++
++static int irqLineVG = -1;
++module_param(irqLineVG, int, 0644);
++
++static ulong registerMemBaseVG = 0x00000000;
++module_param(registerMemBaseVG, ulong, 0644);
++
++static ulong registerMemSizeVG = 2 << 10;
++module_param(registerMemSizeVG, ulong, 0644);
++
++#if gcdENABLE_FSCALE_VAL_ADJUST
++static ulong contiguousSize = 128 << 20;
++#else
++static ulong contiguousSize = 4 << 20;
++#endif
++module_param(contiguousSize, ulong, 0644);
++
++static ulong contiguousBase = 0;
++module_param(contiguousBase, ulong, 0644);
++
++static ulong bankSize = 0;
++module_param(bankSize, ulong, 0644);
++
++static int fastClear = -1;
++module_param(fastClear, int, 0644);
++
++static int compression = -1;
++module_param(compression, int, 0644);
++
++static int powerManagement = 1;
++module_param(powerManagement, int, 0644);
++
++static int gpuProfiler = 0;
++module_param(gpuProfiler, int, 0644);
++
++static int signal = 48;
++module_param(signal, int, 0644);
++
++static ulong baseAddress = 0;
++module_param(baseAddress, ulong, 0644);
++
++static ulong physSize = 0;
++module_param(physSize, ulong, 0644);
++
++static uint logFileSize=0;
++module_param(logFileSize,uint, 0644);
++
++static int showArgs = 0;
++module_param(showArgs, int, 0644);
++
++int gpu3DMinClock = 0;
++module_param(gpu3DMinClock, int, 0644);
++
++#if ENABLE_GPU_CLOCK_BY_DRIVER
++ unsigned long coreClock = 156000000;
++ module_param(coreClock, ulong, 0644);
++#endif
++
++static int drv_open(
++ struct inode* inode,
++ struct file* filp
++ );
++
++static int drv_release(
++ struct inode* inode,
++ struct file* filp
++ );
++
++static long drv_ioctl(
++ struct file* filp,
++ unsigned int ioctlCode,
++ unsigned long arg
++ );
++
++static int drv_mmap(
++ struct file* filp,
++ struct vm_area_struct* vma
++ );
++
++static struct file_operations driver_fops =
++{
++ .owner = THIS_MODULE,
++ .open = drv_open,
++ .release = drv_release,
++ .unlocked_ioctl = drv_ioctl,
++#ifdef HAVE_COMPAT_IOCTL
++ .compat_ioctl = drv_ioctl,
++#endif
++ .mmap = drv_mmap,
++};
++
++#ifdef CONFIG_ANDROID_RESERVED_MEMORY_ACCOUNT
++static size_t viv_gpu_resmem_query(struct task_struct *p, struct reserved_memory_account *m);
++static struct reserved_memory_account viv_gpu_resmem_handler = {
++ .name = "viv_gpu",
++ .get_page_used_by_process = viv_gpu_resmem_query,
++};
++
++size_t viv_gpu_resmem_query(struct task_struct *p, struct reserved_memory_account *m)
++{
++ gcuDATABASE_INFO info;
++ unsigned int processid = p->pid;
++ gckKERNEL gpukernel = m->data;
++
++ /* ignore error happens in this api. */
++ if (gckKERNEL_QueryProcessDB(gpukernel, processid, false, gcvDB_VIDEO_MEMORY, &info) != gcvSTATUS_OK)
++ return 0;
++
++ /* we return pages. */
++ if (info.counters.bytes > 0)
++ return info.counters.bytes / PAGE_SIZE;
++ return 0;
++}
++#endif
++
++int drv_open(
++ struct inode* inode,
++ struct file* filp
++ )
++{
++ gceSTATUS status;
++ gctBOOL attached = gcvFALSE;
++ gcsHAL_PRIVATE_DATA_PTR data = gcvNULL;
++ gctINT i;
++
++ gcmkHEADER_ARG("inode=0x%08X filp=0x%08X", inode, filp);
++
++ if (filp == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): filp is NULL\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ data = kmalloc(sizeof(gcsHAL_PRIVATE_DATA), GFP_KERNEL);
++
++ if (data == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): private_data is NULL\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ data->device = galDevice;
++ data->mappedMemory = gcvNULL;
++ data->contiguousLogical = gcvNULL;
++ gcmkONERROR(gckOS_GetProcessID(&data->pidOpen));
++
++ /* Attached the process. */
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ if (galDevice->kernels[i] != gcvNULL)
++ {
++ gcmkONERROR(gckKERNEL_AttachProcess(galDevice->kernels[i], gcvTRUE));
++ }
++ }
++ attached = gcvTRUE;
++
++ if (!galDevice->contiguousMapped)
++ {
++ gcmkONERROR(gckOS_MapMemory(
++ galDevice->os,
++ galDevice->contiguousPhysical,
++ galDevice->contiguousSize,
++ &data->contiguousLogical
++ ));
++ }
++
++ filp->private_data = data;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return 0;
++
++OnError:
++ if (data != gcvNULL)
++ {
++ if (data->contiguousLogical != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_UnmapMemory(
++ galDevice->os,
++ galDevice->contiguousPhysical,
++ galDevice->contiguousSize,
++ data->contiguousLogical
++ ));
++ }
++
++ kfree(data);
++ }
++
++ if (attached)
++ {
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ if (galDevice->kernels[i] != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckKERNEL_AttachProcess(galDevice->kernels[i], gcvFALSE));
++ }
++ }
++ }
++
++ gcmkFOOTER();
++ return -ENOTTY;
++}
++
++int drv_release(
++ struct inode* inode,
++ struct file* filp
++ )
++{
++ gceSTATUS status;
++ gcsHAL_PRIVATE_DATA_PTR data;
++ gckGALDEVICE device;
++ gctINT i;
++
++ gcmkHEADER_ARG("inode=0x%08X filp=0x%08X", inode, filp);
++
++ if (filp == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): filp is NULL\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ data = filp->private_data;
++
++ if (data == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): private_data is NULL\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ device = data->device;
++
++ if (device == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): device is NULL\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ if (!device->contiguousMapped)
++ {
++ if (data->contiguousLogical != gcvNULL)
++ {
++ gcmkONERROR(gckOS_UnmapMemoryEx(
++ galDevice->os,
++ galDevice->contiguousPhysical,
++ galDevice->contiguousSize,
++ data->contiguousLogical,
++ data->pidOpen
++ ));
++
++ data->contiguousLogical = gcvNULL;
++ }
++ }
++
++ /* A process gets detached. */
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ if (galDevice->kernels[i] != gcvNULL)
++ {
++ gcmkONERROR(gckKERNEL_AttachProcessEx(galDevice->kernels[i], gcvFALSE, data->pidOpen));
++ }
++ }
++
++ kfree(data);
++ filp->private_data = NULL;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return 0;
++
++OnError:
++ gcmkFOOTER();
++ return -ENOTTY;
++}
++
++long drv_ioctl(
++ struct file* filp,
++ unsigned int ioctlCode,
++ unsigned long arg
++ )
++{
++ gceSTATUS status;
++ gcsHAL_INTERFACE iface;
++ gctUINT32 copyLen;
++ DRIVER_ARGS drvArgs;
++ gckGALDEVICE device;
++ gcsHAL_PRIVATE_DATA_PTR data;
++ gctINT32 i, count;
++
++ gcmkHEADER_ARG(
++ "filp=0x%08X ioctlCode=0x%08X arg=0x%08X",
++ filp, ioctlCode, arg
++ );
++
++ if (filp == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): filp is NULL\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ data = filp->private_data;
++
++ if (data == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): private_data is NULL\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ device = data->device;
++
++ if (device == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): device is NULL\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ if ((ioctlCode != IOCTL_GCHAL_INTERFACE)
++ && (ioctlCode != IOCTL_GCHAL_KERNEL_INTERFACE)
++ )
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): unknown command %d\n",
++ __FUNCTION__, __LINE__,
++ ioctlCode
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ /* Get the drvArgs. */
++ copyLen = copy_from_user(
++ &drvArgs, (void *) arg, sizeof(DRIVER_ARGS)
++ );
++
++ if (copyLen != 0)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): error copying of the input arguments.\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ /* Now bring in the gcsHAL_INTERFACE structure. */
++ if ((drvArgs.InputBufferSize != sizeof(gcsHAL_INTERFACE))
++ || (drvArgs.OutputBufferSize != sizeof(gcsHAL_INTERFACE))
++ )
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): input or/and output structures are invalid.\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ copyLen = copy_from_user(
++ &iface, gcmUINT64_TO_PTR(drvArgs.InputBuffer), sizeof(gcsHAL_INTERFACE)
++ );
++
++ if (copyLen != 0)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): error copying of input HAL interface.\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ if (iface.command == gcvHAL_CHIP_INFO)
++ {
++ count = 0;
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ if (device->kernels[i] != gcvNULL)
++ {
++#if gcdENABLE_VG
++ if (i == gcvCORE_VG)
++ {
++ iface.u.ChipInfo.types[count] = gcvHARDWARE_VG;
++ }
++ else
++#endif
++ {
++ gcmkVERIFY_OK(gckHARDWARE_GetType(device->kernels[i]->hardware,
++ &iface.u.ChipInfo.types[count]));
++ }
++ count++;
++ }
++ }
++
++ iface.u.ChipInfo.count = count;
++ iface.status = status = gcvSTATUS_OK;
++ }
++ else
++ {
++ if (iface.hardwareType < 0 || iface.hardwareType > 7)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): unknown hardwareType %d\n",
++ __FUNCTION__, __LINE__,
++ iface.hardwareType
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++#if gcdENABLE_VG
++ if (device->coreMapping[iface.hardwareType] == gcvCORE_VG)
++ {
++ status = gckVGKERNEL_Dispatch(device->kernels[gcvCORE_VG],
++ (ioctlCode == IOCTL_GCHAL_INTERFACE),
++ &iface);
++ }
++ else
++#endif
++ {
++ status = gckKERNEL_Dispatch(device->kernels[device->coreMapping[iface.hardwareType]],
++ (ioctlCode == IOCTL_GCHAL_INTERFACE),
++ &iface);
++ }
++ }
++
++ /* Redo system call after pending signal is handled. */
++ if (status == gcvSTATUS_INTERRUPTED)
++ {
++ gcmkFOOTER();
++ return -ERESTARTSYS;
++ }
++
++ if (gcmIS_SUCCESS(status) && (iface.command == gcvHAL_LOCK_VIDEO_MEMORY))
++ {
++ gcuVIDMEM_NODE_PTR node = gcmUINT64_TO_PTR(iface.u.LockVideoMemory.node);
++ /* Special case for mapped memory. */
++ if ((data->mappedMemory != gcvNULL)
++ && (node->VidMem.memory->object.type == gcvOBJ_VIDMEM)
++ )
++ {
++ /* Compute offset into mapped memory. */
++ gctUINT32 offset
++ = (gctUINT8 *) gcmUINT64_TO_PTR(iface.u.LockVideoMemory.memory)
++ - (gctUINT8 *) device->contiguousBase;
++
++ /* Compute offset into user-mapped region. */
++ iface.u.LockVideoMemory.memory =
++ gcmPTR_TO_UINT64((gctUINT8 *) data->mappedMemory + offset);
++ }
++ }
++
++ /* Copy data back to the user. */
++ copyLen = copy_to_user(
++ gcmUINT64_TO_PTR(drvArgs.OutputBuffer), &iface, sizeof(gcsHAL_INTERFACE)
++ );
++
++ if (copyLen != 0)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): error copying of output HAL interface.\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return 0;
++
++OnError:
++ gcmkFOOTER();
++ return -ENOTTY;
++}
++
++static int drv_mmap(
++ struct file* filp,
++ struct vm_area_struct* vma
++ )
++{
++ gceSTATUS status = gcvSTATUS_OK;
++ gcsHAL_PRIVATE_DATA_PTR data;
++ gckGALDEVICE device;
++
++ gcmkHEADER_ARG("filp=0x%08X vma=0x%08X", filp, vma);
++
++ if (filp == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): filp is NULL\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ data = filp->private_data;
++
++ if (data == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): private_data is NULL\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ device = data->device;
++
++ if (device == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): device is NULL\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++#if !gcdPAGED_MEMORY_CACHEABLE
++ vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
++ vma->vm_flags |= gcdVM_FLAGS;
++#endif
++ vma->vm_pgoff = 0;
++
++ if (device->contiguousMapped)
++ {
++ unsigned long size = vma->vm_end - vma->vm_start;
++ int ret = 0;
++
++ if (size > device->contiguousSize)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Invalid mapping size.\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ ret = io_remap_pfn_range(
++ vma,
++ vma->vm_start,
++ device->requestedContiguousBase >> PAGE_SHIFT,
++ size,
++ vma->vm_page_prot
++ );
++
++ if (ret != 0)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): io_remap_pfn_range failed %d\n",
++ __FUNCTION__, __LINE__,
++ ret
++ );
++
++ data->mappedMemory = gcvNULL;
++
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++ data->mappedMemory = (gctPOINTER) vma->vm_start;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return 0;
++ }
++
++
++OnError:
++ gcmkFOOTER();
++ return -ENOTTY;
++}
++
++
++#if !USE_PLATFORM_DRIVER
++static int __init drv_init(void)
++#else
++static int drv_init(struct device *pdev)
++#endif
++{
++ int ret;
++ int result = -EINVAL;
++ gceSTATUS status;
++ gckGALDEVICE device = gcvNULL;
++ struct class* device_class = gcvNULL;
++
++ gcmkHEADER();
++
++#if ENABLE_GPU_CLOCK_BY_DRIVER && (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,28))
++ {
++# if 0
++ struct clk * clk;
++
++ clk = clk_get(NULL, "GCCLK");
++
++ if (IS_ERR(clk))
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): clk get error: %d\n",
++ __FUNCTION__, __LINE__,
++ PTR_ERR(clk)
++ );
++
++ result = -ENODEV;
++ gcmkONERROR(gcvSTATUS_GENERIC_IO);
++ }
++
++ /*
++ * APMU_GC_156M, APMU_GC_312M, APMU_GC_PLL2, APMU_GC_PLL2_DIV2 currently.
++ * Use the 2X clock.
++ */
++ if (clk_set_rate(clk, coreClock * 2))
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Failed to set core clock.\n",
++ __FUNCTION__, __LINE__
++ );
++
++ result = -EAGAIN;
++ gcmkONERROR(gcvSTATUS_GENERIC_IO);
++ }
++
++ clk_enable(clk);
++
++#if defined(CONFIG_PXA_DVFM) && (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,29))
++ gc_pwr(1);
++# endif
++# endif
++ }
++#endif
++
++ printk(KERN_INFO "Galcore version %d.%d.%d.%d\n",
++ gcvVERSION_MAJOR, gcvVERSION_MINOR, gcvVERSION_PATCH, gcvVERSION_BUILD);
++ /* when enable gpu profiler, we need to turn off gpu powerMangement */
++ if(gpuProfiler)
++ powerManagement = 0;
++ if (showArgs)
++ {
++ printk("galcore options:\n");
++ printk(" irqLine = %d\n", irqLine);
++ printk(" registerMemBase = 0x%08lX\n", registerMemBase);
++ printk(" registerMemSize = 0x%08lX\n", registerMemSize);
++
++ if (irqLine2D != -1)
++ {
++ printk(" irqLine2D = %d\n", irqLine2D);
++ printk(" registerMemBase2D = 0x%08lX\n", registerMemBase2D);
++ printk(" registerMemSize2D = 0x%08lX\n", registerMemSize2D);
++ }
++
++ if (irqLineVG != -1)
++ {
++ printk(" irqLineVG = %d\n", irqLineVG);
++ printk(" registerMemBaseVG = 0x%08lX\n", registerMemBaseVG);
++ printk(" registerMemSizeVG = 0x%08lX\n", registerMemSizeVG);
++ }
++
++ printk(" contiguousSize = %ld\n", contiguousSize);
++ printk(" contiguousBase = 0x%08lX\n", contiguousBase);
++ printk(" bankSize = 0x%08lX\n", bankSize);
++ printk(" fastClear = %d\n", fastClear);
++ printk(" compression = %d\n", compression);
++ printk(" signal = %d\n", signal);
++ printk(" baseAddress = 0x%08lX\n", baseAddress);
++ printk(" physSize = 0x%08lX\n", physSize);
++ printk(" logFileSize = %d KB \n", logFileSize);
++ printk(" powerManagement = %d\n", powerManagement);
++ printk(" gpuProfiler = %d\n", gpuProfiler);
++#if ENABLE_GPU_CLOCK_BY_DRIVER
++ printk(" coreClock = %lu\n", coreClock);
++#endif
++ }
++
++ if(logFileSize != 0)
++ {
++ gckDebugFileSystemInitialize();
++ }
++
++ /* Create the GAL device. */
++ gcmkONERROR(gckGALDEVICE_Construct(
++ irqLine,
++ registerMemBase, registerMemSize,
++ irqLine2D,
++ registerMemBase2D, registerMemSize2D,
++ irqLineVG,
++ registerMemBaseVG, registerMemSizeVG,
++ contiguousBase, contiguousSize,
++ bankSize, fastClear, compression, baseAddress, physSize, signal,
++ logFileSize,
++ pdev,
++ powerManagement,
++ gpuProfiler,
++ &device
++ ));
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
++ device->pool = dev_get_drvdata(pdev);
++#endif
++
++ /* Start the GAL device. */
++ gcmkONERROR(gckGALDEVICE_Start(device));
++
++ if ((physSize != 0)
++ && (device->kernels[gcvCORE_MAJOR] != gcvNULL)
++ && (device->kernels[gcvCORE_MAJOR]->hardware->mmuVersion != 0))
++ {
++ status = gckMMU_Enable(device->kernels[gcvCORE_MAJOR]->mmu, baseAddress, physSize);
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_DRIVER,
++ "Enable new MMU: status=%d\n", status);
++
++ if ((device->kernels[gcvCORE_2D] != gcvNULL)
++ && (device->kernels[gcvCORE_2D]->hardware->mmuVersion != 0))
++ {
++ status = gckMMU_Enable(device->kernels[gcvCORE_2D]->mmu, baseAddress, physSize);
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_DRIVER,
++ "Enable new MMU for 2D: status=%d\n", status);
++ }
++
++ /* Reset the base address */
++ device->baseAddress = 0;
++ }
++
++#ifdef CONFIG_ANDROID_RESERVED_MEMORY_ACCOUNT
++ task_free_register(&task_nb);
++ viv_gpu_resmem_handler.data = device->kernels[gcvCORE_MAJOR];
++ register_reserved_memory_account(&viv_gpu_resmem_handler);
++#endif
++
++
++ /* Register the character device. */
++ ret = register_chrdev(major, DRV_NAME, &driver_fops);
++
++ if (ret < 0)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Could not allocate major number for mmap.\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ if (major == 0)
++ {
++ major = ret;
++ }
++
++ /* Create the device class. */
++ device_class = class_create(THIS_MODULE, "graphics_class");
++
++ if (IS_ERR(device_class))
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Failed to create the class.\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
++ device_create(device_class, NULL, MKDEV(major, 0), NULL, "galcore");
++#else
++ device_create(device_class, NULL, MKDEV(major, 0), "galcore");
++#endif
++
++ galDevice = device;
++ gpuClass = device_class;
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_DRIVER,
++ "%s(%d): irqLine=%d, contiguousSize=%lu, memBase=0x%lX\n",
++ __FUNCTION__, __LINE__,
++ irqLine, contiguousSize, registerMemBase
++ );
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return 0;
++
++OnError:
++ /* Roll back. */
++ if (device_class != gcvNULL)
++ {
++ device_destroy(device_class, MKDEV(major, 0));
++ class_destroy(device_class);
++ }
++
++ if (device != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckGALDEVICE_Stop(device));
++ gcmkVERIFY_OK(gckGALDEVICE_Destroy(device));
++ }
++
++ gcmkFOOTER();
++ return result;
++}
++
++#if !USE_PLATFORM_DRIVER
++static void __exit drv_exit(void)
++#else
++static void drv_exit(void)
++#endif
++{
++ gcmkHEADER();
++
++#ifdef CONFIG_ANDROID_RESERVED_MEMORY_ACCOUNT
++ task_free_unregister(&task_nb);
++ unregister_reserved_memory_account(&viv_gpu_resmem_handler);
++#endif
++
++ gcmkASSERT(gpuClass != gcvNULL);
++ device_destroy(gpuClass, MKDEV(major, 0));
++ class_destroy(gpuClass);
++
++ unregister_chrdev(major, DRV_NAME);
++
++ gcmkVERIFY_OK(gckGALDEVICE_Stop(galDevice));
++ gcmkVERIFY_OK(gckGALDEVICE_Destroy(galDevice));
++
++ if(gckDebugFileSystemIsEnabled())
++ {
++ gckDebugFileSystemTerminate();
++ }
++
++#if ENABLE_GPU_CLOCK_BY_DRIVER && LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,28)
++ {
++# if 0
++ struct clk * clk = NULL;
++
++#if defined(CONFIG_PXA_DVFM) && (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,29))
++ gc_pwr(0);
++#endif
++ clk = clk_get(NULL, "GCCLK");
++ clk_disable(clk);
++# endif
++ }
++#endif
++
++ gcmkFOOTER_NO();
++}
++
++#if !USE_PLATFORM_DRIVER
++ module_init(drv_init);
++ module_exit(drv_exit);
++#else
++
++#ifdef CONFIG_DOVE_GPU
++# define DEVICE_NAME "dove_gpu"
++#else
++# define DEVICE_NAME "galcore"
++#endif
++
++#if gcdENABLE_FSCALE_VAL_ADJUST
++static int thermal_hot_pm_notify(struct notifier_block *nb, unsigned long event,
++ void *dummy)
++{
++ static gctUINT orgFscale, minFscale, maxFscale;
++ static gctBOOL critical;
++ gckHARDWARE hardware = galDevice->kernels[gcvCORE_MAJOR]->hardware;
++
++ if (event > 4) {
++ critical = gcvTRUE;
++ gckHARDWARE_GetFscaleValue(hardware,&orgFscale,&minFscale, &maxFscale);
++ gckHARDWARE_SetFscaleValue(hardware, minFscale);
++ gckOS_Print("System is too hot. GPU3D scalign to %d/64 clock.\n", minFscale);
++ } else if (event > 1) {
++ gckHARDWARE_GetFscaleValue(hardware,&orgFscale,&minFscale, &maxFscale);
++ gckHARDWARE_SetFscaleValue(hardware, maxFscale - (8 * event));
++ } else if (orgFscale) {
++ gckHARDWARE_SetFscaleValue(hardware, orgFscale);
++ if (critical) {
++ gckOS_Print("Hot alarm is canceled. GPU3D clock will return to %d/64\n", orgFscale);
++ critical = gcvFALSE;
++ }
++ }
++ return NOTIFY_OK;
++}
++
++static struct notifier_block thermal_hot_pm_notifier = {
++ .notifier_call = thermal_hot_pm_notify,
++ };
++#endif
++
++
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)
++static int gpu_probe(struct platform_device *pdev)
++#else
++static int __devinit gpu_probe(struct platform_device *pdev)
++#endif
++{
++ int ret = -ENODEV;
++ struct resource* res;
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
++ struct contiguous_mem_pool *pool;
++ struct reset_control *rstc;
++#elif LINUX_VERSION_CODE >= KERNEL_VERSION(3,5,0)
++ struct device_node *dn =pdev->dev.of_node;
++ const u32 *prop;
++#else
++ struct viv_gpu_platform_data *pdata;
++#endif
++ gcmkHEADER();
++
++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phys_baseaddr");
++ if (res)
++ baseAddress = res->start;
++
++ res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "irq_3d");
++ if (res)
++ irqLine = res->start;
++
++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "iobase_3d");
++ if (res)
++ {
++ registerMemBase = res->start;
++ registerMemSize = res->end - res->start + 1;
++ }
++
++ res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "irq_2d");
++ if (res)
++ irqLine2D = res->start;
++
++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "iobase_2d");
++ if (res)
++ {
++ registerMemBase2D = res->start;
++ registerMemSize2D = res->end - res->start + 1;
++ }
++
++ res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "irq_vg");
++ if (res)
++ irqLineVG = res->start;
++
++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "iobase_vg");
++ if (res)
++ {
++ registerMemBaseVG = res->start;
++ registerMemSizeVG = res->end - res->start + 1;
++ }
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
++ pool = devm_kzalloc(&pdev->dev, sizeof(*pool), GFP_KERNEL);
++ if (!pool)
++ return -ENOMEM;
++ pool->size = contiguousSize;
++ init_dma_attrs(&pool->attrs);
++ dma_set_attr(DMA_ATTR_WRITE_COMBINE, &pool->attrs);
++ pool->virt = dma_alloc_attrs(&pdev->dev, pool->size, &pool->phys,
++ GFP_KERNEL, &pool->attrs);
++ if (!pool->virt) {
++ dev_err(&pdev->dev, "Failed to allocate contiguous memory\n");
++ return -ENOMEM;
++ }
++ contiguousBase = pool->phys;
++ dev_set_drvdata(&pdev->dev, pool);
++#elif LINUX_VERSION_CODE >= KERNEL_VERSION(3,5,0)
++ prop = of_get_property(dn, "contiguousbase", NULL);
++ if(prop)
++ contiguousBase = *prop;
++ of_property_read_u32(dn,"contiguoussize", (u32 *)&contiguousSize);
++#else
++ pdata = pdev->dev.platform_data;
++ if (pdata) {
++ contiguousBase = pdata->reserved_mem_base;
++ contiguousSize = pdata->reserved_mem_size;
++ }
++#endif
++ if (contiguousSize == 0)
++ gckOS_Print("Warning: No contiguous memory is reserverd for gpu.!\n ");
++ ret = drv_init(&pdev->dev);
++
++ if (!ret)
++ {
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
++ rstc = devm_reset_control_get(&pdev->dev, "gpu3d");
++ galDevice->rstc[gcvCORE_MAJOR] = IS_ERR(rstc) ? NULL : rstc;
++
++ rstc = devm_reset_control_get(&pdev->dev, "gpu2d");
++ galDevice->rstc[gcvCORE_2D] = IS_ERR(rstc) ? NULL : rstc;
++
++ rstc = devm_reset_control_get(&pdev->dev, "gpuvg");
++ galDevice->rstc[gcvCORE_VG] = IS_ERR(rstc) ? NULL : rstc;
++#endif
++ platform_set_drvdata(pdev, galDevice);
++
++#if gcdENABLE_FSCALE_VAL_ADJUST
++ if (galDevice->kernels[gcvCORE_MAJOR])
++ REG_THERMAL_NOTIFIER(&thermal_hot_pm_notifier);
++#endif
++ gcmkFOOTER_NO();
++ return ret;
++ }
++#if gcdENABLE_FSCALE_VAL_ADJUST
++ UNREG_THERMAL_NOTIFIER(&thermal_hot_pm_notifier);
++#endif
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
++ dma_free_attrs(&pdev->dev, pool->size, pool->virt, pool->phys,
++ &pool->attrs);
++#endif
++ gcmkFOOTER_ARG(KERN_INFO "Failed to register gpu driver: %d\n", ret);
++ return ret;
++}
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)
++static int gpu_remove(struct platform_device *pdev)
++#else
++static int __devexit gpu_remove(struct platform_device *pdev)
++#endif
++{
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
++ gckGALDEVICE device = platform_get_drvdata(pdev);
++ struct contiguous_mem_pool *pool = device->pool;
++#endif
++ gcmkHEADER();
++#if gcdENABLE_FSCALE_VAL_ADJUST
++ if(galDevice->kernels[gcvCORE_MAJOR])
++ UNREG_THERMAL_NOTIFIER(&thermal_hot_pm_notifier);
++#endif
++ drv_exit();
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
++ dma_free_attrs(&pdev->dev, pool->size, pool->virt, pool->phys,
++ &pool->attrs);
++#endif
++ gcmkFOOTER_NO();
++ return 0;
++}
++
++static int gpu_suspend(struct platform_device *dev, pm_message_t state)
++{
++ gceSTATUS status;
++ gckGALDEVICE device;
++ gctINT i;
++
++ device = platform_get_drvdata(dev);
++
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ if (device->kernels[i] != gcvNULL)
++ {
++ /* Store states. */
++#if gcdENABLE_VG
++ if (i == gcvCORE_VG)
++ {
++ status = gckVGHARDWARE_QueryPowerManagementState(device->kernels[i]->vg->hardware, &device->statesStored[i]);
++ }
++ else
++#endif
++ {
++ status = gckHARDWARE_QueryPowerManagementState(device->kernels[i]->hardware, &device->statesStored[i]);
++ }
++
++ if (gcmIS_ERROR(status))
++ {
++ return -1;
++ }
++
++#if gcdENABLE_VG
++ if (i == gcvCORE_VG)
++ {
++ status = gckVGHARDWARE_SetPowerManagementState(device->kernels[i]->vg->hardware, gcvPOWER_OFF);
++ }
++ else
++#endif
++ {
++ status = gckHARDWARE_SetPowerManagementState(device->kernels[i]->hardware, gcvPOWER_OFF);
++ }
++ if (gcmIS_ERROR(status))
++ {
++ return -1;
++ }
++
++ }
++ }
++
++ return 0;
++}
++
++static int gpu_resume(struct platform_device *dev)
++{
++ gceSTATUS status;
++ gckGALDEVICE device;
++ gctINT i;
++ gceCHIPPOWERSTATE statesStored;
++
++ device = platform_get_drvdata(dev);
++
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ if (device->kernels[i] != gcvNULL)
++ {
++#if gcdENABLE_VG
++ if (i == gcvCORE_VG)
++ {
++ status = gckVGHARDWARE_SetPowerManagementState(device->kernels[i]->vg->hardware, gcvPOWER_ON);
++ }
++ else
++#endif
++ {
++ status = gckHARDWARE_SetPowerManagementState(device->kernels[i]->hardware, gcvPOWER_ON);
++ }
++
++ if (gcmIS_ERROR(status))
++ {
++ return -1;
++ }
++
++ /* Convert global state to crossponding internal state. */
++ switch(device->statesStored[i])
++ {
++ case gcvPOWER_OFF:
++ statesStored = gcvPOWER_OFF_BROADCAST;
++ break;
++ case gcvPOWER_IDLE:
++ statesStored = gcvPOWER_IDLE_BROADCAST;
++ break;
++ case gcvPOWER_SUSPEND:
++ statesStored = gcvPOWER_SUSPEND_BROADCAST;
++ break;
++ case gcvPOWER_ON:
++ statesStored = gcvPOWER_ON_AUTO;
++ break;
++ default:
++ statesStored = device->statesStored[i];
++ break;
++ }
++
++ /* Restore states. */
++#if gcdENABLE_VG
++ if (i == gcvCORE_VG)
++ {
++ status = gckVGHARDWARE_SetPowerManagementState(device->kernels[i]->vg->hardware, statesStored);
++ }
++ else
++#endif
++ {
++ status = gckHARDWARE_SetPowerManagementState(device->kernels[i]->hardware, statesStored);
++ }
++
++ if (gcmIS_ERROR(status))
++ {
++ return -1;
++ }
++ }
++ }
++
++ return 0;
++}
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,5,0)
++static const struct of_device_id mxs_gpu_dt_ids[] = {
++ { .compatible = "fsl,imx6q-gpu", },
++ {/* sentinel */}
++};
++MODULE_DEVICE_TABLE(of, mxs_gpu_dt_ids);
++
++#ifdef CONFIG_PM
++static int gpu_runtime_suspend(struct device *dev)
++{
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 7)
++ release_bus_freq(BUS_FREQ_HIGH);
++#endif
++ return 0;
++}
++
++static int gpu_runtime_resume(struct device *dev)
++{
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 7)
++ request_bus_freq(BUS_FREQ_HIGH);
++#endif
++ return 0;
++}
++
++static int gpu_system_suspend(struct device *dev)
++{
++ pm_message_t state={0};
++ return gpu_suspend(to_platform_device(dev), state);
++}
++
++static int gpu_system_resume(struct device *dev)
++{
++ return gpu_resume(to_platform_device(dev));
++}
++
++static const struct dev_pm_ops gpu_pm_ops = {
++ SET_RUNTIME_PM_OPS(gpu_runtime_suspend, gpu_runtime_resume, NULL)
++ SET_SYSTEM_SLEEP_PM_OPS(gpu_system_suspend, gpu_system_resume)
++};
++#endif
++#endif
++
++static struct platform_driver gpu_driver = {
++ .probe = gpu_probe,
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)
++ .remove = gpu_remove,
++#else
++ .remove = __devexit_p(gpu_remove),
++#endif
++
++ .suspend = gpu_suspend,
++ .resume = gpu_resume,
++
++ .driver = {
++ .name = DEVICE_NAME,
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,5,0)
++ .of_match_table = mxs_gpu_dt_ids,
++#if CONFIG_PM
++ .pm = &gpu_pm_ops,
++#endif
++#endif
++ }
++};
++
++#if 0 /*CONFIG_DOVE_GPU*/
++static struct resource gpu_resources[] = {
++ {
++ .name = "gpu_irq",
++ .flags = IORESOURCE_IRQ,
++ },
++ {
++ .name = "gpu_base",
++ .flags = IORESOURCE_MEM,
++ },
++ {
++ .name = "gpu_mem",
++ .flags = IORESOURCE_MEM,
++ },
++};
++
++static struct platform_device * gpu_device;
++#endif
++
++static int __init gpu_init(void)
++{
++ int ret = 0;
++
++#if 0 /*ndef CONFIG_DOVE_GPU*/
++ gpu_resources[0].start = gpu_resources[0].end = irqLine;
++
++ gpu_resources[1].start = registerMemBase;
++ gpu_resources[1].end = registerMemBase + registerMemSize - 1;
++
++ gpu_resources[2].start = contiguousBase;
++ gpu_resources[2].end = contiguousBase + contiguousSize - 1;
++
++ /* Allocate device */
++ gpu_device = platform_device_alloc(DEVICE_NAME, -1);
++ if (!gpu_device)
++ {
++ printk(KERN_ERR "galcore: platform_device_alloc failed.\n");
++ ret = -ENOMEM;
++ goto out;
++ }
++
++ /* Insert resource */
++ ret = platform_device_add_resources(gpu_device, gpu_resources, 3);
++ if (ret)
++ {
++ printk(KERN_ERR "galcore: platform_device_add_resources failed.\n");
++ goto put_dev;
++ }
++
++ /* Add device */
++ ret = platform_device_add(gpu_device);
++ if (ret)
++ {
++ printk(KERN_ERR "galcore: platform_device_add failed.\n");
++ goto put_dev;
++ }
++#endif
++
++ ret = platform_driver_register(&gpu_driver);
++ if (!ret)
++ {
++ goto out;
++ }
++
++#if 0 /*ndef CONFIG_DOVE_GPU*/
++ platform_device_del(gpu_device);
++put_dev:
++ platform_device_put(gpu_device);
++#endif
++
++out:
++ return ret;
++}
++
++static void __exit gpu_exit(void)
++{
++ platform_driver_unregister(&gpu_driver);
++#if 0 /*ndef CONFIG_DOVE_GPU*/
++ platform_device_unregister(gpu_device);
++#endif
++}
++
++module_init(gpu_init);
++module_exit(gpu_exit);
++
++#endif
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_iommu.c linux-xbian-imx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_iommu.c
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_iommu.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_iommu.c 2015-07-27 23:13:06.222780123 +0200
+@@ -0,0 +1,216 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_linux.h"
++#include "gc_hal_kernel_device.h"
++
++#include <linux/iommu.h>
++#include <linux/platform_device.h>
++
++#define _GC_OBJ_ZONE gcvZONE_OS
++
++typedef struct _gcsIOMMU
++{
++ struct iommu_domain * domain;
++ struct device * device;
++}
++gcsIOMMU;
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,5,0)
++static int
++_IOMMU_Fault_Handler(
++ struct iommu_domain * Domain,
++ struct device * Dev,
++ unsigned long DomainAddress,
++ int flags,
++ void * args
++ )
++#else
++static int
++_IOMMU_Fault_Handler(
++ struct iommu_domain * Domain,
++ struct device * Dev,
++ unsigned long DomainAddress,
++ int flags
++ )
++#endif
++{
++ return 0;
++}
++
++static int
++_FlatMapping(
++ IN gckIOMMU Iommu
++ )
++{
++ gceSTATUS status;
++ gctUINT32 physical;
++
++ for (physical = 0; physical < 0x80000000; physical += PAGE_SIZE)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "Map %x => %x bytes = %d",
++ physical, physical, PAGE_SIZE
++ );
++
++ gcmkONERROR(gckIOMMU_Map(Iommu, physical, physical, PAGE_SIZE));
++ }
++
++ return gcvSTATUS_OK;
++
++OnError:
++ return status;
++}
++
++void
++gckIOMMU_Destory(
++ IN gckOS Os,
++ IN gckIOMMU Iommu
++ )
++{
++ gcmkHEADER();
++
++ if (Iommu->domain && Iommu->device)
++ {
++ iommu_attach_device(Iommu->domain, Iommu->device);
++ }
++
++ if (Iommu->domain)
++ {
++ iommu_domain_free(Iommu->domain);
++ }
++
++ if (Iommu)
++ {
++ gcmkOS_SAFE_FREE(Os, Iommu);
++ }
++
++ gcmkFOOTER_NO();
++}
++
++gceSTATUS
++gckIOMMU_Construct(
++ IN gckOS Os,
++ OUT gckIOMMU * Iommu
++ )
++{
++ gceSTATUS status;
++ gckIOMMU iommu = gcvNULL;
++ struct device *dev;
++ int ret;
++
++ gcmkHEADER();
++
++ dev = &Os->device->platform->device->dev;
++
++ gcmkONERROR(gckOS_Allocate(Os, gcmSIZEOF(gcsIOMMU), (gctPOINTER *)&iommu));
++
++ gckOS_ZeroMemory(iommu, gcmSIZEOF(gcsIOMMU));
++
++ iommu->domain = iommu_domain_alloc(&platform_bus_type);
++
++ if (!iommu->domain)
++ {
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_OS, "iommu_domain_alloc() fail");
++
++ gcmkONERROR(gcvSTATUS_NOT_SUPPORTED);
++ }
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,5,0)
++ iommu_set_fault_handler(iommu->domain, _IOMMU_Fault_Handler, dev);
++#else
++ iommu_set_fault_handler(iommu->domain, _IOMMU_Fault_Handler);
++#endif
++
++ ret = iommu_attach_device(iommu->domain, dev);
++
++ if (ret)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS, "iommu_attach_device() fail %d", ret);
++
++ gcmkONERROR(gcvSTATUS_NOT_SUPPORTED);
++ }
++
++ iommu->device = dev;
++
++ _FlatMapping(iommu);
++
++ *Iommu = iommu;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++
++ gckIOMMU_Destory(Os, iommu);
++
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckIOMMU_Map(
++ IN gckIOMMU Iommu,
++ IN gctUINT32 DomainAddress,
++ IN gctUINT32 Physical,
++ IN gctUINT32 Bytes
++ )
++{
++ gceSTATUS status;
++ int ret;
++
++ gcmkHEADER_ARG("DomainAddress=%#X, Physical=%#X, Bytes=%d",
++ DomainAddress, Physical, Bytes);
++
++ ret = iommu_map(Iommu->domain, DomainAddress, Physical, Bytes, 0);
++
++ if (ret)
++ {
++ gcmkONERROR(gcvSTATUS_NOT_SUPPORTED);
++ }
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++
++ gcmkFOOTER();
++ return status;
++
++}
++
++gceSTATUS
++gckIOMMU_Unmap(
++ IN gckIOMMU Iommu,
++ IN gctUINT32 DomainAddress,
++ IN gctUINT32 Bytes
++ )
++{
++ gcmkHEADER();
++
++ iommu_unmap(Iommu->domain, DomainAddress, Bytes);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_linux.c linux-xbian-imx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_linux.c
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_linux.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_linux.c 2015-07-27 23:13:06.222780123 +0200
+@@ -0,0 +1,481 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_linux.h"
++
++#define _GC_OBJ_ZONE gcvZONE_KERNEL
++
++/******************************************************************************\
++******************************* gckKERNEL API Code ******************************
++\******************************************************************************/
++
++/*******************************************************************************
++**
++** gckKERNEL_QueryVideoMemory
++**
++** Query the amount of video memory.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** OUTPUT:
++**
++** gcsHAL_INTERFACE * Interface
++** Pointer to an gcsHAL_INTERFACE structure that will be filled in with
++** the memory information.
++*/
++gceSTATUS
++gckKERNEL_QueryVideoMemory(
++ IN gckKERNEL Kernel,
++ OUT gcsHAL_INTERFACE * Interface
++ )
++{
++ gckGALDEVICE device;
++
++ gcmkHEADER_ARG("Kernel=%p", Kernel);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(Interface != NULL);
++
++ /* Extract the pointer to the gckGALDEVICE class. */
++ device = (gckGALDEVICE) Kernel->context;
++
++ /* Get internal memory size and physical address. */
++ Interface->u.QueryVideoMemory.internalSize = device->internalSize;
++ Interface->u.QueryVideoMemory.internalPhysical = device->internalPhysicalName;
++
++ /* Get external memory size and physical address. */
++ Interface->u.QueryVideoMemory.externalSize = device->externalSize;
++ Interface->u.QueryVideoMemory.externalPhysical = device->externalPhysicalName;
++
++ /* Get contiguous memory size and physical address. */
++ Interface->u.QueryVideoMemory.contiguousSize = device->contiguousSize;
++ Interface->u.QueryVideoMemory.contiguousPhysical = device->contiguousPhysicalName;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_GetVideoMemoryPool
++**
++** Get the gckVIDMEM object belonging to the specified pool.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gcePOOL Pool
++** Pool to query gckVIDMEM object for.
++**
++** OUTPUT:
++**
++** gckVIDMEM * VideoMemory
++** Pointer to a variable that will hold the pointer to the gckVIDMEM
++** object belonging to the requested pool.
++*/
++gceSTATUS
++gckKERNEL_GetVideoMemoryPool(
++ IN gckKERNEL Kernel,
++ IN gcePOOL Pool,
++ OUT gckVIDMEM * VideoMemory
++ )
++{
++ gckGALDEVICE device;
++ gckVIDMEM videoMemory;
++
++ gcmkHEADER_ARG("Kernel=%p Pool=%d", Kernel, Pool);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(VideoMemory != NULL);
++
++ /* Extract the pointer to the gckGALDEVICE class. */
++ device = (gckGALDEVICE) Kernel->context;
++
++ /* Dispatch on pool. */
++ switch (Pool)
++ {
++ case gcvPOOL_LOCAL_INTERNAL:
++ /* Internal memory. */
++ videoMemory = device->internalVidMem;
++ break;
++
++ case gcvPOOL_LOCAL_EXTERNAL:
++ /* External memory. */
++ videoMemory = device->externalVidMem;
++ break;
++
++ case gcvPOOL_SYSTEM:
++ /* System memory. */
++ videoMemory = device->contiguousVidMem;
++ break;
++
++ default:
++ /* Unknown pool. */
++ videoMemory = NULL;
++ }
++
++ /* Return pointer to the gckVIDMEM object. */
++ *VideoMemory = videoMemory;
++
++ /* Return status. */
++ gcmkFOOTER_ARG("*VideoMemory=%p", *VideoMemory);
++ return (videoMemory == NULL) ? gcvSTATUS_OUT_OF_MEMORY : gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_MapMemory
++**
++** Map video memory into the current process space.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gctPHYS_ADDR Physical
++** Physical address of video memory to map.
++**
++** gctSIZE_T Bytes
++** Number of bytes to map.
++**
++** OUTPUT:
++**
++** gctPOINTER * Logical
++** Pointer to a variable that will hold the base address of the mapped
++** memory region.
++*/
++gceSTATUS
++gckKERNEL_MapMemory(
++ IN gckKERNEL Kernel,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Logical
++ )
++{
++ gckKERNEL kernel = Kernel;
++ gctPHYS_ADDR physical = gcmNAME_TO_PTR(Physical);
++
++ return gckOS_MapMemory(Kernel->os, physical, Bytes, Logical);
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_UnmapMemory
++**
++** Unmap video memory from the current process space.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gctPHYS_ADDR Physical
++** Physical address of video memory to map.
++**
++** gctSIZE_T Bytes
++** Number of bytes to map.
++**
++** gctPOINTER Logical
++** Base address of the mapped memory region.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckKERNEL_UnmapMemory(
++ IN gckKERNEL Kernel,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ IN gctPOINTER Logical
++ )
++{
++ gckKERNEL kernel = Kernel;
++ gctPHYS_ADDR physical = gcmNAME_TO_PTR(Physical);
++
++ return gckOS_UnmapMemory(Kernel->os, physical, Bytes, Logical);
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_MapVideoMemory
++**
++** Get the logical address for a hardware specific memory address for the
++** current process.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gctBOOL InUserSpace
++** gcvTRUE to map the memory into the user space.
++**
++** gctUINT32 Address
++** Hardware specific memory address.
++**
++** OUTPUT:
++**
++** gctPOINTER * Logical
++** Pointer to a variable that will hold the logical address of the
++** specified memory address.
++*/
++gceSTATUS
++gckKERNEL_MapVideoMemoryEx(
++ IN gckKERNEL Kernel,
++ IN gceCORE Core,
++ IN gctBOOL InUserSpace,
++ IN gctUINT32 Address,
++ OUT gctPOINTER * Logical
++ )
++{
++ gckGALDEVICE device;
++ PLINUX_MDL mdl;
++ PLINUX_MDL_MAP mdlMap;
++ gcePOOL pool;
++ gctUINT32 offset, base;
++ gceSTATUS status;
++ gctPOINTER logical;
++
++ gcmkHEADER_ARG("Kernel=%p InUserSpace=%d Address=%08x",
++ Kernel, InUserSpace, Address);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(Logical != NULL);
++
++ /* Extract the pointer to the gckGALDEVICE class. */
++ device = (gckGALDEVICE) Kernel->context;
++
++#if gcdENABLE_VG
++ if (Core == gcvCORE_VG)
++ {
++ /* Split the memory address into a pool type and offset. */
++ gcmkONERROR(
++ gckVGHARDWARE_SplitMemory(Kernel->vg->hardware, Address, &pool, &offset));
++ }
++ else
++#endif
++ {
++ /* Split the memory address into a pool type and offset. */
++ gcmkONERROR(
++ gckHARDWARE_SplitMemory(Kernel->hardware, Address, &pool, &offset));
++ }
++
++ /* Dispatch on pool. */
++ switch (pool)
++ {
++ case gcvPOOL_LOCAL_INTERNAL:
++ /* Internal memory. */
++ logical = device->internalLogical;
++ break;
++
++ case gcvPOOL_LOCAL_EXTERNAL:
++ /* External memory. */
++ logical = device->externalLogical;
++ break;
++
++ case gcvPOOL_SYSTEM:
++ /* System memory. */
++ if (device->contiguousMapped)
++ {
++ logical = device->contiguousBase;
++ }
++ else
++ {
++ gctINT processID;
++ gckOS_GetProcessID(&processID);
++
++ mdl = (PLINUX_MDL) device->contiguousPhysical;
++
++ mdlMap = FindMdlMap(mdl, processID);
++ gcmkASSERT(mdlMap);
++
++ logical = (gctPOINTER) mdlMap->vmaAddr;
++ }
++#if gcdENABLE_VG
++ if (Core == gcvCORE_VG)
++ {
++ gcmkVERIFY_OK(
++ gckVGHARDWARE_SplitMemory(Kernel->vg->hardware,
++ device->contiguousVidMem->baseAddress,
++ &pool,
++ &base));
++ }
++ else
++#endif
++ {
++ gctUINT32 baseAddress = 0;
++
++ if (Kernel->hardware->mmuVersion == 0)
++ {
++ gcmkONERROR(gckOS_GetBaseAddress(Kernel->os, &baseAddress));
++ }
++
++ gcmkVERIFY_OK(
++ gckHARDWARE_SplitMemory(Kernel->hardware,
++ device->contiguousVidMem->baseAddress - baseAddress,
++ &pool,
++ &base));
++ }
++ offset -= base;
++ break;
++
++ default:
++ /* Invalid memory pool. */
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ /* Build logical address of specified address. */
++ *Logical = (gctPOINTER) ((gctUINT8_PTR) logical + offset);
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Logical=%p", *Logical);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Retunn the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_MapVideoMemory
++**
++** Get the logical address for a hardware specific memory address for the
++** current process.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gctBOOL InUserSpace
++** gcvTRUE to map the memory into the user space.
++**
++** gctUINT32 Address
++** Hardware specific memory address.
++**
++** OUTPUT:
++**
++** gctPOINTER * Logical
++** Pointer to a variable that will hold the logical address of the
++** specified memory address.
++*/
++gceSTATUS
++gckKERNEL_MapVideoMemory(
++ IN gckKERNEL Kernel,
++ IN gctBOOL InUserSpace,
++ IN gctUINT32 Address,
++ OUT gctPOINTER * Logical
++ )
++{
++ return gckKERNEL_MapVideoMemoryEx(Kernel, gcvCORE_MAJOR, InUserSpace, Address, Logical);
++}
++/*******************************************************************************
++**
++** gckKERNEL_Notify
++**
++** This function iscalled by clients to notify the gckKERNRL object of an event.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gceNOTIFY Notification
++** Notification event.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckKERNEL_Notify(
++ IN gckKERNEL Kernel,
++ IN gceNOTIFY Notification,
++ IN gctBOOL Data
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Kernel=%p Notification=%d Data=%d",
++ Kernel, Notification, Data);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++
++ /* Dispatch on notifcation. */
++ switch (Notification)
++ {
++ case gcvNOTIFY_INTERRUPT:
++ /* Process the interrupt. */
++#if COMMAND_PROCESSOR_VERSION > 1
++ status = gckINTERRUPT_Notify(Kernel->interrupt, Data);
++#else
++ status = gckHARDWARE_Interrupt(Kernel->hardware, Data);
++#endif
++ break;
++
++ default:
++ status = gcvSTATUS_OK;
++ break;
++ }
++
++ /* Success. */
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckKERNEL_QuerySettings(
++ IN gckKERNEL Kernel,
++ OUT gcsKERNEL_SETTINGS * Settings
++ )
++{
++ gckGALDEVICE device;
++
++ gcmkHEADER_ARG("Kernel=%p", Kernel);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(Settings != gcvNULL);
++
++ /* Extract the pointer to the gckGALDEVICE class. */
++ device = (gckGALDEVICE) Kernel->context;
++
++ /* Fill in signal. */
++ Settings->signal = device->signal;
++
++ /* Success. */
++ gcmkFOOTER_ARG("Settings->signal=%d", Settings->signal);
++ return gcvSTATUS_OK;
++}
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_linux.h linux-xbian-imx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_linux.h
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_linux.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_linux.h 2015-07-27 23:13:06.222780123 +0200
+@@ -0,0 +1,94 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_kernel_linux_h_
++#define __gc_hal_kernel_linux_h_
++
++#include <linux/version.h>
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/fs.h>
++#include <linux/mm.h>
++#include <linux/sched.h>
++#include <linux/signal.h>
++#ifdef FLAREON
++# include <asm/arch-realview/dove_gpio_irq.h>
++#endif
++#include <linux/interrupt.h>
++#include <linux/vmalloc.h>
++#include <linux/dma-mapping.h>
++#include <linux/kthread.h>
++
++#ifdef MODVERSIONS
++# include <linux/modversions.h>
++#endif
++#include <asm/io.h>
++#include <asm/uaccess.h>
++
++#if ENABLE_GPU_CLOCK_BY_DRIVER && LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,28)
++#include <linux/clk.h>
++#include <linux/regulator/consumer.h>
++#endif
++
++#define NTSTRSAFE_NO_CCH_FUNCTIONS
++#include "gc_hal.h"
++#include "gc_hal_driver.h"
++#include "gc_hal_kernel.h"
++#include "gc_hal_kernel_device.h"
++#include "gc_hal_kernel_os.h"
++#include "gc_hal_kernel_debugfs.h"
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,31)
++#define FIND_TASK_BY_PID(x) pid_task(find_vpid(x), PIDTYPE_PID)
++#elif LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
++#define FIND_TASK_BY_PID(x) find_task_by_vpid(x)
++#else
++#define FIND_TASK_BY_PID(x) find_task_by_pid(x)
++#endif
++
++#define _WIDE(string) L##string
++#define WIDE(string) _WIDE(string)
++
++#define countof(a) (sizeof(a) / sizeof(a[0]))
++
++#define DRV_NAME "galcore"
++
++#define GetPageCount(size, offset) ((((size) + ((offset) & ~PAGE_CACHE_MASK)) + PAGE_CACHE_SIZE - 1) >> PAGE_CACHE_SHIFT)
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION (3,7,0)
++#define gcdVM_FLAGS (VM_IO | VM_DONTCOPY | VM_DONTEXPAND | VM_DONTDUMP)
++#else
++#define gcdVM_FLAGS (VM_IO | VM_DONTCOPY | VM_DONTEXPAND | VM_RESERVED)
++#endif
++
++static inline gctINT
++GetOrder(
++ IN gctINT numPages
++ )
++{
++ gctINT order = 0;
++
++ while ((1 << order) < numPages) order++;
++
++ return order;
++}
++
++#endif /* __gc_hal_kernel_linux_h_ */
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_math.c linux-xbian-imx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_math.c
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_math.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_math.c 2015-07-27 23:13:06.222780123 +0200
+@@ -0,0 +1,32 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_linux.h"
++
++gctINT
++gckMATH_ModuloInt(
++ IN gctINT X,
++ IN gctINT Y
++ )
++{
++ if(Y ==0) {return 0;}
++ else {return X % Y;}
++}
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_os.c linux-xbian-imx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_os.c
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_os.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_os.c 2015-07-27 23:13:06.226765901 +0200
+@@ -0,0 +1,9078 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_linux.h"
++
++#include <linux/pagemap.h>
++#include <linux/seq_file.h>
++#include <linux/mm.h>
++#include <linux/mman.h>
++#include <linux/sched.h>
++#include <asm/atomic.h>
++#include <linux/dma-mapping.h>
++#include <linux/slab.h>
++#include <linux/idr.h>
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,10,0)
++#include <mach/hardware.h>
++#endif
++#include <linux/workqueue.h>
++#include <linux/idr.h>
++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,23)
++#include <linux/math64.h>
++#endif
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
++#include <linux/reset.h>
++static inline void imx_gpc_power_up_pu(bool flag) {}
++#elif LINUX_VERSION_CODE >= KERNEL_VERSION(3,5,0)
++#include <mach/common.h>
++#endif
++#include <linux/delay.h>
++#include <linux/pm_runtime.h>
++
++
++#if gcdANDROID_NATIVE_FENCE_SYNC
++#include <linux/file.h>
++#include "gc_hal_kernel_sync.h"
++#endif
++
++
++#define _GC_OBJ_ZONE gcvZONE_OS
++
++/*******************************************************************************
++***** Version Signature *******************************************************/
++
++#ifdef ANDROID
++const char * _PLATFORM = "\n\0$PLATFORM$Android$\n";
++#else
++const char * _PLATFORM = "\n\0$PLATFORM$Linux$\n";
++#endif
++
++#define USER_SIGNAL_TABLE_LEN_INIT 64
++#define gcdSUPPRESS_OOM_MESSAGE 1
++
++#define MEMORY_LOCK(os) \
++ gcmkVERIFY_OK(gckOS_AcquireMutex( \
++ (os), \
++ (os)->memoryLock, \
++ gcvINFINITE))
++
++#define MEMORY_UNLOCK(os) \
++ gcmkVERIFY_OK(gckOS_ReleaseMutex((os), (os)->memoryLock))
++
++#define MEMORY_MAP_LOCK(os) \
++ gcmkVERIFY_OK(gckOS_AcquireMutex( \
++ (os), \
++ (os)->memoryMapLock, \
++ gcvINFINITE))
++
++#define MEMORY_MAP_UNLOCK(os) \
++ gcmkVERIFY_OK(gckOS_ReleaseMutex((os), (os)->memoryMapLock))
++
++/* Protection bit when mapping memroy to user sapce */
++#define gcmkPAGED_MEMROY_PROT(x) pgprot_writecombine(x)
++
++#if gcdNONPAGED_MEMORY_BUFFERABLE
++#define gcmkIOREMAP ioremap_wc
++#define gcmkNONPAGED_MEMROY_PROT(x) pgprot_writecombine(x)
++#elif !gcdNONPAGED_MEMORY_CACHEABLE
++#define gcmkIOREMAP ioremap_nocache
++#define gcmkNONPAGED_MEMROY_PROT(x) pgprot_noncached(x)
++#endif
++
++#if gcdSUPPRESS_OOM_MESSAGE
++#define gcdNOWARN __GFP_NOWARN
++#else
++#define gcdNOWARN 0
++#endif
++
++#define gcdINFINITE_TIMEOUT (60 * 1000)
++#define gcdDETECT_TIMEOUT 0
++#define gcdDETECT_DMA_ADDRESS 1
++#define gcdDETECT_DMA_STATE 1
++
++#define gcdUSE_NON_PAGED_MEMORY_CACHE 10
++
++/******************************************************************************\
++********************************** Structures **********************************
++\******************************************************************************/
++#if gcdUSE_NON_PAGED_MEMORY_CACHE
++typedef struct _gcsNonPagedMemoryCache
++{
++#ifndef NO_DMA_COHERENT
++ gctINT size;
++ gctSTRING addr;
++ dma_addr_t dmaHandle;
++#else
++ long order;
++ struct page * page;
++#endif
++
++ struct _gcsNonPagedMemoryCache * prev;
++ struct _gcsNonPagedMemoryCache * next;
++}
++gcsNonPagedMemoryCache;
++#endif /* gcdUSE_NON_PAGED_MEMORY_CACHE */
++
++typedef struct _gcsUSER_MAPPING * gcsUSER_MAPPING_PTR;
++typedef struct _gcsUSER_MAPPING
++{
++ /* Pointer to next mapping structure. */
++ gcsUSER_MAPPING_PTR next;
++
++ /* Physical address of this mapping. */
++ gctUINT32 physical;
++
++ /* Logical address of this mapping. */
++ gctPOINTER logical;
++
++ /* Number of bytes of this mapping. */
++ gctSIZE_T bytes;
++
++ /* Starting address of this mapping. */
++ gctINT8_PTR start;
++
++ /* Ending address of this mapping. */
++ gctINT8_PTR end;
++}
++gcsUSER_MAPPING;
++
++typedef struct _gcsINTEGER_DB * gcsINTEGER_DB_PTR;
++typedef struct _gcsINTEGER_DB
++{
++ struct idr idr;
++ spinlock_t lock;
++ gctINT curr;
++}
++gcsINTEGER_DB;
++
++struct _gckOS
++{
++ /* Object. */
++ gcsOBJECT object;
++
++ /* Heap. */
++ gckHEAP heap;
++
++ /* Pointer to device */
++ gckGALDEVICE device;
++
++ /* Memory management */
++ gctPOINTER memoryLock;
++ gctPOINTER memoryMapLock;
++
++ struct _LINUX_MDL *mdlHead;
++ struct _LINUX_MDL *mdlTail;
++
++ /* Kernel process ID. */
++ gctUINT32 kernelProcessID;
++
++ /* Signal management. */
++
++ /* Lock. */
++ gctPOINTER signalMutex;
++
++ /* signal id database. */
++ gcsINTEGER_DB signalDB;
++
++#if gcdANDROID_NATIVE_FENCE_SYNC
++ /* Lock. */
++ gctPOINTER syncPointMutex;
++
++ /* sync point id database. */
++ gcsINTEGER_DB syncPointDB;
++#endif
++
++ gcsUSER_MAPPING_PTR userMap;
++ gctPOINTER debugLock;
++
++#if gcdUSE_NON_PAGED_MEMORY_CACHE
++ gctUINT cacheSize;
++ gcsNonPagedMemoryCache * cacheHead;
++ gcsNonPagedMemoryCache * cacheTail;
++#endif
++
++ /* workqueue for os timer. */
++ struct workqueue_struct * workqueue;
++
++ int gpu_clk_on[3];
++ struct mutex gpu_clk_mutex;
++
++ gctPOINTER vidmemMutex;
++};
++
++typedef struct _gcsSIGNAL * gcsSIGNAL_PTR;
++typedef struct _gcsSIGNAL
++{
++ /* Kernel sync primitive. */
++ struct completion obj;
++
++ /* Manual reset flag. */
++ gctBOOL manualReset;
++
++ /* The reference counter. */
++ atomic_t ref;
++
++ /* The owner of the signal. */
++ gctHANDLE process;
++
++ gckHARDWARE hardware;
++
++ /* ID. */
++ gctUINT32 id;
++}
++gcsSIGNAL;
++
++#if gcdANDROID_NATIVE_FENCE_SYNC
++typedef struct _gcsSYNC_POINT * gcsSYNC_POINT_PTR;
++typedef struct _gcsSYNC_POINT
++{
++ /* The reference counter. */
++ atomic_t ref;
++
++ /* State. */
++ atomic_t state;
++
++ /* timeline. */
++ struct sync_timeline * timeline;
++
++ /* ID. */
++ gctUINT32 id;
++}
++gcsSYNC_POINT;
++#endif
++
++typedef struct _gcsPageInfo * gcsPageInfo_PTR;
++typedef struct _gcsPageInfo
++{
++ struct page **pages;
++ gctUINT32_PTR pageTable;
++}
++gcsPageInfo;
++
++typedef struct _gcsOSTIMER * gcsOSTIMER_PTR;
++typedef struct _gcsOSTIMER
++{
++ struct delayed_work work;
++ gctTIMERFUNCTION function;
++ gctPOINTER data;
++} gcsOSTIMER;
++
++/******************************************************************************\
++******************************* Private Functions ******************************
++\******************************************************************************/
++
++static gctINT
++_GetProcessID(
++ void
++ )
++{
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)
++ return task_tgid_vnr(current);
++#else
++ return current->tgid;
++#endif
++}
++
++static gctINT
++_GetThreadID(
++ void
++ )
++{
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)
++ return task_pid_vnr(current);
++#else
++ return current->pid;
++#endif
++}
++
++static PLINUX_MDL
++_CreateMdl(
++ IN gctINT ProcessID
++ )
++{
++ PLINUX_MDL mdl;
++
++ gcmkHEADER_ARG("ProcessID=%d", ProcessID);
++
++ mdl = (PLINUX_MDL)kzalloc(sizeof(struct _LINUX_MDL), GFP_KERNEL | gcdNOWARN);
++ if (mdl == gcvNULL)
++ {
++ gcmkFOOTER_NO();
++ return gcvNULL;
++ }
++
++ mdl->pid = ProcessID;
++ mdl->maps = gcvNULL;
++ mdl->prev = gcvNULL;
++ mdl->next = gcvNULL;
++
++ gcmkFOOTER_ARG("0x%X", mdl);
++ return mdl;
++}
++
++static gceSTATUS
++_DestroyMdlMap(
++ IN PLINUX_MDL Mdl,
++ IN PLINUX_MDL_MAP MdlMap
++ );
++
++static gceSTATUS
++_DestroyMdl(
++ IN PLINUX_MDL Mdl
++ )
++{
++ PLINUX_MDL_MAP mdlMap, next;
++
++ gcmkHEADER_ARG("Mdl=0x%X", Mdl);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_ARGUMENT(Mdl != gcvNULL);
++
++ mdlMap = Mdl->maps;
++
++ while (mdlMap != gcvNULL)
++ {
++ next = mdlMap->next;
++
++ gcmkVERIFY_OK(_DestroyMdlMap(Mdl, mdlMap));
++
++ mdlMap = next;
++ }
++
++ kfree(Mdl);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++static PLINUX_MDL_MAP
++_CreateMdlMap(
++ IN PLINUX_MDL Mdl,
++ IN gctINT ProcessID
++ )
++{
++ PLINUX_MDL_MAP mdlMap;
++
++ gcmkHEADER_ARG("Mdl=0x%X ProcessID=%d", Mdl, ProcessID);
++
++ mdlMap = (PLINUX_MDL_MAP)kmalloc(sizeof(struct _LINUX_MDL_MAP), GFP_KERNEL | gcdNOWARN);
++ if (mdlMap == gcvNULL)
++ {
++ gcmkFOOTER_NO();
++ return gcvNULL;
++ }
++
++ mdlMap->pid = ProcessID;
++ mdlMap->vmaAddr = gcvNULL;
++ mdlMap->vma = gcvNULL;
++ mdlMap->count = 0;
++
++ mdlMap->next = Mdl->maps;
++ Mdl->maps = mdlMap;
++
++ gcmkFOOTER_ARG("0x%X", mdlMap);
++ return mdlMap;
++}
++
++static gceSTATUS
++_DestroyMdlMap(
++ IN PLINUX_MDL Mdl,
++ IN PLINUX_MDL_MAP MdlMap
++ )
++{
++ PLINUX_MDL_MAP prevMdlMap;
++
++ gcmkHEADER_ARG("Mdl=0x%X MdlMap=0x%X", Mdl, MdlMap);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_ARGUMENT(MdlMap != gcvNULL);
++ gcmkASSERT(Mdl->maps != gcvNULL);
++
++ if (Mdl->maps == MdlMap)
++ {
++ Mdl->maps = MdlMap->next;
++ }
++ else
++ {
++ prevMdlMap = Mdl->maps;
++
++ while (prevMdlMap->next != MdlMap)
++ {
++ prevMdlMap = prevMdlMap->next;
++
++ gcmkASSERT(prevMdlMap != gcvNULL);
++ }
++
++ prevMdlMap->next = MdlMap->next;
++ }
++
++ kfree(MdlMap);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++extern PLINUX_MDL_MAP
++FindMdlMap(
++ IN PLINUX_MDL Mdl,
++ IN gctINT ProcessID
++ )
++{
++ PLINUX_MDL_MAP mdlMap;
++
++ gcmkHEADER_ARG("Mdl=0x%X ProcessID=%d", Mdl, ProcessID);
++ if(Mdl == gcvNULL)
++ {
++ gcmkFOOTER_NO();
++ return gcvNULL;
++ }
++ mdlMap = Mdl->maps;
++
++ while (mdlMap != gcvNULL)
++ {
++ if (mdlMap->pid == ProcessID)
++ {
++ gcmkFOOTER_ARG("0x%X", mdlMap);
++ return mdlMap;
++ }
++
++ mdlMap = mdlMap->next;
++ }
++
++ gcmkFOOTER_NO();
++ return gcvNULL;
++}
++
++void
++OnProcessExit(
++ IN gckOS Os,
++ IN gckKERNEL Kernel
++ )
++{
++}
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25)
++static inline int
++is_vmalloc_addr(
++ void *Addr
++ )
++{
++ unsigned long addr = (unsigned long)Addr;
++
++ return addr >= VMALLOC_START && addr < VMALLOC_END;
++}
++#endif
++
++static void
++_NonContiguousFree(
++ IN struct page ** Pages,
++ IN gctUINT32 NumPages
++ )
++{
++ gctINT i;
++
++ gcmkHEADER_ARG("Pages=0x%X, NumPages=%d", Pages, NumPages);
++
++ gcmkASSERT(Pages != gcvNULL);
++
++ for (i = 0; i < NumPages; i++)
++ {
++ __free_page(Pages[i]);
++ }
++
++ if (is_vmalloc_addr(Pages))
++ {
++ vfree(Pages);
++ }
++ else
++ {
++ kfree(Pages);
++ }
++
++ gcmkFOOTER_NO();
++}
++
++static struct page **
++_NonContiguousAlloc(
++ IN gctUINT32 NumPages
++ )
++{
++ struct page ** pages;
++ struct page *p;
++ gctINT i, size;
++
++ gcmkHEADER_ARG("NumPages=%lu", NumPages);
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 32)
++ if (NumPages > totalram_pages)
++#else
++ if (NumPages > num_physpages)
++#endif
++ {
++ gcmkFOOTER_NO();
++ return gcvNULL;
++ }
++
++ size = NumPages * sizeof(struct page *);
++
++ pages = kmalloc(size, GFP_KERNEL | gcdNOWARN);
++
++ if (!pages)
++ {
++ pages = vmalloc(size);
++
++ if (!pages)
++ {
++ gcmkFOOTER_NO();
++ return gcvNULL;
++ }
++ }
++
++ for (i = 0; i < NumPages; i++)
++ {
++ p = alloc_page(GFP_KERNEL | __GFP_HIGHMEM | gcdNOWARN);
++
++ if (!p)
++ {
++ _NonContiguousFree(pages, i);
++ gcmkFOOTER_NO();
++ return gcvNULL;
++ }
++
++ pages[i] = p;
++ }
++
++ gcmkFOOTER_ARG("pages=0x%X", pages);
++ return pages;
++}
++
++static inline struct page *
++_NonContiguousToPage(
++ IN struct page ** Pages,
++ IN gctUINT32 Index
++ )
++{
++ gcmkASSERT(Pages != gcvNULL);
++ return Pages[Index];
++}
++
++static inline unsigned long
++_NonContiguousToPfn(
++ IN struct page ** Pages,
++ IN gctUINT32 Index
++ )
++{
++ gcmkASSERT(Pages != gcvNULL);
++ return page_to_pfn(_NonContiguousToPage(Pages, Index));
++}
++
++static inline unsigned long
++_NonContiguousToPhys(
++ IN struct page ** Pages,
++ IN gctUINT32 Index
++ )
++{
++ gcmkASSERT(Pages != gcvNULL);
++ return page_to_phys(_NonContiguousToPage(Pages, Index));
++}
++
++
++#if gcdUSE_NON_PAGED_MEMORY_CACHE
++
++static gctBOOL
++_AddNonPagedMemoryCache(
++ gckOS Os,
++#ifndef NO_DMA_COHERENT
++ gctINT Size,
++ gctSTRING Addr,
++ dma_addr_t DmaHandle
++#else
++ long Order,
++ struct page * Page
++#endif
++ )
++{
++ gcsNonPagedMemoryCache *cache;
++
++ if (Os->cacheSize >= gcdUSE_NON_PAGED_MEMORY_CACHE)
++ {
++ return gcvFALSE;
++ }
++
++ /* Allocate the cache record */
++ cache = (gcsNonPagedMemoryCache *)kmalloc(sizeof(gcsNonPagedMemoryCache), GFP_ATOMIC);
++
++ if (cache == gcvNULL) return gcvFALSE;
++
++#ifndef NO_DMA_COHERENT
++ cache->size = Size;
++ cache->addr = Addr;
++ cache->dmaHandle = DmaHandle;
++#else
++ cache->order = Order;
++ cache->page = Page;
++#endif
++
++ /* Add to list */
++ if (Os->cacheHead == gcvNULL)
++ {
++ cache->prev = gcvNULL;
++ cache->next = gcvNULL;
++ Os->cacheHead =
++ Os->cacheTail = cache;
++ }
++ else
++ {
++ /* Add to the tail. */
++ cache->prev = Os->cacheTail;
++ cache->next = gcvNULL;
++ Os->cacheTail->next = cache;
++ Os->cacheTail = cache;
++ }
++
++ Os->cacheSize++;
++
++ return gcvTRUE;
++}
++
++#ifndef NO_DMA_COHERENT
++static gctSTRING
++_GetNonPagedMemoryCache(
++ gckOS Os,
++ gctINT Size,
++ dma_addr_t * DmaHandle
++ )
++#else
++static struct page *
++_GetNonPagedMemoryCache(
++ gckOS Os,
++ long Order
++ )
++#endif
++{
++ gcsNonPagedMemoryCache *cache;
++#ifndef NO_DMA_COHERENT
++ gctSTRING addr;
++#else
++ struct page * page;
++#endif
++
++ if (Os->cacheHead == gcvNULL) return gcvNULL;
++
++ /* Find the right cache */
++ cache = Os->cacheHead;
++
++ while (cache != gcvNULL)
++ {
++#ifndef NO_DMA_COHERENT
++ if (cache->size == Size) break;
++#else
++ if (cache->order == Order) break;
++#endif
++
++ cache = cache->next;
++ }
++
++ if (cache == gcvNULL) return gcvNULL;
++
++ /* Remove the cache from list */
++ if (cache == Os->cacheHead)
++ {
++ Os->cacheHead = cache->next;
++
++ if (Os->cacheHead == gcvNULL)
++ {
++ Os->cacheTail = gcvNULL;
++ }
++ }
++ else
++ {
++ cache->prev->next = cache->next;
++
++ if (cache == Os->cacheTail)
++ {
++ Os->cacheTail = cache->prev;
++ }
++ else
++ {
++ cache->next->prev = cache->prev;
++ }
++ }
++
++ /* Destroy cache */
++#ifndef NO_DMA_COHERENT
++ addr = cache->addr;
++ *DmaHandle = cache->dmaHandle;
++#else
++ page = cache->page;
++#endif
++
++ kfree(cache);
++
++ Os->cacheSize--;
++
++#ifndef NO_DMA_COHERENT
++ return addr;
++#else
++ return page;
++#endif
++}
++
++static void
++_FreeAllNonPagedMemoryCache(
++ gckOS Os
++ )
++{
++ gcsNonPagedMemoryCache *cache, *nextCache;
++
++ MEMORY_LOCK(Os);
++
++ cache = Os->cacheHead;
++
++ while (cache != gcvNULL)
++ {
++ if (cache != Os->cacheTail)
++ {
++ nextCache = cache->next;
++ }
++ else
++ {
++ nextCache = gcvNULL;
++ }
++
++ /* Remove the cache from list */
++ if (cache == Os->cacheHead)
++ {
++ Os->cacheHead = cache->next;
++
++ if (Os->cacheHead == gcvNULL)
++ {
++ Os->cacheTail = gcvNULL;
++ }
++ }
++ else
++ {
++ cache->prev->next = cache->next;
++
++ if (cache == Os->cacheTail)
++ {
++ Os->cacheTail = cache->prev;
++ }
++ else
++ {
++ cache->next->prev = cache->prev;
++ }
++ }
++
++#ifndef NO_DMA_COHERENT
++ dma_free_coherent(gcvNULL,
++ cache->size,
++ cache->addr,
++ cache->dmaHandle);
++#else
++ free_pages((unsigned long)page_address(cache->page), cache->order);
++#endif
++
++ kfree(cache);
++
++ cache = nextCache;
++ }
++
++ MEMORY_UNLOCK(Os);
++}
++
++#endif /* gcdUSE_NON_PAGED_MEMORY_CACHE */
++
++/*******************************************************************************
++** Integer Id Management.
++*/
++gceSTATUS
++_AllocateIntegerId(
++ IN gcsINTEGER_DB_PTR Database,
++ IN gctPOINTER KernelPointer,
++ OUT gctUINT32 *Id
++ )
++{
++ int result;
++ gctINT next;
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0)
++ idr_preload(GFP_KERNEL | gcdNOWARN);
++
++ spin_lock(&Database->lock);
++
++ next = (Database->curr + 1 <= 0) ? 1 : Database->curr + 1;
++ result = idr_alloc(&Database->idr, KernelPointer, next, 0, GFP_ATOMIC);
++
++ if (!result)
++ {
++ Database->curr = *Id;
++ }
++
++ spin_unlock(&Database->lock);
++
++ idr_preload_end();
++
++ if (result < 0)
++ {
++ return gcvSTATUS_OUT_OF_RESOURCES;
++ }
++
++ *Id = result;
++#else
++again:
++ if (idr_pre_get(&Database->idr, GFP_KERNEL | gcdNOWARN) == 0)
++ {
++ return gcvSTATUS_OUT_OF_MEMORY;
++ }
++
++ spin_lock(&Database->lock);
++
++ next = (Database->curr + 1 <= 0) ? 1 : Database->curr + 1;
++
++ /* Try to get a id greater than current id. */
++ result = idr_get_new_above(&Database->idr, KernelPointer, next, Id);
++
++ if (!result)
++ {
++ Database->curr = *Id;
++ }
++
++ spin_unlock(&Database->lock);
++
++ if (result == -EAGAIN)
++ {
++ goto again;
++ }
++
++ if (result != 0)
++ {
++ return gcvSTATUS_OUT_OF_RESOURCES;
++ }
++#endif
++
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++_QueryIntegerId(
++ IN gcsINTEGER_DB_PTR Database,
++ IN gctUINT32 Id,
++ OUT gctPOINTER * KernelPointer
++ )
++{
++ gctPOINTER pointer;
++
++ spin_lock(&Database->lock);
++
++ pointer = idr_find(&Database->idr, Id);
++
++ spin_unlock(&Database->lock);
++
++ if(pointer)
++ {
++ *KernelPointer = pointer;
++ return gcvSTATUS_OK;
++ }
++ else
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_OS,
++ "%s(%d) Id = %d is not found",
++ __FUNCTION__, __LINE__, Id);
++
++ return gcvSTATUS_NOT_FOUND;
++ }
++}
++
++gceSTATUS
++_DestroyIntegerId(
++ IN gcsINTEGER_DB_PTR Database,
++ IN gctUINT32 Id
++ )
++{
++ spin_lock(&Database->lock);
++
++ idr_remove(&Database->idr, Id);
++
++ spin_unlock(&Database->lock);
++
++ return gcvSTATUS_OK;
++}
++
++static void
++_UnmapUserLogical(
++ IN gctINT Pid,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Size
++)
++{
++ if (unlikely(current->mm == gcvNULL))
++ {
++ /* Do nothing if process is exiting. */
++ return;
++ }
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,5,0)
++ if (vm_munmap((unsigned long)Logical, Size) < 0)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_WARNING, gcvZONE_OS,
++ "%s(%d): vm_munmap failed",
++ __FUNCTION__, __LINE__
++ );
++ }
++#else
++ down_write(&current->mm->mmap_sem);
++ if (do_munmap(current->mm, (unsigned long)Logical, Size) < 0)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_WARNING, gcvZONE_OS,
++ "%s(%d): do_munmap failed",
++ __FUNCTION__, __LINE__
++ );
++ }
++ up_write(&current->mm->mmap_sem);
++#endif
++}
++
++gceSTATUS
++_QueryProcessPageTable(
++ IN gctPOINTER Logical,
++ OUT gctUINT32 * Address
++ )
++{
++ spinlock_t *lock;
++ gctUINTPTR_T logical = (gctUINTPTR_T)Logical;
++ pgd_t *pgd;
++ pud_t *pud;
++ pmd_t *pmd;
++ pte_t *pte;
++
++ if (!current->mm)
++ {
++ return gcvSTATUS_NOT_FOUND;
++ }
++
++ pgd = pgd_offset(current->mm, logical);
++ if (pgd_none(*pgd) || pgd_bad(*pgd))
++ {
++ return gcvSTATUS_NOT_FOUND;
++ }
++
++ pud = pud_offset(pgd, logical);
++ if (pud_none(*pud) || pud_bad(*pud))
++ {
++ return gcvSTATUS_NOT_FOUND;
++ }
++
++ pmd = pmd_offset(pud, logical);
++ if (pmd_none(*pmd) || pmd_bad(*pmd))
++ {
++ return gcvSTATUS_NOT_FOUND;
++ }
++
++ pte = pte_offset_map_lock(current->mm, pmd, logical, &lock);
++ if (!pte)
++ {
++ return gcvSTATUS_NOT_FOUND;
++ }
++
++ if (!pte_present(*pte))
++ {
++ pte_unmap_unlock(pte, lock);
++ return gcvSTATUS_NOT_FOUND;
++ }
++
++ *Address = (pte_pfn(*pte) << PAGE_SHIFT) | (logical & ~PAGE_MASK);
++ pte_unmap_unlock(pte, lock);
++
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_Construct
++**
++** Construct a new gckOS object.
++**
++** INPUT:
++**
++** gctPOINTER Context
++** Pointer to the gckGALDEVICE class.
++**
++** OUTPUT:
++**
++** gckOS * Os
++** Pointer to a variable that will hold the pointer to the gckOS object.
++*/
++gceSTATUS
++gckOS_Construct(
++ IN gctPOINTER Context,
++ OUT gckOS * Os
++ )
++{
++ gckOS os;
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Context=0x%X", Context);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_ARGUMENT(Os != gcvNULL);
++
++ /* Allocate the gckOS object. */
++ os = (gckOS) kmalloc(gcmSIZEOF(struct _gckOS), GFP_KERNEL | gcdNOWARN);
++
++ if (os == gcvNULL)
++ {
++ /* Out of memory. */
++ gcmkFOOTER_ARG("status=%d", gcvSTATUS_OUT_OF_MEMORY);
++ return gcvSTATUS_OUT_OF_MEMORY;
++ }
++
++ /* Zero the memory. */
++ gckOS_ZeroMemory(os, gcmSIZEOF(struct _gckOS));
++
++ /* Initialize the gckOS object. */
++ os->object.type = gcvOBJ_OS;
++
++ /* Set device device. */
++ os->device = Context;
++
++ /* IMPORTANT! No heap yet. */
++ os->heap = gcvNULL;
++
++ /* Initialize the memory lock. */
++ gcmkONERROR(gckOS_CreateMutex(os, &os->memoryLock));
++ gcmkONERROR(gckOS_CreateMutex(os, &os->memoryMapLock));
++
++ /* Create debug lock mutex. */
++ gcmkONERROR(gckOS_CreateMutex(os, &os->debugLock));
++
++
++ os->mdlHead = os->mdlTail = gcvNULL;
++
++ /* Get the kernel process ID. */
++ gcmkONERROR(gckOS_GetProcessID(&os->kernelProcessID));
++
++ /*
++ * Initialize the signal manager.
++ */
++
++ /* Initialize mutex. */
++ gcmkONERROR(gckOS_CreateMutex(os, &os->signalMutex));
++
++ /* Initialize signal id database lock. */
++ spin_lock_init(&os->signalDB.lock);
++
++ /* Initialize signal id database. */
++ idr_init(&os->signalDB.idr);
++
++#if gcdANDROID_NATIVE_FENCE_SYNC
++ /*
++ * Initialize the sync point manager.
++ */
++
++ /* Initialize mutex. */
++ gcmkONERROR(gckOS_CreateMutex(os, &os->syncPointMutex));
++
++ /* Initialize sync point id database lock. */
++ spin_lock_init(&os->syncPointDB.lock);
++
++ /* Initialize sync point id database. */
++ idr_init(&os->syncPointDB.idr);
++#endif
++
++#if gcdUSE_NON_PAGED_MEMORY_CACHE
++ os->cacheSize = 0;
++ os->cacheHead = gcvNULL;
++ os->cacheTail = gcvNULL;
++#endif
++
++ /* Create a workqueue for os timer. */
++ os->workqueue = create_singlethread_workqueue("galcore workqueue");
++
++ if (os->workqueue == gcvNULL)
++ {
++ /* Out of memory. */
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ mutex_init(&os->gpu_clk_mutex);
++
++ /* Construct a video memory mutex. */
++ gcmkONERROR(gckOS_CreateMutex(os, &os->vidmemMutex));
++
++ /* Return pointer to the gckOS object. */
++ *Os = os;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Os=0x%X", *Os);
++ return gcvSTATUS_OK;
++
++OnError:
++
++#if gcdANDROID_NATIVE_FENCE_SYNC
++ if (os->syncPointMutex != gcvNULL)
++ {
++ gcmkVERIFY_OK(
++ gckOS_DeleteMutex(os, os->syncPointMutex));
++ }
++#endif
++
++ if (os->signalMutex != gcvNULL)
++ {
++ gcmkVERIFY_OK(
++ gckOS_DeleteMutex(os, os->signalMutex));
++ }
++
++ if (os->heap != gcvNULL)
++ {
++ gcmkVERIFY_OK(
++ gckHEAP_Destroy(os->heap));
++ }
++
++ if (os->memoryMapLock != gcvNULL)
++ {
++ gcmkVERIFY_OK(
++ gckOS_DeleteMutex(os, os->memoryMapLock));
++ }
++
++ if (os->memoryLock != gcvNULL)
++ {
++ gcmkVERIFY_OK(
++ gckOS_DeleteMutex(os, os->memoryLock));
++ }
++
++ if (os->debugLock != gcvNULL)
++ {
++ gcmkVERIFY_OK(
++ gckOS_DeleteMutex(os, os->debugLock));
++ }
++
++ if (os->workqueue != gcvNULL)
++ {
++ destroy_workqueue(os->workqueue);
++ }
++
++ kfree(os);
++
++ /* Return the error. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_Destroy
++**
++** Destroy an gckOS object.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object that needs to be destroyed.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_Destroy(
++ IN gckOS Os
++ )
++{
++ gckHEAP heap;
++
++ gcmkHEADER_ARG("Os=0x%X", Os);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++
++#if gcdUSE_NON_PAGED_MEMORY_CACHE
++ _FreeAllNonPagedMemoryCache(Os);
++#endif
++
++#if gcdANDROID_NATIVE_FENCE_SYNC
++ /*
++ * Destroy the sync point manager.
++ */
++
++ /* Destroy the mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Os, Os->syncPointMutex));
++#endif
++
++ /*
++ * Destroy the signal manager.
++ */
++
++ /* Destroy the mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Os, Os->signalMutex));
++
++ if (Os->heap != gcvNULL)
++ {
++ /* Mark gckHEAP as gone. */
++ heap = Os->heap;
++ Os->heap = gcvNULL;
++
++ /* Destroy the gckHEAP object. */
++ gcmkVERIFY_OK(gckHEAP_Destroy(heap));
++ }
++
++ /* Destroy the memory lock. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Os, Os->memoryMapLock));
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Os, Os->memoryLock));
++
++ /* Destroy debug lock mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Os, Os->debugLock));
++
++ /* Destroy video memory mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Os, Os->vidmemMutex));
++
++ /* Wait for all works done. */
++ flush_workqueue(Os->workqueue);
++
++ /* Destory work queue. */
++ destroy_workqueue(Os->workqueue);
++
++ /* Flush the debug cache. */
++ gcmkDEBUGFLUSH(~0U);
++
++ /* Mark the gckOS object as unknown. */
++ Os->object.type = gcvOBJ_UNKNOWN;
++
++ /* Free the gckOS object. */
++ kfree(Os);
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++static gctSTRING
++_CreateKernelVirtualMapping(
++ IN PLINUX_MDL Mdl
++ )
++{
++ gctSTRING addr = 0;
++ gctINT numPages = Mdl->numPages;
++
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ if (Mdl->contiguous)
++ {
++ addr = page_address(Mdl->u.contiguousPages);
++ }
++ else
++ {
++ addr = vmap(Mdl->u.nonContiguousPages,
++ numPages,
++ 0,
++ PAGE_KERNEL);
++
++ /* Trigger a page fault. */
++ memset(addr, 0, numPages * PAGE_SIZE);
++ }
++#else
++ struct page ** pages;
++ gctBOOL free = gcvFALSE;
++ gctINT i;
++
++ if (Mdl->contiguous)
++ {
++ pages = kmalloc(sizeof(struct page *) * numPages, GFP_KERNEL | gcdNOWARN);
++
++ if (!pages)
++ {
++ return gcvNULL;
++ }
++
++ for (i = 0; i < numPages; i++)
++ {
++ pages[i] = nth_page(Mdl->u.contiguousPages, i);
++ }
++
++ free = gcvTRUE;
++ }
++ else
++ {
++ pages = Mdl->u.nonContiguousPages;
++ }
++
++ /* ioremap() can't work on system memory since 2.6.38. */
++ addr = vmap(pages, numPages, 0, gcmkNONPAGED_MEMROY_PROT(PAGE_KERNEL));
++
++ /* Trigger a page fault. */
++ memset(addr, 0, numPages * PAGE_SIZE);
++
++ if (free)
++ {
++ kfree(pages);
++ }
++
++#endif
++
++ return addr;
++}
++
++static void
++_DestoryKernelVirtualMapping(
++ IN gctSTRING Addr
++ )
++{
++#if !gcdNONPAGED_MEMORY_CACHEABLE
++ vunmap(Addr);
++#endif
++}
++
++gceSTATUS
++gckOS_CreateKernelVirtualMapping(
++ IN gctPHYS_ADDR Physical,
++ OUT gctSIZE_T * PageCount,
++ OUT gctPOINTER * Logical
++ )
++{
++ *PageCount = ((PLINUX_MDL)Physical)->numPages;
++ *Logical = _CreateKernelVirtualMapping((PLINUX_MDL)Physical);
++
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckOS_DestroyKernelVirtualMapping(
++ IN gctPOINTER Logical
++ )
++{
++ _DestoryKernelVirtualMapping((gctSTRING)Logical);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_Allocate
++**
++** Allocate memory.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctSIZE_T Bytes
++** Number of bytes to allocate.
++**
++** OUTPUT:
++**
++** gctPOINTER * Memory
++** Pointer to a variable that will hold the allocated memory location.
++*/
++gceSTATUS
++gckOS_Allocate(
++ IN gckOS Os,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Memory
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%X Bytes=%lu", Os, Bytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++ gcmkVERIFY_ARGUMENT(Memory != gcvNULL);
++
++ /* Do we have a heap? */
++ if (Os->heap != gcvNULL)
++ {
++ /* Allocate from the heap. */
++ gcmkONERROR(gckHEAP_Allocate(Os->heap, Bytes, Memory));
++ }
++ else
++ {
++ gcmkONERROR(gckOS_AllocateMemory(Os, Bytes, Memory));
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Memory=0x%X", *Memory);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_Free
++**
++** Free allocated memory.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPOINTER Memory
++** Pointer to memory allocation to free.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_Free(
++ IN gckOS Os,
++ IN gctPOINTER Memory
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%X Memory=0x%X", Os, Memory);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Memory != gcvNULL);
++
++ /* Do we have a heap? */
++ if (Os->heap != gcvNULL)
++ {
++ /* Free from the heap. */
++ gcmkONERROR(gckHEAP_Free(Os->heap, Memory));
++ }
++ else
++ {
++ gcmkONERROR(gckOS_FreeMemory(Os, Memory));
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_AllocateMemory
++**
++** Allocate memory wrapper.
++**
++** INPUT:
++**
++** gctSIZE_T Bytes
++** Number of bytes to allocate.
++**
++** OUTPUT:
++**
++** gctPOINTER * Memory
++** Pointer to a variable that will hold the allocated memory location.
++*/
++gceSTATUS
++gckOS_AllocateMemory(
++ IN gckOS Os,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Memory
++ )
++{
++ gctPOINTER memory;
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%X Bytes=%lu", Os, Bytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++ gcmkVERIFY_ARGUMENT(Memory != gcvNULL);
++
++ if (Bytes > PAGE_SIZE)
++ {
++ memory = (gctPOINTER) vmalloc(Bytes);
++ }
++ else
++ {
++ memory = (gctPOINTER) kmalloc(Bytes, GFP_KERNEL | gcdNOWARN);
++ }
++
++ if (memory == gcvNULL)
++ {
++ /* Out of memory. */
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ /* Return pointer to the memory allocation. */
++ *Memory = memory;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Memory=0x%X", *Memory);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_FreeMemory
++**
++** Free allocated memory wrapper.
++**
++** INPUT:
++**
++** gctPOINTER Memory
++** Pointer to memory allocation to free.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_FreeMemory(
++ IN gckOS Os,
++ IN gctPOINTER Memory
++ )
++{
++ gcmkHEADER_ARG("Memory=0x%X", Memory);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_ARGUMENT(Memory != gcvNULL);
++
++ /* Free the memory from the OS pool. */
++ if (is_vmalloc_addr(Memory))
++ {
++ vfree(Memory);
++ }
++ else
++ {
++ kfree(Memory);
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_MapMemory
++**
++** Map physical memory into the current process.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPHYS_ADDR Physical
++** Start of physical address memory.
++**
++** gctSIZE_T Bytes
++** Number of bytes to map.
++**
++** OUTPUT:
++**
++** gctPOINTER * Memory
++** Pointer to a variable that will hold the logical address of the
++** mapped memory.
++*/
++gceSTATUS
++gckOS_MapMemory(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Logical
++ )
++{
++ PLINUX_MDL_MAP mdlMap;
++ PLINUX_MDL mdl = (PLINUX_MDL)Physical;
++
++ gcmkHEADER_ARG("Os=0x%X Physical=0x%X Bytes=%lu", Os, Physical, Bytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Physical != 0);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++
++ MEMORY_LOCK(Os);
++
++ mdlMap = FindMdlMap(mdl, _GetProcessID());
++
++ if (mdlMap == gcvNULL)
++ {
++ mdlMap = _CreateMdlMap(mdl, _GetProcessID());
++
++ if (mdlMap == gcvNULL)
++ {
++ MEMORY_UNLOCK(Os);
++
++ gcmkFOOTER_ARG("status=%d", gcvSTATUS_OUT_OF_MEMORY);
++ return gcvSTATUS_OUT_OF_MEMORY;
++ }
++ }
++
++ if (mdlMap->vmaAddr == gcvNULL)
++ {
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0)
++ mdlMap->vmaAddr = (char *)vm_mmap(gcvNULL,
++ 0L,
++ mdl->numPages * PAGE_SIZE,
++ PROT_READ | PROT_WRITE,
++ MAP_SHARED,
++ 0);
++#else
++ down_write(&current->mm->mmap_sem);
++
++ mdlMap->vmaAddr = (char *)do_mmap_pgoff(gcvNULL,
++ 0L,
++ mdl->numPages * PAGE_SIZE,
++ PROT_READ | PROT_WRITE,
++ MAP_SHARED,
++ 0);
++
++ up_write(&current->mm->mmap_sem);
++#endif
++
++ if (IS_ERR(mdlMap->vmaAddr))
++ {
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): do_mmap_pgoff error",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): mdl->numPages: %d mdl->vmaAddr: 0x%X",
++ __FUNCTION__, __LINE__,
++ mdl->numPages,
++ mdlMap->vmaAddr
++ );
++
++ mdlMap->vmaAddr = gcvNULL;
++
++ MEMORY_UNLOCK(Os);
++
++ gcmkFOOTER_ARG("status=%d", gcvSTATUS_OUT_OF_MEMORY);
++ return gcvSTATUS_OUT_OF_MEMORY;
++ }
++
++ down_write(&current->mm->mmap_sem);
++
++ mdlMap->vma = find_vma(current->mm, (unsigned long)mdlMap->vmaAddr);
++
++ if (!mdlMap->vma)
++ {
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): find_vma error.",
++ __FUNCTION__, __LINE__
++ );
++
++ mdlMap->vmaAddr = gcvNULL;
++
++ up_write(&current->mm->mmap_sem);
++
++ MEMORY_UNLOCK(Os);
++
++ gcmkFOOTER_ARG("status=%d", gcvSTATUS_OUT_OF_RESOURCES);
++ return gcvSTATUS_OUT_OF_RESOURCES;
++ }
++
++#ifndef NO_DMA_COHERENT
++ if (dma_mmap_coherent(gcvNULL,
++ mdlMap->vma,
++ mdl->addr,
++ mdl->dmaHandle,
++ mdl->numPages * PAGE_SIZE) < 0)
++ {
++ up_write(&current->mm->mmap_sem);
++
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): dma_mmap_coherent error.",
++ __FUNCTION__, __LINE__
++ );
++
++ mdlMap->vmaAddr = gcvNULL;
++
++ MEMORY_UNLOCK(Os);
++
++ gcmkFOOTER_ARG("status=%d", gcvSTATUS_OUT_OF_RESOURCES);
++ return gcvSTATUS_OUT_OF_RESOURCES;
++ }
++#else
++#if !gcdPAGED_MEMORY_CACHEABLE
++ mdlMap->vma->vm_page_prot = gcmkPAGED_MEMROY_PROT(mdlMap->vma->vm_page_prot);
++ mdlMap->vma->vm_flags |= gcdVM_FLAGS;
++# endif
++ mdlMap->vma->vm_pgoff = 0;
++
++ if (remap_pfn_range(mdlMap->vma,
++ mdlMap->vma->vm_start,
++ mdl->dmaHandle >> PAGE_SHIFT,
++ mdl->numPages*PAGE_SIZE,
++ mdlMap->vma->vm_page_prot) < 0)
++ {
++ up_write(&current->mm->mmap_sem);
++
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): remap_pfn_range error.",
++ __FUNCTION__, __LINE__
++ );
++
++ mdlMap->vmaAddr = gcvNULL;
++
++ MEMORY_UNLOCK(Os);
++
++ gcmkFOOTER_ARG("status=%d", gcvSTATUS_OUT_OF_RESOURCES);
++ return gcvSTATUS_OUT_OF_RESOURCES;
++ }
++#endif
++
++ up_write(&current->mm->mmap_sem);
++ }
++
++ MEMORY_UNLOCK(Os);
++
++ *Logical = mdlMap->vmaAddr;
++
++ gcmkFOOTER_ARG("*Logical=0x%X", *Logical);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_UnmapMemory
++**
++** Unmap physical memory out of the current process.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPHYS_ADDR Physical
++** Start of physical address memory.
++**
++** gctSIZE_T Bytes
++** Number of bytes to unmap.
++**
++** gctPOINTER Memory
++** Pointer to a previously mapped memory region.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_UnmapMemory(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ IN gctPOINTER Logical
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Physical=0x%X Bytes=%lu Logical=0x%X",
++ Os, Physical, Bytes, Logical);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Physical != 0);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++
++ gckOS_UnmapMemoryEx(Os, Physical, Bytes, Logical, _GetProcessID());
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++
++/*******************************************************************************
++**
++** gckOS_UnmapMemoryEx
++**
++** Unmap physical memory in the specified process.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPHYS_ADDR Physical
++** Start of physical address memory.
++**
++** gctSIZE_T Bytes
++** Number of bytes to unmap.
++**
++** gctPOINTER Memory
++** Pointer to a previously mapped memory region.
++**
++** gctUINT32 PID
++** Pid of the process that opened the device and mapped this memory.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_UnmapMemoryEx(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ IN gctPOINTER Logical,
++ IN gctUINT32 PID
++ )
++{
++ PLINUX_MDL_MAP mdlMap;
++ PLINUX_MDL mdl = (PLINUX_MDL)Physical;
++
++ gcmkHEADER_ARG("Os=0x%X Physical=0x%X Bytes=%lu Logical=0x%X PID=%d",
++ Os, Physical, Bytes, Logical, PID);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Physical != 0);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(PID != 0);
++
++ MEMORY_LOCK(Os);
++
++ if (Logical)
++ {
++ mdlMap = FindMdlMap(mdl, PID);
++
++ if (mdlMap == gcvNULL || mdlMap->vmaAddr == gcvNULL)
++ {
++ MEMORY_UNLOCK(Os);
++
++ gcmkFOOTER_ARG("status=%d", gcvSTATUS_INVALID_ARGUMENT);
++ return gcvSTATUS_INVALID_ARGUMENT;
++ }
++
++ _UnmapUserLogical(PID, mdlMap->vmaAddr, mdl->numPages * PAGE_SIZE);
++
++ gcmkVERIFY_OK(_DestroyMdlMap(mdl, mdlMap));
++ }
++
++ MEMORY_UNLOCK(Os);
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_UnmapUserLogical
++**
++** Unmap user logical memory out of physical memory.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPHYS_ADDR Physical
++** Start of physical address memory.
++**
++** gctSIZE_T Bytes
++** Number of bytes to unmap.
++**
++** gctPOINTER Memory
++** Pointer to a previously mapped memory region.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_UnmapUserLogical(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ IN gctPOINTER Logical
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Physical=0x%X Bytes=%lu Logical=0x%X",
++ Os, Physical, Bytes, Logical);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Physical != 0);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++
++ gckOS_UnmapMemory(Os, Physical, Bytes, Logical);
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++}
++
++/*******************************************************************************
++**
++** gckOS_AllocateNonPagedMemory
++**
++** Allocate a number of pages from non-paged memory.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctBOOL InUserSpace
++** gcvTRUE if the pages need to be mapped into user space.
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that holds the number of bytes to allocate.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that hold the number of bytes allocated.
++**
++** gctPHYS_ADDR * Physical
++** Pointer to a variable that will hold the physical address of the
++** allocation.
++**
++** gctPOINTER * Logical
++** Pointer to a variable that will hold the logical address of the
++** allocation.
++*/
++gceSTATUS
++gckOS_AllocateNonPagedMemory(
++ IN gckOS Os,
++ IN gctBOOL InUserSpace,
++ IN OUT gctSIZE_T * Bytes,
++ OUT gctPHYS_ADDR * Physical,
++ OUT gctPOINTER * Logical
++ )
++{
++ gctSIZE_T bytes;
++ gctINT numPages;
++ PLINUX_MDL mdl = gcvNULL;
++ PLINUX_MDL_MAP mdlMap = gcvNULL;
++ gctSTRING addr;
++#ifdef NO_DMA_COHERENT
++ struct page * page;
++ long size, order;
++ gctPOINTER vaddr;
++#endif
++ gctBOOL locked = gcvFALSE;
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%X InUserSpace=%d *Bytes=%lu",
++ Os, InUserSpace, gcmOPT_VALUE(Bytes));
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Bytes != gcvNULL);
++ gcmkVERIFY_ARGUMENT(*Bytes > 0);
++ gcmkVERIFY_ARGUMENT(Physical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++
++ /* Align number of bytes to page size. */
++ bytes = gcmALIGN(*Bytes, PAGE_SIZE);
++
++ /* Get total number of pages.. */
++ numPages = GetPageCount(bytes, 0);
++
++ /* Allocate mdl+vector structure */
++ mdl = _CreateMdl(_GetProcessID());
++ if (mdl == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ mdl->pagedMem = 0;
++ mdl->numPages = numPages;
++
++ MEMORY_LOCK(Os);
++ locked = gcvTRUE;
++
++#ifndef NO_DMA_COHERENT
++#if gcdUSE_NON_PAGED_MEMORY_CACHE
++ addr = _GetNonPagedMemoryCache(Os,
++ mdl->numPages * PAGE_SIZE,
++ &mdl->dmaHandle);
++
++ if (addr == gcvNULL)
++#endif
++ {
++ addr = dma_zalloc_coherent(gcvNULL,
++ mdl->numPages * PAGE_SIZE,
++ &mdl->dmaHandle,
++ GFP_KERNEL | gcdNOWARN);
++ }
++#if gcdUSE_NON_PAGED_MEMORY_CACHE
++ if(addr == gcvNULL)
++ {
++ MEMORY_UNLOCK(Os);
++ locked = gcvFALSE;
++ /*Free all cache and try again*/
++ _FreeAllNonPagedMemoryCache(Os);
++ MEMORY_LOCK(Os);
++ locked = gcvTRUE;
++ addr = dma_zalloc_coherent(gcvNULL,
++ mdl->numPages * PAGE_SIZE,
++ &mdl->dmaHandle,
++ GFP_KERNEL | gcdNOWARN);
++ }
++#endif
++#else
++ size = mdl->numPages * PAGE_SIZE;
++ order = get_order(size);
++#if gcdUSE_NON_PAGED_MEMORY_CACHE
++ page = _GetNonPagedMemoryCache(Os, order);
++
++ if (page == gcvNULL)
++#endif
++ {
++ page = alloc_pages(GFP_KERNEL | gcdNOWARN, order);
++ }
++
++ if (page == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ vaddr = (gctPOINTER)page_address(page);
++ mdl->contiguous = gcvTRUE;
++ mdl->u.contiguousPages = page;
++ addr = _CreateKernelVirtualMapping(mdl);
++ mdl->dmaHandle = virt_to_phys(vaddr);
++ mdl->kaddr = vaddr;
++ mdl->u.contiguousPages = page;
++
++#if !defined(CONFIG_PPC)
++ /* Cache invalidate. */
++ dma_sync_single_for_device(
++ gcvNULL,
++ page_to_phys(page),
++ bytes,
++ DMA_FROM_DEVICE);
++#endif
++
++ while (size > 0)
++ {
++ SetPageReserved(virt_to_page(vaddr));
++
++ vaddr += PAGE_SIZE;
++ size -= PAGE_SIZE;
++ }
++#endif
++
++ if (addr == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ mdl->addr = addr;
++
++ /* Return allocated memory. */
++ *Bytes = bytes;
++ *Physical = (gctPHYS_ADDR) mdl;
++
++ if (InUserSpace)
++ {
++ mdlMap = _CreateMdlMap(mdl, _GetProcessID());
++
++ if (mdlMap == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ /* Only after mmap this will be valid. */
++
++ /* We need to map this to user space. */
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0)
++ mdlMap->vmaAddr = (gctSTRING) vm_mmap(gcvNULL,
++ 0L,
++ mdl->numPages * PAGE_SIZE,
++ PROT_READ | PROT_WRITE,
++ MAP_SHARED,
++ 0);
++#else
++ down_write(&current->mm->mmap_sem);
++
++ mdlMap->vmaAddr = (gctSTRING) do_mmap_pgoff(gcvNULL,
++ 0L,
++ mdl->numPages * PAGE_SIZE,
++ PROT_READ | PROT_WRITE,
++ MAP_SHARED,
++ 0);
++
++ up_write(&current->mm->mmap_sem);
++#endif
++
++ if (IS_ERR(mdlMap->vmaAddr))
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_WARNING, gcvZONE_OS,
++ "%s(%d): do_mmap_pgoff error",
++ __FUNCTION__, __LINE__
++ );
++
++ mdlMap->vmaAddr = gcvNULL;
++
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ down_write(&current->mm->mmap_sem);
++
++ mdlMap->vma = find_vma(current->mm, (unsigned long)mdlMap->vmaAddr);
++
++ if (mdlMap->vma == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_WARNING, gcvZONE_OS,
++ "%s(%d): find_vma error",
++ __FUNCTION__, __LINE__
++ );
++
++ up_write(&current->mm->mmap_sem);
++
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++#ifndef NO_DMA_COHERENT
++ if (dma_mmap_coherent(gcvNULL,
++ mdlMap->vma,
++ mdl->addr,
++ mdl->dmaHandle,
++ mdl->numPages * PAGE_SIZE) < 0)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_WARNING, gcvZONE_OS,
++ "%s(%d): dma_mmap_coherent error",
++ __FUNCTION__, __LINE__
++ );
++
++ up_write(&current->mm->mmap_sem);
++
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++#else
++ mdlMap->vma->vm_page_prot = gcmkNONPAGED_MEMROY_PROT(mdlMap->vma->vm_page_prot);
++ mdlMap->vma->vm_flags |= gcdVM_FLAGS;
++ mdlMap->vma->vm_pgoff = 0;
++
++ if (remap_pfn_range(mdlMap->vma,
++ mdlMap->vma->vm_start,
++ mdl->dmaHandle >> PAGE_SHIFT,
++ mdl->numPages * PAGE_SIZE,
++ mdlMap->vma->vm_page_prot))
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_WARNING, gcvZONE_OS,
++ "%s(%d): remap_pfn_range error",
++ __FUNCTION__, __LINE__
++ );
++
++ up_write(&current->mm->mmap_sem);
++
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++#endif /* NO_DMA_COHERENT */
++
++ up_write(&current->mm->mmap_sem);
++
++ *Logical = mdlMap->vmaAddr;
++ }
++ else
++ {
++ *Logical = (gctPOINTER)mdl->addr;
++ }
++
++ /*
++ * Add this to a global list.
++ * Will be used by get physical address
++ * and mapuser pointer functions.
++ */
++
++ if (!Os->mdlHead)
++ {
++ /* Initialize the queue. */
++ Os->mdlHead = Os->mdlTail = mdl;
++ }
++ else
++ {
++ /* Add to the tail. */
++ mdl->prev = Os->mdlTail;
++ Os->mdlTail->next = mdl;
++ Os->mdlTail = mdl;
++ }
++
++ MEMORY_UNLOCK(Os);
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Bytes=%lu *Physical=0x%X *Logical=0x%X",
++ *Bytes, *Physical, *Logical);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (mdlMap != gcvNULL)
++ {
++ /* Free LINUX_MDL_MAP. */
++ gcmkVERIFY_OK(_DestroyMdlMap(mdl, mdlMap));
++ }
++
++ if (mdl != gcvNULL)
++ {
++ /* Free LINUX_MDL. */
++ gcmkVERIFY_OK(_DestroyMdl(mdl));
++ }
++
++ if (locked)
++ {
++ /* Unlock memory. */
++ MEMORY_UNLOCK(Os);
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_FreeNonPagedMemory
++**
++** Free previously allocated and mapped pages from non-paged memory.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctSIZE_T Bytes
++** Number of bytes allocated.
++**
++** gctPHYS_ADDR Physical
++** Physical address of the allocated memory.
++**
++** gctPOINTER Logical
++** Logical address of the allocated memory.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS gckOS_FreeNonPagedMemory(
++ IN gckOS Os,
++ IN gctSIZE_T Bytes,
++ IN gctPHYS_ADDR Physical,
++ IN gctPOINTER Logical
++ )
++{
++ PLINUX_MDL mdl;
++ PLINUX_MDL_MAP mdlMap;
++#ifdef NO_DMA_COHERENT
++ unsigned size;
++ gctPOINTER vaddr;
++#endif /* NO_DMA_COHERENT */
++
++ gcmkHEADER_ARG("Os=0x%X Bytes=%lu Physical=0x%X Logical=0x%X",
++ Os, Bytes, Physical, Logical);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++ gcmkVERIFY_ARGUMENT(Physical != 0);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++
++ /* Convert physical address into a pointer to a MDL. */
++ mdl = (PLINUX_MDL) Physical;
++
++ MEMORY_LOCK(Os);
++
++#ifndef NO_DMA_COHERENT
++#if gcdUSE_NON_PAGED_MEMORY_CACHE
++ if (!_AddNonPagedMemoryCache(Os,
++ mdl->numPages * PAGE_SIZE,
++ mdl->addr,
++ mdl->dmaHandle))
++#endif
++ {
++ dma_free_coherent(gcvNULL,
++ mdl->numPages * PAGE_SIZE,
++ mdl->addr,
++ mdl->dmaHandle);
++ }
++#else
++ size = mdl->numPages * PAGE_SIZE;
++ vaddr = mdl->kaddr;
++
++ while (size > 0)
++ {
++ ClearPageReserved(virt_to_page(vaddr));
++
++ vaddr += PAGE_SIZE;
++ size -= PAGE_SIZE;
++ }
++
++#if gcdUSE_NON_PAGED_MEMORY_CACHE
++ if (!_AddNonPagedMemoryCache(Os,
++ get_order(mdl->numPages * PAGE_SIZE),
++ virt_to_page(mdl->kaddr)))
++#endif
++ {
++ free_pages((unsigned long)mdl->kaddr, get_order(mdl->numPages * PAGE_SIZE));
++ }
++
++ _DestoryKernelVirtualMapping(mdl->addr);
++#endif /* NO_DMA_COHERENT */
++
++ mdlMap = mdl->maps;
++
++ while (mdlMap != gcvNULL)
++ {
++ if (mdlMap->vmaAddr != gcvNULL)
++ {
++ /* No mapped memory exists when free nonpaged memory */
++ gcmkASSERT(0);
++ }
++
++ mdlMap = mdlMap->next;
++ }
++
++ /* Remove the node from global list.. */
++ if (mdl == Os->mdlHead)
++ {
++ if ((Os->mdlHead = mdl->next) == gcvNULL)
++ {
++ Os->mdlTail = gcvNULL;
++ }
++ }
++ else
++ {
++ mdl->prev->next = mdl->next;
++ if (mdl == Os->mdlTail)
++ {
++ Os->mdlTail = mdl->prev;
++ }
++ else
++ {
++ mdl->next->prev = mdl->prev;
++ }
++ }
++
++ MEMORY_UNLOCK(Os);
++
++ gcmkVERIFY_OK(_DestroyMdl(mdl));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_ReadRegister
++**
++** Read data from a register.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctUINT32 Address
++** Address of register.
++**
++** OUTPUT:
++**
++** gctUINT32 * Data
++** Pointer to a variable that receives the data read from the register.
++*/
++gceSTATUS
++gckOS_ReadRegister(
++ IN gckOS Os,
++ IN gctUINT32 Address,
++ OUT gctUINT32 * Data
++ )
++{
++ return gckOS_ReadRegisterEx(Os, gcvCORE_MAJOR, Address, Data);
++}
++
++gceSTATUS
++gckOS_ReadRegisterEx(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctUINT32 Address,
++ OUT gctUINT32 * Data
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Core=%d Address=0x%X", Os, Core, Address);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Address < Os->device->requestedRegisterMemSizes[Core]);
++ gcmkVERIFY_ARGUMENT(Data != gcvNULL);
++
++ if(Address != 0x10) mutex_lock(&Os->gpu_clk_mutex);
++ BUG_ON(!Os->gpu_clk_on[Core]);
++
++ if(Address)
++ {
++ gctUINT32 AQHiClockControl = readl((gctUINT8 *)Os->device->registerBases[Core]);
++ BUG_ON((AQHiClockControl & 0x3) == 0x3);
++ }
++
++ *Data = readl((gctUINT8 *)Os->device->registerBases[Core] + Address);
++ if(Address != 0x10) mutex_unlock(&Os->gpu_clk_mutex);
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Data=0x%08x", *Data);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_WriteRegister
++**
++** Write data to a register.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctUINT32 Address
++** Address of register.
++**
++** gctUINT32 Data
++** Data for register.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_WriteRegister(
++ IN gckOS Os,
++ IN gctUINT32 Address,
++ IN gctUINT32 Data
++ )
++{
++ return gckOS_WriteRegisterEx(Os, gcvCORE_MAJOR, Address, Data);
++}
++
++gceSTATUS
++gckOS_WriteRegisterEx(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctUINT32 Address,
++ IN gctUINT32 Data
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Core=%d Address=0x%X Data=0x%08x", Os, Core, Address, Data);
++
++ gcmkVERIFY_ARGUMENT(Address < Os->device->requestedRegisterMemSizes[Core]);
++
++ mutex_lock(&Os->gpu_clk_mutex);
++ BUG_ON(!Os->gpu_clk_on[Core]);
++
++ if(Address)
++ {
++ gctUINT32 AQHiClockControl = readl((gctUINT8 *)Os->device->registerBases[Core]);
++ BUG_ON((AQHiClockControl & 0x3) == 0x3);
++ }
++
++ writel(Data, (gctUINT8 *)Os->device->registerBases[Core] + Address);
++ mutex_unlock(&Os->gpu_clk_mutex);
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_GetPageSize
++**
++** Get the system's page size.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** OUTPUT:
++**
++** gctSIZE_T * PageSize
++** Pointer to a variable that will receive the system's page size.
++*/
++gceSTATUS gckOS_GetPageSize(
++ IN gckOS Os,
++ OUT gctSIZE_T * PageSize
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X", Os);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(PageSize != gcvNULL);
++
++ /* Return the page size. */
++ *PageSize = (gctSIZE_T) PAGE_SIZE;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*PageSize", *PageSize);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_GetPhysicalAddress
++**
++** Get the physical system address of a corresponding virtual address.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPOINTER Logical
++** Logical address.
++**
++** OUTPUT:
++**
++** gctUINT32 * Address
++** Poinetr to a variable that receives the 32-bit physical adress.
++*/
++gceSTATUS
++gckOS_GetPhysicalAddress(
++ IN gckOS Os,
++ IN gctPOINTER Logical,
++ OUT gctUINT32 * Address
++ )
++{
++ gceSTATUS status;
++ gctUINT32 processID;
++
++ gcmkHEADER_ARG("Os=0x%X Logical=0x%X", Os, Logical);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Address != gcvNULL);
++
++ /* Query page table of current process first. */
++ status = _QueryProcessPageTable(Logical, Address);
++
++ if (gcmIS_ERROR(status))
++ {
++ /* Get current process ID. */
++ processID = _GetProcessID();
++
++ /* Route through other function. */
++ gcmkONERROR(
++ gckOS_GetPhysicalAddressProcess(Os, Logical, processID, Address));
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Address=0x%08x", *Address);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++#if gcdSECURE_USER
++static gceSTATUS
++gckOS_AddMapping(
++ IN gckOS Os,
++ IN gctUINT32 Physical,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes
++ )
++{
++ gceSTATUS status;
++ gcsUSER_MAPPING_PTR map;
++
++ gcmkHEADER_ARG("Os=0x%X Physical=0x%X Logical=0x%X Bytes=%lu",
++ Os, Physical, Logical, Bytes);
++
++ gcmkONERROR(gckOS_Allocate(Os,
++ gcmSIZEOF(gcsUSER_MAPPING),
++ (gctPOINTER *) &map));
++
++ map->next = Os->userMap;
++ map->physical = Physical - Os->device->baseAddress;
++ map->logical = Logical;
++ map->bytes = Bytes;
++ map->start = (gctINT8_PTR) Logical;
++ map->end = map->start + Bytes;
++
++ Os->userMap = map;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++static gceSTATUS
++gckOS_RemoveMapping(
++ IN gckOS Os,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes
++ )
++{
++ gceSTATUS status;
++ gcsUSER_MAPPING_PTR map, prev;
++
++ gcmkHEADER_ARG("Os=0x%X Logical=0x%X Bytes=%lu", Os, Logical, Bytes);
++
++ for (map = Os->userMap, prev = gcvNULL; map != gcvNULL; map = map->next)
++ {
++ if ((map->logical == Logical)
++ && (map->bytes == Bytes)
++ )
++ {
++ break;
++ }
++
++ prev = map;
++ }
++
++ if (map == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_INVALID_ADDRESS);
++ }
++
++ if (prev == gcvNULL)
++ {
++ Os->userMap = map->next;
++ }
++ else
++ {
++ prev->next = map->next;
++ }
++
++ gcmkONERROR(gcmkOS_SAFE_FREE(Os, map));
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++#endif
++
++static gceSTATUS
++_ConvertLogical2Physical(
++ IN gckOS Os,
++ IN gctPOINTER Logical,
++ IN gctUINT32 ProcessID,
++ IN PLINUX_MDL Mdl,
++ OUT gctUINT32_PTR Physical
++ )
++{
++ gctINT8_PTR base, vBase;
++ gctUINT32 offset;
++ PLINUX_MDL_MAP map;
++ gcsUSER_MAPPING_PTR userMap;
++
++ base = (Mdl == gcvNULL) ? gcvNULL : (gctINT8_PTR) Mdl->addr;
++
++ /* Check for the logical address match. */
++ if ((base != gcvNULL)
++ && ((gctINT8_PTR) Logical >= base)
++ && ((gctINT8_PTR) Logical < base + Mdl->numPages * PAGE_SIZE)
++ )
++ {
++ offset = (gctINT8_PTR) Logical - base;
++
++ if (Mdl->dmaHandle != 0)
++ {
++ /* The memory was from coherent area. */
++ *Physical = (gctUINT32) Mdl->dmaHandle + offset;
++ }
++ else if (Mdl->pagedMem && !Mdl->contiguous)
++ {
++ /* paged memory is not mapped to kernel space. */
++ return gcvSTATUS_INVALID_ADDRESS;
++ }
++ else
++ {
++ *Physical = gcmPTR2INT(virt_to_phys(base)) + offset;
++ }
++
++ return gcvSTATUS_OK;
++ }
++
++ /* Walk user maps. */
++ for (userMap = Os->userMap; userMap != gcvNULL; userMap = userMap->next)
++ {
++ if (((gctINT8_PTR) Logical >= userMap->start)
++ && ((gctINT8_PTR) Logical < userMap->end)
++ )
++ {
++ *Physical = userMap->physical
++ + (gctUINT32) ((gctINT8_PTR) Logical - userMap->start);
++
++ return gcvSTATUS_OK;
++ }
++ }
++
++ if (ProcessID != Os->kernelProcessID)
++ {
++ map = FindMdlMap(Mdl, (gctINT) ProcessID);
++ vBase = (map == gcvNULL) ? gcvNULL : (gctINT8_PTR) map->vmaAddr;
++
++ /* Is the given address within that range. */
++ if ((vBase != gcvNULL)
++ && ((gctINT8_PTR) Logical >= vBase)
++ && ((gctINT8_PTR) Logical < vBase + Mdl->numPages * PAGE_SIZE)
++ )
++ {
++ offset = (gctINT8_PTR) Logical - vBase;
++
++ if (Mdl->dmaHandle != 0)
++ {
++ /* The memory was from coherent area. */
++ *Physical = (gctUINT32) Mdl->dmaHandle + offset;
++ }
++ else if (Mdl->pagedMem && !Mdl->contiguous)
++ {
++ *Physical = _NonContiguousToPhys(Mdl->u.nonContiguousPages, offset/PAGE_SIZE);
++ }
++ else
++ {
++ *Physical = page_to_phys(Mdl->u.contiguousPages) + offset;
++ }
++
++ return gcvSTATUS_OK;
++ }
++ }
++
++ /* Address not yet found. */
++ return gcvSTATUS_INVALID_ADDRESS;
++}
++
++/*******************************************************************************
++**
++** gckOS_GetPhysicalAddressProcess
++**
++** Get the physical system address of a corresponding virtual address for a
++** given process.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to gckOS object.
++**
++** gctPOINTER Logical
++** Logical address.
++**
++** gctUINT32 ProcessID
++** Process ID.
++**
++** OUTPUT:
++**
++** gctUINT32 * Address
++** Poinetr to a variable that receives the 32-bit physical adress.
++*/
++gceSTATUS
++gckOS_GetPhysicalAddressProcess(
++ IN gckOS Os,
++ IN gctPOINTER Logical,
++ IN gctUINT32 ProcessID,
++ OUT gctUINT32 * Address
++ )
++{
++ PLINUX_MDL mdl;
++ gctINT8_PTR base;
++ gceSTATUS status = gcvSTATUS_INVALID_ADDRESS;
++
++ gcmkHEADER_ARG("Os=0x%X Logical=0x%X ProcessID=%d", Os, Logical, ProcessID);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Address != gcvNULL);
++
++ MEMORY_LOCK(Os);
++
++ /* First try the contiguous memory pool. */
++ if (Os->device->contiguousMapped)
++ {
++ base = (gctINT8_PTR) Os->device->contiguousBase;
++
++ if (((gctINT8_PTR) Logical >= base)
++ && ((gctINT8_PTR) Logical < base + Os->device->contiguousSize)
++ )
++ {
++ /* Convert logical address into physical. */
++ *Address = Os->device->contiguousVidMem->baseAddress
++ + (gctINT8_PTR) Logical - base;
++ status = gcvSTATUS_OK;
++ }
++ }
++ else
++ {
++ /* Try the contiguous memory pool. */
++ mdl = (PLINUX_MDL) Os->device->contiguousPhysical;
++ status = _ConvertLogical2Physical(Os,
++ Logical,
++ ProcessID,
++ mdl,
++ Address);
++ }
++
++ if (gcmIS_ERROR(status))
++ {
++ /* Walk all MDLs. */
++ for (mdl = Os->mdlHead; mdl != gcvNULL; mdl = mdl->next)
++ {
++ /* Try this MDL. */
++ status = _ConvertLogical2Physical(Os,
++ Logical,
++ ProcessID,
++ mdl,
++ Address);
++ if (gcmIS_SUCCESS(status))
++ {
++ break;
++ }
++ }
++ }
++
++ MEMORY_UNLOCK(Os);
++
++ gcmkONERROR(status);
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Address=0x%08x", *Address);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_MapPhysical
++**
++** Map a physical address into kernel space.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctUINT32 Physical
++** Physical address of the memory to map.
++**
++** gctSIZE_T Bytes
++** Number of bytes to map.
++**
++** OUTPUT:
++**
++** gctPOINTER * Logical
++** Pointer to a variable that receives the base address of the mapped
++** memory.
++*/
++gceSTATUS
++gckOS_MapPhysical(
++ IN gckOS Os,
++ IN gctUINT32 Physical,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Logical
++ )
++{
++ gctPOINTER logical;
++ PLINUX_MDL mdl;
++ gctUINT32 physical = Physical;
++
++ gcmkHEADER_ARG("Os=0x%X Physical=0x%X Bytes=%lu", Os, Physical, Bytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++
++ MEMORY_LOCK(Os);
++
++ /* Go through our mapping to see if we know this physical address already. */
++ mdl = Os->mdlHead;
++
++ while (mdl != gcvNULL)
++ {
++ if (mdl->dmaHandle != 0)
++ {
++ if ((physical >= mdl->dmaHandle)
++ && (physical < mdl->dmaHandle + mdl->numPages * PAGE_SIZE)
++ )
++ {
++ *Logical = mdl->addr + (physical - mdl->dmaHandle);
++ break;
++ }
++ }
++
++ mdl = mdl->next;
++ }
++
++ if (mdl == gcvNULL)
++ {
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
++ struct contiguous_mem_pool *pool = Os->device->pool;
++
++ if (Physical >= pool->phys && Physical < pool->phys + pool->size)
++ logical = (gctPOINTER)(Physical - pool->phys + pool->virt);
++ else
++ logical = gcvNULL;
++#else
++ /* Map memory as cached memory. */
++ request_mem_region(physical, Bytes, "MapRegion");
++ logical = (gctPOINTER) ioremap_nocache(physical, Bytes);
++#endif
++
++ if (logical == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): Failed to map physical address 0x%08x",
++ __FUNCTION__, __LINE__, Physical
++ );
++
++ MEMORY_UNLOCK(Os);
++
++ /* Out of resources. */
++ gcmkFOOTER_ARG("status=%d", gcvSTATUS_OUT_OF_RESOURCES);
++ return gcvSTATUS_OUT_OF_RESOURCES;
++ }
++
++ /* Return pointer to mapped memory. */
++ *Logical = logical;
++ }
++
++ MEMORY_UNLOCK(Os);
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Logical=0x%X", *Logical);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_UnmapPhysical
++**
++** Unmap a previously mapped memory region from kernel memory.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPOINTER Logical
++** Pointer to the base address of the memory to unmap.
++**
++** gctSIZE_T Bytes
++** Number of bytes to unmap.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_UnmapPhysical(
++ IN gckOS Os,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes
++ )
++{
++ PLINUX_MDL mdl;
++
++ gcmkHEADER_ARG("Os=0x%X Logical=0x%X Bytes=%lu", Os, Logical, Bytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++
++ MEMORY_LOCK(Os);
++
++ mdl = Os->mdlHead;
++
++ while (mdl != gcvNULL)
++ {
++ if (mdl->addr != gcvNULL)
++ {
++ if (Logical >= (gctPOINTER)mdl->addr
++ && Logical < (gctPOINTER)((gctSTRING)mdl->addr + mdl->numPages * PAGE_SIZE))
++ {
++ break;
++ }
++ }
++
++ mdl = mdl->next;
++ }
++
++ if (mdl == gcvNULL)
++ {
++ /* Unmap the memory. */
++ iounmap(Logical);
++ }
++
++ MEMORY_UNLOCK(Os);
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_CreateMutex
++**
++** Create a new mutex.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** OUTPUT:
++**
++** gctPOINTER * Mutex
++** Pointer to a variable that will hold a pointer to the mutex.
++*/
++gceSTATUS
++gckOS_CreateMutex(
++ IN gckOS Os,
++ OUT gctPOINTER * Mutex
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%X", Os);
++
++ /* Validate the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Mutex != gcvNULL);
++
++ /* Allocate the mutex structure. */
++ gcmkONERROR(gckOS_Allocate(Os, gcmSIZEOF(struct mutex), Mutex));
++
++ /* Initialize the mutex. */
++ mutex_init(*Mutex);
++
++ /* Return status. */
++ gcmkFOOTER_ARG("*Mutex=0x%X", *Mutex);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_DeleteMutex
++**
++** Delete a mutex.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPOINTER Mutex
++** Pointer to the mute to be deleted.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_DeleteMutex(
++ IN gckOS Os,
++ IN gctPOINTER Mutex
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%X Mutex=0x%X", Os, Mutex);
++
++ /* Validate the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Mutex != gcvNULL);
++
++ /* Destroy the mutex. */
++ mutex_destroy(Mutex);
++
++ /* Free the mutex structure. */
++ gcmkONERROR(gckOS_Free(Os, Mutex));
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_AcquireMutex
++**
++** Acquire a mutex.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPOINTER Mutex
++** Pointer to the mutex to be acquired.
++**
++** gctUINT32 Timeout
++** Timeout value specified in milliseconds.
++** Specify the value of gcvINFINITE to keep the thread suspended
++** until the mutex has been acquired.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_AcquireMutex(
++ IN gckOS Os,
++ IN gctPOINTER Mutex,
++ IN gctUINT32 Timeout
++ )
++{
++#if gcdDETECT_TIMEOUT
++ gctUINT32 timeout;
++#endif
++
++ gcmkHEADER_ARG("Os=0x%X Mutex=0x%0x Timeout=%u", Os, Mutex, Timeout);
++
++ /* Validate the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Mutex != gcvNULL);
++
++#if gcdDETECT_TIMEOUT
++ timeout = 0;
++
++ for (;;)
++ {
++ /* Try to acquire the mutex. */
++ if (mutex_trylock(Mutex))
++ {
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++
++ /* Advance the timeout. */
++ timeout += 1;
++
++ if (Timeout == gcvINFINITE)
++ {
++ if (timeout == gcdINFINITE_TIMEOUT)
++ {
++ gctUINT32 dmaAddress1, dmaAddress2;
++ gctUINT32 dmaState1, dmaState2;
++
++ dmaState1 = dmaState2 =
++ dmaAddress1 = dmaAddress2 = 0;
++
++ /* Verify whether DMA is running. */
++ gcmkVERIFY_OK(_VerifyDMA(
++ Os, &dmaAddress1, &dmaAddress2, &dmaState1, &dmaState2
++ ));
++
++#if gcdDETECT_DMA_ADDRESS
++ /* Dump only if DMA appears stuck. */
++ if (
++ (dmaAddress1 == dmaAddress2)
++#if gcdDETECT_DMA_STATE
++ && (dmaState1 == dmaState2)
++# endif
++ )
++# endif
++ {
++ gcmkVERIFY_OK(_DumpGPUState(Os, gcvCORE_MAJOR));
++
++ gcmkPRINT(
++ "%s(%d): mutex 0x%X; forced message flush.",
++ __FUNCTION__, __LINE__, Mutex
++ );
++
++ /* Flush the debug cache. */
++ gcmkDEBUGFLUSH(dmaAddress2);
++ }
++
++ timeout = 0;
++ }
++ }
++ else
++ {
++ /* Timedout? */
++ if (timeout >= Timeout)
++ {
++ break;
++ }
++ }
++
++ /* Wait for 1 millisecond. */
++ gcmkVERIFY_OK(gckOS_Delay(Os, 1));
++ }
++#else
++ if (Timeout == gcvINFINITE)
++ {
++ /* Lock the mutex. */
++ mutex_lock(Mutex);
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++
++ for (;;)
++ {
++ /* Try to acquire the mutex. */
++ if (mutex_trylock(Mutex))
++ {
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++
++ if (Timeout-- == 0)
++ {
++ break;
++ }
++
++ /* Wait for 1 millisecond. */
++ gcmkVERIFY_OK(gckOS_Delay(Os, 1));
++ }
++#endif
++
++ /* Timeout. */
++ gcmkFOOTER_ARG("status=%d", gcvSTATUS_TIMEOUT);
++ return gcvSTATUS_TIMEOUT;
++}
++
++/*******************************************************************************
++**
++** gckOS_ReleaseMutex
++**
++** Release an acquired mutex.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPOINTER Mutex
++** Pointer to the mutex to be released.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_ReleaseMutex(
++ IN gckOS Os,
++ IN gctPOINTER Mutex
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Mutex=0x%0x", Os, Mutex);
++
++ /* Validate the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Mutex != gcvNULL);
++
++ /* Release the mutex. */
++ mutex_unlock(Mutex);
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_AtomicExchange
++**
++** Atomically exchange a pair of 32-bit values.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** IN OUT gctINT32_PTR Target
++** Pointer to the 32-bit value to exchange.
++**
++** IN gctINT32 NewValue
++** Specifies a new value for the 32-bit value pointed to by Target.
++**
++** OUT gctINT32_PTR OldValue
++** The old value of the 32-bit value pointed to by Target.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_AtomicExchange(
++ IN gckOS Os,
++ IN OUT gctUINT32_PTR Target,
++ IN gctUINT32 NewValue,
++ OUT gctUINT32_PTR OldValue
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Target=0x%X NewValue=%u", Os, Target, NewValue);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++
++ /* Exchange the pair of 32-bit values. */
++ *OldValue = (gctUINT32) atomic_xchg((atomic_t *) Target, (int) NewValue);
++
++ /* Success. */
++ gcmkFOOTER_ARG("*OldValue=%u", *OldValue);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_AtomicExchangePtr
++**
++** Atomically exchange a pair of pointers.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** IN OUT gctPOINTER * Target
++** Pointer to the 32-bit value to exchange.
++**
++** IN gctPOINTER NewValue
++** Specifies a new value for the pointer pointed to by Target.
++**
++** OUT gctPOINTER * OldValue
++** The old value of the pointer pointed to by Target.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_AtomicExchangePtr(
++ IN gckOS Os,
++ IN OUT gctPOINTER * Target,
++ IN gctPOINTER NewValue,
++ OUT gctPOINTER * OldValue
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Target=0x%X NewValue=0x%X", Os, Target, NewValue);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++
++ /* Exchange the pair of pointers. */
++ *OldValue = (gctPOINTER)(gctUINTPTR_T) atomic_xchg((atomic_t *) Target, (int)(gctUINTPTR_T) NewValue);
++
++ /* Success. */
++ gcmkFOOTER_ARG("*OldValue=0x%X", *OldValue);
++ return gcvSTATUS_OK;
++}
++
++#if gcdSMP
++/*******************************************************************************
++**
++** gckOS_AtomicSetMask
++**
++** Atomically set mask to Atom
++**
++** INPUT:
++** IN OUT gctPOINTER Atom
++** Pointer to the atom to set.
++**
++** IN gctUINT32 Mask
++** Mask to set.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_AtomSetMask(
++ IN gctPOINTER Atom,
++ IN gctUINT32 Mask
++ )
++{
++ gctUINT32 oval, nval;
++
++ gcmkHEADER_ARG("Atom=0x%0x", Atom);
++ gcmkVERIFY_ARGUMENT(Atom != gcvNULL);
++
++ do
++ {
++ oval = atomic_read((atomic_t *) Atom);
++ nval = oval | Mask;
++ } while (atomic_cmpxchg((atomic_t *) Atom, oval, nval) != oval);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_AtomClearMask
++**
++** Atomically clear mask from Atom
++**
++** INPUT:
++** IN OUT gctPOINTER Atom
++** Pointer to the atom to clear.
++**
++** IN gctUINT32 Mask
++** Mask to clear.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_AtomClearMask(
++ IN gctPOINTER Atom,
++ IN gctUINT32 Mask
++ )
++{
++ gctUINT32 oval, nval;
++
++ gcmkHEADER_ARG("Atom=0x%0x", Atom);
++ gcmkVERIFY_ARGUMENT(Atom != gcvNULL);
++
++ do
++ {
++ oval = atomic_read((atomic_t *) Atom);
++ nval = oval & ~Mask;
++ } while (atomic_cmpxchg((atomic_t *) Atom, oval, nval) != oval);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++#endif
++
++/*******************************************************************************
++**
++** gckOS_AtomConstruct
++**
++** Create an atom.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** OUTPUT:
++**
++** gctPOINTER * Atom
++** Pointer to a variable receiving the constructed atom.
++*/
++gceSTATUS
++gckOS_AtomConstruct(
++ IN gckOS Os,
++ OUT gctPOINTER * Atom
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%X", Os);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Atom != gcvNULL);
++
++ /* Allocate the atom. */
++ gcmkONERROR(gckOS_Allocate(Os, gcmSIZEOF(atomic_t), Atom));
++
++ /* Initialize the atom. */
++ atomic_set((atomic_t *) *Atom, 0);
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Atom=0x%X", *Atom);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_AtomDestroy
++**
++** Destroy an atom.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gctPOINTER Atom
++** Pointer to the atom to destroy.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_AtomDestroy(
++ IN gckOS Os,
++ OUT gctPOINTER Atom
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%X Atom=0x%0x", Os, Atom);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Atom != gcvNULL);
++
++ /* Free the atom. */
++ gcmkONERROR(gcmkOS_SAFE_FREE(Os, Atom));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_AtomGet
++**
++** Get the 32-bit value protected by an atom.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gctPOINTER Atom
++** Pointer to the atom.
++**
++** OUTPUT:
++**
++** gctINT32_PTR Value
++** Pointer to a variable the receives the value of the atom.
++*/
++gceSTATUS
++gckOS_AtomGet(
++ IN gckOS Os,
++ IN gctPOINTER Atom,
++ OUT gctINT32_PTR Value
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Atom=0x%0x", Os, Atom);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Atom != gcvNULL);
++
++ /* Return the current value of atom. */
++ *Value = atomic_read((atomic_t *) Atom);
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Value=%d", *Value);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_AtomSet
++**
++** Set the 32-bit value protected by an atom.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gctPOINTER Atom
++** Pointer to the atom.
++**
++** gctINT32 Value
++** The value of the atom.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_AtomSet(
++ IN gckOS Os,
++ IN gctPOINTER Atom,
++ IN gctINT32 Value
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Atom=0x%0x Value=%d", Os, Atom);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Atom != gcvNULL);
++
++ /* Set the current value of atom. */
++ atomic_set((atomic_t *) Atom, Value);
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_AtomIncrement
++**
++** Atomically increment the 32-bit integer value inside an atom.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gctPOINTER Atom
++** Pointer to the atom.
++**
++** OUTPUT:
++**
++** gctINT32_PTR Value
++** Pointer to a variable that receives the original value of the atom.
++*/
++gceSTATUS
++gckOS_AtomIncrement(
++ IN gckOS Os,
++ IN gctPOINTER Atom,
++ OUT gctINT32_PTR Value
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Atom=0x%0x", Os, Atom);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Atom != gcvNULL);
++
++ /* Increment the atom. */
++ *Value = atomic_inc_return((atomic_t *) Atom) - 1;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Value=%d", *Value);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_AtomDecrement
++**
++** Atomically decrement the 32-bit integer value inside an atom.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gctPOINTER Atom
++** Pointer to the atom.
++**
++** OUTPUT:
++**
++** gctINT32_PTR Value
++** Pointer to a variable that receives the original value of the atom.
++*/
++gceSTATUS
++gckOS_AtomDecrement(
++ IN gckOS Os,
++ IN gctPOINTER Atom,
++ OUT gctINT32_PTR Value
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Atom=0x%0x", Os, Atom);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Atom != gcvNULL);
++
++ /* Decrement the atom. */
++ *Value = atomic_dec_return((atomic_t *) Atom) + 1;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Value=%d", *Value);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_Delay
++**
++** Delay execution of the current thread for a number of milliseconds.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctUINT32 Delay
++** Delay to sleep, specified in milliseconds.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_Delay(
++ IN gckOS Os,
++ IN gctUINT32 Delay
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Delay=%u", Os, Delay);
++
++ if (Delay > 0)
++ {
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 28)
++ ktime_t delay = ktime_set(Delay/1000, (Delay%1000) * NSEC_PER_MSEC);
++ __set_current_state(TASK_UNINTERRUPTIBLE);
++ schedule_hrtimeout(&delay, HRTIMER_MODE_REL);
++#else
++ msleep(Delay);
++#endif
++
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_GetTicks
++**
++** Get the number of milliseconds since the system started.
++**
++** INPUT:
++**
++** OUTPUT:
++**
++** gctUINT32_PTR Time
++** Pointer to a variable to get time.
++**
++*/
++gceSTATUS
++gckOS_GetTicks(
++ OUT gctUINT32_PTR Time
++ )
++{
++ gcmkHEADER();
++
++ *Time = jiffies_to_msecs(jiffies);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_TicksAfter
++**
++** Compare time values got from gckOS_GetTicks.
++**
++** INPUT:
++** gctUINT32 Time1
++** First time value to be compared.
++**
++** gctUINT32 Time2
++** Second time value to be compared.
++**
++** OUTPUT:
++**
++** gctBOOL_PTR IsAfter
++** Pointer to a variable to result.
++**
++*/
++gceSTATUS
++gckOS_TicksAfter(
++ IN gctUINT32 Time1,
++ IN gctUINT32 Time2,
++ OUT gctBOOL_PTR IsAfter
++ )
++{
++ gcmkHEADER();
++
++ *IsAfter = time_after((unsigned long)Time1, (unsigned long)Time2);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_GetTime
++**
++** Get the number of microseconds since the system started.
++**
++** INPUT:
++**
++** OUTPUT:
++**
++** gctUINT64_PTR Time
++** Pointer to a variable to get time.
++**
++*/
++gceSTATUS
++gckOS_GetTime(
++ OUT gctUINT64_PTR Time
++ )
++{
++ gcmkHEADER();
++
++ *Time = 0;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_MemoryBarrier
++**
++** Make sure the CPU has executed everything up to this point and the data got
++** written to the specified pointer.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPOINTER Address
++** Address of memory that needs to be barriered.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_MemoryBarrier(
++ IN gckOS Os,
++ IN gctPOINTER Address
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Address=0x%X", Os, Address);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++
++#if gcdNONPAGED_MEMORY_BUFFERABLE \
++ && defined (CONFIG_ARM) \
++ && (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,34))
++ /* drain write buffer */
++ dsb();
++
++ /* drain outer cache's write buffer? */
++#else
++ mb();
++#endif
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_AllocatePagedMemory
++**
++** Allocate memory from the paged pool.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctSIZE_T Bytes
++** Number of bytes to allocate.
++**
++** OUTPUT:
++**
++** gctPHYS_ADDR * Physical
++** Pointer to a variable that receives the physical address of the
++** memory allocation.
++*/
++gceSTATUS
++gckOS_AllocatePagedMemory(
++ IN gckOS Os,
++ IN gctSIZE_T Bytes,
++ OUT gctPHYS_ADDR * Physical
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%X Bytes=%lu", Os, Bytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++ gcmkVERIFY_ARGUMENT(Physical != gcvNULL);
++
++ /* Allocate the memory. */
++ gcmkONERROR(gckOS_AllocatePagedMemoryEx(Os, gcvFALSE, Bytes, Physical));
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Physical=0x%X", *Physical);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_AllocatePagedMemoryEx
++**
++** Allocate memory from the paged pool.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctBOOL Contiguous
++** Need contiguous memory or not.
++**
++** gctSIZE_T Bytes
++** Number of bytes to allocate.
++**
++** OUTPUT:
++**
++** gctPHYS_ADDR * Physical
++** Pointer to a variable that receives the physical address of the
++** memory allocation.
++*/
++gceSTATUS
++gckOS_AllocatePagedMemoryEx(
++ IN gckOS Os,
++ IN gctBOOL Contiguous,
++ IN gctSIZE_T Bytes,
++ OUT gctPHYS_ADDR * Physical
++ )
++{
++ gctINT numPages;
++ gctINT i;
++ PLINUX_MDL mdl = gcvNULL;
++ gctSIZE_T bytes;
++ gctBOOL locked = gcvFALSE;
++ gceSTATUS status;
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)
++ gctPOINTER addr = gcvNULL;
++#endif
++
++ gcmkHEADER_ARG("Os=0x%X Contiguous=%d Bytes=%lu", Os, Contiguous, Bytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++ gcmkVERIFY_ARGUMENT(Physical != gcvNULL);
++
++ bytes = gcmALIGN(Bytes, PAGE_SIZE);
++
++ numPages = GetPageCount(bytes, 0);
++
++ MEMORY_LOCK(Os);
++ locked = gcvTRUE;
++
++ mdl = _CreateMdl(_GetProcessID());
++ if (mdl == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ if (Contiguous)
++ {
++ gctUINT32 order = get_order(bytes);
++
++ if (order >= MAX_ORDER)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)
++ addr =
++ alloc_pages_exact(numPages * PAGE_SIZE, GFP_KERNEL | gcdNOWARN | __GFP_NORETRY);
++
++ mdl->u.contiguousPages = addr
++ ? virt_to_page(addr)
++ : gcvNULL;
++
++ mdl->exact = gcvTRUE;
++#else
++ mdl->u.contiguousPages =
++ alloc_pages(GFP_KERNEL | gcdNOWARN | __GFP_NORETRY, order);
++#endif
++ if (mdl->u.contiguousPages == gcvNULL)
++ {
++ mdl->u.contiguousPages =
++ alloc_pages(GFP_KERNEL | __GFP_HIGHMEM | gcdNOWARN, order);
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)
++ mdl->exact = gcvFALSE;
++#endif
++ }
++ }
++ else
++ {
++ mdl->u.nonContiguousPages = _NonContiguousAlloc(numPages);
++ }
++
++ if (mdl->u.contiguousPages == gcvNULL && mdl->u.nonContiguousPages == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ mdl->dmaHandle = 0;
++ mdl->addr = 0;
++ mdl->numPages = numPages;
++ mdl->pagedMem = 1;
++ mdl->contiguous = Contiguous;
++
++ for (i = 0; i < mdl->numPages; i++)
++ {
++ struct page *page;
++
++ if (mdl->contiguous)
++ {
++ page = nth_page(mdl->u.contiguousPages, i);
++ }
++ else
++ {
++ page = _NonContiguousToPage(mdl->u.nonContiguousPages, i);
++ }
++
++ SetPageReserved(page);
++
++ if (!PageHighMem(page) && page_to_phys(page))
++ {
++ gcmkVERIFY_OK(
++ gckOS_CacheFlush(Os, _GetProcessID(), gcvNULL,
++ (gctPOINTER)(gctUINTPTR_T)page_to_phys(page),
++ page_address(page),
++ PAGE_SIZE));
++ }
++ }
++
++ /* Return physical address. */
++ *Physical = (gctPHYS_ADDR) mdl;
++
++ /*
++ * Add this to a global list.
++ * Will be used by get physical address
++ * and mapuser pointer functions.
++ */
++ if (!Os->mdlHead)
++ {
++ /* Initialize the queue. */
++ Os->mdlHead = Os->mdlTail = mdl;
++ }
++ else
++ {
++ /* Add to tail. */
++ mdl->prev = Os->mdlTail;
++ Os->mdlTail->next = mdl;
++ Os->mdlTail = mdl;
++ }
++
++ MEMORY_UNLOCK(Os);
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Physical=0x%X", *Physical);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (mdl != gcvNULL)
++ {
++ /* Free the memory. */
++ _DestroyMdl(mdl);
++ }
++
++ if (locked)
++ {
++ /* Unlock the memory. */
++ MEMORY_UNLOCK(Os);
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_FreePagedMemory
++**
++** Free memory allocated from the paged pool.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPHYS_ADDR Physical
++** Physical address of the allocation.
++**
++** gctSIZE_T Bytes
++** Number of bytes of the allocation.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_FreePagedMemory(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes
++ )
++{
++ PLINUX_MDL mdl = (PLINUX_MDL) Physical;
++ gctINT i;
++
++ gcmkHEADER_ARG("Os=0x%X Physical=0x%X Bytes=%lu", Os, Physical, Bytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Physical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++
++ /*addr = mdl->addr;*/
++
++ MEMORY_LOCK(Os);
++
++ for (i = 0; i < mdl->numPages; i++)
++ {
++ if (mdl->contiguous)
++ {
++ ClearPageReserved(nth_page(mdl->u.contiguousPages, i));
++ }
++ else
++ {
++ ClearPageReserved(_NonContiguousToPage(mdl->u.nonContiguousPages, i));
++ }
++ }
++
++ if (mdl->contiguous)
++ {
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)
++ if (mdl->exact == gcvTRUE)
++ {
++ free_pages_exact(page_address(mdl->u.contiguousPages), mdl->numPages * PAGE_SIZE);
++ }
++ else
++#endif
++ {
++ __free_pages(mdl->u.contiguousPages, GetOrder(mdl->numPages));
++ }
++ }
++ else
++ {
++ _NonContiguousFree(mdl->u.nonContiguousPages, mdl->numPages);
++ }
++
++ /* Remove the node from global list. */
++ if (mdl == Os->mdlHead)
++ {
++ if ((Os->mdlHead = mdl->next) == gcvNULL)
++ {
++ Os->mdlTail = gcvNULL;
++ }
++ }
++ else
++ {
++ mdl->prev->next = mdl->next;
++
++ if (mdl == Os->mdlTail)
++ {
++ Os->mdlTail = mdl->prev;
++ }
++ else
++ {
++ mdl->next->prev = mdl->prev;
++ }
++ }
++
++ MEMORY_UNLOCK(Os);
++
++ /* Free the structure... */
++ gcmkVERIFY_OK(_DestroyMdl(mdl));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_LockPages
++**
++** Lock memory allocated from the paged pool.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPHYS_ADDR Physical
++** Physical address of the allocation.
++**
++** gctSIZE_T Bytes
++** Number of bytes of the allocation.
++**
++** gctBOOL Cacheable
++** Cache mode of mapping.
++**
++** OUTPUT:
++**
++** gctPOINTER * Logical
++** Pointer to a variable that receives the address of the mapped
++** memory.
++**
++** gctSIZE_T * PageCount
++** Pointer to a variable that receives the number of pages required for
++** the page table according to the GPU page size.
++*/
++gceSTATUS
++gckOS_LockPages(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ IN gctBOOL Cacheable,
++ OUT gctPOINTER * Logical,
++ OUT gctSIZE_T * PageCount
++ )
++{
++ PLINUX_MDL mdl;
++ PLINUX_MDL_MAP mdlMap;
++ gctSTRING addr;
++ unsigned long start;
++ unsigned long pfn;
++ gctINT i;
++
++ gcmkHEADER_ARG("Os=0x%X Physical=0x%X Bytes=%lu", Os, Physical, Logical);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Physical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(PageCount != gcvNULL);
++
++ mdl = (PLINUX_MDL) Physical;
++
++ MEMORY_LOCK(Os);
++
++ mdlMap = FindMdlMap(mdl, _GetProcessID());
++
++ if (mdlMap == gcvNULL)
++ {
++ mdlMap = _CreateMdlMap(mdl, _GetProcessID());
++
++ if (mdlMap == gcvNULL)
++ {
++ MEMORY_UNLOCK(Os);
++
++ gcmkFOOTER_ARG("*status=%d", gcvSTATUS_OUT_OF_MEMORY);
++ return gcvSTATUS_OUT_OF_MEMORY;
++ }
++ }
++
++ if (mdlMap->vmaAddr == gcvNULL)
++ {
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0)
++ mdlMap->vmaAddr = (gctSTRING)vm_mmap(gcvNULL,
++ 0L,
++ mdl->numPages * PAGE_SIZE,
++ PROT_READ | PROT_WRITE,
++ MAP_SHARED,
++ 0);
++#else
++ down_write(&current->mm->mmap_sem);
++
++ mdlMap->vmaAddr = (gctSTRING)do_mmap_pgoff(gcvNULL,
++ 0L,
++ mdl->numPages * PAGE_SIZE,
++ PROT_READ | PROT_WRITE,
++ MAP_SHARED,
++ 0);
++
++ up_write(&current->mm->mmap_sem);
++#endif
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): vmaAddr->0x%X for phys_addr->0x%X",
++ __FUNCTION__, __LINE__,
++ (gctUINT32)(gctUINTPTR_T)mdlMap->vmaAddr,
++ (gctUINT32)(gctUINTPTR_T)mdl
++ );
++
++ if (IS_ERR(mdlMap->vmaAddr))
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): do_mmap_pgoff error",
++ __FUNCTION__, __LINE__
++ );
++
++ mdlMap->vmaAddr = gcvNULL;
++
++ MEMORY_UNLOCK(Os);
++
++ gcmkFOOTER_ARG("*status=%d", gcvSTATUS_OUT_OF_MEMORY);
++ return gcvSTATUS_OUT_OF_MEMORY;
++ }
++
++ down_write(&current->mm->mmap_sem);
++
++ mdlMap->vma = find_vma(current->mm, (unsigned long)mdlMap->vmaAddr);
++
++ if (mdlMap->vma == gcvNULL)
++ {
++ up_write(&current->mm->mmap_sem);
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): find_vma error",
++ __FUNCTION__, __LINE__
++ );
++
++ mdlMap->vmaAddr = gcvNULL;
++
++ MEMORY_UNLOCK(Os);
++
++ gcmkFOOTER_ARG("*status=%d", gcvSTATUS_OUT_OF_RESOURCES);
++ return gcvSTATUS_OUT_OF_RESOURCES;
++ }
++
++ mdlMap->vma->vm_flags |= gcdVM_FLAGS;
++
++ if (Cacheable == gcvFALSE)
++ {
++ /* Make this mapping non-cached. */
++ mdlMap->vma->vm_page_prot = gcmkPAGED_MEMROY_PROT(mdlMap->vma->vm_page_prot);
++ }
++
++ addr = mdl->addr;
++
++ /* Now map all the vmalloc pages to this user address. */
++ if (mdl->contiguous)
++ {
++ /* map kernel memory to user space.. */
++ if (remap_pfn_range(mdlMap->vma,
++ mdlMap->vma->vm_start,
++ page_to_pfn(mdl->u.contiguousPages),
++ mdlMap->vma->vm_end - mdlMap->vma->vm_start,
++ mdlMap->vma->vm_page_prot) < 0)
++ {
++ up_write(&current->mm->mmap_sem);
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): unable to mmap ret",
++ __FUNCTION__, __LINE__
++ );
++
++ mdlMap->vmaAddr = gcvNULL;
++
++ MEMORY_UNLOCK(Os);
++
++ gcmkFOOTER_ARG("*status=%d", gcvSTATUS_OUT_OF_MEMORY);
++ return gcvSTATUS_OUT_OF_MEMORY;
++ }
++ }
++ else
++ {
++ start = mdlMap->vma->vm_start;
++
++ for (i = 0; i < mdl->numPages; i++)
++ {
++ pfn = _NonContiguousToPfn(mdl->u.nonContiguousPages, i);
++
++ if (remap_pfn_range(mdlMap->vma,
++ start,
++ pfn,
++ PAGE_SIZE,
++ mdlMap->vma->vm_page_prot) < 0)
++ {
++ up_write(&current->mm->mmap_sem);
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): gctPHYS_ADDR->0x%X Logical->0x%X Unable to map addr->0x%X to start->0x%X",
++ __FUNCTION__, __LINE__,
++ (gctUINT32)(gctUINTPTR_T)Physical,
++ (gctUINT32)(gctUINTPTR_T)*Logical,
++ (gctUINT32)(gctUINTPTR_T)addr,
++ (gctUINT32)(gctUINTPTR_T)start
++ );
++
++ mdlMap->vmaAddr = gcvNULL;
++
++ MEMORY_UNLOCK(Os);
++
++ gcmkFOOTER_ARG("*status=%d", gcvSTATUS_OUT_OF_MEMORY);
++ return gcvSTATUS_OUT_OF_MEMORY;
++ }
++
++ start += PAGE_SIZE;
++ addr += PAGE_SIZE;
++ }
++ }
++
++ up_write(&current->mm->mmap_sem);
++ }
++
++ mdlMap->count++;
++
++ /* Convert pointer to MDL. */
++ *Logical = mdlMap->vmaAddr;
++
++ /* Return the page number according to the GPU page size. */
++ gcmkASSERT((PAGE_SIZE % 4096) == 0);
++ gcmkASSERT((PAGE_SIZE / 4096) >= 1);
++
++ *PageCount = mdl->numPages * (PAGE_SIZE / 4096);
++
++ MEMORY_UNLOCK(Os);
++
++ gcmkVERIFY_OK(gckOS_CacheFlush(
++ Os,
++ _GetProcessID(),
++ Physical,
++ gcvNULL,
++ (gctPOINTER)mdlMap->vmaAddr,
++ mdl->numPages * PAGE_SIZE
++ ));
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Logical=0x%X *PageCount=%lu", *Logical, *PageCount);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_MapPages
++**
++** Map paged memory into a page table.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPHYS_ADDR Physical
++** Physical address of the allocation.
++**
++** gctSIZE_T PageCount
++** Number of pages required for the physical address.
++**
++** gctPOINTER PageTable
++** Pointer to the page table to fill in.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_MapPages(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T PageCount,
++ IN gctPOINTER PageTable
++ )
++{
++ return gckOS_MapPagesEx(Os,
++ gcvCORE_MAJOR,
++ Physical,
++ PageCount,
++ PageTable);
++}
++
++gceSTATUS
++gckOS_MapPagesEx(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T PageCount,
++ IN gctPOINTER PageTable
++ )
++{
++ gceSTATUS status = gcvSTATUS_OK;
++ PLINUX_MDL mdl;
++ gctUINT32* table;
++ gctUINT32 offset;
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ gckMMU mmu;
++ PLINUX_MDL mmuMdl;
++ gctUINT32 bytes;
++ gctPHYS_ADDR pageTablePhysical;
++#endif
++
++ gcmkHEADER_ARG("Os=0x%X Core=%d Physical=0x%X PageCount=%u PageTable=0x%X",
++ Os, Core, Physical, PageCount, PageTable);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Physical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(PageCount > 0);
++ gcmkVERIFY_ARGUMENT(PageTable != gcvNULL);
++
++ /* Convert pointer to MDL. */
++ mdl = (PLINUX_MDL)Physical;
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): Physical->0x%X PageCount->0x%X PagedMemory->?%d",
++ __FUNCTION__, __LINE__,
++ (gctUINT32)(gctUINTPTR_T)Physical,
++ (gctUINT32)(gctUINTPTR_T)PageCount,
++ mdl->pagedMem
++ );
++
++ MEMORY_LOCK(Os);
++
++ table = (gctUINT32 *)PageTable;
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ mmu = Os->device->kernels[Core]->mmu;
++ bytes = PageCount * sizeof(*table);
++ mmuMdl = (PLINUX_MDL)mmu->pageTablePhysical;
++#endif
++
++ /* Get all the physical addresses and store them in the page table. */
++
++ offset = 0;
++
++ if (mdl->pagedMem)
++ {
++ /* Try to get the user pages so DMA can happen. */
++ while (PageCount-- > 0)
++ {
++#if gcdENABLE_VG
++ if (Core == gcvCORE_VG)
++ {
++ if (mdl->contiguous)
++ {
++ gcmkONERROR(
++ gckVGMMU_SetPage(Os->device->kernels[Core]->vg->mmu,
++ page_to_phys(nth_page(mdl->u.contiguousPages, offset)),
++ table));
++ }
++ else
++ {
++ gcmkONERROR(
++ gckVGMMU_SetPage(Os->device->kernels[Core]->vg->mmu,
++ _NonContiguousToPhys(mdl->u.nonContiguousPages, offset),
++ table));
++ }
++ }
++ else
++#endif
++ {
++ if (mdl->contiguous)
++ {
++ gcmkONERROR(
++ gckMMU_SetPage(Os->device->kernels[Core]->mmu,
++ page_to_phys(nth_page(mdl->u.contiguousPages, offset)),
++ table));
++ }
++ else
++ {
++ gcmkONERROR(
++ gckMMU_SetPage(Os->device->kernels[Core]->mmu,
++ _NonContiguousToPhys(mdl->u.nonContiguousPages, offset),
++ table));
++ }
++ }
++
++ table++;
++ offset += 1;
++ }
++ }
++ else
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): we should not get this call for Non Paged Memory!",
++ __FUNCTION__, __LINE__
++ );
++
++ while (PageCount-- > 0)
++ {
++#if gcdENABLE_VG
++ if (Core == gcvCORE_VG)
++ {
++ gcmkONERROR(
++ gckVGMMU_SetPage(Os->device->kernels[Core]->vg->mmu,
++ page_to_phys(nth_page(mdl->u.contiguousPages, offset)),
++ table));
++ }
++ else
++#endif
++ {
++ gcmkONERROR(
++ gckMMU_SetPage(Os->device->kernels[Core]->mmu,
++ page_to_phys(nth_page(mdl->u.contiguousPages, offset)),
++ table));
++ }
++ table++;
++ offset += 1;
++ }
++ }
++
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ /* Get physical address of pageTable */
++ pageTablePhysical = (gctPHYS_ADDR)(mmuMdl->dmaHandle +
++ ((gctUINT32 *)PageTable - mmu->pageTableLogical));
++
++ /* Flush the mmu page table cache. */
++ gcmkONERROR(gckOS_CacheClean(
++ Os,
++ _GetProcessID(),
++ gcvNULL,
++ pageTablePhysical,
++ PageTable,
++ bytes
++ ));
++#endif
++
++OnError:
++
++ MEMORY_UNLOCK(Os);
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_UnlockPages
++**
++** Unlock memory allocated from the paged pool.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPHYS_ADDR Physical
++** Physical address of the allocation.
++**
++** gctSIZE_T Bytes
++** Number of bytes of the allocation.
++**
++** gctPOINTER Logical
++** Address of the mapped memory.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_UnlockPages(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ IN gctPOINTER Logical
++ )
++{
++ PLINUX_MDL_MAP mdlMap;
++ PLINUX_MDL mdl = (PLINUX_MDL)Physical;
++
++ gcmkHEADER_ARG("Os=0x%X Physical=0x%X Bytes=%u Logical=0x%X",
++ Os, Physical, Bytes, Logical);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Physical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++
++ /* Make sure there is already a mapping...*/
++ gcmkVERIFY_ARGUMENT(mdl->u.nonContiguousPages != gcvNULL
++ || mdl->u.contiguousPages != gcvNULL);
++
++ MEMORY_LOCK(Os);
++
++ mdlMap = mdl->maps;
++
++ while (mdlMap != gcvNULL)
++ {
++ if ((mdlMap->vmaAddr != gcvNULL) && (_GetProcessID() == mdlMap->pid))
++ {
++ if (--mdlMap->count == 0)
++ {
++ _UnmapUserLogical(mdlMap->pid, mdlMap->vmaAddr, mdl->numPages * PAGE_SIZE);
++ mdlMap->vmaAddr = gcvNULL;
++ }
++ }
++
++ mdlMap = mdlMap->next;
++ }
++
++ MEMORY_UNLOCK(Os);
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++
++/*******************************************************************************
++**
++** gckOS_AllocateContiguous
++**
++** Allocate memory from the contiguous pool.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctBOOL InUserSpace
++** gcvTRUE if the pages need to be mapped into user space.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes to allocate.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that receives the number of bytes allocated.
++**
++** gctPHYS_ADDR * Physical
++** Pointer to a variable that receives the physical address of the
++** memory allocation.
++**
++** gctPOINTER * Logical
++** Pointer to a variable that receives the logical address of the
++** memory allocation.
++*/
++gceSTATUS
++gckOS_AllocateContiguous(
++ IN gckOS Os,
++ IN gctBOOL InUserSpace,
++ IN OUT gctSIZE_T * Bytes,
++ OUT gctPHYS_ADDR * Physical,
++ OUT gctPOINTER * Logical
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%X InUserSpace=%d *Bytes=%lu",
++ Os, InUserSpace, gcmOPT_VALUE(Bytes));
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Bytes != gcvNULL);
++ gcmkVERIFY_ARGUMENT(*Bytes > 0);
++ gcmkVERIFY_ARGUMENT(Physical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++
++ /* Same as non-paged memory for now. */
++ gcmkONERROR(gckOS_AllocateNonPagedMemory(Os,
++ InUserSpace,
++ Bytes,
++ Physical,
++ Logical));
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Bytes=%lu *Physical=0x%X *Logical=0x%X",
++ *Bytes, *Physical, *Logical);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_FreeContiguous
++**
++** Free memory allocated from the contiguous pool.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPHYS_ADDR Physical
++** Physical address of the allocation.
++**
++** gctPOINTER Logical
++** Logicval address of the allocation.
++**
++** gctSIZE_T Bytes
++** Number of bytes of the allocation.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_FreeContiguous(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%X Physical=0x%X Logical=0x%X Bytes=%lu",
++ Os, Physical, Logical, Bytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Physical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++
++ /* Same of non-paged memory for now. */
++ gcmkONERROR(gckOS_FreeNonPagedMemory(Os, Bytes, Physical, Logical));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++#if gcdENABLE_VG
++/******************************************************************************
++**
++** gckOS_GetKernelLogical
++**
++** Return the kernel logical pointer that corresponods to the specified
++** hardware address.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctUINT32 Address
++** Hardware physical address.
++**
++** OUTPUT:
++**
++** gctPOINTER * KernelPointer
++** Pointer to a variable receiving the pointer in kernel address space.
++*/
++gceSTATUS
++gckOS_GetKernelLogical(
++ IN gckOS Os,
++ IN gctUINT32 Address,
++ OUT gctPOINTER * KernelPointer
++ )
++{
++ return gckOS_GetKernelLogicalEx(Os, gcvCORE_MAJOR, Address, KernelPointer);
++}
++
++gceSTATUS
++gckOS_GetKernelLogicalEx(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctUINT32 Address,
++ OUT gctPOINTER * KernelPointer
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%X Core=%d Address=0x%08x", Os, Core, Address);
++
++ do
++ {
++ gckGALDEVICE device;
++ gckKERNEL kernel;
++ gcePOOL pool;
++ gctUINT32 offset;
++ gctPOINTER logical;
++
++ /* Extract the pointer to the gckGALDEVICE class. */
++ device = (gckGALDEVICE) Os->device;
++
++ /* Kernel shortcut. */
++ kernel = device->kernels[Core];
++#if gcdENABLE_VG
++ if (Core == gcvCORE_VG)
++ {
++ gcmkERR_BREAK(gckVGHARDWARE_SplitMemory(
++ kernel->vg->hardware, Address, &pool, &offset
++ ));
++ }
++ else
++#endif
++ {
++ /* Split the memory address into a pool type and offset. */
++ gcmkERR_BREAK(gckHARDWARE_SplitMemory(
++ kernel->hardware, Address, &pool, &offset
++ ));
++ }
++
++ /* Dispatch on pool. */
++ switch (pool)
++ {
++ case gcvPOOL_LOCAL_INTERNAL:
++ /* Internal memory. */
++ logical = device->internalLogical;
++ break;
++
++ case gcvPOOL_LOCAL_EXTERNAL:
++ /* External memory. */
++ logical = device->externalLogical;
++ break;
++
++ case gcvPOOL_SYSTEM:
++ /* System memory. */
++ logical = device->contiguousBase;
++ break;
++
++ default:
++ /* Invalid memory pool. */
++ gcmkFOOTER();
++ return gcvSTATUS_INVALID_ARGUMENT;
++ }
++
++ /* Build logical address of specified address. */
++ * KernelPointer = ((gctUINT8_PTR) logical) + offset;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*KernelPointer=0x%X", *KernelPointer);
++ return gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ /* Return status. */
++ gcmkFOOTER();
++ return status;
++}
++#endif
++
++/*******************************************************************************
++**
++** gckOS_MapUserPointer
++**
++** Map a pointer from the user process into the kernel address space.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPOINTER Pointer
++** Pointer in user process space that needs to be mapped.
++**
++** gctSIZE_T Size
++** Number of bytes that need to be mapped.
++**
++** OUTPUT:
++**
++** gctPOINTER * KernelPointer
++** Pointer to a variable receiving the mapped pointer in kernel address
++** space.
++*/
++gceSTATUS
++gckOS_MapUserPointer(
++ IN gckOS Os,
++ IN gctPOINTER Pointer,
++ IN gctSIZE_T Size,
++ OUT gctPOINTER * KernelPointer
++ )
++{
++ gctPOINTER buf = gcvNULL;
++ gctUINT32 len;
++
++ gcmkHEADER_ARG("Os=0x%X Pointer=0x%X Size=%lu", Os, Pointer, Size);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Pointer != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Size > 0);
++ gcmkVERIFY_ARGUMENT(KernelPointer != gcvNULL);
++
++ buf = kmalloc(Size, GFP_KERNEL | gcdNOWARN);
++ if (buf == gcvNULL)
++ {
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): Failed to allocate memory.",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkFOOTER_ARG("*status=%d", gcvSTATUS_OUT_OF_MEMORY);
++ return gcvSTATUS_OUT_OF_MEMORY;
++ }
++
++ len = copy_from_user(buf, Pointer, Size);
++ if (len != 0)
++ {
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): Failed to copy data from user.",
++ __FUNCTION__, __LINE__
++ );
++
++ if (buf != gcvNULL)
++ {
++ kfree(buf);
++ }
++
++ gcmkFOOTER_ARG("*status=%d", gcvSTATUS_GENERIC_IO);
++ return gcvSTATUS_GENERIC_IO;
++ }
++
++ *KernelPointer = buf;
++
++ gcmkFOOTER_ARG("*KernelPointer=0x%X", *KernelPointer);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_UnmapUserPointer
++**
++** Unmap a user process pointer from the kernel address space.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPOINTER Pointer
++** Pointer in user process space that needs to be unmapped.
++**
++** gctSIZE_T Size
++** Number of bytes that need to be unmapped.
++**
++** gctPOINTER KernelPointer
++** Pointer in kernel address space that needs to be unmapped.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_UnmapUserPointer(
++ IN gckOS Os,
++ IN gctPOINTER Pointer,
++ IN gctSIZE_T Size,
++ IN gctPOINTER KernelPointer
++ )
++{
++ gctUINT32 len;
++
++ gcmkHEADER_ARG("Os=0x%X Pointer=0x%X Size=%lu KernelPointer=0x%X",
++ Os, Pointer, Size, KernelPointer);
++
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Pointer != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Size > 0);
++ gcmkVERIFY_ARGUMENT(KernelPointer != gcvNULL);
++
++ len = copy_to_user(Pointer, KernelPointer, Size);
++
++ kfree(KernelPointer);
++
++ if (len != 0)
++ {
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): Failed to copy data to user.",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkFOOTER_ARG("status=%d", gcvSTATUS_GENERIC_IO);
++ return gcvSTATUS_GENERIC_IO;
++ }
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_QueryNeedCopy
++**
++** Query whether the memory can be accessed or mapped directly or it has to be
++** copied.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctUINT32 ProcessID
++** Process ID of the current process.
++**
++** OUTPUT:
++**
++** gctBOOL_PTR NeedCopy
++** Pointer to a boolean receiving gcvTRUE if the memory needs a copy or
++** gcvFALSE if the memory can be accessed or mapped dircetly.
++*/
++gceSTATUS
++gckOS_QueryNeedCopy(
++ IN gckOS Os,
++ IN gctUINT32 ProcessID,
++ OUT gctBOOL_PTR NeedCopy
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X ProcessID=%d", Os, ProcessID);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(NeedCopy != gcvNULL);
++
++ /* We need to copy data. */
++ *NeedCopy = gcvTRUE;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*NeedCopy=%d", *NeedCopy);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_CopyFromUserData
++**
++** Copy data from user to kernel memory.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPOINTER KernelPointer
++** Pointer to kernel memory.
++**
++** gctPOINTER Pointer
++** Pointer to user memory.
++**
++** gctSIZE_T Size
++** Number of bytes to copy.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_CopyFromUserData(
++ IN gckOS Os,
++ IN gctPOINTER KernelPointer,
++ IN gctPOINTER Pointer,
++ IN gctSIZE_T Size
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%X KernelPointer=0x%X Pointer=0x%X Size=%lu",
++ Os, KernelPointer, Pointer, Size);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(KernelPointer != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Pointer != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Size > 0);
++
++ /* Copy data from user. */
++ if (copy_from_user(KernelPointer, Pointer, Size) != 0)
++ {
++ /* Could not copy all the bytes. */
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_CopyToUserData
++**
++** Copy data from kernel to user memory.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPOINTER KernelPointer
++** Pointer to kernel memory.
++**
++** gctPOINTER Pointer
++** Pointer to user memory.
++**
++** gctSIZE_T Size
++** Number of bytes to copy.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_CopyToUserData(
++ IN gckOS Os,
++ IN gctPOINTER KernelPointer,
++ IN gctPOINTER Pointer,
++ IN gctSIZE_T Size
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%X KernelPointer=0x%X Pointer=0x%X Size=%lu",
++ Os, KernelPointer, Pointer, Size);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(KernelPointer != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Pointer != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Size > 0);
++
++ /* Copy data to user. */
++ if (copy_to_user(Pointer, KernelPointer, Size) != 0)
++ {
++ /* Could not copy all the bytes. */
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_WriteMemory
++**
++** Write data to a memory.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPOINTER Address
++** Address of the memory to write to.
++**
++** gctUINT32 Data
++** Data for register.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_WriteMemory(
++ IN gckOS Os,
++ IN gctPOINTER Address,
++ IN gctUINT32 Data
++ )
++{
++ gceSTATUS status;
++ gcmkHEADER_ARG("Os=0x%X Address=0x%X Data=%u", Os, Address, Data);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_ARGUMENT(Address != gcvNULL);
++
++ /* Write memory. */
++ if (access_ok(VERIFY_WRITE, Address, 4))
++ {
++ /* User address. */
++ if(put_user(Data, (gctUINT32*)Address))
++ {
++ gcmkONERROR(gcvSTATUS_INVALID_ADDRESS);
++ }
++ }
++ else
++ {
++ /* Kernel address. */
++ *(gctUINT32 *)Address = Data;
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_MapUserMemory
++**
++** Lock down a user buffer and return an DMA'able address to be used by the
++** hardware to access it.
++**
++** INPUT:
++**
++** gctPOINTER Memory
++** Pointer to memory to lock down.
++**
++** gctSIZE_T Size
++** Size in bytes of the memory to lock down.
++**
++** OUTPUT:
++**
++** gctPOINTER * Info
++** Pointer to variable receiving the information record required by
++** gckOS_UnmapUserMemory.
++**
++** gctUINT32_PTR Address
++** Pointer to a variable that will receive the address DMA'able by the
++** hardware.
++*/
++gceSTATUS
++gckOS_MapUserMemory(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctPOINTER Memory,
++ IN gctUINT32 Physical,
++ IN gctSIZE_T Size,
++ OUT gctPOINTER * Info,
++ OUT gctUINT32_PTR Address
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%x Core=%d Memory=0x%x Size=%lu", Os, Core, Memory, Size);
++
++#if gcdSECURE_USER
++ gcmkONERROR(gckOS_AddMapping(Os, *Address, Memory, Size));
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++#else
++{
++ gctSIZE_T pageCount, i, j;
++ gctUINT32_PTR pageTable;
++ gctUINT32 address = 0, physical = ~0U;
++ gctUINTPTR_T start, end, memory;
++ gctUINT32 offset;
++ gctINT result = 0;
++
++ gcsPageInfo_PTR info = gcvNULL;
++ struct page **pages = gcvNULL;
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Memory != gcvNULL || Physical != ~0U);
++ gcmkVERIFY_ARGUMENT(Size > 0);
++ gcmkVERIFY_ARGUMENT(Info != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Address != gcvNULL);
++
++ do
++ {
++ memory = (gctUINTPTR_T) Memory;
++
++ /* Get the number of required pages. */
++ end = (memory + Size + PAGE_SIZE - 1) >> PAGE_SHIFT;
++ start = memory >> PAGE_SHIFT;
++ pageCount = end - start;
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): pageCount: %d.",
++ __FUNCTION__, __LINE__,
++ pageCount
++ );
++
++ /* Overflow. */
++ if ((memory + Size) < memory)
++ {
++ gcmkFOOTER_ARG("status=%d", gcvSTATUS_INVALID_ARGUMENT);
++ return gcvSTATUS_INVALID_ARGUMENT;
++ }
++
++ MEMORY_MAP_LOCK(Os);
++
++ /* Allocate the Info struct. */
++ info = (gcsPageInfo_PTR)kmalloc(sizeof(gcsPageInfo), GFP_KERNEL | gcdNOWARN);
++
++ if (info == gcvNULL)
++ {
++ status = gcvSTATUS_OUT_OF_MEMORY;
++ break;
++ }
++
++ /* Allocate the array of page addresses. */
++ pages = (struct page **)kmalloc(pageCount * sizeof(struct page *), GFP_KERNEL | gcdNOWARN);
++
++ if (pages == gcvNULL)
++ {
++ status = gcvSTATUS_OUT_OF_MEMORY;
++ break;
++ }
++
++ if (Physical != ~0U)
++ {
++ for (i = 0; i < pageCount; i++)
++ {
++ pages[i] = pfn_to_page((Physical >> PAGE_SHIFT) + i);
++ get_page(pages[i]);
++ }
++ }
++ else
++ {
++ /* Get the user pages. */
++ down_read(&current->mm->mmap_sem);
++
++ result = get_user_pages(current,
++ current->mm,
++ memory & PAGE_MASK,
++ pageCount,
++ 1,
++ 0,
++ pages,
++ gcvNULL
++ );
++
++ up_read(&current->mm->mmap_sem);
++
++ if (result <=0 || result < pageCount)
++ {
++ struct vm_area_struct *vma;
++
++ /* Release the pages if any. */
++ if (result > 0)
++ {
++ for (i = 0; i < result; i++)
++ {
++ if (pages[i] == gcvNULL)
++ {
++ break;
++ }
++
++ page_cache_release(pages[i]);
++ pages[i] = gcvNULL;
++ }
++
++ result = 0;
++ }
++
++ vma = find_vma(current->mm, memory);
++
++ if (vma && (vma->vm_flags & VM_PFNMAP))
++ {
++ pte_t * pte;
++ spinlock_t * ptl;
++ gctUINTPTR_T logical = memory;
++
++ for (i = 0; i < pageCount; i++)
++ {
++ pgd_t * pgd = pgd_offset(current->mm, logical);
++ pud_t * pud = pud_offset(pgd, logical);
++
++ if (pud)
++ {
++ pmd_t * pmd = pmd_offset(pud, logical);
++ pte = pte_offset_map_lock(current->mm, pmd, logical, &ptl);
++ if (!pte)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++ }
++ else
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++ pages[i] = pte_page(*pte);
++ pte_unmap_unlock(pte, ptl);
++
++ /* Advance to next. */
++ logical += PAGE_SIZE;
++ }
++ }
++ else
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++ /* Check if this memory is contiguous for old mmu. */
++ if (Os->device->kernels[Core]->hardware->mmuVersion == 0)
++ {
++ for (i = 1; i < pageCount; i++)
++ {
++ if (pages[i] != nth_page(pages[0], i))
++ {
++ /* Non-contiguous. */
++ break;
++ }
++ }
++
++ if (i == pageCount)
++ {
++ /* Contiguous memory. */
++ physical = page_to_phys(pages[0]) | (memory & ~PAGE_MASK);
++
++ if (!((physical - Os->device->baseAddress) & 0x80000000))
++ {
++ kfree(pages);
++ pages = gcvNULL;
++
++ info->pages = gcvNULL;
++ info->pageTable = gcvNULL;
++
++ MEMORY_MAP_UNLOCK(Os);
++
++ *Address = physical - Os->device->baseAddress;
++ *Info = info;
++
++ gcmkFOOTER_ARG("*Info=0x%X *Address=0x%08x",
++ *Info, *Address);
++
++ return gcvSTATUS_OK;
++ }
++ }
++ }
++
++ /* Reference pages. */
++ for (i = 0; i < pageCount; i++)
++ {
++ get_page(pages[i]);
++ }
++ }
++ }
++
++ for (i = 0; i < pageCount; i++)
++ {
++#ifdef CONFIG_ARM
++ gctUINT32 data;
++ get_user(data, (gctUINT32*)((memory & PAGE_MASK) + i * PAGE_SIZE));
++#endif
++
++ /* Flush(clean) the data cache. */
++ gcmkONERROR(gckOS_CacheFlush(Os, _GetProcessID(), gcvNULL,
++ (gctPOINTER)(gctUINTPTR_T)page_to_phys(pages[i]),
++ (gctPOINTER)(memory & PAGE_MASK) + i*PAGE_SIZE,
++ PAGE_SIZE));
++ }
++
++#if gcdENABLE_VG
++ if (Core == gcvCORE_VG)
++ {
++ /* Allocate pages inside the page table. */
++ gcmkERR_BREAK(gckVGMMU_AllocatePages(Os->device->kernels[Core]->vg->mmu,
++ pageCount * (PAGE_SIZE/4096),
++ (gctPOINTER *) &pageTable,
++ &address));
++ }
++ else
++#endif
++ {
++ /* Allocate pages inside the page table. */
++ gcmkERR_BREAK(gckMMU_AllocatePages(Os->device->kernels[Core]->mmu,
++ pageCount * (PAGE_SIZE/4096),
++ (gctPOINTER *) &pageTable,
++ &address));
++ }
++
++ /* Fill the page table. */
++ for (i = 0; i < pageCount; i++)
++ {
++ gctUINT32 phys;
++ gctUINT32_PTR tab = pageTable + i * (PAGE_SIZE/4096);
++
++ phys = page_to_phys(pages[i]);
++
++#if gcdENABLE_VG
++ if (Core == gcvCORE_VG)
++ {
++ /* Get the physical address from page struct. */
++ gcmkONERROR(
++ gckVGMMU_SetPage(Os->device->kernels[Core]->vg->mmu,
++ phys,
++ tab));
++ }
++ else
++#endif
++ {
++ /* Get the physical address from page struct. */
++ gcmkONERROR(
++ gckMMU_SetPage(Os->device->kernels[Core]->mmu,
++ phys,
++ tab));
++ }
++
++ for (j = 1; j < (PAGE_SIZE/4096); j++)
++ {
++ pageTable[i * (PAGE_SIZE/4096) + j] = pageTable[i * (PAGE_SIZE/4096)] + 4096 * j;
++ }
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): pageTable[%d]: 0x%X 0x%X.",
++ __FUNCTION__, __LINE__,
++ i, phys, pageTable[i]);
++ }
++
++#if gcdENABLE_VG
++ if (Core == gcvCORE_VG)
++ {
++ gcmkONERROR(gckVGMMU_Flush(Os->device->kernels[Core]->vg->mmu));
++ }
++ else
++#endif
++ {
++ gcmkONERROR(gckMMU_Flush(Os->device->kernels[Core]->mmu));
++ }
++
++ /* Save pointer to page table. */
++ info->pageTable = pageTable;
++ info->pages = pages;
++
++ *Info = (gctPOINTER) info;
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): info->pages: 0x%X, info->pageTable: 0x%X, info: 0x%X.",
++ __FUNCTION__, __LINE__,
++ info->pages,
++ info->pageTable,
++ info
++ );
++
++ offset = (Physical != ~0U)
++ ? (Physical & ~PAGE_MASK)
++ : (memory & ~PAGE_MASK);
++
++ /* Return address. */
++ *Address = address + offset;
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): Address: 0x%X.",
++ __FUNCTION__, __LINE__,
++ *Address
++ );
++
++ /* Success. */
++ status = gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++OnError:
++
++ if (gcmIS_ERROR(status))
++ {
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): error occured: %d.",
++ __FUNCTION__, __LINE__,
++ status
++ );
++
++ /* Release page array. */
++ if (result > 0 && pages != gcvNULL)
++ {
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): error: page table is freed.",
++ __FUNCTION__, __LINE__
++ );
++
++ for (i = 0; i < result; i++)
++ {
++ if (pages[i] == gcvNULL)
++ {
++ break;
++ }
++ page_cache_release(pages[i]);
++ }
++ }
++
++ if (info!= gcvNULL && pages != gcvNULL)
++ {
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): error: pages is freed.",
++ __FUNCTION__, __LINE__
++ );
++
++ /* Free the page table. */
++ kfree(pages);
++ info->pages = gcvNULL;
++ }
++
++ /* Release page info struct. */
++ if (info != gcvNULL)
++ {
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): error: info is freed.",
++ __FUNCTION__, __LINE__
++ );
++
++ /* Free the page info struct. */
++ kfree(info);
++ *Info = gcvNULL;
++ }
++ }
++
++ MEMORY_MAP_UNLOCK(Os);
++
++ /* Return the status. */
++ if (gcmIS_SUCCESS(status))
++ {
++ gcmkFOOTER_ARG("*Info=0x%X *Address=0x%08x", *Info, *Address);
++ }
++ else
++ {
++ gcmkFOOTER();
++ }
++
++ return status;
++}
++#endif
++}
++
++/*******************************************************************************
++**
++** gckOS_UnmapUserMemory
++**
++** Unlock a user buffer and that was previously locked down by
++** gckOS_MapUserMemory.
++**
++** INPUT:
++**
++** gctPOINTER Memory
++** Pointer to memory to unlock.
++**
++** gctSIZE_T Size
++** Size in bytes of the memory to unlock.
++**
++** gctPOINTER Info
++** Information record returned by gckOS_MapUserMemory.
++**
++** gctUINT32_PTR Address
++** The address returned by gckOS_MapUserMemory.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_UnmapUserMemory(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctPOINTER Memory,
++ IN gctSIZE_T Size,
++ IN gctPOINTER Info,
++ IN gctUINT32 Address
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%X Core=%d Memory=0x%X Size=%lu Info=0x%X Address0x%08x",
++ Os, Core, Memory, Size, Info, Address);
++
++#if gcdSECURE_USER
++ gcmkONERROR(gckOS_RemoveMapping(Os, Memory, Size));
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++#else
++{
++ gctUINTPTR_T memory, start, end;
++ gcsPageInfo_PTR info;
++ gctSIZE_T pageCount, i;
++ struct page **pages;
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Memory != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Size > 0);
++ gcmkVERIFY_ARGUMENT(Info != gcvNULL);
++
++ do
++ {
++ info = (gcsPageInfo_PTR) Info;
++
++ pages = info->pages;
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): info=0x%X, pages=0x%X.",
++ __FUNCTION__, __LINE__,
++ info, pages
++ );
++
++ /* Invalid page array. */
++ if (pages == gcvNULL && info->pageTable == gcvNULL)
++ {
++ kfree(info);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++
++ memory = (gctUINTPTR_T)Memory;
++ end = (memory + Size + PAGE_SIZE - 1) >> PAGE_SHIFT;
++ start = memory >> PAGE_SHIFT;
++ pageCount = end - start;
++
++ /* Overflow. */
++ if ((memory + Size) < memory)
++ {
++ gcmkFOOTER_ARG("status=%d", gcvSTATUS_INVALID_ARGUMENT);
++ return gcvSTATUS_INVALID_ARGUMENT;
++ }
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): memory: 0x%X, pageCount: %d, pageTable: 0x%X.",
++ __FUNCTION__, __LINE__,
++ memory, pageCount, info->pageTable
++ );
++
++ MEMORY_MAP_LOCK(Os);
++
++ gcmkASSERT(info->pageTable != gcvNULL);
++
++#if gcdENABLE_VG
++ if (Core == gcvCORE_VG)
++ {
++ /* Free the pages from the MMU. */
++ gcmkERR_BREAK(gckVGMMU_FreePages(Os->device->kernels[Core]->vg->mmu,
++ info->pageTable,
++ pageCount * (PAGE_SIZE/4096)
++ ));
++ }
++ else
++#endif
++ {
++ /* Free the pages from the MMU. */
++ gcmkERR_BREAK(gckMMU_FreePages(Os->device->kernels[Core]->mmu,
++ info->pageTable,
++ pageCount * (PAGE_SIZE/4096)
++ ));
++ }
++
++ /* Release the page cache. */
++ if (pages)
++ {
++ for (i = 0; i < pageCount; i++)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): pages[%d]: 0x%X.",
++ __FUNCTION__, __LINE__,
++ i, pages[i]
++ );
++
++ if (!PageReserved(pages[i]))
++ {
++ SetPageDirty(pages[i]);
++ }
++
++ page_cache_release(pages[i]);
++ }
++ }
++
++ /* Success. */
++ status = gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ if (info != gcvNULL)
++ {
++ /* Free the page array. */
++ if (info->pages != gcvNULL)
++ {
++ kfree(info->pages);
++ }
++
++ kfree(info);
++ }
++
++ MEMORY_MAP_UNLOCK(Os);
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++#endif
++}
++
++/*******************************************************************************
++**
++** gckOS_GetBaseAddress
++**
++** Get the base address for the physical memory.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to the gckOS object.
++**
++** OUTPUT:
++**
++** gctUINT32_PTR BaseAddress
++** Pointer to a variable that will receive the base address.
++*/
++gceSTATUS
++gckOS_GetBaseAddress(
++ IN gckOS Os,
++ OUT gctUINT32_PTR BaseAddress
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X", Os);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(BaseAddress != gcvNULL);
++
++ /* Return base address. */
++ *BaseAddress = Os->device->baseAddress;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*BaseAddress=0x%08x", *BaseAddress);
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckOS_SuspendInterrupt(
++ IN gckOS Os
++ )
++{
++ return gckOS_SuspendInterruptEx(Os, gcvCORE_MAJOR);
++}
++
++gceSTATUS
++gckOS_SuspendInterruptEx(
++ IN gckOS Os,
++ IN gceCORE Core
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Core=%d", Os, Core);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++
++ disable_irq(Os->device->irqLines[Core]);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckOS_ResumeInterrupt(
++ IN gckOS Os
++ )
++{
++ return gckOS_ResumeInterruptEx(Os, gcvCORE_MAJOR);
++}
++
++gceSTATUS
++gckOS_ResumeInterruptEx(
++ IN gckOS Os,
++ IN gceCORE Core
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Core=%d", Os, Core);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++
++ enable_irq(Os->device->irqLines[Core]);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckOS_MemCopy(
++ IN gctPOINTER Destination,
++ IN gctCONST_POINTER Source,
++ IN gctSIZE_T Bytes
++ )
++{
++ gcmkHEADER_ARG("Destination=0x%X Source=0x%X Bytes=%lu",
++ Destination, Source, Bytes);
++
++ gcmkVERIFY_ARGUMENT(Destination != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Source != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++
++ memcpy(Destination, Source, Bytes);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckOS_ZeroMemory(
++ IN gctPOINTER Memory,
++ IN gctSIZE_T Bytes
++ )
++{
++ gcmkHEADER_ARG("Memory=0x%X Bytes=%lu", Memory, Bytes);
++
++ gcmkVERIFY_ARGUMENT(Memory != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++
++ memset(Memory, 0, Bytes);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++********************************* Cache Control ********************************
++*******************************************************************************/
++
++#if !gcdCACHE_FUNCTION_UNIMPLEMENTED && defined(CONFIG_OUTER_CACHE)
++static inline gceSTATUS
++outer_func(
++ gceCACHEOPERATION Type,
++ unsigned long Start,
++ unsigned long End
++ )
++{
++ switch (Type)
++ {
++ case gcvCACHE_CLEAN:
++ outer_clean_range(Start, End);
++ break;
++ case gcvCACHE_INVALIDATE:
++ outer_inv_range(Start, End);
++ break;
++ case gcvCACHE_FLUSH:
++ outer_flush_range(Start, End);
++ break;
++ default:
++ return gcvSTATUS_INVALID_ARGUMENT;
++ break;
++ }
++ return gcvSTATUS_OK;
++}
++
++#if gcdENABLE_OUTER_CACHE_PATCH
++/*******************************************************************************
++** _HandleOuterCache
++**
++** Handle the outer cache for the specified addresses.
++**
++** ARGUMENTS:
++**
++** gckOS Os
++** Pointer to gckOS object.
++**
++** gctUINT32 ProcessID
++** Process ID Logical belongs.
++**
++** gctPHYS_ADDR Handle
++** Physical address handle. If gcvNULL it is video memory.
++**
++** gctPOINTER Physical
++** Physical address to flush.
++**
++** gctPOINTER Logical
++** Logical address to flush.
++**
++** gctSIZE_T Bytes
++** Size of the address range in bytes to flush.
++**
++** gceOUTERCACHE_OPERATION Type
++** Operation need to be execute.
++*/
++static gceSTATUS
++_HandleOuterCache(
++ IN gckOS Os,
++ IN gctUINT32 ProcessID,
++ IN gctPHYS_ADDR Handle,
++ IN gctPOINTER Physical,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes,
++ IN gceCACHEOPERATION Type
++ )
++{
++ gceSTATUS status;
++ gctUINT32 i, pageNum;
++ unsigned long paddr;
++ gctPOINTER vaddr;
++
++ gcmkHEADER_ARG("Os=0x%X ProcessID=%d Handle=0x%X Logical=0x%X Bytes=%lu",
++ Os, ProcessID, Handle, Logical, Bytes);
++
++ if (Physical != gcvNULL)
++ {
++ /* Non paged memory or gcvPOOL_USER surface */
++ paddr = (unsigned long) Physical;
++ gcmkONERROR(outer_func(Type, paddr, paddr + Bytes));
++ }
++ else if ((Handle == gcvNULL)
++ || (Handle != gcvNULL && ((PLINUX_MDL)Handle)->contiguous)
++ )
++ {
++ /* Video Memory or contiguous virtual memory */
++ gcmkONERROR(gckOS_GetPhysicalAddress(Os, Logical, (gctUINT32*)&paddr));
++ gcmkONERROR(outer_func(Type, paddr, paddr + Bytes));
++ }
++ else
++ {
++ /* Non contiguous virtual memory */
++ vaddr = (gctPOINTER)gcmALIGN_BASE((gctUINTPTR_T)Logical, PAGE_SIZE);
++ pageNum = GetPageCount(Bytes, 0);
++
++ for (i = 0; i < pageNum; i += 1)
++ {
++ gcmkONERROR(_ConvertLogical2Physical(
++ Os,
++ vaddr + PAGE_SIZE * i,
++ ProcessID,
++ (PLINUX_MDL)Handle,
++ (gctUINT32*)&paddr
++ ));
++
++ gcmkONERROR(outer_func(Type, paddr, paddr + PAGE_SIZE));
++ }
++ }
++
++ mb();
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++#endif
++#endif
++
++/*******************************************************************************
++** gckOS_CacheClean
++**
++** Clean the cache for the specified addresses. The GPU is going to need the
++** data. If the system is allocating memory as non-cachable, this function can
++** be ignored.
++**
++** ARGUMENTS:
++**
++** gckOS Os
++** Pointer to gckOS object.
++**
++** gctUINT32 ProcessID
++** Process ID Logical belongs.
++**
++** gctPHYS_ADDR Handle
++** Physical address handle. If gcvNULL it is video memory.
++**
++** gctPOINTER Physical
++** Physical address to flush.
++**
++** gctPOINTER Logical
++** Logical address to flush.
++**
++** gctSIZE_T Bytes
++** Size of the address range in bytes to flush.
++*/
++gceSTATUS
++gckOS_CacheClean(
++ IN gckOS Os,
++ IN gctUINT32 ProcessID,
++ IN gctPHYS_ADDR Handle,
++ IN gctPOINTER Physical,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X ProcessID=%d Handle=0x%X Logical=0x%X Bytes=%lu",
++ Os, ProcessID, Handle, Logical, Bytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++
++#if !gcdCACHE_FUNCTION_UNIMPLEMENTED
++#ifdef CONFIG_ARM
++
++ /* Inner cache. */
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35)
++ dmac_map_area(Logical, Bytes, DMA_TO_DEVICE);
++# else
++ dmac_clean_range(Logical, Logical + Bytes);
++# endif
++
++#if defined(CONFIG_OUTER_CACHE)
++ /* Outer cache. */
++#if gcdENABLE_OUTER_CACHE_PATCH
++ _HandleOuterCache(Os, ProcessID, Handle, Physical, Logical, Bytes, gcvCACHE_CLEAN);
++#else
++ outer_clean_range((unsigned long) Handle, (unsigned long) Handle + Bytes);
++#endif
++#endif
++
++#elif defined(CONFIG_MIPS)
++
++ dma_cache_wback((unsigned long) Logical, Bytes);
++
++#elif defined(CONFIG_PPC)
++
++ /* TODO */
++
++#else
++ dma_sync_single_for_device(
++ gcvNULL,
++ (dma_addr_t)Physical,
++ Bytes,
++ DMA_TO_DEVICE);
++#endif
++#endif
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++** gckOS_CacheInvalidate
++**
++** Invalidate the cache for the specified addresses. The GPU is going to need
++** data. If the system is allocating memory as non-cachable, this function can
++** be ignored.
++**
++** ARGUMENTS:
++**
++** gckOS Os
++** Pointer to gckOS object.
++**
++** gctUINT32 ProcessID
++** Process ID Logical belongs.
++**
++** gctPHYS_ADDR Handle
++** Physical address handle. If gcvNULL it is video memory.
++**
++** gctPOINTER Logical
++** Logical address to flush.
++**
++** gctSIZE_T Bytes
++** Size of the address range in bytes to flush.
++*/
++gceSTATUS
++gckOS_CacheInvalidate(
++ IN gckOS Os,
++ IN gctUINT32 ProcessID,
++ IN gctPHYS_ADDR Handle,
++ IN gctPOINTER Physical,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X ProcessID=%d Handle=0x%X Logical=0x%X Bytes=%lu",
++ Os, ProcessID, Handle, Logical, Bytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++
++#if !gcdCACHE_FUNCTION_UNIMPLEMENTED
++#ifdef CONFIG_ARM
++
++ /* Inner cache. */
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35)
++ dmac_map_area(Logical, Bytes, DMA_FROM_DEVICE);
++# else
++ dmac_inv_range(Logical, Logical + Bytes);
++# endif
++
++#if defined(CONFIG_OUTER_CACHE)
++ /* Outer cache. */
++#if gcdENABLE_OUTER_CACHE_PATCH
++ _HandleOuterCache(Os, ProcessID, Handle, Physical, Logical, Bytes, gcvCACHE_INVALIDATE);
++#else
++ outer_inv_range((unsigned long) Handle, (unsigned long) Handle + Bytes);
++#endif
++#endif
++
++#elif defined(CONFIG_MIPS)
++ dma_cache_inv((unsigned long) Logical, Bytes);
++#elif defined(CONFIG_PPC)
++ /* TODO */
++#else
++ dma_sync_single_for_device(
++ gcvNULL,
++ (dma_addr_t)Physical,
++ Bytes,
++ DMA_FROM_DEVICE);
++#endif
++#endif
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++** gckOS_CacheFlush
++**
++** Clean the cache for the specified addresses and invalidate the lines as
++** well. The GPU is going to need and modify the data. If the system is
++** allocating memory as non-cachable, this function can be ignored.
++**
++** ARGUMENTS:
++**
++** gckOS Os
++** Pointer to gckOS object.
++**
++** gctUINT32 ProcessID
++** Process ID Logical belongs.
++**
++** gctPHYS_ADDR Handle
++** Physical address handle. If gcvNULL it is video memory.
++**
++** gctPOINTER Logical
++** Logical address to flush.
++**
++** gctSIZE_T Bytes
++** Size of the address range in bytes to flush.
++*/
++gceSTATUS
++gckOS_CacheFlush(
++ IN gckOS Os,
++ IN gctUINT32 ProcessID,
++ IN gctPHYS_ADDR Handle,
++ IN gctPOINTER Physical,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X ProcessID=%d Handle=0x%X Logical=0x%X Bytes=%lu",
++ Os, ProcessID, Handle, Logical, Bytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++
++#if !gcdCACHE_FUNCTION_UNIMPLEMENTED
++#ifdef CONFIG_ARM
++ /* Inner cache. */
++ dmac_flush_range(Logical, Logical + Bytes);
++
++#if defined(CONFIG_OUTER_CACHE)
++ /* Outer cache. */
++#if gcdENABLE_OUTER_CACHE_PATCH
++ _HandleOuterCache(Os, ProcessID, Handle, Physical, Logical, Bytes, gcvCACHE_FLUSH);
++#else
++ outer_flush_range((unsigned long) Handle, (unsigned long) Handle + Bytes);
++#endif
++#endif
++
++#elif defined(CONFIG_MIPS)
++ dma_cache_wback_inv((unsigned long) Logical, Bytes);
++#elif defined(CONFIG_PPC)
++ /* TODO */
++#else
++ dma_sync_single_for_device(
++ gcvNULL,
++ (dma_addr_t)Physical,
++ Bytes,
++ DMA_BIDIRECTIONAL);
++#endif
++#endif
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++********************************* Broadcasting *********************************
++*******************************************************************************/
++
++/*******************************************************************************
++**
++** gckOS_Broadcast
++**
++** System hook for broadcast events from the kernel driver.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to the gckOS object.
++**
++** gckHARDWARE Hardware
++** Pointer to the gckHARDWARE object.
++**
++** gceBROADCAST Reason
++** Reason for the broadcast. Can be one of the following values:
++**
++** gcvBROADCAST_GPU_IDLE
++** Broadcasted when the kernel driver thinks the GPU might be
++** idle. This can be used to handle power management.
++**
++** gcvBROADCAST_GPU_COMMIT
++** Broadcasted when any client process commits a command
++** buffer. This can be used to handle power management.
++**
++** gcvBROADCAST_GPU_STUCK
++** Broadcasted when the kernel driver hits the timeout waiting
++** for the GPU.
++**
++** gcvBROADCAST_FIRST_PROCESS
++** First process is trying to connect to the kernel.
++**
++** gcvBROADCAST_LAST_PROCESS
++** Last process has detached from the kernel.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_Broadcast(
++ IN gckOS Os,
++ IN gckHARDWARE Hardware,
++ IN gceBROADCAST Reason
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%X Hardware=0x%X Reason=%d", Os, Hardware, Reason);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ switch (Reason)
++ {
++ case gcvBROADCAST_FIRST_PROCESS:
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_OS, "First process has attached");
++ break;
++
++ case gcvBROADCAST_LAST_PROCESS:
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_OS, "Last process has detached");
++
++ /* Put GPU OFF. */
++ gcmkONERROR(
++ gckHARDWARE_SetPowerManagementState(Hardware,
++ gcvPOWER_OFF_BROADCAST));
++ break;
++
++ case gcvBROADCAST_GPU_IDLE:
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_OS, "GPU idle.");
++
++ /* Put GPU IDLE. */
++ gcmkONERROR(
++ gckHARDWARE_SetPowerManagementState(Hardware,
++#if gcdPOWER_SUSNPEND_WHEN_IDLE
++ gcvPOWER_SUSPEND_BROADCAST));
++#else
++ gcvPOWER_IDLE_BROADCAST));
++#endif
++
++ /* Add idle process DB. */
++ gcmkONERROR(gckKERNEL_AddProcessDB(Hardware->kernel,
++ 1,
++ gcvDB_IDLE,
++ gcvNULL, gcvNULL, 0));
++ break;
++
++ case gcvBROADCAST_GPU_COMMIT:
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_OS, "COMMIT has arrived.");
++
++ /* Add busy process DB. */
++ gcmkONERROR(gckKERNEL_AddProcessDB(Hardware->kernel,
++ 0,
++ gcvDB_IDLE,
++ gcvNULL, gcvNULL, 0));
++
++ /* Put GPU ON. */
++ gcmkONERROR(
++ gckHARDWARE_SetPowerManagementState(Hardware, gcvPOWER_ON_AUTO));
++ break;
++
++ case gcvBROADCAST_GPU_STUCK:
++ gcmkTRACE_N(gcvLEVEL_ERROR, 0, "gcvBROADCAST_GPU_STUCK\n");
++#if !gcdENABLE_RECOVERY
++ gcmkONERROR(gckHARDWARE_DumpGPUState(Hardware));
++#endif
++ gcmkONERROR(gckKERNEL_Recovery(Hardware->kernel));
++ break;
++
++ case gcvBROADCAST_AXI_BUS_ERROR:
++ gcmkTRACE_N(gcvLEVEL_ERROR, 0, "gcvBROADCAST_AXI_BUS_ERROR\n");
++ gcmkONERROR(gckHARDWARE_DumpGPUState(Hardware));
++ gcmkONERROR(gckKERNEL_Recovery(Hardware->kernel));
++ break;
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_BroadcastHurry
++**
++** The GPU is running too slow.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to the gckOS object.
++**
++** gckHARDWARE Hardware
++** Pointer to the gckHARDWARE object.
++**
++** gctUINT Urgency
++** The higher the number, the higher the urgency to speed up the GPU.
++** The maximum value is defined by the gcdDYNAMIC_EVENT_THRESHOLD.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_BroadcastHurry(
++ IN gckOS Os,
++ IN gckHARDWARE Hardware,
++ IN gctUINT Urgency
++ )
++{
++ gcmkHEADER_ARG("Os=0x%x Hardware=0x%x Urgency=%u", Os, Hardware, Urgency);
++
++ /* Do whatever you need to do to speed up the GPU now. */
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_BroadcastCalibrateSpeed
++**
++** Calibrate the speed of the GPU.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to the gckOS object.
++**
++** gckHARDWARE Hardware
++** Pointer to the gckHARDWARE object.
++**
++** gctUINT Idle, Time
++** Idle/Time will give the percentage the GPU is idle, so you can use
++** this to calibrate the working point of the GPU.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_BroadcastCalibrateSpeed(
++ IN gckOS Os,
++ IN gckHARDWARE Hardware,
++ IN gctUINT Idle,
++ IN gctUINT Time
++ )
++{
++ gcmkHEADER_ARG("Os=0x%x Hardware=0x%x Idle=%u Time=%u",
++ Os, Hardware, Idle, Time);
++
++ /* Do whatever you need to do to callibrate the GPU speed. */
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++********************************** Semaphores **********************************
++*******************************************************************************/
++
++/*******************************************************************************
++**
++** gckOS_CreateSemaphore
++**
++** Create a semaphore.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to the gckOS object.
++**
++** OUTPUT:
++**
++** gctPOINTER * Semaphore
++** Pointer to the variable that will receive the created semaphore.
++*/
++gceSTATUS
++gckOS_CreateSemaphore(
++ IN gckOS Os,
++ OUT gctPOINTER * Semaphore
++ )
++{
++ gceSTATUS status;
++ struct semaphore *sem = gcvNULL;
++
++ gcmkHEADER_ARG("Os=0x%X", Os);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Semaphore != gcvNULL);
++
++ /* Allocate the semaphore structure. */
++ sem = (struct semaphore *)kmalloc(gcmSIZEOF(struct semaphore), GFP_KERNEL | gcdNOWARN);
++ if (sem == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ /* Initialize the semaphore. */
++ sema_init(sem, 1);
++
++ /* Return to caller. */
++ *Semaphore = (gctPOINTER) sem;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_AcquireSemaphore
++**
++** Acquire a semaphore.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to the gckOS object.
++**
++** gctPOINTER Semaphore
++** Pointer to the semaphore thet needs to be acquired.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_AcquireSemaphore(
++ IN gckOS Os,
++ IN gctPOINTER Semaphore
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%08X Semaphore=0x%08X", Os, Semaphore);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Semaphore != gcvNULL);
++
++ /* Acquire the semaphore. */
++ if (down_interruptible((struct semaphore *) Semaphore))
++ {
++ gcmkONERROR(gcvSTATUS_INTERRUPTED);
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_TryAcquireSemaphore
++**
++** Try to acquire a semaphore.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to the gckOS object.
++**
++** gctPOINTER Semaphore
++** Pointer to the semaphore thet needs to be acquired.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_TryAcquireSemaphore(
++ IN gckOS Os,
++ IN gctPOINTER Semaphore
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%x", Os);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Semaphore != gcvNULL);
++
++ /* Acquire the semaphore. */
++ if (down_trylock((struct semaphore *) Semaphore))
++ {
++ /* Timeout. */
++ status = gcvSTATUS_TIMEOUT;
++ gcmkFOOTER();
++ return status;
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_ReleaseSemaphore
++**
++** Release a previously acquired semaphore.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to the gckOS object.
++**
++** gctPOINTER Semaphore
++** Pointer to the semaphore thet needs to be released.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_ReleaseSemaphore(
++ IN gckOS Os,
++ IN gctPOINTER Semaphore
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Semaphore=0x%X", Os, Semaphore);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Semaphore != gcvNULL);
++
++ /* Release the semaphore. */
++ up((struct semaphore *) Semaphore);
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_DestroySemaphore
++**
++** Destroy a semaphore.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to the gckOS object.
++**
++** gctPOINTER Semaphore
++** Pointer to the semaphore thet needs to be destroyed.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_DestroySemaphore(
++ IN gckOS Os,
++ IN gctPOINTER Semaphore
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Semaphore=0x%X", Os, Semaphore);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Semaphore != gcvNULL);
++
++ /* Free the sempahore structure. */
++ kfree(Semaphore);
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_GetProcessID
++**
++** Get current process ID.
++**
++** INPUT:
++**
++** Nothing.
++**
++** OUTPUT:
++**
++** gctUINT32_PTR ProcessID
++** Pointer to the variable that receives the process ID.
++*/
++gceSTATUS
++gckOS_GetProcessID(
++ OUT gctUINT32_PTR ProcessID
++ )
++{
++ /* Get process ID. */
++ if (ProcessID != gcvNULL)
++ {
++ *ProcessID = _GetProcessID();
++ }
++
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_GetThreadID
++**
++** Get current thread ID.
++**
++** INPUT:
++**
++** Nothing.
++**
++** OUTPUT:
++**
++** gctUINT32_PTR ThreadID
++** Pointer to the variable that receives the thread ID.
++*/
++gceSTATUS
++gckOS_GetThreadID(
++ OUT gctUINT32_PTR ThreadID
++ )
++{
++ /* Get thread ID. */
++ if (ThreadID != gcvNULL)
++ {
++ *ThreadID = _GetThreadID();
++ }
++
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_SetGPUPower
++**
++** Set the power of the GPU on or off.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gckCORE Core
++** GPU whose power is set.
++**
++** gctBOOL Clock
++** gcvTRUE to turn on the clock, or gcvFALSE to turn off the clock.
++**
++** gctBOOL Power
++** gcvTRUE to turn on the power, or gcvFALSE to turn off the power.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_SetGPUPower(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctBOOL Clock,
++ IN gctBOOL Power
++ )
++{
++ struct clk *clk_3dcore = Os->device->clk_3d_core;
++ struct clk *clk_3dshader = Os->device->clk_3d_shader;
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,5,0)
++ struct clk *clk_3d_axi = Os->device->clk_3d_axi;
++#endif
++ struct clk *clk_2dcore = Os->device->clk_2d_core;
++ struct clk *clk_2d_axi = Os->device->clk_2d_axi;
++ struct clk *clk_vg_axi = Os->device->clk_vg_axi;
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,5,0) || LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
++ int ret;
++#endif
++
++ gctBOOL oldClockState = gcvFALSE;
++ gctBOOL oldPowerState = gcvFALSE;
++
++ gcmkHEADER_ARG("Os=0x%X Core=%d Clock=%d Power=%d", Os, Core, Clock, Power);
++
++ if (Os->device->kernels[Core] != NULL)
++ {
++#if gcdENABLE_VG
++ if (Core == gcvCORE_VG)
++ {
++ oldClockState = Os->device->kernels[Core]->vg->hardware->clockState;
++ oldPowerState = Os->device->kernels[Core]->vg->hardware->powerState;
++ }
++ else
++ {
++#endif
++ oldClockState = Os->device->kernels[Core]->hardware->clockState;
++ oldPowerState = Os->device->kernels[Core]->hardware->powerState;
++#if gcdENABLE_VG
++ }
++#endif
++ }
++ if((Power == gcvTRUE) && (oldPowerState == gcvFALSE))
++ {
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,5,0) || LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
++ if(!IS_ERR(Os->device->gpu_regulator)) {
++ ret = regulator_enable(Os->device->gpu_regulator);
++ if (ret != 0)
++ gckOS_Print("%s(%d): fail to enable pu regulator %d!\n",
++ __FUNCTION__, __LINE__, ret);
++ }
++#else
++ imx_gpc_power_up_pu(true);
++#endif
++
++#ifdef CONFIG_PM
++ pm_runtime_get_sync(Os->device->pmdev);
++#endif
++ }
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,5,0)
++ if (Clock == gcvTRUE) {
++ if (oldClockState == gcvFALSE) {
++ mutex_lock(&Os->gpu_clk_mutex);
++ switch (Core) {
++ case gcvCORE_MAJOR:
++ clk_enable(clk_3dcore);
++ if (cpu_is_mx6q())
++ clk_enable(clk_3dshader);
++ break;
++ case gcvCORE_2D:
++ clk_enable(clk_2dcore);
++ clk_enable(clk_2d_axi);
++ break;
++ case gcvCORE_VG:
++ clk_enable(clk_2dcore);
++ clk_enable(clk_vg_axi);
++ break;
++ default:
++ break;
++ }
++ Os->gpu_clk_on[Core] = 1;
++ mutex_unlock(&Os->gpu_clk_mutex);
++ }
++ } else {
++ if (oldClockState == gcvTRUE) {
++ mutex_lock(&Os->gpu_clk_mutex);
++ switch (Core) {
++ case gcvCORE_MAJOR:
++ if (cpu_is_mx6q())
++ clk_disable(clk_3dshader);
++ clk_disable(clk_3dcore);
++ break;
++ case gcvCORE_2D:
++ clk_disable(clk_2dcore);
++ clk_disable(clk_2d_axi);
++ break;
++ case gcvCORE_VG:
++ clk_disable(clk_2dcore);
++ clk_disable(clk_vg_axi);
++ break;
++ default:
++ break;
++ }
++ Os->gpu_clk_on[Core] = 0;
++ mutex_unlock(&Os->gpu_clk_mutex);
++ }
++ }
++#else
++ if (Clock == gcvTRUE) {
++ if (oldClockState == gcvFALSE) {
++ mutex_lock(&Os->gpu_clk_mutex);
++ switch (Core) {
++ case gcvCORE_MAJOR:
++ clk_prepare_enable(clk_3dcore);
++ clk_prepare_enable(clk_3dshader);
++ clk_prepare_enable(clk_3d_axi);
++ break;
++ case gcvCORE_2D:
++ clk_prepare_enable(clk_2dcore);
++ clk_prepare_enable(clk_2d_axi);
++ break;
++ case gcvCORE_VG:
++ clk_prepare_enable(clk_2dcore);
++ clk_prepare_enable(clk_vg_axi);
++ break;
++ default:
++ break;
++ }
++ Os->gpu_clk_on[Core] = 1;
++ mutex_unlock(&Os->gpu_clk_mutex);
++ }
++ } else {
++ if (oldClockState == gcvTRUE) {
++ mutex_lock(&Os->gpu_clk_mutex);
++ switch (Core) {
++ case gcvCORE_MAJOR:
++ clk_disable_unprepare(clk_3d_axi);
++ clk_disable_unprepare(clk_3dshader);
++ clk_disable_unprepare(clk_3dcore);
++ break;
++ case gcvCORE_2D:
++ clk_disable_unprepare(clk_2d_axi);
++ clk_disable_unprepare(clk_2dcore);
++ break;
++ case gcvCORE_VG:
++ clk_disable_unprepare(clk_vg_axi);
++ clk_disable_unprepare(clk_2dcore);
++ break;
++ default:
++ break;
++ }
++ Os->gpu_clk_on[Core] = 0;
++ mutex_unlock(&Os->gpu_clk_mutex);
++ }
++ }
++#endif
++ if((Power == gcvFALSE) && (oldPowerState == gcvTRUE))
++ {
++#ifdef CONFIG_PM
++ pm_runtime_put_sync(Os->device->pmdev);
++#endif
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,5,0) || LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
++ if(!IS_ERR(Os->device->gpu_regulator))
++ regulator_disable(Os->device->gpu_regulator);
++#else
++ imx_gpc_power_up_pu(false);
++#endif
++
++ }
++ /* TODO: Put your code here. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_ResetGPU
++**
++** Reset the GPU.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gckCORE Core
++** GPU whose power is set.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_ResetGPU(
++ IN gckOS Os,
++ IN gceCORE Core
++ )
++{
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,5,0)
++#define SRC_SCR_OFFSET 0
++#define BP_SRC_SCR_GPU3D_RST 1
++#define BP_SRC_SCR_GPU2D_RST 4
++ void __iomem *src_base = IO_ADDRESS(SRC_BASE_ADDR);
++ gctUINT32 bit_offset,val;
++
++ gcmkHEADER_ARG("Os=0x%X Core=%d", Os, Core);
++
++ if(Core == gcvCORE_MAJOR) {
++ bit_offset = BP_SRC_SCR_GPU3D_RST;
++ } else if((Core == gcvCORE_VG)
++ ||(Core == gcvCORE_2D)) {
++ bit_offset = BP_SRC_SCR_GPU2D_RST;
++ } else {
++ return gcvSTATUS_INVALID_CONFIG;
++ }
++ val = __raw_readl(src_base + SRC_SCR_OFFSET);
++ val &= ~(1 << (bit_offset));
++ val |= (1 << (bit_offset));
++ __raw_writel(val, src_base + SRC_SCR_OFFSET);
++
++ while ((__raw_readl(src_base + SRC_SCR_OFFSET) &
++ (1 << (bit_offset))) != 0) {
++ }
++
++ gcmkFOOTER_NO();
++#elif LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
++ struct reset_control *rstc = Os->device->rstc[Core];
++ if (rstc)
++ reset_control_reset(rstc);
++#else
++ imx_src_reset_gpu((int)Core);
++#endif
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_PrepareGPUFrequency
++**
++** Prepare to set GPU frequency and voltage.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gckCORE Core
++** GPU whose frequency and voltage will be set.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_PrepareGPUFrequency(
++ IN gckOS Os,
++ IN gceCORE Core
++ )
++{
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_FinishGPUFrequency
++**
++** Finish GPU frequency setting.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gckCORE Core
++** GPU whose frequency and voltage is set.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_FinishGPUFrequency(
++ IN gckOS Os,
++ IN gceCORE Core
++ )
++{
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_QueryGPUFrequency
++**
++** Query the current frequency of the GPU.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gckCORE Core
++** GPU whose power is set.
++**
++** gctUINT32 * Frequency
++** Pointer to a gctUINT32 to obtain current frequency, in MHz.
++**
++** gctUINT8 * Scale
++** Pointer to a gctUINT8 to obtain current scale(1 - 64).
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_QueryGPUFrequency(
++ IN gckOS Os,
++ IN gceCORE Core,
++ OUT gctUINT32 * Frequency,
++ OUT gctUINT8 * Scale
++ )
++{
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_SetGPUFrequency
++**
++** Set frequency and voltage of the GPU.
++**
++** 1. DVFS manager gives the target scale of full frequency, BSP must find
++** a real frequency according to this scale and board's configure.
++**
++** 2. BSP should find a suitable voltage for this frequency.
++**
++** 3. BSP must make sure setting take effect before this function returns.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gckCORE Core
++** GPU whose power is set.
++**
++** gctUINT8 Scale
++** Target scale of full frequency, range is [1, 64]. 1 means 1/64 of
++** full frequency and 64 means 64/64 of full frequency.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_SetGPUFrequency(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctUINT8 Scale
++ )
++{
++ return gcvSTATUS_OK;
++}
++
++/*----------------------------------------------------------------------------*/
++/*----- Profile --------------------------------------------------------------*/
++
++gceSTATUS
++gckOS_GetProfileTick(
++ OUT gctUINT64_PTR Tick
++ )
++{
++ struct timespec time;
++
++ ktime_get_ts(&time);
++
++ *Tick = time.tv_nsec + time.tv_sec * 1000000000ULL;
++
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckOS_QueryProfileTickRate(
++ OUT gctUINT64_PTR TickRate
++ )
++{
++ struct timespec res;
++
++ hrtimer_get_res(CLOCK_MONOTONIC, &res);
++
++ *TickRate = res.tv_nsec + res.tv_sec * 1000000000ULL;
++
++ return gcvSTATUS_OK;
++}
++
++gctUINT32
++gckOS_ProfileToMS(
++ IN gctUINT64 Ticks
++ )
++{
++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,23)
++ return div_u64(Ticks, 1000000);
++#else
++ gctUINT64 rem = Ticks;
++ gctUINT64 b = 1000000;
++ gctUINT64 res, d = 1;
++ gctUINT32 high = rem >> 32;
++
++ /* Reduce the thing a bit first */
++ res = 0;
++ if (high >= 1000000)
++ {
++ high /= 1000000;
++ res = (gctUINT64) high << 32;
++ rem -= (gctUINT64) (high * 1000000) << 32;
++ }
++
++ while (((gctINT64) b > 0) && (b < rem))
++ {
++ b <<= 1;
++ d <<= 1;
++ }
++
++ do
++ {
++ if (rem >= b)
++ {
++ rem -= b;
++ res += d;
++ }
++
++ b >>= 1;
++ d >>= 1;
++ }
++ while (d);
++
++ return (gctUINT32) res;
++#endif
++}
++
++/******************************************************************************\
++******************************* Signal Management ******************************
++\******************************************************************************/
++
++#undef _GC_OBJ_ZONE
++#define _GC_OBJ_ZONE gcvZONE_SIGNAL
++
++/*******************************************************************************
++**
++** gckOS_CreateSignal
++**
++** Create a new signal.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctBOOL ManualReset
++** If set to gcvTRUE, gckOS_Signal with gcvFALSE must be called in
++** order to set the signal to nonsignaled state.
++** If set to gcvFALSE, the signal will automatically be set to
++** nonsignaled state by gckOS_WaitSignal function.
++**
++** OUTPUT:
++**
++** gctSIGNAL * Signal
++** Pointer to a variable receiving the created gctSIGNAL.
++*/
++gceSTATUS
++gckOS_CreateSignal(
++ IN gckOS Os,
++ IN gctBOOL ManualReset,
++ OUT gctSIGNAL * Signal
++ )
++{
++ gceSTATUS status;
++ gcsSIGNAL_PTR signal;
++
++ gcmkHEADER_ARG("Os=0x%X ManualReset=%d", Os, ManualReset);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Signal != gcvNULL);
++
++ /* Create an event structure. */
++ signal = (gcsSIGNAL_PTR) kmalloc(sizeof(gcsSIGNAL), GFP_KERNEL | gcdNOWARN);
++
++ if (signal == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ /* Save the process ID. */
++ signal->process = (gctHANDLE)(gctUINTPTR_T) _GetProcessID();
++ signal->manualReset = ManualReset;
++ signal->hardware = gcvNULL;
++ init_completion(&signal->obj);
++ atomic_set(&signal->ref, 1);
++
++ gcmkONERROR(_AllocateIntegerId(&Os->signalDB, signal, &signal->id));
++
++ *Signal = (gctSIGNAL)(gctUINTPTR_T)signal->id;
++
++ gcmkFOOTER_ARG("*Signal=0x%X", *Signal);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (signal != gcvNULL)
++ {
++ kfree(signal);
++ }
++
++ gcmkFOOTER_NO();
++ return status;
++}
++
++gceSTATUS
++gckOS_SignalQueryHardware(
++ IN gckOS Os,
++ IN gctSIGNAL Signal,
++ OUT gckHARDWARE * Hardware
++ )
++{
++ gceSTATUS status;
++ gcsSIGNAL_PTR signal;
++
++ gcmkHEADER_ARG("Os=0x%X Signal=0x%X Hardware=0x%X", Os, Signal, Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Signal != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Hardware != gcvNULL);
++
++ gcmkONERROR(_QueryIntegerId(&Os->signalDB, (gctUINT32)(gctUINTPTR_T)Signal, (gctPOINTER)&signal));
++
++ *Hardware = signal->hardware;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckOS_SignalSetHardware(
++ IN gckOS Os,
++ IN gctSIGNAL Signal,
++ IN gckHARDWARE Hardware
++ )
++{
++ gceSTATUS status;
++ gcsSIGNAL_PTR signal;
++
++ gcmkHEADER_ARG("Os=0x%X Signal=0x%X Hardware=0x%X", Os, Signal, Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Signal != gcvNULL);
++
++ gcmkONERROR(_QueryIntegerId(&Os->signalDB, (gctUINT32)(gctUINTPTR_T)Signal, (gctPOINTER)&signal));
++
++ signal->hardware = Hardware;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_DestroySignal
++**
++** Destroy a signal.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctSIGNAL Signal
++** Pointer to the gctSIGNAL.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_DestroySignal(
++ IN gckOS Os,
++ IN gctSIGNAL Signal
++ )
++{
++ gceSTATUS status;
++ gcsSIGNAL_PTR signal;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Os=0x%X Signal=0x%X", Os, Signal);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Signal != gcvNULL);
++
++ gcmkONERROR(gckOS_AcquireMutex(Os, Os->signalMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ gcmkONERROR(_QueryIntegerId(&Os->signalDB, (gctUINT32)(gctUINTPTR_T)Signal, (gctPOINTER)&signal));
++
++ gcmkASSERT(signal->id == (gctUINT32)(gctUINTPTR_T)Signal);
++
++ if (atomic_dec_and_test(&signal->ref))
++ {
++ gcmkVERIFY_OK(_DestroyIntegerId(&Os->signalDB, signal->id));
++
++ /* Free the sgianl. */
++ kfree(signal);
++ }
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Os, Os->signalMutex));
++ acquired = gcvFALSE;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Os, Os->signalMutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_Signal
++**
++** Set a state of the specified signal.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctSIGNAL Signal
++** Pointer to the gctSIGNAL.
++**
++** gctBOOL State
++** If gcvTRUE, the signal will be set to signaled state.
++** If gcvFALSE, the signal will be set to nonsignaled state.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_Signal(
++ IN gckOS Os,
++ IN gctSIGNAL Signal,
++ IN gctBOOL State
++ )
++{
++ gceSTATUS status;
++ gcsSIGNAL_PTR signal;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Os=0x%X Signal=0x%X State=%d", Os, Signal, State);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Signal != gcvNULL);
++
++ gcmkONERROR(gckOS_AcquireMutex(Os, Os->signalMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ gcmkONERROR(_QueryIntegerId(&Os->signalDB, (gctUINT32)(gctUINTPTR_T)Signal, (gctPOINTER)&signal));
++
++ gcmkASSERT(signal->id == (gctUINT32)(gctUINTPTR_T)Signal);
++
++ if (State)
++ {
++ /* unbind the signal from hardware. */
++ signal->hardware = gcvNULL;
++
++ /* Set the event to a signaled state. */
++ complete(&signal->obj);
++ }
++ else
++ {
++ /* Set the event to an unsignaled state. */
++ reinit_completion(&signal->obj);
++ }
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Os, Os->signalMutex));
++ acquired = gcvFALSE;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Os, Os->signalMutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++#if gcdENABLE_VG
++gceSTATUS
++gckOS_SetSignalVG(
++ IN gckOS Os,
++ IN gctHANDLE Process,
++ IN gctSIGNAL Signal
++ )
++{
++ gceSTATUS status;
++ gctINT result;
++ struct task_struct * userTask;
++ struct siginfo info;
++
++ userTask = FIND_TASK_BY_PID((pid_t)(gctUINTPTR_T) Process);
++
++ if (userTask != gcvNULL)
++ {
++ info.si_signo = 48;
++ info.si_code = __SI_CODE(__SI_RT, SI_KERNEL);
++ info.si_pid = 0;
++ info.si_uid = 0;
++ info.si_ptr = (gctPOINTER) Signal;
++
++ /* Signals with numbers between 32 and 63 are real-time,
++ send a real-time signal to the user process. */
++ result = send_sig_info(48, &info, userTask);
++
++ printk("gckOS_SetSignalVG:0x%x\n", result);
++ /* Error? */
++ if (result < 0)
++ {
++ status = gcvSTATUS_GENERIC_IO;
++
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): an error has occurred.\n",
++ __FUNCTION__, __LINE__
++ );
++ }
++ else
++ {
++ status = gcvSTATUS_OK;
++ }
++ }
++ else
++ {
++ status = gcvSTATUS_GENERIC_IO;
++
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): an error has occurred.\n",
++ __FUNCTION__, __LINE__
++ );
++ }
++
++ /* Return status. */
++ return status;
++}
++#endif
++
++/*******************************************************************************
++**
++** gckOS_UserSignal
++**
++** Set the specified signal which is owned by a process to signaled state.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctSIGNAL Signal
++** Pointer to the gctSIGNAL.
++**
++** gctHANDLE Process
++** Handle of process owning the signal.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_UserSignal(
++ IN gckOS Os,
++ IN gctSIGNAL Signal,
++ IN gctHANDLE Process
++ )
++{
++ gceSTATUS status;
++ gctSIGNAL signal;
++
++ gcmkHEADER_ARG("Os=0x%X Signal=0x%X Process=%d",
++ Os, Signal, (gctINT32)(gctUINTPTR_T)Process);
++
++ /* Map the signal into kernel space. */
++ gcmkONERROR(gckOS_MapSignal(Os, Signal, Process, &signal));
++
++ /* Signal. */
++ status = gckOS_Signal(Os, signal, gcvTRUE);
++
++ /* Unmap the signal */
++ gcmkVERIFY_OK(gckOS_UnmapSignal(Os, Signal));
++
++ gcmkFOOTER();
++ return status;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_WaitSignal
++**
++** Wait for a signal to become signaled.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctSIGNAL Signal
++** Pointer to the gctSIGNAL.
++**
++** gctUINT32 Wait
++** Number of milliseconds to wait.
++** Pass the value of gcvINFINITE for an infinite wait.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_WaitSignal(
++ IN gckOS Os,
++ IN gctSIGNAL Signal,
++ IN gctUINT32 Wait
++ )
++{
++ gceSTATUS status = gcvSTATUS_OK;
++ gcsSIGNAL_PTR signal;
++
++ gcmkHEADER_ARG("Os=0x%X Signal=0x%X Wait=0x%08X", Os, Signal, Wait);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Signal != gcvNULL);
++
++ gcmkONERROR(_QueryIntegerId(&Os->signalDB, (gctUINT32)(gctUINTPTR_T)Signal, (gctPOINTER)&signal));
++
++ gcmkASSERT(signal->id == (gctUINT32)(gctUINTPTR_T)Signal);
++
++ might_sleep();
++
++ spin_lock_irq(&signal->obj.wait.lock);
++
++ if (signal->obj.done)
++ {
++ if (!signal->manualReset)
++ {
++ signal->obj.done = 0;
++ }
++
++ status = gcvSTATUS_OK;
++ }
++ else if (Wait == 0)
++ {
++ status = gcvSTATUS_TIMEOUT;
++ }
++ else
++ {
++ /* Convert wait to milliseconds. */
++#if gcdDETECT_TIMEOUT
++ gctINT timeout = (Wait == gcvINFINITE)
++ ? gcdINFINITE_TIMEOUT * HZ / 1000
++ : Wait * HZ / 1000;
++
++ gctUINT complained = 0;
++#else
++ gctINT timeout = (Wait == gcvINFINITE)
++ ? MAX_SCHEDULE_TIMEOUT
++ : Wait * HZ / 1000;
++#endif
++
++ DECLARE_WAITQUEUE(wait, current);
++ wait.flags |= WQ_FLAG_EXCLUSIVE;
++ __add_wait_queue_tail(&signal->obj.wait, &wait);
++
++ while (gcvTRUE)
++ {
++ if (signal_pending(current))
++ {
++ /* Interrupt received. */
++ status = gcvSTATUS_INTERRUPTED;
++ break;
++ }
++
++ __set_current_state(TASK_INTERRUPTIBLE);
++ spin_unlock_irq(&signal->obj.wait.lock);
++ timeout = schedule_timeout(timeout);
++ spin_lock_irq(&signal->obj.wait.lock);
++
++ if (signal->obj.done)
++ {
++ if (!signal->manualReset)
++ {
++ signal->obj.done = 0;
++ }
++
++ status = gcvSTATUS_OK;
++ break;
++ }
++
++#if gcdDETECT_TIMEOUT
++ if ((Wait == gcvINFINITE) && (timeout == 0))
++ {
++ gctUINT32 dmaAddress1, dmaAddress2;
++ gctUINT32 dmaState1, dmaState2;
++
++ dmaState1 = dmaState2 =
++ dmaAddress1 = dmaAddress2 = 0;
++
++ /* Verify whether DMA is running. */
++ gcmkVERIFY_OK(_VerifyDMA(
++ Os, &dmaAddress1, &dmaAddress2, &dmaState1, &dmaState2
++ ));
++
++#if gcdDETECT_DMA_ADDRESS
++ /* Dump only if DMA appears stuck. */
++ if (
++ (dmaAddress1 == dmaAddress2)
++#if gcdDETECT_DMA_STATE
++ && (dmaState1 == dmaState2)
++#endif
++ )
++#endif
++ {
++ /* Increment complain count. */
++ complained += 1;
++
++ gcmkVERIFY_OK(_DumpGPUState(Os, gcvCORE_MAJOR));
++
++ gcmkPRINT(
++ "%s(%d): signal 0x%X; forced message flush (%d).",
++ __FUNCTION__, __LINE__, Signal, complained
++ );
++
++ /* Flush the debug cache. */
++ gcmkDEBUGFLUSH(dmaAddress2);
++ }
++
++ /* Reset timeout. */
++ timeout = gcdINFINITE_TIMEOUT * HZ / 1000;
++ }
++#endif
++
++ if (timeout == 0)
++ {
++
++ status = gcvSTATUS_TIMEOUT;
++ break;
++ }
++ }
++
++ __remove_wait_queue(&signal->obj.wait, &wait);
++
++#if gcdDETECT_TIMEOUT
++ if (complained)
++ {
++ gcmkPRINT(
++ "%s(%d): signal=0x%X; waiting done; status=%d",
++ __FUNCTION__, __LINE__, Signal, status
++ );
++ }
++#endif
++ }
++
++ spin_unlock_irq(&signal->obj.wait.lock);
++
++OnError:
++ /* Return status. */
++ gcmkFOOTER_ARG("Signal=0x%X status=%d", Signal, status);
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_MapSignal
++**
++** Map a signal in to the current process space.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctSIGNAL Signal
++** Pointer to tha gctSIGNAL to map.
++**
++** gctHANDLE Process
++** Handle of process owning the signal.
++**
++** OUTPUT:
++**
++** gctSIGNAL * MappedSignal
++** Pointer to a variable receiving the mapped gctSIGNAL.
++*/
++gceSTATUS
++gckOS_MapSignal(
++ IN gckOS Os,
++ IN gctSIGNAL Signal,
++ IN gctHANDLE Process,
++ OUT gctSIGNAL * MappedSignal
++ )
++{
++ gceSTATUS status;
++ gcsSIGNAL_PTR signal;
++ gcmkHEADER_ARG("Os=0x%X Signal=0x%X Process=0x%X", Os, Signal, Process);
++
++ gcmkVERIFY_ARGUMENT(Signal != gcvNULL);
++ gcmkVERIFY_ARGUMENT(MappedSignal != gcvNULL);
++
++ gcmkONERROR(_QueryIntegerId(&Os->signalDB, (gctUINT32)(gctUINTPTR_T)Signal, (gctPOINTER)&signal));
++
++ if(atomic_inc_return(&signal->ref) <= 1)
++ {
++ /* The previous value is 0, it has been deleted. */
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ *MappedSignal = (gctSIGNAL) Signal;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*MappedSignal=0x%X", *MappedSignal);
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER_NO();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_UnmapSignal
++**
++** Unmap a signal .
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctSIGNAL Signal
++** Pointer to that gctSIGNAL mapped.
++*/
++gceSTATUS
++gckOS_UnmapSignal(
++ IN gckOS Os,
++ IN gctSIGNAL Signal
++ )
++{
++ return gckOS_DestroySignal(Os, Signal);
++}
++
++/*******************************************************************************
++**
++** gckOS_CreateUserSignal
++**
++** Create a new signal to be used in the user space.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctBOOL ManualReset
++** If set to gcvTRUE, gckOS_Signal with gcvFALSE must be called in
++** order to set the signal to nonsignaled state.
++** If set to gcvFALSE, the signal will automatically be set to
++** nonsignaled state by gckOS_WaitSignal function.
++**
++** OUTPUT:
++**
++** gctINT * SignalID
++** Pointer to a variable receiving the created signal's ID.
++*/
++gceSTATUS
++gckOS_CreateUserSignal(
++ IN gckOS Os,
++ IN gctBOOL ManualReset,
++ OUT gctINT * SignalID
++ )
++{
++ gceSTATUS status;
++ gctSIZE_T signal;
++
++ /* Create a new signal. */
++ status = gckOS_CreateSignal(Os, ManualReset, (gctSIGNAL *) &signal);
++ *SignalID = (gctINT) signal;
++
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_DestroyUserSignal
++**
++** Destroy a signal to be used in the user space.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctINT SignalID
++** The signal's ID.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_DestroyUserSignal(
++ IN gckOS Os,
++ IN gctINT SignalID
++ )
++{
++ return gckOS_DestroySignal(Os, (gctSIGNAL)(gctUINTPTR_T)SignalID);
++}
++
++/*******************************************************************************
++**
++** gckOS_WaitUserSignal
++**
++** Wait for a signal used in the user mode to become signaled.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctINT SignalID
++** Signal ID.
++**
++** gctUINT32 Wait
++** Number of milliseconds to wait.
++** Pass the value of gcvINFINITE for an infinite wait.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_WaitUserSignal(
++ IN gckOS Os,
++ IN gctINT SignalID,
++ IN gctUINT32 Wait
++ )
++{
++ return gckOS_WaitSignal(Os, (gctSIGNAL)(gctUINTPTR_T)SignalID, Wait);
++}
++
++/*******************************************************************************
++**
++** gckOS_SignalUserSignal
++**
++** Set a state of the specified signal to be used in the user space.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctINT SignalID
++** SignalID.
++**
++** gctBOOL State
++** If gcvTRUE, the signal will be set to signaled state.
++** If gcvFALSE, the signal will be set to nonsignaled state.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_SignalUserSignal(
++ IN gckOS Os,
++ IN gctINT SignalID,
++ IN gctBOOL State
++ )
++{
++ return gckOS_Signal(Os, (gctSIGNAL)(gctUINTPTR_T)SignalID, State);
++}
++
++#if gcdENABLE_VG
++gceSTATUS
++gckOS_CreateSemaphoreVG(
++ IN gckOS Os,
++ OUT gctSEMAPHORE * Semaphore
++ )
++{
++ gceSTATUS status;
++ struct semaphore * newSemaphore;
++
++ gcmkHEADER_ARG("Os=0x%X Semaphore=0x%x", Os, Semaphore);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Semaphore != gcvNULL);
++
++ do
++ {
++ /* Allocate the semaphore structure. */
++ newSemaphore = (struct semaphore *)kmalloc(gcmSIZEOF(struct semaphore), GFP_KERNEL | gcdNOWARN);
++ if (newSemaphore == gcvNULL)
++ {
++ gcmkERR_BREAK(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ /* Initialize the semaphore. */
++ sema_init(newSemaphore, 0);
++
++ /* Set the handle. */
++ * Semaphore = (gctSEMAPHORE) newSemaphore;
++
++ /* Success. */
++ status = gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ gcmkFOOTER();
++ /* Return the status. */
++ return status;
++}
++
++
++gceSTATUS
++gckOS_IncrementSemaphore(
++ IN gckOS Os,
++ IN gctSEMAPHORE Semaphore
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Semaphore=0x%x", Os, Semaphore);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Semaphore != gcvNULL);
++
++ /* Increment the semaphore's count. */
++ up((struct semaphore *) Semaphore);
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckOS_DecrementSemaphore(
++ IN gckOS Os,
++ IN gctSEMAPHORE Semaphore
++ )
++{
++ gceSTATUS status;
++ gctINT result;
++
++ gcmkHEADER_ARG("Os=0x%X Semaphore=0x%x", Os, Semaphore);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Semaphore != gcvNULL);
++
++ do
++ {
++ /* Decrement the semaphore's count. If the count is zero, wait
++ until it gets incremented. */
++ result = down_interruptible((struct semaphore *) Semaphore);
++
++ /* Signal received? */
++ if (result != 0)
++ {
++ status = gcvSTATUS_TERMINATE;
++ break;
++ }
++
++ /* Success. */
++ status = gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ gcmkFOOTER();
++ /* Return the status. */
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_SetSignal
++**
++** Set the specified signal to signaled state.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to the gckOS object.
++**
++** gctHANDLE Process
++** Handle of process owning the signal.
++**
++** gctSIGNAL Signal
++** Pointer to the gctSIGNAL.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_SetSignal(
++ IN gckOS Os,
++ IN gctHANDLE Process,
++ IN gctSIGNAL Signal
++ )
++{
++ gceSTATUS status;
++ gctINT result;
++ struct task_struct * userTask;
++ struct siginfo info;
++
++ userTask = FIND_TASK_BY_PID((pid_t)(gctUINTPTR_T) Process);
++
++ if (userTask != gcvNULL)
++ {
++ info.si_signo = 48;
++ info.si_code = __SI_CODE(__SI_RT, SI_KERNEL);
++ info.si_pid = 0;
++ info.si_uid = 0;
++ info.si_ptr = (gctPOINTER) Signal;
++
++ /* Signals with numbers between 32 and 63 are real-time,
++ send a real-time signal to the user process. */
++ result = send_sig_info(48, &info, userTask);
++
++ /* Error? */
++ if (result < 0)
++ {
++ status = gcvSTATUS_GENERIC_IO;
++
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): an error has occurred.\n",
++ __FUNCTION__, __LINE__
++ );
++ }
++ else
++ {
++ status = gcvSTATUS_OK;
++ }
++ }
++ else
++ {
++ status = gcvSTATUS_GENERIC_IO;
++
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): an error has occurred.\n",
++ __FUNCTION__, __LINE__
++ );
++ }
++
++ /* Return status. */
++ return status;
++}
++
++/******************************************************************************\
++******************************** Thread Object *********************************
++\******************************************************************************/
++
++gceSTATUS
++gckOS_StartThread(
++ IN gckOS Os,
++ IN gctTHREADFUNC ThreadFunction,
++ IN gctPOINTER ThreadParameter,
++ OUT gctTHREAD * Thread
++ )
++{
++ gceSTATUS status;
++ struct task_struct * thread;
++
++ gcmkHEADER_ARG("Os=0x%X ", Os);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(ThreadFunction != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Thread != gcvNULL);
++
++ do
++ {
++ /* Create the thread. */
++ thread = kthread_create(
++ ThreadFunction,
++ ThreadParameter,
++ "Vivante Kernel Thread"
++ );
++
++ /* Failed? */
++ if (IS_ERR(thread))
++ {
++ status = gcvSTATUS_GENERIC_IO;
++ break;
++ }
++
++ /* Start the thread. */
++ wake_up_process(thread);
++
++ /* Set the thread handle. */
++ * Thread = (gctTHREAD) thread;
++
++ /* Success. */
++ status = gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ gcmkFOOTER();
++ /* Return the status. */
++ return status;
++}
++
++gceSTATUS
++gckOS_StopThread(
++ IN gckOS Os,
++ IN gctTHREAD Thread
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Thread=0x%x", Os, Thread);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Thread != gcvNULL);
++
++ /* Thread should have already been enabled to terminate. */
++ kthread_stop((struct task_struct *) Thread);
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckOS_VerifyThread(
++ IN gckOS Os,
++ IN gctTHREAD Thread
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Thread=0x%x", Os, Thread);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Thread != gcvNULL);
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++#endif
++
++/******************************************************************************\
++******************************** Software Timer ********************************
++\******************************************************************************/
++
++void
++_TimerFunction(
++ struct work_struct * work
++ )
++{
++ gcsOSTIMER_PTR timer = (gcsOSTIMER_PTR)work;
++
++ gctTIMERFUNCTION function = timer->function;
++
++ function(timer->data);
++}
++
++/*******************************************************************************
++**
++** gckOS_CreateTimer
++**
++** Create a software timer.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to the gckOS object.
++**
++** gctTIMERFUNCTION Function.
++** Pointer to a call back function which will be called when timer is
++** expired.
++**
++** gctPOINTER Data.
++** Private data which will be passed to call back function.
++**
++** OUTPUT:
++**
++** gctPOINTER * Timer
++** Pointer to a variable receiving the created timer.
++*/
++gceSTATUS
++gckOS_CreateTimer(
++ IN gckOS Os,
++ IN gctTIMERFUNCTION Function,
++ IN gctPOINTER Data,
++ OUT gctPOINTER * Timer
++ )
++{
++ gceSTATUS status;
++ gcsOSTIMER_PTR pointer;
++ gcmkHEADER_ARG("Os=0x%X Function=0x%X Data=0x%X", Os, Function, Data);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Timer != gcvNULL);
++
++ gcmkONERROR(gckOS_Allocate(Os, sizeof(gcsOSTIMER), (gctPOINTER)&pointer));
++
++ pointer->function = Function;
++ pointer->data = Data;
++
++ INIT_DELAYED_WORK(&pointer->work, _TimerFunction);
++
++ *Timer = pointer;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_DestroyTimer
++**
++** Destory a software timer.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to the gckOS object.
++**
++** gctPOINTER Timer
++** Pointer to the timer to be destoryed.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_DestroyTimer(
++ IN gckOS Os,
++ IN gctPOINTER Timer
++ )
++{
++ gcsOSTIMER_PTR timer;
++ gcmkHEADER_ARG("Os=0x%X Timer=0x%X", Os, Timer);
++
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Timer != gcvNULL);
++
++ timer = (gcsOSTIMER_PTR)Timer;
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,23)
++ cancel_delayed_work_sync(&timer->work);
++#else
++ cancel_delayed_work(&timer->work);
++ flush_workqueue(Os->workqueue);
++#endif
++
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Os, Timer));
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_StartTimer
++**
++** Schedule a software timer.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to the gckOS object.
++**
++** gctPOINTER Timer
++** Pointer to the timer to be scheduled.
++**
++** gctUINT32 Delay
++** Delay in milliseconds.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_StartTimer(
++ IN gckOS Os,
++ IN gctPOINTER Timer,
++ IN gctUINT32 Delay
++ )
++{
++ gcsOSTIMER_PTR timer;
++
++ gcmkHEADER_ARG("Os=0x%X Timer=0x%X Delay=%u", Os, Timer, Delay);
++
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Timer != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Delay != 0);
++
++ timer = (gcsOSTIMER_PTR)Timer;
++
++ if (unlikely(delayed_work_pending(&timer->work)))
++ {
++ if (unlikely(!cancel_delayed_work(&timer->work)))
++ {
++ cancel_work_sync(&timer->work.work);
++
++ if (unlikely(delayed_work_pending(&timer->work)))
++ {
++ gckOS_Print("gckOS_StartTimer error, the pending worker cannot complete!!!! \n");
++
++ return gcvSTATUS_INVALID_REQUEST;
++ }
++ }
++ }
++
++ queue_delayed_work(Os->workqueue, &timer->work, msecs_to_jiffies(Delay));
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_StopTimer
++**
++** Cancel a unscheduled timer.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to the gckOS object.
++**
++** gctPOINTER Timer
++** Pointer to the timer to be cancel.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_StopTimer(
++ IN gckOS Os,
++ IN gctPOINTER Timer
++ )
++{
++ gcsOSTIMER_PTR timer;
++ gcmkHEADER_ARG("Os=0x%X Timer=0x%X", Os, Timer);
++
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Timer != gcvNULL);
++
++ timer = (gcsOSTIMER_PTR)Timer;
++
++ cancel_delayed_work(&timer->work);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++
++gceSTATUS
++gckOS_DumpCallStack(
++ IN gckOS Os
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X", Os);
++
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++
++ dump_stack();
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++
++gceSTATUS
++gckOS_GetProcessNameByPid(
++ IN gctINT Pid,
++ IN gctSIZE_T Length,
++ OUT gctUINT8_PTR String
++ )
++{
++ struct task_struct *task;
++
++ /* Get the task_struct of the task with pid. */
++ rcu_read_lock();
++
++ task = FIND_TASK_BY_PID(Pid);
++
++ if (task == gcvNULL)
++ {
++ rcu_read_unlock();
++ return gcvSTATUS_NOT_FOUND;
++ }
++
++ /* Get name of process. */
++ strncpy(String, task->comm, Length);
++
++ rcu_read_unlock();
++
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckOS_GetVideoMemoryMutex(
++ IN gckOS Os,
++ OUT gctPOINTER *Mutex
++ )
++{
++ gcmkHEADER_ARG("Mutex=x%X", Mutex);
++
++ *Mutex = Os->vidmemMutex;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++#if gcdANDROID_NATIVE_FENCE_SYNC
++
++gceSTATUS
++gckOS_CreateSyncPoint(
++ IN gckOS Os,
++ OUT gctSYNC_POINT * SyncPoint
++ )
++{
++ gceSTATUS status;
++ gcsSYNC_POINT_PTR syncPoint;
++
++ gcmkHEADER_ARG("Os=0x%X", Os);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++
++ /* Create an sync point structure. */
++ syncPoint = (gcsSYNC_POINT_PTR) kmalloc(
++ sizeof(gcsSYNC_POINT), GFP_KERNEL | gcdNOWARN);
++
++ if (syncPoint == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ /* Initialize the sync point. */
++ atomic_set(&syncPoint->ref, 1);
++ atomic_set(&syncPoint->state, 0);
++
++ gcmkONERROR(_AllocateIntegerId(&Os->syncPointDB, syncPoint, &syncPoint->id));
++
++ *SyncPoint = (gctSYNC_POINT)(gctUINTPTR_T)syncPoint->id;
++
++ gcmkFOOTER_ARG("*SyncPonint=%d", syncPoint->id);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (syncPoint != gcvNULL)
++ {
++ kfree(syncPoint);
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckOS_ReferenceSyncPoint(
++ IN gckOS Os,
++ IN gctSYNC_POINT SyncPoint
++ )
++{
++ gceSTATUS status;
++ gcsSYNC_POINT_PTR syncPoint;
++
++ gcmkHEADER_ARG("Os=0x%X", Os);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(SyncPoint != gcvNULL);
++
++ gcmkONERROR(
++ _QueryIntegerId(&Os->syncPointDB,
++ (gctUINT32)(gctUINTPTR_T)SyncPoint,
++ (gctPOINTER)&syncPoint));
++
++ /* Initialize the sync point. */
++ atomic_inc(&syncPoint->ref);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckOS_DestroySyncPoint(
++ IN gckOS Os,
++ IN gctSYNC_POINT SyncPoint
++ )
++{
++ gceSTATUS status;
++ gcsSYNC_POINT_PTR syncPoint;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Os=0x%X SyncPoint=%d", Os, (gctUINT32)(gctUINTPTR_T)SyncPoint);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(SyncPoint != gcvNULL);
++
++ gcmkONERROR(gckOS_AcquireMutex(Os, Os->syncPointMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ gcmkONERROR(
++ _QueryIntegerId(&Os->syncPointDB,
++ (gctUINT32)(gctUINTPTR_T)SyncPoint,
++ (gctPOINTER)&syncPoint));
++
++ gcmkASSERT(syncPoint->id == (gctUINT32)(gctUINTPTR_T)SyncPoint);
++
++ if (atomic_dec_and_test(&syncPoint->ref))
++ {
++ gcmkVERIFY_OK(_DestroyIntegerId(&Os->syncPointDB, syncPoint->id));
++
++ /* Free the sgianl. */
++ syncPoint->timeline = gcvNULL;
++ kfree(syncPoint);
++ }
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Os, Os->syncPointMutex));
++ acquired = gcvFALSE;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Os, Os->syncPointMutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckOS_SignalSyncPoint(
++ IN gckOS Os,
++ IN gctSYNC_POINT SyncPoint
++ )
++{
++ gceSTATUS status;
++ gcsSYNC_POINT_PTR syncPoint;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Os=0x%X SyncPoint=%d", Os, (gctUINT32)(gctUINTPTR_T)SyncPoint);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(SyncPoint != gcvNULL);
++
++ gcmkONERROR(gckOS_AcquireMutex(Os, Os->syncPointMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ gcmkONERROR(
++ _QueryIntegerId(&Os->syncPointDB,
++ (gctUINT32)(gctUINTPTR_T)SyncPoint,
++ (gctPOINTER)&syncPoint));
++
++ gcmkASSERT(syncPoint->id == (gctUINT32)(gctUINTPTR_T)SyncPoint);
++
++ /* Get state. */
++ atomic_set(&syncPoint->state, gcvTRUE);
++
++ /* Signal timeline. */
++ if (syncPoint->timeline)
++ {
++ sync_timeline_signal(syncPoint->timeline);
++ }
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Os, Os->syncPointMutex));
++ acquired = gcvFALSE;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Os, Os->syncPointMutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckOS_QuerySyncPoint(
++ IN gckOS Os,
++ IN gctSYNC_POINT SyncPoint,
++ OUT gctBOOL_PTR State
++ )
++{
++ gceSTATUS status;
++ gcsSYNC_POINT_PTR syncPoint;
++
++ gcmkHEADER_ARG("Os=0x%X SyncPoint=%d", Os, (gctUINT32)(gctUINTPTR_T)SyncPoint);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(SyncPoint != gcvNULL);
++
++ gcmkONERROR(
++ _QueryIntegerId(&Os->syncPointDB,
++ (gctUINT32)(gctUINTPTR_T)SyncPoint,
++ (gctPOINTER)&syncPoint));
++
++ gcmkASSERT(syncPoint->id == (gctUINT32)(gctUINTPTR_T)SyncPoint);
++
++ /* Get state. */
++ *State = atomic_read(&syncPoint->state);
++
++ /* Success. */
++ gcmkFOOTER_ARG("*State=%d", *State);
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckOS_CreateSyncTimeline(
++ IN gckOS Os,
++ OUT gctHANDLE * Timeline
++ )
++{
++ struct viv_sync_timeline * timeline;
++
++ /* Create viv sync timeline. */
++ timeline = viv_sync_timeline_create("viv timeline", Os);
++
++ if (timeline == gcvNULL)
++ {
++ /* Out of memory. */
++ return gcvSTATUS_OUT_OF_MEMORY;
++ }
++
++ *Timeline = (gctHANDLE) timeline;
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckOS_DestroySyncTimeline(
++ IN gckOS Os,
++ IN gctHANDLE Timeline
++ )
++{
++ struct viv_sync_timeline * timeline;
++ gcmkASSERT(Timeline != gcvNULL);
++
++ /* Destroy timeline. */
++ timeline = (struct viv_sync_timeline *) Timeline;
++ sync_timeline_destroy(&timeline->obj);
++
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckOS_CreateNativeFence(
++ IN gckOS Os,
++ IN gctHANDLE Timeline,
++ IN gctSYNC_POINT SyncPoint,
++ OUT gctINT * FenceFD
++ )
++{
++ int fd = -1;
++ struct viv_sync_timeline *timeline;
++ struct sync_pt * pt = gcvNULL;
++ struct sync_fence * fence;
++ char name[32];
++ gcsSYNC_POINT_PTR syncPoint;
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%X Timeline=0x%X SyncPoint=%d",
++ Os, Timeline, (gctUINT)(gctUINTPTR_T)SyncPoint);
++
++ gcmkONERROR(
++ _QueryIntegerId(&Os->syncPointDB,
++ (gctUINT32)(gctUINTPTR_T)SyncPoint,
++ (gctPOINTER)&syncPoint));
++
++ /* Cast timeline. */
++ timeline = (struct viv_sync_timeline *) Timeline;
++
++ fd = get_unused_fd();
++
++ if (fd < 0)
++ {
++ /* Out of resources. */
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++ /* Create viv_sync_pt. */
++ pt = viv_sync_pt_create(timeline, SyncPoint);
++
++ if (pt == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ /* Reference sync_timeline. */
++ syncPoint->timeline = &timeline->obj;
++
++ /* Build fence name. */
++ snprintf(name, 32, "viv sync_fence-%u", (gctUINT)(gctUINTPTR_T)SyncPoint);
++
++ /* Create sync_fence. */
++ fence = sync_fence_create(name, pt);
++
++ if (fence == NULL)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ /* Install fence to fd. */
++ sync_fence_install(fence, fd);
++
++ *FenceFD = fd;
++ gcmkFOOTER_ARG("*FenceFD=%d", fd);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Error roll back. */
++ if (pt)
++ {
++ sync_pt_free(pt);
++ }
++
++ if (fd > 0)
++ {
++ put_unused_fd(fd);
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++#endif
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_os.h linux-xbian-imx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_os.h
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_os.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_os.h 2015-07-27 23:13:06.226765901 +0200
+@@ -0,0 +1,83 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_kernel_os_h_
++#define __gc_hal_kernel_os_h_
++
++typedef struct _LINUX_MDL_MAP
++{
++ gctINT pid;
++ gctPOINTER vmaAddr;
++ gctUINT32 count;
++ struct vm_area_struct * vma;
++ struct _LINUX_MDL_MAP * next;
++}
++LINUX_MDL_MAP;
++
++typedef struct _LINUX_MDL_MAP * PLINUX_MDL_MAP;
++
++typedef struct _LINUX_MDL
++{
++ gctINT pid;
++ char * addr;
++
++ union _pages
++ {
++ /* Pointer to a array of pages. */
++ struct page * contiguousPages;
++ /* Pointer to a array of pointers to page. */
++ struct page ** nonContiguousPages;
++ }
++ u;
++
++#ifdef NO_DMA_COHERENT
++ gctPOINTER kaddr;
++#endif /* NO_DMA_COHERENT */
++
++ gctINT numPages;
++ gctINT pagedMem;
++ gctBOOL contiguous;
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)
++ gctBOOL exact;
++#endif
++ dma_addr_t dmaHandle;
++ PLINUX_MDL_MAP maps;
++ struct _LINUX_MDL * prev;
++ struct _LINUX_MDL * next;
++}
++LINUX_MDL, *PLINUX_MDL;
++
++extern PLINUX_MDL_MAP
++FindMdlMap(
++ IN PLINUX_MDL Mdl,
++ IN gctINT PID
++ );
++
++typedef struct _DRIVER_ARGS
++{
++ gctUINT64 InputBuffer;
++ gctUINT64 InputBufferSize;
++ gctUINT64 OutputBuffer;
++ gctUINT64 OutputBufferSize;
++}
++DRIVER_ARGS;
++
++#endif /* __gc_hal_kernel_os_h_ */
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_platform.h linux-xbian-imx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_platform.h
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_platform.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_platform.h 2015-07-27 23:13:06.226765901 +0200
+@@ -0,0 +1,279 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef _gc_hal_kernel_platform_h_
++#define _gc_hal_kernel_platform_h_
++#include <linux/mm.h>
++
++typedef struct _gcsMODULE_PARAMETERS
++{
++#if gcdMULTI_GPU || gcdMULTI_GPU_AFFINITY
++ gctINT irqLine3D0;
++ gctUINT registerMemBase3D0;
++ gctUINT registerMemSize3D0;
++ gctINT irqLine3D1;
++ gctUINT registerMemBase3D1;
++ gctUINT registerMemSize3D1;
++#else
++ gctINT irqLine;
++ gctUINT registerMemBase;
++ gctUINT registerMemSize;
++#endif
++ gctINT irqLine2D;
++ gctUINT registerMemBase2D;
++ gctUINT registerMemSize2D;
++ gctINT irqLineVG;
++ gctUINT registerMemBaseVG;
++ gctUINT registerMemSizeVG;
++ gctUINT contiguousSize;
++ gctUINT contiguousBase;
++ gctUINT contiguousRequested;
++ gctUINT bankSize;
++ gctINT fastClear;
++ gctINT compression;
++ gctINT powerManagement;
++ gctINT gpuProfiler;
++ gctINT signal;
++ gctUINT baseAddress;
++ gctUINT physSize;
++ gctUINT logFileSize;
++ gctUINT recovery;
++ gctUINT stuckDump;
++ gctUINT showArgs;
++ gctUINT gpu3DMinClock;
++}
++gcsMODULE_PARAMETERS;
++
++typedef struct _gcsPLATFORM * gckPLATFORM;
++
++typedef struct _gcsPLATFORM_OPERATIONS
++{
++ /*******************************************************************************
++ **
++ ** needAddDevice
++ **
++ ** Determine whether platform_device is created by initialization code.
++ ** If platform_device is created by BSP, return gcvFLASE here.
++ */
++ gctBOOL
++ (*needAddDevice)(
++ IN gckPLATFORM Platform
++ );
++
++ /*******************************************************************************
++ **
++ ** adjustParam
++ **
++ ** Override content of arguments, if a argument is not changed here, it will
++ ** keep as default value or value set by insmod command line.
++ */
++ gceSTATUS
++ (*adjustParam)(
++ IN gckPLATFORM Platform,
++ OUT gcsMODULE_PARAMETERS *Args
++ );
++
++ /*******************************************************************************
++ **
++ ** adjustDriver
++ **
++ ** Override content of platform_driver which will be registered.
++ */
++ gceSTATUS
++ (*adjustDriver)(
++ IN gckPLATFORM Platform
++ );
++
++ /*******************************************************************************
++ **
++ ** getPower
++ **
++ ** Prepare power and clock operation.
++ */
++ gceSTATUS
++ (*getPower)(
++ IN gckPLATFORM Platform
++ );
++
++ /*******************************************************************************
++ **
++ ** putPower
++ **
++ ** Finish power and clock operation.
++ */
++ gceSTATUS
++ (*putPower)(
++ IN gckPLATFORM Platform
++ );
++
++ /*******************************************************************************
++ **
++ ** allocPriv
++ **
++ ** Construct platform private data.
++ */
++ gceSTATUS
++ (*allocPriv)(
++ IN gckPLATFORM Platform
++ );
++
++ /*******************************************************************************
++ **
++ ** freePriv
++ **
++ ** free platform private data.
++ */
++ gceSTATUS
++ (*freePriv)(
++ IN gckPLATFORM Platform
++ );
++
++ /*******************************************************************************
++ **
++ ** setPower
++ **
++ ** Set power state of specified GPU.
++ **
++ ** INPUT:
++ **
++ ** gceCORE GPU
++ ** GPU neeed to config.
++ **
++ ** gceBOOL Enable
++ ** Enable or disable power.
++ */
++ gceSTATUS
++ (*setPower)(
++ IN gckPLATFORM Platform,
++ IN gceCORE GPU,
++ IN gctBOOL Enable
++ );
++
++ /*******************************************************************************
++ **
++ ** setClock
++ **
++ ** Set clock state of specified GPU.
++ **
++ ** INPUT:
++ **
++ ** gceCORE GPU
++ ** GPU neeed to config.
++ **
++ ** gceBOOL Enable
++ ** Enable or disable clock.
++ */
++ gceSTATUS
++ (*setClock)(
++ IN gckPLATFORM Platform,
++ IN gceCORE GPU,
++ IN gctBOOL Enable
++ );
++
++ /*******************************************************************************
++ **
++ ** reset
++ **
++ ** Reset GPU outside.
++ **
++ ** INPUT:
++ **
++ ** gceCORE GPU
++ ** GPU neeed to reset.
++ */
++ gceSTATUS
++ (*reset)(
++ IN gckPLATFORM Platform,
++ IN gceCORE GPU
++ );
++
++ /*******************************************************************************
++ **
++ ** getGPUPhysical
++ **
++ ** Convert CPU physical address to GPU physical address if they are
++ ** different.
++ */
++ gceSTATUS
++ (*getGPUPhysical)(
++ IN gckPLATFORM Platform,
++ IN gctUINT32 CPUPhysical,
++ OUT gctUINT32_PTR GPUPhysical
++ );
++
++ /*******************************************************************************
++ **
++ ** adjustProt
++ **
++ ** Override Prot flag when mapping paged memory to userspace.
++ */
++ gceSTATUS
++ (*adjustProt)(
++ IN struct vm_area_struct * vma
++ );
++
++ /*******************************************************************************
++ **
++ ** shrinkMemory
++ **
++ ** Do something to collect memory, eg, act as oom killer.
++ */
++ gceSTATUS
++ (*shrinkMemory)(
++ IN gckPLATFORM Platform
++ );
++
++ /*******************************************************************************
++ **
++ ** cache
++ **
++ ** Cache operation.
++ */
++ gceSTATUS
++ (*cache)(
++ IN gckPLATFORM Platform,
++ IN gctUINT32 ProcessID,
++ IN gctPHYS_ADDR Handle,
++ IN gctUINT32 Physical,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes,
++ IN gceCACHEOPERATION Operation
++ );
++}
++gcsPLATFORM_OPERATIONS;
++
++typedef struct _gcsPLATFORM
++{
++ struct platform_device* device;
++ struct platform_driver* driver;
++
++ gcsPLATFORM_OPERATIONS* ops;
++
++ void* priv;
++}
++gcsPLATFORM;
++
++void
++gckPLATFORM_QueryOperations(
++ IN gcsPLATFORM_OPERATIONS ** Operations
++ );
++
++#endif
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_probe.c linux-xbian-imx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_probe.c
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_probe.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_probe.c 2015-07-27 23:13:06.226765901 +0200
+@@ -0,0 +1,1347 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include <linux/device.h>
++#include <linux/slab.h>
++
++#include "gc_hal_kernel_linux.h"
++#include "gc_hal_driver.h"
++
++#if USE_PLATFORM_DRIVER
++# include <linux/platform_device.h>
++#endif
++
++#ifdef CONFIG_PXA_DVFM
++# include <mach/dvfm.h>
++# include <mach/pxa3xx_dvfm.h>
++#endif
++
++
++/* Zone used for header/footer. */
++#define _GC_OBJ_ZONE gcvZONE_DRIVER
++
++MODULE_DESCRIPTION("Vivante Graphics Driver");
++MODULE_LICENSE("GPL");
++
++static struct class* gpuClass;
++
++static gcsPLATFORM platform;
++
++static gckGALDEVICE galDevice;
++
++static uint major = 199;
++module_param(major, uint, 0644);
++
++#if gcdMULTI_GPU || gcdMULTI_GPU_AFFINITY
++static int irqLine3D0 = -1;
++module_param(irqLine3D0, int, 0644);
++
++static ulong registerMemBase3D0 = 0;
++module_param(registerMemBase3D0, ulong, 0644);
++
++static ulong registerMemSize3D0 = 2 << 10;
++module_param(registerMemSize3D0, ulong, 0644);
++
++static int irqLine3D1 = -1;
++module_param(irqLine3D1, int, 0644);
++
++static ulong registerMemBase3D1 = 0;
++module_param(registerMemBase3D1, ulong, 0644);
++
++static ulong registerMemSize3D1 = 2 << 10;
++module_param(registerMemSize3D1, ulong, 0644);
++#else
++static int irqLine = -1;
++module_param(irqLine, int, 0644);
++
++static ulong registerMemBase = 0x80000000;
++module_param(registerMemBase, ulong, 0644);
++
++static ulong registerMemSize = 2 << 10;
++module_param(registerMemSize, ulong, 0644);
++#endif
++
++static int irqLine2D = -1;
++module_param(irqLine2D, int, 0644);
++
++static ulong registerMemBase2D = 0x00000000;
++module_param(registerMemBase2D, ulong, 0644);
++
++static ulong registerMemSize2D = 2 << 10;
++module_param(registerMemSize2D, ulong, 0644);
++
++static int irqLineVG = -1;
++module_param(irqLineVG, int, 0644);
++
++static ulong registerMemBaseVG = 0x00000000;
++module_param(registerMemBaseVG, ulong, 0644);
++
++static ulong registerMemSizeVG = 2 << 10;
++module_param(registerMemSizeVG, ulong, 0644);
++
++#ifndef gcdDEFAULT_CONTIGUOUS_SIZE
++#define gcdDEFAULT_CONTIGUOUS_SIZE (4 << 20)
++#endif
++static ulong contiguousSize = gcdDEFAULT_CONTIGUOUS_SIZE;
++module_param(contiguousSize, ulong, 0644);
++
++static ulong contiguousBase = 0;
++module_param(contiguousBase, ulong, 0644);
++
++static ulong bankSize = 0;
++module_param(bankSize, ulong, 0644);
++
++static int fastClear = -1;
++module_param(fastClear, int, 0644);
++
++static int compression = -1;
++module_param(compression, int, 0644);
++
++static int powerManagement = -1;
++module_param(powerManagement, int, 0644);
++
++static int gpuProfiler = 0;
++module_param(gpuProfiler, int, 0644);
++
++static int signal = 48;
++module_param(signal, int, 0644);
++
++static ulong baseAddress = 0;
++module_param(baseAddress, ulong, 0644);
++
++static ulong physSize = 0;
++module_param(physSize, ulong, 0644);
++
++static uint logFileSize = 0;
++module_param(logFileSize,uint, 0644);
++
++static uint recovery = 1;
++module_param(recovery, uint, 0644);
++MODULE_PARM_DESC(recovery, "Recover GPU from stuck (1: Enable, 0: Disable)");
++
++/* Middle needs about 40KB buffer, Maximal may need more than 200KB buffer. */
++static uint stuckDump = 1;
++module_param(stuckDump, uint, 0644);
++MODULE_PARM_DESC(stuckDump, "Level of stuck dump content (1: Minimal, 2: Middle, 3: Maximal)");
++
++static int showArgs = 0;
++module_param(showArgs, int, 0644);
++
++static int mmu = 1;
++module_param(mmu, int, 0644);
++
++static int gpu3DMinClock = 1;
++
++static int contiguousRequested = 0;
++
++static int drv_open(
++ struct inode* inode,
++ struct file* filp
++ );
++
++static int drv_release(
++ struct inode* inode,
++ struct file* filp
++ );
++
++static long drv_ioctl(
++ struct file* filp,
++ unsigned int ioctlCode,
++ unsigned long arg
++ );
++
++static int drv_mmap(
++ struct file* filp,
++ struct vm_area_struct* vma
++ );
++
++static struct file_operations driver_fops =
++{
++ .owner = THIS_MODULE,
++ .open = drv_open,
++ .release = drv_release,
++ .unlocked_ioctl = drv_ioctl,
++#ifdef HAVE_COMPAT_IOCTL
++ .compat_ioctl = drv_ioctl,
++#endif
++ .mmap = drv_mmap,
++};
++
++void
++_UpdateModuleParam(
++ gcsMODULE_PARAMETERS *Param
++ )
++{
++#if gcdMULTI_GPU || gcdMULTI_GPU_AFFINITY
++#else
++ irqLine = Param->irqLine ;
++ registerMemBase = Param->registerMemBase;
++ registerMemSize = Param->registerMemSize;
++#endif
++ irqLine2D = Param->irqLine2D ;
++ registerMemBase2D = Param->registerMemBase2D;
++ registerMemSize2D = Param->registerMemSize2D;
++ irqLineVG = Param->irqLineVG;
++ registerMemBaseVG = Param->registerMemBaseVG;
++ registerMemSizeVG = Param->registerMemSizeVG;
++ contiguousSize = Param->contiguousSize;
++ contiguousBase = Param->contiguousBase;
++ bankSize = Param->bankSize;
++ fastClear = Param->fastClear;
++ compression = Param->compression;
++ powerManagement = Param->powerManagement;
++ gpuProfiler = Param->gpuProfiler;
++ signal = Param->signal;
++ baseAddress = Param->baseAddress;
++ physSize = Param->physSize;
++ logFileSize = Param->logFileSize;
++ recovery = Param->recovery;
++ stuckDump = Param->stuckDump;
++ showArgs = Param->showArgs;
++ contiguousRequested = Param->contiguousRequested;
++ gpu3DMinClock = Param->gpu3DMinClock;
++}
++
++void
++gckOS_DumpParam(
++ void
++ )
++{
++ printk("Galcore options:\n");
++#if gcdMULTI_GPU || gcdMULTI_GPU_AFFINITY
++ printk(" irqLine3D0 = %d\n", irqLine3D0);
++ printk(" registerMemBase3D0 = 0x%08lX\n", registerMemBase3D0);
++ printk(" registerMemSize3D0 = 0x%08lX\n", registerMemSize3D0);
++
++ if (irqLine3D1 != -1)
++ {
++ printk(" irqLine3D1 = %d\n", irqLine3D1);
++ printk(" registerMemBase3D1 = 0x%08lX\n", registerMemBase3D1);
++ printk(" registerMemSize3D1 = 0x%08lX\n", registerMemSize3D1);
++ }
++#else
++ printk(" irqLine = %d\n", irqLine);
++ printk(" registerMemBase = 0x%08lX\n", registerMemBase);
++ printk(" registerMemSize = 0x%08lX\n", registerMemSize);
++#endif
++
++ if (irqLine2D != -1)
++ {
++ printk(" irqLine2D = %d\n", irqLine2D);
++ printk(" registerMemBase2D = 0x%08lX\n", registerMemBase2D);
++ printk(" registerMemSize2D = 0x%08lX\n", registerMemSize2D);
++ }
++
++ if (irqLineVG != -1)
++ {
++ printk(" irqLineVG = %d\n", irqLineVG);
++ printk(" registerMemBaseVG = 0x%08lX\n", registerMemBaseVG);
++ printk(" registerMemSizeVG = 0x%08lX\n", registerMemSizeVG);
++ }
++
++ printk(" contiguousSize = %ld\n", contiguousSize);
++ printk(" contiguousBase = 0x%08lX\n", contiguousBase);
++ printk(" bankSize = 0x%08lX\n", bankSize);
++ printk(" fastClear = %d\n", fastClear);
++ printk(" compression = %d\n", compression);
++ printk(" signal = %d\n", signal);
++ printk(" powerManagement = %d\n", powerManagement);
++ printk(" baseAddress = 0x%08lX\n", baseAddress);
++ printk(" physSize = 0x%08lX\n", physSize);
++ printk(" logFileSize = %d KB \n", logFileSize);
++ printk(" recovery = %d\n", recovery);
++ printk(" stuckDump = %d\n", stuckDump);
++ printk(" gpuProfiler = %d\n", gpuProfiler);
++}
++
++int drv_open(
++ struct inode* inode,
++ struct file* filp
++ )
++{
++ gceSTATUS status;
++ gctBOOL attached = gcvFALSE;
++ gcsHAL_PRIVATE_DATA_PTR data = gcvNULL;
++ gctINT i;
++
++ gcmkHEADER_ARG("inode=0x%08X filp=0x%08X", inode, filp);
++
++ if (filp == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): filp is NULL\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ data = kmalloc(sizeof(gcsHAL_PRIVATE_DATA), GFP_KERNEL | __GFP_NOWARN);
++
++ if (data == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): private_data is NULL\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ data->device = galDevice;
++ data->mappedMemory = gcvNULL;
++ data->contiguousLogical = gcvNULL;
++ gcmkONERROR(gckOS_GetProcessID(&data->pidOpen));
++
++ /* Attached the process. */
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ if (galDevice->kernels[i] != gcvNULL)
++ {
++ gcmkONERROR(gckKERNEL_AttachProcess(galDevice->kernels[i], gcvTRUE));
++ }
++ }
++ attached = gcvTRUE;
++
++ if (!galDevice->contiguousMapped)
++ {
++ if (galDevice->contiguousPhysical != gcvNULL)
++ {
++ gcmkONERROR(gckOS_MapMemory(
++ galDevice->os,
++ galDevice->contiguousPhysical,
++ galDevice->contiguousSize,
++ &data->contiguousLogical
++ ));
++ }
++ }
++
++ filp->private_data = data;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return 0;
++
++OnError:
++ if (data != gcvNULL)
++ {
++ if (data->contiguousLogical != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_UnmapMemory(
++ galDevice->os,
++ galDevice->contiguousPhysical,
++ galDevice->contiguousSize,
++ data->contiguousLogical
++ ));
++ }
++
++ kfree(data);
++ }
++
++ if (attached)
++ {
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ if (galDevice->kernels[i] != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckKERNEL_AttachProcess(galDevice->kernels[i], gcvFALSE));
++ }
++ }
++ }
++
++ gcmkFOOTER();
++ return -ENOTTY;
++}
++
++int drv_release(
++ struct inode* inode,
++ struct file* filp
++ )
++{
++ gceSTATUS status;
++ gcsHAL_PRIVATE_DATA_PTR data;
++ gckGALDEVICE device;
++ gctINT i;
++
++ gcmkHEADER_ARG("inode=0x%08X filp=0x%08X", inode, filp);
++
++ if (filp == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): filp is NULL\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ data = filp->private_data;
++
++ if (data == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): private_data is NULL\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ device = data->device;
++
++ if (device == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): device is NULL\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ if (!device->contiguousMapped)
++ {
++ if (data->contiguousLogical != gcvNULL)
++ {
++ gcmkONERROR(gckOS_UnmapMemoryEx(
++ galDevice->os,
++ galDevice->contiguousPhysical,
++ galDevice->contiguousSize,
++ data->contiguousLogical,
++ data->pidOpen
++ ));
++
++ data->contiguousLogical = gcvNULL;
++ }
++ }
++
++ /* A process gets detached. */
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ if (galDevice->kernels[i] != gcvNULL)
++ {
++ gcmkONERROR(gckKERNEL_AttachProcessEx(galDevice->kernels[i], gcvFALSE, data->pidOpen));
++ }
++ }
++
++ kfree(data);
++ filp->private_data = NULL;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return 0;
++
++OnError:
++ gcmkFOOTER();
++ return -ENOTTY;
++}
++
++long drv_ioctl(
++ struct file* filp,
++ unsigned int ioctlCode,
++ unsigned long arg
++ )
++{
++ gceSTATUS status;
++ gcsHAL_INTERFACE iface;
++ gctUINT32 copyLen;
++ DRIVER_ARGS drvArgs;
++ gckGALDEVICE device;
++ gcsHAL_PRIVATE_DATA_PTR data;
++ gctINT32 i, count;
++ gckVIDMEM_NODE nodeObject;
++
++ gcmkHEADER_ARG(
++ "filp=0x%08X ioctlCode=0x%08X arg=0x%08X",
++ filp, ioctlCode, arg
++ );
++
++ if (filp == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): filp is NULL\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ data = filp->private_data;
++
++ if (data == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): private_data is NULL\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ device = data->device;
++
++ if (device == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): device is NULL\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ if ((ioctlCode != IOCTL_GCHAL_INTERFACE)
++ && (ioctlCode != IOCTL_GCHAL_KERNEL_INTERFACE)
++ )
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): unknown command %d\n",
++ __FUNCTION__, __LINE__,
++ ioctlCode
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ /* Get the drvArgs. */
++ copyLen = copy_from_user(
++ &drvArgs, (void *) arg, sizeof(DRIVER_ARGS)
++ );
++
++ if (copyLen != 0)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): error copying of the input arguments.\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ /* Now bring in the gcsHAL_INTERFACE structure. */
++ if ((drvArgs.InputBufferSize != sizeof(gcsHAL_INTERFACE))
++ || (drvArgs.OutputBufferSize != sizeof(gcsHAL_INTERFACE))
++ )
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): input or/and output structures are invalid.\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ copyLen = copy_from_user(
++ &iface, gcmUINT64_TO_PTR(drvArgs.InputBuffer), sizeof(gcsHAL_INTERFACE)
++ );
++
++ if (copyLen != 0)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): error copying of input HAL interface.\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ if (iface.command == gcvHAL_CHIP_INFO)
++ {
++ count = 0;
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ if (device->kernels[i] != gcvNULL)
++ {
++#if gcdENABLE_VG
++ if (i == gcvCORE_VG)
++ {
++ iface.u.ChipInfo.types[count] = gcvHARDWARE_VG;
++ }
++ else
++#endif
++ {
++ gcmkVERIFY_OK(gckHARDWARE_GetType(device->kernels[i]->hardware,
++ &iface.u.ChipInfo.types[count]));
++ }
++ count++;
++ }
++ }
++
++ iface.u.ChipInfo.count = count;
++ iface.status = status = gcvSTATUS_OK;
++ }
++ else
++ {
++ if (iface.hardwareType > 7)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): unknown hardwareType %d\n",
++ __FUNCTION__, __LINE__,
++ iface.hardwareType
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++#if gcdENABLE_VG
++ if (device->coreMapping[iface.hardwareType] == gcvCORE_VG)
++ {
++ status = gckVGKERNEL_Dispatch(device->kernels[gcvCORE_VG],
++ (ioctlCode == IOCTL_GCHAL_INTERFACE),
++ &iface);
++ }
++ else
++#endif
++ {
++ status = gckKERNEL_Dispatch(device->kernels[device->coreMapping[iface.hardwareType]],
++ (ioctlCode == IOCTL_GCHAL_INTERFACE),
++ &iface);
++ }
++ }
++
++ /* Redo system call after pending signal is handled. */
++ if (status == gcvSTATUS_INTERRUPTED)
++ {
++ gcmkFOOTER();
++ return -ERESTARTSYS;
++ }
++
++ if (gcmIS_SUCCESS(status) && (iface.command == gcvHAL_LOCK_VIDEO_MEMORY))
++ {
++ gcuVIDMEM_NODE_PTR node;
++ gctUINT32 processID;
++
++ gckOS_GetProcessID(&processID);
++
++ gcmkONERROR(gckVIDMEM_HANDLE_Lookup(device->kernels[device->coreMapping[iface.hardwareType]],
++ processID,
++ (gctUINT32)iface.u.LockVideoMemory.node,
++ &nodeObject));
++ node = nodeObject->node;
++
++ /* Special case for mapped memory. */
++ if ((data->mappedMemory != gcvNULL)
++ && (node->VidMem.memory->object.type == gcvOBJ_VIDMEM)
++ )
++ {
++ /* Compute offset into mapped memory. */
++ gctUINT32 offset
++ = (gctUINT8 *) gcmUINT64_TO_PTR(iface.u.LockVideoMemory.memory)
++ - (gctUINT8 *) device->contiguousBase;
++
++ /* Compute offset into user-mapped region. */
++ iface.u.LockVideoMemory.memory =
++ gcmPTR_TO_UINT64((gctUINT8 *) data->mappedMemory + offset);
++ }
++ }
++
++ /* Copy data back to the user. */
++ copyLen = copy_to_user(
++ gcmUINT64_TO_PTR(drvArgs.OutputBuffer), &iface, sizeof(gcsHAL_INTERFACE)
++ );
++
++ if (copyLen != 0)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): error copying of output HAL interface.\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return 0;
++
++OnError:
++ gcmkFOOTER();
++ return -ENOTTY;
++}
++
++static int drv_mmap(
++ struct file* filp,
++ struct vm_area_struct* vma
++ )
++{
++ gceSTATUS status = gcvSTATUS_OK;
++ gcsHAL_PRIVATE_DATA_PTR data;
++ gckGALDEVICE device;
++
++ gcmkHEADER_ARG("filp=0x%08X vma=0x%08X", filp, vma);
++
++ if (filp == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): filp is NULL\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ data = filp->private_data;
++
++ if (data == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): private_data is NULL\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ device = data->device;
++
++ if (device == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): device is NULL\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++#if !gcdPAGED_MEMORY_CACHEABLE
++ vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
++ vma->vm_flags |= gcdVM_FLAGS;
++#endif
++ vma->vm_pgoff = 0;
++
++ if (device->contiguousMapped)
++ {
++ unsigned long size = vma->vm_end - vma->vm_start;
++ int ret = 0;
++
++ if (size > device->contiguousSize)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Invalid mapping size.\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ ret = io_remap_pfn_range(
++ vma,
++ vma->vm_start,
++ device->requestedContiguousBase >> PAGE_SHIFT,
++ size,
++ vma->vm_page_prot
++ );
++
++ if (ret != 0)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): io_remap_pfn_range failed %d\n",
++ __FUNCTION__, __LINE__,
++ ret
++ );
++
++ data->mappedMemory = gcvNULL;
++
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++ data->mappedMemory = (gctPOINTER) vma->vm_start;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return 0;
++ }
++
++OnError:
++ gcmkFOOTER();
++ return -ENOTTY;
++}
++
++
++#if !USE_PLATFORM_DRIVER
++static int __init drv_init(void)
++#else
++static int drv_init(void)
++#endif
++{
++ int ret;
++ int result = -EINVAL;
++ gceSTATUS status;
++ gckGALDEVICE device = gcvNULL;
++ struct class* device_class = gcvNULL;
++
++ gcsDEVICE_CONSTRUCT_ARGS args = {
++ .recovery = recovery,
++ .stuckDump = stuckDump,
++ .gpu3DMinClock = gpu3DMinClock,
++ .contiguousRequested = contiguousRequested,
++ .platform = &platform,
++ .mmu = mmu,
++ };
++
++ gcmkHEADER();
++
++ printk(KERN_INFO "Galcore version %d.%d.%d.%d\n",
++ gcvVERSION_MAJOR, gcvVERSION_MINOR, gcvVERSION_PATCH, gcvVERSION_BUILD);
++
++#if !VIVANTE_PROFILER_PM
++ /* when enable gpu profiler, we need to turn off gpu powerMangement */
++ if (gpuProfiler)
++ {
++ powerManagement = 0;
++ }
++#endif
++
++ if (showArgs)
++ {
++ gckOS_DumpParam();
++ }
++
++ if (logFileSize != 0)
++ {
++ gckDEBUGFS_Initialize();
++ }
++
++ /* Create the GAL device. */
++ status = gckGALDEVICE_Construct(
++#if gcdMULTI_GPU || gcdMULTI_GPU_AFFINITY
++ irqLine3D0,
++ registerMemBase3D0, registerMemSize3D0,
++ irqLine3D1,
++ registerMemBase3D1, registerMemSize3D1,
++#else
++ irqLine,
++ registerMemBase, registerMemSize,
++#endif
++ irqLine2D,
++ registerMemBase2D, registerMemSize2D,
++ irqLineVG,
++ registerMemBaseVG, registerMemSizeVG,
++ contiguousBase, contiguousSize,
++ bankSize, fastClear, compression, baseAddress, physSize, signal,
++ logFileSize,
++ powerManagement,
++ gpuProfiler,
++ &args,
++ &device
++ );
++
++ if (gcmIS_ERROR(status))
++ {
++ gcmkTRACE_ZONE(gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Failed to create the GAL device: status=%d\n",
++ __FUNCTION__, __LINE__, status);
++
++ goto OnError;
++ }
++
++ /* Start the GAL device. */
++ gcmkONERROR(gckGALDEVICE_Start(device));
++
++ if ((physSize != 0)
++ && (device->kernels[gcvCORE_MAJOR] != gcvNULL)
++ && (device->kernels[gcvCORE_MAJOR]->hardware->mmuVersion != 0))
++ {
++ /* Reset the base address */
++ device->baseAddress = 0;
++ }
++
++ /* Register the character device. */
++ ret = register_chrdev(major, DEVICE_NAME, &driver_fops);
++
++ if (ret < 0)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Could not allocate major number for mmap.\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ if (major == 0)
++ {
++ major = ret;
++ }
++
++ /* Create the device class. */
++ device_class = class_create(THIS_MODULE, "graphics_class");
++
++ if (IS_ERR(device_class))
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Failed to create the class.\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
++ device_create(device_class, NULL, MKDEV(major, 0), NULL, DEVICE_NAME);
++#else
++ device_create(device_class, NULL, MKDEV(major, 0), DEVICE_NAME);
++#endif
++
++ galDevice = device;
++ gpuClass = device_class;
++
++#if gcdMULTI_GPU || gcdMULTI_GPU_AFFINITY
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_DRIVER,
++ "%s(%d): irqLine3D0=%d, contiguousSize=%lu, memBase3D0=0x%lX\n",
++ __FUNCTION__, __LINE__,
++ irqLine3D0, contiguousSize, registerMemBase3D0
++ );
++#else
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_DRIVER,
++ "%s(%d): irqLine=%d, contiguousSize=%lu, memBase=0x%lX\n",
++ __FUNCTION__, __LINE__,
++ irqLine, contiguousSize, registerMemBase
++ );
++#endif
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return 0;
++
++OnError:
++ /* Roll back. */
++ if (device_class != gcvNULL)
++ {
++ device_destroy(device_class, MKDEV(major, 0));
++ class_destroy(device_class);
++ }
++
++ if (device != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckGALDEVICE_Stop(device));
++ gcmkVERIFY_OK(gckGALDEVICE_Destroy(device));
++ }
++
++ gcmkFOOTER();
++ return result;
++}
++
++#if !USE_PLATFORM_DRIVER
++static void __exit drv_exit(void)
++#else
++static void drv_exit(void)
++#endif
++{
++ gcmkHEADER();
++
++ gcmkASSERT(gpuClass != gcvNULL);
++ device_destroy(gpuClass, MKDEV(major, 0));
++ class_destroy(gpuClass);
++
++ unregister_chrdev(major, DEVICE_NAME);
++
++ gcmkVERIFY_OK(gckGALDEVICE_Stop(galDevice));
++ gcmkVERIFY_OK(gckGALDEVICE_Destroy(galDevice));
++
++ if(gckDEBUGFS_IsEnabled())
++ {
++ gckDEBUGFS_Terminate();
++ }
++
++ gcmkFOOTER_NO();
++}
++
++#if !USE_PLATFORM_DRIVER
++ module_init(drv_init);
++ module_exit(drv_exit);
++#else
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)
++static int gpu_probe(struct platform_device *pdev)
++#else
++static int __devinit gpu_probe(struct platform_device *pdev)
++#endif
++{
++ int ret = -ENODEV;
++ gcsMODULE_PARAMETERS moduleParam = {
++#if gcdMULTI_GPU || gcdMULTI_GPU_AFFINITY
++#else
++ .irqLine = irqLine,
++ .registerMemBase = registerMemBase,
++ .registerMemSize = registerMemSize,
++#endif
++ .irqLine2D = irqLine2D,
++ .registerMemBase2D = registerMemBase2D,
++ .registerMemSize2D = registerMemSize2D,
++ .irqLineVG = irqLineVG,
++ .registerMemBaseVG = registerMemBaseVG,
++ .registerMemSizeVG = registerMemSizeVG,
++ .contiguousSize = contiguousSize,
++ .contiguousBase = contiguousBase,
++ .bankSize = bankSize,
++ .fastClear = fastClear,
++ .compression = compression,
++ .powerManagement = powerManagement,
++ .gpuProfiler = gpuProfiler,
++ .signal = signal,
++ .baseAddress = baseAddress,
++ .physSize = physSize,
++ .logFileSize = logFileSize,
++ .recovery = recovery,
++ .stuckDump = stuckDump,
++ .showArgs = showArgs,
++ .gpu3DMinClock = gpu3DMinClock,
++ };
++
++ gcmkHEADER();
++
++ platform.device = pdev;
++
++ if (platform.ops->getPower)
++ {
++ if (gcmIS_ERROR(platform.ops->getPower(&platform)))
++ {
++ gcmkFOOTER_NO();
++ return ret;
++ }
++ }
++
++ if (platform.ops->adjustParam)
++ {
++ /* Override default module param. */
++ platform.ops->adjustParam(&platform, &moduleParam);
++
++ /* Update module param because drv_init() uses them directly. */
++ _UpdateModuleParam(&moduleParam);
++ }
++
++ ret = drv_init();
++
++ if (!ret)
++ {
++ platform_set_drvdata(pdev, galDevice);
++
++ gcmkFOOTER_NO();
++ return ret;
++ }
++
++ gcmkFOOTER_ARG(KERN_INFO "Failed to register gpu driver: %d\n", ret);
++ return ret;
++}
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)
++static int gpu_remove(struct platform_device *pdev)
++#else
++static int __devexit gpu_remove(struct platform_device *pdev)
++#endif
++{
++ gcmkHEADER();
++
++ drv_exit();
++
++ if (platform.ops->putPower)
++ {
++ platform.ops->putPower(&platform);
++ }
++
++ gcmkFOOTER_NO();
++ return 0;
++}
++
++static int gpu_suspend(struct platform_device *dev, pm_message_t state)
++{
++ gceSTATUS status;
++ gckGALDEVICE device;
++ gctINT i;
++
++ device = platform_get_drvdata(dev);
++
++ if (!device)
++ {
++ return -1;
++ }
++
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ if (device->kernels[i] != gcvNULL)
++ {
++ /* Store states. */
++#if gcdENABLE_VG
++ if (i == gcvCORE_VG)
++ {
++ status = gckVGHARDWARE_QueryPowerManagementState(device->kernels[i]->vg->hardware, &device->statesStored[i]);
++ }
++ else
++#endif
++ {
++ status = gckHARDWARE_QueryPowerManagementState(device->kernels[i]->hardware, &device->statesStored[i]);
++ }
++
++ if (gcmIS_ERROR(status))
++ {
++ return -1;
++ }
++
++#if gcdENABLE_VG
++ if (i == gcvCORE_VG)
++ {
++ status = gckVGHARDWARE_SetPowerManagementState(device->kernels[i]->vg->hardware, gcvPOWER_OFF);
++ }
++ else
++#endif
++ {
++ status = gckHARDWARE_SetPowerManagementState(device->kernels[i]->hardware, gcvPOWER_OFF);
++ }
++
++ if (gcmIS_ERROR(status))
++ {
++ return -1;
++ }
++
++ }
++ }
++
++ return 0;
++}
++
++static int gpu_resume(struct platform_device *dev)
++{
++ gceSTATUS status;
++ gckGALDEVICE device;
++ gctINT i;
++ gceCHIPPOWERSTATE statesStored;
++
++ device = platform_get_drvdata(dev);
++
++ if (!device)
++ {
++ return -1;
++ }
++
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ if (device->kernels[i] != gcvNULL)
++ {
++#if gcdENABLE_VG
++ if (i == gcvCORE_VG)
++ {
++ status = gckVGHARDWARE_SetPowerManagementState(device->kernels[i]->vg->hardware, gcvPOWER_ON);
++ }
++ else
++#endif
++ {
++ status = gckHARDWARE_SetPowerManagementState(device->kernels[i]->hardware, gcvPOWER_ON);
++ }
++
++ if (gcmIS_ERROR(status))
++ {
++ return -1;
++ }
++
++ /* Convert global state to crossponding internal state. */
++ switch(device->statesStored[i])
++ {
++ case gcvPOWER_OFF:
++ statesStored = gcvPOWER_OFF_BROADCAST;
++ break;
++ case gcvPOWER_IDLE:
++ statesStored = gcvPOWER_IDLE_BROADCAST;
++ break;
++ case gcvPOWER_SUSPEND:
++ statesStored = gcvPOWER_SUSPEND_BROADCAST;
++ break;
++ case gcvPOWER_ON:
++ statesStored = gcvPOWER_ON_AUTO;
++ break;
++ default:
++ statesStored = device->statesStored[i];
++ break;
++ }
++
++ /* Restore states. */
++#if gcdENABLE_VG
++ if (i == gcvCORE_VG)
++ {
++ status = gckVGHARDWARE_SetPowerManagementState(device->kernels[i]->vg->hardware, statesStored);
++ }
++ else
++#endif
++ {
++ status = gckHARDWARE_SetPowerManagementState(device->kernels[i]->hardware, statesStored);
++ }
++
++ if (gcmIS_ERROR(status))
++ {
++ return -1;
++ }
++ }
++ }
++
++ return 0;
++}
++
++#if defined(CONFIG_PM) && LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 30)
++#ifdef CONFIG_PM_SLEEP
++static int gpu_system_suspend(struct device *dev)
++{
++ pm_message_t state={0};
++ return gpu_suspend(to_platform_device(dev), state);
++}
++
++static int gpu_system_resume(struct device *dev)
++{
++ return gpu_resume(to_platform_device(dev));
++}
++#endif
++
++static const struct dev_pm_ops gpu_pm_ops = {
++ SET_SYSTEM_SLEEP_PM_OPS(gpu_system_suspend, gpu_system_resume)
++};
++#endif
++
++static struct platform_driver gpu_driver = {
++ .probe = gpu_probe,
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)
++ .remove = gpu_remove,
++#else
++ .remove = __devexit_p(gpu_remove),
++#endif
++
++ .suspend = gpu_suspend,
++ .resume = gpu_resume,
++
++ .driver = {
++ .name = DEVICE_NAME,
++#if defined(CONFIG_PM) && LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 30)
++ .pm = &gpu_pm_ops,
++#endif
++ }
++};
++
++static int __init gpu_init(void)
++{
++ int ret = 0;
++
++ memset(&platform, 0, sizeof(gcsPLATFORM));
++
++ gckPLATFORM_QueryOperations(&platform.ops);
++
++ if (platform.ops == gcvNULL)
++ {
++ printk(KERN_ERR "galcore: No platform specific operations.\n");
++ ret = -ENODEV;
++ goto out;
++ }
++
++ if (platform.ops->allocPriv)
++ {
++ /* Allocate platform private data. */
++ if (gcmIS_ERROR(platform.ops->allocPriv(&platform)))
++ {
++ ret = -ENOMEM;
++ goto out;
++ }
++ }
++
++ if (platform.ops->needAddDevice
++ && platform.ops->needAddDevice(&platform))
++ {
++ /* Allocate device */
++ platform.device = platform_device_alloc(DEVICE_NAME, -1);
++ if (!platform.device)
++ {
++ printk(KERN_ERR "galcore: platform_device_alloc failed.\n");
++ ret = -ENOMEM;
++ goto out;
++ }
++
++ /* Add device */
++ ret = platform_device_add(platform.device);
++ if (ret)
++ {
++ printk(KERN_ERR "galcore: platform_device_add failed.\n");
++ goto put_dev;
++ }
++ }
++
++ platform.driver = &gpu_driver;
++
++ if (platform.ops->adjustDriver)
++ {
++ /* Override default platform_driver struct. */
++ platform.ops->adjustDriver(&platform);
++ }
++
++ ret = platform_driver_register(&gpu_driver);
++ if (!ret)
++ {
++ goto out;
++ }
++
++ platform_device_del(platform.device);
++put_dev:
++ platform_device_put(platform.device);
++
++out:
++ return ret;
++}
++
++static void __exit gpu_exit(void)
++{
++ platform_driver_unregister(&gpu_driver);
++
++ if (platform.ops->needAddDevice
++ && platform.ops->needAddDevice(&platform))
++ {
++ platform_device_unregister(platform.device);
++ }
++
++ if (platform.priv)
++ {
++ /* Free platform private data. */
++ platform.ops->freePriv(&platform);
++ }
++}
++
++module_init(gpu_init);
++module_exit(gpu_exit);
++
++#endif
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_security_channel.c linux-xbian-imx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_security_channel.c
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_security_channel.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_security_channel.c 2015-07-27 23:13:06.226765901 +0200
+@@ -0,0 +1,385 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_linux.h"
++#include <linux/slab.h>
++
++#include "tee_client_api.h"
++
++#define _GC_OBJ_ZONE gcvZONE_OS
++
++#define GPU3D_UUID { 0xcc9f80ea, 0xa836, 0x11e3, { 0x9b, 0x07, 0x78, 0x2b, 0xcb, 0x5c, 0xf3, 0xe3 } }
++
++static const TEEC_UUID gpu3d_uuid = GPU3D_UUID;
++TEEC_Context teecContext;
++
++typedef struct _gcsSecurityChannel {
++ gckOS os;
++ TEEC_Session session;
++ int * virtual;
++ TEEC_SharedMemory inputBuffer;
++ gctUINT32 bytes;
++ gctPOINTER mutex;
++} gcsSecurityChannel;
++
++TEEC_SharedMemory *
++gpu3d_allocate_secure_mem(
++ gckOS Os,
++ unsigned int size
++ )
++{
++ TEEC_Result result;
++ TEEC_Context *context = &teecContext;
++ TEEC_SharedMemory *shm = NULL;
++ void *handle = NULL;
++ unsigned int phyAddr = 0xFFFFFFFF;
++ gceSTATUS status;
++ gctSIZE_T bytes = size;
++
++ shm = kmalloc(sizeof(TEEC_SharedMemory), GFP_KERNEL);
++
++ if (NULL == shm)
++ {
++ return NULL;
++ }
++
++ memset(shm, 0, sizeof(TEEC_SharedMemory));
++
++ status = gckOS_AllocatePagedMemoryEx(
++ Os,
++ gcvALLOC_FLAG_SECURITY,
++ bytes,
++ gcvNULL,
++ (gctPHYS_ADDR *)&handle);
++
++ if (gcmIS_ERROR(status))
++ {
++ kfree(shm);
++ return NULL;
++ }
++
++ status = gckOS_PhysicalToPhysicalAddress(
++ Os,
++ handle,
++ &phyAddr);
++
++ if (gcmIS_ERROR(status))
++ {
++ kfree(shm);
++ return NULL;
++ }
++
++ /* record the handle into shm->user_data */
++ shm->userdata = handle;
++
++ /* [b] Bulk input buffer. */
++ shm->size = size;
++ shm->flags = TEEC_MEM_INPUT;
++
++ /* Use TEE Client API to register the underlying memory buffer. */
++ shm->phyAddr = (void *)phyAddr;
++
++ result = TEEC_RegisterSharedMemory(
++ context,
++ shm);
++
++ if (result != TEEC_SUCCESS)
++ {
++ gckOS_FreePagedMemory(Os, (gctPHYS_ADDR)handle, shm->size);
++ kfree(shm);
++ return NULL;
++ }
++
++ return shm;
++}
++
++void gpu3d_release_secure_mem(
++ gckOS Os,
++ void *shm_handle
++ )
++{
++ TEEC_SharedMemory *shm = shm_handle;
++ void * handle;
++
++ if (!shm)
++ {
++ return;
++ }
++
++ handle = shm->userdata;
++
++ TEEC_ReleaseSharedMemory(shm);
++ gckOS_FreePagedMemory(Os, (gctPHYS_ADDR)handle, shm->size);
++
++ kfree(shm);
++
++ return;
++}
++
++static TEEC_Result gpu3d_session_callback(
++ TEEC_Session* session,
++ uint32_t commandID,
++ TEEC_Operation* operation,
++ void* userdata
++ )
++{
++ gcsSecurityChannel *channel = userdata;
++
++ if (channel == gcvNULL)
++ {
++ return TEEC_ERROR_BAD_PARAMETERS;
++ }
++
++ switch(commandID)
++ {
++ case gcvTA_CALLBACK_ALLOC_SECURE_MEM:
++ {
++ uint32_t size = operation->params[0].value.a;
++ TEEC_SharedMemory *shm = NULL;
++
++ shm = gpu3d_allocate_secure_mem(channel->os, size);
++
++ /* use the value to save the pointer in client side */
++ operation->params[0].value.a = (uint32_t)shm;
++ operation->params[0].value.b = (uint32_t)shm->phyAddr;
++
++ break;
++ }
++ case gcvTA_CALLBACK_FREE_SECURE_MEM:
++ {
++ TEEC_SharedMemory *shm = (TEEC_SharedMemory *)operation->params[0].value.a;
++
++ gpu3d_release_secure_mem(channel->os, shm);
++ break;
++ }
++ default:
++ break;
++ }
++
++ return TEEC_SUCCESS;
++}
++
++gceSTATUS
++gckOS_OpenSecurityChannel(
++ IN gckOS Os,
++ IN gceCORE GPU,
++ OUT gctUINT32 *Channel
++ )
++{
++ gceSTATUS status;
++ TEEC_Result result;
++ static bool initialized = gcvFALSE;
++ gcsSecurityChannel *channel = gcvNULL;
++
++ TEEC_Operation operation = {0};
++
++ /* Connect to TEE. */
++ if (initialized == gcvFALSE)
++ {
++ result = TEEC_InitializeContext(NULL, &teecContext);
++
++ if (result != TEEC_SUCCESS) {
++ gcmkONERROR(gcvSTATUS_CHIP_NOT_READY);
++ }
++
++ initialized = gcvTRUE;
++ }
++
++ /* Construct channel. */
++ gcmkONERROR(
++ gckOS_Allocate(Os, gcmSIZEOF(*channel), (gctPOINTER *)&channel));
++
++ gckOS_ZeroMemory(channel, gcmSIZEOF(gcsSecurityChannel));
++
++ channel->os = Os;
++
++ gcmkONERROR(gckOS_CreateMutex(Os, &channel->mutex));
++
++ /* Allocate shared memory for passing gcTA_INTERFACE. */
++ channel->bytes = gcmSIZEOF(gcsTA_INTERFACE);
++ channel->virtual = kmalloc(channel->bytes, GFP_KERNEL | __GFP_NOWARN);
++
++ if (!channel->virtual)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ channel->inputBuffer.size = channel->bytes;
++ channel->inputBuffer.flags = TEEC_MEM_INPUT | TEEC_MEM_OUTPUT;
++ channel->inputBuffer.phyAddr = (void *)virt_to_phys(channel->virtual);
++
++ result = TEEC_RegisterSharedMemory(&teecContext, &channel->inputBuffer);
++
++ if (result != TEEC_SUCCESS)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++ operation.paramTypes = TEEC_PARAM_TYPES(
++ TEEC_VALUE_INPUT,
++ TEEC_NONE,
++ TEEC_NONE,
++ TEEC_NONE);
++
++ operation.params[0].value.a = GPU;
++
++ /* Open session with TEE application. */
++ result = TEEC_OpenSession(
++ &teecContext,
++ &channel->session,
++ &gpu3d_uuid,
++ TEEC_LOGIN_USER,
++ NULL,
++ &operation,
++ NULL);
++
++ /* Prepare callback. */
++ TEEC_RegisterCallback(&channel->session, gpu3d_session_callback, channel);
++
++ *Channel = (gctUINT32)channel;
++
++ return gcvSTATUS_OK;
++
++OnError:
++ if (channel)
++ {
++ if (channel->virtual)
++ {
++ }
++
++ if (channel->mutex)
++ {
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Os, channel->mutex));
++ }
++
++ gcmkVERIFY_OK(gckOS_Free(Os, channel));
++ }
++
++ return status;
++}
++
++gceSTATUS
++gckOS_CloseSecurityChannel(
++ IN gctUINT32 Channel
++ )
++{
++ /* TODO . */
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckOS_CallSecurityService(
++ IN gctUINT32 Channel,
++ IN gcsTA_INTERFACE *Interface
++ )
++{
++ gceSTATUS status;
++ TEEC_Result result;
++ gcsSecurityChannel *channel = (gcsSecurityChannel *)Channel;
++ TEEC_Operation operation = {0};
++
++ gcmkHEADER();
++ gcmkVERIFY_ARGUMENT(Channel != 0);
++
++ gckOS_AcquireMutex(channel->os, channel->mutex, gcvINFINITE);
++
++ gckOS_MemCopy(channel->virtual, Interface, channel->bytes);
++
++ operation.paramTypes = TEEC_PARAM_TYPES(
++ TEEC_MEMREF_PARTIAL_INPUT,
++ TEEC_NONE,
++ TEEC_NONE,
++ TEEC_NONE);
++
++ /* Note: we use the updated size in the MemRef output by the encryption. */
++ operation.params[0].memref.parent = &channel->inputBuffer;
++ operation.params[0].memref.offset = 0;
++ operation.params[0].memref.size = sizeof(gcsTA_INTERFACE);
++ operation.started = true;
++
++ /* Start the commit command within the TEE application. */
++ result = TEEC_InvokeCommand(
++ &channel->session,
++ gcvTA_COMMAND_DISPATCH,
++ &operation,
++ NULL);
++
++ gckOS_MemCopy(Interface, channel->virtual, channel->bytes);
++
++ gckOS_ReleaseMutex(channel->os, channel->mutex);
++
++ if (result != TEEC_SUCCESS)
++ {
++ gcmkONERROR(gcvSTATUS_GENERIC_IO);
++ }
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckOS_InitSecurityChannel(
++ IN gctUINT32 Channel
++ )
++{
++ gceSTATUS status;
++ TEEC_Result result;
++ gcsSecurityChannel *channel = (gcsSecurityChannel *)Channel;
++ TEEC_Operation operation = {0};
++
++ gcmkHEADER();
++ gcmkVERIFY_ARGUMENT(Channel != 0);
++
++ operation.paramTypes = TEEC_PARAM_TYPES(
++ TEEC_MEMREF_PARTIAL_INPUT,
++ TEEC_NONE,
++ TEEC_NONE,
++ TEEC_NONE);
++
++ /* Note: we use the updated size in the MemRef output by the encryption. */
++ operation.params[0].memref.parent = &channel->inputBuffer;
++ operation.params[0].memref.offset = 0;
++ operation.params[0].memref.size = gcmSIZEOF(gcsTA_INTERFACE);
++ operation.started = true;
++
++ /* Start the commit command within the TEE application. */
++ result = TEEC_InvokeCommand(
++ &channel->session,
++ gcvTA_COMMAND_INIT,
++ &operation,
++ NULL);
++
++ if (result != TEEC_SUCCESS)
++ {
++ gcmkONERROR(gcvSTATUS_GENERIC_IO);
++ }
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_sync.c linux-xbian-imx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_sync.c
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_sync.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_sync.c 2015-07-27 23:13:06.226765901 +0200
+@@ -0,0 +1,174 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include <linux/kernel.h>
++#include <linux/file.h>
++#include <linux/fs.h>
++#include <linux/miscdevice.h>
++#include <linux/module.h>
++#include <linux/syscalls.h>
++#include <linux/uaccess.h>
++
++#include "gc_hal_kernel_sync.h"
++
++#if gcdANDROID_NATIVE_FENCE_SYNC
++
++static struct sync_pt *
++viv_sync_pt_dup(
++ struct sync_pt * sync_pt
++ )
++{
++ gceSTATUS status;
++ struct viv_sync_pt *pt;
++ struct viv_sync_pt *src;
++ struct viv_sync_timeline *obj;
++
++ src = (struct viv_sync_pt *) sync_pt;
++ obj = (struct viv_sync_timeline *) sync_pt->parent;
++
++ /* Create the new sync_pt. */
++ pt = (struct viv_sync_pt *)
++ sync_pt_create(&obj->obj, sizeof(struct viv_sync_pt));
++
++ pt->stamp = src->stamp;
++ pt->sync = src->sync;
++
++ /* Reference sync point. */
++ status = gckOS_ReferenceSyncPoint(obj->os, pt->sync);
++
++ if (gcmIS_ERROR(status))
++ {
++ sync_pt_free((struct sync_pt *)pt);
++ return NULL;
++ }
++
++ return (struct sync_pt *)pt;
++}
++
++static int
++viv_sync_pt_has_signaled(
++ struct sync_pt * sync_pt
++ )
++{
++ gceSTATUS status;
++ gctBOOL state;
++ struct viv_sync_pt * pt;
++ struct viv_sync_timeline * obj;
++
++ pt = (struct viv_sync_pt *)sync_pt;
++ obj = (struct viv_sync_timeline *)sync_pt->parent;
++
++ status = gckOS_QuerySyncPoint(obj->os, pt->sync, &state);
++
++ if (gcmIS_ERROR(status))
++ {
++ /* Error. */
++ return -1;
++ }
++
++ return state;
++}
++
++static int
++viv_sync_pt_compare(
++ struct sync_pt * a,
++ struct sync_pt * b
++ )
++{
++ int ret;
++ struct viv_sync_pt * pt1 = (struct viv_sync_pt *) a;
++ struct viv_sync_pt * pt2 = (struct viv_sync_pt *) b;
++
++ ret = (pt1->stamp < pt2->stamp) ? -1
++ : (pt1->stamp == pt2->stamp) ? 0
++ : 1;
++
++ return ret;
++}
++
++static void
++viv_sync_pt_free(
++ struct sync_pt * sync_pt
++ )
++{
++ struct viv_sync_pt * pt;
++ struct viv_sync_timeline * obj;
++
++ pt = (struct viv_sync_pt *) sync_pt;
++ obj = (struct viv_sync_timeline *) sync_pt->parent;
++
++ gckOS_DestroySyncPoint(obj->os, pt->sync);
++}
++
++static struct sync_timeline_ops viv_timeline_ops =
++{
++ .driver_name = "viv_sync",
++ .dup = viv_sync_pt_dup,
++ .has_signaled = viv_sync_pt_has_signaled,
++ .compare = viv_sync_pt_compare,
++ .free_pt = viv_sync_pt_free,
++};
++
++struct viv_sync_timeline *
++viv_sync_timeline_create(
++ const char * name,
++ gckOS os
++ )
++{
++ struct viv_sync_timeline * obj;
++
++ obj = (struct viv_sync_timeline *)
++ sync_timeline_create(&viv_timeline_ops, sizeof(struct viv_sync_timeline), name);
++
++ obj->os = os;
++ obj->stamp = 0;
++
++ return obj;
++}
++
++struct sync_pt *
++viv_sync_pt_create(
++ struct viv_sync_timeline * obj,
++ gctSYNC_POINT SyncPoint
++ )
++{
++ gceSTATUS status;
++ struct viv_sync_pt * pt;
++
++ pt = (struct viv_sync_pt *)
++ sync_pt_create(&obj->obj, sizeof(struct viv_sync_pt));
++
++ pt->stamp = obj->stamp++;
++ pt->sync = SyncPoint;
++
++ /* Dup signal. */
++ status = gckOS_ReferenceSyncPoint(obj->os, SyncPoint);
++
++ if (gcmIS_ERROR(status))
++ {
++ sync_pt_free((struct sync_pt *)pt);
++ return NULL;
++ }
++
++ return (struct sync_pt *) pt;
++}
++
++#endif
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_sync.h linux-xbian-imx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_sync.h
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_sync.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_sync.h 2015-07-27 23:13:06.226765901 +0200
+@@ -0,0 +1,71 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_kernel_sync_h_
++#define __gc_hal_kernel_sync_h_
++
++#include <linux/types.h>
++
++#include <uapi/sync.h>
++
++#include <gc_hal.h>
++#include <gc_hal_base.h>
++
++struct viv_sync_timeline
++{
++ /* Parent object. */
++ struct sync_timeline obj;
++
++ /* Timestamp when sync_pt is created. */
++ gctUINT stamp;
++
++ /* Pointer to os struct. */
++ gckOS os;
++};
++
++
++struct viv_sync_pt
++{
++ /* Parent object. */
++ struct sync_pt pt;
++
++ /* Reference sync point*/
++ gctSYNC_POINT sync;
++
++ /* Timestamp when sync_pt is created. */
++ gctUINT stamp;
++};
++
++/* Create viv_sync_timeline object. */
++struct viv_sync_timeline *
++viv_sync_timeline_create(
++ const char * Name,
++ gckOS Os
++ );
++
++/* Create viv_sync_pt object. */
++struct sync_pt *
++viv_sync_pt_create(
++ struct viv_sync_timeline * Obj,
++ gctSYNC_POINT SyncPoint
++ );
++
++#endif /* __gc_hal_kernel_sync_h_ */
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/os/linux/kernel/platform/freescale/gc_hal_kernel_platform_imx6q14.c linux-xbian-imx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/platform/freescale/gc_hal_kernel_platform_imx6q14.c
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/os/linux/kernel/platform/freescale/gc_hal_kernel_platform_imx6q14.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/platform/freescale/gc_hal_kernel_platform_imx6q14.c 2015-07-27 23:13:06.226765901 +0200
+@@ -0,0 +1,880 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_linux.h"
++#include "gc_hal_kernel_platform.h"
++#include "gc_hal_kernel_device.h"
++#include "gc_hal_driver.h"
++#include <linux/slab.h>
++
++#if USE_PLATFORM_DRIVER
++# include <linux/platform_device.h>
++#endif
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,5,0)
++#include <mach/viv_gpu.h>
++#else
++#include <linux/pm_runtime.h>
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 10, 0)
++#include <mach/busfreq.h>
++#else
++#include <linux/busfreq-imx6.h>
++#include <linux/reset.h>
++#endif
++#endif
++
++#include <linux/clk.h>
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,10,0)
++#include <mach/hardware.h>
++#endif
++#include <linux/pm_runtime.h>
++
++#include <linux/regulator/consumer.h>
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
++#include <linux/device_cooling.h>
++#define REG_THERMAL_NOTIFIER(a) register_devfreq_cooling_notifier(a);
++#define UNREG_THERMAL_NOTIFIER(a) unregister_devfreq_cooling_notifier(a);
++#else
++extern int register_thermal_notifier(struct notifier_block *nb);
++extern int unregister_thermal_notifier(struct notifier_block *nb);
++#define REG_THERMAL_NOTIFIER(a) register_thermal_notifier(a);
++#define UNREG_THERMAL_NOTIFIER(a) unregister_thermal_notifier(a);
++#endif
++
++static int initgpu3DMinClock = 1;
++module_param(initgpu3DMinClock, int, 0644);
++
++struct platform_device *pdevice;
++
++#ifdef CONFIG_GPU_LOW_MEMORY_KILLER
++# include <linux/kernel.h>
++# include <linux/mm.h>
++# include <linux/oom.h>
++# include <linux/sched.h>
++
++struct task_struct *lowmem_deathpending;
++
++static int
++task_notify_func(struct notifier_block *self, unsigned long val, void *data);
++
++static struct notifier_block task_nb = {
++ .notifier_call = task_notify_func,
++};
++
++static int
++task_notify_func(struct notifier_block *self, unsigned long val, void *data)
++{
++ struct task_struct *task = data;
++
++ if (task == lowmem_deathpending)
++ lowmem_deathpending = NULL;
++
++ return NOTIFY_OK;
++}
++
++extern struct task_struct *lowmem_deathpending;
++static unsigned long lowmem_deathpending_timeout;
++
++static int force_contiguous_lowmem_shrink(IN gckKERNEL Kernel)
++{
++ struct task_struct *p;
++ struct task_struct *selected = NULL;
++ int tasksize;
++ int ret = -1;
++ int min_adj = 0;
++ int selected_tasksize = 0;
++ int selected_oom_adj;
++ /*
++ * If we already have a death outstanding, then
++ * bail out right away; indicating to vmscan
++ * that we have nothing further to offer on
++ * this pass.
++ *
++ */
++ if (lowmem_deathpending &&
++ time_before_eq(jiffies, lowmem_deathpending_timeout))
++ return 0;
++ selected_oom_adj = min_adj;
++
++ rcu_read_lock();
++ for_each_process(p) {
++ struct mm_struct *mm;
++ struct signal_struct *sig;
++ gcuDATABASE_INFO info;
++ int oom_adj;
++
++ task_lock(p);
++ mm = p->mm;
++ sig = p->signal;
++ if (!mm || !sig) {
++ task_unlock(p);
++ continue;
++ }
++ oom_adj = sig->oom_score_adj;
++ if (oom_adj < min_adj) {
++ task_unlock(p);
++ continue;
++ }
++
++ tasksize = 0;
++ task_unlock(p);
++ rcu_read_unlock();
++
++ if (gckKERNEL_QueryProcessDB(Kernel, p->pid, gcvFALSE, gcvDB_VIDEO_MEMORY, &info) == gcvSTATUS_OK){
++ tasksize += info.counters.bytes / PAGE_SIZE;
++ }
++ if (gckKERNEL_QueryProcessDB(Kernel, p->pid, gcvFALSE, gcvDB_CONTIGUOUS, &info) == gcvSTATUS_OK){
++ tasksize += info.counters.bytes / PAGE_SIZE;
++ }
++
++ rcu_read_lock();
++
++ if (tasksize <= 0)
++ continue;
++
++ gckOS_Print("<gpu> pid %d (%s), adj %d, size %d \n", p->pid, p->comm, oom_adj, tasksize);
++
++ if (selected) {
++ if (oom_adj < selected_oom_adj)
++ continue;
++ if (oom_adj == selected_oom_adj &&
++ tasksize <= selected_tasksize)
++ continue;
++ }
++ selected = p;
++ selected_tasksize = tasksize;
++ selected_oom_adj = oom_adj;
++ }
++ if (selected) {
++ gckOS_Print("<gpu> send sigkill to %d (%s), adj %d, size %d\n",
++ selected->pid, selected->comm,
++ selected_oom_adj, selected_tasksize);
++ lowmem_deathpending = selected;
++ lowmem_deathpending_timeout = jiffies + HZ;
++ force_sig(SIGKILL, selected);
++ ret = 0;
++ }
++ rcu_read_unlock();
++ return ret;
++}
++
++
++gceSTATUS
++_ShrinkMemory(
++ IN gckPLATFORM Platform
++ )
++{
++ struct platform_device *pdev;
++ gckGALDEVICE galDevice;
++ gckKERNEL kernel;
++
++ pdev = Platform->device;
++
++ galDevice = platform_get_drvdata(pdev);
++
++ kernel = galDevice->kernels[gcvCORE_MAJOR];
++
++ if (kernel != gcvNULL)
++ {
++ force_contiguous_lowmem_shrink(kernel);
++ }
++ else
++ {
++ gcmkPRINT("%s(%d) can't find kernel! ", __FUNCTION__, __LINE__);
++ }
++
++ return gcvSTATUS_OK;
++}
++#endif
++
++#if gcdENABLE_FSCALE_VAL_ADJUST
++static int thermal_hot_pm_notify(struct notifier_block *nb, unsigned long event,
++ void *dummy)
++{
++ static gctUINT orgFscale, minFscale, maxFscale;
++ static gctBOOL bAlreadyTooHot = gcvFALSE;
++ gckHARDWARE hardware;
++ gckGALDEVICE galDevice;
++
++ galDevice = platform_get_drvdata(pdevice);
++ if (!galDevice)
++ {
++ /* GPU is not ready, so it is meaningless to change GPU freq. */
++ return NOTIFY_OK;
++ }
++
++ if (!galDevice->kernels[gcvCORE_MAJOR])
++ {
++ return NOTIFY_OK;
++ }
++
++ hardware = galDevice->kernels[gcvCORE_MAJOR]->hardware;
++
++ if (!hardware)
++ {
++ return NOTIFY_OK;
++ }
++
++ if (event && !bAlreadyTooHot) {
++ gckHARDWARE_GetFscaleValue(hardware,&orgFscale,&minFscale, &maxFscale);
++ gckHARDWARE_SetFscaleValue(hardware, minFscale);
++ bAlreadyTooHot = gcvTRUE;
++ gckOS_Print("System is too hot. GPU3D will work at %d/64 clock.\n", minFscale);
++ } else if (!event && bAlreadyTooHot) {
++ gckHARDWARE_SetFscaleValue(hardware, orgFscale);
++ gckOS_Print("Hot alarm is canceled. GPU3D clock will return to %d/64\n", orgFscale);
++ bAlreadyTooHot = gcvFALSE;
++ }
++ return NOTIFY_OK;
++}
++
++static struct notifier_block thermal_hot_pm_notifier = {
++ .notifier_call = thermal_hot_pm_notify,
++ };
++
++static ssize_t show_gpu3DMinClock(struct device_driver *dev, char *buf)
++{
++ gctUINT currentf,minf,maxf;
++ gckGALDEVICE galDevice;
++
++ galDevice = platform_get_drvdata(pdevice);
++ if(galDevice->kernels[gcvCORE_MAJOR])
++ {
++ gckHARDWARE_GetFscaleValue(galDevice->kernels[gcvCORE_MAJOR]->hardware,
++ &currentf, &minf, &maxf);
++ }
++ snprintf(buf, PAGE_SIZE, "%d\n", minf);
++ return strlen(buf);
++}
++
++static ssize_t update_gpu3DMinClock(struct device_driver *dev, const char *buf, size_t count)
++{
++
++ gctINT fields;
++ gctUINT MinFscaleValue;
++ gckGALDEVICE galDevice;
++
++ galDevice = platform_get_drvdata(pdevice);
++ if(galDevice->kernels[gcvCORE_MAJOR])
++ {
++ fields = sscanf(buf, "%d", &MinFscaleValue);
++ if (fields < 1)
++ return -EINVAL;
++
++ gckHARDWARE_SetMinFscaleValue(galDevice->kernels[gcvCORE_MAJOR]->hardware,MinFscaleValue);
++ }
++
++ return count;
++}
++
++static DRIVER_ATTR(gpu3DMinClock, S_IRUGO | S_IWUSR, show_gpu3DMinClock, update_gpu3DMinClock);
++#endif
++
++
++
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,5,0)
++static const struct of_device_id mxs_gpu_dt_ids[] = {
++ { .compatible = "fsl,imx6q-gpu", },
++ {/* sentinel */}
++};
++MODULE_DEVICE_TABLE(of, mxs_gpu_dt_ids);
++#endif
++
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
++struct contiguous_mem_pool {
++ struct dma_attrs attrs;
++ dma_addr_t phys;
++ void *virt;
++ size_t size;
++};
++#endif
++
++struct imx_priv {
++ /* Clock management.*/
++ struct clk *clk_3d_core;
++ struct clk *clk_3d_shader;
++ struct clk *clk_3d_axi;
++ struct clk *clk_2d_core;
++ struct clk *clk_2d_axi;
++ struct clk *clk_vg_axi;
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,14,0)
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,5,0) || LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
++ /*Power management.*/
++ struct regulator *gpu_regulator;
++#endif
++#endif
++ /*Run time pm*/
++ struct device *pmdev;
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
++ struct contiguous_mem_pool *pool;
++ struct reset_control *rstc[gcdMAX_GPU_COUNT];
++#endif
++};
++
++static struct imx_priv imxPriv;
++
++gceSTATUS
++gckPLATFORM_AdjustParam(
++ IN gckPLATFORM Platform,
++ OUT gcsMODULE_PARAMETERS *Args
++ )
++{
++ struct resource* res;
++ struct platform_device* pdev = Platform->device;
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
++#elif LINUX_VERSION_CODE >= KERNEL_VERSION(3,5,0)
++ struct device_node *dn =pdev->dev.of_node;
++ const u32 *prop;
++#else
++ struct viv_gpu_platform_data *pdata;
++#endif
++
++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phys_baseaddr");
++ if (res)
++ Args->baseAddress = res->start;
++
++ res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "irq_3d");
++ if (res)
++ Args->irqLine = res->start;
++
++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "iobase_3d");
++ if (res)
++ {
++ Args->registerMemBase = res->start;
++ Args->registerMemSize = res->end - res->start + 1;
++ }
++
++ res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "irq_2d");
++ if (res)
++ Args->irqLine2D = res->start;
++
++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "iobase_2d");
++ if (res)
++ {
++ Args->registerMemBase2D = res->start;
++ Args->registerMemSize2D = res->end - res->start + 1;
++ }
++
++ res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "irq_vg");
++ if (res)
++ Args->irqLineVG = res->start;
++
++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "iobase_vg");
++ if (res)
++ {
++ Args->registerMemBaseVG = res->start;
++ Args->registerMemSizeVG = res->end - res->start + 1;
++ }
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
++ Args->contiguousBase = 0;
++#elif LINUX_VERSION_CODE >= KERNEL_VERSION(3,5,0)
++ prop = of_get_property(dn, "contiguousbase", NULL);
++ if(prop)
++ Args->contiguousBase = *prop;
++ of_property_read_u32(dn,"contiguoussize", (u32 *)&contiguousSize);
++#else
++ pdata = pdev->dev.platform_data;
++ if (pdata) {
++ Args->contiguousBase = pdata->reserved_mem_base;
++ Args->contiguousSize = pdata->reserved_mem_size;
++ }
++#endif
++ if (Args->contiguousSize == 0)
++ gckOS_Print("Warning: No contiguous memory is reserverd for gpu.!\n ");
++
++ Args->gpu3DMinClock = initgpu3DMinClock;
++
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++_AllocPriv(
++ IN gckPLATFORM Platform
++ )
++{
++ Platform->priv = &imxPriv;
++
++#ifdef CONFIG_GPU_LOW_MEMORY_KILLER
++ task_free_register(&task_nb);
++#endif
++
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++_FreePriv(
++ IN gckPLATFORM Platform
++ )
++{
++#ifdef CONFIG_GPU_LOW_MEMORY_KILLER
++ task_free_unregister(&task_nb);
++#endif
++
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++_GetPower(
++ IN gckPLATFORM Platform
++ )
++{
++ struct device* pdev = &Platform->device->dev;
++ struct imx_priv *priv = Platform->priv;
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
++ struct reset_control *rstc;
++#endif
++
++#ifdef CONFIG_PM
++ /*Init runtime pm for gpu*/
++ pm_runtime_enable(pdev);
++ priv->pmdev = pdev;
++#endif
++
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
++ rstc = devm_reset_control_get(pdev, "gpu3d");
++ priv->rstc[gcvCORE_MAJOR] = IS_ERR(rstc) ? NULL : rstc;
++ rstc = devm_reset_control_get(pdev, "gpu2d");
++ priv->rstc[gcvCORE_2D] = IS_ERR(rstc) ? NULL : rstc;
++ rstc = devm_reset_control_get(pdev, "gpuvg");
++ priv->rstc[gcvCORE_VG] = IS_ERR(rstc) ? NULL : rstc;
++#endif
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,14,0)
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,5,0)
++ /*get gpu regulator*/
++ priv->gpu_regulator = regulator_get(pdev, "cpu_vddgpu");
++#elif LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
++ priv->gpu_regulator = devm_regulator_get(pdev, "pu");
++#endif
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,5,0) || LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
++ if (IS_ERR(priv->gpu_regulator)) {
++ gcmkTRACE_ZONE(gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Failed to get gpu regulator \n",
++ __FUNCTION__, __LINE__);
++ return gcvSTATUS_NOT_FOUND;
++ }
++#endif
++#endif
++
++ /*Initialize the clock structure*/
++ priv->clk_3d_core = clk_get(pdev, "gpu3d_clk");
++ if (!IS_ERR(priv->clk_3d_core)) {
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,5,0)
++ if (cpu_is_mx6q()) {
++ priv->clk_3d_shader = clk_get(pdev, "gpu3d_shader_clk");
++ if (IS_ERR(priv->clk_3d_shader)) {
++ clk_put(priv->clk_3d_core);
++ priv->clk_3d_core = NULL;
++ priv->clk_3d_shader = NULL;
++ gckOS_Print("galcore: clk_get gpu3d_shader_clk failed, disable 3d!\n");
++ }
++ }
++#else
++ priv->clk_3d_axi = clk_get(pdev, "gpu3d_axi_clk");
++ priv->clk_3d_shader = clk_get(pdev, "gpu3d_shader_clk");
++ if (IS_ERR(priv->clk_3d_shader)) {
++ clk_put(priv->clk_3d_core);
++ priv->clk_3d_core = NULL;
++ priv->clk_3d_shader = NULL;
++ gckOS_Print("galcore: clk_get gpu3d_shader_clk failed, disable 3d!\n");
++ }
++#endif
++ } else {
++ priv->clk_3d_core = NULL;
++ gckOS_Print("galcore: clk_get gpu3d_clk failed, disable 3d!\n");
++ }
++
++ priv->clk_2d_core = clk_get(pdev, "gpu2d_clk");
++ if (IS_ERR(priv->clk_2d_core)) {
++ priv->clk_2d_core = NULL;
++ gckOS_Print("galcore: clk_get 2d core clock failed, disable 2d/vg!\n");
++ } else {
++ priv->clk_2d_axi = clk_get(pdev, "gpu2d_axi_clk");
++ if (IS_ERR(priv->clk_2d_axi)) {
++ priv->clk_2d_axi = NULL;
++ gckOS_Print("galcore: clk_get 2d axi clock failed, disable 2d\n");
++ }
++
++ priv->clk_vg_axi = clk_get(pdev, "openvg_axi_clk");
++ if (IS_ERR(priv->clk_vg_axi)) {
++ priv->clk_vg_axi = NULL;
++ gckOS_Print("galcore: clk_get vg clock failed, disable vg!\n");
++ }
++ }
++
++
++#if gcdENABLE_FSCALE_VAL_ADJUST
++ pdevice = Platform->device;
++ REG_THERMAL_NOTIFIER(&thermal_hot_pm_notifier);
++ {
++ int ret = 0;
++ ret = driver_create_file(pdevice->dev.driver, &driver_attr_gpu3DMinClock);
++ if(ret)
++ dev_err(&pdevice->dev, "create gpu3DMinClock attr failed (%d)\n", ret);
++ }
++#endif
++
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++_PutPower(
++ IN gckPLATFORM Platform
++ )
++{
++ struct imx_priv *priv = Platform->priv;
++
++ /*Disable clock*/
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,5,0)
++ if (priv->clk_3d_axi) {
++ clk_put(priv->clk_3d_axi);
++ priv->clk_3d_axi = NULL;
++ }
++#endif
++ if (priv->clk_3d_core) {
++ clk_put(priv->clk_3d_core);
++ priv->clk_3d_core = NULL;
++ }
++ if (priv->clk_3d_shader) {
++ clk_put(priv->clk_3d_shader);
++ priv->clk_3d_shader = NULL;
++ }
++ if (priv->clk_2d_core) {
++ clk_put(priv->clk_2d_core);
++ priv->clk_2d_core = NULL;
++ }
++ if (priv->clk_2d_axi) {
++ clk_put(priv->clk_2d_axi);
++ priv->clk_2d_axi = NULL;
++ }
++ if (priv->clk_vg_axi) {
++ clk_put(priv->clk_vg_axi);
++ priv->clk_vg_axi = NULL;
++ }
++
++#ifdef CONFIG_PM
++ if(priv->pmdev)
++ pm_runtime_disable(priv->pmdev);
++#endif
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,5,0)
++ if (priv->gpu_regulator) {
++ regulator_put(priv->gpu_regulator);
++ priv->gpu_regulator = NULL;
++ }
++#endif
++
++#if gcdENABLE_FSCALE_VAL_ADJUST
++ UNREG_THERMAL_NOTIFIER(&thermal_hot_pm_notifier);
++
++ driver_remove_file(pdevice->dev.driver, &driver_attr_gpu3DMinClock);
++#endif
++
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++_SetPower(
++ IN gckPLATFORM Platform,
++ IN gceCORE GPU,
++ IN gctBOOL Enable
++ )
++{
++ struct imx_priv* priv = Platform->priv;
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,14,0)
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,5,0) || LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
++ int ret;
++#endif
++#endif
++
++ if (Enable)
++ {
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,14,0)
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,5,0) || LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
++ if(!IS_ERR(priv->gpu_regulator)) {
++ ret = regulator_enable(priv->gpu_regulator);
++ if (ret != 0)
++ gckOS_Print("%s(%d): fail to enable pu regulator %d!\n",
++ __FUNCTION__, __LINE__, ret);
++ }
++#else
++ imx_gpc_power_up_pu(true);
++#endif
++#endif
++
++#ifdef CONFIG_PM
++ pm_runtime_get_sync(priv->pmdev);
++#endif
++ }
++ else
++ {
++#ifdef CONFIG_PM
++ pm_runtime_put_sync(priv->pmdev);
++#endif
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,14,0)
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,5,0) || LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
++ if(!IS_ERR(priv->gpu_regulator))
++ regulator_disable(priv->gpu_regulator);
++#else
++ imx_gpc_power_up_pu(false);
++#endif
++#endif
++
++ }
++
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++_SetClock(
++ IN gckPLATFORM Platform,
++ IN gceCORE GPU,
++ IN gctBOOL Enable
++ )
++{
++ struct imx_priv* priv = Platform->priv;
++ struct clk *clk_3dcore = priv->clk_3d_core;
++ struct clk *clk_3dshader = priv->clk_3d_shader;
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,5,0)
++ struct clk *clk_3d_axi = priv->clk_3d_axi;
++#endif
++ struct clk *clk_2dcore = priv->clk_2d_core;
++ struct clk *clk_2d_axi = priv->clk_2d_axi;
++ struct clk *clk_vg_axi = priv->clk_vg_axi;
++
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,5,0)
++ if (Enable) {
++ switch (GPU) {
++ case gcvCORE_MAJOR:
++ clk_enable(clk_3dcore);
++ if (cpu_is_mx6q())
++ clk_enable(clk_3dshader);
++ break;
++ case gcvCORE_2D:
++ clk_enable(clk_2dcore);
++ clk_enable(clk_2d_axi);
++ break;
++ case gcvCORE_VG:
++ clk_enable(clk_2dcore);
++ clk_enable(clk_vg_axi);
++ break;
++ default:
++ break;
++ }
++ } else {
++ switch (GPU) {
++ case gcvCORE_MAJOR:
++ if (cpu_is_mx6q())
++ clk_disable(clk_3dshader);
++ clk_disable(clk_3dcore);
++ break;
++ case gcvCORE_2D:
++ clk_disable(clk_2dcore);
++ clk_disable(clk_2d_axi);
++ break;
++ case gcvCORE_VG:
++ clk_disable(clk_2dcore);
++ clk_disable(clk_vg_axi);
++ break;
++ default:
++ break;
++ }
++ }
++#else
++ if (Enable) {
++ switch (GPU) {
++ case gcvCORE_MAJOR:
++ clk_prepare(clk_3dcore);
++ clk_enable(clk_3dcore);
++ clk_prepare(clk_3dshader);
++ clk_enable(clk_3dshader);
++ clk_prepare(clk_3d_axi);
++ clk_enable(clk_3d_axi);
++ break;
++ case gcvCORE_2D:
++ clk_prepare(clk_2dcore);
++ clk_enable(clk_2dcore);
++ clk_prepare(clk_2d_axi);
++ clk_enable(clk_2d_axi);
++ break;
++ case gcvCORE_VG:
++ clk_prepare(clk_2dcore);
++ clk_enable(clk_2dcore);
++ clk_prepare(clk_vg_axi);
++ clk_enable(clk_vg_axi);
++ break;
++ default:
++ break;
++ }
++ } else {
++ switch (GPU) {
++ case gcvCORE_MAJOR:
++ clk_disable(clk_3dshader);
++ clk_unprepare(clk_3dshader);
++ clk_disable(clk_3dcore);
++ clk_unprepare(clk_3dcore);
++ clk_disable(clk_3d_axi);
++ clk_unprepare(clk_3d_axi);
++ break;
++ case gcvCORE_2D:
++ clk_disable(clk_2dcore);
++ clk_unprepare(clk_2dcore);
++ clk_disable(clk_2d_axi);
++ clk_unprepare(clk_2d_axi);
++ break;
++ case gcvCORE_VG:
++ clk_disable(clk_2dcore);
++ clk_unprepare(clk_2dcore);
++ clk_disable(clk_vg_axi);
++ clk_unprepare(clk_vg_axi);
++ break;
++ default:
++ break;
++ }
++ }
++#endif
++
++ return gcvSTATUS_OK;
++}
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,5,0)
++#ifdef CONFIG_PM
++static int gpu_runtime_suspend(struct device *dev)
++{
++ release_bus_freq(BUS_FREQ_HIGH);
++ return 0;
++}
++
++static int gpu_runtime_resume(struct device *dev)
++{
++ request_bus_freq(BUS_FREQ_HIGH);
++ return 0;
++}
++
++static struct dev_pm_ops gpu_pm_ops;
++#endif
++#endif
++
++gceSTATUS
++_AdjustDriver(
++ IN gckPLATFORM Platform
++ )
++{
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,5,0)
++ struct platform_driver * driver = Platform->driver;
++#endif
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,5,0)
++ driver->driver.of_match_table = mxs_gpu_dt_ids;
++#endif
++
++ /* Override PM callbacks to add runtime PM callbacks. */
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,5,0)
++ /* Fill local structure with original value. */
++ memcpy(&gpu_pm_ops, driver->driver.pm, sizeof(struct dev_pm_ops));
++
++ /* Add runtime PM callback. */
++#ifdef CONFIG_PM
++ gpu_pm_ops.runtime_suspend = gpu_runtime_suspend;
++ gpu_pm_ops.runtime_resume = gpu_runtime_resume;
++ gpu_pm_ops.runtime_idle = NULL;
++#endif
++
++ /* Replace callbacks. */
++ driver->driver.pm = &gpu_pm_ops;
++#endif
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++_Reset(
++ IN gckPLATFORM Platform,
++ gceCORE GPU
++ )
++{
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,5,0)
++#define SRC_SCR_OFFSET 0
++#define BP_SRC_SCR_GPU3D_RST 1
++#define BP_SRC_SCR_GPU2D_RST 4
++ void __iomem *src_base = IO_ADDRESS(SRC_BASE_ADDR);
++ gctUINT32 bit_offset,val;
++
++ if(GPU == gcvCORE_MAJOR) {
++ bit_offset = BP_SRC_SCR_GPU3D_RST;
++ } else if((GPU == gcvCORE_VG)
++ ||(GPU == gcvCORE_2D)) {
++ bit_offset = BP_SRC_SCR_GPU2D_RST;
++ } else {
++ return gcvSTATUS_INVALID_CONFIG;
++ }
++ val = __raw_readl(src_base + SRC_SCR_OFFSET);
++ val &= ~(1 << (bit_offset));
++ val |= (1 << (bit_offset));
++ __raw_writel(val, src_base + SRC_SCR_OFFSET);
++
++ while ((__raw_readl(src_base + SRC_SCR_OFFSET) &
++ (1 << (bit_offset))) != 0) {
++ }
++
++ return gcvSTATUS_NOT_SUPPORTED;
++#elif LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
++ struct imx_priv* priv = Platform->priv;
++ struct reset_control *rstc = priv->rstc[GPU];
++ if (rstc)
++ reset_control_reset(rstc);
++#else
++ imx_src_reset_gpu((int)GPU);
++#endif
++ return gcvSTATUS_OK;
++}
++
++gcsPLATFORM_OPERATIONS platformOperations = {
++ .adjustParam = gckPLATFORM_AdjustParam,
++ .allocPriv = _AllocPriv,
++ .freePriv = _FreePriv,
++ .getPower = _GetPower,
++ .putPower = _PutPower,
++ .setPower = _SetPower,
++ .setClock = _SetClock,
++ .adjustDriver = _AdjustDriver,
++ .reset = _Reset,
++#ifdef CONFIG_GPU_LOW_MEMORY_KILLER
++ .shrinkMemory = _ShrinkMemory,
++#endif
++};
++
++void
++gckPLATFORM_QueryOperations(
++ IN gcsPLATFORM_OPERATIONS ** Operations
++ )
++{
++ *Operations = &platformOperations;
++}
++
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/hal/os/linux/kernel/platform/freescale/gc_hal_kernel_platform_imx6q14.config linux-xbian-imx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/platform/freescale/gc_hal_kernel_platform_imx6q14.config
+--- linux-4.1.3/drivers/mxc/gpu-viv/hal/os/linux/kernel/platform/freescale/gc_hal_kernel_platform_imx6q14.config 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/platform/freescale/gc_hal_kernel_platform_imx6q14.config 2015-07-27 23:13:06.226765901 +0200
+@@ -0,0 +1,15 @@
++EXTRA_CFLAGS += -DgcdDEFAULT_CONTIGUOUS_SIZE=134217728
++
++ifneq ($(CONFIG_ANDROID),)
++# build for android
++EXTRA_CFLAGS += -DgcdANDROID_NATIVE_FENCE_SYNC=3
++
++ifeq ($(CONFIG_SYNC),)
++$(warn CONFIG_SYNC is not set in kernel config)
++$(warn Android native fence sync needs CONFIG_SYNC)
++endif
++endif
++
++EXTRA_CFLAGS += -DLINUX_CMA_FSL=1
++ALLOCATOR_ARRAY_H_LOCATION := $(OS_KERNEL_DIR)/allocator/freescale
++CUSTOMER_ALLOCATOR_OBJS := $(ALLOCATOR_ARRAY_H_LOCATION)/gc_hal_kernel_allocator_cma.o
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/Kbuild linux-xbian-imx6/drivers/mxc/gpu-viv/Kbuild
+--- linux-4.1.3/drivers/mxc/gpu-viv/Kbuild 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/Kbuild 2015-07-27 23:13:06.166979215 +0200
+@@ -0,0 +1,236 @@
++##############################################################################
++#
++# Copyright (C) 2005 - 2013 by Vivante Corp.
++#
++# This program is free software; you can redistribute it and/or modify
++# it under the terms of the GNU General Public License as published by
++# the Free Software Foundation; either version 2 of the license, or
++# (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not write to the Free Software
++# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++#
++##############################################################################
++
++
++#
++# Linux build file for kernel HAL driver.
++#
++
++AQROOT := $(srctree)/drivers/mxc/gpu-viv
++AQARCH := $(AQROOT)/arch/XAQ2
++AQVGARCH := $(AQROOT)/arch/GC350
++
++include $(AQROOT)/config
++
++KERNEL_DIR ?= $(TOOL_DIR)/kernel
++
++OS_KERNEL_DIR := hal/os/linux/kernel
++ARCH_KERNEL_DIR := arch/$(notdir $(AQARCH))/hal/kernel
++ARCH_VG_KERNEL_DIR := arch/$(notdir $(AQVGARCH))/hal/kernel
++HAL_KERNEL_DIR := hal/kernel
++
++# EXTRA_CFLAGS += -Werror
++
++OBJS := $(OS_KERNEL_DIR)/gc_hal_kernel_device.o \
++ $(OS_KERNEL_DIR)/gc_hal_kernel_driver.o \
++ $(OS_KERNEL_DIR)/gc_hal_kernel_linux.o \
++ $(OS_KERNEL_DIR)/gc_hal_kernel_math.o \
++ $(OS_KERNEL_DIR)/gc_hal_kernel_os.o \
++ $(OS_KERNEL_DIR)/gc_hal_kernel_debugfs.o
++
++OBJS += $(HAL_KERNEL_DIR)/gc_hal_kernel.o \
++ $(HAL_KERNEL_DIR)/gc_hal_kernel_command.o \
++ $(HAL_KERNEL_DIR)/gc_hal_kernel_db.o \
++ $(HAL_KERNEL_DIR)/gc_hal_kernel_debug.o \
++ $(HAL_KERNEL_DIR)/gc_hal_kernel_event.o \
++ $(HAL_KERNEL_DIR)/gc_hal_kernel_heap.o \
++ $(HAL_KERNEL_DIR)/gc_hal_kernel_mmu.o \
++ $(HAL_KERNEL_DIR)/gc_hal_kernel_video_memory.o \
++ $(HAL_KERNEL_DIR)/gc_hal_kernel_power.o
++
++OBJS += $(ARCH_KERNEL_DIR)/gc_hal_kernel_context.o \
++ $(ARCH_KERNEL_DIR)/gc_hal_kernel_hardware.o
++
++ifeq ($(VIVANTE_ENABLE_VG), 1)
++OBJS +=\
++ $(HAL_KERNEL_DIR)/gc_hal_kernel_vg.o\
++ $(HAL_KERNEL_DIR)/gc_hal_kernel_command_vg.o\
++ $(HAL_KERNEL_DIR)/gc_hal_kernel_interrupt_vg.o\
++ $(HAL_KERNEL_DIR)/gc_hal_kernel_mmu_vg.o\
++ $(ARCH_VG_KERNEL_DIR)/gc_hal_kernel_hardware_command_vg.o\
++ $(ARCH_VG_KERNEL_DIR)/gc_hal_kernel_hardware_vg.o
++endif
++
++ifneq ($(CONFIG_SYNC),)
++OBJS += $(OS_KERNEL_DIR)/gc_hal_kernel_sync.o
++endif
++
++ifeq ($(KERNELRELEASE), )
++
++.PHONY: all clean install
++
++# Define targets.
++all:
++ @make V=$(V) ARCH=$(ARCH_TYPE) -C $(KERNEL_DIR) SUBDIRS=`pwd` modules
++
++clean:
++ @rm -rf $(OBJS)
++ @rm -rf modules.order Module.symvers
++ @find $(AQROOT) -name ".gc_*.cmd" | xargs rm -f
++
++install: all
++ @mkdir -p $(SDK_DIR)/drivers
++
++else
++
++
++EXTRA_CFLAGS += -DLINUX -DDRIVER
++
++ifeq ($(ENUM_WORKAROUND), 1)
++EXTRA_CFLAGS += -DENUM_WORKAROUND=1
++else
++EXTRA_CFLAGS += -DENUM_WORKAROUND=0
++endif
++
++ifeq ($(FLAREON),1)
++EXTRA_CFLAGS += -DFLAREON
++endif
++
++ifeq ($(DEBUG), 1)
++EXTRA_CFLAGS += -DDBG=1 -DDEBUG -D_DEBUG
++else
++EXTRA_CFLAGS += -DDBG=0
++endif
++
++ifeq ($(NO_DMA_COHERENT), 1)
++EXTRA_CFLAGS += -DNO_DMA_COHERENT
++endif
++
++ifeq ($(CONFIG_DOVE_GPU), 1)
++EXTRA_CFLAGS += -DCONFIG_DOVE_GPU=1
++endif
++
++ifneq ($(USE_PLATFORM_DRIVER), 0)
++EXTRA_CFLAGS += -DUSE_PLATFORM_DRIVER=1
++else
++EXTRA_CFLAGS += -DUSE_PLATFORM_DRIVER=0
++endif
++
++
++EXTRA_CFLAGS += -DVIVANTE_PROFILER=1
++EXTRA_CFLAGS += -DVIVANTE_PROFILER_CONTEXT=1
++
++
++ifeq ($(ANDROID), 1)
++EXTRA_CFLAGS += -DANDROID=1
++endif
++
++ifeq ($(ENABLE_GPU_CLOCK_BY_DRIVER), 1)
++EXTRA_CFLAGS += -DENABLE_GPU_CLOCK_BY_DRIVER=1
++else
++EXTRA_CFLAGS += -DENABLE_GPU_CLOCK_BY_DRIVER=0
++endif
++
++ifeq ($(USE_NEW_LINUX_SIGNAL), 1)
++EXTRA_CFLAGS += -DUSE_NEW_LINUX_SIGNAL=1
++else
++EXTRA_CFLAGS += -DUSE_NEW_LINUX_SIGNAL=0
++endif
++
++ifeq ($(NO_USER_DIRECT_ACCESS_FROM_KERNEL), 1)
++EXTRA_CFLAGS += -DNO_USER_DIRECT_ACCESS_FROM_KERNEL=1
++else
++EXTRA_CFLAGS += -DNO_USER_DIRECT_ACCESS_FROM_KERNEL=0
++endif
++
++ifeq ($(FORCE_ALL_VIDEO_MEMORY_CACHED), 1)
++EXTRA_CFLAGS += -DgcdPAGED_MEMORY_CACHEABLE=1
++else
++EXTRA_CFLAGS += -DgcdPAGED_MEMORY_CACHEABLE=0
++endif
++
++ifeq ($(NONPAGED_MEMORY_CACHEABLE), 1)
++EXTRA_CFLAGS += -DgcdNONPAGED_MEMORY_CACHEABLE=1
++else
++EXTRA_CFLAGS += -DgcdNONPAGED_MEMORY_CACHEABLE=0
++endif
++
++ifeq ($(NONPAGED_MEMORY_BUFFERABLE), 1)
++EXTRA_CFLAGS += -DgcdNONPAGED_MEMORY_BUFFERABLE=1
++else
++EXTRA_CFLAGS += -DgcdNONPAGED_MEMORY_BUFFERABLE=0
++endif
++
++ifeq ($(CACHE_FUNCTION_UNIMPLEMENTED), 1)
++EXTRA_CFLAGS += -DgcdCACHE_FUNCTION_UNIMPLEMENTED=1
++else
++EXTRA_CFLAGS += -DgcdCACHE_FUNCTION_UNIMPLEMENTED=0
++endif
++
++ifeq ($(SUPPORT_SWAP_RECTANGLE), 1)
++EXTRA_CFLAGS += -DgcdSUPPORT_SWAP_RECTANGLE=1
++else
++EXTRA_CFLAGS += -DgcdSUPPORT_SWAP_RECTANGLE=0
++endif
++
++ifeq ($(VIVANTE_ENABLE_VG), 1)
++EXTRA_CFLAGS += -DgcdENABLE_VG=1
++else
++EXTRA_CFLAGS += -DgcdENABLE_VG=0
++endif
++
++ifeq ($(CONFIG_SMP), y)
++EXTRA_CFLAGS += -DgcdSMP=1
++else
++EXTRA_CFLAGS += -DgcdSMP=0
++endif
++
++ifeq ($(VIVANTE_NO_3D),1)
++EXTRA_CFLAGS += -DVIVANTE_NO_3D
++endif
++
++ifeq ($(ENABLE_OUTER_CACHE_PATCH), 1)
++EXTRA_CFLAGS += -DgcdENABLE_OUTER_CACHE_PATCH=1
++else
++EXTRA_CFLAGS += -DgcdENABLE_OUTER_CACHE_PATCH=0
++endif
++
++ifeq ($(USE_BANK_ALIGNMENT), 1)
++ EXTRA_CFLAGS += -DgcdENABLE_BANK_ALIGNMENT=1
++ ifneq ($(BANK_BIT_START), 0)
++ ifneq ($(BANK_BIT_END), 0)
++ EXTRA_CFLAGS += -DgcdBANK_BIT_START=$(BANK_BIT_START)
++ EXTRA_CFLAGS += -DgcdBANK_BIT_END=$(BANK_BIT_END)
++ endif
++ endif
++
++ ifneq ($(BANK_CHANNEL_BIT), 0)
++ EXTRA_CFLAGS += -DgcdBANK_CHANNEL_BIT=$(BANK_CHANNEL_BIT)
++ endif
++endif
++
++ifneq ($(CONFIG_SYNC),)
++EXTRA_CFLAGS += -DgcdANDROID_NATIVE_FENCE_SYNC=1
++endif
++
++EXTRA_CFLAGS += -I$(AQROOT)/hal/kernel/inc
++EXTRA_CFLAGS += -I$(AQROOT)/hal/kernel
++EXTRA_CFLAGS += -I$(AQARCH)/hal/kernel
++EXTRA_CFLAGS += -I$(AQROOT)/hal/os/linux/kernel
++
++ifeq ($(VIVANTE_ENABLE_VG), 1)
++EXTRA_CFLAGS += -I$(AQVGARCH)/hal/kernel
++endif
++
++obj-$(CONFIG_MXC_GPU_VIV) += galcore.o
++
++galcore-objs := $(OBJS)
++
++endif
+diff -Nur linux-4.1.3/drivers/mxc/gpu-viv/Kconfig linux-xbian-imx6/drivers/mxc/gpu-viv/Kconfig
+--- linux-4.1.3/drivers/mxc/gpu-viv/Kconfig 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/gpu-viv/Kconfig 2015-07-27 23:13:06.166979215 +0200
+@@ -0,0 +1,9 @@
++menu "MXC Vivante GPU support"
++ depends on SOC_IMX6Q
++
++config MXC_GPU_VIV
++ tristate "MXC Vivante GPU support"
++ ---help---
++ Say Y to get the GPU driver support.
++
++endmenu
+diff -Nur linux-4.1.3/drivers/mxc/hdmi-cec/Kconfig linux-xbian-imx6/drivers/mxc/hdmi-cec/Kconfig
+--- linux-4.1.3/drivers/mxc/hdmi-cec/Kconfig 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/hdmi-cec/Kconfig 2015-07-27 23:13:06.226765901 +0200
+@@ -0,0 +1,11 @@
++
++menu "MXC HDMI CEC (Consumer Electronics Control) support"
++
++config MXC_HDMI_CEC
++ tristate "Support for MXC HDMI CEC (Consumer Electronics Control)"
++ depends on MFD_MXC_HDMI
++ depends on FB_MXC_HDMI || DRM_IMX_HDMI
++ help
++ The HDMI CEC device implement low level protocol on i.MX6x platforms.
++
++endmenu
+diff -Nur linux-4.1.3/drivers/mxc/hdmi-cec/Makefile linux-xbian-imx6/drivers/mxc/hdmi-cec/Makefile
+--- linux-4.1.3/drivers/mxc/hdmi-cec/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/hdmi-cec/Makefile 2015-07-27 23:13:06.226765901 +0200
+@@ -0,0 +1 @@
++obj-$(CONFIG_MXC_HDMI_CEC) += mxc_hdmi-cec.o
+diff -Nur linux-4.1.3/drivers/mxc/hdmi-cec/mxc_hdmi-cec.c linux-xbian-imx6/drivers/mxc/hdmi-cec/mxc_hdmi-cec.c
+--- linux-4.1.3/drivers/mxc/hdmi-cec/mxc_hdmi-cec.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/hdmi-cec/mxc_hdmi-cec.c 2015-07-27 23:13:06.226765901 +0200
+@@ -0,0 +1,786 @@
++/*
++ * Copyright (C) 2012-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*!
++ * @file mxc_hdmi-cec.c
++ *
++ * @brief HDMI CEC system initialization and file operation implementation
++ *
++ * @ingroup HDMI
++ */
++
++//#define DEBUG
++
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/mm.h>
++#include <linux/fs.h>
++#include <linux/stat.h>
++#include <linux/platform_device.h>
++#include <linux/poll.h>
++#include <linux/wait.h>
++#include <linux/list.h>
++#include <linux/delay.h>
++#include <linux/fsl_devices.h>
++#include <linux/uaccess.h>
++#include <linux/io.h>
++#include <linux/slab.h>
++#include <linux/vmalloc.h>
++#include <linux/workqueue.h>
++#include <linux/sizes.h>
++
++#include <linux/console.h>
++#include <linux/types.h>
++#include <linux/mfd/mxc-hdmi-core.h>
++#include <linux/pinctrl/consumer.h>
++
++#include <video/mxc_hdmi.h>
++
++#include "mxc_hdmi-cec.h"
++
++#define MAXCLIENTS 15
++
++struct hdmi_cec_priv {
++ u8 la;
++ struct list_head msg_head;
++ struct list_head client_node;
++ struct list_head wakeup_node;
++ wait_queue_head_t hdmi_cec_qm;
++ spinlock_t i_lock_cl;
++};
++
++struct hdmi_cec_event {
++ u8 event_type;
++ u8 msg_len;
++ u8 msg[MAX_MESSAGE_LEN];
++};
++
++struct hdmi_cec_event_list {
++ struct hdmi_cec_event data;
++ u8 libcec_la;
++ struct list_head msg_node;
++};
++
++struct hdmi_cec_shared {
++ bool write_busy;
++ int receive_error;
++ int send_error;
++ struct delayed_work hdmi_cec_work;
++ spinlock_t i_lock;
++ spinlock_t buffer_lock;
++ struct mutex m_lock;
++ struct list_head client_head;
++ struct list_head buffer_head;
++ int nr_ff;
++ u16 addresses;
++ u8 latest_cec_stat;
++ u32 physical_address;
++};
++
++static struct hdmi_cec_shared hdmi_cec_root;
++
++static bool hdmi_cec_state;
++static int hdmi_cec_ready = 0;
++static int hdmi_cec_major;
++static struct class *hdmi_cec_class;
++static u8 open_count = 0;
++
++static int in_worker = 0;
++
++static wait_queue_head_t hdmi_cec_qs, hdmi_cec_qw;
++
++static int SIGNAL_FREE_ARB = 0;
++
++static inline bool la_is_local(u8 la)
++{
++ return (la == 0xf) ? false : hdmi_cec_root.addresses & BIT(la);
++}
++
++static inline u8 get_o(u8 la)
++{
++ return (la >> 4);
++}
++
++static inline u8 get_o_e(struct hdmi_cec_event_list *event)
++{
++ return (event->data.msg[0] >> 4);
++}
++
++static inline u8 get_d(u8 la)
++{
++ return (la & 0x0f);
++}
++
++static inline u8 get_d_e(struct hdmi_cec_event_list *event)
++{
++ return (event->data.msg[0] & 0x0f);
++}
++
++int mxc_hdmi_cec_buffer(uint16_t offset, int len, u8 cec_type, u8 llla)
++{
++ struct hdmi_cec_event_list *event = NULL;
++ unsigned long flags;
++ u8 i;
++
++ event = kzalloc(sizeof(struct hdmi_cec_event_list), GFP_ATOMIC);
++ if (NULL == event) {
++ pr_err("%s: Not enough memory!\n", __func__);
++ return -ENOMEM;
++ }
++ event->data.msg_len = len;
++ if (!event->data.msg_len || event->data.msg_len > MAX_MESSAGE_LEN) {
++ pr_err("%s: Bad message size %d!\n", __func__, event->data.msg_len);
++ kfree(event);
++ return -E2BIG;
++ }
++
++ for (i = 0; i < event->data.msg_len; i++)
++ event->data.msg[i] = hdmi_readb(offset+i);
++
++ event->data.event_type = cec_type;
++ event->libcec_la = llla ? llla : get_o(event->data.msg[0]);
++
++ spin_lock_irqsave(&hdmi_cec_root.buffer_lock, flags);
++ list_add_tail(&event->msg_node, &hdmi_cec_root.buffer_head);
++ spin_unlock_irqrestore(&hdmi_cec_root.buffer_lock, flags);
++ return 0;
++}
++
++static irqreturn_t mxc_hdmi_cec_isr(int irq, void *data)
++{
++ u8 cec_stat = 0;
++ u8 val;
++ unsigned long flags;
++ irqreturn_t ret = IRQ_HANDLED;
++
++ cec_stat = hdmi_readb(HDMI_IH_CEC_STAT0);
++ if (!cec_stat || !hdmi_cec_state) {
++ ret = IRQ_NONE;
++ goto done;
++ }
++
++ pr_debug("%s: HDMI CEC interrupt handler\n", __func__);
++
++ spin_lock_irqsave(&hdmi_cec_root.i_lock, flags);
++
++ hdmi_writeb(0x7f, HDMI_IH_MUTE_CEC_STAT0);
++ hdmi_writeb(cec_stat, HDMI_IH_CEC_STAT0);
++
++ if (cec_stat & (HDMI_IH_CEC_STAT0_ERROR_INIT | HDMI_IH_CEC_STAT0_ARB_LOST)) {
++ hdmi_cec_root.send_error++;
++ SIGNAL_FREE_ARB = cec_stat & HDMI_IH_CEC_STAT0_ERROR_INIT ? SIGNAL_FREE_TIME_RESEND : SIGNAL_FREE_LOST;
++ pr_debug("%s: error %d\n", __func__, hdmi_cec_root.send_error);
++ wake_up(&hdmi_cec_qs);
++ }
++ if (cec_stat & (HDMI_IH_CEC_STAT0_NACK | HDMI_IH_CEC_STAT0_DONE)) {
++ mxc_hdmi_cec_buffer(HDMI_CEC_TX_DATA0, hdmi_readb(HDMI_CEC_TX_CNT),
++ cec_stat & HDMI_IH_CEC_STAT0_NACK ? MESSAGE_TYPE_NOACK : MESSAGE_TYPE_SEND_SUCCESS, 0);
++ hdmi_cec_root.send_error = 0;
++ hdmi_cec_root.write_busy = false;
++ wake_up(&hdmi_cec_qs);
++ hdmi_writeb(0, HDMI_CEC_TX_CNT);
++ }
++ if (cec_stat & HDMI_IH_CEC_STAT0_EOM) {
++ mxc_hdmi_cec_buffer(HDMI_CEC_RX_DATA0, hdmi_readb(HDMI_CEC_RX_CNT), MESSAGE_TYPE_RECEIVE_SUCCESS, 0);
++ hdmi_writeb(0, HDMI_CEC_LOCK);
++ }
++
++ pr_debug("%s: HDMI CEC interrupt received %#x\n", __func__, cec_stat);
++ if (!in_worker) {
++ in_worker = 1;
++ schedule_delayed_work(&hdmi_cec_root.hdmi_cec_work, msecs_to_jiffies(20));
++ }
++
++ spin_unlock_irqrestore(&hdmi_cec_root.i_lock, flags);
++ val = HDMI_IH_CEC_STAT0_WAKEUP | HDMI_IH_CEC_STAT0_ERROR_FOLL;
++ hdmi_writeb(val, HDMI_IH_MUTE_CEC_STAT0);
++
++done:
++ return ret;
++}
++
++static void __mxc_hdmi_cec_msg(struct hdmi_cec_event_list *event, struct hdmi_cec_priv *client, struct list_head *wakeup, u8 event_type)
++{
++ struct hdmi_cec_event_list *tevent = kzalloc(sizeof(struct hdmi_cec_event_list), GFP_KERNEL);
++ unsigned long flags;
++
++ if (!tevent) {
++ pr_err("%s: Not enough memory!\n", __func__);
++ return;
++ }
++ memcpy(&tevent->data, &event->data, min(sizeof(struct hdmi_cec_event), (size_t)(event->data.msg_len + 2)));
++ if (event_type)
++ tevent->data.event_type = event_type;
++
++ spin_lock_irqsave(&client->i_lock_cl, flags);
++ list_add_tail(&tevent->msg_node, &client->msg_head);
++ spin_unlock_irqrestore(&client->i_lock_cl, flags);
++
++ if (wakeup)
++ list_add_tail(&client->wakeup_node, wakeup);
++}
++
++void mxc_hdmi_cec_handle(u32 cec_stat)
++{
++ struct hdmi_cec_event_list *event = NULL;
++ struct hdmi_cec_priv *client = NULL;
++
++ if (cec_stat)
++ hdmi_cec_root.physical_address = cec_stat;
++
++ /* HDMI cable connected / HDMI cable disconnected */
++ if (!hdmi_cec_ready)
++ return;
++ pr_debug("%s: enter\n", __func__);
++
++ event = kzalloc(sizeof(struct hdmi_cec_event_list), GFP_ATOMIC);
++ if (!event) {
++ pr_err("%s: Not enough memory!\n", __func__);
++ return;
++ }
++ event->data.event_type = cec_stat ?
++ MESSAGE_TYPE_CONNECTED : MESSAGE_TYPE_DISCONNECTED;
++
++ list_for_each_entry(client, &hdmi_cec_root.client_head, client_node) {
++ mutex_lock(&hdmi_cec_root.m_lock);
++ __mxc_hdmi_cec_msg(event, client, NULL, 0);
++ mutex_unlock(&hdmi_cec_root.m_lock);
++ wake_up(&client->hdmi_cec_qm);
++ }
++ pr_debug("%s: exit\n", __func__);
++}
++EXPORT_SYMBOL(mxc_hdmi_cec_handle);
++
++void mxc_hdmi_cec_msg(void)
++{
++ struct hdmi_cec_event_list *event = NULL;
++ struct hdmi_cec_priv *client = NULL;
++ unsigned long flags;
++ LIST_HEAD(wakeup);
++
++ spin_lock_irqsave(&hdmi_cec_root.buffer_lock, flags);
++ event = list_first_entry_or_null(&hdmi_cec_root.buffer_head, struct hdmi_cec_event_list, msg_node);
++ if (!event) {
++ spin_unlock_irqrestore(&hdmi_cec_root.buffer_lock, flags);
++ return;
++ }
++ list_del_init(&event->msg_node);
++ spin_unlock_irqrestore(&hdmi_cec_root.buffer_lock, flags);
++
++ event->data.event_type = (event->data.event_type == MESSAGE_TYPE_NOACK && la_is_local(event->data.msg[0] & 0x0f)) ?
++ MESSAGE_TYPE_SEND_SUCCESS : event->data.event_type;
++
++ list_for_each_entry(client, &hdmi_cec_root.client_head, client_node) {
++ if (client->la == 0xff) continue;
++ pr_debug("client %d: MSG from %d to %d, %x. (clla: %d) ET: %d\n", client->la, get_o(event->data.msg[0]), get_d(event->data.msg[0]), event->data.msg[1], event->libcec_la, event->data.event_type);
++
++ if ((event->data.event_type == MESSAGE_TYPE_RECEIVE_SUCCESS &&
++ ((get_d_e(event) == 15 && event->libcec_la != client->la) || (event->data.msg[0] & 0x0f) == client->la))
++ ||
++ (event->data.event_type != MESSAGE_TYPE_RECEIVE_SUCCESS &&
++ ((get_o_e(event) == get_d_e(event) && client->la == 15) || client->la == get_o_e(event))) )
++ {
++ pr_debug("writing to %d\n", client->la);
++ __mxc_hdmi_cec_msg(event, client, &wakeup, 0);
++ }
++
++ if ((event->data.event_type == MESSAGE_TYPE_SEND_SUCCESS) &&
++ ((la_is_local(event->data.msg[0] & 0x0f) && (event->data.msg[0] & 0x0f) == client->la)
++ ||
++ ((event->data.msg[0] & 0x0f) == 15 && !event->libcec_la)) )
++ {
++ pr_debug("writing to %d\n", client->la);
++ __mxc_hdmi_cec_msg(event, client, &wakeup, MESSAGE_TYPE_RECEIVE_SUCCESS);
++ }
++ }
++ list_for_each_entry(client, &wakeup, wakeup_node)
++ wake_up(&(client->hdmi_cec_qm));
++ kfree(event);
++}
++
++static void mxc_hdmi_cec_worker(struct work_struct *work)
++{
++ pr_debug("%s: \n", __func__);
++ while (!list_empty_careful(&hdmi_cec_root.buffer_head))
++ mxc_hdmi_cec_msg();
++ in_worker = 0;
++ pr_debug("%s: exit\n", __func__);
++}
++
++static long hdmi_cec_set_address(u8 arg, struct hdmi_cec_priv *hdmi_cec);
++/*!
++ * @brief open function for cec file operation
++ *
++ * @return 0 on success or negative error code on error
++ */
++static int hdmi_cec_open(struct inode *inode, struct file *filp)
++{
++ struct hdmi_cec_priv *hdmi_cec = NULL;
++
++ mutex_lock(&hdmi_cec_root.m_lock);
++ if (open_count == MAXCLIENTS || !hdmi_cec_ready) {
++ mutex_unlock(&hdmi_cec_root.m_lock);
++ return -EBUSY;
++ }
++ open_count++;
++
++ hdmi_cec = kzalloc(sizeof(struct hdmi_cec_priv), GFP_KERNEL);
++ hdmi_cec->la = -1;
++ init_waitqueue_head(&(hdmi_cec->hdmi_cec_qm));
++ spin_lock_init(&(hdmi_cec->i_lock_cl));
++ INIT_LIST_HEAD(&hdmi_cec->msg_head);
++
++ filp->private_data = (void *)(hdmi_cec);
++
++ list_add_tail(&hdmi_cec->client_node, &hdmi_cec_root.client_head);
++ hdmi_cec_set_address(15, hdmi_cec);
++ mutex_unlock(&hdmi_cec_root.m_lock);
++
++ return 0;
++}
++
++static ssize_t hdmi_cec_read(struct file *file, char __user *buf, size_t count,
++ loff_t *ppos)
++{
++ struct hdmi_cec_priv *hdmi_cec = file->private_data;
++ int ret = 0;
++
++ if (!open_count || hdmi_cec->la == 0xff)
++ return -ENODEV;
++
++ pr_debug("%s: client la %x, (addr %x)\n", __func__, hdmi_cec->la, (unsigned int)hdmi_cec);
++
++ count = min(count, sizeof(struct hdmi_cec_event));
++ do {
++ unsigned long flags;
++ struct hdmi_cec_event_list *event = NULL;
++
++ spin_lock_irqsave(&(hdmi_cec->i_lock_cl), flags);
++ if (!list_empty(&hdmi_cec->msg_head)) {
++ event = list_first_entry_or_null(&hdmi_cec->msg_head, struct hdmi_cec_event_list, msg_node);
++ list_del(&event->msg_node);
++ }
++ spin_unlock_irqrestore(&(hdmi_cec->i_lock_cl), flags);
++
++ if (event) {
++ ret = copy_to_user(buf, &event->data, count) ? -EFAULT : count;
++ kfree(event);
++ }
++ else if (file->f_flags & O_NONBLOCK) {
++ ret = -EAGAIN;
++ }
++ else if (wait_event_interruptible(hdmi_cec->hdmi_cec_qm, (!list_empty(&hdmi_cec->msg_head)))) {
++ ret = -ERESTARTSYS;
++ }
++ } while(!ret);
++
++ pr_debug("%s: exit %d\n", __func__, ret);
++ return ret;
++}
++
++static ssize_t hdmi_cec_write(struct file *file, const char __user *buf,
++ size_t count, loff_t *ppos)
++{
++ struct hdmi_cec_priv *hdmi_cec = file->private_data;
++ int ret = 0 , i = 0;
++ u8 msg[MAX_MESSAGE_LEN];
++ u8 val = 0;
++ int timeout = 1500;
++
++ if (!open_count || hdmi_cec->la == 0xff)
++ return -ENODEV;
++
++ if (count > MAX_MESSAGE_LEN)
++ return -E2BIG;
++
++ memset(&msg, 0, MAX_MESSAGE_LEN);
++ if (copy_from_user(&msg, buf, count))
++ return -EFAULT;
++
++ if (file->f_flags & O_NONBLOCK && hdmi_cec_root.write_busy)
++ return -EAGAIN;
++ else if (wait_event_interruptible(hdmi_cec_qw, (!hdmi_cec_root.write_busy)))
++ return -ERESTARTSYS;
++
++ mutex_lock(&hdmi_cec_root.m_lock);
++ pr_debug("%s: \n", __func__);
++ hdmi_cec_root.write_busy = true;
++
++ hdmi_writeb(count, HDMI_CEC_TX_CNT);
++ for (i = 0; i < count; i++)
++ hdmi_writeb(msg[i], HDMI_CEC_TX_DATA0+i);
++
++ if (get_d(msg[0]) == 15) {
++ ret = count;
++ mxc_hdmi_cec_buffer(HDMI_CEC_TX_DATA0, count, MESSAGE_TYPE_RECEIVE_SUCCESS, hdmi_cec->la);
++ pr_debug("%s: wait_event la_is_local\n", __func__);
++ hdmi_cec_root.write_busy = false;
++ }
++
++ do {
++ val = hdmi_readb(HDMI_CEC_CTRL); val |= 0x01; val &= ~0x6;
++ val |= SIGNAL_FREE_ARB;
++ hdmi_writeb(val, HDMI_CEC_CTRL);
++ SIGNAL_FREE_ARB = SIGNAL_FREE_TIME_NORMAL;
++
++ ret = wait_event_timeout(hdmi_cec_qs, !((val = hdmi_readb(HDMI_CEC_CTRL)) & 0x01), msecs_to_jiffies(timeout));
++ pr_debug("%s: wait_event ret %d\n", __func__, ret);
++ if (hdmi_cec_root.send_error > 5 || ret < 2) {
++ hdmi_writeb(0, HDMI_CEC_TX_CNT);
++ hdmi_cec_root.write_busy = false;
++ ret = -EIO;
++ } else if (hdmi_cec_root.send_error && ret > 1) {
++ pr_debug("%s: --- resending msg\n", __func__);
++ timeout = jiffies_to_msecs(ret);
++ ret = 0;
++ } else if (ret > 1) {
++ ret = count;
++ }
++ } while(!ret);
++
++ mutex_unlock(&hdmi_cec_root.m_lock);
++ wake_up(&hdmi_cec_qw);
++ return ret;
++}
++
++static void hdmi_cec_hwenable(void)
++{
++ u8 val;
++
++ pr_debug("%s: \n", __func__);
++ hdmi_cec_state = true;
++
++ val = hdmi_readb(HDMI_MC_CLKDIS);
++ val &= ~HDMI_MC_CLKDIS_CECCLK_DISABLE;
++ hdmi_writeb(val, HDMI_MC_CLKDIS);
++
++ val = HDMI_IH_CEC_STAT0_ERROR_INIT | HDMI_IH_CEC_STAT0_NACK |
++ HDMI_IH_CEC_STAT0_EOM | HDMI_IH_CEC_STAT0_DONE |
++ HDMI_IH_CEC_STAT0_ARB_LOST;
++ hdmi_writeb(val, HDMI_CEC_POLARITY);
++
++ val = HDMI_IH_CEC_STAT0_WAKEUP | HDMI_IH_CEC_STAT0_ERROR_FOLL;
++ hdmi_writeb(val, HDMI_CEC_MASK);
++ hdmi_writeb(val, HDMI_IH_MUTE_CEC_STAT0);
++ hdmi_writeb(0x0, HDMI_CEC_LOCK);
++ hdmi_writeb(0x2, HDMI_CEC_CTRL);
++}
++
++static void hdmi_cec_hwdisable(void)
++{
++ u8 val;
++
++ pr_debug("%s: \n", __func__);
++ hdmi_cec_state = false;
++
++ hdmi_writeb(0x10, HDMI_CEC_CTRL);
++
++ val = HDMI_IH_CEC_STAT0_WAKEUP | HDMI_IH_CEC_STAT0_ERROR_FOLL |
++ HDMI_IH_CEC_STAT0_ERROR_INIT | HDMI_IH_CEC_STAT0_ARB_LOST |
++ HDMI_IH_CEC_STAT0_NACK | HDMI_IH_CEC_STAT0_EOM |
++ HDMI_IH_CEC_STAT0_DONE;
++ hdmi_writeb(val, HDMI_CEC_MASK);
++ hdmi_writeb(val, HDMI_IH_MUTE_CEC_STAT0);
++
++ hdmi_writeb(0x0, HDMI_CEC_POLARITY);
++
++ val = hdmi_readb(HDMI_MC_CLKDIS);
++ val |= HDMI_MC_CLKDIS_CECCLK_DISABLE;
++ hdmi_writeb(val, HDMI_MC_CLKDIS);
++}
++
++static long hdmi_cec_set_address(u8 arg, struct hdmi_cec_priv *hdmi_cec)
++{
++
++ if (hdmi_cec->la == arg)
++ return 0;
++
++ pr_debug("%s: to %d\n", __func__, arg);
++
++ if (arg == 15)
++ hdmi_cec_root.nr_ff++;
++ if (hdmi_cec->la == 15)
++ hdmi_cec_root.nr_ff--;
++ else
++ hdmi_cec_root.addresses &= ~BIT(hdmi_cec->la);
++
++ hdmi_cec->la = arg;
++ if ((u8)arg != 0xff)
++ hdmi_cec_root.addresses |= BIT(arg);
++ else
++ wake_up(&hdmi_cec->hdmi_cec_qm);
++
++ if (!hdmi_cec_root.nr_ff)
++ hdmi_cec_root.addresses &= ~BIT(15);
++
++ hdmi_writeb(hdmi_cec_root.addresses & 0xff, HDMI_CEC_ADDR_L);
++ /*
++ * Don't register LA = 15 to with hardware. with it set, broadcast messages are never
++ * sent (considered local by CEC controler)
++ */
++ hdmi_writeb((hdmi_cec_root.addresses & 0x7f00) >> 8, HDMI_CEC_ADDR_H);
++ return 0;
++}
++
++/*!
++ * @brief IO ctrl function for vpu file operation
++ * @param cmd IO ctrl command
++ * @return 0 on success or negative error code on error
++ */
++static long hdmi_cec_ioctl(struct file *filp, u_int cmd,
++ u_long arg)
++{
++ int ret = 0, i;
++ struct hdmi_cec_priv *hdmi_cec = filp->private_data;
++
++ pr_debug("%s: \n", __func__);
++
++ if (!open_count)
++ return -ENODEV;
++
++ switch (cmd) {
++ case HDMICEC_IOC_SETLOGICALADDRESS:
++ mutex_lock(&hdmi_cec_root.m_lock);
++ ret = hdmi_cec_set_address(arg, hdmi_cec);
++ mutex_unlock(&hdmi_cec_root.m_lock);
++ /*
++ * in case we have more clients, inform them about PA change.
++ * (if libCEC is not in monitoring mode, it won't allow more
++ * clients with same PA - it changes all previous holders of
++ * that 'taken' PA to 1000.
++ * to avoid that, we expand PA further by replacing first empty
++ * dimension with LA (for instance if our PA is 2.2.0.0, we
++ * change to 2.2.X.0 all concurent clients, where X is actual LA
++ */
++ if (open_count > 1 && arg != 15)
++ mxc_hdmi_cec_handle(hdmi_cec_root.physical_address);
++ break;
++
++ case HDMICEC_IOC_STARTDEVICE:
++ if (!hdmi_cec_state)
++ hdmi_cec_hwenable();
++ break;
++
++ case HDMICEC_IOC_STOPDEVICE:
++ hdmi_cec_set_address(-1, hdmi_cec);
++ if (hdmi_cec_state && open_count < 2)
++ hdmi_cec_hwdisable();
++ break;
++
++ case HDMICEC_IOC_GETPHYADDRESS:
++ ret = copy_to_user((void __user *)arg, &hdmi_cec_root.physical_address,
++ 4*sizeof(u8))?-EFAULT:0;
++ if (open_count > 1) {
++ for (i = 0; i < 4 && ((u8*)arg)[i] != 0x0; i++);
++ ((u8*)arg)[i] = hdmi_cec->la;
++ }
++ break;
++
++ default:
++ ret = -EINVAL;
++ break;
++ }
++
++ return ret;
++}
++
++void hdmi_cec_start_device(void)
++{
++ if(open_count && hdmi_cec_ready && !hdmi_cec_state)
++ hdmi_cec_hwenable();
++}
++EXPORT_SYMBOL(hdmi_cec_start_device);
++
++void hdmi_cec_stop_device(void)
++{
++ if(hdmi_cec_ready && hdmi_cec_state)
++ hdmi_cec_hwdisable();
++}
++EXPORT_SYMBOL(hdmi_cec_stop_device);
++
++/*!
++* @brief Release function for vpu file operation
++* @return 0 on success or negative error code on error
++*/
++static int hdmi_cec_release(struct inode *inode, struct file *filp)
++{
++ struct hdmi_cec_priv *hdmi_cec = filp->private_data;
++ struct hdmi_cec_priv *client, *t;
++ unsigned long flags;
++
++ pr_debug("%s: \n", __func__);
++
++ mutex_lock(&hdmi_cec_root.m_lock);
++ spin_lock_irqsave(&hdmi_cec->i_lock_cl, flags);
++
++ hdmi_cec_set_address(-1, hdmi_cec);
++ if (!--open_count)
++ hdmi_cec_hwdisable();
++ while (!list_empty(&hdmi_cec->msg_head)) {
++ struct hdmi_cec_event_list *event = NULL;
++
++ event = list_first_entry(&hdmi_cec->msg_head, struct hdmi_cec_event_list, msg_node);
++ list_del(&event->msg_node);
++ kfree(event);
++ }
++ spin_unlock_irqrestore(&hdmi_cec->i_lock_cl, flags);
++
++ list_for_each_entry_safe(client, t, &hdmi_cec_root.client_head, client_node) {
++ if (client == hdmi_cec) {
++ list_del(&client->client_node);
++ filp->private_data = NULL;
++ kfree(client);
++ }
++ }
++
++ mutex_unlock(&hdmi_cec_root.m_lock);
++ return 0;
++}
++
++static unsigned int hdmi_cec_poll(struct file *file, poll_table *wait)
++{
++ unsigned int mask = 0;
++ struct hdmi_cec_priv *hdmi_cec = file->private_data;
++
++ pr_debug("%s: poll client %lx, la %d\n", __func__, (unsigned long)hdmi_cec, hdmi_cec->la);
++
++ if (hdmi_cec->la == 0xff)
++ return POLLHUP;
++
++ poll_wait(file, &hdmi_cec->hdmi_cec_qm, wait);
++ poll_wait(file, &hdmi_cec_qw, wait);
++
++ if (!hdmi_cec_root.write_busy)
++ mask = (POLLOUT | POLLWRNORM);
++ if (!list_empty(&hdmi_cec->msg_head))
++ mask |= (POLLIN | POLLRDNORM);
++
++ return mask;
++}
++
++const struct file_operations hdmi_cec_fops = {
++ .owner = THIS_MODULE,
++ .read = hdmi_cec_read,
++ .write = hdmi_cec_write,
++ .open = hdmi_cec_open,
++ .unlocked_ioctl = hdmi_cec_ioctl,
++ .release = hdmi_cec_release,
++ .poll = hdmi_cec_poll,
++};
++
++static int hdmi_cec_dev_probe(struct platform_device *pdev)
++{
++ int err = 0;
++ struct device *temp_class;
++ struct resource *res;
++ struct pinctrl *pinctrl;
++ int irq = platform_get_irq(pdev, 0);
++
++ hdmi_cec_major = register_chrdev(hdmi_cec_major, "mxc_hdmi_cec", &hdmi_cec_fops);
++ if (hdmi_cec_major < 0) {
++ dev_err(&pdev->dev, "%s: unable to get a major for HDMI CEC\n", __func__);
++ err = -EBUSY;
++ goto out;
++ }
++
++ res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
++ if (unlikely(res == NULL)) {
++ dev_err(&pdev->dev, "%s: No HDMI irq line provided\n", __func__);
++ goto err_out_chrdev;
++ }
++ spin_lock_init(&hdmi_cec_root.i_lock);
++
++ err = devm_request_irq(&pdev->dev, irq, mxc_hdmi_cec_isr, IRQF_SHARED,
++ dev_name(&pdev->dev), &hdmi_cec_root);
++ if (err < 0) {
++ dev_err(&pdev->dev, "%s: Unable to request irq: %d\n", __func__, err);
++ goto err_out_chrdev;
++ }
++
++ hdmi_cec_class = class_create(THIS_MODULE, "mxc_hdmi_cec");
++ if (IS_ERR(hdmi_cec_class)) {
++ err = PTR_ERR(hdmi_cec_class);
++ goto err_out_chrdev;
++ }
++
++ temp_class = device_create(hdmi_cec_class, NULL,
++ MKDEV(hdmi_cec_major, 0), NULL, "mxc_hdmi_cec");
++ if (IS_ERR(temp_class)) {
++ err = PTR_ERR(temp_class);
++ goto err_out_class;
++ }
++
++ pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
++ if (IS_ERR(pinctrl)) {
++ dev_err(&pdev->dev, "%s: can't get/select CEC pinctrl\n", __func__);
++ goto err_out_class;
++ }
++
++ init_waitqueue_head(&hdmi_cec_qs);
++ init_waitqueue_head(&hdmi_cec_qw);
++
++ INIT_LIST_HEAD(&hdmi_cec_root.client_head);
++ INIT_LIST_HEAD(&hdmi_cec_root.buffer_head);
++
++ mutex_init(&hdmi_cec_root.m_lock);
++ hdmi_cec_root.addresses = 0;
++ platform_set_drvdata(pdev, &hdmi_cec_root);
++ INIT_DELAYED_WORK(&hdmi_cec_root.hdmi_cec_work, mxc_hdmi_cec_worker);
++
++ dev_info(&pdev->dev, "%s: HDMI CEC initialized\n", __func__);
++ hdmi_cec_ready = 1;
++ goto out;
++
++err_out_class:
++ device_destroy(hdmi_cec_class, MKDEV(hdmi_cec_major, 0));
++ class_destroy(hdmi_cec_class);
++err_out_chrdev:
++ unregister_chrdev(hdmi_cec_major, "mxc_hdmi_cec");
++out:
++ return err;
++}
++
++static int hdmi_cec_dev_remove(struct platform_device *pdev)
++{
++ if (hdmi_cec_major > 0) {
++ flush_scheduled_work();
++ device_destroy(hdmi_cec_class, MKDEV(hdmi_cec_major, 0));
++ class_destroy(hdmi_cec_class);
++ unregister_chrdev(hdmi_cec_major, "mxc_hdmi_cec");
++ hdmi_cec_major = 0;
++ }
++ return 0;
++}
++
++static const struct of_device_id imx_hdmi_cec_match[] = {
++ { .compatible = "fsl,imx6q-hdmi-cec", },
++ { .compatible = "fsl,imx6dl-hdmi-cec", },
++ { /* sentinel */ }
++};
++
++static struct platform_driver mxc_hdmi_cec_driver = {
++ .probe = hdmi_cec_dev_probe,
++ .remove = hdmi_cec_dev_remove,
++ .driver = {
++ .name = "mxc_hdmi_cec",
++ .of_match_table = imx_hdmi_cec_match,
++ },
++};
++
++module_platform_driver(mxc_hdmi_cec_driver);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("Linux HDMI CEC driver for Freescale i.MX/MXC");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:mxc_hdmi_cec");
++
+diff -Nur linux-4.1.3/drivers/mxc/hdmi-cec/mxc_hdmi-cec.debug.c linux-xbian-imx6/drivers/mxc/hdmi-cec/mxc_hdmi-cec.debug.c
+--- linux-4.1.3/drivers/mxc/hdmi-cec/mxc_hdmi-cec.debug.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/hdmi-cec/mxc_hdmi-cec.debug.c 2015-07-27 23:13:06.226765901 +0200
+@@ -0,0 +1,765 @@
++/*
++ * Copyright (C) 2012-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*!
++ * @file mxc_hdmi-cec.c
++ *
++ * @brief HDMI CEC system initialization and file operation implementation
++ *
++ * @ingroup HDMI
++ */
++
++//#define DEBUG
++
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/mm.h>
++#include <linux/fs.h>
++#include <linux/stat.h>
++#include <linux/platform_device.h>
++#include <linux/poll.h>
++#include <linux/wait.h>
++#include <linux/list.h>
++#include <linux/delay.h>
++#include <linux/fsl_devices.h>
++#include <linux/uaccess.h>
++#include <linux/io.h>
++#include <linux/slab.h>
++#include <linux/vmalloc.h>
++#include <linux/workqueue.h>
++#include <linux/sizes.h>
++
++#include <linux/console.h>
++#include <linux/types.h>
++#include <linux/mfd/mxc-hdmi-core.h>
++#include <linux/pinctrl/consumer.h>
++
++#include <video/mxc_hdmi.h>
++
++#include "mxc_hdmi-cec.h"
++
++#define MAXCLIENTS 15
++
++struct hdmi_cec_priv {
++ u8 la;
++ u8 libcec_la;
++ struct list_head msg_head;
++ struct list_head client_node;
++ struct list_head wakeup_node;
++ wait_queue_head_t hdmi_cec_qm;
++ spinlock_t i_lock_cl;
++};
++
++struct hdmi_cec_event {
++ u8 event_type;
++ u8 msg_len;
++ u8 msg[MAX_MESSAGE_LEN];
++};
++
++struct hdmi_cec_event_list {
++ struct hdmi_cec_event data;
++ struct list_head msg_node;
++};
++
++struct hdmi_cec_shared {
++ bool write_busy;
++ int receive_error;
++ int send_error;
++ struct delayed_work hdmi_cec_work, hdmi_msg_trigger;
++ spinlock_t i_lock;
++ struct mutex m_lock_cl;
++ struct list_head client_head;
++ int nr_ff;
++ u16 addresses;
++ u8 latest_cec_stat;
++ u32 physical_address;
++};
++
++static struct hdmi_cec_shared hdmi_cec_root;
++
++static bool hdmi_cec_state;
++static int hdmi_cec_ready = 0;
++static int hdmi_cec_major;
++static struct class *hdmi_cec_class;
++static u8 open_count = 0;
++
++static wait_queue_head_t hdmi_cec_qs, hdmi_cec_qw;
++
++static inline bool la_is_local(u8 la)
++{
++ return (la == 0xf) ? false : hdmi_cec_root.addresses & BIT(la);
++}
++
++static irqreturn_t mxc_hdmi_cec_isr(int irq, void *data)
++{
++ u8 cec_stat = 0;
++ unsigned long flags;
++ irqreturn_t ret = IRQ_HANDLED;
++
++ spin_lock_irqsave(&hdmi_cec_root.i_lock, flags);
++
++ cec_stat = hdmi_readb(HDMI_IH_CEC_STAT0);
++ if (!cec_stat) {
++ ret = IRQ_NONE;
++ goto irqnone;
++ }
++ hdmi_writeb(0x7f, HDMI_IH_MUTE_CEC_STAT0);
++ hdmi_writeb(cec_stat, HDMI_IH_CEC_STAT0);
++
++ if (cec_stat & HDMI_IH_CEC_STAT0_ERROR_INIT) {
++ hdmi_cec_root.send_error++;
++ pr_debug("%s: error %d\n", __func__, hdmi_cec_root.send_error);
++ wake_up(&hdmi_cec_qs);
++ }
++ if (cec_stat & (HDMI_IH_CEC_STAT0_NACK | HDMI_IH_CEC_STAT0_DONE)) {
++ hdmi_cec_root.send_error = 0;
++ wake_up(&hdmi_cec_qs);
++ }
++
++ hdmi_cec_root.latest_cec_stat = cec_stat;
++ pr_debug("%s: HDMI CEC interrupt received\n", __func__);
++ schedule_delayed_work(&(hdmi_cec_root.hdmi_cec_work), msecs_to_jiffies(5));
++
++irqnone:
++ spin_unlock_irqrestore(&hdmi_cec_root.i_lock, flags);
++ return ret;
++}
++
++static void __mxc_hdmi_cec_msg(struct hdmi_cec_event_list *event, struct hdmi_cec_priv *client, struct list_head *wakeup, u8 event_type)
++{
++ struct hdmi_cec_event_list *tevent = NULL;
++ unsigned long flags;
++
++ if (!(tevent = kzalloc(sizeof(struct hdmi_cec_event_list), GFP_KERNEL))) {
++ pr_err("%s: Not enough memory!\n", __func__);
++ return;
++ }
++ memcpy(tevent, event, max(sizeof(struct hdmi_cec_event_list),(size_t)event->data.msg_len));
++ if (event_type)
++ tevent->data.event_type = event_type;
++ spin_lock_irqsave(&client->i_lock_cl, flags);
++ list_add_tail(&tevent->msg_node, &client->msg_head);
++ spin_unlock_irqrestore(&client->i_lock_cl, flags);
++
++ if (wakeup)
++ list_add_tail(&client->wakeup_node, wakeup);
++ pr_debug("%s: -- event to client %x\n", __func__, (int)client);
++}
++
++void mxc_hdmi_cec_handle(u32 cec_stat)
++{
++ struct hdmi_cec_event_list *event = NULL;
++ struct hdmi_cec_priv *client = NULL;
++
++ if (cec_stat)
++ hdmi_cec_root.physical_address = cec_stat;
++
++ /* HDMI cable connected / HDMI cable disconnected */
++ if (!hdmi_cec_ready)
++ return;
++ pr_debug("%s: enter\n", __func__);
++
++ event = kzalloc(sizeof(struct hdmi_cec_event_list), GFP_KERNEL);
++ if (!event) {
++ pr_err("%s: Not enough memory!\n", __func__);
++ return;
++ }
++ event->data.event_type = cec_stat ?
++ MESSAGE_TYPE_CONNECTED : MESSAGE_TYPE_DISCONNECTED;
++
++ list_for_each_entry(client, &hdmi_cec_root.client_head, client_node) {
++ __mxc_hdmi_cec_msg(event, client, NULL, 0);
++ wake_up(&client->hdmi_cec_qm);
++ }
++ pr_debug("%s: exit\n", __func__);
++}
++EXPORT_SYMBOL(mxc_hdmi_cec_handle);
++
++void mxc_hdmi_cec_msg(u8 event_type)
++{
++ struct hdmi_cec_event_list *event = NULL;
++ struct hdmi_cec_priv *client = NULL;
++ u8 i;
++ LIST_HEAD(wakeup);
++
++ event = kzalloc(sizeof(struct hdmi_cec_event_list), GFP_KERNEL);
++ if (NULL == event) {
++ pr_err("%s: Not enough memory!\n", __func__);
++ goto error2;
++ }
++ event->data.msg_len = (event_type == MESSAGE_TYPE_RECEIVE_SUCCESS) ?
++ hdmi_readb(HDMI_CEC_RX_CNT) : hdmi_readb(HDMI_CEC_TX_CNT);
++
++ if (!event->data.msg_len || event->data.msg_len > MAX_MESSAGE_LEN) {
++ pr_err("%s: Bad message size %d!\n", __func__, event->data.msg_len);
++ goto error1;
++ }
++
++ for (i = 0; i < event->data.msg_len; i++)
++ event->data.msg[i] = (event_type == MESSAGE_TYPE_RECEIVE_SUCCESS) ?
++ hdmi_readb(HDMI_CEC_RX_DATA0+i) : hdmi_readb(HDMI_CEC_TX_DATA0+i);
++
++ if (event_type == MESSAGE_TYPE_RECEIVE_SUCCESS)
++ hdmi_writeb(0x0, HDMI_CEC_LOCK);
++
++ event->data.event_type = (event_type == MESSAGE_TYPE_NOACK && la_is_local(event->data.msg[0] & 0x0f)) ?
++ MESSAGE_TYPE_SEND_SUCCESS : event_type;
++
++ list_for_each_entry(client, &hdmi_cec_root.client_head, client_node) {
++ if (client->la == 0xff) continue;
++ pr_debug("%s: -- l:%x, r:%x, ch:%x LA: %x\n", __func__, (event->data.msg[0] & 0xf0) >> 4, event->data.msg[0] & 0x0f, client->libcec_la, client->la);
++
++ if ((event_type == MESSAGE_TYPE_RECEIVE_SUCCESS &&
++ (((event->data.msg[0] & 0x0f) == 15 && client->libcec_la != client->la) || (event->data.msg[0] & 0x0f) == client->la))
++ ||
++ (event_type != MESSAGE_TYPE_RECEIVE_SUCCESS &&
++ (client->libcec_la == (int)client->la)) )
++ {
++ pr_debug("%s: -- adding msg %x->%x to client %x (event: %x)\n", __func__, (event->data.msg[0] & 0xf0) >> 4, event->data.msg[0] & 0x0f, client->la, (int)event);
++ __mxc_hdmi_cec_msg(event, client, &wakeup, 0);
++ }
++
++ if ((event->data.event_type == MESSAGE_TYPE_SEND_SUCCESS) &&
++ ((la_is_local(event->data.msg[0] & 0x0f) && (event->data.msg[0] & 0x0f) == client->la)
++ ||
++ ((event->data.msg[0] & 0x0f) == 15 && !client->libcec_la)) )
++ {
++ pr_debug("%s: -- COPYing event to client %x\n", __func__, (int)client);
++ __mxc_hdmi_cec_msg(event, client, &wakeup, MESSAGE_TYPE_RECEIVE_SUCCESS);
++ }
++ client->libcec_la = 0;
++ }
++ list_for_each_entry(client, &wakeup, wakeup_node)
++ wake_up(&(client->hdmi_cec_qm));
++
++error1:
++ kfree(event);
++error2:
++ if (event_type != MESSAGE_TYPE_RECEIVE_SUCCESS) {
++ mutex_lock(&hdmi_cec_root.m_lock_cl);
++ hdmi_cec_root.write_busy = false;
++ hdmi_writeb(0, HDMI_CEC_TX_CNT);
++ mutex_unlock(&hdmi_cec_root.m_lock_cl);
++ wake_up(&hdmi_cec_qw);
++ }
++}
++
++static void mxc_hdmi_cec_worker(struct work_struct *work)
++{
++ unsigned long flags;
++ u8 val;
++
++ pr_debug("%s: \n", __func__);
++ if (hdmi_cec_root.latest_cec_stat && open_count) {
++ /* The current transmission is successful (for initiator only).*/
++ if (hdmi_cec_root.latest_cec_stat & HDMI_IH_CEC_STAT0_DONE) {
++ mxc_hdmi_cec_msg(MESSAGE_TYPE_SEND_SUCCESS);
++ }
++ /*A frame is not acknowledged in a directly addressed message. Or a frame is negatively acknowledged in
++ a broadcast message (for initiator only).*/
++ if (hdmi_cec_root.latest_cec_stat & HDMI_IH_CEC_STAT0_NACK) {
++ mxc_hdmi_cec_msg(MESSAGE_TYPE_NOACK);
++ }
++ /*EOM is detected so that the received data is ready in the receiver data buffer*/
++ if (hdmi_cec_root.latest_cec_stat & HDMI_IH_CEC_STAT0_EOM) {
++ mxc_hdmi_cec_msg(MESSAGE_TYPE_RECEIVE_SUCCESS);
++ }
++ hdmi_cec_root.latest_cec_stat = 0;
++ }
++
++ val = HDMI_IH_CEC_STAT0_WAKEUP | HDMI_IH_CEC_STAT0_ERROR_FOLL | HDMI_IH_CEC_STAT0_ARB_LOST;
++// spin_lock_irqsave(&hdmi_cec_root.i_lock, flags);
++ hdmi_writeb(val, HDMI_IH_MUTE_CEC_STAT0);
++// spin_unlock_irqrestore(&hdmi_cec_root.i_lock, flags);
++ pr_debug("%s: exit\n", __func__);
++}
++
++static long hdmi_cec_set_address(u8 arg, struct hdmi_cec_priv *hdmi_cec);
++/*!
++ * @brief open function for cec file operation
++ *
++ * @return 0 on success or negative error code on error
++ */
++static int hdmi_cec_open(struct inode *inode, struct file *filp)
++{
++ struct hdmi_cec_priv *hdmi_cec = NULL;
++
++ mutex_lock(&hdmi_cec_root.m_lock_cl);
++ if (open_count == MAXCLIENTS || !hdmi_cec_ready) {
++ mutex_unlock(&hdmi_cec_root.m_lock_cl);
++ return -EBUSY;
++ }
++ open_count++;
++
++ hdmi_cec = kzalloc(sizeof(struct hdmi_cec_priv), GFP_KERNEL);
++ hdmi_cec->la = -1;
++ init_waitqueue_head(&(hdmi_cec->hdmi_cec_qm));
++ spin_lock_init(&(hdmi_cec->i_lock_cl));
++ INIT_LIST_HEAD(&hdmi_cec->msg_head);
++
++ filp->private_data = (void *)(hdmi_cec);
++
++ list_add_tail(&hdmi_cec->client_node, &hdmi_cec_root.client_head);
++ hdmi_cec_set_address(15, hdmi_cec);
++ mutex_unlock(&hdmi_cec_root.m_lock_cl);
++
++ return 0;
++}
++
++/*
++ * run delayed mxc_hdmi_cec_msg() to deal with msgs to LAs registered on local CEC.
++ * imx CEC is not transporting such messages through (local) interface
++ * (messages with destination the same as any regstered LA)
++ */
++static void mxc_hdmi_cec_msg_trigger(struct work_struct *work)
++{
++ mxc_hdmi_cec_msg(MESSAGE_TYPE_SEND_SUCCESS);
++}
++
++static ssize_t hdmi_cec_read(struct file *file, char __user *buf, size_t count,
++ loff_t *ppos)
++{
++ struct hdmi_cec_priv *hdmi_cec = file->private_data;
++ int ret = 0;
++
++ if (!open_count || hdmi_cec->la == 0xff)
++ return -ENODEV;
++
++ pr_debug("%s: client la %x, (addr %x)\n", __func__, hdmi_cec->la, (unsigned int)hdmi_cec);
++
++ count = min(count, sizeof(struct hdmi_cec_event));
++ do {
++ unsigned long flags;
++ struct hdmi_cec_event_list *event = NULL;
++
++ spin_lock_irqsave(&(hdmi_cec->i_lock_cl), flags);
++ if (!list_empty(&hdmi_cec->msg_head)) {
++ event = list_first_entry_or_null(&hdmi_cec->msg_head, struct hdmi_cec_event_list, msg_node);
++ list_del(&event->msg_node);
++ }
++ spin_unlock_irqrestore(&(hdmi_cec->i_lock_cl), flags);
++
++ if (event) {
++ ret = copy_to_user(buf, &event->data, count) ? -EFAULT : count;
++ kfree(event);
++ }
++ else if (file->f_flags & O_NONBLOCK) {
++ ret = -EAGAIN;
++ }
++ else if (wait_event_interruptible(hdmi_cec->hdmi_cec_qm, (!list_empty(&hdmi_cec->msg_head)))) {
++ ret = -ERESTARTSYS;
++ }
++ } while(!ret);
++
++ pr_debug("%s: exit %d\n", __func__, ret);
++ return ret;
++}
++
++static ssize_t hdmi_cec_write(struct file *file, const char __user *buf,
++ size_t count, loff_t *ppos)
++{
++ struct hdmi_cec_priv *hdmi_cec = file->private_data;
++ int ret = 0 , i = 0;
++ u8 msg[MAX_MESSAGE_LEN];
++ u8 val = 0;
++ int timeout = 1500;
++
++ if (!open_count || hdmi_cec->la == 0xff)
++ return -ENODEV;
++
++ if (count > MAX_MESSAGE_LEN)
++ return -E2BIG;
++
++ memset(&msg, 0, MAX_MESSAGE_LEN);
++ if (copy_from_user(&msg, buf, count))
++ return -EFAULT;
++
++ if (file->f_flags & O_NONBLOCK && hdmi_cec_root.write_busy)
++ return -EAGAIN;
++ else if (wait_event_interruptible(hdmi_cec_qw, (!hdmi_cec_root.write_busy)))
++ return -ERESTARTSYS;
++
++ mutex_lock(&hdmi_cec_root.m_lock_cl);
++ pr_debug("%s: \n", __func__);
++ hdmi_cec_root.write_busy = true;
++
++ hdmi_writeb(count, HDMI_CEC_TX_CNT);
++ for (i = 0; i < count; i++)
++ hdmi_writeb(msg[i], HDMI_CEC_TX_DATA0+i);
++
++ hdmi_cec->libcec_la = hdmi_cec->la;
++ if (la_is_local(msg[0] & 0x0f)) {
++ ret = count;
++ schedule_delayed_work(&(hdmi_cec_root.hdmi_msg_trigger), msecs_to_jiffies(20));
++ pr_debug("%s: wait_event la_is_local\n", __func__);
++ } else
++
++ do {
++ val = hdmi_readb(HDMI_CEC_CTRL) | 0x01;
++ val |= hdmi_cec_root.send_error ? SIGNAL_FREE_TIME_RESEND : SIGNAL_FREE_TIME_NORMAL;
++ hdmi_writeb(val, HDMI_CEC_CTRL);
++
++ ret = wait_event_timeout(hdmi_cec_qs, !((val = hdmi_readb(HDMI_CEC_CTRL)) & 0x01), msecs_to_jiffies(timeout));
++ pr_debug("%s: wait_event ret %d\n", __func__, ret);
++ if (hdmi_cec_root.send_error > 5 || ret < 2) {
++ hdmi_writeb(0, HDMI_CEC_TX_CNT);
++ hdmi_cec_root.write_busy = false;
++ wake_up(&hdmi_cec_qw);
++ ret = -EIO;
++ } else if (hdmi_cec_root.send_error && ret > 1) {
++ pr_debug("%s: --- resending msg\n", __func__);
++ timeout = jiffies_to_msecs(ret);
++ ret = 0;
++ } else if (ret > 1) {
++ ret = count;
++ }
++ } while(!ret);
++
++ mutex_unlock(&hdmi_cec_root.m_lock_cl);
++ return ret;
++}
++
++static void hdmi_cec_hwenable(void)
++{
++ u8 val;
++
++ pr_debug("%s: \n", __func__);
++ hdmi_cec_state = true;
++
++ val = hdmi_readb(HDMI_MC_CLKDIS);
++ val &= ~HDMI_MC_CLKDIS_CECCLK_DISABLE;
++ hdmi_writeb(val, HDMI_MC_CLKDIS);
++
++ val = HDMI_IH_CEC_STAT0_ERROR_INIT | HDMI_IH_CEC_STAT0_NACK |
++ HDMI_IH_CEC_STAT0_EOM | HDMI_IH_CEC_STAT0_DONE;
++ hdmi_writeb(val, HDMI_CEC_POLARITY);
++
++ val = HDMI_IH_CEC_STAT0_WAKEUP | HDMI_IH_CEC_STAT0_ERROR_FOLL |
++ HDMI_IH_CEC_STAT0_ARB_LOST;
++ hdmi_writeb(val, HDMI_CEC_MASK);
++ hdmi_writeb(val, HDMI_IH_MUTE_CEC_STAT0);
++ hdmi_writeb(0x0, HDMI_CEC_LOCK);
++ hdmi_writeb(0x02, HDMI_CEC_CTRL);
++}
++
++static void hdmi_cec_hwdisable(void)
++{
++ u8 val;
++
++ pr_debug("%s: \n", __func__);
++ hdmi_cec_state = false;
++
++ hdmi_writeb(0x10, HDMI_CEC_CTRL);
++
++ val = HDMI_IH_CEC_STAT0_WAKEUP | HDMI_IH_CEC_STAT0_ERROR_FOLL |
++ HDMI_IH_CEC_STAT0_ERROR_INIT | HDMI_IH_CEC_STAT0_ARB_LOST |
++ HDMI_IH_CEC_STAT0_NACK | HDMI_IH_CEC_STAT0_EOM |
++ HDMI_IH_CEC_STAT0_DONE;
++ hdmi_writeb(val, HDMI_CEC_MASK);
++ hdmi_writeb(val, HDMI_IH_MUTE_CEC_STAT0);
++
++ hdmi_writeb(0x0, HDMI_CEC_POLARITY);
++
++ val = hdmi_readb(HDMI_MC_CLKDIS);
++ val |= HDMI_MC_CLKDIS_CECCLK_DISABLE;
++ hdmi_writeb(val, HDMI_MC_CLKDIS);
++}
++
++static long hdmi_cec_set_address(u8 arg, struct hdmi_cec_priv *hdmi_cec)
++{
++
++ if (hdmi_cec->la == arg)
++ return 0;
++
++ pr_debug("%s: to %d\n", __func__, arg);
++
++ if (arg == 15)
++ hdmi_cec_root.nr_ff++;
++ if (hdmi_cec->la == 15)
++ hdmi_cec_root.nr_ff--;
++ else
++ hdmi_cec_root.addresses &= ~BIT(hdmi_cec->la);
++
++ hdmi_cec->la = arg;
++ if ((u8)arg != 0xff)
++ hdmi_cec_root.addresses |= BIT(arg);
++ else
++ wake_up(&hdmi_cec->hdmi_cec_qm);
++
++ if (!hdmi_cec_root.nr_ff)
++ hdmi_cec_root.addresses &= ~BIT(15);
++
++ hdmi_writeb(hdmi_cec_root.addresses & 0xff, HDMI_CEC_ADDR_L);
++ /*
++ * Don't register LA = 15 to with hardware. with it set, broadcast messages are never
++ * sent (considered local by CEC controler)
++ */
++ hdmi_writeb((hdmi_cec_root.addresses & 0x7f00) >> 8, HDMI_CEC_ADDR_H);
++ return 0;
++}
++
++/*!
++ * @brief IO ctrl function for vpu file operation
++ * @param cmd IO ctrl command
++ * @return 0 on success or negative error code on error
++ */
++static long hdmi_cec_ioctl(struct file *filp, u_int cmd,
++ u_long arg)
++{
++ int ret = 0, i;
++ struct hdmi_cec_priv *hdmi_cec = filp->private_data;
++
++ pr_debug("%s: \n", __func__);
++
++ if (!open_count)
++ return -ENODEV;
++
++ switch (cmd) {
++ case HDMICEC_IOC_SETLOGICALADDRESS:
++ mutex_lock(&hdmi_cec_root.m_lock_cl);
++ ret = hdmi_cec_set_address(arg, hdmi_cec);
++ mutex_unlock(&hdmi_cec_root.m_lock_cl);
++ /*
++ * in case we have more clients, inform them about PA change.
++ * (if libCEC is not in monitoring mode, it won't allow more
++ * clients with same PA - it changes all previous holders of
++ * that 'taken' PA to 1000.
++ * to avoid that, we expand PA further by replacing first empty
++ * dimension with LA (for instance if our PA is 2.2.0.0, we
++ * change to 2.2.X.0 all concurent clients, where X is actual LA
++ */
++ if (open_count > 1 && arg != 15)
++ mxc_hdmi_cec_handle(hdmi_cec_root.physical_address);
++ break;
++
++ case HDMICEC_IOC_STARTDEVICE:
++ if (!hdmi_cec_state)
++ hdmi_cec_hwenable();
++ break;
++
++ case HDMICEC_IOC_STOPDEVICE:
++ hdmi_cec_set_address(-1, hdmi_cec);
++ if (hdmi_cec_state && open_count < 2)
++ hdmi_cec_hwdisable();
++ break;
++
++ case HDMICEC_IOC_GETPHYADDRESS:
++ ret = copy_to_user((void __user *)arg, &hdmi_cec_root.physical_address,
++ 4*sizeof(u8))?-EFAULT:0;
++ if (open_count > 1) {
++ for (i = 0; i < 4 && ((u8*)arg)[i] != 0x0; i++);
++ ((u8*)arg)[i] = hdmi_cec->la;
++ }
++ break;
++
++ default:
++ ret = -EINVAL;
++ break;
++ }
++
++ return ret;
++}
++
++void hdmi_cec_start_device(void)
++{
++ if(open_count && hdmi_cec_ready && !hdmi_cec_state)
++ hdmi_cec_hwenable();
++}
++EXPORT_SYMBOL(hdmi_cec_start_device);
++
++void hdmi_cec_stop_device(void)
++{
++ if(hdmi_cec_ready && hdmi_cec_state)
++ hdmi_cec_hwdisable();
++}
++EXPORT_SYMBOL(hdmi_cec_stop_device);
++
++/*!
++* @brief Release function for vpu file operation
++* @return 0 on success or negative error code on error
++*/
++static int hdmi_cec_release(struct inode *inode, struct file *filp)
++{
++ struct hdmi_cec_priv *hdmi_cec = filp->private_data;
++ struct hdmi_cec_priv *client, *t;
++ unsigned long flags;
++
++ pr_debug("%s: \n", __func__);
++
++ mutex_lock(&hdmi_cec_root.m_lock_cl);
++ spin_lock_irqsave(&hdmi_cec->i_lock_cl, flags);
++
++ hdmi_cec_set_address(-1, hdmi_cec);
++ if (open_count > 0)
++ open_count--;
++ if (!open_count)
++ hdmi_cec_hwdisable();
++ while (!list_empty(&hdmi_cec->msg_head)) {
++ struct hdmi_cec_event_list *event = NULL;
++
++ event = list_first_entry(&hdmi_cec->msg_head, struct hdmi_cec_event_list, msg_node);
++ list_del(&event->msg_node);
++ kfree(event);
++ }
++
++ spin_unlock_irqrestore(&hdmi_cec->i_lock_cl, flags);
++
++ list_for_each_entry_safe(client, t, &hdmi_cec_root.client_head, client_node) {
++ if (client == hdmi_cec) {
++ list_del(&client->client_node);
++ filp->private_data = NULL;
++ kfree(client);
++ }
++ }
++
++ mutex_unlock(&hdmi_cec_root.m_lock_cl);
++ return 0;
++}
++
++static unsigned int hdmi_cec_poll(struct file *file, poll_table *wait)
++{
++ unsigned int mask = 0;
++ struct hdmi_cec_priv *hdmi_cec = file->private_data;
++
++ pr_debug("%s: poll client %lx, la %d\n", __func__, (unsigned long)hdmi_cec, hdmi_cec->la);
++
++ if (hdmi_cec->la == 0xff)
++ return POLLHUP;
++
++ poll_wait(file, &hdmi_cec->hdmi_cec_qm, wait);
++ poll_wait(file, &hdmi_cec_qw, wait);
++
++ if (!hdmi_cec_root.write_busy)
++ mask = (POLLOUT | POLLWRNORM);
++ if (!list_empty(&hdmi_cec->msg_head))
++ mask |= (POLLIN | POLLRDNORM);
++
++ return mask;
++}
++
++const struct file_operations hdmi_cec_fops = {
++ .owner = THIS_MODULE,
++ .read = hdmi_cec_read,
++ .write = hdmi_cec_write,
++ .open = hdmi_cec_open,
++ .unlocked_ioctl = hdmi_cec_ioctl,
++ .release = hdmi_cec_release,
++ .poll = hdmi_cec_poll,
++};
++
++static int hdmi_cec_dev_probe(struct platform_device *pdev)
++{
++ int err = 0;
++ struct device *temp_class;
++ struct resource *res;
++ struct pinctrl *pinctrl;
++ int irq = platform_get_irq(pdev, 0);
++
++ hdmi_cec_major = register_chrdev(hdmi_cec_major, "mxc_hdmi_cec", &hdmi_cec_fops);
++ if (hdmi_cec_major < 0) {
++ dev_err(&pdev->dev, "%s: unable to get a major for HDMI CEC\n", __func__);
++ err = -EBUSY;
++ goto out;
++ }
++
++ res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
++ if (unlikely(res == NULL)) {
++ dev_err(&pdev->dev, "%s: No HDMI irq line provided\n", __func__);
++ goto err_out_chrdev;
++ }
++ spin_lock_init(&hdmi_cec_root.i_lock);
++
++ err = devm_request_irq(&pdev->dev, irq, mxc_hdmi_cec_isr, IRQF_SHARED,
++ dev_name(&pdev->dev), &hdmi_cec_root);
++ if (err < 0) {
++ dev_err(&pdev->dev, "%s: Unable to request irq: %d\n", __func__, err);
++ goto err_out_chrdev;
++ }
++
++ hdmi_cec_class = class_create(THIS_MODULE, "mxc_hdmi_cec");
++ if (IS_ERR(hdmi_cec_class)) {
++ err = PTR_ERR(hdmi_cec_class);
++ goto err_out_chrdev;
++ }
++
++ temp_class = device_create(hdmi_cec_class, NULL,
++ MKDEV(hdmi_cec_major, 0), NULL, "mxc_hdmi_cec");
++ if (IS_ERR(temp_class)) {
++ err = PTR_ERR(temp_class);
++ goto err_out_class;
++ }
++
++ pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
++ if (IS_ERR(pinctrl)) {
++ dev_err(&pdev->dev, "%s: can't get/select CEC pinctrl\n", __func__);
++ goto err_out_class;
++ }
++
++ init_waitqueue_head(&hdmi_cec_qs);
++ init_waitqueue_head(&hdmi_cec_qw);
++
++ INIT_LIST_HEAD(&hdmi_cec_root.client_head);
++
++ mutex_init(&hdmi_cec_root.m_lock_cl);
++ hdmi_cec_root.addresses = 0;
++ platform_set_drvdata(pdev, &hdmi_cec_root);
++ INIT_DELAYED_WORK(&hdmi_cec_root.hdmi_cec_work, mxc_hdmi_cec_worker);
++ INIT_DELAYED_WORK(&hdmi_cec_root.hdmi_msg_trigger, mxc_hdmi_cec_msg_trigger);
++
++ dev_info(&pdev->dev, "%s: HDMI CEC initialized\n", __func__);
++ hdmi_cec_ready = 1;
++ goto out;
++
++err_out_class:
++ device_destroy(hdmi_cec_class, MKDEV(hdmi_cec_major, 0));
++ class_destroy(hdmi_cec_class);
++err_out_chrdev:
++ unregister_chrdev(hdmi_cec_major, "mxc_hdmi_cec");
++out:
++ return err;
++}
++
++static int hdmi_cec_dev_remove(struct platform_device *pdev)
++{
++ if (hdmi_cec_major > 0) {
++ flush_scheduled_work();
++ device_destroy(hdmi_cec_class, MKDEV(hdmi_cec_major, 0));
++ class_destroy(hdmi_cec_class);
++ unregister_chrdev(hdmi_cec_major, "mxc_hdmi_cec");
++ hdmi_cec_major = 0;
++ }
++ return 0;
++}
++
++static const struct of_device_id imx_hdmi_cec_match[] = {
++ { .compatible = "fsl,imx6q-hdmi-cec", },
++ { .compatible = "fsl,imx6dl-hdmi-cec", },
++ { /* sentinel */ }
++};
++
++static struct platform_driver mxc_hdmi_cec_driver = {
++ .probe = hdmi_cec_dev_probe,
++ .remove = hdmi_cec_dev_remove,
++ .driver = {
++ .name = "mxc_hdmi_cec",
++ .of_match_table = imx_hdmi_cec_match,
++ },
++};
++
++module_platform_driver(mxc_hdmi_cec_driver);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("Linux HDMI CEC driver for Freescale i.MX/MXC");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:mxc_hdmi_cec");
++
+diff -Nur linux-4.1.3/drivers/mxc/hdmi-cec/mxc_hdmi-cec.h linux-xbian-imx6/drivers/mxc/hdmi-cec/mxc_hdmi-cec.h
+--- linux-4.1.3/drivers/mxc/hdmi-cec/mxc_hdmi-cec.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/hdmi-cec/mxc_hdmi-cec.h 2015-07-27 23:13:06.226765901 +0200
+@@ -0,0 +1,53 @@
++/*
++ * Copyright 2005-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++#ifndef _HDMICEC_H_
++#define _HDMICEC_H_
++#include <linux/ioctl.h>
++
++/*
++ * Ioctl definitions
++ */
++
++/* Use 'k' as magic number */
++#define HDMICEC_IOC_MAGIC 'H'
++/*
++ * S means "Set" through a ptr,
++ * T means "Tell" directly with the argument value
++ * G means "Get": reply by setting through a pointer
++ * Q means "Query": response is on the return value
++ * X means "eXchange": G and S atomically
++ * H means "sHift": T and Q atomically
++ */
++#define HDMICEC_IOC_SETLOGICALADDRESS \
++ _IOW(HDMICEC_IOC_MAGIC, 1, unsigned char)
++#define HDMICEC_IOC_STARTDEVICE _IO(HDMICEC_IOC_MAGIC, 2)
++#define HDMICEC_IOC_STOPDEVICE _IO(HDMICEC_IOC_MAGIC, 3)
++#define HDMICEC_IOC_GETPHYADDRESS \
++ _IOR(HDMICEC_IOC_MAGIC, 4, unsigned char[4])
++#define HDMICEC_IOC_LOG \
++ _IOW(HDMICEC_IOC_MAGIC, 5, unsigned char[255])
++
++#define MAX_MESSAGE_LEN 16
++
++#define MESSAGE_TYPE_RECEIVE_SUCCESS 1
++#define MESSAGE_TYPE_NOACK 2
++#define MESSAGE_TYPE_DISCONNECTED 3
++#define MESSAGE_TYPE_CONNECTED 4
++#define MESSAGE_TYPE_SEND_SUCCESS 5
++
++#define SIGNAL_FREE_LOST BIT(2)
++#define SIGNAL_FREE_TIME_NORMAL BIT(1)
++#define SIGNAL_FREE_TIME_RESEND 0
++
++#endif /* !_HDMICEC_H_ */
++
+diff -Nur linux-4.1.3/drivers/mxc/ipu3/ipu_calc_stripes_sizes.c linux-xbian-imx6/drivers/mxc/ipu3/ipu_calc_stripes_sizes.c
+--- linux-4.1.3/drivers/mxc/ipu3/ipu_calc_stripes_sizes.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/ipu3/ipu_calc_stripes_sizes.c 2015-07-27 23:13:06.226765901 +0200
+@@ -0,0 +1,495 @@
++/*
++ * Copyright 2009-2014 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*
++ * @file ipu_calc_stripes_sizes.c
++ *
++ * @brief IPU IC functions
++ *
++ * @ingroup IPU
++ */
++
++#include <linux/ipu-v3.h>
++#include <linux/module.h>
++#include <linux/math64.h>
++
++#define BPP_32 0
++#define BPP_16 3
++#define BPP_8 5
++#define BPP_24 1
++#define BPP_12 4
++#define BPP_18 2
++
++static u32 truncate(u32 up, /* 0: down; else: up */
++ u64 a, /* must be non-negative */
++ u32 b)
++{
++ u32 d;
++ u64 div;
++ div = div_u64(a, b);
++ d = b * (div >> 32);
++ if (up && (a > (((u64)d) << 32)))
++ return d+b;
++ else
++ return d;
++}
++
++static unsigned int f_calc(unsigned int pfs, unsigned int bpp, unsigned int *write)
++{/* return input_f */
++ unsigned int f_calculated = 0;
++ switch (pfs) {
++ case IPU_PIX_FMT_YVU422P:
++ case IPU_PIX_FMT_YUV422P:
++ case IPU_PIX_FMT_YUV420P2:
++ case IPU_PIX_FMT_YUV420P:
++ case IPU_PIX_FMT_YVU420P:
++ case IPU_PIX_FMT_YUV444P:
++ f_calculated = 16;
++ break;
++
++ case IPU_PIX_FMT_RGB565:
++ case IPU_PIX_FMT_YUYV:
++ case IPU_PIX_FMT_UYVY:
++ f_calculated = 8;
++ break;
++
++ case IPU_PIX_FMT_NV12:
++ f_calculated = 8;
++ break;
++
++ default:
++ f_calculated = 0;
++ break;
++
++ }
++ if (!f_calculated) {
++ switch (bpp) {
++ case BPP_32:
++ f_calculated = 2;
++ break;
++
++ case BPP_16:
++ f_calculated = 4;
++ break;
++
++ case BPP_8:
++ case BPP_24:
++ f_calculated = 8;
++ break;
++
++ case BPP_12:
++ f_calculated = 16;
++ break;
++
++ case BPP_18:
++ f_calculated = 32;
++ break;
++
++ default:
++ f_calculated = 0;
++ break;
++ }
++ }
++ return f_calculated;
++}
++
++
++static unsigned int m_calc(unsigned int pfs)
++{
++ unsigned int m_calculated = 0;
++ switch (pfs) {
++ case IPU_PIX_FMT_YUV420P2:
++ case IPU_PIX_FMT_YUV420P:
++ case IPU_PIX_FMT_YVU422P:
++ case IPU_PIX_FMT_YUV422P:
++ case IPU_PIX_FMT_YVU420P:
++ case IPU_PIX_FMT_YUV444P:
++ m_calculated = 16;
++ break;
++
++ case IPU_PIX_FMT_NV12:
++ case IPU_PIX_FMT_YUYV:
++ case IPU_PIX_FMT_UYVY:
++ m_calculated = 8;
++ break;
++
++ default:
++ m_calculated = 8;
++ break;
++
++ }
++ return m_calculated;
++}
++
++static int calc_split_resize_coeffs(unsigned int inSize, unsigned int outSize,
++ unsigned int *resizeCoeff,
++ unsigned int *downsizeCoeff)
++{
++ uint32_t tempSize;
++ uint32_t tempDownsize;
++
++ if (inSize > 4096) {
++ pr_debug("IC input size(%d) cannot exceed 4096\n",
++ inSize);
++ return -EINVAL;
++ }
++
++ if (outSize > 1024) {
++ pr_debug("IC output size(%d) cannot exceed 1024\n",
++ outSize);
++ return -EINVAL;
++ }
++
++ if ((outSize << 3) < inSize) {
++ pr_debug("IC cannot downsize more than 8:1\n");
++ return -EINVAL;
++ }
++
++ /* Compute downsizing coefficient */
++ /* Output of downsizing unit cannot be more than 1024 */
++ tempDownsize = 0;
++ tempSize = inSize;
++ while (((tempSize > 1024) || (tempSize >= outSize * 2)) &&
++ (tempDownsize < 2)) {
++ tempSize >>= 1;
++ tempDownsize++;
++ }
++ *downsizeCoeff = tempDownsize;
++
++ /* compute resizing coefficient using the following equation:
++ resizeCoeff = M*(SI -1)/(SO - 1)
++ where M = 2^13, SI - input size, SO - output size */
++ *resizeCoeff = (8192L * (tempSize - 1)) / (outSize - 1);
++ if (*resizeCoeff >= 16384L) {
++ pr_debug("Overflow on IC resize coefficient.\n");
++ return -EINVAL;
++ }
++
++ pr_debug("resizing from %u -> %u pixels, "
++ "downsize=%u, resize=%u.%lu (reg=%u)\n", inSize, outSize,
++ *downsizeCoeff, (*resizeCoeff >= 8192L) ? 1 : 0,
++ ((*resizeCoeff & 0x1FFF) * 10000L) / 8192L, *resizeCoeff);
++
++ return 0;
++}
++
++/* Stripe parameters calculator */
++/**************************************************************************
++Notes:
++MSW = the maximal width allowed for a stripe
++ i.MX31: 720, i.MX35: 800, i.MX37/51/53: 1024
++cirr = the maximal inverse resizing ratio for which overlap in the input
++ is requested; typically cirr~2
++flags
++ bit 0 - equal_stripes
++ 0 each stripe is allowed to have independent parameters
++ for maximal image quality
++ 1 the stripes are requested to have identical parameters
++ (except the base address), for maximal performance
++ bit 1 - vertical/horizontal
++ 0 horizontal
++ 1 vertical
++
++If performance is the top priority (above image quality)
++ Avoid overlap, by setting CIRR = 0
++ This will also force effectively identical_stripes = 1
++ Choose IF & OF that corresponds to the same IOX/SX for both stripes
++ Choose IFW & OFW such that
++ IFW/IM, IFW/IF, OFW/OM, OFW/OF are even integers
++ The function returns an error status:
++ 0: no error
++ 1: invalid input parameters -> aborted without result
++ Valid parameters should satisfy the following conditions
++ IFW <= OFW, otherwise downsizing is required
++ - which is not supported yet
++ 4 <= IFW,OFW, so some interpolation may be needed even without overlap
++ IM, OM, IF, OF should not vanish
++ 2*IF <= IFW
++ so the frame can be split to two equal stripes, even without overlap
++ 2*(OF+IF/irr_opt) <= OFW
++ so a valid positive INW exists even for equal stripes
++ OF <= MSW, otherwise, the left stripe cannot be sufficiently large
++ MSW < OFW, so splitting to stripes is required
++ OFW <= 2*MSW, so two stripes are sufficient
++ (this also implies that 2<=MSW)
++ 2: OF is not a multiple of OM - not fully-supported yet
++ Output is produced but OW is not guaranited to be a multiple of OM
++ 4: OFW reduced to be a multiple of OM
++ 8: CIRR > 1: truncated to 1
++ Overlap is not supported (and not needed) y for upsizing)
++**************************************************************************/
++int ipu_calc_stripes_sizes(const unsigned int input_frame_width,
++ /* input frame width;>1 */
++ unsigned int output_frame_width, /* output frame width; >1 */
++ const unsigned int maximal_stripe_width,
++ /* the maximal width allowed for a stripe */
++ const unsigned long long cirr, /* see above */
++ const unsigned int flags, /* see above */
++ u32 input_pixelformat,/* pixel format after of read channel*/
++ u32 output_pixelformat,/* pixel format after of write channel*/
++ struct stripe_param *left,
++ struct stripe_param *right)
++{
++ const unsigned int irr_frac_bits = 13;
++ const unsigned long irr_steps = 1 << irr_frac_bits;
++ const u64 dirr = ((u64)1) << (32 - 2);
++ /* The maximum relative difference allowed between the irrs */
++ const u64 cr = ((u64)4) << 32;
++ /* The importance ratio between the two terms in the cost function below */
++
++ unsigned int status;
++ unsigned int temp;
++ unsigned int onw_min;
++ unsigned int inw = 0, onw = 0, inw_best = 0;
++ /* number of pixels in the left stripe NOT hidden by the right stripe */
++ u64 irr_opt; /* the optimal inverse resizing ratio */
++ u64 rr_opt; /* the optimal resizing ratio = 1/irr_opt*/
++ u64 dinw; /* the misalignment between the stripes */
++ /* (measured in units of input columns) */
++ u64 difwl, difwr = 0;
++ /* The number of input columns not reflected in the output */
++ /* the resizing ratio used for the right stripe is */
++ /* left->irr and right->irr respectively */
++ u64 cost, cost_min;
++ u64 div; /* result of division */
++ bool equal_stripes = (flags & 0x1) != 0;
++ bool vertical = (flags & 0x2) != 0;
++
++ unsigned int input_m, input_f, output_m, output_f; /* parameters for upsizing by stripes */
++ unsigned int resize_coeff;
++ unsigned int downsize_coeff;
++
++ status = 0;
++
++ if (vertical) {
++ input_f = 2;
++ input_m = 8;
++ output_f = 8;
++ output_m = 2;
++ } else {
++ input_f = f_calc(input_pixelformat, 0, NULL);
++ input_m = m_calc(input_pixelformat);
++ output_f = input_m;
++ output_m = m_calc(output_pixelformat);
++ }
++ if ((input_frame_width < 4) || (output_frame_width < 4))
++ return 1;
++
++ irr_opt = div_u64((((u64)(input_frame_width - 1)) << 32),
++ (output_frame_width - 1));
++ rr_opt = div_u64((((u64)(output_frame_width - 1)) << 32),
++ (input_frame_width - 1));
++
++ if ((input_m == 0) || (output_m == 0) || (input_f == 0) || (output_f == 0)
++ || (input_frame_width < (2 * input_f))
++ || ((((u64)output_frame_width) << 32) <
++ (2 * ((((u64)output_f) << 32) + (input_f * rr_opt))))
++ || (maximal_stripe_width < output_f)
++ || ((output_frame_width <= maximal_stripe_width)
++ && (equal_stripes == 0))
++ || ((2 * maximal_stripe_width) < output_frame_width))
++ return 1;
++
++ if (output_f % output_m)
++ status += 2;
++
++ temp = truncate(0, (((u64)output_frame_width) << 32), output_m);
++ if (temp < output_frame_width) {
++ output_frame_width = temp;
++ status += 4;
++ }
++
++ pr_debug("---------------->\n"
++ "if = %d\n"
++ "im = %d\n"
++ "of = %d\n"
++ "om = %d\n"
++ "irr_opt = %llu\n"
++ "rr_opt = %llu\n"
++ "cirr = %llu\n"
++ "pixel in = %08x\n"
++ "pixel out = %08x\n"
++ "ifw = %d\n"
++ "ofwidth = %d\n",
++ input_f,
++ input_m,
++ output_f,
++ output_m,
++ irr_opt,
++ rr_opt,
++ cirr,
++ input_pixelformat,
++ output_pixelformat,
++ input_frame_width,
++ output_frame_width
++ );
++
++ if (equal_stripes) {
++ if ((irr_opt > cirr) /* overlap in the input is not requested */
++ && ((input_frame_width % (input_m << 1)) == 0)
++ && ((input_frame_width % (input_f << 1)) == 0)
++ && ((output_frame_width % (output_m << 1)) == 0)
++ && ((output_frame_width % (output_f << 1)) == 0)) {
++ /* without overlap */
++ left->input_width = right->input_width = right->input_column =
++ input_frame_width >> 1;
++ left->output_width = right->output_width = right->output_column =
++ output_frame_width >> 1;
++ left->input_column = 0;
++ left->output_column = 0;
++ div = div_u64(((((u64)irr_steps) << 32) *
++ (right->input_width - 1)), (right->output_width - 1));
++ left->irr = right->irr = truncate(0, div, 1);
++ } else { /* with overlap */
++ onw = truncate(0, (((u64)output_frame_width - 1) << 32) >> 1,
++ output_f);
++ inw = truncate(0, onw * irr_opt, input_f);
++ /* this is the maximal inw which allows the same resizing ratio */
++ /* in both stripes */
++ onw = truncate(1, (inw * rr_opt), output_f);
++ div = div_u64((((u64)(irr_steps * inw)) <<
++ 32), onw);
++ left->irr = right->irr = truncate(0, div, 1);
++ left->output_width = right->output_width =
++ output_frame_width - onw;
++ /* These are valid assignments for output_width, */
++ /* assuming output_f is a multiple of output_m */
++ div = (((u64)(left->output_width-1) * (left->irr)) << 32);
++ div = (((u64)1) << 32) + div_u64(div, irr_steps);
++
++ left->input_width = right->input_width = truncate(1, div, input_m);
++
++ div = div_u64((((u64)((right->output_width - 1) * right->irr)) <<
++ 32), irr_steps);
++ difwr = (((u64)(input_frame_width - 1 - inw)) << 32) - div;
++ div = div_u64((difwr + (((u64)input_f) << 32)), 2);
++ left->input_column = truncate(0, div, input_f);
++
++
++ /* This splits the truncated input columns evenly */
++ /* between the left and right margins */
++ right->input_column = left->input_column + inw;
++ left->output_column = 0;
++ right->output_column = onw;
++ }
++ if (left->input_width > left->output_width) {
++ if (calc_split_resize_coeffs(left->input_width,
++ left->output_width,
++ &resize_coeff,
++ &downsize_coeff) < 0)
++ return -EINVAL;
++
++ if (downsize_coeff > 0) {
++ left->irr = right->irr =
++ (downsize_coeff << 14) | resize_coeff;
++ }
++ }
++ pr_debug("inw %d, onw %d, ilw %d, ilc %d, olw %d,"
++ " irw %d, irc %d, orw %d, orc %d, "
++ "difwr %llu, lirr %u\n",
++ inw, onw, left->input_width,
++ left->input_column, left->output_width,
++ right->input_width, right->input_column,
++ right->output_width,
++ right->output_column, difwr, left->irr);
++ } else { /* independent stripes */
++ onw_min = output_frame_width - maximal_stripe_width;
++ /* onw is a multiple of output_f, in the range */
++ /* [max(output_f,output_frame_width-maximal_stripe_width),*/
++ /*min(output_frame_width-2,maximal_stripe_width)] */
++ /* definitely beyond the cost of any valid setting */
++ cost_min = (((u64)input_frame_width) << 32) + cr;
++ onw = truncate(0, ((u64)maximal_stripe_width), output_f);
++ if (output_frame_width - onw == 1)
++ onw -= output_f; /* => onw and output_frame_width-1-onw are positive */
++ inw = truncate(0, onw * irr_opt, input_f);
++ /* this is the maximal inw which allows the same resizing ratio */
++ /* in both stripes */
++ onw = truncate(1, inw * rr_opt, output_f);
++ do {
++ div = div_u64((((u64)(irr_steps * inw)) << 32), onw);
++ left->irr = truncate(0, div, 1);
++ div = div_u64((((u64)(onw * left->irr)) << 32),
++ irr_steps);
++ dinw = (((u64)inw) << 32) - div;
++
++ div = div_u64((((u64)((output_frame_width - 1 - onw) * left->irr)) <<
++ 32), irr_steps);
++
++ difwl = (((u64)(input_frame_width - 1 - inw)) << 32) - div;
++
++ cost = difwl + (((u64)(cr * dinw)) >> 32);
++
++ if (cost < cost_min) {
++ inw_best = inw;
++ cost_min = cost;
++ }
++
++ inw -= input_f;
++ onw = truncate(1, inw * rr_opt, output_f);
++ /* This is the minimal onw which allows the same resizing ratio */
++ /* in both stripes */
++ } while (onw >= onw_min);
++
++ inw = inw_best;
++ onw = truncate(1, inw * rr_opt, output_f);
++ div = div_u64((((u64)(irr_steps * inw)) << 32), onw);
++ left->irr = truncate(0, div, 1);
++
++ left->output_width = onw;
++ right->output_width = output_frame_width - onw;
++ /* These are valid assignments for output_width, */
++ /* assuming output_f is a multiple of output_m */
++ left->input_width = truncate(1, ((u64)(inw + 1)) << 32, input_m);
++ right->input_width = truncate(1, ((u64)(input_frame_width - inw)) <<
++ 32, input_m);
++
++ div = div_u64((((u64)(irr_steps * (input_frame_width - 1 - inw))) <<
++ 32), (right->output_width - 1));
++ right->irr = truncate(0, div, 1);
++ temp = truncate(0, ((u64)left->irr) * ((((u64)1) << 32) + dirr), 1);
++ if (temp < right->irr)
++ right->irr = temp;
++ div = div_u64(((u64)((right->output_width - 1) * right->irr) <<
++ 32), irr_steps);
++ difwr = (u64)(input_frame_width - 1 - inw) - div;
++
++
++ div = div_u64((difwr + (((u64)input_f) << 32)), 2);
++ left->input_column = truncate(0, div, input_f);
++
++ /* This splits the truncated input columns evenly */
++ /* between the left and right margins */
++ right->input_column = left->input_column + inw;
++ left->output_column = 0;
++ right->output_column = onw;
++ if (left->input_width > left->output_width) {
++ if (calc_split_resize_coeffs(left->input_width,
++ left->output_width,
++ &resize_coeff,
++ &downsize_coeff) < 0)
++ return -EINVAL;
++ left->irr = (downsize_coeff << 14) | resize_coeff;
++ }
++ if (right->input_width > right->output_width) {
++ if (calc_split_resize_coeffs(right->input_width,
++ right->output_width,
++ &resize_coeff,
++ &downsize_coeff) < 0)
++ return -EINVAL;
++ right->irr = (downsize_coeff << 14) | resize_coeff;
++ }
++ }
++ return status;
++}
++EXPORT_SYMBOL(ipu_calc_stripes_sizes);
+diff -Nur linux-4.1.3/drivers/mxc/ipu3/ipu_capture.c linux-xbian-imx6/drivers/mxc/ipu3/ipu_capture.c
+--- linux-4.1.3/drivers/mxc/ipu3/ipu_capture.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/ipu3/ipu_capture.c 2015-07-27 23:13:06.226765901 +0200
+@@ -0,0 +1,816 @@
++/*
++ * Copyright 2008-2014 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*!
++ * @file ipu_capture.c
++ *
++ * @brief IPU capture dase functions
++ *
++ * @ingroup IPU
++ */
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/errno.h>
++#include <linux/init.h>
++#include <linux/io.h>
++#include <linux/ipu-v3.h>
++#include <linux/module.h>
++#include <linux/spinlock.h>
++#include <linux/types.h>
++
++#include "ipu_prv.h"
++#include "ipu_regs.h"
++
++/*!
++ * _ipu_csi_mclk_set
++ *
++ * @param ipu ipu handler
++ * @param pixel_clk desired pixel clock frequency in Hz
++ * @param csi csi 0 or csi 1
++ *
++ * @return Returns 0 on success or negative error code on fail
++ */
++int _ipu_csi_mclk_set(struct ipu_soc *ipu, uint32_t pixel_clk, uint32_t csi)
++{
++ uint32_t temp;
++ uint32_t div_ratio;
++
++ div_ratio = (clk_get_rate(ipu->ipu_clk) / pixel_clk) - 1;
++
++ if (div_ratio > 0xFF || div_ratio < 0) {
++ dev_dbg(ipu->dev, "value of pixel_clk extends normal range\n");
++ return -EINVAL;
++ }
++
++ temp = ipu_csi_read(ipu, csi, CSI_SENS_CONF);
++ temp &= ~CSI_SENS_CONF_DIVRATIO_MASK;
++ ipu_csi_write(ipu, csi, temp |
++ (div_ratio << CSI_SENS_CONF_DIVRATIO_SHIFT),
++ CSI_SENS_CONF);
++
++ return 0;
++}
++
++/*!
++ * ipu_csi_init_interface
++ * Sets initial values for the CSI registers.
++ * The width and height of the sensor and the actual frame size will be
++ * set to the same values.
++ * @param ipu ipu handler
++ * @param width Sensor width
++ * @param height Sensor height
++ * @param pixel_fmt pixel format
++ * @param cfg_param ipu_csi_signal_cfg_t structure
++ * @param csi csi 0 or csi 1
++ *
++ * @return 0 for success, -EINVAL for error
++ */
++int32_t
++ipu_csi_init_interface(struct ipu_soc *ipu, uint16_t width, uint16_t height,
++ uint32_t pixel_fmt, ipu_csi_signal_cfg_t cfg_param)
++{
++ uint32_t data = 0;
++ uint32_t csi = cfg_param.csi;
++
++ /* Set SENS_DATA_FORMAT bits (8, 9 and 10)
++ RGB or YUV444 is 0 which is current value in data so not set
++ explicitly
++ This is also the default value if attempts are made to set it to
++ something invalid. */
++ switch (pixel_fmt) {
++ case IPU_PIX_FMT_YUYV:
++ cfg_param.data_fmt = CSI_SENS_CONF_DATA_FMT_YUV422_YUYV;
++ break;
++ case IPU_PIX_FMT_UYVY:
++ cfg_param.data_fmt = CSI_SENS_CONF_DATA_FMT_YUV422_UYVY;
++ break;
++ case IPU_PIX_FMT_RGB24:
++ case IPU_PIX_FMT_BGR24:
++ cfg_param.data_fmt = CSI_SENS_CONF_DATA_FMT_RGB_YUV444;
++ break;
++ case IPU_PIX_FMT_GENERIC:
++ case IPU_PIX_FMT_GENERIC_16:
++ cfg_param.data_fmt = CSI_SENS_CONF_DATA_FMT_BAYER;
++ break;
++ case IPU_PIX_FMT_RGB565:
++ cfg_param.data_fmt = CSI_SENS_CONF_DATA_FMT_RGB565;
++ break;
++ case IPU_PIX_FMT_RGB555:
++ cfg_param.data_fmt = CSI_SENS_CONF_DATA_FMT_RGB555;
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ /* Set the CSI_SENS_CONF register remaining fields */
++ data |= cfg_param.data_width << CSI_SENS_CONF_DATA_WIDTH_SHIFT |
++ cfg_param.data_fmt << CSI_SENS_CONF_DATA_FMT_SHIFT |
++ cfg_param.data_pol << CSI_SENS_CONF_DATA_POL_SHIFT |
++ cfg_param.Vsync_pol << CSI_SENS_CONF_VSYNC_POL_SHIFT |
++ cfg_param.Hsync_pol << CSI_SENS_CONF_HSYNC_POL_SHIFT |
++ cfg_param.pixclk_pol << CSI_SENS_CONF_PIX_CLK_POL_SHIFT |
++ cfg_param.ext_vsync << CSI_SENS_CONF_EXT_VSYNC_SHIFT |
++ cfg_param.clk_mode << CSI_SENS_CONF_SENS_PRTCL_SHIFT |
++ cfg_param.pack_tight << CSI_SENS_CONF_PACK_TIGHT_SHIFT |
++ cfg_param.force_eof << CSI_SENS_CONF_FORCE_EOF_SHIFT |
++ cfg_param.data_en_pol << CSI_SENS_CONF_DATA_EN_POL_SHIFT;
++
++ _ipu_get(ipu);
++
++ mutex_lock(&ipu->mutex_lock);
++
++ ipu_csi_write(ipu, csi, data, CSI_SENS_CONF);
++
++ /* Setup sensor frame size */
++ ipu_csi_write(ipu, csi, (width - 1) | (height - 1) << 16, CSI_SENS_FRM_SIZE);
++
++ /* Set CCIR registers */
++ if (cfg_param.clk_mode == IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE) {
++ ipu_csi_write(ipu, csi, 0x40030, CSI_CCIR_CODE_1);
++ ipu_csi_write(ipu, csi, 0xFF0000, CSI_CCIR_CODE_3);
++ } else if (cfg_param.clk_mode == IPU_CSI_CLK_MODE_CCIR656_INTERLACED) {
++ if (width == 720 && height == 625) {
++ /* PAL case */
++ /*
++ * Field0BlankEnd = 0x6, Field0BlankStart = 0x2,
++ * Field0ActiveEnd = 0x4, Field0ActiveStart = 0
++ */
++ ipu_csi_write(ipu, csi, 0x40596, CSI_CCIR_CODE_1);
++ /*
++ * Field1BlankEnd = 0x7, Field1BlankStart = 0x3,
++ * Field1ActiveEnd = 0x5, Field1ActiveStart = 0x1
++ */
++ ipu_csi_write(ipu, csi, 0xD07DF, CSI_CCIR_CODE_2);
++
++ ipu_csi_write(ipu, csi, 0xFF0000, CSI_CCIR_CODE_3);
++
++ } else if (width == 720 && height == 525) {
++ /* NTSC case */
++ /*
++ * Field0BlankEnd = 0x7, Field0BlankStart = 0x3,
++ * Field0ActiveEnd = 0x5, Field0ActiveStart = 0x1
++ */
++ ipu_csi_write(ipu, csi, 0xD07DF, CSI_CCIR_CODE_1);
++ /*
++ * Field1BlankEnd = 0x6, Field1BlankStart = 0x2,
++ * Field1ActiveEnd = 0x4, Field1ActiveStart = 0
++ */
++ ipu_csi_write(ipu, csi, 0x40596, CSI_CCIR_CODE_2);
++ ipu_csi_write(ipu, csi, 0xFF0000, CSI_CCIR_CODE_3);
++ } else {
++ dev_err(ipu->dev, "Unsupported CCIR656 interlaced "
++ "video mode\n");
++ mutex_unlock(&ipu->mutex_lock);
++ _ipu_put(ipu);
++ return -EINVAL;
++ }
++ _ipu_csi_ccir_err_detection_enable(ipu, csi);
++ } else if ((cfg_param.clk_mode ==
++ IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_DDR) ||
++ (cfg_param.clk_mode ==
++ IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR) ||
++ (cfg_param.clk_mode ==
++ IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_DDR) ||
++ (cfg_param.clk_mode ==
++ IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR)) {
++ ipu_csi_write(ipu, csi, 0x40030, CSI_CCIR_CODE_1);
++ ipu_csi_write(ipu, csi, 0xFF0000, CSI_CCIR_CODE_3);
++ _ipu_csi_ccir_err_detection_enable(ipu, csi);
++ } else if ((cfg_param.clk_mode == IPU_CSI_CLK_MODE_GATED_CLK) ||
++ (cfg_param.clk_mode == IPU_CSI_CLK_MODE_NONGATED_CLK)) {
++ _ipu_csi_ccir_err_detection_disable(ipu, csi);
++ }
++
++ dev_dbg(ipu->dev, "CSI_SENS_CONF = 0x%08X\n",
++ ipu_csi_read(ipu, csi, CSI_SENS_CONF));
++ dev_dbg(ipu->dev, "CSI_ACT_FRM_SIZE = 0x%08X\n",
++ ipu_csi_read(ipu, csi, CSI_ACT_FRM_SIZE));
++
++ mutex_unlock(&ipu->mutex_lock);
++
++ _ipu_put(ipu);
++
++ return 0;
++}
++EXPORT_SYMBOL(ipu_csi_init_interface);
++
++/*!
++ * ipu_csi_get_sensor_protocol
++ *
++ * @param ipu ipu handler
++ * @param csi csi 0 or csi 1
++ *
++ * @return Returns sensor protocol
++ */
++int32_t ipu_csi_get_sensor_protocol(struct ipu_soc *ipu, uint32_t csi)
++{
++ int ret;
++ _ipu_get(ipu);
++ ret = (ipu_csi_read(ipu, csi, CSI_SENS_CONF) &
++ CSI_SENS_CONF_SENS_PRTCL_MASK) >>
++ CSI_SENS_CONF_SENS_PRTCL_SHIFT;
++ _ipu_put(ipu);
++ return ret;
++}
++EXPORT_SYMBOL(ipu_csi_get_sensor_protocol);
++
++/*!
++ * ipu_csi_enable_mclk
++ *
++ * @param ipu ipu handler
++ * @param csi csi 0 or csi 1
++ * @param flag true to enable mclk, false to disable mclk
++ * @param wait true to wait 100ms make clock stable, false not wait
++ *
++ * @return Returns 0 on success
++ */
++int ipu_csi_enable_mclk(struct ipu_soc *ipu, int csi, bool flag, bool wait)
++{
++ /* Return immediately if there is no csi_clk to manage */
++ if (ipu->csi_clk[csi] == NULL)
++ return 0;
++
++ if (flag) {
++ clk_enable(ipu->csi_clk[csi]);
++ if (wait == true)
++ msleep(10);
++ } else {
++ clk_disable(ipu->csi_clk[csi]);
++ }
++
++ return 0;
++}
++EXPORT_SYMBOL(ipu_csi_enable_mclk);
++
++/*!
++ * ipu_csi_get_window_size
++ *
++ * @param ipu ipu handler
++ * @param width pointer to window width
++ * @param height pointer to window height
++ * @param csi csi 0 or csi 1
++ */
++void ipu_csi_get_window_size(struct ipu_soc *ipu, uint32_t *width, uint32_t *height, uint32_t csi)
++{
++ uint32_t reg;
++
++ _ipu_get(ipu);
++
++ mutex_lock(&ipu->mutex_lock);
++
++ reg = ipu_csi_read(ipu, csi, CSI_ACT_FRM_SIZE);
++ *width = (reg & 0xFFFF) + 1;
++ *height = (reg >> 16 & 0xFFFF) + 1;
++
++ mutex_unlock(&ipu->mutex_lock);
++
++ _ipu_put(ipu);
++}
++EXPORT_SYMBOL(ipu_csi_get_window_size);
++
++/*!
++ * ipu_csi_set_window_size
++ *
++ * @param ipu ipu handler
++ * @param width window width
++ * @param height window height
++ * @param csi csi 0 or csi 1
++ */
++void ipu_csi_set_window_size(struct ipu_soc *ipu, uint32_t width, uint32_t height, uint32_t csi)
++{
++ _ipu_get(ipu);
++
++ mutex_lock(&ipu->mutex_lock);
++
++ ipu_csi_write(ipu, csi, (width - 1) | (height - 1) << 16, CSI_ACT_FRM_SIZE);
++
++ mutex_unlock(&ipu->mutex_lock);
++
++ _ipu_put(ipu);
++}
++EXPORT_SYMBOL(ipu_csi_set_window_size);
++
++/*!
++ * ipu_csi_set_window_pos
++ *
++ * @param ipu ipu handler
++ * @param left uint32 window x start
++ * @param top uint32 window y start
++ * @param csi csi 0 or csi 1
++ */
++void ipu_csi_set_window_pos(struct ipu_soc *ipu, uint32_t left, uint32_t top, uint32_t csi)
++{
++ uint32_t temp;
++
++ _ipu_get(ipu);
++
++ mutex_lock(&ipu->mutex_lock);
++
++ temp = ipu_csi_read(ipu, csi, CSI_OUT_FRM_CTRL);
++ temp &= ~(CSI_HSC_MASK | CSI_VSC_MASK);
++ temp |= ((top << CSI_VSC_SHIFT) | (left << CSI_HSC_SHIFT));
++ ipu_csi_write(ipu, csi, temp, CSI_OUT_FRM_CTRL);
++
++ mutex_unlock(&ipu->mutex_lock);
++
++ _ipu_put(ipu);
++}
++EXPORT_SYMBOL(ipu_csi_set_window_pos);
++
++/*!
++ * _ipu_csi_horizontal_downsize_enable
++ * Enable horizontal downsizing(decimation) by 2.
++ *
++ * @param ipu ipu handler
++ * @param csi csi 0 or csi 1
++ */
++void _ipu_csi_horizontal_downsize_enable(struct ipu_soc *ipu, uint32_t csi)
++{
++ uint32_t temp;
++
++ temp = ipu_csi_read(ipu, csi, CSI_OUT_FRM_CTRL);
++ temp |= CSI_HORI_DOWNSIZE_EN;
++ ipu_csi_write(ipu, csi, temp, CSI_OUT_FRM_CTRL);
++}
++
++/*!
++ * _ipu_csi_horizontal_downsize_disable
++ * Disable horizontal downsizing(decimation) by 2.
++ *
++ * @param ipu ipu handler
++ * @param csi csi 0 or csi 1
++ */
++void _ipu_csi_horizontal_downsize_disable(struct ipu_soc *ipu, uint32_t csi)
++{
++ uint32_t temp;
++
++ temp = ipu_csi_read(ipu, csi, CSI_OUT_FRM_CTRL);
++ temp &= ~CSI_HORI_DOWNSIZE_EN;
++ ipu_csi_write(ipu, csi, temp, CSI_OUT_FRM_CTRL);
++}
++
++/*!
++ * _ipu_csi_vertical_downsize_enable
++ * Enable vertical downsizing(decimation) by 2.
++ *
++ * @param ipu ipu handler
++ * @param csi csi 0 or csi 1
++ */
++void _ipu_csi_vertical_downsize_enable(struct ipu_soc *ipu, uint32_t csi)
++{
++ uint32_t temp;
++
++ temp = ipu_csi_read(ipu, csi, CSI_OUT_FRM_CTRL);
++ temp |= CSI_VERT_DOWNSIZE_EN;
++ ipu_csi_write(ipu, csi, temp, CSI_OUT_FRM_CTRL);
++}
++
++/*!
++ * _ipu_csi_vertical_downsize_disable
++ * Disable vertical downsizing(decimation) by 2.
++ *
++ * @param ipu ipu handler
++ * @param csi csi 0 or csi 1
++ */
++void _ipu_csi_vertical_downsize_disable(struct ipu_soc *ipu, uint32_t csi)
++{
++ uint32_t temp;
++
++ temp = ipu_csi_read(ipu, csi, CSI_OUT_FRM_CTRL);
++ temp &= ~CSI_VERT_DOWNSIZE_EN;
++ ipu_csi_write(ipu, csi, temp, CSI_OUT_FRM_CTRL);
++}
++
++/*!
++ * _ipu_csi_set_test_generator
++ *
++ * @param ipu ipu handler
++ * @param active 1 for active and 0 for inactive
++ * @param r_value red value for the generated pattern of even pixel
++ * @param g_value green value for the generated pattern of even
++ * pixel
++ * @param b_value blue value for the generated pattern of even pixel
++ * @param pixel_clk desired pixel clock frequency in Hz
++ * @param csi csi 0 or csi 1
++ */
++void _ipu_csi_set_test_generator(struct ipu_soc *ipu, bool active, uint32_t r_value,
++ uint32_t g_value, uint32_t b_value, uint32_t pix_clk, uint32_t csi)
++{
++ uint32_t temp;
++
++ temp = ipu_csi_read(ipu, csi, CSI_TST_CTRL);
++
++ if (active == false) {
++ temp &= ~CSI_TEST_GEN_MODE_EN;
++ ipu_csi_write(ipu, csi, temp, CSI_TST_CTRL);
++ } else {
++ /* Set sensb_mclk div_ratio*/
++ _ipu_csi_mclk_set(ipu, pix_clk, csi);
++
++ temp &= ~(CSI_TEST_GEN_R_MASK | CSI_TEST_GEN_G_MASK |
++ CSI_TEST_GEN_B_MASK);
++ temp |= CSI_TEST_GEN_MODE_EN;
++ temp |= (r_value << CSI_TEST_GEN_R_SHIFT) |
++ (g_value << CSI_TEST_GEN_G_SHIFT) |
++ (b_value << CSI_TEST_GEN_B_SHIFT);
++ ipu_csi_write(ipu, csi, temp, CSI_TST_CTRL);
++ }
++}
++
++/*!
++ * _ipu_csi_ccir_err_detection_en
++ * Enable error detection and correction for
++ * CCIR interlaced mode with protection bit.
++ *
++ * @param ipu ipu handler
++ * @param csi csi 0 or csi 1
++ */
++void _ipu_csi_ccir_err_detection_enable(struct ipu_soc *ipu, uint32_t csi)
++{
++ uint32_t temp;
++
++ temp = ipu_csi_read(ipu, csi, CSI_CCIR_CODE_1);
++ temp |= CSI_CCIR_ERR_DET_EN;
++ ipu_csi_write(ipu, csi, temp, CSI_CCIR_CODE_1);
++
++}
++
++/*!
++ * _ipu_csi_ccir_err_detection_disable
++ * Disable error detection and correction for
++ * CCIR interlaced mode with protection bit.
++ *
++ * @param ipu ipu handler
++ * @param csi csi 0 or csi 1
++ */
++void _ipu_csi_ccir_err_detection_disable(struct ipu_soc *ipu, uint32_t csi)
++{
++ uint32_t temp;
++
++ temp = ipu_csi_read(ipu, csi, CSI_CCIR_CODE_1);
++ temp &= ~CSI_CCIR_ERR_DET_EN;
++ ipu_csi_write(ipu, csi, temp, CSI_CCIR_CODE_1);
++
++}
++
++/*!
++ * _ipu_csi_set_mipi_di
++ *
++ * @param ipu ipu handler
++ * @param num MIPI data identifier 0-3 handled by CSI
++ * @param di_val data identifier value
++ * @param csi csi 0 or csi 1
++ *
++ * @return Returns 0 on success or negative error code on fail
++ */
++int _ipu_csi_set_mipi_di(struct ipu_soc *ipu, uint32_t num, uint32_t di_val, uint32_t csi)
++{
++ uint32_t temp;
++ int retval = 0;
++
++ if (di_val > 0xFFL) {
++ retval = -EINVAL;
++ goto err;
++ }
++
++ temp = ipu_csi_read(ipu, csi, CSI_MIPI_DI);
++
++ switch (num) {
++ case IPU_CSI_MIPI_DI0:
++ temp &= ~CSI_MIPI_DI0_MASK;
++ temp |= (di_val << CSI_MIPI_DI0_SHIFT);
++ ipu_csi_write(ipu, csi, temp, CSI_MIPI_DI);
++ break;
++ case IPU_CSI_MIPI_DI1:
++ temp &= ~CSI_MIPI_DI1_MASK;
++ temp |= (di_val << CSI_MIPI_DI1_SHIFT);
++ ipu_csi_write(ipu, csi, temp, CSI_MIPI_DI);
++ break;
++ case IPU_CSI_MIPI_DI2:
++ temp &= ~CSI_MIPI_DI2_MASK;
++ temp |= (di_val << CSI_MIPI_DI2_SHIFT);
++ ipu_csi_write(ipu, csi, temp, CSI_MIPI_DI);
++ break;
++ case IPU_CSI_MIPI_DI3:
++ temp &= ~CSI_MIPI_DI3_MASK;
++ temp |= (di_val << CSI_MIPI_DI3_SHIFT);
++ ipu_csi_write(ipu, csi, temp, CSI_MIPI_DI);
++ break;
++ default:
++ retval = -EINVAL;
++ }
++
++err:
++ return retval;
++}
++
++/*!
++ * _ipu_csi_set_skip_isp
++ *
++ * @param ipu ipu handler
++ * @param skip select frames to be skipped and set the
++ * correspond bits to 1
++ * @param max_ratio number of frames in a skipping set and the
++ * maximum value of max_ratio is 5
++ * @param csi csi 0 or csi 1
++ *
++ * @return Returns 0 on success or negative error code on fail
++ */
++int _ipu_csi_set_skip_isp(struct ipu_soc *ipu, uint32_t skip, uint32_t max_ratio, uint32_t csi)
++{
++ uint32_t temp;
++ int retval = 0;
++
++ if (max_ratio > 5) {
++ retval = -EINVAL;
++ goto err;
++ }
++
++ temp = ipu_csi_read(ipu, csi, CSI_SKIP);
++ temp &= ~(CSI_MAX_RATIO_SKIP_ISP_MASK | CSI_SKIP_ISP_MASK);
++ temp |= (max_ratio << CSI_MAX_RATIO_SKIP_ISP_SHIFT) |
++ (skip << CSI_SKIP_ISP_SHIFT);
++ ipu_csi_write(ipu, csi, temp, CSI_SKIP);
++
++err:
++ return retval;
++}
++
++/*!
++ * _ipu_csi_set_skip_smfc
++ *
++ * @param ipu ipu handler
++ * @param skip select frames to be skipped and set the
++ * correspond bits to 1
++ * @param max_ratio number of frames in a skipping set and the
++ * maximum value of max_ratio is 5
++ * @param id csi to smfc skipping id
++ * @param csi csi 0 or csi 1
++ *
++ * @return Returns 0 on success or negative error code on fail
++ */
++int _ipu_csi_set_skip_smfc(struct ipu_soc *ipu, uint32_t skip,
++ uint32_t max_ratio, uint32_t id, uint32_t csi)
++{
++ uint32_t temp;
++ int retval = 0;
++
++ if (max_ratio > 5 || id > 3) {
++ retval = -EINVAL;
++ goto err;
++ }
++
++ temp = ipu_csi_read(ipu, csi, CSI_SKIP);
++ temp &= ~(CSI_MAX_RATIO_SKIP_SMFC_MASK | CSI_ID_2_SKIP_MASK |
++ CSI_SKIP_SMFC_MASK);
++ temp |= (max_ratio << CSI_MAX_RATIO_SKIP_SMFC_SHIFT) |
++ (id << CSI_ID_2_SKIP_SHIFT) |
++ (skip << CSI_SKIP_SMFC_SHIFT);
++ ipu_csi_write(ipu, csi, temp, CSI_SKIP);
++
++err:
++ return retval;
++}
++
++/*!
++ * _ipu_smfc_init
++ * Map CSI frames to IDMAC channels.
++ *
++ * @param ipu ipu handler
++ * @param channel IDMAC channel 0-3
++ * @param mipi_id mipi id number 0-3
++ * @param csi csi0 or csi1
++ */
++void _ipu_smfc_init(struct ipu_soc *ipu, ipu_channel_t channel, uint32_t mipi_id, uint32_t csi)
++{
++ uint32_t temp;
++
++ temp = ipu_smfc_read(ipu, SMFC_MAP);
++
++ switch (channel) {
++ case CSI_MEM0:
++ temp &= ~SMFC_MAP_CH0_MASK;
++ temp |= ((csi << 2) | mipi_id) << SMFC_MAP_CH0_SHIFT;
++ break;
++ case CSI_MEM1:
++ temp &= ~SMFC_MAP_CH1_MASK;
++ temp |= ((csi << 2) | mipi_id) << SMFC_MAP_CH1_SHIFT;
++ break;
++ case CSI_MEM2:
++ temp &= ~SMFC_MAP_CH2_MASK;
++ temp |= ((csi << 2) | mipi_id) << SMFC_MAP_CH2_SHIFT;
++ break;
++ case CSI_MEM3:
++ temp &= ~SMFC_MAP_CH3_MASK;
++ temp |= ((csi << 2) | mipi_id) << SMFC_MAP_CH3_SHIFT;
++ break;
++ default:
++ return;
++ }
++
++ ipu_smfc_write(ipu, temp, SMFC_MAP);
++}
++
++/*!
++ * _ipu_smfc_set_wmc
++ * Caution: The number of required channels, the enabled channels
++ * and the FIFO size per channel are configured restrictedly.
++ *
++ * @param ipu ipu handler
++ * @param channel IDMAC channel 0-3
++ * @param set set 1 or clear 0
++ * @param level water mark level when FIFO is on the
++ * relative size
++ */
++void _ipu_smfc_set_wmc(struct ipu_soc *ipu, ipu_channel_t channel, bool set, uint32_t level)
++{
++ uint32_t temp;
++
++ temp = ipu_smfc_read(ipu, SMFC_WMC);
++
++ switch (channel) {
++ case CSI_MEM0:
++ if (set == true) {
++ temp &= ~SMFC_WM0_SET_MASK;
++ temp |= level << SMFC_WM0_SET_SHIFT;
++ } else {
++ temp &= ~SMFC_WM0_CLR_MASK;
++ temp |= level << SMFC_WM0_CLR_SHIFT;
++ }
++ break;
++ case CSI_MEM1:
++ if (set == true) {
++ temp &= ~SMFC_WM1_SET_MASK;
++ temp |= level << SMFC_WM1_SET_SHIFT;
++ } else {
++ temp &= ~SMFC_WM1_CLR_MASK;
++ temp |= level << SMFC_WM1_CLR_SHIFT;
++ }
++ break;
++ case CSI_MEM2:
++ if (set == true) {
++ temp &= ~SMFC_WM2_SET_MASK;
++ temp |= level << SMFC_WM2_SET_SHIFT;
++ } else {
++ temp &= ~SMFC_WM2_CLR_MASK;
++ temp |= level << SMFC_WM2_CLR_SHIFT;
++ }
++ break;
++ case CSI_MEM3:
++ if (set == true) {
++ temp &= ~SMFC_WM3_SET_MASK;
++ temp |= level << SMFC_WM3_SET_SHIFT;
++ } else {
++ temp &= ~SMFC_WM3_CLR_MASK;
++ temp |= level << SMFC_WM3_CLR_SHIFT;
++ }
++ break;
++ default:
++ return;
++ }
++
++ ipu_smfc_write(ipu, temp, SMFC_WMC);
++}
++
++/*!
++ * _ipu_smfc_set_burst_size
++ *
++ * @param ipu ipu handler
++ * @param channel IDMAC channel 0-3
++ * @param bs burst size of IDMAC channel,
++ * the value programmed here shoud be BURST_SIZE-1
++ */
++void _ipu_smfc_set_burst_size(struct ipu_soc *ipu, ipu_channel_t channel, uint32_t bs)
++{
++ uint32_t temp;
++
++ temp = ipu_smfc_read(ipu, SMFC_BS);
++
++ switch (channel) {
++ case CSI_MEM0:
++ temp &= ~SMFC_BS0_MASK;
++ temp |= bs << SMFC_BS0_SHIFT;
++ break;
++ case CSI_MEM1:
++ temp &= ~SMFC_BS1_MASK;
++ temp |= bs << SMFC_BS1_SHIFT;
++ break;
++ case CSI_MEM2:
++ temp &= ~SMFC_BS2_MASK;
++ temp |= bs << SMFC_BS2_SHIFT;
++ break;
++ case CSI_MEM3:
++ temp &= ~SMFC_BS3_MASK;
++ temp |= bs << SMFC_BS3_SHIFT;
++ break;
++ default:
++ return;
++ }
++
++ ipu_smfc_write(ipu, temp, SMFC_BS);
++}
++
++/*!
++ * _ipu_csi_init
++ *
++ * @param ipu ipu handler
++ * @param channel IDMAC channel
++ * @param csi csi 0 or csi 1
++ *
++ * @return Returns 0 on success or negative error code on fail
++ */
++int _ipu_csi_init(struct ipu_soc *ipu, ipu_channel_t channel, uint32_t csi)
++{
++ uint32_t csi_sens_conf, csi_dest;
++ int retval = 0;
++
++ switch (channel) {
++ case CSI_MEM0:
++ case CSI_MEM1:
++ case CSI_MEM2:
++ case CSI_MEM3:
++ csi_dest = CSI_DATA_DEST_IDMAC;
++ break;
++ case CSI_PRP_ENC_MEM:
++ case CSI_PRP_VF_MEM:
++ csi_dest = CSI_DATA_DEST_IC;
++ break;
++ default:
++ retval = -EINVAL;
++ goto err;
++ }
++
++ csi_sens_conf = ipu_csi_read(ipu, csi, CSI_SENS_CONF);
++ csi_sens_conf &= ~CSI_SENS_CONF_DATA_DEST_MASK;
++ ipu_csi_write(ipu, csi, csi_sens_conf | (csi_dest <<
++ CSI_SENS_CONF_DATA_DEST_SHIFT), CSI_SENS_CONF);
++err:
++ return retval;
++}
++
++/*!
++ * csi_irq_handler
++ *
++ * @param irq interrupt id
++ * @param dev_id pointer to ipu handler
++ *
++ * @return Returns if irq is handled
++ */
++static irqreturn_t csi_irq_handler(int irq, void *dev_id)
++{
++ struct ipu_soc *ipu = dev_id;
++ struct completion *comp = &ipu->csi_comp;
++
++ complete(comp);
++ return IRQ_HANDLED;
++}
++
++/*!
++ * _ipu_csi_wait4eof
++ *
++ * @param ipu ipu handler
++ * @param channel IDMAC channel
++ *
++ */
++void _ipu_csi_wait4eof(struct ipu_soc *ipu, ipu_channel_t channel)
++{
++ int ret;
++ int irq = 0;
++
++ if (channel == CSI_MEM0)
++ irq = IPU_IRQ_CSI0_OUT_EOF;
++ else if (channel == CSI_MEM1)
++ irq = IPU_IRQ_CSI1_OUT_EOF;
++ else if (channel == CSI_MEM2)
++ irq = IPU_IRQ_CSI2_OUT_EOF;
++ else if (channel == CSI_MEM3)
++ irq = IPU_IRQ_CSI3_OUT_EOF;
++ else if (channel == CSI_PRP_ENC_MEM)
++ irq = IPU_IRQ_PRP_ENC_OUT_EOF;
++ else if (channel == CSI_PRP_VF_MEM)
++ irq = IPU_IRQ_PRP_VF_OUT_EOF;
++ else{
++ dev_err(ipu->dev, "Not a CSI channel\n");
++ return;
++ }
++
++ init_completion(&ipu->csi_comp);
++ ret = ipu_request_irq(ipu, irq, csi_irq_handler, 0, NULL, ipu);
++ if (ret < 0) {
++ dev_err(ipu->dev, "CSI irq %d in use\n", irq);
++ return;
++ }
++ ret = wait_for_completion_timeout(&ipu->csi_comp, msecs_to_jiffies(500));
++ ipu_free_irq(ipu, irq, ipu);
++ dev_dbg(ipu->dev, "CSI stop timeout - %d * 10ms\n", 5 - ret);
++}
+diff -Nur linux-4.1.3/drivers/mxc/ipu3/ipu_common.c linux-xbian-imx6/drivers/mxc/ipu3/ipu_common.c
+--- linux-4.1.3/drivers/mxc/ipu3/ipu_common.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/ipu3/ipu_common.c 2015-07-27 23:13:06.226765901 +0200
+@@ -0,0 +1,3151 @@
++/*
++ * Copyright 2005-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*!
++ * @file ipu_common.c
++ *
++ * @brief This file contains the IPU driver common API functions.
++ *
++ * @ingroup IPU
++ */
++
++
++#include <linux/clk.h>
++#include <linux/clk-provider.h>
++#include <linux/clk/clk-conf.h>
++
++
++#include <linux/busfreq-imx6.h>
++#include <linux/delay.h>
++#include <linux/err.h>
++#include <linux/init.h>
++#include <linux/interrupt.h>
++#include <linux/io.h>
++#include <linux/ipu-v3.h>
++#include <linux/irq.h>
++#include <linux/irqdesc.h>
++#include <linux/module.h>
++#include <linux/mod_devicetable.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++#include <linux/pm_runtime.h>
++#include <linux/reset.h>
++#include <linux/spinlock.h>
++#include <linux/types.h>
++
++#include <asm/cacheflush.h>
++
++#include "ipu_param_mem.h"
++#include "ipu_regs.h"
++
++static struct ipu_soc ipu_array[MXC_IPU_MAX_NUM];
++int g_ipu_hw_rev;
++
++/* Static functions */
++static irqreturn_t ipu_sync_irq_handler(int irq, void *desc);
++static irqreturn_t ipu_err_irq_handler(int irq, void *desc);
++
++static inline uint32_t channel_2_dma(ipu_channel_t ch, ipu_buffer_t type)
++{
++ return ((uint32_t) ch >> (6 * type)) & 0x3F;
++};
++
++static inline int _ipu_is_ic_chan(uint32_t dma_chan)
++{
++ return (((dma_chan >= 11) && (dma_chan <= 22) && (dma_chan != 17) &&
++ (dma_chan != 18)));
++}
++
++static inline int _ipu_is_vdi_out_chan(uint32_t dma_chan)
++{
++ return (dma_chan == 5);
++}
++
++static inline int _ipu_is_ic_graphic_chan(uint32_t dma_chan)
++{
++ return (dma_chan == 14 || dma_chan == 15);
++}
++
++/* Either DP BG or DP FG can be graphic window */
++static inline int _ipu_is_dp_graphic_chan(uint32_t dma_chan)
++{
++ return (dma_chan == 23 || dma_chan == 27);
++}
++
++static inline int _ipu_is_irt_chan(uint32_t dma_chan)
++{
++ return ((dma_chan >= 45) && (dma_chan <= 50));
++}
++
++static inline int _ipu_is_dmfc_chan(uint32_t dma_chan)
++{
++ return ((dma_chan >= 23) && (dma_chan <= 29));
++}
++
++static inline int _ipu_is_smfc_chan(uint32_t dma_chan)
++{
++ return ((dma_chan >= 0) && (dma_chan <= 3));
++}
++
++static inline int _ipu_is_trb_chan(uint32_t dma_chan)
++{
++ return (((dma_chan == 8) || (dma_chan == 9) ||
++ (dma_chan == 10) || (dma_chan == 13) ||
++ (dma_chan == 21) || (dma_chan == 23) ||
++ (dma_chan == 27) || (dma_chan == 28)) &&
++ (g_ipu_hw_rev >= IPU_V3DEX));
++}
++
++/*
++ * We usually use IDMAC 23 as full plane and IDMAC 27 as partial
++ * plane.
++ * IDMAC 23/24/28/41 can drive a display respectively - primary
++ * IDMAC 27 depends on IDMAC 23 - nonprimary
++ */
++static inline int _ipu_is_primary_disp_chan(uint32_t dma_chan)
++{
++ return ((dma_chan == 23) || (dma_chan == 24) ||
++ (dma_chan == 28) || (dma_chan == 41));
++}
++
++static inline int _ipu_is_sync_irq(uint32_t irq)
++{
++ /* sync interrupt register number */
++ int reg_num = irq / 32 + 1;
++
++ return ((reg_num == 1) || (reg_num == 2) || (reg_num == 3) ||
++ (reg_num == 4) || (reg_num == 7) || (reg_num == 8) ||
++ (reg_num == 11) || (reg_num == 12) || (reg_num == 13) ||
++ (reg_num == 14) || (reg_num == 15));
++}
++
++#define idma_is_valid(ch) (ch != NO_DMA)
++#define idma_mask(ch) (idma_is_valid(ch) ? (1UL << (ch & 0x1F)) : 0)
++#define idma_is_set(ipu, reg, dma) (ipu_idmac_read(ipu, reg(dma)) & idma_mask(dma))
++#define tri_cur_buf_mask(ch) (idma_mask(ch*2) * 3)
++#define tri_cur_buf_shift(ch) (ffs(idma_mask(ch*2)) - 1)
++
++static int ipu_clk_setup_enable(struct ipu_soc *ipu,
++ struct ipu_pltfm_data *pdata)
++{
++ char pixel_clk_0[] = "ipu1_pclk_0";
++ char pixel_clk_1[] = "ipu1_pclk_1";
++ char pixel_clk_0_sel[] = "ipu1_pclk0_sel";
++ char pixel_clk_1_sel[] = "ipu1_pclk1_sel";
++ char pixel_clk_0_div[] = "ipu1_pclk0_div";
++ char pixel_clk_1_div[] = "ipu1_pclk1_div";
++ char *ipu_pixel_clk_sel1[] = { "ipu1", "ipu1_di0", "ipu1_di1", };
++ char *ipu_pixel_clk_sel2[] = { "ipu2", "ipu2_di0", "ipu2_di1", };
++ char **ipu_pixel_clk_sel;
++ struct clk *clk;
++ int ret;
++
++ strncpy(ipu->pixel_clk_0, pixel_clk_0, sizeof(ipu->pixel_clk_0));
++ ipu->pixel_clk_0[3] += pdata->id;
++ strncpy(ipu->pixel_clk_1, pixel_clk_1, sizeof(ipu->pixel_clk_1));
++ ipu->pixel_clk_1[3] += pdata->id;
++ strncpy(ipu->pixel_clk_0_sel, pixel_clk_0_sel, sizeof(ipu->pixel_clk_0_sel));
++ ipu->pixel_clk_0_sel[3] += pdata->id;
++ strncpy(ipu->pixel_clk_1_sel, pixel_clk_1_sel, sizeof(ipu->pixel_clk_1_sel));
++ ipu->pixel_clk_1_sel[3] += pdata->id;
++ strncpy(ipu->pixel_clk_0_div, pixel_clk_0_div, sizeof(ipu->pixel_clk_0_div));
++ ipu->pixel_clk_0_div[3] += pdata->id;
++ strncpy(ipu->pixel_clk_1_div, pixel_clk_1_div, sizeof(ipu->pixel_clk_1_div));
++ ipu->pixel_clk_1_div[3] += pdata->id;
++
++ if (pdata->id == 0)
++ ipu_pixel_clk_sel = ipu_pixel_clk_sel1;
++ else
++ ipu_pixel_clk_sel = ipu_pixel_clk_sel2;
++
++ clk = clk_register_mux_pix_clk(ipu->dev, ipu->pixel_clk_0_sel,
++ (const char **)ipu_pixel_clk_sel,
++ ARRAY_SIZE(ipu_pixel_clk_sel1),
++ 0, pdata->id, 0, 0);
++ if (IS_ERR(clk)) {
++ dev_err(ipu->dev, "clk_register mux di0 failed");
++ return PTR_ERR(clk);
++ }
++ ipu->pixel_clk_sel[0] = clk;
++ clk = clk_register_mux_pix_clk(ipu->dev, ipu->pixel_clk_1_sel,
++ (const char **)ipu_pixel_clk_sel,
++ ARRAY_SIZE(ipu_pixel_clk_sel1),
++ 0, pdata->id, 1, 0);
++ if (IS_ERR(clk)) {
++ dev_err(ipu->dev, "clk_register mux di1 failed");
++ return PTR_ERR(clk);
++ }
++ ipu->pixel_clk_sel[1] = clk;
++
++ clk = clk_register_div_pix_clk(ipu->dev, ipu->pixel_clk_0_div,
++ ipu->pixel_clk_0_sel, 0, pdata->id, 0, 0);
++ if (IS_ERR(clk)) {
++ dev_err(ipu->dev, "clk register di0 div failed");
++ return PTR_ERR(clk);
++ }
++ clk = clk_register_div_pix_clk(ipu->dev, ipu->pixel_clk_1_div,
++ ipu->pixel_clk_1_sel, CLK_SET_RATE_PARENT, pdata->id, 1, 0);
++ if (IS_ERR(clk)) {
++ dev_err(ipu->dev, "clk register di1 div failed");
++ return PTR_ERR(clk);
++ }
++
++ ipu->pixel_clk[0] = clk_register_gate_pix_clk(ipu->dev, ipu->pixel_clk_0,
++ ipu->pixel_clk_0_div, CLK_SET_RATE_PARENT,
++ pdata->id, 0, 0);
++ if (IS_ERR(ipu->pixel_clk[0])) {
++ dev_err(ipu->dev, "clk register di0 gate failed");
++ return PTR_ERR(ipu->pixel_clk[0]);
++ }
++ ipu->pixel_clk[1] = clk_register_gate_pix_clk(ipu->dev, ipu->pixel_clk_1,
++ ipu->pixel_clk_1_div, CLK_SET_RATE_PARENT,
++ pdata->id, 1, 0);
++ if (IS_ERR(ipu->pixel_clk[1])) {
++ dev_err(ipu->dev, "clk register di1 gate failed");
++ return PTR_ERR(ipu->pixel_clk[1]);
++ }
++
++ ret = clk_set_parent(ipu->pixel_clk_sel[0], ipu->ipu_clk);
++ if (ret) {
++ dev_err(ipu->dev, "clk set parent failed %s, %d", __clk_get_name(ipu->ipu_clk), ret);
++ return ret;
++ }
++
++ ret = clk_set_parent(ipu->pixel_clk_sel[1], ipu->ipu_clk);
++ if (ret) {
++ dev_err(ipu->dev, "clk set parent failed %s, %d", __clk_get_name(ipu->ipu_clk), ret);
++ return ret;
++ }
++
++ ipu->di_clk[0] = devm_clk_get(ipu->dev, "di0");
++ if (IS_ERR(ipu->di_clk[0])) {
++ dev_err(ipu->dev, "clk_get di0 failed");
++ return PTR_ERR(ipu->di_clk[0]);
++ }
++ ipu->di_clk[1] = devm_clk_get(ipu->dev, "di1");
++ if (IS_ERR(ipu->di_clk[1])) {
++ dev_err(ipu->dev, "clk_get di1 failed");
++ return PTR_ERR(ipu->di_clk[1]);
++ }
++
++ ipu->di_clk_sel[0] = devm_clk_get(ipu->dev, "di0_sel");
++ if (IS_ERR(ipu->di_clk_sel[0])) {
++ dev_err(ipu->dev, "clk_get di0_sel failed");
++ return PTR_ERR(ipu->di_clk_sel[0]);
++ }
++ ipu->di_clk_sel[1] = devm_clk_get(ipu->dev, "di1_sel");
++ if (IS_ERR(ipu->di_clk_sel[1])) {
++ dev_err(ipu->dev, "clk_get di1_sel failed");
++ return PTR_ERR(ipu->di_clk_sel[1]);
++ }
++
++ return 0;
++}
++
++static int ipu_mem_reset(struct ipu_soc *ipu)
++{
++ int timeout = 1000;
++
++ ipu_cm_write(ipu, 0x807FFFFF, IPU_MEM_RST);
++
++ while (ipu_cm_read(ipu, IPU_MEM_RST) & 0x80000000) {
++ if (!timeout--)
++ return -ETIME;
++ msleep(1);
++ }
++
++ return 0;
++}
++
++struct ipu_soc *ipu_get_soc(int id)
++{
++ if (id >= MXC_IPU_MAX_NUM)
++ return ERR_PTR(-ENODEV);
++ else if (!ipu_array[id].online)
++ return ERR_PTR(-ENODEV);
++ else
++ return &(ipu_array[id]);
++}
++EXPORT_SYMBOL_GPL(ipu_get_soc);
++
++void _ipu_get(struct ipu_soc *ipu)
++{
++ int ret;
++
++ ret = clk_enable(ipu->ipu_clk);
++ if (ret < 0)
++ BUG();
++}
++
++void _ipu_put(struct ipu_soc *ipu)
++{
++ clk_disable(ipu->ipu_clk);
++}
++
++void ipu_disable_hsp_clk(struct ipu_soc *ipu)
++{
++ _ipu_put(ipu);
++}
++EXPORT_SYMBOL(ipu_disable_hsp_clk);
++
++static struct platform_device_id imx_ipu_type[] = {
++ {
++ .name = "ipu-imx6q",
++ .driver_data = IPU_V3H,
++ }, {
++ /* sentinel */
++ }
++};
++MODULE_DEVICE_TABLE(platform, imx_ipu_type);
++
++static const struct of_device_id imx_ipuv3_dt_ids[] = {
++ { .compatible = "fsl,imx6q-ipu", .data = &imx_ipu_type[IMX6Q_IPU], },
++ { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, imx_ipuv3_dt_ids);
++
++/*!
++ * This function is called by the driver framework to initialize the IPU
++ * hardware.
++ *
++ * @param dev The device structure for the IPU passed in by the
++ * driver framework.
++ *
++ * @return Returns 0 on success or negative error code on error
++ */
++static int ipu_probe(struct platform_device *pdev)
++{
++ struct ipu_soc *ipu;
++ struct resource *res;
++ unsigned long ipu_base;
++ const struct of_device_id *of_id =
++ of_match_device(imx_ipuv3_dt_ids, &pdev->dev);
++ struct ipu_pltfm_data *pltfm_data;
++ int ret = 0;
++ u32 bypass_reset;
++
++ dev_dbg(&pdev->dev, "<%s>\n", __func__);
++
++ pltfm_data = devm_kzalloc(&pdev->dev, sizeof(struct ipu_pltfm_data),
++ GFP_KERNEL);
++ if (!pltfm_data)
++ return -ENOMEM;
++
++ ret = of_property_read_u32(pdev->dev.of_node,
++ "bypass_reset", &bypass_reset);
++ if (ret < 0) {
++ dev_dbg(&pdev->dev, "can not get bypass_reset\n");
++ return ret;
++ }
++ pltfm_data->bypass_reset = (bool)bypass_reset;
++
++ pltfm_data->id = of_alias_get_id(pdev->dev.of_node, "ipu");
++ if (pltfm_data->id < 0) {
++ dev_dbg(&pdev->dev, "can not get alias id\n");
++ return pltfm_data->id;
++ } else
++ dev_dbg(&pdev->dev, "get alias id %d\n", pltfm_data->id);
++
++ if (of_id)
++ pdev->id_entry = of_id->data;
++ pltfm_data->devtype = pdev->id_entry->driver_data;
++ g_ipu_hw_rev = pltfm_data->devtype;
++
++ ipu = &ipu_array[pltfm_data->id];
++ memset(ipu, 0, sizeof(struct ipu_soc));
++ ipu->dev = &pdev->dev;
++ ipu->pdata = pltfm_data;
++ dev_dbg(ipu->dev, "IPU rev:%d\n", g_ipu_hw_rev);
++ spin_lock_init(&ipu->int_reg_spin_lock);
++ spin_lock_init(&ipu->rdy_reg_spin_lock);
++ mutex_init(&ipu->mutex_lock);
++
++ ipu->irq_sync = platform_get_irq(pdev, 0);
++ ipu->irq_err = platform_get_irq(pdev, 1);
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++
++ if (!res || ipu->irq_sync < 0 || ipu->irq_err < 0) {
++ dev_err(&pdev->dev, "can't get device resources\n");
++ return -ENODEV;
++ }
++
++ if (!devm_request_mem_region(&pdev->dev, res->start,
++ resource_size(res), pdev->name))
++ return -EBUSY;
++
++ ret = devm_request_irq(&pdev->dev, ipu->irq_sync,
++ ipu_sync_irq_handler, 0, pdev->name, ipu);
++ if (ret) {
++ dev_err(ipu->dev, "request SYNC interrupt failed\n");
++ return ret;
++ }
++ ret = devm_request_irq(&pdev->dev, ipu->irq_err,
++ ipu_err_irq_handler, 0, pdev->name, ipu);
++ if (ret) {
++ dev_err(ipu->dev, "request ERR interrupt failed\n");
++ return ret;
++ }
++
++ ipu_base = res->start;
++ /* base fixup */
++ if (g_ipu_hw_rev == IPU_V3H) /* IPUv3H */
++ ipu_base += IPUV3H_REG_BASE;
++ else if (g_ipu_hw_rev == IPU_V3M) /* IPUv3M */
++ ipu_base += IPUV3M_REG_BASE;
++ else /* IPUv3D, v3E, v3EX */
++ ipu_base += IPUV3DEX_REG_BASE;
++
++ ipu->cm_reg = devm_ioremap(&pdev->dev,
++ ipu_base + IPU_CM_REG_BASE, PAGE_SIZE);
++ ipu->ic_reg = devm_ioremap(&pdev->dev,
++ ipu_base + IPU_IC_REG_BASE, PAGE_SIZE);
++ ipu->idmac_reg = devm_ioremap(&pdev->dev,
++ ipu_base + IPU_IDMAC_REG_BASE, PAGE_SIZE);
++ /* DP Registers are accessed thru the SRM */
++ ipu->dp_reg = devm_ioremap(&pdev->dev,
++ ipu_base + IPU_SRM_REG_BASE, PAGE_SIZE);
++ ipu->dc_reg = devm_ioremap(&pdev->dev,
++ ipu_base + IPU_DC_REG_BASE, PAGE_SIZE);
++ ipu->dmfc_reg = devm_ioremap(&pdev->dev,
++ ipu_base + IPU_DMFC_REG_BASE, PAGE_SIZE);
++ ipu->di_reg[0] = devm_ioremap(&pdev->dev,
++ ipu_base + IPU_DI0_REG_BASE, PAGE_SIZE);
++ ipu->di_reg[1] = devm_ioremap(&pdev->dev,
++ ipu_base + IPU_DI1_REG_BASE, PAGE_SIZE);
++ ipu->smfc_reg = devm_ioremap(&pdev->dev,
++ ipu_base + IPU_SMFC_REG_BASE, PAGE_SIZE);
++ ipu->csi_reg[0] = devm_ioremap(&pdev->dev,
++ ipu_base + IPU_CSI0_REG_BASE, PAGE_SIZE);
++ ipu->csi_reg[1] = devm_ioremap(&pdev->dev,
++ ipu_base + IPU_CSI1_REG_BASE, PAGE_SIZE);
++ ipu->cpmem_base = devm_ioremap(&pdev->dev,
++ ipu_base + IPU_CPMEM_REG_BASE, SZ_128K);
++ ipu->tpmem_base = devm_ioremap(&pdev->dev,
++ ipu_base + IPU_TPM_REG_BASE, SZ_64K);
++ ipu->dc_tmpl_reg = devm_ioremap(&pdev->dev,
++ ipu_base + IPU_DC_TMPL_REG_BASE, SZ_128K);
++ ipu->vdi_reg = devm_ioremap(&pdev->dev,
++ ipu_base + IPU_VDI_REG_BASE, PAGE_SIZE);
++ ipu->disp_base[1] = devm_ioremap(&pdev->dev,
++ ipu_base + IPU_DISP1_BASE, SZ_4K);
++ if (!ipu->cm_reg || !ipu->ic_reg || !ipu->idmac_reg ||
++ !ipu->dp_reg || !ipu->dc_reg || !ipu->dmfc_reg ||
++ !ipu->di_reg[0] || !ipu->di_reg[1] || !ipu->smfc_reg ||
++ !ipu->csi_reg[0] || !ipu->csi_reg[1] || !ipu->cpmem_base ||
++ !ipu->tpmem_base || !ipu->dc_tmpl_reg || !ipu->disp_base[1]
++ || !ipu->vdi_reg)
++ return -ENOMEM;
++
++ dev_dbg(ipu->dev, "IPU CM Regs = %p\n", ipu->cm_reg);
++ dev_dbg(ipu->dev, "IPU IC Regs = %p\n", ipu->ic_reg);
++ dev_dbg(ipu->dev, "IPU IDMAC Regs = %p\n", ipu->idmac_reg);
++ dev_dbg(ipu->dev, "IPU DP Regs = %p\n", ipu->dp_reg);
++ dev_dbg(ipu->dev, "IPU DC Regs = %p\n", ipu->dc_reg);
++ dev_dbg(ipu->dev, "IPU DMFC Regs = %p\n", ipu->dmfc_reg);
++ dev_dbg(ipu->dev, "IPU DI0 Regs = %p\n", ipu->di_reg[0]);
++ dev_dbg(ipu->dev, "IPU DI1 Regs = %p\n", ipu->di_reg[1]);
++ dev_dbg(ipu->dev, "IPU SMFC Regs = %p\n", ipu->smfc_reg);
++ dev_dbg(ipu->dev, "IPU CSI0 Regs = %p\n", ipu->csi_reg[0]);
++ dev_dbg(ipu->dev, "IPU CSI1 Regs = %p\n", ipu->csi_reg[1]);
++ dev_dbg(ipu->dev, "IPU CPMem = %p\n", ipu->cpmem_base);
++ dev_dbg(ipu->dev, "IPU TPMem = %p\n", ipu->tpmem_base);
++ dev_dbg(ipu->dev, "IPU DC Template Mem = %p\n", ipu->dc_tmpl_reg);
++ dev_dbg(ipu->dev, "IPU Display Region 1 Mem = %p\n", ipu->disp_base[1]);
++ dev_dbg(ipu->dev, "IPU VDI Regs = %p\n", ipu->vdi_reg);
++
++ ipu->ipu_clk = devm_clk_get(ipu->dev, "bus");
++ if (IS_ERR(ipu->ipu_clk)) {
++ dev_err(ipu->dev, "clk_get ipu failed");
++ return PTR_ERR(ipu->ipu_clk);
++ }
++
++ /* ipu_clk is always prepared */
++ ret = clk_prepare_enable(ipu->ipu_clk);
++ if (ret < 0) {
++ dev_err(ipu->dev, "ipu clk enable failed\n");
++ return ret;
++ }
++
++ ipu->online = true;
++
++ platform_set_drvdata(pdev, ipu);
++
++ if (!pltfm_data->bypass_reset) {
++ ret = device_reset(&pdev->dev);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to reset: %d\n", ret);
++ return ret;
++ }
++
++ ipu_mem_reset(ipu);
++
++ ipu_disp_init(ipu);
++
++ /* Set MCU_T to divide MCU access window into 2 */
++ ipu_cm_write(ipu, 0x00400000L | (IPU_MCU_T_DEFAULT << 18),
++ IPU_DISP_GEN);
++ }
++
++ /* setup ipu clk tree after ipu reset */
++ ret = ipu_clk_setup_enable(ipu, pltfm_data);
++ if (ret < 0) {
++ dev_err(ipu->dev, "ipu clk setup failed\n");
++ ipu->online = false;
++ return ret;
++ }
++
++ /* Set sync refresh channels and CSI->mem channel as high priority */
++ ipu_idmac_write(ipu, 0x18800001L, IDMAC_CHA_PRI(0));
++
++ /* Enable error interrupts by default */
++ ipu_cm_write(ipu, 0xFFFFFFFF, IPU_INT_CTRL(5));
++ ipu_cm_write(ipu, 0xFFFFFFFF, IPU_INT_CTRL(6));
++ ipu_cm_write(ipu, 0xFFFFFFFF, IPU_INT_CTRL(9));
++ ipu_cm_write(ipu, 0xFFFFFFFF, IPU_INT_CTRL(10));
++
++ if (!pltfm_data->bypass_reset)
++ clk_disable(ipu->ipu_clk);
++
++ register_ipu_device(ipu, ipu->pdata->id);
++
++ pm_runtime_enable(&pdev->dev);
++
++ return ret;
++}
++
++int ipu_remove(struct platform_device *pdev)
++{
++ struct ipu_soc *ipu = platform_get_drvdata(pdev);
++
++ unregister_ipu_device(ipu, ipu->pdata->id);
++
++ clk_put(ipu->ipu_clk);
++
++ return 0;
++}
++
++void ipu_dump_registers(struct ipu_soc *ipu)
++{
++ dev_dbg(ipu->dev, "IPU_CONF = \t0x%08X\n", ipu_cm_read(ipu, IPU_CONF));
++ dev_dbg(ipu->dev, "IDMAC_CONF = \t0x%08X\n", ipu_idmac_read(ipu, IDMAC_CONF));
++ dev_dbg(ipu->dev, "IDMAC_CHA_EN1 = \t0x%08X\n",
++ ipu_idmac_read(ipu, IDMAC_CHA_EN(0)));
++ dev_dbg(ipu->dev, "IDMAC_CHA_EN2 = \t0x%08X\n",
++ ipu_idmac_read(ipu, IDMAC_CHA_EN(32)));
++ dev_dbg(ipu->dev, "IDMAC_CHA_PRI1 = \t0x%08X\n",
++ ipu_idmac_read(ipu, IDMAC_CHA_PRI(0)));
++ dev_dbg(ipu->dev, "IDMAC_CHA_PRI2 = \t0x%08X\n",
++ ipu_idmac_read(ipu, IDMAC_CHA_PRI(32)));
++ dev_dbg(ipu->dev, "IDMAC_BAND_EN1 = \t0x%08X\n",
++ ipu_idmac_read(ipu, IDMAC_BAND_EN(0)));
++ dev_dbg(ipu->dev, "IDMAC_BAND_EN2 = \t0x%08X\n",
++ ipu_idmac_read(ipu, IDMAC_BAND_EN(32)));
++ dev_dbg(ipu->dev, "IPU_CHA_DB_MODE_SEL0 = \t0x%08X\n",
++ ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(0)));
++ dev_dbg(ipu->dev, "IPU_CHA_DB_MODE_SEL1 = \t0x%08X\n",
++ ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(32)));
++ if (g_ipu_hw_rev >= IPU_V3DEX) {
++ dev_dbg(ipu->dev, "IPU_CHA_TRB_MODE_SEL0 = \t0x%08X\n",
++ ipu_cm_read(ipu, IPU_CHA_TRB_MODE_SEL(0)));
++ dev_dbg(ipu->dev, "IPU_CHA_TRB_MODE_SEL1 = \t0x%08X\n",
++ ipu_cm_read(ipu, IPU_CHA_TRB_MODE_SEL(32)));
++ }
++ dev_dbg(ipu->dev, "DMFC_WR_CHAN = \t0x%08X\n",
++ ipu_dmfc_read(ipu, DMFC_WR_CHAN));
++ dev_dbg(ipu->dev, "DMFC_WR_CHAN_DEF = \t0x%08X\n",
++ ipu_dmfc_read(ipu, DMFC_WR_CHAN_DEF));
++ dev_dbg(ipu->dev, "DMFC_DP_CHAN = \t0x%08X\n",
++ ipu_dmfc_read(ipu, DMFC_DP_CHAN));
++ dev_dbg(ipu->dev, "DMFC_DP_CHAN_DEF = \t0x%08X\n",
++ ipu_dmfc_read(ipu, DMFC_DP_CHAN_DEF));
++ dev_dbg(ipu->dev, "DMFC_IC_CTRL = \t0x%08X\n",
++ ipu_dmfc_read(ipu, DMFC_IC_CTRL));
++ dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW1 = \t0x%08X\n",
++ ipu_cm_read(ipu, IPU_FS_PROC_FLOW1));
++ dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW2 = \t0x%08X\n",
++ ipu_cm_read(ipu, IPU_FS_PROC_FLOW2));
++ dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW3 = \t0x%08X\n",
++ ipu_cm_read(ipu, IPU_FS_PROC_FLOW3));
++ dev_dbg(ipu->dev, "IPU_FS_DISP_FLOW1 = \t0x%08X\n",
++ ipu_cm_read(ipu, IPU_FS_DISP_FLOW1));
++ dev_dbg(ipu->dev, "IPU_VDIC_VDI_FSIZE = \t0x%08X\n",
++ ipu_vdi_read(ipu, VDI_FSIZE));
++ dev_dbg(ipu->dev, "IPU_VDIC_VDI_C = \t0x%08X\n",
++ ipu_vdi_read(ipu, VDI_C));
++ dev_dbg(ipu->dev, "IPU_IC_CONF = \t0x%08X\n",
++ ipu_ic_read(ipu, IC_CONF));
++}
++
++/*!
++ * This function is called to initialize a logical IPU channel.
++ *
++ * @param ipu ipu handler
++ * @param channel Input parameter for the logical channel ID to init.
++ *
++ * @param params Input parameter containing union of channel
++ * initialization parameters.
++ *
++ * @return Returns 0 on success or negative error code on fail
++ */
++int32_t ipu_init_channel(struct ipu_soc *ipu, ipu_channel_t channel, ipu_channel_params_t *params)
++{
++ int ret = 0;
++ bool bad_pixfmt;
++ uint32_t ipu_conf, reg, in_g_pixel_fmt, sec_dma;
++
++ dev_dbg(ipu->dev, "init channel = %d\n", IPU_CHAN_ID(channel));
++
++ ret = pm_runtime_get_sync(ipu->dev);
++ if (ret < 0) {
++ dev_err(ipu->dev, "ch = %d, pm_runtime_get failed:%d!\n",
++ IPU_CHAN_ID(channel), ret);
++ dump_stack();
++ return ret;
++ }
++ /*
++ * Here, ret could be 1 if the device's runtime PM status was
++ * already 'active', so clear it to be 0.
++ */
++ ret = 0;
++
++ _ipu_get(ipu);
++
++ mutex_lock(&ipu->mutex_lock);
++
++ /* Re-enable error interrupts every time a channel is initialized */
++ ipu_cm_write(ipu, 0xFFFFFFFF, IPU_INT_CTRL(5));
++ ipu_cm_write(ipu, 0xFFFFFFFF, IPU_INT_CTRL(6));
++ ipu_cm_write(ipu, 0xFFFFFFFF, IPU_INT_CTRL(9));
++ ipu_cm_write(ipu, 0xFFFFFFFF, IPU_INT_CTRL(10));
++
++ if (ipu->channel_init_mask & (1L << IPU_CHAN_ID(channel))) {
++ dev_warn(ipu->dev, "Warning: channel already initialized %d\n",
++ IPU_CHAN_ID(channel));
++ }
++
++ ipu_conf = ipu_cm_read(ipu, IPU_CONF);
++
++ switch (channel) {
++ case CSI_MEM0:
++ case CSI_MEM1:
++ case CSI_MEM2:
++ case CSI_MEM3:
++ if (params->csi_mem.csi > 1) {
++ ret = -EINVAL;
++ goto err;
++ }
++
++ if (params->csi_mem.interlaced)
++ ipu->chan_is_interlaced[channel_2_dma(channel,
++ IPU_OUTPUT_BUFFER)] = true;
++ else
++ ipu->chan_is_interlaced[channel_2_dma(channel,
++ IPU_OUTPUT_BUFFER)] = false;
++
++ ipu->smfc_use_count++;
++ ipu->csi_channel[params->csi_mem.csi] = channel;
++
++ /*SMFC setting*/
++ if (params->csi_mem.mipi_en) {
++ ipu_conf |= (1 << (IPU_CONF_CSI0_DATA_SOURCE_OFFSET +
++ params->csi_mem.csi));
++ _ipu_smfc_init(ipu, channel, params->csi_mem.mipi_vc,
++ params->csi_mem.csi);
++ _ipu_csi_set_mipi_di(ipu, params->csi_mem.mipi_vc,
++ params->csi_mem.mipi_id, params->csi_mem.csi);
++ } else {
++ ipu_conf &= ~(1 << (IPU_CONF_CSI0_DATA_SOURCE_OFFSET +
++ params->csi_mem.csi));
++ _ipu_smfc_init(ipu, channel, 0, params->csi_mem.csi);
++ }
++
++ /*CSI data (include compander) dest*/
++ _ipu_csi_init(ipu, channel, params->csi_mem.csi);
++ break;
++ case CSI_PRP_ENC_MEM:
++ if (params->csi_prp_enc_mem.csi > 1) {
++ ret = -EINVAL;
++ goto err;
++ }
++ if ((ipu->using_ic_dirct_ch == MEM_VDI_PRP_VF_MEM) ||
++ (ipu->using_ic_dirct_ch == MEM_VDI_MEM)) {
++ ret = -EINVAL;
++ goto err;
++ }
++ ipu->using_ic_dirct_ch = CSI_PRP_ENC_MEM;
++
++ ipu->ic_use_count++;
++ ipu->csi_channel[params->csi_prp_enc_mem.csi] = channel;
++
++ if (params->csi_prp_enc_mem.mipi_en) {
++ ipu_conf |= (1 << (IPU_CONF_CSI0_DATA_SOURCE_OFFSET +
++ params->csi_prp_enc_mem.csi));
++ _ipu_csi_set_mipi_di(ipu,
++ params->csi_prp_enc_mem.mipi_vc,
++ params->csi_prp_enc_mem.mipi_id,
++ params->csi_prp_enc_mem.csi);
++ } else
++ ipu_conf &= ~(1 << (IPU_CONF_CSI0_DATA_SOURCE_OFFSET +
++ params->csi_prp_enc_mem.csi));
++
++ /*CSI0/1 feed into IC*/
++ ipu_conf &= ~IPU_CONF_IC_INPUT;
++ if (params->csi_prp_enc_mem.csi)
++ ipu_conf |= IPU_CONF_CSI_SEL;
++ else
++ ipu_conf &= ~IPU_CONF_CSI_SEL;
++
++ /*PRP skip buffer in memory, only valid when RWS_EN is true*/
++ reg = ipu_cm_read(ipu, IPU_FS_PROC_FLOW1);
++ ipu_cm_write(ipu, reg & ~FS_ENC_IN_VALID, IPU_FS_PROC_FLOW1);
++
++ /*CSI data (include compander) dest*/
++ _ipu_csi_init(ipu, channel, params->csi_prp_enc_mem.csi);
++ _ipu_ic_init_prpenc(ipu, params, true);
++ break;
++ case CSI_PRP_VF_MEM:
++ if (params->csi_prp_vf_mem.csi > 1) {
++ ret = -EINVAL;
++ goto err;
++ }
++ if ((ipu->using_ic_dirct_ch == MEM_VDI_PRP_VF_MEM) ||
++ (ipu->using_ic_dirct_ch == MEM_VDI_MEM)) {
++ ret = -EINVAL;
++ goto err;
++ }
++ ipu->using_ic_dirct_ch = CSI_PRP_VF_MEM;
++
++ ipu->ic_use_count++;
++ ipu->csi_channel[params->csi_prp_vf_mem.csi] = channel;
++
++ if (params->csi_prp_vf_mem.mipi_en) {
++ ipu_conf |= (1 << (IPU_CONF_CSI0_DATA_SOURCE_OFFSET +
++ params->csi_prp_vf_mem.csi));
++ _ipu_csi_set_mipi_di(ipu,
++ params->csi_prp_vf_mem.mipi_vc,
++ params->csi_prp_vf_mem.mipi_id,
++ params->csi_prp_vf_mem.csi);
++ } else
++ ipu_conf &= ~(1 << (IPU_CONF_CSI0_DATA_SOURCE_OFFSET +
++ params->csi_prp_vf_mem.csi));
++
++ /*CSI0/1 feed into IC*/
++ ipu_conf &= ~IPU_CONF_IC_INPUT;
++ if (params->csi_prp_vf_mem.csi)
++ ipu_conf |= IPU_CONF_CSI_SEL;
++ else
++ ipu_conf &= ~IPU_CONF_CSI_SEL;
++
++ /*PRP skip buffer in memory, only valid when RWS_EN is true*/
++ reg = ipu_cm_read(ipu, IPU_FS_PROC_FLOW1);
++ ipu_cm_write(ipu, reg & ~FS_VF_IN_VALID, IPU_FS_PROC_FLOW1);
++
++ /*CSI data (include compander) dest*/
++ _ipu_csi_init(ipu, channel, params->csi_prp_vf_mem.csi);
++ _ipu_ic_init_prpvf(ipu, params, true);
++ break;
++ case MEM_PRP_VF_MEM:
++ if (params->mem_prp_vf_mem.graphics_combine_en) {
++ sec_dma = channel_2_dma(channel, IPU_GRAPH_IN_BUFFER);
++ in_g_pixel_fmt = params->mem_prp_vf_mem.in_g_pixel_fmt;
++ bad_pixfmt =
++ _ipu_ch_param_bad_alpha_pos(in_g_pixel_fmt);
++
++ if (params->mem_prp_vf_mem.alpha_chan_en) {
++ if (bad_pixfmt) {
++ dev_err(ipu->dev, "bad pixel format "
++ "for graphics plane from "
++ "ch%d\n", sec_dma);
++ ret = -EINVAL;
++ goto err;
++ }
++ ipu->thrd_chan_en[IPU_CHAN_ID(channel)] = true;
++ }
++ ipu->sec_chan_en[IPU_CHAN_ID(channel)] = true;
++ }
++
++ reg = ipu_cm_read(ipu, IPU_FS_PROC_FLOW1);
++ ipu_cm_write(ipu, reg | FS_VF_IN_VALID, IPU_FS_PROC_FLOW1);
++
++ _ipu_ic_init_prpvf(ipu, params, false);
++ ipu->ic_use_count++;
++ break;
++ case MEM_VDI_PRP_VF_MEM:
++ if ((ipu->using_ic_dirct_ch == CSI_PRP_VF_MEM) ||
++ (ipu->using_ic_dirct_ch == MEM_VDI_MEM) ||
++ (ipu->using_ic_dirct_ch == CSI_PRP_ENC_MEM)) {
++ ret = -EINVAL;
++ goto err;
++ }
++ ipu->using_ic_dirct_ch = MEM_VDI_PRP_VF_MEM;
++ ipu->ic_use_count++;
++ ipu->vdi_use_count++;
++ reg = ipu_cm_read(ipu, IPU_FS_PROC_FLOW1);
++ reg &= ~FS_VDI_SRC_SEL_MASK;
++ ipu_cm_write(ipu, reg , IPU_FS_PROC_FLOW1);
++
++ if (params->mem_prp_vf_mem.graphics_combine_en)
++ ipu->sec_chan_en[IPU_CHAN_ID(channel)] = true;
++ _ipu_ic_init_prpvf(ipu, params, false);
++ _ipu_vdi_init(ipu, channel, params);
++ break;
++ case MEM_VDI_PRP_VF_MEM_P:
++ case MEM_VDI_PRP_VF_MEM_N:
++ case MEM_VDI_MEM_P:
++ case MEM_VDI_MEM_N:
++ _ipu_vdi_init(ipu, channel, params);
++ break;
++ case MEM_VDI_MEM:
++ if ((ipu->using_ic_dirct_ch == CSI_PRP_VF_MEM) ||
++ (ipu->using_ic_dirct_ch == MEM_VDI_PRP_VF_MEM) ||
++ (ipu->using_ic_dirct_ch == CSI_PRP_ENC_MEM)) {
++ ret = -EINVAL;
++ goto err;
++ }
++ ipu->using_ic_dirct_ch = MEM_VDI_MEM;
++ ipu->ic_use_count++;
++ ipu->vdi_use_count++;
++ _ipu_vdi_init(ipu, channel, params);
++ break;
++ case MEM_ROT_VF_MEM:
++ ipu->ic_use_count++;
++ ipu->rot_use_count++;
++ _ipu_ic_init_rotate_vf(ipu, params);
++ break;
++ case MEM_PRP_ENC_MEM:
++ ipu->ic_use_count++;
++ reg = ipu_cm_read(ipu, IPU_FS_PROC_FLOW1);
++ ipu_cm_write(ipu, reg | FS_ENC_IN_VALID, IPU_FS_PROC_FLOW1);
++ _ipu_ic_init_prpenc(ipu, params, false);
++ break;
++ case MEM_ROT_ENC_MEM:
++ ipu->ic_use_count++;
++ ipu->rot_use_count++;
++ _ipu_ic_init_rotate_enc(ipu, params);
++ break;
++ case MEM_PP_MEM:
++ if (params->mem_pp_mem.graphics_combine_en) {
++ sec_dma = channel_2_dma(channel, IPU_GRAPH_IN_BUFFER);
++ in_g_pixel_fmt = params->mem_pp_mem.in_g_pixel_fmt;
++ bad_pixfmt =
++ _ipu_ch_param_bad_alpha_pos(in_g_pixel_fmt);
++
++ if (params->mem_pp_mem.alpha_chan_en) {
++ if (bad_pixfmt) {
++ dev_err(ipu->dev, "bad pixel format "
++ "for graphics plane from "
++ "ch%d\n", sec_dma);
++ ret = -EINVAL;
++ goto err;
++ }
++ ipu->thrd_chan_en[IPU_CHAN_ID(channel)] = true;
++ }
++
++ ipu->sec_chan_en[IPU_CHAN_ID(channel)] = true;
++ }
++
++ _ipu_ic_init_pp(ipu, params);
++ ipu->ic_use_count++;
++ break;
++ case MEM_ROT_PP_MEM:
++ _ipu_ic_init_rotate_pp(ipu, params);
++ ipu->ic_use_count++;
++ ipu->rot_use_count++;
++ break;
++ case MEM_DC_SYNC:
++ if (params->mem_dc_sync.di > 1) {
++ ret = -EINVAL;
++ goto err;
++ }
++
++ ipu->dc_di_assignment[1] = params->mem_dc_sync.di;
++ _ipu_dc_init(ipu, 1, params->mem_dc_sync.di,
++ params->mem_dc_sync.interlaced,
++ params->mem_dc_sync.out_pixel_fmt);
++ ipu->di_use_count[params->mem_dc_sync.di]++;
++ ipu->dc_use_count++;
++ ipu->dmfc_use_count++;
++ break;
++ case MEM_BG_SYNC:
++ if (params->mem_dp_bg_sync.di > 1) {
++ ret = -EINVAL;
++ goto err;
++ }
++
++ if (params->mem_dp_bg_sync.alpha_chan_en)
++ ipu->thrd_chan_en[IPU_CHAN_ID(channel)] = true;
++
++ ipu->dc_di_assignment[5] = params->mem_dp_bg_sync.di;
++ _ipu_dp_init(ipu, channel, params->mem_dp_bg_sync.in_pixel_fmt,
++ params->mem_dp_bg_sync.out_pixel_fmt);
++ _ipu_dc_init(ipu, 5, params->mem_dp_bg_sync.di,
++ params->mem_dp_bg_sync.interlaced,
++ params->mem_dp_bg_sync.out_pixel_fmt);
++ ipu->di_use_count[params->mem_dp_bg_sync.di]++;
++ ipu->dc_use_count++;
++ ipu->dp_use_count++;
++ ipu->dmfc_use_count++;
++ break;
++ case MEM_FG_SYNC:
++ _ipu_dp_init(ipu, channel, params->mem_dp_fg_sync.in_pixel_fmt,
++ params->mem_dp_fg_sync.out_pixel_fmt);
++
++ if (params->mem_dp_fg_sync.alpha_chan_en)
++ ipu->thrd_chan_en[IPU_CHAN_ID(channel)] = true;
++
++ ipu->dc_use_count++;
++ ipu->dp_use_count++;
++ ipu->dmfc_use_count++;
++ break;
++ case DIRECT_ASYNC0:
++ if (params->direct_async.di > 1) {
++ ret = -EINVAL;
++ goto err;
++ }
++
++ ipu->dc_di_assignment[8] = params->direct_async.di;
++ _ipu_dc_init(ipu, 8, params->direct_async.di, false, IPU_PIX_FMT_GENERIC);
++ ipu->di_use_count[params->direct_async.di]++;
++ ipu->dc_use_count++;
++ break;
++ case DIRECT_ASYNC1:
++ if (params->direct_async.di > 1) {
++ ret = -EINVAL;
++ goto err;
++ }
++
++ ipu->dc_di_assignment[9] = params->direct_async.di;
++ _ipu_dc_init(ipu, 9, params->direct_async.di, false, IPU_PIX_FMT_GENERIC);
++ ipu->di_use_count[params->direct_async.di]++;
++ ipu->dc_use_count++;
++ break;
++ default:
++ dev_err(ipu->dev, "Missing channel initialization\n");
++ break;
++ }
++
++ ipu->channel_init_mask |= 1L << IPU_CHAN_ID(channel);
++
++ ipu_cm_write(ipu, ipu_conf, IPU_CONF);
++
++err:
++ mutex_unlock(&ipu->mutex_lock);
++ return ret;
++}
++EXPORT_SYMBOL(ipu_init_channel);
++
++/*!
++ * This function is called to uninitialize a logical IPU channel.
++ *
++ * @param ipu ipu handler
++ * @param channel Input parameter for the logical channel ID to uninit.
++ */
++void ipu_uninit_channel(struct ipu_soc *ipu, ipu_channel_t channel)
++{
++ uint32_t reg;
++ uint32_t in_dma, out_dma = 0;
++ uint32_t ipu_conf;
++ uint32_t dc_chan = 0;
++ int ret;
++
++ mutex_lock(&ipu->mutex_lock);
++
++ if ((ipu->channel_init_mask & (1L << IPU_CHAN_ID(channel))) == 0) {
++ dev_dbg(ipu->dev, "Channel already uninitialized %d\n",
++ IPU_CHAN_ID(channel));
++ mutex_unlock(&ipu->mutex_lock);
++ return;
++ }
++
++ /* Make sure channel is disabled */
++ /* Get input and output dma channels */
++ in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
++ out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
++
++ if (idma_is_set(ipu, IDMAC_CHA_EN, in_dma) ||
++ idma_is_set(ipu, IDMAC_CHA_EN, out_dma)) {
++ dev_err(ipu->dev,
++ "Channel %d is not disabled, disable first\n",
++ IPU_CHAN_ID(channel));
++ mutex_unlock(&ipu->mutex_lock);
++ return;
++ }
++
++ ipu_conf = ipu_cm_read(ipu, IPU_CONF);
++
++ /* Reset the double buffer */
++ reg = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(in_dma));
++ ipu_cm_write(ipu, reg & ~idma_mask(in_dma), IPU_CHA_DB_MODE_SEL(in_dma));
++ reg = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(out_dma));
++ ipu_cm_write(ipu, reg & ~idma_mask(out_dma), IPU_CHA_DB_MODE_SEL(out_dma));
++
++ /* Reset the triple buffer */
++ reg = ipu_cm_read(ipu, IPU_CHA_TRB_MODE_SEL(in_dma));
++ ipu_cm_write(ipu, reg & ~idma_mask(in_dma), IPU_CHA_TRB_MODE_SEL(in_dma));
++ reg = ipu_cm_read(ipu, IPU_CHA_TRB_MODE_SEL(out_dma));
++ ipu_cm_write(ipu, reg & ~idma_mask(out_dma), IPU_CHA_TRB_MODE_SEL(out_dma));
++
++ if (_ipu_is_ic_chan(in_dma) || _ipu_is_dp_graphic_chan(in_dma)) {
++ ipu->sec_chan_en[IPU_CHAN_ID(channel)] = false;
++ ipu->thrd_chan_en[IPU_CHAN_ID(channel)] = false;
++ }
++
++ switch (channel) {
++ case CSI_MEM0:
++ case CSI_MEM1:
++ case CSI_MEM2:
++ case CSI_MEM3:
++ ipu->smfc_use_count--;
++ if (ipu->csi_channel[0] == channel) {
++ ipu->csi_channel[0] = CHAN_NONE;
++ } else if (ipu->csi_channel[1] == channel) {
++ ipu->csi_channel[1] = CHAN_NONE;
++ }
++ break;
++ case CSI_PRP_ENC_MEM:
++ ipu->ic_use_count--;
++ if (ipu->using_ic_dirct_ch == CSI_PRP_ENC_MEM)
++ ipu->using_ic_dirct_ch = 0;
++ _ipu_ic_uninit_prpenc(ipu);
++ if (ipu->csi_channel[0] == channel) {
++ ipu->csi_channel[0] = CHAN_NONE;
++ } else if (ipu->csi_channel[1] == channel) {
++ ipu->csi_channel[1] = CHAN_NONE;
++ }
++ break;
++ case CSI_PRP_VF_MEM:
++ ipu->ic_use_count--;
++ if (ipu->using_ic_dirct_ch == CSI_PRP_VF_MEM)
++ ipu->using_ic_dirct_ch = 0;
++ _ipu_ic_uninit_prpvf(ipu);
++ if (ipu->csi_channel[0] == channel) {
++ ipu->csi_channel[0] = CHAN_NONE;
++ } else if (ipu->csi_channel[1] == channel) {
++ ipu->csi_channel[1] = CHAN_NONE;
++ }
++ break;
++ case MEM_PRP_VF_MEM:
++ ipu->ic_use_count--;
++ _ipu_ic_uninit_prpvf(ipu);
++ reg = ipu_cm_read(ipu, IPU_FS_PROC_FLOW1);
++ ipu_cm_write(ipu, reg & ~FS_VF_IN_VALID, IPU_FS_PROC_FLOW1);
++ break;
++ case MEM_VDI_PRP_VF_MEM:
++ ipu->ic_use_count--;
++ ipu->vdi_use_count--;
++ if (ipu->using_ic_dirct_ch == MEM_VDI_PRP_VF_MEM)
++ ipu->using_ic_dirct_ch = 0;
++ _ipu_ic_uninit_prpvf(ipu);
++ _ipu_vdi_uninit(ipu);
++ reg = ipu_cm_read(ipu, IPU_FS_PROC_FLOW1);
++ ipu_cm_write(ipu, reg & ~FS_VF_IN_VALID, IPU_FS_PROC_FLOW1);
++ break;
++ case MEM_VDI_MEM:
++ ipu->ic_use_count--;
++ ipu->vdi_use_count--;
++ if (ipu->using_ic_dirct_ch == MEM_VDI_MEM)
++ ipu->using_ic_dirct_ch = 0;
++ _ipu_vdi_uninit(ipu);
++ break;
++ case MEM_VDI_PRP_VF_MEM_P:
++ case MEM_VDI_PRP_VF_MEM_N:
++ case MEM_VDI_MEM_P:
++ case MEM_VDI_MEM_N:
++ break;
++ case MEM_ROT_VF_MEM:
++ ipu->rot_use_count--;
++ ipu->ic_use_count--;
++ _ipu_ic_uninit_rotate_vf(ipu);
++ break;
++ case MEM_PRP_ENC_MEM:
++ ipu->ic_use_count--;
++ _ipu_ic_uninit_prpenc(ipu);
++ reg = ipu_cm_read(ipu, IPU_FS_PROC_FLOW1);
++ ipu_cm_write(ipu, reg & ~FS_ENC_IN_VALID, IPU_FS_PROC_FLOW1);
++ break;
++ case MEM_ROT_ENC_MEM:
++ ipu->rot_use_count--;
++ ipu->ic_use_count--;
++ _ipu_ic_uninit_rotate_enc(ipu);
++ break;
++ case MEM_PP_MEM:
++ ipu->ic_use_count--;
++ _ipu_ic_uninit_pp(ipu);
++ break;
++ case MEM_ROT_PP_MEM:
++ ipu->rot_use_count--;
++ ipu->ic_use_count--;
++ _ipu_ic_uninit_rotate_pp(ipu);
++ break;
++ case MEM_DC_SYNC:
++ dc_chan = 1;
++ _ipu_dc_uninit(ipu, 1);
++ ipu->di_use_count[ipu->dc_di_assignment[1]]--;
++ ipu->dc_use_count--;
++ ipu->dmfc_use_count--;
++ break;
++ case MEM_BG_SYNC:
++ dc_chan = 5;
++ _ipu_dp_uninit(ipu, channel);
++ _ipu_dc_uninit(ipu, 5);
++ ipu->di_use_count[ipu->dc_di_assignment[5]]--;
++ ipu->dc_use_count--;
++ ipu->dp_use_count--;
++ ipu->dmfc_use_count--;
++ break;
++ case MEM_FG_SYNC:
++ _ipu_dp_uninit(ipu, channel);
++ ipu->dc_use_count--;
++ ipu->dp_use_count--;
++ ipu->dmfc_use_count--;
++ break;
++ case DIRECT_ASYNC0:
++ dc_chan = 8;
++ _ipu_dc_uninit(ipu, 8);
++ ipu->di_use_count[ipu->dc_di_assignment[8]]--;
++ ipu->dc_use_count--;
++ break;
++ case DIRECT_ASYNC1:
++ dc_chan = 9;
++ _ipu_dc_uninit(ipu, 9);
++ ipu->di_use_count[ipu->dc_di_assignment[9]]--;
++ ipu->dc_use_count--;
++ break;
++ default:
++ break;
++ }
++
++ if (ipu->ic_use_count == 0)
++ ipu_conf &= ~IPU_CONF_IC_EN;
++ if (ipu->vdi_use_count == 0) {
++ ipu_conf &= ~IPU_CONF_ISP_EN;
++ ipu_conf &= ~IPU_CONF_VDI_EN;
++ ipu_conf &= ~IPU_CONF_IC_INPUT;
++ }
++ if (ipu->rot_use_count == 0)
++ ipu_conf &= ~IPU_CONF_ROT_EN;
++ if (ipu->dc_use_count == 0)
++ ipu_conf &= ~IPU_CONF_DC_EN;
++ if (ipu->dp_use_count == 0)
++ ipu_conf &= ~IPU_CONF_DP_EN;
++ if (ipu->dmfc_use_count == 0)
++ ipu_conf &= ~IPU_CONF_DMFC_EN;
++ if (ipu->di_use_count[0] == 0) {
++ ipu_conf &= ~IPU_CONF_DI0_EN;
++ }
++ if (ipu->di_use_count[1] == 0) {
++ ipu_conf &= ~IPU_CONF_DI1_EN;
++ }
++ if (ipu->smfc_use_count == 0)
++ ipu_conf &= ~IPU_CONF_SMFC_EN;
++
++ ipu_cm_write(ipu, ipu_conf, IPU_CONF);
++
++ ipu->channel_init_mask &= ~(1L << IPU_CHAN_ID(channel));
++
++ /*
++ * Disable pixel clk and its parent clock(if the parent clock
++ * usecount is 1) after clearing DC/DP/DI bits in IPU_CONF
++ * register to prevent LVDS display channel starvation.
++ */
++ if (_ipu_is_primary_disp_chan(in_dma))
++ clk_disable_unprepare(ipu->pixel_clk[ipu->dc_di_assignment[dc_chan]]);
++
++ mutex_unlock(&ipu->mutex_lock);
++
++ _ipu_put(ipu);
++
++ ret = pm_runtime_put_sync_suspend(ipu->dev);
++ if (ret < 0) {
++ dev_err(ipu->dev, "ch = %d, pm_runtime_put failed:%d!\n",
++ IPU_CHAN_ID(channel), ret);
++ dump_stack();
++ }
++
++ WARN_ON(ipu->ic_use_count < 0);
++ WARN_ON(ipu->vdi_use_count < 0);
++ WARN_ON(ipu->rot_use_count < 0);
++ WARN_ON(ipu->dc_use_count < 0);
++ WARN_ON(ipu->dp_use_count < 0);
++ WARN_ON(ipu->dmfc_use_count < 0);
++ WARN_ON(ipu->smfc_use_count < 0);
++}
++EXPORT_SYMBOL(ipu_uninit_channel);
++
++/*!
++ * This function is called to initialize buffer(s) for logical IPU channel.
++ *
++ * @param ipu ipu handler
++ *
++ * @param channel Input parameter for the logical channel ID.
++ *
++ * @param type Input parameter which buffer to initialize.
++ *
++ * @param pixel_fmt Input parameter for pixel format of buffer.
++ * Pixel format is a FOURCC ASCII code.
++ *
++ * @param width Input parameter for width of buffer in pixels.
++ *
++ * @param height Input parameter for height of buffer in pixels.
++ *
++ * @param stride Input parameter for stride length of buffer
++ * in pixels.
++ *
++ * @param rot_mode Input parameter for rotation setting of buffer.
++ * A rotation setting other than
++ * IPU_ROTATE_VERT_FLIP
++ * should only be used for input buffers of
++ * rotation channels.
++ *
++ * @param phyaddr_0 Input parameter buffer 0 physical address.
++ *
++ * @param phyaddr_1 Input parameter buffer 1 physical address.
++ * Setting this to a value other than NULL enables
++ * double buffering mode.
++ *
++ * @param phyaddr_2 Input parameter buffer 2 physical address.
++ * Setting this to a value other than NULL enables
++ * triple buffering mode, phyaddr_1 should not be
++ * NULL then.
++ *
++ * @param u private u offset for additional cropping,
++ * zero if not used.
++ *
++ * @param v private v offset for additional cropping,
++ * zero if not used.
++ *
++ * @return Returns 0 on success or negative error code on fail
++ */
++int32_t ipu_init_channel_buffer(struct ipu_soc *ipu, ipu_channel_t channel,
++ ipu_buffer_t type,
++ uint32_t pixel_fmt,
++ uint16_t width, uint16_t height,
++ uint32_t stride,
++ ipu_rotate_mode_t rot_mode,
++ dma_addr_t phyaddr_0, dma_addr_t phyaddr_1,
++ dma_addr_t phyaddr_2,
++ uint32_t u, uint32_t v)
++{
++ uint32_t reg;
++ uint32_t dma_chan;
++ uint32_t burst_size;
++
++ dma_chan = channel_2_dma(channel, type);
++ if (!idma_is_valid(dma_chan))
++ return -EINVAL;
++
++ if (stride < width * bytes_per_pixel(pixel_fmt))
++ stride = width * bytes_per_pixel(pixel_fmt);
++
++ if (stride % 4) {
++ dev_err(ipu->dev,
++ "Stride not 32-bit aligned, stride = %d\n", stride);
++ return -EINVAL;
++ }
++ /* IC & IRT channels' width must be multiple of 8 pixels */
++ if ((_ipu_is_ic_chan(dma_chan) || _ipu_is_irt_chan(dma_chan))
++ && (width % 8)) {
++ dev_err(ipu->dev, "Width must be 8 pixel multiple\n");
++ return -EINVAL;
++ }
++
++ if (_ipu_is_vdi_out_chan(dma_chan) &&
++ ((width < 16) || (height < 16) || (width % 2) || (height % 4))) {
++ dev_err(ipu->dev, "vdi width/height limited err\n");
++ return -EINVAL;
++ }
++
++ /* IPUv3EX and IPUv3M support triple buffer */
++ if ((!_ipu_is_trb_chan(dma_chan)) && phyaddr_2) {
++ dev_err(ipu->dev, "Chan%d doesn't support triple buffer "
++ "mode\n", dma_chan);
++ return -EINVAL;
++ }
++ if (!phyaddr_1 && phyaddr_2) {
++ dev_err(ipu->dev, "Chan%d's buf1 physical addr is NULL for "
++ "triple buffer mode\n", dma_chan);
++ return -EINVAL;
++ }
++
++ mutex_lock(&ipu->mutex_lock);
++
++ /* Build parameter memory data for DMA channel */
++ _ipu_ch_param_init(ipu, dma_chan, pixel_fmt, width, height, stride, u, v, 0,
++ phyaddr_0, phyaddr_1, phyaddr_2);
++
++ /* Set correlative channel parameter of local alpha channel */
++ if ((_ipu_is_ic_graphic_chan(dma_chan) ||
++ _ipu_is_dp_graphic_chan(dma_chan)) &&
++ (ipu->thrd_chan_en[IPU_CHAN_ID(channel)] == true)) {
++ _ipu_ch_param_set_alpha_use_separate_channel(ipu, dma_chan, true);
++ _ipu_ch_param_set_alpha_buffer_memory(ipu, dma_chan);
++ _ipu_ch_param_set_alpha_condition_read(ipu, dma_chan);
++ /* fix alpha width as 8 and burst size as 16*/
++ _ipu_ch_params_set_alpha_width(ipu, dma_chan, 8);
++ _ipu_ch_param_set_burst_size(ipu, dma_chan, 16);
++ } else if (_ipu_is_ic_graphic_chan(dma_chan) &&
++ ipu_pixel_format_has_alpha(pixel_fmt))
++ _ipu_ch_param_set_alpha_use_separate_channel(ipu, dma_chan, false);
++
++ if (rot_mode)
++ _ipu_ch_param_set_rotation(ipu, dma_chan, rot_mode);
++
++ /* IC and ROT channels have restriction of 8 or 16 pix burst length */
++ if (_ipu_is_ic_chan(dma_chan) || _ipu_is_vdi_out_chan(dma_chan)) {
++ if ((width % 16) == 0)
++ _ipu_ch_param_set_burst_size(ipu, dma_chan, 16);
++ else
++ _ipu_ch_param_set_burst_size(ipu, dma_chan, 8);
++ } else if (_ipu_is_irt_chan(dma_chan)) {
++ _ipu_ch_param_set_burst_size(ipu, dma_chan, 8);
++ _ipu_ch_param_set_block_mode(ipu, dma_chan);
++ } else if (_ipu_is_dmfc_chan(dma_chan)) {
++ burst_size = _ipu_ch_param_get_burst_size(ipu, dma_chan);
++ _ipu_dmfc_set_wait4eot(ipu, dma_chan, width);
++ _ipu_dmfc_set_burst_size(ipu, dma_chan, burst_size);
++ }
++
++ if (_ipu_disp_chan_is_interlaced(ipu, channel) ||
++ ipu->chan_is_interlaced[dma_chan])
++ _ipu_ch_param_set_interlaced_scan(ipu, dma_chan);
++
++ if (_ipu_is_ic_chan(dma_chan) || _ipu_is_irt_chan(dma_chan) ||
++ _ipu_is_vdi_out_chan(dma_chan)) {
++ burst_size = _ipu_ch_param_get_burst_size(ipu, dma_chan);
++ _ipu_ic_idma_init(ipu, dma_chan, width, height, burst_size,
++ rot_mode);
++ } else if (_ipu_is_smfc_chan(dma_chan)) {
++ burst_size = _ipu_ch_param_get_burst_size(ipu, dma_chan);
++ /*
++ * This is different from IPUv3 spec, but it is confirmed
++ * in IPUforum that SMFC burst size should be NPB[6:3]
++ * when IDMAC works in 16-bit generic data mode.
++ */
++ if (pixel_fmt == IPU_PIX_FMT_GENERIC)
++ /* 8 bits per pixel */
++ burst_size = burst_size >> 4;
++ else if (pixel_fmt == IPU_PIX_FMT_GENERIC_16)
++ /* 16 bits per pixel */
++ burst_size = burst_size >> 3;
++ else
++ burst_size = burst_size >> 2;
++ _ipu_smfc_set_burst_size(ipu, channel, burst_size-1);
++ }
++
++ /* AXI-id */
++ if (idma_is_set(ipu, IDMAC_CHA_PRI, dma_chan)) {
++ unsigned reg = IDMAC_CH_LOCK_EN_1;
++ uint32_t value = 0;
++ if (ipu->pdata->devtype == IPU_V3H) {
++ _ipu_ch_param_set_axi_id(ipu, dma_chan, 0);
++ switch (dma_chan) {
++ case 5:
++ value = 0x3;
++ break;
++ case 11:
++ value = 0x3 << 2;
++ break;
++ case 12:
++ value = 0x3 << 4;
++ break;
++ case 14:
++ value = 0x3 << 6;
++ break;
++ case 15:
++ value = 0x3 << 8;
++ break;
++ case 20:
++ value = 0x3 << 10;
++ break;
++ case 21:
++ value = 0x3 << 12;
++ break;
++ case 22:
++ value = 0x3 << 14;
++ break;
++ case 23:
++ value = 0x3 << 16;
++ break;
++ case 27:
++ value = 0x3 << 18;
++ break;
++ case 28:
++ value = 0x3 << 20;
++ break;
++ case 45:
++ reg = IDMAC_CH_LOCK_EN_2;
++ value = 0x3 << 0;
++ break;
++ case 46:
++ reg = IDMAC_CH_LOCK_EN_2;
++ value = 0x3 << 2;
++ break;
++ case 47:
++ reg = IDMAC_CH_LOCK_EN_2;
++ value = 0x3 << 4;
++ break;
++ case 48:
++ reg = IDMAC_CH_LOCK_EN_2;
++ value = 0x3 << 6;
++ break;
++ case 49:
++ reg = IDMAC_CH_LOCK_EN_2;
++ value = 0x3 << 8;
++ break;
++ case 50:
++ reg = IDMAC_CH_LOCK_EN_2;
++ value = 0x3 << 10;
++ break;
++ default:
++ break;
++ }
++ value |= ipu_idmac_read(ipu, reg);
++ ipu_idmac_write(ipu, value, reg);
++ } else
++ _ipu_ch_param_set_axi_id(ipu, dma_chan, 1);
++ } else {
++ if (ipu->pdata->devtype == IPU_V3H)
++ _ipu_ch_param_set_axi_id(ipu, dma_chan, 1);
++ }
++
++ _ipu_ch_param_dump(ipu, dma_chan);
++
++ if (phyaddr_2 && g_ipu_hw_rev >= IPU_V3DEX) {
++ reg = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(dma_chan));
++ reg &= ~idma_mask(dma_chan);
++ ipu_cm_write(ipu, reg, IPU_CHA_DB_MODE_SEL(dma_chan));
++
++ reg = ipu_cm_read(ipu, IPU_CHA_TRB_MODE_SEL(dma_chan));
++ reg |= idma_mask(dma_chan);
++ ipu_cm_write(ipu, reg, IPU_CHA_TRB_MODE_SEL(dma_chan));
++
++ /* Set IDMAC third buffer's cpmem number */
++ /* See __ipu_ch_get_third_buf_cpmem_num() for mapping */
++ ipu_idmac_write(ipu, 0x00444047L, IDMAC_SUB_ADDR_4);
++ ipu_idmac_write(ipu, 0x46004241L, IDMAC_SUB_ADDR_3);
++ ipu_idmac_write(ipu, 0x00000045L, IDMAC_SUB_ADDR_1);
++
++ /* Reset to buffer 0 */
++ ipu_cm_write(ipu, tri_cur_buf_mask(dma_chan),
++ IPU_CHA_TRIPLE_CUR_BUF(dma_chan));
++ } else {
++ reg = ipu_cm_read(ipu, IPU_CHA_TRB_MODE_SEL(dma_chan));
++ reg &= ~idma_mask(dma_chan);
++ ipu_cm_write(ipu, reg, IPU_CHA_TRB_MODE_SEL(dma_chan));
++
++ reg = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(dma_chan));
++ if (phyaddr_1)
++ reg |= idma_mask(dma_chan);
++ else
++ reg &= ~idma_mask(dma_chan);
++ ipu_cm_write(ipu, reg, IPU_CHA_DB_MODE_SEL(dma_chan));
++
++ /* Reset to buffer 0 */
++ ipu_cm_write(ipu, idma_mask(dma_chan),
++ IPU_CHA_CUR_BUF(dma_chan));
++
++ }
++
++ mutex_unlock(&ipu->mutex_lock);
++
++ return 0;
++}
++EXPORT_SYMBOL(ipu_init_channel_buffer);
++
++/*!
++ * This function is called to update the physical address of a buffer for
++ * a logical IPU channel.
++ *
++ * @param ipu ipu handler
++ * @param channel Input parameter for the logical channel ID.
++ *
++ * @param type Input parameter which buffer to initialize.
++ *
++ * @param bufNum Input parameter for buffer number to update.
++ * 0 or 1 are the only valid values.
++ *
++ * @param phyaddr Input parameter buffer physical address.
++ *
++ * @return This function returns 0 on success or negative error code on
++ * fail. This function will fail if the buffer is set to ready.
++ */
++int32_t ipu_update_channel_buffer(struct ipu_soc *ipu, ipu_channel_t channel,
++ ipu_buffer_t type, uint32_t bufNum, dma_addr_t phyaddr)
++{
++ uint32_t reg;
++ int ret = 0;
++ uint32_t dma_chan = channel_2_dma(channel, type);
++ unsigned long lock_flags;
++
++ if (dma_chan == IDMA_CHAN_INVALID)
++ return -EINVAL;
++
++ spin_lock_irqsave(&ipu->rdy_reg_spin_lock, lock_flags);
++ if (bufNum == 0)
++ reg = ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(dma_chan));
++ else if (bufNum == 1)
++ reg = ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(dma_chan));
++ else
++ reg = ipu_cm_read(ipu, IPU_CHA_BUF2_RDY(dma_chan));
++
++ if ((reg & idma_mask(dma_chan)) == 0)
++ _ipu_ch_param_set_buffer(ipu, dma_chan, bufNum, phyaddr);
++ else
++ ret = -EACCES;
++ spin_unlock_irqrestore(&ipu->rdy_reg_spin_lock, lock_flags);
++
++ return ret;
++}
++EXPORT_SYMBOL(ipu_update_channel_buffer);
++
++/*!
++ * This function is called to update the band mode setting for
++ * a logical IPU channel.
++ *
++ * @param ipu ipu handler
++ *
++ * @param channel Input parameter for the logical channel ID.
++ *
++ * @param type Input parameter which buffer to initialize.
++ *
++ * @param band_height Input parameter for band lines:
++ * shoule be log2(4/8/16/32/64/128/256).
++ *
++ * @return This function returns 0 on success or negative error code on
++ * fail.
++ */
++int32_t ipu_set_channel_bandmode(struct ipu_soc *ipu, ipu_channel_t channel,
++ ipu_buffer_t type, uint32_t band_height)
++{
++ uint32_t reg;
++ int ret = 0;
++ uint32_t dma_chan = channel_2_dma(channel, type);
++
++ if ((2 > band_height) || (8 < band_height))
++ return -EINVAL;
++
++ mutex_lock(&ipu->mutex_lock);
++
++ reg = ipu_idmac_read(ipu, IDMAC_BAND_EN(dma_chan));
++ reg |= 1 << (dma_chan % 32);
++ ipu_idmac_write(ipu, reg, IDMAC_BAND_EN(dma_chan));
++
++ _ipu_ch_param_set_bandmode(ipu, dma_chan, band_height);
++ dev_dbg(ipu->dev, "dma_chan:%d, band_height:%d.\n\n",
++ dma_chan, 1 << band_height);
++ mutex_unlock(&ipu->mutex_lock);
++
++ return ret;
++}
++EXPORT_SYMBOL(ipu_set_channel_bandmode);
++
++/*!
++ * This function is called to initialize a buffer for logical IPU channel.
++ *
++ * @param ipu ipu handler
++ * @param channel Input parameter for the logical channel ID.
++ *
++ * @param type Input parameter which buffer to initialize.
++ *
++ * @param pixel_fmt Input parameter for pixel format of buffer.
++ * Pixel format is a FOURCC ASCII code.
++ *
++ * @param width Input parameter for width of buffer in pixels.
++ *
++ * @param height Input parameter for height of buffer in pixels.
++ *
++ * @param stride Input parameter for stride length of buffer
++ * in pixels.
++ *
++ * @param u predefined private u offset for additional cropping,
++ * zero if not used.
++ *
++ * @param v predefined private v offset for additional cropping,
++ * zero if not used.
++ *
++ * @param vertical_offset vertical offset for Y coordinate
++ * in the existed frame
++ *
++ *
++ * @param horizontal_offset horizontal offset for X coordinate
++ * in the existed frame
++ *
++ *
++ * @return Returns 0 on success or negative error code on fail
++ * This function will fail if any buffer is set to ready.
++ */
++
++int32_t ipu_update_channel_offset(struct ipu_soc *ipu,
++ ipu_channel_t channel, ipu_buffer_t type,
++ uint32_t pixel_fmt,
++ uint16_t width, uint16_t height,
++ uint32_t stride,
++ uint32_t u, uint32_t v,
++ uint32_t vertical_offset, uint32_t horizontal_offset)
++{
++ int ret = 0;
++ uint32_t dma_chan = channel_2_dma(channel, type);
++ unsigned long lock_flags;
++
++ if (dma_chan == IDMA_CHAN_INVALID)
++ return -EINVAL;
++
++ spin_lock_irqsave(&ipu->rdy_reg_spin_lock, lock_flags);
++ if ((ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(dma_chan)) & idma_mask(dma_chan)) ||
++ (ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(dma_chan)) & idma_mask(dma_chan)) ||
++ ((ipu_cm_read(ipu, IPU_CHA_BUF2_RDY(dma_chan)) & idma_mask(dma_chan)) &&
++ (ipu_cm_read(ipu, IPU_CHA_TRB_MODE_SEL(dma_chan)) & idma_mask(dma_chan)) &&
++ _ipu_is_trb_chan(dma_chan)))
++ ret = -EACCES;
++ else
++ _ipu_ch_offset_update(ipu, dma_chan, pixel_fmt, width, height, stride,
++ u, v, 0, vertical_offset, horizontal_offset);
++ spin_unlock_irqrestore(&ipu->rdy_reg_spin_lock, lock_flags);
++
++ return ret;
++}
++EXPORT_SYMBOL(ipu_update_channel_offset);
++
++
++/*!
++ * This function is called to set a channel's buffer as ready.
++ *
++ * @param ipu ipu handler
++ * @param channel Input parameter for the logical channel ID.
++ *
++ * @param type Input parameter which buffer to initialize.
++ *
++ * @param bufNum Input parameter for which buffer number set to
++ * ready state.
++ *
++ * @return Returns 0 on success or negative error code on fail
++ */
++int32_t ipu_select_buffer(struct ipu_soc *ipu, ipu_channel_t channel,
++ ipu_buffer_t type, uint32_t bufNum)
++{
++ uint32_t dma_chan = channel_2_dma(channel, type);
++ unsigned long lock_flags;
++
++ if (dma_chan == IDMA_CHAN_INVALID)
++ return -EINVAL;
++
++ spin_lock_irqsave(&ipu->rdy_reg_spin_lock, lock_flags);
++ /* Mark buffer to be ready. */
++ if (bufNum == 0)
++ ipu_cm_write(ipu, idma_mask(dma_chan),
++ IPU_CHA_BUF0_RDY(dma_chan));
++ else if (bufNum == 1)
++ ipu_cm_write(ipu, idma_mask(dma_chan),
++ IPU_CHA_BUF1_RDY(dma_chan));
++ else
++ ipu_cm_write(ipu, idma_mask(dma_chan),
++ IPU_CHA_BUF2_RDY(dma_chan));
++ spin_unlock_irqrestore(&ipu->rdy_reg_spin_lock, lock_flags);
++
++ return 0;
++}
++EXPORT_SYMBOL(ipu_select_buffer);
++
++/*!
++ * This function is called to set a channel's buffer as ready.
++ *
++ * @param ipu ipu handler
++ * @param bufNum Input parameter for which buffer number set to
++ * ready state.
++ *
++ * @return Returns 0 on success or negative error code on fail
++ */
++int32_t ipu_select_multi_vdi_buffer(struct ipu_soc *ipu, uint32_t bufNum)
++{
++
++ uint32_t dma_chan = channel_2_dma(MEM_VDI_PRP_VF_MEM, IPU_INPUT_BUFFER);
++ uint32_t mask_bit =
++ idma_mask(channel_2_dma(MEM_VDI_PRP_VF_MEM_P, IPU_INPUT_BUFFER))|
++ idma_mask(dma_chan)|
++ idma_mask(channel_2_dma(MEM_VDI_PRP_VF_MEM_N, IPU_INPUT_BUFFER));
++ unsigned long lock_flags;
++
++ spin_lock_irqsave(&ipu->rdy_reg_spin_lock, lock_flags);
++ /* Mark buffers to be ready. */
++ if (bufNum == 0)
++ ipu_cm_write(ipu, mask_bit, IPU_CHA_BUF0_RDY(dma_chan));
++ else
++ ipu_cm_write(ipu, mask_bit, IPU_CHA_BUF1_RDY(dma_chan));
++ spin_unlock_irqrestore(&ipu->rdy_reg_spin_lock, lock_flags);
++
++ return 0;
++}
++EXPORT_SYMBOL(ipu_select_multi_vdi_buffer);
++
++#define NA -1
++static int proc_dest_sel[] = {
++ 0, 1, 1, 3, 5, 5, 4, 7, 8, 9, 10, 11, 12, 14, 15, 16,
++ 0, 1, 1, 5, 5, 5, 5, 5, 7, 8, 9, 10, 11, 12, 14, 31 };
++static int proc_src_sel[] = { 0, 6, 7, 6, 7, 8, 5, NA, NA, NA,
++ NA, NA, NA, NA, NA, 1, 2, 3, 4, 7, 8, NA, 8, NA };
++static int disp_src_sel[] = { 0, 6, 7, 8, 3, 4, 5, NA, NA, NA,
++ NA, NA, NA, NA, NA, 1, NA, 2, NA, 3, 4, 4, 4, 4 };
++
++
++/*!
++ * This function links 2 channels together for automatic frame
++ * synchronization. The output of the source channel is linked to the input of
++ * the destination channel.
++ *
++ * @param ipu ipu handler
++ * @param src_ch Input parameter for the logical channel ID of
++ * the source channel.
++ *
++ * @param dest_ch Input parameter for the logical channel ID of
++ * the destination channel.
++ *
++ * @return This function returns 0 on success or negative error code on
++ * fail.
++ */
++int32_t ipu_link_channels(struct ipu_soc *ipu, ipu_channel_t src_ch, ipu_channel_t dest_ch)
++{
++ int retval = 0;
++ uint32_t fs_proc_flow1;
++ uint32_t fs_proc_flow2;
++ uint32_t fs_proc_flow3;
++ uint32_t fs_disp_flow1;
++
++ mutex_lock(&ipu->mutex_lock);
++
++ fs_proc_flow1 = ipu_cm_read(ipu, IPU_FS_PROC_FLOW1);
++ fs_proc_flow2 = ipu_cm_read(ipu, IPU_FS_PROC_FLOW2);
++ fs_proc_flow3 = ipu_cm_read(ipu, IPU_FS_PROC_FLOW3);
++ fs_disp_flow1 = ipu_cm_read(ipu, IPU_FS_DISP_FLOW1);
++
++ switch (src_ch) {
++ case CSI_MEM0:
++ fs_proc_flow3 &= ~FS_SMFC0_DEST_SEL_MASK;
++ fs_proc_flow3 |=
++ proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
++ FS_SMFC0_DEST_SEL_OFFSET;
++ break;
++ case CSI_MEM1:
++ fs_proc_flow3 &= ~FS_SMFC1_DEST_SEL_MASK;
++ fs_proc_flow3 |=
++ proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
++ FS_SMFC1_DEST_SEL_OFFSET;
++ break;
++ case CSI_MEM2:
++ fs_proc_flow3 &= ~FS_SMFC2_DEST_SEL_MASK;
++ fs_proc_flow3 |=
++ proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
++ FS_SMFC2_DEST_SEL_OFFSET;
++ break;
++ case CSI_MEM3:
++ fs_proc_flow3 &= ~FS_SMFC3_DEST_SEL_MASK;
++ fs_proc_flow3 |=
++ proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
++ FS_SMFC3_DEST_SEL_OFFSET;
++ break;
++ case CSI_PRP_ENC_MEM:
++ fs_proc_flow2 &= ~FS_PRPENC_DEST_SEL_MASK;
++ fs_proc_flow2 |=
++ proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
++ FS_PRPENC_DEST_SEL_OFFSET;
++ break;
++ case CSI_PRP_VF_MEM:
++ fs_proc_flow2 &= ~FS_PRPVF_DEST_SEL_MASK;
++ fs_proc_flow2 |=
++ proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
++ FS_PRPVF_DEST_SEL_OFFSET;
++ break;
++ case MEM_PP_MEM:
++ fs_proc_flow2 &= ~FS_PP_DEST_SEL_MASK;
++ fs_proc_flow2 |=
++ proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
++ FS_PP_DEST_SEL_OFFSET;
++ break;
++ case MEM_ROT_PP_MEM:
++ fs_proc_flow2 &= ~FS_PP_ROT_DEST_SEL_MASK;
++ fs_proc_flow2 |=
++ proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
++ FS_PP_ROT_DEST_SEL_OFFSET;
++ break;
++ case MEM_PRP_ENC_MEM:
++ fs_proc_flow2 &= ~FS_PRPENC_DEST_SEL_MASK;
++ fs_proc_flow2 |=
++ proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
++ FS_PRPENC_DEST_SEL_OFFSET;
++ break;
++ case MEM_ROT_ENC_MEM:
++ fs_proc_flow2 &= ~FS_PRPENC_ROT_DEST_SEL_MASK;
++ fs_proc_flow2 |=
++ proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
++ FS_PRPENC_ROT_DEST_SEL_OFFSET;
++ break;
++ case MEM_PRP_VF_MEM:
++ fs_proc_flow2 &= ~FS_PRPVF_DEST_SEL_MASK;
++ fs_proc_flow2 |=
++ proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
++ FS_PRPVF_DEST_SEL_OFFSET;
++ break;
++ case MEM_VDI_PRP_VF_MEM:
++ fs_proc_flow2 &= ~FS_PRPVF_DEST_SEL_MASK;
++ fs_proc_flow2 |=
++ proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
++ FS_PRPVF_DEST_SEL_OFFSET;
++ break;
++ case MEM_ROT_VF_MEM:
++ fs_proc_flow2 &= ~FS_PRPVF_ROT_DEST_SEL_MASK;
++ fs_proc_flow2 |=
++ proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
++ FS_PRPVF_ROT_DEST_SEL_OFFSET;
++ break;
++ case MEM_VDOA_MEM:
++ fs_proc_flow3 &= ~FS_VDOA_DEST_SEL_MASK;
++ if (MEM_VDI_MEM == dest_ch)
++ fs_proc_flow3 |= FS_VDOA_DEST_SEL_VDI;
++ else if (MEM_PP_MEM == dest_ch)
++ fs_proc_flow3 |= FS_VDOA_DEST_SEL_IC;
++ else {
++ retval = -EINVAL;
++ goto err;
++ }
++ break;
++ default:
++ retval = -EINVAL;
++ goto err;
++ }
++
++ switch (dest_ch) {
++ case MEM_PP_MEM:
++ fs_proc_flow1 &= ~FS_PP_SRC_SEL_MASK;
++ if (MEM_VDOA_MEM == src_ch)
++ fs_proc_flow1 |= FS_PP_SRC_SEL_VDOA;
++ else
++ fs_proc_flow1 |= proc_src_sel[IPU_CHAN_ID(src_ch)] <<
++ FS_PP_SRC_SEL_OFFSET;
++ break;
++ case MEM_ROT_PP_MEM:
++ fs_proc_flow1 &= ~FS_PP_ROT_SRC_SEL_MASK;
++ fs_proc_flow1 |=
++ proc_src_sel[IPU_CHAN_ID(src_ch)] <<
++ FS_PP_ROT_SRC_SEL_OFFSET;
++ break;
++ case MEM_PRP_ENC_MEM:
++ fs_proc_flow1 &= ~FS_PRP_SRC_SEL_MASK;
++ fs_proc_flow1 |=
++ proc_src_sel[IPU_CHAN_ID(src_ch)] << FS_PRP_SRC_SEL_OFFSET;
++ break;
++ case MEM_ROT_ENC_MEM:
++ fs_proc_flow1 &= ~FS_PRPENC_ROT_SRC_SEL_MASK;
++ fs_proc_flow1 |=
++ proc_src_sel[IPU_CHAN_ID(src_ch)] <<
++ FS_PRPENC_ROT_SRC_SEL_OFFSET;
++ break;
++ case MEM_PRP_VF_MEM:
++ fs_proc_flow1 &= ~FS_PRP_SRC_SEL_MASK;
++ fs_proc_flow1 |=
++ proc_src_sel[IPU_CHAN_ID(src_ch)] << FS_PRP_SRC_SEL_OFFSET;
++ break;
++ case MEM_VDI_PRP_VF_MEM:
++ fs_proc_flow1 &= ~FS_PRP_SRC_SEL_MASK;
++ fs_proc_flow1 |=
++ proc_src_sel[IPU_CHAN_ID(src_ch)] << FS_PRP_SRC_SEL_OFFSET;
++ break;
++ case MEM_ROT_VF_MEM:
++ fs_proc_flow1 &= ~FS_PRPVF_ROT_SRC_SEL_MASK;
++ fs_proc_flow1 |=
++ proc_src_sel[IPU_CHAN_ID(src_ch)] <<
++ FS_PRPVF_ROT_SRC_SEL_OFFSET;
++ break;
++ case MEM_DC_SYNC:
++ fs_disp_flow1 &= ~FS_DC1_SRC_SEL_MASK;
++ fs_disp_flow1 |=
++ disp_src_sel[IPU_CHAN_ID(src_ch)] << FS_DC1_SRC_SEL_OFFSET;
++ break;
++ case MEM_BG_SYNC:
++ fs_disp_flow1 &= ~FS_DP_SYNC0_SRC_SEL_MASK;
++ fs_disp_flow1 |=
++ disp_src_sel[IPU_CHAN_ID(src_ch)] <<
++ FS_DP_SYNC0_SRC_SEL_OFFSET;
++ break;
++ case MEM_FG_SYNC:
++ fs_disp_flow1 &= ~FS_DP_SYNC1_SRC_SEL_MASK;
++ fs_disp_flow1 |=
++ disp_src_sel[IPU_CHAN_ID(src_ch)] <<
++ FS_DP_SYNC1_SRC_SEL_OFFSET;
++ break;
++ case MEM_DC_ASYNC:
++ fs_disp_flow1 &= ~FS_DC2_SRC_SEL_MASK;
++ fs_disp_flow1 |=
++ disp_src_sel[IPU_CHAN_ID(src_ch)] << FS_DC2_SRC_SEL_OFFSET;
++ break;
++ case MEM_BG_ASYNC0:
++ fs_disp_flow1 &= ~FS_DP_ASYNC0_SRC_SEL_MASK;
++ fs_disp_flow1 |=
++ disp_src_sel[IPU_CHAN_ID(src_ch)] <<
++ FS_DP_ASYNC0_SRC_SEL_OFFSET;
++ break;
++ case MEM_FG_ASYNC0:
++ fs_disp_flow1 &= ~FS_DP_ASYNC1_SRC_SEL_MASK;
++ fs_disp_flow1 |=
++ disp_src_sel[IPU_CHAN_ID(src_ch)] <<
++ FS_DP_ASYNC1_SRC_SEL_OFFSET;
++ break;
++ case MEM_VDI_MEM:
++ fs_proc_flow1 &= ~FS_VDI_SRC_SEL_MASK;
++ if (MEM_VDOA_MEM == src_ch)
++ fs_proc_flow1 |= FS_VDI_SRC_SEL_VDOA;
++ else {
++ retval = -EINVAL;
++ goto err;
++ }
++ break;
++ default:
++ retval = -EINVAL;
++ goto err;
++ }
++
++ ipu_cm_write(ipu, fs_proc_flow1, IPU_FS_PROC_FLOW1);
++ ipu_cm_write(ipu, fs_proc_flow2, IPU_FS_PROC_FLOW2);
++ ipu_cm_write(ipu, fs_proc_flow3, IPU_FS_PROC_FLOW3);
++ ipu_cm_write(ipu, fs_disp_flow1, IPU_FS_DISP_FLOW1);
++
++err:
++ mutex_unlock(&ipu->mutex_lock);
++ return retval;
++}
++EXPORT_SYMBOL(ipu_link_channels);
++
++/*!
++ * This function unlinks 2 channels and disables automatic frame
++ * synchronization.
++ *
++ * @param ipu ipu handler
++ * @param src_ch Input parameter for the logical channel ID of
++ * the source channel.
++ *
++ * @param dest_ch Input parameter for the logical channel ID of
++ * the destination channel.
++ *
++ * @return This function returns 0 on success or negative error code on
++ * fail.
++ */
++int32_t ipu_unlink_channels(struct ipu_soc *ipu, ipu_channel_t src_ch, ipu_channel_t dest_ch)
++{
++ int retval = 0;
++ uint32_t fs_proc_flow1;
++ uint32_t fs_proc_flow2;
++ uint32_t fs_proc_flow3;
++ uint32_t fs_disp_flow1;
++
++ mutex_lock(&ipu->mutex_lock);
++
++ fs_proc_flow1 = ipu_cm_read(ipu, IPU_FS_PROC_FLOW1);
++ fs_proc_flow2 = ipu_cm_read(ipu, IPU_FS_PROC_FLOW2);
++ fs_proc_flow3 = ipu_cm_read(ipu, IPU_FS_PROC_FLOW3);
++ fs_disp_flow1 = ipu_cm_read(ipu, IPU_FS_DISP_FLOW1);
++
++ switch (src_ch) {
++ case CSI_MEM0:
++ fs_proc_flow3 &= ~FS_SMFC0_DEST_SEL_MASK;
++ break;
++ case CSI_MEM1:
++ fs_proc_flow3 &= ~FS_SMFC1_DEST_SEL_MASK;
++ break;
++ case CSI_MEM2:
++ fs_proc_flow3 &= ~FS_SMFC2_DEST_SEL_MASK;
++ break;
++ case CSI_MEM3:
++ fs_proc_flow3 &= ~FS_SMFC3_DEST_SEL_MASK;
++ break;
++ case CSI_PRP_ENC_MEM:
++ fs_proc_flow2 &= ~FS_PRPENC_DEST_SEL_MASK;
++ break;
++ case CSI_PRP_VF_MEM:
++ fs_proc_flow2 &= ~FS_PRPVF_DEST_SEL_MASK;
++ break;
++ case MEM_PP_MEM:
++ fs_proc_flow2 &= ~FS_PP_DEST_SEL_MASK;
++ break;
++ case MEM_ROT_PP_MEM:
++ fs_proc_flow2 &= ~FS_PP_ROT_DEST_SEL_MASK;
++ break;
++ case MEM_PRP_ENC_MEM:
++ fs_proc_flow2 &= ~FS_PRPENC_DEST_SEL_MASK;
++ break;
++ case MEM_ROT_ENC_MEM:
++ fs_proc_flow2 &= ~FS_PRPENC_ROT_DEST_SEL_MASK;
++ break;
++ case MEM_PRP_VF_MEM:
++ fs_proc_flow2 &= ~FS_PRPVF_DEST_SEL_MASK;
++ break;
++ case MEM_VDI_PRP_VF_MEM:
++ fs_proc_flow2 &= ~FS_PRPVF_DEST_SEL_MASK;
++ break;
++ case MEM_ROT_VF_MEM:
++ fs_proc_flow2 &= ~FS_PRPVF_ROT_DEST_SEL_MASK;
++ break;
++ case MEM_VDOA_MEM:
++ fs_proc_flow3 &= ~FS_VDOA_DEST_SEL_MASK;
++ break;
++ default:
++ retval = -EINVAL;
++ goto err;
++ }
++
++ switch (dest_ch) {
++ case MEM_PP_MEM:
++ fs_proc_flow1 &= ~FS_PP_SRC_SEL_MASK;
++ break;
++ case MEM_ROT_PP_MEM:
++ fs_proc_flow1 &= ~FS_PP_ROT_SRC_SEL_MASK;
++ break;
++ case MEM_PRP_ENC_MEM:
++ fs_proc_flow1 &= ~FS_PRP_SRC_SEL_MASK;
++ break;
++ case MEM_ROT_ENC_MEM:
++ fs_proc_flow1 &= ~FS_PRPENC_ROT_SRC_SEL_MASK;
++ break;
++ case MEM_PRP_VF_MEM:
++ fs_proc_flow1 &= ~FS_PRP_SRC_SEL_MASK;
++ break;
++ case MEM_VDI_PRP_VF_MEM:
++ fs_proc_flow1 &= ~FS_PRP_SRC_SEL_MASK;
++ break;
++ case MEM_ROT_VF_MEM:
++ fs_proc_flow1 &= ~FS_PRPVF_ROT_SRC_SEL_MASK;
++ break;
++ case MEM_DC_SYNC:
++ fs_disp_flow1 &= ~FS_DC1_SRC_SEL_MASK;
++ break;
++ case MEM_BG_SYNC:
++ fs_disp_flow1 &= ~FS_DP_SYNC0_SRC_SEL_MASK;
++ break;
++ case MEM_FG_SYNC:
++ fs_disp_flow1 &= ~FS_DP_SYNC1_SRC_SEL_MASK;
++ break;
++ case MEM_DC_ASYNC:
++ fs_disp_flow1 &= ~FS_DC2_SRC_SEL_MASK;
++ break;
++ case MEM_BG_ASYNC0:
++ fs_disp_flow1 &= ~FS_DP_ASYNC0_SRC_SEL_MASK;
++ break;
++ case MEM_FG_ASYNC0:
++ fs_disp_flow1 &= ~FS_DP_ASYNC1_SRC_SEL_MASK;
++ break;
++ case MEM_VDI_MEM:
++ fs_proc_flow1 &= ~FS_VDI_SRC_SEL_MASK;
++ break;
++ default:
++ retval = -EINVAL;
++ goto err;
++ }
++
++ ipu_cm_write(ipu, fs_proc_flow1, IPU_FS_PROC_FLOW1);
++ ipu_cm_write(ipu, fs_proc_flow2, IPU_FS_PROC_FLOW2);
++ ipu_cm_write(ipu, fs_proc_flow3, IPU_FS_PROC_FLOW3);
++ ipu_cm_write(ipu, fs_disp_flow1, IPU_FS_DISP_FLOW1);
++
++err:
++ mutex_unlock(&ipu->mutex_lock);
++ return retval;
++}
++EXPORT_SYMBOL(ipu_unlink_channels);
++
++/*!
++ * This function check whether a logical channel was enabled.
++ *
++ * @param ipu ipu handler
++ * @param channel Input parameter for the logical channel ID.
++ *
++ * @return This function returns 1 while request channel is enabled or
++ * 0 for not enabled.
++ */
++int32_t ipu_is_channel_busy(struct ipu_soc *ipu, ipu_channel_t channel)
++{
++ uint32_t reg;
++ uint32_t in_dma;
++ uint32_t out_dma;
++
++ out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
++ in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
++
++ reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(in_dma));
++ if (reg & idma_mask(in_dma))
++ return 1;
++ reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(out_dma));
++ if (reg & idma_mask(out_dma))
++ return 1;
++ return 0;
++}
++EXPORT_SYMBOL(ipu_is_channel_busy);
++
++/*!
++ * This function enables a logical channel.
++ *
++ * @param ipu ipu handler
++ * @param channel Input parameter for the logical channel ID.
++ *
++ * @return This function returns 0 on success or negative error code on
++ * fail.
++ */
++int32_t ipu_enable_channel(struct ipu_soc *ipu, ipu_channel_t channel)
++{
++ uint32_t reg;
++ uint32_t ipu_conf;
++ uint32_t in_dma;
++ uint32_t out_dma;
++ uint32_t sec_dma;
++ uint32_t thrd_dma;
++
++ mutex_lock(&ipu->mutex_lock);
++
++ if (ipu->channel_enable_mask & (1L << IPU_CHAN_ID(channel))) {
++ dev_err(ipu->dev, "Warning: channel already enabled %d\n",
++ IPU_CHAN_ID(channel));
++ mutex_unlock(&ipu->mutex_lock);
++ return -EACCES;
++ }
++
++ /* Get input and output dma channels */
++ out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
++ in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
++
++ ipu_conf = ipu_cm_read(ipu, IPU_CONF);
++ if (ipu->di_use_count[0] > 0) {
++ ipu_conf |= IPU_CONF_DI0_EN;
++ }
++ if (ipu->di_use_count[1] > 0) {
++ ipu_conf |= IPU_CONF_DI1_EN;
++ }
++ if (ipu->dp_use_count > 0)
++ ipu_conf |= IPU_CONF_DP_EN;
++ if (ipu->dc_use_count > 0)
++ ipu_conf |= IPU_CONF_DC_EN;
++ if (ipu->dmfc_use_count > 0)
++ ipu_conf |= IPU_CONF_DMFC_EN;
++ if (ipu->ic_use_count > 0)
++ ipu_conf |= IPU_CONF_IC_EN;
++ if (ipu->vdi_use_count > 0) {
++ ipu_conf |= IPU_CONF_ISP_EN;
++ ipu_conf |= IPU_CONF_VDI_EN;
++ ipu_conf |= IPU_CONF_IC_INPUT;
++ }
++ if (ipu->rot_use_count > 0)
++ ipu_conf |= IPU_CONF_ROT_EN;
++ if (ipu->smfc_use_count > 0)
++ ipu_conf |= IPU_CONF_SMFC_EN;
++ ipu_cm_write(ipu, ipu_conf, IPU_CONF);
++
++ if (idma_is_valid(in_dma)) {
++ reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(in_dma));
++ ipu_idmac_write(ipu, reg | idma_mask(in_dma), IDMAC_CHA_EN(in_dma));
++ }
++ if (idma_is_valid(out_dma)) {
++ reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(out_dma));
++ ipu_idmac_write(ipu, reg | idma_mask(out_dma), IDMAC_CHA_EN(out_dma));
++ }
++
++ if ((ipu->sec_chan_en[IPU_CHAN_ID(channel)]) &&
++ ((channel == MEM_PP_MEM) || (channel == MEM_PRP_VF_MEM) ||
++ (channel == MEM_VDI_PRP_VF_MEM))) {
++ sec_dma = channel_2_dma(channel, IPU_GRAPH_IN_BUFFER);
++ reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(sec_dma));
++ ipu_idmac_write(ipu, reg | idma_mask(sec_dma), IDMAC_CHA_EN(sec_dma));
++ }
++ if ((ipu->thrd_chan_en[IPU_CHAN_ID(channel)]) &&
++ ((channel == MEM_PP_MEM) || (channel == MEM_PRP_VF_MEM))) {
++ thrd_dma = channel_2_dma(channel, IPU_ALPHA_IN_BUFFER);
++ reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(thrd_dma));
++ ipu_idmac_write(ipu, reg | idma_mask(thrd_dma), IDMAC_CHA_EN(thrd_dma));
++
++ sec_dma = channel_2_dma(channel, IPU_GRAPH_IN_BUFFER);
++ reg = ipu_idmac_read(ipu, IDMAC_SEP_ALPHA);
++ ipu_idmac_write(ipu, reg | idma_mask(sec_dma), IDMAC_SEP_ALPHA);
++ } else if ((ipu->thrd_chan_en[IPU_CHAN_ID(channel)]) &&
++ ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC))) {
++ thrd_dma = channel_2_dma(channel, IPU_ALPHA_IN_BUFFER);
++ reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(thrd_dma));
++ ipu_idmac_write(ipu, reg | idma_mask(thrd_dma), IDMAC_CHA_EN(thrd_dma));
++ reg = ipu_idmac_read(ipu, IDMAC_SEP_ALPHA);
++ ipu_idmac_write(ipu, reg | idma_mask(in_dma), IDMAC_SEP_ALPHA);
++ }
++
++ if ((channel == MEM_DC_SYNC) || (channel == MEM_BG_SYNC) ||
++ (channel == MEM_FG_SYNC)) {
++ reg = ipu_idmac_read(ipu, IDMAC_WM_EN(in_dma));
++ ipu_idmac_write(ipu, reg | idma_mask(in_dma), IDMAC_WM_EN(in_dma));
++
++ _ipu_dp_dc_enable(ipu, channel);
++ }
++
++ if (_ipu_is_ic_chan(in_dma) || _ipu_is_ic_chan(out_dma) ||
++ _ipu_is_irt_chan(in_dma) || _ipu_is_irt_chan(out_dma) ||
++ _ipu_is_vdi_out_chan(out_dma))
++ _ipu_ic_enable_task(ipu, channel);
++
++ ipu->channel_enable_mask |= 1L << IPU_CHAN_ID(channel);
++
++ mutex_unlock(&ipu->mutex_lock);
++
++ return 0;
++}
++EXPORT_SYMBOL(ipu_enable_channel);
++
++/*!
++ * This function check buffer ready for a logical channel.
++ *
++ * @param ipu ipu handler
++ * @param channel Input parameter for the logical channel ID.
++ *
++ * @param type Input parameter which buffer to clear.
++ *
++ * @param bufNum Input parameter for which buffer number clear
++ * ready state.
++ *
++ */
++int32_t ipu_check_buffer_ready(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type,
++ uint32_t bufNum)
++{
++ uint32_t dma_chan = channel_2_dma(channel, type);
++ uint32_t reg;
++ unsigned long lock_flags;
++
++ if (dma_chan == IDMA_CHAN_INVALID)
++ return -EINVAL;
++
++ spin_lock_irqsave(&ipu->rdy_reg_spin_lock, lock_flags);
++ if (bufNum == 0)
++ reg = ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(dma_chan));
++ else if (bufNum == 1)
++ reg = ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(dma_chan));
++ else
++ reg = ipu_cm_read(ipu, IPU_CHA_BUF2_RDY(dma_chan));
++ spin_unlock_irqrestore(&ipu->rdy_reg_spin_lock, lock_flags);
++
++ if (reg & idma_mask(dma_chan))
++ return 1;
++ else
++ return 0;
++}
++EXPORT_SYMBOL(ipu_check_buffer_ready);
++
++/*!
++ * This function clear buffer ready for a logical channel.
++ *
++ * @param ipu ipu handler
++ * @param channel Input parameter for the logical channel ID.
++ *
++ * @param type Input parameter which buffer to clear.
++ *
++ * @param bufNum Input parameter for which buffer number clear
++ * ready state.
++ *
++ */
++void _ipu_clear_buffer_ready(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type,
++ uint32_t bufNum)
++{
++ uint32_t dma_ch = channel_2_dma(channel, type);
++
++ if (!idma_is_valid(dma_ch))
++ return;
++
++ ipu_cm_write(ipu, 0xF0300000, IPU_GPR); /* write one to clear */
++ if (bufNum == 0)
++ ipu_cm_write(ipu, idma_mask(dma_ch),
++ IPU_CHA_BUF0_RDY(dma_ch));
++ else if (bufNum == 1)
++ ipu_cm_write(ipu, idma_mask(dma_ch),
++ IPU_CHA_BUF1_RDY(dma_ch));
++ else
++ ipu_cm_write(ipu, idma_mask(dma_ch),
++ IPU_CHA_BUF2_RDY(dma_ch));
++ ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */
++}
++
++void ipu_clear_buffer_ready(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type,
++ uint32_t bufNum)
++{
++ unsigned long lock_flags;
++
++ spin_lock_irqsave(&ipu->rdy_reg_spin_lock, lock_flags);
++ _ipu_clear_buffer_ready(ipu, channel, type, bufNum);
++ spin_unlock_irqrestore(&ipu->rdy_reg_spin_lock, lock_flags);
++}
++EXPORT_SYMBOL(ipu_clear_buffer_ready);
++
++/*!
++ * This function disables a logical channel.
++ *
++ * @param ipu ipu handler
++ * @param channel Input parameter for the logical channel ID.
++ *
++ * @param wait_for_stop Flag to set whether to wait for channel end
++ * of frame or return immediately.
++ *
++ * @return This function returns 0 on success or negative error code on
++ * fail.
++ */
++int32_t ipu_disable_channel(struct ipu_soc *ipu, ipu_channel_t channel, bool wait_for_stop)
++{
++ uint32_t reg;
++ uint32_t in_dma;
++ uint32_t out_dma;
++ uint32_t sec_dma = NO_DMA;
++ uint32_t thrd_dma = NO_DMA;
++ uint16_t fg_pos_x, fg_pos_y;
++ unsigned long lock_flags;
++
++ mutex_lock(&ipu->mutex_lock);
++
++ if ((ipu->channel_enable_mask & (1L << IPU_CHAN_ID(channel))) == 0) {
++ dev_dbg(ipu->dev, "Channel already disabled %d\n",
++ IPU_CHAN_ID(channel));
++ mutex_unlock(&ipu->mutex_lock);
++ return -EACCES;
++ }
++
++ /* Get input and output dma channels */
++ out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
++ in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
++
++ if ((idma_is_valid(in_dma) &&
++ !idma_is_set(ipu, IDMAC_CHA_EN, in_dma))
++ && (idma_is_valid(out_dma) &&
++ !idma_is_set(ipu, IDMAC_CHA_EN, out_dma))) {
++ mutex_unlock(&ipu->mutex_lock);
++ return -EINVAL;
++ }
++
++ if (ipu->sec_chan_en[IPU_CHAN_ID(channel)])
++ sec_dma = channel_2_dma(channel, IPU_GRAPH_IN_BUFFER);
++ if (ipu->thrd_chan_en[IPU_CHAN_ID(channel)]) {
++ sec_dma = channel_2_dma(channel, IPU_GRAPH_IN_BUFFER);
++ thrd_dma = channel_2_dma(channel, IPU_ALPHA_IN_BUFFER);
++ }
++
++ if ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC) ||
++ (channel == MEM_DC_SYNC)) {
++ if (channel == MEM_FG_SYNC) {
++ _ipu_disp_get_window_pos(ipu, channel, &fg_pos_x, &fg_pos_y);
++ _ipu_disp_set_window_pos(ipu, channel, 0, 0);
++ }
++
++ _ipu_dp_dc_disable(ipu, channel, false);
++
++ /*
++ * wait for BG channel EOF then disable FG-IDMAC,
++ * it avoid FG NFB4EOF error.
++ */
++ if ((channel == MEM_FG_SYNC) && (ipu_is_channel_busy(ipu, MEM_BG_SYNC))) {
++ int timeout = 50;
++
++ ipu_cm_write(ipu, IPUIRQ_2_MASK(IPU_IRQ_BG_SYNC_EOF),
++ IPUIRQ_2_STATREG(IPU_IRQ_BG_SYNC_EOF));
++ while ((ipu_cm_read(ipu, IPUIRQ_2_STATREG(IPU_IRQ_BG_SYNC_EOF)) &
++ IPUIRQ_2_MASK(IPU_IRQ_BG_SYNC_EOF)) == 0) {
++ msleep(10);
++ timeout -= 10;
++ if (timeout <= 0) {
++ dev_err(ipu->dev, "warning: wait for bg sync eof timeout\n");
++ break;
++ }
++ }
++ }
++ } else if (wait_for_stop && !_ipu_is_smfc_chan(out_dma) &&
++ channel != CSI_PRP_VF_MEM && channel != CSI_PRP_ENC_MEM) {
++ while (idma_is_set(ipu, IDMAC_CHA_BUSY, in_dma) ||
++ idma_is_set(ipu, IDMAC_CHA_BUSY, out_dma) ||
++ (ipu->sec_chan_en[IPU_CHAN_ID(channel)] &&
++ idma_is_set(ipu, IDMAC_CHA_BUSY, sec_dma)) ||
++ (ipu->thrd_chan_en[IPU_CHAN_ID(channel)] &&
++ idma_is_set(ipu, IDMAC_CHA_BUSY, thrd_dma))) {
++ uint32_t irq = 0xffffffff;
++ int timeout = 50000;
++
++ if (idma_is_set(ipu, IDMAC_CHA_BUSY, out_dma))
++ irq = out_dma;
++ if (ipu->sec_chan_en[IPU_CHAN_ID(channel)] &&
++ idma_is_set(ipu, IDMAC_CHA_BUSY, sec_dma))
++ irq = sec_dma;
++ if (ipu->thrd_chan_en[IPU_CHAN_ID(channel)] &&
++ idma_is_set(ipu, IDMAC_CHA_BUSY, thrd_dma))
++ irq = thrd_dma;
++ if (idma_is_set(ipu, IDMAC_CHA_BUSY, in_dma))
++ irq = in_dma;
++
++ if (irq == 0xffffffff) {
++ dev_dbg(ipu->dev, "warning: no channel busy, break\n");
++ break;
++ }
++
++ ipu_cm_write(ipu, IPUIRQ_2_MASK(irq),
++ IPUIRQ_2_STATREG(irq));
++
++ dev_dbg(ipu->dev, "warning: channel %d busy, need wait\n", irq);
++
++ while (((ipu_cm_read(ipu, IPUIRQ_2_STATREG(irq))
++ & IPUIRQ_2_MASK(irq)) == 0) &&
++ (idma_is_set(ipu, IDMAC_CHA_BUSY, irq))) {
++ udelay(10);
++ timeout -= 10;
++ if (timeout <= 0) {
++ ipu_dump_registers(ipu);
++ dev_err(ipu->dev, "warning: disable ipu dma channel %d during its busy state\n", irq);
++ break;
++ }
++ }
++ dev_dbg(ipu->dev, "wait_time:%d\n", 50000 - timeout);
++
++ }
++ }
++
++ if ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC) ||
++ (channel == MEM_DC_SYNC)) {
++ reg = ipu_idmac_read(ipu, IDMAC_WM_EN(in_dma));
++ ipu_idmac_write(ipu, reg & ~idma_mask(in_dma), IDMAC_WM_EN(in_dma));
++ }
++
++ /* Disable IC task */
++ if (_ipu_is_ic_chan(in_dma) || _ipu_is_ic_chan(out_dma) ||
++ _ipu_is_irt_chan(in_dma) || _ipu_is_irt_chan(out_dma) ||
++ _ipu_is_vdi_out_chan(out_dma))
++ _ipu_ic_disable_task(ipu, channel);
++
++ /* Disable DMA channel(s) */
++ if (idma_is_valid(in_dma)) {
++ reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(in_dma));
++ ipu_idmac_write(ipu, reg & ~idma_mask(in_dma), IDMAC_CHA_EN(in_dma));
++ ipu_cm_write(ipu, idma_mask(in_dma), IPU_CHA_CUR_BUF(in_dma));
++ ipu_cm_write(ipu, tri_cur_buf_mask(in_dma),
++ IPU_CHA_TRIPLE_CUR_BUF(in_dma));
++ }
++ if (idma_is_valid(out_dma)) {
++ reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(out_dma));
++ ipu_idmac_write(ipu, reg & ~idma_mask(out_dma), IDMAC_CHA_EN(out_dma));
++ ipu_cm_write(ipu, idma_mask(out_dma), IPU_CHA_CUR_BUF(out_dma));
++ ipu_cm_write(ipu, tri_cur_buf_mask(out_dma),
++ IPU_CHA_TRIPLE_CUR_BUF(out_dma));
++ }
++ if (ipu->sec_chan_en[IPU_CHAN_ID(channel)] && idma_is_valid(sec_dma)) {
++ reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(sec_dma));
++ ipu_idmac_write(ipu, reg & ~idma_mask(sec_dma), IDMAC_CHA_EN(sec_dma));
++ ipu_cm_write(ipu, idma_mask(sec_dma), IPU_CHA_CUR_BUF(sec_dma));
++ }
++ if (ipu->thrd_chan_en[IPU_CHAN_ID(channel)] && idma_is_valid(thrd_dma)) {
++ reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(thrd_dma));
++ ipu_idmac_write(ipu, reg & ~idma_mask(thrd_dma), IDMAC_CHA_EN(thrd_dma));
++ if (channel == MEM_BG_SYNC || channel == MEM_FG_SYNC) {
++ reg = ipu_idmac_read(ipu, IDMAC_SEP_ALPHA);
++ ipu_idmac_write(ipu, reg & ~idma_mask(in_dma), IDMAC_SEP_ALPHA);
++ } else {
++ reg = ipu_idmac_read(ipu, IDMAC_SEP_ALPHA);
++ ipu_idmac_write(ipu, reg & ~idma_mask(sec_dma), IDMAC_SEP_ALPHA);
++ }
++ ipu_cm_write(ipu, idma_mask(thrd_dma), IPU_CHA_CUR_BUF(thrd_dma));
++ }
++
++ if (channel == MEM_FG_SYNC)
++ _ipu_disp_set_window_pos(ipu, channel, fg_pos_x, fg_pos_y);
++
++ spin_lock_irqsave(&ipu->rdy_reg_spin_lock, lock_flags);
++ /* Set channel buffers NOT to be ready */
++ if (idma_is_valid(in_dma)) {
++ _ipu_clear_buffer_ready(ipu, channel, IPU_VIDEO_IN_BUFFER, 0);
++ _ipu_clear_buffer_ready(ipu, channel, IPU_VIDEO_IN_BUFFER, 1);
++ _ipu_clear_buffer_ready(ipu, channel, IPU_VIDEO_IN_BUFFER, 2);
++ }
++ if (idma_is_valid(out_dma)) {
++ _ipu_clear_buffer_ready(ipu, channel, IPU_OUTPUT_BUFFER, 0);
++ _ipu_clear_buffer_ready(ipu, channel, IPU_OUTPUT_BUFFER, 1);
++ }
++ if (ipu->sec_chan_en[IPU_CHAN_ID(channel)] && idma_is_valid(sec_dma)) {
++ _ipu_clear_buffer_ready(ipu, channel, IPU_GRAPH_IN_BUFFER, 0);
++ _ipu_clear_buffer_ready(ipu, channel, IPU_GRAPH_IN_BUFFER, 1);
++ }
++ if (ipu->thrd_chan_en[IPU_CHAN_ID(channel)] && idma_is_valid(thrd_dma)) {
++ _ipu_clear_buffer_ready(ipu, channel, IPU_ALPHA_IN_BUFFER, 0);
++ _ipu_clear_buffer_ready(ipu, channel, IPU_ALPHA_IN_BUFFER, 1);
++ }
++ spin_unlock_irqrestore(&ipu->rdy_reg_spin_lock, lock_flags);
++
++ ipu->channel_enable_mask &= ~(1L << IPU_CHAN_ID(channel));
++
++ mutex_unlock(&ipu->mutex_lock);
++
++ return 0;
++}
++EXPORT_SYMBOL(ipu_disable_channel);
++
++/*!
++ * This function enables CSI.
++ *
++ * @param ipu ipu handler
++ * @param csi csi num 0 or 1
++ *
++ * @return This function returns 0 on success or negative error code on
++ * fail.
++ */
++int32_t ipu_enable_csi(struct ipu_soc *ipu, uint32_t csi)
++{
++ uint32_t reg;
++
++ if (csi > 1) {
++ dev_err(ipu->dev, "Wrong csi num_%d\n", csi);
++ return -EINVAL;
++ }
++
++ _ipu_get(ipu);
++ mutex_lock(&ipu->mutex_lock);
++ ipu->csi_use_count[csi]++;
++
++ if (ipu->csi_use_count[csi] == 1) {
++ reg = ipu_cm_read(ipu, IPU_CONF);
++ if (csi == 0)
++ ipu_cm_write(ipu, reg | IPU_CONF_CSI0_EN, IPU_CONF);
++ else
++ ipu_cm_write(ipu, reg | IPU_CONF_CSI1_EN, IPU_CONF);
++ }
++ mutex_unlock(&ipu->mutex_lock);
++ _ipu_put(ipu);
++ return 0;
++}
++EXPORT_SYMBOL(ipu_enable_csi);
++
++/*!
++ * This function disables CSI.
++ *
++ * @param ipu ipu handler
++ * @param csi csi num 0 or 1
++ *
++ * @return This function returns 0 on success or negative error code on
++ * fail.
++ */
++int32_t ipu_disable_csi(struct ipu_soc *ipu, uint32_t csi)
++{
++ uint32_t reg;
++
++ if (csi > 1) {
++ dev_err(ipu->dev, "Wrong csi num_%d\n", csi);
++ return -EINVAL;
++ }
++ _ipu_get(ipu);
++ mutex_lock(&ipu->mutex_lock);
++ ipu->csi_use_count[csi]--;
++ if (ipu->csi_use_count[csi] == 0) {
++ _ipu_csi_wait4eof(ipu, ipu->csi_channel[csi]);
++ reg = ipu_cm_read(ipu, IPU_CONF);
++ if (csi == 0)
++ ipu_cm_write(ipu, reg & ~IPU_CONF_CSI0_EN, IPU_CONF);
++ else
++ ipu_cm_write(ipu, reg & ~IPU_CONF_CSI1_EN, IPU_CONF);
++ }
++ mutex_unlock(&ipu->mutex_lock);
++ _ipu_put(ipu);
++ return 0;
++}
++EXPORT_SYMBOL(ipu_disable_csi);
++
++static irqreturn_t ipu_sync_irq_handler(int irq, void *desc)
++{
++ struct ipu_soc *ipu = desc;
++ int i;
++ uint32_t line, bit, int_stat, int_ctrl;
++ irqreturn_t result = IRQ_NONE;
++ const int int_reg[] = { 1, 2, 3, 4, 11, 12, 13, 14, 15, 0 };
++
++ spin_lock(&ipu->int_reg_spin_lock);
++
++ for (i = 0; int_reg[i] != 0; i++) {
++ int_stat = ipu_cm_read(ipu, IPU_INT_STAT(int_reg[i]));
++ int_ctrl = ipu_cm_read(ipu, IPU_INT_CTRL(int_reg[i]));
++ int_stat &= int_ctrl;
++ ipu_cm_write(ipu, int_stat, IPU_INT_STAT(int_reg[i]));
++ while ((line = ffs(int_stat)) != 0) {
++ bit = --line;
++ int_stat &= ~(1UL << line);
++ line += (int_reg[i] - 1) * 32;
++ result |=
++ ipu->irq_list[line].handler(line,
++ ipu->irq_list[line].
++ dev_id);
++ if (ipu->irq_list[line].flags & IPU_IRQF_ONESHOT) {
++ int_ctrl &= ~(1UL << bit);
++ ipu_cm_write(ipu, int_ctrl,
++ IPU_INT_CTRL(int_reg[i]));
++ }
++ }
++ }
++
++ spin_unlock(&ipu->int_reg_spin_lock);
++
++ return result;
++}
++
++static irqreturn_t ipu_err_irq_handler(int irq, void *desc)
++{
++ struct ipu_soc *ipu = desc;
++ int i;
++ uint32_t int_stat;
++ const int err_reg[] = { 5, 6, 9, 10, 0 };
++
++ spin_lock(&ipu->int_reg_spin_lock);
++
++ for (i = 0; err_reg[i] != 0; i++) {
++ int_stat = ipu_cm_read(ipu, IPU_INT_STAT(err_reg[i]));
++ int_stat &= ipu_cm_read(ipu, IPU_INT_CTRL(err_reg[i]));
++ if (int_stat) {
++ ipu_cm_write(ipu, int_stat, IPU_INT_STAT(err_reg[i]));
++ dev_warn(ipu->dev,
++ "IPU Warning - IPU_INT_STAT_%d = 0x%08X\n",
++ err_reg[i], int_stat);
++ /* Disable interrupts so we only get error once */
++ int_stat = ipu_cm_read(ipu, IPU_INT_CTRL(err_reg[i])) &
++ ~int_stat;
++ ipu_cm_write(ipu, int_stat, IPU_INT_CTRL(err_reg[i]));
++ }
++ }
++
++ spin_unlock(&ipu->int_reg_spin_lock);
++
++ return IRQ_HANDLED;
++}
++
++/*!
++ * This function enables the interrupt for the specified interrupt line.
++ * The interrupt lines are defined in \b ipu_irq_line enum.
++ *
++ * @param ipu ipu handler
++ * @param irq Interrupt line to enable interrupt for.
++ *
++ * @return This function returns 0 on success or negative error code on
++ * fail.
++ */
++int ipu_enable_irq(struct ipu_soc *ipu, uint32_t irq)
++{
++ uint32_t reg;
++ unsigned long lock_flags;
++ int ret = 0;
++
++ _ipu_get(ipu);
++
++ spin_lock_irqsave(&ipu->int_reg_spin_lock, lock_flags);
++
++ /*
++ * Check sync interrupt handler only, since we do nothing for
++ * error interrupts but than print out register values in the
++ * error interrupt source handler.
++ */
++ if (_ipu_is_sync_irq(irq) && (ipu->irq_list[irq].handler == NULL)) {
++ dev_err(ipu->dev, "handler hasn't been registered on sync "
++ "irq %d\n", irq);
++ ret = -EACCES;
++ goto out;
++ }
++
++ reg = ipu_cm_read(ipu, IPUIRQ_2_CTRLREG(irq));
++ reg |= IPUIRQ_2_MASK(irq);
++ ipu_cm_write(ipu, reg, IPUIRQ_2_CTRLREG(irq));
++out:
++ spin_unlock_irqrestore(&ipu->int_reg_spin_lock, lock_flags);
++
++ _ipu_put(ipu);
++
++ return ret;
++}
++EXPORT_SYMBOL(ipu_enable_irq);
++
++/*!
++ * This function disables the interrupt for the specified interrupt line.
++ * The interrupt lines are defined in \b ipu_irq_line enum.
++ *
++ * @param ipu ipu handler
++ * @param irq Interrupt line to disable interrupt for.
++ *
++ */
++void ipu_disable_irq(struct ipu_soc *ipu, uint32_t irq)
++{
++ uint32_t reg;
++ unsigned long lock_flags;
++
++ _ipu_get(ipu);
++
++ spin_lock_irqsave(&ipu->int_reg_spin_lock, lock_flags);
++
++ reg = ipu_cm_read(ipu, IPUIRQ_2_CTRLREG(irq));
++ reg &= ~IPUIRQ_2_MASK(irq);
++ ipu_cm_write(ipu, reg, IPUIRQ_2_CTRLREG(irq));
++
++ spin_unlock_irqrestore(&ipu->int_reg_spin_lock, lock_flags);
++
++ _ipu_put(ipu);
++}
++EXPORT_SYMBOL(ipu_disable_irq);
++
++/*!
++ * This function clears the interrupt for the specified interrupt line.
++ * The interrupt lines are defined in \b ipu_irq_line enum.
++ *
++ * @param ipu ipu handler
++ * @param irq Interrupt line to clear interrupt for.
++ *
++ */
++void ipu_clear_irq(struct ipu_soc *ipu, uint32_t irq)
++{
++ unsigned long lock_flags;
++
++ _ipu_get(ipu);
++
++ spin_lock_irqsave(&ipu->int_reg_spin_lock, lock_flags);
++
++ ipu_cm_write(ipu, IPUIRQ_2_MASK(irq), IPUIRQ_2_STATREG(irq));
++
++ spin_unlock_irqrestore(&ipu->int_reg_spin_lock, lock_flags);
++
++ _ipu_put(ipu);
++}
++EXPORT_SYMBOL(ipu_clear_irq);
++
++/*!
++ * This function returns the current interrupt status for the specified
++ * interrupt line. The interrupt lines are defined in \b ipu_irq_line enum.
++ *
++ * @param ipu ipu handler
++ * @param irq Interrupt line to get status for.
++ *
++ * @return Returns true if the interrupt is pending/asserted or false if
++ * the interrupt is not pending.
++ */
++bool ipu_get_irq_status(struct ipu_soc *ipu, uint32_t irq)
++{
++ uint32_t reg;
++ unsigned long lock_flags;
++
++ _ipu_get(ipu);
++
++ spin_lock_irqsave(&ipu->int_reg_spin_lock, lock_flags);
++ reg = ipu_cm_read(ipu, IPUIRQ_2_STATREG(irq));
++ spin_unlock_irqrestore(&ipu->int_reg_spin_lock, lock_flags);
++
++ _ipu_put(ipu);
++
++ if (reg & IPUIRQ_2_MASK(irq))
++ return true;
++ else
++ return false;
++}
++EXPORT_SYMBOL(ipu_get_irq_status);
++
++/*!
++ * This function registers an interrupt handler function for the specified
++ * interrupt line. The interrupt lines are defined in \b ipu_irq_line enum.
++ *
++ * @param ipu ipu handler
++ * @param irq Interrupt line to get status for.
++ *
++ * @param handler Input parameter for address of the handler
++ * function.
++ *
++ * @param irq_flags Flags for interrupt mode. Currently not used.
++ *
++ * @param devname Input parameter for string name of driver
++ * registering the handler.
++ *
++ * @param dev_id Input parameter for pointer of data to be
++ * passed to the handler.
++ *
++ * @return This function returns 0 on success or negative error code on
++ * fail.
++ */
++int ipu_request_irq(struct ipu_soc *ipu, uint32_t irq,
++ irqreturn_t(*handler) (int, void *),
++ uint32_t irq_flags, const char *devname, void *dev_id)
++{
++ uint32_t reg;
++ unsigned long lock_flags;
++ int ret = 0;
++
++ BUG_ON(irq >= IPU_IRQ_COUNT);
++
++ _ipu_get(ipu);
++
++ spin_lock_irqsave(&ipu->int_reg_spin_lock, lock_flags);
++
++ if (ipu->irq_list[irq].handler != NULL) {
++ dev_err(ipu->dev,
++ "handler already installed on irq %d\n", irq);
++ ret = -EINVAL;
++ goto out;
++ }
++
++ /*
++ * Check sync interrupt handler only, since we do nothing for
++ * error interrupts but than print out register values in the
++ * error interrupt source handler.
++ */
++ if (_ipu_is_sync_irq(irq) && (handler == NULL)) {
++ dev_err(ipu->dev, "handler is NULL for sync irq %d\n", irq);
++ ret = -EINVAL;
++ goto out;
++ }
++
++ ipu->irq_list[irq].handler = handler;
++ ipu->irq_list[irq].flags = irq_flags;
++ ipu->irq_list[irq].dev_id = dev_id;
++ ipu->irq_list[irq].name = devname;
++
++ /* clear irq stat for previous use */
++ ipu_cm_write(ipu, IPUIRQ_2_MASK(irq), IPUIRQ_2_STATREG(irq));
++ /* enable the interrupt */
++ reg = ipu_cm_read(ipu, IPUIRQ_2_CTRLREG(irq));
++ reg |= IPUIRQ_2_MASK(irq);
++ ipu_cm_write(ipu, reg, IPUIRQ_2_CTRLREG(irq));
++out:
++ spin_unlock_irqrestore(&ipu->int_reg_spin_lock, lock_flags);
++
++ _ipu_put(ipu);
++
++ return ret;
++}
++EXPORT_SYMBOL(ipu_request_irq);
++
++/*!
++ * This function unregisters an interrupt handler for the specified interrupt
++ * line. The interrupt lines are defined in \b ipu_irq_line enum.
++ *
++ * @param ipu ipu handler
++ * @param irq Interrupt line to get status for.
++ *
++ * @param dev_id Input parameter for pointer of data to be passed
++ * to the handler. This must match value passed to
++ * ipu_request_irq().
++ *
++ */
++void ipu_free_irq(struct ipu_soc *ipu, uint32_t irq, void *dev_id)
++{
++ uint32_t reg;
++ unsigned long lock_flags;
++
++ _ipu_get(ipu);
++
++ if (ipu->irq_list[irq].dev_id != dev_id)
++ return;
++
++ spin_lock_irqsave(&ipu->int_reg_spin_lock, lock_flags);
++
++ /* disable the interrupt */
++ reg = ipu_cm_read(ipu, IPUIRQ_2_CTRLREG(irq));
++ reg &= ~IPUIRQ_2_MASK(irq);
++ ipu_cm_write(ipu, reg, IPUIRQ_2_CTRLREG(irq));
++ memset(&ipu->irq_list[irq], 0, sizeof(ipu->irq_list[irq]));
++
++ spin_unlock_irqrestore(&ipu->int_reg_spin_lock, lock_flags);
++
++ _ipu_put(ipu);
++}
++EXPORT_SYMBOL(ipu_free_irq);
++
++uint32_t ipu_get_cur_buffer_idx(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type)
++{
++ uint32_t reg, dma_chan;
++
++ dma_chan = channel_2_dma(channel, type);
++ if (!idma_is_valid(dma_chan))
++ return -EINVAL;
++
++ reg = ipu_cm_read(ipu, IPU_CHA_TRB_MODE_SEL(dma_chan));
++ if ((reg & idma_mask(dma_chan)) && _ipu_is_trb_chan(dma_chan)) {
++ reg = ipu_cm_read(ipu, IPU_CHA_TRIPLE_CUR_BUF(dma_chan));
++ return (reg & tri_cur_buf_mask(dma_chan)) >>
++ tri_cur_buf_shift(dma_chan);
++ } else {
++ reg = ipu_cm_read(ipu, IPU_CHA_CUR_BUF(dma_chan));
++ if (reg & idma_mask(dma_chan))
++ return 1;
++ else
++ return 0;
++ }
++}
++EXPORT_SYMBOL(ipu_get_cur_buffer_idx);
++
++uint32_t _ipu_channel_status(struct ipu_soc *ipu, ipu_channel_t channel)
++{
++ uint32_t stat = 0;
++ uint32_t task_stat_reg = ipu_cm_read(ipu, IPU_PROC_TASK_STAT);
++
++ switch (channel) {
++ case MEM_PRP_VF_MEM:
++ stat = (task_stat_reg & TSTAT_VF_MASK) >> TSTAT_VF_OFFSET;
++ break;
++ case MEM_VDI_PRP_VF_MEM:
++ stat = (task_stat_reg & TSTAT_VF_MASK) >> TSTAT_VF_OFFSET;
++ break;
++ case MEM_ROT_VF_MEM:
++ stat =
++ (task_stat_reg & TSTAT_VF_ROT_MASK) >> TSTAT_VF_ROT_OFFSET;
++ break;
++ case MEM_PRP_ENC_MEM:
++ stat = (task_stat_reg & TSTAT_ENC_MASK) >> TSTAT_ENC_OFFSET;
++ break;
++ case MEM_ROT_ENC_MEM:
++ stat =
++ (task_stat_reg & TSTAT_ENC_ROT_MASK) >>
++ TSTAT_ENC_ROT_OFFSET;
++ break;
++ case MEM_PP_MEM:
++ stat = (task_stat_reg & TSTAT_PP_MASK) >> TSTAT_PP_OFFSET;
++ break;
++ case MEM_ROT_PP_MEM:
++ stat =
++ (task_stat_reg & TSTAT_PP_ROT_MASK) >> TSTAT_PP_ROT_OFFSET;
++ break;
++
++ default:
++ stat = TASK_STAT_IDLE;
++ break;
++ }
++ return stat;
++}
++
++/*!
++ * This function check for a logical channel status
++ *
++ * @param ipu ipu handler
++ * @param channel Input parameter for the logical channel ID.
++ *
++ * @return This function returns 0 on idle and 1 on busy.
++ *
++ */
++uint32_t ipu_channel_status(struct ipu_soc *ipu, ipu_channel_t channel)
++{
++ uint32_t dma_status;
++
++ _ipu_get(ipu);
++ mutex_lock(&ipu->mutex_lock);
++ dma_status = ipu_is_channel_busy(ipu, channel);
++ mutex_unlock(&ipu->mutex_lock);
++ _ipu_put(ipu);
++
++ dev_dbg(ipu->dev, "%s, dma_status:%d.\n", __func__, dma_status);
++
++ return dma_status;
++}
++EXPORT_SYMBOL(ipu_channel_status);
++
++int32_t ipu_swap_channel(struct ipu_soc *ipu, ipu_channel_t from_ch, ipu_channel_t to_ch)
++{
++ uint32_t reg;
++ unsigned long lock_flags;
++ int from_dma = channel_2_dma(from_ch, IPU_INPUT_BUFFER);
++ int to_dma = channel_2_dma(to_ch, IPU_INPUT_BUFFER);
++
++ mutex_lock(&ipu->mutex_lock);
++
++ /* enable target channel */
++ reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(to_dma));
++ ipu_idmac_write(ipu, reg | idma_mask(to_dma), IDMAC_CHA_EN(to_dma));
++
++ ipu->channel_enable_mask |= 1L << IPU_CHAN_ID(to_ch);
++
++ /* switch dp dc */
++ _ipu_dp_dc_disable(ipu, from_ch, true);
++
++ /* disable source channel */
++ reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(from_dma));
++ ipu_idmac_write(ipu, reg & ~idma_mask(from_dma), IDMAC_CHA_EN(from_dma));
++ ipu_cm_write(ipu, idma_mask(from_dma), IPU_CHA_CUR_BUF(from_dma));
++ ipu_cm_write(ipu, tri_cur_buf_mask(from_dma),
++ IPU_CHA_TRIPLE_CUR_BUF(from_dma));
++
++ ipu->channel_enable_mask &= ~(1L << IPU_CHAN_ID(from_ch));
++
++ spin_lock_irqsave(&ipu->rdy_reg_spin_lock, lock_flags);
++ _ipu_clear_buffer_ready(ipu, from_ch, IPU_VIDEO_IN_BUFFER, 0);
++ _ipu_clear_buffer_ready(ipu, from_ch, IPU_VIDEO_IN_BUFFER, 1);
++ _ipu_clear_buffer_ready(ipu, from_ch, IPU_VIDEO_IN_BUFFER, 2);
++ spin_unlock_irqrestore(&ipu->rdy_reg_spin_lock, lock_flags);
++
++ mutex_unlock(&ipu->mutex_lock);
++
++ return 0;
++}
++EXPORT_SYMBOL(ipu_swap_channel);
++
++uint32_t bytes_per_pixel(uint32_t fmt)
++{
++ switch (fmt) {
++ case IPU_PIX_FMT_GENERIC: /*generic data */
++ case IPU_PIX_FMT_RGB332:
++ case IPU_PIX_FMT_YUV420P:
++ case IPU_PIX_FMT_YVU420P:
++ case IPU_PIX_FMT_YUV422P:
++ case IPU_PIX_FMT_YUV444P:
++ return 1;
++ break;
++ case IPU_PIX_FMT_GENERIC_16: /* generic data */
++ case IPU_PIX_FMT_RGB565:
++ case IPU_PIX_FMT_YUYV:
++ case IPU_PIX_FMT_UYVY:
++ return 2;
++ break;
++ case IPU_PIX_FMT_BGR24:
++ case IPU_PIX_FMT_RGB24:
++ case IPU_PIX_FMT_YUV444:
++ return 3;
++ break;
++ case IPU_PIX_FMT_GENERIC_32: /*generic data */
++ case IPU_PIX_FMT_BGR32:
++ case IPU_PIX_FMT_BGRA32:
++ case IPU_PIX_FMT_RGB32:
++ case IPU_PIX_FMT_RGBA32:
++ case IPU_PIX_FMT_ABGR32:
++ return 4;
++ break;
++ default:
++ return 1;
++ break;
++ }
++ return 0;
++}
++EXPORT_SYMBOL(bytes_per_pixel);
++
++ipu_color_space_t format_to_colorspace(uint32_t fmt)
++{
++ switch (fmt) {
++ case IPU_PIX_FMT_RGB666:
++ case IPU_PIX_FMT_RGB565:
++ case IPU_PIX_FMT_BGR24:
++ case IPU_PIX_FMT_RGB24:
++ case IPU_PIX_FMT_GBR24:
++ case IPU_PIX_FMT_BGR32:
++ case IPU_PIX_FMT_BGRA32:
++ case IPU_PIX_FMT_RGB32:
++ case IPU_PIX_FMT_RGBA32:
++ case IPU_PIX_FMT_ABGR32:
++ case IPU_PIX_FMT_LVDS666:
++ case IPU_PIX_FMT_LVDS888:
++ return RGB;
++ break;
++
++ default:
++ return YCbCr;
++ break;
++ }
++ return RGB;
++}
++
++bool ipu_pixel_format_has_alpha(uint32_t fmt)
++{
++ switch (fmt) {
++ case IPU_PIX_FMT_RGBA32:
++ case IPU_PIX_FMT_BGRA32:
++ case IPU_PIX_FMT_ABGR32:
++ return true;
++ break;
++ default:
++ return false;
++ break;
++ }
++ return false;
++}
++
++bool ipu_ch_param_bad_alpha_pos(uint32_t pixel_fmt)
++{
++ return _ipu_ch_param_bad_alpha_pos(pixel_fmt);
++}
++EXPORT_SYMBOL(ipu_ch_param_bad_alpha_pos);
++
++#ifdef CONFIG_PM
++static int ipu_suspend(struct device *dev)
++{
++ struct ipu_soc *ipu = dev_get_drvdata(dev);
++
++ /* All IDMAC channel and IPU clock should be disabled.*/
++ if (ipu->pdata->pg)
++ ipu->pdata->pg(1);
++
++ dev_dbg(dev, "ipu suspend.\n");
++ return 0;
++}
++
++static int ipu_resume(struct device *dev)
++{
++ struct ipu_soc *ipu = dev_get_drvdata(dev);
++
++ if (ipu->pdata->pg) {
++ ipu->pdata->pg(0);
++
++ _ipu_get(ipu);
++ _ipu_dmfc_init(ipu, dmfc_type_setup, 1);
++ /* Set sync refresh channels as high priority */
++ ipu_idmac_write(ipu, 0x18800001L, IDMAC_CHA_PRI(0));
++ _ipu_put(ipu);
++ }
++ dev_dbg(dev, "ipu resume.\n");
++ return 0;
++}
++
++int ipu_runtime_suspend(struct device *dev)
++{
++ dev_dbg(dev, "ipu busfreq high release.\n");
++ release_bus_freq(BUS_FREQ_HIGH);
++
++ return 0;
++}
++
++int ipu_runtime_resume(struct device *dev)
++{
++ dev_dbg(dev, "ipu busfreq high requst.\n");
++ request_bus_freq(BUS_FREQ_HIGH);
++
++ return 0;
++}
++
++static const struct dev_pm_ops ipu_pm_ops = {
++ SET_RUNTIME_PM_OPS(ipu_runtime_suspend, ipu_runtime_resume, NULL)
++ SET_SYSTEM_SLEEP_PM_OPS(ipu_suspend, ipu_resume)
++};
++#endif
++
++/*!
++ * This structure contains pointers to the power management callback functions.
++ */
++static struct platform_driver mxcipu_driver = {
++ .driver = {
++ .name = "imx-ipuv3",
++ .of_match_table = imx_ipuv3_dt_ids,
++ #ifdef CONFIG_PM
++ .pm = &ipu_pm_ops,
++ #endif
++ },
++ .probe = ipu_probe,
++ .id_table = imx_ipu_type,
++ .remove = ipu_remove,
++};
++
++int32_t __init ipu_gen_init(void)
++{
++ int32_t ret;
++
++ ret = platform_driver_register(&mxcipu_driver);
++ return 0;
++}
++
++subsys_initcall(ipu_gen_init);
++
++static void __exit ipu_gen_uninit(void)
++{
++ platform_driver_unregister(&mxcipu_driver);
++}
++
++module_exit(ipu_gen_uninit);
++
++MODULE_DESCRIPTION("i.MX IPU v3 driver");
++MODULE_LICENSE("GPL");
+diff -Nur linux-4.1.3/drivers/mxc/ipu3/ipu_device.c linux-xbian-imx6/drivers/mxc/ipu3/ipu_device.c
+--- linux-4.1.3/drivers/mxc/ipu3/ipu_device.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/ipu3/ipu_device.c 2015-07-27 23:13:06.226765901 +0200
+@@ -0,0 +1,3725 @@
++/*
++ * Copyright 2005-2014 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*!
++ * @file ipu_device.c
++ *
++ * @brief This file contains the IPUv3 driver device interface and fops functions.
++ *
++ * @ingroup IPU
++ */
++#include <linux/clk.h>
++#include <linux/cpumask.h>
++#include <linux/delay.h>
++#include <linux/dma-mapping.h>
++#include <linux/err.h>
++#include <linux/init.h>
++#include <linux/io.h>
++#include <linux/ipu-v3.h>
++#include <linux/kernel.h>
++#include <linux/kthread.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/poll.h>
++#include <linux/sched.h>
++#include <linux/sched/rt.h>
++#include <linux/slab.h>
++#include <linux/spinlock.h>
++#include <linux/time.h>
++#include <linux/types.h>
++#include <linux/vmalloc.h>
++#include <linux/wait.h>
++
++#include <asm/cacheflush.h>
++#include <asm/outercache.h>
++
++#include "ipu_param_mem.h"
++#include "ipu_regs.h"
++#include "vdoa.h"
++
++#define CHECK_RETCODE(cont, str, err, label, ret) \
++do { \
++ if (cont) { \
++ dev_err(t->dev, "ERR:[0x%p]-no:0x%x "#str" ret:%d," \
++ "line:%d\n", t, t->task_no, ret, __LINE__);\
++ if (ret != -EACCES) { \
++ t->state = err; \
++ goto label; \
++ } \
++ } \
++} while (0)
++
++#define CHECK_RETCODE_CONT(cont, str, err, ret) \
++do { \
++ if (cont) { \
++ dev_err(t->dev, "ERR:[0x%p]-no:0x%x"#str" ret:%d," \
++ "line:%d\n", t, t->task_no, ret, __LINE__);\
++ if (ret != -EACCES) { \
++ if (t->state == STATE_OK) \
++ t->state = err; \
++ } \
++ } \
++} while (0)
++
++#undef DBG_IPU_PERF
++#ifdef DBG_IPU_PERF
++#define CHECK_PERF(ts) \
++do { \
++ getnstimeofday(ts); \
++} while (0)
++
++#define DECLARE_PERF_VAR \
++ struct timespec ts_queue; \
++ struct timespec ts_dotask; \
++ struct timespec ts_waitirq; \
++ struct timespec ts_sche; \
++ struct timespec ts_rel; \
++ struct timespec ts_frame
++
++#define PRINT_TASK_STATISTICS \
++do { \
++ ts_queue = timespec_sub(tsk->ts_dotask, tsk->ts_queue); \
++ ts_dotask = timespec_sub(tsk->ts_waitirq, tsk->ts_dotask); \
++ ts_waitirq = timespec_sub(tsk->ts_inirq, tsk->ts_waitirq); \
++ ts_sche = timespec_sub(tsk->ts_wakeup, tsk->ts_inirq); \
++ ts_rel = timespec_sub(tsk->ts_rel, tsk->ts_wakeup); \
++ ts_frame = timespec_sub(tsk->ts_rel, tsk->ts_queue); \
++ dev_dbg(tsk->dev, "[0x%p] no-0x%x, ts_q:%ldus, ts_do:%ldus," \
++ "ts_waitirq:%ldus,ts_sche:%ldus, ts_rel:%ldus," \
++ "ts_frame: %ldus\n", tsk, tsk->task_no, \
++ ts_queue.tv_nsec / NSEC_PER_USEC + ts_queue.tv_sec * USEC_PER_SEC,\
++ ts_dotask.tv_nsec / NSEC_PER_USEC + ts_dotask.tv_sec * USEC_PER_SEC,\
++ ts_waitirq.tv_nsec / NSEC_PER_USEC + ts_waitirq.tv_sec * USEC_PER_SEC,\
++ ts_sche.tv_nsec / NSEC_PER_USEC + ts_sche.tv_sec * USEC_PER_SEC,\
++ ts_rel.tv_nsec / NSEC_PER_USEC + ts_rel.tv_sec * USEC_PER_SEC,\
++ ts_frame.tv_nsec / NSEC_PER_USEC + ts_frame.tv_sec * USEC_PER_SEC); \
++ if ((ts_frame.tv_nsec/NSEC_PER_USEC + ts_frame.tv_sec*USEC_PER_SEC) > \
++ 80000) \
++ dev_dbg(tsk->dev, "ts_frame larger than 80ms [0x%p] no-0x%x.\n"\
++ , tsk, tsk->task_no); \
++} while (0)
++#else
++#define CHECK_PERF(ts)
++#define DECLARE_PERF_VAR
++#define PRINT_TASK_STATISTICS
++#endif
++
++#define IPU_PP_CH_VF (IPU_TASK_ID_VF - 1)
++#define IPU_PP_CH_PP (IPU_TASK_ID_PP - 1)
++#define MAX_PP_CH (IPU_TASK_ID_MAX - 1)
++#define VDOA_DEF_TIMEOUT_MS (HZ/2)
++
++/* Strucutures and variables for exporting MXC IPU as device*/
++typedef enum {
++ STATE_OK = 0,
++ STATE_QUEUE,
++ STATE_IN_PROGRESS,
++ STATE_ERR,
++ STATE_TIMEOUT,
++ STATE_RES_TIMEOUT,
++ STATE_NO_IPU,
++ STATE_NO_IRQ,
++ STATE_IPU_BUSY,
++ STATE_IRQ_FAIL,
++ STATE_IRQ_TIMEOUT,
++ STATE_ENABLE_CHAN_FAIL,
++ STATE_DISABLE_CHAN_FAIL,
++ STATE_SEL_BUF_FAIL,
++ STATE_INIT_CHAN_FAIL,
++ STATE_LINK_CHAN_FAIL,
++ STATE_UNLINK_CHAN_FAIL,
++ STATE_INIT_CHAN_BUF_FAIL,
++ STATE_INIT_CHAN_BAND_FAIL,
++ STATE_SYS_NO_MEM,
++ STATE_VDOA_IRQ_TIMEOUT,
++ STATE_VDOA_IRQ_FAIL,
++ STATE_VDOA_TASK_FAIL,
++} ipu_state_t;
++
++enum {
++ INPUT_CHAN_VDI_P = 1,
++ INPUT_CHAN,
++ INPUT_CHAN_VDI_N,
++};
++
++struct ipu_state_msg {
++ int state;
++ char *msg;
++} state_msg[] = {
++ {STATE_OK, "ok"},
++ {STATE_QUEUE, "split queue"},
++ {STATE_IN_PROGRESS, "split in progress"},
++ {STATE_ERR, "error"},
++ {STATE_TIMEOUT, "split task timeout"},
++ {STATE_RES_TIMEOUT, "wait resource timeout"},
++ {STATE_NO_IPU, "no ipu found"},
++ {STATE_NO_IRQ, "no irq found for task"},
++ {STATE_IPU_BUSY, "ipu busy"},
++ {STATE_IRQ_FAIL, "request irq failed"},
++ {STATE_IRQ_TIMEOUT, "wait for irq timeout"},
++ {STATE_ENABLE_CHAN_FAIL, "ipu enable channel fail"},
++ {STATE_DISABLE_CHAN_FAIL, "ipu disable channel fail"},
++ {STATE_SEL_BUF_FAIL, "ipu select buf fail"},
++ {STATE_INIT_CHAN_FAIL, "ipu init channel fail"},
++ {STATE_LINK_CHAN_FAIL, "ipu link channel fail"},
++ {STATE_UNLINK_CHAN_FAIL, "ipu unlink channel fail"},
++ {STATE_INIT_CHAN_BUF_FAIL, "ipu init channel buffer fail"},
++ {STATE_INIT_CHAN_BAND_FAIL, "ipu init channel band mode fail"},
++ {STATE_SYS_NO_MEM, "sys no mem: -ENOMEM"},
++ {STATE_VDOA_IRQ_TIMEOUT, "wait for vdoa irq timeout"},
++ {STATE_VDOA_IRQ_FAIL, "vdoa irq fail"},
++ {STATE_VDOA_TASK_FAIL, "vdoa task fail"},
++};
++
++struct stripe_setting {
++ u32 iw;
++ u32 ih;
++ u32 ow;
++ u32 oh;
++ u32 outh_resize_ratio;
++ u32 outv_resize_ratio;
++ u32 i_left_pos;
++ u32 i_right_pos;
++ u32 i_top_pos;
++ u32 i_bottom_pos;
++ u32 o_left_pos;
++ u32 o_right_pos;
++ u32 o_top_pos;
++ u32 o_bottom_pos;
++ u32 rl_split_line;
++ u32 ud_split_line;
++};
++
++struct task_set {
++#define NULL_MODE 0x0
++#define IC_MODE 0x1
++#define ROT_MODE 0x2
++#define VDI_MODE 0x4
++#define IPU_PREPROCESS_MODE_MASK (IC_MODE | ROT_MODE | VDI_MODE)
++/* VDOA_MODE means this task use vdoa, and VDOA has two modes:
++ * BAND MODE and non-BAND MODE. Non-band mode will do transfer data
++ * to memory. BAND mode needs hareware sync with IPU, it is used default
++ * if connected to VDIC.
++ */
++#define VDOA_MODE 0x8
++#define VDOA_BAND_MODE 0x10
++ u8 mode;
++#define IC_VF 0x1
++#define IC_PP 0x2
++#define ROT_VF 0x4
++#define ROT_PP 0x8
++#define VDI_VF 0x10
++#define VDOA_ONLY 0x20
++ u8 task;
++#define NO_SPLIT 0x0
++#define RL_SPLIT 0x1
++#define UD_SPLIT 0x2
++#define LEFT_STRIPE 0x1
++#define RIGHT_STRIPE 0x2
++#define UP_STRIPE 0x4
++#define DOWN_STRIPE 0x8
++#define SPLIT_MASK 0xF
++ u8 split_mode;
++ u8 band_lines;
++ ipu_channel_t ic_chan;
++ ipu_channel_t rot_chan;
++ ipu_channel_t vdi_ic_p_chan;
++ ipu_channel_t vdi_ic_n_chan;
++
++ u32 i_off;
++ u32 i_uoff;
++ u32 i_voff;
++ u32 istride;
++
++ u32 ov_off;
++ u32 ov_uoff;
++ u32 ov_voff;
++ u32 ovstride;
++
++ u32 ov_alpha_off;
++ u32 ov_alpha_stride;
++
++ u32 o_off;
++ u32 o_uoff;
++ u32 o_voff;
++ u32 ostride;
++
++ u32 r_fmt;
++ u32 r_width;
++ u32 r_height;
++ u32 r_stride;
++ dma_addr_t r_paddr;
++
++ struct stripe_setting sp_setting;
++};
++
++struct ipu_split_task {
++ struct ipu_task task;
++ struct ipu_task_entry *parent_task;
++ struct ipu_task_entry *child_task;
++ u32 task_no;
++};
++
++struct ipu_task_entry {
++ struct ipu_input input;
++ struct ipu_output output;
++
++ bool overlay_en;
++ struct ipu_overlay overlay;
++#define DEF_TIMEOUT_MS 1000
++#define DEF_DELAY_MS 20
++ int timeout;
++ int irq;
++
++ u8 task_id;
++ u8 ipu_id;
++ u8 task_in_list;
++ u8 split_done;
++ struct mutex split_lock;
++ struct mutex vdic_lock;
++ wait_queue_head_t split_waitq;
++
++ struct list_head node;
++ struct list_head split_list;
++ struct ipu_soc *ipu;
++ struct device *dev;
++ struct task_set set;
++ wait_queue_head_t task_waitq;
++ struct completion irq_comp;
++ struct kref refcount;
++ ipu_state_t state;
++ u32 task_no;
++ atomic_t done;
++ atomic_t res_free;
++ atomic_t res_get;
++
++ struct ipu_task_entry *parent;
++ char *vditmpbuf[2];
++ u32 old_save_lines;
++ u32 old_size;
++ bool buf1filled;
++ bool buf0filled;
++
++ vdoa_handle_t vdoa_handle;
++ struct vdoa_output_mem {
++ void *vaddr;
++ dma_addr_t paddr;
++ int size;
++ } vdoa_dma;
++
++#ifdef DBG_IPU_PERF
++ struct timespec ts_queue;
++ struct timespec ts_dotask;
++ struct timespec ts_waitirq;
++ struct timespec ts_inirq;
++ struct timespec ts_wakeup;
++ struct timespec ts_rel;
++#endif
++};
++
++struct ipu_channel_tabel {
++ struct mutex lock;
++ u8 used[MXC_IPU_MAX_NUM][MAX_PP_CH];
++ u8 vdoa_used;
++};
++
++struct ipu_thread_data {
++ struct ipu_soc *ipu;
++ u32 id;
++ u32 is_vdoa;
++};
++
++struct ipu_alloc_list {
++ struct list_head list;
++ dma_addr_t phy_addr;
++ void *cpu_addr;
++ u32 size;
++ void *file_index;
++};
++
++static LIST_HEAD(ipu_alloc_list);
++static DEFINE_MUTEX(ipu_alloc_lock);
++static struct ipu_channel_tabel ipu_ch_tbl;
++static LIST_HEAD(ipu_task_list);
++static DEFINE_SPINLOCK(ipu_task_list_lock);
++static DECLARE_WAIT_QUEUE_HEAD(thread_waitq);
++static DECLARE_WAIT_QUEUE_HEAD(res_waitq);
++static atomic_t req_cnt;
++static atomic_t file_index = ATOMIC_INIT(1);
++static int major;
++static int max_ipu_no;
++static int thread_id;
++static atomic_t frame_no;
++static struct class *ipu_class;
++static struct device *ipu_dev;
++static int debug;
++module_param(debug, int, 0600);
++#ifdef DBG_IPU_PERF
++static struct timespec ts_frame_max;
++static u32 ts_frame_avg;
++static atomic_t frame_cnt;
++#endif
++
++static bool deinterlace_3_field(struct ipu_task_entry *t)
++{
++ return ((t->set.mode & VDI_MODE) &&
++ (t->input.deinterlace.motion != HIGH_MOTION));
++}
++
++static u32 tiled_filed_size(struct ipu_task_entry *t)
++{
++ u32 field_size;
++
++ /* note: page_align is required by VPU hw ouput buffer */
++ field_size = TILED_NV12_FRAME_SIZE(t->input.width, t->input.height/2);
++ return field_size;
++}
++
++static bool only_ic(u8 mode)
++{
++ mode = mode & IPU_PREPROCESS_MODE_MASK;
++ return ((mode == IC_MODE) || (mode == VDI_MODE));
++}
++
++static bool only_rot(u8 mode)
++{
++ mode = mode & IPU_PREPROCESS_MODE_MASK;
++ return (mode == ROT_MODE);
++}
++
++static bool ic_and_rot(u8 mode)
++{
++ mode = mode & IPU_PREPROCESS_MODE_MASK;
++ return ((mode == (IC_MODE | ROT_MODE)) ||
++ (mode == (VDI_MODE | ROT_MODE)));
++}
++
++static bool need_split(struct ipu_task_entry *t)
++{
++ return ((t->set.split_mode != NO_SPLIT) || (t->task_no & SPLIT_MASK));
++}
++
++unsigned int fmt_to_bpp(unsigned int pixelformat)
++{
++ u32 bpp;
++
++ switch (pixelformat) {
++ case IPU_PIX_FMT_RGB565:
++ /*interleaved 422*/
++ case IPU_PIX_FMT_YUYV:
++ case IPU_PIX_FMT_UYVY:
++ /*non-interleaved 422*/
++ case IPU_PIX_FMT_YUV422P:
++ case IPU_PIX_FMT_YVU422P:
++ bpp = 16;
++ break;
++ case IPU_PIX_FMT_BGR24:
++ case IPU_PIX_FMT_RGB24:
++ case IPU_PIX_FMT_YUV444:
++ case IPU_PIX_FMT_YUV444P:
++ bpp = 24;
++ break;
++ case IPU_PIX_FMT_BGR32:
++ case IPU_PIX_FMT_BGRA32:
++ case IPU_PIX_FMT_RGB32:
++ case IPU_PIX_FMT_RGBA32:
++ case IPU_PIX_FMT_ABGR32:
++ bpp = 32;
++ break;
++ /*non-interleaved 420*/
++ case IPU_PIX_FMT_YUV420P:
++ case IPU_PIX_FMT_YVU420P:
++ case IPU_PIX_FMT_YUV420P2:
++ case IPU_PIX_FMT_NV12:
++ bpp = 12;
++ break;
++ default:
++ bpp = 8;
++ break;
++ }
++ return bpp;
++}
++EXPORT_SYMBOL_GPL(fmt_to_bpp);
++
++cs_t colorspaceofpixel(int fmt)
++{
++ switch (fmt) {
++ case IPU_PIX_FMT_RGB565:
++ case IPU_PIX_FMT_RGB666:
++ case IPU_PIX_FMT_BGR24:
++ case IPU_PIX_FMT_RGB24:
++ case IPU_PIX_FMT_BGRA32:
++ case IPU_PIX_FMT_BGR32:
++ case IPU_PIX_FMT_RGBA32:
++ case IPU_PIX_FMT_RGB32:
++ case IPU_PIX_FMT_ABGR32:
++ return RGB_CS;
++ break;
++ case IPU_PIX_FMT_UYVY:
++ case IPU_PIX_FMT_YUYV:
++ case IPU_PIX_FMT_YUV420P2:
++ case IPU_PIX_FMT_YUV420P:
++ case IPU_PIX_FMT_YVU420P:
++ case IPU_PIX_FMT_YVU422P:
++ case IPU_PIX_FMT_YUV422P:
++ case IPU_PIX_FMT_YUV444:
++ case IPU_PIX_FMT_YUV444P:
++ case IPU_PIX_FMT_NV12:
++ case IPU_PIX_FMT_TILED_NV12:
++ case IPU_PIX_FMT_TILED_NV12F:
++ return YUV_CS;
++ break;
++ default:
++ return NULL_CS;
++ }
++}
++EXPORT_SYMBOL_GPL(colorspaceofpixel);
++
++int need_csc(int ifmt, int ofmt)
++{
++ cs_t ics, ocs;
++
++ ics = colorspaceofpixel(ifmt);
++ ocs = colorspaceofpixel(ofmt);
++
++ if ((ics == NULL_CS) || (ocs == NULL_CS))
++ return -1;
++ else if (ics != ocs)
++ return 1;
++
++ return 0;
++}
++EXPORT_SYMBOL_GPL(need_csc);
++
++static int soc_max_in_width(u32 is_vdoa)
++{
++ return is_vdoa ? 8192 : 4096;
++}
++
++static int soc_max_vdi_in_width(void)
++{
++ return IPU_MAX_VDI_IN_WIDTH;
++}
++static int soc_max_in_height(void)
++{
++ return 4096;
++}
++
++static int soc_max_out_width(void)
++{
++ /* mx51/mx53/mx6q is 1024*/
++ return 1024;
++}
++
++static int soc_max_out_height(void)
++{
++ /* mx51/mx53/mx6q is 1024*/
++ return 1024;
++}
++
++static void dump_task_info(struct ipu_task_entry *t)
++{
++ if (!debug)
++ return;
++ dev_dbg(t->dev, "[0x%p]input:\n", (void *)t);
++ dev_dbg(t->dev, "[0x%p]\tformat = 0x%x\n", (void *)t, t->input.format);
++ dev_dbg(t->dev, "[0x%p]\twidth = %d\n", (void *)t, t->input.width);
++ dev_dbg(t->dev, "[0x%p]\theight = %d\n", (void *)t, t->input.height);
++ dev_dbg(t->dev, "[0x%p]\tcrop.w = %d\n", (void *)t, t->input.crop.w);
++ dev_dbg(t->dev, "[0x%p]\tcrop.h = %d\n", (void *)t, t->input.crop.h);
++ dev_dbg(t->dev, "[0x%p]\tcrop.pos.x = %d\n",
++ (void *)t, t->input.crop.pos.x);
++ dev_dbg(t->dev, "[0x%p]\tcrop.pos.y = %d\n",
++ (void *)t, t->input.crop.pos.y);
++ dev_dbg(t->dev, "[0x%p]input buffer:\n", (void *)t);
++ dev_dbg(t->dev, "[0x%p]\tpaddr = 0x%x\n", (void *)t, t->input.paddr);
++ dev_dbg(t->dev, "[0x%p]\ti_off = 0x%x\n", (void *)t, t->set.i_off);
++ dev_dbg(t->dev, "[0x%p]\ti_uoff = 0x%x\n", (void *)t, t->set.i_uoff);
++ dev_dbg(t->dev, "[0x%p]\ti_voff = 0x%x\n", (void *)t, t->set.i_voff);
++ dev_dbg(t->dev, "[0x%p]\tistride = %d\n", (void *)t, t->set.istride);
++ if (t->input.deinterlace.enable) {
++ dev_dbg(t->dev, "[0x%p]deinterlace enabled with:\n", (void *)t);
++ if (t->input.deinterlace.motion != HIGH_MOTION) {
++ dev_dbg(t->dev, "[0x%p]\tlow/medium motion\n", (void *)t);
++ dev_dbg(t->dev, "[0x%p]\tpaddr_n = 0x%x\n",
++ (void *)t, t->input.paddr_n);
++ } else
++ dev_dbg(t->dev, "[0x%p]\thigh motion\n", (void *)t);
++ }
++
++ dev_dbg(t->dev, "[0x%p]output:\n", (void *)t);
++ dev_dbg(t->dev, "[0x%p]\tformat = 0x%x\n", (void *)t, t->output.format);
++ dev_dbg(t->dev, "[0x%p]\twidth = %d\n", (void *)t, t->output.width);
++ dev_dbg(t->dev, "[0x%p]\theight = %d\n", (void *)t, t->output.height);
++ dev_dbg(t->dev, "[0x%p]\tcrop.w = %d\n", (void *)t, t->output.crop.w);
++ dev_dbg(t->dev, "[0x%p]\tcrop.h = %d\n", (void *)t, t->output.crop.h);
++ dev_dbg(t->dev, "[0x%p]\tcrop.pos.x = %d\n",
++ (void *)t, t->output.crop.pos.x);
++ dev_dbg(t->dev, "[0x%p]\tcrop.pos.y = %d\n",
++ (void *)t, t->output.crop.pos.y);
++ dev_dbg(t->dev, "[0x%p]\trotate = %d\n", (void *)t, t->output.rotate);
++ dev_dbg(t->dev, "[0x%p]output buffer:\n", (void *)t);
++ dev_dbg(t->dev, "[0x%p]\tpaddr = 0x%x\n", (void *)t, t->output.paddr);
++ dev_dbg(t->dev, "[0x%p]\to_off = 0x%x\n", (void *)t, t->set.o_off);
++ dev_dbg(t->dev, "[0x%p]\to_uoff = 0x%x\n", (void *)t, t->set.o_uoff);
++ dev_dbg(t->dev, "[0x%p]\to_voff = 0x%x\n", (void *)t, t->set.o_voff);
++ dev_dbg(t->dev, "[0x%p]\tostride = %d\n", (void *)t, t->set.ostride);
++
++ if (t->overlay_en) {
++ dev_dbg(t->dev, "[0x%p]overlay:\n", (void *)t);
++ dev_dbg(t->dev, "[0x%p]\tformat = 0x%x\n",
++ (void *)t, t->overlay.format);
++ dev_dbg(t->dev, "[0x%p]\twidth = %d\n",
++ (void *)t, t->overlay.width);
++ dev_dbg(t->dev, "[0x%p]\theight = %d\n",
++ (void *)t, t->overlay.height);
++ dev_dbg(t->dev, "[0x%p]\tcrop.w = %d\n",
++ (void *)t, t->overlay.crop.w);
++ dev_dbg(t->dev, "[0x%p]\tcrop.h = %d\n",
++ (void *)t, t->overlay.crop.h);
++ dev_dbg(t->dev, "[0x%p]\tcrop.pos.x = %d\n",
++ (void *)t, t->overlay.crop.pos.x);
++ dev_dbg(t->dev, "[0x%p]\tcrop.pos.y = %d\n",
++ (void *)t, t->overlay.crop.pos.y);
++ dev_dbg(t->dev, "[0x%p]overlay buffer:\n", (void *)t);
++ dev_dbg(t->dev, "[0x%p]\tpaddr = 0x%x\n",
++ (void *)t, t->overlay.paddr);
++ dev_dbg(t->dev, "[0x%p]\tov_off = 0x%x\n",
++ (void *)t, t->set.ov_off);
++ dev_dbg(t->dev, "[0x%p]\tov_uoff = 0x%x\n",
++ (void *)t, t->set.ov_uoff);
++ dev_dbg(t->dev, "[0x%p]\tov_voff = 0x%x\n",
++ (void *)t, t->set.ov_voff);
++ dev_dbg(t->dev, "[0x%p]\tovstride = %d\n",
++ (void *)t, t->set.ovstride);
++ if (t->overlay.alpha.mode == IPU_ALPHA_MODE_LOCAL) {
++ dev_dbg(t->dev, "[0x%p]local alpha enabled with:\n",
++ (void *)t);
++ dev_dbg(t->dev, "[0x%p]\tpaddr = 0x%x\n",
++ (void *)t, t->overlay.alpha.loc_alp_paddr);
++ dev_dbg(t->dev, "[0x%p]\tov_alpha_off = 0x%x\n",
++ (void *)t, t->set.ov_alpha_off);
++ dev_dbg(t->dev, "[0x%p]\tov_alpha_stride = %d\n",
++ (void *)t, t->set.ov_alpha_stride);
++ } else
++ dev_dbg(t->dev, "[0x%p]globle alpha enabled with value 0x%x\n",
++ (void *)t, t->overlay.alpha.gvalue);
++ if (t->overlay.colorkey.enable)
++ dev_dbg(t->dev, "[0x%p]colorkey enabled with value 0x%x\n",
++ (void *)t, t->overlay.colorkey.value);
++ }
++
++ dev_dbg(t->dev, "[0x%p]want task_id = %d\n", (void *)t, t->task_id);
++ dev_dbg(t->dev, "[0x%p]want task mode is 0x%x\n",
++ (void *)t, t->set.mode);
++ dev_dbg(t->dev, "[0x%p]\tIC_MODE = 0x%x\n", (void *)t, IC_MODE);
++ dev_dbg(t->dev, "[0x%p]\tROT_MODE = 0x%x\n", (void *)t, ROT_MODE);
++ dev_dbg(t->dev, "[0x%p]\tVDI_MODE = 0x%x\n", (void *)t, VDI_MODE);
++ dev_dbg(t->dev, "[0x%p]\tTask_no = 0x%x\n\n\n", (void *)t, t->task_no);
++}
++
++static void dump_check_err(struct device *dev, int err)
++{
++ switch (err) {
++ case IPU_CHECK_ERR_INPUT_CROP:
++ dev_err(dev, "input crop setting error\n");
++ break;
++ case IPU_CHECK_ERR_OUTPUT_CROP:
++ dev_err(dev, "output crop setting error\n");
++ break;
++ case IPU_CHECK_ERR_OVERLAY_CROP:
++ dev_err(dev, "overlay crop setting error\n");
++ break;
++ case IPU_CHECK_ERR_INPUT_OVER_LIMIT:
++ dev_err(dev, "input over limitation\n");
++ break;
++ case IPU_CHECK_ERR_OVERLAY_WITH_VDI:
++ dev_err(dev, "do not support overlay with deinterlace\n");
++ break;
++ case IPU_CHECK_ERR_OV_OUT_NO_FIT:
++ dev_err(dev,
++ "width/height of overlay and ic output should be same\n");
++ break;
++ case IPU_CHECK_ERR_PROC_NO_NEED:
++ dev_err(dev, "no ipu processing need\n");
++ break;
++ case IPU_CHECK_ERR_SPLIT_INPUTW_OVER:
++ dev_err(dev, "split mode input width overflow\n");
++ break;
++ case IPU_CHECK_ERR_SPLIT_INPUTH_OVER:
++ dev_err(dev, "split mode input height overflow\n");
++ break;
++ case IPU_CHECK_ERR_SPLIT_OUTPUTW_OVER:
++ dev_err(dev, "split mode output width overflow\n");
++ break;
++ case IPU_CHECK_ERR_SPLIT_OUTPUTH_OVER:
++ dev_err(dev, "split mode output height overflow\n");
++ break;
++ case IPU_CHECK_ERR_SPLIT_WITH_ROT:
++ dev_err(dev, "not support split mode with rotation\n");
++ break;
++ case IPU_CHECK_ERR_W_DOWNSIZE_OVER:
++ dev_err(dev, "horizontal downsizing ratio overflow\n");
++ break;
++ case IPU_CHECK_ERR_H_DOWNSIZE_OVER:
++ dev_err(dev, "vertical downsizing ratio overflow\n");
++ break;
++ default:
++ break;
++ }
++}
++
++static void dump_check_warn(struct device *dev, int warn)
++{
++ if (warn & IPU_CHECK_WARN_INPUT_OFFS_NOT8ALIGN)
++ dev_warn(dev, "input u/v offset not 8 align\n");
++ if (warn & IPU_CHECK_WARN_OUTPUT_OFFS_NOT8ALIGN)
++ dev_warn(dev, "output u/v offset not 8 align\n");
++ if (warn & IPU_CHECK_WARN_OVERLAY_OFFS_NOT8ALIGN)
++ dev_warn(dev, "overlay u/v offset not 8 align\n");
++}
++
++static int set_crop(struct ipu_crop *crop, int width, int height, int fmt)
++{
++ if ((width == 0) || (height == 0)) {
++ pr_err("Invalid param: width=%d, height=%d\n", width, height);
++ return -EINVAL;
++ }
++
++ if ((IPU_PIX_FMT_TILED_NV12 == fmt) ||
++ (IPU_PIX_FMT_TILED_NV12F == fmt)) {
++ if (crop->w || crop->h) {
++ if (((crop->w + crop->pos.x) > width)
++ || ((crop->h + crop->pos.y) > height)
++ || (0 != (crop->w % IPU_PIX_FMT_TILED_NV12_MBALIGN))
++ || (0 != (crop->h % IPU_PIX_FMT_TILED_NV12_MBALIGN))
++ || (0 != (crop->pos.x % IPU_PIX_FMT_TILED_NV12_MBALIGN))
++ || (0 != (crop->pos.y % IPU_PIX_FMT_TILED_NV12_MBALIGN))
++ ) {
++ pr_err("set_crop error MB align.\n");
++ return -EINVAL;
++ }
++ } else {
++ crop->pos.x = 0;
++ crop->pos.y = 0;
++ crop->w = width;
++ crop->h = height;
++ if ((0 != (crop->w % IPU_PIX_FMT_TILED_NV12_MBALIGN))
++ || (0 != (crop->h % IPU_PIX_FMT_TILED_NV12_MBALIGN))) {
++ pr_err("set_crop error w/h MB align.\n");
++ return -EINVAL;
++ }
++ }
++ } else {
++ if (crop->w || crop->h) {
++ if (((crop->w + crop->pos.x) > (width + 16))
++ || ((crop->h + crop->pos.y) > height + 16)) {
++ pr_err("set_crop error exceeds width/height.\n");
++ return -EINVAL;
++ }
++ } else {
++ crop->pos.x = 0;
++ crop->pos.y = 0;
++ crop->w = width;
++ crop->h = height;
++ }
++ crop->w -= crop->w%8;
++ crop->h -= crop->h%8;
++ }
++
++ if ((crop->w == 0) || (crop->h == 0)) {
++ pr_err("Invalid crop param: crop.w=%d, crop.h=%d\n",
++ crop->w, crop->h);
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++static void update_offset(unsigned int fmt,
++ unsigned int width, unsigned int height,
++ unsigned int pos_x, unsigned int pos_y,
++ int *off, int *uoff, int *voff, int *stride)
++{
++ /* NOTE: u v offset should based on start point of off*/
++ switch (fmt) {
++ case IPU_PIX_FMT_YUV420P2:
++ case IPU_PIX_FMT_YUV420P:
++ *off = pos_y * width + pos_x;
++ *uoff = (width * (height - pos_y) - pos_x)
++ + (width/2) * (pos_y/2) + pos_x/2;
++ /* In case height is odd, round up to even */
++ *voff = *uoff + (width/2) * ((height+1)/2);
++ break;
++ case IPU_PIX_FMT_YVU420P:
++ *off = pos_y * width + pos_x;
++ *voff = (width * (height - pos_y) - pos_x)
++ + (width/2) * (pos_y/2) + pos_x/2;
++ /* In case height is odd, round up to even */
++ *uoff = *voff + (width/2) * ((height+1)/2);
++ break;
++ case IPU_PIX_FMT_YVU422P:
++ *off = pos_y * width + pos_x;
++ *voff = (width * (height - pos_y) - pos_x)
++ + (width/2) * pos_y + pos_x/2;
++ *uoff = *voff + (width/2) * height;
++ break;
++ case IPU_PIX_FMT_YUV422P:
++ *off = pos_y * width + pos_x;
++ *uoff = (width * (height - pos_y) - pos_x)
++ + (width/2) * pos_y + pos_x/2;
++ *voff = *uoff + (width/2) * height;
++ break;
++ case IPU_PIX_FMT_YUV444P:
++ *off = pos_y * width + pos_x;
++ *uoff = width * height;
++ *voff = width * height * 2;
++ break;
++ case IPU_PIX_FMT_NV12:
++ *off = pos_y * width + pos_x;
++ *uoff = (width * (height - pos_y) - pos_x)
++ + width * (pos_y/2) + pos_x;
++ break;
++ case IPU_PIX_FMT_TILED_NV12:
++ /*
++ * tiled format, progressive:
++ * assuming that line is aligned with MB height (aligned to 16)
++ * offset = line * stride + (pixel / MB_width) * pixels_in_MB
++ * = line * stride + (pixel / 16) * 256
++ * = line * stride + pixel * 16
++ */
++ *off = pos_y * width + (pos_x << 4);
++ *uoff = ALIGN(width * height, SZ_4K) + (*off >> 1) - *off;
++ break;
++ case IPU_PIX_FMT_TILED_NV12F:
++ /*
++ * tiled format, interlaced:
++ * same as above, only number of pixels in MB is 128,
++ * instead of 256
++ */
++ *off = (pos_y >> 1) * width + (pos_x << 3);
++ *uoff = ALIGN(width * height/2, SZ_4K) + (*off >> 1) - *off;
++ break;
++ default:
++ *off = (pos_y * width + pos_x) * fmt_to_bpp(fmt)/8;
++ break;
++ }
++ *stride = width * bytes_per_pixel(fmt);
++}
++
++static int update_split_setting(struct ipu_task_entry *t, bool vdi_split)
++{
++ struct stripe_param left_stripe;
++ struct stripe_param right_stripe;
++ struct stripe_param up_stripe;
++ struct stripe_param down_stripe;
++ u32 iw, ih, ow, oh;
++ u32 max_width;
++ int ret;
++
++ if (t->output.rotate >= IPU_ROTATE_90_RIGHT)
++ return IPU_CHECK_ERR_SPLIT_WITH_ROT;
++
++ iw = t->input.crop.w;
++ ih = t->input.crop.h;
++
++ ow = t->output.crop.w;
++ oh = t->output.crop.h;
++
++ memset(&left_stripe, 0, sizeof(left_stripe));
++ memset(&right_stripe, 0, sizeof(right_stripe));
++ memset(&up_stripe, 0, sizeof(up_stripe));
++ memset(&down_stripe, 0, sizeof(down_stripe));
++
++ if (t->set.split_mode & RL_SPLIT) {
++ /*
++ * We do want equal strips: initialize stripes in case
++ * calc_stripes returns before actually doing the calculation
++ */
++ left_stripe.input_width = iw / 2;
++ left_stripe.output_width = ow / 2;
++ right_stripe.input_column = iw / 2;
++ right_stripe.output_column = ow / 2;
++
++ if (vdi_split)
++ max_width = soc_max_vdi_in_width();
++ else
++ max_width = soc_max_out_width();
++ ret = ipu_calc_stripes_sizes(iw,
++ ow,
++ max_width,
++ (((unsigned long long)1) << 32), /* 32bit for fractional*/
++ 1, /* equal stripes */
++ t->input.format,
++ t->output.format,
++ &left_stripe,
++ &right_stripe);
++ if (ret < 0)
++ return IPU_CHECK_ERR_W_DOWNSIZE_OVER;
++ else if (ret)
++ dev_dbg(t->dev, "Warn: no:0x%x,calc_stripes ret:%d\n",
++ t->task_no, ret);
++ t->set.sp_setting.iw = left_stripe.input_width;
++ t->set.sp_setting.ow = left_stripe.output_width;
++ t->set.sp_setting.outh_resize_ratio = left_stripe.irr;
++ t->set.sp_setting.i_left_pos = left_stripe.input_column;
++ t->set.sp_setting.o_left_pos = left_stripe.output_column;
++ t->set.sp_setting.i_right_pos = right_stripe.input_column;
++ t->set.sp_setting.o_right_pos = right_stripe.output_column;
++ } else {
++ t->set.sp_setting.iw = iw;
++ t->set.sp_setting.ow = ow;
++ t->set.sp_setting.outh_resize_ratio = 0;
++ t->set.sp_setting.i_left_pos = 0;
++ t->set.sp_setting.o_left_pos = 0;
++ t->set.sp_setting.i_right_pos = 0;
++ t->set.sp_setting.o_right_pos = 0;
++ }
++ if ((t->set.sp_setting.iw + t->set.sp_setting.i_right_pos) > (iw+16))
++ return IPU_CHECK_ERR_SPLIT_INPUTW_OVER;
++ if (((t->set.sp_setting.ow + t->set.sp_setting.o_right_pos) > ow)
++ || (t->set.sp_setting.ow > soc_max_out_width()))
++ return IPU_CHECK_ERR_SPLIT_OUTPUTW_OVER;
++ if (rounddown(t->set.sp_setting.ow, 8) * 8 <=
++ rounddown(t->set.sp_setting.iw, 8))
++ return IPU_CHECK_ERR_W_DOWNSIZE_OVER;
++
++ if (t->set.split_mode & UD_SPLIT) {
++ /*
++ * We do want equal strips: initialize stripes in case
++ * calc_stripes returns before actually doing the calculation
++ */
++ up_stripe.input_width = ih / 2;
++ up_stripe.output_width = oh / 2;
++ down_stripe.input_column = ih / 2;
++ down_stripe.output_column = oh / 2;
++ ret = ipu_calc_stripes_sizes(ih,
++ oh,
++ soc_max_out_height(),
++ (((unsigned long long)1) << 32), /* 32bit for fractional*/
++ 0x1 | 0x2, /* equal stripes and vertical */
++ t->input.format,
++ t->output.format,
++ &up_stripe,
++ &down_stripe);
++ if (ret < 0)
++ return IPU_CHECK_ERR_H_DOWNSIZE_OVER;
++ else if (ret)
++ dev_err(t->dev, "Warn: no:0x%x,calc_stripes ret:%d\n",
++ t->task_no, ret);
++ t->set.sp_setting.ih = up_stripe.input_width;
++ t->set.sp_setting.oh = up_stripe.output_width;
++ t->set.sp_setting.outv_resize_ratio = up_stripe.irr;
++ t->set.sp_setting.i_top_pos = up_stripe.input_column;
++ t->set.sp_setting.o_top_pos = up_stripe.output_column;
++ t->set.sp_setting.i_bottom_pos = down_stripe.input_column;
++ t->set.sp_setting.o_bottom_pos = down_stripe.output_column;
++ } else {
++ t->set.sp_setting.ih = ih;
++ t->set.sp_setting.oh = oh;
++ t->set.sp_setting.outv_resize_ratio = 0;
++ t->set.sp_setting.i_top_pos = 0;
++ t->set.sp_setting.o_top_pos = 0;
++ t->set.sp_setting.i_bottom_pos = 0;
++ t->set.sp_setting.o_bottom_pos = 0;
++ }
++
++ /* downscale case: enforce limits */
++ if (((t->set.sp_setting.ih + t->set.sp_setting.i_bottom_pos) > (ih))
++ && (t->set.sp_setting.ih >= t->set.sp_setting.oh))
++ return IPU_CHECK_ERR_SPLIT_INPUTH_OVER;
++ /* upscale case: relax limits because ipu_calc_stripes_sizes() may
++ create input stripe that falls just outside of the input window */
++ else if ((t->set.sp_setting.ih + t->set.sp_setting.i_bottom_pos)
++ > (ih+16))
++ return IPU_CHECK_ERR_SPLIT_INPUTH_OVER;
++ if (((t->set.sp_setting.oh + t->set.sp_setting.o_bottom_pos) > oh)
++ || (t->set.sp_setting.oh > soc_max_out_height()))
++ return IPU_CHECK_ERR_SPLIT_OUTPUTH_OVER;
++ if (rounddown(t->set.sp_setting.oh, 8) * 8 <=
++ rounddown(t->set.sp_setting.ih, 8))
++ return IPU_CHECK_ERR_H_DOWNSIZE_OVER;
++
++ return IPU_CHECK_OK;
++}
++
++static int check_task(struct ipu_task_entry *t)
++{
++ int tmp;
++ int ret = IPU_CHECK_OK;
++ int timeout;
++ bool vdi_split = false;
++ int ocw, och;
++
++ if ((IPU_PIX_FMT_TILED_NV12 == t->overlay.format) ||
++ (IPU_PIX_FMT_TILED_NV12F == t->overlay.format) ||
++ (IPU_PIX_FMT_TILED_NV12 == t->output.format) ||
++ (IPU_PIX_FMT_TILED_NV12F == t->output.format) ||
++ ((IPU_PIX_FMT_TILED_NV12F == t->input.format) &&
++ !t->input.deinterlace.enable)) {
++ ret = IPU_CHECK_ERR_NOT_SUPPORT;
++ goto done;
++ }
++
++ /* check input */
++ ret = set_crop(&t->input.crop, t->input.width, t->input.height,
++ t->input.format);
++ if (ret < 0) {
++ ret = IPU_CHECK_ERR_INPUT_CROP;
++ goto done;
++ } else
++ update_offset(t->input.format, t->input.width, t->input.height,
++ t->input.crop.pos.x, t->input.crop.pos.y,
++ &t->set.i_off, &t->set.i_uoff,
++ &t->set.i_voff, &t->set.istride);
++
++ /* check output */
++ ret = set_crop(&t->output.crop, t->output.width, t->output.height,
++ t->output.format);
++ if (ret < 0) {
++ ret = IPU_CHECK_ERR_OUTPUT_CROP;
++ goto done;
++ } else
++ update_offset(t->output.format,
++ t->output.width, t->output.height,
++ t->output.crop.pos.x, t->output.crop.pos.y,
++ &t->set.o_off, &t->set.o_uoff,
++ &t->set.o_voff, &t->set.ostride);
++
++ if (t->output.rotate >= IPU_ROTATE_90_RIGHT) {
++ /*
++ * Cache output width and height and
++ * swap them so that we may check
++ * downsize overflow correctly.
++ */
++ ocw = t->output.crop.h;
++ och = t->output.crop.w;
++ } else {
++ ocw = t->output.crop.w;
++ och = t->output.crop.h;
++ }
++
++ if (ocw * 8 <= t->input.crop.w) {
++ ret = IPU_CHECK_ERR_W_DOWNSIZE_OVER;
++ goto done;
++ }
++
++ if (och * 8 <= t->input.crop.h) {
++ ret = IPU_CHECK_ERR_H_DOWNSIZE_OVER;
++ goto done;
++ }
++
++ if ((IPU_PIX_FMT_TILED_NV12 == t->input.format) ||
++ (IPU_PIX_FMT_TILED_NV12F == t->input.format)) {
++ if ((t->input.crop.w > soc_max_in_width(1)) ||
++ (t->input.crop.h > soc_max_in_height())) {
++ ret = IPU_CHECK_ERR_INPUT_OVER_LIMIT;
++ goto done;
++ }
++ /* output fmt: NV12 and YUYV, now don't support resize */
++ if (((IPU_PIX_FMT_NV12 != t->output.format) &&
++ (IPU_PIX_FMT_YUYV != t->output.format)) ||
++ (t->input.crop.w != t->output.crop.w) ||
++ (t->input.crop.h != t->output.crop.h)) {
++ ret = IPU_CHECK_ERR_NOT_SUPPORT;
++ goto done;
++ }
++ }
++
++ /* check overlay if there is */
++ if (t->overlay_en) {
++ if (t->input.deinterlace.enable) {
++ ret = IPU_CHECK_ERR_OVERLAY_WITH_VDI;
++ goto done;
++ }
++
++ ret = set_crop(&t->overlay.crop, t->overlay.width,
++ t->overlay.height, t->overlay.format);
++ if (ret < 0) {
++ ret = IPU_CHECK_ERR_OVERLAY_CROP;
++ goto done;
++ } else {
++ ocw = t->output.crop.w;
++ och = t->output.crop.h;
++
++ if (t->output.rotate >= IPU_ROTATE_90_RIGHT) {
++ ocw = t->output.crop.h;
++ och = t->output.crop.w;
++ }
++ if ((t->overlay.crop.w != ocw) ||
++ (t->overlay.crop.h != och)) {
++ ret = IPU_CHECK_ERR_OV_OUT_NO_FIT;
++ goto done;
++ }
++
++ update_offset(t->overlay.format,
++ t->overlay.width, t->overlay.height,
++ t->overlay.crop.pos.x, t->overlay.crop.pos.y,
++ &t->set.ov_off, &t->set.ov_uoff,
++ &t->set.ov_voff, &t->set.ovstride);
++ if (t->overlay.alpha.mode == IPU_ALPHA_MODE_LOCAL) {
++ t->set.ov_alpha_stride = t->overlay.width;
++ t->set.ov_alpha_off = t->overlay.crop.pos.y *
++ t->overlay.width + t->overlay.crop.pos.x;
++ }
++ }
++ }
++
++ /* input overflow? */
++ if (!((IPU_PIX_FMT_TILED_NV12 == t->input.format) ||
++ (IPU_PIX_FMT_TILED_NV12F == t->input.format))) {
++ if ((t->input.crop.w > soc_max_in_width(0)) ||
++ (t->input.crop.h > soc_max_in_height())) {
++ ret = IPU_CHECK_ERR_INPUT_OVER_LIMIT;
++ goto done;
++ }
++ }
++
++ /* check task mode */
++ t->set.mode = NULL_MODE;
++ t->set.split_mode = NO_SPLIT;
++
++ if (t->output.rotate >= IPU_ROTATE_90_RIGHT) {
++ /*output swap*/
++ tmp = t->output.crop.w;
++ t->output.crop.w = t->output.crop.h;
++ t->output.crop.h = tmp;
++ }
++
++ if (t->output.rotate >= IPU_ROTATE_90_RIGHT)
++ t->set.mode |= ROT_MODE;
++
++ /*need resize or CSC?*/
++ if ((t->input.crop.w != t->output.crop.w) ||
++ (t->input.crop.h != t->output.crop.h) ||
++ need_csc(t->input.format, t->output.format))
++ t->set.mode |= IC_MODE;
++
++ /*need cropping?*/
++ if ((t->input.crop.w != t->input.width) ||
++ (t->input.crop.h != t->input.height) ||
++ (t->output.crop.w != t->output.width) ||
++ (t->output.crop.h != t->output.height))
++ t->set.mode |= IC_MODE;
++
++ /*need flip?*/
++ if ((t->set.mode == NULL_MODE) && (t->output.rotate > IPU_ROTATE_NONE))
++ t->set.mode |= IC_MODE;
++
++ /*need IDMAC do format(same color space)?*/
++ if ((t->set.mode == NULL_MODE) && (t->input.format != t->output.format))
++ t->set.mode |= IC_MODE;
++
++ /*overlay support*/
++ if (t->overlay_en)
++ t->set.mode |= IC_MODE;
++
++ /*deinterlace*/
++ if (t->input.deinterlace.enable) {
++ t->set.mode &= ~IC_MODE;
++ t->set.mode |= VDI_MODE;
++ }
++ if ((IPU_PIX_FMT_TILED_NV12 == t->input.format) ||
++ (IPU_PIX_FMT_TILED_NV12F == t->input.format)) {
++ if (t->set.mode & ROT_MODE) {
++ ret = IPU_CHECK_ERR_NOT_SUPPORT;
++ goto done;
++ }
++ t->set.mode |= VDOA_MODE;
++ if (IPU_PIX_FMT_TILED_NV12F == t->input.format)
++ t->set.mode |= VDOA_BAND_MODE;
++ t->set.mode &= ~IC_MODE;
++ }
++
++ if ((t->set.mode & (IC_MODE | VDI_MODE)) &&
++ (IPU_PIX_FMT_TILED_NV12F != t->input.format)) {
++ if (t->output.crop.w > soc_max_out_width())
++ t->set.split_mode |= RL_SPLIT;
++ if (t->output.crop.h > soc_max_out_height())
++ t->set.split_mode |= UD_SPLIT;
++ if (!t->set.split_mode && (t->set.mode & VDI_MODE) &&
++ (t->input.crop.w > soc_max_vdi_in_width())) {
++ t->set.split_mode |= RL_SPLIT;
++ vdi_split = true;
++ }
++ if (t->set.split_mode) {
++ if ((t->set.split_mode == RL_SPLIT) ||
++ (t->set.split_mode == UD_SPLIT))
++ timeout = DEF_TIMEOUT_MS * 2 + DEF_DELAY_MS;
++ else
++ timeout = DEF_TIMEOUT_MS * 4 + DEF_DELAY_MS;
++ if (t->timeout < timeout)
++ t->timeout = timeout;
++
++ ret = update_split_setting(t, vdi_split);
++ if (ret > IPU_CHECK_ERR_MIN)
++ goto done;
++ }
++ }
++
++ if (t->output.rotate >= IPU_ROTATE_90_RIGHT) {
++ /*output swap*/
++ tmp = t->output.crop.w;
++ t->output.crop.w = t->output.crop.h;
++ t->output.crop.h = tmp;
++ }
++
++ if (t->set.mode == NULL_MODE) {
++ ret = IPU_CHECK_ERR_PROC_NO_NEED;
++ goto done;
++ }
++
++ if ((t->set.i_uoff % 8) || (t->set.i_voff % 8))
++ ret |= IPU_CHECK_WARN_INPUT_OFFS_NOT8ALIGN;
++ if ((t->set.o_uoff % 8) || (t->set.o_voff % 8))
++ ret |= IPU_CHECK_WARN_OUTPUT_OFFS_NOT8ALIGN;
++ if (t->overlay_en && ((t->set.ov_uoff % 8) || (t->set.ov_voff % 8)))
++ ret |= IPU_CHECK_WARN_OVERLAY_OFFS_NOT8ALIGN;
++
++done:
++ /* dump msg */
++ if (debug) {
++ if (ret > IPU_CHECK_ERR_MIN)
++ dump_check_err(t->dev, ret);
++ else if (ret != IPU_CHECK_OK)
++ dump_check_warn(t->dev, ret);
++ }
++
++ return ret;
++}
++
++static int prepare_task(struct ipu_task_entry *t)
++{
++ int ret = 0;
++
++ ret = check_task(t);
++ if (ret > IPU_CHECK_ERR_MIN)
++ return -EINVAL;
++
++ if (t->set.mode & VDI_MODE) {
++ t->task_id = IPU_TASK_ID_VF;
++ t->set.task = VDI_VF;
++ if (t->set.mode & ROT_MODE)
++ t->set.task |= ROT_VF;
++ }
++
++ if (VDOA_MODE == t->set.mode) {
++ if (t->set.task != 0) {
++ dev_err(t->dev, "ERR: vdoa only task:0x%x, [0x%p].\n",
++ t->set.task, t);
++ return -EINVAL;
++ }
++ t->set.task |= VDOA_ONLY;
++ }
++
++ if (VDOA_BAND_MODE & t->set.mode) {
++ /* to save band size: 1<<3 = 8 lines */
++ t->set.band_lines = 3;
++ }
++
++ dump_task_info(t);
++
++ return ret;
++}
++
++static uint32_t ic_vf_pp_is_busy(struct ipu_soc *ipu, bool is_vf)
++{
++ uint32_t status;
++ uint32_t status_vf;
++ uint32_t status_rot;
++
++ if (is_vf) {
++ status = ipu_channel_status(ipu, MEM_VDI_PRP_VF_MEM);
++ status_vf = ipu_channel_status(ipu, MEM_PRP_VF_MEM);
++ status_rot = ipu_channel_status(ipu, MEM_ROT_VF_MEM);
++ return status || status_vf || status_rot;
++ } else {
++ status = ipu_channel_status(ipu, MEM_PP_MEM);
++ status_rot = ipu_channel_status(ipu, MEM_ROT_PP_MEM);
++ return status || status_rot;
++ }
++}
++
++static int _get_vdoa_ipu_res(struct ipu_task_entry *t)
++{
++ int i;
++ struct ipu_soc *ipu;
++ u8 *used;
++ uint32_t found_ipu = 0;
++ uint32_t found_vdoa = 0;
++ struct ipu_channel_tabel *tbl = &ipu_ch_tbl;
++
++ mutex_lock(&tbl->lock);
++ if (t->set.mode & VDOA_MODE) {
++ if (NULL != t->vdoa_handle)
++ found_vdoa = 1;
++ else {
++ found_vdoa = tbl->vdoa_used ? 0 : 1;
++ if (found_vdoa) {
++ tbl->vdoa_used = 1;
++ vdoa_get_handle(&t->vdoa_handle);
++ } else
++ /* first get vdoa->ipu resource sequence */
++ goto out;
++ if (t->set.task & VDOA_ONLY)
++ goto out;
++ }
++ }
++
++ for (i = 0; i < max_ipu_no; i++) {
++ ipu = ipu_get_soc(i);
++ if (IS_ERR(ipu))
++ dev_err(t->dev, "no:0x%x,found_vdoa:%d, ipu:%d\n",
++ t->task_no, found_vdoa, i);
++
++ used = &tbl->used[i][IPU_PP_CH_VF];
++ if (t->set.mode & VDI_MODE) {
++ if (0 == *used) {
++ *used = 1;
++ found_ipu = 1;
++ break;
++ }
++ } else if ((t->set.mode & IC_MODE) || only_rot(t->set.mode)) {
++ if (0 == *used) {
++ t->task_id = IPU_TASK_ID_VF;
++ if (t->set.mode & IC_MODE)
++ t->set.task |= IC_VF;
++ if (t->set.mode & ROT_MODE)
++ t->set.task |= ROT_VF;
++ *used = 1;
++ found_ipu = 1;
++ break;
++ }
++ } else
++ dev_err(t->dev, "no:0x%x,found_vdoa:%d, mode:0x%x\n",
++ t->task_no, found_vdoa, t->set.mode);
++ }
++ if (found_ipu)
++ goto next;
++
++ for (i = 0; i < max_ipu_no; i++) {
++ ipu = ipu_get_soc(i);
++ if (IS_ERR(ipu))
++ dev_err(t->dev, "no:0x%x,found_vdoa:%d, ipu:%d\n",
++ t->task_no, found_vdoa, i);
++
++ if ((t->set.mode & IC_MODE) || only_rot(t->set.mode)) {
++ used = &tbl->used[i][IPU_PP_CH_PP];
++ if (0 == *used) {
++ t->task_id = IPU_TASK_ID_PP;
++ if (t->set.mode & IC_MODE)
++ t->set.task |= IC_PP;
++ if (t->set.mode & ROT_MODE)
++ t->set.task |= ROT_PP;
++ *used = 1;
++ found_ipu = 1;
++ break;
++ }
++ }
++ }
++
++next:
++ if (found_ipu) {
++ t->ipu = ipu;
++ t->ipu_id = i;
++ t->dev = ipu->dev;
++ if (atomic_inc_return(&t->res_get) == 2)
++ dev_err(t->dev,
++ "ERR no:0x%x,found_vdoa:%d,get ipu twice\n",
++ t->task_no, found_vdoa);
++ }
++out:
++ dev_dbg(t->dev,
++ "%s:no:0x%x,found_vdoa:%d, found_ipu:%d\n",
++ __func__, t->task_no, found_vdoa, found_ipu);
++ mutex_unlock(&tbl->lock);
++ if (t->set.task & VDOA_ONLY)
++ return found_vdoa;
++ else if (t->set.mode & VDOA_MODE)
++ return found_vdoa && found_ipu;
++ else
++ return found_ipu;
++}
++
++static void put_vdoa_ipu_res(struct ipu_task_entry *tsk, int vdoa_only)
++{
++ int ret;
++ int rel_vdoa = 0, rel_ipu = 0;
++ struct ipu_channel_tabel *tbl = &ipu_ch_tbl;
++
++ mutex_lock(&tbl->lock);
++ if (tsk->set.mode & VDOA_MODE) {
++ if (!tbl->vdoa_used && tsk->vdoa_handle)
++ dev_err(tsk->dev,
++ "ERR no:0x%x,vdoa not used,mode:0x%x\n",
++ tsk->task_no, tsk->set.mode);
++ if (tbl->vdoa_used && tsk->vdoa_handle) {
++ tbl->vdoa_used = 0;
++ vdoa_put_handle(&tsk->vdoa_handle);
++ if (tsk->ipu)
++ tsk->ipu->vdoa_en = 0;
++ rel_vdoa = 1;
++ if (vdoa_only || (tsk->set.task & VDOA_ONLY))
++ goto out;
++ }
++ }
++
++ tbl->used[tsk->ipu_id][tsk->task_id - 1] = 0;
++ rel_ipu = 1;
++ ret = atomic_inc_return(&tsk->res_free);
++ if (ret == 2)
++ dev_err(tsk->dev,
++ "ERR no:0x%x,rel_vdoa:%d,put ipu twice\n",
++ tsk->task_no, rel_vdoa);
++out:
++ dev_dbg(tsk->dev,
++ "%s:no:0x%x,rel_vdoa:%d, rel_ipu:%d\n",
++ __func__, tsk->task_no, rel_vdoa, rel_ipu);
++ mutex_unlock(&tbl->lock);
++}
++
++static int get_vdoa_ipu_res(struct ipu_task_entry *t)
++{
++ int ret;
++ uint32_t found = 0;
++
++ found = _get_vdoa_ipu_res(t);
++ if (!found) {
++ t->ipu_id = -1;
++ t->ipu = NULL;
++ /* blocking to get resource */
++ ret = atomic_inc_return(&req_cnt);
++ dev_dbg(t->dev,
++ "wait_res:no:0x%x,req_cnt:%d\n", t->task_no, ret);
++ ret = wait_event_timeout(res_waitq, _get_vdoa_ipu_res(t),
++ msecs_to_jiffies(t->timeout - DEF_DELAY_MS));
++ if (ret == 0) {
++ dev_err(t->dev, "ERR[0x%p,no-0x%x] wait_res timeout:%dms!\n",
++ t, t->task_no, t->timeout - DEF_DELAY_MS);
++ ret = -ETIMEDOUT;
++ t->state = STATE_RES_TIMEOUT;
++ goto out;
++ } else {
++ if (!(t->set.task & VDOA_ONLY) && (!t->ipu))
++ dev_err(t->dev,
++ "ERR[no-0x%x] can not get ipu!\n",
++ t->task_no);
++ ret = atomic_read(&req_cnt);
++ if (ret > 0)
++ ret = atomic_dec_return(&req_cnt);
++ else
++ dev_err(t->dev,
++ "ERR[no-0x%x] req_cnt:%d mismatch!\n",
++ t->task_no, ret);
++ dev_dbg(t->dev, "no-0x%x,[0x%p],req_cnt:%d, got_res!\n",
++ t->task_no, t, ret);
++ found = 1;
++ }
++ }
++
++out:
++ return found;
++}
++
++static struct ipu_task_entry *create_task_entry(struct ipu_task *task)
++{
++ struct ipu_task_entry *tsk;
++
++ tsk = kzalloc(sizeof(struct ipu_task_entry), GFP_KERNEL);
++ if (!tsk)
++ return ERR_PTR(-ENOMEM);
++ kref_init(&tsk->refcount);
++ tsk->state = -EINVAL;
++ tsk->ipu_id = -1;
++ tsk->dev = ipu_dev;
++ tsk->input = task->input;
++ tsk->output = task->output;
++ tsk->overlay_en = task->overlay_en;
++ if (tsk->overlay_en)
++ tsk->overlay = task->overlay;
++ if (task->timeout > DEF_TIMEOUT_MS)
++ tsk->timeout = task->timeout;
++ else
++ tsk->timeout = DEF_TIMEOUT_MS;
++
++ return tsk;
++}
++
++static void task_mem_free(struct kref *ref)
++{
++ struct ipu_task_entry *tsk =
++ container_of(ref, struct ipu_task_entry, refcount);
++ kfree(tsk);
++}
++
++int create_split_child_task(struct ipu_split_task *sp_task)
++{
++ int ret = 0;
++ struct ipu_task_entry *tsk;
++
++ tsk = create_task_entry(&sp_task->task);
++ if (IS_ERR(tsk))
++ return PTR_ERR(tsk);
++
++ sp_task->child_task = tsk;
++ tsk->task_no = sp_task->task_no;
++
++ ret = prepare_task(tsk);
++ if (ret < 0)
++ goto err;
++
++ tsk->parent = sp_task->parent_task;
++ tsk->set.sp_setting = sp_task->parent_task->set.sp_setting;
++
++ list_add(&tsk->node, &tsk->parent->split_list);
++ dev_dbg(tsk->dev, "[0x%p] sp_tsk Q list,no-0x%x\n", tsk, tsk->task_no);
++ tsk->state = STATE_QUEUE;
++ CHECK_PERF(&tsk->ts_queue);
++err:
++ return ret;
++}
++
++static inline int sp_task_check_done(struct ipu_split_task *sp_task,
++ struct ipu_task_entry *parent, int num, int *idx)
++{
++ int i;
++ int ret = 0;
++ struct ipu_task_entry *tsk;
++ struct mutex *lock = &parent->split_lock;
++
++ *idx = -EINVAL;
++ mutex_lock(lock);
++ for (i = 0; i < num; i++) {
++ tsk = sp_task[i].child_task;
++ if (tsk && tsk->split_done) {
++ *idx = i;
++ ret = 1;
++ goto out;
++ }
++ }
++
++out:
++ mutex_unlock(lock);
++ return ret;
++}
++
++static int create_split_task(
++ int stripe,
++ struct ipu_split_task *sp_task)
++{
++ struct ipu_task *task = &(sp_task->task);
++ struct ipu_task_entry *t = sp_task->parent_task;
++ int ret;
++
++ sp_task->task_no |= stripe;
++
++ task->input = t->input;
++ task->output = t->output;
++ task->overlay_en = t->overlay_en;
++ if (task->overlay_en)
++ task->overlay = t->overlay;
++ task->task_id = t->task_id;
++ if ((t->set.split_mode == RL_SPLIT) ||
++ (t->set.split_mode == UD_SPLIT))
++ task->timeout = t->timeout / 2;
++ else
++ task->timeout = t->timeout / 4;
++
++ task->input.crop.w = t->set.sp_setting.iw;
++ task->input.crop.h = t->set.sp_setting.ih;
++ if (task->overlay_en) {
++ task->overlay.crop.w = t->set.sp_setting.ow;
++ task->overlay.crop.h = t->set.sp_setting.oh;
++ }
++ if (t->output.rotate >= IPU_ROTATE_90_RIGHT) {
++ task->output.crop.w = t->set.sp_setting.oh;
++ task->output.crop.h = t->set.sp_setting.ow;
++ t->set.sp_setting.rl_split_line = t->set.sp_setting.o_bottom_pos;
++ t->set.sp_setting.ud_split_line = t->set.sp_setting.o_right_pos;
++
++ } else {
++ task->output.crop.w = t->set.sp_setting.ow;
++ task->output.crop.h = t->set.sp_setting.oh;
++ t->set.sp_setting.rl_split_line = t->set.sp_setting.o_right_pos;
++ t->set.sp_setting.ud_split_line = t->set.sp_setting.o_bottom_pos;
++ }
++
++ if (stripe & LEFT_STRIPE)
++ task->input.crop.pos.x += t->set.sp_setting.i_left_pos;
++ else if (stripe & RIGHT_STRIPE)
++ task->input.crop.pos.x += t->set.sp_setting.i_right_pos;
++ if (stripe & UP_STRIPE)
++ task->input.crop.pos.y += t->set.sp_setting.i_top_pos;
++ else if (stripe & DOWN_STRIPE)
++ task->input.crop.pos.y += t->set.sp_setting.i_bottom_pos;
++
++ if (task->overlay_en) {
++ if (stripe & LEFT_STRIPE)
++ task->overlay.crop.pos.x += t->set.sp_setting.o_left_pos;
++ else if (stripe & RIGHT_STRIPE)
++ task->overlay.crop.pos.x += t->set.sp_setting.o_right_pos;
++ if (stripe & UP_STRIPE)
++ task->overlay.crop.pos.y += t->set.sp_setting.o_top_pos;
++ else if (stripe & DOWN_STRIPE)
++ task->overlay.crop.pos.y += t->set.sp_setting.o_bottom_pos;
++ }
++
++ switch (t->output.rotate) {
++ case IPU_ROTATE_NONE:
++ if (stripe & LEFT_STRIPE)
++ task->output.crop.pos.x += t->set.sp_setting.o_left_pos;
++ else if (stripe & RIGHT_STRIPE)
++ task->output.crop.pos.x += t->set.sp_setting.o_right_pos;
++ if (stripe & UP_STRIPE)
++ task->output.crop.pos.y += t->set.sp_setting.o_top_pos;
++ else if (stripe & DOWN_STRIPE)
++ task->output.crop.pos.y += t->set.sp_setting.o_bottom_pos;
++ break;
++ case IPU_ROTATE_VERT_FLIP:
++ if (stripe & LEFT_STRIPE)
++ task->output.crop.pos.x += t->set.sp_setting.o_left_pos;
++ else if (stripe & RIGHT_STRIPE)
++ task->output.crop.pos.x += t->set.sp_setting.o_right_pos;
++ if (stripe & UP_STRIPE)
++ task->output.crop.pos.y =
++ t->output.crop.pos.y + t->output.crop.h
++ - t->set.sp_setting.o_top_pos - t->set.sp_setting.oh;
++ else if (stripe & DOWN_STRIPE)
++ task->output.crop.pos.y =
++ t->output.crop.pos.y + t->output.crop.h
++ - t->set.sp_setting.o_bottom_pos - t->set.sp_setting.oh;
++ break;
++ case IPU_ROTATE_HORIZ_FLIP:
++ if (stripe & LEFT_STRIPE)
++ task->output.crop.pos.x =
++ t->output.crop.pos.x + t->output.crop.w
++ - t->set.sp_setting.o_left_pos - t->set.sp_setting.ow;
++ else if (stripe & RIGHT_STRIPE)
++ task->output.crop.pos.x =
++ t->output.crop.pos.x + t->output.crop.w
++ - t->set.sp_setting.o_right_pos - t->set.sp_setting.ow;
++ if (stripe & UP_STRIPE)
++ task->output.crop.pos.y += t->set.sp_setting.o_top_pos;
++ else if (stripe & DOWN_STRIPE)
++ task->output.crop.pos.y += t->set.sp_setting.o_bottom_pos;
++ break;
++ case IPU_ROTATE_180:
++ if (stripe & LEFT_STRIPE)
++ task->output.crop.pos.x =
++ t->output.crop.pos.x + t->output.crop.w
++ - t->set.sp_setting.o_left_pos - t->set.sp_setting.ow;
++ else if (stripe & RIGHT_STRIPE)
++ task->output.crop.pos.x =
++ t->output.crop.pos.x + t->output.crop.w
++ - t->set.sp_setting.o_right_pos - t->set.sp_setting.ow;
++ if (stripe & UP_STRIPE)
++ task->output.crop.pos.y =
++ t->output.crop.pos.y + t->output.crop.h
++ - t->set.sp_setting.o_top_pos - t->set.sp_setting.oh;
++ else if (stripe & DOWN_STRIPE)
++ task->output.crop.pos.y =
++ t->output.crop.pos.y + t->output.crop.h
++ - t->set.sp_setting.o_bottom_pos - t->set.sp_setting.oh;
++ break;
++ case IPU_ROTATE_90_RIGHT:
++ if (stripe & UP_STRIPE)
++ task->output.crop.pos.x =
++ t->output.crop.pos.x + t->output.crop.w
++ - t->set.sp_setting.o_top_pos - t->set.sp_setting.oh;
++ else if (stripe & DOWN_STRIPE)
++ task->output.crop.pos.x =
++ t->output.crop.pos.x + t->output.crop.w
++ - t->set.sp_setting.o_bottom_pos - t->set.sp_setting.oh;
++ if (stripe & LEFT_STRIPE)
++ task->output.crop.pos.y += t->set.sp_setting.o_left_pos;
++ else if (stripe & RIGHT_STRIPE)
++ task->output.crop.pos.y += t->set.sp_setting.o_right_pos;
++ break;
++ case IPU_ROTATE_90_RIGHT_HFLIP:
++ if (stripe & UP_STRIPE)
++ task->output.crop.pos.x += t->set.sp_setting.o_top_pos;
++ else if (stripe & DOWN_STRIPE)
++ task->output.crop.pos.x += t->set.sp_setting.o_bottom_pos;
++ if (stripe & LEFT_STRIPE)
++ task->output.crop.pos.y += t->set.sp_setting.o_left_pos;
++ else if (stripe & RIGHT_STRIPE)
++ task->output.crop.pos.y += t->set.sp_setting.o_right_pos;
++ break;
++ case IPU_ROTATE_90_RIGHT_VFLIP:
++ if (stripe & UP_STRIPE)
++ task->output.crop.pos.x =
++ t->output.crop.pos.x + t->output.crop.w
++ - t->set.sp_setting.o_top_pos - t->set.sp_setting.oh;
++ else if (stripe & DOWN_STRIPE)
++ task->output.crop.pos.x =
++ t->output.crop.pos.x + t->output.crop.w
++ - t->set.sp_setting.o_bottom_pos - t->set.sp_setting.oh;
++ if (stripe & LEFT_STRIPE)
++ task->output.crop.pos.y =
++ t->output.crop.pos.y + t->output.crop.h
++ - t->set.sp_setting.o_left_pos - t->set.sp_setting.ow;
++ else if (stripe & RIGHT_STRIPE)
++ task->output.crop.pos.y =
++ t->output.crop.pos.y + t->output.crop.h
++ - t->set.sp_setting.o_right_pos - t->set.sp_setting.ow;
++ break;
++ case IPU_ROTATE_90_LEFT:
++ if (stripe & UP_STRIPE)
++ task->output.crop.pos.x += t->set.sp_setting.o_top_pos;
++ else if (stripe & DOWN_STRIPE)
++ task->output.crop.pos.x += t->set.sp_setting.o_bottom_pos;
++ if (stripe & LEFT_STRIPE)
++ task->output.crop.pos.y =
++ t->output.crop.pos.y + t->output.crop.h
++ - t->set.sp_setting.o_left_pos - t->set.sp_setting.ow;
++ else if (stripe & RIGHT_STRIPE)
++ task->output.crop.pos.y =
++ t->output.crop.pos.y + t->output.crop.h
++ - t->set.sp_setting.o_right_pos - t->set.sp_setting.ow;
++ break;
++ default:
++ dev_err(t->dev, "ERR:should not be here\n");
++ break;
++ }
++
++ ret = create_split_child_task(sp_task);
++ if (ret < 0)
++ dev_err(t->dev, "ERR:create_split_child_task() ret:%d\n", ret);
++ return ret;
++}
++
++static int queue_split_task(struct ipu_task_entry *t,
++ struct ipu_split_task *sp_task, uint32_t size)
++{
++ int err[4];
++ int ret = 0;
++ int i, j;
++ struct ipu_task_entry *tsk = NULL;
++ struct mutex *lock = &t->split_lock;
++ struct mutex *vdic_lock = &t->vdic_lock;
++
++ dev_dbg(t->dev, "Split task 0x%p, no-0x%x, size:%d\n",
++ t, t->task_no, size);
++ mutex_init(lock);
++ mutex_init(vdic_lock);
++ init_waitqueue_head(&t->split_waitq);
++ INIT_LIST_HEAD(&t->split_list);
++ for (j = 0; j < size; j++) {
++ memset(&sp_task[j], 0, sizeof(*sp_task));
++ sp_task[j].parent_task = t;
++ sp_task[j].task_no = t->task_no;
++ }
++
++ if (t->set.split_mode == RL_SPLIT) {
++ i = 0;
++ err[i] = create_split_task(RIGHT_STRIPE, &sp_task[i]);
++ if (err[i] < 0)
++ goto err_start;
++ i = 1;
++ err[i] = create_split_task(LEFT_STRIPE, &sp_task[i]);
++ } else if (t->set.split_mode == UD_SPLIT) {
++ i = 0;
++ err[i] = create_split_task(DOWN_STRIPE, &sp_task[i]);
++ if (err[i] < 0)
++ goto err_start;
++ i = 1;
++ err[i] = create_split_task(UP_STRIPE, &sp_task[i]);
++ } else {
++ i = 0;
++ err[i] = create_split_task(RIGHT_STRIPE | DOWN_STRIPE, &sp_task[i]);
++ if (err[i] < 0)
++ goto err_start;
++ i = 1;
++ err[i] = create_split_task(LEFT_STRIPE | DOWN_STRIPE, &sp_task[i]);
++ if (err[i] < 0)
++ goto err_start;
++ i = 2;
++ err[i] = create_split_task(RIGHT_STRIPE | UP_STRIPE, &sp_task[i]);
++ if (err[i] < 0)
++ goto err_start;
++ i = 3;
++ err[i] = create_split_task(LEFT_STRIPE | UP_STRIPE, &sp_task[i]);
++ }
++
++err_start:
++ for (j = 0; j < (i + 1); j++) {
++ if (err[j] < 0) {
++ if (sp_task[j].child_task)
++ dev_err(t->dev,
++ "sp_task[%d],no-0x%x fail state:%d, queue err:%d.\n",
++ j, sp_task[j].child_task->task_no,
++ sp_task[j].child_task->state, err[j]);
++ goto err_exit;
++ }
++ dev_dbg(t->dev, "[0x%p] sp_task[%d], no-0x%x state:%s, queue ret:%d.\n",
++ sp_task[j].child_task, j, sp_task[j].child_task->task_no,
++ state_msg[sp_task[j].child_task->state].msg, err[j]);
++ }
++
++ return ret;
++
++err_exit:
++ for (j = 0; j < (i + 1); j++) {
++ if (err[j] < 0 && !ret)
++ ret = err[j];
++ tsk = sp_task[j].child_task;
++ if (!tsk)
++ continue;
++ kfree(tsk);
++ }
++ t->state = STATE_ERR;
++ return ret;
++
++}
++
++static int init_tiled_buf(struct ipu_soc *ipu, struct ipu_task_entry *t,
++ ipu_channel_t channel, uint32_t ch_type)
++{
++ int ret = 0;
++ int i;
++ uint32_t ipu_fmt;
++ dma_addr_t inbuf_base = 0;
++ u32 field_size;
++ struct vdoa_params param;
++ struct vdoa_ipu_buf buf;
++ struct ipu_soc *ipu_idx;
++ u32 ipu_stride, obuf_size;
++ u32 height, width;
++ ipu_buffer_t type;
++
++ if ((IPU_PIX_FMT_YUYV != t->output.format) &&
++ (IPU_PIX_FMT_NV12 != t->output.format)) {
++ dev_err(t->dev, "ERR:[0x%d] output format\n", t->task_no);
++ return -EINVAL;
++ }
++
++ memset(&param, 0, sizeof(param));
++ /* init channel tiled bufs */
++ if (deinterlace_3_field(t) &&
++ (IPU_PIX_FMT_TILED_NV12F == t->input.format)) {
++ field_size = tiled_filed_size(t);
++ if (INPUT_CHAN_VDI_P == ch_type) {
++ inbuf_base = t->input.paddr + field_size;
++ param.vfield_buf.prev_veba = inbuf_base + t->set.i_off;
++ } else if (INPUT_CHAN == ch_type) {
++ inbuf_base = t->input.paddr_n;
++ param.vfield_buf.cur_veba = inbuf_base + t->set.i_off;
++ } else if (INPUT_CHAN_VDI_N == ch_type) {
++ inbuf_base = t->input.paddr_n + field_size;
++ param.vfield_buf.next_veba = inbuf_base + t->set.i_off;
++ } else
++ return -EINVAL;
++ height = t->input.crop.h >> 1; /* field format for vdoa */
++ width = t->input.crop.w;
++ param.vfield_buf.vubo = t->set.i_uoff;
++ param.interlaced = 1;
++ param.scan_order = 1;
++ type = IPU_INPUT_BUFFER;
++ } else if ((IPU_PIX_FMT_TILED_NV12 == t->input.format) &&
++ (INPUT_CHAN == ch_type)) {
++ height = t->input.crop.h;
++ width = t->input.crop.w;
++ param.vframe_buf.veba = t->input.paddr + t->set.i_off;
++ param.vframe_buf.vubo = t->set.i_uoff;
++ type = IPU_INPUT_BUFFER;
++ } else
++ return -EINVAL;
++
++ param.band_mode = (t->set.mode & VDOA_BAND_MODE) ? 1 : 0;
++ if (param.band_mode && (t->set.band_lines != 3) &&
++ (t->set.band_lines != 4) && (t->set.band_lines != 5))
++ return -EINVAL;
++ else if (param.band_mode)
++ param.band_lines = (1 << t->set.band_lines);
++ for (i = 0; i < max_ipu_no; i++) {
++ ipu_idx = ipu_get_soc(i);
++ if (!IS_ERR(ipu_idx) && ipu_idx == ipu)
++ break;
++ }
++ if (t->set.task & VDOA_ONLY)
++ /* dummy, didn't need ipu res */
++ i = 0;
++ if (max_ipu_no == i) {
++ dev_err(t->dev, "ERR:[0x%p] get ipu num\n", t);
++ return -EINVAL;
++ }
++
++ param.ipu_num = i;
++ param.vpu_stride = t->input.width;
++ param.height = height;
++ param.width = width;
++ if (IPU_PIX_FMT_NV12 == t->output.format)
++ param.pfs = VDOA_PFS_NV12;
++ else
++ param.pfs = VDOA_PFS_YUYV;
++ ipu_fmt = (param.pfs == VDOA_PFS_YUYV) ? IPU_PIX_FMT_YUYV :
++ IPU_PIX_FMT_NV12;
++ ipu_stride = param.width * bytes_per_pixel(ipu_fmt);
++ obuf_size = PAGE_ALIGN(param.width * param.height *
++ fmt_to_bpp(ipu_fmt)/8);
++ dev_dbg(t->dev, "band_mode:%d, band_lines:%d\n",
++ param.band_mode, param.band_lines);
++ if (!param.band_mode) {
++ /* note: if only for tiled -> raster convert and
++ no other post-processing, we don't need alloc buf
++ and use output buffer directly.
++ */
++ if (t->set.task & VDOA_ONLY)
++ param.ieba0 = t->output.paddr;
++ else {
++ dev_err(t->dev, "ERR:[0x%d] vdoa task\n", t->task_no);
++ return -EINVAL;
++ }
++ } else {
++ if (IPU_PIX_FMT_TILED_NV12F != t->input.format) {
++ dev_err(t->dev, "ERR [0x%d] vdoa task\n", t->task_no);
++ return -EINVAL;
++ }
++ }
++ ret = vdoa_setup(t->vdoa_handle, &param);
++ if (ret)
++ goto done;
++ vdoa_get_output_buf(t->vdoa_handle, &buf);
++ if (t->set.task & VDOA_ONLY)
++ goto done;
++
++ ret = ipu_init_channel_buffer(ipu,
++ channel,
++ type,
++ ipu_fmt,
++ width,
++ height,
++ ipu_stride,
++ IPU_ROTATE_NONE,
++ buf.ieba0,
++ buf.ieba1,
++ 0,
++ buf.iubo,
++ 0);
++ if (ret < 0) {
++ t->state = STATE_INIT_CHAN_BUF_FAIL;
++ goto done;
++ }
++
++ if (param.band_mode) {
++ ret = ipu_set_channel_bandmode(ipu, channel,
++ type, t->set.band_lines);
++ if (ret < 0) {
++ t->state = STATE_INIT_CHAN_BAND_FAIL;
++ goto done;
++ }
++ }
++done:
++ return ret;
++}
++
++static int init_tiled_ch_bufs(struct ipu_soc *ipu, struct ipu_task_entry *t)
++{
++ int ret = 0;
++
++ if (IPU_PIX_FMT_TILED_NV12 == t->input.format) {
++ ret = init_tiled_buf(ipu, t, t->set.ic_chan, INPUT_CHAN);
++ CHECK_RETCODE(ret < 0, "init tiled_ch", t->state, done, ret);
++ } else if (IPU_PIX_FMT_TILED_NV12F == t->input.format) {
++ ret = init_tiled_buf(ipu, t, t->set.ic_chan, INPUT_CHAN);
++ CHECK_RETCODE(ret < 0, "init tiled_ch-c", t->state, done, ret);
++ ret = init_tiled_buf(ipu, t, t->set.vdi_ic_p_chan,
++ INPUT_CHAN_VDI_P);
++ CHECK_RETCODE(ret < 0, "init tiled_ch-p", t->state, done, ret);
++ ret = init_tiled_buf(ipu, t, t->set.vdi_ic_n_chan,
++ INPUT_CHAN_VDI_N);
++ CHECK_RETCODE(ret < 0, "init tiled_ch-n", t->state, done, ret);
++ } else {
++ ret = -EINVAL;
++ dev_err(t->dev, "ERR[no-0x%x] invalid fmt:0x%x!\n",
++ t->task_no, t->input.format);
++ }
++
++done:
++ return ret;
++}
++
++static int init_ic(struct ipu_soc *ipu, struct ipu_task_entry *t)
++{
++ int ret = 0;
++ ipu_channel_params_t params;
++ dma_addr_t inbuf = 0, ovbuf = 0, ov_alp_buf = 0;
++ dma_addr_t inbuf_p = 0, inbuf_n = 0;
++ dma_addr_t outbuf = 0;
++ int out_uoff = 0, out_voff = 0, out_rot;
++ int out_w = 0, out_h = 0, out_stride;
++ int out_fmt;
++ u32 vdi_frame_idx = 0;
++
++ memset(&params, 0, sizeof(params));
++
++ /* is it need link a rot channel */
++ if (ic_and_rot(t->set.mode)) {
++ outbuf = t->set.r_paddr;
++ out_w = t->set.r_width;
++ out_h = t->set.r_height;
++ out_stride = t->set.r_stride;
++ out_fmt = t->set.r_fmt;
++ out_uoff = 0;
++ out_voff = 0;
++ out_rot = IPU_ROTATE_NONE;
++ } else {
++ outbuf = t->output.paddr + t->set.o_off;
++ out_w = t->output.crop.w;
++ out_h = t->output.crop.h;
++ out_stride = t->set.ostride;
++ out_fmt = t->output.format;
++ out_uoff = t->set.o_uoff;
++ out_voff = t->set.o_voff;
++ out_rot = t->output.rotate;
++ }
++
++ /* settings */
++ params.mem_prp_vf_mem.in_width = t->input.crop.w;
++ params.mem_prp_vf_mem.out_width = out_w;
++ params.mem_prp_vf_mem.in_height = t->input.crop.h;
++ params.mem_prp_vf_mem.out_height = out_h;
++ params.mem_prp_vf_mem.in_pixel_fmt = t->input.format;
++ params.mem_prp_vf_mem.out_pixel_fmt = out_fmt;
++ params.mem_prp_vf_mem.motion_sel = t->input.deinterlace.motion;
++
++ params.mem_prp_vf_mem.outh_resize_ratio =
++ t->set.sp_setting.outh_resize_ratio;
++ params.mem_prp_vf_mem.outv_resize_ratio =
++ t->set.sp_setting.outv_resize_ratio;
++
++ if (t->overlay_en) {
++ params.mem_prp_vf_mem.in_g_pixel_fmt = t->overlay.format;
++ params.mem_prp_vf_mem.graphics_combine_en = 1;
++ if (t->overlay.alpha.mode == IPU_ALPHA_MODE_GLOBAL)
++ params.mem_prp_vf_mem.global_alpha_en = 1;
++ else if (t->overlay.alpha.loc_alp_paddr)
++ params.mem_prp_vf_mem.alpha_chan_en = 1;
++ /* otherwise, alpha bending per pixel is used. */
++ params.mem_prp_vf_mem.alpha = t->overlay.alpha.gvalue;
++ if (t->overlay.colorkey.enable) {
++ params.mem_prp_vf_mem.key_color_en = 1;
++ params.mem_prp_vf_mem.key_color = t->overlay.colorkey.value;
++ }
++ }
++
++ if (t->input.deinterlace.enable) {
++ if (t->input.deinterlace.field_fmt & IPU_DEINTERLACE_FIELD_MASK)
++ params.mem_prp_vf_mem.field_fmt =
++ IPU_DEINTERLACE_FIELD_BOTTOM;
++ else
++ params.mem_prp_vf_mem.field_fmt =
++ IPU_DEINTERLACE_FIELD_TOP;
++
++ if (t->input.deinterlace.field_fmt & IPU_DEINTERLACE_RATE_EN)
++ vdi_frame_idx = t->input.deinterlace.field_fmt &
++ IPU_DEINTERLACE_RATE_FRAME1;
++ }
++
++ if (t->set.mode & VDOA_MODE)
++ ipu->vdoa_en = 1;
++
++ /* init channels */
++ if (!(t->set.task & VDOA_ONLY)) {
++ ret = ipu_init_channel(ipu, t->set.ic_chan, &params);
++ if (ret < 0) {
++ t->state = STATE_INIT_CHAN_FAIL;
++ goto done;
++ }
++ }
++
++ if (deinterlace_3_field(t)) {
++ ret = ipu_init_channel(ipu, t->set.vdi_ic_p_chan, &params);
++ if (ret < 0) {
++ t->state = STATE_INIT_CHAN_FAIL;
++ goto done;
++ }
++ ret = ipu_init_channel(ipu, t->set.vdi_ic_n_chan, &params);
++ if (ret < 0) {
++ t->state = STATE_INIT_CHAN_FAIL;
++ goto done;
++ }
++ }
++
++ /* init channel bufs */
++ if ((IPU_PIX_FMT_TILED_NV12 == t->input.format) ||
++ (IPU_PIX_FMT_TILED_NV12F == t->input.format)) {
++ ret = init_tiled_ch_bufs(ipu, t);
++ if (ret < 0)
++ goto done;
++ } else {
++ if ((deinterlace_3_field(t)) &&
++ (IPU_PIX_FMT_TILED_NV12F != t->input.format)) {
++ if (params.mem_prp_vf_mem.field_fmt ==
++ IPU_DEINTERLACE_FIELD_TOP) {
++ if (vdi_frame_idx) {
++ inbuf_p = t->input.paddr + t->set.istride +
++ t->set.i_off;
++ inbuf = t->input.paddr_n + t->set.i_off;
++ inbuf_n = t->input.paddr_n + t->set.istride +
++ t->set.i_off;
++ params.mem_prp_vf_mem.field_fmt =
++ IPU_DEINTERLACE_FIELD_BOTTOM;
++ } else {
++ inbuf_p = t->input.paddr + t->set.i_off;
++ inbuf = t->input.paddr + t->set.istride + t->set.i_off;
++ inbuf_n = t->input.paddr_n + t->set.i_off;
++ }
++ } else {
++ if (vdi_frame_idx) {
++ inbuf_p = t->input.paddr + t->set.i_off;
++ inbuf = t->input.paddr_n + t->set.istride + t->set.i_off;
++ inbuf_n = t->input.paddr_n + t->set.i_off;
++ params.mem_prp_vf_mem.field_fmt =
++ IPU_DEINTERLACE_FIELD_TOP;
++ } else {
++ inbuf_p = t->input.paddr + t->set.istride +
++ t->set.i_off;
++ inbuf = t->input.paddr + t->set.i_off;
++ inbuf_n = t->input.paddr_n + t->set.istride +
++ t->set.i_off;
++ }
++ }
++ } else {
++ if (t->input.deinterlace.enable) {
++ if (params.mem_prp_vf_mem.field_fmt ==
++ IPU_DEINTERLACE_FIELD_TOP) {
++ if (vdi_frame_idx) {
++ inbuf = t->input.paddr + t->set.istride + t->set.i_off;
++ params.mem_prp_vf_mem.field_fmt =
++ IPU_DEINTERLACE_FIELD_BOTTOM;
++ } else
++ inbuf = t->input.paddr + t->set.i_off;
++ } else {
++ if (vdi_frame_idx) {
++ inbuf = t->input.paddr + t->set.i_off;
++ params.mem_prp_vf_mem.field_fmt =
++ IPU_DEINTERLACE_FIELD_TOP;
++ } else
++ inbuf = t->input.paddr + t->set.istride + t->set.i_off;
++ }
++ } else
++ inbuf = t->input.paddr + t->set.i_off;
++ }
++
++ if (t->overlay_en)
++ ovbuf = t->overlay.paddr + t->set.ov_off;
++ }
++ if (t->overlay_en && (t->overlay.alpha.mode == IPU_ALPHA_MODE_LOCAL))
++ ov_alp_buf = t->overlay.alpha.loc_alp_paddr
++ + t->set.ov_alpha_off;
++
++ if ((IPU_PIX_FMT_TILED_NV12 != t->input.format) &&
++ (IPU_PIX_FMT_TILED_NV12F != t->input.format)) {
++ ret = ipu_init_channel_buffer(ipu,
++ t->set.ic_chan,
++ IPU_INPUT_BUFFER,
++ t->input.format,
++ t->input.crop.w,
++ t->input.crop.h,
++ t->set.istride,
++ IPU_ROTATE_NONE,
++ inbuf,
++ 0,
++ 0,
++ t->set.i_uoff,
++ t->set.i_voff);
++ if (ret < 0) {
++ t->state = STATE_INIT_CHAN_BUF_FAIL;
++ goto done;
++ }
++ }
++ if (deinterlace_3_field(t) &&
++ (IPU_PIX_FMT_TILED_NV12F != t->input.format)) {
++ ret = ipu_init_channel_buffer(ipu,
++ t->set.vdi_ic_p_chan,
++ IPU_INPUT_BUFFER,
++ t->input.format,
++ t->input.crop.w,
++ t->input.crop.h,
++ t->set.istride,
++ IPU_ROTATE_NONE,
++ inbuf_p,
++ 0,
++ 0,
++ t->set.i_uoff,
++ t->set.i_voff);
++ if (ret < 0) {
++ t->state = STATE_INIT_CHAN_BUF_FAIL;
++ goto done;
++ }
++
++ ret = ipu_init_channel_buffer(ipu,
++ t->set.vdi_ic_n_chan,
++ IPU_INPUT_BUFFER,
++ t->input.format,
++ t->input.crop.w,
++ t->input.crop.h,
++ t->set.istride,
++ IPU_ROTATE_NONE,
++ inbuf_n,
++ 0,
++ 0,
++ t->set.i_uoff,
++ t->set.i_voff);
++ if (ret < 0) {
++ t->state = STATE_INIT_CHAN_BUF_FAIL;
++ goto done;
++ }
++ }
++
++ if (t->overlay_en) {
++ ret = ipu_init_channel_buffer(ipu,
++ t->set.ic_chan,
++ IPU_GRAPH_IN_BUFFER,
++ t->overlay.format,
++ t->overlay.crop.w,
++ t->overlay.crop.h,
++ t->set.ovstride,
++ IPU_ROTATE_NONE,
++ ovbuf,
++ 0,
++ 0,
++ t->set.ov_uoff,
++ t->set.ov_voff);
++ if (ret < 0) {
++ t->state = STATE_INIT_CHAN_BUF_FAIL;
++ goto done;
++ }
++ }
++
++ if (t->overlay.alpha.mode == IPU_ALPHA_MODE_LOCAL) {
++ ret = ipu_init_channel_buffer(ipu,
++ t->set.ic_chan,
++ IPU_ALPHA_IN_BUFFER,
++ IPU_PIX_FMT_GENERIC,
++ t->overlay.crop.w,
++ t->overlay.crop.h,
++ t->set.ov_alpha_stride,
++ IPU_ROTATE_NONE,
++ ov_alp_buf,
++ 0,
++ 0,
++ 0, 0);
++ if (ret < 0) {
++ t->state = STATE_INIT_CHAN_BUF_FAIL;
++ goto done;
++ }
++ }
++
++ if (!(t->set.task & VDOA_ONLY)) {
++ ret = ipu_init_channel_buffer(ipu,
++ t->set.ic_chan,
++ IPU_OUTPUT_BUFFER,
++ out_fmt,
++ out_w,
++ out_h,
++ out_stride,
++ out_rot,
++ outbuf,
++ 0,
++ 0,
++ out_uoff,
++ out_voff);
++ if (ret < 0) {
++ t->state = STATE_INIT_CHAN_BUF_FAIL;
++ goto done;
++ }
++ }
++
++ if ((t->set.mode & VDOA_BAND_MODE) && (t->set.task & VDI_VF)) {
++ ret = ipu_link_channels(ipu, MEM_VDOA_MEM, t->set.ic_chan);
++ CHECK_RETCODE(ret < 0, "ipu_link_ch vdoa_ic",
++ STATE_LINK_CHAN_FAIL, done, ret);
++ }
++
++done:
++ return ret;
++}
++
++static void uninit_ic(struct ipu_soc *ipu, struct ipu_task_entry *t)
++{
++ int ret;
++
++ if ((t->set.mode & VDOA_BAND_MODE) && (t->set.task & VDI_VF)) {
++ ret = ipu_unlink_channels(ipu, MEM_VDOA_MEM, t->set.ic_chan);
++ CHECK_RETCODE_CONT(ret < 0, "ipu_unlink_ch vdoa_ic",
++ STATE_UNLINK_CHAN_FAIL, ret);
++ }
++ ipu_uninit_channel(ipu, t->set.ic_chan);
++ if (deinterlace_3_field(t)) {
++ ipu_uninit_channel(ipu, t->set.vdi_ic_p_chan);
++ ipu_uninit_channel(ipu, t->set.vdi_ic_n_chan);
++ }
++}
++
++static int init_rot(struct ipu_soc *ipu, struct ipu_task_entry *t)
++{
++ int ret = 0;
++ dma_addr_t inbuf = 0, outbuf = 0;
++ int in_uoff = 0, in_voff = 0;
++ int in_fmt, in_width, in_height, in_stride;
++
++ /* init channel */
++ ret = ipu_init_channel(ipu, t->set.rot_chan, NULL);
++ if (ret < 0) {
++ t->state = STATE_INIT_CHAN_FAIL;
++ goto done;
++ }
++
++ /* init channel buf */
++ /* is it need link to a ic channel */
++ if (ic_and_rot(t->set.mode)) {
++ in_fmt = t->set.r_fmt;
++ in_width = t->set.r_width;
++ in_height = t->set.r_height;
++ in_stride = t->set.r_stride;
++ inbuf = t->set.r_paddr;
++ in_uoff = 0;
++ in_voff = 0;
++ } else {
++ in_fmt = t->input.format;
++ in_width = t->input.crop.w;
++ in_height = t->input.crop.h;
++ in_stride = t->set.istride;
++ inbuf = t->input.paddr + t->set.i_off;
++ in_uoff = t->set.i_uoff;
++ in_voff = t->set.i_voff;
++ }
++ outbuf = t->output.paddr + t->set.o_off;
++
++ ret = ipu_init_channel_buffer(ipu,
++ t->set.rot_chan,
++ IPU_INPUT_BUFFER,
++ in_fmt,
++ in_width,
++ in_height,
++ in_stride,
++ t->output.rotate,
++ inbuf,
++ 0,
++ 0,
++ in_uoff,
++ in_voff);
++ if (ret < 0) {
++ t->state = STATE_INIT_CHAN_BUF_FAIL;
++ goto done;
++ }
++
++ ret = ipu_init_channel_buffer(ipu,
++ t->set.rot_chan,
++ IPU_OUTPUT_BUFFER,
++ t->output.format,
++ t->output.crop.w,
++ t->output.crop.h,
++ t->set.ostride,
++ IPU_ROTATE_NONE,
++ outbuf,
++ 0,
++ 0,
++ t->set.o_uoff,
++ t->set.o_voff);
++ if (ret < 0) {
++ t->state = STATE_INIT_CHAN_BUF_FAIL;
++ goto done;
++ }
++
++done:
++ return ret;
++}
++
++static void uninit_rot(struct ipu_soc *ipu, struct ipu_task_entry *t)
++{
++ ipu_uninit_channel(ipu, t->set.rot_chan);
++}
++
++static int get_irq(struct ipu_task_entry *t)
++{
++ int irq;
++ ipu_channel_t chan;
++
++ if (only_ic(t->set.mode))
++ chan = t->set.ic_chan;
++ else
++ chan = t->set.rot_chan;
++
++ switch (chan) {
++ case MEM_ROT_VF_MEM:
++ irq = IPU_IRQ_PRP_VF_ROT_OUT_EOF;
++ break;
++ case MEM_ROT_PP_MEM:
++ irq = IPU_IRQ_PP_ROT_OUT_EOF;
++ break;
++ case MEM_VDI_PRP_VF_MEM:
++ case MEM_PRP_VF_MEM:
++ irq = IPU_IRQ_PRP_VF_OUT_EOF;
++ break;
++ case MEM_PP_MEM:
++ irq = IPU_IRQ_PP_OUT_EOF;
++ break;
++ case MEM_VDI_MEM:
++ irq = IPU_IRQ_VDIC_OUT_EOF;
++ break;
++ default:
++ irq = -EINVAL;
++ }
++
++ return irq;
++}
++
++static irqreturn_t task_irq_handler(int irq, void *dev_id)
++{
++ struct ipu_task_entry *prev_tsk = dev_id;
++
++ CHECK_PERF(&prev_tsk->ts_inirq);
++ complete(&prev_tsk->irq_comp);
++ dev_dbg(prev_tsk->dev, "[0x%p] no-0x%x in-irq!",
++ prev_tsk, prev_tsk->task_no);
++
++ return IRQ_HANDLED;
++}
++
++/* Fix deinterlace up&down split mode medium line */
++static void vdi_split_process(struct ipu_soc *ipu, struct ipu_task_entry *t)
++{
++ u32 vdi_size;
++ u32 vdi_save_lines;
++ u32 stripe_mode;
++ u32 task_no;
++ u32 i, offset_addr;
++ u32 line_size;
++ unsigned char *base_off;
++ struct ipu_task_entry *parent = t->parent;
++ struct mutex *lock = &parent->vdic_lock;
++
++ if (!parent) {
++ dev_err(t->dev, "ERR[0x%x]invalid parent\n", t->task_no);
++ return;
++ }
++ mutex_lock(lock);
++ stripe_mode = t->task_no & 0xf;
++ task_no = t->task_no >> 4;
++
++ /* Save both luma and chroma part for interleaved YUV(e.g. YUYV).
++ * Save luma part for non-interleaved and partial-interleaved
++ * YUV format (e.g NV12 and YV12). */
++ if (t->output.format == IPU_PIX_FMT_YUYV ||
++ t->output.format == IPU_PIX_FMT_UYVY)
++ line_size = t->output.crop.w * fmt_to_bpp(t->output.format)/8;
++ else
++ line_size = t->output.crop.w;
++
++ vdi_save_lines = (t->output.crop.h - t->set.sp_setting.ud_split_line)/2;
++ vdi_size = vdi_save_lines * line_size;
++ if (vdi_save_lines <= 0) {
++ dev_err(t->dev, "[0x%p] vdi_save_line error\n", (void *)t);
++ mutex_unlock(lock);
++ return;
++ }
++
++ /*check vditmpbuf buffer have alloced or buffer size is changed */
++ if ((vdi_save_lines != parent->old_save_lines) ||
++ (vdi_size != parent->old_size)) {
++ if (parent->vditmpbuf[0] != NULL)
++ kfree(parent->vditmpbuf[0]);
++ if (parent->vditmpbuf[1] != NULL)
++ kfree(parent->vditmpbuf[1]);
++
++ parent->vditmpbuf[0] = kmalloc(vdi_size, GFP_KERNEL);
++ if (parent->vditmpbuf[0] == NULL) {
++ dev_err(t->dev,
++ "[0x%p]Falied Alloc vditmpbuf[0]\n", (void *)t);
++ mutex_unlock(lock);
++ return;
++ }
++ memset(parent->vditmpbuf[0], 0, vdi_size);
++
++ parent->vditmpbuf[1] = kmalloc(vdi_size, GFP_KERNEL);
++ if (parent->vditmpbuf[1] == NULL) {
++ dev_err(t->dev,
++ "[0x%p]Falied Alloc vditmpbuf[1]\n", (void *)t);
++ mutex_unlock(lock);
++ return;
++ }
++ memset(parent->vditmpbuf[1], 0, vdi_size);
++
++ parent->old_save_lines = vdi_save_lines;
++ parent->old_size = vdi_size;
++ }
++
++ if (pfn_valid(t->output.paddr >> PAGE_SHIFT)) {
++ base_off = page_address(pfn_to_page(t->output.paddr >> PAGE_SHIFT));
++ base_off += t->output.paddr & ((1 << PAGE_SHIFT) - 1);
++ } else {
++ base_off = (char *)ioremap_nocache(t->output.paddr,
++ t->output.width * t->output.height *
++ fmt_to_bpp(t->output.format)/8);
++ }
++ if (base_off == NULL) {
++ dev_err(t->dev, "ERR[0x%p]Failed get virtual address\n", t);
++ mutex_unlock(lock);
++ return;
++ }
++
++ /* UP stripe or UP&LEFT stripe */
++ if ((stripe_mode == UP_STRIPE) ||
++ (stripe_mode == (UP_STRIPE | LEFT_STRIPE))) {
++ if (!parent->buf0filled) {
++ offset_addr = t->set.o_off +
++ t->set.sp_setting.ud_split_line*t->set.ostride;
++ dmac_flush_range(base_off + offset_addr,
++ base_off + offset_addr + vdi_size);
++ outer_flush_range(t->output.paddr + offset_addr,
++ t->output.paddr + offset_addr + vdi_size);
++
++ for (i = 0; i < vdi_save_lines; i++)
++ memcpy(parent->vditmpbuf[0] + i*line_size,
++ base_off + offset_addr +
++ i*t->set.ostride, line_size);
++ parent->buf0filled = true;
++ } else {
++ offset_addr = t->set.o_off + (t->output.crop.h -
++ vdi_save_lines) * t->set.ostride;
++ for (i = 0; i < vdi_save_lines; i++)
++ memcpy(base_off + offset_addr + i*t->set.ostride,
++ parent->vditmpbuf[0] + i*line_size, line_size);
++
++ dmac_flush_range(base_off + offset_addr,
++ base_off + offset_addr + i*t->set.ostride);
++ outer_flush_range(t->output.paddr + offset_addr,
++ t->output.paddr + offset_addr + i*t->set.ostride);
++ parent->buf0filled = false;
++ }
++ }
++ /*Down stripe or Down&Left stripe*/
++ else if ((stripe_mode == DOWN_STRIPE) ||
++ (stripe_mode == (DOWN_STRIPE | LEFT_STRIPE))) {
++ if (!parent->buf0filled) {
++ offset_addr = t->set.o_off + vdi_save_lines*t->set.ostride;
++ dmac_flush_range(base_off + offset_addr,
++ base_off + offset_addr + vdi_size);
++ outer_flush_range(t->output.paddr + offset_addr,
++ t->output.paddr + offset_addr + vdi_size);
++
++ for (i = 0; i < vdi_save_lines; i++)
++ memcpy(parent->vditmpbuf[0] + i*line_size,
++ base_off + offset_addr + i*t->set.ostride,
++ line_size);
++ parent->buf0filled = true;
++ } else {
++ offset_addr = t->set.o_off;
++ for (i = 0; i < vdi_save_lines; i++)
++ memcpy(base_off + offset_addr + i*t->set.ostride,
++ parent->vditmpbuf[0] + i*line_size,
++ line_size);
++
++ dmac_flush_range(base_off + offset_addr,
++ base_off + offset_addr + i*t->set.ostride);
++ outer_flush_range(t->output.paddr + offset_addr,
++ t->output.paddr + offset_addr + i*t->set.ostride);
++ parent->buf0filled = false;
++ }
++ }
++ /*Up&Right stripe*/
++ else if (stripe_mode == (UP_STRIPE | RIGHT_STRIPE)) {
++ if (!parent->buf1filled) {
++ offset_addr = t->set.o_off +
++ t->set.sp_setting.ud_split_line*t->set.ostride;
++ dmac_flush_range(base_off + offset_addr,
++ base_off + offset_addr + vdi_size);
++ outer_flush_range(t->output.paddr + offset_addr,
++ t->output.paddr + offset_addr + vdi_size);
++
++ for (i = 0; i < vdi_save_lines; i++)
++ memcpy(parent->vditmpbuf[1] + i*line_size,
++ base_off + offset_addr + i*t->set.ostride,
++ line_size);
++ parent->buf1filled = true;
++ } else {
++ offset_addr = t->set.o_off +
++ (t->output.crop.h - vdi_save_lines)*t->set.ostride;
++ for (i = 0; i < vdi_save_lines; i++)
++ memcpy(base_off + offset_addr + i*t->set.ostride,
++ parent->vditmpbuf[1] + i*line_size,
++ line_size);
++
++ dmac_flush_range(base_off + offset_addr,
++ base_off + offset_addr + i*t->set.ostride);
++ outer_flush_range(t->output.paddr + offset_addr,
++ t->output.paddr + offset_addr + i*t->set.ostride);
++ parent->buf1filled = false;
++ }
++ }
++ /*Down stripe or Down&Right stript*/
++ else if (stripe_mode == (DOWN_STRIPE | RIGHT_STRIPE)) {
++ if (!parent->buf1filled) {
++ offset_addr = t->set.o_off + vdi_save_lines*t->set.ostride;
++ dmac_flush_range(base_off + offset_addr,
++ base_off + offset_addr + vdi_save_lines*t->set.ostride);
++ outer_flush_range(t->output.paddr + offset_addr,
++ t->output.paddr + offset_addr + vdi_save_lines*t->set.ostride);
++
++ for (i = 0; i < vdi_save_lines; i++)
++ memcpy(parent->vditmpbuf[1] + i*line_size,
++ base_off + offset_addr + i*t->set.ostride,
++ line_size);
++ parent->buf1filled = true;
++ } else {
++ offset_addr = t->set.o_off;
++ for (i = 0; i < vdi_save_lines; i++)
++ memcpy(base_off + offset_addr + i*t->set.ostride,
++ parent->vditmpbuf[1] + i*line_size,
++ line_size);
++
++ dmac_flush_range(base_off + offset_addr,
++ base_off + offset_addr + vdi_save_lines*t->set.ostride);
++ outer_flush_range(t->output.paddr + offset_addr,
++ t->output.paddr + offset_addr + vdi_save_lines*t->set.ostride);
++ parent->buf1filled = false;
++ }
++ }
++ if (!pfn_valid(t->output.paddr >> PAGE_SHIFT))
++ iounmap(base_off);
++ mutex_unlock(lock);
++}
++
++static void do_task_release(struct ipu_task_entry *t, int fail)
++{
++ int ret;
++ struct ipu_soc *ipu = t->ipu;
++
++ if (t->input.deinterlace.enable && !fail &&
++ (t->task_no & (UP_STRIPE | DOWN_STRIPE)))
++ vdi_split_process(ipu, t);
++
++ ipu_free_irq(ipu, t->irq, t);
++
++ if (t->vdoa_dma.vaddr)
++ dma_free_coherent(t->dev,
++ t->vdoa_dma.size,
++ t->vdoa_dma.vaddr,
++ t->vdoa_dma.paddr);
++
++ if (only_ic(t->set.mode)) {
++ ret = ipu_disable_channel(ipu, t->set.ic_chan, true);
++ CHECK_RETCODE_CONT(ret < 0, "ipu_disable_ch only_ic",
++ STATE_DISABLE_CHAN_FAIL, ret);
++ if (deinterlace_3_field(t)) {
++ ret = ipu_disable_channel(ipu, t->set.vdi_ic_p_chan,
++ true);
++ CHECK_RETCODE_CONT(ret < 0, "ipu_disable_ch only_ic_p",
++ STATE_DISABLE_CHAN_FAIL, ret);
++ ret = ipu_disable_channel(ipu, t->set.vdi_ic_n_chan,
++ true);
++ CHECK_RETCODE_CONT(ret < 0, "ipu_disable_ch only_ic_n",
++ STATE_DISABLE_CHAN_FAIL, ret);
++ }
++ } else if (only_rot(t->set.mode)) {
++ ret = ipu_disable_channel(ipu, t->set.rot_chan, true);
++ CHECK_RETCODE_CONT(ret < 0, "ipu_disable_ch only_rot",
++ STATE_DISABLE_CHAN_FAIL, ret);
++ } else if (ic_and_rot(t->set.mode)) {
++ ret = ipu_unlink_channels(ipu, t->set.ic_chan, t->set.rot_chan);
++ CHECK_RETCODE_CONT(ret < 0, "ipu_unlink_ch",
++ STATE_UNLINK_CHAN_FAIL, ret);
++ ret = ipu_disable_channel(ipu, t->set.rot_chan, true);
++ CHECK_RETCODE_CONT(ret < 0, "ipu_disable_ch ic_and_rot-rot",
++ STATE_DISABLE_CHAN_FAIL, ret);
++ ret = ipu_disable_channel(ipu, t->set.ic_chan, true);
++ CHECK_RETCODE_CONT(ret < 0, "ipu_disable_ch ic_and_rot-ic",
++ STATE_DISABLE_CHAN_FAIL, ret);
++ if (deinterlace_3_field(t)) {
++ ret = ipu_disable_channel(ipu, t->set.vdi_ic_p_chan,
++ true);
++ CHECK_RETCODE_CONT(ret < 0, "ipu_disable_ch icrot-ic-p",
++ STATE_DISABLE_CHAN_FAIL, ret);
++ ret = ipu_disable_channel(ipu, t->set.vdi_ic_n_chan,
++ true);
++ CHECK_RETCODE_CONT(ret < 0, "ipu_disable_ch icrot-ic-n",
++ STATE_DISABLE_CHAN_FAIL, ret);
++ }
++ }
++
++ if (only_ic(t->set.mode))
++ uninit_ic(ipu, t);
++ else if (only_rot(t->set.mode))
++ uninit_rot(ipu, t);
++ else if (ic_and_rot(t->set.mode)) {
++ uninit_ic(ipu, t);
++ uninit_rot(ipu, t);
++ }
++
++ t->state = STATE_OK;
++ CHECK_PERF(&t->ts_rel);
++ return;
++}
++
++static void do_task_vdoa_only(struct ipu_task_entry *t)
++{
++ int ret;
++
++ ret = init_tiled_ch_bufs(NULL, t);
++ CHECK_RETCODE(ret < 0, "do_vdoa_only", STATE_ERR, out, ret);
++ ret = vdoa_start(t->vdoa_handle, VDOA_DEF_TIMEOUT_MS);
++ vdoa_stop(t->vdoa_handle);
++ CHECK_RETCODE(ret < 0, "vdoa_wait4complete, do_vdoa_only",
++ STATE_VDOA_IRQ_TIMEOUT, out, ret);
++
++ t->state = STATE_OK;
++out:
++ return;
++}
++
++static void do_task(struct ipu_task_entry *t)
++{
++ int r_size;
++ int irq;
++ int ret;
++ uint32_t busy;
++ struct ipu_soc *ipu = t->ipu;
++
++ CHECK_PERF(&t->ts_dotask);
++
++ if (!ipu) {
++ t->state = STATE_NO_IPU;
++ return;
++ }
++
++ init_completion(&t->irq_comp);
++ dev_dbg(ipu->dev, "[0x%p]Do task no:0x%x: id %d\n", (void *)t,
++ t->task_no, t->task_id);
++ dump_task_info(t);
++
++ if (t->set.task & IC_PP) {
++ t->set.ic_chan = MEM_PP_MEM;
++ dev_dbg(ipu->dev, "[0x%p]ic channel MEM_PP_MEM\n", (void *)t);
++ } else if (t->set.task & IC_VF) {
++ t->set.ic_chan = MEM_PRP_VF_MEM;
++ dev_dbg(ipu->dev, "[0x%p]ic channel MEM_PRP_VF_MEM\n", (void *)t);
++ } else if (t->set.task & VDI_VF) {
++ if (t->set.mode & VDOA_BAND_MODE) {
++ t->set.ic_chan = MEM_VDI_MEM;
++ if (deinterlace_3_field(t)) {
++ t->set.vdi_ic_p_chan = MEM_VDI_MEM_P;
++ t->set.vdi_ic_n_chan = MEM_VDI_MEM_N;
++ }
++ dev_dbg(ipu->dev, "[0x%p]ic ch MEM_VDI_MEM\n",
++ (void *)t);
++ } else {
++ t->set.ic_chan = MEM_VDI_PRP_VF_MEM;
++ if (deinterlace_3_field(t)) {
++ t->set.vdi_ic_p_chan = MEM_VDI_PRP_VF_MEM_P;
++ t->set.vdi_ic_n_chan = MEM_VDI_PRP_VF_MEM_N;
++ }
++ dev_dbg(ipu->dev,
++ "[0x%p]ic ch MEM_VDI_PRP_VF_MEM\n", t);
++ }
++ }
++
++ if (t->set.task & ROT_PP) {
++ t->set.rot_chan = MEM_ROT_PP_MEM;
++ dev_dbg(ipu->dev, "[0x%p]rot channel MEM_ROT_PP_MEM\n", (void *)t);
++ } else if (t->set.task & ROT_VF) {
++ t->set.rot_chan = MEM_ROT_VF_MEM;
++ dev_dbg(ipu->dev, "[0x%p]rot channel MEM_ROT_VF_MEM\n", (void *)t);
++ }
++
++ if (t->task_id == IPU_TASK_ID_VF)
++ busy = ic_vf_pp_is_busy(ipu, true);
++ else if (t->task_id == IPU_TASK_ID_PP)
++ busy = ic_vf_pp_is_busy(ipu, false);
++ else {
++ dev_err(ipu->dev, "ERR[no:0x%x]ipu task_id:%d invalid!\n",
++ t->task_no, t->task_id);
++ return;
++ }
++ if (busy) {
++ dev_err(ipu->dev, "ERR[0x%p-no:0x%x]ipu task_id:%d busy!\n",
++ (void *)t, t->task_no, t->task_id);
++ t->state = STATE_IPU_BUSY;
++ return;
++ }
++
++ irq = get_irq(t);
++ if (irq < 0) {
++ t->state = STATE_NO_IRQ;
++ return;
++ }
++ t->irq = irq;
++
++ /* channel setup */
++ if (only_ic(t->set.mode)) {
++ dev_dbg(t->dev, "[0x%p]only ic mode\n", (void *)t);
++ ret = init_ic(ipu, t);
++ CHECK_RETCODE(ret < 0, "init_ic only_ic",
++ t->state, chan_setup, ret);
++ } else if (only_rot(t->set.mode)) {
++ dev_dbg(t->dev, "[0x%p]only rot mode\n", (void *)t);
++ ret = init_rot(ipu, t);
++ CHECK_RETCODE(ret < 0, "init_rot only_rot",
++ t->state, chan_setup, ret);
++ } else if (ic_and_rot(t->set.mode)) {
++ int rot_idx = (t->task_id == IPU_TASK_ID_VF) ? 0 : 1;
++
++ dev_dbg(t->dev, "[0x%p]ic + rot mode\n", (void *)t);
++ t->set.r_fmt = t->output.format;
++ if (t->output.rotate >= IPU_ROTATE_90_RIGHT) {
++ t->set.r_width = t->output.crop.h;
++ t->set.r_height = t->output.crop.w;
++ } else {
++ t->set.r_width = t->output.crop.w;
++ t->set.r_height = t->output.crop.h;
++ }
++ t->set.r_stride = t->set.r_width *
++ bytes_per_pixel(t->set.r_fmt);
++ r_size = PAGE_ALIGN(t->set.r_width * t->set.r_height
++ * fmt_to_bpp(t->set.r_fmt)/8);
++
++ if (r_size > ipu->rot_dma[rot_idx].size) {
++ dev_dbg(t->dev, "[0x%p]realloc rot buffer\n", (void *)t);
++
++ if (ipu->rot_dma[rot_idx].vaddr)
++ dma_free_coherent(t->dev,
++ ipu->rot_dma[rot_idx].size,
++ ipu->rot_dma[rot_idx].vaddr,
++ ipu->rot_dma[rot_idx].paddr);
++
++ ipu->rot_dma[rot_idx].size = r_size;
++ ipu->rot_dma[rot_idx].vaddr = dma_zalloc_coherent(t->dev,
++ r_size,
++ &ipu->rot_dma[rot_idx].paddr,
++ GFP_DMA | GFP_KERNEL);
++ CHECK_RETCODE(ipu->rot_dma[rot_idx].vaddr == NULL,
++ "ic_and_rot", STATE_SYS_NO_MEM,
++ chan_setup, -ENOMEM);
++ }
++ t->set.r_paddr = ipu->rot_dma[rot_idx].paddr;
++
++ dev_dbg(t->dev, "[0x%p]rotation:\n", (void *)t);
++ dev_dbg(t->dev, "[0x%p]\tformat = 0x%x\n", (void *)t, t->set.r_fmt);
++ dev_dbg(t->dev, "[0x%p]\twidth = %d\n", (void *)t, t->set.r_width);
++ dev_dbg(t->dev, "[0x%p]\theight = %d\n", (void *)t, t->set.r_height);
++ dev_dbg(t->dev, "[0x%p]\tpaddr = 0x%x\n", (void *)t, t->set.r_paddr);
++ dev_dbg(t->dev, "[0x%p]\trstride = %d\n", (void *)t, t->set.r_stride);
++
++ ret = init_ic(ipu, t);
++ CHECK_RETCODE(ret < 0, "init_ic ic_and_rot",
++ t->state, chan_setup, ret);
++ ret = init_rot(ipu, t);
++ CHECK_RETCODE(ret < 0, "init_rot ic_and_rot",
++ t->state, chan_setup, ret);
++ ret = ipu_link_channels(ipu, t->set.ic_chan,
++ t->set.rot_chan);
++ CHECK_RETCODE(ret < 0, "ipu_link_ch ic_and_rot",
++ STATE_LINK_CHAN_FAIL, chan_setup, ret);
++ } else {
++ dev_err(t->dev, "ERR [0x%p]do task: should not be here\n", t);
++ t->state = STATE_ERR;
++ return;
++ }
++
++ ret = ipu_request_irq(ipu, irq, task_irq_handler, 0, NULL, t);
++ CHECK_RETCODE(ret < 0, "ipu_req_irq",
++ STATE_IRQ_FAIL, chan_setup, ret);
++
++ /* enable/start channel */
++ if (only_ic(t->set.mode)) {
++ ret = ipu_enable_channel(ipu, t->set.ic_chan);
++ CHECK_RETCODE(ret < 0, "ipu_enable_ch only_ic",
++ STATE_ENABLE_CHAN_FAIL, chan_en, ret);
++ if (deinterlace_3_field(t)) {
++ ret = ipu_enable_channel(ipu, t->set.vdi_ic_p_chan);
++ CHECK_RETCODE(ret < 0, "ipu_enable_ch only_ic_p",
++ STATE_ENABLE_CHAN_FAIL, chan_en, ret);
++ ret = ipu_enable_channel(ipu, t->set.vdi_ic_n_chan);
++ CHECK_RETCODE(ret < 0, "ipu_enable_ch only_ic_n",
++ STATE_ENABLE_CHAN_FAIL, chan_en, ret);
++ }
++
++ ret = ipu_select_buffer(ipu, t->set.ic_chan, IPU_OUTPUT_BUFFER,
++ 0);
++ CHECK_RETCODE(ret < 0, "ipu_sel_buf only_ic",
++ STATE_SEL_BUF_FAIL, chan_buf, ret);
++ if (t->overlay_en) {
++ ret = ipu_select_buffer(ipu, t->set.ic_chan,
++ IPU_GRAPH_IN_BUFFER, 0);
++ CHECK_RETCODE(ret < 0, "ipu_sel_buf only_ic_g",
++ STATE_SEL_BUF_FAIL, chan_buf, ret);
++ if (t->overlay.alpha.mode == IPU_ALPHA_MODE_LOCAL) {
++ ret = ipu_select_buffer(ipu, t->set.ic_chan,
++ IPU_ALPHA_IN_BUFFER, 0);
++ CHECK_RETCODE(ret < 0, "ipu_sel_buf only_ic_a",
++ STATE_SEL_BUF_FAIL, chan_buf,
++ ret);
++ }
++ }
++ if (!(t->set.mode & VDOA_BAND_MODE)) {
++ if (deinterlace_3_field(t))
++ ipu_select_multi_vdi_buffer(ipu, 0);
++ else {
++ ret = ipu_select_buffer(ipu, t->set.ic_chan,
++ IPU_INPUT_BUFFER, 0);
++ CHECK_RETCODE(ret < 0, "ipu_sel_buf only_ic_i",
++ STATE_SEL_BUF_FAIL, chan_buf, ret);
++ }
++ }
++ } else if (only_rot(t->set.mode)) {
++ ret = ipu_enable_channel(ipu, t->set.rot_chan);
++ CHECK_RETCODE(ret < 0, "ipu_enable_ch only_rot",
++ STATE_ENABLE_CHAN_FAIL, chan_en, ret);
++ ret = ipu_select_buffer(ipu, t->set.rot_chan,
++ IPU_OUTPUT_BUFFER, 0);
++ CHECK_RETCODE(ret < 0, "ipu_sel_buf only_rot_o",
++ STATE_SEL_BUF_FAIL, chan_buf, ret);
++ ret = ipu_select_buffer(ipu, t->set.rot_chan,
++ IPU_INPUT_BUFFER, 0);
++ CHECK_RETCODE(ret < 0, "ipu_sel_buf only_rot_i",
++ STATE_SEL_BUF_FAIL, chan_buf, ret);
++ } else if (ic_and_rot(t->set.mode)) {
++ ret = ipu_enable_channel(ipu, t->set.rot_chan);
++ CHECK_RETCODE(ret < 0, "ipu_enable_ch ic_and_rot-rot",
++ STATE_ENABLE_CHAN_FAIL, chan_en, ret);
++ ret = ipu_enable_channel(ipu, t->set.ic_chan);
++ CHECK_RETCODE(ret < 0, "ipu_enable_ch ic_and_rot-ic",
++ STATE_ENABLE_CHAN_FAIL, chan_en, ret);
++ if (deinterlace_3_field(t)) {
++ ret = ipu_enable_channel(ipu, t->set.vdi_ic_p_chan);
++ CHECK_RETCODE(ret < 0, "ipu_enable_ch ic_and_rot-p",
++ STATE_ENABLE_CHAN_FAIL, chan_en, ret);
++ ret = ipu_enable_channel(ipu, t->set.vdi_ic_n_chan);
++ CHECK_RETCODE(ret < 0, "ipu_enable_ch ic_and_rot-n",
++ STATE_ENABLE_CHAN_FAIL, chan_en, ret);
++ }
++
++ ret = ipu_select_buffer(ipu, t->set.rot_chan,
++ IPU_OUTPUT_BUFFER, 0);
++ CHECK_RETCODE(ret < 0, "ipu_sel_buf ic_and_rot-rot-o",
++ STATE_SEL_BUF_FAIL, chan_buf, ret);
++ if (t->overlay_en) {
++ ret = ipu_select_buffer(ipu, t->set.ic_chan,
++ IPU_GRAPH_IN_BUFFER, 0);
++ CHECK_RETCODE(ret < 0, "ipu_sel_buf ic_and_rot-ic-g",
++ STATE_SEL_BUF_FAIL, chan_buf, ret);
++ if (t->overlay.alpha.mode == IPU_ALPHA_MODE_LOCAL) {
++ ret = ipu_select_buffer(ipu, t->set.ic_chan,
++ IPU_ALPHA_IN_BUFFER, 0);
++ CHECK_RETCODE(ret < 0, "ipu_sel_buf icrot-ic-a",
++ STATE_SEL_BUF_FAIL,
++ chan_buf, ret);
++ }
++ }
++ ret = ipu_select_buffer(ipu, t->set.ic_chan,
++ IPU_OUTPUT_BUFFER, 0);
++ CHECK_RETCODE(ret < 0, "ipu_sel_buf ic_and_rot-ic-o",
++ STATE_SEL_BUF_FAIL, chan_buf, ret);
++ if (deinterlace_3_field(t))
++ ipu_select_multi_vdi_buffer(ipu, 0);
++ else {
++ ret = ipu_select_buffer(ipu, t->set.ic_chan,
++ IPU_INPUT_BUFFER, 0);
++ CHECK_RETCODE(ret < 0, "ipu_sel_buf ic_and_rot-ic-i",
++ STATE_SEL_BUF_FAIL, chan_buf, ret);
++ }
++ }
++
++ if (need_split(t))
++ t->state = STATE_IN_PROGRESS;
++
++ if (t->set.mode & VDOA_BAND_MODE) {
++ ret = vdoa_start(t->vdoa_handle, VDOA_DEF_TIMEOUT_MS);
++ CHECK_RETCODE(ret < 0, "vdoa_wait4complete, do_vdoa_band",
++ STATE_VDOA_IRQ_TIMEOUT, chan_rel, ret);
++ }
++
++ CHECK_PERF(&t->ts_waitirq);
++ ret = wait_for_completion_timeout(&t->irq_comp,
++ msecs_to_jiffies(t->timeout - DEF_DELAY_MS));
++ CHECK_PERF(&t->ts_wakeup);
++ CHECK_RETCODE(ret == 0, "wait_for_comp_timeout",
++ STATE_IRQ_TIMEOUT, chan_rel, ret);
++ dev_dbg(t->dev, "[0x%p] no-0x%x ipu irq done!", t, t->task_no);
++
++chan_rel:
++chan_buf:
++chan_en:
++chan_setup:
++ if (t->set.mode & VDOA_BAND_MODE)
++ vdoa_stop(t->vdoa_handle);
++ do_task_release(t, t->state >= STATE_ERR);
++ return;
++}
++
++static void do_task_vdoa_vdi(struct ipu_task_entry *t)
++{
++ int i;
++ int ret;
++ u32 stripe_width;
++
++ /* FIXME: crop mode not support now */
++ stripe_width = t->input.width >> 1;
++ t->input.crop.pos.x = 0;
++ t->input.crop.pos.y = 0;
++ t->input.crop.w = stripe_width;
++ t->input.crop.h = t->input.height;
++ t->output.crop.w = stripe_width;
++ t->output.crop.h = t->input.height;
++
++ for (i = 0; i < 2; i++) {
++ t->input.crop.pos.x = t->input.crop.pos.x + i * stripe_width;
++ t->output.crop.pos.x = t->output.crop.pos.x + i * stripe_width;
++ /* check input */
++ ret = set_crop(&t->input.crop, t->input.width, t->input.height,
++ t->input.format);
++ if (ret < 0) {
++ ret = STATE_ERR;
++ goto done;
++ } else
++ update_offset(t->input.format,
++ t->input.width, t->input.height,
++ t->input.crop.pos.x,
++ t->input.crop.pos.y,
++ &t->set.i_off, &t->set.i_uoff,
++ &t->set.i_voff, &t->set.istride);
++ dev_dbg(t->dev, "i_off:0x%x, i_uoff:0x%x, istride:%d.\n",
++ t->set.i_off, t->set.i_uoff, t->set.istride);
++ /* check output */
++ ret = set_crop(&t->output.crop, t->input.width,
++ t->output.height, t->output.format);
++ if (ret < 0) {
++ ret = STATE_ERR;
++ goto done;
++ } else
++ update_offset(t->output.format,
++ t->output.width, t->output.height,
++ t->output.crop.pos.x,
++ t->output.crop.pos.y,
++ &t->set.o_off, &t->set.o_uoff,
++ &t->set.o_voff, &t->set.ostride);
++
++ dev_dbg(t->dev, "o_off:0x%x, o_uoff:0x%x, ostride:%d.\n",
++ t->set.o_off, t->set.o_uoff, t->set.ostride);
++
++ do_task(t);
++ }
++
++ return;
++done:
++ dev_err(t->dev, "ERR %s set_crop.\n", __func__);
++ t->state = ret;
++ return;
++}
++
++static void get_res_do_task(struct ipu_task_entry *t)
++{
++ uint32_t found;
++ uint32_t split_child;
++ struct mutex *lock;
++
++ found = get_vdoa_ipu_res(t);
++ if (!found) {
++ dev_err(t->dev, "ERR:[0x%p] no-0x%x can not get res\n",
++ t, t->task_no);
++ return;
++ } else {
++ if (t->set.task & VDOA_ONLY)
++ do_task_vdoa_only(t);
++ else if ((IPU_PIX_FMT_TILED_NV12F == t->input.format) &&
++ (t->set.mode & VDOA_BAND_MODE) &&
++ (t->input.crop.w > soc_max_vdi_in_width()))
++ do_task_vdoa_vdi(t);
++ else
++ do_task(t);
++ put_vdoa_ipu_res(t, 0);
++ }
++ if (t->state != STATE_OK) {
++ dev_err(t->dev, "ERR:[0x%p] no-0x%x state: %s\n",
++ t, t->task_no, state_msg[t->state].msg);
++ }
++
++ split_child = need_split(t) && t->parent;
++ if (split_child) {
++ lock = &t->parent->split_lock;
++ mutex_lock(lock);
++ t->split_done = 1;
++ mutex_unlock(lock);
++ wake_up(&t->parent->split_waitq);
++ }
++
++ return;
++}
++
++static void wait_split_task_complete(struct ipu_task_entry *parent,
++ struct ipu_split_task *sp_task, uint32_t size)
++{
++ struct ipu_task_entry *tsk = NULL;
++ int ret = 0, rc;
++ int j, idx = -1;
++ unsigned long flags;
++ struct mutex *lock = &parent->split_lock;
++ int k, busy_vf, busy_pp;
++ struct ipu_soc *ipu;
++ DECLARE_PERF_VAR;
++
++ for (j = 0; j < size; j++) {
++ rc = wait_event_timeout(
++ parent->split_waitq,
++ sp_task_check_done(sp_task, parent, size, &idx),
++ msecs_to_jiffies(parent->timeout - DEF_DELAY_MS));
++ if (!rc) {
++ dev_err(parent->dev,
++ "ERR:[0x%p] no-0x%x, split_task timeout,j:%d,"
++ "size:%d.\n",
++ parent, parent->task_no, j, size);
++ ret = -ETIMEDOUT;
++ goto out;
++ } else {
++ if (idx < 0) {
++ dev_err(parent->dev,
++ "ERR:[0x%p] no-0x%x, invalid task idx:%d\n",
++ parent, parent->task_no, idx);
++ continue;
++ }
++ tsk = sp_task[idx].child_task;
++ mutex_lock(lock);
++ if (!tsk->split_done || !tsk->ipu)
++ dev_err(tsk->dev,
++ "ERR:no-0x%x,split not done:%d/null ipu:0x%p\n",
++ tsk->task_no, tsk->split_done, tsk->ipu);
++ tsk->split_done = 0;
++ mutex_unlock(lock);
++
++ dev_dbg(tsk->dev,
++ "[0x%p] no-0x%x sp_tsk[%d] done,state:%d.\n",
++ tsk, tsk->task_no, idx, tsk->state);
++ #ifdef DBG_IPU_PERF
++ CHECK_PERF(&tsk->ts_rel);
++ PRINT_TASK_STATISTICS;
++ #endif
++ }
++ }
++
++out:
++ if (ret == -ETIMEDOUT) {
++ /* debug */
++ for (k = 0; k < max_ipu_no; k++) {
++ ipu = ipu_get_soc(k);
++ if (IS_ERR(ipu)) {
++ dev_err(parent->dev, "no:0x%x, null ipu:%d\n",
++ parent->task_no, k);
++ } else {
++ busy_vf = ic_vf_pp_is_busy(ipu, true);
++ busy_pp = ic_vf_pp_is_busy(ipu, false);
++ dev_err(parent->dev,
++ "ERR:ipu[%d] busy_vf:%d, busy_pp:%d.\n",
++ k, busy_vf, busy_pp);
++ }
++ }
++ for (k = 0; k < size; k++) {
++ tsk = sp_task[k].child_task;
++ if (!tsk)
++ continue;
++ dev_err(parent->dev,
++ "ERR: sp_task[%d][0x%p] no-0x%x done:%d,"
++ "state:%s,on_list:%d, ipu:0x%p,timeout!\n",
++ k, tsk, tsk->task_no, tsk->split_done,
++ state_msg[tsk->state].msg, tsk->task_in_list,
++ tsk->ipu);
++ }
++ }
++
++ for (j = 0; j < size; j++) {
++ tsk = sp_task[j].child_task;
++ if (!tsk)
++ continue;
++ spin_lock_irqsave(&ipu_task_list_lock, flags);
++ if (tsk->task_in_list) {
++ list_del(&tsk->node);
++ tsk->task_in_list = 0;
++ dev_dbg(tsk->dev,
++ "[0x%p] no-0x%x,id:%d sp_tsk timeout list_del.\n",
++ tsk, tsk->task_no, tsk->task_id);
++ }
++ spin_unlock_irqrestore(&ipu_task_list_lock, flags);
++ if (!tsk->ipu)
++ continue;
++ if (tsk->state != STATE_OK) {
++ dev_err(tsk->dev,
++ "ERR:[0x%p] no-0x%x,id:%d, sp_tsk state: %s\n",
++ tsk, tsk->task_no, tsk->task_id,
++ state_msg[tsk->state].msg);
++ }
++ kref_put(&tsk->refcount, task_mem_free);
++ }
++
++ kfree(parent->vditmpbuf[0]);
++ kfree(parent->vditmpbuf[1]);
++
++ if (ret < 0)
++ parent->state = STATE_TIMEOUT;
++ else
++ parent->state = STATE_OK;
++ return;
++}
++
++static inline int find_task(struct ipu_task_entry **t, int thread_id)
++{
++ int found;
++ unsigned long flags;
++ struct ipu_task_entry *tsk;
++ struct list_head *task_list = &ipu_task_list;
++
++ *t = NULL;
++ spin_lock_irqsave(&ipu_task_list_lock, flags);
++ found = !list_empty(task_list);
++ if (found) {
++ tsk = list_first_entry(task_list, struct ipu_task_entry, node);
++ if (tsk->task_in_list) {
++ list_del(&tsk->node);
++ tsk->task_in_list = 0;
++ *t = tsk;
++ kref_get(&tsk->refcount);
++ dev_dbg(tsk->dev,
++ "thread_id:%d,[0x%p] task_no:0x%x,mode:0x%x list_del\n",
++ thread_id, tsk, tsk->task_no, tsk->set.mode);
++ } else
++ dev_err(tsk->dev,
++ "thread_id:%d,task_no:0x%x,mode:0x%x not on list_del\n",
++ thread_id, tsk->task_no, tsk->set.mode);
++ }
++ spin_unlock_irqrestore(&ipu_task_list_lock, flags);
++
++ return found;
++}
++
++static int ipu_task_thread(void *argv)
++{
++ struct ipu_task_entry *tsk;
++ struct ipu_task_entry *sp_tsk0;
++ struct ipu_split_task sp_task[4];
++ /* priority lower than irq_thread */
++ const struct sched_param param = {
++ .sched_priority = MAX_USER_RT_PRIO/2 - 1,
++ };
++ int ret;
++ int curr_thread_id;
++ uint32_t size;
++ unsigned long flags;
++ unsigned int cpu;
++ struct cpumask cpu_mask;
++ struct ipu_thread_data *data = (struct ipu_thread_data *)argv;
++
++ thread_id++;
++ curr_thread_id = thread_id;
++ sched_setscheduler(current, SCHED_FIFO, &param);
++
++ if (!data->is_vdoa) {
++ cpu = cpumask_first(cpu_online_mask);
++ cpumask_set_cpu(cpu, &cpu_mask);
++ ret = sched_setaffinity(data->ipu->thread[data->id]->pid,
++ &cpu_mask);
++ if (ret < 0) {
++ pr_err("%s: sched_setaffinity fail:%d.\n", __func__, ret);
++ }
++ pr_debug("%s: sched_setaffinity cpu:%d.\n", __func__, cpu);
++ }
++
++ while (!kthread_should_stop()) {
++ int split_fail = 0;
++ int split_parent;
++ int split_child;
++
++ wait_event_interruptible(thread_waitq, find_task(&tsk, curr_thread_id));
++
++ if (!tsk) {
++ pr_err("thread:%d can not find task.\n",
++ curr_thread_id);
++ continue;
++ }
++
++ /* note: other threads run split child task */
++ split_parent = need_split(tsk) && !tsk->parent;
++ split_child = need_split(tsk) && tsk->parent;
++ if (split_parent) {
++ if ((tsk->set.split_mode == RL_SPLIT) ||
++ (tsk->set.split_mode == UD_SPLIT))
++ size = 2;
++ else
++ size = 4;
++ ret = queue_split_task(tsk, sp_task, size);
++ if (ret < 0) {
++ split_fail = 1;
++ } else {
++ struct list_head *pos;
++
++ spin_lock_irqsave(&ipu_task_list_lock, flags);
++
++ sp_tsk0 = list_first_entry(&tsk->split_list,
++ struct ipu_task_entry, node);
++ list_del(&sp_tsk0->node);
++
++ list_for_each(pos, &tsk->split_list) {
++ struct ipu_task_entry *tmp;
++
++ tmp = list_entry(pos,
++ struct ipu_task_entry, node);
++ tmp->task_in_list = 1;
++ dev_dbg(tmp->dev,
++ "[0x%p] no-0x%x,id:%d sp_tsk "
++ "add_to_list.\n", tmp,
++ tmp->task_no, tmp->task_id);
++ }
++ /* add to global list */
++ list_splice(&tsk->split_list, &ipu_task_list);
++
++ spin_unlock_irqrestore(&ipu_task_list_lock,
++ flags);
++ /* let the parent thread do the first sp_task */
++ /* FIXME: ensure the correct sequence for split
++ 4size: 5/6->9/a*/
++ if (!sp_tsk0)
++ dev_err(tsk->dev,
++ "ERR: no-0x%x,can not get split_tsk0\n",
++ tsk->task_no);
++ wake_up_interruptible(&thread_waitq);
++ get_res_do_task(sp_tsk0);
++ dev_dbg(sp_tsk0->dev,
++ "thread:%d complete tsk no:0x%x.\n",
++ curr_thread_id, sp_tsk0->task_no);
++ ret = atomic_read(&req_cnt);
++ if (ret > 0) {
++ wake_up(&res_waitq);
++ dev_dbg(sp_tsk0->dev,
++ "sp_tsk0 sche thread:%d no:0x%x,"
++ "req_cnt:%d\n", curr_thread_id,
++ sp_tsk0->task_no, ret);
++ /* For other threads to get_res */
++ schedule();
++ }
++ }
++ } else
++ get_res_do_task(tsk);
++
++ /* wait for all 4 sp_task finished here or timeout
++ and then release all resources */
++ if (split_parent && !split_fail)
++ wait_split_task_complete(tsk, sp_task, size);
++
++ if (!split_child) {
++ atomic_inc(&tsk->done);
++ wake_up(&tsk->task_waitq);
++ }
++
++ dev_dbg(tsk->dev, "thread:%d complete tsk no:0x%x-[0x%p].\n",
++ curr_thread_id, tsk->task_no, tsk);
++ ret = atomic_read(&req_cnt);
++ if (ret > 0) {
++ wake_up(&res_waitq);
++ dev_dbg(tsk->dev, "sche thread:%d no:0x%x,req_cnt:%d\n",
++ curr_thread_id, tsk->task_no, ret);
++ /* note: give cpu to other threads to get_res */
++ schedule();
++ }
++
++ kref_put(&tsk->refcount, task_mem_free);
++ }
++
++ pr_info("ERR %s exit.\n", __func__);
++ return 0;
++}
++
++int ipu_check_task(struct ipu_task *task)
++{
++ struct ipu_task_entry *tsk;
++ int ret = 0;
++
++ tsk = create_task_entry(task);
++ if (IS_ERR(tsk))
++ return PTR_ERR(tsk);
++
++ ret = check_task(tsk);
++
++ task->input = tsk->input;
++ task->output = tsk->output;
++ task->overlay = tsk->overlay;
++ dump_task_info(tsk);
++
++ kref_put(&tsk->refcount, task_mem_free);
++ if (ret != 0)
++ pr_debug("%s ret:%d.\n", __func__, ret);
++ return ret;
++}
++EXPORT_SYMBOL_GPL(ipu_check_task);
++
++int ipu_queue_task(struct ipu_task *task)
++{
++ struct ipu_task_entry *tsk;
++ unsigned long flags;
++ int ret;
++ u32 tmp_task_no;
++ DECLARE_PERF_VAR;
++
++ tsk = create_task_entry(task);
++ if (IS_ERR(tsk))
++ return PTR_ERR(tsk);
++
++ CHECK_PERF(&tsk->ts_queue);
++ ret = prepare_task(tsk);
++ if (ret < 0)
++ goto done;
++
++ if (need_split(tsk)) {
++ CHECK_PERF(&tsk->ts_dotask);
++ CHECK_PERF(&tsk->ts_waitirq);
++ CHECK_PERF(&tsk->ts_inirq);
++ CHECK_PERF(&tsk->ts_wakeup);
++ }
++
++ /* task_no last four bits for split task type*/
++ tmp_task_no = atomic_inc_return(&frame_no);
++ tsk->task_no = tmp_task_no << 4;
++ init_waitqueue_head(&tsk->task_waitq);
++
++ spin_lock_irqsave(&ipu_task_list_lock, flags);
++ list_add_tail(&tsk->node, &ipu_task_list);
++ tsk->task_in_list = 1;
++ dev_dbg(tsk->dev, "[0x%p,no-0x%x] list_add_tail\n", tsk, tsk->task_no);
++ spin_unlock_irqrestore(&ipu_task_list_lock, flags);
++ wake_up_interruptible(&thread_waitq);
++
++ ret = wait_event_timeout(tsk->task_waitq, atomic_read(&tsk->done),
++ msecs_to_jiffies(tsk->timeout));
++ if (0 == ret) {
++ /* note: the timeout should larger than the internal timeout!*/
++ ret = -ETIMEDOUT;
++ dev_err(tsk->dev, "ERR: [0x%p] no-0x%x, timeout:%dms!\n",
++ tsk, tsk->task_no, tsk->timeout);
++ } else {
++ if (STATE_OK != tsk->state) {
++ dev_err(tsk->dev, "ERR: [0x%p] no-0x%x,state %d: %s\n",
++ tsk, tsk->task_no, tsk->state,
++ state_msg[tsk->state].msg);
++ ret = -ECANCELED;
++ } else
++ ret = 0;
++ }
++
++ spin_lock_irqsave(&ipu_task_list_lock, flags);
++ if (tsk->task_in_list) {
++ list_del(&tsk->node);
++ tsk->task_in_list = 0;
++ dev_dbg(tsk->dev, "[0x%p] no:0x%x list_del\n",
++ tsk, tsk->task_no);
++ }
++ spin_unlock_irqrestore(&ipu_task_list_lock, flags);
++
++#ifdef DBG_IPU_PERF
++ CHECK_PERF(&tsk->ts_rel);
++ PRINT_TASK_STATISTICS;
++ if (ts_frame_avg == 0)
++ ts_frame_avg = ts_frame.tv_nsec / NSEC_PER_USEC +
++ ts_frame.tv_sec * USEC_PER_SEC;
++ else
++ ts_frame_avg = (ts_frame_avg + ts_frame.tv_nsec / NSEC_PER_USEC
++ + ts_frame.tv_sec * USEC_PER_SEC)/2;
++ if (timespec_compare(&ts_frame, &ts_frame_max) > 0)
++ ts_frame_max = ts_frame;
++
++ atomic_inc(&frame_cnt);
++
++ if ((atomic_read(&frame_cnt) % 1000) == 0)
++ pr_debug("ipu_dev: max frame time:%ldus, avg frame time:%dus,"
++ "frame_cnt:%d\n", ts_frame_max.tv_nsec / NSEC_PER_USEC
++ + ts_frame_max.tv_sec * USEC_PER_SEC,
++ ts_frame_avg, atomic_read(&frame_cnt));
++#endif
++done:
++ if (ret < 0)
++ dev_err(tsk->dev, "ERR: no-0x%x,ipu_queue_task err:%d\n",
++ tsk->task_no, ret);
++
++ kref_put(&tsk->refcount, task_mem_free);
++
++ return ret;
++}
++EXPORT_SYMBOL_GPL(ipu_queue_task);
++
++static int mxc_ipu_open(struct inode *inode, struct file *file)
++{
++ file->private_data = (void *)atomic_inc_return(&file_index);
++ return 0;
++}
++
++static long mxc_ipu_ioctl(struct file *file,
++ unsigned int cmd, unsigned long arg)
++{
++ int __user *argp = (void __user *)arg;
++ int ret = 0;
++
++ switch (cmd) {
++ case IPU_CHECK_TASK:
++ {
++ struct ipu_task task;
++
++ if (copy_from_user
++ (&task, (struct ipu_task *) arg,
++ sizeof(struct ipu_task)))
++ return -EFAULT;
++ ret = ipu_check_task(&task);
++ if (copy_to_user((struct ipu_task *) arg,
++ &task, sizeof(struct ipu_task)))
++ return -EFAULT;
++ break;
++ }
++ case IPU_QUEUE_TASK:
++ {
++ struct ipu_task task;
++
++ if (copy_from_user
++ (&task, (struct ipu_task *) arg,
++ sizeof(struct ipu_task)))
++ return -EFAULT;
++ ret = ipu_queue_task(&task);
++ break;
++ }
++ case IPU_ALLOC:
++ {
++ int size;
++ struct ipu_alloc_list *mem;
++
++ mem = kzalloc(sizeof(*mem), GFP_KERNEL);
++ if (mem == NULL)
++ return -ENOMEM;
++
++ if (get_user(size, argp))
++ return -EFAULT;
++
++ mem->size = PAGE_ALIGN(size);
++
++ mem->cpu_addr = dma_zalloc_coherent(ipu_dev, size,
++ &mem->phy_addr,
++ GFP_DMA | GFP_KERNEL);
++ if (mem->cpu_addr == NULL) {
++ kfree(mem);
++ return -ENOMEM;
++ }
++ mem->file_index = file->private_data;
++ mutex_lock(&ipu_alloc_lock);
++ list_add(&mem->list, &ipu_alloc_list);
++ mutex_unlock(&ipu_alloc_lock);
++
++ dev_dbg(ipu_dev, "allocated %d bytes @ 0x%08X\n",
++ mem->size, mem->phy_addr);
++
++ if (put_user(mem->phy_addr, argp))
++ return -EFAULT;
++
++ break;
++ }
++ case IPU_FREE:
++ {
++ unsigned long offset;
++ struct ipu_alloc_list *mem;
++
++ if (get_user(offset, argp))
++ return -EFAULT;
++
++ ret = -EINVAL;
++ mutex_lock(&ipu_alloc_lock);
++ list_for_each_entry(mem, &ipu_alloc_list, list) {
++ if (mem->phy_addr == offset) {
++ list_del(&mem->list);
++ dma_free_coherent(ipu_dev,
++ mem->size,
++ mem->cpu_addr,
++ mem->phy_addr);
++ kfree(mem);
++ ret = 0;
++ break;
++ }
++ }
++ mutex_unlock(&ipu_alloc_lock);
++ if (0 == ret)
++ dev_dbg(ipu_dev, "free %d bytes @ 0x%08X\n",
++ mem->size, mem->phy_addr);
++
++ break;
++ }
++ default:
++ break;
++ }
++ return ret;
++}
++
++static int mxc_ipu_mmap(struct file *file, struct vm_area_struct *vma)
++{
++ bool found = false;
++ u32 len;
++ unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
++ struct ipu_alloc_list *mem;
++
++ mutex_lock(&ipu_alloc_lock);
++ list_for_each_entry(mem, &ipu_alloc_list, list) {
++ if (offset == mem->phy_addr) {
++ found = true;
++ len = mem->size;
++ break;
++ }
++ }
++ mutex_unlock(&ipu_alloc_lock);
++ if (!found)
++ return -EINVAL;
++
++ if (vma->vm_end - vma->vm_start > len)
++ return -EINVAL;
++
++ vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
++
++ if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
++ vma->vm_end - vma->vm_start,
++ vma->vm_page_prot)) {
++ printk(KERN_ERR
++ "mmap failed!\n");
++ return -ENOBUFS;
++ }
++ return 0;
++}
++
++static int mxc_ipu_release(struct inode *inode, struct file *file)
++{
++ struct ipu_alloc_list *mem;
++ struct ipu_alloc_list *n;
++
++ mutex_lock(&ipu_alloc_lock);
++ list_for_each_entry_safe(mem, n, &ipu_alloc_list, list) {
++ if ((mem->cpu_addr != 0) &&
++ (file->private_data == mem->file_index)) {
++ list_del(&mem->list);
++ dma_free_coherent(ipu_dev,
++ mem->size,
++ mem->cpu_addr,
++ mem->phy_addr);
++ dev_dbg(ipu_dev, "rel-free %d bytes @ 0x%08X\n",
++ mem->size, mem->phy_addr);
++ kfree(mem);
++ }
++ }
++ mutex_unlock(&ipu_alloc_lock);
++ atomic_dec(&file_index);
++
++ return 0;
++}
++
++static struct file_operations mxc_ipu_fops = {
++ .owner = THIS_MODULE,
++ .open = mxc_ipu_open,
++ .mmap = mxc_ipu_mmap,
++ .release = mxc_ipu_release,
++ .unlocked_ioctl = mxc_ipu_ioctl,
++};
++
++int register_ipu_device(struct ipu_soc *ipu, int id)
++{
++ int ret = 0;
++ static int idx;
++ static struct ipu_thread_data thread_data[5];
++
++ if (!major) {
++ major = register_chrdev(0, "mxc_ipu", &mxc_ipu_fops);
++ if (major < 0) {
++ printk(KERN_ERR "Unable to register mxc_ipu as a char device\n");
++ ret = major;
++ goto register_cdev_fail;
++ }
++
++ ipu_class = class_create(THIS_MODULE, "mxc_ipu");
++ if (IS_ERR(ipu_class)) {
++ ret = PTR_ERR(ipu_class);
++ goto ipu_class_fail;
++ }
++
++ ipu_dev = device_create(ipu_class, NULL, MKDEV(major, 0),
++ NULL, "mxc_ipu");
++ if (IS_ERR(ipu_dev)) {
++ ret = PTR_ERR(ipu_dev);
++ goto dev_create_fail;
++ }
++ ipu_dev->dma_mask = kmalloc(sizeof(*ipu_dev->dma_mask), GFP_KERNEL);
++ *ipu_dev->dma_mask = DMA_BIT_MASK(32);
++ ipu_dev->coherent_dma_mask = DMA_BIT_MASK(32);
++
++ mutex_init(&ipu_ch_tbl.lock);
++ }
++ max_ipu_no = ++id;
++ ipu->rot_dma[0].size = 0;
++ ipu->rot_dma[1].size = 0;
++
++ thread_data[idx].ipu = ipu;
++ thread_data[idx].id = 0;
++ thread_data[idx].is_vdoa = 0;
++ ipu->thread[0] = kthread_run(ipu_task_thread, &thread_data[idx++],
++ "ipu%d_task", id);
++ if (IS_ERR(ipu->thread[0])) {
++ ret = PTR_ERR(ipu->thread[0]);
++ goto kthread0_fail;
++ }
++
++ thread_data[idx].ipu = ipu;
++ thread_data[idx].id = 1;
++ thread_data[idx].is_vdoa = 0;
++ ipu->thread[1] = kthread_run(ipu_task_thread, &thread_data[idx++],
++ "ipu%d_task", id);
++ if (IS_ERR(ipu->thread[1])) {
++ ret = PTR_ERR(ipu->thread[1]);
++ goto kthread1_fail;
++ }
++
++
++ return ret;
++
++kthread1_fail:
++ kthread_stop(ipu->thread[0]);
++kthread0_fail:
++ if (id == 0)
++ device_destroy(ipu_class, MKDEV(major, 0));
++dev_create_fail:
++ if (id == 0) {
++ class_destroy(ipu_class);
++ }
++ipu_class_fail:
++ if (id == 0)
++ unregister_chrdev(major, "mxc_ipu");
++register_cdev_fail:
++ return ret;
++}
++
++void unregister_ipu_device(struct ipu_soc *ipu, int id)
++{
++ int i;
++
++ kthread_stop(ipu->thread[0]);
++ kthread_stop(ipu->thread[1]);
++ for (i = 0; i < 2; i++) {
++ if (ipu->rot_dma[i].vaddr)
++ dma_free_coherent(ipu_dev,
++ ipu->rot_dma[i].size,
++ ipu->rot_dma[i].vaddr,
++ ipu->rot_dma[i].paddr);
++ }
++
++ if (major) {
++ device_destroy(ipu_class, MKDEV(major, 0));
++ class_destroy(ipu_class);
++ unregister_chrdev(major, "mxc_ipu");
++ major = 0;
++ }
++}
+diff -Nur linux-4.1.3/drivers/mxc/ipu3/ipu_disp.c linux-xbian-imx6/drivers/mxc/ipu3/ipu_disp.c
+--- linux-4.1.3/drivers/mxc/ipu3/ipu_disp.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/ipu3/ipu_disp.c 2015-07-27 23:13:06.226765901 +0200
+@@ -0,0 +1,1956 @@
++/*
++ * Copyright 2005-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*!
++ * @file ipu_disp.c
++ *
++ * @brief IPU display submodule API functions
++ *
++ * @ingroup IPU
++ */
++
++#include <linux/clk.h>
++#include <linux/clk-provider.h>
++#include <linux/delay.h>
++#include <linux/err.h>
++#include <linux/errno.h>
++#include <linux/io.h>
++#include <linux/ipu-v3.h>
++#include <linux/module.h>
++#include <linux/spinlock.h>
++#include <linux/types.h>
++
++#include <asm/atomic.h>
++
++#include "ipu_param_mem.h"
++#include "ipu_regs.h"
++
++struct dp_csc_param_t {
++ int mode;
++ void *coeff;
++};
++
++#define SYNC_WAVE 0
++#define NULL_WAVE (-1)
++#define ASYNC_SER_WAVE 6
++
++/* DC display ID assignments */
++#define DC_DISP_ID_SYNC(di) (di)
++#define DC_DISP_ID_SERIAL 2
++#define DC_DISP_ID_ASYNC 3
++
++int dmfc_type_setup;
++
++void _ipu_dmfc_init(struct ipu_soc *ipu, int dmfc_type, int first)
++{
++ u32 dmfc_wr_chan, dmfc_dp_chan;
++
++ if (first) {
++ if (dmfc_type_setup > dmfc_type)
++ dmfc_type = dmfc_type_setup;
++ else
++ dmfc_type_setup = dmfc_type;
++
++ /* disable DMFC-IC channel*/
++ ipu_dmfc_write(ipu, 0x2, DMFC_IC_CTRL);
++ } else if (dmfc_type_setup >= DMFC_HIGH_RESOLUTION_DC) {
++ dev_dbg(ipu->dev, "DMFC high resolution has set, will not change\n");
++ return;
++ } else
++ dmfc_type_setup = dmfc_type;
++
++ if (dmfc_type == DMFC_HIGH_RESOLUTION_DC) {
++ /* 1 - segment 0~3;
++ * 5B - segement 4, 5;
++ * 5F - segement 6, 7;
++ * 1C, 2C and 6B, 6F unused;
++ */
++ dev_info(ipu->dev, "IPU DMFC DC HIGH RESOLUTION: 1(0~3), 5B(4,5), 5F(6,7)\n");
++ dmfc_wr_chan = 0x00000088;
++ dmfc_dp_chan = 0x00009694;
++ ipu->dmfc_size_28 = 256*4;
++ ipu->dmfc_size_29 = 0;
++ ipu->dmfc_size_24 = 0;
++ ipu->dmfc_size_27 = 128*4;
++ ipu->dmfc_size_23 = 128*4;
++ } else if (dmfc_type == DMFC_HIGH_RESOLUTION_DP) {
++ /* 1 - segment 0, 1;
++ * 5B - segement 2~5;
++ * 5F - segement 6,7;
++ * 1C, 2C and 6B, 6F unused;
++ */
++ dev_info(ipu->dev, "IPU DMFC DP HIGH RESOLUTION: 1(0,1), 5B(2~5), 5F(6,7)\n");
++ dmfc_wr_chan = 0x00000090;
++ dmfc_dp_chan = 0x0000968a;
++ ipu->dmfc_size_28 = 128*4;
++ ipu->dmfc_size_29 = 0;
++ ipu->dmfc_size_24 = 0;
++ ipu->dmfc_size_27 = 128*4;
++ ipu->dmfc_size_23 = 256*4;
++ } else if (dmfc_type == DMFC_HIGH_RESOLUTION_ONLY_DP) {
++ /* 5B - segement 0~3;
++ * 5F - segement 4~7;
++ * 1, 1C, 2C and 6B, 6F unused;
++ */
++ dev_info(ipu->dev, "IPU DMFC ONLY-DP HIGH RESOLUTION: 5B(0~3), 5F(4~7)\n");
++ dmfc_wr_chan = 0x00000000;
++ dmfc_dp_chan = 0x00008c88;
++ ipu->dmfc_size_28 = 0;
++ ipu->dmfc_size_29 = 0;
++ ipu->dmfc_size_24 = 0;
++ ipu->dmfc_size_27 = 256*4;
++ ipu->dmfc_size_23 = 256*4;
++ } else {
++ /* 1 - segment 0, 1;
++ * 5B - segement 4, 5;
++ * 5F - segement 6, 7;
++ * 1C, 2C and 6B, 6F unused;
++ */
++ dev_info(ipu->dev, "IPU DMFC NORMAL mode: 1(0~1), 5B(4,5), 5F(6,7)\n");
++ dmfc_wr_chan = 0x00000090;
++ dmfc_dp_chan = 0x00009694;
++ ipu->dmfc_size_28 = 128*4;
++ ipu->dmfc_size_29 = 0;
++ ipu->dmfc_size_24 = 0;
++ ipu->dmfc_size_27 = 128*4;
++ ipu->dmfc_size_23 = 128*4;
++ }
++ ipu_dmfc_write(ipu, dmfc_wr_chan, DMFC_WR_CHAN);
++ ipu_dmfc_write(ipu, 0x202020F6, DMFC_WR_CHAN_DEF);
++ ipu_dmfc_write(ipu, dmfc_dp_chan, DMFC_DP_CHAN);
++ /* Enable chan 5 watermark set at 5 bursts and clear at 7 bursts */
++ ipu_dmfc_write(ipu, 0x2020F6F6, DMFC_DP_CHAN_DEF);
++}
++
++static int __init dmfc_setup(char *options)
++{
++ get_option(&options, &dmfc_type_setup);
++ if (dmfc_type_setup > DMFC_HIGH_RESOLUTION_ONLY_DP)
++ dmfc_type_setup = DMFC_HIGH_RESOLUTION_ONLY_DP;
++ return 1;
++}
++__setup("dmfc=", dmfc_setup);
++
++void _ipu_dmfc_set_wait4eot(struct ipu_soc *ipu, int dma_chan, int width)
++{
++ u32 dmfc_gen1 = ipu_dmfc_read(ipu, DMFC_GENERAL1);
++
++ if (width >= HIGH_RESOLUTION_WIDTH) {
++ if (dma_chan == 23)
++ _ipu_dmfc_init(ipu, DMFC_HIGH_RESOLUTION_DP, 0);
++ else if (dma_chan == 28)
++ _ipu_dmfc_init(ipu, DMFC_HIGH_RESOLUTION_DC, 0);
++ }
++
++ if (dma_chan == 23) { /*5B*/
++ if (ipu->dmfc_size_23/width > 3)
++ dmfc_gen1 |= 1UL << 20;
++ else
++ dmfc_gen1 &= ~(1UL << 20);
++ } else if (dma_chan == 24) { /*6B*/
++ if (ipu->dmfc_size_24/width > 1)
++ dmfc_gen1 |= 1UL << 22;
++ else
++ dmfc_gen1 &= ~(1UL << 22);
++ } else if (dma_chan == 27) { /*5F*/
++ if (ipu->dmfc_size_27/width > 2)
++ dmfc_gen1 |= 1UL << 21;
++ else
++ dmfc_gen1 &= ~(1UL << 21);
++ } else if (dma_chan == 28) { /*1*/
++ if (ipu->dmfc_size_28/width > 2)
++ dmfc_gen1 |= 1UL << 16;
++ else
++ dmfc_gen1 &= ~(1UL << 16);
++ } else if (dma_chan == 29) { /*6F*/
++ if (ipu->dmfc_size_29/width > 1)
++ dmfc_gen1 |= 1UL << 23;
++ else
++ dmfc_gen1 &= ~(1UL << 23);
++ }
++
++ ipu_dmfc_write(ipu, dmfc_gen1, DMFC_GENERAL1);
++}
++
++void _ipu_dmfc_set_burst_size(struct ipu_soc *ipu, int dma_chan, int burst_size)
++{
++ u32 dmfc_wr_chan = ipu_dmfc_read(ipu, DMFC_WR_CHAN);
++ u32 dmfc_dp_chan = ipu_dmfc_read(ipu, DMFC_DP_CHAN);
++ int dmfc_bs = 0;
++
++ switch (burst_size) {
++ case 64:
++ dmfc_bs = 0x40;
++ break;
++ case 32:
++ case 20:
++ dmfc_bs = 0x80;
++ break;
++ case 16:
++ dmfc_bs = 0xc0;
++ break;
++ default:
++ dev_err(ipu->dev, "Unsupported burst size %d\n",
++ burst_size);
++ return;
++ }
++
++ if (dma_chan == 23) { /*5B*/
++ dmfc_dp_chan &= ~(0xc0);
++ dmfc_dp_chan |= dmfc_bs;
++ } else if (dma_chan == 27) { /*5F*/
++ dmfc_dp_chan &= ~(0xc000);
++ dmfc_dp_chan |= (dmfc_bs << 8);
++ } else if (dma_chan == 28) { /*1*/
++ dmfc_wr_chan &= ~(0xc0);
++ dmfc_wr_chan |= dmfc_bs;
++ }
++
++ ipu_dmfc_write(ipu, dmfc_wr_chan, DMFC_WR_CHAN);
++ ipu_dmfc_write(ipu, dmfc_dp_chan, DMFC_DP_CHAN);
++}
++
++static void _ipu_di_data_wave_config(struct ipu_soc *ipu,
++ int di, int wave_gen,
++ int access_size, int component_size)
++{
++ u32 reg;
++ reg = (access_size << DI_DW_GEN_ACCESS_SIZE_OFFSET) |
++ (component_size << DI_DW_GEN_COMPONENT_SIZE_OFFSET);
++ ipu_di_write(ipu, di, reg, DI_DW_GEN(wave_gen));
++}
++
++static void _ipu_di_data_pin_config(struct ipu_soc *ipu,
++ int di, int wave_gen, int di_pin, int set,
++ int up, int down)
++{
++ u32 reg;
++
++ reg = ipu_di_read(ipu, di, DI_DW_GEN(wave_gen));
++ reg &= ~(0x3 << (di_pin * 2));
++ reg |= set << (di_pin * 2);
++ ipu_di_write(ipu, di, reg, DI_DW_GEN(wave_gen));
++
++ ipu_di_write(ipu, di, (down << 16) | up, DI_DW_SET(wave_gen, set));
++}
++
++static void _ipu_di_sync_config(struct ipu_soc *ipu,
++ int di, int wave_gen,
++ int run_count, int run_src,
++ int offset_count, int offset_src,
++ int repeat_count, int cnt_clr_src,
++ int cnt_polarity_gen_en,
++ int cnt_polarity_clr_src,
++ int cnt_polarity_trigger_src,
++ int cnt_up, int cnt_down)
++{
++ u32 reg;
++
++ if ((run_count >= 0x1000) || (offset_count >= 0x1000) || (repeat_count >= 0x1000) ||
++ (cnt_up >= 0x400) || (cnt_down >= 0x400)) {
++ dev_err(ipu->dev, "DI%d counters out of range.\n", di);
++ return;
++ }
++
++ reg = (run_count << 19) | (++run_src << 16) |
++ (offset_count << 3) | ++offset_src;
++ ipu_di_write(ipu, di, reg, DI_SW_GEN0(wave_gen));
++ reg = (cnt_polarity_gen_en << 29) | (++cnt_clr_src << 25) |
++ (++cnt_polarity_trigger_src << 12) | (++cnt_polarity_clr_src << 9);
++ reg |= (cnt_down << 16) | cnt_up;
++ if (repeat_count == 0) {
++ /* Enable auto reload */
++ reg |= 0x10000000;
++ }
++ ipu_di_write(ipu, di, reg, DI_SW_GEN1(wave_gen));
++ reg = ipu_di_read(ipu, di, DI_STP_REP(wave_gen));
++ reg &= ~(0xFFFF << (16 * ((wave_gen - 1) & 0x1)));
++ reg |= repeat_count << (16 * ((wave_gen - 1) & 0x1));
++ ipu_di_write(ipu, di, reg, DI_STP_REP(wave_gen));
++}
++
++static void _ipu_dc_map_link(struct ipu_soc *ipu,
++ int current_map,
++ int base_map_0, int buf_num_0,
++ int base_map_1, int buf_num_1,
++ int base_map_2, int buf_num_2)
++{
++ int ptr_0 = base_map_0 * 3 + buf_num_0;
++ int ptr_1 = base_map_1 * 3 + buf_num_1;
++ int ptr_2 = base_map_2 * 3 + buf_num_2;
++ int ptr;
++ u32 reg;
++ ptr = (ptr_2 << 10) + (ptr_1 << 5) + ptr_0;
++
++ reg = ipu_dc_read(ipu, DC_MAP_CONF_PTR(current_map));
++ reg &= ~(0x1F << ((16 * (current_map & 0x1))));
++ reg |= ptr << ((16 * (current_map & 0x1)));
++ ipu_dc_write(ipu, reg, DC_MAP_CONF_PTR(current_map));
++}
++
++static void _ipu_dc_map_config(struct ipu_soc *ipu,
++ int map, int byte_num, int offset, int mask)
++{
++ int ptr = map * 3 + byte_num;
++ u32 reg;
++
++ reg = ipu_dc_read(ipu, DC_MAP_CONF_VAL(ptr));
++ reg &= ~(0xFFFF << (16 * (ptr & 0x1)));
++ reg |= ((offset << 8) | mask) << (16 * (ptr & 0x1));
++ ipu_dc_write(ipu, reg, DC_MAP_CONF_VAL(ptr));
++
++ reg = ipu_dc_read(ipu, DC_MAP_CONF_PTR(map));
++ reg &= ~(0x1F << ((16 * (map & 0x1)) + (5 * byte_num)));
++ reg |= ptr << ((16 * (map & 0x1)) + (5 * byte_num));
++ ipu_dc_write(ipu, reg, DC_MAP_CONF_PTR(map));
++}
++
++static void _ipu_dc_map_clear(struct ipu_soc *ipu, int map)
++{
++ u32 reg = ipu_dc_read(ipu, DC_MAP_CONF_PTR(map));
++ ipu_dc_write(ipu, reg & ~(0xFFFF << (16 * (map & 0x1))),
++ DC_MAP_CONF_PTR(map));
++}
++
++static void _ipu_dc_write_tmpl(struct ipu_soc *ipu,
++ int word, u32 opcode, u32 operand, int map,
++ int wave, int glue, int sync, int stop)
++{
++ u32 reg;
++
++ if (opcode == WRG) {
++ reg = sync;
++ reg |= (glue << 4);
++ reg |= (++wave << 11);
++ reg |= ((operand & 0x1FFFF) << 15);
++ ipu_dc_tmpl_write(ipu, reg, word * 8);
++
++ reg = (operand >> 17);
++ reg |= opcode << 7;
++ reg |= (stop << 9);
++ ipu_dc_tmpl_write(ipu, reg, word * 8 + 4);
++ } else {
++ reg = sync;
++ reg |= (glue << 4);
++ reg |= (++wave << 11);
++ reg |= (++map << 15);
++ reg |= (operand << 20) & 0xFFF00000;
++ ipu_dc_tmpl_write(ipu, reg, word * 8);
++
++ reg = (operand >> 12);
++ reg |= opcode << 4;
++ reg |= (stop << 9);
++ ipu_dc_tmpl_write(ipu, reg, word * 8 + 4);
++ }
++}
++
++static void _ipu_dc_link_event(struct ipu_soc *ipu,
++ int chan, int event, int addr, int priority)
++{
++ u32 reg;
++ u32 address_shift;
++ if (event < DC_EVEN_UGDE0) {
++ reg = ipu_dc_read(ipu, DC_RL_CH(chan, event));
++ reg &= ~(0xFFFF << (16 * (event & 0x1)));
++ reg |= ((addr << 8) | priority) << (16 * (event & 0x1));
++ ipu_dc_write(ipu, reg, DC_RL_CH(chan, event));
++ } else {
++ reg = ipu_dc_read(ipu, DC_UGDE_0((event - DC_EVEN_UGDE0) / 2));
++ if ((event - DC_EVEN_UGDE0) & 0x1) {
++ reg &= ~(0x2FF << 16);
++ reg |= (addr << 16);
++ reg |= priority ? (2 << 24) : 0x0;
++ } else {
++ reg &= ~0xFC00FFFF;
++ if (priority)
++ chan = (chan >> 1) +
++ ((((chan & 0x1) + ((chan & 0x2) >> 1))) | (chan >> 3));
++ else
++ chan = 0x7;
++ address_shift = ((event - DC_EVEN_UGDE0) >> 1) ? 7 : 8;
++ reg |= (addr << address_shift) | (priority << 3) | chan;
++ }
++ ipu_dc_write(ipu, reg, DC_UGDE_0((event - DC_EVEN_UGDE0) / 2));
++ }
++}
++
++/* Y = R * 1.200 + G * 2.343 + B * .453 + 0.250;
++ U = R * -.672 + G * -1.328 + B * 2.000 + 512.250.;
++ V = R * 2.000 + G * -1.672 + B * -.328 + 512.250.;*/
++static const int rgb2ycbcr_coeff[5][3] = {
++ {0x4D, 0x96, 0x1D},
++ {-0x2B, -0x55, 0x80},
++ {0x80, -0x6B, -0x15},
++ {0x0000, 0x0200, 0x0200}, /* B0, B1, B2 */
++ {0x2, 0x2, 0x2}, /* S0, S1, S2 */
++};
++
++/* R = (1.164 * (Y - 16)) + (1.596 * (Cr - 128));
++ G = (1.164 * (Y - 16)) - (0.392 * (Cb - 128)) - (0.813 * (Cr - 128));
++ B = (1.164 * (Y - 16)) + (2.017 * (Cb - 128); */
++static const int ycbcr2rgb_coeff[5][3] = {
++ {0x095, 0x000, 0x0CC},
++ {0x095, 0x3CE, 0x398},
++ {0x095, 0x0FF, 0x000},
++ {0x3E42, 0x010A, 0x3DD6}, /*B0,B1,B2 */
++ {0x1, 0x1, 0x1}, /*S0,S1,S2 */
++};
++
++#define mask_a(a) ((u32)(a) & 0x3FF)
++#define mask_b(b) ((u32)(b) & 0x3FFF)
++
++/* Pls keep S0, S1 and S2 as 0x2 by using this convertion */
++static int _rgb_to_yuv(int n, int red, int green, int blue)
++{
++ int c;
++ c = red * rgb2ycbcr_coeff[n][0];
++ c += green * rgb2ycbcr_coeff[n][1];
++ c += blue * rgb2ycbcr_coeff[n][2];
++ c /= 16;
++ c += rgb2ycbcr_coeff[3][n] * 4;
++ c += 8;
++ c /= 16;
++ if (c < 0)
++ c = 0;
++ if (c > 255)
++ c = 255;
++ return c;
++}
++
++/*
++ * Row is for BG: RGB2YUV YUV2RGB RGB2RGB YUV2YUV CSC_NONE
++ * Column is for FG: RGB2YUV YUV2RGB RGB2RGB YUV2YUV CSC_NONE
++ */
++static struct dp_csc_param_t dp_csc_array[CSC_NUM][CSC_NUM] = {
++{{DP_COM_CONF_CSC_DEF_BOTH, &rgb2ycbcr_coeff}, {0, 0}, {0, 0}, {DP_COM_CONF_CSC_DEF_BG, &rgb2ycbcr_coeff}, {DP_COM_CONF_CSC_DEF_BG, &rgb2ycbcr_coeff} },
++{{0, 0}, {DP_COM_CONF_CSC_DEF_BOTH, &ycbcr2rgb_coeff}, {DP_COM_CONF_CSC_DEF_BG, &ycbcr2rgb_coeff}, {0, 0}, {DP_COM_CONF_CSC_DEF_BG, &ycbcr2rgb_coeff} },
++{{0, 0}, {DP_COM_CONF_CSC_DEF_FG, &ycbcr2rgb_coeff}, {0, 0}, {0, 0}, {0, 0} },
++{{DP_COM_CONF_CSC_DEF_FG, &rgb2ycbcr_coeff}, {0, 0}, {0, 0}, {0, 0}, {0, 0} },
++{{DP_COM_CONF_CSC_DEF_FG, &rgb2ycbcr_coeff}, {DP_COM_CONF_CSC_DEF_FG, &ycbcr2rgb_coeff}, {0, 0}, {0, 0}, {0, 0} }
++};
++
++void __ipu_dp_csc_setup(struct ipu_soc *ipu,
++ int dp, struct dp_csc_param_t dp_csc_param,
++ bool srm_mode_update)
++{
++ u32 reg;
++ const int (*coeff)[5][3];
++
++ if (dp_csc_param.mode >= 0) {
++ reg = ipu_dp_read(ipu, DP_COM_CONF(dp));
++ reg &= ~DP_COM_CONF_CSC_DEF_MASK;
++ reg |= dp_csc_param.mode;
++ ipu_dp_write(ipu, reg, DP_COM_CONF(dp));
++ }
++
++ coeff = dp_csc_param.coeff;
++
++ if (coeff) {
++ ipu_dp_write(ipu, mask_a((*coeff)[0][0]) |
++ (mask_a((*coeff)[0][1]) << 16), DP_CSC_A_0(dp));
++ ipu_dp_write(ipu, mask_a((*coeff)[0][2]) |
++ (mask_a((*coeff)[1][0]) << 16), DP_CSC_A_1(dp));
++ ipu_dp_write(ipu, mask_a((*coeff)[1][1]) |
++ (mask_a((*coeff)[1][2]) << 16), DP_CSC_A_2(dp));
++ ipu_dp_write(ipu, mask_a((*coeff)[2][0]) |
++ (mask_a((*coeff)[2][1]) << 16), DP_CSC_A_3(dp));
++ ipu_dp_write(ipu, mask_a((*coeff)[2][2]) |
++ (mask_b((*coeff)[3][0]) << 16) |
++ ((*coeff)[4][0] << 30), DP_CSC_0(dp));
++ ipu_dp_write(ipu, mask_b((*coeff)[3][1]) | ((*coeff)[4][1] << 14) |
++ (mask_b((*coeff)[3][2]) << 16) |
++ ((*coeff)[4][2] << 30), DP_CSC_1(dp));
++ }
++
++ if (srm_mode_update) {
++ reg = ipu_cm_read(ipu, IPU_SRM_PRI2) | 0x8;
++ ipu_cm_write(ipu, reg, IPU_SRM_PRI2);
++ }
++}
++
++int _ipu_dp_init(struct ipu_soc *ipu,
++ ipu_channel_t channel, uint32_t in_pixel_fmt,
++ uint32_t out_pixel_fmt)
++{
++ int in_fmt, out_fmt;
++ int dp;
++ int partial = false;
++ uint32_t reg;
++
++ if (channel == MEM_FG_SYNC) {
++ dp = DP_SYNC;
++ partial = true;
++ } else if (channel == MEM_BG_SYNC) {
++ dp = DP_SYNC;
++ partial = false;
++ } else if (channel == MEM_BG_ASYNC0) {
++ dp = DP_ASYNC0;
++ partial = false;
++ } else {
++ return -EINVAL;
++ }
++
++ in_fmt = format_to_colorspace(in_pixel_fmt);
++ out_fmt = format_to_colorspace(out_pixel_fmt);
++
++ if (partial) {
++ if (in_fmt == RGB) {
++ if (out_fmt == RGB)
++ ipu->fg_csc_type = RGB2RGB;
++ else
++ ipu->fg_csc_type = RGB2YUV;
++ } else {
++ if (out_fmt == RGB)
++ ipu->fg_csc_type = YUV2RGB;
++ else
++ ipu->fg_csc_type = YUV2YUV;
++ }
++ } else {
++ if (in_fmt == RGB) {
++ if (out_fmt == RGB)
++ ipu->bg_csc_type = RGB2RGB;
++ else
++ ipu->bg_csc_type = RGB2YUV;
++ } else {
++ if (out_fmt == RGB)
++ ipu->bg_csc_type = YUV2RGB;
++ else
++ ipu->bg_csc_type = YUV2YUV;
++ }
++ }
++
++ /* Transform color key from rgb to yuv if CSC is enabled */
++ reg = ipu_dp_read(ipu, DP_COM_CONF(dp));
++ if (ipu->color_key_4rgb && (reg & DP_COM_CONF_GWCKE) &&
++ (((ipu->fg_csc_type == RGB2YUV) && (ipu->bg_csc_type == YUV2YUV)) ||
++ ((ipu->fg_csc_type == YUV2YUV) && (ipu->bg_csc_type == RGB2YUV)) ||
++ ((ipu->fg_csc_type == YUV2YUV) && (ipu->bg_csc_type == YUV2YUV)) ||
++ ((ipu->fg_csc_type == YUV2RGB) && (ipu->bg_csc_type == YUV2RGB)))) {
++ int red, green, blue;
++ int y, u, v;
++ uint32_t color_key = ipu_dp_read(ipu, DP_GRAPH_WIND_CTRL(dp)) & 0xFFFFFFL;
++
++ dev_dbg(ipu->dev, "_ipu_dp_init color key 0x%x need change to yuv fmt!\n", color_key);
++
++ red = (color_key >> 16) & 0xFF;
++ green = (color_key >> 8) & 0xFF;
++ blue = color_key & 0xFF;
++
++ y = _rgb_to_yuv(0, red, green, blue);
++ u = _rgb_to_yuv(1, red, green, blue);
++ v = _rgb_to_yuv(2, red, green, blue);
++ color_key = (y << 16) | (u << 8) | v;
++
++ reg = ipu_dp_read(ipu, DP_GRAPH_WIND_CTRL(dp)) & 0xFF000000L;
++ ipu_dp_write(ipu, reg | color_key, DP_GRAPH_WIND_CTRL(dp));
++ ipu->color_key_4rgb = false;
++
++ dev_dbg(ipu->dev, "_ipu_dp_init color key change to yuv fmt 0x%x!\n", color_key);
++ }
++
++ __ipu_dp_csc_setup(ipu, dp, dp_csc_array[ipu->bg_csc_type][ipu->fg_csc_type], true);
++
++ return 0;
++}
++
++void _ipu_dp_uninit(struct ipu_soc *ipu, ipu_channel_t channel)
++{
++ int dp;
++ int partial = false;
++
++ if (channel == MEM_FG_SYNC) {
++ dp = DP_SYNC;
++ partial = true;
++ } else if (channel == MEM_BG_SYNC) {
++ dp = DP_SYNC;
++ partial = false;
++ } else if (channel == MEM_BG_ASYNC0) {
++ dp = DP_ASYNC0;
++ partial = false;
++ } else {
++ return;
++ }
++
++ if (partial)
++ ipu->fg_csc_type = CSC_NONE;
++ else
++ ipu->bg_csc_type = CSC_NONE;
++
++ __ipu_dp_csc_setup(ipu, dp, dp_csc_array[ipu->bg_csc_type][ipu->fg_csc_type], false);
++}
++
++void _ipu_dc_init(struct ipu_soc *ipu, int dc_chan, int di, bool interlaced, uint32_t pixel_fmt)
++{
++ u32 reg = 0;
++
++ if ((dc_chan == 1) || (dc_chan == 5)) {
++ if (interlaced) {
++ if (di) {
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NL, 1, 3);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_EOL, 1, 2);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA, 1, 1);
++ if ((pixel_fmt == IPU_PIX_FMT_YUYV) ||
++ (pixel_fmt == IPU_PIX_FMT_UYVY) ||
++ (pixel_fmt == IPU_PIX_FMT_YVYU) ||
++ (pixel_fmt == IPU_PIX_FMT_VYUY)) {
++ _ipu_dc_link_event(ipu, dc_chan, DC_ODD_UGDE1, 9, 5);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVEN_UGDE1, 8, 5);
++ }
++ } else {
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NL, 0, 3);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_EOL, 0, 2);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA, 0, 1);
++ if ((pixel_fmt == IPU_PIX_FMT_YUYV) ||
++ (pixel_fmt == IPU_PIX_FMT_UYVY) ||
++ (pixel_fmt == IPU_PIX_FMT_YVYU) ||
++ (pixel_fmt == IPU_PIX_FMT_VYUY)) {
++ _ipu_dc_link_event(ipu, dc_chan, DC_ODD_UGDE0, 10, 5);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVEN_UGDE0, 11, 5);
++ }
++ }
++ } else {
++ if (di) {
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NL, 2, 3);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_EOL, 3, 2);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA, 1, 1);
++ if ((pixel_fmt == IPU_PIX_FMT_YUYV) ||
++ (pixel_fmt == IPU_PIX_FMT_UYVY) ||
++ (pixel_fmt == IPU_PIX_FMT_YVYU) ||
++ (pixel_fmt == IPU_PIX_FMT_VYUY)) {
++ _ipu_dc_link_event(ipu, dc_chan, DC_ODD_UGDE1, 9, 5);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVEN_UGDE1, 8, 5);
++ }
++ } else {
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NL, 5, 3);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_EOL, 6, 2);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA, 12, 1);
++ if ((pixel_fmt == IPU_PIX_FMT_YUYV) ||
++ (pixel_fmt == IPU_PIX_FMT_UYVY) ||
++ (pixel_fmt == IPU_PIX_FMT_YVYU) ||
++ (pixel_fmt == IPU_PIX_FMT_VYUY)) {
++ _ipu_dc_link_event(ipu, dc_chan, DC_ODD_UGDE0, 10, 5);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVEN_UGDE0, 11, 5);
++ }
++ }
++ }
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NF, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NFIELD, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_EOF, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_EOFIELD, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_CHAN, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_ADDR, 0, 0);
++
++ reg = 0x2;
++ reg |= DC_DISP_ID_SYNC(di) << DC_WR_CH_CONF_PROG_DISP_ID_OFFSET;
++ reg |= di << 2;
++ if (interlaced)
++ reg |= DC_WR_CH_CONF_FIELD_MODE;
++ } else if ((dc_chan == 8) || (dc_chan == 9)) {
++ /* async channels */
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA_W_0, 0x64, 1);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA_W_1, 0x64, 1);
++
++ reg = 0x3;
++ reg |= DC_DISP_ID_SERIAL << DC_WR_CH_CONF_PROG_DISP_ID_OFFSET;
++ }
++ ipu_dc_write(ipu, reg, DC_WR_CH_CONF(dc_chan));
++
++ ipu_dc_write(ipu, 0x00000000, DC_WR_CH_ADDR(dc_chan));
++
++ ipu_dc_write(ipu, 0x00000084, DC_GEN);
++}
++
++void _ipu_dc_uninit(struct ipu_soc *ipu, int dc_chan)
++{
++ if ((dc_chan == 1) || (dc_chan == 5)) {
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NL, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_EOL, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NF, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NFIELD, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_EOF, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_EOFIELD, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_CHAN, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_ADDR, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_ODD_UGDE0, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVEN_UGDE0, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_ODD_UGDE1, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVEN_UGDE1, 0, 0);
++ } else if ((dc_chan == 8) || (dc_chan == 9)) {
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_ADDR_W_0, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_ADDR_W_1, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_CHAN_W_0, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_CHAN_W_1, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA_W_0, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA_W_1, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_ADDR_R_0, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_ADDR_R_1, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_CHAN_R_0, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_CHAN_R_1, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA_R_0, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA_R_1, 0, 0);
++ }
++}
++
++int _ipu_disp_chan_is_interlaced(struct ipu_soc *ipu, ipu_channel_t channel)
++{
++ if (channel == MEM_DC_SYNC)
++ return !!(ipu_dc_read(ipu, DC_WR_CH_CONF_1) &
++ DC_WR_CH_CONF_FIELD_MODE);
++ else if ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC))
++ return !!(ipu_dc_read(ipu, DC_WR_CH_CONF_5) &
++ DC_WR_CH_CONF_FIELD_MODE);
++ return 0;
++}
++
++void _ipu_dp_dc_enable(struct ipu_soc *ipu, ipu_channel_t channel)
++{
++ int di;
++ uint32_t reg;
++ uint32_t dc_chan;
++ int irq = 0;
++
++ if (channel == MEM_FG_SYNC)
++ irq = IPU_IRQ_DP_SF_END;
++ else if (channel == MEM_DC_SYNC)
++ dc_chan = 1;
++ else if (channel == MEM_BG_SYNC)
++ dc_chan = 5;
++ else
++ return;
++
++ if (channel == MEM_FG_SYNC) {
++ /* Enable FG channel */
++ reg = ipu_dp_read(ipu, DP_COM_CONF(DP_SYNC));
++ ipu_dp_write(ipu, reg | DP_COM_CONF_FG_EN, DP_COM_CONF(DP_SYNC));
++
++ reg = ipu_cm_read(ipu, IPU_SRM_PRI2) | 0x8;
++ ipu_cm_write(ipu, reg, IPU_SRM_PRI2);
++ return;
++ } else if (channel == MEM_BG_SYNC) {
++ reg = ipu_cm_read(ipu, IPU_SRM_PRI2) | 0x8;
++ ipu_cm_write(ipu, reg, IPU_SRM_PRI2);
++ }
++
++ di = ipu->dc_di_assignment[dc_chan];
++
++ /* Make sure other DC sync channel is not assigned same DI */
++ reg = ipu_dc_read(ipu, DC_WR_CH_CONF(6 - dc_chan));
++ if ((di << 2) == (reg & DC_WR_CH_CONF_PROG_DI_ID)) {
++ reg &= ~DC_WR_CH_CONF_PROG_DI_ID;
++ reg |= di ? 0 : DC_WR_CH_CONF_PROG_DI_ID;
++ ipu_dc_write(ipu, reg, DC_WR_CH_CONF(6 - dc_chan));
++ }
++
++ reg = ipu_dc_read(ipu, DC_WR_CH_CONF(dc_chan));
++ reg |= 4 << DC_WR_CH_CONF_PROG_TYPE_OFFSET;
++ ipu_dc_write(ipu, reg, DC_WR_CH_CONF(dc_chan));
++
++ clk_prepare_enable(ipu->pixel_clk[di]);
++}
++
++static irqreturn_t dc_irq_handler(int irq, void *dev_id)
++{
++ struct ipu_soc *ipu = dev_id;
++ struct completion *comp = &ipu->dc_comp;
++ uint32_t reg;
++ uint32_t dc_chan;
++
++ if (irq == IPU_IRQ_DC_FC_1)
++ dc_chan = 1;
++ else
++ dc_chan = 5;
++
++ if (!ipu->dc_swap) {
++ reg = ipu_dc_read(ipu, DC_WR_CH_CONF(dc_chan));
++ reg &= ~DC_WR_CH_CONF_PROG_TYPE_MASK;
++ ipu_dc_write(ipu, reg, DC_WR_CH_CONF(dc_chan));
++
++ reg = ipu_cm_read(ipu, IPU_DISP_GEN);
++ if (ipu->dc_di_assignment[dc_chan])
++ reg &= ~DI1_COUNTER_RELEASE;
++ else
++ reg &= ~DI0_COUNTER_RELEASE;
++ ipu_cm_write(ipu, reg, IPU_DISP_GEN);
++ }
++
++ complete(comp);
++ return IRQ_HANDLED;
++}
++
++void _ipu_dp_dc_disable(struct ipu_soc *ipu, ipu_channel_t channel, bool swap)
++{
++ int ret;
++ uint32_t reg;
++ uint32_t csc;
++ uint32_t dc_chan;
++ int irq = 0;
++ int timeout = 50;
++
++ ipu->dc_swap = swap;
++
++ if (channel == MEM_DC_SYNC) {
++ dc_chan = 1;
++ irq = IPU_IRQ_DC_FC_1;
++ } else if (channel == MEM_BG_SYNC) {
++ dc_chan = 5;
++ irq = IPU_IRQ_DP_SF_END;
++ } else if (channel == MEM_FG_SYNC) {
++ /* Disable FG channel */
++ dc_chan = 5;
++
++ reg = ipu_dp_read(ipu, DP_COM_CONF(DP_SYNC));
++ csc = reg & DP_COM_CONF_CSC_DEF_MASK;
++ if (csc == DP_COM_CONF_CSC_DEF_FG)
++ reg &= ~DP_COM_CONF_CSC_DEF_MASK;
++
++ reg &= ~DP_COM_CONF_FG_EN;
++ ipu_dp_write(ipu, reg, DP_COM_CONF(DP_SYNC));
++
++ reg = ipu_cm_read(ipu, IPU_SRM_PRI2) | 0x8;
++ ipu_cm_write(ipu, reg, IPU_SRM_PRI2);
++
++ if (ipu_is_channel_busy(ipu, MEM_BG_SYNC)) {
++ ipu_cm_write(ipu, IPUIRQ_2_MASK(IPU_IRQ_DP_SF_END),
++ IPUIRQ_2_STATREG(IPU_IRQ_DP_SF_END));
++ while ((ipu_cm_read(ipu, IPUIRQ_2_STATREG(IPU_IRQ_DP_SF_END)) &
++ IPUIRQ_2_MASK(IPU_IRQ_DP_SF_END)) == 0) {
++ msleep(2);
++ timeout -= 2;
++ if (timeout <= 0)
++ break;
++ }
++ }
++ return;
++ } else {
++ return;
++ }
++
++ init_completion(&ipu->dc_comp);
++ ret = ipu_request_irq(ipu, irq, dc_irq_handler, 0, NULL, ipu);
++ if (ret < 0) {
++ dev_err(ipu->dev, "DC irq %d in use\n", irq);
++ return;
++ }
++ ret = wait_for_completion_timeout(&ipu->dc_comp, msecs_to_jiffies(50));
++ ipu_free_irq(ipu, irq, ipu);
++ dev_dbg(ipu->dev, "DC stop timeout - %d * 10ms\n", 5 - ret);
++
++ if (ipu->dc_swap) {
++ /* Swap DC channel 1 and 5 settings, and disable old dc chan */
++ reg = ipu_dc_read(ipu, DC_WR_CH_CONF(dc_chan));
++ ipu_dc_write(ipu, reg, DC_WR_CH_CONF(6 - dc_chan));
++ reg &= ~DC_WR_CH_CONF_PROG_TYPE_MASK;
++ reg ^= DC_WR_CH_CONF_PROG_DI_ID;
++ ipu_dc_write(ipu, reg, DC_WR_CH_CONF(dc_chan));
++ }
++}
++
++void _ipu_init_dc_mappings(struct ipu_soc *ipu)
++{
++ /* IPU_PIX_FMT_RGB24 */
++ _ipu_dc_map_clear(ipu, 0);
++ _ipu_dc_map_config(ipu, 0, 0, 7, 0xFF);
++ _ipu_dc_map_config(ipu, 0, 1, 15, 0xFF);
++ _ipu_dc_map_config(ipu, 0, 2, 23, 0xFF);
++
++ /* IPU_PIX_FMT_RGB666 */
++ _ipu_dc_map_clear(ipu, 1);
++ _ipu_dc_map_config(ipu, 1, 0, 5, 0xFC);
++ _ipu_dc_map_config(ipu, 1, 1, 11, 0xFC);
++ _ipu_dc_map_config(ipu, 1, 2, 17, 0xFC);
++
++ /* IPU_PIX_FMT_YUV444 */
++ _ipu_dc_map_clear(ipu, 2);
++ _ipu_dc_map_config(ipu, 2, 0, 15, 0xFF);
++ _ipu_dc_map_config(ipu, 2, 1, 23, 0xFF);
++ _ipu_dc_map_config(ipu, 2, 2, 7, 0xFF);
++
++ /* IPU_PIX_FMT_RGB565 */
++ _ipu_dc_map_clear(ipu, 3);
++ _ipu_dc_map_config(ipu, 3, 0, 4, 0xF8);
++ _ipu_dc_map_config(ipu, 3, 1, 10, 0xFC);
++ _ipu_dc_map_config(ipu, 3, 2, 15, 0xF8);
++
++ /* IPU_PIX_FMT_LVDS666 */
++ _ipu_dc_map_clear(ipu, 4);
++ _ipu_dc_map_config(ipu, 4, 0, 5, 0xFC);
++ _ipu_dc_map_config(ipu, 4, 1, 13, 0xFC);
++ _ipu_dc_map_config(ipu, 4, 2, 21, 0xFC);
++
++ /* IPU_PIX_FMT_VYUY 16bit width */
++ _ipu_dc_map_clear(ipu, 5);
++ _ipu_dc_map_config(ipu, 5, 0, 7, 0xFF);
++ _ipu_dc_map_config(ipu, 5, 1, 0, 0x0);
++ _ipu_dc_map_config(ipu, 5, 2, 15, 0xFF);
++ _ipu_dc_map_clear(ipu, 6);
++ _ipu_dc_map_config(ipu, 6, 0, 0, 0x0);
++ _ipu_dc_map_config(ipu, 6, 1, 7, 0xFF);
++ _ipu_dc_map_config(ipu, 6, 2, 15, 0xFF);
++
++ /* IPU_PIX_FMT_UYUV 16bit width */
++ _ipu_dc_map_clear(ipu, 7);
++ _ipu_dc_map_link(ipu, 7, 6, 0, 6, 1, 6, 2);
++ _ipu_dc_map_clear(ipu, 8);
++ _ipu_dc_map_link(ipu, 8, 5, 0, 5, 1, 5, 2);
++
++ /* IPU_PIX_FMT_YUYV 16bit width */
++ _ipu_dc_map_clear(ipu, 9);
++ _ipu_dc_map_link(ipu, 9, 5, 2, 5, 1, 5, 0);
++ _ipu_dc_map_clear(ipu, 10);
++ _ipu_dc_map_link(ipu, 10, 5, 1, 5, 2, 5, 0);
++
++ /* IPU_PIX_FMT_YVYU 16bit width */
++ _ipu_dc_map_clear(ipu, 11);
++ _ipu_dc_map_link(ipu, 11, 5, 1, 5, 2, 5, 0);
++ _ipu_dc_map_clear(ipu, 12);
++ _ipu_dc_map_link(ipu, 12, 5, 2, 5, 1, 5, 0);
++
++ /* IPU_PIX_FMT_GBR24 */
++ /* IPU_PIX_FMT_VYU444 */
++ _ipu_dc_map_clear(ipu, 13);
++ _ipu_dc_map_link(ipu, 13, 0, 2, 0, 0, 0, 1);
++
++ /* IPU_PIX_FMT_BGR24 */
++ _ipu_dc_map_clear(ipu, 14);
++ _ipu_dc_map_link(ipu, 14, 0, 2, 0, 1, 0, 0);
++}
++
++int _ipu_pixfmt_to_map(uint32_t fmt)
++{
++ switch (fmt) {
++ case IPU_PIX_FMT_GENERIC:
++ case IPU_PIX_FMT_RGB24:
++ return 0;
++ case IPU_PIX_FMT_RGB666:
++ return 1;
++ case IPU_PIX_FMT_YUV444:
++ return 2;
++ case IPU_PIX_FMT_RGB565:
++ return 3;
++ case IPU_PIX_FMT_LVDS666:
++ return 4;
++ case IPU_PIX_FMT_VYUY:
++ return 6;
++ case IPU_PIX_FMT_UYVY:
++ return 8;
++ case IPU_PIX_FMT_YUYV:
++ return 10;
++ case IPU_PIX_FMT_YVYU:
++ return 12;
++ case IPU_PIX_FMT_GBR24:
++ case IPU_PIX_FMT_VYU444:
++ return 13;
++ case IPU_PIX_FMT_BGR24:
++ return 14;
++ }
++
++ return -1;
++}
++
++/*!
++ * This function sets the colorspace for of dp.
++ * modes.
++ *
++ * @param ipu ipu handler
++ * @param channel Input parameter for the logical channel ID.
++ *
++ * @param param If it's not NULL, update the csc table
++ * with this parameter.
++ *
++ * @return N/A
++ */
++void _ipu_dp_set_csc_coefficients(struct ipu_soc *ipu, ipu_channel_t channel, int32_t param[][3])
++{
++ int dp;
++ struct dp_csc_param_t dp_csc_param;
++
++ if (channel == MEM_FG_SYNC)
++ dp = DP_SYNC;
++ else if (channel == MEM_BG_SYNC)
++ dp = DP_SYNC;
++ else if (channel == MEM_BG_ASYNC0)
++ dp = DP_ASYNC0;
++ else
++ return;
++
++ dp_csc_param.mode = -1;
++ dp_csc_param.coeff = param;
++ __ipu_dp_csc_setup(ipu, dp, dp_csc_param, true);
++}
++
++void ipu_set_csc_coefficients(struct ipu_soc *ipu, ipu_channel_t channel, int32_t param[][3])
++{
++ _ipu_dp_set_csc_coefficients(ipu, channel, param);
++}
++EXPORT_SYMBOL(ipu_set_csc_coefficients);
++
++/*!
++ * This function is called to adapt synchronous LCD panel to IPU restriction.
++ *
++ */
++void adapt_panel_to_ipu_restricitions(struct ipu_soc *ipu, uint16_t *v_start_width,
++ uint16_t *v_sync_width,
++ uint16_t *v_end_width)
++{
++ if (*v_end_width < 2) {
++ uint16_t diff = 2 - *v_end_width;
++ if (*v_start_width >= diff) {
++ *v_end_width = 2;
++ *v_start_width = *v_start_width - diff;
++ } else if (*v_sync_width > diff) {
++ *v_end_width = 2;
++ *v_sync_width = *v_sync_width - diff;
++ } else
++ dev_err(ipu->dev, "WARNING: try to adapt timming, but failed\n");
++ dev_err(ipu->dev, "WARNING: adapt panel end blank lines\n");
++ }
++}
++
++/*!
++ * This function is called to initialize a synchronous LCD panel.
++ *
++ * @param ipu ipu handler
++ * @param disp The DI the panel is attached to.
++ *
++ * @param pixel_clk Desired pixel clock frequency in Hz.
++ *
++ * @param pixel_fmt Input parameter for pixel format of buffer.
++ * Pixel format is a FOURCC ASCII code.
++ *
++ * @param width The width of panel in pixels.
++ *
++ * @param height The height of panel in pixels.
++ *
++ * @param hStartWidth The number of pixel clocks between the HSYNC
++ * signal pulse and the start of valid data.
++ *
++ * @param hSyncWidth The width of the HSYNC signal in units of pixel
++ * clocks.
++ *
++ * @param hEndWidth The number of pixel clocks between the end of
++ * valid data and the HSYNC signal for next line.
++ *
++ * @param vStartWidth The number of lines between the VSYNC
++ * signal pulse and the start of valid data.
++ *
++ * @param vSyncWidth The width of the VSYNC signal in units of lines
++ *
++ * @param vEndWidth The number of lines between the end of valid
++ * data and the VSYNC signal for next frame.
++ *
++ * @param sig Bitfield of signal polarities for LCD interface.
++ *
++ * @return This function returns 0 on success or negative error code on
++ * fail.
++ */
++int32_t ipu_init_sync_panel(struct ipu_soc *ipu, int disp, uint32_t pixel_clk,
++ uint16_t width, uint16_t height,
++ uint32_t pixel_fmt,
++ uint16_t h_start_width, uint16_t h_sync_width,
++ uint16_t h_end_width, uint16_t v_start_width,
++ uint16_t v_sync_width, uint16_t v_end_width,
++ uint32_t v_to_h_sync, ipu_di_signal_cfg_t sig)
++{
++ uint32_t field0_offset = 0;
++ uint32_t field1_offset;
++ uint32_t reg;
++ uint32_t di_gen, vsync_cnt;
++ uint32_t div, rounded_pixel_clk;
++ uint32_t h_total, v_total;
++ int map;
++ int ret;
++ struct clk *ldb_di0_clk, *ldb_di1_clk;
++ struct clk *di_parent;
++
++ dev_dbg(ipu->dev, "panel size = %d x %d\n", width, height);
++
++ if ((v_sync_width == 0) || (h_sync_width == 0))
++ return -EINVAL;
++
++ adapt_panel_to_ipu_restricitions(ipu, &v_start_width, &v_sync_width, &v_end_width);
++ h_total = width + h_sync_width + h_start_width + h_end_width;
++ v_total = height + v_sync_width + v_start_width + v_end_width;
++
++ /* Init clocking */
++ dev_dbg(ipu->dev, "pixel clk = %d\n", pixel_clk);
++
++ di_parent = clk_get_parent(ipu->di_clk_sel[disp]);
++ if (!di_parent) {
++ dev_err(ipu->dev, "get di clk parent fail\n");
++ return -EINVAL;
++ }
++ ldb_di0_clk = clk_get(ipu->dev, "ldb_di0");
++ if (IS_ERR(ldb_di0_clk)) {
++ dev_err(ipu->dev, "clk_get di0 failed");
++ return PTR_ERR(ldb_di0_clk);
++ }
++ ldb_di1_clk = clk_get(ipu->dev, "ldb_di1");
++ if (IS_ERR(ldb_di1_clk)) {
++ dev_err(ipu->dev, "clk_get di1 failed");
++ return PTR_ERR(ldb_di1_clk);
++ }
++
++ if (ldb_di0_clk == di_parent || ldb_di1_clk == di_parent) {
++ /* if di clk parent is tve/ldb, then keep it;*/
++ dev_dbg(ipu->dev, "use special clk parent\n");
++ ret = clk_set_parent(ipu->pixel_clk_sel[disp], ipu->di_clk[disp]);
++ if (ret) {
++ dev_err(ipu->dev, "set pixel clk error:%d\n", ret);
++ return ret;
++ }
++ clk_put(ldb_di0_clk);
++ clk_put(ldb_di1_clk);
++ } else {
++ /* try ipu clk first*/
++ dev_dbg(ipu->dev, "try ipu internal clk\n");
++ ret = clk_set_parent(ipu->pixel_clk_sel[disp], ipu->ipu_clk);
++ if (ret) {
++ dev_err(ipu->dev, "set pixel clk error:%d\n", ret);
++ return ret;
++ }
++ rounded_pixel_clk = clk_round_rate(ipu->pixel_clk[disp], pixel_clk);
++ dev_dbg(ipu->dev, "rounded pix clk:%d\n", rounded_pixel_clk);
++ /*
++ * we will only use 1/2 fraction for ipu clk,
++ * so if the clk rate is not fit, try ext clk.
++ */
++ if (!sig.int_clk &&
++ ((rounded_pixel_clk >= pixel_clk + pixel_clk/200) ||
++ (rounded_pixel_clk <= pixel_clk - pixel_clk/200))) {
++ dev_dbg(ipu->dev, "try ipu ext di clk\n");
++
++ rounded_pixel_clk =
++ clk_round_rate(ipu->di_clk[disp], pixel_clk);
++ ret = clk_set_rate(ipu->di_clk[disp],
++ rounded_pixel_clk);
++ if (ret) {
++ dev_err(ipu->dev,
++ "set di clk rate error:%d\n", ret);
++ return ret;
++ }
++ dev_dbg(ipu->dev, "di clk:%d\n", rounded_pixel_clk);
++ ret = clk_set_parent(ipu->pixel_clk_sel[disp],
++ ipu->di_clk[disp]);
++ if (ret) {
++ dev_err(ipu->dev,
++ "set pixel clk parent error:%d\n", ret);
++ return ret;
++ }
++ }
++ }
++ rounded_pixel_clk = clk_round_rate(ipu->pixel_clk[disp], pixel_clk);
++ dev_dbg(ipu->dev, "round pixel clk:%d\n", rounded_pixel_clk);
++ ret = clk_set_rate(ipu->pixel_clk[disp], rounded_pixel_clk);
++ if (ret) {
++ dev_err(ipu->dev, "set pixel clk rate error:%d\n", ret);
++ return ret;
++ }
++ msleep(5);
++ /* Get integer portion of divider */
++ div = clk_get_rate(clk_get_parent(ipu->pixel_clk_sel[disp])) / rounded_pixel_clk;
++ dev_dbg(ipu->dev, "div:%d\n", div);
++ if (!div) {
++ dev_err(ipu->dev, "invalid pixel clk div = 0\n");
++ return -EINVAL;
++ }
++
++
++ mutex_lock(&ipu->mutex_lock);
++
++ _ipu_di_data_wave_config(ipu, disp, SYNC_WAVE, div - 1, div - 1);
++ _ipu_di_data_pin_config(ipu, disp, SYNC_WAVE, DI_PIN15, 3, 0, div * 2);
++
++ map = _ipu_pixfmt_to_map(pixel_fmt);
++ if (map < 0) {
++ dev_dbg(ipu->dev, "IPU_DISP: No MAP\n");
++ mutex_unlock(&ipu->mutex_lock);
++ return -EINVAL;
++ }
++
++ /*clear DI*/
++ di_gen = ipu_di_read(ipu, disp, DI_GENERAL);
++ di_gen &= (0x3 << 20);
++ ipu_di_write(ipu, disp, di_gen, DI_GENERAL);
++
++ if (sig.interlaced) {
++ if (g_ipu_hw_rev >= IPU_V3DEX) {
++ /* Internal VSYNC for each frame */
++ _ipu_di_sync_config(ipu,
++ disp, /* display */
++ DI_SYNC_COUNT_1, /* counter */
++ v_total*2 - 1, /* run count */
++ (3 - 1), /* run_resolution, counter 1 can reference to counter 6,7,8 with run_resolution=2,3,4 */
++ 1, /* offset */
++ (3 - 1), /* offset resolution, 3=counter 7 */
++ 0, /* repeat count */
++ DI_SYNC_NONE, /* CNT_CLR_SEL */
++ 0, /* CNT_POLARITY_GEN_EN */
++ DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
++ DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */
++ 0, /* COUNT UP */
++ 0 /* COUNT DOWN */
++ );
++
++ /* HSYNC waveform on DI_PIN02 */
++ _ipu_di_sync_config(ipu,
++ disp, /* display */
++ DI_SYNC_HSYNC, /* counter */
++ h_total - 1, /* run count */
++ DI_SYNC_CLK, /* run_resolution, counter 2 can reference to counter 5,7 with run_resolution=3,4 */
++ 0, /* offset */
++ DI_SYNC_NONE, /* offset resolution */
++ 0, /* repeat count */
++ DI_SYNC_NONE, /* CNT_CLR_SEL */
++ 1, /* CNT_POLARITY_GEN_EN */
++ DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
++ DI_SYNC_CLK, /* CNT_POLARITY_TRIGGER_SEL */
++ 0, /* COUNT UP */
++ 2*h_sync_width /* COUNT DOWN */
++ );
++
++ /* VSYNC waveform on DI_PIN03 */
++ vsync_cnt = DI_SYNC_VSYNC;
++ _ipu_di_sync_config(ipu,
++ disp, /* display */
++ DI_SYNC_VSYNC, /* counter */
++ v_total - 1, /* run count */
++ (4 - 1), /* run_resolution, counter 3 can reference to counter 7 with run_resolution=4 */
++ 1, /* offset */
++ (4 - 1), /* offset resolution, 4=counter 7 */
++ 2, /* repeat count */
++ DI_SYNC_COUNT_1, /* CNT_CLR_SEL */
++ 1, /* CNT_POLARITY_GEN_EN */
++ DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
++ (4 - 1), /* CNT_POLARITY_TRIGGER_SEL, 4=counter 7 */
++ 0, /* COUNT UP */
++ 2*v_sync_width /* COUNT DOWN */
++ );
++
++ /* Active Field */
++ _ipu_di_sync_config(ipu,
++ disp, /* display */
++ DI_SYNC_AFIELD, /* counter */
++ (v_total/2 + 1) - 1, /* run count */
++ DI_SYNC_HSYNC, /* run_resolution */
++ h_total/2, /* offset */
++ DI_SYNC_CLK, /* offset resolution */
++ 2, /* repeat count */
++ DI_SYNC_COUNT_1, /* CNT_CLR_SEL */
++ 0, /* CNT_POLARITY_GEN_EN */
++ DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
++ DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */
++ 0, /* COUNT UP */
++ 0 /* COUNT DOWN */
++ );
++
++ /* Active Line */
++ _ipu_di_sync_config(ipu,
++ disp, /* display */
++ DI_SYNC_ALINE, /* counter */
++ 0, /* run count */
++ DI_SYNC_HSYNC, /* run_resolution */
++ (v_start_width + v_sync_width) / 2, /* offset */
++ DI_SYNC_HSYNC, /* offset resolution */
++ height/2, /* repeat count */
++ DI_SYNC_AFIELD, /* CNT_CLR_SEL */
++ 0, /* CNT_POLARITY_GEN_EN */
++ DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
++ DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */
++ 0, /* COUNT UP */
++ 0 /* COUNT DOWN */
++ );
++
++ /* Active Pixel */
++ _ipu_di_sync_config(ipu,
++ disp, /* display */
++ DI_SYNC_APIXEL, /* counter */
++ 0, /* run count */
++ DI_SYNC_CLK, /* run_resolution */
++ h_start_width + h_sync_width, /* offset */
++ DI_SYNC_CLK, /* offset resolution */
++ width, /* repeat count */
++ DI_SYNC_ALINE, /* CNT_CLR_SEL */
++ 0, /* CNT_POLARITY_GEN_EN */
++ DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
++ DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */
++ 0, /* COUNT UP */
++ 0 /* COUNT DOWN */
++ );
++
++ /* Half line HSYNC */
++ _ipu_di_sync_config(ipu,
++ disp, /* display */
++ DI_SYNC_COUNT_7, /* counter */
++ h_total/2 - 1, /* run count */
++ DI_SYNC_CLK, /* run_resolution */
++ 0, /* offset */
++ DI_SYNC_NONE, /* offset resolution */
++ 0, /* repeat count */
++ DI_SYNC_NONE, /* CNT_CLR_SEL */
++ 0, /* CNT_POLARITY_GEN_EN */
++ DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
++ DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */
++ 0, /* COUNT UP */
++ 0 /* COUNT DOWN */
++ );
++
++ ipu_di_write(ipu, disp, v_total / 2 - 1, DI_SCR_CONF);
++
++ /* set y_sel = 1 */
++ di_gen |= ((DI_SYNC_HSYNC-1)<<28);
++ } else {
++ /* Internal HSYNC waveform */
++ _ipu_di_sync_config(ipu, disp, DI_SYNC_INT_HSYNC, h_total - 1, DI_SYNC_CLK,
++ 0, DI_SYNC_NONE, 0, DI_SYNC_NONE, 0, DI_SYNC_NONE,
++ DI_SYNC_NONE, 0, 0);
++
++ field1_offset = v_sync_width + v_start_width + height / 2 +
++ v_end_width;
++ if (sig.odd_field_first) {
++ field0_offset = field1_offset - 1;
++ field1_offset = 0;
++ }
++ v_total += v_start_width + v_end_width;
++
++ /* HSYNC waveform */
++ _ipu_di_sync_config(ipu, disp, DI_SYNC_HSYNC, h_total - 1, DI_SYNC_CLK,
++ 0, DI_SYNC_NONE, 0, DI_SYNC_NONE, 0,
++ DI_SYNC_NONE, DI_SYNC_NONE, 0, 4);
++
++ /* Field 1 VSYNC waveform */
++ _ipu_di_sync_config(ipu, disp, DI_SYNC_VSYNC, v_total - 1, DI_SYNC_INT_HSYNC,
++ field0_offset,
++ field0_offset ? DI_SYNC_INT_HSYNC : DI_SYNC_NONE,
++ 0, DI_SYNC_NONE, 0,
++ DI_SYNC_NONE, DI_SYNC_NONE, 0, 4);
++
++ /* Active Field */
++ _ipu_di_sync_config(ipu, disp, DI_SYNC_AFIELD,
++ field0_offset ?
++ field0_offset : field1_offset - 2,
++ DI_SYNC_INT_HSYNC, v_start_width + v_sync_width, DI_SYNC_INT_HSYNC,
++ 2, DI_SYNC_VSYNC, 0, DI_SYNC_NONE, DI_SYNC_NONE, 0, 0);
++
++ /* Active Line */
++ _ipu_di_sync_config(ipu, disp, DI_SYNC_ALINE, 0, DI_SYNC_INT_HSYNC,
++ 0, DI_SYNC_NONE,
++ height / 2, DI_SYNC_AFIELD, 0, DI_SYNC_NONE,
++ DI_SYNC_NONE, 0, 0);
++
++ /* Active Pixel */
++ _ipu_di_sync_config(ipu, disp, DI_SYNC_APIXEL, 0, DI_SYNC_CLK,
++ h_sync_width + h_start_width, DI_SYNC_CLK,
++ width, DI_SYNC_ALINE, 0, DI_SYNC_NONE, DI_SYNC_NONE,
++ 0, 0);
++
++ /* DC VSYNC waveform */
++ vsync_cnt = DI_SYNC_COUNT_7;
++ _ipu_di_sync_config(ipu, disp, DI_SYNC_COUNT_7, 0, DI_SYNC_INT_HSYNC,
++ field1_offset,
++ field1_offset ? DI_SYNC_INT_HSYNC : DI_SYNC_NONE,
++ 1, DI_SYNC_VSYNC, 0, DI_SYNC_NONE, DI_SYNC_NONE, 0, 0);
++
++ /* Field 0 VSYNC waveform */
++ _ipu_di_sync_config(ipu, disp, DI_SYNC_COUNT_8, v_total - 1, DI_SYNC_INT_HSYNC,
++ 0, DI_SYNC_NONE,
++ 0, DI_SYNC_NONE, 0, DI_SYNC_NONE,
++ DI_SYNC_NONE, 0, 0);
++
++ /* ??? */
++ _ipu_di_sync_config(ipu, disp, DI_SYNC_COUNT_9, v_total - 1, (DI_SYNC_HSYNC - 1),
++ 0, DI_SYNC_NONE,
++ 0, DI_SYNC_NONE, 6, DI_SYNC_NONE,
++ DI_SYNC_NONE, 0, 0);
++
++ reg = ipu_di_read(ipu, disp, DI_SW_GEN1(9));
++ reg |= 0x8000;
++ ipu_di_write(ipu, disp, reg, DI_SW_GEN1(9));
++
++ ipu_di_write(ipu, disp, v_sync_width + v_start_width +
++ v_end_width + height / 2 - 1, DI_SCR_CONF);
++ }
++
++ /* Init template microcode */
++ if (disp) {
++ _ipu_dc_write_tmpl(ipu, 1, WROD(0), 0, map, SYNC_WAVE, 0, DI_SYNC_APIXEL, 1);
++ if ((pixel_fmt == IPU_PIX_FMT_YUYV) ||
++ (pixel_fmt == IPU_PIX_FMT_UYVY) ||
++ (pixel_fmt == IPU_PIX_FMT_YVYU) ||
++ (pixel_fmt == IPU_PIX_FMT_VYUY)) {
++ _ipu_dc_write_tmpl(ipu, 8, WROD(0), 0, (map - 1), SYNC_WAVE, 0, DI_SYNC_APIXEL, 1);
++ _ipu_dc_write_tmpl(ipu, 9, WROD(0), 0, map, SYNC_WAVE, 0, DI_SYNC_APIXEL, 1);
++ /* configure user events according to DISP NUM */
++ ipu_dc_write(ipu, (width - 1), DC_UGDE_3(disp));
++ }
++ } else {
++ _ipu_dc_write_tmpl(ipu, 0, WROD(0), 0, map, SYNC_WAVE, 0, DI_SYNC_APIXEL, 1);
++ if ((pixel_fmt == IPU_PIX_FMT_YUYV) ||
++ (pixel_fmt == IPU_PIX_FMT_UYVY) ||
++ (pixel_fmt == IPU_PIX_FMT_YVYU) ||
++ (pixel_fmt == IPU_PIX_FMT_VYUY)) {
++ _ipu_dc_write_tmpl(ipu, 10, WROD(0), 0, (map - 1), SYNC_WAVE, 0, DI_SYNC_APIXEL, 1);
++ _ipu_dc_write_tmpl(ipu, 11, WROD(0), 0, map, SYNC_WAVE, 0, DI_SYNC_APIXEL, 1);
++ /* configure user events according to DISP NUM */
++ ipu_dc_write(ipu, width - 1, DC_UGDE_3(disp));
++ }
++ }
++
++ if (sig.Hsync_pol)
++ di_gen |= DI_GEN_POLARITY_2;
++ if (sig.Vsync_pol)
++ di_gen |= DI_GEN_POLARITY_3;
++ } else {
++ /* Setup internal HSYNC waveform */
++ _ipu_di_sync_config(ipu, disp, DI_SYNC_INT_HSYNC, h_total - 1, DI_SYNC_CLK,
++ 0, DI_SYNC_NONE, 0, DI_SYNC_NONE, 0, DI_SYNC_NONE,
++ DI_SYNC_NONE, 0, 0);
++
++ /* Setup external (delayed) HSYNC waveform */
++ _ipu_di_sync_config(ipu, disp, DI_SYNC_HSYNC, h_total - 1,
++ DI_SYNC_CLK, div * v_to_h_sync, DI_SYNC_CLK,
++ 0, DI_SYNC_NONE, 1, DI_SYNC_NONE,
++ DI_SYNC_CLK, 0, h_sync_width * 2);
++ /* Setup VSYNC waveform */
++ vsync_cnt = DI_SYNC_VSYNC;
++ _ipu_di_sync_config(ipu, disp, DI_SYNC_VSYNC, v_total - 1,
++ DI_SYNC_INT_HSYNC, 0, DI_SYNC_NONE, 0,
++ DI_SYNC_NONE, 1, DI_SYNC_NONE,
++ DI_SYNC_INT_HSYNC, 0, v_sync_width * 2);
++ ipu_di_write(ipu, disp, v_total - 1, DI_SCR_CONF);
++
++ /* Setup active data waveform to sync with DC */
++ _ipu_di_sync_config(ipu, disp, DI_SYNC_ALINE, 0, DI_SYNC_HSYNC,
++ v_sync_width + v_start_width, DI_SYNC_HSYNC, height,
++ DI_SYNC_VSYNC, 0, DI_SYNC_NONE,
++ DI_SYNC_NONE, 0, 0);
++ _ipu_di_sync_config(ipu, disp, DI_SYNC_APIXEL, 0, DI_SYNC_CLK,
++ h_sync_width + h_start_width, DI_SYNC_CLK,
++ width, DI_SYNC_ALINE, 0, DI_SYNC_NONE, DI_SYNC_NONE, 0,
++ 0);
++
++ /* set VGA delayed hsync/vsync no matter VGA enabled */
++ if (disp) {
++ /* couter 7 for VGA delay HSYNC */
++ _ipu_di_sync_config(ipu, disp, DI_SYNC_COUNT_7,
++ h_total - 1, DI_SYNC_CLK,
++ 18, DI_SYNC_CLK,
++ 0, DI_SYNC_NONE,
++ 1, DI_SYNC_NONE, DI_SYNC_CLK,
++ 0, h_sync_width * 2);
++
++ /* couter 8 for VGA delay VSYNC */
++ _ipu_di_sync_config(ipu, disp, DI_SYNC_COUNT_8,
++ v_total - 1, DI_SYNC_INT_HSYNC,
++ 1, DI_SYNC_INT_HSYNC,
++ 0, DI_SYNC_NONE,
++ 1, DI_SYNC_NONE, DI_SYNC_INT_HSYNC,
++ 0, v_sync_width * 2);
++ }
++
++ /* reset all unused counters */
++ if (!disp) {
++ ipu_di_write(ipu, disp, 0, DI_SW_GEN0(7));
++ ipu_di_write(ipu, disp, 0, DI_SW_GEN1(7));
++ ipu_di_write(ipu, disp, 0, DI_STP_REP(7));
++ ipu_di_write(ipu, disp, 0, DI_SW_GEN0(8));
++ ipu_di_write(ipu, disp, 0, DI_SW_GEN1(8));
++ ipu_di_write(ipu, disp, 0, DI_STP_REP(8));
++ }
++ ipu_di_write(ipu, disp, 0, DI_SW_GEN0(9));
++ ipu_di_write(ipu, disp, 0, DI_SW_GEN1(9));
++ ipu_di_write(ipu, disp, 0, DI_STP_REP(9));
++
++ /* Init template microcode */
++ if (disp) {
++ if ((pixel_fmt == IPU_PIX_FMT_YUYV) ||
++ (pixel_fmt == IPU_PIX_FMT_UYVY) ||
++ (pixel_fmt == IPU_PIX_FMT_YVYU) ||
++ (pixel_fmt == IPU_PIX_FMT_VYUY)) {
++ _ipu_dc_write_tmpl(ipu, 8, WROD(0), 0, (map - 1), SYNC_WAVE, 0, DI_SYNC_APIXEL, 1);
++ _ipu_dc_write_tmpl(ipu, 9, WROD(0), 0, map, SYNC_WAVE, 0, DI_SYNC_APIXEL, 1);
++ /* configure user events according to DISP NUM */
++ ipu_dc_write(ipu, (width - 1), DC_UGDE_3(disp));
++ }
++ _ipu_dc_write_tmpl(ipu, 2, WROD(0), 0, map, SYNC_WAVE, 8, DI_SYNC_APIXEL, 1);
++ _ipu_dc_write_tmpl(ipu, 3, WROD(0), 0, map, SYNC_WAVE, 4, DI_SYNC_APIXEL, 0);
++ _ipu_dc_write_tmpl(ipu, 4, WRG, 0, map, NULL_WAVE, 0, DI_SYNC_CLK, 1);
++ _ipu_dc_write_tmpl(ipu, 1, WROD(0), 0, map, SYNC_WAVE, 0, DI_SYNC_APIXEL, 1);
++
++ } else {
++ if ((pixel_fmt == IPU_PIX_FMT_YUYV) ||
++ (pixel_fmt == IPU_PIX_FMT_UYVY) ||
++ (pixel_fmt == IPU_PIX_FMT_YVYU) ||
++ (pixel_fmt == IPU_PIX_FMT_VYUY)) {
++ _ipu_dc_write_tmpl(ipu, 10, WROD(0), 0, (map - 1), SYNC_WAVE, 0, DI_SYNC_APIXEL, 1);
++ _ipu_dc_write_tmpl(ipu, 11, WROD(0), 0, map, SYNC_WAVE, 0, DI_SYNC_APIXEL, 1);
++ /* configure user events according to DISP NUM */
++ ipu_dc_write(ipu, width - 1, DC_UGDE_3(disp));
++ }
++ _ipu_dc_write_tmpl(ipu, 5, WROD(0), 0, map, SYNC_WAVE, 8, DI_SYNC_APIXEL, 1);
++ _ipu_dc_write_tmpl(ipu, 6, WROD(0), 0, map, SYNC_WAVE, 4, DI_SYNC_APIXEL, 0);
++ _ipu_dc_write_tmpl(ipu, 7, WRG, 0, map, NULL_WAVE, 0, DI_SYNC_CLK, 1);
++ _ipu_dc_write_tmpl(ipu, 12, WROD(0), 0, map, SYNC_WAVE, 0, DI_SYNC_APIXEL, 1);
++ }
++
++ if (sig.Hsync_pol) {
++ di_gen |= DI_GEN_POLARITY_2;
++ if (disp)
++ di_gen |= DI_GEN_POLARITY_7;
++ }
++ if (sig.Vsync_pol) {
++ di_gen |= DI_GEN_POLARITY_3;
++ if (disp)
++ di_gen |= DI_GEN_POLARITY_8;
++ }
++ }
++ /* changinc DISP_CLK polarity: it can be wrong for some applications */
++ if ((pixel_fmt == IPU_PIX_FMT_YUYV) ||
++ (pixel_fmt == IPU_PIX_FMT_UYVY) ||
++ (pixel_fmt == IPU_PIX_FMT_YVYU) ||
++ (pixel_fmt == IPU_PIX_FMT_VYUY))
++ di_gen |= 0x00020000;
++
++ if (!sig.clk_pol)
++ di_gen |= DI_GEN_POLARITY_DISP_CLK;
++
++ ipu_di_write(ipu, disp, di_gen, DI_GENERAL);
++
++ ipu_di_write(ipu, disp, (--vsync_cnt << DI_VSYNC_SEL_OFFSET) |
++ 0x00000002, DI_SYNC_AS_GEN);
++ reg = ipu_di_read(ipu, disp, DI_POL);
++ reg &= ~(DI_POL_DRDY_DATA_POLARITY | DI_POL_DRDY_POLARITY_15);
++ if (sig.enable_pol)
++ reg |= DI_POL_DRDY_POLARITY_15;
++ if (sig.data_pol)
++ reg |= DI_POL_DRDY_DATA_POLARITY;
++ ipu_di_write(ipu, disp, reg, DI_POL);
++
++ ipu_dc_write(ipu, width, DC_DISP_CONF2(DC_DISP_ID_SYNC(disp)));
++
++ mutex_unlock(&ipu->mutex_lock);
++
++ return 0;
++}
++EXPORT_SYMBOL(ipu_init_sync_panel);
++
++void ipu_uninit_sync_panel(struct ipu_soc *ipu, int disp)
++{
++ uint32_t reg;
++ uint32_t di_gen;
++
++ if ((disp != 0) || (disp != 1))
++ return;
++
++ mutex_lock(&ipu->mutex_lock);
++
++ di_gen = ipu_di_read(ipu, disp, DI_GENERAL);
++ di_gen |= 0x3ff | DI_GEN_POLARITY_DISP_CLK;
++ ipu_di_write(ipu, disp, di_gen, DI_GENERAL);
++
++ reg = ipu_di_read(ipu, disp, DI_POL);
++ reg |= 0x3ffffff;
++ ipu_di_write(ipu, disp, reg, DI_POL);
++
++ mutex_unlock(&ipu->mutex_lock);
++}
++EXPORT_SYMBOL(ipu_uninit_sync_panel);
++
++int ipu_init_async_panel(struct ipu_soc *ipu, int disp, int type, uint32_t cycle_time,
++ uint32_t pixel_fmt, ipu_adc_sig_cfg_t sig)
++{
++ int map;
++ u32 ser_conf = 0;
++ u32 div;
++ u32 di_clk = clk_get_rate(ipu->ipu_clk);
++
++ /* round up cycle_time, then calcalate the divider using scaled math */
++ cycle_time += (1000000000UL / di_clk) - 1;
++ div = (cycle_time * (di_clk / 256UL)) / (1000000000UL / 256UL);
++
++ map = _ipu_pixfmt_to_map(pixel_fmt);
++ if (map < 0)
++ return -EINVAL;
++
++ mutex_lock(&ipu->mutex_lock);
++
++ if (type == IPU_PANEL_SERIAL) {
++ ipu_di_write(ipu, disp, (div << 24) | ((sig.ifc_width - 1) << 4),
++ DI_DW_GEN(ASYNC_SER_WAVE));
++
++ _ipu_di_data_pin_config(ipu, disp, ASYNC_SER_WAVE, DI_PIN_CS,
++ 0, 0, (div * 2) + 1);
++ _ipu_di_data_pin_config(ipu, disp, ASYNC_SER_WAVE, DI_PIN_SER_CLK,
++ 1, div, div * 2);
++ _ipu_di_data_pin_config(ipu, disp, ASYNC_SER_WAVE, DI_PIN_SER_RS,
++ 2, 0, 0);
++
++ _ipu_dc_write_tmpl(ipu, 0x64, WROD(0), 0, map, ASYNC_SER_WAVE, 0, 0, 1);
++
++ /* Configure DC for serial panel */
++ ipu_dc_write(ipu, 0x14, DC_DISP_CONF1(DC_DISP_ID_SERIAL));
++
++ if (sig.clk_pol)
++ ser_conf |= DI_SER_CONF_SERIAL_CLK_POL;
++ if (sig.data_pol)
++ ser_conf |= DI_SER_CONF_SERIAL_DATA_POL;
++ if (sig.rs_pol)
++ ser_conf |= DI_SER_CONF_SERIAL_RS_POL;
++ if (sig.cs_pol)
++ ser_conf |= DI_SER_CONF_SERIAL_CS_POL;
++ ipu_di_write(ipu, disp, ser_conf, DI_SER_CONF);
++ }
++
++ mutex_unlock(&ipu->mutex_lock);
++ return 0;
++}
++EXPORT_SYMBOL(ipu_init_async_panel);
++
++/*!
++ * This function sets the foreground and background plane global alpha blending
++ * modes. This function also sets the DP graphic plane according to the
++ * parameter of IPUv3 DP channel.
++ *
++ * @param ipu ipu handler
++ * @param channel IPUv3 DP channel
++ *
++ * @param enable Boolean to enable or disable global alpha
++ * blending. If disabled, local blending is used.
++ *
++ * @param alpha Global alpha value.
++ *
++ * @return Returns 0 on success or negative error code on fail
++ */
++int32_t ipu_disp_set_global_alpha(struct ipu_soc *ipu, ipu_channel_t channel,
++ bool enable, uint8_t alpha)
++{
++ uint32_t reg;
++ uint32_t flow;
++ bool bg_chan;
++
++ if (channel == MEM_BG_SYNC || channel == MEM_FG_SYNC)
++ flow = DP_SYNC;
++ else if (channel == MEM_BG_ASYNC0 || channel == MEM_FG_ASYNC0)
++ flow = DP_ASYNC0;
++ else if (channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1)
++ flow = DP_ASYNC1;
++ else
++ return -EINVAL;
++
++ if (channel == MEM_BG_SYNC || channel == MEM_BG_ASYNC0 ||
++ channel == MEM_BG_ASYNC1)
++ bg_chan = true;
++ else
++ bg_chan = false;
++
++ _ipu_get(ipu);
++
++ mutex_lock(&ipu->mutex_lock);
++
++ if (bg_chan) {
++ reg = ipu_dp_read(ipu, DP_COM_CONF(flow));
++ ipu_dp_write(ipu, reg & ~DP_COM_CONF_GWSEL, DP_COM_CONF(flow));
++ } else {
++ reg = ipu_dp_read(ipu, DP_COM_CONF(flow));
++ ipu_dp_write(ipu, reg | DP_COM_CONF_GWSEL, DP_COM_CONF(flow));
++ }
++
++ if (enable) {
++ reg = ipu_dp_read(ipu, DP_GRAPH_WIND_CTRL(flow)) & 0x00FFFFFFL;
++ ipu_dp_write(ipu, reg | ((uint32_t) alpha << 24),
++ DP_GRAPH_WIND_CTRL(flow));
++
++ reg = ipu_dp_read(ipu, DP_COM_CONF(flow));
++ ipu_dp_write(ipu, reg | DP_COM_CONF_GWAM, DP_COM_CONF(flow));
++ } else {
++ reg = ipu_dp_read(ipu, DP_COM_CONF(flow));
++ ipu_dp_write(ipu, reg & ~DP_COM_CONF_GWAM, DP_COM_CONF(flow));
++ }
++
++ reg = ipu_cm_read(ipu, IPU_SRM_PRI2) | 0x8;
++ ipu_cm_write(ipu, reg, IPU_SRM_PRI2);
++
++ mutex_unlock(&ipu->mutex_lock);
++
++ _ipu_put(ipu);
++
++ return 0;
++}
++EXPORT_SYMBOL(ipu_disp_set_global_alpha);
++
++/*!
++ * This function sets the transparent color key for SDC graphic plane.
++ *
++ * @param ipu ipu handler
++ * @param channel Input parameter for the logical channel ID.
++ *
++ * @param enable Boolean to enable or disable color key
++ *
++ * @param colorKey 24-bit RGB color for transparent color key.
++ *
++ * @return Returns 0 on success or negative error code on fail
++ */
++int32_t ipu_disp_set_color_key(struct ipu_soc *ipu, ipu_channel_t channel,
++ bool enable, uint32_t color_key)
++{
++ uint32_t reg, flow;
++ int y, u, v;
++ int red, green, blue;
++
++ if (channel == MEM_BG_SYNC || channel == MEM_FG_SYNC)
++ flow = DP_SYNC;
++ else if (channel == MEM_BG_ASYNC0 || channel == MEM_FG_ASYNC0)
++ flow = DP_ASYNC0;
++ else if (channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1)
++ flow = DP_ASYNC1;
++ else
++ return -EINVAL;
++
++ _ipu_get(ipu);
++
++ mutex_lock(&ipu->mutex_lock);
++
++ ipu->color_key_4rgb = true;
++ /* Transform color key from rgb to yuv if CSC is enabled */
++ if (((ipu->fg_csc_type == RGB2YUV) && (ipu->bg_csc_type == YUV2YUV)) ||
++ ((ipu->fg_csc_type == YUV2YUV) && (ipu->bg_csc_type == RGB2YUV)) ||
++ ((ipu->fg_csc_type == YUV2YUV) && (ipu->bg_csc_type == YUV2YUV)) ||
++ ((ipu->fg_csc_type == YUV2RGB) && (ipu->bg_csc_type == YUV2RGB))) {
++
++ dev_dbg(ipu->dev, "color key 0x%x need change to yuv fmt\n", color_key);
++
++ red = (color_key >> 16) & 0xFF;
++ green = (color_key >> 8) & 0xFF;
++ blue = color_key & 0xFF;
++
++ y = _rgb_to_yuv(0, red, green, blue);
++ u = _rgb_to_yuv(1, red, green, blue);
++ v = _rgb_to_yuv(2, red, green, blue);
++ color_key = (y << 16) | (u << 8) | v;
++
++ ipu->color_key_4rgb = false;
++
++ dev_dbg(ipu->dev, "color key change to yuv fmt 0x%x\n", color_key);
++ }
++
++ if (enable) {
++ reg = ipu_dp_read(ipu, DP_GRAPH_WIND_CTRL(flow)) & 0xFF000000L;
++ ipu_dp_write(ipu, reg | color_key, DP_GRAPH_WIND_CTRL(flow));
++
++ reg = ipu_dp_read(ipu, DP_COM_CONF(flow));
++ ipu_dp_write(ipu, reg | DP_COM_CONF_GWCKE, DP_COM_CONF(flow));
++ } else {
++ reg = ipu_dp_read(ipu, DP_COM_CONF(flow));
++ ipu_dp_write(ipu, reg & ~DP_COM_CONF_GWCKE, DP_COM_CONF(flow));
++ }
++
++ reg = ipu_cm_read(ipu, IPU_SRM_PRI2) | 0x8;
++ ipu_cm_write(ipu, reg, IPU_SRM_PRI2);
++
++ mutex_unlock(&ipu->mutex_lock);
++
++ _ipu_put(ipu);
++
++ return 0;
++}
++EXPORT_SYMBOL(ipu_disp_set_color_key);
++
++/*!
++ * This function sets the gamma correction for DP output.
++ *
++ * @param ipu ipu handler
++ * @param channel Input parameter for the logical channel ID.
++ *
++ * @param enable Boolean to enable or disable gamma correction.
++ *
++ * @param constk Gamma piecewise linear approximation constk coeff.
++ *
++ * @param slopek Gamma piecewise linear approximation slopek coeff.
++ *
++ * @return Returns 0 on success or negative error code on fail
++ */
++int32_t ipu_disp_set_gamma_correction(struct ipu_soc *ipu, ipu_channel_t channel, bool enable, int constk[], int slopek[])
++{
++ uint32_t reg, flow, i;
++
++ if (channel == MEM_BG_SYNC || channel == MEM_FG_SYNC)
++ flow = DP_SYNC;
++ else if (channel == MEM_BG_ASYNC0 || channel == MEM_FG_ASYNC0)
++ flow = DP_ASYNC0;
++ else if (channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1)
++ flow = DP_ASYNC1;
++ else
++ return -EINVAL;
++
++ _ipu_get(ipu);
++
++ mutex_lock(&ipu->mutex_lock);
++
++ for (i = 0; i < 8; i++)
++ ipu_dp_write(ipu, (constk[2*i] & 0x1ff) | ((constk[2*i+1] & 0x1ff) << 16), DP_GAMMA_C(flow, i));
++ for (i = 0; i < 4; i++)
++ ipu_dp_write(ipu, (slopek[4*i] & 0xff) | ((slopek[4*i+1] & 0xff) << 8) |
++ ((slopek[4*i+2] & 0xff) << 16) | ((slopek[4*i+3] & 0xff) << 24), DP_GAMMA_S(flow, i));
++
++ reg = ipu_dp_read(ipu, DP_COM_CONF(flow));
++ if (enable) {
++ if ((ipu->bg_csc_type == RGB2YUV) || (ipu->bg_csc_type == YUV2YUV))
++ reg |= DP_COM_CONF_GAMMA_YUV_EN;
++ else
++ reg &= ~DP_COM_CONF_GAMMA_YUV_EN;
++ ipu_dp_write(ipu, reg | DP_COM_CONF_GAMMA_EN, DP_COM_CONF(flow));
++ } else
++ ipu_dp_write(ipu, reg & ~DP_COM_CONF_GAMMA_EN, DP_COM_CONF(flow));
++
++ reg = ipu_cm_read(ipu, IPU_SRM_PRI2) | 0x8;
++ ipu_cm_write(ipu, reg, IPU_SRM_PRI2);
++
++ mutex_unlock(&ipu->mutex_lock);
++
++ _ipu_put(ipu);
++
++ return 0;
++}
++EXPORT_SYMBOL(ipu_disp_set_gamma_correction);
++
++/*!
++ * This function sets the window position of the foreground or background plane.
++ * modes.
++ *
++ * @param ipu ipu handler
++ * @param channel Input parameter for the logical channel ID.
++ *
++ * @param x_pos The X coordinate position to place window at.
++ * The position is relative to the top left corner.
++ *
++ * @param y_pos The Y coordinate position to place window at.
++ * The position is relative to the top left corner.
++ *
++ * @return Returns 0 on success or negative error code on fail
++ */
++int32_t _ipu_disp_set_window_pos(struct ipu_soc *ipu, ipu_channel_t channel,
++ int16_t x_pos, int16_t y_pos)
++{
++ u32 reg;
++ uint32_t flow = 0;
++ uint32_t dp_srm_shift;
++
++ if ((channel == MEM_FG_SYNC) || (channel == MEM_BG_SYNC)) {
++ flow = DP_SYNC;
++ dp_srm_shift = 3;
++ } else if (channel == MEM_FG_ASYNC0) {
++ flow = DP_ASYNC0;
++ dp_srm_shift = 5;
++ } else if (channel == MEM_FG_ASYNC1) {
++ flow = DP_ASYNC1;
++ dp_srm_shift = 7;
++ } else
++ return -EINVAL;
++
++ ipu_dp_write(ipu, (x_pos << 16) | y_pos, DP_FG_POS(flow));
++
++ if (ipu_is_channel_busy(ipu, channel)) {
++ /* controled by FSU if channel enabled */
++ reg = ipu_cm_read(ipu, IPU_SRM_PRI2) & (~(0x3 << dp_srm_shift));
++ reg |= (0x1 << dp_srm_shift);
++ ipu_cm_write(ipu, reg, IPU_SRM_PRI2);
++ } else {
++ /* disable auto swap, controled by MCU if channel disabled */
++ reg = ipu_cm_read(ipu, IPU_SRM_PRI2) & (~(0x3 << dp_srm_shift));
++ ipu_cm_write(ipu, reg, IPU_SRM_PRI2);
++ }
++
++ return 0;
++}
++
++int32_t ipu_disp_set_window_pos(struct ipu_soc *ipu, ipu_channel_t channel,
++ int16_t x_pos, int16_t y_pos)
++{
++ int ret;
++
++ _ipu_get(ipu);
++ mutex_lock(&ipu->mutex_lock);
++ ret = _ipu_disp_set_window_pos(ipu, channel, x_pos, y_pos);
++ mutex_unlock(&ipu->mutex_lock);
++ _ipu_put(ipu);
++ return ret;
++}
++EXPORT_SYMBOL(ipu_disp_set_window_pos);
++
++int32_t _ipu_disp_get_window_pos(struct ipu_soc *ipu, ipu_channel_t channel,
++ int16_t *x_pos, int16_t *y_pos)
++{
++ u32 reg;
++ uint32_t flow = 0;
++
++ if (channel == MEM_FG_SYNC)
++ flow = DP_SYNC;
++ else if (channel == MEM_FG_ASYNC0)
++ flow = DP_ASYNC0;
++ else if (channel == MEM_FG_ASYNC1)
++ flow = DP_ASYNC1;
++ else
++ return -EINVAL;
++
++ reg = ipu_dp_read(ipu, DP_FG_POS(flow));
++
++ *x_pos = (reg >> 16) & 0x7FF;
++ *y_pos = reg & 0x7FF;
++
++ return 0;
++}
++int32_t ipu_disp_get_window_pos(struct ipu_soc *ipu, ipu_channel_t channel,
++ int16_t *x_pos, int16_t *y_pos)
++{
++ int ret;
++
++ _ipu_get(ipu);
++ mutex_lock(&ipu->mutex_lock);
++ ret = _ipu_disp_get_window_pos(ipu, channel, x_pos, y_pos);
++ mutex_unlock(&ipu->mutex_lock);
++ _ipu_put(ipu);
++ return ret;
++}
++EXPORT_SYMBOL(ipu_disp_get_window_pos);
++
++void ipu_disp_direct_write(struct ipu_soc *ipu, ipu_channel_t channel, u32 value, u32 offset)
++{
++ if (channel == DIRECT_ASYNC0)
++ writel(value, ipu->disp_base[0] + offset);
++ else if (channel == DIRECT_ASYNC1)
++ writel(value, ipu->disp_base[1] + offset);
++}
++EXPORT_SYMBOL(ipu_disp_direct_write);
++
++void ipu_reset_disp_panel(struct ipu_soc *ipu)
++{
++ uint32_t tmp;
++
++ tmp = ipu_di_read(ipu, 1, DI_GENERAL);
++ ipu_di_write(ipu, 1, tmp | 0x08, DI_GENERAL);
++ msleep(10); /* tRES >= 100us */
++ tmp = ipu_di_read(ipu, 1, DI_GENERAL);
++ ipu_di_write(ipu, 1, tmp & ~0x08, DI_GENERAL);
++ msleep(60);
++
++ return;
++}
++EXPORT_SYMBOL(ipu_reset_disp_panel);
++
++void ipu_disp_init(struct ipu_soc *ipu)
++{
++ ipu->fg_csc_type = ipu->bg_csc_type = CSC_NONE;
++ ipu->color_key_4rgb = true;
++ _ipu_init_dc_mappings(ipu);
++ _ipu_dmfc_init(ipu, DMFC_NORMAL, 1);
++}
+diff -Nur linux-4.1.3/drivers/mxc/ipu3/ipu_ic.c linux-xbian-imx6/drivers/mxc/ipu3/ipu_ic.c
+--- linux-4.1.3/drivers/mxc/ipu3/ipu_ic.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/ipu3/ipu_ic.c 2015-07-27 23:13:06.226765901 +0200
+@@ -0,0 +1,924 @@
++/*
++ * Copyright 2005-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*
++ * @file ipu_ic.c
++ *
++ * @brief IPU IC functions
++ *
++ * @ingroup IPU
++ */
++#include <linux/errno.h>
++#include <linux/init.h>
++#include <linux/io.h>
++#include <linux/ipu-v3.h>
++#include <linux/spinlock.h>
++#include <linux/types.h>
++#include <linux/videodev2.h>
++
++#include "ipu_param_mem.h"
++#include "ipu_regs.h"
++
++enum {
++ IC_TASK_VIEWFINDER,
++ IC_TASK_ENCODER,
++ IC_TASK_POST_PROCESSOR
++};
++
++static void _init_csc(struct ipu_soc *ipu, uint8_t ic_task, ipu_color_space_t in_format,
++ ipu_color_space_t out_format, int csc_index);
++
++static int _calc_resize_coeffs(struct ipu_soc *ipu,
++ uint32_t inSize, uint32_t outSize,
++ uint32_t *resizeCoeff,
++ uint32_t *downsizeCoeff);
++
++void _ipu_vdi_set_top_field_man(struct ipu_soc *ipu, bool top_field_0)
++{
++ uint32_t reg;
++
++ reg = ipu_vdi_read(ipu, VDI_C);
++ if (top_field_0)
++ reg &= ~VDI_C_TOP_FIELD_MAN_1;
++ else
++ reg |= VDI_C_TOP_FIELD_MAN_1;
++ ipu_vdi_write(ipu, reg, VDI_C);
++}
++
++void _ipu_vdi_set_motion(struct ipu_soc *ipu, ipu_motion_sel motion_sel)
++{
++ uint32_t reg;
++
++ reg = ipu_vdi_read(ipu, VDI_C);
++ reg &= ~(VDI_C_MOT_SEL_FULL | VDI_C_MOT_SEL_MED | VDI_C_MOT_SEL_LOW);
++ if (motion_sel == HIGH_MOTION)
++ reg |= VDI_C_MOT_SEL_FULL;
++ else if (motion_sel == MED_MOTION)
++ reg |= VDI_C_MOT_SEL_MED;
++ else
++ reg |= VDI_C_MOT_SEL_LOW;
++
++ ipu_vdi_write(ipu, reg, VDI_C);
++ dev_dbg(ipu->dev, "VDI_C = \t0x%08X\n", reg);
++}
++
++void ic_dump_register(struct ipu_soc *ipu)
++{
++ printk(KERN_DEBUG "IC_CONF = \t0x%08X\n", ipu_ic_read(ipu, IC_CONF));
++ printk(KERN_DEBUG "IC_PRP_ENC_RSC = \t0x%08X\n",
++ ipu_ic_read(ipu, IC_PRP_ENC_RSC));
++ printk(KERN_DEBUG "IC_PRP_VF_RSC = \t0x%08X\n",
++ ipu_ic_read(ipu, IC_PRP_VF_RSC));
++ printk(KERN_DEBUG "IC_PP_RSC = \t0x%08X\n", ipu_ic_read(ipu, IC_PP_RSC));
++ printk(KERN_DEBUG "IC_IDMAC_1 = \t0x%08X\n", ipu_ic_read(ipu, IC_IDMAC_1));
++ printk(KERN_DEBUG "IC_IDMAC_2 = \t0x%08X\n", ipu_ic_read(ipu, IC_IDMAC_2));
++ printk(KERN_DEBUG "IC_IDMAC_3 = \t0x%08X\n", ipu_ic_read(ipu, IC_IDMAC_3));
++}
++
++void _ipu_ic_enable_task(struct ipu_soc *ipu, ipu_channel_t channel)
++{
++ uint32_t ic_conf;
++
++ ic_conf = ipu_ic_read(ipu, IC_CONF);
++ switch (channel) {
++ case CSI_PRP_VF_MEM:
++ case MEM_PRP_VF_MEM:
++ ic_conf |= IC_CONF_PRPVF_EN;
++ break;
++ case MEM_VDI_PRP_VF_MEM:
++ ic_conf |= IC_CONF_PRPVF_EN;
++ break;
++ case MEM_VDI_MEM:
++ ic_conf |= IC_CONF_PRPVF_EN | IC_CONF_RWS_EN ;
++ break;
++ case MEM_ROT_VF_MEM:
++ ic_conf |= IC_CONF_PRPVF_ROT_EN;
++ break;
++ case CSI_PRP_ENC_MEM:
++ case MEM_PRP_ENC_MEM:
++ ic_conf |= IC_CONF_PRPENC_EN;
++ break;
++ case MEM_ROT_ENC_MEM:
++ ic_conf |= IC_CONF_PRPENC_ROT_EN;
++ break;
++ case MEM_PP_MEM:
++ ic_conf |= IC_CONF_PP_EN;
++ break;
++ case MEM_ROT_PP_MEM:
++ ic_conf |= IC_CONF_PP_ROT_EN;
++ break;
++ default:
++ break;
++ }
++ ipu_ic_write(ipu, ic_conf, IC_CONF);
++}
++
++void _ipu_ic_disable_task(struct ipu_soc *ipu, ipu_channel_t channel)
++{
++ uint32_t ic_conf;
++
++ ic_conf = ipu_ic_read(ipu, IC_CONF);
++ switch (channel) {
++ case CSI_PRP_VF_MEM:
++ case MEM_PRP_VF_MEM:
++ ic_conf &= ~IC_CONF_PRPVF_EN;
++ break;
++ case MEM_VDI_PRP_VF_MEM:
++ ic_conf &= ~IC_CONF_PRPVF_EN;
++ break;
++ case MEM_VDI_MEM:
++ ic_conf &= ~(IC_CONF_PRPVF_EN | IC_CONF_RWS_EN);
++ break;
++ case MEM_ROT_VF_MEM:
++ ic_conf &= ~IC_CONF_PRPVF_ROT_EN;
++ break;
++ case CSI_PRP_ENC_MEM:
++ case MEM_PRP_ENC_MEM:
++ ic_conf &= ~IC_CONF_PRPENC_EN;
++ break;
++ case MEM_ROT_ENC_MEM:
++ ic_conf &= ~IC_CONF_PRPENC_ROT_EN;
++ break;
++ case MEM_PP_MEM:
++ ic_conf &= ~IC_CONF_PP_EN;
++ break;
++ case MEM_ROT_PP_MEM:
++ ic_conf &= ~IC_CONF_PP_ROT_EN;
++ break;
++ default:
++ break;
++ }
++ ipu_ic_write(ipu, ic_conf, IC_CONF);
++}
++
++void _ipu_vdi_init(struct ipu_soc *ipu, ipu_channel_t channel, ipu_channel_params_t *params)
++{
++ uint32_t reg;
++ uint32_t pixel_fmt;
++ uint32_t pix_per_burst;
++
++ reg = ((params->mem_prp_vf_mem.in_height-1) << 16) |
++ (params->mem_prp_vf_mem.in_width-1);
++ ipu_vdi_write(ipu, reg, VDI_FSIZE);
++
++ /* Full motion, only vertical filter is used
++ Burst size is 4 accesses */
++ if (params->mem_prp_vf_mem.in_pixel_fmt ==
++ IPU_PIX_FMT_UYVY ||
++ params->mem_prp_vf_mem.in_pixel_fmt ==
++ IPU_PIX_FMT_YUYV) {
++ pixel_fmt = VDI_C_CH_422;
++ pix_per_burst = 32;
++ } else {
++ pixel_fmt = VDI_C_CH_420;
++ pix_per_burst = 64;
++ }
++
++ reg = ipu_vdi_read(ipu, VDI_C);
++ reg |= pixel_fmt;
++ switch (channel) {
++ case MEM_VDI_PRP_VF_MEM:
++ reg |= VDI_C_BURST_SIZE2_4;
++ break;
++ case MEM_VDI_PRP_VF_MEM_P:
++ reg |= VDI_C_BURST_SIZE1_4 | VDI_C_VWM1_SET_1 | VDI_C_VWM1_CLR_2;
++ break;
++ case MEM_VDI_PRP_VF_MEM_N:
++ reg |= VDI_C_BURST_SIZE3_4 | VDI_C_VWM3_SET_1 | VDI_C_VWM3_CLR_2;
++ break;
++
++ case MEM_VDI_MEM:
++ reg |= (((pix_per_burst >> 2) - 1) & VDI_C_BURST_SIZE_MASK)
++ << VDI_C_BURST_SIZE2_OFFSET;
++ break;
++ case MEM_VDI_MEM_P:
++ reg |= (((pix_per_burst >> 2) - 1) & VDI_C_BURST_SIZE_MASK)
++ << VDI_C_BURST_SIZE1_OFFSET;
++ reg |= VDI_C_VWM1_SET_2 | VDI_C_VWM1_CLR_2;
++ break;
++ case MEM_VDI_MEM_N:
++ reg |= (((pix_per_burst >> 2) - 1) & VDI_C_BURST_SIZE_MASK)
++ << VDI_C_BURST_SIZE3_OFFSET;
++ reg |= VDI_C_VWM3_SET_2 | VDI_C_VWM3_CLR_2;
++ break;
++ default:
++ break;
++ }
++ ipu_vdi_write(ipu, reg, VDI_C);
++
++ if (params->mem_prp_vf_mem.field_fmt == IPU_DEINTERLACE_FIELD_TOP)
++ _ipu_vdi_set_top_field_man(ipu, true);
++ else if (params->mem_prp_vf_mem.field_fmt == IPU_DEINTERLACE_FIELD_BOTTOM)
++ _ipu_vdi_set_top_field_man(ipu, false);
++
++ _ipu_vdi_set_motion(ipu, params->mem_prp_vf_mem.motion_sel);
++
++ reg = ipu_ic_read(ipu, IC_CONF);
++ reg &= ~IC_CONF_RWS_EN;
++ ipu_ic_write(ipu, reg, IC_CONF);
++}
++
++void _ipu_vdi_uninit(struct ipu_soc *ipu)
++{
++ ipu_vdi_write(ipu, 0, VDI_FSIZE);
++ ipu_vdi_write(ipu, 0, VDI_C);
++}
++
++int _ipu_ic_init_prpvf(struct ipu_soc *ipu, ipu_channel_params_t *params,
++ bool src_is_csi)
++{
++ uint32_t reg, ic_conf;
++ uint32_t downsizeCoeff, resizeCoeff;
++ ipu_color_space_t in_fmt, out_fmt;
++ int ret = 0;
++
++ /* Setup vertical resizing */
++ if (!params->mem_prp_vf_mem.outv_resize_ratio) {
++ ret = _calc_resize_coeffs(ipu, params->mem_prp_vf_mem.in_height,
++ params->mem_prp_vf_mem.out_height,
++ &resizeCoeff, &downsizeCoeff);
++ if (ret < 0) {
++ dev_err(ipu->dev, "failed to calculate prpvf height "
++ "scaling coefficients\n");
++ return ret;
++ }
++
++ reg = (downsizeCoeff << 30) | (resizeCoeff << 16);
++ } else
++ reg = (params->mem_prp_vf_mem.outv_resize_ratio) << 16;
++
++ /* Setup horizontal resizing */
++ if (!params->mem_prp_vf_mem.outh_resize_ratio) {
++ ret = _calc_resize_coeffs(ipu, params->mem_prp_vf_mem.in_width,
++ params->mem_prp_vf_mem.out_width,
++ &resizeCoeff, &downsizeCoeff);
++ if (ret < 0) {
++ dev_err(ipu->dev, "failed to calculate prpvf width "
++ "scaling coefficients\n");
++ return ret;
++ }
++
++ reg |= (downsizeCoeff << 14) | resizeCoeff;
++ } else
++ reg |= params->mem_prp_vf_mem.outh_resize_ratio;
++
++ ipu_ic_write(ipu, reg, IC_PRP_VF_RSC);
++
++ ic_conf = ipu_ic_read(ipu, IC_CONF);
++
++ /* Setup color space conversion */
++ in_fmt = format_to_colorspace(params->mem_prp_vf_mem.in_pixel_fmt);
++ out_fmt = format_to_colorspace(params->mem_prp_vf_mem.out_pixel_fmt);
++ if (in_fmt == RGB) {
++ if ((out_fmt == YCbCr) || (out_fmt == YUV)) {
++ /* Enable RGB->YCBCR CSC1 */
++ _init_csc(ipu, IC_TASK_VIEWFINDER, RGB, out_fmt, 1);
++ ic_conf |= IC_CONF_PRPVF_CSC1;
++ }
++ }
++ if ((in_fmt == YCbCr) || (in_fmt == YUV)) {
++ if (out_fmt == RGB) {
++ /* Enable YCBCR->RGB CSC1 */
++ _init_csc(ipu, IC_TASK_VIEWFINDER, YCbCr, RGB, 1);
++ ic_conf |= IC_CONF_PRPVF_CSC1;
++ } else {
++ /* TODO: Support YUV<->YCbCr conversion? */
++ }
++ }
++
++ if (params->mem_prp_vf_mem.graphics_combine_en) {
++ ic_conf |= IC_CONF_PRPVF_CMB;
++
++ if (!(ic_conf & IC_CONF_PRPVF_CSC1)) {
++ /* need transparent CSC1 conversion */
++ _init_csc(ipu, IC_TASK_VIEWFINDER, RGB, RGB, 1);
++ ic_conf |= IC_CONF_PRPVF_CSC1; /* Enable RGB->RGB CSC */
++ }
++ in_fmt = format_to_colorspace(params->mem_prp_vf_mem.in_g_pixel_fmt);
++ out_fmt = format_to_colorspace(params->mem_prp_vf_mem.out_pixel_fmt);
++ if (in_fmt == RGB) {
++ if ((out_fmt == YCbCr) || (out_fmt == YUV)) {
++ /* Enable RGB->YCBCR CSC2 */
++ _init_csc(ipu, IC_TASK_VIEWFINDER, RGB, out_fmt, 2);
++ ic_conf |= IC_CONF_PRPVF_CSC2;
++ }
++ }
++ if ((in_fmt == YCbCr) || (in_fmt == YUV)) {
++ if (out_fmt == RGB) {
++ /* Enable YCBCR->RGB CSC2 */
++ _init_csc(ipu, IC_TASK_VIEWFINDER, YCbCr, RGB, 2);
++ ic_conf |= IC_CONF_PRPVF_CSC2;
++ } else {
++ /* TODO: Support YUV<->YCbCr conversion? */
++ }
++ }
++
++ if (params->mem_prp_vf_mem.global_alpha_en) {
++ ic_conf |= IC_CONF_IC_GLB_LOC_A;
++ reg = ipu_ic_read(ipu, IC_CMBP_1);
++ reg &= ~(0xff);
++ reg |= params->mem_prp_vf_mem.alpha;
++ ipu_ic_write(ipu, reg, IC_CMBP_1);
++ } else
++ ic_conf &= ~IC_CONF_IC_GLB_LOC_A;
++
++ if (params->mem_prp_vf_mem.key_color_en) {
++ ic_conf |= IC_CONF_KEY_COLOR_EN;
++ ipu_ic_write(ipu, params->mem_prp_vf_mem.key_color,
++ IC_CMBP_2);
++ } else
++ ic_conf &= ~IC_CONF_KEY_COLOR_EN;
++ } else {
++ ic_conf &= ~IC_CONF_PRPVF_CMB;
++ }
++
++ if (src_is_csi)
++ ic_conf &= ~IC_CONF_RWS_EN;
++ else
++ ic_conf |= IC_CONF_RWS_EN;
++
++ ipu_ic_write(ipu, ic_conf, IC_CONF);
++
++ return ret;
++}
++
++void _ipu_ic_uninit_prpvf(struct ipu_soc *ipu)
++{
++ uint32_t reg;
++
++ reg = ipu_ic_read(ipu, IC_CONF);
++ reg &= ~(IC_CONF_PRPVF_EN | IC_CONF_PRPVF_CMB |
++ IC_CONF_PRPVF_CSC2 | IC_CONF_PRPVF_CSC1);
++ ipu_ic_write(ipu, reg, IC_CONF);
++}
++
++void _ipu_ic_init_rotate_vf(struct ipu_soc *ipu, ipu_channel_params_t *params)
++{
++}
++
++void _ipu_ic_uninit_rotate_vf(struct ipu_soc *ipu)
++{
++ uint32_t reg;
++ reg = ipu_ic_read(ipu, IC_CONF);
++ reg &= ~IC_CONF_PRPVF_ROT_EN;
++ ipu_ic_write(ipu, reg, IC_CONF);
++}
++
++int _ipu_ic_init_prpenc(struct ipu_soc *ipu, ipu_channel_params_t *params,
++ bool src_is_csi)
++{
++ uint32_t reg, ic_conf;
++ uint32_t downsizeCoeff, resizeCoeff;
++ ipu_color_space_t in_fmt, out_fmt;
++ int ret = 0;
++
++ /* Setup vertical resizing */
++ if (!params->mem_prp_enc_mem.outv_resize_ratio) {
++ ret = _calc_resize_coeffs(ipu,
++ params->mem_prp_enc_mem.in_height,
++ params->mem_prp_enc_mem.out_height,
++ &resizeCoeff, &downsizeCoeff);
++ if (ret < 0) {
++ dev_err(ipu->dev, "failed to calculate prpenc height "
++ "scaling coefficients\n");
++ return ret;
++ }
++
++ reg = (downsizeCoeff << 30) | (resizeCoeff << 16);
++ } else
++ reg = (params->mem_prp_enc_mem.outv_resize_ratio) << 16;
++
++ /* Setup horizontal resizing */
++ if (!params->mem_prp_enc_mem.outh_resize_ratio) {
++ ret = _calc_resize_coeffs(ipu, params->mem_prp_enc_mem.in_width,
++ params->mem_prp_enc_mem.out_width,
++ &resizeCoeff, &downsizeCoeff);
++ if (ret < 0) {
++ dev_err(ipu->dev, "failed to calculate prpenc width "
++ "scaling coefficients\n");
++ return ret;
++ }
++
++ reg |= (downsizeCoeff << 14) | resizeCoeff;
++ } else
++ reg |= params->mem_prp_enc_mem.outh_resize_ratio;
++
++ ipu_ic_write(ipu, reg, IC_PRP_ENC_RSC);
++
++ ic_conf = ipu_ic_read(ipu, IC_CONF);
++
++ /* Setup color space conversion */
++ in_fmt = format_to_colorspace(params->mem_prp_enc_mem.in_pixel_fmt);
++ out_fmt = format_to_colorspace(params->mem_prp_enc_mem.out_pixel_fmt);
++ if (in_fmt == RGB) {
++ if ((out_fmt == YCbCr) || (out_fmt == YUV)) {
++ /* Enable RGB->YCBCR CSC1 */
++ _init_csc(ipu, IC_TASK_ENCODER, RGB, out_fmt, 1);
++ ic_conf |= IC_CONF_PRPENC_CSC1;
++ }
++ }
++ if ((in_fmt == YCbCr) || (in_fmt == YUV)) {
++ if (out_fmt == RGB) {
++ /* Enable YCBCR->RGB CSC1 */
++ _init_csc(ipu, IC_TASK_ENCODER, YCbCr, RGB, 1);
++ ic_conf |= IC_CONF_PRPENC_CSC1;
++ } else {
++ /* TODO: Support YUV<->YCbCr conversion? */
++ }
++ }
++
++ if (src_is_csi)
++ ic_conf &= ~IC_CONF_RWS_EN;
++ else
++ ic_conf |= IC_CONF_RWS_EN;
++
++ ipu_ic_write(ipu, ic_conf, IC_CONF);
++
++ return ret;
++}
++
++void _ipu_ic_uninit_prpenc(struct ipu_soc *ipu)
++{
++ uint32_t reg;
++
++ reg = ipu_ic_read(ipu, IC_CONF);
++ reg &= ~(IC_CONF_PRPENC_EN | IC_CONF_PRPENC_CSC1);
++ ipu_ic_write(ipu, reg, IC_CONF);
++}
++
++void _ipu_ic_init_rotate_enc(struct ipu_soc *ipu, ipu_channel_params_t *params)
++{
++}
++
++void _ipu_ic_uninit_rotate_enc(struct ipu_soc *ipu)
++{
++ uint32_t reg;
++
++ reg = ipu_ic_read(ipu, IC_CONF);
++ reg &= ~(IC_CONF_PRPENC_ROT_EN);
++ ipu_ic_write(ipu, reg, IC_CONF);
++}
++
++int _ipu_ic_init_pp(struct ipu_soc *ipu, ipu_channel_params_t *params)
++{
++ uint32_t reg, ic_conf;
++ uint32_t downsizeCoeff, resizeCoeff;
++ ipu_color_space_t in_fmt, out_fmt;
++ int ret = 0;
++
++ /* Setup vertical resizing */
++ if (!params->mem_pp_mem.outv_resize_ratio) {
++ ret = _calc_resize_coeffs(ipu, params->mem_pp_mem.in_height,
++ params->mem_pp_mem.out_height,
++ &resizeCoeff, &downsizeCoeff);
++ if (ret < 0) {
++ dev_err(ipu->dev, "failed to calculate pp height "
++ "scaling coefficients\n");
++ return ret;
++ }
++
++ reg = (downsizeCoeff << 30) | (resizeCoeff << 16);
++ } else {
++ reg = (params->mem_pp_mem.outv_resize_ratio) << 16;
++ }
++
++ /* Setup horizontal resizing */
++ if (!params->mem_pp_mem.outh_resize_ratio) {
++ ret = _calc_resize_coeffs(ipu, params->mem_pp_mem.in_width,
++ params->mem_pp_mem.out_width,
++ &resizeCoeff, &downsizeCoeff);
++ if (ret < 0) {
++ dev_err(ipu->dev, "failed to calculate pp width "
++ "scaling coefficients\n");
++ return ret;
++ }
++
++ reg |= (downsizeCoeff << 14) | resizeCoeff;
++ } else {
++ reg |= params->mem_pp_mem.outh_resize_ratio;
++ }
++
++ ipu_ic_write(ipu, reg, IC_PP_RSC);
++
++ ic_conf = ipu_ic_read(ipu, IC_CONF);
++
++ /* Setup color space conversion */
++ in_fmt = format_to_colorspace(params->mem_pp_mem.in_pixel_fmt);
++ out_fmt = format_to_colorspace(params->mem_pp_mem.out_pixel_fmt);
++ if (in_fmt == RGB) {
++ if ((out_fmt == YCbCr) || (out_fmt == YUV)) {
++ /* Enable RGB->YCBCR CSC1 */
++ _init_csc(ipu, IC_TASK_POST_PROCESSOR, RGB, out_fmt, 1);
++ ic_conf |= IC_CONF_PP_CSC1;
++ }
++ }
++ if ((in_fmt == YCbCr) || (in_fmt == YUV)) {
++ if (out_fmt == RGB) {
++ /* Enable YCBCR->RGB CSC1 */
++ _init_csc(ipu, IC_TASK_POST_PROCESSOR, YCbCr, RGB, 1);
++ ic_conf |= IC_CONF_PP_CSC1;
++ } else {
++ /* TODO: Support YUV<->YCbCr conversion? */
++ }
++ }
++
++ if (params->mem_pp_mem.graphics_combine_en) {
++ ic_conf |= IC_CONF_PP_CMB;
++
++ if (!(ic_conf & IC_CONF_PP_CSC1)) {
++ /* need transparent CSC1 conversion */
++ _init_csc(ipu, IC_TASK_POST_PROCESSOR, RGB, RGB, 1);
++ ic_conf |= IC_CONF_PP_CSC1; /* Enable RGB->RGB CSC */
++ }
++
++ in_fmt = format_to_colorspace(params->mem_pp_mem.in_g_pixel_fmt);
++ out_fmt = format_to_colorspace(params->mem_pp_mem.out_pixel_fmt);
++ if (in_fmt == RGB) {
++ if ((out_fmt == YCbCr) || (out_fmt == YUV)) {
++ /* Enable RGB->YCBCR CSC2 */
++ _init_csc(ipu, IC_TASK_POST_PROCESSOR, RGB, out_fmt, 2);
++ ic_conf |= IC_CONF_PP_CSC2;
++ }
++ }
++ if ((in_fmt == YCbCr) || (in_fmt == YUV)) {
++ if (out_fmt == RGB) {
++ /* Enable YCBCR->RGB CSC2 */
++ _init_csc(ipu, IC_TASK_POST_PROCESSOR, YCbCr, RGB, 2);
++ ic_conf |= IC_CONF_PP_CSC2;
++ } else {
++ /* TODO: Support YUV<->YCbCr conversion? */
++ }
++ }
++
++ if (params->mem_pp_mem.global_alpha_en) {
++ ic_conf |= IC_CONF_IC_GLB_LOC_A;
++ reg = ipu_ic_read(ipu, IC_CMBP_1);
++ reg &= ~(0xff00);
++ reg |= (params->mem_pp_mem.alpha << 8);
++ ipu_ic_write(ipu, reg, IC_CMBP_1);
++ } else
++ ic_conf &= ~IC_CONF_IC_GLB_LOC_A;
++
++ if (params->mem_pp_mem.key_color_en) {
++ ic_conf |= IC_CONF_KEY_COLOR_EN;
++ ipu_ic_write(ipu, params->mem_pp_mem.key_color,
++ IC_CMBP_2);
++ } else
++ ic_conf &= ~IC_CONF_KEY_COLOR_EN;
++ } else {
++ ic_conf &= ~IC_CONF_PP_CMB;
++ }
++
++ ipu_ic_write(ipu, ic_conf, IC_CONF);
++
++ return ret;
++}
++
++void _ipu_ic_uninit_pp(struct ipu_soc *ipu)
++{
++ uint32_t reg;
++
++ reg = ipu_ic_read(ipu, IC_CONF);
++ reg &= ~(IC_CONF_PP_EN | IC_CONF_PP_CSC1 | IC_CONF_PP_CSC2 |
++ IC_CONF_PP_CMB);
++ ipu_ic_write(ipu, reg, IC_CONF);
++}
++
++void _ipu_ic_init_rotate_pp(struct ipu_soc *ipu, ipu_channel_params_t *params)
++{
++}
++
++void _ipu_ic_uninit_rotate_pp(struct ipu_soc *ipu)
++{
++ uint32_t reg;
++ reg = ipu_ic_read(ipu, IC_CONF);
++ reg &= ~IC_CONF_PP_ROT_EN;
++ ipu_ic_write(ipu, reg, IC_CONF);
++}
++
++int _ipu_ic_idma_init(struct ipu_soc *ipu, int dma_chan,
++ uint16_t width, uint16_t height,
++ int burst_size, ipu_rotate_mode_t rot)
++{
++ u32 ic_idmac_1, ic_idmac_2, ic_idmac_3;
++ u32 temp_rot = bitrev8(rot) >> 5;
++ bool need_hor_flip = false;
++
++ if ((burst_size != 8) && (burst_size != 16)) {
++ dev_dbg(ipu->dev, "Illegal burst length for IC\n");
++ return -EINVAL;
++ }
++
++ width--;
++ height--;
++
++ if (temp_rot & 0x2) /* Need horizontal flip */
++ need_hor_flip = true;
++
++ ic_idmac_1 = ipu_ic_read(ipu, IC_IDMAC_1);
++ ic_idmac_2 = ipu_ic_read(ipu, IC_IDMAC_2);
++ ic_idmac_3 = ipu_ic_read(ipu, IC_IDMAC_3);
++ if (dma_chan == 22) { /* PP output - CB2 */
++ if (burst_size == 16)
++ ic_idmac_1 |= IC_IDMAC_1_CB2_BURST_16;
++ else
++ ic_idmac_1 &= ~IC_IDMAC_1_CB2_BURST_16;
++
++ if (need_hor_flip)
++ ic_idmac_1 |= IC_IDMAC_1_PP_FLIP_RS;
++ else
++ ic_idmac_1 &= ~IC_IDMAC_1_PP_FLIP_RS;
++
++ ic_idmac_2 &= ~IC_IDMAC_2_PP_HEIGHT_MASK;
++ ic_idmac_2 |= height << IC_IDMAC_2_PP_HEIGHT_OFFSET;
++
++ ic_idmac_3 &= ~IC_IDMAC_3_PP_WIDTH_MASK;
++ ic_idmac_3 |= width << IC_IDMAC_3_PP_WIDTH_OFFSET;
++ } else if (dma_chan == 11) { /* PP Input - CB5 */
++ if (burst_size == 16)
++ ic_idmac_1 |= IC_IDMAC_1_CB5_BURST_16;
++ else
++ ic_idmac_1 &= ~IC_IDMAC_1_CB5_BURST_16;
++ } else if (dma_chan == 47) { /* PP Rot input */
++ ic_idmac_1 &= ~IC_IDMAC_1_PP_ROT_MASK;
++ ic_idmac_1 |= temp_rot << IC_IDMAC_1_PP_ROT_OFFSET;
++ }
++
++ if (dma_chan == 12) { /* PRP Input - CB6 */
++ if (burst_size == 16)
++ ic_idmac_1 |= IC_IDMAC_1_CB6_BURST_16;
++ else
++ ic_idmac_1 &= ~IC_IDMAC_1_CB6_BURST_16;
++ }
++
++ if (dma_chan == 20) { /* PRP ENC output - CB0 */
++ if (burst_size == 16)
++ ic_idmac_1 |= IC_IDMAC_1_CB0_BURST_16;
++ else
++ ic_idmac_1 &= ~IC_IDMAC_1_CB0_BURST_16;
++
++ if (need_hor_flip)
++ ic_idmac_1 |= IC_IDMAC_1_PRPENC_FLIP_RS;
++ else
++ ic_idmac_1 &= ~IC_IDMAC_1_PRPENC_FLIP_RS;
++
++ ic_idmac_2 &= ~IC_IDMAC_2_PRPENC_HEIGHT_MASK;
++ ic_idmac_2 |= height << IC_IDMAC_2_PRPENC_HEIGHT_OFFSET;
++
++ ic_idmac_3 &= ~IC_IDMAC_3_PRPENC_WIDTH_MASK;
++ ic_idmac_3 |= width << IC_IDMAC_3_PRPENC_WIDTH_OFFSET;
++
++ } else if (dma_chan == 45) { /* PRP ENC Rot input */
++ ic_idmac_1 &= ~IC_IDMAC_1_PRPENC_ROT_MASK;
++ ic_idmac_1 |= temp_rot << IC_IDMAC_1_PRPENC_ROT_OFFSET;
++ }
++
++ if (dma_chan == 21) { /* PRP VF output - CB1 */
++ if (burst_size == 16)
++ ic_idmac_1 |= IC_IDMAC_1_CB1_BURST_16;
++ else
++ ic_idmac_1 &= ~IC_IDMAC_1_CB1_BURST_16;
++
++ if (need_hor_flip)
++ ic_idmac_1 |= IC_IDMAC_1_PRPVF_FLIP_RS;
++ else
++ ic_idmac_1 &= ~IC_IDMAC_1_PRPVF_FLIP_RS;
++
++ ic_idmac_2 &= ~IC_IDMAC_2_PRPVF_HEIGHT_MASK;
++ ic_idmac_2 |= height << IC_IDMAC_2_PRPVF_HEIGHT_OFFSET;
++
++ ic_idmac_3 &= ~IC_IDMAC_3_PRPVF_WIDTH_MASK;
++ ic_idmac_3 |= width << IC_IDMAC_3_PRPVF_WIDTH_OFFSET;
++
++ } else if (dma_chan == 46) { /* PRP VF Rot input */
++ ic_idmac_1 &= ~IC_IDMAC_1_PRPVF_ROT_MASK;
++ ic_idmac_1 |= temp_rot << IC_IDMAC_1_PRPVF_ROT_OFFSET;
++ }
++
++ if (dma_chan == 14) { /* PRP VF graphics combining input - CB3 */
++ if (burst_size == 16)
++ ic_idmac_1 |= IC_IDMAC_1_CB3_BURST_16;
++ else
++ ic_idmac_1 &= ~IC_IDMAC_1_CB3_BURST_16;
++ } else if (dma_chan == 15) { /* PP graphics combining input - CB4 */
++ if (burst_size == 16)
++ ic_idmac_1 |= IC_IDMAC_1_CB4_BURST_16;
++ else
++ ic_idmac_1 &= ~IC_IDMAC_1_CB4_BURST_16;
++ } else if (dma_chan == 5) { /* VDIC OUTPUT - CB7 */
++ if (burst_size == 16)
++ ic_idmac_1 |= IC_IDMAC_1_CB7_BURST_16;
++ else
++ ic_idmac_1 &= ~IC_IDMAC_1_CB7_BURST_16;
++ }
++
++ ipu_ic_write(ipu, ic_idmac_1, IC_IDMAC_1);
++ ipu_ic_write(ipu, ic_idmac_2, IC_IDMAC_2);
++ ipu_ic_write(ipu, ic_idmac_3, IC_IDMAC_3);
++ return 0;
++}
++
++static void _init_csc(struct ipu_soc *ipu, uint8_t ic_task, ipu_color_space_t in_format,
++ ipu_color_space_t out_format, int csc_index)
++{
++ /*
++ * Y = 0.257 * R + 0.504 * G + 0.098 * B + 16;
++ * U = -0.148 * R - 0.291 * G + 0.439 * B + 128;
++ * V = 0.439 * R - 0.368 * G - 0.071 * B + 128;
++ */
++ static const uint32_t rgb2ycbcr_coeff[4][3] = {
++ {0x0042, 0x0081, 0x0019},
++ {0x01DA, 0x01B6, 0x0070},
++ {0x0070, 0x01A2, 0x01EE},
++ {0x0040, 0x0200, 0x0200}, /* A0, A1, A2 */
++ };
++
++ /* transparent RGB->RGB matrix for combining
++ */
++ static const uint32_t rgb2rgb_coeff[4][3] = {
++ {0x0080, 0x0000, 0x0000},
++ {0x0000, 0x0080, 0x0000},
++ {0x0000, 0x0000, 0x0080},
++ {0x0000, 0x0000, 0x0000}, /* A0, A1, A2 */
++ };
++
++/* R = (1.164 * (Y - 16)) + (1.596 * (Cr - 128));
++ G = (1.164 * (Y - 16)) - (0.392 * (Cb - 128)) - (0.813 * (Cr - 128));
++ B = (1.164 * (Y - 16)) + (2.017 * (Cb - 128); */
++ static const uint32_t ycbcr2rgb_coeff[4][3] = {
++ {149, 0, 204},
++ {149, 462, 408},
++ {149, 255, 0},
++ {8192 - 446, 266, 8192 - 554}, /* A0, A1, A2 */
++ };
++
++ uint32_t param;
++ uint32_t *base = NULL;
++
++ if (ic_task == IC_TASK_ENCODER) {
++ base = (uint32_t *)ipu->tpmem_base + 0x2008 / 4;
++ } else if (ic_task == IC_TASK_VIEWFINDER) {
++ if (csc_index == 1)
++ base = (uint32_t *)ipu->tpmem_base + 0x4028 / 4;
++ else
++ base = (uint32_t *)ipu->tpmem_base + 0x4040 / 4;
++ } else if (ic_task == IC_TASK_POST_PROCESSOR) {
++ if (csc_index == 1)
++ base = (uint32_t *)ipu->tpmem_base + 0x6060 / 4;
++ else
++ base = (uint32_t *)ipu->tpmem_base + 0x6078 / 4;
++ } else {
++ BUG();
++ }
++
++ if ((in_format == YCbCr) && (out_format == RGB)) {
++ /* Init CSC (YCbCr->RGB) */
++ param = (ycbcr2rgb_coeff[3][0] << 27) |
++ (ycbcr2rgb_coeff[0][0] << 18) |
++ (ycbcr2rgb_coeff[1][1] << 9) | ycbcr2rgb_coeff[2][2];
++ writel(param, base++);
++ /* scale = 2, sat = 0 */
++ param = (ycbcr2rgb_coeff[3][0] >> 5) | (2L << (40 - 32));
++ writel(param, base++);
++
++ param = (ycbcr2rgb_coeff[3][1] << 27) |
++ (ycbcr2rgb_coeff[0][1] << 18) |
++ (ycbcr2rgb_coeff[1][0] << 9) | ycbcr2rgb_coeff[2][0];
++ writel(param, base++);
++ param = (ycbcr2rgb_coeff[3][1] >> 5);
++ writel(param, base++);
++
++ param = (ycbcr2rgb_coeff[3][2] << 27) |
++ (ycbcr2rgb_coeff[0][2] << 18) |
++ (ycbcr2rgb_coeff[1][2] << 9) | ycbcr2rgb_coeff[2][1];
++ writel(param, base++);
++ param = (ycbcr2rgb_coeff[3][2] >> 5);
++ writel(param, base++);
++ } else if ((in_format == RGB) && (out_format == YCbCr)) {
++ /* Init CSC (RGB->YCbCr) */
++ param = (rgb2ycbcr_coeff[3][0] << 27) |
++ (rgb2ycbcr_coeff[0][0] << 18) |
++ (rgb2ycbcr_coeff[1][1] << 9) | rgb2ycbcr_coeff[2][2];
++ writel(param, base++);
++ /* scale = 1, sat = 0 */
++ param = (rgb2ycbcr_coeff[3][0] >> 5) | (1UL << 8);
++ writel(param, base++);
++
++ param = (rgb2ycbcr_coeff[3][1] << 27) |
++ (rgb2ycbcr_coeff[0][1] << 18) |
++ (rgb2ycbcr_coeff[1][0] << 9) | rgb2ycbcr_coeff[2][0];
++ writel(param, base++);
++ param = (rgb2ycbcr_coeff[3][1] >> 5);
++ writel(param, base++);
++
++ param = (rgb2ycbcr_coeff[3][2] << 27) |
++ (rgb2ycbcr_coeff[0][2] << 18) |
++ (rgb2ycbcr_coeff[1][2] << 9) | rgb2ycbcr_coeff[2][1];
++ writel(param, base++);
++ param = (rgb2ycbcr_coeff[3][2] >> 5);
++ writel(param, base++);
++ } else if ((in_format == RGB) && (out_format == RGB)) {
++ /* Init CSC */
++ param =
++ (rgb2rgb_coeff[3][0] << 27) | (rgb2rgb_coeff[0][0] << 18) |
++ (rgb2rgb_coeff[1][1] << 9) | rgb2rgb_coeff[2][2];
++ writel(param, base++);
++ /* scale = 2, sat = 0 */
++ param = (rgb2rgb_coeff[3][0] >> 5) | (2UL << 8);
++ writel(param, base++);
++
++ param =
++ (rgb2rgb_coeff[3][1] << 27) | (rgb2rgb_coeff[0][1] << 18) |
++ (rgb2rgb_coeff[1][0] << 9) | rgb2rgb_coeff[2][0];
++ writel(param, base++);
++ param = (rgb2rgb_coeff[3][1] >> 5);
++ writel(param, base++);
++
++ param =
++ (rgb2rgb_coeff[3][2] << 27) | (rgb2rgb_coeff[0][2] << 18) |
++ (rgb2rgb_coeff[1][2] << 9) | rgb2rgb_coeff[2][1];
++ writel(param, base++);
++ param = (rgb2rgb_coeff[3][2] >> 5);
++ writel(param, base++);
++ } else {
++ dev_err(ipu->dev, "Unsupported color space conversion\n");
++ }
++}
++
++static int _calc_resize_coeffs(struct ipu_soc *ipu,
++ uint32_t inSize, uint32_t outSize,
++ uint32_t *resizeCoeff,
++ uint32_t *downsizeCoeff)
++{
++ uint32_t tempSize;
++ uint32_t tempDownsize;
++
++ if (inSize > 4096) {
++ dev_err(ipu->dev, "IC input size(%d) cannot exceed 4096\n",
++ inSize);
++ return -EINVAL;
++ }
++
++ if (outSize > 1024) {
++ dev_err(ipu->dev, "IC output size(%d) cannot exceed 1024\n",
++ outSize);
++ return -EINVAL;
++ }
++
++ if ((outSize << 3) < inSize) {
++ dev_err(ipu->dev, "IC cannot downsize more than 8:1\n");
++ return -EINVAL;
++ }
++
++ /* Compute downsizing coefficient */
++ /* Output of downsizing unit cannot be more than 1024 */
++ tempDownsize = 0;
++ tempSize = inSize;
++ while (((tempSize > 1024) || (tempSize >= outSize * 2)) &&
++ (tempDownsize < 2)) {
++ tempSize >>= 1;
++ tempDownsize++;
++ }
++ *downsizeCoeff = tempDownsize;
++
++ /* compute resizing coefficient using the following equation:
++ resizeCoeff = M*(SI -1)/(SO - 1)
++ where M = 2^13, SI - input size, SO - output size */
++ *resizeCoeff = (8192L * (tempSize - 1)) / (outSize - 1);
++ if (*resizeCoeff >= 16384L) {
++ dev_err(ipu->dev, "Overflow on IC resize coefficient.\n");
++ return -EINVAL;
++ }
++
++ dev_dbg(ipu->dev, "resizing from %u -> %u pixels, "
++ "downsize=%u, resize=%u.%lu (reg=%u)\n", inSize, outSize,
++ *downsizeCoeff, (*resizeCoeff >= 8192L) ? 1 : 0,
++ ((*resizeCoeff & 0x1FFF) * 10000L) / 8192L, *resizeCoeff);
++
++ return 0;
++}
++
++void _ipu_vdi_toggle_top_field_man(struct ipu_soc *ipu)
++{
++ uint32_t reg;
++ uint32_t mask_reg;
++
++ reg = ipu_vdi_read(ipu, VDI_C);
++ mask_reg = reg & VDI_C_TOP_FIELD_MAN_1;
++ if (mask_reg == VDI_C_TOP_FIELD_MAN_1)
++ reg &= ~VDI_C_TOP_FIELD_MAN_1;
++ else
++ reg |= VDI_C_TOP_FIELD_MAN_1;
++
++ ipu_vdi_write(ipu, reg, VDI_C);
++}
+diff -Nur linux-4.1.3/drivers/mxc/ipu3/ipu_param_mem.h linux-xbian-imx6/drivers/mxc/ipu3/ipu_param_mem.h
+--- linux-4.1.3/drivers/mxc/ipu3/ipu_param_mem.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/ipu3/ipu_param_mem.h 2015-07-27 23:13:06.226765901 +0200
+@@ -0,0 +1,921 @@
++/*
++ * Copyright 2005-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++#ifndef __INCLUDE_IPU_PARAM_MEM_H__
++#define __INCLUDE_IPU_PARAM_MEM_H__
++
++#include <linux/bitrev.h>
++#include <linux/types.h>
++
++#include "ipu_prv.h"
++
++extern u32 *ipu_cpmem_base;
++
++struct ipu_ch_param_word {
++ uint32_t data[5];
++ uint32_t res[3];
++};
++
++struct ipu_ch_param {
++ struct ipu_ch_param_word word[2];
++};
++
++#define ipu_ch_param_addr(ipu, ch) (((struct ipu_ch_param *)ipu->cpmem_base) + (ch))
++
++#define _param_word(base, w) \
++ (((struct ipu_ch_param *)(base))->word[(w)].data)
++
++#define ipu_ch_param_set_field(base, w, bit, size, v) { \
++ int i = (bit) / 32; \
++ int off = (bit) % 32; \
++ _param_word(base, w)[i] |= (v) << off; \
++ if (((bit)+(size)-1)/32 > i) { \
++ _param_word(base, w)[i + 1] |= (v) >> (off ? (32 - off) : 0); \
++ } \
++}
++
++#define ipu_ch_param_set_field_io(base, w, bit, size, v) { \
++ int i = (bit) / 32; \
++ int off = (bit) % 32; \
++ unsigned reg_offset; \
++ u32 temp; \
++ reg_offset = sizeof(struct ipu_ch_param_word) * w / 4; \
++ reg_offset += i; \
++ temp = readl((u32 *)base + reg_offset); \
++ temp |= (v) << off; \
++ writel(temp, (u32 *)base + reg_offset); \
++ if (((bit)+(size)-1)/32 > i) { \
++ reg_offset++; \
++ temp = readl((u32 *)base + reg_offset); \
++ temp |= (v) >> (off ? (32 - off) : 0); \
++ writel(temp, (u32 *)base + reg_offset); \
++ } \
++}
++
++#define ipu_ch_param_mod_field(base, w, bit, size, v) { \
++ int i = (bit) / 32; \
++ int off = (bit) % 32; \
++ u32 mask = (1UL << size) - 1; \
++ u32 temp = _param_word(base, w)[i]; \
++ temp &= ~(mask << off); \
++ _param_word(base, w)[i] = temp | (v) << off; \
++ if (((bit)+(size)-1)/32 > i) { \
++ temp = _param_word(base, w)[i + 1]; \
++ temp &= ~(mask >> (32 - off)); \
++ _param_word(base, w)[i + 1] = \
++ temp | ((v) >> (off ? (32 - off) : 0)); \
++ } \
++}
++
++#define ipu_ch_param_mod_field_io(base, w, bit, size, v) { \
++ int i = (bit) / 32; \
++ int off = (bit) % 32; \
++ u32 mask = (1UL << size) - 1; \
++ unsigned reg_offset; \
++ u32 temp; \
++ reg_offset = sizeof(struct ipu_ch_param_word) * w / 4; \
++ reg_offset += i; \
++ temp = readl((u32 *)base + reg_offset); \
++ temp &= ~(mask << off); \
++ temp |= (v) << off; \
++ writel(temp, (u32 *)base + reg_offset); \
++ if (((bit)+(size)-1)/32 > i) { \
++ reg_offset++; \
++ temp = readl((u32 *)base + reg_offset); \
++ temp &= ~(mask >> (32 - off)); \
++ temp |= ((v) >> (off ? (32 - off) : 0)); \
++ writel(temp, (u32 *)base + reg_offset); \
++ } \
++}
++
++#define ipu_ch_param_read_field(base, w, bit, size) ({ \
++ u32 temp2; \
++ int i = (bit) / 32; \
++ int off = (bit) % 32; \
++ u32 mask = (1UL << size) - 1; \
++ u32 temp1 = _param_word(base, w)[i]; \
++ temp1 = mask & (temp1 >> off); \
++ if (((bit)+(size)-1)/32 > i) { \
++ temp2 = _param_word(base, w)[i + 1]; \
++ temp2 &= mask >> (off ? (32 - off) : 0); \
++ temp1 |= temp2 << (off ? (32 - off) : 0); \
++ } \
++ temp1; \
++})
++
++#define ipu_ch_param_read_field_io(base, w, bit, size) ({ \
++ u32 temp1, temp2; \
++ int i = (bit) / 32; \
++ int off = (bit) % 32; \
++ u32 mask = (1UL << size) - 1; \
++ unsigned reg_offset; \
++ reg_offset = sizeof(struct ipu_ch_param_word) * w / 4; \
++ reg_offset += i; \
++ temp1 = readl((u32 *)base + reg_offset); \
++ temp1 = mask & (temp1 >> off); \
++ if (((bit)+(size)-1)/32 > i) { \
++ reg_offset++; \
++ temp2 = readl((u32 *)base + reg_offset); \
++ temp2 &= mask >> (off ? (32 - off) : 0); \
++ temp1 |= temp2 << (off ? (32 - off) : 0); \
++ } \
++ temp1; \
++})
++
++static inline int __ipu_ch_get_third_buf_cpmem_num(int ch)
++{
++ switch (ch) {
++ case 8:
++ return 64;
++ case 9:
++ return 65;
++ case 10:
++ return 66;
++ case 13:
++ return 67;
++ case 21:
++ return 68;
++ case 23:
++ return 69;
++ case 27:
++ return 70;
++ case 28:
++ return 71;
++ default:
++ return -EINVAL;
++ }
++ return 0;
++}
++
++static inline void _ipu_ch_params_set_packing(struct ipu_ch_param *p,
++ int red_width, int red_offset,
++ int green_width, int green_offset,
++ int blue_width, int blue_offset,
++ int alpha_width, int alpha_offset)
++{
++ /* Setup red width and offset */
++ ipu_ch_param_set_field(p, 1, 116, 3, red_width - 1);
++ ipu_ch_param_set_field(p, 1, 128, 5, red_offset);
++ /* Setup green width and offset */
++ ipu_ch_param_set_field(p, 1, 119, 3, green_width - 1);
++ ipu_ch_param_set_field(p, 1, 133, 5, green_offset);
++ /* Setup blue width and offset */
++ ipu_ch_param_set_field(p, 1, 122, 3, blue_width - 1);
++ ipu_ch_param_set_field(p, 1, 138, 5, blue_offset);
++ /* Setup alpha width and offset */
++ ipu_ch_param_set_field(p, 1, 125, 3, alpha_width - 1);
++ ipu_ch_param_set_field(p, 1, 143, 5, alpha_offset);
++}
++
++static inline void _ipu_ch_param_dump(struct ipu_soc *ipu, int ch)
++{
++ struct ipu_ch_param *p = ipu_ch_param_addr(ipu, ch);
++ dev_dbg(ipu->dev, "ch %d word 0 - %08X %08X %08X %08X %08X\n", ch,
++ p->word[0].data[0], p->word[0].data[1], p->word[0].data[2],
++ p->word[0].data[3], p->word[0].data[4]);
++ dev_dbg(ipu->dev, "ch %d word 1 - %08X %08X %08X %08X %08X\n", ch,
++ p->word[1].data[0], p->word[1].data[1], p->word[1].data[2],
++ p->word[1].data[3], p->word[1].data[4]);
++ dev_dbg(ipu->dev, "PFS 0x%x, ",
++ ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 1, 85, 4));
++ dev_dbg(ipu->dev, "BPP 0x%x, ",
++ ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 0, 107, 3));
++ dev_dbg(ipu->dev, "NPB 0x%x\n",
++ ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 1, 78, 7));
++
++ dev_dbg(ipu->dev, "FW %d, ",
++ ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 0, 125, 13));
++ dev_dbg(ipu->dev, "FH %d, ",
++ ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 0, 138, 12));
++ dev_dbg(ipu->dev, "EBA0 0x%x\n",
++ ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 1, 0, 29) << 3);
++ dev_dbg(ipu->dev, "EBA1 0x%x\n",
++ ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 1, 29, 29) << 3);
++ dev_dbg(ipu->dev, "Stride %d\n",
++ ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 1, 102, 14));
++ dev_dbg(ipu->dev, "scan_order %d\n",
++ ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 0, 113, 1));
++ dev_dbg(ipu->dev, "uv_stride %d\n",
++ ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 1, 128, 14));
++ dev_dbg(ipu->dev, "u_offset 0x%x\n",
++ ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 0, 46, 22) << 3);
++ dev_dbg(ipu->dev, "v_offset 0x%x\n",
++ ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 0, 68, 22) << 3);
++
++ dev_dbg(ipu->dev, "Width0 %d+1, ",
++ ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 1, 116, 3));
++ dev_dbg(ipu->dev, "Width1 %d+1, ",
++ ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 1, 119, 3));
++ dev_dbg(ipu->dev, "Width2 %d+1, ",
++ ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 1, 122, 3));
++ dev_dbg(ipu->dev, "Width3 %d+1, ",
++ ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 1, 125, 3));
++ dev_dbg(ipu->dev, "Offset0 %d, ",
++ ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 1, 128, 5));
++ dev_dbg(ipu->dev, "Offset1 %d, ",
++ ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 1, 133, 5));
++ dev_dbg(ipu->dev, "Offset2 %d, ",
++ ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 1, 138, 5));
++ dev_dbg(ipu->dev, "Offset3 %d\n",
++ ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 1, 143, 5));
++}
++
++static inline void fill_cpmem(struct ipu_soc *ipu, int ch, struct ipu_ch_param *params)
++{
++ int i, w;
++ void *addr = ipu_ch_param_addr(ipu, ch);
++
++ /* 2 words, 5 valid data */
++ for (w = 0; w < 2; w++) {
++ for (i = 0; i < 5; i++) {
++ writel(params->word[w].data[i], addr);
++ addr += 4;
++ }
++ addr += 12;
++ }
++}
++
++static inline void _ipu_ch_param_init(struct ipu_soc *ipu, int ch,
++ uint32_t pixel_fmt, uint32_t width,
++ uint32_t height, uint32_t stride,
++ uint32_t u, uint32_t v,
++ uint32_t uv_stride, dma_addr_t addr0,
++ dma_addr_t addr1, dma_addr_t addr2)
++{
++ uint32_t u_offset = 0;
++ uint32_t v_offset = 0;
++ int32_t sub_ch = 0;
++ struct ipu_ch_param params;
++
++ memset(&params, 0, sizeof(params));
++
++ ipu_ch_param_set_field(&params, 0, 125, 13, width - 1);
++
++ if (((ch == 8) || (ch == 9) || (ch == 10)) && !ipu->vdoa_en) {
++ ipu_ch_param_set_field(&params, 0, 138, 12, (height / 2) - 1);
++ ipu_ch_param_set_field(&params, 1, 102, 14, (stride * 2) - 1);
++ } else {
++ /* note: for vdoa+vdi- ch8/9/10, always use band mode */
++ ipu_ch_param_set_field(&params, 0, 138, 12, height - 1);
++ ipu_ch_param_set_field(&params, 1, 102, 14, stride - 1);
++ }
++
++ /* EBA is 8-byte aligned */
++ ipu_ch_param_set_field(&params, 1, 0, 29, addr0 >> 3);
++ ipu_ch_param_set_field(&params, 1, 29, 29, addr1 >> 3);
++ if (addr0%8)
++ dev_warn(ipu->dev,
++ "IDMAC%d's EBA0 is not 8-byte aligned\n", ch);
++ if (addr1%8)
++ dev_warn(ipu->dev,
++ "IDMAC%d's EBA1 is not 8-byte aligned\n", ch);
++
++ switch (pixel_fmt) {
++ case IPU_PIX_FMT_GENERIC:
++ /*Represents 8-bit Generic data */
++ ipu_ch_param_set_field(&params, 0, 107, 3, 5); /* bits/pixel */
++ ipu_ch_param_set_field(&params, 1, 85, 4, 6); /* pix format */
++ ipu_ch_param_set_field(&params, 1, 78, 7, 63); /* burst size */
++
++ break;
++ case IPU_PIX_FMT_GENERIC_16:
++ /* Represents 16-bit generic data */
++ ipu_ch_param_set_field(&params, 0, 107, 3, 3); /* bits/pixel */
++ ipu_ch_param_set_field(&params, 1, 85, 4, 6); /* pix format */
++ ipu_ch_param_set_field(&params, 1, 78, 7, 31); /* burst size */
++
++ break;
++ case IPU_PIX_FMT_GENERIC_32:
++ /*Represents 32-bit Generic data */
++ break;
++ case IPU_PIX_FMT_RGB565:
++ ipu_ch_param_set_field(&params, 0, 107, 3, 3); /* bits/pixel */
++ ipu_ch_param_set_field(&params, 1, 85, 4, 7); /* pix format */
++ ipu_ch_param_set_field(&params, 1, 78, 7, 31); /* burst size */
++
++ _ipu_ch_params_set_packing(&params, 5, 0, 6, 5, 5, 11, 8, 16);
++ break;
++ case IPU_PIX_FMT_BGR24:
++ ipu_ch_param_set_field(&params, 0, 107, 3, 1); /* bits/pixel */
++ ipu_ch_param_set_field(&params, 1, 85, 4, 7); /* pix format */
++ ipu_ch_param_set_field(&params, 1, 78, 7, 19); /* burst size */
++
++ _ipu_ch_params_set_packing(&params, 8, 0, 8, 8, 8, 16, 8, 24);
++ break;
++ case IPU_PIX_FMT_RGB24:
++ case IPU_PIX_FMT_YUV444:
++ ipu_ch_param_set_field(&params, 0, 107, 3, 1); /* bits/pixel */
++ ipu_ch_param_set_field(&params, 1, 85, 4, 7); /* pix format */
++ ipu_ch_param_set_field(&params, 1, 78, 7, 19); /* burst size */
++
++ _ipu_ch_params_set_packing(&params, 8, 16, 8, 8, 8, 0, 8, 24);
++ break;
++ case IPU_PIX_FMT_VYU444:
++ ipu_ch_param_set_field(&params, 0, 107, 3, 1); /* bits/pixel */
++ ipu_ch_param_set_field(&params, 1, 85, 4, 7); /* pix format */
++ ipu_ch_param_set_field(&params, 1, 78, 7, 19); /* burst size */
++
++ _ipu_ch_params_set_packing(&params, 8, 8, 8, 0, 8, 16, 8, 24);
++ break;
++ case IPU_PIX_FMT_BGRA32:
++ case IPU_PIX_FMT_BGR32:
++ ipu_ch_param_set_field(&params, 0, 107, 3, 0); /* bits/pixel */
++ ipu_ch_param_set_field(&params, 1, 85, 4, 7); /* pix format */
++ ipu_ch_param_set_field(&params, 1, 78, 7, 15); /* burst size */
++
++ _ipu_ch_params_set_packing(&params, 8, 8, 8, 16, 8, 24, 8, 0);
++ break;
++ case IPU_PIX_FMT_RGBA32:
++ case IPU_PIX_FMT_RGB32:
++ ipu_ch_param_set_field(&params, 0, 107, 3, 0); /* bits/pixel */
++ ipu_ch_param_set_field(&params, 1, 85, 4, 7); /* pix format */
++ ipu_ch_param_set_field(&params, 1, 78, 7, 15); /* burst size */
++
++ _ipu_ch_params_set_packing(&params, 8, 24, 8, 16, 8, 8, 8, 0);
++ break;
++ case IPU_PIX_FMT_ABGR32:
++ ipu_ch_param_set_field(&params, 0, 107, 3, 0); /* bits/pixel */
++ ipu_ch_param_set_field(&params, 1, 85, 4, 7); /* pix format */
++ ipu_ch_param_set_field(&params, 1, 78, 7, 15); /* burst size */
++
++ _ipu_ch_params_set_packing(&params, 8, 0, 8, 8, 8, 16, 8, 24);
++ break;
++ case IPU_PIX_FMT_UYVY:
++ ipu_ch_param_set_field(&params, 0, 107, 3, 3); /* bits/pixel */
++ ipu_ch_param_set_field(&params, 1, 85, 4, 0xA); /* pix format */
++ if ((ch == 8) || (ch == 9) || (ch == 10)) {
++ ipu_ch_param_set_field(&params, 1, 78, 7, 15); /* burst size */
++ } else {
++ ipu_ch_param_set_field(&params, 1, 78, 7, 31); /* burst size */
++ }
++ break;
++ case IPU_PIX_FMT_YUYV:
++ ipu_ch_param_set_field(&params, 0, 107, 3, 3); /* bits/pixel */
++ ipu_ch_param_set_field(&params, 1, 85, 4, 0x8); /* pix format */
++ if ((ch == 8) || (ch == 9) || (ch == 10)) {
++ if (ipu->vdoa_en) {
++ ipu_ch_param_set_field(&params, 1, 78, 7, 31);
++ } else {
++ ipu_ch_param_set_field(&params, 1, 78, 7, 15);
++ }
++ } else {
++ ipu_ch_param_set_field(&params, 1, 78, 7, 31); /* burst size */
++ }
++ break;
++ case IPU_PIX_FMT_YUV420P2:
++ case IPU_PIX_FMT_YUV420P:
++ ipu_ch_param_set_field(&params, 1, 85, 4, 2); /* pix format */
++
++ if (uv_stride < stride / 2)
++ uv_stride = stride / 2;
++
++ u_offset = stride * height;
++ v_offset = u_offset + (uv_stride * height / 2);
++ if ((ch == 8) || (ch == 9) || (ch == 10)) {
++ ipu_ch_param_set_field(&params, 1, 78, 7, 15); /* burst size */
++ uv_stride = uv_stride*2;
++ } else {
++ ipu_ch_param_set_field(&params, 1, 78, 7, 63); /* burst size */
++ }
++ break;
++ case IPU_PIX_FMT_YVU420P:
++ ipu_ch_param_set_field(&params, 1, 85, 4, 2); /* pix format */
++
++ if (uv_stride < stride / 2)
++ uv_stride = stride / 2;
++
++ v_offset = stride * height;
++ u_offset = v_offset + (uv_stride * height / 2);
++ if ((ch == 8) || (ch == 9) || (ch == 10)) {
++ ipu_ch_param_set_field(&params, 1, 78, 7, 15); /* burst size */
++ uv_stride = uv_stride*2;
++ } else {
++ ipu_ch_param_set_field(&params, 1, 78, 7, 31); /* burst size */
++ }
++ break;
++ case IPU_PIX_FMT_YVU422P:
++ /* BPP & pixel format */
++ ipu_ch_param_set_field(&params, 1, 85, 4, 1); /* pix format */
++ ipu_ch_param_set_field(&params, 1, 78, 7, 31); /* burst size */
++
++ if (uv_stride < stride / 2)
++ uv_stride = stride / 2;
++
++ v_offset = (v == 0) ? stride * height : v;
++ u_offset = (u == 0) ? v_offset + v_offset / 2 : u;
++ break;
++ case IPU_PIX_FMT_YUV422P:
++ /* BPP & pixel format */
++ ipu_ch_param_set_field(&params, 1, 85, 4, 1); /* pix format */
++ ipu_ch_param_set_field(&params, 1, 78, 7, 31); /* burst size */
++
++ if (uv_stride < stride / 2)
++ uv_stride = stride / 2;
++
++ u_offset = (u == 0) ? stride * height : u;
++ v_offset = (v == 0) ? u_offset + u_offset / 2 : v;
++ break;
++ case IPU_PIX_FMT_YUV444P:
++ /* BPP & pixel format */
++ ipu_ch_param_set_field(&params, 1, 85, 4, 0); /* pix format */
++ ipu_ch_param_set_field(&params, 1, 78, 7, 31); /* burst size */
++ uv_stride = stride;
++ u_offset = (u == 0) ? stride * height : u;
++ v_offset = (v == 0) ? u_offset * 2 : v;
++ break;
++ case IPU_PIX_FMT_NV12:
++ /* BPP & pixel format */
++ ipu_ch_param_set_field(&params, 1, 85, 4, 4); /* pix format */
++ uv_stride = stride;
++ u_offset = (u == 0) ? stride * height : u;
++ if ((ch == 8) || (ch == 9) || (ch == 10)) {
++ if (ipu->vdoa_en) {
++ /* one field buffer, memory width 64bits */
++ ipu_ch_param_set_field(&params, 1, 78, 7, 63);
++ } else {
++ ipu_ch_param_set_field(&params, 1, 78, 7, 15);
++ /* top/bottom field in one buffer*/
++ uv_stride = uv_stride*2;
++ }
++ } else {
++ ipu_ch_param_set_field(&params, 1, 78, 7, 31); /* burst size */
++ }
++ break;
++ default:
++ dev_err(ipu->dev, "mxc ipu: unimplemented pixel format\n");
++ break;
++ }
++ /*set burst size to 16*/
++
++
++ if (uv_stride)
++ ipu_ch_param_set_field(&params, 1, 128, 14, uv_stride - 1);
++
++ /* Get the uv offset from user when need cropping */
++ if (u || v) {
++ u_offset = u;
++ v_offset = v;
++ }
++
++ /* UBO and VBO are 22-bit and 8-byte aligned */
++ if (u_offset/8 > 0x3fffff)
++ dev_warn(ipu->dev,
++ "IDMAC%d's U offset exceeds IPU limitation\n", ch);
++ if (v_offset/8 > 0x3fffff)
++ dev_warn(ipu->dev,
++ "IDMAC%d's V offset exceeds IPU limitation\n", ch);
++ if (u_offset%8)
++ dev_warn(ipu->dev,
++ "IDMAC%d's U offset is not 8-byte aligned\n", ch);
++ if (v_offset%8)
++ dev_warn(ipu->dev,
++ "IDMAC%d's V offset is not 8-byte aligned\n", ch);
++
++ ipu_ch_param_set_field(&params, 0, 46, 22, u_offset / 8);
++ ipu_ch_param_set_field(&params, 0, 68, 22, v_offset / 8);
++
++ dev_dbg(ipu->dev, "initializing idma ch %d @ %p\n", ch, ipu_ch_param_addr(ipu, ch));
++ fill_cpmem(ipu, ch, &params);
++ if (addr2) {
++ sub_ch = __ipu_ch_get_third_buf_cpmem_num(ch);
++ if (sub_ch <= 0)
++ return;
++
++ ipu_ch_param_set_field(&params, 1, 0, 29, addr2 >> 3);
++ ipu_ch_param_set_field(&params, 1, 29, 29, 0);
++ if (addr2%8)
++ dev_warn(ipu->dev,
++ "IDMAC%d's sub-CPMEM entry%d EBA0 is not "
++ "8-byte aligned\n", ch, sub_ch);
++
++ dev_dbg(ipu->dev, "initializing idma ch %d @ %p sub cpmem\n", ch,
++ ipu_ch_param_addr(ipu, sub_ch));
++ fill_cpmem(ipu, sub_ch, &params);
++ }
++};
++
++static inline void _ipu_ch_param_set_burst_size(struct ipu_soc *ipu,
++ uint32_t ch,
++ uint16_t burst_pixels)
++{
++ int32_t sub_ch = 0;
++
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, ch), 1, 78, 7,
++ burst_pixels - 1);
++
++ sub_ch = __ipu_ch_get_third_buf_cpmem_num(ch);
++ if (sub_ch <= 0)
++ return;
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, sub_ch), 1, 78, 7,
++ burst_pixels - 1);
++};
++
++static inline int _ipu_ch_param_get_burst_size(struct ipu_soc *ipu, uint32_t ch)
++{
++ return ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 1, 78, 7) + 1;
++};
++
++static inline int _ipu_ch_param_get_bpp(struct ipu_soc *ipu, uint32_t ch)
++{
++ return ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 0, 107, 3);
++};
++
++static inline void _ipu_ch_param_set_buffer(struct ipu_soc *ipu, uint32_t ch,
++ int bufNum, dma_addr_t phyaddr)
++{
++ if (bufNum == 2) {
++ ch = __ipu_ch_get_third_buf_cpmem_num(ch);
++ if (ch <= 0)
++ return;
++ bufNum = 0;
++ }
++
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, ch), 1, 29 * bufNum, 29,
++ phyaddr / 8);
++};
++
++static inline void _ipu_ch_param_set_rotation(struct ipu_soc *ipu, uint32_t ch,
++ ipu_rotate_mode_t rot)
++{
++ u32 temp_rot = bitrev8(rot) >> 5;
++ int32_t sub_ch = 0;
++
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, ch), 0, 119, 3, temp_rot);
++
++ sub_ch = __ipu_ch_get_third_buf_cpmem_num(ch);
++ if (sub_ch <= 0)
++ return;
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, sub_ch), 0, 119, 3, temp_rot);
++};
++
++static inline void _ipu_ch_param_set_block_mode(struct ipu_soc *ipu, uint32_t ch)
++{
++ int32_t sub_ch = 0;
++
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, ch), 0, 117, 2, 1);
++
++ sub_ch = __ipu_ch_get_third_buf_cpmem_num(ch);
++ if (sub_ch <= 0)
++ return;
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, sub_ch), 0, 117, 2, 1);
++};
++
++static inline void _ipu_ch_param_set_alpha_use_separate_channel(struct ipu_soc *ipu,
++ uint32_t ch,
++ bool option)
++{
++ int32_t sub_ch = 0;
++
++ if (option) {
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, ch), 1, 89, 1, 1);
++ } else {
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, ch), 1, 89, 1, 0);
++ }
++
++ sub_ch = __ipu_ch_get_third_buf_cpmem_num(ch);
++ if (sub_ch <= 0)
++ return;
++
++ if (option) {
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, sub_ch), 1, 89, 1, 1);
++ } else {
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, sub_ch), 1, 89, 1, 0);
++ }
++};
++
++static inline void _ipu_ch_param_set_alpha_condition_read(struct ipu_soc *ipu, uint32_t ch)
++{
++ int32_t sub_ch = 0;
++
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, ch), 1, 149, 1, 1);
++
++ sub_ch = __ipu_ch_get_third_buf_cpmem_num(ch);
++ if (sub_ch <= 0)
++ return;
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, sub_ch), 1, 149, 1, 1);
++};
++
++static inline void _ipu_ch_param_set_alpha_buffer_memory(struct ipu_soc *ipu, uint32_t ch)
++{
++ int alp_mem_idx;
++ int32_t sub_ch = 0;
++
++ switch (ch) {
++ case 14: /* PRP graphic */
++ alp_mem_idx = 0;
++ break;
++ case 15: /* PP graphic */
++ alp_mem_idx = 1;
++ break;
++ case 23: /* DP BG SYNC graphic */
++ alp_mem_idx = 4;
++ break;
++ case 27: /* DP FG SYNC graphic */
++ alp_mem_idx = 2;
++ break;
++ default:
++ dev_err(ipu->dev, "unsupported correlative channel of local "
++ "alpha channel\n");
++ return;
++ }
++
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, ch), 1, 90, 3, alp_mem_idx);
++
++ sub_ch = __ipu_ch_get_third_buf_cpmem_num(ch);
++ if (sub_ch <= 0)
++ return;
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, sub_ch), 1, 90, 3, alp_mem_idx);
++};
++
++static inline void _ipu_ch_param_set_interlaced_scan(struct ipu_soc *ipu, uint32_t ch)
++{
++ u32 stride;
++ int32_t sub_ch = 0;
++
++ sub_ch = __ipu_ch_get_third_buf_cpmem_num(ch);
++
++ ipu_ch_param_set_field_io(ipu_ch_param_addr(ipu, ch), 0, 113, 1, 1);
++ if (sub_ch > 0)
++ ipu_ch_param_set_field_io(ipu_ch_param_addr(ipu, sub_ch), 0, 113, 1, 1);
++ stride = ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 1, 102, 14) + 1;
++ /* ILO is 20-bit and 8-byte aligned */
++ if (stride/8 > 0xfffff)
++ dev_warn(ipu->dev,
++ "IDMAC%d's ILO exceeds IPU limitation\n", ch);
++ if (stride%8)
++ dev_warn(ipu->dev,
++ "IDMAC%d's ILO is not 8-byte aligned\n", ch);
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, ch), 1, 58, 20, stride / 8);
++ if (sub_ch > 0)
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, sub_ch), 1, 58, 20,
++ stride / 8);
++ stride *= 2;
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, ch), 1, 102, 14, stride - 1);
++ if (sub_ch > 0)
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, sub_ch), 1, 102, 14,
++ stride - 1);
++};
++
++static inline void _ipu_ch_param_set_axi_id(struct ipu_soc *ipu, uint32_t ch, uint32_t id)
++{
++ int32_t sub_ch = 0;
++
++ id %= 4;
++
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, ch), 1, 93, 2, id);
++
++ sub_ch = __ipu_ch_get_third_buf_cpmem_num(ch);
++ if (sub_ch <= 0)
++ return;
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, sub_ch), 1, 93, 2, id);
++};
++
++/* IDMAC U/V offset changing support */
++/* U and V input is not affected, */
++/* the update is done by new calculation according to */
++/* vertical_offset and horizontal_offset */
++static inline void _ipu_ch_offset_update(struct ipu_soc *ipu,
++ int ch,
++ uint32_t pixel_fmt,
++ uint32_t width,
++ uint32_t height,
++ uint32_t stride,
++ uint32_t u,
++ uint32_t v,
++ uint32_t uv_stride,
++ uint32_t vertical_offset,
++ uint32_t horizontal_offset)
++{
++ uint32_t u_offset = 0;
++ uint32_t v_offset = 0;
++ uint32_t old_offset = 0;
++ uint32_t u_fix = 0;
++ uint32_t v_fix = 0;
++ int32_t sub_ch = 0;
++
++ switch (pixel_fmt) {
++ case IPU_PIX_FMT_GENERIC:
++ case IPU_PIX_FMT_GENERIC_16:
++ case IPU_PIX_FMT_GENERIC_32:
++ case IPU_PIX_FMT_RGB565:
++ case IPU_PIX_FMT_BGR24:
++ case IPU_PIX_FMT_RGB24:
++ case IPU_PIX_FMT_YUV444:
++ case IPU_PIX_FMT_BGRA32:
++ case IPU_PIX_FMT_BGR32:
++ case IPU_PIX_FMT_RGBA32:
++ case IPU_PIX_FMT_RGB32:
++ case IPU_PIX_FMT_ABGR32:
++ case IPU_PIX_FMT_UYVY:
++ case IPU_PIX_FMT_YUYV:
++ break;
++
++ case IPU_PIX_FMT_YUV420P2:
++ case IPU_PIX_FMT_YUV420P:
++ if (uv_stride < stride / 2)
++ uv_stride = stride / 2;
++
++ u_offset = stride * (height - vertical_offset - 1) +
++ (stride - horizontal_offset) +
++ (uv_stride * vertical_offset / 2) +
++ horizontal_offset / 2;
++ v_offset = u_offset + (uv_stride * height / 2);
++ u_fix = u ? (u + (uv_stride * vertical_offset / 2) +
++ (horizontal_offset / 2) -
++ (stride * vertical_offset) - (horizontal_offset)) :
++ u_offset;
++ v_fix = v ? (v + (uv_stride * vertical_offset / 2) +
++ (horizontal_offset / 2) -
++ (stride * vertical_offset) - (horizontal_offset)) :
++ v_offset;
++
++ break;
++ case IPU_PIX_FMT_YVU420P:
++ if (uv_stride < stride / 2)
++ uv_stride = stride / 2;
++
++ v_offset = stride * (height - vertical_offset - 1) +
++ (stride - horizontal_offset) +
++ (uv_stride * vertical_offset / 2) +
++ horizontal_offset / 2;
++ u_offset = v_offset + (uv_stride * height / 2);
++ u_fix = u ? (u + (uv_stride * vertical_offset / 2) +
++ (horizontal_offset / 2) -
++ (stride * vertical_offset) - (horizontal_offset)) :
++ u_offset;
++ v_fix = v ? (v + (uv_stride * vertical_offset / 2) +
++ (horizontal_offset / 2) -
++ (stride * vertical_offset) - (horizontal_offset)) :
++ v_offset;
++
++ break;
++ case IPU_PIX_FMT_YVU422P:
++ if (uv_stride < stride / 2)
++ uv_stride = stride / 2;
++
++ v_offset = stride * (height - vertical_offset - 1) +
++ (stride - horizontal_offset) +
++ (uv_stride * vertical_offset) +
++ horizontal_offset / 2;
++ u_offset = v_offset + uv_stride * height;
++ u_fix = u ? (u + (uv_stride * vertical_offset) +
++ horizontal_offset / 2 -
++ (stride * vertical_offset) - (horizontal_offset)) :
++ u_offset;
++ v_fix = v ? (v + (uv_stride * vertical_offset) +
++ horizontal_offset / 2 -
++ (stride * vertical_offset) - (horizontal_offset)) :
++ v_offset;
++ break;
++ case IPU_PIX_FMT_YUV422P:
++ if (uv_stride < stride / 2)
++ uv_stride = stride / 2;
++
++ u_offset = stride * (height - vertical_offset - 1) +
++ (stride - horizontal_offset) +
++ (uv_stride * vertical_offset) +
++ horizontal_offset / 2;
++ v_offset = u_offset + uv_stride * height;
++ u_fix = u ? (u + (uv_stride * vertical_offset) +
++ horizontal_offset / 2 -
++ (stride * vertical_offset) - (horizontal_offset)) :
++ u_offset;
++ v_fix = v ? (v + (uv_stride * vertical_offset) +
++ horizontal_offset / 2 -
++ (stride * vertical_offset) - (horizontal_offset)) :
++ v_offset;
++ break;
++
++ case IPU_PIX_FMT_YUV444P:
++ uv_stride = stride;
++ u_offset = stride * (height - vertical_offset - 1) +
++ (stride - horizontal_offset) +
++ (uv_stride * vertical_offset) +
++ horizontal_offset;
++ v_offset = u_offset + uv_stride * height;
++ u_fix = u ? (u + (uv_stride * vertical_offset) +
++ horizontal_offset -
++ (stride * vertical_offset) -
++ (horizontal_offset)) :
++ u_offset;
++ v_fix = v ? (v + (uv_stride * vertical_offset) +
++ horizontal_offset -
++ (stride * vertical_offset) -
++ (horizontal_offset)) :
++ v_offset;
++ break;
++ case IPU_PIX_FMT_NV12:
++ uv_stride = stride;
++ u_offset = stride * (height - vertical_offset - 1) +
++ (stride - horizontal_offset) +
++ (uv_stride * vertical_offset / 2) +
++ horizontal_offset;
++ u_fix = u ? (u + (uv_stride * vertical_offset / 2) +
++ horizontal_offset -
++ (stride * vertical_offset) - (horizontal_offset)) :
++ u_offset;
++
++ break;
++ default:
++ dev_err(ipu->dev, "mxc ipu: unimplemented pixel format\n");
++ break;
++ }
++
++
++
++ if (u_fix > u_offset)
++ u_offset = u_fix;
++
++ if (v_fix > v_offset)
++ v_offset = v_fix;
++
++ /* UBO and VBO are 22-bit and 8-byte aligned */
++ if (u_offset/8 > 0x3fffff)
++ dev_warn(ipu->dev,
++ "IDMAC%d's U offset exceeds IPU limitation\n", ch);
++ if (v_offset/8 > 0x3fffff)
++ dev_warn(ipu->dev,
++ "IDMAC%d's V offset exceeds IPU limitation\n", ch);
++ if (u_offset%8)
++ dev_warn(ipu->dev,
++ "IDMAC%d's U offset is not 8-byte aligned\n", ch);
++ if (v_offset%8)
++ dev_warn(ipu->dev,
++ "IDMAC%d's V offset is not 8-byte aligned\n", ch);
++
++ old_offset = ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 0, 46, 22);
++ if (old_offset != u_offset / 8)
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, ch), 0, 46, 22, u_offset / 8);
++ old_offset = ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 0, 68, 22);
++ if (old_offset != v_offset / 8)
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, ch), 0, 68, 22, v_offset / 8);
++
++ sub_ch = __ipu_ch_get_third_buf_cpmem_num(ch);
++ if (sub_ch <= 0)
++ return;
++ old_offset = ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, sub_ch), 0, 46, 22);
++ if (old_offset != u_offset / 8)
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, sub_ch), 0, 46, 22, u_offset / 8);
++ old_offset = ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, sub_ch), 0, 68, 22);
++ if (old_offset != v_offset / 8)
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, sub_ch), 0, 68, 22, v_offset / 8);
++};
++
++static inline void _ipu_ch_params_set_alpha_width(struct ipu_soc *ipu, uint32_t ch, int alpha_width)
++{
++ int32_t sub_ch = 0;
++
++ ipu_ch_param_set_field_io(ipu_ch_param_addr(ipu, ch), 1, 125, 3, alpha_width - 1);
++
++ sub_ch = __ipu_ch_get_third_buf_cpmem_num(ch);
++ if (sub_ch <= 0)
++ return;
++ ipu_ch_param_set_field_io(ipu_ch_param_addr(ipu, sub_ch), 1, 125, 3, alpha_width - 1);
++};
++
++static inline void _ipu_ch_param_set_bandmode(struct ipu_soc *ipu,
++ uint32_t ch, uint32_t band_height)
++{
++ int32_t sub_ch = 0;
++
++ ipu_ch_param_set_field_io(ipu_ch_param_addr(ipu, ch),
++ 0, 114, 3, band_height - 1);
++ sub_ch = __ipu_ch_get_third_buf_cpmem_num(ch);
++ if (sub_ch <= 0)
++ return;
++ ipu_ch_param_set_field_io(ipu_ch_param_addr(ipu, sub_ch),
++ 0, 114, 3, band_height - 1);
++
++ dev_dbg(ipu->dev, "BNDM 0x%x, ",
++ ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 0, 114, 3));
++}
++
++/*
++ * The IPUv3 IDMAC has a bug to read 32bpp pixels from a graphics plane
++ * whose alpha component is at the most significant 8 bits. The bug only
++ * impacts on cases in which the relevant separate alpha channel is enabled.
++ *
++ * Return true on bad alpha component position, otherwise, return false.
++ */
++static inline bool _ipu_ch_param_bad_alpha_pos(uint32_t pixel_fmt)
++{
++ switch (pixel_fmt) {
++ case IPU_PIX_FMT_BGRA32:
++ case IPU_PIX_FMT_BGR32:
++ case IPU_PIX_FMT_RGBA32:
++ case IPU_PIX_FMT_RGB32:
++ return true;
++ }
++
++ return false;
++}
++#endif
+diff -Nur linux-4.1.3/drivers/mxc/ipu3/ipu_pixel_clk.c linux-xbian-imx6/drivers/mxc/ipu3/ipu_pixel_clk.c
+--- linux-4.1.3/drivers/mxc/ipu3/ipu_pixel_clk.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/ipu3/ipu_pixel_clk.c 2015-07-27 23:13:06.226765901 +0200
+@@ -0,0 +1,317 @@
++/*
++ * Copyright (C) 2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*!
++ * @file ipu_pixel_clk.c
++ *
++ * @brief IPU pixel clock implementation
++ *
++ * @ingroup IPU
++ */
++
++#include <linux/clk-provider.h>
++#include <linux/err.h>
++#include <linux/io.h>
++#include <linux/ipu-v3.h>
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <linux/string.h>
++
++#include "ipu_prv.h"
++#include "ipu_regs.h"
++
++ /*
++ * muxd clock implementation
++ */
++struct clk_di_mux {
++ struct clk_hw hw;
++ u8 ipu_id;
++ u8 di_id;
++ u8 flags;
++ u8 index;
++};
++#define to_clk_di_mux(_hw) container_of(_hw, struct clk_di_mux, hw)
++
++static int _ipu_pixel_clk_set_parent(struct clk_hw *hw, u8 index)
++{
++ struct clk_di_mux *mux = to_clk_di_mux(hw);
++ struct ipu_soc *ipu = ipu_get_soc(mux->ipu_id);
++ u32 di_gen;
++
++ di_gen = ipu_di_read(ipu, mux->di_id, DI_GENERAL);
++ if (index == 0)
++ /* ipu1_clk or ipu2_clk internal clk */
++ di_gen &= ~DI_GEN_DI_CLK_EXT;
++ else
++ di_gen |= DI_GEN_DI_CLK_EXT;
++
++ ipu_di_write(ipu, mux->di_id, di_gen, DI_GENERAL);
++ mux->index = index;
++ pr_debug("ipu_pixel_clk: di_clk_ext:0x%x, di_gen reg:0x%x.\n",
++ !(di_gen & DI_GEN_DI_CLK_EXT), di_gen);
++ return 0;
++}
++
++static u8 _ipu_pixel_clk_get_parent(struct clk_hw *hw)
++{
++ struct clk_di_mux *mux = to_clk_di_mux(hw);
++
++ return mux->index;
++}
++
++const struct clk_ops clk_mux_di_ops = {
++ .get_parent = _ipu_pixel_clk_get_parent,
++ .set_parent = _ipu_pixel_clk_set_parent,
++};
++
++struct clk *clk_register_mux_pix_clk(struct device *dev, const char *name,
++ const char **parent_names, u8 num_parents, unsigned long flags,
++ u8 ipu_id, u8 di_id, u8 clk_mux_flags)
++{
++ struct clk_di_mux *mux;
++ struct clk *clk;
++ struct clk_init_data init;
++
++ mux = kzalloc(sizeof(struct clk_di_mux), GFP_KERNEL);
++ if (!mux)
++ return ERR_PTR(-ENOMEM);
++
++ init.name = name;
++ init.ops = &clk_mux_di_ops;
++ init.flags = flags;
++ init.parent_names = parent_names;
++ init.num_parents = num_parents;
++
++ mux->ipu_id = ipu_id;
++ mux->di_id = di_id;
++ mux->flags = clk_mux_flags | CLK_SET_RATE_PARENT;
++ mux->hw.init = &init;
++
++ clk = clk_register(dev, &mux->hw);
++ if (IS_ERR(clk))
++ kfree(mux);
++
++ return clk;
++}
++
++/*
++ * Gated clock implementation
++ */
++struct clk_di_div {
++ struct clk_hw hw;
++ u8 ipu_id;
++ u8 di_id;
++ u8 flags;
++};
++#define to_clk_di_div(_hw) container_of(_hw, struct clk_di_div, hw)
++
++static unsigned long _ipu_pixel_clk_div_recalc_rate(struct clk_hw *hw,
++ unsigned long parent_rate)
++{
++ struct clk_di_div *di_div = to_clk_di_div(hw);
++ struct ipu_soc *ipu = ipu_get_soc(di_div->ipu_id);
++ u32 div;
++ u64 final_rate = (unsigned long long)parent_rate * 16;
++
++ _ipu_get(ipu);
++ div = ipu_di_read(ipu, di_div->di_id, DI_BS_CLKGEN0);
++ _ipu_put(ipu);
++ pr_debug("ipu_di%d read BS_CLKGEN0 div:%d, final_rate:%lld, prate:%ld\n",
++ di_div->di_id, div, final_rate, parent_rate);
++
++ if (div == 0)
++ return 0;
++ do_div(final_rate, div);
++
++ return (unsigned long)final_rate;
++}
++
++static long _ipu_pixel_clk_div_round_rate(struct clk_hw *hw, unsigned long rate,
++ unsigned long *parent_clk_rate)
++{
++ u64 div, final_rate;
++ u32 remainder;
++ u64 parent_rate = (unsigned long long)(*parent_clk_rate) * 16;
++
++ /*
++ * Calculate divider
++ * Fractional part is 4 bits,
++ * so simply multiply by 2^4 to get fractional part.
++ */
++ div = parent_rate;
++ remainder = do_div(div, rate);
++ /* Round the divider value */
++ if (remainder > (rate/2))
++ div++;
++ if (div < 0x10) /* Min DI disp clock divider is 1 */
++ div = 0x10;
++ if (div & ~0xFEF)
++ div &= 0xFF8;
++ else {
++ /* Round up divider if it gets us closer to desired pix clk */
++ if ((div & 0xC) == 0xC) {
++ div += 0x10;
++ div &= ~0xF;
++ }
++ }
++ final_rate = parent_rate;
++ do_div(final_rate, div);
++
++ return final_rate;
++}
++
++static int _ipu_pixel_clk_div_set_rate(struct clk_hw *hw, unsigned long rate,
++ unsigned long parent_clk_rate)
++{
++ struct clk_di_div *di_div = to_clk_di_div(hw);
++ struct ipu_soc *ipu = ipu_get_soc(di_div->ipu_id);
++ u64 div, parent_rate;
++ u32 remainder;
++
++ parent_rate = (unsigned long long)parent_clk_rate * 16;
++ div = parent_rate;
++ remainder = do_div(div, rate);
++ /* Round the divider value */
++ if (remainder > (rate/2))
++ div++;
++
++ /* Round up divider if it gets us closer to desired pix clk */
++ if ((div & 0xC) == 0xC) {
++ div += 0x10;
++ div &= ~0xF;
++ }
++ if (div > 0x1000)
++ pr_err("Overflow, di:%d, DI_BS_CLKGEN0 div:0x%x\n",
++ di_div->di_id, (u32)div);
++ _ipu_get(ipu);
++ ipu_di_write(ipu, di_div->di_id, (u32)div, DI_BS_CLKGEN0);
++
++ /* Setup pixel clock timing */
++ /* FIXME: needs to be more flexible */
++ /* Down time is half of period */
++ ipu_di_write(ipu, di_div->di_id, ((u32)div / 16) << 16, DI_BS_CLKGEN1);
++ _ipu_put(ipu);
++
++ return 0;
++}
++
++static struct clk_ops clk_div_ops = {
++ .recalc_rate = _ipu_pixel_clk_div_recalc_rate,
++ .round_rate = _ipu_pixel_clk_div_round_rate,
++ .set_rate = _ipu_pixel_clk_div_set_rate,
++};
++
++struct clk *clk_register_div_pix_clk(struct device *dev, const char *name,
++ const char *parent_name, unsigned long flags,
++ u8 ipu_id, u8 di_id, u8 clk_div_flags)
++{
++ struct clk_di_div *di_div;
++ struct clk *clk;
++ struct clk_init_data init;
++
++ di_div = kzalloc(sizeof(struct clk_di_div), GFP_KERNEL);
++ if (!di_div)
++ return ERR_PTR(-ENOMEM);
++
++ /* struct clk_di_div assignments */
++ di_div->ipu_id = ipu_id;
++ di_div->di_id = di_id;
++ di_div->flags = clk_div_flags;
++
++ init.name = name;
++ init.ops = &clk_div_ops;
++ init.flags = flags | CLK_SET_RATE_PARENT;
++ init.parent_names = parent_name ? &parent_name : NULL;
++ init.num_parents = parent_name ? 1 : 0;
++
++ di_div->hw.init = &init;
++
++ clk = clk_register(dev, &di_div->hw);
++ if (IS_ERR(clk))
++ kfree(clk);
++
++ return clk;
++}
++
++/*
++ * Gated clock implementation
++ */
++struct clk_di_gate {
++ struct clk_hw hw;
++ u8 ipu_id;
++ u8 di_id;
++ u8 flags;
++};
++#define to_clk_di_gate(_hw) container_of(_hw, struct clk_di_gate, hw)
++
++static int _ipu_pixel_clk_enable(struct clk_hw *hw)
++{
++ struct clk_di_gate *gate = to_clk_di_gate(hw);
++ struct ipu_soc *ipu = ipu_get_soc(gate->ipu_id);
++ u32 disp_gen;
++
++ disp_gen = ipu_cm_read(ipu, IPU_DISP_GEN);
++ disp_gen |= gate->di_id ? DI1_COUNTER_RELEASE : DI0_COUNTER_RELEASE;
++ ipu_cm_write(ipu, disp_gen, IPU_DISP_GEN);
++
++ return 0;
++}
++
++static void _ipu_pixel_clk_disable(struct clk_hw *hw)
++{
++ struct clk_di_gate *gate = to_clk_di_gate(hw);
++ struct ipu_soc *ipu = ipu_get_soc(gate->ipu_id);
++ u32 disp_gen;
++
++ disp_gen = ipu_cm_read(ipu, IPU_DISP_GEN);
++ disp_gen &= gate->di_id ? ~DI1_COUNTER_RELEASE : ~DI0_COUNTER_RELEASE;
++ ipu_cm_write(ipu, disp_gen, IPU_DISP_GEN);
++
++}
++
++
++static struct clk_ops clk_gate_di_ops = {
++ .enable = _ipu_pixel_clk_enable,
++ .disable = _ipu_pixel_clk_disable,
++};
++
++struct clk *clk_register_gate_pix_clk(struct device *dev, const char *name,
++ const char *parent_name, unsigned long flags,
++ u8 ipu_id, u8 di_id, u8 clk_gate_flags)
++{
++ struct clk_di_gate *gate;
++ struct clk *clk;
++ struct clk_init_data init;
++
++ gate = kzalloc(sizeof(struct clk_di_gate), GFP_KERNEL);
++ if (!gate)
++ return ERR_PTR(-ENOMEM);
++
++ gate->ipu_id = ipu_id;
++ gate->di_id = di_id;
++ gate->flags = clk_gate_flags;
++
++ init.name = name;
++ init.ops = &clk_gate_di_ops;
++ init.flags = flags | CLK_SET_RATE_PARENT;
++ init.parent_names = parent_name ? &parent_name : NULL;
++ init.num_parents = parent_name ? 1 : 0;
++
++ gate->hw.init = &init;
++
++ clk = clk_register(dev, &gate->hw);
++ if (IS_ERR(clk))
++ kfree(clk);
++
++ return clk;
++}
+diff -Nur linux-4.1.3/drivers/mxc/ipu3/ipu_prv.h linux-xbian-imx6/drivers/mxc/ipu3/ipu_prv.h
+--- linux-4.1.3/drivers/mxc/ipu3/ipu_prv.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/ipu3/ipu_prv.h 2015-07-27 23:13:06.226765901 +0200
+@@ -0,0 +1,363 @@
++/*
++ * Copyright 2005-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++#ifndef __INCLUDE_IPU_PRV_H__
++#define __INCLUDE_IPU_PRV_H__
++
++#include <linux/clkdev.h>
++#include <linux/device.h>
++#include <linux/fsl_devices.h>
++#include <linux/interrupt.h>
++#include <linux/types.h>
++
++#define MXC_IPU_MAX_NUM 2
++#define MXC_DI_NUM_PER_IPU 2
++
++/* Globals */
++extern int dmfc_type_setup;
++
++#define IDMA_CHAN_INVALID 0xFF
++#define HIGH_RESOLUTION_WIDTH 1024
++
++struct ipu_irq_node {
++ irqreturn_t(*handler) (int, void *); /*!< the ISR */
++ const char *name; /*!< device associated with the interrupt */
++ void *dev_id; /*!< some unique information for the ISR */
++ __u32 flags; /*!< not used */
++};
++
++enum csc_type_t {
++ RGB2YUV = 0,
++ YUV2RGB,
++ RGB2RGB,
++ YUV2YUV,
++ CSC_NONE,
++ CSC_NUM
++};
++
++enum imx_ipu_type {
++ IMX6Q_IPU,
++};
++
++struct ipu_pltfm_data {
++ u32 id;
++ u32 devtype;
++ int (*init) (int);
++ void (*pg) (int);
++
++ /*
++ * Bypass reset to avoid display channel being
++ * stopped by probe since it may starts to work
++ * in bootloader.
++ */
++ bool bypass_reset;
++};
++
++struct ipu_soc {
++ bool online;
++ struct ipu_pltfm_data *pdata;
++
++ /*clk*/
++ struct clk *ipu_clk;
++ struct clk *di_clk[2];
++ struct clk *di_clk_sel[2];
++ struct clk *pixel_clk[2];
++ struct clk *pixel_clk_sel[2];
++ struct clk *csi_clk[2];
++
++ /*irq*/
++ int irq_sync;
++ int irq_err;
++ struct ipu_irq_node irq_list[IPU_IRQ_COUNT];
++
++ /*reg*/
++ void __iomem *cm_reg;
++ void __iomem *idmac_reg;
++ void __iomem *dp_reg;
++ void __iomem *ic_reg;
++ void __iomem *dc_reg;
++ void __iomem *dc_tmpl_reg;
++ void __iomem *dmfc_reg;
++ void __iomem *di_reg[2];
++ void __iomem *smfc_reg;
++ void __iomem *csi_reg[2];
++ void __iomem *cpmem_base;
++ void __iomem *tpmem_base;
++ void __iomem *disp_base[2];
++ void __iomem *vdi_reg;
++
++ struct device *dev;
++
++ ipu_channel_t csi_channel[2];
++ ipu_channel_t using_ic_dirct_ch;
++ unsigned char dc_di_assignment[10];
++ bool sec_chan_en[24];
++ bool thrd_chan_en[24];
++ bool chan_is_interlaced[52];
++ uint32_t channel_init_mask;
++ uint32_t channel_enable_mask;
++
++ /*use count*/
++ int dc_use_count;
++ int dp_use_count;
++ int dmfc_use_count;
++ int smfc_use_count;
++ int ic_use_count;
++ int rot_use_count;
++ int vdi_use_count;
++ int di_use_count[2];
++ int csi_use_count[2];
++
++ struct mutex mutex_lock;
++ spinlock_t int_reg_spin_lock;
++ spinlock_t rdy_reg_spin_lock;
++
++ int dmfc_size_28;
++ int dmfc_size_29;
++ int dmfc_size_24;
++ int dmfc_size_27;
++ int dmfc_size_23;
++
++ enum csc_type_t fg_csc_type;
++ enum csc_type_t bg_csc_type;
++ bool color_key_4rgb;
++ bool dc_swap;
++ struct completion dc_comp;
++ struct completion csi_comp;
++
++ struct rot_mem {
++ void *vaddr;
++ dma_addr_t paddr;
++ int size;
++ } rot_dma[2];
++
++ int vdoa_en;
++ struct task_struct *thread[2];
++
++ char pixel_clk_0[12];
++ char pixel_clk_1[12];
++ char pixel_clk_0_sel[15];
++ char pixel_clk_1_sel[15];
++ char pixel_clk_0_div[15];
++ char pixel_clk_1_div[15];
++ char ipu_pixel_clk_sel[3][9];
++};
++
++struct ipu_channel {
++ u8 video_in_dma;
++ u8 alpha_in_dma;
++ u8 graph_in_dma;
++ u8 out_dma;
++};
++
++enum ipu_dmfc_type {
++ DMFC_NORMAL = 0,
++ DMFC_HIGH_RESOLUTION_DC,
++ DMFC_HIGH_RESOLUTION_DP,
++ DMFC_HIGH_RESOLUTION_ONLY_DP,
++};
++
++static inline u32 ipu_cm_read(struct ipu_soc *ipu, unsigned offset)
++{
++ return readl(ipu->cm_reg + offset);
++}
++
++static inline void ipu_cm_write(struct ipu_soc *ipu,
++ u32 value, unsigned offset)
++{
++ writel(value, ipu->cm_reg + offset);
++}
++
++static inline u32 ipu_idmac_read(struct ipu_soc *ipu, unsigned offset)
++{
++ return readl(ipu->idmac_reg + offset);
++}
++
++static inline void ipu_idmac_write(struct ipu_soc *ipu,
++ u32 value, unsigned offset)
++{
++ writel(value, ipu->idmac_reg + offset);
++}
++
++static inline u32 ipu_dc_read(struct ipu_soc *ipu, unsigned offset)
++{
++ return readl(ipu->dc_reg + offset);
++}
++
++static inline void ipu_dc_write(struct ipu_soc *ipu,
++ u32 value, unsigned offset)
++{
++ writel(value, ipu->dc_reg + offset);
++}
++
++static inline u32 ipu_dc_tmpl_read(struct ipu_soc *ipu, unsigned offset)
++{
++ return readl(ipu->dc_tmpl_reg + offset);
++}
++
++static inline void ipu_dc_tmpl_write(struct ipu_soc *ipu,
++ u32 value, unsigned offset)
++{
++ writel(value, ipu->dc_tmpl_reg + offset);
++}
++
++static inline u32 ipu_dmfc_read(struct ipu_soc *ipu, unsigned offset)
++{
++ return readl(ipu->dmfc_reg + offset);
++}
++
++static inline void ipu_dmfc_write(struct ipu_soc *ipu,
++ u32 value, unsigned offset)
++{
++ writel(value, ipu->dmfc_reg + offset);
++}
++
++static inline u32 ipu_dp_read(struct ipu_soc *ipu, unsigned offset)
++{
++ return readl(ipu->dp_reg + offset);
++}
++
++static inline void ipu_dp_write(struct ipu_soc *ipu,
++ u32 value, unsigned offset)
++{
++ writel(value, ipu->dp_reg + offset);
++}
++
++static inline u32 ipu_di_read(struct ipu_soc *ipu, int di, unsigned offset)
++{
++ return readl(ipu->di_reg[di] + offset);
++}
++
++static inline void ipu_di_write(struct ipu_soc *ipu, int di,
++ u32 value, unsigned offset)
++{
++ writel(value, ipu->di_reg[di] + offset);
++}
++
++static inline u32 ipu_csi_read(struct ipu_soc *ipu, int csi, unsigned offset)
++{
++ return readl(ipu->csi_reg[csi] + offset);
++}
++
++static inline void ipu_csi_write(struct ipu_soc *ipu, int csi,
++ u32 value, unsigned offset)
++{
++ writel(value, ipu->csi_reg[csi] + offset);
++}
++
++static inline u32 ipu_smfc_read(struct ipu_soc *ipu, unsigned offset)
++{
++ return readl(ipu->smfc_reg + offset);
++}
++
++static inline void ipu_smfc_write(struct ipu_soc *ipu,
++ u32 value, unsigned offset)
++{
++ writel(value, ipu->smfc_reg + offset);
++}
++
++static inline u32 ipu_vdi_read(struct ipu_soc *ipu, unsigned offset)
++{
++ return readl(ipu->vdi_reg + offset);
++}
++
++static inline void ipu_vdi_write(struct ipu_soc *ipu,
++ u32 value, unsigned offset)
++{
++ writel(value, ipu->vdi_reg + offset);
++}
++
++static inline u32 ipu_ic_read(struct ipu_soc *ipu, unsigned offset)
++{
++ return readl(ipu->ic_reg + offset);
++}
++
++static inline void ipu_ic_write(struct ipu_soc *ipu,
++ u32 value, unsigned offset)
++{
++ writel(value, ipu->ic_reg + offset);
++}
++
++int register_ipu_device(struct ipu_soc *ipu, int id);
++void unregister_ipu_device(struct ipu_soc *ipu, int id);
++ipu_color_space_t format_to_colorspace(uint32_t fmt);
++bool ipu_pixel_format_has_alpha(uint32_t fmt);
++
++void ipu_dump_registers(struct ipu_soc *ipu);
++
++uint32_t _ipu_channel_status(struct ipu_soc *ipu, ipu_channel_t channel);
++
++void ipu_disp_init(struct ipu_soc *ipu);
++void _ipu_init_dc_mappings(struct ipu_soc *ipu);
++int _ipu_dp_init(struct ipu_soc *ipu, ipu_channel_t channel, uint32_t in_pixel_fmt,
++ uint32_t out_pixel_fmt);
++void _ipu_dp_uninit(struct ipu_soc *ipu, ipu_channel_t channel);
++void _ipu_dc_init(struct ipu_soc *ipu, int dc_chan, int di, bool interlaced, uint32_t pixel_fmt);
++void _ipu_dc_uninit(struct ipu_soc *ipu, int dc_chan);
++void _ipu_dp_dc_enable(struct ipu_soc *ipu, ipu_channel_t channel);
++void _ipu_dp_dc_disable(struct ipu_soc *ipu, ipu_channel_t channel, bool swap);
++void _ipu_dmfc_init(struct ipu_soc *ipu, int dmfc_type, int first);
++void _ipu_dmfc_set_wait4eot(struct ipu_soc *ipu, int dma_chan, int width);
++void _ipu_dmfc_set_burst_size(struct ipu_soc *ipu, int dma_chan, int burst_size);
++int _ipu_disp_chan_is_interlaced(struct ipu_soc *ipu, ipu_channel_t channel);
++
++void _ipu_ic_enable_task(struct ipu_soc *ipu, ipu_channel_t channel);
++void _ipu_ic_disable_task(struct ipu_soc *ipu, ipu_channel_t channel);
++int _ipu_ic_init_prpvf(struct ipu_soc *ipu, ipu_channel_params_t *params,
++ bool src_is_csi);
++void _ipu_vdi_init(struct ipu_soc *ipu, ipu_channel_t channel, ipu_channel_params_t *params);
++void _ipu_vdi_uninit(struct ipu_soc *ipu);
++void _ipu_ic_uninit_prpvf(struct ipu_soc *ipu);
++void _ipu_ic_init_rotate_vf(struct ipu_soc *ipu, ipu_channel_params_t *params);
++void _ipu_ic_uninit_rotate_vf(struct ipu_soc *ipu);
++void _ipu_ic_init_csi(struct ipu_soc *ipu, ipu_channel_params_t *params);
++void _ipu_ic_uninit_csi(struct ipu_soc *ipu);
++int _ipu_ic_init_prpenc(struct ipu_soc *ipu, ipu_channel_params_t *params,
++ bool src_is_csi);
++void _ipu_ic_uninit_prpenc(struct ipu_soc *ipu);
++void _ipu_ic_init_rotate_enc(struct ipu_soc *ipu, ipu_channel_params_t *params);
++void _ipu_ic_uninit_rotate_enc(struct ipu_soc *ipu);
++int _ipu_ic_init_pp(struct ipu_soc *ipu, ipu_channel_params_t *params);
++void _ipu_ic_uninit_pp(struct ipu_soc *ipu);
++void _ipu_ic_init_rotate_pp(struct ipu_soc *ipu, ipu_channel_params_t *params);
++void _ipu_ic_uninit_rotate_pp(struct ipu_soc *ipu);
++int _ipu_ic_idma_init(struct ipu_soc *ipu, int dma_chan, uint16_t width, uint16_t height,
++ int burst_size, ipu_rotate_mode_t rot);
++void _ipu_vdi_toggle_top_field_man(struct ipu_soc *ipu);
++int _ipu_csi_init(struct ipu_soc *ipu, ipu_channel_t channel, uint32_t csi);
++int _ipu_csi_set_mipi_di(struct ipu_soc *ipu, uint32_t num, uint32_t di_val, uint32_t csi);
++void ipu_csi_set_test_generator(struct ipu_soc *ipu, bool active, uint32_t r_value,
++ uint32_t g_value, uint32_t b_value,
++ uint32_t pix_clk, uint32_t csi);
++void _ipu_csi_ccir_err_detection_enable(struct ipu_soc *ipu, uint32_t csi);
++void _ipu_csi_ccir_err_detection_disable(struct ipu_soc *ipu, uint32_t csi);
++void _ipu_csi_wait4eof(struct ipu_soc *ipu, ipu_channel_t channel);
++void _ipu_smfc_init(struct ipu_soc *ipu, ipu_channel_t channel, uint32_t mipi_id, uint32_t csi);
++void _ipu_smfc_set_burst_size(struct ipu_soc *ipu, ipu_channel_t channel, uint32_t bs);
++void _ipu_dp_set_csc_coefficients(struct ipu_soc *ipu, ipu_channel_t channel, int32_t param[][3]);
++int32_t _ipu_disp_set_window_pos(struct ipu_soc *ipu, ipu_channel_t channel,
++ int16_t x_pos, int16_t y_pos);
++int32_t _ipu_disp_get_window_pos(struct ipu_soc *ipu, ipu_channel_t channel,
++ int16_t *x_pos, int16_t *y_pos);
++void _ipu_get(struct ipu_soc *ipu);
++void _ipu_put(struct ipu_soc *ipu);
++
++struct clk *clk_register_mux_pix_clk(struct device *dev, const char *name,
++ const char **parent_names, u8 num_parents, unsigned long flags,
++ u8 ipu_id, u8 di_id, u8 clk_mux_flags);
++struct clk *clk_register_div_pix_clk(struct device *dev, const char *name,
++ const char *parent_name, unsigned long flags,
++ u8 ipu_id, u8 di_id, u8 clk_div_flags);
++struct clk *clk_register_gate_pix_clk(struct device *dev, const char *name,
++ const char *parent_name, unsigned long flags,
++ u8 ipu_id, u8 di_id, u8 clk_gate_flags);
++#endif /* __INCLUDE_IPU_PRV_H__ */
+diff -Nur linux-4.1.3/drivers/mxc/ipu3/ipu_regs.h linux-xbian-imx6/drivers/mxc/ipu3/ipu_regs.h
+--- linux-4.1.3/drivers/mxc/ipu3/ipu_regs.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/ipu3/ipu_regs.h 2015-07-27 23:13:06.226765901 +0200
+@@ -0,0 +1,749 @@
++/*
++ * Copyright (C) 2005-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*
++ * @file ipu_regs.h
++ *
++ * @brief IPU Register definitions
++ *
++ * @ingroup IPU
++ */
++#ifndef __IPU_REGS_INCLUDED__
++#define __IPU_REGS_INCLUDED__
++
++enum imx_ipu_rev {
++ IPU_V3DEX = 2,
++ IPU_V3M,
++ IPU_V3H,
++};
++
++/*
++ * hw_rev 2: IPUV3DEX
++ * hw_rev 3: IPUV3M
++ * hw_rev 4: IPUV3H
++ */
++extern int g_ipu_hw_rev;
++
++#define IPU_MAX_VDI_IN_WIDTH ({g_ipu_hw_rev >= 3 ? \
++ (968) : \
++ (720); })
++#define IPU_DISP0_BASE 0x00000000
++#define IPU_MCU_T_DEFAULT 8
++#define IPU_DISP1_BASE ({g_ipu_hw_rev < 4 ? \
++ (IPU_MCU_T_DEFAULT << 25) : \
++ (0x00000000); })
++#define IPUV3DEX_REG_BASE 0x1E000000
++#define IPUV3M_REG_BASE 0x06000000
++#define IPUV3H_REG_BASE 0x00200000
++
++#define IPU_CM_REG_BASE 0x00000000
++#define IPU_IDMAC_REG_BASE 0x00008000
++#define IPU_ISP_REG_BASE 0x00010000
++#define IPU_DP_REG_BASE 0x00018000
++#define IPU_IC_REG_BASE 0x00020000
++#define IPU_IRT_REG_BASE 0x00028000
++#define IPU_CSI0_REG_BASE 0x00030000
++#define IPU_CSI1_REG_BASE 0x00038000
++#define IPU_DI0_REG_BASE 0x00040000
++#define IPU_DI1_REG_BASE 0x00048000
++#define IPU_SMFC_REG_BASE 0x00050000
++#define IPU_DC_REG_BASE 0x00058000
++#define IPU_DMFC_REG_BASE 0x00060000
++#define IPU_VDI_REG_BASE 0x00068000
++#define IPU_CPMEM_REG_BASE ({g_ipu_hw_rev >= 4 ? \
++ (0x00100000) : \
++ (0x01000000); })
++#define IPU_LUT_REG_BASE 0x01020000
++#define IPU_SRM_REG_BASE ({g_ipu_hw_rev >= 4 ? \
++ (0x00140000) : \
++ (0x01040000); })
++#define IPU_TPM_REG_BASE ({g_ipu_hw_rev >= 4 ? \
++ (0x00160000) : \
++ (0x01060000); })
++#define IPU_DC_TMPL_REG_BASE ({g_ipu_hw_rev >= 4 ? \
++ (0x00180000) : \
++ (0x01080000); })
++#define IPU_ISP_TBPR_REG_BASE 0x010C0000
++
++/* Register addresses */
++/* IPU Common registers */
++#define IPU_CM_REG(offset) (offset)
++
++#define IPU_CONF IPU_CM_REG(0)
++#define IPU_SRM_PRI1 IPU_CM_REG(0x00A0)
++#define IPU_SRM_PRI2 IPU_CM_REG(0x00A4)
++#define IPU_FS_PROC_FLOW1 IPU_CM_REG(0x00A8)
++#define IPU_FS_PROC_FLOW2 IPU_CM_REG(0x00AC)
++#define IPU_FS_PROC_FLOW3 IPU_CM_REG(0x00B0)
++#define IPU_FS_DISP_FLOW1 IPU_CM_REG(0x00B4)
++#define IPU_FS_DISP_FLOW2 IPU_CM_REG(0x00B8)
++#define IPU_SKIP IPU_CM_REG(0x00BC)
++#define IPU_DISP_ALT_CONF IPU_CM_REG(0x00C0)
++#define IPU_DISP_GEN IPU_CM_REG(0x00C4)
++#define IPU_DISP_ALT1 IPU_CM_REG(0x00C8)
++#define IPU_DISP_ALT2 IPU_CM_REG(0x00CC)
++#define IPU_DISP_ALT3 IPU_CM_REG(0x00D0)
++#define IPU_DISP_ALT4 IPU_CM_REG(0x00D4)
++#define IPU_SNOOP IPU_CM_REG(0x00D8)
++#define IPU_MEM_RST IPU_CM_REG(0x00DC)
++#define IPU_PM IPU_CM_REG(0x00E0)
++#define IPU_GPR IPU_CM_REG(0x00E4)
++#define IPU_CHA_DB_MODE_SEL(ch) IPU_CM_REG(0x0150 + 4 * ((ch) / 32))
++#define IPU_ALT_CHA_DB_MODE_SEL(ch) IPU_CM_REG(0x0168 + 4 * ((ch) / 32))
++/*
++ * IPUv3D doesn't support triple buffer, so point
++ * IPU_CHA_TRB_MODE_SEL, IPU_CHA_TRIPLE_CUR_BUF and
++ * IPU_CHA_BUF2_RDY to readonly
++ * IPU_ALT_CUR_BUF0 for IPUv3D.
++ */
++#define IPU_CHA_TRB_MODE_SEL(ch) IPU_CM_REG({g_ipu_hw_rev >= 2 ? \
++ (0x0178 + 4 * ((ch) / 32)) : \
++ (0x012C); })
++#define IPU_CHA_TRIPLE_CUR_BUF(ch) IPU_CM_REG({g_ipu_hw_rev >= 2 ? \
++ (0x0258 + \
++ 4 * (((ch) * 2) / 32)) : \
++ (0x012C); })
++#define IPU_CHA_BUF2_RDY(ch) IPU_CM_REG({g_ipu_hw_rev >= 2 ? \
++ (0x0288 + 4 * ((ch) / 32)) : \
++ (0x012C); })
++#define IPU_CHA_CUR_BUF(ch) IPU_CM_REG({g_ipu_hw_rev >= 2 ? \
++ (0x023C + 4 * ((ch) / 32)) : \
++ (0x0124 + 4 * ((ch) / 32)); })
++#define IPU_ALT_CUR_BUF0 IPU_CM_REG({g_ipu_hw_rev >= 2 ? \
++ (0x0244) : \
++ (0x012C); })
++#define IPU_ALT_CUR_BUF1 IPU_CM_REG({g_ipu_hw_rev >= 2 ? \
++ (0x0248) : \
++ (0x0130); })
++#define IPU_SRM_STAT IPU_CM_REG({g_ipu_hw_rev >= 2 ? \
++ (0x024C) : \
++ (0x0134); })
++#define IPU_PROC_TASK_STAT IPU_CM_REG({g_ipu_hw_rev >= 2 ? \
++ (0x0250) : \
++ (0x0138); })
++#define IPU_DISP_TASK_STAT IPU_CM_REG({g_ipu_hw_rev >= 2 ? \
++ (0x0254) : \
++ (0x013C); })
++#define IPU_CHA_BUF0_RDY(ch) IPU_CM_REG({g_ipu_hw_rev >= 2 ? \
++ (0x0268 + 4 * ((ch) / 32)) : \
++ (0x0140 + 4 * ((ch) / 32)); })
++#define IPU_CHA_BUF1_RDY(ch) IPU_CM_REG({g_ipu_hw_rev >= 2 ? \
++ (0x0270 + 4 * ((ch) / 32)) : \
++ (0x0148 + 4 * ((ch) / 32)); })
++#define IPU_ALT_CHA_BUF0_RDY(ch) IPU_CM_REG({g_ipu_hw_rev >= 2 ? \
++ (0x0278 + 4 * ((ch) / 32)) : \
++ (0x0158 + 4 * ((ch) / 32)); })
++#define IPU_ALT_CHA_BUF1_RDY(ch) IPU_CM_REG({g_ipu_hw_rev >= 2 ? \
++ (0x0280 + 4 * ((ch) / 32)) : \
++ (0x0160 + 4 * ((ch) / 32)); })
++
++#define IPU_INT_CTRL(n) IPU_CM_REG(0x003C + 4 * ((n) - 1))
++#define IPU_INT_STAT(n) IPU_CM_REG({g_ipu_hw_rev >= 2 ? \
++ (0x0200 + 4 * ((n) - 1)) : \
++ (0x00E8 + 4 * ((n) - 1)); })
++
++#define IPUIRQ_2_STATREG(irq) IPU_CM_REG(IPU_INT_STAT(1) + 4 * ((irq) / 32))
++#define IPUIRQ_2_CTRLREG(irq) IPU_CM_REG(IPU_INT_CTRL(1) + 4 * ((irq) / 32))
++#define IPUIRQ_2_MASK(irq) (1UL << ((irq) & 0x1F))
++
++/* IPU VDI registers */
++#define IPU_VDI_REG(offset) (offset)
++
++#define VDI_FSIZE IPU_VDI_REG(0)
++#define VDI_C IPU_VDI_REG(0x0004)
++
++/* IPU CSI Registers */
++#define IPU_CSI_REG(offset) (offset)
++
++#define CSI_SENS_CONF IPU_CSI_REG(0)
++#define CSI_SENS_FRM_SIZE IPU_CSI_REG(0x0004)
++#define CSI_ACT_FRM_SIZE IPU_CSI_REG(0x0008)
++#define CSI_OUT_FRM_CTRL IPU_CSI_REG(0x000C)
++#define CSI_TST_CTRL IPU_CSI_REG(0x0010)
++#define CSI_CCIR_CODE_1 IPU_CSI_REG(0x0014)
++#define CSI_CCIR_CODE_2 IPU_CSI_REG(0x0018)
++#define CSI_CCIR_CODE_3 IPU_CSI_REG(0x001C)
++#define CSI_MIPI_DI IPU_CSI_REG(0x0020)
++#define CSI_SKIP IPU_CSI_REG(0x0024)
++#define CSI_CPD_CTRL IPU_CSI_REG(0x0028)
++#define CSI_CPD_RC(n) IPU_CSI_REG(0x002C + 4 * (n))
++#define CSI_CPD_RS(n) IPU_CSI_REG(0x004C + 4 * (n))
++#define CSI_CPD_GRC(n) IPU_CSI_REG(0x005C + 4 * (n))
++#define CSI_CPD_GRS(n) IPU_CSI_REG(0x007C + 4 * (n))
++#define CSI_CPD_GBC(n) IPU_CSI_REG(0x008C + 4 * (n))
++#define CSI_CPD_GBS(n) IPU_CSI_REG(0x00AC + 4 * (n))
++#define CSI_CPD_BC(n) IPU_CSI_REG(0x00BC + 4 * (n))
++#define CSI_CPD_BS(n) IPU_CSI_REG(0x00DC + 4 * (n))
++#define CSI_CPD_OFFSET1 IPU_CSI_REG(0x00EC)
++#define CSI_CPD_OFFSET2 IPU_CSI_REG(0x00F0)
++
++/* IPU SMFC Registers */
++#define IPU_SMFC_REG(offset) (offset)
++
++#define SMFC_MAP IPU_SMFC_REG(0)
++#define SMFC_WMC IPU_SMFC_REG(0x0004)
++#define SMFC_BS IPU_SMFC_REG(0x0008)
++
++/* IPU IC Registers */
++#define IPU_IC_REG(offset) (offset)
++
++#define IC_CONF IPU_IC_REG(0)
++#define IC_PRP_ENC_RSC IPU_IC_REG(0x0004)
++#define IC_PRP_VF_RSC IPU_IC_REG(0x0008)
++#define IC_PP_RSC IPU_IC_REG(0x000C)
++#define IC_CMBP_1 IPU_IC_REG(0x0010)
++#define IC_CMBP_2 IPU_IC_REG(0x0014)
++#define IC_IDMAC_1 IPU_IC_REG(0x0018)
++#define IC_IDMAC_2 IPU_IC_REG(0x001C)
++#define IC_IDMAC_3 IPU_IC_REG(0x0020)
++#define IC_IDMAC_4 IPU_IC_REG(0x0024)
++
++/* IPU IDMAC Registers */
++#define IPU_IDMAC_REG(offset) (offset)
++
++#define IDMAC_CONF IPU_IDMAC_REG(0x0000)
++#define IDMAC_CHA_EN(ch) IPU_IDMAC_REG(0x0004 + 4 * ((ch) / 32))
++#define IDMAC_SEP_ALPHA IPU_IDMAC_REG(0x000C)
++#define IDMAC_ALT_SEP_ALPHA IPU_IDMAC_REG(0x0010)
++#define IDMAC_CHA_PRI(ch) IPU_IDMAC_REG(0x0014 + 4 * ((ch) / 32))
++#define IDMAC_WM_EN(ch) IPU_IDMAC_REG(0x001C + 4 * ((ch) / 32))
++#define IDMAC_CH_LOCK_EN_1 IPU_IDMAC_REG({g_ipu_hw_rev >= 2 ? \
++ (0x0024) : 0; })
++#define IDMAC_CH_LOCK_EN_2 IPU_IDMAC_REG({g_ipu_hw_rev >= 2 ? \
++ (0x0028) : \
++ (0x0024); })
++#define IDMAC_SUB_ADDR_0 IPU_IDMAC_REG({g_ipu_hw_rev >= 2 ? \
++ (0x002C) : \
++ (0x0028); })
++#define IDMAC_SUB_ADDR_1 IPU_IDMAC_REG({g_ipu_hw_rev >= 2 ? \
++ (0x0030) : \
++ (0x002C); })
++#define IDMAC_SUB_ADDR_2 IPU_IDMAC_REG({g_ipu_hw_rev >= 2 ? \
++ (0x0034) : \
++ (0x0030); })
++/*
++ * IPUv3D doesn't support IDMAC_SUB_ADDR_3 and IDMAC_SUB_ADDR_4,
++ * so point them to readonly IDMAC_CHA_BUSY1 for IPUv3D.
++ */
++#define IDMAC_SUB_ADDR_3 IPU_IDMAC_REG({g_ipu_hw_rev >= 2 ? \
++ (0x0038) : \
++ (0x0040); })
++#define IDMAC_SUB_ADDR_4 IPU_IDMAC_REG({g_ipu_hw_rev >= 2 ? \
++ (0x003C) : \
++ (0x0040); })
++#define IDMAC_BAND_EN(ch) IPU_IDMAC_REG({g_ipu_hw_rev >= 2 ? \
++ (0x0040 + 4 * ((ch) / 32)) : \
++ (0x0034 + 4 * ((ch) / 32)); })
++#define IDMAC_CHA_BUSY(ch) IPU_IDMAC_REG({g_ipu_hw_rev >= 2 ? \
++ (0x0100 + 4 * ((ch) / 32)) : \
++ (0x0040 + 4 * ((ch) / 32)); })
++
++/* IPU DI Registers */
++#define IPU_DI_REG(offset) (offset)
++
++#define DI_GENERAL IPU_DI_REG(0)
++#define DI_BS_CLKGEN0 IPU_DI_REG(0x0004)
++#define DI_BS_CLKGEN1 IPU_DI_REG(0x0008)
++#define DI_SW_GEN0(gen) IPU_DI_REG(0x000C + 4 * ((gen) - 1))
++#define DI_SW_GEN1(gen) IPU_DI_REG(0x0030 + 4 * ((gen) - 1))
++#define DI_STP_REP(gen) IPU_DI_REG(0x0148 + 4 * (((gen) - 1) / 2))
++#define DI_SYNC_AS_GEN IPU_DI_REG(0x0054)
++#define DI_DW_GEN(gen) IPU_DI_REG(0x0058 + 4 * (gen))
++#define DI_DW_SET(gen, set) IPU_DI_REG(0x0088 + 4 * ((gen) + 0xC * (set)))
++#define DI_SER_CONF IPU_DI_REG(0x015C)
++#define DI_SSC IPU_DI_REG(0x0160)
++#define DI_POL IPU_DI_REG(0x0164)
++#define DI_AW0 IPU_DI_REG(0x0168)
++#define DI_AW1 IPU_DI_REG(0x016C)
++#define DI_SCR_CONF IPU_DI_REG(0x0170)
++#define DI_STAT IPU_DI_REG(0x0174)
++
++/* IPU DMFC Registers */
++#define IPU_DMFC_REG(offset) (offset)
++
++#define DMFC_RD_CHAN IPU_DMFC_REG(0)
++#define DMFC_WR_CHAN IPU_DMFC_REG(0x0004)
++#define DMFC_WR_CHAN_DEF IPU_DMFC_REG(0x0008)
++#define DMFC_DP_CHAN IPU_DMFC_REG(0x000C)
++#define DMFC_DP_CHAN_DEF IPU_DMFC_REG(0x0010)
++#define DMFC_GENERAL1 IPU_DMFC_REG(0x0014)
++#define DMFC_GENERAL2 IPU_DMFC_REG(0x0018)
++#define DMFC_IC_CTRL IPU_DMFC_REG(0x001C)
++#define DMFC_STAT IPU_DMFC_REG(0x0020)
++
++/* IPU DC Registers */
++#define IPU_DC_REG(offset) (offset)
++
++#define DC_MAP_CONF_PTR(n) IPU_DC_REG(0x0108 + ((n) & ~0x1) * 2)
++#define DC_MAP_CONF_VAL(n) IPU_DC_REG(0x0144 + ((n) & ~0x1) * 2)
++
++#define _RL_CH_2_OFFSET(ch) (((ch) == 0) ? 8 : ( \
++ ((ch) == 1) ? 0x24 : ( \
++ ((ch) == 2) ? 0x40 : ( \
++ ((ch) == 5) ? 0x64 : ( \
++ ((ch) == 6) ? 0x80 : ( \
++ ((ch) == 8) ? 0x9C : ( \
++ ((ch) == 9) ? 0xBC : (-1))))))))
++#define DC_RL_CH(ch, evt) IPU_DC_REG(_RL_CH_2_OFFSET(ch) + \
++ ((evt) & ~0x1) * 2)
++
++#define DC_EVT_NF 0
++#define DC_EVT_NL 1
++#define DC_EVT_EOF 2
++#define DC_EVT_NFIELD 3
++#define DC_EVT_EOL 4
++#define DC_EVT_EOFIELD 5
++#define DC_EVT_NEW_ADDR 6
++#define DC_EVT_NEW_CHAN 7
++#define DC_EVT_NEW_DATA 8
++
++#define DC_EVT_NEW_ADDR_W_0 0
++#define DC_EVT_NEW_ADDR_W_1 1
++#define DC_EVT_NEW_CHAN_W_0 2
++#define DC_EVT_NEW_CHAN_W_1 3
++#define DC_EVT_NEW_DATA_W_0 4
++#define DC_EVT_NEW_DATA_W_1 5
++#define DC_EVT_NEW_ADDR_R_0 6
++#define DC_EVT_NEW_ADDR_R_1 7
++#define DC_EVT_NEW_CHAN_R_0 8
++#define DC_EVT_NEW_CHAN_R_1 9
++#define DC_EVT_NEW_DATA_R_0 10
++#define DC_EVT_NEW_DATA_R_1 11
++#define DC_EVEN_UGDE0 12
++#define DC_ODD_UGDE0 13
++#define DC_EVEN_UGDE1 14
++#define DC_ODD_UGDE1 15
++#define DC_EVEN_UGDE2 16
++#define DC_ODD_UGDE2 17
++#define DC_EVEN_UGDE3 18
++#define DC_ODD_UGDE3 19
++
++#define dc_ch_offset(ch) \
++({ \
++ const u8 _offset[] = { \
++ 0, 0x1C, 0x38, 0x54, 0x58, 0x5C, 0x78, 0, 0x94, 0xB4}; \
++ _offset[ch]; \
++})
++#define DC_WR_CH_CONF(ch) IPU_DC_REG(dc_ch_offset(ch))
++#define DC_WR_CH_ADDR(ch) IPU_DC_REG(dc_ch_offset(ch) + 4)
++
++#define DC_WR_CH_CONF_1 IPU_DC_REG(0x001C)
++#define DC_WR_CH_ADDR_1 IPU_DC_REG(0x0020)
++#define DC_WR_CH_CONF_5 IPU_DC_REG(0x005C)
++#define DC_WR_CH_ADDR_5 IPU_DC_REG(0x0060)
++#define DC_GEN IPU_DC_REG(0x00D4)
++#define DC_DISP_CONF1(disp) IPU_DC_REG(0x00D8 + 4 * (disp))
++#define DC_DISP_CONF2(disp) IPU_DC_REG(0x00E8 + 4 * (disp))
++#define DC_STAT IPU_DC_REG(0x01C8)
++#define DC_UGDE_0(evt) IPU_DC_REG(0x0174 + 16 * (evt))
++#define DC_UGDE_1(evt) IPU_DC_REG(0x0178 + 16 * (evt))
++#define DC_UGDE_2(evt) IPU_DC_REG(0x017C + 16 * (evt))
++#define DC_UGDE_3(evt) IPU_DC_REG(0x0180 + 16 * (evt))
++
++/* IPU DP Registers */
++#define IPU_DP_REG(offset) (offset)
++
++#define DP_SYNC 0
++#define DP_ASYNC0 0x60
++#define DP_ASYNC1 0xBC
++#define DP_COM_CONF(flow) IPU_DP_REG(flow)
++#define DP_GRAPH_WIND_CTRL(flow) IPU_DP_REG(0x0004 + (flow))
++#define DP_FG_POS(flow) IPU_DP_REG(0x0008 + (flow))
++#define DP_GAMMA_C(flow, i) IPU_DP_REG(0x0014 + (flow) + 4 * (i))
++#define DP_GAMMA_S(flow, i) IPU_DP_REG(0x0034 + (flow) + 4 * (i))
++#define DP_CSC_A_0(flow) IPU_DP_REG(0x0044 + (flow))
++#define DP_CSC_A_1(flow) IPU_DP_REG(0x0048 + (flow))
++#define DP_CSC_A_2(flow) IPU_DP_REG(0x004C + (flow))
++#define DP_CSC_A_3(flow) IPU_DP_REG(0x0050 + (flow))
++#define DP_CSC_0(flow) IPU_DP_REG(0x0054 + (flow))
++#define DP_CSC_1(flow) IPU_DP_REG(0x0058 + (flow))
++
++enum {
++ IPU_CONF_CSI0_EN = 0x00000001,
++ IPU_CONF_CSI1_EN = 0x00000002,
++ IPU_CONF_IC_EN = 0x00000004,
++ IPU_CONF_ROT_EN = 0x00000008,
++ IPU_CONF_ISP_EN = 0x00000010,
++ IPU_CONF_DP_EN = 0x00000020,
++ IPU_CONF_DI0_EN = 0x00000040,
++ IPU_CONF_DI1_EN = 0x00000080,
++ IPU_CONF_DMFC_EN = 0x00000400,
++ IPU_CONF_SMFC_EN = 0x00000100,
++ IPU_CONF_DC_EN = 0x00000200,
++ IPU_CONF_VDI_EN = 0x00001000,
++ IPU_CONF_IDMAC_DIS = 0x00400000,
++ IPU_CONF_IC_DMFC_SEL = 0x02000000,
++ IPU_CONF_IC_DMFC_SYNC = 0x04000000,
++ IPU_CONF_VDI_DMFC_SYNC = 0x08000000,
++ IPU_CONF_CSI0_DATA_SOURCE = 0x10000000,
++ IPU_CONF_CSI0_DATA_SOURCE_OFFSET = 28,
++ IPU_CONF_CSI1_DATA_SOURCE = 0x20000000,
++ IPU_CONF_IC_INPUT = 0x40000000,
++ IPU_CONF_CSI_SEL = 0x80000000,
++
++ DI0_COUNTER_RELEASE = 0x01000000,
++ DI1_COUNTER_RELEASE = 0x02000000,
++
++ FS_PRPVF_ROT_SRC_SEL_MASK = 0x00000F00,
++ FS_PRPVF_ROT_SRC_SEL_OFFSET = 8,
++ FS_PRPENC_ROT_SRC_SEL_MASK = 0x0000000F,
++ FS_PRPENC_ROT_SRC_SEL_OFFSET = 0,
++ FS_PP_ROT_SRC_SEL_MASK = 0x000F0000,
++ FS_PP_ROT_SRC_SEL_OFFSET = 16,
++ FS_PP_SRC_SEL_MASK = 0x0000F000,
++ FS_PP_SRC_SEL_VDOA = 0x00008000,
++ FS_PP_SRC_SEL_OFFSET = 12,
++ FS_PRP_SRC_SEL_MASK = 0x0F000000,
++ FS_PRP_SRC_SEL_OFFSET = 24,
++ FS_VF_IN_VALID = 0x80000000,
++ FS_ENC_IN_VALID = 0x40000000,
++ FS_VDI_SRC_SEL_MASK = 0x30000000,
++ FS_VDI_SRC_SEL_VDOA = 0x20000000,
++ FS_VDOA_DEST_SEL_MASK = 0x00030000,
++ FS_VDOA_DEST_SEL_VDI = 0x00020000,
++ FS_VDOA_DEST_SEL_IC = 0x00010000,
++ FS_VDI_SRC_SEL_OFFSET = 28,
++
++
++ FS_PRPENC_DEST_SEL_MASK = 0x0000000F,
++ FS_PRPENC_DEST_SEL_OFFSET = 0,
++ FS_PRPVF_DEST_SEL_MASK = 0x000000F0,
++ FS_PRPVF_DEST_SEL_OFFSET = 4,
++ FS_PRPVF_ROT_DEST_SEL_MASK = 0x00000F00,
++ FS_PRPVF_ROT_DEST_SEL_OFFSET = 8,
++ FS_PP_DEST_SEL_MASK = 0x0000F000,
++ FS_PP_DEST_SEL_OFFSET = 12,
++ FS_PP_ROT_DEST_SEL_MASK = 0x000F0000,
++ FS_PP_ROT_DEST_SEL_OFFSET = 16,
++ FS_PRPENC_ROT_DEST_SEL_MASK = 0x00F00000,
++ FS_PRPENC_ROT_DEST_SEL_OFFSET = 20,
++
++ FS_SMFC0_DEST_SEL_MASK = 0x0000000F,
++ FS_SMFC0_DEST_SEL_OFFSET = 0,
++ FS_SMFC1_DEST_SEL_MASK = 0x00000070,
++ FS_SMFC1_DEST_SEL_OFFSET = 4,
++ FS_SMFC2_DEST_SEL_MASK = 0x00000780,
++ FS_SMFC2_DEST_SEL_OFFSET = 7,
++ FS_SMFC3_DEST_SEL_MASK = 0x00003800,
++ FS_SMFC3_DEST_SEL_OFFSET = 11,
++
++ FS_DC1_SRC_SEL_MASK = 0x00F00000,
++ FS_DC1_SRC_SEL_OFFSET = 20,
++ FS_DC2_SRC_SEL_MASK = 0x000F0000,
++ FS_DC2_SRC_SEL_OFFSET = 16,
++ FS_DP_SYNC0_SRC_SEL_MASK = 0x0000000F,
++ FS_DP_SYNC0_SRC_SEL_OFFSET = 0,
++ FS_DP_SYNC1_SRC_SEL_MASK = 0x000000F0,
++ FS_DP_SYNC1_SRC_SEL_OFFSET = 4,
++ FS_DP_ASYNC0_SRC_SEL_MASK = 0x00000F00,
++ FS_DP_ASYNC0_SRC_SEL_OFFSET = 8,
++ FS_DP_ASYNC1_SRC_SEL_MASK = 0x0000F000,
++ FS_DP_ASYNC1_SRC_SEL_OFFSET = 12,
++
++ FS_AUTO_REF_PER_MASK = 0,
++ FS_AUTO_REF_PER_OFFSET = 16,
++
++ TSTAT_VF_MASK = 0x0000000C,
++ TSTAT_VF_OFFSET = 2,
++ TSTAT_VF_ROT_MASK = 0x00000300,
++ TSTAT_VF_ROT_OFFSET = 8,
++ TSTAT_ENC_MASK = 0x00000003,
++ TSTAT_ENC_OFFSET = 0,
++ TSTAT_ENC_ROT_MASK = 0x000000C0,
++ TSTAT_ENC_ROT_OFFSET = 6,
++ TSTAT_PP_MASK = 0x00000030,
++ TSTAT_PP_OFFSET = 4,
++ TSTAT_PP_ROT_MASK = 0x00000C00,
++ TSTAT_PP_ROT_OFFSET = 10,
++
++ TASK_STAT_IDLE = 0,
++ TASK_STAT_ACTIVE = 1,
++ TASK_STAT_WAIT4READY = 2,
++
++ /* Image Converter Register bits */
++ IC_CONF_PRPENC_EN = 0x00000001,
++ IC_CONF_PRPENC_CSC1 = 0x00000002,
++ IC_CONF_PRPENC_ROT_EN = 0x00000004,
++ IC_CONF_PRPVF_EN = 0x00000100,
++ IC_CONF_PRPVF_CSC1 = 0x00000200,
++ IC_CONF_PRPVF_CSC2 = 0x00000400,
++ IC_CONF_PRPVF_CMB = 0x00000800,
++ IC_CONF_PRPVF_ROT_EN = 0x00001000,
++ IC_CONF_PP_EN = 0x00010000,
++ IC_CONF_PP_CSC1 = 0x00020000,
++ IC_CONF_PP_CSC2 = 0x00040000,
++ IC_CONF_PP_CMB = 0x00080000,
++ IC_CONF_PP_ROT_EN = 0x00100000,
++ IC_CONF_IC_GLB_LOC_A = 0x10000000,
++ IC_CONF_KEY_COLOR_EN = 0x20000000,
++ IC_CONF_RWS_EN = 0x40000000,
++ IC_CONF_CSI_MEM_WR_EN = 0x80000000,
++
++ IC_RSZ_MAX_RESIZE_RATIO = 0x00004000,
++
++ IC_IDMAC_1_CB0_BURST_16 = 0x00000001,
++ IC_IDMAC_1_CB1_BURST_16 = 0x00000002,
++ IC_IDMAC_1_CB2_BURST_16 = 0x00000004,
++ IC_IDMAC_1_CB3_BURST_16 = 0x00000008,
++ IC_IDMAC_1_CB4_BURST_16 = 0x00000010,
++ IC_IDMAC_1_CB5_BURST_16 = 0x00000020,
++ IC_IDMAC_1_CB6_BURST_16 = 0x00000040,
++ IC_IDMAC_1_CB7_BURST_16 = 0x00000080,
++ IC_IDMAC_1_PRPENC_ROT_MASK = 0x00003800,
++ IC_IDMAC_1_PRPENC_ROT_OFFSET = 11,
++ IC_IDMAC_1_PRPVF_ROT_MASK = 0x0001C000,
++ IC_IDMAC_1_PRPVF_ROT_OFFSET = 14,
++ IC_IDMAC_1_PP_ROT_MASK = 0x000E0000,
++ IC_IDMAC_1_PP_ROT_OFFSET = 17,
++ IC_IDMAC_1_PP_FLIP_RS = 0x00400000,
++ IC_IDMAC_1_PRPVF_FLIP_RS = 0x00200000,
++ IC_IDMAC_1_PRPENC_FLIP_RS = 0x00100000,
++
++ IC_IDMAC_2_PRPENC_HEIGHT_MASK = 0x000003FF,
++ IC_IDMAC_2_PRPENC_HEIGHT_OFFSET = 0,
++ IC_IDMAC_2_PRPVF_HEIGHT_MASK = 0x000FFC00,
++ IC_IDMAC_2_PRPVF_HEIGHT_OFFSET = 10,
++ IC_IDMAC_2_PP_HEIGHT_MASK = 0x3FF00000,
++ IC_IDMAC_2_PP_HEIGHT_OFFSET = 20,
++
++ IC_IDMAC_3_PRPENC_WIDTH_MASK = 0x000003FF,
++ IC_IDMAC_3_PRPENC_WIDTH_OFFSET = 0,
++ IC_IDMAC_3_PRPVF_WIDTH_MASK = 0x000FFC00,
++ IC_IDMAC_3_PRPVF_WIDTH_OFFSET = 10,
++ IC_IDMAC_3_PP_WIDTH_MASK = 0x3FF00000,
++ IC_IDMAC_3_PP_WIDTH_OFFSET = 20,
++
++ CSI_SENS_CONF_DATA_FMT_SHIFT = 8,
++ CSI_SENS_CONF_DATA_FMT_MASK = 0x00000700,
++ CSI_SENS_CONF_DATA_FMT_RGB_YUV444 = 0L,
++ CSI_SENS_CONF_DATA_FMT_YUV422_YUYV = 1L,
++ CSI_SENS_CONF_DATA_FMT_YUV422_UYVY = 2L,
++ CSI_SENS_CONF_DATA_FMT_BAYER = 3L,
++ CSI_SENS_CONF_DATA_FMT_RGB565 = 4L,
++ CSI_SENS_CONF_DATA_FMT_RGB555 = 5L,
++ CSI_SENS_CONF_DATA_FMT_RGB444 = 6L,
++ CSI_SENS_CONF_DATA_FMT_JPEG = 7L,
++
++ CSI_SENS_CONF_VSYNC_POL_SHIFT = 0,
++ CSI_SENS_CONF_HSYNC_POL_SHIFT = 1,
++ CSI_SENS_CONF_DATA_POL_SHIFT = 2,
++ CSI_SENS_CONF_PIX_CLK_POL_SHIFT = 3,
++ CSI_SENS_CONF_SENS_PRTCL_MASK = 0x00000070L,
++ CSI_SENS_CONF_SENS_PRTCL_SHIFT = 4,
++ CSI_SENS_CONF_PACK_TIGHT_SHIFT = 7,
++ CSI_SENS_CONF_DATA_WIDTH_SHIFT = 11,
++ CSI_SENS_CONF_EXT_VSYNC_SHIFT = 15,
++ CSI_SENS_CONF_DIVRATIO_SHIFT = 16,
++
++ CSI_SENS_CONF_DIVRATIO_MASK = 0x00FF0000L,
++ CSI_SENS_CONF_DATA_DEST_SHIFT = 24,
++ CSI_SENS_CONF_DATA_DEST_MASK = 0x07000000L,
++ CSI_SENS_CONF_JPEG8_EN_SHIFT = 27,
++ CSI_SENS_CONF_JPEG_EN_SHIFT = 28,
++ CSI_SENS_CONF_FORCE_EOF_SHIFT = 29,
++ CSI_SENS_CONF_DATA_EN_POL_SHIFT = 31,
++
++ CSI_DATA_DEST_ISP = 1L,
++ CSI_DATA_DEST_IC = 2L,
++ CSI_DATA_DEST_IDMAC = 4L,
++
++ CSI_CCIR_ERR_DET_EN = 0x01000000L,
++ CSI_HORI_DOWNSIZE_EN = 0x80000000L,
++ CSI_VERT_DOWNSIZE_EN = 0x40000000L,
++ CSI_TEST_GEN_MODE_EN = 0x01000000L,
++
++ CSI_HSC_MASK = 0x1FFF0000,
++ CSI_HSC_SHIFT = 16,
++ CSI_VSC_MASK = 0x00000FFF,
++ CSI_VSC_SHIFT = 0,
++
++ CSI_TEST_GEN_R_MASK = 0x000000FFL,
++ CSI_TEST_GEN_R_SHIFT = 0,
++ CSI_TEST_GEN_G_MASK = 0x0000FF00L,
++ CSI_TEST_GEN_G_SHIFT = 8,
++ CSI_TEST_GEN_B_MASK = 0x00FF0000L,
++ CSI_TEST_GEN_B_SHIFT = 16,
++
++ CSI_MIPI_DI0_MASK = 0x000000FFL,
++ CSI_MIPI_DI0_SHIFT = 0,
++ CSI_MIPI_DI1_MASK = 0x0000FF00L,
++ CSI_MIPI_DI1_SHIFT = 8,
++ CSI_MIPI_DI2_MASK = 0x00FF0000L,
++ CSI_MIPI_DI2_SHIFT = 16,
++ CSI_MIPI_DI3_MASK = 0xFF000000L,
++ CSI_MIPI_DI3_SHIFT = 24,
++
++ CSI_MAX_RATIO_SKIP_ISP_MASK = 0x00070000L,
++ CSI_MAX_RATIO_SKIP_ISP_SHIFT = 16,
++ CSI_SKIP_ISP_MASK = 0x00F80000L,
++ CSI_SKIP_ISP_SHIFT = 19,
++ CSI_MAX_RATIO_SKIP_SMFC_MASK = 0x00000007L,
++ CSI_MAX_RATIO_SKIP_SMFC_SHIFT = 0,
++ CSI_SKIP_SMFC_MASK = 0x000000F8L,
++ CSI_SKIP_SMFC_SHIFT = 3,
++ CSI_ID_2_SKIP_MASK = 0x00000300L,
++ CSI_ID_2_SKIP_SHIFT = 8,
++
++ CSI_COLOR_FIRST_ROW_MASK = 0x00000002L,
++ CSI_COLOR_FIRST_COMP_MASK = 0x00000001L,
++
++ SMFC_MAP_CH0_MASK = 0x00000007L,
++ SMFC_MAP_CH0_SHIFT = 0,
++ SMFC_MAP_CH1_MASK = 0x00000038L,
++ SMFC_MAP_CH1_SHIFT = 3,
++ SMFC_MAP_CH2_MASK = 0x000001C0L,
++ SMFC_MAP_CH2_SHIFT = 6,
++ SMFC_MAP_CH3_MASK = 0x00000E00L,
++ SMFC_MAP_CH3_SHIFT = 9,
++
++ SMFC_WM0_SET_MASK = 0x00000007L,
++ SMFC_WM0_SET_SHIFT = 0,
++ SMFC_WM1_SET_MASK = 0x000001C0L,
++ SMFC_WM1_SET_SHIFT = 6,
++ SMFC_WM2_SET_MASK = 0x00070000L,
++ SMFC_WM2_SET_SHIFT = 16,
++ SMFC_WM3_SET_MASK = 0x01C00000L,
++ SMFC_WM3_SET_SHIFT = 22,
++
++ SMFC_WM0_CLR_MASK = 0x00000038L,
++ SMFC_WM0_CLR_SHIFT = 3,
++ SMFC_WM1_CLR_MASK = 0x00000E00L,
++ SMFC_WM1_CLR_SHIFT = 9,
++ SMFC_WM2_CLR_MASK = 0x00380000L,
++ SMFC_WM2_CLR_SHIFT = 19,
++ SMFC_WM3_CLR_MASK = 0x0E000000L,
++ SMFC_WM3_CLR_SHIFT = 25,
++
++ SMFC_BS0_MASK = 0x0000000FL,
++ SMFC_BS0_SHIFT = 0,
++ SMFC_BS1_MASK = 0x000000F0L,
++ SMFC_BS1_SHIFT = 4,
++ SMFC_BS2_MASK = 0x00000F00L,
++ SMFC_BS2_SHIFT = 8,
++ SMFC_BS3_MASK = 0x0000F000L,
++ SMFC_BS3_SHIFT = 12,
++
++ PF_CONF_TYPE_MASK = 0x00000007,
++ PF_CONF_TYPE_SHIFT = 0,
++ PF_CONF_PAUSE_EN = 0x00000010,
++ PF_CONF_RESET = 0x00008000,
++ PF_CONF_PAUSE_ROW_MASK = 0x00FF0000,
++ PF_CONF_PAUSE_ROW_SHIFT = 16,
++
++ DI_DW_GEN_ACCESS_SIZE_OFFSET = 24,
++ DI_DW_GEN_COMPONENT_SIZE_OFFSET = 16,
++
++ DI_GEN_DI_CLK_EXT = 0x100000,
++ DI_GEN_POLARITY_DISP_CLK = 0x00020000,
++ DI_GEN_POLARITY_1 = 0x00000001,
++ DI_GEN_POLARITY_2 = 0x00000002,
++ DI_GEN_POLARITY_3 = 0x00000004,
++ DI_GEN_POLARITY_4 = 0x00000008,
++ DI_GEN_POLARITY_5 = 0x00000010,
++ DI_GEN_POLARITY_6 = 0x00000020,
++ DI_GEN_POLARITY_7 = 0x00000040,
++ DI_GEN_POLARITY_8 = 0x00000080,
++
++ DI_POL_DRDY_DATA_POLARITY = 0x00000080,
++ DI_POL_DRDY_POLARITY_15 = 0x00000010,
++
++ DI_VSYNC_SEL_OFFSET = 13,
++
++ DC_WR_CH_CONF_FIELD_MODE = 0x00000200,
++ DC_WR_CH_CONF_PROG_TYPE_OFFSET = 5,
++ DC_WR_CH_CONF_PROG_TYPE_MASK = 0x000000E0,
++ DC_WR_CH_CONF_PROG_DI_ID = 0x00000004,
++ DC_WR_CH_CONF_PROG_DISP_ID_OFFSET = 3,
++ DC_WR_CH_CONF_PROG_DISP_ID_MASK = 0x00000018,
++
++ DC_UGDE_0_ODD_EN = 0x02000000,
++ DC_UGDE_0_ID_CODED_MASK = 0x00000007,
++ DC_UGDE_0_ID_CODED_OFFSET = 0,
++ DC_UGDE_0_EV_PRIORITY_MASK = 0x00000078,
++ DC_UGDE_0_EV_PRIORITY_OFFSET = 3,
++
++ DP_COM_CONF_FG_EN = 0x00000001,
++ DP_COM_CONF_GWSEL = 0x00000002,
++ DP_COM_CONF_GWAM = 0x00000004,
++ DP_COM_CONF_GWCKE = 0x00000008,
++ DP_COM_CONF_CSC_DEF_MASK = 0x00000300,
++ DP_COM_CONF_CSC_DEF_OFFSET = 8,
++ DP_COM_CONF_CSC_DEF_FG = 0x00000300,
++ DP_COM_CONF_CSC_DEF_BG = 0x00000200,
++ DP_COM_CONF_CSC_DEF_BOTH = 0x00000100,
++ DP_COM_CONF_GAMMA_EN = 0x00001000,
++ DP_COM_CONF_GAMMA_YUV_EN = 0x00002000,
++
++ DI_SER_CONF_LLA_SER_ACCESS = 0x00000020,
++ DI_SER_CONF_SERIAL_CLK_POL = 0x00000010,
++ DI_SER_CONF_SERIAL_DATA_POL = 0x00000008,
++ DI_SER_CONF_SERIAL_RS_POL = 0x00000004,
++ DI_SER_CONF_SERIAL_CS_POL = 0x00000002,
++ DI_SER_CONF_WAIT4SERIAL = 0x00000001,
++
++ VDI_C_CH_420 = 0x00000000,
++ VDI_C_CH_422 = 0x00000002,
++ VDI_C_MOT_SEL_FULL = 0x00000008,
++ VDI_C_MOT_SEL_LOW = 0x00000004,
++ VDI_C_MOT_SEL_MED = 0x00000000,
++ VDI_C_BURST_SIZE1_4 = 0x00000030,
++ VDI_C_BURST_SIZE2_4 = 0x00000300,
++ VDI_C_BURST_SIZE3_4 = 0x00003000,
++ VDI_C_BURST_SIZE_MASK = 0xF,
++ VDI_C_BURST_SIZE1_OFFSET = 4,
++ VDI_C_BURST_SIZE2_OFFSET = 8,
++ VDI_C_BURST_SIZE3_OFFSET = 12,
++ VDI_C_VWM1_SET_1 = 0x00000000,
++ VDI_C_VWM1_SET_2 = 0x00010000,
++ VDI_C_VWM1_CLR_2 = 0x00080000,
++ VDI_C_VWM3_SET_1 = 0x00000000,
++ VDI_C_VWM3_SET_2 = 0x00400000,
++ VDI_C_VWM3_CLR_2 = 0x02000000,
++ VDI_C_TOP_FIELD_MAN_1 = 0x40000000,
++ VDI_C_TOP_FIELD_AUTO_1 = 0x80000000,
++};
++
++enum di_pins {
++ DI_PIN11 = 0,
++ DI_PIN12 = 1,
++ DI_PIN13 = 2,
++ DI_PIN14 = 3,
++ DI_PIN15 = 4,
++ DI_PIN16 = 5,
++ DI_PIN17 = 6,
++ DI_PIN_CS = 7,
++
++ DI_PIN_SER_CLK = 0,
++ DI_PIN_SER_RS = 1,
++};
++
++enum di_sync_wave {
++ DI_SYNC_NONE = -1,
++ DI_SYNC_CLK = 0,
++ DI_SYNC_INT_HSYNC = 1,
++ DI_SYNC_COUNT_1 = 1,
++ DI_SYNC_HSYNC = 2,
++ DI_SYNC_VSYNC = 3,
++ DI_SYNC_AFIELD = 4,
++ DI_SYNC_ALINE = 5,
++ DI_SYNC_APIXEL = 6,
++ DI_SYNC_COUNT_7 = 7,
++ DI_SYNC_COUNT_8 = 8,
++ DI_SYNC_COUNT_9 = 9,
++};
++
++/* DC template opcodes */
++#define WROD(lf) (0x18 | (lf << 1))
++#define WRG (0x01)
++
++#endif
+diff -Nur linux-4.1.3/drivers/mxc/ipu3/Kconfig linux-xbian-imx6/drivers/mxc/ipu3/Kconfig
+--- linux-4.1.3/drivers/mxc/ipu3/Kconfig 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/ipu3/Kconfig 2015-07-27 23:13:06.226765901 +0200
+@@ -0,0 +1,2 @@
++config MXC_IPU_V3_FSL
++ bool
+diff -Nur linux-4.1.3/drivers/mxc/ipu3/Makefile linux-xbian-imx6/drivers/mxc/ipu3/Makefile
+--- linux-4.1.3/drivers/mxc/ipu3/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/ipu3/Makefile 2015-07-27 23:13:06.226765901 +0200
+@@ -0,0 +1,4 @@
++obj-$(CONFIG_MXC_IPU_V3_FSL) = mxc_ipu.o
++
++mxc_ipu-objs := ipu_common.o ipu_ic.o ipu_disp.o ipu_capture.o ipu_device.o \
++ ipu_calc_stripes_sizes.o vdoa.o ipu_pixel_clk.o
+diff -Nur linux-4.1.3/drivers/mxc/ipu3/vdoa.c linux-xbian-imx6/drivers/mxc/ipu3/vdoa.c
+--- linux-4.1.3/drivers/mxc/ipu3/vdoa.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/ipu3/vdoa.c 2015-07-27 23:13:06.230751680 +0200
+@@ -0,0 +1,547 @@
++/*
++ * Copyright (C) 2012-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++#include <linux/clk.h>
++#include <linux/err.h>
++#include <linux/io.h>
++#include <linux/ipu.h>
++#include <linux/genalloc.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/slab.h>
++#include <linux/types.h>
++#include <linux/of.h>
++#include <linux/of_irq.h>
++#include <linux/of_pci.h>
++
++#include "vdoa.h"
++/* 6band(3field* double buffer) * (width*2) * bandline(8)
++ = 6x1024x2x8 = 96k or 72k(1.5byte) */
++#define MAX_VDOA_IRAM_SIZE (1024*96)
++#define VDOA_IRAM_SIZE (1024*72)
++
++#define VDOAC_BAND_HEIGHT_32LINES (32)
++#define VDOAC_BAND_HEIGHT_16LINES (16)
++#define VDOAC_BAND_HEIGHT_8LINES (8)
++#define VDOAC_THREE_FRAMES (0x1 << 2)
++#define VDOAC_SYNC_BAND_MODE (0x1 << 3)
++#define VDOAC_SCAN_ORDER_INTERLACED (0x1 << 4)
++#define VDOAC_PFS_YUYV (0x1 << 5)
++#define VDOAC_IPU_SEL_1 (0x1 << 6)
++#define VDOAFP_FH_MASK (0x1FFF)
++#define VDOAFP_FH_SHIFT (16)
++#define VDOAFP_FW_MASK (0x3FFF)
++#define VDOAFP_FW_SHIFT (0)
++#define VDOASL_VSLY_MASK (0x3FFF)
++#define VDOASL_VSLY_SHIFT (16)
++#define VDOASL_ISLY_MASK (0x7FFF)
++#define VDOASL_ISLY_SHIFT (0)
++#define VDOASRR_START_XFER (0x2)
++#define VDOASRR_SWRST (0x1)
++#define VDOAIEIST_TRANSFER_ERR (0x2)
++#define VDOAIEIST_TRANSFER_END (0x1)
++
++#define VDOAC (0x0) /* Control Register */
++#define VDOASRR (0x4) /* Start and Reset Register */
++#define VDOAIE (0x8) /* Interrupt Enable Register */
++#define VDOAIST (0xc) /* Interrupt Status Register */
++#define VDOAFP (0x10) /* Frame Parameters Register */
++#define VDOAIEBA00 (0x14) /* External Buffer n Frame m Address Register */
++#define VDOAIEBA01 (0x18) /* External Buffer n Frame m Address Register */
++#define VDOAIEBA02 (0x1c) /* External Buffer n Frame m Address Register */
++#define VDOAIEBA10 (0x20) /* External Buffer n Frame m Address Register */
++#define VDOAIEBA11 (0x24) /* External Buffer n Frame m Address Register */
++#define VDOAIEBA12 (0x28) /* External Buffer n Frame m Address Register */
++#define VDOASL (0x2c) /* IPU Stride Line Register */
++#define VDOAIUBO (0x30) /* IPU Chroma Buffer Offset Register */
++#define VDOAVEBA0 (0x34) /* External Buffer m Address Register */
++#define VDOAVEBA1 (0x38) /* External Buffer m Address Register */
++#define VDOAVEBA2 (0x3c) /* External Buffer m Address Register */
++#define VDOAVUBO (0x40) /* VPU Chroma Buffer Offset */
++#define VDOASR (0x44) /* Status Register */
++#define VDOATD (0x48) /* Test Debug Register */
++
++
++enum {
++ VDOA_INIT = 0x1,
++ VDOA_GET = 0x2,
++ VDOA_SETUP = 0x4,
++ VDOA_GET_OBUF = 0x8,
++ VDOA_START = 0x10,
++ VDOA_INIRQ = 0x20,
++ VDOA_STOP = 0x40,
++ VDOA_PUT = VDOA_INIT,
++};
++
++enum {
++ VDOA_NULL = 0,
++ VDOA_FRAME = 1,
++ VDOA_PREV_FIELD = 2,
++ VDOA_CURR_FIELD = 3,
++ VDOA_NEXT_FIELD = 4,
++};
++
++#define CHECK_STATE(expect, retcode) \
++do { \
++ if (!((expect) & vdoa->state)) { \
++ dev_err(vdoa->dev, "ERR: %s state:0x%x, expect:0x%x.\n",\
++ __func__, vdoa->state, (expect)); \
++ retcode; \
++ } \
++} while (0)
++
++#define CHECK_NULL_PTR(ptr) \
++do { \
++ pr_debug("vdoa_ptr:0x%p in %s state:0x%x.\n", \
++ vdoa, __func__, vdoa->state); \
++ if (NULL == (ptr)) { \
++ pr_err("ERR vdoa: %s state:0x%x null ptr.\n", \
++ __func__, vdoa->state); \
++ } \
++} while (0)
++
++struct vdoa_info {
++ int state;
++ struct device *dev;
++ struct clk *vdoa_clk;
++ void __iomem *reg_base;
++ struct gen_pool *iram_pool;
++ unsigned long iram_base;
++ unsigned long iram_paddr;
++ int irq;
++ int field;
++ struct completion comp;
++};
++
++static struct vdoa_info *g_vdoa;
++static unsigned long iram_size;
++static DEFINE_MUTEX(vdoa_lock);
++
++static inline void vdoa_read_register(struct vdoa_info *vdoa,
++ u32 reg, u32 *val)
++{
++ *val = ioread32(vdoa->reg_base + reg);
++ dev_dbg(vdoa->dev, "read_reg:0x%02x, val:0x%08x.\n", reg, *val);
++}
++
++static inline void vdoa_write_register(struct vdoa_info *vdoa,
++ u32 reg, u32 val)
++{
++ iowrite32(val, vdoa->reg_base + reg);
++ dev_dbg(vdoa->dev, "\t\twrite_reg:0x%02x, val:0x%08x.\n", reg, val);
++}
++
++static void dump_registers(struct vdoa_info *vdoa)
++{
++ int i;
++ u32 data;
++
++ for (i = VDOAC; i < VDOATD; i += 4)
++ vdoa_read_register(vdoa, i, &data);
++}
++
++int vdoa_setup(vdoa_handle_t handle, struct vdoa_params *params)
++{
++ int band_size;
++ int total_band_size = 0;
++ int ipu_stride;
++ u32 data;
++ struct vdoa_info *vdoa = (struct vdoa_info *)handle;
++
++ CHECK_NULL_PTR(vdoa);
++ CHECK_STATE(VDOA_GET | VDOA_GET_OBUF | VDOA_STOP, return -EINVAL);
++ if (VDOA_GET == vdoa->state) {
++ dev_dbg(vdoa->dev, "w:%d, h:%d.\n",
++ params->width, params->height);
++ data = (params->band_lines == VDOAC_BAND_HEIGHT_32LINES) ? 2 :
++ ((params->band_lines == VDOAC_BAND_HEIGHT_16LINES) ?
++ 1 : 0);
++ data |= params->scan_order ? VDOAC_SCAN_ORDER_INTERLACED : 0;
++ data |= params->band_mode ? VDOAC_SYNC_BAND_MODE : 0;
++ data |= params->pfs ? VDOAC_PFS_YUYV : 0;
++ data |= params->ipu_num ? VDOAC_IPU_SEL_1 : 0;
++ vdoa_write_register(vdoa, VDOAC, data);
++
++ data = ((params->width & VDOAFP_FW_MASK) << VDOAFP_FW_SHIFT) |
++ ((params->height & VDOAFP_FH_MASK) << VDOAFP_FH_SHIFT);
++ vdoa_write_register(vdoa, VDOAFP, data);
++
++ ipu_stride = params->pfs ? params->width << 1 : params->width;
++ data = ((params->vpu_stride & VDOASL_VSLY_MASK) <<
++ VDOASL_VSLY_SHIFT) |
++ ((ipu_stride & VDOASL_ISLY_MASK) << VDOASL_ISLY_SHIFT);
++ vdoa_write_register(vdoa, VDOASL, data);
++
++ dev_dbg(vdoa->dev, "band_mode:%d, band_line:%d, base:0x%lx.\n",
++ params->band_mode, params->band_lines, vdoa->iram_paddr);
++ }
++ /*
++ * band size = (luma_per_line + chroma_per_line) * bandLines
++ * = width * (3/2 or 2) * bandLines
++ * double buffer mode used.
++ */
++ if (params->pfs)
++ band_size = (params->width << 1) * params->band_lines;
++ else
++ band_size = ((params->width * 3) >> 1) *
++ params->band_lines;
++ if (params->interlaced) {
++ total_band_size = 6 * band_size; /* 3 frames*double buffer */
++ if (iram_size < total_band_size) {
++ dev_err(vdoa->dev, "iram_size:0x%lx is smaller than "
++ "request:0x%x!\n", iram_size, total_band_size);
++ return -EINVAL;
++ }
++ if (params->vfield_buf.prev_veba) {
++ if (params->band_mode) {
++ vdoa_write_register(vdoa, VDOAIEBA00,
++ vdoa->iram_paddr);
++ vdoa_write_register(vdoa, VDOAIEBA10,
++ vdoa->iram_paddr + band_size);
++ } else
++ vdoa_write_register(vdoa, VDOAIEBA00,
++ params->ieba0);
++ vdoa_write_register(vdoa, VDOAVEBA0,
++ params->vfield_buf.prev_veba);
++ vdoa->field = VDOA_PREV_FIELD;
++ }
++ if (params->vfield_buf.cur_veba) {
++ if (params->band_mode) {
++ vdoa_write_register(vdoa, VDOAIEBA01,
++ vdoa->iram_paddr + band_size * 2);
++ vdoa_write_register(vdoa, VDOAIEBA11,
++ vdoa->iram_paddr + band_size * 3);
++ } else
++ vdoa_write_register(vdoa, VDOAIEBA01,
++ params->ieba1);
++ vdoa_write_register(vdoa, VDOAVEBA1,
++ params->vfield_buf.cur_veba);
++ vdoa->field = VDOA_CURR_FIELD;
++ }
++ if (params->vfield_buf.next_veba) {
++ if (params->band_mode) {
++ vdoa_write_register(vdoa, VDOAIEBA02,
++ vdoa->iram_paddr + band_size * 4);
++ vdoa_write_register(vdoa, VDOAIEBA12,
++ vdoa->iram_paddr + band_size * 5);
++ } else
++ vdoa_write_register(vdoa, VDOAIEBA02,
++ params->ieba2);
++ vdoa_write_register(vdoa, VDOAVEBA2,
++ params->vfield_buf.next_veba);
++ vdoa->field = VDOA_NEXT_FIELD;
++ vdoa_read_register(vdoa, VDOAC, &data);
++ data |= VDOAC_THREE_FRAMES;
++ vdoa_write_register(vdoa, VDOAC, data);
++ }
++
++ if (!params->pfs)
++ vdoa_write_register(vdoa, VDOAIUBO,
++ params->width * params->band_lines);
++ vdoa_write_register(vdoa, VDOAVUBO,
++ params->vfield_buf.vubo);
++ dev_dbg(vdoa->dev, "total band_size:0x%x.\n", band_size*6);
++ } else if (params->band_mode) {
++ /* used for progressive frame resize on PrP channel */
++ BUG(); /* currently not support */
++ /* progressvie frame: band mode */
++ vdoa_write_register(vdoa, VDOAIEBA00, vdoa->iram_paddr);
++ vdoa_write_register(vdoa, VDOAIEBA10,
++ vdoa->iram_paddr + band_size);
++ if (!params->pfs)
++ vdoa_write_register(vdoa, VDOAIUBO,
++ params->width * params->band_lines);
++ dev_dbg(vdoa->dev, "total band_size:0x%x\n", band_size*2);
++ } else {
++ /* progressive frame: mem->mem, non-band mode */
++ vdoa->field = VDOA_FRAME;
++ vdoa_write_register(vdoa, VDOAVEBA0, params->vframe_buf.veba);
++ vdoa_write_register(vdoa, VDOAVUBO, params->vframe_buf.vubo);
++ vdoa_write_register(vdoa, VDOAIEBA00, params->ieba0);
++ if (!params->pfs)
++ /* note: iubo is relative value, based on ieba0 */
++ vdoa_write_register(vdoa, VDOAIUBO,
++ params->width * params->height);
++ }
++ vdoa->state = VDOA_SETUP;
++ return 0;
++}
++
++void vdoa_get_output_buf(vdoa_handle_t handle, struct vdoa_ipu_buf *buf)
++{
++ u32 data;
++ struct vdoa_info *vdoa = (struct vdoa_info *)handle;
++
++ CHECK_NULL_PTR(vdoa);
++ CHECK_STATE(VDOA_SETUP, return);
++ vdoa->state = VDOA_GET_OBUF;
++ memset(buf, 0, sizeof(*buf));
++
++ vdoa_read_register(vdoa, VDOAC, &data);
++ switch (vdoa->field) {
++ case VDOA_FRAME:
++ case VDOA_PREV_FIELD:
++ vdoa_read_register(vdoa, VDOAIEBA00, &buf->ieba0);
++ if (data & VDOAC_SYNC_BAND_MODE)
++ vdoa_read_register(vdoa, VDOAIEBA10, &buf->ieba1);
++ break;
++ case VDOA_CURR_FIELD:
++ vdoa_read_register(vdoa, VDOAIEBA01, &buf->ieba0);
++ vdoa_read_register(vdoa, VDOAIEBA11, &buf->ieba1);
++ break;
++ case VDOA_NEXT_FIELD:
++ vdoa_read_register(vdoa, VDOAIEBA02, &buf->ieba0);
++ vdoa_read_register(vdoa, VDOAIEBA12, &buf->ieba1);
++ break;
++ default:
++ BUG();
++ break;
++ }
++ if (!(data & VDOAC_PFS_YUYV))
++ vdoa_read_register(vdoa, VDOAIUBO, &buf->iubo);
++}
++
++int vdoa_start(vdoa_handle_t handle, int timeout_ms)
++{
++ int ret;
++ struct vdoa_info *vdoa = (struct vdoa_info *)handle;
++
++ CHECK_NULL_PTR(vdoa);
++ CHECK_STATE(VDOA_GET_OBUF, return -EINVAL);
++ vdoa->state = VDOA_START;
++ init_completion(&vdoa->comp);
++ vdoa_write_register(vdoa, VDOAIST,
++ VDOAIEIST_TRANSFER_ERR | VDOAIEIST_TRANSFER_END);
++ vdoa_write_register(vdoa, VDOAIE,
++ VDOAIEIST_TRANSFER_ERR | VDOAIEIST_TRANSFER_END);
++
++ enable_irq(vdoa->irq);
++ vdoa_write_register(vdoa, VDOASRR, VDOASRR_START_XFER);
++ dump_registers(vdoa);
++
++ ret = wait_for_completion_timeout(&vdoa->comp,
++ msecs_to_jiffies(timeout_ms));
++
++ return ret > 0 ? 0 : -ETIMEDOUT;
++}
++
++void vdoa_stop(vdoa_handle_t handle)
++{
++ struct vdoa_info *vdoa = (struct vdoa_info *)handle;
++
++ CHECK_NULL_PTR(vdoa);
++ CHECK_STATE(VDOA_GET | VDOA_START | VDOA_INIRQ, return);
++ vdoa->state = VDOA_STOP;
++
++ disable_irq(vdoa->irq);
++
++ vdoa_write_register(vdoa, VDOASRR, VDOASRR_SWRST);
++}
++
++void vdoa_get_handle(vdoa_handle_t *handle)
++{
++ struct vdoa_info *vdoa = g_vdoa;
++
++ CHECK_NULL_PTR(handle);
++ *handle = (vdoa_handle_t *)NULL;
++ CHECK_STATE(VDOA_INIT, return);
++ mutex_lock(&vdoa_lock);
++ clk_prepare_enable(vdoa->vdoa_clk);
++ vdoa->state = VDOA_GET;
++ vdoa->field = VDOA_NULL;
++ vdoa_write_register(vdoa, VDOASRR, VDOASRR_SWRST);
++
++ *handle = (vdoa_handle_t *)vdoa;
++}
++
++void vdoa_put_handle(vdoa_handle_t *handle)
++{
++ struct vdoa_info *vdoa = (struct vdoa_info *)(*handle);
++
++ CHECK_NULL_PTR(vdoa);
++ CHECK_STATE(VDOA_STOP, return);
++ if (vdoa != g_vdoa)
++ BUG();
++
++ clk_disable_unprepare(vdoa->vdoa_clk);
++ vdoa->state = VDOA_PUT;
++ *handle = (vdoa_handle_t *)NULL;
++ mutex_unlock(&vdoa_lock);
++}
++
++static irqreturn_t vdoa_irq_handler(int irq, void *data)
++{
++ u32 status, mask, val;
++ struct vdoa_info *vdoa = data;
++
++ CHECK_NULL_PTR(vdoa);
++ CHECK_STATE(VDOA_START, return IRQ_HANDLED);
++ vdoa->state = VDOA_INIRQ;
++ vdoa_read_register(vdoa, VDOAIST, &status);
++ vdoa_read_register(vdoa, VDOAIE, &mask);
++ val = status & mask;
++ vdoa_write_register(vdoa, VDOAIST, val);
++ if (VDOAIEIST_TRANSFER_ERR & val)
++ dev_err(vdoa->dev, "vdoa Transfer err irq!\n");
++ if (VDOAIEIST_TRANSFER_END & val)
++ dev_dbg(vdoa->dev, "vdoa Transfer end irq!\n");
++ if (0 == val) {
++ dev_err(vdoa->dev, "vdoa unknown irq!\n");
++ BUG();
++ }
++
++ complete(&vdoa->comp);
++ return IRQ_HANDLED;
++}
++
++/* IRAM Size in Kbytes, example:vdoa_iram_size=64, 64KBytes */
++static int __init vdoa_iram_size_setup(char *options)
++{
++ int ret;
++
++ ret = kstrtol(options, 0, &iram_size);
++ if (ret)
++ iram_size = 0;
++ else
++ iram_size *= SZ_1K;
++
++ return 1;
++}
++__setup("vdoa_iram_size=", vdoa_iram_size_setup);
++
++static const struct of_device_id imx_vdoa_dt_ids[] = {
++ { .compatible = "fsl,imx6q-vdoa", },
++ { /* sentinel */ }
++};
++
++static int vdoa_probe(struct platform_device *pdev)
++{
++ int ret;
++ struct vdoa_info *vdoa;
++ struct resource *res;
++ struct resource *res_irq;
++ struct device *dev = &pdev->dev;
++ struct device_node *np = pdev->dev.of_node;
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (!res) {
++ dev_err(dev, "can't get device resources\n");
++ return -ENOENT;
++ }
++
++ res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
++ if (!res_irq) {
++ dev_err(dev, "failed to get irq resource\n");
++ return -ENOENT;
++ }
++
++ vdoa = devm_kzalloc(dev, sizeof(struct vdoa_info), GFP_KERNEL);
++ if (!vdoa)
++ return -ENOMEM;
++ vdoa->dev = dev;
++
++ vdoa->reg_base = devm_ioremap_resource(&pdev->dev, res);
++ if (!vdoa->reg_base)
++ return -EBUSY;
++
++ vdoa->irq = res_irq->start;
++ ret = devm_request_irq(dev, vdoa->irq, vdoa_irq_handler, 0,
++ "vdoa", vdoa);
++ if (ret) {
++ dev_err(dev, "can't claim irq %d\n", vdoa->irq);
++ return ret;
++ }
++ disable_irq(vdoa->irq);
++
++ vdoa->vdoa_clk = devm_clk_get(dev, NULL);
++ if (IS_ERR(vdoa->vdoa_clk)) {
++ dev_err(dev, "failed to get vdoa_clk\n");
++ return PTR_ERR(vdoa->vdoa_clk);
++ }
++
++ vdoa->iram_pool = of_get_named_gen_pool(np, "iram", 0);
++ if (!vdoa->iram_pool) {
++ dev_err(&pdev->dev, "iram pool not available\n");
++ return -ENOMEM;
++ }
++
++ if ((iram_size == 0) || (iram_size > MAX_VDOA_IRAM_SIZE))
++ iram_size = VDOA_IRAM_SIZE;
++
++ vdoa->iram_base = gen_pool_alloc(vdoa->iram_pool, iram_size);
++ if (!vdoa->iram_base) {
++ dev_err(&pdev->dev, "unable to alloc iram\n");
++ return -ENOMEM;
++ }
++
++ vdoa->iram_paddr = gen_pool_virt_to_phys(vdoa->iram_pool,
++ vdoa->iram_base);
++
++ dev_dbg(dev, "iram_base:0x%lx,iram_paddr:0x%lx,size:0x%lx\n",
++ vdoa->iram_base, vdoa->iram_paddr, iram_size);
++
++ vdoa->state = VDOA_INIT;
++ dev_set_drvdata(dev, vdoa);
++ g_vdoa = vdoa;
++ dev_info(dev, "i.MX Video Data Order Adapter(VDOA) driver probed\n");
++ return 0;
++}
++
++static int vdoa_remove(struct platform_device *pdev)
++{
++ struct vdoa_info *vdoa = dev_get_drvdata(&pdev->dev);
++
++ gen_pool_free(vdoa->iram_pool, vdoa->iram_base, iram_size);
++ kfree(vdoa);
++ dev_set_drvdata(&pdev->dev, NULL);
++
++ return 0;
++}
++
++static struct platform_driver vdoa_driver = {
++ .driver = {
++ .name = "mxc_vdoa",
++ .of_match_table = imx_vdoa_dt_ids,
++ },
++ .probe = vdoa_probe,
++ .remove = vdoa_remove,
++};
++
++static int __init vdoa_init(void)
++{
++ int err;
++
++ err = platform_driver_register(&vdoa_driver);
++ if (err) {
++ pr_err("vdoa_driver register failed\n");
++ return -ENODEV;
++ }
++ return 0;
++}
++
++static void __exit vdoa_cleanup(void)
++{
++ platform_driver_unregister(&vdoa_driver);
++}
++
++module_init(vdoa_init);
++module_exit(vdoa_cleanup);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("i.MX Video Data Order Adapter(VDOA) driver");
++MODULE_LICENSE("GPL");
+diff -Nur linux-4.1.3/drivers/mxc/ipu3/vdoa.h linux-xbian-imx6/drivers/mxc/ipu3/vdoa.h
+--- linux-4.1.3/drivers/mxc/ipu3/vdoa.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/ipu3/vdoa.h 2015-07-27 23:13:06.230751680 +0200
+@@ -0,0 +1,69 @@
++/*
++ * Copyright (C) 2012-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++#ifndef __VDOA_H__
++#define __VDOA_H__
++
++#define VDOA_PFS_YUYV (1)
++#define VDOA_PFS_NV12 (0)
++
++
++struct vfield_buf {
++ u32 prev_veba;
++ u32 cur_veba;
++ u32 next_veba;
++ u32 vubo;
++};
++
++struct vframe_buf {
++ u32 veba;
++ u32 vubo;
++};
++
++struct vdoa_params {
++ u32 width;
++ u32 height;
++ int vpu_stride;
++ int interlaced;
++ int scan_order;
++ int ipu_num;
++ int band_lines;
++ int band_mode;
++ int pfs;
++ u32 ieba0;
++ u32 ieba1;
++ u32 ieba2;
++ struct vframe_buf vframe_buf;
++ struct vfield_buf vfield_buf;
++};
++struct vdoa_ipu_buf {
++ u32 ieba0;
++ u32 ieba1;
++ u32 iubo;
++};
++
++struct vdoa_info;
++typedef void *vdoa_handle_t;
++
++int vdoa_setup(vdoa_handle_t handle, struct vdoa_params *params);
++void vdoa_get_output_buf(vdoa_handle_t handle, struct vdoa_ipu_buf *buf);
++int vdoa_start(vdoa_handle_t handle, int timeout_ms);
++void vdoa_stop(vdoa_handle_t handle);
++void vdoa_get_handle(vdoa_handle_t *handle);
++void vdoa_put_handle(vdoa_handle_t *handle);
++#endif
+diff -Nur linux-4.1.3/drivers/mxc/Kconfig linux-xbian-imx6/drivers/mxc/Kconfig
+--- linux-4.1.3/drivers/mxc/Kconfig 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/Kconfig 2015-07-27 23:13:06.166979215 +0200
+@@ -0,0 +1,25 @@
++# drivers/mxc/Kconfig
++
++if ARCH_MXC
++
++menu "MXC support drivers"
++
++config MXC_IPU
++ tristate "Image Processing Unit Driver"
++ select MXC_IPU_V3_FSL
++ depends on !IMX_IPUV3_CORE
++ help
++ If you plan to use the Image Processing unit, say
++ Y here. IPU is needed by Framebuffer and V4L2 drivers.
++
++source "drivers/mxc/gpu-viv/Kconfig"
++source "drivers/mxc/ipu3/Kconfig"
++source "drivers/mxc/asrc/Kconfig"
++source "drivers/mxc/vpu/Kconfig"
++source "drivers/mxc/hdmi-cec/Kconfig"
++source "drivers/mxc/mipi/Kconfig"
++source "drivers/mxc/mlb/Kconfig"
++
++endmenu
++
++endif
+diff -Nur linux-4.1.3/drivers/mxc/Makefile linux-xbian-imx6/drivers/mxc/Makefile
+--- linux-4.1.3/drivers/mxc/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/Makefile 2015-07-27 23:13:06.166979215 +0200
+@@ -0,0 +1,7 @@
++obj-$(CONFIG_MXC_GPU_VIV) += gpu-viv/
++obj-$(CONFIG_MXC_IPU_V3_FSL) += ipu3/
++obj-$(CONFIG_MXC_ASRC) += asrc/
++obj-$(CONFIG_MXC_VPU) += vpu/
++obj-$(CONFIG_MXC_HDMI_CEC) += hdmi-cec/
++obj-$(CONFIG_MXC_MIPI_CSI2) += mipi/
++obj-$(CONFIG_MXC_MLB) += mlb/
+diff -Nur linux-4.1.3/drivers/mxc/mipi/Kconfig linux-xbian-imx6/drivers/mxc/mipi/Kconfig
+--- linux-4.1.3/drivers/mxc/mipi/Kconfig 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/mipi/Kconfig 2015-07-27 23:13:06.230751680 +0200
+@@ -0,0 +1,14 @@
++#
++# MIPI configuration
++#
++
++menu "MXC MIPI Support"
++
++config MXC_MIPI_CSI2
++ tristate "MIPI CSI2 support"
++ depends on SOC_IMX6Q
++ default n
++ ---help---
++ Say Y to get the MIPI CSI2 support.
++
++endmenu
+diff -Nur linux-4.1.3/drivers/mxc/mipi/Makefile linux-xbian-imx6/drivers/mxc/mipi/Makefile
+--- linux-4.1.3/drivers/mxc/mipi/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/mipi/Makefile 2015-07-27 23:13:06.230751680 +0200
+@@ -0,0 +1,4 @@
++#
++# Makefile for the mipi interface driver
++#
++obj-$(CONFIG_MXC_MIPI_CSI2) += mxc_mipi_csi2.o
+diff -Nur linux-4.1.3/drivers/mxc/mipi/mxc_mipi_csi2.c linux-xbian-imx6/drivers/mxc/mipi/mxc_mipi_csi2.c
+--- linux-4.1.3/drivers/mxc/mipi/mxc_mipi_csi2.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/mipi/mxc_mipi_csi2.c 2015-07-27 23:13:06.230751680 +0200
+@@ -0,0 +1,540 @@
++/*
++ * Copyright (C) 2011-2014 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++#include <linux/module.h>
++#include <linux/types.h>
++#include <linux/interrupt.h>
++#include <linux/irq.h>
++#include <linux/irqdesc.h>
++#include <linux/init.h>
++#include <linux/platform_device.h>
++#include <linux/err.h>
++#include <linux/clk.h>
++#include <linux/console.h>
++#include <linux/io.h>
++#include <linux/bitops.h>
++#include <linux/delay.h>
++#include <linux/fsl_devices.h>
++#include <linux/slab.h>
++#include <linux/of.h>
++
++#include <linux/mipi_csi2.h>
++
++#include "mxc_mipi_csi2.h"
++
++static struct mipi_csi2_info *gmipi_csi2;
++
++void _mipi_csi2_lock(struct mipi_csi2_info *info)
++{
++ if (!in_irq() && !in_softirq())
++ mutex_lock(&info->mutex_lock);
++}
++
++void _mipi_csi2_unlock(struct mipi_csi2_info *info)
++{
++ if (!in_irq() && !in_softirq())
++ mutex_unlock(&info->mutex_lock);
++}
++
++static inline void mipi_csi2_write(struct mipi_csi2_info *info,
++ unsigned value, unsigned offset)
++{
++ writel(value, info->mipi_csi2_base + offset);
++}
++
++static inline unsigned int mipi_csi2_read(struct mipi_csi2_info *info,
++ unsigned offset)
++{
++ return readl(info->mipi_csi2_base + offset);
++}
++
++/*!
++ * This function is called to enable the mipi csi2 interface.
++ *
++ * @param info mipi csi2 hander
++ * @return Returns setted value
++ */
++bool mipi_csi2_enable(struct mipi_csi2_info *info)
++{
++ bool status;
++
++ _mipi_csi2_lock(info);
++
++ if (!info->mipi_en) {
++ info->mipi_en = true;
++ clk_prepare_enable(info->cfg_clk);
++ clk_prepare_enable(info->dphy_clk);
++ } else
++ mipi_dbg("mipi csi2 already enabled!\n");
++
++ status = info->mipi_en;
++
++ _mipi_csi2_unlock(info);
++
++ return status;
++}
++EXPORT_SYMBOL(mipi_csi2_enable);
++
++/*!
++ * This function is called to disable the mipi csi2 interface.
++ *
++ * @param info mipi csi2 hander
++ * @return Returns setted value
++ */
++bool mipi_csi2_disable(struct mipi_csi2_info *info)
++{
++ bool status;
++
++ _mipi_csi2_lock(info);
++
++ if (info->mipi_en) {
++ info->mipi_en = false;
++ clk_disable_unprepare(info->dphy_clk);
++ clk_disable_unprepare(info->cfg_clk);
++ } else
++ mipi_dbg("mipi csi2 already disabled!\n");
++
++ status = info->mipi_en;
++
++ _mipi_csi2_unlock(info);
++
++ return status;
++}
++EXPORT_SYMBOL(mipi_csi2_disable);
++
++/*!
++ * This function is called to get mipi csi2 disable/enable status.
++ *
++ * @param info mipi csi2 hander
++ * @return Returns mipi csi2 status
++ */
++bool mipi_csi2_get_status(struct mipi_csi2_info *info)
++{
++ bool status;
++
++ _mipi_csi2_lock(info);
++ status = info->mipi_en;
++ _mipi_csi2_unlock(info);
++
++ return status;
++}
++EXPORT_SYMBOL(mipi_csi2_get_status);
++
++/*!
++ * This function is called to set mipi lanes.
++ *
++ * @param info mipi csi2 hander
++ * @return Returns setted value
++ */
++unsigned int mipi_csi2_set_lanes(struct mipi_csi2_info *info)
++{
++ unsigned int lanes;
++
++ _mipi_csi2_lock(info);
++ mipi_csi2_write(info, info->lanes - 1, MIPI_CSI2_N_LANES);
++ lanes = mipi_csi2_read(info, MIPI_CSI2_N_LANES);
++ _mipi_csi2_unlock(info);
++
++ return lanes;
++}
++EXPORT_SYMBOL(mipi_csi2_set_lanes);
++
++/*!
++ * This function is called to set mipi data type.
++ *
++ * @param info mipi csi2 hander
++ * @return Returns setted value
++ */
++unsigned int mipi_csi2_set_datatype(struct mipi_csi2_info *info,
++ unsigned int datatype)
++{
++ unsigned int dtype;
++
++ _mipi_csi2_lock(info);
++ info->datatype = datatype;
++ dtype = info->datatype;
++ _mipi_csi2_unlock(info);
++
++ return dtype;
++}
++EXPORT_SYMBOL(mipi_csi2_set_datatype);
++
++/*!
++ * This function is called to get mipi data type.
++ *
++ * @param info mipi csi2 hander
++ * @return Returns mipi data type
++ */
++unsigned int mipi_csi2_get_datatype(struct mipi_csi2_info *info)
++{
++ unsigned int dtype;
++
++ _mipi_csi2_lock(info);
++ dtype = info->datatype;
++ _mipi_csi2_unlock(info);
++
++ return dtype;
++}
++EXPORT_SYMBOL(mipi_csi2_get_datatype);
++
++/*!
++ * This function is called to get mipi csi2 dphy status.
++ *
++ * @param info mipi csi2 hander
++ * @return Returns dphy status
++ */
++unsigned int mipi_csi2_dphy_status(struct mipi_csi2_info *info)
++{
++ unsigned int status;
++
++ _mipi_csi2_lock(info);
++ status = mipi_csi2_read(info, MIPI_CSI2_PHY_STATE);
++ _mipi_csi2_unlock(info);
++
++ return status;
++}
++EXPORT_SYMBOL(mipi_csi2_dphy_status);
++
++/*!
++ * This function is called to get mipi csi2 error1 status.
++ *
++ * @param info mipi csi2 hander
++ * @return Returns error1 value
++ */
++unsigned int mipi_csi2_get_error1(struct mipi_csi2_info *info)
++{
++ unsigned int err1;
++
++ _mipi_csi2_lock(info);
++ err1 = mipi_csi2_read(info, MIPI_CSI2_ERR1);
++ _mipi_csi2_unlock(info);
++
++ return err1;
++}
++EXPORT_SYMBOL(mipi_csi2_get_error1);
++
++/*!
++ * This function is called to get mipi csi2 error1 status.
++ *
++ * @param info mipi csi2 hander
++ * @return Returns error1 value
++ */
++unsigned int mipi_csi2_get_error2(struct mipi_csi2_info *info)
++{
++ unsigned int err2;
++
++ _mipi_csi2_lock(info);
++ err2 = mipi_csi2_read(info, MIPI_CSI2_ERR2);
++ _mipi_csi2_unlock(info);
++
++ return err2;
++}
++EXPORT_SYMBOL(mipi_csi2_get_error2);
++
++/*!
++ * This function is called to enable mipi to ipu pixel clock.
++ *
++ * @param info mipi csi2 hander
++ * @return Returns 0 on success or negative error code on fail
++ */
++int mipi_csi2_pixelclk_enable(struct mipi_csi2_info *info)
++{
++ return clk_prepare_enable(info->pixel_clk);
++}
++EXPORT_SYMBOL(mipi_csi2_pixelclk_enable);
++
++/*!
++ * This function is called to disable mipi to ipu pixel clock.
++ *
++ * @param info mipi csi2 hander
++ * @return Returns 0 on success or negative error code on fail
++ */
++void mipi_csi2_pixelclk_disable(struct mipi_csi2_info *info)
++{
++ clk_disable_unprepare(info->pixel_clk);
++}
++EXPORT_SYMBOL(mipi_csi2_pixelclk_disable);
++
++/*!
++ * This function is called to power on mipi csi2.
++ *
++ * @param info mipi csi2 hander
++ * @return Returns 0 on success or negative error code on fail
++ */
++int mipi_csi2_reset(struct mipi_csi2_info *info)
++{
++ _mipi_csi2_lock(info);
++
++ mipi_csi2_write(info, 0x0, MIPI_CSI2_PHY_SHUTDOWNZ);
++ mipi_csi2_write(info, 0x0, MIPI_CSI2_DPHY_RSTZ);
++ mipi_csi2_write(info, 0x0, MIPI_CSI2_CSI2_RESETN);
++
++ mipi_csi2_write(info, 0x00000001, MIPI_CSI2_PHY_TST_CTRL0);
++ mipi_csi2_write(info, 0x00000000, MIPI_CSI2_PHY_TST_CTRL1);
++ mipi_csi2_write(info, 0x00000000, MIPI_CSI2_PHY_TST_CTRL0);
++ mipi_csi2_write(info, 0x00000002, MIPI_CSI2_PHY_TST_CTRL0);
++ mipi_csi2_write(info, 0x00010044, MIPI_CSI2_PHY_TST_CTRL1);
++ mipi_csi2_write(info, 0x00000000, MIPI_CSI2_PHY_TST_CTRL0);
++ mipi_csi2_write(info, 0x00000014, MIPI_CSI2_PHY_TST_CTRL1);
++ mipi_csi2_write(info, 0x00000002, MIPI_CSI2_PHY_TST_CTRL0);
++ mipi_csi2_write(info, 0x00000000, MIPI_CSI2_PHY_TST_CTRL0);
++
++ mipi_csi2_write(info, 0xffffffff, MIPI_CSI2_PHY_SHUTDOWNZ);
++ mipi_csi2_write(info, 0xffffffff, MIPI_CSI2_DPHY_RSTZ);
++ mipi_csi2_write(info, 0xffffffff, MIPI_CSI2_CSI2_RESETN);
++
++ _mipi_csi2_unlock(info);
++
++ return 0;
++}
++EXPORT_SYMBOL(mipi_csi2_reset);
++
++/*!
++ * This function is called to get mipi csi2 info.
++ *
++ * @return Returns mipi csi2 info struct pointor
++ */
++struct mipi_csi2_info *mipi_csi2_get_info(void)
++{
++ return gmipi_csi2;
++}
++EXPORT_SYMBOL(mipi_csi2_get_info);
++
++/*!
++ * This function is called to get mipi csi2 bind ipu num.
++ *
++ * @return Returns mipi csi2 bind ipu num
++ */
++int mipi_csi2_get_bind_ipu(struct mipi_csi2_info *info)
++{
++ int ipu_id;
++
++ _mipi_csi2_lock(info);
++ ipu_id = info->ipu_id;
++ _mipi_csi2_unlock(info);
++
++ return ipu_id;
++}
++EXPORT_SYMBOL(mipi_csi2_get_bind_ipu);
++
++/*!
++ * This function is called to get mipi csi2 bind csi num.
++ *
++ * @return Returns mipi csi2 bind csi num
++ */
++unsigned int mipi_csi2_get_bind_csi(struct mipi_csi2_info *info)
++{
++ unsigned int csi_id;
++
++ _mipi_csi2_lock(info);
++ csi_id = info->csi_id;
++ _mipi_csi2_unlock(info);
++
++ return csi_id;
++}
++EXPORT_SYMBOL(mipi_csi2_get_bind_csi);
++
++/*!
++ * This function is called to get mipi csi2 virtual channel.
++ *
++ * @return Returns mipi csi2 virtual channel num
++ */
++unsigned int mipi_csi2_get_virtual_channel(struct mipi_csi2_info *info)
++{
++ unsigned int v_channel;
++
++ _mipi_csi2_lock(info);
++ v_channel = info->v_channel;
++ _mipi_csi2_unlock(info);
++
++ return v_channel;
++}
++EXPORT_SYMBOL(mipi_csi2_get_virtual_channel);
++
++/**
++ * This function is called by the driver framework to initialize the MIPI CSI2
++ * device.
++ *
++ * @param pdev The device structure for the MIPI CSI2 passed in by the
++ * driver framework.
++ *
++ * @return Returns 0 on success or negative error code on error
++ */
++static int mipi_csi2_probe(struct platform_device *pdev)
++{
++ struct device *dev = &pdev->dev;
++ struct device_node *np = pdev->dev.of_node;
++ struct resource *res;
++ u32 mipi_csi2_dphy_ver;
++ int ret;
++
++ gmipi_csi2 = kmalloc(sizeof(struct mipi_csi2_info), GFP_KERNEL);
++ if (!gmipi_csi2) {
++ ret = -ENOMEM;
++ goto alloc_failed;
++ }
++
++ ret = of_property_read_u32(np, "ipu_id", &(gmipi_csi2->ipu_id));
++ if (ret) {
++ dev_err(&pdev->dev, "ipu_id missing or invalid\n");
++ goto err;
++ }
++
++ ret = of_property_read_u32(np, "csi_id", &(gmipi_csi2->csi_id));
++ if (ret) {
++ dev_err(&pdev->dev, "csi_id missing or invalid\n");
++ goto err;
++ }
++
++ ret = of_property_read_u32(np, "v_channel", &(gmipi_csi2->v_channel));
++ if (ret) {
++ dev_err(&pdev->dev, "v_channel missing or invalid\n");
++ goto err;
++ }
++
++ ret = of_property_read_u32(np, "lanes", &(gmipi_csi2->lanes));
++ if (ret) {
++ dev_err(&pdev->dev, "lanes missing or invalid\n");
++ goto err;
++ }
++
++ if ((gmipi_csi2->ipu_id < 0) || (gmipi_csi2->ipu_id > 1) ||
++ (gmipi_csi2->csi_id > 1) || (gmipi_csi2->v_channel > 3) ||
++ (gmipi_csi2->lanes > 4)) {
++ dev_err(&pdev->dev, "invalid param for mipi csi2!\n");
++ ret = -EINVAL;
++ goto err;
++ }
++
++ /* initialize mutex */
++ mutex_init(&gmipi_csi2->mutex_lock);
++
++ /* get mipi csi2 informaiton */
++ gmipi_csi2->pdev = pdev;
++ gmipi_csi2->mipi_en = false;
++
++ gmipi_csi2->cfg_clk = devm_clk_get(dev, "cfg_clk");
++ if (IS_ERR(gmipi_csi2->cfg_clk)) {
++ dev_err(&pdev->dev, "failed to get cfg_clk\n");
++ ret = PTR_ERR(gmipi_csi2->cfg_clk);
++ goto err;
++ }
++
++ /* get mipi dphy clk */
++ gmipi_csi2->dphy_clk = devm_clk_get(dev, "dphy_clk");
++ if (IS_ERR(gmipi_csi2->dphy_clk)) {
++ dev_err(&pdev->dev, "failed to get dphy pll_ref_clk\n");
++ ret = PTR_ERR(gmipi_csi2->dphy_clk);
++ goto err;
++ }
++
++ /* get mipi to ipu pixel clk */
++ gmipi_csi2->pixel_clk = devm_clk_get(dev, "pixel_clk");
++ if (IS_ERR(gmipi_csi2->pixel_clk)) {
++ dev_err(&pdev->dev, "failed to get mipi pixel clk\n");
++ ret = PTR_ERR(gmipi_csi2->pixel_clk);
++ goto err;
++ }
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (!res) {
++ ret = -ENODEV;
++ goto err;
++ }
++
++ /* mipi register mapping */
++ gmipi_csi2->mipi_csi2_base = ioremap(res->start, PAGE_SIZE);
++ if (!gmipi_csi2->mipi_csi2_base) {
++ ret = -ENOMEM;
++ goto err;
++ }
++
++ /* mipi dphy clk enable for register access */
++ clk_prepare_enable(gmipi_csi2->dphy_clk);
++ /* get mipi csi2 dphy version */
++ mipi_csi2_dphy_ver = mipi_csi2_read(gmipi_csi2, MIPI_CSI2_VERSION);
++
++ clk_disable_unprepare(gmipi_csi2->dphy_clk);
++
++ platform_set_drvdata(pdev, gmipi_csi2);
++
++ dev_info(&pdev->dev, "i.MX MIPI CSI2 driver probed\n");
++ dev_info(&pdev->dev, "i.MX MIPI CSI2 dphy version is 0x%x\n",
++ mipi_csi2_dphy_ver);
++
++ return 0;
++
++err:
++ kfree(gmipi_csi2);
++alloc_failed:
++ dev_err(&pdev->dev, "i.MX MIPI CSI2 driver probed - error\n");
++ return ret;
++}
++
++static int mipi_csi2_remove(struct platform_device *pdev)
++{
++ /* unmapping mipi register */
++ iounmap(gmipi_csi2->mipi_csi2_base);
++
++ kfree(gmipi_csi2);
++
++ dev_set_drvdata(&pdev->dev, NULL);
++
++ return 0;
++}
++
++static const struct of_device_id imx_mipi_csi2_dt_ids[] = {
++ { .compatible = "fsl,imx6q-mipi-csi2", },
++ { /* sentinel */ }
++};
++
++static struct platform_driver mipi_csi2_driver = {
++ .driver = {
++ .name = "mxc_mipi_csi2",
++ .of_match_table = imx_mipi_csi2_dt_ids,
++ },
++ .probe = mipi_csi2_probe,
++ .remove = mipi_csi2_remove,
++};
++
++static int __init mipi_csi2_init(void)
++{
++ int err;
++
++ err = platform_driver_register(&mipi_csi2_driver);
++ if (err) {
++ pr_err("mipi_csi2_driver register failed\n");
++ return -ENODEV;
++ }
++
++ pr_info("MIPI CSI2 driver module loaded\n");
++
++ return 0;
++}
++
++static void __exit mipi_csi2_cleanup(void)
++{
++ platform_driver_unregister(&mipi_csi2_driver);
++}
++
++subsys_initcall(mipi_csi2_init);
++module_exit(mipi_csi2_cleanup);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("i.MX MIPI CSI2 driver");
++MODULE_LICENSE("GPL");
+diff -Nur linux-4.1.3/drivers/mxc/mipi/mxc_mipi_csi2.h linux-xbian-imx6/drivers/mxc/mipi/mxc_mipi_csi2.h
+--- linux-4.1.3/drivers/mxc/mipi/mxc_mipi_csi2.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/mipi/mxc_mipi_csi2.h 2015-07-27 23:13:06.230751680 +0200
+@@ -0,0 +1,46 @@
++/*
++ * Copyright (C) 2011-2014 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++#ifndef __MXC_MIPI_CSI2_H__
++#define __MXC_MIPI_CSI2_H__
++
++#ifdef DEBUG
++#define mipi_dbg(fmt, ...) \
++ printk(KERN_DEBUG pr_fmt(fmt), ##__VA_ARGS__)
++#else
++#define mipi_dbg(fmt, ...)
++#endif
++
++/* driver private data */
++struct mipi_csi2_info {
++ bool mipi_en;
++ int ipu_id;
++ unsigned int csi_id;
++ unsigned int v_channel;
++ unsigned int lanes;
++ unsigned int datatype;
++ struct clk *cfg_clk;
++ struct clk *dphy_clk;
++ struct clk *pixel_clk;
++ void __iomem *mipi_csi2_base;
++ struct platform_device *pdev;
++
++ struct mutex mutex_lock;
++};
++
++#endif
+diff -Nur linux-4.1.3/drivers/mxc/mlb/Kconfig linux-xbian-imx6/drivers/mxc/mlb/Kconfig
+--- linux-4.1.3/drivers/mxc/mlb/Kconfig 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/mlb/Kconfig 2015-07-27 23:13:06.230751680 +0200
+@@ -0,0 +1,17 @@
++#
++# MLB150 configuration
++#
++
++menu "MXC Media Local Bus Driver"
++
++config MXC_MLB
++ boolean
++
++config MXC_MLB150
++ tristate "MLB150 support"
++ depends on SOC_IMX6Q
++ select MXC_MLB
++ ---help---
++ Say Y to get the MLB150 support.
++
++endmenu
+diff -Nur linux-4.1.3/drivers/mxc/mlb/Makefile linux-xbian-imx6/drivers/mxc/mlb/Makefile
+--- linux-4.1.3/drivers/mxc/mlb/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/mlb/Makefile 2015-07-27 23:13:06.230751680 +0200
+@@ -0,0 +1,5 @@
++#
++# Makefile for the i.MX6Q/DL MLB150 driver
++#
++
++obj-$(CONFIG_MXC_MLB150) += mxc_mlb150.o
+diff -Nur linux-4.1.3/drivers/mxc/mlb/mxc_mlb150.c linux-xbian-imx6/drivers/mxc/mlb/mxc_mlb150.c
+--- linux-4.1.3/drivers/mxc/mlb/mxc_mlb150.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/mlb/mxc_mlb150.c 2015-07-27 23:13:06.230751680 +0200
+@@ -0,0 +1,2778 @@
++/*
++ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++#include <linux/cdev.h>
++#include <linux/circ_buf.h>
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/device.h>
++#include <linux/errno.h>
++#include <linux/fs.h>
++#include <linux/genalloc.h>
++#include <linux/init.h>
++#include <linux/interrupt.h>
++#include <linux/io.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/mxc_mlb.h>
++#include <linux/of.h>
++#include <linux/platform_device.h>
++#include <linux/poll.h>
++#include <linux/regulator/consumer.h>
++#include <linux/sched.h>
++#include <linux/slab.h>
++#include <linux/spinlock.h>
++#include <linux/uaccess.h>
++
++#define DRIVER_NAME "mxc_mlb150"
++
++/*
++ * MLB module memory map registers define
++ */
++#define REG_MLBC0 0x0
++#define MLBC0_MLBEN (0x1)
++#define MLBC0_MLBCLK_MASK (0x7 << 2)
++#define MLBC0_MLBCLK_SHIFT (2)
++#define MLBC0_MLBPEN (0x1 << 5)
++#define MLBC0_MLBLK (0x1 << 7)
++#define MLBC0_ASYRETRY (0x1 << 12)
++#define MLBC0_CTLRETRY (0x1 << 12)
++#define MLBC0_FCNT_MASK (0x7 << 15)
++#define MLBC0_FCNT_SHIFT (15)
++
++#define REG_MLBPC0 0x8
++#define MLBPC0_MCLKHYS (0x1 << 11)
++
++#define REG_MS0 0xC
++#define REG_MS1 0x14
++
++#define REG_MSS 0x20
++#define MSS_RSTSYSCMD (0x1)
++#define MSS_LKSYSCMD (0x1 << 1)
++#define MSS_ULKSYSCMD (0x1 << 2)
++#define MSS_CSSYSCMD (0x1 << 3)
++#define MSS_SWSYSCMD (0x1 << 4)
++#define MSS_SERVREQ (0x1 << 5)
++
++#define REG_MSD 0x24
++
++#define REG_MIEN 0x2C
++#define MIEN_ISOC_PE (0x1)
++#define MIEN_ISOC_BUFO (0x1 << 1)
++#define MIEN_SYNC_PE (0x1 << 16)
++#define MIEN_ARX_DONE (0x1 << 17)
++#define MIEN_ARX_PE (0x1 << 18)
++#define MIEN_ARX_BREAK (0x1 << 19)
++#define MIEN_ATX_DONE (0x1 << 20)
++#define MIEN_ATX_PE (0x1 << 21)
++#define MIEN_ATX_BREAK (0x1 << 22)
++#define MIEN_CRX_DONE (0x1 << 24)
++#define MIEN_CRX_PE (0x1 << 25)
++#define MIEN_CRX_BREAK (0x1 << 26)
++#define MIEN_CTX_DONE (0x1 << 27)
++#define MIEN_CTX_PE (0x1 << 28)
++#define MIEN_CTX_BREAK (0x1 << 29)
++
++#define REG_MLBPC2 0x34
++#define REG_MLBPC1 0x38
++#define MLBPC1_VAL (0x00000888)
++
++#define REG_MLBC1 0x3C
++#define MLBC1_LOCK (0x1 << 6)
++#define MLBC1_CLKM (0x1 << 7)
++#define MLBC1_NDA_MASK (0xFF << 8)
++#define MLBC1_NDA_SHIFT (8)
++
++#define REG_HCTL 0x80
++#define HCTL_RST0 (0x1)
++#define HCTL_RST1 (0x1 << 1)
++#define HCTL_EN (0x1 << 15)
++
++#define REG_HCMR0 0x88
++#define REG_HCMR1 0x8C
++#define REG_HCER0 0x90
++#define REG_HCER1 0x94
++#define REG_HCBR0 0x98
++#define REG_HCBR1 0x9C
++
++#define REG_MDAT0 0xC0
++#define REG_MDAT1 0xC4
++#define REG_MDAT2 0xC8
++#define REG_MDAT3 0xCC
++
++#define REG_MDWE0 0xD0
++#define REG_MDWE1 0xD4
++#define REG_MDWE2 0xD8
++#define REG_MDWE3 0xDC
++
++#define REG_MCTL 0xE0
++#define MCTL_XCMP (0x1)
++
++#define REG_MADR 0xE4
++#define MADR_WNR (0x1 << 31)
++#define MADR_TB (0x1 << 30)
++#define MADR_ADDR_MASK (0x7f << 8)
++#define MADR_ADDR_SHIFT (0)
++
++#define REG_ACTL 0x3C0
++#define ACTL_MPB (0x1 << 4)
++#define ACTL_DMAMODE (0x1 << 2)
++#define ACTL_SMX (0x1 << 1)
++#define ACTL_SCE (0x1)
++
++#define REG_ACSR0 0x3D0
++#define REG_ACSR1 0x3D4
++#define REG_ACMR0 0x3D8
++#define REG_ACMR1 0x3DC
++
++#define REG_CAT_MDATn(ch) (REG_MDAT0 + ((ch % 8) >> 1) * 4)
++#define REG_CAT_MDWEn(ch) (REG_MDWE0 + ((ch % 8) >> 1) * 4)
++
++#define INT_AHB0_CH_START (0)
++#define INT_AHB1_CH_START (32)
++
++#define LOGIC_CH_NUM (64)
++#define BUF_CDT_OFFSET (0x0)
++#define BUF_ADT_OFFSET (0x40)
++#define BUF_CAT_MLB_OFFSET (0x80)
++#define BUF_CAT_HBI_OFFSET (0x88)
++#define BUF_CTR_END_OFFSET (0x8F)
++
++#define CAT_MODE_RX (0x1 << 0)
++#define CAT_MODE_TX (0x1 << 1)
++#define CAT_MODE_INBOUND_DMA (0x1 << 8)
++#define CAT_MODE_OUTBOUND_DMA (0x1 << 9)
++
++#define CH_SYNC_DEFAULT_QUAD (1)
++#define CH_SYNC_MAX_QUAD (15)
++#define CH_SYNC_CDT_BUF_DEP (CH_SYNC_DEFAULT_QUAD * 4 * 4)
++#define CH_SYNC_ADT_BUF_MULTI (4)
++#define CH_SYNC_ADT_BUF_DEP (CH_SYNC_CDT_BUF_DEP * CH_SYNC_ADT_BUF_MULTI)
++#define CH_SYNC_BUF_SZ (CH_SYNC_MAX_QUAD * 4 * 4 * \
++ CH_SYNC_ADT_BUF_MULTI)
++#define CH_CTRL_CDT_BUF_DEP (64)
++#define CH_CTRL_ADT_BUF_DEP (CH_CTRL_CDT_BUF_DEP)
++#define CH_CTRL_BUF_SZ (CH_CTRL_ADT_BUF_DEP)
++#define CH_ASYNC_MDP_PACKET_LEN (1024)
++#define CH_ASYNC_MEP_PACKET_LEN (1536)
++#define CH_ASYNC_CDT_BUF_DEP (CH_ASYNC_MEP_PACKET_LEN)
++#define CH_ASYNC_ADT_BUF_DEP (CH_ASYNC_CDT_BUF_DEP)
++#define CH_ASYNC_BUF_SZ (CH_ASYNC_ADT_BUF_DEP)
++#define CH_ISOC_BLK_SIZE_188 (188)
++#define CH_ISOC_BLK_SIZE_196 (196)
++#define CH_ISOC_BLK_SIZE (CH_ISOC_BLK_SIZE_188)
++#define CH_ISOC_BLK_NUM (1)
++#define CH_ISOC_CDT_BUF_DEP (CH_ISOC_BLK_SIZE * CH_ISOC_BLK_NUM)
++#define CH_ISOC_ADT_BUF_DEP (CH_ISOC_CDT_BUF_DEP)
++#define CH_ISOC_BUF_SZ (1024)
++
++#define CH_SYNC_DBR_BUF_OFFSET (0x0)
++#define CH_CTRL_DBR_BUF_OFFSET (CH_SYNC_DBR_BUF_OFFSET + \
++ 2 * (CH_SYNC_MAX_QUAD * 4 * 4))
++#define CH_ASYNC_DBR_BUF_OFFSET (CH_CTRL_DBR_BUF_OFFSET + \
++ 2 * CH_CTRL_CDT_BUF_DEP)
++#define CH_ISOC_DBR_BUF_OFFSET (CH_ASYNC_DBR_BUF_OFFSET + \
++ 2 * CH_ASYNC_CDT_BUF_DEP)
++
++#define DBR_BUF_START 0x00000
++
++#define CDT_LEN (16)
++#define ADT_LEN (16)
++#define CAT_LEN (2)
++
++#define CDT_SZ (CDT_LEN * LOGIC_CH_NUM)
++#define ADT_SZ (ADT_LEN * LOGIC_CH_NUM)
++#define CAT_SZ (CAT_LEN * LOGIC_CH_NUM * 2)
++
++#define CDT_BASE(base) (base + BUF_CDT_OFFSET)
++#define ADT_BASE(base) (base + BUF_ADT_OFFSET)
++#define CAT_MLB_BASE(base) (base + BUF_CAT_MLB_OFFSET)
++#define CAT_HBI_BASE(base) (base + BUF_CAT_HBI_OFFSET)
++
++#define CDTn_ADDR(base, n) (base + BUF_CDT_OFFSET + n * CDT_LEN)
++#define ADTn_ADDR(base, n) (base + BUF_ADT_OFFSET + n * ADT_LEN)
++#define CATn_MLB_ADDR(base, n) (base + BUF_CAT_MLB_OFFSET + n * CAT_LEN)
++#define CATn_HBI_ADDR(base, n) (base + BUF_CAT_HBI_OFFSET + n * CAT_LEN)
++
++#define CAT_CL_SHIFT (0x0)
++#define CAT_CT_SHIFT (8)
++#define CAT_CE (0x1 << 11)
++#define CAT_RNW (0x1 << 12)
++#define CAT_MT (0x1 << 13)
++#define CAT_FCE (0x1 << 14)
++#define CAT_MFE (0x1 << 14)
++
++#define CDT_WSBC_SHIFT (14)
++#define CDT_WPC_SHIFT (11)
++#define CDT_RSBC_SHIFT (30)
++#define CDT_RPC_SHIFT (27)
++#define CDT_WPC_1_SHIFT (12)
++#define CDT_RPC_1_SHIFT (28)
++#define CDT_WPTR_SHIFT (0)
++#define CDT_SYNC_WSTS_MASK (0x0000f000)
++#define CDT_SYNC_WSTS_SHIFT (12)
++#define CDT_CTRL_ASYNC_WSTS_MASK (0x0000f000)
++#define CDT_CTRL_ASYNC_WSTS_SHIFT (12)
++#define CDT_ISOC_WSTS_MASK (0x0000e000)
++#define CDT_ISOC_WSTS_SHIFT (13)
++#define CDT_RPTR_SHIFT (16)
++#define CDT_SYNC_RSTS_MASK (0xf0000000)
++#define CDT_SYNC_RSTS_SHIFT (28)
++#define CDT_CTRL_ASYNC_RSTS_MASK (0xf0000000)
++#define CDT_CTRL_ASYNC_RSTS_SHIFT (28)
++#define CDT_ISOC_RSTS_MASK (0xe0000000)
++#define CDT_ISOC_RSTS_SHIFT (29)
++#define CDT_CTRL_ASYNC_WSTS_1 (0x1 << 14)
++#define CDT_CTRL_ASYNC_RSTS_1 (0x1 << 15)
++#define CDT_BD_SHIFT (0)
++#define CDT_BA_SHIFT (16)
++#define CDT_BS_SHIFT (0)
++#define CDT_BF_SHIFT (31)
++
++#define ADT_PG (0x1 << 13)
++#define ADT_LE (0x1 << 14)
++#define ADT_CE (0x1 << 15)
++#define ADT_BD1_SHIFT (0)
++#define ADT_ERR1 (0x1 << 13)
++#define ADT_DNE1 (0x1 << 14)
++#define ADT_RDY1 (0x1 << 15)
++#define ADT_BD2_SHIFT (16)
++#define ADT_ERR2 (0x1 << 29)
++#define ADT_DNE2 (0x1 << 30)
++#define ADT_RDY2 (0x1 << 31)
++#define ADT_BA1_SHIFT (0x0)
++#define ADT_BA2_SHIFT (0x0)
++#define ADT_PS1 (0x1 << 12)
++#define ADT_PS2 (0x1 << 28)
++#define ADT_MEP1 (0x1 << 11)
++#define ADT_MEP2 (0x1 << 27)
++
++#define MLB_MINOR_DEVICES 4
++#define MLB_CONTROL_DEV_NAME "ctrl"
++#define MLB_ASYNC_DEV_NAME "async"
++#define MLB_SYNC_DEV_NAME "sync"
++#define MLB_ISOC_DEV_NAME "isoc"
++
++#define TX_CHANNEL 0
++#define RX_CHANNEL 1
++
++#define TRANS_RING_NODES (1 << 3)
++
++enum MLB_CTYPE {
++ MLB_CTYPE_SYNC,
++ MLB_CTYPE_CTRL,
++ MLB_CTYPE_ASYNC,
++ MLB_CTYPE_ISOC,
++};
++
++enum CLK_SPEED {
++ CLK_256FS,
++ CLK_512FS,
++ CLK_1024FS,
++ CLK_2048FS,
++ CLK_3072FS,
++ CLK_4096FS,
++ CLK_6144FS,
++ CLK_8192FS,
++};
++
++struct mlb_ringbuf {
++ s8 *virt_bufs[TRANS_RING_NODES];
++ u32 phy_addrs[TRANS_RING_NODES];
++ s32 head;
++ s32 tail;
++ s32 unit_size;
++ s32 total_size;
++ rwlock_t rb_lock ____cacheline_aligned; /* ring index lock */
++};
++
++struct mlb_channel_info {
++ /* Input MLB channel address */
++ u32 address;
++ /* Internal AHB channel label */
++ u32 cl;
++ /* DBR buf head */
++ u32 dbr_buf_head;
++};
++
++struct mlb_dev_info {
++ /* device node name */
++ const char dev_name[20];
++ /* channel type */
++ const unsigned int channel_type;
++ /* ch fps */
++ enum CLK_SPEED fps;
++ /* channel info for tx/rx */
++ struct mlb_channel_info channels[2];
++ /* ring buffer */
++ u8 *rbuf_base_virt;
++ u32 rbuf_base_phy;
++ struct mlb_ringbuf rx_rbuf;
++ struct mlb_ringbuf tx_rbuf;
++ /* exception event */
++ unsigned long ex_event;
++ /* tx busy indicator */
++ unsigned long tx_busy;
++ /* channel started up or not */
++ atomic_t on;
++ /* device open count */
++ atomic_t opencnt;
++ /* wait queue head for channel */
++ wait_queue_head_t rx_wq;
++ wait_queue_head_t tx_wq;
++ /* TX OK */
++ s32 tx_ok;
++ /* spinlock for event access */
++ spinlock_t event_lock;
++ /*
++ * Block size for isoc mode
++ * This variable can be configured in ioctl
++ */
++ u32 isoc_blksz;
++ /*
++ * Quads number for sync mode
++ * This variable can be confifured in ioctl
++ */
++ u32 sync_quad;
++ /* Buffer depth in cdt */
++ u32 cdt_buf_dep;
++ /* Buffer depth in adt */
++ u32 adt_buf_dep;
++ /* Buffer size to hold data */
++ u32 buf_size;
++};
++
++struct mlb_data {
++ struct mlb_dev_info *devinfo;
++ struct clk *clk_mlb3p;
++ struct clk *clk_mlb6p;
++ struct cdev cdev;
++ struct class *class; /* device class */
++ dev_t firstdev;
++#ifdef CONFIG_REGULATOR
++ struct regulator *nvcc;
++#endif
++ void __iomem *membase; /* mlb module base address */
++ struct gen_pool *iram_pool;
++ u32 iram_size;
++ u32 irq_ahb0;
++ u32 irq_ahb1;
++ u32 irq_mlb;
++};
++
++/*
++ * For optimization, we use fixed channel label for
++ * input channels of each mode
++ * SYNC: CL = 0 for RX, CL = 64 for TX
++ * CTRL: CL = 1 for RX, CL = 65 for TX
++ * ASYNC: CL = 2 for RX, CL = 66 for TX
++ * ISOC: CL = 3 for RX, CL = 67 for TX
++ */
++#define SYNC_RX_CL_AHB0 0
++#define CTRL_RX_CL_AHB0 1
++#define ASYNC_RX_CL_AHB0 2
++#define ISOC_RX_CL_AHB0 3
++#define SYNC_TX_CL_AHB0 4
++#define CTRL_TX_CL_AHB0 5
++#define ASYNC_TX_CL_AHB0 6
++#define ISOC_TX_CL_AHB0 7
++
++#define SYNC_RX_CL_AHB1 32
++#define CTRL_RX_CL_AHB1 33
++#define ASYNC_RX_CL_AHB1 34
++#define ISOC_RX_CL_AHB1 35
++#define SYNC_TX_CL_AHB1 36
++#define CTRL_TX_CL_AHB1 37
++#define ASYNC_TX_CL_AHB1 38
++#define ISOC_TX_CL_AHB1 39
++
++#define SYNC_RX_CL SYNC_RX_CL_AHB0
++#define CTRL_RX_CL CTRL_RX_CL_AHB0
++#define ASYNC_RX_CL ASYNC_RX_CL_AHB0
++#define ISOC_RX_CL ISOC_RX_CL_AHB0
++
++#define SYNC_TX_CL SYNC_TX_CL_AHB0
++#define CTRL_TX_CL CTRL_TX_CL_AHB0
++#define ASYNC_TX_CL ASYNC_TX_CL_AHB0
++#define ISOC_TX_CL ISOC_TX_CL_AHB0
++
++static struct mlb_dev_info mlb_devinfo[MLB_MINOR_DEVICES] = {
++ {
++ .dev_name = MLB_SYNC_DEV_NAME,
++ .channel_type = MLB_CTYPE_SYNC,
++ .channels = {
++ [0] = {
++ .cl = SYNC_TX_CL,
++ .dbr_buf_head = CH_SYNC_DBR_BUF_OFFSET,
++ },
++ [1] = {
++ .cl = SYNC_RX_CL,
++ .dbr_buf_head = CH_SYNC_DBR_BUF_OFFSET
++ + CH_SYNC_BUF_SZ,
++ },
++ },
++ .rx_rbuf = {
++ .unit_size = CH_SYNC_BUF_SZ,
++ .rb_lock =
++ __RW_LOCK_UNLOCKED(mlb_devinfo[0].rx_rbuf.rb_lock),
++ },
++ .tx_rbuf = {
++ .unit_size = CH_SYNC_BUF_SZ,
++ .rb_lock =
++ __RW_LOCK_UNLOCKED(mlb_devinfo[0].tx_rbuf.rb_lock),
++ },
++ .cdt_buf_dep = CH_SYNC_CDT_BUF_DEP,
++ .adt_buf_dep = CH_SYNC_ADT_BUF_DEP,
++ .buf_size = CH_SYNC_BUF_SZ,
++ .on = ATOMIC_INIT(0),
++ .opencnt = ATOMIC_INIT(0),
++ .event_lock = __SPIN_LOCK_UNLOCKED(mlb_devinfo[0].event_lock),
++ },
++ {
++ .dev_name = MLB_CONTROL_DEV_NAME,
++ .channel_type = MLB_CTYPE_CTRL,
++ .channels = {
++ [0] = {
++ .cl = CTRL_TX_CL,
++ .dbr_buf_head = CH_CTRL_DBR_BUF_OFFSET,
++ },
++ [1] = {
++ .cl = CTRL_RX_CL,
++ .dbr_buf_head = CH_CTRL_DBR_BUF_OFFSET
++ + CH_CTRL_BUF_SZ,
++ },
++ },
++ .rx_rbuf = {
++ .unit_size = CH_CTRL_BUF_SZ,
++ .rb_lock =
++ __RW_LOCK_UNLOCKED(mlb_devinfo[1].rx_rbuf.rb_lock),
++ },
++ .tx_rbuf = {
++ .unit_size = CH_CTRL_BUF_SZ,
++ .rb_lock =
++ __RW_LOCK_UNLOCKED(mlb_devinfo[1].tx_rbuf.rb_lock),
++ },
++ .cdt_buf_dep = CH_CTRL_CDT_BUF_DEP,
++ .adt_buf_dep = CH_CTRL_ADT_BUF_DEP,
++ .buf_size = CH_CTRL_BUF_SZ,
++ .on = ATOMIC_INIT(0),
++ .opencnt = ATOMIC_INIT(0),
++ .event_lock = __SPIN_LOCK_UNLOCKED(mlb_devinfo[1].event_lock),
++ },
++ {
++ .dev_name = MLB_ASYNC_DEV_NAME,
++ .channel_type = MLB_CTYPE_ASYNC,
++ .channels = {
++ [0] = {
++ .cl = ASYNC_TX_CL,
++ .dbr_buf_head = CH_ASYNC_DBR_BUF_OFFSET,
++ },
++ [1] = {
++ .cl = ASYNC_RX_CL,
++ .dbr_buf_head = CH_ASYNC_DBR_BUF_OFFSET
++ + CH_ASYNC_BUF_SZ,
++ },
++ },
++ .rx_rbuf = {
++ .unit_size = CH_ASYNC_BUF_SZ,
++ .rb_lock =
++ __RW_LOCK_UNLOCKED(mlb_devinfo[2].rx_rbuf.rb_lock),
++ },
++ .tx_rbuf = {
++ .unit_size = CH_ASYNC_BUF_SZ,
++ .rb_lock =
++ __RW_LOCK_UNLOCKED(mlb_devinfo[2].tx_rbuf.rb_lock),
++ },
++ .cdt_buf_dep = CH_ASYNC_CDT_BUF_DEP,
++ .adt_buf_dep = CH_ASYNC_ADT_BUF_DEP,
++ .buf_size = CH_ASYNC_BUF_SZ,
++ .on = ATOMIC_INIT(0),
++ .opencnt = ATOMIC_INIT(0),
++ .event_lock = __SPIN_LOCK_UNLOCKED(mlb_devinfo[2].event_lock),
++ },
++ {
++ .dev_name = MLB_ISOC_DEV_NAME,
++ .channel_type = MLB_CTYPE_ISOC,
++ .channels = {
++ [0] = {
++ .cl = ISOC_TX_CL,
++ .dbr_buf_head = CH_ISOC_DBR_BUF_OFFSET,
++ },
++ [1] = {
++ .cl = ISOC_RX_CL,
++ .dbr_buf_head = CH_ISOC_DBR_BUF_OFFSET
++ + CH_ISOC_BUF_SZ,
++ },
++ },
++ .rx_rbuf = {
++ .unit_size = CH_ISOC_BUF_SZ,
++ .rb_lock =
++ __RW_LOCK_UNLOCKED(mlb_devinfo[3].rx_rbuf.rb_lock),
++ },
++ .tx_rbuf = {
++ .unit_size = CH_ISOC_BUF_SZ,
++ .rb_lock =
++ __RW_LOCK_UNLOCKED(mlb_devinfo[3].tx_rbuf.rb_lock),
++ },
++ .cdt_buf_dep = CH_ISOC_CDT_BUF_DEP,
++ .adt_buf_dep = CH_ISOC_ADT_BUF_DEP,
++ .buf_size = CH_ISOC_BUF_SZ,
++ .on = ATOMIC_INIT(0),
++ .opencnt = ATOMIC_INIT(0),
++ .event_lock = __SPIN_LOCK_UNLOCKED(mlb_devinfo[3].event_lock),
++ .isoc_blksz = CH_ISOC_BLK_SIZE_188,
++ },
++};
++
++static void __iomem *mlb_base;
++
++DEFINE_SPINLOCK(ctr_lock);
++
++#ifdef DEBUG
++#define DUMP_REG(reg) pr_debug(#reg": 0x%08x\n", __raw_readl(mlb_base + reg))
++
++static void mlb150_dev_dump_reg(void)
++{
++ pr_debug("mxc_mlb150: Dump registers:\n");
++ DUMP_REG(REG_MLBC0);
++ DUMP_REG(REG_MLBPC0);
++ DUMP_REG(REG_MS0);
++ DUMP_REG(REG_MS1);
++ DUMP_REG(REG_MSS);
++ DUMP_REG(REG_MSD);
++ DUMP_REG(REG_MIEN);
++ DUMP_REG(REG_MLBPC2);
++ DUMP_REG(REG_MLBPC1);
++ DUMP_REG(REG_MLBC1);
++ DUMP_REG(REG_HCTL);
++ DUMP_REG(REG_HCMR0);
++ DUMP_REG(REG_HCMR1);
++ DUMP_REG(REG_HCER0);
++ DUMP_REG(REG_HCER1);
++ DUMP_REG(REG_HCBR0);
++ DUMP_REG(REG_HCBR1);
++ DUMP_REG(REG_MDAT0);
++ DUMP_REG(REG_MDAT1);
++ DUMP_REG(REG_MDAT2);
++ DUMP_REG(REG_MDAT3);
++ DUMP_REG(REG_MDWE0);
++ DUMP_REG(REG_MDWE1);
++ DUMP_REG(REG_MDWE2);
++ DUMP_REG(REG_MDWE3);
++ DUMP_REG(REG_MCTL);
++ DUMP_REG(REG_MADR);
++ DUMP_REG(REG_ACTL);
++ DUMP_REG(REG_ACSR0);
++ DUMP_REG(REG_ACSR1);
++ DUMP_REG(REG_ACMR0);
++ DUMP_REG(REG_ACMR1);
++}
++
++static void mlb150_dev_dump_hex(const u8 *buf, u32 len)
++{
++ print_hex_dump(KERN_DEBUG, "CTR DUMP:",
++ DUMP_PREFIX_OFFSET, 8, 1, buf, len, 0);
++}
++#endif
++
++static inline void mlb150_dev_enable_ctr_write(u32 mdat0_bits_en,
++ u32 mdat1_bits_en, u32 mdat2_bits_en, u32 mdat3_bits_en)
++{
++ __raw_writel(mdat0_bits_en, mlb_base + REG_MDWE0);
++ __raw_writel(mdat1_bits_en, mlb_base + REG_MDWE1);
++ __raw_writel(mdat2_bits_en, mlb_base + REG_MDWE2);
++ __raw_writel(mdat3_bits_en, mlb_base + REG_MDWE3);
++}
++
++#ifdef DEBUG
++static inline u8 mlb150_dev_dbr_read(u32 dbr_addr)
++{
++ s32 timeout = 1000;
++ u8 dbr_val = 0;
++ unsigned long flags;
++
++ spin_lock_irqsave(&ctr_lock, flags);
++ __raw_writel(MADR_TB | dbr_addr,
++ mlb_base + REG_MADR);
++
++ while ((!(__raw_readl(mlb_base + REG_MCTL)
++ & MCTL_XCMP)) &&
++ timeout--)
++ ;
++
++ if (0 == timeout) {
++ spin_unlock_irqrestore(&ctr_lock, flags);
++ return -ETIME;
++ }
++
++ dbr_val = __raw_readl(mlb_base + REG_MDAT0) & 0x000000ff;
++
++ __raw_writel(0, mlb_base + REG_MCTL);
++ spin_unlock_irqrestore(&ctr_lock, flags);
++
++ return dbr_val;
++}
++
++static inline s32 mlb150_dev_dbr_write(u32 dbr_addr, u8 dbr_val)
++{
++ s32 timeout = 1000;
++ u32 mdat0 = dbr_val & 0x000000ff;
++ unsigned long flags;
++
++ spin_lock_irqsave(&ctr_lock, flags);
++ __raw_writel(mdat0, mlb_base + REG_MDAT0);
++
++ __raw_writel(MADR_WNR | MADR_TB | dbr_addr,
++ mlb_base + REG_MADR);
++
++ while ((!(__raw_readl(mlb_base + REG_MCTL)
++ & MCTL_XCMP)) &&
++ timeout--)
++ ;
++
++ if (timeout <= 0) {
++ spin_unlock_irqrestore(&ctr_lock, flags);
++ return -ETIME;
++ }
++
++ __raw_writel(0, mlb_base + REG_MCTL);
++ spin_unlock_irqrestore(&ctr_lock, flags);
++
++ return 0;
++}
++
++static inline s32 mlb150_dev_dbr_dump(u32 addr, u32 size)
++{
++ u8 *dump_buf = NULL;
++ u8 *buf_ptr = NULL;
++ s32 i;
++
++ dump_buf = kzalloc(size, GFP_KERNEL);
++ if (!dump_buf) {
++ pr_err("can't allocate enough memory\n");
++ return -ENOMEM;
++ }
++
++ for (i = 0, buf_ptr = dump_buf;
++ i < size; ++i, ++buf_ptr)
++ *buf_ptr = mlb150_dev_dbr_read(addr + i);
++
++ mlb150_dev_dump_hex(dump_buf, size);
++
++ kfree(dump_buf);
++
++ return 0;
++}
++#endif
++
++static s32 mlb150_dev_ctr_read(u32 ctr_offset, u32 *ctr_val)
++{
++ s32 timeout = 1000;
++ unsigned long flags;
++
++ spin_lock_irqsave(&ctr_lock, flags);
++ __raw_writel(ctr_offset, mlb_base + REG_MADR);
++
++ while ((!(__raw_readl(mlb_base + REG_MCTL)
++ & MCTL_XCMP)) &&
++ timeout--)
++ ;
++
++ if (timeout <= 0) {
++ spin_unlock_irqrestore(&ctr_lock, flags);
++ pr_debug("mxc_mlb150: Read CTR timeout\n");
++ return -ETIME;
++ }
++
++ ctr_val[0] = __raw_readl(mlb_base + REG_MDAT0);
++ ctr_val[1] = __raw_readl(mlb_base + REG_MDAT1);
++ ctr_val[2] = __raw_readl(mlb_base + REG_MDAT2);
++ ctr_val[3] = __raw_readl(mlb_base + REG_MDAT3);
++
++ __raw_writel(0, mlb_base + REG_MCTL);
++
++ spin_unlock_irqrestore(&ctr_lock, flags);
++
++ return 0;
++}
++
++static s32 mlb150_dev_ctr_write(u32 ctr_offset, const u32 *ctr_val)
++{
++ s32 timeout = 1000;
++ unsigned long flags;
++
++ spin_lock_irqsave(&ctr_lock, flags);
++
++ __raw_writel(ctr_val[0], mlb_base + REG_MDAT0);
++ __raw_writel(ctr_val[1], mlb_base + REG_MDAT1);
++ __raw_writel(ctr_val[2], mlb_base + REG_MDAT2);
++ __raw_writel(ctr_val[3], mlb_base + REG_MDAT3);
++
++ __raw_writel(MADR_WNR | ctr_offset,
++ mlb_base + REG_MADR);
++
++ while ((!(__raw_readl(mlb_base + REG_MCTL)
++ & MCTL_XCMP)) &&
++ timeout--)
++ ;
++
++ if (timeout <= 0) {
++ spin_unlock_irqrestore(&ctr_lock, flags);
++ pr_debug("mxc_mlb150: Write CTR timeout\n");
++ return -ETIME;
++ }
++
++ __raw_writel(0, mlb_base + REG_MCTL);
++
++ spin_unlock_irqrestore(&ctr_lock, flags);
++
++#ifdef DEBUG_CTR
++ {
++ u32 ctr_rd[4] = { 0 };
++
++ if (!mlb150_dev_ctr_read(ctr_offset, ctr_rd)) {
++ if (ctr_val[0] == ctr_rd[0] &&
++ ctr_val[1] == ctr_rd[1] &&
++ ctr_val[2] == ctr_rd[2] &&
++ ctr_val[3] == ctr_rd[3])
++ return 0;
++ else {
++ pr_debug("mxc_mlb150: ctr write failed\n");
++ pr_debug("offset: 0x%x\n", ctr_offset);
++ pr_debug("Write: 0x%x 0x%x 0x%x 0x%x\n",
++ ctr_val[3], ctr_val[2],
++ ctr_val[1], ctr_val[0]);
++ pr_debug("Read: 0x%x 0x%x 0x%x 0x%x\n",
++ ctr_rd[3], ctr_rd[2],
++ ctr_rd[1], ctr_rd[0]);
++ return -EBADE;
++ }
++ } else {
++ pr_debug("mxc_mlb150: ctr read failed\n");
++ return -EBADE;
++ }
++ }
++#endif
++
++ return 0;
++}
++
++#ifdef DEBUG
++static s32 mlb150_dev_cat_read(u32 ctr_offset, u32 ch, u16 *cat_val)
++{
++ u16 ctr_val[8] = { 0 };
++
++ if (mlb150_dev_ctr_read(ctr_offset, (u32 *)ctr_val))
++ return -ETIME;
++
++ /*
++ * Use u16 array to get u32 array value,
++ * need to convert
++ */
++ cat_val = ctr_val[ch % 8];
++
++ return 0;
++}
++#endif
++
++static s32 mlb150_dev_cat_write(u32 ctr_offset, u32 ch, const u16 cat_val)
++{
++ u16 ctr_val[8] = { 0 };
++
++ if (mlb150_dev_ctr_read(ctr_offset, (u32 *)ctr_val))
++ return -ETIME;
++
++ ctr_val[ch % 8] = cat_val;
++ if (mlb150_dev_ctr_write(ctr_offset, (u32 *)ctr_val))
++ return -ETIME;
++
++ return 0;
++}
++
++#define mlb150_dev_cat_mlb_read(ch, cat_val) \
++ mlb150_dev_cat_read(BUF_CAT_MLB_OFFSET + (ch >> 3), ch, cat_val)
++#define mlb150_dev_cat_mlb_write(ch, cat_val) \
++ mlb150_dev_cat_write(BUF_CAT_MLB_OFFSET + (ch >> 3), ch, cat_val)
++#define mlb150_dev_cat_hbi_read(ch, cat_val) \
++ mlb150_dev_cat_read(BUF_CAT_HBI_OFFSET + (ch >> 3), ch, cat_val)
++#define mlb150_dev_cat_hbi_write(ch, cat_val) \
++ mlb150_dev_cat_write(BUF_CAT_HBI_OFFSET + (ch >> 3), ch, cat_val)
++
++#define mlb150_dev_cdt_read(ch, cdt_val) \
++ mlb150_dev_ctr_read(BUF_CDT_OFFSET + ch, cdt_val)
++#define mlb150_dev_cdt_write(ch, cdt_val) \
++ mlb150_dev_ctr_write(BUF_CDT_OFFSET + ch, cdt_val)
++#define mlb150_dev_adt_read(ch, adt_val) \
++ mlb150_dev_ctr_read(BUF_ADT_OFFSET + ch, adt_val)
++#define mlb150_dev_adt_write(ch, adt_val) \
++ mlb150_dev_ctr_write(BUF_ADT_OFFSET + ch, adt_val)
++
++static s32 mlb150_dev_get_adt_sts(u32 ch)
++{
++ s32 timeout = 1000;
++ unsigned long flags;
++ u32 reg;
++
++ spin_lock_irqsave(&ctr_lock, flags);
++ __raw_writel(BUF_ADT_OFFSET + ch,
++ mlb_base + REG_MADR);
++
++ while ((!(__raw_readl(mlb_base + REG_MCTL)
++ & MCTL_XCMP)) &&
++ timeout--)
++ ;
++
++ if (timeout <= 0) {
++ spin_unlock_irqrestore(&ctr_lock, flags);
++ pr_debug("mxc_mlb150: Read CTR timeout\n");
++ return -ETIME;
++ }
++
++ reg = __raw_readl(mlb_base + REG_MDAT1);
++
++ __raw_writel(0, mlb_base + REG_MCTL);
++ spin_unlock_irqrestore(&ctr_lock, flags);
++
++#ifdef DEBUG_ADT
++ pr_debug("mxc_mlb150: Get ch %d adt sts: 0x%08x\n", ch, reg);
++#endif
++
++ return reg;
++}
++
++#ifdef DEBUG
++static void mlb150_dev_dump_ctr_tbl(u32 ch_start, u32 ch_end)
++{
++ u32 i = 0;
++ u32 ctr_val[4] = { 0 };
++
++ pr_debug("mxc_mlb150: CDT Table");
++ for (i = BUF_CDT_OFFSET + ch_start;
++ i < BUF_CDT_OFFSET + ch_end;
++ ++i) {
++ mlb150_dev_ctr_read(i, ctr_val);
++ pr_debug("CTR 0x%02x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
++ i, ctr_val[3], ctr_val[2], ctr_val[1], ctr_val[0]);
++ }
++
++ pr_debug("mxc_mlb150: ADT Table");
++ for (i = BUF_ADT_OFFSET + ch_start;
++ i < BUF_ADT_OFFSET + ch_end;
++ ++i) {
++ mlb150_dev_ctr_read(i, ctr_val);
++ pr_debug("CTR 0x%02x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
++ i, ctr_val[3], ctr_val[2], ctr_val[1], ctr_val[0]);
++ }
++
++ pr_debug("mxc_mlb150: CAT MLB Table");
++ for (i = BUF_CAT_MLB_OFFSET + (ch_start >> 3);
++ i <= BUF_CAT_MLB_OFFSET + ((ch_end + 8) >> 3);
++ ++i) {
++ mlb150_dev_ctr_read(i, ctr_val);
++ pr_debug("CTR 0x%02x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
++ i, ctr_val[3], ctr_val[2], ctr_val[1], ctr_val[0]);
++ }
++
++ pr_debug("mxc_mlb150: CAT HBI Table");
++ for (i = BUF_CAT_HBI_OFFSET + (ch_start >> 3);
++ i <= BUF_CAT_HBI_OFFSET + ((ch_end + 8) >> 3);
++ ++i) {
++ mlb150_dev_ctr_read(i, ctr_val);
++ pr_debug("CTR 0x%02x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
++ i, ctr_val[3], ctr_val[2], ctr_val[1], ctr_val[0]);
++ }
++}
++#endif
++
++/*
++ * Initial the MLB module device
++ */
++static inline void mlb150_dev_enable_dma_irq(u32 enable)
++{
++ u32 ch_rx_mask = (1 << SYNC_RX_CL_AHB0) | (1 << CTRL_RX_CL_AHB0)
++ | (1 << ASYNC_RX_CL_AHB0) | (1 << ISOC_RX_CL_AHB0)
++ | (1 << SYNC_TX_CL_AHB0) | (1 << CTRL_TX_CL_AHB0)
++ | (1 << ASYNC_TX_CL_AHB0) | (1 << ISOC_TX_CL_AHB0);
++ u32 ch_tx_mask = (1 << (SYNC_RX_CL_AHB1 - INT_AHB1_CH_START)) |
++ (1 << (CTRL_RX_CL_AHB1 - INT_AHB1_CH_START)) |
++ (1 << (ASYNC_RX_CL_AHB1 - INT_AHB1_CH_START)) |
++ (1 << (ISOC_RX_CL_AHB1 - INT_AHB1_CH_START)) |
++ (1 << (SYNC_TX_CL_AHB1 - INT_AHB1_CH_START)) |
++ (1 << (CTRL_TX_CL_AHB1 - INT_AHB1_CH_START)) |
++ (1 << (ASYNC_TX_CL_AHB1 - INT_AHB1_CH_START)) |
++ (1 << (ISOC_TX_CL_AHB1 - INT_AHB1_CH_START));
++
++ if (enable) {
++ __raw_writel(ch_rx_mask, mlb_base + REG_ACMR0);
++ __raw_writel(ch_tx_mask, mlb_base + REG_ACMR1);
++ } else {
++ __raw_writel(0x0, mlb_base + REG_ACMR0);
++ __raw_writel(0x0, mlb_base + REG_ACMR1);
++ }
++}
++
++
++static void mlb150_dev_init_ir_amba_ahb(void)
++{
++ u32 reg = 0;
++
++ /*
++ * Step 1. Program the ACMRn registers to enable interrupts from all
++ * active DMA channels
++ */
++ mlb150_dev_enable_dma_irq(1);
++
++ /*
++ * Step 2. Select the status clear method:
++ * ACTL.SCE = 0, hardware clears on read
++ * ACTL.SCE = 1, software writes a '1' to clear
++ * We only support DMA MODE 1
++ */
++ reg = __raw_readl(mlb_base + REG_ACTL);
++ reg |= ACTL_DMAMODE;
++#ifdef MULTIPLE_PACKAGE_MODE
++ reg |= REG_ACTL_MPB;
++#endif
++
++ /*
++ * Step 3. Select 1 or 2 interrupt signals:
++ * ACTL.SMX = 0: one interrupt for channels 0 - 31 on ahb_init[0]
++ * and another interrupt for channels 32 - 63 on ahb_init[1]
++ * ACTL.SMX = 1: singel interrupt all channels on ahb_init[0]
++ */
++ reg &= ~ACTL_SMX;
++
++ __raw_writel(reg, mlb_base + REG_ACTL);
++}
++
++static inline void mlb150_dev_enable_ir_mlb(u32 enable)
++{
++ /*
++ * Step 1, Select the MSn to be cleared by software,
++ * writing a '0' to the appropriate bits
++ */
++ __raw_writel(0, mlb_base + REG_MS0);
++ __raw_writel(0, mlb_base + REG_MS1);
++
++ /*
++ * Step 1, Program MIEN to enable protocol error
++ * interrupts for all active MLB channels
++ */
++ if (enable)
++ __raw_writel(MIEN_CTX_PE |
++ MIEN_CRX_PE | MIEN_ATX_PE |
++ MIEN_ARX_PE | MIEN_SYNC_PE |
++ MIEN_ISOC_PE,
++ mlb_base + REG_MIEN);
++ else
++ __raw_writel(0, mlb_base + REG_MIEN);
++}
++
++static inline void mlb150_enable_pll(struct mlb_data *drvdata)
++{
++ u32 c0_val;
++
++ __raw_writel(MLBPC1_VAL,
++ drvdata->membase + REG_MLBPC1);
++
++ c0_val = __raw_readl(drvdata->membase + REG_MLBC0);
++ if (c0_val & MLBC0_MLBPEN) {
++ c0_val &= ~MLBC0_MLBPEN;
++ __raw_writel(c0_val,
++ drvdata->membase + REG_MLBC0);
++ }
++
++ clk_prepare_enable(drvdata->clk_mlb6p);
++
++ c0_val |= (MLBC0_MLBPEN);
++ __raw_writel(c0_val, drvdata->membase + REG_MLBC0);
++}
++
++static inline void mlb150_disable_pll(struct mlb_data *drvdata)
++{
++ u32 c0_val;
++
++ clk_disable_unprepare(drvdata->clk_mlb6p);
++
++ c0_val = __raw_readl(drvdata->membase + REG_MLBC0);
++
++ __raw_writel(0x0, drvdata->membase + REG_MLBPC1);
++
++ c0_val &= ~MLBC0_MLBPEN;
++ __raw_writel(c0_val, drvdata->membase + REG_MLBC0);
++}
++
++static void mlb150_dev_reset_cdt(void)
++{
++ int i = 0;
++ u32 ctr_val[4] = { 0 };
++
++ mlb150_dev_enable_ctr_write(0xffffffff, 0xffffffff,
++ 0xffffffff, 0xffffffff);
++
++ for (i = 0; i < (LOGIC_CH_NUM); ++i)
++ mlb150_dev_ctr_write(BUF_CDT_OFFSET + i, ctr_val);
++}
++
++static s32 mlb150_dev_init_ch_cdt(struct mlb_dev_info *pdevinfo, u32 ch,
++ enum MLB_CTYPE ctype, u32 ch_func)
++{
++ u32 cdt_val[4] = { 0 };
++
++ /* a. Set the 14-bit base address (BA) */
++ pr_debug("mxc_mlb150: ctype: %d, ch: %d, dbr_buf_head: 0x%08x",
++ ctype, ch, pdevinfo->channels[ch_func].dbr_buf_head);
++ cdt_val[3] = (pdevinfo->channels[ch_func].dbr_buf_head)
++ << CDT_BA_SHIFT;
++ /*
++ * b. Set the 12-bit or 13-bit buffer depth (BD)
++ * BD = buffer depth in bytes - 1
++ * For synchronous channels: (BD + 1) = 4 * m * bpf
++ * For control channels: (BD + 1) >= max packet length (64)
++ * For asynchronous channels: (BD + 1) >= max packet length
++ * 1024 for a MOST Data packet (MDP);
++ * 1536 for a MOST Ethernet Packet (MEP)
++ * For isochronous channels: (BD + 1) mod (BS + 1) = 0
++ * BS
++ */
++ if (MLB_CTYPE_ISOC == ctype)
++ cdt_val[1] |= (pdevinfo->isoc_blksz - 1);
++ /* BD */
++ cdt_val[3] |= (pdevinfo->cdt_buf_dep - 1) << CDT_BD_SHIFT;
++
++ pr_debug("mxc_mlb150: Set CDT val of channel %d, type: %d: "
++ "0x%08x 0x%08x 0x%08x 0x%08x\n",
++ ch, ctype, cdt_val[3], cdt_val[2], cdt_val[1], cdt_val[0]);
++
++ if (mlb150_dev_cdt_write(ch, cdt_val))
++ return -ETIME;
++
++#ifdef DEBUG_CTR
++ {
++ u32 cdt_rd[4] = { 0 };
++ if (!mlb150_dev_cdt_read(ch, cdt_rd)) {
++ pr_debug("mxc_mlb150: CDT val of channel %d: "
++ "0x%08x 0x%08x 0x%08x 0x%08x\n",
++ ch, cdt_rd[3], cdt_rd[2], cdt_rd[1], cdt_rd[0]);
++ if (cdt_rd[3] == cdt_val[3] &&
++ cdt_rd[2] == cdt_val[2] &&
++ cdt_rd[1] == cdt_val[1] &&
++ cdt_rd[0] == cdt_val[0]) {
++ pr_debug("mxc_mlb150: set cdt succeed!\n");
++ return 0;
++ } else {
++ pr_debug("mxc_mlb150: set cdt failed!\n");
++ return -EBADE;
++ }
++ } else {
++ pr_debug("mxc_mlb150: Read CDT val of channel %d failed\n",
++ ch);
++ return -EBADE;
++ }
++ }
++#endif
++
++ return 0;
++}
++
++static s32 mlb150_dev_init_ch_cat(u32 ch, u32 cl,
++ u32 cat_mode, enum MLB_CTYPE ctype)
++{
++ u16 cat_val = 0;
++#ifdef DEBUG_CTR
++ u16 cat_rd = 0;
++#endif
++
++ cat_val = CAT_CE | (ctype << CAT_CT_SHIFT) | cl;
++
++ if (cat_mode & CAT_MODE_OUTBOUND_DMA)
++ cat_val |= CAT_RNW;
++
++ if (MLB_CTYPE_SYNC == ctype)
++ cat_val |= CAT_MT;
++
++ switch (cat_mode) {
++ case CAT_MODE_RX | CAT_MODE_INBOUND_DMA:
++ case CAT_MODE_TX | CAT_MODE_OUTBOUND_DMA:
++ pr_debug("mxc_mlb150: set CAT val of channel %d, type: %d: 0x%04x\n",
++ ch, ctype, cat_val);
++
++ if (mlb150_dev_cat_mlb_write(ch, cat_val))
++ return -ETIME;
++#ifdef DEBUG_CTR
++ if (!mlb150_dev_cat_mlb_read(ch, &cat_rd))
++ pr_debug("mxc_mlb150: CAT val of mlb channel %d: 0x%04x",
++ ch, cat_rd);
++ else {
++ pr_debug("mxc_mlb150: Read CAT of mlb channel %d failed\n",
++ ch);
++ return -EBADE;
++ }
++#endif
++ break;
++ case CAT_MODE_TX | CAT_MODE_INBOUND_DMA:
++ case CAT_MODE_RX | CAT_MODE_OUTBOUND_DMA:
++ pr_debug("mxc_mlb150: set CAT val of channel %d, type: %d: 0x%04x\n",
++ cl, ctype, cat_val);
++
++ if (mlb150_dev_cat_hbi_write(cl, cat_val))
++ return -ETIME;
++#ifdef DEBUG_CTR
++ if (!mlb150_dev_cat_hbi_read(cl, &cat_rd))
++ pr_debug("mxc_mlb150: CAT val of hbi channel %d: 0x%04x",
++ cl, cat_rd);
++ else {
++ pr_debug("mxc_mlb150: Read CAT of hbi channel %d failed\n",
++ cl);
++ return -EBADE;
++ }
++#endif
++ break;
++ default:
++ return EBADRQC;
++ }
++
++#ifdef DEBUG_CTR
++ {
++ if (cat_val == cat_rd) {
++ pr_debug("mxc_mlb150: set cat succeed!\n");
++ return 0;
++ } else {
++ pr_debug("mxc_mlb150: set cat failed!\n");
++ return -EBADE;
++ }
++ }
++#endif
++ return 0;
++}
++
++static void mlb150_dev_reset_cat(void)
++{
++ int i = 0;
++ u32 ctr_val[4] = { 0 };
++
++ mlb150_dev_enable_ctr_write(0xffffffff, 0xffffffff,
++ 0xffffffff, 0xffffffff);
++
++ for (i = 0; i < (LOGIC_CH_NUM >> 3); ++i) {
++ mlb150_dev_ctr_write(BUF_CAT_MLB_OFFSET + i, ctr_val);
++ mlb150_dev_ctr_write(BUF_CAT_HBI_OFFSET + i, ctr_val);
++ }
++}
++
++static void mlb150_dev_init_rfb(struct mlb_dev_info *pdevinfo, u32 rx_ch,
++ u32 tx_ch, enum MLB_CTYPE ctype)
++{
++ u32 rx_cl = pdevinfo->channels[RX_CHANNEL].cl;
++ u32 tx_cl = pdevinfo->channels[TX_CHANNEL].cl;
++ /* Step 1, Initialize all bits of CAT to '0' */
++ mlb150_dev_reset_cat();
++ mlb150_dev_reset_cdt();
++ /*
++ * Step 2, Initialize logical channel
++ * Step 3, Program the CDT for channel N
++ */
++ mlb150_dev_init_ch_cdt(pdevinfo, rx_cl, ctype, RX_CHANNEL);
++ mlb150_dev_init_ch_cdt(pdevinfo, tx_cl, ctype, TX_CHANNEL);
++
++ /* Step 4&5, Program the CAT for the inbound and outbound DMA */
++ mlb150_dev_init_ch_cat(rx_ch, rx_cl,
++ CAT_MODE_RX | CAT_MODE_INBOUND_DMA,
++ ctype);
++ mlb150_dev_init_ch_cat(rx_ch, rx_cl,
++ CAT_MODE_RX | CAT_MODE_OUTBOUND_DMA,
++ ctype);
++ mlb150_dev_init_ch_cat(tx_ch, tx_cl,
++ CAT_MODE_TX | CAT_MODE_INBOUND_DMA,
++ ctype);
++ mlb150_dev_init_ch_cat(tx_ch, tx_cl,
++ CAT_MODE_TX | CAT_MODE_OUTBOUND_DMA,
++ ctype);
++}
++
++static void mlb150_dev_reset_adt(void)
++{
++ int i = 0;
++ u32 ctr_val[4] = { 0 };
++
++ mlb150_dev_enable_ctr_write(0xffffffff, 0xffffffff,
++ 0xffffffff, 0xffffffff);
++
++ for (i = 0; i < (LOGIC_CH_NUM); ++i)
++ mlb150_dev_ctr_write(BUF_ADT_OFFSET + i, ctr_val);
++}
++
++static void mlb150_dev_reset_whole_ctr(void)
++{
++ mlb150_dev_enable_ctr_write(0xffffffff, 0xffffffff,
++ 0xffffffff, 0xffffffff);
++ mlb150_dev_reset_cdt();
++ mlb150_dev_reset_adt();
++ mlb150_dev_reset_cat();
++}
++
++#define CLR_REG(reg) __raw_writel(0x0, mlb_base + reg)
++
++static void mlb150_dev_reset_all_regs(void)
++{
++ CLR_REG(REG_MLBC0);
++ CLR_REG(REG_MLBPC0);
++ CLR_REG(REG_MS0);
++ CLR_REG(REG_MS1);
++ CLR_REG(REG_MSS);
++ CLR_REG(REG_MSD);
++ CLR_REG(REG_MIEN);
++ CLR_REG(REG_MLBPC2);
++ CLR_REG(REG_MLBPC1);
++ CLR_REG(REG_MLBC1);
++ CLR_REG(REG_HCTL);
++ CLR_REG(REG_HCMR0);
++ CLR_REG(REG_HCMR1);
++ CLR_REG(REG_HCER0);
++ CLR_REG(REG_HCER1);
++ CLR_REG(REG_HCBR0);
++ CLR_REG(REG_HCBR1);
++ CLR_REG(REG_MDAT0);
++ CLR_REG(REG_MDAT1);
++ CLR_REG(REG_MDAT2);
++ CLR_REG(REG_MDAT3);
++ CLR_REG(REG_MDWE0);
++ CLR_REG(REG_MDWE1);
++ CLR_REG(REG_MDWE2);
++ CLR_REG(REG_MDWE3);
++ CLR_REG(REG_MCTL);
++ CLR_REG(REG_MADR);
++ CLR_REG(REG_ACTL);
++ CLR_REG(REG_ACSR0);
++ CLR_REG(REG_ACSR1);
++ CLR_REG(REG_ACMR0);
++ CLR_REG(REG_ACMR1);
++}
++
++static inline s32 mlb150_dev_pipo_start(struct mlb_ringbuf *rbuf,
++ u32 ahb_ch, u32 buf_addr)
++{
++ u32 ctr_val[4] = { 0 };
++
++ ctr_val[1] |= ADT_RDY1;
++ ctr_val[2] = buf_addr;
++
++ if (mlb150_dev_adt_write(ahb_ch, ctr_val))
++ return -ETIME;
++
++ return 0;
++}
++
++static inline s32 mlb150_dev_pipo_next(u32 ahb_ch, enum MLB_CTYPE ctype,
++ u32 dne_sts, u32 buf_addr)
++{
++ u32 ctr_val[4] = { 0 };
++
++ if (MLB_CTYPE_ASYNC == ctype ||
++ MLB_CTYPE_CTRL == ctype) {
++ ctr_val[1] |= ADT_PS1;
++ ctr_val[1] |= ADT_PS2;
++ }
++
++ /*
++ * Clear DNE1 and ERR1
++ * Set the page ready bit (RDY1)
++ */
++ if (dne_sts & ADT_DNE1) {
++ ctr_val[1] |= ADT_RDY2;
++ ctr_val[3] = buf_addr;
++ } else {
++ ctr_val[1] |= ADT_RDY1;
++ ctr_val[2] = buf_addr;
++ }
++
++ if (mlb150_dev_adt_write(ahb_ch, ctr_val))
++ return -ETIME;
++
++ return 0;
++}
++
++static inline s32 mlb150_dev_pipo_stop(struct mlb_ringbuf *rbuf, u32 ahb_ch)
++{
++ u32 ctr_val[4] = { 0 };
++ unsigned long flags;
++
++ write_lock_irqsave(&rbuf->rb_lock, flags);
++ rbuf->head = rbuf->tail = 0;
++ write_unlock_irqrestore(&rbuf->rb_lock, flags);
++
++ if (mlb150_dev_adt_write(ahb_ch, ctr_val))
++ return -ETIME;
++
++ return 0;
++}
++
++static s32 mlb150_dev_init_ch_amba_ahb(struct mlb_dev_info *pdevinfo,
++ struct mlb_channel_info *chinfo,
++ enum MLB_CTYPE ctype)
++{
++ u32 ctr_val[4] = { 0 };
++
++ /* a. Set the 32-bit base address (BA1) */
++ ctr_val[3] = 0;
++ ctr_val[2] = 0;
++ ctr_val[1] = (pdevinfo->adt_buf_dep - 1) << ADT_BD1_SHIFT;
++ ctr_val[1] |= (pdevinfo->adt_buf_dep - 1) << ADT_BD2_SHIFT;
++ if (MLB_CTYPE_ASYNC == ctype ||
++ MLB_CTYPE_CTRL == ctype) {
++ ctr_val[1] |= ADT_PS1;
++ ctr_val[1] |= ADT_PS2;
++ }
++
++ ctr_val[0] |= (ADT_LE | ADT_CE);
++
++ pr_debug("mxc_mlb150: Set ADT val of channel %d, ctype: %d: "
++ "0x%08x 0x%08x 0x%08x 0x%08x\n",
++ chinfo->cl, ctype, ctr_val[3], ctr_val[2],
++ ctr_val[1], ctr_val[0]);
++
++ if (mlb150_dev_adt_write(chinfo->cl, ctr_val))
++ return -ETIME;
++
++#ifdef DEBUG_CTR
++ {
++ u32 ctr_rd[4] = { 0 };
++ if (!mlb150_dev_adt_read(chinfo->cl, ctr_rd)) {
++ pr_debug("mxc_mlb150: ADT val of channel %d: "
++ "0x%08x 0x%08x 0x%08x 0x%08x\n",
++ chinfo->cl, ctr_rd[3], ctr_rd[2],
++ ctr_rd[1], ctr_rd[0]);
++ if (ctr_rd[3] == ctr_val[3] &&
++ ctr_rd[2] == ctr_val[2] &&
++ ctr_rd[1] == ctr_val[1] &&
++ ctr_rd[0] == ctr_val[0]) {
++ pr_debug("mxc_mlb150: set adt succeed!\n");
++ return 0;
++ } else {
++ pr_debug("mxc_mlb150: set adt failed!\n");
++ return -EBADE;
++ }
++ } else {
++ pr_debug("mxc_mlb150: Read ADT val of channel %d failed\n",
++ chinfo->cl);
++ return -EBADE;
++ }
++ }
++#endif
++
++ return 0;
++}
++
++static void mlb150_dev_init_amba_ahb(struct mlb_dev_info *pdevinfo,
++ enum MLB_CTYPE ctype)
++{
++ struct mlb_channel_info *tx_chinfo = &pdevinfo->channels[TX_CHANNEL];
++ struct mlb_channel_info *rx_chinfo = &pdevinfo->channels[RX_CHANNEL];
++
++ /* Step 1, Initialize all bits of the ADT to '0' */
++ mlb150_dev_reset_adt();
++
++ /*
++ * Step 2, Select a logic channel
++ * Step 3, Program the AMBA AHB block ping page for channel N
++ * Step 4, Program the AMBA AHB block pong page for channel N
++ */
++ mlb150_dev_init_ch_amba_ahb(pdevinfo, rx_chinfo, ctype);
++ mlb150_dev_init_ch_amba_ahb(pdevinfo, tx_chinfo, ctype);
++}
++
++static void mlb150_dev_exit(void)
++{
++ u32 c0_val, hctl_val;
++
++ /* Disable EN bits */
++ c0_val = __raw_readl(mlb_base + REG_MLBC0);
++ c0_val &= ~(MLBC0_MLBEN | MLBC0_MLBPEN);
++ __raw_writel(c0_val, mlb_base + REG_MLBC0);
++
++ hctl_val = __raw_readl(mlb_base + REG_HCTL);
++ hctl_val &= ~HCTL_EN;
++ __raw_writel(hctl_val, mlb_base + REG_HCTL);
++
++ __raw_writel(0x0, mlb_base + REG_HCMR0);
++ __raw_writel(0x0, mlb_base + REG_HCMR1);
++
++ mlb150_dev_enable_dma_irq(0);
++ mlb150_dev_enable_ir_mlb(0);
++}
++
++static void mlb150_dev_init(void)
++{
++ u32 c0_val;
++ u32 ch_rx_mask = (1 << SYNC_RX_CL_AHB0) | (1 << CTRL_RX_CL_AHB0)
++ | (1 << ASYNC_RX_CL_AHB0) | (1 << ISOC_RX_CL_AHB0)
++ | (1 << SYNC_TX_CL_AHB0) | (1 << CTRL_TX_CL_AHB0)
++ | (1 << ASYNC_TX_CL_AHB0) | (1 << ISOC_TX_CL_AHB0);
++ u32 ch_tx_mask = (1 << (SYNC_RX_CL_AHB1 - INT_AHB1_CH_START)) |
++ (1 << (CTRL_RX_CL_AHB1 - INT_AHB1_CH_START)) |
++ (1 << (ASYNC_RX_CL_AHB1 - INT_AHB1_CH_START)) |
++ (1 << (ISOC_RX_CL_AHB1 - INT_AHB1_CH_START)) |
++ (1 << (SYNC_TX_CL_AHB1 - INT_AHB1_CH_START)) |
++ (1 << (CTRL_TX_CL_AHB1 - INT_AHB1_CH_START)) |
++ (1 << (ASYNC_TX_CL_AHB1 - INT_AHB1_CH_START)) |
++ (1 << (ISOC_TX_CL_AHB1 - INT_AHB1_CH_START));
++
++ /* Disable EN bits */
++ mlb150_dev_exit();
++
++ /*
++ * Step 1. Initialize CTR and registers
++ * a. Set all bit of the CTR (CAT, CDT, and ADT) to 0.
++ */
++ mlb150_dev_reset_whole_ctr();
++
++ /* a. Set all bit of the CTR (CAT, CDT, and ADT) to 0. */
++ mlb150_dev_reset_all_regs();
++
++ /*
++ * Step 2, Configure the MediaLB interface
++ * Select pin mode and clock, 3-pin and 256fs
++ */
++ c0_val = __raw_readl(mlb_base + REG_MLBC0);
++ c0_val &= ~(MLBC0_MLBPEN | MLBC0_MLBCLK_MASK);
++ __raw_writel(c0_val, mlb_base + REG_MLBC0);
++
++ c0_val |= MLBC0_MLBEN;
++ __raw_writel(c0_val, mlb_base + REG_MLBC0);
++
++ /* Step 3, Configure the HBI interface */
++ __raw_writel(ch_rx_mask, mlb_base + REG_HCMR0);
++ __raw_writel(ch_tx_mask, mlb_base + REG_HCMR1);
++ __raw_writel(HCTL_EN, mlb_base + REG_HCTL);
++
++ mlb150_dev_init_ir_amba_ahb();
++
++ mlb150_dev_enable_ir_mlb(1);
++}
++
++static s32 mlb150_dev_unmute_syn_ch(u32 rx_ch, u32 rx_cl, u32 tx_ch, u32 tx_cl)
++{
++ u32 timeout = 10000;
++
++ /*
++ * Check that MediaLB clock is running (MLBC1.CLKM = 0)
++ * If MLBC1.CLKM = 1, clear the register bit, wait one
++ * APB or I/O clock cycle and repeat the check
++ */
++ while ((__raw_readl(mlb_base + REG_MLBC1) & MLBC1_CLKM)
++ && --timeout)
++ __raw_writel(~MLBC1_CLKM, mlb_base + REG_MLBC1);
++
++ if (0 == timeout)
++ return -ETIME;
++
++ timeout = 10000;
++ /* Poll for MLB lock (MLBC0.MLBLK = 1) */
++ while (!(__raw_readl(mlb_base + REG_MLBC0) & MLBC0_MLBLK)
++ && --timeout)
++ ;
++
++ if (0 == timeout)
++ return -ETIME;
++
++ /* Unmute synchronous channel(s) */
++ mlb150_dev_cat_mlb_write(rx_ch, CAT_CE | rx_cl);
++ mlb150_dev_cat_mlb_write(tx_ch,
++ CAT_CE | tx_cl | CAT_RNW);
++ mlb150_dev_cat_hbi_write(rx_cl,
++ CAT_CE | rx_cl | CAT_RNW);
++ mlb150_dev_cat_hbi_write(tx_cl, CAT_CE | tx_cl);
++
++ return 0;
++}
++
++/* In case the user calls channel shutdown, but rx or tx is not completed yet */
++static s32 mlb150_trans_complete_check(struct mlb_dev_info *pdevinfo)
++{
++ struct mlb_ringbuf *rx_rbuf = &pdevinfo->rx_rbuf;
++ struct mlb_ringbuf *tx_rbuf = &pdevinfo->tx_rbuf;
++ s32 timeout = 1024;
++
++ while (timeout--) {
++ read_lock(&tx_rbuf->rb_lock);
++ if (!CIRC_CNT(tx_rbuf->head, tx_rbuf->tail, TRANS_RING_NODES)) {
++ read_unlock(&tx_rbuf->rb_lock);
++ break;
++ } else
++ read_unlock(&tx_rbuf->rb_lock);
++ }
++
++ if (timeout <= 0) {
++ pr_debug("TX complete check timeout!\n");
++ return -ETIME;
++ }
++
++ timeout = 1024;
++ while (timeout--) {
++ read_lock(&rx_rbuf->rb_lock);
++ if (!CIRC_CNT(rx_rbuf->head, rx_rbuf->tail, TRANS_RING_NODES)) {
++ read_unlock(&rx_rbuf->rb_lock);
++ break;
++ } else
++ read_unlock(&rx_rbuf->rb_lock);
++ }
++
++ if (timeout <= 0) {
++ pr_debug("RX complete check timeout!\n");
++ return -ETIME;
++ }
++
++ /*
++ * Interrupt from TX can only inform that the data is sent
++ * to AHB bus, not mean that it is sent to MITB. Thus we add
++ * a delay here for data to be completed sent.
++ */
++ udelay(1000);
++
++ return 0;
++}
++
++/*
++ * Enable/Disable the MLB IRQ
++ */
++static void mxc_mlb150_irq_enable(struct mlb_data *drvdata, u8 enable)
++{
++ if (enable) {
++ enable_irq(drvdata->irq_ahb0);
++ enable_irq(drvdata->irq_ahb1);
++ enable_irq(drvdata->irq_mlb);
++ } else {
++ disable_irq(drvdata->irq_ahb0);
++ disable_irq(drvdata->irq_ahb1);
++ disable_irq(drvdata->irq_mlb);
++ }
++}
++
++/*
++ * Enable the MLB channel
++ */
++static s32 mlb_channel_enable(struct mlb_data *drvdata,
++ int chan_dev_id, int on)
++{
++ struct mlb_dev_info *pdevinfo = drvdata->devinfo;
++ struct mlb_channel_info *tx_chinfo = &pdevinfo->channels[TX_CHANNEL];
++ struct mlb_channel_info *rx_chinfo = &pdevinfo->channels[RX_CHANNEL];
++ u32 tx_ch = tx_chinfo->address;
++ u32 rx_ch = rx_chinfo->address;
++ u32 tx_cl = tx_chinfo->cl;
++ u32 rx_cl = rx_chinfo->cl;
++ s32 ret = 0;
++
++ /*
++ * setup the direction, enable, channel type,
++ * mode select, channel address and mask buf start
++ */
++ if (on) {
++ u32 ctype = pdevinfo->channel_type;
++
++ mlb150_dev_enable_ctr_write(0xffffffff, 0xffffffff,
++ 0xffffffff, 0xffffffff);
++ mlb150_dev_init_rfb(pdevinfo, rx_ch, tx_ch, ctype);
++
++ mlb150_dev_init_amba_ahb(pdevinfo, ctype);
++
++#ifdef DEBUG
++ mlb150_dev_dump_ctr_tbl(0, tx_chinfo->cl + 1);
++#endif
++ /* Synchronize and unmute synchrouous channel */
++ if (MLB_CTYPE_SYNC == ctype) {
++ ret = mlb150_dev_unmute_syn_ch(rx_ch, rx_cl,
++ tx_ch, tx_cl);
++ if (ret)
++ return ret;
++ }
++
++ mlb150_dev_enable_ctr_write(0x0, ADT_RDY1 | ADT_DNE1 |
++ ADT_ERR1 | ADT_PS1 |
++ ADT_RDY2 | ADT_DNE2 | ADT_ERR2 | ADT_PS2,
++ 0xffffffff, 0xffffffff);
++
++ if (pdevinfo->fps >= CLK_2048FS)
++ mlb150_enable_pll(drvdata);
++
++ atomic_set(&pdevinfo->on, 1);
++
++#ifdef DEBUG
++ mlb150_dev_dump_reg();
++ mlb150_dev_dump_ctr_tbl(0, tx_chinfo->cl + 1);
++#endif
++ /* Init RX ADT */
++ mlb150_dev_pipo_start(&pdevinfo->rx_rbuf, rx_cl,
++ pdevinfo->rx_rbuf.phy_addrs[0]);
++ } else {
++ mlb150_dev_pipo_stop(&pdevinfo->rx_rbuf, rx_cl);
++
++ mlb150_dev_enable_dma_irq(0);
++ mlb150_dev_enable_ir_mlb(0);
++
++ mlb150_dev_reset_cat();
++
++ atomic_set(&pdevinfo->on, 0);
++
++ if (pdevinfo->fps >= CLK_2048FS)
++ mlb150_disable_pll(drvdata);
++ }
++
++ return 0;
++}
++
++/*
++ * MLB interrupt handler
++ */
++static void mlb_rx_isr(s32 ctype, u32 ahb_ch, struct mlb_dev_info *pdevinfo)
++{
++ struct mlb_ringbuf *rx_rbuf = &pdevinfo->rx_rbuf;
++ s32 head, tail, adt_sts;
++ u32 rx_buf_ptr;
++
++#ifdef DEBUG_RX
++ pr_debug("mxc_mlb150: mlb_rx_isr\n");
++#endif
++
++ read_lock(&rx_rbuf->rb_lock);
++
++ head = (rx_rbuf->head + 1) & (TRANS_RING_NODES - 1);
++ tail = ACCESS_ONCE(rx_rbuf->tail);
++ read_unlock(&rx_rbuf->rb_lock);
++
++ if (CIRC_SPACE(head, tail, TRANS_RING_NODES) >= 1) {
++ rx_buf_ptr = rx_rbuf->phy_addrs[head];
++
++ /* commit the item before incrementing the head */
++ smp_wmb();
++
++ write_lock(&rx_rbuf->rb_lock);
++ rx_rbuf->head = head;
++ write_unlock(&rx_rbuf->rb_lock);
++
++ /* wake up the reader */
++ wake_up_interruptible(&pdevinfo->rx_wq);
++ } else {
++ rx_buf_ptr = rx_rbuf->phy_addrs[head];
++ pr_debug("drop RX package, due to no space, (%d,%d)\n",
++ head, tail);
++ }
++
++ adt_sts = mlb150_dev_get_adt_sts(ahb_ch);
++ /* Set ADT for RX */
++ mlb150_dev_pipo_next(ahb_ch, ctype, adt_sts, rx_buf_ptr);
++}
++
++static void mlb_tx_isr(s32 ctype, u32 ahb_ch, struct mlb_dev_info *pdevinfo)
++{
++ struct mlb_ringbuf *tx_rbuf = &pdevinfo->tx_rbuf;
++ s32 head, tail, adt_sts;
++ u32 tx_buf_ptr;
++
++ read_lock(&tx_rbuf->rb_lock);
++
++ head = ACCESS_ONCE(tx_rbuf->head);
++ tail = (tx_rbuf->tail + 1) & (TRANS_RING_NODES - 1);
++ read_unlock(&tx_rbuf->rb_lock);
++
++ smp_mb();
++ write_lock(&tx_rbuf->rb_lock);
++ tx_rbuf->tail = tail;
++ write_unlock(&tx_rbuf->rb_lock);
++
++ /* check the current tx buffer is available or not */
++ if (CIRC_CNT(head, tail, TRANS_RING_NODES) >= 1) {
++ /* read index before reading contents at that index */
++ smp_read_barrier_depends();
++
++ tx_buf_ptr = tx_rbuf->phy_addrs[tail];
++
++ wake_up_interruptible(&pdevinfo->tx_wq);
++
++ adt_sts = mlb150_dev_get_adt_sts(ahb_ch);
++ /* Set ADT for TX */
++ mlb150_dev_pipo_next(ahb_ch, ctype, adt_sts, tx_buf_ptr);
++ }
++}
++
++static irqreturn_t mlb_ahb_isr(int irq, void *dev_id)
++{
++ u32 acsr0, hcer0;
++ u32 ch_mask = (1 << SYNC_RX_CL) | (1 << CTRL_RX_CL)
++ | (1 << ASYNC_RX_CL) | (1 << ISOC_RX_CL)
++ | (1 << SYNC_TX_CL) | (1 << CTRL_TX_CL)
++ | (1 << ASYNC_TX_CL) | (1 << ISOC_TX_CL);
++
++ /*
++ * Step 5, Read the ACSRn registers to determine which channel or
++ * channels are causing the interrupt
++ */
++ acsr0 = __raw_readl(mlb_base + REG_ACSR0);
++
++ hcer0 = __raw_readl(mlb_base + REG_HCER0);
++
++ /*
++ * Step 6, If ACTL.SCE = 1, write the result of step 5 back to ACSR0
++ * and ACSR1 to clear the interrupt
++ * We'll not set ACTL_SCE
++ */
++
++ if (ch_mask & hcer0)
++ pr_err("CH encounters an AHB error: 0x%x\n", hcer0);
++
++ if ((1 << SYNC_RX_CL) & acsr0)
++ mlb_rx_isr(MLB_CTYPE_SYNC, SYNC_RX_CL,
++ &mlb_devinfo[MLB_CTYPE_SYNC]);
++
++ if ((1 << CTRL_RX_CL) & acsr0)
++ mlb_rx_isr(MLB_CTYPE_CTRL, CTRL_RX_CL,
++ &mlb_devinfo[MLB_CTYPE_CTRL]);
++
++ if ((1 << ASYNC_RX_CL) & acsr0)
++ mlb_rx_isr(MLB_CTYPE_ASYNC, ASYNC_RX_CL,
++ &mlb_devinfo[MLB_CTYPE_ASYNC]);
++
++ if ((1 << ISOC_RX_CL) & acsr0)
++ mlb_rx_isr(MLB_CTYPE_ISOC, ISOC_RX_CL,
++ &mlb_devinfo[MLB_CTYPE_ISOC]);
++
++ if ((1 << SYNC_TX_CL) & acsr0)
++ mlb_tx_isr(MLB_CTYPE_SYNC, SYNC_TX_CL,
++ &mlb_devinfo[MLB_CTYPE_SYNC]);
++
++ if ((1 << CTRL_TX_CL) & acsr0)
++ mlb_tx_isr(MLB_CTYPE_CTRL, CTRL_TX_CL,
++ &mlb_devinfo[MLB_CTYPE_CTRL]);
++
++ if ((1 << ASYNC_TX_CL) & acsr0)
++ mlb_tx_isr(MLB_CTYPE_ASYNC, ASYNC_TX_CL,
++ &mlb_devinfo[MLB_CTYPE_ASYNC]);
++
++ if ((1 << ISOC_TX_CL) & acsr0)
++ mlb_tx_isr(MLB_CTYPE_ASYNC, ISOC_TX_CL,
++ &mlb_devinfo[MLB_CTYPE_ISOC]);
++
++ return IRQ_HANDLED;
++}
++
++static irqreturn_t mlb_isr(int irq, void *dev_id)
++{
++ u32 rx_int_sts, tx_int_sts, ms0,
++ ms1, tx_cis, rx_cis, ctype;
++ int minor;
++ u32 cdt_val[4] = { 0 };
++
++ /*
++ * Step 4, Read the MSn register to determine which channel(s)
++ * are causing the interrupt
++ */
++ ms0 = __raw_readl(mlb_base + REG_MS0);
++ ms1 = __raw_readl(mlb_base + REG_MS1);
++
++ /*
++ * The MLB150_MS0, MLB150_MS1 registers need to be cleared. In
++ * the spec description, the registers should be cleared when
++ * enabling interrupt. In fact, we also should clear it in ISR.
++ */
++ __raw_writel(0, mlb_base + REG_MS0);
++ __raw_writel(0, mlb_base + REG_MS1);
++
++ pr_debug("mxc_mlb150: mlb interrupt:0x%08x 0x%08x\n",
++ (u32)ms0, (u32)ms1);
++
++ for (minor = 0; minor < MLB_MINOR_DEVICES; minor++) {
++ struct mlb_dev_info *pdevinfo = &mlb_devinfo[minor];
++ u32 rx_mlb_ch = pdevinfo->channels[RX_CHANNEL].address;
++ u32 tx_mlb_ch = pdevinfo->channels[TX_CHANNEL].address;
++ u32 rx_mlb_cl = pdevinfo->channels[RX_CHANNEL].cl;
++ u32 tx_mlb_cl = pdevinfo->channels[TX_CHANNEL].cl;
++
++ tx_cis = rx_cis = 0;
++
++ ctype = pdevinfo->channel_type;
++ rx_int_sts = (rx_mlb_ch < 31) ? ms0 : ms1;
++ tx_int_sts = (tx_mlb_ch < 31) ? ms0 : ms1;
++
++ pr_debug("mxc_mlb150: channel interrupt: "
++ "tx %d: 0x%08x, rx %d: 0x%08x\n",
++ tx_mlb_ch, (u32)tx_int_sts, rx_mlb_ch, (u32)rx_int_sts);
++
++ /* Get tx channel interrupt status */
++ if (tx_int_sts & (1 << (tx_mlb_ch % 32))) {
++ mlb150_dev_cdt_read(tx_mlb_cl, cdt_val);
++ pr_debug("mxc_mlb150: TX_CH: %d, cdt_val[3]: 0x%08x, "
++ "cdt_val[2]: 0x%08x, "
++ "cdt_val[1]: 0x%08x, "
++ "cdt_val[0]: 0x%08x\n",
++ tx_mlb_ch, cdt_val[3], cdt_val[2],
++ cdt_val[1], cdt_val[0]);
++ switch (ctype) {
++ case MLB_CTYPE_SYNC:
++ tx_cis = (cdt_val[2] & ~CDT_SYNC_WSTS_MASK)
++ >> CDT_SYNC_WSTS_SHIFT;
++ /*
++ * Clear RSTS/WSTS errors to resume
++ * channel operation
++ * a. For synchronous channels: WSTS[3] = 0
++ */
++ cdt_val[2] &= ~(0x8 << CDT_SYNC_WSTS_SHIFT);
++ break;
++ case MLB_CTYPE_CTRL:
++ case MLB_CTYPE_ASYNC:
++ tx_cis = (cdt_val[2] &
++ ~CDT_CTRL_ASYNC_WSTS_MASK)
++ >> CDT_CTRL_ASYNC_WSTS_SHIFT;
++ tx_cis = (cdt_val[3] & CDT_CTRL_ASYNC_WSTS_1) ?
++ (tx_cis | (0x1 << 4)) : tx_cis;
++ /*
++ * b. For async and ctrl channels:
++ * RSTS[4]/WSTS[4] = 0
++ * and RSTS[2]/WSTS[2] = 0
++ */
++ cdt_val[3] &= ~CDT_CTRL_ASYNC_WSTS_1;
++ cdt_val[2] &=
++ ~(0x4 << CDT_CTRL_ASYNC_WSTS_SHIFT);
++ break;
++ case MLB_CTYPE_ISOC:
++ tx_cis = (cdt_val[2] & ~CDT_ISOC_WSTS_MASK)
++ >> CDT_ISOC_WSTS_SHIFT;
++ /* c. For isoc channels: WSTS[2:1] = 0x00 */
++ cdt_val[2] &= ~(0x6 << CDT_ISOC_WSTS_SHIFT);
++ break;
++ default:
++ break;
++ }
++ mlb150_dev_cdt_write(tx_mlb_ch, cdt_val);
++ }
++
++ /* Get rx channel interrupt status */
++ if (rx_int_sts & (1 << (rx_mlb_ch % 32))) {
++ mlb150_dev_cdt_read(rx_mlb_cl, cdt_val);
++ pr_debug("mxc_mlb150: RX_CH: %d, cdt_val[3]: 0x%08x, "
++ "cdt_val[2]: 0x%08x, "
++ "cdt_val[1]: 0x%08x, "
++ "cdt_val[0]: 0x%08x\n",
++ rx_mlb_ch, cdt_val[3], cdt_val[2],
++ cdt_val[1], cdt_val[0]);
++ switch (ctype) {
++ case MLB_CTYPE_SYNC:
++ tx_cis = (cdt_val[2] & ~CDT_SYNC_RSTS_MASK)
++ >> CDT_SYNC_RSTS_SHIFT;
++ cdt_val[2] &= ~(0x8 << CDT_SYNC_WSTS_SHIFT);
++ break;
++ case MLB_CTYPE_CTRL:
++ case MLB_CTYPE_ASYNC:
++ tx_cis =
++ (cdt_val[2] & ~CDT_CTRL_ASYNC_RSTS_MASK)
++ >> CDT_CTRL_ASYNC_RSTS_SHIFT;
++ tx_cis = (cdt_val[3] & CDT_CTRL_ASYNC_RSTS_1) ?
++ (tx_cis | (0x1 << 4)) : tx_cis;
++ cdt_val[3] &= ~CDT_CTRL_ASYNC_RSTS_1;
++ cdt_val[2] &=
++ ~(0x4 << CDT_CTRL_ASYNC_RSTS_SHIFT);
++ break;
++ case MLB_CTYPE_ISOC:
++ tx_cis = (cdt_val[2] & ~CDT_ISOC_RSTS_MASK)
++ >> CDT_ISOC_RSTS_SHIFT;
++ cdt_val[2] &= ~(0x6 << CDT_ISOC_WSTS_SHIFT);
++ break;
++ default:
++ break;
++ }
++ mlb150_dev_cdt_write(rx_mlb_ch, cdt_val);
++ }
++
++ if (!tx_cis && !rx_cis)
++ continue;
++
++ /* fill exception event */
++ spin_lock(&pdevinfo->event_lock);
++ pdevinfo->ex_event |= (rx_cis << 16) | tx_cis;
++ spin_unlock(&pdevinfo->event_lock);
++ }
++
++ return IRQ_HANDLED;
++}
++
++static int mxc_mlb150_open(struct inode *inode, struct file *filp)
++{
++ int minor, ring_buf_size, buf_size, j, ret;
++ void __iomem *buf_addr;
++ ulong phy_addr;
++ struct mlb_dev_info *pdevinfo = NULL;
++ struct mlb_channel_info *pchinfo = NULL;
++ struct mlb_data *drvdata;
++
++ minor = MINOR(inode->i_rdev);
++ drvdata = container_of(inode->i_cdev, struct mlb_data, cdev);
++
++ if (minor < 0 || minor >= MLB_MINOR_DEVICES) {
++ pr_err("no device\n");
++ return -ENODEV;
++ }
++
++ /* open for each channel device */
++ if (atomic_cmpxchg(&mlb_devinfo[minor].opencnt, 0, 1) != 0) {
++ pr_err("busy\n");
++ return -EBUSY;
++ }
++
++ clk_prepare_enable(drvdata->clk_mlb3p);
++
++ /* initial MLB module */
++ mlb150_dev_init();
++
++ pdevinfo = &mlb_devinfo[minor];
++ pchinfo = &pdevinfo->channels[TX_CHANNEL];
++
++ ring_buf_size = pdevinfo->buf_size;
++ buf_size = ring_buf_size * (TRANS_RING_NODES * 2);
++ buf_addr = (void __iomem *)gen_pool_alloc(drvdata->iram_pool, buf_size);
++ if (buf_addr == NULL) {
++ ret = -ENOMEM;
++ pr_err("can not alloc rx/tx buffers: %d\n", buf_size);
++ return ret;
++ }
++ phy_addr = gen_pool_virt_to_phys(drvdata->iram_pool, (ulong)buf_addr);
++ pr_debug("IRAM Range: Virt 0x%p - 0x%p, Phys 0x%x - 0x%x, size: 0x%x\n",
++ buf_addr, (buf_addr + buf_size - 1), (u32)phy_addr,
++ (u32)(phy_addr + buf_size - 1), buf_size);
++ pdevinfo->rbuf_base_virt = buf_addr;
++ pdevinfo->rbuf_base_phy = phy_addr;
++ drvdata->iram_size = buf_size;
++
++ memset(buf_addr, 0, buf_size);
++
++ for (j = 0; j < (TRANS_RING_NODES);
++ ++j, buf_addr += ring_buf_size, phy_addr += ring_buf_size) {
++ pdevinfo->rx_rbuf.virt_bufs[j] = buf_addr;
++ pdevinfo->rx_rbuf.phy_addrs[j] = phy_addr;
++ pr_debug("RX Ringbuf[%d]: 0x%p 0x%x\n",
++ j, buf_addr, (u32)phy_addr);
++ }
++ pdevinfo->rx_rbuf.unit_size = ring_buf_size;
++ pdevinfo->rx_rbuf.total_size = buf_size;
++ for (j = 0; j < (TRANS_RING_NODES);
++ ++j, buf_addr += ring_buf_size, phy_addr += ring_buf_size) {
++ pdevinfo->tx_rbuf.virt_bufs[j] = buf_addr;
++ pdevinfo->tx_rbuf.phy_addrs[j] = phy_addr;
++ pr_debug("TX Ringbuf[%d]: 0x%p 0x%x\n",
++ j, buf_addr, (u32)phy_addr);
++ }
++
++ pdevinfo->tx_rbuf.unit_size = ring_buf_size;
++ pdevinfo->tx_rbuf.total_size = buf_size;
++
++ /* reset the buffer read/write ptr */
++ pdevinfo->rx_rbuf.head = pdevinfo->rx_rbuf.tail = 0;
++ pdevinfo->tx_rbuf.head = pdevinfo->tx_rbuf.tail = 0;
++ pdevinfo->ex_event = 0;
++ pdevinfo->tx_ok = 0;
++
++ init_waitqueue_head(&pdevinfo->rx_wq);
++ init_waitqueue_head(&pdevinfo->tx_wq);
++
++ drvdata = container_of(inode->i_cdev, struct mlb_data, cdev);
++ drvdata->devinfo = pdevinfo;
++ mxc_mlb150_irq_enable(drvdata, 1);
++ filp->private_data = drvdata;
++
++ return 0;
++}
++
++static int mxc_mlb150_release(struct inode *inode, struct file *filp)
++{
++ int minor;
++ struct mlb_data *drvdata = filp->private_data;
++ struct mlb_dev_info *pdevinfo = drvdata->devinfo;
++
++ minor = MINOR(inode->i_rdev);
++ mxc_mlb150_irq_enable(drvdata, 0);
++
++#ifdef DEBUG
++ mlb150_dev_dump_reg();
++ mlb150_dev_dump_ctr_tbl(0, pdevinfo->channels[TX_CHANNEL].cl + 1);
++#endif
++
++ gen_pool_free(drvdata->iram_pool,
++ (ulong)pdevinfo->rbuf_base_virt, drvdata->iram_size);
++
++ mlb150_dev_exit();
++
++ if (pdevinfo && atomic_read(&pdevinfo->on)
++ && (pdevinfo->fps >= CLK_2048FS))
++ clk_disable_unprepare(drvdata->clk_mlb6p);
++
++ atomic_set(&pdevinfo->on, 0);
++
++ clk_disable_unprepare(drvdata->clk_mlb3p);
++ /* decrease the open count */
++ atomic_set(&pdevinfo->opencnt, 0);
++
++ drvdata->devinfo = NULL;
++
++ return 0;
++}
++
++static long mxc_mlb150_ioctl(struct file *filp,
++ unsigned int cmd, unsigned long arg)
++{
++ struct inode *inode = filp->f_path.dentry->d_inode;
++ struct mlb_data *drvdata = filp->private_data;
++ struct mlb_dev_info *pdevinfo = drvdata->devinfo;
++ void __user *argp = (void __user *)arg;
++ unsigned long flags, event;
++ int minor;
++
++ minor = MINOR(inode->i_rdev);
++
++ switch (cmd) {
++ case MLB_CHAN_SETADDR:
++ {
++ unsigned int caddr;
++ /* get channel address from user space */
++ if (copy_from_user(&caddr, argp, sizeof(caddr))) {
++ pr_err("mxc_mlb150: copy from user failed\n");
++ return -EFAULT;
++ }
++ pdevinfo->channels[TX_CHANNEL].address =
++ (caddr >> 16) & 0xFFFF;
++ pdevinfo->channels[RX_CHANNEL].address = caddr & 0xFFFF;
++ pr_debug("mxc_mlb150: set ch addr, tx: %d, rx: %d\n",
++ pdevinfo->channels[TX_CHANNEL].address,
++ pdevinfo->channels[RX_CHANNEL].address);
++ break;
++ }
++
++ case MLB_CHAN_STARTUP:
++ if (atomic_read(&pdevinfo->on)) {
++ pr_debug("mxc_mlb150: channel alreadly startup\n");
++ break;
++ }
++ if (mlb_channel_enable(drvdata, minor, 1))
++ return -EFAULT;
++ break;
++ case MLB_CHAN_SHUTDOWN:
++ if (atomic_read(&pdevinfo->on) == 0) {
++ pr_debug("mxc_mlb150: channel areadly shutdown\n");
++ break;
++ }
++ mlb150_trans_complete_check(pdevinfo);
++ mlb_channel_enable(drvdata, minor, 0);
++ break;
++ case MLB_CHAN_GETEVENT:
++ /* get and clear the ex_event */
++ spin_lock_irqsave(&pdevinfo->event_lock, flags);
++ event = pdevinfo->ex_event;
++ pdevinfo->ex_event = 0;
++ spin_unlock_irqrestore(&pdevinfo->event_lock, flags);
++
++ if (event) {
++ if (copy_to_user(argp, &event, sizeof(event))) {
++ pr_err("mxc_mlb150: copy to user failed\n");
++ return -EFAULT;
++ }
++ } else
++ return -EAGAIN;
++ break;
++ case MLB_SET_ISOC_BLKSIZE_188:
++ pdevinfo->isoc_blksz = 188;
++ pdevinfo->cdt_buf_dep = pdevinfo->adt_buf_dep =
++ pdevinfo->isoc_blksz * CH_ISOC_BLK_NUM;
++ break;
++ case MLB_SET_ISOC_BLKSIZE_196:
++ pdevinfo->isoc_blksz = 196;
++ pdevinfo->cdt_buf_dep = pdevinfo->adt_buf_dep =
++ pdevinfo->isoc_blksz * CH_ISOC_BLK_NUM;
++ break;
++ case MLB_SET_SYNC_QUAD:
++ {
++ u32 quad;
++
++ if (copy_from_user(&quad, argp, sizeof(quad))) {
++ pr_err("mxc_mlb150: get quad number "
++ "from user failed\n");
++ return -EFAULT;
++ }
++ if (quad <= 0 || quad > 3) {
++ pr_err("mxc_mlb150: Invalid Quadlets!"
++ "Quadlets in Sync mode can "
++ "only be 1, 2, 3\n");
++ return -EINVAL;
++ }
++ pdevinfo->sync_quad = quad;
++ /* Each quadlets is 4 bytes */
++ pdevinfo->cdt_buf_dep = quad * 4 * 4;
++ pdevinfo->adt_buf_dep =
++ pdevinfo->cdt_buf_dep * CH_SYNC_ADT_BUF_MULTI;
++ }
++ break;
++ case MLB_SET_FPS:
++ {
++ u32 fps, c0_val;
++
++ /* get fps from user space */
++ if (copy_from_user(&fps, argp, sizeof(fps))) {
++ pr_err("mxc_mlb150: copy from user failed\n");
++ return -EFAULT;
++ }
++
++ c0_val = __raw_readl(mlb_base + REG_MLBC0);
++ c0_val &= ~MLBC0_MLBCLK_MASK;
++
++ /* check fps value */
++ switch (fps) {
++ case 256:
++ case 512:
++ case 1024:
++ pdevinfo->fps = fps >> 9;
++ c0_val &= ~MLBC0_MLBPEN;
++ c0_val |= (fps >> 9)
++ << MLBC0_MLBCLK_SHIFT;
++
++ if (1024 == fps) {
++ /*
++ * Invert output clock phase
++ * in 1024 fps
++ */
++ __raw_writel(0x1,
++ mlb_base + REG_MLBPC2);
++ }
++ break;
++ case 2048:
++ case 3072:
++ case 4096:
++ pdevinfo->fps = (fps >> 10) + 1;
++ c0_val |= ((fps >> 10) + 1)
++ << MLBC0_MLBCLK_SHIFT;
++ break;
++ case 6144:
++ pdevinfo->fps = fps >> 10;
++ c0_val |= ((fps >> 10) + 1)
++ << MLBC0_MLBCLK_SHIFT;
++ break;
++ case 8192:
++ pdevinfo->fps = (fps >> 10) - 1;
++ c0_val |= ((fps >> 10) - 1)
++ << MLBC0_MLBCLK_SHIFT;
++ break;
++ default:
++ pr_debug("mxc_mlb150: invalid fps argument: %d\n",
++ fps);
++ return -EINVAL;
++ }
++
++ __raw_writel(c0_val, mlb_base + REG_MLBC0);
++
++ pr_debug("mxc_mlb150: set fps to %d, MLBC0: 0x%08x\n",
++ fps,
++ (u32)__raw_readl(mlb_base + REG_MLBC0));
++
++ break;
++ }
++
++ case MLB_GET_VER:
++ {
++ u32 version;
++
++ /* get MLB device module version */
++ version = 0x03030003;
++
++ pr_debug("mxc_mlb150: get version: 0x%08x\n",
++ version);
++
++ if (copy_to_user(argp, &version, sizeof(version))) {
++ pr_err("mxc_mlb150: copy to user failed\n");
++ return -EFAULT;
++ }
++ break;
++ }
++
++ case MLB_SET_DEVADDR:
++ {
++ u32 c1_val;
++ u8 devaddr;
++
++ /* get MLB device address from user space */
++ if (copy_from_user
++ (&devaddr, argp, sizeof(unsigned char))) {
++ pr_err("mxc_mlb150: copy from user failed\n");
++ return -EFAULT;
++ }
++
++ c1_val = __raw_readl(mlb_base + REG_MLBC1);
++ c1_val &= ~MLBC1_NDA_MASK;
++ c1_val |= devaddr << MLBC1_NDA_SHIFT;
++ __raw_writel(c1_val, mlb_base + REG_MLBC1);
++ pr_debug("mxc_mlb150: set dev addr, dev addr: %d, "
++ "MLBC1: 0x%08x\n", devaddr,
++ (u32)__raw_readl(mlb_base + REG_MLBC1));
++
++ break;
++ }
++
++ case MLB_IRQ_DISABLE:
++ {
++ disable_irq(drvdata->irq_mlb);
++ break;
++ }
++
++ case MLB_IRQ_ENABLE:
++ {
++ enable_irq(drvdata->irq_mlb);
++ break;
++ }
++ default:
++ pr_info("mxc_mlb150: Invalid ioctl command\n");
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++/*
++ * MLB read routine
++ * Read the current received data from queued buffer,
++ * and free this buffer for hw to fill ingress data.
++ */
++static ssize_t mxc_mlb150_read(struct file *filp, char __user *buf,
++ size_t count, loff_t *f_pos)
++{
++ int size;
++ struct mlb_data *drvdata = filp->private_data;
++ struct mlb_dev_info *pdevinfo = drvdata->devinfo;
++ struct mlb_ringbuf *rx_rbuf = &pdevinfo->rx_rbuf;
++ int head, tail;
++ unsigned long flags;
++
++ read_lock_irqsave(&rx_rbuf->rb_lock, flags);
++
++ head = ACCESS_ONCE(rx_rbuf->head);
++ tail = rx_rbuf->tail;
++
++ read_unlock_irqrestore(&rx_rbuf->rb_lock, flags);
++
++ /* check the current rx buffer is available or not */
++ if (0 == CIRC_CNT(head, tail, TRANS_RING_NODES)) {
++
++ if (filp->f_flags & O_NONBLOCK)
++ return -EAGAIN;
++
++ do {
++ DEFINE_WAIT(__wait);
++
++ for (;;) {
++ prepare_to_wait(&pdevinfo->rx_wq,
++ &__wait, TASK_INTERRUPTIBLE);
++
++ read_lock_irqsave(&rx_rbuf->rb_lock, flags);
++ if (CIRC_CNT(rx_rbuf->head, rx_rbuf->tail,
++ TRANS_RING_NODES) > 0) {
++ read_unlock_irqrestore(&rx_rbuf->rb_lock,
++ flags);
++ break;
++ }
++ read_unlock_irqrestore(&rx_rbuf->rb_lock,
++ flags);
++
++ if (!signal_pending(current)) {
++ schedule();
++ continue;
++ }
++ return -ERESTARTSYS;
++ }
++ finish_wait(&pdevinfo->rx_wq, &__wait);
++ } while (0);
++ }
++
++ /* read index before reading contents at that index */
++ smp_read_barrier_depends();
++
++ size = pdevinfo->adt_buf_dep;
++ if (size > count) {
++ /* the user buffer is too small */
++ pr_warning
++ ("mxc_mlb150: received data size is bigger than "
++ "size: %d, count: %d\n", size, count);
++ return -EINVAL;
++ }
++
++ /* extract one item from the buffer */
++ if (copy_to_user(buf, rx_rbuf->virt_bufs[tail], size)) {
++ pr_err("mxc_mlb150: copy from user failed\n");
++ return -EFAULT;
++ }
++
++ /* finish reading descriptor before incrementing tail */
++ smp_mb();
++
++ write_lock_irqsave(&rx_rbuf->rb_lock, flags);
++ rx_rbuf->tail = (tail + 1) & (TRANS_RING_NODES - 1);
++ write_unlock_irqrestore(&rx_rbuf->rb_lock, flags);
++
++ *f_pos = 0;
++
++ return size;
++}
++
++/*
++ * MLB write routine
++ * Copy the user data to tx channel buffer,
++ * and prepare the channel current/next buffer ptr.
++ */
++static ssize_t mxc_mlb150_write(struct file *filp, const char __user *buf,
++ size_t count, loff_t *f_pos)
++{
++ s32 ret = 0;
++ struct mlb_channel_info *pchinfo = NULL;
++ struct mlb_data *drvdata = filp->private_data;
++ struct mlb_dev_info *pdevinfo = drvdata->devinfo;
++ struct mlb_ringbuf *tx_rbuf = &pdevinfo->tx_rbuf;
++ int head, tail;
++ unsigned long flags;
++
++ /*
++ * minor = MINOR(filp->f_dentry->d_inode->i_rdev);
++ */
++ pchinfo = &pdevinfo->channels[TX_CHANNEL];
++
++ if (count > pdevinfo->buf_size) {
++ /* too many data to write */
++ pr_warning("mxc_mlb150: overflow write data\n");
++ return -EFBIG;
++ }
++
++ *f_pos = 0;
++
++ read_lock_irqsave(&tx_rbuf->rb_lock, flags);
++
++ head = tx_rbuf->head;
++ tail = ACCESS_ONCE(tx_rbuf->tail);
++ read_unlock_irqrestore(&tx_rbuf->rb_lock, flags);
++
++ if (0 == CIRC_SPACE(head, tail, TRANS_RING_NODES)) {
++ if (filp->f_flags & O_NONBLOCK)
++ return -EAGAIN;
++ do {
++ DEFINE_WAIT(__wait);
++
++ for (;;) {
++ prepare_to_wait(&pdevinfo->tx_wq,
++ &__wait, TASK_INTERRUPTIBLE);
++
++ read_lock_irqsave(&tx_rbuf->rb_lock, flags);
++ if (CIRC_SPACE(tx_rbuf->head, tx_rbuf->tail,
++ TRANS_RING_NODES) > 0) {
++ read_unlock_irqrestore(&tx_rbuf->rb_lock,
++ flags);
++ break;
++ }
++ read_unlock_irqrestore(&tx_rbuf->rb_lock,
++ flags);
++
++ if (!signal_pending(current)) {
++ schedule();
++ continue;
++ }
++ return -ERESTARTSYS;
++ }
++ finish_wait(&pdevinfo->tx_wq, &__wait);
++ } while (0);
++ }
++
++ if (copy_from_user((void *)tx_rbuf->virt_bufs[head], buf, count)) {
++ read_unlock_irqrestore(&tx_rbuf->rb_lock, flags);
++ pr_err("mxc_mlb: copy from user failed\n");
++ ret = -EFAULT;
++ goto out;
++ }
++
++ write_lock_irqsave(&tx_rbuf->rb_lock, flags);
++ smp_wmb();
++ tx_rbuf->head = (head + 1) & (TRANS_RING_NODES - 1);
++ write_unlock_irqrestore(&tx_rbuf->rb_lock, flags);
++
++ if (0 == CIRC_CNT(head, tail, TRANS_RING_NODES)) {
++ u32 tx_buf_ptr, ahb_ch;
++ s32 adt_sts;
++ u32 ctype = pdevinfo->channel_type;
++
++ /* read index before reading contents at that index */
++ smp_read_barrier_depends();
++
++ tx_buf_ptr = tx_rbuf->phy_addrs[tail];
++
++ ahb_ch = pdevinfo->channels[TX_CHANNEL].cl;
++ adt_sts = mlb150_dev_get_adt_sts(ahb_ch);
++
++ /* Set ADT for TX */
++ mlb150_dev_pipo_next(ahb_ch, ctype, adt_sts, tx_buf_ptr);
++ }
++
++ ret = count;
++out:
++ return ret;
++}
++
++static unsigned int mxc_mlb150_poll(struct file *filp,
++ struct poll_table_struct *wait)
++{
++ int minor;
++ unsigned int ret = 0;
++ struct mlb_data *drvdata = filp->private_data;
++ struct mlb_dev_info *pdevinfo = drvdata->devinfo;
++ struct mlb_ringbuf *tx_rbuf = &pdevinfo->tx_rbuf;
++ struct mlb_ringbuf *rx_rbuf = &pdevinfo->rx_rbuf;
++ int head, tail;
++ unsigned long flags;
++
++
++ minor = MINOR(filp->f_path.dentry->d_inode->i_rdev);
++
++ poll_wait(filp, &pdevinfo->rx_wq, wait);
++ poll_wait(filp, &pdevinfo->tx_wq, wait);
++
++ read_lock_irqsave(&tx_rbuf->rb_lock, flags);
++ head = tx_rbuf->head;
++ tail = tx_rbuf->tail;
++ read_unlock_irqrestore(&tx_rbuf->rb_lock, flags);
++
++ /* check the tx buffer is avaiable or not */
++ if (CIRC_SPACE(head, tail, TRANS_RING_NODES) >= 1)
++ ret |= POLLOUT | POLLWRNORM;
++
++ read_lock_irqsave(&rx_rbuf->rb_lock, flags);
++ head = rx_rbuf->head;
++ tail = rx_rbuf->tail;
++ read_unlock_irqrestore(&rx_rbuf->rb_lock, flags);
++
++ /* check the rx buffer filled or not */
++ if (CIRC_CNT(head, tail, TRANS_RING_NODES) >= 1)
++ ret |= POLLIN | POLLRDNORM;
++
++
++ /* check the exception event */
++ if (pdevinfo->ex_event)
++ ret |= POLLIN | POLLRDNORM;
++
++ return ret;
++}
++
++/*
++ * char dev file operations structure
++ */
++static const struct file_operations mxc_mlb150_fops = {
++
++ .owner = THIS_MODULE,
++ .open = mxc_mlb150_open,
++ .release = mxc_mlb150_release,
++ .unlocked_ioctl = mxc_mlb150_ioctl,
++ .poll = mxc_mlb150_poll,
++ .read = mxc_mlb150_read,
++ .write = mxc_mlb150_write,
++};
++
++static struct platform_device_id imx_mlb150_devtype[] = {
++ {
++ .name = "imx6q-mlb150",
++ .driver_data = 0,
++ }, {
++ /* sentinel */
++ }
++};
++MODULE_DEVICE_TABLE(platform, imx_mlb150_devtype);
++
++static const struct of_device_id mlb150_imx_dt_ids[] = {
++ { .compatible = "fsl,imx6q-mlb150", .data = &imx_mlb150_devtype[0], },
++ { /* sentinel */ }
++};
++
++/*
++ * This function is called whenever the MLB device is detected.
++ */
++static int mxc_mlb150_probe(struct platform_device *pdev)
++{
++ int ret, mlb_major, i;
++ struct mlb_data *drvdata;
++ struct resource *res;
++ struct device_node *np = pdev->dev.of_node;
++
++ drvdata = devm_kzalloc(&pdev->dev, sizeof(struct mlb_data),
++ GFP_KERNEL);
++ if (!drvdata) {
++ dev_err(&pdev->dev, "can't allocate enough memory\n");
++ return -ENOMEM;
++ }
++
++ /*
++ * Register MLB lld as four character devices
++ */
++ ret = alloc_chrdev_region(&drvdata->firstdev, 0,
++ MLB_MINOR_DEVICES, "mxc_mlb150");
++ if (ret < 0) {
++ dev_err(&pdev->dev, "alloc region error\n");
++ goto err_reg;
++ }
++ mlb_major = MAJOR(drvdata->firstdev);
++ dev_dbg(&pdev->dev, "MLB device major: %d\n", mlb_major);
++
++ cdev_init(&drvdata->cdev, &mxc_mlb150_fops);
++ drvdata->cdev.owner = THIS_MODULE;
++
++ ret = cdev_add(&drvdata->cdev, drvdata->firstdev, MLB_MINOR_DEVICES);
++ if (ret) {
++ dev_err(&pdev->dev, "can't add cdev\n");
++ goto err_reg;
++ }
++
++ /* create class and device for udev information */
++ drvdata->class = class_create(THIS_MODULE, "mlb150");
++ if (IS_ERR(drvdata->class)) {
++ dev_err(&pdev->dev, "failed to create device class\n");
++ ret = -ENOMEM;
++ goto err_class;
++ }
++
++ for (i = 0; i < MLB_MINOR_DEVICES; i++) {
++ struct device *class_dev;
++
++ class_dev = device_create(drvdata->class, NULL,
++ MKDEV(mlb_major, i),
++ NULL, mlb_devinfo[i].dev_name);
++ if (IS_ERR(class_dev)) {
++ dev_err(&pdev->dev, "failed to create mlb150 %s"
++ " class device\n", mlb_devinfo[i].dev_name);
++ ret = -ENOMEM;
++ goto err_dev;
++ }
++ }
++
++ /* ahb0 irq */
++ drvdata->irq_ahb0 = platform_get_irq(pdev, 1);
++ if (drvdata->irq_ahb0 < 0) {
++ dev_err(&pdev->dev, "No ahb0 irq line provided\n");
++ goto err_dev;
++ }
++ dev_dbg(&pdev->dev, "ahb0_irq: %d\n", drvdata->irq_ahb0);
++ if (devm_request_irq(&pdev->dev, drvdata->irq_ahb0, mlb_ahb_isr,
++ 0, "mlb_ahb0", NULL)) {
++ dev_err(&pdev->dev, "can't claim irq %d\n", drvdata->irq_ahb0);
++ goto err_dev;
++ }
++
++ /* ahb1 irq */
++ drvdata->irq_ahb1 = platform_get_irq(pdev, 2);
++ if (drvdata->irq_ahb1 < 0) {
++ dev_err(&pdev->dev, "No ahb1 irq line provided\n");
++ goto err_dev;
++ }
++ dev_dbg(&pdev->dev, "ahb1_irq: %d\n", drvdata->irq_ahb1);
++ if (devm_request_irq(&pdev->dev, drvdata->irq_ahb1, mlb_ahb_isr,
++ 0, "mlb_ahb1", NULL)) {
++ dev_err(&pdev->dev, "can't claim irq %d\n", drvdata->irq_ahb1);
++ goto err_dev;
++ }
++
++ /* mlb irq */
++ drvdata->irq_mlb = platform_get_irq(pdev, 0);
++ if (drvdata->irq_mlb < 0) {
++ dev_err(&pdev->dev, "No mlb irq line provided\n");
++ goto err_dev;
++ }
++ dev_dbg(&pdev->dev, "mlb_irq: %d\n", drvdata->irq_mlb);
++ if (devm_request_irq(&pdev->dev, drvdata->irq_mlb, mlb_isr,
++ 0, "mlb", NULL)) {
++ dev_err(&pdev->dev, "can't claim irq %d\n", drvdata->irq_mlb);
++ goto err_dev;
++ }
++
++ /* ioremap from phy mlb to kernel space */
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (!res) {
++ dev_err(&pdev->dev, "can't get device resources\n");
++ ret = -ENOENT;
++ goto err_dev;
++ }
++ mlb_base = devm_ioremap_resource(&pdev->dev, res);
++ dev_dbg(&pdev->dev, "mapped base address: 0x%08x\n", (u32)mlb_base);
++ if (IS_ERR(mlb_base)) {
++ dev_err(&pdev->dev,
++ "failed to get ioremap base\n");
++ ret = PTR_ERR(mlb_base);
++ goto err_dev;
++ }
++ drvdata->membase = mlb_base;
++
++#ifdef CONFIG_REGULATOR
++ drvdata->nvcc = devm_regulator_get(&pdev->dev, "reg_nvcc");
++ if (!IS_ERR(drvdata->nvcc)) {
++ regulator_set_voltage(drvdata->nvcc, 2500000, 2500000);
++ dev_err(&pdev->dev, "enalbe regulator\n");
++ ret = regulator_enable(drvdata->nvcc);
++ if (ret) {
++ dev_err(&pdev->dev, "vdd set voltage error\n");
++ goto err_dev;
++ }
++ }
++#endif
++
++ /* enable clock */
++ drvdata->clk_mlb3p = devm_clk_get(&pdev->dev, "mlb");
++ if (IS_ERR(drvdata->clk_mlb3p)) {
++ dev_err(&pdev->dev, "unable to get mlb clock\n");
++ ret = PTR_ERR(drvdata->clk_mlb3p);
++ goto err_dev;
++ }
++
++ drvdata->clk_mlb6p = devm_clk_get(&pdev->dev, "pll8_mlb");
++ if (IS_ERR(drvdata->clk_mlb6p)) {
++ dev_err(&pdev->dev, "unable to get mlb pll clock\n");
++ ret = PTR_ERR(drvdata->clk_mlb6p);
++ goto err_dev;
++ }
++
++
++ drvdata->iram_pool = of_get_named_gen_pool(np, "iram", 0);
++ if (!drvdata->iram_pool) {
++ dev_err(&pdev->dev, "iram pool not available\n");
++ ret = -ENOMEM;
++ goto err_dev;
++ }
++
++ drvdata->devinfo = NULL;
++ mxc_mlb150_irq_enable(drvdata, 0);
++ platform_set_drvdata(pdev, drvdata);
++ return 0;
++
++err_dev:
++ for (--i; i >= 0; i--)
++ device_destroy(drvdata->class, MKDEV(mlb_major, i));
++
++ class_destroy(drvdata->class);
++err_class:
++ cdev_del(&drvdata->cdev);
++err_reg:
++ unregister_chrdev_region(drvdata->firstdev, MLB_MINOR_DEVICES);
++
++ return ret;
++}
++
++static int mxc_mlb150_remove(struct platform_device *pdev)
++{
++ int i;
++ struct mlb_data *drvdata = platform_get_drvdata(pdev);
++ struct mlb_dev_info *pdevinfo = drvdata->devinfo;
++
++ if (pdevinfo && atomic_read(&pdevinfo->on)
++ && (pdevinfo->fps >= CLK_2048FS))
++ clk_disable_unprepare(drvdata->clk_mlb6p);
++
++ if (pdevinfo && atomic_read(&pdevinfo->opencnt))
++ clk_disable_unprepare(drvdata->clk_mlb3p);
++
++ /* disable mlb power */
++#ifdef CONFIG_REGULATOR
++ if (!IS_ERR(drvdata->nvcc))
++ regulator_disable(drvdata->nvcc);
++#endif
++
++ /* destroy mlb device class */
++ for (i = MLB_MINOR_DEVICES - 1; i >= 0; i--)
++ device_destroy(drvdata->class,
++ MKDEV(MAJOR(drvdata->firstdev), i));
++ class_destroy(drvdata->class);
++
++ cdev_del(&drvdata->cdev);
++
++ /* Unregister the two MLB devices */
++ unregister_chrdev_region(drvdata->firstdev, MLB_MINOR_DEVICES);
++
++ return 0;
++}
++
++#ifdef CONFIG_PM
++static int mxc_mlb150_suspend(struct platform_device *pdev, pm_message_t state)
++{
++ struct mlb_data *drvdata = platform_get_drvdata(pdev);
++ struct mlb_dev_info *pdevinfo = drvdata->devinfo;
++
++ if (pdevinfo && atomic_read(&pdevinfo->on)
++ && (pdevinfo->fps >= CLK_2048FS))
++ clk_disable_unprepare(drvdata->clk_mlb6p);
++
++ if (pdevinfo && atomic_read(&pdevinfo->opencnt)) {
++ mlb150_dev_exit();
++ clk_disable_unprepare(drvdata->clk_mlb3p);
++ }
++
++ return 0;
++}
++
++static int mxc_mlb150_resume(struct platform_device *pdev)
++{
++ struct mlb_data *drvdata = platform_get_drvdata(pdev);
++ struct mlb_dev_info *pdevinfo = drvdata->devinfo;
++
++ if (pdevinfo && atomic_read(&pdevinfo->opencnt)) {
++ clk_prepare_enable(drvdata->clk_mlb3p);
++ mlb150_dev_init();
++ }
++
++ if (pdevinfo && atomic_read(&pdevinfo->on) &&
++ (pdevinfo->fps >= CLK_2048FS))
++ clk_prepare_enable(drvdata->clk_mlb6p);
++
++ return 0;
++}
++#else
++#define mxc_mlb150_suspend NULL
++#define mxc_mlb150_resume NULL
++#endif
++
++/*
++ * platform driver structure for MLB
++ */
++static struct platform_driver mxc_mlb150_driver = {
++ .driver = {
++ .name = DRIVER_NAME,
++ .owner = THIS_MODULE,
++ .of_match_table = mlb150_imx_dt_ids,
++ },
++ .probe = mxc_mlb150_probe,
++ .remove = mxc_mlb150_remove,
++ .suspend = mxc_mlb150_suspend,
++ .resume = mxc_mlb150_resume,
++ .id_table = imx_mlb150_devtype,
++};
++
++static int __init mxc_mlb150_init(void)
++{
++ return platform_driver_register(&mxc_mlb150_driver);
++}
++
++static void __exit mxc_mlb150_exit(void)
++{
++ platform_driver_unregister(&mxc_mlb150_driver);
++}
++
++module_init(mxc_mlb150_init);
++module_exit(mxc_mlb150_exit);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("MLB150 low level driver");
++MODULE_LICENSE("GPL");
+diff -Nur linux-4.1.3/drivers/mxc/vpu/Kconfig linux-xbian-imx6/drivers/mxc/vpu/Kconfig
+--- linux-4.1.3/drivers/mxc/vpu/Kconfig 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/vpu/Kconfig 2015-07-27 23:13:06.230751680 +0200
+@@ -0,0 +1,31 @@
++#
++# Codec configuration
++#
++
++menu "MXC VPU(Video Processing Unit) support"
++
++config MXC_VPU
++ tristate "Support for MXC VPU(Video Processing Unit)"
++ depends on (SOC_IMX27 || SOC_IMX5 || SOC_IMX6Q)
++ default y
++ ---help---
++ The VPU codec device provides codec function for H.264/MPEG4/H.263,
++ as well as MPEG2/VC-1/DivX on some platforms.
++
++config MXC_VPU_DEBUG
++ bool "MXC VPU debugging"
++ depends on MXC_VPU != n
++ help
++ This is an option for the developers; most people should
++ say N here. This enables MXC VPU driver debugging.
++
++config MX6_VPU_352M
++ bool "MX6 VPU 352M"
++ depends on MXC_VPU
++ default n
++ help
++ Increase VPU frequncy to 352M, the config will disable bus frequency
++ adjust dynamic, and CPU lowest setpoint will be 352Mhz.
++ This config is used for special VPU use case.
++
++endmenu
+diff -Nur linux-4.1.3/drivers/mxc/vpu/Makefile linux-xbian-imx6/drivers/mxc/vpu/Makefile
+--- linux-4.1.3/drivers/mxc/vpu/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/vpu/Makefile 2015-07-27 23:13:06.230751680 +0200
+@@ -0,0 +1,9 @@
++#
++# Makefile for the VPU drivers.
++#
++
++obj-$(CONFIG_MXC_VPU) += mxc_vpu.o
++
++ifeq ($(CONFIG_MXC_VPU_DEBUG),y)
++EXTRA_CFLAGS += -DDEBUG
++endif
+diff -Nur linux-4.1.3/drivers/mxc/vpu/mxc_vpu.c linux-xbian-imx6/drivers/mxc/vpu/mxc_vpu.c
+--- linux-4.1.3/drivers/mxc/vpu/mxc_vpu.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/mxc/vpu/mxc_vpu.c 2015-07-27 23:13:06.230751680 +0200
+@@ -0,0 +1,1344 @@
++/*
++ * Copyright 2006-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*!
++ * @file mxc_vpu.c
++ *
++ * @brief VPU system initialization and file operation implementation
++ *
++ * @ingroup VPU
++ */
++#include <linux/kernel.h>
++#include <linux/mm.h>
++#include <linux/interrupt.h>
++#include <linux/ioport.h>
++#include <linux/stat.h>
++#include <linux/platform_device.h>
++#include <linux/kdev_t.h>
++#include <linux/dma-mapping.h>
++#include <linux/wait.h>
++#include <linux/list.h>
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/fsl_devices.h>
++#include <linux/uaccess.h>
++#include <linux/io.h>
++#include <linux/slab.h>
++#include <linux/workqueue.h>
++#include <linux/sched.h>
++#include <linux/vmalloc.h>
++#include <linux/regulator/consumer.h>
++#include <linux/page-flags.h>
++#include <linux/mm_types.h>
++#include <linux/types.h>
++#include <linux/memblock.h>
++#include <linux/memory.h>
++#include <linux/version.h>
++#include <asm/page.h>
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)
++#include <linux/module.h>
++#include <linux/pm_runtime.h>
++#include <linux/sizes.h>
++#endif
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 10, 0)
++#include <linux/iram_alloc.h>
++#include <mach/clock.h>
++#include <mach/hardware.h>
++#include <mach/mxc_vpu.h>
++#endif
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0)
++#include <linux/busfreq-imx6.h>
++#include <linux/clk.h>
++#include <linux/genalloc.h>
++#include <linux/mxc_vpu.h>
++#include <linux/of.h>
++#include <linux/reset.h>
++#elif LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)
++#include <mach/busfreq.h>
++#include <mach/common.h>
++#else
++#include <asm/sizes.h>
++#endif
++
++/* Define one new pgprot which combined uncached and XN(never executable) */
++#define pgprot_noncachedxn(prot) \
++ __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED | L_PTE_XN)
++
++struct vpu_priv {
++ struct fasync_struct *async_queue;
++ struct work_struct work;
++ struct workqueue_struct *workqueue;
++ struct mutex lock;
++};
++
++/* To track the allocated memory buffer */
++struct memalloc_record {
++ struct list_head list;
++ struct vpu_mem_desc mem;
++};
++
++struct iram_setting {
++ u32 start;
++ u32 end;
++};
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0)
++static struct gen_pool *iram_pool;
++static u32 iram_base;
++#endif
++
++static LIST_HEAD(head);
++
++static int vpu_major;
++static int vpu_clk_usercount;
++static struct class *vpu_class;
++static struct vpu_priv vpu_data;
++static u8 open_count;
++static struct clk *vpu_clk;
++static struct vpu_mem_desc bitwork_mem = { 0 };
++static struct vpu_mem_desc pic_para_mem = { 0 };
++static struct vpu_mem_desc user_data_mem = { 0 };
++static struct vpu_mem_desc share_mem = { 0 };
++static struct vpu_mem_desc vshare_mem = { 0 };
++
++static void __iomem *vpu_base;
++static int vpu_ipi_irq;
++static u32 phy_vpu_base_addr;
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 5, 0)
++static phys_addr_t top_address_DRAM;
++static struct mxc_vpu_platform_data *vpu_plat;
++#endif
++
++static struct device *vpu_dev;
++
++/* IRAM setting */
++static struct iram_setting iram;
++
++/* implement the blocking ioctl */
++static int irq_status;
++static int codec_done;
++static wait_queue_head_t vpu_queue;
++
++#ifdef CONFIG_SOC_IMX6Q
++#define MXC_VPU_HAS_JPU
++#endif
++
++#ifdef MXC_VPU_HAS_JPU
++static int vpu_jpu_irq;
++#endif
++
++#ifdef CONFIG_PM
++static unsigned int regBk[64];
++static unsigned int pc_before_suspend;
++#endif
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 5, 0) || LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0)
++static struct regulator *vpu_regulator;
++#endif
++static atomic_t clk_cnt_from_ioc = ATOMIC_INIT(0);
++
++#define READ_REG(x) readl_relaxed(vpu_base + x)
++#define WRITE_REG(val, x) writel_relaxed(val, vpu_base + x)
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)
++/* redirect to static functions */
++static int cpu_is_mx6dl(void)
++{
++ int ret;
++ ret = of_machine_is_compatible("fsl,imx6dl");
++ return ret;
++}
++
++static int cpu_is_mx6q(void)
++{
++ int ret;
++ ret = of_machine_is_compatible("fsl,imx6q");
++ return ret;
++}
++#endif
++
++static void vpu_reset(void)
++{
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0)
++ device_reset(vpu_dev);
++#elif LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)
++ imx_src_reset_vpu();
++#else
++ if (vpu_plat->reset)
++ vpu_plat->reset();
++#endif
++}
++
++static long vpu_power_get(bool on)
++{
++ long ret = 0;
++
++ if (on) {
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 5, 0)
++ vpu_regulator = regulator_get(NULL, "cpu_vddvpu");
++ ret = IS_ERR(vpu_regulator);
++#elif LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0)
++ vpu_regulator = devm_regulator_get(vpu_dev, "pu");
++ ret = IS_ERR(vpu_regulator);
++#endif
++ } else {
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 5, 0)
++ if (!IS_ERR(vpu_regulator))
++ regulator_put(vpu_regulator);
++#endif
++ }
++ return ret;
++}
++
++static void vpu_power_up(bool on)
++{
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 5, 0) || LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0)
++ int ret = 0;
++
++ if (on) {
++ if (!IS_ERR(vpu_regulator)) {
++ ret = regulator_enable(vpu_regulator);
++ if (ret)
++ dev_err(vpu_dev, "failed to power up vpu\n");
++ }
++ } else {
++ if (!IS_ERR(vpu_regulator)) {
++ ret = regulator_disable(vpu_regulator);
++ if (ret)
++ dev_err(vpu_dev, "failed to power down vpu\n");
++ }
++ }
++#else
++ imx_gpc_power_up_pu(on);
++#endif
++}
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0)
++static int cpu_is_mx53(void)
++{
++ return 0;
++}
++
++static int cpu_is_mx51(void)
++{
++ return 0;
++}
++
++#define VM_RESERVED 0
++#endif
++
++/*!
++ * Private function to alloc dma buffer
++ * @return status 0 success.
++ */
++static int vpu_alloc_dma_buffer(struct vpu_mem_desc *mem)
++{
++ mem->cpu_addr = (unsigned long)
++ dma_zalloc_coherent(NULL, PAGE_ALIGN(mem->size),
++ (dma_addr_t *) (&mem->phy_addr),
++ GFP_DMA | GFP_KERNEL);
++ dev_dbg(vpu_dev, "[ALLOC] mem alloc cpu_addr = 0x%x\n", mem->cpu_addr);
++ if ((void *)(mem->cpu_addr) == NULL) {
++ dev_err(vpu_dev, "Physical memory allocation error!\n");
++ return -1;
++ }
++ return 0;
++}
++
++/*!
++ * Private function to free dma buffer
++ */
++static void vpu_free_dma_buffer(struct vpu_mem_desc *mem)
++{
++ if (mem->cpu_addr != 0) {
++ dma_free_coherent(0, PAGE_ALIGN(mem->size),
++ (void *)mem->cpu_addr, mem->phy_addr);
++ }
++}
++
++/*!
++ * Private function to free buffers
++ * @return status 0 success.
++ */
++static int vpu_free_buffers(void)
++{
++ struct memalloc_record *rec, *n;
++ struct vpu_mem_desc mem;
++
++ list_for_each_entry_safe(rec, n, &head, list) {
++ mem = rec->mem;
++ if (mem.cpu_addr != 0) {
++ vpu_free_dma_buffer(&mem);
++ dev_dbg(vpu_dev, "[FREE] freed paddr=0x%08X\n", mem.phy_addr);
++ /* delete from list */
++ list_del(&rec->list);
++ kfree(rec);
++ }
++ }
++
++ return 0;
++}
++
++static inline void vpu_worker_callback(struct work_struct *w)
++{
++ struct vpu_priv *dev = container_of(w, struct vpu_priv,
++ work);
++
++ if (dev->async_queue)
++ kill_fasync(&dev->async_queue, SIGIO, POLL_IN);
++
++ irq_status = 1;
++ /*
++ * Clock is gated on when dec/enc started, gate it off when
++ * codec is done.
++ */
++ if (codec_done)
++ codec_done = 0;
++
++ wake_up_interruptible(&vpu_queue);
++}
++
++/*!
++ * @brief vpu interrupt handler
++ */
++static irqreturn_t vpu_ipi_irq_handler(int irq, void *dev_id)
++{
++ struct vpu_priv *dev = dev_id;
++ unsigned long reg;
++
++ reg = READ_REG(BIT_INT_REASON);
++ if (reg & 0x8)
++ codec_done = 1;
++ WRITE_REG(0x1, BIT_INT_CLEAR);
++
++ queue_work(dev->workqueue, &dev->work);
++
++ return IRQ_HANDLED;
++}
++
++/*!
++ * @brief vpu jpu interrupt handler
++ */
++#ifdef MXC_VPU_HAS_JPU
++static irqreturn_t vpu_jpu_irq_handler(int irq, void *dev_id)
++{
++ struct vpu_priv *dev = dev_id;
++ unsigned long reg;
++
++ reg = READ_REG(MJPEG_PIC_STATUS_REG);
++ if (reg & 0x3)
++ codec_done = 1;
++
++ queue_work(dev->workqueue, &dev->work);
++
++ return IRQ_HANDLED;
++}
++#endif
++
++/*!
++ * @brief check phy memory prepare to pass to vpu is valid or not, we
++ * already address some issue that if pass a wrong address to vpu
++ * (like virtual address), system will hang.
++ *
++ * @return true return is a valid phy memory address, false return not.
++ */
++bool vpu_is_valid_phy_memory(u32 paddr)
++{
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 5, 0)
++ if (paddr > top_address_DRAM)
++ return false;
++#endif
++
++ return true;
++}
++
++/*!
++ * @brief open function for vpu file operation
++ *
++ * @return 0 on success or negative error code on error
++ */
++static int vpu_open(struct inode *inode, struct file *filp)
++{
++
++ mutex_lock(&vpu_data.lock);
++
++ if (open_count++ == 0) {
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)
++ pm_runtime_get_sync(vpu_dev);
++#endif
++ vpu_power_up(true);
++
++#ifdef CONFIG_SOC_IMX6Q
++ clk_prepare(vpu_clk);
++ clk_enable(vpu_clk);
++ if (READ_REG(BIT_CUR_PC))
++ dev_dbg(vpu_dev, "Not power off before vpu open!\n");
++ clk_disable(vpu_clk);
++ clk_unprepare(vpu_clk);
++#endif
++ }
++
++ filp->private_data = (void *)(&vpu_data);
++ mutex_unlock(&vpu_data.lock);
++ return 0;
++}
++
++/*!
++ * @brief IO ctrl function for vpu file operation
++ * @param cmd IO ctrl command
++ * @return 0 on success or negative error code on error
++ */
++static long vpu_ioctl(struct file *filp, u_int cmd,
++ u_long arg)
++{
++ int ret = 0;
++
++ switch (cmd) {
++ case VPU_IOC_PHYMEM_ALLOC:
++ {
++ struct memalloc_record *rec;
++
++ rec = kzalloc(sizeof(*rec), GFP_KERNEL);
++ if (!rec)
++ return -ENOMEM;
++
++ ret = copy_from_user(&(rec->mem),
++ (struct vpu_mem_desc *)arg,
++ sizeof(struct vpu_mem_desc));
++ if (ret) {
++ kfree(rec);
++ return -EFAULT;
++ }
++
++ dev_dbg(vpu_dev, "[ALLOC] mem alloc size = 0x%x\n",
++ rec->mem.size);
++
++ ret = vpu_alloc_dma_buffer(&(rec->mem));
++ if (ret == -1) {
++ kfree(rec);
++ dev_err(vpu_dev,
++ "Physical memory allocation error!\n");
++ break;
++ }
++ ret = copy_to_user((void __user *)arg, &(rec->mem),
++ sizeof(struct vpu_mem_desc));
++ if (ret) {
++ kfree(rec);
++ ret = -EFAULT;
++ break;
++ }
++
++ mutex_lock(&vpu_data.lock);
++ list_add(&rec->list, &head);
++ mutex_unlock(&vpu_data.lock);
++
++ break;
++ }
++ case VPU_IOC_PHYMEM_FREE:
++ {
++ struct memalloc_record *rec, *n;
++ struct vpu_mem_desc vpu_mem;
++
++ ret = copy_from_user(&vpu_mem,
++ (struct vpu_mem_desc *)arg,
++ sizeof(struct vpu_mem_desc));
++ if (ret)
++ return -EACCES;
++
++ dev_dbg(vpu_dev, "[FREE] mem freed cpu_addr = 0x%x\n",
++ vpu_mem.cpu_addr);
++ if ((void *)vpu_mem.cpu_addr != NULL)
++ vpu_free_dma_buffer(&vpu_mem);
++
++ mutex_lock(&vpu_data.lock);
++ list_for_each_entry_safe(rec, n, &head, list) {
++ if (rec->mem.cpu_addr == vpu_mem.cpu_addr) {
++ /* delete from list */
++ list_del(&rec->list);
++ kfree(rec);
++ break;
++ }
++ }
++ mutex_unlock(&vpu_data.lock);
++
++ break;
++ }
++ case VPU_IOC_WAIT4INT:
++ {
++ u_long timeout = (u_long) arg;
++ if (!wait_event_interruptible_timeout
++ (vpu_queue, irq_status != 0,
++ msecs_to_jiffies(timeout))) {
++ dev_warn(vpu_dev, "VPU blocking: timeout.\n");
++ ret = -ETIME;
++ } else if (signal_pending(current)) {
++ dev_warn(vpu_dev, "VPU interrupt received.\n");
++ ret = -ERESTARTSYS;
++ } else
++ irq_status = 0;
++ break;
++ }
++ case VPU_IOC_IRAM_SETTING:
++ {
++ ret = copy_to_user((void __user *)arg, &iram,
++ sizeof(struct iram_setting));
++ if (ret)
++ ret = -EFAULT;
++
++ break;
++ }
++ case VPU_IOC_CLKGATE_SETTING:
++ {
++ u32 clkgate_en;
++
++ if (get_user(clkgate_en, (u32 __user *) arg))
++ return -EFAULT;
++
++ if (clkgate_en) {
++ clk_prepare(vpu_clk);
++ clk_enable(vpu_clk);
++ atomic_inc(&clk_cnt_from_ioc);
++ } else {
++ clk_disable(vpu_clk);
++ clk_unprepare(vpu_clk);
++ atomic_dec(&clk_cnt_from_ioc);
++ }
++
++ break;
++ }
++ case VPU_IOC_GET_SHARE_MEM:
++ {
++ mutex_lock(&vpu_data.lock);
++ if (share_mem.cpu_addr != 0) {
++ ret = copy_to_user((void __user *)arg,
++ &share_mem,
++ sizeof(struct vpu_mem_desc));
++ mutex_unlock(&vpu_data.lock);
++ break;
++ } else {
++ if (copy_from_user(&share_mem,
++ (struct vpu_mem_desc *)arg,
++ sizeof(struct vpu_mem_desc))) {
++ mutex_unlock(&vpu_data.lock);
++ return -EFAULT;
++ }
++ if (vpu_alloc_dma_buffer(&share_mem) == -1)
++ ret = -EFAULT;
++ else {
++ if (copy_to_user((void __user *)arg,
++ &share_mem,
++ sizeof(struct
++ vpu_mem_desc)))
++ ret = -EFAULT;
++ }
++ }
++ mutex_unlock(&vpu_data.lock);
++ break;
++ }
++ case VPU_IOC_REQ_VSHARE_MEM:
++ {
++ mutex_lock(&vpu_data.lock);
++ if (vshare_mem.cpu_addr != 0) {
++ ret = copy_to_user((void __user *)arg,
++ &vshare_mem,
++ sizeof(struct vpu_mem_desc));
++ mutex_unlock(&vpu_data.lock);
++ break;
++ } else {
++ if (copy_from_user(&vshare_mem,
++ (struct vpu_mem_desc *)arg,
++ sizeof(struct
++ vpu_mem_desc))) {
++ mutex_unlock(&vpu_data.lock);
++ return -EFAULT;
++ }
++ /* vmalloc shared memory if not allocated */
++ if (!vshare_mem.cpu_addr)
++ vshare_mem.cpu_addr =
++ (unsigned long)
++ vmalloc_user(vshare_mem.size);
++ if (copy_to_user
++ ((void __user *)arg, &vshare_mem,
++ sizeof(struct vpu_mem_desc)))
++ ret = -EFAULT;
++ }
++ mutex_unlock(&vpu_data.lock);
++ break;
++ }
++ case VPU_IOC_GET_WORK_ADDR:
++ {
++ if (bitwork_mem.cpu_addr != 0) {
++ ret =
++ copy_to_user((void __user *)arg,
++ &bitwork_mem,
++ sizeof(struct vpu_mem_desc));
++ break;
++ } else {
++ if (copy_from_user(&bitwork_mem,
++ (struct vpu_mem_desc *)arg,
++ sizeof(struct vpu_mem_desc)))
++ return -EFAULT;
++
++ if (vpu_alloc_dma_buffer(&bitwork_mem) == -1)
++ ret = -EFAULT;
++ else if (copy_to_user((void __user *)arg,
++ &bitwork_mem,
++ sizeof(struct
++ vpu_mem_desc)))
++ ret = -EFAULT;
++ }
++ break;
++ }
++ /*
++ * The following two ioctl is used when user allocates working buffer
++ * and register it to vpu driver.
++ */
++ case VPU_IOC_QUERY_BITWORK_MEM:
++ {
++ if (copy_to_user((void __user *)arg,
++ &bitwork_mem,
++ sizeof(struct vpu_mem_desc)))
++ ret = -EFAULT;
++ break;
++ }
++ case VPU_IOC_SET_BITWORK_MEM:
++ {
++ if (copy_from_user(&bitwork_mem,
++ (struct vpu_mem_desc *)arg,
++ sizeof(struct vpu_mem_desc)))
++ ret = -EFAULT;
++ break;
++ }
++ case VPU_IOC_SYS_SW_RESET:
++ {
++ vpu_reset();
++ break;
++ }
++ case VPU_IOC_REG_DUMP:
++ break;
++ case VPU_IOC_PHYMEM_DUMP:
++ break;
++ case VPU_IOC_PHYMEM_CHECK:
++ {
++ struct vpu_mem_desc check_memory;
++ ret = copy_from_user(&check_memory,
++ (void __user *)arg,
++ sizeof(struct vpu_mem_desc));
++ if (ret != 0) {
++ dev_err(vpu_dev, "copy from user failure:%d\n", ret);
++ ret = -EFAULT;
++ break;
++ }
++ ret = vpu_is_valid_phy_memory((u32)check_memory.phy_addr);
++
++ dev_dbg(vpu_dev, "vpu: memory phy:0x%x %s phy memory\n",
++ check_memory.phy_addr, (ret ? "is" : "isn't"));
++ /* borrow .size to pass back the result. */
++ check_memory.size = ret;
++ ret = copy_to_user((void __user *)arg, &check_memory,
++ sizeof(struct vpu_mem_desc));
++ if (ret) {
++ ret = -EFAULT;
++ break;
++ }
++ break;
++ }
++ case VPU_IOC_LOCK_DEV:
++ {
++ u32 lock_en;
++
++ if (get_user(lock_en, (u32 __user *) arg))
++ return -EFAULT;
++
++ if (lock_en)
++ mutex_lock(&vpu_data.lock);
++ else
++ mutex_unlock(&vpu_data.lock);
++
++ break;
++ }
++ default:
++ {
++ dev_err(vpu_dev, "No such IOCTL, cmd is %d\n", cmd);
++ ret = -EINVAL;
++ break;
++ }
++ }
++ return ret;
++}
++
++/*!
++ * @brief Release function for vpu file operation
++ * @return 0 on success or negative error code on error
++ */
++static int vpu_release(struct inode *inode, struct file *filp)
++{
++ int i;
++ unsigned long timeout;
++
++ mutex_lock(&vpu_data.lock);
++
++ if (open_count > 0 && !(--open_count)) {
++
++ /* Wait for vpu go to idle state */
++ clk_prepare(vpu_clk);
++ clk_enable(vpu_clk);
++ if (READ_REG(BIT_CUR_PC)) {
++
++ timeout = jiffies + HZ;
++ while (READ_REG(BIT_BUSY_FLAG)) {
++ msleep(1);
++ if (time_after(jiffies, timeout)) {
++ dev_warn(vpu_dev, "VPU timeout during release\n");
++ break;
++ }
++ }
++ clk_disable(vpu_clk);
++ clk_unprepare(vpu_clk);
++
++ /* Clean up interrupt */
++ cancel_work_sync(&vpu_data.work);
++ flush_workqueue(vpu_data.workqueue);
++ irq_status = 0;
++
++ clk_prepare(vpu_clk);
++ clk_enable(vpu_clk);
++ if (READ_REG(BIT_BUSY_FLAG)) {
++
++ if (cpu_is_mx51() || cpu_is_mx53()) {
++ dev_err(vpu_dev,
++ "fatal error: can't gate/power off when VPU is busy\n");
++ clk_disable(vpu_clk);
++ clk_unprepare(vpu_clk);
++ mutex_unlock(&vpu_data.lock);
++ return -EFAULT;
++ }
++
++#ifdef CONFIG_SOC_IMX6Q
++ if (cpu_is_mx6dl() || cpu_is_mx6q()) {
++ WRITE_REG(0x11, 0x10F0);
++ timeout = jiffies + HZ;
++ while (READ_REG(0x10F4) != 0x77) {
++ msleep(1);
++ if (time_after(jiffies, timeout))
++ break;
++ }
++
++ if (READ_REG(0x10F4) != 0x77) {
++ dev_err(vpu_dev,
++ "fatal error: can't gate/power off when VPU is busy\n");
++ WRITE_REG(0x0, 0x10F0);
++ clk_disable(vpu_clk);
++ clk_unprepare(vpu_clk);
++ mutex_unlock(&vpu_data.lock);
++ return -EFAULT;
++ } else
++ vpu_reset();
++ }
++#endif
++ }
++ }
++ clk_disable(vpu_clk);
++ clk_unprepare(vpu_clk);
++
++ vpu_free_buffers();
++
++ /* Free shared memory when vpu device is idle */
++ vpu_free_dma_buffer(&share_mem);
++ share_mem.cpu_addr = 0;
++ vfree((void *)vshare_mem.cpu_addr);
++ vshare_mem.cpu_addr = 0;
++
++ vpu_clk_usercount = atomic_read(&clk_cnt_from_ioc);
++ for (i = 0; i < vpu_clk_usercount; i++) {
++ clk_disable(vpu_clk);
++ clk_unprepare(vpu_clk);
++ atomic_dec(&clk_cnt_from_ioc);
++ }
++
++ vpu_power_up(false);
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)
++ pm_runtime_put_sync_suspend(vpu_dev);
++#endif
++
++ }
++ mutex_unlock(&vpu_data.lock);
++
++ return 0;
++}
++
++/*!
++ * @brief fasync function for vpu file operation
++ * @return 0 on success or negative error code on error
++ */
++static int vpu_fasync(int fd, struct file *filp, int mode)
++{
++ struct vpu_priv *dev = (struct vpu_priv *)filp->private_data;
++ return fasync_helper(fd, filp, mode, &dev->async_queue);
++}
++
++/*!
++ * @brief memory map function of harware registers for vpu file operation
++ * @return 0 on success or negative error code on error
++ */
++static int vpu_map_hwregs(struct file *fp, struct vm_area_struct *vm)
++{
++ unsigned long pfn;
++
++ vm->vm_flags |= VM_IO | VM_RESERVED;
++ /*
++ * Since vpu registers have been mapped with ioremap() at probe
++ * which L_PTE_XN is 1, and the same physical address must be
++ * mapped multiple times with same type, so set L_PTE_XN to 1 here.
++ * Otherwise, there may be unexpected result in video codec.
++ */
++ vm->vm_page_prot = pgprot_noncachedxn(vm->vm_page_prot);
++ pfn = phy_vpu_base_addr >> PAGE_SHIFT;
++ dev_dbg(vpu_dev, "size=0x%x, page no.=0x%x\n",
++ (int)(vm->vm_end - vm->vm_start), (int)pfn);
++ return remap_pfn_range(vm, vm->vm_start, pfn, vm->vm_end - vm->vm_start,
++ vm->vm_page_prot) ? -EAGAIN : 0;
++}
++
++/*!
++ * @brief memory map function of memory for vpu file operation
++ * @return 0 on success or negative error code on error
++ */
++static int vpu_map_dma_mem(struct file *fp, struct vm_area_struct *vm)
++{
++ int request_size;
++ request_size = vm->vm_end - vm->vm_start;
++
++ dev_dbg(vpu_dev, "start=0x%x, pgoff=0x%x, size=0x%x\n",
++ (unsigned int)(vm->vm_start), (unsigned int)(vm->vm_pgoff),
++ request_size);
++
++ vm->vm_flags |= VM_IO | VM_RESERVED;
++ vm->vm_page_prot = pgprot_writecombine(vm->vm_page_prot);
++
++ return remap_pfn_range(vm, vm->vm_start, vm->vm_pgoff,
++ request_size, vm->vm_page_prot) ? -EAGAIN : 0;
++
++}
++
++/* !
++ * @brief memory map function of vmalloced share memory
++ * @return 0 on success or negative error code on error
++ */
++static int vpu_map_vshare_mem(struct file *fp, struct vm_area_struct *vm)
++{
++ int ret = -EINVAL;
++
++ ret = remap_vmalloc_range(vm, (void *)(vm->vm_pgoff << PAGE_SHIFT), 0);
++ vm->vm_flags |= VM_IO;
++
++ return ret;
++}
++/*!
++ * @brief memory map interface for vpu file operation
++ * @return 0 on success or negative error code on error
++ */
++static int vpu_mmap(struct file *fp, struct vm_area_struct *vm)
++{
++ unsigned long offset;
++
++ offset = vshare_mem.cpu_addr >> PAGE_SHIFT;
++
++ if (vm->vm_pgoff && (vm->vm_pgoff == offset))
++ return vpu_map_vshare_mem(fp, vm);
++ else if (vm->vm_pgoff)
++ return vpu_map_dma_mem(fp, vm);
++ else
++ return vpu_map_hwregs(fp, vm);
++}
++
++const struct file_operations vpu_fops = {
++ .owner = THIS_MODULE,
++ .open = vpu_open,
++ .unlocked_ioctl = vpu_ioctl,
++ .release = vpu_release,
++ .fasync = vpu_fasync,
++ .mmap = vpu_mmap,
++};
++
++/*!
++ * This function is called by the driver framework to initialize the vpu device.
++ * @param dev The device structure for the vpu passed in by the framework.
++ * @return 0 on success or negative error code on error
++ */
++static int vpu_dev_probe(struct platform_device *pdev)
++{
++ int err = 0;
++ struct device *temp_class;
++ struct resource *res;
++ unsigned long addr = 0;
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)
++ struct device_node *np = pdev->dev.of_node;
++ u32 iramsize;
++
++ err = of_property_read_u32(np, "iramsize", (u32 *)&iramsize);
++ if (!err && iramsize)
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0)
++ {
++ iram_pool = of_get_named_gen_pool(np, "iram", 0);
++ if (!iram_pool) {
++ dev_err(&pdev->dev, "iram pool not available\n");
++ return -ENOMEM;
++ }
++
++ iram_base = gen_pool_alloc(iram_pool, iramsize);
++ if (!iram_base) {
++ dev_err(&pdev->dev, "unable to alloc iram\n");
++ return -ENOMEM;
++ }
++
++ addr = gen_pool_virt_to_phys(iram_pool, iram_base);
++ }
++#else
++ iram_alloc(iramsize, &addr);
++#endif
++ if (addr == 0)
++ iram.start = iram.end = 0;
++ else {
++ iram.start = addr;
++ iram.end = addr + iramsize - 1;
++ }
++#else
++
++ vpu_plat = pdev->dev.platform_data;
++
++ if (vpu_plat && vpu_plat->iram_enable && vpu_plat->iram_size)
++ iram_alloc(vpu_plat->iram_size, &addr);
++ if (addr == 0)
++ iram.start = iram.end = 0;
++ else {
++ iram.start = addr;
++ iram.end = addr + vpu_plat->iram_size - 1;
++ }
++#endif
++
++ vpu_dev = &pdev->dev;
++
++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "vpu_regs");
++ if (!res) {
++ dev_err(vpu_dev, "vpu: unable to get vpu base addr\n");
++ return -ENODEV;
++ }
++ phy_vpu_base_addr = res->start;
++ vpu_base = ioremap(res->start, res->end - res->start);
++
++ vpu_major = register_chrdev(vpu_major, "mxc_vpu", &vpu_fops);
++ if (vpu_major < 0) {
++ dev_err(vpu_dev, "vpu: unable to get a major for VPU\n");
++ err = -EBUSY;
++ goto error;
++ }
++
++ vpu_class = class_create(THIS_MODULE, "mxc_vpu");
++ if (IS_ERR(vpu_class)) {
++ err = PTR_ERR(vpu_class);
++ goto err_out_chrdev;
++ }
++
++ temp_class = device_create(vpu_class, NULL, MKDEV(vpu_major, 0),
++ NULL, "mxc_vpu");
++ if (IS_ERR(temp_class)) {
++ err = PTR_ERR(temp_class);
++ goto err_out_class;
++ }
++
++ vpu_clk = clk_get(&pdev->dev, "per");
++ if (IS_ERR(vpu_clk)) {
++ err = -ENOENT;
++ goto err_out_class;
++ }
++
++ vpu_ipi_irq = platform_get_irq_byname(pdev, "bit");
++ if (vpu_ipi_irq < 0) {
++ dev_err(vpu_dev, "vpu: unable to get vpu interrupt\n");
++ err = -ENXIO;
++ goto err_out_class;
++ }
++ err = request_irq(vpu_ipi_irq, vpu_ipi_irq_handler, 0, "VPU_CODEC_IRQ",
++ (void *)(&vpu_data));
++ if (err)
++ goto err_out_class;
++ if (vpu_power_get(true)) {
++ if (!(cpu_is_mx51() || cpu_is_mx53())) {
++ dev_err(vpu_dev, "failed to get vpu power\n");
++ goto err_out_class;
++ } else {
++ /* regulator_get will return error on MX5x,
++ * just igore it everywhere*/
++ dev_warn(vpu_dev, "failed to get vpu power\n");
++ }
++ }
++
++#ifdef MXC_VPU_HAS_JPU
++ vpu_jpu_irq = platform_get_irq_byname(pdev, "jpeg");
++ if (vpu_jpu_irq < 0) {
++ dev_err(vpu_dev, "vpu: unable to get vpu jpu interrupt\n");
++ err = -ENXIO;
++ free_irq(vpu_ipi_irq, &vpu_data);
++ goto err_out_class;
++ }
++ err = request_irq(vpu_jpu_irq, vpu_jpu_irq_handler, IRQF_TRIGGER_RISING,
++ "VPU_JPG_IRQ", (void *)(&vpu_data));
++ if (err) {
++ free_irq(vpu_ipi_irq, &vpu_data);
++ goto err_out_class;
++ }
++#endif
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)
++ pm_runtime_enable(&pdev->dev);
++#endif
++
++ vpu_data.workqueue = create_workqueue("vpu_wq");
++ INIT_WORK(&vpu_data.work, vpu_worker_callback);
++ mutex_init(&vpu_data.lock);
++ dev_info(vpu_dev, "VPU initialized\n");
++ goto out;
++
++err_out_class:
++ device_destroy(vpu_class, MKDEV(vpu_major, 0));
++ class_destroy(vpu_class);
++err_out_chrdev:
++ unregister_chrdev(vpu_major, "mxc_vpu");
++error:
++ iounmap(vpu_base);
++out:
++ return err;
++}
++
++static int vpu_dev_remove(struct platform_device *pdev)
++{
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)
++ pm_runtime_disable(&pdev->dev);
++#endif
++ free_irq(vpu_ipi_irq, &vpu_data);
++#ifdef MXC_VPU_HAS_JPU
++ free_irq(vpu_jpu_irq, &vpu_data);
++#endif
++ cancel_work_sync(&vpu_data.work);
++ flush_workqueue(vpu_data.workqueue);
++ destroy_workqueue(vpu_data.workqueue);
++
++ iounmap(vpu_base);
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)
++ if (iram.start)
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0)
++ gen_pool_free(iram_pool, iram_base, iram.end-iram.start+1);
++#else
++ iram_free(iram.start, iram.end-iram.start+1);
++#endif
++#else
++ if (vpu_plat && vpu_plat->iram_enable && vpu_plat->iram_size)
++ iram_free(iram.start, vpu_plat->iram_size);
++#endif
++
++ vpu_power_get(false);
++ return 0;
++}
++
++#ifdef CONFIG_PM
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)
++static int vpu_suspend(struct device *dev)
++#else
++static int vpu_suspend(struct platform_device *pdev, pm_message_t state)
++#endif
++{
++ int i;
++ unsigned long timeout;
++
++ mutex_lock(&vpu_data.lock);
++ if (open_count == 0) {
++ /* VPU is released (all instances are freed),
++ * clock is already off, context is no longer needed,
++ * power is already off on MX6,
++ * gate power on MX51 */
++ if (cpu_is_mx51()) {
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 5, 0)
++ if (vpu_plat->pg)
++ vpu_plat->pg(1);
++#endif
++ }
++ } else {
++ /* Wait for vpu go to idle state, suspect vpu cannot be changed
++ to idle state after about 1 sec */
++ timeout = jiffies + HZ;
++ clk_prepare(vpu_clk);
++ clk_enable(vpu_clk);
++ while (READ_REG(BIT_BUSY_FLAG)) {
++ msleep(1);
++ if (time_after(jiffies, timeout)) {
++ clk_disable(vpu_clk);
++ clk_unprepare(vpu_clk);
++ mutex_unlock(&vpu_data.lock);
++ return -EAGAIN;
++ }
++ }
++ clk_disable(vpu_clk);
++ clk_unprepare(vpu_clk);
++
++ /* Make sure clock is disabled before suspend */
++ vpu_clk_usercount = atomic_read(&clk_cnt_from_ioc);
++ for (i = 0; i < vpu_clk_usercount; i++) {
++ clk_disable(vpu_clk);
++ clk_unprepare(vpu_clk);
++ }
++
++ if (cpu_is_mx53()) {
++ mutex_unlock(&vpu_data.lock);
++ return 0;
++ }
++
++ if (bitwork_mem.cpu_addr != 0) {
++ clk_prepare(vpu_clk);
++ clk_enable(vpu_clk);
++ /* Save 64 registers from BIT_CODE_BUF_ADDR */
++ for (i = 0; i < 64; i++)
++ regBk[i] = READ_REG(BIT_CODE_BUF_ADDR + (i * 4));
++ pc_before_suspend = READ_REG(BIT_CUR_PC);
++ clk_disable(vpu_clk);
++ clk_unprepare(vpu_clk);
++ }
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 5, 0)
++ if (vpu_plat->pg)
++ vpu_plat->pg(1);
++#endif
++
++ /* If VPU is working before suspend, disable
++ * regulator to make usecount right. */
++ vpu_power_up(false);
++ }
++
++ mutex_unlock(&vpu_data.lock);
++ return 0;
++}
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)
++static int vpu_resume(struct device *dev)
++#else
++static int vpu_resume(struct platform_device *pdev)
++#endif
++{
++ int i;
++
++ mutex_lock(&vpu_data.lock);
++ if (open_count == 0) {
++ /* VPU is released (all instances are freed),
++ * clock should be kept off, context is no longer needed,
++ * power should be kept off on MX6,
++ * disable power gating on MX51 */
++ if (cpu_is_mx51()) {
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 5, 0)
++ if (vpu_plat->pg)
++ vpu_plat->pg(0);
++#endif
++ }
++ } else {
++ if (cpu_is_mx53())
++ goto recover_clk;
++
++ /* If VPU is working before suspend, enable
++ * regulator to make usecount right. */
++ vpu_power_up(true);
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 5, 0)
++ if (vpu_plat->pg)
++ vpu_plat->pg(0);
++#endif
++
++ if (bitwork_mem.cpu_addr != 0) {
++ u32 *p = (u32 *) bitwork_mem.cpu_addr;
++ u32 data, pc;
++ u16 data_hi;
++ u16 data_lo;
++
++ clk_prepare(vpu_clk);
++ clk_enable(vpu_clk);
++
++ pc = READ_REG(BIT_CUR_PC);
++ if (pc) {
++ dev_warn(vpu_dev, "Not power off after suspend (PC=0x%x)\n", pc);
++ clk_disable(vpu_clk);
++ clk_unprepare(vpu_clk);
++ goto recover_clk;
++ }
++
++ /* Restore registers */
++ for (i = 0; i < 64; i++)
++ WRITE_REG(regBk[i], BIT_CODE_BUF_ADDR + (i * 4));
++
++ WRITE_REG(0x0, BIT_RESET_CTRL);
++ WRITE_REG(0x0, BIT_CODE_RUN);
++ /* MX6 RTL has a bug not to init MBC_SET_SUBBLK_EN on reset */
++#ifdef CONFIG_SOC_IMX6Q
++ WRITE_REG(0x0, MBC_SET_SUBBLK_EN);
++#endif
++
++ /*
++ * Re-load boot code, from the codebuffer in external RAM.
++ * Thankfully, we only need 4096 bytes, same for all platforms.
++ */
++ for (i = 0; i < 2048; i += 4) {
++ data = p[(i / 2) + 1];
++ data_hi = (data >> 16) & 0xFFFF;
++ data_lo = data & 0xFFFF;
++ WRITE_REG((i << 16) | data_hi, BIT_CODE_DOWN);
++ WRITE_REG(((i + 1) << 16) | data_lo,
++ BIT_CODE_DOWN);
++
++ data = p[i / 2];
++ data_hi = (data >> 16) & 0xFFFF;
++ data_lo = data & 0xFFFF;
++ WRITE_REG(((i + 2) << 16) | data_hi,
++ BIT_CODE_DOWN);
++ WRITE_REG(((i + 3) << 16) | data_lo,
++ BIT_CODE_DOWN);
++ }
++
++ if (pc_before_suspend) {
++ WRITE_REG(0x1, BIT_BUSY_FLAG);
++ WRITE_REG(0x1, BIT_CODE_RUN);
++ while (READ_REG(BIT_BUSY_FLAG))
++ ;
++ } else {
++ dev_warn(vpu_dev, "PC=0 before suspend\n");
++ }
++ clk_disable(vpu_clk);
++ clk_unprepare(vpu_clk);
++ }
++
++recover_clk:
++ /* Recover vpu clock */
++ for (i = 0; i < vpu_clk_usercount; i++) {
++ clk_prepare(vpu_clk);
++ clk_enable(vpu_clk);
++ }
++ }
++
++ mutex_unlock(&vpu_data.lock);
++ return 0;
++}
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)
++static int vpu_runtime_suspend(struct device *dev)
++{
++ dev_dbg(dev, "ipu busfreq high release.\n");
++ release_bus_freq(BUS_FREQ_HIGH);
++ return 0;
++}
++
++static int vpu_runtime_resume(struct device *dev)
++{
++ dev_dbg(dev, "ipu busfreq high request.\n");
++ request_bus_freq(BUS_FREQ_HIGH);
++ return 0;
++}
++
++static const struct dev_pm_ops vpu_pm_ops = {
++ SET_RUNTIME_PM_OPS(vpu_runtime_suspend, vpu_runtime_resume, NULL)
++ SET_SYSTEM_SLEEP_PM_OPS(vpu_suspend, vpu_resume)
++};
++#endif
++
++#else
++#define vpu_suspend NULL
++#define vpu_resume NULL
++#endif /* !CONFIG_PM */
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)
++static const struct of_device_id vpu_of_match[] = {
++ { .compatible = "fsl,imx6-vpu", },
++ { .compatible = "fsl,imx6q-vpu", },
++ {/* sentinel */}
++};
++MODULE_DEVICE_TABLE(of, vpu_of_match);
++#endif
++
++/*! Driver definition
++ *
++ */
++static struct platform_driver mxcvpu_driver = {
++ .driver = {
++ .name = "mxc_vpu",
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)
++ .of_match_table = vpu_of_match,
++#ifdef CONFIG_PM
++ .pm = &vpu_pm_ops,
++#endif
++#endif
++ },
++ .probe = vpu_dev_probe,
++ .remove = vpu_dev_remove,
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 5, 0)
++ .suspend = vpu_suspend,
++ .resume = vpu_resume,
++#endif
++};
++
++static int __init vpu_init(void)
++{
++ int ret = platform_driver_register(&mxcvpu_driver);
++
++ init_waitqueue_head(&vpu_queue);
++
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 5, 0)
++ memblock_analyze();
++ top_address_DRAM = memblock_end_of_DRAM_with_reserved();
++#endif
++
++ return ret;
++}
++
++static void __exit vpu_exit(void)
++{
++ if (vpu_major > 0) {
++ device_destroy(vpu_class, MKDEV(vpu_major, 0));
++ class_destroy(vpu_class);
++ unregister_chrdev(vpu_major, "mxc_vpu");
++ vpu_major = 0;
++ }
++
++ vpu_free_dma_buffer(&bitwork_mem);
++ vpu_free_dma_buffer(&pic_para_mem);
++ vpu_free_dma_buffer(&user_data_mem);
++
++ /* reset VPU state */
++ vpu_power_up(true);
++ clk_prepare(vpu_clk);
++ clk_enable(vpu_clk);
++ vpu_reset();
++ clk_disable(vpu_clk);
++ clk_unprepare(vpu_clk);
++ vpu_power_up(false);
++
++ clk_put(vpu_clk);
++
++ platform_driver_unregister(&mxcvpu_driver);
++ return;
++}
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("Linux VPU driver for Freescale i.MX/MXC");
++MODULE_LICENSE("GPL");
++
++module_init(vpu_init);
++module_exit(vpu_exit);
+diff -Nur linux-4.1.3/drivers/net/wireless/brcm80211/brcmfmac/bcmsdh.c linux-xbian-imx6/drivers/net/wireless/brcm80211/brcmfmac/bcmsdh.c
+--- linux-4.1.3/drivers/net/wireless/brcm80211/brcmfmac/bcmsdh.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/drivers/net/wireless/brcm80211/brcmfmac/bcmsdh.c 2015-07-27 23:13:06.848547454 +0200
+@@ -1011,6 +1011,14 @@
+ return 0;
+ }
+
++static void brcmf_sdiod_host_fixup(struct mmc_host *host)
++{
++ /* runtime-pm powers off the device */
++ pm_runtime_forbid(host->parent);
++ /* avoid removal detection upon resume */
++ host->caps |= MMC_CAP_NONREMOVABLE;
++}
++
+ static int brcmf_sdiod_probe(struct brcmf_sdio_dev *sdiodev)
+ {
+ struct sdio_func *func;
+@@ -1076,7 +1084,7 @@
+ ret = -ENODEV;
+ goto out;
+ }
+- pm_runtime_forbid(host->parent);
++ brcmf_sdiod_host_fixup(host);
+ out:
+ if (ret)
+ brcmf_sdiod_remove(sdiodev);
+@@ -1246,15 +1254,15 @@
+ brcmf_sdiod_freezer_on(sdiodev);
+ brcmf_sdio_wd_timer(sdiodev->bus, 0);
+
++ sdio_flags = MMC_PM_KEEP_POWER;
+ if (sdiodev->wowl_enabled) {
+- sdio_flags = MMC_PM_KEEP_POWER;
+ if (sdiodev->pdata->oob_irq_supported)
+ enable_irq_wake(sdiodev->pdata->oob_irq_nr);
+ else
+- sdio_flags = MMC_PM_WAKE_SDIO_IRQ;
+- if (sdio_set_host_pm_flags(sdiodev->func[1], sdio_flags))
+- brcmf_err("Failed to set pm_flags %x\n", sdio_flags);
++ sdio_flags |= MMC_PM_WAKE_SDIO_IRQ;
+ }
++ if (sdio_set_host_pm_flags(sdiodev->func[1], sdio_flags))
++ brcmf_err("Failed to set pm_flags %x\n", sdio_flags);
+ return 0;
+ }
+
+diff -Nur linux-4.1.3/drivers/net/wireless/brcm80211/brcmfmac/cfg80211.c linux-xbian-imx6/drivers/net/wireless/brcm80211/brcmfmac/cfg80211.c
+--- linux-4.1.3/drivers/net/wireless/brcm80211/brcmfmac/cfg80211.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/drivers/net/wireless/brcm80211/brcmfmac/cfg80211.c 2015-07-27 23:13:06.848547454 +0200
+@@ -129,13 +129,47 @@
+ RATETAB_ENT(BRCM_RATE_54M, 0),
+ };
+
+-#define wl_a_rates (__wl_rates + 4)
+-#define wl_a_rates_size 8
+ #define wl_g_rates (__wl_rates + 0)
+-#define wl_g_rates_size 12
++#define wl_g_rates_size ARRAY_SIZE(__wl_rates)
++#define wl_a_rates (__wl_rates + 4)
++#define wl_a_rates_size (wl_g_rates_size - 4)
++
++#define CHAN2G(_channel, _freq) { \
++ .band = IEEE80211_BAND_2GHZ, \
++ .center_freq = (_freq), \
++ .hw_value = (_channel), \
++ .flags = IEEE80211_CHAN_DISABLED, \
++ .max_antenna_gain = 0, \
++ .max_power = 30, \
++}
++
++#define CHAN5G(_channel) { \
++ .band = IEEE80211_BAND_5GHZ, \
++ .center_freq = 5000 + (5 * (_channel)), \
++ .hw_value = (_channel), \
++ .flags = IEEE80211_CHAN_DISABLED, \
++ .max_antenna_gain = 0, \
++ .max_power = 30, \
++}
++
++static struct ieee80211_channel __wl_2ghz_channels[] = {
++ CHAN2G(1, 2412), CHAN2G(2, 2417), CHAN2G(3, 2422), CHAN2G(4, 2427),
++ CHAN2G(5, 2432), CHAN2G(6, 2437), CHAN2G(7, 2442), CHAN2G(8, 2447),
++ CHAN2G(9, 2452), CHAN2G(10, 2457), CHAN2G(11, 2462), CHAN2G(12, 2467),
++ CHAN2G(13, 2472), CHAN2G(14, 2484)
++};
++
++static struct ieee80211_channel __wl_5ghz_channels[] = {
++ CHAN5G(34), CHAN5G(36), CHAN5G(38), CHAN5G(40), CHAN5G(42),
++ CHAN5G(44), CHAN5G(46), CHAN5G(48), CHAN5G(52), CHAN5G(56),
++ CHAN5G(60), CHAN5G(64), CHAN5G(100), CHAN5G(104), CHAN5G(108),
++ CHAN5G(112), CHAN5G(116), CHAN5G(120), CHAN5G(124), CHAN5G(128),
++ CHAN5G(132), CHAN5G(136), CHAN5G(140), CHAN5G(144), CHAN5G(149),
++ CHAN5G(153), CHAN5G(157), CHAN5G(161), CHAN5G(165)
++};
+
+ /* Band templates duplicated per wiphy. The channel info
+- * is filled in after querying the device.
++ * above is added to the band during setup.
+ */
+ static const struct ieee80211_supported_band __wl_band_2ghz = {
+ .band = IEEE80211_BAND_2GHZ,
+@@ -143,7 +177,7 @@
+ .n_bitrates = wl_g_rates_size,
+ };
+
+-static const struct ieee80211_supported_band __wl_band_5ghz_a = {
++static const struct ieee80211_supported_band __wl_band_5ghz = {
+ .band = IEEE80211_BAND_5GHZ,
+ .bitrates = wl_a_rates,
+ .n_bitrates = wl_a_rates_size,
+@@ -5253,40 +5287,6 @@
+ return err;
+ }
+
+-/* Filter the list of channels received from firmware counting only
+- * the 20MHz channels. The wiphy band data only needs those which get
+- * flagged to indicate if they can take part in higher bandwidth.
+- */
+-static void brcmf_count_20mhz_channels(struct brcmf_cfg80211_info *cfg,
+- struct brcmf_chanspec_list *chlist,
+- u32 chcnt[])
+-{
+- u32 total = le32_to_cpu(chlist->count);
+- struct brcmu_chan ch;
+- int i;
+-
+- for (i = 0; i < total; i++) {
+- ch.chspec = (u16)le32_to_cpu(chlist->element[i]);
+- cfg->d11inf.decchspec(&ch);
+-
+- /* Firmware gives a ordered list. We skip non-20MHz
+- * channels is 2G. For 5G we can abort upon reaching
+- * a non-20MHz channel in the list.
+- */
+- if (ch.bw != BRCMU_CHAN_BW_20) {
+- if (ch.band == BRCMU_CHAN_BAND_5G)
+- break;
+- else
+- continue;
+- }
+-
+- if (ch.band == BRCMU_CHAN_BAND_2G)
+- chcnt[0] += 1;
+- else if (ch.band == BRCMU_CHAN_BAND_5G)
+- chcnt[1] += 1;
+- }
+-}
+-
+ static void brcmf_update_bw40_channel_flag(struct ieee80211_channel *channel,
+ struct brcmu_chan *ch)
+ {
+@@ -5322,7 +5322,6 @@
+ u32 i, j;
+ u32 total;
+ u32 chaninfo;
+- u32 chcnt[2] = { 0, 0 };
+ u32 index;
+
+ pbuf = kzalloc(BRCMF_DCMD_MEDLEN, GFP_KERNEL);
+@@ -5339,42 +5338,15 @@
+ goto fail_pbuf;
+ }
+
+- brcmf_count_20mhz_channels(cfg, list, chcnt);
+ wiphy = cfg_to_wiphy(cfg);
+- if (chcnt[0]) {
+- band = kmemdup(&__wl_band_2ghz, sizeof(__wl_band_2ghz),
+- GFP_KERNEL);
+- if (band == NULL) {
+- err = -ENOMEM;
+- goto fail_pbuf;
+- }
+- band->channels = kcalloc(chcnt[0], sizeof(*channel),
+- GFP_KERNEL);
+- if (band->channels == NULL) {
+- kfree(band);
+- err = -ENOMEM;
+- goto fail_pbuf;
+- }
+- band->n_channels = 0;
+- wiphy->bands[IEEE80211_BAND_2GHZ] = band;
+- }
+- if (chcnt[1]) {
+- band = kmemdup(&__wl_band_5ghz_a, sizeof(__wl_band_5ghz_a),
+- GFP_KERNEL);
+- if (band == NULL) {
+- err = -ENOMEM;
+- goto fail_band2g;
+- }
+- band->channels = kcalloc(chcnt[1], sizeof(*channel),
+- GFP_KERNEL);
+- if (band->channels == NULL) {
+- kfree(band);
+- err = -ENOMEM;
+- goto fail_band2g;
+- }
+- band->n_channels = 0;
+- wiphy->bands[IEEE80211_BAND_5GHZ] = band;
+- }
++ band = wiphy->bands[IEEE80211_BAND_2GHZ];
++ if (band)
++ for (i = 0; i < band->n_channels; i++)
++ band->channels[i].flags = IEEE80211_CHAN_DISABLED;
++ band = wiphy->bands[IEEE80211_BAND_5GHZ];
++ if (band)
++ for (i = 0; i < band->n_channels; i++)
++ band->channels[i].flags = IEEE80211_CHAN_DISABLED;
+
+ total = le32_to_cpu(list->count);
+ for (i = 0; i < total; i++) {
+@@ -5389,6 +5361,8 @@
+ brcmf_err("Invalid channel Spec. 0x%x.\n", ch.chspec);
+ continue;
+ }
++ if (!band)
++ continue;
+ if (!(bw_cap[band->band] & WLC_BW_40MHZ_BIT) &&
+ ch.bw == BRCMU_CHAN_BW_40)
+ continue;
+@@ -5416,9 +5390,9 @@
+ } else if (ch.bw == BRCMU_CHAN_BW_40) {
+ brcmf_update_bw40_channel_flag(&channel[index], &ch);
+ } else {
+- /* disable other bandwidths for now as mentioned
+- * order assure they are enabled for subsequent
+- * chanspecs.
++ /* enable the channel and disable other bandwidths
++ * for now as mentioned order assure they are enabled
++ * for subsequent chanspecs.
+ */
+ channel[index].flags = IEEE80211_CHAN_NO_HT40 |
+ IEEE80211_CHAN_NO_80MHZ;
+@@ -5437,16 +5411,8 @@
+ IEEE80211_CHAN_NO_IR;
+ }
+ }
+- if (index == band->n_channels)
+- band->n_channels++;
+ }
+- kfree(pbuf);
+- return 0;
+
+-fail_band2g:
+- kfree(wiphy->bands[IEEE80211_BAND_2GHZ]->channels);
+- kfree(wiphy->bands[IEEE80211_BAND_2GHZ]);
+- wiphy->bands[IEEE80211_BAND_2GHZ] = NULL;
+ fail_pbuf:
+ kfree(pbuf);
+ return err;
+@@ -5779,7 +5745,12 @@
+
+ static int brcmf_setup_wiphy(struct wiphy *wiphy, struct brcmf_if *ifp)
+ {
++ struct ieee80211_supported_band *band;
+ struct ieee80211_iface_combination ifc_combo;
++ __le32 bandlist[3];
++ u32 n_bands;
++ int err, i;
++
+ wiphy->max_scan_ssids = WL_NUM_SCAN_MAX;
+ wiphy->max_scan_ie_len = BRCMF_SCAN_IE_LEN_MAX;
+ wiphy->max_num_pmkids = WL_NUM_PMKIDS_MAX;
+@@ -5812,7 +5783,8 @@
+ wiphy->flags |= WIPHY_FLAG_SUPPORTS_FW_ROAM;
+ wiphy->mgmt_stypes = brcmf_txrx_stypes;
+ wiphy->max_remain_on_channel_duration = 5000;
+- brcmf_wiphy_pno_params(wiphy);
++ if (brcmf_feat_is_enabled(ifp, BRCMF_FEAT_PNO))
++ brcmf_wiphy_pno_params(wiphy);
+
+ /* vendor commands/events support */
+ wiphy->vendor_commands = brcmf_vendor_cmds;
+@@ -5821,7 +5793,52 @@
+ if (brcmf_feat_is_enabled(ifp, BRCMF_FEAT_WOWL))
+ brcmf_wiphy_wowl_params(wiphy);
+
+- return brcmf_setup_wiphybands(wiphy);
++ err = brcmf_fil_cmd_data_get(ifp, BRCMF_C_GET_BANDLIST, &bandlist,
++ sizeof(bandlist));
++ if (err) {
++ brcmf_err("could not obtain band info: err=%d\n", err);
++ return err;
++ }
++ /* first entry in bandlist is number of bands */
++ n_bands = le32_to_cpu(bandlist[0]);
++ for (i = 1; i <= n_bands && i < ARRAY_SIZE(bandlist); i++) {
++ if (bandlist[i] == cpu_to_le32(WLC_BAND_2G)) {
++ band = kmemdup(&__wl_band_2ghz, sizeof(__wl_band_2ghz),
++ GFP_KERNEL);
++ if (!band)
++ return -ENOMEM;
++
++ band->channels = kmemdup(&__wl_2ghz_channels,
++ sizeof(__wl_2ghz_channels),
++ GFP_KERNEL);
++ if (!band->channels) {
++ kfree(band);
++ return -ENOMEM;
++ }
++
++ band->n_channels = ARRAY_SIZE(__wl_2ghz_channels);
++ wiphy->bands[IEEE80211_BAND_2GHZ] = band;
++ }
++ if (bandlist[i] == cpu_to_le32(WLC_BAND_5G)) {
++ band = kmemdup(&__wl_band_5ghz, sizeof(__wl_band_5ghz),
++ GFP_KERNEL);
++ if (!band)
++ return -ENOMEM;
++
++ band->channels = kmemdup(&__wl_5ghz_channels,
++ sizeof(__wl_5ghz_channels),
++ GFP_KERNEL);
++ if (!band->channels) {
++ kfree(band);
++ return -ENOMEM;
++ }
++
++ band->n_channels = ARRAY_SIZE(__wl_5ghz_channels);
++ wiphy->bands[IEEE80211_BAND_5GHZ] = band;
++ }
++ }
++ err = brcmf_setup_wiphybands(wiphy);
++ return err;
+ }
+
+ static s32 brcmf_config_dongle(struct brcmf_cfg80211_info *cfg)
+@@ -5998,7 +6015,15 @@
+ brcmf_dbg(TRACE, "enter: initiator=%d, alpha=%c%c\n", req->initiator,
+ req->alpha2[0], req->alpha2[1]);
+
+- /* ignore non-ISO3166 country codes */
++ /* ignore non-ISO3166 country codes
++ * don't report an error on 00 the world roaming
++ * designator as the firmware don't support it
++ * but there is no reason to pass that info to userspace
++ */
++
++ if (req->alpha2[0] == '0' && req->alpha2[1] == '0')
++ return;
++
+ for (i = 0; i < sizeof(req->alpha2); i++)
+ if (req->alpha2[i] < 'A' || req->alpha2[i] > 'Z') {
+ brcmf_err("not a ISO3166 code\n");
+@@ -6007,11 +6032,18 @@
+ memset(&ccreq, 0, sizeof(ccreq));
+ ccreq.rev = cpu_to_le32(-1);
+ memcpy(ccreq.ccode, req->alpha2, sizeof(req->alpha2));
+- brcmf_fil_iovar_data_set(ifp, "country", &ccreq, sizeof(ccreq));
++ if (brcmf_fil_iovar_data_set(ifp, "country", &ccreq, sizeof(ccreq))) {
++ brcmf_err("firmware rejected country setting\n");
++ return;
++ }
++ brcmf_setup_wiphybands(wiphy);
+ }
+
+ static void brcmf_free_wiphy(struct wiphy *wiphy)
+ {
++ if (!wiphy)
++ return;
++
+ kfree(wiphy->iface_combinations);
+ if (wiphy->bands[IEEE80211_BAND_2GHZ]) {
+ kfree(wiphy->bands[IEEE80211_BAND_2GHZ]->channels);
+diff -Nur linux-4.1.3/drivers/net/wireless/brcm80211/brcmfmac/commonring.c linux-xbian-imx6/drivers/net/wireless/brcm80211/brcmfmac/commonring.c
+--- linux-4.1.3/drivers/net/wireless/brcm80211/brcmfmac/commonring.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/drivers/net/wireless/brcm80211/brcmfmac/commonring.c 2015-07-27 23:13:06.848547454 +0200
+@@ -22,17 +22,6 @@
+ #include "core.h"
+ #include "commonring.h"
+
+-
+-/* dma flushing needs implementation for mips and arm platforms. Should
+- * be put in util. Note, this is not real flushing. It is virtual non
+- * cached memory. Only write buffers should have to be drained. Though
+- * this may be different depending on platform......
+- * SEE ALSO msgbuf.c
+- */
+-#define brcmf_dma_flush(addr, len)
+-#define brcmf_dma_invalidate_cache(addr, len)
+-
+-
+ void brcmf_commonring_register_cb(struct brcmf_commonring *commonring,
+ int (*cr_ring_bell)(void *ctx),
+ int (*cr_update_rptr)(void *ctx),
+@@ -206,14 +195,9 @@
+ address = commonring->buf_addr;
+ address += (commonring->f_ptr * commonring->item_len);
+ if (commonring->f_ptr > commonring->w_ptr) {
+- brcmf_dma_flush(address,
+- (commonring->depth - commonring->f_ptr) *
+- commonring->item_len);
+ address = commonring->buf_addr;
+ commonring->f_ptr = 0;
+ }
+- brcmf_dma_flush(address, (commonring->w_ptr - commonring->f_ptr) *
+- commonring->item_len);
+
+ commonring->f_ptr = commonring->w_ptr;
+
+@@ -258,8 +242,6 @@
+ if (commonring->r_ptr == commonring->depth)
+ commonring->r_ptr = 0;
+
+- brcmf_dma_invalidate_cache(ret_addr, *n_ items * commonring->item_len);
+-
+ return ret_addr;
+ }
+
+diff -Nur linux-4.1.3/drivers/net/wireless/brcm80211/brcmfmac/core.c linux-xbian-imx6/drivers/net/wireless/brcm80211/brcmfmac/core.c
+--- linux-4.1.3/drivers/net/wireless/brcm80211/brcmfmac/core.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/drivers/net/wireless/brcm80211/brcmfmac/core.c 2015-07-27 23:13:06.848547454 +0200
+@@ -791,15 +791,15 @@
+ * in case we missed the BRCMF_E_IF_DEL event.
+ */
+ if (ifp) {
+- brcmf_err("ERROR: netdev:%s already exists\n",
+- ifp->ndev->name);
+ if (ifidx) {
++ brcmf_err("ERROR: netdev:%s already exists, deleting old interface\n",
++ ifp->ndev->name);
+ netif_stop_queue(ifp->ndev);
+ unregister_netdev(ifp->ndev);
+ free_netdev(ifp->ndev);
+ drvr->iflist[bssidx] = NULL;
+ } else {
+- brcmf_err("ignore IF event\n");
++ brcmf_dbg(EVENT, "ignore IF event\n");
+ return ERR_PTR(-EINVAL);
+ }
+ }
+diff -Nur linux-4.1.3/drivers/net/wireless/brcm80211/brcmfmac/feature.c linux-xbian-imx6/drivers/net/wireless/brcm80211/brcmfmac/feature.c
+--- linux-4.1.3/drivers/net/wireless/brcm80211/brcmfmac/feature.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/drivers/net/wireless/brcm80211/brcmfmac/feature.c 2015-07-27 23:13:06.848547454 +0200
+@@ -124,9 +124,11 @@
+ struct brcmf_if *ifp = drvr->iflist[0];
+
+ brcmf_feat_iovar_int_get(ifp, BRCMF_FEAT_MCHAN, "mchan");
++ brcmf_feat_iovar_int_get(ifp, BRCMF_FEAT_PNO, "pfn");
+ if (drvr->bus_if->wowl_supported)
+ brcmf_feat_iovar_int_get(ifp, BRCMF_FEAT_WOWL, "wowl");
+- if (drvr->bus_if->chip != BRCM_CC_43362_CHIP_ID)
++ if ((drvr->bus_if->chip != BRCM_CC_43362_CHIP_ID) &&
++ (drvr->bus_if->chip != BRCM_CC_4330_CHIP_ID))
+ brcmf_feat_iovar_int_set(ifp, BRCMF_FEAT_MBSS, "mbss", 0);
+
+ /* set chip related quirks */
+diff -Nur linux-4.1.3/drivers/net/wireless/brcm80211/brcmfmac/feature.h linux-xbian-imx6/drivers/net/wireless/brcm80211/brcmfmac/feature.h
+--- linux-4.1.3/drivers/net/wireless/brcm80211/brcmfmac/feature.h 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/drivers/net/wireless/brcm80211/brcmfmac/feature.h 2015-07-27 23:13:06.848547454 +0200
+@@ -19,11 +19,15 @@
+ /*
+ * Features:
+ *
++ * MBSS: multiple BSSID support (eg. guest network in AP mode).
+ * MCHAN: multi-channel for concurrent P2P.
++ * PNO: preferred network offload.
++ * WOWL: Wake-On-WLAN.
+ */
+ #define BRCMF_FEAT_LIST \
+ BRCMF_FEAT_DEF(MBSS) \
+ BRCMF_FEAT_DEF(MCHAN) \
++ BRCMF_FEAT_DEF(PNO) \
+ BRCMF_FEAT_DEF(WOWL)
+ /*
+ * Quirks:
+diff -Nur linux-4.1.3/drivers/net/wireless/brcm80211/brcmfmac/firmware.c linux-xbian-imx6/drivers/net/wireless/brcm80211/brcmfmac/firmware.c
+--- linux-4.1.3/drivers/net/wireless/brcm80211/brcmfmac/firmware.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/drivers/net/wireless/brcm80211/brcmfmac/firmware.c 2015-07-27 23:13:06.848547454 +0200
+@@ -23,6 +23,10 @@
+ #include "debug.h"
+ #include "firmware.h"
+
++#define BRCMF_FW_MAX_NVRAM_SIZE 64000
++#define BRCMF_FW_NVRAM_DEVPATH_LEN 19 /* devpath0=pcie/1/4/ */
++#define BRCMF_FW_NVRAM_PCIEDEV_LEN 9 /* pcie/1/4/ */
++
+ char brcmf_firmware_path[BRCMF_FW_PATH_LEN];
+ module_param_string(firmware_path, brcmf_firmware_path,
+ BRCMF_FW_PATH_LEN, 0440);
+@@ -46,6 +50,8 @@
+ * @column: current column in line.
+ * @pos: byte offset in input buffer.
+ * @entry: start position of key,value entry.
++ * @multi_dev_v1: detect pcie multi device v1 (compressed).
++ * @multi_dev_v2: detect pcie multi device v2.
+ */
+ struct nvram_parser {
+ enum nvram_parser_state state;
+@@ -56,6 +62,8 @@
+ u32 column;
+ u32 pos;
+ u32 entry;
++ bool multi_dev_v1;
++ bool multi_dev_v2;
+ };
+
+ static bool is_nvram_char(char c)
+@@ -108,6 +116,10 @@
+ st = COMMENT;
+ else
+ st = VALUE;
++ if (strncmp(&nvp->fwnv->data[nvp->entry], "devpath", 7) == 0)
++ nvp->multi_dev_v1 = true;
++ if (strncmp(&nvp->fwnv->data[nvp->entry], "pcie/", 5) == 0)
++ nvp->multi_dev_v2 = true;
+ } else if (!is_nvram_char(c)) {
+ brcmf_dbg(INFO, "warning: ln=%d:col=%d: '=' expected, skip invalid key entry\n",
+ nvp->line, nvp->column);
+@@ -133,6 +145,8 @@
+ ekv = (u8 *)&nvp->fwnv->data[nvp->pos];
+ skv = (u8 *)&nvp->fwnv->data[nvp->entry];
+ cplen = ekv - skv;
++ if (nvp->nvram_len + cplen + 1 >= BRCMF_FW_MAX_NVRAM_SIZE)
++ return END;
+ /* copy to output buffer */
+ memcpy(&nvp->nvram[nvp->nvram_len], skv, cplen);
+ nvp->nvram_len += cplen;
+@@ -180,10 +194,18 @@
+ static int brcmf_init_nvram_parser(struct nvram_parser *nvp,
+ const struct firmware *nv)
+ {
++ size_t size;
++
+ memset(nvp, 0, sizeof(*nvp));
+ nvp->fwnv = nv;
++ /* Limit size to MAX_NVRAM_SIZE, some files contain lot of comment */
++ if (nv->size > BRCMF_FW_MAX_NVRAM_SIZE)
++ size = BRCMF_FW_MAX_NVRAM_SIZE;
++ else
++ size = nv->size;
+ /* Alloc for extra 0 byte + roundup by 4 + length field */
+- nvp->nvram = kzalloc(nv->size + 1 + 3 + sizeof(u32), GFP_KERNEL);
++ size += 1 + 3 + sizeof(u32);
++ nvp->nvram = kzalloc(size, GFP_KERNEL);
+ if (!nvp->nvram)
+ return -ENOMEM;
+
+@@ -192,12 +214,136 @@
+ return 0;
+ }
+
++/* brcmf_fw_strip_multi_v1 :Some nvram files contain settings for multiple
++ * devices. Strip it down for one device, use domain_nr/bus_nr to determine
++ * which data is to be returned. v1 is the version where nvram is stored
++ * compressed and "devpath" maps to index for valid entries.
++ */
++static void brcmf_fw_strip_multi_v1(struct nvram_parser *nvp, u16 domain_nr,
++ u16 bus_nr)
++{
++ u32 i, j;
++ bool found;
++ u8 *nvram;
++ u8 id;
++
++ nvram = kzalloc(nvp->nvram_len + 1 + 3 + sizeof(u32), GFP_KERNEL);
++ if (!nvram)
++ goto fail;
++
++ /* min length: devpath0=pcie/1/4/ + 0:x=y */
++ if (nvp->nvram_len < BRCMF_FW_NVRAM_DEVPATH_LEN + 6)
++ goto fail;
++
++ /* First search for the devpathX and see if it is the configuration
++ * for domain_nr/bus_nr. Search complete nvp
++ */
++ found = false;
++ i = 0;
++ while (i < nvp->nvram_len - BRCMF_FW_NVRAM_DEVPATH_LEN) {
++ /* Format: devpathX=pcie/Y/Z/
++ * Y = domain_nr, Z = bus_nr, X = virtual ID
++ */
++ if ((strncmp(&nvp->nvram[i], "devpath", 7) == 0) &&
++ (strncmp(&nvp->nvram[i + 8], "=pcie/", 6) == 0)) {
++ if (((nvp->nvram[i + 14] - '0') == domain_nr) &&
++ ((nvp->nvram[i + 16] - '0') == bus_nr)) {
++ id = nvp->nvram[i + 7] - '0';
++ found = true;
++ break;
++ }
++ }
++ while (nvp->nvram[i] != 0)
++ i++;
++ i++;
++ }
++ if (!found)
++ goto fail;
++
++ /* Now copy all valid entries, release old nvram and assign new one */
++ i = 0;
++ j = 0;
++ while (i < nvp->nvram_len) {
++ if ((nvp->nvram[i] - '0' == id) && (nvp->nvram[i + 1] == ':')) {
++ i += 2;
++ while (nvp->nvram[i] != 0) {
++ nvram[j] = nvp->nvram[i];
++ i++;
++ j++;
++ }
++ nvram[j] = 0;
++ j++;
++ }
++ while (nvp->nvram[i] != 0)
++ i++;
++ i++;
++ }
++ kfree(nvp->nvram);
++ nvp->nvram = nvram;
++ nvp->nvram_len = j;
++ return;
++
++fail:
++ kfree(nvram);
++ nvp->nvram_len = 0;
++}
++
++/* brcmf_fw_strip_multi_v2 :Some nvram files contain settings for multiple
++ * devices. Strip it down for one device, use domain_nr/bus_nr to determine
++ * which data is to be returned. v2 is the version where nvram is stored
++ * uncompressed, all relevant valid entries are identified by
++ * pcie/domain_nr/bus_nr:
++ */
++static void brcmf_fw_strip_multi_v2(struct nvram_parser *nvp, u16 domain_nr,
++ u16 bus_nr)
++{
++ u32 i, j;
++ u8 *nvram;
++
++ nvram = kzalloc(nvp->nvram_len + 1 + 3 + sizeof(u32), GFP_KERNEL);
++ if (!nvram)
++ goto fail;
++
++ /* Copy all valid entries, release old nvram and assign new one.
++ * Valid entries are of type pcie/X/Y/ where X = domain_nr and
++ * Y = bus_nr.
++ */
++ i = 0;
++ j = 0;
++ while (i < nvp->nvram_len - BRCMF_FW_NVRAM_PCIEDEV_LEN) {
++ if ((strncmp(&nvp->nvram[i], "pcie/", 5) == 0) &&
++ (nvp->nvram[i + 6] == '/') && (nvp->nvram[i + 8] == '/') &&
++ ((nvp->nvram[i + 5] - '0') == domain_nr) &&
++ ((nvp->nvram[i + 7] - '0') == bus_nr)) {
++ i += BRCMF_FW_NVRAM_PCIEDEV_LEN;
++ while (nvp->nvram[i] != 0) {
++ nvram[j] = nvp->nvram[i];
++ i++;
++ j++;
++ }
++ nvram[j] = 0;
++ j++;
++ }
++ while (nvp->nvram[i] != 0)
++ i++;
++ i++;
++ }
++ kfree(nvp->nvram);
++ nvp->nvram = nvram;
++ nvp->nvram_len = j;
++ return;
++fail:
++ kfree(nvram);
++ nvp->nvram_len = 0;
++}
++
+ /* brcmf_nvram_strip :Takes a buffer of "<var>=<value>\n" lines read from a fil
+ * and ending in a NUL. Removes carriage returns, empty lines, comment lines,
+ * and converts newlines to NULs. Shortens buffer as needed and pads with NULs.
+ * End of buffer is completed with token identifying length of buffer.
+ */
+-static void *brcmf_fw_nvram_strip(const struct firmware *nv, u32 *new_length)
++static void *brcmf_fw_nvram_strip(const struct firmware *nv, u32 *new_length,
++ u16 domain_nr, u16 bus_nr)
+ {
+ struct nvram_parser nvp;
+ u32 pad;
+@@ -212,6 +358,16 @@
+ if (nvp.state == END)
+ break;
+ }
++ if (nvp.multi_dev_v1)
++ brcmf_fw_strip_multi_v1(&nvp, domain_nr, bus_nr);
++ else if (nvp.multi_dev_v2)
++ brcmf_fw_strip_multi_v2(&nvp, domain_nr, bus_nr);
++
++ if (nvp.nvram_len == 0) {
++ kfree(nvp.nvram);
++ return NULL;
++ }
++
+ pad = nvp.nvram_len;
+ *new_length = roundup(nvp.nvram_len + 1, 4);
+ while (pad != *new_length) {
+@@ -239,6 +395,8 @@
+ u16 flags;
+ const struct firmware *code;
+ const char *nvram_name;
++ u16 domain_nr;
++ u16 bus_nr;
+ void (*done)(struct device *dev, const struct firmware *fw,
+ void *nvram_image, u32 nvram_len);
+ };
+@@ -254,7 +412,8 @@
+ goto fail;
+
+ if (fw) {
+- nvram = brcmf_fw_nvram_strip(fw, &nvram_length);
++ nvram = brcmf_fw_nvram_strip(fw, &nvram_length,
++ fwctx->domain_nr, fwctx->bus_nr);
+ release_firmware(fw);
+ if (!nvram && !(fwctx->flags & BRCMF_FW_REQ_NV_OPTIONAL))
+ goto fail;
+@@ -309,11 +468,12 @@
+ kfree(fwctx);
+ }
+
+-int brcmf_fw_get_firmwares(struct device *dev, u16 flags,
+- const char *code, const char *nvram,
+- void (*fw_cb)(struct device *dev,
+- const struct firmware *fw,
+- void *nvram_image, u32 nvram_len))
++int brcmf_fw_get_firmwares_pcie(struct device *dev, u16 flags,
++ const char *code, const char *nvram,
++ void (*fw_cb)(struct device *dev,
++ const struct firmware *fw,
++ void *nvram_image, u32 nvram_len),
++ u16 domain_nr, u16 bus_nr)
+ {
+ struct brcmf_fw *fwctx;
+
+@@ -333,8 +493,21 @@
+ fwctx->done = fw_cb;
+ if (flags & BRCMF_FW_REQUEST_NVRAM)
+ fwctx->nvram_name = nvram;
++ fwctx->domain_nr = domain_nr;
++ fwctx->bus_nr = bus_nr;
+
+ return request_firmware_nowait(THIS_MODULE, true, code, dev,
+ GFP_KERNEL, fwctx,
+ brcmf_fw_request_code_done);
+ }
++
++int brcmf_fw_get_firmwares(struct device *dev, u16 flags,
++ const char *code, const char *nvram,
++ void (*fw_cb)(struct device *dev,
++ const struct firmware *fw,
++ void *nvram_image, u32 nvram_len))
++{
++ return brcmf_fw_get_firmwares_pcie(dev, flags, code, nvram, fw_cb, 0,
++ 0);
++}
++
+diff -Nur linux-4.1.3/drivers/net/wireless/brcm80211/brcmfmac/firmware.h linux-xbian-imx6/drivers/net/wireless/brcm80211/brcmfmac/firmware.h
+--- linux-4.1.3/drivers/net/wireless/brcm80211/brcmfmac/firmware.h 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/drivers/net/wireless/brcm80211/brcmfmac/firmware.h 2015-07-27 23:13:06.848547454 +0200
+@@ -32,6 +32,12 @@
+ * fails it will not use the callback, but call device_release_driver()
+ * instead which will call the driver .remove() callback.
+ */
++int brcmf_fw_get_firmwares_pcie(struct device *dev, u16 flags,
++ const char *code, const char *nvram,
++ void (*fw_cb)(struct device *dev,
++ const struct firmware *fw,
++ void *nvram_image, u32 nvram_len),
++ u16 domain_nr, u16 bus_nr);
+ int brcmf_fw_get_firmwares(struct device *dev, u16 flags,
+ const char *code, const char *nvram,
+ void (*fw_cb)(struct device *dev,
+diff -Nur linux-4.1.3/drivers/net/wireless/brcm80211/brcmfmac/flowring.c linux-xbian-imx6/drivers/net/wireless/brcm80211/brcmfmac/flowring.c
+--- linux-4.1.3/drivers/net/wireless/brcm80211/brcmfmac/flowring.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/drivers/net/wireless/brcm80211/brcmfmac/flowring.c 2015-07-27 23:13:06.848547454 +0200
+@@ -249,8 +249,8 @@
+ }
+
+
+-void brcmf_flowring_enqueue(struct brcmf_flowring *flow, u8 flowid,
+- struct sk_buff *skb)
++u32 brcmf_flowring_enqueue(struct brcmf_flowring *flow, u8 flowid,
++ struct sk_buff *skb)
+ {
+ struct brcmf_flowring_ring *ring;
+
+@@ -271,6 +271,7 @@
+ if (skb_queue_len(&ring->skblist) < BRCMF_FLOWRING_LOW)
+ brcmf_flowring_block(flow, flowid, false);
+ }
++ return skb_queue_len(&ring->skblist);
+ }
+
+
+diff -Nur linux-4.1.3/drivers/net/wireless/brcm80211/brcmfmac/flowring.h linux-xbian-imx6/drivers/net/wireless/brcm80211/brcmfmac/flowring.h
+--- linux-4.1.3/drivers/net/wireless/brcm80211/brcmfmac/flowring.h 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/drivers/net/wireless/brcm80211/brcmfmac/flowring.h 2015-07-27 23:13:06.848547454 +0200
+@@ -64,8 +64,8 @@
+ void brcmf_flowring_delete(struct brcmf_flowring *flow, u8 flowid);
+ void brcmf_flowring_open(struct brcmf_flowring *flow, u8 flowid);
+ u8 brcmf_flowring_tid(struct brcmf_flowring *flow, u8 flowid);
+-void brcmf_flowring_enqueue(struct brcmf_flowring *flow, u8 flowid,
+- struct sk_buff *skb);
++u32 brcmf_flowring_enqueue(struct brcmf_flowring *flow, u8 flowid,
++ struct sk_buff *skb);
+ struct sk_buff *brcmf_flowring_dequeue(struct brcmf_flowring *flow, u8 flowid);
+ void brcmf_flowring_reinsert(struct brcmf_flowring *flow, u8 flowid,
+ struct sk_buff *skb);
+diff -Nur linux-4.1.3/drivers/net/wireless/brcm80211/brcmfmac/fwsignal.c linux-xbian-imx6/drivers/net/wireless/brcm80211/brcmfmac/fwsignal.c
+--- linux-4.1.3/drivers/net/wireless/brcm80211/brcmfmac/fwsignal.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/drivers/net/wireless/brcm80211/brcmfmac/fwsignal.c 2015-07-27 23:13:06.860504792 +0200
+@@ -635,7 +635,7 @@
+ return 0;
+ }
+
+-static int brcmf_fws_hanger_poppkt(struct brcmf_fws_hanger *h,
++static inline int brcmf_fws_hanger_poppkt(struct brcmf_fws_hanger *h,
+ u32 slot_id, struct sk_buff **pktout,
+ bool remove_item)
+ {
+diff -Nur linux-4.1.3/drivers/net/wireless/brcm80211/brcmfmac/msgbuf.c linux-xbian-imx6/drivers/net/wireless/brcm80211/brcmfmac/msgbuf.c
+--- linux-4.1.3/drivers/net/wireless/brcm80211/brcmfmac/msgbuf.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/drivers/net/wireless/brcm80211/brcmfmac/msgbuf.c 2015-07-27 23:13:06.860504792 +0200
+@@ -73,7 +73,7 @@
+ #define BRCMF_MSGBUF_TX_FLUSH_CNT1 32
+ #define BRCMF_MSGBUF_TX_FLUSH_CNT2 96
+
+-#define BRCMF_MSGBUF_DELAY_TXWORKER_THRS 64
++#define BRCMF_MSGBUF_DELAY_TXWORKER_THRS 96
+ #define BRCMF_MSGBUF_TRICKLE_TXWORKER_THRS 32
+
+ struct msgbuf_common_hdr {
+@@ -278,16 +278,6 @@
+ struct brcmf_msgbuf_pktid *array;
+ };
+
+-
+-/* dma flushing needs implementation for mips and arm platforms. Should
+- * be put in util. Note, this is not real flushing. It is virtual non
+- * cached memory. Only write buffers should have to be drained. Though
+- * this may be different depending on platform......
+- */
+-#define brcmf_dma_flush(addr, len)
+-#define brcmf_dma_invalidate_cache(addr, len)
+-
+-
+ static void brcmf_msgbuf_rxbuf_ioctlresp_post(struct brcmf_msgbuf *msgbuf);
+
+
+@@ -462,7 +452,6 @@
+ memcpy(msgbuf->ioctbuf, buf, buf_len);
+ else
+ memset(msgbuf->ioctbuf, 0, buf_len);
+- brcmf_dma_flush(ioctl_buf, buf_len);
+
+ err = brcmf_commonring_write_complete(commonring);
+ brcmf_commonring_unlock(commonring);
+@@ -795,6 +784,8 @@
+ struct brcmf_flowring *flow = msgbuf->flow;
+ struct ethhdr *eh = (struct ethhdr *)(skb->data);
+ u32 flowid;
++ u32 queue_count;
++ bool force;
+
+ flowid = brcmf_flowring_lookup(flow, eh->h_dest, skb->priority, ifidx);
+ if (flowid == BRCMF_FLOWRING_INVALID_ID) {
+@@ -802,8 +793,9 @@
+ if (flowid == BRCMF_FLOWRING_INVALID_ID)
+ return -ENOMEM;
+ }
+- brcmf_flowring_enqueue(flow, flowid, skb);
+- brcmf_msgbuf_schedule_txdata(msgbuf, flowid, false);
++ queue_count = brcmf_flowring_enqueue(flow, flowid, skb);
++ force = ((queue_count % BRCMF_MSGBUF_TRICKLE_TXWORKER_THRS) == 0);
++ brcmf_msgbuf_schedule_txdata(msgbuf, flowid, force);
+
+ return 0;
+ }
+diff -Nur linux-4.1.3/drivers/net/wireless/brcm80211/brcmfmac/of.c linux-xbian-imx6/drivers/net/wireless/brcm80211/brcmfmac/of.c
+--- linux-4.1.3/drivers/net/wireless/brcm80211/brcmfmac/of.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/drivers/net/wireless/brcm80211/brcmfmac/of.c 2015-07-27 23:13:06.868476350 +0200
+@@ -39,10 +39,16 @@
+ if (!sdiodev->pdata)
+ return;
+
++ if (of_property_read_u32(np, "brcm,drive-strength", &val) == 0)
++ sdiodev->pdata->drive_strength = val;
++
++ /* make sure there are interrupts defined in the node */
++ if (!of_find_property(np, "interrupts", NULL))
++ return;
++
+ irq = irq_of_parse_and_map(np, 0);
+ if (!irq) {
+ brcmf_err("interrupt could not be mapped\n");
+- devm_kfree(dev, sdiodev->pdata);
+ return;
+ }
+ irqf = irqd_get_trigger_type(irq_get_irq_data(irq));
+@@ -50,7 +56,4 @@
+ sdiodev->pdata->oob_irq_supported = true;
+ sdiodev->pdata->oob_irq_nr = irq;
+ sdiodev->pdata->oob_irq_flags = irqf;
+-
+- if (of_property_read_u32(np, "brcm,drive-strength", &val) == 0)
+- sdiodev->pdata->drive_strength = val;
+ }
+diff -Nur linux-4.1.3/drivers/net/wireless/brcm80211/brcmfmac/pcie.c linux-xbian-imx6/drivers/net/wireless/brcm80211/brcmfmac/pcie.c
+--- linux-4.1.3/drivers/net/wireless/brcm80211/brcmfmac/pcie.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/drivers/net/wireless/brcm80211/brcmfmac/pcie.c 2015-07-27 23:13:06.868476350 +0200
+@@ -110,10 +110,12 @@
+ BRCMF_PCIE_MB_INT_D2H3_DB0 | \
+ BRCMF_PCIE_MB_INT_D2H3_DB1)
+
+-#define BRCMF_PCIE_MIN_SHARED_VERSION 4
++#define BRCMF_PCIE_MIN_SHARED_VERSION 5
+ #define BRCMF_PCIE_MAX_SHARED_VERSION 5
+ #define BRCMF_PCIE_SHARED_VERSION_MASK 0x00FF
+ #define BRCMF_PCIE_SHARED_TXPUSH_SUPPORT 0x4000
++#define BRCMF_PCIE_SHARED_DMA_INDEX 0x10000
++#define BRCMF_PCIE_SHARED_DMA_2B_IDX 0x100000
+
+ #define BRCMF_PCIE_FLAGS_HTOD_SPLIT 0x4000
+ #define BRCMF_PCIE_FLAGS_DTOH_SPLIT 0x8000
+@@ -145,6 +147,10 @@
+ #define BRCMF_SHARED_RING_H2D_R_IDX_PTR_OFFSET 8
+ #define BRCMF_SHARED_RING_D2H_W_IDX_PTR_OFFSET 12
+ #define BRCMF_SHARED_RING_D2H_R_IDX_PTR_OFFSET 16
++#define BRCMF_SHARED_RING_H2D_WP_HADDR_OFFSET 20
++#define BRCMF_SHARED_RING_H2D_RP_HADDR_OFFSET 28
++#define BRCMF_SHARED_RING_D2H_WP_HADDR_OFFSET 36
++#define BRCMF_SHARED_RING_D2H_RP_HADDR_OFFSET 44
+ #define BRCMF_SHARED_RING_TCM_MEMLOC_OFFSET 0
+ #define BRCMF_SHARED_RING_MAX_SUB_QUEUES 52
+
+@@ -244,6 +250,13 @@
+ bool mbdata_completed;
+ bool irq_allocated;
+ bool wowl_enabled;
++ u8 dma_idx_sz;
++ void *idxbuf;
++ u32 idxbuf_sz;
++ dma_addr_t idxbuf_dmahandle;
++ u16 (*read_ptr)(struct brcmf_pciedev_info *devinfo, u32 mem_offset);
++ void (*write_ptr)(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
++ u16 value);
+ };
+
+ struct brcmf_pcie_ringbuf {
+@@ -273,15 +286,6 @@
+ };
+
+
+-/* dma flushing needs implementation for mips and arm platforms. Should
+- * be put in util. Note, this is not real flushing. It is virtual non
+- * cached memory. Only write buffers should have to be drained. Though
+- * this may be different depending on platform......
+- */
+-#define brcmf_dma_flush(addr, len)
+-#define brcmf_dma_invalidate_cache(addr, len)
+-
+-
+ static u32
+ brcmf_pcie_read_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset)
+ {
+@@ -329,6 +333,25 @@
+ }
+
+
++static u16
++brcmf_pcie_read_idx(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
++{
++ u16 *address = devinfo->idxbuf + mem_offset;
++
++ return (*(address));
++}
++
++
++static void
++brcmf_pcie_write_idx(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
++ u16 value)
++{
++ u16 *address = devinfo->idxbuf + mem_offset;
++
++ *(address) = value;
++}
++
++
+ static u32
+ brcmf_pcie_read_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
+ {
+@@ -874,7 +897,7 @@
+ brcmf_dbg(PCIE, "W r_ptr %d (%d), ring %d\n", commonring->r_ptr,
+ commonring->w_ptr, ring->id);
+
+- brcmf_pcie_write_tcm16(devinfo, ring->r_idx_addr, commonring->r_ptr);
++ devinfo->write_ptr(devinfo, ring->r_idx_addr, commonring->r_ptr);
+
+ return 0;
+ }
+@@ -892,7 +915,7 @@
+ brcmf_dbg(PCIE, "W w_ptr %d (%d), ring %d\n", commonring->w_ptr,
+ commonring->r_ptr, ring->id);
+
+- brcmf_pcie_write_tcm16(devinfo, ring->w_idx_addr, commonring->w_ptr);
++ devinfo->write_ptr(devinfo, ring->w_idx_addr, commonring->w_ptr);
+
+ return 0;
+ }
+@@ -921,7 +944,7 @@
+ if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
+ return -EIO;
+
+- commonring->r_ptr = brcmf_pcie_read_tcm16(devinfo, ring->r_idx_addr);
++ commonring->r_ptr = devinfo->read_ptr(devinfo, ring->r_idx_addr);
+
+ brcmf_dbg(PCIE, "R r_ptr %d (%d), ring %d\n", commonring->r_ptr,
+ commonring->w_ptr, ring->id);
+@@ -939,7 +962,7 @@
+ if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
+ return -EIO;
+
+- commonring->w_ptr = brcmf_pcie_read_tcm16(devinfo, ring->w_idx_addr);
++ commonring->w_ptr = devinfo->read_ptr(devinfo, ring->w_idx_addr);
+
+ brcmf_dbg(PCIE, "R w_ptr %d (%d), ring %d\n", commonring->w_ptr,
+ commonring->r_ptr, ring->id);
+@@ -1044,6 +1067,13 @@
+ }
+ kfree(devinfo->shared.flowrings);
+ devinfo->shared.flowrings = NULL;
++ if (devinfo->idxbuf) {
++ dma_free_coherent(&devinfo->pdev->dev,
++ devinfo->idxbuf_sz,
++ devinfo->idxbuf,
++ devinfo->idxbuf_dmahandle);
++ devinfo->idxbuf = NULL;
++ }
+ }
+
+
+@@ -1059,19 +1089,72 @@
+ u32 addr;
+ u32 ring_mem_ptr;
+ u32 i;
++ u64 address;
++ u32 bufsz;
+ u16 max_sub_queues;
++ u8 idx_offset;
+
+ ring_addr = devinfo->shared.ring_info_addr;
+ brcmf_dbg(PCIE, "Base ring addr = 0x%08x\n", ring_addr);
++ addr = ring_addr + BRCMF_SHARED_RING_MAX_SUB_QUEUES;
++ max_sub_queues = brcmf_pcie_read_tcm16(devinfo, addr);
+
+- addr = ring_addr + BRCMF_SHARED_RING_D2H_W_IDX_PTR_OFFSET;
+- d2h_w_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
+- addr = ring_addr + BRCMF_SHARED_RING_D2H_R_IDX_PTR_OFFSET;
+- d2h_r_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
+- addr = ring_addr + BRCMF_SHARED_RING_H2D_W_IDX_PTR_OFFSET;
+- h2d_w_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
+- addr = ring_addr + BRCMF_SHARED_RING_H2D_R_IDX_PTR_OFFSET;
+- h2d_r_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
++ if (devinfo->dma_idx_sz != 0) {
++ bufsz = (BRCMF_NROF_D2H_COMMON_MSGRINGS + max_sub_queues) *
++ devinfo->dma_idx_sz * 2;
++ devinfo->idxbuf = dma_alloc_coherent(&devinfo->pdev->dev, bufsz,
++ &devinfo->idxbuf_dmahandle,
++ GFP_KERNEL);
++ if (!devinfo->idxbuf)
++ devinfo->dma_idx_sz = 0;
++ }
++
++ if (devinfo->dma_idx_sz == 0) {
++ addr = ring_addr + BRCMF_SHARED_RING_D2H_W_IDX_PTR_OFFSET;
++ d2h_w_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
++ addr = ring_addr + BRCMF_SHARED_RING_D2H_R_IDX_PTR_OFFSET;
++ d2h_r_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
++ addr = ring_addr + BRCMF_SHARED_RING_H2D_W_IDX_PTR_OFFSET;
++ h2d_w_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
++ addr = ring_addr + BRCMF_SHARED_RING_H2D_R_IDX_PTR_OFFSET;
++ h2d_r_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
++ idx_offset = sizeof(u32);
++ devinfo->write_ptr = brcmf_pcie_write_tcm16;
++ devinfo->read_ptr = brcmf_pcie_read_tcm16;
++ brcmf_dbg(PCIE, "Using TCM indices\n");
++ } else {
++ memset(devinfo->idxbuf, 0, bufsz);
++ devinfo->idxbuf_sz = bufsz;
++ idx_offset = devinfo->dma_idx_sz;
++ devinfo->write_ptr = brcmf_pcie_write_idx;
++ devinfo->read_ptr = brcmf_pcie_read_idx;
++
++ h2d_w_idx_ptr = 0;
++ addr = ring_addr + BRCMF_SHARED_RING_H2D_WP_HADDR_OFFSET;
++ address = (u64)devinfo->idxbuf_dmahandle;
++ brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
++ brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
++
++ h2d_r_idx_ptr = h2d_w_idx_ptr + max_sub_queues * idx_offset;
++ addr = ring_addr + BRCMF_SHARED_RING_H2D_RP_HADDR_OFFSET;
++ address += max_sub_queues * idx_offset;
++ brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
++ brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
++
++ d2h_w_idx_ptr = h2d_r_idx_ptr + max_sub_queues * idx_offset;
++ addr = ring_addr + BRCMF_SHARED_RING_D2H_WP_HADDR_OFFSET;
++ address += max_sub_queues * idx_offset;
++ brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
++ brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
++
++ d2h_r_idx_ptr = d2h_w_idx_ptr +
++ BRCMF_NROF_D2H_COMMON_MSGRINGS * idx_offset;
++ addr = ring_addr + BRCMF_SHARED_RING_D2H_RP_HADDR_OFFSET;
++ address += BRCMF_NROF_D2H_COMMON_MSGRINGS * idx_offset;
++ brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
++ brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
++ brcmf_dbg(PCIE, "Using host memory indices\n");
++ }
+
+ addr = ring_addr + BRCMF_SHARED_RING_TCM_MEMLOC_OFFSET;
+ ring_mem_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
+@@ -1085,8 +1168,8 @@
+ ring->id = i;
+ devinfo->shared.commonrings[i] = ring;
+
+- h2d_w_idx_ptr += sizeof(u32);
+- h2d_r_idx_ptr += sizeof(u32);
++ h2d_w_idx_ptr += idx_offset;
++ h2d_r_idx_ptr += idx_offset;
+ ring_mem_ptr += BRCMF_RING_MEM_SZ;
+ }
+
+@@ -1100,13 +1183,11 @@
+ ring->id = i;
+ devinfo->shared.commonrings[i] = ring;
+
+- d2h_w_idx_ptr += sizeof(u32);
+- d2h_r_idx_ptr += sizeof(u32);
++ d2h_w_idx_ptr += idx_offset;
++ d2h_r_idx_ptr += idx_offset;
+ ring_mem_ptr += BRCMF_RING_MEM_SZ;
+ }
+
+- addr = ring_addr + BRCMF_SHARED_RING_MAX_SUB_QUEUES;
+- max_sub_queues = brcmf_pcie_read_tcm16(devinfo, addr);
+ devinfo->shared.nrof_flowrings =
+ max_sub_queues - BRCMF_NROF_H2D_COMMON_MSGRINGS;
+ rings = kcalloc(devinfo->shared.nrof_flowrings, sizeof(*ring),
+@@ -1130,15 +1211,15 @@
+ ring);
+ ring->w_idx_addr = h2d_w_idx_ptr;
+ ring->r_idx_addr = h2d_r_idx_ptr;
+- h2d_w_idx_ptr += sizeof(u32);
+- h2d_r_idx_ptr += sizeof(u32);
++ h2d_w_idx_ptr += idx_offset;
++ h2d_r_idx_ptr += idx_offset;
+ }
+ devinfo->shared.flowrings = rings;
+
+ return 0;
+
+ fail:
+- brcmf_err("Allocating commonring buffers failed\n");
++ brcmf_err("Allocating ring buffers failed\n");
+ brcmf_pcie_release_ringbuffers(devinfo);
+ return -ENOMEM;
+ }
+@@ -1171,7 +1252,6 @@
+ goto fail;
+
+ memset(devinfo->shared.scratch, 0, BRCMF_DMA_D2H_SCRATCH_BUF_LEN);
+- brcmf_dma_flush(devinfo->shared.scratch, BRCMF_DMA_D2H_SCRATCH_BUF_LEN);
+
+ addr = devinfo->shared.tcm_base_address +
+ BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET;
+@@ -1189,7 +1269,6 @@
+ goto fail;
+
+ memset(devinfo->shared.ringupd, 0, BRCMF_DMA_D2H_RINGUPD_BUF_LEN);
+- brcmf_dma_flush(devinfo->shared.ringupd, BRCMF_DMA_D2H_RINGUPD_BUF_LEN);
+
+ addr = devinfo->shared.tcm_base_address +
+ BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET;
+@@ -1276,10 +1355,13 @@
+ brcmf_err("Unsupported PCIE version %d\n", version);
+ return -EINVAL;
+ }
+- if (shared->flags & BRCMF_PCIE_SHARED_TXPUSH_SUPPORT) {
+- brcmf_err("Unsupported legacy TX mode 0x%x\n",
+- shared->flags & BRCMF_PCIE_SHARED_TXPUSH_SUPPORT);
+- return -EINVAL;
++
++ /* check firmware support dma indicies */
++ if (shared->flags & BRCMF_PCIE_SHARED_DMA_INDEX) {
++ if (shared->flags & BRCMF_PCIE_SHARED_DMA_2B_IDX)
++ devinfo->dma_idx_sz = sizeof(u16);
++ else
++ devinfo->dma_idx_sz = sizeof(u32);
+ }
+
+ addr = sharedram_addr + BRCMF_SHARED_MAX_RXBUFPOST_OFFSET;
+@@ -1609,7 +1691,7 @@
+ bus->msgbuf->commonrings[i] =
+ &devinfo->shared.commonrings[i]->commonring;
+
+- flowrings = kcalloc(devinfo->shared.nrof_flowrings, sizeof(flowrings),
++ flowrings = kcalloc(devinfo->shared.nrof_flowrings, sizeof(*flowrings),
+ GFP_KERNEL);
+ if (!flowrings)
+ goto fail;
+@@ -1641,8 +1723,13 @@
+ struct brcmf_pciedev_info *devinfo;
+ struct brcmf_pciedev *pcie_bus_dev;
+ struct brcmf_bus *bus;
++ u16 domain_nr;
++ u16 bus_nr;
+
+- brcmf_dbg(PCIE, "Enter %x:%x\n", pdev->vendor, pdev->device);
++ domain_nr = pci_domain_nr(pdev->bus) + 1;
++ bus_nr = pdev->bus->number;
++ brcmf_dbg(PCIE, "Enter %x:%x (%d/%d)\n", pdev->vendor, pdev->device,
++ domain_nr, bus_nr);
+
+ ret = -ENOMEM;
+ devinfo = kzalloc(sizeof(*devinfo), GFP_KERNEL);
+@@ -1691,10 +1778,10 @@
+ if (ret)
+ goto fail_bus;
+
+- ret = brcmf_fw_get_firmwares(bus->dev, BRCMF_FW_REQUEST_NVRAM |
+- BRCMF_FW_REQ_NV_OPTIONAL,
+- devinfo->fw_name, devinfo->nvram_name,
+- brcmf_pcie_setup);
++ ret = brcmf_fw_get_firmwares_pcie(bus->dev, BRCMF_FW_REQUEST_NVRAM |
++ BRCMF_FW_REQ_NV_OPTIONAL,
++ devinfo->fw_name, devinfo->nvram_name,
++ brcmf_pcie_setup, domain_nr, bus_nr);
+ if (ret == 0)
+ return 0;
+ fail_bus:
+diff -Nur linux-4.1.3/drivers/net/wireless/brcm80211/brcmfmac/sdio.c linux-xbian-imx6/drivers/net/wireless/brcm80211/brcmfmac/sdio.c
+--- linux-4.1.3/drivers/net/wireless/brcm80211/brcmfmac/sdio.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/drivers/net/wireless/brcm80211/brcmfmac/sdio.c 2015-07-27 23:13:06.872462130 +0200
+@@ -3550,10 +3550,6 @@
+ return;
+ }
+
+- if (bus->sdiodev->state != BRCMF_SDIOD_DATA) {
+- brcmf_err("bus is down. we have nothing to do\n");
+- return;
+- }
+ /* Count the interrupt call */
+ bus->sdcnt.intrcount++;
+ if (in_interrupt())
+diff -Nur linux-4.1.3/drivers/net/wireless/brcm80211/brcmfmac/usb.c linux-xbian-imx6/drivers/net/wireless/brcm80211/brcmfmac/usb.c
+--- linux-4.1.3/drivers/net/wireless/brcm80211/brcmfmac/usb.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/drivers/net/wireless/brcm80211/brcmfmac/usb.c 2015-07-27 23:13:06.872462130 +0200
+@@ -1270,8 +1270,13 @@
+ bus->chiprev = bus_pub->chiprev;
+
+ /* request firmware here */
+- brcmf_fw_get_firmwares(dev, 0, brcmf_usb_get_fwname(devinfo), NULL,
+- brcmf_usb_probe_phase2);
++ ret = brcmf_fw_get_firmwares(dev, 0, brcmf_usb_get_fwname(devinfo),
++ NULL, brcmf_usb_probe_phase2);
++ if (ret) {
++ brcmf_err("firmware request failed: %d\n", ret);
++ goto fail;
++ }
++
+ return 0;
+
+ fail:
+diff -Nur linux-4.1.3/drivers/spi/spi-imx.c linux-xbian-imx6/drivers/spi/spi-imx.c
+--- linux-4.1.3/drivers/spi/spi-imx.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/drivers/spi/spi-imx.c 2015-07-27 23:13:07.837020693 +0200
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
++ * Copyright 2004-2007, 2015 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2008 Juergen Beisert
+ *
+ * This program is free software; you can redistribute it and/or
+@@ -53,10 +53,14 @@
+ /* generic defines to abstract from the different register layouts */
+ #define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */
+ #define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */
++#define MXC_INT_TCEN (1 << 7) /* Transfer complete */
+
+ /* The maximum bytes that a sdma BD can transfer.*/
+ #define MAX_SDMA_BD_BYTES (1 << 15)
+-#define IMX_DMA_TIMEOUT (msecs_to_jiffies(3000))
++/* 3 Sec for 1MB or less than 1MB, else change with the transfer length */
++#define IMX_DEFAULT_DMA_TIMEOUT (msecs_to_jiffies(3000))
++#define IMX_DMA_TIMEOUT(len) ((len < 0x100000) ? IMX_DEFAULT_DMA_TIMEOUT : \
++ len * IMX_DEFAULT_DMA_TIMEOUT / 0x100000)
+ struct spi_imx_config {
+ unsigned int speed_hz;
+ unsigned int bpw;
+@@ -102,18 +106,23 @@
+
+ /* DMA */
+ unsigned int dma_is_inited;
+- unsigned int dma_finished;
+ bool usedma;
+ u32 rx_wml;
+ u32 tx_wml;
+ u32 rxt_wml;
+ struct completion dma_rx_completion;
+ struct completion dma_tx_completion;
++ struct dma_slave_config rx_config;
++ struct dma_slave_config tx_config;
+
+ const struct spi_imx_devtype_data *devtype_data;
+ int chipselect[0];
+ };
+
++static struct spi_board_info info = {
++ .modalias = "spidev",
++};
++
+ static inline int is_imx27_cspi(struct spi_imx_data *d)
+ {
+ return d->devtype_data->devtype == IMX27_CSPI;
+@@ -201,8 +210,9 @@
+ {
+ struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
+
+- if (spi_imx->dma_is_inited && (transfer->len > spi_imx->rx_wml)
+- && (transfer->len > spi_imx->tx_wml))
++ if (spi_imx->dma_is_inited &&
++ (transfer->len > spi_imx_get_fifosize(spi_imx)) &&
++ (transfer->len > spi_imx_get_fifosize(spi_imx)))
+ return true;
+ return false;
+ }
+@@ -227,6 +237,7 @@
+ #define MX51_ECSPI_INT 0x10
+ #define MX51_ECSPI_INT_TEEN (1 << 0)
+ #define MX51_ECSPI_INT_RREN (1 << 3)
++#define MX51_ECSPI_INT_TCEN (1 << 7)
+
+ #define MX51_ECSPI_DMA 0x14
+ #define MX51_ECSPI_DMA_TX_WML_OFFSET 0
+@@ -291,17 +302,21 @@
+ if (enable & MXC_INT_RR)
+ val |= MX51_ECSPI_INT_RREN;
+
++ if (enable & MXC_INT_TCEN)
++ val |= MX51_ECSPI_INT_TCEN;
++
+ writel(val, spi_imx->base + MX51_ECSPI_INT);
+ }
+
+ static void __maybe_unused mx51_ecspi_trigger(struct spi_imx_data *spi_imx)
+ {
+ u32 reg = readl(spi_imx->base + MX51_ECSPI_CTRL);
+-
++ /*
++ * To workaround TKT238285, SDMA script need use XCH instead of SMC
++ * just like PIO mode.
++ */
+ if (!spi_imx->usedma)
+ reg |= MX51_ECSPI_CTRL_XCH;
+- else if (!spi_imx->dma_finished)
+- reg |= MX51_ECSPI_CTRL_SMC;
+ else
+ reg &= ~MX51_ECSPI_CTRL_SMC;
+ writel(reg, spi_imx->base + MX51_ECSPI_CTRL);
+@@ -311,7 +326,6 @@
+ struct spi_imx_config *config)
+ {
+ u32 ctrl = MX51_ECSPI_CTRL_ENABLE, cfg = 0, dma = 0;
+- u32 tx_wml_cfg, rx_wml_cfg, rxt_wml_cfg;
+ u32 clk = config->speed_hz, delay;
+
+ /*
+@@ -368,20 +382,10 @@
+ * and enable DMA request.
+ */
+ if (spi_imx->dma_is_inited) {
+- dma = readl(spi_imx->base + MX51_ECSPI_DMA);
+-
+- spi_imx->rxt_wml = spi_imx_get_fifosize(spi_imx) / 2;
+- rx_wml_cfg = spi_imx->rx_wml << MX51_ECSPI_DMA_RX_WML_OFFSET;
+- tx_wml_cfg = spi_imx->tx_wml << MX51_ECSPI_DMA_TX_WML_OFFSET;
+- rxt_wml_cfg = spi_imx->rxt_wml << MX51_ECSPI_DMA_RXT_WML_OFFSET;
+- dma = (dma & ~MX51_ECSPI_DMA_TX_WML_MASK
+- & ~MX51_ECSPI_DMA_RX_WML_MASK
+- & ~MX51_ECSPI_DMA_RXT_WML_MASK)
+- | rx_wml_cfg | tx_wml_cfg | rxt_wml_cfg
+- |(1 << MX51_ECSPI_DMA_TEDEN_OFFSET)
+- |(1 << MX51_ECSPI_DMA_RXDEN_OFFSET)
+- |(1 << MX51_ECSPI_DMA_RXTDEN_OFFSET);
+-
++ spi_imx->rx_wml = spi_imx_get_fifosize(spi_imx) / 2;
++ dma = (spi_imx->rx_wml - 1) << MX51_ECSPI_DMA_RX_WML_OFFSET
++ | (1 << MX51_ECSPI_DMA_TEDEN_OFFSET)
++ | (1 << MX51_ECSPI_DMA_RXDEN_OFFSET);
+ writel(dma, spi_imx->base + MX51_ECSPI_DMA);
+ }
+
+@@ -768,6 +772,7 @@
+ {
+ struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
+ struct spi_imx_config config;
++ int ret;
+
+ config.bpw = t ? t->bits_per_word : spi->bits_per_word;
+ config.speed_hz = t ? t->speed_hz : spi->max_speed_hz;
+@@ -783,12 +788,35 @@
+ if (config.bpw <= 8) {
+ spi_imx->rx = spi_imx_buf_rx_u8;
+ spi_imx->tx = spi_imx_buf_tx_u8;
++ spi_imx->tx_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
++ spi_imx->rx_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
+ } else if (config.bpw <= 16) {
+ spi_imx->rx = spi_imx_buf_rx_u16;
+ spi_imx->tx = spi_imx_buf_tx_u16;
++ spi_imx->tx_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
++ spi_imx->rx_config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
+ } else {
+ spi_imx->rx = spi_imx_buf_rx_u32;
+ spi_imx->tx = spi_imx_buf_tx_u32;
++ spi_imx->tx_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
++ spi_imx->rx_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
++ }
++
++ if (spi_imx->bitbang.master->can_dma &&
++ spi_imx_can_dma(spi_imx->bitbang.master, spi, t)) {
++ ret = dmaengine_slave_config(spi_imx->bitbang.master->dma_tx,
++ &spi_imx->tx_config);
++ if (ret) {
++ dev_err(&spi->dev, "error in TX dma configuration.\n");
++ return ret;
++ }
++
++ ret = dmaengine_slave_config(spi_imx->bitbang.master->dma_rx,
++ &spi_imx->rx_config);
++ if (ret) {
++ dev_err(&spi->dev, "error in RX dma configuration.\n");
++ return ret;
++ }
+ }
+
+ spi_imx->devtype_data->config(spi_imx, &config);
+@@ -817,7 +845,6 @@
+ struct spi_master *master,
+ const struct resource *res)
+ {
+- struct dma_slave_config slave_config = {};
+ int ret;
+
+ /* use pio mode for i.mx6dl chip TKT238285 */
+@@ -832,11 +859,11 @@
+ goto err;
+ }
+
+- slave_config.direction = DMA_MEM_TO_DEV;
+- slave_config.dst_addr = res->start + MXC_CSPITXDATA;
+- slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
+- slave_config.dst_maxburst = spi_imx_get_fifosize(spi_imx) / 2;
+- ret = dmaengine_slave_config(master->dma_tx, &slave_config);
++ spi_imx->tx_config.direction = DMA_MEM_TO_DEV;
++ spi_imx->tx_config.dst_addr = res->start + MXC_CSPITXDATA;
++ spi_imx->tx_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
++ spi_imx->tx_config.dst_maxburst = spi_imx_get_fifosize(spi_imx) / 4;
++ ret = dmaengine_slave_config(master->dma_tx, &spi_imx->tx_config);
+ if (ret) {
+ dev_err(dev, "error in TX dma configuration.\n");
+ goto err;
+@@ -850,11 +877,11 @@
+ goto err;
+ }
+
+- slave_config.direction = DMA_DEV_TO_MEM;
+- slave_config.src_addr = res->start + MXC_CSPIRXDATA;
+- slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
+- slave_config.src_maxburst = spi_imx_get_fifosize(spi_imx) / 2;
+- ret = dmaengine_slave_config(master->dma_rx, &slave_config);
++ spi_imx->rx_config.direction = DMA_DEV_TO_MEM;
++ spi_imx->rx_config.src_addr = res->start + MXC_CSPIRXDATA;
++ spi_imx->rx_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
++ spi_imx->rx_config.src_maxburst = spi_imx_get_fifosize(spi_imx) / 2;
++ ret = dmaengine_slave_config(master->dma_rx, &spi_imx->rx_config);
+ if (ret) {
+ dev_err(dev, "error in RX dma configuration.\n");
+ goto err;
+@@ -890,14 +917,33 @@
+ complete(&spi_imx->dma_tx_completion);
+ }
+
++static void spi_imx_tail_pio_set(struct spi_imx_data *spi_imx, int left)
++{
++
++ switch (spi_imx->rx_config.src_addr_width) {
++ case DMA_SLAVE_BUSWIDTH_1_BYTE:
++ spi_imx->rx = spi_imx_buf_rx_u8;
++ break;
++ case DMA_SLAVE_BUSWIDTH_2_BYTES:
++ spi_imx->rx = spi_imx_buf_rx_u16;
++ break;
++ case DMA_SLAVE_BUSWIDTH_4_BYTES:
++ spi_imx->rx = spi_imx_buf_rx_u32;
++ break;
++ default:
++ spi_imx->rx = spi_imx_buf_rx_u8;
++ break;
++ }
++
++ spi_imx->txfifo = left / spi_imx->tx_config.dst_addr_width;
++}
++
+ static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx,
+ struct spi_transfer *transfer)
+ {
+ struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL;
+ int ret;
+- unsigned long timeout;
+- u32 dma;
+- int left;
++ int left = 0;
+ struct spi_master *master = spi_imx->bitbang.master;
+ struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg;
+
+@@ -914,6 +960,18 @@
+ }
+
+ if (rx) {
++ struct scatterlist *sgl_last = &rx->sgl[rx->nents - 1];
++ unsigned int orig_length = sgl_last->length;
++ int wml_mask = ~(spi_imx->rx_wml - 1);
++ /*
++ * Adjust the transfer lenth of the last scattlist if there are
++ * some tail data, use PIO read to get the tail data since DMA
++ * sometimes miss the last tail interrupt.
++ */
++ left = transfer->len % spi_imx->rx_wml;
++ if (left)
++ sgl_last->length = orig_length & wml_mask;
++
+ desc_rx = dmaengine_prep_slave_sg(master->dma_rx,
+ rx->sgl, rx->nents, DMA_DEV_TO_MEM,
+ DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+@@ -929,46 +987,50 @@
+ reinit_completion(&spi_imx->dma_tx_completion);
+
+ /* Trigger the cspi module. */
+- spi_imx->dma_finished = 0;
+-
+- dma = readl(spi_imx->base + MX51_ECSPI_DMA);
+- dma = dma & (~MX51_ECSPI_DMA_RXT_WML_MASK);
+- /* Change RX_DMA_LENGTH trigger dma fetch tail data */
+- left = transfer->len % spi_imx->rxt_wml;
+- if (left)
+- writel(dma | (left << MX51_ECSPI_DMA_RXT_WML_OFFSET),
+- spi_imx->base + MX51_ECSPI_DMA);
+ spi_imx->devtype_data->trigger(spi_imx);
+
+ dma_async_issue_pending(master->dma_tx);
+ dma_async_issue_pending(master->dma_rx);
+ /* Wait SDMA to finish the data transfer.*/
+- timeout = wait_for_completion_timeout(&spi_imx->dma_tx_completion,
+- IMX_DMA_TIMEOUT);
+- if (!timeout) {
+- pr_warn("%s %s: I/O Error in DMA TX\n",
++ ret = wait_for_completion_timeout(&spi_imx->dma_tx_completion,
++ IMX_DMA_TIMEOUT(transfer->len));
++ if (!ret) {
++ pr_warn("%s %s: I/O Error in DMA TX:%x\n",
+ dev_driver_string(&master->dev),
+- dev_name(&master->dev));
++ dev_name(&master->dev), transfer->len);
+ dmaengine_terminate_all(master->dma_tx);
+ } else {
+- timeout = wait_for_completion_timeout(
+- &spi_imx->dma_rx_completion, IMX_DMA_TIMEOUT);
+- if (!timeout) {
+- pr_warn("%s %s: I/O Error in DMA RX\n",
++ ret = wait_for_completion_timeout(&spi_imx->dma_rx_completion,
++ IMX_DMA_TIMEOUT(transfer->len));
++ if (!ret) {
++ pr_warn("%s %s: I/O Error in DMA RX:%x\n",
+ dev_driver_string(&master->dev),
+- dev_name(&master->dev));
++ dev_name(&master->dev), transfer->len);
+ spi_imx->devtype_data->reset(spi_imx);
+ dmaengine_terminate_all(master->dma_rx);
++ } else if (left) {
++ /* read the tail data by PIO */
++ dma_sync_sg_for_cpu(master->dma_rx->device->dev,
++ &rx->sgl[rx->nents - 1], 1,
++ DMA_FROM_DEVICE);
++ spi_imx->rx_buf = transfer->rx_buf
++ + (transfer->len - left);
++ spi_imx_tail_pio_set(spi_imx, left);
++ reinit_completion(&spi_imx->xfer_done);
++
++ spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TCEN);
++
++ ret = wait_for_completion_timeout(&spi_imx->xfer_done,
++ IMX_DMA_TIMEOUT(transfer->len));
++ if (!ret) {
++ pr_warn("%s %s: I/O Error in RX tail\n",
++ dev_driver_string(&master->dev),
++ dev_name(&master->dev));
++ }
+ }
+- writel(dma |
+- spi_imx->rxt_wml << MX51_ECSPI_DMA_RXT_WML_OFFSET,
+- spi_imx->base + MX51_ECSPI_DMA);
+ }
+
+- spi_imx->dma_finished = 1;
+- spi_imx->devtype_data->trigger(spi_imx);
+-
+- if (!timeout)
++ if (!ret)
+ ret = -ETIMEDOUT;
+ else
+ ret = transfer->len;
+@@ -1013,6 +1075,7 @@
+ spi_imx_can_dma(spi_imx->bitbang.master, spi, transfer)) {
+ spi_imx->usedma = true;
+ ret = spi_imx_dma_transfer(spi_imx, transfer);
++ spi_imx->usedma = false; /* clear the dma flag */
+ if (ret != -EAGAIN)
+ return ret;
+ }
+@@ -1200,6 +1263,7 @@
+ goto out_clk_put;
+ }
+
++ spi_new_device(master, &info);
+ dev_info(&pdev->dev, "probed\n");
+
+ clk_disable(spi_imx->clk_ipg);
+diff -Nur linux-4.1.3/drivers/video/fbdev/core/fbmon.c linux-xbian-imx6/drivers/video/fbdev/core/fbmon.c
+--- linux-4.1.3/drivers/video/fbdev/core/fbmon.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/drivers/video/fbdev/core/fbmon.c 2015-07-27 23:13:08.674034323 +0200
+@@ -494,7 +494,7 @@
+ static int get_std_timing(unsigned char *block, struct fb_videomode *mode,
+ int ver, int rev, const struct fb_monspecs *specs)
+ {
+- int i;
++ int xres, yres = 0, ratio, i;
+
+ for (i = 0; i < DMT_SIZE; i++) {
+ u32 std_2byte_code = block[0] << 8 | block[1];
+@@ -502,6 +502,32 @@
+ break;
+ }
+
++ ratio = (block[1] & 0xc0) >> 6;
++ switch (ratio) {
++ case 0:
++ /* in EDID 1.3 the meaning of 0 changed to 16:10 (prior 1:1) */
++ if (ver < 1 || (ver == 1 && rev < 3)) {
++ yres = xres;
++ mode->vmode &= FB_VMODE_ASPECT_1;
++ } else {
++ yres = (xres * 10)/16;
++ mode->vmode &= FB_VMODE_ASPECT_16_10;
++ }
++ break;
++ case 1:
++ yres = (xres * 3)/4;
++ mode->vmode &= FB_VMODE_ASPECT_4_3;
++ break;
++ case 2:
++ yres = (xres * 4)/5;
++ mode->vmode &= FB_VMODE_ASPECT_5_4;
++ break;
++ case 3:
++ yres = (xres * 9)/16;
++ mode->vmode &= FB_VMODE_ASPECT_16_9;
++ break;
++ }
++
+ if (i < DMT_SIZE && dmt_modes[i].mode) {
+ /* DMT mode found */
+ *mode = *dmt_modes[i].mode;
+diff -Nur linux-4.1.3/drivers/video/fbdev/core/fbsysfs.c linux-xbian-imx6/drivers/video/fbdev/core/fbsysfs.c
+--- linux-4.1.3/drivers/video/fbdev/core/fbsysfs.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/drivers/video/fbdev/core/fbsysfs.c 2015-07-27 23:13:08.674034323 +0200
+@@ -20,6 +20,7 @@
+ #include <linux/fb.h>
+ #include <linux/console.h>
+ #include <linux/module.h>
++#include <linux/ctype.h>
+
+ #define FB_SYSFS_FLAG_ATTR 1
+
+@@ -119,7 +120,15 @@
+ v = 'i';
+ if (mode->vmode & FB_VMODE_DOUBLE)
+ v = 'd';
++ if (mode->vmode & FB_VMODE_3D_SBS_HALF)
++ m = 'H';
++ if (mode->vmode & FB_VMODE_3D_TOP_BOTTOM)
++ m = 'T';
++ if (mode->vmode & FB_VMODE_3D_FRAME_PACK)
++ m = 'F';
+
++ if (mode->vmode & FB_VMODE_FRACTIONAL)
++ m = tolower(m);
+ return snprintf(&buf[offset], PAGE_SIZE - offset, "%c:%dx%d%c-%d\n",
+ m, mode->xres, mode->yres, v, mode->refresh);
+ }
+diff -Nur linux-4.1.3/drivers/video/Kconfig linux-xbian-imx6/drivers/video/Kconfig
+--- linux-4.1.3/drivers/video/Kconfig 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/drivers/video/Kconfig 2015-07-27 23:13:08.626204974 +0200
+@@ -30,6 +30,8 @@
+ source "drivers/video/fbdev/Kconfig"
+ endmenu
+
++source "drivers/video/mxc/Kconfig"
++
+ source "drivers/video/backlight/Kconfig"
+
+ config VGASTATE
+diff -Nur linux-4.1.3/drivers/video/Makefile linux-xbian-imx6/drivers/video/Makefile
+--- linux-4.1.3/drivers/video/Makefile 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/drivers/video/Makefile 2015-07-27 23:13:08.626204974 +0200
+@@ -6,6 +6,7 @@
+ obj-y += backlight/
+
+ obj-y += fbdev/
++obj-y += mxc/
+
+ obj-$(CONFIG_VIDEOMODE_HELPERS) += display_timing.o videomode.o
+ ifeq ($(CONFIG_OF),y)
+diff -Nur linux-4.1.3/drivers/video/mxc/Kconfig linux-xbian-imx6/drivers/video/mxc/Kconfig
+--- linux-4.1.3/drivers/video/mxc/Kconfig 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/video/mxc/Kconfig 2015-07-27 23:13:08.749764128 +0200
+@@ -0,0 +1,55 @@
++config FB_MXC
++ tristate "MXC Framebuffer support"
++ depends on FB
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ select FB_MODE_HELPERS
++ default y
++ help
++ This is a framebuffer device for the MXC LCD Controller.
++ See <http://www.linux-fbdev.org/> for information on framebuffer
++ devices.
++
++ If you plan to use the LCD display with your MXC system, say
++ Y here.
++
++config FB_MXC_SYNC_PANEL
++ depends on FB_MXC
++ tristate "Synchronous Panel Framebuffer"
++
++config FB_MXC_LDB
++ tristate "MXC LDB"
++ depends on FB_MXC_SYNC_PANEL
++ depends on MXC_IPU_V3_FSL || IMX_IPUV3_CORE
++
++config FB_MXC_MIPI_DSI
++ tristate "MXC MIPI_DSI"
++ depends on FB_MXC_SYNC_PANEL
++ depends on MXC_IPU_V3_FSL || IMX_IPUV3_CORE
++
++config FB_MXC_TRULY_WVGA_SYNC_PANEL
++ tristate "TRULY WVGA Panel"
++ depends on FB_MXC_SYNC_PANEL
++ depends on FB_MXC_MIPI_DSI
++
++config FB_MXC_HDMI
++ depends on FB_MXC_SYNC_PANEL
++ depends on MXC_IPU_V3_FSL || IMX_IPUV3_CORE
++ depends on I2C
++ tristate "MXC HDMI driver support"
++ select MFD_MXC_HDMI
++ select HDMI
++ help
++ Driver for the on-chip MXC HDMI controller.
++
++config FB_MXC_DCIC
++ tristate "MXC DCIC"
++ depends on FB_MXC_SYNC_PANEL
++ depends on MXC_IPU_V3_FSL || FB_MXS
++ select VIDEOMODE_HELPERS
++
++config FB_MXC_EDID
++ depends on FB_MXC && I2C
++ tristate "MXC EDID support"
++ default y
+diff -Nur linux-4.1.3/drivers/video/mxc/ldb.c linux-xbian-imx6/drivers/video/mxc/ldb.c
+--- linux-4.1.3/drivers/video/mxc/ldb.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/video/mxc/ldb.c 2015-07-27 23:13:08.749764128 +0200
+@@ -0,0 +1,1036 @@
++/*
++ * Copyright (C) 2012-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++/*!
++ * @file mxc_ldb.c
++ *
++ * @brief This file contains the LDB driver device interface and fops
++ * functions.
++ */
++#include <linux/types.h>
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/err.h>
++#include <linux/clk.h>
++#include <linux/console.h>
++#include <linux/io.h>
++#include <linux/ipu.h>
++#include <linux/mxcfb.h>
++#include <linux/regulator/consumer.h>
++#include <linux/spinlock.h>
++#include <linux/of_device.h>
++#include <linux/mod_devicetable.h>
++#include "mxc_dispdrv.h"
++
++#define DISPDRV_LDB "ldb"
++
++#define LDB_BGREF_RMODE_MASK 0x00008000
++#define LDB_BGREF_RMODE_INT 0x00008000
++#define LDB_BGREF_RMODE_EXT 0x0
++
++#define LDB_DI1_VS_POL_MASK 0x00000400
++#define LDB_DI1_VS_POL_ACT_LOW 0x00000400
++#define LDB_DI1_VS_POL_ACT_HIGH 0x0
++#define LDB_DI0_VS_POL_MASK 0x00000200
++#define LDB_DI0_VS_POL_ACT_LOW 0x00000200
++#define LDB_DI0_VS_POL_ACT_HIGH 0x0
++
++#define LDB_BIT_MAP_CH1_MASK 0x00000100
++#define LDB_BIT_MAP_CH1_JEIDA 0x00000100
++#define LDB_BIT_MAP_CH1_SPWG 0x0
++#define LDB_BIT_MAP_CH0_MASK 0x00000040
++#define LDB_BIT_MAP_CH0_JEIDA 0x00000040
++#define LDB_BIT_MAP_CH0_SPWG 0x0
++
++#define LDB_DATA_WIDTH_CH1_MASK 0x00000080
++#define LDB_DATA_WIDTH_CH1_24 0x00000080
++#define LDB_DATA_WIDTH_CH1_18 0x0
++#define LDB_DATA_WIDTH_CH0_MASK 0x00000020
++#define LDB_DATA_WIDTH_CH0_24 0x00000020
++#define LDB_DATA_WIDTH_CH0_18 0x0
++
++#define LDB_CH1_MODE_MASK 0x0000000C
++#define LDB_CH1_MODE_EN_TO_DI1 0x0000000C
++#define LDB_CH1_MODE_EN_TO_DI0 0x00000004
++#define LDB_CH1_MODE_DISABLE 0x0
++#define LDB_CH0_MODE_MASK 0x00000003
++#define LDB_CH0_MODE_EN_TO_DI1 0x00000003
++#define LDB_CH0_MODE_EN_TO_DI0 0x00000001
++#define LDB_CH0_MODE_DISABLE 0x0
++
++#define LDB_SPLIT_MODE_EN 0x00000010
++
++enum {
++ IMX6_LDB,
++};
++
++enum {
++ LDB_IMX6 = 1,
++};
++
++struct fsl_mxc_ldb_platform_data {
++ int devtype;
++ u32 ext_ref;
++#define LDB_SPL_DI0 1
++#define LDB_SPL_DI1 2
++#define LDB_DUL_DI0 3
++#define LDB_DUL_DI1 4
++#define LDB_SIN0 5
++#define LDB_SIN1 6
++#define LDB_SEP0 7
++#define LDB_SEP1 8
++ int mode;
++ int ipu_id;
++ int disp_id;
++
++ /*only work for separate mode*/
++ int sec_ipu_id;
++ int sec_disp_id;
++};
++
++struct ldb_data {
++ struct platform_device *pdev;
++ struct mxc_dispdrv_handle *disp_ldb;
++ uint32_t *reg;
++ uint32_t *control_reg;
++ uint32_t *gpr3_reg;
++ uint32_t control_reg_data;
++ struct regulator *lvds_bg_reg;
++ int mode;
++ bool inited;
++ struct ldb_setting {
++ struct clk *di_clk;
++ struct clk *ldb_di_clk;
++ struct clk *div_3_5_clk;
++ struct clk *div_7_clk;
++ struct clk *div_sel_clk;
++ bool active;
++ bool clk_en;
++ int ipu;
++ int di;
++ uint32_t ch_mask;
++ uint32_t ch_val;
++ } setting[2];
++ struct notifier_block nb;
++};
++
++static int g_ldb_mode;
++
++static struct fb_videomode ldb_modedb[] = {
++ {
++ "LDB-WXGA", 60, 1280, 800, 14065,
++ 40, 40,
++ 10, 3,
++ 80, 10,
++ 0,
++ FB_VMODE_NONINTERLACED,
++ FB_MODE_IS_DETAILED,},
++ {
++ "LDB-XGA", 60, 1024, 768, 15385,
++ 220, 40,
++ 21, 7,
++ 60, 10,
++ 0,
++ FB_VMODE_NONINTERLACED,
++ FB_MODE_IS_DETAILED,},
++ {
++ "LDB-1080P60", 60, 1920, 1080, 7692,
++ 100, 40,
++ 30, 3,
++ 10, 2,
++ 0,
++ FB_VMODE_NONINTERLACED,
++ FB_MODE_IS_DETAILED,},
++};
++static int ldb_modedb_sz = ARRAY_SIZE(ldb_modedb);
++
++static inline int is_imx6_ldb(struct fsl_mxc_ldb_platform_data *plat_data)
++{
++ return (plat_data->devtype == LDB_IMX6);
++}
++
++static int bits_per_pixel(int pixel_fmt)
++{
++ switch (pixel_fmt) {
++ case IPU_PIX_FMT_BGR24:
++ case IPU_PIX_FMT_RGB24:
++ return 24;
++ break;
++ case IPU_PIX_FMT_BGR666:
++ case IPU_PIX_FMT_RGB666:
++ case IPU_PIX_FMT_LVDS666:
++ return 18;
++ break;
++ default:
++ break;
++ }
++ return 0;
++}
++
++static int valid_mode(int pixel_fmt)
++{
++ return ((pixel_fmt == IPU_PIX_FMT_RGB24) ||
++ (pixel_fmt == IPU_PIX_FMT_BGR24) ||
++ (pixel_fmt == IPU_PIX_FMT_LVDS666) ||
++ (pixel_fmt == IPU_PIX_FMT_RGB666) ||
++ (pixel_fmt == IPU_PIX_FMT_BGR666));
++}
++
++static int parse_ldb_mode(char *mode)
++{
++ int ldb_mode;
++
++ if (!strcmp(mode, "spl0"))
++ ldb_mode = LDB_SPL_DI0;
++ else if (!strcmp(mode, "spl1"))
++ ldb_mode = LDB_SPL_DI1;
++ else if (!strcmp(mode, "dul0"))
++ ldb_mode = LDB_DUL_DI0;
++ else if (!strcmp(mode, "dul1"))
++ ldb_mode = LDB_DUL_DI1;
++ else if (!strcmp(mode, "sin0"))
++ ldb_mode = LDB_SIN0;
++ else if (!strcmp(mode, "sin1"))
++ ldb_mode = LDB_SIN1;
++ else if (!strcmp(mode, "sep0"))
++ ldb_mode = LDB_SEP0;
++ else if (!strcmp(mode, "sep1"))
++ ldb_mode = LDB_SEP1;
++ else
++ ldb_mode = -EINVAL;
++
++ return ldb_mode;
++}
++
++#ifndef MODULE
++/*
++ * "ldb=spl0/1" -- split mode on DI0/1
++ * "ldb=dul0/1" -- dual mode on DI0/1
++ * "ldb=sin0/1" -- single mode on LVDS0/1
++ * "ldb=sep0/1" -- separate mode begin from LVDS0/1
++ *
++ * there are two LVDS channels(LVDS0 and LVDS1) which can transfer video
++ * datas, there two channels can be used as split/dual/single/separate mode.
++ *
++ * split mode means display data from DI0 or DI1 will send to both channels
++ * LVDS0+LVDS1.
++ * dual mode means display data from DI0 or DI1 will be duplicated on LVDS0
++ * and LVDS1, it said, LVDS0 and LVDS1 has the same content.
++ * single mode means only work for DI0/DI1->LVDS0 or DI0/DI1->LVDS1.
++ * separate mode means you can make DI0/DI1->LVDS0 and DI0/DI1->LVDS1 work
++ * at the same time.
++ */
++static int __init ldb_setup(char *options)
++{
++ g_ldb_mode = parse_ldb_mode(options);
++ return (g_ldb_mode < 0) ? 0 : 1;
++}
++__setup("ldb=", ldb_setup);
++#endif
++
++static int ldb_get_of_property(struct platform_device *pdev,
++ struct fsl_mxc_ldb_platform_data *plat_data)
++{
++ struct device_node *np = pdev->dev.of_node;
++ int err;
++ u32 ipu_id, disp_id;
++ u32 sec_ipu_id, sec_disp_id;
++ char *mode;
++ u32 ext_ref;
++
++ err = of_property_read_string(np, "mode", (const char **)&mode);
++ if (err) {
++ dev_dbg(&pdev->dev, "get of property mode fail\n");
++ return err;
++ }
++ err = of_property_read_u32(np, "ext_ref", &ext_ref);
++ if (err) {
++ dev_dbg(&pdev->dev, "get of property ext_ref fail\n");
++ return err;
++ }
++ err = of_property_read_u32(np, "ipu_id", &ipu_id);
++ if (err) {
++ dev_dbg(&pdev->dev, "get of property ipu_id fail\n");
++ return err;
++ }
++ err = of_property_read_u32(np, "disp_id", &disp_id);
++ if (err) {
++ dev_dbg(&pdev->dev, "get of property disp_id fail\n");
++ return err;
++ }
++ err = of_property_read_u32(np, "sec_ipu_id", &sec_ipu_id);
++ if (err) {
++ dev_dbg(&pdev->dev, "get of property sec_ipu_id fail\n");
++ return err;
++ }
++ err = of_property_read_u32(np, "sec_disp_id", &sec_disp_id);
++ if (err) {
++ dev_dbg(&pdev->dev, "get of property sec_disp_id fail\n");
++ return err;
++ }
++
++ plat_data->mode = parse_ldb_mode(mode);
++ plat_data->ext_ref = ext_ref;
++ plat_data->ipu_id = ipu_id;
++ plat_data->disp_id = disp_id;
++ plat_data->sec_ipu_id = sec_ipu_id;
++ plat_data->sec_disp_id = sec_disp_id;
++
++ return err;
++}
++
++static int find_ldb_setting(struct ldb_data *ldb, struct fb_info *fbi)
++{
++ char *id_di[] = {
++ "DISP3 BG",
++ "DISP3 BG - DI1",
++ };
++ char id[16];
++ int i;
++
++ for (i = 0; i < 2; i++) {
++ if (ldb->setting[i].active) {
++ memset(id, 0, 16);
++ memcpy(id, id_di[ldb->setting[i].di],
++ strlen(id_di[ldb->setting[i].di]));
++ id[4] += ldb->setting[i].ipu;
++ if (!strcmp(id, fbi->fix.id))
++ return i;
++ }
++ }
++ return -EINVAL;
++}
++
++static int ldb_disp_setup(struct mxc_dispdrv_handle *disp, struct fb_info *fbi)
++{
++ uint32_t reg, val;
++ uint32_t pixel_clk, rounded_pixel_clk;
++ struct clk *ldb_clk_parent;
++ struct ldb_data *ldb = mxc_dispdrv_getdata(disp);
++ int setting_idx, di;
++ int ret;
++
++ setting_idx = find_ldb_setting(ldb, fbi);
++ if (setting_idx < 0)
++ return setting_idx;
++
++ di = ldb->setting[setting_idx].di;
++
++ /* restore channel mode setting */
++ val = readl(ldb->control_reg);
++ val |= ldb->setting[setting_idx].ch_val;
++ writel(val, ldb->control_reg);
++ dev_dbg(&ldb->pdev->dev, "LDB setup, control reg:0x%x\n",
++ readl(ldb->control_reg));
++
++ /* vsync setup */
++ reg = readl(ldb->control_reg);
++ if (fbi->var.sync & FB_SYNC_VERT_HIGH_ACT) {
++ if (di == 0)
++ reg = (reg & ~LDB_DI0_VS_POL_MASK)
++ | LDB_DI0_VS_POL_ACT_HIGH;
++ else
++ reg = (reg & ~LDB_DI1_VS_POL_MASK)
++ | LDB_DI1_VS_POL_ACT_HIGH;
++ } else {
++ if (di == 0)
++ reg = (reg & ~LDB_DI0_VS_POL_MASK)
++ | LDB_DI0_VS_POL_ACT_LOW;
++ else
++ reg = (reg & ~LDB_DI1_VS_POL_MASK)
++ | LDB_DI1_VS_POL_ACT_LOW;
++ }
++ writel(reg, ldb->control_reg);
++
++ /* clk setup */
++ if (ldb->setting[setting_idx].clk_en)
++ clk_disable_unprepare(ldb->setting[setting_idx].ldb_di_clk);
++ pixel_clk = (PICOS2KHZ(fbi->var.pixclock)) * 1000UL;
++ ldb_clk_parent = clk_get_parent(ldb->setting[setting_idx].ldb_di_clk);
++ if (IS_ERR(ldb_clk_parent)) {
++ dev_err(&ldb->pdev->dev, "get ldb di parent clk fail\n");
++ return PTR_ERR(ldb_clk_parent);
++ }
++ if ((ldb->mode == LDB_SPL_DI0) || (ldb->mode == LDB_SPL_DI1))
++ ret = clk_set_rate(ldb_clk_parent, pixel_clk * 7 / 2);
++ else
++ ret = clk_set_rate(ldb_clk_parent, pixel_clk * 7);
++ if (ret < 0) {
++ dev_err(&ldb->pdev->dev, "set ldb parent clk fail:%d\n", ret);
++ return ret;
++ }
++ rounded_pixel_clk = clk_round_rate(ldb->setting[setting_idx].ldb_di_clk,
++ pixel_clk);
++ dev_dbg(&ldb->pdev->dev, "pixel_clk:%d, rounded_pixel_clk:%d\n",
++ pixel_clk, rounded_pixel_clk);
++ ret = clk_set_rate(ldb->setting[setting_idx].ldb_di_clk,
++ rounded_pixel_clk);
++ if (ret < 0) {
++ dev_err(&ldb->pdev->dev, "set ldb di clk fail:%d\n", ret);
++ return ret;
++ }
++ ret = clk_prepare_enable(ldb->setting[setting_idx].ldb_di_clk);
++ if (ret < 0) {
++ dev_err(&ldb->pdev->dev, "enable ldb di clk fail:%d\n", ret);
++ return ret;
++ }
++
++ if (!ldb->setting[setting_idx].clk_en)
++ ldb->setting[setting_idx].clk_en = true;
++
++ return 0;
++}
++
++int ldb_fb_event(struct notifier_block *nb, unsigned long val, void *v)
++{
++ struct ldb_data *ldb = container_of(nb, struct ldb_data, nb);
++ struct fb_event *event = v;
++ struct fb_info *fbi = event->info;
++ int index;
++ uint32_t data;
++
++ index = find_ldb_setting(ldb, fbi);
++ if (index < 0)
++ return 0;
++
++ fbi->mode = (struct fb_videomode *)fb_match_mode(&fbi->var,
++ &fbi->modelist);
++
++ if (!fbi->mode) {
++ dev_warn(&ldb->pdev->dev,
++ "LDB: can not find mode for xres=%d, yres=%d\n",
++ fbi->var.xres, fbi->var.yres);
++ if (ldb->setting[index].clk_en) {
++ clk_disable(ldb->setting[index].ldb_di_clk);
++ ldb->setting[index].clk_en = false;
++ data = readl(ldb->control_reg);
++ data &= ~ldb->setting[index].ch_mask;
++ writel(data, ldb->control_reg);
++ }
++ return 0;
++ }
++
++ switch (val) {
++ case FB_EVENT_BLANK:
++ {
++ if (*((int *)event->data) == FB_BLANK_UNBLANK) {
++ if (!ldb->setting[index].clk_en) {
++ clk_enable(ldb->setting[index].ldb_di_clk);
++ ldb->setting[index].clk_en = true;
++ }
++ } else {
++ if (ldb->setting[index].clk_en) {
++ clk_disable(ldb->setting[index].ldb_di_clk);
++ ldb->setting[index].clk_en = false;
++ data = readl(ldb->control_reg);
++ data &= ~ldb->setting[index].ch_mask;
++ writel(data, ldb->control_reg);
++ dev_dbg(&ldb->pdev->dev,
++ "LDB blank, control reg:0x%x\n",
++ readl(ldb->control_reg));
++ }
++ }
++ break;
++ }
++ case FB_EVENT_SUSPEND:
++ if (ldb->setting[index].clk_en) {
++ clk_disable(ldb->setting[index].ldb_di_clk);
++ ldb->setting[index].clk_en = false;
++ }
++ break;
++ default:
++ break;
++ }
++ return 0;
++}
++
++#define LVDS_MUX_CTL_WIDTH 2
++#define LVDS_MUX_CTL_MASK 3
++#define LVDS0_MUX_CTL_OFFS 6
++#define LVDS1_MUX_CTL_OFFS 8
++#define LVDS0_MUX_CTL_MASK (LVDS_MUX_CTL_MASK << 6)
++#define LVDS1_MUX_CTL_MASK (LVDS_MUX_CTL_MASK << 8)
++#define ROUTE_IPU_DI(ipu, di) (((ipu << 1) | di) & LVDS_MUX_CTL_MASK)
++static int ldb_ipu_ldb_route(int ipu, int di, struct ldb_data *ldb)
++{
++ uint32_t reg;
++ int channel;
++ int shift;
++ int mode = ldb->mode;
++
++ reg = readl(ldb->gpr3_reg);
++ if (mode < LDB_SIN0) {
++ reg &= ~(LVDS0_MUX_CTL_MASK | LVDS1_MUX_CTL_MASK);
++ reg |= (ROUTE_IPU_DI(ipu, di) << LVDS0_MUX_CTL_OFFS) |
++ (ROUTE_IPU_DI(ipu, di) << LVDS1_MUX_CTL_OFFS);
++ dev_dbg(&ldb->pdev->dev,
++ "Dual/Split mode both channels route to IPU%d-DI%d\n",
++ ipu, di);
++ } else if ((mode == LDB_SIN0) || (mode == LDB_SIN1)) {
++ reg &= ~(LVDS0_MUX_CTL_MASK | LVDS1_MUX_CTL_MASK);
++ channel = mode - LDB_SIN0;
++ shift = LVDS0_MUX_CTL_OFFS + channel * LVDS_MUX_CTL_WIDTH;
++ reg |= ROUTE_IPU_DI(ipu, di) << shift;
++ dev_dbg(&ldb->pdev->dev,
++ "Single mode channel %d route to IPU%d-DI%d\n",
++ channel, ipu, di);
++ } else {
++ static bool first = true;
++
++ if (first) {
++ if (mode == LDB_SEP0) {
++ reg &= ~LVDS0_MUX_CTL_MASK;
++ channel = 0;
++ } else {
++ reg &= ~LVDS1_MUX_CTL_MASK;
++ channel = 1;
++ }
++ first = false;
++ } else {
++ if (mode == LDB_SEP0) {
++ reg &= ~LVDS1_MUX_CTL_MASK;
++ channel = 1;
++ } else {
++ reg &= ~LVDS0_MUX_CTL_MASK;
++ channel = 0;
++ }
++ }
++
++ shift = LVDS0_MUX_CTL_OFFS + channel * LVDS_MUX_CTL_WIDTH;
++ reg |= ROUTE_IPU_DI(ipu, di) << shift;
++
++ dev_dbg(&ldb->pdev->dev,
++ "Separate mode channel %d route to IPU%d-DI%d\n",
++ channel, ipu, di);
++ }
++ writel(reg, ldb->gpr3_reg);
++
++ return 0;
++}
++
++static int ldb_disp_init(struct mxc_dispdrv_handle *disp,
++ struct mxc_dispdrv_setting *setting)
++{
++ int ret = 0, i, lvds_channel = 0;
++ struct ldb_data *ldb = mxc_dispdrv_getdata(disp);
++ struct fsl_mxc_ldb_platform_data *plat_data = ldb->pdev->dev.platform_data;
++ struct resource *res;
++ uint32_t reg, setting_idx;
++ uint32_t ch_mask = 0, ch_val = 0;
++ uint32_t ipu_id, disp_id;
++ char di_clk[] = "ipu1_di0_sel";
++ char ldb_clk[] = "ldb_di0";
++ char div_3_5_clk[] = "di0_div_3_5";
++ char div_7_clk[] = "di0_div_7";
++ char div_sel_clk[] = "di0_div_sel";
++
++ /* if input format not valid, make RGB666 as default*/
++ if (!valid_mode(setting->if_fmt)) {
++ dev_warn(&ldb->pdev->dev, "Input pixel format not valid"
++ " use default RGB666\n");
++ setting->if_fmt = IPU_PIX_FMT_RGB666;
++ }
++
++ if (!ldb->inited) {
++ setting_idx = 0;
++ res = platform_get_resource(ldb->pdev, IORESOURCE_MEM, 0);
++ if (!res) {
++ dev_err(&ldb->pdev->dev, "get iomem fail.\n");
++ return -ENOMEM;
++ }
++
++ ldb->reg = devm_ioremap(&ldb->pdev->dev, res->start,
++ resource_size(res));
++ ldb->control_reg = ldb->reg + 2;
++ ldb->gpr3_reg = ldb->reg + 3;
++
++ /* ipu selected by platform data setting */
++ setting->dev_id = plat_data->ipu_id;
++
++ reg = readl(ldb->control_reg);
++
++ /* refrence resistor select */
++ reg &= ~LDB_BGREF_RMODE_MASK;
++ if (plat_data->ext_ref)
++ reg |= LDB_BGREF_RMODE_EXT;
++ else
++ reg |= LDB_BGREF_RMODE_INT;
++
++ /* TODO: now only use SPWG data mapping for both channel */
++ reg &= ~(LDB_BIT_MAP_CH0_MASK | LDB_BIT_MAP_CH1_MASK);
++ reg |= LDB_BIT_MAP_CH0_SPWG | LDB_BIT_MAP_CH1_SPWG;
++
++ /* channel mode setting */
++ reg &= ~(LDB_CH0_MODE_MASK | LDB_CH1_MODE_MASK);
++ reg &= ~(LDB_DATA_WIDTH_CH0_MASK | LDB_DATA_WIDTH_CH1_MASK);
++
++ if (bits_per_pixel(setting->if_fmt) == 24)
++ reg |= LDB_DATA_WIDTH_CH0_24 | LDB_DATA_WIDTH_CH1_24;
++ else
++ reg |= LDB_DATA_WIDTH_CH0_18 | LDB_DATA_WIDTH_CH1_18;
++
++ if (g_ldb_mode >= LDB_SPL_DI0)
++ ldb->mode = g_ldb_mode;
++ else
++ ldb->mode = plat_data->mode;
++
++ if ((ldb->mode == LDB_SIN0) || (ldb->mode == LDB_SIN1)) {
++ ret = ldb->mode - LDB_SIN0;
++ if (plat_data->disp_id != ret) {
++ dev_warn(&ldb->pdev->dev,
++ "change IPU DI%d to IPU DI%d for LDB "
++ "channel%d.\n",
++ plat_data->disp_id, ret, ret);
++ plat_data->disp_id = ret;
++ }
++ } else if (((ldb->mode == LDB_SEP0) || (ldb->mode == LDB_SEP1))
++ && is_imx6_ldb(plat_data)) {
++ if (plat_data->disp_id == plat_data->sec_disp_id) {
++ dev_err(&ldb->pdev->dev,
++ "For LVDS separate mode,"
++ "two DIs should be different!\n");
++ return -EINVAL;
++ }
++
++ if (((!plat_data->disp_id) && (ldb->mode == LDB_SEP1))
++ || ((plat_data->disp_id) &&
++ (ldb->mode == LDB_SEP0))) {
++ dev_dbg(&ldb->pdev->dev,
++ "LVDS separate mode:"
++ "swap DI configuration!\n");
++ ipu_id = plat_data->ipu_id;
++ disp_id = plat_data->disp_id;
++ plat_data->ipu_id = plat_data->sec_ipu_id;
++ plat_data->disp_id = plat_data->sec_disp_id;
++ plat_data->sec_ipu_id = ipu_id;
++ plat_data->sec_disp_id = disp_id;
++ }
++ }
++
++ if (ldb->mode == LDB_SPL_DI0) {
++ reg |= LDB_SPLIT_MODE_EN | LDB_CH0_MODE_EN_TO_DI0
++ | LDB_CH1_MODE_EN_TO_DI0;
++ setting->disp_id = 0;
++ } else if (ldb->mode == LDB_SPL_DI1) {
++ reg |= LDB_SPLIT_MODE_EN | LDB_CH0_MODE_EN_TO_DI1
++ | LDB_CH1_MODE_EN_TO_DI1;
++ setting->disp_id = 1;
++ } else if (ldb->mode == LDB_DUL_DI0) {
++ reg &= ~LDB_SPLIT_MODE_EN;
++ reg |= LDB_CH0_MODE_EN_TO_DI0 | LDB_CH1_MODE_EN_TO_DI0;
++ setting->disp_id = 0;
++ } else if (ldb->mode == LDB_DUL_DI1) {
++ reg &= ~LDB_SPLIT_MODE_EN;
++ reg |= LDB_CH0_MODE_EN_TO_DI1 | LDB_CH1_MODE_EN_TO_DI1;
++ setting->disp_id = 1;
++ } else if (ldb->mode == LDB_SIN0) {
++ reg &= ~LDB_SPLIT_MODE_EN;
++ setting->disp_id = plat_data->disp_id;
++ if (setting->disp_id == 0)
++ reg |= LDB_CH0_MODE_EN_TO_DI0;
++ else
++ reg |= LDB_CH0_MODE_EN_TO_DI1;
++ ch_mask = LDB_CH0_MODE_MASK;
++ ch_val = reg & LDB_CH0_MODE_MASK;
++ } else if (ldb->mode == LDB_SIN1) {
++ reg &= ~LDB_SPLIT_MODE_EN;
++ setting->disp_id = plat_data->disp_id;
++ if (setting->disp_id == 0)
++ reg |= LDB_CH1_MODE_EN_TO_DI0;
++ else
++ reg |= LDB_CH1_MODE_EN_TO_DI1;
++ ch_mask = LDB_CH1_MODE_MASK;
++ ch_val = reg & LDB_CH1_MODE_MASK;
++ } else { /* separate mode*/
++ setting->disp_id = plat_data->disp_id;
++
++ /* first output is LVDS0 or LVDS1 */
++ if (ldb->mode == LDB_SEP0)
++ lvds_channel = 0;
++ else
++ lvds_channel = 1;
++
++ reg &= ~LDB_SPLIT_MODE_EN;
++
++ if ((lvds_channel == 0) && (setting->disp_id == 0))
++ reg |= LDB_CH0_MODE_EN_TO_DI0;
++ else if ((lvds_channel == 0) && (setting->disp_id == 1))
++ reg |= LDB_CH0_MODE_EN_TO_DI1;
++ else if ((lvds_channel == 1) && (setting->disp_id == 0))
++ reg |= LDB_CH1_MODE_EN_TO_DI0;
++ else
++ reg |= LDB_CH1_MODE_EN_TO_DI1;
++ ch_mask = lvds_channel ? LDB_CH1_MODE_MASK :
++ LDB_CH0_MODE_MASK;
++ ch_val = reg & ch_mask;
++
++ if (bits_per_pixel(setting->if_fmt) == 24) {
++ if (lvds_channel == 0)
++ reg &= ~LDB_DATA_WIDTH_CH1_24;
++ else
++ reg &= ~LDB_DATA_WIDTH_CH0_24;
++ } else {
++ if (lvds_channel == 0)
++ reg &= ~LDB_DATA_WIDTH_CH1_18;
++ else
++ reg &= ~LDB_DATA_WIDTH_CH0_18;
++ }
++ }
++
++ writel(reg, ldb->control_reg);
++ if (ldb->mode < LDB_SIN0) {
++ ch_mask = LDB_CH0_MODE_MASK | LDB_CH1_MODE_MASK;
++ ch_val = reg & (LDB_CH0_MODE_MASK | LDB_CH1_MODE_MASK);
++ }
++ } else { /* second time for separate mode */
++ if ((ldb->mode == LDB_SPL_DI0) ||
++ (ldb->mode == LDB_SPL_DI1) ||
++ (ldb->mode == LDB_DUL_DI0) ||
++ (ldb->mode == LDB_DUL_DI1) ||
++ (ldb->mode == LDB_SIN0) ||
++ (ldb->mode == LDB_SIN1)) {
++ dev_err(&ldb->pdev->dev, "for second ldb disp"
++ "ldb mode should in separate mode\n");
++ return -EINVAL;
++ }
++
++ setting_idx = 1;
++ if (is_imx6_ldb(plat_data)) {
++ setting->dev_id = plat_data->sec_ipu_id;
++ setting->disp_id = plat_data->sec_disp_id;
++ } else {
++ setting->dev_id = plat_data->ipu_id;
++ setting->disp_id = !plat_data->disp_id;
++ }
++ if (setting->disp_id == ldb->setting[0].di) {
++ dev_err(&ldb->pdev->dev, "Err: for second ldb disp in"
++ "separate mode, DI should be different!\n");
++ return -EINVAL;
++ }
++
++ /* second output is LVDS0 or LVDS1 */
++ if (ldb->mode == LDB_SEP0)
++ lvds_channel = 1;
++ else
++ lvds_channel = 0;
++
++ reg = readl(ldb->control_reg);
++ if ((lvds_channel == 0) && (setting->disp_id == 0))
++ reg |= LDB_CH0_MODE_EN_TO_DI0;
++ else if ((lvds_channel == 0) && (setting->disp_id == 1))
++ reg |= LDB_CH0_MODE_EN_TO_DI1;
++ else if ((lvds_channel == 1) && (setting->disp_id == 0))
++ reg |= LDB_CH1_MODE_EN_TO_DI0;
++ else
++ reg |= LDB_CH1_MODE_EN_TO_DI1;
++ ch_mask = lvds_channel ? LDB_CH1_MODE_MASK :
++ LDB_CH0_MODE_MASK;
++ ch_val = reg & ch_mask;
++
++ if (bits_per_pixel(setting->if_fmt) == 24) {
++ if (lvds_channel == 0)
++ reg |= LDB_DATA_WIDTH_CH0_24;
++ else
++ reg |= LDB_DATA_WIDTH_CH1_24;
++ } else {
++ if (lvds_channel == 0)
++ reg |= LDB_DATA_WIDTH_CH0_18;
++ else
++ reg |= LDB_DATA_WIDTH_CH1_18;
++ }
++ writel(reg, ldb->control_reg);
++ }
++
++ /* get clocks */
++ if (is_imx6_ldb(plat_data) &&
++ ((ldb->mode == LDB_SEP0) || (ldb->mode == LDB_SEP1))) {
++ ldb_clk[6] += lvds_channel;
++ div_3_5_clk[2] += lvds_channel;
++ div_7_clk[2] += lvds_channel;
++ div_sel_clk[2] += lvds_channel;
++ } else {
++ ldb_clk[6] += setting->disp_id;
++ div_3_5_clk[2] += setting->disp_id;
++ div_7_clk[2] += setting->disp_id;
++ div_sel_clk[2] += setting->disp_id;
++ }
++ ldb->setting[setting_idx].ldb_di_clk = clk_get(&ldb->pdev->dev,
++ ldb_clk);
++ if (IS_ERR(ldb->setting[setting_idx].ldb_di_clk)) {
++ dev_err(&ldb->pdev->dev, "get ldb clk failed\n");
++ return PTR_ERR(ldb->setting[setting_idx].ldb_di_clk);
++ }
++
++ ldb->setting[setting_idx].div_3_5_clk = clk_get(&ldb->pdev->dev,
++ div_3_5_clk);
++ if (IS_ERR(ldb->setting[setting_idx].div_3_5_clk)) {
++ dev_err(&ldb->pdev->dev, "get div 3.5 clk failed\n");
++ return PTR_ERR(ldb->setting[setting_idx].div_3_5_clk);
++ }
++ ldb->setting[setting_idx].div_7_clk = clk_get(&ldb->pdev->dev,
++ div_7_clk);
++ if (IS_ERR(ldb->setting[setting_idx].div_7_clk)) {
++ dev_err(&ldb->pdev->dev, "get div 7 clk failed\n");
++ return PTR_ERR(ldb->setting[setting_idx].div_7_clk);
++ }
++
++ ldb->setting[setting_idx].div_sel_clk = clk_get(&ldb->pdev->dev,
++ div_sel_clk);
++ if (IS_ERR(ldb->setting[setting_idx].div_sel_clk)) {
++ dev_err(&ldb->pdev->dev, "get div sel clk failed\n");
++ return PTR_ERR(ldb->setting[setting_idx].div_sel_clk);
++ }
++
++ di_clk[3] += setting->dev_id;
++ di_clk[7] += setting->disp_id;
++ ldb->setting[setting_idx].di_clk = clk_get(&ldb->pdev->dev,
++ di_clk);
++ if (IS_ERR(ldb->setting[setting_idx].di_clk)) {
++ dev_err(&ldb->pdev->dev, "get di clk failed\n");
++ return PTR_ERR(ldb->setting[setting_idx].di_clk);
++ }
++
++ ldb->setting[setting_idx].ch_mask = ch_mask;
++ ldb->setting[setting_idx].ch_val = ch_val;
++
++ if (is_imx6_ldb(plat_data))
++ ldb_ipu_ldb_route(setting->dev_id, setting->disp_id, ldb);
++
++ /* must use spec video mode defined by driver */
++ ret = fb_find_mode(&setting->fbi->var, setting->fbi, setting->dft_mode_str,
++ ldb_modedb, ldb_modedb_sz, NULL, setting->default_bpp);
++ if (ret != 1)
++ fb_videomode_to_var(&setting->fbi->var, &ldb_modedb[0]);
++
++ INIT_LIST_HEAD(&setting->fbi->modelist);
++ for (i = 0; i < ldb_modedb_sz; i++) {
++ struct fb_videomode m;
++ fb_var_to_videomode(&m, &setting->fbi->var);
++ if (fb_mode_is_equal(&m, &ldb_modedb[i])) {
++ fb_add_videomode(&ldb_modedb[i],
++ &setting->fbi->modelist);
++ break;
++ }
++ }
++
++ ldb->setting[setting_idx].ipu = setting->dev_id;
++ ldb->setting[setting_idx].di = setting->disp_id;
++
++ return ret;
++}
++
++static int ldb_post_disp_init(struct mxc_dispdrv_handle *disp,
++ int ipu_id, int disp_id)
++{
++ struct ldb_data *ldb = mxc_dispdrv_getdata(disp);
++ int setting_idx = ldb->inited ? 1 : 0;
++ int ret = 0;
++
++ if (!ldb->inited) {
++ ldb->nb.notifier_call = ldb_fb_event;
++ fb_register_client(&ldb->nb);
++ }
++
++ ret = clk_set_parent(ldb->setting[setting_idx].di_clk,
++ ldb->setting[setting_idx].ldb_di_clk);
++ if (ret) {
++ dev_err(&ldb->pdev->dev, "fail to set ldb_di clk as"
++ "the parent of ipu_di clk\n");
++ return ret;
++ }
++
++ if ((ldb->mode == LDB_SPL_DI0) || (ldb->mode == LDB_SPL_DI1)) {
++ ret = clk_set_parent(ldb->setting[setting_idx].div_sel_clk,
++ ldb->setting[setting_idx].div_3_5_clk);
++ if (ret) {
++ dev_err(&ldb->pdev->dev, "fail to set div 3.5 clk as"
++ "the parent of div sel clk\n");
++ return ret;
++ }
++ } else {
++ ret = clk_set_parent(ldb->setting[setting_idx].div_sel_clk,
++ ldb->setting[setting_idx].div_7_clk);
++ if (ret) {
++ dev_err(&ldb->pdev->dev, "fail to set div 7 clk as"
++ "the parent of div sel clk\n");
++ return ret;
++ }
++ }
++
++ /* save active ldb setting for fb notifier */
++ ldb->setting[setting_idx].active = true;
++
++ ldb->inited = true;
++ return ret;
++}
++
++static void ldb_disp_deinit(struct mxc_dispdrv_handle *disp)
++{
++ struct ldb_data *ldb = mxc_dispdrv_getdata(disp);
++ int i;
++
++ writel(0, ldb->control_reg);
++
++ for (i = 0; i < 2; i++) {
++ clk_disable(ldb->setting[i].ldb_di_clk);
++ clk_put(ldb->setting[i].ldb_di_clk);
++ clk_put(ldb->setting[i].div_3_5_clk);
++ clk_put(ldb->setting[i].div_7_clk);
++ clk_put(ldb->setting[i].div_sel_clk);
++ }
++
++ fb_unregister_client(&ldb->nb);
++}
++
++static struct mxc_dispdrv_driver ldb_drv = {
++ .name = DISPDRV_LDB,
++ .init = ldb_disp_init,
++ .post_init = ldb_post_disp_init,
++ .deinit = ldb_disp_deinit,
++ .setup = ldb_disp_setup,
++};
++
++static int ldb_suspend(struct platform_device *pdev, pm_message_t state)
++{
++ struct ldb_data *ldb = dev_get_drvdata(&pdev->dev);
++ uint32_t data;
++
++ if (!ldb->inited)
++ return 0;
++ data = readl(ldb->control_reg);
++ ldb->control_reg_data = data;
++ data &= ~(LDB_CH0_MODE_MASK | LDB_CH1_MODE_MASK);
++ writel(data, ldb->control_reg);
++
++ return 0;
++}
++
++static int ldb_resume(struct platform_device *pdev)
++{
++ struct ldb_data *ldb = dev_get_drvdata(&pdev->dev);
++
++ if (!ldb->inited)
++ return 0;
++ writel(ldb->control_reg_data, ldb->control_reg);
++
++ return 0;
++}
++
++static struct platform_device_id imx_ldb_devtype[] = {
++ {
++ .name = "ldb-imx6",
++ .driver_data = LDB_IMX6,
++ }, {
++ /* sentinel */
++ }
++};
++
++static const struct of_device_id imx_ldb_dt_ids[] = {
++ { .compatible = "fsl,imx6q-ldb", .data = &imx_ldb_devtype[IMX6_LDB],},
++ { /* sentinel */ }
++};
++
++/*!
++ * This function is called by the driver framework to initialize the LDB
++ * device.
++ *
++ * @param dev The device structure for the LDB passed in by the
++ * driver framework.
++ *
++ * @return Returns 0 on success or negative error code on error
++ */
++static int ldb_probe(struct platform_device *pdev)
++{
++ int ret = 0;
++ struct ldb_data *ldb;
++ struct fsl_mxc_ldb_platform_data *plat_data;
++ const struct of_device_id *of_id =
++ of_match_device(imx_ldb_dt_ids, &pdev->dev);
++
++ dev_dbg(&pdev->dev, "%s enter\n", __func__);
++ ldb = devm_kzalloc(&pdev->dev, sizeof(struct ldb_data), GFP_KERNEL);
++ if (!ldb)
++ return -ENOMEM;
++
++ plat_data = devm_kzalloc(&pdev->dev,
++ sizeof(struct fsl_mxc_ldb_platform_data),
++ GFP_KERNEL);
++ if (!plat_data)
++ return -ENOMEM;
++ pdev->dev.platform_data = plat_data;
++ if (of_id)
++ pdev->id_entry = of_id->data;
++ plat_data->devtype = pdev->id_entry->driver_data;
++
++ ret = ldb_get_of_property(pdev, plat_data);
++ if (ret < 0) {
++ dev_err(&pdev->dev, "get ldb of property fail\n");
++ return ret;
++ }
++
++ ldb->pdev = pdev;
++ ldb->disp_ldb = mxc_dispdrv_register(&ldb_drv);
++ mxc_dispdrv_setdata(ldb->disp_ldb, ldb);
++
++ dev_set_drvdata(&pdev->dev, ldb);
++
++ dev_dbg(&pdev->dev, "%s exit\n", __func__);
++ return ret;
++}
++
++static int ldb_remove(struct platform_device *pdev)
++{
++ struct ldb_data *ldb = dev_get_drvdata(&pdev->dev);
++
++ if (!ldb->inited)
++ return 0;
++ mxc_dispdrv_puthandle(ldb->disp_ldb);
++ mxc_dispdrv_unregister(ldb->disp_ldb);
++ return 0;
++}
++
++static struct platform_driver mxcldb_driver = {
++ .driver = {
++ .name = "mxc_ldb",
++ .of_match_table = imx_ldb_dt_ids,
++ },
++ .probe = ldb_probe,
++ .remove = ldb_remove,
++ .suspend = ldb_suspend,
++ .resume = ldb_resume,
++};
++
++static int __init ldb_init(void)
++{
++ return platform_driver_register(&mxcldb_driver);
++}
++
++static void __exit ldb_uninit(void)
++{
++ platform_driver_unregister(&mxcldb_driver);
++}
++
++module_init(ldb_init);
++module_exit(ldb_uninit);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("MXC LDB driver");
++MODULE_LICENSE("GPL");
+diff -Nur linux-4.1.3/drivers/video/mxc/Makefile linux-xbian-imx6/drivers/video/mxc/Makefile
+--- linux-4.1.3/drivers/video/mxc/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/video/mxc/Makefile 2015-07-27 23:13:08.749764128 +0200
+@@ -0,0 +1,7 @@
++obj-$(CONFIG_FB_MXC_LDB) += ldb.o
++obj-$(CONFIG_FB_MXC_MIPI_DSI) += mipi_dsi.o
++obj-$(CONFIG_FB_MXC_TRULY_WVGA_SYNC_PANEL) += mxcfb_hx8369_wvga.o
++obj-$(CONFIG_FB_MXC_HDMI) += mxc_hdmi.o
++obj-$(CONFIG_FB_MXC_EDID) += mxc_edid.o
++obj-$(CONFIG_FB_MXC_SYNC_PANEL) += mxc_dispdrv.o mxc_lcdif.o mxc_ipuv3_fb.o
++obj-$(CONFIG_FB_MXC_DCIC) += mxc_dcic.o
+diff -Nur linux-4.1.3/drivers/video/mxc/mipi_dsi.c linux-xbian-imx6/drivers/video/mxc/mipi_dsi.c
+--- linux-4.1.3/drivers/video/mxc/mipi_dsi.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/video/mxc/mipi_dsi.c 2015-07-27 23:13:08.749764128 +0200
+@@ -0,0 +1,953 @@
++/*
++ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++#include <linux/types.h>
++#include <linux/init.h>
++#include <linux/platform_device.h>
++#include <linux/err.h>
++#include <linux/clk.h>
++#include <linux/console.h>
++#include <linux/io.h>
++#include <linux/bitops.h>
++#include <linux/ipu.h>
++#include <linux/mfd/syscon.h>
++#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
++#include <linux/mipi_dsi.h>
++#include <linux/module.h>
++#include <linux/mxcfb.h>
++#include <linux/backlight.h>
++#include <linux/of_device.h>
++#include <linux/regulator/consumer.h>
++#include <linux/reset.h>
++#include <linux/spinlock.h>
++#include <linux/delay.h>
++#include <video/mipi_display.h>
++
++#include "mxc_dispdrv.h"
++#include "mipi_dsi.h"
++
++#define DISPDRV_MIPI "mipi_dsi"
++#define ROUND_UP(x) ((x)+1)
++#define NS2PS_RATIO (1000)
++#define NUMBER_OF_CHUNKS (0x8)
++#define NULL_PKT_SIZE (0x8)
++#define PHY_BTA_MAXTIME (0xd00)
++#define PHY_LP2HS_MAXTIME (0x40)
++#define PHY_HS2LP_MAXTIME (0x40)
++#define PHY_STOP_WAIT_TIME (0x20)
++#define DSI_CLKMGR_CFG_CLK_DIV (0x107)
++#define DSI_GEN_PLD_DATA_BUF_ENTRY (0x10)
++#define MIPI_MUX_CTRL(v) (((v) & 0x3) << 4)
++#define MIPI_LCD_SLEEP_MODE_DELAY (120)
++#define MIPI_DSI_REG_RW_TIMEOUT (20)
++#define MIPI_DSI_PHY_TIMEOUT (10)
++
++static struct mipi_dsi_match_lcd mipi_dsi_lcd_db[] = {
++#ifdef CONFIG_FB_MXC_TRULY_WVGA_SYNC_PANEL
++ {
++ "TRULY-WVGA",
++ {mipid_hx8369_get_lcd_videomode, mipid_hx8369_lcd_setup}
++ },
++#endif
++ {
++ "", {NULL, NULL}
++ }
++};
++
++struct _mipi_dsi_phy_pll_clk {
++ u32 max_phy_clk;
++ u32 config;
++};
++
++/* configure data for DPHY PLL 27M reference clk out */
++static const struct _mipi_dsi_phy_pll_clk mipi_dsi_phy_pll_clk_table[] = {
++ {1000, 0x74}, /* 950-1000MHz */
++ {950, 0x54}, /* 900-950Mhz */
++ {900, 0x34}, /* 850-900Mhz */
++ {850, 0x14}, /* 800-850MHz */
++ {800, 0x32}, /* 750-800MHz */
++ {750, 0x12}, /* 700-750Mhz */
++ {700, 0x30}, /* 650-700Mhz */
++ {650, 0x10}, /* 600-650MHz */
++ {600, 0x2e}, /* 550-600MHz */
++ {550, 0x0e}, /* 500-550Mhz */
++ {500, 0x2c}, /* 450-500Mhz */
++ {450, 0x0c}, /* 400-450MHz */
++ {400, 0x4a}, /* 360-400MHz */
++ {360, 0x2a}, /* 330-360Mhz */
++ {330, 0x48}, /* 300-330Mhz */
++ {300, 0x28}, /* 270-300MHz */
++ {270, 0x08}, /* 250-270MHz */
++ {250, 0x46}, /* 240-250Mhz */
++ {240, 0x26}, /* 210-240Mhz */
++ {210, 0x06}, /* 200-210MHz */
++ {200, 0x44}, /* 180-200MHz */
++ {180, 0x24}, /* 160-180MHz */
++ {160, 0x04}, /* 150-160MHz */
++};
++
++static int valid_mode(int pixel_fmt)
++{
++ return ((pixel_fmt == IPU_PIX_FMT_RGB24) ||
++ (pixel_fmt == IPU_PIX_FMT_BGR24) ||
++ (pixel_fmt == IPU_PIX_FMT_RGB666) ||
++ (pixel_fmt == IPU_PIX_FMT_RGB565) ||
++ (pixel_fmt == IPU_PIX_FMT_BGR666) ||
++ (pixel_fmt == IPU_PIX_FMT_RGB332));
++}
++
++static inline void mipi_dsi_read_register(struct mipi_dsi_info *mipi_dsi,
++ u32 reg, u32 *val)
++{
++ *val = ioread32(mipi_dsi->mmio_base + reg);
++ dev_dbg(&mipi_dsi->pdev->dev, "read_reg:0x%02x, val:0x%08x.\n",
++ reg, *val);
++}
++
++static inline void mipi_dsi_write_register(struct mipi_dsi_info *mipi_dsi,
++ u32 reg, u32 val)
++{
++ iowrite32(val, mipi_dsi->mmio_base + reg);
++ dev_dbg(&mipi_dsi->pdev->dev, "\t\twrite_reg:0x%02x, val:0x%08x.\n",
++ reg, val);
++}
++
++int mipi_dsi_pkt_write(struct mipi_dsi_info *mipi_dsi,
++ u8 data_type, const u32 *buf, int len)
++{
++ u32 val;
++ u32 status = 0;
++ int write_len = len;
++ uint32_t timeout = 0;
++
++ if (len) {
++ /* generic long write command */
++ while (len / DSI_GEN_PLD_DATA_BUF_SIZE) {
++ mipi_dsi_write_register(mipi_dsi,
++ MIPI_DSI_GEN_PLD_DATA, *buf);
++ buf++;
++ len -= DSI_GEN_PLD_DATA_BUF_SIZE;
++ mipi_dsi_read_register(mipi_dsi,
++ MIPI_DSI_CMD_PKT_STATUS, &status);
++ while ((status & DSI_CMD_PKT_STATUS_GEN_PLD_W_FULL) ==
++ DSI_CMD_PKT_STATUS_GEN_PLD_W_FULL) {
++ msleep(1);
++ timeout++;
++ if (timeout == MIPI_DSI_REG_RW_TIMEOUT)
++ return -EIO;
++ mipi_dsi_read_register(mipi_dsi,
++ MIPI_DSI_CMD_PKT_STATUS, &status);
++ }
++ }
++ /* write the remainder bytes */
++ if (len > 0) {
++ while ((status & DSI_CMD_PKT_STATUS_GEN_PLD_W_FULL) ==
++ DSI_CMD_PKT_STATUS_GEN_PLD_W_FULL) {
++ msleep(1);
++ timeout++;
++ if (timeout == MIPI_DSI_REG_RW_TIMEOUT)
++ return -EIO;
++ mipi_dsi_read_register(mipi_dsi,
++ MIPI_DSI_CMD_PKT_STATUS, &status);
++ }
++ mipi_dsi_write_register(mipi_dsi,
++ MIPI_DSI_GEN_PLD_DATA, *buf);
++ }
++
++ val = data_type | ((write_len & DSI_GEN_HDR_DATA_MASK)
++ << DSI_GEN_HDR_DATA_SHIFT);
++ } else {
++ /* generic short write command */
++ val = data_type | ((*buf & DSI_GEN_HDR_DATA_MASK)
++ << DSI_GEN_HDR_DATA_SHIFT);
++ }
++
++ mipi_dsi_read_register(mipi_dsi, MIPI_DSI_CMD_PKT_STATUS, &status);
++ while ((status & DSI_CMD_PKT_STATUS_GEN_CMD_FULL) ==
++ DSI_CMD_PKT_STATUS_GEN_CMD_FULL) {
++ msleep(1);
++ timeout++;
++ if (timeout == MIPI_DSI_REG_RW_TIMEOUT)
++ return -EIO;
++ mipi_dsi_read_register(mipi_dsi, MIPI_DSI_CMD_PKT_STATUS,
++ &status);
++ }
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_GEN_HDR, val);
++
++ mipi_dsi_read_register(mipi_dsi, MIPI_DSI_CMD_PKT_STATUS, &status);
++ while (!((status & DSI_CMD_PKT_STATUS_GEN_CMD_EMPTY) ==
++ DSI_CMD_PKT_STATUS_GEN_CMD_EMPTY) ||
++ !((status & DSI_CMD_PKT_STATUS_GEN_PLD_W_EMPTY) ==
++ DSI_CMD_PKT_STATUS_GEN_PLD_W_EMPTY)) {
++ msleep(1);
++ timeout++;
++ if (timeout == MIPI_DSI_REG_RW_TIMEOUT)
++ return -EIO;
++ mipi_dsi_read_register(mipi_dsi, MIPI_DSI_CMD_PKT_STATUS,
++ &status);
++ }
++
++ return 0;
++}
++
++int mipi_dsi_pkt_read(struct mipi_dsi_info *mipi_dsi,
++ u8 data_type, u32 *buf, int len)
++{
++ u32 val;
++ int read_len = 0;
++ uint32_t timeout = 0;
++
++ if (!len) {
++ mipi_dbg("%s, len = 0 invalid error!\n", __func__);
++ return -EINVAL;
++ }
++
++ val = data_type | ((*buf & DSI_GEN_HDR_DATA_MASK)
++ << DSI_GEN_HDR_DATA_SHIFT);
++ memset(buf, 0, len);
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_GEN_HDR, val);
++
++ /* wait for cmd to sent out */
++ mipi_dsi_read_register(mipi_dsi, MIPI_DSI_CMD_PKT_STATUS, &val);
++ while ((val & DSI_CMD_PKT_STATUS_GEN_RD_CMD_BUSY) !=
++ DSI_CMD_PKT_STATUS_GEN_RD_CMD_BUSY) {
++ msleep(1);
++ timeout++;
++ if (timeout == MIPI_DSI_REG_RW_TIMEOUT)
++ return -EIO;
++ mipi_dsi_read_register(mipi_dsi, MIPI_DSI_CMD_PKT_STATUS,
++ &val);
++ }
++ /* wait for entire response stroed in FIFO */
++ while ((val & DSI_CMD_PKT_STATUS_GEN_RD_CMD_BUSY) ==
++ DSI_CMD_PKT_STATUS_GEN_RD_CMD_BUSY) {
++ msleep(1);
++ timeout++;
++ if (timeout == MIPI_DSI_REG_RW_TIMEOUT)
++ return -EIO;
++ mipi_dsi_read_register(mipi_dsi, MIPI_DSI_CMD_PKT_STATUS,
++ &val);
++ }
++
++ mipi_dsi_read_register(mipi_dsi, MIPI_DSI_CMD_PKT_STATUS, &val);
++ while (!(val & DSI_CMD_PKT_STATUS_GEN_PLD_R_EMPTY)) {
++ mipi_dsi_read_register(mipi_dsi, MIPI_DSI_GEN_PLD_DATA, buf);
++ read_len += DSI_GEN_PLD_DATA_BUF_SIZE;
++ buf++;
++ mipi_dsi_read_register(mipi_dsi, MIPI_DSI_CMD_PKT_STATUS,
++ &val);
++ if (read_len == (DSI_GEN_PLD_DATA_BUF_ENTRY *
++ DSI_GEN_PLD_DATA_BUF_SIZE))
++ break;
++ }
++
++ if ((len <= read_len) &&
++ ((len + DSI_GEN_PLD_DATA_BUF_SIZE) >= read_len))
++ return 0;
++ else {
++ dev_err(&mipi_dsi->pdev->dev,
++ "actually read_len:%d != len:%d.\n", read_len, len);
++ return -ERANGE;
++ }
++}
++
++int mipi_dsi_dcs_cmd(struct mipi_dsi_info *mipi_dsi,
++ u8 cmd, const u32 *param, int num)
++{
++ int err = 0;
++ u32 buf[DSI_CMD_BUF_MAXSIZE];
++
++ switch (cmd) {
++ case MIPI_DCS_EXIT_SLEEP_MODE:
++ case MIPI_DCS_ENTER_SLEEP_MODE:
++ case MIPI_DCS_SET_DISPLAY_ON:
++ case MIPI_DCS_SET_DISPLAY_OFF:
++ buf[0] = cmd;
++ err = mipi_dsi_pkt_write(mipi_dsi,
++ MIPI_DSI_DCS_SHORT_WRITE, buf, 0);
++ break;
++
++ default:
++ dev_err(&mipi_dsi->pdev->dev,
++ "MIPI DSI DCS Command:0x%x Not supported!\n", cmd);
++ break;
++ }
++
++ return err;
++}
++
++static void mipi_dsi_dphy_init(struct mipi_dsi_info *mipi_dsi,
++ u32 cmd, u32 data)
++{
++ u32 val;
++ u32 timeout = 0;
++
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PHY_IF_CTRL,
++ DSI_PHY_IF_CTRL_RESET);
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PWR_UP, DSI_PWRUP_POWERUP);
++
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PHY_TST_CTRL0, 0);
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PHY_TST_CTRL1,
++ (0x10000 | cmd));
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PHY_TST_CTRL0, 2);
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PHY_TST_CTRL0, 0);
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PHY_TST_CTRL1, (0 | data));
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PHY_TST_CTRL0, 2);
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PHY_TST_CTRL0, 0);
++ val = DSI_PHY_RSTZ_EN_CLK | DSI_PHY_RSTZ_DISABLE_RST |
++ DSI_PHY_RSTZ_DISABLE_SHUTDOWN;
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PHY_RSTZ, val);
++
++ mipi_dsi_read_register(mipi_dsi, MIPI_DSI_PHY_STATUS, &val);
++ while ((val & DSI_PHY_STATUS_LOCK) != DSI_PHY_STATUS_LOCK) {
++ msleep(1);
++ timeout++;
++ if (timeout == MIPI_DSI_PHY_TIMEOUT) {
++ dev_err(&mipi_dsi->pdev->dev,
++ "Error: phy lock timeout!\n");
++ break;
++ }
++ mipi_dsi_read_register(mipi_dsi, MIPI_DSI_PHY_STATUS, &val);
++ }
++ timeout = 0;
++ while ((val & DSI_PHY_STATUS_STOPSTATE_CLK_LANE) !=
++ DSI_PHY_STATUS_STOPSTATE_CLK_LANE) {
++ msleep(1);
++ timeout++;
++ if (timeout == MIPI_DSI_PHY_TIMEOUT) {
++ dev_err(&mipi_dsi->pdev->dev,
++ "Error: phy lock lane timeout!\n");
++ break;
++ }
++ mipi_dsi_read_register(mipi_dsi, MIPI_DSI_PHY_STATUS, &val);
++ }
++}
++
++static void mipi_dsi_enable_controller(struct mipi_dsi_info *mipi_dsi,
++ bool init)
++{
++ u32 val;
++ u32 lane_byte_clk_period;
++ struct fb_videomode *mode = mipi_dsi->mode;
++ struct mipi_lcd_config *lcd_config = mipi_dsi->lcd_config;
++
++ if (init) {
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PWR_UP,
++ DSI_PWRUP_RESET);
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PHY_RSTZ,
++ DSI_PHY_RSTZ_RST);
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_CLKMGR_CFG,
++ DSI_CLKMGR_CFG_CLK_DIV);
++
++ if (!(mode->sync & FB_SYNC_VERT_HIGH_ACT))
++ val = DSI_DPI_CFG_VSYNC_ACT_LOW;
++ if (!(mode->sync & FB_SYNC_HOR_HIGH_ACT))
++ val |= DSI_DPI_CFG_HSYNC_ACT_LOW;
++ if ((mode->sync & FB_SYNC_OE_LOW_ACT))
++ val |= DSI_DPI_CFG_DATAEN_ACT_LOW;
++ if (MIPI_RGB666_LOOSELY == lcd_config->dpi_fmt)
++ val |= DSI_DPI_CFG_EN18LOOSELY;
++ val |= (lcd_config->dpi_fmt & DSI_DPI_CFG_COLORCODE_MASK)
++ << DSI_DPI_CFG_COLORCODE_SHIFT;
++ val |= (lcd_config->virtual_ch & DSI_DPI_CFG_VID_MASK)
++ << DSI_DPI_CFG_VID_SHIFT;
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_DPI_CFG, val);
++
++ val = DSI_PCKHDL_CFG_EN_BTA |
++ DSI_PCKHDL_CFG_EN_ECC_RX |
++ DSI_PCKHDL_CFG_EN_CRC_RX;
++
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PCKHDL_CFG, val);
++
++ val = (mode->xres & DSI_VID_PKT_CFG_VID_PKT_SZ_MASK)
++ << DSI_VID_PKT_CFG_VID_PKT_SZ_SHIFT;
++ val |= (NUMBER_OF_CHUNKS & DSI_VID_PKT_CFG_NUM_CHUNKS_MASK)
++ << DSI_VID_PKT_CFG_NUM_CHUNKS_SHIFT;
++ val |= (NULL_PKT_SIZE & DSI_VID_PKT_CFG_NULL_PKT_SZ_MASK)
++ << DSI_VID_PKT_CFG_NULL_PKT_SZ_SHIFT;
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_VID_PKT_CFG, val);
++
++ /* enable LP mode when TX DCS cmd and enable DSI command mode */
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_CMD_MODE_CFG,
++ MIPI_DSI_CMD_MODE_CFG_EN_LOWPOWER);
++
++ /* mipi lane byte clk period in ns unit */
++ lane_byte_clk_period = NS2PS_RATIO /
++ (lcd_config->max_phy_clk / BITS_PER_BYTE);
++ val = ROUND_UP(mode->hsync_len * mode->pixclock /
++ NS2PS_RATIO / lane_byte_clk_period)
++ << DSI_TME_LINE_CFG_HSA_TIME_SHIFT;
++ val |= ROUND_UP(mode->left_margin * mode->pixclock /
++ NS2PS_RATIO / lane_byte_clk_period)
++ << DSI_TME_LINE_CFG_HBP_TIME_SHIFT;
++ val |= ROUND_UP((mode->left_margin + mode->right_margin +
++ mode->hsync_len + mode->xres) * mode->pixclock
++ / NS2PS_RATIO / lane_byte_clk_period)
++ << DSI_TME_LINE_CFG_HLINE_TIME_SHIFT;
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_TMR_LINE_CFG, val);
++
++ val = ((mode->vsync_len & DSI_VTIMING_CFG_VSA_LINES_MASK)
++ << DSI_VTIMING_CFG_VSA_LINES_SHIFT);
++ val |= ((mode->upper_margin & DSI_VTIMING_CFG_VBP_LINES_MASK)
++ << DSI_VTIMING_CFG_VBP_LINES_SHIFT);
++ val |= ((mode->lower_margin & DSI_VTIMING_CFG_VFP_LINES_MASK)
++ << DSI_VTIMING_CFG_VFP_LINES_SHIFT);
++ val |= ((mode->yres & DSI_VTIMING_CFG_V_ACT_LINES_MASK)
++ << DSI_VTIMING_CFG_V_ACT_LINES_SHIFT);
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_VTIMING_CFG, val);
++
++ val = ((PHY_BTA_MAXTIME & DSI_PHY_TMR_CFG_BTA_TIME_MASK)
++ << DSI_PHY_TMR_CFG_BTA_TIME_SHIFT);
++ val |= ((PHY_LP2HS_MAXTIME & DSI_PHY_TMR_CFG_LP2HS_TIME_MASK)
++ << DSI_PHY_TMR_CFG_LP2HS_TIME_SHIFT);
++ val |= ((PHY_HS2LP_MAXTIME & DSI_PHY_TMR_CFG_HS2LP_TIME_MASK)
++ << DSI_PHY_TMR_CFG_HS2LP_TIME_SHIFT);
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PHY_TMR_CFG, val);
++
++ val = (((lcd_config->data_lane_num - 1) &
++ DSI_PHY_IF_CFG_N_LANES_MASK)
++ << DSI_PHY_IF_CFG_N_LANES_SHIFT);
++ val |= ((PHY_STOP_WAIT_TIME & DSI_PHY_IF_CFG_WAIT_TIME_MASK)
++ << DSI_PHY_IF_CFG_WAIT_TIME_SHIFT);
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PHY_IF_CFG, val);
++
++ mipi_dsi_read_register(mipi_dsi, MIPI_DSI_ERROR_ST0, &val);
++ mipi_dsi_read_register(mipi_dsi, MIPI_DSI_ERROR_ST1, &val);
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_ERROR_MSK0, 0);
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_ERROR_MSK1, 0);
++
++ mipi_dsi_dphy_init(mipi_dsi, DSI_PHY_CLK_INIT_COMMAND,
++ mipi_dsi->dphy_pll_config);
++ } else {
++ mipi_dsi_dphy_init(mipi_dsi, DSI_PHY_CLK_INIT_COMMAND,
++ mipi_dsi->dphy_pll_config);
++ }
++}
++
++static void mipi_dsi_disable_controller(struct mipi_dsi_info *mipi_dsi)
++{
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PHY_IF_CTRL,
++ DSI_PHY_IF_CTRL_RESET);
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PWR_UP, DSI_PWRUP_RESET);
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PHY_RSTZ, DSI_PHY_RSTZ_RST);
++}
++
++static irqreturn_t mipi_dsi_irq_handler(int irq, void *data)
++{
++ u32 mask0;
++ u32 mask1;
++ u32 status0;
++ u32 status1;
++ struct mipi_dsi_info *mipi_dsi;
++
++ mipi_dsi = (struct mipi_dsi_info *)data;
++ mipi_dsi_read_register(mipi_dsi, MIPI_DSI_ERROR_ST0, &status0);
++ mipi_dsi_read_register(mipi_dsi, MIPI_DSI_ERROR_ST1, &status1);
++ mipi_dsi_read_register(mipi_dsi, MIPI_DSI_ERROR_MSK0, &mask0);
++ mipi_dsi_read_register(mipi_dsi, MIPI_DSI_ERROR_MSK1, &mask1);
++
++ if ((status0 & (~mask0)) || (status1 & (~mask1))) {
++ dev_err(&mipi_dsi->pdev->dev,
++ "mipi_dsi IRQ status0:0x%x, status1:0x%x!\n",
++ status0, status1);
++ }
++
++ return IRQ_HANDLED;
++}
++
++static inline void mipi_dsi_set_mode(struct mipi_dsi_info *mipi_dsi,
++ bool cmd_mode)
++{
++ u32 val;
++
++ if (cmd_mode) {
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PWR_UP,
++ DSI_PWRUP_RESET);
++ mipi_dsi_read_register(mipi_dsi, MIPI_DSI_CMD_MODE_CFG, &val);
++ val |= MIPI_DSI_CMD_MODE_CFG_EN_CMD_MODE;
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_CMD_MODE_CFG, val);
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_VID_MODE_CFG, 0);
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PWR_UP,
++ DSI_PWRUP_POWERUP);
++ } else {
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PWR_UP,
++ DSI_PWRUP_RESET);
++ /* Disable Command mode when tranfering video data */
++ mipi_dsi_read_register(mipi_dsi, MIPI_DSI_CMD_MODE_CFG, &val);
++ val &= ~MIPI_DSI_CMD_MODE_CFG_EN_CMD_MODE;
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_CMD_MODE_CFG, val);
++ val = DSI_VID_MODE_CFG_EN | DSI_VID_MODE_CFG_EN_BURSTMODE |
++ DSI_VID_MODE_CFG_EN_LP_MODE;
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_VID_MODE_CFG, val);
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PWR_UP,
++ DSI_PWRUP_POWERUP);
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PHY_IF_CTRL,
++ DSI_PHY_IF_CTRL_TX_REQ_CLK_HS);
++ }
++}
++
++static int mipi_dsi_power_on(struct mxc_dispdrv_handle *disp)
++{
++ int err;
++ struct mipi_dsi_info *mipi_dsi = mxc_dispdrv_getdata(disp);
++
++ if (!mipi_dsi->dsi_power_on) {
++ clk_prepare_enable(mipi_dsi->dphy_clk);
++ clk_prepare_enable(mipi_dsi->cfg_clk);
++ mipi_dsi_enable_controller(mipi_dsi, false);
++ mipi_dsi_set_mode(mipi_dsi, false);
++ /* host send pclk/hsync/vsync for two frames before sleep-out */
++ msleep((1000/mipi_dsi->mode->refresh + 1) << 1);
++ mipi_dsi_set_mode(mipi_dsi, true);
++ err = mipi_dsi_dcs_cmd(mipi_dsi, MIPI_DCS_EXIT_SLEEP_MODE,
++ NULL, 0);
++ if (err) {
++ dev_err(&mipi_dsi->pdev->dev,
++ "MIPI DSI DCS Command sleep-in error!\n");
++ }
++ msleep(MIPI_LCD_SLEEP_MODE_DELAY);
++ mipi_dsi_set_mode(mipi_dsi, false);
++ mipi_dsi->dsi_power_on = 1;
++ }
++
++ return 0;
++}
++
++void mipi_dsi_power_off(struct mxc_dispdrv_handle *disp)
++{
++ int err;
++ struct mipi_dsi_info *mipi_dsi = mxc_dispdrv_getdata(disp);
++
++ if (mipi_dsi->dsi_power_on) {
++ mipi_dsi_set_mode(mipi_dsi, true);
++ err = mipi_dsi_dcs_cmd(mipi_dsi, MIPI_DCS_ENTER_SLEEP_MODE,
++ NULL, 0);
++ if (err) {
++ dev_err(&mipi_dsi->pdev->dev,
++ "MIPI DSI DCS Command display on error!\n");
++ }
++ /* To allow time for the supply voltages
++ * and clock circuits to stabilize.
++ */
++ msleep(5);
++ /* video stream timing on */
++ mipi_dsi_set_mode(mipi_dsi, false);
++ msleep(MIPI_LCD_SLEEP_MODE_DELAY);
++
++ mipi_dsi_set_mode(mipi_dsi, true);
++ mipi_dsi_disable_controller(mipi_dsi);
++ mipi_dsi->dsi_power_on = 0;
++ clk_disable_unprepare(mipi_dsi->dphy_clk);
++ clk_disable_unprepare(mipi_dsi->cfg_clk);
++ }
++}
++
++static int mipi_dsi_lcd_init(struct mipi_dsi_info *mipi_dsi,
++ struct mxc_dispdrv_setting *setting)
++{
++ int err;
++ int size;
++ int i;
++ struct fb_videomode *mipi_lcd_modedb;
++ struct fb_videomode mode;
++ struct device *dev = &mipi_dsi->pdev->dev;
++
++ for (i = 0; i < ARRAY_SIZE(mipi_dsi_lcd_db); i++) {
++ if (!strcmp(mipi_dsi->lcd_panel,
++ mipi_dsi_lcd_db[i].lcd_panel)) {
++ mipi_dsi->lcd_callback =
++ &mipi_dsi_lcd_db[i].lcd_callback;
++ break;
++ }
++ }
++ if (i == ARRAY_SIZE(mipi_dsi_lcd_db)) {
++ dev_err(dev, "failed to find supported lcd panel.\n");
++ return -EINVAL;
++ }
++ /* get the videomode in the order: cmdline->platform data->driver */
++ mipi_dsi->lcd_callback->get_mipi_lcd_videomode(&mipi_lcd_modedb, &size,
++ &mipi_dsi->lcd_config);
++ err = fb_find_mode(&setting->fbi->var, setting->fbi,
++ setting->dft_mode_str,
++ mipi_lcd_modedb, size, NULL,
++ setting->default_bpp);
++ if (err != 1)
++ fb_videomode_to_var(&setting->fbi->var, mipi_lcd_modedb);
++
++ INIT_LIST_HEAD(&setting->fbi->modelist);
++ for (i = 0; i < size; i++) {
++ fb_var_to_videomode(&mode, &setting->fbi->var);
++ if (fb_mode_is_equal(&mode, mipi_lcd_modedb + i)) {
++ err = fb_add_videomode(mipi_lcd_modedb + i,
++ &setting->fbi->modelist);
++ /* Note: only support fb mode from driver */
++ mipi_dsi->mode = mipi_lcd_modedb + i;
++ break;
++ }
++ }
++ if ((err < 0) || (size == i)) {
++ dev_err(dev, "failed to add videomode.\n");
++ return err;
++ }
++
++ for (i = 0; i < ARRAY_SIZE(mipi_dsi_phy_pll_clk_table); i++) {
++ if (mipi_dsi_phy_pll_clk_table[i].max_phy_clk <
++ mipi_dsi->lcd_config->max_phy_clk)
++ break;
++ }
++ if ((i == ARRAY_SIZE(mipi_dsi_phy_pll_clk_table)) ||
++ (mipi_dsi->lcd_config->max_phy_clk >
++ mipi_dsi_phy_pll_clk_table[0].max_phy_clk)) {
++ dev_err(dev, "failed to find data in"
++ "mipi_dsi_phy_pll_clk_table.\n");
++ return -EINVAL;
++ }
++ mipi_dsi->dphy_pll_config = mipi_dsi_phy_pll_clk_table[--i].config;
++ dev_dbg(dev, "dphy_pll_config:0x%x.\n", mipi_dsi->dphy_pll_config);
++
++ return 0;
++}
++
++int mipi_dsi_enable(struct mxc_dispdrv_handle *disp)
++{
++ int err;
++ struct mipi_dsi_info *mipi_dsi = mxc_dispdrv_getdata(disp);
++
++ if (!mipi_dsi->lcd_inited) {
++ err = clk_prepare_enable(mipi_dsi->dphy_clk);
++ err |= clk_prepare_enable(mipi_dsi->cfg_clk);
++ if (err)
++ dev_err(&mipi_dsi->pdev->dev,
++ "clk enable error:%d!\n", err);
++ mipi_dsi_enable_controller(mipi_dsi, true);
++ err = mipi_dsi->lcd_callback->mipi_lcd_setup(
++ mipi_dsi);
++ if (err < 0) {
++ dev_err(&mipi_dsi->pdev->dev,
++ "failed to init mipi lcd.");
++ clk_disable_unprepare(mipi_dsi->dphy_clk);
++ clk_disable_unprepare(mipi_dsi->cfg_clk);
++ return err;
++ }
++ mipi_dsi_set_mode(mipi_dsi, false);
++ mipi_dsi->dsi_power_on = 1;
++ mipi_dsi->lcd_inited = 1;
++ }
++ mipi_dsi_power_on(mipi_dsi->disp_mipi);
++
++ return 0;
++}
++
++static int mipi_dsi_disp_init(struct mxc_dispdrv_handle *disp,
++ struct mxc_dispdrv_setting *setting)
++{
++ struct mipi_dsi_info *mipi_dsi = mxc_dispdrv_getdata(disp);
++ struct device *dev = &mipi_dsi->pdev->dev;
++ int ret = 0;
++
++ if (!valid_mode(setting->if_fmt)) {
++ dev_warn(dev, "Input pixel format not valid"
++ "use default RGB24\n");
++ setting->if_fmt = IPU_PIX_FMT_RGB24;
++ }
++
++ setting->dev_id = mipi_dsi->dev_id;
++ setting->disp_id = mipi_dsi->disp_id;
++
++ ret = mipi_dsi_lcd_init(mipi_dsi, setting);
++ if (ret) {
++ dev_err(dev, "failed to init mipi dsi lcd\n");
++ return ret;
++ }
++
++ dev_dbg(dev, "MIPI DSI dispdrv inited!\n");
++ return ret;
++}
++
++static void mipi_dsi_disp_deinit(struct mxc_dispdrv_handle *disp)
++{
++ struct mipi_dsi_info *mipi_dsi;
++
++ mipi_dsi = mxc_dispdrv_getdata(disp);
++
++ mipi_dsi_power_off(mipi_dsi->disp_mipi);
++ if (mipi_dsi->bl)
++ backlight_device_unregister(mipi_dsi->bl);
++}
++
++static struct mxc_dispdrv_driver mipi_dsi_drv = {
++ .name = DISPDRV_MIPI,
++ .init = mipi_dsi_disp_init,
++ .deinit = mipi_dsi_disp_deinit,
++ .enable = mipi_dsi_enable,
++ .disable = mipi_dsi_power_off,
++};
++
++static int imx6q_mipi_dsi_get_mux(int dev_id, int disp_id)
++{
++ if (dev_id > 1 || disp_id > 1)
++ return -EINVAL;
++
++ return (dev_id << 5) | (disp_id << 4);
++}
++
++static struct mipi_dsi_bus_mux imx6q_mipi_dsi_mux[] = {
++ {
++ .reg = IOMUXC_GPR3,
++ .mask = IMX6Q_GPR3_MIPI_MUX_CTL_MASK,
++ .get_mux = imx6q_mipi_dsi_get_mux,
++ },
++};
++
++static int imx6dl_mipi_dsi_get_mux(int dev_id, int disp_id)
++{
++ if (dev_id > 1 || disp_id > 1)
++ return -EINVAL;
++
++ /* MIPI DSI source is LCDIF */
++ if (dev_id)
++ disp_id = 0;
++
++ return (dev_id << 5) | (disp_id << 4);
++}
++
++static struct mipi_dsi_bus_mux imx6dl_mipi_dsi_mux[] = {
++ {
++ .reg = IOMUXC_GPR3,
++ .mask = IMX6Q_GPR3_MIPI_MUX_CTL_MASK,
++ .get_mux = imx6dl_mipi_dsi_get_mux,
++ },
++};
++
++static const struct of_device_id imx_mipi_dsi_dt_ids[] = {
++ { .compatible = "fsl,imx6q-mipi-dsi", .data = imx6q_mipi_dsi_mux, },
++ { .compatible = "fsl,imx6dl-mipi-dsi", .data = imx6dl_mipi_dsi_mux, },
++ { }
++};
++MODULE_DEVICE_TABLE(of, imx_mipi_dsi_dt_ids);
++
++/**
++ * This function is called by the driver framework to initialize the MIPI DSI
++ * device.
++ *
++ * @param pdev The device structure for the MIPI DSI passed in by the
++ * driver framework.
++ *
++ * @return Returns 0 on success or negative error code on error
++ */
++static int mipi_dsi_probe(struct platform_device *pdev)
++{
++ struct device_node *np = pdev->dev.of_node;
++ const struct of_device_id *of_id =
++ of_match_device(of_match_ptr(imx_mipi_dsi_dt_ids),
++ &pdev->dev);
++ struct mipi_dsi_info *mipi_dsi;
++ struct resource *res;
++ u32 dev_id, disp_id;
++ const char *lcd_panel;
++ unsigned int mux;
++ int ret = 0;
++
++ mipi_dsi = devm_kzalloc(&pdev->dev, sizeof(*mipi_dsi), GFP_KERNEL);
++ if (!mipi_dsi)
++ return -ENOMEM;
++
++ ret = of_property_read_string(np, "lcd_panel", &lcd_panel);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to read of property lcd_panel\n");
++ return ret;
++ }
++
++ ret = of_property_read_u32(np, "dev_id", &dev_id);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to read of property dev_id\n");
++ return ret;
++ }
++ ret = of_property_read_u32(np, "disp_id", &disp_id);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to read of property disp_id\n");
++ return ret;
++ }
++ mipi_dsi->dev_id = dev_id;
++ mipi_dsi->disp_id = disp_id;
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (!res) {
++ dev_err(&pdev->dev, "failed to get platform resource 0\n");
++ return -ENODEV;
++ }
++
++ if (!devm_request_mem_region(&pdev->dev, res->start,
++ resource_size(res), pdev->name))
++ return -EBUSY;
++
++ mipi_dsi->mmio_base = devm_ioremap(&pdev->dev, res->start,
++ resource_size(res));
++ if (!mipi_dsi->mmio_base)
++ return -EBUSY;
++
++ mipi_dsi->irq = platform_get_irq(pdev, 0);
++ if (mipi_dsi->irq < 0) {
++ dev_err(&pdev->dev, "failed get device irq\n");
++ return -ENODEV;
++ }
++
++ ret = devm_request_irq(&pdev->dev, mipi_dsi->irq,
++ mipi_dsi_irq_handler,
++ 0, "mipi_dsi", mipi_dsi);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to request irq\n");
++ return ret;
++ }
++
++ mipi_dsi->dphy_clk = devm_clk_get(&pdev->dev, "mipi_pllref_clk");
++ if (IS_ERR(mipi_dsi->dphy_clk)) {
++ dev_err(&pdev->dev, "failed to get dphy pll_ref_clk\n");
++ return PTR_ERR(mipi_dsi->dphy_clk);
++ }
++
++ mipi_dsi->cfg_clk = devm_clk_get(&pdev->dev, "mipi_cfg_clk");
++ if (IS_ERR(mipi_dsi->cfg_clk)) {
++ dev_err(&pdev->dev, "failed to get cfg_clk\n");
++ return PTR_ERR(mipi_dsi->cfg_clk);
++ }
++
++ mipi_dsi->disp_power_on = devm_regulator_get(&pdev->dev,
++ "disp-power-on");
++ if (!IS_ERR(mipi_dsi->disp_power_on)) {
++ ret = regulator_enable(mipi_dsi->disp_power_on);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to enable display "
++ "power regulator, err=%d\n", ret);
++ return ret;
++ }
++ } else {
++ mipi_dsi->disp_power_on = NULL;
++ }
++
++ ret = device_reset(&pdev->dev);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to reset: %d\n", ret);
++ goto dev_reset_fail;
++ }
++
++ if (of_id)
++ mipi_dsi->bus_mux = of_id->data;
++
++ mipi_dsi->regmap = syscon_regmap_lookup_by_phandle(np, "gpr");
++ if (IS_ERR(mipi_dsi->regmap)) {
++ dev_err(&pdev->dev, "failed to get parent regmap\n");
++ ret = PTR_ERR(mipi_dsi->regmap);
++ goto get_parent_regmap_fail;
++ }
++
++ mux = mipi_dsi->bus_mux->get_mux(dev_id, disp_id);
++ if (mux >= 0)
++ regmap_update_bits(mipi_dsi->regmap, mipi_dsi->bus_mux->reg,
++ mipi_dsi->bus_mux->mask, mux);
++ else
++ dev_warn(&pdev->dev, "invalid dev_id or disp_id muxing\n");
++
++ mipi_dsi->lcd_panel = kstrdup(lcd_panel, GFP_KERNEL);
++ if (!mipi_dsi->lcd_panel) {
++ dev_err(&pdev->dev, "failed to allocate lcd panel name\n");
++ ret = -ENOMEM;
++ goto kstrdup_fail;
++ }
++
++ mipi_dsi->pdev = pdev;
++ mipi_dsi->disp_mipi = mxc_dispdrv_register(&mipi_dsi_drv);
++ if (IS_ERR(mipi_dsi->disp_mipi)) {
++ dev_err(&pdev->dev, "mxc_dispdrv_register error\n");
++ ret = PTR_ERR(mipi_dsi->disp_mipi);
++ goto dispdrv_reg_fail;
++ }
++
++ mxc_dispdrv_setdata(mipi_dsi->disp_mipi, mipi_dsi);
++ dev_set_drvdata(&pdev->dev, mipi_dsi);
++
++ dev_info(&pdev->dev, "i.MX MIPI DSI driver probed\n");
++ return ret;
++
++dispdrv_reg_fail:
++ kfree(mipi_dsi->lcd_panel);
++kstrdup_fail:
++get_parent_regmap_fail:
++dev_reset_fail:
++ if (mipi_dsi->disp_power_on)
++ regulator_disable(mipi_dsi->disp_power_on);
++ return ret;
++}
++
++static void mipi_dsi_shutdown(struct platform_device *pdev)
++{
++ struct mipi_dsi_info *mipi_dsi = dev_get_drvdata(&pdev->dev);
++
++ mipi_dsi_power_off(mipi_dsi->disp_mipi);
++}
++
++static int mipi_dsi_remove(struct platform_device *pdev)
++{
++ struct mipi_dsi_info *mipi_dsi = dev_get_drvdata(&pdev->dev);
++
++ mxc_dispdrv_puthandle(mipi_dsi->disp_mipi);
++ mxc_dispdrv_unregister(mipi_dsi->disp_mipi);
++
++ if (mipi_dsi->disp_power_on)
++ regulator_disable(mipi_dsi->disp_power_on);
++
++ kfree(mipi_dsi->lcd_panel);
++ dev_set_drvdata(&pdev->dev, NULL);
++
++ return 0;
++}
++
++static struct platform_driver mipi_dsi_driver = {
++ .driver = {
++ .of_match_table = imx_mipi_dsi_dt_ids,
++ .name = "mxc_mipi_dsi",
++ },
++ .probe = mipi_dsi_probe,
++ .remove = mipi_dsi_remove,
++ .shutdown = mipi_dsi_shutdown,
++};
++
++static int __init mipi_dsi_init(void)
++{
++ int err;
++
++ err = platform_driver_register(&mipi_dsi_driver);
++ if (err) {
++ pr_err("mipi_dsi_driver register failed\n");
++ return -ENODEV;
++ }
++ pr_info("MIPI DSI driver module loaded\n");
++ return 0;
++}
++
++static void __exit mipi_dsi_cleanup(void)
++{
++ platform_driver_unregister(&mipi_dsi_driver);
++}
++
++module_init(mipi_dsi_init);
++module_exit(mipi_dsi_cleanup);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("i.MX MIPI DSI driver");
++MODULE_LICENSE("GPL");
+diff -Nur linux-4.1.3/drivers/video/mxc/mipi_dsi.h linux-xbian-imx6/drivers/video/mxc/mipi_dsi.h
+--- linux-4.1.3/drivers/video/mxc/mipi_dsi.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/video/mxc/mipi_dsi.h 2015-07-27 23:13:08.749764128 +0200
+@@ -0,0 +1,112 @@
++/*
++ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++#ifndef __MIPI_DSI_H__
++#define __MIPI_DSI_H__
++
++#include <linux/regmap.h>
++
++#ifdef DEBUG
++#define mipi_dbg(fmt, ...) printk(KERN_DEBUG pr_fmt(fmt), ##__VA_ARGS__)
++#else
++#define mipi_dbg(fmt, ...)
++#endif
++
++#define DSI_CMD_BUF_MAXSIZE (32)
++
++/* DPI interface pixel color coding map */
++enum mipi_dsi_dpi_fmt {
++ MIPI_RGB565_PACKED = 0,
++ MIPI_RGB565_LOOSELY,
++ MIPI_RGB565_CONFIG3,
++ MIPI_RGB666_PACKED,
++ MIPI_RGB666_LOOSELY,
++ MIPI_RGB888,
++};
++
++struct mipi_lcd_config {
++ u32 virtual_ch;
++ u32 data_lane_num;
++ /* device max DPHY clock in MHz unit */
++ u32 max_phy_clk;
++ enum mipi_dsi_dpi_fmt dpi_fmt;
++};
++
++struct mipi_dsi_info;
++struct mipi_dsi_lcd_callback {
++ /* callback for lcd panel operation */
++ void (*get_mipi_lcd_videomode)(struct fb_videomode **, int *,
++ struct mipi_lcd_config **);
++ int (*mipi_lcd_setup)(struct mipi_dsi_info *);
++
++};
++
++struct mipi_dsi_match_lcd {
++ char *lcd_panel;
++ struct mipi_dsi_lcd_callback lcd_callback;
++};
++
++struct mipi_dsi_bus_mux {
++ int reg;
++ int mask;
++ int (*get_mux) (int dev_id, int disp_id);
++};
++
++/* driver private data */
++struct mipi_dsi_info {
++ struct platform_device *pdev;
++ void __iomem *mmio_base;
++ struct regmap *regmap;
++ const struct mipi_dsi_bus_mux *bus_mux;
++ int dsi_power_on;
++ int lcd_inited;
++ u32 dphy_pll_config;
++ int dev_id;
++ int disp_id;
++ char *lcd_panel;
++ int irq;
++ struct clk *dphy_clk;
++ struct clk *cfg_clk;
++ struct mxc_dispdrv_handle *disp_mipi;
++ struct fb_videomode *mode;
++ struct regulator *disp_power_on;
++ struct mipi_lcd_config *lcd_config;
++ /* board related power control */
++ struct backlight_device *bl;
++ /* callback for lcd panel operation */
++ struct mipi_dsi_lcd_callback *lcd_callback;
++};
++
++int mipi_dsi_pkt_write(struct mipi_dsi_info *mipi,
++ u8 data_type, const u32 *buf, int len);
++int mipi_dsi_pkt_read(struct mipi_dsi_info *mipi,
++ u8 data_type, u32 *buf, int len);
++int mipi_dsi_dcs_cmd(struct mipi_dsi_info *mipi,
++ u8 cmd, const u32 *param, int num);
++
++#ifdef CONFIG_FB_MXC_TRULY_WVGA_SYNC_PANEL
++void mipid_hx8369_get_lcd_videomode(struct fb_videomode **mode, int *size,
++ struct mipi_lcd_config **data);
++int mipid_hx8369_lcd_setup(struct mipi_dsi_info *);
++#endif
++
++#ifndef CONFIG_FB_MXC_TRULY_WVGA_SYNC_PANEL
++#error "Please configure MIPI LCD panel, we cannot find one!"
++#endif
++
++#endif
+diff -Nur linux-4.1.3/drivers/video/mxc/mxc_dcic.c linux-xbian-imx6/drivers/video/mxc/mxc_dcic.c
+--- linux-4.1.3/drivers/video/mxc/mxc_dcic.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/video/mxc/mxc_dcic.c 2015-07-27 23:13:08.749764128 +0200
+@@ -0,0 +1,697 @@
++/*
++ * Copyright (C) 2014 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++#include <linux/clk.h>
++#include <linux/cdev.h>
++#include <linux/delay.h>
++#include <linux/err.h>
++#include <linux/fs.h>
++#include <linux/fb.h>
++#include <linux/init.h>
++#include <linux/io.h>
++#include <linux/ioctl.h>
++#include <linux/interrupt.h>
++#include <linux/mfd/syscon.h>
++#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
++#include <linux/module.h>
++#include <linux/mxc_dcic.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++#include <linux/regmap.h>
++#include <linux/types.h>
++#include <linux/uaccess.h>
++#include <video/videomode.h>
++#include <video/of_videomode.h>
++
++#define DRIVER_NAME "mxc_dcic"
++
++#define DCIC_IPU1_DI0 "dcic-ipu1-di0"
++#define DCIC_IPU1_DI1 "dcic-ipu1-di1"
++#define DCIC_IPU2_DI0 "dcic-ipu2-di0"
++#define DCIC_IPU2_DI1 "dcic-ipu2-di1"
++#define DCIC_LCDIF "dcic-lcdif"
++#define DCIC_LCDIF1 "dcic-lcdif1"
++#define DCIC_LCDIF2 "dcic-lcdif2"
++#define DCIC_LVDS "dcic-lvds"
++#define DCIC_LVDS0 "dcic-lvds0"
++#define DCIC_LVDS1 "dcic-lvds1"
++#define DCIC_HDMI "dcic-hdmi"
++
++#define DCIC0_DEV_NAME "mxc_dcic0"
++#define DCIC1_DEV_NAME "mxc_dcic1"
++
++#define FB_SYNC_OE_LOW_ACT 0x80000000
++#define FB_SYNC_CLK_LAT_FALL 0x40000000
++
++static wait_queue_head_t mxc_dcic_wait;
++static int mxc_dcic_vsync;
++static uint16_t mxc_dcic_irq;
++static unsigned long mxc_dcic_counter;
++static uint16_t mxc_dcic_clients;
++
++static const struct dcic_mux imx6q_dcic0_mux[] = {
++ {
++ .dcic = DCIC_IPU1_DI0,
++ .val = IMX6Q_GPR10_DCIC1_MUX_CTL_IPU1_DI0,
++ }, {
++ .dcic = DCIC_LVDS0,
++ .val = IMX6Q_GPR10_DCIC1_MUX_CTL_LVDS0,
++ }, {
++ .dcic = DCIC_LVDS1,
++ .val = IMX6Q_GPR10_DCIC1_MUX_CTL_LVDS1,
++ }, {
++ .dcic = DCIC_HDMI,
++ .val = IMX6Q_GPR10_DCIC1_MUX_CTL_HDMI,
++ }
++};
++
++static const struct dcic_mux imx6q_dcic1_mux[] = {
++ {
++ .dcic = DCIC_IPU1_DI1,
++ .val = IMX6Q_GPR10_DCIC2_MUX_CTL_IPU1_DI1,
++ }, {
++ .dcic = DCIC_LVDS0,
++ .val = IMX6Q_GPR10_DCIC2_MUX_CTL_LVDS0,
++ }, {
++ .dcic = DCIC_LVDS1,
++ .val = IMX6Q_GPR10_DCIC2_MUX_CTL_LVDS1,
++ }, {
++ .dcic = DCIC_HDMI,
++ .val = IMX6Q_GPR10_DCIC2_MUX_CTL_MIPI,
++ }
++};
++
++static const struct bus_mux imx6q_dcic_buses[] = {
++ {
++ .name = DCIC0_DEV_NAME,
++ .reg = IOMUXC_GPR10,
++ .shift = 0,
++ .mask = IMX6Q_GPR10_DCIC1_MUX_CTL_MASK,
++ .dcic_mux_num = ARRAY_SIZE(imx6q_dcic0_mux),
++ .dcics = imx6q_dcic0_mux,
++ }, {
++ .name = DCIC1_DEV_NAME,
++ .reg = IOMUXC_GPR10,
++ .shift = 2,
++ .mask = IMX6Q_GPR10_DCIC2_MUX_CTL_MASK,
++ .dcic_mux_num = ARRAY_SIZE(imx6q_dcic1_mux),
++ .dcics = imx6q_dcic1_mux,
++ }
++};
++
++static const struct dcic_info imx6q_dcic_info = {
++ .bus_mux_num = ARRAY_SIZE(imx6q_dcic_buses),
++ .buses = imx6q_dcic_buses,
++};
++
++static const struct dcic_mux imx6sx_dcic0_mux[] = {
++ {
++ .dcic = DCIC_LCDIF1,
++ .val = IMX6SX_GPR5_DISP_MUX_DCIC1_LCDIF1,
++ }, {
++ .dcic = DCIC_LVDS,
++ .val = IMX6SX_GPR5_DISP_MUX_DCIC1_LVDS,
++ }
++};
++
++static const struct dcic_mux imx6sx_dcic1_mux[] = {
++ {
++ .dcic = DCIC_LCDIF2,
++ .val = IMX6SX_GPR5_DISP_MUX_DCIC2_LCDIF2,
++ }, {
++ .dcic = DCIC_LVDS,
++ .val = IMX6SX_GPR5_DISP_MUX_DCIC2_LVDS,
++ }
++};
++
++static const struct bus_mux imx6sx_dcic_buses[] = {
++ {
++ .name = DCIC0_DEV_NAME,
++ .reg = IOMUXC_GPR5,
++ .shift = 1,
++ .mask = IMX6SX_GPR5_DISP_MUX_DCIC1_MASK,
++ .dcic_mux_num = ARRAY_SIZE(imx6sx_dcic0_mux),
++ .dcics = imx6sx_dcic0_mux,
++ }, {
++ .name = DCIC1_DEV_NAME,
++ .reg = IOMUXC_GPR5,
++ .shift = 2,
++ .mask = IMX6SX_GPR5_DISP_MUX_DCIC2_MASK,
++ .dcic_mux_num = ARRAY_SIZE(imx6sx_dcic1_mux),
++ .dcics = imx6sx_dcic1_mux,
++ }
++};
++
++static const struct dcic_info imx6sx_dcic_info = {
++ .bus_mux_num = ARRAY_SIZE(imx6sx_dcic_buses),
++ .buses = imx6sx_dcic_buses,
++};
++
++static const struct of_device_id dcic_dt_ids[] = {
++ { .compatible = "fsl,imx6q-dcic", .data = &imx6q_dcic_info, },
++ { .compatible = "fsl,imx6sx-dcic", .data = &imx6sx_dcic_info, },
++ { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, dcic_dt_ids);
++
++static int of_get_dcic_val(struct device_node *np, struct dcic_data *dcic)
++{
++ const char *mux;
++ int ret;
++ u32 i, dcic_id;
++
++ ret = of_property_read_string(np, "dcic_mux", &mux);
++ if (ret < 0) {
++ dev_err(dcic->dev, "Can not get dcic_mux\n");
++ return ret;
++ }
++ ret = of_property_read_u32(np, "dcic_id", &dcic_id);
++ if (ret < 0) {
++ dev_err(dcic->dev, "Can not get dcic_id\n");
++ return ret;
++ }
++
++ dcic->bus_n = dcic_id;
++
++ for (i = 0; i < dcic->buses[dcic_id].dcic_mux_num; i++)
++ if (!strcmp(mux, dcic->buses[dcic_id].dcics[i].dcic)) {
++ dcic->mux_n = i;
++ return dcic->buses[dcic_id].dcics[i].val;
++ }
++
++ return -EINVAL;
++}
++
++static void dcic_enable(struct dcic_data *dcic)
++{
++ u32 val;
++
++ val = readl(&dcic->regs->dcicc);
++ val |= DCICC_IC_ENABLE;
++ writel(val, &dcic->regs->dcicc);
++}
++
++void dcic_disable(struct dcic_data *dcic)
++{
++ u32 val;
++
++ val = readl(&dcic->regs->dcicc);
++ val &= ~DCICC_IC_MASK;
++ val |= DCICC_IC_DISABLE;
++ writel(val, &dcic->regs->dcicc);
++}
++
++static void roi_enable(struct dcic_data *dcic, struct roi_params *roi_param)
++{
++ u32 val;
++ u32 roi_n = roi_param->roi_n;
++
++ val = readl(&dcic->regs->ROI[roi_n].dcicrc);
++ val |= DCICRC_ROI_ENABLE;
++ if (roi_param->freeze)
++ val |= DCICRC_ROI_FROZEN;
++ writel(val, &dcic->regs->ROI[roi_n].dcicrc);
++}
++
++static void roi_disable(struct dcic_data *dcic, u32 roi_n)
++{
++ u32 val;
++
++ val = readl(&dcic->regs->ROI[roi_n].dcicrc);
++ val &= ~DCICRC_ROI_ENABLE;
++ writel(val, &dcic->regs->ROI[roi_n].dcicrc);
++}
++
++static bool roi_configure(struct dcic_data *dcic, struct roi_params *roi_param)
++{
++ struct roi_regs *roi_reg;
++ u32 val;
++
++ if (roi_param->roi_n < 0 || roi_param->roi_n >= 16) {
++ pr_err("Error, Wrong ROI number %d\n", roi_param->roi_n);
++ return false;
++ }
++
++ if (roi_param->end_x <= roi_param->start_x ||
++ roi_param->end_y <= roi_param->start_y) {
++ pr_err("Error, Wrong ROI\n");
++ return false;
++ }
++
++ roi_reg = (struct roi_regs *) &dcic->regs->ROI[roi_param->roi_n];
++
++ /* init roi block size */
++ val = roi_param->start_y << 16 | roi_param->start_x;
++ writel(val, &roi_reg->dcicrc);
++
++ val = roi_param->end_y << 16 | roi_param->end_x;
++ writel(val, &roi_reg->dcicrs);
++
++ writel(roi_param->ref_sig, &roi_reg->dcicrrs);
++
++ roi_enable(dcic, roi_param);
++ return true;
++}
++
++static void dcic_int_enable(struct dcic_data *dcic)
++{
++ u32 val;
++
++ /* Clean pending interrupt before enable int */
++ writel(DCICS_FI_STAT_PENDING, &dcic->regs->dcics);
++ writel(0xffffffff, &dcic->regs->dcics);
++
++ /* Enable function interrupt */
++ val = readl(&dcic->regs->dcicic);
++ val &= ~DCICIC_FUN_INT_MASK;
++ val |= DCICIC_FUN_INT_ENABLE;
++ writel(val, &dcic->regs->dcicic);
++}
++
++static void dcic_int_disable(struct dcic_data *dcic)
++{
++ u32 val;
++
++ /* Disable both function and error interrupt */
++ val = readl(&dcic->regs->dcicic);
++ val = DCICIC_ERROR_INT_DISABLE | DCICIC_FUN_INT_DISABLE;
++ writel(val, &dcic->regs->dcicic);
++}
++
++static irqreturn_t dcic_irq_handler(int irq, void *data)
++{
++ u32 i;
++
++ struct dcic_data *dcic = data;
++ u32 dcics = readl(&dcic->regs->dcics);
++
++ dcic->result = dcics & 0xffff;
++
++ if (!mxc_dcic_vsync)
++ dcic_int_disable(dcic);
++ else {
++ mxc_dcic_irq = -1;
++ mxc_dcic_counter++;
++ }
++
++ /* clean dcic interrupt state */
++ writel(DCICS_FI_STAT_PENDING, &dcic->regs->dcics);
++ writel(dcics, &dcic->regs->dcics);
++
++ if (mxc_dcic_vsync) {
++ wake_up(&mxc_dcic_wait);
++ return IRQ_HANDLED;
++ }
++
++ for (i = 0; i < 16; i++) {
++ pr_debug("ROI=%d,crcRS=0x%x, crcCS=0x%x\n", i,
++ readl(&dcic->regs->ROI[i].dcicrrs),
++ readl(&dcic->regs->ROI[i].dcicrcs));
++ }
++ complete(&dcic->roi_crc_comp);
++
++ return IRQ_HANDLED;
++}
++
++static int dcic_configure(struct dcic_data *dcic, unsigned int sync)
++{
++ u32 val;
++ val = 0;
++
++ /* vsync, hsync, DE, clk_pol */
++ if (!(sync & FB_SYNC_HOR_HIGH_ACT))
++ val |= DCICC_HSYNC_POL_ACTIVE_LOW;
++ if (!(sync & FB_SYNC_VERT_HIGH_ACT))
++ val |= DCICC_VSYNC_POL_ACTIVE_LOW;
++ if (sync & FB_SYNC_OE_LOW_ACT)
++ val |= DCICC_DE_ACTIVE_LOW;
++ if (sync & FB_SYNC_CLK_LAT_FALL)
++ val |= DCICC_CLK_POL_INVERTED;
++
++ writel(val, &dcic->regs->dcicc);
++ return 0;
++}
++
++static int dcic_open(struct inode *inode, struct file *file)
++{
++ struct dcic_data *dcic = container_of(inode->i_cdev, struct dcic_data, cdev);
++ struct dcic_private *dcic_client;
++ int i = 0;
++
++ dcic_client = devm_kzalloc(dcic->dev,
++ sizeof(struct dcic_private),
++ GFP_KERNEL);
++ if (!dcic_client) {
++ dev_err(dcic->dev, "Cannot allocate device data\n");
++ return -ENOMEM;
++ }
++
++ mutex_lock(&dcic->lock);
++
++ if (mxc_dcic_clients == 0xffff) {
++ mutex_unlock(&dcic->lock);
++ return -EBUSY;
++ }
++
++ clk_prepare_enable(dcic->disp_axi_clk);
++ clk_prepare_enable(dcic->dcic_clk);
++
++ dcic_client->dcic = dcic;
++ file->private_data = dcic_client;
++
++ while (mxc_dcic_clients & BIT(i++));
++ mxc_dcic_clients |= BIT(i);
++ dcic_client->client_id |= BIT(i);
++
++ mutex_unlock(&dcic->lock);
++ return 0;
++}
++
++static int dcic_release(struct inode *inode, struct file *file)
++{
++ struct dcic_private *dcic_client = file->private_data;
++ struct dcic_data *dcic = dcic_client->dcic;
++ u32 i;
++
++ mutex_lock(&dcic->lock);
++
++ mxc_dcic_clients &= ~dcic_client->client_id;
++ if (!mxc_dcic_clients) {
++ for (i = 0; i < 16; i++)
++ roi_disable(dcic, i);
++
++ clk_disable_unprepare(dcic->dcic_clk);
++ clk_disable_unprepare(dcic->disp_axi_clk);
++ }
++
++ mutex_unlock(&dcic->lock);
++ devm_kfree(dcic->dev, dcic_client);
++ return 0;
++}
++
++static int dcic_init(struct device_node *np, struct dcic_data *dcic)
++{
++ u32 val, bus;
++
++ val = of_get_dcic_val(np, dcic);
++ if (val < 0) {
++ pr_err("Error incorrect\n");
++ return -1;
++ }
++
++ bus = dcic->bus_n;
++
++ regmap_update_bits(dcic->regmap, dcic->buses[bus].reg ,
++ dcic->buses[bus].mask, val);
++
++ return 0;
++}
++
++static long dcic_ioctl(struct file *file,
++ unsigned int cmd, unsigned long arg)
++{
++ int __user *argp = (void __user *)arg;
++ struct dcic_private *dcic_client = file->private_data;
++ struct dcic_data *dcic = dcic_client->dcic;
++ struct roi_params roi_param;
++ unsigned int sync;
++ int ret = 0;
++ int i, t = 0;
++
++ if (cmd == DCIC_IOC_STOP_VSYNC || cmd == DCIC_IOC_START_VSYNC) {
++ for (i = 0; i < 16; i++)
++ if (mxc_dcic_clients & BIT(i) && ++t > 1)
++ return 0;
++ }
++
++ switch (cmd) {
++ case DCIC_IOC_CONFIG_DCIC:
++ if (!copy_from_user(&sync, argp, sizeof(unsigned int)))
++ dcic_configure(dcic, sync);
++ break;
++ case DCIC_IOC_CONFIG_ROI:
++ if (copy_from_user(&roi_param, argp, sizeof(roi_param)))
++ return -EFAULT;
++ else
++ if (!roi_configure(dcic, &roi_param))
++ return -EINVAL;
++ break;
++ case DCIC_IOC_GET_RESULT:
++ init_completion(&dcic->roi_crc_comp);
++
++ dcic_enable(dcic);
++
++ dcic->result = 0;
++ msleep(25);
++
++ dcic_int_enable(dcic);
++
++ ret = wait_for_completion_interruptible_timeout(
++ &dcic->roi_crc_comp, 1 * HZ);
++ if (ret == 0) {
++ dev_err(dcic->dev,
++ "dcic wait for roi crc cal timeout\n");
++ ret = -ETIME;
++ } else if (ret > 0) {
++ if (copy_to_user(argp, &dcic->result, sizeof(dcic->result)))
++ return -EFAULT;
++ ret = 0;
++ }
++ dcic_disable(dcic);
++ break;
++ case DCIC_IOC_START_VSYNC:
++ mxc_dcic_vsync = 1;
++ mxc_dcic_irq = 0;
++ mxc_dcic_counter = 0;
++
++ // configure minimum roi block
++ roi_param.roi_n = 0;
++ roi_param.end_x = 1;
++ roi_param.start_x = 0;
++ roi_param.end_y = 1;
++ roi_param.start_y = 0;
++ roi_configure(dcic, &roi_param);
++
++ dcic_enable(dcic);
++ dcic_int_enable(dcic);
++ break;
++ case DCIC_IOC_STOP_VSYNC:
++ mxc_dcic_vsync = 0;
++ mxc_dcic_irq = 0;
++ init_completion(&dcic->roi_crc_comp);
++ wait_for_completion_interruptible_timeout(&dcic->roi_crc_comp, 1 * HZ);
++ dcic_disable(dcic);
++ break;
++ default:
++ pr_err("%s, Unsupport cmd %d\n", __func__, cmd);
++ break;
++ }
++ return ret;
++}
++
++static ssize_t dcic_read(struct file *file, char __user *buf, size_t count,
++ loff_t *ppos)
++{
++ struct dcic_private *dcic_client = file->private_data;
++ int ret = 0;
++
++ do {
++ if (mxc_dcic_irq & dcic_client->client_id) {
++ count = min(sizeof(unsigned long), count);
++ ret = copy_to_user(buf, &mxc_dcic_counter, count) ? -EFAULT : count;
++ mxc_dcic_irq &= ~dcic_client->client_id;
++ break;
++ }
++ if (file->f_flags & O_NONBLOCK) {
++ ret = -EAGAIN;
++ }
++ else if (wait_event_interruptible(mxc_dcic_wait, mxc_dcic_irq & dcic_client->client_id))
++ ret = -ERESTARTSYS;
++ } while(!ret);
++
++ return ret;
++}
++
++static const struct file_operations mxc_dcic_fops = {
++ .owner = THIS_MODULE,
++ .open = dcic_open,
++ .release = dcic_release,
++ .unlocked_ioctl = dcic_ioctl,
++ .read = dcic_read,
++};
++
++static int dcic_probe(struct platform_device *pdev)
++{
++ struct device *dev = &pdev->dev;
++ const struct of_device_id *of_id =
++ of_match_device(dcic_dt_ids, dev);
++ const struct dcic_info *dcic_info =
++ (const struct dcic_info *)of_id->data;
++ struct device_node *np = dev->of_node;
++ struct dcic_data *dcic;
++ struct resource *res;
++ const char *name;
++ dev_t devt;
++ int ret = 0;
++ int irq;
++
++ dcic = devm_kzalloc(&pdev->dev,
++ sizeof(struct dcic_data),
++ GFP_KERNEL);
++ if (!dcic) {
++ dev_err(&pdev->dev, "Cannot allocate device data\n");
++ ret = -ENOMEM;
++ goto ealloc;
++ }
++
++ platform_set_drvdata(pdev, dcic);
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (!res) {
++ dev_err(&pdev->dev, "No dcic base address found.\n");
++ ret = -ENODEV;
++ goto ealloc;
++ }
++
++ dcic->regs = (struct dcic_regs *) devm_ioremap(&pdev->dev, res->start, resource_size(res));
++ if (!dcic->regs) {
++ dev_err(&pdev->dev, "ioremap failed with dcic base\n");
++ ret = -ENOMEM;
++ goto ealloc;
++ }
++
++ dcic->dev = dev;
++ dcic->buses = dcic_info->buses;
++
++ dcic->regmap = syscon_regmap_lookup_by_phandle(np, "gpr");
++ if (IS_ERR(dcic->regmap)) {
++ dev_err(dev, "failed to get parent regmap\n");
++ ret = PTR_ERR(dcic->regmap);
++ goto ealloc;
++ }
++
++ /* clock */
++ dcic->disp_axi_clk = devm_clk_get(&pdev->dev, "disp-axi");
++ if (IS_ERR(dcic->disp_axi_clk)) {
++ dev_err(&pdev->dev, "get disp-axi clock failed\n");
++ ret = PTR_ERR(dcic->disp_axi_clk);
++ goto ealloc;
++ }
++
++ dcic->dcic_clk = devm_clk_get(&pdev->dev, "dcic");
++ if (IS_ERR(dcic->dcic_clk)) {
++ dev_err(&pdev->dev, "get dcic clk failed\n");
++ ret = PTR_ERR(dcic->dcic_clk);
++ goto ealloc;
++ }
++
++ mutex_init(&dcic->lock);
++ ret = dcic_init(np, dcic);
++ if (ret < 0) {
++ pr_err("Failed init dcic\n");
++ goto ealloc;
++ }
++
++ /* register device */
++ name = dcic->buses[dcic->bus_n].name;
++ dcic->major = register_chrdev(0, name, &mxc_dcic_fops);
++ if (dcic->major < 0) {
++ pr_err("DCIC: unable to get a major for dcic\n");
++ ret = -EBUSY;
++ goto ealloc;
++ }
++
++ dcic->class = class_create(THIS_MODULE, name);
++ if (IS_ERR(dcic->class)) {
++ ret = PTR_ERR(dcic->class);
++ goto err_out_chrdev;
++ }
++
++ /* create char device */
++ devt = MKDEV(dcic->major, 0);
++ dcic->devt = devt;
++
++ cdev_init(&dcic->cdev, &mxc_dcic_fops);
++ dcic->cdev.owner = THIS_MODULE;
++ ret = cdev_add(&dcic->cdev, devt, 1);
++ if (ret)
++ goto err_out_class;
++
++ device_create(dcic->class, NULL, devt,
++ NULL, name);
++
++ /* IRQ */
++ irq = platform_get_irq(pdev, 0);
++
++ ret = devm_request_irq(&pdev->dev, irq, dcic_irq_handler, 0,
++ dev_name(&pdev->dev), dcic);
++ if (ret) {
++ dev_err(&pdev->dev, "request_irq (%d) failed with error %d\n",
++ irq, ret);
++ goto err_out_cdev;
++ }
++
++ init_waitqueue_head(&mxc_dcic_wait);
++ mxc_dcic_vsync = 0;
++ mxc_dcic_irq = 0;
++
++ return 0;
++
++err_out_cdev:
++ cdev_del(&dcic->cdev);
++err_out_class:
++ device_destroy(dcic->class, devt);
++ class_destroy(dcic->class);
++err_out_chrdev:
++ unregister_chrdev(dcic->major, name);
++ealloc:
++ return ret;
++}
++
++static int dcic_remove(struct platform_device *pdev)
++{
++ struct dcic_data *dcic = platform_get_drvdata(pdev);
++ const char *name;
++
++ name = dcic->buses[dcic->bus_n].name;
++
++ device_destroy(dcic->class, dcic->devt);
++ cdev_del(&dcic->cdev);
++ class_destroy(dcic->class);
++ unregister_chrdev(dcic->major, name);
++ mutex_destroy(&dcic->lock);
++
++ return 0;
++}
++
++static struct platform_driver dcic_driver = {
++ .driver = {
++ .name = DRIVER_NAME,
++ .of_match_table = dcic_dt_ids,
++ },
++ .probe = dcic_probe,
++ .remove = dcic_remove,
++};
++
++module_platform_driver(dcic_driver);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("MXC DCIC driver");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:" DRIVER_NAME);
+diff -Nur linux-4.1.3/drivers/video/mxc/mxc_dispdrv.c linux-xbian-imx6/drivers/video/mxc/mxc_dispdrv.c
+--- linux-4.1.3/drivers/video/mxc/mxc_dispdrv.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/video/mxc/mxc_dispdrv.c 2015-07-27 23:13:08.749764128 +0200
+@@ -0,0 +1,150 @@
++/*
++ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*!
++ * @file mxc_dispdrv.c
++ * @brief mxc display driver framework.
++ *
++ * A display device driver could call mxc_dispdrv_register(drv) in its dev_probe() function.
++ * Move all dev_probe() things into mxc_dispdrv_driver->init(), init() function should init
++ * and feedback setting;
++ * Necessary deferred operations can be done in mxc_dispdrv_driver->post_init(),
++ * after dev_id and disp_id pass usage check;
++ * Move all dev_remove() things into mxc_dispdrv_driver->deinit();
++ * Move all dev_suspend() things into fb_notifier for SUSPEND, if there is;
++ * Move all dev_resume() things into fb_notifier for RESUME, if there is;
++ *
++ * ipuv3 fb driver could call mxc_dispdrv_gethandle(name, setting) before a fb
++ * need be added, with fbi param passing by setting, after
++ * mxc_dispdrv_gethandle() return, FB driver should get the basic setting
++ * about fbi info and ipuv3-hw (ipu_id and disp_id).
++ *
++ * @ingroup Framebuffer
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/list.h>
++#include <linux/mutex.h>
++#include <linux/slab.h>
++#include <linux/err.h>
++#include <linux/string.h>
++#include "mxc_dispdrv.h"
++
++static LIST_HEAD(dispdrv_list);
++static DEFINE_MUTEX(dispdrv_lock);
++
++struct mxc_dispdrv_entry {
++ /* Note: drv always the first element */
++ struct mxc_dispdrv_driver *drv;
++ bool active;
++ void *priv;
++ struct list_head list;
++};
++
++struct mxc_dispdrv_handle *mxc_dispdrv_register(struct mxc_dispdrv_driver *drv)
++{
++ struct mxc_dispdrv_entry *new;
++
++ mutex_lock(&dispdrv_lock);
++
++ new = kzalloc(sizeof(struct mxc_dispdrv_entry), GFP_KERNEL);
++ if (!new) {
++ mutex_unlock(&dispdrv_lock);
++ return ERR_PTR(-ENOMEM);
++ }
++
++ new->drv = drv;
++ list_add_tail(&new->list, &dispdrv_list);
++
++ mutex_unlock(&dispdrv_lock);
++
++ return (struct mxc_dispdrv_handle *)new;
++}
++EXPORT_SYMBOL_GPL(mxc_dispdrv_register);
++
++int mxc_dispdrv_unregister(struct mxc_dispdrv_handle *handle)
++{
++ struct mxc_dispdrv_entry *entry = (struct mxc_dispdrv_entry *)handle;
++
++ if (entry) {
++ mutex_lock(&dispdrv_lock);
++ list_del(&entry->list);
++ mutex_unlock(&dispdrv_lock);
++ kfree(entry);
++ return 0;
++ } else
++ return -EINVAL;
++}
++EXPORT_SYMBOL_GPL(mxc_dispdrv_unregister);
++
++struct mxc_dispdrv_handle *mxc_dispdrv_gethandle(char *name,
++ struct mxc_dispdrv_setting *setting)
++{
++ int ret, found = 0;
++ struct mxc_dispdrv_entry *entry;
++
++ mutex_lock(&dispdrv_lock);
++ list_for_each_entry(entry, &dispdrv_list, list) {
++ if (!strcmp(entry->drv->name, name) && (entry->drv->init)) {
++ ret = entry->drv->init((struct mxc_dispdrv_handle *)
++ entry, setting);
++ if (ret >= 0) {
++ entry->active = true;
++ found = 1;
++ break;
++ }
++ }
++ }
++ mutex_unlock(&dispdrv_lock);
++
++ return found ? (struct mxc_dispdrv_handle *)entry:ERR_PTR(-ENODEV);
++}
++EXPORT_SYMBOL_GPL(mxc_dispdrv_gethandle);
++
++void mxc_dispdrv_puthandle(struct mxc_dispdrv_handle *handle)
++{
++ struct mxc_dispdrv_entry *entry = (struct mxc_dispdrv_entry *)handle;
++
++ mutex_lock(&dispdrv_lock);
++ if (entry && entry->active && entry->drv->deinit) {
++ entry->drv->deinit(handle);
++ entry->active = false;
++ }
++ mutex_unlock(&dispdrv_lock);
++
++}
++EXPORT_SYMBOL_GPL(mxc_dispdrv_puthandle);
++
++int mxc_dispdrv_setdata(struct mxc_dispdrv_handle *handle, void *data)
++{
++ struct mxc_dispdrv_entry *entry = (struct mxc_dispdrv_entry *)handle;
++
++ if (entry) {
++ entry->priv = data;
++ return 0;
++ } else
++ return -EINVAL;
++}
++EXPORT_SYMBOL_GPL(mxc_dispdrv_setdata);
++
++void *mxc_dispdrv_getdata(struct mxc_dispdrv_handle *handle)
++{
++ struct mxc_dispdrv_entry *entry = (struct mxc_dispdrv_entry *)handle;
++
++ if (entry) {
++ return entry->priv;
++ } else
++ return ERR_PTR(-EINVAL);
++}
++EXPORT_SYMBOL_GPL(mxc_dispdrv_getdata);
+diff -Nur linux-4.1.3/drivers/video/mxc/mxc_dispdrv.h linux-xbian-imx6/drivers/video/mxc/mxc_dispdrv.h
+--- linux-4.1.3/drivers/video/mxc/mxc_dispdrv.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/video/mxc/mxc_dispdrv.h 2015-07-27 23:13:08.749764128 +0200
+@@ -0,0 +1,54 @@
++/*
++ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++#ifndef __MXC_DISPDRV_H__
++#define __MXC_DISPDRV_H__
++#include <linux/fb.h>
++
++struct mxc_dispdrv_handle {
++ struct mxc_dispdrv_driver *drv;
++};
++
++struct mxc_dispdrv_setting {
++ /*input-feedback parameter*/
++ struct fb_info *fbi;
++ int if_fmt;
++ int default_bpp;
++ char *dft_mode_str;
++
++ /*feedback parameter*/
++ int dev_id;
++ int disp_id;
++};
++
++struct mxc_dispdrv_driver {
++ const char *name;
++ int (*init) (struct mxc_dispdrv_handle *, struct mxc_dispdrv_setting *);
++ /* deferred operations after dev_id and disp_id pass usage check */
++ int (*post_init) (struct mxc_dispdrv_handle *, int dev_id, int disp_id);
++ void (*deinit) (struct mxc_dispdrv_handle *);
++ /* display driver enable function for extension */
++ int (*enable) (struct mxc_dispdrv_handle *);
++ /* display driver disable function, called at early part of fb_blank */
++ void (*disable) (struct mxc_dispdrv_handle *);
++ /* display driver setup function, called at early part of fb_set_par */
++ int (*setup) (struct mxc_dispdrv_handle *, struct fb_info *fbi);
++};
++
++struct mxc_dispdrv_handle *mxc_dispdrv_register(struct mxc_dispdrv_driver *drv);
++int mxc_dispdrv_unregister(struct mxc_dispdrv_handle *handle);
++struct mxc_dispdrv_handle *mxc_dispdrv_gethandle(char *name,
++ struct mxc_dispdrv_setting *setting);
++void mxc_dispdrv_puthandle(struct mxc_dispdrv_handle *handle);
++int mxc_dispdrv_setdata(struct mxc_dispdrv_handle *handle, void *data);
++void *mxc_dispdrv_getdata(struct mxc_dispdrv_handle *handle);
++#endif
+diff -Nur linux-4.1.3/drivers/video/mxc/mxc_edid.c linux-xbian-imx6/drivers/video/mxc/mxc_edid.c
+--- linux-4.1.3/drivers/video/mxc/mxc_edid.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/video/mxc/mxc_edid.c 2015-07-27 23:13:08.753749907 +0200
+@@ -0,0 +1,828 @@
++/*
++ * Copyright 2009-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*!
++ * @defgroup Framebuffer Framebuffer Driver for SDC and ADC.
++ */
++
++/*!
++ * @file mxc_edid.c
++ *
++ * @brief MXC EDID driver
++ *
++ * @ingroup Framebuffer
++ */
++
++/*!
++ * Include files
++ */
++#include <linux/i2c.h>
++#include <linux/fb.h>
++#include <video/mxc_edid.h>
++#include "../fbdev/edid.h"
++
++#undef DEBUG /* define this for verbose EDID parsing output */
++#ifdef DEBUG
++#define DPRINTK(fmt, args...) printk(fmt, ## args)
++#else
++#define DPRINTK(fmt, args...)
++#endif
++
++const struct fb_videomode mxc_cea_mode[64] = {
++ /* #1: 640x480p@59.94/60Hz 4:3 */
++ [1] = {
++ NULL, 60, 640, 480, 39722, 48, 16, 33, 10, 96, 2, 0,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_4_3, 0,
++ },
++ /* #2: 720x480p@59.94/60Hz 4:3 */
++ [2] = {
++ NULL, 60, 720, 480, 37037, 60, 16, 30, 9, 62, 6, 0,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_4_3, 0,
++ },
++ /* #3: 720x480p@59.94/60Hz 16:9 */
++ [3] = {
++ NULL, 60, 720, 480, 37037, 60, 16, 30, 9, 62, 6, 0,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_16_9, 0,
++ },
++ /* #4: 1280x720p@59.94/60Hz 16:9 */
++ [4] = {
++ NULL, 60, 1280, 720, 13468, 220, 110, 20, 5, 40, 5,
++ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_16_9, 0
++ },
++ /* #5: 1920x1080i@59.94/60Hz 16:9 */
++ [5] = {
++ NULL, 60, 1920, 1080, 13468, 88, 148, 4, 31, 44, 10,
++ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
++ FB_VMODE_INTERLACED | FB_VMODE_ASPECT_16_9, 0,
++ },
++ /* #6: 720(1440)x480iH@59.94/60Hz 4:3 */
++ [6] = {
++ NULL, 60, 1440, 480, 37037, 38, 114, 8, 31, 124, 6, 0,
++ FB_VMODE_INTERLACED | FB_VMODE_ASPECT_4_3, 0,
++ },
++ /* #7: 720(1440)x480iH@59.94/60Hz 16:9 */
++ [7] = {
++ NULL, 60, 1440, 480, 37037, 38, 114, 8, 31, 124, 6, 0,
++ FB_VMODE_INTERLACED | FB_VMODE_ASPECT_16_9, 0,
++ },
++ /* #8: 720(1440)x240pH@59.94/60Hz 4:3 */
++ [8] = {
++ NULL, 60, 1440, 240, 37108, 114, 38, 15, 4, 124, 3, 0,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_4_3, 0,
++ },
++ /* #9: 720(1440)x240pH@59.94/60Hz 16:9 */
++ [9] = {
++ NULL, 60, 1440, 240, 37108, 114, 38, 15, 4, 124, 3, 0,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_16_9, 0,
++ },
++ /* #14: 1440x480p@59.94/60Hz 4:3 */
++ [14] = {
++ NULL, 60, 1440, 480, 18500, 120, 32, 30, 9, 124, 6, 0,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_4_3, 0,
++ },
++ /* #15: 1440x480p@59.94/60Hz 16:9 */
++ [15] = {
++ NULL, 60, 1440, 480, 18500, 120, 32, 30, 9, 124, 6, 0,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_16_9, 0,
++ },
++ /* #16: 1920x1080p@60Hz 16:9 */
++ [16] = {
++ NULL, 60, 1920, 1080, 6734, 148, 88, 36, 4, 44, 5,
++ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_16_9, 0,
++ },
++ /* #17: 720x576pH@50Hz 4:3 */
++ [17] = {
++ NULL, 50, 720, 576, 37037, 68, 12, 39, 5, 64, 5, 0,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_4_3, 0,
++ },
++ /* #18: 720x576pH@50Hz 16:9 */
++ [18] = {
++ NULL, 50, 720, 576, 37037, 68, 12, 39, 5, 64, 5, 0,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_16_9, 0,
++ },
++ /* #19: 1280x720p@50Hz */
++ [19] = {
++ NULL, 50, 1280, 720, 13468, 220, 440, 20, 5, 40, 5,
++ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_16_9, 0,
++ },
++ /* #20: 1920x1080i@50Hz */
++ [20] = {
++ NULL, 50, 1920, 1080, 13468, 148, 528, 4, 31, 44, 10,
++ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
++ FB_VMODE_INTERLACED | FB_VMODE_ASPECT_16_9, 0,
++ },
++ /* #21: 720(1440)x576i@50Hz */
++ [21] = {
++ NULL, 50, 1440, 576, 37037, 24, 138, 4, 39, 126, 6, 0,
++ FB_VMODE_INTERLACED | FB_VMODE_ASPECT_4_3, 0,
++ },
++ /* #22: 720(1440)x576i@50Hz */
++ [22] = {
++ NULL, 50, 1440, 576, 37037, 24, 138, 4, 39, 126, 6, 0,
++ FB_VMODE_INTERLACED | FB_VMODE_ASPECT_16_9, 0,
++ },
++ /* #23: 720(1440)x288pH@50Hz 4:3 */
++ [23] = {
++ NULL, 50, 1440, 288, 37037, 138, 24, 19, 2, 126, 3, 0,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_4_3, 0,
++ },
++ /* #24: 720(1440)x288pH@50Hz 16:9 */
++ [24] = {
++ NULL, 50, 1440, 288, 37037, 138, 24, 19, 2, 126, 3, 0,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_16_9, 0,
++ },
++ /* #29: 720(1440)x576pH@50Hz 4:3 */
++ [29] = {
++ NULL, 50, 1440, 576, 18518, 136, 24, 39, 5, 128, 5, 0,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_4_3, 0,
++ },
++ /* #30: 720(1440)x576pH@50Hz 16:9 */
++ [30] = {
++ NULL, 50, 1440, 576, 18518, 136, 24, 39, 5, 128, 5, 0,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_16_9, 0,
++ },
++ /* #31: 1920x1080p@50Hz */
++ [31] = {
++ NULL, 50, 1920, 1080, 6734, 148, 528, 36, 4, 44, 5,
++ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_16_9, 0,
++ },
++ /* #32: 1920x1080p@23.98/24Hz */
++ [32] = {
++ NULL, 24, 1920, 1080, 13468, 148, 638, 36, 4, 44, 5,
++ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_16_9, 0,
++ },
++ /* #33: 1920x1080p@25Hz */
++ [33] = {
++ NULL, 25, 1920, 1080, 13468, 148, 528, 36, 4, 44, 5,
++ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_16_9, 0,
++ },
++ /* #34: 1920x1080p@30Hz */
++ [34] = {
++ NULL, 30, 1920, 1080, 13468, 148, 88, 36, 4, 44, 5,
++ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_16_9, 0,
++ },
++ /* #41: 1280x720p@100Hz 16:9 */
++ [41] = {
++ NULL, 100, 1280, 720, 6734, 220, 440, 20, 5, 40, 5,
++ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_16_9, 0
++ },
++ /* #47: 1280x720p@119.88/120Hz 16:9 */
++ [47] = {
++ NULL, 120, 1280, 720, 6734, 220, 110, 20, 5, 40, 5,
++ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_16_9, 0
++ },
++};
++
++/*
++ * We have a special version of fb_mode_is_equal that ignores
++ * pixclock, since for many CEA modes, 2 frequencies are supported
++ * e.g. 640x480 @ 60Hz or 59.94Hz
++ */
++int mxc_edid_fb_mode_is_equal(bool use_aspect,
++ const struct fb_videomode *mode1,
++ const struct fb_videomode *mode2,
++ u32 mode_mask)
++{
++ u32 mask;
++
++ if (use_aspect)
++ mask = ~0;
++ else
++ mask = ~FB_VMODE_ASPECT_MASK;
++
++ return (mode1->xres == mode2->xres &&
++ mode1->yres == mode2->yres &&
++ mode1->hsync_len == mode2->hsync_len &&
++ mode1->vsync_len == mode2->vsync_len &&
++ mode1->left_margin == mode2->left_margin &&
++ mode1->right_margin == mode2->right_margin &&
++ mode1->upper_margin == mode2->upper_margin &&
++ mode1->lower_margin == mode2->lower_margin &&
++ mode1->sync == mode2->sync &&
++ /* refresh check, 59.94Hz and 60Hz have the same parameter
++ * in struct of mxc_cea_mode */
++ abs(mode1->refresh - mode2->refresh) <= 1 &&
++ (mode1->vmode & mask & mode_mask) ==
++ (mode2->vmode & mask & mode_mask));
++}
++EXPORT_SYMBOL(mxc_edid_fb_mode_is_equal);
++
++static void get_detailed_timing(unsigned char *block,
++ struct fb_videomode *mode)
++{
++ mode->xres = H_ACTIVE;
++ mode->yres = V_ACTIVE;
++ mode->pixclock = PIXEL_CLOCK;
++ mode->pixclock /= 1000;
++ mode->pixclock = KHZ2PICOS(mode->pixclock);
++ mode->right_margin = H_SYNC_OFFSET;
++ mode->left_margin = (H_ACTIVE + H_BLANKING) -
++ (H_ACTIVE + H_SYNC_OFFSET + H_SYNC_WIDTH);
++ mode->upper_margin = V_BLANKING - V_SYNC_OFFSET -
++ V_SYNC_WIDTH;
++ mode->lower_margin = V_SYNC_OFFSET;
++ mode->hsync_len = H_SYNC_WIDTH;
++ mode->vsync_len = V_SYNC_WIDTH;
++ if (HSYNC_POSITIVE)
++ mode->sync |= FB_SYNC_HOR_HIGH_ACT;
++ if (VSYNC_POSITIVE)
++ mode->sync |= FB_SYNC_VERT_HIGH_ACT;
++ mode->refresh = PIXEL_CLOCK/((H_ACTIVE + H_BLANKING) *
++ (V_ACTIVE + V_BLANKING));
++ if (INTERLACED) {
++ mode->yres *= 2;
++ mode->upper_margin *= 2;
++ mode->lower_margin *= 2;
++ mode->vsync_len *= 2;
++ mode->vmode |= FB_VMODE_INTERLACED;
++ }
++ mode->flag = FB_MODE_IS_DETAILED;
++
++ if ((H_SIZE / 16) == (V_SIZE / 9))
++ mode->vmode |= FB_VMODE_ASPECT_16_9;
++ else if ((H_SIZE / 4) == (V_SIZE / 3))
++ mode->vmode |= FB_VMODE_ASPECT_4_3;
++ else if ((mode->xres / 16) == (mode->yres / 9))
++ mode->vmode |= FB_VMODE_ASPECT_16_9;
++ else if ((mode->xres / 4) == (mode->yres / 3))
++ mode->vmode |= FB_VMODE_ASPECT_4_3;
++
++ if (mode->vmode & FB_VMODE_ASPECT_16_9)
++ DPRINTK("Aspect ratio: 16:9\n");
++ if (mode->vmode & FB_VMODE_ASPECT_4_3)
++ DPRINTK("Aspect ratio: 4:3\n");
++ DPRINTK(" %d MHz ", PIXEL_CLOCK/1000000);
++ DPRINTK("%d %d %d %d ", H_ACTIVE, H_ACTIVE + H_SYNC_OFFSET,
++ H_ACTIVE + H_SYNC_OFFSET + H_SYNC_WIDTH, H_ACTIVE + H_BLANKING);
++ DPRINTK("%d %d %d %d ", V_ACTIVE, V_ACTIVE + V_SYNC_OFFSET,
++ V_ACTIVE + V_SYNC_OFFSET + V_SYNC_WIDTH, V_ACTIVE + V_BLANKING);
++ DPRINTK("%sHSync %sVSync\n\n", (HSYNC_POSITIVE) ? "+" : "-",
++ (VSYNC_POSITIVE) ? "+" : "-");
++}
++
++int mxc_edid_parse_ext_blk(unsigned char *edid,
++ struct mxc_edid_cfg *cfg,
++ struct fb_monspecs *specs)
++{
++ char detail_timing_desc_offset;
++ struct fb_videomode *mode, *m;
++ unsigned char index = 0x0;
++ unsigned char *block;
++ int i, num = 0, revision;
++
++ if (edid[index++] != 0x2) /* only support cea ext block now */
++ return -1;
++ revision = edid[index++];
++ DPRINTK("cea extent revision %d\n", revision);
++ mode = kzalloc(50 * sizeof(struct fb_videomode), GFP_KERNEL);
++ if (mode == NULL)
++ return -1;
++
++ detail_timing_desc_offset = edid[index++];
++
++ if (revision >= 2) {
++ cfg->cea_underscan = (edid[index] >> 7) & 0x1;
++ cfg->cea_basicaudio = (edid[index] >> 6) & 0x1;
++ cfg->cea_ycbcr444 = (edid[index] >> 5) & 0x1;
++ cfg->cea_ycbcr422 = (edid[index] >> 4) & 0x1;
++
++ DPRINTK("CEA underscan %d\n", cfg->cea_underscan);
++ DPRINTK("CEA basicaudio %d\n", cfg->cea_basicaudio);
++ DPRINTK("CEA ycbcr444 %d\n", cfg->cea_ycbcr444);
++ DPRINTK("CEA ycbcr422 %d\n", cfg->cea_ycbcr422);
++ }
++
++ if (revision >= 3) {
++ /* short desc */
++ DPRINTK("CEA Short desc timmings\n");
++ index++;
++ while (index < detail_timing_desc_offset) {
++ unsigned char tagcode, blklen;
++
++ tagcode = (edid[index] >> 5) & 0x7;
++ blklen = (edid[index]) & 0x1f;
++
++ DPRINTK("Tagcode %x Len %d\n", tagcode, blklen);
++
++ switch (tagcode) {
++ case 0x2: /*Video data block*/
++ {
++ int cea_idx;
++ i = 0;
++ while (i < blklen) {
++ index++;
++ cea_idx = edid[index] & 0x7f;
++ if (cea_idx < ARRAY_SIZE(mxc_cea_mode) &&
++ (mxc_cea_mode[cea_idx].xres)) {
++ DPRINTK("Support CEA Format #%d\n", cea_idx);
++ mode[num] = mxc_cea_mode[cea_idx];
++ mode[num].flag |= FB_MODE_IS_STANDARD;
++ num++;
++ }
++ i++;
++ }
++ break;
++ }
++ case 0x3: /*Vendor specific data*/
++ {
++ unsigned char IEEE_reg_iden[3];
++ unsigned char deep_color;
++ unsigned char latency_present;
++ unsigned char I_latency_present;
++ unsigned char hdmi_video_present;
++ unsigned char hdmi_3d_present;
++ unsigned char hdmi_3d_multi_present;
++ unsigned char hdmi_vic_len;
++ unsigned char hdmi_3d_len;
++ unsigned char index_inc = 0;
++ unsigned char vsd_end;
++
++ vsd_end = index + blklen;
++
++ IEEE_reg_iden[0] = edid[index+1];
++ IEEE_reg_iden[1] = edid[index+2];
++ IEEE_reg_iden[2] = edid[index+3];
++ cfg->physical_address[0] = (edid[index+4] & 0xf0) >> 4;
++ cfg->physical_address[1] = (edid[index+4] & 0x0f);
++ cfg->physical_address[2] = (edid[index+5] & 0xf0) >> 4;
++ cfg->physical_address[3] = (edid[index+5] & 0x0f);
++
++ if ((IEEE_reg_iden[0] == 0x03) &&
++ (IEEE_reg_iden[1] == 0x0c) &&
++ (IEEE_reg_iden[2] == 0x00))
++ cfg->hdmi_cap = 1;
++
++ if (blklen > 5) {
++ deep_color = edid[index+6];
++ if (deep_color & 0x80)
++ cfg->vsd_support_ai = true;
++ if (deep_color & 0x40)
++ cfg->vsd_dc_48bit = true;
++ if (deep_color & 0x20)
++ cfg->vsd_dc_36bit = true;
++ if (deep_color & 0x10)
++ cfg->vsd_dc_30bit = true;
++ if (deep_color & 0x08)
++ cfg->vsd_dc_y444 = true;
++ if (deep_color & 0x01)
++ cfg->vsd_dvi_dual = true;
++ }
++
++ DPRINTK("VSD hdmi capability %d\n", cfg->hdmi_cap);
++ DPRINTK("VSD support ai %d\n", cfg->vsd_support_ai);
++ DPRINTK("VSD support deep color 48bit %d\n", cfg->vsd_dc_48bit);
++ DPRINTK("VSD support deep color 36bit %d\n", cfg->vsd_dc_36bit);
++ DPRINTK("VSD support deep color 30bit %d\n", cfg->vsd_dc_30bit);
++ DPRINTK("VSD support deep color y444 %d\n", cfg->vsd_dc_y444);
++ DPRINTK("VSD support dvi dual %d\n", cfg->vsd_dvi_dual);
++
++ if (blklen > 6)
++ cfg->vsd_max_tmdsclk_rate = edid[index+7] * 5;
++ DPRINTK("VSD MAX TMDS CLOCK RATE %d\n", cfg->vsd_max_tmdsclk_rate);
++
++ if (blklen > 7) {
++ latency_present = edid[index+8] >> 7;
++ I_latency_present = (edid[index+8] & 0x40) >> 6;
++ hdmi_video_present = (edid[index+8] & 0x20) >> 5;
++ cfg->vsd_cnc3 = (edid[index+8] & 0x8) >> 3;
++ cfg->vsd_cnc2 = (edid[index+8] & 0x4) >> 2;
++ cfg->vsd_cnc1 = (edid[index+8] & 0x2) >> 1;
++ cfg->vsd_cnc0 = edid[index+8] & 0x1;
++
++ DPRINTK("VSD cnc0 %d\n", cfg->vsd_cnc0);
++ DPRINTK("VSD cnc1 %d\n", cfg->vsd_cnc1);
++ DPRINTK("VSD cnc2 %d\n", cfg->vsd_cnc2);
++ DPRINTK("VSD cnc3 %d\n", cfg->vsd_cnc3);
++ DPRINTK("latency_present %d\n", latency_present);
++ DPRINTK("I_latency_present %d\n", I_latency_present);
++ DPRINTK("hdmi_video_present %d\n", hdmi_video_present);
++
++ } else {
++ index += blklen;
++ break;
++ }
++
++ index += 9;
++
++ /*latency present */
++ if (latency_present) {
++ cfg->vsd_video_latency = edid[index++];
++ cfg->vsd_audio_latency = edid[index++];
++
++ if (I_latency_present) {
++ cfg->vsd_I_video_latency = edid[index++];
++ cfg->vsd_I_audio_latency = edid[index++];
++ } else {
++ cfg->vsd_I_video_latency = cfg->vsd_video_latency;
++ cfg->vsd_I_audio_latency = cfg->vsd_audio_latency;
++ }
++
++ DPRINTK("VSD latency video_latency %d\n", cfg->vsd_video_latency);
++ DPRINTK("VSD latency audio_latency %d\n", cfg->vsd_audio_latency);
++ DPRINTK("VSD latency I_video_latency %d\n", cfg->vsd_I_video_latency);
++ DPRINTK("VSD latency I_audio_latency %d\n", cfg->vsd_I_audio_latency);
++ }
++
++ if (hdmi_video_present) {
++ hdmi_3d_present = edid[index] >> 7;
++ hdmi_3d_multi_present = (edid[index] & 0x60) >> 5;
++ index++;
++ hdmi_vic_len = (edid[index] & 0xe0) >> 5;
++ hdmi_3d_len = edid[index] & 0x1f;
++ index++;
++
++ DPRINTK("hdmi_3d_present %d\n", hdmi_3d_present);
++ DPRINTK("hdmi_3d_multi_present %d\n", hdmi_3d_multi_present);
++ DPRINTK("hdmi_vic_len %d\n", hdmi_vic_len);
++ DPRINTK("hdmi_3d_len %d\n", hdmi_3d_len);
++
++ if (hdmi_vic_len > 0) {
++ for (i = 0; i < hdmi_vic_len; i++) {
++ cfg->hdmi_vic[i] = edid[index++];
++ DPRINTK("HDMI_vic=%d\n", cfg->hdmi_vic[i]);
++ }
++ }
++
++ if (hdmi_3d_len > 0) {
++ if (hdmi_3d_present) {
++ cfg->hdmi_3d_present = hdmi_3d_present;
++ if (hdmi_3d_multi_present == 0x1) {
++ cfg->hdmi_3d_struct_all = (edid[index] << 8) | edid[index+1];
++ index_inc = 2;
++ } else if (hdmi_3d_multi_present == 0x2) {
++ cfg->hdmi_3d_struct_all = (edid[index] << 8) | edid[index+1];
++ cfg->hdmi_3d_mask_all = (edid[index+2] << 8) | edid[index+3];
++ index_inc = 4;
++ } else
++ index_inc = 0;
++ cfg->hdmi_3d_len = hdmi_3d_len - index_inc;
++ cfg->hdmi_3d_multi_present = hdmi_3d_multi_present;
++ }
++
++ DPRINTK("HDMI 3d struct all =0x%x\n", cfg->hdmi_3d_struct_all);
++ DPRINTK("HDMI 3d mask all =0x%x\n", cfg->hdmi_3d_mask_all);
++
++ /* Read 2D vic 3D_struct */
++ if ((hdmi_3d_len - index_inc) > 0) {
++ DPRINTK("Support 3D video format\n");
++ i = 0;
++ while ((hdmi_3d_len - index_inc) > 0) {
++
++ cfg->hdmi_3d_format[i].vic_order_2d = edid[index+index_inc] >> 4;
++ cfg->hdmi_3d_format[i].struct_3d = edid[index+index_inc] & 0x0f;
++ index_inc++;
++
++ if (cfg->hdmi_3d_format[i].struct_3d == 8) {
++ cfg->hdmi_3d_format[i].detail_3d = edid[index+index_inc] >> 4;
++ index_inc++;
++ } else if (cfg->hdmi_3d_format[i].struct_3d > 8) {
++ cfg->hdmi_3d_format[i].detail_3d = 0;
++ index_inc++;
++ }
++
++ DPRINTK("vic_order_2d=%d, 3d_struct=%d, 3d_detail=0x%x\n",
++ cfg->hdmi_3d_format[i].vic_order_2d,
++ cfg->hdmi_3d_format[i].struct_3d,
++ cfg->hdmi_3d_format[i].detail_3d);
++ i++;
++ }
++ }
++ index += index_inc;
++ }
++ }
++
++ index = vsd_end;
++
++ break;
++ }
++ case 0x1: /*Audio data block*/
++ {
++ u8 audio_format, max_ch, byte1, byte2, byte3;
++
++ i = 0;
++ cfg->max_channels = 0;
++ cfg->sample_rates = 0;
++ cfg->sample_sizes = 0;
++
++ while (i < blklen) {
++ byte1 = edid[index + 1];
++ byte2 = edid[index + 2];
++ byte3 = edid[index + 3];
++ index += 3;
++ i += 3;
++
++ audio_format = byte1 >> 3;
++ max_ch = (byte1 & 0x07) + 1;
++
++ DPRINTK("Audio Format Descriptor : %2d\n", audio_format);
++ DPRINTK("Max Number of Channels : %2d\n", max_ch);
++ DPRINTK("Sample Rates : %02x\n", byte2);
++
++ /* ALSA can't specify specific compressed
++ * formats, so only care about PCM for now. */
++ if (audio_format == AUDIO_CODING_TYPE_LPCM) {
++ if (max_ch > cfg->max_channels)
++ cfg->max_channels = max_ch;
++
++ cfg->sample_rates |= byte2;
++ cfg->sample_sizes |= byte3 & 0x7;
++ DPRINTK("Sample Sizes : %02x\n",
++ byte3 & 0x7);
++ }
++ }
++ break;
++ }
++ case 0x4: /*Speaker allocation block*/
++ {
++ i = 0;
++ while (i < blklen) {
++ cfg->speaker_alloc = edid[index + 1];
++ index += 3;
++ i += 3;
++ DPRINTK("Speaker Alloc : %02x\n", cfg->speaker_alloc);
++ }
++ break;
++ }
++ case 0x7: /*User extended block*/
++ default:
++ /* skip */
++ DPRINTK("Not handle block, tagcode = 0x%x\n", tagcode);
++ index += blklen;
++ break;
++ }
++
++ index++;
++ }
++ }
++
++ /* long desc */
++ DPRINTK("CEA long desc timmings\n");
++ index = detail_timing_desc_offset;
++ block = edid + index;
++ while (index < (EDID_LENGTH - DETAILED_TIMING_DESCRIPTION_SIZE)) {
++ if (!(block[0] == 0x00 && block[1] == 0x00)) {
++ get_detailed_timing(block, &mode[num]);
++ num++;
++ }
++ block += DETAILED_TIMING_DESCRIPTION_SIZE;
++ index += DETAILED_TIMING_DESCRIPTION_SIZE;
++ }
++
++ if (!num) {
++ kfree(mode);
++ return 0;
++ }
++
++ m = kmalloc((num + specs->modedb_len) *
++ sizeof(struct fb_videomode), GFP_KERNEL);
++ if (!m)
++ return 0;
++
++ if (specs->modedb_len) {
++ memmove(m, specs->modedb,
++ specs->modedb_len * sizeof(struct fb_videomode));
++ kfree(specs->modedb);
++ }
++ memmove(m+specs->modedb_len, mode,
++ num * sizeof(struct fb_videomode));
++ kfree(mode);
++
++ specs->modedb_len += num;
++ specs->modedb = m;
++
++ return 0;
++}
++EXPORT_SYMBOL(mxc_edid_parse_ext_blk);
++
++static int mxc_edid_readblk(struct i2c_adapter *adp,
++ unsigned short addr, unsigned char *edid)
++{
++ int ret = 0, extblknum = 0;
++ unsigned char regaddr = 0x0;
++ struct i2c_msg msg[2] = {
++ {
++ .addr = addr,
++ .flags = 0,
++ .len = 1,
++ .buf = &regaddr,
++ }, {
++ .addr = addr,
++ .flags = I2C_M_RD,
++ .len = EDID_LENGTH,
++ .buf = edid,
++ },
++ };
++
++ ret = i2c_transfer(adp, msg, ARRAY_SIZE(msg));
++ if (ret != ARRAY_SIZE(msg)) {
++ DPRINTK("unable to read EDID block\n");
++ return -EIO;
++ }
++
++ if (edid[1] == 0x00)
++ return -ENOENT;
++
++ extblknum = edid[0x7E];
++
++ if (extblknum) {
++ regaddr = 128;
++ msg[1].buf = edid + EDID_LENGTH;
++
++ ret = i2c_transfer(adp, msg, ARRAY_SIZE(msg));
++ if (ret != ARRAY_SIZE(msg)) {
++ DPRINTK("unable to read EDID ext block\n");
++ return -EIO;
++ }
++ }
++
++ return extblknum;
++}
++
++static int mxc_edid_readsegblk(struct i2c_adapter *adp, unsigned short addr,
++ unsigned char *edid, int seg_num)
++{
++ int ret = 0;
++ unsigned char segment = 0x1, regaddr = 0;
++ struct i2c_msg msg[3] = {
++ {
++ .addr = 0x30,
++ .flags = 0,
++ .len = 1,
++ .buf = &segment,
++ }, {
++ .addr = addr,
++ .flags = 0,
++ .len = 1,
++ .buf = &regaddr,
++ }, {
++ .addr = addr,
++ .flags = I2C_M_RD,
++ .len = EDID_LENGTH,
++ .buf = edid,
++ },
++ };
++
++ ret = i2c_transfer(adp, msg, ARRAY_SIZE(msg));
++ if (ret != ARRAY_SIZE(msg)) {
++ DPRINTK("unable to read EDID block\n");
++ return -EIO;
++ }
++
++ if (seg_num == 2) {
++ regaddr = 128;
++ msg[2].buf = edid + EDID_LENGTH;
++
++ ret = i2c_transfer(adp, msg, ARRAY_SIZE(msg));
++ if (ret != ARRAY_SIZE(msg)) {
++ DPRINTK("unable to read EDID block\n");
++ return -EIO;
++ }
++ }
++
++ return ret;
++}
++
++int mxc_edid_var_to_vic(struct fb_var_screeninfo *var)
++{
++ int i;
++ struct fb_videomode m;
++
++ for (i = 0; i < ARRAY_SIZE(mxc_cea_mode); i++) {
++ fb_var_to_videomode(&m, var);
++ if (mxc_edid_fb_mode_is_equal(false, &m, &mxc_cea_mode[i], FB_VMODE_MASK))
++ break;
++ }
++
++ if (i == ARRAY_SIZE(mxc_cea_mode))
++ return 0;
++
++ return i;
++}
++EXPORT_SYMBOL(mxc_edid_var_to_vic);
++
++int mxc_edid_mode_to_vic(const struct fb_videomode *mode, u32 mode_mask)
++{
++ int i;
++ bool use_aspect = (mode->vmode & FB_VMODE_ASPECT_MASK);
++ u32 use_mask = mode_mask ? mode_mask : FB_VMODE_MASK ^ (FB_VMODE_3D_MASK | FB_VMODE_FRACTIONAL);
++
++ for (i = 0; i < ARRAY_SIZE(mxc_cea_mode); i++) {
++ if (mxc_edid_fb_mode_is_equal(use_aspect, mode, &mxc_cea_mode[i], use_mask))
++ break;
++ }
++
++ if (i == ARRAY_SIZE(mxc_cea_mode))
++ return 0;
++
++ return i;
++}
++EXPORT_SYMBOL(mxc_edid_mode_to_vic);
++
++/* make sure edid has 512 bytes*/
++int mxc_edid_read(struct i2c_adapter *adp, unsigned short addr,
++ unsigned char *edid, struct mxc_edid_cfg *cfg, struct fb_info *fbi)
++{
++ int ret = 0, extblknum;
++ if (!adp || !edid || !cfg || !fbi)
++ return -EINVAL;
++
++ memset(edid, 0, EDID_LENGTH*4);
++ memset(cfg, 0, sizeof(struct mxc_edid_cfg));
++
++ extblknum = mxc_edid_readblk(adp, addr, edid);
++ if (extblknum < 0)
++ return extblknum;
++
++ /* edid first block parsing */
++ memset(&fbi->monspecs, 0, sizeof(fbi->monspecs));
++ fb_edid_to_monspecs(edid, &fbi->monspecs);
++
++ if (extblknum) {
++ int i;
++
++ /* need read segment block? */
++ if (extblknum > 1) {
++ ret = mxc_edid_readsegblk(adp, addr,
++ edid + EDID_LENGTH*2, extblknum - 1);
++ if (ret < 0)
++ return ret;
++ }
++
++ for (i = 1; i <= extblknum; i++)
++ /* edid ext block parsing */
++ mxc_edid_parse_ext_blk(edid + i*EDID_LENGTH,
++ cfg, &fbi->monspecs);
++ }
++
++ return 0;
++}
++EXPORT_SYMBOL(mxc_edid_read);
++
++const struct fb_videomode *mxc_fb_find_nearest_mode(const struct fb_videomode *mode,
++ struct list_head *head)
++{
++ struct list_head *pos;
++ struct fb_modelist *modelist;
++ struct fb_videomode *cmode, *best = NULL;
++ u32 diff = -1, diff_refresh = -1;
++
++ list_for_each(pos, head) {
++ u32 d;
++
++ modelist = list_entry(pos, struct fb_modelist, list);
++ cmode = &modelist->mode;
++
++ if (!(mode->vmode & FB_VMODE_3D_MASK) &&
++ (cmode->vmode & FB_VMODE_3D_MASK))
++ continue;
++ if ((mode->vmode & FB_VMODE_3D_MASK) &&
++ ((mode->vmode & FB_VMODE_3D_MASK) != (cmode->vmode & FB_VMODE_3D_MASK)))
++ continue;
++
++ if ((mode->vmode & FB_VMODE_MASK_SIMPLE) != (cmode->vmode & FB_VMODE_MASK_SIMPLE))
++ continue;
++
++ if ((mode->vmode & FB_VMODE_ASPECT_MASK) &&
++ ((mode->vmode & FB_VMODE_ASPECT_MASK) != (cmode->vmode & FB_VMODE_ASPECT_MASK)))
++ continue;
++
++ if ((mode->vmode & FB_VMODE_FRACTIONAL) != (cmode->vmode & FB_VMODE_FRACTIONAL))
++ continue;
++
++ d = abs(cmode->xres - mode->xres) +
++ abs(cmode->yres - mode->yres);
++ if (diff > d) {
++ diff = d;
++ diff_refresh = abs(cmode->refresh - mode->refresh);
++ best = cmode;
++ } else if (diff == d) {
++ d = abs(cmode->refresh - mode->refresh);
++ if (diff_refresh > d) {
++ diff_refresh = d;
++ best = cmode;
++ }
++ }
++ }
++
++ return best;
++}
++EXPORT_SYMBOL(mxc_fb_find_nearest_mode);
+diff -Nur linux-4.1.3/drivers/video/mxc/mxcfb_hx8369_wvga.c linux-xbian-imx6/drivers/video/mxc/mxcfb_hx8369_wvga.c
+--- linux-4.1.3/drivers/video/mxc/mxcfb_hx8369_wvga.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/video/mxc/mxcfb_hx8369_wvga.c 2015-07-27 23:13:08.753749907 +0200
+@@ -0,0 +1,449 @@
++/*
++ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++#include <linux/types.h>
++#include <linux/init.h>
++#include <linux/delay.h>
++#include <linux/platform_device.h>
++#include <linux/err.h>
++#include <linux/clk.h>
++#include <linux/console.h>
++#include <linux/io.h>
++#include <linux/bitops.h>
++#include <linux/spinlock.h>
++#include <linux/mipi_dsi.h>
++#include <linux/mxcfb.h>
++#include <linux/backlight.h>
++#include <video/mipi_display.h>
++
++#include "mipi_dsi.h"
++
++#define MIPI_DSI_MAX_RET_PACK_SIZE (0x4)
++
++#define HX8369BL_MAX_BRIGHT (255)
++#define HX8369BL_DEF_BRIGHT (255)
++
++#define HX8369_MAX_DPHY_CLK (800)
++#define HX8369_ONE_DATA_LANE (0x1)
++#define HX8369_TWO_DATA_LANE (0x2)
++
++#define HX8369_CMD_SETEXTC (0xB9)
++#define HX8369_CMD_SETEXTC_LEN (0x4)
++#define HX8369_CMD_SETEXTC_PARAM_1 (0x6983ff)
++
++#define HX8369_CMD_GETHXID (0xF4)
++#define HX8369_CMD_GETHXID_LEN (0x4)
++#define HX8369_ID (0x69)
++#define HX8369_ID_MASK (0xFF)
++
++#define HX8369_CMD_SETDISP (0xB2)
++#define HX8369_CMD_SETDISP_LEN (16)
++#define HX8369_CMD_SETDISP_1_HALT (0x00)
++#define HX8369_CMD_SETDISP_2_RES_MODE (0x23)
++#define HX8369_CMD_SETDISP_3_BP (0x03)
++#define HX8369_CMD_SETDISP_4_FP (0x03)
++#define HX8369_CMD_SETDISP_5_SAP (0x70)
++#define HX8369_CMD_SETDISP_6_GENON (0x00)
++#define HX8369_CMD_SETDISP_7_GENOFF (0xff)
++#define HX8369_CMD_SETDISP_8_RTN (0x00)
++#define HX8369_CMD_SETDISP_9_TEI (0x00)
++#define HX8369_CMD_SETDISP_10_TEP_UP (0x00)
++#define HX8369_CMD_SETDISP_11_TEP_LOW (0x00)
++#define HX8369_CMD_SETDISP_12_BP_PE (0x03)
++#define HX8369_CMD_SETDISP_13_FP_PE (0x03)
++#define HX8369_CMD_SETDISP_14_RTN_PE (0x00)
++#define HX8369_CMD_SETDISP_15_GON (0x01)
++
++#define HX8369_CMD_SETCYC (0xB4)
++#define HX8369_CMD_SETCYC_LEN (6)
++#define HX8369_CMD_SETCYC_PARAM_1 (0x5f1d00)
++#define HX8369_CMD_SETCYC_PARAM_2 (0x060e)
++
++#define HX8369_CMD_SETGIP (0xD5)
++#define HX8369_CMD_SETGIP_LEN (27)
++#define HX8369_CMD_SETGIP_PARAM_1 (0x030400)
++#define HX8369_CMD_SETGIP_PARAM_2 (0x1c050100)
++#define HX8369_CMD_SETGIP_PARAM_3 (0x00030170)
++#define HX8369_CMD_SETGIP_PARAM_4 (0x51064000)
++#define HX8369_CMD_SETGIP_PARAM_5 (0x41000007)
++#define HX8369_CMD_SETGIP_PARAM_6 (0x07075006)
++#define HX8369_CMD_SETGIP_PARAM_7 (0x040f)
++
++#define HX8369_CMD_SETPOWER (0xB1)
++#define HX8369_CMD_SETPOWER_LEN (20)
++#define HX8369_CMD_SETPOWER_PARAM_1 (0x340001)
++#define HX8369_CMD_SETPOWER_PARAM_2 (0x0f0f0006)
++#define HX8369_CMD_SETPOWER_PARAM_3 (0x3f3f322a)
++#define HX8369_CMD_SETPOWER_PARAM_4 (0xe6013a07)
++#define HX8369_CMD_SETPOWER_PARAM_5 (0xe6e6e6e6)
++
++#define HX8369_CMD_SETVCOM (0xB6)
++#define HX8369_CMD_SETVCOM_LEN (3)
++#define HX8369_CMD_SETVCOM_PARAM_1 (0x5656)
++
++#define HX8369_CMD_SETPANEL (0xCC)
++#define HX8369_CMD_SETPANEL_PARAM_1 (0x02)
++
++#define HX8369_CMD_SETGAMMA (0xE0)
++#define HX8369_CMD_SETGAMMA_LEN (35)
++#define HX8369_CMD_SETGAMMA_PARAM_1 (0x221d00)
++#define HX8369_CMD_SETGAMMA_PARAM_2 (0x2e3f3d38)
++#define HX8369_CMD_SETGAMMA_PARAM_3 (0x0f0d064a)
++#define HX8369_CMD_SETGAMMA_PARAM_4 (0x16131513)
++#define HX8369_CMD_SETGAMMA_PARAM_5 (0x1d001910)
++#define HX8369_CMD_SETGAMMA_PARAM_6 (0x3f3d3822)
++#define HX8369_CMD_SETGAMMA_PARAM_7 (0x0d064a2e)
++#define HX8369_CMD_SETGAMMA_PARAM_8 (0x1315130f)
++#define HX8369_CMD_SETGAMMA_PARAM_9 (0x191016)
++
++#define HX8369_CMD_SETMIPI (0xBA)
++#define HX8369_CMD_SETMIPI_LEN (14)
++#define HX8369_CMD_SETMIPI_PARAM_1 (0xc6a000)
++#define HX8369_CMD_SETMIPI_PARAM_2 (0x10000a00)
++#define HX8369_CMD_SETMIPI_ONELANE (0x10 << 24)
++#define HX8369_CMD_SETMIPI_TWOLANE (0x11 << 24)
++#define HX8369_CMD_SETMIPI_PARAM_3 (0x00026f30)
++#define HX8369_CMD_SETMIPI_PARAM_4 (0x4018)
++
++#define HX8369_CMD_SETPIXEL_FMT (0x3A)
++#define HX8369_CMD_SETPIXEL_FMT_24BPP (0x77)
++#define HX8369_CMD_SETPIXEL_FMT_18BPP (0x66)
++#define HX8369_CMD_SETPIXEL_FMT_16BPP (0x55)
++
++#define HX8369_CMD_SETCLUMN_ADDR (0x2A)
++#define HX8369_CMD_SETCLUMN_ADDR_LEN (5)
++#define HX8369_CMD_SETCLUMN_ADDR_PARAM_1 (0xdf0000)
++#define HX8369_CMD_SETCLUMN_ADDR_PARAM_2 (0x01)
++
++#define HX8369_CMD_SETPAGE_ADDR (0x2B)
++#define HX8369_CMD_SETPAGE_ADDR_LEN (5)
++#define HX8369_CMD_SETPAGE_ADDR_PARAM_1 (0x1f0000)
++#define HX8369_CMD_SETPAGE_ADDR_PARAM_2 (0x03)
++
++#define HX8369_CMD_WRT_DISP_BRIGHT (0x51)
++#define HX8369_CMD_WRT_DISP_BRIGHT_PARAM_1 (0xFF)
++
++#define HX8369_CMD_WRT_CABC_MIN_BRIGHT (0x5E)
++#define HX8369_CMD_WRT_CABC_MIN_BRIGHT_PARAM_1 (0x20)
++
++#define HX8369_CMD_WRT_CABC_CTRL (0x55)
++#define HX8369_CMD_WRT_CABC_CTRL_PARAM_1 (0x1)
++
++#define HX8369_CMD_WRT_CTRL_DISP (0x53)
++#define HX8369_CMD_WRT_CTRL_DISP_PARAM_1 (0x24)
++
++#define CHECK_RETCODE(ret) \
++do { \
++ if (ret < 0) { \
++ dev_err(&mipi_dsi->pdev->dev, \
++ "%s ERR: ret:%d, line:%d.\n", \
++ __func__, ret, __LINE__); \
++ return ret; \
++ } \
++} while (0)
++
++static int hx8369bl_brightness;
++static int mipid_init_backlight(struct mipi_dsi_info *mipi_dsi);
++
++static struct fb_videomode truly_lcd_modedb[] = {
++ {
++ "TRULY-WVGA", 64, 480, 800, 37880,
++ 8, 8,
++ 6, 6,
++ 8, 6,
++ FB_SYNC_OE_LOW_ACT,
++ FB_VMODE_NONINTERLACED,
++ 0,
++ },
++};
++
++static struct mipi_lcd_config lcd_config = {
++ .virtual_ch = 0x0,
++ .data_lane_num = HX8369_TWO_DATA_LANE,
++ .max_phy_clk = HX8369_MAX_DPHY_CLK,
++ .dpi_fmt = MIPI_RGB888,
++};
++void mipid_hx8369_get_lcd_videomode(struct fb_videomode **mode, int *size,
++ struct mipi_lcd_config **data)
++{
++ *mode = &truly_lcd_modedb[0];
++ *size = ARRAY_SIZE(truly_lcd_modedb);
++ *data = &lcd_config;
++}
++
++int mipid_hx8369_lcd_setup(struct mipi_dsi_info *mipi_dsi)
++{
++ u32 buf[DSI_CMD_BUF_MAXSIZE];
++ int err;
++
++ dev_dbg(&mipi_dsi->pdev->dev, "MIPI DSI LCD setup.\n");
++ buf[0] = HX8369_CMD_SETEXTC | (HX8369_CMD_SETEXTC_PARAM_1 << 8);
++ err = mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_LONG_WRITE,
++ buf, HX8369_CMD_SETEXTC_LEN);
++ CHECK_RETCODE(err);
++ buf[0] = MIPI_DSI_MAX_RET_PACK_SIZE;
++ err = mipi_dsi_pkt_write(mipi_dsi,
++ MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE,
++ buf, 0);
++ CHECK_RETCODE(err);
++ buf[0] = HX8369_CMD_GETHXID;
++ err = mipi_dsi_pkt_read(mipi_dsi,
++ MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM,
++ buf, HX8369_CMD_GETHXID_LEN);
++ if (!err && ((buf[0] & HX8369_ID_MASK) == HX8369_ID)) {
++ dev_info(&mipi_dsi->pdev->dev,
++ "MIPI DSI LCD ID:0x%x.\n", buf[0]);
++ } else {
++ dev_err(&mipi_dsi->pdev->dev,
++ "mipi_dsi_pkt_read err:%d, data:0x%x.\n",
++ err, buf[0]);
++ dev_info(&mipi_dsi->pdev->dev,
++ "MIPI DSI LCD not detected!\n");
++ return err;
++ }
++
++ /* set LCD resolution as 480RGBx800, DPI interface,
++ * display operation mode: RGB data bypass GRAM mode.
++ */
++ buf[0] = HX8369_CMD_SETDISP | (HX8369_CMD_SETDISP_1_HALT << 8) |
++ (HX8369_CMD_SETDISP_2_RES_MODE << 16) |
++ (HX8369_CMD_SETDISP_3_BP << 24);
++ buf[1] = HX8369_CMD_SETDISP_4_FP | (HX8369_CMD_SETDISP_5_SAP << 8) |
++ (HX8369_CMD_SETDISP_6_GENON << 16) |
++ (HX8369_CMD_SETDISP_7_GENOFF << 24);
++ buf[2] = HX8369_CMD_SETDISP_8_RTN | (HX8369_CMD_SETDISP_9_TEI << 8) |
++ (HX8369_CMD_SETDISP_10_TEP_UP << 16) |
++ (HX8369_CMD_SETDISP_11_TEP_LOW << 24);
++ buf[3] = HX8369_CMD_SETDISP_12_BP_PE |
++ (HX8369_CMD_SETDISP_13_FP_PE << 8) |
++ (HX8369_CMD_SETDISP_14_RTN_PE << 16) |
++ (HX8369_CMD_SETDISP_15_GON << 24);
++ err = mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_LONG_WRITE,
++ buf, HX8369_CMD_SETDISP_LEN);
++ CHECK_RETCODE(err);
++
++ /* Set display waveform cycle */
++ buf[0] = HX8369_CMD_SETCYC | (HX8369_CMD_SETCYC_PARAM_1 << 8);
++ buf[1] = HX8369_CMD_SETCYC_PARAM_2;
++ err = mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_LONG_WRITE,
++ buf, HX8369_CMD_SETCYC_LEN);
++ CHECK_RETCODE(err);
++
++ /* Set GIP timing output control */
++ buf[0] = HX8369_CMD_SETGIP | (HX8369_CMD_SETGIP_PARAM_1 << 8);
++ buf[1] = HX8369_CMD_SETGIP_PARAM_2;
++ buf[2] = HX8369_CMD_SETGIP_PARAM_3;
++ buf[3] = HX8369_CMD_SETGIP_PARAM_4;
++ buf[4] = HX8369_CMD_SETGIP_PARAM_5;
++ buf[5] = HX8369_CMD_SETGIP_PARAM_6;
++ buf[6] = HX8369_CMD_SETGIP_PARAM_7;
++ err = mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_LONG_WRITE, buf,
++ HX8369_CMD_SETGIP_LEN);
++ CHECK_RETCODE(err);
++
++ /* Set power: standby, DC etc. */
++ buf[0] = HX8369_CMD_SETPOWER | (HX8369_CMD_SETPOWER_PARAM_1 << 8);
++ buf[1] = HX8369_CMD_SETPOWER_PARAM_2;
++ buf[2] = HX8369_CMD_SETPOWER_PARAM_3;
++ buf[3] = HX8369_CMD_SETPOWER_PARAM_4;
++ buf[4] = HX8369_CMD_SETPOWER_PARAM_5;
++ err = mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_LONG_WRITE, buf,
++ HX8369_CMD_SETPOWER_LEN);
++ CHECK_RETCODE(err);
++
++ /* Set VCOM voltage. */
++ buf[0] = HX8369_CMD_SETVCOM | (HX8369_CMD_SETVCOM_PARAM_1 << 8);
++ err = mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_LONG_WRITE, buf,
++ HX8369_CMD_SETVCOM_LEN);
++ CHECK_RETCODE(err);
++
++ /* Set Panel: BGR/RGB or Inversion. */
++ buf[0] = HX8369_CMD_SETPANEL | (HX8369_CMD_SETPANEL_PARAM_1 << 8);
++ err = mipi_dsi_pkt_write(mipi_dsi,
++ MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM, buf, 0);
++ CHECK_RETCODE(err);
++
++ /* Set gamma curve related setting */
++ buf[0] = HX8369_CMD_SETGAMMA | (HX8369_CMD_SETGAMMA_PARAM_1 << 8);
++ buf[1] = HX8369_CMD_SETGAMMA_PARAM_2;
++ buf[2] = HX8369_CMD_SETGAMMA_PARAM_3;
++ buf[3] = HX8369_CMD_SETGAMMA_PARAM_4;
++ buf[4] = HX8369_CMD_SETGAMMA_PARAM_5;
++ buf[5] = HX8369_CMD_SETGAMMA_PARAM_6;
++ buf[7] = HX8369_CMD_SETGAMMA_PARAM_7;
++ buf[7] = HX8369_CMD_SETGAMMA_PARAM_8;
++ buf[8] = HX8369_CMD_SETGAMMA_PARAM_9;
++ err = mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_LONG_WRITE, buf,
++ HX8369_CMD_SETGAMMA_LEN);
++ CHECK_RETCODE(err);
++
++ /* Set MIPI: DPHYCMD & DSICMD, data lane number */
++ buf[0] = HX8369_CMD_SETMIPI | (HX8369_CMD_SETMIPI_PARAM_1 << 8);
++ buf[1] = HX8369_CMD_SETMIPI_PARAM_2;
++ buf[2] = HX8369_CMD_SETMIPI_PARAM_3;
++ if (lcd_config.data_lane_num == HX8369_ONE_DATA_LANE)
++ buf[2] |= HX8369_CMD_SETMIPI_ONELANE;
++ else
++ buf[2] |= HX8369_CMD_SETMIPI_TWOLANE;
++ buf[3] = HX8369_CMD_SETMIPI_PARAM_4;
++ err = mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_LONG_WRITE, buf,
++ HX8369_CMD_SETMIPI_LEN);
++ CHECK_RETCODE(err);
++
++ /* Set pixel format:24bpp */
++ buf[0] = HX8369_CMD_SETPIXEL_FMT;
++ switch (lcd_config.dpi_fmt) {
++ case MIPI_RGB565_PACKED:
++ case MIPI_RGB565_LOOSELY:
++ case MIPI_RGB565_CONFIG3:
++ buf[0] |= (HX8369_CMD_SETPIXEL_FMT_16BPP << 8);
++ break;
++
++ case MIPI_RGB666_LOOSELY:
++ case MIPI_RGB666_PACKED:
++ buf[0] |= (HX8369_CMD_SETPIXEL_FMT_18BPP << 8);
++ break;
++
++ case MIPI_RGB888:
++ buf[0] |= (HX8369_CMD_SETPIXEL_FMT_24BPP << 8);
++ break;
++
++ default:
++ buf[0] |= (HX8369_CMD_SETPIXEL_FMT_24BPP << 8);
++ break;
++ }
++ err = mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM,
++ buf, 0);
++ CHECK_RETCODE(err);
++
++ /* Set column address: 0~479 */
++ buf[0] = HX8369_CMD_SETCLUMN_ADDR |
++ (HX8369_CMD_SETCLUMN_ADDR_PARAM_1 << 8);
++ buf[1] = HX8369_CMD_SETCLUMN_ADDR_PARAM_2;
++ err = mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_LONG_WRITE,
++ buf, HX8369_CMD_SETCLUMN_ADDR_LEN);
++ CHECK_RETCODE(err);
++
++ /* Set page address: 0~799 */
++ buf[0] = HX8369_CMD_SETPAGE_ADDR |
++ (HX8369_CMD_SETPAGE_ADDR_PARAM_1 << 8);
++ buf[1] = HX8369_CMD_SETPAGE_ADDR_PARAM_2;
++ err = mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_LONG_WRITE,
++ buf, HX8369_CMD_SETPAGE_ADDR_LEN);
++ CHECK_RETCODE(err);
++
++ /* Set display brightness related */
++ buf[0] = HX8369_CMD_WRT_DISP_BRIGHT |
++ (HX8369_CMD_WRT_DISP_BRIGHT_PARAM_1 << 8);
++ err = mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM,
++ buf, 0);
++ CHECK_RETCODE(err);
++
++ buf[0] = HX8369_CMD_WRT_CABC_CTRL |
++ (HX8369_CMD_WRT_CABC_CTRL_PARAM_1 << 8);
++ err = mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM,
++ buf, 0);
++ CHECK_RETCODE(err);
++
++ buf[0] = HX8369_CMD_WRT_CTRL_DISP |
++ (HX8369_CMD_WRT_CTRL_DISP_PARAM_1 << 8);
++ err = mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM,
++ buf, 0);
++ CHECK_RETCODE(err);
++
++ /* exit sleep mode and set display on */
++ buf[0] = MIPI_DCS_EXIT_SLEEP_MODE;
++ err = mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM,
++ buf, 0);
++ CHECK_RETCODE(err);
++ /* To allow time for the supply voltages
++ * and clock circuits to stabilize.
++ */
++ msleep(5);
++ buf[0] = MIPI_DCS_SET_DISPLAY_ON;
++ err = mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM,
++ buf, 0);
++ CHECK_RETCODE(err);
++
++ err = mipid_init_backlight(mipi_dsi);
++ return err;
++}
++
++static int mipid_bl_update_status(struct backlight_device *bl)
++{
++ u32 buf;
++ int brightness = bl->props.brightness;
++ struct mipi_dsi_info *mipi_dsi = bl_get_data(bl);
++
++ if (bl->props.power != FB_BLANK_UNBLANK ||
++ bl->props.fb_blank != FB_BLANK_UNBLANK)
++ brightness = 0;
++
++ buf = HX8369_CMD_WRT_DISP_BRIGHT |
++ ((brightness & HX8369BL_MAX_BRIGHT) << 8);
++ mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM,
++ &buf, 0);
++
++ hx8369bl_brightness = brightness & HX8369BL_MAX_BRIGHT;
++
++ dev_dbg(&bl->dev, "mipid backlight bringtness:%d.\n", brightness);
++ return 0;
++}
++
++static int mipid_bl_get_brightness(struct backlight_device *bl)
++{
++ return hx8369bl_brightness;
++}
++
++static int mipi_bl_check_fb(struct backlight_device *bl, struct fb_info *fbi)
++{
++ return 0;
++}
++
++static const struct backlight_ops mipid_lcd_bl_ops = {
++ .update_status = mipid_bl_update_status,
++ .get_brightness = mipid_bl_get_brightness,
++ .check_fb = mipi_bl_check_fb,
++};
++
++static int mipid_init_backlight(struct mipi_dsi_info *mipi_dsi)
++{
++ struct backlight_properties props;
++ struct backlight_device *bl;
++
++ if (mipi_dsi->bl) {
++ pr_debug("mipid backlight already init!\n");
++ return 0;
++ }
++ memset(&props, 0, sizeof(struct backlight_properties));
++ props.max_brightness = HX8369BL_MAX_BRIGHT;
++ props.type = BACKLIGHT_RAW;
++ bl = backlight_device_register("mipid-bl", &mipi_dsi->pdev->dev,
++ mipi_dsi, &mipid_lcd_bl_ops, &props);
++ if (IS_ERR(bl)) {
++ pr_err("error %ld on backlight register\n", PTR_ERR(bl));
++ return PTR_ERR(bl);
++ }
++ mipi_dsi->bl = bl;
++ bl->props.power = FB_BLANK_UNBLANK;
++ bl->props.fb_blank = FB_BLANK_UNBLANK;
++ bl->props.brightness = HX8369BL_DEF_BRIGHT;
++
++ mipid_bl_update_status(bl);
++ return 0;
++}
+diff -Nur linux-4.1.3/drivers/video/mxc/mxc_hdmi.c linux-xbian-imx6/drivers/video/mxc/mxc_hdmi.c
+--- linux-4.1.3/drivers/video/mxc/mxc_hdmi.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/video/mxc/mxc_hdmi.c 2015-07-27 23:13:08.753749907 +0200
+@@ -0,0 +1,3404 @@
++/*
++ * Copyright (C) 2011-2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ */
++/*
++ * SH-Mobile High-Definition Multimedia Interface (HDMI) driver
++ * for SLISHDMI13T and SLIPHDMIT IP cores
++ *
++ * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/device.h>
++#include <linux/platform_device.h>
++#include <linux/input.h>
++#include <linux/interrupt.h>
++#include <linux/irq.h>
++#include <linux/io.h>
++#include <linux/fb.h>
++#include <linux/init.h>
++#include <linux/list.h>
++#include <linux/delay.h>
++#include <linux/dma-mapping.h>
++#include <linux/err.h>
++#include <linux/clk.h>
++#include <linux/uaccess.h>
++#include <linux/cpufreq.h>
++#include <linux/firmware.h>
++#include <linux/kthread.h>
++#include <linux/regulator/driver.h>
++#include <linux/fsl_devices.h>
++#include <linux/ipu.h>
++#include <linux/regmap.h>
++#include <linux/pinctrl/consumer.h>
++#include <linux/of_device.h>
++
++#include <linux/console.h>
++#include <linux/types.h>
++
++#include "../fbdev/edid.h"
++#include <video/mxc_edid.h>
++#include <video/mxc_hdmi.h>
++#include "mxc_dispdrv.h"
++
++#include <linux/mfd/mxc-hdmi-core.h>
++
++#include <linux/hdmi.h>
++
++#define DISPDRV_HDMI "hdmi"
++#define HDMI_EDID_LEN 512
++
++/* status codes for reading edid */
++#define HDMI_EDID_SUCCESS 0
++#define HDMI_EDID_FAIL -1
++#define HDMI_EDID_SAME -2
++#define HDMI_EDID_NO_MODES -3
++
++#define NUM_CEA_VIDEO_MODES 64
++#define DEFAULT_VIDEO_MODE 16 /* 1080P */
++
++#define RGB 0
++#define YCBCR444 1
++#define YCBCR422_16BITS 2
++#define YCBCR422_8BITS 3
++#define XVYCC444 4
++
++#define fb_mode_is_equal(a, b) mxc_edid_fb_mode_is_equal(true, a, b, ~0)
++
++/*
++ * We follow a flowchart which is in the "Synopsys DesignWare Courses
++ * HDMI Transmitter Controller User Guide, 1.30a", section 3.1
++ * (dwc_hdmi_tx_user.pdf)
++ *
++ * Below are notes that say "HDMI Initialization Step X"
++ * These correspond to the flowchart.
++ */
++
++/*
++ * We are required to configure VGA mode before reading edid
++ * in HDMI Initialization Step B
++ */
++static const struct fb_videomode vga_mode = {
++ /* 640x480 @ 60 Hz, 31.5 kHz hsync */
++ NULL, 60, 640, 480, 39721, 48, 16, 33, 10, 96, 2, 0,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_4_3, FB_MODE_IS_VESA,
++};
++
++enum hdmi_datamap {
++ RGB444_8B = 0x01,
++ RGB444_10B = 0x03,
++ RGB444_12B = 0x05,
++ RGB444_16B = 0x07,
++ YCbCr444_8B = 0x09,
++ YCbCr444_10B = 0x0B,
++ YCbCr444_12B = 0x0D,
++ YCbCr444_16B = 0x0F,
++ YCbCr422_8B = 0x16,
++ YCbCr422_10B = 0x14,
++ YCbCr422_12B = 0x12,
++};
++
++enum hdmi_mxc_colorimetry {
++ eITU601,
++ eITU709,
++};
++
++struct hdmi_vmode {
++ bool mDVI;
++ bool mHSyncPolarity;
++ bool mVSyncPolarity;
++ bool mInterlaced;
++ bool mDataEnablePolarity;
++
++ unsigned long mPixelClock;
++ unsigned int mPixelRepetitionInput;
++ unsigned int mPixelRepetitionOutput;
++};
++
++struct hdmi_data_info {
++ unsigned int enc_in_format;
++ unsigned int enc_out_format;
++ unsigned int enc_color_depth;
++ unsigned int colorimetry;
++ unsigned int pix_repet_factor;
++ unsigned int hdcp_enable;
++ unsigned int rgb_out_enable;
++ unsigned int rgb_quant_range;
++ unsigned int enable_3d;
++ unsigned int enable_fract;
++ struct hdmi_vmode video_mode;
++};
++
++struct hdmi_phy_reg_config {
++ /* HDMI PHY register config for pass HCT */
++ u16 reg_vlev;
++ u16 reg_cksymtx;
++};
++
++struct mxc_hdmi {
++ struct platform_device *pdev;
++ struct platform_device *core_pdev;
++ struct mxc_dispdrv_handle *disp_mxc_hdmi;
++ struct fb_info *fbi;
++ struct clk *hdmi_isfr_clk;
++ struct clk *hdmi_iahb_clk;
++ struct timer_list jitter_timer;
++ struct work_struct hotplug_work;
++ struct delayed_work hdcp_hdp_work;
++
++ struct notifier_block nb;
++
++ struct hdmi_data_info hdmi_data;
++ int vic;
++ int edid_status;
++ struct mxc_edid_cfg edid_cfg;
++ u8 edid[HDMI_EDID_LEN];
++ bool fb_reg;
++ bool cable_plugin;
++ u8 blank;
++ bool dft_mode_set;
++ char *dft_mode_str;
++ int default_bpp;
++ u8 latest_intr_stat;
++ u8 plug_event;
++ u8 plug_mask;
++ bool irq_enabled;
++ spinlock_t irq_lock;
++ bool phy_enabled;
++ struct fb_videomode default_mode;
++ struct fb_var_screeninfo previous_non_vga_mode;
++ bool requesting_vga_for_initialization;
++
++ int *gpr_base;
++ int *gpr_hdmi_base;
++ int *gpr_sdma_base;
++ int cpu_type;
++ int cpu_version;
++ struct hdmi_phy_reg_config phy_config;
++
++ struct pinctrl *pinctrl;
++};
++
++static int hdmi_major;
++static struct class *hdmi_class;
++
++struct i2c_client *hdmi_i2c;
++struct mxc_hdmi *g_hdmi;
++
++static bool hdmi_inited;
++static bool hdcp_init;
++
++extern const struct fb_videomode mxc_cea_mode[64];
++extern void mxc_hdmi_cec_handle(u32 cec_stat);
++
++static void mxc_hdmi_setup(struct mxc_hdmi *hdmi, unsigned long event);
++static void hdmi_enable_overflow_interrupts(void);
++static void hdmi_disable_overflow_interrupts(void);
++static void mxc_hdmi_edid_rebuild_modelist(struct mxc_hdmi *hdmi);
++static void mxc_hdmi_default_edid_cfg(struct mxc_hdmi *hdmi);
++static void mxc_hdmi_default_modelist(struct mxc_hdmi *hdmi);
++static void mxc_hdmi_set_mode(struct mxc_hdmi *hdmi);
++
++static char *rgb_quant_range = "default";
++module_param(rgb_quant_range, charp, S_IRUGO);
++MODULE_PARM_DESC(rgb_quant_range, "RGB Quant Range (default, limited, full)");
++
++static char *enable_3d = "1";
++module_param(enable_3d, charp, S_IRUGO);
++MODULE_PARM_DESC(enable_3d, "3D modes enabled (0/1)");
++
++static char *enable_fract = "1";
++module_param(enable_fract, charp, S_IRUGO);
++MODULE_PARM_DESC(enable_fract, "Fractional modes enabled (0/1)");
++
++static struct platform_device_id imx_hdmi_devtype[] = {
++ {
++ .name = "hdmi-imx6DL",
++ .driver_data = IMX6DL_HDMI,
++ }, {
++ .name = "hdmi-imx6Q",
++ .driver_data = IMX6Q_HDMI,
++ }, {
++ /* sentinel */
++ }
++};
++MODULE_DEVICE_TABLE(platform, imx_hdmi_devtype);
++
++static const struct of_device_id imx_hdmi_dt_ids[] = {
++ { .compatible = "fsl,imx6dl-hdmi-video", .data = &imx_hdmi_devtype[IMX6DL_HDMI], },
++ { .compatible = "fsl,imx6q-hdmi-video", .data = &imx_hdmi_devtype[IMX6Q_HDMI], },
++ { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, imx_hdmi_dt_ids);
++
++static inline int cpu_is_imx6dl(struct mxc_hdmi *hdmi)
++{
++ return hdmi->cpu_type == IMX6DL_HDMI;
++}
++
++static inline void get_refresh_str(struct fb_videomode *m, char *refresh)
++{
++ snprintf(refresh, 10, "%u.%uHz", m->refresh - (int)(m->vmode & FB_VMODE_FRACTIONAL ? 1 : 0),
++ m->refresh * (int)(m->vmode & FB_VMODE_FRACTIONAL ? 999 : 1000) % 1000);
++}
++
++static void dump_fb_videomode(struct fb_videomode *m)
++{
++ char refresh[10];
++
++ get_refresh_str(m, refresh);
++ pr_debug("fb_videomode = %ux%u%c-%s (%ukHz) %u %u %u %u %u %u %u %u %u\n",
++ m->xres, m->yres, m->vmode & FB_VMODE_INTERLACED ? 'i' : 'p',
++ refresh, m->pixclock, m->left_margin,
++ m->right_margin, m->upper_margin, m->lower_margin,
++ m->hsync_len, m->vsync_len, m->sync, m->vmode, m->flag);
++}
++
++static ssize_t mxc_hdmi_show_name(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct mxc_hdmi *hdmi = dev_get_drvdata(dev);
++
++ strcpy(buf, hdmi->fbi->fix.id);
++ sprintf(buf+strlen(buf), "\n");
++
++ return strlen(buf);
++}
++
++static DEVICE_ATTR(fb_name, S_IRUGO, mxc_hdmi_show_name, NULL);
++
++static ssize_t mxc_hdmi_show_state(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct mxc_hdmi *hdmi = dev_get_drvdata(dev);
++
++ if (hdmi->cable_plugin == false)
++ strcpy(buf, "plugout\n");
++ else
++ strcpy(buf, "plugin\n");
++
++ return strlen(buf);
++}
++
++static DEVICE_ATTR(cable_state, S_IRUGO, mxc_hdmi_show_state, NULL);
++
++static ssize_t mxc_hdmi_show_edid(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct mxc_hdmi *hdmi = dev_get_drvdata(dev);
++ int i, j, len = 0;
++
++ for (j = 0; j < HDMI_EDID_LEN/16; j++) {
++ for (i = 0; i < 16; i++)
++ len += sprintf(buf+len, "0x%02X ",
++ hdmi->edid[j*16 + i]);
++ len += sprintf(buf+len, "\n");
++ }
++
++ return len;
++}
++
++static DEVICE_ATTR(edid, S_IRUGO, mxc_hdmi_show_edid, NULL);
++
++static ssize_t mxc_hdmi_show_rgb_out_enable(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct mxc_hdmi *hdmi = dev_get_drvdata(dev);
++
++ if (hdmi->hdmi_data.rgb_out_enable == true)
++ strcpy(buf, "RGB out\n");
++ else
++ strcpy(buf, "YCbCr out\n");
++
++ return strlen(buf);
++}
++
++static ssize_t mxc_hdmi_store_rgb_out_enable(struct device *dev,
++ struct device_attribute *attr, const char *buf, size_t count)
++{
++ struct mxc_hdmi *hdmi = dev_get_drvdata(dev);
++ unsigned long value;
++ int ret;
++
++ ret = kstrtol(buf, 10, &value);
++ if (ret)
++ return ret;
++
++ hdmi->hdmi_data.rgb_out_enable = value;
++
++ /* Reconfig HDMI for output color space change */
++ mxc_hdmi_setup(hdmi, 0);
++
++ return count;
++}
++
++static DEVICE_ATTR(rgb_out_enable, S_IRUGO | S_IWUSR,
++ mxc_hdmi_show_rgb_out_enable,
++ mxc_hdmi_store_rgb_out_enable);
++
++static ssize_t mxc_hdmi_show_rgb_quant_range(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct mxc_hdmi *hdmi = dev_get_drvdata(dev);
++
++ switch (hdmi->hdmi_data.rgb_quant_range) {
++ case HDMI_FC_AVICONF2_RGB_QUANT_LIMITED_RANGE:
++ strcpy(buf, "limited\n");
++ break;
++ case HDMI_FC_AVICONF2_RGB_QUANT_FULL_RANGE:
++ strcpy(buf, "full\n");
++ break;
++ case HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT:
++ default:
++ strcpy(buf, "default\n");
++ break;
++ };
++
++ return strlen(buf);
++}
++
++static ssize_t mxc_hdmi_store_rgb_quant_range(struct device *dev,
++ struct device_attribute *attr, const char *buf, size_t count)
++{
++ struct mxc_hdmi *hdmi = dev_get_drvdata(dev);
++ int ret = count;
++
++ if (sysfs_streq("limited", buf)) {
++ hdmi->hdmi_data.rgb_quant_range = HDMI_FC_AVICONF2_RGB_QUANT_LIMITED_RANGE;
++ } else if (sysfs_streq("full", buf)) {
++ hdmi->hdmi_data.rgb_quant_range = HDMI_FC_AVICONF2_RGB_QUANT_FULL_RANGE;
++ } else if (sysfs_streq("default", buf)) {
++ hdmi->hdmi_data.rgb_quant_range = HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT;
++ } else {
++ ret = -EINVAL;
++ goto out;
++ }
++
++ /* Reconfig HDMI for output RGB Quant Range change if using RGB out */
++ if(hdmi->hdmi_data.rgb_out_enable)
++ mxc_hdmi_setup(hdmi, 0);
++out:
++ return ret;
++}
++
++static DEVICE_ATTR(rgb_quant_range, S_IRUGO | S_IWUSR,
++ mxc_hdmi_show_rgb_quant_range,
++ mxc_hdmi_store_rgb_quant_range);
++
++static ssize_t mxc_hdmi_show_enable_3d(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct mxc_hdmi *hdmi = dev_get_drvdata(dev);
++
++ switch (hdmi->hdmi_data.enable_3d) {
++ case 0:
++ strcpy(buf, "disabled\n");
++ break;
++ default:
++ strcpy(buf, "enabled\n");
++ break;
++ };
++
++ return strlen(buf);
++}
++
++static ssize_t mxc_hdmi_store_enable_3d(struct device *dev,
++ struct device_attribute *attr, const char *buf, size_t count)
++{
++ struct mxc_hdmi *hdmi = dev_get_drvdata(dev);
++ int ret = count;
++
++ if (sysfs_streq("disable", buf)) {
++ hdmi->hdmi_data.enable_3d = 0;
++ } else if (sysfs_streq("0", buf)) {
++ hdmi->hdmi_data.enable_3d = 0;
++ } else {
++ hdmi->hdmi_data.enable_3d = 1;
++ }
++
++ mxc_hdmi_edid_rebuild_modelist(hdmi);
++ if (hdmi->cable_plugin)
++ mxc_hdmi_set_mode(hdmi);
++
++ return ret;
++}
++
++static DEVICE_ATTR(enable_3d, S_IRUGO | S_IWUSR,
++ mxc_hdmi_show_enable_3d,
++ mxc_hdmi_store_enable_3d);
++
++static ssize_t mxc_hdmi_show_enable_fract(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct mxc_hdmi *hdmi = dev_get_drvdata(dev);
++
++ switch (hdmi->hdmi_data.enable_fract) {
++ case 0:
++ strcpy(buf, "disabled\n");
++ break;
++ default:
++ strcpy(buf, "enabled\n");
++ break;
++ };
++
++ return strlen(buf);
++}
++
++static ssize_t mxc_hdmi_store_enable_fract(struct device *dev,
++ struct device_attribute *attr, const char *buf, size_t count)
++{
++ struct mxc_hdmi *hdmi = dev_get_drvdata(dev);
++ int ret = count;
++
++ if (sysfs_streq("disable", buf)) {
++ hdmi->hdmi_data.enable_fract = 0;
++ } else if (sysfs_streq("0", buf)) {
++ hdmi->hdmi_data.enable_fract = 0;
++ } else {
++ hdmi->hdmi_data.enable_fract = 1;
++ }
++
++ mxc_hdmi_edid_rebuild_modelist(hdmi);
++ if (hdmi->cable_plugin)
++ mxc_hdmi_set_mode(hdmi);
++
++ return ret;
++}
++
++static DEVICE_ATTR(enable_fract, S_IRUGO | S_IWUSR,
++ mxc_hdmi_show_enable_fract,
++ mxc_hdmi_store_enable_fract);
++
++static ssize_t mxc_hdmi_show_hdcp_enable(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct mxc_hdmi *hdmi = dev_get_drvdata(dev);
++
++ if (hdmi->hdmi_data.hdcp_enable == false)
++ strcpy(buf, "hdcp disable\n");
++ else
++ strcpy(buf, "hdcp enable\n");
++
++ return strlen(buf);
++
++}
++
++static ssize_t mxc_hdmi_store_hdcp_enable(struct device *dev,
++ struct device_attribute *attr, const char *buf, size_t count)
++{
++ struct mxc_hdmi *hdmi = dev_get_drvdata(dev);
++ char event_string[32];
++ char *envp[] = { event_string, NULL };
++ unsigned long value;
++ int ret;
++
++ ret = kstrtol(buf, 10, &value);
++ if (ret)
++ return ret;
++
++ hdmi->hdmi_data.hdcp_enable = value;
++
++ /* Reconfig HDMI for HDCP */
++ mxc_hdmi_setup(hdmi, 0);
++
++ if (hdmi->hdmi_data.hdcp_enable == false) {
++ sprintf(event_string, "EVENT=hdcpdisable");
++ kobject_uevent_env(&hdmi->pdev->dev.kobj, KOBJ_CHANGE, envp);
++ } else {
++ sprintf(event_string, "EVENT=hdcpenable");
++ kobject_uevent_env(&hdmi->pdev->dev.kobj, KOBJ_CHANGE, envp);
++ }
++
++ return count;
++
++}
++
++static DEVICE_ATTR(hdcp_enable, S_IRUGO | S_IWUSR,
++ mxc_hdmi_show_hdcp_enable, mxc_hdmi_store_hdcp_enable);
++
++/*!
++ * this submodule is responsible for the video data synchronization.
++ * for example, for RGB 4:4:4 input, the data map is defined as
++ * pin{47~40} <==> R[7:0]
++ * pin{31~24} <==> G[7:0]
++ * pin{15~8} <==> B[7:0]
++ */
++static void hdmi_video_sample(struct mxc_hdmi *hdmi)
++{
++ int color_format = 0;
++ u8 val;
++
++ if (hdmi->hdmi_data.enc_in_format == RGB) {
++ if (hdmi->hdmi_data.enc_color_depth == 8)
++ color_format = 0x01;
++ else if (hdmi->hdmi_data.enc_color_depth == 10)
++ color_format = 0x03;
++ else if (hdmi->hdmi_data.enc_color_depth == 12)
++ color_format = 0x05;
++ else if (hdmi->hdmi_data.enc_color_depth == 16)
++ color_format = 0x07;
++ else
++ return;
++ } else if (hdmi->hdmi_data.enc_in_format == YCBCR444) {
++ if (hdmi->hdmi_data.enc_color_depth == 8)
++ color_format = 0x09;
++ else if (hdmi->hdmi_data.enc_color_depth == 10)
++ color_format = 0x0B;
++ else if (hdmi->hdmi_data.enc_color_depth == 12)
++ color_format = 0x0D;
++ else if (hdmi->hdmi_data.enc_color_depth == 16)
++ color_format = 0x0F;
++ else
++ return;
++ } else if (hdmi->hdmi_data.enc_in_format == YCBCR422_8BITS) {
++ if (hdmi->hdmi_data.enc_color_depth == 8)
++ color_format = 0x16;
++ else if (hdmi->hdmi_data.enc_color_depth == 10)
++ color_format = 0x14;
++ else if (hdmi->hdmi_data.enc_color_depth == 12)
++ color_format = 0x12;
++ else
++ return;
++ }
++
++ val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
++ ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
++ HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
++ hdmi_writeb(val, HDMI_TX_INVID0);
++
++ /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
++ val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
++ HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
++ HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
++ hdmi_writeb(val, HDMI_TX_INSTUFFING);
++ hdmi_writeb(0x0, HDMI_TX_GYDATA0);
++ hdmi_writeb(0x0, HDMI_TX_GYDATA1);
++ hdmi_writeb(0x0, HDMI_TX_RCRDATA0);
++ hdmi_writeb(0x0, HDMI_TX_RCRDATA1);
++ hdmi_writeb(0x0, HDMI_TX_BCBDATA0);
++ hdmi_writeb(0x0, HDMI_TX_BCBDATA1);
++}
++
++static int isColorSpaceConversion(struct mxc_hdmi *hdmi)
++{
++ return (hdmi->hdmi_data.enc_in_format != hdmi->hdmi_data.enc_out_format) ||
++ (hdmi->hdmi_data.enc_out_format == RGB &&
++ ((hdmi->hdmi_data.rgb_quant_range == HDMI_FC_AVICONF2_RGB_QUANT_LIMITED_RANGE) ||
++ (hdmi->hdmi_data.rgb_quant_range == HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT && hdmi->vic > 1)));
++}
++
++static int isColorSpaceDecimation(struct mxc_hdmi *hdmi)
++{
++ return ((hdmi->hdmi_data.enc_out_format == YCBCR422_8BITS) &&
++ (hdmi->hdmi_data.enc_in_format == RGB ||
++ hdmi->hdmi_data.enc_in_format == YCBCR444));
++}
++
++static int isColorSpaceInterpolation(struct mxc_hdmi *hdmi)
++{
++ return ((hdmi->hdmi_data.enc_in_format == YCBCR422_8BITS) &&
++ (hdmi->hdmi_data.enc_out_format == RGB
++ || hdmi->hdmi_data.enc_out_format == YCBCR444));
++}
++
++/*!
++ * update the color space conversion coefficients.
++ */
++static void update_csc_coeffs(struct mxc_hdmi *hdmi)
++{
++ unsigned short csc_coeff[3][4];
++ unsigned int csc_scale = 1;
++ u8 val;
++ bool coeff_selected = false;
++
++ if (isColorSpaceConversion(hdmi)) { /* csc needed */
++ if (hdmi->hdmi_data.enc_out_format == RGB) {
++ if (hdmi->hdmi_data.enc_in_format == RGB) {
++ csc_coeff[0][0] = 0x1b80;
++ csc_coeff[0][1] = 0x0000;
++ csc_coeff[0][2] = 0x0000;
++ csc_coeff[0][3] = 0x0020;
++
++ csc_coeff[1][0] = 0x0000;
++ csc_coeff[1][1] = 0x1b80;
++ csc_coeff[1][2] = 0x0000;
++ csc_coeff[1][3] = 0x0020;
++
++ csc_coeff[2][0] = 0x0000;
++ csc_coeff[2][1] = 0x0000;
++ csc_coeff[2][2] = 0x1b80;
++ csc_coeff[2][3] = 0x0020;
++
++ csc_scale = 1;
++ coeff_selected = true;
++ } else if (hdmi->hdmi_data.colorimetry == eITU601) {
++ csc_coeff[0][0] = 0x2000;
++ csc_coeff[0][1] = 0x6926;
++ csc_coeff[0][2] = 0x74fd;
++ csc_coeff[0][3] = 0x010e;
++
++ csc_coeff[1][0] = 0x2000;
++ csc_coeff[1][1] = 0x2cdd;
++ csc_coeff[1][2] = 0x0000;
++ csc_coeff[1][3] = 0x7e9a;
++
++ csc_coeff[2][0] = 0x2000;
++ csc_coeff[2][1] = 0x0000;
++ csc_coeff[2][2] = 0x38b4;
++ csc_coeff[2][3] = 0x7e3b;
++
++ csc_scale = 1;
++ coeff_selected = true;
++ } else if (hdmi->hdmi_data.colorimetry == eITU709) {
++ csc_coeff[0][0] = 0x2000;
++ csc_coeff[0][1] = 0x7106;
++ csc_coeff[0][2] = 0x7a02;
++ csc_coeff[0][3] = 0x00a7;
++
++ csc_coeff[1][0] = 0x2000;
++ csc_coeff[1][1] = 0x3264;
++ csc_coeff[1][2] = 0x0000;
++ csc_coeff[1][3] = 0x7e6d;
++
++ csc_coeff[2][0] = 0x2000;
++ csc_coeff[2][1] = 0x0000;
++ csc_coeff[2][2] = 0x3b61;
++ csc_coeff[2][3] = 0x7e25;
++
++ csc_scale = 1;
++ coeff_selected = true;
++ }
++ } else if (hdmi->hdmi_data.enc_in_format == RGB) {
++ if (hdmi->hdmi_data.colorimetry == eITU601) {
++ csc_coeff[0][0] = 0x2591;
++ csc_coeff[0][1] = 0x1322;
++ csc_coeff[0][2] = 0x074b;
++ csc_coeff[0][3] = 0x0000;
++
++ csc_coeff[1][0] = 0x6535;
++ csc_coeff[1][1] = 0x2000;
++ csc_coeff[1][2] = 0x7acc;
++ csc_coeff[1][3] = 0x0200;
++
++ csc_coeff[2][0] = 0x6acd;
++ csc_coeff[2][1] = 0x7534;
++ csc_coeff[2][2] = 0x2000;
++ csc_coeff[2][3] = 0x0200;
++
++ csc_scale = 0;
++ coeff_selected = true;
++ } else if (hdmi->hdmi_data.colorimetry == eITU709) {
++ csc_coeff[0][0] = 0x2dc5;
++ csc_coeff[0][1] = 0x0d9b;
++ csc_coeff[0][2] = 0x049e;
++ csc_coeff[0][3] = 0x0000;
++
++ csc_coeff[1][0] = 0x62f0;
++ csc_coeff[1][1] = 0x2000;
++ csc_coeff[1][2] = 0x7d11;
++ csc_coeff[1][3] = 0x0200;
++
++ csc_coeff[2][0] = 0x6756;
++ csc_coeff[2][1] = 0x78ab;
++ csc_coeff[2][2] = 0x2000;
++ csc_coeff[2][3] = 0x0200;
++
++ csc_scale = 0;
++ coeff_selected = true;
++ }
++ }
++ }
++
++ if (!coeff_selected) {
++ csc_coeff[0][0] = 0x2000;
++ csc_coeff[0][1] = 0x0000;
++ csc_coeff[0][2] = 0x0000;
++ csc_coeff[0][3] = 0x0000;
++
++ csc_coeff[1][0] = 0x0000;
++ csc_coeff[1][1] = 0x2000;
++ csc_coeff[1][2] = 0x0000;
++ csc_coeff[1][3] = 0x0000;
++
++ csc_coeff[2][0] = 0x0000;
++ csc_coeff[2][1] = 0x0000;
++ csc_coeff[2][2] = 0x2000;
++ csc_coeff[2][3] = 0x0000;
++
++ csc_scale = 1;
++ }
++
++ /* Update CSC parameters in HDMI CSC registers */
++ hdmi_writeb((unsigned char)(csc_coeff[0][0] & 0xFF),
++ HDMI_CSC_COEF_A1_LSB);
++ hdmi_writeb((unsigned char)(csc_coeff[0][0] >> 8),
++ HDMI_CSC_COEF_A1_MSB);
++ hdmi_writeb((unsigned char)(csc_coeff[0][1] & 0xFF),
++ HDMI_CSC_COEF_A2_LSB);
++ hdmi_writeb((unsigned char)(csc_coeff[0][1] >> 8),
++ HDMI_CSC_COEF_A2_MSB);
++ hdmi_writeb((unsigned char)(csc_coeff[0][2] & 0xFF),
++ HDMI_CSC_COEF_A3_LSB);
++ hdmi_writeb((unsigned char)(csc_coeff[0][2] >> 8),
++ HDMI_CSC_COEF_A3_MSB);
++ hdmi_writeb((unsigned char)(csc_coeff[0][3] & 0xFF),
++ HDMI_CSC_COEF_A4_LSB);
++ hdmi_writeb((unsigned char)(csc_coeff[0][3] >> 8),
++ HDMI_CSC_COEF_A4_MSB);
++
++ hdmi_writeb((unsigned char)(csc_coeff[1][0] & 0xFF),
++ HDMI_CSC_COEF_B1_LSB);
++ hdmi_writeb((unsigned char)(csc_coeff[1][0] >> 8),
++ HDMI_CSC_COEF_B1_MSB);
++ hdmi_writeb((unsigned char)(csc_coeff[1][1] & 0xFF),
++ HDMI_CSC_COEF_B2_LSB);
++ hdmi_writeb((unsigned char)(csc_coeff[1][1] >> 8),
++ HDMI_CSC_COEF_B2_MSB);
++ hdmi_writeb((unsigned char)(csc_coeff[1][2] & 0xFF),
++ HDMI_CSC_COEF_B3_LSB);
++ hdmi_writeb((unsigned char)(csc_coeff[1][2] >> 8),
++ HDMI_CSC_COEF_B3_MSB);
++ hdmi_writeb((unsigned char)(csc_coeff[1][3] & 0xFF),
++ HDMI_CSC_COEF_B4_LSB);
++ hdmi_writeb((unsigned char)(csc_coeff[1][3] >> 8),
++ HDMI_CSC_COEF_B4_MSB);
++
++ hdmi_writeb((unsigned char)(csc_coeff[2][0] & 0xFF),
++ HDMI_CSC_COEF_C1_LSB);
++ hdmi_writeb((unsigned char)(csc_coeff[2][0] >> 8),
++ HDMI_CSC_COEF_C1_MSB);
++ hdmi_writeb((unsigned char)(csc_coeff[2][1] & 0xFF),
++ HDMI_CSC_COEF_C2_LSB);
++ hdmi_writeb((unsigned char)(csc_coeff[2][1] >> 8),
++ HDMI_CSC_COEF_C2_MSB);
++ hdmi_writeb((unsigned char)(csc_coeff[2][2] & 0xFF),
++ HDMI_CSC_COEF_C3_LSB);
++ hdmi_writeb((unsigned char)(csc_coeff[2][2] >> 8),
++ HDMI_CSC_COEF_C3_MSB);
++ hdmi_writeb((unsigned char)(csc_coeff[2][3] & 0xFF),
++ HDMI_CSC_COEF_C4_LSB);
++ hdmi_writeb((unsigned char)(csc_coeff[2][3] >> 8),
++ HDMI_CSC_COEF_C4_MSB);
++
++ val = hdmi_readb(HDMI_CSC_SCALE);
++ val &= ~HDMI_CSC_SCALE_CSCSCALE_MASK;
++ val |= csc_scale & HDMI_CSC_SCALE_CSCSCALE_MASK;
++ hdmi_writeb(val, HDMI_CSC_SCALE);
++}
++
++static void hdmi_video_csc(struct mxc_hdmi *hdmi)
++{
++ int color_depth = 0;
++ int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
++ int decimation = HDMI_CSC_CFG_DECMODE_DISABLE;
++ u8 val;
++
++ /* YCC422 interpolation to 444 mode */
++ if (isColorSpaceInterpolation(hdmi))
++ interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
++ else if (isColorSpaceDecimation(hdmi))
++ decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
++
++ if (hdmi->hdmi_data.enc_color_depth == 8)
++ color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
++ else if (hdmi->hdmi_data.enc_color_depth == 10)
++ color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
++ else if (hdmi->hdmi_data.enc_color_depth == 12)
++ color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
++ else if (hdmi->hdmi_data.enc_color_depth == 16)
++ color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
++ else
++ return;
++
++ /*configure the CSC registers */
++ hdmi_writeb(interpolation | decimation, HDMI_CSC_CFG);
++ val = hdmi_readb(HDMI_CSC_SCALE);
++ val &= ~HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK;
++ val |= color_depth;
++ hdmi_writeb(val, HDMI_CSC_SCALE);
++
++ update_csc_coeffs(hdmi);
++}
++
++/*!
++ * HDMI video packetizer is used to packetize the data.
++ * for example, if input is YCC422 mode or repeater is used,
++ * data should be repacked this module can be bypassed.
++ */
++static void hdmi_video_packetize(struct mxc_hdmi *hdmi)
++{
++ unsigned int color_depth = 0;
++ unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
++ unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
++ struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
++ u8 val;
++
++ if (hdmi_data->enc_out_format == RGB
++ || hdmi_data->enc_out_format == YCBCR444) {
++ if (hdmi_data->enc_color_depth == 0)
++ output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
++ else if (hdmi_data->enc_color_depth == 8) {
++ color_depth = 4;
++ output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
++ } else if (hdmi_data->enc_color_depth == 10)
++ color_depth = 5;
++ else if (hdmi_data->enc_color_depth == 12)
++ color_depth = 6;
++ else if (hdmi_data->enc_color_depth == 16)
++ color_depth = 7;
++ else
++ return;
++ } else if (hdmi_data->enc_out_format == YCBCR422_8BITS) {
++ if (hdmi_data->enc_color_depth == 0 ||
++ hdmi_data->enc_color_depth == 8)
++ remap_size = HDMI_VP_REMAP_YCC422_16bit;
++ else if (hdmi_data->enc_color_depth == 10)
++ remap_size = HDMI_VP_REMAP_YCC422_20bit;
++ else if (hdmi_data->enc_color_depth == 12)
++ remap_size = HDMI_VP_REMAP_YCC422_24bit;
++ else
++ return;
++ output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
++ } else
++ return;
++
++ /* HDMI not support deep color,
++ * because IPU MAX support color depth is 24bit */
++ color_depth = 0;
++
++ /* set the packetizer registers */
++ val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
++ HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
++ ((hdmi_data->pix_repet_factor <<
++ HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
++ HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
++ hdmi_writeb(val, HDMI_VP_PR_CD);
++
++ val = hdmi_readb(HDMI_VP_STUFF);
++ val &= ~HDMI_VP_STUFF_PR_STUFFING_MASK;
++ val |= HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE;
++ hdmi_writeb(val, HDMI_VP_STUFF);
++
++ /* Data from pixel repeater block */
++ if (hdmi_data->pix_repet_factor > 1) {
++ val = hdmi_readb(HDMI_VP_CONF);
++ val &= ~(HDMI_VP_CONF_PR_EN_MASK |
++ HDMI_VP_CONF_BYPASS_SELECT_MASK);
++ val |= HDMI_VP_CONF_PR_EN_ENABLE |
++ HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
++ hdmi_writeb(val, HDMI_VP_CONF);
++ } else { /* data from packetizer block */
++ val = hdmi_readb(HDMI_VP_CONF);
++ val &= ~(HDMI_VP_CONF_PR_EN_MASK |
++ HDMI_VP_CONF_BYPASS_SELECT_MASK);
++ val |= HDMI_VP_CONF_PR_EN_DISABLE |
++ HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
++ hdmi_writeb(val, HDMI_VP_CONF);
++ }
++
++ val = hdmi_readb(HDMI_VP_STUFF);
++ val &= ~HDMI_VP_STUFF_IDEFAULT_PHASE_MASK;
++ val |= 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET;
++ hdmi_writeb(val, HDMI_VP_STUFF);
++
++ hdmi_writeb(remap_size, HDMI_VP_REMAP);
++
++ if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
++ val = hdmi_readb(HDMI_VP_CONF);
++ val &= ~(HDMI_VP_CONF_BYPASS_EN_MASK |
++ HDMI_VP_CONF_PP_EN_ENMASK |
++ HDMI_VP_CONF_YCC422_EN_MASK);
++ val |= HDMI_VP_CONF_BYPASS_EN_DISABLE |
++ HDMI_VP_CONF_PP_EN_ENABLE |
++ HDMI_VP_CONF_YCC422_EN_DISABLE;
++ hdmi_writeb(val, HDMI_VP_CONF);
++ } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
++ val = hdmi_readb(HDMI_VP_CONF);
++ val &= ~(HDMI_VP_CONF_BYPASS_EN_MASK |
++ HDMI_VP_CONF_PP_EN_ENMASK |
++ HDMI_VP_CONF_YCC422_EN_MASK);
++ val |= HDMI_VP_CONF_BYPASS_EN_DISABLE |
++ HDMI_VP_CONF_PP_EN_DISABLE |
++ HDMI_VP_CONF_YCC422_EN_ENABLE;
++ hdmi_writeb(val, HDMI_VP_CONF);
++ } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
++ val = hdmi_readb(HDMI_VP_CONF);
++ val &= ~(HDMI_VP_CONF_BYPASS_EN_MASK |
++ HDMI_VP_CONF_PP_EN_ENMASK |
++ HDMI_VP_CONF_YCC422_EN_MASK);
++ val |= HDMI_VP_CONF_BYPASS_EN_ENABLE |
++ HDMI_VP_CONF_PP_EN_DISABLE |
++ HDMI_VP_CONF_YCC422_EN_DISABLE;
++ hdmi_writeb(val, HDMI_VP_CONF);
++ } else {
++ return;
++ }
++
++ val = hdmi_readb(HDMI_VP_STUFF);
++ val &= ~(HDMI_VP_STUFF_PP_STUFFING_MASK |
++ HDMI_VP_STUFF_YCC422_STUFFING_MASK);
++ val |= HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
++ HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE;
++ hdmi_writeb(val, HDMI_VP_STUFF);
++
++ val = hdmi_readb(HDMI_VP_CONF);
++ val &= ~HDMI_VP_CONF_OUTPUT_SELECTOR_MASK;
++ val |= output_select;
++ hdmi_writeb(val, HDMI_VP_CONF);
++}
++
++#if 0
++/* Force a fixed color screen */
++static void hdmi_video_force_output(struct mxc_hdmi *hdmi, unsigned char force)
++{
++ u8 val;
++
++ dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
++
++ if (force) {
++ hdmi_writeb(0x00, HDMI_FC_DBGTMDS2); /* R */
++ hdmi_writeb(0x00, HDMI_FC_DBGTMDS1); /* G */
++ hdmi_writeb(0xFF, HDMI_FC_DBGTMDS0); /* B */
++ val = hdmi_readb(HDMI_FC_DBGFORCE);
++ val |= HDMI_FC_DBGFORCE_FORCEVIDEO;
++ hdmi_writeb(val, HDMI_FC_DBGFORCE);
++ } else {
++ val = hdmi_readb(HDMI_FC_DBGFORCE);
++ val &= ~HDMI_FC_DBGFORCE_FORCEVIDEO;
++ hdmi_writeb(val, HDMI_FC_DBGFORCE);
++ hdmi_writeb(0x00, HDMI_FC_DBGTMDS2); /* R */
++ hdmi_writeb(0x00, HDMI_FC_DBGTMDS1); /* G */
++ hdmi_writeb(0x00, HDMI_FC_DBGTMDS0); /* B */
++ }
++}
++#endif
++
++static inline void hdmi_phy_test_clear(struct mxc_hdmi *hdmi,
++ unsigned char bit)
++{
++ u8 val = hdmi_readb(HDMI_PHY_TST0);
++ val &= ~HDMI_PHY_TST0_TSTCLR_MASK;
++ val |= (bit << HDMI_PHY_TST0_TSTCLR_OFFSET) &
++ HDMI_PHY_TST0_TSTCLR_MASK;
++ hdmi_writeb(val, HDMI_PHY_TST0);
++}
++
++static inline void hdmi_phy_test_enable(struct mxc_hdmi *hdmi,
++ unsigned char bit)
++{
++ u8 val = hdmi_readb(HDMI_PHY_TST0);
++ val &= ~HDMI_PHY_TST0_TSTEN_MASK;
++ val |= (bit << HDMI_PHY_TST0_TSTEN_OFFSET) &
++ HDMI_PHY_TST0_TSTEN_MASK;
++ hdmi_writeb(val, HDMI_PHY_TST0);
++}
++
++static inline void hdmi_phy_test_clock(struct mxc_hdmi *hdmi,
++ unsigned char bit)
++{
++ u8 val = hdmi_readb(HDMI_PHY_TST0);
++ val &= ~HDMI_PHY_TST0_TSTCLK_MASK;
++ val |= (bit << HDMI_PHY_TST0_TSTCLK_OFFSET) &
++ HDMI_PHY_TST0_TSTCLK_MASK;
++ hdmi_writeb(val, HDMI_PHY_TST0);
++}
++
++static inline void hdmi_phy_test_din(struct mxc_hdmi *hdmi,
++ unsigned char bit)
++{
++ hdmi_writeb(bit, HDMI_PHY_TST1);
++}
++
++static inline void hdmi_phy_test_dout(struct mxc_hdmi *hdmi,
++ unsigned char bit)
++{
++ hdmi_writeb(bit, HDMI_PHY_TST2);
++}
++
++static bool hdmi_phy_wait_i2c_done(struct mxc_hdmi *hdmi, int msec)
++{
++ unsigned char val = 0;
++ val = hdmi_readb(HDMI_IH_I2CMPHY_STAT0) & 0x3;
++ while (val == 0) {
++ udelay(1000);
++ if (msec-- == 0)
++ return false;
++ val = hdmi_readb(HDMI_IH_I2CMPHY_STAT0) & 0x3;
++ }
++ return true;
++}
++
++static void hdmi_phy_i2c_write(struct mxc_hdmi *hdmi, unsigned short data,
++ unsigned char addr)
++{
++ hdmi_writeb(0xFF, HDMI_IH_I2CMPHY_STAT0);
++ hdmi_writeb(addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
++ hdmi_writeb((unsigned char)(data >> 8),
++ HDMI_PHY_I2CM_DATAO_1_ADDR);
++ hdmi_writeb((unsigned char)(data >> 0),
++ HDMI_PHY_I2CM_DATAO_0_ADDR);
++ hdmi_writeb(HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
++ HDMI_PHY_I2CM_OPERATION_ADDR);
++ hdmi_phy_wait_i2c_done(hdmi, 1000);
++}
++
++#if 0
++static unsigned short hdmi_phy_i2c_read(struct mxc_hdmi *hdmi,
++ unsigned char addr)
++{
++ unsigned short data;
++ unsigned char msb = 0, lsb = 0;
++ hdmi_writeb(0xFF, HDMI_IH_I2CMPHY_STAT0);
++ hdmi_writeb(addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
++ hdmi_writeb(HDMI_PHY_I2CM_OPERATION_ADDR_READ,
++ HDMI_PHY_I2CM_OPERATION_ADDR);
++ hdmi_phy_wait_i2c_done(hdmi, 1000);
++ msb = hdmi_readb(HDMI_PHY_I2CM_DATAI_1_ADDR);
++ lsb = hdmi_readb(HDMI_PHY_I2CM_DATAI_0_ADDR);
++ data = (msb << 8) | lsb;
++ return data;
++}
++
++static int hdmi_phy_i2c_write_verify(struct mxc_hdmi *hdmi, unsigned short data,
++ unsigned char addr)
++{
++ unsigned short val = 0;
++ hdmi_phy_i2c_write(hdmi, data, addr);
++ val = hdmi_phy_i2c_read(hdmi, addr);
++ return (val == data);
++}
++#endif
++
++static bool hdmi_edid_wait_i2c_done(struct mxc_hdmi *hdmi, int msec)
++{
++ unsigned char val = 0;
++ val = hdmi_readb(HDMI_IH_I2CM_STAT0) & 0x2;
++ while (val == 0) {
++
++ udelay(1000);
++ if (msec-- == 0) {
++ dev_dbg(&hdmi->pdev->dev,
++ "HDMI EDID i2c operation time out!!\n");
++ return false;
++ }
++ val = hdmi_readb(HDMI_IH_I2CM_STAT0) & 0x2;
++ }
++ return true;
++}
++
++static u8 hdmi_edid_i2c_read(struct mxc_hdmi *hdmi,
++ u8 addr, u8 blockno)
++{
++ u8 spointer = blockno / 2;
++ u8 edidaddress = ((blockno % 2) * 0x80) + addr;
++ u8 data;
++
++ hdmi_writeb(0xFF, HDMI_IH_I2CM_STAT0);
++ hdmi_writeb(edidaddress, HDMI_I2CM_ADDRESS);
++ hdmi_writeb(spointer, HDMI_I2CM_SEGADDR);
++ if (spointer == 0)
++ hdmi_writeb(HDMI_I2CM_OPERATION_READ,
++ HDMI_I2CM_OPERATION);
++ else
++ hdmi_writeb(HDMI_I2CM_OPERATION_READ_EXT,
++ HDMI_I2CM_OPERATION);
++
++ hdmi_edid_wait_i2c_done(hdmi, 1000);
++ data = hdmi_readb(HDMI_I2CM_DATAI);
++ hdmi_writeb(0xFF, HDMI_IH_I2CM_STAT0);
++ return data;
++}
++
++
++/* "Power-down enable (active low)"
++ * That mean that power up == 1! */
++static void mxc_hdmi_phy_enable_power(u8 enable)
++{
++ hdmi_mask_writeb(enable, HDMI_PHY_CONF0,
++ HDMI_PHY_CONF0_PDZ_OFFSET,
++ HDMI_PHY_CONF0_PDZ_MASK);
++}
++
++static void mxc_hdmi_phy_enable_tmds(u8 enable)
++{
++ hdmi_mask_writeb(enable, HDMI_PHY_CONF0,
++ HDMI_PHY_CONF0_ENTMDS_OFFSET,
++ HDMI_PHY_CONF0_ENTMDS_MASK);
++}
++
++static void mxc_hdmi_phy_gen2_pddq(u8 enable)
++{
++ hdmi_mask_writeb(enable, HDMI_PHY_CONF0,
++ HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
++ HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
++}
++
++static void mxc_hdmi_phy_gen2_txpwron(u8 enable)
++{
++ hdmi_mask_writeb(enable, HDMI_PHY_CONF0,
++ HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
++ HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
++}
++
++#if 0
++static void mxc_hdmi_phy_gen2_enhpdrxsense(u8 enable)
++{
++ hdmi_mask_writeb(enable, HDMI_PHY_CONF0,
++ HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE_OFFSET,
++ HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE_MASK);
++}
++#endif
++
++static void mxc_hdmi_phy_sel_data_en_pol(u8 enable)
++{
++ hdmi_mask_writeb(enable, HDMI_PHY_CONF0,
++ HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
++ HDMI_PHY_CONF0_SELDATAENPOL_MASK);
++}
++
++static void mxc_hdmi_phy_sel_interface_control(u8 enable)
++{
++ hdmi_mask_writeb(enable, HDMI_PHY_CONF0,
++ HDMI_PHY_CONF0_SELDIPIF_OFFSET,
++ HDMI_PHY_CONF0_SELDIPIF_MASK);
++}
++
++static int hdmi_phy_configure(struct mxc_hdmi *hdmi, unsigned char pRep,
++ unsigned char cRes, int cscOn)
++{
++ u8 val;
++ u8 msec;
++
++ dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
++
++ /* color resolution 0 is 8 bit colour depth */
++ if (cRes == 0)
++ cRes = 8;
++
++ if (pRep != 0)
++ return false;
++ else if (cRes != 8 && cRes != 12)
++ return false;
++
++ /* Enable csc path */
++ if (cscOn)
++ val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH;
++ else
++ val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS;
++
++ hdmi_writeb(val, HDMI_MC_FLOWCTRL);
++
++ /* gen2 tx power off */
++ mxc_hdmi_phy_gen2_txpwron(0);
++
++ /* gen2 pddq */
++ mxc_hdmi_phy_gen2_pddq(1);
++
++ /* PHY reset */
++ hdmi_writeb(HDMI_MC_PHYRSTZ_DEASSERT, HDMI_MC_PHYRSTZ);
++ hdmi_writeb(HDMI_MC_PHYRSTZ_ASSERT, HDMI_MC_PHYRSTZ);
++
++ hdmi_writeb(HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
++
++ hdmi_phy_test_clear(hdmi, 1);
++ hdmi_writeb(HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2,
++ HDMI_PHY_I2CM_SLAVE_ADDR);
++ hdmi_phy_test_clear(hdmi, 0);
++
++ if (hdmi->hdmi_data.video_mode.mPixelClock < 0) {
++ dev_dbg(&hdmi->pdev->dev, "Pixel clock (%lu) must be positive\n",
++ hdmi->hdmi_data.video_mode.mPixelClock);
++ return false;
++ }
++
++ if (hdmi->hdmi_data.video_mode.mPixelClock <= 45250000) {
++ switch (cRes) {
++ case 8:
++ /* PLL/MPLL Cfg */
++ hdmi_phy_i2c_write(hdmi, 0x01e0, 0x06);
++ hdmi_phy_i2c_write(hdmi, 0x0000, 0x15); /* GMPCTRL */
++ break;
++ case 10:
++ hdmi_phy_i2c_write(hdmi, 0x21e1, 0x06);
++ hdmi_phy_i2c_write(hdmi, 0x0000, 0x15);
++ break;
++ case 12:
++ hdmi_phy_i2c_write(hdmi, 0x41e2, 0x06);
++ hdmi_phy_i2c_write(hdmi, 0x0000, 0x15);
++ break;
++ default:
++ return false;
++ }
++ } else if (hdmi->hdmi_data.video_mode.mPixelClock <= 92500000) {
++ switch (cRes) {
++ case 8:
++ hdmi_phy_i2c_write(hdmi, 0x0140, 0x06);
++ hdmi_phy_i2c_write(hdmi, 0x0005, 0x15);
++ break;
++ case 10:
++ hdmi_phy_i2c_write(hdmi, 0x2141, 0x06);
++ hdmi_phy_i2c_write(hdmi, 0x0005, 0x15);
++ break;
++ case 12:
++ hdmi_phy_i2c_write(hdmi, 0x4142, 0x06);
++ hdmi_phy_i2c_write(hdmi, 0x0005, 0x15);
++ default:
++ return false;
++ }
++ } else if (hdmi->hdmi_data.video_mode.mPixelClock <= 148500000) {
++ switch (cRes) {
++ case 8:
++ hdmi_phy_i2c_write(hdmi, 0x00a0, 0x06);
++ hdmi_phy_i2c_write(hdmi, 0x000a, 0x15);
++ break;
++ case 10:
++ hdmi_phy_i2c_write(hdmi, 0x20a1, 0x06);
++ hdmi_phy_i2c_write(hdmi, 0x000a, 0x15);
++ break;
++ case 12:
++ hdmi_phy_i2c_write(hdmi, 0x40a2, 0x06);
++ hdmi_phy_i2c_write(hdmi, 0x000a, 0x15);
++ default:
++ return false;
++ }
++ } else {
++ switch (cRes) {
++ case 8:
++ hdmi_phy_i2c_write(hdmi, 0x00a0, 0x06);
++ hdmi_phy_i2c_write(hdmi, 0x000a, 0x15);
++ break;
++ case 10:
++ hdmi_phy_i2c_write(hdmi, 0x2001, 0x06);
++ hdmi_phy_i2c_write(hdmi, 0x000f, 0x15);
++ break;
++ case 12:
++ hdmi_phy_i2c_write(hdmi, 0x4002, 0x06);
++ hdmi_phy_i2c_write(hdmi, 0x000f, 0x15);
++ default:
++ return false;
++ }
++ }
++
++ if (hdmi->hdmi_data.video_mode.mPixelClock <= 54000000) {
++ switch (cRes) {
++ case 8:
++ hdmi_phy_i2c_write(hdmi, 0x091c, 0x10); /* CURRCTRL */
++ break;
++ case 10:
++ hdmi_phy_i2c_write(hdmi, 0x091c, 0x10);
++ break;
++ case 12:
++ hdmi_phy_i2c_write(hdmi, 0x06dc, 0x10);
++ break;
++ default:
++ return false;
++ }
++ } else if (hdmi->hdmi_data.video_mode.mPixelClock <= 58400000) {
++ switch (cRes) {
++ case 8:
++ hdmi_phy_i2c_write(hdmi, 0x091c, 0x10);
++ break;
++ case 10:
++ hdmi_phy_i2c_write(hdmi, 0x06dc, 0x10);
++ break;
++ case 12:
++ hdmi_phy_i2c_write(hdmi, 0x06dc, 0x10);
++ break;
++ default:
++ return false;
++ }
++ } else if (hdmi->hdmi_data.video_mode.mPixelClock <= 72000000) {
++ switch (cRes) {
++ case 8:
++ hdmi_phy_i2c_write(hdmi, 0x06dc, 0x10);
++ break;
++ case 10:
++ hdmi_phy_i2c_write(hdmi, 0x06dc, 0x10);
++ break;
++ case 12:
++ hdmi_phy_i2c_write(hdmi, 0x091c, 0x10);
++ break;
++ default:
++ return false;
++ }
++ } else if (hdmi->hdmi_data.video_mode.mPixelClock <= 74250000) {
++ switch (cRes) {
++ case 8:
++ hdmi_phy_i2c_write(hdmi, 0x06dc, 0x10);
++ break;
++ case 10:
++ hdmi_phy_i2c_write(hdmi, 0x0b5c, 0x10);
++ break;
++ case 12:
++ hdmi_phy_i2c_write(hdmi, 0x091c, 0x10);
++ break;
++ default:
++ return false;
++ }
++ } else if (hdmi->hdmi_data.video_mode.mPixelClock <= 118800000) {
++ switch (cRes) {
++ case 8:
++ hdmi_phy_i2c_write(hdmi, 0x091c, 0x10);
++ break;
++ case 10:
++ hdmi_phy_i2c_write(hdmi, 0x091c, 0x10);
++ break;
++ case 12:
++ hdmi_phy_i2c_write(hdmi, 0x06dc, 0x10);
++ break;
++ default:
++ return false;
++ }
++ } else if (hdmi->hdmi_data.video_mode.mPixelClock <= 216000000) {
++ switch (cRes) {
++ case 8:
++ hdmi_phy_i2c_write(hdmi, 0x06dc, 0x10);
++ break;
++ case 10:
++ hdmi_phy_i2c_write(hdmi, 0x0b5c, 0x10);
++ break;
++ case 12:
++ hdmi_phy_i2c_write(hdmi, 0x091c, 0x10);
++ break;
++ default:
++ return false;
++ }
++ } else {
++ dev_err(&hdmi->pdev->dev,
++ "Pixel clock %lu - unsupported by HDMI\n",
++ hdmi->hdmi_data.video_mode.mPixelClock);
++ return false;
++ }
++
++ hdmi_phy_i2c_write(hdmi, 0x0000, 0x13); /* PLLPHBYCTRL */
++ hdmi_phy_i2c_write(hdmi, 0x0006, 0x17);
++ /* RESISTANCE TERM 133Ohm Cfg */
++ hdmi_phy_i2c_write(hdmi, 0x0005, 0x19); /* TXTERM */
++ /* PREEMP Cgf 0.00 */
++ hdmi_phy_i2c_write(hdmi, 0x800d, 0x09); /* CKSYMTXCTRL */
++ /* TX/CK LVL 10 */
++ hdmi_phy_i2c_write(hdmi, 0x01ad, 0x0E); /* VLEVCTRL */
++
++ /* Board specific setting for PHY register 0x09, 0x0e to pass HCT */
++ if (hdmi->phy_config.reg_cksymtx != 0)
++ hdmi_phy_i2c_write(hdmi, hdmi->phy_config.reg_cksymtx, 0x09);
++
++ if (hdmi->phy_config.reg_vlev != 0)
++ hdmi_phy_i2c_write(hdmi, hdmi->phy_config.reg_vlev, 0x0E);
++
++ /* REMOVE CLK TERM */
++ hdmi_phy_i2c_write(hdmi, 0x8000, 0x05); /* CKCALCTRL */
++
++ if (hdmi->hdmi_data.video_mode.mPixelClock > 148500000) {
++ hdmi_phy_i2c_write(hdmi, 0x800b, 0x09);
++ hdmi_phy_i2c_write(hdmi, 0x0129, 0x0E);
++ }
++
++ mxc_hdmi_phy_enable_power(1);
++
++ /* toggle TMDS enable */
++ mxc_hdmi_phy_enable_tmds(0);
++ mxc_hdmi_phy_enable_tmds(1);
++
++ /* gen2 tx power on */
++ mxc_hdmi_phy_gen2_txpwron(1);
++ mxc_hdmi_phy_gen2_pddq(0);
++
++ /*Wait for PHY PLL lock */
++ msec = 4;
++ val = hdmi_readb(HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
++ while (val == 0) {
++ udelay(1000);
++ if (msec-- == 0) {
++ dev_dbg(&hdmi->pdev->dev, "PHY PLL not locked\n");
++ return false;
++ }
++ val = hdmi_readb(HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
++ }
++
++ return true;
++}
++
++static void mxc_hdmi_phy_init(struct mxc_hdmi *hdmi)
++{
++ int i;
++ bool cscon = false;
++
++ dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
++
++ /* Never do phy init if pixel clock is gated.
++ * Otherwise HDMI PHY will get messed up and generate an overflow
++ * interrupt that can't be cleared or detected by accessing the
++ * status register. */
++ if (!hdmi->fb_reg || !hdmi->cable_plugin
++ || (hdmi->blank != FB_BLANK_UNBLANK))
++ return;
++
++ /*check csc whether needed activated in HDMI mode */
++ cscon = (isColorSpaceConversion(hdmi) &&
++ !hdmi->hdmi_data.video_mode.mDVI);
++
++ /* HDMI Phy spec says to do the phy initialization sequence twice */
++ for (i = 0 ; i < 2 ; i++) {
++ mxc_hdmi_phy_sel_data_en_pol(1);
++ mxc_hdmi_phy_sel_interface_control(0);
++ mxc_hdmi_phy_enable_tmds(0);
++ mxc_hdmi_phy_enable_power(0);
++
++ /* Enable CSC */
++ hdmi_phy_configure(hdmi, 0, 8, cscon);
++ }
++
++ hdmi->phy_enabled = true;
++}
++
++static enum hdmi_3d_structure mxc_3d_structure_infoframe(u32 layout)
++{
++ switch (layout) {
++ case FB_VMODE_3D_SBS_HALF:
++ return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
++ case FB_VMODE_3D_SBS_FULL:
++ return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
++ case FB_VMODE_3D_TOP_BOTTOM:
++ return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
++ case FB_VMODE_3D_FRAME_PACK:
++ return HDMI_3D_STRUCTURE_FRAME_PACKING;
++ default:
++ return HDMI_3D_STRUCTURE_INVALID;
++ }
++}
++
++static int mxc_hdmi_vendor_infoframe(struct mxc_hdmi *hdmi, struct hdmi_vendor_infoframe *frame)
++{
++ int err;
++ u32 s3d_flags;
++ u8 vic;
++ uint8_t buffer[32]; //HDMI_FC_VSDPAYLOAD23 - HDMI_FC_VSDIEEEID0
++ //(with a hole starting at 0102B, ending 102F
++ ssize_t len;
++ int i;
++
++ if (!frame)
++ return -EINVAL;
++
++ vic = hdmi->vic;
++ s3d_flags = (*hdmi->fbi->mode).vmode & FB_VMODE_3D_MASK;
++
++ if (!vic && !s3d_flags)
++ return -EINVAL;
++
++ err = hdmi_vendor_infoframe_init(frame);
++ if (err < 0)
++ return err;
++
++ if (s3d_flags)
++ frame->s3d_struct = mxc_3d_structure_infoframe(s3d_flags);
++ else if (vic)
++ frame->vic = vic;
++ else
++ return -EINVAL;
++
++ /* see comment above for the reason for this offset */
++ len = hdmi_vendor_infoframe_pack(frame, buffer+1, sizeof(buffer)-1);
++ if (len < 0)
++ return -EINVAL;
++
++ buffer[0] = buffer[5];
++ buffer[1] = buffer[3];
++ buffer[2] = 0;
++ buffer[3] = 0;
++ buffer[4] = 0;
++ buffer[5] = 0;
++
++ //buffer[6] = buffer[6];
++ //buffer[7] = buffer[7];
++
++ for (i = 0; i < 32; i++)
++ hdmi_writeb(buffer[i], HDMI_FC_VSDIEEEID0 + i);
++ return 0;
++}
++
++static void hdmi_config_AVI(struct mxc_hdmi *hdmi)
++{
++ u8 val;
++ u8 pix_fmt;
++ u8 under_scan;
++ u8 act_ratio, coded_ratio, colorimetry, ext_colorimetry;
++ struct fb_videomode mode;
++ const struct fb_videomode *edid_mode;
++ bool aspect_16_9;
++ struct hdmi_vendor_infoframe vendor_infoframe;
++
++ dev_dbg(&hdmi->pdev->dev, "set up AVI frame\n");
++ fb_var_to_videomode(&mode, &hdmi->fbi->var);
++ /* Use mode from list extracted from EDID to get aspect ratio */
++ if (!list_empty(&hdmi->fbi->modelist)) {
++ edid_mode = fb_find_nearest_mode(&mode, &hdmi->fbi->modelist);
++ if (edid_mode->vmode & FB_VMODE_ASPECT_16_9)
++ aspect_16_9 = true;
++ else
++ aspect_16_9 = false;
++ } else
++ aspect_16_9 = false;
++
++ /********************************************
++ * AVI Data Byte 1
++ ********************************************/
++ if (hdmi->hdmi_data.enc_out_format == YCBCR444)
++ pix_fmt = HDMI_FC_AVICONF0_PIX_FMT_YCBCR444;
++ else if (hdmi->hdmi_data.enc_out_format == YCBCR422_8BITS)
++ pix_fmt = HDMI_FC_AVICONF0_PIX_FMT_YCBCR422;
++ else
++ pix_fmt = HDMI_FC_AVICONF0_PIX_FMT_RGB;
++
++ if (hdmi->edid_cfg.cea_underscan)
++ under_scan = HDMI_FC_AVICONF0_SCAN_INFO_UNDERSCAN;
++ else
++ under_scan = HDMI_FC_AVICONF0_SCAN_INFO_NODATA;
++
++ /*
++ * Active format identification data is present in the AVI InfoFrame.
++ * Under scan info, no bar data
++ */
++ val = pix_fmt | under_scan |
++ HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT |
++ HDMI_FC_AVICONF0_BAR_DATA_NO_DATA;
++
++ hdmi_writeb(val, HDMI_FC_AVICONF0);
++
++ /********************************************
++ * AVI Data Byte 2
++ ********************************************/
++
++ /* Set the Aspect Ratio */
++ if (aspect_16_9) {
++ act_ratio = HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9;
++ coded_ratio = HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9;
++ } else {
++ act_ratio = HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3;
++ coded_ratio = HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3;
++ }
++
++ /* Set up colorimetry */
++ if (hdmi->hdmi_data.enc_out_format == XVYCC444) {
++ colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO;
++ if (hdmi->hdmi_data.colorimetry == eITU601)
++ ext_colorimetry =
++ HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601;
++ else /* hdmi->hdmi_data.colorimetry == eITU709 */
++ ext_colorimetry =
++ HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709;
++ } else if (hdmi->hdmi_data.enc_out_format != RGB) {
++ if (hdmi->hdmi_data.colorimetry == eITU601)
++ colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_SMPTE;
++ else /* hdmi->hdmi_data.colorimetry == eITU709 */
++ colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_ITUR;
++ ext_colorimetry = HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601;
++ } else { /* Carries no data */
++ colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA;
++ ext_colorimetry = HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601;
++ }
++
++ val = colorimetry | coded_ratio | act_ratio;
++ hdmi_writeb(val, HDMI_FC_AVICONF1);
++
++ /********************************************
++ * AVI Data Byte 3
++ ********************************************/
++
++ val = HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA | ext_colorimetry |
++ hdmi->hdmi_data.rgb_quant_range |
++ HDMI_FC_AVICONF2_SCALING_NONE;
++ hdmi_writeb(val, HDMI_FC_AVICONF2);
++
++ /********************************************
++ * AVI Data Byte 4
++ ********************************************/
++ hdmi_writeb(hdmi->vic, HDMI_FC_AVIVID);
++
++ /********************************************
++ * AVI Data Byte 5
++ ********************************************/
++
++ /* Set up input and output pixel repetition */
++ val = (((hdmi->hdmi_data.video_mode.mPixelRepetitionInput + 1) <<
++ HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
++ HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
++ ((hdmi->hdmi_data.video_mode.mPixelRepetitionOutput <<
++ HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
++ HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
++ hdmi_writeb(val, HDMI_FC_PRCONF);
++
++ /* IT Content and quantization range = don't care */
++ val = HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS |
++ HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED;
++ hdmi_writeb(val, HDMI_FC_AVICONF3);
++
++ /********************************************
++ * AVI Data Bytes 6-13
++ ********************************************/
++ hdmi_writeb(0, HDMI_FC_AVIETB0);
++ hdmi_writeb(0, HDMI_FC_AVIETB1);
++ hdmi_writeb(0, HDMI_FC_AVISBB0);
++ hdmi_writeb(0, HDMI_FC_AVISBB1);
++ hdmi_writeb(0, HDMI_FC_AVIELB0);
++ hdmi_writeb(0, HDMI_FC_AVIELB1);
++ hdmi_writeb(0, HDMI_FC_AVISRB0);
++ hdmi_writeb(0, HDMI_FC_AVISRB1);
++
++ mxc_hdmi_vendor_infoframe(hdmi, &vendor_infoframe);
++}
++
++/*!
++ * this submodule is responsible for the video/audio data composition.
++ */
++static void hdmi_av_composer(struct mxc_hdmi *hdmi)
++{
++ u8 inv_val;
++ struct fb_info *fbi = hdmi->fbi;
++ struct fb_videomode fb_mode;
++ struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
++ int hblank, vblank;
++
++ dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
++
++ fb_var_to_videomode(&fb_mode, &fbi->var);
++
++ vmode->mHSyncPolarity = ((fb_mode.sync & FB_SYNC_HOR_HIGH_ACT) != 0);
++ vmode->mVSyncPolarity = ((fb_mode.sync & FB_SYNC_VERT_HIGH_ACT) != 0);
++ vmode->mInterlaced = ((fb_mode.vmode & FB_VMODE_INTERLACED) != 0);
++ vmode->mPixelClock = (u32) (PICOS2KHZ(fb_mode.pixclock) * 1000UL);
++
++ dev_dbg(&hdmi->pdev->dev, "final pixclk = %lu\n", vmode->mPixelClock);
++
++ /* Set up HDMI_FC_INVIDCONF */
++ inv_val = (vmode->mVSyncPolarity ?
++ HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
++ HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW);
++
++ inv_val |= (vmode->mHSyncPolarity ?
++ HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
++ HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW);
++
++ inv_val |= (vmode->mDataEnablePolarity ?
++ HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
++ HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
++
++ if (fb_mode.vmode & FB_VMODE_FRACTIONAL)
++ inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
++ else
++ inv_val |= (vmode->mInterlaced ?
++ HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
++ HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW);
++
++ inv_val |= (vmode->mInterlaced ?
++ HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
++ HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE);
++
++ inv_val |= (vmode->mDVI ?
++ HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE :
++ HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE);
++
++ hdmi_writeb(inv_val, HDMI_FC_INVIDCONF);
++
++ /* Set up horizontal active pixel region width */
++ hdmi_writeb(fb_mode.xres >> 8, HDMI_FC_INHACTV1);
++ hdmi_writeb(fb_mode.xres, HDMI_FC_INHACTV0);
++
++ /* Set up vertical blanking pixel region width */
++ if (vmode->mInterlaced) {
++ hdmi_writeb((fb_mode.yres/2) >> 8, HDMI_FC_INVACTV1);
++ hdmi_writeb((fb_mode.yres/2), HDMI_FC_INVACTV0);
++ } else {
++ hdmi_writeb(fb_mode.yres >> 8, HDMI_FC_INVACTV1);
++ hdmi_writeb(fb_mode.yres, HDMI_FC_INVACTV0);
++ }
++
++ /* Set up horizontal blanking pixel region width */
++ hblank = fb_mode.left_margin + fb_mode.right_margin +
++ fb_mode.hsync_len;
++ hdmi_writeb(hblank >> 8, HDMI_FC_INHBLANK1);
++ hdmi_writeb(hblank, HDMI_FC_INHBLANK0);
++
++ /* Set up vertical blanking pixel region width */
++ vblank = fb_mode.upper_margin + fb_mode.lower_margin +
++ fb_mode.vsync_len;
++ if (vmode->mInterlaced)
++ hdmi_writeb(vblank/2, HDMI_FC_INVBLANK);
++ else
++ hdmi_writeb(vblank, HDMI_FC_INVBLANK);
++
++ /* Set up HSYNC active edge delay width (in pixel clks) */
++ hdmi_writeb(fb_mode.right_margin >> 8, HDMI_FC_HSYNCINDELAY1);
++ hdmi_writeb(fb_mode.right_margin, HDMI_FC_HSYNCINDELAY0);
++
++ /* Set up VSYNC active edge delay (in pixel clks) */
++ if (vmode->mInterlaced)
++ hdmi_writeb(fb_mode.lower_margin / 2, HDMI_FC_VSYNCINDELAY);
++ else
++ hdmi_writeb(fb_mode.lower_margin, HDMI_FC_VSYNCINDELAY);
++
++ /* Set up HSYNC active pulse width (in pixel clks) */
++ hdmi_writeb(fb_mode.hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
++ hdmi_writeb(fb_mode.hsync_len, HDMI_FC_HSYNCINWIDTH0);
++
++ /* Set up VSYNC active edge delay (in pixel clks) */
++ if (vmode->mInterlaced)
++ hdmi_writeb(fb_mode.vsync_len / 2, HDMI_FC_VSYNCINWIDTH);
++ else
++ hdmi_writeb(fb_mode.vsync_len, HDMI_FC_VSYNCINWIDTH);
++
++ dev_dbg(&hdmi->pdev->dev, "%s exit\n", __func__);
++}
++
++static int mxc_edid_read_internal(struct mxc_hdmi *hdmi, unsigned char *edid,
++ struct mxc_edid_cfg *cfg, struct fb_info *fbi)
++{
++ int extblknum;
++ int i, j, ret;
++ unsigned char *ediddata = edid;
++ unsigned char tmpedid[EDID_LENGTH];
++
++ dev_info(&hdmi->pdev->dev, "%s\n", __func__);
++
++ if (!edid || !cfg || !fbi)
++ return -EINVAL;
++
++ /* init HDMI I2CM for read edid*/
++ hdmi_writeb(0x0, HDMI_I2CM_DIV);
++ hdmi_writeb(0x00, HDMI_I2CM_SS_SCL_HCNT_1_ADDR);
++ hdmi_writeb(0x79, HDMI_I2CM_SS_SCL_HCNT_0_ADDR);
++ hdmi_writeb(0x00, HDMI_I2CM_SS_SCL_LCNT_1_ADDR);
++ hdmi_writeb(0x91, HDMI_I2CM_SS_SCL_LCNT_0_ADDR);
++
++ hdmi_writeb(0x00, HDMI_I2CM_FS_SCL_HCNT_1_ADDR);
++ hdmi_writeb(0x0F, HDMI_I2CM_FS_SCL_HCNT_0_ADDR);
++ hdmi_writeb(0x00, HDMI_I2CM_FS_SCL_LCNT_1_ADDR);
++ hdmi_writeb(0x21, HDMI_I2CM_FS_SCL_LCNT_0_ADDR);
++
++ hdmi_writeb(0x50, HDMI_I2CM_SLAVE);
++ hdmi_writeb(0x30, HDMI_I2CM_SEGADDR);
++
++ /* Umask edid interrupt */
++ hdmi_writeb(HDMI_I2CM_INT_DONE_POL,
++ HDMI_I2CM_INT);
++
++ hdmi_writeb(HDMI_I2CM_CTLINT_NAC_POL |
++ HDMI_I2CM_CTLINT_ARBITRATION_POL,
++ HDMI_I2CM_CTLINT);
++
++ /* reset edid data zero */
++ memset(edid, 0, EDID_LENGTH*4);
++ memset(cfg, 0, sizeof(struct mxc_edid_cfg));
++
++ /* Check first three byte of EDID head */
++ if (!(hdmi_edid_i2c_read(hdmi, 0, 0) == 0x00) ||
++ !(hdmi_edid_i2c_read(hdmi, 1, 0) == 0xFF) ||
++ !(hdmi_edid_i2c_read(hdmi, 2, 0) == 0xFF)) {
++ dev_info(&hdmi->pdev->dev, "EDID head check failed!");
++ return -ENOENT;
++ }
++
++ for (i = 0; i < 128; i++) {
++ *ediddata = hdmi_edid_i2c_read(hdmi, i, 0);
++ ediddata++;
++ }
++
++ extblknum = edid[0x7E];
++ if (extblknum < 0)
++ return extblknum;
++
++ if (extblknum) {
++ ediddata = edid + EDID_LENGTH;
++ for (i = 0; i < 128; i++) {
++ *ediddata = hdmi_edid_i2c_read(hdmi, i, 1);
++ ediddata++;
++ }
++ }
++
++ /* edid first block parsing */
++ memset(&fbi->monspecs, 0, sizeof(fbi->monspecs));
++ fb_edid_to_monspecs(edid, &fbi->monspecs);
++
++ ret = mxc_edid_parse_ext_blk(edid + EDID_LENGTH,
++ cfg, &fbi->monspecs);
++ if (ret < 0) {
++ fb_edid_add_monspecs(edid + EDID_LENGTH, &fbi->monspecs);
++ if (fbi->monspecs.modedb_len > 0)
++ hdmi->edid_cfg.hdmi_cap = false;
++ else
++ return -ENOENT;
++ }
++
++ /* need read segment block? */
++ if (extblknum > 1) {
++ for (j = 1; j <= extblknum; j++) {
++ for (i = 0; i < 128; i++)
++ *(tmpedid + 1) = hdmi_edid_i2c_read(hdmi, i, j);
++
++ /* edid ext block parsing */
++ ret = mxc_edid_parse_ext_blk(tmpedid + EDID_LENGTH,
++ cfg, &fbi->monspecs);
++ if (ret < 0)
++ return -ENOENT;
++ }
++ }
++
++ return 0;
++}
++
++static int mxc_hdmi_read_edid(struct mxc_hdmi *hdmi)
++{
++ int ret;
++ u8 edid_old[HDMI_EDID_LEN];
++ u8 clkdis;
++
++ dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
++
++ /* save old edid */
++ memcpy(edid_old, hdmi->edid, HDMI_EDID_LEN);
++
++ /* Read EDID via HDMI DDC when HDCP Enable */
++ if (!hdcp_init)
++ ret = mxc_edid_read(hdmi_i2c->adapter, hdmi_i2c->addr,
++ hdmi->edid, &hdmi->edid_cfg, hdmi->fbi);
++ else {
++
++ /* Disable HDCP clk */
++ if (hdmi->hdmi_data.hdcp_enable) {
++ clkdis = hdmi_readb(HDMI_MC_CLKDIS);
++ clkdis |= HDMI_MC_CLKDIS_HDCPCLK_DISABLE;
++ hdmi_writeb(clkdis, HDMI_MC_CLKDIS);
++ }
++
++ ret = mxc_edid_read_internal(hdmi, hdmi->edid,
++ &hdmi->edid_cfg, hdmi->fbi);
++
++ /* Enable HDCP clk */
++ if (hdmi->hdmi_data.hdcp_enable) {
++ clkdis = hdmi_readb(HDMI_MC_CLKDIS);
++ clkdis &= ~HDMI_MC_CLKDIS_HDCPCLK_DISABLE;
++ hdmi_writeb(clkdis, HDMI_MC_CLKDIS);
++ }
++
++ }
++
++ if (ret < 0)
++ return HDMI_EDID_FAIL;
++
++ dev_info(&hdmi->pdev->dev, "%s HDMI in %s mode\n", __func__, hdmi->edid_cfg.hdmi_cap?"HDMI":"DVI");
++ hdmi->plug_event = hdmi->edid_cfg.hdmi_cap?HDMI_IH_PHY_STAT0_HPD:HDMI_DVI_IH_STAT;
++ hdmi->plug_mask = hdmi->edid_cfg.hdmi_cap?HDMI_PHY_HPD:HDMI_DVI_STAT;
++
++ if (!memcmp(edid_old, hdmi->edid, HDMI_EDID_LEN)) {
++ dev_info(&hdmi->pdev->dev, "same edid\n");
++ return HDMI_EDID_SAME;
++ }
++
++ if (hdmi->fbi->monspecs.modedb_len == 0) {
++ dev_info(&hdmi->pdev->dev, "No modes read from edid\n");
++ return HDMI_EDID_NO_MODES;
++ }
++
++ return HDMI_EDID_SUCCESS;
++}
++
++static void mxc_hdmi_phy_disable(struct mxc_hdmi *hdmi)
++{
++ dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
++
++ if (!hdmi->phy_enabled)
++ return;
++
++ hdmi_disable_overflow_interrupts();
++
++ /* Setting PHY to reset status */
++ hdmi_writeb(HDMI_MC_PHYRSTZ_DEASSERT, HDMI_MC_PHYRSTZ);
++
++ /* Power down PHY */
++ mxc_hdmi_phy_enable_tmds(0);
++ mxc_hdmi_phy_enable_power(0);
++ mxc_hdmi_phy_gen2_txpwron(0);
++ mxc_hdmi_phy_gen2_pddq(1);
++
++ hdmi->phy_enabled = false;
++ dev_dbg(&hdmi->pdev->dev, "%s - exit\n", __func__);
++}
++
++/* HDMI Initialization Step B.4 */
++static void mxc_hdmi_enable_video_path(struct mxc_hdmi *hdmi)
++{
++ u8 clkdis;
++
++ dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
++
++ /* control period minimum duration */
++ hdmi_writeb(12, HDMI_FC_CTRLDUR);
++ hdmi_writeb(32, HDMI_FC_EXCTRLDUR);
++ hdmi_writeb(1, HDMI_FC_EXCTRLSPAC);
++
++ /* Set to fill TMDS data channels */
++ hdmi_writeb(0x0B, HDMI_FC_CH0PREAM);
++ hdmi_writeb(0x16, HDMI_FC_CH1PREAM);
++ hdmi_writeb(0x21, HDMI_FC_CH2PREAM);
++
++ /* Save CEC clock */
++ clkdis = hdmi_readb(HDMI_MC_CLKDIS) & HDMI_MC_CLKDIS_CECCLK_DISABLE;
++ clkdis |= ~HDMI_MC_CLKDIS_CECCLK_DISABLE;
++
++ /* Enable pixel clock and tmds data path */
++ clkdis = 0x7F & clkdis;
++ clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
++ hdmi_writeb(clkdis, HDMI_MC_CLKDIS);
++
++ clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
++ hdmi_writeb(clkdis, HDMI_MC_CLKDIS);
++
++ /* Enable csc path */
++ if (isColorSpaceConversion(hdmi) && !hdmi->hdmi_data.video_mode.mDVI) {
++ clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
++ hdmi_writeb(clkdis, HDMI_MC_CLKDIS);
++ }
++}
++
++static void hdmi_enable_audio_clk(struct mxc_hdmi *hdmi)
++{
++ u8 clkdis;
++
++ dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
++
++ clkdis = hdmi_readb(HDMI_MC_CLKDIS);
++ clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE;
++ hdmi_writeb(clkdis, HDMI_MC_CLKDIS);
++}
++
++/* Workaround to clear the overflow condition */
++static void mxc_hdmi_clear_overflow(struct mxc_hdmi *hdmi)
++{
++ int count;
++ u8 val;
++
++ /* TMDS software reset */
++ hdmi_writeb((u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
++
++ val = hdmi_readb(HDMI_FC_INVIDCONF);
++
++ if (cpu_is_imx6dl(hdmi)) {
++ hdmi_writeb(val, HDMI_FC_INVIDCONF);
++ return;
++ }
++
++ for (count = 0 ; count < 5 ; count++)
++ hdmi_writeb(val, HDMI_FC_INVIDCONF);
++}
++
++static void hdmi_enable_overflow_interrupts(void)
++{
++ pr_debug("%s\n", __func__);
++ hdmi_writeb(0, HDMI_FC_MASK2);
++ hdmi_writeb(0, HDMI_IH_MUTE_FC_STAT2);
++}
++
++static void hdmi_disable_overflow_interrupts(void)
++{
++ pr_debug("%s\n", __func__);
++ hdmi_writeb(HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
++ HDMI_IH_MUTE_FC_STAT2);
++ hdmi_writeb(0x7f, HDMI_FC_MASK2);
++}
++
++static void mxc_hdmi_notify_fb(struct mxc_hdmi *hdmi)
++{
++ dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
++
++ /* Don't notify if we aren't registered yet */
++ WARN_ON(!hdmi->fb_reg);
++
++ /* disable the phy before ipu changes mode */
++ mxc_hdmi_phy_disable(hdmi);
++
++ /*
++ * Note that fb_set_var will block. During this time,
++ * FB_EVENT_MODE_CHANGE callback will happen.
++ * So by the end of this function, mxc_hdmi_setup()
++ * will be done.
++ */
++ hdmi->fbi->var.activate |= FB_ACTIVATE_FORCE;
++ console_lock();
++ hdmi->fbi->flags |= FBINFO_MISC_USEREVENT;
++ fb_set_var(hdmi->fbi, &hdmi->fbi->var);
++ hdmi->fbi->flags &= ~FBINFO_MISC_USEREVENT;
++ console_unlock();
++
++ dev_dbg(&hdmi->pdev->dev, "%s exit\n", __func__);
++}
++
++inline
++static void mxc_fb_add_videomode(const struct fb_videomode *src_mode, struct list_head *modelist, const u32 new_flag, const u32 mod_vmode)
++{
++ struct fb_videomode mode;
++
++ memcpy(&mode, src_mode, sizeof(struct fb_videomode));
++ mode.flag = new_flag; mode.vmode |= mod_vmode;
++ fb_add_videomode(&mode, modelist);
++}
++
++enum {
++ hzSTART = 0,
++ hz50 = 50,
++ hz60 = 60,
++ hzEND = 61
++};
++
++struct stereo_mandatory_mode {
++ int rfc_refresh;
++ const struct fb_videomode *rfc_parent_cea_mode;
++ uint32_t flag;
++ uint32_t vmode;
++};
++
++static struct stereo_mandatory_mode stereo_mandatory_modes[] = {
++ // 1280x720p @ 59.94 / 60Hz TOP-and-BOTTOM
++ { 60, &mxc_cea_mode[4], FB_MODE_IS_3D, FB_VMODE_3D_TOP_BOTTOM },
++ // 1920x1080p @ 23.98 / 24Hz TOP-and-BOTTOM
++ { 60, &mxc_cea_mode[32], FB_MODE_IS_3D, FB_VMODE_3D_TOP_BOTTOM },
++ // 1280x720p @ 59.94 / 60Hz FRAME-PACK
++ { 60, &mxc_cea_mode[4], FB_MODE_IS_3D, FB_VMODE_3D_FRAME_PACK },
++ // 1920x1080p @ 23.98 / 24Hz FRAME-PACK
++ { 60, &mxc_cea_mode[32], FB_MODE_IS_3D, FB_VMODE_3D_FRAME_PACK },
++ // 1920x1080i @ 59.94 / 60Hz SIDE-by-SIDE half
++ { 60, &mxc_cea_mode[5], FB_MODE_IS_3D, FB_VMODE_3D_SBS_HALF },
++ // 1280x720p @ 50Hz TOP-and-BOTTOM
++ { 50, &mxc_cea_mode[19], FB_MODE_IS_3D, FB_VMODE_3D_TOP_BOTTOM },
++ // 1280x720p @ 50Hz FRAME-PACK
++ { 50, &mxc_cea_mode[19], FB_MODE_IS_3D, FB_VMODE_3D_FRAME_PACK },
++ // 1920x1080i @ 50Hz SIDE-by-SIDE half
++ { 50, &mxc_cea_mode[20], FB_MODE_IS_3D, FB_VMODE_3D_SBS_HALF }
++};
++
++static void mxc_hdmi_edid_rebuild_modelist(struct mxc_hdmi *hdmi)
++{
++ int i, j, k, nvic = 0, vic;
++ struct fb_videomode *mode;
++
++ dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
++
++ console_lock();
++
++ fb_destroy_modelist(&hdmi->fbi->modelist);
++ fb_add_videomode(&vga_mode, &hdmi->fbi->modelist);
++
++ for (i = 0; i < hdmi->fbi->monspecs.modedb_len; i++) {
++ /*
++ * We might check here if mode is supported by HDMI.
++ * We do not currently support interlaced modes.
++ * And add CEA modes in the modelist.
++ */
++ mode = &hdmi->fbi->monspecs.modedb[i];
++
++ if ((vic = mxc_edid_mode_to_vic(mode, 0)))
++ nvic++;
++
++ // allow detailed timing specification with vic=0 for HDMI
++ // mode
++ if (hdmi->edid_cfg.hdmi_cap &&
++ (((mode->flag != FB_MODE_IS_DETAILED) && (vic == 0))
++ ||
++ (mode->flag == FB_MODE_IS_VESA)))
++ continue;
++
++ if (!mode->xres || !mode->refresh)
++ continue;
++
++ if (!(mode->vmode & FB_VMODE_ASPECT_MASK)) {
++ if (mode->yres == (mode->xres * 3)/4)
++ mode->vmode |= FB_VMODE_ASPECT_4_3;
++ else
++ mode->vmode |= FB_VMODE_ASPECT_16_9;
++ }
++
++ for (j = 0; j < 1 || (hdmi->hdmi_data.enable_fract && j < 2); j++) {
++ struct fb_videomode *tm = mode;
++ struct fb_videomode mode2;
++ char refresh[10];
++
++ if (j == 1 && (mode->refresh != 24 && mode->refresh != 30 && mode->refresh != 60))
++ break;
++
++ switch (j) {
++ case 1:
++ memcpy(&mode2, mode, sizeof(struct fb_videomode));
++ mode2.vmode = mode->vmode | FB_VMODE_FRACTIONAL;
++ mode2.pixclock = PICOS2KHZ(KHZ2PICOS(mode2.pixclock) * 1000/1001);
++ fb_add_videomode(&mode2, &hdmi->fbi->modelist);
++ tm = &mode2;
++ break;
++ default:
++ break;
++ }
++
++ get_refresh_str(tm, refresh);
++ dev_info(&hdmi->pdev->dev, "Added mode: %d, vic: %d %s", i, vic, j == 1 ? " fractional" : "");
++ dev_info(&hdmi->pdev->dev,
++ "xres = %d, yres = %d, ratio = %s, freq = %s, vmode = %d, flag = %d, pclk = %d\n",
++ tm->xres,
++ tm->yres,
++ tm->vmode & FB_VMODE_ASPECT_1 ? "1" :
++ mode->vmode & FB_VMODE_ASPECT_4_3 ? "4/3" :
++ mode->vmode & FB_VMODE_ASPECT_5_4 ? "5/4" :
++ mode->vmode & FB_VMODE_ASPECT_16_10 ? "16/10" :
++ mode->vmode & FB_VMODE_ASPECT_16_9 ? "16/9" : "n/a",
++ refresh,
++ tm->vmode,
++ tm->flag,
++ tm->pixclock);
++ fb_add_videomode(tm, &hdmi->fbi->modelist);
++ }
++
++ if (!hdmi->hdmi_data.enable_3d || !vic)
++ continue;
++
++ /* according to HDMI 1.4 specs, add mandatory modes for 50 and 60Hz existing 2d modes */
++ for (k = hzSTART + 1; k < hzEND; k++) {
++ if (mode->refresh == k && hdmi->edid_cfg.hdmi_3d_present) {
++ for (j = 0; j < sizeof(stereo_mandatory_modes) / sizeof(struct stereo_mandatory_mode); j++) {
++ if (stereo_mandatory_modes[j].rfc_refresh != k)
++ continue;
++ mxc_fb_add_videomode(stereo_mandatory_modes[j].rfc_parent_cea_mode, &hdmi->fbi->modelist,
++ stereo_mandatory_modes[j].flag, stereo_mandatory_modes[j].vmode);
++ }
++ }
++ }
++
++ if ((hdmi->edid_cfg.hdmi_3d_multi_present == 2 && hdmi->edid_cfg.hdmi_3d_mask_all & (1 << (nvic-1))) ||
++ (hdmi->edid_cfg.hdmi_3d_multi_present == 1 && nvic <= 16)) {
++ if (hdmi->edid_cfg.hdmi_3d_struct_all & 0x1)
++ mxc_fb_add_videomode(mode, &hdmi->fbi->modelist, FB_MODE_IS_3D, FB_VMODE_3D_FRAME_PACK);
++ if (hdmi->edid_cfg.hdmi_3d_struct_all & 0x6)
++ mxc_fb_add_videomode(mode, &hdmi->fbi->modelist, FB_MODE_IS_3D, FB_VMODE_3D_SBS_FULL);
++ if (hdmi->edid_cfg.hdmi_3d_struct_all & 0x40)
++ mxc_fb_add_videomode(mode, &hdmi->fbi->modelist, FB_MODE_IS_3D, FB_VMODE_3D_TOP_BOTTOM);
++ if (hdmi->edid_cfg.hdmi_3d_struct_all & 0x100)
++ mxc_fb_add_videomode(mode, &hdmi->fbi->modelist, FB_MODE_IS_3D, FB_VMODE_3D_SBS_HALF);
++ }
++
++ for (j = 0; j < hdmi->edid_cfg.hdmi_3d_len; j++) {
++ if (hdmi->edid_cfg.hdmi_3d_format[j].vic_order_2d != nvic-1)
++ continue;
++
++ if (hdmi->edid_cfg.hdmi_3d_format[j].struct_3d == 0)
++ mxc_fb_add_videomode(mode, &hdmi->fbi->modelist, FB_MODE_IS_3D, FB_VMODE_3D_FRAME_PACK);
++ if (hdmi->edid_cfg.hdmi_3d_format[j].struct_3d == 3)
++ mxc_fb_add_videomode(mode, &hdmi->fbi->modelist, FB_MODE_IS_3D, FB_VMODE_3D_SBS_FULL);
++ if (hdmi->edid_cfg.hdmi_3d_format[j].struct_3d == 6)
++ mxc_fb_add_videomode(mode, &hdmi->fbi->modelist, FB_MODE_IS_3D, FB_VMODE_3D_TOP_BOTTOM);
++ if (hdmi->edid_cfg.hdmi_3d_format[j].struct_3d == 8)
++ mxc_fb_add_videomode(mode, &hdmi->fbi->modelist, FB_MODE_IS_3D, FB_VMODE_3D_SBS_HALF);
++ }
++ }
++
++ fb_new_modelist(hdmi->fbi);
++
++ console_unlock();
++}
++
++static void mxc_hdmi_default_edid_cfg(struct mxc_hdmi *hdmi)
++{
++ /* Default setting HDMI working in HDMI mode */
++ hdmi->edid_cfg.hdmi_cap = true;
++}
++
++static void mxc_hdmi_default_modelist(struct mxc_hdmi *hdmi)
++{
++ u32 i;
++ const struct fb_videomode *mode;
++ struct fb_videomode m;
++
++ dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
++
++ /* If not EDID data read, set up default modelist */
++ dev_info(&hdmi->pdev->dev, "No modes read from edid\n");
++ dev_info(&hdmi->pdev->dev, "create default modelist\n");
++
++ console_lock();
++
++ fb_destroy_modelist(&hdmi->fbi->modelist);
++
++ fb_var_to_videomode(&m, &hdmi->fbi->var);
++ fb_add_videomode(&m, &hdmi->fbi->modelist);
++
++ /*Add all no interlaced CEA mode to default modelist */
++ for (i = 0; i < ARRAY_SIZE(mxc_cea_mode); i++) {
++ mode = &mxc_cea_mode[i];
++ if (mode->xres != 0)
++ fb_add_videomode(mode, &hdmi->fbi->modelist);
++ }
++
++ fb_new_modelist(hdmi->fbi);
++
++ console_unlock();
++}
++
++static void mxc_hdmi_set_mode(struct mxc_hdmi *hdmi)
++{
++ const struct fb_videomode *mode;
++ struct fb_videomode m;
++ struct fb_var_screeninfo var;
++
++ dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
++
++ /* Set the default mode only once. */
++ if (!hdmi->dft_mode_set) {
++ fb_videomode_to_var(&var, &hdmi->default_mode);
++ hdmi->dft_mode_set = true;
++ hdmi->requesting_vga_for_initialization = false;
++ } else
++ memcpy(&var, &hdmi->previous_non_vga_mode,
++ sizeof(struct fb_var_screeninfo));
++
++ fb_var_to_videomode(&m, &var);
++
++ mode = mxc_fb_find_nearest_mode(&m, &hdmi->fbi->modelist);
++ if (!mode) {
++ pr_err("%s: could not find mode in modelist\n", __func__);
++ return;
++ }
++
++ /* If video mode same as previous, init HDMI again */
++ if (fb_mode_is_equal(&m, mode) && hdmi->edid_status == HDMI_EDID_SAME) {
++ dev_dbg(&hdmi->pdev->dev,
++ "%s: Video mode and EDID same as previous\n", __func__);
++ /* update fbi mode in case modelist is updated */
++ hdmi->fbi->mode = (struct fb_videomode *)mode;
++ memcpy(&hdmi->fbi->var, &hdmi->previous_non_vga_mode,
++ sizeof(struct fb_var_screeninfo));
++ /* update hdmi setting in case EDID data updated */
++ mxc_hdmi_setup(hdmi, 0);
++ } else if (fb_mode_is_equal(&m, mode)) {
++ dev_dbg(&hdmi->pdev->dev,
++ "%s: Video mode same as previous\n", __func__);
++ /* update fbi mode in case modelist is updated */
++ hdmi->fbi->mode = (struct fb_videomode *)mode;
++ dump_fb_videomode(hdmi->fbi->mode);
++ memcpy(&hdmi->fbi->var, &hdmi->previous_non_vga_mode,
++ sizeof(struct fb_var_screeninfo));
++ mxc_hdmi_notify_fb(hdmi);
++ } else {
++ dev_dbg(&hdmi->pdev->dev, "%s: New video mode\n", __func__);
++ fb_videomode_to_var(&hdmi->fbi->var, mode);
++ dump_fb_videomode((struct fb_videomode *)mode);
++ mxc_hdmi_notify_fb(hdmi);
++ }
++
++}
++
++static void mxc_hdmi_cable_connected(struct mxc_hdmi *hdmi)
++{
++ dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
++
++ hdmi->cable_plugin = true;
++
++ /* HDMI Initialization Step C */
++ hdmi->edid_status = mxc_hdmi_read_edid(hdmi);
++
++ /* Read EDID again if first EDID read failed */
++ if (hdmi->edid_status == HDMI_EDID_NO_MODES ||
++ hdmi->edid_status == HDMI_EDID_FAIL) {
++ dev_info(&hdmi->pdev->dev, "Read EDID again\n");
++ msleep(25);
++ hdmi->edid_status = mxc_hdmi_read_edid(hdmi);
++ }
++
++ /* HDMI Initialization Steps D, E, F */
++ switch (hdmi->edid_status) {
++ case HDMI_EDID_SUCCESS:
++ mxc_hdmi_edid_rebuild_modelist(hdmi);
++ break;
++
++ /* Nothing to do if EDID same */
++ case HDMI_EDID_SAME:
++ break;
++
++ case HDMI_EDID_FAIL:
++ mxc_hdmi_default_edid_cfg(hdmi);
++ /* No break here */
++ case HDMI_EDID_NO_MODES:
++ default:
++ mxc_hdmi_default_modelist(hdmi);
++ break;
++ }
++
++ /* Save edid cfg for audio driver */
++ hdmi_set_edid_cfg(hdmi->edid_status, &hdmi->edid_cfg);
++
++ /* Setting video mode */
++ mxc_hdmi_set_mode(hdmi);
++
++ dev_dbg(&hdmi->pdev->dev, "%s exit\n", __func__);
++}
++
++static int mxc_hdmi_power_on(struct mxc_dispdrv_handle *disp)
++{
++ struct mxc_hdmi *hdmi = mxc_dispdrv_getdata(disp);
++
++ dev_dbg(&hdmi->pdev->dev, "%s reg %d cable %d blank %d\n", __func__, hdmi->fb_reg, hdmi->cable_plugin, hdmi->blank);
++
++ mxc_hdmi_phy_init(hdmi);
++ hdmi_clk_regenerator_update_pixel_clock(hdmi->fbi->var.pixclock);
++ return 0;
++}
++
++static void mxc_hdmi_power_off(struct mxc_dispdrv_handle *disp)
++{
++ struct mxc_hdmi *hdmi = mxc_dispdrv_getdata(disp);
++
++ dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
++
++ mxc_hdmi_phy_disable(hdmi);
++}
++
++static void mxc_hdmi_cable_disconnected(struct mxc_hdmi *hdmi)
++{
++ u8 clkdis;
++
++ dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
++
++ /* Save CEC clock */
++ clkdis = hdmi_readb(HDMI_MC_CLKDIS) & HDMI_MC_CLKDIS_CECCLK_DISABLE;
++ clkdis |= ~HDMI_MC_CLKDIS_CECCLK_DISABLE;
++
++ /* Disable All HDMI clock */
++ hdmi_writeb(0x7f, HDMI_MC_CLKDIS);
++
++ mxc_hdmi_phy_disable(hdmi);
++
++ //hdmi_disable_overflow_interrupts();
++ hdmi_writeb(clkdis, HDMI_MC_CLKDIS);
++
++ hdmi->cable_plugin = false;
++}
++
++static void hotplug_worker(struct work_struct *work)
++{
++ struct mxc_hdmi *hdmi =
++ container_of(work, struct mxc_hdmi, hotplug_work);
++ u32 hdmi_phy_stat0, hdmi_phy_pol0, hdmi_phy_mask0;
++ unsigned long flags;
++ char event_string[32];
++ char *envp[] = { event_string, NULL };
++ u32 l;
++
++ hdmi_phy_stat0 = hdmi_readb(HDMI_PHY_STAT0);
++ hdmi_phy_pol0 = hdmi_readb(HDMI_PHY_POL0);
++
++ dev_dbg(&hdmi->pdev->dev, "phy_int_stat=0x%x/0x%x, phy_int_pol=0x%x, plug_event=0x%x, plug_mask=0x%x\n",
++ hdmi_phy_stat0, hdmi->latest_intr_stat, hdmi_phy_pol0, hdmi->plug_event, hdmi->plug_mask);
++
++ /* Make HPD intr active low to capture unplug event or
++ * active high to capture plugin event */
++ hdmi_writeb((hdmi->plug_mask & ~hdmi_phy_pol0), HDMI_PHY_POL0);
++
++ /* cable connection changes */
++ if (hdmi_phy_pol0 & hdmi->plug_mask) {
++ /* Plugin event */
++ dev_dbg(&hdmi->pdev->dev, "EVENT=plugin\n");
++ mxc_hdmi_cable_connected(hdmi);
++
++ sprintf(event_string, "EVENT=plugin");
++ kobject_uevent_env(&hdmi->pdev->dev.kobj, KOBJ_CHANGE, envp);
++#ifdef CONFIG_MXC_HDMI_CEC
++ memcpy(&l, &hdmi->edid_cfg.physical_address, 4 *sizeof(u8));
++ mxc_hdmi_cec_handle(l);
++#endif
++ hdmi_set_cable_state(1);
++ } else {
++ /* Plugout event */
++ dev_dbg(&hdmi->pdev->dev, "EVENT=plugout\n");
++ hdmi_set_cable_state(0);
++ mxc_hdmi_abort_stream();
++ mxc_hdmi_cable_disconnected(hdmi);
++
++ sprintf(event_string, "EVENT=plugout");
++ kobject_uevent_env(&hdmi->pdev->dev.kobj, KOBJ_CHANGE, envp);
++#ifdef CONFIG_MXC_HDMI_CEC
++ mxc_hdmi_cec_handle(0x0);
++#endif
++ }
++
++ /* Lock here to ensure full powerdown sequence
++ * completed before next interrupt processed */
++ spin_lock_irqsave(&hdmi->irq_lock, flags);
++
++ /* Re-enable HPD interrupts */
++ hdmi_phy_mask0 = hdmi_readb(HDMI_PHY_MASK0);
++ hdmi_phy_mask0 &= ~hdmi->plug_mask;
++ hdmi_writeb(hdmi_phy_mask0, HDMI_PHY_MASK0);
++
++ /* Unmute interrupts */
++ hdmi_writeb(~hdmi->plug_event, HDMI_IH_MUTE_PHY_STAT0);
++
++ if (hdmi_readb(HDMI_IH_FC_STAT2) & HDMI_IH_FC_STAT2_OVERFLOW_MASK)
++ mxc_hdmi_clear_overflow(hdmi);
++
++ spin_unlock_irqrestore(&hdmi->irq_lock, flags);
++ pr_debug("%s exit\n", __func__);
++}
++
++static void hotplug_work_launch(unsigned long data)
++{
++ struct mxc_hdmi *hdmi = (struct mxc_hdmi *)data;
++ pr_debug("%s\n", __func__);
++ schedule_work(&hdmi->hotplug_work);
++}
++
++static void hdcp_hdp_worker(struct work_struct *work)
++{
++ struct delayed_work *delay_work = to_delayed_work(work);
++ struct mxc_hdmi *hdmi =
++ container_of(delay_work, struct mxc_hdmi, hdcp_hdp_work);
++ char event_string[32];
++ char *envp[] = { event_string, NULL };
++
++ /* HDCP interrupt */
++ sprintf(event_string, "EVENT=hdcpint");
++ kobject_uevent_env(&hdmi->pdev->dev.kobj, KOBJ_CHANGE, envp);
++
++ /* Unmute interrupts in HDCP application*/
++}
++
++static irqreturn_t mxc_hdmi_hotplug(int irq, void *data)
++{
++ struct mxc_hdmi *hdmi = data;
++ u8 val, intr_stat;
++ unsigned long flags;
++
++ spin_lock_irqsave(&hdmi->irq_lock, flags);
++
++ /* Check and clean packet overflow interrupt.*/
++ if (hdmi_readb(HDMI_IH_FC_STAT2) &
++ HDMI_IH_FC_STAT2_OVERFLOW_MASK) {
++ mxc_hdmi_clear_overflow(hdmi);
++
++ dev_dbg(&hdmi->pdev->dev, "Overflow interrupt received\n");
++ /* clear irq status */
++ hdmi_writeb(HDMI_IH_FC_STAT2_OVERFLOW_MASK,
++ HDMI_IH_FC_STAT2);
++ }
++
++ /*
++ * We could not disable the irq. Probably the audio driver
++ * has enabled it. Masking off the HDMI interrupts using
++ * HDMI registers.
++ */
++ /* Capture status - used in hotplug_worker ISR */
++ intr_stat = hdmi_readb(HDMI_IH_PHY_STAT0);
++ if (intr_stat & hdmi->plug_event) {
++
++ dev_dbg(&hdmi->pdev->dev, "Hotplug interrupt received\n");
++ hdmi->latest_intr_stat = intr_stat;
++
++ /* Mute interrupts until handled */
++
++ val = hdmi_readb(HDMI_IH_MUTE_PHY_STAT0);
++ val |= hdmi->plug_event;
++ hdmi_writeb(val, HDMI_IH_MUTE_PHY_STAT0);
++
++ val = hdmi_readb(HDMI_PHY_MASK0);
++ val |= hdmi->plug_mask;
++ hdmi_writeb(val, HDMI_PHY_MASK0);
++
++ /* Clear Hotplug interrupts */
++ hdmi_writeb(hdmi->plug_event, HDMI_IH_PHY_STAT0);
++
++ if(hdmi_inited) {
++ if (!hdmi->dft_mode_set)
++ mod_timer(&hdmi->jitter_timer, jiffies + msecs_to_jiffies(20));
++ else
++ mod_timer(&hdmi->jitter_timer, jiffies + HZ);
++ }
++ }
++
++ /* Check HDCP interrupt state */
++ if (hdmi->hdmi_data.hdcp_enable) {
++ val = hdmi_readb(HDMI_A_APIINTSTAT);
++ if (val != 0) {
++ /* Mute interrupts until interrupt handled */
++ val = 0x7F;
++ hdmi_writeb(val, HDMI_A_APIINTMSK);
++ schedule_delayed_work(&(hdmi->hdcp_hdp_work), msecs_to_jiffies(50));
++ }
++ }
++
++ spin_unlock_irqrestore(&hdmi->irq_lock, flags);
++ return IRQ_HANDLED;
++}
++
++static void mxc_hdmi_setup(struct mxc_hdmi *hdmi, unsigned long event)
++{
++ struct fb_videomode m;
++ const struct fb_videomode *edid_mode;
++
++ dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
++
++ fb_var_to_videomode(&m, &hdmi->fbi->var);
++
++ dev_dbg(&hdmi->pdev->dev, "%s - video mode changed\n", __func__);
++
++ hdmi->vic = 0;
++ if (!hdmi->requesting_vga_for_initialization) {
++ /* Save mode if this isn't the result of requesting
++ * vga default. */
++ memcpy(&hdmi->previous_non_vga_mode, &hdmi->fbi->var,
++ sizeof(struct fb_var_screeninfo));
++ if (!list_empty(&hdmi->fbi->modelist)) {
++ edid_mode = mxc_fb_find_nearest_mode(&m, &hdmi->fbi->modelist);
++ pr_debug("edid mode vx:%d vy:%d", hdmi->fbi->var.xres_virtual, hdmi->fbi->var.yres_virtual);
++ dump_fb_videomode((struct fb_videomode *)edid_mode);
++ /* update fbi mode */
++ hdmi->fbi->mode = (struct fb_videomode *)edid_mode;
++ hdmi->vic = mxc_edid_mode_to_vic(edid_mode, 0);
++ }
++ }
++
++ hdmi_disable_overflow_interrupts();
++
++ dev_dbg(&hdmi->pdev->dev, "CEA mode used vic=%d\n", hdmi->vic);
++ if (hdmi->edid_cfg.hdmi_cap || !hdmi->edid_status) {
++ hdmi_set_dvi_mode(0);
++ hdmi->hdmi_data.video_mode.mDVI = false;
++ } else {
++ hdmi_set_dvi_mode(1);
++ dev_dbg(&hdmi->pdev->dev, "CEA mode vic=%d work in DVI\n", hdmi->vic);
++ hdmi->hdmi_data.video_mode.mDVI = true;
++ }
++
++ if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
++ (hdmi->vic == 21) || (hdmi->vic == 22) ||
++ (hdmi->vic == 2) || (hdmi->vic == 3) ||
++ (hdmi->vic == 17) || (hdmi->vic == 18))
++ hdmi->hdmi_data.colorimetry = eITU601;
++ else
++ hdmi->hdmi_data.colorimetry = eITU709;
++
++ if ((hdmi->vic == 10) || (hdmi->vic == 11) ||
++ (hdmi->vic == 12) || (hdmi->vic == 13) ||
++ (hdmi->vic == 14) || (hdmi->vic == 15) ||
++ (hdmi->vic == 25) || (hdmi->vic == 26) ||
++ (hdmi->vic == 27) || (hdmi->vic == 28) ||
++ (hdmi->vic == 29) || (hdmi->vic == 30) ||
++ (hdmi->vic == 35) || (hdmi->vic == 36) ||
++ (hdmi->vic == 37) || (hdmi->vic == 38))
++ hdmi->hdmi_data.video_mode.mPixelRepetitionOutput = 1;
++ else
++ hdmi->hdmi_data.video_mode.mPixelRepetitionOutput = 0;
++
++ hdmi->hdmi_data.video_mode.mPixelRepetitionInput = 0;
++
++ /* TODO: Get input format from IPU (via FB driver iface) */
++ hdmi->hdmi_data.enc_in_format = RGB;
++
++ hdmi->hdmi_data.enc_out_format = RGB;
++
++ /* YCbCr only enabled in HDMI mode */
++ if (!hdmi->hdmi_data.video_mode.mDVI &&
++ !hdmi->hdmi_data.rgb_out_enable) {
++ if (hdmi->edid_cfg.cea_ycbcr444)
++ hdmi->hdmi_data.enc_out_format = YCBCR444;
++ else if (hdmi->edid_cfg.cea_ycbcr422)
++ hdmi->hdmi_data.enc_out_format = YCBCR422_8BITS;
++ }
++
++ /* IPU not support depth color output */
++ hdmi->hdmi_data.enc_color_depth = 8;
++ hdmi->hdmi_data.pix_repet_factor = 0;
++ hdmi->hdmi_data.video_mode.mDataEnablePolarity = true;
++
++ /* HDMI Initialization Step B.1 */
++ hdmi_av_composer(hdmi);
++
++ /* HDMI Initializateion Step B.2 */
++ mxc_hdmi_phy_init(hdmi);
++
++ /* HDMI Initialization Step B.3 */
++ mxc_hdmi_enable_video_path(hdmi);
++
++ /* not for DVI mode */
++ if (hdmi->hdmi_data.video_mode.mDVI)
++ dev_dbg(&hdmi->pdev->dev, "%s DVI mode\n", __func__);
++ else {
++ dev_dbg(&hdmi->pdev->dev, "%s CEA mode\n", __func__);
++
++ /* HDMI Initialization Step E - Configure audio */
++ hdmi_enable_audio_clk(hdmi);
++
++ /* HDMI Initialization Step F - Configure AVI InfoFrame */
++ hdmi_config_AVI(hdmi);
++ }
++
++ hdmi_video_packetize(hdmi);
++ hdmi_video_csc(hdmi);
++ hdmi_video_sample(hdmi);
++
++ mxc_hdmi_clear_overflow(hdmi);
++
++ if (hdmi->cable_plugin && !hdmi->hdmi_data.video_mode.mDVI)
++ hdmi_enable_overflow_interrupts();
++
++ dev_dbg(&hdmi->pdev->dev, "%s exit\n\n", __func__);
++
++}
++
++/* Wait until we are registered to enable interrupts */
++static void mxc_hdmi_fb_registered(struct mxc_hdmi *hdmi)
++{
++ unsigned long flags;
++
++ if (hdmi->fb_reg)
++ return;
++
++ spin_lock_irqsave(&hdmi->irq_lock, flags);
++
++ dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
++
++ hdmi_writeb(HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
++ HDMI_PHY_I2CM_INT_ADDR);
++
++ hdmi_writeb(HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
++ HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
++ HDMI_PHY_I2CM_CTLINT_ADDR);
++
++ /* enable cable hot plug irq */
++ hdmi_writeb(~hdmi->plug_mask, HDMI_PHY_MASK0);
++
++ /* Clear Hotplug interrupts */
++ hdmi_writeb(hdmi->plug_event, HDMI_IH_PHY_STAT0);
++
++ /* Unmute interrupts */
++ hdmi_writeb(~hdmi->plug_event, HDMI_IH_MUTE_PHY_STAT0);
++
++ hdmi->fb_reg = true;
++
++ spin_unlock_irqrestore(&hdmi->irq_lock, flags);
++
++}
++
++static int mxc_hdmi_fb_event(struct notifier_block *nb,
++ unsigned long val, void *v)
++{
++ struct fb_event *event = v;
++ struct mxc_hdmi *hdmi = container_of(nb, struct mxc_hdmi, nb);
++
++ if (strcmp(event->info->fix.id, hdmi->fbi->fix.id))
++ return 0;
++
++ switch (val) {
++ case FB_EVENT_FB_REGISTERED:
++ dev_dbg(&hdmi->pdev->dev, "event=FB_EVENT_FB_REGISTERED\n");
++ mxc_hdmi_fb_registered(hdmi);
++ hdmi_set_registered(1);
++ break;
++
++ case FB_EVENT_FB_UNREGISTERED:
++ dev_dbg(&hdmi->pdev->dev, "event=FB_EVENT_FB_UNREGISTERED\n");
++ hdmi->fb_reg = false;
++ hdmi_set_registered(0);
++ break;
++
++ case FB_EVENT_MODE_CHANGE:
++ dev_dbg(&hdmi->pdev->dev, "event=FB_EVENT_MODE_CHANGE\n");
++ if (hdmi->fb_reg)
++ mxc_hdmi_setup(hdmi, val);
++ break;
++
++ case FB_EVENT_BLANK:
++ if ((*((int *)event->data) == FB_BLANK_UNBLANK) &&
++ (*((int *)event->data) != hdmi->blank)) {
++ dev_dbg(&hdmi->pdev->dev,
++ "event=FB_EVENT_BLANK - UNBLANK\n");
++
++ hdmi->blank = *((int *)event->data);
++
++ /* Re-enable HPD interrupts */
++ val = hdmi_readb(HDMI_PHY_MASK0);
++ val &= ~hdmi->plug_mask;
++ hdmi_writeb(val, HDMI_PHY_MASK0);
++
++ /* Unmute interrupts */
++ hdmi_writeb(~hdmi->plug_event, HDMI_IH_MUTE_PHY_STAT0);
++
++ if (hdmi->fb_reg && hdmi->cable_plugin)
++ mxc_hdmi_setup(hdmi, val);
++ hdmi_set_blank_state(1);
++
++ } else if (*((int *)event->data) != hdmi->blank) {
++ dev_dbg(&hdmi->pdev->dev,
++ "event=FB_EVENT_BLANK - BLANK\n");
++ hdmi_set_blank_state(0);
++ mxc_hdmi_abort_stream();
++
++ mxc_hdmi_phy_disable(hdmi);
++
++ if(hdmi->plug_mask == HDMI_DVI_STAT) {
++ u8 val;
++ pr_info("In DVI Mode disable interrupts\n");
++ val = hdmi_readb(HDMI_IH_MUTE_PHY_STAT0);
++ val |= hdmi->plug_event;
++ hdmi_writeb(val, HDMI_IH_MUTE_PHY_STAT0);
++
++ val = hdmi_readb(HDMI_PHY_MASK0);
++ val |= hdmi->plug_mask;
++ hdmi_writeb(val, HDMI_PHY_MASK0);
++
++ hdmi_set_dvi_mode(1);
++ }
++
++ hdmi->blank = *((int *)event->data);
++ } else
++ dev_dbg(&hdmi->pdev->dev,
++ "FB BLANK state no changed!\n");
++
++ break;
++
++ case FB_EVENT_SUSPEND:
++ dev_dbg(&hdmi->pdev->dev,
++ "event=FB_EVENT_SUSPEND\n");
++
++ if (hdmi->blank == FB_BLANK_UNBLANK) {
++ mxc_hdmi_phy_disable(hdmi);
++ clk_disable(hdmi->hdmi_iahb_clk);
++ clk_disable(hdmi->hdmi_isfr_clk);
++ }
++ break;
++
++ case FB_EVENT_RESUME:
++ dev_dbg(&hdmi->pdev->dev,
++ "event=FB_EVENT_RESUME\n");
++
++ if (hdmi->blank == FB_BLANK_UNBLANK) {
++ clk_enable(hdmi->hdmi_iahb_clk);
++ clk_enable(hdmi->hdmi_isfr_clk);
++ mxc_hdmi_phy_init(hdmi);
++ }
++ break;
++ default:
++ break;
++ }
++
++ return 0;
++}
++
++static void hdmi_init_route(struct mxc_hdmi *hdmi)
++{
++ uint32_t hdmi_mux_setting, reg;
++ int ipu_id, disp_id;
++
++ ipu_id = mxc_hdmi_ipu_id;
++ disp_id = mxc_hdmi_disp_id;
++
++ if ((ipu_id > 1) || (ipu_id < 0)) {
++ pr_err("Invalid IPU select for HDMI: %d. Set to 0\n", ipu_id);
++ ipu_id = 0;
++ }
++
++ if ((disp_id > 1) || (disp_id < 0)) {
++ pr_err("Invalid DI select for HDMI: %d. Set to 0\n", disp_id);
++ disp_id = 0;
++ }
++
++ reg = readl(hdmi->gpr_hdmi_base);
++
++ /* Configure the connection between IPU1/2 and HDMI */
++ hdmi_mux_setting = 2*ipu_id + disp_id;
++
++ /* GPR3, bits 2-3 = HDMI_MUX_CTL */
++ reg &= ~0xd;
++ reg |= hdmi_mux_setting << 2;
++
++ writel(reg, hdmi->gpr_hdmi_base);
++
++ /* Set HDMI event as SDMA event2 for HDMI audio */
++ reg = readl(hdmi->gpr_sdma_base);
++ reg |= 0x1;
++ writel(reg, hdmi->gpr_sdma_base);
++}
++
++static void hdmi_hdcp_get_property(struct platform_device *pdev)
++{
++ struct device_node *np = pdev->dev.of_node;
++
++ /* Check hdcp enable by dts.*/
++ hdcp_init = of_property_read_bool(np, "fsl,hdcp");
++ if (hdcp_init)
++ dev_dbg(&pdev->dev, "hdcp enable\n");
++ else
++ dev_dbg(&pdev->dev, "hdcp disable\n");
++}
++
++static void hdmi_get_of_property(struct mxc_hdmi *hdmi)
++{
++ struct platform_device *pdev = hdmi->pdev;
++ struct device_node *np = pdev->dev.of_node;
++ const struct of_device_id *of_id =
++ of_match_device(imx_hdmi_dt_ids, &pdev->dev);
++ int ret;
++ u32 phy_reg_vlev = 0, phy_reg_cksymtx = 0;
++
++ if (of_id) {
++ pdev->id_entry = of_id->data;
++ hdmi->cpu_type = pdev->id_entry->driver_data;
++ }
++
++ /* HDMI PHY register vlev and cksymtx preperty is optional.
++ * It is for specific board to pass HCT electrical part.
++ * Default value will been setting in HDMI PHY config function
++ * if it is not define in device tree.
++ */
++ ret = of_property_read_u32(np, "fsl,phy_reg_vlev", &phy_reg_vlev);
++ if (ret)
++ dev_dbg(&pdev->dev, "No board specific HDMI PHY vlev\n");
++
++ ret = of_property_read_u32(np, "fsl,phy_reg_cksymtx", &phy_reg_cksymtx);
++ if (ret)
++ dev_dbg(&pdev->dev, "No board specific HDMI PHY cksymtx\n");
++
++ /* Specific phy config */
++ hdmi->phy_config.reg_cksymtx = phy_reg_cksymtx;
++ hdmi->phy_config.reg_vlev = phy_reg_vlev;
++
++}
++
++/* HDMI Initialization Step A */
++static int mxc_hdmi_disp_init(struct mxc_dispdrv_handle *disp,
++ struct mxc_dispdrv_setting *setting)
++{
++ int ret = 0;
++ u32 i;
++ const struct fb_videomode *mode;
++ struct fb_videomode m;
++ struct mxc_hdmi *hdmi = mxc_dispdrv_getdata(disp);
++ int irq = platform_get_irq(hdmi->pdev, 0);
++
++ dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
++
++ /* Check hdmi disp init once */
++ if (hdmi_inited) {
++ dev_err(&hdmi->pdev->dev,
++ "Error only one HDMI output support now!\n");
++ return -1;
++ }
++
++ hdmi_get_of_property(hdmi);
++
++ if (irq < 0)
++ return -ENODEV;
++
++ /* Setting HDMI default to blank state */
++ hdmi->blank = FB_BLANK_POWERDOWN;
++
++ setting->dev_id = mxc_hdmi_ipu_id;
++ setting->disp_id = mxc_hdmi_disp_id;
++ setting->if_fmt = IPU_PIX_FMT_RGB24;
++
++ hdmi->dft_mode_str = setting->dft_mode_str;
++ hdmi->default_bpp = setting->default_bpp;
++ dev_dbg(&hdmi->pdev->dev, "%s - default mode %s bpp=%d\n",
++ __func__, hdmi->dft_mode_str, hdmi->default_bpp);
++
++ hdmi->fbi = setting->fbi;
++
++ hdmi_init_route(hdmi);
++
++ hdmi->hdmi_isfr_clk = clk_get(&hdmi->pdev->dev, "hdmi_isfr");
++ if (IS_ERR(hdmi->hdmi_isfr_clk)) {
++ ret = PTR_ERR(hdmi->hdmi_isfr_clk);
++ dev_err(&hdmi->pdev->dev,
++ "Unable to get HDMI clk: %d\n", ret);
++ goto egetclk1;
++ }
++
++ ret = clk_prepare_enable(hdmi->hdmi_isfr_clk);
++ if (ret < 0) {
++ dev_err(&hdmi->pdev->dev,
++ "Cannot enable HDMI isfr clock: %d\n", ret);
++ goto erate1;
++ }
++
++ hdmi->hdmi_iahb_clk = clk_get(&hdmi->pdev->dev, "hdmi_iahb");
++ if (IS_ERR(hdmi->hdmi_iahb_clk)) {
++ ret = PTR_ERR(hdmi->hdmi_iahb_clk);
++ dev_err(&hdmi->pdev->dev,
++ "Unable to get HDMI clk: %d\n", ret);
++ goto egetclk2;
++ }
++
++ ret = clk_prepare_enable(hdmi->hdmi_iahb_clk);
++ if (ret < 0) {
++ dev_err(&hdmi->pdev->dev,
++ "Cannot enable HDMI iahb clock: %d\n", ret);
++ goto erate2;
++ }
++
++ dev_dbg(&hdmi->pdev->dev, "Enabled HDMI clocks\n");
++
++ /* Init DDC pins for HDCP */
++ if (hdcp_init) {
++ hdmi->pinctrl = devm_pinctrl_get_select_default(&hdmi->pdev->dev);
++ if (IS_ERR(hdmi->pinctrl)) {
++ dev_err(&hdmi->pdev->dev, "can't get/select DDC pinctrl\n");
++ goto erate2;
++ }
++ }
++
++ /* Product and revision IDs */
++ dev_info(&hdmi->pdev->dev,
++ "Detected HDMI controller 0x%x:0x%x:0x%x:0x%x\n",
++ hdmi_readb(HDMI_DESIGN_ID),
++ hdmi_readb(HDMI_REVISION_ID),
++ hdmi_readb(HDMI_PRODUCT_ID0),
++ hdmi_readb(HDMI_PRODUCT_ID1));
++
++ /* To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
++ * N and cts values before enabling phy */
++ hdmi_init_clk_regenerator();
++
++ INIT_LIST_HEAD(&hdmi->fbi->modelist);
++
++ spin_lock_init(&hdmi->irq_lock);
++
++ /* Set the default mode and modelist when disp init. */
++ fb_find_mode(&hdmi->fbi->var, hdmi->fbi,
++ hdmi->dft_mode_str, /*NULL, 0, NULL,*/mxc_cea_mode, ARRAY_SIZE(mxc_cea_mode), NULL,
++ hdmi->default_bpp);
++
++ console_lock();
++
++ fb_destroy_modelist(&hdmi->fbi->modelist);
++
++ /*Add all no interlaced CEA mode to default modelist */
++ for (i = 0; i < ARRAY_SIZE(mxc_cea_mode); i++) {
++ mode = &mxc_cea_mode[i];
++ if (mode->xres != 0)
++ fb_add_videomode(mode, &hdmi->fbi->modelist);
++ }
++
++ console_unlock();
++
++ /* Find a nearest mode in default modelist */
++ fb_var_to_videomode(&m, &hdmi->fbi->var);
++ dump_fb_videomode(&m);
++ hdmi->dft_mode_set = false;
++ /* Save default video mode */
++ memcpy(&hdmi->default_mode, &m, sizeof(struct fb_videomode));
++
++ mode = mxc_fb_find_nearest_mode(&m, &hdmi->fbi->modelist);
++ if (!mode) {
++ pr_err("%s: could not find mode in modelist\n", __func__);
++ return -1;
++ }
++
++ fb_videomode_to_var(&hdmi->fbi->var, mode);
++
++ /* update fbi mode */
++ hdmi->fbi->mode = (struct fb_videomode *)mode;
++
++ /* Default setting HDMI working in HDMI mode*/
++ hdmi->edid_cfg.hdmi_cap = true;
++
++ hdmi->plug_event = HDMI_DVI_IH_STAT;
++ hdmi->plug_mask = HDMI_DVI_STAT;
++
++ setup_timer(&hdmi->jitter_timer, hotplug_work_launch, (unsigned long)hdmi);
++ INIT_WORK(&hdmi->hotplug_work, hotplug_worker);
++ INIT_DELAYED_WORK(&hdmi->hdcp_hdp_work, hdcp_hdp_worker);
++
++ /* Configure registers related to HDMI interrupt
++ * generation before registering IRQ. */
++ hdmi_writeb(hdmi->plug_mask, HDMI_PHY_POL0);
++
++ /* Clear Hotplug interrupts */
++ hdmi_writeb(hdmi->plug_event, HDMI_IH_PHY_STAT0);
++
++ hdmi->nb.notifier_call = mxc_hdmi_fb_event;
++ ret = fb_register_client(&hdmi->nb);
++ if (ret < 0)
++ goto efbclient;
++
++ memset(&hdmi->hdmi_data, 0, sizeof(struct hdmi_data_info));
++
++ /* Default HDMI working in RGB mode */
++ hdmi->hdmi_data.rgb_out_enable = true;
++
++ if (!strcasecmp(rgb_quant_range, "limited")) {
++ hdmi->hdmi_data.rgb_quant_range = HDMI_FC_AVICONF2_RGB_QUANT_LIMITED_RANGE;
++ } else if (!strcasecmp(rgb_quant_range, "full")) {
++ hdmi->hdmi_data.rgb_quant_range = HDMI_FC_AVICONF2_RGB_QUANT_FULL_RANGE;
++ } else {
++ hdmi->hdmi_data.rgb_quant_range = HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT;
++ }
++
++ if (!strcasecmp(enable_3d, "disable")) {
++ hdmi->hdmi_data.enable_3d = 0;
++ } else if (!strcasecmp(enable_3d, "0")) {
++ hdmi->hdmi_data.enable_3d = 0;
++ } else {
++ hdmi->hdmi_data.enable_3d = 1;
++ }
++
++ if (!strcasecmp(enable_fract, "disable")) {
++ hdmi->hdmi_data.enable_fract = 0;
++ } else if (!strcasecmp(enable_fract, "0")) {
++ hdmi->hdmi_data.enable_fract = 0;
++ } else {
++ hdmi->hdmi_data.enable_fract = 1;
++ }
++
++ ret = devm_request_irq(&hdmi->pdev->dev, irq, mxc_hdmi_hotplug, IRQF_SHARED,
++ dev_name(&hdmi->pdev->dev), hdmi);
++ if (ret < 0) {
++ dev_err(&hdmi->pdev->dev,
++ "Unable to request irq: %d\n", ret);
++ goto ereqirq;
++ }
++
++ ret = device_create_file(&hdmi->pdev->dev, &dev_attr_fb_name);
++ if (ret < 0)
++ dev_warn(&hdmi->pdev->dev,
++ "cound not create sys node for fb name\n");
++ ret = device_create_file(&hdmi->pdev->dev, &dev_attr_cable_state);
++ if (ret < 0)
++ dev_warn(&hdmi->pdev->dev,
++ "cound not create sys node for cable state\n");
++ ret = device_create_file(&hdmi->pdev->dev, &dev_attr_edid);
++ if (ret < 0)
++ dev_warn(&hdmi->pdev->dev,
++ "cound not create sys node for edid\n");
++
++ ret = device_create_file(&hdmi->pdev->dev, &dev_attr_rgb_out_enable);
++ if (ret < 0)
++ dev_warn(&hdmi->pdev->dev,
++ "cound not create sys node for rgb out enable\n");
++
++ ret = device_create_file(&hdmi->pdev->dev, &dev_attr_rgb_quant_range);
++ if (ret < 0)
++ dev_warn(&hdmi->pdev->dev,
++ "cound not create sys node for rgb quant range\n");
++
++ ret = device_create_file(&hdmi->pdev->dev, &dev_attr_enable_3d);
++ if (ret < 0)
++ dev_warn(&hdmi->pdev->dev,
++ "cound not create sys node for enable_3d\n");
++
++ ret = device_create_file(&hdmi->pdev->dev, &dev_attr_enable_fract);
++ if (ret < 0)
++ dev_warn(&hdmi->pdev->dev,
++ "cound not create sys node for enable_fract\n");
++
++ ret = device_create_file(&hdmi->pdev->dev, &dev_attr_hdcp_enable);
++ if (ret < 0)
++ dev_warn(&hdmi->pdev->dev,
++ "cound not create sys node for hdcp enable\n");
++
++ dev_dbg(&hdmi->pdev->dev, "%s exit\n", __func__);
++
++ hdmi_inited = true;
++
++ return ret;
++
++efbclient:
++ free_irq(irq, hdmi);
++ereqirq:
++ clk_disable_unprepare(hdmi->hdmi_iahb_clk);
++erate2:
++ clk_put(hdmi->hdmi_iahb_clk);
++egetclk2:
++ clk_disable_unprepare(hdmi->hdmi_isfr_clk);
++erate1:
++ clk_put(hdmi->hdmi_isfr_clk);
++egetclk1:
++ dev_dbg(&hdmi->pdev->dev, "%s error exit\n", __func__);
++
++ return ret;
++}
++
++static void mxc_hdmi_disp_deinit(struct mxc_dispdrv_handle *disp)
++{
++ struct mxc_hdmi *hdmi = mxc_dispdrv_getdata(disp);
++
++ dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
++
++ fb_unregister_client(&hdmi->nb);
++
++ clk_disable_unprepare(hdmi->hdmi_isfr_clk);
++ clk_put(hdmi->hdmi_isfr_clk);
++ clk_disable_unprepare(hdmi->hdmi_iahb_clk);
++ clk_put(hdmi->hdmi_iahb_clk);
++
++ platform_device_unregister(hdmi->pdev);
++
++ hdmi_inited = false;
++}
++
++static struct mxc_dispdrv_driver mxc_hdmi_drv = {
++ .name = DISPDRV_HDMI,
++ .init = mxc_hdmi_disp_init,
++ .deinit = mxc_hdmi_disp_deinit,
++ .enable = mxc_hdmi_power_on,
++ .disable = mxc_hdmi_power_off,
++};
++
++
++static int mxc_hdmi_open(struct inode *inode, struct file *file)
++{
++ return 0;
++}
++
++static long mxc_hdmi_ioctl(struct file *file,
++ unsigned int cmd, unsigned long arg)
++{
++ int __user *argp = (void __user *)arg;
++ int ret = 0;
++
++ switch (cmd) {
++ case HDMI_IOC_GET_RESOURCE:
++ ret = copy_to_user(argp, &g_hdmi->hdmi_data,
++ sizeof(g_hdmi->hdmi_data)) ? -EFAULT : 0;
++ break;
++ case HDMI_IOC_GET_CPU_TYPE:
++ *argp = g_hdmi->cpu_type;
++ break;
++ default:
++ pr_debug("Unsupport cmd %d\n", cmd);
++ break;
++ }
++ return ret;
++}
++
++static int mxc_hdmi_release(struct inode *inode, struct file *file)
++{
++ return 0;
++}
++
++static const struct file_operations mxc_hdmi_fops = {
++ .owner = THIS_MODULE,
++ .open = mxc_hdmi_open,
++ .release = mxc_hdmi_release,
++ .unlocked_ioctl = mxc_hdmi_ioctl,
++};
++
++
++static int mxc_hdmi_probe(struct platform_device *pdev)
++{
++ struct mxc_hdmi *hdmi;
++ struct device *temp_class;
++ struct resource *res;
++ int ret = 0;
++
++ /* Check I2C driver is loaded and available
++ * check hdcp function is enable by dts */
++ hdmi_hdcp_get_property(pdev);
++ if (!hdmi_i2c && !hdcp_init)
++ return -ENODEV;
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (!res)
++ return -ENOENT;
++
++ hdmi = devm_kzalloc(&pdev->dev,
++ sizeof(struct mxc_hdmi),
++ GFP_KERNEL);
++ if (!hdmi) {
++ dev_err(&pdev->dev, "Cannot allocate device data\n");
++ ret = -ENOMEM;
++ goto ealloc;
++ }
++ g_hdmi = hdmi;
++
++ hdmi_major = register_chrdev(hdmi_major, "mxc_hdmi", &mxc_hdmi_fops);
++ if (hdmi_major < 0) {
++ printk(KERN_ERR "HDMI: unable to get a major for HDMI\n");
++ ret = -EBUSY;
++ goto ealloc;
++ }
++
++ hdmi_class = class_create(THIS_MODULE, "mxc_hdmi");
++ if (IS_ERR(hdmi_class)) {
++ ret = PTR_ERR(hdmi_class);
++ goto err_out_chrdev;
++ }
++
++ temp_class = device_create(hdmi_class, NULL, MKDEV(hdmi_major, 0),
++ NULL, "mxc_hdmi");
++ if (IS_ERR(temp_class)) {
++ ret = PTR_ERR(temp_class);
++ goto err_out_class;
++ }
++
++ hdmi->pdev = pdev;
++
++ hdmi->core_pdev = platform_device_alloc("mxc_hdmi_core", -1);
++ if (!hdmi->core_pdev) {
++ pr_err("%s failed platform_device_alloc for hdmi core\n",
++ __func__);
++ ret = -ENOMEM;
++ goto ecore;
++ }
++
++ hdmi->gpr_base = ioremap(res->start, resource_size(res));
++ if (!hdmi->gpr_base) {
++ dev_err(&pdev->dev, "ioremap failed\n");
++ ret = -ENOMEM;
++ goto eiomap;
++ }
++
++ hdmi->gpr_hdmi_base = hdmi->gpr_base + 3;
++ hdmi->gpr_sdma_base = hdmi->gpr_base;
++
++ hdmi_inited = false;
++
++ hdmi->disp_mxc_hdmi = mxc_dispdrv_register(&mxc_hdmi_drv);
++ if (IS_ERR(hdmi->disp_mxc_hdmi)) {
++ dev_err(&pdev->dev, "Failed to register dispdrv - 0x%x\n",
++ (int)hdmi->disp_mxc_hdmi);
++ ret = (int)hdmi->disp_mxc_hdmi;
++ goto edispdrv;
++ }
++ mxc_dispdrv_setdata(hdmi->disp_mxc_hdmi, hdmi);
++
++ platform_set_drvdata(pdev, hdmi);
++
++ return 0;
++edispdrv:
++ iounmap(hdmi->gpr_base);
++eiomap:
++ platform_device_put(hdmi->core_pdev);
++ecore:
++ kfree(hdmi);
++err_out_class:
++ device_destroy(hdmi_class, MKDEV(hdmi_major, 0));
++ class_destroy(hdmi_class);
++err_out_chrdev:
++ unregister_chrdev(hdmi_major, "mxc_hdmi");
++ealloc:
++ return ret;
++}
++
++static int mxc_hdmi_remove(struct platform_device *pdev)
++{
++ struct mxc_hdmi *hdmi = platform_get_drvdata(pdev);
++ int irq = platform_get_irq(pdev, 0);
++
++ fb_unregister_client(&hdmi->nb);
++
++ mxc_dispdrv_puthandle(hdmi->disp_mxc_hdmi);
++ mxc_dispdrv_unregister(hdmi->disp_mxc_hdmi);
++ iounmap(hdmi->gpr_base);
++ /* No new work will be scheduled, wait for running ISR */
++ free_irq(irq, hdmi);
++ kfree(hdmi);
++ g_hdmi = NULL;
++
++ return 0;
++}
++
++static struct platform_driver mxc_hdmi_driver = {
++ .probe = mxc_hdmi_probe,
++ .remove = mxc_hdmi_remove,
++ .driver = {
++ .name = "mxc_hdmi",
++ .of_match_table = imx_hdmi_dt_ids,
++ .owner = THIS_MODULE,
++ },
++};
++
++static int __init mxc_hdmi_init(void)
++{
++ return platform_driver_register(&mxc_hdmi_driver);
++}
++module_init(mxc_hdmi_init);
++
++static void __exit mxc_hdmi_exit(void)
++{
++ if (hdmi_major > 0) {
++ device_destroy(hdmi_class, MKDEV(hdmi_major, 0));
++ class_destroy(hdmi_class);
++ unregister_chrdev(hdmi_major, "mxc_hdmi");
++ hdmi_major = 0;
++ }
++
++ platform_driver_unregister(&mxc_hdmi_driver);
++}
++module_exit(mxc_hdmi_exit);
++
++static int mxc_hdmi_i2c_probe(struct i2c_client *client,
++ const struct i2c_device_id *id)
++{
++ if (!i2c_check_functionality(client->adapter,
++ I2C_FUNC_SMBUS_BYTE | I2C_FUNC_I2C))
++ return -ENODEV;
++
++ hdmi_i2c = client;
++
++ return 0;
++}
++
++static int mxc_hdmi_i2c_remove(struct i2c_client *client)
++{
++ hdmi_i2c = NULL;
++ return 0;
++}
++
++static const struct of_device_id imx_hdmi_i2c_match[] = {
++ { .compatible = "fsl,imx6-hdmi-i2c", },
++ { /* sentinel */ }
++};
++
++static const struct i2c_device_id mxc_hdmi_i2c_id[] = {
++ { "mxc_hdmi_i2c", 0 },
++ {},
++};
++MODULE_DEVICE_TABLE(i2c, mxc_hdmi_i2c_id);
++
++static struct i2c_driver mxc_hdmi_i2c_driver = {
++ .driver = {
++ .name = "mxc_hdmi_i2c",
++ .of_match_table = imx_hdmi_i2c_match,
++ },
++ .probe = mxc_hdmi_i2c_probe,
++ .remove = mxc_hdmi_i2c_remove,
++ .id_table = mxc_hdmi_i2c_id,
++};
++
++static int __init mxc_hdmi_i2c_init(void)
++{
++ return i2c_add_driver(&mxc_hdmi_i2c_driver);
++}
++
++static void __exit mxc_hdmi_i2c_exit(void)
++{
++ i2c_del_driver(&mxc_hdmi_i2c_driver);
++}
++
++subsys_initcall(mxc_hdmi_i2c_init);
++module_exit(mxc_hdmi_i2c_exit);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+diff -Nur linux-4.1.3/drivers/video/mxc/mxc_ipuv3_fb.c linux-xbian-imx6/drivers/video/mxc/mxc_ipuv3_fb.c
+--- linux-4.1.3/drivers/video/mxc/mxc_ipuv3_fb.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/video/mxc/mxc_ipuv3_fb.c 2015-07-27 23:13:08.753749907 +0200
+@@ -0,0 +1,2579 @@
++/*
++ * Copyright 2004-2014 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*!
++ * @defgroup Framebuffer Framebuffer Driver for SDC and ADC.
++ */
++
++/*!
++ * @file mxcfb.c
++ *
++ * @brief MXC Frame buffer driver for SDC
++ *
++ * @ingroup Framebuffer
++ */
++
++/*!
++ * Include files
++ */
++#include <linux/clk.h>
++#include <linux/console.h>
++#include <linux/delay.h>
++#include <linux/dma-mapping.h>
++#include <linux/errno.h>
++#include <linux/fb.h>
++#include <linux/fsl_devices.h>
++#include <linux/init.h>
++#include <linux/interrupt.h>
++#include <linux/io.h>
++#include <linux/ioport.h>
++#include <linux/ipu.h>
++#include <linux/ipu-v3.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/mxcfb.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++#include <linux/sched.h>
++#include <linux/slab.h>
++#include <linux/string.h>
++#include <linux/uaccess.h>
++
++#include "mxc_dispdrv.h"
++
++/*
++ * Driver name
++ */
++#define MXCFB_NAME "mxc_sdc_fb"
++
++/* Display port number */
++#define MXCFB_PORT_NUM 2
++/*!
++ * Structure containing the MXC specific framebuffer information.
++ */
++struct mxcfb_info {
++ int default_bpp;
++ int cur_blank;
++ int next_blank;
++ ipu_channel_t ipu_ch;
++ int ipu_id;
++ int ipu_di;
++ u32 ipu_di_pix_fmt;
++ bool ipu_int_clk;
++ bool overlay;
++ bool alpha_chan_en;
++ bool late_init;
++ bool first_set_par;
++ dma_addr_t alpha_phy_addr0;
++ dma_addr_t alpha_phy_addr1;
++ void *alpha_virt_addr0;
++ void *alpha_virt_addr1;
++ uint32_t alpha_mem_len;
++ uint32_t ipu_ch_irq;
++ uint32_t ipu_ch_nf_irq;
++ uint32_t ipu_alp_ch_irq;
++ uint32_t cur_ipu_buf;
++ uint32_t cur_ipu_alpha_buf;
++
++ u32 pseudo_palette[16];
++
++ bool mode_found;
++ struct completion flip_complete;
++ struct completion alpha_flip_complete;
++ struct completion vsync_complete;
++
++ void *ipu;
++ struct fb_info *ovfbi;
++
++ struct mxc_dispdrv_handle *dispdrv;
++
++ struct fb_var_screeninfo cur_var;
++};
++
++struct mxcfb_pfmt {
++ u32 fb_pix_fmt;
++ int bpp;
++ struct fb_bitfield red;
++ struct fb_bitfield green;
++ struct fb_bitfield blue;
++ struct fb_bitfield transp;
++};
++
++static const struct mxcfb_pfmt mxcfb_pfmts[] = {
++ /* pixel bpp red green blue transp */
++ {IPU_PIX_FMT_RGB565, 16, {11, 5, 0}, { 5, 6, 0}, { 0, 5, 0}, { 0, 0, 0} },
++ {IPU_PIX_FMT_RGB24, 24, { 0, 8, 0}, { 8, 8, 0}, {16, 8, 0}, { 0, 0, 0} },
++ {IPU_PIX_FMT_BGR24, 24, {16, 8, 0}, { 8, 8, 0}, { 0, 8, 0}, { 0, 0, 0} },
++ {IPU_PIX_FMT_RGB32, 32, { 0, 8, 0}, { 8, 8, 0}, {16, 8, 0}, {24, 8, 0} },
++ {IPU_PIX_FMT_BGR32, 32, {16, 8, 0}, { 8, 8, 0}, { 0, 8, 0}, {24, 8, 0} },
++ {IPU_PIX_FMT_ABGR32, 32, {24, 8, 0}, {16, 8, 0}, { 8, 8, 0}, { 0, 8, 0} },
++};
++
++struct mxcfb_alloc_list {
++ struct list_head list;
++ dma_addr_t phy_addr;
++ void *cpu_addr;
++ u32 size;
++};
++
++enum {
++ BOTH_ON,
++ SRC_ON,
++ TGT_ON,
++ BOTH_OFF
++};
++
++static bool g_dp_in_use[2];
++LIST_HEAD(fb_alloc_list);
++
++/* Return default standard(RGB) pixel format */
++static uint32_t bpp_to_pixfmt(int bpp)
++{
++ uint32_t pixfmt = 0;
++
++ switch (bpp) {
++ case 24:
++ pixfmt = IPU_PIX_FMT_BGR24;
++ break;
++ case 32:
++ pixfmt = IPU_PIX_FMT_BGR32;
++ break;
++ case 16:
++ pixfmt = IPU_PIX_FMT_RGB565;
++ break;
++ }
++ return pixfmt;
++}
++
++static inline int bitfield_is_equal(struct fb_bitfield f1,
++ struct fb_bitfield f2)
++{
++ return !memcmp(&f1, &f2, sizeof(f1));
++}
++
++static int pixfmt_to_var(uint32_t pixfmt, struct fb_var_screeninfo *var)
++{
++ int i, ret = -1;
++
++ for (i = 0; i < ARRAY_SIZE(mxcfb_pfmts); i++) {
++ if (pixfmt == mxcfb_pfmts[i].fb_pix_fmt) {
++ var->red = mxcfb_pfmts[i].red;
++ var->green = mxcfb_pfmts[i].green;
++ var->blue = mxcfb_pfmts[i].blue;
++ var->transp = mxcfb_pfmts[i].transp;
++ var->bits_per_pixel = mxcfb_pfmts[i].bpp;
++ ret = 0;
++ break;
++ }
++ }
++ return ret;
++}
++
++static int bpp_to_var(int bpp, struct fb_var_screeninfo *var)
++{
++ uint32_t pixfmt = 0;
++
++ pixfmt = bpp_to_pixfmt(bpp);
++ if (pixfmt)
++ return pixfmt_to_var(pixfmt, var);
++ else
++ return -1;
++}
++
++static int check_var_pixfmt(struct fb_var_screeninfo *var)
++{
++ int i, ret = -1;
++
++ for (i = 0; i < ARRAY_SIZE(mxcfb_pfmts); i++) {
++ if (bitfield_is_equal(var->red, mxcfb_pfmts[i].red) &&
++ bitfield_is_equal(var->green, mxcfb_pfmts[i].green) &&
++ bitfield_is_equal(var->blue, mxcfb_pfmts[i].blue) &&
++ bitfield_is_equal(var->transp, mxcfb_pfmts[i].transp) &&
++ var->bits_per_pixel == mxcfb_pfmts[i].bpp) {
++ ret = 0;
++ break;
++ }
++ }
++ return ret;
++}
++
++static uint32_t fbi_to_pixfmt(struct fb_info *fbi)
++{
++ int i;
++ uint32_t pixfmt = 0;
++
++ if (fbi->var.nonstd)
++ return fbi->var.nonstd;
++
++ for (i = 0; i < ARRAY_SIZE(mxcfb_pfmts); i++) {
++ if (bitfield_is_equal(fbi->var.red, mxcfb_pfmts[i].red) &&
++ bitfield_is_equal(fbi->var.green, mxcfb_pfmts[i].green) &&
++ bitfield_is_equal(fbi->var.blue, mxcfb_pfmts[i].blue) &&
++ bitfield_is_equal(fbi->var.transp, mxcfb_pfmts[i].transp)) {
++ pixfmt = mxcfb_pfmts[i].fb_pix_fmt;
++ break;
++ }
++ }
++
++ if (pixfmt == 0)
++ dev_err(fbi->device, "cannot get pixel format\n");
++
++ return pixfmt;
++}
++
++static struct fb_info *found_registered_fb(ipu_channel_t ipu_ch, int ipu_id)
++{
++ int i;
++ struct mxcfb_info *mxc_fbi;
++ struct fb_info *fbi = NULL;
++
++ for (i = 0; i < num_registered_fb; i++) {
++ mxc_fbi =
++ ((struct mxcfb_info *)(registered_fb[i]->par));
++
++ if ((mxc_fbi->ipu_ch == ipu_ch) &&
++ (mxc_fbi->ipu_id == ipu_id)) {
++ fbi = registered_fb[i];
++ break;
++ }
++ }
++ return fbi;
++}
++
++static irqreturn_t mxcfb_irq_handler(int irq, void *dev_id);
++static irqreturn_t mxcfb_nf_irq_handler(int irq, void *dev_id);
++static int mxcfb_blank(int blank, struct fb_info *info);
++static int mxcfb_map_video_memory(struct fb_info *fbi);
++static int mxcfb_unmap_video_memory(struct fb_info *fbi);
++
++/*
++ * Set fixed framebuffer parameters based on variable settings.
++ *
++ * @param info framebuffer information pointer
++ */
++static int mxcfb_set_fix(struct fb_info *info)
++{
++ struct fb_fix_screeninfo *fix = &info->fix;
++ struct fb_var_screeninfo *var = &info->var;
++
++ fix->line_length = var->xres_virtual * var->bits_per_pixel / 8;
++
++ fix->type = FB_TYPE_PACKED_PIXELS;
++ fix->accel = FB_ACCEL_NONE;
++ fix->visual = FB_VISUAL_TRUECOLOR;
++ fix->xpanstep = 1;
++ fix->ywrapstep = 1;
++ fix->ypanstep = 1;
++
++ return 0;
++}
++
++static int _setup_disp_channel1(struct fb_info *fbi)
++{
++ ipu_channel_params_t params;
++ struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par;
++
++ memset(&params, 0, sizeof(params));
++
++ if (mxc_fbi->ipu_ch == MEM_DC_SYNC) {
++ params.mem_dc_sync.di = mxc_fbi->ipu_di;
++ if (fbi->var.vmode & FB_VMODE_INTERLACED)
++ params.mem_dc_sync.interlaced = true;
++ params.mem_dc_sync.out_pixel_fmt = mxc_fbi->ipu_di_pix_fmt;
++ params.mem_dc_sync.in_pixel_fmt = fbi_to_pixfmt(fbi);
++ } else {
++ params.mem_dp_bg_sync.di = mxc_fbi->ipu_di;
++ if (fbi->var.vmode & FB_VMODE_INTERLACED)
++ params.mem_dp_bg_sync.interlaced = true;
++ params.mem_dp_bg_sync.out_pixel_fmt = mxc_fbi->ipu_di_pix_fmt;
++ params.mem_dp_bg_sync.in_pixel_fmt = fbi_to_pixfmt(fbi);
++ if (mxc_fbi->alpha_chan_en)
++ params.mem_dp_bg_sync.alpha_chan_en = true;
++ }
++ ipu_init_channel(mxc_fbi->ipu, mxc_fbi->ipu_ch, &params);
++
++ return 0;
++}
++
++static int _setup_disp_channel2(struct fb_info *fbi)
++{
++ int retval = 0;
++ struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par;
++ int fb_stride;
++ unsigned long base;
++ unsigned int fr_xoff, fr_yoff, fr_w, fr_h;
++
++ switch (fbi_to_pixfmt(fbi)) {
++ case IPU_PIX_FMT_YUV420P2:
++ case IPU_PIX_FMT_YVU420P:
++ case IPU_PIX_FMT_NV12:
++ case IPU_PIX_FMT_YUV422P:
++ case IPU_PIX_FMT_YVU422P:
++ case IPU_PIX_FMT_YUV420P:
++ case IPU_PIX_FMT_YUV444P:
++ fb_stride = fbi->var.xres_virtual;
++ break;
++ default:
++ fb_stride = fbi->fix.line_length;
++ }
++
++ base = fbi->fix.smem_start;
++ fr_xoff = fbi->var.xoffset;
++ fr_w = fbi->var.xres_virtual;
++ if (!(fbi->var.vmode & FB_VMODE_YWRAP)) {
++ dev_dbg(fbi->device, "Y wrap disabled\n");
++ fr_yoff = fbi->var.yoffset % fbi->var.yres;
++ fr_h = fbi->var.yres;
++ base += fbi->fix.line_length * fbi->var.yres *
++ (fbi->var.yoffset / fbi->var.yres);
++ } else {
++ dev_dbg(fbi->device, "Y wrap enabled\n");
++ fr_yoff = fbi->var.yoffset;
++ fr_h = fbi->var.yres_virtual;
++ }
++ base += fr_yoff * fb_stride + fr_xoff;
++
++ mxc_fbi->cur_ipu_buf = 2;
++ init_completion(&mxc_fbi->flip_complete);
++ /*
++ * We don't need to wait for vsync at the first time
++ * we do pan display after fb is initialized, as IPU will
++ * switch to the newly selected buffer automatically,
++ * so we call complete() for both mxc_fbi->flip_complete
++ * and mxc_fbi->alpha_flip_complete.
++ */
++ complete(&mxc_fbi->flip_complete);
++ if (mxc_fbi->alpha_chan_en) {
++ mxc_fbi->cur_ipu_alpha_buf = 1;
++ init_completion(&mxc_fbi->alpha_flip_complete);
++ complete(&mxc_fbi->alpha_flip_complete);
++ }
++
++ retval = ipu_init_channel_buffer(mxc_fbi->ipu,
++ mxc_fbi->ipu_ch, IPU_INPUT_BUFFER,
++ fbi_to_pixfmt(fbi),
++ fbi->var.xres, fbi->var.yres,
++ fb_stride,
++ fbi->var.rotate,
++ base,
++ base,
++ fbi->var.accel_flags &
++ FB_ACCEL_DOUBLE_FLAG ? 0 : base,
++ 0, 0);
++ if (retval) {
++ dev_err(fbi->device,
++ "ipu_init_channel_buffer error %d\n", retval);
++ return retval;
++ }
++
++ /* update u/v offset */
++ ipu_update_channel_offset(mxc_fbi->ipu, mxc_fbi->ipu_ch,
++ IPU_INPUT_BUFFER,
++ fbi_to_pixfmt(fbi),
++ fr_w,
++ fr_h,
++ fr_w,
++ 0, 0,
++ fr_yoff,
++ fr_xoff);
++
++ if (mxc_fbi->alpha_chan_en) {
++ retval = ipu_init_channel_buffer(mxc_fbi->ipu,
++ mxc_fbi->ipu_ch,
++ IPU_ALPHA_IN_BUFFER,
++ IPU_PIX_FMT_GENERIC,
++ fbi->var.xres, fbi->var.yres,
++ fbi->var.xres,
++ fbi->var.rotate,
++ mxc_fbi->alpha_phy_addr1,
++ mxc_fbi->alpha_phy_addr0,
++ 0,
++ 0, 0);
++ if (retval) {
++ dev_err(fbi->device,
++ "ipu_init_channel_buffer error %d\n", retval);
++ return retval;
++ }
++ }
++
++ return retval;
++}
++
++static bool mxcfb_need_to_set_par(struct fb_info *fbi)
++{
++ struct mxcfb_info *mxc_fbi = fbi->par;
++
++ if ((fbi->var.activate & FB_ACTIVATE_FORCE) &&
++ (fbi->var.activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW)
++ return true;
++
++ /*
++ * Ignore xoffset and yoffset update,
++ * because pan display handles this case.
++ */
++ mxc_fbi->cur_var.xoffset = fbi->var.xoffset;
++ mxc_fbi->cur_var.yoffset = fbi->var.yoffset;
++
++ return !!memcmp(&mxc_fbi->cur_var, &fbi->var,
++ sizeof(struct fb_var_screeninfo));
++}
++
++/*
++ * Set framebuffer parameters and change the operating mode.
++ *
++ * @param info framebuffer information pointer
++ */
++static int mxcfb_set_par(struct fb_info *fbi)
++{
++ int retval = 0;
++ u32 mem_len, alpha_mem_len;
++ ipu_di_signal_cfg_t sig_cfg;
++ struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par;
++
++ int16_t ov_pos_x = 0, ov_pos_y = 0;
++ int ov_pos_ret = 0;
++ struct mxcfb_info *mxc_fbi_fg = NULL;
++ bool ovfbi_enable = false;
++
++ if (ipu_ch_param_bad_alpha_pos(fbi_to_pixfmt(fbi)) &&
++ mxc_fbi->alpha_chan_en) {
++ dev_err(fbi->device, "Bad pixel format for "
++ "graphics plane fb\n");
++ return -EINVAL;
++ }
++
++ if (mxc_fbi->ovfbi)
++ mxc_fbi_fg = (struct mxcfb_info *)mxc_fbi->ovfbi->par;
++
++ if (mxc_fbi->ovfbi && mxc_fbi_fg)
++ if (mxc_fbi_fg->next_blank == FB_BLANK_UNBLANK)
++ ovfbi_enable = true;
++
++ if (!mxcfb_need_to_set_par(fbi))
++ return 0;
++
++ dev_dbg(fbi->device, "Reconfiguring framebuffer\n");
++
++ if (fbi->var.xres == 0 || fbi->var.yres == 0)
++ return 0;
++
++ if (ovfbi_enable) {
++ ov_pos_ret = ipu_disp_get_window_pos(
++ mxc_fbi_fg->ipu, mxc_fbi_fg->ipu_ch,
++ &ov_pos_x, &ov_pos_y);
++ if (ov_pos_ret < 0)
++ dev_err(fbi->device, "Get overlay pos failed, dispdrv:%s.\n",
++ mxc_fbi->dispdrv->drv->name);
++
++ ipu_clear_irq(mxc_fbi_fg->ipu, mxc_fbi_fg->ipu_ch_irq);
++ ipu_disable_irq(mxc_fbi_fg->ipu, mxc_fbi_fg->ipu_ch_irq);
++ ipu_clear_irq(mxc_fbi_fg->ipu, mxc_fbi_fg->ipu_ch_nf_irq);
++ ipu_disable_irq(mxc_fbi_fg->ipu, mxc_fbi_fg->ipu_ch_nf_irq);
++ ipu_disable_channel(mxc_fbi_fg->ipu, mxc_fbi_fg->ipu_ch, true);
++ ipu_uninit_channel(mxc_fbi_fg->ipu, mxc_fbi_fg->ipu_ch);
++ }
++
++ ipu_clear_irq(mxc_fbi->ipu, mxc_fbi->ipu_ch_irq);
++ ipu_disable_irq(mxc_fbi->ipu, mxc_fbi->ipu_ch_irq);
++ ipu_clear_irq(mxc_fbi->ipu, mxc_fbi->ipu_ch_nf_irq);
++ ipu_disable_irq(mxc_fbi->ipu, mxc_fbi->ipu_ch_nf_irq);
++ ipu_disable_channel(mxc_fbi->ipu, mxc_fbi->ipu_ch, true);
++ ipu_uninit_channel(mxc_fbi->ipu, mxc_fbi->ipu_ch);
++
++ /*
++ * Disable IPU hsp clock if it is enabled for an
++ * additional time in ipu common driver.
++ */
++ if (mxc_fbi->first_set_par && mxc_fbi->late_init)
++ ipu_disable_hsp_clk(mxc_fbi->ipu);
++
++ mxcfb_set_fix(fbi);
++
++ mem_len = fbi->var.yres_virtual * fbi->fix.line_length;
++ if (!fbi->fix.smem_start || (mem_len > fbi->fix.smem_len)) {
++ if (fbi->fix.smem_start)
++ mxcfb_unmap_video_memory(fbi);
++
++ if (mxcfb_map_video_memory(fbi) < 0)
++ return -ENOMEM;
++ }
++
++ if (mxc_fbi->first_set_par) {
++ /*
++ * Clear the screen in case uboot fb pixel format is not
++ * the same to kernel fb pixel format.
++ */
++ if (mxc_fbi->late_init)
++ memset((char *)fbi->screen_base, 0, fbi->fix.smem_len);
++
++ mxc_fbi->first_set_par = false;
++ }
++
++ if (mxc_fbi->alpha_chan_en) {
++ alpha_mem_len = fbi->var.xres * fbi->var.yres;
++ if ((!mxc_fbi->alpha_phy_addr0 && !mxc_fbi->alpha_phy_addr1) ||
++ (alpha_mem_len > mxc_fbi->alpha_mem_len)) {
++ if (mxc_fbi->alpha_phy_addr0)
++ dma_free_coherent(fbi->device,
++ mxc_fbi->alpha_mem_len,
++ mxc_fbi->alpha_virt_addr0,
++ mxc_fbi->alpha_phy_addr0);
++ if (mxc_fbi->alpha_phy_addr1)
++ dma_free_coherent(fbi->device,
++ mxc_fbi->alpha_mem_len,
++ mxc_fbi->alpha_virt_addr1,
++ mxc_fbi->alpha_phy_addr1);
++
++ mxc_fbi->alpha_virt_addr0 =
++ dma_alloc_coherent(fbi->device,
++ alpha_mem_len,
++ &mxc_fbi->alpha_phy_addr0,
++ GFP_DMA | GFP_KERNEL);
++
++ mxc_fbi->alpha_virt_addr1 =
++ dma_alloc_coherent(fbi->device,
++ alpha_mem_len,
++ &mxc_fbi->alpha_phy_addr1,
++ GFP_DMA | GFP_KERNEL);
++ if (mxc_fbi->alpha_virt_addr0 == NULL ||
++ mxc_fbi->alpha_virt_addr1 == NULL) {
++ dev_err(fbi->device, "mxcfb: dma alloc for"
++ " alpha buffer failed.\n");
++ if (mxc_fbi->alpha_virt_addr0)
++ dma_free_coherent(fbi->device,
++ mxc_fbi->alpha_mem_len,
++ mxc_fbi->alpha_virt_addr0,
++ mxc_fbi->alpha_phy_addr0);
++ if (mxc_fbi->alpha_virt_addr1)
++ dma_free_coherent(fbi->device,
++ mxc_fbi->alpha_mem_len,
++ mxc_fbi->alpha_virt_addr1,
++ mxc_fbi->alpha_phy_addr1);
++ return -ENOMEM;
++ }
++ mxc_fbi->alpha_mem_len = alpha_mem_len;
++ }
++ }
++
++ if (mxc_fbi->next_blank != FB_BLANK_UNBLANK)
++ return retval;
++
++ if (mxc_fbi->dispdrv && mxc_fbi->dispdrv->drv->setup) {
++ retval = mxc_fbi->dispdrv->drv->setup(mxc_fbi->dispdrv, fbi);
++ if (retval < 0) {
++ dev_err(fbi->device, "setup error, dispdrv:%s.\n",
++ mxc_fbi->dispdrv->drv->name);
++ return -EINVAL;
++ }
++ }
++
++ _setup_disp_channel1(fbi);
++ if (ovfbi_enable)
++ _setup_disp_channel1(mxc_fbi->ovfbi);
++
++ if (!mxc_fbi->overlay) {
++ uint32_t out_pixel_fmt;
++
++ memset(&sig_cfg, 0, sizeof(sig_cfg));
++ if (fbi->var.vmode & FB_VMODE_INTERLACED)
++ sig_cfg.interlaced = true;
++ out_pixel_fmt = mxc_fbi->ipu_di_pix_fmt;
++ if (fbi->var.vmode & FB_VMODE_ODD_FLD_FIRST) /* PAL */
++ sig_cfg.odd_field_first = true;
++ if (mxc_fbi->ipu_int_clk)
++ sig_cfg.int_clk = true;
++ if (fbi->var.sync & FB_SYNC_HOR_HIGH_ACT)
++ sig_cfg.Hsync_pol = true;
++ if (fbi->var.sync & FB_SYNC_VERT_HIGH_ACT)
++ sig_cfg.Vsync_pol = true;
++ if (!(fbi->var.sync & FB_SYNC_CLK_LAT_FALL))
++ sig_cfg.clk_pol = true;
++ if (fbi->var.sync & FB_SYNC_DATA_INVERT)
++ sig_cfg.data_pol = true;
++ if (!(fbi->var.sync & FB_SYNC_OE_LOW_ACT))
++ sig_cfg.enable_pol = true;
++ if (fbi->var.sync & FB_SYNC_CLK_IDLE_EN)
++ sig_cfg.clkidle_en = true;
++
++ dev_dbg(fbi->device, "pixclock = %ul Hz\n",
++ (u32) (PICOS2KHZ(fbi->var.pixclock) * 1000UL));
++
++ if (ipu_init_sync_panel(mxc_fbi->ipu, mxc_fbi->ipu_di,
++ (PICOS2KHZ(fbi->var.pixclock)) * 1000UL,
++ fbi->var.xres, fbi->var.yres,
++ out_pixel_fmt,
++ fbi->var.left_margin,
++ fbi->var.hsync_len,
++ fbi->var.right_margin,
++ fbi->var.upper_margin,
++ fbi->var.vsync_len,
++ fbi->var.lower_margin,
++ 0, sig_cfg) != 0) {
++ dev_err(fbi->device,
++ "mxcfb: Error initializing panel.\n");
++ return -EINVAL;
++ }
++
++ fbi->mode =
++ (struct fb_videomode *)fb_match_mode(&fbi->var,
++ &fbi->modelist);
++
++ ipu_disp_set_window_pos(mxc_fbi->ipu, mxc_fbi->ipu_ch, 0, 0);
++ }
++
++ retval = _setup_disp_channel2(fbi);
++ if (retval) {
++ ipu_uninit_channel(mxc_fbi->ipu, mxc_fbi->ipu_ch);
++ return retval;
++ }
++
++ if (ovfbi_enable) {
++ if (ov_pos_ret >= 0)
++ ipu_disp_set_window_pos(
++ mxc_fbi_fg->ipu, mxc_fbi_fg->ipu_ch,
++ ov_pos_x, ov_pos_y);
++ retval = _setup_disp_channel2(mxc_fbi->ovfbi);
++ if (retval) {
++ ipu_uninit_channel(mxc_fbi_fg->ipu, mxc_fbi_fg->ipu_ch);
++ ipu_uninit_channel(mxc_fbi->ipu, mxc_fbi->ipu_ch);
++ return retval;
++ }
++ }
++
++ ipu_enable_channel(mxc_fbi->ipu, mxc_fbi->ipu_ch);
++ if (ovfbi_enable)
++ ipu_enable_channel(mxc_fbi_fg->ipu, mxc_fbi_fg->ipu_ch);
++
++ if (mxc_fbi->dispdrv && mxc_fbi->dispdrv->drv->enable) {
++ retval = mxc_fbi->dispdrv->drv->enable(mxc_fbi->dispdrv);
++ if (retval < 0) {
++ dev_err(fbi->device, "enable error, dispdrv:%s.\n",
++ mxc_fbi->dispdrv->drv->name);
++ return -EINVAL;
++ }
++ }
++
++ mxc_fbi->cur_var = fbi->var;
++
++ return retval;
++}
++
++static int _swap_channels(struct fb_info *fbi_from,
++ struct fb_info *fbi_to, bool both_on)
++{
++ int retval, tmp;
++ ipu_channel_t old_ch;
++ struct fb_info *ovfbi;
++ struct mxcfb_info *mxc_fbi_from = (struct mxcfb_info *)fbi_from->par;
++ struct mxcfb_info *mxc_fbi_to = (struct mxcfb_info *)fbi_to->par;
++
++ if (both_on) {
++ ipu_disable_channel(mxc_fbi_to->ipu, mxc_fbi_to->ipu_ch, true);
++ ipu_uninit_channel(mxc_fbi_to->ipu, mxc_fbi_to->ipu_ch);
++ }
++
++ /* switch the mxc fbi parameters */
++ old_ch = mxc_fbi_from->ipu_ch;
++ mxc_fbi_from->ipu_ch = mxc_fbi_to->ipu_ch;
++ mxc_fbi_to->ipu_ch = old_ch;
++ tmp = mxc_fbi_from->ipu_ch_irq;
++ mxc_fbi_from->ipu_ch_irq = mxc_fbi_to->ipu_ch_irq;
++ mxc_fbi_to->ipu_ch_irq = tmp;
++ tmp = mxc_fbi_from->ipu_ch_nf_irq;
++ mxc_fbi_from->ipu_ch_nf_irq = mxc_fbi_to->ipu_ch_nf_irq;
++ mxc_fbi_to->ipu_ch_nf_irq = tmp;
++ ovfbi = mxc_fbi_from->ovfbi;
++ mxc_fbi_from->ovfbi = mxc_fbi_to->ovfbi;
++ mxc_fbi_to->ovfbi = ovfbi;
++
++ _setup_disp_channel1(fbi_from);
++ retval = _setup_disp_channel2(fbi_from);
++ if (retval)
++ return retval;
++
++ /* switch between dp and dc, disable old idmac, enable new idmac */
++ retval = ipu_swap_channel(mxc_fbi_from->ipu, old_ch, mxc_fbi_from->ipu_ch);
++ ipu_uninit_channel(mxc_fbi_from->ipu, old_ch);
++
++ if (both_on) {
++ _setup_disp_channel1(fbi_to);
++ retval = _setup_disp_channel2(fbi_to);
++ if (retval)
++ return retval;
++ ipu_enable_channel(mxc_fbi_to->ipu, mxc_fbi_to->ipu_ch);
++ }
++
++ return retval;
++}
++
++static int swap_channels(struct fb_info *fbi_from)
++{
++ int i;
++ int swap_mode;
++ ipu_channel_t ch_to;
++ struct mxcfb_info *mxc_fbi_from = (struct mxcfb_info *)fbi_from->par;
++ struct fb_info *fbi_to = NULL;
++ struct mxcfb_info *mxc_fbi_to;
++
++ /* what's the target channel? */
++ if (mxc_fbi_from->ipu_ch == MEM_BG_SYNC)
++ ch_to = MEM_DC_SYNC;
++ else
++ ch_to = MEM_BG_SYNC;
++
++ fbi_to = found_registered_fb(ch_to, mxc_fbi_from->ipu_id);
++ if (!fbi_to)
++ return -1;
++ mxc_fbi_to = (struct mxcfb_info *)fbi_to->par;
++
++ ipu_clear_irq(mxc_fbi_from->ipu, mxc_fbi_from->ipu_ch_irq);
++ ipu_clear_irq(mxc_fbi_to->ipu, mxc_fbi_to->ipu_ch_irq);
++ ipu_free_irq(mxc_fbi_from->ipu, mxc_fbi_from->ipu_ch_irq, fbi_from);
++ ipu_free_irq(mxc_fbi_to->ipu, mxc_fbi_to->ipu_ch_irq, fbi_to);
++ ipu_clear_irq(mxc_fbi_from->ipu, mxc_fbi_from->ipu_ch_nf_irq);
++ ipu_clear_irq(mxc_fbi_to->ipu, mxc_fbi_to->ipu_ch_nf_irq);
++ ipu_free_irq(mxc_fbi_from->ipu, mxc_fbi_from->ipu_ch_nf_irq, fbi_from);
++ ipu_free_irq(mxc_fbi_to->ipu, mxc_fbi_to->ipu_ch_nf_irq, fbi_to);
++
++ if (mxc_fbi_from->cur_blank == FB_BLANK_UNBLANK) {
++ if (mxc_fbi_to->cur_blank == FB_BLANK_UNBLANK)
++ swap_mode = BOTH_ON;
++ else
++ swap_mode = SRC_ON;
++ } else {
++ if (mxc_fbi_to->cur_blank == FB_BLANK_UNBLANK)
++ swap_mode = TGT_ON;
++ else
++ swap_mode = BOTH_OFF;
++ }
++
++ switch (swap_mode) {
++ case BOTH_ON:
++ /* disable target->switch src->enable target */
++ _swap_channels(fbi_from, fbi_to, true);
++ break;
++ case SRC_ON:
++ /* just switch src */
++ _swap_channels(fbi_from, fbi_to, false);
++ break;
++ case TGT_ON:
++ /* just switch target */
++ _swap_channels(fbi_to, fbi_from, false);
++ break;
++ case BOTH_OFF:
++ /* switch directly, no more need to do */
++ mxc_fbi_to->ipu_ch = mxc_fbi_from->ipu_ch;
++ mxc_fbi_from->ipu_ch = ch_to;
++ i = mxc_fbi_from->ipu_ch_irq;
++ mxc_fbi_from->ipu_ch_irq = mxc_fbi_to->ipu_ch_irq;
++ mxc_fbi_to->ipu_ch_irq = i;
++ i = mxc_fbi_from->ipu_ch_nf_irq;
++ mxc_fbi_from->ipu_ch_nf_irq = mxc_fbi_to->ipu_ch_nf_irq;
++ mxc_fbi_to->ipu_ch_nf_irq = i;
++ break;
++ default:
++ break;
++ }
++
++ if (ipu_request_irq(mxc_fbi_from->ipu, mxc_fbi_from->ipu_ch_irq,
++ mxcfb_irq_handler, IPU_IRQF_ONESHOT,
++ MXCFB_NAME, fbi_from) != 0) {
++ dev_err(fbi_from->device, "Error registering irq %d\n",
++ mxc_fbi_from->ipu_ch_irq);
++ return -EBUSY;
++ }
++ ipu_disable_irq(mxc_fbi_from->ipu, mxc_fbi_from->ipu_ch_irq);
++ if (ipu_request_irq(mxc_fbi_to->ipu, mxc_fbi_to->ipu_ch_irq,
++ mxcfb_irq_handler, IPU_IRQF_ONESHOT,
++ MXCFB_NAME, fbi_to) != 0) {
++ dev_err(fbi_to->device, "Error registering irq %d\n",
++ mxc_fbi_to->ipu_ch_irq);
++ return -EBUSY;
++ }
++ ipu_disable_irq(mxc_fbi_to->ipu, mxc_fbi_to->ipu_ch_irq);
++ if (ipu_request_irq(mxc_fbi_from->ipu, mxc_fbi_from->ipu_ch_nf_irq,
++ mxcfb_nf_irq_handler, IPU_IRQF_ONESHOT,
++ MXCFB_NAME, fbi_from) != 0) {
++ dev_err(fbi_from->device, "Error registering irq %d\n",
++ mxc_fbi_from->ipu_ch_nf_irq);
++ return -EBUSY;
++ }
++ ipu_disable_irq(mxc_fbi_from->ipu, mxc_fbi_from->ipu_ch_nf_irq);
++ if (ipu_request_irq(mxc_fbi_to->ipu, mxc_fbi_to->ipu_ch_nf_irq,
++ mxcfb_nf_irq_handler, IPU_IRQF_ONESHOT,
++ MXCFB_NAME, fbi_to) != 0) {
++ dev_err(fbi_to->device, "Error registering irq %d\n",
++ mxc_fbi_to->ipu_ch_nf_irq);
++ return -EBUSY;
++ }
++ ipu_disable_irq(mxc_fbi_to->ipu, mxc_fbi_to->ipu_ch_nf_irq);
++
++ return 0;
++}
++
++/*
++ * Check framebuffer variable parameters and adjust to valid values.
++ *
++ * @param var framebuffer variable parameters
++ *
++ * @param info framebuffer information pointer
++ */
++static int mxcfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
++{
++ u32 vtotal;
++ u32 htotal;
++ struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)info->par;
++
++
++ if (var->xres == 0 || var->yres == 0)
++ return 0;
++
++ /* fg should not bigger than bg */
++ if (mxc_fbi->ipu_ch == MEM_FG_SYNC) {
++ struct fb_info *fbi_tmp;
++ int bg_xres = 0, bg_yres = 0;
++ int16_t pos_x, pos_y;
++
++ bg_xres = var->xres;
++ bg_yres = var->yres;
++
++ fbi_tmp = found_registered_fb(MEM_BG_SYNC, mxc_fbi->ipu_id);
++ if (fbi_tmp) {
++ bg_xres = fbi_tmp->var.xres;
++ bg_yres = fbi_tmp->var.yres;
++ }
++
++ ipu_disp_get_window_pos(mxc_fbi->ipu, mxc_fbi->ipu_ch, &pos_x, &pos_y);
++
++ if ((var->xres + pos_x) > bg_xres)
++ var->xres = bg_xres - pos_x;
++ if ((var->yres + pos_y) > bg_yres)
++ var->yres = bg_yres - pos_y;
++ }
++
++ if (var->rotate > IPU_ROTATE_VERT_FLIP)
++ var->rotate = IPU_ROTATE_NONE;
++
++ if (var->xres_virtual < var->xres)
++ var->xres_virtual = var->xres;
++
++ if (var->yres_virtual < var->yres)
++ var->yres_virtual = var->yres * 3;
++
++ if ((var->bits_per_pixel != 32) && (var->bits_per_pixel != 24) &&
++ (var->bits_per_pixel != 16) && (var->bits_per_pixel != 12) &&
++ (var->bits_per_pixel != 8))
++ var->bits_per_pixel = 16;
++
++ if (check_var_pixfmt(var))
++ /* Fall back to default */
++ bpp_to_var(var->bits_per_pixel, var);
++
++ if (var->pixclock < 1000) {
++ htotal = var->xres + var->right_margin + var->hsync_len +
++ var->left_margin;
++ vtotal = var->yres + var->lower_margin + var->vsync_len +
++ var->upper_margin;
++ var->pixclock = (vtotal * htotal * 6UL) / 100UL;
++ var->pixclock = KHZ2PICOS(var->pixclock);
++ dev_dbg(info->device,
++ "pixclock set for 60Hz refresh = %u ps\n",
++ var->pixclock);
++ }
++
++ var->height = -1;
++ var->width = -1;
++ var->grayscale = 0;
++
++ return 0;
++}
++
++static inline u_int _chan_to_field(u_int chan, struct fb_bitfield *bf)
++{
++ chan &= 0xffff;
++ chan >>= 16 - bf->length;
++ return chan << bf->offset;
++}
++
++static int mxcfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
++ u_int trans, struct fb_info *fbi)
++{
++ unsigned int val;
++ int ret = 1;
++
++ /*
++ * If greyscale is true, then we convert the RGB value
++ * to greyscale no matter what visual we are using.
++ */
++ if (fbi->var.grayscale)
++ red = green = blue = (19595 * red + 38470 * green +
++ 7471 * blue) >> 16;
++ switch (fbi->fix.visual) {
++ case FB_VISUAL_TRUECOLOR:
++ /*
++ * 16-bit True Colour. We encode the RGB value
++ * according to the RGB bitfield information.
++ */
++ if (regno < 16) {
++ u32 *pal = fbi->pseudo_palette;
++
++ val = _chan_to_field(red, &fbi->var.red);
++ val |= _chan_to_field(green, &fbi->var.green);
++ val |= _chan_to_field(blue, &fbi->var.blue);
++
++ pal[regno] = val;
++ ret = 0;
++ }
++ break;
++
++ case FB_VISUAL_STATIC_PSEUDOCOLOR:
++ case FB_VISUAL_PSEUDOCOLOR:
++ break;
++ }
++
++ return ret;
++}
++
++/*
++ * Function to handle custom ioctls for MXC framebuffer.
++ *
++ * @param inode inode struct
++ *
++ * @param file file struct
++ *
++ * @param cmd Ioctl command to handle
++ *
++ * @param arg User pointer to command arguments
++ *
++ * @param fbi framebuffer information pointer
++ */
++static int mxcfb_ioctl(struct fb_info *fbi, unsigned int cmd, unsigned long arg)
++{
++ int retval = 0;
++ int __user *argp = (void __user *)arg;
++ struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par;
++
++ switch (cmd) {
++ case MXCFB_SET_GBL_ALPHA:
++ {
++ struct mxcfb_gbl_alpha ga;
++
++ if (copy_from_user(&ga, (void *)arg, sizeof(ga))) {
++ retval = -EFAULT;
++ break;
++ }
++
++ if (ipu_disp_set_global_alpha(mxc_fbi->ipu,
++ mxc_fbi->ipu_ch,
++ (bool)ga.enable,
++ ga.alpha)) {
++ retval = -EINVAL;
++ break;
++ }
++
++ if (ga.enable)
++ mxc_fbi->alpha_chan_en = false;
++
++ if (ga.enable)
++ dev_dbg(fbi->device,
++ "Set global alpha of %s to %d\n",
++ fbi->fix.id, ga.alpha);
++ break;
++ }
++ case MXCFB_SET_LOC_ALPHA:
++ {
++ struct mxcfb_loc_alpha la;
++ bool bad_pixfmt =
++ ipu_ch_param_bad_alpha_pos(fbi_to_pixfmt(fbi));
++
++ if (copy_from_user(&la, (void *)arg, sizeof(la))) {
++ retval = -EFAULT;
++ break;
++ }
++
++ if (la.enable && !la.alpha_in_pixel) {
++ struct fb_info *fbi_tmp;
++ ipu_channel_t ipu_ch;
++
++ if (bad_pixfmt) {
++ dev_err(fbi->device, "Bad pixel format "
++ "for graphics plane fb\n");
++ retval = -EINVAL;
++ break;
++ }
++
++ mxc_fbi->alpha_chan_en = true;
++
++ if (mxc_fbi->ipu_ch == MEM_FG_SYNC)
++ ipu_ch = MEM_BG_SYNC;
++ else if (mxc_fbi->ipu_ch == MEM_BG_SYNC)
++ ipu_ch = MEM_FG_SYNC;
++ else {
++ retval = -EINVAL;
++ break;
++ }
++
++ fbi_tmp = found_registered_fb(ipu_ch, mxc_fbi->ipu_id);
++ if (fbi_tmp)
++ ((struct mxcfb_info *)(fbi_tmp->par))->alpha_chan_en = false;
++ } else
++ mxc_fbi->alpha_chan_en = false;
++
++ if (ipu_disp_set_global_alpha(mxc_fbi->ipu,
++ mxc_fbi->ipu_ch,
++ !(bool)la.enable, 0)) {
++ retval = -EINVAL;
++ break;
++ }
++
++ fbi->var.activate = (fbi->var.activate & ~FB_ACTIVATE_MASK) |
++ FB_ACTIVATE_NOW | FB_ACTIVATE_FORCE;
++ mxcfb_set_par(fbi);
++
++ la.alpha_phy_addr0 = mxc_fbi->alpha_phy_addr0;
++ la.alpha_phy_addr1 = mxc_fbi->alpha_phy_addr1;
++ if (copy_to_user((void *)arg, &la, sizeof(la))) {
++ retval = -EFAULT;
++ break;
++ }
++
++ if (la.enable)
++ dev_dbg(fbi->device,
++ "Enable DP local alpha for %s\n",
++ fbi->fix.id);
++ break;
++ }
++ case MXCFB_SET_LOC_ALP_BUF:
++ {
++ unsigned long base;
++ uint32_t ipu_alp_ch_irq;
++
++ if (!(((mxc_fbi->ipu_ch == MEM_FG_SYNC) ||
++ (mxc_fbi->ipu_ch == MEM_BG_SYNC)) &&
++ (mxc_fbi->alpha_chan_en))) {
++ dev_err(fbi->device,
++ "Should use background or overlay "
++ "framebuffer to set the alpha buffer "
++ "number\n");
++ return -EINVAL;
++ }
++
++ if (get_user(base, argp))
++ return -EFAULT;
++
++ if (base != mxc_fbi->alpha_phy_addr0 &&
++ base != mxc_fbi->alpha_phy_addr1) {
++ dev_err(fbi->device,
++ "Wrong alpha buffer physical address "
++ "%lu\n", base);
++ return -EINVAL;
++ }
++
++ if (mxc_fbi->ipu_ch == MEM_FG_SYNC)
++ ipu_alp_ch_irq = IPU_IRQ_FG_ALPHA_SYNC_EOF;
++ else
++ ipu_alp_ch_irq = IPU_IRQ_BG_ALPHA_SYNC_EOF;
++
++ retval = wait_for_completion_timeout(
++ &mxc_fbi->alpha_flip_complete, HZ/2);
++ if (retval == 0) {
++ dev_err(fbi->device, "timeout when waiting for alpha flip irq\n");
++ retval = -ETIMEDOUT;
++ break;
++ }
++
++ mxc_fbi->cur_ipu_alpha_buf =
++ !mxc_fbi->cur_ipu_alpha_buf;
++ if (ipu_update_channel_buffer(mxc_fbi->ipu, mxc_fbi->ipu_ch,
++ IPU_ALPHA_IN_BUFFER,
++ mxc_fbi->
++ cur_ipu_alpha_buf,
++ base) == 0) {
++ ipu_select_buffer(mxc_fbi->ipu, mxc_fbi->ipu_ch,
++ IPU_ALPHA_IN_BUFFER,
++ mxc_fbi->cur_ipu_alpha_buf);
++ ipu_clear_irq(mxc_fbi->ipu, ipu_alp_ch_irq);
++ ipu_enable_irq(mxc_fbi->ipu, ipu_alp_ch_irq);
++ } else {
++ dev_err(fbi->device,
++ "Error updating %s SDC alpha buf %d "
++ "to address=0x%08lX\n",
++ fbi->fix.id,
++ mxc_fbi->cur_ipu_alpha_buf, base);
++ }
++ break;
++ }
++ case MXCFB_SET_CLR_KEY:
++ {
++ struct mxcfb_color_key key;
++ if (copy_from_user(&key, (void *)arg, sizeof(key))) {
++ retval = -EFAULT;
++ break;
++ }
++ retval = ipu_disp_set_color_key(mxc_fbi->ipu, mxc_fbi->ipu_ch,
++ key.enable,
++ key.color_key);
++ dev_dbg(fbi->device, "Set color key to 0x%08X\n",
++ key.color_key);
++ break;
++ }
++ case MXCFB_SET_GAMMA:
++ {
++ struct mxcfb_gamma gamma;
++ if (copy_from_user(&gamma, (void *)arg, sizeof(gamma))) {
++ retval = -EFAULT;
++ break;
++ }
++ retval = ipu_disp_set_gamma_correction(mxc_fbi->ipu,
++ mxc_fbi->ipu_ch,
++ gamma.enable,
++ gamma.constk,
++ gamma.slopek);
++ break;
++ }
++ case MXCFB_WAIT_FOR_VSYNC:
++ {
++ if (mxc_fbi->ipu_ch == MEM_FG_SYNC) {
++ /* BG should poweron */
++ struct mxcfb_info *bg_mxcfbi = NULL;
++ struct fb_info *fbi_tmp;
++
++ fbi_tmp = found_registered_fb(MEM_BG_SYNC, mxc_fbi->ipu_id);
++ if (fbi_tmp)
++ bg_mxcfbi = ((struct mxcfb_info *)(fbi_tmp->par));
++
++ if (!bg_mxcfbi) {
++ retval = -EINVAL;
++ break;
++ }
++ if (bg_mxcfbi->cur_blank != FB_BLANK_UNBLANK) {
++ retval = -EINVAL;
++ break;
++ }
++ }
++ if (mxc_fbi->cur_blank != FB_BLANK_UNBLANK) {
++ retval = -EINVAL;
++ break;
++ }
++
++ init_completion(&mxc_fbi->vsync_complete);
++ ipu_clear_irq(mxc_fbi->ipu, mxc_fbi->ipu_ch_nf_irq);
++ ipu_enable_irq(mxc_fbi->ipu, mxc_fbi->ipu_ch_nf_irq);
++ retval = wait_for_completion_interruptible_timeout(
++ &mxc_fbi->vsync_complete, 1 * HZ);
++ if (retval == 0) {
++ dev_err(fbi->device,
++ "MXCFB_WAIT_FOR_VSYNC: timeout %d\n",
++ retval);
++ retval = -ETIME;
++ } else if (retval > 0) {
++ retval = 0;
++ }
++ break;
++ }
++ case FBIO_ALLOC:
++ {
++ int size;
++ struct mxcfb_alloc_list *mem;
++
++ mem = kzalloc(sizeof(*mem), GFP_KERNEL);
++ if (mem == NULL)
++ return -ENOMEM;
++
++ if (get_user(size, argp))
++ return -EFAULT;
++
++ mem->size = PAGE_ALIGN(size);
++
++ mem->cpu_addr = dma_alloc_coherent(fbi->device, size,
++ &mem->phy_addr,
++ GFP_KERNEL);
++ if (mem->cpu_addr == NULL) {
++ kfree(mem);
++ return -ENOMEM;
++ }
++
++ list_add(&mem->list, &fb_alloc_list);
++
++ dev_dbg(fbi->device, "allocated %d bytes @ 0x%08X\n",
++ mem->size, mem->phy_addr);
++
++ if (put_user(mem->phy_addr, argp))
++ return -EFAULT;
++
++ break;
++ }
++ case FBIO_FREE:
++ {
++ unsigned long offset;
++ struct mxcfb_alloc_list *mem;
++
++ if (get_user(offset, argp))
++ return -EFAULT;
++
++ retval = -EINVAL;
++ list_for_each_entry(mem, &fb_alloc_list, list) {
++ if (mem->phy_addr == offset) {
++ list_del(&mem->list);
++ dma_free_coherent(fbi->device,
++ mem->size,
++ mem->cpu_addr,
++ mem->phy_addr);
++ kfree(mem);
++ retval = 0;
++ break;
++ }
++ }
++
++ break;
++ }
++ case MXCFB_SET_OVERLAY_POS:
++ {
++ struct mxcfb_pos pos;
++ struct fb_info *bg_fbi = NULL;
++ struct mxcfb_info *bg_mxcfbi = NULL;
++
++ if (mxc_fbi->ipu_ch != MEM_FG_SYNC) {
++ dev_err(fbi->device, "Should use the overlay "
++ "framebuffer to set the position of "
++ "the overlay window\n");
++ retval = -EINVAL;
++ break;
++ }
++
++ if (copy_from_user(&pos, (void *)arg, sizeof(pos))) {
++ retval = -EFAULT;
++ break;
++ }
++
++ bg_fbi = found_registered_fb(MEM_BG_SYNC, mxc_fbi->ipu_id);
++ if (bg_fbi)
++ bg_mxcfbi = ((struct mxcfb_info *)(bg_fbi->par));
++
++ if (bg_fbi == NULL) {
++ dev_err(fbi->device, "Cannot find the "
++ "background framebuffer\n");
++ retval = -ENOENT;
++ break;
++ }
++
++ /* if fb is unblank, check if the pos fit the display */
++ if (mxc_fbi->cur_blank == FB_BLANK_UNBLANK) {
++ if (fbi->var.xres + pos.x > bg_fbi->var.xres) {
++ if (bg_fbi->var.xres < fbi->var.xres)
++ pos.x = 0;
++ else
++ pos.x = bg_fbi->var.xres - fbi->var.xres;
++ }
++ if (fbi->var.yres + pos.y > bg_fbi->var.yres) {
++ if (bg_fbi->var.yres < fbi->var.yres)
++ pos.y = 0;
++ else
++ pos.y = bg_fbi->var.yres - fbi->var.yres;
++ }
++ }
++
++ retval = ipu_disp_set_window_pos(mxc_fbi->ipu, mxc_fbi->ipu_ch,
++ pos.x, pos.y);
++
++ if (copy_to_user((void *)arg, &pos, sizeof(pos))) {
++ retval = -EFAULT;
++ break;
++ }
++ break;
++ }
++ case MXCFB_GET_FB_IPU_CHAN:
++ {
++ struct mxcfb_info *mxc_fbi =
++ (struct mxcfb_info *)fbi->par;
++
++ if (put_user(mxc_fbi->ipu_ch, argp))
++ return -EFAULT;
++ break;
++ }
++ case MXCFB_GET_DIFMT:
++ {
++ struct mxcfb_info *mxc_fbi =
++ (struct mxcfb_info *)fbi->par;
++
++ if (put_user(mxc_fbi->ipu_di_pix_fmt, argp))
++ return -EFAULT;
++ break;
++ }
++ case MXCFB_GET_FB_IPU_DI:
++ {
++ struct mxcfb_info *mxc_fbi =
++ (struct mxcfb_info *)fbi->par;
++
++ if (put_user(mxc_fbi->ipu_di, argp))
++ return -EFAULT;
++ break;
++ }
++ case MXCFB_GET_FB_BLANK:
++ {
++ struct mxcfb_info *mxc_fbi =
++ (struct mxcfb_info *)fbi->par;
++
++ if (put_user(mxc_fbi->cur_blank, argp))
++ return -EFAULT;
++ break;
++ }
++ case MXCFB_SET_DIFMT:
++ {
++ struct mxcfb_info *mxc_fbi =
++ (struct mxcfb_info *)fbi->par;
++
++ if (get_user(mxc_fbi->ipu_di_pix_fmt, argp))
++ return -EFAULT;
++
++ break;
++ }
++ case MXCFB_CSC_UPDATE:
++ {
++ struct mxcfb_csc_matrix csc;
++
++ if (copy_from_user(&csc, (void *) arg, sizeof(csc)))
++ return -EFAULT;
++
++ if ((mxc_fbi->ipu_ch != MEM_FG_SYNC) &&
++ (mxc_fbi->ipu_ch != MEM_BG_SYNC) &&
++ (mxc_fbi->ipu_ch != MEM_BG_ASYNC0))
++ return -EFAULT;
++ ipu_set_csc_coefficients(mxc_fbi->ipu, mxc_fbi->ipu_ch,
++ csc.param);
++ break;
++ }
++ default:
++ retval = -EINVAL;
++ }
++ return retval;
++}
++
++/*
++ * mxcfb_blank():
++ * Blank the display.
++ */
++static int mxcfb_blank(int blank, struct fb_info *info)
++{
++ struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)info->par;
++ int ret = 0;
++
++ dev_dbg(info->device, "blank = %d\n", blank);
++
++ if (mxc_fbi->cur_blank == blank)
++ return 0;
++
++ mxc_fbi->next_blank = blank;
++
++ switch (blank) {
++ case FB_BLANK_POWERDOWN:
++ case FB_BLANK_VSYNC_SUSPEND:
++ case FB_BLANK_HSYNC_SUSPEND:
++ case FB_BLANK_NORMAL:
++ if (mxc_fbi->dispdrv && mxc_fbi->dispdrv->drv->disable)
++ mxc_fbi->dispdrv->drv->disable(mxc_fbi->dispdrv);
++ ipu_disable_channel(mxc_fbi->ipu, mxc_fbi->ipu_ch, true);
++ if (mxc_fbi->ipu_di >= 0)
++ ipu_uninit_sync_panel(mxc_fbi->ipu, mxc_fbi->ipu_di);
++ ipu_uninit_channel(mxc_fbi->ipu, mxc_fbi->ipu_ch);
++ break;
++ case FB_BLANK_UNBLANK:
++ info->var.activate = (info->var.activate & ~FB_ACTIVATE_MASK) |
++ FB_ACTIVATE_NOW | FB_ACTIVATE_FORCE;
++ ret = mxcfb_set_par(info);
++ break;
++ }
++ if (!ret)
++ mxc_fbi->cur_blank = blank;
++ return ret;
++}
++
++/*
++ * Pan or Wrap the Display
++ *
++ * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
++ *
++ * @param var Variable screen buffer information
++ * @param info Framebuffer information pointer
++ */
++static int
++mxcfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
++{
++ struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)info->par,
++ *mxc_graphic_fbi = NULL;
++ u_int y_bottom;
++ unsigned int fr_xoff, fr_yoff, fr_w, fr_h;
++ unsigned long base, active_alpha_phy_addr = 0;
++ bool loc_alpha_en = false;
++ int fb_stride;
++ int i;
++ int ret;
++
++ /* no pan display during fb blank */
++ if (mxc_fbi->ipu_ch == MEM_FG_SYNC) {
++ struct mxcfb_info *bg_mxcfbi = NULL;
++ struct fb_info *fbi_tmp;
++
++ fbi_tmp = found_registered_fb(MEM_BG_SYNC, mxc_fbi->ipu_id);
++ if (fbi_tmp)
++ bg_mxcfbi = ((struct mxcfb_info *)(fbi_tmp->par));
++ if (!bg_mxcfbi)
++ return -EINVAL;
++ if (bg_mxcfbi->cur_blank != FB_BLANK_UNBLANK)
++ return -EINVAL;
++ }
++ if (mxc_fbi->cur_blank != FB_BLANK_UNBLANK)
++ return -EINVAL;
++
++ y_bottom = var->yoffset;
++
++ if (y_bottom > info->var.yres_virtual)
++ return -EINVAL;
++
++ switch (fbi_to_pixfmt(info)) {
++ case IPU_PIX_FMT_YUV420P2:
++ case IPU_PIX_FMT_YVU420P:
++ case IPU_PIX_FMT_NV12:
++ case IPU_PIX_FMT_YUV422P:
++ case IPU_PIX_FMT_YVU422P:
++ case IPU_PIX_FMT_YUV420P:
++ case IPU_PIX_FMT_YUV444P:
++ fb_stride = info->var.xres_virtual;
++ break;
++ default:
++ fb_stride = info->fix.line_length;
++ }
++
++ base = info->fix.smem_start;
++ fr_xoff = var->xoffset;
++ fr_w = info->var.xres_virtual;
++ if (!(var->vmode & FB_VMODE_YWRAP)) {
++ dev_dbg(info->device, "Y wrap disabled\n");
++ fr_yoff = var->yoffset % info->var.yres;
++ fr_h = info->var.yres;
++ base += info->fix.line_length * info->var.yres *
++ (var->yoffset / info->var.yres);
++ } else {
++ dev_dbg(info->device, "Y wrap enabled\n");
++ fr_yoff = var->yoffset;
++ fr_h = info->var.yres_virtual;
++ }
++ base += fr_yoff * fb_stride + fr_xoff;
++
++ /* Check if DP local alpha is enabled and find the graphic fb */
++ if (mxc_fbi->ipu_ch == MEM_BG_SYNC || mxc_fbi->ipu_ch == MEM_FG_SYNC) {
++ for (i = 0; i < num_registered_fb; i++) {
++ char bg_id[] = "DISP3 BG";
++ char fg_id[] = "DISP3 FG";
++ char *idstr = registered_fb[i]->fix.id;
++ bg_id[4] += mxc_fbi->ipu_id;
++ fg_id[4] += mxc_fbi->ipu_id;
++ if ((strcmp(idstr, bg_id) == 0 ||
++ strcmp(idstr, fg_id) == 0) &&
++ ((struct mxcfb_info *)
++ (registered_fb[i]->par))->alpha_chan_en) {
++ loc_alpha_en = true;
++ mxc_graphic_fbi = (struct mxcfb_info *)
++ (registered_fb[i]->par);
++ active_alpha_phy_addr =
++ mxc_fbi->cur_ipu_alpha_buf ?
++ mxc_graphic_fbi->alpha_phy_addr1 :
++ mxc_graphic_fbi->alpha_phy_addr0;
++ dev_dbg(info->device, "Updating SDC alpha "
++ "buf %d address=0x%08lX\n",
++ !mxc_fbi->cur_ipu_alpha_buf,
++ active_alpha_phy_addr);
++ break;
++ }
++ }
++ }
++
++ ret = wait_for_completion_timeout(&mxc_fbi->flip_complete, HZ/2);
++ if (ret == 0) {
++ dev_err(info->device, "timeout when waiting for flip irq\n");
++ return -ETIMEDOUT;
++ }
++
++ ++mxc_fbi->cur_ipu_buf;
++ mxc_fbi->cur_ipu_buf %= 3;
++ mxc_fbi->cur_ipu_alpha_buf = !mxc_fbi->cur_ipu_alpha_buf;
++
++ dev_dbg(info->device, "Updating SDC %s buf %d address=0x%08lX\n",
++ info->fix.id, mxc_fbi->cur_ipu_buf, base);
++
++ if (ipu_update_channel_buffer(mxc_fbi->ipu, mxc_fbi->ipu_ch, IPU_INPUT_BUFFER,
++ mxc_fbi->cur_ipu_buf, base) == 0) {
++ /* Update the DP local alpha buffer only for graphic plane */
++ if (loc_alpha_en && mxc_graphic_fbi == mxc_fbi &&
++ ipu_update_channel_buffer(mxc_graphic_fbi->ipu, mxc_graphic_fbi->ipu_ch,
++ IPU_ALPHA_IN_BUFFER,
++ mxc_fbi->cur_ipu_alpha_buf,
++ active_alpha_phy_addr) == 0) {
++ ipu_select_buffer(mxc_graphic_fbi->ipu, mxc_graphic_fbi->ipu_ch,
++ IPU_ALPHA_IN_BUFFER,
++ mxc_fbi->cur_ipu_alpha_buf);
++ }
++
++ /* update u/v offset */
++ ipu_update_channel_offset(mxc_fbi->ipu, mxc_fbi->ipu_ch,
++ IPU_INPUT_BUFFER,
++ fbi_to_pixfmt(info),
++ fr_w,
++ fr_h,
++ fr_w,
++ 0, 0,
++ fr_yoff,
++ fr_xoff);
++
++ ipu_select_buffer(mxc_fbi->ipu, mxc_fbi->ipu_ch, IPU_INPUT_BUFFER,
++ mxc_fbi->cur_ipu_buf);
++ ipu_clear_irq(mxc_fbi->ipu, mxc_fbi->ipu_ch_irq);
++ ipu_enable_irq(mxc_fbi->ipu, mxc_fbi->ipu_ch_irq);
++ } else {
++ dev_err(info->device,
++ "Error updating SDC buf %d to address=0x%08lX, "
++ "current buf %d, buf0 ready %d, buf1 ready %d, "
++ "buf2 ready %d\n", mxc_fbi->cur_ipu_buf, base,
++ ipu_get_cur_buffer_idx(mxc_fbi->ipu, mxc_fbi->ipu_ch,
++ IPU_INPUT_BUFFER),
++ ipu_check_buffer_ready(mxc_fbi->ipu, mxc_fbi->ipu_ch,
++ IPU_INPUT_BUFFER, 0),
++ ipu_check_buffer_ready(mxc_fbi->ipu, mxc_fbi->ipu_ch,
++ IPU_INPUT_BUFFER, 1),
++ ipu_check_buffer_ready(mxc_fbi->ipu, mxc_fbi->ipu_ch,
++ IPU_INPUT_BUFFER, 2));
++ ++mxc_fbi->cur_ipu_buf;
++ mxc_fbi->cur_ipu_buf %= 3;
++ ++mxc_fbi->cur_ipu_buf;
++ mxc_fbi->cur_ipu_buf %= 3;
++ mxc_fbi->cur_ipu_alpha_buf = !mxc_fbi->cur_ipu_alpha_buf;
++ ipu_clear_irq(mxc_fbi->ipu, mxc_fbi->ipu_ch_irq);
++ ipu_enable_irq(mxc_fbi->ipu, mxc_fbi->ipu_ch_irq);
++ return -EBUSY;
++ }
++
++ dev_dbg(info->device, "Update complete\n");
++
++ info->var.yoffset = var->yoffset;
++
++ return 0;
++}
++
++/*
++ * Function to handle custom mmap for MXC framebuffer.
++ *
++ * @param fbi framebuffer information pointer
++ *
++ * @param vma Pointer to vm_area_struct
++ */
++static int mxcfb_mmap(struct fb_info *fbi, struct vm_area_struct *vma)
++{
++ bool found = false;
++ u32 len;
++ unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
++ struct mxcfb_alloc_list *mem;
++ struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par;
++
++ if (offset < fbi->fix.smem_len) {
++ /* mapping framebuffer memory */
++ len = fbi->fix.smem_len - offset;
++ vma->vm_pgoff = (fbi->fix.smem_start + offset) >> PAGE_SHIFT;
++ } else if ((vma->vm_pgoff ==
++ (mxc_fbi->alpha_phy_addr0 >> PAGE_SHIFT)) ||
++ (vma->vm_pgoff ==
++ (mxc_fbi->alpha_phy_addr1 >> PAGE_SHIFT))) {
++ len = mxc_fbi->alpha_mem_len;
++ } else {
++ list_for_each_entry(mem, &fb_alloc_list, list) {
++ if (offset == mem->phy_addr) {
++ found = true;
++ len = mem->size;
++ break;
++ }
++ }
++ if (!found)
++ return -EINVAL;
++ }
++
++ len = PAGE_ALIGN(len);
++ if (vma->vm_end - vma->vm_start > len)
++ return -EINVAL;
++
++ /* make buffers bufferable */
++ vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
++
++ vma->vm_flags |= VM_IO;
++
++ if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
++ vma->vm_end - vma->vm_start, vma->vm_page_prot)) {
++ dev_dbg(fbi->device, "mmap remap_pfn_range failed\n");
++ return -ENOBUFS;
++ }
++
++ return 0;
++}
++
++/*!
++ * This structure contains the pointers to the control functions that are
++ * invoked by the core framebuffer driver to perform operations like
++ * blitting, rectangle filling, copy regions and cursor definition.
++ */
++static struct fb_ops mxcfb_ops = {
++ .owner = THIS_MODULE,
++ .fb_set_par = mxcfb_set_par,
++ .fb_check_var = mxcfb_check_var,
++ .fb_setcolreg = mxcfb_setcolreg,
++ .fb_pan_display = mxcfb_pan_display,
++ .fb_ioctl = mxcfb_ioctl,
++ .fb_mmap = mxcfb_mmap,
++ .fb_fillrect = cfb_fillrect,
++ .fb_copyarea = cfb_copyarea,
++ .fb_imageblit = cfb_imageblit,
++ .fb_blank = mxcfb_blank,
++};
++
++static irqreturn_t mxcfb_irq_handler(int irq, void *dev_id)
++{
++ struct fb_info *fbi = dev_id;
++ struct mxcfb_info *mxc_fbi = fbi->par;
++
++ complete(&mxc_fbi->flip_complete);
++ return IRQ_HANDLED;
++}
++
++static irqreturn_t mxcfb_nf_irq_handler(int irq, void *dev_id)
++{
++ struct fb_info *fbi = dev_id;
++ struct mxcfb_info *mxc_fbi = fbi->par;
++
++ complete(&mxc_fbi->vsync_complete);
++ return IRQ_HANDLED;
++}
++
++static irqreturn_t mxcfb_alpha_irq_handler(int irq, void *dev_id)
++{
++ struct fb_info *fbi = dev_id;
++ struct mxcfb_info *mxc_fbi = fbi->par;
++
++ complete(&mxc_fbi->alpha_flip_complete);
++ return IRQ_HANDLED;
++}
++
++/*
++ * Suspends the framebuffer and blanks the screen. Power management support
++ */
++static int mxcfb_suspend(struct platform_device *pdev, pm_message_t state)
++{
++ struct fb_info *fbi = platform_get_drvdata(pdev);
++ struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par;
++ int saved_blank;
++#ifdef CONFIG_FB_MXC_LOW_PWR_DISPLAY
++ void *fbmem;
++#endif
++
++ if (mxc_fbi->ovfbi) {
++ struct mxcfb_info *mxc_fbi_fg =
++ (struct mxcfb_info *)mxc_fbi->ovfbi->par;
++
++ console_lock();
++ fb_set_suspend(mxc_fbi->ovfbi, 1);
++ saved_blank = mxc_fbi_fg->cur_blank;
++ mxcfb_blank(FB_BLANK_POWERDOWN, mxc_fbi->ovfbi);
++ mxc_fbi_fg->next_blank = saved_blank;
++ console_unlock();
++ }
++
++ console_lock();
++ fb_set_suspend(fbi, 1);
++ saved_blank = mxc_fbi->cur_blank;
++ mxcfb_blank(FB_BLANK_POWERDOWN, fbi);
++ mxc_fbi->next_blank = saved_blank;
++ console_unlock();
++
++ return 0;
++}
++
++/*
++ * Resumes the framebuffer and unblanks the screen. Power management support
++ */
++static int mxcfb_resume(struct platform_device *pdev)
++{
++ struct fb_info *fbi = platform_get_drvdata(pdev);
++ struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par;
++
++ console_lock();
++ mxcfb_blank(mxc_fbi->next_blank, fbi);
++ fb_set_suspend(fbi, 0);
++ console_unlock();
++
++ if (mxc_fbi->ovfbi) {
++ struct mxcfb_info *mxc_fbi_fg =
++ (struct mxcfb_info *)mxc_fbi->ovfbi->par;
++ console_lock();
++ mxcfb_blank(mxc_fbi_fg->next_blank, mxc_fbi->ovfbi);
++ fb_set_suspend(mxc_fbi->ovfbi, 0);
++ console_unlock();
++ }
++
++ return 0;
++}
++
++/*
++ * Main framebuffer functions
++ */
++
++/*!
++ * Allocates the DRAM memory for the frame buffer. This buffer is remapped
++ * into a non-cached, non-buffered, memory region to allow palette and pixel
++ * writes to occur without flushing the cache. Once this area is remapped,
++ * all virtual memory access to the video memory should occur at the new region.
++ *
++ * @param fbi framebuffer information pointer
++ *
++ * @return Error code indicating success or failure
++ */
++static int mxcfb_map_video_memory(struct fb_info *fbi)
++{
++ if (fbi->fix.smem_len < fbi->var.yres_virtual * fbi->fix.line_length)
++ fbi->fix.smem_len = fbi->var.yres_virtual *
++ fbi->fix.line_length;
++
++ fbi->screen_base = dma_alloc_writecombine(fbi->device,
++ fbi->fix.smem_len,
++ (dma_addr_t *)&fbi->fix.smem_start,
++ GFP_DMA | GFP_KERNEL);
++ if (fbi->screen_base == 0) {
++ dev_err(fbi->device, "Unable to allocate framebuffer memory\n");
++ fbi->fix.smem_len = 0;
++ fbi->fix.smem_start = 0;
++ return -EBUSY;
++ }
++
++ dev_dbg(fbi->device, "allocated fb @ paddr=0x%08X, size=%d.\n",
++ (uint32_t) fbi->fix.smem_start, fbi->fix.smem_len);
++
++ fbi->screen_size = fbi->fix.smem_len;
++
++ /* Clear the screen */
++ memset((char *)fbi->screen_base, 0, fbi->fix.smem_len);
++
++ return 0;
++}
++
++/*!
++ * De-allocates the DRAM memory for the frame buffer.
++ *
++ * @param fbi framebuffer information pointer
++ *
++ * @return Error code indicating success or failure
++ */
++static int mxcfb_unmap_video_memory(struct fb_info *fbi)
++{
++ dma_free_writecombine(fbi->device, fbi->fix.smem_len,
++ fbi->screen_base, fbi->fix.smem_start);
++ fbi->screen_base = 0;
++ fbi->fix.smem_start = 0;
++ fbi->fix.smem_len = 0;
++ return 0;
++}
++
++/*!
++ * Initializes the framebuffer information pointer. After allocating
++ * sufficient memory for the framebuffer structure, the fields are
++ * filled with custom information passed in from the configurable
++ * structures. This includes information such as bits per pixel,
++ * color maps, screen width/height and RGBA offsets.
++ *
++ * @return Framebuffer structure initialized with our information
++ */
++static struct fb_info *mxcfb_init_fbinfo(struct device *dev, struct fb_ops *ops)
++{
++ struct fb_info *fbi;
++ struct mxcfb_info *mxcfbi;
++
++ /*
++ * Allocate sufficient memory for the fb structure
++ */
++ fbi = framebuffer_alloc(sizeof(struct mxcfb_info), dev);
++ if (!fbi)
++ return NULL;
++
++ mxcfbi = (struct mxcfb_info *)fbi->par;
++
++ fbi->var.activate = FB_ACTIVATE_NOW;
++
++ fbi->fbops = ops;
++ fbi->flags = FBINFO_FLAG_DEFAULT;
++ fbi->pseudo_palette = mxcfbi->pseudo_palette;
++
++ /*
++ * Allocate colormap
++ */
++ fb_alloc_cmap(&fbi->cmap, 16, 0);
++
++ return fbi;
++}
++
++static ssize_t show_disp_chan(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct fb_info *info = dev_get_drvdata(dev);
++ struct mxcfb_info *mxcfbi = (struct mxcfb_info *)info->par;
++
++ if (mxcfbi->ipu_ch == MEM_BG_SYNC)
++ return sprintf(buf, "2-layer-fb-bg\n");
++ else if (mxcfbi->ipu_ch == MEM_FG_SYNC)
++ return sprintf(buf, "2-layer-fb-fg\n");
++ else if (mxcfbi->ipu_ch == MEM_DC_SYNC)
++ return sprintf(buf, "1-layer-fb\n");
++ else
++ return sprintf(buf, "err: no display chan\n");
++}
++
++static ssize_t swap_disp_chan(struct device *dev,
++ struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ struct fb_info *info = dev_get_drvdata(dev);
++ struct mxcfb_info *mxcfbi = (struct mxcfb_info *)info->par;
++ struct mxcfb_info *fg_mxcfbi = NULL;
++
++ console_lock();
++ /* swap only happen between DP-BG and DC, while DP-FG disable */
++ if (((mxcfbi->ipu_ch == MEM_BG_SYNC) &&
++ (strstr(buf, "1-layer-fb") != NULL)) ||
++ ((mxcfbi->ipu_ch == MEM_DC_SYNC) &&
++ (strstr(buf, "2-layer-fb-bg") != NULL))) {
++ struct fb_info *fbi_fg;
++
++ fbi_fg = found_registered_fb(MEM_FG_SYNC, mxcfbi->ipu_id);
++ if (fbi_fg)
++ fg_mxcfbi = (struct mxcfb_info *)fbi_fg->par;
++
++ if (!fg_mxcfbi ||
++ fg_mxcfbi->cur_blank == FB_BLANK_UNBLANK) {
++ dev_err(dev,
++ "Can not switch while fb2(fb-fg) is on.\n");
++ console_unlock();
++ return count;
++ }
++
++ if (swap_channels(info) < 0)
++ dev_err(dev, "Swap display channel failed.\n");
++ }
++
++ console_unlock();
++ return count;
++}
++static DEVICE_ATTR(fsl_disp_property, S_IWUSR | S_IRUGO,
++ show_disp_chan, swap_disp_chan);
++
++static ssize_t show_disp_dev(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct fb_info *info = dev_get_drvdata(dev);
++ struct mxcfb_info *mxcfbi = (struct mxcfb_info *)info->par;
++
++ if (mxcfbi->ipu_ch == MEM_FG_SYNC)
++ return sprintf(buf, "overlay\n");
++ else
++ return sprintf(buf, "%s\n", mxcfbi->dispdrv->drv->name);
++}
++static DEVICE_ATTR(fsl_disp_dev_property, S_IRUGO, show_disp_dev, NULL);
++
++static int mxcfb_dispdrv_init(struct platform_device *pdev,
++ struct fb_info *fbi)
++{
++ struct ipuv3_fb_platform_data *plat_data = pdev->dev.platform_data;
++ struct mxcfb_info *mxcfbi = (struct mxcfb_info *)fbi->par;
++ struct mxc_dispdrv_setting setting;
++ char disp_dev[32], *default_dev = "lcd";
++ int ret = 0;
++
++ setting.if_fmt = plat_data->interface_pix_fmt;
++ setting.dft_mode_str = plat_data->mode_str;
++ setting.default_bpp = plat_data->default_bpp;
++ if (!setting.default_bpp)
++ setting.default_bpp = 16;
++ setting.fbi = fbi;
++ if (!strlen(plat_data->disp_dev)) {
++ memcpy(disp_dev, default_dev, strlen(default_dev));
++ disp_dev[strlen(default_dev)] = '\0';
++ } else {
++ memcpy(disp_dev, plat_data->disp_dev,
++ strlen(plat_data->disp_dev));
++ disp_dev[strlen(plat_data->disp_dev)] = '\0';
++ }
++
++ dev_info(&pdev->dev, "register mxc display driver %s\n", disp_dev);
++
++ mxcfbi->dispdrv = mxc_dispdrv_gethandle(disp_dev, &setting);
++ if (IS_ERR(mxcfbi->dispdrv)) {
++ ret = PTR_ERR(mxcfbi->dispdrv);
++ dev_err(&pdev->dev, "NO mxc display driver found!\n");
++ return ret;
++ } else {
++ /* fix-up */
++ mxcfbi->ipu_di_pix_fmt = setting.if_fmt;
++ mxcfbi->default_bpp = setting.default_bpp;
++
++ /* setting */
++ mxcfbi->ipu_id = setting.dev_id;
++ mxcfbi->ipu_di = setting.disp_id;
++ dev_dbg(&pdev->dev, "di_pixfmt:0x%x, bpp:0x%x, di:%d, ipu:%d\n",
++ setting.if_fmt, setting.default_bpp,
++ setting.disp_id, setting.dev_id);
++ }
++
++ return ret;
++}
++
++/*
++ * Parse user specified options (`video=trident:')
++ * example:
++ * video=mxcfb0:dev=lcd,800x480M-16@55,if=RGB565,bpp=16,noaccel
++ * video=mxcfb0:dev=lcd,800x480M-16@55,if=RGB565,fbpix=RGB565
++ */
++static int mxcfb_option_setup(struct platform_device *pdev, struct fb_info *fbi)
++{
++ struct ipuv3_fb_platform_data *pdata = pdev->dev.platform_data;
++ char *options, *opt, *fb_mode_str = NULL;
++ char name[] = "mxcfb0";
++ uint32_t fb_pix_fmt = 0;
++
++ name[5] += pdev->id;
++ if (fb_get_options(name, &options)) {
++ dev_err(&pdev->dev, "Can't get fb option for %s!\n", name);
++ return -ENODEV;
++ }
++
++ if (!options || !*options)
++ return 0;
++
++ while ((opt = strsep(&options, ",")) != NULL) {
++ if (!*opt)
++ continue;
++
++ if (!strncmp(opt, "dev=", 4)) {
++ memcpy(pdata->disp_dev, opt + 4, strlen(opt) - 4);
++ pdata->disp_dev[strlen(opt) - 4] = '\0';
++ } else if (!strncmp(opt, "if=", 3)) {
++ if (!strncmp(opt+3, "RGB24", 5))
++ pdata->interface_pix_fmt = IPU_PIX_FMT_RGB24;
++ else if (!strncmp(opt+3, "BGR24", 5))
++ pdata->interface_pix_fmt = IPU_PIX_FMT_BGR24;
++ else if (!strncmp(opt+3, "GBR24", 5))
++ pdata->interface_pix_fmt = IPU_PIX_FMT_GBR24;
++ else if (!strncmp(opt+3, "RGB565", 6))
++ pdata->interface_pix_fmt = IPU_PIX_FMT_RGB565;
++ else if (!strncmp(opt+3, "RGB666", 6))
++ pdata->interface_pix_fmt = IPU_PIX_FMT_RGB666;
++ else if (!strncmp(opt+3, "YUV444", 6))
++ pdata->interface_pix_fmt = IPU_PIX_FMT_YUV444;
++ else if (!strncmp(opt+3, "LVDS666", 7))
++ pdata->interface_pix_fmt = IPU_PIX_FMT_LVDS666;
++ else if (!strncmp(opt+3, "YUYV16", 6))
++ pdata->interface_pix_fmt = IPU_PIX_FMT_YUYV;
++ else if (!strncmp(opt+3, "UYVY16", 6))
++ pdata->interface_pix_fmt = IPU_PIX_FMT_UYVY;
++ else if (!strncmp(opt+3, "YVYU16", 6))
++ pdata->interface_pix_fmt = IPU_PIX_FMT_YVYU;
++ else if (!strncmp(opt+3, "VYUY16", 6))
++ pdata->interface_pix_fmt = IPU_PIX_FMT_VYUY;
++ } else if (!strncmp(opt, "fbpix=", 6)) {
++ if (!strncmp(opt+6, "RGB24", 5))
++ fb_pix_fmt = IPU_PIX_FMT_RGB24;
++ else if (!strncmp(opt+6, "BGR24", 5))
++ fb_pix_fmt = IPU_PIX_FMT_BGR24;
++ else if (!strncmp(opt+6, "RGB32", 5))
++ fb_pix_fmt = IPU_PIX_FMT_RGB32;
++ else if (!strncmp(opt+6, "BGR32", 5))
++ fb_pix_fmt = IPU_PIX_FMT_BGR32;
++ else if (!strncmp(opt+6, "ABGR32", 6))
++ fb_pix_fmt = IPU_PIX_FMT_ABGR32;
++ else if (!strncmp(opt+6, "RGB565", 6))
++ fb_pix_fmt = IPU_PIX_FMT_RGB565;
++
++ if (fb_pix_fmt) {
++ pixfmt_to_var(fb_pix_fmt, &fbi->var);
++ pdata->default_bpp =
++ fbi->var.bits_per_pixel;
++ }
++ } else if (!strncmp(opt, "int_clk", 7)) {
++ pdata->int_clk = true;
++ continue;
++ } else if (!strncmp(opt, "bpp=", 4)) {
++ /* bpp setting cannot overwirte fbpix setting */
++ if (fb_pix_fmt)
++ continue;
++
++ pdata->default_bpp =
++ simple_strtoul(opt + 4, NULL, 0);
++
++ fb_pix_fmt = bpp_to_pixfmt(pdata->default_bpp);
++ if (fb_pix_fmt)
++ pixfmt_to_var(fb_pix_fmt, &fbi->var);
++ } else
++ fb_mode_str = opt;
++ }
++
++ if (fb_mode_str)
++ pdata->mode_str = fb_mode_str;
++
++ return 0;
++}
++
++static int mxcfb_register(struct fb_info *fbi)
++{
++ struct mxcfb_info *mxcfbi = (struct mxcfb_info *)fbi->par;
++ struct fb_videomode m;
++ int ret = 0;
++ char bg0_id[] = "DISP3 BG";
++ char bg1_id[] = "DISP3 BG - DI1";
++ char fg_id[] = "DISP3 FG";
++
++ if (mxcfbi->ipu_di == 0) {
++ bg0_id[4] += mxcfbi->ipu_id;
++ strcpy(fbi->fix.id, bg0_id);
++ } else if (mxcfbi->ipu_di == 1) {
++ bg1_id[4] += mxcfbi->ipu_id;
++ strcpy(fbi->fix.id, bg1_id);
++ } else { /* Overlay */
++ fg_id[4] += mxcfbi->ipu_id;
++ strcpy(fbi->fix.id, fg_id);
++ }
++
++ mxcfb_check_var(&fbi->var, fbi);
++
++ mxcfb_set_fix(fbi);
++
++ /* Added first mode to fbi modelist. */
++ if (!fbi->modelist.next || !fbi->modelist.prev)
++ INIT_LIST_HEAD(&fbi->modelist);
++ fb_var_to_videomode(&m, &fbi->var);
++ fb_add_videomode(&m, &fbi->modelist);
++
++ if (ipu_request_irq(mxcfbi->ipu, mxcfbi->ipu_ch_irq,
++ mxcfb_irq_handler, IPU_IRQF_ONESHOT, MXCFB_NAME, fbi) != 0) {
++ dev_err(fbi->device, "Error registering EOF irq handler.\n");
++ ret = -EBUSY;
++ goto err0;
++ }
++ ipu_disable_irq(mxcfbi->ipu, mxcfbi->ipu_ch_irq);
++ if (ipu_request_irq(mxcfbi->ipu, mxcfbi->ipu_ch_nf_irq,
++ mxcfb_nf_irq_handler, IPU_IRQF_ONESHOT, MXCFB_NAME, fbi) != 0) {
++ dev_err(fbi->device, "Error registering NFACK irq handler.\n");
++ ret = -EBUSY;
++ goto err1;
++ }
++ ipu_disable_irq(mxcfbi->ipu, mxcfbi->ipu_ch_nf_irq);
++
++ if (mxcfbi->ipu_alp_ch_irq != -1)
++ if (ipu_request_irq(mxcfbi->ipu, mxcfbi->ipu_alp_ch_irq,
++ mxcfb_alpha_irq_handler, IPU_IRQF_ONESHOT,
++ MXCFB_NAME, fbi) != 0) {
++ dev_err(fbi->device, "Error registering alpha irq "
++ "handler.\n");
++ ret = -EBUSY;
++ goto err2;
++ }
++
++ if (!mxcfbi->late_init) {
++ fbi->var.activate |= FB_ACTIVATE_FORCE;
++ console_lock();
++ fbi->flags |= FBINFO_MISC_USEREVENT;
++ ret = fb_set_var(fbi, &fbi->var);
++ fbi->flags &= ~FBINFO_MISC_USEREVENT;
++ console_unlock();
++ if (ret < 0) {
++ dev_err(fbi->device, "Error fb_set_var ret:%d\n", ret);
++ goto err3;
++ }
++
++ if (mxcfbi->next_blank == FB_BLANK_UNBLANK) {
++ console_lock();
++ ret = fb_blank(fbi, FB_BLANK_UNBLANK);
++ console_unlock();
++ if (ret < 0) {
++ dev_err(fbi->device,
++ "Error fb_blank ret:%d\n", ret);
++ goto err4;
++ }
++ }
++ } else {
++ /*
++ * Setup the channel again though bootloader
++ * has done this, then set_par() can stop the
++ * channel neatly and re-initialize it .
++ */
++ if (mxcfbi->next_blank == FB_BLANK_UNBLANK) {
++ console_lock();
++ _setup_disp_channel1(fbi);
++ ipu_enable_channel(mxcfbi->ipu, mxcfbi->ipu_ch);
++ console_unlock();
++ }
++ }
++
++
++ ret = register_framebuffer(fbi);
++ if (ret < 0)
++ goto err5;
++
++ return ret;
++err5:
++ if (mxcfbi->next_blank == FB_BLANK_UNBLANK) {
++ console_lock();
++ if (!mxcfbi->late_init)
++ fb_blank(fbi, FB_BLANK_POWERDOWN);
++ else {
++ ipu_disable_channel(mxcfbi->ipu, mxcfbi->ipu_ch,
++ true);
++ ipu_uninit_channel(mxcfbi->ipu, mxcfbi->ipu_ch);
++ }
++ console_unlock();
++ }
++err4:
++err3:
++ if (mxcfbi->ipu_alp_ch_irq != -1)
++ ipu_free_irq(mxcfbi->ipu, mxcfbi->ipu_alp_ch_irq, fbi);
++err2:
++ ipu_free_irq(mxcfbi->ipu, mxcfbi->ipu_ch_nf_irq, fbi);
++err1:
++ ipu_free_irq(mxcfbi->ipu, mxcfbi->ipu_ch_irq, fbi);
++err0:
++ return ret;
++}
++
++static void mxcfb_unregister(struct fb_info *fbi)
++{
++ struct mxcfb_info *mxcfbi = (struct mxcfb_info *)fbi->par;
++
++ if (mxcfbi->ipu_alp_ch_irq != -1)
++ ipu_free_irq(mxcfbi->ipu, mxcfbi->ipu_alp_ch_irq, fbi);
++ if (mxcfbi->ipu_ch_irq)
++ ipu_free_irq(mxcfbi->ipu, mxcfbi->ipu_ch_irq, fbi);
++ if (mxcfbi->ipu_ch_nf_irq)
++ ipu_free_irq(mxcfbi->ipu, mxcfbi->ipu_ch_nf_irq, fbi);
++
++ unregister_framebuffer(fbi);
++}
++
++static int mxcfb_setup_overlay(struct platform_device *pdev,
++ struct fb_info *fbi_bg, struct resource *res)
++{
++ struct fb_info *ovfbi;
++ struct mxcfb_info *mxcfbi_bg = (struct mxcfb_info *)fbi_bg->par;
++ struct mxcfb_info *mxcfbi_fg;
++ int ret = 0;
++
++ ovfbi = mxcfb_init_fbinfo(&pdev->dev, &mxcfb_ops);
++ if (!ovfbi) {
++ ret = -ENOMEM;
++ goto init_ovfbinfo_failed;
++ }
++ mxcfbi_fg = (struct mxcfb_info *)ovfbi->par;
++
++ mxcfbi_fg->ipu = ipu_get_soc(mxcfbi_bg->ipu_id);
++ if (IS_ERR(mxcfbi_fg->ipu)) {
++ ret = -ENODEV;
++ goto get_ipu_failed;
++ }
++ mxcfbi_fg->ipu_id = mxcfbi_bg->ipu_id;
++ mxcfbi_fg->ipu_ch_irq = IPU_IRQ_FG_SYNC_EOF;
++ mxcfbi_fg->ipu_ch_nf_irq = IPU_IRQ_FG_SYNC_NFACK;
++ mxcfbi_fg->ipu_alp_ch_irq = IPU_IRQ_FG_ALPHA_SYNC_EOF;
++ mxcfbi_fg->ipu_ch = MEM_FG_SYNC;
++ mxcfbi_fg->ipu_di = -1;
++ mxcfbi_fg->ipu_di_pix_fmt = mxcfbi_bg->ipu_di_pix_fmt;
++ mxcfbi_fg->overlay = true;
++ mxcfbi_fg->cur_blank = mxcfbi_fg->next_blank = FB_BLANK_POWERDOWN;
++
++ /* Need dummy values until real panel is configured */
++ ovfbi->var.xres = 240;
++ ovfbi->var.yres = 320;
++
++ if (res && res->start && res->end) {
++ ovfbi->fix.smem_len = res->end - res->start + 1;
++ ovfbi->fix.smem_start = res->start;
++ ovfbi->screen_base = ioremap(
++ ovfbi->fix.smem_start,
++ ovfbi->fix.smem_len);
++ }
++
++ ret = mxcfb_register(ovfbi);
++ if (ret < 0)
++ goto register_ov_failed;
++
++ mxcfbi_bg->ovfbi = ovfbi;
++
++ return ret;
++
++register_ov_failed:
++get_ipu_failed:
++ fb_dealloc_cmap(&ovfbi->cmap);
++ framebuffer_release(ovfbi);
++init_ovfbinfo_failed:
++ return ret;
++}
++
++static void mxcfb_unsetup_overlay(struct fb_info *fbi_bg)
++{
++ struct mxcfb_info *mxcfbi_bg = (struct mxcfb_info *)fbi_bg->par;
++ struct fb_info *ovfbi = mxcfbi_bg->ovfbi;
++
++ mxcfb_unregister(ovfbi);
++
++ if (&ovfbi->cmap)
++ fb_dealloc_cmap(&ovfbi->cmap);
++ framebuffer_release(ovfbi);
++}
++
++static bool ipu_usage[2][2];
++static int ipu_test_set_usage(int ipu, int di)
++{
++ if (ipu_usage[ipu][di])
++ return -EBUSY;
++ else
++ ipu_usage[ipu][di] = true;
++ return 0;
++}
++
++static void ipu_clear_usage(int ipu, int di)
++{
++ ipu_usage[ipu][di] = false;
++}
++
++static int mxcfb_get_of_property(struct platform_device *pdev,
++ struct ipuv3_fb_platform_data *plat_data)
++{
++ struct device_node *np = pdev->dev.of_node;
++ const char *disp_dev;
++ const char *mode_str;
++ const char *pixfmt;
++ int err;
++ int len;
++ u32 bpp, int_clk;
++ u32 late_init;
++
++ err = of_property_read_string(np, "disp_dev", &disp_dev);
++ if (err < 0) {
++ dev_dbg(&pdev->dev, "get of property disp_dev fail\n");
++ return err;
++ }
++ err = of_property_read_string(np, "mode_str", &mode_str);
++ if (err < 0) {
++ dev_dbg(&pdev->dev, "get of property mode_str fail\n");
++ return err;
++ }
++ err = of_property_read_string(np, "interface_pix_fmt", &pixfmt);
++ if (err) {
++ dev_dbg(&pdev->dev, "get of property pix fmt fail\n");
++ return err;
++ }
++ err = of_property_read_u32(np, "default_bpp", &bpp);
++ if (err) {
++ dev_dbg(&pdev->dev, "get of property bpp fail\n");
++ return err;
++ }
++ err = of_property_read_u32(np, "int_clk", &int_clk);
++ if (err) {
++ dev_dbg(&pdev->dev, "get of property int_clk fail\n");
++ return err;
++ }
++ err = of_property_read_u32(np, "late_init", &late_init);
++ if (err) {
++ dev_dbg(&pdev->dev, "get of property late_init fail\n");
++ return err;
++ }
++
++ if (!strncmp(pixfmt, "RGB24", 5))
++ plat_data->interface_pix_fmt = IPU_PIX_FMT_RGB24;
++ else if (!strncmp(pixfmt, "BGR24", 5))
++ plat_data->interface_pix_fmt = IPU_PIX_FMT_BGR24;
++ else if (!strncmp(pixfmt, "GBR24", 5))
++ plat_data->interface_pix_fmt = IPU_PIX_FMT_GBR24;
++ else if (!strncmp(pixfmt, "RGB565", 6))
++ plat_data->interface_pix_fmt = IPU_PIX_FMT_RGB565;
++ else if (!strncmp(pixfmt, "RGB666", 6))
++ plat_data->interface_pix_fmt = IPU_PIX_FMT_RGB666;
++ else if (!strncmp(pixfmt, "YUV444", 6))
++ plat_data->interface_pix_fmt = IPU_PIX_FMT_YUV444;
++ else if (!strncmp(pixfmt, "LVDS666", 7))
++ plat_data->interface_pix_fmt = IPU_PIX_FMT_LVDS666;
++ else if (!strncmp(pixfmt, "YUYV16", 6))
++ plat_data->interface_pix_fmt = IPU_PIX_FMT_YUYV;
++ else if (!strncmp(pixfmt, "UYVY16", 6))
++ plat_data->interface_pix_fmt = IPU_PIX_FMT_UYVY;
++ else if (!strncmp(pixfmt, "YVYU16", 6))
++ plat_data->interface_pix_fmt = IPU_PIX_FMT_YVYU;
++ else if (!strncmp(pixfmt, "VYUY16", 6))
++ plat_data->interface_pix_fmt = IPU_PIX_FMT_VYUY;
++ else {
++ dev_err(&pdev->dev, "err interface_pix_fmt!\n");
++ return -ENOENT;
++ }
++
++ len = min(sizeof(plat_data->disp_dev) - 1, strlen(disp_dev));
++ memcpy(plat_data->disp_dev, disp_dev, len);
++ plat_data->disp_dev[len] = '\0';
++ plat_data->mode_str = (char *)mode_str;
++ plat_data->default_bpp = bpp;
++ plat_data->int_clk = (bool)int_clk;
++ plat_data->late_init = (bool)late_init;
++ return err;
++}
++
++/*!
++ * Probe routine for the framebuffer driver. It is called during the
++ * driver binding process. The following functions are performed in
++ * this routine: Framebuffer initialization, Memory allocation and
++ * mapping, Framebuffer registration, IPU initialization.
++ *
++ * @return Appropriate error code to the kernel common code
++ */
++static int mxcfb_probe(struct platform_device *pdev)
++{
++ struct ipuv3_fb_platform_data *plat_data;
++ struct fb_info *fbi;
++ struct mxcfb_info *mxcfbi;
++ struct resource *res;
++ int ret = 0;
++
++ dev_dbg(&pdev->dev, "%s enter\n", __func__);
++ pdev->id = of_alias_get_id(pdev->dev.of_node, "mxcfb");
++ if (pdev->id < 0) {
++ dev_err(&pdev->dev, "can not get alias id\n");
++ return pdev->id;
++ }
++
++ plat_data = devm_kzalloc(&pdev->dev, sizeof(struct
++ ipuv3_fb_platform_data), GFP_KERNEL);
++ if (!plat_data)
++ return -ENOMEM;
++ pdev->dev.platform_data = plat_data;
++
++ ret = mxcfb_get_of_property(pdev, plat_data);
++ if (ret < 0) {
++ dev_err(&pdev->dev, "get mxcfb of property fail\n");
++ return ret;
++ }
++
++ /* Initialize FB structures */
++ fbi = mxcfb_init_fbinfo(&pdev->dev, &mxcfb_ops);
++ if (!fbi) {
++ ret = -ENOMEM;
++ goto init_fbinfo_failed;
++ }
++
++ ret = mxcfb_option_setup(pdev, fbi);
++ if (ret)
++ goto get_fb_option_failed;
++
++ mxcfbi = (struct mxcfb_info *)fbi->par;
++ mxcfbi->ipu_int_clk = plat_data->int_clk;
++ mxcfbi->late_init = plat_data->late_init;
++ mxcfbi->first_set_par = true;
++ ret = mxcfb_dispdrv_init(pdev, fbi);
++ if (ret < 0)
++ goto init_dispdrv_failed;
++
++ ret = ipu_test_set_usage(mxcfbi->ipu_id, mxcfbi->ipu_di);
++ if (ret < 0) {
++ dev_err(&pdev->dev, "ipu%d-di%d already in use\n",
++ mxcfbi->ipu_id, mxcfbi->ipu_di);
++ goto ipu_in_busy;
++ }
++
++ if (mxcfbi->dispdrv->drv->post_init) {
++ ret = mxcfbi->dispdrv->drv->post_init(mxcfbi->dispdrv,
++ mxcfbi->ipu_id,
++ mxcfbi->ipu_di);
++ if (ret < 0) {
++ dev_err(&pdev->dev, "post init failed\n");
++ goto post_init_failed;
++ }
++ }
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (res && res->start && res->end) {
++ fbi->fix.smem_len = res->end - res->start + 1;
++ fbi->fix.smem_start = res->start;
++ fbi->screen_base = ioremap(fbi->fix.smem_start, fbi->fix.smem_len);
++ /* Do not clear the fb content drawn in bootloader. */
++ if (!mxcfbi->late_init)
++ memset(fbi->screen_base, 0, fbi->fix.smem_len);
++ }
++
++ mxcfbi->ipu = ipu_get_soc(mxcfbi->ipu_id);
++ if (IS_ERR(mxcfbi->ipu)) {
++ ret = -ENODEV;
++ goto get_ipu_failed;
++ }
++
++ /* first user uses DP with alpha feature */
++ if (!g_dp_in_use[mxcfbi->ipu_id]) {
++ mxcfbi->ipu_ch_irq = IPU_IRQ_BG_SYNC_EOF;
++ mxcfbi->ipu_ch_nf_irq = IPU_IRQ_BG_SYNC_NFACK;
++ mxcfbi->ipu_alp_ch_irq = IPU_IRQ_BG_ALPHA_SYNC_EOF;
++ mxcfbi->ipu_ch = MEM_BG_SYNC;
++ /* Unblank the primary fb only by default */
++ if (pdev->id == 0)
++ mxcfbi->cur_blank = mxcfbi->next_blank = FB_BLANK_UNBLANK;
++ else
++ mxcfbi->cur_blank = mxcfbi->next_blank = FB_BLANK_POWERDOWN;
++
++ ret = mxcfb_register(fbi);
++ if (ret < 0)
++ goto mxcfb_register_failed;
++
++ ipu_disp_set_global_alpha(mxcfbi->ipu, mxcfbi->ipu_ch,
++ true, 0x80);
++ ipu_disp_set_color_key(mxcfbi->ipu, mxcfbi->ipu_ch, false, 0);
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
++ ret = mxcfb_setup_overlay(pdev, fbi, res);
++
++ if (ret < 0) {
++ mxcfb_unregister(fbi);
++ goto mxcfb_setupoverlay_failed;
++ }
++
++ g_dp_in_use[mxcfbi->ipu_id] = true;
++
++ ret = device_create_file(mxcfbi->ovfbi->dev,
++ &dev_attr_fsl_disp_property);
++ if (ret)
++ dev_err(mxcfbi->ovfbi->dev, "Error %d on creating "
++ "file for disp property\n",
++ ret);
++
++ ret = device_create_file(mxcfbi->ovfbi->dev,
++ &dev_attr_fsl_disp_dev_property);
++ if (ret)
++ dev_err(mxcfbi->ovfbi->dev, "Error %d on creating "
++ "file for disp device "
++ "propety\n", ret);
++ } else {
++ mxcfbi->ipu_ch_irq = IPU_IRQ_DC_SYNC_EOF;
++ mxcfbi->ipu_ch_nf_irq = IPU_IRQ_DC_SYNC_NFACK;
++ mxcfbi->ipu_alp_ch_irq = -1;
++ mxcfbi->ipu_ch = MEM_DC_SYNC;
++ mxcfbi->cur_blank = mxcfbi->next_blank = FB_BLANK_POWERDOWN;
++
++ ret = mxcfb_register(fbi);
++ if (ret < 0)
++ goto mxcfb_register_failed;
++ }
++
++ platform_set_drvdata(pdev, fbi);
++
++ ret = device_create_file(fbi->dev, &dev_attr_fsl_disp_property);
++ if (ret)
++ dev_err(&pdev->dev, "Error %d on creating file for disp "
++ "property\n", ret);
++
++ ret = device_create_file(fbi->dev, &dev_attr_fsl_disp_dev_property);
++ if (ret)
++ dev_err(&pdev->dev, "Error %d on creating file for disp "
++ " device propety\n", ret);
++
++ return 0;
++
++mxcfb_setupoverlay_failed:
++mxcfb_register_failed:
++get_ipu_failed:
++post_init_failed:
++ ipu_clear_usage(mxcfbi->ipu_id, mxcfbi->ipu_di);
++ipu_in_busy:
++init_dispdrv_failed:
++ fb_dealloc_cmap(&fbi->cmap);
++ framebuffer_release(fbi);
++get_fb_option_failed:
++init_fbinfo_failed:
++ return ret;
++}
++
++static int mxcfb_remove(struct platform_device *pdev)
++{
++ struct fb_info *fbi = platform_get_drvdata(pdev);
++ struct mxcfb_info *mxc_fbi = fbi->par;
++
++ if (!fbi)
++ return 0;
++
++ device_remove_file(fbi->dev, &dev_attr_fsl_disp_dev_property);
++ device_remove_file(fbi->dev, &dev_attr_fsl_disp_property);
++ mxcfb_blank(FB_BLANK_POWERDOWN, fbi);
++ mxcfb_unregister(fbi);
++ mxcfb_unmap_video_memory(fbi);
++
++ if (mxc_fbi->ovfbi) {
++ device_remove_file(mxc_fbi->ovfbi->dev,
++ &dev_attr_fsl_disp_dev_property);
++ device_remove_file(mxc_fbi->ovfbi->dev,
++ &dev_attr_fsl_disp_property);
++ mxcfb_blank(FB_BLANK_POWERDOWN, mxc_fbi->ovfbi);
++ mxcfb_unsetup_overlay(fbi);
++ mxcfb_unmap_video_memory(mxc_fbi->ovfbi);
++ }
++
++ ipu_clear_usage(mxc_fbi->ipu_id, mxc_fbi->ipu_di);
++ if (&fbi->cmap)
++ fb_dealloc_cmap(&fbi->cmap);
++ framebuffer_release(fbi);
++ return 0;
++}
++
++static const struct of_device_id imx_mxcfb_dt_ids[] = {
++ { .compatible = "fsl,mxc_sdc_fb"},
++ { /* sentinel */ }
++};
++
++/*!
++ * This structure contains pointers to the power management callback functions.
++ */
++static struct platform_driver mxcfb_driver = {
++ .driver = {
++ .name = MXCFB_NAME,
++ .of_match_table = imx_mxcfb_dt_ids,
++ },
++ .probe = mxcfb_probe,
++ .remove = mxcfb_remove,
++ .suspend = mxcfb_suspend,
++ .resume = mxcfb_resume,
++};
++
++/*!
++ * Main entry function for the framebuffer. The function registers the power
++ * management callback functions with the kernel and also registers the MXCFB
++ * callback functions with the core Linux framebuffer driver \b fbmem.c
++ *
++ * @return Error code indicating success or failure
++ */
++int __init mxcfb_init(void)
++{
++ return platform_driver_register(&mxcfb_driver);
++}
++
++void mxcfb_exit(void)
++{
++ platform_driver_unregister(&mxcfb_driver);
++}
++
++module_init(mxcfb_init);
++module_exit(mxcfb_exit);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("MXC framebuffer driver");
++MODULE_LICENSE("GPL");
++MODULE_SUPPORTED_DEVICE("fb");
+diff -Nur linux-4.1.3/drivers/video/mxc/mxc_lcdif.c linux-xbian-imx6/drivers/video/mxc/mxc_lcdif.c
+--- linux-4.1.3/drivers/video/mxc/mxc_lcdif.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/drivers/video/mxc/mxc_lcdif.c 2015-07-27 23:13:08.753749907 +0200
+@@ -0,0 +1,241 @@
++/*
++ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++#include <linux/init.h>
++#include <linux/ipu.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/mxcfb.h>
++#include <linux/of_device.h>
++#include <linux/pinctrl/consumer.h>
++#include <linux/platform_device.h>
++
++#include "mxc_dispdrv.h"
++
++struct mxc_lcd_platform_data {
++ u32 default_ifmt;
++ u32 ipu_id;
++ u32 disp_id;
++};
++
++struct mxc_lcdif_data {
++ struct platform_device *pdev;
++ struct mxc_dispdrv_handle *disp_lcdif;
++};
++
++#define DISPDRV_LCD "lcd"
++
++static struct fb_videomode lcdif_modedb[] = {
++ {
++ /* 800x480 @ 57 Hz , pixel clk @ 27MHz */
++ "CLAA-WVGA", 57, 800, 480, 37037, 40, 60, 10, 10, 20, 10,
++ FB_SYNC_CLK_LAT_FALL,
++ FB_VMODE_NONINTERLACED,
++ 0,},
++ {
++ /* 800x480 @ 60 Hz , pixel clk @ 32MHz */
++ "SEIKO-WVGA", 60, 800, 480, 29850, 89, 164, 23, 10, 10, 10,
++ FB_SYNC_CLK_LAT_FALL,
++ FB_VMODE_NONINTERLACED,
++ 0,},
++ {
++ /* 1920x1080i @ 50 Hz , pixel clk @ 74.5MHz */
++ "LCD-1080I50", 50, 1920, 1080, 13468, 528, 148, 4, 31, 44, 10,
++ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
++ FB_VMODE_INTERLACED,
++ 0,},
++};
++static int lcdif_modedb_sz = ARRAY_SIZE(lcdif_modedb);
++
++static int lcdif_init(struct mxc_dispdrv_handle *disp,
++ struct mxc_dispdrv_setting *setting)
++{
++ int ret, i;
++ struct mxc_lcdif_data *lcdif = mxc_dispdrv_getdata(disp);
++ struct mxc_lcd_platform_data *plat_data
++ = lcdif->pdev->dev.platform_data;
++ struct fb_videomode *modedb = lcdif_modedb;
++ int modedb_sz = lcdif_modedb_sz;
++
++ /* use platform defined ipu/di */
++ setting->dev_id = plat_data->ipu_id;
++ setting->disp_id = plat_data->disp_id;
++
++ ret = fb_find_mode(&setting->fbi->var, setting->fbi, setting->dft_mode_str,
++ modedb, modedb_sz, NULL, setting->default_bpp);
++ if (!ret) {
++ fb_videomode_to_var(&setting->fbi->var, &modedb[0]);
++ setting->if_fmt = plat_data->default_ifmt;
++ }
++
++ INIT_LIST_HEAD(&setting->fbi->modelist);
++ for (i = 0; i < modedb_sz; i++) {
++ struct fb_videomode m;
++ fb_var_to_videomode(&m, &setting->fbi->var);
++ if (fb_mode_is_equal(&m, &modedb[i])) {
++ fb_add_videomode(&modedb[i],
++ &setting->fbi->modelist);
++ break;
++ }
++ }
++
++ return ret;
++}
++
++void lcdif_deinit(struct mxc_dispdrv_handle *disp)
++{
++ /*TODO*/
++}
++
++static struct mxc_dispdrv_driver lcdif_drv = {
++ .name = DISPDRV_LCD,
++ .init = lcdif_init,
++ .deinit = lcdif_deinit,
++};
++
++static int lcd_get_of_property(struct platform_device *pdev,
++ struct mxc_lcd_platform_data *plat_data)
++{
++ struct device_node *np = pdev->dev.of_node;
++ int err;
++ u32 ipu_id, disp_id;
++ const char *default_ifmt;
++
++ err = of_property_read_string(np, "default_ifmt", &default_ifmt);
++ if (err) {
++ dev_dbg(&pdev->dev, "get of property default_ifmt fail\n");
++ return err;
++ }
++ err = of_property_read_u32(np, "ipu_id", &ipu_id);
++ if (err) {
++ dev_dbg(&pdev->dev, "get of property ipu_id fail\n");
++ return err;
++ }
++ err = of_property_read_u32(np, "disp_id", &disp_id);
++ if (err) {
++ dev_dbg(&pdev->dev, "get of property disp_id fail\n");
++ return err;
++ }
++
++ plat_data->ipu_id = ipu_id;
++ plat_data->disp_id = disp_id;
++ if (!strncmp(default_ifmt, "RGB24", 5))
++ plat_data->default_ifmt = IPU_PIX_FMT_RGB24;
++ else if (!strncmp(default_ifmt, "BGR24", 5))
++ plat_data->default_ifmt = IPU_PIX_FMT_BGR24;
++ else if (!strncmp(default_ifmt, "GBR24", 5))
++ plat_data->default_ifmt = IPU_PIX_FMT_GBR24;
++ else if (!strncmp(default_ifmt, "RGB565", 6))
++ plat_data->default_ifmt = IPU_PIX_FMT_RGB565;
++ else if (!strncmp(default_ifmt, "RGB666", 6))
++ plat_data->default_ifmt = IPU_PIX_FMT_RGB666;
++ else if (!strncmp(default_ifmt, "YUV444", 6))
++ plat_data->default_ifmt = IPU_PIX_FMT_YUV444;
++ else if (!strncmp(default_ifmt, "LVDS666", 7))
++ plat_data->default_ifmt = IPU_PIX_FMT_LVDS666;
++ else if (!strncmp(default_ifmt, "YUYV16", 6))
++ plat_data->default_ifmt = IPU_PIX_FMT_YUYV;
++ else if (!strncmp(default_ifmt, "UYVY16", 6))
++ plat_data->default_ifmt = IPU_PIX_FMT_UYVY;
++ else if (!strncmp(default_ifmt, "YVYU16", 6))
++ plat_data->default_ifmt = IPU_PIX_FMT_YVYU;
++ else if (!strncmp(default_ifmt, "VYUY16", 6))
++ plat_data->default_ifmt = IPU_PIX_FMT_VYUY;
++ else {
++ dev_err(&pdev->dev, "err default_ifmt!\n");
++ return -ENOENT;
++ }
++
++ return err;
++}
++
++static int mxc_lcdif_probe(struct platform_device *pdev)
++{
++ int ret;
++ struct pinctrl *pinctrl;
++ struct mxc_lcdif_data *lcdif;
++ struct mxc_lcd_platform_data *plat_data;
++
++ dev_dbg(&pdev->dev, "%s enter\n", __func__);
++ lcdif = devm_kzalloc(&pdev->dev, sizeof(struct mxc_lcdif_data),
++ GFP_KERNEL);
++ if (!lcdif)
++ return -ENOMEM;
++ plat_data = devm_kzalloc(&pdev->dev,
++ sizeof(struct mxc_lcd_platform_data),
++ GFP_KERNEL);
++ if (!plat_data)
++ return -ENOMEM;
++ pdev->dev.platform_data = plat_data;
++
++ ret = lcd_get_of_property(pdev, plat_data);
++ if (ret < 0) {
++ dev_err(&pdev->dev, "get lcd of property fail\n");
++ return ret;
++ }
++
++ pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
++ if (IS_ERR(pinctrl)) {
++ dev_err(&pdev->dev, "can't get/select pinctrl\n");
++ return PTR_ERR(pinctrl);
++ }
++
++ lcdif->pdev = pdev;
++ lcdif->disp_lcdif = mxc_dispdrv_register(&lcdif_drv);
++ mxc_dispdrv_setdata(lcdif->disp_lcdif, lcdif);
++
++ dev_set_drvdata(&pdev->dev, lcdif);
++ dev_dbg(&pdev->dev, "%s exit\n", __func__);
++
++ return ret;
++}
++
++static int mxc_lcdif_remove(struct platform_device *pdev)
++{
++ struct mxc_lcdif_data *lcdif = dev_get_drvdata(&pdev->dev);
++
++ mxc_dispdrv_puthandle(lcdif->disp_lcdif);
++ mxc_dispdrv_unregister(lcdif->disp_lcdif);
++ kfree(lcdif);
++ return 0;
++}
++
++static const struct of_device_id imx_lcd_dt_ids[] = {
++ { .compatible = "fsl,lcd"},
++ { /* sentinel */ }
++};
++static struct platform_driver mxc_lcdif_driver = {
++ .driver = {
++ .name = "mxc_lcdif",
++ .of_match_table = imx_lcd_dt_ids,
++ },
++ .probe = mxc_lcdif_probe,
++ .remove = mxc_lcdif_remove,
++};
++
++static int __init mxc_lcdif_init(void)
++{
++ return platform_driver_register(&mxc_lcdif_driver);
++}
++
++static void __exit mxc_lcdif_exit(void)
++{
++ platform_driver_unregister(&mxc_lcdif_driver);
++}
++
++module_init(mxc_lcdif_init);
++module_exit(mxc_lcdif_exit);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("i.MX ipuv3 LCD extern port driver");
++MODULE_LICENSE("GPL");
+diff -Nur linux-4.1.3/firmware/imx/sdma/sdma-imx6q.bin.ihex linux-xbian-imx6/firmware/imx/sdma/sdma-imx6q.bin.ihex
+--- linux-4.1.3/firmware/imx/sdma/sdma-imx6q.bin.ihex 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/firmware/imx/sdma/sdma-imx6q.bin.ihex 2015-07-27 23:13:08.841437049 +0200
+@@ -0,0 +1,116 @@
++:1000000053444D4101000000010000001C000000AD
++:1000100026000000B40000007A0600008202000002
++:10002000FFFFFFFF00000000FFFFFFFFFFFFFFFFDC
++:10003000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFD0
++:10004000FFFFFFFFFFFFFFFF6A1A0000FFFFFFFF38
++:10005000EB020000BB180000FFFFFFFF08040000D8
++:10006000FFFFFFFFC0030000FFFFFFFFFFFFFFFFD9
++:10007000FFFFFFFFAB020000FFFFFFFF7B0300005D
++:10008000FFFFFFFFFFFFFFFF4C0400006E040000B6
++:10009000FFFFFFFF00180000FFFFFFFFFFFFFFFF54
++:1000A000000000000018000062180000161A00008E
++:1000B000061B0000E3C1DB57E35FE357F352016A1D
++:1000C0008F00D500017D8D00A005EB5D7804037DD8
++:1000D00079042C7D367C79041F7CEE56000F600677
++:1000E000057D0965437E0A62417E20980A623E7E54
++:1000F00009653C7E12051205AD026007037DFB55C4
++:10010000D36D2B98FB55041DD36DC86A2F7F011F3B
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++:1001A000207C700B1103EB53000F6003057D096584
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++:1001C00012051205AD026007027C065A8E98265A67
++:1001D000277F011F03200048E87C700B1103135395
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++:10021000077C0000EB55004D067DFAC1E357699855
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++:1002B0007F07157D8804D500017D8D00A005EB5DCD
++:1002C0008F0212021202FF3ADA05027C3E071899E9
++:1002D000A402DD02027D3E0718995E071899EB55CE
++:1002E0009805EB5DF352FB546A07267D6C07017D90
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++:1003B00087999358D600017D8E009355A005935DD3
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++:10041000A005B4999D008C05BA05A0051002BA0488
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++:10045000FB556007027DC36DD599041DC36DC8624D
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++:1005800077C254040AC2189AE3C1DB57F352056AD2
++:10059000FB568E02941AC36AC8626902247D941EB7
++:1005A000C36ED36EC8624802C86A9426981EC36E92
++:1005B000D36EC8624C02C86A9826C36E981EC36E7A
++:1005C000C8629826C36E6002097CC8626E02247DF0
++:1005D000096A1E7F0125004D257D849A286A187FAF
++:1005E00004627AC2B89AE36E8F00D805017D8D004F
++:1005F000A005C8626E02107D096A0A7F0120F97C9D
++:10060000286A067F0000004D0D7DFAC1DB576E9A07
++:10061000070004620C6AB59A286AFA7F04627AC2FB
++:1006200058045404286AF47F0AC26B9AD9C1E3C102
++:10063000DB57F352056AFB568E02941A0252690286
++:100640001D7D941E06524802065A9426981E065294
++:100650004C02065A9826981E065260020A7C98267A
++:1006600006526E02237D096A1D7F0125004D247DFF
++:10067000D19A286A177F04627AC2029B8F00D8053C
++:10068000017D8D00A00506526E02107D096A0A7F69
++:100690000120F97C286A067F0000004D0D7DFAC11B
++:1006A000DB57C19A070004620C6AFF9A286AFA7F36
++:1006B00004627AC258045404286AF47F0AC2BE9ABB
++:1006C000016E0B612F7E0B622D7E0B632B7E0C0D5A
++:1006D0001704170417049D04081DCC05017C0C0D9C
++:1006E000D16A000F4207C86FDD6F1C7F8E009D002E
++:1006F00001680B67177ED56B04080278C86F120774
++:10070000117C0B670F7E04080278C86F12070A7C01
++:10071000DD6F087FD169010FC86FDD6F037F0101B5
++:0E0720000004129B0700FF680C680002129B89
++:00000001FF
+diff -Nur linux-4.1.3/firmware/Makefile linux-xbian-imx6/firmware/Makefile
+--- linux-4.1.3/firmware/Makefile 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/firmware/Makefile 2015-07-27 23:13:08.809550816 +0200
+@@ -62,6 +62,7 @@
+ radeon/RV730_pfp.bin radeon/RV730_me.bin \
+ radeon/RV710_pfp.bin radeon/RV710_me.bin
+ fw-shipped-$(CONFIG_DVB_AV7110) += av7110/bootcode.bin
++fw-shipped-$(CONFIG_IMX_SDMA) += imx/sdma/sdma-imx6q.bin
+ fw-shipped-$(CONFIG_DVB_TTUSB_BUDGET) += ttusb-budget/dspbootcode.bin
+ fw-shipped-$(CONFIG_E100) += e100/d101m_ucode.bin e100/d101s_ucode.bin \
+ e100/d102e_ucode.bin
+diff -Nur linux-4.1.3/fs/btrfs/compression.c linux-xbian-imx6/fs/btrfs/compression.c
+--- linux-4.1.3/fs/btrfs/compression.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/fs/btrfs/compression.c 2015-07-27 23:13:08.905209516 +0200
+@@ -753,6 +753,8 @@
+ static const struct btrfs_compress_op * const btrfs_compress_op[] = {
+ &btrfs_zlib_compress,
+ &btrfs_lzo_compress,
++ &btrfs_lz4_compress,
++ &btrfs_lz4hc_compress,
+ };
+
+ void __init btrfs_init_compress(void)
+diff -Nur linux-4.1.3/fs/btrfs/compression.h linux-xbian-imx6/fs/btrfs/compression.h
+--- linux-4.1.3/fs/btrfs/compression.h 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/fs/btrfs/compression.h 2015-07-27 23:13:08.905209516 +0200
+@@ -79,5 +79,7 @@
+
+ extern const struct btrfs_compress_op btrfs_zlib_compress;
+ extern const struct btrfs_compress_op btrfs_lzo_compress;
++extern const struct btrfs_compress_op btrfs_lz4_compress;
++extern const struct btrfs_compress_op btrfs_lz4hc_compress;
+
+ #endif
+diff -Nur linux-4.1.3/fs/btrfs/ctree.h linux-xbian-imx6/fs/btrfs/ctree.h
+--- linux-4.1.3/fs/btrfs/ctree.h 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/fs/btrfs/ctree.h 2015-07-27 23:13:08.909195295 +0200
+@@ -504,13 +504,7 @@
+ #define BTRFS_FEATURE_INCOMPAT_DEFAULT_SUBVOL (1ULL << 1)
+ #define BTRFS_FEATURE_INCOMPAT_MIXED_GROUPS (1ULL << 2)
+ #define BTRFS_FEATURE_INCOMPAT_COMPRESS_LZO (1ULL << 3)
+-/*
+- * some patches floated around with a second compression method
+- * lets save that incompat here for when they do get in
+- * Note we don't actually support it, we're just reserving the
+- * number
+- */
+-#define BTRFS_FEATURE_INCOMPAT_COMPRESS_LZOv2 (1ULL << 4)
++#define BTRFS_FEATURE_INCOMPAT_COMPRESS_LZ4 (1ULL << 4)
+
+ /*
+ * older kernels tried to do bigger metadata blocks, but the
+@@ -539,6 +533,7 @@
+ BTRFS_FEATURE_INCOMPAT_RAID56 | \
+ BTRFS_FEATURE_INCOMPAT_EXTENDED_IREF | \
+ BTRFS_FEATURE_INCOMPAT_SKINNY_METADATA | \
++ BTRFS_FEATURE_INCOMPAT_COMPRESS_LZ4 | \
+ BTRFS_FEATURE_INCOMPAT_NO_HOLES)
+
+ #define BTRFS_FEATURE_INCOMPAT_SAFE_SET \
+@@ -709,8 +704,10 @@
+ BTRFS_COMPRESS_NONE = 0,
+ BTRFS_COMPRESS_ZLIB = 1,
+ BTRFS_COMPRESS_LZO = 2,
+- BTRFS_COMPRESS_TYPES = 2,
+- BTRFS_COMPRESS_LAST = 3,
++ BTRFS_COMPRESS_LZ4 = 3,
++ BTRFS_COMPRESS_LZ4HC = 4,
++ BTRFS_COMPRESS_TYPES = 4,
++ BTRFS_COMPRESS_LAST = 5,
+ };
+
+ struct btrfs_inode_item {
+diff -Nur linux-4.1.3/fs/btrfs/disk-io.c linux-xbian-imx6/fs/btrfs/disk-io.c
+--- linux-4.1.3/fs/btrfs/disk-io.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/fs/btrfs/disk-io.c 2015-07-27 23:13:08.909195295 +0200
+@@ -2703,6 +2703,10 @@
+ if (tree_root->fs_info->compress_type == BTRFS_COMPRESS_LZO)
+ features |= BTRFS_FEATURE_INCOMPAT_COMPRESS_LZO;
+
++ if (tree_root->fs_info->compress_type == BTRFS_COMPRESS_LZ4 ||
++ tree_root->fs_info->compress_type == BTRFS_COMPRESS_LZ4HC)
++ features |= BTRFS_FEATURE_INCOMPAT_COMPRESS_LZ4;
++
+ if (features & BTRFS_FEATURE_INCOMPAT_SKINNY_METADATA)
+ printk(KERN_INFO "BTRFS: has skinny extents\n");
+
+diff -Nur linux-4.1.3/fs/btrfs/ioctl.c linux-xbian-imx6/fs/btrfs/ioctl.c
+--- linux-4.1.3/fs/btrfs/ioctl.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/fs/btrfs/ioctl.c 2015-07-27 23:13:08.921152633 +0200
+@@ -1439,6 +1439,10 @@
+ if (range->compress_type == BTRFS_COMPRESS_LZO) {
+ btrfs_set_fs_incompat(root->fs_info, COMPRESS_LZO);
+ }
++ if (range->compress_type == BTRFS_COMPRESS_LZ4 ||
++ range->compress_type == BTRFS_COMPRESS_LZ4HC) {
++ btrfs_set_fs_incompat(root->fs_info, COMPRESS_LZ4);
++ }
+
+ ret = defrag_count;
+
+diff -Nur linux-4.1.3/fs/btrfs/lz4_wrapper.c linux-xbian-imx6/fs/btrfs/lz4_wrapper.c
+--- linux-4.1.3/fs/btrfs/lz4_wrapper.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/fs/btrfs/lz4_wrapper.c 2015-07-27 23:13:08.921152633 +0200
+@@ -0,0 +1,487 @@
++/*
++ * Copyright (C) 2008 Oracle. All rights reserved.
++ * Copyright (C) 2013 SUSE. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public
++ * License v2 as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
++ * General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public
++ * License along with this program; if not, write to the
++ * Free Software Foundation, Inc., 59 Temple Place - Suite 330,
++ * Boston, MA 021110-1307, USA.
++ */
++
++#include <linux/kernel.h>
++#include <linux/slab.h>
++#include <linux/vmalloc.h>
++#include <linux/init.h>
++#include <linux/err.h>
++#include <linux/sched.h>
++#include <linux/pagemap.h>
++#include <linux/bio.h>
++#include <linux/lz4.h>
++#include "compression.h"
++
++#define LZ4_LEN 4
++#define LZ4_CHUNK_SIZE (4096)
++#define LZ4_MAX_WORKBUF 2*LZ4_CHUNK_SIZE
++
++struct workspace {
++ void *mem; /* work memory for compression */
++ void *buf; /* where compressed data goes */
++ void *cbuf; /* where decompressed data goes */
++ struct list_head list;
++};
++
++static void lz4_free_workspace(struct list_head *ws)
++{
++ struct workspace *workspace = list_entry(ws, struct workspace, list);
++
++ vfree(workspace->buf);
++ vfree(workspace->cbuf);
++ vfree(workspace->mem);
++ kfree(workspace);
++}
++
++static struct list_head *lz4_alloc_workspace_generic(int hi)
++{
++ struct workspace *workspace;
++
++ workspace = kzalloc(sizeof(*workspace), GFP_NOFS);
++ if (!workspace)
++ return ERR_PTR(-ENOMEM);
++
++ if (hi)
++ workspace->mem = vmalloc(LZ4HC_MEM_COMPRESS);
++ else
++ workspace->mem = vmalloc(LZ4_MEM_COMPRESS);
++ workspace->buf = vmalloc(LZ4_MAX_WORKBUF);
++ workspace->cbuf = vmalloc(LZ4_MAX_WORKBUF);
++ if (!workspace->mem || !workspace->buf || !workspace->cbuf)
++ goto fail;
++
++ INIT_LIST_HEAD(&workspace->list);
++
++ return &workspace->list;
++fail:
++ lz4_free_workspace(&workspace->list);
++ return ERR_PTR(-ENOMEM);
++}
++
++static struct list_head *lz4_alloc_workspace(void)
++{
++ return lz4_alloc_workspace_generic(0);
++}
++
++static struct list_head *lz4hc_alloc_workspace(void)
++{
++ return lz4_alloc_workspace_generic(1);
++}
++
++static inline void write_compress_length(char *buf, size_t len)
++{
++ __le32 dlen;
++
++ dlen = cpu_to_le32(len);
++ memcpy(buf, &dlen, LZ4_LEN);
++}
++
++static inline size_t read_compress_length(char *buf)
++{
++ __le32 dlen;
++
++ memcpy(&dlen, buf, LZ4_LEN);
++ return le32_to_cpu(dlen);
++}
++
++static int lz4_compress_pages_generic(struct list_head *ws,
++ struct address_space *mapping,
++ u64 start, unsigned long len,
++ struct page **pages,
++ unsigned long nr_dest_pages,
++ unsigned long *out_pages,
++ unsigned long *total_in,
++ unsigned long *total_out,
++ unsigned long max_out, int hi)
++{
++ struct workspace *workspace = list_entry(ws, struct workspace, list);
++ int ret = 0;
++ char *data_in;
++ char *cpage_out;
++ int nr_pages = 0;
++ struct page *in_page = NULL;
++ struct page *out_page = NULL;
++ unsigned long bytes_left;
++
++ size_t in_len;
++ size_t out_len;
++ char *buf;
++ unsigned long tot_in = 0;
++ unsigned long tot_out = 0;
++ unsigned long pg_bytes_left;
++ unsigned long out_offset;
++ unsigned long bytes;
++
++ *out_pages = 0;
++ *total_out = 0;
++ *total_in = 0;
++
++ in_page = find_get_page(mapping, start >> PAGE_CACHE_SHIFT);
++ data_in = kmap(in_page);
++
++ /*
++ * store the size of all chunks of compressed data in
++ * the first 4 bytes
++ */
++ out_page = alloc_page(GFP_NOFS | __GFP_HIGHMEM);
++ if (out_page == NULL) {
++ ret = -ENOMEM;
++ goto out;
++ }
++ cpage_out = kmap(out_page);
++ out_offset = LZ4_LEN;
++ tot_out = LZ4_LEN;
++ pages[0] = out_page;
++ nr_pages = 1;
++ pg_bytes_left = PAGE_CACHE_SIZE - LZ4_LEN;
++
++ /* compress at most one page of data each time */
++ in_len = min(len, PAGE_CACHE_SIZE);
++ while (tot_in < len) {
++ if (hi)
++ ret = lz4hc_compress(data_in, in_len, workspace->cbuf,
++ &out_len, workspace->mem);
++ else
++ ret = lz4_compress(data_in, in_len, workspace->cbuf, &out_len,
++ workspace->mem);
++ if (ret < 0) {
++ printk(KERN_DEBUG
++ "btrfs: lz4 compress in loop returned %d\n",
++ ret);
++ ret = -1;
++ goto out;
++ }
++
++ /* store the size of this chunk of compressed data */
++ write_compress_length(cpage_out + out_offset, out_len);
++ tot_out += LZ4_LEN;
++ out_offset += LZ4_LEN;
++ pg_bytes_left -= LZ4_LEN;
++
++ tot_in += in_len;
++ tot_out += out_len;
++
++ /* copy bytes from the working buffer into the pages */
++ buf = workspace->cbuf;
++ while (out_len) {
++ bytes = min_t(unsigned long, pg_bytes_left, out_len);
++
++ memcpy(cpage_out + out_offset, buf, bytes);
++
++ out_len -= bytes;
++ pg_bytes_left -= bytes;
++ buf += bytes;
++ out_offset += bytes;
++
++ /*
++ * we need another page for writing out.
++ *
++ * Note if there's less than 4 bytes left, we just
++ * skip to a new page.
++ */
++ if ((out_len == 0 && pg_bytes_left < LZ4_LEN) ||
++ pg_bytes_left == 0) {
++ if (pg_bytes_left) {
++ memset(cpage_out + out_offset, 0,
++ pg_bytes_left);
++ tot_out += pg_bytes_left;
++ }
++
++ /* we're done, don't allocate new page */
++ if (out_len == 0 && tot_in >= len)
++ break;
++
++ kunmap(out_page);
++ if (nr_pages == nr_dest_pages) {
++ out_page = NULL;
++ ret = -1;
++ goto out;
++ }
++
++ out_page = alloc_page(GFP_NOFS | __GFP_HIGHMEM);
++ if (out_page == NULL) {
++ ret = -ENOMEM;
++ goto out;
++ }
++ cpage_out = kmap(out_page);
++ pages[nr_pages++] = out_page;
++
++ pg_bytes_left = PAGE_CACHE_SIZE;
++ out_offset = 0;
++ }
++ }
++
++ /* we're making it bigger, give up */
++ if (tot_in > 8192 && tot_in < tot_out)
++ goto out;
++
++ /* we're all done */
++ if (tot_in >= len)
++ break;
++
++ if (tot_out > max_out)
++ break;
++
++ bytes_left = len - tot_in;
++ kunmap(in_page);
++ page_cache_release(in_page);
++
++ start += PAGE_CACHE_SIZE;
++ in_page = find_get_page(mapping, start >> PAGE_CACHE_SHIFT);
++ data_in = kmap(in_page);
++ in_len = min(bytes_left, PAGE_CACHE_SIZE);
++ }
++
++ if (tot_out > tot_in)
++ goto out;
++
++ /* store the size of all chunks of compressed data */
++ cpage_out = kmap(pages[0]);
++ write_compress_length(cpage_out, tot_out);
++
++ kunmap(pages[0]);
++
++ ret = 0;
++ *total_out = tot_out;
++ *total_in = tot_in;
++out:
++ *out_pages = nr_pages;
++ if (out_page)
++ kunmap(out_page);
++
++ if (in_page) {
++ kunmap(in_page);
++ page_cache_release(in_page);
++ }
++
++ return ret;
++}
++
++static int lz4_compress_pages(struct list_head *ws,
++ struct address_space *mapping,
++ u64 start, unsigned long len,
++ struct page **pages,
++ unsigned long nr_dest_pages,
++ unsigned long *out_pages,
++ unsigned long *total_in,
++ unsigned long *total_out,
++ unsigned long max_out)
++{
++ return lz4_compress_pages_generic(ws, mapping, start, len, pages,
++ nr_dest_pages, out_pages, total_in, total_out,
++ max_out, 0);
++}
++
++static int lz4hc_compress_pages(struct list_head *ws,
++ struct address_space *mapping,
++ u64 start, unsigned long len,
++ struct page **pages,
++ unsigned long nr_dest_pages,
++ unsigned long *out_pages,
++ unsigned long *total_in,
++ unsigned long *total_out,
++ unsigned long max_out)
++{
++ return lz4_compress_pages_generic(ws, mapping, start, len, pages,
++ nr_dest_pages, out_pages, total_in, total_out,
++ max_out, 1);
++}
++
++static int lz4_decompress_biovec(struct list_head *ws,
++ struct page **pages_in,
++ u64 disk_start,
++ struct bio_vec *bvec,
++ int vcnt,
++ size_t srclen)
++{
++ struct workspace *workspace = list_entry(ws, struct workspace, list);
++ int ret = 0, ret2;
++ char *data_in;
++ unsigned long page_in_index = 0;
++ unsigned long page_out_index = 0;
++ unsigned long total_pages_in = (srclen + PAGE_CACHE_SIZE - 1) /
++ PAGE_CACHE_SIZE;
++ unsigned long buf_start;
++ unsigned long buf_offset = 0;
++ unsigned long bytes;
++ unsigned long working_bytes;
++ unsigned long pg_offset;
++
++ size_t in_len;
++ size_t out_len;
++ unsigned long in_offset;
++ unsigned long in_page_bytes_left;
++ unsigned long tot_in;
++ unsigned long tot_out;
++ unsigned long tot_len;
++ char *buf;
++ bool may_late_unmap, need_unmap;
++
++ data_in = kmap(pages_in[0]);
++ tot_len = read_compress_length(data_in);
++
++ tot_in = LZ4_LEN;
++ in_offset = LZ4_LEN;
++ tot_len = min_t(size_t, srclen, tot_len);
++ in_page_bytes_left = PAGE_CACHE_SIZE - LZ4_LEN;
++
++ tot_out = 0;
++ pg_offset = 0;
++
++ while (tot_in < tot_len) {
++ in_len = read_compress_length(data_in + in_offset);
++ in_page_bytes_left -= LZ4_LEN;
++ in_offset += LZ4_LEN;
++ tot_in += LZ4_LEN;
++
++ tot_in += in_len;
++ working_bytes = in_len;
++ may_late_unmap = need_unmap = false;
++
++ /* fast path: avoid using the working buffer */
++ if (in_page_bytes_left >= in_len) {
++ buf = data_in + in_offset;
++ bytes = in_len;
++ may_late_unmap = true;
++ goto cont;
++ }
++
++ /* copy bytes from the pages into the working buffer */
++ buf = workspace->cbuf;
++ buf_offset = 0;
++ while (working_bytes) {
++ bytes = min(working_bytes, in_page_bytes_left);
++
++ memcpy(buf + buf_offset, data_in + in_offset, bytes);
++ buf_offset += bytes;
++cont:
++ working_bytes -= bytes;
++ in_page_bytes_left -= bytes;
++ in_offset += bytes;
++
++ /* check if we need to pick another page */
++ if ((working_bytes == 0 && in_page_bytes_left < LZ4_LEN)
++ || in_page_bytes_left == 0) {
++ tot_in += in_page_bytes_left;
++
++ if (working_bytes == 0 && tot_in >= tot_len)
++ break;
++
++ if (page_in_index + 1 >= total_pages_in) {
++ ret = -1;
++ goto done;
++ }
++
++ if (may_late_unmap)
++ need_unmap = true;
++ else
++ kunmap(pages_in[page_in_index]);
++
++ data_in = kmap(pages_in[++page_in_index]);
++
++ in_page_bytes_left = PAGE_CACHE_SIZE;
++ in_offset = 0;
++ }
++ }
++
++ out_len = LZ4_CHUNK_SIZE;
++ ret = lz4_decompress_unknownoutputsize(buf, in_len, workspace->buf,
++ &out_len);
++ if (need_unmap)
++ kunmap(pages_in[page_in_index - 1]);
++ if (ret < 0) {
++ printk(KERN_WARNING "btrfs: lz4 decompress failed\n");
++ ret = -1;
++ break;
++ }
++
++ buf_start = tot_out;
++ tot_out += out_len;
++
++ ret2 = btrfs_decompress_buf2page(workspace->buf, buf_start,
++ tot_out, disk_start,
++ bvec, vcnt,
++ &page_out_index, &pg_offset);
++ if (ret2 == 0)
++ break;
++ }
++done:
++ kunmap(pages_in[page_in_index]);
++ return ret;
++}
++
++static int lz4_decompress_wrapper(struct list_head *ws, unsigned char *data_in,
++ struct page *dest_page,
++ unsigned long start_byte,
++ size_t srclen, size_t destlen)
++{
++ struct workspace *workspace = list_entry(ws, struct workspace, list);
++ size_t in_len;
++ size_t out_len;
++ size_t tot_len;
++ int ret = 0;
++ char *kaddr;
++ unsigned long bytes;
++
++ BUG_ON(srclen < LZ4_LEN);
++
++ tot_len = read_compress_length(data_in);
++ data_in += LZ4_LEN;
++
++ in_len = read_compress_length(data_in);
++ data_in += LZ4_LEN;
++
++ out_len = LZ4_CHUNK_SIZE;
++ ret = lz4_decompress_unknownoutputsize(data_in, in_len, workspace->buf,
++ &out_len);
++ if (ret < 0) {
++ printk(KERN_WARNING "btrfs: lz4 decompress failed\n");
++ ret = -1;
++ goto out;
++ }
++
++ if (out_len < start_byte) {
++ ret = -1;
++ goto out;
++ }
++
++ bytes = min_t(unsigned long, destlen, out_len - start_byte);
++
++ kaddr = kmap_atomic(dest_page);
++ memcpy(kaddr, workspace->buf + start_byte, bytes);
++ kunmap_atomic(kaddr);
++out:
++ return ret;
++}
++
++const struct btrfs_compress_op btrfs_lz4_compress = {
++ .alloc_workspace = lz4_alloc_workspace,
++ .free_workspace = lz4_free_workspace,
++ .compress_pages = lz4_compress_pages,
++ .decompress_biovec = lz4_decompress_biovec,
++ .decompress = lz4_decompress_wrapper,
++};
++
++const struct btrfs_compress_op btrfs_lz4hc_compress = {
++ .alloc_workspace = lz4hc_alloc_workspace,
++ .free_workspace = lz4_free_workspace,
++ .compress_pages = lz4hc_compress_pages,
++ .decompress_biovec = lz4_decompress_biovec,
++ .decompress = lz4_decompress_wrapper,
++};
+diff -Nur linux-4.1.3/fs/btrfs/Makefile linux-xbian-imx6/fs/btrfs/Makefile
+--- linux-4.1.3/fs/btrfs/Makefile 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/fs/btrfs/Makefile 2015-07-27 23:13:08.901223737 +0200
+@@ -9,7 +9,7 @@
+ export.o tree-log.o free-space-cache.o zlib.o lzo.o \
+ compression.o delayed-ref.o relocation.o delayed-inode.o scrub.o \
+ reada.o backref.o ulist.o qgroup.o send.o dev-replace.o raid56.o \
+- uuid-tree.o props.o hash.o
++ uuid-tree.o props.o hash.o lz4_wrapper.o
+
+ btrfs-$(CONFIG_BTRFS_FS_POSIX_ACL) += acl.o
+ btrfs-$(CONFIG_BTRFS_FS_CHECK_INTEGRITY) += check-integrity.o
+diff -Nur linux-4.1.3/fs/btrfs/super.c linux-xbian-imx6/fs/btrfs/super.c
+--- linux-4.1.3/fs/btrfs/super.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/fs/btrfs/super.c 2015-07-27 23:13:08.961010425 +0200
+@@ -492,6 +492,20 @@
+ btrfs_clear_opt(info->mount_opt, COMPRESS);
+ btrfs_clear_opt(info->mount_opt, FORCE_COMPRESS);
+ compress_force = false;
++ } else if (strcmp(args[0].from, "lz4") == 0) {
++ compress_type = "lz4";
++ info->compress_type = BTRFS_COMPRESS_LZ4;
++ btrfs_set_opt(info->mount_opt, COMPRESS);
++ btrfs_clear_opt(info->mount_opt, NODATACOW);
++ btrfs_clear_opt(info->mount_opt, NODATASUM);
++ btrfs_set_fs_incompat(info, COMPRESS_LZ4);
++ } else if (strcmp(args[0].from, "lz4hc") == 0) {
++ compress_type = "lz4hc";
++ info->compress_type = BTRFS_COMPRESS_LZ4HC;
++ btrfs_set_opt(info->mount_opt, COMPRESS);
++ btrfs_clear_opt(info->mount_opt, NODATACOW);
++ btrfs_clear_opt(info->mount_opt, NODATASUM);
++ btrfs_set_fs_incompat(info, COMPRESS_LZ4);
+ } else {
+ ret = -EINVAL;
+ goto out;
+@@ -1051,8 +1065,14 @@
+ if (btrfs_test_opt(root, COMPRESS)) {
+ if (info->compress_type == BTRFS_COMPRESS_ZLIB)
+ compress_type = "zlib";
++ else if (info->compress_type == BTRFS_COMPRESS_LZ4)
++ compress_type = "lz4";
++ else if (info->compress_type == BTRFS_COMPRESS_LZ4HC)
++ compress_type = "lz4hc";
++ else if (info->compress_type == BTRFS_COMPRESS_LZO)
++ compress_type = "lzo";
+ else
+- compress_type = "lzo";
++ compress_type = "none";
+ if (btrfs_test_opt(root, FORCE_COMPRESS))
+ seq_printf(seq, ",compress-force=%s", compress_type);
+ else
+diff -Nur linux-4.1.3/include/dt-bindings/clock/imx6qdl-clock.h linux-xbian-imx6/include/dt-bindings/clock/imx6qdl-clock.h
+--- linux-4.1.3/include/dt-bindings/clock/imx6qdl-clock.h 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/include/dt-bindings/clock/imx6qdl-clock.h 2015-07-27 23:13:09.467204382 +0200
+@@ -86,8 +86,6 @@
+ #define IMX6QDL_CLK_GPU3D_SHADER 74
+ #define IMX6QDL_CLK_IPU1_PODF 75
+ #define IMX6QDL_CLK_IPU2_PODF 76
+-#define IMX6QDL_CLK_LDB_DI0_PODF 77
+-#define IMX6QDL_CLK_LDB_DI1_PODF 78
+ #define IMX6QDL_CLK_IPU1_DI0_PRE 79
+ #define IMX6QDL_CLK_IPU1_DI1_PRE 80
+ #define IMX6QDL_CLK_IPU2_DI0_PRE 81
+@@ -251,6 +249,13 @@
+ #define IMX6QDL_CLK_VIDEO_27M 238
+ #define IMX6QDL_CLK_MIPI_CORE_CFG 239
+ #define IMX6QDL_CLK_MIPI_IPG 240
+-#define IMX6QDL_CLK_END 241
++#define IMX6QDL_CLK_LDB_DI0_DIV_7 241
++#define IMX6QDL_CLK_LDB_DI1_DIV_7 242
++#define IMX6QDL_CLK_LDB_DI0_DIV_SEL 243
++#define IMX6QDL_CLK_LDB_DI1_DIV_SEL 244
++#define IMX6QDL_CLK_DCIC1 245
++#define IMX6QDL_CLK_DCIC2 246
++#define IMX6QDL_CLK_SPDIF_GCLK 247
++#define IMX6QDL_CLK_END 248
+
+ #endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */
+diff -Nur linux-4.1.3/include/linux/busfreq-imx6.h linux-xbian-imx6/include/linux/busfreq-imx6.h
+--- linux-4.1.3/include/linux/busfreq-imx6.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/include/linux/busfreq-imx6.h 2015-07-27 23:13:09.479161721 +0200
+@@ -0,0 +1,23 @@
++/*
++ * Copyright 2012-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef __ASM_ARCH_MXC_BUSFREQ_H__
++#define __ASM_ARCH_MXC_BUSFREQ_H__
++
++/*
++ * This enumerates busfreq mode.
++ */
++enum bus_freq_mode {
++ BUS_FREQ_HIGH,
++ BUS_FREQ_MED,
++ BUS_FREQ_AUDIO,
++ BUS_FREQ_LOW,
++};
++void request_bus_freq(enum bus_freq_mode mode);
++void release_bus_freq(enum bus_freq_mode mode);
++#endif
+diff -Nur linux-4.1.3/include/linux/cgroup_subsys.h linux-xbian-imx6/include/linux/cgroup_subsys.h
+--- linux-4.1.3/include/linux/cgroup_subsys.h 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/include/linux/cgroup_subsys.h 2015-07-27 23:13:09.483147501 +0200
+@@ -35,6 +35,10 @@
+ SUBSYS(net_cls)
+ #endif
+
++#if IS_ENABLED(CONFIG_CGROUP_BFQIO)
++SUBSYS(bfqio)
++#endif
++
+ #if IS_ENABLED(CONFIG_CGROUP_PERF)
+ SUBSYS(perf_event)
+ #endif
+diff -Nur linux-4.1.3/include/linux/device_cooling.h linux-xbian-imx6/include/linux/device_cooling.h
+--- linux-4.1.3/include/linux/device_cooling.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/include/linux/device_cooling.h 2015-07-27 23:13:09.491119057 +0200
+@@ -0,0 +1,45 @@
++/*
++ * Copyright (C) 2013 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#ifndef __DEVICE_THERMAL_H__
++#define __DEVICE_THERMAL_H__
++
++#include <linux/thermal.h>
++
++#ifdef CONFIG_DEVICE_THERMAL
++int register_devfreq_cooling_notifier(struct notifier_block *nb);
++int unregister_devfreq_cooling_notifier(struct notifier_block *nb);
++struct thermal_cooling_device *devfreq_cooling_register(void);
++void devfreq_cooling_unregister(struct thermal_cooling_device *cdev);
++#else
++static inline
++int register_devfreq_cooling_notifier(struct notifier_block *nb)
++{
++ return 0;
++}
++
++static inline
++int unregister_devfreq_cooling_notifier(struct notifier_block *nb)
++{
++ return 0;
++}
++
++static inline
++struct thermal_cooling_device *devfreq_cooling_register(void)
++{
++ return NULL;
++}
++
++static inline
++void devfreq_cooling_unregister(struct thermal_cooling_device *cdev)
++{
++ return;
++}
++#endif
++#endif /* __DEVICE_THERMAL_H__ */
+diff -Nur linux-4.1.3/include/linux/fb.h linux-xbian-imx6/include/linux/fb.h
+--- linux-4.1.3/include/linux/fb.h 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/include/linux/fb.h 2015-07-27 23:13:09.495104834 +0200
+@@ -702,7 +702,8 @@
+ #define FB_MODE_IS_VESA 4
+ #define FB_MODE_IS_CALCULATED 8
+ #define FB_MODE_IS_FIRST 16
+-#define FB_MODE_IS_FROM_VAR 32
++#define FB_MODE_IS_FROM_VAR 32
++#define FB_MODE_IS_3D 64
+
+ extern int fbmon_dpms(const struct fb_info *fb_info);
+ extern int fb_get_mode(int flags, u32 val, struct fb_var_screeninfo *var,
+diff -Nur linux-4.1.3/include/linux/ipu.h linux-xbian-imx6/include/linux/ipu.h
+--- linux-4.1.3/include/linux/ipu.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/include/linux/ipu.h 2015-07-27 23:13:09.542934188 +0200
+@@ -0,0 +1,38 @@
++/*
++ * Copyright 2005-2013 Freescale Semiconductor, Inc.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU Lesser General
++ * Public License. You may obtain a copy of the GNU Lesser General
++ * Public License Version 2.1 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/lgpl-license.html
++ * http://www.gnu.org/copyleft/lgpl.html
++ */
++
++/*!
++ * @defgroup IPU MXC Image Processing Unit (IPU) Driver
++ */
++/*!
++ * @file linux/ipu.h
++ *
++ * @brief This file contains the IPU driver API declarations.
++ *
++ * @ingroup IPU
++ */
++
++#ifndef __LINUX_IPU_H__
++#define __LINUX_IPU_H__
++
++#include <linux/interrupt.h>
++#include <uapi/linux/ipu.h>
++
++unsigned int fmt_to_bpp(unsigned int pixelformat);
++cs_t colorspaceofpixel(int fmt);
++int need_csc(int ifmt, int ofmt);
++
++int ipu_queue_task(struct ipu_task *task);
++int ipu_check_task(struct ipu_task *task);
++
++#endif
+diff -Nur linux-4.1.3/include/linux/ipu-v3.h linux-xbian-imx6/include/linux/ipu-v3.h
+--- linux-4.1.3/include/linux/ipu-v3.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/include/linux/ipu-v3.h 2015-07-27 23:13:09.542934188 +0200
+@@ -0,0 +1,752 @@
++/*
++ * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
++ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
++ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
++ * for more details.
++ */
++
++#ifndef __LINUX_IPU_V3_H_
++#define __LINUX_IPU_V3_H_
++
++#include <linux/ipu.h>
++
++/* IPU Driver channels definitions. */
++/* Note these are different from IDMA channels */
++#define IPU_MAX_CH 32
++#define _MAKE_CHAN(num, v_in, g_in, a_in, out) \
++ ((num << 24) | (v_in << 18) | (g_in << 12) | (a_in << 6) | out)
++#define _MAKE_ALT_CHAN(ch) (ch | (IPU_MAX_CH << 24))
++#define IPU_CHAN_ID(ch) (ch >> 24)
++#define IPU_CHAN_ALT(ch) (ch & 0x02000000)
++#define IPU_CHAN_ALPHA_IN_DMA(ch) ((uint32_t) (ch >> 6) & 0x3F)
++#define IPU_CHAN_GRAPH_IN_DMA(ch) ((uint32_t) (ch >> 12) & 0x3F)
++#define IPU_CHAN_VIDEO_IN_DMA(ch) ((uint32_t) (ch >> 18) & 0x3F)
++#define IPU_CHAN_OUT_DMA(ch) ((uint32_t) (ch & 0x3F))
++#define NO_DMA 0x3F
++#define ALT 1
++/*!
++ * Enumeration of IPU logical channels. An IPU logical channel is defined as a
++ * combination of an input (memory to IPU), output (IPU to memory), and/or
++ * secondary input IDMA channels and in some cases an Image Converter task.
++ * Some channels consist of only an input or output.
++ */
++typedef enum {
++ CHAN_NONE = -1,
++ MEM_ROT_ENC_MEM = _MAKE_CHAN(1, 45, NO_DMA, NO_DMA, 48),
++ MEM_ROT_VF_MEM = _MAKE_CHAN(2, 46, NO_DMA, NO_DMA, 49),
++ MEM_ROT_PP_MEM = _MAKE_CHAN(3, 47, NO_DMA, NO_DMA, 50),
++
++ MEM_PRP_ENC_MEM = _MAKE_CHAN(4, 12, 14, 17, 20),
++ MEM_PRP_VF_MEM = _MAKE_CHAN(5, 12, 14, 17, 21),
++ MEM_PP_MEM = _MAKE_CHAN(6, 11, 15, 18, 22),
++
++ MEM_DC_SYNC = _MAKE_CHAN(7, 28, NO_DMA, NO_DMA, NO_DMA),
++ MEM_DC_ASYNC = _MAKE_CHAN(8, 41, NO_DMA, NO_DMA, NO_DMA),
++ MEM_BG_SYNC = _MAKE_CHAN(9, 23, NO_DMA, 51, NO_DMA),
++ MEM_FG_SYNC = _MAKE_CHAN(10, 27, NO_DMA, 31, NO_DMA),
++
++ MEM_BG_ASYNC0 = _MAKE_CHAN(11, 24, NO_DMA, 52, NO_DMA),
++ MEM_FG_ASYNC0 = _MAKE_CHAN(12, 29, NO_DMA, 33, NO_DMA),
++ MEM_BG_ASYNC1 = _MAKE_ALT_CHAN(MEM_BG_ASYNC0),
++ MEM_FG_ASYNC1 = _MAKE_ALT_CHAN(MEM_FG_ASYNC0),
++
++ DIRECT_ASYNC0 = _MAKE_CHAN(13, NO_DMA, NO_DMA, NO_DMA, NO_DMA),
++ DIRECT_ASYNC1 = _MAKE_CHAN(14, NO_DMA, NO_DMA, NO_DMA, NO_DMA),
++
++ CSI_MEM0 = _MAKE_CHAN(15, NO_DMA, NO_DMA, NO_DMA, 0),
++ CSI_MEM1 = _MAKE_CHAN(16, NO_DMA, NO_DMA, NO_DMA, 1),
++ CSI_MEM2 = _MAKE_CHAN(17, NO_DMA, NO_DMA, NO_DMA, 2),
++ CSI_MEM3 = _MAKE_CHAN(18, NO_DMA, NO_DMA, NO_DMA, 3),
++
++ CSI_MEM = CSI_MEM0,
++
++ CSI_PRP_ENC_MEM = _MAKE_CHAN(19, NO_DMA, NO_DMA, NO_DMA, 20),
++ CSI_PRP_VF_MEM = _MAKE_CHAN(20, NO_DMA, NO_DMA, NO_DMA, 21),
++
++ /* for vdi mem->vdi->ic->mem , add graphics plane and alpha*/
++ MEM_VDI_PRP_VF_MEM_P = _MAKE_CHAN(21, 8, 14, 17, 21),
++ MEM_VDI_PRP_VF_MEM = _MAKE_CHAN(22, 9, 14, 17, 21),
++ MEM_VDI_PRP_VF_MEM_N = _MAKE_CHAN(23, 10, 14, 17, 21),
++
++ /* for vdi mem->vdi->mem */
++ MEM_VDI_MEM_P = _MAKE_CHAN(24, 8, NO_DMA, NO_DMA, 5),
++ MEM_VDI_MEM = _MAKE_CHAN(25, 9, NO_DMA, NO_DMA, 5),
++ MEM_VDI_MEM_N = _MAKE_CHAN(26, 10, NO_DMA, NO_DMA, 5),
++
++ /* fake channel for vdoa to link with IPU */
++ MEM_VDOA_MEM = _MAKE_CHAN(27, NO_DMA, NO_DMA, NO_DMA, NO_DMA),
++
++ MEM_PP_ADC = CHAN_NONE,
++ ADC_SYS2 = CHAN_NONE,
++
++} ipu_channel_t;
++
++/*!
++ * Enumeration of types of buffers for a logical channel.
++ */
++typedef enum {
++ IPU_OUTPUT_BUFFER = 0, /*!< Buffer for output from IPU */
++ IPU_ALPHA_IN_BUFFER = 1, /*!< Buffer for input to IPU */
++ IPU_GRAPH_IN_BUFFER = 2, /*!< Buffer for input to IPU */
++ IPU_VIDEO_IN_BUFFER = 3, /*!< Buffer for input to IPU */
++ IPU_INPUT_BUFFER = IPU_VIDEO_IN_BUFFER,
++ IPU_SEC_INPUT_BUFFER = IPU_GRAPH_IN_BUFFER,
++} ipu_buffer_t;
++
++#define IPU_PANEL_SERIAL 1
++#define IPU_PANEL_PARALLEL 2
++
++/*!
++ * Enumeration of ADC channel operation mode.
++ */
++typedef enum {
++ Disable,
++ WriteTemplateNonSeq,
++ ReadTemplateNonSeq,
++ WriteTemplateUnCon,
++ ReadTemplateUnCon,
++ WriteDataWithRS,
++ WriteDataWoRS,
++ WriteCmd
++} mcu_mode_t;
++
++/*!
++ * Enumeration of ADC channel addressing mode.
++ */
++typedef enum {
++ FullWoBE,
++ FullWithBE,
++ XY
++} display_addressing_t;
++
++/*!
++ * Union of initialization parameters for a logical channel.
++ */
++typedef union {
++ struct {
++ uint32_t csi;
++ uint32_t mipi_id;
++ uint32_t mipi_vc;
++ bool mipi_en;
++ bool interlaced;
++ } csi_mem;
++ struct {
++ uint32_t in_width;
++ uint32_t in_height;
++ uint32_t in_pixel_fmt;
++ uint32_t out_width;
++ uint32_t out_height;
++ uint32_t out_pixel_fmt;
++ uint32_t outh_resize_ratio;
++ uint32_t outv_resize_ratio;
++ uint32_t csi;
++ uint32_t mipi_id;
++ uint32_t mipi_vc;
++ bool mipi_en;
++ } csi_prp_enc_mem;
++ struct {
++ uint32_t in_width;
++ uint32_t in_height;
++ uint32_t in_pixel_fmt;
++ uint32_t out_width;
++ uint32_t out_height;
++ uint32_t out_pixel_fmt;
++ uint32_t outh_resize_ratio;
++ uint32_t outv_resize_ratio;
++ } mem_prp_enc_mem;
++ struct {
++ uint32_t in_width;
++ uint32_t in_height;
++ uint32_t in_pixel_fmt;
++ uint32_t out_width;
++ uint32_t out_height;
++ uint32_t out_pixel_fmt;
++ } mem_rot_enc_mem;
++ struct {
++ uint32_t in_width;
++ uint32_t in_height;
++ uint32_t in_pixel_fmt;
++ uint32_t out_width;
++ uint32_t out_height;
++ uint32_t out_pixel_fmt;
++ uint32_t outh_resize_ratio;
++ uint32_t outv_resize_ratio;
++ bool graphics_combine_en;
++ bool global_alpha_en;
++ bool key_color_en;
++ uint32_t in_g_pixel_fmt;
++ uint8_t alpha;
++ uint32_t key_color;
++ bool alpha_chan_en;
++ ipu_motion_sel motion_sel;
++ enum v4l2_field field_fmt;
++ uint32_t csi;
++ uint32_t mipi_id;
++ uint32_t mipi_vc;
++ bool mipi_en;
++ } csi_prp_vf_mem;
++ struct {
++ uint32_t in_width;
++ uint32_t in_height;
++ uint32_t in_pixel_fmt;
++ uint32_t out_width;
++ uint32_t out_height;
++ uint32_t out_pixel_fmt;
++ bool graphics_combine_en;
++ bool global_alpha_en;
++ bool key_color_en;
++ display_port_t disp;
++ uint32_t out_left;
++ uint32_t out_top;
++ } csi_prp_vf_adc;
++ struct {
++ uint32_t in_width;
++ uint32_t in_height;
++ uint32_t in_pixel_fmt;
++ uint32_t out_width;
++ uint32_t out_height;
++ uint32_t out_pixel_fmt;
++ uint32_t outh_resize_ratio;
++ uint32_t outv_resize_ratio;
++ bool graphics_combine_en;
++ bool global_alpha_en;
++ bool key_color_en;
++ uint32_t in_g_pixel_fmt;
++ uint8_t alpha;
++ uint32_t key_color;
++ bool alpha_chan_en;
++ ipu_motion_sel motion_sel;
++ enum v4l2_field field_fmt;
++ } mem_prp_vf_mem;
++ struct {
++ uint32_t temp;
++ } mem_prp_vf_adc;
++ struct {
++ uint32_t temp;
++ } mem_rot_vf_mem;
++ struct {
++ uint32_t in_width;
++ uint32_t in_height;
++ uint32_t in_pixel_fmt;
++ uint32_t out_width;
++ uint32_t out_height;
++ uint32_t out_pixel_fmt;
++ uint32_t outh_resize_ratio;
++ uint32_t outv_resize_ratio;
++ bool graphics_combine_en;
++ bool global_alpha_en;
++ bool key_color_en;
++ uint32_t in_g_pixel_fmt;
++ uint8_t alpha;
++ uint32_t key_color;
++ bool alpha_chan_en;
++ } mem_pp_mem;
++ struct {
++ uint32_t temp;
++ } mem_rot_mem;
++ struct {
++ uint32_t in_width;
++ uint32_t in_height;
++ uint32_t in_pixel_fmt;
++ uint32_t out_width;
++ uint32_t out_height;
++ uint32_t out_pixel_fmt;
++ bool graphics_combine_en;
++ bool global_alpha_en;
++ bool key_color_en;
++ display_port_t disp;
++ uint32_t out_left;
++ uint32_t out_top;
++ } mem_pp_adc;
++ struct {
++ uint32_t di;
++ bool interlaced;
++ uint32_t in_pixel_fmt;
++ uint32_t out_pixel_fmt;
++ } mem_dc_sync;
++ struct {
++ uint32_t temp;
++ } mem_sdc_fg;
++ struct {
++ uint32_t di;
++ bool interlaced;
++ uint32_t in_pixel_fmt;
++ uint32_t out_pixel_fmt;
++ bool alpha_chan_en;
++ } mem_dp_bg_sync;
++ struct {
++ uint32_t temp;
++ } mem_sdc_bg;
++ struct {
++ uint32_t di;
++ bool interlaced;
++ uint32_t in_pixel_fmt;
++ uint32_t out_pixel_fmt;
++ bool alpha_chan_en;
++ } mem_dp_fg_sync;
++ struct {
++ uint32_t di;
++ } direct_async;
++ struct {
++ display_port_t disp;
++ mcu_mode_t ch_mode;
++ uint32_t out_left;
++ uint32_t out_top;
++ } adc_sys1;
++ struct {
++ display_port_t disp;
++ mcu_mode_t ch_mode;
++ uint32_t out_left;
++ uint32_t out_top;
++ } adc_sys2;
++} ipu_channel_params_t;
++
++/*
++ * IPU_IRQF_ONESHOT - Interrupt is not reenabled after the irq handler finished.
++ */
++#define IPU_IRQF_NONE 0x00000000
++#define IPU_IRQF_ONESHOT 0x00000001
++
++/*!
++ * Enumeration of IPU interrupt sources.
++ */
++enum ipu_irq_line {
++ IPU_IRQ_CSI0_OUT_EOF = 0,
++ IPU_IRQ_CSI1_OUT_EOF = 1,
++ IPU_IRQ_CSI2_OUT_EOF = 2,
++ IPU_IRQ_CSI3_OUT_EOF = 3,
++ IPU_IRQ_VDIC_OUT_EOF = 5,
++ IPU_IRQ_VDI_P_IN_EOF = 8,
++ IPU_IRQ_VDI_C_IN_EOF = 9,
++ IPU_IRQ_VDI_N_IN_EOF = 10,
++ IPU_IRQ_PP_IN_EOF = 11,
++ IPU_IRQ_PRP_IN_EOF = 12,
++ IPU_IRQ_PRP_GRAPH_IN_EOF = 14,
++ IPU_IRQ_PP_GRAPH_IN_EOF = 15,
++ IPU_IRQ_PRP_ALPHA_IN_EOF = 17,
++ IPU_IRQ_PP_ALPHA_IN_EOF = 18,
++ IPU_IRQ_PRP_ENC_OUT_EOF = 20,
++ IPU_IRQ_PRP_VF_OUT_EOF = 21,
++ IPU_IRQ_PP_OUT_EOF = 22,
++ IPU_IRQ_BG_SYNC_EOF = 23,
++ IPU_IRQ_BG_ASYNC_EOF = 24,
++ IPU_IRQ_FG_SYNC_EOF = 27,
++ IPU_IRQ_DC_SYNC_EOF = 28,
++ IPU_IRQ_FG_ASYNC_EOF = 29,
++ IPU_IRQ_FG_ALPHA_SYNC_EOF = 31,
++
++ IPU_IRQ_FG_ALPHA_ASYNC_EOF = 33,
++ IPU_IRQ_DC_READ_EOF = 40,
++ IPU_IRQ_DC_ASYNC_EOF = 41,
++ IPU_IRQ_DC_CMD1_EOF = 42,
++ IPU_IRQ_DC_CMD2_EOF = 43,
++ IPU_IRQ_DC_MASK_EOF = 44,
++ IPU_IRQ_PRP_ENC_ROT_IN_EOF = 45,
++ IPU_IRQ_PRP_VF_ROT_IN_EOF = 46,
++ IPU_IRQ_PP_ROT_IN_EOF = 47,
++ IPU_IRQ_PRP_ENC_ROT_OUT_EOF = 48,
++ IPU_IRQ_PRP_VF_ROT_OUT_EOF = 49,
++ IPU_IRQ_PP_ROT_OUT_EOF = 50,
++ IPU_IRQ_BG_ALPHA_SYNC_EOF = 51,
++ IPU_IRQ_BG_ALPHA_ASYNC_EOF = 52,
++
++ IPU_IRQ_BG_SYNC_NFACK = 64 + 23,
++ IPU_IRQ_FG_SYNC_NFACK = 64 + 27,
++ IPU_IRQ_DC_SYNC_NFACK = 64 + 28,
++
++ IPU_IRQ_DP_SF_START = 448 + 2,
++ IPU_IRQ_DP_SF_END = 448 + 3,
++ IPU_IRQ_BG_SF_END = IPU_IRQ_DP_SF_END,
++ IPU_IRQ_DC_FC_0 = 448 + 8,
++ IPU_IRQ_DC_FC_1 = 448 + 9,
++ IPU_IRQ_DC_FC_2 = 448 + 10,
++ IPU_IRQ_DC_FC_3 = 448 + 11,
++ IPU_IRQ_DC_FC_4 = 448 + 12,
++ IPU_IRQ_DC_FC_6 = 448 + 13,
++ IPU_IRQ_VSYNC_PRE_0 = 448 + 14,
++ IPU_IRQ_VSYNC_PRE_1 = 448 + 15,
++
++ IPU_IRQ_COUNT
++};
++
++/*!
++ * Bitfield of Display Interface signal polarities.
++ */
++typedef struct {
++ unsigned datamask_en:1;
++ unsigned int_clk:1;
++ unsigned interlaced:1;
++ unsigned odd_field_first:1;
++ unsigned clksel_en:1;
++ unsigned clkidle_en:1;
++ unsigned data_pol:1; /* true = inverted */
++ unsigned clk_pol:1; /* true = rising edge */
++ unsigned enable_pol:1;
++ unsigned Hsync_pol:1; /* true = active high */
++ unsigned Vsync_pol:1;
++} ipu_di_signal_cfg_t;
++
++/*!
++ * Bitfield of CSI signal polarities and modes.
++ */
++
++typedef struct {
++ unsigned data_width:4;
++ unsigned clk_mode:3;
++ unsigned ext_vsync:1;
++ unsigned Vsync_pol:1;
++ unsigned Hsync_pol:1;
++ unsigned pixclk_pol:1;
++ unsigned data_pol:1;
++ unsigned sens_clksrc:1;
++ unsigned pack_tight:1;
++ unsigned force_eof:1;
++ unsigned data_en_pol:1;
++ unsigned data_fmt;
++ unsigned csi;
++ unsigned mclk;
++} ipu_csi_signal_cfg_t;
++
++/*!
++ * Enumeration of CSI data bus widths.
++ */
++enum {
++ IPU_CSI_DATA_WIDTH_4 = 0,
++ IPU_CSI_DATA_WIDTH_8 = 1,
++ IPU_CSI_DATA_WIDTH_10 = 3,
++ IPU_CSI_DATA_WIDTH_16 = 9,
++};
++
++/*!
++ * Enumeration of CSI clock modes.
++ */
++enum {
++ IPU_CSI_CLK_MODE_GATED_CLK,
++ IPU_CSI_CLK_MODE_NONGATED_CLK,
++ IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE,
++ IPU_CSI_CLK_MODE_CCIR656_INTERLACED,
++ IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_DDR,
++ IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR,
++ IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_DDR,
++ IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR,
++};
++
++enum {
++ IPU_CSI_MIPI_DI0,
++ IPU_CSI_MIPI_DI1,
++ IPU_CSI_MIPI_DI2,
++ IPU_CSI_MIPI_DI3,
++};
++
++typedef enum {
++ RGB,
++ YCbCr,
++ YUV
++} ipu_color_space_t;
++
++/*!
++ * Enumeration of ADC vertical sync mode.
++ */
++typedef enum {
++ VsyncNone,
++ VsyncInternal,
++ VsyncCSI,
++ VsyncExternal
++} vsync_t;
++
++typedef enum {
++ DAT,
++ CMD
++} cmddata_t;
++
++/*!
++ * Enumeration of ADC display update mode.
++ */
++typedef enum {
++ IPU_ADC_REFRESH_NONE,
++ IPU_ADC_AUTO_REFRESH,
++ IPU_ADC_AUTO_REFRESH_SNOOP,
++ IPU_ADC_SNOOPING,
++} ipu_adc_update_mode_t;
++
++/*!
++ * Enumeration of ADC display interface types (serial or parallel).
++ */
++enum {
++ IPU_ADC_IFC_MODE_SYS80_TYPE1,
++ IPU_ADC_IFC_MODE_SYS80_TYPE2,
++ IPU_ADC_IFC_MODE_SYS68K_TYPE1,
++ IPU_ADC_IFC_MODE_SYS68K_TYPE2,
++ IPU_ADC_IFC_MODE_3WIRE_SERIAL,
++ IPU_ADC_IFC_MODE_4WIRE_SERIAL,
++ IPU_ADC_IFC_MODE_5WIRE_SERIAL_CLK,
++ IPU_ADC_IFC_MODE_5WIRE_SERIAL_CS,
++};
++
++enum {
++ IPU_ADC_IFC_WIDTH_8,
++ IPU_ADC_IFC_WIDTH_16,
++};
++
++/*!
++ * Enumeration of ADC display interface burst mode.
++ */
++enum {
++ IPU_ADC_BURST_WCS,
++ IPU_ADC_BURST_WBLCK,
++ IPU_ADC_BURST_NONE,
++ IPU_ADC_BURST_SERIAL,
++};
++
++/*!
++ * Enumeration of ADC display interface RW signal timing modes.
++ */
++enum {
++ IPU_ADC_SER_NO_RW,
++ IPU_ADC_SER_RW_BEFORE_RS,
++ IPU_ADC_SER_RW_AFTER_RS,
++};
++
++/*!
++ * Bitfield of ADC signal polarities and modes.
++ */
++typedef struct {
++ unsigned data_pol:1;
++ unsigned clk_pol:1;
++ unsigned cs_pol:1;
++ unsigned rs_pol:1;
++ unsigned addr_pol:1;
++ unsigned read_pol:1;
++ unsigned write_pol:1;
++ unsigned Vsync_pol:1;
++ unsigned burst_pol:1;
++ unsigned burst_mode:2;
++ unsigned ifc_mode:3;
++ unsigned ifc_width:5;
++ unsigned ser_preamble_len:4;
++ unsigned ser_preamble:8;
++ unsigned ser_rw_mode:2;
++} ipu_adc_sig_cfg_t;
++
++/*!
++ * Enumeration of ADC template commands.
++ */
++enum {
++ RD_DATA,
++ RD_ACK,
++ RD_WAIT,
++ WR_XADDR,
++ WR_YADDR,
++ WR_ADDR,
++ WR_CMND,
++ WR_DATA,
++};
++
++/*!
++ * Enumeration of ADC template command flow control.
++ */
++enum {
++ SINGLE_STEP,
++ PAUSE,
++ STOP,
++};
++
++
++/*Define template constants*/
++#define ATM_ADDR_RANGE 0x20 /*offset address of DISP */
++#define TEMPLATE_BUF_SIZE 0x20 /*size of template */
++
++/*!
++ * Define to create ADC template command entry.
++ */
++#define ipu_adc_template_gen(oc, rs, fc, dat) (((rs) << 29) | ((fc) << 27) | \
++ ((oc) << 24) | (dat))
++
++typedef struct {
++ u32 reg;
++ u32 value;
++} ipu_lpmc_reg_t;
++
++#define IPU_LPMC_REG_READ 0x80000000L
++
++#define CSI_MCLK_VF 1
++#define CSI_MCLK_ENC 2
++#define CSI_MCLK_RAW 4
++#define CSI_MCLK_I2C 8
++
++struct ipu_soc;
++/* Common IPU API */
++struct ipu_soc *ipu_get_soc(int id);
++int32_t ipu_init_channel(struct ipu_soc *ipu, ipu_channel_t channel, ipu_channel_params_t *params);
++void ipu_uninit_channel(struct ipu_soc *ipu, ipu_channel_t channel);
++void ipu_disable_hsp_clk(struct ipu_soc *ipu);
++
++static inline bool ipu_can_rotate_in_place(ipu_rotate_mode_t rot)
++{
++#ifdef CONFIG_MXC_IPU_V3D
++ return (rot < IPU_ROTATE_HORIZ_FLIP);
++#else
++ return (rot < IPU_ROTATE_90_RIGHT);
++#endif
++}
++
++int32_t ipu_init_channel_buffer(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type,
++ uint32_t pixel_fmt,
++ uint16_t width, uint16_t height,
++ uint32_t stride,
++ ipu_rotate_mode_t rot_mode,
++ dma_addr_t phyaddr_0, dma_addr_t phyaddr_1,
++ dma_addr_t phyaddr_2,
++ uint32_t u_offset, uint32_t v_offset);
++
++int32_t ipu_update_channel_buffer(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type,
++ uint32_t bufNum, dma_addr_t phyaddr);
++
++int32_t ipu_update_channel_offset(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type,
++ uint32_t pixel_fmt,
++ uint16_t width, uint16_t height,
++ uint32_t stride,
++ uint32_t u, uint32_t v,
++ uint32_t vertical_offset, uint32_t horizontal_offset);
++
++int32_t ipu_select_buffer(struct ipu_soc *ipu, ipu_channel_t channel,
++ ipu_buffer_t type, uint32_t bufNum);
++int32_t ipu_select_multi_vdi_buffer(struct ipu_soc *ipu, uint32_t bufNum);
++
++int32_t ipu_link_channels(struct ipu_soc *ipu, ipu_channel_t src_ch, ipu_channel_t dest_ch);
++int32_t ipu_unlink_channels(struct ipu_soc *ipu, ipu_channel_t src_ch, ipu_channel_t dest_ch);
++
++int32_t ipu_is_channel_busy(struct ipu_soc *ipu, ipu_channel_t channel);
++int32_t ipu_check_buffer_ready(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type,
++ uint32_t bufNum);
++void ipu_clear_buffer_ready(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type,
++ uint32_t bufNum);
++uint32_t ipu_get_cur_buffer_idx(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type);
++int32_t ipu_enable_channel(struct ipu_soc *ipu, ipu_channel_t channel);
++int32_t ipu_disable_channel(struct ipu_soc *ipu, ipu_channel_t channel, bool wait_for_stop);
++int32_t ipu_swap_channel(struct ipu_soc *ipu, ipu_channel_t from_ch, ipu_channel_t to_ch);
++uint32_t ipu_channel_status(struct ipu_soc *ipu, ipu_channel_t channel);
++
++int32_t ipu_enable_csi(struct ipu_soc *ipu, uint32_t csi);
++int32_t ipu_disable_csi(struct ipu_soc *ipu, uint32_t csi);
++
++int ipu_lowpwr_display_enable(void);
++int ipu_lowpwr_display_disable(void);
++
++int ipu_enable_irq(struct ipu_soc *ipu, uint32_t irq);
++void ipu_disable_irq(struct ipu_soc *ipu, uint32_t irq);
++void ipu_clear_irq(struct ipu_soc *ipu, uint32_t irq);
++int ipu_request_irq(struct ipu_soc *ipu, uint32_t irq,
++ irqreturn_t(*handler) (int, void *),
++ uint32_t irq_flags, const char *devname, void *dev_id);
++void ipu_free_irq(struct ipu_soc *ipu, uint32_t irq, void *dev_id);
++bool ipu_get_irq_status(struct ipu_soc *ipu, uint32_t irq);
++void ipu_set_csc_coefficients(struct ipu_soc *ipu, ipu_channel_t channel, int32_t param[][3]);
++int32_t ipu_set_channel_bandmode(struct ipu_soc *ipu, ipu_channel_t channel,
++ ipu_buffer_t type, uint32_t band_height);
++
++/* two stripe calculations */
++struct stripe_param{
++ unsigned int input_width; /* width of the input stripe */
++ unsigned int output_width; /* width of the output stripe */
++ unsigned int input_column; /* the first column on the input stripe */
++ unsigned int output_column; /* the first column on the output stripe */
++ unsigned int idr;
++ /* inverse downisizing ratio parameter; expressed as a power of 2 */
++ unsigned int irr;
++ /* inverse resizing ratio parameter; expressed as a multiple of 2^-13 */
++};
++int ipu_calc_stripes_sizes(const unsigned int input_frame_width,
++ unsigned int output_frame_width,
++ const unsigned int maximal_stripe_width,
++ const unsigned long long cirr,
++ const unsigned int equal_stripes,
++ u32 input_pixelformat,
++ u32 output_pixelformat,
++ struct stripe_param *left,
++ struct stripe_param *right);
++
++/* SDC API */
++int32_t ipu_init_sync_panel(struct ipu_soc *ipu, int disp,
++ uint32_t pixel_clk,
++ uint16_t width, uint16_t height,
++ uint32_t pixel_fmt,
++ uint16_t h_start_width, uint16_t h_sync_width,
++ uint16_t h_end_width, uint16_t v_start_width,
++ uint16_t v_sync_width, uint16_t v_end_width,
++ uint32_t v_to_h_sync, ipu_di_signal_cfg_t sig);
++
++void ipu_uninit_sync_panel(struct ipu_soc *ipu, int disp);
++
++int32_t ipu_disp_set_window_pos(struct ipu_soc *ipu, ipu_channel_t channel, int16_t x_pos,
++ int16_t y_pos);
++int32_t ipu_disp_get_window_pos(struct ipu_soc *ipu, ipu_channel_t channel, int16_t *x_pos,
++ int16_t *y_pos);
++int32_t ipu_disp_set_global_alpha(struct ipu_soc *ipu, ipu_channel_t channel, bool enable,
++ uint8_t alpha);
++int32_t ipu_disp_set_color_key(struct ipu_soc *ipu, ipu_channel_t channel, bool enable,
++ uint32_t colorKey);
++int32_t ipu_disp_set_gamma_correction(struct ipu_soc *ipu, ipu_channel_t channel, bool enable,
++ int constk[], int slopek[]);
++
++int ipu_init_async_panel(struct ipu_soc *ipu, int disp, int type, uint32_t cycle_time,
++ uint32_t pixel_fmt, ipu_adc_sig_cfg_t sig);
++void ipu_disp_direct_write(struct ipu_soc *ipu, ipu_channel_t channel, u32 value, u32 offset);
++void ipu_reset_disp_panel(struct ipu_soc *ipu);
++
++/* CMOS Sensor Interface API */
++int32_t ipu_csi_init_interface(struct ipu_soc *ipu, uint16_t width, uint16_t height,
++ uint32_t pixel_fmt, ipu_csi_signal_cfg_t sig);
++
++int32_t ipu_csi_get_sensor_protocol(struct ipu_soc *ipu, uint32_t csi);
++
++int32_t ipu_csi_enable_mclk(struct ipu_soc *ipu, int src, bool flag, bool wait);
++
++static inline int32_t ipu_csi_enable_mclk_if(struct ipu_soc *ipu, int src, uint32_t csi,
++ bool flag, bool wait)
++{
++ return ipu_csi_enable_mclk(ipu, csi, flag, wait);
++}
++
++int ipu_csi_read_mclk_flag(void);
++
++void ipu_csi_flash_strobe(bool flag);
++
++void ipu_csi_get_window_size(struct ipu_soc *ipu, uint32_t *width, uint32_t *height, uint32_t csi);
++
++void ipu_csi_set_window_size(struct ipu_soc *ipu, uint32_t width, uint32_t height, uint32_t csi);
++
++void ipu_csi_set_window_pos(struct ipu_soc *ipu, uint32_t left, uint32_t top, uint32_t csi);
++
++uint32_t bytes_per_pixel(uint32_t fmt);
++
++bool ipu_ch_param_bad_alpha_pos(uint32_t fmt);
++
++struct ipuv3_fb_platform_data {
++ char disp_dev[32];
++ u32 interface_pix_fmt;
++ char *mode_str;
++ int default_bpp;
++ bool int_clk;
++
++ /* reserved mem */
++ resource_size_t res_base[2];
++ resource_size_t res_size[2];
++
++ /*
++ * Late init to avoid display channel being
++ * re-initialized as we've probably setup the
++ * channel in bootloader.
++ */
++ bool late_init;
++};
++
++#endif /* __LINUX_IPU_V3_H_ */
+diff -Nur linux-4.1.3/include/linux/mfd/mxc-hdmi-core.h linux-xbian-imx6/include/linux/mfd/mxc-hdmi-core.h
+--- linux-4.1.3/include/linux/mfd/mxc-hdmi-core.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/include/linux/mfd/mxc-hdmi-core.h 2015-07-27 23:13:09.586777757 +0200
+@@ -0,0 +1,68 @@
++/*
++ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ */
++#ifndef __LINUX_MXC_HDMI_CORE_H_
++#define __LINUX_MXC_HDMI_CORE_H_
++
++#include <video/mxc_edid.h>
++
++#include <sound/core.h>
++#include <sound/pcm.h>
++#include <sound/pcm_params.h>
++#include <sound/soc.h>
++
++#define IRQ_DISABLE_SUCCEED 0
++#define IRQ_DISABLE_FAIL 1
++
++bool hdmi_check_overflow(void);
++
++u8 hdmi_readb(unsigned int reg);
++void hdmi_writeb(u8 value, unsigned int reg);
++void hdmi_mask_writeb(u8 data, unsigned int addr, u8 shift, u8 mask);
++unsigned int hdmi_read4(unsigned int reg);
++void hdmi_write4(unsigned int value, unsigned int reg);
++
++void hdmi_irq_init(void);
++void hdmi_irq_enable(int irq);
++unsigned int hdmi_irq_disable(int irq);
++
++void hdmi_set_sample_rate(unsigned int rate);
++void hdmi_set_dma_mode(unsigned int dma_running);
++void hdmi_init_clk_regenerator(void);
++void hdmi_clk_regenerator_update_pixel_clock(u32 pixclock);
++
++void hdmi_set_edid_cfg(int edid_status, struct mxc_edid_cfg *cfg);
++int hdmi_get_edid_cfg(struct mxc_edid_cfg *cfg);
++
++extern int mxc_hdmi_ipu_id;
++extern int mxc_hdmi_disp_id;
++
++void hdmi_set_registered(int registered);
++int hdmi_get_registered(void);
++int mxc_hdmi_abort_stream(void);
++int mxc_hdmi_register_audio(struct snd_pcm_substream *substream);
++void mxc_hdmi_unregister_audio(struct snd_pcm_substream *substream);
++void hdmi_set_dvi_mode(unsigned int state);
++unsigned int hdmi_set_cable_state(unsigned int state);
++unsigned int hdmi_set_blank_state(unsigned int state);
++int check_hdmi_state(void);
++
++void hdmi_cec_start_device(void);
++void hdmi_cec_stop_device(void);
++
++#endif
+diff -Nur linux-4.1.3/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h linux-xbian-imx6/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
+--- linux-4.1.3/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h 2015-07-27 23:13:09.590763539 +0200
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright (C) 2012 Freescale Semiconductor, Inc.
++ * Copyright (C) 2012-2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+@@ -123,6 +123,9 @@
+ #define IMX6Q_GPR1_USB_OTG_ID_SEL_ENET_RX_ER 0x0
+ #define IMX6Q_GPR1_USB_OTG_ID_SEL_GPIO_1 BIT(13)
+ #define IMX6Q_GPR1_GINT BIT(12)
++#define IMX6Q_GPR1_GINT_MASK BIT(12)
++#define IMX6Q_GPR1_GINT_CLEAR 0x0
++#define IMX6Q_GPR1_GINT_ASSERT BIT(12)
+ #define IMX6Q_GPR1_ADDRS3_MASK (0x3 << 10)
+ #define IMX6Q_GPR1_ADDRS3_32MB (0x0 << 10)
+ #define IMX6Q_GPR1_ADDRS3_64MB (0x1 << 10)
+@@ -285,15 +288,15 @@
+ #define IMX6Q_GPR10_OCRAM_TZ_ADDR_MASK (0x3f << 5)
+ #define IMX6Q_GPR10_OCRAM_TZ_EN_MASK BIT(4)
+ #define IMX6Q_GPR10_DCIC2_MUX_CTL_MASK (0x3 << 2)
+-#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU1_DI0 (0x0 << 2)
+-#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU1_DI1 (0x1 << 2)
+-#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU2_DI0 (0x2 << 2)
+-#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU2_DI1 (0x3 << 2)
++#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU1_DI1 (0x0 << 2)
++#define IMX6Q_GPR10_DCIC2_MUX_CTL_LVDS0 (0x1 << 2)
++#define IMX6Q_GPR10_DCIC2_MUX_CTL_LVDS1 (0x2 << 2)
++#define IMX6Q_GPR10_DCIC2_MUX_CTL_MIPI (0x3 << 2)
+ #define IMX6Q_GPR10_DCIC1_MUX_CTL_MASK (0x3 << 0)
+ #define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU1_DI0 (0x0 << 0)
+-#define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU1_DI1 (0x1 << 0)
+-#define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU2_DI0 (0x2 << 0)
+-#define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU2_DI1 (0x3 << 0)
++#define IMX6Q_GPR10_DCIC1_MUX_CTL_LVDS0 (0x1 << 0)
++#define IMX6Q_GPR10_DCIC1_MUX_CTL_LVDS1 (0x2 << 0)
++#define IMX6Q_GPR10_DCIC1_MUX_CTL_HDMI (0x3 << 0)
+
+ #define IMX6Q_GPR12_ARMP_IPG_CLK_EN BIT(27)
+ #define IMX6Q_GPR12_ARMP_AHB_CLK_EN BIT(26)
+@@ -302,6 +305,7 @@
+ #define IMX6Q_GPR12_DEVICE_TYPE (0xf << 12)
+ #define IMX6Q_GPR12_PCIE_CTL_2 BIT(10)
+ #define IMX6Q_GPR12_LOS_LEVEL (0x1f << 4)
++#define IMX6Q_GPR12_LOS_LEVEL_9 (0x9 << 4)
+
+ #define IMX6Q_GPR13_SDMA_STOP_REQ BIT(30)
+ #define IMX6Q_GPR13_CAN2_STOP_REQ BIT(29)
+@@ -392,6 +396,16 @@
+ #define IMX6Q_GPR13_SATA_MPLL_CLK_EN BIT(1)
+ #define IMX6Q_GPR13_SATA_TX_EDGE_RATE BIT(0)
+
++/* For imx6dl iomux gpr register field definitions */
++#define IMX6DL_GPR3_LVDS1_MUX_CTL_MASK (0x3 << 8)
++#define IMX6DL_GPR3_LVDS1_MUX_CTL_IPU1_DI0 (0x0 << 8)
++#define IMX6DL_GPR3_LVDS1_MUX_CTL_IPU1_DI1 (0x1 << 8)
++#define IMX6DL_GPR3_LVDS1_MUX_CTL_LCDIF (0x2 << 8)
++#define IMX6DL_GPR3_LVDS0_MUX_CTL_MASK (0x3 << 6)
++#define IMX6DL_GPR3_LVDS0_MUX_CTL_IPU1_DI0 (0x0 << 6)
++#define IMX6DL_GPR3_LVDS0_MUX_CTL_IPU1_DI1 (0x1 << 6)
++#define IMX6DL_GPR3_LVDS0_MUX_CTL_LCDIF (0x2 << 6)
++
+ /* For imx6sl iomux gpr register field define */
+ #define IMX6SL_GPR1_FEC_CLOCK_MUX1_SEL_MASK (0x3 << 17)
+ #define IMX6SL_GPR1_FEC_CLOCK_MUX2_SEL_MASK (0x1 << 14)
+@@ -407,6 +421,15 @@
+ #define IMX6SX_GPR1_FEC_CLOCK_PAD_DIR_MASK (0x3 << 17)
+ #define IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_EXT (0x3 << 13)
+
++#define IMX6SX_GPR2_MQS_OVERSAMPLE_MASK (0x1 << 26)
++#define IMX6SX_GPR2_MQS_OVERSAMPLE_SHIFT (26)
++#define IMX6SX_GPR2_MQS_EN_MASK (0x1 << 25)
++#define IMX6SX_GPR2_MQS_EN_SHIFT (25)
++#define IMX6SX_GPR2_MQS_SW_RST_MASK (0x1 << 24)
++#define IMX6SX_GPR2_MQS_SW_RST_SHIFT (24)
++#define IMX6SX_GPR2_MQS_CLK_DIV_MASK (0xFF << 16)
++#define IMX6SX_GPR2_MQS_CLK_DIV_SHIFT (16)
++
+ #define IMX6SX_GPR4_FEC_ENET1_STOP_REQ (0x1 << 3)
+ #define IMX6SX_GPR4_FEC_ENET2_STOP_REQ (0x1 << 4)
+
+@@ -435,4 +458,11 @@
+ #define IMX6SX_GPR5_DISP_MUX_DCIC1_LVDS (0x1 << 1)
+ #define IMX6SX_GPR5_DISP_MUX_DCIC1_MASK (0x1 << 1)
+
++#define IMX6SX_GPR5_PCIE_BTNRST BIT(19)
++#define IMX6SX_GPR5_PCIE_PERST BIT(18)
++
++#define IMX6SX_GPR12_PCIE_PM_TURN_OFF BIT(16)
++#define IMX6SX_GPR12_PCIE_TEST_PD BIT(30)
++#define IMX6SX_GPR12_RX_EQ_MASK (0x7 << 0)
++#define IMX6SX_GPR12_RX_EQ_2 (0x2 << 0)
+ #endif /* __LINUX_IMX6Q_IOMUXC_GPR_H */
+diff -Nur linux-4.1.3/include/linux/mipi_csi2.h linux-xbian-imx6/include/linux/mipi_csi2.h
+--- linux-4.1.3/include/linux/mipi_csi2.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/include/linux/mipi_csi2.h 2015-07-27 23:13:09.598735098 +0200
+@@ -0,0 +1,93 @@
++/*
++ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++#ifndef __INCLUDE_MIPI_CSI2_H
++#define __INCLUDE_MIPI_CSI2_H
++
++/* MIPI CSI2 registers */
++#define MIPI_CSI2_REG(offset) (offset)
++
++#define MIPI_CSI2_VERSION MIPI_CSI2_REG(0x000)
++#define MIPI_CSI2_N_LANES MIPI_CSI2_REG(0x004)
++#define MIPI_CSI2_PHY_SHUTDOWNZ MIPI_CSI2_REG(0x008)
++#define MIPI_CSI2_DPHY_RSTZ MIPI_CSI2_REG(0x00c)
++#define MIPI_CSI2_CSI2_RESETN MIPI_CSI2_REG(0x010)
++#define MIPI_CSI2_PHY_STATE MIPI_CSI2_REG(0x014)
++#define MIPI_CSI2_DATA_IDS_1 MIPI_CSI2_REG(0x018)
++#define MIPI_CSI2_DATA_IDS_2 MIPI_CSI2_REG(0x01c)
++#define MIPI_CSI2_ERR1 MIPI_CSI2_REG(0x020)
++#define MIPI_CSI2_ERR2 MIPI_CSI2_REG(0x024)
++#define MIPI_CSI2_MASK1 MIPI_CSI2_REG(0x028)
++#define MIPI_CSI2_MASK2 MIPI_CSI2_REG(0x02c)
++#define MIPI_CSI2_PHY_TST_CTRL0 MIPI_CSI2_REG(0x030)
++#define MIPI_CSI2_PHY_TST_CTRL1 MIPI_CSI2_REG(0x034)
++#define MIPI_CSI2_SFT_RESET MIPI_CSI2_REG(0xf00)
++
++/* mipi data type */
++#define MIPI_DT_YUV420 0x18 /* YYY.../UYVY.... */
++#define MIPI_DT_YUV420_LEGACY 0x1a /* UYY.../VYY... */
++#define MIPI_DT_YUV422 0x1e /* UYVY... */
++#define MIPI_DT_RGB444 0x20
++#define MIPI_DT_RGB555 0x21
++#define MIPI_DT_RGB565 0x22
++#define MIPI_DT_RGB666 0x23
++#define MIPI_DT_RGB888 0x24
++#define MIPI_DT_RAW6 0x28
++#define MIPI_DT_RAW7 0x29
++#define MIPI_DT_RAW8 0x2a
++#define MIPI_DT_RAW10 0x2b
++#define MIPI_DT_RAW12 0x2c
++#define MIPI_DT_RAW14 0x2d
++
++
++struct mipi_csi2_info;
++/* mipi csi2 API */
++struct mipi_csi2_info *mipi_csi2_get_info(void);
++
++bool mipi_csi2_enable(struct mipi_csi2_info *info);
++
++bool mipi_csi2_disable(struct mipi_csi2_info *info);
++
++bool mipi_csi2_get_status(struct mipi_csi2_info *info);
++
++int mipi_csi2_get_bind_ipu(struct mipi_csi2_info *info);
++
++unsigned int mipi_csi2_get_bind_csi(struct mipi_csi2_info *info);
++
++unsigned int mipi_csi2_get_virtual_channel(struct mipi_csi2_info *info);
++
++unsigned int mipi_csi2_set_lanes(struct mipi_csi2_info *info);
++
++unsigned int mipi_csi2_set_datatype(struct mipi_csi2_info *info,
++ unsigned int datatype);
++
++unsigned int mipi_csi2_get_datatype(struct mipi_csi2_info *info);
++
++unsigned int mipi_csi2_dphy_status(struct mipi_csi2_info *info);
++
++unsigned int mipi_csi2_get_error1(struct mipi_csi2_info *info);
++
++unsigned int mipi_csi2_get_error2(struct mipi_csi2_info *info);
++
++int mipi_csi2_pixelclk_enable(struct mipi_csi2_info *info);
++
++void mipi_csi2_pixelclk_disable(struct mipi_csi2_info *info);
++
++int mipi_csi2_reset(struct mipi_csi2_info *info);
++
++#endif
+diff -Nur linux-4.1.3/include/linux/mipi_dsi.h linux-xbian-imx6/include/linux/mipi_dsi.h
+--- linux-4.1.3/include/linux/mipi_dsi.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/include/linux/mipi_dsi.h 2015-07-27 23:13:09.598735098 +0200
+@@ -0,0 +1,171 @@
++/*
++ * Copyright (C) 2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++#ifndef __INCLUDE_MIPI_DSI_H
++#define __INCLUDE_MIPI_DSI_H
++
++#define MIPI_DSI_VERSION (0x000)
++#define MIPI_DSI_PWR_UP (0x004)
++#define MIPI_DSI_CLKMGR_CFG (0x008)
++#define MIPI_DSI_DPI_CFG (0x00c)
++#define MIPI_DSI_DBI_CFG (0x010)
++#define MIPI_DSI_DBIS_CMDSIZE (0x014)
++#define MIPI_DSI_PCKHDL_CFG (0x018)
++#define MIPI_DSI_VID_MODE_CFG (0x01c)
++#define MIPI_DSI_VID_PKT_CFG (0x020)
++#define MIPI_DSI_CMD_MODE_CFG (0x024)
++#define MIPI_DSI_TMR_LINE_CFG (0x028)
++#define MIPI_DSI_VTIMING_CFG (0x02c)
++#define MIPI_DSI_PHY_TMR_CFG (0x030)
++#define MIPI_DSI_GEN_HDR (0x034)
++#define MIPI_DSI_GEN_PLD_DATA (0x038)
++#define MIPI_DSI_CMD_PKT_STATUS (0x03c)
++#define MIPI_DSI_TO_CNT_CFG (0x040)
++#define MIPI_DSI_ERROR_ST0 (0x044)
++#define MIPI_DSI_ERROR_ST1 (0x048)
++#define MIPI_DSI_ERROR_MSK0 (0x04c)
++#define MIPI_DSI_ERROR_MSK1 (0x050)
++#define MIPI_DSI_PHY_RSTZ (0x054)
++#define MIPI_DSI_PHY_IF_CFG (0x058)
++#define MIPI_DSI_PHY_IF_CTRL (0x05c)
++#define MIPI_DSI_PHY_STATUS (0x060)
++#define MIPI_DSI_PHY_TST_CTRL0 (0x064)
++#define MIPI_DSI_PHY_TST_CTRL1 (0x068)
++
++#define DSI_PWRUP_RESET (0x0 << 0)
++#define DSI_PWRUP_POWERUP (0x1 << 0)
++
++#define DSI_DPI_CFG_VID_SHIFT (0)
++#define DSI_DPI_CFG_VID_MASK (0x3)
++#define DSI_DPI_CFG_COLORCODE_SHIFT (2)
++#define DSI_DPI_CFG_COLORCODE_MASK (0x7)
++#define DSI_DPI_CFG_DATAEN_ACT_LOW (0x1 << 5)
++#define DSI_DPI_CFG_DATAEN_ACT_HIGH (0x0 << 5)
++#define DSI_DPI_CFG_VSYNC_ACT_LOW (0x1 << 6)
++#define DSI_DPI_CFG_VSYNC_ACT_HIGH (0x0 << 6)
++#define DSI_DPI_CFG_HSYNC_ACT_LOW (0x1 << 7)
++#define DSI_DPI_CFG_HSYNC_ACT_HIGH (0x0 << 7)
++#define DSI_DPI_CFG_SHUTD_ACT_LOW (0x1 << 8)
++#define DSI_DPI_CFG_SHUTD_ACT_HIGH (0x0 << 8)
++#define DSI_DPI_CFG_COLORMODE_ACT_LOW (0x1 << 9)
++#define DSI_DPI_CFG_COLORMODE_ACT_HIGH (0x0 << 9)
++#define DSI_DPI_CFG_EN18LOOSELY (0x1 << 10)
++
++#define DSI_PCKHDL_CFG_EN_EOTP_TX (0x1 << 0)
++#define DSI_PCKHDL_CFG_EN_EOTP_RX (0x1 << 1)
++#define DSI_PCKHDL_CFG_EN_BTA (0x1 << 2)
++#define DSI_PCKHDL_CFG_EN_ECC_RX (0x1 << 3)
++#define DSI_PCKHDL_CFG_EN_CRC_RX (0x1 << 4)
++#define DSI_PCKHDL_CFG_GEN_VID_RX_MASK (0x3)
++#define DSI_PCKHDL_CFG_GEN_VID_RX_SHIFT (5)
++
++#define DSI_VID_MODE_CFG_EN (0x1 << 0)
++#define DSI_VID_MODE_CFG_EN_BURSTMODE (0x3 << 1)
++#define DSI_VID_MODE_CFG_TYPE_MASK (0x3)
++#define DSI_VID_MODE_CFG_TYPE_SHIFT (1)
++#define DSI_VID_MODE_CFG_EN_LP_VSA (0x1 << 3)
++#define DSI_VID_MODE_CFG_EN_LP_VBP (0x1 << 4)
++#define DSI_VID_MODE_CFG_EN_LP_VFP (0x1 << 5)
++#define DSI_VID_MODE_CFG_EN_LP_VACT (0x1 << 6)
++#define DSI_VID_MODE_CFG_EN_LP_HBP (0x1 << 7)
++#define DSI_VID_MODE_CFG_EN_LP_HFP (0x1 << 8)
++#define DSI_VID_MODE_CFG_EN_MULTI_PKT (0x1 << 9)
++#define DSI_VID_MODE_CFG_EN_NULL_PKT (0x1 << 10)
++#define DSI_VID_MODE_CFG_EN_FRAME_ACK (0x1 << 11)
++#define DSI_VID_MODE_CFG_EN_LP_MODE (DSI_VID_MODE_CFG_EN_LP_VSA | \
++ DSI_VID_MODE_CFG_EN_LP_VBP | \
++ DSI_VID_MODE_CFG_EN_LP_VFP | \
++ DSI_VID_MODE_CFG_EN_LP_HFP | \
++ DSI_VID_MODE_CFG_EN_LP_HBP | \
++ DSI_VID_MODE_CFG_EN_LP_VACT)
++
++
++
++#define DSI_VID_PKT_CFG_VID_PKT_SZ_MASK (0x7ff)
++#define DSI_VID_PKT_CFG_VID_PKT_SZ_SHIFT (0)
++#define DSI_VID_PKT_CFG_NUM_CHUNKS_MASK (0x3ff)
++#define DSI_VID_PKT_CFG_NUM_CHUNKS_SHIFT (11)
++#define DSI_VID_PKT_CFG_NULL_PKT_SZ_MASK (0x3ff)
++#define DSI_VID_PKT_CFG_NULL_PKT_SZ_SHIFT (21)
++
++#define MIPI_DSI_CMD_MODE_CFG_EN_LOWPOWER (0x1FFF)
++#define MIPI_DSI_CMD_MODE_CFG_EN_CMD_MODE (0x1 << 0)
++
++#define DSI_TME_LINE_CFG_HSA_TIME_MASK (0x1ff)
++#define DSI_TME_LINE_CFG_HSA_TIME_SHIFT (0)
++#define DSI_TME_LINE_CFG_HBP_TIME_MASK (0x1ff)
++#define DSI_TME_LINE_CFG_HBP_TIME_SHIFT (9)
++#define DSI_TME_LINE_CFG_HLINE_TIME_MASK (0x3fff)
++#define DSI_TME_LINE_CFG_HLINE_TIME_SHIFT (18)
++
++#define DSI_VTIMING_CFG_VSA_LINES_MASK (0xf)
++#define DSI_VTIMING_CFG_VSA_LINES_SHIFT (0)
++#define DSI_VTIMING_CFG_VBP_LINES_MASK (0x3f)
++#define DSI_VTIMING_CFG_VBP_LINES_SHIFT (4)
++#define DSI_VTIMING_CFG_VFP_LINES_MASK (0x3f)
++#define DSI_VTIMING_CFG_VFP_LINES_SHIFT (10)
++#define DSI_VTIMING_CFG_V_ACT_LINES_MASK (0x7ff)
++#define DSI_VTIMING_CFG_V_ACT_LINES_SHIFT (16)
++
++#define DSI_PHY_TMR_CFG_BTA_TIME_MASK (0xfff)
++#define DSI_PHY_TMR_CFG_BTA_TIME_SHIFT (0)
++#define DSI_PHY_TMR_CFG_LP2HS_TIME_MASK (0xff)
++#define DSI_PHY_TMR_CFG_LP2HS_TIME_SHIFT (12)
++#define DSI_PHY_TMR_CFG_HS2LP_TIME_MASK (0xff)
++#define DSI_PHY_TMR_CFG_HS2LP_TIME_SHIFT (20)
++
++#define DSI_PHY_IF_CFG_N_LANES_MASK (0x3)
++#define DSI_PHY_IF_CFG_N_LANES_SHIFT (0)
++#define DSI_PHY_IF_CFG_WAIT_TIME_MASK (0xff)
++#define DSI_PHY_IF_CFG_WAIT_TIME_SHIFT (2)
++
++#define DSI_PHY_RSTZ_EN_CLK (0x1 << 2)
++#define DSI_PHY_RSTZ_DISABLE_RST (0x1 << 1)
++#define DSI_PHY_RSTZ_DISABLE_SHUTDOWN (0x1 << 0)
++#define DSI_PHY_RSTZ_RST (0x0)
++
++#define DSI_PHY_STATUS_LOCK (0x1 << 0)
++#define DSI_PHY_STATUS_STOPSTATE_CLK_LANE (0x1 << 2)
++
++#define DSI_GEN_HDR_TYPE_MASK (0xff)
++#define DSI_GEN_HDR_TYPE_SHIFT (0)
++#define DSI_GEN_HDR_DATA_MASK (0xffff)
++#define DSI_GEN_HDR_DATA_SHIFT (8)
++
++#define DSI_CMD_PKT_STATUS_GEN_CMD_EMPTY (0x1 << 0)
++#define DSI_CMD_PKT_STATUS_GEN_CMD_FULL (0x1 << 1)
++#define DSI_CMD_PKT_STATUS_GEN_PLD_W_EMPTY (0x1 << 2)
++#define DSI_CMD_PKT_STATUS_GEN_PLD_W_FULL (0x1 << 3)
++#define DSI_CMD_PKT_STATUS_GEN_PLD_R_EMPTY (0x1 << 4)
++#define DSI_CMD_PKT_STATUS_GEN_RD_CMD_BUSY (0x1 << 6)
++
++#define DSI_ERROR_MSK0_ALL_MASK (0x1fffff)
++#define DSI_ERROR_MSK1_ALL_MASK (0x3ffff)
++
++#define DSI_PHY_IF_CTRL_RESET (0x0)
++#define DSI_PHY_IF_CTRL_TX_REQ_CLK_HS (0x1 << 0)
++#define DSI_PHY_IF_CTRL_TX_REQ_CLK_ULPS (0x1 << 1)
++#define DSI_PHY_IF_CTRL_TX_EXIT_CLK_ULPS (0x1 << 2)
++#define DSI_PHY_IF_CTRL_TX_REQ_DATA_ULPS (0x1 << 3)
++#define DSI_PHY_IF_CTRL_TX_EXIT_DATA_ULPS (0x1 << 4)
++#define DSI_PHY_IF_CTRL_TX_TRIG_MASK (0xF)
++#define DSI_PHY_IF_CTRL_TX_TRIG_SHIFT (5)
++
++#define DSI_PHY_CLK_INIT_COMMAND (0x44)
++#define DSI_GEN_PLD_DATA_BUF_SIZE (0x4)
++#endif
+diff -Nur linux-4.1.3/include/linux/mmc/host.h linux-xbian-imx6/include/linux/mmc/host.h
+--- linux-4.1.3/include/linux/mmc/host.h 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/include/linux/mmc/host.h 2015-07-27 23:13:09.602720875 +0200
+@@ -300,6 +300,11 @@
+ unsigned long clkgate_delay;
+ #endif
+
++ /* card specific properties to deal with power and reset */
++ struct regulator *card_regulator; /* External VCC needed by the card */
++ struct gpio_desc *card_reset_gpios[2]; /* External resets, active low */
++ struct clk *card_clk; /* External clock needed by the card */
++
+ /* host specific block data */
+ unsigned int max_seg_size; /* see blk_queue_max_segment_size */
+ unsigned short max_segs; /* see blk_queue_max_segments */
+diff -Nur linux-4.1.3/include/linux/mm_types.h linux-xbian-imx6/include/linux/mm_types.h
+--- linux-4.1.3/include/linux/mm_types.h 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/include/linux/mm_types.h 2015-07-27 23:13:09.602720875 +0200
+@@ -23,7 +23,7 @@
+ struct address_space;
+ struct mem_cgroup;
+
+-#define USE_SPLIT_PTE_PTLOCKS (NR_CPUS >= CONFIG_SPLIT_PTLOCK_CPUS)
++#define USE_SPLIT_PTE_PTLOCKS (0)
+ #define USE_SPLIT_PMD_PTLOCKS (USE_SPLIT_PTE_PTLOCKS && \
+ IS_ENABLED(CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK))
+ #define ALLOC_SPLIT_PTLOCKS (SPINLOCK_SIZE > BITS_PER_LONG/8)
+diff -Nur linux-4.1.3/include/linux/mxc_asrc.h linux-xbian-imx6/include/linux/mxc_asrc.h
+--- linux-4.1.3/include/linux/mxc_asrc.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/include/linux/mxc_asrc.h 2015-07-27 23:13:09.606706653 +0200
+@@ -0,0 +1,389 @@
++/*
++ * Copyright 2008-2014 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ *
++ * @file mxc_asrc.h
++ *
++ * @brief i.MX Asynchronous Sample Rate Converter
++ *
++ * @ingroup Audio
++ */
++
++#ifndef __MXC_ASRC_H__
++#define __MXC_ASRC_H__
++
++#include <uapi/linux/mxc_asrc.h>
++#include <linux/scatterlist.h>
++
++#define ASRC_DMA_BUFFER_NUM 2
++#define ASRC_INPUTFIFO_THRESHOLD 32
++#define ASRC_OUTPUTFIFO_THRESHOLD 32
++#define ASRC_FIFO_THRESHOLD_MIN 0
++#define ASRC_FIFO_THRESHOLD_MAX 63
++#define ASRC_DMA_BUFFER_SIZE (1024 * 48 * 4)
++#define ASRC_MAX_BUFFER_SIZE (1024 * 48)
++#define ASRC_OUTPUT_LAST_SAMPLE_DEFAULT_MAX 32
++#define ASRC_OUTPUT_LAST_SAMPLE_DEFAULT 16
++
++
++/* Ideal Ratio mode doesn't care the outclk frequency, so be fixed */
++#define ASRC_PRESCALER_IDEAL_RATIO 5
++/* SPDIF rxclk pulse rate is 128 * samplerate, so 2 ^ 7 */
++#define ASRC_PRESCALER_SPDIF_RX 7
++/* SPDIF txclk pulse rate is 64 * samplerate, so 2 ^ 6 */
++#define ASRC_PRESCALER_SPDIF_TX 6
++/* I2S bclk is 16 * 2 = 32, so 2 ^ 5 */
++#define ASRC_PRESCALER_I2S_16BIT 5
++/* I2S bclk is 24 * 2 = 48 -> 64, so 2 ^ 6 */
++#define ASRC_PRESCALER_I2S_24BIT 6
++
++
++#define REG_ASRCTR 0x00
++#define REG_ASRIER 0x04
++#define REG_ASRCNCR 0x0C
++#define REG_ASRCFG 0x10
++#define REG_ASRCSR 0x14
++
++#define REG_ASRCDR1 0x18
++#define REG_ASRCDR2 0x1C
++#define REG_ASRCDR(x) ((x < 2) ? REG_ASRCDR1 : REG_ASRCDR2)
++
++#define REG_ASRSTR 0x20
++#define REG_ASRRA 0x24
++#define REG_ASRRB 0x28
++#define REG_ASRRC 0x2C
++#define REG_ASRPM1 0x40
++#define REG_ASRPM2 0x44
++#define REG_ASRPM3 0x48
++#define REG_ASRPM4 0x4C
++#define REG_ASRPM5 0x50
++#define REG_ASRTFR1 0x54
++#define REG_ASRCCR 0x5C
++
++#define REG_ASRDIA 0x60
++#define REG_ASRDOA 0x64
++#define REG_ASRDIB 0x68
++#define REG_ASRDOB 0x6C
++#define REG_ASRDIC 0x70
++#define REG_ASRDOC 0x74
++#define REG_ASRDI(x) (REG_ASRDIA + (x << 3))
++#define REG_ASRDO(x) (REG_ASRDOA + (x << 3))
++
++#define REG_ASRIDRHA 0x80
++#define REG_ASRIDRLA 0x84
++#define REG_ASRIDRHB 0x88
++#define REG_ASRIDRLB 0x8C
++#define REG_ASRIDRHC 0x90
++#define REG_ASRIDRLC 0x94
++#define REG_ASRIDRH(x) (REG_ASRIDRHA + (x << 3))
++#define REG_ASRIDRL(x) (REG_ASRIDRLA + (x << 3))
++
++#define REG_ASR76K 0x98
++#define REG_ASR56K 0x9C
++
++#define REG_ASRMCRA 0xA0
++#define REG_ASRFSTA 0xA4
++#define REG_ASRMCRB 0xA8
++#define REG_ASRFSTB 0xAC
++#define REG_ASRMCRC 0xB0
++#define REG_ASRFSTC 0xB4
++#define REG_ASRMCR(x) (REG_ASRMCRA + (x << 3))
++#define REG_ASRFST(x) (REG_ASRFSTA + (x << 3))
++
++#define REG_ASRMCR1A 0xC0
++#define REG_ASRMCR1B 0xC4
++#define REG_ASRMCR1C 0xC8
++#define REG_ASRMCR1(x) (REG_ASRMCR1A + (x << 2))
++
++
++/* REG0 0x00 REG_ASRCTR */
++#define ASRCTR_ATSx_SHIFT(x) (20 + x)
++#define ASRCTR_ATSx_MASK(x) (1 << ASRCTR_ATSx_SHIFT(x))
++#define ASRCTR_ATS(x) (1 << ASRCTR_ATSx_SHIFT(x))
++#define ASRCTR_USRx_SHIFT(x) (14 + (x << 1))
++#define ASRCTR_USRx_MASK(x) (1 << ASRCTR_USRx_SHIFT(x))
++#define ASRCTR_USR(x) (1 << ASRCTR_USRx_SHIFT(x))
++#define ASRCTR_IDRx_SHIFT(x) (13 + (x << 1))
++#define ASRCTR_IDRx_MASK(x) (1 << ASRCTR_IDRx_SHIFT(x))
++#define ASRCTR_IDR(x) (1 << ASRCTR_IDRx_SHIFT(x))
++#define ASRCTR_SRST_SHIFT 4
++#define ASRCTR_SRST_MASK (1 << ASRCTR_SRST_SHIFT)
++#define ASRCTR_SRST (1 << ASRCTR_SRST_SHIFT)
++#define ASRCTR_ASRCEx_SHIFT(x) (1 + x)
++#define ASRCTR_ASRCEx_MASK(x) (1 << ASRCTR_ASRCEx_SHIFT(x))
++#define ASRCTR_ASRCE(x) (1 << ASRCTR_ASRCEx_SHIFT(x))
++#define ASRCTR_ASRCEx_ALL_MASK (0x7 << ASRCTR_ASRCEx_SHIFT(0))
++#define ASRCTR_ASRCEN_SHIFT 0
++#define ASRCTR_ASRCEN_MASK (1 << ASRCTR_ASRCEN_SHIFT)
++#define ASRCTR_ASRCEN (1 << ASRCTR_ASRCEN_SHIFT)
++
++/* REG1 0x04 REG_ASRIER */
++#define ASRIER_AFPWE_SHIFT 7
++#define ASRIER_AFPWE_MASK (1 << ASRIER_AFPWE_SHIFT)
++#define ASRIER_AFPWE (1 << ASRIER_AFPWE_SHIFT)
++#define ASRIER_AOLIE_SHIFT 6
++#define ASRIER_AOLIE_MASK (1 << ASRIER_AOLIE_SHIFT)
++#define ASRIER_AOLIE (1 << ASRIER_AOLIE_SHIFT)
++#define ASRIER_ADOEx_SHIFT(x) (3 + x)
++#define ASRIER_ADOEx_MASK(x) (1 << ASRIER_ADOEx_SHIFT(x))
++#define ASRIER_ADOE(x) (1 << ASRIER_ADOEx_SHIFT(x))
++#define ASRIER_ADIEx_SHIFT(x) (0 + x)
++#define ASRIER_ADIEx_MASK(x) (1 << ASRIER_ADIEx_SHIFT(x))
++#define ASRIER_ADIE(x) (1 << ASRIER_ADIEx_SHIFT(x))
++
++/* REG2 0x0C REG_ASRCNCR */
++#define ASRCNCR_ANCx_SHIFT(x, b) (b * x)
++#define ASRCNCR_ANCx_MASK(x, b) (((1 << b) - 1) << ASRCNCR_ANCx_SHIFT(x, b))
++#define ASRCNCR_ANCx_get(x, v, b) ((v & ASRCNCR_ANCx_MASK(x, b)) >> ASRCNCR_ANCx_SHIFT(x, b))
++#define ASRCNCR_ANCx_set(x, v, b) ((v << ASRCNCR_ANCx_SHIFT(x, b)) & ASRCNCR_ANCx_MASK(x, b))
++
++/* REG3 0x10 REG_ASRCFG */
++#define ASRCFG_INIRQx_SHIFT(x) (21 + x)
++#define ASRCFG_INIRQx_MASK(x) (1 << ASRCFG_INIRQx_SHIFT(x))
++#define ASRCFG_INIRQx (1 << ASRCFG_INIRQx_SHIFT(x))
++#define ASRCFG_NDPRx_SHIFT(x) (18 + x)
++#define ASRCFG_NDPRx_MASK(x) (1 << ASRCFG_NDPRx_SHIFT(x))
++#define ASRCFG_NDPRx (1 << ASRCFG_NDPRx_SHIFT(x))
++#define ASRCFG_POSTMODx_SHIFT(x) (8 + (x << 2))
++#define ASRCFG_POSTMODx_WIDTH 2
++#define ASRCFG_POSTMODx_MASK(x) (((1 << ASRCFG_POSTMODx_WIDTH) - 1) << ASRCFG_POSTMODx_SHIFT(x))
++#define ASRCFG_POSTMOD(x, v) ((v) << ASRCFG_POSTMODx_SHIFT(x))
++#define ASRCFG_POSTMODx_UP(x) (0 << ASRCFG_POSTMODx_SHIFT(x))
++#define ASRCFG_POSTMODx_DCON(x) (1 << ASRCFG_POSTMODx_SHIFT(x))
++#define ASRCFG_POSTMODx_DOWN(x) (2 << ASRCFG_POSTMODx_SHIFT(x))
++#define ASRCFG_PREMODx_SHIFT(x) (6 + (x << 2))
++#define ASRCFG_PREMODx_WIDTH 2
++#define ASRCFG_PREMODx_MASK(x) (((1 << ASRCFG_PREMODx_WIDTH) - 1) << ASRCFG_PREMODx_SHIFT(x))
++#define ASRCFG_PREMOD(x, v) ((v) << ASRCFG_PREMODx_SHIFT(x))
++#define ASRCFG_PREMODx_UP(x) (0 << ASRCFG_PREMODx_SHIFT(x))
++#define ASRCFG_PREMODx_DCON(x) (1 << ASRCFG_PREMODx_SHIFT(x))
++#define ASRCFG_PREMODx_DOWN(x) (2 << ASRCFG_PREMODx_SHIFT(x))
++#define ASRCFG_PREMODx_BYPASS(x) (3 << ASRCFG_PREMODx_SHIFT(x))
++
++/* REG4 0x14 REG_ASRCSR */
++#define ASRCSR_AxCSx_WIDTH 4
++#define ASRCSR_AxCSx_MASK ((1 << ASRCSR_AxCSx_WIDTH) - 1)
++#define ASRCSR_AOCSx_SHIFT(x) (12 + (x << 2))
++#define ASRCSR_AOCSx_MASK(x) (((1 << ASRCSR_AxCSx_WIDTH) - 1) << ASRCSR_AOCSx_SHIFT(x))
++#define ASRCSR_AOCS(x, v) ((v) << ASRCSR_AOCSx_SHIFT(x))
++#define ASRCSR_AICSx_SHIFT(x) (x << 2)
++#define ASRCSR_AICSx_MASK(x) (((1 << ASRCSR_AxCSx_WIDTH) - 1) << ASRCSR_AICSx_SHIFT(x))
++#define ASRCSR_AICS(x, v) ((v) << ASRCSR_AICSx_SHIFT(x))
++
++/* REG5&6 0x18 & 0x1C REG_ASRCDR1 & ASRCDR2 */
++#define ASRCDRx_AxCPx_WIDTH 3
++#define ASRCDRx_AICPx_SHIFT(x) (0 + (x % 2) * 6)
++#define ASRCDRx_AICPx_MASK(x) (((1 << ASRCDRx_AxCPx_WIDTH) - 1) << ASRCDRx_AICPx_SHIFT(x))
++#define ASRCDRx_AICP(x, v) ((v) << ASRCDRx_AICPx_SHIFT(x))
++#define ASRCDRx_AICDx_SHIFT(x) (3 + (x % 2) * 6)
++#define ASRCDRx_AICDx_MASK(x) (((1 << ASRCDRx_AxCPx_WIDTH) - 1) << ASRCDRx_AICDx_SHIFT(x))
++#define ASRCDRx_AICD(x, v) ((v) << ASRCDRx_AICDx_SHIFT(x))
++#define ASRCDRx_AOCPx_SHIFT(x) ((x < 2) ? 12 + x * 6 : 6)
++#define ASRCDRx_AOCPx_MASK(x) (((1 << ASRCDRx_AxCPx_WIDTH) - 1) << ASRCDRx_AOCPx_SHIFT(x))
++#define ASRCDRx_AOCP(x, v) ((v) << ASRCDRx_AOCPx_SHIFT(x))
++#define ASRCDRx_AOCDx_SHIFT(x) ((x < 2) ? 15 + x * 6 : 9)
++#define ASRCDRx_AOCDx_MASK(x) (((1 << ASRCDRx_AxCPx_WIDTH) - 1) << ASRCDRx_AOCDx_SHIFT(x))
++#define ASRCDRx_AOCD(x, v) ((v) << ASRCDRx_AOCDx_SHIFT(x))
++
++/* REG7 0x20 REG_ASRSTR */
++#define ASRSTR_DSLCNT_SHIFT 21
++#define ASRSTR_DSLCNT_MASK (1 << ASRSTR_DSLCNT_SHIFT)
++#define ASRSTR_DSLCNT (1 << ASRSTR_DSLCNT_SHIFT)
++#define ASRSTR_ATQOL_SHIFT 20
++#define ASRSTR_ATQOL_MASK (1 << ASRSTR_ATQOL_SHIFT)
++#define ASRSTR_ATQOL (1 << ASRSTR_ATQOL_SHIFT)
++#define ASRSTR_AOOLx_SHIFT(x) (17 + x)
++#define ASRSTR_AOOLx_MASK(x) (1 << ASRSTR_AOOLx_SHIFT(x))
++#define ASRSTR_AOOL(x) (1 << ASRSTR_AOOLx_SHIFT(x))
++#define ASRSTR_AIOLx_SHIFT(x) (14 + x)
++#define ASRSTR_AIOLx_MASK(x) (1 << ASRSTR_AIOLx_SHIFT(x))
++#define ASRSTR_AIOL(x) (1 << ASRSTR_AIOLx_SHIFT(x))
++#define ASRSTR_AODOx_SHIFT(x) (11 + x)
++#define ASRSTR_AODOx_MASK(x) (1 << ASRSTR_AODOx_SHIFT(x))
++#define ASRSTR_AODO(x) (1 << ASRSTR_AODOx_SHIFT(x))
++#define ASRSTR_AIDUx_SHIFT(x) (8 + x)
++#define ASRSTR_AIDUx_MASK(x) (1 << ASRSTR_AIDUx_SHIFT(x))
++#define ASRSTR_AIDU(x) (1 << ASRSTR_AIDUx_SHIFT(x))
++#define ASRSTR_FPWT_SHIFT 7
++#define ASRSTR_FPWT_MASK (1 << ASRSTR_FPWT_SHIFT)
++#define ASRSTR_FPWT (1 << ASRSTR_FPWT_SHIFT)
++#define ASRSTR_AOLE_SHIFT 6
++#define ASRSTR_AOLE_MASK (1 << ASRSTR_AOLE_SHIFT)
++#define ASRSTR_AOLE (1 << ASRSTR_AOLE_SHIFT)
++#define ASRSTR_AODEx_SHIFT(x) (3 + x)
++#define ASRSTR_AODFx_MASK(x) (1 << ASRSTR_AODEx_SHIFT(x))
++#define ASRSTR_AODF(x) (1 << ASRSTR_AODEx_SHIFT(x))
++#define ASRSTR_AIDEx_SHIFT(x) (0 + x)
++#define ASRSTR_AIDEx_MASK(x) (1 << ASRSTR_AIDEx_SHIFT(x))
++#define ASRSTR_AIDE(x) (1 << ASRSTR_AIDEx_SHIFT(x))
++
++/* REG10 0x54 REG_ASRTFR1 */
++#define ASRTFR1_TF_BASE_WIDTH 7
++#define ASRTFR1_TF_BASE_SHIFT 6
++#define ASRTFR1_TF_BASE_MASK (((1 << ASRTFR1_TF_BASE_WIDTH) - 1) << ASRTFR1_TF_BASE_SHIFT)
++#define ASRTFR1_TF_BASE(x) ((x) << ASRTFR1_TF_BASE_SHIFT)
++
++/*
++ * REG22 0xA0 REG_ASRMCRA
++ * REG24 0xA8 REG_ASRMCRB
++ * REG26 0xB0 REG_ASRMCRC
++ */
++#define ASRMCRx_ZEROBUFx_SHIFT 23
++#define ASRMCRx_ZEROBUFxCLR_MASK (1 << ASRMCRx_ZEROBUFx_SHIFT)
++#define ASRMCRx_ZEROBUFxCLR (1 << ASRMCRx_ZEROBUFx_SHIFT)
++#define ASRMCRx_EXTTHRSHx_SHIFT 22
++#define ASRMCRx_EXTTHRSHx_MASK (1 << ASRMCRx_EXTTHRSHx_SHIFT)
++#define ASRMCRx_EXTTHRSHx (1 << ASRMCRx_EXTTHRSHx_SHIFT)
++#define ASRMCRx_BUFSTALLx_SHIFT 21
++#define ASRMCRx_BUFSTALLx_MASK (1 << ASRMCRx_BUFSTALLx_SHIFT)
++#define ASRMCRx_BUFSTALLx (1 << ASRMCRx_BUFSTALLx_SHIFT)
++#define ASRMCRx_BYPASSPOLYx_SHIFT 20
++#define ASRMCRx_BYPASSPOLYx_MASK (1 << ASRMCRx_BYPASSPOLYx_SHIFT)
++#define ASRMCRx_BYPASSPOLYx (1 << ASRMCRx_BYPASSPOLYx_SHIFT)
++#define ASRMCRx_OUTFIFO_THRESHOLD_WIDTH 6
++#define ASRMCRx_OUTFIFO_THRESHOLD_SHIFT 12
++#define ASRMCRx_OUTFIFO_THRESHOLD_MASK (((1 << ASRMCRx_OUTFIFO_THRESHOLD_WIDTH) - 1) << ASRMCRx_OUTFIFO_THRESHOLD_SHIFT)
++#define ASRMCRx_OUTFIFO_THRESHOLD(v) (((v) << ASRMCRx_OUTFIFO_THRESHOLD_SHIFT) & ASRMCRx_OUTFIFO_THRESHOLD_MASK)
++#define ASRMCRx_RSYNIFx_SHIFT 11
++#define ASRMCRx_RSYNIFx_MASK (1 << ASRMCRx_RSYNIFx_SHIFT)
++#define ASRMCRx_RSYNIFx (1 << ASRMCRx_RSYNIFx_SHIFT)
++#define ASRMCRx_RSYNOFx_SHIFT 10
++#define ASRMCRx_RSYNOFx_MASK (1 << ASRMCRx_RSYNOFx_SHIFT)
++#define ASRMCRx_RSYNOFx (1 << ASRMCRx_RSYNOFx_SHIFT)
++#define ASRMCRx_INFIFO_THRESHOLD_WIDTH 6
++#define ASRMCRx_INFIFO_THRESHOLD_SHIFT 0
++#define ASRMCRx_INFIFO_THRESHOLD_MASK (((1 << ASRMCRx_INFIFO_THRESHOLD_WIDTH) - 1) << ASRMCRx_INFIFO_THRESHOLD_SHIFT)
++#define ASRMCRx_INFIFO_THRESHOLD(v) (((v) << ASRMCRx_INFIFO_THRESHOLD_SHIFT) & ASRMCRx_INFIFO_THRESHOLD_MASK)
++
++/*
++ * REG23 0xA4 REG_ASRFSTA
++ * REG25 0xAC REG_ASRFSTB
++ * REG27 0xB4 REG_ASRFSTC
++ */
++#define ASRFSTx_OAFx_SHIFT 23
++#define ASRFSTx_OAFx_MASK (1 << ASRFSTx_OAFx_SHIFT)
++#define ASRFSTx_OAFx (1 << ASRFSTx_OAFx_SHIFT)
++#define ASRFSTx_OUTPUT_FIFO_WIDTH 7
++#define ASRFSTx_OUTPUT_FIFO_SHIFT 12
++#define ASRFSTx_OUTPUT_FIFO_MASK (((1 << ASRFSTx_OUTPUT_FIFO_WIDTH) - 1) << ASRFSTx_OUTPUT_FIFO_SHIFT)
++#define ASRFSTx_IAEx_SHIFT 11
++#define ASRFSTx_IAEx_MASK (1 << ASRFSTx_OAFx_SHIFT)
++#define ASRFSTx_IAEx (1 << ASRFSTx_OAFx_SHIFT)
++#define ASRFSTx_INPUT_FIFO_WIDTH 7
++#define ASRFSTx_INPUT_FIFO_SHIFT 0
++#define ASRFSTx_INPUT_FIFO_MASK ((1 << ASRFSTx_INPUT_FIFO_WIDTH) - 1)
++
++/* REG28 0xC0 & 0xC4 & 0xC8 REG_ASRMCR1x */
++#define ASRMCR1x_IWD_WIDTH 3
++#define ASRMCR1x_IWD_SHIFT 9
++#define ASRMCR1x_IWD_MASK (((1 << ASRMCR1x_IWD_WIDTH) - 1) << ASRMCR1x_IWD_SHIFT)
++#define ASRMCR1x_IWD(v) ((v) << ASRMCR1x_IWD_SHIFT)
++#define ASRMCR1x_IMSB_SHIFT 8
++#define ASRMCR1x_IMSB_MASK (1 << ASRMCR1x_IMSB_SHIFT)
++#define ASRMCR1x_IMSB_MSB (1 << ASRMCR1x_IMSB_SHIFT)
++#define ASRMCR1x_IMSB_LSB (0 << ASRMCR1x_IMSB_SHIFT)
++#define ASRMCR1x_OMSB_SHIFT 2
++#define ASRMCR1x_OMSB_MASK (1 << ASRMCR1x_OMSB_SHIFT)
++#define ASRMCR1x_OMSB_MSB (1 << ASRMCR1x_OMSB_SHIFT)
++#define ASRMCR1x_OMSB_LSB (0 << ASRMCR1x_OMSB_SHIFT)
++#define ASRMCR1x_OSGN_SHIFT 1
++#define ASRMCR1x_OSGN_MASK (1 << ASRMCR1x_OSGN_SHIFT)
++#define ASRMCR1x_OSGN (1 << ASRMCR1x_OSGN_SHIFT)
++#define ASRMCR1x_OW16_SHIFT 0
++#define ASRMCR1x_OW16_MASK (1 << ASRMCR1x_OW16_SHIFT)
++#define ASRMCR1x_OW16(v) ((v) << ASRMCR1x_OW16_SHIFT)
++
++
++struct dma_block {
++ unsigned int index;
++ unsigned int length;
++ void *dma_vaddr;
++ dma_addr_t dma_paddr;
++ struct list_head queue;
++};
++
++struct asrc_p2p_params {
++ u32 p2p_rate; /* ASRC output rate for p2p */
++ enum asrc_word_width p2p_width; /* ASRC output wordwidth for p2p */
++};
++
++struct asrc_pair_params {
++ enum asrc_pair_index index;
++ struct completion input_complete;
++ struct completion output_complete;
++ struct dma_chan *input_dma_channel;
++ struct dma_chan *output_dma_channel;
++ unsigned int input_buffer_size;
++ unsigned int output_buffer_size;
++ unsigned int buffer_num;
++ unsigned int pair_hold;
++ unsigned int asrc_active;
++ unsigned int channel_nums;
++ struct dma_block input_dma_total;
++ struct dma_block input_dma[ASRC_DMA_BUFFER_NUM];
++ struct dma_block output_dma_total;
++ struct dma_block output_dma[ASRC_DMA_BUFFER_NUM];
++ struct dma_block output_last_period;
++ struct dma_async_tx_descriptor *desc_in;
++ struct dma_async_tx_descriptor *desc_out;
++ unsigned int input_sg_nodes;
++ unsigned int output_sg_nodes;
++ struct scatterlist input_sg[4], output_sg[4];
++ enum asrc_word_width input_word_width;
++ enum asrc_word_width output_word_width;
++ u32 input_sample_rate;
++ u32 output_sample_rate;
++ u32 input_wm;
++ u32 output_wm;
++ unsigned int last_period_sample;
++};
++
++struct asrc_data {
++ struct asrc_pair_params *params[ASRC_PAIR_MAX_NUM];
++ struct asrc_pair asrc_pair[ASRC_PAIR_MAX_NUM];
++ struct proc_dir_entry *proc_asrc;
++ struct class *asrc_class;
++ struct regmap *regmap;
++ struct clk *mem_clk;
++ struct clk *ipg_clk;
++ struct clk *asrck_clk;
++ struct clk *dma_clk;
++ unsigned long paddr;
++ unsigned int channel_bits;
++ int asrc_major;
++ int irq;
++ struct device *dev;
++};
++
++struct asrc_p2p_ops {
++ void (*asrc_p2p_start_conv)(enum asrc_pair_index);
++ void (*asrc_p2p_stop_conv)(enum asrc_pair_index);
++ int (*asrc_p2p_get_dma_request)(enum asrc_pair_index, bool);
++ u32 (*asrc_p2p_per_addr)(enum asrc_pair_index, bool);
++ int (*asrc_p2p_req_pair)(int, enum asrc_pair_index *index);
++ int (*asrc_p2p_config_pair)(struct asrc_config *config);
++ void (*asrc_p2p_release_pair)(enum asrc_pair_index);
++ void (*asrc_p2p_finish_conv)(enum asrc_pair_index);
++};
++
++extern void asrc_p2p_hook(struct asrc_p2p_ops *asrc_p2p_ct);
++
++extern int asrc_req_pair(int chn_num, enum asrc_pair_index *index);
++extern void asrc_release_pair(enum asrc_pair_index index);
++extern int asrc_config_pair(struct asrc_config *config);
++extern void asrc_get_status(struct asrc_status_flags *flags);
++extern void asrc_start_conv(enum asrc_pair_index index);
++extern void asrc_stop_conv(enum asrc_pair_index index);
++extern u32 asrc_get_per_addr(enum asrc_pair_index index, bool i);
++extern int asrc_get_dma_request(enum asrc_pair_index index, bool i);
++extern void asrc_finish_conv(enum asrc_pair_index index);
++extern int asrc_set_watermark(enum asrc_pair_index index,
++ u32 in_wm, u32 out_wm);
++
++#endif/* __MXC_ASRC_H__ */
+diff -Nur linux-4.1.3/include/linux/mxc_dcic.h linux-xbian-imx6/include/linux/mxc_dcic.h
+--- linux-4.1.3/include/linux/mxc_dcic.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/include/linux/mxc_dcic.h 2015-07-27 23:13:09.606706653 +0200
+@@ -0,0 +1,139 @@
++/*
++ * Copyright (C) 2014 Freescale Semiconductor, Inc. All Rights Reserved
++ */
++
++/*
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++/*!
++ * @file linux/mxc_dcic.h
++ *
++ * @brief Global header file for the MXC DCIC driver
++ *
++ * @ingroup MXC DCIC
++ */
++
++#ifndef __LINUX_DCIC_H__
++#define __LINUX_DCIC_H__
++
++#include <uapi/linux/mxc_dcic.h>
++
++#define DCICC_IC_ENABLE 0x1
++#define DCICC_IC_DISABLE 0x0
++#define DCICC_IC_MASK 0x1
++#define DCICC_DE_ACTIVE_HIGH 0
++#define DCICC_DE_ACTIVE_LOW (0x1 << 4)
++#define DCICC_DE_ACTIVE_MASK (0x1 << 4)
++#define DCICC_HSYNC_POL_ACTIVE_HIGH 0
++#define DCICC_HSYNC_POL_ACTIVE_LOW (0x1 << 5)
++#define DCICC_HSYNC_POL_ACTIVE_MASK (0x1 << 5)
++#define DCICC_VSYNC_POL_ACTIVE_HIGH 0
++#define DCICC_VSYNC_POL_ACTIVE_LOW (0x1 << 6)
++#define DCICC_VSYNC_POL_ACTIVE_MASK (0x1 << 6)
++#define DCICC_CLK_POL_NO_INVERTED 0
++#define DCICC_CLK_POL_INVERTED (0x1 << 7)
++#define DCICC_CLK_POL_INVERTED_MASK (0x1 << 7)
++
++#define DCICIC_ERROR_INT_DISABLE 1
++#define DCICIC_ERROR_INT_ENABLE 0
++#define DCICIC_ERROR_INT_MASK_MASK 1
++#define DCICIC_FUN_INT_DISABLE (0x1 << 1)
++#define DCICIC_FUN_INT_ENABLE 0
++#define DCICIC_FUN_INT_MASK (0x1 << 1)
++#define DCICIC_FREEZE_MASK_CHANGED 0
++#define DCICIC_FREEZE_MASK_FORZEN (0x1 << 3)
++#define DCICIC_FREEZE_MASK_MASK (0x1 << 3)
++#define DCICIC_EXT_SIG_EX_DISABLE 0
++#define DCICIC_EXT_SIG_EN_ENABLE (0x1 << 16)
++#define DCICIC_EXT_SIG_EN_MASK (0x1 << 16)
++
++#define DCICS_ROI_MATCH_STAT_MASK 0xFFFF
++#define DCICS_EI_STAT_PENDING (0x1 << 16)
++#define DCICS_EI_STAT_NO_PENDING 0
++#define DCICS_FI_STAT_PENDING (0x1 << 17)
++#define DCICS_FI_STAT_NO_PENDING 0
++
++#define DCICRC_ROI_START_OFFSET_X_MASK 0x1FFF
++#define DCICRC_ROI_START_OFFSET_X_SHIFT 0
++#define DCICRC_ROI_START_OFFSET_Y_MASK (0xFFF << 16)
++#define DCICRC_ROI_START_OFFSET_Y_SHIFT 16
++#define DCICRC_ROI_CHANGED 0
++#define DCICRC_ROI_FROZEN (0x1 << 30)
++#define DCICRC_ROI_ENABLE (0x1 << 31)
++#define DCICRC_ROI_DISABLE 0
++
++#define DCICRS_ROI_END_OFFSET_X_MASK 0x1FFF
++#define DCICRS_ROI_END_OFFSET_X_SHIFT 0
++#define DCICRS_ROI_END_OFFSET_Y_MASK (0xFFF << 16)
++#define DCICRS_ROI_END_OFFSET_Y_SHIFT 16
++
++struct roi_regs {
++ u32 dcicrc;
++ u32 dcicrs;
++ u32 dcicrrs;
++ u32 dcicrcs;
++};
++
++struct dcic_regs {
++ u32 dcicc;
++ u32 dcicic;
++ u32 dcics;
++ u32 dcic_reserved;
++ struct roi_regs ROI[16];
++};
++
++struct dcic_mux {
++ char dcic[16];
++ u32 val;
++};
++
++struct bus_mux {
++ char name[16];
++ int reg;
++ int shift;
++ int mask;
++ int dcic_mux_num;
++ const struct dcic_mux *dcics;
++};
++
++struct dcic_info {
++ int bus_mux_num;
++ const struct bus_mux *buses;
++};
++
++struct dcic_data {
++ struct regmap *regmap;
++ struct device *dev;
++ struct dcic_regs *regs;
++ const struct bus_mux *buses;
++ u32 bus_n;
++ u32 mux_n;
++ struct clk *disp_axi_clk;
++ struct clk *dcic_clk;
++ struct mutex lock;
++ struct completion roi_crc_comp;
++ struct class *class;
++ int major;
++ struct cdev cdev; /* Char device structure */
++ dev_t devt;
++ unsigned int result;
++};
++
++struct dcic_private {
++ struct dcic_data *dcic;
++ u16 client_id;
++};
++#endif
+diff -Nur linux-4.1.3/include/linux/mxc_vpu.h linux-xbian-imx6/include/linux/mxc_vpu.h
+--- linux-4.1.3/include/linux/mxc_vpu.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/include/linux/mxc_vpu.h 2015-07-27 23:13:09.606706653 +0200
+@@ -0,0 +1,118 @@
++/*
++ * Copyright 2004-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU Lesser General
++ * Public License. You may obtain a copy of the GNU Lesser General
++ * Public License Version 2.1 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/lgpl-license.html
++ * http://www.gnu.org/copyleft/lgpl.html
++ */
++
++/*!
++ * @defgroup VPU Video Processor Unit Driver
++ */
++
++/*!
++ * @file linux/mxc_vpu.h
++ *
++ * @brief VPU system initialization and file operation definition
++ *
++ * @ingroup VPU
++ */
++
++#ifndef __LINUX_MXC_VPU_H__
++#define __LINUX_MXC_VPU_H__
++
++#include <linux/fs.h>
++
++struct mxc_vpu_platform_data {
++ bool iram_enable;
++ int iram_size;
++ void (*reset) (void);
++ void (*pg) (int);
++};
++
++struct vpu_mem_desc {
++ u32 size;
++ dma_addr_t phy_addr;
++ u32 cpu_addr; /* cpu address to free the dma mem */
++ u32 virt_uaddr; /* virtual user space address */
++};
++
++#define VPU_IOC_MAGIC 'V'
++
++#define VPU_IOC_PHYMEM_ALLOC _IO(VPU_IOC_MAGIC, 0)
++#define VPU_IOC_PHYMEM_FREE _IO(VPU_IOC_MAGIC, 1)
++#define VPU_IOC_WAIT4INT _IO(VPU_IOC_MAGIC, 2)
++#define VPU_IOC_PHYMEM_DUMP _IO(VPU_IOC_MAGIC, 3)
++#define VPU_IOC_REG_DUMP _IO(VPU_IOC_MAGIC, 4)
++#define VPU_IOC_IRAM_SETTING _IO(VPU_IOC_MAGIC, 6)
++#define VPU_IOC_CLKGATE_SETTING _IO(VPU_IOC_MAGIC, 7)
++#define VPU_IOC_GET_WORK_ADDR _IO(VPU_IOC_MAGIC, 8)
++#define VPU_IOC_REQ_VSHARE_MEM _IO(VPU_IOC_MAGIC, 9)
++#define VPU_IOC_SYS_SW_RESET _IO(VPU_IOC_MAGIC, 11)
++#define VPU_IOC_GET_SHARE_MEM _IO(VPU_IOC_MAGIC, 12)
++#define VPU_IOC_QUERY_BITWORK_MEM _IO(VPU_IOC_MAGIC, 13)
++#define VPU_IOC_SET_BITWORK_MEM _IO(VPU_IOC_MAGIC, 14)
++#define VPU_IOC_PHYMEM_CHECK _IO(VPU_IOC_MAGIC, 15)
++#define VPU_IOC_LOCK_DEV _IO(VPU_IOC_MAGIC, 16)
++
++#define BIT_CODE_RUN 0x000
++#define BIT_CODE_DOWN 0x004
++#define BIT_INT_CLEAR 0x00C
++#define BIT_INT_STATUS 0x010
++#define BIT_CUR_PC 0x018
++#define BIT_INT_REASON 0x174
++
++#define MJPEG_PIC_STATUS_REG 0x3004
++#define MBC_SET_SUBBLK_EN 0x4A0
++
++#define BIT_WORK_CTRL_BUF_BASE 0x100
++#define BIT_WORK_CTRL_BUF_REG(i) (BIT_WORK_CTRL_BUF_BASE + i * 4)
++#define BIT_CODE_BUF_ADDR BIT_WORK_CTRL_BUF_REG(0)
++#define BIT_WORK_BUF_ADDR BIT_WORK_CTRL_BUF_REG(1)
++#define BIT_PARA_BUF_ADDR BIT_WORK_CTRL_BUF_REG(2)
++#define BIT_BIT_STREAM_CTRL BIT_WORK_CTRL_BUF_REG(3)
++#define BIT_FRAME_MEM_CTRL BIT_WORK_CTRL_BUF_REG(4)
++#define BIT_BIT_STREAM_PARAM BIT_WORK_CTRL_BUF_REG(5)
++
++#ifndef CONFIG_SOC_IMX6Q
++#define BIT_RESET_CTRL 0x11C
++#else
++#define BIT_RESET_CTRL 0x128
++#endif
++
++/* i could be 0, 1, 2, 3 */
++#define BIT_RD_PTR_BASE 0x120
++#define BIT_RD_PTR_REG(i) (BIT_RD_PTR_BASE + i * 8)
++#define BIT_WR_PTR_REG(i) (BIT_RD_PTR_BASE + i * 8 + 4)
++
++/* i could be 0, 1, 2, 3 */
++#define BIT_FRM_DIS_FLG_BASE (cpu_is_mx51() ? 0x150 : 0x140)
++#define BIT_FRM_DIS_FLG_REG(i) (BIT_FRM_DIS_FLG_BASE + i * 4)
++
++#define BIT_BUSY_FLAG 0x160
++#define BIT_RUN_COMMAND 0x164
++#define BIT_INT_ENABLE 0x170
++
++#define BITVAL_PIC_RUN 8
++
++#define VPU_SLEEP_REG_VALUE 10
++#define VPU_WAKE_REG_VALUE 11
++
++int vl2cc_init(u32 vl2cc_hw_base);
++void vl2cc_enable(void);
++void vl2cc_flush(void);
++void vl2cc_disable(void);
++void vl2cc_cleanup(void);
++
++int vl2cc_init(u32 vl2cc_hw_base);
++void vl2cc_enable(void);
++void vl2cc_flush(void);
++void vl2cc_disable(void);
++void vl2cc_cleanup(void);
++
++#endif
+diff -Nur linux-4.1.3/include/linux/platform_data/dma-imx.h linux-xbian-imx6/include/linux/platform_data/dma-imx.h
+--- linux-4.1.3/include/linux/platform_data/dma-imx.h 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/include/linux/platform_data/dma-imx.h 2015-07-27 23:13:09.622649772 +0200
+@@ -17,31 +17,30 @@
+ * This enumerates peripheral types. Used for SDMA.
+ */
+ enum sdma_peripheral_type {
+- IMX_DMATYPE_SSI, /* MCU domain SSI */
+- IMX_DMATYPE_SSI_SP, /* Shared SSI */
+- IMX_DMATYPE_MMC, /* MMC */
+- IMX_DMATYPE_SDHC, /* SDHC */
+- IMX_DMATYPE_UART, /* MCU domain UART */
+- IMX_DMATYPE_UART_SP, /* Shared UART */
+- IMX_DMATYPE_FIRI, /* FIRI */
+- IMX_DMATYPE_CSPI, /* MCU domain CSPI */
+- IMX_DMATYPE_CSPI_SP, /* Shared CSPI */
+- IMX_DMATYPE_SIM, /* SIM */
+- IMX_DMATYPE_ATA, /* ATA */
+- IMX_DMATYPE_CCM, /* CCM */
+- IMX_DMATYPE_EXT, /* External peripheral */
+- IMX_DMATYPE_MSHC, /* Memory Stick Host Controller */
+- IMX_DMATYPE_MSHC_SP, /* Shared Memory Stick Host Controller */
+- IMX_DMATYPE_DSP, /* DSP */
+- IMX_DMATYPE_MEMORY, /* Memory */
+- IMX_DMATYPE_FIFO_MEMORY,/* FIFO type Memory */
+- IMX_DMATYPE_SPDIF, /* SPDIF */
+- IMX_DMATYPE_IPU_MEMORY, /* IPU Memory */
+- IMX_DMATYPE_ASRC, /* ASRC */
+- IMX_DMATYPE_ESAI, /* ESAI */
+- IMX_DMATYPE_SSI_DUAL, /* SSI Dual FIFO */
+- IMX_DMATYPE_ASRC_SP, /* Shared ASRC */
+- IMX_DMATYPE_SAI, /* SAI */
++ IMX_DMATYPE_SSI, /* MCU domain SSI */
++ IMX_DMATYPE_SSI_SP, /* Shared SSI */
++ IMX_DMATYPE_MMC, /* MMC */
++ IMX_DMATYPE_SDHC, /* SDHC */
++ IMX_DMATYPE_UART, /* MCU domain UART */
++ IMX_DMATYPE_UART_SP, /* Shared UART */
++ IMX_DMATYPE_FIRI, /* FIRI */
++ IMX_DMATYPE_CSPI, /* MCU domain CSPI */
++ IMX_DMATYPE_CSPI_SP, /* Shared CSPI */
++ IMX_DMATYPE_SIM, /* SIM */
++ IMX_DMATYPE_ATA, /* ATA */
++ IMX_DMATYPE_CCM, /* CCM */
++ IMX_DMATYPE_EXT, /* External peripheral */
++ IMX_DMATYPE_MSHC, /* Memory Stick Host Controller */
++ IMX_DMATYPE_MSHC_SP, /* Shared Memory Stick Host Controller */
++ IMX_DMATYPE_DSP, /* DSP */
++ IMX_DMATYPE_MEMORY, /* Memory */
++ IMX_DMATYPE_FIFO_MEMORY,/* FIFO type Memory */
++ IMX_DMATYPE_SPDIF, /* SPDIF */
++ IMX_DMATYPE_IPU_MEMORY, /* IPU Memory */
++ IMX_DMATYPE_ASRC, /* ASRC */
++ IMX_DMATYPE_ESAI, /* ESAI */
++ IMX_DMATYPE_SSI_DUAL, /* SSI Dual FIFO */
++ IMX_DMATYPE_HDMI, /* HDMI Audio */
+ };
+
+ enum imx_dma_prio {
+@@ -55,6 +54,7 @@
+ int dma_request2; /* secondary DMA request line */
+ enum sdma_peripheral_type peripheral_type;
+ int priority;
++ void *data_addr1, *data_addr2;
+ };
+
+ static inline int imx_dma_is_ipu(struct dma_chan *chan)
+diff -Nur linux-4.1.3/include/linux/pxp_device.h linux-xbian-imx6/include/linux/pxp_device.h
+--- linux-4.1.3/include/linux/pxp_device.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/include/linux/pxp_device.h 2015-07-27 23:13:09.634607108 +0200
+@@ -0,0 +1,68 @@
++/*
++ * Copyright (C) 2013-2014 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ */
++#ifndef _PXP_DEVICE
++#define _PXP_DEVICE
++
++#include <linux/idr.h>
++#include <linux/hash.h>
++#include <uapi/linux/pxp_device.h>
++
++struct pxp_irq_info {
++ wait_queue_head_t waitq;
++ atomic_t irq_pending;
++ int hist_status;
++};
++
++struct pxp_buffer_hash {
++ struct hlist_head *hash_table;
++ u32 order;
++ spinlock_t hash_lock;
++};
++
++struct pxp_buf_obj {
++ uint32_t handle;
++
++ uint32_t size;
++ uint32_t mem_type;
++
++ unsigned long offset;
++ void *virtual;
++
++ struct hlist_node item;
++};
++
++struct pxp_chan_obj {
++ uint32_t handle;
++ struct dma_chan *chan;
++};
++
++/* File private data */
++struct pxp_file {
++ struct file *filp;
++
++ /* record allocated dma buffer */
++ struct idr buffer_idr;
++ spinlock_t buffer_lock;
++
++ /* record allocated dma channel */
++ struct idr channel_idr;
++ spinlock_t channel_lock;
++};
++
++#endif
+diff -Nur linux-4.1.3/include/linux/pxp_dma.h linux-xbian-imx6/include/linux/pxp_dma.h
+--- linux-4.1.3/include/linux/pxp_dma.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/include/linux/pxp_dma.h 2015-07-27 23:13:09.634607108 +0200
+@@ -0,0 +1,72 @@
++/*
++ * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ */
++#ifndef _PXP_DMA
++#define _PXP_DMA
++
++#include <uapi/linux/pxp_dma.h>
++
++struct pxp_tx_desc {
++ struct dma_async_tx_descriptor txd;
++ struct list_head tx_list;
++ struct list_head list;
++ int len;
++ union {
++ struct pxp_layer_param s0_param;
++ struct pxp_layer_param out_param;
++ struct pxp_layer_param ol_param;
++ } layer_param;
++ struct pxp_proc_data proc_data;
++
++ u32 hist_status; /* Histogram output status */
++
++ struct pxp_tx_desc *next;
++};
++
++struct pxp_channel {
++ struct dma_chan dma_chan;
++ dma_cookie_t completed; /* last completed cookie */
++ enum pxp_channel_status status;
++ void *client; /* Only one client per channel */
++ unsigned int n_tx_desc;
++ struct pxp_tx_desc *desc; /* allocated tx-descriptors */
++ struct list_head queue; /* queued tx-descriptors */
++ struct list_head list; /* track queued channel number */
++ spinlock_t lock; /* protects sg[0,1], queue,
++ * status, cookie, free_list
++ */
++ int active_buffer;
++ unsigned int eof_irq;
++ char eof_name[16]; /* EOF IRQ name for request_irq() */
++};
++
++#define to_tx_desc(tx) container_of(tx, struct pxp_tx_desc, txd)
++#define to_pxp_channel(d) container_of(d, struct pxp_channel, dma_chan)
++
++void pxp_txd_ack(struct dma_async_tx_descriptor *txd,
++ struct pxp_channel *pxp_chan);
++
++#ifdef CONFIG_MXC_PXP_CLIENT_DEVICE
++int register_pxp_device(void);
++void unregister_pxp_device(void);
++#else
++int register_pxp_device(void) { return 0; }
++void unregister_pxp_device(void) {}
++#endif
++
++#endif
+diff -Nur linux-4.1.3/include/mmc-mxcmmc.h linux-xbian-imx6/include/mmc-mxcmmc.h
+--- linux-4.1.3/include/mmc-mxcmmc.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/include/mmc-mxcmmc.h 2015-07-27 23:13:09.770123601 +0200
+@@ -0,0 +1,39 @@
++#ifndef ASMARM_ARCH_MMC_H
++#define ASMARM_ARCH_MMC_H
++
++#include <linux/mmc/host.h>
++
++struct device;
++
++/* board specific SDHC data, optional.
++ * If not present, a writable card with 3,3V is assumed.
++ */
++struct imxmmc_platform_data {
++ /* Return values for the get_ro callback should be:
++ * 0 for a read/write card
++ * 1 for a read-only card
++ * -ENOSYS when not supported (equal to NULL callback)
++ * or a negative errno value when something bad happened
++ */
++ int (*get_ro)(struct device *);
++
++ /* board specific hook to (de)initialize the SD slot.
++ * The board code can call 'handler' on a card detection
++ * change giving data as argument.
++ */
++ int (*init)(struct device *dev, irq_handler_t handler, void *data);
++ void (*exit)(struct device *dev, void *data);
++
++ /* available voltages. If not given, assume
++ * MMC_VDD_32_33 | MMC_VDD_33_34
++ */
++ unsigned int ocr_avail;
++
++ /* adjust slot voltage */
++ void (*setpower)(struct device *, unsigned int vdd);
++
++ /* enable card detect using DAT3 */
++ int dat3_card_detect;
++};
++
++#endif
+diff -Nur linux-4.1.3/include/mtd-mxc_nand.h linux-xbian-imx6/include/mtd-mxc_nand.h
+--- linux-4.1.3/include/mtd-mxc_nand.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/include/mtd-mxc_nand.h 2015-07-27 23:13:09.770123601 +0200
+@@ -0,0 +1,32 @@
++/*
++ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
++ * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
++ * MA 02110-1301, USA.
++ */
++
++#ifndef __ASM_ARCH_NAND_H
++#define __ASM_ARCH_NAND_H
++
++#include <linux/mtd/partitions.h>
++
++struct mxc_nand_platform_data {
++ unsigned int width; /* data bus width in bytes */
++ unsigned int hw_ecc:1; /* 0 if suppress hardware ECC */
++ unsigned int flash_bbt:1; /* set to 1 to use a flash based bbt */
++ struct mtd_partition *parts; /* partition table */
++ int nr_parts; /* size of parts */
++};
++#endif /* __ASM_ARCH_NAND_H */
+diff -Nur linux-4.1.3/include/sound/soc.h linux-xbian-imx6/include/sound/soc.h
+--- linux-4.1.3/include/sound/soc.h 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/include/sound/soc.h 2015-07-27 23:13:09.837881847 +0200
+@@ -28,6 +28,18 @@
+ #include <sound/control.h>
+ #include <sound/ac97_codec.h>
+
++/*enum snd_soc_control_type {
++ SND_SOC_CUSTOM,
++ SND_SOC_I2C,
++ SND_SOC_SPI,
++};*/
++
++enum snd_soc_control_type {
++ SND_SOC_I2C = 1,
++ SND_SOC_SPI,
++ SND_SOC_REGMAP,
++};
++
+ /*
+ * Convenience kcontrol builders
+ */
+@@ -805,16 +817,24 @@
+
+ struct list_head list;
+ struct list_head card_list;
++ int (*volatile_register)(struct snd_soc_codec *, unsigned int);
+
+ /* runtime */
+ unsigned int cache_bypass:1; /* Suppress access to the cache */
+ unsigned int suspended:1; /* Codec is in suspend PM state */
+ unsigned int cache_init:1; /* codec cache has been initialized */
++ unsigned int using_regmap:1; /* using regmap access */
++ u32 cache_only; /* Suppress writes to hardware */
++ u32 cache_sync; /* Cache needs to be synced to hardware */
+
+ /* codec IO */
+ void *control_data; /* codec control (i2c/3wire) data */
+ hw_write_t hw_write;
++ unsigned int (*read)(struct snd_soc_codec *, unsigned int);
++ int (*write)(struct snd_soc_codec *, unsigned int, unsigned int);
+ void *reg_cache;
++ struct mutex cache_rw_mutex;
++ int val_bytes;
+
+ /* component */
+ struct snd_soc_component component;
+diff -Nur linux-4.1.3/include/sync.h linux-xbian-imx6/include/sync.h
+--- linux-4.1.3/include/sync.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/include/sync.h 2015-07-27 23:13:09.837881847 +0200
+@@ -0,0 +1,356 @@
++/*
++ * include/linux/sync.h
++ *
++ * Copyright (C) 2012 Google, Inc.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ */
++
++#ifndef _LINUX_SYNC_H
++#define _LINUX_SYNC_H
++
++#include <linux/types.h>
++#include <linux/kref.h>
++#include <linux/ktime.h>
++#include <linux/list.h>
++#include <linux/spinlock.h>
++#include <linux/wait.h>
++#include <linux/fence.h>
++
++#include "uapi/sync.h"
++
++struct sync_timeline;
++struct sync_pt;
++struct sync_fence;
++
++/**
++ * struct sync_timeline_ops - sync object implementation ops
++ * @driver_name: name of the implementation
++ * @dup: duplicate a sync_pt
++ * @has_signaled: returns:
++ * 1 if pt has signaled
++ * 0 if pt has not signaled
++ * <0 on error
++ * @compare: returns:
++ * 1 if b will signal before a
++ * 0 if a and b will signal at the same time
++ * -1 if a will signal before b
++ * @free_pt: called before sync_pt is freed
++ * @release_obj: called before sync_timeline is freed
++ * @fill_driver_data: write implementation specific driver data to data.
++ * should return an error if there is not enough room
++ * as specified by size. This information is returned
++ * to userspace by SYNC_IOC_FENCE_INFO.
++ * @timeline_value_str: fill str with the value of the sync_timeline's counter
++ * @pt_value_str: fill str with the value of the sync_pt
++ */
++struct sync_timeline_ops {
++ const char *driver_name;
++
++ /* required */
++ struct sync_pt * (*dup)(struct sync_pt *pt);
++
++ /* required */
++ int (*has_signaled)(struct sync_pt *pt);
++
++ /* required */
++ int (*compare)(struct sync_pt *a, struct sync_pt *b);
++
++ /* optional */
++ void (*free_pt)(struct sync_pt *sync_pt);
++
++ /* optional */
++ void (*release_obj)(struct sync_timeline *sync_timeline);
++
++ /* optional */
++ int (*fill_driver_data)(struct sync_pt *syncpt, void *data, int size);
++
++ /* optional */
++ void (*timeline_value_str)(struct sync_timeline *timeline, char *str,
++ int size);
++
++ /* optional */
++ void (*pt_value_str)(struct sync_pt *pt, char *str, int size);
++};
++
++/**
++ * struct sync_timeline - sync object
++ * @kref: reference count on fence.
++ * @ops: ops that define the implementation of the sync_timeline
++ * @name: name of the sync_timeline. Useful for debugging
++ * @destroyed: set when sync_timeline is destroyed
++ * @child_list_head: list of children sync_pts for this sync_timeline
++ * @child_list_lock: lock protecting @child_list_head, destroyed, and
++ * sync_pt.status
++ * @active_list_head: list of active (unsignaled/errored) sync_pts
++ * @sync_timeline_list: membership in global sync_timeline_list
++ */
++struct sync_timeline {
++ struct kref kref;
++ const struct sync_timeline_ops *ops;
++ char name[32];
++
++ /* protected by child_list_lock */
++ bool destroyed;
++ int context, value;
++
++ struct list_head child_list_head;
++ spinlock_t child_list_lock;
++
++ struct list_head active_list_head;
++
++#ifdef CONFIG_DEBUG_FS
++ struct list_head sync_timeline_list;
++#endif
++};
++
++/**
++ * struct sync_pt - sync point
++ * @fence: base fence class
++ * @child_list: membership in sync_timeline.child_list_head
++ * @active_list: membership in sync_timeline.active_list_head
++ * @signaled_list: membership in temporary signaled_list on stack
++ * @fence: sync_fence to which the sync_pt belongs
++ * @pt_list: membership in sync_fence.pt_list_head
++ * @status: 1: signaled, 0:active, <0: error
++ * @timestamp: time which sync_pt status transitioned from active to
++ * signaled or error.
++ */
++struct sync_pt {
++ struct fence base;
++
++ struct list_head child_list;
++ struct list_head active_list;
++};
++
++static inline struct sync_timeline *sync_pt_parent(struct sync_pt *pt)
++{
++ return container_of(pt->base.lock, struct sync_timeline,
++ child_list_lock);
++}
++
++struct sync_fence_cb {
++ struct fence_cb cb;
++ struct fence *sync_pt;
++ struct sync_fence *fence;
++};
++
++/**
++ * struct sync_fence - sync fence
++ * @file: file representing this fence
++ * @kref: reference count on fence.
++ * @name: name of sync_fence. Useful for debugging
++ * @pt_list_head: list of sync_pts in the fence. immutable once fence
++ * is created
++ * @status: 0: signaled, >0:active, <0: error
++ *
++ * @wq: wait queue for fence signaling
++ * @sync_fence_list: membership in global fence list
++ */
++struct sync_fence {
++ struct file *file;
++ struct kref kref;
++ char name[32];
++#ifdef CONFIG_DEBUG_FS
++ struct list_head sync_fence_list;
++#endif
++ int num_fences;
++
++ wait_queue_head_t wq;
++ atomic_t status;
++
++ struct sync_fence_cb cbs[];
++};
++
++struct sync_fence_waiter;
++typedef void (*sync_callback_t)(struct sync_fence *fence,
++ struct sync_fence_waiter *waiter);
++
++/**
++ * struct sync_fence_waiter - metadata for asynchronous waiter on a fence
++ * @waiter_list: membership in sync_fence.waiter_list_head
++ * @callback: function pointer to call when fence signals
++ * @callback_data: pointer to pass to @callback
++ */
++struct sync_fence_waiter {
++ wait_queue_t work;
++ sync_callback_t callback;
++};
++
++static inline void sync_fence_waiter_init(struct sync_fence_waiter *waiter,
++ sync_callback_t callback)
++{
++ INIT_LIST_HEAD(&waiter->work.task_list);
++ waiter->callback = callback;
++}
++
++/*
++ * API for sync_timeline implementers
++ */
++
++/**
++ * sync_timeline_create() - creates a sync object
++ * @ops: specifies the implementation ops for the object
++ * @size: size to allocate for this obj
++ * @name: sync_timeline name
++ *
++ * Creates a new sync_timeline which will use the implementation specified by
++ * @ops. @size bytes will be allocated allowing for implementation specific
++ * data to be kept after the generic sync_timeline struct.
++ */
++struct sync_timeline *sync_timeline_create(const struct sync_timeline_ops *ops,
++ int size, const char *name);
++
++/**
++ * sync_timeline_destroy() - destroys a sync object
++ * @obj: sync_timeline to destroy
++ *
++ * A sync implementation should call this when the @obj is going away
++ * (i.e. module unload.) @obj won't actually be freed until all its children
++ * sync_pts are freed.
++ */
++void sync_timeline_destroy(struct sync_timeline *obj);
++
++/**
++ * sync_timeline_signal() - signal a status change on a sync_timeline
++ * @obj: sync_timeline to signal
++ *
++ * A sync implementation should call this any time one of it's sync_pts
++ * has signaled or has an error condition.
++ */
++void sync_timeline_signal(struct sync_timeline *obj);
++
++/**
++ * sync_pt_create() - creates a sync pt
++ * @parent: sync_pt's parent sync_timeline
++ * @size: size to allocate for this pt
++ *
++ * Creates a new sync_pt as a child of @parent. @size bytes will be
++ * allocated allowing for implementation specific data to be kept after
++ * the generic sync_timeline struct.
++ */
++struct sync_pt *sync_pt_create(struct sync_timeline *parent, int size);
++
++/**
++ * sync_pt_free() - frees a sync pt
++ * @pt: sync_pt to free
++ *
++ * This should only be called on sync_pts which have been created but
++ * not added to a fence.
++ */
++void sync_pt_free(struct sync_pt *pt);
++
++/**
++ * sync_fence_create() - creates a sync fence
++ * @name: name of fence to create
++ * @pt: sync_pt to add to the fence
++ *
++ * Creates a fence containg @pt. Once this is called, the fence takes
++ * ownership of @pt.
++ */
++struct sync_fence *sync_fence_create(const char *name, struct sync_pt *pt);
++
++/*
++ * API for sync_fence consumers
++ */
++
++/**
++ * sync_fence_merge() - merge two fences
++ * @name: name of new fence
++ * @a: fence a
++ * @b: fence b
++ *
++ * Creates a new fence which contains copies of all the sync_pts in both
++ * @a and @b. @a and @b remain valid, independent fences.
++ */
++struct sync_fence *sync_fence_merge(const char *name,
++ struct sync_fence *a, struct sync_fence *b);
++
++/**
++ * sync_fence_fdget() - get a fence from an fd
++ * @fd: fd referencing a fence
++ *
++ * Ensures @fd references a valid fence, increments the refcount of the backing
++ * file, and returns the fence.
++ */
++struct sync_fence *sync_fence_fdget(int fd);
++
++/**
++ * sync_fence_put() - puts a reference of a sync fence
++ * @fence: fence to put
++ *
++ * Puts a reference on @fence. If this is the last reference, the fence and
++ * all it's sync_pts will be freed
++ */
++void sync_fence_put(struct sync_fence *fence);
++
++/**
++ * sync_fence_install() - installs a fence into a file descriptor
++ * @fence: fence to install
++ * @fd: file descriptor in which to install the fence
++ *
++ * Installs @fence into @fd. @fd's should be acquired through
++ * get_unused_fd_flags(O_CLOEXEC).
++ */
++void sync_fence_install(struct sync_fence *fence, int fd);
++
++/**
++ * sync_fence_wait_async() - registers and async wait on the fence
++ * @fence: fence to wait on
++ * @waiter: waiter callback struck
++ *
++ * Returns 1 if @fence has already signaled.
++ *
++ * Registers a callback to be called when @fence signals or has an error.
++ * @waiter should be initialized with sync_fence_waiter_init().
++ */
++int sync_fence_wait_async(struct sync_fence *fence,
++ struct sync_fence_waiter *waiter);
++
++/**
++ * sync_fence_cancel_async() - cancels an async wait
++ * @fence: fence to wait on
++ * @waiter: waiter callback struck
++ *
++ * returns 0 if waiter was removed from fence's async waiter list.
++ * returns -ENOENT if waiter was not found on fence's async waiter list.
++ *
++ * Cancels a previously registered async wait. Will fail gracefully if
++ * @waiter was never registered or if @fence has already signaled @waiter.
++ */
++int sync_fence_cancel_async(struct sync_fence *fence,
++ struct sync_fence_waiter *waiter);
++
++/**
++ * sync_fence_wait() - wait on fence
++ * @fence: fence to wait on
++ * @tiemout: timeout in ms
++ *
++ * Wait for @fence to be signaled or have an error. Waits indefinitely
++ * if @timeout < 0
++ */
++int sync_fence_wait(struct sync_fence *fence, long timeout);
++
++#ifdef CONFIG_DEBUG_FS
++
++extern void sync_timeline_debug_add(struct sync_timeline *obj);
++extern void sync_timeline_debug_remove(struct sync_timeline *obj);
++extern void sync_fence_debug_add(struct sync_fence *fence);
++extern void sync_fence_debug_remove(struct sync_fence *fence);
++extern void sync_dump(void);
++
++#else
++# define sync_timeline_debug_add(obj)
++# define sync_timeline_debug_remove(obj)
++# define sync_fence_debug_add(fence)
++# define sync_fence_debug_remove(fence)
++# define sync_dump()
++#endif
++int sync_fence_wake_up_wq(wait_queue_t *curr, unsigned mode,
++ int wake_flags, void *key);
++
++#endif /* _LINUX_SYNC_H */
+diff -Nur linux-4.1.3/include/uapi/linux/fb.h linux-xbian-imx6/include/uapi/linux/fb.h
+--- linux-4.1.3/include/uapi/linux/fb.h 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/include/uapi/linux/fb.h 2015-07-27 23:13:09.853824963 +0200
+@@ -217,14 +217,45 @@
+ #define FB_SYNC_ON_GREEN 32 /* sync on green */
+
+ #define FB_VMODE_NONINTERLACED 0 /* non interlaced */
+-#define FB_VMODE_INTERLACED 1 /* interlaced */
+-#define FB_VMODE_DOUBLE 2 /* double scan */
+-#define FB_VMODE_ODD_FLD_FIRST 4 /* interlaced: top line first */
+-#define FB_VMODE_MASK 255
+-
+-#define FB_VMODE_YWRAP 256 /* ywrap instead of panning */
+-#define FB_VMODE_SMOOTH_XPAN 512 /* smooth xpan possible (internally used) */
+-#define FB_VMODE_CONUPDATE 512 /* don't update x/yoffset */
++#define FB_VMODE_INTERLACED BIT(1) /* interlaced */
++#define FB_VMODE_DOUBLE BIT(2) /* double scan */
++#define FB_VMODE_ODD_FLD_FIRST BIT(3) /* interlaced: top line first */
++#define FB_VMODE_MASK_SIMPLE (BIT(1) | \
++ BIT(2))
++/*
++ * mxc_edid is taking 16 and 32 for ASPECT_16_9/4_3
++ */
++#define FB_VMODE_3D_SBS_HALF BIT(4) /* HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF */
++#define FB_VMODE_3D_SBS_FULL BIT(5) /* HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL */
++#define FB_VMODE_3D_TOP_BOTTOM BIT(6) /* HDMI_3D_STRUCTURE_TOP_AND_BOTTOM */
++#define FB_VMODE_3D_FRAME_PACK BIT(7) /* HDMI_3D_STRUCTURE_FRAME_PACKING */
++#define FB_VMODE_3D_MASK (BIT(4) | \
++ BIT(5) | \
++ BIT(6) | \
++ BIT(7))
++
++#define FB_VMODE_YWRAP BIT(8) /* ywrap instead of panning */
++#define FB_VMODE_SMOOTH_XPAN BIT(9) /* smooth xpan possible (internally used) */
++#define FB_VMODE_CONUPDATE BIT(9) /* don't update x/yoffset */
++
++#define FB_VMODE_ASPECT_1 BIT(10)
++#define FB_VMODE_ASPECT_4_3 BIT(11)
++#define FB_VMODE_ASPECT_5_4 BIT(12)
++#define FB_VMODE_ASPECT_16_9 BIT(13)
++#define FB_VMODE_ASPECT_16_10 BIT(14)
++#define FB_VMODE_ASPECT_MASK (BIT(10) | \
++ BIT(11) | \
++ BIT(12) | \
++ BIT(13) | \
++ BIT(14))
++
++#define FB_VMODE_FRACTIONAL BIT(15)
++
++#define FB_VMODE_MASK (FB_VMODE_MASK_SIMPLE | \
++ FB_VMODE_3D_MASK | \
++ FB_VMODE_ASPECT_MASK | \
++ FB_VMODE_FRACTIONAL)
++
+
+ /*
+ * Display rotation support
+diff -Nur linux-4.1.3/include/uapi/linux/ipu.h linux-xbian-imx6/include/uapi/linux/ipu.h
+--- linux-4.1.3/include/uapi/linux/ipu.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/include/uapi/linux/ipu.h 2015-07-27 23:13:09.861796522 +0200
+@@ -0,0 +1,282 @@
++/*
++ * Copyright (C) 2013 Freescale Semiconductor, Inc. All Rights Reserved
++ */
++
++/*
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++/*!
++ * @defgroup IPU MXC Image Processing Unit (IPU) Driver
++ */
++/*!
++ * @file uapi/linux/ipu.h
++ *
++ * @brief This file contains the IPU driver API declarations.
++ *
++ * @ingroup IPU
++ */
++
++#ifndef __ASM_ARCH_IPU_H__
++#define __ASM_ARCH_IPU_H__
++
++#include <linux/types.h>
++#include <linux/videodev2.h>
++
++#ifndef __KERNEL__
++#ifndef __cplusplus
++typedef unsigned char bool;
++#endif
++#define irqreturn_t int
++#define dma_addr_t int
++#define uint32_t unsigned int
++#define uint16_t unsigned short
++#define uint8_t unsigned char
++#define u32 unsigned int
++#define u8 unsigned char
++#define __u32 u32
++#endif
++
++/*!
++ * Enumeration of IPU rotation modes
++ */
++typedef enum {
++ /* Note the enum values correspond to BAM value */
++ IPU_ROTATE_NONE = 0,
++ IPU_ROTATE_VERT_FLIP = 1,
++ IPU_ROTATE_HORIZ_FLIP = 2,
++ IPU_ROTATE_180 = 3,
++ IPU_ROTATE_90_RIGHT = 4,
++ IPU_ROTATE_90_RIGHT_VFLIP = 5,
++ IPU_ROTATE_90_RIGHT_HFLIP = 6,
++ IPU_ROTATE_90_LEFT = 7,
++} ipu_rotate_mode_t;
++
++/*!
++ * Enumeration of VDI MOTION select
++ */
++typedef enum {
++ MED_MOTION = 0,
++ LOW_MOTION = 1,
++ HIGH_MOTION = 2,
++} ipu_motion_sel;
++
++/*!
++ * Enumeration of DI ports for ADC.
++ */
++typedef enum {
++ DISP0,
++ DISP1,
++ DISP2,
++ DISP3
++} display_port_t;
++
++/* IPU Pixel format definitions */
++/* Four-character-code (FOURCC) */
++#define fourcc(a, b, c, d)\
++ (((__u32)(a)<<0)|((__u32)(b)<<8)|((__u32)(c)<<16)|((__u32)(d)<<24))
++
++/*!
++ * @name IPU Pixel Formats
++ *
++ * Pixel formats are defined with ASCII FOURCC code. The pixel format codes are
++ * the same used by V4L2 API.
++ */
++
++/*! @{ */
++/*! @name Generic or Raw Data Formats */
++/*! @{ */
++#define IPU_PIX_FMT_GENERIC fourcc('I', 'P', 'U', '0') /*!< IPU Generic Data */
++#define IPU_PIX_FMT_GENERIC_32 fourcc('I', 'P', 'U', '1') /*!< IPU Generic Data */
++#define IPU_PIX_FMT_GENERIC_16 fourcc('I', 'P', 'U', '2') /*!< IPU Generic Data */
++#define IPU_PIX_FMT_LVDS666 fourcc('L', 'V', 'D', '6') /*!< IPU Generic Data */
++#define IPU_PIX_FMT_LVDS888 fourcc('L', 'V', 'D', '8') /*!< IPU Generic Data */
++/*! @} */
++/*! @name RGB Formats */
++/*! @{ */
++#define IPU_PIX_FMT_RGB332 fourcc('R', 'G', 'B', '1') /*!< 8 RGB-3-3-2 */
++#define IPU_PIX_FMT_RGB555 fourcc('R', 'G', 'B', 'O') /*!< 16 RGB-5-5-5 */
++#define IPU_PIX_FMT_RGB565 fourcc('R', 'G', 'B', 'P') /*!< 1 6 RGB-5-6-5 */
++#define IPU_PIX_FMT_RGB666 fourcc('R', 'G', 'B', '6') /*!< 18 RGB-6-6-6 */
++#define IPU_PIX_FMT_BGR666 fourcc('B', 'G', 'R', '6') /*!< 18 BGR-6-6-6 */
++#define IPU_PIX_FMT_BGR24 fourcc('B', 'G', 'R', '3') /*!< 24 BGR-8-8-8 */
++#define IPU_PIX_FMT_RGB24 fourcc('R', 'G', 'B', '3') /*!< 24 RGB-8-8-8 */
++#define IPU_PIX_FMT_GBR24 fourcc('G', 'B', 'R', '3') /*!< 24 GBR-8-8-8 */
++#define IPU_PIX_FMT_BGR32 fourcc('B', 'G', 'R', '4') /*!< 32 BGR-8-8-8-8 */
++#define IPU_PIX_FMT_BGRA32 fourcc('B', 'G', 'R', 'A') /*!< 32 BGR-8-8-8-8 */
++#define IPU_PIX_FMT_RGB32 fourcc('R', 'G', 'B', '4') /*!< 32 RGB-8-8-8-8 */
++#define IPU_PIX_FMT_RGBA32 fourcc('R', 'G', 'B', 'A') /*!< 32 RGB-8-8-8-8 */
++#define IPU_PIX_FMT_ABGR32 fourcc('A', 'B', 'G', 'R') /*!< 32 ABGR-8-8-8-8 */
++/*! @} */
++/*! @name YUV Interleaved Formats */
++/*! @{ */
++#define IPU_PIX_FMT_YUYV fourcc('Y', 'U', 'Y', 'V') /*!< 16 YUV 4:2:2 */
++#define IPU_PIX_FMT_UYVY fourcc('U', 'Y', 'V', 'Y') /*!< 16 YUV 4:2:2 */
++#define IPU_PIX_FMT_YVYU fourcc('Y', 'V', 'Y', 'U') /*!< 16 YVYU 4:2:2 */
++#define IPU_PIX_FMT_VYUY fourcc('V', 'Y', 'U', 'Y') /*!< 16 VYYU 4:2:2 */
++#define IPU_PIX_FMT_Y41P fourcc('Y', '4', '1', 'P') /*!< 12 YUV 4:1:1 */
++#define IPU_PIX_FMT_YUV444 fourcc('Y', '4', '4', '4') /*!< 24 YUV 4:4:4 */
++#define IPU_PIX_FMT_VYU444 fourcc('V', '4', '4', '4') /*!< 24 VYU 4:4:4 */
++/* two planes -- one Y, one Cb + Cr interleaved */
++#define IPU_PIX_FMT_NV12 fourcc('N', 'V', '1', '2') /* 12 Y/CbCr 4:2:0 */
++/* two planes -- 12 tiled Y/CbCr 4:2:0 */
++#define IPU_PIX_FMT_TILED_NV12 fourcc('T', 'N', 'V', 'P')
++#define IPU_PIX_FMT_TILED_NV12F fourcc('T', 'N', 'V', 'F')
++
++/*! @} */
++/*! @name YUV Planar Formats */
++/*! @{ */
++#define IPU_PIX_FMT_GREY fourcc('G', 'R', 'E', 'Y') /*!< 8 Greyscale */
++#define IPU_PIX_FMT_YVU410P fourcc('Y', 'V', 'U', '9') /*!< 9 YVU 4:1:0 */
++#define IPU_PIX_FMT_YUV410P fourcc('Y', 'U', 'V', '9') /*!< 9 YUV 4:1:0 */
++#define IPU_PIX_FMT_YVU420P fourcc('Y', 'V', '1', '2') /*!< 12 YVU 4:2:0 */
++#define IPU_PIX_FMT_YUV420P fourcc('I', '4', '2', '0') /*!< 12 YUV 4:2:0 */
++#define IPU_PIX_FMT_YUV420P2 fourcc('Y', 'U', '1', '2') /*!< 12 YUV 4:2:0 */
++#define IPU_PIX_FMT_YVU422P fourcc('Y', 'V', '1', '6') /*!< 16 YVU 4:2:2 */
++#define IPU_PIX_FMT_YUV422P fourcc('4', '2', '2', 'P') /*!< 16 YUV 4:2:2 */
++/* non-interleaved 4:4:4 */
++#define IPU_PIX_FMT_YUV444P fourcc('4', '4', '4', 'P') /*!< 24 YUV 4:4:4 */
++/*! @} */
++#define IPU_PIX_FMT_TILED_NV12_MBALIGN (16)
++#define TILED_NV12_FRAME_SIZE(w, h) \
++ (ALIGN((w) * (h), SZ_4K) + ALIGN((w) * (h) / 2, SZ_4K))
++/* IPU device */
++typedef enum {
++ RGB_CS,
++ YUV_CS,
++ NULL_CS
++} cs_t;
++
++struct ipu_pos {
++ u32 x;
++ u32 y;
++};
++
++struct ipu_crop {
++ struct ipu_pos pos;
++ u32 w;
++ u32 h;
++};
++
++struct ipu_deinterlace {
++ bool enable;
++ u8 motion; /*see ipu_motion_sel*/
++#define IPU_DEINTERLACE_FIELD_TOP 0
++#define IPU_DEINTERLACE_FIELD_BOTTOM 1
++#define IPU_DEINTERLACE_FIELD_MASK \
++ (IPU_DEINTERLACE_FIELD_TOP | IPU_DEINTERLACE_FIELD_BOTTOM)
++ /* deinterlace frame rate double flags */
++#define IPU_DEINTERLACE_RATE_EN 0x80
++#define IPU_DEINTERLACE_RATE_FRAME1 0x40
++#define IPU_DEINTERLACE_RATE_MASK \
++ (IPU_DEINTERLACE_RATE_EN | IPU_DEINTERLACE_RATE_FRAME1)
++#define IPU_DEINTERLACE_MAX_FRAME 2
++ u8 field_fmt;
++};
++
++struct ipu_input {
++ u32 width;
++ u32 height;
++ u32 format;
++ struct ipu_crop crop;
++ dma_addr_t paddr;
++
++ struct ipu_deinterlace deinterlace;
++ dma_addr_t paddr_n; /*valid when deinterlace enable*/
++};
++
++struct ipu_alpha {
++#define IPU_ALPHA_MODE_GLOBAL 0
++#define IPU_ALPHA_MODE_LOCAL 1
++ u8 mode;
++ u8 gvalue; /* 0~255 */
++ dma_addr_t loc_alp_paddr;
++};
++
++struct ipu_colorkey {
++ bool enable;
++ u32 value; /* RGB 24bit */
++};
++
++struct ipu_overlay {
++ u32 width;
++ u32 height;
++ u32 format;
++ struct ipu_crop crop;
++ struct ipu_alpha alpha;
++ struct ipu_colorkey colorkey;
++ dma_addr_t paddr;
++};
++
++struct ipu_output {
++ u32 width;
++ u32 height;
++ u32 format;
++ u8 rotate;
++ struct ipu_crop crop;
++ dma_addr_t paddr;
++};
++
++struct ipu_task {
++ struct ipu_input input;
++ struct ipu_output output;
++
++ bool overlay_en;
++ struct ipu_overlay overlay;
++
++#define IPU_TASK_PRIORITY_NORMAL 0
++#define IPU_TASK_PRIORITY_HIGH 1
++ u8 priority;
++
++#define IPU_TASK_ID_ANY 0
++#define IPU_TASK_ID_VF 1
++#define IPU_TASK_ID_PP 2
++#define IPU_TASK_ID_MAX 3
++ u8 task_id;
++
++ int timeout;
++};
++
++enum {
++ IPU_CHECK_OK = 0,
++ IPU_CHECK_WARN_INPUT_OFFS_NOT8ALIGN = 0x1,
++ IPU_CHECK_WARN_OUTPUT_OFFS_NOT8ALIGN = 0x2,
++ IPU_CHECK_WARN_OVERLAY_OFFS_NOT8ALIGN = 0x4,
++ IPU_CHECK_ERR_MIN,
++ IPU_CHECK_ERR_INPUT_CROP,
++ IPU_CHECK_ERR_OUTPUT_CROP,
++ IPU_CHECK_ERR_OVERLAY_CROP,
++ IPU_CHECK_ERR_INPUT_OVER_LIMIT,
++ IPU_CHECK_ERR_OV_OUT_NO_FIT,
++ IPU_CHECK_ERR_OVERLAY_WITH_VDI,
++ IPU_CHECK_ERR_PROC_NO_NEED,
++ IPU_CHECK_ERR_SPLIT_INPUTW_OVER,
++ IPU_CHECK_ERR_SPLIT_INPUTH_OVER,
++ IPU_CHECK_ERR_SPLIT_OUTPUTW_OVER,
++ IPU_CHECK_ERR_SPLIT_OUTPUTH_OVER,
++ IPU_CHECK_ERR_SPLIT_WITH_ROT,
++ IPU_CHECK_ERR_NOT_SUPPORT,
++ IPU_CHECK_ERR_NOT16ALIGN,
++ IPU_CHECK_ERR_W_DOWNSIZE_OVER,
++ IPU_CHECK_ERR_H_DOWNSIZE_OVER,
++};
++
++/* IOCTL commands */
++#define IPU_CHECK_TASK _IOWR('I', 0x1, struct ipu_task)
++#define IPU_QUEUE_TASK _IOW('I', 0x2, struct ipu_task)
++#define IPU_ALLOC _IOWR('I', 0x3, int)
++#define IPU_FREE _IOW('I', 0x4, int)
++
++#endif
+diff -Nur linux-4.1.3/include/uapi/linux/Kbuild linux-xbian-imx6/include/uapi/linux/Kbuild
+--- linux-4.1.3/include/uapi/linux/Kbuild 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/include/uapi/linux/Kbuild 2015-07-27 23:13:09.849839184 +0200
+@@ -266,6 +266,9 @@
+ header-y += msdos_fs.h
+ header-y += msg.h
+ header-y += mtio.h
++header-y += mxcfb.h
++header-y += mxc_dcic.h
++header-y += ipu.h
+ header-y += nbd.h
+ header-y += ncp_fs.h
+ header-y += ncp.h
+@@ -451,3 +454,6 @@
+ header-y += xilinx-v4l2-controls.h
+ header-y += zorro.h
+ header-y += zorro_ids.h
++
++header-y += pxp_device.h
++header-y += pxp_dma.h
+diff -Nur linux-4.1.3/include/uapi/linux/mxc_asrc.h linux-xbian-imx6/include/uapi/linux/mxc_asrc.h
+--- linux-4.1.3/include/uapi/linux/mxc_asrc.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/include/uapi/linux/mxc_asrc.h 2015-07-27 23:13:09.865782301 +0200
+@@ -0,0 +1,143 @@
++/*
++ * Copyright 2008-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ *
++ * @file mxc_asrc.h
++ *
++ * @brief i.MX Asynchronous Sample Rate Converter
++ *
++ * @ingroup Audio
++ */
++
++#ifndef __MXC_ASRC_UAPI_H__
++#define __MXC_ASRC_UAPI_H__
++
++#define ASRC_IOC_MAGIC 'C'
++
++#define ASRC_REQ_PAIR _IOWR(ASRC_IOC_MAGIC, 0, struct asrc_req)
++#define ASRC_CONFIG_PAIR _IOWR(ASRC_IOC_MAGIC, 1, struct asrc_config)
++#define ASRC_RELEASE_PAIR _IOW(ASRC_IOC_MAGIC, 2, enum asrc_pair_index)
++#define ASRC_CONVERT _IOW(ASRC_IOC_MAGIC, 3, struct asrc_convert_buffer)
++#define ASRC_START_CONV _IOW(ASRC_IOC_MAGIC, 4, enum asrc_pair_index)
++#define ASRC_STOP_CONV _IOW(ASRC_IOC_MAGIC, 5, enum asrc_pair_index)
++#define ASRC_STATUS _IOW(ASRC_IOC_MAGIC, 6, struct asrc_status_flags)
++#define ASRC_FLUSH _IOW(ASRC_IOC_MAGIC, 7, enum asrc_pair_index)
++
++enum asrc_pair_index {
++ ASRC_UNVALID_PAIR = -1,
++ ASRC_PAIR_A = 0,
++ ASRC_PAIR_B = 1,
++ ASRC_PAIR_C = 2,
++};
++
++#define ASRC_PAIR_MAX_NUM (ASRC_PAIR_C + 1)
++
++enum asrc_inclk {
++ INCLK_NONE = 0x03,
++ INCLK_ESAI_RX = 0x00,
++ INCLK_SSI1_RX = 0x01,
++ INCLK_SSI2_RX = 0x02,
++ INCLK_SSI3_RX = 0x07,
++ INCLK_SPDIF_RX = 0x04,
++ INCLK_MLB_CLK = 0x05,
++ INCLK_PAD = 0x06,
++ INCLK_ESAI_TX = 0x08,
++ INCLK_SSI1_TX = 0x09,
++ INCLK_SSI2_TX = 0x0a,
++ INCLK_SSI3_TX = 0x0b,
++ INCLK_SPDIF_TX = 0x0c,
++ INCLK_ASRCK1_CLK = 0x0f,
++};
++
++enum asrc_outclk {
++ OUTCLK_NONE = 0x03,
++ OUTCLK_ESAI_TX = 0x00,
++ OUTCLK_SSI1_TX = 0x01,
++ OUTCLK_SSI2_TX = 0x02,
++ OUTCLK_SSI3_TX = 0x07,
++ OUTCLK_SPDIF_TX = 0x04,
++ OUTCLK_MLB_CLK = 0x05,
++ OUTCLK_PAD = 0x06,
++ OUTCLK_ESAI_RX = 0x08,
++ OUTCLK_SSI1_RX = 0x09,
++ OUTCLK_SSI2_RX = 0x0a,
++ OUTCLK_SSI3_RX = 0x0b,
++ OUTCLK_SPDIF_RX = 0x0c,
++ OUTCLK_ASRCK1_CLK = 0x0f,
++};
++
++enum asrc_word_width {
++ ASRC_WIDTH_24_BIT = 0,
++ ASRC_WIDTH_16_BIT = 1,
++ ASRC_WIDTH_8_BIT = 2,
++};
++
++struct asrc_config {
++ enum asrc_pair_index pair;
++ unsigned int channel_num;
++ unsigned int buffer_num;
++ unsigned int dma_buffer_size;
++ unsigned int input_sample_rate;
++ unsigned int output_sample_rate;
++ enum asrc_word_width input_word_width;
++ enum asrc_word_width output_word_width;
++ enum asrc_inclk inclk;
++ enum asrc_outclk outclk;
++};
++
++struct asrc_pair {
++ unsigned int start_channel;
++ unsigned int chn_num;
++ unsigned int chn_max;
++ unsigned int active;
++ unsigned int overload_error;
++};
++
++struct asrc_req {
++ unsigned int chn_num;
++ enum asrc_pair_index index;
++};
++
++struct asrc_querybuf {
++ unsigned int buffer_index;
++ unsigned int input_length;
++ unsigned int output_length;
++ unsigned long input_offset;
++ unsigned long output_offset;
++};
++
++struct asrc_convert_buffer {
++ void *input_buffer_vaddr;
++ void *output_buffer_vaddr;
++ unsigned int input_buffer_length;
++ unsigned int output_buffer_length;
++};
++
++struct asrc_buffer {
++ unsigned int index;
++ unsigned int length;
++ unsigned int output_last_length;
++ int buf_valid;
++};
++
++struct asrc_status_flags {
++ enum asrc_pair_index index;
++ unsigned int overload_error;
++};
++
++#define ASRC_BUF_NA -35 /* ASRC DQ's buffer is NOT available */
++#define ASRC_BUF_AV 35 /* ASRC DQ's buffer is available */
++enum asrc_error_status {
++ ASRC_TASK_Q_OVERLOAD = 0x01,
++ ASRC_OUTPUT_TASK_OVERLOAD = 0x02,
++ ASRC_INPUT_TASK_OVERLOAD = 0x04,
++ ASRC_OUTPUT_BUFFER_OVERFLOW = 0x08,
++ ASRC_INPUT_BUFFER_UNDERRUN = 0x10,
++};
++#endif/* __MXC_ASRC_UAPI_H__ */
+diff -Nur linux-4.1.3/include/uapi/linux/mxc_dcic.h linux-xbian-imx6/include/uapi/linux/mxc_dcic.h
+--- linux-4.1.3/include/uapi/linux/mxc_dcic.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/include/uapi/linux/mxc_dcic.h 2015-07-27 23:13:09.865782301 +0200
+@@ -0,0 +1,49 @@
++/*
++ * Copyright (C) 2014 Freescale Semiconductor, Inc. All Rights Reserved
++ */
++
++/*
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++/*!
++ * @file uapi/linux/mxc_dcic.h
++ *
++ * @brief MXC DCIC private header file
++ *
++ * @ingroup MXC DCIC
++ */
++#ifndef __ASM_ARCH_MXC_DCIC_H__
++#define __ASM_ARCH_MXC_DCIC_H__
++
++#define DCIC_IOC_ALLOC_ROI_NUM _IO('D', 10)
++#define DCIC_IOC_FREE_ROI_NUM _IO('D', 11)
++#define DCIC_IOC_CONFIG_DCIC _IO('D', 12)
++#define DCIC_IOC_CONFIG_ROI _IO('D', 13)
++#define DCIC_IOC_GET_RESULT _IO('D', 14)
++#define DCIC_IOC_START_VSYNC _IO('D', 15)
++#define DCIC_IOC_STOP_VSYNC _IO('D', 16)
++
++struct roi_params {
++ unsigned int roi_n;
++ unsigned int ref_sig;
++ unsigned int start_y;
++ unsigned int start_x;
++ unsigned int end_y;
++ unsigned int end_x;
++ char freeze;
++};
++
++#endif
+diff -Nur linux-4.1.3/include/uapi/linux/mxcfb.h linux-xbian-imx6/include/uapi/linux/mxcfb.h
+--- linux-4.1.3/include/uapi/linux/mxcfb.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/include/uapi/linux/mxcfb.h 2015-07-27 23:13:09.865782301 +0200
+@@ -0,0 +1,176 @@
++/*
++ * Copyright (C) 2013-2014 Freescale Semiconductor, Inc. All Rights Reserved
++ */
++
++/*
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++/*
++ * @file uapi/linux/mxcfb.h
++ *
++ * @brief Global header file for the MXC frame buffer
++ *
++ * @ingroup Framebuffer
++ */
++#ifndef __ASM_ARCH_MXCFB_H__
++#define __ASM_ARCH_MXCFB_H__
++
++#include <linux/fb.h>
++
++#define FB_SYNC_OE_LOW_ACT 0x80000000
++#define FB_SYNC_CLK_LAT_FALL 0x40000000
++#define FB_SYNC_DATA_INVERT 0x20000000
++#define FB_SYNC_CLK_IDLE_EN 0x10000000
++#define FB_SYNC_SHARP_MODE 0x08000000
++#define FB_SYNC_SWAP_RGB 0x04000000
++#define FB_ACCEL_TRIPLE_FLAG 0x00000000
++#define FB_ACCEL_DOUBLE_FLAG 0x00000001
++
++struct mxcfb_gbl_alpha {
++ int enable;
++ int alpha;
++};
++
++struct mxcfb_loc_alpha {
++ int enable;
++ int alpha_in_pixel;
++ unsigned long alpha_phy_addr0;
++ unsigned long alpha_phy_addr1;
++};
++
++struct mxcfb_color_key {
++ int enable;
++ __u32 color_key;
++};
++
++struct mxcfb_pos {
++ __u16 x;
++ __u16 y;
++};
++
++struct mxcfb_gamma {
++ int enable;
++ int constk[16];
++ int slopek[16];
++};
++
++struct mxcfb_rect {
++ __u32 top;
++ __u32 left;
++ __u32 width;
++ __u32 height;
++};
++
++#define GRAYSCALE_8BIT 0x1
++#define GRAYSCALE_8BIT_INVERTED 0x2
++#define GRAYSCALE_4BIT 0x3
++#define GRAYSCALE_4BIT_INVERTED 0x4
++
++#define AUTO_UPDATE_MODE_REGION_MODE 0
++#define AUTO_UPDATE_MODE_AUTOMATIC_MODE 1
++
++#define UPDATE_SCHEME_SNAPSHOT 0
++#define UPDATE_SCHEME_QUEUE 1
++#define UPDATE_SCHEME_QUEUE_AND_MERGE 2
++
++#define UPDATE_MODE_PARTIAL 0x0
++#define UPDATE_MODE_FULL 0x1
++
++#define WAVEFORM_MODE_AUTO 257
++
++#define TEMP_USE_AMBIENT 0x1000
++
++#define EPDC_FLAG_ENABLE_INVERSION 0x01
++#define EPDC_FLAG_FORCE_MONOCHROME 0x02
++#define EPDC_FLAG_USE_CMAP 0x04
++#define EPDC_FLAG_USE_ALT_BUFFER 0x100
++#define EPDC_FLAG_TEST_COLLISION 0x200
++#define EPDC_FLAG_GROUP_UPDATE 0x400
++#define EPDC_FLAG_USE_DITHERING_Y1 0x2000
++#define EPDC_FLAG_USE_DITHERING_Y4 0x4000
++
++#define FB_POWERDOWN_DISABLE -1
++
++struct mxcfb_alt_buffer_data {
++ __u32 phys_addr;
++ __u32 width; /* width of entire buffer */
++ __u32 height; /* height of entire buffer */
++ struct mxcfb_rect alt_update_region; /* region within buffer to update */
++};
++
++struct mxcfb_update_data {
++ struct mxcfb_rect update_region;
++ __u32 waveform_mode;
++ __u32 update_mode;
++ __u32 update_marker;
++ int temp;
++ unsigned int flags;
++ struct mxcfb_alt_buffer_data alt_buffer_data;
++};
++
++struct mxcfb_update_marker_data {
++ __u32 update_marker;
++ __u32 collision_test;
++};
++
++/*
++ * Structure used to define waveform modes for driver
++ * Needed for driver to perform auto-waveform selection
++ */
++struct mxcfb_waveform_modes {
++ int mode_init;
++ int mode_du;
++ int mode_gc4;
++ int mode_gc8;
++ int mode_gc16;
++ int mode_gc32;
++};
++
++/*
++ * Structure used to define a 5*3 matrix of parameters for
++ * setting IPU DP CSC module related to this framebuffer.
++ */
++struct mxcfb_csc_matrix {
++ int param[5][3];
++};
++
++#define MXCFB_WAIT_FOR_VSYNC _IOW('F', 0x20, u_int32_t)
++#define MXCFB_SET_GBL_ALPHA _IOW('F', 0x21, struct mxcfb_gbl_alpha)
++#define MXCFB_SET_CLR_KEY _IOW('F', 0x22, struct mxcfb_color_key)
++#define MXCFB_SET_OVERLAY_POS _IOWR('F', 0x24, struct mxcfb_pos)
++#define MXCFB_GET_FB_IPU_CHAN _IOR('F', 0x25, u_int32_t)
++#define MXCFB_SET_LOC_ALPHA _IOWR('F', 0x26, struct mxcfb_loc_alpha)
++#define MXCFB_SET_LOC_ALP_BUF _IOW('F', 0x27, unsigned long)
++#define MXCFB_SET_GAMMA _IOW('F', 0x28, struct mxcfb_gamma)
++#define MXCFB_GET_FB_IPU_DI _IOR('F', 0x29, u_int32_t)
++#define MXCFB_GET_DIFMT _IOR('F', 0x2A, u_int32_t)
++#define MXCFB_GET_FB_BLANK _IOR('F', 0x2B, u_int32_t)
++#define MXCFB_SET_DIFMT _IOW('F', 0x2C, u_int32_t)
++#define MXCFB_CSC_UPDATE _IOW('F', 0x2D, struct mxcfb_csc_matrix)
++
++/* IOCTLs for E-ink panel updates */
++#define MXCFB_SET_WAVEFORM_MODES _IOW('F', 0x2B, struct mxcfb_waveform_modes)
++#define MXCFB_SET_TEMPERATURE _IOW('F', 0x2C, int32_t)
++#define MXCFB_SET_AUTO_UPDATE_MODE _IOW('F', 0x2D, __u32)
++#define MXCFB_SEND_UPDATE _IOW('F', 0x2E, struct mxcfb_update_data)
++#define MXCFB_WAIT_FOR_UPDATE_COMPLETE _IOWR('F', 0x2F, struct mxcfb_update_marker_data)
++#define MXCFB_SET_PWRDOWN_DELAY _IOW('F', 0x30, int32_t)
++#define MXCFB_GET_PWRDOWN_DELAY _IOR('F', 0x31, int32_t)
++#define MXCFB_SET_UPDATE_SCHEME _IOW('F', 0x32, __u32)
++#define MXCFB_GET_WORK_BUFFER _IOWR('F', 0x34, unsigned long)
++#define MXCFB_DISABLE_EPDC_ACCESS _IO('F', 0x35)
++#define MXCFB_ENABLE_EPDC_ACCESS _IO('F', 0x36)
++#endif
+diff -Nur linux-4.1.3/include/uapi/linux/mxc_mlb.h linux-xbian-imx6/include/uapi/linux/mxc_mlb.h
+--- linux-4.1.3/include/uapi/linux/mxc_mlb.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/include/uapi/linux/mxc_mlb.h 2015-07-27 23:13:09.865782301 +0200
+@@ -0,0 +1,55 @@
++/*
++ * mxc_mlb.h
++ *
++ * Copyright 2008-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++#ifndef _MXC_MLB_UAPI_H
++#define _MXC_MLB_UAPI_H
++
++/* define IOCTL command */
++#define MLB_DBG_RUNTIME _IO('S', 0x09)
++#define MLB_SET_FPS _IOW('S', 0x10, unsigned int)
++#define MLB_GET_VER _IOR('S', 0x11, unsigned long)
++#define MLB_SET_DEVADDR _IOR('S', 0x12, unsigned char)
++
++/*!
++ * set channel address for each logical channel
++ * the MSB 16bits is for tx channel, the left LSB is for rx channel
++ */
++#define MLB_CHAN_SETADDR _IOW('S', 0x13, unsigned int)
++#define MLB_CHAN_STARTUP _IO('S', 0x14)
++#define MLB_CHAN_SHUTDOWN _IO('S', 0x15)
++#define MLB_CHAN_GETEVENT _IOR('S', 0x16, unsigned long)
++
++#define MLB_SET_ISOC_BLKSIZE_188 _IO('S', 0x17)
++#define MLB_SET_ISOC_BLKSIZE_196 _IO('S', 0x18)
++#define MLB_SET_SYNC_QUAD _IOW('S', 0x19, unsigned int)
++#define MLB_IRQ_ENABLE _IO('S', 0x20)
++#define MLB_IRQ_DISABLE _IO('S', 0x21)
++
++/*!
++ * MLB event define
++ */
++enum {
++ MLB_EVT_TX_PROTO_ERR_CUR = 1 << 0,
++ MLB_EVT_TX_BRK_DETECT_CUR = 1 << 1,
++ MLB_EVT_TX_PROTO_ERR_PREV = 1 << 8,
++ MLB_EVT_TX_BRK_DETECT_PREV = 1 << 9,
++ MLB_EVT_RX_PROTO_ERR_CUR = 1 << 16,
++ MLB_EVT_RX_BRK_DETECT_CUR = 1 << 17,
++ MLB_EVT_RX_PROTO_ERR_PREV = 1 << 24,
++ MLB_EVT_RX_BRK_DETECT_PREV = 1 << 25,
++};
++
++
++#endif /* _MXC_MLB_H */
+diff -Nur linux-4.1.3/include/uapi/linux/mxc_v4l2.h linux-xbian-imx6/include/uapi/linux/mxc_v4l2.h
+--- linux-4.1.3/include/uapi/linux/mxc_v4l2.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/include/uapi/linux/mxc_v4l2.h 2015-07-27 23:13:09.865782301 +0200
+@@ -0,0 +1,56 @@
++/*
++ * Copyright (C) 2013 Freescale Semiconductor, Inc. All Rights Reserved
++ */
++
++/*
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++/*!
++ * @file uapi/linux/mxc_v4l2.h
++ *
++ * @brief MXC V4L2 private header file
++ *
++ * @ingroup MXC V4L2
++ */
++
++#ifndef __ASM_ARCH_MXC_V4L2_H__
++#define __ASM_ARCH_MXC_V4L2_H__
++
++/*
++ * For IPUv1 and IPUv3, V4L2_CID_MXC_ROT means encoder ioctl ID.
++ * And V4L2_CID_MXC_VF_ROT is viewfinder ioctl ID only for IPUv1 and IPUv3.
++ */
++#define V4L2_CID_MXC_ROT (V4L2_CID_PRIVATE_BASE + 0)
++#define V4L2_CID_MXC_FLASH (V4L2_CID_PRIVATE_BASE + 1)
++#define V4L2_CID_MXC_VF_ROT (V4L2_CID_PRIVATE_BASE + 2)
++#define V4L2_CID_MXC_MOTION (V4L2_CID_PRIVATE_BASE + 3)
++#define V4L2_CID_MXC_SWITCH_CAM (V4L2_CID_PRIVATE_BASE + 6)
++
++#define V4L2_MXC_ROTATE_NONE 0
++#define V4L2_MXC_ROTATE_VERT_FLIP 1
++#define V4L2_MXC_ROTATE_HORIZ_FLIP 2
++#define V4L2_MXC_ROTATE_180 3
++#define V4L2_MXC_ROTATE_90_RIGHT 4
++#define V4L2_MXC_ROTATE_90_RIGHT_VFLIP 5
++#define V4L2_MXC_ROTATE_90_RIGHT_HFLIP 6
++#define V4L2_MXC_ROTATE_90_LEFT 7
++
++struct v4l2_mxc_offset {
++ uint32_t u_offset;
++ uint32_t v_offset;
++};
++
++#endif
+diff -Nur linux-4.1.3/include/uapi/linux/pxp_device.h linux-xbian-imx6/include/uapi/linux/pxp_device.h
+--- linux-4.1.3/include/uapi/linux/pxp_device.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/include/uapi/linux/pxp_device.h 2015-07-27 23:13:09.941512106 +0200
+@@ -0,0 +1,63 @@
++/*
++ * Copyright (C) 2013-2014 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ */
++#ifndef _UAPI_PXP_DEVICE
++#define _UAPI_PXP_DEVICE
++
++#include <linux/pxp_dma.h>
++
++struct pxp_chan_handle {
++ unsigned int handle;
++ int hist_status;
++};
++
++struct pxp_mem_desc {
++ unsigned int handle;
++ unsigned int size;
++ dma_addr_t phys_addr;
++ unsigned int virt_uaddr; /* virtual user space address */
++ unsigned int mtype;
++};
++
++struct pxp_mem_flush {
++ unsigned int handle;
++ unsigned int type;
++};
++
++#define PXP_IOC_MAGIC 'P'
++
++#define PXP_IOC_GET_CHAN _IOR(PXP_IOC_MAGIC, 0, struct pxp_mem_desc)
++#define PXP_IOC_PUT_CHAN _IOW(PXP_IOC_MAGIC, 1, struct pxp_mem_desc)
++#define PXP_IOC_CONFIG_CHAN _IOW(PXP_IOC_MAGIC, 2, struct pxp_mem_desc)
++#define PXP_IOC_START_CHAN _IOW(PXP_IOC_MAGIC, 3, struct pxp_mem_desc)
++#define PXP_IOC_GET_PHYMEM _IOWR(PXP_IOC_MAGIC, 4, struct pxp_mem_desc)
++#define PXP_IOC_PUT_PHYMEM _IOW(PXP_IOC_MAGIC, 5, struct pxp_mem_desc)
++#define PXP_IOC_WAIT4CMPLT _IOWR(PXP_IOC_MAGIC, 6, struct pxp_mem_desc)
++#define PXP_IOC_FLUSH_PHYMEM _IOR(PXP_IOC_MAGIC, 7, struct pxp_mem_flush)
++
++/* Memory types supported*/
++#define MEMORY_TYPE_UNCACHED 0x0
++#define MEMORY_TYPE_WC 0x1
++#define MEMORY_TYPE_CACHED 0x2
++
++/* Cache flush operations */
++#define CACHE_CLEAN 0x1
++#define CACHE_INVALIDATE 0x2
++#define CACHE_FLUSH 0x4
++
++#endif
+diff -Nur linux-4.1.3/include/uapi/linux/pxp_dma.h linux-xbian-imx6/include/uapi/linux/pxp_dma.h
+--- linux-4.1.3/include/uapi/linux/pxp_dma.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/include/uapi/linux/pxp_dma.h 2015-07-27 23:13:09.941512106 +0200
+@@ -0,0 +1,173 @@
++/*
++ * Copyright (C) 2013-2015 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ */
++#ifndef _UAPI_PXP_DMA
++#define _UAPI_PXP_DMA
++
++#include <linux/posix_types.h>
++#include <linux/types.h>
++
++#ifndef __KERNEL__
++typedef unsigned long dma_addr_t;
++typedef unsigned char bool;
++#endif
++
++/* PXP Pixel format definitions */
++/* Four-character-code (FOURCC) */
++#define fourcc(a, b, c, d)\
++ (((__u32)(a)<<0)|((__u32)(b)<<8)|((__u32)(c)<<16)|((__u32)(d)<<24))
++
++/*!
++ * @name PXP Pixel Formats
++ *
++ * Pixel formats are defined with ASCII FOURCC code. The pixel format codes are
++ * the same used by V4L2 API.
++ */
++
++/*! @} */
++/*! @name RGB Formats */
++/*! @{ */
++#define PXP_PIX_FMT_RGB332 fourcc('R', 'G', 'B', '1') /*!< 8 RGB-3-3-2 */
++#define PXP_PIX_FMT_RGB555 fourcc('R', 'G', 'B', 'O') /*!< 16 RGB-5-5-5 */
++#define PXP_PIX_FMT_RGB565 fourcc('R', 'G', 'B', 'P') /*!< 1 6 RGB-5-6-5 */
++#define PXP_PIX_FMT_RGB666 fourcc('R', 'G', 'B', '6') /*!< 18 RGB-6-6-6 */
++#define PXP_PIX_FMT_BGR666 fourcc('B', 'G', 'R', '6') /*!< 18 BGR-6-6-6 */
++#define PXP_PIX_FMT_BGR24 fourcc('B', 'G', 'R', '3') /*!< 24 BGR-8-8-8 */
++#define PXP_PIX_FMT_RGB24 fourcc('R', 'G', 'B', '3') /*!< 24 RGB-8-8-8 */
++#define PXP_PIX_FMT_BGR32 fourcc('B', 'G', 'R', '4') /*!< 32 BGR-8-8-8-8 */
++#define PXP_PIX_FMT_BGRA32 fourcc('B', 'G', 'R', 'A') /*!< 32 BGR-8-8-8-8 */
++#define PXP_PIX_FMT_RGB32 fourcc('R', 'G', 'B', '4') /*!< 32 RGB-8-8-8-8 */
++#define PXP_PIX_FMT_RGBA32 fourcc('R', 'G', 'B', 'A') /*!< 32 RGB-8-8-8-8 */
++#define PXP_PIX_FMT_ABGR32 fourcc('A', 'B', 'G', 'R') /*!< 32 ABGR-8-8-8-8 */
++/*! @} */
++/*! @name YUV Interleaved Formats */
++/*! @{ */
++#define PXP_PIX_FMT_YUYV fourcc('Y', 'U', 'Y', 'V') /*!< 16 YUV 4:2:2 */
++#define PXP_PIX_FMT_UYVY fourcc('U', 'Y', 'V', 'Y') /*!< 16 YUV 4:2:2 */
++#define PXP_PIX_FMT_VYUY fourcc('V', 'Y', 'U', 'Y') /*!< 16 YVU 4:2:2 */
++#define PXP_PIX_FMT_YVYU fourcc('Y', 'V', 'Y', 'U') /*!< 16 YVU 4:2:2 */
++#define PXP_PIX_FMT_Y41P fourcc('Y', '4', '1', 'P') /*!< 12 YUV 4:1:1 */
++#define PXP_PIX_FMT_VUY444 fourcc('V', 'U', 'Y', 'A') /*!< 32 VUYA 8:8:8 */
++/* two planes -- one Y, one Cb + Cr interleaved */
++#define PXP_PIX_FMT_NV12 fourcc('N', 'V', '1', '2') /* 12 Y/CbCr 4:2:0 */
++#define PXP_PIX_FMT_NV21 fourcc('N', 'V', '2', '1') /* 12 Y/CbCr 4:2:0 */
++#define PXP_PIX_FMT_NV16 fourcc('N', 'V', '1', '6') /* 12 Y/CbCr 4:2:2 */
++#define PXP_PIX_FMT_NV61 fourcc('N', 'V', '6', '1') /* 12 Y/CbCr 4:2:2 */
++/*! @} */
++/*! @name YUV Planar Formats */
++/*! @{ */
++#define PXP_PIX_FMT_GREY fourcc('G', 'R', 'E', 'Y') /*!< 8 Greyscale */
++#define PXP_PIX_FMT_GY04 fourcc('G', 'Y', '0', '4') /*!< 4 Greyscale */
++#define PXP_PIX_FMT_YVU410P fourcc('Y', 'V', 'U', '9') /*!< 9 YVU 4:1:0 */
++#define PXP_PIX_FMT_YUV410P fourcc('Y', 'U', 'V', '9') /*!< 9 YUV 4:1:0 */
++#define PXP_PIX_FMT_YVU420P fourcc('Y', 'V', '1', '2') /*!< 12 YVU 4:2:0 */
++#define PXP_PIX_FMT_YUV420P fourcc('I', '4', '2', '0') /*!< 12 YUV 4:2:0 */
++#define PXP_PIX_FMT_YUV420P2 fourcc('Y', 'U', '1', '2') /*!< 12 YUV 4:2:0 */
++#define PXP_PIX_FMT_YVU422P fourcc('Y', 'V', '1', '6') /*!< 16 YVU 4:2:2 */
++#define PXP_PIX_FMT_YUV422P fourcc('4', '2', '2', 'P') /*!< 16 YUV 4:2:2 */
++/*! @} */
++
++#define PXP_LUT_NONE 0x0
++#define PXP_LUT_INVERT 0x1
++#define PXP_LUT_BLACK_WHITE 0x2
++#define PXP_LUT_USE_CMAP 0x4
++
++#define NR_PXP_VIRT_CHANNEL 16
++
++/* Order significant! */
++enum pxp_channel_status {
++ PXP_CHANNEL_FREE,
++ PXP_CHANNEL_INITIALIZED,
++ PXP_CHANNEL_READY,
++};
++
++struct rect {
++ int top; /* Upper left coordinate of rectangle */
++ int left;
++ int width;
++ int height;
++};
++
++struct pxp_layer_param {
++ unsigned short width;
++ unsigned short height;
++ unsigned short stride; /* aka pitch */
++ unsigned int pixel_fmt;
++
++ /* layers combining parameters
++ * (these are ignored for S0 and output
++ * layers, and only apply for OL layer)
++ */
++ bool combine_enable;
++ unsigned int color_key_enable;
++ unsigned int color_key;
++ bool global_alpha_enable;
++ /* global alpha is either override or multiply */
++ bool global_override;
++ unsigned char global_alpha;
++ bool alpha_invert;
++ bool local_alpha_enable;
++
++ dma_addr_t paddr;
++};
++
++struct pxp_proc_data {
++ /* S0 Transformation Info */
++ int scaling;
++ int hflip;
++ int vflip;
++ int rotate;
++ int rot_pos;
++ int yuv;
++
++ /* Source rectangle (srect) defines the sub-rectangle
++ * within S0 to undergo processing.
++ */
++ struct rect srect;
++ /* Dest rect (drect) defines how to position the processed
++ * source rectangle (after resizing) within the output frame,
++ * whose dimensions are defined in pxp->pxp_conf_state.out_param
++ */
++ struct rect drect;
++
++ /* Current S0 configuration */
++ unsigned int bgcolor;
++
++ /* Output overlay support */
++ int overlay_state;
++
++ /* LUT transformation on Y data */
++ int lut_transform;
++ unsigned char *lut_map; /* 256 entries */
++ bool lut_map_updated; /* Map recently changed */
++ bool combine_enable;
++};
++
++struct pxp_config_data {
++ struct pxp_layer_param s0_param;
++ struct pxp_layer_param ol_param[8];
++ struct pxp_layer_param out_param;
++ struct pxp_proc_data proc_data;
++ int layer_nr;
++
++ /* Users don't touch */
++ int handle;
++};
++
++
++#endif
+diff -Nur linux-4.1.3/include/uapi/sync.h linux-xbian-imx6/include/uapi/sync.h
+--- linux-4.1.3/include/uapi/sync.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/include/uapi/sync.h 2015-07-27 23:13:09.977384118 +0200
+@@ -0,0 +1,97 @@
++/*
++ * Copyright (C) 2012 Google, Inc.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ */
++
++#ifndef _UAPI_LINUX_SYNC_H
++#define _UAPI_LINUX_SYNC_H
++
++#include <linux/ioctl.h>
++#include <linux/types.h>
++
++/**
++ * struct sync_merge_data - data passed to merge ioctl
++ * @fd2: file descriptor of second fence
++ * @name: name of new fence
++ * @fence: returns the fd of the new fence to userspace
++ */
++struct sync_merge_data {
++ __s32 fd2; /* fd of second fence */
++ char name[32]; /* name of new fence */
++ __s32 fence; /* fd on newly created fence */
++};
++
++/**
++ * struct sync_pt_info - detailed sync_pt information
++ * @len: length of sync_pt_info including any driver_data
++ * @obj_name: name of parent sync_timeline
++ * @driver_name: name of driver implementing the parent
++ * @status: status of the sync_pt 0:active 1:signaled <0:error
++ * @timestamp_ns: timestamp of status change in nanoseconds
++ * @driver_data: any driver dependent data
++ */
++struct sync_pt_info {
++ __u32 len;
++ char obj_name[32];
++ char driver_name[32];
++ __s32 status;
++ __u64 timestamp_ns;
++
++ __u8 driver_data[0];
++};
++
++/**
++ * struct sync_fence_info_data - data returned from fence info ioctl
++ * @len: ioctl caller writes the size of the buffer its passing in.
++ * ioctl returns length of sync_fence_data returned to userspace
++ * including pt_info.
++ * @name: name of fence
++ * @status: status of fence. 1: signaled 0:active <0:error
++ * @pt_info: a sync_pt_info struct for every sync_pt in the fence
++ */
++struct sync_fence_info_data {
++ __u32 len;
++ char name[32];
++ __s32 status;
++
++ __u8 pt_info[0];
++};
++
++#define SYNC_IOC_MAGIC '>'
++
++/**
++ * DOC: SYNC_IOC_WAIT - wait for a fence to signal
++ *
++ * pass timeout in milliseconds. Waits indefinitely timeout < 0.
++ */
++#define SYNC_IOC_WAIT _IOW(SYNC_IOC_MAGIC, 0, __s32)
++
++/**
++ * DOC: SYNC_IOC_MERGE - merge two fences
++ *
++ * Takes a struct sync_merge_data. Creates a new fence containing copies of
++ * the sync_pts in both the calling fd and sync_merge_data.fd2. Returns the
++ * new fence's fd in sync_merge_data.fence
++ */
++#define SYNC_IOC_MERGE _IOWR(SYNC_IOC_MAGIC, 1, struct sync_merge_data)
++
++/**
++ * DOC: SYNC_IOC_FENCE_INFO - get detailed information on a fence
++ *
++ * Takes a struct sync_fence_info_data with extra space allocated for pt_info.
++ * Caller should write the size of the buffer into len. On return, len is
++ * updated to reflect the total size of the sync_fence_info_data including
++ * pt_info.
++ *
++ * pt_info is a buffer containing sync_pt_infos for every sync_pt in the fence.
++ * To iterate over the sync_pt_infos, use the sync_pt_info.len field.
++ */
++#define SYNC_IOC_FENCE_INFO _IOWR(SYNC_IOC_MAGIC, 2,\
++ struct sync_fence_info_data)
++
++#endif /* _UAPI_LINUX_SYNC_H */
+diff -Nur linux-4.1.3/include/usb-ehci-mxc.h linux-xbian-imx6/include/usb-ehci-mxc.h
+--- linux-4.1.3/include/usb-ehci-mxc.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/include/usb-ehci-mxc.h 2015-07-27 23:13:09.981369897 +0200
+@@ -0,0 +1,13 @@
++#ifndef __INCLUDE_ASM_ARCH_MXC_EHCI_H
++#define __INCLUDE_ASM_ARCH_MXC_EHCI_H
++
++struct mxc_usbh_platform_data {
++ int (*init)(struct platform_device *pdev);
++ int (*exit)(struct platform_device *pdev);
++
++ unsigned int portsc;
++ struct usb_phy *otg;
++};
++
++#endif /* __INCLUDE_ASM_ARCH_MXC_EHCI_H */
++
+diff -Nur linux-4.1.3/include/video/mxc_edid.h linux-xbian-imx6/include/video/mxc_edid.h
+--- linux-4.1.3/include/video/mxc_edid.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/include/video/mxc_edid.h 2015-07-27 23:13:09.981369897 +0200
+@@ -0,0 +1,108 @@
++/*
++ * Copyright 2009-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*!
++ * @defgroup Framebuffer Framebuffer Driver for SDC and ADC.
++ */
++
++/*!
++ * @file mxc_edid.h
++ *
++ * @brief MXC EDID tools
++ *
++ * @ingroup Framebuffer
++ */
++
++#ifndef MXC_EDID_H
++#define MXC_EDID_H
++
++#include <linux/fb.h>
++
++enum cea_audio_coding_types {
++ AUDIO_CODING_TYPE_REF_STREAM_HEADER = 0,
++ AUDIO_CODING_TYPE_LPCM = 1,
++ AUDIO_CODING_TYPE_AC3 = 2,
++ AUDIO_CODING_TYPE_MPEG1 = 3,
++ AUDIO_CODING_TYPE_MP3 = 4,
++ AUDIO_CODING_TYPE_MPEG2 = 5,
++ AUDIO_CODING_TYPE_AACLC = 6,
++ AUDIO_CODING_TYPE_DTS = 7,
++ AUDIO_CODING_TYPE_ATRAC = 8,
++ AUDIO_CODING_TYPE_SACD = 9,
++ AUDIO_CODING_TYPE_EAC3 = 10,
++ AUDIO_CODING_TYPE_DTS_HD = 11,
++ AUDIO_CODING_TYPE_MLP = 12,
++ AUDIO_CODING_TYPE_DST = 13,
++ AUDIO_CODING_TYPE_WMAPRO = 14,
++ AUDIO_CODING_TYPE_RESERVED = 15,
++};
++
++struct mxc_hdmi_3d_format {
++ unsigned char vic_order_2d;
++ unsigned char struct_3d;
++ unsigned char detail_3d;
++ unsigned char reserved;
++};
++
++struct mxc_edid_cfg {
++ bool cea_underscan;
++ bool cea_basicaudio;
++ bool cea_ycbcr444;
++ bool cea_ycbcr422;
++ bool hdmi_cap;
++
++ /*VSD*/
++ bool vsd_support_ai;
++ bool vsd_dc_48bit;
++ bool vsd_dc_36bit;
++ bool vsd_dc_30bit;
++ bool vsd_dc_y444;
++ bool vsd_dvi_dual;
++
++ bool vsd_cnc0;
++ bool vsd_cnc1;
++ bool vsd_cnc2;
++ bool vsd_cnc3;
++
++ u8 vsd_video_latency;
++ u8 vsd_audio_latency;
++ u8 vsd_I_video_latency;
++ u8 vsd_I_audio_latency;
++
++ u8 physical_address[4];
++ u8 hdmi_vic[64];
++ struct mxc_hdmi_3d_format hdmi_3d_format[64];
++ u16 hdmi_3d_mask_all;
++ u16 hdmi_3d_struct_all;
++ unsigned char hdmi_3d_present;
++ unsigned char hdmi_3d_len;
++ unsigned char hdmi_3d_multi_present;
++ u32 vsd_max_tmdsclk_rate;
++
++ u8 max_channels;
++ u8 sample_sizes;
++ u8 sample_rates;
++ u8 speaker_alloc;
++};
++
++int mxc_edid_var_to_vic(struct fb_var_screeninfo *var);
++int mxc_edid_mode_to_vic(const struct fb_videomode *mode, u32 mode_mask);
++int mxc_edid_read(struct i2c_adapter *adp, unsigned short addr,
++ unsigned char *edid, struct mxc_edid_cfg *cfg, struct fb_info *fbi);
++int mxc_edid_parse_ext_blk(unsigned char *edid, struct mxc_edid_cfg *cfg,
++ struct fb_monspecs *specs);
++const struct fb_videomode *mxc_fb_find_nearest_mode(const struct fb_videomode *mode,
++ struct list_head *head);
++int mxc_edid_fb_mode_is_equal(bool use_aspect, const struct fb_videomode *mode1,
++ const struct fb_videomode *mode2, u32 mode_mask);
++#endif
+diff -Nur linux-4.1.3/include/video/mxc_hdmi.h linux-xbian-imx6/include/video/mxc_hdmi.h
+--- linux-4.1.3/include/video/mxc_hdmi.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/include/video/mxc_hdmi.h 2015-07-27 23:13:09.981369897 +0200
+@@ -0,0 +1,1027 @@
++/*
++ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
++ */
++
++/*
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++#ifndef __MXC_HDMI_H__
++#define __MXC_HDMI_H__
++
++/*
++ * Hdmi controller registers
++ */
++
++/* Identification Registers */
++#define HDMI_DESIGN_ID 0x0000
++#define HDMI_REVISION_ID 0x0001
++#define HDMI_PRODUCT_ID0 0x0002
++#define HDMI_PRODUCT_ID1 0x0003
++#define HDMI_CONFIG0_ID 0x0004
++#define HDMI_CONFIG1_ID 0x0005
++#define HDMI_CONFIG2_ID 0x0006
++#define HDMI_CONFIG3_ID 0x0007
++
++/* Interrupt Registers */
++#define HDMI_IH_FC_STAT0 0x0100
++#define HDMI_IH_FC_STAT1 0x0101
++#define HDMI_IH_FC_STAT2 0x0102
++#define HDMI_IH_AS_STAT0 0x0103
++#define HDMI_IH_PHY_STAT0 0x0104
++#define HDMI_IH_I2CM_STAT0 0x0105
++#define HDMI_IH_CEC_STAT0 0x0106
++#define HDMI_IH_VP_STAT0 0x0107
++#define HDMI_IH_I2CMPHY_STAT0 0x0108
++#define HDMI_IH_AHBDMAAUD_STAT0 0x0109
++
++#define HDMI_IH_MUTE_FC_STAT0 0x0180
++#define HDMI_IH_MUTE_FC_STAT1 0x0181
++#define HDMI_IH_MUTE_FC_STAT2 0x0182
++#define HDMI_IH_MUTE_AS_STAT0 0x0183
++#define HDMI_IH_MUTE_PHY_STAT0 0x0184
++#define HDMI_IH_MUTE_I2CM_STAT0 0x0185
++#define HDMI_IH_MUTE_CEC_STAT0 0x0186
++#define HDMI_IH_MUTE_VP_STAT0 0x0187
++#define HDMI_IH_MUTE_I2CMPHY_STAT0 0x0188
++#define HDMI_IH_MUTE_AHBDMAAUD_STAT0 0x0189
++#define HDMI_IH_MUTE 0x01FF
++
++/* Video Sample Registers */
++#define HDMI_TX_INVID0 0x0200
++#define HDMI_TX_INSTUFFING 0x0201
++#define HDMI_TX_GYDATA0 0x0202
++#define HDMI_TX_GYDATA1 0x0203
++#define HDMI_TX_RCRDATA0 0x0204
++#define HDMI_TX_RCRDATA1 0x0205
++#define HDMI_TX_BCBDATA0 0x0206
++#define HDMI_TX_BCBDATA1 0x0207
++
++/* Video Packetizer Registers */
++#define HDMI_VP_STATUS 0x0800
++#define HDMI_VP_PR_CD 0x0801
++#define HDMI_VP_STUFF 0x0802
++#define HDMI_VP_REMAP 0x0803
++#define HDMI_VP_CONF 0x0804
++#define HDMI_VP_STAT 0x0805
++#define HDMI_VP_INT 0x0806
++#define HDMI_VP_MASK 0x0807
++#define HDMI_VP_POL 0x0808
++
++/* Frame Composer Registers */
++#define HDMI_FC_INVIDCONF 0x1000
++#define HDMI_FC_INHACTV0 0x1001
++#define HDMI_FC_INHACTV1 0x1002
++#define HDMI_FC_INHBLANK0 0x1003
++#define HDMI_FC_INHBLANK1 0x1004
++#define HDMI_FC_INVACTV0 0x1005
++#define HDMI_FC_INVACTV1 0x1006
++#define HDMI_FC_INVBLANK 0x1007
++#define HDMI_FC_HSYNCINDELAY0 0x1008
++#define HDMI_FC_HSYNCINDELAY1 0x1009
++#define HDMI_FC_HSYNCINWIDTH0 0x100A
++#define HDMI_FC_HSYNCINWIDTH1 0x100B
++#define HDMI_FC_VSYNCINDELAY 0x100C
++#define HDMI_FC_VSYNCINWIDTH 0x100D
++#define HDMI_FC_INFREQ0 0x100E
++#define HDMI_FC_INFREQ1 0x100F
++#define HDMI_FC_INFREQ2 0x1010
++#define HDMI_FC_CTRLDUR 0x1011
++#define HDMI_FC_EXCTRLDUR 0x1012
++#define HDMI_FC_EXCTRLSPAC 0x1013
++#define HDMI_FC_CH0PREAM 0x1014
++#define HDMI_FC_CH1PREAM 0x1015
++#define HDMI_FC_CH2PREAM 0x1016
++#define HDMI_FC_AVICONF3 0x1017
++#define HDMI_FC_GCP 0x1018
++#define HDMI_FC_AVICONF0 0x1019
++#define HDMI_FC_AVICONF1 0x101A
++#define HDMI_FC_AVICONF2 0x101B
++#define HDMI_FC_AVIVID 0x101C
++#define HDMI_FC_AVIETB0 0x101D
++#define HDMI_FC_AVIETB1 0x101E
++#define HDMI_FC_AVISBB0 0x101F
++#define HDMI_FC_AVISBB1 0x1020
++#define HDMI_FC_AVIELB0 0x1021
++#define HDMI_FC_AVIELB1 0x1022
++#define HDMI_FC_AVISRB0 0x1023
++#define HDMI_FC_AVISRB1 0x1024
++#define HDMI_FC_AUDICONF0 0x1025
++#define HDMI_FC_AUDICONF1 0x1026
++#define HDMI_FC_AUDICONF2 0x1027
++#define HDMI_FC_AUDICONF3 0x1028
++#define HDMI_FC_VSDIEEEID0 0x1029
++#define HDMI_FC_VSDSIZE 0x102A
++#define HDMI_FC_VSDIEEEID1 0x1030
++#define HDMI_FC_VSDIEEEID2 0x1031
++#define HDMI_FC_VSDPAYLOAD0 0x1032
++#define HDMI_FC_VSDPAYLOAD1 0x1033
++#define HDMI_FC_VSDPAYLOAD2 0x1034
++#define HDMI_FC_VSDPAYLOAD3 0x1035
++#define HDMI_FC_VSDPAYLOAD4 0x1036
++#define HDMI_FC_VSDPAYLOAD5 0x1037
++#define HDMI_FC_VSDPAYLOAD6 0x1038
++#define HDMI_FC_VSDPAYLOAD7 0x1039
++#define HDMI_FC_VSDPAYLOAD8 0x103A
++#define HDMI_FC_VSDPAYLOAD9 0x103B
++#define HDMI_FC_VSDPAYLOAD10 0x103C
++#define HDMI_FC_VSDPAYLOAD11 0x103D
++#define HDMI_FC_VSDPAYLOAD12 0x103E
++#define HDMI_FC_VSDPAYLOAD13 0x103F
++#define HDMI_FC_VSDPAYLOAD14 0x1040
++#define HDMI_FC_VSDPAYLOAD15 0x1041
++#define HDMI_FC_VSDPAYLOAD16 0x1042
++#define HDMI_FC_VSDPAYLOAD17 0x1043
++#define HDMI_FC_VSDPAYLOAD18 0x1044
++#define HDMI_FC_VSDPAYLOAD19 0x1045
++#define HDMI_FC_VSDPAYLOAD20 0x1046
++#define HDMI_FC_VSDPAYLOAD21 0x1047
++#define HDMI_FC_VSDPAYLOAD22 0x1048
++#define HDMI_FC_VSDPAYLOAD23 0x1049
++#define HDMI_FC_SPDVENDORNAME0 0x104A
++#define HDMI_FC_SPDVENDORNAME1 0x104B
++#define HDMI_FC_SPDVENDORNAME2 0x104C
++#define HDMI_FC_SPDVENDORNAME3 0x104D
++#define HDMI_FC_SPDVENDORNAME4 0x104E
++#define HDMI_FC_SPDVENDORNAME5 0x104F
++#define HDMI_FC_SPDVENDORNAME6 0x1050
++#define HDMI_FC_SPDVENDORNAME7 0x1051
++#define HDMI_FC_SDPPRODUCTNAME0 0x1052
++#define HDMI_FC_SDPPRODUCTNAME1 0x1053
++#define HDMI_FC_SDPPRODUCTNAME2 0x1054
++#define HDMI_FC_SDPPRODUCTNAME3 0x1055
++#define HDMI_FC_SDPPRODUCTNAME4 0x1056
++#define HDMI_FC_SDPPRODUCTNAME5 0x1057
++#define HDMI_FC_SDPPRODUCTNAME6 0x1058
++#define HDMI_FC_SDPPRODUCTNAME7 0x1059
++#define HDMI_FC_SDPPRODUCTNAME8 0x105A
++#define HDMI_FC_SDPPRODUCTNAME9 0x105B
++#define HDMI_FC_SDPPRODUCTNAME10 0x105C
++#define HDMI_FC_SDPPRODUCTNAME11 0x105D
++#define HDMI_FC_SDPPRODUCTNAME12 0x105E
++#define HDMI_FC_SDPPRODUCTNAME13 0x105F
++#define HDMI_FC_SDPPRODUCTNAME14 0x1060
++#define HDMI_FC_SPDPRODUCTNAME15 0x1061
++#define HDMI_FC_SPDDEVICEINF 0x1062
++#define HDMI_FC_AUDSCONF 0x1063
++#define HDMI_FC_AUDSSTAT 0x1064
++#define HDMI_FC_DATACH0FILL 0x1070
++#define HDMI_FC_DATACH1FILL 0x1071
++#define HDMI_FC_DATACH2FILL 0x1072
++#define HDMI_FC_CTRLQHIGH 0x1073
++#define HDMI_FC_CTRLQLOW 0x1074
++#define HDMI_FC_ACP0 0x1075
++#define HDMI_FC_ACP28 0x1076
++#define HDMI_FC_ACP27 0x1077
++#define HDMI_FC_ACP26 0x1078
++#define HDMI_FC_ACP25 0x1079
++#define HDMI_FC_ACP24 0x107A
++#define HDMI_FC_ACP23 0x107B
++#define HDMI_FC_ACP22 0x107C
++#define HDMI_FC_ACP21 0x107D
++#define HDMI_FC_ACP20 0x107E
++#define HDMI_FC_ACP19 0x107F
++#define HDMI_FC_ACP18 0x1080
++#define HDMI_FC_ACP17 0x1081
++#define HDMI_FC_ACP16 0x1082
++#define HDMI_FC_ACP15 0x1083
++#define HDMI_FC_ACP14 0x1084
++#define HDMI_FC_ACP13 0x1085
++#define HDMI_FC_ACP12 0x1086
++#define HDMI_FC_ACP11 0x1087
++#define HDMI_FC_ACP10 0x1088
++#define HDMI_FC_ACP9 0x1089
++#define HDMI_FC_ACP8 0x108A
++#define HDMI_FC_ACP7 0x108B
++#define HDMI_FC_ACP6 0x108C
++#define HDMI_FC_ACP5 0x108D
++#define HDMI_FC_ACP4 0x108E
++#define HDMI_FC_ACP3 0x108F
++#define HDMI_FC_ACP2 0x1090
++#define HDMI_FC_ACP1 0x1091
++#define HDMI_FC_ISCR1_0 0x1092
++#define HDMI_FC_ISCR1_16 0x1093
++#define HDMI_FC_ISCR1_15 0x1094
++#define HDMI_FC_ISCR1_14 0x1095
++#define HDMI_FC_ISCR1_13 0x1096
++#define HDMI_FC_ISCR1_12 0x1097
++#define HDMI_FC_ISCR1_11 0x1098
++#define HDMI_FC_ISCR1_10 0x1099
++#define HDMI_FC_ISCR1_9 0x109A
++#define HDMI_FC_ISCR1_8 0x109B
++#define HDMI_FC_ISCR1_7 0x109C
++#define HDMI_FC_ISCR1_6 0x109D
++#define HDMI_FC_ISCR1_5 0x109E
++#define HDMI_FC_ISCR1_4 0x109F
++#define HDMI_FC_ISCR1_3 0x10A0
++#define HDMI_FC_ISCR1_2 0x10A1
++#define HDMI_FC_ISCR1_1 0x10A2
++#define HDMI_FC_ISCR2_15 0x10A3
++#define HDMI_FC_ISCR2_14 0x10A4
++#define HDMI_FC_ISCR2_13 0x10A5
++#define HDMI_FC_ISCR2_12 0x10A6
++#define HDMI_FC_ISCR2_11 0x10A7
++#define HDMI_FC_ISCR2_10 0x10A8
++#define HDMI_FC_ISCR2_9 0x10A9
++#define HDMI_FC_ISCR2_8 0x10AA
++#define HDMI_FC_ISCR2_7 0x10AB
++#define HDMI_FC_ISCR2_6 0x10AC
++#define HDMI_FC_ISCR2_5 0x10AD
++#define HDMI_FC_ISCR2_4 0x10AE
++#define HDMI_FC_ISCR2_3 0x10AF
++#define HDMI_FC_ISCR2_2 0x10B0
++#define HDMI_FC_ISCR2_1 0x10B1
++#define HDMI_FC_ISCR2_0 0x10B2
++#define HDMI_FC_DATAUTO0 0x10B3
++#define HDMI_FC_DATAUTO1 0x10B4
++#define HDMI_FC_DATAUTO2 0x10B5
++#define HDMI_FC_DATMAN 0x10B6
++#define HDMI_FC_DATAUTO3 0x10B7
++#define HDMI_FC_RDRB0 0x10B8
++#define HDMI_FC_RDRB1 0x10B9
++#define HDMI_FC_RDRB2 0x10BA
++#define HDMI_FC_RDRB3 0x10BB
++#define HDMI_FC_RDRB4 0x10BC
++#define HDMI_FC_RDRB5 0x10BD
++#define HDMI_FC_RDRB6 0x10BE
++#define HDMI_FC_RDRB7 0x10BF
++#define HDMI_FC_STAT0 0x10D0
++#define HDMI_FC_INT0 0x10D1
++#define HDMI_FC_MASK0 0x10D2
++#define HDMI_FC_POL0 0x10D3
++#define HDMI_FC_STAT1 0x10D4
++#define HDMI_FC_INT1 0x10D5
++#define HDMI_FC_MASK1 0x10D6
++#define HDMI_FC_POL1 0x10D7
++#define HDMI_FC_STAT2 0x10D8
++#define HDMI_FC_INT2 0x10D9
++#define HDMI_FC_MASK2 0x10DA
++#define HDMI_FC_POL2 0x10DB
++#define HDMI_FC_PRCONF 0x10E0
++
++#define HDMI_FC_GMD_STAT 0x1100
++#define HDMI_FC_GMD_EN 0x1101
++#define HDMI_FC_GMD_UP 0x1102
++#define HDMI_FC_GMD_CONF 0x1103
++#define HDMI_FC_GMD_HB 0x1104
++#define HDMI_FC_GMD_PB0 0x1105
++#define HDMI_FC_GMD_PB1 0x1106
++#define HDMI_FC_GMD_PB2 0x1107
++#define HDMI_FC_GMD_PB3 0x1108
++#define HDMI_FC_GMD_PB4 0x1109
++#define HDMI_FC_GMD_PB5 0x110A
++#define HDMI_FC_GMD_PB6 0x110B
++#define HDMI_FC_GMD_PB7 0x110C
++#define HDMI_FC_GMD_PB8 0x110D
++#define HDMI_FC_GMD_PB9 0x110E
++#define HDMI_FC_GMD_PB10 0x110F
++#define HDMI_FC_GMD_PB11 0x1110
++#define HDMI_FC_GMD_PB12 0x1111
++#define HDMI_FC_GMD_PB13 0x1112
++#define HDMI_FC_GMD_PB14 0x1113
++#define HDMI_FC_GMD_PB15 0x1114
++#define HDMI_FC_GMD_PB16 0x1115
++#define HDMI_FC_GMD_PB17 0x1116
++#define HDMI_FC_GMD_PB18 0x1117
++#define HDMI_FC_GMD_PB19 0x1118
++#define HDMI_FC_GMD_PB20 0x1119
++#define HDMI_FC_GMD_PB21 0x111A
++#define HDMI_FC_GMD_PB22 0x111B
++#define HDMI_FC_GMD_PB23 0x111C
++#define HDMI_FC_GMD_PB24 0x111D
++#define HDMI_FC_GMD_PB25 0x111E
++#define HDMI_FC_GMD_PB26 0x111F
++#define HDMI_FC_GMD_PB27 0x1120
++
++#define HDMI_FC_DBGFORCE 0x1200
++#define HDMI_FC_DBGAUD0CH0 0x1201
++#define HDMI_FC_DBGAUD1CH0 0x1202
++#define HDMI_FC_DBGAUD2CH0 0x1203
++#define HDMI_FC_DBGAUD0CH1 0x1204
++#define HDMI_FC_DBGAUD1CH1 0x1205
++#define HDMI_FC_DBGAUD2CH1 0x1206
++#define HDMI_FC_DBGAUD0CH2 0x1207
++#define HDMI_FC_DBGAUD1CH2 0x1208
++#define HDMI_FC_DBGAUD2CH2 0x1209
++#define HDMI_FC_DBGAUD0CH3 0x120A
++#define HDMI_FC_DBGAUD1CH3 0x120B
++#define HDMI_FC_DBGAUD2CH3 0x120C
++#define HDMI_FC_DBGAUD0CH4 0x120D
++#define HDMI_FC_DBGAUD1CH4 0x120E
++#define HDMI_FC_DBGAUD2CH4 0x120F
++#define HDMI_FC_DBGAUD0CH5 0x1210
++#define HDMI_FC_DBGAUD1CH5 0x1211
++#define HDMI_FC_DBGAUD2CH5 0x1212
++#define HDMI_FC_DBGAUD0CH6 0x1213
++#define HDMI_FC_DBGAUD1CH6 0x1214
++#define HDMI_FC_DBGAUD2CH6 0x1215
++#define HDMI_FC_DBGAUD0CH7 0x1216
++#define HDMI_FC_DBGAUD1CH7 0x1217
++#define HDMI_FC_DBGAUD2CH7 0x1218
++#define HDMI_FC_DBGTMDS0 0x1219
++#define HDMI_FC_DBGTMDS1 0x121A
++#define HDMI_FC_DBGTMDS2 0x121B
++
++/* HDMI Source PHY Registers */
++#define HDMI_PHY_CONF0 0x3000
++#define HDMI_PHY_TST0 0x3001
++#define HDMI_PHY_TST1 0x3002
++#define HDMI_PHY_TST2 0x3003
++#define HDMI_PHY_STAT0 0x3004
++#define HDMI_PHY_INT0 0x3005
++#define HDMI_PHY_MASK0 0x3006
++#define HDMI_PHY_POL0 0x3007
++
++/* HDMI Master PHY Registers */
++#define HDMI_PHY_I2CM_SLAVE_ADDR 0x3020
++#define HDMI_PHY_I2CM_ADDRESS_ADDR 0x3021
++#define HDMI_PHY_I2CM_DATAO_1_ADDR 0x3022
++#define HDMI_PHY_I2CM_DATAO_0_ADDR 0x3023
++#define HDMI_PHY_I2CM_DATAI_1_ADDR 0x3024
++#define HDMI_PHY_I2CM_DATAI_0_ADDR 0x3025
++#define HDMI_PHY_I2CM_OPERATION_ADDR 0x3026
++#define HDMI_PHY_I2CM_INT_ADDR 0x3027
++#define HDMI_PHY_I2CM_CTLINT_ADDR 0x3028
++#define HDMI_PHY_I2CM_DIV_ADDR 0x3029
++#define HDMI_PHY_I2CM_SOFTRSTZ_ADDR 0x302a
++#define HDMI_PHY_I2CM_SS_SCL_HCNT_1_ADDR 0x302b
++#define HDMI_PHY_I2CM_SS_SCL_HCNT_0_ADDR 0x302c
++#define HDMI_PHY_I2CM_SS_SCL_LCNT_1_ADDR 0x302d
++#define HDMI_PHY_I2CM_SS_SCL_LCNT_0_ADDR 0x302e
++#define HDMI_PHY_I2CM_FS_SCL_HCNT_1_ADDR 0x302f
++#define HDMI_PHY_I2CM_FS_SCL_HCNT_0_ADDR 0x3030
++#define HDMI_PHY_I2CM_FS_SCL_LCNT_1_ADDR 0x3031
++#define HDMI_PHY_I2CM_FS_SCL_LCNT_0_ADDR 0x3032
++
++/* Audio Sampler Registers */
++#define HDMI_AUD_CONF0 0x3100
++#define HDMI_AUD_CONF1 0x3101
++#define HDMI_AUD_INT 0x3102
++#define HDMI_AUD_CONF2 0x3103
++#define HDMI_AUD_N1 0x3200
++#define HDMI_AUD_N2 0x3201
++#define HDMI_AUD_N3 0x3202
++#define HDMI_AUD_CTS1 0x3203
++#define HDMI_AUD_CTS2 0x3204
++#define HDMI_AUD_CTS3 0x3205
++#define HDMI_AUD_INPUTCLKFS 0x3206
++#define HDMI_AUD_SPDIFINT 0x3302
++#define HDMI_AUD_CONF0_HBR 0x3400
++#define HDMI_AUD_HBR_STATUS 0x3401
++#define HDMI_AUD_HBR_INT 0x3402
++#define HDMI_AUD_HBR_POL 0x3403
++#define HDMI_AUD_HBR_MASK 0x3404
++
++/* Generic Parallel Audio Interface Registers */
++/* Not used as GPAUD interface is not enabled in hw */
++#define HDMI_GP_CONF0 0x3500
++#define HDMI_GP_CONF1 0x3501
++#define HDMI_GP_CONF2 0x3502
++#define HDMI_GP_STAT 0x3503
++#define HDMI_GP_INT 0x3504
++#define HDMI_GP_MASK 0x3505
++#define HDMI_GP_POL 0x3506
++
++/* Audio DMA Registers */
++#define HDMI_AHB_DMA_CONF0 0x3600
++#define HDMI_AHB_DMA_START 0x3601
++#define HDMI_AHB_DMA_STOP 0x3602
++#define HDMI_AHB_DMA_THRSLD 0x3603
++#define HDMI_AHB_DMA_STRADDR0 0x3604
++#define HDMI_AHB_DMA_STRADDR1 0x3605
++#define HDMI_AHB_DMA_STRADDR2 0x3606
++#define HDMI_AHB_DMA_STRADDR3 0x3607
++#define HDMI_AHB_DMA_STPADDR0 0x3608
++#define HDMI_AHB_DMA_STPADDR1 0x3609
++#define HDMI_AHB_DMA_STPADDR2 0x360a
++#define HDMI_AHB_DMA_STPADDR3 0x360b
++#define HDMI_AHB_DMA_BSTADDR0 0x360c
++#define HDMI_AHB_DMA_BSTADDR1 0x360d
++#define HDMI_AHB_DMA_BSTADDR2 0x360e
++#define HDMI_AHB_DMA_BSTADDR3 0x360f
++#define HDMI_AHB_DMA_MBLENGTH0 0x3610
++#define HDMI_AHB_DMA_MBLENGTH1 0x3611
++#define HDMI_AHB_DMA_STAT 0x3612
++#define HDMI_AHB_DMA_INT 0x3613
++#define HDMI_AHB_DMA_MASK 0x3614
++#define HDMI_AHB_DMA_POL 0x3615
++#define HDMI_AHB_DMA_CONF1 0x3616
++#define HDMI_AHB_DMA_BUFFSTAT 0x3617
++#define HDMI_AHB_DMA_BUFFINT 0x3618
++#define HDMI_AHB_DMA_BUFFMASK 0x3619
++#define HDMI_AHB_DMA_BUFFPOL 0x361a
++
++/* Main Controller Registers */
++#define HDMI_MC_SFRDIV 0x4000
++#define HDMI_MC_CLKDIS 0x4001
++#define HDMI_MC_SWRSTZ 0x4002
++#define HDMI_MC_OPCTRL 0x4003
++#define HDMI_MC_FLOWCTRL 0x4004
++#define HDMI_MC_PHYRSTZ 0x4005
++#define HDMI_MC_LOCKONCLOCK 0x4006
++#define HDMI_MC_HEACPHY_RST 0x4007
++
++/* Color Space Converter Registers */
++#define HDMI_CSC_CFG 0x4100
++#define HDMI_CSC_SCALE 0x4101
++#define HDMI_CSC_COEF_A1_MSB 0x4102
++#define HDMI_CSC_COEF_A1_LSB 0x4103
++#define HDMI_CSC_COEF_A2_MSB 0x4104
++#define HDMI_CSC_COEF_A2_LSB 0x4105
++#define HDMI_CSC_COEF_A3_MSB 0x4106
++#define HDMI_CSC_COEF_A3_LSB 0x4107
++#define HDMI_CSC_COEF_A4_MSB 0x4108
++#define HDMI_CSC_COEF_A4_LSB 0x4109
++#define HDMI_CSC_COEF_B1_MSB 0x410A
++#define HDMI_CSC_COEF_B1_LSB 0x410B
++#define HDMI_CSC_COEF_B2_MSB 0x410C
++#define HDMI_CSC_COEF_B2_LSB 0x410D
++#define HDMI_CSC_COEF_B3_MSB 0x410E
++#define HDMI_CSC_COEF_B3_LSB 0x410F
++#define HDMI_CSC_COEF_B4_MSB 0x4110
++#define HDMI_CSC_COEF_B4_LSB 0x4111
++#define HDMI_CSC_COEF_C1_MSB 0x4112
++#define HDMI_CSC_COEF_C1_LSB 0x4113
++#define HDMI_CSC_COEF_C2_MSB 0x4114
++#define HDMI_CSC_COEF_C2_LSB 0x4115
++#define HDMI_CSC_COEF_C3_MSB 0x4116
++#define HDMI_CSC_COEF_C3_LSB 0x4117
++#define HDMI_CSC_COEF_C4_MSB 0x4118
++#define HDMI_CSC_COEF_C4_LSB 0x4119
++
++/* HDCP Interrupt Registers */
++#define HDMI_A_APIINTCLR 0x5006
++#define HDMI_A_APIINTSTAT 0x5007
++#define HDMI_A_APIINTMSK 0x5008
++
++/* CEC Engine Registers */
++#define HDMI_CEC_CTRL 0x7D00
++#define HDMI_CEC_STAT 0x7D01
++#define HDMI_CEC_MASK 0x7D02
++#define HDMI_CEC_POLARITY 0x7D03
++#define HDMI_CEC_INT 0x7D04
++#define HDMI_CEC_ADDR_L 0x7D05
++#define HDMI_CEC_ADDR_H 0x7D06
++#define HDMI_CEC_TX_CNT 0x7D07
++#define HDMI_CEC_RX_CNT 0x7D08
++#define HDMI_CEC_TX_DATA0 0x7D10
++#define HDMI_CEC_TX_DATA1 0x7D11
++#define HDMI_CEC_TX_DATA2 0x7D12
++#define HDMI_CEC_TX_DATA3 0x7D13
++#define HDMI_CEC_TX_DATA4 0x7D14
++#define HDMI_CEC_TX_DATA5 0x7D15
++#define HDMI_CEC_TX_DATA6 0x7D16
++#define HDMI_CEC_TX_DATA7 0x7D17
++#define HDMI_CEC_TX_DATA8 0x7D18
++#define HDMI_CEC_TX_DATA9 0x7D19
++#define HDMI_CEC_TX_DATA10 0x7D1a
++#define HDMI_CEC_TX_DATA11 0x7D1b
++#define HDMI_CEC_TX_DATA12 0x7D1c
++#define HDMI_CEC_TX_DATA13 0x7D1d
++#define HDMI_CEC_TX_DATA14 0x7D1e
++#define HDMI_CEC_TX_DATA15 0x7D1f
++#define HDMI_CEC_RX_DATA0 0x7D20
++#define HDMI_CEC_RX_DATA1 0x7D21
++#define HDMI_CEC_RX_DATA2 0x7D22
++#define HDMI_CEC_RX_DATA3 0x7D23
++#define HDMI_CEC_RX_DATA4 0x7D24
++#define HDMI_CEC_RX_DATA5 0x7D25
++#define HDMI_CEC_RX_DATA6 0x7D26
++#define HDMI_CEC_RX_DATA7 0x7D27
++#define HDMI_CEC_RX_DATA8 0x7D28
++#define HDMI_CEC_RX_DATA9 0x7D29
++#define HDMI_CEC_RX_DATA10 0x7D2a
++#define HDMI_CEC_RX_DATA11 0x7D2b
++#define HDMI_CEC_RX_DATA12 0x7D2c
++#define HDMI_CEC_RX_DATA13 0x7D2d
++#define HDMI_CEC_RX_DATA14 0x7D2e
++#define HDMI_CEC_RX_DATA15 0x7D2f
++#define HDMI_CEC_LOCK 0x7D30
++#define HDMI_CEC_WKUPCTRL 0x7D31
++
++/* I2C Master Registers (E-DDC) */
++#define HDMI_I2CM_SLAVE 0x7E00
++#define HDMI_I2CM_ADDRESS 0x7E01
++#define HDMI_I2CM_DATAO 0x7E02
++#define HDMI_I2CM_DATAI 0x7E03
++#define HDMI_I2CM_OPERATION 0x7E04
++#define HDMI_I2CM_INT 0x7E05
++#define HDMI_I2CM_CTLINT 0x7E06
++#define HDMI_I2CM_DIV 0x7E07
++#define HDMI_I2CM_SEGADDR 0x7E08
++#define HDMI_I2CM_SOFTRSTZ 0x7E09
++#define HDMI_I2CM_SEGPTR 0x7E0A
++#define HDMI_I2CM_SS_SCL_HCNT_1_ADDR 0x7E0B
++#define HDMI_I2CM_SS_SCL_HCNT_0_ADDR 0x7E0C
++#define HDMI_I2CM_SS_SCL_LCNT_1_ADDR 0x7E0D
++#define HDMI_I2CM_SS_SCL_LCNT_0_ADDR 0x7E0E
++#define HDMI_I2CM_FS_SCL_HCNT_1_ADDR 0x7E0F
++#define HDMI_I2CM_FS_SCL_HCNT_0_ADDR 0x7E10
++#define HDMI_I2CM_FS_SCL_LCNT_1_ADDR 0x7E11
++#define HDMI_I2CM_FS_SCL_LCNT_0_ADDR 0x7E12
++
++/* Random Number Generator Registers (RNG) */
++#define HDMI_RNG_BASE 0x8000
++
++
++/*
++ * Register field definitions
++ */
++enum {
++/* IH_FC_INT2 field values */
++ HDMI_IH_FC_INT2_OVERFLOW_MASK = 0x03,
++ HDMI_IH_FC_INT2_LOW_PRIORITY_OVERFLOW = 0x02,
++ HDMI_IH_FC_INT2_HIGH_PRIORITY_OVERFLOW = 0x01,
++
++/* IH_FC_STAT2 field values */
++ HDMI_IH_FC_STAT2_OVERFLOW_MASK = 0x03,
++ HDMI_IH_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02,
++ HDMI_IH_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01,
++
++/* IH_PHY_STAT0 field values */
++ HDMI_IH_PHY_STAT0_RX_SENSE3 = 0x20,
++ HDMI_IH_PHY_STAT0_RX_SENSE2 = 0x10,
++ HDMI_IH_PHY_STAT0_RX_SENSE1 = 0x8,
++ HDMI_IH_PHY_STAT0_RX_SENSE0 = 0x4,
++ HDMI_IH_PHY_STAT0_TX_PHY_LOCK = 0x2,
++ HDMI_IH_PHY_STAT0_HPD = 0x1,
++
++/* IH_CEC_STAT0 field values */
++ HDMI_IH_CEC_STAT0_WAKEUP = 0x40,
++ HDMI_IH_CEC_STAT0_ERROR_FOLL = 0x20,
++ HDMI_IH_CEC_STAT0_ERROR_INIT = 0x10,
++ HDMI_IH_CEC_STAT0_ARB_LOST = 0x8,
++ HDMI_IH_CEC_STAT0_NACK = 0x4,
++ HDMI_IH_CEC_STAT0_EOM = 0x2,
++ HDMI_IH_CEC_STAT0_DONE = 0x1,
++
++
++/* IH_MUTE_I2CMPHY_STAT0 field values */
++ HDMI_IH_MUTE_I2CMPHY_STAT0_I2CMPHYDONE = 0x2,
++ HDMI_IH_MUTE_I2CMPHY_STAT0_I2CMPHYERROR = 0x1,
++
++/* IH_PHY_STAT0 field values */
++ HDMI_IH_MUTE_PHY_STAT0_RX_SENSE3 = 0x20,
++ HDMI_IH_MUTE_PHY_STAT0_RX_SENSE2 = 0x10,
++ HDMI_IH_MUTE_PHY_STAT0_RX_SENSE1 = 0x8,
++ HDMI_IH_MUTE_PHY_STAT0_RX_SENSE0 = 0x4,
++ HDMI_IH_MUTE_PHY_STAT0_TX_PHY_LOCK = 0x2,
++ HDMI_IH_MUTE_PHY_STAT0_HPD = 0x1,
++
++/* IH and IH_MUTE convenience macro RX_SENSE | HPD*/
++ HDMI_DVI_IH_STAT = 0x3D,
++
++
++/* IH_AHBDMAAUD_STAT0 field values */
++ HDMI_IH_AHBDMAAUD_STAT0_ERROR = 0x20,
++ HDMI_IH_AHBDMAAUD_STAT0_LOST = 0x10,
++ HDMI_IH_AHBDMAAUD_STAT0_RETRY = 0x08,
++ HDMI_IH_AHBDMAAUD_STAT0_DONE = 0x04,
++ HDMI_IH_AHBDMAAUD_STAT0_BUFFFULL = 0x02,
++ HDMI_IH_AHBDMAAUD_STAT0_BUFFEMPTY = 0x01,
++
++/* IH_MUTE_FC_STAT2 field values */
++ HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK = 0x03,
++ HDMI_IH_MUTE_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02,
++ HDMI_IH_MUTE_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01,
++
++/* IH_MUTE_AHBDMAAUD_STAT0 field values */
++ HDMI_IH_MUTE_AHBDMAAUD_STAT0_ERROR = 0x20,
++ HDMI_IH_MUTE_AHBDMAAUD_STAT0_LOST = 0x10,
++ HDMI_IH_MUTE_AHBDMAAUD_STAT0_RETRY = 0x08,
++ HDMI_IH_MUTE_AHBDMAAUD_STAT0_DONE = 0x04,
++ HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFFULL = 0x02,
++ HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFEMPTY = 0x01,
++
++/* IH_MUTE field values */
++ HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT = 0x2,
++ HDMI_IH_MUTE_MUTE_ALL_INTERRUPT = 0x1,
++
++/* TX_INVID0 field values */
++ HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_MASK = 0x80,
++ HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_ENABLE = 0x80,
++ HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE = 0x00,
++ HDMI_TX_INVID0_VIDEO_MAPPING_MASK = 0x1F,
++ HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET = 0,
++
++/* TX_INSTUFFING field values */
++ HDMI_TX_INSTUFFING_BDBDATA_STUFFING_MASK = 0x4,
++ HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE = 0x4,
++ HDMI_TX_INSTUFFING_BDBDATA_STUFFING_DISABLE = 0x0,
++ HDMI_TX_INSTUFFING_RCRDATA_STUFFING_MASK = 0x2,
++ HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE = 0x2,
++ HDMI_TX_INSTUFFING_RCRDATA_STUFFING_DISABLE = 0x0,
++ HDMI_TX_INSTUFFING_GYDATA_STUFFING_MASK = 0x1,
++ HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE = 0x1,
++ HDMI_TX_INSTUFFING_GYDATA_STUFFING_DISABLE = 0x0,
++
++/* VP_PR_CD field values */
++ HDMI_VP_PR_CD_COLOR_DEPTH_MASK = 0xF0,
++ HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET = 4,
++ HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK = 0x0F,
++ HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET = 0,
++
++/* VP_STUFF field values */
++ HDMI_VP_STUFF_IDEFAULT_PHASE_MASK = 0x20,
++ HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET = 5,
++ HDMI_VP_STUFF_IFIX_PP_TO_LAST_MASK = 0x10,
++ HDMI_VP_STUFF_IFIX_PP_TO_LAST_OFFSET = 4,
++ HDMI_VP_STUFF_ICX_GOTO_P0_ST_MASK = 0x8,
++ HDMI_VP_STUFF_ICX_GOTO_P0_ST_OFFSET = 3,
++ HDMI_VP_STUFF_YCC422_STUFFING_MASK = 0x4,
++ HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE = 0x4,
++ HDMI_VP_STUFF_YCC422_STUFFING_DIRECT_MODE = 0x0,
++ HDMI_VP_STUFF_PP_STUFFING_MASK = 0x2,
++ HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE = 0x2,
++ HDMI_VP_STUFF_PP_STUFFING_DIRECT_MODE = 0x0,
++ HDMI_VP_STUFF_PR_STUFFING_MASK = 0x1,
++ HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE = 0x1,
++ HDMI_VP_STUFF_PR_STUFFING_DIRECT_MODE = 0x0,
++
++/* VP_CONF field values */
++ HDMI_VP_CONF_BYPASS_EN_MASK = 0x40,
++ HDMI_VP_CONF_BYPASS_EN_ENABLE = 0x40,
++ HDMI_VP_CONF_BYPASS_EN_DISABLE = 0x00,
++ HDMI_VP_CONF_PP_EN_ENMASK = 0x20,
++ HDMI_VP_CONF_PP_EN_ENABLE = 0x20,
++ HDMI_VP_CONF_PP_EN_DISABLE = 0x00,
++ HDMI_VP_CONF_PR_EN_MASK = 0x10,
++ HDMI_VP_CONF_PR_EN_ENABLE = 0x10,
++ HDMI_VP_CONF_PR_EN_DISABLE = 0x00,
++ HDMI_VP_CONF_YCC422_EN_MASK = 0x8,
++ HDMI_VP_CONF_YCC422_EN_ENABLE = 0x8,
++ HDMI_VP_CONF_YCC422_EN_DISABLE = 0x0,
++ HDMI_VP_CONF_BYPASS_SELECT_MASK = 0x4,
++ HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER = 0x4,
++ HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER = 0x0,
++ HDMI_VP_CONF_OUTPUT_SELECTOR_MASK = 0x3,
++ HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS = 0x3,
++ HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422 = 0x1,
++ HDMI_VP_CONF_OUTPUT_SELECTOR_PP = 0x0,
++
++/* VP_REMAP field values */
++ HDMI_VP_REMAP_MASK = 0x3,
++ HDMI_VP_REMAP_YCC422_24bit = 0x2,
++ HDMI_VP_REMAP_YCC422_20bit = 0x1,
++ HDMI_VP_REMAP_YCC422_16bit = 0x0,
++
++/* FC_INVIDCONF field values */
++ HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_MASK = 0x40,
++ HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH = 0x40,
++ HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW = 0x00,
++ HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_MASK = 0x20,
++ HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH = 0x20,
++ HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW = 0x00,
++ HDMI_FC_INVIDCONF_DE_IN_POLARITY_MASK = 0x10,
++ HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH = 0x10,
++ HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW = 0x00,
++ HDMI_FC_INVIDCONF_DVI_MODEZ_MASK = 0x8,
++ HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE = 0x8,
++ HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE = 0x0,
++ HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_MASK = 0x2,
++ HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH = 0x2,
++ HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW = 0x0,
++ HDMI_FC_INVIDCONF_IN_I_P_MASK = 0x1,
++ HDMI_FC_INVIDCONF_IN_I_P_INTERLACED = 0x1,
++ HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE = 0x0,
++
++/* FC_AUDICONF0 field values */
++ HDMI_FC_AUDICONF0_CC_OFFSET = 4,
++ HDMI_FC_AUDICONF0_CC_MASK = 0x70,
++ HDMI_FC_AUDICONF0_CT_OFFSET = 0,
++ HDMI_FC_AUDICONF0_CT_MASK = 0xF,
++
++/* FC_AUDICONF1 field values */
++ HDMI_FC_AUDICONF1_SS_OFFSET = 3,
++ HDMI_FC_AUDICONF1_SS_MASK = 0x18,
++ HDMI_FC_AUDICONF1_SF_OFFSET = 0,
++ HDMI_FC_AUDICONF1_SF_MASK = 0x7,
++
++/* FC_AUDICONF3 field values */
++ HDMI_FC_AUDICONF3_LFEPBL_OFFSET = 5,
++ HDMI_FC_AUDICONF3_LFEPBL_MASK = 0x60,
++ HDMI_FC_AUDICONF3_DM_INH_OFFSET = 4,
++ HDMI_FC_AUDICONF3_DM_INH_MASK = 0x10,
++ HDMI_FC_AUDICONF3_LSV_OFFSET = 0,
++ HDMI_FC_AUDICONF3_LSV_MASK = 0xF,
++
++/* FC_AUDSCHNLS0 field values */
++ HDMI_FC_AUDSCHNLS0_CGMSA_OFFSET = 4,
++ HDMI_FC_AUDSCHNLS0_CGMSA_MASK = 0x30,
++ HDMI_FC_AUDSCHNLS0_COPYRIGHT_OFFSET = 0,
++ HDMI_FC_AUDSCHNLS0_COPYRIGHT_MASK = 0x01,
++
++/* FC_AUDSCHNLS3-6 field values */
++ HDMI_FC_AUDSCHNLS3_OIEC_CH0_OFFSET = 0,
++ HDMI_FC_AUDSCHNLS3_OIEC_CH0_MASK = 0x0f,
++ HDMI_FC_AUDSCHNLS3_OIEC_CH1_OFFSET = 4,
++ HDMI_FC_AUDSCHNLS3_OIEC_CH1_MASK = 0xf0,
++ HDMI_FC_AUDSCHNLS4_OIEC_CH2_OFFSET = 0,
++ HDMI_FC_AUDSCHNLS4_OIEC_CH2_MASK = 0x0f,
++ HDMI_FC_AUDSCHNLS4_OIEC_CH3_OFFSET = 4,
++ HDMI_FC_AUDSCHNLS4_OIEC_CH3_MASK = 0xf0,
++
++ HDMI_FC_AUDSCHNLS5_OIEC_CH0_OFFSET = 0,
++ HDMI_FC_AUDSCHNLS5_OIEC_CH0_MASK = 0x0f,
++ HDMI_FC_AUDSCHNLS5_OIEC_CH1_OFFSET = 4,
++ HDMI_FC_AUDSCHNLS5_OIEC_CH1_MASK = 0xf0,
++ HDMI_FC_AUDSCHNLS6_OIEC_CH2_OFFSET = 0,
++ HDMI_FC_AUDSCHNLS6_OIEC_CH2_MASK = 0x0f,
++ HDMI_FC_AUDSCHNLS6_OIEC_CH3_OFFSET = 4,
++ HDMI_FC_AUDSCHNLS6_OIEC_CH3_MASK = 0xf0,
++
++/* HDMI_FC_AUDSCHNLS7 field values */
++ HDMI_FC_AUDSCHNLS7_ACCURACY_OFFSET = 4,
++ HDMI_FC_AUDSCHNLS7_ACCURACY_MASK = 0x30,
++
++/* HDMI_FC_AUDSCHNLS8 field values */
++ HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_MASK = 0xf0,
++ HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_OFFSET = 4,
++ HDMI_FC_AUDSCHNLS8_WORDLEGNTH_MASK = 0x0f,
++ HDMI_FC_AUDSCHNLS8_WORDLEGNTH_OFFSET = 0,
++
++/* FC_AUDSCONF field values */
++ HDMI_FC_AUDSCONF_AUD_PACKET_SAMPFIT_MASK = 0xF0,
++ HDMI_FC_AUDSCONF_AUD_PACKET_SAMPFIT_OFFSET = 4,
++ HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK = 0x1,
++ HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_OFFSET = 0,
++ HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT1 = 0x1,
++ HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT0 = 0x0,
++
++/* FC_STAT2 field values */
++ HDMI_FC_STAT2_OVERFLOW_MASK = 0x03,
++ HDMI_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02,
++ HDMI_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01,
++
++/* FC_INT2 field values */
++ HDMI_FC_INT2_OVERFLOW_MASK = 0x03,
++ HDMI_FC_INT2_LOW_PRIORITY_OVERFLOW = 0x02,
++ HDMI_FC_INT2_HIGH_PRIORITY_OVERFLOW = 0x01,
++
++/* FC_MASK2 field values */
++ HDMI_FC_MASK2_OVERFLOW_MASK = 0x03,
++ HDMI_FC_MASK2_LOW_PRIORITY_OVERFLOW = 0x02,
++ HDMI_FC_MASK2_HIGH_PRIORITY_OVERFLOW = 0x01,
++
++/* FC_PRCONF field values */
++ HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK = 0xF0,
++ HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET = 4,
++ HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK = 0x0F,
++ HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET = 0,
++
++/* FC_AVICONF0-FC_AVICONF3 field values */
++ HDMI_FC_AVICONF0_PIX_FMT_MASK = 0x03,
++ HDMI_FC_AVICONF0_PIX_FMT_RGB = 0x00,
++ HDMI_FC_AVICONF0_PIX_FMT_YCBCR422 = 0x01,
++ HDMI_FC_AVICONF0_PIX_FMT_YCBCR444 = 0x02,
++ HDMI_FC_AVICONF0_ACTIVE_FMT_MASK = 0x40,
++ HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT = 0x40,
++ HDMI_FC_AVICONF0_ACTIVE_FMT_NO_INFO = 0x00,
++ HDMI_FC_AVICONF0_BAR_DATA_MASK = 0x0C,
++ HDMI_FC_AVICONF0_BAR_DATA_NO_DATA = 0x00,
++ HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR = 0x04,
++ HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR = 0x08,
++ HDMI_FC_AVICONF0_BAR_DATA_VERT_HORIZ_BAR = 0x0C,
++ HDMI_FC_AVICONF0_SCAN_INFO_MASK = 0x30,
++ HDMI_FC_AVICONF0_SCAN_INFO_OVERSCAN = 0x10,
++ HDMI_FC_AVICONF0_SCAN_INFO_UNDERSCAN = 0x20,
++ HDMI_FC_AVICONF0_SCAN_INFO_NODATA = 0x00,
++
++ HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_MASK = 0x0F,
++ HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_USE_CODED = 0x08,
++ HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3 = 0x09,
++ HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9 = 0x0A,
++ HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_14_9 = 0x0B,
++ HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_MASK = 0x30,
++ HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_NO_DATA = 0x00,
++ HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3 = 0x10,
++ HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9 = 0x20,
++ HDMI_FC_AVICONF1_COLORIMETRY_MASK = 0xC0,
++ HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA = 0x00,
++ HDMI_FC_AVICONF1_COLORIMETRY_SMPTE = 0x40,
++ HDMI_FC_AVICONF1_COLORIMETRY_ITUR = 0x80,
++ HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO = 0xC0,
++
++ HDMI_FC_AVICONF2_SCALING_MASK = 0x03,
++ HDMI_FC_AVICONF2_SCALING_NONE = 0x00,
++ HDMI_FC_AVICONF2_SCALING_HORIZ = 0x01,
++ HDMI_FC_AVICONF2_SCALING_VERT = 0x02,
++ HDMI_FC_AVICONF2_SCALING_HORIZ_VERT = 0x03,
++ HDMI_FC_AVICONF2_RGB_QUANT_MASK = 0x0C,
++ HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT = 0x00,
++ HDMI_FC_AVICONF2_RGB_QUANT_LIMITED_RANGE = 0x04,
++ HDMI_FC_AVICONF2_RGB_QUANT_FULL_RANGE = 0x08,
++ HDMI_FC_AVICONF2_EXT_COLORIMETRY_MASK = 0x70,
++ HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601 = 0x00,
++ HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709 = 0x10,
++ HDMI_FC_AVICONF2_EXT_COLORIMETRY_SYCC601 = 0x20,
++ HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_YCC601 = 0x30,
++ HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_RGB = 0x40,
++ HDMI_FC_AVICONF2_IT_CONTENT_MASK = 0x80,
++ HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA = 0x00,
++ HDMI_FC_AVICONF2_IT_CONTENT_VALID = 0x80,
++
++ HDMI_FC_AVICONF3_IT_CONTENT_TYPE_MASK = 0x03,
++ HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS = 0x00,
++ HDMI_FC_AVICONF3_IT_CONTENT_TYPE_PHOTO = 0x01,
++ HDMI_FC_AVICONF3_IT_CONTENT_TYPE_CINEMA = 0x02,
++ HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GAME = 0x03,
++ HDMI_FC_AVICONF3_QUANT_RANGE_MASK = 0x0C,
++ HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED = 0x00,
++ HDMI_FC_AVICONF3_QUANT_RANGE_FULL = 0x04,
++
++/* FC_DBGFORCE field values */
++ HDMI_FC_DBGFORCE_FORCEAUDIO = 0x10,
++ HDMI_FC_DBGFORCE_FORCEVIDEO = 0x1,
++
++/* PHY_CONF0 field values */
++ HDMI_PHY_CONF0_PDZ_MASK = 0x80,
++ HDMI_PHY_CONF0_PDZ_OFFSET = 7,
++ HDMI_PHY_CONF0_ENTMDS_MASK = 0x40,
++ HDMI_PHY_CONF0_ENTMDS_OFFSET = 6,
++ HDMI_PHY_CONF0_SPARECTRL = 0x20,
++ HDMI_PHY_CONF0_GEN2_PDDQ_MASK = 0x10,
++ HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET = 4,
++ HDMI_PHY_CONF0_GEN2_TXPWRON_MASK = 0x8,
++ HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET = 3,
++ HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE_MASK = 0x4,
++ HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE_OFFSET = 2,
++ HDMI_PHY_CONF0_SELDATAENPOL_MASK = 0x2,
++ HDMI_PHY_CONF0_SELDATAENPOL_OFFSET = 1,
++ HDMI_PHY_CONF0_SELDIPIF_MASK = 0x1,
++ HDMI_PHY_CONF0_SELDIPIF_OFFSET = 0,
++
++/* PHY_TST0 field values */
++ HDMI_PHY_TST0_TSTCLR_MASK = 0x20,
++ HDMI_PHY_TST0_TSTCLR_OFFSET = 5,
++ HDMI_PHY_TST0_TSTEN_MASK = 0x10,
++ HDMI_PHY_TST0_TSTEN_OFFSET = 4,
++ HDMI_PHY_TST0_TSTCLK_MASK = 0x1,
++ HDMI_PHY_TST0_TSTCLK_OFFSET = 0,
++
++/* PHY_STAT0 field values */
++ HDMI_PHY_RX_SENSE3 = 0x80,
++ HDMI_PHY_RX_SENSE2 = 0x40,
++ HDMI_PHY_RX_SENSE1 = 0x20,
++ HDMI_PHY_RX_SENSE0 = 0x10,
++ HDMI_PHY_HPD = 0x02,
++ HDMI_PHY_TX_PHY_LOCK = 0x01,
++
++/* HDMI STAT convenience RX_SENSE | HPD */
++ HDMI_DVI_STAT = 0xF2,
++
++/* PHY_I2CM_SLAVE_ADDR field values */
++ HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2 = 0x69,
++ HDMI_PHY_I2CM_SLAVE_ADDR_HEAC_PHY = 0x49,
++
++/* PHY_I2CM_OPERATION_ADDR field values */
++ HDMI_PHY_I2CM_OPERATION_ADDR_WRITE = 0x10,
++ HDMI_PHY_I2CM_OPERATION_ADDR_READ = 0x1,
++
++/* HDMI_PHY_I2CM_INT_ADDR */
++ HDMI_PHY_I2CM_INT_ADDR_DONE_POL = 0x08,
++ HDMI_PHY_I2CM_INT_ADDR_DONE_MASK = 0x04,
++
++/* HDMI_PHY_I2CM_CTLINT_ADDR */
++ HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL = 0x80,
++ HDMI_PHY_I2CM_CTLINT_ADDR_NAC_MASK = 0x40,
++ HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL = 0x08,
++ HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_MASK = 0x04,
++
++/* AUD_CTS3 field values */
++ HDMI_AUD_CTS3_N_SHIFT_OFFSET = 5,
++ HDMI_AUD_CTS3_N_SHIFT_MASK = 0xe0,
++ HDMI_AUD_CTS3_N_SHIFT_1 = 0,
++ HDMI_AUD_CTS3_N_SHIFT_16 = 0x20,
++ HDMI_AUD_CTS3_N_SHIFT_32 = 0x40,
++ HDMI_AUD_CTS3_N_SHIFT_64 = 0x60,
++ HDMI_AUD_CTS3_N_SHIFT_128 = 0x80,
++ HDMI_AUD_CTS3_N_SHIFT_256 = 0xa0,
++ /* note that the CTS3 MANUAL bit has been removed
++ from our part. Can't set it, will read as 0. */
++ HDMI_AUD_CTS3_CTS_MANUAL = 0x10,
++ HDMI_AUD_CTS3_AUDCTS19_16_MASK = 0x0f,
++
++/* AHB_DMA_CONF0 field values */
++ HDMI_AHB_DMA_CONF0_SW_FIFO_RST_OFFSET = 7,
++ HDMI_AHB_DMA_CONF0_SW_FIFO_RST_MASK = 0x80,
++ HDMI_AHB_DMA_CONF0_HBR_OFFSET = 4,
++ HDMI_AHB_DMA_CONF0_HBR_MASK = 0x10,
++ HDMI_AHB_DMA_CONF0_EN_HLOCK_OFFSET = 3,
++ HDMI_AHB_DMA_CONF0_EN_HLOCK_MASK = 0x08,
++ HDMI_AHB_DMA_CONF0_INCR_TYPE_OFFSET = 1,
++ HDMI_AHB_DMA_CONF0_INCR_TYPE_MASK = 0x06,
++ HDMI_AHB_DMA_CONF0_INCR4 = 0x0,
++ HDMI_AHB_DMA_CONF0_INCR8 = 0x2,
++ HDMI_AHB_DMA_CONF0_INCR16 = 0x4,
++ HDMI_AHB_DMA_CONF0_BURST_MODE = 0x1,
++
++/* HDMI_AHB_DMA_START field values */
++ HDMI_AHB_DMA_START_START_OFFSET = 0,
++ HDMI_AHB_DMA_START_START_MASK = 0x01,
++
++/* HDMI_AHB_DMA_STOP field values */
++ HDMI_AHB_DMA_STOP_STOP_OFFSET = 0,
++ HDMI_AHB_DMA_STOP_STOP_MASK = 0x01,
++
++/* AHB_DMA_STAT, AHB_DMA_INT, AHB_DMA_MASK, AHB_DMA_POL field values */
++ HDMI_AHB_DMA_DONE = 0x80,
++ HDMI_AHB_DMA_RETRY_SPLIT = 0x40,
++ HDMI_AHB_DMA_LOSTOWNERSHIP = 0x20,
++ HDMI_AHB_DMA_ERROR = 0x10,
++ HDMI_AHB_DMA_FIFO_THREMPTY = 0x04,
++ HDMI_AHB_DMA_FIFO_FULL = 0x02,
++ HDMI_AHB_DMA_FIFO_EMPTY = 0x01,
++
++/* AHB_DMA_BUFFSTAT, AHB_DMA_BUFFINT, AHB_DMA_BUFFMASK, AHB_DMA_BUFFPOL field values */
++ HDMI_AHB_DMA_BUFFSTAT_FULL = 0x02,
++ HDMI_AHB_DMA_BUFFSTAT_EMPTY = 0x01,
++
++/* MC_CLKDIS field values */
++ HDMI_MC_CLKDIS_HDCPCLK_DISABLE = 0x40,
++ HDMI_MC_CLKDIS_CECCLK_DISABLE = 0x20,
++ HDMI_MC_CLKDIS_CSCCLK_DISABLE = 0x10,
++ HDMI_MC_CLKDIS_AUDCLK_DISABLE = 0x8,
++ HDMI_MC_CLKDIS_PREPCLK_DISABLE = 0x4,
++ HDMI_MC_CLKDIS_TMDSCLK_DISABLE = 0x2,
++ HDMI_MC_CLKDIS_PIXELCLK_DISABLE = 0x1,
++
++/* MC_SWRSTZ field values */
++ HDMI_MC_SWRSTZ_TMDSSWRST_REQ = 0x02,
++
++/* MC_FLOWCTRL field values */
++ HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_MASK = 0x1,
++ HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH = 0x1,
++ HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS = 0x0,
++
++/* MC_PHYRSTZ field values */
++ HDMI_MC_PHYRSTZ_ASSERT = 0x0,
++ HDMI_MC_PHYRSTZ_DEASSERT = 0x1,
++
++/* MC_HEACPHY_RST field values */
++ HDMI_MC_HEACPHY_RST_ASSERT = 0x1,
++ HDMI_MC_HEACPHY_RST_DEASSERT = 0x0,
++
++/* CSC_CFG field values */
++ HDMI_CSC_CFG_INTMODE_MASK = 0x30,
++ HDMI_CSC_CFG_INTMODE_OFFSET = 4,
++ HDMI_CSC_CFG_INTMODE_DISABLE = 0x00,
++ HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1 = 0x10,
++ HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA2 = 0x20,
++ HDMI_CSC_CFG_DECMODE_MASK = 0x3,
++ HDMI_CSC_CFG_DECMODE_OFFSET = 0,
++ HDMI_CSC_CFG_DECMODE_DISABLE = 0x0,
++ HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA1 = 0x1,
++ HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA2 = 0x2,
++ HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3 = 0x3,
++
++/* CSC_SCALE field values */
++ HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK = 0xF0,
++ HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP = 0x00,
++ HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP = 0x50,
++ HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP = 0x60,
++ HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP = 0x70,
++ HDMI_CSC_SCALE_CSCSCALE_MASK = 0x03,
++
++/* I2CM_OPERATION field values */
++ HDMI_I2CM_OPERATION_WRITE = 0x10,
++ HDMI_I2CM_OPERATION_READ_EXT = 0x2,
++ HDMI_I2CM_OPERATION_READ = 0x1,
++
++/* HDMI_I2CM_INT */
++ HDMI_I2CM_INT_DONE_POL = 0x08,
++ HDMI_I2CM_INT_DONE_MASK = 0x04,
++
++/* HDMI_I2CM_CTLINT */
++ HDMI_I2CM_CTLINT_NAC_POL = 0x80,
++ HDMI_I2CM_CTLINT_NAC_MASK = 0x40,
++ HDMI_I2CM_CTLINT_ARBITRATION_POL = 0x08,
++ HDMI_I2CM_CTLINT_ARBITRATION_MASK = 0x04,
++
++};
++
++enum imx_hdmi_type {
++ IMX6DL_HDMI,
++ IMX6Q_HDMI,
++};
++
++/* IOCTL commands */
++#define HDMI_IOC_MAGIC 'H'
++
++#define HDMI_IOC_GET_RESOURCE _IO(HDMI_IOC_MAGIC, 0)
++#define HDMI_IOC_GET_CPU_TYPE _IO(HDMI_IOC_MAGIC, 1)
++
++
++#endif /* __MXC_HDMI_H__ */
+diff -Nur linux-4.1.3/sound/soc/codecs/hdmi.c linux-xbian-imx6/sound/soc/codecs/hdmi.c
+--- linux-4.1.3/sound/soc/codecs/hdmi.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/sound/soc/codecs/hdmi.c 2015-07-27 23:13:11.073473395 +0200
+@@ -47,7 +47,7 @@
+ SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000,
+ .formats = SNDRV_PCM_FMTBIT_S16_LE |
+ SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
+- .sig_bits = 24,
++// .sig_bits = 24,
+ },
+ .capture = {
+ .stream_name = "Capture",
+diff -Nur linux-4.1.3/sound/soc/codecs/sgtl5000.c linux-xbian-imx6/sound/soc/codecs/sgtl5000.c
+--- linux-4.1.3/sound/soc/codecs/sgtl5000.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/sound/soc/codecs/sgtl5000.c 2015-07-27 23:13:11.085430733 +0200
+@@ -16,7 +16,6 @@
+ #include <linux/pm.h>
+ #include <linux/i2c.h>
+ #include <linux/clk.h>
+-#include <linux/log2.h>
+ #include <linux/regmap.h>
+ #include <linux/regulator/driver.h>
+ #include <linux/regulator/machine.h>
+@@ -35,34 +34,25 @@
+ #define SGTL5000_DAP_REG_OFFSET 0x0100
+ #define SGTL5000_MAX_REG_OFFSET 0x013A
+
++
++int snd_soc_codec_set_cache_io(struct snd_soc_codec *codec,
++ int addr_bits, int data_bits,
++ enum snd_soc_control_type control);
++
+ /* default value of sgtl5000 registers */
+ static const struct reg_default sgtl5000_reg_defaults[] = {
+- { SGTL5000_CHIP_DIG_POWER, 0x0000 },
+ { SGTL5000_CHIP_CLK_CTRL, 0x0008 },
+ { SGTL5000_CHIP_I2S_CTRL, 0x0010 },
+ { SGTL5000_CHIP_SSS_CTRL, 0x0010 },
+- { SGTL5000_CHIP_ADCDAC_CTRL, 0x020c },
+ { SGTL5000_CHIP_DAC_VOL, 0x3c3c },
+ { SGTL5000_CHIP_PAD_STRENGTH, 0x015f },
+- { SGTL5000_CHIP_ANA_ADC_CTRL, 0x0000 },
+ { SGTL5000_CHIP_ANA_HP_CTRL, 0x1818 },
+ { SGTL5000_CHIP_ANA_CTRL, 0x0111 },
+- { SGTL5000_CHIP_LINREG_CTRL, 0x0000 },
+- { SGTL5000_CHIP_REF_CTRL, 0x0000 },
+- { SGTL5000_CHIP_MIC_CTRL, 0x0000 },
+- { SGTL5000_CHIP_LINE_OUT_CTRL, 0x0000 },
+ { SGTL5000_CHIP_LINE_OUT_VOL, 0x0404 },
+ { SGTL5000_CHIP_ANA_POWER, 0x7060 },
+ { SGTL5000_CHIP_PLL_CTRL, 0x5000 },
+- { SGTL5000_CHIP_CLK_TOP_CTRL, 0x0000 },
+- { SGTL5000_CHIP_ANA_STATUS, 0x0000 },
+- { SGTL5000_CHIP_SHORT_CTRL, 0x0000 },
+- { SGTL5000_CHIP_ANA_TEST2, 0x0000 },
+- { SGTL5000_DAP_CTRL, 0x0000 },
+- { SGTL5000_DAP_PEQ, 0x0000 },
+ { SGTL5000_DAP_BASS_ENHANCE, 0x0040 },
+ { SGTL5000_DAP_BASS_ENHANCE_CTRL, 0x051f },
+- { SGTL5000_DAP_AUDIO_EQ, 0x0000 },
+ { SGTL5000_DAP_SURROUND, 0x0040 },
+ { SGTL5000_DAP_EQ_BASS_BAND0, 0x002f },
+ { SGTL5000_DAP_EQ_BASS_BAND1, 0x002f },
+@@ -70,7 +60,6 @@
+ { SGTL5000_DAP_EQ_BASS_BAND3, 0x002f },
+ { SGTL5000_DAP_EQ_BASS_BAND4, 0x002f },
+ { SGTL5000_DAP_MAIN_CHAN, 0x8000 },
+- { SGTL5000_DAP_MIX_CHAN, 0x0000 },
+ { SGTL5000_DAP_AVC_CTRL, 0x0510 },
+ { SGTL5000_DAP_AVC_THRESHOLD, 0x1473 },
+ { SGTL5000_DAP_AVC_ATTACK, 0x0028 },
+@@ -122,13 +111,6 @@
+ bool enabled;
+ };
+
+-enum sgtl5000_micbias_resistor {
+- SGTL5000_MICBIAS_OFF = 0,
+- SGTL5000_MICBIAS_2K = 2,
+- SGTL5000_MICBIAS_4K = 4,
+- SGTL5000_MICBIAS_8K = 8,
+-};
+-
+ /* sgtl5000 private structure in codec */
+ struct sgtl5000_priv {
+ int sysclk; /* sysclk rate */
+@@ -216,9 +198,8 @@
+ "MIC_IN", "LINE_IN"
+ };
+
+-static SOC_ENUM_SINGLE_DECL(adc_enum,
+- SGTL5000_CHIP_ANA_CTRL, 2,
+- adc_mux_text);
++static const struct soc_enum adc_enum =
++SOC_ENUM_SINGLE(SGTL5000_CHIP_ANA_CTRL, 2, 2, adc_mux_text);
+
+ static const struct snd_kcontrol_new adc_mux =
+ SOC_DAPM_ENUM("Capture Mux", adc_enum);
+@@ -228,9 +209,8 @@
+ "DAC", "LINE_IN"
+ };
+
+-static SOC_ENUM_SINGLE_DECL(dac_enum,
+- SGTL5000_CHIP_ANA_CTRL, 6,
+- dac_mux_text);
++static const struct soc_enum dac_enum =
++SOC_ENUM_SINGLE(SGTL5000_CHIP_ANA_CTRL, 6, 2, dac_mux_text);
+
+ static const struct snd_kcontrol_new dac_mux =
+ SOC_DAPM_ENUM("Headphone Mux", dac_enum);
+@@ -325,7 +305,7 @@
+ static int dac_get_volsw(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+- struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
++ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+ int reg;
+ int l;
+ int r;
+@@ -378,7 +358,7 @@
+ static int dac_put_volsw(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+- struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
++ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+ int reg;
+ int l;
+ int r;
+@@ -485,21 +465,21 @@
+ /* setting i2s data format */
+ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+ case SND_SOC_DAIFMT_DSP_A:
+- i2sctl |= SGTL5000_I2S_MODE_PCM << SGTL5000_I2S_MODE_SHIFT;
++ i2sctl |= SGTL5000_I2S_MODE_PCM;
+ break;
+ case SND_SOC_DAIFMT_DSP_B:
+- i2sctl |= SGTL5000_I2S_MODE_PCM << SGTL5000_I2S_MODE_SHIFT;
++ i2sctl |= SGTL5000_I2S_MODE_PCM;
+ i2sctl |= SGTL5000_I2S_LRALIGN;
+ break;
+ case SND_SOC_DAIFMT_I2S:
+- i2sctl |= SGTL5000_I2S_MODE_I2S_LJ << SGTL5000_I2S_MODE_SHIFT;
++ i2sctl |= SGTL5000_I2S_MODE_I2S_LJ;
+ break;
+ case SND_SOC_DAIFMT_RIGHT_J:
+- i2sctl |= SGTL5000_I2S_MODE_RJ << SGTL5000_I2S_MODE_SHIFT;
++ i2sctl |= SGTL5000_I2S_MODE_RJ;
+ i2sctl |= SGTL5000_I2S_LRPOL;
+ break;
+ case SND_SOC_DAIFMT_LEFT_J:
+- i2sctl |= SGTL5000_I2S_MODE_I2S_LJ << SGTL5000_I2S_MODE_SHIFT;
++ i2sctl |= SGTL5000_I2S_MODE_I2S_LJ;
+ i2sctl |= SGTL5000_I2S_LRALIGN;
+ break;
+ default:
+@@ -544,16 +524,16 @@
+
+ /*
+ * set clock according to i2s frame clock,
+- * sgtl5000 provides 2 clock sources:
+- * 1. sys_mclk: sample freq can only be configured to
++ * sgtl5000 provide 2 clock sources.
++ * 1. sys_mclk. sample freq can only configure to
+ * 1/256, 1/384, 1/512 of sys_mclk.
+- * 2. pll: can derive any audio clocks.
++ * 2. pll. can derive any audio clocks.
+ *
+ * clock setting rules:
+- * 1. in slave mode, only sys_mclk can be used
+- * 2. as constraint by sys_mclk, sample freq should be set to 32 kHz, 44.1 kHz
+- * and above.
+- * 3. usage of sys_mclk is preferred over pll to save power.
++ * 1. in slave mode, only sys_mclk can use.
++ * 2. as constraint by sys_mclk, sample freq should
++ * set to 32k, 44.1k and above.
++ * 3. using sys_mclk prefer to pll to save power.
+ */
+ static int sgtl5000_set_clock(struct snd_soc_codec *codec, int frame_rate)
+ {
+@@ -563,8 +543,8 @@
+
+ /*
+ * sample freq should be divided by frame clock,
+- * if frame clock is lower than 44.1 kHz, sample freq should be set to
+- * 32 kHz or 44.1 kHz.
++ * if frame clock lower than 44.1khz, sample feq should set to
++ * 32khz or 44.1khz.
+ */
+ switch (frame_rate) {
+ case 8000:
+@@ -617,10 +597,9 @@
+
+ /*
+ * calculate the divider of mclk/sample_freq,
+- * factor of freq = 96 kHz can only be 256, since mclk is in the range
+- * of 8 MHz - 27 MHz
++ * factor of freq =96k can only be 256, since mclk in range (12m,27m)
+ */
+- switch (sgtl5000->sysclk / frame_rate) {
++ switch (sgtl5000->sysclk / sys_fs) {
+ case 256:
+ clk_ctl |= SGTL5000_MCLK_FREQ_256FS <<
+ SGTL5000_MCLK_FREQ_SHIFT;
+@@ -634,16 +613,13 @@
+ SGTL5000_MCLK_FREQ_SHIFT;
+ break;
+ default:
+- /* if mclk does not satisfy the divider, use pll */
++ /* if mclk not satisify the divider, use pll */
+ if (sgtl5000->master) {
+ clk_ctl |= SGTL5000_MCLK_FREQ_PLL <<
+ SGTL5000_MCLK_FREQ_SHIFT;
+ } else {
+ dev_err(codec->dev,
+ "PLL not supported in slave mode\n");
+- dev_err(codec->dev, "%d ratio is not supported. "
+- "SYS_MCLK needs to be 256, 384 or 512 * fs\n",
+- sgtl5000->sysclk / frame_rate);
+ return -EINVAL;
+ }
+ }
+@@ -742,25 +718,25 @@
+ return ret;
+
+ /* set i2s data format */
+- switch (params_width(params)) {
+- case 16:
++ switch (params_format(params)) {
++ case SNDRV_PCM_FORMAT_S16_LE:
+ if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J)
+ return -EINVAL;
+ i2s_ctl |= SGTL5000_I2S_DLEN_16 << SGTL5000_I2S_DLEN_SHIFT;
+ i2s_ctl |= SGTL5000_I2S_SCLKFREQ_32FS <<
+ SGTL5000_I2S_SCLKFREQ_SHIFT;
+ break;
+- case 20:
++ case SNDRV_PCM_FORMAT_S20_3LE:
+ i2s_ctl |= SGTL5000_I2S_DLEN_20 << SGTL5000_I2S_DLEN_SHIFT;
+ i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
+ SGTL5000_I2S_SCLKFREQ_SHIFT;
+ break;
+- case 24:
++ case SNDRV_PCM_FORMAT_S24_LE:
+ i2s_ctl |= SGTL5000_I2S_DLEN_24 << SGTL5000_I2S_DLEN_SHIFT;
+ i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
+ SGTL5000_I2S_SCLKFREQ_SHIFT;
+ break;
+- case 32:
++ case SNDRV_PCM_FORMAT_S32_LE:
+ if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J)
+ return -EINVAL;
+ i2s_ctl |= SGTL5000_I2S_DLEN_32 << SGTL5000_I2S_DLEN_SHIFT;
+@@ -791,7 +767,7 @@
+ struct ldo_regulator *ldo = rdev_get_drvdata(dev);
+ struct snd_soc_codec *codec = (struct snd_soc_codec *)ldo->codec_data;
+ int reg;
+-
++dev_info(codec->dev, "%s(): enabled %u\n", __func__, ldo->enabled);
+ if (ldo_regulator_is_enabled(dev))
+ return 0;
+
+@@ -810,7 +786,7 @@
+ SGTL5000_LINEREG_D_POWERUP,
+ SGTL5000_LINEREG_D_POWERUP);
+
+- /* when internal ldo is enabled, simple digital power can be disabled */
++ /* when internal ldo enabled, simple digital power can be disabled */
+ snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
+ SGTL5000_LINREG_SIMPLE_POWERUP,
+ 0);
+@@ -823,10 +799,16 @@
+ {
+ struct ldo_regulator *ldo = rdev_get_drvdata(dev);
+ struct snd_soc_codec *codec = (struct snd_soc_codec *)ldo->codec_data;
++dev_info(codec->dev, "%s(): enabled %u\n", __func__, ldo->enabled);
++
++ snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
++ SGTL5000_LINREG_SIMPLE_POWERUP,
++ SGTL5000_LINREG_SIMPLE_POWERUP);
+
+ snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
+ SGTL5000_LINEREG_D_POWERUP,
+ 0);
++dev_info(codec->dev, "%s: ANA_POWER = 0x%04x\n", __func__, snd_soc_read(codec, SGTL5000_CHIP_ANA_POWER));
+
+ /* clear voltage info */
+ snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL,
+@@ -861,8 +843,10 @@
+
+ ldo = kzalloc(sizeof(struct ldo_regulator), GFP_KERNEL);
+
+- if (!ldo)
++ if (!ldo) {
++ dev_err(codec->dev, "failed to allocate ldo_regulator\n");
+ return -ENOMEM;
++ }
+
+ ldo->desc.name = kstrdup(dev_name(codec->dev), GFP_KERNEL);
+ if (!ldo->desc.name) {
+@@ -882,6 +866,7 @@
+ config.dev = codec->dev;
+ config.driver_data = ldo;
+ config.init_data = init_data;
++ config.ena_gpio = -EINVAL;
+
+ ldo->dev = regulator_register(&ldo->desc, &config);
+ if (IS_ERR(ldo->dev)) {
+@@ -1091,10 +1076,90 @@
+ }
+ }
+
++#ifdef CONFIG_SUSPEND
++static int sgtl5000_suspend(struct snd_soc_codec *codec)
++{
++ sgtl5000_set_bias_level(codec, SND_SOC_BIAS_OFF);
++
++ return 0;
++}
++
++/*
++ * restore all sgtl5000 registers,
++ * since a big hole between dap and regular registers,
++ * we will restore them respectively.
++ */
++static int sgtl5000_restore_regs(struct snd_soc_codec *codec)
++{
++ u16 *cache = codec->reg_cache;
++ u16 reg;
++
++ /* restore regular registers */
++ for (reg = 0; reg <= SGTL5000_CHIP_SHORT_CTRL; reg += 2) {
++
++ /* These regs should restore in particular order */
++ if (reg == SGTL5000_CHIP_ANA_POWER ||
++ reg == SGTL5000_CHIP_CLK_CTRL ||
++ reg == SGTL5000_CHIP_LINREG_CTRL ||
++ reg == SGTL5000_CHIP_LINE_OUT_CTRL ||
++ reg == SGTL5000_CHIP_REF_CTRL)
++ continue;
++
++ snd_soc_write(codec, reg, cache[reg]);
++ }
++
++ /* restore dap registers */
++ for (reg = SGTL5000_DAP_REG_OFFSET; reg < SGTL5000_MAX_REG_OFFSET; reg += 2)
++ snd_soc_write(codec, reg, cache[reg]);
++
++ /*
++ * restore these regs according to the power setting sequence in
++ * sgtl5000_set_power_regs() and clock setting sequence in
++ * sgtl5000_set_clock().
++ *
++ * The order of restore is:
++ * 1. SGTL5000_CHIP_CLK_CTRL MCLK_FREQ bits (1:0) should be restore after
++ * SGTL5000_CHIP_ANA_POWER PLL bits set
++ * 2. SGTL5000_CHIP_LINREG_CTRL should be set before
++ * SGTL5000_CHIP_ANA_POWER LINREG_D restored
++ * 3. SGTL5000_CHIP_REF_CTRL controls Analog Ground Voltage,
++ * prefer to resotre it after SGTL5000_CHIP_ANA_POWER restored
++ */
++ snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL,
++ cache[SGTL5000_CHIP_LINREG_CTRL]);
++
++ snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER,
++ cache[SGTL5000_CHIP_ANA_POWER]);
++
++ snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL,
++ cache[SGTL5000_CHIP_CLK_CTRL]);
++
++ snd_soc_write(codec, SGTL5000_CHIP_REF_CTRL,
++ cache[SGTL5000_CHIP_REF_CTRL]);
++
++ snd_soc_write(codec, SGTL5000_CHIP_LINE_OUT_CTRL,
++ cache[SGTL5000_CHIP_LINE_OUT_CTRL]);
++ return 0;
++}
++
++static int sgtl5000_resume(struct snd_soc_codec *codec)
++{
++ /* Bring the codec back up to standby to enable regulators */
++ sgtl5000_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
++
++ /* Restore registers by cached in memory */
++ sgtl5000_restore_regs(codec);
++ return 0;
++}
++#else
++#define sgtl5000_suspend NULL
++#define sgtl5000_resume NULL
++#endif /* CONFIG_SUSPEND */
++
+ /*
+ * sgtl5000 has 3 internal power supplies:
+ * 1. VAG, normally set to vdda/2
+- * 2. charge pump, set to different value
++ * 2. chargepump, set to different value
+ * according to voltage of vdda and vddio
+ * 3. line out VAG, normally set to vddio/2
+ *
+@@ -1267,7 +1332,7 @@
+ return ret;
+ }
+
+- ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(sgtl5000->supplies),
++ ret = devm_regulator_bulk_get(codec->dev, ARRAY_SIZE(sgtl5000->supplies),
+ sgtl5000->supplies);
+ if (ret)
+ goto err_ldo_remove;
+@@ -1275,16 +1340,13 @@
+ ret = regulator_bulk_enable(ARRAY_SIZE(sgtl5000->supplies),
+ sgtl5000->supplies);
+ if (ret)
+- goto err_regulator_free;
++ goto err_ldo_remove;
+
+ /* wait for all power rails bring up */
+ udelay(10);
+
+ return 0;
+
+-err_regulator_free:
+- regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
+- sgtl5000->supplies);
+ err_ldo_remove:
+ if (!external_vddd)
+ ldo_regulator_remove(codec);
+@@ -1297,6 +1359,17 @@
+ int ret;
+ struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
+
++ /* setup i2c data ops */
++ codec->control_data = sgtl5000->regmap;
++ ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP);
++ if (ret < 0) {
++ dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
++ return ret;
++ }
++
++ if (!devres_open_group(codec->dev, NULL, GFP_KERNEL))
++ return -ENOMEM;
++
+ ret = sgtl5000_enable_regulators(codec);
+ if (ret)
+ return ret;
+@@ -1334,13 +1407,8 @@
+ SGTL5000_HP_ZCD_EN |
+ SGTL5000_ADC_ZCD_EN);
+
+- snd_soc_update_bits(codec, SGTL5000_CHIP_MIC_CTRL,
+- SGTL5000_BIAS_R_MASK,
+- sgtl5000->micbias_resistor << SGTL5000_BIAS_R_SHIFT);
++ snd_soc_write(codec, SGTL5000_CHIP_MIC_CTRL, 2);
+
+- snd_soc_update_bits(codec, SGTL5000_CHIP_MIC_CTRL,
+- SGTL5000_BIAS_R_MASK,
+- sgtl5000->micbias_voltage << SGTL5000_BIAS_R_SHIFT);
+ /*
+ * disable DAP
+ * TODO:
+@@ -1348,13 +1416,19 @@
+ */
+ snd_soc_write(codec, SGTL5000_DAP_CTRL, 0);
+
++ /* leading to standby state */
++ ret = sgtl5000_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
++ if (ret)
++ goto err;
++
+ return 0;
+
+ err:
+ regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
+ sgtl5000->supplies);
+- regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
+- sgtl5000->supplies);
++
++ devres_release_group(codec->dev, NULL);
++
+ ldo_regulator_remove(codec);
+
+ return ret;
+@@ -1364,10 +1438,13 @@
+ {
+ struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
+
++ sgtl5000_set_bias_level(codec, SND_SOC_BIAS_OFF);
++
+ regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
+ sgtl5000->supplies);
+- regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
+- sgtl5000->supplies);
++
++ devres_release_group(codec->dev, NULL);
++
+ ldo_regulator_remove(codec);
+
+ return 0;
+@@ -1376,8 +1453,9 @@
+ static struct snd_soc_codec_driver sgtl5000_driver = {
+ .probe = sgtl5000_probe,
+ .remove = sgtl5000_remove,
++ .suspend = sgtl5000_suspend,
++ .resume = sgtl5000_resume,
+ .set_bias_level = sgtl5000_set_bias_level,
+- .suspend_bias_off = true,
+ .controls = sgtl5000_snd_controls,
+ .num_controls = ARRAY_SIZE(sgtl5000_snd_controls),
+ .dapm_widgets = sgtl5000_dapm_widgets,
+@@ -1430,10 +1508,9 @@
+ {
+ struct sgtl5000_priv *sgtl5000;
+ int ret, reg, rev;
+- struct device_node *np = client->dev.of_node;
+- u32 value;
+
+- sgtl5000 = devm_kzalloc(&client->dev, sizeof(*sgtl5000), GFP_KERNEL);
++ sgtl5000 = devm_kzalloc(&client->dev, sizeof(struct sgtl5000_priv),
++ GFP_KERNEL);
+ if (!sgtl5000)
+ return -ENOMEM;
+
+@@ -1478,47 +1555,6 @@
+ dev_info(&client->dev, "sgtl5000 revision 0x%x\n", rev);
+ sgtl5000->revision = rev;
+
+- if (np) {
+- if (!of_property_read_u32(np,
+- "micbias-resistor-k-ohms", &value)) {
+- switch (value) {
+- case SGTL5000_MICBIAS_OFF:
+- sgtl5000->micbias_resistor = 0;
+- break;
+- case SGTL5000_MICBIAS_2K:
+- sgtl5000->micbias_resistor = 1;
+- break;
+- case SGTL5000_MICBIAS_4K:
+- sgtl5000->micbias_resistor = 2;
+- break;
+- case SGTL5000_MICBIAS_8K:
+- sgtl5000->micbias_resistor = 3;
+- break;
+- default:
+- sgtl5000->micbias_resistor = 2;
+- dev_err(&client->dev,
+- "Unsuitable MicBias resistor\n");
+- }
+- } else {
+- /* default is 4Kohms */
+- sgtl5000->micbias_resistor = 2;
+- }
+- if (!of_property_read_u32(np,
+- "micbias-voltage-m-volts", &value)) {
+- /* 1250mV => 0 */
+- /* steps of 250mV */
+- if ((value >= 1250) && (value <= 3000))
+- sgtl5000->micbias_voltage = (value / 250) - 5;
+- else {
+- sgtl5000->micbias_voltage = 0;
+- dev_err(&client->dev,
+- "Unsuitable MicBias resistor\n");
+- }
+- } else {
+- sgtl5000->micbias_voltage = 0;
+- }
+- }
+-
+ i2c_set_clientdata(client, sgtl5000);
+
+ /* Ensure sgtl5000 will start with sane register values */
+diff -Nur linux-4.1.3/sound/soc/fsl/fsl_asrc.h linux-xbian-imx6/sound/soc/fsl/fsl_asrc.h
+--- linux-4.1.3/sound/soc/fsl/fsl_asrc.h 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/sound/soc/fsl/fsl_asrc.h 2015-07-27 23:13:11.149203200 +0200
+@@ -326,7 +326,7 @@
+ OUTCLK_ASRCK1_CLK = 0x0f,
+ };
+
+-#define ASRC_CLK_MAX_NUM 16
++#define ASRC_CLK_MAX_NUM 1
+
+ enum asrc_word_width {
+ ASRC_WIDTH_24_BIT = 0,
+diff -Nur linux-4.1.3/sound/soc/fsl/fsl_esai.c linux-xbian-imx6/sound/soc/fsl/fsl_esai.c
+--- linux-4.1.3/sound/soc/fsl/fsl_esai.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/sound/soc/fsl/fsl_esai.c 2015-07-27 23:13:11.149203200 +0200
+@@ -839,7 +839,7 @@
+ return ret;
+ }
+
+- ret = imx_pcm_dma_init(pdev);
++ ret = imx_pcm_dma_init(pdev, IMX_ESAI_DMABUF_SIZE);
+ if (ret)
+ dev_err(&pdev->dev, "failed to init imx pcm dma: %d\n", ret);
+
+diff -Nur linux-4.1.3/sound/soc/fsl/fsl_hdmi.c linux-xbian-imx6/sound/soc/fsl/fsl_hdmi.c
+--- linux-4.1.3/sound/soc/fsl/fsl_hdmi.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/sound/soc/fsl/fsl_hdmi.c 2015-07-27 23:13:11.149203200 +0200
+@@ -0,0 +1,614 @@
++/*
++ * ALSA SoC HDMI Audio Layer for Freescale i.MX
++ *
++ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
++ *
++ * Some code from patch_hdmi.c
++ * Copyright (c) 2008-2010 Intel Corporation. All rights reserved.
++ * Copyright (c) 2006 ATI Technologies Inc.
++ * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
++ * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/dma-mapping.h>
++#include <linux/slab.h>
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/mfd/mxc-hdmi-core.h>
++#include <sound/pcm.h>
++#include <sound/soc.h>
++#include <sound/asoundef.h>
++
++#include <video/mxc_hdmi.h>
++
++#include "imx-hdmi.h"
++
++
++static struct mxc_edid_cfg edid_cfg;
++
++static u32 playback_rates[HDMI_MAX_RATES];
++static u32 playback_sample_size[HDMI_MAX_SAMPLE_SIZE];
++static u32 playback_channels[HDMI_MAX_CHANNEL_CONSTRAINTS];
++
++static struct snd_pcm_hw_constraint_list playback_constraint_rates;
++static struct snd_pcm_hw_constraint_list playback_constraint_bits;
++static struct snd_pcm_hw_constraint_list playback_constraint_channels;
++
++#ifdef DEBUG
++static void dumpregs(struct snd_soc_dai *dai)
++{
++ u32 n, cts;
++
++ cts = (hdmi_readb(HDMI_AUD_CTS3) << 16) |
++ (hdmi_readb(HDMI_AUD_CTS2) << 8) |
++ hdmi_readb(HDMI_AUD_CTS1);
++
++ n = (hdmi_readb(HDMI_AUD_N3) << 16) |
++ (hdmi_readb(HDMI_AUD_N2) << 8) |
++ hdmi_readb(HDMI_AUD_N1);
++
++ dev_dbg(dai->dev, "HDMI_PHY_CONF0 0x%02x\n",
++ hdmi_readb(HDMI_PHY_CONF0));
++ dev_dbg(dai->dev, "HDMI_MC_CLKDIS 0x%02x\n",
++ hdmi_readb(HDMI_MC_CLKDIS));
++ dev_dbg(dai->dev, "HDMI_AUD_N[1-3] 0x%06x (%d)\n",
++ n, n);
++ dev_dbg(dai->dev, "HDMI_AUD_CTS[1-3] 0x%06x (%d)\n",
++ cts, cts);
++ dev_dbg(dai->dev, "HDMI_FC_AUDSCONF 0x%02x\n",
++ hdmi_readb(HDMI_FC_AUDSCONF));
++}
++#else
++static void dumpregs(struct snd_soc_dai *dai) {}
++#endif
++
++enum cea_speaker_placement {
++ FL = (1 << 0), /* Front Left */
++ FC = (1 << 1), /* Front Center */
++ FR = (1 << 2), /* Front Right */
++ FLC = (1 << 3), /* Front Left Center */
++ FRC = (1 << 4), /* Front Right Center */
++ RL = (1 << 5), /* Rear Left */
++ RC = (1 << 6), /* Rear Center */
++ RR = (1 << 7), /* Rear Right */
++ RLC = (1 << 8), /* Rear Left Center */
++ RRC = (1 << 9), /* Rear Right Center */
++ LFE = (1 << 10), /* Low Frequency Effect */
++ FLW = (1 << 11), /* Front Left Wide */
++ FRW = (1 << 12), /* Front Right Wide */
++ FLH = (1 << 13), /* Front Left High */
++ FCH = (1 << 14), /* Front Center High */
++ FRH = (1 << 15), /* Front Right High */
++ TC = (1 << 16), /* Top Center */
++};
++
++/*
++ * EDID SA bits in the CEA Speaker Allocation data block
++ */
++static int edid_speaker_allocation_bits[] = {
++ [0] = FL | FR,
++ [1] = LFE,
++ [2] = FC,
++ [3] = RL | RR,
++ [4] = RC,
++ [5] = FLC | FRC,
++ [6] = RLC | RRC,
++ [7] = FLW | FRW,
++ [8] = FLH | FRH,
++ [9] = TC,
++ [10] = FCH,
++};
++
++struct cea_channel_speaker_allocation {
++ int ca_index;
++ int speakers[8];
++
++ /* Derived values, just for convenience */
++ int channels;
++ int spk_mask;
++};
++
++/*
++ * This is an ordered list!
++ *
++ * The preceding ones have better chances to be selected by
++ * hdmi_channel_allocation().
++ */
++static struct cea_channel_speaker_allocation channel_allocations[] = {
++ /* channel: 7 6 5 4 3 2 1 0 */
++ { .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL },},
++ /* 2.1 */
++ { .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL },},
++ /* Dolby Surround */
++ { .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL },}, /* Prefer FL/FR/RL/RR over FL/FR/LFE/FC */
++ { .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL },},
++ { .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL },},
++ { .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL },},
++ { .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL },},
++ { .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL },},
++ { .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL },},
++ { .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL },},
++ { .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL },},
++ /* surround51 */
++ { .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL },},
++ { .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL },},
++ { .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL },},
++ { .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL },},
++ /* 6.1 */
++ { .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL },},
++ { .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL },},
++ { .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL },},
++ { .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL },},
++ /* surround71 */
++ { .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL },},
++ { .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL },},
++ { .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL },},
++ { .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL },},
++ { .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL },},
++ { .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL },},
++ { .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL },},
++ { .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL },},
++ { .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL },},
++ { .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL },},
++ { .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL },},
++ { .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL },},
++ { .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL },},
++ { .ca_index = 0x20, .speakers = { 0, FCH, RR, RL, FC, 0, FR, FL },},
++ { .ca_index = 0x21, .speakers = { 0, FCH, RR, RL, FC, LFE, FR, FL },},
++ { .ca_index = 0x22, .speakers = { TC, 0, RR, RL, FC, 0, FR, FL },},
++ { .ca_index = 0x23, .speakers = { TC, 0, RR, RL, FC, LFE, FR, FL },},
++ { .ca_index = 0x24, .speakers = { FRH, FLH, RR, RL, 0, 0, FR, FL },},
++ { .ca_index = 0x25, .speakers = { FRH, FLH, RR, RL, 0, LFE, FR, FL },},
++ { .ca_index = 0x26, .speakers = { FRW, FLW, RR, RL, 0, 0, FR, FL },},
++ { .ca_index = 0x27, .speakers = { FRW, FLW, RR, RL, 0, LFE, FR, FL },},
++ { .ca_index = 0x28, .speakers = { TC, RC, RR, RL, FC, 0, FR, FL },},
++ { .ca_index = 0x29, .speakers = { TC, RC, RR, RL, FC, LFE, FR, FL },},
++ { .ca_index = 0x2a, .speakers = { FCH, RC, RR, RL, FC, 0, FR, FL },},
++ { .ca_index = 0x2b, .speakers = { FCH, RC, RR, RL, FC, LFE, FR, FL },},
++ { .ca_index = 0x2c, .speakers = { TC, FCH, RR, RL, FC, 0, FR, FL },},
++ { .ca_index = 0x2d, .speakers = { TC, FCH, RR, RL, FC, LFE, FR, FL },},
++ { .ca_index = 0x2e, .speakers = { FRH, FLH, RR, RL, FC, 0, FR, FL },},
++ { .ca_index = 0x2f, .speakers = { FRH, FLH, RR, RL, FC, LFE, FR, FL },},
++ { .ca_index = 0x30, .speakers = { FRW, FLW, RR, RL, FC, 0, FR, FL },},
++ { .ca_index = 0x31, .speakers = { FRW, FLW, RR, RL, FC, LFE, FR, FL },},
++};
++
++/* Compute derived values in channel_allocations[] */
++static void init_channel_allocations(void)
++{
++ struct cea_channel_speaker_allocation *p;
++ int i, j;
++
++ for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
++ p = channel_allocations + i;
++ p->channels = 0;
++ p->spk_mask = 0;
++ for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
++ if (p->speakers[j]) {
++ p->channels++;
++ p->spk_mask |= p->speakers[j];
++ }
++ }
++}
++
++/*
++ * The transformation takes two steps:
++ *
++ * speaker_alloc => (edid_speaker_allocation_bits[]) => spk_mask
++ * spk_mask => (channel_allocations[]) => CA
++ *
++ * TODO: it could select the wrong CA from multiple candidates.
++*/
++static int hdmi_channel_allocation(int channels)
++{
++ int spk_mask = 0, ca = 0, i, tmpchn, tmpspk;
++
++ /* CA defaults to 0 for basic stereo audio */
++ if (channels <= 2)
++ return 0;
++
++ /*
++ * Expand EDID's speaker allocation mask
++ *
++ * EDID tells the speaker mask in a compact(paired) form,
++ * expand EDID's notions to match the ones used by Audio InfoFrame.
++ */
++ for (i = 0; i < ARRAY_SIZE(edid_speaker_allocation_bits); i++) {
++ if (edid_cfg.speaker_alloc & (1 << i))
++ spk_mask |= edid_speaker_allocation_bits[i];
++ }
++
++ /* Search for the first working match in the CA table */
++ for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
++ tmpchn = channel_allocations[i].channels;
++ tmpspk = channel_allocations[i].spk_mask;
++
++ if (channels == tmpchn && (spk_mask & tmpspk) == tmpspk) {
++ ca = channel_allocations[i].ca_index;
++ break;
++ }
++ }
++
++ return ca;
++}
++
++static void hdmi_set_audio_infoframe(unsigned int channels)
++{
++ u8 audiconf0, audiconf2;
++
++ /*
++ * From CEA-861-D spec:
++ * HDMI requires the CT, SS and SF fields to be set to 0 ("Refer
++ * to Stream Header") as these items are carried in the audio stream.
++ *
++ * So we only set the CC and CA fields.
++ */
++ audiconf0 = ((channels - 1) << HDMI_FC_AUDICONF0_CC_OFFSET) &
++ HDMI_FC_AUDICONF0_CC_MASK;
++
++ audiconf2 = hdmi_channel_allocation(channels);
++
++ hdmi_writeb(audiconf0, HDMI_FC_AUDICONF0);
++ hdmi_writeb(0, HDMI_FC_AUDICONF1);
++ hdmi_writeb(audiconf2, HDMI_FC_AUDICONF2);
++ hdmi_writeb(0, HDMI_FC_AUDICONF3);
++}
++
++static int cea_audio_rates[HDMI_MAX_RATES] = {
++ 32000, 44100, 48000, 88200, 96000, 176400, 192000,
++};
++
++static void fsl_hdmi_get_playback_rates(void)
++{
++ int i, count = 0;
++ u8 rates;
++
++ /* Always assume basic audio support */
++ rates = edid_cfg.sample_rates | 0x7;
++
++ for (i = 0 ; i < HDMI_MAX_RATES ; i++)
++ if ((rates & (1 << i)) != 0)
++ playback_rates[count++] = cea_audio_rates[i];
++
++ playback_constraint_rates.list = playback_rates;
++ playback_constraint_rates.count = count;
++
++ for (i = 0 ; i < playback_constraint_rates.count ; i++)
++ pr_debug("%s: constraint = %d Hz\n", __func__, playback_rates[i]);
++}
++
++static void fsl_hdmi_get_playback_sample_size(void)
++{
++ int i = 0;
++
++ /* Always assume basic audio support */
++ playback_sample_size[i++] = 16;
++
++ if (edid_cfg.sample_sizes & 0x4)
++ playback_sample_size[i++] = 32;
++
++ playback_constraint_bits.list = playback_sample_size;
++ playback_constraint_bits.count = i;
++
++ for (i = 0 ; i < playback_constraint_bits.count ; i++)
++ pr_debug("%s: constraint = %d bits\n", __func__, playback_sample_size[i]);
++}
++
++static void fsl_hdmi_get_playback_channels(void)
++{
++ int channels = 2, i = 0;
++
++ /* Always assume basic audio support */
++ playback_channels[i++] = channels;
++ channels += 2;
++
++ while ((i < HDMI_MAX_CHANNEL_CONSTRAINTS) &&
++ (channels <= edid_cfg.max_channels)) {
++ playback_channels[i++] = channels;
++ channels += 2;
++ }
++
++ playback_constraint_channels.list = playback_channels;
++ playback_constraint_channels.count = i;
++
++ for (i = 0 ; i < playback_constraint_channels.count ; i++)
++ pr_debug("%s: constraint = %d channels\n", __func__, playback_channels[i]);
++}
++
++static int fsl_hdmi_update_constraints(struct snd_pcm_substream *substream)
++{
++ struct snd_pcm_runtime *runtime = substream->runtime;
++ int edid_status, ret;
++
++ edid_status = hdmi_get_edid_cfg(&edid_cfg);
++
++ if (edid_status && !edid_cfg.hdmi_cap)
++ return -1;
++
++ fsl_hdmi_get_playback_rates();
++ ret = snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
++ &playback_constraint_rates);
++ if (ret)
++ return ret;
++
++ fsl_hdmi_get_playback_sample_size();
++ ret = snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
++ &playback_constraint_bits);
++ if (ret)
++ return ret;
++
++ fsl_hdmi_get_playback_channels();
++ ret = snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
++ &playback_constraint_channels);
++ if (ret)
++ return ret;
++
++ ret = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
++ if (ret)
++ return ret;
++
++ return 0;
++}
++
++static int fsl_hdmi_soc_startup(struct snd_pcm_substream *substream,
++ struct snd_soc_dai *dai)
++{
++ struct imx_hdmi *hdmi_data = snd_soc_dai_get_drvdata(dai);
++ int ret;
++
++ ret = fsl_hdmi_update_constraints(substream);
++ if (ret < 0)
++ return ret;
++
++ clk_prepare_enable(hdmi_data->isfr_clk);
++ clk_prepare_enable(hdmi_data->iahb_clk);
++
++ dev_dbg(dai->dev, "%s hdmi clks: isfr:%d iahb:%d\n", __func__,
++ (int)clk_get_rate(hdmi_data->isfr_clk),
++ (int)clk_get_rate(hdmi_data->iahb_clk));
++
++ /* Indicates the subpacket represents a flatline sample */
++ hdmi_audio_writeb(FC_AUDSCONF, AUD_PACKET_SAMPFIT, 0x0);
++
++ return 0;
++}
++
++static void fsl_hdmi_soc_shutdown(struct snd_pcm_substream *substream,
++ struct snd_soc_dai *dai)
++{
++ struct imx_hdmi *hdmi_data = snd_soc_dai_get_drvdata(dai);
++
++ clk_disable_unprepare(hdmi_data->iahb_clk);
++ clk_disable_unprepare(hdmi_data->isfr_clk);
++}
++
++static int fsl_hdmi_soc_prepare(struct snd_pcm_substream *substream,
++ struct snd_soc_dai *dai)
++{
++ struct snd_pcm_runtime *runtime = substream->runtime;
++
++ hdmi_set_audio_infoframe(runtime->channels);
++ hdmi_audio_writeb(FC_AUDSCONF, AUD_PACKET_LAYOUT,
++ (runtime->channels > 2) ? 0x1 : 0x0);
++ hdmi_set_sample_rate(runtime->rate);
++ dumpregs(dai);
++
++ return 0;
++}
++
++static struct snd_soc_dai_ops fsl_hdmi_soc_dai_ops = {
++ .startup = fsl_hdmi_soc_startup,
++ .shutdown = fsl_hdmi_soc_shutdown,
++ .prepare = fsl_hdmi_soc_prepare,
++};
++
++/* IEC60958 status functions */
++static int fsl_hdmi_iec_info(struct snd_kcontrol *kcontrol,
++ struct snd_ctl_elem_info *uinfo)
++{
++ uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
++ uinfo->count = 1;
++
++ return 0;
++}
++
++
++static int fsl_hdmi_iec_get(struct snd_kcontrol *kcontrol,
++ struct snd_ctl_elem_value *uvalue)
++{
++ int i;
++
++ for (i = 0 ; i < 6 ; i++)
++ uvalue->value.iec958.status[i] = iec_header.status[i];
++
++ return 0;
++}
++
++static int fsl_hdmi_iec_put(struct snd_kcontrol *kcontrol,
++ struct snd_ctl_elem_value *uvalue)
++{
++ int i;
++
++ /* Do not allow professional mode */
++ if (uvalue->value.iec958.status[0] & IEC958_AES0_PROFESSIONAL)
++ return -EPERM;
++
++ for (i = 0 ; i < 6 ; i++) {
++ iec_header.status[i] = uvalue->value.iec958.status[i];
++ pr_debug("%s status[%d]=0x%02x\n", __func__, i, iec_header.status[i]);
++ }
++
++ return 0;
++}
++
++static struct snd_kcontrol_new fsl_hdmi_ctrls[] = {
++ /* Status cchanel controller */
++ {
++ .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
++ .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
++ .access = SNDRV_CTL_ELEM_ACCESS_READ |
++ SNDRV_CTL_ELEM_ACCESS_WRITE |
++ SNDRV_CTL_ELEM_ACCESS_VOLATILE,
++ .info = fsl_hdmi_iec_info,
++ .get = fsl_hdmi_iec_get,
++ .put = fsl_hdmi_iec_put,
++ },
++};
++
++static int fsl_hdmi_soc_dai_probe(struct snd_soc_dai *dai)
++{
++ int ret;
++
++ init_channel_allocations();
++
++ ret = snd_soc_add_dai_controls(dai, fsl_hdmi_ctrls,
++ ARRAY_SIZE(fsl_hdmi_ctrls));
++ if (ret)
++ dev_warn(dai->dev, "failed to add dai controls\n");
++
++ return 0;
++}
++
++static struct snd_soc_dai_driver fsl_hdmi_dai = {
++ .probe = &fsl_hdmi_soc_dai_probe,
++ .playback = {
++ .channels_min = 2,
++ .channels_max = 8,
++ .rates = MXC_HDMI_RATES_PLAYBACK,
++ .formats = MXC_HDMI_FORMATS_PLAYBACK,
++ },
++ .ops = &fsl_hdmi_soc_dai_ops,
++};
++
++static const struct snd_soc_component_driver fsl_hdmi_component = {
++ .name = "fsl-hdmi",
++};
++
++static int fsl_hdmi_dai_probe(struct platform_device *pdev)
++{
++ struct device_node *np = pdev->dev.of_node;
++ struct imx_hdmi *hdmi_data;
++ int ret = 0;
++
++ if (!np)
++ return -ENODEV;
++
++ if (!hdmi_get_registered()) {
++ dev_err(&pdev->dev, "failed to probe. Load HDMI-video first.\n");
++ return -ENOMEM;
++ }
++
++ hdmi_data = devm_kzalloc(&pdev->dev, sizeof(*hdmi_data), GFP_KERNEL);
++ if (!hdmi_data) {
++ dev_err(&pdev->dev, "failed to alloc hdmi_data\n");
++ return -ENOMEM;
++ }
++
++ hdmi_data->pdev = pdev;
++
++ memcpy(&hdmi_data->cpu_dai_drv, &fsl_hdmi_dai, sizeof(fsl_hdmi_dai));
++ hdmi_data->cpu_dai_drv.name = np->name;
++
++ hdmi_data->isfr_clk = devm_clk_get(&pdev->dev, "hdmi_isfr");
++ if (IS_ERR(hdmi_data->isfr_clk)) {
++ ret = PTR_ERR(hdmi_data->isfr_clk);
++ dev_err(&pdev->dev, "failed to get HDMI isfr clk: %d\n", ret);
++ return -EINVAL;
++ }
++
++ hdmi_data->iahb_clk = devm_clk_get(&pdev->dev, "hdmi_iahb");
++ if (IS_ERR(hdmi_data->iahb_clk)) {
++ ret = PTR_ERR(hdmi_data->iahb_clk);
++ dev_err(&pdev->dev, "failed to get HDMI ahb clk: %d\n", ret);
++ return -EINVAL;
++ }
++
++ dev_set_drvdata(&pdev->dev, hdmi_data);
++ ret = snd_soc_register_component(&pdev->dev, &fsl_hdmi_component,
++ &hdmi_data->cpu_dai_drv, 1);
++ if (ret) {
++ dev_err(&pdev->dev, "register DAI failed\n");
++ return ret;
++ }
++
++ hdmi_data->codec_dev = platform_device_register_simple(
++ "hdmi-audio-codec", -1, NULL, 0);
++ if (IS_ERR(hdmi_data->codec_dev)) {
++ dev_err(&pdev->dev, "failed to register HDMI audio codec\n");
++ ret = PTR_ERR(hdmi_data->codec_dev);
++ goto fail;
++ }
++
++ hdmi_data->dma_dev = platform_device_alloc("imx-hdmi-audio", -1);
++ if (IS_ERR(hdmi_data->dma_dev)) {
++ ret = PTR_ERR(hdmi_data->dma_dev);
++ goto fail_dma;
++ }
++
++ platform_set_drvdata(hdmi_data->dma_dev, hdmi_data);
++
++ ret = platform_device_add(hdmi_data->dma_dev);
++ if (ret) {
++ platform_device_put(hdmi_data->dma_dev);
++ goto fail_dma;
++ }
++
++ return 0;
++
++fail_dma:
++ platform_device_unregister(hdmi_data->codec_dev);
++fail:
++ snd_soc_unregister_component(&pdev->dev);
++
++ return ret;
++}
++
++static int fsl_hdmi_dai_remove(struct platform_device *pdev)
++{
++ struct imx_hdmi *hdmi_data = platform_get_drvdata(pdev);
++
++ platform_device_unregister(hdmi_data->dma_dev);
++ platform_device_unregister(hdmi_data->codec_dev);
++ snd_soc_unregister_component(&pdev->dev);
++
++ return 0;
++}
++
++static const struct of_device_id fsl_hdmi_dai_dt_ids[] = {
++ { .compatible = "fsl,imx6dl-hdmi-audio", },
++ { .compatible = "fsl,imx6q-hdmi-audio", },
++ { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, fsl_hdmi_dai_dt_ids);
++
++static struct platform_driver fsl_hdmi_driver = {
++ .probe = fsl_hdmi_dai_probe,
++ .remove = fsl_hdmi_dai_remove,
++ .driver = {
++ .name = "fsl-hdmi-dai",
++ .owner = THIS_MODULE,
++ .of_match_table = fsl_hdmi_dai_dt_ids,
++ },
++};
++module_platform_driver(fsl_hdmi_driver);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("IMX HDMI TX DAI");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:fsl-hdmi-dai");
+diff -Nur linux-4.1.3/sound/soc/fsl/fsl_sai.c linux-xbian-imx6/sound/soc/fsl/fsl_sai.c
+--- linux-4.1.3/sound/soc/fsl/fsl_sai.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/sound/soc/fsl/fsl_sai.c 2015-07-27 23:13:11.149203200 +0200
+@@ -1,7 +1,7 @@
+ /*
+ * Freescale ALSA SoC Digital Audio Interface (SAI) driver.
+ *
+- * Copyright 2012-2013 Freescale Semiconductor, Inc.
++ * Copyright 2012-2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software, you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+@@ -662,7 +662,7 @@
+ return ret;
+
+ if (sai->sai_on_imx)
+- return imx_pcm_dma_init(pdev);
++ return imx_pcm_dma_init(pdev, IMX_SAI_DMABUF_SIZE);
+ else
+ return devm_snd_dmaengine_pcm_register(&pdev->dev, NULL,
+ SND_DMAENGINE_PCM_FLAG_NO_RESIDUE);
+diff -Nur linux-4.1.3/sound/soc/fsl/fsl_spdif.c linux-xbian-imx6/sound/soc/fsl/fsl_spdif.c
+--- linux-4.1.3/sound/soc/fsl/fsl_spdif.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/sound/soc/fsl/fsl_spdif.c 2015-07-27 23:13:11.149203200 +0200
+@@ -1,7 +1,7 @@
+ /*
+ * Freescale S/PDIF ALSA SoC Digital Audio Interface (DAI) driver
+ *
+- * Copyright (C) 2013 Freescale Semiconductor, Inc.
++ * Copyright (C) 2013-2014 Freescale Semiconductor, Inc.
+ *
+ * Based on stmp3xxx_spdif_dai.c
+ * Vladimir Barinov <vbarinov@embeddedalley.com>
+@@ -20,6 +20,8 @@
+ #include <linux/of_device.h>
+ #include <linux/of_irq.h>
+ #include <linux/regmap.h>
++#include <linux/pm_runtime.h>
++#include <linux/busfreq-imx6.h>
+
+ #include <sound/asoundef.h>
+ #include <sound/dmaengine_pcm.h>
+@@ -106,8 +108,11 @@
+ struct clk *rxclk;
+ struct clk *coreclk;
+ struct clk *sysclk;
++ struct clk *dmaclk;
+ struct snd_dmaengine_dai_dma_data dma_params_tx;
+ struct snd_dmaengine_dai_dma_data dma_params_rx;
++ /* regcache for SRPC */
++ u32 regcache_srpc;
+ };
+
+ /* DPLL locked and lock loss interrupt handler */
+@@ -300,6 +305,8 @@
+ struct regmap *regmap = spdif_priv->regmap;
+ u32 val, cycle = 1000;
+
++ regcache_cache_bypass(regmap, true);
++
+ regmap_write(regmap, REG_SPDIF_SCR, SCR_SOFT_RESET);
+
+ /*
+@@ -310,6 +317,10 @@
+ regmap_read(regmap, REG_SPDIF_SCR, &val);
+ } while ((val & SCR_SOFT_RESET) && cycle--);
+
++ regcache_cache_bypass(regmap, false);
++ regcache_mark_dirty(regmap);
++ regcache_sync(regmap);
++
+ if (cycle)
+ return 0;
+ else
+@@ -371,7 +382,6 @@
+ unsigned long csfs = 0;
+ u32 stc, mask, rate;
+ u8 clk, txclk_df, sysclk_df;
+- int ret;
+
+ switch (sample_rate) {
+ case 32000:
+@@ -413,21 +423,6 @@
+
+ sysclk_df = spdif_priv->sysclk_df[rate];
+
+- /* Don't mess up the clocks from other modules */
+- if (clk != STC_TXCLK_SPDIF_ROOT)
+- goto clk_set_bypass;
+-
+- /*
+- * The S/PDIF block needs a clock of 64 * fs * txclk_df.
+- * So request 64 * fs * (txclk_df + 1) to get rounded.
+- */
+- ret = clk_set_rate(spdif_priv->txclk[rate], 64 * sample_rate * (txclk_df + 1));
+- if (ret) {
+- dev_err(&pdev->dev, "failed to set tx clock rate\n");
+- return ret;
+- }
+-
+-clk_set_bypass:
+ dev_dbg(&pdev->dev, "expected clock rate = %d\n",
+ (64 * sample_rate * txclk_df * sysclk_df));
+ dev_dbg(&pdev->dev, "actual clock rate = %ld\n",
+@@ -459,6 +454,8 @@
+ u32 scr, mask, i;
+ int ret;
+
++ pm_runtime_get_sync(cpu_dai->dev);
++
+ /* Reset module and interrupts only for first initialization */
+ if (!cpu_dai->active) {
+ ret = clk_prepare_enable(spdif_priv->coreclk);
+@@ -467,6 +464,12 @@
+ return ret;
+ }
+
++ ret = clk_prepare_enable(spdif_priv->dmaclk);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to enable dma clock\n");
++ return ret;
++ }
++
+ ret = spdif_softreset(spdif_priv);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to soft reset\n");
+@@ -533,8 +536,11 @@
+ spdif_intr_status_clear(spdif_priv);
+ regmap_update_bits(regmap, REG_SPDIF_SCR,
+ SCR_LOW_POWER, SCR_LOW_POWER);
++ clk_disable_unprepare(spdif_priv->dmaclk);
+ clk_disable_unprepare(spdif_priv->coreclk);
+ }
++
++ pm_runtime_put_sync(cpu_dai->dev);
+ }
+
+ static int fsl_spdif_hw_params(struct snd_pcm_substream *substream,
+@@ -1015,6 +1021,27 @@
+ }
+ }
+
++static bool fsl_spdif_volatile_reg(struct device *dev, unsigned int reg)
++{
++ switch (reg) {
++ case REG_SPDIF_SRPC:
++ case REG_SPDIF_SIS:
++ case REG_SPDIF_SRL:
++ case REG_SPDIF_SRR:
++ case REG_SPDIF_SRCSH:
++ case REG_SPDIF_SRCSL:
++ case REG_SPDIF_SRU:
++ case REG_SPDIF_SRQ:
++ case REG_SPDIF_STL:
++ case REG_SPDIF_STR:
++ case REG_SPDIF_SRFM:
++ return true;
++ default:
++ return false;
++ }
++
++}
++
+ static bool fsl_spdif_writeable_reg(struct device *dev, unsigned int reg)
+ {
+ switch (reg) {
+@@ -1041,7 +1068,9 @@
+
+ .max_register = REG_SPDIF_STC,
+ .readable_reg = fsl_spdif_readable_reg,
++ .volatile_reg = fsl_spdif_volatile_reg,
+ .writeable_reg = fsl_spdif_writeable_reg,
++ .cache_type = REGCACHE_RBTREE,
+ };
+
+ static u32 fsl_spdif_txclk_caldiv(struct fsl_spdif_priv *spdif_priv,
+@@ -1049,8 +1078,8 @@
+ enum spdif_txrate index, bool round)
+ {
+ const u32 rate[] = { 32000, 44100, 48000, 96000, 192000 };
+- bool is_sysclk = clk_is_match(clk, spdif_priv->sysclk);
+- u64 rate_ideal, rate_actual, sub;
++ bool is_sysclk = clk == spdif_priv->sysclk;
++ u64 rate_actual, sub;
+ u32 sysclk_dfmin, sysclk_dfmax;
+ u32 txclk_df, sysclk_df, arate;
+
+@@ -1060,11 +1089,7 @@
+
+ for (sysclk_df = sysclk_dfmin; sysclk_df <= sysclk_dfmax; sysclk_df++) {
+ for (txclk_df = 1; txclk_df <= 128; txclk_df++) {
+- rate_ideal = rate[index] * (txclk_df + 1) * 64;
+- if (round)
+- rate_actual = clk_round_rate(clk, rate_ideal);
+- else
+- rate_actual = clk_get_rate(clk);
++ rate_actual = clk_get_rate(clk);
+
+ arate = rate_actual / 64;
+ arate /= txclk_df * sysclk_df;
+@@ -1214,6 +1239,13 @@
+ return PTR_ERR(spdif_priv->coreclk);
+ }
+
++ /* Get dma clock for dma script operation */
++ spdif_priv->dmaclk = devm_clk_get(&pdev->dev, "dma");
++ if (IS_ERR(spdif_priv->dmaclk)) {
++ dev_err(&pdev->dev, "no dma clock in devicetree\n");
++ return PTR_ERR(spdif_priv->dmaclk);
++ }
++
+ /* Select clock source for rx/tx clock */
+ spdif_priv->rxclk = devm_clk_get(&pdev->dev, "rxtx1");
+ if (IS_ERR(spdif_priv->rxclk)) {
+@@ -1247,6 +1279,8 @@
+ spdif_priv->dma_params_tx.addr = res->start + REG_SPDIF_STL;
+ spdif_priv->dma_params_rx.addr = res->start + REG_SPDIF_SRL;
+
++ pm_runtime_enable(&pdev->dev);
++
+ /* Register with ASoC */
+ dev_set_drvdata(&pdev->dev, spdif_priv);
+
+@@ -1257,13 +1291,62 @@
+ return ret;
+ }
+
+- ret = imx_pcm_dma_init(pdev);
++ ret = imx_pcm_dma_init(pdev, IMX_SPDIF_DMABUF_SIZE);
+ if (ret)
+ dev_err(&pdev->dev, "imx_pcm_dma_init failed: %d\n", ret);
+
+ return ret;
+ }
+
++#ifdef CONFIG_PM
++static int fsl_spdif_runtime_resume(struct device *dev)
++{
++ request_bus_freq(BUS_FREQ_HIGH);
++ return 0;
++}
++
++static int fsl_spdif_runtime_suspend(struct device *dev)
++{
++ release_bus_freq(BUS_FREQ_HIGH);
++ return 0;
++}
++#endif
++
++#ifdef CONFIG_PM_SLEEP
++static int fsl_spdif_suspend(struct device *dev)
++{
++ struct fsl_spdif_priv *spdif_priv = dev_get_drvdata(dev);
++
++ regmap_read(spdif_priv->regmap, REG_SPDIF_SRPC,
++ &spdif_priv->regcache_srpc);
++
++ regcache_cache_only(spdif_priv->regmap, true);
++ regcache_mark_dirty(spdif_priv->regmap);
++
++ return 0;
++}
++
++static int fsl_spdif_resume(struct device *dev)
++{
++ struct fsl_spdif_priv *spdif_priv = dev_get_drvdata(dev);
++
++ regcache_cache_only(spdif_priv->regmap, false);
++
++ regmap_update_bits(spdif_priv->regmap, REG_SPDIF_SRPC,
++ SRPC_CLKSRC_SEL_MASK | SRPC_GAINSEL_MASK,
++ spdif_priv->regcache_srpc);
++
++ return regcache_sync(spdif_priv->regmap);
++}
++#endif /* CONFIG_PM_SLEEP */
++
++static const struct dev_pm_ops fsl_spdif_pm = {
++ SET_RUNTIME_PM_OPS(fsl_spdif_runtime_suspend,
++ fsl_spdif_runtime_resume,
++ NULL)
++ SET_SYSTEM_SLEEP_PM_OPS(fsl_spdif_suspend, fsl_spdif_resume)
++};
++
+ static const struct of_device_id fsl_spdif_dt_ids[] = {
+ { .compatible = "fsl,imx35-spdif", },
+ { .compatible = "fsl,vf610-spdif", },
+@@ -1275,6 +1358,7 @@
+ .driver = {
+ .name = "fsl-spdif-dai",
+ .of_match_table = fsl_spdif_dt_ids,
++ .pm = &fsl_spdif_pm,
+ },
+ .probe = fsl_spdif_probe,
+ };
+diff -Nur linux-4.1.3/sound/soc/fsl/fsl_ssi.c linux-xbian-imx6/sound/soc/fsl/fsl_ssi.c
+--- linux-4.1.3/sound/soc/fsl/fsl_ssi.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/sound/soc/fsl/fsl_ssi.c 2015-07-27 23:13:11.153188979 +0200
+@@ -3,7 +3,7 @@
+ *
+ * Author: Timur Tabi <timur@freescale.com>
+ *
+- * Copyright 2007-2010 Freescale Semiconductor, Inc.
++ * Copyright (C) 2007-2013 Freescale Semiconductor, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+@@ -30,19 +30,21 @@
+ * around this by not polling these bits but only wait a fixed delay.
+ */
+
++#include <linux/busfreq-imx6.h>
+ #include <linux/init.h>
+ #include <linux/io.h>
+ #include <linux/module.h>
+ #include <linux/interrupt.h>
+ #include <linux/clk.h>
++#include <linux/debugfs.h>
+ #include <linux/device.h>
+ #include <linux/delay.h>
+ #include <linux/slab.h>
+ #include <linux/spinlock.h>
+-#include <linux/of.h>
+ #include <linux/of_address.h>
+ #include <linux/of_irq.h>
+ #include <linux/of_platform.h>
++#include <linux/pm_runtime.h>
+
+ #include <sound/core.h>
+ #include <sound/pcm.h>
+@@ -54,6 +56,43 @@
+ #include "fsl_ssi.h"
+ #include "imx-pcm.h"
+
++#ifdef PPC
++#define read_ssi(addr) in_be32(addr)
++#define write_ssi(val, addr) out_be32(addr, val)
++#define write_ssi_mask(addr, clear, set) clrsetbits_be32(addr, clear, set)
++#else
++#define read_ssi(addr) readl(addr)
++#define write_ssi(val, addr) writel(val, addr)
++/*
++ * FIXME: Proper locking should be added at write_ssi_mask caller level
++ * to ensure this register read/modify/write sequence is race free.
++ */
++static inline void write_ssi_mask(u32 __iomem *addr, u32 clear, u32 set)
++{
++ u32 val = readl(addr);
++ val = (val & ~clear) | set;
++ writel(val, addr);
++}
++#endif
++
++#ifdef DEBUG
++#define NUM_OF_SSI_REG (sizeof(struct ccsr_ssi) / sizeof(__be32))
++
++void dump_reg(struct ccsr_ssi __iomem *ssi)
++{
++ u32 val, i;
++
++ for (i = 0; i < NUM_OF_SSI_REG; i++) {
++ if (&ssi->stx0 + i == NULL)
++ continue;
++ val = read_ssi(&ssi->stx0 + i);
++ pr_debug("REG %x = %x\n", (u32)(&ssi->stx0 + i) & 0xff, val);
++ }
++}
++#else
++void dump_reg(struct ccsr_ssi __iomem *ssi) {}
++#endif
++
+ /**
+ * FSLSSI_I2S_RATES: sample rates supported by the I2S
+ *
+@@ -67,6 +106,8 @@
+ /**
+ * FSLSSI_I2S_FORMATS: audio formats supported by the SSI
+ *
++ * This driver currently only supports the SSI running in I2S slave mode.
++ *
+ * The SSI has a limitation in that the samples must be in the same byte
+ * order as the host CPU. This is because when multiple bytes are written
+ * to the STX register, the bytes and bits must be written in the same
+@@ -92,6 +133,8 @@
+ #define FSLSSI_SIER_DBG_TX_FLAGS (CCSR_SSI_SIER_TFE0_EN | \
+ CCSR_SSI_SIER_TLS_EN | CCSR_SSI_SIER_TFS_EN | \
+ CCSR_SSI_SIER_TUE0_EN | CCSR_SSI_SIER_TFRC_EN)
++#define FSLSSI_SISR_MASK (FSLSSI_SIER_DBG_RX_FLAGS | FSLSSI_SIER_DBG_TX_FLAGS)
++
+
+ enum fsl_ssi_type {
+ FSL_SSI_MCP8610,
+@@ -111,158 +154,105 @@
+ struct fsl_ssi_reg_val rx;
+ struct fsl_ssi_reg_val tx;
+ };
+-static const struct regmap_config fsl_ssi_regconfig = {
+- .max_register = CCSR_SSI_SACCDIS,
+- .reg_bits = 32,
+- .val_bits = 32,
+- .reg_stride = 4,
+- .val_format_endian = REGMAP_ENDIAN_NATIVE,
+-};
+-
+-struct fsl_ssi_soc_data {
+- bool imx;
+- bool offline_config;
+- u32 sisr_write_mask;
+-};
+
+ /**
+ * fsl_ssi_private: per-SSI private data
+ *
+- * @reg: Pointer to the regmap registers
+- * @irq: IRQ of this SSI
+- * @cpu_dai_drv: CPU DAI driver for this device
+- *
+- * @dai_fmt: DAI configuration this device is currently used with
+- * @i2s_mode: i2s and network mode configuration of the device. Is used to
+- * switch between normal and i2s/network mode
+- * mode depending on the number of channels
+- * @use_dma: DMA is used or FIQ with stream filter
+- * @use_dual_fifo: DMA with support for both FIFOs used
+- * @fifo_deph: Depth of the SSI FIFOs
+- * @rxtx_reg_val: Specific register settings for receive/transmit configuration
+- *
+- * @clk: SSI clock
+- * @baudclk: SSI baud clock for master mode
+- * @baudclk_streams: Active streams that are using baudclk
+- * @bitclk_freq: bitclock frequency set by .set_dai_sysclk
+- *
+- * @dma_params_tx: DMA transmit parameters
+- * @dma_params_rx: DMA receive parameters
++ * @ssi: pointer to the SSI's registers
+ * @ssi_phys: physical address of the SSI registers
+- *
+- * @fiq_params: FIQ stream filtering parameters
+- *
+- * @pdev: Pointer to pdev used for deprecated fsl-ssi sound card
+- *
+- * @dbg_stats: Debugging statistics
+- *
+- * @soc: SoC specifc data
++ * @irq: IRQ of this SSI
++ * @playback: the number of playback streams opened
++ * @capture: the number of capture streams opened
++ * @cpu_dai: the CPU DAI for this device
++ * @dev_attr: the sysfs device attribute structure
++ * @stats: SSI statistics
++ * @name: name for this device
+ */
+ struct fsl_ssi_private {
+- struct regmap *regs;
+- int irq;
++ struct ccsr_ssi __iomem *ssi;
++ dma_addr_t ssi_phys;
++ unsigned int irq;
++ unsigned int fifo_depth;
+ struct snd_soc_dai_driver cpu_dai_drv;
++ struct platform_device *pdev;
+
+- unsigned int dai_fmt;
+- u8 i2s_mode;
++ enum fsl_ssi_type hw_type;
++ bool new_binding;
++ bool ssi_on_imx;
++ bool imx_ac97;
+ bool use_dma;
++ bool baudclk_locked;
++ bool irq_stats;
++ bool offline_config;
+ bool use_dual_fifo;
+- bool has_ipg_clk_name;
+- unsigned int fifo_depth;
+- struct fsl_ssi_rxtx_reg_val rxtx_reg_val;
+-
+- struct clk *clk;
++ u8 i2s_mode;
++ spinlock_t baudclk_lock;
+ struct clk *baudclk;
+- unsigned int baudclk_streams;
+- unsigned int bitclk_freq;
+-
+- /* DMA params */
++ struct clk *clk;
+ struct snd_dmaengine_dai_dma_data dma_params_tx;
+ struct snd_dmaengine_dai_dma_data dma_params_rx;
+- dma_addr_t ssi_phys;
+-
+- /* params for non-dma FIQ stream filtered mode */
+ struct imx_pcm_fiq_params fiq_params;
++ /* Register values for rx/tx configuration */
++ struct fsl_ssi_rxtx_reg_val rxtx_reg_val;
+
+- /* Used when using fsl-ssi as sound-card. This is only used by ppc and
+- * should be replaced with simple-sound-card. */
+- struct platform_device *pdev;
+-
+- struct fsl_ssi_dbg dbg_stats;
+-
+- const struct fsl_ssi_soc_data *soc;
+-};
+-
+-/*
+- * imx51 and later SoCs have a slightly different IP that allows the
+- * SSI configuration while the SSI unit is running.
+- *
+- * More important, it is necessary on those SoCs to configure the
+- * sperate TX/RX DMA bits just before starting the stream
+- * (fsl_ssi_trigger). The SDMA unit has to be configured before fsl_ssi
+- * sends any DMA requests to the SDMA unit, otherwise it is not defined
+- * how the SDMA unit handles the DMA request.
+- *
+- * SDMA units are present on devices starting at imx35 but the imx35
+- * reference manual states that the DMA bits should not be changed
+- * while the SSI unit is running (SSIEN). So we support the necessary
+- * online configuration of fsl-ssi starting at imx51.
+- */
++ struct {
++ unsigned int rfrc;
++ unsigned int tfrc;
++ unsigned int cmdau;
++ unsigned int cmddu;
++ unsigned int rxt;
++ unsigned int rdr1;
++ unsigned int rdr0;
++ unsigned int tde1;
++ unsigned int tde0;
++ unsigned int roe1;
++ unsigned int roe0;
++ unsigned int tue1;
++ unsigned int tue0;
++ unsigned int tfs;
++ unsigned int rfs;
++ unsigned int tls;
++ unsigned int rls;
++ unsigned int rff1;
++ unsigned int rff0;
++ unsigned int tfe1;
++ unsigned int tfe0;
++ } stats;
++ struct dentry *dbg_dir;
++ struct dentry *dbg_stats;
+
+-static struct fsl_ssi_soc_data fsl_ssi_mpc8610 = {
+- .imx = false,
+- .offline_config = true,
+- .sisr_write_mask = CCSR_SSI_SISR_RFRC | CCSR_SSI_SISR_TFRC |
+- CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
+- CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1,
++ char name[1];
+ };
+
+-static struct fsl_ssi_soc_data fsl_ssi_imx21 = {
+- .imx = true,
+- .offline_config = true,
+- .sisr_write_mask = 0,
+-};
++#ifdef CONFIG_PM
++static int fsl_ssi_runtime_resume(struct device *dev)
++{
++ request_bus_freq(BUS_FREQ_AUDIO);
++ return 0;
++}
+
+-static struct fsl_ssi_soc_data fsl_ssi_imx35 = {
+- .imx = true,
+- .offline_config = true,
+- .sisr_write_mask = CCSR_SSI_SISR_RFRC | CCSR_SSI_SISR_TFRC |
+- CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
+- CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1,
+-};
++static int fsl_ssi_runtime_suspend(struct device *dev)
++{
++ release_bus_freq(BUS_FREQ_AUDIO);
++ return 0;
++}
++#endif
+
+-static struct fsl_ssi_soc_data fsl_ssi_imx51 = {
+- .imx = true,
+- .offline_config = false,
+- .sisr_write_mask = CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
+- CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1,
++static const struct dev_pm_ops fsl_ssi_pm = {
++ SET_RUNTIME_PM_OPS(fsl_ssi_runtime_suspend,
++ fsl_ssi_runtime_resume,
++ NULL)
+ };
+
+ static const struct of_device_id fsl_ssi_ids[] = {
+- { .compatible = "fsl,mpc8610-ssi", .data = &fsl_ssi_mpc8610 },
+- { .compatible = "fsl,imx51-ssi", .data = &fsl_ssi_imx51 },
+- { .compatible = "fsl,imx35-ssi", .data = &fsl_ssi_imx35 },
+- { .compatible = "fsl,imx21-ssi", .data = &fsl_ssi_imx21 },
++ { .compatible = "fsl,mpc8610-ssi", .data = (void *) FSL_SSI_MCP8610},
++ { .compatible = "fsl,imx51-ssi", .data = (void *) FSL_SSI_MX51},
++ { .compatible = "fsl,imx35-ssi", .data = (void *) FSL_SSI_MX35},
++ { .compatible = "fsl,imx21-ssi", .data = (void *) FSL_SSI_MX21},
+ {}
+ };
+ MODULE_DEVICE_TABLE(of, fsl_ssi_ids);
+
+-static bool fsl_ssi_is_ac97(struct fsl_ssi_private *ssi_private)
+-{
+- return !!(ssi_private->dai_fmt & SND_SOC_DAIFMT_AC97);
+-}
+-
+-static bool fsl_ssi_is_i2s_master(struct fsl_ssi_private *ssi_private)
+-{
+- return (ssi_private->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) ==
+- SND_SOC_DAIFMT_CBS_CFS;
+-}
+-
+-static bool fsl_ssi_is_i2s_cbm_cfs(struct fsl_ssi_private *ssi_private)
+-{
+- return (ssi_private->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) ==
+- SND_SOC_DAIFMT_CBM_CFS;
+-}
+ /**
+ * fsl_ssi_isr: SSI interrupt handler
+ *
+@@ -278,74 +268,281 @@
+ static irqreturn_t fsl_ssi_isr(int irq, void *dev_id)
+ {
+ struct fsl_ssi_private *ssi_private = dev_id;
+- struct regmap *regs = ssi_private->regs;
++ struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
++ irqreturn_t ret = IRQ_NONE;
+ __be32 sisr;
+ __be32 sisr2;
++ __be32 sisr_write_mask = 0;
++
++ switch (ssi_private->hw_type) {
++ case FSL_SSI_MX21:
++ sisr_write_mask = 0;
++ break;
++
++ case FSL_SSI_MCP8610:
++ case FSL_SSI_MX35:
++ sisr_write_mask = CCSR_SSI_SISR_RFRC | CCSR_SSI_SISR_TFRC |
++ CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
++ CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1;
++ break;
++
++ case FSL_SSI_MX51:
++ sisr_write_mask = CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
++ CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1;
++ break;
++ }
+
+ /* We got an interrupt, so read the status register to see what we
+ were interrupted for. We mask it with the Interrupt Enable register
+ so that we only check for events that we're interested in.
+ */
+- regmap_read(regs, CCSR_SSI_SISR, &sisr);
++ sisr = read_ssi(&ssi->sisr) & FSLSSI_SISR_MASK;
+
+- sisr2 = sisr & ssi_private->soc->sisr_write_mask;
++ if (sisr & CCSR_SSI_SISR_RFRC) {
++ ssi_private->stats.rfrc++;
++ ret = IRQ_HANDLED;
++ }
++
++ if (sisr & CCSR_SSI_SISR_TFRC) {
++ ssi_private->stats.tfrc++;
++ ret = IRQ_HANDLED;
++ }
++
++ if (sisr & CCSR_SSI_SISR_CMDAU) {
++ ssi_private->stats.cmdau++;
++ ret = IRQ_HANDLED;
++ }
++
++ if (sisr & CCSR_SSI_SISR_CMDDU) {
++ ssi_private->stats.cmddu++;
++ ret = IRQ_HANDLED;
++ }
++
++ if (sisr & CCSR_SSI_SISR_RXT) {
++ ssi_private->stats.rxt++;
++ ret = IRQ_HANDLED;
++ }
++
++ if (sisr & CCSR_SSI_SISR_RDR1) {
++ ssi_private->stats.rdr1++;
++ ret = IRQ_HANDLED;
++ }
++
++ if (sisr & CCSR_SSI_SISR_RDR0) {
++ ssi_private->stats.rdr0++;
++ ret = IRQ_HANDLED;
++ }
++
++ if (sisr & CCSR_SSI_SISR_TDE1) {
++ ssi_private->stats.tde1++;
++ ret = IRQ_HANDLED;
++ }
++
++ if (sisr & CCSR_SSI_SISR_TDE0) {
++ ssi_private->stats.tde0++;
++ ret = IRQ_HANDLED;
++ }
++
++ if (sisr & CCSR_SSI_SISR_ROE1) {
++ ssi_private->stats.roe1++;
++ ret = IRQ_HANDLED;
++ }
++
++ if (sisr & CCSR_SSI_SISR_ROE0) {
++ ssi_private->stats.roe0++;
++ ret = IRQ_HANDLED;
++ }
++
++ if (sisr & CCSR_SSI_SISR_TUE1) {
++ ssi_private->stats.tue1++;
++ ret = IRQ_HANDLED;
++ }
++
++ if (sisr & CCSR_SSI_SISR_TUE0) {
++ ssi_private->stats.tue0++;
++ ret = IRQ_HANDLED;
++ }
++
++ if (sisr & CCSR_SSI_SISR_TFS) {
++ ssi_private->stats.tfs++;
++ ret = IRQ_HANDLED;
++ }
++
++ if (sisr & CCSR_SSI_SISR_RFS) {
++ ssi_private->stats.rfs++;
++ ret = IRQ_HANDLED;
++ }
++
++ if (sisr & CCSR_SSI_SISR_TLS) {
++ ssi_private->stats.tls++;
++ ret = IRQ_HANDLED;
++ }
++
++ if (sisr & CCSR_SSI_SISR_RLS) {
++ ssi_private->stats.rls++;
++ ret = IRQ_HANDLED;
++ }
++
++ if (sisr & CCSR_SSI_SISR_RFF1) {
++ ssi_private->stats.rff1++;
++ ret = IRQ_HANDLED;
++ }
++
++ if (sisr & CCSR_SSI_SISR_RFF0) {
++ ssi_private->stats.rff0++;
++ ret = IRQ_HANDLED;
++ }
++
++ if (sisr & CCSR_SSI_SISR_TFE1) {
++ ssi_private->stats.tfe1++;
++ ret = IRQ_HANDLED;
++ }
++
++ if (sisr & CCSR_SSI_SISR_TFE0) {
++ ssi_private->stats.tfe0++;
++ ret = IRQ_HANDLED;
++ }
++
++ sisr2 = sisr & sisr_write_mask;
+ /* Clear the bits that we set */
+ if (sisr2)
+- regmap_write(regs, CCSR_SSI_SISR, sisr2);
++ write_ssi(sisr2, &ssi->sisr);
++
++ return ret;
++}
++
++#if IS_ENABLED(CONFIG_DEBUG_FS)
++/* Show the statistics of a flag only if its interrupt is enabled. The
++ * compiler will optimze this code to a no-op if the interrupt is not
++ * enabled.
++ */
++#define SIER_SHOW(flag, name) \
++ do { \
++ if (FSLSSI_SISR_MASK & CCSR_SSI_SIER_##flag) \
++ seq_printf(s, #name "=%u\n", ssi_private->stats.name); \
++ } while (0)
++
++
++/**
++ * fsl_sysfs_ssi_show: display SSI statistics
++ *
++ * Display the statistics for the current SSI device. To avoid confusion,
++ * we only show those counts that are enabled.
++ */
++static int fsl_ssi_stats_show(struct seq_file *s, void *unused)
++{
++ struct fsl_ssi_private *ssi_private = s->private;
++
++ SIER_SHOW(RFRC_EN, rfrc);
++ SIER_SHOW(TFRC_EN, tfrc);
++ SIER_SHOW(CMDAU_EN, cmdau);
++ SIER_SHOW(CMDDU_EN, cmddu);
++ SIER_SHOW(RXT_EN, rxt);
++ SIER_SHOW(RDR1_EN, rdr1);
++ SIER_SHOW(RDR0_EN, rdr0);
++ SIER_SHOW(TDE1_EN, tde1);
++ SIER_SHOW(TDE0_EN, tde0);
++ SIER_SHOW(ROE1_EN, roe1);
++ SIER_SHOW(ROE0_EN, roe0);
++ SIER_SHOW(TUE1_EN, tue1);
++ SIER_SHOW(TUE0_EN, tue0);
++ SIER_SHOW(TFS_EN, tfs);
++ SIER_SHOW(RFS_EN, rfs);
++ SIER_SHOW(TLS_EN, tls);
++ SIER_SHOW(RLS_EN, rls);
++ SIER_SHOW(RFF1_EN, rff1);
++ SIER_SHOW(RFF0_EN, rff0);
++ SIER_SHOW(TFE1_EN, tfe1);
++ SIER_SHOW(TFE0_EN, tfe0);
++
++ return 0;
++}
++
++static int fsl_ssi_stats_open(struct inode *inode, struct file *file)
++{
++ return single_open(file, fsl_ssi_stats_show, inode->i_private);
++}
+
+- fsl_ssi_dbg_isr(&ssi_private->dbg_stats, sisr);
++static const struct file_operations fsl_ssi_stats_ops = {
++ .open = fsl_ssi_stats_open,
++ .read = seq_read,
++ .llseek = seq_lseek,
++ .release = single_release,
++};
++
++static int fsl_ssi_debugfs_create(struct fsl_ssi_private *ssi_private,
++ struct device *dev)
++{
++ ssi_private->dbg_dir = debugfs_create_dir(dev_name(dev), NULL);
++ if (!ssi_private->dbg_dir)
++ return -ENOMEM;
++
++ ssi_private->dbg_stats = debugfs_create_file("stats", S_IRUGO,
++ ssi_private->dbg_dir, ssi_private, &fsl_ssi_stats_ops);
++ if (!ssi_private->dbg_stats) {
++ debugfs_remove(ssi_private->dbg_dir);
++ return -ENOMEM;
++ }
++
++ return 0;
++}
++
++static void fsl_ssi_debugfs_remove(struct fsl_ssi_private *ssi_private)
++{
++ debugfs_remove(ssi_private->dbg_stats);
++ debugfs_remove(ssi_private->dbg_dir);
++}
++
++#else
++
++static int fsl_ssi_debugfs_create(struct fsl_ssi_private *ssi_private,
++ struct device *dev)
++{
++ return 0;
++}
+
+- return IRQ_HANDLED;
++static void fsl_ssi_debugfs_remove(struct fsl_ssi_private *ssi_private)
++{
+ }
+
++#endif /* IS_ENABLED(CONFIG_DEBUG_FS) */
++
+ /*
+ * Enable/Disable all rx/tx config flags at once.
+ */
+ static void fsl_ssi_rxtx_config(struct fsl_ssi_private *ssi_private,
+ bool enable)
+ {
+- struct regmap *regs = ssi_private->regs;
++ struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
+ struct fsl_ssi_rxtx_reg_val *vals = &ssi_private->rxtx_reg_val;
+
+ if (enable) {
+- regmap_update_bits(regs, CCSR_SSI_SIER,
+- vals->rx.sier | vals->tx.sier,
+- vals->rx.sier | vals->tx.sier);
+- regmap_update_bits(regs, CCSR_SSI_SRCR,
+- vals->rx.srcr | vals->tx.srcr,
+- vals->rx.srcr | vals->tx.srcr);
+- regmap_update_bits(regs, CCSR_SSI_STCR,
+- vals->rx.stcr | vals->tx.stcr,
+- vals->rx.stcr | vals->tx.stcr);
++ write_ssi_mask(&ssi->sier, 0, vals->rx.sier | vals->tx.sier);
++ write_ssi_mask(&ssi->srcr, 0, vals->rx.srcr | vals->tx.srcr);
++ write_ssi_mask(&ssi->stcr, 0, vals->rx.stcr | vals->tx.stcr);
+ } else {
+- regmap_update_bits(regs, CCSR_SSI_SRCR,
+- vals->rx.srcr | vals->tx.srcr, 0);
+- regmap_update_bits(regs, CCSR_SSI_STCR,
+- vals->rx.stcr | vals->tx.stcr, 0);
+- regmap_update_bits(regs, CCSR_SSI_SIER,
+- vals->rx.sier | vals->tx.sier, 0);
++ write_ssi_mask(&ssi->srcr, vals->rx.srcr | vals->tx.srcr, 0);
++ write_ssi_mask(&ssi->stcr, vals->rx.stcr | vals->tx.stcr, 0);
++ write_ssi_mask(&ssi->sier, vals->rx.sier | vals->tx.sier, 0);
+ }
+ }
+
+-/*
+- * Calculate the bits that have to be disabled for the current stream that is
+- * getting disabled. This keeps the bits enabled that are necessary for the
+- * second stream to work if 'stream_active' is true.
+- *
+- * Detailed calculation:
+- * These are the values that need to be active after disabling. For non-active
+- * second stream, this is 0:
+- * vals_stream * !!stream_active
+- *
+- * The following computes the overall differences between the setup for the
+- * to-disable stream and the active stream, a simple XOR:
+- * vals_disable ^ (vals_stream * !!(stream_active))
+- *
+- * The full expression adds a mask on all values we care about
+- */
+-#define fsl_ssi_disable_val(vals_disable, vals_stream, stream_active) \
+- ((vals_disable) & \
+- ((vals_disable) ^ ((vals_stream) * (u32)!!(stream_active))))
++static void fsl_ssi_clk_ctrl(struct fsl_ssi_private *ssi_private, bool enable)
++{
++ if (enable) {
++ if (ssi_private->ssi_on_imx) {
++ if (!IS_ERR(ssi_private->baudclk))
++ clk_enable(ssi_private->baudclk);
++ clk_enable(ssi_private->clk);
++ }
++ } else {
++ if (ssi_private->ssi_on_imx) {
++ if (!IS_ERR(ssi_private->baudclk))
++ clk_disable(ssi_private->baudclk);
++ clk_disable(ssi_private->clk);
++ }
++ }
++}
+
+ /*
+ * Enable/Disable a ssi configuration. You have to pass either
+@@ -354,22 +551,12 @@
+ static void fsl_ssi_config(struct fsl_ssi_private *ssi_private, bool enable,
+ struct fsl_ssi_reg_val *vals)
+ {
+- struct regmap *regs = ssi_private->regs;
++ struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
+ struct fsl_ssi_reg_val *avals;
+- int nr_active_streams;
+- u32 scr_val;
+- int keep_active;
+-
+- regmap_read(regs, CCSR_SSI_SCR, &scr_val);
+-
+- nr_active_streams = !!(scr_val & CCSR_SSI_SCR_TE) +
++ u32 scr_val = read_ssi(&ssi->scr);
++ int nr_active_streams = !!(scr_val & CCSR_SSI_SCR_TE) +
+ !!(scr_val & CCSR_SSI_SCR_RE);
+
+- if (nr_active_streams - 1 > 0)
+- keep_active = 1;
+- else
+- keep_active = 0;
+-
+ /* Find the other direction values rx or tx which we do not want to
+ * modify */
+ if (&ssi_private->rxtx_reg_val.rx == vals)
+@@ -377,11 +564,12 @@
+ else
+ avals = &ssi_private->rxtx_reg_val.rx;
+
++ fsl_ssi_clk_ctrl(ssi_private, enable);
++
+ /* If vals should be disabled, start with disabling the unit */
+ if (!enable) {
+- u32 scr = fsl_ssi_disable_val(vals->scr, avals->scr,
+- keep_active);
+- regmap_update_bits(regs, CCSR_SSI_SCR, scr, 0);
++ u32 scr = vals->scr & (vals->scr ^ avals->scr);
++ write_ssi_mask(&ssi->scr, scr, 0);
+ }
+
+ /*
+@@ -389,9 +577,9 @@
+ * reconfiguration, so we have to enable all necessary flags at once
+ * even if we do not use them later (capture and playback configuration)
+ */
+- if (ssi_private->soc->offline_config) {
++ if (ssi_private->offline_config) {
+ if ((enable && !nr_active_streams) ||
+- (!enable && !keep_active))
++ (!enable && nr_active_streams == 1))
+ fsl_ssi_rxtx_config(ssi_private, enable);
+
+ goto config_done;
+@@ -402,9 +590,9 @@
+ * (online configuration)
+ */
+ if (enable) {
+- regmap_update_bits(regs, CCSR_SSI_SIER, vals->sier, vals->sier);
+- regmap_update_bits(regs, CCSR_SSI_SRCR, vals->srcr, vals->srcr);
+- regmap_update_bits(regs, CCSR_SSI_STCR, vals->stcr, vals->stcr);
++ write_ssi_mask(&ssi->sier, 0, vals->sier);
++ write_ssi_mask(&ssi->srcr, 0, vals->srcr);
++ write_ssi_mask(&ssi->stcr, 0, vals->stcr);
+ } else {
+ u32 sier;
+ u32 srcr;
+@@ -420,22 +608,19 @@
+ */
+
+ /* These assignments are simply vals without bits set in avals*/
+- sier = fsl_ssi_disable_val(vals->sier, avals->sier,
+- keep_active);
+- srcr = fsl_ssi_disable_val(vals->srcr, avals->srcr,
+- keep_active);
+- stcr = fsl_ssi_disable_val(vals->stcr, avals->stcr,
+- keep_active);
+-
+- regmap_update_bits(regs, CCSR_SSI_SRCR, srcr, 0);
+- regmap_update_bits(regs, CCSR_SSI_STCR, stcr, 0);
+- regmap_update_bits(regs, CCSR_SSI_SIER, sier, 0);
++ sier = vals->sier & (vals->sier ^ avals->sier);
++ srcr = vals->srcr & (vals->srcr ^ avals->srcr);
++ stcr = vals->stcr & (vals->stcr ^ avals->stcr);
++
++ write_ssi_mask(&ssi->srcr, srcr, 0);
++ write_ssi_mask(&ssi->stcr, stcr, 0);
++ write_ssi_mask(&ssi->sier, sier, 0);
+ }
+
+ config_done:
+ /* Enabling of subunits is done after configuration */
+ if (enable)
+- regmap_update_bits(regs, CCSR_SSI_SCR, vals->scr, vals->scr);
++ write_ssi_mask(&ssi->scr, 0, vals->scr);
+ }
+
+
+@@ -465,7 +650,7 @@
+ reg->tx.stcr = CCSR_SSI_STCR_TFEN0;
+ reg->tx.scr = 0;
+
+- if (!fsl_ssi_is_ac97(ssi_private)) {
++ if (!ssi_private->imx_ac97) {
+ reg->rx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE;
+ reg->rx.sier |= CCSR_SSI_SIER_RFF0_EN;
+ reg->tx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE;
+@@ -486,197 +671,161 @@
+
+ static void fsl_ssi_setup_ac97(struct fsl_ssi_private *ssi_private)
+ {
+- struct regmap *regs = ssi_private->regs;
++ struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
+
+ /*
+ * Setup the clock control register
+ */
+- regmap_write(regs, CCSR_SSI_STCCR,
+- CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13));
+- regmap_write(regs, CCSR_SSI_SRCCR,
+- CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13));
++ write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13),
++ &ssi->stccr);
++ write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13),
++ &ssi->srccr);
+
+ /*
+ * Enable AC97 mode and startup the SSI
+ */
+- regmap_write(regs, CCSR_SSI_SACNT,
+- CCSR_SSI_SACNT_AC97EN | CCSR_SSI_SACNT_FV);
+- regmap_write(regs, CCSR_SSI_SACCDIS, 0xff);
+- regmap_write(regs, CCSR_SSI_SACCEN, 0x300);
++ write_ssi(CCSR_SSI_SACNT_AC97EN | CCSR_SSI_SACNT_FV,
++ &ssi->sacnt);
++ write_ssi(0xff, &ssi->saccdis);
++ write_ssi(0x300, &ssi->saccen);
+
+ /*
+ * Enable SSI, Transmit and Receive. AC97 has to communicate with the
+ * codec before a stream is started.
+ */
+- regmap_update_bits(regs, CCSR_SSI_SCR,
+- CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE,
+- CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE);
+-
+- regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_WAIT(3));
+-}
+-
+-/**
+- * fsl_ssi_startup: create a new substream
+- *
+- * This is the first function called when a stream is opened.
+- *
+- * If this is the first stream open, then grab the IRQ and program most of
+- * the SSI registers.
+- */
+-static int fsl_ssi_startup(struct snd_pcm_substream *substream,
+- struct snd_soc_dai *dai)
+-{
+- struct snd_soc_pcm_runtime *rtd = substream->private_data;
+- struct fsl_ssi_private *ssi_private =
+- snd_soc_dai_get_drvdata(rtd->cpu_dai);
+- int ret;
+-
+- ret = clk_prepare_enable(ssi_private->clk);
+- if (ret)
+- return ret;
+-
+- /* When using dual fifo mode, it is safer to ensure an even period
+- * size. If appearing to an odd number while DMA always starts its
+- * task from fifo0, fifo1 would be neglected at the end of each
+- * period. But SSI would still access fifo1 with an invalid data.
+- */
+- if (ssi_private->use_dual_fifo)
+- snd_pcm_hw_constraint_step(substream->runtime, 0,
+- SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
++ write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_SSIEN |
++ CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE);
+
+- return 0;
++ write_ssi(CCSR_SSI_SOR_WAIT(3), &ssi->sor);
+ }
+
+-/**
+- * fsl_ssi_shutdown: shutdown the SSI
+- *
+- */
+-static void fsl_ssi_shutdown(struct snd_pcm_substream *substream,
+- struct snd_soc_dai *dai)
++static int fsl_ssi_setup(struct fsl_ssi_private *ssi_private)
+ {
+- struct snd_soc_pcm_runtime *rtd = substream->private_data;
+- struct fsl_ssi_private *ssi_private =
+- snd_soc_dai_get_drvdata(rtd->cpu_dai);
+-
+- clk_disable_unprepare(ssi_private->clk);
+-
+-}
++ struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
++ u8 wm;
++ int synchronous = ssi_private->cpu_dai_drv.symmetric_rates;
+
+-/**
+- * fsl_ssi_set_bclk - configure Digital Audio Interface bit clock
+- *
+- * Note: This function can be only called when using SSI as DAI master
+- *
+- * Quick instruction for parameters:
+- * freq: Output BCLK frequency = samplerate * 32 (fixed) * channels
+- * dir: SND_SOC_CLOCK_OUT -> TxBCLK, SND_SOC_CLOCK_IN -> RxBCLK.
+- */
+-static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream,
+- struct snd_soc_dai *cpu_dai,
+- struct snd_pcm_hw_params *hw_params)
+-{
+- struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
+- struct regmap *regs = ssi_private->regs;
+- int synchronous = ssi_private->cpu_dai_drv.symmetric_rates, ret;
+- u32 pm = 999, div2, psr, stccr, mask, afreq, factor, i;
+- unsigned long clkrate, baudrate, tmprate;
+- u64 sub, savesub = 100000;
+- unsigned int freq;
+- bool baudclk_is_used;
++ fsl_ssi_setup_reg_vals(ssi_private);
+
+- /* Prefer the explicitly set bitclock frequency */
+- if (ssi_private->bitclk_freq)
+- freq = ssi_private->bitclk_freq;
++ if (ssi_private->imx_ac97)
++ ssi_private->i2s_mode = CCSR_SSI_SCR_I2S_MODE_NORMAL | CCSR_SSI_SCR_NET;
+ else
+- freq = params_channels(hw_params) * 32 * params_rate(hw_params);
+-
+- /* Don't apply it to any non-baudclk circumstance */
+- if (IS_ERR(ssi_private->baudclk))
+- return -EINVAL;
+-
+- baudclk_is_used = ssi_private->baudclk_streams & ~(BIT(substream->stream));
++ ssi_private->i2s_mode = CCSR_SSI_SCR_I2S_MODE_SLAVE;
+
+- /* It should be already enough to divide clock by setting pm alone */
+- psr = 0;
+- div2 = 0;
+-
+- factor = (div2 + 1) * (7 * psr + 1) * 2;
++ /*
++ * Section 16.5 of the MPC8610 reference manual says that the SSI needs
++ * to be disabled before updating the registers we set here.
++ */
++ write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, 0);
+
+- for (i = 0; i < 255; i++) {
+- tmprate = freq * factor * (i + 1);
++ /*
++ * Program the SSI into I2S Slave Non-Network Synchronous mode. Also
++ * enable the transmit and receive FIFO.
++ *
++ * FIXME: Little-endian samples require a different shift dir
++ */
++ write_ssi_mask(&ssi->scr,
++ CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_SYN,
++ CCSR_SSI_SCR_TFR_CLK_DIS |
++ ssi_private->i2s_mode |
++ (synchronous ? CCSR_SSI_SCR_SYN : 0));
+
+- if (baudclk_is_used)
+- clkrate = clk_get_rate(ssi_private->baudclk);
+- else
+- clkrate = clk_round_rate(ssi_private->baudclk, tmprate);
++ write_ssi(CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFSI |
++ CCSR_SSI_STCR_TEFS | CCSR_SSI_STCR_TSCKP, &ssi->stcr);
+
+- /*
+- * Hardware limitation: The bclk rate must be
+- * never greater than 1/5 IPG clock rate
+- */
+- if (clkrate * 5 > clk_get_rate(ssi_private->clk))
+- continue;
++ write_ssi(CCSR_SSI_SRCR_RXBIT0 | CCSR_SSI_SRCR_RFSI |
++ CCSR_SSI_SRCR_REFS | CCSR_SSI_SRCR_RSCKP, &ssi->srcr);
+
+- clkrate /= factor;
+- afreq = clkrate / (i + 1);
++ /*
++ * The DC and PM bits are only used if the SSI is the clock master.
++ */
+
+- if (freq == afreq)
+- sub = 0;
+- else if (freq / afreq == 1)
+- sub = freq - afreq;
+- else if (afreq / freq == 1)
+- sub = afreq - freq;
+- else
+- continue;
++ /*
++ * Set the watermark for transmit FIFI 0 and receive FIFO 0. We don't
++ * use FIFO 1. We program the transmit water to signal a DMA transfer
++ * if there are only two (or fewer) elements left in the FIFO. Two
++ * elements equals one frame (left channel, right channel). This value,
++ * however, depends on the depth of the transmit buffer.
++ *
++ * We set the watermark on the same level as the DMA burstsize. For
++ * fiq it is probably better to use the biggest possible watermark
++ * size.
++ */
++ if (ssi_private->use_dma)
++ wm = ssi_private->fifo_depth - 2;
++ else
++ wm = ssi_private->fifo_depth;
+
+- /* Calculate the fraction */
+- sub *= 100000;
+- do_div(sub, freq);
++ write_ssi(CCSR_SSI_SFCSR_TFWM0(wm) | CCSR_SSI_SFCSR_RFWM0(wm) |
++ CCSR_SSI_SFCSR_TFWM1(wm) | CCSR_SSI_SFCSR_RFWM1(wm),
++ &ssi->sfcsr);
+
+- if (sub < savesub) {
+- baudrate = tmprate;
+- savesub = sub;
+- pm = i;
+- }
++ /*
++ * For ac97 interrupts are enabled with the startup of the substream
++ * because it is also running without an active substream. Normally SSI
++ * is only enabled when there is a substream.
++ */
++ if (ssi_private->imx_ac97)
++ fsl_ssi_setup_ac97(ssi_private);
+
+- /* We are lucky */
+- if (savesub == 0)
+- break;
++ /*
++ * Set a default slot number so that there is no need for those common
++ * cases like I2S mode to call the extra set_tdm_slot() any more.
++ */
++ if (!ssi_private->imx_ac97) {
++ write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_DC_MASK,
++ CCSR_SSI_SxCCR_DC(2));
++ write_ssi_mask(&ssi->srccr, CCSR_SSI_SxCCR_DC_MASK,
++ CCSR_SSI_SxCCR_DC(2));
+ }
+
+- /* No proper pm found if it is still remaining the initial value */
+- if (pm == 999) {
+- dev_err(cpu_dai->dev, "failed to handle the required sysclk\n");
+- return -EINVAL;
++ if (ssi_private->use_dual_fifo) {
++ write_ssi_mask(&ssi->srcr, 0, CCSR_SSI_SRCR_RFEN1);
++ write_ssi_mask(&ssi->stcr, 0, CCSR_SSI_STCR_TFEN1);
++ write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_TCH_EN);
+ }
+
+- stccr = CCSR_SSI_SxCCR_PM(pm + 1) | (div2 ? CCSR_SSI_SxCCR_DIV2 : 0) |
+- (psr ? CCSR_SSI_SxCCR_PSR : 0);
+- mask = CCSR_SSI_SxCCR_PM_MASK | CCSR_SSI_SxCCR_DIV2 |
+- CCSR_SSI_SxCCR_PSR;
++ return 0;
++}
+
+- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || synchronous)
+- regmap_update_bits(regs, CCSR_SSI_STCCR, mask, stccr);
+- else
+- regmap_update_bits(regs, CCSR_SSI_SRCCR, mask, stccr);
+
+- if (!baudclk_is_used) {
+- ret = clk_set_rate(ssi_private->baudclk, baudrate);
+- if (ret) {
+- dev_err(cpu_dai->dev, "failed to set baudclk rate\n");
+- return -EINVAL;
+- }
+- }
++/**
++ * fsl_ssi_startup: create a new substream
++ *
++ * This is the first function called when a stream is opened.
++ *
++ * If this is the first stream open, then grab the IRQ and program most of
++ * the SSI registers.
++ */
++static int fsl_ssi_startup(struct snd_pcm_substream *substream,
++ struct snd_soc_dai *dai)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct fsl_ssi_private *ssi_private =
++ snd_soc_dai_get_drvdata(rtd->cpu_dai);
++ unsigned long flags;
+
+- return 0;
+-}
++ pm_runtime_get_sync(dai->dev);
+
+-static int fsl_ssi_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
+- int clk_id, unsigned int freq, int dir)
+-{
+- struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
++ /* First, we only do fsl_ssi_setup() when SSI is going to be active.
++ * Second, fsl_ssi_setup was already called by ac97_init earlier if
++ * the driver is in ac97 mode.
++ */
++ if (!dai->active && !ssi_private->imx_ac97) {
++ fsl_ssi_setup(ssi_private);
++ spin_lock_irqsave(&ssi_private->baudclk_lock, flags);
++ ssi_private->baudclk_locked = false;
++ spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags);
++ }
+
+- ssi_private->bitclk_freq = freq;
++ /* When using dual fifo mode, it is safer to ensure an even period
++ * size. If appearing to an odd number while DMA always starts its
++ * task from fifo0, fifo1 would be neglected at the end of each
++ * period. But SSI would still access fifo1 with an invalid data.
++ */
++ if (ssi_private->use_dual_fifo)
++ snd_pcm_hw_constraint_step(substream->runtime, 0,
++ SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
+
+ return 0;
+ }
+@@ -698,17 +847,12 @@
+ struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *cpu_dai)
+ {
+ struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
+- struct regmap *regs = ssi_private->regs;
++ struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
+ unsigned int channels = params_channels(hw_params);
+ unsigned int sample_size =
+ snd_pcm_format_width(params_format(hw_params));
+ u32 wl = CCSR_SSI_SxCCR_WL(sample_size);
+- int ret;
+- u32 scr_val;
+- int enabled;
+-
+- regmap_read(regs, CCSR_SSI_SCR, &scr_val);
+- enabled = scr_val & CCSR_SSI_SCR_SSIEN;
++ int enabled = read_ssi(&ssi->scr) & CCSR_SSI_SCR_SSIEN;
+
+ /*
+ * If we're in synchronous mode, and the SSI is already enabled,
+@@ -717,38 +861,6 @@
+ if (enabled && ssi_private->cpu_dai_drv.symmetric_rates)
+ return 0;
+
+- if (fsl_ssi_is_i2s_master(ssi_private)) {
+- ret = fsl_ssi_set_bclk(substream, cpu_dai, hw_params);
+- if (ret)
+- return ret;
+-
+- /* Do not enable the clock if it is already enabled */
+- if (!(ssi_private->baudclk_streams & BIT(substream->stream))) {
+- ret = clk_prepare_enable(ssi_private->baudclk);
+- if (ret)
+- return ret;
+-
+- ssi_private->baudclk_streams |= BIT(substream->stream);
+- }
+- }
+-
+- if (!fsl_ssi_is_ac97(ssi_private)) {
+- u8 i2smode;
+- /*
+- * Switch to normal net mode in order to have a frame sync
+- * signal every 32 bits instead of 16 bits
+- */
+- if (fsl_ssi_is_i2s_cbm_cfs(ssi_private) && sample_size == 16)
+- i2smode = CCSR_SSI_SCR_I2S_MODE_NORMAL |
+- CCSR_SSI_SCR_NET;
+- else
+- i2smode = ssi_private->i2s_mode;
+-
+- regmap_update_bits(regs, CCSR_SSI_SCR,
+- CCSR_SSI_SCR_NET | CCSR_SSI_SCR_I2S_MODE_MASK,
+- channels == 1 ? 0 : i2smode);
+- }
+-
+ /*
+ * FIXME: The documentation says that SxCCR[WL] should not be
+ * modified while the SSI is enabled. The only time this can
+@@ -762,80 +874,49 @@
+ /* In synchronous mode, the SSI uses STCCR for capture */
+ if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ||
+ ssi_private->cpu_dai_drv.symmetric_rates)
+- regmap_update_bits(regs, CCSR_SSI_STCCR, CCSR_SSI_SxCCR_WL_MASK,
+- wl);
++ write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_WL_MASK, wl);
+ else
+- regmap_update_bits(regs, CCSR_SSI_SRCCR, CCSR_SSI_SxCCR_WL_MASK,
+- wl);
++ write_ssi_mask(&ssi->srccr, CCSR_SSI_SxCCR_WL_MASK, wl);
+
+- return 0;
+-}
+-
+-static int fsl_ssi_hw_free(struct snd_pcm_substream *substream,
+- struct snd_soc_dai *cpu_dai)
+-{
+- struct snd_soc_pcm_runtime *rtd = substream->private_data;
+- struct fsl_ssi_private *ssi_private =
+- snd_soc_dai_get_drvdata(rtd->cpu_dai);
+-
+- if (fsl_ssi_is_i2s_master(ssi_private) &&
+- ssi_private->baudclk_streams & BIT(substream->stream)) {
+- clk_disable_unprepare(ssi_private->baudclk);
+- ssi_private->baudclk_streams &= ~BIT(substream->stream);
+- }
++ if (!ssi_private->imx_ac97)
++ write_ssi_mask(&ssi->scr,
++ CCSR_SSI_SCR_NET | CCSR_SSI_SCR_I2S_MODE_MASK,
++ channels == 1 ? 0 : ssi_private->i2s_mode);
+
+ return 0;
+ }
+
+-static int _fsl_ssi_set_dai_fmt(struct device *dev,
+- struct fsl_ssi_private *ssi_private,
+- unsigned int fmt)
++/**
++ * fsl_ssi_set_dai_fmt - configure Digital Audio Interface Format.
++ */
++static int fsl_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
+ {
+- struct regmap *regs = ssi_private->regs;
++ struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
++ struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
+ u32 strcr = 0, stcr, srcr, scr, mask;
+- u8 wm;
+
+- ssi_private->dai_fmt = fmt;
+-
+- if (fsl_ssi_is_i2s_master(ssi_private) && IS_ERR(ssi_private->baudclk)) {
+- dev_err(dev, "baudclk is missing which is necessary for master mode\n");
+- return -EINVAL;
+- }
+-
+- fsl_ssi_setup_reg_vals(ssi_private);
+-
+- regmap_read(regs, CCSR_SSI_SCR, &scr);
+- scr &= ~(CCSR_SSI_SCR_SYN | CCSR_SSI_SCR_I2S_MODE_MASK);
+- scr |= CCSR_SSI_SCR_SYNC_TX_FS;
++ scr = read_ssi(&ssi->scr) & ~(CCSR_SSI_SCR_SYN | CCSR_SSI_SCR_I2S_MODE_MASK);
++ scr |= CCSR_SSI_SCR_NET;
+
+ mask = CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR |
+ CCSR_SSI_STCR_TSCKP | CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TFSL |
+ CCSR_SSI_STCR_TEFS;
+- regmap_read(regs, CCSR_SSI_STCR, &stcr);
+- regmap_read(regs, CCSR_SSI_SRCR, &srcr);
+- stcr &= ~mask;
+- srcr &= ~mask;
++ stcr = read_ssi(&ssi->stcr) & ~mask;
++ srcr = read_ssi(&ssi->srcr) & ~mask;
+
+- ssi_private->i2s_mode = CCSR_SSI_SCR_NET;
+ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+ case SND_SOC_DAIFMT_I2S:
+ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+- case SND_SOC_DAIFMT_CBM_CFS:
+ case SND_SOC_DAIFMT_CBS_CFS:
+- ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_MASTER;
+- regmap_update_bits(regs, CCSR_SSI_STCCR,
+- CCSR_SSI_SxCCR_DC_MASK,
+- CCSR_SSI_SxCCR_DC(2));
+- regmap_update_bits(regs, CCSR_SSI_SRCCR,
+- CCSR_SSI_SxCCR_DC_MASK,
+- CCSR_SSI_SxCCR_DC(2));
++ ssi_private->i2s_mode = CCSR_SSI_SCR_I2S_MODE_MASTER;
+ break;
+ case SND_SOC_DAIFMT_CBM_CFM:
+- ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_SLAVE;
++ ssi_private->i2s_mode = CCSR_SSI_SCR_I2S_MODE_SLAVE;
+ break;
+ default:
+ return -EINVAL;
+ }
++ scr |= ssi_private->i2s_mode;
+
+ /* Data on rising edge of bclk, frame low, 1clk before data */
+ strcr |= CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TSCKP |
+@@ -855,13 +936,9 @@
+ strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP |
+ CCSR_SSI_STCR_TXBIT0;
+ break;
+- case SND_SOC_DAIFMT_AC97:
+- ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_NORMAL;
+- break;
+ default:
+ return -EINVAL;
+ }
+- scr |= ssi_private->i2s_mode;
+
+ /* DAI clock inversion */
+ switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
+@@ -894,11 +971,6 @@
+ case SND_SOC_DAIFMT_CBM_CFM:
+ scr &= ~CCSR_SSI_SCR_SYS_CLK_EN;
+ break;
+- case SND_SOC_DAIFMT_CBM_CFS:
+- strcr &= ~CCSR_SSI_STCR_TXDIR;
+- strcr |= CCSR_SSI_STCR_TFDIR;
+- scr &= ~CCSR_SSI_SCR_SYS_CLK_EN;
+- break;
+ default:
+ return -EINVAL;
+ }
+@@ -912,54 +984,105 @@
+ scr |= CCSR_SSI_SCR_SYN;
+ }
+
+- regmap_write(regs, CCSR_SSI_STCR, stcr);
+- regmap_write(regs, CCSR_SSI_SRCR, srcr);
+- regmap_write(regs, CCSR_SSI_SCR, scr);
+-
+- /*
+- * Set the watermark for transmit FIFI 0 and receive FIFO 0. We don't
+- * use FIFO 1. We program the transmit water to signal a DMA transfer
+- * if there are only two (or fewer) elements left in the FIFO. Two
+- * elements equals one frame (left channel, right channel). This value,
+- * however, depends on the depth of the transmit buffer.
+- *
+- * We set the watermark on the same level as the DMA burstsize. For
+- * fiq it is probably better to use the biggest possible watermark
+- * size.
+- */
+- if (ssi_private->use_dma)
+- wm = ssi_private->fifo_depth - 2;
+- else
+- wm = ssi_private->fifo_depth;
+-
+- regmap_write(regs, CCSR_SSI_SFCSR,
+- CCSR_SSI_SFCSR_TFWM0(wm) | CCSR_SSI_SFCSR_RFWM0(wm) |
+- CCSR_SSI_SFCSR_TFWM1(wm) | CCSR_SSI_SFCSR_RFWM1(wm));
+-
+- if (ssi_private->use_dual_fifo) {
+- regmap_update_bits(regs, CCSR_SSI_SRCR, CCSR_SSI_SRCR_RFEN1,
+- CCSR_SSI_SRCR_RFEN1);
+- regmap_update_bits(regs, CCSR_SSI_STCR, CCSR_SSI_STCR_TFEN1,
+- CCSR_SSI_STCR_TFEN1);
+- regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_TCH_EN,
+- CCSR_SSI_SCR_TCH_EN);
+- }
+-
+- if (fmt & SND_SOC_DAIFMT_AC97)
+- fsl_ssi_setup_ac97(ssi_private);
++ write_ssi(stcr, &ssi->stcr);
++ write_ssi(srcr, &ssi->srcr);
++ write_ssi(scr, &ssi->scr);
+
+ return 0;
+-
+ }
+
+ /**
+- * fsl_ssi_set_dai_fmt - configure Digital Audio Interface Format.
++ * fsl_ssi_set_dai_sysclk - configure Digital Audio Interface bit clock
++ *
++ * Note: This function can be only called when using SSI as DAI master
++ *
++ * Quick instruction for parameters:
++ * freq: Output BCLK frequency = samplerate * 32 (fixed) * channels
++ * dir: SND_SOC_CLOCK_OUT -> TxBCLK, SND_SOC_CLOCK_IN -> RxBCLK.
+ */
+-static int fsl_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
++static int fsl_ssi_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
++ int clk_id, unsigned int freq, int dir)
+ {
+ struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
++ struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
++ int synchronous = ssi_private->cpu_dai_drv.symmetric_rates, ret;
++ u32 pm = 999, div2, psr, stccr, mask, afreq, factor, i;
++ unsigned long flags, clkrate, baudrate, tmprate;
++ u64 sub, savesub = 100000;
++
++ /* Don't apply it to any non-baudclk circumstance */
++ if (IS_ERR(ssi_private->baudclk))
++ return -EINVAL;
++
++ /* It should be already enough to divide clock by setting pm alone */
++ psr = 0;
++ div2 = 0;
++
++ factor = (div2 + 1) * (7 * psr + 1) * 2;
++
++ for (i = 0; i < 255; i++) {
++ /* The bclk rate must be smaller than 1/5 sysclk rate */
++ if (factor * (i + 1) < 5)
++ continue;
++
++ tmprate = freq * factor * (i + 2);
++ clkrate = clk_round_rate(ssi_private->baudclk, tmprate);
++
++ do_div(clkrate, factor);
++ afreq = (u32)clkrate / (i + 1);
++
++ if (freq == afreq)
++ sub = 0;
++ else if (freq / afreq == 1)
++ sub = freq - afreq;
++ else if (afreq / freq == 1)
++ sub = afreq - freq;
++ else
++ continue;
++
++ /* Calculate the fraction */
++ sub *= 100000;
++ do_div(sub, freq);
++
++ if (sub < savesub) {
++ baudrate = tmprate;
++ savesub = sub;
++ pm = i;
++ }
++
++ /* We are lucky */
++ if (savesub == 0)
++ break;
++ }
++
++ /* No proper pm found if it is still remaining the initial value */
++ if (pm == 999) {
++ dev_err(cpu_dai->dev, "failed to handle the required sysclk\n");
++ return -EINVAL;
++ }
++
++ stccr = CCSR_SSI_SxCCR_PM(pm + 1) | (div2 ? CCSR_SSI_SxCCR_DIV2 : 0) |
++ (psr ? CCSR_SSI_SxCCR_PSR : 0);
++ mask = CCSR_SSI_SxCCR_PM_MASK | CCSR_SSI_SxCCR_DIV2 | CCSR_SSI_SxCCR_PSR;
++
++ if (dir == SND_SOC_CLOCK_OUT || synchronous)
++ write_ssi_mask(&ssi->stccr, mask, stccr);
++ else
++ write_ssi_mask(&ssi->srccr, mask, stccr);
++
++ spin_lock_irqsave(&ssi_private->baudclk_lock, flags);
++ if (!ssi_private->baudclk_locked) {
++ ret = clk_set_rate(ssi_private->baudclk, baudrate);
++ if (ret) {
++ spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags);
++ dev_err(cpu_dai->dev, "failed to set baudclk rate\n");
++ return -EINVAL;
++ }
++ ssi_private->baudclk_locked = true;
++ }
++ spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags);
+
+- return _fsl_ssi_set_dai_fmt(cpu_dai->dev, ssi_private, fmt);
++ return 0;
+ }
+
+ /**
+@@ -971,34 +1094,31 @@
+ u32 rx_mask, int slots, int slot_width)
+ {
+ struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
+- struct regmap *regs = ssi_private->regs;
++ struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
+ u32 val;
+
+ /* The slot number should be >= 2 if using Network mode or I2S mode */
+- regmap_read(regs, CCSR_SSI_SCR, &val);
+- val &= CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_NET;
++ val = read_ssi(&ssi->scr) & (CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_NET);
+ if (val && slots < 2) {
+ dev_err(cpu_dai->dev, "slot number should be >= 2 in I2S or NET\n");
+ return -EINVAL;
+ }
+
+- regmap_update_bits(regs, CCSR_SSI_STCCR, CCSR_SSI_SxCCR_DC_MASK,
++ write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_DC_MASK,
+ CCSR_SSI_SxCCR_DC(slots));
+- regmap_update_bits(regs, CCSR_SSI_SRCCR, CCSR_SSI_SxCCR_DC_MASK,
++ write_ssi_mask(&ssi->srccr, CCSR_SSI_SxCCR_DC_MASK,
+ CCSR_SSI_SxCCR_DC(slots));
+
+ /* The register SxMSKs needs SSI to provide essential clock due to
+ * hardware design. So we here temporarily enable SSI to set them.
+ */
+- regmap_read(regs, CCSR_SSI_SCR, &val);
+- val &= CCSR_SSI_SCR_SSIEN;
+- regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_SSIEN,
+- CCSR_SSI_SCR_SSIEN);
++ val = read_ssi(&ssi->scr) & CCSR_SSI_SCR_SSIEN;
++ write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_SSIEN);
+
+- regmap_write(regs, CCSR_SSI_STMSK, ~tx_mask);
+- regmap_write(regs, CCSR_SSI_SRMSK, ~rx_mask);
++ write_ssi(tx_mask, &ssi->stmsk);
++ write_ssi(rx_mask, &ssi->srmsk);
+
+- regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_SSIEN, val);
++ write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, val);
+
+ return 0;
+ }
+@@ -1017,7 +1137,8 @@
+ {
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai);
+- struct regmap *regs = ssi_private->regs;
++ struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
++ unsigned long flags;
+
+ switch (cmd) {
+ case SNDRV_PCM_TRIGGER_START:
+@@ -1027,6 +1148,7 @@
+ fsl_ssi_tx_config(ssi_private, true);
+ else
+ fsl_ssi_rx_config(ssi_private, true);
++ dump_reg(ssi);
+ break;
+
+ case SNDRV_PCM_TRIGGER_STOP:
+@@ -1036,27 +1158,40 @@
+ fsl_ssi_tx_config(ssi_private, false);
+ else
+ fsl_ssi_rx_config(ssi_private, false);
++
++ if (!ssi_private->imx_ac97 && (read_ssi(&ssi->scr) &
++ (CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE)) == 0) {
++ spin_lock_irqsave(&ssi_private->baudclk_lock, flags);
++ ssi_private->baudclk_locked = false;
++ spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags);
++ }
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+- if (fsl_ssi_is_ac97(ssi_private)) {
++ if (ssi_private->imx_ac97) {
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+- regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_TX_CLR);
++ write_ssi(CCSR_SSI_SOR_TX_CLR, &ssi->sor);
+ else
+- regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_RX_CLR);
++ write_ssi(CCSR_SSI_SOR_RX_CLR, &ssi->sor);
+ }
+
+ return 0;
+ }
+
++static void fsl_ssi_shutdown(struct snd_pcm_substream *substream,
++ struct snd_soc_dai *dai)
++{
++ pm_runtime_put_sync(dai->dev);
++}
++
+ static int fsl_ssi_dai_probe(struct snd_soc_dai *dai)
+ {
+ struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(dai);
+
+- if (ssi_private->soc->imx && ssi_private->use_dma) {
++ if (ssi_private->ssi_on_imx && ssi_private->use_dma) {
+ dai->playback_dma_data = &ssi_private->dma_params_tx;
+ dai->capture_dma_data = &ssi_private->dma_params_rx;
+ }
+@@ -1066,27 +1201,24 @@
+
+ static const struct snd_soc_dai_ops fsl_ssi_dai_ops = {
+ .startup = fsl_ssi_startup,
+- .shutdown = fsl_ssi_shutdown,
+ .hw_params = fsl_ssi_hw_params,
+- .hw_free = fsl_ssi_hw_free,
+ .set_fmt = fsl_ssi_set_dai_fmt,
+ .set_sysclk = fsl_ssi_set_dai_sysclk,
+ .set_tdm_slot = fsl_ssi_set_dai_tdm_slot,
+ .trigger = fsl_ssi_trigger,
++ .shutdown = fsl_ssi_shutdown,
+ };
+
+ /* Template for the CPU dai driver structure */
+ static struct snd_soc_dai_driver fsl_ssi_dai_template = {
+ .probe = fsl_ssi_dai_probe,
+ .playback = {
+- .stream_name = "CPU-Playback",
+ .channels_min = 1,
+ .channels_max = 2,
+ .rates = FSLSSI_I2S_RATES,
+ .formats = FSLSSI_I2S_FORMATS,
+ },
+ .capture = {
+- .stream_name = "CPU-Capture",
+ .channels_min = 1,
+ .channels_max = 2,
+ .rates = FSLSSI_I2S_RATES,
+@@ -1100,7 +1232,7 @@
+ };
+
+ static struct snd_soc_dai_driver fsl_ssi_ac97_dai = {
+- .bus_control = true,
++// .ac97_control = 1,
+ .playback = {
+ .stream_name = "AC97 Playback",
+ .channels_min = 2,
+@@ -1121,10 +1253,15 @@
+
+ static struct fsl_ssi_private *fsl_ac97_data;
+
++static void fsl_ssi_ac97_init(void)
++{
++ fsl_ssi_setup(fsl_ac97_data);
++}
++
+ static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
+ unsigned short val)
+ {
+- struct regmap *regs = fsl_ac97_data->regs;
++ struct ccsr_ssi *ssi = fsl_ac97_data->ssi;
+ unsigned int lreg;
+ unsigned int lval;
+
+@@ -1133,12 +1270,12 @@
+
+
+ lreg = reg << 12;
+- regmap_write(regs, CCSR_SSI_SACADD, lreg);
++ write_ssi(lreg, &ssi->sacadd);
+
+ lval = val << 4;
+- regmap_write(regs, CCSR_SSI_SACDAT, lval);
++ write_ssi(lval , &ssi->sacdat);
+
+- regmap_update_bits(regs, CCSR_SSI_SACNT, CCSR_SSI_SACNT_RDWR_MASK,
++ write_ssi_mask(&ssi->sacnt, CCSR_SSI_SACNT_RDWR_MASK,
+ CCSR_SSI_SACNT_WR);
+ udelay(100);
+ }
+@@ -1146,21 +1283,19 @@
+ static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97,
+ unsigned short reg)
+ {
+- struct regmap *regs = fsl_ac97_data->regs;
++ struct ccsr_ssi *ssi = fsl_ac97_data->ssi;
+
+ unsigned short val = -1;
+- u32 reg_val;
+ unsigned int lreg;
+
+ lreg = (reg & 0x7f) << 12;
+- regmap_write(regs, CCSR_SSI_SACADD, lreg);
+- regmap_update_bits(regs, CCSR_SSI_SACNT, CCSR_SSI_SACNT_RDWR_MASK,
++ write_ssi(lreg, &ssi->sacadd);
++ write_ssi_mask(&ssi->sacnt, CCSR_SSI_SACNT_RDWR_MASK,
+ CCSR_SSI_SACNT_RD);
+
+ udelay(100);
+
+- regmap_read(regs, CCSR_SSI_SACDAT, &reg_val);
+- val = (reg_val >> 4) & 0xffff;
++ val = (read_ssi(&ssi->sacdat) >> 4) & 0xffff;
+
+ return val;
+ }
+@@ -1185,112 +1320,20 @@
+ }
+ }
+
+-static int fsl_ssi_imx_probe(struct platform_device *pdev,
+- struct fsl_ssi_private *ssi_private, void __iomem *iomem)
+-{
+- struct device_node *np = pdev->dev.of_node;
+- u32 dmas[4];
+- int ret;
+-
+- if (ssi_private->has_ipg_clk_name)
+- ssi_private->clk = devm_clk_get(&pdev->dev, "ipg");
+- else
+- ssi_private->clk = devm_clk_get(&pdev->dev, NULL);
+- if (IS_ERR(ssi_private->clk)) {
+- ret = PTR_ERR(ssi_private->clk);
+- dev_err(&pdev->dev, "could not get clock: %d\n", ret);
+- return ret;
+- }
+-
+- if (!ssi_private->has_ipg_clk_name) {
+- ret = clk_prepare_enable(ssi_private->clk);
+- if (ret) {
+- dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret);
+- return ret;
+- }
+- }
+-
+- /* For those SLAVE implementations, we ingore non-baudclk cases
+- * and, instead, abandon MASTER mode that needs baud clock.
+- */
+- ssi_private->baudclk = devm_clk_get(&pdev->dev, "baud");
+- if (IS_ERR(ssi_private->baudclk))
+- dev_dbg(&pdev->dev, "could not get baud clock: %ld\n",
+- PTR_ERR(ssi_private->baudclk));
+-
+- /*
+- * We have burstsize be "fifo_depth - 2" to match the SSI
+- * watermark setting in fsl_ssi_startup().
+- */
+- ssi_private->dma_params_tx.maxburst = ssi_private->fifo_depth - 2;
+- ssi_private->dma_params_rx.maxburst = ssi_private->fifo_depth - 2;
+- ssi_private->dma_params_tx.addr = ssi_private->ssi_phys + CCSR_SSI_STX0;
+- ssi_private->dma_params_rx.addr = ssi_private->ssi_phys + CCSR_SSI_SRX0;
+-
+- ret = of_property_read_u32_array(np, "dmas", dmas, 4);
+- if (ssi_private->use_dma && !ret && dmas[2] == IMX_DMATYPE_SSI_DUAL) {
+- ssi_private->use_dual_fifo = true;
+- /* When using dual fifo mode, we need to keep watermark
+- * as even numbers due to dma script limitation.
+- */
+- ssi_private->dma_params_tx.maxburst &= ~0x1;
+- ssi_private->dma_params_rx.maxburst &= ~0x1;
+- }
+-
+- if (!ssi_private->use_dma) {
+-
+- /*
+- * Some boards use an incompatible codec. To get it
+- * working, we are using imx-fiq-pcm-audio, that
+- * can handle those codecs. DMA is not possible in this
+- * situation.
+- */
+-
+- ssi_private->fiq_params.irq = ssi_private->irq;
+- ssi_private->fiq_params.base = iomem;
+- ssi_private->fiq_params.dma_params_rx =
+- &ssi_private->dma_params_rx;
+- ssi_private->fiq_params.dma_params_tx =
+- &ssi_private->dma_params_tx;
+-
+- ret = imx_pcm_fiq_init(pdev, &ssi_private->fiq_params);
+- if (ret)
+- goto error_pcm;
+- } else {
+- ret = imx_pcm_dma_init(pdev);
+- if (ret)
+- goto error_pcm;
+- }
+-
+- return 0;
+-
+-error_pcm:
+-
+- if (!ssi_private->has_ipg_clk_name)
+- clk_disable_unprepare(ssi_private->clk);
+- return ret;
+-}
+-
+-static void fsl_ssi_imx_clean(struct platform_device *pdev,
+- struct fsl_ssi_private *ssi_private)
+-{
+- if (!ssi_private->use_dma)
+- imx_pcm_fiq_exit(pdev);
+- if (!ssi_private->has_ipg_clk_name)
+- clk_disable_unprepare(ssi_private->clk);
+-}
+-
+ static int fsl_ssi_probe(struct platform_device *pdev)
+ {
+ struct fsl_ssi_private *ssi_private;
+ int ret = 0;
++ struct device_attribute *dev_attr = NULL;
+ struct device_node *np = pdev->dev.of_node;
++ u32 dmas[4];
+ const struct of_device_id *of_id;
++ enum fsl_ssi_type hw_type;
+ const char *p, *sprop;
+ const uint32_t *iprop;
+- struct resource *res;
+- void __iomem *iomem;
++ struct resource res;
+ char name[64];
++ bool ac97 = false;
+
+ /* SSIs that are not connected on the board should have a
+ * status = "disabled"
+@@ -1300,32 +1343,39 @@
+ return -ENODEV;
+
+ of_id = of_match_device(fsl_ssi_ids, &pdev->dev);
+- if (!of_id || !of_id->data)
++ if (!of_id)
++ return -EINVAL;
++ hw_type = (enum fsl_ssi_type) of_id->data;
++
++ sprop = of_get_property(np, "fsl,mode", NULL);
++ if (!sprop) {
++ dev_err(&pdev->dev, "fsl,mode property is necessary\n");
+ return -EINVAL;
++ }
++ if (!strcmp(sprop, "ac97-slave"))
++ ac97 = true;
+
+- ssi_private = devm_kzalloc(&pdev->dev, sizeof(*ssi_private),
+- GFP_KERNEL);
++ /* The DAI name is the last part of the full name of the node. */
++ p = strrchr(np->full_name, '/') + 1;
++ ssi_private = devm_kzalloc(&pdev->dev, sizeof(*ssi_private) + strlen(p),
++ GFP_KERNEL);
+ if (!ssi_private) {
+ dev_err(&pdev->dev, "could not allocate DAI object\n");
+ return -ENOMEM;
+ }
+
+- ssi_private->soc = of_id->data;
+-
+- sprop = of_get_property(np, "fsl,mode", NULL);
+- if (sprop) {
+- if (!strcmp(sprop, "ac97-slave"))
+- ssi_private->dai_fmt = SND_SOC_DAIFMT_AC97;
+- }
++ strcpy(ssi_private->name, p);
+
+ ssi_private->use_dma = !of_property_read_bool(np,
+ "fsl,fiq-stream-filter");
++ ssi_private->hw_type = hw_type;
+
+- if (fsl_ssi_is_ac97(ssi_private)) {
++ if (ac97) {
+ memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_ac97_dai,
+ sizeof(fsl_ssi_ac97_dai));
+
+ fsl_ac97_data = ssi_private;
++ ssi_private->imx_ac97 = true;
+
+ snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops, pdev);
+ } else {
+@@ -1333,33 +1383,25 @@
+ memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_dai_template,
+ sizeof(fsl_ssi_dai_template));
+ }
+- ssi_private->cpu_dai_drv.name = dev_name(&pdev->dev);
++ ssi_private->cpu_dai_drv.name = ssi_private->name;
+
+- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+- iomem = devm_ioremap_resource(&pdev->dev, res);
+- if (IS_ERR(iomem))
+- return PTR_ERR(iomem);
+- ssi_private->ssi_phys = res->start;
+-
+- ret = of_property_match_string(np, "clock-names", "ipg");
+- if (ret < 0) {
+- ssi_private->has_ipg_clk_name = false;
+- ssi_private->regs = devm_regmap_init_mmio(&pdev->dev, iomem,
+- &fsl_ssi_regconfig);
+- } else {
+- ssi_private->has_ipg_clk_name = true;
+- ssi_private->regs = devm_regmap_init_mmio_clk(&pdev->dev,
+- "ipg", iomem, &fsl_ssi_regconfig);
+- }
+- if (IS_ERR(ssi_private->regs)) {
+- dev_err(&pdev->dev, "Failed to init register map\n");
+- return PTR_ERR(ssi_private->regs);
++ /* Get the addresses and IRQ */
++ ret = of_address_to_resource(np, 0, &res);
++ if (ret) {
++ dev_err(&pdev->dev, "could not determine device resources\n");
++ return ret;
++ }
++ ssi_private->ssi = of_iomap(np, 0);
++ if (!ssi_private->ssi) {
++ dev_err(&pdev->dev, "could not map device resources\n");
++ return -ENOMEM;
+ }
++ ssi_private->ssi_phys = res.start;
+
+- ssi_private->irq = platform_get_irq(pdev, 0);
+- if (ssi_private->irq < 0) {
+- dev_err(&pdev->dev, "no irq for node %s\n", pdev->name);
+- return ssi_private->irq;
++ ssi_private->irq = irq_of_parse_and_map(np, 0);
++ if (!ssi_private->irq) {
++ dev_err(&pdev->dev, "no irq for node %s\n", np->full_name);
++ return -ENXIO;
+ }
+
+ /* Are the RX and the TX clocks locked? */
+@@ -1377,43 +1419,153 @@
+ /* Older 8610 DTs didn't have the fifo-depth property */
+ ssi_private->fifo_depth = 8;
+
+- dev_set_drvdata(&pdev->dev, ssi_private);
++ ssi_private->baudclk_locked = false;
++ spin_lock_init(&ssi_private->baudclk_lock);
+
+- if (ssi_private->soc->imx) {
+- ret = fsl_ssi_imx_probe(pdev, ssi_private, iomem);
+- if (ret)
+- return ret;
++ /*
++ * imx51 and later SoCs have a slightly different IP that allows the
++ * SSI configuration while the SSI unit is running.
++ *
++ * More important, it is necessary on those SoCs to configure the
++ * sperate TX/RX DMA bits just before starting the stream
++ * (fsl_ssi_trigger). The SDMA unit has to be configured before fsl_ssi
++ * sends any DMA requests to the SDMA unit, otherwise it is not defined
++ * how the SDMA unit handles the DMA request.
++ *
++ * SDMA units are present on devices starting at imx35 but the imx35
++ * reference manual states that the DMA bits should not be changed
++ * while the SSI unit is running (SSIEN). So we support the necessary
++ * online configuration of fsl-ssi starting at imx51.
++ */
++ switch (hw_type) {
++ case FSL_SSI_MCP8610:
++ case FSL_SSI_MX21:
++ case FSL_SSI_MX35:
++ ssi_private->offline_config = true;
++ break;
++ case FSL_SSI_MX51:
++ ssi_private->offline_config = false;
++ break;
+ }
+
+- ret = devm_snd_soc_register_component(&pdev->dev, &fsl_ssi_component,
+- &ssi_private->cpu_dai_drv, 1);
+- if (ret) {
+- dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
+- goto error_asoc_register;
++ if (hw_type == FSL_SSI_MX21 || hw_type == FSL_SSI_MX51 ||
++ hw_type == FSL_SSI_MX35) {
++ ssi_private->ssi_on_imx = true;
++
++ ssi_private->clk = devm_clk_get(&pdev->dev, NULL);
++ if (IS_ERR(ssi_private->clk)) {
++ ret = PTR_ERR(ssi_private->clk);
++ dev_err(&pdev->dev, "could not get clock: %d\n", ret);
++ goto error_irqmap;
++ }
++ ret = clk_prepare(ssi_private->clk);
++ if (ret) {
++ dev_err(&pdev->dev, "clk_prepare failed: %d\n",
++ ret);
++ goto error_irqmap;
++ }
++
++ /* For those SLAVE implementations, we ingore non-baudclk cases
++ * and, instead, abandon MASTER mode that needs baud clock.
++ */
++ ssi_private->baudclk = devm_clk_get(&pdev->dev, "baud");
++ if (IS_ERR(ssi_private->baudclk))
++ dev_dbg(&pdev->dev, "could not get baud clock: %ld\n",
++ PTR_ERR(ssi_private->baudclk));
++ else
++ clk_prepare(ssi_private->baudclk);
++
++ /*
++ * We have burstsize be "fifo_depth - 2" to match the SSI
++ * watermark setting in fsl_ssi_startup().
++ */
++ ssi_private->dma_params_tx.maxburst = ssi_private->fifo_depth - 2;
++ ssi_private->dma_params_rx.maxburst = ssi_private->fifo_depth - 2;
++ ssi_private->dma_params_tx.addr =
++ ssi_private->ssi_phys + offsetof(struct ccsr_ssi, stx0);
++ ssi_private->dma_params_rx.addr =
++ ssi_private->ssi_phys + offsetof(struct ccsr_ssi, srx0);
++
++ ret = !of_property_read_u32_array(np, "dmas", dmas, 4);
++ if (ssi_private->use_dma && !ret && dmas[2] == IMX_DMATYPE_SSI_DUAL) {
++ ssi_private->use_dual_fifo = true;
++ /* When using dual fifo mode, we need to keep watermark
++ * as even numbers due to dma script limitation.
++ */
++ ssi_private->dma_params_tx.maxburst &= ~0x1;
++ ssi_private->dma_params_rx.maxburst &= ~0x1;
++ }
+ }
+
++ /*
++ * Enable interrupts only for MCP8610 and MX51. The other MXs have
++ * different writeable interrupt status registers.
++ */
+ if (ssi_private->use_dma) {
++ /* The 'name' should not have any slashes in it. */
+ ret = devm_request_irq(&pdev->dev, ssi_private->irq,
+- fsl_ssi_isr, 0, dev_name(&pdev->dev),
++ fsl_ssi_isr, 0, ssi_private->name,
+ ssi_private);
++ ssi_private->irq_stats = true;
+ if (ret < 0) {
+ dev_err(&pdev->dev, "could not claim irq %u\n",
+ ssi_private->irq);
+- goto error_asoc_register;
++ goto error_clk;
+ }
+ }
+
+- ret = fsl_ssi_debugfs_create(&ssi_private->dbg_stats, &pdev->dev);
++ pm_runtime_enable(&pdev->dev);
++
++ /* Register with ASoC */
++ dev_set_drvdata(&pdev->dev, ssi_private);
++
++ ret = snd_soc_register_component(&pdev->dev, &fsl_ssi_component,
++ &ssi_private->cpu_dai_drv, 1);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
++ goto error_dev;
++ }
++
++ ret = fsl_ssi_debugfs_create(ssi_private, &pdev->dev);
+ if (ret)
+- goto error_asoc_register;
++ goto error_dbgfs;
++
++ if (ssi_private->ssi_on_imx) {
++ if (!ssi_private->use_dma) {
++
++ /*
++ * Some boards use an incompatible codec. To get it
++ * working, we are using imx-fiq-pcm-audio, that
++ * can handle those codecs. DMA is not possible in this
++ * situation.
++ */
++
++ ssi_private->fiq_params.irq = ssi_private->irq;
++ ssi_private->fiq_params.base = ssi_private->ssi;
++ ssi_private->fiq_params.dma_params_rx =
++ &ssi_private->dma_params_rx;
++ ssi_private->fiq_params.dma_params_tx =
++ &ssi_private->dma_params_tx;
++
++ ret = imx_pcm_fiq_init(pdev, &ssi_private->fiq_params);
++ if (ret)
++ goto error_pcm;
++ } else {
++ ret = imx_pcm_dma_init(pdev, IMX_SSI_DMABUF_SIZE);
++ if (ret)
++ goto error_pcm;
++ }
++ }
+
+ /*
+ * If codec-handle property is missing from SSI node, we assume
+ * that the machine driver uses new binding which does not require
+ * SSI driver to trigger machine driver's probe.
+ */
+- if (!of_get_property(np, "codec-handle", NULL))
++ if (!of_get_property(np, "codec-handle", NULL)) {
++ ssi_private->new_binding = true;
+ goto done;
++ }
+
+ /* Trigger the machine driver's probe function. The platform driver
+ * name of the machine driver is taken from /compatible property of the
+@@ -1433,22 +1585,42 @@
+ if (IS_ERR(ssi_private->pdev)) {
+ ret = PTR_ERR(ssi_private->pdev);
+ dev_err(&pdev->dev, "failed to register platform: %d\n", ret);
+- goto error_sound_card;
++ goto error_dai;
+ }
+
+ done:
+- if (ssi_private->dai_fmt)
+- _fsl_ssi_set_dai_fmt(&pdev->dev, ssi_private,
+- ssi_private->dai_fmt);
++ if (ssi_private->imx_ac97)
++ fsl_ssi_ac97_init();
+
+ return 0;
+
+-error_sound_card:
+- fsl_ssi_debugfs_remove(&ssi_private->dbg_stats);
++error_dai:
++ if (ssi_private->ssi_on_imx && !ssi_private->use_dma)
++ imx_pcm_fiq_exit(pdev);
++
++error_pcm:
++ fsl_ssi_debugfs_remove(ssi_private);
++
++error_dbgfs:
++ snd_soc_unregister_component(&pdev->dev);
++
++error_dev:
++ device_remove_file(&pdev->dev, dev_attr);
+
+-error_asoc_register:
+- if (ssi_private->soc->imx)
+- fsl_ssi_imx_clean(pdev, ssi_private);
++ if (ssi_private->ssi_on_imx) {
++ if (!IS_ERR(ssi_private->baudclk))
++ clk_unprepare(ssi_private->baudclk);
++ clk_unprepare(ssi_private->clk);
++ }
++error_clk:
++ if (!IS_ERR(ssi_private->baudclk))
++ clk_unprepare(ssi_private->baudclk);
++ if (!IS_ERR(ssi_private->clk))
++ clk_unprepare(ssi_private->clk);
++
++error_irqmap:
++ if (ssi_private->irq_stats)
++ irq_dispose_mapping(ssi_private->irq);
+
+ return ret;
+ }
+@@ -1457,13 +1629,18 @@
+ {
+ struct fsl_ssi_private *ssi_private = dev_get_drvdata(&pdev->dev);
+
+- fsl_ssi_debugfs_remove(&ssi_private->dbg_stats);
++ fsl_ssi_debugfs_remove(ssi_private);
+
+- if (ssi_private->pdev)
++ if (!ssi_private->new_binding)
+ platform_device_unregister(ssi_private->pdev);
+-
+- if (ssi_private->soc->imx)
+- fsl_ssi_imx_clean(pdev, ssi_private);
++ snd_soc_unregister_component(&pdev->dev);
++ if (ssi_private->ssi_on_imx) {
++ if (!IS_ERR(ssi_private->baudclk))
++ clk_unprepare(ssi_private->baudclk);
++ clk_unprepare(ssi_private->clk);
++ }
++ if (ssi_private->irq_stats)
++ irq_dispose_mapping(ssi_private->irq);
+
+ return 0;
+ }
+@@ -1471,7 +1648,9 @@
+ static struct platform_driver fsl_ssi_driver = {
+ .driver = {
+ .name = "fsl-ssi-dai",
++ .owner = THIS_MODULE,
+ .of_match_table = fsl_ssi_ids,
++ .pm = &fsl_ssi_pm,
+ },
+ .probe = fsl_ssi_probe,
+ .remove = fsl_ssi_remove,
+diff -Nur linux-4.1.3/sound/soc/fsl/fsl_ssi.h linux-xbian-imx6/sound/soc/fsl/fsl_ssi.h
+--- linux-4.1.3/sound/soc/fsl/fsl_ssi.h 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/sound/soc/fsl/fsl_ssi.h 2015-07-27 23:13:11.153188979 +0200
+@@ -12,32 +12,33 @@
+ #ifndef _MPC8610_I2S_H
+ #define _MPC8610_I2S_H
+
+-/* SSI registers */
+-#define CCSR_SSI_STX0 0x00
+-#define CCSR_SSI_STX1 0x04
+-#define CCSR_SSI_SRX0 0x08
+-#define CCSR_SSI_SRX1 0x0c
+-#define CCSR_SSI_SCR 0x10
+-#define CCSR_SSI_SISR 0x14
+-#define CCSR_SSI_SIER 0x18
+-#define CCSR_SSI_STCR 0x1c
+-#define CCSR_SSI_SRCR 0x20
+-#define CCSR_SSI_STCCR 0x24
+-#define CCSR_SSI_SRCCR 0x28
+-#define CCSR_SSI_SFCSR 0x2c
+-#define CCSR_SSI_STR 0x30
+-#define CCSR_SSI_SOR 0x34
+-#define CCSR_SSI_SACNT 0x38
+-#define CCSR_SSI_SACADD 0x3c
+-#define CCSR_SSI_SACDAT 0x40
+-#define CCSR_SSI_SATAG 0x44
+-#define CCSR_SSI_STMSK 0x48
+-#define CCSR_SSI_SRMSK 0x4c
+-#define CCSR_SSI_SACCST 0x50
+-#define CCSR_SSI_SACCEN 0x54
+-#define CCSR_SSI_SACCDIS 0x58
++/* SSI Register Map */
++struct ccsr_ssi {
++ __be32 stx0; /* 0x.0000 - SSI Transmit Data Register 0 */
++ __be32 stx1; /* 0x.0004 - SSI Transmit Data Register 1 */
++ __be32 srx0; /* 0x.0008 - SSI Receive Data Register 0 */
++ __be32 srx1; /* 0x.000C - SSI Receive Data Register 1 */
++ __be32 scr; /* 0x.0010 - SSI Control Register */
++ __be32 sisr; /* 0x.0014 - SSI Interrupt Status Register Mixed */
++ __be32 sier; /* 0x.0018 - SSI Interrupt Enable Register */
++ __be32 stcr; /* 0x.001C - SSI Transmit Configuration Register */
++ __be32 srcr; /* 0x.0020 - SSI Receive Configuration Register */
++ __be32 stccr; /* 0x.0024 - SSI Transmit Clock Control Register */
++ __be32 srccr; /* 0x.0028 - SSI Receive Clock Control Register */
++ __be32 sfcsr; /* 0x.002C - SSI FIFO Control/Status Register */
++ __be32 str; /* 0x.0030 - SSI Test Register */
++ __be32 sor; /* 0x.0034 - SSI Option Register */
++ __be32 sacnt; /* 0x.0038 - SSI AC97 Control Register */
++ __be32 sacadd; /* 0x.003C - SSI AC97 Command Address Register */
++ __be32 sacdat; /* 0x.0040 - SSI AC97 Command Data Register */
++ __be32 satag; /* 0x.0044 - SSI AC97 Tag Register */
++ __be32 stmsk; /* 0x.0048 - SSI Transmit Time Slot Mask Register */
++ __be32 srmsk; /* 0x.004C - SSI Receive Time Slot Mask Register */
++ __be32 saccst; /* 0x.0050 - SSI AC97 Channel Status Register */
++ __be32 saccen; /* 0x.0054 - SSI AC97 Channel Enable Register */
++ __be32 saccdis; /* 0x.0058 - SSI AC97 Channel Disable Register */
++};
+
+-#define CCSR_SSI_SCR_SYNC_TX_FS 0x00001000
+ #define CCSR_SSI_SCR_RFR_CLK_DIS 0x00000800
+ #define CCSR_SSI_SCR_TFR_CLK_DIS 0x00000400
+ #define CCSR_SSI_SCR_TCH_EN 0x00000100
+@@ -205,64 +206,5 @@
+ #define CCSR_SSI_SACNT_FV 0x00000002
+ #define CCSR_SSI_SACNT_AC97EN 0x00000001
+
+-
+-struct device;
+-
+-#if IS_ENABLED(CONFIG_DEBUG_FS)
+-
+-struct fsl_ssi_dbg {
+- struct dentry *dbg_dir;
+- struct dentry *dbg_stats;
+-
+- struct {
+- unsigned int rfrc;
+- unsigned int tfrc;
+- unsigned int cmdau;
+- unsigned int cmddu;
+- unsigned int rxt;
+- unsigned int rdr1;
+- unsigned int rdr0;
+- unsigned int tde1;
+- unsigned int tde0;
+- unsigned int roe1;
+- unsigned int roe0;
+- unsigned int tue1;
+- unsigned int tue0;
+- unsigned int tfs;
+- unsigned int rfs;
+- unsigned int tls;
+- unsigned int rls;
+- unsigned int rff1;
+- unsigned int rff0;
+- unsigned int tfe1;
+- unsigned int tfe0;
+- } stats;
+-};
+-
+-void fsl_ssi_dbg_isr(struct fsl_ssi_dbg *ssi_dbg, u32 sisr);
+-
+-int fsl_ssi_debugfs_create(struct fsl_ssi_dbg *ssi_dbg, struct device *dev);
+-
+-void fsl_ssi_debugfs_remove(struct fsl_ssi_dbg *ssi_dbg);
+-
+-#else
+-
+-struct fsl_ssi_dbg {
+-};
+-
+-static inline void fsl_ssi_dbg_isr(struct fsl_ssi_dbg *stats, u32 sisr)
+-{
+-}
+-
+-static inline int fsl_ssi_debugfs_create(struct fsl_ssi_dbg *ssi_dbg,
+- struct device *dev)
+-{
+- return 0;
+-}
+-
+-static inline void fsl_ssi_debugfs_remove(struct fsl_ssi_dbg *ssi_dbg)
+-{
+-}
+-#endif /* ! IS_ENABLED(CONFIG_DEBUG_FS) */
+-
+ #endif
++
+diff -Nur linux-4.1.3/sound/soc/fsl/hdmi_pcm.S linux-xbian-imx6/sound/soc/fsl/hdmi_pcm.S
+--- linux-4.1.3/sound/soc/fsl/hdmi_pcm.S 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/sound/soc/fsl/hdmi_pcm.S 2015-07-27 23:13:11.153188979 +0200
+@@ -0,0 +1,246 @@
++/**
++ * Copyright (C) 2010-2014 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++.section .text
++
++.global hdmi_dma_copy_16_neon_lut
++.global hdmi_dma_copy_16_neon_fast
++.global hdmi_dma_copy_24_neon_lut
++.global hdmi_dma_copy_24_neon_fast
++
++
++/**
++ * hdmi_dma_copy_16_neon_lut
++ * Convert pcm sample to iec sample. Pcm sample is 16 bits.
++ * Frame index's between 0 and 47 inclusively. Channel count can be 1, 2, 4, 8.
++ * Frame count should be multipliable by 4, and Sample count by 8.
++ *
++ * C Prototype
++ * void hdmi_dma_copy_16_neon_lut(unsigned short *src, unsigned int *dst,
++ * int samples, unsigned char *lookup_table);
++ * Return value
++ * None
++ * Parameters
++ * src Source PCM16 samples
++ * dst Dest buffer to store pcm with header
++ * samples Contains sample count (=frame_count * channel_count)
++ * lookup_table Preconstructed header table. Channels interleaved.
++ */
++
++hdmi_dma_copy_16_neon_lut:
++ mov r12, #1 /* construct vector(1) */
++ vdup.8 d6, r12
++
++hdmi_dma_copy_16_neon_lut_start:
++
++ /* get 8 samples to q0 */
++ vld1.16 {d0, d1}, [r0]! /* TODO: aligned */
++
++ /* pld [r1, #(64*4)] */
++
++ /* xor every bit */
++ vcnt.8 q1, q0 /* count of 1s */
++ vpadd.i8 d2, d2, d3 /* only care about the LST in every element */
++ vand d2, d2, d6 /* clear other bits while keep the least bit */
++ vshl.u8 d2, d2, #3 /* bit p: d2 = d2 << 3 */
++
++ /* get packet header */
++ vld1.8 {d5}, [r3]!
++ veor d4, d5, d2 /* xor bit c */
++
++ /* store: (d4 << 16 | q0) << 8 */
++ vmovl.u8 q2, d4 /* expand from char to short */
++ vzip.16 q0, q2
++ vshl.u32 q0, q0, #8
++ vshl.u32 q1, q2, #8
++ vst1.32 {d0, d1, d2, d3}, [r1]!
++
++ /* decrease sample count */
++ subs r2, r2, #8
++ bne hdmi_dma_copy_16_neon_lut_start
++
++ mov pc, lr
++
++/**
++ * hdmi_dma_copy_16_neon_fast
++ * Convert pcm sample to iec sample. Pcm sample is 16 bits.
++ * Frame index's between 48 and 191 inclusively.
++ * Channel count can be 1, 2, 4 or 8.
++ * Frame count should be multipliable by 4, and Sample count by 8.
++ *
++ * C Prototype
++ * void hdmi_dma_copy_16_neon_fast(unsigned short *src,
++ * unsigned int *dst, int samples);
++ * Return value
++ * None
++ * Parameters
++ * src Source PCM16 samples
++ * dst Dest buffer to store pcm with header
++ * samples Contains sample count (=frame_count * channel_count)
++ */
++
++hdmi_dma_copy_16_neon_fast:
++ mov r12, #1 /* construct vector(1) */
++ vdup.8 d6, r12
++
++hdmi_dma_copy_16_neon_fast_start:
++ /* get 8 samples to q0 */
++ vld1.16 {d0, d1}, [r0]! /* TODO: aligned */
++
++ /* pld [r1, #(64*4)] */
++
++ /* xor every bit */
++ vcnt.8 q1, q0 /* count of 1s */
++ vpadd.i8 d2, d2, d3
++ vand d2, d2, d6 /* clear other bits while keep the LST */
++ /* finally we construct packet header */
++ vshl.u8 d4, d2, #3 /* bit p: d2 = d2 << 3 */
++
++ /* get packet header: always 0 */
++
++ /* store: (d4 << 16 | q0) << 8 */
++ vmovl.u8 q2, d4 /* expand from char to short */
++ vzip.16 q0, q2
++ vshl.u32 q0, q0, #8
++ vshl.u32 q1, q2, #8
++ vst1.32 {d0, d1, d2, d3}, [r1]!
++
++ /* decrease sample count */
++ subs r2, r2, #8
++ bne hdmi_dma_copy_16_neon_fast_start
++
++ mov pc, lr
++
++
++
++/**
++ * hdmi_dma_copy_24_neon_lut
++ * Convert pcm sample to iec sample. Pcm sample is 24 bits.
++ * Frame index's between 0 and 47 inclusively. Channel count can be 1, 2, 4, 8.
++ * Frame count should be multipliable by 4, and Sample count by 8.
++ *
++ * C Prototype
++ * void hdmi_dma_copy_24_neon_lut(unsigned int *src, unsigned int *dst,
++ * int samples, unsigned char *lookup_table);
++ * Return value
++ * None
++ * Parameters
++ * src Source PCM24 samples
++ * dst Dest buffer to store pcm with header
++ * samples Contains sample count (=frame_count * channel_count)
++ * lookup_table Preconstructed header table. Channels interleaved.
++ */
++
++hdmi_dma_copy_24_neon_lut:
++ vpush {d8}
++
++ mov r12, #1 /* construct vector(1) */
++ vdup.8 d8, r12
++
++hdmi_dma_copy_24_neon_lut_start:
++
++ /* get 8 samples to q0 and q1 */
++ vld1.32 {d0, d1, d2, d3}, [r0]! /* TODO: aligned */
++
++ /* pld [r1, #(64*4)] */
++
++ /* xor every bit */
++ vcnt.8 q2, q0 /* count of 1s */
++ vpadd.i8 d4, d4, d5 /* only care about the LSB in every element */
++ vcnt.8 q3, q1
++ vpadd.i8 d6, d6, d7
++ vpadd.i8 d4, d4, d6 /* d4: contains xor result and other dirty bits */
++ vand d4, d4, d8 /* clear other bits while keep the least bit */
++ vshl.u8 d4, d4, #3 /* bit p: d4 = d4 << 3 */
++
++ /* get packet header */
++ vld1.8 {d5}, [r3]!/* d5: original header */
++ veor d5, d5, d4 /* fix bit p */
++
++ /* store: (d5 << 24 | q0) */
++ vmovl.u8 q3, d5 /* expand from char to short */
++ vmovl.u16 q2, d6 /* expand from short to int */
++ vmovl.u16 q3, d7
++ vshl.u32 q2, q2, #24
++ vshl.u32 q3, q3, #24
++ vorr q0, q0, q2
++ vorr q1, q1, q3
++ vst1.32 {d0, d1, d2, d3}, [r1]!
++
++ /* decrease sample count */
++ subs r2, r2, #8
++ bne hdmi_dma_copy_24_neon_lut_start
++
++ vpop {d8}
++ mov pc, lr
++
++/**
++ * hdmi_dma_copy_24_neon_fast
++ * Convert pcm sample to iec sample. Pcm sample is 24 bits.
++ * Frame index's between 48 and 191 inclusively.
++ * Channel count can be 1, 2, 4 or 8.
++ * Frame count should be multipliable by 4, and Sample count by 8.
++ *
++ * C Prototype
++ * void hdmi_dma_copy_24_neon_fast(unsigned int *src,
++ * unsigned int *dst, int samples);
++ * Return value
++ * None
++ * Parameters
++ * src Source PCM24 samples
++ * dst Dest buffer to store pcm with header
++ * samples Contains sample count (=frame_count * channel_count)
++ */
++
++hdmi_dma_copy_24_neon_fast:
++ vpush {d8}
++
++ mov r12, #1 /* construct vector(1) */
++ vdup.8 d8, r12
++
++hdmi_dma_copy_24_neon_fast_start:
++ /* get 8 samples to q0 and q1 */
++ vld1.32 {d0, d1, d2, d3}, [r0]! /* TODO: aligned */
++
++ /* pld [r1, #(64*4)] */
++
++ /* xor every bit */
++ vcnt.8 q2, q0 /* count of 1s */
++ vpadd.i8 d4, d4, d5 /* only care about the LSB in every element */
++ vcnt.8 q3, q1
++ vpadd.i8 d6, d6, d7
++ vpadd.i8 d4, d4, d6 /* d4: contains xor result and other dirty bits */
++ vand d4, d4, d8 /* clear other bits while keep the least bit */
++ vshl.u8 d4, d4, #3 /* bit p: d4 = d4 << 3 */
++
++ /* store: (d4 << 24 | q0) */
++ vmovl.u8 q3, d4 /* expand from char to short */
++ vmovl.u16 q2, d6 /* expand from short to int */
++ vmovl.u16 q3, d7
++ vshl.u32 q2, q2, #24
++ vshl.u32 q3, q3, #24
++ vorr q0, q0, q2
++ vorr q1, q1, q3
++ vst1.32 {d0, d1, d2, d3}, [r1]!
++
++ /* decrease sample count */
++ subs r2, r2, #8
++ bne hdmi_dma_copy_24_neon_fast_start
++
++ vpop {d8}
++ mov pc, lr
+diff -Nur linux-4.1.3/sound/soc/fsl/imx-audmux.c linux-xbian-imx6/sound/soc/fsl/imx-audmux.c
+--- linux-4.1.3/sound/soc/fsl/imx-audmux.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/sound/soc/fsl/imx-audmux.c 2015-07-27 23:13:11.153188979 +0200
+@@ -67,7 +67,7 @@
+ {
+ ssize_t ret;
+ char *buf;
+- uintptr_t port = (uintptr_t)file->private_data;
++ int port = (int)file->private_data;
+ u32 pdcr, ptcr;
+
+ if (audmux_clk) {
+@@ -145,9 +145,9 @@
+ .llseek = default_llseek,
+ };
+
+-static void audmux_debugfs_init(void)
++static void __init audmux_debugfs_init(void)
+ {
+- uintptr_t i;
++ int i;
+ char buf[20];
+
+ audmux_debugfs_root = debugfs_create_dir("audmux", NULL);
+@@ -157,10 +157,10 @@
+ }
+
+ for (i = 0; i < MX31_AUDMUX_PORT7_SSI_PINS_7 + 1; i++) {
+- snprintf(buf, sizeof(buf), "ssi%lu", i);
++ snprintf(buf, sizeof(buf), "ssi%d", i);
+ if (!debugfs_create_file(buf, 0444, audmux_debugfs_root,
+ (void *)i, &audmux_debugfs_fops))
+- pr_warning("Failed to create AUDMUX port %lu debugfs file\n",
++ pr_warning("Failed to create AUDMUX port %d debugfs file\n",
+ i);
+ }
+ }
+@@ -356,6 +356,7 @@
+ .id_table = imx_audmux_ids,
+ .driver = {
+ .name = DRIVER_NAME,
++ .owner = THIS_MODULE,
+ .of_match_table = imx_audmux_dt_ids,
+ }
+ };
+diff -Nur linux-4.1.3/sound/soc/fsl/imx-hdmi.c linux-xbian-imx6/sound/soc/fsl/imx-hdmi.c
+--- linux-4.1.3/sound/soc/fsl/imx-hdmi.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/sound/soc/fsl/imx-hdmi.c 2015-07-27 23:13:11.153188979 +0200
+@@ -0,0 +1,114 @@
++/*
++ * ASoC HDMI Transmitter driver for IMX development boards
++ *
++ * Copyright (C) 2011-2014 Freescale Semiconductor, Inc.
++ *
++ * based on stmp3780_devb_hdmi.c
++ *
++ * Vladimir Barinov <vbarinov@embeddedalley.com>
++ *
++ * Copyright 2008 SigmaTel, Inc
++ * Copyright 2008 Embedded Alley Solutions, Inc
++ *
++ * This file is licensed under the terms of the GNU General Public License
++ * version 2. This program is licensed "as is" without any warranty of any
++ * kind, whether express or implied.
++ */
++
++#include <linux/module.h>
++#include <linux/of_platform.h>
++#include <linux/mfd/mxc-hdmi-core.h>
++#include <sound/soc.h>
++
++#include "imx-hdmi.h"
++
++/* imx digital audio interface glue - connects codec <--> CPU */
++static struct snd_soc_dai_link imx_hdmi_dai_link = {
++ .name = "i.MX HDMI Audio Tx",
++ .stream_name = "i.MX HDMI Audio Tx",
++ .codec_dai_name = "hdmi-hifi",
++ .codec_name = "hdmi-audio-codec",
++ .platform_name = "imx-hdmi-audio",
++ .ignore_pmdown_time = 1,
++};
++
++static struct snd_soc_card snd_soc_card_imx_hdmi = {
++ .name = "imx-hdmi-soc",
++ .dai_link = &imx_hdmi_dai_link,
++ .num_links = 1,
++};
++
++static int imx_hdmi_audio_probe(struct platform_device *pdev)
++{
++ struct device_node *hdmi_np, *np = pdev->dev.of_node;
++ struct snd_soc_card *card = &snd_soc_card_imx_hdmi;
++ struct platform_device *hdmi_pdev;
++ int ret = 0;
++
++ if (!hdmi_get_registered()) {
++ dev_err(&pdev->dev, "initialize HDMI-audio failed. load HDMI-video first!\n");
++ return -ENODEV;
++ }
++
++ hdmi_np = of_parse_phandle(np, "hdmi-controller", 0);
++ if (!hdmi_np) {
++ dev_err(&pdev->dev, "failed to find hdmi-audio cpudai\n");
++ ret = -EINVAL;
++ goto end;
++ }
++
++ hdmi_pdev = of_find_device_by_node(hdmi_np);
++ if (!hdmi_pdev) {
++ dev_err(&pdev->dev, "failed to find SSI platform device\n");
++ ret = -EINVAL;
++ goto end;
++ }
++
++ card->dev = &pdev->dev;
++ card->dai_link->cpu_dai_name = dev_name(&hdmi_pdev->dev);
++
++ platform_set_drvdata(pdev, card);
++
++ ret = snd_soc_register_card(card);
++ if (ret)
++ dev_err(&pdev->dev, "failed to register card: %d\n", ret);
++
++end:
++ if (hdmi_np)
++ of_node_put(hdmi_np);
++
++ return ret;
++}
++
++static int imx_hdmi_audio_remove(struct platform_device *pdev)
++{
++ struct snd_soc_card *card = platform_get_drvdata(pdev);
++
++ snd_soc_unregister_card(card);
++
++ return 0;
++}
++
++static const struct of_device_id imx_hdmi_dt_ids[] = {
++ { .compatible = "fsl,imx-audio-hdmi", },
++ { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, imx_hdmi_dt_ids);
++
++static struct platform_driver imx_hdmi_audio_driver = {
++ .probe = imx_hdmi_audio_probe,
++ .remove = imx_hdmi_audio_remove,
++ .driver = {
++ .of_match_table = imx_hdmi_dt_ids,
++ .name = "imx-audio-hdmi",
++ .owner = THIS_MODULE,
++ .pm = &snd_soc_pm_ops,
++ },
++};
++
++module_platform_driver(imx_hdmi_audio_driver);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("IMX HDMI TX ASoC driver");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:imx-audio-hdmi");
+diff -Nur linux-4.1.3/sound/soc/fsl/imx-hdmi-dma.c linux-xbian-imx6/sound/soc/fsl/imx-hdmi-dma.c
+--- linux-4.1.3/sound/soc/fsl/imx-hdmi-dma.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/sound/soc/fsl/imx-hdmi-dma.c 2015-07-27 23:13:11.153188979 +0200
+@@ -0,0 +1,1256 @@
++/*
++ * imx-hdmi-dma.c -- HDMI DMA driver for ALSA Soc Audio Layer
++ *
++ * Copyright (C) 2011-2014 Freescale Semiconductor, Inc.
++ *
++ * based on imx-pcm-dma-mx2.c
++ * Copyright 2009 Sascha Hauer <s.hauer@pengutronix.de>
++ *
++ * This code is based on code copyrighted by Freescale,
++ * Liam Girdwood, Javier Martin and probably others.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ */
++
++#include <linux/module.h>
++#include <linux/delay.h>
++#include <linux/dma-mapping.h>
++#include <linux/mfd/mxc-hdmi-core.h>
++#include <linux/platform_data/dma-imx.h>
++
++#include <video/mxc_hdmi.h>
++
++#include "imx-hdmi.h"
++
++#define HDMI_DMA_BURST_UNSPECIFIED_LEGNTH 0
++#define HDMI_DMA_BURST_INCR4 1
++#define HDMI_DMA_BURST_INCR8 2
++#define HDMI_DMA_BURST_INCR16 3
++
++#define HDMI_BASE_ADDR 0x00120000
++
++struct hdmi_sdma_script {
++ int control_reg_addr;
++ int status_reg_addr;
++ int dma_start_addr;
++ u32 buffer[20];
++};
++
++struct hdmi_dma_priv {
++ struct snd_pcm_substream *substream;
++ struct platform_device *pdev;
++
++ struct snd_dma_buffer hw_buffer;
++ unsigned long buffer_bytes;
++ unsigned long appl_bytes;
++
++ int periods;
++ int period_time;
++ int period_bytes;
++ int dma_period_bytes;
++ int buffer_ratio;
++
++ unsigned long offset;
++
++ snd_pcm_format_t format;
++ int sample_align;
++ int sample_bits;
++ int channels;
++ int rate;
++
++ int frame_idx;
++
++ bool tx_active;
++ spinlock_t irq_lock;
++
++ /* SDMA part */
++ dma_addr_t phy_hdmi_sdma_t;
++ struct hdmi_sdma_script *hdmi_sdma_t;
++ struct dma_chan *dma_channel;
++ struct imx_dma_data dma_data;
++ struct dma_async_tx_descriptor *desc;
++ struct imx_hdmi_sdma_params sdma_params;
++};
++
++/* bit 0:0:0:b:p(0):c:(u)0:(v)0 */
++/* max 8 channels supported; channels are interleaved */
++static u8 g_packet_head_table[48 * 8];
++
++/* channel remapping for hdmi_dma_copy_xxxx() */
++static u8 g_channel_remap_table[24];
++
++/* default mapping tables */
++static const u8 channel_maps_alsa_cea[5][8] = {
++ { 0, 1, 2, 3, 4, 5, 6, 7 }, /* 0CH: no remapping */
++ { 0, 1, 2, 3, 4, 5, 6, 7 }, /* 2CH: no remapping */
++ { 0, 1, 2, 3, 4, 5, 6, 7 }, /* 4CH: no remapping */
++ { 0, 1, 4, 5, 3, 2, 6, 7 }, /* 6CH: ALSA5.1 to CEA */
++ { 0, 1, 6, 7, 3, 2, 4, 5 } /* 8CH: ALSA7.1 to CEA */
++};
++
++static const u8 channel_maps_cea_alsa[5][8] = {
++ { 0, 1, 2, 3, 4, 5, 6, 7 }, /* 0CH: no remapping */
++ { 0, 1, 2, 3, 4, 5, 6, 7 }, /* 2CH: no remapping */
++ { 0, 1, 2, 3, 4, 5, 6, 7 }, /* 4CH: no remapping */
++ { 0, 1, 5, 4, 2, 3, 6, 7 }, /* 6CH: CEA to ALSA5.1 */
++ { 0, 1, 5, 4, 6, 7, 2, 3 } /* 8CH: CEA to ALSA7.1 */
++};
++
++union hdmi_audio_header_t iec_header;
++EXPORT_SYMBOL(iec_header);
++
++/*
++ * Note that the period size for DMA != period size for ALSA because the
++ * driver adds iec frame info to the audio samples (in hdmi_dma_copy).
++ *
++ * Each 4 byte subframe = 1 byte of iec data + 3 byte audio sample.
++ *
++ * A 16 bit audio sample becomes 32 bits including the frame info. Ratio=2
++ * A 24 bit audio sample becomes 32 bits including the frame info. Ratio=3:4
++ * If the 24 bit raw audio is in 32 bit words, the
++ *
++ * Original Packed into subframe Ratio of size Format
++ * sample how many size of DMA buffer
++ * (bits) bits to ALSA buffer
++ * -------- ----------- -------- -------------- ------------------------
++ * 16 16 32 2 SNDRV_PCM_FORMAT_S16_LE
++ * 24 24 32 1.33 SNDRV_PCM_FORMAT_S24_3LE*
++ * 24 32 32 1 SNDRV_PCM_FORMAT_S24_LE
++ *
++ * *so SNDRV_PCM_FORMAT_S24_3LE is not supported.
++ */
++
++/*
++ * The minimum dma period is one IEC audio frame (192 * 4 * channels).
++ * The maximum dma period for the HDMI DMA is 8K.
++ *
++ * channels minimum maximum
++ * dma period dma period
++ * -------- ------------------ ----------
++ * 2 192 * 4 * 2 = 1536 * 4 = 6144
++ * 4 192 * 4 * 4 = 3072 * 2 = 6144
++ * 6 192 * 4 * 6 = 4608 * 1 = 4608
++ * 8 192 * 4 * 8 = 6144 * 1 = 6144
++ *
++ * Bottom line:
++ * 1. Must keep the ratio of DMA buffer to ALSA buffer consistent.
++ * 2. frame_idx is saved in the private data, so even if a frame cannot be
++ * transmitted in a period, it can be continued in the next period. This
++ * is necessary for 6 ch.
++ */
++#define HDMI_DMA_PERIOD_BYTES (12288)
++#define HDMI_DMA_BUF_SIZE (1280 * 1024)
++#define HDMI_PCM_BUF_SIZE (1280 * 1024)
++
++#define hdmi_audio_debug(dev, reg) \
++ dev_dbg(dev, #reg ": 0x%02x\n", hdmi_readb(reg))
++
++#ifdef DEBUG
++static void dumpregs(struct device *dev)
++{
++ hdmi_audio_debug(dev, HDMI_AHB_DMA_CONF0);
++ hdmi_audio_debug(dev, HDMI_AHB_DMA_START);
++ hdmi_audio_debug(dev, HDMI_AHB_DMA_STOP);
++ hdmi_audio_debug(dev, HDMI_AHB_DMA_THRSLD);
++ hdmi_audio_debug(dev, HDMI_AHB_DMA_STRADDR0);
++ hdmi_audio_debug(dev, HDMI_AHB_DMA_STPADDR0);
++ hdmi_audio_debug(dev, HDMI_AHB_DMA_BSTADDR0);
++ hdmi_audio_debug(dev, HDMI_AHB_DMA_MBLENGTH0);
++ hdmi_audio_debug(dev, HDMI_AHB_DMA_MBLENGTH1);
++ hdmi_audio_debug(dev, HDMI_AHB_DMA_STAT);
++ hdmi_audio_debug(dev, HDMI_AHB_DMA_INT);
++ hdmi_audio_debug(dev, HDMI_AHB_DMA_MASK);
++ hdmi_audio_debug(dev, HDMI_AHB_DMA_POL);
++ hdmi_audio_debug(dev, HDMI_AHB_DMA_CONF1);
++ hdmi_audio_debug(dev, HDMI_AHB_DMA_BUFFSTAT);
++ hdmi_audio_debug(dev, HDMI_AHB_DMA_BUFFINT);
++ hdmi_audio_debug(dev, HDMI_AHB_DMA_BUFFMASK);
++ hdmi_audio_debug(dev, HDMI_AHB_DMA_BUFFPOL);
++ hdmi_audio_debug(dev, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
++ hdmi_audio_debug(dev, HDMI_IH_AHBDMAAUD_STAT0);
++ hdmi_audio_debug(dev, HDMI_IH_MUTE);
++}
++
++static void dumppriv(struct device *dev, struct hdmi_dma_priv *priv)
++{
++ dev_dbg(dev, "channels = %d\n", priv->channels);
++ dev_dbg(dev, "periods = %d\n", priv->periods);
++ dev_dbg(dev, "period_bytes = %d\n", priv->period_bytes);
++ dev_dbg(dev, "dma period_bytes = %d\n", priv->dma_period_bytes);
++ dev_dbg(dev, "buffer_ratio = %d\n", priv->buffer_ratio);
++ dev_dbg(dev, "hw dma buffer = 0x%08x\n", (int)priv->hw_buffer.addr);
++ dev_dbg(dev, "dma buf size = %d\n", (int)priv->buffer_bytes);
++ dev_dbg(dev, "sample_rate = %d\n", (int)priv->rate);
++}
++#else
++static void dumpregs(struct device *dev) {}
++static void dumppriv(struct device *dev, struct hdmi_dma_priv *priv) {}
++#endif
++
++/*
++ * Conditions for DMA to work:
++ * ((final_addr - initial_addr)>>2)+1) < 2k. So max period is 8k.
++ * (inital_addr & 0x3) == 0
++ * (final_addr & 0x3) == 0x3
++ *
++ * The DMA Period should be an integer multiple of the IEC 60958 audio
++ * frame size, which is 768 bytes (192 * 4).
++ */
++static void hdmi_dma_set_addr(int start_addr, int dma_period_bytes)
++{
++ int final_addr = start_addr + dma_period_bytes - 1;
++
++ hdmi_write4(start_addr, HDMI_AHB_DMA_STRADDR0);
++ hdmi_write4(final_addr, HDMI_AHB_DMA_STPADDR0);
++}
++
++static void hdmi_dma_irq_set(bool set)
++{
++ u8 val = hdmi_readb(HDMI_AHB_DMA_MASK);
++
++ if (set)
++ val |= HDMI_AHB_DMA_DONE;
++ else
++ val &= (u8)~HDMI_AHB_DMA_DONE;
++
++ hdmi_writeb(val, HDMI_AHB_DMA_MASK);
++}
++
++static void hdmi_mask(int mask)
++{
++ u8 regval = hdmi_readb(HDMI_AHB_DMA_MASK);
++
++ if (mask)
++ regval |= HDMI_AHB_DMA_ERROR | HDMI_AHB_DMA_FIFO_EMPTY;
++ else
++ regval &= (u8)~(HDMI_AHB_DMA_ERROR | HDMI_AHB_DMA_FIFO_EMPTY);
++
++ hdmi_writeb(regval, HDMI_AHB_DMA_MASK);
++}
++
++static inline int odd_ones(unsigned a)
++{
++ a ^= a >> 16;
++ a ^= a >> 8;
++ a ^= a >> 4;
++ a ^= a >> 2;
++ a ^= a >> 1;
++
++ return a & 1;
++}
++
++/* Add frame information for one pcm subframe */
++static u32 hdmi_dma_add_frame_info(struct hdmi_dma_priv *priv,
++ u32 pcm_data, int subframe_idx)
++{
++ union hdmi_audio_dma_data_t subframe;
++ union hdmi_audio_header_t tmp_header;
++
++ subframe.U = 0;
++
++ if (priv->frame_idx < 42) {
++ tmp_header = iec_header;
++
++ /* fill v (validity) */
++ subframe.B.v = tmp_header.B.linear_pcm;
++
++ /* fill c (channel status) */
++ if (tmp_header.B.linear_pcm == 0)
++ tmp_header.B.channel = subframe_idx + 1;
++ subframe.B.c = tmp_header.U >> priv->frame_idx;
++ } else {
++ /* fill v (validity), c is always zero */
++ subframe.B.v = iec_header.B.linear_pcm;
++ }
++
++ /* fill data */
++ if (priv->sample_bits == 16)
++ pcm_data <<= 8;
++ subframe.B.data = pcm_data;
++
++ /* fill p (parity) Note: Do not include b ! */
++ subframe.B.p = odd_ones(subframe.U);
++
++ /* fill b (start-of-block) */
++ if (priv->frame_idx == 0)
++ subframe.B.b = 1;
++
++ return subframe.U;
++}
++
++static void init_table(int channels)
++{
++ int i, map_sel, ch;
++ unsigned char *p = g_packet_head_table;
++ union hdmi_audio_header_t tmp_header = iec_header;
++
++ for (i = 0; i < 48; i++) {
++ int b = 0;
++ if (i == 0)
++ b = 1;
++
++ for (ch = 0; ch < channels; ch++) {
++ int c = 0;
++ if (i < 42) {
++ tmp_header.B.channel = ch + 1;
++ c = (tmp_header.U >> i) & 0x1;
++ }
++ /* preset bit p as c */
++ *p++ = (b << 4) | (c << 2) | (c << 3);
++ }
++ }
++
++ map_sel = channels / 2;
++ for (i = 0; i < 24; i++) {
++ g_channel_remap_table[i] = (i / channels) * channels +
++ channel_maps_cea_alsa[map_sel][i % channels];
++ }
++}
++
++/* Optimization for IEC head */
++static void hdmi_dma_copy_16_c_lut(u16 *src, u32 *dst, int samples,
++ u8 *lookup_table)
++{
++ u32 sample, head;
++ int i = 0;
++
++ while (samples--) {
++ /* get source sample */
++ sample = src[g_channel_remap_table[i]];
++
++ /* get packet header and p-bit */
++ head = *lookup_table++ ^ (odd_ones(sample) << 3);
++
++ /* store sample and header */
++ *dst++ = (head << 24) | (sample << 8);
++
++ if (++i == 24) {
++ src += 24;
++ i = 0;
++ }
++ }
++}
++
++static void hdmi_dma_copy_16_c_fast(u16 *src, u32 *dst, int samples)
++{
++ u32 sample;
++ int i = 0;
++
++ while (samples--) {
++ /* get source sample */
++ sample = src[g_channel_remap_table[i]];
++
++ /* store sample and p-bit */
++ *dst++ = (odd_ones(sample) << (3+24)) | (sample << 8);
++
++ if (++i == 24) {
++ src += 24;
++ i = 0;
++ }
++ }
++}
++
++static void hdmi_dma_copy_24_c_lut(u32 *src, u32 *dst, int samples,
++ u8 *lookup_table)
++{
++ u32 sample, head;
++ int i = 0;
++
++ while (samples--) {
++ /* get source sample */
++ sample = src[g_channel_remap_table[i]] & 0x00ffffff;
++
++ /* get packet header and p-bit */
++ head = *lookup_table++ ^ (odd_ones(sample) << 3);
++
++ /* store sample and header */
++ *dst++ = (head << 24) | sample;
++
++ if (++i == 24) {
++ src += 24;
++ i = 0;
++ }
++ }
++}
++
++static void hdmi_dma_copy_24_c_fast(u32 *src, u32 *dst, int samples)
++{
++ u32 sample;
++ int i = 0;
++
++ while (samples--) {
++ /* get source sample */
++ sample = src[g_channel_remap_table[i]] & 0x00ffffff;
++
++ /* store sample and p-bit */
++ *dst++ = (odd_ones(sample) << (3+24)) | sample;
++
++ if (++i == 24) {
++ src += 24;
++ i = 0;
++ }
++ }
++}
++
++static void hdmi_mmap_copy(u8 *src, int samplesize, u32 *dst, int framecnt, int channelcnt)
++{
++ /* split input frames into 192-frame each */
++ int count_in_192 = (framecnt + 191) / 192;
++ int i;
++
++ typedef void (*fn_copy_lut)(u8 *src, u32 *dst, int samples, u8 *lookup_table);
++ typedef void (*fn_copy_fast)(u8 *src, u32 *dst, int samples);
++ fn_copy_lut copy_lut;
++ fn_copy_fast copy_fast;
++
++ if (samplesize == 4) {
++ copy_lut = (fn_copy_lut)hdmi_dma_copy_24_c_lut;
++ copy_fast = (fn_copy_fast)hdmi_dma_copy_24_c_fast;
++ } else {
++ copy_lut = (fn_copy_lut)hdmi_dma_copy_16_c_lut;
++ copy_fast = (fn_copy_fast)hdmi_dma_copy_16_c_fast;
++ }
++
++ for (i = 0; i < count_in_192; i++) {
++ int count, samples;
++
++ /* handles frame index [0, 48) */
++ count = (framecnt < 48) ? framecnt : 48;
++ samples = count * channelcnt;
++ copy_lut(src, dst, samples, g_packet_head_table);
++ framecnt -= count;
++ if (framecnt == 0)
++ break;
++
++ src += samples * samplesize;
++ dst += samples;
++
++ /* handles frame index [48, 192) */
++ count = (framecnt < 192 - 48) ? framecnt : 192 - 48;
++ samples = count * channelcnt;
++ copy_fast(src, dst, samples);
++ framecnt -= count;
++ src += samples * samplesize;
++ dst += samples;
++ }
++}
++
++static void hdmi_dma_mmap_copy(struct snd_pcm_substream *substream,
++ int offset, int count)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_pcm_runtime *runtime = substream->runtime;
++ struct hdmi_dma_priv *priv = runtime->private_data;
++ struct device *dev = rtd->platform->dev;
++ u32 framecount, *dst;
++
++ framecount = count / (priv->sample_align * priv->channels);
++
++ /* hw_buffer is the destination for pcm data plus frame info. */
++ dst = (u32 *)(priv->hw_buffer.area + (offset * priv->buffer_ratio));
++
++ switch (priv->format) {
++ case SNDRV_PCM_FORMAT_S16_LE:
++ case SNDRV_PCM_FORMAT_S24_LE:
++ /* dma_buffer is the mmapped buffer we are copying pcm from. */
++ hdmi_mmap_copy(runtime->dma_area + offset,
++ priv->sample_align, dst, framecount, priv->channels);
++ break;
++ default:
++ dev_err(dev, "unsupported sample format %s\n",
++ snd_pcm_format_name(priv->format));
++ return;
++ }
++}
++
++static void hdmi_dma_data_copy(struct snd_pcm_substream *substream,
++ struct hdmi_dma_priv *priv, char type)
++{
++ struct snd_pcm_runtime *runtime = substream->runtime;
++ unsigned long offset, count, appl_bytes, space_to_end;
++
++ if (runtime->access != SNDRV_PCM_ACCESS_MMAP_INTERLEAVED)
++ return;
++
++ appl_bytes = frames_to_bytes(runtime, runtime->status->hw_ptr);
++
++ switch (type) {
++ case 'p':
++ offset = (appl_bytes + 2 * priv->period_bytes) % priv->buffer_bytes;
++ count = priv->period_bytes;
++ space_to_end = priv->period_bytes;
++ break;
++ case 'b':
++ offset = appl_bytes % priv->buffer_bytes;
++ count = priv->buffer_bytes;
++ space_to_end = priv->buffer_bytes - offset;
++ break;
++ default:
++ return;
++ }
++
++ if (count <= space_to_end) {
++ hdmi_dma_mmap_copy(substream, offset, count);
++ } else {
++ hdmi_dma_mmap_copy(substream, offset, space_to_end);
++ hdmi_dma_mmap_copy(substream, 0, count - space_to_end);
++ }
++}
++
++static void hdmi_sdma_callback(void *data)
++{
++ struct hdmi_dma_priv *priv = (struct hdmi_dma_priv *)data;
++ struct snd_pcm_substream *substream = priv->substream;
++ struct snd_pcm_runtime *runtime = substream->runtime;
++ unsigned long flags;
++
++ spin_lock_irqsave(&priv->irq_lock, flags);
++
++ if (runtime && runtime->dma_area && priv->tx_active) {
++ priv->offset += priv->period_bytes;
++ priv->offset %= priv->period_bytes * priv->periods;
++
++ /* Copy data by period_bytes */
++ hdmi_dma_data_copy(substream, priv, 'p');
++
++ snd_pcm_period_elapsed(substream);
++ }
++
++ spin_unlock_irqrestore(&priv->irq_lock, flags);
++
++ return;
++}
++
++static int hdmi_dma_set_thrsld_incrtype(struct device *dev, int channels)
++{
++ u8 mask = HDMI_AHB_DMA_CONF0_BURST_MODE | HDMI_AHB_DMA_CONF0_INCR_TYPE_MASK;
++ u8 val = hdmi_readb(HDMI_AHB_DMA_CONF0) & ~mask;
++ int incr_type, threshold;
++
++ switch (hdmi_readb(HDMI_REVISION_ID)) {
++ case 0x0a:
++ incr_type = HDMI_DMA_BURST_INCR4;
++ if (channels == 2)
++ threshold = 126;
++ else
++ threshold = 124;
++ break;
++ case 0x1a:
++ incr_type = HDMI_DMA_BURST_INCR8;
++ threshold = 128;
++ break;
++ default:
++ dev_err(dev, "unknown hdmi controller!\n");
++ return -ENODEV;
++ }
++
++ hdmi_writeb(threshold, HDMI_AHB_DMA_THRSLD);
++
++ switch (incr_type) {
++ case HDMI_DMA_BURST_UNSPECIFIED_LEGNTH:
++ break;
++ case HDMI_DMA_BURST_INCR4:
++ val |= HDMI_AHB_DMA_CONF0_BURST_MODE;
++ break;
++ case HDMI_DMA_BURST_INCR8:
++ val |= HDMI_AHB_DMA_CONF0_BURST_MODE |
++ HDMI_AHB_DMA_CONF0_INCR8;
++ break;
++ case HDMI_DMA_BURST_INCR16:
++ val |= HDMI_AHB_DMA_CONF0_BURST_MODE |
++ HDMI_AHB_DMA_CONF0_INCR16;
++ break;
++ default:
++ dev_err(dev, "invalid increment type: %d!", incr_type);
++ return -EINVAL;
++ }
++
++ hdmi_writeb(val, HDMI_AHB_DMA_CONF0);
++
++ hdmi_audio_debug(dev, HDMI_AHB_DMA_THRSLD);
++
++ return 0;
++}
++
++static void hdmi_dma_set_hbr(struct device *dev, int channels)
++{
++ u8 value = hdmi_readb(HDMI_AHB_DMA_CONF0) & (~HDMI_AHB_DMA_CONF0_HBR_MASK);
++
++ /* non audio AES and 8 channels means we have to enable HBR */
++ if ((channels == 8) &&
++ (iec_header.B.linear_pcm == 0)) {
++ value |= HDMI_AHB_DMA_CONF0_HBR_MASK;
++ dev_info(dev, "Enabling HBR");
++ }
++
++ hdmi_writeb(value, HDMI_AHB_DMA_CONF0);
++}
++
++static int hdmi_dma_configure_dma(struct device *dev, int channels)
++{
++ int ret;
++ static u8 chan_enable[] = { 0x00, 0x03, 0x33, 0x3f, 0xff };
++
++ if (channels <= 0 || channels > 8 || channels % 2 != 0) {
++ dev_err(dev, "unsupported channel number: %d\n", channels);
++ return -EINVAL;
++ }
++
++ hdmi_audio_writeb(AHB_DMA_CONF0, EN_HLOCK, 0x1);
++
++ ret = hdmi_dma_set_thrsld_incrtype(dev, channels);
++ if (ret)
++ return ret;
++
++ hdmi_writeb(chan_enable[channels / 2], HDMI_AHB_DMA_CONF1);
++
++ /* Handle HBR */
++ hdmi_dma_set_hbr(dev, channels);
++
++ return 0;
++}
++
++static void hdmi_dma_init_iec_header(void)
++{
++ iec_header.U = 0;
++
++ iec_header.B.consumer = 0; /* Consumer use */
++ iec_header.B.linear_pcm = 0; /* linear pcm audio */
++ iec_header.B.copyright = 1; /* no copyright */
++ iec_header.B.pre_emphasis = 0; /* 2 channels without pre-emphasis */
++ iec_header.B.mode = 0; /* Mode 0 */
++
++ iec_header.B.category_code = 0;
++
++ iec_header.B.source = 2; /* stereo */
++ iec_header.B.channel = 0;
++
++ iec_header.B.sample_freq = 0x02; /* 48 KHz */
++ iec_header.B.clock_acc = 0; /* Level II */
++
++ iec_header.B.word_length = 0x02; /* 16 bits */
++ iec_header.B.org_sample_freq = 0x0D; /* 48 KHz */
++
++ iec_header.B.cgms_a = 0; /* Copying is permitted without restriction */
++}
++
++static int hdmi_dma_update_iec_header(struct snd_pcm_substream *substream)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_pcm_runtime *runtime = substream->runtime;
++ struct hdmi_dma_priv *priv = runtime->private_data;
++ struct device *dev = rtd->platform->dev;
++
++ iec_header.B.source = priv->channels;
++
++ switch (priv->rate) {
++ case 32000:
++ iec_header.B.sample_freq = 0x03;
++ iec_header.B.org_sample_freq = 0x0C;
++ break;
++ case 44100:
++ iec_header.B.sample_freq = 0x00;
++ iec_header.B.org_sample_freq = 0x0F;
++ break;
++ case 48000:
++ iec_header.B.sample_freq = 0x02;
++ iec_header.B.org_sample_freq = 0x0D;
++ break;
++ case 88200:
++ iec_header.B.sample_freq = 0x08;
++ iec_header.B.org_sample_freq = 0x07;
++ break;
++ case 96000:
++ iec_header.B.sample_freq = 0x0A;
++ iec_header.B.org_sample_freq = 0x05;
++ break;
++ case 176400:
++ iec_header.B.sample_freq = 0x0C;
++ iec_header.B.org_sample_freq = 0x03;
++ break;
++ case 192000:
++ iec_header.B.sample_freq = 0x0E;
++ iec_header.B.org_sample_freq = 0x01;
++ break;
++ default:
++ dev_err(dev, "unsupported sample rate\n");
++ return -EFAULT;
++ }
++
++ switch (priv->format) {
++ case SNDRV_PCM_FORMAT_S16_LE:
++ iec_header.B.word_length = 0x02;
++ break;
++ case SNDRV_PCM_FORMAT_S24_LE:
++ iec_header.B.word_length = 0x0b;
++ break;
++ default:
++ return -EFAULT;
++ }
++
++ return 0;
++}
++
++/*
++ * The HDMI block transmits the audio data without adding any of the audio
++ * frame bits. So we have to copy the raw dma data from the ALSA buffer
++ * to the DMA buffer, adding the frame information.
++ */
++static int hdmi_dma_copy(struct snd_pcm_substream *substream, int channel,
++ snd_pcm_uframes_t pos, void __user *buf,
++ snd_pcm_uframes_t frames)
++{
++ struct snd_pcm_runtime *runtime = substream->runtime;
++ struct hdmi_dma_priv *priv = runtime->private_data;
++ unsigned int count = frames_to_bytes(runtime, frames);
++ unsigned int pos_bytes = frames_to_bytes(runtime, pos);
++ int channel_no, pcm_idx, subframe_idx, bits_left, sample_bits, map_sel;
++ u32 pcm_data[8], pcm_temp, *hw_buf, sample_block, inc_mask;
++
++ /* Adding frame info to pcm data from userspace and copy to hw_buffer */
++ hw_buf = (u32 *)(priv->hw_buffer.area + (pos_bytes * priv->buffer_ratio));
++
++ sample_bits = priv->sample_align * 8;
++ sample_block = priv->sample_align * priv->channels;
++
++ if (iec_header.B.linear_pcm == 0) {
++ map_sel = priv->channels / 2;
++ inc_mask = 1 << (priv->channels - 1);
++ } else {
++ map_sel = 0;
++ inc_mask = 0xaa;
++ }
++
++ while (count > 0) {
++ if (copy_from_user(pcm_data, buf, sample_block))
++ return -EFAULT;
++
++ buf += sample_block;
++ count -= sample_block;
++
++ channel_no = pcm_idx = 0;
++ do {
++ pcm_temp = pcm_data[pcm_idx++];
++ bits_left = 32;
++ for (;;) {
++ /* re-map channels */
++ subframe_idx = channel_maps_alsa_cea[map_sel][channel_no];
++
++ /* Save the header info to the audio dma buffer */
++ hw_buf[subframe_idx] = hdmi_dma_add_frame_info(
++ priv, pcm_temp, subframe_idx);
++
++ if (inc_mask & (1 << channel_no)) {
++ if (++priv->frame_idx == 192)
++ priv->frame_idx = 0;
++ }
++
++ channel_no++;
++
++ if (bits_left <= sample_bits)
++ break;
++
++ bits_left -= sample_bits;
++ pcm_temp >>= sample_bits;
++ }
++ } while (channel_no < priv->channels);
++
++ hw_buf += priv->channels;
++ }
++
++ return 0;
++}
++
++static int hdmi_sdma_initbuf(struct device *dev, struct hdmi_dma_priv *priv)
++{
++ struct hdmi_sdma_script *hdmi_sdma_t = priv->hdmi_sdma_t;
++ u32 *head, *tail, i;
++
++ if (!hdmi_sdma_t) {
++ dev_err(dev, "hdmi private addr invalid!!!\n");
++ return -EINVAL;
++ }
++
++ hdmi_sdma_t->control_reg_addr = HDMI_BASE_ADDR + HDMI_AHB_DMA_START;
++ hdmi_sdma_t->status_reg_addr = HDMI_BASE_ADDR + HDMI_IH_AHBDMAAUD_STAT0;
++ hdmi_sdma_t->dma_start_addr = HDMI_BASE_ADDR + HDMI_AHB_DMA_STRADDR0;
++
++ head = &hdmi_sdma_t->buffer[0];
++ tail = &hdmi_sdma_t->buffer[1];
++
++ for (i = 0; i < priv->sdma_params.buffer_num; i++) {
++ *head = priv->hw_buffer.addr + i * priv->period_bytes * priv->buffer_ratio;
++ *tail = *head + priv->dma_period_bytes - 1;
++ head += 2;
++ tail += 2;
++ }
++
++ return 0;
++}
++
++static int hdmi_sdma_config(struct snd_pcm_substream *substream,
++ struct hdmi_dma_priv *priv)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct device *dai_dev = &priv->pdev->dev;
++ struct device *dev = rtd->platform->dev;
++ struct dma_slave_config slave_config;
++ int ret;
++
++ priv->dma_channel = dma_request_slave_channel(dai_dev, "tx");
++ if (priv->dma_channel == NULL) {
++ dev_err(dev, "failed to alloc dma channel\n");
++ return -EBUSY;
++ }
++
++ priv->dma_data.data_addr1 = &priv->sdma_params.buffer_num;
++ priv->dma_data.data_addr2 = &priv->sdma_params.phyaddr;
++ //priv->dma_data.peripheral_type = IMX_DMATYPE_HDMI;
++ priv->dma_channel->private = &priv->dma_data;
++
++ slave_config.direction = DMA_TRANS_NONE;
++
++ ret = dmaengine_slave_config(priv->dma_channel, &slave_config);
++ if (ret) {
++ dev_err(dev, "failed to config slave dma, (%d)\n", ret);
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++static int hdmi_dma_hw_free(struct snd_pcm_substream *substream)
++{
++ struct snd_pcm_runtime *runtime = substream->runtime;
++ struct hdmi_dma_priv *priv = runtime->private_data;
++
++ if (priv->dma_channel) {
++ dma_release_channel(priv->dma_channel);
++ priv->dma_channel = NULL;
++ }
++
++ return 0;
++}
++
++static int hdmi_dma_hw_params(struct snd_pcm_substream *substream,
++ struct snd_pcm_hw_params *params)
++{
++ struct snd_pcm_runtime *runtime = substream->runtime;
++ struct hdmi_dma_priv *priv = runtime->private_data;
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct device *dev = rtd->platform->dev;
++ int ret;
++
++ priv->buffer_bytes = params_buffer_bytes(params);
++ priv->periods = params_periods(params);
++ priv->period_bytes = params_period_bytes(params);
++ priv->channels = params_channels(params);
++ priv->format = params_format(params);
++ priv->rate = params_rate(params);
++
++ priv->offset = 0;
++ priv->period_time = HZ / (priv->rate / params_period_size(params));
++
++ switch (priv->format) {
++ case SNDRV_PCM_FORMAT_S16_LE:
++ priv->buffer_ratio = 2;
++ priv->sample_align = 2;
++ priv->sample_bits = 16;
++ break;
++ case SNDRV_PCM_FORMAT_S24_LE:
++ /* 24 bit audio in 32 bit word */
++ priv->buffer_ratio = 1;
++ priv->sample_align = 4;
++ priv->sample_bits = 24;
++ break;
++ default:
++ dev_err(dev, "unsupported sample format: %d\n", priv->format);
++ return -EINVAL;
++ }
++
++ priv->dma_period_bytes = priv->period_bytes * priv->buffer_ratio;
++ priv->sdma_params.buffer_num = priv->periods;
++ priv->sdma_params.phyaddr = priv->phy_hdmi_sdma_t;
++
++ ret = hdmi_sdma_initbuf(dev, priv);
++ if (ret)
++ return ret;
++
++ ret = hdmi_sdma_config(substream, priv);
++ if (ret)
++ return ret;
++
++ snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
++
++ ret = hdmi_dma_configure_dma(dev, priv->channels);
++ if (ret)
++ return ret;
++
++ hdmi_dma_set_addr(priv->hw_buffer.addr, priv->dma_period_bytes);
++
++ dumppriv(dev, priv);
++
++ hdmi_dma_update_iec_header(substream);
++
++ /* Init par for mmap optimizate */
++ init_table(priv->channels);
++
++ priv->appl_bytes = 0;
++ priv->frame_idx = 0;
++
++ return 0;
++}
++
++static void hdmi_dma_trigger_init(struct snd_pcm_substream *substream,
++ struct hdmi_dma_priv *priv)
++{
++ unsigned long status;
++ bool hbr;
++
++ /*
++ * Set HBR mode (>192kHz IEC-61937 HD audio bitstreaming).
++ * This is done this late because userspace may alter the AESx
++ * parameters until the stream is finally prepared.
++ */
++ hbr = (iec_header.B.linear_pcm != 0 && priv->channels == 8);
++ hdmi_audio_writeb(AHB_DMA_CONF0, HBR, !!hbr);
++
++ /*
++ * Override AES3 - parameter: This is a temporary hack for
++ * callers that provide incorrect information when opening
++ * the device. 0x09 (i.e. 768K) is the only acceptable value.
++ */
++ if (hbr) {
++ iec_header.B.sample_freq = 0x09;
++ iec_header.B.org_sample_freq = 0x00;
++ }
++
++ priv->offset = 0;
++
++ /* Copy data by buffer_bytes */
++ hdmi_dma_data_copy(substream, priv, 'b');
++
++ hdmi_audio_writeb(AHB_DMA_CONF0, SW_FIFO_RST, 0x1);
++
++ /* Delay after reset */
++ udelay(1);
++
++ status = hdmi_readb(HDMI_IH_AHBDMAAUD_STAT0);
++ hdmi_writeb(status, HDMI_IH_AHBDMAAUD_STAT0);
++}
++
++static int hdmi_dma_prepare_and_submit(struct snd_pcm_substream *substream,
++ struct hdmi_dma_priv *priv)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct device *dev = rtd->platform->dev;
++
++ priv->desc = dmaengine_prep_dma_cyclic(priv->dma_channel, 0, 0, 0,
++ DMA_TRANS_NONE, 0);
++ if (!priv->desc) {
++ dev_err(dev, "failed to prepare slave dma\n");
++ return -EINVAL;
++ }
++
++ priv->desc->callback = hdmi_sdma_callback;
++ priv->desc->callback_param = (void *)priv;
++ dmaengine_submit(priv->desc);
++
++ return 0;
++}
++
++static int hdmi_dma_trigger(struct snd_pcm_substream *substream, int cmd)
++{
++ struct snd_pcm_runtime *runtime = substream->runtime;
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct hdmi_dma_priv *priv = runtime->private_data;
++ struct device *dev = rtd->platform->dev;
++ int ret;
++
++ switch (cmd) {
++ case SNDRV_PCM_TRIGGER_START:
++ case SNDRV_PCM_TRIGGER_RESUME:
++ if (!check_hdmi_state())
++ return 0;
++ hdmi_dma_trigger_init(substream, priv);
++
++ dumpregs(dev);
++
++ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
++ priv->tx_active = true;
++ hdmi_audio_writeb(AHB_DMA_START, START, 0x1);
++ hdmi_dma_irq_set(false);
++ hdmi_set_dma_mode(1);
++ ret = hdmi_dma_prepare_and_submit(substream, priv);
++ if (ret)
++ return ret;
++ dma_async_issue_pending(priv->desc->chan);
++ break;
++ case SNDRV_PCM_TRIGGER_STOP:
++ case SNDRV_PCM_TRIGGER_SUSPEND:
++ case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
++ dmaengine_terminate_all(priv->dma_channel);
++ hdmi_set_dma_mode(0);
++ hdmi_dma_irq_set(true);
++ hdmi_audio_writeb(AHB_DMA_STOP, STOP, 0x1);
++ priv->tx_active = false;
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++static snd_pcm_uframes_t hdmi_dma_pointer(struct snd_pcm_substream *substream)
++{
++ struct snd_pcm_runtime *runtime = substream->runtime;
++ struct hdmi_dma_priv *priv = runtime->private_data;
++
++ return bytes_to_frames(runtime, priv->offset);
++}
++
++static struct snd_pcm_hardware snd_imx_hardware = {
++ .info = SNDRV_PCM_INFO_INTERLEAVED |
++ SNDRV_PCM_INFO_BLOCK_TRANSFER |
++ SNDRV_PCM_INFO_MMAP |
++ SNDRV_PCM_INFO_MMAP_VALID |
++ SNDRV_PCM_INFO_PAUSE |
++ SNDRV_PCM_INFO_RESUME,
++ .formats = MXC_HDMI_FORMATS_PLAYBACK,
++ .rate_min = 32000,
++ .channels_min = 2,
++ .channels_max = 8,
++ .buffer_bytes_max = HDMI_PCM_BUF_SIZE,
++ .period_bytes_min = HDMI_DMA_PERIOD_BYTES / 2,
++ .period_bytes_max = HDMI_DMA_PERIOD_BYTES / 2,
++ .periods_min = 2, //8
++ .periods_max = HDMI_DMA_BUF_SIZE / HDMI_DMA_PERIOD_BYTES,
++ .fifo_size = 0,
++};
++
++static void hdmi_dma_irq_enable(struct hdmi_dma_priv *priv)
++{
++ unsigned long flags;
++
++ hdmi_writeb(0xff, HDMI_AHB_DMA_POL);
++ hdmi_writeb(0xff, HDMI_AHB_DMA_BUFFPOL);
++
++ spin_lock_irqsave(&priv->irq_lock, flags);
++
++ hdmi_writeb(0xff, HDMI_IH_AHBDMAAUD_STAT0);
++ hdmi_writeb(0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
++ hdmi_dma_irq_set(false);
++ hdmi_mask(0);
++
++ spin_unlock_irqrestore(&priv->irq_lock, flags);
++}
++
++static void hdmi_dma_irq_disable(struct hdmi_dma_priv *priv)
++{
++ unsigned long flags;
++
++ spin_lock_irqsave(&priv->irq_lock, flags);
++
++ hdmi_dma_irq_set(true);
++ hdmi_writeb(0x0, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
++ hdmi_writeb(0xff, HDMI_IH_AHBDMAAUD_STAT0);
++ hdmi_mask(1);
++
++ spin_unlock_irqrestore(&priv->irq_lock, flags);
++}
++
++static int hdmi_dma_open(struct snd_pcm_substream *substream)
++{
++ struct snd_pcm_runtime *runtime = substream->runtime;
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct device *dev = rtd->platform->dev;
++ struct hdmi_dma_priv *priv = dev_get_drvdata(dev);
++ int ret;
++
++ runtime->private_data = priv;
++
++ ret = mxc_hdmi_register_audio(substream);
++ if (ret < 0) {
++ dev_err(dev, "HDMI Video is not ready!\n");
++ return ret;
++ }
++
++ hdmi_audio_writeb(AHB_DMA_CONF0, SW_FIFO_RST, 0x1);
++
++ ret = snd_pcm_hw_constraint_integer(substream->runtime,
++ SNDRV_PCM_HW_PARAM_PERIODS);
++ if (ret < 0)
++ return ret;
++
++ snd_soc_set_runtime_hwparams(substream, &snd_imx_hardware);
++
++ hdmi_dma_irq_enable(priv);
++
++ return 0;
++}
++
++static int hdmi_dma_close(struct snd_pcm_substream *substream)
++{
++ struct snd_pcm_runtime *runtime = substream->runtime;
++ struct hdmi_dma_priv *priv = runtime->private_data;
++
++ hdmi_dma_irq_disable(priv);
++ mxc_hdmi_unregister_audio(substream);
++
++ return 0;
++}
++
++static struct snd_pcm_ops imx_hdmi_dma_pcm_ops = {
++ .open = hdmi_dma_open,
++ .close = hdmi_dma_close,
++ .ioctl = snd_pcm_lib_ioctl,
++ .hw_params = hdmi_dma_hw_params,
++ .hw_free = hdmi_dma_hw_free,
++ .trigger = hdmi_dma_trigger,
++ .pointer = hdmi_dma_pointer,
++ .copy = hdmi_dma_copy,
++};
++
++static int imx_hdmi_dma_pcm_new(struct snd_soc_pcm_runtime *rtd)
++{
++ struct hdmi_dma_priv *priv = dev_get_drvdata(rtd->platform->dev);
++ struct snd_card *card = rtd->card->snd_card;
++ struct snd_pcm_substream *substream;
++ struct snd_pcm *pcm = rtd->pcm;
++ u64 dma_mask = DMA_BIT_MASK(32);
++ int ret = 0;
++
++ if (!card->dev->dma_mask)
++ card->dev->dma_mask = &dma_mask;
++ if (!card->dev->coherent_dma_mask)
++ card->dev->coherent_dma_mask = DMA_BIT_MASK(32);
++
++ substream = pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
++
++ ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, pcm->card->dev,
++ HDMI_PCM_BUF_SIZE, &substream->dma_buffer);
++ if (ret) {
++ dev_err(card->dev, "failed to alloc playback dma buffer\n");
++ return ret;
++ }
++
++ priv->substream = substream;
++
++ /* Alloc the hw_buffer */
++ ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, pcm->card->dev,
++ HDMI_DMA_BUF_SIZE, &priv->hw_buffer);
++ if (ret) {
++ dev_err(card->dev, "failed to alloc hw dma buffer\n");
++ return ret;
++ }
++
++ return ret;
++}
++
++static void imx_hdmi_dma_pcm_free(struct snd_pcm *pcm)
++{
++ int stream = SNDRV_PCM_STREAM_PLAYBACK;
++ struct snd_pcm_substream *substream = pcm->streams[stream].substream;
++ struct snd_soc_pcm_runtime *rtd = pcm->private_data;
++ struct hdmi_dma_priv *priv = dev_get_drvdata(rtd->platform->dev);
++
++ if (substream) {
++ snd_dma_free_pages(&substream->dma_buffer);
++ substream->dma_buffer.area = NULL;
++ substream->dma_buffer.addr = 0;
++ }
++
++ /* Free the hw_buffer */
++ snd_dma_free_pages(&priv->hw_buffer);
++ priv->hw_buffer.area = NULL;
++ priv->hw_buffer.addr = 0;
++}
++
++static struct snd_soc_platform_driver imx_hdmi_platform = {
++ .ops = &imx_hdmi_dma_pcm_ops,
++ .pcm_new = imx_hdmi_dma_pcm_new,
++ .pcm_free = imx_hdmi_dma_pcm_free,
++};
++
++static int imx_soc_platform_probe(struct platform_device *pdev)
++{
++ struct imx_hdmi *hdmi_drvdata = platform_get_drvdata(pdev);
++ struct hdmi_dma_priv *priv;
++ int ret = 0;
++
++ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
++ if (!priv) {
++ dev_err(&pdev->dev, "Failed to alloc hdmi_dma\n");
++ return -ENOMEM;
++ }
++
++ priv->hdmi_sdma_t = dma_alloc_coherent(NULL,
++ sizeof(struct hdmi_sdma_script),
++ &priv->phy_hdmi_sdma_t, GFP_KERNEL);
++ if (!priv->hdmi_sdma_t) {
++ dev_err(&pdev->dev, "Failed to alloc hdmi_sdma_t\n");
++ return -ENOMEM;
++ }
++
++ priv->tx_active = false;
++ spin_lock_init(&priv->irq_lock);
++
++ priv->pdev = hdmi_drvdata->pdev;
++
++ hdmi_dma_init_iec_header();
++
++ dev_set_drvdata(&pdev->dev, priv);
++
++ switch (hdmi_readb(HDMI_REVISION_ID)) {
++ case 0x0a:
++ snd_imx_hardware.period_bytes_max = HDMI_DMA_PERIOD_BYTES / 4;
++ snd_imx_hardware.period_bytes_min = HDMI_DMA_PERIOD_BYTES / 4;
++ snd_imx_hardware.periods_max = HDMI_DMA_BUF_SIZE / (HDMI_DMA_PERIOD_BYTES / 2);
++ break;
++ default:
++ break;
++ }
++
++ ret = snd_soc_register_platform(&pdev->dev, &imx_hdmi_platform);
++ if (ret)
++ goto err_plat;
++
++ return 0;
++
++err_plat:
++ dma_free_coherent(NULL, sizeof(struct hdmi_sdma_script),
++ priv->hdmi_sdma_t, priv->phy_hdmi_sdma_t);
++
++ return ret;
++}
++
++static int imx_soc_platform_remove(struct platform_device *pdev)
++{
++ struct hdmi_dma_priv *priv = dev_get_drvdata(&pdev->dev);
++
++ dma_free_coherent(NULL, sizeof(struct hdmi_sdma_script),
++ priv->hdmi_sdma_t, priv->phy_hdmi_sdma_t);
++
++ snd_soc_unregister_platform(&pdev->dev);
++
++ return 0;
++}
++
++static struct platform_driver imx_hdmi_dma_driver = {
++ .driver = {
++ .name = "imx-hdmi-audio",
++ .owner = THIS_MODULE,
++ },
++ .probe = imx_soc_platform_probe,
++ .remove = imx_soc_platform_remove,
++};
++
++module_platform_driver(imx_hdmi_dma_driver);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("i.MX HDMI audio DMA");
++MODULE_LICENSE("GPL");
+diff -Nur linux-4.1.3/sound/soc/fsl/imx-hdmi.h linux-xbian-imx6/sound/soc/fsl/imx-hdmi.h
+--- linux-4.1.3/sound/soc/fsl/imx-hdmi.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-xbian-imx6/sound/soc/fsl/imx-hdmi.h 2015-07-27 23:13:11.153188979 +0200
+@@ -0,0 +1,106 @@
++/*
++ * Copyright (C) 2011-2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++#ifndef __IMX_HDMI_H
++#define __IMX_HDMI_H
++
++struct imx_hdmi_sdma_params {
++ dma_addr_t phyaddr;
++ u32 buffer_num;
++ int dma;
++};
++
++struct imx_hdmi {
++ struct snd_soc_dai_driver cpu_dai_drv;
++ struct platform_device *codec_dev;
++ struct platform_device *dma_dev;
++ struct platform_device *pdev;
++ struct clk *isfr_clk;
++ struct clk *iahb_clk;
++ struct clk *mipi_core_clk;
++};
++
++#define HDMI_MAX_RATES 7
++#define HDMI_MAX_SAMPLE_SIZE 3
++#define HDMI_MAX_CHANNEL_CONSTRAINTS 4
++
++#define MXC_HDMI_RATES_PLAYBACK \
++ (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | \
++ SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | \
++ SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000)
++
++#define MXC_HDMI_FORMATS_PLAYBACK \
++ (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
++
++union hdmi_audio_header_t {
++ uint64_t U;
++ struct {
++ unsigned consumer:1;
++ unsigned linear_pcm:1;
++ unsigned copyright:1;
++ unsigned pre_emphasis:3;
++ unsigned mode:2;
++
++ unsigned category_code:8;
++
++ unsigned source:4;
++ unsigned channel:4;
++
++ unsigned sample_freq:4;
++ unsigned clock_acc:2;
++ unsigned reserved0:2;
++
++ unsigned word_length:4;
++ unsigned org_sample_freq:4;
++
++ unsigned cgms_a:2;
++ unsigned reserved1:6;
++
++ unsigned reserved2:8;
++
++ unsigned reserved3:8;
++ } B;
++ unsigned char status[8];
++};
++
++union hdmi_audio_dma_data_t {
++ uint32_t U;
++ struct {
++ unsigned data:24;
++ unsigned v:1;
++ unsigned u:1;
++ unsigned c:1;
++ unsigned p:1;
++ unsigned b:1;
++ unsigned reserved:3;
++ } B;
++};
++
++extern union hdmi_audio_header_t iec_header;
++
++#define hdmi_audio_writeb(reg, bit, val) \
++ do { \
++ hdmi_mask_writeb(val, HDMI_ ## reg, \
++ HDMI_ ## reg ## _ ## bit ## _OFFSET, \
++ HDMI_ ## reg ## _ ## bit ## _MASK); \
++ pr_debug("Set reg: HDMI_" #reg " (0x%x) "\
++ "bit: HDMI_" #reg "_" #bit " (%d) to val: %x\n", \
++ HDMI_ ## reg, HDMI_ ## reg ## _ ## bit ## _OFFSET, val); \
++ } while (0)
++
++#endif /* __IMX_HDMI_H */
+diff -Nur linux-4.1.3/sound/soc/fsl/imx-pcm-dma.c linux-xbian-imx6/sound/soc/fsl/imx-pcm-dma.c
+--- linux-4.1.3/sound/soc/fsl/imx-pcm-dma.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/sound/soc/fsl/imx-pcm-dma.c 2015-07-27 23:13:11.153188979 +0200
+@@ -43,7 +43,7 @@
+ .buffer_bytes_max = IMX_SSI_DMABUF_SIZE,
+ .period_bytes_min = 128,
+ .period_bytes_max = 65535, /* Limited by SDMA engine */
+- .periods_min = 2,
++ .periods_min = 4,
+ .periods_max = 255,
+ .fifo_size = 0,
+ };
+@@ -55,10 +55,27 @@
+ .prealloc_buffer_size = IMX_SSI_DMABUF_SIZE,
+ };
+
+-int imx_pcm_dma_init(struct platform_device *pdev)
++int imx_pcm_dma_init(struct platform_device *pdev, size_t size)
+ {
++ struct snd_dmaengine_pcm_config *config;
++ struct snd_pcm_hardware *pcm_hardware;
++
++ config = devm_kzalloc(&pdev->dev,
++ sizeof(struct snd_dmaengine_pcm_config), GFP_KERNEL);
++ *config = imx_dmaengine_pcm_config;
++ if (size)
++ config->prealloc_buffer_size = size;
++
++ pcm_hardware = devm_kzalloc(&pdev->dev,
++ sizeof(struct snd_pcm_hardware), GFP_KERNEL);
++ *pcm_hardware = imx_pcm_hardware;
++ if (size)
++ pcm_hardware->buffer_bytes_max = size;
++
++ config->pcm_hardware = pcm_hardware;
++
+ return devm_snd_dmaengine_pcm_register(&pdev->dev,
+- &imx_dmaengine_pcm_config,
++ config,
+ SND_DMAENGINE_PCM_FLAG_COMPAT);
+ }
+ EXPORT_SYMBOL_GPL(imx_pcm_dma_init);
+diff -Nur linux-4.1.3/sound/soc/fsl/imx-pcm.h linux-xbian-imx6/sound/soc/fsl/imx-pcm.h
+--- linux-4.1.3/sound/soc/fsl/imx-pcm.h 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/sound/soc/fsl/imx-pcm.h 2015-07-27 23:13:11.153188979 +0200
+@@ -19,6 +19,10 @@
+ * Do not change this as the FIQ handler depends on this size
+ */
+ #define IMX_SSI_DMABUF_SIZE (64 * 1024)
++#define IMX_SAI_DMABUF_SIZE (64 * 1024)
++#define IMX_SPDIF_DMABUF_SIZE (64 * 1024)
++#define IMX_ESAI_DMABUF_SIZE (256 * 1024)
++#define IMX_ASRC_DMABUF_SIZE (256 * 1024)
+
+ static inline void
+ imx_pcm_dma_params_init_data(struct imx_dma_data *dma_data,
+@@ -39,9 +43,9 @@
+ };
+
+ #if IS_ENABLED(CONFIG_SND_SOC_IMX_PCM_DMA)
+-int imx_pcm_dma_init(struct platform_device *pdev);
++int imx_pcm_dma_init(struct platform_device *pdev, size_t size);
+ #else
+-static inline int imx_pcm_dma_init(struct platform_device *pdev)
++static inline int imx_pcm_dma_init(struct platform_device *pdev, size_t size)
+ {
+ return -ENODEV;
+ }
+diff -Nur linux-4.1.3/sound/soc/fsl/imx-sgtl5000.c linux-xbian-imx6/sound/soc/fsl/imx-sgtl5000.c
+--- linux-4.1.3/sound/soc/fsl/imx-sgtl5000.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/sound/soc/fsl/imx-sgtl5000.c 2015-07-27 23:13:11.153188979 +0200
+@@ -175,8 +175,10 @@
+ fail:
+ if (data && !IS_ERR(data->codec_clk))
+ clk_put(data->codec_clk);
+- of_node_put(ssi_np);
+- of_node_put(codec_np);
++ if (ssi_np)
++ of_node_put(ssi_np);
++ if (codec_np)
++ of_node_put(codec_np);
+
+ return ret;
+ }
+@@ -200,6 +202,7 @@
+ static struct platform_driver imx_sgtl5000_driver = {
+ .driver = {
+ .name = "imx-sgtl5000",
++ .owner = THIS_MODULE,
+ .pm = &snd_soc_pm_ops,
+ .of_match_table = imx_sgtl5000_dt_ids,
+ },
+diff -Nur linux-4.1.3/sound/soc/fsl/imx-spdif.c linux-xbian-imx6/sound/soc/fsl/imx-spdif.c
+--- linux-4.1.3/sound/soc/fsl/imx-spdif.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/sound/soc/fsl/imx-spdif.c 2015-07-27 23:13:11.153188979 +0200
+@@ -66,16 +66,18 @@
+ if (ret)
+ goto end;
+
++ platform_set_drvdata(pdev, &data->card);
++ snd_soc_card_set_drvdata(&data->card, data);
++
+ ret = devm_snd_soc_register_card(&pdev->dev, &data->card);
+ if (ret) {
+ dev_err(&pdev->dev, "snd_soc_register_card failed: %d\n", ret);
+ goto end;
+ }
+
+- platform_set_drvdata(pdev, data);
+-
+ end:
+- of_node_put(spdif_np);
++ if (spdif_np)
++ of_node_put(spdif_np);
+
+ return ret;
+ }
+@@ -89,6 +91,8 @@
+ static struct platform_driver imx_spdif_driver = {
+ .driver = {
+ .name = "imx-spdif",
++ .owner = THIS_MODULE,
++ .pm = &snd_soc_pm_ops,
+ .of_match_table = imx_spdif_dt_ids,
+ },
+ .probe = imx_spdif_audio_probe,
+diff -Nur linux-4.1.3/sound/soc/fsl/imx-ssi.c linux-xbian-imx6/sound/soc/fsl/imx-ssi.c
+--- linux-4.1.3/sound/soc/fsl/imx-ssi.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/sound/soc/fsl/imx-ssi.c 2015-07-27 23:13:11.153188979 +0200
+@@ -603,7 +603,7 @@
+ ssi->fiq_params.dma_params_tx = &ssi->dma_params_tx;
+
+ ssi->fiq_init = imx_pcm_fiq_init(pdev, &ssi->fiq_params);
+- ssi->dma_init = imx_pcm_dma_init(pdev);
++ ssi->dma_init = imx_pcm_dma_init(pdev, IMX_SSI_DMABUF_SIZE);
+
+ if (ssi->fiq_init && ssi->dma_init) {
+ ret = ssi->fiq_init;
+diff -Nur linux-4.1.3/sound/soc/fsl/Kconfig linux-xbian-imx6/sound/soc/fsl/Kconfig
+--- linux-4.1.3/sound/soc/fsl/Kconfig 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/sound/soc/fsl/Kconfig 2015-07-27 23:13:11.149203200 +0200
+@@ -55,6 +55,9 @@
+ This option is only useful for out-of-tree drivers since
+ in-tree drivers select it automatically.
+
++config SND_SOC_FSL_HDMI
++ tristate
++
+ config SND_SOC_FSL_UTILS
+ tristate
+
+@@ -62,6 +65,11 @@
+ tristate
+ select SND_SOC_GENERIC_DMAENGINE_PCM
+
++config SND_SOC_IMX_HDMI_DMA
++ bool
++ select SND_SOC_GENERIC_DMAENGINE_PCM
++ select SND_SOC_IMX_PCM_DMA
++
+ config SND_SOC_IMX_AUDMUX
+ tristate "Digital Audio Mux module support"
+ help
+@@ -235,7 +243,9 @@
+ select SND_SOC_WM8962
+ select SND_SOC_IMX_PCM_DMA
+ select SND_SOC_IMX_AUDMUX
++ select SND_SOC_FSL_SAI
+ select SND_SOC_FSL_SSI
++ select SND_SOC_FSL_UTILS
+ help
+ Say Y if you want to add support for SoC audio on an i.MX board with
+ a wm8962 codec.
+@@ -258,7 +268,9 @@
+ select SND_SOC_SGTL5000
+ select SND_SOC_IMX_PCM_DMA
+ select SND_SOC_IMX_AUDMUX
++ select SND_SOC_FSL_SAI
+ select SND_SOC_FSL_SSI
++ select SND_SOC_FSL_UTILS
+ help
+ Say Y if you want to add support for SoC audio on an i.MX board with
+ a sgtl5000 codec.
+@@ -280,6 +292,17 @@
+ select SND_SOC_MC13783
+ select SND_SOC_IMX_PCM_DMA
+
++config SND_SOC_IMX_HDMI
++ tristate "SoC Audio support for i.MX boards with HDMI port"
++ depends on MFD_MXC_HDMI
++ select SND_SOC_IMX_HDMI_DMA
++ select SND_SOC_FSL_HDMI
++ select SND_SOC_OMAP_HDMI_CODEC
++ help
++ SoC Audio support for i.MX boards with HDMI audio
++ Say Y if you want to add support for SoC audio on an i.MX board with
++ IMX HDMI.
++
+ config SND_SOC_FSL_ASOC_CARD
+ tristate "Generic ASoC Sound Card with ASRC support"
+ depends on OF && I2C
+diff -Nur linux-4.1.3/sound/soc/fsl/Makefile linux-xbian-imx6/sound/soc/fsl/Makefile
+--- linux-4.1.3/sound/soc/fsl/Makefile 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/sound/soc/fsl/Makefile 2015-07-27 23:13:11.149203200 +0200
+@@ -15,7 +15,8 @@
+ snd-soc-fsl-asrc-objs := fsl_asrc.o fsl_asrc_dma.o
+ snd-soc-fsl-sai-objs := fsl_sai.o
+ snd-soc-fsl-ssi-y := fsl_ssi.o
+-snd-soc-fsl-ssi-$(CONFIG_DEBUG_FS) += fsl_ssi_dbg.o
++##snd-soc-fsl-ssi-$(CONFIG_DEBUG_FS) += fsl_ssi_dbg.o
++snd-soc-fsl-hdmi-objs := fsl_hdmi.o
+ snd-soc-fsl-spdif-objs := fsl_spdif.o
+ snd-soc-fsl-esai-objs := fsl_esai.o
+ snd-soc-fsl-utils-objs := fsl_utils.o
+@@ -26,6 +27,7 @@
+ obj-$(CONFIG_SND_SOC_FSL_SSI) += snd-soc-fsl-ssi.o
+ obj-$(CONFIG_SND_SOC_FSL_SPDIF) += snd-soc-fsl-spdif.o
+ obj-$(CONFIG_SND_SOC_FSL_ESAI) += snd-soc-fsl-esai.o
++obj-$(CONFIG_SND_SOC_FSL_HDMI) += snd-soc-fsl-hdmi.o
+ obj-$(CONFIG_SND_SOC_FSL_UTILS) += snd-soc-fsl-utils.o
+ obj-$(CONFIG_SND_SOC_POWERPC_DMA) += snd-soc-fsl-dma.o
+
+@@ -46,7 +48,7 @@
+
+ obj-$(CONFIG_SND_SOC_IMX_PCM_FIQ) += imx-pcm-fiq.o
+ obj-$(CONFIG_SND_SOC_IMX_PCM_DMA) += imx-pcm-dma.o
+-
++obj-$(CONFIG_SND_SOC_IMX_HDMI_DMA) += imx-hdmi-dma.o hdmi_pcm.o
+ # i.MX Machine Support
+ snd-soc-eukrea-tlv320-objs := eukrea-tlv320.o
+ snd-soc-phycore-ac97-objs := phycore-ac97.o
+@@ -57,6 +59,7 @@
+ snd-soc-imx-wm8962-objs := imx-wm8962.o
+ snd-soc-imx-spdif-objs := imx-spdif.o
+ snd-soc-imx-mc13783-objs := imx-mc13783.o
++snd-soc-imx-hdmi-objs := imx-hdmi.o
+
+ obj-$(CONFIG_SND_SOC_EUKREA_TLV320) += snd-soc-eukrea-tlv320.o
+ obj-$(CONFIG_SND_SOC_PHYCORE_AC97) += snd-soc-phycore-ac97.o
+@@ -67,3 +70,6 @@
+ obj-$(CONFIG_SND_SOC_IMX_WM8962) += snd-soc-imx-wm8962.o
+ obj-$(CONFIG_SND_SOC_IMX_SPDIF) += snd-soc-imx-spdif.o
+ obj-$(CONFIG_SND_SOC_IMX_MC13783) += snd-soc-imx-mc13783.o
++obj-$(CONFIG_SND_SOC_IMX_HDMI) += snd-soc-imx-hdmi.o
++
++AFLAGS_hdmi_pcm.o := -march=armv7-a -mtune=cortex-a9 -mfpu=neon -mfloat-abi=softfp
+diff -Nur linux-4.1.3/sound/soc/soc-io.c linux-xbian-imx6/sound/soc/soc-io.c
+--- linux-4.1.3/sound/soc/soc-io.c 2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/sound/soc/soc-io.c 2015-07-27 23:13:11.344506380 +0200
+@@ -17,6 +17,8 @@
+ #include <linux/export.h>
+ #include <sound/soc.h>
+
++#include <trace/events/asoc.h>
++
+ /**
+ * snd_soc_component_read() - Read register value
+ * @component: Component to read from
+@@ -271,3 +273,233 @@
+ return snd_soc_component_write(&platform->component, reg, val);
+ }
+ EXPORT_SYMBOL_GPL(snd_soc_platform_write);
++
++#ifdef CONFIG_REGMAP
++static bool snd_soc_set_cache_val(void *base, unsigned int idx,
++ unsigned int val, unsigned int word_size)
++{
++ switch (word_size) {
++ case 1: {
++ u8 *cache = base;
++ if (cache[idx] == val)
++ return true;
++ cache[idx] = val;
++ break;
++ }
++ case 2: {
++ u16 *cache = base;
++ if (cache[idx] == val)
++ return true;
++ cache[idx] = val;
++ break;
++ }
++ default:
++ WARN(1, "Invalid word_size %d\n", word_size);
++ break;
++ }
++ return false;
++}
++
++static unsigned int snd_soc_get_cache_val(const void *base, unsigned int idx,
++ unsigned int word_size)
++{
++ if (!base)
++ return -1;
++
++ switch (word_size) {
++ case 1: {
++ const u8 *cache = base;
++ return cache[idx];
++ }
++ case 2: {
++ const u16 *cache = base;
++ return cache[idx];
++ }
++ default:
++ WARN(1, "Invalid word_size %d\n", word_size);
++ break;
++ }
++ /* unreachable */
++ return -1;
++}
++
++/**
++ * snd_soc_cache_read: Fetch the value of a given register from the cache.
++ *
++ * @codec: CODEC to configure.
++ * @reg: The register index.
++ * @value: The value to be returned.
++ */
++int snd_soc_cache_read(struct snd_soc_codec *codec,
++ unsigned int reg, unsigned int *value)
++{
++ if (!value)
++ return -EINVAL;
++
++ mutex_lock(&codec->cache_rw_mutex);
++ *value = snd_soc_get_cache_val(codec->reg_cache, reg,
++ codec->driver->reg_word_size);
++ mutex_unlock(&codec->cache_rw_mutex);
++
++ return 0;
++}
++
++/**
++ * snd_soc_cache_write: Set the value of a given register in the cache.
++ *
++ * @codec: CODEC to configure.
++ * @reg: The register index.
++ * @value: The new register value.
++ */
++int snd_soc_cache_write(struct snd_soc_codec *codec,
++ unsigned int reg, unsigned int value)
++{
++ mutex_lock(&codec->cache_rw_mutex);
++ snd_soc_set_cache_val(codec->reg_cache, reg, value,
++ codec->driver->reg_word_size);
++ mutex_unlock(&codec->cache_rw_mutex);
++
++ return 0;
++}
++
++/**
++ * snd_soc_codec_volatile_register: Report if a register is volatile.
++ *
++ * @codec: CODEC to query.
++ * @reg: Register to query.
++ *
++ * Boolean function indiciating if a CODEC register is volatile.
++ */
++int snd_soc_codec_volatile_register(struct snd_soc_codec *codec,
++ unsigned int reg)
++{
++ if (codec->volatile_register)
++ return codec->volatile_register(codec, reg);
++ else
++ return 0;
++}
++
++static int hw_write(struct snd_soc_codec *codec, unsigned int reg,
++ unsigned int value)
++{
++ int ret;
++
++ if (!snd_soc_codec_volatile_register(codec, reg) &&
++ reg < codec->driver->reg_cache_size &&
++ !codec->cache_bypass) {
++ ret = snd_soc_cache_write(codec, reg, value);
++ if (ret < 0)
++ return -1;
++ }
++
++ if (codec->cache_only) {
++ codec->cache_sync = 1;
++ return 0;
++ }
++
++ return regmap_write(codec->control_data, reg, value);
++}
++
++static unsigned int hw_read(struct snd_soc_codec *codec, unsigned int reg)
++{
++ int ret;
++ unsigned int val;
++
++ if (reg >= codec->driver->reg_cache_size ||
++ snd_soc_codec_volatile_register(codec, reg) ||
++ codec->cache_bypass) {
++ if (codec->cache_only)
++ return -1;
++
++ ret = regmap_read(codec->control_data, reg, &val);
++ if (ret == 0)
++ return val;
++ else
++ return -1;
++ }
++
++ ret = snd_soc_cache_read(codec, reg, &val);
++ if (ret < 0)
++ return -1;
++ return val;
++}
++
++/**
++ * snd_soc_codec_set_cache_io: Set up standard I/O functions.
++ *
++ * @codec: CODEC to configure.
++ * @addr_bits: Number of bits of register address data.
++ * @data_bits: Number of bits of data per register.
++ * @control: Control bus used.
++ *
++ * Register formats are frequently shared between many I2C and SPI
++ * devices. In order to promote code reuse the ASoC core provides
++ * some standard implementations of CODEC read and write operations
++ * which can be set up using this function.
++ *
++ * The caller is responsible for allocating and initialising the
++ * actual cache.
++ *
++ * Note that at present this code cannot be used by CODECs with
++ * volatile registers.
++ */
++int snd_soc_codec_set_cache_io(struct snd_soc_codec *codec,
++ int addr_bits, int data_bits,
++ enum snd_soc_control_type control)
++{
++ struct regmap_config config;
++ int ret;
++
++ memset(&config, 0, sizeof(config));
++ codec->write = hw_write;
++ codec->read = hw_read;
++
++ config.reg_bits = addr_bits;
++ config.val_bits = data_bits;
++
++ switch (control) {
++#if IS_ENABLED(CONFIG_REGMAP_I2C)
++ case SND_SOC_I2C:
++ codec->control_data = regmap_init_i2c(to_i2c_client(codec->dev),
++ &config);
++ break;
++#endif
++
++#if IS_ENABLED(CONFIG_REGMAP_SPI)
++ case SND_SOC_SPI:
++ codec->control_data = regmap_init_spi(to_spi_device(codec->dev),
++ &config);
++ break;
++#endif
++
++ case SND_SOC_REGMAP:
++ /* Device has made its own regmap arrangements */
++ codec->using_regmap = true;
++ if (!codec->control_data)
++ codec->control_data = dev_get_regmap(codec->dev, NULL);
++
++ if (codec->control_data) {
++ ret = regmap_get_val_bytes(codec->control_data);
++ /* Errors are legitimate for non-integer byte
++ * multiples */
++ if (ret > 0)
++ codec->val_bytes = ret;
++ }
++ break;
++
++ default:
++ return -EINVAL;
++ }
++
++ return PTR_ERR_OR_ZERO(codec->control_data);
++}
++EXPORT_SYMBOL_GPL(snd_soc_codec_set_cache_io);
++#else
++int snd_soc_codec_set_cache_io(struct snd_soc_codec *codec,
++ int addr_bits, int data_bits,
++ enum snd_soc_control_type control)
++{
++ return -ENOTSUPP;
++}
++EXPORT_SYMBOL_GPL(snd_soc_codec_set_cache_io);
++#endif
diff --git a/target/config/Config.in.kernelversion.choice b/target/config/Config.in.kernelversion.choice
index e4836562a..01bec6c8e 100644
--- a/target/config/Config.in.kernelversion.choice
+++ b/target/config/Config.in.kernelversion.choice
@@ -13,9 +13,8 @@ config ADK_KERNEL_VERSION_GIT
depends on !ADK_TARGET_SYSTEM_RASPBERRY_PI2 || ADK_EXPERIMENTAL
depends on !ADK_TARGET_SYSTEM_SOLIDRUN_IMX6 || ADK_EXPERIMENTAL
-config ADK_KERNEL_VERSION_4_1_2
- bool "4.1.2"
- depends on !ADK_TARGET_SYSTEM_SOLIDRUN_IMX6 || ADK_EXPERIMENTAL
+config ADK_KERNEL_VERSION_4_1_3
+ bool "4.1.3"
depends on !ADK_TARGET_ARCH_H8300
depends on !ADK_TARGET_SYSTEM_KINETIS_K70
select ADK_KERNEL_VERSION_4_1
diff --git a/target/config/Config.in.kernelversion.default b/target/config/Config.in.kernelversion.default
index e350a73fc..b42fa3a76 100644
--- a/target/config/Config.in.kernelversion.default
+++ b/target/config/Config.in.kernelversion.default
@@ -30,7 +30,7 @@ config ADK_KERNEL_VERSION_2_6_32
config ADK_KERNEL_VERSION
string
- default "4.1.2" if ADK_KERNEL_VERSION_4_1_2
+ default "4.1.3" if ADK_KERNEL_VERSION_4_1_3
default "4.0.6" if ADK_KERNEL_VERSION_4_0_6
default "3.18.16" if ADK_KERNEL_VERSION_3_18_16
default "3.14.45" if ADK_KERNEL_VERSION_3_14_45
diff --git a/target/linux/config/Config.in.audio b/target/linux/config/Config.in.audio
index 1e08c94b5..54270c374 100644
--- a/target/linux/config/Config.in.audio
+++ b/target/linux/config/Config.in.audio
@@ -28,6 +28,9 @@ config ADK_KERNEL_SND_SOC_IMX_SGTL5000
config ADK_KERNEL_SND_SOC_IMX_PCM_DMA
bool
+config ADK_KERNEL_SND_SOC_HDMI_CODEC
+ bool
+
config ADK_KERNEL_SND_SOC_IMX_HDMI_DMA
bool
@@ -203,6 +206,7 @@ config ADK_KERNEL_SND_IMX_SOC
bool "IMX6 SoC sound chip"
select ADK_KERNEL_SND
select ADK_KERNEL_SND_SOC
+ select ADK_KERNEL_SND_SOC_HDMI_CODEC
select ADK_KERNEL_SND_SOC_IMX_PCM_DMA
select ADK_KERNEL_SND_SOC_IMX_HDMI_DMA
select ADK_KERNEL_SND_SOC_IMX_HDMI
@@ -212,7 +216,7 @@ config ADK_KERNEL_SND_IMX_SOC
select ADK_KERNEL_SND_SOC_FSL_SPDIF
select ADK_KERNEL_REGMAP_SPI
select ADK_KERNEL_REGMAP_I2C
- depends on ADK_TARGET_SYSTEM_SOLIDRUN_IMX6 && ADK_KERNEL_VERSION_3_14
+ depends on ADK_TARGET_SYSTEM_SOLIDRUN_IMX6
default y if ADK_TARGET_SYSTEM_SOLIDRUN_IMX6
default n
diff --git a/target/linux/config/Config.in.cpu b/target/linux/config/Config.in.cpu
index 797e1a60e..f0caaea9b 100644
--- a/target/linux/config/Config.in.cpu
+++ b/target/linux/config/Config.in.cpu
@@ -48,7 +48,6 @@ config ADK_KERNEL_ARM_IMX6Q_CPUFREQ
select ADK_KERNEL_REGULATOR_ANATOP
select ADK_KERNEL_REGULATOR_PFUZE100
depends on ADK_TARGET_SYSTEM_SOLIDRUN_IMX6
- depends on !ADK_KERNEL_VERSION_3_12
default y if ADK_TARGET_SYSTEM_SOLIDRUN_IMX6
default n
diff --git a/target/linux/config/Config.in.graphics b/target/linux/config/Config.in.graphics
index 4993dd57d..5e5aef2d9 100644
--- a/target/linux/config/Config.in.graphics
+++ b/target/linux/config/Config.in.graphics
@@ -244,7 +244,6 @@ config ADK_KERNEL_DRM_VIVANTE
select ADK_KERNEL_FB_MXC_EDID
select ADK_KERNEL_MXC_VPU
depends on ADK_TARGET_SYSTEM_SOLIDRUN_IMX6
- depends on ADK_KERNEL_VERSION_3_14
default y if ADK_TARGET_SYSTEM_SOLIDRUN_IMX6
default n
help
diff --git a/target/linux/config/Config.in.pm b/target/linux/config/Config.in.pm
index 0e418ce0c..e7c875047 100644
--- a/target/linux/config/Config.in.pm
+++ b/target/linux/config/Config.in.pm
@@ -1,34 +1,39 @@
+config ADK_KERNEL_PM
+ bool
+ default y if ADK_TARGET_SYSTEM_SOLIDRUN_IMX6
+
config ADK_KERNEL_PM_RUNTIME
- boolean
+ bool
default y if ADK_TARGET_SYSTEM_SOLIDRUN_IMX6
config ADK_KERNEL_ACPI
- boolean
+ bool
config ADK_KERNEL_ACPI_SYSFS_POWER
- boolean
+ bool
config ADK_KERNEL_ACPI_AC
- boolean
+ bool
config ADK_KERNEL_ACPI_BATTERY
- boolean
+ bool
config ADK_KERNEL_ACPI_BUTTON
- boolean
+ bool
config ADK_KERNEL_ACPI_FAN
- boolean
+ bool
config ADK_KERNEL_ACPI_DOCK
- boolean
+ bool
menu "Power Management support"
depends on ADK_TARGET_WITH_ACPI || ADK_TARGET_SYSTEM_LEMOTE_YEELONG
config ADK_HARDWARE_ACPI
prompt "Enable ACPI support"
- boolean
+ bool
+ select ADK_KERNEL_PM
select ADK_KERNEL_PM_RUNTIME
select ADK_KERNEL_ACPI
select ADK_KERNEL_ACPI_SYSFS_POWER
@@ -45,7 +50,8 @@ config ADK_HARDWARE_ACPI
config ADK_KERNEL_SUSPEND
prompt "Enable Suspend-to-RAM support"
- boolean
+ bool
+ select ADK_KERNEL_PM
select ADK_KERNEL_PM_RUNTIME
default y if ADK_TARGET_SYSTEM_IBM_X40
default y if ADK_TARGET_SYSTEM_LEMOTE_YEELONG
@@ -55,7 +61,8 @@ config ADK_KERNEL_SUSPEND
config ADK_KERNEL_HIBERNATION
prompt "Enable Suspend-to-Disk support"
- boolean
+ bool
+ select ADK_KERNEL_PM
select ADK_KERNEL_PM_RUNTIME
select ADK_KERNEL_SWAP
select BUSYBOX_SWAPONOFF
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-09 17:09:02 +0000